- {MinimumRequiredVersion: 4.26.0}
- arcturus
- gfx908
- [Device 7380, Device 7388, Device 738c, Device 7390]
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  AssignedDerivedParameters: true
  Batched: true
  ComplexConjugateA: false
  ComplexConjugateB: false
  ComputeDataType: 6
  ConvolutionConfig: []
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  DestDataType: 6
  HighPrecisionAccumulate: true
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  Index01A: 0
  Index01B: 1
  Index1: 1
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  IndexUnrollB: 0
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  IndicesFree: [0, 1]
  IndicesSummation: [3]
  MirrorDimsA: []
  MirrorDimsB: []
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  NumIndicesC: 3
  NumIndicesFree: 2
  NumIndicesLD: 4
  NumIndicesSummation: 1
  OperationType: GEMM
  SetConstStrideA: []
  SetConstStrideB: []
  SilentHighPrecisionAccumulate: false
  StridedBatched: false
  TLUA: false
  TLUB: false
  Tensor0: 0
  Tensor1: 1
  TileA: 0
  TileAwareSelection: false
  TileB: 1
  TotalIndices: 4
  TransposeA: true
  TransposeB: false
  UseBeta: true
  UseInitialStridesAB: false
  UseInitialStridesCD: false
  ZeroPadA: []
  ZeroPadB: []
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    AggressivePerfMode: 1
    AssertFree0ElementMultiple: 4
    AssertFree1ElementMultiple: 1
    AssertMinApproxSize: 3
    AssertSizeEqual: {}
    AssertStrideAEqual: {0: 1}
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    AssertStrideCEqual: {0: 1}
    AssertStrideDEqual: {0: 1}
    AssertSummationElementMultiple: 1
    AssignedDerivedParameters: true
    AssignedProblemIndependentDerivedParameters: true
    BufferLoad: true
    BufferStore: true
    CheckDimOverflow: 0
    CheckTensorDimAsserts: false
    CodeObjectVersion: V3
    DepthU: 32
    DepthULdsDivisor: 1
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    DirectToLdsA: false
    DirectToLdsB: false
    DisableAtomicFail: 0
    DisableKernelPieces: 0
    DisableVgprOverlapping: false
    EdgeType: ShiftPtr
    EnableMatrixInstruction: true
    ExpandPointerSwap: true
    FractionalLoad: 0
    GlobalLoadVectorWidthA: 4
    GlobalLoadVectorWidthB: 4
    GlobalRead2A: true
    GlobalRead2B: true
    GlobalReadCoalesceGroupA: true
    GlobalReadCoalesceGroupB: true
    GlobalReadCoalesceVectorA: true
    GlobalReadCoalesceVectorB: true
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    GlobalSplitUAlgorithm: MultipleBuffer
    GlobalSplitUSummationAssignmentRoundRobin: true
    GlobalSplitUWorkGroupMappingRoundRobin: false
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    GuaranteeNoPartialB: true
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    InnerUnroll: 1
    InterleaveAlpha: 0
    KernelLanguage: Assembly
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    LSCB: 32
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    LocalRead2B: true
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    LocalWriteUseSgprB: false
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    MacroTile1: 64
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    MatrixInstN: 32
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    NonTemporalB: 0
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    PrefetchLocalRead: true
    ProblemType:
      AllowNoFreeDims: false
      AssignedDerivedParameters: true
      Batched: true
      ComplexConjugateA: false
      ComplexConjugateB: false
      ComputeDataType: 6
      ConvolutionConfig: []
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      HighPrecisionAccumulate: true
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    SolutionNameMin: Cijk_Alik_Bljk_I8II_BH_GB_MT64x64x32_MI32x32x8x1_SN_1LDSB0_EPS1_GRVW4_LPA4_LPB4_OPLV0_PK0_PAP0_PGR1_PLR1_SU32_SUS256_SRVW0_TT1_32_WG64_4_1_WGM8
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    ProblemType:
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    SolutionNameMin: Cijk_Alik_Bljk_I8II_BH_GB_MT32x32x128_MI16x16x16x1_SN_1LDSB0_EPS0_GRVW16_LPA32_LPB32_OPLV0_PK0_PAP0_PGR2_PLR9_SU0_SUS128_SRVW0_TT1_16_WG32_8_1_WGM1
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    SolutionNameMin: Cijk_Alik_Bljk_I8II_BH_GB_MT64x128x64_MI32x32x8x1_SN_1LDSB0_EPS1_GRVW4_LPA16_LPB16_OPLV0_PK0_PAP0_PGR1_PLR9_SU0_SUS128_SRVW4_TT1_64_WG64_4_1_WGM1
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    SolutionNameMin: Cijk_Alik_Bljk_I8II_BH_GB_MT64x64x64_MI32x32x8x1_SN_1LDSB0_EPS0_GRVW16_LPA16_LPB16_OPLV0_PK0_PAP0_PGR2_PLR9_SU0_SUS128_SRVW4_TT1_32_WG64_4_1_WGM1
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    SolutionNameMin: Cijk_Alik_Bljk_I8II_BH_GB_MT32x32x128_MI16x16x16x1_SN_1LDSB1_EPS1_GRVW4_LPA32_LPB32_OPLV0_PK0_PAP0_PGR1_PLR9_SU0_SUS128_SRVW0_TT1_16_WG32_8_1_WGM1
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    SolutionNameMin: Cijk_Alik_Bljk_I8II_BH_GB_MT64x64x64_MI32x32x8x1_SN_1LDSB1_EPS0_GRVW4_LPA16_LPB16_OPLV0_PK0_PAP0_PGR2_PLR9_SU0_SUS128_SRVW0_TT1_32_WG64_4_1_WGM1
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    SolutionNameMin: Cijk_Alik_Bljk_I8II_BH_GB_MT32x32x128_MI16x16x16x1_SN_1LDSB1_EPS0_GRVW8_LPA32_LPB32_OPLV0_PK0_PAP0_PGR2_PLR9_SU0_SUS128_SRVW0_TT1_16_WG32_8_1_WGM1
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    SolutionNameMin: Cijk_Alik_Bljk_I8II_BH_GB_MT64x32x128_MI16x16x16x1_SN_1LDSB1_EPS1_GRVW16_LPA32_LPB32_OPLV0_PK0_PAP0_PGR1_PLR9_SU0_SUS128_SRVW4_TT2_16_WG32_8_1_WGM1
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    SolutionNameMin: Cijk_Alik_Bljk_I8II_BH_GB_MT64x64x128_MI32x32x8x1_SN_1LDSB1_EPS1_GRVW16_LPA16_LPB16_OPLV0_PK0_PAP0_PGR1_PLR17_SU0_SUS128_SRVW4_TT1_32_WG64_4_1_WGM1
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    SolutionNameMin: Cijk_Alik_Bljk_I8II_BH_GB_MT64x64x128_MI32x32x8x1_SN_1LDSB1_EPS0_GRVW16_LPA16_LPB16_OPLV0_PK0_PAP0_PGR2_PLR17_SU0_SUS128_SRVW4_TT1_32_WG64_4_1_WGM1
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    SolutionNameMin: Cijk_Alik_Bljk_I8II_BH_GB_MT64x128x64_MI32x32x8x1_SN_1LDSB1_EPS0_GRVW4_LPA16_LPB16_OPLV0_PK0_PAP0_PGR2_PLR9_SU0_SUS256_SRVW0_TT1_64_WG64_4_1_WGM1
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    SolutionNameMin: Cijk_Alik_Bljk_I8II_BH_GB_MT32x32x128_MI16x16x16x1_SN_1LDSB1_EPS0_GRVW8_LPA32_LPB32_OPLV0_PK0_PAP0_PGR2_PLR9_SU0_SUS256_SRVW0_TT1_16_WG32_8_1_WGM1
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    SolutionNameMin: Cijk_Alik_Bljk_I8II_BH_GB_MT32x32x128_MI16x16x16x1_SN_1LDSB1_EPS0_GRVW16_LPA32_LPB32_OPLV0_PK0_PAP0_PGR2_PLR9_SU0_SUS256_SRVW4_TT1_16_WG32_8_1_WGM1
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    SolutionNameMin: Cijk_Alik_Bljk_I8II_BH_GB_MT64x64x128_MI32x32x8x1_SN_1LDSB1_EPS1_GRVW16_LPA16_LPB16_OPLV0_PK0_PAP0_PGR1_PLR17_SU0_SUS256_SRVW4_TT1_32_WG64_4_1_WGM1
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    SolutionNameMin: Cijk_Alik_Bljk_I8II_BH_GB_MT64x64x128_MI32x32x8x1_SN_1LDSB1_EPS1_GRVW8_LPA16_LPB16_OPLV0_PK0_PAP0_PGR1_PLR17_SU32_SUS128_SRVW4_TT1_32_WG64_4_1_WGM1
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    SolutionNameMin: Cijk_Alik_Bljk_I8II_BH_GB_MT64x64x128_MI32x32x8x1_SN_1LDSB1_EPS0_GRVW8_LPA16_LPB16_OPLV0_PK0_PAP0_PGR2_PLR17_SU32_SUS128_SRVW4_TT1_32_WG64_4_1_WGM1
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    SolutionNameMin: Cijk_Alik_Bljk_I8II_BH_GB_MT64x64x128_MI32x32x8x1_SN_1LDSB1_EPS0_GRVW16_LPA16_LPB16_OPLV0_PK0_PAP0_PGR2_PLR17_SU32_SUS256_SRVW4_TT1_32_WG64_4_1_WGM1
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    SolutionNameMin: Cijk_Alik_Bljk_I8II_BH_GB_MT64x64x64_MI32x32x8x1_SN_1LDSB0_EPS1_GRVW8_LPA16_LPB16_OPLV0_PK0_PAP0_PGR1_PLR9_SU0_SUS128_SRVW0_TT1_32_WG64_4_1_WGM2
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    SolutionNameMin: Cijk_Alik_Bljk_I8II_BH_GB_MT32x32x128_MI16x16x16x1_SN_1LDSB0_EPS0_GRVW16_LPA32_LPB32_OPLV0_PK0_PAP0_PGR2_PLR9_SU0_SUS128_SRVW0_TT1_16_WG32_8_1_WGM2
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    SolutionNameMin: Cijk_Alik_Bljk_I8II_BH_GB_MT32x32x128_MI16x16x16x1_SN_1LDSB1_EPS1_GRVW16_LPA32_LPB32_OPLV0_PK0_PAP0_PGR1_PLR9_SU0_SUS128_SRVW0_TT1_16_WG32_8_1_WGM2
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    SolutionNameMin: Cijk_Alik_Bljk_I8II_BH_GB_MT64x32x128_MI16x16x16x1_SN_1LDSB1_EPS1_GRVW16_LPA32_LPB32_OPLV0_PK0_PAP0_PGR1_PLR9_SU0_SUS128_SRVW0_TT2_16_WG32_8_1_WGM2
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    SolutionNameMin: Cijk_Alik_Bljk_I8II_BH_GB_MT64x64x64_MI32x32x8x1_SN_1LDSB1_EPS0_GRVW8_LPA16_LPB16_OPLV0_PK0_PAP0_PGR2_PLR9_SU0_SUS128_SRVW0_TT1_32_WG64_4_1_WGM2
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    SolutionNameMin: Cijk_Alik_Bljk_I8II_BH_GB_MT64x64x128_MI32x32x8x1_SN_1LDSB1_EPS0_GRVW16_LPA16_LPB16_OPLV0_PK0_PAP0_PGR2_PLR17_SU0_SUS128_SRVW4_TT1_32_WG64_4_1_WGM2
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    SolutionNameMin: Cijk_Alik_Bljk_I8II_BH_GB_MT64x64x64_MI32x32x8x1_SN_1LDSB1_EPS1_GRVW4_LPA16_LPB16_OPLV0_PK0_PAP0_PGR1_PLR9_SU0_SUS256_SRVW0_TT1_32_WG64_4_1_WGM2
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    SolutionNameMin: Cijk_Alik_Bljk_I8II_BH_GB_MT64x128x128_MI32x32x8x1_SN_1LDSB1_EPS1_GRVW16_LPA16_LPB16_OPLV0_PK0_PAP0_PGR1_PLR17_SU32_SUS128_SRVW4_TT1_64_WG64_4_1_WGM2
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    SolutionNameMin: Cijk_Alik_Bljk_I8II_BH_GB_MT64x128x64_MI32x32x8x1_SN_1LDSB0_EPS0_GRVW16_LPA16_LPB16_OPLV0_PK0_PAP0_PGR2_PLR9_SU32_SUS256_SRVW4_TT1_64_WG64_4_1_WGM2
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    SolutionNameMin: Cijk_Alik_Bljk_I8II_BH_GB_MT64x128x64_MI32x32x8x1_SN_1LDSB0_EPS1_GRVW16_LPA16_LPB16_OPLV0_PK0_PAP0_PGR1_PLR9_SU0_SUS128_SRVW4_TT1_64_WG64_4_1_WGM15
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    SolutionNameMin: Cijk_Alik_Bljk_I8II_BH_GB_MT32x32x128_MI16x16x16x1_SN_1LDSB1_EPS1_GRVW16_LPA32_LPB32_OPLV0_PK0_PAP0_PGR1_PLR9_SU0_SUS128_SRVW0_TT1_16_WG32_8_1_WGM15
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    SolutionNameMin: Cijk_Alik_Bljk_I8II_BH_GB_MT32x64x128_MI16x16x16x1_SN_1LDSB1_EPS1_GRVW16_LPA32_LPB32_OPLV0_PK0_PAP0_PGR1_PLR9_SU0_SUS128_SRVW4_TT1_32_WG32_8_1_WGM15
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    SolutionNameMin: Cijk_Alik_Bljk_I8II_BH_GB_MT64x64x128_MI32x32x8x1_SN_1LDSB1_EPS1_GRVW16_LPA16_LPB16_OPLV0_PK0_PAP0_PGR1_PLR17_SU0_SUS128_SRVW4_TT1_32_WG64_4_1_WGM15
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    SolutionNameMin: Cijk_Alik_Bljk_I8II_BH_GB_MT32x32x128_MI16x16x16x1_SN_1LDSB0_EPS0_GRVW16_LPA32_LPB32_OPLV0_PK0_PAP0_PGR2_PLR9_SU0_SUS256_SRVW4_TT1_16_WG32_8_1_WGM15
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    SolutionNameMin: Cijk_Alik_Bljk_I8II_BH_GB_MT32x32x128_MI16x16x16x1_SN_1LDSB1_EPS1_GRVW16_LPA32_LPB32_OPLV0_PK0_PAP0_PGR1_PLR9_SU0_SUS256_SRVW0_TT1_16_WG32_8_1_WGM15
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    SolutionNameMin: Cijk_Alik_Bljk_I8II_BH_GB_MT32x64x128_MI16x16x16x1_SN_1LDSB1_EPS0_GRVW16_LPA32_LPB32_OPLV0_PK0_PAP0_PGR2_PLR9_SU0_SUS256_SRVW0_TT1_32_WG32_8_1_WGM15
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    SolutionNameMin: Cijk_Alik_Bljk_I8II_BH_GB_MT64x64x128_MI32x32x8x1_SN_1LDSB1_EPS1_GRVW16_LPA16_LPB16_OPLV0_PK0_PAP0_PGR1_PLR17_SU0_SUS256_SRVW4_TT1_32_WG64_4_1_WGM15
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    SolutionNameMin: Cijk_Alik_Bljk_I8II_BH_GB_MT64x64x128_MI32x32x8x1_SN_1LDSB1_EPS1_GRVW4_LPA16_LPB16_OPLV0_PK0_PAP0_PGR1_PLR17_SU32_SUS128_SRVW4_TT1_32_WG64_4_1_WGM15
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    SolutionNameMin: Cijk_Alik_Bljk_I8II_BH_GB_MT64x64x128_MI32x32x8x1_SN_1LDSB1_EPS1_GRVW16_LPA16_LPB16_OPLV0_PK0_PAP0_PGR1_PLR17_SU32_SUS128_SRVW4_TT1_32_WG64_4_1_WGM15
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    SolutionNameMin: Cijk_Alik_Bljk_I8II_BH_GB_MT64x64x128_MI32x32x8x1_SN_1LDSB1_EPS0_GRVW16_LPA16_LPB16_OPLV0_PK0_PAP0_PGR2_PLR17_SU32_SUS128_SRVW4_TT1_32_WG64_4_1_WGM15
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    ScheduleLocalWrite: 1
    SolutionIndex: 139
    SolutionNameMin: Cijk_Alik_Bljk_I8II_BH_GB_MT64x64x128_MI32x32x8x1_SN_1LDSB1_EPS1_GRVW16_LPA16_LPB16_OPLV0_PK0_PAP0_PGR1_PLR17_SU32_SUS256_SRVW4_TT1_32_WG64_4_1_WGM15
    StaggerU: 32
    StaggerUMapping: 0
    StaggerUStride: 256
    StoreRemapVectorWidth: 4
    StoreVectorWidth: 4
    SubGroup0: 4
    SubGroup1: 64
    SubGroupA: 4
    SubGroupB: 64
    SuppressNoLoadLoop: false
    ThreadTile: [1, 32]
    ThreadTile0: 16
    ThreadTile1: 1
    ThreadTileA: 16
    ThreadTileB: 1
    TransposeLDS: true
    UnrollIncIsDepthU: 0
    UnrollMajorLDSA: true
    UnrollMajorLDSB: true
    UnrollMemFence: false
    Use64bShadowLimit: 1
    UseInstOffsetForGRO: 0
    UseSgprForGRO: -1
    Valid: true
    VectorAtomicWidth: 1
    VectorStore: -1
    VectorWidth: 4
    WaveSeparateGlobalReadA: 1
    WaveSeparateGlobalReadB: 1
    WorkGroup: [64, 4, 1]
    WorkGroupMapping: 15
    WorkGroupMappingType: B
    _DepthULds: 128
    _GlobalAccumulation: null
    _UseSgprForGRO: 1
    _VectorStore: 1
    _WorkspaceSizePerElemC: 0
    _staggerStrideShift: 1
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- null
