; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck %s -check-prefixes=SI
; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck %s -check-prefixes=VI
; RUN: llc -march=r600 -mcpu=redwood < %s | FileCheck  %s -check-prefixes=EG

declare float @llvm.fabs.f32(float) #1

define amdgpu_kernel void @fp_to_uint_f32_to_i32 (i32 addrspace(1)* %out, float %in) {
; SI-LABEL: fp_to_uint_f32_to_i32:
; SI:       ; %bb.0:
; SI-NEXT:    s_load_dword s4, s[0:1], 0xb
; SI-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x9
; SI-NEXT:    s_mov_b32 s3, 0xf000
; SI-NEXT:    s_mov_b32 s2, -1
; SI-NEXT:    s_waitcnt lgkmcnt(0)
; SI-NEXT:    v_cvt_u32_f32_e32 v0, s4
; SI-NEXT:    buffer_store_dword v0, off, s[0:3], 0
; SI-NEXT:    s_endpgm
;
; VI-LABEL: fp_to_uint_f32_to_i32:
; VI:       ; %bb.0:
; VI-NEXT:    s_load_dword s2, s[0:1], 0x2c
; VI-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x24
; VI-NEXT:    s_mov_b32 s3, 0xf000
; VI-NEXT:    s_waitcnt lgkmcnt(0)
; VI-NEXT:    v_cvt_u32_f32_e32 v0, s2
; VI-NEXT:    s_mov_b32 s2, -1
; VI-NEXT:    buffer_store_dword v0, off, s[0:3], 0
; VI-NEXT:    s_endpgm
;
; EG-LABEL: fp_to_uint_f32_to_i32:
; EG:       ; %bb.0:
; EG-NEXT:    ALU 3, @4, KC0[CB0:0-32], KC1[]
; EG-NEXT:    MEM_RAT_CACHELESS STORE_RAW T1.X, T0.X, 1
; EG-NEXT:    CF_END
; EG-NEXT:    PAD
; EG-NEXT:    ALU clause starting at 4:
; EG-NEXT:     TRUNC * T0.W, KC0[2].Z,
; EG-NEXT:     LSHR T0.X, KC0[2].Y, literal.x,
; EG-NEXT:     FLT_TO_UINT * T1.X, PV.W,
; EG-NEXT:    2(2.802597e-45), 0(0.000000e+00)
  %conv = fptoui float %in to i32
  store i32 %conv, i32 addrspace(1)* %out
  ret void
}

define amdgpu_kernel void @fp_to_uint_v2f32_to_v2i32(<2 x i32> addrspace(1)* %out, <2 x float> %in) {
; SI-LABEL: fp_to_uint_v2f32_to_v2i32:
; SI:       ; %bb.0:
; SI-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0xb
; SI-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x9
; SI-NEXT:    s_mov_b32 s3, 0xf000
; SI-NEXT:    s_mov_b32 s2, -1
; SI-NEXT:    s_waitcnt lgkmcnt(0)
; SI-NEXT:    v_cvt_u32_f32_e32 v1, s5
; SI-NEXT:    v_cvt_u32_f32_e32 v0, s4
; SI-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0
; SI-NEXT:    s_endpgm
;
; VI-LABEL: fp_to_uint_v2f32_to_v2i32:
; VI:       ; %bb.0:
; VI-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0x2c
; VI-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x24
; VI-NEXT:    s_waitcnt lgkmcnt(0)
; VI-NEXT:    v_cvt_u32_f32_e32 v1, s3
; VI-NEXT:    v_cvt_u32_f32_e32 v0, s2
; VI-NEXT:    s_mov_b32 s3, 0xf000
; VI-NEXT:    s_mov_b32 s2, -1
; VI-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0
; VI-NEXT:    s_endpgm
;
; EG-LABEL: fp_to_uint_v2f32_to_v2i32:
; EG:       ; %bb.0:
; EG-NEXT:    ALU 5, @4, KC0[CB0:0-32], KC1[]
; EG-NEXT:    MEM_RAT_CACHELESS STORE_RAW T0.XY, T1.X, 1
; EG-NEXT:    CF_END
; EG-NEXT:    PAD
; EG-NEXT:    ALU clause starting at 4:
; EG-NEXT:     TRUNC T0.W, KC0[3].X,
; EG-NEXT:     TRUNC * T1.W, KC0[2].W,
; EG-NEXT:     FLT_TO_UINT * T0.Y, PV.W,
; EG-NEXT:     LSHR T1.X, KC0[2].Y, literal.x,
; EG-NEXT:     FLT_TO_UINT * T0.X, T1.W,
; EG-NEXT:    2(2.802597e-45), 0(0.000000e+00)
  %result = fptoui <2 x float> %in to <2 x i32>
  store <2 x i32> %result, <2 x i32> addrspace(1)* %out
  ret void
}

define amdgpu_kernel void @fp_to_uint_v4f32_to_v4i32(<4 x i32> addrspace(1)* %out, <4 x float> addrspace(1)* %in) {
; SI-LABEL: fp_to_uint_v4f32_to_v4i32:
; SI:       ; %bb.0:
; SI-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x9
; SI-NEXT:    s_waitcnt lgkmcnt(0)
; SI-NEXT:    s_load_dwordx4 s[4:7], s[2:3], 0x0
; SI-NEXT:    s_mov_b32 s3, 0xf000
; SI-NEXT:    s_mov_b32 s2, -1
; SI-NEXT:    s_waitcnt lgkmcnt(0)
; SI-NEXT:    v_cvt_u32_f32_e32 v3, s7
; SI-NEXT:    v_cvt_u32_f32_e32 v2, s6
; SI-NEXT:    v_cvt_u32_f32_e32 v1, s5
; SI-NEXT:    v_cvt_u32_f32_e32 v0, s4
; SI-NEXT:    buffer_store_dwordx4 v[0:3], off, s[0:3], 0
; SI-NEXT:    s_endpgm
;
; VI-LABEL: fp_to_uint_v4f32_to_v4i32:
; VI:       ; %bb.0:
; VI-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x24
; VI-NEXT:    s_waitcnt lgkmcnt(0)
; VI-NEXT:    s_load_dwordx4 s[4:7], s[2:3], 0x0
; VI-NEXT:    s_mov_b32 s3, 0xf000
; VI-NEXT:    s_mov_b32 s2, -1
; VI-NEXT:    s_waitcnt lgkmcnt(0)
; VI-NEXT:    v_cvt_u32_f32_e32 v3, s7
; VI-NEXT:    v_cvt_u32_f32_e32 v2, s6
; VI-NEXT:    v_cvt_u32_f32_e32 v1, s5
; VI-NEXT:    v_cvt_u32_f32_e32 v0, s4
; VI-NEXT:    buffer_store_dwordx4 v[0:3], off, s[0:3], 0
; VI-NEXT:    s_endpgm
;
; EG-LABEL: fp_to_uint_v4f32_to_v4i32:
; EG:       ; %bb.0:
; EG-NEXT:    ALU 0, @8, KC0[CB0:0-32], KC1[]
; EG-NEXT:    TEX 0 @6
; EG-NEXT:    ALU 9, @9, KC0[CB0:0-32], KC1[]
; EG-NEXT:    MEM_RAT_CACHELESS STORE_RAW T0.XYZW, T1.X, 1
; EG-NEXT:    CF_END
; EG-NEXT:    PAD
; EG-NEXT:    Fetch clause starting at 6:
; EG-NEXT:     VTX_READ_128 T0.XYZW, T0.X, 0, #1
; EG-NEXT:    ALU clause starting at 8:
; EG-NEXT:     MOV * T0.X, KC0[2].Z,
; EG-NEXT:    ALU clause starting at 9:
; EG-NEXT:     TRUNC T0.W, T0.W,
; EG-NEXT:     TRUNC * T1.W, T0.Z,
; EG-NEXT:     FLT_TO_UINT * T0.W, PV.W,
; EG-NEXT:     TRUNC T2.W, T0.Y,
; EG-NEXT:     FLT_TO_UINT * T0.Z, T1.W,
; EG-NEXT:     TRUNC T1.W, T0.X,
; EG-NEXT:     FLT_TO_UINT * T0.Y, PV.W,
; EG-NEXT:     LSHR T1.X, KC0[2].Y, literal.x,
; EG-NEXT:     FLT_TO_UINT * T0.X, PV.W,
; EG-NEXT:    2(2.802597e-45), 0(0.000000e+00)
  %value = load <4 x float>, <4 x float> addrspace(1) * %in
  %result = fptoui <4 x float> %value to <4 x i32>
  store <4 x i32> %result, <4 x i32> addrspace(1)* %out
  ret void
}

define amdgpu_kernel void @fp_to_uint_f32_to_i64(i64 addrspace(1)* %out, float %x) {
; SI-LABEL: fp_to_uint_f32_to_i64:
; SI:       ; %bb.0:
; SI-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
; SI-NEXT:    s_load_dword s8, s[0:1], 0xb
; SI-NEXT:    s_mov_b32 s7, 0xf000
; SI-NEXT:    s_mov_b32 s6, -1
; SI-NEXT:    s_movk_i32 s9, 0xff6a
; SI-NEXT:    s_mov_b32 s2, 0x7fffff
; SI-NEXT:    s_mov_b32 s10, 0x800000
; SI-NEXT:    s_mov_b32 s1, 0
; SI-NEXT:    s_movk_i32 s11, 0x96
; SI-NEXT:    s_movk_i32 s12, 0xff81
; SI-NEXT:    v_mov_b32_e32 v1, 0
; SI-NEXT:    v_mov_b32_e32 v4, 0x5f000000
; SI-NEXT:    s_waitcnt lgkmcnt(0)
; SI-NEXT:    s_bfe_u32 s3, s8, 0x80017
; SI-NEXT:    s_and_b32 s0, s8, s2
; SI-NEXT:    v_sub_f32_e32 v0, s8, v4
; SI-NEXT:    s_add_i32 s13, s3, s9
; SI-NEXT:    s_or_b32 s0, s0, s10
; SI-NEXT:    s_sub_i32 s14, s11, s3
; SI-NEXT:    s_add_i32 s15, s3, s12
; SI-NEXT:    v_bfe_u32 v2, v0, 23, 8
; SI-NEXT:    v_and_b32_e32 v3, s2, v0
; SI-NEXT:    v_ashrrev_i32_e32 v5, 31, v0
; SI-NEXT:    s_lshl_b64 s[2:3], s[0:1], s13
; SI-NEXT:    s_lshr_b64 s[0:1], s[0:1], s14
; SI-NEXT:    v_add_i32_e32 v6, vcc, s9, v2
; SI-NEXT:    v_or_b32_e32 v0, s10, v3
; SI-NEXT:    v_sub_i32_e32 v7, vcc, s11, v2
; SI-NEXT:    v_add_i32_e32 v8, vcc, s12, v2
; SI-NEXT:    v_ashrrev_i32_e32 v9, 31, v5
; SI-NEXT:    s_cmp_gt_i32 s15, 23
; SI-NEXT:    v_mov_b32_e32 v10, s1
; SI-NEXT:    v_mov_b32_e32 v11, s3
; SI-NEXT:    v_mov_b32_e32 v12, s0
; SI-NEXT:    v_mov_b32_e32 v13, s2
; SI-NEXT:    v_lshl_b64 v[2:3], v[0:1], v6
; SI-NEXT:    v_lshr_b64 v[0:1], v[0:1], v7
; SI-NEXT:    s_cselect_b64 vcc, -1, 0
; SI-NEXT:    v_cndmask_b32_e32 v6, v10, v11, vcc
; SI-NEXT:    s_ashr_i32 s2, s8, 31
; SI-NEXT:    v_cmp_lt_i32_e64 s[0:1], 23, v8
; SI-NEXT:    v_cndmask_b32_e64 v1, v1, v3, s[0:1]
; SI-NEXT:    v_cndmask_b32_e64 v0, v0, v2, s[0:1]
; SI-NEXT:    v_cndmask_b32_e32 v2, v12, v13, vcc
; SI-NEXT:    s_ashr_i32 s0, s2, 31
; SI-NEXT:    v_xor_b32_e32 v0, v0, v5
; SI-NEXT:    v_xor_b32_e32 v1, v1, v9
; SI-NEXT:    v_xor_b32_e32 v2, s2, v2
; SI-NEXT:    v_xor_b32_e32 v3, s0, v6
; SI-NEXT:    v_mov_b32_e32 v6, s0
; SI-NEXT:    s_cmp_lt_i32 s15, 0
; SI-NEXT:    v_sub_i32_e32 v0, vcc, v0, v5
; SI-NEXT:    v_subb_u32_e32 v1, vcc, v1, v9, vcc
; SI-NEXT:    v_subrev_i32_e32 v2, vcc, s2, v2
; SI-NEXT:    v_subb_u32_e32 v3, vcc, v3, v6, vcc
; SI-NEXT:    v_cmp_gt_i32_e32 vcc, 0, v8
; SI-NEXT:    v_cndmask_b32_e64 v0, v0, 0, vcc
; SI-NEXT:    v_cndmask_b32_e64 v1, v1, 0, vcc
; SI-NEXT:    s_cselect_b64 s[0:1], -1, 0
; SI-NEXT:    v_cndmask_b32_e64 v2, v2, 0, s[0:1]
; SI-NEXT:    v_cndmask_b32_e64 v3, v3, 0, s[0:1]
; SI-NEXT:    v_xor_b32_e32 v1, 0x80000000, v1
; SI-NEXT:    v_cmp_lt_f32_e32 vcc, s8, v4
; SI-NEXT:    v_cndmask_b32_e32 v0, v0, v2, vcc
; SI-NEXT:    v_cndmask_b32_e32 v1, v1, v3, vcc
; SI-NEXT:    buffer_store_dwordx2 v[0:1], off, s[4:7], 0
; SI-NEXT:    s_endpgm
;
; VI-LABEL: fp_to_uint_f32_to_i64:
; VI:       ; %bb.0:
; VI-NEXT:    s_load_dword s8, s[0:1], 0x2c
; VI-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x24
; VI-NEXT:    s_mov_b32 s11, 0x7fffff
; VI-NEXT:    s_movk_i32 s9, 0xff6a
; VI-NEXT:    s_mov_b32 s12, 0x800000
; VI-NEXT:    s_waitcnt lgkmcnt(0)
; VI-NEXT:    s_bfe_u32 s10, s8, 0x80017
; VI-NEXT:    s_and_b32 s0, s8, s11
; VI-NEXT:    s_movk_i32 s13, 0x96
; VI-NEXT:    s_add_i32 s2, s10, s9
; VI-NEXT:    s_or_b32 s0, s0, s12
; VI-NEXT:    s_mov_b32 s1, 0
; VI-NEXT:    s_sub_i32 s14, s13, s10
; VI-NEXT:    s_lshl_b64 s[2:3], s[0:1], s2
; VI-NEXT:    s_lshr_b64 s[0:1], s[0:1], s14
; VI-NEXT:    s_movk_i32 s14, 0xff81
; VI-NEXT:    s_add_i32 s10, s10, s14
; VI-NEXT:    s_cmp_gt_i32 s10, 23
; VI-NEXT:    v_mov_b32_e32 v0, s1
; VI-NEXT:    v_mov_b32_e32 v1, s3
; VI-NEXT:    s_cselect_b64 vcc, -1, 0
; VI-NEXT:    v_cndmask_b32_e32 v0, v0, v1, vcc
; VI-NEXT:    v_mov_b32_e32 v1, s0
; VI-NEXT:    v_mov_b32_e32 v2, s2
; VI-NEXT:    v_cndmask_b32_e32 v1, v1, v2, vcc
; VI-NEXT:    s_ashr_i32 s0, s8, 31
; VI-NEXT:    s_ashr_i32 s1, s0, 31
; VI-NEXT:    v_xor_b32_e32 v1, s0, v1
; VI-NEXT:    v_mov_b32_e32 v6, 0x5f000000
; VI-NEXT:    v_xor_b32_e32 v0, s1, v0
; VI-NEXT:    v_mov_b32_e32 v2, s1
; VI-NEXT:    v_subrev_u32_e32 v3, vcc, s0, v1
; VI-NEXT:    v_sub_f32_e32 v7, s8, v6
; VI-NEXT:    v_subb_u32_e32 v4, vcc, v0, v2, vcc
; VI-NEXT:    s_cmp_lt_i32 s10, 0
; VI-NEXT:    v_bfe_u32 v8, v7, 23, 8
; VI-NEXT:    v_and_b32_e32 v0, s11, v7
; VI-NEXT:    v_mov_b32_e32 v1, 0
; VI-NEXT:    s_cselect_b64 s[2:3], -1, 0
; VI-NEXT:    v_add_u32_e32 v2, vcc, s9, v8
; VI-NEXT:    v_or_b32_e32 v0, s12, v0
; VI-NEXT:    v_sub_u32_e32 v9, vcc, s13, v8
; VI-NEXT:    v_cndmask_b32_e64 v5, v3, 0, s[2:3]
; VI-NEXT:    v_lshlrev_b64 v[2:3], v2, v[0:1]
; VI-NEXT:    v_lshrrev_b64 v[0:1], v9, v[0:1]
; VI-NEXT:    v_add_u32_e32 v8, vcc, s14, v8
; VI-NEXT:    v_cmp_lt_i32_e32 vcc, 23, v8
; VI-NEXT:    v_cndmask_b32_e32 v0, v0, v2, vcc
; VI-NEXT:    v_ashrrev_i32_e32 v2, 31, v7
; VI-NEXT:    v_cndmask_b32_e32 v1, v1, v3, vcc
; VI-NEXT:    v_ashrrev_i32_e32 v3, 31, v2
; VI-NEXT:    v_xor_b32_e32 v0, v0, v2
; VI-NEXT:    v_xor_b32_e32 v1, v1, v3
; VI-NEXT:    v_sub_u32_e32 v0, vcc, v0, v2
; VI-NEXT:    v_subb_u32_e32 v1, vcc, v1, v3, vcc
; VI-NEXT:    v_cmp_gt_i32_e32 vcc, 0, v8
; VI-NEXT:    v_cndmask_b32_e64 v1, v1, 0, vcc
; VI-NEXT:    v_cndmask_b32_e64 v0, v0, 0, vcc
; VI-NEXT:    v_cmp_lt_f32_e64 s[0:1], s8, v6
; VI-NEXT:    v_cndmask_b32_e64 v2, v4, 0, s[2:3]
; VI-NEXT:    v_xor_b32_e32 v1, 0x80000000, v1
; VI-NEXT:    s_mov_b32 s7, 0xf000
; VI-NEXT:    s_mov_b32 s6, -1
; VI-NEXT:    v_cndmask_b32_e64 v0, v0, v5, s[0:1]
; VI-NEXT:    v_cndmask_b32_e64 v1, v1, v2, s[0:1]
; VI-NEXT:    buffer_store_dwordx2 v[0:1], off, s[4:7], 0
; VI-NEXT:    s_endpgm
;
; EG-LABEL: fp_to_uint_f32_to_i64:
; EG:       ; %bb.0:
; EG-NEXT:    ALU 40, @4, KC0[CB0:0-32], KC1[]
; EG-NEXT:    MEM_RAT_CACHELESS STORE_RAW T0.XY, T1.X, 1
; EG-NEXT:    CF_END
; EG-NEXT:    PAD
; EG-NEXT:    ALU clause starting at 4:
; EG-NEXT:     MOV * T0.W, literal.x,
; EG-NEXT:    8(1.121039e-44), 0(0.000000e+00)
; EG-NEXT:     BFE_UINT T0.W, KC0[2].Z, literal.x, PV.W,
; EG-NEXT:     AND_INT * T1.W, KC0[2].Z, literal.y,
; EG-NEXT:    23(3.222986e-44), 8388607(1.175494e-38)
; EG-NEXT:     OR_INT T1.W, PS, literal.x,
; EG-NEXT:     ADD_INT * T2.W, PV.W, literal.y,
; EG-NEXT:    8388608(1.175494e-38), -150(nan)
; EG-NEXT:     ADD_INT T0.X, T0.W, literal.x,
; EG-NEXT:     SUB_INT T0.Y, literal.y, T0.W,
; EG-NEXT:     AND_INT T0.Z, PS, literal.z,
; EG-NEXT:     NOT_INT T0.W, PS,
; EG-NEXT:     LSHR * T3.W, PV.W, 1,
; EG-NEXT:    -127(nan), 150(2.101948e-43)
; EG-NEXT:    31(4.344025e-44), 0(0.000000e+00)
; EG-NEXT:     BIT_ALIGN_INT T1.X, 0.0, PS, PV.W,
; EG-NEXT:     LSHL T1.Y, T1.W, PV.Z,
; EG-NEXT:     AND_INT T0.Z, T2.W, literal.x, BS:VEC_120/SCL_212
; EG-NEXT:     BIT_ALIGN_INT T0.W, 0.0, T1.W, PV.Y, BS:VEC_021/SCL_122
; EG-NEXT:     AND_INT * T1.W, PV.Y, literal.x,
; EG-NEXT:    32(4.484155e-44), 0(0.000000e+00)
; EG-NEXT:     CNDE_INT T0.Y, PS, PV.W, 0.0,
; EG-NEXT:     CNDE_INT T1.Z, PV.Z, PV.Y, 0.0,
; EG-NEXT:     CNDE_INT T0.W, PV.Z, PV.X, PV.Y,
; EG-NEXT:     SETGT_INT * T1.W, T0.X, literal.x,
; EG-NEXT:    23(3.222986e-44), 0(0.000000e+00)
; EG-NEXT:     CNDE_INT T0.Z, PS, 0.0, PV.W,
; EG-NEXT:     CNDE_INT T0.W, PS, PV.Y, PV.Z,
; EG-NEXT:     ASHR * T1.W, KC0[2].Z, literal.x,
; EG-NEXT:    31(4.344025e-44), 0(0.000000e+00)
; EG-NEXT:     XOR_INT T0.W, PV.W, PS,
; EG-NEXT:     XOR_INT * T2.W, PV.Z, PS,
; EG-NEXT:     SUB_INT T2.W, PS, T1.W,
; EG-NEXT:     SUBB_UINT * T3.W, PV.W, T1.W,
; EG-NEXT:     SUB_INT T2.W, PV.W, PS,
; EG-NEXT:     SETGT_INT * T3.W, 0.0, T0.X,
; EG-NEXT:     CNDE_INT T0.Y, PS, PV.W, 0.0,
; EG-NEXT:     SUB_INT * T0.W, T0.W, T1.W,
; EG-NEXT:     CNDE_INT T0.X, T3.W, PV.W, 0.0,
; EG-NEXT:     LSHR * T1.X, KC0[2].Y, literal.x,
; EG-NEXT:    2(2.802597e-45), 0(0.000000e+00)
  %conv = fptoui float %x to i64
  store i64 %conv, i64 addrspace(1)* %out
  ret void
}

define amdgpu_kernel void @fp_to_uint_v2f32_to_v2i64(<2 x i64> addrspace(1)* %out, <2 x float> %x) {
; SI-LABEL: fp_to_uint_v2f32_to_v2i64:
; SI:       ; %bb.0:
; SI-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
; SI-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0xb
; SI-NEXT:    s_mov_b32 s7, 0xf000
; SI-NEXT:    s_mov_b32 s6, -1
; SI-NEXT:    s_movk_i32 s12, 0xff6a
; SI-NEXT:    s_mov_b32 s13, 0x7fffff
; SI-NEXT:    s_mov_b32 s14, 0x800000
; SI-NEXT:    s_mov_b32 s9, 0
; SI-NEXT:    s_movk_i32 s15, 0x96
; SI-NEXT:    s_movk_i32 s16, 0xff81
; SI-NEXT:    v_mov_b32_e32 v2, 0
; SI-NEXT:    v_mov_b32_e32 v0, 0x5f000000
; SI-NEXT:    s_brev_b32 s17, 1
; SI-NEXT:    s_waitcnt lgkmcnt(0)
; SI-NEXT:    s_bfe_u32 s0, s3, 0x80017
; SI-NEXT:    s_and_b32 s1, s3, s13
; SI-NEXT:    v_sub_f32_e32 v1, s3, v0
; SI-NEXT:    v_sub_f32_e32 v3, s2, v0
; SI-NEXT:    s_add_i32 s10, s0, s12
; SI-NEXT:    s_or_b32 s8, s1, s14
; SI-NEXT:    s_sub_i32 s11, s15, s0
; SI-NEXT:    s_add_i32 s18, s0, s16
; SI-NEXT:    v_bfe_u32 v4, v1, 23, 8
; SI-NEXT:    v_and_b32_e32 v5, s13, v1
; SI-NEXT:    v_ashrrev_i32_e32 v7, 31, v1
; SI-NEXT:    v_bfe_u32 v6, v3, 23, 8
; SI-NEXT:    v_and_b32_e32 v8, s13, v3
; SI-NEXT:    v_ashrrev_i32_e32 v9, 31, v3
; SI-NEXT:    s_lshl_b64 s[0:1], s[8:9], s10
; SI-NEXT:    s_lshr_b64 s[10:11], s[8:9], s11
; SI-NEXT:    v_add_i32_e32 v3, vcc, s12, v4
; SI-NEXT:    v_or_b32_e32 v1, s14, v5
; SI-NEXT:    v_sub_i32_e32 v5, vcc, s15, v4
; SI-NEXT:    v_add_i32_e32 v10, vcc, s16, v4
; SI-NEXT:    v_ashrrev_i32_e32 v11, 31, v7
; SI-NEXT:    v_add_i32_e32 v12, vcc, s12, v6
; SI-NEXT:    v_sub_i32_e32 v13, vcc, s15, v6
; SI-NEXT:    v_add_i32_e32 v14, vcc, s16, v6
; SI-NEXT:    v_ashrrev_i32_e32 v15, 31, v9
; SI-NEXT:    s_cmp_gt_i32 s18, 23
; SI-NEXT:    v_mov_b32_e32 v16, s11
; SI-NEXT:    v_mov_b32_e32 v17, s1
; SI-NEXT:    v_mov_b32_e32 v18, s10
; SI-NEXT:    v_mov_b32_e32 v19, s0
; SI-NEXT:    v_lshl_b64 v[3:4], v[1:2], v3
; SI-NEXT:    v_lshr_b64 v[5:6], v[1:2], v5
; SI-NEXT:    v_or_b32_e32 v1, s14, v8
; SI-NEXT:    s_cselect_b64 vcc, -1, 0
; SI-NEXT:    v_cndmask_b32_e32 v8, v16, v17, vcc
; SI-NEXT:    s_ashr_i32 s8, s3, 31
; SI-NEXT:    v_cmp_lt_i32_e64 s[0:1], 23, v10
; SI-NEXT:    v_cndmask_b32_e64 v6, v6, v4, s[0:1]
; SI-NEXT:    v_cndmask_b32_e64 v5, v5, v3, s[0:1]
; SI-NEXT:    v_lshl_b64 v[3:4], v[1:2], v12
; SI-NEXT:    v_lshr_b64 v[1:2], v[1:2], v13
; SI-NEXT:    v_cndmask_b32_e32 v12, v18, v19, vcc
; SI-NEXT:    s_ashr_i32 s0, s8, 31
; SI-NEXT:    v_xor_b32_e32 v5, v5, v7
; SI-NEXT:    v_xor_b32_e32 v6, v6, v11
; SI-NEXT:    v_cmp_lt_i32_e32 vcc, 23, v14
; SI-NEXT:    v_cndmask_b32_e32 v2, v2, v4, vcc
; SI-NEXT:    v_cndmask_b32_e32 v1, v1, v3, vcc
; SI-NEXT:    v_xor_b32_e32 v3, s8, v12
; SI-NEXT:    v_xor_b32_e32 v4, s0, v8
; SI-NEXT:    v_mov_b32_e32 v8, s0
; SI-NEXT:    s_cmp_lt_i32 s18, 0
; SI-NEXT:    v_sub_i32_e32 v5, vcc, v5, v7
; SI-NEXT:    v_subb_u32_e32 v6, vcc, v6, v11, vcc
; SI-NEXT:    v_xor_b32_e32 v1, v1, v9
; SI-NEXT:    v_xor_b32_e32 v2, v2, v15
; SI-NEXT:    v_subrev_i32_e32 v3, vcc, s8, v3
; SI-NEXT:    v_subb_u32_e32 v4, vcc, v4, v8, vcc
; SI-NEXT:    s_cselect_b64 s[10:11], -1, 0
; SI-NEXT:    v_cmp_gt_i32_e32 vcc, 0, v10
; SI-NEXT:    v_cndmask_b32_e64 v5, v5, 0, vcc
; SI-NEXT:    s_bfe_u32 s18, s2, 0x80017
; SI-NEXT:    s_and_b32 s8, s2, s13
; SI-NEXT:    v_sub_i32_e64 v1, s[0:1], v1, v9
; SI-NEXT:    v_subb_u32_e64 v2, s[0:1], v2, v15, s[0:1]
; SI-NEXT:    v_cndmask_b32_e64 v6, v6, 0, vcc
; SI-NEXT:    v_cndmask_b32_e64 v3, v3, 0, s[10:11]
; SI-NEXT:    s_add_i32 s0, s18, s12
; SI-NEXT:    s_or_b32 s8, s8, s14
; SI-NEXT:    s_sub_i32 s12, s15, s18
; SI-NEXT:    s_add_i32 s18, s18, s16
; SI-NEXT:    v_cmp_gt_i32_e32 vcc, 0, v14
; SI-NEXT:    v_cndmask_b32_e64 v1, v1, 0, vcc
; SI-NEXT:    v_cndmask_b32_e64 v4, v4, 0, s[10:11]
; SI-NEXT:    v_xor_b32_e32 v6, s17, v6
; SI-NEXT:    v_cndmask_b32_e64 v7, v2, 0, vcc
; SI-NEXT:    v_cmp_lt_f32_e32 vcc, s3, v0
; SI-NEXT:    v_cndmask_b32_e32 v2, v5, v3, vcc
; SI-NEXT:    s_lshl_b64 s[0:1], s[8:9], s0
; SI-NEXT:    s_lshr_b64 s[8:9], s[8:9], s12
; SI-NEXT:    v_cndmask_b32_e32 v3, v6, v4, vcc
; SI-NEXT:    v_xor_b32_e32 v4, s17, v7
; SI-NEXT:    s_cmp_gt_i32 s18, 23
; SI-NEXT:    v_mov_b32_e32 v5, s9
; SI-NEXT:    v_mov_b32_e32 v6, s1
; SI-NEXT:    v_mov_b32_e32 v7, s8
; SI-NEXT:    v_mov_b32_e32 v8, s0
; SI-NEXT:    s_cselect_b64 vcc, -1, 0
; SI-NEXT:    v_cndmask_b32_e32 v5, v5, v6, vcc
; SI-NEXT:    s_ashr_i32 s0, s2, 31
; SI-NEXT:    v_cndmask_b32_e32 v6, v7, v8, vcc
; SI-NEXT:    s_ashr_i32 s1, s0, 31
; SI-NEXT:    v_xor_b32_e32 v6, s0, v6
; SI-NEXT:    v_xor_b32_e32 v5, s1, v5
; SI-NEXT:    v_mov_b32_e32 v7, s1
; SI-NEXT:    s_cmp_lt_i32 s18, 0
; SI-NEXT:    v_subrev_i32_e32 v6, vcc, s0, v6
; SI-NEXT:    v_subb_u32_e32 v5, vcc, v5, v7, vcc
; SI-NEXT:    s_cselect_b64 s[0:1], -1, 0
; SI-NEXT:    v_cndmask_b32_e64 v6, v6, 0, s[0:1]
; SI-NEXT:    v_cndmask_b32_e64 v5, v5, 0, s[0:1]
; SI-NEXT:    v_cmp_lt_f32_e32 vcc, s2, v0
; SI-NEXT:    v_cndmask_b32_e32 v0, v1, v6, vcc
; SI-NEXT:    v_cndmask_b32_e32 v1, v4, v5, vcc
; SI-NEXT:    buffer_store_dwordx4 v[0:3], off, s[4:7], 0
; SI-NEXT:    s_endpgm
;
; VI-LABEL: fp_to_uint_v2f32_to_v2i64:
; VI:       ; %bb.0:
; VI-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x2c
; VI-NEXT:    s_load_dwordx2 s[8:9], s[0:1], 0x24
; VI-NEXT:    s_mov_b32 s17, 0x7fffff
; VI-NEXT:    s_movk_i32 s16, 0xff6a
; VI-NEXT:    s_mov_b32 s18, 0x800000
; VI-NEXT:    s_waitcnt lgkmcnt(0)
; VI-NEXT:    s_bfe_u32 s12, s5, 0x80017
; VI-NEXT:    s_and_b32 s1, s5, s17
; VI-NEXT:    s_movk_i32 s19, 0x96
; VI-NEXT:    s_add_i32 s0, s12, s16
; VI-NEXT:    s_or_b32 s6, s1, s18
; VI-NEXT:    s_mov_b32 s7, 0
; VI-NEXT:    s_sub_i32 s2, s19, s12
; VI-NEXT:    s_movk_i32 s20, 0xff81
; VI-NEXT:    s_lshl_b64 s[0:1], s[6:7], s0
; VI-NEXT:    s_lshr_b64 s[2:3], s[6:7], s2
; VI-NEXT:    s_add_i32 s12, s12, s20
; VI-NEXT:    s_cmp_gt_i32 s12, 23
; VI-NEXT:    v_mov_b32_e32 v0, s3
; VI-NEXT:    v_mov_b32_e32 v1, s1
; VI-NEXT:    s_cselect_b64 vcc, -1, 0
; VI-NEXT:    v_cndmask_b32_e32 v0, v0, v1, vcc
; VI-NEXT:    v_mov_b32_e32 v1, s2
; VI-NEXT:    v_mov_b32_e32 v2, s0
; VI-NEXT:    v_cndmask_b32_e32 v1, v1, v2, vcc
; VI-NEXT:    s_ashr_i32 s0, s5, 31
; VI-NEXT:    s_ashr_i32 s1, s0, 31
; VI-NEXT:    v_xor_b32_e32 v1, s0, v1
; VI-NEXT:    v_mov_b32_e32 v8, 0x5f000000
; VI-NEXT:    v_xor_b32_e32 v0, s1, v0
; VI-NEXT:    v_mov_b32_e32 v2, s1
; VI-NEXT:    v_subrev_u32_e32 v3, vcc, s0, v1
; VI-NEXT:    v_sub_f32_e32 v9, s5, v8
; VI-NEXT:    v_subb_u32_e32 v6, vcc, v0, v2, vcc
; VI-NEXT:    s_cmp_lt_i32 s12, 0
; VI-NEXT:    v_bfe_u32 v10, v9, 23, 8
; VI-NEXT:    v_and_b32_e32 v0, s17, v9
; VI-NEXT:    v_mov_b32_e32 v1, 0
; VI-NEXT:    s_cselect_b64 s[12:13], -1, 0
; VI-NEXT:    v_add_u32_e32 v2, vcc, s16, v10
; VI-NEXT:    v_or_b32_e32 v0, s18, v0
; VI-NEXT:    v_sub_u32_e32 v4, vcc, s19, v10
; VI-NEXT:    v_cndmask_b32_e64 v7, v3, 0, s[12:13]
; VI-NEXT:    v_lshlrev_b64 v[2:3], v2, v[0:1]
; VI-NEXT:    v_lshrrev_b64 v[4:5], v4, v[0:1]
; VI-NEXT:    v_add_u32_e32 v0, vcc, s20, v10
; VI-NEXT:    v_cmp_lt_i32_e32 vcc, 23, v0
; VI-NEXT:    v_cndmask_b32_e32 v2, v4, v2, vcc
; VI-NEXT:    v_ashrrev_i32_e32 v4, 31, v9
; VI-NEXT:    v_cmp_lt_f32_e64 s[2:3], s5, v8
; VI-NEXT:    s_bfe_u32 s5, s4, 0x80017
; VI-NEXT:    s_and_b32 s6, s4, s17
; VI-NEXT:    v_cndmask_b32_e32 v3, v5, v3, vcc
; VI-NEXT:    v_ashrrev_i32_e32 v5, 31, v4
; VI-NEXT:    v_xor_b32_e32 v2, v2, v4
; VI-NEXT:    s_add_i32 s14, s5, s16
; VI-NEXT:    s_or_b32 s6, s6, s18
; VI-NEXT:    s_sub_i32 s21, s19, s5
; VI-NEXT:    v_xor_b32_e32 v3, v3, v5
; VI-NEXT:    v_sub_u32_e32 v2, vcc, v2, v4
; VI-NEXT:    v_cmp_gt_i32_e64 s[0:1], 0, v0
; VI-NEXT:    s_lshl_b64 s[14:15], s[6:7], s14
; VI-NEXT:    s_lshr_b64 s[6:7], s[6:7], s21
; VI-NEXT:    s_add_i32 s5, s5, s20
; VI-NEXT:    v_subb_u32_e32 v5, vcc, v3, v5, vcc
; VI-NEXT:    v_cndmask_b32_e64 v0, v2, 0, s[0:1]
; VI-NEXT:    s_cmp_gt_i32 s5, 23
; VI-NEXT:    v_cndmask_b32_e64 v2, v0, v7, s[2:3]
; VI-NEXT:    v_mov_b32_e32 v0, s7
; VI-NEXT:    v_mov_b32_e32 v3, s15
; VI-NEXT:    s_cselect_b64 vcc, -1, 0
; VI-NEXT:    v_cndmask_b32_e32 v0, v0, v3, vcc
; VI-NEXT:    v_mov_b32_e32 v3, s6
; VI-NEXT:    v_mov_b32_e32 v4, s14
; VI-NEXT:    v_cndmask_b32_e32 v3, v3, v4, vcc
; VI-NEXT:    s_ashr_i32 s6, s4, 31
; VI-NEXT:    s_ashr_i32 s7, s6, 31
; VI-NEXT:    v_xor_b32_e32 v3, s6, v3
; VI-NEXT:    v_xor_b32_e32 v0, s7, v0
; VI-NEXT:    v_mov_b32_e32 v4, s7
; VI-NEXT:    v_subrev_u32_e32 v3, vcc, s6, v3
; VI-NEXT:    s_cmp_lt_i32 s5, 0
; VI-NEXT:    v_sub_f32_e32 v10, s4, v8
; VI-NEXT:    v_subb_u32_e32 v7, vcc, v0, v4, vcc
; VI-NEXT:    s_cselect_b64 s[6:7], -1, 0
; VI-NEXT:    v_bfe_u32 v11, v10, 23, 8
; VI-NEXT:    v_and_b32_e32 v0, s17, v10
; VI-NEXT:    v_cndmask_b32_e64 v9, v3, 0, s[6:7]
; VI-NEXT:    v_add_u32_e32 v3, vcc, s16, v11
; VI-NEXT:    v_or_b32_e32 v0, s18, v0
; VI-NEXT:    v_sub_u32_e32 v12, vcc, s19, v11
; VI-NEXT:    v_lshlrev_b64 v[3:4], v3, v[0:1]
; VI-NEXT:    v_lshrrev_b64 v[0:1], v12, v[0:1]
; VI-NEXT:    v_add_u32_e32 v11, vcc, s20, v11
; VI-NEXT:    v_cmp_lt_i32_e32 vcc, 23, v11
; VI-NEXT:    v_cndmask_b32_e32 v0, v0, v3, vcc
; VI-NEXT:    v_ashrrev_i32_e32 v3, 31, v10
; VI-NEXT:    v_cndmask_b32_e32 v1, v1, v4, vcc
; VI-NEXT:    v_ashrrev_i32_e32 v4, 31, v3
; VI-NEXT:    v_xor_b32_e32 v0, v0, v3
; VI-NEXT:    v_xor_b32_e32 v1, v1, v4
; VI-NEXT:    v_sub_u32_e32 v0, vcc, v0, v3
; VI-NEXT:    v_subb_u32_e32 v1, vcc, v1, v4, vcc
; VI-NEXT:    v_cmp_gt_i32_e32 vcc, 0, v11
; VI-NEXT:    v_cndmask_b32_e64 v4, v5, 0, s[0:1]
; VI-NEXT:    s_brev_b32 s0, 1
; VI-NEXT:    v_cndmask_b32_e64 v3, v6, 0, s[12:13]
; VI-NEXT:    v_xor_b32_e32 v4, s0, v4
; VI-NEXT:    v_cndmask_b32_e64 v1, v1, 0, vcc
; VI-NEXT:    v_cndmask_b32_e64 v0, v0, 0, vcc
; VI-NEXT:    v_cmp_lt_f32_e64 s[4:5], s4, v8
; VI-NEXT:    v_cndmask_b32_e64 v3, v4, v3, s[2:3]
; VI-NEXT:    v_cndmask_b32_e64 v4, v7, 0, s[6:7]
; VI-NEXT:    v_xor_b32_e32 v1, s0, v1
; VI-NEXT:    s_mov_b32 s11, 0xf000
; VI-NEXT:    s_mov_b32 s10, -1
; VI-NEXT:    v_cndmask_b32_e64 v0, v0, v9, s[4:5]
; VI-NEXT:    v_cndmask_b32_e64 v1, v1, v4, s[4:5]
; VI-NEXT:    buffer_store_dwordx4 v[0:3], off, s[8:11], 0
; VI-NEXT:    s_endpgm
;
; EG-LABEL: fp_to_uint_v2f32_to_v2i64:
; EG:       ; %bb.0:
; EG-NEXT:    ALU 75, @4, KC0[CB0:0-32], KC1[]
; EG-NEXT:    MEM_RAT_CACHELESS STORE_RAW T1.XYZW, T0.X, 1
; EG-NEXT:    CF_END
; EG-NEXT:    PAD
; EG-NEXT:    ALU clause starting at 4:
; EG-NEXT:     MOV * T0.W, literal.x,
; EG-NEXT:    8(1.121039e-44), 0(0.000000e+00)
; EG-NEXT:     BFE_UINT * T1.W, KC0[2].W, literal.x, PV.W,
; EG-NEXT:    23(3.222986e-44), 0(0.000000e+00)
; EG-NEXT:     AND_INT T0.Z, KC0[2].W, literal.x,
; EG-NEXT:     BFE_UINT T0.W, KC0[3].X, literal.y, T0.W,
; EG-NEXT:     ADD_INT * T2.W, PV.W, literal.z,
; EG-NEXT:    8388607(1.175494e-38), 23(3.222986e-44)
; EG-NEXT:    -150(nan), 0(0.000000e+00)
; EG-NEXT:     SUB_INT T0.X, literal.x, PV.W,
; EG-NEXT:     SUB_INT T0.Y, literal.x, T1.W,
; EG-NEXT:     AND_INT T1.Z, PS, literal.y,
; EG-NEXT:     OR_INT T3.W, PV.Z, literal.z,
; EG-NEXT:     AND_INT * T4.W, KC0[3].X, literal.w,
; EG-NEXT:    150(2.101948e-43), 31(4.344025e-44)
; EG-NEXT:    8388608(1.175494e-38), 8388607(1.175494e-38)
; EG-NEXT:     OR_INT T1.X, PS, literal.x,
; EG-NEXT:     LSHL T1.Y, PV.W, PV.Z,
; EG-NEXT:     AND_INT T0.Z, T2.W, literal.y,
; EG-NEXT:     BIT_ALIGN_INT T4.W, 0.0, PV.W, PV.Y,
; EG-NEXT:     AND_INT * T5.W, PV.Y, literal.y,
; EG-NEXT:    8388608(1.175494e-38), 32(4.484155e-44)
; EG-NEXT:     CNDE_INT T2.X, PS, PV.W, 0.0,
; EG-NEXT:     CNDE_INT T0.Y, PV.Z, PV.Y, 0.0,
; EG-NEXT:     ADD_INT T1.Z, T0.W, literal.x,
; EG-NEXT:     BIT_ALIGN_INT T4.W, 0.0, PV.X, T0.X,
; EG-NEXT:     AND_INT * T5.W, T0.X, literal.y,
; EG-NEXT:    -150(nan), 32(4.484155e-44)
; EG-NEXT:     CNDE_INT T0.X, PS, PV.W, 0.0,
; EG-NEXT:     NOT_INT T2.Y, T2.W,
; EG-NEXT:     AND_INT T2.Z, PV.Z, literal.x,
; EG-NEXT:     NOT_INT T2.W, PV.Z,
; EG-NEXT:     LSHR * T4.W, T1.X, 1,
; EG-NEXT:    31(4.344025e-44), 0(0.000000e+00)
; EG-NEXT:     LSHR T3.X, T3.W, 1,
; EG-NEXT:     ADD_INT T3.Y, T0.W, literal.x, BS:VEC_120/SCL_212
; EG-NEXT:     BIT_ALIGN_INT T3.Z, 0.0, PS, PV.W,
; EG-NEXT:     LSHL T0.W, T1.X, PV.Z,
; EG-NEXT:     AND_INT * T2.W, T1.Z, literal.y,
; EG-NEXT:    -127(nan), 32(4.484155e-44)
; EG-NEXT:     CNDE_INT T1.X, PS, PV.W, 0.0,
; EG-NEXT:     CNDE_INT T4.Y, PS, PV.Z, PV.W,
; EG-NEXT:     SETGT_INT T1.Z, PV.Y, literal.x,
; EG-NEXT:     BIT_ALIGN_INT T0.W, 0.0, PV.X, T2.Y,
; EG-NEXT:     ADD_INT * T1.W, T1.W, literal.y,
; EG-NEXT:    23(3.222986e-44), -127(nan)
; EG-NEXT:     CNDE_INT T3.X, T0.Z, PV.W, T1.Y,
; EG-NEXT:     SETGT_INT T1.Y, PS, literal.x,
; EG-NEXT:     CNDE_INT T0.Z, PV.Z, 0.0, PV.Y,
; EG-NEXT:     CNDE_INT T0.W, PV.Z, T0.X, PV.X,
; EG-NEXT:     ASHR * T2.W, KC0[3].X, literal.y,
; EG-NEXT:    23(3.222986e-44), 31(4.344025e-44)
; EG-NEXT:     XOR_INT T0.X, PV.W, PS,
; EG-NEXT:     XOR_INT T2.Y, PV.Z, PS,
; EG-NEXT:     CNDE_INT T0.Z, PV.Y, 0.0, PV.X,
; EG-NEXT:     CNDE_INT T0.W, PV.Y, T2.X, T0.Y,
; EG-NEXT:     ASHR * T3.W, KC0[2].W, literal.x,
; EG-NEXT:    31(4.344025e-44), 0(0.000000e+00)
; EG-NEXT:     XOR_INT T0.Y, PV.W, PS,
; EG-NEXT:     XOR_INT T0.Z, PV.Z, PS,
; EG-NEXT:     SUB_INT T0.W, PV.Y, T2.W,
; EG-NEXT:     SUBB_UINT * T4.W, PV.X, T2.W,
; EG-NEXT:     SUB_INT T1.Y, PV.W, PS,
; EG-NEXT:     SETGT_INT T1.Z, 0.0, T3.Y,
; EG-NEXT:     SUB_INT T0.W, PV.Z, T3.W,
; EG-NEXT:     SUBB_UINT * T4.W, PV.Y, T3.W,
; EG-NEXT:     SUB_INT T0.Z, PV.W, PS,
; EG-NEXT:     SETGT_INT T0.W, 0.0, T1.W,
; EG-NEXT:     CNDE_INT * T1.W, PV.Z, PV.Y, 0.0,
; EG-NEXT:     CNDE_INT T1.Y, PV.W, PV.Z, 0.0,
; EG-NEXT:     SUB_INT * T2.W, T0.X, T2.W,
; EG-NEXT:     CNDE_INT T1.Z, T1.Z, PV.W, 0.0,
; EG-NEXT:     SUB_INT * T2.W, T0.Y, T3.W,
; EG-NEXT:     CNDE_INT T1.X, T0.W, PV.W, 0.0,
; EG-NEXT:     LSHR * T0.X, KC0[2].Y, literal.x,
; EG-NEXT:    2(2.802597e-45), 0(0.000000e+00)
  %conv = fptoui <2 x float> %x to <2 x i64>
  store <2 x i64> %conv, <2 x i64> addrspace(1)* %out
  ret void
}

define amdgpu_kernel void @fp_to_uint_v4f32_to_v4i64(<4 x i64> addrspace(1)* %out, <4 x float> %x) {
; SI-LABEL: fp_to_uint_v4f32_to_v4i64:
; SI:       ; %bb.0:
; SI-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
; SI-NEXT:    s_load_dwordx4 s[8:11], s[0:1], 0xd
; SI-NEXT:    s_mov_b32 s7, 0xf000
; SI-NEXT:    s_mov_b32 s6, -1
; SI-NEXT:    s_movk_i32 s12, 0xff6a
; SI-NEXT:    s_mov_b32 s13, 0x7fffff
; SI-NEXT:    s_mov_b32 s14, 0x800000
; SI-NEXT:    s_mov_b32 s3, 0
; SI-NEXT:    s_movk_i32 s15, 0x96
; SI-NEXT:    s_movk_i32 s16, 0xff81
; SI-NEXT:    v_mov_b32_e32 v1, 0
; SI-NEXT:    v_mov_b32_e32 v2, 0x5f000000
; SI-NEXT:    s_brev_b32 s17, 1
; SI-NEXT:    s_waitcnt lgkmcnt(0)
; SI-NEXT:    s_bfe_u32 s0, s9, 0x80017
; SI-NEXT:    s_and_b32 s1, s9, s13
; SI-NEXT:    v_sub_f32_e32 v0, s9, v2
; SI-NEXT:    v_sub_f32_e32 v3, s8, v2
; SI-NEXT:    v_sub_f32_e32 v4, s11, v2
; SI-NEXT:    v_sub_f32_e32 v7, s10, v2
; SI-NEXT:    s_add_i32 s18, s0, s12
; SI-NEXT:    s_or_b32 s2, s1, s14
; SI-NEXT:    s_sub_i32 s19, s15, s0
; SI-NEXT:    s_add_i32 s20, s0, s16
; SI-NEXT:    v_bfe_u32 v5, v0, 23, 8
; SI-NEXT:    v_and_b32_e32 v6, s13, v0
; SI-NEXT:    v_ashrrev_i32_e32 v8, 31, v0
; SI-NEXT:    v_bfe_u32 v9, v3, 23, 8
; SI-NEXT:    v_and_b32_e32 v10, s13, v3
; SI-NEXT:    v_ashrrev_i32_e32 v11, 31, v3
; SI-NEXT:    v_bfe_u32 v12, v4, 23, 8
; SI-NEXT:    v_and_b32_e32 v13, s13, v4
; SI-NEXT:    v_ashrrev_i32_e32 v14, 31, v4
; SI-NEXT:    v_bfe_u32 v15, v7, 23, 8
; SI-NEXT:    v_add_i32_e32 v3, vcc, s12, v5
; SI-NEXT:    v_or_b32_e32 v0, s14, v6
; SI-NEXT:    v_sub_i32_e32 v6, vcc, s15, v5
; SI-NEXT:    v_add_i32_e32 v16, vcc, s16, v5
; SI-NEXT:    v_add_i32_e32 v17, vcc, s12, v9
; SI-NEXT:    v_sub_i32_e32 v18, vcc, s15, v9
; SI-NEXT:    v_add_i32_e32 v9, vcc, s16, v9
; SI-NEXT:    v_lshl_b64 v[3:4], v[0:1], v3
; SI-NEXT:    v_lshr_b64 v[5:6], v[0:1], v6
; SI-NEXT:    v_cmp_lt_i32_e32 vcc, 23, v16
; SI-NEXT:    v_cndmask_b32_e32 v19, v6, v4, vcc
; SI-NEXT:    v_cndmask_b32_e32 v20, v5, v3, vcc
; SI-NEXT:    v_add_i32_e32 v21, vcc, s12, v12
; SI-NEXT:    v_sub_i32_e32 v22, vcc, s15, v12
; SI-NEXT:    v_add_i32_e32 v12, vcc, s16, v12
; SI-NEXT:    v_or_b32_e32 v0, s14, v10
; SI-NEXT:    v_lshl_b64 v[3:4], v[0:1], v17
; SI-NEXT:    v_lshr_b64 v[5:6], v[0:1], v18
; SI-NEXT:    v_or_b32_e32 v0, s14, v13
; SI-NEXT:    v_cmp_lt_i32_e32 vcc, 23, v9
; SI-NEXT:    v_cndmask_b32_e32 v10, v6, v4, vcc
; SI-NEXT:    v_cndmask_b32_e32 v13, v5, v3, vcc
; SI-NEXT:    v_lshl_b64 v[3:4], v[0:1], v21
; SI-NEXT:    v_lshr_b64 v[5:6], v[0:1], v22
; SI-NEXT:    v_cmp_lt_i32_e32 vcc, 23, v12
; SI-NEXT:    v_cndmask_b32_e32 v6, v6, v4, vcc
; SI-NEXT:    v_cndmask_b32_e32 v5, v5, v3, vcc
; SI-NEXT:    v_and_b32_e32 v0, s13, v7
; SI-NEXT:    v_ashrrev_i32_e32 v7, 31, v7
; SI-NEXT:    s_lshl_b64 s[0:1], s[2:3], s18
; SI-NEXT:    s_lshr_b64 s[18:19], s[2:3], s19
; SI-NEXT:    v_add_i32_e32 v3, vcc, s12, v15
; SI-NEXT:    v_sub_i32_e32 v17, vcc, s15, v15
; SI-NEXT:    v_add_i32_e32 v15, vcc, s16, v15
; SI-NEXT:    s_cmp_gt_i32 s20, 23
; SI-NEXT:    v_or_b32_e32 v0, s14, v0
; SI-NEXT:    v_lshl_b64 v[3:4], v[0:1], v3
; SI-NEXT:    v_lshr_b64 v[0:1], v[0:1], v17
; SI-NEXT:    v_cmp_lt_i32_e32 vcc, 23, v15
; SI-NEXT:    v_cndmask_b32_e32 v1, v1, v4, vcc
; SI-NEXT:    v_cndmask_b32_e32 v0, v0, v3, vcc
; SI-NEXT:    v_mov_b32_e32 v3, s19
; SI-NEXT:    v_mov_b32_e32 v4, s1
; SI-NEXT:    v_mov_b32_e32 v17, s18
; SI-NEXT:    s_cselect_b64 vcc, -1, 0
; SI-NEXT:    v_cndmask_b32_e32 v3, v3, v4, vcc
; SI-NEXT:    v_mov_b32_e32 v4, s0
; SI-NEXT:    v_cndmask_b32_e32 v4, v17, v4, vcc
; SI-NEXT:    v_ashrrev_i32_e32 v17, 31, v8
; SI-NEXT:    v_xor_b32_e32 v18, v20, v8
; SI-NEXT:    v_xor_b32_e32 v19, v19, v17
; SI-NEXT:    v_sub_i32_e32 v8, vcc, v18, v8
; SI-NEXT:    v_ashrrev_i32_e32 v18, 31, v11
; SI-NEXT:    s_ashr_i32 s0, s9, 31
; SI-NEXT:    s_ashr_i32 s1, s0, 31
; SI-NEXT:    v_xor_b32_e32 v4, s0, v4
; SI-NEXT:    v_xor_b32_e32 v3, s1, v3
; SI-NEXT:    v_subb_u32_e32 v17, vcc, v19, v17, vcc
; SI-NEXT:    v_mov_b32_e32 v19, s1
; SI-NEXT:    v_subrev_i32_e32 v4, vcc, s0, v4
; SI-NEXT:    v_subb_u32_e32 v3, vcc, v3, v19, vcc
; SI-NEXT:    v_ashrrev_i32_e32 v19, 31, v14
; SI-NEXT:    v_cmp_gt_i32_e32 vcc, 0, v16
; SI-NEXT:    v_ashrrev_i32_e32 v16, 31, v7
; SI-NEXT:    s_cmp_lt_i32 s20, 0
; SI-NEXT:    v_xor_b32_e32 v13, v13, v11
; SI-NEXT:    v_xor_b32_e32 v10, v10, v18
; SI-NEXT:    s_cselect_b64 s[18:19], -1, 0
; SI-NEXT:    v_cndmask_b32_e64 v8, v8, 0, vcc
; SI-NEXT:    s_bfe_u32 s20, s8, 0x80017
; SI-NEXT:    s_and_b32 s2, s8, s13
; SI-NEXT:    v_sub_i32_e64 v11, s[0:1], v13, v11
; SI-NEXT:    v_subb_u32_e64 v10, s[0:1], v10, v18, s[0:1]
; SI-NEXT:    v_cndmask_b32_e64 v13, v17, 0, vcc
; SI-NEXT:    v_xor_b32_e32 v5, v5, v14
; SI-NEXT:    v_xor_b32_e32 v6, v6, v19
; SI-NEXT:    v_cndmask_b32_e64 v4, v4, 0, s[18:19]
; SI-NEXT:    s_add_i32 s0, s20, s12
; SI-NEXT:    s_or_b32 s2, s2, s14
; SI-NEXT:    s_sub_i32 s1, s15, s20
; SI-NEXT:    s_add_i32 s22, s20, s16
; SI-NEXT:    v_cmp_gt_i32_e32 vcc, 0, v9
; SI-NEXT:    v_cndmask_b32_e64 v9, v11, 0, vcc
; SI-NEXT:    v_cndmask_b32_e64 v3, v3, 0, s[18:19]
; SI-NEXT:    v_xor_b32_e32 v11, s17, v13
; SI-NEXT:    v_cndmask_b32_e64 v10, v10, 0, vcc
; SI-NEXT:    v_sub_i32_e32 v13, vcc, v5, v14
; SI-NEXT:    v_subb_u32_e32 v14, vcc, v6, v19, vcc
; SI-NEXT:    v_xor_b32_e32 v0, v0, v7
; SI-NEXT:    v_xor_b32_e32 v1, v1, v16
; SI-NEXT:    v_cmp_lt_f32_e32 vcc, s9, v2
; SI-NEXT:    v_cndmask_b32_e32 v5, v8, v4, vcc
; SI-NEXT:    s_lshl_b64 s[18:19], s[2:3], s0
; SI-NEXT:    s_lshr_b64 s[20:21], s[2:3], s1
; SI-NEXT:    v_cndmask_b32_e32 v6, v11, v3, vcc
; SI-NEXT:    v_xor_b32_e32 v4, s17, v10
; SI-NEXT:    v_cmp_gt_i32_e32 vcc, 0, v12
; SI-NEXT:    v_cndmask_b32_e64 v8, v13, 0, vcc
; SI-NEXT:    v_sub_i32_e64 v0, s[0:1], v0, v7
; SI-NEXT:    v_subb_u32_e64 v1, s[0:1], v1, v16, s[0:1]
; SI-NEXT:    v_cndmask_b32_e64 v3, v14, 0, vcc
; SI-NEXT:    s_cmp_gt_i32 s22, 23
; SI-NEXT:    v_mov_b32_e32 v7, s21
; SI-NEXT:    v_mov_b32_e32 v10, s19
; SI-NEXT:    v_mov_b32_e32 v11, s20
; SI-NEXT:    v_mov_b32_e32 v12, s18
; SI-NEXT:    v_cmp_gt_i32_e32 vcc, 0, v15
; SI-NEXT:    v_cndmask_b32_e64 v0, v0, 0, vcc
; SI-NEXT:    v_xor_b32_e32 v13, s17, v3
; SI-NEXT:    v_cndmask_b32_e64 v1, v1, 0, vcc
; SI-NEXT:    s_cselect_b64 vcc, -1, 0
; SI-NEXT:    v_cndmask_b32_e32 v3, v7, v10, vcc
; SI-NEXT:    s_ashr_i32 s0, s8, 31
; SI-NEXT:    v_xor_b32_e32 v1, s17, v1
; SI-NEXT:    v_cndmask_b32_e32 v7, v11, v12, vcc
; SI-NEXT:    s_ashr_i32 s1, s0, 31
; SI-NEXT:    v_xor_b32_e32 v7, s0, v7
; SI-NEXT:    v_xor_b32_e32 v3, s1, v3
; SI-NEXT:    v_mov_b32_e32 v10, s1
; SI-NEXT:    s_cmp_lt_i32 s22, 0
; SI-NEXT:    v_subrev_i32_e32 v7, vcc, s0, v7
; SI-NEXT:    v_subb_u32_e32 v3, vcc, v3, v10, vcc
; SI-NEXT:    s_cselect_b64 s[0:1], -1, 0
; SI-NEXT:    s_bfe_u32 s9, s11, 0x80017
; SI-NEXT:    s_and_b32 s2, s11, s13
; SI-NEXT:    v_cndmask_b32_e64 v7, v7, 0, s[0:1]
; SI-NEXT:    v_cndmask_b32_e64 v10, v3, 0, s[0:1]
; SI-NEXT:    s_add_i32 s0, s9, s12
; SI-NEXT:    s_or_b32 s2, s2, s14
; SI-NEXT:    s_sub_i32 s17, s15, s9
; SI-NEXT:    s_add_i32 s18, s9, s16
; SI-NEXT:    v_cmp_lt_f32_e32 vcc, s8, v2
; SI-NEXT:    v_cndmask_b32_e32 v3, v9, v7, vcc
; SI-NEXT:    v_cndmask_b32_e32 v4, v4, v10, vcc
; SI-NEXT:    s_lshl_b64 s[0:1], s[2:3], s0
; SI-NEXT:    s_lshr_b64 s[8:9], s[2:3], s17
; SI-NEXT:    s_cmp_gt_i32 s18, 23
; SI-NEXT:    v_mov_b32_e32 v7, s9
; SI-NEXT:    v_mov_b32_e32 v9, s1
; SI-NEXT:    v_mov_b32_e32 v10, s8
; SI-NEXT:    v_mov_b32_e32 v11, s0
; SI-NEXT:    s_cselect_b64 vcc, -1, 0
; SI-NEXT:    v_cndmask_b32_e32 v7, v7, v9, vcc
; SI-NEXT:    s_ashr_i32 s0, s11, 31
; SI-NEXT:    v_cndmask_b32_e32 v9, v10, v11, vcc
; SI-NEXT:    s_ashr_i32 s1, s0, 31
; SI-NEXT:    v_xor_b32_e32 v9, s0, v9
; SI-NEXT:    v_xor_b32_e32 v7, s1, v7
; SI-NEXT:    v_mov_b32_e32 v10, s1
; SI-NEXT:    s_cmp_lt_i32 s18, 0
; SI-NEXT:    v_subrev_i32_e32 v9, vcc, s0, v9
; SI-NEXT:    v_subb_u32_e32 v7, vcc, v7, v10, vcc
; SI-NEXT:    s_cselect_b64 s[0:1], -1, 0
; SI-NEXT:    s_bfe_u32 s8, s10, 0x80017
; SI-NEXT:    s_and_b32 s2, s10, s13
; SI-NEXT:    v_cndmask_b32_e64 v9, v9, 0, s[0:1]
; SI-NEXT:    s_add_i32 s9, s8, s12
; SI-NEXT:    s_or_b32 s2, s2, s14
; SI-NEXT:    s_sub_i32 s12, s15, s8
; SI-NEXT:    s_add_i32 s8, s8, s16
; SI-NEXT:    v_cndmask_b32_e64 v7, v7, 0, s[0:1]
; SI-NEXT:    v_cmp_lt_f32_e32 vcc, s11, v2
; SI-NEXT:    v_cndmask_b32_e32 v9, v8, v9, vcc
; SI-NEXT:    s_lshl_b64 s[0:1], s[2:3], s9
; SI-NEXT:    s_lshr_b64 s[2:3], s[2:3], s12
; SI-NEXT:    v_cndmask_b32_e32 v10, v13, v7, vcc
; SI-NEXT:    s_cmp_gt_i32 s8, 23
; SI-NEXT:    v_mov_b32_e32 v7, s3
; SI-NEXT:    v_mov_b32_e32 v8, s1
; SI-NEXT:    v_mov_b32_e32 v11, s2
; SI-NEXT:    v_mov_b32_e32 v12, s0
; SI-NEXT:    s_cselect_b64 vcc, -1, 0
; SI-NEXT:    v_cndmask_b32_e32 v7, v7, v8, vcc
; SI-NEXT:    s_ashr_i32 s0, s10, 31
; SI-NEXT:    v_cndmask_b32_e32 v8, v11, v12, vcc
; SI-NEXT:    s_ashr_i32 s1, s0, 31
; SI-NEXT:    v_xor_b32_e32 v8, s0, v8
; SI-NEXT:    v_xor_b32_e32 v7, s1, v7
; SI-NEXT:    v_mov_b32_e32 v11, s1
; SI-NEXT:    s_cmp_lt_i32 s8, 0
; SI-NEXT:    v_subrev_i32_e32 v8, vcc, s0, v8
; SI-NEXT:    v_subb_u32_e32 v7, vcc, v7, v11, vcc
; SI-NEXT:    s_cselect_b64 s[0:1], -1, 0
; SI-NEXT:    v_cndmask_b32_e64 v8, v8, 0, s[0:1]
; SI-NEXT:    v_cndmask_b32_e64 v11, v7, 0, s[0:1]
; SI-NEXT:    v_cmp_lt_f32_e32 vcc, s10, v2
; SI-NEXT:    v_cndmask_b32_e32 v7, v0, v8, vcc
; SI-NEXT:    v_cndmask_b32_e32 v8, v1, v11, vcc
; SI-NEXT:    buffer_store_dwordx4 v[7:10], off, s[4:7], 0 offset:16
; SI-NEXT:    buffer_store_dwordx4 v[3:6], off, s[4:7], 0
; SI-NEXT:    s_endpgm
;
; VI-LABEL: fp_to_uint_v4f32_to_v4i64:
; VI:       ; %bb.0:
; VI-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x34
; VI-NEXT:    s_load_dwordx2 s[8:9], s[0:1], 0x24
; VI-NEXT:    s_mov_b32 s15, 0x7fffff
; VI-NEXT:    s_movk_i32 s14, 0xff6a
; VI-NEXT:    s_mov_b32 s16, 0x800000
; VI-NEXT:    s_waitcnt lgkmcnt(0)
; VI-NEXT:    s_bfe_u32 s19, s5, 0x80017
; VI-NEXT:    s_and_b32 s1, s5, s15
; VI-NEXT:    s_movk_i32 s17, 0x96
; VI-NEXT:    s_add_i32 s0, s19, s14
; VI-NEXT:    s_or_b32 s12, s1, s16
; VI-NEXT:    s_mov_b32 s13, 0
; VI-NEXT:    s_sub_i32 s2, s17, s19
; VI-NEXT:    s_movk_i32 s18, 0xff81
; VI-NEXT:    s_lshl_b64 s[0:1], s[12:13], s0
; VI-NEXT:    s_lshr_b64 s[2:3], s[12:13], s2
; VI-NEXT:    s_add_i32 s19, s19, s18
; VI-NEXT:    s_cmp_gt_i32 s19, 23
; VI-NEXT:    v_mov_b32_e32 v0, s3
; VI-NEXT:    v_mov_b32_e32 v1, s1
; VI-NEXT:    s_cselect_b64 vcc, -1, 0
; VI-NEXT:    v_cndmask_b32_e32 v0, v0, v1, vcc
; VI-NEXT:    v_mov_b32_e32 v1, s2
; VI-NEXT:    v_mov_b32_e32 v2, s0
; VI-NEXT:    s_ashr_i32 s0, s5, 31
; VI-NEXT:    v_cndmask_b32_e32 v1, v1, v2, vcc
; VI-NEXT:    s_ashr_i32 s1, s0, 31
; VI-NEXT:    v_xor_b32_e32 v1, s0, v1
; VI-NEXT:    s_cmp_lt_i32 s19, 0
; VI-NEXT:    v_mov_b32_e32 v6, 0x5f000000
; VI-NEXT:    v_subrev_u32_e32 v1, vcc, s0, v1
; VI-NEXT:    s_cselect_b64 s[20:21], -1, 0
; VI-NEXT:    v_sub_f32_e32 v9, s5, v6
; VI-NEXT:    v_xor_b32_e32 v0, s1, v0
; VI-NEXT:    v_mov_b32_e32 v2, s1
; VI-NEXT:    v_cndmask_b32_e64 v8, v1, 0, s[20:21]
; VI-NEXT:    v_bfe_u32 v10, v9, 23, 8
; VI-NEXT:    v_and_b32_e32 v1, s15, v9
; VI-NEXT:    v_subb_u32_e32 v7, vcc, v0, v2, vcc
; VI-NEXT:    v_mov_b32_e32 v5, 0
; VI-NEXT:    v_add_u32_e32 v0, vcc, s14, v10
; VI-NEXT:    v_or_b32_e32 v4, s16, v1
; VI-NEXT:    v_sub_u32_e32 v2, vcc, s17, v10
; VI-NEXT:    v_lshlrev_b64 v[0:1], v0, v[4:5]
; VI-NEXT:    v_lshrrev_b64 v[2:3], v2, v[4:5]
; VI-NEXT:    v_add_u32_e32 v4, vcc, s18, v10
; VI-NEXT:    v_cmp_lt_i32_e32 vcc, 23, v4
; VI-NEXT:    v_cmp_lt_f32_e64 s[2:3], s5, v6
; VI-NEXT:    s_bfe_u32 s5, s4, 0x80017
; VI-NEXT:    s_and_b32 s12, s4, s15
; VI-NEXT:    v_cndmask_b32_e32 v0, v2, v0, vcc
; VI-NEXT:    v_ashrrev_i32_e32 v2, 31, v9
; VI-NEXT:    s_add_i32 s19, s5, s14
; VI-NEXT:    s_or_b32 s12, s12, s16
; VI-NEXT:    v_cndmask_b32_e32 v1, v3, v1, vcc
; VI-NEXT:    v_ashrrev_i32_e32 v3, 31, v2
; VI-NEXT:    v_xor_b32_e32 v0, v0, v2
; VI-NEXT:    s_lshl_b64 s[22:23], s[12:13], s19
; VI-NEXT:    s_sub_i32 s19, s17, s5
; VI-NEXT:    v_xor_b32_e32 v1, v1, v3
; VI-NEXT:    v_sub_u32_e32 v0, vcc, v0, v2
; VI-NEXT:    v_cmp_gt_i32_e64 s[0:1], 0, v4
; VI-NEXT:    s_lshr_b64 s[24:25], s[12:13], s19
; VI-NEXT:    s_add_i32 s5, s5, s18
; VI-NEXT:    v_subb_u32_e32 v9, vcc, v1, v3, vcc
; VI-NEXT:    v_cndmask_b32_e64 v0, v0, 0, s[0:1]
; VI-NEXT:    s_cmp_gt_i32 s5, 23
; VI-NEXT:    v_cndmask_b32_e64 v2, v0, v8, s[2:3]
; VI-NEXT:    v_mov_b32_e32 v0, s25
; VI-NEXT:    v_mov_b32_e32 v1, s23
; VI-NEXT:    s_cselect_b64 vcc, -1, 0
; VI-NEXT:    v_cndmask_b32_e32 v0, v0, v1, vcc
; VI-NEXT:    v_mov_b32_e32 v1, s24
; VI-NEXT:    v_mov_b32_e32 v3, s22
; VI-NEXT:    s_ashr_i32 s12, s4, 31
; VI-NEXT:    v_cndmask_b32_e32 v1, v1, v3, vcc
; VI-NEXT:    s_ashr_i32 s19, s12, 31
; VI-NEXT:    v_xor_b32_e32 v1, s12, v1
; VI-NEXT:    s_cmp_lt_i32 s5, 0
; VI-NEXT:    v_subrev_u32_e32 v1, vcc, s12, v1
; VI-NEXT:    s_cselect_b64 s[22:23], -1, 0
; VI-NEXT:    v_sub_f32_e32 v11, s4, v6
; VI-NEXT:    v_xor_b32_e32 v0, s19, v0
; VI-NEXT:    v_mov_b32_e32 v3, s19
; VI-NEXT:    v_cndmask_b32_e64 v10, v1, 0, s[22:23]
; VI-NEXT:    v_bfe_u32 v12, v11, 23, 8
; VI-NEXT:    v_and_b32_e32 v1, s15, v11
; VI-NEXT:    v_subb_u32_e32 v8, vcc, v0, v3, vcc
; VI-NEXT:    v_add_u32_e32 v0, vcc, s14, v12
; VI-NEXT:    v_or_b32_e32 v4, s16, v1
; VI-NEXT:    v_sub_u32_e32 v3, vcc, s17, v12
; VI-NEXT:    v_lshlrev_b64 v[0:1], v0, v[4:5]
; VI-NEXT:    v_lshrrev_b64 v[3:4], v3, v[4:5]
; VI-NEXT:    v_add_u32_e32 v12, vcc, s18, v12
; VI-NEXT:    v_cmp_lt_i32_e32 vcc, 23, v12
; VI-NEXT:    v_cndmask_b32_e32 v0, v3, v0, vcc
; VI-NEXT:    v_ashrrev_i32_e32 v3, 31, v11
; VI-NEXT:    v_cndmask_b32_e32 v1, v4, v1, vcc
; VI-NEXT:    v_ashrrev_i32_e32 v4, 31, v3
; VI-NEXT:    v_xor_b32_e32 v0, v0, v3
; VI-NEXT:    v_xor_b32_e32 v1, v1, v4
; VI-NEXT:    v_sub_u32_e32 v0, vcc, v0, v3
; VI-NEXT:    v_subb_u32_e32 v1, vcc, v1, v4, vcc
; VI-NEXT:    v_cmp_gt_i32_e32 vcc, 0, v12
; VI-NEXT:    v_cndmask_b32_e64 v4, v9, 0, s[0:1]
; VI-NEXT:    s_brev_b32 s19, 1
; VI-NEXT:    v_cndmask_b32_e64 v3, v7, 0, s[20:21]
; VI-NEXT:    v_xor_b32_e32 v4, s19, v4
; VI-NEXT:    v_cndmask_b32_e64 v1, v1, 0, vcc
; VI-NEXT:    v_cndmask_b32_e64 v0, v0, 0, vcc
; VI-NEXT:    v_cmp_lt_f32_e64 s[4:5], s4, v6
; VI-NEXT:    v_cndmask_b32_e64 v3, v4, v3, s[2:3]
; VI-NEXT:    v_cndmask_b32_e64 v4, v8, 0, s[22:23]
; VI-NEXT:    v_xor_b32_e32 v1, s19, v1
; VI-NEXT:    v_cndmask_b32_e64 v0, v0, v10, s[4:5]
; VI-NEXT:    v_cndmask_b32_e64 v1, v1, v4, s[4:5]
; VI-NEXT:    s_bfe_u32 s4, s7, 0x80017
; VI-NEXT:    s_and_b32 s1, s7, s15
; VI-NEXT:    s_add_i32 s0, s4, s14
; VI-NEXT:    s_or_b32 s12, s1, s16
; VI-NEXT:    s_sub_i32 s2, s17, s4
; VI-NEXT:    s_lshl_b64 s[0:1], s[12:13], s0
; VI-NEXT:    s_lshr_b64 s[2:3], s[12:13], s2
; VI-NEXT:    s_add_i32 s4, s4, s18
; VI-NEXT:    s_cmp_gt_i32 s4, 23
; VI-NEXT:    v_mov_b32_e32 v4, s3
; VI-NEXT:    v_mov_b32_e32 v7, s1
; VI-NEXT:    s_cselect_b64 vcc, -1, 0
; VI-NEXT:    v_cndmask_b32_e32 v4, v4, v7, vcc
; VI-NEXT:    v_mov_b32_e32 v7, s2
; VI-NEXT:    v_mov_b32_e32 v8, s0
; VI-NEXT:    v_cndmask_b32_e32 v7, v7, v8, vcc
; VI-NEXT:    s_ashr_i32 s0, s7, 31
; VI-NEXT:    s_ashr_i32 s1, s0, 31
; VI-NEXT:    v_xor_b32_e32 v7, s0, v7
; VI-NEXT:    v_xor_b32_e32 v4, s1, v4
; VI-NEXT:    v_mov_b32_e32 v8, s1
; VI-NEXT:    v_subrev_u32_e32 v7, vcc, s0, v7
; VI-NEXT:    s_cmp_lt_i32 s4, 0
; VI-NEXT:    v_sub_f32_e32 v13, s7, v6
; VI-NEXT:    v_subb_u32_e32 v11, vcc, v4, v8, vcc
; VI-NEXT:    s_cselect_b64 s[20:21], -1, 0
; VI-NEXT:    v_bfe_u32 v14, v13, 23, 8
; VI-NEXT:    v_and_b32_e32 v4, s15, v13
; VI-NEXT:    v_cndmask_b32_e64 v12, v7, 0, s[20:21]
; VI-NEXT:    v_add_u32_e32 v7, vcc, s14, v14
; VI-NEXT:    v_or_b32_e32 v4, s16, v4
; VI-NEXT:    v_sub_u32_e32 v9, vcc, s17, v14
; VI-NEXT:    v_lshlrev_b64 v[7:8], v7, v[4:5]
; VI-NEXT:    v_lshrrev_b64 v[9:10], v9, v[4:5]
; VI-NEXT:    v_add_u32_e32 v4, vcc, s18, v14
; VI-NEXT:    v_cmp_lt_i32_e32 vcc, 23, v4
; VI-NEXT:    v_cndmask_b32_e32 v7, v9, v7, vcc
; VI-NEXT:    v_ashrrev_i32_e32 v9, 31, v13
; VI-NEXT:    v_cmp_lt_f32_e64 s[2:3], s7, v6
; VI-NEXT:    s_bfe_u32 s7, s6, 0x80017
; VI-NEXT:    s_and_b32 s5, s6, s15
; VI-NEXT:    v_cndmask_b32_e32 v8, v10, v8, vcc
; VI-NEXT:    v_ashrrev_i32_e32 v10, 31, v9
; VI-NEXT:    v_xor_b32_e32 v7, v7, v9
; VI-NEXT:    s_add_i32 s4, s7, s14
; VI-NEXT:    s_or_b32 s12, s5, s16
; VI-NEXT:    s_sub_i32 s22, s17, s7
; VI-NEXT:    v_xor_b32_e32 v8, v8, v10
; VI-NEXT:    v_sub_u32_e32 v7, vcc, v7, v9
; VI-NEXT:    v_cmp_gt_i32_e64 s[0:1], 0, v4
; VI-NEXT:    s_lshl_b64 s[4:5], s[12:13], s4
; VI-NEXT:    s_lshr_b64 s[12:13], s[12:13], s22
; VI-NEXT:    s_add_i32 s7, s7, s18
; VI-NEXT:    v_subb_u32_e32 v10, vcc, v8, v10, vcc
; VI-NEXT:    v_cndmask_b32_e64 v4, v7, 0, s[0:1]
; VI-NEXT:    s_cmp_gt_i32 s7, 23
; VI-NEXT:    v_cndmask_b32_e64 v7, v4, v12, s[2:3]
; VI-NEXT:    v_mov_b32_e32 v4, s13
; VI-NEXT:    v_mov_b32_e32 v8, s5
; VI-NEXT:    s_cselect_b64 vcc, -1, 0
; VI-NEXT:    v_cndmask_b32_e32 v4, v4, v8, vcc
; VI-NEXT:    v_mov_b32_e32 v8, s12
; VI-NEXT:    v_mov_b32_e32 v9, s4
; VI-NEXT:    v_cndmask_b32_e32 v8, v8, v9, vcc
; VI-NEXT:    s_ashr_i32 s4, s6, 31
; VI-NEXT:    s_ashr_i32 s5, s4, 31
; VI-NEXT:    v_xor_b32_e32 v8, s4, v8
; VI-NEXT:    v_xor_b32_e32 v4, s5, v4
; VI-NEXT:    v_mov_b32_e32 v9, s5
; VI-NEXT:    v_subrev_u32_e32 v8, vcc, s4, v8
; VI-NEXT:    s_cmp_lt_i32 s7, 0
; VI-NEXT:    v_sub_f32_e32 v14, s6, v6
; VI-NEXT:    v_subb_u32_e32 v12, vcc, v4, v9, vcc
; VI-NEXT:    s_cselect_b64 s[12:13], -1, 0
; VI-NEXT:    v_bfe_u32 v15, v14, 23, 8
; VI-NEXT:    v_and_b32_e32 v4, s15, v14
; VI-NEXT:    v_cndmask_b32_e64 v13, v8, 0, s[12:13]
; VI-NEXT:    v_add_u32_e32 v8, vcc, s14, v15
; VI-NEXT:    v_or_b32_e32 v4, s16, v4
; VI-NEXT:    v_sub_u32_e32 v16, vcc, s17, v15
; VI-NEXT:    v_lshlrev_b64 v[8:9], v8, v[4:5]
; VI-NEXT:    v_lshrrev_b64 v[4:5], v16, v[4:5]
; VI-NEXT:    v_add_u32_e32 v15, vcc, s18, v15
; VI-NEXT:    v_cmp_lt_i32_e32 vcc, 23, v15
; VI-NEXT:    v_cndmask_b32_e32 v4, v4, v8, vcc
; VI-NEXT:    v_ashrrev_i32_e32 v8, 31, v14
; VI-NEXT:    v_cndmask_b32_e32 v5, v5, v9, vcc
; VI-NEXT:    v_ashrrev_i32_e32 v9, 31, v8
; VI-NEXT:    v_xor_b32_e32 v4, v4, v8
; VI-NEXT:    v_xor_b32_e32 v5, v5, v9
; VI-NEXT:    v_sub_u32_e32 v4, vcc, v4, v8
; VI-NEXT:    v_subb_u32_e32 v9, vcc, v5, v9, vcc
; VI-NEXT:    v_cmp_gt_i32_e32 vcc, 0, v15
; VI-NEXT:    v_cndmask_b32_e64 v4, v4, 0, vcc
; VI-NEXT:    v_cmp_lt_f32_e64 s[4:5], s6, v6
; VI-NEXT:    v_cndmask_b32_e64 v6, v10, 0, s[0:1]
; VI-NEXT:    v_cndmask_b32_e64 v5, v4, v13, s[4:5]
; VI-NEXT:    v_cndmask_b32_e64 v4, v11, 0, s[20:21]
; VI-NEXT:    v_xor_b32_e32 v6, s19, v6
; VI-NEXT:    v_cndmask_b32_e64 v8, v6, v4, s[2:3]
; VI-NEXT:    v_cndmask_b32_e64 v6, v9, 0, vcc
; VI-NEXT:    v_cndmask_b32_e64 v4, v12, 0, s[12:13]
; VI-NEXT:    v_xor_b32_e32 v6, s19, v6
; VI-NEXT:    s_mov_b32 s11, 0xf000
; VI-NEXT:    s_mov_b32 s10, -1
; VI-NEXT:    v_cndmask_b32_e64 v6, v6, v4, s[4:5]
; VI-NEXT:    buffer_store_dwordx4 v[5:8], off, s[8:11], 0 offset:16
; VI-NEXT:    buffer_store_dwordx4 v[0:3], off, s[8:11], 0
; VI-NEXT:    s_endpgm
;
; EG-LABEL: fp_to_uint_v4f32_to_v4i64:
; EG:       ; %bb.0:
; EG-NEXT:    ALU 101, @6, KC0[CB0:0-32], KC1[]
; EG-NEXT:    ALU 54, @108, KC0[CB0:0-32], KC1[]
; EG-NEXT:    MEM_RAT_CACHELESS STORE_RAW T4.XYZW, T0.X, 0
; EG-NEXT:    MEM_RAT_CACHELESS STORE_RAW T6.XYZW, T2.X, 1
; EG-NEXT:    CF_END
; EG-NEXT:    PAD
; EG-NEXT:    ALU clause starting at 6:
; EG-NEXT:     MOV * T0.W, literal.x,
; EG-NEXT:    8(1.121039e-44), 0(0.000000e+00)
; EG-NEXT:     BFE_UINT T1.W, KC0[4].X, literal.x, PV.W,
; EG-NEXT:     AND_INT * T2.W, KC0[4].X, literal.y,
; EG-NEXT:    23(3.222986e-44), 8388607(1.175494e-38)
; EG-NEXT:     OR_INT T0.Z, PS, literal.x,
; EG-NEXT:     BFE_UINT T2.W, KC0[3].Z, literal.y, T0.W,
; EG-NEXT:     ADD_INT * T3.W, PV.W, literal.z,
; EG-NEXT:    8388608(1.175494e-38), 23(3.222986e-44)
; EG-NEXT:    -150(nan), 0(0.000000e+00)
; EG-NEXT:     ADD_INT T0.Y, PV.W, literal.x,
; EG-NEXT:     AND_INT T1.Z, PS, literal.y,
; EG-NEXT:     NOT_INT T4.W, PS,
; EG-NEXT:     LSHR * T5.W, PV.Z, 1,
; EG-NEXT:    -127(nan), 31(4.344025e-44)
; EG-NEXT:     ADD_INT T0.X, T1.W, literal.x,
; EG-NEXT:     BIT_ALIGN_INT T1.Y, 0.0, PS, PV.W,
; EG-NEXT:     AND_INT T2.Z, T3.W, literal.y, BS:VEC_201
; EG-NEXT:     LSHL T3.W, T0.Z, PV.Z,
; EG-NEXT:     SUB_INT * T1.W, literal.z, T1.W,
; EG-NEXT:    -127(nan), 32(4.484155e-44)
; EG-NEXT:    150(2.101948e-43), 0(0.000000e+00)
; EG-NEXT:     AND_INT T1.X, PS, literal.x,
; EG-NEXT:     BIT_ALIGN_INT T2.Y, 0.0, T0.Z, PS,
; EG-NEXT:     AND_INT T0.Z, KC0[3].Z, literal.y,
; EG-NEXT:     CNDE_INT T1.W, PV.Z, PV.Y, PV.W,
; EG-NEXT:     SETGT_INT * T4.W, PV.X, literal.z,
; EG-NEXT:    32(4.484155e-44), 8388607(1.175494e-38)
; EG-NEXT:    23(3.222986e-44), 0(0.000000e+00)
; EG-NEXT:     CNDE_INT T2.X, PS, 0.0, PV.W,
; EG-NEXT:     OR_INT T1.Y, PV.Z, literal.x,
; EG-NEXT:     ADD_INT T0.Z, T2.W, literal.y,
; EG-NEXT:     CNDE_INT T1.W, PV.X, PV.Y, 0.0,
; EG-NEXT:     CNDE_INT * T3.W, T2.Z, T3.W, 0.0,
; EG-NEXT:    8388608(1.175494e-38), -150(nan)
; EG-NEXT:     CNDE_INT T1.X, T4.W, PV.W, PS,
; EG-NEXT:     ASHR T2.Y, KC0[4].X, literal.x,
; EG-NEXT:     AND_INT T1.Z, PV.Z, literal.x,
; EG-NEXT:     NOT_INT T1.W, PV.Z,
; EG-NEXT:     LSHR * T3.W, PV.Y, 1,
; EG-NEXT:    31(4.344025e-44), 0(0.000000e+00)
; EG-NEXT:     BIT_ALIGN_INT T3.X, 0.0, PS, PV.W,
; EG-NEXT:     LSHL T3.Y, T1.Y, PV.Z,
; EG-NEXT:     XOR_INT T1.Z, PV.X, PV.Y,
; EG-NEXT:     XOR_INT T1.W, T2.X, PV.Y,
; EG-NEXT:     SUB_INT * T2.W, literal.x, T2.W,
; EG-NEXT:    150(2.101948e-43), 0(0.000000e+00)
; EG-NEXT:     AND_INT T1.X, T0.Z, literal.x,
; EG-NEXT:     AND_INT T4.Y, PS, literal.x,
; EG-NEXT:     BIT_ALIGN_INT T0.Z, 0.0, T1.Y, PS, BS:VEC_021/SCL_122
; EG-NEXT:     SUB_INT T1.W, PV.W, T2.Y,
; EG-NEXT:     SUBB_UINT * T2.W, PV.Z, T2.Y,
; EG-NEXT:    32(4.484155e-44), 0(0.000000e+00)
; EG-NEXT:     SUB_INT T2.X, PV.W, PS,
; EG-NEXT:     CNDE_INT T1.Y, PV.Y, PV.Z, 0.0,
; EG-NEXT:     CNDE_INT T0.Z, PV.X, T3.Y, 0.0,
; EG-NEXT:     CNDE_INT T1.W, PV.X, T3.X, T3.Y, BS:VEC_021/SCL_122
; EG-NEXT:     SETGT_INT * T2.W, T0.Y, literal.x,
; EG-NEXT:    23(3.222986e-44), 0(0.000000e+00)
; EG-NEXT:     BFE_UINT T1.X, KC0[3].W, literal.x, T0.W,
; EG-NEXT:     AND_INT T3.Y, KC0[3].W, literal.y,
; EG-NEXT:     CNDE_INT T2.Z, PS, 0.0, PV.W,
; EG-NEXT:     CNDE_INT T1.W, PS, PV.Y, PV.Z,
; EG-NEXT:     ASHR * T2.W, KC0[3].Z, literal.z,
; EG-NEXT:    23(3.222986e-44), 8388607(1.175494e-38)
; EG-NEXT:    31(4.344025e-44), 0(0.000000e+00)
; EG-NEXT:     BFE_UINT T3.X, KC0[3].Y, literal.x, T0.W,
; EG-NEXT:     XOR_INT T1.Y, PV.W, PS,
; EG-NEXT:     XOR_INT T0.Z, PV.Z, PS,
; EG-NEXT:     OR_INT T0.W, PV.Y, literal.y,
; EG-NEXT:     SUB_INT * T1.W, literal.z, PV.X,
; EG-NEXT:    23(3.222986e-44), 8388608(1.175494e-38)
; EG-NEXT:    150(2.101948e-43), 0(0.000000e+00)
; EG-NEXT:     AND_INT T4.X, KC0[3].Y, literal.x,
; EG-NEXT:     AND_INT T3.Y, PS, literal.y,
; EG-NEXT:     BIT_ALIGN_INT T2.Z, 0.0, PV.W, PS,
; EG-NEXT:     SUB_INT T1.W, PV.Z, T2.W,
; EG-NEXT:     SUBB_UINT * T3.W, PV.Y, T2.W,
; EG-NEXT:    8388607(1.175494e-38), 32(4.484155e-44)
; EG-NEXT:     SUB_INT T5.X, PV.W, PS,
; EG-NEXT:     SETGT_INT T0.Y, 0.0, T0.Y,
; EG-NEXT:     CNDE_INT T0.Z, PV.Y, PV.Z, 0.0,
; EG-NEXT:     OR_INT T1.W, PV.X, literal.x,
; EG-NEXT:     ADD_INT * T3.W, T3.X, literal.y,
; EG-NEXT:    8388608(1.175494e-38), -150(nan)
; EG-NEXT:     ADD_INT T4.X, T3.X, literal.x,
; EG-NEXT:     SUB_INT T3.Y, literal.y, T3.X,
; EG-NEXT:     AND_INT T2.Z, PS, literal.z,
; EG-NEXT:     NOT_INT T4.W, PS,
; EG-NEXT:     LSHR * T5.W, PV.W, 1,
; EG-NEXT:    -127(nan), 150(2.101948e-43)
; EG-NEXT:    31(4.344025e-44), 0(0.000000e+00)
; EG-NEXT:     BIT_ALIGN_INT T3.X, 0.0, PS, PV.W,
; EG-NEXT:     LSHL T4.Y, T1.W, PV.Z,
; EG-NEXT:     AND_INT T2.Z, T3.W, literal.x, BS:VEC_120/SCL_212
; EG-NEXT:     BIT_ALIGN_INT T1.W, 0.0, T1.W, PV.Y, BS:VEC_021/SCL_122
; EG-NEXT:     AND_INT * T3.W, PV.Y, literal.x,
; EG-NEXT:    32(4.484155e-44), 0(0.000000e+00)
; EG-NEXT:     ADD_INT T6.X, T1.X, literal.x,
; EG-NEXT:     CNDE_INT T3.Y, PS, PV.W, 0.0,
; EG-NEXT:     CNDE_INT * T3.Z, PV.Z, PV.Y, 0.0,
; EG-NEXT:    -150(nan), 0(0.000000e+00)
; EG-NEXT:    ALU clause starting at 108:
; EG-NEXT:     CNDE_INT T1.W, T2.Z, T3.X, T4.Y,
; EG-NEXT:     SETGT_INT * T3.W, T4.X, literal.x,
; EG-NEXT:    23(3.222986e-44), 0(0.000000e+00)
; EG-NEXT:     CNDE_INT T3.X, PS, 0.0, PV.W,
; EG-NEXT:     CNDE_INT T3.Y, PS, T3.Y, T3.Z,
; EG-NEXT:     AND_INT T2.Z, T6.X, literal.x,
; EG-NEXT:     NOT_INT T1.W, T6.X,
; EG-NEXT:     LSHR * T3.W, T0.W, 1,
; EG-NEXT:    31(4.344025e-44), 0(0.000000e+00)
; EG-NEXT:     ASHR T7.X, KC0[3].Y, literal.x,
; EG-NEXT:     ADD_INT T4.Y, T1.X, literal.y,
; EG-NEXT:     BIT_ALIGN_INT T3.Z, 0.0, PS, PV.W,
; EG-NEXT:     LSHL T0.W, T0.W, PV.Z,
; EG-NEXT:     AND_INT * T1.W, T6.X, literal.z,
; EG-NEXT:    31(4.344025e-44), -127(nan)
; EG-NEXT:    32(4.484155e-44), 0(0.000000e+00)
; EG-NEXT:     CNDE_INT T1.X, PS, PV.W, 0.0,
; EG-NEXT:     CNDE_INT T5.Y, PS, PV.Z, PV.W,
; EG-NEXT:     SETGT_INT T2.Z, PV.Y, literal.x,
; EG-NEXT:     XOR_INT T0.W, T3.Y, PV.X,
; EG-NEXT:     XOR_INT * T1.W, T3.X, PV.X,
; EG-NEXT:    23(3.222986e-44), 0(0.000000e+00)
; EG-NEXT:     SUB_INT T3.X, PS, T7.X,
; EG-NEXT:     SUBB_UINT T3.Y, PV.W, T7.X,
; EG-NEXT:     CNDE_INT T3.Z, PV.Z, 0.0, PV.Y,
; EG-NEXT:     CNDE_INT T1.W, PV.Z, T0.Z, PV.X,
; EG-NEXT:     ASHR * T3.W, KC0[3].W, literal.x,
; EG-NEXT:    31(4.344025e-44), 0(0.000000e+00)
; EG-NEXT:     XOR_INT T1.X, PV.W, PS,
; EG-NEXT:     XOR_INT T5.Y, PV.Z, PS,
; EG-NEXT:     SUB_INT T0.Z, PV.X, PV.Y,
; EG-NEXT:     SETGT_INT T1.W, 0.0, T4.X, BS:VEC_021/SCL_122
; EG-NEXT:     CNDE_INT * T6.W, T0.Y, T5.X, 0.0,
; EG-NEXT:     SETGT_INT T0.X, 0.0, T0.X,
; EG-NEXT:     CNDE_INT T6.Y, PV.W, PV.Z, 0.0,
; EG-NEXT:     SUB_INT T0.Z, T1.Y, T2.W, BS:VEC_021/SCL_122
; EG-NEXT:     SUB_INT T2.W, PV.Y, T3.W,
; EG-NEXT:     SUBB_UINT * T4.W, PV.X, T3.W,
; EG-NEXT:     SUB_INT T3.X, PV.W, PS,
; EG-NEXT:     SETGT_INT T1.Y, 0.0, T4.Y,
; EG-NEXT:     CNDE_INT T6.Z, T0.Y, PV.Z, 0.0,
; EG-NEXT:     SUB_INT T0.W, T0.W, T7.X, BS:VEC_021/SCL_122
; EG-NEXT:     CNDE_INT * T4.W, PV.X, T2.X, 0.0,
; EG-NEXT:     CNDE_INT T6.X, T1.W, PV.W, 0.0,
; EG-NEXT:     CNDE_INT T4.Y, PV.Y, PV.X, 0.0,
; EG-NEXT:     SUB_INT T0.W, T1.Z, T2.Y,
; EG-NEXT:     LSHR * T2.X, KC0[2].Y, literal.x,
; EG-NEXT:    2(2.802597e-45), 0(0.000000e+00)
; EG-NEXT:     CNDE_INT T4.Z, T0.X, PV.W, 0.0,
; EG-NEXT:     SUB_INT * T0.W, T1.X, T3.W, BS:VEC_120/SCL_212
; EG-NEXT:     CNDE_INT T4.X, T1.Y, PV.W, 0.0,
; EG-NEXT:     ADD_INT * T0.W, KC0[2].Y, literal.x,
; EG-NEXT:    16(2.242078e-44), 0(0.000000e+00)
; EG-NEXT:     LSHR * T0.X, PV.W, literal.x,
; EG-NEXT:    2(2.802597e-45), 0(0.000000e+00)
  %conv = fptoui <4 x float> %x to <4 x i64>
  store <4 x i64> %conv, <4 x i64> addrspace(1)* %out
  ret void
}

define amdgpu_kernel void @fp_to_uint_f32_to_i1(i1 addrspace(1)* %out, float %in) #0 {
; SI-LABEL: fp_to_uint_f32_to_i1:
; SI:       ; %bb.0:
; SI-NEXT:    s_load_dword s4, s[0:1], 0xb
; SI-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x9
; SI-NEXT:    s_mov_b32 s3, 0xf000
; SI-NEXT:    s_mov_b32 s2, -1
; SI-NEXT:    s_waitcnt lgkmcnt(0)
; SI-NEXT:    v_cmp_eq_f32_e64 s[4:5], 1.0, s4
; SI-NEXT:    v_cndmask_b32_e64 v0, 0, 1, s[4:5]
; SI-NEXT:    buffer_store_byte v0, off, s[0:3], 0
; SI-NEXT:    s_endpgm
;
; VI-LABEL: fp_to_uint_f32_to_i1:
; VI:       ; %bb.0:
; VI-NEXT:    s_load_dword s4, s[0:1], 0x2c
; VI-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x24
; VI-NEXT:    s_mov_b32 s3, 0xf000
; VI-NEXT:    s_mov_b32 s2, -1
; VI-NEXT:    s_waitcnt lgkmcnt(0)
; VI-NEXT:    v_cmp_eq_f32_e64 s[4:5], 1.0, s4
; VI-NEXT:    v_cndmask_b32_e64 v0, 0, 1, s[4:5]
; VI-NEXT:    buffer_store_byte v0, off, s[0:3], 0
; VI-NEXT:    s_endpgm
;
; EG-LABEL: fp_to_uint_f32_to_i1:
; EG:       ; %bb.0:
; EG-NEXT:    ALU 12, @4, KC0[CB0:0-32], KC1[]
; EG-NEXT:    MEM_RAT MSKOR T0.XW, T1.X
; EG-NEXT:    CF_END
; EG-NEXT:    PAD
; EG-NEXT:    ALU clause starting at 4:
; EG-NEXT:     AND_INT T0.W, KC0[2].Y, literal.x,
; EG-NEXT:     SETE_DX10 * T1.W, KC0[2].Z, 1.0,
; EG-NEXT:    3(4.203895e-45), 0(0.000000e+00)
; EG-NEXT:     AND_INT T1.W, PS, 1,
; EG-NEXT:     LSHL * T0.W, PV.W, literal.x,
; EG-NEXT:    3(4.203895e-45), 0(0.000000e+00)
; EG-NEXT:     LSHL T0.X, PV.W, PS,
; EG-NEXT:     LSHL * T0.W, literal.x, PS,
; EG-NEXT:    255(3.573311e-43), 0(0.000000e+00)
; EG-NEXT:     MOV T0.Y, 0.0,
; EG-NEXT:     MOV * T0.Z, 0.0,
; EG-NEXT:     LSHR * T1.X, KC0[2].Y, literal.x,
; EG-NEXT:    2(2.802597e-45), 0(0.000000e+00)
  %conv = fptoui float %in to i1
  store i1 %conv, i1 addrspace(1)* %out
  ret void
}

define amdgpu_kernel void @fp_to_uint_fabs_f32_to_i1(i1 addrspace(1)* %out, float %in) #0 {
; SI-LABEL: fp_to_uint_fabs_f32_to_i1:
; SI:       ; %bb.0:
; SI-NEXT:    s_load_dword s4, s[0:1], 0xb
; SI-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x9
; SI-NEXT:    s_mov_b32 s3, 0xf000
; SI-NEXT:    s_mov_b32 s2, -1
; SI-NEXT:    s_waitcnt lgkmcnt(0)
; SI-NEXT:    v_cmp_eq_f32_e64 s[4:5], 1.0, |s4|
; SI-NEXT:    v_cndmask_b32_e64 v0, 0, 1, s[4:5]
; SI-NEXT:    buffer_store_byte v0, off, s[0:3], 0
; SI-NEXT:    s_endpgm
;
; VI-LABEL: fp_to_uint_fabs_f32_to_i1:
; VI:       ; %bb.0:
; VI-NEXT:    s_load_dword s4, s[0:1], 0x2c
; VI-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x24
; VI-NEXT:    s_mov_b32 s3, 0xf000
; VI-NEXT:    s_mov_b32 s2, -1
; VI-NEXT:    s_waitcnt lgkmcnt(0)
; VI-NEXT:    v_cmp_eq_f32_e64 s[4:5], 1.0, |s4|
; VI-NEXT:    v_cndmask_b32_e64 v0, 0, 1, s[4:5]
; VI-NEXT:    buffer_store_byte v0, off, s[0:3], 0
; VI-NEXT:    s_endpgm
;
; EG-LABEL: fp_to_uint_fabs_f32_to_i1:
; EG:       ; %bb.0:
; EG-NEXT:    ALU 12, @4, KC0[CB0:0-32], KC1[]
; EG-NEXT:    MEM_RAT MSKOR T0.XW, T1.X
; EG-NEXT:    CF_END
; EG-NEXT:    PAD
; EG-NEXT:    ALU clause starting at 4:
; EG-NEXT:     AND_INT T0.W, KC0[2].Y, literal.x,
; EG-NEXT:     SETE_DX10 * T1.W, |KC0[2].Z|, 1.0,
; EG-NEXT:    3(4.203895e-45), 0(0.000000e+00)
; EG-NEXT:     AND_INT T1.W, PS, 1,
; EG-NEXT:     LSHL * T0.W, PV.W, literal.x,
; EG-NEXT:    3(4.203895e-45), 0(0.000000e+00)
; EG-NEXT:     LSHL T0.X, PV.W, PS,
; EG-NEXT:     LSHL * T0.W, literal.x, PS,
; EG-NEXT:    255(3.573311e-43), 0(0.000000e+00)
; EG-NEXT:     MOV T0.Y, 0.0,
; EG-NEXT:     MOV * T0.Z, 0.0,
; EG-NEXT:     LSHR * T1.X, KC0[2].Y, literal.x,
; EG-NEXT:    2(2.802597e-45), 0(0.000000e+00)
  %in.fabs = call float @llvm.fabs.f32(float %in)
  %conv = fptoui float %in.fabs to i1
  store i1 %conv, i1 addrspace(1)* %out
  ret void
}

define amdgpu_kernel void @fp_to_uint_f32_to_i16(i16 addrspace(1)* %out, float %in) #0 {
; SI-LABEL: fp_to_uint_f32_to_i16:
; SI:       ; %bb.0:
; SI-NEXT:    s_load_dword s4, s[0:1], 0xb
; SI-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x9
; SI-NEXT:    s_mov_b32 s3, 0xf000
; SI-NEXT:    s_mov_b32 s2, -1
; SI-NEXT:    s_waitcnt lgkmcnt(0)
; SI-NEXT:    v_cvt_u32_f32_e32 v0, s4
; SI-NEXT:    buffer_store_short v0, off, s[0:3], 0
; SI-NEXT:    s_endpgm
;
; VI-LABEL: fp_to_uint_f32_to_i16:
; VI:       ; %bb.0:
; VI-NEXT:    s_load_dword s2, s[0:1], 0x2c
; VI-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x24
; VI-NEXT:    s_mov_b32 s3, 0xf000
; VI-NEXT:    s_waitcnt lgkmcnt(0)
; VI-NEXT:    v_cvt_u32_f32_e32 v0, s2
; VI-NEXT:    s_mov_b32 s2, -1
; VI-NEXT:    buffer_store_short v0, off, s[0:3], 0
; VI-NEXT:    s_endpgm
;
; EG-LABEL: fp_to_uint_f32_to_i16:
; EG:       ; %bb.0:
; EG-NEXT:    ALU 12, @4, KC0[CB0:0-32], KC1[]
; EG-NEXT:    MEM_RAT MSKOR T0.XW, T1.X
; EG-NEXT:    CF_END
; EG-NEXT:    PAD
; EG-NEXT:    ALU clause starting at 4:
; EG-NEXT:     TRUNC T0.W, KC0[2].Z,
; EG-NEXT:     AND_INT * T1.W, KC0[2].Y, literal.x,
; EG-NEXT:    3(4.203895e-45), 0(0.000000e+00)
; EG-NEXT:     LSHL T1.W, PS, literal.x,
; EG-NEXT:     FLT_TO_UINT * T0.X, PV.W,
; EG-NEXT:    3(4.203895e-45), 0(0.000000e+00)
; EG-NEXT:     LSHL T0.X, PS, PV.W,
; EG-NEXT:     LSHL * T0.W, literal.x, PV.W,
; EG-NEXT:    65535(9.183409e-41), 0(0.000000e+00)
; EG-NEXT:     MOV T0.Y, 0.0,
; EG-NEXT:     MOV * T0.Z, 0.0,
; EG-NEXT:     LSHR * T1.X, KC0[2].Y, literal.x,
; EG-NEXT:    2(2.802597e-45), 0(0.000000e+00)
  %uint = fptoui float %in to i16
  store i16 %uint, i16 addrspace(1)* %out
  ret void
}

attributes #0 = { nounwind }
attributes #1 = { nounwind readnone }