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---
include: rocsparse_common.yaml
include: known_bugs.yaml

Definitions:
  - &alpha_beta_range_quick
    - { alpha:   1.0, beta:   1.0, alphai:  1.0, betai: 0.5 }
    - { alpha:  -0.5, beta:   0.0, alphai: -0.5, betai: 1.0 }
    - { alpha:   0.0, beta:   1.0, alphai:  0.0, betai: 1.0 }

  - &alpha_beta_range_checkin
    - { alpha: -99.0, beta:   1.5, alphai:  0.0, betai: 0.3 }
    - { alpha:   2.0, beta: -99.0, alphai:  0.5, betai: 0.3 }
    - { alpha:   3.0, beta:   1.7, alphai: -0.5, betai: 0.8 }

  - &alpha_beta_range_nightly
    - { alpha:  -0.5, beta:  -0.2, alphai:  1.0, betai: 1.9 }

Tests:
- name: spgemm_csr_bad_arg
  category: pre_checkin
  function: spgemm_csr_bad_arg
  indextype: *i32i32_i64i32_i64i64
  precision: *single_double_precisions_complex_real

# C = alpha * A * B
- name: spgemm_mult_csr
  category: quick
  function: spgemm_csr
  indextype: *i32i32_i64i32_i64i64
  precision: *single_double_precisions_complex_real
  M: [50, 647]
  N: [13, 523]
  K: [50, 254]
  alpha_beta: *alpha_beta_range_quick
  transA: [rocsparse_operation_none]
  transB: [rocsparse_operation_none]
  baseA: [rocsparse_index_base_one]
  baseB: [rocsparse_index_base_zero]
  baseC: [rocsparse_index_base_zero]
  matrix: [rocsparse_matrix_random]
  spgemm_alg: [rocsparse_spgemm_alg_default]

- name: spgemm_mult_csr
  category: pre_checkin
  function: spgemm_csr
  indextype: *i32i32_i64i32_i64i64
  precision: *single_double_precisions_complex_real
  M: [0, 1799, 32519]
  N: [0, 3712, 16021]
  K: [0, 1942, 9848]
  alpha_beta: *alpha_beta_range_checkin
  transA: [rocsparse_operation_none]
  transB: [rocsparse_operation_none]
  baseA: [rocsparse_index_base_zero]
  baseB: [rocsparse_index_base_zero]
  baseC: [rocsparse_index_base_one]
  matrix: [rocsparse_matrix_random]
  spgemm_alg: [rocsparse_spgemm_alg_default]

- name: spgemm_mult_csr
  category: nightly
  function: spgemm_csr
  indextype: *i32i32_i64i32_i64i64
  precision: *single_double_precisions_complex_real
  M: [73923, 842323]
  N: [5239, 1492312]
  K: [442, 743434]
  alpha_beta: *alpha_beta_range_nightly
  transA: [rocsparse_operation_none]
  transB: [rocsparse_operation_none]
  baseA: [rocsparse_index_base_zero]
  baseB: [rocsparse_index_base_zero]
  baseC: [rocsparse_index_base_zero]
  matrix: [rocsparse_matrix_random]
  spgemm_alg: [rocsparse_spgemm_alg_default]

- name: spgemm_mult_csr_file
  category: quick
  function: spgemm_csr
  indextype: *i32i32_i64i32_i64i64
  precision: *single_double_precisions
  M: 1
  N: [13, 523]
  K: 1
  alpha_beta: *alpha_beta_range_quick
  transA: [rocsparse_operation_none]
  transB: [rocsparse_operation_none]
  baseA: [rocsparse_index_base_one]
  baseB: [rocsparse_index_base_zero]
  baseC: [rocsparse_index_base_one]
  matrix: [rocsparse_matrix_file_rocalution]
  spgemm_alg: [rocsparse_spgemm_alg_default]
  filename: [mac_econ_fwd500,
             nos2,
             nos6,
             scircuit]

- name: spgemm_mult_csr_file
  category: pre_checkin
  function: spgemm_csr
  indextype: *i32i32_i64i32_i64i64
  precision: *single_double_precisions
  M: 1
  N: [0, 3712, 16021]
  K: 1
  alpha_beta: *alpha_beta_range_checkin
  transA: [rocsparse_operation_none]
  transB: [rocsparse_operation_none]
  baseA: [rocsparse_index_base_zero]
  baseB: [rocsparse_index_base_one]
  baseC: [rocsparse_index_base_one]
  matrix: [rocsparse_matrix_file_rocalution]
  spgemm_alg: [rocsparse_spgemm_alg_default]
  filename: [rma10,
             mc2depi,
             ASIC_320k,
             nos1,
             nos7]

- name: spgemm_mult_csr_file
  category: nightly
  function: spgemm_csr
  indextype: *i32i32_i64i32_i64i64
  precision: *single_double_precisions
  M: 1
  N: [5239, 1492312]
  K: 1
  alpha_beta: *alpha_beta_range_nightly
  transA: [rocsparse_operation_none]
  transB: [rocsparse_operation_none]
  baseA: [rocsparse_index_base_zero]
  baseB: [rocsparse_index_base_zero]
  baseC: [rocsparse_index_base_zero]
  matrix: [rocsparse_matrix_file_rocalution]
  spgemm_alg: [rocsparse_spgemm_alg_default]
  filename: [bibd_22_8,
             bmwcra_1,
             amazon0312,
             Chebyshev4,
             sme3Dc,
             webbase-1M,
             shipsec1]

- name: spgemm_mult_csr_file
  category: quick
  function: spgemm_csr
  indextype: *i32i32_i64i32_i64i64
  precision: *single_double_precisions_complex
  M: 1
  N: [21, 719]
  K: 1
  alpha_beta: *alpha_beta_range_quick
  transA: [rocsparse_operation_none]
  transB: [rocsparse_operation_none]
  baseA: [rocsparse_index_base_one]
  baseB: [rocsparse_index_base_one]
  baseC: [rocsparse_index_base_one]
  matrix: [rocsparse_matrix_file_rocalution]
  spgemm_alg: [rocsparse_spgemm_alg_default]
  filename: [qc2534,
             Chevron2]

- name: spgemm_mult_csr_file
  category: pre_checkin
  function: spgemm_csr
  indextype: *i32i32_i64i32_i64i64
  precision: *single_double_precisions_complex
  M: 1
  N: [0, 5925, 20142]
  K: 1
  alpha_beta: *alpha_beta_range_checkin
  transA: [rocsparse_operation_none]
  transB: [rocsparse_operation_none]
  baseA: [rocsparse_index_base_one]
  baseB: [rocsparse_index_base_zero]
  baseC: [rocsparse_index_base_one]
  matrix: [rocsparse_matrix_file_rocalution]
  spgemm_alg: [rocsparse_spgemm_alg_default]
  filename: [mplate,
             Chevron3]

- name: spgemm_mult_csr_file
  category: nightly
  function: spgemm_csr
  indextype: *i32i32_i64i32_i64i64
  precision: *single_double_precisions_complex
  M: 1
  N: [4823, 901923]
  K: 1
  alpha_beta: *alpha_beta_range_nightly
  transA: [rocsparse_operation_none]
  transB: [rocsparse_operation_none]
  baseA: [rocsparse_index_base_zero]
  baseB: [rocsparse_index_base_zero]
  baseC: [rocsparse_index_base_zero]
  matrix: [rocsparse_matrix_file_rocalution]
  spgemm_alg: [rocsparse_spgemm_alg_default]
  filename: [Chevron4]
