static struct umr_bitfield ixATTR00[] = {
	 { "ATTR_PAL", 0, 5, &umr_bitfield_default },
};
static struct umr_bitfield ixATTR01[] = {
	 { "ATTR_PAL", 0, 5, &umr_bitfield_default },
};
static struct umr_bitfield ixATTR02[] = {
	 { "ATTR_PAL", 0, 5, &umr_bitfield_default },
};
static struct umr_bitfield ixATTR03[] = {
	 { "ATTR_PAL", 0, 5, &umr_bitfield_default },
};
static struct umr_bitfield ixATTR04[] = {
	 { "ATTR_PAL", 0, 5, &umr_bitfield_default },
};
static struct umr_bitfield ixATTR05[] = {
	 { "ATTR_PAL", 0, 5, &umr_bitfield_default },
};
static struct umr_bitfield ixATTR06[] = {
	 { "ATTR_PAL", 0, 5, &umr_bitfield_default },
};
static struct umr_bitfield ixATTR07[] = {
	 { "ATTR_PAL", 0, 5, &umr_bitfield_default },
};
static struct umr_bitfield ixATTR08[] = {
	 { "ATTR_PAL", 0, 5, &umr_bitfield_default },
};
static struct umr_bitfield ixATTR09[] = {
	 { "ATTR_PAL", 0, 5, &umr_bitfield_default },
};
static struct umr_bitfield ixATTR0A[] = {
	 { "ATTR_PAL", 0, 5, &umr_bitfield_default },
};
static struct umr_bitfield ixATTR0B[] = {
	 { "ATTR_PAL", 0, 5, &umr_bitfield_default },
};
static struct umr_bitfield ixATTR0C[] = {
	 { "ATTR_PAL", 0, 5, &umr_bitfield_default },
};
static struct umr_bitfield ixATTR0D[] = {
	 { "ATTR_PAL", 0, 5, &umr_bitfield_default },
};
static struct umr_bitfield ixATTR0E[] = {
	 { "ATTR_PAL", 0, 5, &umr_bitfield_default },
};
static struct umr_bitfield ixATTR0F[] = {
	 { "ATTR_PAL", 0, 5, &umr_bitfield_default },
};
static struct umr_bitfield ixATTR10[] = {
	 { "ATTR_BLINK_EN", 3, 3, &umr_bitfield_default },
	 { "ATTR_CSEL_EN", 7, 7, &umr_bitfield_default },
	 { "ATTR_GRPH_MODE", 0, 0, &umr_bitfield_default },
	 { "ATTR_LGRPH_EN", 2, 2, &umr_bitfield_default },
	 { "ATTR_MONO_EN", 1, 1, &umr_bitfield_default },
	 { "ATTR_PANTOPONLY", 5, 5, &umr_bitfield_default },
	 { "ATTR_PCLKBY2", 6, 6, &umr_bitfield_default },
};
static struct umr_bitfield ixATTR11[] = {
	 { "ATTR_OVSC", 0, 7, &umr_bitfield_default },
};
static struct umr_bitfield ixATTR12[] = {
	 { "ATTR_MAP_EN", 0, 3, &umr_bitfield_default },
	 { "ATTR_VSMUX", 4, 5, &umr_bitfield_default },
};
static struct umr_bitfield ixATTR13[] = {
	 { "ATTR_PPAN", 0, 3, &umr_bitfield_default },
};
static struct umr_bitfield ixATTR14[] = {
	 { "ATTR_CSEL1", 0, 1, &umr_bitfield_default },
	 { "ATTR_CSEL2", 2, 3, &umr_bitfield_default },
};
static struct umr_bitfield ixCRT15[] = {
	 { "V_BLANK_START", 0, 7, &umr_bitfield_default },
};
static struct umr_bitfield ixCRT16[] = {
	 { "V_BLANK_END", 0, 7, &umr_bitfield_default },
};
static struct umr_bitfield ixCRT17[] = {
	 { "ADDR_CNT_BY2", 3, 3, &umr_bitfield_default },
	 { "BYTE_MODE", 6, 6, &umr_bitfield_default },
	 { "CRTC_SYNC_EN", 7, 7, &umr_bitfield_default },
	 { "RA0_AS_A13B", 0, 0, &umr_bitfield_default },
	 { "RA1_AS_A14B", 1, 1, &umr_bitfield_default },
	 { "VCOUNT_BY2", 2, 2, &umr_bitfield_default },
	 { "WRAP_A15TOA0", 5, 5, &umr_bitfield_default },
};
static struct umr_bitfield ixCRT18[] = {
	 { "LINE_CMP", 0, 7, &umr_bitfield_default },
};
static struct umr_bitfield ixCRT1E[] = {
	 { "GRPH_DEC_RD1", 1, 1, &umr_bitfield_default },
};
static struct umr_bitfield ixCRT1F[] = {
	 { "GRPH_DEC_RD0", 0, 7, &umr_bitfield_default },
};
static struct umr_bitfield ixAZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES[] = {
	 { "AMPLIFIER_PARAMETER_OVERRIDE", 3, 3, &umr_bitfield_default },
	 { "AUDIO_CHANNEL_CAPABILITIES", 0, 0, &umr_bitfield_default },
	 { "AUDIO_WIDGET_CAPABILITIES_DELAY", 16, 19, &umr_bitfield_default },
	 { "CONNECTION_LIST", 8, 8, &umr_bitfield_default },
	 { "DIGITAL", 9, 9, &umr_bitfield_default },
	 { "INPUT_AMPLIFIER_PRESENT", 1, 1, &umr_bitfield_default },
	 { "LR_SWAP", 11, 11, &umr_bitfield_default },
	 { "OUTPUT_AMPLIFIER_PRESENT", 2, 2, &umr_bitfield_default },
	 { "POWER_CONTROL", 10, 10, &umr_bitfield_default },
	 { "PROCESSING_WIDGET", 6, 6, &umr_bitfield_default },
	 { "STRIPE", 5, 5, &umr_bitfield_default },
	 { "TYPE", 20, 23, &umr_bitfield_default },
	 { "UNSOLICITED_RESPONSE_CAPABILITY", 7, 7, &umr_bitfield_default },
};
static struct umr_bitfield ixAZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES[] = {
	 { "BALANCED_I_O_PINS", 6, 6, &umr_bitfield_default },
	 { "DP", 24, 24, &umr_bitfield_default },
	 { "EAPD_CAPABLE", 16, 16, &umr_bitfield_default },
	 { "HDMI", 7, 7, &umr_bitfield_default },
	 { "HEADPHONE_DRIVE_CAPABLE", 3, 3, &umr_bitfield_default },
	 { "IMPEDANCE_SENSE_CAPABLE", 0, 0, &umr_bitfield_default },
	 { "INPUT_CAPABLE", 5, 5, &umr_bitfield_default },
	 { "JACK_DETECTION_CAPABILITY", 2, 2, &umr_bitfield_default },
	 { "OUTPUT_CAPABLE", 4, 4, &umr_bitfield_default },
	 { "TRIGGER_REQUIRED", 1, 1, &umr_bitfield_default },
	 { "VREF_CONTROL", 8, 15, &umr_bitfield_default },
};
static struct umr_bitfield ixAZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE[] = {
	 { "ENABLE", 7, 7, &umr_bitfield_default },
	 { "TAG", 0, 5, &umr_bitfield_default },
};
static struct umr_bitfield ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE[] = {
	 { "IMPEDANCE_SENSE", 0, 30, &umr_bitfield_default },
};
static struct umr_bitfield ixAZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL[] = {
	 { "OUT_ENABLE", 6, 6, &umr_bitfield_default },
};
static struct umr_bitfield ixAZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER[] = {
	 { "CHANNEL_ALLOCATION", 8, 15, &umr_bitfield_default },
	 { "DOWN_MIX_INHIBIT", 31, 31, &umr_bitfield_default },
	 { "DP_CONNECTION", 17, 17, &umr_bitfield_default },
	 { "EXTRA_CONNECTION_INFO", 18, 23, &umr_bitfield_default },
	 { "HDMI_CONNECTION", 16, 16, &umr_bitfield_default },
	 { "LEVEL_SHIFT", 27, 30, &umr_bitfield_default },
	 { "SPEAKER_ALLOCATION", 0, 6, &umr_bitfield_default },
};
static struct umr_bitfield ixDP_AUX2_DEBUG_G[] = {
	 { "DP_AUX2_DEBUG_G", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixDP_AUX2_DEBUG_H[] = {
	 { "DP_AUX2_DEBUG_H", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0[] = {
	 { "DESCRIPTOR_BYTE_2", 16, 23, &umr_bitfield_default },
	 { "MAX_CHANNELS", 0, 2, &umr_bitfield_default },
	 { "SUPPORTED_FREQUENCIES", 8, 15, &umr_bitfield_default },
	 { "SUPPORTED_FREQUENCIES_STEREO", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1[] = {
	 { "DESCRIPTOR_BYTE_2", 16, 23, &umr_bitfield_default },
	 { "MAX_CHANNELS", 0, 2, &umr_bitfield_default },
	 { "SUPPORTED_FREQUENCIES", 8, 15, &umr_bitfield_default },
};
static struct umr_bitfield ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2[] = {
	 { "DESCRIPTOR_BYTE_2", 16, 23, &umr_bitfield_default },
	 { "MAX_CHANNELS", 0, 2, &umr_bitfield_default },
	 { "SUPPORTED_FREQUENCIES", 8, 15, &umr_bitfield_default },
};
static struct umr_bitfield ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3[] = {
	 { "DESCRIPTOR_BYTE_2", 16, 23, &umr_bitfield_default },
	 { "MAX_CHANNELS", 0, 2, &umr_bitfield_default },
	 { "SUPPORTED_FREQUENCIES", 8, 15, &umr_bitfield_default },
};
static struct umr_bitfield ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4[] = {
	 { "DESCRIPTOR_BYTE_2", 16, 23, &umr_bitfield_default },
	 { "MAX_CHANNELS", 0, 2, &umr_bitfield_default },
	 { "SUPPORTED_FREQUENCIES", 8, 15, &umr_bitfield_default },
};
static struct umr_bitfield ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5[] = {
	 { "DESCRIPTOR_BYTE_2", 16, 23, &umr_bitfield_default },
	 { "MAX_CHANNELS", 0, 2, &umr_bitfield_default },
	 { "SUPPORTED_FREQUENCIES", 8, 15, &umr_bitfield_default },
};
static struct umr_bitfield ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6[] = {
	 { "DESCRIPTOR_BYTE_2", 16, 23, &umr_bitfield_default },
	 { "MAX_CHANNELS", 0, 2, &umr_bitfield_default },
	 { "SUPPORTED_FREQUENCIES", 8, 15, &umr_bitfield_default },
};
static struct umr_bitfield ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7[] = {
	 { "DESCRIPTOR_BYTE_2", 16, 23, &umr_bitfield_default },
	 { "MAX_CHANNELS", 0, 2, &umr_bitfield_default },
	 { "SUPPORTED_FREQUENCIES", 8, 15, &umr_bitfield_default },
};
static struct umr_bitfield ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8[] = {
	 { "DESCRIPTOR_BYTE_2", 16, 23, &umr_bitfield_default },
	 { "MAX_CHANNELS", 0, 2, &umr_bitfield_default },
	 { "SUPPORTED_FREQUENCIES", 8, 15, &umr_bitfield_default },
};
static struct umr_bitfield ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9[] = {
	 { "DESCRIPTOR_BYTE_2", 16, 23, &umr_bitfield_default },
	 { "MAX_CHANNELS", 0, 2, &umr_bitfield_default },
	 { "SUPPORTED_FREQUENCIES", 8, 15, &umr_bitfield_default },
};
static struct umr_bitfield ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10[] = {
	 { "DESCRIPTOR_BYTE_2", 16, 23, &umr_bitfield_default },
	 { "MAX_CHANNELS", 0, 2, &umr_bitfield_default },
	 { "SUPPORTED_FREQUENCIES", 8, 15, &umr_bitfield_default },
};
static struct umr_bitfield ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11[] = {
	 { "DESCRIPTOR_BYTE_2", 16, 23, &umr_bitfield_default },
	 { "MAX_CHANNELS", 0, 2, &umr_bitfield_default },
	 { "SUPPORTED_FREQUENCIES", 8, 15, &umr_bitfield_default },
};
static struct umr_bitfield ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12[] = {
	 { "DESCRIPTOR_BYTE_2", 16, 23, &umr_bitfield_default },
	 { "MAX_CHANNELS", 0, 2, &umr_bitfield_default },
	 { "SUPPORTED_FREQUENCIES", 8, 15, &umr_bitfield_default },
};
static struct umr_bitfield ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13[] = {
	 { "DESCRIPTOR_BYTE_2", 16, 23, &umr_bitfield_default },
	 { "MAX_CHANNELS", 0, 2, &umr_bitfield_default },
	 { "SUPPORTED_FREQUENCIES", 8, 15, &umr_bitfield_default },
};
static struct umr_bitfield ixAZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE[] = {
	 { "MULTICHANNEL01_CHANNEL_ID", 4, 7, &umr_bitfield_default },
	 { "MULTICHANNEL01_ENABLE", 0, 0, &umr_bitfield_default },
	 { "MULTICHANNEL01_MUTE", 1, 1, &umr_bitfield_default },
	 { "MULTICHANNEL23_CHANNEL_ID", 12, 15, &umr_bitfield_default },
	 { "MULTICHANNEL23_ENABLE", 8, 8, &umr_bitfield_default },
	 { "MULTICHANNEL23_MUTE", 9, 9, &umr_bitfield_default },
	 { "MULTICHANNEL45_CHANNEL_ID", 20, 23, &umr_bitfield_default },
	 { "MULTICHANNEL45_ENABLE", 16, 16, &umr_bitfield_default },
	 { "MULTICHANNEL45_MUTE", 17, 17, &umr_bitfield_default },
	 { "MULTICHANNEL67_CHANNEL_ID", 28, 31, &umr_bitfield_default },
	 { "MULTICHANNEL67_ENABLE", 24, 24, &umr_bitfield_default },
	 { "MULTICHANNEL67_MUTE", 25, 25, &umr_bitfield_default },
};
static struct umr_bitfield ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC[] = {
	 { "AUDIO_LIPSYNC", 8, 15, &umr_bitfield_default },
	 { "VIDEO_LIPSYNC", 0, 7, &umr_bitfield_default },
};
static struct umr_bitfield ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR[] = {
	 { "HBR_CAPABLE", 0, 0, &umr_bitfield_default },
	 { "HBR_ENABLE", 4, 4, &umr_bitfield_default },
};
static struct umr_bitfield ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0[] = {
	 { "MANUFACTURER_ID", 0, 15, &umr_bitfield_default },
	 { "PRODUCT_ID", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1[] = {
	 { "SINK_DESCRIPTION_LEN", 0, 7, &umr_bitfield_default },
};
static struct umr_bitfield ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2[] = {
	 { "PORT_ID0", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3[] = {
	 { "PORT_ID1", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4[] = {
	 { "DESCRIPTION0", 0, 7, &umr_bitfield_default },
	 { "DESCRIPTION1", 8, 15, &umr_bitfield_default },
	 { "DESCRIPTION2", 16, 23, &umr_bitfield_default },
	 { "DESCRIPTION3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5[] = {
	 { "DESCRIPTION4", 0, 7, &umr_bitfield_default },
	 { "DESCRIPTION5", 8, 15, &umr_bitfield_default },
	 { "DESCRIPTION6", 16, 23, &umr_bitfield_default },
	 { "DESCRIPTION7", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6[] = {
	 { "DESCRIPTION10", 16, 23, &umr_bitfield_default },
	 { "DESCRIPTION11", 24, 31, &umr_bitfield_default },
	 { "DESCRIPTION8", 0, 7, &umr_bitfield_default },
	 { "DESCRIPTION9", 8, 15, &umr_bitfield_default },
};
static struct umr_bitfield ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7[] = {
	 { "DESCRIPTION12", 0, 7, &umr_bitfield_default },
	 { "DESCRIPTION13", 8, 15, &umr_bitfield_default },
	 { "DESCRIPTION14", 16, 23, &umr_bitfield_default },
	 { "DESCRIPTION15", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8[] = {
	 { "DESCRIPTION16", 0, 7, &umr_bitfield_default },
	 { "DESCRIPTION17", 8, 15, &umr_bitfield_default },
};
static struct umr_bitfield ixDP_AUX4_DEBUG_D[] = {
	 { "DP_AUX4_DEBUG_D", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixDP_AUX4_DEBUG_E[] = {
	 { "DP_AUX4_DEBUG_E", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixDP_AUX4_DEBUG_F[] = {
	 { "DP_AUX4_DEBUG_F", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixDP_AUX4_DEBUG_G[] = {
	 { "DP_AUX4_DEBUG_G", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixDP_AUX4_DEBUG_H[] = {
	 { "DP_AUX4_DEBUG_H", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixDP_AUX4_DEBUG_I[] = {
	 { "DP_AUX4_DEBUG_I", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixAZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL[] = {
	 { "AUDIO_ENABLED", 31, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixAZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE[] = {
	 { "UNSOLICITED_RESPONSE_FORCE", 28, 28, &umr_bitfield_default },
	 { "UNSOLICITED_RESPONSE_PAYLOAD", 0, 25, &umr_bitfield_default },
};
static struct umr_bitfield ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT[] = {
	 { "COLOR", 12, 15, &umr_bitfield_default },
	 { "CONNECTION_TYPE", 16, 19, &umr_bitfield_default },
	 { "DEFAULT_ASSOCIATION", 4, 7, &umr_bitfield_default },
	 { "DEFAULT_DEVICE", 20, 23, &umr_bitfield_default },
	 { "LOCATION", 24, 29, &umr_bitfield_default },
	 { "MISC", 8, 11, &umr_bitfield_default },
	 { "PORT_CONNECTIVITY", 30, 31, &umr_bitfield_default },
	 { "SEQUENCE", 0, 3, &umr_bitfield_default },
};
static struct umr_bitfield ixAZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2[] = {
	 { "MULTICHANNEL1_CHANNEL_ID", 4, 7, &umr_bitfield_default },
	 { "MULTICHANNEL1_ENABLE", 0, 0, &umr_bitfield_default },
	 { "MULTICHANNEL1_MUTE", 1, 1, &umr_bitfield_default },
	 { "MULTICHANNEL3_CHANNEL_ID", 12, 15, &umr_bitfield_default },
	 { "MULTICHANNEL3_ENABLE", 8, 8, &umr_bitfield_default },
	 { "MULTICHANNEL3_MUTE", 9, 9, &umr_bitfield_default },
	 { "MULTICHANNEL5_CHANNEL_ID", 20, 23, &umr_bitfield_default },
	 { "MULTICHANNEL5_ENABLE", 16, 16, &umr_bitfield_default },
	 { "MULTICHANNEL5_MUTE", 17, 17, &umr_bitfield_default },
	 { "MULTICHANNEL7_CHANNEL_ID", 28, 31, &umr_bitfield_default },
	 { "MULTICHANNEL7_ENABLE", 24, 24, &umr_bitfield_default },
	 { "MULTICHANNEL7_MUTE", 25, 25, &umr_bitfield_default },
};
static struct umr_bitfield ixAZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE[] = {
	 { "MULTICHANNEL_MODE", 0, 0, &umr_bitfield_default },
};
static struct umr_bitfield ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0[] = {
	 { "IEC_60958_CS_MODE", 0, 1, &umr_bitfield_default },
	 { "IEC_60958_CS_SOURCE_NUMBER", 2, 5, &umr_bitfield_default },
};
static struct umr_bitfield ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1[] = {
	 { "IEC_60958_CS_CLOCK_ACCURACY", 0, 1, &umr_bitfield_default },
	 { "IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN", 2, 2, &umr_bitfield_default },
	 { "IEC_60958_CS_WORD_LENGTH", 3, 6, &umr_bitfield_default },
	 { "IEC_60958_CS_WORD_LENGTH_OVRRD_EN", 7, 7, &umr_bitfield_default },
};
static struct umr_bitfield ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2[] = {
	 { "IEC_60958_CS_SAMPLING_FREQUENCY", 0, 5, &umr_bitfield_default },
	 { "IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN", 6, 6, &umr_bitfield_default },
};
static struct umr_bitfield ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3[] = {
	 { "IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY", 0, 3, &umr_bitfield_default },
	 { "IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN", 4, 4, &umr_bitfield_default },
};
static struct umr_bitfield ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4[] = {
	 { "IEC_60958_CS_CGMS_A", 5, 6, &umr_bitfield_default },
	 { "IEC_60958_CS_CGMS_A_VALID", 7, 7, &umr_bitfield_default },
	 { "IEC_60958_CS_MPEG_SURROUND_INFO", 4, 4, &umr_bitfield_default },
	 { "IEC_60958_CS_SAMPLING_FREQUENCY_COEFF", 0, 3, &umr_bitfield_default },
};
static struct umr_bitfield ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5[] = {
	 { "IEC_60958_CS_CHANNEL_NUMBER_L", 0, 3, &umr_bitfield_default },
	 { "IEC_60958_CS_CHANNEL_NUMBER_R", 4, 7, &umr_bitfield_default },
};
static struct umr_bitfield ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6[] = {
	 { "IEC_60958_CS_CHANNEL_NUMBER_2", 0, 3, &umr_bitfield_default },
	 { "IEC_60958_CS_CHANNEL_NUMBER_3", 4, 7, &umr_bitfield_default },
};
static struct umr_bitfield ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7[] = {
	 { "IEC_60958_CS_CHANNEL_NUMBER_4", 0, 3, &umr_bitfield_default },
	 { "IEC_60958_CS_CHANNEL_NUMBER_5", 4, 7, &umr_bitfield_default },
};
static struct umr_bitfield ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8[] = {
	 { "IEC_60958_CS_CHANNEL_NUMBER_6", 0, 3, &umr_bitfield_default },
	 { "IEC_60958_CS_CHANNEL_NUMBER_7", 4, 7, &umr_bitfield_default },
};
static struct umr_bitfield ixAZALIA_F0_CODEC_PIN_ASSOCIATION_INFO[] = {
	 { "ASSOCIATION_INFO", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixDP_AUX5_DEBUG_A[] = {
	 { "DP_AUX5_DEBUG_A", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixDP_AUX5_DEBUG_B[] = {
	 { "DP_AUX5_DEBUG_B", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixDP_AUX5_DEBUG_C[] = {
	 { "DP_AUX5_DEBUG_C", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixDP_AUX5_DEBUG_D[] = {
	 { "DP_AUX5_DEBUG_D", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixDP_AUX5_DEBUG_E[] = {
	 { "DP_AUX5_DEBUG_E", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixDP_AUX5_DEBUG_F[] = {
	 { "DP_AUX5_DEBUG_F", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixDP_AUX5_DEBUG_G[] = {
	 { "DP_AUX5_DEBUG_G", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixDP_AUX5_DEBUG_H[] = {
	 { "DP_AUX5_DEBUG_H", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixDP_AUX5_DEBUG_I[] = {
	 { "DP_AUX5_DEBUG_I", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixVGADCC_DBG_DCCIF_C[] = {
	 { "DBG_DCCIF_C", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixDP_AUX6_DEBUG_A[] = {
	 { "DP_AUX6_DEBUG_A", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixDP_AUX6_DEBUG_B[] = {
	 { "DP_AUX6_DEBUG_B", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixDP_AUX6_DEBUG_C[] = {
	 { "DP_AUX6_DEBUG_C", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixDP_AUX6_DEBUG_D[] = {
	 { "DP_AUX6_DEBUG_D", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixDP_AUX6_DEBUG_E[] = {
	 { "DP_AUX6_DEBUG_E", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixDP_AUX6_DEBUG_F[] = {
	 { "DP_AUX6_DEBUG_F", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixDP_AUX6_DEBUG_G[] = {
	 { "DP_AUX6_DEBUG_G", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixDP_AUX6_DEBUG_H[] = {
	 { "DP_AUX6_DEBUG_H", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixDP_AUX6_DEBUG_I[] = {
	 { "DP_AUX6_DEBUG_I", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmVGA_RENDER_CONTROL[] = {
	 { "VGA_BLINK_MODE", 5, 6, &umr_bitfield_default },
	 { "VGA_BLINK_RATE", 0, 4, &umr_bitfield_default },
	 { "VGA_CURSOR_BLINK_INVERT", 7, 7, &umr_bitfield_default },
	 { "VGA_EXTD_ADDR_COUNT_ENABLE", 8, 8, &umr_bitfield_default },
	 { "VGA_LOCK_8DOT", 24, 24, &umr_bitfield_default },
	 { "VGAREG_LINECMP_COMPATIBILITY_SEL", 25, 25, &umr_bitfield_default },
	 { "VGA_VSTATUS_CNTL", 16, 17, &umr_bitfield_default },
};
static struct umr_bitfield mmVGA_SEQUENCER_RESET_CONTROL[] = {
	 { "D1_BLANK_DISPLAY_WHEN_SEQUENCER_RESET", 0, 0, &umr_bitfield_default },
	 { "D1_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET", 8, 8, &umr_bitfield_default },
	 { "D2_BLANK_DISPLAY_WHEN_SEQUENCER_RESET", 1, 1, &umr_bitfield_default },
	 { "D2_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET", 9, 9, &umr_bitfield_default },
	 { "D3_BLANK_DISPLAY_WHEN_SEQUENCER_RESET", 2, 2, &umr_bitfield_default },
	 { "D3_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET", 10, 10, &umr_bitfield_default },
	 { "D4_BLANK_DISPLAY_WHEN_SEQUENCER_RESET", 3, 3, &umr_bitfield_default },
	 { "D4_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET", 11, 11, &umr_bitfield_default },
	 { "D5_BLANK_DISPLAY_WHEN_SEQUENCER_RESET", 4, 4, &umr_bitfield_default },
	 { "D5_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET", 12, 12, &umr_bitfield_default },
	 { "D6_BLANK_DISPLAY_WHEN_SEQUENCER_RESET", 5, 5, &umr_bitfield_default },
	 { "D6_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET", 13, 13, &umr_bitfield_default },
	 { "VGA_MODE_AUTO_TRIGGER_ENABLE", 16, 16, &umr_bitfield_default },
	 { "VGA_MODE_AUTO_TRIGGER_INDEX_SELECT", 18, 23, &umr_bitfield_default },
	 { "VGA_MODE_AUTO_TRIGGER_REGISTER_SELECT", 17, 17, &umr_bitfield_default },
};
static struct umr_bitfield mmVGA_MODE_CONTROL[] = {
	 { "VGA_128K_APERTURE_PAGING", 8, 8, &umr_bitfield_default },
	 { "VGA_ATI_LINEAR", 0, 0, &umr_bitfield_default },
	 { "VGA_LUT_PALETTE_UPDATE_MODE", 4, 5, &umr_bitfield_default },
	 { "VGA_TEXT_132_COLUMNS_EN", 16, 16, &umr_bitfield_default },
};
static struct umr_bitfield mmVGA_SURFACE_PITCH_SELECT[] = {
	 { "VGA_SURFACE_HEIGHT_SELECT", 8, 9, &umr_bitfield_default },
	 { "VGA_SURFACE_PITCH_SELECT", 0, 1, &umr_bitfield_default },
};
static struct umr_bitfield mmVGA_MEMORY_BASE_ADDRESS[] = {
	 { "VGA_MEMORY_BASE_ADDRESS", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmVGA_TEST_DEBUG_INDEX[] = {
	 { "VGA_TEST_DEBUG_INDEX", 0, 7, &umr_bitfield_default },
	 { "VGA_TEST_DEBUG_WRITE_EN", 8, 8, &umr_bitfield_default },
};
static struct umr_bitfield mmVGA_DISPBUF1_SURFACE_ADDR[] = {
	 { "VGA_DISPBUF1_SURFACE_ADDR", 0, 24, &umr_bitfield_default },
};
static struct umr_bitfield mmVGA_TEST_DEBUG_DATA[] = {
	 { "VGA_TEST_DEBUG_DATA", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmVGA_DISPBUF2_SURFACE_ADDR[] = {
	 { "VGA_DISPBUF2_SURFACE_ADDR", 0, 24, &umr_bitfield_default },
};
static struct umr_bitfield mmVGA_MEMORY_BASE_ADDRESS_HIGH[] = {
	 { "VGA_MEMORY_BASE_ADDRESS_HIGH", 0, 7, &umr_bitfield_default },
};
static struct umr_bitfield mmVGA_HDP_CONTROL[] = {
	 { "VGA_MEMORY_DISABLE", 4, 4, &umr_bitfield_default },
	 { "VGA_MEM_PAGE_SELECT_EN", 0, 0, &umr_bitfield_default },
	 { "VGA_RBBM_LOCK_DISABLE", 8, 8, &umr_bitfield_default },
	 { "VGA_SOFT_RESET", 16, 16, &umr_bitfield_default },
	 { "VGA_TEST_RESET_CONTROL", 24, 24, &umr_bitfield_default },
};
static struct umr_bitfield mmVGA_CACHE_CONTROL[] = {
	 { "VGA_DCCIF_W256ONLY", 20, 20, &umr_bitfield_default },
	 { "VGA_DCCIF_WC_TIMEOUT", 24, 29, &umr_bitfield_default },
	 { "VGA_READ_BUFFER_INVALIDATE", 16, 16, &umr_bitfield_default },
	 { "VGA_READ_CACHE_DISABLE", 8, 8, &umr_bitfield_default },
	 { "VGA_WRITE_THROUGH_CACHE_DIS", 0, 0, &umr_bitfield_default },
};
static struct umr_bitfield mmD1VGA_CONTROL[] = {
	 { "D1VGA_MODE_ENABLE", 0, 0, &umr_bitfield_default },
	 { "D1VGA_OVERSCAN_COLOR_EN", 16, 16, &umr_bitfield_default },
	 { "D1VGA_ROTATE", 24, 25, &umr_bitfield_default },
	 { "D1VGA_SYNC_POLARITY_SELECT", 9, 9, &umr_bitfield_default },
	 { "D1VGA_TIMING_SELECT", 8, 8, &umr_bitfield_default },
};
static struct umr_bitfield mmD2VGA_CONTROL[] = {
	 { "D2VGA_MODE_ENABLE", 0, 0, &umr_bitfield_default },
	 { "D2VGA_OVERSCAN_COLOR_EN", 16, 16, &umr_bitfield_default },
	 { "D2VGA_ROTATE", 24, 25, &umr_bitfield_default },
	 { "D2VGA_SYNC_POLARITY_SELECT", 9, 9, &umr_bitfield_default },
	 { "D2VGA_TIMING_SELECT", 8, 8, &umr_bitfield_default },
};
static struct umr_bitfield mmVGA_HW_DEBUG[] = {
	 { "VGA_HW_DEBUG", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmVGA_STATUS[] = {
	 { "VGA_DISPLAY_SWITCH_STATUS", 2, 2, &umr_bitfield_default },
	 { "VGA_MEM_ACCESS_STATUS", 0, 0, &umr_bitfield_default },
	 { "VGA_MODE_AUTO_TRIGGER_STATUS", 3, 3, &umr_bitfield_default },
	 { "VGA_REG_ACCESS_STATUS", 1, 1, &umr_bitfield_default },
};
static struct umr_bitfield mmVGA_INTERRUPT_CONTROL[] = {
	 { "VGA_DISPLAY_SWITCH_INT_MASK", 16, 16, &umr_bitfield_default },
	 { "VGA_MEM_ACCESS_INT_MASK", 0, 0, &umr_bitfield_default },
	 { "VGA_MODE_AUTO_TRIGGER_INT_MASK", 24, 24, &umr_bitfield_default },
	 { "VGA_REG_ACCESS_INT_MASK", 8, 8, &umr_bitfield_default },
};
static struct umr_bitfield mmVGA_STATUS_CLEAR[] = {
	 { "VGA_DISPLAY_SWITCH_INT_CLEAR", 16, 16, &umr_bitfield_default },
	 { "VGA_MEM_ACCESS_INT_CLEAR", 0, 0, &umr_bitfield_default },
	 { "VGA_MODE_AUTO_TRIGGER_INT_CLEAR", 24, 24, &umr_bitfield_default },
	 { "VGA_REG_ACCESS_INT_CLEAR", 8, 8, &umr_bitfield_default },
};
static struct umr_bitfield mmVGA_INTERRUPT_STATUS[] = {
	 { "VGA_DISPLAY_SWITCH_INT_STATUS", 2, 2, &umr_bitfield_default },
	 { "VGA_MEM_ACCESS_INT_STATUS", 0, 0, &umr_bitfield_default },
	 { "VGA_MODE_AUTO_TRIGGER_INT_STATUS", 3, 3, &umr_bitfield_default },
	 { "VGA_REG_ACCESS_INT_STATUS", 1, 1, &umr_bitfield_default },
};
static struct umr_bitfield mmVGA_MAIN_CONTROL[] = {
	 { "VGA_CRTC_TIMEOUT", 0, 1, &umr_bitfield_default },
	 { "VGA_EXTERNAL_DAC_SENSE", 29, 29, &umr_bitfield_default },
	 { "VGA_MAIN_TEST_VSTATUS_NO_DISPLAY_CRTC_TIMEOUT", 31, 31, &umr_bitfield_default },
	 { "VGA_READBACK_CRT_INTR_SOURCE_SELECT", 24, 25, &umr_bitfield_default },
	 { "VGA_READBACK_NO_DISPLAY_SOURCE_SELECT", 16, 17, &umr_bitfield_default },
	 { "VGA_READBACK_SENSE_SWITCH_SELECT", 26, 26, &umr_bitfield_default },
	 { "VGA_READBACK_VGA_VSTATUS_SOURCE_SELECT", 8, 9, &umr_bitfield_default },
	 { "VGA_READ_URGENT_ENABLE", 27, 27, &umr_bitfield_default },
	 { "VGA_RENDER_TIMEOUT_COUNT", 3, 4, &umr_bitfield_default },
	 { "VGA_VIRTUAL_VERTICAL_RETRACE_DURATION", 5, 7, &umr_bitfield_default },
	 { "VGA_WRITES_URGENT_ENABLE", 28, 28, &umr_bitfield_default },
};
static struct umr_bitfield mmVGA_TEST_CONTROL[] = {
	 { "VGA_TEST_ENABLE", 0, 0, &umr_bitfield_default },
	 { "VGA_TEST_RENDER_DISPBUF_SELECT", 24, 24, &umr_bitfield_default },
	 { "VGA_TEST_RENDER_DONE", 16, 16, &umr_bitfield_default },
	 { "VGA_TEST_RENDER_START", 8, 8, &umr_bitfield_default },
};
static struct umr_bitfield mmVGA_DEBUG_READBACK_INDEX[] = {
	 { "VGA_DEBUG_READBACK_INDEX", 0, 7, &umr_bitfield_default },
};
static struct umr_bitfield mmVGA_DEBUG_READBACK_DATA[] = {
	 { "VGA_DEBUG_READBACK_DATA", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmVGA25_PPLL_REF_DIV[] = {
	 { "VGA25_PPLL_REF_DIV", 0, 9, &umr_bitfield_default },
};
static struct umr_bitfield mmVGA28_PPLL_REF_DIV[] = {
	 { "VGA28_PPLL_REF_DIV", 0, 9, &umr_bitfield_default },
};
static struct umr_bitfield mmVGA41_PPLL_REF_DIV[] = {
	 { "VGA41_PPLL_REF_DIV", 0, 9, &umr_bitfield_default },
};
static struct umr_bitfield mmVGA25_PPLL_FB_DIV[] = {
	 { "VGA25_PPLL_FB_DIV_FRACTION_CNTL", 4, 5, &umr_bitfield_default },
	 { "VGA25_PPLL_FB_DIV_FRACTION", 0, 3, &umr_bitfield_default },
	 { "VGA25_PPLL_FB_DIV", 16, 26, &umr_bitfield_default },
};
static struct umr_bitfield mmVGA28_PPLL_FB_DIV[] = {
	 { "VGA28_PPLL_FB_DIV_FRACTION_CNTL", 4, 5, &umr_bitfield_default },
	 { "VGA28_PPLL_FB_DIV_FRACTION", 0, 3, &umr_bitfield_default },
	 { "VGA28_PPLL_FB_DIV", 16, 26, &umr_bitfield_default },
};
static struct umr_bitfield mmVGA41_PPLL_FB_DIV[] = {
	 { "VGA41_PPLL_FB_DIV_FRACTION_CNTL", 4, 5, &umr_bitfield_default },
	 { "VGA41_PPLL_FB_DIV_FRACTION", 0, 3, &umr_bitfield_default },
	 { "VGA41_PPLL_FB_DIV", 16, 26, &umr_bitfield_default },
};
static struct umr_bitfield mmVGA25_PPLL_POST_DIV[] = {
	 { "VGA25_PPLL_POST_DIV_DVOCLK", 8, 14, &umr_bitfield_default },
	 { "VGA25_PPLL_POST_DIV_IDCLK", 16, 22, &umr_bitfield_default },
	 { "VGA25_PPLL_POST_DIV_PIXCLK", 0, 6, &umr_bitfield_default },
};
static struct umr_bitfield mmVGA28_PPLL_POST_DIV[] = {
	 { "VGA28_PPLL_POST_DIV_DVOCLK", 8, 14, &umr_bitfield_default },
	 { "VGA28_PPLL_POST_DIV_IDCLK", 16, 22, &umr_bitfield_default },
	 { "VGA28_PPLL_POST_DIV_PIXCLK", 0, 6, &umr_bitfield_default },
};
static struct umr_bitfield mmVGA41_PPLL_POST_DIV[] = {
	 { "VGA41_PPLL_POST_DIV_DVOCLK", 8, 14, &umr_bitfield_default },
	 { "VGA41_PPLL_POST_DIV_IDCLK", 16, 22, &umr_bitfield_default },
	 { "VGA41_PPLL_POST_DIV_PIXCLK", 0, 6, &umr_bitfield_default },
};
static struct umr_bitfield mmVGA25_PPLL_ANALOG[] = {
	 { "VGA25_CAL_MODE", 0, 4, &umr_bitfield_default },
	 { "VGA25_PPLL_CP", 8, 11, &umr_bitfield_default },
	 { "VGA25_PPLL_IBIAS", 24, 31, &umr_bitfield_default },
	 { "VGA25_PPLL_LF_MODE", 12, 20, &umr_bitfield_default },
	 { "VGA25_PPLL_PFD_PULSE_SEL", 5, 6, &umr_bitfield_default },
};
static struct umr_bitfield mmVGA28_PPLL_ANALOG[] = {
	 { "VGA28_CAL_MODE", 0, 4, &umr_bitfield_default },
	 { "VGA28_PPLL_CP", 8, 11, &umr_bitfield_default },
	 { "VGA28_PPLL_IBIAS", 24, 31, &umr_bitfield_default },
	 { "VGA28_PPLL_LF_MODE", 12, 20, &umr_bitfield_default },
	 { "VGA28_PPLL_PFD_PULSE_SEL", 5, 6, &umr_bitfield_default },
};
static struct umr_bitfield mmVGA41_PPLL_ANALOG[] = {
	 { "VGA41_CAL_MODE", 0, 4, &umr_bitfield_default },
	 { "VGA41_PPLL_CP", 8, 11, &umr_bitfield_default },
	 { "VGA41_PPLL_IBIAS", 24, 31, &umr_bitfield_default },
	 { "VGA41_PPLL_LF_MODE", 12, 20, &umr_bitfield_default },
	 { "VGA41_PPLL_PFD_PULSE_SEL", 5, 6, &umr_bitfield_default },
};
static struct umr_bitfield mmCRTC8_DATA[] = {
	 { "VCRTC_DATA", 0, 7, &umr_bitfield_default },
};
static struct umr_bitfield mmGENFC_WT[] = {
	 { "VSYNC_SEL_W", 3, 3, &umr_bitfield_default },
};
static struct umr_bitfield mmATTRDR[] = {
	 { "ATTR_DATA", 0, 7, &umr_bitfield_default },
};
static struct umr_bitfield mmDAC_MASK[] = {
	 { "DAC_MASK", 0, 7, &umr_bitfield_default },
};
static struct umr_bitfield mmDAC_DATA[] = {
	 { "DAC_DATA", 0, 5, &umr_bitfield_default },
};
static struct umr_bitfield mmGENMO_RD[] = {
	 { "GENMO_MONO_ADDRESS_B", 0, 0, &umr_bitfield_default },
	 { "ODD_EVEN_MD_PGSEL", 5, 5, &umr_bitfield_default },
	 { "VGA_CKSEL", 2, 3, &umr_bitfield_default },
	 { "VGA_HSYNC_POL", 6, 6, &umr_bitfield_default },
	 { "VGA_RAM_EN", 1, 1, &umr_bitfield_default },
	 { "VGA_VSYNC_POL", 7, 7, &umr_bitfield_default },
};
static struct umr_bitfield mmD3VGA_CONTROL[] = {
	 { "D3VGA_MODE_ENABLE", 0, 0, &umr_bitfield_default },
	 { "D3VGA_OVERSCAN_COLOR_EN", 16, 16, &umr_bitfield_default },
	 { "D3VGA_ROTATE", 24, 25, &umr_bitfield_default },
	 { "D3VGA_SYNC_POLARITY_SELECT", 9, 9, &umr_bitfield_default },
	 { "D3VGA_TIMING_SELECT", 8, 8, &umr_bitfield_default },
};
static struct umr_bitfield mmD4VGA_CONTROL[] = {
	 { "D4VGA_MODE_ENABLE", 0, 0, &umr_bitfield_default },
	 { "D4VGA_OVERSCAN_COLOR_EN", 16, 16, &umr_bitfield_default },
	 { "D4VGA_ROTATE", 24, 25, &umr_bitfield_default },
	 { "D4VGA_SYNC_POLARITY_SELECT", 9, 9, &umr_bitfield_default },
	 { "D4VGA_TIMING_SELECT", 8, 8, &umr_bitfield_default },
};
static struct umr_bitfield mmD5VGA_CONTROL[] = {
	 { "D5VGA_MODE_ENABLE", 0, 0, &umr_bitfield_default },
	 { "D5VGA_OVERSCAN_COLOR_EN", 16, 16, &umr_bitfield_default },
	 { "D5VGA_ROTATE", 24, 25, &umr_bitfield_default },
	 { "D5VGA_SYNC_POLARITY_SELECT", 9, 9, &umr_bitfield_default },
	 { "D5VGA_TIMING_SELECT", 8, 8, &umr_bitfield_default },
};
static struct umr_bitfield mmD6VGA_CONTROL[] = {
	 { "D6VGA_MODE_ENABLE", 0, 0, &umr_bitfield_default },
	 { "D6VGA_OVERSCAN_COLOR_EN", 16, 16, &umr_bitfield_default },
	 { "D6VGA_ROTATE", 24, 25, &umr_bitfield_default },
	 { "D6VGA_SYNC_POLARITY_SELECT", 9, 9, &umr_bitfield_default },
	 { "D6VGA_TIMING_SELECT", 8, 8, &umr_bitfield_default },
};
static struct umr_bitfield mmVGA_SOURCE_SELECT[] = {
	 { "VGA_SOURCE_SEL_A", 0, 2, &umr_bitfield_default },
	 { "VGA_SOURCE_SEL_B", 8, 10, &umr_bitfield_default },
};
static struct umr_bitfield mmDCCG_GTC_CNTL[] = {
	 { "DCCG_GTC_ENABLE", 0, 0, &umr_bitfield_default },
};
static struct umr_bitfield mmDCCG_GTC_DTO_MODULO[] = {
	 { "DCCG_GTC_DTO_MODULO", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCCG_GTC_CURRENT[] = {
	 { "DCCG_GTC_CURRENT", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDENTIST_DISPCLK_CNTL[] = {
	 { "DENTIST_DISPCLK_CHG_DONE", 19, 19, &umr_bitfield_default },
	 { "DENTIST_DISPCLK_CHG_MODE", 15, 16, &umr_bitfield_default },
	 { "DENTIST_DISPCLK_CHGTOG", 17, 17, &umr_bitfield_default },
	 { "DENTIST_DISPCLK_DONETOG", 18, 18, &umr_bitfield_default },
	 { "DENTIST_DISPCLK_RDIVIDER", 8, 14, &umr_bitfield_default },
	 { "DENTIST_DISPCLK_WDIVIDER", 0, 6, &umr_bitfield_default },
	 { "DENTIST_DPREFCLK_CHG_DONE", 20, 20, &umr_bitfield_default },
	 { "DENTIST_DPREFCLK_CHGTOG", 21, 21, &umr_bitfield_default },
	 { "DENTIST_DPREFCLK_DONETOG", 22, 22, &umr_bitfield_default },
	 { "DENTIST_DPREFCLK_WDIVIDER", 24, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmDAC_CLK_ENABLE[] = {
	 { "DACA_CLK_ENABLE", 0, 0, &umr_bitfield_default },
	 { "DACB_CLK_ENABLE", 4, 4, &umr_bitfield_default },
};
static struct umr_bitfield mmDVO_CLK_ENABLE[] = {
	 { "DVO_CLK_ENABLE", 0, 0, &umr_bitfield_default },
};
static struct umr_bitfield mmMILLISECOND_TIME_BASE_DIV[] = {
	 { "MILLISECOND_TIME_BASE_CLOCK_SOURCE_SEL", 20, 20, &umr_bitfield_default },
	 { "MILLISECOND_TIME_BASE_DIV", 0, 16, &umr_bitfield_default },
};
static struct umr_bitfield mmDISPCLK_FREQ_CHANGE_CNTL[] = {
	 { "DCCG_FIFO_ERRDET_OVR_EN", 30, 30, &umr_bitfield_default },
	 { "DCCG_FIFO_ERRDET_RESET", 28, 28, &umr_bitfield_default },
	 { "DCCG_FIFO_ERRDET_STATE", 29, 29, &umr_bitfield_default },
	 { "DISPCLK_CHG_FWD_CORR_DISABLE", 31, 31, &umr_bitfield_default },
	 { "DISPCLK_FREQ_RAMP_DONE", 20, 20, &umr_bitfield_default },
	 { "DISPCLK_MAX_ERRDET_CYCLES", 25, 27, &umr_bitfield_default },
	 { "DISPCLK_STEP_DELAY", 0, 13, &umr_bitfield_default },
	 { "DISPCLK_STEP_SIZE", 16, 19, &umr_bitfield_default },
};
static struct umr_bitfield mmLIGHT_SLEEP_CNTL[] = {
	 { "LIGHT_SLEEP_DIS", 0, 0, &umr_bitfield_default },
	 { "MEM_SHUTDOWN_DIS", 8, 8, &umr_bitfield_default },
};
static struct umr_bitfield mmDCCG_PERFMON_CNTL[] = {
	 { "DCCG_PERF_CRTC_SEL", 8, 10, &umr_bitfield_default },
	 { "DCCG_PERF_DISPCLK_ENABLE", 0, 0, &umr_bitfield_default },
	 { "DCCG_PERF_DPREFCLK_ENABLE", 1, 1, &umr_bitfield_default },
	 { "DCCG_PERF_MODE_HSYNC", 7, 7, &umr_bitfield_default },
	 { "DCCG_PERF_MODE_VSYNC", 6, 6, &umr_bitfield_default },
	 { "DCCG_PERF_PIXCLK0_ENABLE", 4, 4, &umr_bitfield_default },
	 { "DCCG_PERF_PIXCLK1_ENABLE", 2, 2, &umr_bitfield_default },
	 { "DCCG_PERF_PIXCLK2_ENABLE", 3, 3, &umr_bitfield_default },
	 { "DCCG_PERF_RUN", 5, 5, &umr_bitfield_default },
};
static struct umr_bitfield mmDCCG_GATE_DISABLE_CNTL[] = {
	 { "DACACLK_GATE_DISABLE", 4, 4, &umr_bitfield_default },
	 { "DACBCLK_GATE_DISABLE", 5, 5, &umr_bitfield_default },
	 { "DISPCLK_DCCG_GATE_DISABLE", 0, 0, &umr_bitfield_default },
	 { "DISPCLK_RAMP_DIV_ID", 24, 26, &umr_bitfield_default },
	 { "DISPCLK_R_DCCG_GATE_DISABLE", 1, 1, &umr_bitfield_default },
	 { "DISPCLK_R_DCCG_RAMP_DISABLE", 20, 20, &umr_bitfield_default },
	 { "DVOACLK_GATE_DISABLE", 6, 6, &umr_bitfield_default },
	 { "PCLK_TV_GATE_DISABLE", 16, 16, &umr_bitfield_default },
	 { "SCLK_GATE_DISABLE", 2, 2, &umr_bitfield_default },
	 { "SCLK_RAMP_DIV_ID", 28, 30, &umr_bitfield_default },
	 { "SYMCLKA_GATE_DISABLE", 8, 8, &umr_bitfield_default },
	 { "SYMCLKB_GATE_DISABLE", 9, 9, &umr_bitfield_default },
	 { "SYMCLKC_GATE_DISABLE", 10, 10, &umr_bitfield_default },
	 { "SYMCLKD_GATE_DISABLE", 11, 11, &umr_bitfield_default },
	 { "SYMCLKE_GATE_DISABLE", 12, 12, &umr_bitfield_default },
	 { "SYMCLKF_GATE_DISABLE", 13, 13, &umr_bitfield_default },
};
static struct umr_bitfield mmDISPCLK_CGTT_BLK_CTRL_REG[] = {
	 { "DISPCLK_TURN_OFF_DELAY", 4, 11, &umr_bitfield_default },
	 { "DISPCLK_TURN_ON_DELAY", 0, 3, &umr_bitfield_default },
};
static struct umr_bitfield mmSCLK_CGTT_BLK_CTRL_REG[] = {
	 { "SCLK_TURN_OFF_DELAY", 4, 11, &umr_bitfield_default },
	 { "SCLK_TURN_ON_DELAY", 0, 3, &umr_bitfield_default },
};
static struct umr_bitfield mmDCCG_CAC_STATUS[] = {
	 { "CAC_STATUS_RDDATA", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmPIXCLK1_RESYNC_CNTL[] = {
	 { "DCCG_DEEP_COLOR_CNTL1", 4, 5, &umr_bitfield_default },
	 { "PIXCLK1_RESYNC_ENABLE", 0, 0, &umr_bitfield_default },
};
static struct umr_bitfield mmPIXCLK2_RESYNC_CNTL[] = {
	 { "DCCG_DEEP_COLOR_CNTL2", 4, 5, &umr_bitfield_default },
	 { "PIXCLK2_RESYNC_ENABLE", 0, 0, &umr_bitfield_default },
};
static struct umr_bitfield mmPIXCLK0_RESYNC_CNTL[] = {
	 { "DCCG_DEEP_COLOR_CNTL0", 4, 5, &umr_bitfield_default },
	 { "PIXCLK0_RESYNC_ENABLE", 0, 0, &umr_bitfield_default },
};
static struct umr_bitfield mmMICROSECOND_TIME_BASE_DIV[] = {
	 { "MICROSECOND_TIME_BASE_CLOCK_SOURCE_SEL", 20, 20, &umr_bitfield_default },
	 { "MICROSECOND_TIME_BASE_DIV", 0, 6, &umr_bitfield_default },
	 { "XTAL_REF_CLOCK_SOURCE_SEL", 17, 17, &umr_bitfield_default },
	 { "XTAL_REF_DIV", 8, 14, &umr_bitfield_default },
	 { "XTAL_REF_SEL", 16, 16, &umr_bitfield_default },
};
static struct umr_bitfield mmDISPPLL_BG_CNTL[] = {
	 { "DISPPLL_BG_ADJ", 4, 7, &umr_bitfield_default },
	 { "DISPPLL_BG_PDN", 0, 0, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG_SOFT_RESET[] = {
	 { "DIGA_BE_SOFT_RESET", 1, 1, &umr_bitfield_default },
	 { "DIGA_FE_SOFT_RESET", 0, 0, &umr_bitfield_default },
	 { "DIGB_BE_SOFT_RESET", 5, 5, &umr_bitfield_default },
	 { "DIGB_FE_SOFT_RESET", 4, 4, &umr_bitfield_default },
	 { "DIGC_BE_SOFT_RESET", 9, 9, &umr_bitfield_default },
	 { "DIGC_FE_SOFT_RESET", 8, 8, &umr_bitfield_default },
	 { "DIGD_BE_SOFT_RESET", 13, 13, &umr_bitfield_default },
	 { "DIGD_FE_SOFT_RESET", 12, 12, &umr_bitfield_default },
	 { "DIGE_BE_SOFT_RESET", 17, 17, &umr_bitfield_default },
	 { "DIGE_FE_SOFT_RESET", 16, 16, &umr_bitfield_default },
	 { "DIGF_BE_SOFT_RESET", 21, 21, &umr_bitfield_default },
	 { "DIGF_FE_SOFT_RESET", 20, 20, &umr_bitfield_default },
};
static struct umr_bitfield mmCRTC0_PIXEL_RATE_CNTL[] = {
	 { "CRTC0_ADD_PIXEL", 8, 8, &umr_bitfield_default },
	 { "CRTC0_DISPOUT_ERROR_COUNT", 16, 27, &umr_bitfield_default },
	 { "CRTC0_DISPOUT_FIFO_ERROR", 14, 15, &umr_bitfield_default },
	 { "CRTC0_DROP_PIXEL", 9, 9, &umr_bitfield_default },
	 { "CRTC0_PIXEL_RATE_SOURCE", 0, 1, &umr_bitfield_default },
	 { "DP_DTO0_ENABLE", 4, 4, &umr_bitfield_default },
};
static struct umr_bitfield mmDP_DTO0_PHASE[] = {
	 { "DP_DTO0_PHASE", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDP_DTO0_MODULO[] = {
	 { "DP_DTO0_MODULO", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmCRTC1_PIXEL_RATE_CNTL[] = {
	 { "CRTC1_ADD_PIXEL", 8, 8, &umr_bitfield_default },
	 { "CRTC1_DISPOUT_ERROR_COUNT", 16, 27, &umr_bitfield_default },
	 { "CRTC1_DISPOUT_FIFO_ERROR", 14, 15, &umr_bitfield_default },
	 { "CRTC1_DROP_PIXEL", 9, 9, &umr_bitfield_default },
	 { "CRTC1_PIXEL_RATE_SOURCE", 0, 1, &umr_bitfield_default },
	 { "DP_DTO1_ENABLE", 4, 4, &umr_bitfield_default },
};
static struct umr_bitfield mmDP_DTO1_PHASE[] = {
	 { "DP_DTO1_PHASE", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDP_DTO1_MODULO[] = {
	 { "DP_DTO1_MODULO", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmCRTC2_PIXEL_RATE_CNTL[] = {
	 { "CRTC2_ADD_PIXEL", 8, 8, &umr_bitfield_default },
	 { "CRTC2_DISPOUT_ERROR_COUNT", 16, 27, &umr_bitfield_default },
	 { "CRTC2_DISPOUT_FIFO_ERROR", 14, 15, &umr_bitfield_default },
	 { "CRTC2_DROP_PIXEL", 9, 9, &umr_bitfield_default },
	 { "CRTC2_PIXEL_RATE_SOURCE", 0, 1, &umr_bitfield_default },
	 { "DP_DTO2_ENABLE", 4, 4, &umr_bitfield_default },
};
static struct umr_bitfield mmDP_DTO2_PHASE[] = {
	 { "DP_DTO2_PHASE", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDP_DTO2_MODULO[] = {
	 { "DP_DTO2_MODULO", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmCRTC3_PIXEL_RATE_CNTL[] = {
	 { "CRTC3_ADD_PIXEL", 8, 8, &umr_bitfield_default },
	 { "CRTC3_DISPOUT_ERROR_COUNT", 16, 27, &umr_bitfield_default },
	 { "CRTC3_DISPOUT_FIFO_ERROR", 14, 15, &umr_bitfield_default },
	 { "CRTC3_DROP_PIXEL", 9, 9, &umr_bitfield_default },
	 { "CRTC3_PIXEL_RATE_SOURCE", 0, 1, &umr_bitfield_default },
	 { "DP_DTO3_ENABLE", 4, 4, &umr_bitfield_default },
};
static struct umr_bitfield mmDP_DTO3_PHASE[] = {
	 { "DP_DTO3_PHASE", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDP_DTO3_MODULO[] = {
	 { "DP_DTO3_MODULO", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmCRTC4_PIXEL_RATE_CNTL[] = {
	 { "CRTC4_ADD_PIXEL", 8, 8, &umr_bitfield_default },
	 { "CRTC4_DISPOUT_ERROR_COUNT", 16, 27, &umr_bitfield_default },
	 { "CRTC4_DISPOUT_FIFO_ERROR", 14, 15, &umr_bitfield_default },
	 { "CRTC4_DROP_PIXEL", 9, 9, &umr_bitfield_default },
	 { "CRTC4_PIXEL_RATE_SOURCE", 0, 1, &umr_bitfield_default },
	 { "DP_DTO4_ENABLE", 4, 4, &umr_bitfield_default },
};
static struct umr_bitfield mmDP_DTO4_PHASE[] = {
	 { "DP_DTO4_PHASE", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDP_DTO4_MODULO[] = {
	 { "DP_DTO4_MODULO", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmCRTC5_PIXEL_RATE_CNTL[] = {
	 { "CRTC5_ADD_PIXEL", 8, 8, &umr_bitfield_default },
	 { "CRTC5_DISPOUT_ERROR_COUNT", 16, 27, &umr_bitfield_default },
	 { "CRTC5_DISPOUT_FIFO_ERROR", 14, 15, &umr_bitfield_default },
	 { "CRTC5_DROP_PIXEL", 9, 9, &umr_bitfield_default },
	 { "CRTC5_PIXEL_RATE_SOURCE", 0, 1, &umr_bitfield_default },
	 { "DP_DTO5_ENABLE", 4, 4, &umr_bitfield_default },
};
static struct umr_bitfield mmDP_DTO5_PHASE[] = {
	 { "DP_DTO5_PHASE", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDP_DTO5_MODULO[] = {
	 { "DP_DTO5_MODULO", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCFE0_SOFT_RESET[] = {
	 { "CRTC0_SOFT_RESET", 4, 4, &umr_bitfield_default },
	 { "DCP0_PIXPIPE_SOFT_RESET", 0, 0, &umr_bitfield_default },
	 { "DCP0_REQ_SOFT_RESET", 1, 1, &umr_bitfield_default },
	 { "SCL0_ALU_SOFT_RESET", 2, 2, &umr_bitfield_default },
	 { "SCL0_SOFT_RESET", 3, 3, &umr_bitfield_default },
};
static struct umr_bitfield mmDCFE1_SOFT_RESET[] = {
	 { "CRTC1_SOFT_RESET", 4, 4, &umr_bitfield_default },
	 { "DCP1_PIXPIPE_SOFT_RESET", 0, 0, &umr_bitfield_default },
	 { "DCP1_REQ_SOFT_RESET", 1, 1, &umr_bitfield_default },
	 { "SCL1_ALU_SOFT_RESET", 2, 2, &umr_bitfield_default },
	 { "SCL1_SOFT_RESET", 3, 3, &umr_bitfield_default },
};
static struct umr_bitfield mmDCFE2_SOFT_RESET[] = {
	 { "CRTC2_SOFT_RESET", 4, 4, &umr_bitfield_default },
	 { "DCP2_PIXPIPE_SOFT_RESET", 0, 0, &umr_bitfield_default },
	 { "DCP2_REQ_SOFT_RESET", 1, 1, &umr_bitfield_default },
	 { "SCL2_ALU_SOFT_RESET", 2, 2, &umr_bitfield_default },
	 { "SCL2_SOFT_RESET", 3, 3, &umr_bitfield_default },
};
static struct umr_bitfield mmDCFE3_SOFT_RESET[] = {
	 { "CRTC3_SOFT_RESET", 4, 4, &umr_bitfield_default },
	 { "DCP3_PIXPIPE_SOFT_RESET", 0, 0, &umr_bitfield_default },
	 { "DCP3_REQ_SOFT_RESET", 1, 1, &umr_bitfield_default },
	 { "SCL3_ALU_SOFT_RESET", 2, 2, &umr_bitfield_default },
	 { "SCL3_SOFT_RESET", 3, 3, &umr_bitfield_default },
};
static struct umr_bitfield mmDCFE4_SOFT_RESET[] = {
	 { "CRTC4_SOFT_RESET", 4, 4, &umr_bitfield_default },
	 { "DCP4_PIXPIPE_SOFT_RESET", 0, 0, &umr_bitfield_default },
	 { "DCP4_REQ_SOFT_RESET", 1, 1, &umr_bitfield_default },
	 { "SCL4_ALU_SOFT_RESET", 2, 2, &umr_bitfield_default },
	 { "SCL4_SOFT_RESET", 3, 3, &umr_bitfield_default },
};
static struct umr_bitfield mmDCFE5_SOFT_RESET[] = {
	 { "CRTC5_SOFT_RESET", 4, 4, &umr_bitfield_default },
	 { "DCP5_PIXPIPE_SOFT_RESET", 0, 0, &umr_bitfield_default },
	 { "DCP5_REQ_SOFT_RESET", 1, 1, &umr_bitfield_default },
	 { "SCL5_ALU_SOFT_RESET", 2, 2, &umr_bitfield_default },
	 { "SCL5_SOFT_RESET", 3, 3, &umr_bitfield_default },
};
static struct umr_bitfield mmDCI_SOFT_RESET[] = {
	 { "DMIF0_SOFT_RESET", 4, 4, &umr_bitfield_default },
	 { "DMIF1_SOFT_RESET", 5, 5, &umr_bitfield_default },
	 { "DMIF2_SOFT_RESET", 6, 6, &umr_bitfield_default },
	 { "DMIF3_SOFT_RESET", 7, 7, &umr_bitfield_default },
	 { "DMIF4_SOFT_RESET", 8, 8, &umr_bitfield_default },
	 { "DMIF5_SOFT_RESET", 9, 9, &umr_bitfield_default },
	 { "DMIFARB_SOFT_RESET", 12, 12, &umr_bitfield_default },
	 { "FBC_SOFT_RESET", 3, 3, &umr_bitfield_default },
	 { "MCIF_SOFT_RESET", 2, 2, &umr_bitfield_default },
	 { "VGA_SOFT_RESET", 0, 0, &umr_bitfield_default },
	 { "VIP_SOFT_RESET", 1, 1, &umr_bitfield_default },
};
static struct umr_bitfield mmDCCG_SOFT_RESET[] = {
	 { "REFCLK_SOFT_RESET", 0, 0, &umr_bitfield_default },
};
static struct umr_bitfield mmSYMCLKA_CLOCK_ENABLE[] = {
	 { "SYMCLKA_CLOCK_ENABLE", 0, 0, &umr_bitfield_default },
	 { "SYMCLKA_FE_FORCE_EN", 4, 4, &umr_bitfield_default },
	 { "SYMCLKA_FE_FORCE_SRC", 8, 10, &umr_bitfield_default },
};
static struct umr_bitfield mmSYMCLKB_CLOCK_ENABLE[] = {
	 { "SYMCLKB_CLOCK_ENABLE", 0, 0, &umr_bitfield_default },
	 { "SYMCLKB_FE_FORCE_EN", 4, 4, &umr_bitfield_default },
	 { "SYMCLKB_FE_FORCE_SRC", 8, 10, &umr_bitfield_default },
};
static struct umr_bitfield mmSYMCLKC_CLOCK_ENABLE[] = {
	 { "SYMCLKC_CLOCK_ENABLE", 0, 0, &umr_bitfield_default },
	 { "SYMCLKC_FE_FORCE_EN", 4, 4, &umr_bitfield_default },
	 { "SYMCLKC_FE_FORCE_SRC", 8, 10, &umr_bitfield_default },
};
static struct umr_bitfield mmSYMCLKD_CLOCK_ENABLE[] = {
	 { "SYMCLKD_CLOCK_ENABLE", 0, 0, &umr_bitfield_default },
	 { "SYMCLKD_FE_FORCE_EN", 4, 4, &umr_bitfield_default },
	 { "SYMCLKD_FE_FORCE_SRC", 8, 10, &umr_bitfield_default },
};
static struct umr_bitfield mmSYMCLKE_CLOCK_ENABLE[] = {
	 { "SYMCLKE_CLOCK_ENABLE", 0, 0, &umr_bitfield_default },
	 { "SYMCLKE_FE_FORCE_EN", 4, 4, &umr_bitfield_default },
	 { "SYMCLKE_FE_FORCE_SRC", 8, 10, &umr_bitfield_default },
};
static struct umr_bitfield mmSYMCLKF_CLOCK_ENABLE[] = {
	 { "SYMCLKF_CLOCK_ENABLE", 0, 0, &umr_bitfield_default },
	 { "SYMCLKF_FE_FORCE_EN", 4, 4, &umr_bitfield_default },
	 { "SYMCLKF_FE_FORCE_SRC", 8, 10, &umr_bitfield_default },
};
static struct umr_bitfield mmUNIPHY_SOFT_RESET[] = {
	 { "DSYNCA_SOFT_RESET", 0, 0, &umr_bitfield_default },
	 { "DSYNCB_SOFT_RESET", 1, 1, &umr_bitfield_default },
	 { "DSYNCC_SOFT_RESET", 2, 2, &umr_bitfield_default },
	 { "DSYNCD_SOFT_RESET", 3, 3, &umr_bitfield_default },
	 { "DSYNCE_SOFT_RESET", 4, 4, &umr_bitfield_default },
	 { "DSYNCF_SOFT_RESET", 5, 5, &umr_bitfield_default },
};
static struct umr_bitfield mmDCO_SOFT_RESET[] = {
	 { "ABM_SOFT_RESET", 25, 25, &umr_bitfield_default },
	 { "DACA_CFG_IF_SOFT_RESET", 29, 29, &umr_bitfield_default },
	 { "DACA_SOFT_RESET", 0, 0, &umr_bitfield_default },
	 { "DACB_SOFT_RESET", 1, 1, &umr_bitfield_default },
	 { "DVO_ENABLE_RST", 3, 3, &umr_bitfield_default },
	 { "DVO_SOFT_RESET", 27, 27, &umr_bitfield_default },
	 { "FMT0_SOFT_RESET", 16, 16, &umr_bitfield_default },
	 { "FMT1_SOFT_RESET", 17, 17, &umr_bitfield_default },
	 { "FMT2_SOFT_RESET", 18, 18, &umr_bitfield_default },
	 { "FMT3_SOFT_RESET", 19, 19, &umr_bitfield_default },
	 { "FMT4_SOFT_RESET", 20, 20, &umr_bitfield_default },
	 { "FMT5_SOFT_RESET", 21, 21, &umr_bitfield_default },
	 { "MVP_SOFT_RESET", 24, 24, &umr_bitfield_default },
	 { "SOFT_RESET_DVO", 2, 2, &umr_bitfield_default },
	 { "SRBM_SOFT_RESET_ENABLE", 28, 28, &umr_bitfield_default },
	 { "TVOUT_SOFT_RESET", 26, 26, &umr_bitfield_default },
};
static struct umr_bitfield mmDVOACLKD_CNTL[] = {
	 { "DVOACLKD_COARSE_ADJUST_EN", 17, 17, &umr_bitfield_default },
	 { "DVOACLKD_COARSE_SKEW_CNTL", 8, 12, &umr_bitfield_default },
	 { "DVOACLKD_FINE_ADJUST_EN", 16, 16, &umr_bitfield_default },
	 { "DVOACLKD_FINE_SKEW_CNTL", 0, 2, &umr_bitfield_default },
	 { "DVOACLKD_IN_PHASE", 18, 18, &umr_bitfield_default },
};
static struct umr_bitfield mmDVOACLKC_MVP_CNTL[] = {
	 { "DVOACLKC_MVP_COARSE_ADJUST_EN", 17, 17, &umr_bitfield_default },
	 { "DVOACLKC_MVP_COARSE_SKEW_CNTL", 8, 12, &umr_bitfield_default },
	 { "DVOACLKC_MVP_FINE_ADJUST_EN", 16, 16, &umr_bitfield_default },
	 { "DVOACLKC_MVP_FINE_SKEW_CNTL", 0, 2, &umr_bitfield_default },
	 { "DVOACLKC_MVP_IN_PHASE", 18, 18, &umr_bitfield_default },
	 { "DVOACLKC_MVP_SKEW_PHASE_OVERRIDE", 20, 20, &umr_bitfield_default },
	 { "MVP_CLK_A_SRC_SEL", 24, 25, &umr_bitfield_default },
	 { "MVP_CLK_B_SRC_SEL", 28, 29, &umr_bitfield_default },
};
static struct umr_bitfield mmDVOACLKC_CNTL[] = {
	 { "DVOACLKC_COARSE_ADJUST_EN", 17, 17, &umr_bitfield_default },
	 { "DVOACLKC_COARSE_SKEW_CNTL", 8, 12, &umr_bitfield_default },
	 { "DVOACLKC_FINE_ADJUST_EN", 16, 16, &umr_bitfield_default },
	 { "DVOACLKC_FINE_SKEW_CNTL", 0, 2, &umr_bitfield_default },
	 { "DVOACLKC_IN_PHASE", 18, 18, &umr_bitfield_default },
};
static struct umr_bitfield mmDCCG_AUDIO_DTO_SOURCE[] = {
	 { "DCCG_AUDIO_DTO0_SOURCE_SEL", 0, 2, &umr_bitfield_default },
	 { "DCCG_AUDIO_DTO_SEL", 4, 4, &umr_bitfield_default },
};
static struct umr_bitfield mmDCCG_AUDIO_DTO0_PHASE[] = {
	 { "DCCG_AUDIO_DTO0_PHASE", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCCG_AUDIO_DTO0_MODULE[] = {
	 { "DCCG_AUDIO_DTO0_MODULE", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCCG_AUDIO_DTO1_PHASE[] = {
	 { "DCCG_AUDIO_DTO1_PHASE", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCCG_AUDIO_DTO1_MODULE[] = {
	 { "DCCG_AUDIO_DTO1_MODULE", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCCG_TEST_DEBUG_INDEX[] = {
	 { "DCCG_DBG_SEL", 12, 12, &umr_bitfield_default },
	 { "DCCG_TEST_DEBUG_INDEX", 0, 7, &umr_bitfield_default },
	 { "DCCG_TEST_DEBUG_WRITE_EN", 8, 8, &umr_bitfield_default },
};
static struct umr_bitfield mmDCCG_TEST_DEBUG_DATA[] = {
	 { "DCCG_TEST_DEBUG_DATA", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCCG_TEST_CLK_SEL[] = {
	 { "DCCG_TEST_CLK_GENERICA_INV", 16, 16, &umr_bitfield_default },
	 { "DCCG_TEST_CLK_GENERICA_SEL", 0, 7, &umr_bitfield_default },
	 { "DCCG_TEST_CLK_GENERICB_INV", 24, 24, &umr_bitfield_default },
	 { "DCCG_TEST_CLK_GENERICB_SEL", 8, 15, &umr_bitfield_default },
};
static struct umr_bitfield mmDMIF_ADDR_CONFIG[] = {
	 { "BANK_INTERLEAVE_SIZE", 8, 10, &umr_bitfield_default },
	 { "NUM_LOWER_PIPES", 30, 30, &umr_bitfield_default },
	 { "NUM_PIPES", 0, 2, &umr_bitfield_default },
	 { "NUM_SHADER_ENGINES", 12, 13, &umr_bitfield_default },
	 { "PIPE_INTERLEAVE_SIZE", 4, 6, &umr_bitfield_default },
	 { "ROW_SIZE", 28, 29, &umr_bitfield_default },
	 { "SHADER_ENGINE_TILE_SIZE", 16, 18, &umr_bitfield_default },
};
static struct umr_bitfield mmDMIF_CONTROL[] = {
	 { "DMIF_BUFF_SIZE", 0, 1, &umr_bitfield_default },
	 { "DMIF_CHUNK_BUFF_MARGIN", 29, 30, &umr_bitfield_default },
	 { "DMIF_DELAY_ARBITRATION", 24, 28, &umr_bitfield_default },
	 { "DMIF_DISABLE_EARLY_RECEIVED_LEVEL_COUNT", 4, 4, &umr_bitfield_default },
	 { "DMIF_FORCE_TOTAL_REQ_BURST_SIZE", 12, 15, &umr_bitfield_default },
	 { "DMIF_GROUP_REQUESTS_IN_CHUNK", 2, 2, &umr_bitfield_default },
	 { "DMIF_MAX_TOTAL_OUTSTANDING_CHUNK_REQUESTS", 16, 21, &umr_bitfield_default },
	 { "DMIF_REQ_BURST_SIZE", 8, 10, &umr_bitfield_default },
};
static struct umr_bitfield mmDMIF_STATUS[] = {
	 { "DMIF_CLEAR_MC_SEND_ON_IDLE", 8, 13, &umr_bitfield_default },
	 { "DMIF_MC_LATENCY_COUNTER_ENABLE", 16, 16, &umr_bitfield_default },
	 { "DMIF_MC_LATENCY_COUNTER_SOURCE_SELECT", 20, 22, &umr_bitfield_default },
	 { "DMIF_MC_LATENCY_COUNTER_URGENT_ONLY", 17, 17, &umr_bitfield_default },
	 { "DMIF_MC_SEND_ON_IDLE", 0, 5, &umr_bitfield_default },
	 { "DMIF_PERFORMANCE_COUNTER_SOURCE_SELECT", 24, 26, &umr_bitfield_default },
	 { "DMIF_UNDERFLOW", 28, 28, &umr_bitfield_default },
};
static struct umr_bitfield mmDMIF_HW_DEBUG[] = {
	 { "DMIF_HW_DEBUG", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDMIF_ARBITRATION_CONTROL[] = {
	 { "DMIF_ARBITRATION_REFERENCE_CLOCK_PERIOD", 0, 15, &umr_bitfield_default },
	 { "PIPE_SWITCH_EFFICIENCY_WEIGHT", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmPIPE0_ARBITRATION_CONTROL3[] = {
	 { "EFFICIENCY_WEIGHT", 0, 15, &umr_bitfield_default },
};
static struct umr_bitfield mmPIPE1_ARBITRATION_CONTROL3[] = {
	 { "EFFICIENCY_WEIGHT", 0, 15, &umr_bitfield_default },
};
static struct umr_bitfield mmPIPE2_ARBITRATION_CONTROL3[] = {
	 { "EFFICIENCY_WEIGHT", 0, 15, &umr_bitfield_default },
};
static struct umr_bitfield mmPIPE3_ARBITRATION_CONTROL3[] = {
	 { "EFFICIENCY_WEIGHT", 0, 15, &umr_bitfield_default },
};
static struct umr_bitfield mmPIPE4_ARBITRATION_CONTROL3[] = {
	 { "EFFICIENCY_WEIGHT", 0, 15, &umr_bitfield_default },
};
static struct umr_bitfield mmPIPE5_ARBITRATION_CONTROL3[] = {
	 { "EFFICIENCY_WEIGHT", 0, 15, &umr_bitfield_default },
};
static struct umr_bitfield mmDMIF_ADDR_CALC[] = {
	 { "ADDR_CONFIG_PIPE_INTERLEAVE_SIZE", 4, 6, &umr_bitfield_default },
	 { "ADDR_CONFIG_ROW_SIZE", 28, 29, &umr_bitfield_default },
};
static struct umr_bitfield mmDMIF_STATUS2[] = {
	 { "DMIF_CHUNK_TRACKER_SCLK_STATUS", 8, 8, &umr_bitfield_default },
	 { "DMIF_FBC_TRACKER_SCLK_STATUS", 9, 9, &umr_bitfield_default },
	 { "DMIF_PIPE0_DISPCLK_STATUS", 0, 0, &umr_bitfield_default },
	 { "DMIF_PIPE1_DISPCLK_STATUS", 1, 1, &umr_bitfield_default },
	 { "DMIF_PIPE2_DISPCLK_STATUS", 2, 2, &umr_bitfield_default },
	 { "DMIF_PIPE3_DISPCLK_STATUS", 3, 3, &umr_bitfield_default },
	 { "DMIF_PIPE4_DISPCLK_STATUS", 4, 4, &umr_bitfield_default },
	 { "DMIF_PIPE5_DISPCLK_STATUS", 5, 5, &umr_bitfield_default },
};
static struct umr_bitfield mmPIPE0_MAX_REQUESTS[] = {
	 { "MAX_REQUESTS", 0, 9, &umr_bitfield_default },
};
static struct umr_bitfield mmPIPE1_MAX_REQUESTS[] = {
	 { "MAX_REQUESTS", 0, 9, &umr_bitfield_default },
};
static struct umr_bitfield mmPIPE2_MAX_REQUESTS[] = {
	 { "MAX_REQUESTS", 0, 9, &umr_bitfield_default },
};
static struct umr_bitfield mmPIPE3_MAX_REQUESTS[] = {
	 { "MAX_REQUESTS", 0, 9, &umr_bitfield_default },
};
static struct umr_bitfield mmPIPE4_MAX_REQUESTS[] = {
	 { "MAX_REQUESTS", 0, 9, &umr_bitfield_default },
};
static struct umr_bitfield mmPIPE5_MAX_REQUESTS[] = {
	 { "MAX_REQUESTS", 0, 9, &umr_bitfield_default },
};
static struct umr_bitfield mmDMIF_TEST_DEBUG_INDEX[] = {
	 { "DMIF_TEST_DEBUG_INDEX", 0, 7, &umr_bitfield_default },
	 { "DMIF_TEST_DEBUG_WRITE_EN", 8, 8, &umr_bitfield_default },
};
static struct umr_bitfield mmDMIF_TEST_DEBUG_DATA[] = {
	 { "DMIF_TEST_DEBUG_DATA", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMCIF_CONTROL[] = {
	 { "ADDRESS_TRANSLATION_ENABLE", 4, 4, &umr_bitfield_default },
	 { "LOW_READ_URG_LEVEL", 16, 23, &umr_bitfield_default },
	 { "MC_CLEAN_DEASSERT_LATENCY", 24, 29, &umr_bitfield_default },
	 { "MCIF_BUFF_SIZE", 0, 1, &umr_bitfield_default },
	 { "MCIF_MC_LATENCY_COUNTER_ENABLE", 30, 30, &umr_bitfield_default },
	 { "MCIF_MC_LATENCY_COUNTER_URGENT_ONLY", 31, 31, &umr_bitfield_default },
	 { "MCIF_SLOW_REQ_INTERVAL", 12, 15, &umr_bitfield_default },
	 { "PRIVILEGED_ACCESS_ENABLE", 8, 8, &umr_bitfield_default },
};
static struct umr_bitfield mmMCIF_WRITE_COMBINE_CONTROL[] = {
	 { "MCIF_WRITE_COMBINE_TIMEOUT", 0, 7, &umr_bitfield_default },
	 { "VIP_WRITE_COMBINE_TIMEOUT", 8, 15, &umr_bitfield_default },
};
static struct umr_bitfield mmMCIF_TEST_DEBUG_INDEX[] = {
	 { "MCIF_TEST_DEBUG_INDEX", 0, 7, &umr_bitfield_default },
	 { "MCIF_TEST_DEBUG_WRITE_EN", 8, 8, &umr_bitfield_default },
};
static struct umr_bitfield mmMCIF_TEST_DEBUG_DATA[] = {
	 { "MCIF_TEST_DEBUG_DATA", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMCIF_VMID[] = {
	 { "MCIF_WR_VMID", 0, 3, &umr_bitfield_default },
	 { "VIP_WR_VMID", 4, 7, &umr_bitfield_default },
};
static struct umr_bitfield mmMCIF_MEM_CONTROL[] = {
	 { "MCIFMEM_CACHE_MODE_DIS", 0, 0, &umr_bitfield_default },
	 { "MCIFMEM_CACHE_MODE", 4, 5, &umr_bitfield_default },
	 { "MCIFMEM_CACHE_PIPE", 16, 18, &umr_bitfield_default },
	 { "MCIFMEM_CACHE_SIZE", 8, 14, &umr_bitfield_default },
	 { "MCIFMEM_CACHE_TYPE", 19, 20, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_RBBMIF_RDWR_CNTL1[] = {
	 { "DC_RBBMIF_CLIENT0_RDWR_DELAY", 0, 2, &umr_bitfield_default },
	 { "DC_RBBMIF_CLIENT0_RDWR_TIMEOUT_DIS", 3, 3, &umr_bitfield_default },
	 { "DC_RBBMIF_CLIENT1_RDWR_DELAY", 4, 6, &umr_bitfield_default },
	 { "DC_RBBMIF_CLIENT1_RDWR_TIMEOUT_DIS", 7, 7, &umr_bitfield_default },
	 { "DC_RBBMIF_CLIENT2_RDWR_DELAY", 8, 10, &umr_bitfield_default },
	 { "DC_RBBMIF_CLIENT2_RDWR_TIMEOUT_DIS", 11, 11, &umr_bitfield_default },
	 { "DC_RBBMIF_CLIENT3_RDWR_DELAY", 12, 14, &umr_bitfield_default },
	 { "DC_RBBMIF_CLIENT3_RDWR_TIMEOUT_DIS", 15, 15, &umr_bitfield_default },
	 { "DC_RBBMIF_CLIENT4_RDWR_DELAY", 16, 18, &umr_bitfield_default },
	 { "DC_RBBMIF_CLIENT4_RDWR_TIMEOUT_DIS", 19, 19, &umr_bitfield_default },
};
static struct umr_bitfield mmDCI_MEM_PWR_STATE[] = {
	 { "AZ_MEM_PWR_STATE", 22, 23, &umr_bitfield_default },
	 { "DMCU_IRAM_PWR_STATE", 28, 29, &umr_bitfield_default },
	 { "DMCU_MEM_PWR_STATE", 0, 1, &umr_bitfield_default },
	 { "DMIF0_MEM_PWR_STATE", 2, 3, &umr_bitfield_default },
	 { "DMIF1_MEM_PWR_STATE", 4, 5, &umr_bitfield_default },
	 { "DMIF2_MEM_PWR_STATE", 6, 7, &umr_bitfield_default },
	 { "DMIF3_MEM_PWR_STATE", 8, 9, &umr_bitfield_default },
	 { "DMIF4_MEM_PWR_STATE", 10, 11, &umr_bitfield_default },
	 { "DMIF5_MEM_PWR_STATE", 12, 13, &umr_bitfield_default },
	 { "DMIF_XLR_MEM1_PWR_STATE", 26, 27, &umr_bitfield_default },
	 { "DMIF_XLR_MEM_PWR_STATE", 24, 25, &umr_bitfield_default },
	 { "FBC_MEM_PWR_STATE", 16, 17, &umr_bitfield_default },
	 { "MCIF_MEM_PWR_STATE", 18, 19, &umr_bitfield_default },
	 { "VGA_MEM_PWR_STATE", 14, 15, &umr_bitfield_default },
	 { "VIP_MEM_PWR_STATE", 20, 21, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_DC_INTERFACE_NACK_STATUS[] = {
	 { "DMIF_RDRET_NACK_CLEAR", 4, 4, &umr_bitfield_default },
	 { "DMIF_RDRET_NACK_OCCURRED", 0, 0, &umr_bitfield_default },
	 { "MCIF_RDRET_NACK_CLEAR", 20, 20, &umr_bitfield_default },
	 { "MCIF_RDRET_NACK_OCCURRED", 16, 16, &umr_bitfield_default },
	 { "MCIF_WRRET_NACK_CLEAR", 28, 28, &umr_bitfield_default },
	 { "MCIF_WRRET_NACK_OCCURRED", 24, 24, &umr_bitfield_default },
	 { "VIP_WRRET_NACK_CLEAR", 12, 12, &umr_bitfield_default },
	 { "VIP_WRRET_NACK_OCCURRED", 8, 8, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_RBBMIF_RDWR_CNTL2[] = {
	 { "DC_RBBMIF_CLIENT8_RDWR_DELAY", 0, 2, &umr_bitfield_default },
	 { "DC_RBBMIF_CLIENT8_RDWR_TIMEOUT_DIS", 3, 3, &umr_bitfield_default },
	 { "DC_RBBMIF_CLIENT9_RDWR_DELAY", 4, 6, &umr_bitfield_default },
	 { "DC_RBBMIF_CLIENT9_RDWR_TIMEOUT_DIS", 7, 7, &umr_bitfield_default },
};
static struct umr_bitfield mmDCI_CLK_CNTL[] = {
	 { "DCI_PG_TEST_CLK_SEL", 27, 31, &umr_bitfield_default },
	 { "DCI_TEST_CLK_SEL", 0, 4, &umr_bitfield_default },
	 { "DISPCLK_G_DMCU_GATE_DIS", 15, 15, &umr_bitfield_default },
	 { "DISPCLK_G_DMIF0_GATE_DIS", 16, 16, &umr_bitfield_default },
	 { "DISPCLK_G_DMIF1_GATE_DIS", 17, 17, &umr_bitfield_default },
	 { "DISPCLK_G_DMIF2_GATE_DIS", 18, 18, &umr_bitfield_default },
	 { "DISPCLK_G_DMIF3_GATE_DIS", 19, 19, &umr_bitfield_default },
	 { "DISPCLK_G_DMIF4_GATE_DIS", 20, 20, &umr_bitfield_default },
	 { "DISPCLK_G_DMIF5_GATE_DIS", 21, 21, &umr_bitfield_default },
	 { "DISPCLK_G_FBC_GATE_DIS", 9, 9, &umr_bitfield_default },
	 { "DISPCLK_G_VGA_GATE_DIS", 11, 11, &umr_bitfield_default },
	 { "DISPCLK_G_VIP_GATE_DIS", 13, 13, &umr_bitfield_default },
	 { "DISPCLK_M_GATE_DIS", 6, 6, &umr_bitfield_default },
	 { "DISPCLK_R_DCI_GATE_DIS", 5, 5, &umr_bitfield_default },
	 { "DISPCLK_R_DMCU_GATE_DIS", 14, 14, &umr_bitfield_default },
	 { "DISPCLK_R_VGA_GATE_DIS", 10, 10, &umr_bitfield_default },
	 { "DISPCLK_R_VIP_GATE_DIS", 12, 12, &umr_bitfield_default },
	 { "SCLK_G_DMIF_GATE_DIS", 22, 22, &umr_bitfield_default },
	 { "SCLK_G_DMIFTRK_GATE_DIS", 23, 23, &umr_bitfield_default },
	 { "SCLK_R_AZ_GATE_DIS", 8, 8, &umr_bitfield_default },
};
static struct umr_bitfield mmDCCG_VPCLK_CNTL[] = {
	 { "AZ_LIGHT_SLEEP_DIS", 2, 2, &umr_bitfield_default },
	 { "AZ_MEM_SHUTDOWN_DIS", 26, 26, &umr_bitfield_default },
	 { "DCCG_VPCLK_POL", 0, 0, &umr_bitfield_default },
	 { "DMCU_LIGHT_SLEEP_DIS", 3, 3, &umr_bitfield_default },
	 { "DMCU_MEM_SHUTDOWN_DIS", 16, 16, &umr_bitfield_default },
	 { "DMIF0_LIGHT_SLEEP_DIS", 8, 8, &umr_bitfield_default },
	 { "DMIF0_MEM_SHUTDOWN_DIS", 20, 20, &umr_bitfield_default },
	 { "DMIF1_LIGHT_SLEEP_DIS", 9, 9, &umr_bitfield_default },
	 { "DMIF1_MEM_SHUTDOWN_DIS", 21, 21, &umr_bitfield_default },
	 { "DMIF2_LIGHT_SLEEP_DIS", 10, 10, &umr_bitfield_default },
	 { "DMIF2_MEM_SHUTDOWN_DIS", 22, 22, &umr_bitfield_default },
	 { "DMIF3_LIGHT_SLEEP_DIS", 11, 11, &umr_bitfield_default },
	 { "DMIF3_MEM_SHUTDOWN_DIS", 23, 23, &umr_bitfield_default },
	 { "DMIF4_LIGHT_SLEEP_DIS", 12, 12, &umr_bitfield_default },
	 { "DMIF4_MEM_SHUTDOWN_DIS", 24, 24, &umr_bitfield_default },
	 { "DMIF5_LIGHT_SLEEP_DIS", 13, 13, &umr_bitfield_default },
	 { "DMIF5_MEM_SHUTDOWN_DIS", 25, 25, &umr_bitfield_default },
	 { "DMIF_XLR_LIGHT_SLEEP_MODE_FORCE", 5, 5, &umr_bitfield_default },
	 { "DMIF_XLR_MEM_SHUTDOWN_MODE_FORCE", 18, 18, &umr_bitfield_default },
	 { "FBC_LIGHT_SLEEP_DIS", 14, 14, &umr_bitfield_default },
	 { "FBC_MEM_SHUTDOWN_DIS", 19, 19, &umr_bitfield_default },
	 { "MCIF_LIGHT_SLEEP_MODE_FORCE", 4, 4, &umr_bitfield_default },
	 { "MCIF_MEM_SHUTDOWN_MODE_FORCE", 17, 17, &umr_bitfield_default },
	 { "VGA_LIGHT_SLEEP_MODE_FORCE", 1, 1, &umr_bitfield_default },
	 { "VIP_LIGHT_SLEEP_DIS", 15, 15, &umr_bitfield_default },
};
static struct umr_bitfield mmDCI_TEST_DEBUG_INDEX[] = {
	 { "DCI_TEST_DEBUG_INDEX", 0, 7, &umr_bitfield_default },
	 { "DCI_TEST_DEBUG_WRITE_EN", 8, 8, &umr_bitfield_default },
};
static struct umr_bitfield mmDCI_TEST_DEBUG_DATA[] = {
	 { "DCI_TEST_DEBUG_DATA", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCI_MEM_PWR_STATE2[] = {
	 { "DMCU_ERAM1_PWR_STATE", 0, 1, &umr_bitfield_default },
	 { "DMCU_ERAM2_PWR_STATE", 2, 3, &umr_bitfield_default },
	 { "DMCU_ERAM3_PWR_STATE", 4, 5, &umr_bitfield_default },
};
static struct umr_bitfield mmDCI_DEBUG_CONFIG[] = {
	 { "DCI_DBG_SEL", 0, 3, &umr_bitfield_default },
};
static struct umr_bitfield mmLOW_POWER_TILING_CONTROL[] = {
	 { "LOW_POWER_TILING_ENABLE", 0, 0, &umr_bitfield_default },
	 { "LOW_POWER_TILING_MODE", 3, 4, &umr_bitfield_default },
	 { "LOW_POWER_TILING_NUM_BANKS", 8, 10, &umr_bitfield_default },
	 { "LOW_POWER_TILING_NUM_PIPES", 5, 7, &umr_bitfield_default },
	 { "LOW_POWER_TILING_PIPE_INTERLEAVE_SIZE", 11, 11, &umr_bitfield_default },
	 { "LOW_POWER_TILING_ROW_SIZE", 12, 14, &umr_bitfield_default },
	 { "LOW_POWER_TILING_ROWS_PER_CHAN", 16, 27, &umr_bitfield_default },
};
static struct umr_bitfield mmDCI_MEM_PWR_CNTL[] = {
	 { "DMIF0_ASYNC_LIGHT_SLEEP_DIS", 0, 0, &umr_bitfield_default },
	 { "DMIF0_ASYNC_MEM_PWR_STATE", 12, 13, &umr_bitfield_default },
	 { "DMIF0_ASYNC_MEM_SHUTDOWN_DIS", 6, 6, &umr_bitfield_default },
	 { "DMIF1_ASYNC_LIGHT_SLEEP_DIS", 1, 1, &umr_bitfield_default },
	 { "DMIF1_ASYNC_MEM_PWR_STATE", 14, 15, &umr_bitfield_default },
	 { "DMIF1_ASYNC_MEM_SHUTDOWN_DIS", 7, 7, &umr_bitfield_default },
	 { "DMIF2_ASYNC_LIGHT_SLEEP_DIS", 2, 2, &umr_bitfield_default },
	 { "DMIF2_ASYNC_MEM_PWR_STATE", 16, 17, &umr_bitfield_default },
	 { "DMIF2_ASYNC_MEM_SHUTDOWN_DIS", 8, 8, &umr_bitfield_default },
	 { "DMIF3_ASYNC_LIGHT_SLEEP_DIS", 3, 3, &umr_bitfield_default },
	 { "DMIF3_ASYNC_MEM_PWR_STATE", 18, 19, &umr_bitfield_default },
	 { "DMIF3_ASYNC_MEM_SHUTDOWN_DIS", 9, 9, &umr_bitfield_default },
	 { "DMIF4_ASYNC_LIGHT_SLEEP_DIS", 4, 4, &umr_bitfield_default },
	 { "DMIF4_ASYNC_MEM_PWR_STATE", 20, 21, &umr_bitfield_default },
	 { "DMIF4_ASYNC_MEM_SHUTDOWN_DIS", 10, 10, &umr_bitfield_default },
	 { "DMIF5_ASYNC_LIGHT_SLEEP_DIS", 5, 5, &umr_bitfield_default },
	 { "DMIF5_ASYNC_MEM_PWR_STATE", 22, 23, &umr_bitfield_default },
	 { "DMIF5_ASYNC_MEM_SHUTDOWN_DIS", 11, 11, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_XDMA_INTERFACE_CNTL[] = {
	 { "DC_FLIP_PENDING_TO_DCP", 22, 22, &umr_bitfield_default },
	 { "DC_XDMA_FLIP_PENDING", 16, 16, &umr_bitfield_default },
	 { "XDMA_M_FLIP_PENDING_TO_DCP", 20, 20, &umr_bitfield_default },
	 { "XDMA_PIPE_ENABLE", 0, 5, &umr_bitfield_default },
	 { "XDMA_PIPE_SEL", 8, 10, &umr_bitfield_default },
	 { "XDMA_S_FLIP_PENDING_TO_DCP", 21, 21, &umr_bitfield_default },
};
static struct umr_bitfield mmPIPE0_DMIF_BUFFER_CONTROL[] = {
	 { "DMIF_BUFFERS_ALLOCATED", 0, 2, &umr_bitfield_default },
	 { "DMIF_BUFFERS_ALLOCATION_COMPLETED", 4, 4, &umr_bitfield_default },
};
static struct umr_bitfield mmPIPE1_DMIF_BUFFER_CONTROL[] = {
	 { "DMIF_BUFFERS_ALLOCATED", 0, 2, &umr_bitfield_default },
	 { "DMIF_BUFFERS_ALLOCATION_COMPLETED", 4, 4, &umr_bitfield_default },
};
static struct umr_bitfield mmPIPE2_DMIF_BUFFER_CONTROL[] = {
	 { "DMIF_BUFFERS_ALLOCATED", 0, 2, &umr_bitfield_default },
	 { "DMIF_BUFFERS_ALLOCATION_COMPLETED", 4, 4, &umr_bitfield_default },
};
static struct umr_bitfield mmPIPE3_DMIF_BUFFER_CONTROL[] = {
	 { "DMIF_BUFFERS_ALLOCATED", 0, 2, &umr_bitfield_default },
	 { "DMIF_BUFFERS_ALLOCATION_COMPLETED", 4, 4, &umr_bitfield_default },
};
static struct umr_bitfield mmPIPE4_DMIF_BUFFER_CONTROL[] = {
	 { "DMIF_BUFFERS_ALLOCATED", 0, 2, &umr_bitfield_default },
	 { "DMIF_BUFFERS_ALLOCATION_COMPLETED", 4, 4, &umr_bitfield_default },
};
static struct umr_bitfield mmPIPE5_DMIF_BUFFER_CONTROL[] = {
	 { "DMIF_BUFFERS_ALLOCATED", 0, 2, &umr_bitfield_default },
	 { "DMIF_BUFFERS_ALLOCATION_COMPLETED", 4, 4, &umr_bitfield_default },
};
static struct umr_bitfield mmXDMA_MSTR_CNTL[] = {
	 { "XDMA_MSTR_DEBUG_MODE", 18, 18, &umr_bitfield_default },
	 { "XDMA_MSTR_ENABLE", 16, 16, &umr_bitfield_default },
	 { "XDMA_MSTR_MEM_READY", 9, 9, &umr_bitfield_default },
	 { "XDMA_MSTR_SOFT_RESET", 20, 20, &umr_bitfield_default },
};
static struct umr_bitfield mmXDMA_MSTR_READ_COMMAND[] = {
	 { "XDMA_MSTR_REQUEST_PREFETCH", 16, 29, &umr_bitfield_default },
	 { "XDMA_MSTR_REQUEST_SIZE", 0, 13, &umr_bitfield_default },
};
static struct umr_bitfield mmXDMA_MSTR_HEIGHT[] = {
	 { "XDMA_MSTR_ACTIVE_HEIGHT", 0, 13, &umr_bitfield_default },
	 { "XDMA_MSTR_FRAME_HEIGHT", 16, 29, &umr_bitfield_default },
};
static struct umr_bitfield mmXDMA_MSTR_REMOTE_SURFACE_BASE[] = {
	 { "XDMA_MSTR_REMOTE_SURFACE_BASE", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmXDMA_MSTR_REMOTE_SURFACE_BASE_HIGH[] = {
	 { "XDMA_MSTR_REMOTE_SURFACE_BASE_HIGH", 0, 7, &umr_bitfield_default },
};
static struct umr_bitfield mmXDMA_MSTR_REMOTE_GPU_ADDRESS[] = {
	 { "XDMA_MSTR_REMOTE_GPU_ADDRESS", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmXDMA_MSTR_REMOTE_GPU_ADDRESS_HIGH[] = {
	 { "XDMA_MSTR_REMOTE_GPU_ADDRESS_HIGH", 0, 7, &umr_bitfield_default },
};
static struct umr_bitfield mmXDMA_MSTR_STATUS[] = {
	 { "XDMA_MSTR_VCOUNT_CURRENT", 0, 13, &umr_bitfield_default },
	 { "XDMA_MSTR_WRITE_LINE_CURRENT", 16, 29, &umr_bitfield_default },
};
static struct umr_bitfield mmXDMA_MC_PCIE_CLIENT_CONFIG[] = {
	 { "XDMA_MC_PCIE_PRIV", 16, 16, &umr_bitfield_default },
	 { "XDMA_MC_PCIE_SWAP", 8, 9, &umr_bitfield_default },
	 { "XDMA_MC_PCIE_VMID", 12, 15, &umr_bitfield_default },
};
static struct umr_bitfield mmXDMA_MSTR_MEM_CLIENT_CONFIG[] = {
	 { "XDMA_MSTR_MEM_CLIENT_PRIV", 16, 16, &umr_bitfield_default },
	 { "XDMA_MSTR_MEM_CLIENT_SWAP", 8, 9, &umr_bitfield_default },
	 { "XDMA_MSTR_MEM_CLIENT_VMID", 12, 15, &umr_bitfield_default },
};
static struct umr_bitfield mmXDMA_MSTR_LOCAL_SURFACE_BASE_ADDR[] = {
	 { "XDMA_MSTR_LOCAL_SURFACE_BASE_ADDR", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmXDMA_MSTR_LOCAL_SURFACE_BASE_ADDR_HIGH[] = {
	 { "XDMA_MSTR_LOCAL_SURFACE_BASE_ADDR_HIGH", 0, 7, &umr_bitfield_default },
};
static struct umr_bitfield mmXDMA_MSTR_LOCAL_SURFACE_PITCH[] = {
	 { "XDMA_MSTR_LOCAL_SURFACE_PITCH", 0, 13, &umr_bitfield_default },
};
static struct umr_bitfield mmXDMA_LOCAL_SURFACE_TILING1[] = {
	 { "XDMA_LOCAL_ARRAY_MODE", 0, 3, &umr_bitfield_default },
	 { "XDMA_LOCAL_BANK_HEIGHT", 10, 11, &umr_bitfield_default },
	 { "XDMA_LOCAL_BANK_WIDTH", 8, 9, &umr_bitfield_default },
	 { "XDMA_LOCAL_MACRO_TILE_ASPECT", 12, 13, &umr_bitfield_default },
	 { "XDMA_LOCAL_NUM_BANKS", 20, 21, &umr_bitfield_default },
	 { "XDMA_LOCAL_TILE_SPLIT", 4, 6, &umr_bitfield_default },
};
static struct umr_bitfield mmXDMA_LOCAL_SURFACE_TILING2[] = {
	 { "XDMA_LOCAL_MICRO_TILE_MODE", 22, 23, &umr_bitfield_default },
	 { "XDMA_LOCAL_PIPE_CONFIG", 27, 31, &umr_bitfield_default },
	 { "XDMA_LOCAL_PIPE_INTERLEAVE_SIZE", 0, 2, &umr_bitfield_default },
};
static struct umr_bitfield mmXDMA_MSTR_CMD_URGENT_CNTL[] = {
	 { "XDMA_MSTR_CMD_URGENT_LEVEL", 8, 11, &umr_bitfield_default },
};
static struct umr_bitfield mmXDMA_MSTR_MEM_URGENT_CNTL[] = {
	 { "XDMA_MSTR_MEM_CLIENT_STALL", 0, 0, &umr_bitfield_default },
	 { "XDMA_MSTR_MEM_STALL_DELAY", 12, 15, &umr_bitfield_default },
	 { "XDMA_MSTR_MEM_URGENT_LEVEL", 8, 11, &umr_bitfield_default },
	 { "XDMA_MSTR_MEM_URGENT_LIMIT", 4, 7, &umr_bitfield_default },
	 { "XDMA_MSTR_MEM_URGENT_TIMER", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmXDMA_SLV_CNTL[] = {
	 { "XDMA_SLV_ACTIVE", 8, 8, &umr_bitfield_default },
	 { "XDMA_SLV_ENABLE", 16, 16, &umr_bitfield_default },
	 { "XDMA_SLV_MEM_READY", 9, 9, &umr_bitfield_default },
	 { "XDMA_SLV_READ_LAT_TEST_EN", 19, 19, &umr_bitfield_default },
	 { "XDMA_SLV_SOFT_RESET", 20, 20, &umr_bitfield_default },
};
static struct umr_bitfield mmXDMA_SLV_MEM_CLIENT_CONFIG[] = {
	 { "XDMA_SLV_MEM_CLIENT_PRIV", 16, 16, &umr_bitfield_default },
	 { "XDMA_SLV_MEM_CLIENT_SWAP", 8, 9, &umr_bitfield_default },
	 { "XDMA_SLV_MEM_CLIENT_VMID", 12, 15, &umr_bitfield_default },
};
static struct umr_bitfield mmXDMA_SLV_SLS_PITCH[] = {
	 { "XDMA_SLV_SLS_PITCH", 0, 13, &umr_bitfield_default },
	 { "XDMA_SLV_SLS_WIDTH", 16, 29, &umr_bitfield_default },
};
static struct umr_bitfield mmXDMA_SLV_READ_URGENT_CNTL[] = {
	 { "XDMA_SLV_READ_CLIENT_STALL", 0, 0, &umr_bitfield_default },
	 { "XDMA_SLV_READ_STALL_DELAY", 12, 15, &umr_bitfield_default },
	 { "XDMA_SLV_READ_URGENT_LEVEL", 8, 11, &umr_bitfield_default },
	 { "XDMA_SLV_READ_URGENT_LIMIT", 4, 7, &umr_bitfield_default },
	 { "XDMA_SLV_READ_URGENT_TIMER", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmXDMA_SLV_WRITE_URGENT_CNTL[] = {
	 { "XDMA_SLV_WRITE_STALL_DELAY", 12, 15, &umr_bitfield_default },
	 { "XDMA_SLV_WRITE_STALL", 0, 0, &umr_bitfield_default },
	 { "XDMA_SLV_WRITE_URGENT_LEVEL", 8, 11, &umr_bitfield_default },
};
static struct umr_bitfield mmXDMA_SLV_WB_RATE_CNTL[] = {
	 { "XDMA_SLV_WB_BURST_PERIOD", 16, 31, &umr_bitfield_default },
	 { "XDMA_SLV_WB_BURST_SIZE", 0, 8, &umr_bitfield_default },
};
static struct umr_bitfield mmXDMA_SLV_REMOTE_GPU_ADDRESS[] = {
	 { "XDMA_SLV_REMOTE_GPU_ADDRESS", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmXDMA_SLV_REMOTE_GPU_ADDRESS_HIGH[] = {
	 { "XDMA_SLV_REMOTE_GPU_ADDRESS_HIGH", 0, 7, &umr_bitfield_default },
};
static struct umr_bitfield mmXDMA_SLV_READ_LATENCY_MINMAX[] = {
	 { "XDMA_SLV_READ_LATENCY_MAX", 16, 31, &umr_bitfield_default },
	 { "XDMA_SLV_READ_LATENCY_MIN", 0, 15, &umr_bitfield_default },
};
static struct umr_bitfield mmXDMA_SLV_READ_LATENCY_AVE[] = {
	 { "XDMA_SLV_READ_LATENCY_ACC", 0, 19, &umr_bitfield_default },
	 { "XDMA_SLV_READ_LATENCY_COUNT", 20, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmXDMA_INTERRUPT[] = {
	 { "XDMA_MSTR_MEM_URGENT_ACK", 10, 10, &umr_bitfield_default },
	 { "XDMA_MSTR_MEM_URGENT_MASK", 9, 9, &umr_bitfield_default },
	 { "XDMA_MSTR_MEM_URGENT_STAT", 8, 8, &umr_bitfield_default },
	 { "XDMA_MSTR_UNDERFLOW_ACK", 14, 14, &umr_bitfield_default },
	 { "XDMA_MSTR_UNDERFLOW_MASK", 13, 13, &umr_bitfield_default },
	 { "XDMA_MSTR_UNDERFLOW_STAT", 12, 12, &umr_bitfield_default },
	 { "XDMA_SLV_READ_URGENT_ACK", 18, 18, &umr_bitfield_default },
	 { "XDMA_SLV_READ_URGENT_MASK", 17, 17, &umr_bitfield_default },
	 { "XDMA_SLV_READ_URGENT_STAT", 16, 16, &umr_bitfield_default },
};
static struct umr_bitfield mmXDMA_SLV_FLIP_PENDING[] = {
	 { "XDMA_SLV_FLIP_PENDING", 0, 0, &umr_bitfield_default },
};
static struct umr_bitfield mmXDMA_CLOCK_GATING_CNTL[] = {
	 { "XDMA_SCLK_GATE_DIS", 15, 15, &umr_bitfield_default },
	 { "XDMA_SCLK_G_MSTAT_GATE_DIS", 19, 19, &umr_bitfield_default },
	 { "XDMA_SCLK_G_SDYN_GATE_DIS", 18, 18, &umr_bitfield_default },
	 { "XDMA_SCLK_G_SSTAT_GATE_DIS", 20, 20, &umr_bitfield_default },
	 { "XDMA_SCLK_REG_GATE_DIS", 16, 16, &umr_bitfield_default },
	 { "XDMA_SCLK_TURN_OFF_DELAY", 4, 11, &umr_bitfield_default },
	 { "XDMA_SCLK_TURN_ON_DELAY", 0, 3, &umr_bitfield_default },
};
static struct umr_bitfield mmXDMA_RBBMIF_RDWR_CNTL[] = {
	 { "XDMA_RBBMIF_RDWR_DELAY", 0, 2, &umr_bitfield_default },
	 { "XDMA_RBBMIF_RDWR_TIMEOUT_DIS", 3, 3, &umr_bitfield_default },
	 { "XDMA_RBBMIF_TIMEOUT_DELAY", 15, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmXDMA_MEM_POWER_CNTL[] = {
	 { "XDMA_MEM_LIGHT_SLEEP_DIS", 0, 0, &umr_bitfield_default },
	 { "XDMA_MEM_LIGHT_SLEEP_MODE_FORCE", 16, 16, &umr_bitfield_default },
	 { "XDMA_MEM_POWER_STATE", 30, 31, &umr_bitfield_default },
	 { "XDMA_MEM_SHUTDOWN_DIS", 8, 8, &umr_bitfield_default },
	 { "XDMA_MEM_SHUTDOWN_MODE_FORCE", 24, 24, &umr_bitfield_default },
};
static struct umr_bitfield mmXDMA_MSTR_PCIE_NACK_STATUS[] = {
	 { "XDMA_MSTR_PCIE_NACK_CLR", 16, 16, &umr_bitfield_default },
	 { "XDMA_MSTR_PCIE_NACK", 12, 13, &umr_bitfield_default },
	 { "XDMA_MSTR_PCIE_NACK_TAG", 0, 9, &umr_bitfield_default },
};
static struct umr_bitfield mmXDMA_MSTR_MEM_NACK_STATUS[] = {
	 { "XDMA_MSTR_MEM_NACK_CLR", 16, 16, &umr_bitfield_default },
	 { "XDMA_MSTR_MEM_NACK", 12, 13, &umr_bitfield_default },
	 { "XDMA_MSTR_MEM_NACK_TAG", 0, 9, &umr_bitfield_default },
};
static struct umr_bitfield mmXDMA_SLV_PCIE_NACK_STATUS[] = {
	 { "XDMA_SLV_PCIE_NACK_CLR", 16, 16, &umr_bitfield_default },
	 { "XDMA_SLV_PCIE_NACK", 12, 13, &umr_bitfield_default },
	 { "XDMA_SLV_PCIE_NACK_TAG", 0, 9, &umr_bitfield_default },
};
static struct umr_bitfield mmXDMA_SLV_MEM_NACK_STATUS[] = {
	 { "XDMA_SLV_MEM_NACK_CLR", 31, 31, &umr_bitfield_default },
	 { "XDMA_SLV_MEM_NACK", 16, 17, &umr_bitfield_default },
	 { "XDMA_SLV_MEM_NACK_TAG", 0, 15, &umr_bitfield_default },
};
static struct umr_bitfield mmXDMA_SLV_READ_LATENCY_TIMER[] = {
	 { "XDMA_SLV_READ_LATENCY_TIMER", 0, 15, &umr_bitfield_default },
};
static struct umr_bitfield mmXDMA_IF_BIF_STATUS[] = {
	 { "XDMA_IF_BIF_ERROR_CLEAR", 8, 8, &umr_bitfield_default },
	 { "XDMA_IF_BIF_ERROR_STATUS", 0, 3, &umr_bitfield_default },
};
static struct umr_bitfield mmXDMA_TEST_DEBUG_INDEX[] = {
	 { "XDMA_TEST_DEBUG_INDEX", 0, 7, &umr_bitfield_default },
	 { "XDMA_TEST_DEBUG_WRITE_EN", 8, 8, &umr_bitfield_default },
};
static struct umr_bitfield mmXDMA_TEST_DEBUG_DATA[] = {
	 { "XDMA_TEST_DEBUG_DATA", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixAZALIA_F2_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID[] = {
	 { "AZALIA_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixAZALIA_F2_CODEC_ROOT_PARAMETER_REVISION_ID[] = {
	 { "AZALIA_CODEC_ROOT_PARAMETER_REVISION_ID", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixAZALIA_F2_CODEC_ROOT_PARAMETER_SUBORDINATE_NODE_COUNT[] = {
	 { "AZALIA_CODEC_ROOT_PARAMETER_SUBORDINATE_NODE_COUNT", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDMCU_CTRL[] = {
	 { "DISABLE_IRQ_TO_UC", 2, 2, &umr_bitfield_default },
	 { "DISABLE_XIRQ_TO_UC", 3, 3, &umr_bitfield_default },
	 { "DMCU_ENABLE", 4, 4, &umr_bitfield_default },
	 { "IGNORE_PWRMGT", 1, 1, &umr_bitfield_default },
	 { "RESET_UC", 0, 0, &umr_bitfield_default },
	 { "UC_REG_RD_TIMEOUT", 22, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDMCU_STATUS[] = {
	 { "UC_IN_RESET", 0, 0, &umr_bitfield_default },
	 { "UC_IN_STOP_MODE", 2, 2, &umr_bitfield_default },
	 { "UC_IN_WAIT_MODE", 1, 1, &umr_bitfield_default },
};
static struct umr_bitfield mmDMCU_PC_START_ADDR[] = {
	 { "PC_START_ADDR_LSB", 0, 7, &umr_bitfield_default },
	 { "PC_START_ADDR_MSB", 8, 15, &umr_bitfield_default },
};
static struct umr_bitfield mmDMCU_FW_START_ADDR[] = {
	 { "FW_START_ADDR_LSB", 0, 7, &umr_bitfield_default },
	 { "FW_START_ADDR_MSB", 8, 15, &umr_bitfield_default },
};
static struct umr_bitfield mmDMCU_FW_END_ADDR[] = {
	 { "FW_END_ADDR_LSB", 0, 7, &umr_bitfield_default },
	 { "FW_END_ADDR_MSB", 8, 15, &umr_bitfield_default },
};
static struct umr_bitfield mmDMCU_FW_ISR_START_ADDR[] = {
	 { "FW_ISR_START_ADDR_LSB", 0, 7, &umr_bitfield_default },
	 { "FW_ISR_START_ADDR_MSB", 8, 15, &umr_bitfield_default },
};
static struct umr_bitfield mmDMCU_FW_CS_HI[] = {
	 { "FW_CHECKSUM_HI", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDMCU_FW_CS_LO[] = {
	 { "FW_CHECKSUM_LO", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDMCU_RAM_ACCESS_CTRL[] = {
	 { "ERAM_HOST_ACCESS_EN", 4, 4, &umr_bitfield_default },
	 { "ERAM_RD_ADDR_AUTO_INC", 1, 1, &umr_bitfield_default },
	 { "ERAM_WR_ADDR_AUTO_INC", 0, 0, &umr_bitfield_default },
	 { "IRAM_HOST_ACCESS_EN", 5, 5, &umr_bitfield_default },
	 { "IRAM_RD_ADDR_AUTO_INC", 3, 3, &umr_bitfield_default },
	 { "IRAM_WR_ADDR_AUTO_INC", 2, 2, &umr_bitfield_default },
	 { "UC_RST_RELEASE_DELAY_CNT", 8, 15, &umr_bitfield_default },
};
static struct umr_bitfield mmDMCU_ERAM_WR_CTRL[] = {
	 { "ERAM_WR_ADDR", 0, 15, &umr_bitfield_default },
	 { "ERAM_WR_BE", 16, 19, &umr_bitfield_default },
	 { "ERAM_WR_BYTE_MODE", 20, 20, &umr_bitfield_default },
};
static struct umr_bitfield mmDMCU_ERAM_WR_DATA[] = {
	 { "ERAM_WR_DATA", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDMCU_ERAM_RD_CTRL[] = {
	 { "ERAM_RD_ADDR", 0, 15, &umr_bitfield_default },
	 { "ERAM_RD_BE", 16, 19, &umr_bitfield_default },
	 { "ERAM_RD_BYTE_MODE", 20, 20, &umr_bitfield_default },
};
static struct umr_bitfield mmDMCU_ERAM_RD_DATA[] = {
	 { "ERAM_RD_DATA", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDMCU_IRAM_WR_CTRL[] = {
	 { "IRAM_WR_ADDR", 0, 9, &umr_bitfield_default },
};
static struct umr_bitfield mmDMCU_IRAM_WR_DATA[] = {
	 { "IRAM_WR_DATA", 0, 7, &umr_bitfield_default },
};
static struct umr_bitfield mmDMCU_IRAM_RD_CTRL[] = {
	 { "IRAM_RD_ADDR", 0, 9, &umr_bitfield_default },
};
static struct umr_bitfield mmDMCU_IRAM_RD_DATA[] = {
	 { "IRAM_RD_DATA", 0, 7, &umr_bitfield_default },
};
static struct umr_bitfield mmDMCU_EVENT_TRIGGER[] = {
	 { "GEN_SW_INT_TO_UC", 0, 0, &umr_bitfield_default },
	 { "GEN_UC_INTERNAL_INT_TO_HOST", 23, 23, &umr_bitfield_default },
	 { "UC_INTERNAL_INT_CODE", 16, 22, &umr_bitfield_default },
};
static struct umr_bitfield mmDMCU_UC_INTERNAL_INT_STATUS[] = {
	 { "UC_INT_ILLEGAL_OPCODE_TRAP", 3, 3, &umr_bitfield_default },
	 { "UC_INT_IRQ_N_PIN", 0, 0, &umr_bitfield_default },
	 { "UC_INT_PULSE_ACCUMULATOR_INPUT_EDGE", 14, 14, &umr_bitfield_default },
	 { "UC_INT_PULSE_ACCUMULATOR_OVERFLOW", 15, 15, &umr_bitfield_default },
	 { "UC_INT_REAL_TIME_INTERRUPT", 9, 9, &umr_bitfield_default },
	 { "UC_INT_SOFTWARE_INTERRUPT", 2, 2, &umr_bitfield_default },
	 { "UC_INT_TIMER_INPUT_CAPTURE_1", 13, 13, &umr_bitfield_default },
	 { "UC_INT_TIMER_INPUT_CAPTURE_2", 12, 12, &umr_bitfield_default },
	 { "UC_INT_TIMER_INPUT_CAPTURE_3", 11, 11, &umr_bitfield_default },
	 { "UC_INT_TIMER_INPUT_CAPTURE_4_OUTPUT_COMPARE_5", 10, 10, &umr_bitfield_default },
	 { "UC_INT_TIMER_OUTPUT_COMPARE_1", 7, 7, &umr_bitfield_default },
	 { "UC_INT_TIMER_OUTPUT_COMPARE_2", 6, 6, &umr_bitfield_default },
	 { "UC_INT_TIMER_OUTPUT_COMPARE_3", 5, 5, &umr_bitfield_default },
	 { "UC_INT_TIMER_OUTPUT_COMPARE_4", 4, 4, &umr_bitfield_default },
	 { "UC_INT_TIMER_OVERFLOW", 8, 8, &umr_bitfield_default },
	 { "UC_INT_XIRQ_N_PIN", 1, 1, &umr_bitfield_default },
};
static struct umr_bitfield mmDMCU_INTERRUPT_STATUS[] = {
	 { "ABM1_BL_UPDATE_INT_CLEAR", 2, 2, &umr_bitfield_default },
	 { "ABM1_BL_UPDATE_INT_OCCURRED", 2, 2, &umr_bitfield_default },
	 { "ABM1_HG_READY_INT_CLEAR", 0, 0, &umr_bitfield_default },
	 { "ABM1_HG_READY_INT_OCCURRED", 0, 0, &umr_bitfield_default },
	 { "ABM1_LS_READY_INT_CLEAR", 1, 1, &umr_bitfield_default },
	 { "ABM1_LS_READY_INT_OCCURRED", 1, 1, &umr_bitfield_default },
	 { "DCPG_IHC_DCFE0_POWER_DOWN_INT_CLEAR", 18, 18, &umr_bitfield_default },
	 { "DCPG_IHC_DCFE0_POWER_DOWN_INT_OCCURRED", 18, 18, &umr_bitfield_default },
	 { "DCPG_IHC_DCFE0_POWER_UP_INT_CLEAR", 12, 12, &umr_bitfield_default },
	 { "DCPG_IHC_DCFE0_POWER_UP_INT_OCCURRED", 12, 12, &umr_bitfield_default },
	 { "DCPG_IHC_DCFE1_POWER_DOWN_INT_CLEAR", 19, 19, &umr_bitfield_default },
	 { "DCPG_IHC_DCFE1_POWER_DOWN_INT_OCCURRED", 19, 19, &umr_bitfield_default },
	 { "DCPG_IHC_DCFE1_POWER_UP_INT_CLEAR", 13, 13, &umr_bitfield_default },
	 { "DCPG_IHC_DCFE1_POWER_UP_INT_OCCURRED", 13, 13, &umr_bitfield_default },
	 { "DCPG_IHC_DCFE2_POWER_DOWN_INT_CLEAR", 20, 20, &umr_bitfield_default },
	 { "DCPG_IHC_DCFE2_POWER_DOWN_INT_OCCURRED", 20, 20, &umr_bitfield_default },
	 { "DCPG_IHC_DCFE2_POWER_UP_INT_CLEAR", 14, 14, &umr_bitfield_default },
	 { "DCPG_IHC_DCFE2_POWER_UP_INT_OCCURRED", 14, 14, &umr_bitfield_default },
	 { "DCPG_IHC_DCFE3_POWER_DOWN_INT_CLEAR", 21, 21, &umr_bitfield_default },
	 { "DCPG_IHC_DCFE3_POWER_DOWN_INT_OCCURRED", 21, 21, &umr_bitfield_default },
	 { "DCPG_IHC_DCFE3_POWER_UP_INT_CLEAR", 15, 15, &umr_bitfield_default },
	 { "DCPG_IHC_DCFE3_POWER_UP_INT_OCCURRED", 15, 15, &umr_bitfield_default },
	 { "DCPG_IHC_DCFE4_POWER_DOWN_INT_CLEAR", 22, 22, &umr_bitfield_default },
	 { "DCPG_IHC_DCFE4_POWER_DOWN_INT_OCCURRED", 22, 22, &umr_bitfield_default },
	 { "DCPG_IHC_DCFE4_POWER_UP_INT_CLEAR", 16, 16, &umr_bitfield_default },
	 { "DCPG_IHC_DCFE4_POWER_UP_INT_OCCURRED", 16, 16, &umr_bitfield_default },
	 { "DCPG_IHC_DCFE5_POWER_DOWN_INT_CLEAR", 23, 23, &umr_bitfield_default },
	 { "DCPG_IHC_DCFE5_POWER_DOWN_INT_OCCURRED", 23, 23, &umr_bitfield_default },
	 { "DCPG_IHC_DCFE5_POWER_UP_INT_CLEAR", 17, 17, &umr_bitfield_default },
	 { "DCPG_IHC_DCFE5_POWER_UP_INT_OCCURRED", 17, 17, &umr_bitfield_default },
	 { "EXTERNAL_SW_INT_CLEAR", 8, 8, &umr_bitfield_default },
	 { "EXTERNAL_SW_INT_OCCURRED", 8, 8, &umr_bitfield_default },
	 { "MCP_INT_OCCURRED", 3, 3, &umr_bitfield_default },
	 { "SCP_INT_OCCURRED", 9, 9, &umr_bitfield_default },
	 { "UC_INTERNAL_INT_CLEAR", 10, 10, &umr_bitfield_default },
	 { "UC_INTERNAL_INT_OCCURRED", 10, 10, &umr_bitfield_default },
	 { "UC_REG_RD_TIMEOUT_INT_CLEAR", 11, 11, &umr_bitfield_default },
	 { "UC_REG_RD_TIMEOUT_INT_OCCURRED", 11, 11, &umr_bitfield_default },
	 { "VBLANK1_INT_CLEAR", 24, 24, &umr_bitfield_default },
	 { "VBLANK1_INT_OCCURRED", 24, 24, &umr_bitfield_default },
	 { "VBLANK2_INT_CLEAR", 25, 25, &umr_bitfield_default },
	 { "VBLANK2_INT_OCCURRED", 25, 25, &umr_bitfield_default },
	 { "VBLANK3_INT_CLEAR", 26, 26, &umr_bitfield_default },
	 { "VBLANK3_INT_OCCURRED", 26, 26, &umr_bitfield_default },
	 { "VBLANK4_INT_CLEAR", 27, 27, &umr_bitfield_default },
	 { "VBLANK4_INT_OCCURRED", 27, 27, &umr_bitfield_default },
	 { "VBLANK5_INT_CLEAR", 28, 28, &umr_bitfield_default },
	 { "VBLANK5_INT_OCCURRED", 28, 28, &umr_bitfield_default },
	 { "VBLANK6_INT_CLEAR", 29, 29, &umr_bitfield_default },
	 { "VBLANK6_INT_OCCURRED", 29, 29, &umr_bitfield_default },
};
static struct umr_bitfield mmDMCU_INTERRUPT_TO_HOST_EN_MASK[] = {
	 { "ABM1_BL_UPDATE_INT_MASK", 2, 2, &umr_bitfield_default },
	 { "ABM1_HG_READY_INT_MASK", 0, 0, &umr_bitfield_default },
	 { "ABM1_LS_READY_INT_MASK", 1, 1, &umr_bitfield_default },
	 { "DCPG_IHC_DCFE0_POWER_DOWN_INT_MASK", 18, 18, &umr_bitfield_default },
	 { "DCPG_IHC_DCFE0_POWER_UP_INT_MASK", 12, 12, &umr_bitfield_default },
	 { "DCPG_IHC_DCFE1_POWER_DOWN_INT_MASK", 19, 19, &umr_bitfield_default },
	 { "DCPG_IHC_DCFE1_POWER_UP_INT_MASK", 13, 13, &umr_bitfield_default },
	 { "DCPG_IHC_DCFE2_POWER_DOWN_INT_MASK", 20, 20, &umr_bitfield_default },
	 { "DCPG_IHC_DCFE2_POWER_UP_INT_MASK", 14, 14, &umr_bitfield_default },
	 { "DCPG_IHC_DCFE3_POWER_DOWN_INT_MASK", 21, 21, &umr_bitfield_default },
	 { "DCPG_IHC_DCFE3_POWER_UP_INT_MASK", 15, 15, &umr_bitfield_default },
	 { "DCPG_IHC_DCFE4_POWER_DOWN_INT_MASK", 22, 22, &umr_bitfield_default },
	 { "DCPG_IHC_DCFE4_POWER_UP_INT_MASK", 16, 16, &umr_bitfield_default },
	 { "DCPG_IHC_DCFE5_POWER_DOWN_INT_MASK", 23, 23, &umr_bitfield_default },
	 { "DCPG_IHC_DCFE5_POWER_UP_INT_MASK", 17, 17, &umr_bitfield_default },
	 { "SCP_INT_MASK", 9, 9, &umr_bitfield_default },
	 { "UC_INTERNAL_INT_MASK", 10, 10, &umr_bitfield_default },
	 { "UC_REG_RD_TIMEOUT_INT_MASK", 11, 11, &umr_bitfield_default },
};
static struct umr_bitfield mmDMCU_INTERRUPT_TO_UC_EN_MASK[] = {
	 { "ABM1_BL_UPDATE_INT_TO_UC_EN", 2, 2, &umr_bitfield_default },
	 { "ABM1_HG_READY_INT_TO_UC_EN", 0, 0, &umr_bitfield_default },
	 { "ABM1_LS_READY_INT_TO_UC_EN", 1, 1, &umr_bitfield_default },
	 { "DCPG_IHC_DCFE0_POWER_DOWN_INT_TO_UC_EN", 18, 18, &umr_bitfield_default },
	 { "DCPG_IHC_DCFE0_POWER_UP_INT_TO_UC_EN", 12, 12, &umr_bitfield_default },
	 { "DCPG_IHC_DCFE1_POWER_DOWN_INT_TO_UC_EN", 19, 19, &umr_bitfield_default },
	 { "DCPG_IHC_DCFE1_POWER_UP_INT_TO_UC_EN", 13, 13, &umr_bitfield_default },
	 { "DCPG_IHC_DCFE2_POWER_DOWN_INT_TO_UC_EN", 20, 20, &umr_bitfield_default },
	 { "DCPG_IHC_DCFE2_POWER_UP_INT_TO_UC_EN", 14, 14, &umr_bitfield_default },
	 { "DCPG_IHC_DCFE3_POWER_DOWN_INT_TO_UC_EN", 21, 21, &umr_bitfield_default },
	 { "DCPG_IHC_DCFE3_POWER_UP_INT_TO_UC_EN", 15, 15, &umr_bitfield_default },
	 { "DCPG_IHC_DCFE4_POWER_DOWN_INT_TO_UC_EN", 22, 22, &umr_bitfield_default },
	 { "DCPG_IHC_DCFE4_POWER_UP_INT_TO_UC_EN", 16, 16, &umr_bitfield_default },
	 { "DCPG_IHC_DCFE5_POWER_DOWN_INT_TO_UC_EN", 23, 23, &umr_bitfield_default },
	 { "DCPG_IHC_DCFE5_POWER_UP_INT_TO_UC_EN", 17, 17, &umr_bitfield_default },
	 { "EXTERNAL_SW_INT_TO_UC_EN", 8, 8, &umr_bitfield_default },
	 { "MCP_INT_TO_UC_EN", 3, 3, &umr_bitfield_default },
	 { "VBLANK1_INT_TO_UC_EN", 24, 24, &umr_bitfield_default },
	 { "VBLANK2_INT_TO_UC_EN", 25, 25, &umr_bitfield_default },
	 { "VBLANK3_INT_TO_UC_EN", 26, 26, &umr_bitfield_default },
	 { "VBLANK4_INT_TO_UC_EN", 27, 27, &umr_bitfield_default },
	 { "VBLANK5_INT_TO_UC_EN", 28, 28, &umr_bitfield_default },
	 { "VBLANK6_INT_TO_UC_EN", 29, 29, &umr_bitfield_default },
};
static struct umr_bitfield mmDMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL[] = {
	 { "ABM1_BL_UPDATE_INT_XIRQ_IRQ_SEL", 2, 2, &umr_bitfield_default },
	 { "ABM1_HG_READY_INT_XIRQ_IRQ_SEL", 0, 0, &umr_bitfield_default },
	 { "ABM1_LS_READY_INT_XIRQ_IRQ_SEL", 1, 1, &umr_bitfield_default },
	 { "DCPG_IHC_DCFE0_POWER_DOWN_INT_XIRQ_IRQ_SEL", 18, 18, &umr_bitfield_default },
	 { "DCPG_IHC_DCFE0_POWER_UP_INT_XIRQ_IRQ_SEL", 12, 12, &umr_bitfield_default },
	 { "DCPG_IHC_DCFE1_POWER_DOWN_INT_XIRQ_IRQ_SEL", 19, 19, &umr_bitfield_default },
	 { "DCPG_IHC_DCFE1_POWER_UP_INT_XIRQ_IRQ_SEL", 13, 13, &umr_bitfield_default },
	 { "DCPG_IHC_DCFE2_POWER_DOWN_INT_XIRQ_IRQ_SEL", 20, 20, &umr_bitfield_default },
	 { "DCPG_IHC_DCFE2_POWER_UP_INT_XIRQ_IRQ_SEL", 14, 14, &umr_bitfield_default },
	 { "DCPG_IHC_DCFE3_POWER_DOWN_INT_XIRQ_IRQ_SEL", 21, 21, &umr_bitfield_default },
	 { "DCPG_IHC_DCFE3_POWER_UP_INT_XIRQ_IRQ_SEL", 15, 15, &umr_bitfield_default },
	 { "DCPG_IHC_DCFE4_POWER_DOWN_INT_XIRQ_IRQ_SEL", 22, 22, &umr_bitfield_default },
	 { "DCPG_IHC_DCFE4_POWER_UP_INT_XIRQ_IRQ_SEL", 16, 16, &umr_bitfield_default },
	 { "DCPG_IHC_DCFE5_POWER_DOWN_INT_XIRQ_IRQ_SEL", 23, 23, &umr_bitfield_default },
	 { "DCPG_IHC_DCFE5_POWER_UP_INT_XIRQ_IRQ_SEL", 17, 17, &umr_bitfield_default },
	 { "EXTERNAL_SW_INT_XIRQ_IRQ_SEL", 8, 8, &umr_bitfield_default },
	 { "MCP_INT_XIRQ_IRQ_SEL", 3, 3, &umr_bitfield_default },
	 { "VBLANK1_INT_XIRQ_IRQ_SEL", 24, 24, &umr_bitfield_default },
	 { "VBLANK2_INT_XIRQ_IRQ_SEL", 25, 25, &umr_bitfield_default },
	 { "VBLANK3_INT_XIRQ_IRQ_SEL", 26, 26, &umr_bitfield_default },
	 { "VBLANK4_INT_XIRQ_IRQ_SEL", 27, 27, &umr_bitfield_default },
	 { "VBLANK5_INT_XIRQ_IRQ_SEL", 28, 28, &umr_bitfield_default },
	 { "VBLANK6_INT_XIRQ_IRQ_SEL", 29, 29, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_DMCU_SCRATCH[] = {
	 { "DMCU_SCRATCH", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDMCU_INT_CNT[] = {
	 { "DMCU_ABM1_BL_UPDATE_INT_CNT", 16, 23, &umr_bitfield_default },
	 { "DMCU_ABM1_HG_READY_INT_CNT", 0, 7, &umr_bitfield_default },
	 { "DMCU_ABM1_LS_READY_INT_CNT", 8, 15, &umr_bitfield_default },
};
static struct umr_bitfield mmDMCU_FW_CHECKSUM_SMPL_BYTE_POS[] = {
	 { "DMCU_FW_CHECKSUM_HI_SMPL_BYTE_POS", 2, 3, &umr_bitfield_default },
	 { "DMCU_FW_CHECKSUM_LO_SMPL_BYTE_POS", 0, 1, &umr_bitfield_default },
};
static struct umr_bitfield mmDMCU_UC_CLK_GATING_CNTL[] = {
	 { "UC_ERAM_RD_DELAY", 8, 10, &umr_bitfield_default },
	 { "UC_IRAM_RD_DELAY", 0, 2, &umr_bitfield_default },
	 { "UC_RBBM_RD_CLK_GATING_EN", 16, 16, &umr_bitfield_default },
};
static struct umr_bitfield mmMASTER_COMM_DATA_REG1[] = {
	 { "MASTER_COMM_DATA_REG1_BYTE0", 0, 7, &umr_bitfield_default },
	 { "MASTER_COMM_DATA_REG1_BYTE1", 8, 15, &umr_bitfield_default },
	 { "MASTER_COMM_DATA_REG1_BYTE2", 16, 23, &umr_bitfield_default },
	 { "MASTER_COMM_DATA_REG1_BYTE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMASTER_COMM_DATA_REG2[] = {
	 { "MASTER_COMM_DATA_REG2_BYTE0", 0, 7, &umr_bitfield_default },
	 { "MASTER_COMM_DATA_REG2_BYTE1", 8, 15, &umr_bitfield_default },
	 { "MASTER_COMM_DATA_REG2_BYTE2", 16, 23, &umr_bitfield_default },
	 { "MASTER_COMM_DATA_REG2_BYTE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMASTER_COMM_DATA_REG3[] = {
	 { "MASTER_COMM_DATA_REG3_BYTE0", 0, 7, &umr_bitfield_default },
	 { "MASTER_COMM_DATA_REG3_BYTE1", 8, 15, &umr_bitfield_default },
	 { "MASTER_COMM_DATA_REG3_BYTE2", 16, 23, &umr_bitfield_default },
	 { "MASTER_COMM_DATA_REG3_BYTE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMASTER_COMM_CMD_REG[] = {
	 { "MASTER_COMM_CMD_REG_BYTE0", 0, 7, &umr_bitfield_default },
	 { "MASTER_COMM_CMD_REG_BYTE1", 8, 15, &umr_bitfield_default },
	 { "MASTER_COMM_CMD_REG_BYTE2", 16, 23, &umr_bitfield_default },
	 { "MASTER_COMM_CMD_REG_BYTE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMASTER_COMM_CNTL_REG[] = {
	 { "MASTER_COMM_INTERRUPT", 0, 0, &umr_bitfield_default },
};
static struct umr_bitfield mmSLAVE_COMM_DATA_REG1[] = {
	 { "SLAVE_COMM_DATA_REG1_BYTE0", 0, 7, &umr_bitfield_default },
	 { "SLAVE_COMM_DATA_REG1_BYTE1", 8, 15, &umr_bitfield_default },
	 { "SLAVE_COMM_DATA_REG1_BYTE2", 16, 23, &umr_bitfield_default },
	 { "SLAVE_COMM_DATA_REG1_BYTE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSLAVE_COMM_DATA_REG2[] = {
	 { "SLAVE_COMM_DATA_REG2_BYTE0", 0, 7, &umr_bitfield_default },
	 { "SLAVE_COMM_DATA_REG2_BYTE1", 8, 15, &umr_bitfield_default },
	 { "SLAVE_COMM_DATA_REG2_BYTE2", 16, 23, &umr_bitfield_default },
	 { "SLAVE_COMM_DATA_REG2_BYTE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSLAVE_COMM_DATA_REG3[] = {
	 { "SLAVE_COMM_DATA_REG3_BYTE0", 0, 7, &umr_bitfield_default },
	 { "SLAVE_COMM_DATA_REG3_BYTE1", 8, 15, &umr_bitfield_default },
	 { "SLAVE_COMM_DATA_REG3_BYTE2", 16, 23, &umr_bitfield_default },
	 { "SLAVE_COMM_DATA_REG3_BYTE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSLAVE_COMM_CMD_REG[] = {
	 { "SLAVE_COMM_CMD_REG_BYTE0", 0, 7, &umr_bitfield_default },
	 { "SLAVE_COMM_CMD_REG_BYTE1", 8, 15, &umr_bitfield_default },
	 { "SLAVE_COMM_CMD_REG_BYTE2", 16, 23, &umr_bitfield_default },
	 { "SLAVE_COMM_CMD_REG_BYTE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSLAVE_COMM_CNTL_REG[] = {
	 { "COMM_PORT_MSG_TO_HOST_IN_PROGRESS", 8, 8, &umr_bitfield_default },
	 { "SLAVE_COMM_INTERRUPT", 0, 0, &umr_bitfield_default },
};
static struct umr_bitfield mmDMCU_TEST_DEBUG_INDEX[] = {
	 { "DMCU_TEST_DEBUG_INDEX", 0, 7, &umr_bitfield_default },
	 { "DMCU_TEST_DEBUG_WRITE_EN", 8, 8, &umr_bitfield_default },
};
static struct umr_bitfield mmDMCU_TEST_DEBUG_DATA[] = {
	 { "DMCU_TEST_DEBUG_DATA", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmBL1_PWM_AMBIENT_LIGHT_LEVEL[] = {
	 { "BL1_PWM_AMBIENT_LIGHT_LEVEL", 0, 16, &umr_bitfield_default },
};
static struct umr_bitfield mmBL1_PWM_USER_LEVEL[] = {
	 { "BL1_PWM_USER_LEVEL", 0, 16, &umr_bitfield_default },
};
static struct umr_bitfield mmBL1_PWM_TARGET_ABM_LEVEL[] = {
	 { "BL1_PWM_TARGET_ABM_LEVEL", 0, 16, &umr_bitfield_default },
};
static struct umr_bitfield mmBL1_PWM_CURRENT_ABM_LEVEL[] = {
	 { "BL1_PWM_CURRENT_ABM_LEVEL", 0, 16, &umr_bitfield_default },
};
static struct umr_bitfield mmBL1_PWM_FINAL_DUTY_CYCLE[] = {
	 { "BL1_PWM_FINAL_DUTY_CYCLE", 0, 16, &umr_bitfield_default },
};
static struct umr_bitfield mmBL1_PWM_MINIMUM_DUTY_CYCLE[] = {
	 { "BL1_PWM_MINIMUM_DUTY_CYCLE", 0, 16, &umr_bitfield_default },
};
static struct umr_bitfield mmBL1_PWM_ABM_CNTL[] = {
	 { "BL1_PWM_AUTO_CALC_FINAL_DUTY_CYCLE_EN", 3, 3, &umr_bitfield_default },
	 { "BL1_PWM_AUTO_UPDATE_CURRENT_ABM_LEVEL_EN", 2, 2, &umr_bitfield_default },
	 { "BL1_PWM_AUTO_UPDATE_CURRENT_ABM_STEP_SIZE", 16, 31, &umr_bitfield_default },
	 { "BL1_PWM_USE_ABM_EN", 0, 0, &umr_bitfield_default },
	 { "BL1_PWM_USE_AMBIENT_LEVEL_EN", 1, 1, &umr_bitfield_default },
};
static struct umr_bitfield mmBL1_PWM_BL_UPDATE_SAMPLE_RATE[] = {
	 { "ABM1_HGLS_REG_LOCK", 31, 31, &umr_bitfield_default },
	 { "BL1_PWM_BL_UPDATE_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET", 16, 23, &umr_bitfield_default },
	 { "BL1_PWM_BL_UPDATE_RESET_SAMPLE_RATE_FRAME_COUNTER", 1, 1, &umr_bitfield_default },
	 { "BL1_PWM_BL_UPDATE_SAMPLE_RATE_COUNT_EN", 0, 0, &umr_bitfield_default },
	 { "BL1_PWM_BL_UPDATE_SAMPLE_RATE_FRAME_COUNT", 8, 15, &umr_bitfield_default },
};
static struct umr_bitfield mmBL1_PWM_GRP2_REG_LOCK[] = {
	 { "BL1_PWM_GRP2_FRAME_START_DISP_SEL", 17, 19, &umr_bitfield_default },
	 { "BL1_PWM_GRP2_IGNORE_MASTER_LOCK_EN", 31, 31, &umr_bitfield_default },
	 { "BL1_PWM_GRP2_READBACK_DB_REG_VALUE_EN", 24, 24, &umr_bitfield_default },
	 { "BL1_PWM_GRP2_REG_LOCK", 0, 0, &umr_bitfield_default },
	 { "BL1_PWM_GRP2_REG_UPDATE_PENDING", 8, 8, &umr_bitfield_default },
	 { "BL1_PWM_GRP2_UPDATE_AT_FRAME_START", 16, 16, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_ABM1_CNTL[] = {
	 { "ABM1_BLANK_MODE_SUPPORT_ENABLE", 31, 31, &umr_bitfield_default },
	 { "ABM1_EN", 0, 0, &umr_bitfield_default },
	 { "ABM1_SOURCE_SELECT", 8, 10, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_ABM1_IPCSC_COEFF_SEL[] = {
	 { "ABM1_HGLS_REG_LOCK", 31, 31, &umr_bitfield_default },
	 { "ABM1_IPCSC_COEFF_SEL_B", 0, 3, &umr_bitfield_default },
	 { "ABM1_IPCSC_COEFF_SEL_G", 8, 11, &umr_bitfield_default },
	 { "ABM1_IPCSC_COEFF_SEL_R", 16, 19, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_ABM1_ACE_OFFSET_SLOPE_0[] = {
	 { "ABM1_ACE_LOCK", 31, 31, &umr_bitfield_default },
	 { "ABM1_ACE_OFFSET_0", 16, 26, &umr_bitfield_default },
	 { "ABM1_ACE_SLOPE_0", 0, 14, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_ABM1_ACE_OFFSET_SLOPE_1[] = {
	 { "ABM1_ACE_LOCK", 31, 31, &umr_bitfield_default },
	 { "ABM1_ACE_OFFSET_1", 16, 26, &umr_bitfield_default },
	 { "ABM1_ACE_SLOPE_1", 0, 14, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_ABM1_ACE_OFFSET_SLOPE_2[] = {
	 { "ABM1_ACE_LOCK", 31, 31, &umr_bitfield_default },
	 { "ABM1_ACE_OFFSET_2", 16, 26, &umr_bitfield_default },
	 { "ABM1_ACE_SLOPE_2", 0, 14, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_ABM1_ACE_OFFSET_SLOPE_3[] = {
	 { "ABM1_ACE_LOCK", 31, 31, &umr_bitfield_default },
	 { "ABM1_ACE_OFFSET_3", 16, 26, &umr_bitfield_default },
	 { "ABM1_ACE_SLOPE_3", 0, 14, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_ABM1_ACE_OFFSET_SLOPE_4[] = {
	 { "ABM1_ACE_LOCK", 31, 31, &umr_bitfield_default },
	 { "ABM1_ACE_OFFSET_4", 16, 26, &umr_bitfield_default },
	 { "ABM1_ACE_SLOPE_4", 0, 14, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_ABM1_ACE_THRES_12[] = {
	 { "ABM1_ACE_LOCK", 31, 31, &umr_bitfield_default },
	 { "ABM1_ACE_THRES_1", 0, 9, &umr_bitfield_default },
	 { "ABM1_ACE_THRES_2", 16, 25, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_ABM1_ACE_THRES_34[] = {
	 { "ABM1_ACE_DBUF_REG_UPDATE_PENDING", 30, 30, &umr_bitfield_default },
	 { "ABM1_ACE_IGNORE_MASTER_LOCK_EN", 28, 28, &umr_bitfield_default },
	 { "ABM1_ACE_LOCK", 31, 31, &umr_bitfield_default },
	 { "ABM1_ACE_READBACK_DB_REG_VALUE_EN", 29, 29, &umr_bitfield_default },
	 { "ABM1_ACE_THRES_3", 0, 9, &umr_bitfield_default },
	 { "ABM1_ACE_THRES_4", 16, 25, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_ABM1_ACE_CNTL_MISC[] = {
	 { "ABM1_ACE_REG_WR_MISSED_FRAME_CLEAR", 8, 8, &umr_bitfield_default },
	 { "ABM1_ACE_REG_WR_MISSED_FRAME", 0, 0, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_ABM1_DEBUG_MISC[] = {
	 { "ABM1_BL_FORCE_INTERRUPT", 16, 16, &umr_bitfield_default },
	 { "ABM1_HG_FORCE_INTERRUPT", 0, 0, &umr_bitfield_default },
	 { "ABM1_LS_FORCE_INTERRUPT", 8, 8, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_ABM1_HGLS_REG_READ_PROGRESS[] = {
	 { "ABM1_BL_REG_READ_IN_PROGRESS", 2, 2, &umr_bitfield_default },
	 { "ABM1_BL_REG_READ_MISSED_FRAME_CLEAR", 31, 31, &umr_bitfield_default },
	 { "ABM1_BL_REG_READ_MISSED_FRAME", 10, 10, &umr_bitfield_default },
	 { "ABM1_HG_REG_READ_IN_PROGRESS", 0, 0, &umr_bitfield_default },
	 { "ABM1_HG_REG_READ_MISSED_FRAME_CLEAR", 16, 16, &umr_bitfield_default },
	 { "ABM1_HG_REG_READ_MISSED_FRAME", 8, 8, &umr_bitfield_default },
	 { "ABM1_LS_REG_READ_IN_PROGRESS", 1, 1, &umr_bitfield_default },
	 { "ABM1_LS_REG_READ_MISSED_FRAME_CLEAR", 24, 24, &umr_bitfield_default },
	 { "ABM1_LS_REG_READ_MISSED_FRAME", 9, 9, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_ABM1_HG_MISC_CTRL[] = {
	 { "ABM1_DBUF_HGLS_READBACK_DB_REG_VALUE_EN", 23, 23, &umr_bitfield_default },
	 { "ABM1_DBUF_HGLS_REG_FRAME_START_DISP_SEL", 24, 26, &umr_bitfield_default },
	 { "ABM1_DBUF_HGLS_REG_UPDATE_AT_FRAME_START", 28, 28, &umr_bitfield_default },
	 { "ABM1_DBUF_HGLS_REG_UPDATE_PENDING", 30, 30, &umr_bitfield_default },
	 { "ABM1_HG_BIN_BITWIDTH_SIZE_SEL", 16, 17, &umr_bitfield_default },
	 { "ABM1_HG_FINE_MODE_BIN_SEL", 12, 12, &umr_bitfield_default },
	 { "ABM1_HGLS_IGNORE_MASTER_LOCK_EN", 29, 29, &umr_bitfield_default },
	 { "ABM1_HGLS_REG_LOCK", 31, 31, &umr_bitfield_default },
	 { "ABM1_HG_NUM_OF_BINS_SEL", 0, 1, &umr_bitfield_default },
	 { "ABM1_HG_VMAX_SEL", 8, 8, &umr_bitfield_default },
	 { "ABM1_OVR_SCAN_PIXEL_PROCESS_EN", 20, 20, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_ABM1_LS_SUM_OF_LUMA[] = {
	 { "ABM1_LS_SUM_OF_LUMA", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_ABM1_LS_MIN_MAX_LUMA[] = {
	 { "ABM1_LS_MAX_LUMA", 16, 25, &umr_bitfield_default },
	 { "ABM1_LS_MIN_LUMA", 0, 9, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_ABM1_LS_FILTERED_MIN_MAX_LUMA[] = {
	 { "ABM1_LS_FILTERED_MAX_LUMA", 16, 25, &umr_bitfield_default },
	 { "ABM1_LS_FILTERED_MIN_LUMA", 0, 9, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_ABM1_LS_PIXEL_COUNT[] = {
	 { "ABM1_LS_PIXEL_COUNT", 0, 23, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_ABM1_LS_OVR_SCAN_BIN[] = {
	 { "ABM1_LS_OVR_SCAN_BIN", 0, 23, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES[] = {
	 { "ABM1_HGLS_REG_LOCK", 31, 31, &umr_bitfield_default },
	 { "ABM1_LS_MAX_PIXEL_VALUE_THRES", 16, 25, &umr_bitfield_default },
	 { "ABM1_LS_MIN_PIXEL_VALUE_THRES", 0, 9, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_ABM1_LS_MIN_PIXEL_VALUE_COUNT[] = {
	 { "ABM1_LS_MIN_PIXEL_VALUE_COUNT", 0, 23, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_ABM1_LS_MAX_PIXEL_VALUE_COUNT[] = {
	 { "ABM1_LS_MAX_PIXEL_VALUE_COUNT", 0, 23, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_ABM1_HG_SAMPLE_RATE[] = {
	 { "ABM1_HG_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET", 16, 23, &umr_bitfield_default },
	 { "ABM1_HGLS_REG_LOCK", 31, 31, &umr_bitfield_default },
	 { "ABM1_HG_RESET_SAMPLE_RATE_FRAME_COUNTER", 1, 1, &umr_bitfield_default },
	 { "ABM1_HG_SAMPLE_RATE_COUNT_EN", 0, 0, &umr_bitfield_default },
	 { "ABM1_HG_SAMPLE_RATE_FRAME_COUNT", 8, 15, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_ABM1_LS_SAMPLE_RATE[] = {
	 { "ABM1_HGLS_REG_LOCK", 31, 31, &umr_bitfield_default },
	 { "ABM1_LS_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET", 16, 23, &umr_bitfield_default },
	 { "ABM1_LS_RESET_SAMPLE_RATE_FRAME_COUNTER", 1, 1, &umr_bitfield_default },
	 { "ABM1_LS_SAMPLE_RATE_COUNT_EN", 0, 0, &umr_bitfield_default },
	 { "ABM1_LS_SAMPLE_RATE_FRAME_COUNT", 8, 15, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_ABM1_HG_BIN_1_32_SHIFT_FLAG[] = {
	 { "ABM1_HG_BIN_1_32_SHIFT_FLAG", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_ABM1_HG_BIN_1_8_SHIFT_INDEX[] = {
	 { "ABM1_HG_BIN_1_8_SHIFT_INDEX", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_ABM1_HG_BIN_9_16_SHIFT_INDEX[] = {
	 { "ABM1_HG_BIN_9_16_SHIFT_INDEX", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_ABM1_HG_BIN_17_24_SHIFT_INDEX[] = {
	 { "ABM1_HG_BIN_17_24_SHIFT_INDEX", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_ABM1_HG_BIN_25_32_SHIFT_INDEX[] = {
	 { "ABM1_HG_BIN_25_32_SHIFT_INDEX", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_ABM1_HG_RESULT_1[] = {
	 { "ABM1_HG_RESULT_1", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_ABM1_HG_RESULT_2[] = {
	 { "ABM1_HG_RESULT_2", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_ABM1_HG_RESULT_3[] = {
	 { "ABM1_HG_RESULT_3", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_ABM1_HG_RESULT_4[] = {
	 { "ABM1_HG_RESULT_4", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_ABM1_HG_RESULT_5[] = {
	 { "ABM1_HG_RESULT_5", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_ABM1_HG_RESULT_6[] = {
	 { "ABM1_HG_RESULT_6", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_ABM1_HG_RESULT_7[] = {
	 { "ABM1_HG_RESULT_7", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_ABM1_HG_RESULT_8[] = {
	 { "ABM1_HG_RESULT_8", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_ABM1_HG_RESULT_9[] = {
	 { "ABM1_HG_RESULT_9", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_ABM1_HG_RESULT_10[] = {
	 { "ABM1_HG_RESULT_10", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_ABM1_HG_RESULT_11[] = {
	 { "ABM1_HG_RESULT_11", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_ABM1_HG_RESULT_12[] = {
	 { "ABM1_HG_RESULT_12", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_ABM1_HG_RESULT_13[] = {
	 { "ABM1_HG_RESULT_13", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_ABM1_HG_RESULT_14[] = {
	 { "ABM1_HG_RESULT_14", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_ABM1_HG_RESULT_15[] = {
	 { "ABM1_HG_RESULT_15", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_ABM1_HG_RESULT_16[] = {
	 { "ABM1_HG_RESULT_16", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_ABM1_HG_RESULT_17[] = {
	 { "ABM1_HG_RESULT_17", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_ABM1_HG_RESULT_18[] = {
	 { "ABM1_HG_RESULT_18", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_ABM1_HG_RESULT_19[] = {
	 { "ABM1_HG_RESULT_19", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_ABM1_HG_RESULT_20[] = {
	 { "ABM1_HG_RESULT_20", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_ABM1_HG_RESULT_21[] = {
	 { "ABM1_HG_RESULT_21", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_ABM1_HG_RESULT_22[] = {
	 { "ABM1_HG_RESULT_22", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_ABM1_HG_RESULT_23[] = {
	 { "ABM1_HG_RESULT_23", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_ABM1_HG_RESULT_24[] = {
	 { "ABM1_HG_RESULT_24", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMVP_CONTROL1[] = {
	 { "MVP_30BPP_EN", 28, 28, &umr_bitfield_default },
	 { "MVP_ARBITRATION_MODE_FOR_AFR_MANUAL_SWITCH_MODE", 10, 10, &umr_bitfield_default },
	 { "MVP_CHANNEL_CONTROL", 16, 16, &umr_bitfield_default },
	 { "MVP_DISABLE_MSB_EXPAND", 24, 24, &umr_bitfield_default },
	 { "MVP_EN", 0, 0, &umr_bitfield_default },
	 { "MVP_GPU_CHAIN_LOCATION", 20, 21, &umr_bitfield_default },
	 { "MVP_MIXER_MODE", 4, 6, &umr_bitfield_default },
	 { "MVP_MIXER_SLAVE_SEL_DELAY_UNTIL_END_OF_BLANK", 9, 9, &umr_bitfield_default },
	 { "MVP_MIXER_SLAVE_SEL", 8, 8, &umr_bitfield_default },
	 { "MVP_RATE_CONTROL", 12, 12, &umr_bitfield_default },
	 { "MVP_TERMINATION_CNTL_A", 30, 30, &umr_bitfield_default },
	 { "MVP_TERMINATION_CNTL_B", 31, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMVP_CONTROL2[] = {
	 { "MVP_DVOCNTL_MUX", 16, 16, &umr_bitfield_default },
	 { "MVP_FLOW_CONTROL_OUT_EN", 20, 20, &umr_bitfield_default },
	 { "MVP_MUXA_CLK_SEL", 8, 8, &umr_bitfield_default },
	 { "MVP_MUXB_CLK_SEL", 12, 12, &umr_bitfield_default },
	 { "MVP_MUX_DE_DVOCNTL0_SEL", 0, 0, &umr_bitfield_default },
	 { "MVP_MUX_DE_DVOCNTL2_SEL", 4, 4, &umr_bitfield_default },
	 { "MVP_SWAP_AB_IN_DC_DDR", 28, 28, &umr_bitfield_default },
	 { "MVP_SWAP_LOCK_OUT_EN", 24, 24, &umr_bitfield_default },
};
static struct umr_bitfield mmMVP_FIFO_CONTROL[] = {
	 { "MVP_PAUSE_SLAVE_CNT", 16, 23, &umr_bitfield_default },
	 { "MVP_PAUSE_SLAVE_WM", 8, 15, &umr_bitfield_default },
	 { "MVP_STOP_SLAVE_WM", 0, 7, &umr_bitfield_default },
};
static struct umr_bitfield mmMVP_FIFO_STATUS[] = {
	 { "MVP_FIFO_ERROR_INT_STATUS", 31, 31, &umr_bitfield_default },
	 { "MVP_FIFO_ERROR_MASK", 30, 30, &umr_bitfield_default },
	 { "MVP_FIFO_LEVEL", 0, 7, &umr_bitfield_default },
	 { "MVP_FIFO_OVERFLOW_ACK", 16, 16, &umr_bitfield_default },
	 { "MVP_FIFO_OVERFLOW", 8, 8, &umr_bitfield_default },
	 { "MVP_FIFO_OVERFLOW_OCCURRED", 12, 12, &umr_bitfield_default },
	 { "MVP_FIFO_UNDERFLOW_ACK", 28, 28, &umr_bitfield_default },
	 { "MVP_FIFO_UNDERFLOW", 20, 20, &umr_bitfield_default },
	 { "MVP_FIFO_UNDERFLOW_OCCURRED", 24, 24, &umr_bitfield_default },
};
static struct umr_bitfield mmMVP_SLAVE_STATUS[] = {
	 { "MVP_SLAVE_LINES_PER_FRAME_RCVED", 16, 28, &umr_bitfield_default },
	 { "MVP_SLAVE_PIXELS_PER_LINE_RCVED", 0, 12, &umr_bitfield_default },
};
static struct umr_bitfield mmMVP_INBAND_CNTL_CAP[] = {
	 { "MVP_IGNOR_INBAND_CNTL", 0, 0, &umr_bitfield_default },
	 { "MVP_INBAND_CNTL_CHAR_CAP", 8, 31, &umr_bitfield_default },
	 { "MVP_PASSING_INBAND_CNTL_EN", 4, 4, &umr_bitfield_default },
};
static struct umr_bitfield mmMVP_BLACK_KEYER[] = {
	 { "MVP_BLACK_KEYER_B", 20, 29, &umr_bitfield_default },
	 { "MVP_BLACK_KEYER_G", 10, 19, &umr_bitfield_default },
	 { "MVP_BLACK_KEYER_R", 0, 9, &umr_bitfield_default },
};
static struct umr_bitfield mmMVP_CRC_CNTL[] = {
	 { "MVP_CRC_BLUE_MASK", 0, 7, &umr_bitfield_default },
	 { "MVP_CRC_CONT_EN", 29, 29, &umr_bitfield_default },
	 { "MVP_CRC_EN", 28, 28, &umr_bitfield_default },
	 { "MVP_CRC_GREEN_MASK", 8, 15, &umr_bitfield_default },
	 { "MVP_CRC_RED_MASK", 16, 23, &umr_bitfield_default },
	 { "MVP_DC_DDR_CRC_EVEN_ODD_PIX_SEL", 30, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmMVP_CRC_RESULT_BLUE_GREEN[] = {
	 { "MVP_CRC_BLUE_RESULT", 0, 15, &umr_bitfield_default },
	 { "MVP_CRC_GREEN_RESULT", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMVP_CRC_RESULT_RED[] = {
	 { "MVP_CRC_RED_RESULT", 0, 15, &umr_bitfield_default },
};
static struct umr_bitfield mmMVP_CONTROL3[] = {
	 { "MVP_DDR_SC_AB_SEL", 4, 4, &umr_bitfield_default },
	 { "MVP_DDR_SC_B_START_MODE", 8, 8, &umr_bitfield_default },
	 { "MVP_FLOW_CONTROL_CASCADE_EN", 20, 20, &umr_bitfield_default },
	 { "MVP_FLOW_CONTROL_IN_CAP", 28, 28, &umr_bitfield_default },
	 { "MVP_FLOW_CONTROL_OUT_FORCE_ONE", 12, 12, &umr_bitfield_default },
	 { "MVP_FLOW_CONTROL_OUT_FORCE_ZERO", 16, 16, &umr_bitfield_default },
	 { "MVP_RESET_IN_BETWEEN_FRAMES", 0, 0, &umr_bitfield_default },
	 { "MVP_SWAP_48BIT_EN", 24, 24, &umr_bitfield_default },
};
static struct umr_bitfield mmMVP_RECEIVE_CNT_CNTL1[] = {
	 { "MVP_SLAVE_DATA_CHK_EN", 31, 31, &umr_bitfield_default },
	 { "MVP_SLAVE_LINE_ERROR_CNT", 16, 28, &umr_bitfield_default },
	 { "MVP_SLAVE_PIXEL_ERROR_CNT", 0, 12, &umr_bitfield_default },
};
static struct umr_bitfield mmMVP_RECEIVE_CNT_CNTL2[] = {
	 { "MVP_SLAVE_FRAME_ERROR_CNT", 0, 12, &umr_bitfield_default },
	 { "MVP_SLAVE_FRAME_ERROR_CNT_RESET", 31, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMVP_TEST_DEBUG_INDEX[] = {
	 { "MVP_TEST_DEBUG_INDEX", 0, 7, &umr_bitfield_default },
	 { "MVP_TEST_DEBUG_WRITE_EN", 8, 8, &umr_bitfield_default },
};
static struct umr_bitfield mmMVP_TEST_DEBUG_DATA[] = {
	 { "MVP_TEST_DEBUG_DATA", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMVP_DEBUG[] = {
	 { "MVP_DEBUG_BITS", 8, 31, &umr_bitfield_default },
	 { "MVP_DIS_FIX_AFR_AUTO_VSYNC_FLIP", 5, 5, &umr_bitfield_default },
	 { "MVP_DIS_FIX_AFR_MANUAL_HSYNC_FLIP", 4, 4, &umr_bitfield_default },
	 { "MVP_DIS_READ_POINTER_RESET_DELAY", 7, 7, &umr_bitfield_default },
	 { "MVP_EN_FIX_AFR_MANUAL_SWITCH_IN_SFR", 6, 6, &umr_bitfield_default },
	 { "MVP_FLOW_CONTROL_IN_EN", 1, 1, &umr_bitfield_default },
	 { "MVP_FLOW_CONTROL_IN_SEL", 3, 3, &umr_bitfield_default },
	 { "MVP_SWAP_LOCK_IN_EN", 0, 0, &umr_bitfield_default },
	 { "MVP_SWAP_LOCK_IN_SEL", 2, 2, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_ABM1_OVERSCAN_PIXEL_VALUE[] = {
	 { "ABM1_OVERSCAN_B_PIXEL_VALUE", 20, 29, &umr_bitfield_default },
	 { "ABM1_OVERSCAN_G_PIXEL_VALUE", 10, 19, &umr_bitfield_default },
	 { "ABM1_OVERSCAN_R_PIXEL_VALUE", 0, 9, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_ABM1_BL_MASTER_LOCK[] = {
	 { "ABM1_BL_MASTER_LOCK", 31, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmABM_TEST_DEBUG_INDEX[] = {
	 { "ABM_TEST_DEBUG_INDEX", 0, 7, &umr_bitfield_default },
	 { "ABM_TEST_DEBUG_WRITE_EN", 8, 8, &umr_bitfield_default },
};
static struct umr_bitfield mmABM_TEST_DEBUG_DATA[] = {
	 { "ABM_TEST_DEBUG_DATA", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmFBC_CNTL[] = {
	 { "FBC_COHERENCY_MODE", 16, 17, &umr_bitfield_default },
	 { "FBC_EN", 31, 31, &umr_bitfield_default },
	 { "FBC_GRPH_COMP_EN", 0, 0, &umr_bitfield_default },
	 { "FBC_SOFT_COMPRESS_EN", 25, 25, &umr_bitfield_default },
	 { "FBC_SRC_SEL", 1, 3, &umr_bitfield_default },
};
static struct umr_bitfield mmFBC_IDLE_MASK[] = {
	 { "FBC_IDLE_MASK", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmFBC_IDLE_FORCE_CLEAR_MASK[] = {
	 { "FBC_IDLE_FORCE_CLEAR_MASK", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmFBC_START_STOP_DELAY[] = {
	 { "FBC_COMP_START_DELAY", 8, 12, &umr_bitfield_default },
	 { "FBC_DECOMP_START_DELAY", 0, 4, &umr_bitfield_default },
	 { "FBC_DECOMP_STOP_DELAY", 7, 7, &umr_bitfield_default },
};
static struct umr_bitfield mmFBC_COMP_CNTL[] = {
	 { "FBC_DEPTH_MONO08_EN", 16, 16, &umr_bitfield_default },
	 { "FBC_DEPTH_MONO16_EN", 17, 17, &umr_bitfield_default },
	 { "FBC_DEPTH_RGB04_EN", 18, 18, &umr_bitfield_default },
	 { "FBC_DEPTH_RGB08_EN", 19, 19, &umr_bitfield_default },
	 { "FBC_DEPTH_RGB16_EN", 20, 20, &umr_bitfield_default },
	 { "FBC_MIN_COMPRESSION", 0, 3, &umr_bitfield_default },
};
static struct umr_bitfield mmFBC_COMP_MODE[] = {
	 { "FBC_DPCM4_RGB_EN", 8, 8, &umr_bitfield_default },
	 { "FBC_DPCM4_YUV_EN", 10, 10, &umr_bitfield_default },
	 { "FBC_DPCM8_RGB_EN", 9, 9, &umr_bitfield_default },
	 { "FBC_DPCM8_YUV_EN", 11, 11, &umr_bitfield_default },
	 { "FBC_IND_EN", 16, 16, &umr_bitfield_default },
	 { "FBC_RLE_EN", 0, 0, &umr_bitfield_default },
};
static struct umr_bitfield mmFBC_DEBUG0[] = {
	 { "FBC_COMP_WAKE_DIS", 16, 16, &umr_bitfield_default },
	 { "FBC_DEBUG0", 17, 23, &umr_bitfield_default },
	 { "FBC_DEBUG_MUX", 24, 31, &umr_bitfield_default },
	 { "FBC_PERF_MUX0", 0, 7, &umr_bitfield_default },
	 { "FBC_PERF_MUX1", 8, 15, &umr_bitfield_default },
};
static struct umr_bitfield mmFBC_DEBUG1[] = {
	 { "FBC_DEBUG1", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmFBC_DEBUG2[] = {
	 { "FBC_DEBUG2", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmFBC_IND_LUT0[] = {
	 { "FBC_IND_LUT0", 0, 23, &umr_bitfield_default },
};
static struct umr_bitfield mmFBC_IND_LUT1[] = {
	 { "FBC_IND_LUT1", 0, 23, &umr_bitfield_default },
};
static struct umr_bitfield mmFBC_IND_LUT2[] = {
	 { "FBC_IND_LUT2", 0, 23, &umr_bitfield_default },
};
static struct umr_bitfield mmFBC_IND_LUT3[] = {
	 { "FBC_IND_LUT3", 0, 23, &umr_bitfield_default },
};
static struct umr_bitfield mmFBC_IND_LUT4[] = {
	 { "FBC_IND_LUT4", 0, 23, &umr_bitfield_default },
};
static struct umr_bitfield mmFBC_IND_LUT5[] = {
	 { "FBC_IND_LUT5", 0, 23, &umr_bitfield_default },
};
static struct umr_bitfield mmFBC_IND_LUT6[] = {
	 { "FBC_IND_LUT6", 0, 23, &umr_bitfield_default },
};
static struct umr_bitfield mmFBC_IND_LUT7[] = {
	 { "FBC_IND_LUT7", 0, 23, &umr_bitfield_default },
};
static struct umr_bitfield mmFBC_IND_LUT8[] = {
	 { "FBC_IND_LUT8", 0, 23, &umr_bitfield_default },
};
static struct umr_bitfield mmFBC_IND_LUT9[] = {
	 { "FBC_IND_LUT9", 0, 23, &umr_bitfield_default },
};
static struct umr_bitfield mmFBC_IND_LUT10[] = {
	 { "FBC_IND_LUT10", 0, 23, &umr_bitfield_default },
};
static struct umr_bitfield mmFBC_IND_LUT11[] = {
	 { "FBC_IND_LUT11", 0, 23, &umr_bitfield_default },
};
static struct umr_bitfield mmFBC_IND_LUT12[] = {
	 { "FBC_IND_LUT12", 0, 23, &umr_bitfield_default },
};
static struct umr_bitfield mmFBC_IND_LUT13[] = {
	 { "FBC_IND_LUT13", 0, 23, &umr_bitfield_default },
};
static struct umr_bitfield mmFBC_IND_LUT14[] = {
	 { "FBC_IND_LUT14", 0, 23, &umr_bitfield_default },
};
static struct umr_bitfield mmFBC_IND_LUT15[] = {
	 { "FBC_IND_LUT15", 0, 23, &umr_bitfield_default },
};
static struct umr_bitfield mmFBC_CSM_REGION_OFFSET_01[] = {
	 { "FBC_CSM_REGION_OFFSET_0", 0, 9, &umr_bitfield_default },
	 { "FBC_CSM_REGION_OFFSET_1", 16, 25, &umr_bitfield_default },
};
static struct umr_bitfield mmFBC_CSM_REGION_OFFSET_23[] = {
	 { "FBC_CSM_REGION_OFFSET_2", 0, 9, &umr_bitfield_default },
	 { "FBC_CSM_REGION_OFFSET_3", 16, 25, &umr_bitfield_default },
};
static struct umr_bitfield mmFBC_CLIENT_REGION_MASK[] = {
	 { "FBC_MEMORY_REGION_MASK", 16, 19, &umr_bitfield_default },
};
static struct umr_bitfield mmFBC_DEBUG_COMP[] = {
	 { "FBC_COMP_ADDRESS_TRANSLATION_ENABLE", 11, 11, &umr_bitfield_default },
	 { "FBC_COMP_BUSY_HYSTERESIS", 4, 7, &umr_bitfield_default },
	 { "FBC_COMP_CLK_CNTL", 8, 9, &umr_bitfield_default },
	 { "FBC_COMP_PRIVILEGED_ACCESS_ENABLE", 10, 10, &umr_bitfield_default },
	 { "FBC_COMP_RSIZE", 3, 3, &umr_bitfield_default },
	 { "FBC_COMP_SWAP", 0, 1, &umr_bitfield_default },
};
static struct umr_bitfield mmFBC_DEBUG_CSR[] = {
	 { "FBC_DEBUG_CSR_ADDR", 0, 9, &umr_bitfield_default },
	 { "FBC_DEBUG_CSR_EN", 31, 31, &umr_bitfield_default },
	 { "FBC_DEBUG_CSR_RD_DATA", 17, 17, &umr_bitfield_default },
	 { "FBC_DEBUG_CSR_WR_DATA", 16, 16, &umr_bitfield_default },
};
static struct umr_bitfield mmFBC_DEBUG_CSR_RDATA[] = {
	 { "FBC_DEBUG_CSR_RDATA", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmFBC_DEBUG_CSR_WDATA[] = {
	 { "FBC_DEBUG_CSR_WDATA", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmFBC_MISC[] = {
	 { "FBC_DECOMPRESS_ERROR_CLEAR", 16, 16, &umr_bitfield_default },
	 { "FBC_DECOMPRESS_ERROR", 0, 1, &umr_bitfield_default },
	 { "FBC_DIVIDE_X", 8, 9, &umr_bitfield_default },
	 { "FBC_DIVIDE_Y", 10, 10, &umr_bitfield_default },
	 { "FBC_ERROR_PIXEL", 4, 7, &umr_bitfield_default },
	 { "FBC_INVALIDATE_ON_ERROR", 3, 3, &umr_bitfield_default },
	 { "FBC_RESET_AT_DISABLE", 21, 21, &umr_bitfield_default },
	 { "FBC_RESET_AT_ENABLE", 20, 20, &umr_bitfield_default },
	 { "FBC_RSM_UNCOMP_DATA_IMMEDIATELY", 12, 12, &umr_bitfield_default },
	 { "FBC_RSM_WRITE_VALUE", 11, 11, &umr_bitfield_default },
	 { "FBC_SLOW_REQ_INTERVAL", 28, 31, &umr_bitfield_default },
	 { "FBC_STOP_ON_ERROR", 2, 2, &umr_bitfield_default },
};
static struct umr_bitfield mmFBC_STATUS[] = {
	 { "FBC_ENABLE_STATUS", 0, 0, &umr_bitfield_default },
};
static struct umr_bitfield mmFBC_TEST_DEBUG_INDEX[] = {
	 { "FBC_TEST_DEBUG_INDEX", 0, 7, &umr_bitfield_default },
	 { "FBC_TEST_DEBUG_WRITE_EN", 8, 8, &umr_bitfield_default },
};
static struct umr_bitfield mmFBC_TEST_DEBUG_DATA[] = {
	 { "FBC_TEST_DEBUG_DATA", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmFBC_DEBUG_CSR_RDATA_HI[] = {
	 { "FBC_DEBUG_CSR_RDATA_HI", 0, 7, &umr_bitfield_default },
};
static struct umr_bitfield mmFBC_DEBUG_CSR_WDATA_HI[] = {
	 { "FBC_DEBUG_CSR_WDATA_HI", 0, 7, &umr_bitfield_default },
};
static struct umr_bitfield ixAZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE[] = {
	 { "CLKSTOPOK", 9, 9, &umr_bitfield_default },
	 { "POWER_STATE_ACT", 4, 7, &umr_bitfield_default },
	 { "POWER_STATE_SET", 0, 3, &umr_bitfield_default },
	 { "POWER_STATE_SETTINGS_RESET", 10, 10, &umr_bitfield_default },
};
static struct umr_bitfield ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID[] = {
	 { "SUBSYSTEM_ID_BYTE0", 0, 7, &umr_bitfield_default },
	 { "SUBSYSTEM_ID_BYTE1", 8, 15, &umr_bitfield_default },
	 { "SUBSYSTEM_ID_BYTE2", 16, 23, &umr_bitfield_default },
	 { "SUBSYSTEM_ID_BYTE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_2[] = {
	 { "SUBSYSTEM_ID_BYTE1", 0, 7, &umr_bitfield_default },
};
static struct umr_bitfield ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_3[] = {
	 { "SUBSYSTEM_ID_BYTE2", 0, 7, &umr_bitfield_default },
};
static struct umr_bitfield ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_4[] = {
	 { "SUBSYSTEM_ID_BYTE3", 0, 7, &umr_bitfield_default },
};
static struct umr_bitfield mmPIPE0_PG_CONFIG[] = {
	 { "PIPE0_POWER_FORCEON", 0, 0, &umr_bitfield_default },
};
static struct umr_bitfield mmPIPE0_PG_ENABLE[] = {
	 { "PIPE0_POWER_GATE", 0, 0, &umr_bitfield_default },
};
static struct umr_bitfield mmPIPE0_PG_STATUS[] = {
	 { "PIPE0_DESIRED_PWR_STATE", 28, 28, &umr_bitfield_default },
	 { "PIPE0_PGFSM_PWR_STATUS", 30, 31, &umr_bitfield_default },
	 { "PIPE0_PGFSM_READ_DATA", 0, 23, &umr_bitfield_default },
	 { "PIPE0_REQUESTED_PWR_STATE", 29, 29, &umr_bitfield_default },
};
static struct umr_bitfield mmPIPE1_PG_CONFIG[] = {
	 { "PIPE1_POWER_FORCEON", 0, 0, &umr_bitfield_default },
};
static struct umr_bitfield mmPIPE1_PG_ENABLE[] = {
	 { "PIPE1_POWER_GATE", 0, 0, &umr_bitfield_default },
};
static struct umr_bitfield mmPIPE1_PG_STATUS[] = {
	 { "PIPE1_DESIRED_PWR_STATE", 28, 28, &umr_bitfield_default },
	 { "PIPE1_PGFSM_PWR_STATUS", 30, 31, &umr_bitfield_default },
	 { "PIPE1_PGFSM_READ_DATA", 0, 23, &umr_bitfield_default },
	 { "PIPE1_REQUESTED_PWR_STATE", 29, 29, &umr_bitfield_default },
};
static struct umr_bitfield mmPIPE2_PG_CONFIG[] = {
	 { "PIPE2_POWER_FORCEON", 0, 0, &umr_bitfield_default },
};
static struct umr_bitfield mmPIPE2_PG_ENABLE[] = {
	 { "PIPE2_POWER_GATE", 0, 0, &umr_bitfield_default },
};
static struct umr_bitfield mmPIPE2_PG_STATUS[] = {
	 { "PIPE2_DESIRED_PWR_STATE", 28, 28, &umr_bitfield_default },
	 { "PIPE2_PGFSM_PWR_STATUS", 30, 31, &umr_bitfield_default },
	 { "PIPE2_PGFSM_READ_DATA", 0, 23, &umr_bitfield_default },
	 { "PIPE2_REQUESTED_PWR_STATE", 29, 29, &umr_bitfield_default },
};
static struct umr_bitfield mmPIPE3_PG_CONFIG[] = {
	 { "PIPE3_POWER_FORCEON", 0, 0, &umr_bitfield_default },
};
static struct umr_bitfield mmPIPE3_PG_ENABLE[] = {
	 { "PIPE3_POWER_GATE", 0, 0, &umr_bitfield_default },
};
static struct umr_bitfield mmPIPE3_PG_STATUS[] = {
	 { "PIPE3_DESIRED_PWR_STATE", 28, 28, &umr_bitfield_default },
	 { "PIPE3_PGFSM_PWR_STATUS", 30, 31, &umr_bitfield_default },
	 { "PIPE3_PGFSM_READ_DATA", 0, 23, &umr_bitfield_default },
	 { "PIPE3_REQUESTED_PWR_STATE", 29, 29, &umr_bitfield_default },
};
static struct umr_bitfield ixAZALIA_F2_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION[] = {
	 { "CONVERTER_SYNCHRONIZATION", 0, 5, &umr_bitfield_default },
};
static struct umr_bitfield mmPIPE4_PG_ENABLE[] = {
	 { "PIPE4_POWER_GATE", 0, 0, &umr_bitfield_default },
};
static struct umr_bitfield mmPIPE4_PG_STATUS[] = {
	 { "PIPE4_DESIRED_PWR_STATE", 28, 28, &umr_bitfield_default },
	 { "PIPE4_PGFSM_PWR_STATUS", 30, 31, &umr_bitfield_default },
	 { "PIPE4_PGFSM_READ_DATA", 0, 23, &umr_bitfield_default },
	 { "PIPE4_REQUESTED_PWR_STATE", 29, 29, &umr_bitfield_default },
};
static struct umr_bitfield mmPIPE5_PG_CONFIG[] = {
	 { "PIPE5_POWER_FORCEON", 0, 0, &umr_bitfield_default },
};
static struct umr_bitfield mmPIPE5_PG_ENABLE[] = {
	 { "PIPE5_POWER_GATE", 0, 0, &umr_bitfield_default },
};
static struct umr_bitfield mmPIPE5_PG_STATUS[] = {
	 { "PIPE5_DESIRED_PWR_STATE", 28, 28, &umr_bitfield_default },
	 { "PIPE5_PGFSM_PWR_STATUS", 30, 31, &umr_bitfield_default },
	 { "PIPE5_PGFSM_READ_DATA", 0, 23, &umr_bitfield_default },
	 { "PIPE5_REQUESTED_PWR_STATE", 29, 29, &umr_bitfield_default },
};
static struct umr_bitfield mmDCPG_TEST_DEBUG_INDEX[] = {
	 { "DCPG_TEST_DEBUG_INDEX", 0, 7, &umr_bitfield_default },
	 { "DCPG_TEST_DEBUG_WRITE_EN", 8, 8, &umr_bitfield_default },
};
static struct umr_bitfield mmDCPG_TEST_DEBUG_DATA[] = {
	 { "DCPG_TEST_DEBUG_DATA", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_PGFSM_CONFIG_REG[] = {
	 { "PGFSM_CONFIG_REG", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_PGFSM_WRITE_REG[] = {
	 { "PGFSM_WRITE_REG", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_PGCNTL_STATUS_REG[] = {
	 { "DCPG_ECO_DEBUG", 16, 31, &umr_bitfield_default },
	 { "IPREQ_IGNORE_STATUS", 2, 2, &umr_bitfield_default },
	 { "SWREQ_RWOP_BUSY", 0, 0, &umr_bitfield_default },
	 { "SWREQ_RWOP_FORCE", 1, 1, &umr_bitfield_default },
};
static struct umr_bitfield mmCC_DC_PIPE_DIS[] = {
	 { "DC_PIPE_DIS", 1, 6, &umr_bitfield_default },
};
static struct umr_bitfield mmAZALIA_F0_CODEC_ENDPOINT_INDEX[] = {
	 { "AZALIA_ENDPOINT_REG_INDEX", 0, 7, &umr_bitfield_default },
	 { "AZALIA_ENDPOINT_REG_WRITE_EN", 8, 8, &umr_bitfield_default },
};
static struct umr_bitfield mmAZALIA_F0_CODEC_ENDPOINT_DATA[] = {
	 { "AZALIA_ENDPOINT_REG_DATA", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmAZALIA_AUDIO_DTO[] = {
	 { "AZALIA_AUDIO_DTO_MODULE", 16, 31, &umr_bitfield_default },
	 { "AZALIA_AUDIO_DTO_PHASE", 0, 15, &umr_bitfield_default },
};
static struct umr_bitfield mmAZALIA_AUDIO_DTO_CONTROL[] = {
	 { "AZALIA_AUDIO_FORCE_DTO", 8, 9, &umr_bitfield_default },
};
static struct umr_bitfield mmAZALIA_SCLK_CONTROL[] = {
	 { "AUDIO_SCLK_CONTROL", 4, 5, &umr_bitfield_default },
};
static struct umr_bitfield mmAZALIA_UNDERFLOW_FILLER_SAMPLE[] = {
	 { "AZALIA_UNDERFLOW_FILLER_SAMPLE", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmAZALIA_DATA_DMA_CONTROL[] = {
	 { "AZALIA_IOC_GENERATION_METHOD", 16, 16, &umr_bitfield_default },
	 { "AZALIA_UNDERFLOW_CONTROL", 17, 17, &umr_bitfield_default },
	 { "DATA_DMA_ISOCHRONOUS", 4, 5, &umr_bitfield_default },
	 { "DATA_DMA_NON_SNOOP", 0, 1, &umr_bitfield_default },
};
static struct umr_bitfield mmAZALIA_BDL_DMA_CONTROL[] = {
	 { "BDL_DMA_ISOCHRONOUS", 4, 5, &umr_bitfield_default },
	 { "BDL_DMA_NON_SNOOP", 0, 1, &umr_bitfield_default },
};
static struct umr_bitfield mmAZALIA_RIRB_AND_DP_CONTROL[] = {
	 { "DP_DMA_NON_SNOOP", 4, 4, &umr_bitfield_default },
	 { "RIRB_NON_SNOOP", 0, 0, &umr_bitfield_default },
};
static struct umr_bitfield mmAZALIA_CORB_DMA_CONTROL[] = {
	 { "CORB_DMA_ISOCHRONOUS", 4, 4, &umr_bitfield_default },
	 { "CORB_DMA_NON_SNOOP", 0, 0, &umr_bitfield_default },
};
static struct umr_bitfield mmAZALIA_APPLICATION_POSITION_IN_CYCLIC_BUFFER[] = {
	 { "APPLICATION_POSITION_IN_CYCLIC_BUFFER", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmAZALIA_CYCLIC_BUFFER_SYNC[] = {
	 { "CYCLIC_BUFFER_SYNC_ENABLE", 0, 0, &umr_bitfield_default },
};
static struct umr_bitfield mmAZALIA_GLOBAL_CAPABILITIES[] = {
	 { "NUMBER_OF_SERIAL_DATA_OUTPUT_SIGNALS", 1, 2, &umr_bitfield_default },
};
static struct umr_bitfield mmAZALIA_OUTPUT_PAYLOAD_CAPABILITY[] = {
	 { "OUTPUT_PAYLOAD_CAPABILITY", 0, 15, &umr_bitfield_default },
	 { "OUTSTRMPAY", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmAZALIA_OUTPUT_STREAM_ARBITER_CONTROL[] = {
	 { "LATENCY_HIDING_LEVEL", 0, 7, &umr_bitfield_default },
	 { "SYS_MEM_ACTIVE_ENABLE", 8, 8, &umr_bitfield_default },
};
static struct umr_bitfield mmAZALIA_CONTROLLER_DEBUG[] = {
	 { "CONTROLLER_DEBUG", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmAZ_TEST_DEBUG_INDEX[] = {
	 { "AZ_TEST_DEBUG_INDEX", 0, 7, &umr_bitfield_default },
	 { "AZ_TEST_DEBUG_WRITE_EN", 8, 8, &umr_bitfield_default },
};
static struct umr_bitfield mmAZ_TEST_DEBUG_DATA[] = {
	 { "AZ_TEST_DEBUG_DATA", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmAZALIA_F0_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID[] = {
	 { "AZALIA_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmAZALIA_F0_CODEC_ROOT_PARAMETER_REVISION_ID[] = {
	 { "AZALIA_CODEC_ROOT_PARAMETER_REVISION_ID", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmCC_RCU_DC_AUDIO_PORT_CONNECTIVITY[] = {
	 { "PORT_CONNECTIVITY", 0, 2, &umr_bitfield_default },
	 { "PORT_CONNECTIVITY_OVERRIDE_ENABLE", 4, 4, &umr_bitfield_default },
};
static struct umr_bitfield mmAZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL[] = {
	 { "COMPRESSED_CHANNEL_COUNT", 4, 6, &umr_bitfield_default },
	 { "HBR_CHANNEL_COUNT", 0, 2, &umr_bitfield_default },
};
static struct umr_bitfield mmAZALIA_F0_CODEC_RESYNC_FIFO_CONTROL[] = {
	 { "RESYNC_FIFO_STARTUP_KEEPOUT_WINDOW", 0, 5, &umr_bitfield_default },
};
static struct umr_bitfield mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_GROUP_TYPE[] = {
	 { "AZALIA_CODEC_FUNCTION_PARAMETER_GROUP_TYPE", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES[] = {
	 { "AUDIO_BIT_CAPABILITIES", 16, 20, &umr_bitfield_default },
	 { "AUDIO_RATE_CAPABILITIES", 0, 11, &umr_bitfield_default },
};
static struct umr_bitfield mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS[] = {
	 { "AZALIA_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES[] = {
	 { "AZALIA_CODEC_FUNCTION_PARAMETER_POWER_STATES", 0, 29, &umr_bitfield_default },
	 { "CLKSTOP", 30, 30, &umr_bitfield_default },
	 { "EPSS", 31, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmAZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE[] = {
	 { "CLKSTOPOK", 9, 9, &umr_bitfield_default },
	 { "POWER_STATE_ACT", 4, 7, &umr_bitfield_default },
	 { "POWER_STATE_SET", 0, 3, &umr_bitfield_default },
	 { "POWER_STATE_SETTINGS_RESET", 10, 10, &umr_bitfield_default },
};
static struct umr_bitfield mmAZALIA_F0_CODEC_FUNCTION_CONTROL_RESET[] = {
	 { "CODEC_RESET", 0, 0, &umr_bitfield_default },
};
static struct umr_bitfield mmAZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID[] = {
	 { "SUBSYSTEM_ID_BYTE0", 0, 7, &umr_bitfield_default },
	 { "SUBSYSTEM_ID_BYTE1", 8, 15, &umr_bitfield_default },
	 { "SUBSYSTEM_ID_BYTE2", 16, 23, &umr_bitfield_default },
	 { "SUBSYSTEM_ID_BYTE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmAZALIA_F0_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION[] = {
	 { "CONVERTER_SYNCHRONIZATION", 0, 5, &umr_bitfield_default },
};
static struct umr_bitfield mmAZALIA_F0_CODEC_DEBUG[] = {
	 { "CODEC_DEBUG", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmAZALIA_STREAM_INDEX[] = {
	 { "AZALIA_STREAM_REG_INDEX", 0, 7, &umr_bitfield_default },
	 { "AZALIA_STREAM_REG_WRITE_EN", 8, 8, &umr_bitfield_default },
};
static struct umr_bitfield mmAZALIA_STREAM_DATA[] = {
	 { "AZALIA_STREAM_REG_DATA", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESET[] = {
	 { "CODEC_RESET", 0, 0, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_HPD1_INT_STATUS[] = {
	 { "DC_HPD1_INT_STATUS", 0, 0, &umr_bitfield_default },
	 { "DC_HPD1_RX_INT_STATUS", 8, 8, &umr_bitfield_default },
	 { "DC_HPD1_SENSE_DELAYED", 4, 4, &umr_bitfield_default },
	 { "DC_HPD1_SENSE", 1, 1, &umr_bitfield_default },
	 { "DC_HPD1_TOGGLE_FILT_CON_TIMER_VAL", 12, 19, &umr_bitfield_default },
	 { "DC_HPD1_TOGGLE_FILT_DISCON_TIMER_VAL", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_HPD1_INT_CONTROL[] = {
	 { "DC_HPD1_INT_ACK", 0, 0, &umr_bitfield_default },
	 { "DC_HPD1_INT_EN", 16, 16, &umr_bitfield_default },
	 { "DC_HPD1_INT_POLARITY", 8, 8, &umr_bitfield_default },
	 { "DC_HPD1_RX_INT_ACK", 20, 20, &umr_bitfield_default },
	 { "DC_HPD1_RX_INT_EN", 24, 24, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_HPD1_CONTROL[] = {
	 { "DC_HPD1_CONNECTION_TIMER", 0, 12, &umr_bitfield_default },
	 { "DC_HPD1_EN", 28, 28, &umr_bitfield_default },
	 { "DC_HPD1_RX_INT_TIMER", 16, 25, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_HPD2_INT_STATUS[] = {
	 { "DC_HPD2_INT_STATUS", 0, 0, &umr_bitfield_default },
	 { "DC_HPD2_RX_INT_STATUS", 8, 8, &umr_bitfield_default },
	 { "DC_HPD2_SENSE_DELAYED", 4, 4, &umr_bitfield_default },
	 { "DC_HPD2_SENSE", 1, 1, &umr_bitfield_default },
	 { "DC_HPD2_TOGGLE_FILT_CON_TIMER_VAL", 12, 19, &umr_bitfield_default },
	 { "DC_HPD2_TOGGLE_FILT_DISCON_TIMER_VAL", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_HPD2_INT_CONTROL[] = {
	 { "DC_HPD2_INT_ACK", 0, 0, &umr_bitfield_default },
	 { "DC_HPD2_INT_EN", 16, 16, &umr_bitfield_default },
	 { "DC_HPD2_INT_POLARITY", 8, 8, &umr_bitfield_default },
	 { "DC_HPD2_RX_INT_ACK", 20, 20, &umr_bitfield_default },
	 { "DC_HPD2_RX_INT_EN", 24, 24, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_HPD2_CONTROL[] = {
	 { "DC_HPD2_CONNECTION_TIMER", 0, 12, &umr_bitfield_default },
	 { "DC_HPD2_EN", 28, 28, &umr_bitfield_default },
	 { "DC_HPD2_RX_INT_TIMER", 16, 25, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_HPD3_INT_STATUS[] = {
	 { "DC_HPD3_INT_STATUS", 0, 0, &umr_bitfield_default },
	 { "DC_HPD3_RX_INT_STATUS", 8, 8, &umr_bitfield_default },
	 { "DC_HPD3_SENSE_DELAYED", 4, 4, &umr_bitfield_default },
	 { "DC_HPD3_SENSE", 1, 1, &umr_bitfield_default },
	 { "DC_HPD3_TOGGLE_FILT_CON_TIMER_VAL", 12, 19, &umr_bitfield_default },
	 { "DC_HPD3_TOGGLE_FILT_DISCON_TIMER_VAL", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_HPD3_INT_CONTROL[] = {
	 { "DC_HPD3_INT_ACK", 0, 0, &umr_bitfield_default },
	 { "DC_HPD3_INT_EN", 16, 16, &umr_bitfield_default },
	 { "DC_HPD3_INT_POLARITY", 8, 8, &umr_bitfield_default },
	 { "DC_HPD3_RX_INT_ACK", 20, 20, &umr_bitfield_default },
	 { "DC_HPD3_RX_INT_EN", 24, 24, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_HPD3_CONTROL[] = {
	 { "DC_HPD3_CONNECTION_TIMER", 0, 12, &umr_bitfield_default },
	 { "DC_HPD3_EN", 28, 28, &umr_bitfield_default },
	 { "DC_HPD3_RX_INT_TIMER", 16, 25, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_HPD4_INT_STATUS[] = {
	 { "DC_HPD4_INT_STATUS", 0, 0, &umr_bitfield_default },
	 { "DC_HPD4_RX_INT_STATUS", 8, 8, &umr_bitfield_default },
	 { "DC_HPD4_SENSE_DELAYED", 4, 4, &umr_bitfield_default },
	 { "DC_HPD4_SENSE", 1, 1, &umr_bitfield_default },
	 { "DC_HPD4_TOGGLE_FILT_CON_TIMER_VAL", 12, 19, &umr_bitfield_default },
	 { "DC_HPD4_TOGGLE_FILT_DISCON_TIMER_VAL", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_HPD4_INT_CONTROL[] = {
	 { "DC_HPD4_INT_ACK", 0, 0, &umr_bitfield_default },
	 { "DC_HPD4_INT_EN", 16, 16, &umr_bitfield_default },
	 { "DC_HPD4_INT_POLARITY", 8, 8, &umr_bitfield_default },
	 { "DC_HPD4_RX_INT_ACK", 20, 20, &umr_bitfield_default },
	 { "DC_HPD4_RX_INT_EN", 24, 24, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_HPD4_CONTROL[] = {
	 { "DC_HPD4_CONNECTION_TIMER", 0, 12, &umr_bitfield_default },
	 { "DC_HPD4_EN", 28, 28, &umr_bitfield_default },
	 { "DC_HPD4_RX_INT_TIMER", 16, 25, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_HPD5_INT_STATUS[] = {
	 { "DC_HPD5_INT_STATUS", 0, 0, &umr_bitfield_default },
	 { "DC_HPD5_RX_INT_STATUS", 8, 8, &umr_bitfield_default },
	 { "DC_HPD5_SENSE_DELAYED", 4, 4, &umr_bitfield_default },
	 { "DC_HPD5_SENSE", 1, 1, &umr_bitfield_default },
	 { "DC_HPD5_TOGGLE_FILT_CON_TIMER_VAL", 12, 19, &umr_bitfield_default },
	 { "DC_HPD5_TOGGLE_FILT_DISCON_TIMER_VAL", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_HPD5_INT_CONTROL[] = {
	 { "DC_HPD5_INT_ACK", 0, 0, &umr_bitfield_default },
	 { "DC_HPD5_INT_EN", 16, 16, &umr_bitfield_default },
	 { "DC_HPD5_INT_POLARITY", 8, 8, &umr_bitfield_default },
	 { "DC_HPD5_RX_INT_ACK", 20, 20, &umr_bitfield_default },
	 { "DC_HPD5_RX_INT_EN", 24, 24, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_HPD5_CONTROL[] = {
	 { "DC_HPD5_CONNECTION_TIMER", 0, 12, &umr_bitfield_default },
	 { "DC_HPD5_EN", 28, 28, &umr_bitfield_default },
	 { "DC_HPD5_RX_INT_TIMER", 16, 25, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_HPD6_INT_STATUS[] = {
	 { "DC_HPD6_INT_STATUS", 0, 0, &umr_bitfield_default },
	 { "DC_HPD6_RX_INT_STATUS", 8, 8, &umr_bitfield_default },
	 { "DC_HPD6_SENSE_DELAYED", 4, 4, &umr_bitfield_default },
	 { "DC_HPD6_SENSE", 1, 1, &umr_bitfield_default },
	 { "DC_HPD6_TOGGLE_FILT_CON_TIMER_VAL", 12, 19, &umr_bitfield_default },
	 { "DC_HPD6_TOGGLE_FILT_DISCON_TIMER_VAL", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_HPD6_INT_CONTROL[] = {
	 { "DC_HPD6_INT_ACK", 0, 0, &umr_bitfield_default },
	 { "DC_HPD6_INT_EN", 16, 16, &umr_bitfield_default },
	 { "DC_HPD6_INT_POLARITY", 8, 8, &umr_bitfield_default },
	 { "DC_HPD6_RX_INT_ACK", 20, 20, &umr_bitfield_default },
	 { "DC_HPD6_RX_INT_EN", 24, 24, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_HPD6_CONTROL[] = {
	 { "DC_HPD6_CONNECTION_TIMER", 0, 12, &umr_bitfield_default },
	 { "DC_HPD6_EN", 28, 28, &umr_bitfield_default },
	 { "DC_HPD6_RX_INT_TIMER", 16, 25, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_I2C_CONTROL[] = {
	 { "DC_I2C_DBG_REF_SEL", 31, 31, &umr_bitfield_default },
	 { "DC_I2C_DDC_SELECT", 8, 10, &umr_bitfield_default },
	 { "DC_I2C_GO", 0, 0, &umr_bitfield_default },
	 { "DC_I2C_SEND_RESET", 2, 2, &umr_bitfield_default },
	 { "DC_I2C_SOFT_RESET", 1, 1, &umr_bitfield_default },
	 { "DC_I2C_SW_STATUS_RESET", 3, 3, &umr_bitfield_default },
	 { "DC_I2C_TRANSACTION_COUNT", 20, 21, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_I2C_ARBITRATION[] = {
	 { "DC_I2C_ABORT_HW_XFER", 8, 8, &umr_bitfield_default },
	 { "DC_I2C_ABORT_SW_XFER", 12, 12, &umr_bitfield_default },
	 { "DC_I2C_DMCU_DONE_USING_I2C_REG", 25, 25, &umr_bitfield_default },
	 { "DC_I2C_DMCU_USE_I2C_REG_REQ", 24, 24, &umr_bitfield_default },
	 { "DC_I2C_NO_QUEUED_SW_GO", 4, 4, &umr_bitfield_default },
	 { "DC_I2C_REG_RW_CNTL_STATUS", 2, 3, &umr_bitfield_default },
	 { "DC_I2C_SW_DONE_USING_I2C_REG", 21, 21, &umr_bitfield_default },
	 { "DC_I2C_SW_PRIORITY", 0, 1, &umr_bitfield_default },
	 { "DC_I2C_SW_USE_I2C_REG_REQ", 20, 20, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_I2C_INTERRUPT_CONTROL[] = {
	 { "DC_I2C_DDC1_HW_DONE_ACK", 5, 5, &umr_bitfield_default },
	 { "DC_I2C_DDC1_HW_DONE_INT", 4, 4, &umr_bitfield_default },
	 { "DC_I2C_DDC1_HW_DONE_MASK", 6, 6, &umr_bitfield_default },
	 { "DC_I2C_DDC2_HW_DONE_ACK", 9, 9, &umr_bitfield_default },
	 { "DC_I2C_DDC2_HW_DONE_INT", 8, 8, &umr_bitfield_default },
	 { "DC_I2C_DDC2_HW_DONE_MASK", 10, 10, &umr_bitfield_default },
	 { "DC_I2C_DDC3_HW_DONE_ACK", 13, 13, &umr_bitfield_default },
	 { "DC_I2C_DDC3_HW_DONE_INT", 12, 12, &umr_bitfield_default },
	 { "DC_I2C_DDC3_HW_DONE_MASK", 14, 14, &umr_bitfield_default },
	 { "DC_I2C_DDC4_HW_DONE_ACK", 17, 17, &umr_bitfield_default },
	 { "DC_I2C_DDC4_HW_DONE_INT", 16, 16, &umr_bitfield_default },
	 { "DC_I2C_DDC4_HW_DONE_MASK", 18, 18, &umr_bitfield_default },
	 { "DC_I2C_DDC5_HW_DONE_ACK", 21, 21, &umr_bitfield_default },
	 { "DC_I2C_DDC5_HW_DONE_INT", 20, 20, &umr_bitfield_default },
	 { "DC_I2C_DDC5_HW_DONE_MASK", 22, 22, &umr_bitfield_default },
	 { "DC_I2C_DDC6_HW_DONE_ACK", 25, 25, &umr_bitfield_default },
	 { "DC_I2C_DDC6_HW_DONE_INT", 24, 24, &umr_bitfield_default },
	 { "DC_I2C_DDC6_HW_DONE_MASK", 26, 26, &umr_bitfield_default },
	 { "DC_I2C_DDCVGA_HW_DONE_ACK", 28, 28, &umr_bitfield_default },
	 { "DC_I2C_DDCVGA_HW_DONE_INT", 27, 27, &umr_bitfield_default },
	 { "DC_I2C_DDCVGA_HW_DONE_MASK", 29, 29, &umr_bitfield_default },
	 { "DC_I2C_SW_DONE_ACK", 1, 1, &umr_bitfield_default },
	 { "DC_I2C_SW_DONE_INT", 0, 0, &umr_bitfield_default },
	 { "DC_I2C_SW_DONE_MASK", 2, 2, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_I2C_SW_STATUS[] = {
	 { "DC_I2C_SW_ABORTED", 4, 4, &umr_bitfield_default },
	 { "DC_I2C_SW_BUFFER_OVERFLOW", 7, 7, &umr_bitfield_default },
	 { "DC_I2C_SW_DONE", 2, 2, &umr_bitfield_default },
	 { "DC_I2C_SW_INTERRUPTED", 6, 6, &umr_bitfield_default },
	 { "DC_I2C_SW_NACK0", 12, 12, &umr_bitfield_default },
	 { "DC_I2C_SW_NACK1", 13, 13, &umr_bitfield_default },
	 { "DC_I2C_SW_NACK2", 14, 14, &umr_bitfield_default },
	 { "DC_I2C_SW_NACK3", 15, 15, &umr_bitfield_default },
	 { "DC_I2C_SW_REQ", 18, 18, &umr_bitfield_default },
	 { "DC_I2C_SW_STATUS", 0, 1, &umr_bitfield_default },
	 { "DC_I2C_SW_STOPPED_ON_NACK", 8, 8, &umr_bitfield_default },
	 { "DC_I2C_SW_TIMEOUT", 5, 5, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_I2C_DDC1_HW_STATUS[] = {
	 { "DC_I2C_DDC1_EDID_DETECT_NUM_VALID_TRIES", 24, 27, &umr_bitfield_default },
	 { "DC_I2C_DDC1_EDID_DETECT_STATE", 28, 30, &umr_bitfield_default },
	 { "DC_I2C_DDC1_EDID_DETECT_STATUS", 20, 20, &umr_bitfield_default },
	 { "DC_I2C_DDC1_HW_DONE", 3, 3, &umr_bitfield_default },
	 { "DC_I2C_DDC1_HW_REQ", 16, 16, &umr_bitfield_default },
	 { "DC_I2C_DDC1_HW_STATUS", 0, 1, &umr_bitfield_default },
	 { "DC_I2C_DDC1_HW_URG", 17, 17, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_I2C_DDC2_HW_STATUS[] = {
	 { "DC_I2C_DDC2_EDID_DETECT_NUM_VALID_TRIES", 24, 27, &umr_bitfield_default },
	 { "DC_I2C_DDC2_EDID_DETECT_STATE", 28, 30, &umr_bitfield_default },
	 { "DC_I2C_DDC2_EDID_DETECT_STATUS", 20, 20, &umr_bitfield_default },
	 { "DC_I2C_DDC2_HW_DONE", 3, 3, &umr_bitfield_default },
	 { "DC_I2C_DDC2_HW_REQ", 16, 16, &umr_bitfield_default },
	 { "DC_I2C_DDC2_HW_STATUS", 0, 1, &umr_bitfield_default },
	 { "DC_I2C_DDC2_HW_URG", 17, 17, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_I2C_DDC3_HW_STATUS[] = {
	 { "DC_I2C_DDC3_EDID_DETECT_NUM_VALID_TRIES", 24, 27, &umr_bitfield_default },
	 { "DC_I2C_DDC3_EDID_DETECT_STATE", 28, 30, &umr_bitfield_default },
	 { "DC_I2C_DDC3_EDID_DETECT_STATUS", 20, 20, &umr_bitfield_default },
	 { "DC_I2C_DDC3_HW_DONE", 3, 3, &umr_bitfield_default },
	 { "DC_I2C_DDC3_HW_REQ", 16, 16, &umr_bitfield_default },
	 { "DC_I2C_DDC3_HW_STATUS", 0, 1, &umr_bitfield_default },
	 { "DC_I2C_DDC3_HW_URG", 17, 17, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_I2C_DDC4_HW_STATUS[] = {
	 { "DC_I2C_DDC4_EDID_DETECT_NUM_VALID_TRIES", 24, 27, &umr_bitfield_default },
	 { "DC_I2C_DDC4_EDID_DETECT_STATE", 28, 30, &umr_bitfield_default },
	 { "DC_I2C_DDC4_EDID_DETECT_STATUS", 20, 20, &umr_bitfield_default },
	 { "DC_I2C_DDC4_HW_DONE", 3, 3, &umr_bitfield_default },
	 { "DC_I2C_DDC4_HW_REQ", 16, 16, &umr_bitfield_default },
	 { "DC_I2C_DDC4_HW_STATUS", 0, 1, &umr_bitfield_default },
	 { "DC_I2C_DDC4_HW_URG", 17, 17, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_I2C_DDC5_HW_STATUS[] = {
	 { "DC_I2C_DDC5_EDID_DETECT_NUM_VALID_TRIES", 24, 27, &umr_bitfield_default },
	 { "DC_I2C_DDC5_EDID_DETECT_STATE", 28, 30, &umr_bitfield_default },
	 { "DC_I2C_DDC5_EDID_DETECT_STATUS", 20, 20, &umr_bitfield_default },
	 { "DC_I2C_DDC5_HW_DONE", 3, 3, &umr_bitfield_default },
	 { "DC_I2C_DDC5_HW_REQ", 16, 16, &umr_bitfield_default },
	 { "DC_I2C_DDC5_HW_STATUS", 0, 1, &umr_bitfield_default },
	 { "DC_I2C_DDC5_HW_URG", 17, 17, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_I2C_DDC6_HW_STATUS[] = {
	 { "DC_I2C_DDC6_EDID_DETECT_NUM_VALID_TRIES", 24, 27, &umr_bitfield_default },
	 { "DC_I2C_DDC6_EDID_DETECT_STATE", 28, 30, &umr_bitfield_default },
	 { "DC_I2C_DDC6_EDID_DETECT_STATUS", 20, 20, &umr_bitfield_default },
	 { "DC_I2C_DDC6_HW_DONE", 3, 3, &umr_bitfield_default },
	 { "DC_I2C_DDC6_HW_REQ", 16, 16, &umr_bitfield_default },
	 { "DC_I2C_DDC6_HW_STATUS", 0, 1, &umr_bitfield_default },
	 { "DC_I2C_DDC6_HW_URG", 17, 17, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_I2C_DDC1_SPEED[] = {
	 { "DC_I2C_DDC1_DISABLE_FILTER_DURING_STALL", 4, 4, &umr_bitfield_default },
	 { "DC_I2C_DDC1_PRESCALE", 16, 31, &umr_bitfield_default },
	 { "DC_I2C_DDC1_THRESHOLD", 0, 1, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_I2C_DDC1_SETUP[] = {
	 { "DC_I2C_DDC1_CLK_DRIVE_EN", 7, 7, &umr_bitfield_default },
	 { "DC_I2C_DDC1_DATA_DRIVE_EN", 0, 0, &umr_bitfield_default },
	 { "DC_I2C_DDC1_DATA_DRIVE_SEL", 1, 1, &umr_bitfield_default },
	 { "DC_I2C_DDC1_EDID_DETECT_ENABLE", 4, 4, &umr_bitfield_default },
	 { "DC_I2C_DDC1_EDID_DETECT_MODE", 5, 5, &umr_bitfield_default },
	 { "DC_I2C_DDC1_ENABLE", 6, 6, &umr_bitfield_default },
	 { "DC_I2C_DDC1_INTRA_BYTE_DELAY", 8, 15, &umr_bitfield_default },
	 { "DC_I2C_DDC1_INTRA_TRANSACTION_DELAY", 16, 23, &umr_bitfield_default },
	 { "DC_I2C_DDC1_TIME_LIMIT", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_I2C_DDC2_SPEED[] = {
	 { "DC_I2C_DDC2_DISABLE_FILTER_DURING_STALL", 4, 4, &umr_bitfield_default },
	 { "DC_I2C_DDC2_PRESCALE", 16, 31, &umr_bitfield_default },
	 { "DC_I2C_DDC2_THRESHOLD", 0, 1, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_I2C_DDC2_SETUP[] = {
	 { "DC_I2C_DDC2_CLK_DRIVE_EN", 7, 7, &umr_bitfield_default },
	 { "DC_I2C_DDC2_DATA_DRIVE_EN", 0, 0, &umr_bitfield_default },
	 { "DC_I2C_DDC2_DATA_DRIVE_SEL", 1, 1, &umr_bitfield_default },
	 { "DC_I2C_DDC2_EDID_DETECT_ENABLE", 4, 4, &umr_bitfield_default },
	 { "DC_I2C_DDC2_EDID_DETECT_MODE", 5, 5, &umr_bitfield_default },
	 { "DC_I2C_DDC2_ENABLE", 6, 6, &umr_bitfield_default },
	 { "DC_I2C_DDC2_INTRA_BYTE_DELAY", 8, 15, &umr_bitfield_default },
	 { "DC_I2C_DDC2_INTRA_TRANSACTION_DELAY", 16, 23, &umr_bitfield_default },
	 { "DC_I2C_DDC2_TIME_LIMIT", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_I2C_DDC3_SPEED[] = {
	 { "DC_I2C_DDC3_DISABLE_FILTER_DURING_STALL", 4, 4, &umr_bitfield_default },
	 { "DC_I2C_DDC3_PRESCALE", 16, 31, &umr_bitfield_default },
	 { "DC_I2C_DDC3_THRESHOLD", 0, 1, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_I2C_DDC3_SETUP[] = {
	 { "DC_I2C_DDC3_CLK_DRIVE_EN", 7, 7, &umr_bitfield_default },
	 { "DC_I2C_DDC3_DATA_DRIVE_EN", 0, 0, &umr_bitfield_default },
	 { "DC_I2C_DDC3_DATA_DRIVE_SEL", 1, 1, &umr_bitfield_default },
	 { "DC_I2C_DDC3_EDID_DETECT_ENABLE", 4, 4, &umr_bitfield_default },
	 { "DC_I2C_DDC3_EDID_DETECT_MODE", 5, 5, &umr_bitfield_default },
	 { "DC_I2C_DDC3_ENABLE", 6, 6, &umr_bitfield_default },
	 { "DC_I2C_DDC3_INTRA_BYTE_DELAY", 8, 15, &umr_bitfield_default },
	 { "DC_I2C_DDC3_INTRA_TRANSACTION_DELAY", 16, 23, &umr_bitfield_default },
	 { "DC_I2C_DDC3_TIME_LIMIT", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_I2C_DDC4_SPEED[] = {
	 { "DC_I2C_DDC4_DISABLE_FILTER_DURING_STALL", 4, 4, &umr_bitfield_default },
	 { "DC_I2C_DDC4_PRESCALE", 16, 31, &umr_bitfield_default },
	 { "DC_I2C_DDC4_THRESHOLD", 0, 1, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_I2C_DDC4_SETUP[] = {
	 { "DC_I2C_DDC4_CLK_DRIVE_EN", 7, 7, &umr_bitfield_default },
	 { "DC_I2C_DDC4_DATA_DRIVE_EN", 0, 0, &umr_bitfield_default },
	 { "DC_I2C_DDC4_DATA_DRIVE_SEL", 1, 1, &umr_bitfield_default },
	 { "DC_I2C_DDC4_EDID_DETECT_ENABLE", 4, 4, &umr_bitfield_default },
	 { "DC_I2C_DDC4_EDID_DETECT_MODE", 5, 5, &umr_bitfield_default },
	 { "DC_I2C_DDC4_ENABLE", 6, 6, &umr_bitfield_default },
	 { "DC_I2C_DDC4_INTRA_BYTE_DELAY", 8, 15, &umr_bitfield_default },
	 { "DC_I2C_DDC4_INTRA_TRANSACTION_DELAY", 16, 23, &umr_bitfield_default },
	 { "DC_I2C_DDC4_TIME_LIMIT", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_I2C_DDC5_SPEED[] = {
	 { "DC_I2C_DDC5_DISABLE_FILTER_DURING_STALL", 4, 4, &umr_bitfield_default },
	 { "DC_I2C_DDC5_PRESCALE", 16, 31, &umr_bitfield_default },
	 { "DC_I2C_DDC5_THRESHOLD", 0, 1, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_I2C_DDC5_SETUP[] = {
	 { "DC_I2C_DDC5_CLK_DRIVE_EN", 7, 7, &umr_bitfield_default },
	 { "DC_I2C_DDC5_DATA_DRIVE_EN", 0, 0, &umr_bitfield_default },
	 { "DC_I2C_DDC5_DATA_DRIVE_SEL", 1, 1, &umr_bitfield_default },
	 { "DC_I2C_DDC5_EDID_DETECT_ENABLE", 4, 4, &umr_bitfield_default },
	 { "DC_I2C_DDC5_EDID_DETECT_MODE", 5, 5, &umr_bitfield_default },
	 { "DC_I2C_DDC5_ENABLE", 6, 6, &umr_bitfield_default },
	 { "DC_I2C_DDC5_INTRA_BYTE_DELAY", 8, 15, &umr_bitfield_default },
	 { "DC_I2C_DDC5_INTRA_TRANSACTION_DELAY", 16, 23, &umr_bitfield_default },
	 { "DC_I2C_DDC5_TIME_LIMIT", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_I2C_DDC6_SPEED[] = {
	 { "DC_I2C_DDC6_DISABLE_FILTER_DURING_STALL", 4, 4, &umr_bitfield_default },
	 { "DC_I2C_DDC6_PRESCALE", 16, 31, &umr_bitfield_default },
	 { "DC_I2C_DDC6_THRESHOLD", 0, 1, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_I2C_DDC6_SETUP[] = {
	 { "DC_I2C_DDC6_CLK_DRIVE_EN", 7, 7, &umr_bitfield_default },
	 { "DC_I2C_DDC6_DATA_DRIVE_EN", 0, 0, &umr_bitfield_default },
	 { "DC_I2C_DDC6_DATA_DRIVE_SEL", 1, 1, &umr_bitfield_default },
	 { "DC_I2C_DDC6_EDID_DETECT_ENABLE", 4, 4, &umr_bitfield_default },
	 { "DC_I2C_DDC6_EDID_DETECT_MODE", 5, 5, &umr_bitfield_default },
	 { "DC_I2C_DDC6_ENABLE", 6, 6, &umr_bitfield_default },
	 { "DC_I2C_DDC6_INTRA_BYTE_DELAY", 8, 15, &umr_bitfield_default },
	 { "DC_I2C_DDC6_INTRA_TRANSACTION_DELAY", 16, 23, &umr_bitfield_default },
	 { "DC_I2C_DDC6_TIME_LIMIT", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_I2C_TRANSACTION0[] = {
	 { "DC_I2C_COUNT0", 16, 23, &umr_bitfield_default },
	 { "DC_I2C_RW0", 0, 0, &umr_bitfield_default },
	 { "DC_I2C_START0", 12, 12, &umr_bitfield_default },
	 { "DC_I2C_STOP0", 13, 13, &umr_bitfield_default },
	 { "DC_I2C_STOP_ON_NACK0", 8, 8, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_I2C_TRANSACTION1[] = {
	 { "DC_I2C_COUNT1", 16, 23, &umr_bitfield_default },
	 { "DC_I2C_RW1", 0, 0, &umr_bitfield_default },
	 { "DC_I2C_START1", 12, 12, &umr_bitfield_default },
	 { "DC_I2C_STOP1", 13, 13, &umr_bitfield_default },
	 { "DC_I2C_STOP_ON_NACK1", 8, 8, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_I2C_TRANSACTION2[] = {
	 { "DC_I2C_COUNT2", 16, 23, &umr_bitfield_default },
	 { "DC_I2C_RW2", 0, 0, &umr_bitfield_default },
	 { "DC_I2C_START2", 12, 12, &umr_bitfield_default },
	 { "DC_I2C_STOP2", 13, 13, &umr_bitfield_default },
	 { "DC_I2C_STOP_ON_NACK2", 8, 8, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_I2C_TRANSACTION3[] = {
	 { "DC_I2C_COUNT3", 16, 23, &umr_bitfield_default },
	 { "DC_I2C_RW3", 0, 0, &umr_bitfield_default },
	 { "DC_I2C_START3", 12, 12, &umr_bitfield_default },
	 { "DC_I2C_STOP3", 13, 13, &umr_bitfield_default },
	 { "DC_I2C_STOP_ON_NACK3", 8, 8, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_I2C_DATA[] = {
	 { "DC_I2C_DATA", 8, 15, &umr_bitfield_default },
	 { "DC_I2C_DATA_RW", 0, 0, &umr_bitfield_default },
	 { "DC_I2C_INDEX", 16, 23, &umr_bitfield_default },
	 { "DC_I2C_INDEX_WRITE", 31, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmGENERIC_I2C_CONTROL[] = {
	 { "GENERIC_I2C_DBG_REF_SEL", 31, 31, &umr_bitfield_default },
	 { "GENERIC_I2C_ENABLE", 3, 3, &umr_bitfield_default },
	 { "GENERIC_I2C_GO", 0, 0, &umr_bitfield_default },
	 { "GENERIC_I2C_SEND_RESET", 2, 2, &umr_bitfield_default },
	 { "GENERIC_I2C_SOFT_RESET", 1, 1, &umr_bitfield_default },
};
static struct umr_bitfield mmGENERIC_I2C_INTERRUPT_CONTROL[] = {
	 { "GENERIC_I2C_DONE_ACK", 1, 1, &umr_bitfield_default },
	 { "GENERIC_I2C_DONE_INT", 0, 0, &umr_bitfield_default },
	 { "GENERIC_I2C_DONE_MASK", 2, 2, &umr_bitfield_default },
};
static struct umr_bitfield mmGENERIC_I2C_STATUS[] = {
	 { "GENERIC_I2C_ABORTED", 5, 5, &umr_bitfield_default },
	 { "GENERIC_I2C_DONE", 4, 4, &umr_bitfield_default },
	 { "GENERIC_I2C_NACK", 10, 10, &umr_bitfield_default },
	 { "GENERIC_I2C_STATUS", 0, 3, &umr_bitfield_default },
	 { "GENERIC_I2C_STOPPED_ON_NACK", 9, 9, &umr_bitfield_default },
	 { "GENERIC_I2C_TIMEOUT", 6, 6, &umr_bitfield_default },
};
static struct umr_bitfield mmGENERIC_I2C_SPEED[] = {
	 { "GENERIC_I2C_DISABLE_FILTER_DURING_STALL", 4, 4, &umr_bitfield_default },
	 { "GENERIC_I2C_PRESCALE", 16, 31, &umr_bitfield_default },
	 { "GENERIC_I2C_THRESHOLD", 0, 1, &umr_bitfield_default },
};
static struct umr_bitfield mmGENERIC_I2C_SETUP[] = {
	 { "GENERIC_I2C_CLK_DRIVE_EN", 7, 7, &umr_bitfield_default },
	 { "GENERIC_I2C_DATA_DRIVE_EN", 0, 0, &umr_bitfield_default },
	 { "GENERIC_I2C_DATA_DRIVE_SEL", 1, 1, &umr_bitfield_default },
	 { "GENERIC_I2C_INTRA_BYTE_DELAY", 8, 15, &umr_bitfield_default },
	 { "GENERIC_I2C_TIME_LIMIT", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmGENERIC_I2C_TRANSACTION[] = {
	 { "GENERIC_I2C_ACK_ON_READ", 9, 9, &umr_bitfield_default },
	 { "GENERIC_I2C_COUNT", 16, 19, &umr_bitfield_default },
	 { "GENERIC_I2C_RW", 0, 0, &umr_bitfield_default },
	 { "GENERIC_I2C_START", 12, 12, &umr_bitfield_default },
	 { "GENERIC_I2C_STOP", 13, 13, &umr_bitfield_default },
	 { "GENERIC_I2C_STOP_ON_NACK", 8, 8, &umr_bitfield_default },
};
static struct umr_bitfield mmGENERIC_I2C_DATA[] = {
	 { "GENERIC_I2C_DATA", 8, 15, &umr_bitfield_default },
	 { "GENERIC_I2C_DATA_RW", 0, 0, &umr_bitfield_default },
	 { "GENERIC_I2C_INDEX", 16, 19, &umr_bitfield_default },
	 { "GENERIC_I2C_INDEX_WRITE", 31, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmGENERIC_I2C_PIN_SELECTION[] = {
	 { "GENERIC_I2C_SCL_PIN_SEL", 0, 6, &umr_bitfield_default },
	 { "GENERIC_I2C_SDA_PIN_SEL", 8, 14, &umr_bitfield_default },
};
static struct umr_bitfield mmGENERIC_I2C_PIN_DEBUG[] = {
	 { "GENERIC_I2C_SCL_EN", 2, 2, &umr_bitfield_default },
	 { "GENERIC_I2C_SCL_INPUT", 1, 1, &umr_bitfield_default },
	 { "GENERIC_I2C_SCL_OUTPUT", 0, 0, &umr_bitfield_default },
	 { "GENERIC_I2C_SDA_EN", 6, 6, &umr_bitfield_default },
	 { "GENERIC_I2C_SDA_INPUT", 5, 5, &umr_bitfield_default },
	 { "GENERIC_I2C_SDA_OUTPUT", 4, 4, &umr_bitfield_default },
};
static struct umr_bitfield mmDISP_INTERRUPT_STATUS[] = {
	 { "ABM1_BL_UPDATE_INT", 30, 30, &umr_bitfield_default },
	 { "ABM1_HG_READY_INT", 28, 28, &umr_bitfield_default },
	 { "ABM1_LS_READY_INT", 29, 29, &umr_bitfield_default },
	 { "AUX1_LS_DONE_INTERRUPT", 20, 20, &umr_bitfield_default },
	 { "AUX1_SW_DONE_INTERRUPT", 19, 19, &umr_bitfield_default },
	 { "CRTC1_FORCE_COUNT_NOW_INTERRUPT", 6, 6, &umr_bitfield_default },
	 { "CRTC1_FORCE_VSYNC_NEXT_LINE_INTERRUPT", 5, 5, &umr_bitfield_default },
	 { "CRTC1_SET_V_TOTAL_MIN_EVENT_OCCURED_INT", 10, 10, &umr_bitfield_default },
	 { "CRTC1_SNAPSHOT_INTERRUPT", 4, 4, &umr_bitfield_default },
	 { "CRTC1_TRIGA_INTERRUPT", 7, 7, &umr_bitfield_default },
	 { "CRTC1_TRIGB_INTERRUPT", 8, 8, &umr_bitfield_default },
	 { "CRTC1_VSYNC_NOM_INTERRUPT", 9, 9, &umr_bitfield_default },
	 { "DACA_AUTODETECT_INTERRUPT", 22, 22, &umr_bitfield_default },
	 { "DACB_AUTODETECT_INTERRUPT", 23, 23, &umr_bitfield_default },
	 { "DC_HPD1_INTERRUPT", 17, 17, &umr_bitfield_default },
	 { "DC_HPD1_RX_INTERRUPT", 18, 18, &umr_bitfield_default },
	 { "DC_I2C_HW_DONE_INTERRUPT", 25, 25, &umr_bitfield_default },
	 { "DC_I2C_SW_DONE_INTERRUPT", 24, 24, &umr_bitfield_default },
	 { "DIGA_DISPCLK_SWITCH_ALLOWED_INTERRUPT", 21, 21, &umr_bitfield_default },
	 { "DIGA_DP_FAST_TRAINING_COMPLETE_INTERRUPT", 15, 15, &umr_bitfield_default },
	 { "DIGA_DP_VID_STREAM_DISABLE_INTERRUPT", 16, 16, &umr_bitfield_default },
	 { "DISP_INTERRUPT_STATUS_CONTINUE", 31, 31, &umr_bitfield_default },
	 { "DMCU_SCP_INT", 27, 27, &umr_bitfield_default },
	 { "DMCU_UC_INTERNAL_INT", 26, 26, &umr_bitfield_default },
	 { "LB_D1_VBLANK_INTERRUPT", 3, 3, &umr_bitfield_default },
	 { "LB_D1_VLINE_INTERRUPT", 2, 2, &umr_bitfield_default },
	 { "SCL_DISP1_MODE_CHANGE_INTERRUPT", 0, 0, &umr_bitfield_default },
};
static struct umr_bitfield mmDISP_INTERRUPT_STATUS_CONTINUE[] = {
	 { "AUX2_LS_DONE_INTERRUPT", 20, 20, &umr_bitfield_default },
	 { "AUX2_SW_DONE_INTERRUPT", 19, 19, &umr_bitfield_default },
	 { "CRTC2_FORCE_COUNT_NOW_INTERRUPT", 6, 6, &umr_bitfield_default },
	 { "CRTC2_FORCE_VSYNC_NEXT_LINE_INTERRUPT", 5, 5, &umr_bitfield_default },
	 { "CRTC2_SET_V_TOTAL_MIN_EVENT_OCCURED_INT", 10, 10, &umr_bitfield_default },
	 { "CRTC2_SNAPSHOT_INTERRUPT", 4, 4, &umr_bitfield_default },
	 { "CRTC2_TRIGA_INTERRUPT", 7, 7, &umr_bitfield_default },
	 { "CRTC2_TRIGB_INTERRUPT", 8, 8, &umr_bitfield_default },
	 { "CRTC2_VSYNC_NOM_INTERRUPT", 9, 9, &umr_bitfield_default },
	 { "DC_HPD2_INTERRUPT", 17, 17, &umr_bitfield_default },
	 { "DC_HPD2_RX_INTERRUPT", 18, 18, &umr_bitfield_default },
	 { "DIGB_DP_FAST_TRAINING_COMPLETE_INTERRUPT", 15, 15, &umr_bitfield_default },
	 { "DIGB_DP_VID_STREAM_DISABLE_INTERRUPT", 16, 16, &umr_bitfield_default },
	 { "DISP_INTERRUPT_STATUS_CONTINUE2", 31, 31, &umr_bitfield_default },
	 { "DISP_TIMER_INTERRUPT", 24, 24, &umr_bitfield_default },
	 { "LB_D2_VBLANK_INTERRUPT", 3, 3, &umr_bitfield_default },
	 { "LB_D2_VLINE_INTERRUPT", 2, 2, &umr_bitfield_default },
	 { "SCL_DISP2_MODE_CHANGE_INTERRUPT", 0, 0, &umr_bitfield_default },
};
static struct umr_bitfield mmDISP_INTERRUPT_STATUS_CONTINUE2[] = {
	 { "AUX3_LS_DONE_INTERRUPT", 20, 20, &umr_bitfield_default },
	 { "AUX3_SW_DONE_INTERRUPT", 19, 19, &umr_bitfield_default },
	 { "CRTC3_FORCE_COUNT_NOW_INTERRUPT", 6, 6, &umr_bitfield_default },
	 { "CRTC3_FORCE_VSYNC_NEXT_LINE_INTERRUPT", 5, 5, &umr_bitfield_default },
	 { "CRTC3_SET_V_TOTAL_MIN_EVENT_OCCURED_INT", 10, 10, &umr_bitfield_default },
	 { "CRTC3_SNAPSHOT_INTERRUPT", 4, 4, &umr_bitfield_default },
	 { "CRTC3_TRIGA_INTERRUPT", 7, 7, &umr_bitfield_default },
	 { "CRTC3_TRIGB_INTERRUPT", 8, 8, &umr_bitfield_default },
	 { "CRTC3_VSYNC_NOM_INTERRUPT", 9, 9, &umr_bitfield_default },
	 { "DC_HPD3_INTERRUPT", 17, 17, &umr_bitfield_default },
	 { "DC_HPD3_RX_INTERRUPT", 18, 18, &umr_bitfield_default },
	 { "DIGC_DP_FAST_TRAINING_COMPLETE_INTERRUPT", 15, 15, &umr_bitfield_default },
	 { "DIGC_DP_VID_STREAM_DISABLE_INTERRUPT", 16, 16, &umr_bitfield_default },
	 { "DISP_INTERRUPT_STATUS_CONTINUE3", 31, 31, &umr_bitfield_default },
	 { "LB_D3_VBLANK_INTERRUPT", 3, 3, &umr_bitfield_default },
	 { "LB_D3_VLINE_INTERRUPT", 2, 2, &umr_bitfield_default },
	 { "SCL_DISP3_MODE_CHANGE_INTERRUPT", 0, 0, &umr_bitfield_default },
};
static struct umr_bitfield mmDISP_INTERRUPT_STATUS_CONTINUE3[] = {
	 { "AUX4_LS_DONE_INTERRUPT", 20, 20, &umr_bitfield_default },
	 { "AUX4_SW_DONE_INTERRUPT", 19, 19, &umr_bitfield_default },
	 { "CRTC4_FORCE_COUNT_NOW_INTERRUPT", 6, 6, &umr_bitfield_default },
	 { "CRTC4_FORCE_VSYNC_NEXT_LINE_INTERRUPT", 5, 5, &umr_bitfield_default },
	 { "CRTC4_SET_V_TOTAL_MIN_EVENT_OCCURED_INT", 10, 10, &umr_bitfield_default },
	 { "CRTC4_SNAPSHOT_INTERRUPT", 4, 4, &umr_bitfield_default },
	 { "CRTC4_TRIGA_INTERRUPT", 7, 7, &umr_bitfield_default },
	 { "CRTC4_TRIGB_INTERRUPT", 8, 8, &umr_bitfield_default },
	 { "CRTC4_VSYNC_NOM_INTERRUPT", 9, 9, &umr_bitfield_default },
	 { "DC_HPD4_INTERRUPT", 17, 17, &umr_bitfield_default },
	 { "DC_HPD4_RX_INTERRUPT", 18, 18, &umr_bitfield_default },
	 { "DIGD_DP_FAST_TRAINING_COMPLETE_INTERRUPT", 15, 15, &umr_bitfield_default },
	 { "DIGD_DP_VID_STREAM_DISABLE_INTERRUPT", 16, 16, &umr_bitfield_default },
	 { "DISP_INTERRUPT_STATUS_CONTINUE4", 31, 31, &umr_bitfield_default },
	 { "LB_D4_VBLANK_INTERRUPT", 3, 3, &umr_bitfield_default },
	 { "LB_D4_VLINE_INTERRUPT", 2, 2, &umr_bitfield_default },
	 { "SCL_DISP4_MODE_CHANGE_INTERRUPT", 0, 0, &umr_bitfield_default },
};
static struct umr_bitfield mmDOUT_POWER_MANAGEMENT_CNTL[] = {
	 { "PM_ALL_BUSY_OFF", 8, 8, &umr_bitfield_default },
	 { "PM_ASSERT_RESET", 0, 0, &umr_bitfield_default },
};
static struct umr_bitfield mmDISP_TIMER_CONTROL[] = {
	 { "DISP_TIMER_INT_COUNT", 0, 24, &umr_bitfield_default },
	 { "DISP_TIMER_INT_ENABLE", 25, 25, &umr_bitfield_default },
	 { "DISP_TIMER_INT", 30, 30, &umr_bitfield_default },
	 { "DISP_TIMER_INT_MSK", 27, 27, &umr_bitfield_default },
	 { "DISP_TIMER_INT_RUNNING", 26, 26, &umr_bitfield_default },
	 { "DISP_TIMER_INT_STAT_AK", 29, 29, &umr_bitfield_default },
	 { "DISP_TIMER_INT_STAT", 28, 28, &umr_bitfield_default },
};
static struct umr_bitfield mmDOUT_SCRATCH0[] = {
	 { "DOUT_SCRATCH0", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDOUT_SCRATCH1[] = {
	 { "DOUT_SCRATCH1", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDOUT_SCRATCH2[] = {
	 { "DOUT_SCRATCH2", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDOUT_SCRATCH3[] = {
	 { "DOUT_SCRATCH3", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDOUT_SCRATCH4[] = {
	 { "DOUT_SCRATCH4", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDOUT_SCRATCH5[] = {
	 { "DOUT_SCRATCH5", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDOUT_SCRATCH6[] = {
	 { "DOUT_SCRATCH6", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDOUT_SCRATCH7[] = {
	 { "DOUT_SCRATCH7", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDOUT_TEST_DEBUG_INDEX[] = {
	 { "DOUT_TEST_DEBUG_INDEX", 0, 7, &umr_bitfield_default },
	 { "DOUT_TEST_DEBUG_WRITE_EN", 8, 8, &umr_bitfield_default },
};
static struct umr_bitfield mmDOUT_TEST_DEBUG_DATA[] = {
	 { "DOUT_TEST_DEBUG_DATA", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDISP_INTERRUPT_STATUS_CONTINUE4[] = {
	 { "AUX5_LS_DONE_INTERRUPT", 20, 20, &umr_bitfield_default },
	 { "AUX5_SW_DONE_INTERRUPT", 19, 19, &umr_bitfield_default },
	 { "CRTC5_FORCE_COUNT_NOW_INTERRUPT", 6, 6, &umr_bitfield_default },
	 { "CRTC5_FORCE_VSYNC_NEXT_LINE_INTERRUPT", 5, 5, &umr_bitfield_default },
	 { "CRTC5_SET_V_TOTAL_MIN_EVENT_OCCURED_INT", 10, 10, &umr_bitfield_default },
	 { "CRTC5_SNAPSHOT_INTERRUPT", 4, 4, &umr_bitfield_default },
	 { "CRTC5_TRIGA_INTERRUPT", 7, 7, &umr_bitfield_default },
	 { "CRTC5_TRIGB_INTERRUPT", 8, 8, &umr_bitfield_default },
	 { "CRTC5_VSYNC_NOM_INTERRUPT", 9, 9, &umr_bitfield_default },
	 { "DC_HPD5_INTERRUPT", 17, 17, &umr_bitfield_default },
	 { "DC_HPD5_RX_INTERRUPT", 18, 18, &umr_bitfield_default },
	 { "DIGE_DP_FAST_TRAINING_COMPLETE_INTERRUPT", 15, 15, &umr_bitfield_default },
	 { "DIGE_DP_VID_STREAM_DISABLE_INTERRUPT", 16, 16, &umr_bitfield_default },
	 { "DISP_INTERRUPT_STATUS_CONTINUE5", 31, 31, &umr_bitfield_default },
	 { "LB_D5_VBLANK_INTERRUPT", 3, 3, &umr_bitfield_default },
	 { "LB_D5_VLINE_INTERRUPT", 2, 2, &umr_bitfield_default },
	 { "SCL_DISP5_MODE_CHANGE_INTERRUPT", 0, 0, &umr_bitfield_default },
};
static struct umr_bitfield mmDISP_INTERRUPT_STATUS_CONTINUE5[] = {
	 { "AUX6_LS_DONE_INTERRUPT", 20, 20, &umr_bitfield_default },
	 { "AUX6_SW_DONE_INTERRUPT", 19, 19, &umr_bitfield_default },
	 { "CRTC6_FORCE_COUNT_NOW_INTERRUPT", 6, 6, &umr_bitfield_default },
	 { "CRTC6_FORCE_VSYNC_NEXT_LINE_INTERRUPT", 5, 5, &umr_bitfield_default },
	 { "CRTC6_SET_V_TOTAL_MIN_EVENT_OCCURED_INT", 10, 10, &umr_bitfield_default },
	 { "CRTC6_SNAPSHOT_INTERRUPT", 4, 4, &umr_bitfield_default },
	 { "CRTC6_TRIGA_INTERRUPT", 7, 7, &umr_bitfield_default },
	 { "CRTC6_TRIGB_INTERRUPT", 8, 8, &umr_bitfield_default },
	 { "CRTC6_VSYNC_NOM_INTERRUPT", 9, 9, &umr_bitfield_default },
	 { "DC_HPD6_INTERRUPT", 17, 17, &umr_bitfield_default },
	 { "DC_HPD6_RX_INTERRUPT", 18, 18, &umr_bitfield_default },
	 { "DIGF_DP_FAST_TRAINING_COMPLETE_INTERRUPT", 15, 15, &umr_bitfield_default },
	 { "DIGF_DP_VID_STREAM_DISABLE_INTERRUPT", 16, 16, &umr_bitfield_default },
	 { "LB_D6_VBLANK_INTERRUPT", 3, 3, &umr_bitfield_default },
	 { "LB_D6_VLINE_INTERRUPT", 2, 2, &umr_bitfield_default },
	 { "SCL_DISP6_MODE_CHANGE_INTERRUPT", 0, 0, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_I2C_DDCVGA_HW_STATUS[] = {
	 { "DC_I2C_DDCVGA_EDID_DETECT_NUM_VALID_TRIES", 24, 27, &umr_bitfield_default },
	 { "DC_I2C_DDCVGA_EDID_DETECT_STATE", 28, 30, &umr_bitfield_default },
	 { "DC_I2C_DDCVGA_EDID_DETECT_STATUS", 20, 20, &umr_bitfield_default },
	 { "DC_I2C_DDCVGA_HW_DONE", 3, 3, &umr_bitfield_default },
	 { "DC_I2C_DDCVGA_HW_REQ", 16, 16, &umr_bitfield_default },
	 { "DC_I2C_DDCVGA_HW_STATUS", 0, 1, &umr_bitfield_default },
	 { "DC_I2C_DDCVGA_HW_URG", 17, 17, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_I2C_DDCVGA_SPEED[] = {
	 { "DC_I2C_DDCVGA_DISABLE_FILTER_DURING_STALL", 4, 4, &umr_bitfield_default },
	 { "DC_I2C_DDCVGA_PRESCALE", 16, 31, &umr_bitfield_default },
	 { "DC_I2C_DDCVGA_THRESHOLD", 0, 1, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_I2C_DDCVGA_SETUP[] = {
	 { "DC_I2C_DDCVGA_CLK_DRIVE_EN", 7, 7, &umr_bitfield_default },
	 { "DC_I2C_DDCVGA_DATA_DRIVE_EN", 0, 0, &umr_bitfield_default },
	 { "DC_I2C_DDCVGA_DATA_DRIVE_SEL", 1, 1, &umr_bitfield_default },
	 { "DC_I2C_DDCVGA_EDID_DETECT_ENABLE", 4, 4, &umr_bitfield_default },
	 { "DC_I2C_DDCVGA_EDID_DETECT_MODE", 5, 5, &umr_bitfield_default },
	 { "DC_I2C_DDCVGA_ENABLE", 6, 6, &umr_bitfield_default },
	 { "DC_I2C_DDCVGA_INTRA_BYTE_DELAY", 8, 15, &umr_bitfield_default },
	 { "DC_I2C_DDCVGA_INTRA_TRANSACTION_DELAY", 16, 23, &umr_bitfield_default },
	 { "DC_I2C_DDCVGA_TIME_LIMIT", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDVO_ENABLE[] = {
	 { "DVO_ENABLE", 0, 0, &umr_bitfield_default },
};
static struct umr_bitfield mmDVO_SOURCE_SELECT[] = {
	 { "DVO_SOURCE_SELECT", 0, 2, &umr_bitfield_default },
	 { "DVO_STEREOSYNC_SELECT", 16, 18, &umr_bitfield_default },
};
static struct umr_bitfield mmDVO_OUTPUT[] = {
	 { "DVO_CLOCK_MODE", 8, 8, &umr_bitfield_default },
	 { "DVO_OUTPUT_ENABLE_MODE", 0, 1, &umr_bitfield_default },
};
static struct umr_bitfield mmDVO_CONTROL[] = {
	 { "DVO_COLOR_FORMAT", 24, 25, &umr_bitfield_default },
	 { "DVO_CTL3", 31, 31, &umr_bitfield_default },
	 { "DVO_DUAL_CHANNEL_EN", 8, 8, &umr_bitfield_default },
	 { "DVO_INVERT_DVOCLK", 18, 18, &umr_bitfield_default },
	 { "DVO_RATE_SELECT", 0, 0, &umr_bitfield_default },
	 { "DVO_RESET_FIFO", 16, 16, &umr_bitfield_default },
	 { "DVO_SDRCLK_SEL", 1, 1, &umr_bitfield_default },
	 { "DVO_SYNC_PHASE", 17, 17, &umr_bitfield_default },
};
static struct umr_bitfield mmDVO_CRC_EN[] = {
	 { "DVO_CRC2_EN", 16, 16, &umr_bitfield_default },
};
static struct umr_bitfield mmDVO_CRC2_SIG_MASK[] = {
	 { "DVO_CRC2_SIG_MASK", 0, 26, &umr_bitfield_default },
};
static struct umr_bitfield mmDVO_CRC2_SIG_RESULT[] = {
	 { "DVO_CRC2_SIG_RESULT", 0, 26, &umr_bitfield_default },
};
static struct umr_bitfield mmDVO_FIFO_ERROR_STATUS[] = {
	 { "DVO_FIFO_CAL_AVERAGE_LEVEL", 10, 15, &umr_bitfield_default },
	 { "DVO_FIFO_CALIBRATED", 29, 29, &umr_bitfield_default },
	 { "DVO_FIFO_ERROR_ACK", 8, 8, &umr_bitfield_default },
	 { "DVO_FIFO_FORCE_RECAL_AVERAGE", 30, 30, &umr_bitfield_default },
	 { "DVO_FIFO_FORCE_RECOMP_MINMAX", 31, 31, &umr_bitfield_default },
	 { "DVO_FIFO_LEVEL_ERROR", 0, 0, &umr_bitfield_default },
	 { "DVO_FIFO_MAXIMUM_LEVEL", 16, 19, &umr_bitfield_default },
	 { "DVO_FIFO_MINIMUM_LEVEL", 22, 25, &umr_bitfield_default },
	 { "DVO_FIFO_OVERWRITE_LEVEL", 2, 7, &umr_bitfield_default },
	 { "DVO_FIFO_USE_OVERWRITE_LEVEL", 1, 1, &umr_bitfield_default },
};
static struct umr_bitfield mmDCDEBUG_BUS_CLK1_SEL[] = {
	 { "DCDEBUG_BUS_CLK1_SEL", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCDEBUG_BUS_CLK2_SEL[] = {
	 { "DCDEBUG_BUS_CLK2_SEL", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCDEBUG_BUS_CLK3_SEL[] = {
	 { "DCDEBUG_BUS_CLK3_SEL", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCDEBUG_BUS_CLK4_SEL[] = {
	 { "DCDEBUG_BUS_CLK4_SEL", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_HPD1_FAST_TRAIN_CNTL[] = {
	 { "DC_HPD1_CONNECT_AUX_TX_DELAY", 0, 7, &umr_bitfield_default },
	 { "DC_HPD1_CONNECT_AUX_TX_EN", 24, 24, &umr_bitfield_default },
	 { "DC_HPD1_CONNECT_FAST_TRAIN_DELAY", 12, 19, &umr_bitfield_default },
	 { "DC_HPD1_CONNECT_FAST_TRAIN_EN", 28, 28, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_HPD2_FAST_TRAIN_CNTL[] = {
	 { "DC_HPD2_CONNECT_AUX_TX_DELAY", 0, 7, &umr_bitfield_default },
	 { "DC_HPD2_CONNECT_AUX_TX_EN", 24, 24, &umr_bitfield_default },
	 { "DC_HPD2_CONNECT_FAST_TRAIN_DELAY", 12, 19, &umr_bitfield_default },
	 { "DC_HPD2_CONNECT_FAST_TRAIN_EN", 28, 28, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_HPD3_FAST_TRAIN_CNTL[] = {
	 { "DC_HPD3_CONNECT_AUX_TX_DELAY", 0, 7, &umr_bitfield_default },
	 { "DC_HPD3_CONNECT_AUX_TX_EN", 24, 24, &umr_bitfield_default },
	 { "DC_HPD3_CONNECT_FAST_TRAIN_DELAY", 12, 19, &umr_bitfield_default },
	 { "DC_HPD3_CONNECT_FAST_TRAIN_EN", 28, 28, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_HPD4_FAST_TRAIN_CNTL[] = {
	 { "DC_HPD4_CONNECT_AUX_TX_DELAY", 0, 7, &umr_bitfield_default },
	 { "DC_HPD4_CONNECT_AUX_TX_EN", 24, 24, &umr_bitfield_default },
	 { "DC_HPD4_CONNECT_FAST_TRAIN_DELAY", 12, 19, &umr_bitfield_default },
	 { "DC_HPD4_CONNECT_FAST_TRAIN_EN", 28, 28, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_HPD5_FAST_TRAIN_CNTL[] = {
	 { "DC_HPD5_CONNECT_AUX_TX_DELAY", 0, 7, &umr_bitfield_default },
	 { "DC_HPD5_CONNECT_AUX_TX_EN", 24, 24, &umr_bitfield_default },
	 { "DC_HPD5_CONNECT_FAST_TRAIN_DELAY", 12, 19, &umr_bitfield_default },
	 { "DC_HPD5_CONNECT_FAST_TRAIN_EN", 28, 28, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_HPD6_FAST_TRAIN_CNTL[] = {
	 { "DC_HPD6_CONNECT_AUX_TX_DELAY", 0, 7, &umr_bitfield_default },
	 { "DC_HPD6_CONNECT_AUX_TX_EN", 24, 24, &umr_bitfield_default },
	 { "DC_HPD6_CONNECT_FAST_TRAIN_DELAY", 12, 19, &umr_bitfield_default },
	 { "DC_HPD6_CONNECT_FAST_TRAIN_EN", 28, 28, &umr_bitfield_default },
};
static struct umr_bitfield mmDCDEBUG_OUT_PIN_OVERRIDE[] = {
	 { "DCDEBUG_OUT_OVERRIDE1_EN", 12, 12, &umr_bitfield_default },
	 { "DCDEBUG_OUT_OVERRIDE1_PIN_SEL", 0, 3, &umr_bitfield_default },
	 { "DCDEBUG_OUT_OVERRIDE1_REGBIT_SEL", 4, 8, &umr_bitfield_default },
	 { "DCDEBUG_OUT_OVERRIDE2_EN", 28, 28, &umr_bitfield_default },
	 { "DCDEBUG_OUT_OVERRIDE2_PIN_SEL", 16, 19, &umr_bitfield_default },
	 { "DCDEBUG_OUT_OVERRIDE2_REGBIT_SEL", 20, 24, &umr_bitfield_default },
};
static struct umr_bitfield mmDCDEBUG_OUT_CNTL[] = {
	 { "DCDEBUG_BLOCK_SEL", 0, 4, &umr_bitfield_default },
	 { "DCDEBUG_OUT_EN", 5, 5, &umr_bitfield_default },
	 { "DCDEBUG_OUT_PIN_SEL", 6, 6, &umr_bitfield_default },
	 { "DCDEBUG_OUT_SEL", 20, 21, &umr_bitfield_default },
	 { "DCDEBUG_OUT_TEST_DATA_EN", 7, 7, &umr_bitfield_default },
	 { "DCDEBUG_OUT_TEST_DATA", 8, 19, &umr_bitfield_default },
};
static struct umr_bitfield mmDCDEBUG_OUT_DATA[] = {
	 { "DCDEBUG_OUT_DATA", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_I2C_EDID_DETECT_CTRL[] = {
	 { "DC_I2C_EDID_DETECT_NUM_TRIES_UNTIL_VALID", 20, 23, &umr_bitfield_default },
	 { "DC_I2C_EDID_DETECT_SEND_RESET", 28, 28, &umr_bitfield_default },
	 { "DC_I2C_EDID_DETECT_WAIT_TIME", 0, 15, &umr_bitfield_default },
};
static struct umr_bitfield mmAUX_CONTROL[] = {
	 { "AUX_DEGLITCH_EN", 29, 29, &umr_bitfield_default },
	 { "AUX_EN", 0, 0, &umr_bitfield_default },
	 { "AUX_HPD_SEL", 20, 22, &umr_bitfield_default },
	 { "AUX_IGNORE_HPD_DISCON", 16, 16, &umr_bitfield_default },
	 { "AUX_IMPCAL_REQ_EN", 24, 24, &umr_bitfield_default },
	 { "AUX_LS_READ_EN", 8, 8, &umr_bitfield_default },
	 { "AUX_LS_UPDATE_DISABLE", 12, 12, &umr_bitfield_default },
	 { "AUX_MODE_DET_EN", 18, 18, &umr_bitfield_default },
	 { "AUX_TEST_MODE", 28, 28, &umr_bitfield_default },
	 { "SPARE_0", 30, 30, &umr_bitfield_default },
	 { "SPARE_1", 31, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmAUX_SW_CONTROL[] = {
	 { "AUX_LS_READ_TRIG", 2, 2, &umr_bitfield_default },
	 { "AUX_SW_GO", 0, 0, &umr_bitfield_default },
	 { "AUX_SW_START_DELAY", 4, 7, &umr_bitfield_default },
	 { "AUX_SW_WR_BYTES", 16, 20, &umr_bitfield_default },
};
static struct umr_bitfield mmAUX_ARB_CONTROL[] = {
	 { "AUX_ARB_PRIORITY", 0, 1, &umr_bitfield_default },
	 { "AUX_DMCU_DONE_USING_AUX_REG", 25, 25, &umr_bitfield_default },
	 { "AUX_DMCU_PENDING_USE_AUX_REG_REQ", 24, 24, &umr_bitfield_default },
	 { "AUX_DMCU_USE_AUX_REG_REQ", 24, 24, &umr_bitfield_default },
	 { "AUX_NO_QUEUED_LS_GO", 10, 10, &umr_bitfield_default },
	 { "AUX_NO_QUEUED_SW_GO", 8, 8, &umr_bitfield_default },
	 { "AUX_REG_RW_CNTL_STATUS", 2, 3, &umr_bitfield_default },
	 { "AUX_SW_DONE_USING_AUX_REG", 17, 17, &umr_bitfield_default },
	 { "AUX_SW_PENDING_USE_AUX_REG_REQ", 16, 16, &umr_bitfield_default },
	 { "AUX_SW_USE_AUX_REG_REQ", 16, 16, &umr_bitfield_default },
};
static struct umr_bitfield mmAUX_INTERRUPT_CONTROL[] = {
	 { "AUX_LS_DONE_ACK", 5, 5, &umr_bitfield_default },
	 { "AUX_LS_DONE_INT", 4, 4, &umr_bitfield_default },
	 { "AUX_LS_DONE_MASK", 6, 6, &umr_bitfield_default },
	 { "AUX_SW_DONE_ACK", 1, 1, &umr_bitfield_default },
	 { "AUX_SW_DONE_INT", 0, 0, &umr_bitfield_default },
	 { "AUX_SW_DONE_MASK", 2, 2, &umr_bitfield_default },
};
static struct umr_bitfield mmAUX_SW_STATUS[] = {
	 { "AUX_ARB_STATUS", 30, 31, &umr_bitfield_default },
	 { "AUX_SW_DONE", 0, 0, &umr_bitfield_default },
	 { "AUX_SW_HPD_DISCON", 9, 9, &umr_bitfield_default },
	 { "AUX_SW_NON_AUX_MODE", 11, 11, &umr_bitfield_default },
	 { "AUX_SW_REPLY_BYTE_COUNT", 24, 28, &umr_bitfield_default },
	 { "AUX_SW_REQ", 1, 1, &umr_bitfield_default },
	 { "AUX_SW_RX_INVALID_START", 19, 19, &umr_bitfield_default },
	 { "AUX_SW_RX_INVALID_STOP", 14, 14, &umr_bitfield_default },
	 { "AUX_SW_RX_MIN_COUNT_VIOL", 12, 12, &umr_bitfield_default },
	 { "AUX_SW_RX_OVERFLOW", 8, 8, &umr_bitfield_default },
	 { "AUX_SW_RX_PARTIAL_BYTE", 10, 10, &umr_bitfield_default },
	 { "AUX_SW_RX_RECV_INVALID_H", 22, 22, &umr_bitfield_default },
	 { "AUX_SW_RX_RECV_INVALID_L", 23, 23, &umr_bitfield_default },
	 { "AUX_SW_RX_RECV_NO_DET", 20, 20, &umr_bitfield_default },
	 { "AUX_SW_RX_SYNC_INVALID_H", 18, 18, &umr_bitfield_default },
	 { "AUX_SW_RX_SYNC_INVALID_L", 17, 17, &umr_bitfield_default },
	 { "AUX_SW_RX_TIMEOUT", 7, 7, &umr_bitfield_default },
	 { "AUX_SW_RX_TIMEOUT_STATE", 4, 6, &umr_bitfield_default },
};
static struct umr_bitfield mmAUX_LS_STATUS[] = {
	 { "AUX_LS_CP_IRQ", 29, 29, &umr_bitfield_default },
	 { "AUX_LS_DONE", 0, 0, &umr_bitfield_default },
	 { "AUX_LS_HPD_DISCON", 9, 9, &umr_bitfield_default },
	 { "AUX_LS_NON_AUX_MODE", 11, 11, &umr_bitfield_default },
	 { "AUX_LS_REPLY_BYTE_COUNT", 24, 28, &umr_bitfield_default },
	 { "AUX_LS_REQ", 1, 1, &umr_bitfield_default },
	 { "AUX_LS_RX_INVALID_START", 19, 19, &umr_bitfield_default },
	 { "AUX_LS_RX_INVALID_STOP", 14, 14, &umr_bitfield_default },
	 { "AUX_LS_RX_MIN_COUNT_VIOL", 12, 12, &umr_bitfield_default },
	 { "AUX_LS_RX_OVERFLOW", 8, 8, &umr_bitfield_default },
	 { "AUX_LS_RX_PARTIAL_BYTE", 10, 10, &umr_bitfield_default },
	 { "AUX_LS_RX_RECV_INVALID_H", 22, 22, &umr_bitfield_default },
	 { "AUX_LS_RX_RECV_INVALID_L", 23, 23, &umr_bitfield_default },
	 { "AUX_LS_RX_RECV_NO_DET", 20, 20, &umr_bitfield_default },
	 { "AUX_LS_RX_SYNC_INVALID_H", 18, 18, &umr_bitfield_default },
	 { "AUX_LS_RX_SYNC_INVALID_L", 17, 17, &umr_bitfield_default },
	 { "AUX_LS_RX_TIMEOUT", 7, 7, &umr_bitfield_default },
	 { "AUX_LS_RX_TIMEOUT_STATE", 4, 6, &umr_bitfield_default },
	 { "AUX_LS_UPDATED_ACK", 31, 31, &umr_bitfield_default },
	 { "AUX_LS_UPDATED", 30, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmAUX_SW_DATA[] = {
	 { "AUX_SW_AUTOINCREMENT_DISABLE", 31, 31, &umr_bitfield_default },
	 { "AUX_SW_DATA", 8, 15, &umr_bitfield_default },
	 { "AUX_SW_DATA_RW", 0, 0, &umr_bitfield_default },
	 { "AUX_SW_INDEX", 16, 20, &umr_bitfield_default },
};
static struct umr_bitfield mmAUX_LS_DATA[] = {
	 { "AUX_LS_DATA", 8, 15, &umr_bitfield_default },
	 { "AUX_LS_INDEX", 16, 20, &umr_bitfield_default },
};
static struct umr_bitfield mmAUX_DPHY_TX_REF_CONTROL[] = {
	 { "AUX_TX_RATE", 4, 5, &umr_bitfield_default },
	 { "AUX_TX_REF_DIV", 16, 24, &umr_bitfield_default },
	 { "AUX_TX_REF_SEL", 0, 0, &umr_bitfield_default },
};
static struct umr_bitfield mmAUX_DPHY_TX_CONTROL[] = {
	 { "AUX_TX_PRECHARGE_LEN", 0, 2, &umr_bitfield_default },
	 { "AUX_TX_PRECHARGE_SYMBOLS", 8, 13, &umr_bitfield_default },
};
static struct umr_bitfield mmAUX_DPHY_RX_CONTROL0[] = {
	 { "AUX_RX_ALLOW_BELOW_THRESHOLD_PHASE_DETECT", 17, 17, &umr_bitfield_default },
	 { "AUX_RX_ALLOW_BELOW_THRESHOLD_START", 18, 18, &umr_bitfield_default },
	 { "AUX_RX_ALLOW_BELOW_THRESHOLD_STOP", 19, 19, &umr_bitfield_default },
	 { "AUX_RX_DETECTION_THRESHOLD", 28, 30, &umr_bitfield_default },
	 { "AUX_RX_HALF_SYM_DETECT_LEN", 12, 13, &umr_bitfield_default },
	 { "AUX_RX_PHASE_DETECT_LEN", 20, 21, &umr_bitfield_default },
	 { "AUX_RX_RECEIVE_WINDOW", 8, 10, &umr_bitfield_default },
	 { "AUX_RX_START_WINDOW", 4, 6, &umr_bitfield_default },
	 { "AUX_RX_TIMEOUT_LEN", 24, 26, &umr_bitfield_default },
	 { "AUX_RX_TRANSITION_FILTER_EN", 16, 16, &umr_bitfield_default },
};
static struct umr_bitfield mmAUX_DPHY_RX_CONTROL1[] = {
	 { "AUX_RX_PRECHARGE_SKIP", 0, 7, &umr_bitfield_default },
};
static struct umr_bitfield mmAUX_DPHY_TX_STATUS[] = {
	 { "AUX_TX_ACTIVE", 0, 0, &umr_bitfield_default },
	 { "AUX_TX_HALF_SYM_PERIOD", 16, 24, &umr_bitfield_default },
	 { "AUX_TX_STATE", 4, 6, &umr_bitfield_default },
};
static struct umr_bitfield mmAUX_DPHY_RX_STATUS[] = {
	 { "AUX_RX_HALF_SYM_PERIOD_FRACT", 16, 20, &umr_bitfield_default },
	 { "AUX_RX_HALF_SYM_PERIOD", 21, 29, &umr_bitfield_default },
	 { "AUX_RX_STATE", 0, 2, &umr_bitfield_default },
	 { "AUX_RX_SYNC_VALID_COUNT", 8, 12, &umr_bitfield_default },
};
static struct umr_bitfield mmAUX_GTC_SYNC_CONTROL[] = {
	 { "AUX_GTC_SYNC_EN", 0, 0, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_HPD1_TOGGLE_FILT_CNTL[] = {
	 { "DC_HPD1_CONNECT_INT_DELAY", 0, 7, &umr_bitfield_default },
	 { "DC_HPD1_DISCONNECT_INT_DELAY", 20, 27, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_HPD2_TOGGLE_FILT_CNTL[] = {
	 { "DC_HPD2_CONNECT_INT_DELAY", 0, 7, &umr_bitfield_default },
	 { "DC_HPD2_DISCONNECT_INT_DELAY", 20, 27, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_HPD3_TOGGLE_FILT_CNTL[] = {
	 { "DC_HPD3_CONNECT_INT_DELAY", 0, 7, &umr_bitfield_default },
	 { "DC_HPD3_DISCONNECT_INT_DELAY", 20, 27, &umr_bitfield_default },
};
static struct umr_bitfield mmDISPOUT_STEREOSYNC_SEL[] = {
	 { "GENERICA_STEREOSYNC_SEL", 0, 2, &umr_bitfield_default },
	 { "GENERICB_STEREOSYNC_SEL", 16, 18, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_HPD4_TOGGLE_FILT_CNTL[] = {
	 { "DC_HPD4_CONNECT_INT_DELAY", 0, 7, &umr_bitfield_default },
	 { "DC_HPD4_DISCONNECT_INT_DELAY", 20, 27, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_HPD5_TOGGLE_FILT_CNTL[] = {
	 { "DC_HPD5_CONNECT_INT_DELAY", 0, 7, &umr_bitfield_default },
	 { "DC_HPD5_DISCONNECT_INT_DELAY", 20, 27, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_HPD6_TOGGLE_FILT_CNTL[] = {
	 { "DC_HPD6_CONNECT_INT_DELAY", 0, 7, &umr_bitfield_default },
	 { "DC_HPD6_DISCONNECT_INT_DELAY", 20, 27, &umr_bitfield_default },
};
static struct umr_bitfield mmDOUT_DCE_VCE_CONTROL[] = {
	 { "DC_VCE_AUDIO_STREAM_SELECT", 4, 6, &umr_bitfield_default },
	 { "DC_VCE_VIDEO_PIPE_SELECT", 0, 2, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_GENERICA[] = {
	 { "GENERICA_EN", 0, 0, &umr_bitfield_default },
	 { "GENERICA_SEL", 8, 11, &umr_bitfield_default },
	 { "GENERICA_UNIPHY_FBDIV_CLK_DIV2_SEL", 24, 26, &umr_bitfield_default },
	 { "GENERICA_UNIPHY_FBDIV_CLK_SEL", 16, 18, &umr_bitfield_default },
	 { "GENERICA_UNIPHY_FBDIV_SSC_CLK_SEL", 20, 22, &umr_bitfield_default },
	 { "GENERICA_UNIPHY_REFDIV_CLK_SEL", 12, 14, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_GENERICB[] = {
	 { "GENERICB_EN", 0, 0, &umr_bitfield_default },
	 { "GENERICB_SEL", 8, 11, &umr_bitfield_default },
	 { "GENERICB_UNIPHY_FBDIV_CLK_DIV2_SEL", 24, 26, &umr_bitfield_default },
	 { "GENERICB_UNIPHY_FBDIV_CLK_SEL", 16, 18, &umr_bitfield_default },
	 { "GENERICB_UNIPHY_FBDIV_SSC_CLK_SEL", 20, 22, &umr_bitfield_default },
	 { "GENERICB_UNIPHY_REFDIV_CLK_SEL", 12, 14, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_PAD_EXTERN_SIG[] = {
	 { "DC_PAD_EXTERN_SIG_SEL", 0, 3, &umr_bitfield_default },
	 { "MVP_PIXEL_SRC_STATUS", 4, 5, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_REF_CLK_CNTL[] = {
	 { "GENLK_CLK_OUTPUT_SEL", 8, 9, &umr_bitfield_default },
	 { "HSYNCA_OUTPUT_SEL", 0, 1, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_GPIO_DEBUG[] = {
	 { "DC_GPIO_CHIP_DEBUG_OUT_PIN_SEL", 16, 16, &umr_bitfield_default },
	 { "DC_GPIO_MACRO_DEBUG", 8, 9, &umr_bitfield_default },
	 { "DC_GPIO_VIP_DEBUG", 0, 0, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_DVODATA_CONFIG[] = {
	 { "DVO_ALTER_MAPPING_EN", 21, 21, &umr_bitfield_default },
	 { "VIP_ALTER_MAPPING_EN", 20, 20, &umr_bitfield_default },
	 { "VIP_MUX_EN", 19, 19, &umr_bitfield_default },
};
static struct umr_bitfield mmDCO_MEM_POWER_STATE[] = {
	 { "DPA_MEM_PWR_STATE", 6, 7, &umr_bitfield_default },
	 { "DPB_MEM_PWR_STATE", 8, 9, &umr_bitfield_default },
	 { "DPC_MEM_PWR_STATE", 10, 11, &umr_bitfield_default },
	 { "DPD_MEM_PWR_STATE", 12, 13, &umr_bitfield_default },
	 { "DPE_MEM_PWR_STATE", 14, 15, &umr_bitfield_default },
	 { "DPF_MEM_PWR_STATE", 16, 17, &umr_bitfield_default },
	 { "HDMI0_MEM_PWR_STATE", 18, 19, &umr_bitfield_default },
	 { "HDMI1_MEM_PWR_STATE", 20, 21, &umr_bitfield_default },
	 { "HDMI2_MEM_PWR_STATE", 22, 23, &umr_bitfield_default },
	 { "HDMI3_MEM_PWR_STATE", 24, 25, &umr_bitfield_default },
	 { "HDMI4_MEM_PWR_STATE", 26, 27, &umr_bitfield_default },
	 { "HDMI5_MEM_PWR_STATE", 28, 29, &umr_bitfield_default },
	 { "I2C_MEM_PWR_STATE", 2, 3, &umr_bitfield_default },
	 { "MVP_MEM_PWR_STATE", 4, 5, &umr_bitfield_default },
	 { "TVOUT_MEM_PWR_STATE", 0, 1, &umr_bitfield_default },
};
static struct umr_bitfield mmDCO_LIGHT_SLEEP_DIS[] = {
	 { "DPA_LIGHT_SLEEP_DIS", 3, 3, &umr_bitfield_default },
	 { "DPA_MEM_SHUTDOWN_DIS", 17, 17, &umr_bitfield_default },
	 { "DPB_LIGHT_SLEEP_DIS", 4, 4, &umr_bitfield_default },
	 { "DPB_MEM_SHUTDOWN_DIS", 18, 18, &umr_bitfield_default },
	 { "DPC_LIGHT_SLEEP_DIS", 5, 5, &umr_bitfield_default },
	 { "DPC_MEM_SHUTDOWN_DIS", 19, 19, &umr_bitfield_default },
	 { "DPD_LIGHT_SLEEP_DIS", 6, 6, &umr_bitfield_default },
	 { "DPD_MEM_SHUTDOWN_DIS", 20, 20, &umr_bitfield_default },
	 { "DPE_LIGHT_SLEEP_DIS", 7, 7, &umr_bitfield_default },
	 { "DPE_MEM_SHUTDOWN_DIS", 21, 21, &umr_bitfield_default },
	 { "DPF_LIGHT_SLEEP_DIS", 8, 8, &umr_bitfield_default },
	 { "DPF_MEM_SHUTDOWN_DIS", 22, 22, &umr_bitfield_default },
	 { "HDMI0_LIGHT_SLEEP_DIS", 9, 9, &umr_bitfield_default },
	 { "HDMI1_LIGHT_SLEEP_DIS", 10, 10, &umr_bitfield_default },
	 { "HDMI2_LIGHT_SLEEP_DIS", 11, 11, &umr_bitfield_default },
	 { "HDMI3_LIGHT_SLEEP_DIS", 12, 12, &umr_bitfield_default },
	 { "HDMI4_LIGHT_SLEEP_DIS", 13, 13, &umr_bitfield_default },
	 { "HDMI5_LIGHT_SLEEP_DIS", 14, 14, &umr_bitfield_default },
	 { "I2C_LIGHT_SLEEP_FORCE", 1, 1, &umr_bitfield_default },
	 { "MVP_LIGHT_SLEEP_DIS", 2, 2, &umr_bitfield_default },
	 { "MVP_MEM_SHUTDOWN_DIS", 16, 16, &umr_bitfield_default },
	 { "TVOUT_LIGHT_SLEEP_DIS", 0, 0, &umr_bitfield_default },
};
static struct umr_bitfield mmUNIPHY_IMPCAL_LINKA[] = {
	 { "UNIPHY_CALOUT_ERROR_LINKA_AK", 10, 10, &umr_bitfield_default },
	 { "UNIPHY_CALOUT_ERROR_LINKA", 9, 9, &umr_bitfield_default },
	 { "UNIPHY_IMPCAL_CALOUT_LINKA", 8, 8, &umr_bitfield_default },
	 { "UNIPHY_IMPCAL_ENABLE_LINKA", 0, 0, &umr_bitfield_default },
	 { "UNIPHY_IMPCAL_OVERRIDE_ENABLE_LINKA", 28, 28, &umr_bitfield_default },
	 { "UNIPHY_IMPCAL_OVERRIDE_LINKA", 24, 27, &umr_bitfield_default },
	 { "UNIPHY_IMPCAL_SEL_LINKA", 30, 30, &umr_bitfield_default },
	 { "UNIPHY_IMPCAL_STEP_DELAY_LINKA", 20, 23, &umr_bitfield_default },
	 { "UNIPHY_IMPCAL_VALUE_LINKA", 16, 19, &umr_bitfield_default },
};
static struct umr_bitfield mmUNIPHY_IMPCAL_LINKB[] = {
	 { "UNIPHY_CALOUT_ERROR_LINKB_AK", 10, 10, &umr_bitfield_default },
	 { "UNIPHY_CALOUT_ERROR_LINKB", 9, 9, &umr_bitfield_default },
	 { "UNIPHY_IMPCAL_CALOUT_LINKB", 8, 8, &umr_bitfield_default },
	 { "UNIPHY_IMPCAL_ENABLE_LINKB", 0, 0, &umr_bitfield_default },
	 { "UNIPHY_IMPCAL_OVERRIDE_ENABLE_LINKB", 28, 28, &umr_bitfield_default },
	 { "UNIPHY_IMPCAL_OVERRIDE_LINKB", 24, 27, &umr_bitfield_default },
	 { "UNIPHY_IMPCAL_SEL_LINKB", 30, 30, &umr_bitfield_default },
	 { "UNIPHY_IMPCAL_STEP_DELAY_LINKB", 20, 23, &umr_bitfield_default },
	 { "UNIPHY_IMPCAL_VALUE_LINKB", 16, 19, &umr_bitfield_default },
};
static struct umr_bitfield mmUNIPHY_IMPCAL_PERIOD[] = {
	 { "UNIPHY_IMPCAL_PERIOD", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmAUXP_IMPCAL[] = {
	 { "AUXP_CALOUT_ERROR_AK", 10, 10, &umr_bitfield_default },
	 { "AUXP_CALOUT_ERROR", 9, 9, &umr_bitfield_default },
	 { "AUXP_IMPCAL_CALOUT", 8, 8, &umr_bitfield_default },
	 { "AUXP_IMPCAL_ENABLE", 0, 0, &umr_bitfield_default },
	 { "AUXP_IMPCAL_OVERRIDE_ENABLE", 28, 28, &umr_bitfield_default },
	 { "AUXP_IMPCAL_OVERRIDE", 24, 27, &umr_bitfield_default },
	 { "AUXP_IMPCAL_STEP_DELAY", 20, 23, &umr_bitfield_default },
	 { "AUXP_IMPCAL_VALUE", 16, 19, &umr_bitfield_default },
};
static struct umr_bitfield mmAUXN_IMPCAL[] = {
	 { "AUXN_CALOUT_ERROR_AK", 10, 10, &umr_bitfield_default },
	 { "AUXN_CALOUT_ERROR", 9, 9, &umr_bitfield_default },
	 { "AUXN_IMPCAL_CALOUT", 8, 8, &umr_bitfield_default },
	 { "AUXN_IMPCAL_ENABLE", 0, 0, &umr_bitfield_default },
	 { "AUXN_IMPCAL_OVERRIDE_ENABLE", 28, 28, &umr_bitfield_default },
	 { "AUXN_IMPCAL_OVERRIDE", 24, 27, &umr_bitfield_default },
	 { "AUXN_IMPCAL_STEP_DELAY", 20, 23, &umr_bitfield_default },
	 { "AUXN_IMPCAL_VALUE", 16, 19, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_IMPCAL_CNTL_AB[] = {
	 { "CALR_CNTL_OVERRIDE", 0, 3, &umr_bitfield_default },
	 { "IMPCAL_ARB_STATE", 12, 14, &umr_bitfield_default },
	 { "IMPCAL_SOFT_RESET", 5, 5, &umr_bitfield_default },
	 { "IMPCAL_STATUS", 8, 9, &umr_bitfield_default },
};
static struct umr_bitfield mmUNIPHY_IMPCAL_PSW_AB[] = {
	 { "UNIPHY_IMPCAL_PSW_LINKA", 0, 14, &umr_bitfield_default },
	 { "UNIPHY_IMPCAL_PSW_LINKB", 16, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmUNIPHY_IMPCAL_LINKC[] = {
	 { "UNIPHY_CALOUT_ERROR_LINKC_AK", 10, 10, &umr_bitfield_default },
	 { "UNIPHY_CALOUT_ERROR_LINKC", 9, 9, &umr_bitfield_default },
	 { "UNIPHY_IMPCAL_CALOUT_LINKC", 8, 8, &umr_bitfield_default },
	 { "UNIPHY_IMPCAL_ENABLE_LINKC", 0, 0, &umr_bitfield_default },
	 { "UNIPHY_IMPCAL_OVERRIDE_ENABLE_LINKC", 28, 28, &umr_bitfield_default },
	 { "UNIPHY_IMPCAL_OVERRIDE_LINKC", 24, 27, &umr_bitfield_default },
	 { "UNIPHY_IMPCAL_SEL_LINKC", 30, 30, &umr_bitfield_default },
	 { "UNIPHY_IMPCAL_STEP_DELAY_LINKC", 20, 23, &umr_bitfield_default },
	 { "UNIPHY_IMPCAL_VALUE_LINKC", 16, 19, &umr_bitfield_default },
};
static struct umr_bitfield mmUNIPHY_IMPCAL_LINKD[] = {
	 { "UNIPHY_CALOUT_ERROR_LINKD_AK", 10, 10, &umr_bitfield_default },
	 { "UNIPHY_CALOUT_ERROR_LINKD", 9, 9, &umr_bitfield_default },
	 { "UNIPHY_IMPCAL_CALOUT_LINKD", 8, 8, &umr_bitfield_default },
	 { "UNIPHY_IMPCAL_ENABLE_LINKD", 0, 0, &umr_bitfield_default },
	 { "UNIPHY_IMPCAL_OVERRIDE_ENABLE_LINKD", 28, 28, &umr_bitfield_default },
	 { "UNIPHY_IMPCAL_OVERRIDE_LINKD", 24, 27, &umr_bitfield_default },
	 { "UNIPHY_IMPCAL_SEL_LINKD", 30, 30, &umr_bitfield_default },
	 { "UNIPHY_IMPCAL_STEP_DELAY_LINKD", 20, 23, &umr_bitfield_default },
	 { "UNIPHY_IMPCAL_VALUE_LINKD", 16, 19, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_IMPCAL_CNTL_CD[] = {
	 { "CALR_CNTL_OVERRIDE", 0, 3, &umr_bitfield_default },
	 { "IMPCAL_ARB_STATE", 12, 14, &umr_bitfield_default },
	 { "IMPCAL_SOFT_RESET", 5, 5, &umr_bitfield_default },
	 { "IMPCAL_STATUS", 8, 9, &umr_bitfield_default },
};
static struct umr_bitfield mmUNIPHY_IMPCAL_PSW_CD[] = {
	 { "UNIPHY_IMPCAL_PSW_LINKC", 0, 14, &umr_bitfield_default },
	 { "UNIPHY_IMPCAL_PSW_LINKD", 16, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmUNIPHY_IMPCAL_LINKE[] = {
	 { "UNIPHY_CALOUT_ERROR_LINKE_AK", 10, 10, &umr_bitfield_default },
	 { "UNIPHY_CALOUT_ERROR_LINKE", 9, 9, &umr_bitfield_default },
	 { "UNIPHY_IMPCAL_CALOUT_LINKE", 8, 8, &umr_bitfield_default },
	 { "UNIPHY_IMPCAL_ENABLE_LINKE", 0, 0, &umr_bitfield_default },
	 { "UNIPHY_IMPCAL_OVERRIDE_ENABLE_LINKE", 28, 28, &umr_bitfield_default },
	 { "UNIPHY_IMPCAL_OVERRIDE_LINKE", 24, 27, &umr_bitfield_default },
	 { "UNIPHY_IMPCAL_SEL_LINKE", 30, 30, &umr_bitfield_default },
	 { "UNIPHY_IMPCAL_STEP_DELAY_LINKE", 20, 23, &umr_bitfield_default },
	 { "UNIPHY_IMPCAL_VALUE_LINKE", 16, 19, &umr_bitfield_default },
};
static struct umr_bitfield mmUNIPHY_IMPCAL_LINKF[] = {
	 { "UNIPHY_CALOUT_ERROR_LINKF_AK", 10, 10, &umr_bitfield_default },
	 { "UNIPHY_CALOUT_ERROR_LINKF", 9, 9, &umr_bitfield_default },
	 { "UNIPHY_IMPCAL_CALOUT_LINKF", 8, 8, &umr_bitfield_default },
	 { "UNIPHY_IMPCAL_ENABLE_LINKF", 0, 0, &umr_bitfield_default },
	 { "UNIPHY_IMPCAL_OVERRIDE_ENABLE_LINKF", 28, 28, &umr_bitfield_default },
	 { "UNIPHY_IMPCAL_OVERRIDE_LINKF", 24, 27, &umr_bitfield_default },
	 { "UNIPHY_IMPCAL_SEL_LINKF", 30, 30, &umr_bitfield_default },
	 { "UNIPHY_IMPCAL_STEP_DELAY_LINKF", 20, 23, &umr_bitfield_default },
	 { "UNIPHY_IMPCAL_VALUE_LINKF", 16, 19, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_IMPCAL_CNTL_EF[] = {
	 { "CALR_CNTL_OVERRIDE", 0, 3, &umr_bitfield_default },
	 { "IMPCAL_ARB_STATE", 12, 14, &umr_bitfield_default },
	 { "IMPCAL_SOFT_RESET", 5, 5, &umr_bitfield_default },
	 { "IMPCAL_STATUS", 8, 9, &umr_bitfield_default },
};
static struct umr_bitfield mmUNIPHY_IMPCAL_PSW_EF[] = {
	 { "UNIPHY_IMPCAL_PSW_LINKE", 0, 14, &umr_bitfield_default },
	 { "UNIPHY_IMPCAL_PSW_LINKF", 16, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_PINSTRAPS[] = {
	 { "DC_PINSTRAPS_AUDIO", 14, 15, &umr_bitfield_default },
	 { "DC_PINSTRAPS_BIF_CEC_DIS", 10, 10, &umr_bitfield_default },
	 { "DC_PINSTRAPS_CCBYPASS", 16, 16, &umr_bitfield_default },
	 { "DC_PINSTRAPS_SMS_EN_HARD", 13, 13, &umr_bitfield_default },
	 { "DC_PINSTRAPS_VIP_DEVICE", 11, 11, &umr_bitfield_default },
};
static struct umr_bitfield mmLVTMA_PWRSEQ_CNTL[] = {
	 { "LVTMA_BLON", 24, 24, &umr_bitfield_default },
	 { "LVTMA_BLON_OVRD", 25, 25, &umr_bitfield_default },
	 { "LVTMA_BLON_POL", 26, 26, &umr_bitfield_default },
	 { "LVTMA_DIGON", 16, 16, &umr_bitfield_default },
	 { "LVTMA_DIGON_OVRD", 17, 17, &umr_bitfield_default },
	 { "LVTMA_DIGON_POL", 18, 18, &umr_bitfield_default },
	 { "LVTMA_PWRSEQ_DISABLE_SYNCEN_CONTROL_OF_TX_EN", 1, 1, &umr_bitfield_default },
	 { "LVTMA_PWRSEQ_EN", 0, 0, &umr_bitfield_default },
	 { "LVTMA_PWRSEQ_TARGET_STATE", 4, 4, &umr_bitfield_default },
	 { "LVTMA_SYNCEN", 8, 8, &umr_bitfield_default },
	 { "LVTMA_SYNCEN_OVRD", 9, 9, &umr_bitfield_default },
	 { "LVTMA_SYNCEN_POL", 10, 10, &umr_bitfield_default },
};
static struct umr_bitfield mmLVTMA_PWRSEQ_STATE[] = {
	 { "LVTMA_PWRSEQ_BLON", 3, 3, &umr_bitfield_default },
	 { "LVTMA_PWRSEQ_DIGON", 1, 1, &umr_bitfield_default },
	 { "LVTMA_PWRSEQ_DONE", 4, 4, &umr_bitfield_default },
	 { "LVTMA_PWRSEQ_STATE", 8, 11, &umr_bitfield_default },
	 { "LVTMA_PWRSEQ_SYNCEN", 2, 2, &umr_bitfield_default },
	 { "LVTMA_PWRSEQ_TARGET_STATE_R", 0, 0, &umr_bitfield_default },
};
static struct umr_bitfield mmLVTMA_PWRSEQ_REF_DIV[] = {
	 { "BL_PWM_REF_DIV", 16, 31, &umr_bitfield_default },
	 { "LVTMA_PWRSEQ_REF_DIV", 0, 11, &umr_bitfield_default },
};
static struct umr_bitfield mmLVTMA_PWRSEQ_DELAY1[] = {
	 { "LVTMA_PWRDN_DELAY1", 16, 23, &umr_bitfield_default },
	 { "LVTMA_PWRDN_DELAY2", 24, 31, &umr_bitfield_default },
	 { "LVTMA_PWRUP_DELAY1", 0, 7, &umr_bitfield_default },
	 { "LVTMA_PWRUP_DELAY2", 8, 15, &umr_bitfield_default },
};
static struct umr_bitfield mmLVTMA_PWRSEQ_DELAY2[] = {
	 { "LVTMA_PWRDN_DELAY3", 16, 23, &umr_bitfield_default },
	 { "LVTMA_PWRDN_MIN_LENGTH", 0, 7, &umr_bitfield_default },
	 { "LVTMA_PWRUP_DELAY3", 8, 15, &umr_bitfield_default },
	 { "LVTMA_VARY_BL_OVERRIDE_EN", 24, 24, &umr_bitfield_default },
};
static struct umr_bitfield mmBL_PWM_CNTL[] = {
	 { "BL_ACTIVE_INT_FRAC_CNT", 0, 15, &umr_bitfield_default },
	 { "BL_PWM_EN", 31, 31, &umr_bitfield_default },
	 { "BL_PWM_FRACTIONAL_EN", 30, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmBL_PWM_CNTL2[] = {
	 { "BL_PWM_OVERRIDE_BL_OUT_ENABLE", 30, 30, &umr_bitfield_default },
	 { "BL_PWM_OVERRIDE_LVTMA_PWRSEQ_EN", 31, 31, &umr_bitfield_default },
	 { "BL_PWM_POST_FRAME_START_DELAY_BEFORE_UPDATE", 0, 15, &umr_bitfield_default },
	 { "DBG_BL_PWM_INPUT_REFCLK_SELECT", 28, 29, &umr_bitfield_default },
};
static struct umr_bitfield mmBL_PWM_PERIOD_CNTL[] = {
	 { "BL_PWM_PERIOD_BITCNT", 16, 19, &umr_bitfield_default },
	 { "BL_PWM_PERIOD", 0, 15, &umr_bitfield_default },
};
static struct umr_bitfield mmBL_PWM_GRP1_REG_LOCK[] = {
	 { "BL_PWM_GRP1_FRAME_START_DISP_SEL", 17, 19, &umr_bitfield_default },
	 { "BL_PWM_GRP1_IGNORE_MASTER_LOCK_EN", 31, 31, &umr_bitfield_default },
	 { "BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN", 24, 24, &umr_bitfield_default },
	 { "BL_PWM_GRP1_REG_LOCK", 0, 0, &umr_bitfield_default },
	 { "BL_PWM_GRP1_REG_UPDATE_PENDING", 8, 8, &umr_bitfield_default },
	 { "BL_PWM_GRP1_UPDATE_AT_FRAME_START", 16, 16, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_GSL_GENLK_PAD_CNTL[] = {
	 { "DCIO_GENLK_CLK_GSL_FLIP_LOCK_SEL", 4, 5, &umr_bitfield_default },
	 { "DCIO_GENLK_CLK_GSL_MASK", 8, 9, &umr_bitfield_default },
	 { "DCIO_GENLK_CLK_GSL_TIMING_SYNC_SEL", 0, 1, &umr_bitfield_default },
	 { "DCIO_GENLK_VSYNC_GSL_FLIP_LOCK_SEL", 20, 21, &umr_bitfield_default },
	 { "DCIO_GENLK_VSYNC_GSL_MASK", 24, 25, &umr_bitfield_default },
	 { "DCIO_GENLK_VSYNC_GSL_TIMING_SYNC_SEL", 16, 17, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_GSL_SWAPLOCK_PAD_CNTL[] = {
	 { "DCIO_SWAPLOCK_A_GSL_FLIP_LOCK_SEL", 4, 5, &umr_bitfield_default },
	 { "DCIO_SWAPLOCK_A_GSL_MASK", 8, 9, &umr_bitfield_default },
	 { "DCIO_SWAPLOCK_A_GSL_TIMING_SYNC_SEL", 0, 1, &umr_bitfield_default },
	 { "DCIO_SWAPLOCK_B_GSL_FLIP_LOCK_SEL", 20, 21, &umr_bitfield_default },
	 { "DCIO_SWAPLOCK_B_GSL_MASK", 24, 25, &umr_bitfield_default },
	 { "DCIO_SWAPLOCK_B_GSL_TIMING_SYNC_SEL", 16, 17, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_GSL0_CNTL[] = {
	 { "DCIO_GSL0_GLOBAL_UNLOCK_SEL", 16, 18, &umr_bitfield_default },
	 { "DCIO_GSL0_TIMING_SYNC_SEL", 8, 10, &umr_bitfield_default },
	 { "DCIO_GSL0_VSYNC_SEL", 0, 2, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_GSL1_CNTL[] = {
	 { "DCIO_GSL1_GLOBAL_UNLOCK_SEL", 16, 18, &umr_bitfield_default },
	 { "DCIO_GSL1_TIMING_SYNC_SEL", 8, 10, &umr_bitfield_default },
	 { "DCIO_GSL1_VSYNC_SEL", 0, 2, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_GSL2_CNTL[] = {
	 { "DCIO_GSL2_GLOBAL_UNLOCK_SEL", 16, 18, &umr_bitfield_default },
	 { "DCIO_GSL2_TIMING_SYNC_SEL", 8, 10, &umr_bitfield_default },
	 { "DCIO_GSL2_VSYNC_SEL", 0, 2, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_GPU_TIMER_START_POSITION_V_UPDATE[] = {
	 { "DC_GPU_TIMER_START_POSITION_D1_V_UPDATE", 0, 2, &umr_bitfield_default },
	 { "DC_GPU_TIMER_START_POSITION_D2_V_UPDATE", 4, 6, &umr_bitfield_default },
	 { "DC_GPU_TIMER_START_POSITION_D3_V_UPDATE", 8, 10, &umr_bitfield_default },
	 { "DC_GPU_TIMER_START_POSITION_D4_V_UPDATE", 12, 14, &umr_bitfield_default },
	 { "DC_GPU_TIMER_START_POSITION_D5_V_UPDATE", 16, 18, &umr_bitfield_default },
	 { "DC_GPU_TIMER_START_POSITION_D6_V_UPDATE", 20, 22, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_GPU_TIMER_START_POSITION_P_FLIP[] = {
	 { "DC_GPU_TIMER_START_POSITION_D1_P_FLIP", 0, 2, &umr_bitfield_default },
	 { "DC_GPU_TIMER_START_POSITION_D2_P_FLIP", 4, 6, &umr_bitfield_default },
	 { "DC_GPU_TIMER_START_POSITION_D3_P_FLIP", 8, 10, &umr_bitfield_default },
	 { "DC_GPU_TIMER_START_POSITION_D4_P_FLIP", 12, 14, &umr_bitfield_default },
	 { "DC_GPU_TIMER_START_POSITION_D5_P_FLIP", 16, 18, &umr_bitfield_default },
	 { "DC_GPU_TIMER_START_POSITION_D6_P_FLIP", 20, 22, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_GPU_TIMER_READ[] = {
	 { "DC_GPU_TIMER_READ", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_GPU_TIMER_READ_CNTL[] = {
	 { "DC_GPU_TIMER_READ_SELECT", 0, 5, &umr_bitfield_default },
	 { "DC_GPU_TIMER_START_POSITION_D1_VSYNC_NOM", 8, 10, &umr_bitfield_default },
	 { "DC_GPU_TIMER_START_POSITION_D2_VSYNC_NOM", 11, 13, &umr_bitfield_default },
	 { "DC_GPU_TIMER_START_POSITION_D3_VSYNC_NOM", 14, 16, &umr_bitfield_default },
	 { "DC_GPU_TIMER_START_POSITION_D4_VSYNC_NOM", 17, 19, &umr_bitfield_default },
	 { "DC_GPU_TIMER_START_POSITION_D5_VSYNC_NOM", 20, 22, &umr_bitfield_default },
	 { "DC_GPU_TIMER_START_POSITION_D6_VSYNC_NOM", 23, 25, &umr_bitfield_default },
};
static struct umr_bitfield mmDCO_CLK_CNTL[] = {
	 { "DCO_TEST_CLK_SEL", 0, 4, &umr_bitfield_default },
	 { "DISPCLK_G_ABM_GATE_DIS", 6, 6, &umr_bitfield_default },
	 { "DISPCLK_G_DACA_GATE_DIS", 8, 8, &umr_bitfield_default },
	 { "DISPCLK_G_DACB_GATE_DIS", 9, 9, &umr_bitfield_default },
	 { "DISPCLK_G_DIGA_GATE_DIS", 24, 24, &umr_bitfield_default },
	 { "DISPCLK_G_DIGB_GATE_DIS", 25, 25, &umr_bitfield_default },
	 { "DISPCLK_G_DIGC_GATE_DIS", 26, 26, &umr_bitfield_default },
	 { "DISPCLK_G_DIGD_GATE_DIS", 27, 27, &umr_bitfield_default },
	 { "DISPCLK_G_DIGE_GATE_DIS", 28, 28, &umr_bitfield_default },
	 { "DISPCLK_G_DIGF_GATE_DIS", 29, 29, &umr_bitfield_default },
	 { "DISPCLK_G_DVO_GATE_DIS", 7, 7, &umr_bitfield_default },
	 { "DISPCLK_G_FMT0_GATE_DIS", 16, 16, &umr_bitfield_default },
	 { "DISPCLK_G_FMT1_GATE_DIS", 17, 17, &umr_bitfield_default },
	 { "DISPCLK_G_FMT2_GATE_DIS", 18, 18, &umr_bitfield_default },
	 { "DISPCLK_G_FMT3_GATE_DIS", 19, 19, &umr_bitfield_default },
	 { "DISPCLK_G_FMT4_GATE_DIS", 20, 20, &umr_bitfield_default },
	 { "DISPCLK_G_FMT5_GATE_DIS", 21, 21, &umr_bitfield_default },
	 { "DISPCLK_R_ABM_GATE_DIS", 12, 12, &umr_bitfield_default },
	 { "DISPCLK_R_DCO_GATE_DIS", 5, 5, &umr_bitfield_default },
};
static struct umr_bitfield mmDCO_CLK_RAMP_CNTL[] = {
	 { "DISPCLK_G_ABM_RAMP_DIS", 6, 6, &umr_bitfield_default },
	 { "DISPCLK_G_DACA_RAMP_DIS", 8, 8, &umr_bitfield_default },
	 { "DISPCLK_G_DACB_RAMP_DIS", 9, 9, &umr_bitfield_default },
	 { "DISPCLK_G_DIGA_RAMP_DIS", 24, 24, &umr_bitfield_default },
	 { "DISPCLK_G_DIGB_RAMP_DIS", 25, 25, &umr_bitfield_default },
	 { "DISPCLK_G_DIGC_RAMP_DIS", 26, 26, &umr_bitfield_default },
	 { "DISPCLK_G_DIGD_RAMP_DIS", 27, 27, &umr_bitfield_default },
	 { "DISPCLK_G_DIGE_RAMP_DIS", 28, 28, &umr_bitfield_default },
	 { "DISPCLK_G_DIGF_RAMP_DIS", 29, 29, &umr_bitfield_default },
	 { "DISPCLK_G_DVO_RAMP_DIS", 7, 7, &umr_bitfield_default },
	 { "DISPCLK_G_FMT0_RAMP_DIS", 16, 16, &umr_bitfield_default },
	 { "DISPCLK_G_FMT1_RAMP_DIS", 17, 17, &umr_bitfield_default },
	 { "DISPCLK_G_FMT2_RAMP_DIS", 18, 18, &umr_bitfield_default },
	 { "DISPCLK_G_FMT3_RAMP_DIS", 19, 19, &umr_bitfield_default },
	 { "DISPCLK_G_FMT4_RAMP_DIS", 20, 20, &umr_bitfield_default },
	 { "DISPCLK_G_FMT5_RAMP_DIS", 21, 21, &umr_bitfield_default },
	 { "DISPCLK_R_ABM_RAMP_DIS", 12, 12, &umr_bitfield_default },
	 { "DISPCLK_R_DCO_RAMP_DIS", 5, 5, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_DEBUG[] = {
	 { "DCIO_DEBUG", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_TEST_DEBUG_INDEX[] = {
	 { "DCIO_TEST_DEBUG_INDEX", 0, 7, &umr_bitfield_default },
	 { "DCIO_TEST_DEBUG_WRITE_EN", 8, 8, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_TEST_DEBUG_DATA[] = {
	 { "DCIO_TEST_DEBUG_DATA", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmUNIPHYAB_TPG_CONTROL[] = {
	 { "UNIPHYAB_STATIC_TEST_PATTERN", 0, 9, &umr_bitfield_default },
	 { "UNIPHYAB_TPG_EN", 16, 16, &umr_bitfield_default },
	 { "UNIPHYAB_TPG_SEL", 17, 19, &umr_bitfield_default },
};
static struct umr_bitfield mmUNIPHYAB_TPG_SEED[] = {
	 { "UNIPHYAB_TPG_SEED", 0, 22, &umr_bitfield_default },
};
static struct umr_bitfield mmUNIPHYCD_TPG_CONTROL[] = {
	 { "UNIPHYCD_STATIC_TEST_PATTERN", 0, 9, &umr_bitfield_default },
	 { "UNIPHYCD_TPG_EN", 16, 16, &umr_bitfield_default },
	 { "UNIPHYCD_TPG_SEL", 17, 19, &umr_bitfield_default },
};
static struct umr_bitfield mmUNIPHYCD_TPG_SEED[] = {
	 { "UNIPHYCD_TPG_SEED", 0, 22, &umr_bitfield_default },
};
static struct umr_bitfield mmUNIPHYEF_TPG_CONTROL[] = {
	 { "UNIPHYEF_STATIC_TEST_PATTERN", 0, 9, &umr_bitfield_default },
	 { "UNIPHYEF_TPG_EN", 16, 16, &umr_bitfield_default },
	 { "UNIPHYEF_TPG_SEL", 17, 19, &umr_bitfield_default },
};
static struct umr_bitfield mmUNIPHYEF_TPG_SEED[] = {
	 { "UNIPHYEF_TPG_SEED", 0, 22, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_GPIO_PWRSEQ_MASK[] = {
	 { "DC_GPIO_BLON_MASK", 0, 0, &umr_bitfield_default },
	 { "DC_GPIO_BLON_PD_DIS", 4, 4, &umr_bitfield_default },
	 { "DC_GPIO_BLON_RECV", 6, 6, &umr_bitfield_default },
	 { "DC_GPIO_DIGON_MASK", 8, 8, &umr_bitfield_default },
	 { "DC_GPIO_DIGON_PD_DIS", 12, 12, &umr_bitfield_default },
	 { "DC_GPIO_DIGON_RECV", 14, 14, &umr_bitfield_default },
	 { "DC_GPIO_ENA_BL_MASK", 16, 16, &umr_bitfield_default },
	 { "DC_GPIO_ENA_BL_PD_DIS", 20, 20, &umr_bitfield_default },
	 { "DC_GPIO_ENA_BL_RECV", 22, 22, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_GPIO_PWRSEQ_A[] = {
	 { "DC_GPIO_BLON_A", 0, 0, &umr_bitfield_default },
	 { "DC_GPIO_DIGON_A", 8, 8, &umr_bitfield_default },
	 { "DC_GPIO_ENA_BL_A", 16, 16, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_GPIO_PWRSEQ_EN[] = {
	 { "DC_GPIO_BLON_EN", 0, 0, &umr_bitfield_default },
	 { "DC_GPIO_DIGON_EN", 8, 8, &umr_bitfield_default },
	 { "DC_GPIO_ENA_BL_EN", 16, 16, &umr_bitfield_default },
	 { "DC_GPIO_VARY_BL_GENERICA_EN", 1, 1, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_GPIO_PWRSEQ_Y[] = {
	 { "DC_GPIO_BLON_Y", 0, 0, &umr_bitfield_default },
	 { "DC_GPIO_DIGON_Y", 8, 8, &umr_bitfield_default },
	 { "DC_GPIO_ENA_BL_Y", 16, 16, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_GPIO_GENERIC_MASK[] = {
	 { "DC_GPIO_GENERICA_MASK", 0, 0, &umr_bitfield_default },
	 { "DC_GPIO_GENERICA_PD_DIS", 1, 1, &umr_bitfield_default },
	 { "DC_GPIO_GENERICA_RECV", 2, 2, &umr_bitfield_default },
	 { "DC_GPIO_GENERICB_MASK", 4, 4, &umr_bitfield_default },
	 { "DC_GPIO_GENERICB_PD_DIS", 5, 5, &umr_bitfield_default },
	 { "DC_GPIO_GENERICB_RECV", 6, 6, &umr_bitfield_default },
	 { "DC_GPIO_GENERICC_MASK", 8, 8, &umr_bitfield_default },
	 { "DC_GPIO_GENERICC_PD_DIS", 9, 9, &umr_bitfield_default },
	 { "DC_GPIO_GENERICC_RECV", 10, 10, &umr_bitfield_default },
	 { "DC_GPIO_GENERICD_MASK", 12, 12, &umr_bitfield_default },
	 { "DC_GPIO_GENERICD_PD_DIS", 13, 13, &umr_bitfield_default },
	 { "DC_GPIO_GENERICD_RECV", 14, 14, &umr_bitfield_default },
	 { "DC_GPIO_GENERICE_MASK", 16, 16, &umr_bitfield_default },
	 { "DC_GPIO_GENERICE_PD_DIS", 17, 17, &umr_bitfield_default },
	 { "DC_GPIO_GENERICE_RECV", 18, 18, &umr_bitfield_default },
	 { "DC_GPIO_GENERICF_MASK", 20, 20, &umr_bitfield_default },
	 { "DC_GPIO_GENERICF_PD_DIS", 21, 21, &umr_bitfield_default },
	 { "DC_GPIO_GENERICF_RECV", 22, 22, &umr_bitfield_default },
	 { "DC_GPIO_GENERICG_MASK", 24, 24, &umr_bitfield_default },
	 { "DC_GPIO_GENERICG_PD_DIS", 25, 25, &umr_bitfield_default },
	 { "DC_GPIO_GENERICG_RECV", 26, 26, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_GPIO_GENERIC_A[] = {
	 { "DC_GPIO_GENERICA_A", 0, 0, &umr_bitfield_default },
	 { "DC_GPIO_GENERICB_A", 8, 8, &umr_bitfield_default },
	 { "DC_GPIO_GENERICC_A", 16, 16, &umr_bitfield_default },
	 { "DC_GPIO_GENERICD_A", 20, 20, &umr_bitfield_default },
	 { "DC_GPIO_GENERICE_A", 21, 21, &umr_bitfield_default },
	 { "DC_GPIO_GENERICF_A", 22, 22, &umr_bitfield_default },
	 { "DC_GPIO_GENERICG_A", 23, 23, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_GPIO_GENERIC_EN[] = {
	 { "DC_GPIO_GENERICA_EN", 0, 0, &umr_bitfield_default },
	 { "DC_GPIO_GENERICB_EN", 8, 8, &umr_bitfield_default },
	 { "DC_GPIO_GENERICC_EN", 16, 16, &umr_bitfield_default },
	 { "DC_GPIO_GENERICD_EN", 20, 20, &umr_bitfield_default },
	 { "DC_GPIO_GENERICE_EN", 21, 21, &umr_bitfield_default },
	 { "DC_GPIO_GENERICF_EN", 22, 22, &umr_bitfield_default },
	 { "DC_GPIO_GENERICG_EN", 23, 23, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_GPIO_GENERIC_Y[] = {
	 { "DC_GPIO_GENERICA_Y", 0, 0, &umr_bitfield_default },
	 { "DC_GPIO_GENERICB_Y", 8, 8, &umr_bitfield_default },
	 { "DC_GPIO_GENERICC_Y", 16, 16, &umr_bitfield_default },
	 { "DC_GPIO_GENERICD_Y", 20, 20, &umr_bitfield_default },
	 { "DC_GPIO_GENERICE_Y", 21, 21, &umr_bitfield_default },
	 { "DC_GPIO_GENERICF_Y", 22, 22, &umr_bitfield_default },
	 { "DC_GPIO_GENERICG_Y", 23, 23, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_GPIO_DVODATA_MASK[] = {
	 { "DC_GPIO_DVOCLK_MASK", 28, 28, &umr_bitfield_default },
	 { "DC_GPIO_DVOCNTL_MASK", 24, 26, &umr_bitfield_default },
	 { "DC_GPIO_DVODATA_MASK", 0, 23, &umr_bitfield_default },
	 { "DC_GPIO_MVP_DVOCNTL_MASK", 30, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_GPIO_DVODATA_A[] = {
	 { "DC_GPIO_DVOCLK_A", 28, 28, &umr_bitfield_default },
	 { "DC_GPIO_DVOCNTL_A", 24, 26, &umr_bitfield_default },
	 { "DC_GPIO_DVODATA_A", 0, 23, &umr_bitfield_default },
	 { "DC_GPIO_MVP_DVOCNTL_A", 30, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_GPIO_DVODATA_EN[] = {
	 { "DC_GPIO_DVOCLK_EN", 28, 28, &umr_bitfield_default },
	 { "DC_GPIO_DVOCNTL_EN", 24, 26, &umr_bitfield_default },
	 { "DC_GPIO_DVODATA_EN", 0, 23, &umr_bitfield_default },
	 { "DC_GPIO_MVP_DVOCNTL_EN", 30, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_GPIO_DVODATA_Y[] = {
	 { "DC_GPIO_DVOCLK_Y", 28, 28, &umr_bitfield_default },
	 { "DC_GPIO_DVOCNTL_Y", 24, 26, &umr_bitfield_default },
	 { "DC_GPIO_DVODATA_Y", 0, 23, &umr_bitfield_default },
	 { "DC_GPIO_MVP_DVOCNTL_Y", 30, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_GPIO_DDC1_MASK[] = {
	 { "ALLOW_HW_DDC1_PD_EN", 22, 22, &umr_bitfield_default },
	 { "AUX1_POL", 20, 20, &umr_bitfield_default },
	 { "AUX_PAD1_MODE", 16, 16, &umr_bitfield_default },
	 { "DC_GPIO_DDC1CLK_MASK", 0, 0, &umr_bitfield_default },
	 { "DC_GPIO_DDC1CLK_PD_EN", 4, 4, &umr_bitfield_default },
	 { "DC_GPIO_DDC1CLK_RECV", 6, 6, &umr_bitfield_default },
	 { "DC_GPIO_DDC1CLK_STR", 24, 27, &umr_bitfield_default },
	 { "DC_GPIO_DDC1DATA_MASK", 8, 8, &umr_bitfield_default },
	 { "DC_GPIO_DDC1DATA_PD_EN", 12, 12, &umr_bitfield_default },
	 { "DC_GPIO_DDC1DATA_RECV", 14, 14, &umr_bitfield_default },
	 { "DC_GPIO_DDC1DATA_STR", 28, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_GPIO_DDC1_A[] = {
	 { "DC_GPIO_DDC1CLK_A", 0, 0, &umr_bitfield_default },
	 { "DC_GPIO_DDC1DATA_A", 8, 8, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_GPIO_DDC1_EN[] = {
	 { "DC_GPIO_DDC1CLK_EN", 0, 0, &umr_bitfield_default },
	 { "DC_GPIO_DDC1DATA_EN", 8, 8, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_GPIO_DDC1_Y[] = {
	 { "DC_GPIO_DDC1CLK_Y", 0, 0, &umr_bitfield_default },
	 { "DC_GPIO_DDC1DATA_Y", 8, 8, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_GPIO_DDC2_MASK[] = {
	 { "ALLOW_HW_DDC2_PD_EN", 22, 22, &umr_bitfield_default },
	 { "AUX2_POL", 20, 20, &umr_bitfield_default },
	 { "AUX_PAD2_MODE", 16, 16, &umr_bitfield_default },
	 { "DC_GPIO_DDC2CLK_MASK", 0, 0, &umr_bitfield_default },
	 { "DC_GPIO_DDC2CLK_PD_EN", 4, 4, &umr_bitfield_default },
	 { "DC_GPIO_DDC2CLK_RECV", 6, 6, &umr_bitfield_default },
	 { "DC_GPIO_DDC2CLK_STR", 24, 27, &umr_bitfield_default },
	 { "DC_GPIO_DDC2DATA_MASK", 8, 8, &umr_bitfield_default },
	 { "DC_GPIO_DDC2DATA_PD_EN", 12, 12, &umr_bitfield_default },
	 { "DC_GPIO_DDC2DATA_RECV", 14, 14, &umr_bitfield_default },
	 { "DC_GPIO_DDC2DATA_STR", 28, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_GPIO_DDC2_A[] = {
	 { "DC_GPIO_DDC2CLK_A", 0, 0, &umr_bitfield_default },
	 { "DC_GPIO_DDC2DATA_A", 8, 8, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_GPIO_DDC2_EN[] = {
	 { "DC_GPIO_DDC2CLK_EN", 0, 0, &umr_bitfield_default },
	 { "DC_GPIO_DDC2DATA_EN", 8, 8, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_GPIO_DDC2_Y[] = {
	 { "DC_GPIO_DDC2CLK_Y", 0, 0, &umr_bitfield_default },
	 { "DC_GPIO_DDC2DATA_Y", 8, 8, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_GPIO_DDC3_MASK[] = {
	 { "ALLOW_HW_DDC3_PD_EN", 22, 22, &umr_bitfield_default },
	 { "AUX3_POL", 20, 20, &umr_bitfield_default },
	 { "AUX_PAD3_MODE", 16, 16, &umr_bitfield_default },
	 { "DC_GPIO_DDC3CLK_MASK", 0, 0, &umr_bitfield_default },
	 { "DC_GPIO_DDC3CLK_PD_EN", 4, 4, &umr_bitfield_default },
	 { "DC_GPIO_DDC3CLK_RECV", 6, 6, &umr_bitfield_default },
	 { "DC_GPIO_DDC3CLK_STR", 24, 27, &umr_bitfield_default },
	 { "DC_GPIO_DDC3DATA_MASK", 8, 8, &umr_bitfield_default },
	 { "DC_GPIO_DDC3DATA_PD_EN", 12, 12, &umr_bitfield_default },
	 { "DC_GPIO_DDC3DATA_RECV", 14, 14, &umr_bitfield_default },
	 { "DC_GPIO_DDC3DATA_STR", 28, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_GPIO_DDC3_A[] = {
	 { "DC_GPIO_DDC3CLK_A", 0, 0, &umr_bitfield_default },
	 { "DC_GPIO_DDC3DATA_A", 8, 8, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_GPIO_DDC3_EN[] = {
	 { "DC_GPIO_DDC3CLK_EN", 0, 0, &umr_bitfield_default },
	 { "DC_GPIO_DDC3DATA_EN", 8, 8, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_GPIO_DDC3_Y[] = {
	 { "DC_GPIO_DDC3CLK_Y", 0, 0, &umr_bitfield_default },
	 { "DC_GPIO_DDC3DATA_Y", 8, 8, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_GPIO_DDC4_MASK[] = {
	 { "ALLOW_HW_DDC4_PD_EN", 22, 22, &umr_bitfield_default },
	 { "AUX4_POL", 20, 20, &umr_bitfield_default },
	 { "AUX_PAD4_MODE", 16, 16, &umr_bitfield_default },
	 { "DC_GPIO_DDC4CLK_MASK", 0, 0, &umr_bitfield_default },
	 { "DC_GPIO_DDC4CLK_PD_EN", 4, 4, &umr_bitfield_default },
	 { "DC_GPIO_DDC4CLK_RECV", 6, 6, &umr_bitfield_default },
	 { "DC_GPIO_DDC4CLK_STR", 24, 27, &umr_bitfield_default },
	 { "DC_GPIO_DDC4DATA_MASK", 8, 8, &umr_bitfield_default },
	 { "DC_GPIO_DDC4DATA_PD_EN", 12, 12, &umr_bitfield_default },
	 { "DC_GPIO_DDC4DATA_RECV", 14, 14, &umr_bitfield_default },
	 { "DC_GPIO_DDC4DATA_STR", 28, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_GPIO_DDC4_A[] = {
	 { "DC_GPIO_DDC4CLK_A", 0, 0, &umr_bitfield_default },
	 { "DC_GPIO_DDC4DATA_A", 8, 8, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_GPIO_DDC4_EN[] = {
	 { "DC_GPIO_DDC4CLK_EN", 0, 0, &umr_bitfield_default },
	 { "DC_GPIO_DDC4DATA_EN", 8, 8, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_GPIO_DDC4_Y[] = {
	 { "DC_GPIO_DDC4CLK_Y", 0, 0, &umr_bitfield_default },
	 { "DC_GPIO_DDC4DATA_Y", 8, 8, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_GPIO_DDC5_MASK[] = {
	 { "ALLOW_HW_DDC5_PD_EN", 22, 22, &umr_bitfield_default },
	 { "AUX5_POL", 20, 20, &umr_bitfield_default },
	 { "AUX_PAD5_MODE", 16, 16, &umr_bitfield_default },
	 { "DC_GPIO_DDC5CLK_MASK", 0, 0, &umr_bitfield_default },
	 { "DC_GPIO_DDC5CLK_PD_EN", 4, 4, &umr_bitfield_default },
	 { "DC_GPIO_DDC5CLK_RECV", 6, 6, &umr_bitfield_default },
	 { "DC_GPIO_DDC5CLK_STR", 24, 27, &umr_bitfield_default },
	 { "DC_GPIO_DDC5DATA_MASK", 8, 8, &umr_bitfield_default },
	 { "DC_GPIO_DDC5DATA_PD_EN", 12, 12, &umr_bitfield_default },
	 { "DC_GPIO_DDC5DATA_RECV", 14, 14, &umr_bitfield_default },
	 { "DC_GPIO_DDC5DATA_STR", 28, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_GPIO_DDC5_A[] = {
	 { "DC_GPIO_DDC5CLK_A", 0, 0, &umr_bitfield_default },
	 { "DC_GPIO_DDC5DATA_A", 8, 8, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_GPIO_DDC5_EN[] = {
	 { "DC_GPIO_DDC5CLK_EN", 0, 0, &umr_bitfield_default },
	 { "DC_GPIO_DDC5DATA_EN", 8, 8, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_GPIO_DDC5_Y[] = {
	 { "DC_GPIO_DDC5CLK_Y", 0, 0, &umr_bitfield_default },
	 { "DC_GPIO_DDC5DATA_Y", 8, 8, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_GPIO_DDC6_MASK[] = {
	 { "ALLOW_HW_DDC6_PD_EN", 22, 22, &umr_bitfield_default },
	 { "AUX6_POL", 20, 20, &umr_bitfield_default },
	 { "AUX_PAD6_MODE", 16, 16, &umr_bitfield_default },
	 { "DC_GPIO_DDC6CLK_MASK", 0, 0, &umr_bitfield_default },
	 { "DC_GPIO_DDC6CLK_PD_EN", 4, 4, &umr_bitfield_default },
	 { "DC_GPIO_DDC6CLK_RECV", 6, 6, &umr_bitfield_default },
	 { "DC_GPIO_DDC6CLK_STR", 24, 27, &umr_bitfield_default },
	 { "DC_GPIO_DDC6DATA_MASK", 8, 8, &umr_bitfield_default },
	 { "DC_GPIO_DDC6DATA_PD_EN", 12, 12, &umr_bitfield_default },
	 { "DC_GPIO_DDC6DATA_RECV", 14, 14, &umr_bitfield_default },
	 { "DC_GPIO_DDC6DATA_STR", 28, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_GPIO_DDC6_A[] = {
	 { "DC_GPIO_DDC6CLK_A", 0, 0, &umr_bitfield_default },
	 { "DC_GPIO_DDC6DATA_A", 8, 8, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_GPIO_DDC6_EN[] = {
	 { "DC_GPIO_DDC6CLK_EN", 0, 0, &umr_bitfield_default },
	 { "DC_GPIO_DDC6DATA_EN", 8, 8, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_GPIO_DDC6_Y[] = {
	 { "DC_GPIO_DDC6CLK_Y", 0, 0, &umr_bitfield_default },
	 { "DC_GPIO_DDC6DATA_Y", 8, 8, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_GPIO_SYNCA_MASK[] = {
	 { "DC_GPIO_HSYNCA_CRTC_HSYNC_MASK", 24, 26, &umr_bitfield_default },
	 { "DC_GPIO_HSYNCA_MASK", 0, 0, &umr_bitfield_default },
	 { "DC_GPIO_HSYNCA_PD_DIS", 4, 4, &umr_bitfield_default },
	 { "DC_GPIO_HSYNCA_RECV", 6, 6, &umr_bitfield_default },
	 { "DC_GPIO_VSYNCA_CRTC_VSYNC_MASK", 28, 30, &umr_bitfield_default },
	 { "DC_GPIO_VSYNCA_MASK", 8, 8, &umr_bitfield_default },
	 { "DC_GPIO_VSYNCA_PD_DIS", 12, 12, &umr_bitfield_default },
	 { "DC_GPIO_VSYNCA_RECV", 14, 14, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_GPIO_SYNCA_A[] = {
	 { "DC_GPIO_HSYNCA_A", 0, 0, &umr_bitfield_default },
	 { "DC_GPIO_VSYNCA_A", 8, 8, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_GPIO_SYNCA_EN[] = {
	 { "DC_GPIO_HSYNCA_EN", 0, 0, &umr_bitfield_default },
	 { "DC_GPIO_VSYNCA_EN", 8, 8, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_GPIO_SYNCA_Y[] = {
	 { "DC_GPIO_HSYNCA_Y", 0, 0, &umr_bitfield_default },
	 { "DC_GPIO_VSYNCA_Y", 8, 8, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_GPIO_GENLK_MASK[] = {
	 { "DC_GPIO_GENLK_CLK_MASK", 0, 0, &umr_bitfield_default },
	 { "DC_GPIO_GENLK_CLK_PD_DIS", 1, 1, &umr_bitfield_default },
	 { "DC_GPIO_GENLK_CLK_PU_EN", 3, 3, &umr_bitfield_default },
	 { "DC_GPIO_GENLK_CLK_RECV", 2, 2, &umr_bitfield_default },
	 { "DC_GPIO_GENLK_VSYNC_MASK", 8, 8, &umr_bitfield_default },
	 { "DC_GPIO_GENLK_VSYNC_PD_DIS", 9, 9, &umr_bitfield_default },
	 { "DC_GPIO_GENLK_VSYNC_PU_EN", 11, 11, &umr_bitfield_default },
	 { "DC_GPIO_GENLK_VSYNC_RECV", 10, 10, &umr_bitfield_default },
	 { "DC_GPIO_SWAPLOCK_A_MASK", 16, 16, &umr_bitfield_default },
	 { "DC_GPIO_SWAPLOCK_A_PD_DIS", 17, 17, &umr_bitfield_default },
	 { "DC_GPIO_SWAPLOCK_A_PU_EN", 19, 19, &umr_bitfield_default },
	 { "DC_GPIO_SWAPLOCK_A_RECV", 18, 18, &umr_bitfield_default },
	 { "DC_GPIO_SWAPLOCK_B_MASK", 24, 24, &umr_bitfield_default },
	 { "DC_GPIO_SWAPLOCK_B_PD_DIS", 25, 25, &umr_bitfield_default },
	 { "DC_GPIO_SWAPLOCK_B_PU_EN", 27, 27, &umr_bitfield_default },
	 { "DC_GPIO_SWAPLOCK_B_RECV", 26, 26, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_GPIO_GENLK_A[] = {
	 { "DC_GPIO_GENLK_CLK_A", 0, 0, &umr_bitfield_default },
	 { "DC_GPIO_GENLK_VSYNC_A", 8, 8, &umr_bitfield_default },
	 { "DC_GPIO_SWAPLOCK_A_A", 16, 16, &umr_bitfield_default },
	 { "DC_GPIO_SWAPLOCK_B_A", 24, 24, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_GPIO_GENLK_EN[] = {
	 { "DC_GPIO_GENLK_CLK_EN", 0, 0, &umr_bitfield_default },
	 { "DC_GPIO_GENLK_VSYNC_EN", 8, 8, &umr_bitfield_default },
	 { "DC_GPIO_SWAPLOCK_A_EN", 16, 16, &umr_bitfield_default },
	 { "DC_GPIO_SWAPLOCK_B_EN", 24, 24, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_GPIO_GENLK_Y[] = {
	 { "DC_GPIO_GENLK_CLK_Y", 0, 0, &umr_bitfield_default },
	 { "DC_GPIO_GENLK_VSYNC_Y", 8, 8, &umr_bitfield_default },
	 { "DC_GPIO_SWAPLOCK_A_Y", 16, 16, &umr_bitfield_default },
	 { "DC_GPIO_SWAPLOCK_B_Y", 24, 24, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_GPIO_HPD_MASK[] = {
	 { "DC_GPIO_HPD1_MASK", 0, 0, &umr_bitfield_default },
	 { "DC_GPIO_HPD1_PD_DIS", 4, 4, &umr_bitfield_default },
	 { "DC_GPIO_HPD1_RECV", 6, 6, &umr_bitfield_default },
	 { "DC_GPIO_HPD2_MASK", 8, 8, &umr_bitfield_default },
	 { "DC_GPIO_HPD2_PD_DIS", 9, 9, &umr_bitfield_default },
	 { "DC_GPIO_HPD2_RECV", 10, 10, &umr_bitfield_default },
	 { "DC_GPIO_HPD3_MASK", 16, 16, &umr_bitfield_default },
	 { "DC_GPIO_HPD3_PD_DIS", 17, 17, &umr_bitfield_default },
	 { "DC_GPIO_HPD3_RECV", 18, 18, &umr_bitfield_default },
	 { "DC_GPIO_HPD4_MASK", 20, 20, &umr_bitfield_default },
	 { "DC_GPIO_HPD4_PD_DIS", 21, 21, &umr_bitfield_default },
	 { "DC_GPIO_HPD4_RECV", 22, 22, &umr_bitfield_default },
	 { "DC_GPIO_HPD5_MASK", 24, 24, &umr_bitfield_default },
	 { "DC_GPIO_HPD5_PD_DIS", 25, 25, &umr_bitfield_default },
	 { "DC_GPIO_HPD5_RECV", 26, 26, &umr_bitfield_default },
	 { "DC_GPIO_HPD6_MASK", 28, 28, &umr_bitfield_default },
	 { "DC_GPIO_HPD6_PD_DIS", 29, 29, &umr_bitfield_default },
	 { "DC_GPIO_HPD6_RECV", 30, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_GPIO_HPD_A[] = {
	 { "DC_GPIO_HPD1_A", 0, 0, &umr_bitfield_default },
	 { "DC_GPIO_HPD2_A", 8, 8, &umr_bitfield_default },
	 { "DC_GPIO_HPD3_A", 16, 16, &umr_bitfield_default },
	 { "DC_GPIO_HPD4_A", 24, 24, &umr_bitfield_default },
	 { "DC_GPIO_HPD5_A", 26, 26, &umr_bitfield_default },
	 { "DC_GPIO_HPD6_A", 28, 28, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_GPIO_HPD_EN[] = {
	 { "DC_GPIO_HPD1_EN", 0, 0, &umr_bitfield_default },
	 { "DC_GPIO_HPD2_EN", 8, 8, &umr_bitfield_default },
	 { "DC_GPIO_HPD3_EN", 16, 16, &umr_bitfield_default },
	 { "DC_GPIO_HPD4_EN", 24, 24, &umr_bitfield_default },
	 { "DC_GPIO_HPD5_EN", 26, 26, &umr_bitfield_default },
	 { "DC_GPIO_HPD6_EN", 28, 28, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_GPIO_HPD_Y[] = {
	 { "DC_GPIO_HPD1_Y", 0, 0, &umr_bitfield_default },
	 { "DC_GPIO_HPD2_Y", 8, 8, &umr_bitfield_default },
	 { "DC_GPIO_HPD3_Y", 16, 16, &umr_bitfield_default },
	 { "DC_GPIO_HPD4_Y", 24, 24, &umr_bitfield_default },
	 { "DC_GPIO_HPD5_Y", 26, 26, &umr_bitfield_default },
	 { "DC_GPIO_HPD6_Y", 28, 28, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_GPIO_DDCVGA_MASK[] = {
	 { "ALLOW_HW_DDCVGA_PD_EN", 22, 22, &umr_bitfield_default },
	 { "AUX_PADVGA_MODE", 16, 16, &umr_bitfield_default },
	 { "AUXVGA_POL", 20, 20, &umr_bitfield_default },
	 { "DC_GPIO_DDCVGACLK_MASK", 0, 0, &umr_bitfield_default },
	 { "DC_GPIO_DDCVGACLK_RECV", 6, 6, &umr_bitfield_default },
	 { "DC_GPIO_DDCVGACLK_STR", 24, 27, &umr_bitfield_default },
	 { "DC_GPIO_DDCVGADATA_MASK", 8, 8, &umr_bitfield_default },
	 { "DC_GPIO_DDCVGADATA_PD_EN", 12, 12, &umr_bitfield_default },
	 { "DC_GPIO_DDCVGADATA_RECV", 14, 14, &umr_bitfield_default },
	 { "DC_GPIO_DDCVGADATA_STR", 28, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_GPIO_DDCVGA_A[] = {
	 { "DC_GPIO_DDCVGACLK_A", 0, 0, &umr_bitfield_default },
	 { "DC_GPIO_DDCVGADATA_A", 8, 8, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_GPIO_DDCVGA_EN[] = {
	 { "DC_GPIO_DDCVGACLK_EN", 0, 0, &umr_bitfield_default },
	 { "DC_GPIO_DDCVGADATA_EN", 8, 8, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_GPIO_DDCVGA_Y[] = {
	 { "DC_GPIO_DDCVGACLK_Y", 0, 0, &umr_bitfield_default },
	 { "DC_GPIO_DDCVGADATA_Y", 8, 8, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_GPIO_I2CPAD_MASK[] = {
	 { "DC_GPIO_SCL_MASK", 0, 0, &umr_bitfield_default },
	 { "DC_GPIO_SCL_PD_DIS", 1, 1, &umr_bitfield_default },
	 { "DC_GPIO_SCL_RECV", 2, 2, &umr_bitfield_default },
	 { "DC_GPIO_SDA_MASK", 4, 4, &umr_bitfield_default },
	 { "DC_GPIO_SDA_PD_DIS", 5, 5, &umr_bitfield_default },
	 { "DC_GPIO_SDA_RECV", 6, 6, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_GPIO_I2CPAD_A[] = {
	 { "DC_GPIO_SCL_A", 0, 0, &umr_bitfield_default },
	 { "DC_GPIO_SDA_A", 1, 1, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_GPIO_I2CPAD_EN[] = {
	 { "DC_GPIO_SCL_EN", 0, 0, &umr_bitfield_default },
	 { "DC_GPIO_SDA_EN", 1, 1, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_GPIO_I2CPAD_Y[] = {
	 { "DC_GPIO_SCL_Y", 0, 0, &umr_bitfield_default },
	 { "DC_GPIO_SDA_Y", 1, 1, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_GPIO_PAD_STRENGTH_1[] = {
	 { "GENLK_STRENGTH_SN", 0, 3, &umr_bitfield_default },
	 { "GENLK_STRENGTH_SP", 4, 7, &umr_bitfield_default },
	 { "SYNC_STRENGTH_SN", 24, 27, &umr_bitfield_default },
	 { "SYNC_STRENGTH_SP", 28, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_GPIO_PAD_STRENGTH_2[] = {
	 { "PWRSEQ_STRENGTH_SN", 16, 19, &umr_bitfield_default },
	 { "PWRSEQ_STRENGTH_SP", 20, 23, &umr_bitfield_default },
	 { "STRENGTH_SN", 0, 3, &umr_bitfield_default },
	 { "STRENGTH_SP", 4, 7, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_GPIO_I2CPAD_STRENGTH[] = {
	 { "I2C_STRENGTH_SN", 0, 3, &umr_bitfield_default },
	 { "I2C_STRENGTH_SP", 4, 7, &umr_bitfield_default },
};
static struct umr_bitfield mmDVO_STRENGTH_CONTROL[] = {
	 { "DVOCLK_SN", 12, 15, &umr_bitfield_default },
	 { "DVOCLK_SP", 8, 11, &umr_bitfield_default },
	 { "DVO_LSB_VMODE", 28, 28, &umr_bitfield_default },
	 { "DVO_MSB_VMODE", 29, 29, &umr_bitfield_default },
	 { "DVO_SN", 4, 7, &umr_bitfield_default },
	 { "DVO_SP", 0, 3, &umr_bitfield_default },
};
static struct umr_bitfield mmDVO_VREF_CONTROL[] = {
	 { "DVO_VREFCAL", 4, 7, &umr_bitfield_default },
	 { "DVO_VREFPON", 0, 0, &umr_bitfield_default },
	 { "DVO_VREFSEL", 1, 1, &umr_bitfield_default },
};
static struct umr_bitfield mmDVO_SKEW_ADJUST[] = {
	 { "DVO_SKEW_ADJUST", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmPHY_AUX_CNTL[] = {
	 { "AUX_PAD_RXSEL", 16, 16, &umr_bitfield_default },
	 { "AUX_PAD_SLEWN", 12, 12, &umr_bitfield_default },
	 { "AUX_PAD_WAKE", 14, 14, &umr_bitfield_default },
};
static struct umr_bitfield mmDAC_ENABLE[] = {
	 { "DAC_ENABLE", 0, 0, &umr_bitfield_default },
	 { "DAC_RESYNC_FIFO_ENABLE", 1, 1, &umr_bitfield_default },
	 { "DAC_RESYNC_FIFO_ERROR_ACK", 5, 5, &umr_bitfield_default },
	 { "DAC_RESYNC_FIFO_ERROR", 4, 4, &umr_bitfield_default },
	 { "DAC_RESYNC_FIFO_POINTER_SKEW", 2, 3, &umr_bitfield_default },
	 { "DAC_RESYNC_FIFO_TVOUT_SIM", 8, 8, &umr_bitfield_default },
};
static struct umr_bitfield mmDAC_SOURCE_SELECT[] = {
	 { "DAC_SOURCE_SELECT", 0, 2, &umr_bitfield_default },
	 { "DAC_TV_SELECT", 3, 3, &umr_bitfield_default },
};
static struct umr_bitfield mmDAC_CRC_EN[] = {
	 { "DAC_CRC_CONT_EN", 16, 16, &umr_bitfield_default },
	 { "DAC_CRC_EN", 0, 0, &umr_bitfield_default },
};
static struct umr_bitfield mmDAC_CRC_CONTROL[] = {
	 { "DAC_CRC_FIELD", 0, 0, &umr_bitfield_default },
	 { "DAC_CRC_ONLY_BLANKb", 8, 8, &umr_bitfield_default },
};
static struct umr_bitfield mmDAC_CRC_SIG_RGB_MASK[] = {
	 { "DAC_CRC_SIG_BLUE_MASK", 0, 9, &umr_bitfield_default },
	 { "DAC_CRC_SIG_GREEN_MASK", 10, 19, &umr_bitfield_default },
	 { "DAC_CRC_SIG_RED_MASK", 20, 29, &umr_bitfield_default },
};
static struct umr_bitfield mmDAC_CRC_SIG_CONTROL_MASK[] = {
	 { "DAC_CRC_SIG_CONTROL_MASK", 0, 5, &umr_bitfield_default },
};
static struct umr_bitfield mmDAC_CRC_SIG_RGB[] = {
	 { "DAC_CRC_SIG_BLUE", 0, 9, &umr_bitfield_default },
	 { "DAC_CRC_SIG_GREEN", 10, 19, &umr_bitfield_default },
	 { "DAC_CRC_SIG_RED", 20, 29, &umr_bitfield_default },
};
static struct umr_bitfield mmDAC_CRC_SIG_CONTROL[] = {
	 { "DAC_CRC_SIG_CONTROL", 0, 5, &umr_bitfield_default },
};
static struct umr_bitfield mmDAC_SYNC_TRISTATE_CONTROL[] = {
	 { "DAC_HSYNCA_TRISTATE", 0, 0, &umr_bitfield_default },
	 { "DAC_SYNCA_TRISTATE", 16, 16, &umr_bitfield_default },
	 { "DAC_VSYNCA_TRISTATE", 8, 8, &umr_bitfield_default },
};
static struct umr_bitfield mmDAC_STEREOSYNC_SELECT[] = {
	 { "DAC_STEREOSYNC_SELECT", 0, 2, &umr_bitfield_default },
};
static struct umr_bitfield mmDAC_AUTODETECT_CONTROL[] = {
	 { "DAC_AUTODETECT_CHECK_MASK", 16, 18, &umr_bitfield_default },
	 { "DAC_AUTODETECT_FRAME_TIME_COUNTER", 8, 15, &umr_bitfield_default },
	 { "DAC_AUTODETECT_MODE", 0, 1, &umr_bitfield_default },
};
static struct umr_bitfield mmDAC_AUTODETECT_CONTROL2[] = {
	 { "DAC_AUTODETECT_POWERUP_COUNTER", 0, 7, &umr_bitfield_default },
	 { "DAC_AUTODETECT_TESTMODE", 8, 8, &umr_bitfield_default },
};
static struct umr_bitfield mmDAC_AUTODETECT_CONTROL3[] = {
	 { "DAC_AUTODET_COMPARATOR_IN_DELAY", 0, 7, &umr_bitfield_default },
	 { "DAC_AUTODET_COMPARATOR_OUT_DELAY", 8, 15, &umr_bitfield_default },
};
static struct umr_bitfield mmDAC_AUTODETECT_STATUS[] = {
	 { "DAC_AUTODETECT_BLUE_SENSE", 24, 25, &umr_bitfield_default },
	 { "DAC_AUTODETECT_CONNECT", 4, 4, &umr_bitfield_default },
	 { "DAC_AUTODETECT_GREEN_SENSE", 16, 17, &umr_bitfield_default },
	 { "DAC_AUTODETECT_RED_SENSE", 8, 9, &umr_bitfield_default },
	 { "DAC_AUTODETECT_STATUS", 0, 0, &umr_bitfield_default },
};
static struct umr_bitfield mmDAC_AUTODETECT_INT_CONTROL[] = {
	 { "DAC_AUTODETECT_ACK", 0, 0, &umr_bitfield_default },
	 { "DAC_AUTODETECT_INT_ENABLE", 16, 16, &umr_bitfield_default },
};
static struct umr_bitfield mmDAC_FORCE_OUTPUT_CNTL[] = {
	 { "DAC_FORCE_DATA_EN", 0, 0, &umr_bitfield_default },
	 { "DAC_FORCE_DATA_ON_BLANKb_ONLY", 24, 24, &umr_bitfield_default },
	 { "DAC_FORCE_DATA_SEL", 8, 10, &umr_bitfield_default },
};
static struct umr_bitfield mmDAC_FORCE_DATA[] = {
	 { "DAC_FORCE_DATA", 0, 9, &umr_bitfield_default },
};
static struct umr_bitfield mmDAC_POWERDOWN[] = {
	 { "DAC_POWERDOWN_BLUE", 8, 8, &umr_bitfield_default },
	 { "DAC_POWERDOWN_GREEN", 16, 16, &umr_bitfield_default },
	 { "DAC_POWERDOWN", 0, 0, &umr_bitfield_default },
	 { "DAC_POWERDOWN_RED", 24, 24, &umr_bitfield_default },
};
static struct umr_bitfield mmDAC_CONTROL[] = {
	 { "DAC_DFORCE_EN", 0, 0, &umr_bitfield_default },
	 { "DAC_TV_ENABLE", 8, 8, &umr_bitfield_default },
	 { "DAC_ZSCALE_SHIFT", 16, 16, &umr_bitfield_default },
};
static struct umr_bitfield mmDAC_COMPARATOR_ENABLE[] = {
	 { "DAC_B_ASYNC_ENABLE", 18, 18, &umr_bitfield_default },
	 { "DAC_COMP_DDET_REF_EN", 0, 0, &umr_bitfield_default },
	 { "DAC_COMP_SDET_REF_EN", 8, 8, &umr_bitfield_default },
	 { "DAC_G_ASYNC_ENABLE", 17, 17, &umr_bitfield_default },
	 { "DAC_R_ASYNC_ENABLE", 16, 16, &umr_bitfield_default },
};
static struct umr_bitfield mmDAC_COMPARATOR_OUTPUT[] = {
	 { "DAC_COMPARATOR_OUTPUT_BLUE", 1, 1, &umr_bitfield_default },
	 { "DAC_COMPARATOR_OUTPUT_GREEN", 2, 2, &umr_bitfield_default },
	 { "DAC_COMPARATOR_OUTPUT", 0, 0, &umr_bitfield_default },
	 { "DAC_COMPARATOR_OUTPUT_RED", 3, 3, &umr_bitfield_default },
};
static struct umr_bitfield mmDAC_PWR_CNTL[] = {
	 { "DAC_BG_MODE", 0, 1, &umr_bitfield_default },
	 { "DAC_PWRCNTL", 16, 17, &umr_bitfield_default },
};
static struct umr_bitfield mmDAC_DFT_CONFIG[] = {
	 { "DAC_DFT_CONFIG", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDAC_FIFO_STATUS[] = {
	 { "DAC_FIFO_CAL_AVERAGE_LEVEL", 10, 15, &umr_bitfield_default },
	 { "DAC_FIFO_CALIBRATED", 29, 29, &umr_bitfield_default },
	 { "DAC_FIFO_FORCE_RECAL_AVERAGE", 30, 30, &umr_bitfield_default },
	 { "DAC_FIFO_FORCE_RECOMP_MINMAX", 31, 31, &umr_bitfield_default },
	 { "DAC_FIFO_MAXIMUM_LEVEL", 16, 19, &umr_bitfield_default },
	 { "DAC_FIFO_MINIMUM_LEVEL", 22, 25, &umr_bitfield_default },
	 { "DAC_FIFO_OVERWRITE_LEVEL", 2, 7, &umr_bitfield_default },
	 { "DAC_FIFO_USE_OVERWRITE_LEVEL", 1, 1, &umr_bitfield_default },
};
static struct umr_bitfield mmDAC_MACRO_CNTL_RESERVED0[] = {
	 { "DAC_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmBPHYC_DAC_MACRO_CNTL[] = {
	 { "BPHYC_DAC_ANALOG_MONITOR", 24, 27, &umr_bitfield_default },
	 { "BPHYC_DAC_BANDGAP_ADJUSTMENT", 16, 21, &umr_bitfield_default },
	 { "BPHYC_DAC_COREMON", 28, 28, &umr_bitfield_default },
	 { "BPHYC_DAC_WHITE_FINE_CONTROL", 8, 13, &umr_bitfield_default },
	 { "BPHYC_DAC_WHITE_LEVEL", 0, 1, &umr_bitfield_default },
};
static struct umr_bitfield mmBPHYC_DAC_AUTO_CALIB_CONTROL[] = {
	 { "BPHYC_DAC_CAL_COMPLETE", 28, 28, &umr_bitfield_default },
	 { "BPHYC_DAC_CAL_DACADJ_EN", 2, 2, &umr_bitfield_default },
	 { "BPHYC_DAC_CAL_EN", 1, 1, &umr_bitfield_default },
	 { "BPHYC_DAC_CAL_INITB", 0, 0, &umr_bitfield_default },
	 { "BPHYC_DAC_CAL_MASK", 20, 22, &umr_bitfield_default },
	 { "BPHYC_DAC_CAL_WAIT_ADJUST", 4, 13, &umr_bitfield_default },
};
static struct umr_bitfield mmDAC_MACRO_CNTL_RESERVED3[] = {
	 { "DAC_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmCOMM_MATRIXA_TRANS_C11_C12[] = {
	 { "COMM_MATRIXA_TRANS_C11", 0, 15, &umr_bitfield_default },
	 { "COMM_MATRIXA_TRANS_C12", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmCOMM_MATRIXA_TRANS_C13_C14[] = {
	 { "COMM_MATRIXA_TRANS_C13", 0, 15, &umr_bitfield_default },
	 { "COMM_MATRIXA_TRANS_C14", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmCOMM_MATRIXA_TRANS_C21_C22[] = {
	 { "COMM_MATRIXA_TRANS_C21", 0, 15, &umr_bitfield_default },
	 { "COMM_MATRIXA_TRANS_C22", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmCOMM_MATRIXA_TRANS_C23_C24[] = {
	 { "COMM_MATRIXA_TRANS_C23", 0, 15, &umr_bitfield_default },
	 { "COMM_MATRIXA_TRANS_C24", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmCOMM_MATRIXA_TRANS_C31_C32[] = {
	 { "COMM_MATRIXA_TRANS_C31", 0, 15, &umr_bitfield_default },
	 { "COMM_MATRIXA_TRANS_C32", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmCOMM_MATRIXA_TRANS_C33_C34[] = {
	 { "COMM_MATRIXA_TRANS_C33", 0, 15, &umr_bitfield_default },
	 { "COMM_MATRIXA_TRANS_C34", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmCOMM_MATRIXB_TRANS_C11_C12[] = {
	 { "COMM_MATRIXB_TRANS_C11", 0, 15, &umr_bitfield_default },
	 { "COMM_MATRIXB_TRANS_C12", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmCOMM_MATRIXB_TRANS_C13_C14[] = {
	 { "COMM_MATRIXB_TRANS_C13", 0, 15, &umr_bitfield_default },
	 { "COMM_MATRIXB_TRANS_C14", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmCOMM_MATRIXB_TRANS_C21_C22[] = {
	 { "COMM_MATRIXB_TRANS_C21", 0, 15, &umr_bitfield_default },
	 { "COMM_MATRIXB_TRANS_C22", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmCOMM_MATRIXB_TRANS_C23_C24[] = {
	 { "COMM_MATRIXB_TRANS_C23", 0, 15, &umr_bitfield_default },
	 { "COMM_MATRIXB_TRANS_C24", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmCOMM_MATRIXB_TRANS_C31_C32[] = {
	 { "COMM_MATRIXB_TRANS_C31", 0, 15, &umr_bitfield_default },
	 { "COMM_MATRIXB_TRANS_C32", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmCOMM_MATRIXB_TRANS_C33_C34[] = {
	 { "COMM_MATRIXB_TRANS_C33", 0, 15, &umr_bitfield_default },
	 { "COMM_MATRIXB_TRANS_C34", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmCUR_CONTROL[] = {
	 { "CUR_INV_TRANS_CLAMP", 4, 4, &umr_bitfield_default },
	 { "CURSOR_2X_MAGNIFY", 16, 16, &umr_bitfield_default },
	 { "CURSOR_EN", 0, 0, &umr_bitfield_default },
	 { "CURSOR_FORCE_MC_ON", 20, 20, &umr_bitfield_default },
	 { "CURSOR_MODE", 8, 9, &umr_bitfield_default },
	 { "CURSOR_URGENT_CONTROL", 24, 26, &umr_bitfield_default },
};
static struct umr_bitfield mmCUR_SURFACE_ADDRESS[] = {
	 { "CURSOR_SURFACE_ADDRESS", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmCUR_SIZE[] = {
	 { "CURSOR_HEIGHT", 0, 5, &umr_bitfield_default },
	 { "CURSOR_WIDTH", 16, 21, &umr_bitfield_default },
};
static struct umr_bitfield mmCUR_SURFACE_ADDRESS_HIGH[] = {
	 { "CURSOR_SURFACE_ADDRESS_HIGH", 0, 7, &umr_bitfield_default },
};
static struct umr_bitfield mmCUR_POSITION[] = {
	 { "CURSOR_X_POSITION", 16, 29, &umr_bitfield_default },
	 { "CURSOR_Y_POSITION", 0, 13, &umr_bitfield_default },
};
static struct umr_bitfield mmCUR_HOT_SPOT[] = {
	 { "CURSOR_HOT_SPOT_X", 16, 21, &umr_bitfield_default },
	 { "CURSOR_HOT_SPOT_Y", 0, 5, &umr_bitfield_default },
};
static struct umr_bitfield mmCUR_COLOR1[] = {
	 { "CUR_COLOR1_BLUE", 0, 7, &umr_bitfield_default },
	 { "CUR_COLOR1_GREEN", 8, 15, &umr_bitfield_default },
	 { "CUR_COLOR1_RED", 16, 23, &umr_bitfield_default },
};
static struct umr_bitfield mmCUR_COLOR2[] = {
	 { "CUR_COLOR2_BLUE", 0, 7, &umr_bitfield_default },
	 { "CUR_COLOR2_GREEN", 8, 15, &umr_bitfield_default },
	 { "CUR_COLOR2_RED", 16, 23, &umr_bitfield_default },
};
static struct umr_bitfield mmCUR_UPDATE[] = {
	 { "CURSOR_DISABLE_MULTIPLE_UPDATE", 24, 24, &umr_bitfield_default },
	 { "CURSOR_UPDATE_LOCK", 16, 16, &umr_bitfield_default },
	 { "CURSOR_UPDATE_PENDING", 0, 0, &umr_bitfield_default },
	 { "CURSOR_UPDATE_TAKEN", 1, 1, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_LUT_RW_MODE[] = {
	 { "DC_LUT_RW_MODE", 0, 0, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_LUT_RW_INDEX[] = {
	 { "DC_LUT_RW_INDEX", 0, 7, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_LUT_SEQ_COLOR[] = {
	 { "DC_LUT_SEQ_COLOR", 0, 15, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_LUT_PWL_DATA[] = {
	 { "DC_LUT_BASE", 0, 15, &umr_bitfield_default },
	 { "DC_LUT_DELTA", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_LUT_30_COLOR[] = {
	 { "DC_LUT_COLOR_10_BLUE", 0, 9, &umr_bitfield_default },
	 { "DC_LUT_COLOR_10_GREEN", 10, 19, &umr_bitfield_default },
	 { "DC_LUT_COLOR_10_RED", 20, 29, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_LUT_VGA_ACCESS_ENABLE[] = {
	 { "DC_LUT_VGA_ACCESS_ENABLE", 0, 0, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_LUT_WRITE_EN_MASK[] = {
	 { "DC_LUT_WRITE_EN_MASK", 0, 2, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_LUT_AUTOFILL[] = {
	 { "DC_LUT_AUTOFILL_DONE", 1, 1, &umr_bitfield_default },
	 { "DC_LUT_AUTOFILL", 0, 0, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_LUT_CONTROL[] = {
	 { "DC_LUT_DATA_B_FLOAT_POINT_EN", 5, 5, &umr_bitfield_default },
	 { "DC_LUT_DATA_B_FORMAT", 6, 7, &umr_bitfield_default },
	 { "DC_LUT_DATA_B_SIGNED_EN", 4, 4, &umr_bitfield_default },
	 { "DC_LUT_DATA_G_FLOAT_POINT_EN", 13, 13, &umr_bitfield_default },
	 { "DC_LUT_DATA_G_FORMAT", 14, 15, &umr_bitfield_default },
	 { "DC_LUT_DATA_G_SIGNED_EN", 12, 12, &umr_bitfield_default },
	 { "DC_LUT_DATA_R_FLOAT_POINT_EN", 21, 21, &umr_bitfield_default },
	 { "DC_LUT_DATA_R_FORMAT", 22, 23, &umr_bitfield_default },
	 { "DC_LUT_DATA_R_SIGNED_EN", 20, 20, &umr_bitfield_default },
	 { "DC_LUT_INC_B", 0, 3, &umr_bitfield_default },
	 { "DC_LUT_INC_G", 8, 11, &umr_bitfield_default },
	 { "DC_LUT_INC_R", 16, 19, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_LUT_BLACK_OFFSET_BLUE[] = {
	 { "DC_LUT_BLACK_OFFSET_BLUE", 0, 15, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_LUT_BLACK_OFFSET_GREEN[] = {
	 { "DC_LUT_BLACK_OFFSET_GREEN", 0, 15, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_LUT_BLACK_OFFSET_RED[] = {
	 { "DC_LUT_BLACK_OFFSET_RED", 0, 15, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_LUT_WHITE_OFFSET_BLUE[] = {
	 { "DC_LUT_WHITE_OFFSET_BLUE", 0, 15, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_LUT_WHITE_OFFSET_GREEN[] = {
	 { "DC_LUT_WHITE_OFFSET_GREEN", 0, 15, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_LUT_WHITE_OFFSET_RED[] = {
	 { "DC_LUT_WHITE_OFFSET_RED", 0, 15, &umr_bitfield_default },
};
static struct umr_bitfield mmCUR_REQUEST_FILTER_CNTL[] = {
	 { "CUR_REQUEST_FILTER_DIS", 0, 0, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_MVP_LB_CONTROL[] = {
	 { "DC_MVP_SPARE_FLOPS", 31, 31, &umr_bitfield_default },
	 { "DC_MVP_SWAP_LOCK_IN_CAP", 28, 28, &umr_bitfield_default },
	 { "DC_MVP_SWAP_LOCK_OUT_FORCE_ONE", 12, 12, &umr_bitfield_default },
	 { "DC_MVP_SWAP_LOCK_OUT_FORCE_ZERO", 16, 16, &umr_bitfield_default },
	 { "DC_MVP_SWAP_LOCK_OUT_SEL", 8, 8, &umr_bitfield_default },
	 { "DC_MVP_SWAP_LOCK_STATUS", 20, 20, &umr_bitfield_default },
	 { "MVP_SWAP_LOCK_IN_MODE", 0, 1, &umr_bitfield_default },
};
static struct umr_bitfield mmEXT_OVERSCAN_LEFT_RIGHT[] = {
	 { "EXT_OVERSCAN_LEFT", 16, 27, &umr_bitfield_default },
	 { "EXT_OVERSCAN_RIGHT", 0, 11, &umr_bitfield_default },
};
static struct umr_bitfield mmEXT_OVERSCAN_TOP_BOTTOM[] = {
	 { "EXT_OVERSCAN_BOTTOM", 0, 11, &umr_bitfield_default },
	 { "EXT_OVERSCAN_TOP", 16, 27, &umr_bitfield_default },
};
static struct umr_bitfield mmAFMT_AUDIO_PACKET_CONTROL2[] = {
	 { "AFMT_60958_OSF_OVRD", 28, 28, &umr_bitfield_default },
	 { "AFMT_AUDIO_CHANNEL_ENABLE", 8, 15, &umr_bitfield_default },
	 { "AFMT_AUDIO_LAYOUT_OVRD", 0, 0, &umr_bitfield_default },
	 { "AFMT_AUDIO_LAYOUT_SELECT", 1, 1, &umr_bitfield_default },
	 { "AFMT_DP_AUDIO_STREAM_ID", 16, 23, &umr_bitfield_default },
	 { "AFMT_HBR_ENABLE_OVRD", 24, 24, &umr_bitfield_default },
};
static struct umr_bitfield mmAFMT_ISRC1_0[] = {
	 { "AFMT_ISRC_CONTINUE", 6, 6, &umr_bitfield_default },
	 { "AFMT_ISRC_STATUS", 0, 2, &umr_bitfield_default },
	 { "AFMT_ISRC_VALID", 7, 7, &umr_bitfield_default },
};
static struct umr_bitfield mmAFMT_ISRC1_1[] = {
	 { "AFMT_UPC_EAN_ISRC0", 0, 7, &umr_bitfield_default },
	 { "AFMT_UPC_EAN_ISRC1", 8, 15, &umr_bitfield_default },
	 { "AFMT_UPC_EAN_ISRC2", 16, 23, &umr_bitfield_default },
	 { "AFMT_UPC_EAN_ISRC3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmAFMT_ISRC1_2[] = {
	 { "AFMT_UPC_EAN_ISRC4", 0, 7, &umr_bitfield_default },
	 { "AFMT_UPC_EAN_ISRC5", 8, 15, &umr_bitfield_default },
	 { "AFMT_UPC_EAN_ISRC6", 16, 23, &umr_bitfield_default },
	 { "AFMT_UPC_EAN_ISRC7", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmAFMT_ISRC1_3[] = {
	 { "AFMT_UPC_EAN_ISRC10", 16, 23, &umr_bitfield_default },
	 { "AFMT_UPC_EAN_ISRC11", 24, 31, &umr_bitfield_default },
	 { "AFMT_UPC_EAN_ISRC8", 0, 7, &umr_bitfield_default },
	 { "AFMT_UPC_EAN_ISRC9", 8, 15, &umr_bitfield_default },
};
static struct umr_bitfield mmAFMT_ISRC1_4[] = {
	 { "AFMT_UPC_EAN_ISRC12", 0, 7, &umr_bitfield_default },
	 { "AFMT_UPC_EAN_ISRC13", 8, 15, &umr_bitfield_default },
	 { "AFMT_UPC_EAN_ISRC14", 16, 23, &umr_bitfield_default },
	 { "AFMT_UPC_EAN_ISRC15", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmAFMT_ISRC2_0[] = {
	 { "AFMT_UPC_EAN_ISRC16", 0, 7, &umr_bitfield_default },
	 { "AFMT_UPC_EAN_ISRC17", 8, 15, &umr_bitfield_default },
	 { "AFMT_UPC_EAN_ISRC18", 16, 23, &umr_bitfield_default },
	 { "AFMT_UPC_EAN_ISRC19", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmAFMT_ISRC2_1[] = {
	 { "AFMT_UPC_EAN_ISRC20", 0, 7, &umr_bitfield_default },
	 { "AFMT_UPC_EAN_ISRC21", 8, 15, &umr_bitfield_default },
	 { "AFMT_UPC_EAN_ISRC22", 16, 23, &umr_bitfield_default },
	 { "AFMT_UPC_EAN_ISRC23", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmAFMT_ISRC2_2[] = {
	 { "AFMT_UPC_EAN_ISRC24", 0, 7, &umr_bitfield_default },
	 { "AFMT_UPC_EAN_ISRC25", 8, 15, &umr_bitfield_default },
	 { "AFMT_UPC_EAN_ISRC26", 16, 23, &umr_bitfield_default },
	 { "AFMT_UPC_EAN_ISRC27", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmAFMT_ISRC2_3[] = {
	 { "AFMT_UPC_EAN_ISRC28", 0, 7, &umr_bitfield_default },
	 { "AFMT_UPC_EAN_ISRC29", 8, 15, &umr_bitfield_default },
	 { "AFMT_UPC_EAN_ISRC30", 16, 23, &umr_bitfield_default },
	 { "AFMT_UPC_EAN_ISRC31", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmAFMT_AVI_INFO0[] = {
	 { "AFMT_AVI_INFO_A", 12, 12, &umr_bitfield_default },
	 { "AFMT_AVI_INFO_B", 10, 11, &umr_bitfield_default },
	 { "AFMT_AVI_INFO_CHECKSUM", 0, 7, &umr_bitfield_default },
	 { "AFMT_AVI_INFO_C", 22, 23, &umr_bitfield_default },
	 { "AFMT_AVI_INFO_EC", 28, 30, &umr_bitfield_default },
	 { "AFMT_AVI_INFO_ITC", 31, 31, &umr_bitfield_default },
	 { "AFMT_AVI_INFO_M", 20, 21, &umr_bitfield_default },
	 { "AFMT_AVI_INFO_PB1_RSVD", 15, 15, &umr_bitfield_default },
	 { "AFMT_AVI_INFO_Q", 26, 27, &umr_bitfield_default },
	 { "AFMT_AVI_INFO_R", 16, 19, &umr_bitfield_default },
	 { "AFMT_AVI_INFO_SC", 24, 25, &umr_bitfield_default },
	 { "AFMT_AVI_INFO_S", 8, 9, &umr_bitfield_default },
	 { "AFMT_AVI_INFO_Y", 13, 14, &umr_bitfield_default },
};
static struct umr_bitfield mmAFMT_AVI_INFO1[] = {
	 { "AFMT_AVI_INFO_CN", 12, 13, &umr_bitfield_default },
	 { "AFMT_AVI_INFO_PB4_RSVD", 7, 7, &umr_bitfield_default },
	 { "AFMT_AVI_INFO_PR", 8, 11, &umr_bitfield_default },
	 { "AFMT_AVI_INFO_TOP", 16, 31, &umr_bitfield_default },
	 { "AFMT_AVI_INFO_VIC", 0, 6, &umr_bitfield_default },
	 { "AFMT_AVI_INFO_YQ", 14, 15, &umr_bitfield_default },
};
static struct umr_bitfield mmAFMT_AVI_INFO2[] = {
	 { "AFMT_AVI_INFO_BOTTOM", 0, 15, &umr_bitfield_default },
	 { "AFMT_AVI_INFO_LEFT", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmAFMT_AVI_INFO3[] = {
	 { "AFMT_AVI_INFO_RIGHT", 0, 15, &umr_bitfield_default },
	 { "AFMT_AVI_INFO_VERSION", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmAFMT_MPEG_INFO0[] = {
	 { "AFMT_MPEG_INFO_CHECKSUM", 0, 7, &umr_bitfield_default },
	 { "AFMT_MPEG_INFO_MB0", 8, 15, &umr_bitfield_default },
	 { "AFMT_MPEG_INFO_MB1", 16, 23, &umr_bitfield_default },
	 { "AFMT_MPEG_INFO_MB2", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmAFMT_MPEG_INFO1[] = {
	 { "AFMT_MPEG_INFO_FR", 12, 12, &umr_bitfield_default },
	 { "AFMT_MPEG_INFO_MB3", 0, 7, &umr_bitfield_default },
	 { "AFMT_MPEG_INFO_MF", 8, 9, &umr_bitfield_default },
};
static struct umr_bitfield mmAFMT_GENERIC_HDR[] = {
	 { "AFMT_GENERIC_HB0", 0, 7, &umr_bitfield_default },
	 { "AFMT_GENERIC_HB1", 8, 15, &umr_bitfield_default },
	 { "AFMT_GENERIC_HB2", 16, 23, &umr_bitfield_default },
	 { "AFMT_GENERIC_HB3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmAFMT_GENERIC_0[] = {
	 { "AFMT_GENERIC_BYTE0", 0, 7, &umr_bitfield_default },
	 { "AFMT_GENERIC_BYTE1", 8, 15, &umr_bitfield_default },
	 { "AFMT_GENERIC_BYTE2", 16, 23, &umr_bitfield_default },
	 { "AFMT_GENERIC_BYTE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmAFMT_GENERIC_1[] = {
	 { "AFMT_GENERIC_BYTE4", 0, 7, &umr_bitfield_default },
	 { "AFMT_GENERIC_BYTE5", 8, 15, &umr_bitfield_default },
	 { "AFMT_GENERIC_BYTE6", 16, 23, &umr_bitfield_default },
	 { "AFMT_GENERIC_BYTE7", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmAFMT_GENERIC_2[] = {
	 { "AFMT_GENERIC_BYTE10", 16, 23, &umr_bitfield_default },
	 { "AFMT_GENERIC_BYTE11", 24, 31, &umr_bitfield_default },
	 { "AFMT_GENERIC_BYTE8", 0, 7, &umr_bitfield_default },
	 { "AFMT_GENERIC_BYTE9", 8, 15, &umr_bitfield_default },
};
static struct umr_bitfield mmAFMT_GENERIC_3[] = {
	 { "AFMT_GENERIC_BYTE12", 0, 7, &umr_bitfield_default },
	 { "AFMT_GENERIC_BYTE13", 8, 15, &umr_bitfield_default },
	 { "AFMT_GENERIC_BYTE14", 16, 23, &umr_bitfield_default },
	 { "AFMT_GENERIC_BYTE15", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmAFMT_GENERIC_4[] = {
	 { "AFMT_GENERIC_BYTE16", 0, 7, &umr_bitfield_default },
	 { "AFMT_GENERIC_BYTE17", 8, 15, &umr_bitfield_default },
	 { "AFMT_GENERIC_BYTE18", 16, 23, &umr_bitfield_default },
	 { "AFMT_GENERIC_BYTE19", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmAFMT_GENERIC_5[] = {
	 { "AFMT_GENERIC_BYTE20", 0, 7, &umr_bitfield_default },
	 { "AFMT_GENERIC_BYTE21", 8, 15, &umr_bitfield_default },
	 { "AFMT_GENERIC_BYTE22", 16, 23, &umr_bitfield_default },
	 { "AFMT_GENERIC_BYTE23", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmAFMT_GENERIC_6[] = {
	 { "AFMT_GENERIC_BYTE24", 0, 7, &umr_bitfield_default },
	 { "AFMT_GENERIC_BYTE25", 8, 15, &umr_bitfield_default },
	 { "AFMT_GENERIC_BYTE26", 16, 23, &umr_bitfield_default },
	 { "AFMT_GENERIC_BYTE27", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmAFMT_GENERIC_7[] = {
	 { "AFMT_GENERIC_BYTE28", 0, 7, &umr_bitfield_default },
	 { "AFMT_GENERIC_BYTE29", 8, 15, &umr_bitfield_default },
	 { "AFMT_GENERIC_BYTE30", 16, 23, &umr_bitfield_default },
	 { "AFMT_GENERIC_BYTE31", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmAFMT_AUDIO_INFO0[] = {
	 { "AFMT_AUDIO_INFO_CC", 8, 10, &umr_bitfield_default },
	 { "AFMT_AUDIO_INFO_CHECKSUM", 0, 7, &umr_bitfield_default },
	 { "AFMT_AUDIO_INFO_CHECKSUM_OFFSET", 16, 23, &umr_bitfield_default },
	 { "AFMT_AUDIO_INFO_CT", 11, 14, &umr_bitfield_default },
	 { "AFMT_AUDIO_INFO_CXT", 24, 28, &umr_bitfield_default },
};
static struct umr_bitfield mmAFMT_AUDIO_INFO1[] = {
	 { "AFMT_AUDIO_INFO_CA", 0, 7, &umr_bitfield_default },
	 { "AFMT_AUDIO_INFO_DM_INH", 15, 15, &umr_bitfield_default },
	 { "AFMT_AUDIO_INFO_LFEPBL", 16, 17, &umr_bitfield_default },
	 { "AFMT_AUDIO_INFO_LSV", 11, 14, &umr_bitfield_default },
};
static struct umr_bitfield mmAFMT_60958_0[] = {
	 { "AFMT_60958_CS_A", 0, 0, &umr_bitfield_default },
	 { "AFMT_60958_CS_B", 1, 1, &umr_bitfield_default },
	 { "AFMT_60958_CS_CATEGORY_CODE", 8, 15, &umr_bitfield_default },
	 { "AFMT_60958_CS_CHANNEL_NUMBER_L", 20, 23, &umr_bitfield_default },
	 { "AFMT_60958_CS_CLOCK_ACCURACY", 28, 29, &umr_bitfield_default },
	 { "AFMT_60958_CS_C", 2, 2, &umr_bitfield_default },
	 { "AFMT_60958_CS_D", 3, 5, &umr_bitfield_default },
	 { "AFMT_60958_CS_MODE", 6, 7, &umr_bitfield_default },
	 { "AFMT_60958_CS_SAMPLING_FREQUENCY", 24, 27, &umr_bitfield_default },
	 { "AFMT_60958_CS_SOURCE_NUMBER", 16, 19, &umr_bitfield_default },
};
static struct umr_bitfield mmAFMT_60958_1[] = {
	 { "AFMT_60958_CS_CHANNEL_NUMBER_R", 20, 23, &umr_bitfield_default },
	 { "AFMT_60958_CS_ORIGINAL_SAMPLING_FREQUENCY", 4, 7, &umr_bitfield_default },
	 { "AFMT_60958_CS_WORD_LENGTH", 0, 3, &umr_bitfield_default },
	 { "AFMT_60958_VALID_L", 16, 16, &umr_bitfield_default },
	 { "AFMT_60958_VALID_R", 18, 18, &umr_bitfield_default },
};
static struct umr_bitfield mmAFMT_AUDIO_CRC_CONTROL[] = {
	 { "AFMT_AUDIO_CRC_CH_SEL", 12, 15, &umr_bitfield_default },
	 { "AFMT_AUDIO_CRC_CONT", 4, 4, &umr_bitfield_default },
	 { "AFMT_AUDIO_CRC_COUNT", 16, 31, &umr_bitfield_default },
	 { "AFMT_AUDIO_CRC_EN", 0, 0, &umr_bitfield_default },
	 { "AFMT_AUDIO_CRC_SOURCE", 8, 8, &umr_bitfield_default },
};
static struct umr_bitfield mmAFMT_RAMP_CONTROL0[] = {
	 { "AFMT_RAMP_DATA_SIGN", 31, 31, &umr_bitfield_default },
	 { "AFMT_RAMP_MAX_COUNT", 0, 23, &umr_bitfield_default },
};
static struct umr_bitfield mmAFMT_RAMP_CONTROL1[] = {
	 { "AFMT_AUDIO_TEST_CH_DISABLE", 24, 31, &umr_bitfield_default },
	 { "AFMT_RAMP_MIN_COUNT", 0, 23, &umr_bitfield_default },
};
static struct umr_bitfield mmAFMT_RAMP_CONTROL2[] = {
	 { "AFMT_RAMP_INC_COUNT", 0, 23, &umr_bitfield_default },
};
static struct umr_bitfield mmAFMT_RAMP_CONTROL3[] = {
	 { "AFMT_RAMP_DEC_COUNT", 0, 23, &umr_bitfield_default },
};
static struct umr_bitfield mmAFMT_60958_2[] = {
	 { "AFMT_60958_CS_CHANNEL_NUMBER_2", 0, 3, &umr_bitfield_default },
	 { "AFMT_60958_CS_CHANNEL_NUMBER_3", 4, 7, &umr_bitfield_default },
	 { "AFMT_60958_CS_CHANNEL_NUMBER_4", 8, 11, &umr_bitfield_default },
	 { "AFMT_60958_CS_CHANNEL_NUMBER_5", 12, 15, &umr_bitfield_default },
	 { "AFMT_60958_CS_CHANNEL_NUMBER_6", 16, 19, &umr_bitfield_default },
	 { "AFMT_60958_CS_CHANNEL_NUMBER_7", 20, 23, &umr_bitfield_default },
};
static struct umr_bitfield mmAFMT_AUDIO_CRC_RESULT[] = {
	 { "AFMT_AUDIO_CRC_DONE", 0, 0, &umr_bitfield_default },
	 { "AFMT_AUDIO_CRC", 8, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmAFMT_STATUS[] = {
	 { "AFMT_AUDIO_ENABLE", 4, 4, &umr_bitfield_default },
	 { "AFMT_AUDIO_FIFO_OVERFLOW", 24, 24, &umr_bitfield_default },
	 { "AFMT_AZ_AUDIO_ENABLE_CHG", 30, 30, &umr_bitfield_default },
	 { "AFMT_AZ_HBR_ENABLE", 8, 8, &umr_bitfield_default },
};
static struct umr_bitfield mmAFMT_AUDIO_PACKET_CONTROL[] = {
	 { "AFMT_60958_CS_UPDATE", 26, 26, &umr_bitfield_default },
	 { "AFMT_AUDIO_CHANNEL_SWAP", 24, 24, &umr_bitfield_default },
	 { "AFMT_AUDIO_FIFO_OVERFLOW_ACK", 23, 23, &umr_bitfield_default },
	 { "AFMT_AUDIO_SAMPLE_SEND", 0, 0, &umr_bitfield_default },
	 { "AFMT_AUDIO_TEST_EN", 12, 12, &umr_bitfield_default },
	 { "AFMT_AUDIO_TEST_MODE", 14, 14, &umr_bitfield_default },
	 { "AFMT_AZ_AUDIO_ENABLE_CHG_ACK", 30, 30, &umr_bitfield_default },
	 { "AFMT_BLANK_TEST_DATA_ON_ENC_ENB", 31, 31, &umr_bitfield_default },
	 { "AFMT_RESET_FIFO_WHEN_AUDIO_DIS", 11, 11, &umr_bitfield_default },
};
static struct umr_bitfield mmAFMT_VBI_PACKET_CONTROL[] = {
	 { "AFMT_GENERIC0_UPDATE", 2, 2, &umr_bitfield_default },
	 { "AFMT_GENERIC2_UPDATE", 3, 3, &umr_bitfield_default },
	 { "AFMT_GENERIC_INDEX", 30, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmAFMT_INFOFRAME_CONTROL0[] = {
	 { "AFMT_AUDIO_INFO_SOURCE", 6, 6, &umr_bitfield_default },
	 { "AFMT_AUDIO_INFO_UPDATE", 7, 7, &umr_bitfield_default },
	 { "AFMT_MPEG_INFO_UPDATE", 10, 10, &umr_bitfield_default },
};
static struct umr_bitfield mmAFMT_AUDIO_SRC_CONTROL[] = {
	 { "AFMT_AUDIO_SRC_SELECT", 0, 2, &umr_bitfield_default },
};
static struct umr_bitfield mmAFMT_AUDIO_DBG_DTO_CNTL[] = {
	 { "AFMT_AUDIO_DTO_DBG_BASE", 8, 8, &umr_bitfield_default },
	 { "AFMT_AUDIO_DTO_DBG_DIV", 16, 18, &umr_bitfield_default },
	 { "AFMT_AUDIO_DTO_DBG_MULTI", 12, 14, &umr_bitfield_default },
	 { "AFMT_AUDIO_DTO_FS_DIV_SEL", 0, 2, &umr_bitfield_default },
};
static struct umr_bitfield ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_SUBORDINATE_NODE_COUNT[] = {
	 { "AZALIA_CODEC_FUNCTION_PARAMETER_SUBORDINATE_NODE_COUNT", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_GROUP_TYPE[] = {
	 { "AZALIA_CODEC_FUNCTION_PARAMETER_GROUP_TYPE", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES[] = {
	 { "AUDIO_BIT_CAPABILITIES", 16, 20, &umr_bitfield_default },
	 { "AUDIO_RATE_CAPABILITIES", 0, 11, &umr_bitfield_default },
};
static struct umr_bitfield ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS[] = {
	 { "AZALIA_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES[] = {
	 { "AZALIA_CODEC_FUNCTION_PARAMETER_POWER_STATES", 0, 29, &umr_bitfield_default },
	 { "CLKSTOP", 30, 30, &umr_bitfield_default },
	 { "EPSS", 31, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixAZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT[] = {
	 { "BITS_PER_SAMPLE", 4, 6, &umr_bitfield_default },
	 { "NUMBER_OF_CHANNELS", 0, 3, &umr_bitfield_default },
	 { "SAMPLE_BASE_DIVISOR", 8, 10, &umr_bitfield_default },
	 { "SAMPLE_BASE_MULTIPLE", 11, 13, &umr_bitfield_default },
	 { "SAMPLE_BASE_RATE", 14, 14, &umr_bitfield_default },
	 { "STREAM_TYPE", 15, 15, &umr_bitfield_default },
	 { "STREAM_TYPE_R", 15, 15, &umr_bitfield_default },
};
static struct umr_bitfield ixAZALIA_F2_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID[] = {
	 { "CHANNEL_ID", 0, 3, &umr_bitfield_default },
	 { "STREAM_ID", 4, 7, &umr_bitfield_default },
};
static struct umr_bitfield ixAZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER[] = {
	 { "CC", 8, 14, &umr_bitfield_default },
	 { "COPY", 4, 4, &umr_bitfield_default },
	 { "DIGEN", 0, 0, &umr_bitfield_default },
	 { "KEEPALIVE", 23, 23, &umr_bitfield_default },
	 { "L", 7, 7, &umr_bitfield_default },
	 { "NON_AUDIO", 5, 5, &umr_bitfield_default },
	 { "PRE", 3, 3, &umr_bitfield_default },
	 { "PRO", 6, 6, &umr_bitfield_default },
	 { "VCFG", 2, 2, &umr_bitfield_default },
	 { "V", 1, 1, &umr_bitfield_default },
};
static struct umr_bitfield ixAZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_2[] = {
	 { "CC", 0, 6, &umr_bitfield_default },
};
static struct umr_bitfield ixAZALIA_F2_CODEC_CONVERTER_STRIPE_CONTROL[] = {
	 { "STRIPE_CAPABILITY", 20, 22, &umr_bitfield_default },
	 { "STRIPE_CONTROL", 0, 1, &umr_bitfield_default },
};
static struct umr_bitfield ixAZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3[] = {
	 { "KEEPALIVE", 7, 7, &umr_bitfield_default },
};
static struct umr_bitfield ixAZALIA_F2_CODEC_CONVERTER_CONTROL_RAMP_RATE[] = {
	 { "RAMP_RATE", 0, 7, &umr_bitfield_default },
};
static struct umr_bitfield ixAZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES[] = {
	 { "AMPLIFIER_PARAMETER_OVERRIDE", 3, 3, &umr_bitfield_default },
	 { "AUDIO_CHANNEL_CAPABILITIES", 0, 0, &umr_bitfield_default },
	 { "AUDIO_WIDGET_CAPABILITIES_DELAY", 16, 19, &umr_bitfield_default },
	 { "CONNECTION_LIST", 8, 8, &umr_bitfield_default },
	 { "DIGITAL", 9, 9, &umr_bitfield_default },
	 { "FORMAT_OVERRIDE", 4, 4, &umr_bitfield_default },
	 { "INPUT_AMPLIFIER_PRESENT", 1, 1, &umr_bitfield_default },
	 { "LR_SWAP", 11, 11, &umr_bitfield_default },
	 { "OUTPUT_AMPLIFIER_PRESENT", 2, 2, &umr_bitfield_default },
	 { "POWER_CONTROL", 10, 10, &umr_bitfield_default },
	 { "PROCESSING_WIDGET", 6, 6, &umr_bitfield_default },
	 { "STRIPE", 5, 5, &umr_bitfield_default },
	 { "TYPE", 20, 23, &umr_bitfield_default },
	 { "UNSOLICITED_RESPONSE_CAPABILITY", 7, 7, &umr_bitfield_default },
};
static struct umr_bitfield ixAZALIA_F2_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES[] = {
	 { "AUDIO_BIT_CAPABILITIES", 16, 20, &umr_bitfield_default },
	 { "AUDIO_RATE_CAPABILITIES", 0, 11, &umr_bitfield_default },
};
static struct umr_bitfield ixAZALIA_F2_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS[] = {
	 { "STREAM_FORMATS", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONNECTION_LIST_ENTRY[] = {
	 { "CONNECTION_LIST_ENTRY", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixAZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL[] = {
	 { "OUT_ENABLE", 6, 6, &umr_bitfield_default },
};
static struct umr_bitfield ixAZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE[] = {
	 { "ENABLE", 7, 7, &umr_bitfield_default },
	 { "TAG", 0, 5, &umr_bitfield_default },
};
static struct umr_bitfield ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE[] = {
	 { "IMPEDANCE_SENSE", 0, 30, &umr_bitfield_default },
	 { "PRESENCE_DETECT", 31, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT[] = {
	 { "COLOR", 12, 15, &umr_bitfield_default },
	 { "CONNECTION_TYPE", 16, 19, &umr_bitfield_default },
	 { "DEFAULT_ASSOCIATION", 4, 7, &umr_bitfield_default },
	 { "DEFAULT_DEVICE", 20, 23, &umr_bitfield_default },
	 { "LOCATION", 24, 29, &umr_bitfield_default },
	 { "MISC", 8, 11, &umr_bitfield_default },
	 { "PORT_CONNECTIVITY", 30, 31, &umr_bitfield_default },
	 { "SEQUENCE", 0, 3, &umr_bitfield_default },
};
static struct umr_bitfield ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2[] = {
	 { "COLOR", 4, 7, &umr_bitfield_default },
	 { "MISC", 0, 3, &umr_bitfield_default },
};
static struct umr_bitfield ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3[] = {
	 { "CONNECTION_TYPE", 0, 3, &umr_bitfield_default },
	 { "DEFAULT_DEVICE", 4, 7, &umr_bitfield_default },
};
static struct umr_bitfield ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4[] = {
	 { "LOCATION", 0, 5, &umr_bitfield_default },
	 { "PORT_CONNECTIVITY", 6, 7, &umr_bitfield_default },
};
static struct umr_bitfield ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION[] = {
	 { "DP_CONNECTION", 9, 9, &umr_bitfield_default },
	 { "EXTRA_CONNECTION_INFO", 10, 15, &umr_bitfield_default },
	 { "HDMI_CONNECTION", 8, 8, &umr_bitfield_default },
	 { "SPEAKER_ALLOCATION", 0, 6, &umr_bitfield_default },
};
static struct umr_bitfield ixAZALIA_F2_CODEC_PIN_CONTROL_CHANNEL_ALLOCATION[] = {
	 { "CHANNEL_ALLOCATION", 0, 7, &umr_bitfield_default },
};
static struct umr_bitfield ixAZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO[] = {
	 { "DOWN_MIX_INHIBIT", 7, 7, &umr_bitfield_default },
	 { "LEVEL_SHIFT", 3, 6, &umr_bitfield_default },
};
static struct umr_bitfield ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR[] = {
	 { "DESCRIPTOR_BYTE_2", 16, 23, &umr_bitfield_default },
	 { "FORMAT_CODE", 3, 6, &umr_bitfield_default },
	 { "MAX_CHANNELS", 0, 2, &umr_bitfield_default },
	 { "SUPPORTED_FREQUENCIES", 8, 15, &umr_bitfield_default },
	 { "SUPPORTED_FREQUENCIES_STEREO", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE[] = {
	 { "MULTICHANNEL01_CHANNEL_ID", 4, 7, &umr_bitfield_default },
	 { "MULTICHANNEL01_ENABLE", 0, 0, &umr_bitfield_default },
	 { "MULTICHANNEL01_MUTE", 1, 1, &umr_bitfield_default },
};
static struct umr_bitfield ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE[] = {
	 { "MULTICHANNEL23_CHANNEL_ID", 4, 7, &umr_bitfield_default },
	 { "MULTICHANNEL23_ENABLE", 0, 0, &umr_bitfield_default },
	 { "MULTICHANNEL23_MUTE", 1, 1, &umr_bitfield_default },
};
static struct umr_bitfield ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE[] = {
	 { "MULTICHANNEL45_CHANNEL_ID", 4, 7, &umr_bitfield_default },
	 { "MULTICHANNEL45_ENABLE", 0, 0, &umr_bitfield_default },
	 { "MULTICHANNEL45_MUTE", 1, 1, &umr_bitfield_default },
};
static struct umr_bitfield ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE[] = {
	 { "MULTICHANNEL67_CHANNEL_ID", 4, 7, &umr_bitfield_default },
	 { "MULTICHANNEL67_ENABLE", 0, 0, &umr_bitfield_default },
	 { "MULTICHANNEL67_MUTE", 1, 1, &umr_bitfield_default },
};
static struct umr_bitfield ixAZALIA_F2_CODEC_PIN_CONTROL_LIPSYNC[] = {
	 { "AUDIO_LIPSYNC", 8, 15, &umr_bitfield_default },
	 { "VIDEO_LIPSYNC", 0, 7, &umr_bitfield_default },
};
static struct umr_bitfield ixAZALIA_F2_CODEC_PIN_CONTROL_HBR[] = {
	 { "HBR_CAPABLE", 0, 0, &umr_bitfield_default },
	 { "HBR_ENABLE", 4, 4, &umr_bitfield_default },
};
static struct umr_bitfield ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_INDEX[] = {
	 { "SINK_INFO_INDEX", 0, 7, &umr_bitfield_default },
};
static struct umr_bitfield ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_DATA[] = {
	 { "SINK_DATA", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE[] = {
	 { "MULTICHANNEL1_CHANNEL_ID", 4, 7, &umr_bitfield_default },
	 { "MULTICHANNEL1_ENABLE", 0, 0, &umr_bitfield_default },
	 { "MULTICHANNEL1_MUTE", 1, 1, &umr_bitfield_default },
};
static struct umr_bitfield ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE[] = {
	 { "MULTICHANNEL3_CHANNEL_ID", 4, 7, &umr_bitfield_default },
	 { "MULTICHANNEL3_ENABLE", 0, 0, &umr_bitfield_default },
	 { "MULTICHANNEL3_MUTE", 1, 1, &umr_bitfield_default },
};
static struct umr_bitfield ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE[] = {
	 { "MULTICHANNEL5_CHANNEL_ID", 4, 7, &umr_bitfield_default },
	 { "MULTICHANNEL5_ENABLE", 0, 0, &umr_bitfield_default },
	 { "MULTICHANNEL5_MUTE", 1, 1, &umr_bitfield_default },
};
static struct umr_bitfield ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE[] = {
	 { "MULTICHANNEL7_CHANNEL_ID", 4, 7, &umr_bitfield_default },
	 { "MULTICHANNEL7_ENABLE", 0, 0, &umr_bitfield_default },
	 { "MULTICHANNEL7_MUTE", 1, 1, &umr_bitfield_default },
};
static struct umr_bitfield ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE[] = {
	 { "MULTICHANNEL_MODE", 0, 0, &umr_bitfield_default },
};
static struct umr_bitfield ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_0[] = {
	 { "IEC_60958_CS_MODE", 0, 1, &umr_bitfield_default },
	 { "IEC_60958_CS_SOURCE_NUMBER", 2, 5, &umr_bitfield_default },
};
static struct umr_bitfield ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1[] = {
	 { "IEC_60958_CS_CLOCK_ACCURACY", 0, 1, &umr_bitfield_default },
	 { "IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN", 2, 2, &umr_bitfield_default },
	 { "IEC_60958_CS_WORD_LENGTH", 3, 6, &umr_bitfield_default },
	 { "IEC_60958_CS_WORD_LENGTH_OVRRD_EN", 7, 7, &umr_bitfield_default },
};
static struct umr_bitfield ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_2[] = {
	 { "IEC_60958_CS_SAMPLING_FREQUENCY", 0, 5, &umr_bitfield_default },
	 { "IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN", 6, 6, &umr_bitfield_default },
};
static struct umr_bitfield ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_3[] = {
	 { "IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY", 0, 3, &umr_bitfield_default },
	 { "IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN", 4, 4, &umr_bitfield_default },
};
static struct umr_bitfield ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4[] = {
	 { "IEC_60958_CS_CGMS_A", 5, 6, &umr_bitfield_default },
	 { "IEC_60958_CS_CGMS_A_VALID", 7, 7, &umr_bitfield_default },
	 { "IEC_60958_CS_MPEG_SURROUND_INFO", 4, 4, &umr_bitfield_default },
	 { "IEC_60958_CS_SAMPLING_FREQUENCY_COEFF", 0, 3, &umr_bitfield_default },
};
static struct umr_bitfield ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_5[] = {
	 { "IEC_60958_CS_CHANNEL_NUMBER_L", 0, 3, &umr_bitfield_default },
	 { "IEC_60958_CS_CHANNEL_NUMBER_R", 4, 7, &umr_bitfield_default },
};
static struct umr_bitfield ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_6[] = {
	 { "IEC_60958_CS_CHANNEL_NUMBER_2", 0, 3, &umr_bitfield_default },
	 { "IEC_60958_CS_CHANNEL_NUMBER_3", 4, 7, &umr_bitfield_default },
};
static struct umr_bitfield ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_7[] = {
	 { "IEC_60958_CS_CHANNEL_NUMBER_4", 0, 3, &umr_bitfield_default },
	 { "IEC_60958_CS_CHANNEL_NUMBER_5", 4, 7, &umr_bitfield_default },
};
static struct umr_bitfield ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_8[] = {
	 { "IEC_60958_CS_CHANNEL_NUMBER_6", 0, 3, &umr_bitfield_default },
	 { "IEC_60958_CS_CHANNEL_NUMBER_7", 4, 7, &umr_bitfield_default },
};
static struct umr_bitfield ixAZALIA_F2_CODEC_PIN_ASSOCIATION_INFO[] = {
	 { "ASSOCIATION_INFO", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixAZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES[] = {
	 { "AMPLIFIER_PARAMETER_OVERRIDE", 3, 3, &umr_bitfield_default },
	 { "AUDIO_CHANNEL_CAPABILITIES", 0, 0, &umr_bitfield_default },
	 { "AUDIO_WIDGET_CAPABILITIES_DELAY", 16, 19, &umr_bitfield_default },
	 { "CONNECTION_LIST", 8, 8, &umr_bitfield_default },
	 { "DIGITAL", 9, 9, &umr_bitfield_default },
	 { "INPUT_AMPLIFIER_PRESENT", 1, 1, &umr_bitfield_default },
	 { "LR_SWAP", 11, 11, &umr_bitfield_default },
	 { "OUTPUT_AMPLIFIER_PRESENT", 2, 2, &umr_bitfield_default },
	 { "POWER_CONTROL", 10, 10, &umr_bitfield_default },
	 { "PROCESSING_WIDGET", 6, 6, &umr_bitfield_default },
	 { "STRIPE", 5, 5, &umr_bitfield_default },
	 { "TYPE", 20, 23, &umr_bitfield_default },
	 { "UNSOLICITED_RESPONSE_CAPABILITY", 7, 7, &umr_bitfield_default },
};
static struct umr_bitfield ixAZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES[] = {
	 { "BALANCED_I_O_PINS", 6, 6, &umr_bitfield_default },
	 { "DP", 24, 24, &umr_bitfield_default },
	 { "EAPD_CAPABLE", 16, 16, &umr_bitfield_default },
	 { "HDMI", 7, 7, &umr_bitfield_default },
	 { "HEADPHONE_DRIVE_CAPABLE", 3, 3, &umr_bitfield_default },
	 { "IMPEDANCE_SENSE_CAPABLE", 0, 0, &umr_bitfield_default },
	 { "INPUT_CAPABLE", 5, 5, &umr_bitfield_default },
	 { "JACK_DETECTION_CAPABILITY", 2, 2, &umr_bitfield_default },
	 { "OUTPUT_CAPABLE", 4, 4, &umr_bitfield_default },
	 { "TRIGGER_REQUIRED", 1, 1, &umr_bitfield_default },
	 { "VREF_CONTROL", 8, 15, &umr_bitfield_default },
};
static struct umr_bitfield ixAZALIA_F2_CODEC_PIN_PARAMETER_CONNECTION_LIST_LENGTH[] = {
	 { "CONNECTION_LIST_LENGTH", 0, 31, &umr_bitfield_default },
};