static struct umr_bitfield mmVGA_MEM_WRITE_PAGE_ADDR[] = {
	 { "VGA_MEM_WRITE_PAGE0_ADDR", 0, 9, &umr_bitfield_default },
	 { "VGA_MEM_WRITE_PAGE1_ADDR", 16, 25, &umr_bitfield_default },
};
static struct umr_bitfield mmVGA_MEM_READ_PAGE_ADDR[] = {
	 { "VGA_MEM_READ_PAGE0_ADDR", 0, 9, &umr_bitfield_default },
	 { "VGA_MEM_READ_PAGE1_ADDR", 16, 25, &umr_bitfield_default },
};
static struct umr_bitfield mmCRTC8_IDX[] = {
	 { "VCRTC_IDX", 0, 5, &umr_bitfield_default },
};
static struct umr_bitfield mmCRTC8_DATA[] = {
	 { "VCRTC_DATA", 0, 7, &umr_bitfield_default },
};
static struct umr_bitfield mmGENFC_WT[] = {
	 { "VSYNC_SEL_W", 3, 3, &umr_bitfield_default },
};
static struct umr_bitfield mmGENS1[] = {
	 { "NO_DISPLAY", 0, 0, &umr_bitfield_default },
	 { "VGA_VSTATUS", 3, 3, &umr_bitfield_default },
	 { "PIXEL_READ_BACK", 4, 5, &umr_bitfield_default },
};
static struct umr_bitfield mmATTRDW[] = {
	 { "ATTR_DATA", 0, 7, &umr_bitfield_default },
};
static struct umr_bitfield mmATTRX[] = {
	 { "ATTR_IDX", 0, 4, &umr_bitfield_default },
	 { "ATTR_PAL_RW_ENB", 5, 5, &umr_bitfield_default },
};
static struct umr_bitfield mmATTRDR[] = {
	 { "ATTR_DATA", 0, 7, &umr_bitfield_default },
};
static struct umr_bitfield mmGENMO_WT[] = {
	 { "GENMO_MONO_ADDRESS_B", 0, 0, &umr_bitfield_default },
	 { "VGA_RAM_EN", 1, 1, &umr_bitfield_default },
	 { "VGA_CKSEL", 2, 3, &umr_bitfield_default },
	 { "ODD_EVEN_MD_PGSEL", 5, 5, &umr_bitfield_default },
	 { "VGA_HSYNC_POL", 6, 6, &umr_bitfield_default },
	 { "VGA_VSYNC_POL", 7, 7, &umr_bitfield_default },
};
static struct umr_bitfield mmGENS0[] = {
	 { "SENSE_SWITCH", 4, 4, &umr_bitfield_default },
	 { "CRT_INTR", 7, 7, &umr_bitfield_default },
};
static struct umr_bitfield mmGENENB[] = {
	 { "BLK_IO_BASE", 0, 7, &umr_bitfield_default },
};
static struct umr_bitfield mmSEQ8_IDX[] = {
	 { "SEQ_IDX", 0, 2, &umr_bitfield_default },
};
static struct umr_bitfield mmSEQ8_DATA[] = {
	 { "SEQ_DATA", 0, 7, &umr_bitfield_default },
};
static struct umr_bitfield mmDAC_MASK[] = {
	 { "DAC_MASK", 0, 7, &umr_bitfield_default },
};
static struct umr_bitfield mmDAC_R_INDEX[] = {
	 { "DAC_R_INDEX", 0, 7, &umr_bitfield_default },
};
static struct umr_bitfield mmDAC_W_INDEX[] = {
	 { "DAC_W_INDEX", 0, 7, &umr_bitfield_default },
};
static struct umr_bitfield mmDAC_DATA[] = {
	 { "DAC_DATA", 0, 5, &umr_bitfield_default },
};
static struct umr_bitfield mmGENFC_RD[] = {
	 { "VSYNC_SEL_R", 3, 3, &umr_bitfield_default },
};
static struct umr_bitfield mmGENMO_RD[] = {
	 { "GENMO_MONO_ADDRESS_B", 0, 0, &umr_bitfield_default },
	 { "VGA_RAM_EN", 1, 1, &umr_bitfield_default },
	 { "VGA_CKSEL", 2, 3, &umr_bitfield_default },
	 { "ODD_EVEN_MD_PGSEL", 5, 5, &umr_bitfield_default },
	 { "VGA_HSYNC_POL", 6, 6, &umr_bitfield_default },
	 { "VGA_VSYNC_POL", 7, 7, &umr_bitfield_default },
};
static struct umr_bitfield mmGRPH8_IDX[] = {
	 { "GRPH_IDX", 0, 3, &umr_bitfield_default },
};
static struct umr_bitfield mmGRPH8_DATA[] = {
	 { "GRPH_DATA", 0, 7, &umr_bitfield_default },
};
static struct umr_bitfield mmCRTC8_IDX_1[] = {
	 { "VCRTC_IDX", 0, 5, &umr_bitfield_default },
};
static struct umr_bitfield mmCRTC8_DATA_1[] = {
	 { "VCRTC_DATA", 0, 7, &umr_bitfield_default },
};
static struct umr_bitfield mmGENFC_WT_1[] = {
	 { "VSYNC_SEL_W", 3, 3, &umr_bitfield_default },
};
static struct umr_bitfield mmGENS1_1[] = {
	 { "NO_DISPLAY", 0, 0, &umr_bitfield_default },
	 { "VGA_VSTATUS", 3, 3, &umr_bitfield_default },
	 { "PIXEL_READ_BACK", 4, 5, &umr_bitfield_default },
};
static struct umr_bitfield mmCORB_WRITE_POINTER[] = {
	 { "CORB_WRITE_POINTER", 0, 7, &umr_bitfield_default },
};
static struct umr_bitfield mmCORB_READ_POINTER[] = {
	 { "CORB_READ_POINTER", 0, 7, &umr_bitfield_default },
	 { "CORB_READ_POINTER_RESET", 15, 15, &umr_bitfield_default },
};
static struct umr_bitfield mmCORB_CONTROL[] = {
	 { "CORB_MEMORY_ERROR_INTERRUPT_ENABLE", 0, 0, &umr_bitfield_default },
	 { "ENABLE_CORB_DMA_ENGINE", 1, 1, &umr_bitfield_default },
};
static struct umr_bitfield mmCORB_STATUS[] = {
	 { "CORB_MEMORY_ERROR_INDICATION", 0, 0, &umr_bitfield_default },
};
static struct umr_bitfield mmCORB_SIZE[] = {
	 { "CORB_SIZE", 0, 1, &umr_bitfield_default },
	 { "CORB_SIZE_CAPABILITY", 4, 7, &umr_bitfield_default },
};
static struct umr_bitfield mmRIRB_LOWER_BASE_ADDRESS[] = {
	 { "RIRB_LOWER_BASE_UNIMPLEMENTED_BITS", 0, 6, &umr_bitfield_default },
	 { "RIRB_LOWER_BASE_ADDRESS", 7, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmRIRB_UPPER_BASE_ADDRESS[] = {
	 { "RIRB_UPPER_BASE_ADDRESS", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmRIRB_WRITE_POINTER[] = {
	 { "RIRB_WRITE_POINTER", 0, 7, &umr_bitfield_default },
	 { "RIRB_WRITE_POINTER_RESET", 15, 15, &umr_bitfield_default },
};
static struct umr_bitfield mmRESPONSE_INTERRUPT_COUNT[] = {
	 { "N_RESPONSE_INTERRUPT_COUNT", 0, 7, &umr_bitfield_default },
};
static struct umr_bitfield mmRIRB_CONTROL[] = {
	 { "RESPONSE_INTERRUPT_CONTROL", 0, 0, &umr_bitfield_default },
	 { "RIRB_DMA_ENABLE", 1, 1, &umr_bitfield_default },
	 { "RESPONSE_OVERRUN_INTERRUPT_CONTROL", 2, 2, &umr_bitfield_default },
};
static struct umr_bitfield mmRIRB_STATUS[] = {
	 { "RESPONSE_INTERRUPT", 0, 0, &umr_bitfield_default },
	 { "RESPONSE_OVERRUN_INTERRUPT_STATUS", 2, 2, &umr_bitfield_default },
};
static struct umr_bitfield mmRIRB_SIZE[] = {
	 { "RIRB_SIZE", 0, 1, &umr_bitfield_default },
	 { "RIRB_SIZE_CAPABILITY", 4, 7, &umr_bitfield_default },
};
static struct umr_bitfield mmIMMEDIATE_COMMAND_OUTPUT_INTERFACE[] = {
	 { "IMMEDIATE_COMMAND_WRITE_VERB_AND_PAYLOAD", 0, 27, &umr_bitfield_default },
	 { "IMMEDIATE_COMMAND_WRITE_CODEC_ADDRESS", 28, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmIMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA[] = {
	 { "IMMEDIATE_COMMAND_WRITE", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmIMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX[] = {
	 { "IMMEDIATE_COMMAND_WRITE", 0, 15, &umr_bitfield_default },
};
static struct umr_bitfield mmIMMEDIATE_RESPONSE_INPUT_INTERFACE[] = {
	 { "IMMEDIATE_RESPONSE_READ", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmIMMEDIATE_COMMAND_STATUS[] = {
	 { "IMMEDIATE_COMMAND_BUSY", 0, 0, &umr_bitfield_default },
	 { "IMMEDIATE_RESULT_VALID", 1, 1, &umr_bitfield_default },
};
static struct umr_bitfield mmDMA_POSITION_LOWER_BASE_ADDRESS[] = {
	 { "DMA_POSITION_BUFFER_ENABLE", 0, 0, &umr_bitfield_default },
	 { "DMA_POSITION_LOWER_BASE_UNIMPLEMENTED_BITS", 1, 6, &umr_bitfield_default },
	 { "DMA_POSITION_LOWER_BASE_ADDRESS", 7, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDMA_POSITION_UPPER_BASE_ADDRESS[] = {
	 { "DMA_POSITION_UPPER_BASE_ADDRESS", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmWALL_CLOCK_COUNTER_ALIAS[] = {
	 { "WALL_CLOCK_COUNTER_ALIAS", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmAZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA[] = {
	 { "IMMEDIATE_COMMAND_WRITE", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmAZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX[] = {
	 { "IMMEDIATE_COMMAND_WRITE", 0, 16, &umr_bitfield_default },
};
static struct umr_bitfield mmAZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_DATA[] = {
	 { "IMMEDIATE_COMMAND_WRITE", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmAZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_INDEX[] = {
	 { "IMMEDIATE_COMMAND_WRITE", 0, 16, &umr_bitfield_default },
};
static struct umr_bitfield mmAZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA[] = {
	 { "IMMEDIATE_COMMAND_WRITE", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmAZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX[] = {
	 { "IMMEDIATE_COMMAND_WRITE", 0, 16, &umr_bitfield_default },
};
static struct umr_bitfield mmAZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS[] = {
	 { "STREAM_RESET", 0, 0, &umr_bitfield_default },
	 { "STREAM_RUN", 1, 1, &umr_bitfield_default },
	 { "INTERRUPT_ON_COMPLETION_ENABLE", 2, 2, &umr_bitfield_default },
	 { "FIFO_ERROR_INTERRUPT_ENABLE", 3, 3, &umr_bitfield_default },
	 { "DESCRIPTOR_ERROR_INTERRUPT_ENABLE", 4, 4, &umr_bitfield_default },
	 { "STRIPE_CONTROL", 16, 17, &umr_bitfield_default },
	 { "TRAFFIC_PRIORITY", 18, 18, &umr_bitfield_default },
	 { "STREAM_NUMBER", 20, 23, &umr_bitfield_default },
	 { "BUFFER_COMPLETION_INTERRUPT_STATUS", 26, 26, &umr_bitfield_default },
	 { "FIFO_ERROR", 27, 27, &umr_bitfield_default },
	 { "DESCRIPTOR_ERROR", 28, 28, &umr_bitfield_default },
	 { "FIFO_READY", 29, 29, &umr_bitfield_default },
};
static struct umr_bitfield mmAZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER[] = {
	 { "LINK_POSITION_IN_BUFFER", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmAZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH[] = {
	 { "CYCLIC_BUFFER_LENGTH", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmAZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX[] = {
	 { "LAST_VALID_INDEX", 0, 7, &umr_bitfield_default },
};
static struct umr_bitfield mmAZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE[] = {
	 { "FIFO_SIZE", 0, 15, &umr_bitfield_default },
};
static struct umr_bitfield mmAZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT[] = {
	 { "NUMBER_OF_CHANNELS", 0, 3, &umr_bitfield_default },
	 { "BITS_PER_SAMPLE", 4, 6, &umr_bitfield_default },
	 { "SAMPLE_BASE_DIVISOR", 8, 10, &umr_bitfield_default },
	 { "SAMPLE_BASE_MULTIPLE", 11, 13, &umr_bitfield_default },
	 { "SAMPLE_BASE_RATE", 14, 14, &umr_bitfield_default },
};
static struct umr_bitfield mmAZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS[] = {
	 { "BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_UNIMPLEMENTED_BITS", 0, 6, &umr_bitfield_default },
	 { "BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS", 7, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmAZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS[] = {
	 { "BUFFER_DESCRIPTOR_LIST_UPPER_BASE_ADDRESS", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmAZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS[] = {
	 { "LINK_POSITION_IN_BUFFER_ALIAS", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmAZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS[] = {
	 { "STREAM_RESET", 0, 0, &umr_bitfield_default },
	 { "STREAM_RUN", 1, 1, &umr_bitfield_default },
	 { "INTERRUPT_ON_COMPLETION_ENABLE", 2, 2, &umr_bitfield_default },
	 { "FIFO_ERROR_INTERRUPT_ENABLE", 3, 3, &umr_bitfield_default },
	 { "DESCRIPTOR_ERROR_INTERRUPT_ENABLE", 4, 4, &umr_bitfield_default },
	 { "STRIPE_CONTROL", 16, 17, &umr_bitfield_default },
	 { "TRAFFIC_PRIORITY", 18, 18, &umr_bitfield_default },
	 { "STREAM_NUMBER", 20, 23, &umr_bitfield_default },
	 { "BUFFER_COMPLETION_INTERRUPT_STATUS", 26, 26, &umr_bitfield_default },
	 { "FIFO_ERROR", 27, 27, &umr_bitfield_default },
	 { "DESCRIPTOR_ERROR", 28, 28, &umr_bitfield_default },
	 { "FIFO_READY", 29, 29, &umr_bitfield_default },
};
static struct umr_bitfield mmAZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER[] = {
	 { "LINK_POSITION_IN_BUFFER", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmAZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH[] = {
	 { "CYCLIC_BUFFER_LENGTH", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmAZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX[] = {
	 { "LAST_VALID_INDEX", 0, 7, &umr_bitfield_default },
};
static struct umr_bitfield mmAZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE[] = {
	 { "FIFO_SIZE", 0, 15, &umr_bitfield_default },
};
static struct umr_bitfield mmAZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT[] = {
	 { "NUMBER_OF_CHANNELS", 0, 3, &umr_bitfield_default },
	 { "BITS_PER_SAMPLE", 4, 6, &umr_bitfield_default },
	 { "SAMPLE_BASE_DIVISOR", 8, 10, &umr_bitfield_default },
	 { "SAMPLE_BASE_MULTIPLE", 11, 13, &umr_bitfield_default },
	 { "SAMPLE_BASE_RATE", 14, 14, &umr_bitfield_default },
};
static struct umr_bitfield mmAZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS[] = {
	 { "BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_UNIMPLEMENTED_BITS", 0, 6, &umr_bitfield_default },
	 { "BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS", 7, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmAZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS[] = {
	 { "BUFFER_DESCRIPTOR_LIST_UPPER_BASE_ADDRESS", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmAZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS[] = {
	 { "LINK_POSITION_IN_BUFFER_ALIAS", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmAZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS[] = {
	 { "STREAM_RESET", 0, 0, &umr_bitfield_default },
	 { "STREAM_RUN", 1, 1, &umr_bitfield_default },
	 { "INTERRUPT_ON_COMPLETION_ENABLE", 2, 2, &umr_bitfield_default },
	 { "FIFO_ERROR_INTERRUPT_ENABLE", 3, 3, &umr_bitfield_default },
	 { "DESCRIPTOR_ERROR_INTERRUPT_ENABLE", 4, 4, &umr_bitfield_default },
	 { "STRIPE_CONTROL", 16, 17, &umr_bitfield_default },
	 { "TRAFFIC_PRIORITY", 18, 18, &umr_bitfield_default },
	 { "STREAM_NUMBER", 20, 23, &umr_bitfield_default },
	 { "BUFFER_COMPLETION_INTERRUPT_STATUS", 26, 26, &umr_bitfield_default },
	 { "FIFO_ERROR", 27, 27, &umr_bitfield_default },
	 { "DESCRIPTOR_ERROR", 28, 28, &umr_bitfield_default },
	 { "FIFO_READY", 29, 29, &umr_bitfield_default },
};
static struct umr_bitfield mmAZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER[] = {
	 { "LINK_POSITION_IN_BUFFER", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmAZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH[] = {
	 { "CYCLIC_BUFFER_LENGTH", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmAZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX[] = {
	 { "LAST_VALID_INDEX", 0, 7, &umr_bitfield_default },
};
static struct umr_bitfield mmAZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE[] = {
	 { "FIFO_SIZE", 0, 15, &umr_bitfield_default },
};
static struct umr_bitfield mmAZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT[] = {
	 { "NUMBER_OF_CHANNELS", 0, 3, &umr_bitfield_default },
	 { "BITS_PER_SAMPLE", 4, 6, &umr_bitfield_default },
	 { "SAMPLE_BASE_DIVISOR", 8, 10, &umr_bitfield_default },
	 { "SAMPLE_BASE_MULTIPLE", 11, 13, &umr_bitfield_default },
	 { "SAMPLE_BASE_RATE", 14, 14, &umr_bitfield_default },
};
static struct umr_bitfield mmAZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS[] = {
	 { "BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_UNIMPLEMENTED_BITS", 0, 6, &umr_bitfield_default },
	 { "BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS", 7, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmAZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS[] = {
	 { "BUFFER_DESCRIPTOR_LIST_UPPER_BASE_ADDRESS", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmAZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS[] = {
	 { "LINK_POSITION_IN_BUFFER_ALIAS", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmAZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS[] = {
	 { "STREAM_RESET", 0, 0, &umr_bitfield_default },
	 { "STREAM_RUN", 1, 1, &umr_bitfield_default },
	 { "INTERRUPT_ON_COMPLETION_ENABLE", 2, 2, &umr_bitfield_default },
	 { "FIFO_ERROR_INTERRUPT_ENABLE", 3, 3, &umr_bitfield_default },
	 { "DESCRIPTOR_ERROR_INTERRUPT_ENABLE", 4, 4, &umr_bitfield_default },
	 { "STRIPE_CONTROL", 16, 17, &umr_bitfield_default },
	 { "TRAFFIC_PRIORITY", 18, 18, &umr_bitfield_default },
	 { "STREAM_NUMBER", 20, 23, &umr_bitfield_default },
	 { "BUFFER_COMPLETION_INTERRUPT_STATUS", 26, 26, &umr_bitfield_default },
	 { "FIFO_ERROR", 27, 27, &umr_bitfield_default },
	 { "DESCRIPTOR_ERROR", 28, 28, &umr_bitfield_default },
	 { "FIFO_READY", 29, 29, &umr_bitfield_default },
};
static struct umr_bitfield mmAZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER[] = {
	 { "LINK_POSITION_IN_BUFFER", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmAZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH[] = {
	 { "CYCLIC_BUFFER_LENGTH", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmAZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX[] = {
	 { "LAST_VALID_INDEX", 0, 7, &umr_bitfield_default },
};
static struct umr_bitfield mmAZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE[] = {
	 { "FIFO_SIZE", 0, 15, &umr_bitfield_default },
};
static struct umr_bitfield mmAZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT[] = {
	 { "NUMBER_OF_CHANNELS", 0, 3, &umr_bitfield_default },
	 { "BITS_PER_SAMPLE", 4, 6, &umr_bitfield_default },
	 { "SAMPLE_BASE_DIVISOR", 8, 10, &umr_bitfield_default },
	 { "SAMPLE_BASE_MULTIPLE", 11, 13, &umr_bitfield_default },
	 { "SAMPLE_BASE_RATE", 14, 14, &umr_bitfield_default },
};
static struct umr_bitfield mmAZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS[] = {
	 { "BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_UNIMPLEMENTED_BITS", 0, 6, &umr_bitfield_default },
	 { "BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS", 7, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmAZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS[] = {
	 { "BUFFER_DESCRIPTOR_LIST_UPPER_BASE_ADDRESS", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmAZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS[] = {
	 { "LINK_POSITION_IN_BUFFER_ALIAS", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmAZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS[] = {
	 { "STREAM_RESET", 0, 0, &umr_bitfield_default },
	 { "STREAM_RUN", 1, 1, &umr_bitfield_default },
	 { "INTERRUPT_ON_COMPLETION_ENABLE", 2, 2, &umr_bitfield_default },
	 { "FIFO_ERROR_INTERRUPT_ENABLE", 3, 3, &umr_bitfield_default },
	 { "DESCRIPTOR_ERROR_INTERRUPT_ENABLE", 4, 4, &umr_bitfield_default },
	 { "STRIPE_CONTROL", 16, 17, &umr_bitfield_default },
	 { "TRAFFIC_PRIORITY", 18, 18, &umr_bitfield_default },
	 { "STREAM_NUMBER", 20, 23, &umr_bitfield_default },
	 { "BUFFER_COMPLETION_INTERRUPT_STATUS", 26, 26, &umr_bitfield_default },
	 { "FIFO_ERROR", 27, 27, &umr_bitfield_default },
	 { "DESCRIPTOR_ERROR", 28, 28, &umr_bitfield_default },
	 { "FIFO_READY", 29, 29, &umr_bitfield_default },
};
static struct umr_bitfield mmAZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER[] = {
	 { "LINK_POSITION_IN_BUFFER", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmAZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH[] = {
	 { "CYCLIC_BUFFER_LENGTH", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmAZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX[] = {
	 { "LAST_VALID_INDEX", 0, 7, &umr_bitfield_default },
};
static struct umr_bitfield mmAZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE[] = {
	 { "FIFO_SIZE", 0, 15, &umr_bitfield_default },
};
static struct umr_bitfield mmAZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT[] = {
	 { "NUMBER_OF_CHANNELS", 0, 3, &umr_bitfield_default },
	 { "BITS_PER_SAMPLE", 4, 6, &umr_bitfield_default },
	 { "SAMPLE_BASE_DIVISOR", 8, 10, &umr_bitfield_default },
	 { "SAMPLE_BASE_MULTIPLE", 11, 13, &umr_bitfield_default },
	 { "SAMPLE_BASE_RATE", 14, 14, &umr_bitfield_default },
};
static struct umr_bitfield mmAZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS[] = {
	 { "BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_UNIMPLEMENTED_BITS", 0, 6, &umr_bitfield_default },
	 { "BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS", 7, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmAZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS[] = {
	 { "BUFFER_DESCRIPTOR_LIST_UPPER_BASE_ADDRESS", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmAZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS[] = {
	 { "LINK_POSITION_IN_BUFFER_ALIAS", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmAZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS[] = {
	 { "STREAM_RESET", 0, 0, &umr_bitfield_default },
	 { "STREAM_RUN", 1, 1, &umr_bitfield_default },
	 { "INTERRUPT_ON_COMPLETION_ENABLE", 2, 2, &umr_bitfield_default },
	 { "FIFO_ERROR_INTERRUPT_ENABLE", 3, 3, &umr_bitfield_default },
	 { "DESCRIPTOR_ERROR_INTERRUPT_ENABLE", 4, 4, &umr_bitfield_default },
	 { "STRIPE_CONTROL", 16, 17, &umr_bitfield_default },
	 { "TRAFFIC_PRIORITY", 18, 18, &umr_bitfield_default },
	 { "STREAM_NUMBER", 20, 23, &umr_bitfield_default },
	 { "BUFFER_COMPLETION_INTERRUPT_STATUS", 26, 26, &umr_bitfield_default },
	 { "FIFO_ERROR", 27, 27, &umr_bitfield_default },
	 { "DESCRIPTOR_ERROR", 28, 28, &umr_bitfield_default },
	 { "FIFO_READY", 29, 29, &umr_bitfield_default },
};
static struct umr_bitfield mmAZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER[] = {
	 { "LINK_POSITION_IN_BUFFER", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmAZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH[] = {
	 { "CYCLIC_BUFFER_LENGTH", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmAZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX[] = {
	 { "LAST_VALID_INDEX", 0, 7, &umr_bitfield_default },
};
static struct umr_bitfield mmAZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE[] = {
	 { "FIFO_SIZE", 0, 15, &umr_bitfield_default },
};
static struct umr_bitfield mmAZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT[] = {
	 { "NUMBER_OF_CHANNELS", 0, 3, &umr_bitfield_default },
	 { "BITS_PER_SAMPLE", 4, 6, &umr_bitfield_default },
	 { "SAMPLE_BASE_DIVISOR", 8, 10, &umr_bitfield_default },
	 { "SAMPLE_BASE_MULTIPLE", 11, 13, &umr_bitfield_default },
	 { "SAMPLE_BASE_RATE", 14, 14, &umr_bitfield_default },
};
static struct umr_bitfield mmAZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS[] = {
	 { "BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_UNIMPLEMENTED_BITS", 0, 6, &umr_bitfield_default },
	 { "BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS", 7, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmAZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS[] = {
	 { "BUFFER_DESCRIPTOR_LIST_UPPER_BASE_ADDRESS", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmAZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS[] = {
	 { "LINK_POSITION_IN_BUFFER_ALIAS", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmAZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS[] = {
	 { "STREAM_RESET", 0, 0, &umr_bitfield_default },
	 { "STREAM_RUN", 1, 1, &umr_bitfield_default },
	 { "INTERRUPT_ON_COMPLETION_ENABLE", 2, 2, &umr_bitfield_default },
	 { "FIFO_ERROR_INTERRUPT_ENABLE", 3, 3, &umr_bitfield_default },
	 { "DESCRIPTOR_ERROR_INTERRUPT_ENABLE", 4, 4, &umr_bitfield_default },
	 { "STRIPE_CONTROL", 16, 17, &umr_bitfield_default },
	 { "TRAFFIC_PRIORITY", 18, 18, &umr_bitfield_default },
	 { "STREAM_NUMBER", 20, 23, &umr_bitfield_default },
	 { "BUFFER_COMPLETION_INTERRUPT_STATUS", 26, 26, &umr_bitfield_default },
	 { "FIFO_ERROR", 27, 27, &umr_bitfield_default },
	 { "DESCRIPTOR_ERROR", 28, 28, &umr_bitfield_default },
	 { "FIFO_READY", 29, 29, &umr_bitfield_default },
};
static struct umr_bitfield mmAZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER[] = {
	 { "LINK_POSITION_IN_BUFFER", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmAZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH[] = {
	 { "CYCLIC_BUFFER_LENGTH", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmAZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX[] = {
	 { "LAST_VALID_INDEX", 0, 7, &umr_bitfield_default },
};
static struct umr_bitfield mmAZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE[] = {
	 { "FIFO_SIZE", 0, 15, &umr_bitfield_default },
};
static struct umr_bitfield mmAZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT[] = {
	 { "NUMBER_OF_CHANNELS", 0, 3, &umr_bitfield_default },
	 { "BITS_PER_SAMPLE", 4, 6, &umr_bitfield_default },
	 { "SAMPLE_BASE_DIVISOR", 8, 10, &umr_bitfield_default },
	 { "SAMPLE_BASE_MULTIPLE", 11, 13, &umr_bitfield_default },
	 { "SAMPLE_BASE_RATE", 14, 14, &umr_bitfield_default },
};
static struct umr_bitfield mmAZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS[] = {
	 { "BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_UNIMPLEMENTED_BITS", 0, 6, &umr_bitfield_default },
	 { "BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS", 7, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmAZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS[] = {
	 { "BUFFER_DESCRIPTOR_LIST_UPPER_BASE_ADDRESS", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmAZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS[] = {
	 { "LINK_POSITION_IN_BUFFER_ALIAS", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmAZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS[] = {
	 { "STREAM_RESET", 0, 0, &umr_bitfield_default },
	 { "STREAM_RUN", 1, 1, &umr_bitfield_default },
	 { "INTERRUPT_ON_COMPLETION_ENABLE", 2, 2, &umr_bitfield_default },
	 { "FIFO_ERROR_INTERRUPT_ENABLE", 3, 3, &umr_bitfield_default },
	 { "DESCRIPTOR_ERROR_INTERRUPT_ENABLE", 4, 4, &umr_bitfield_default },
	 { "STRIPE_CONTROL", 16, 17, &umr_bitfield_default },
	 { "TRAFFIC_PRIORITY", 18, 18, &umr_bitfield_default },
	 { "STREAM_NUMBER", 20, 23, &umr_bitfield_default },
	 { "BUFFER_COMPLETION_INTERRUPT_STATUS", 26, 26, &umr_bitfield_default },
	 { "FIFO_ERROR", 27, 27, &umr_bitfield_default },
	 { "DESCRIPTOR_ERROR", 28, 28, &umr_bitfield_default },
	 { "FIFO_READY", 29, 29, &umr_bitfield_default },
};
static struct umr_bitfield mmAZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER[] = {
	 { "LINK_POSITION_IN_BUFFER", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmAZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH[] = {
	 { "CYCLIC_BUFFER_LENGTH", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmAZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX[] = {
	 { "LAST_VALID_INDEX", 0, 7, &umr_bitfield_default },
};
static struct umr_bitfield mmAZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE[] = {
	 { "FIFO_SIZE", 0, 15, &umr_bitfield_default },
};
static struct umr_bitfield mmAZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT[] = {
	 { "NUMBER_OF_CHANNELS", 0, 3, &umr_bitfield_default },
	 { "BITS_PER_SAMPLE", 4, 6, &umr_bitfield_default },
	 { "SAMPLE_BASE_DIVISOR", 8, 10, &umr_bitfield_default },
	 { "SAMPLE_BASE_MULTIPLE", 11, 13, &umr_bitfield_default },
	 { "SAMPLE_BASE_RATE", 14, 14, &umr_bitfield_default },
};
static struct umr_bitfield mmAZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS[] = {
	 { "BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_UNIMPLEMENTED_BITS", 0, 6, &umr_bitfield_default },
	 { "BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS", 7, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmAZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS[] = {
	 { "BUFFER_DESCRIPTOR_LIST_UPPER_BASE_ADDRESS", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmAZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS[] = {
	 { "LINK_POSITION_IN_BUFFER_ALIAS", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmVGA_RENDER_CONTROL[] = {
	 { "VGA_BLINK_RATE", 0, 4, &umr_bitfield_default },
	 { "VGA_BLINK_MODE", 5, 6, &umr_bitfield_default },
	 { "VGA_CURSOR_BLINK_INVERT", 7, 7, &umr_bitfield_default },
	 { "VGA_EXTD_ADDR_COUNT_ENABLE", 8, 8, &umr_bitfield_default },
	 { "VGA_VSTATUS_CNTL", 16, 17, &umr_bitfield_default },
	 { "VGA_LOCK_8DOT", 24, 24, &umr_bitfield_default },
	 { "VGAREG_LINECMP_COMPATIBILITY_SEL", 25, 25, &umr_bitfield_default },
};
static struct umr_bitfield mmVGA_SEQUENCER_RESET_CONTROL[] = {
	 { "D1_BLANK_DISPLAY_WHEN_SEQUENCER_RESET", 0, 0, &umr_bitfield_default },
	 { "D2_BLANK_DISPLAY_WHEN_SEQUENCER_RESET", 1, 1, &umr_bitfield_default },
	 { "D3_BLANK_DISPLAY_WHEN_SEQUENCER_RESET", 2, 2, &umr_bitfield_default },
	 { "D4_BLANK_DISPLAY_WHEN_SEQUENCER_RESET", 3, 3, &umr_bitfield_default },
	 { "D5_BLANK_DISPLAY_WHEN_SEQUENCER_RESET", 4, 4, &umr_bitfield_default },
	 { "D6_BLANK_DISPLAY_WHEN_SEQUENCER_RESET", 5, 5, &umr_bitfield_default },
	 { "D1_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET", 8, 8, &umr_bitfield_default },
	 { "D2_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET", 9, 9, &umr_bitfield_default },
	 { "D3_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET", 10, 10, &umr_bitfield_default },
	 { "D4_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET", 11, 11, &umr_bitfield_default },
	 { "D5_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET", 12, 12, &umr_bitfield_default },
	 { "D6_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET", 13, 13, &umr_bitfield_default },
	 { "VGA_MODE_AUTO_TRIGGER_ENABLE", 16, 16, &umr_bitfield_default },
	 { "VGA_MODE_AUTO_TRIGGER_REGISTER_SELECT", 17, 17, &umr_bitfield_default },
	 { "VGA_MODE_AUTO_TRIGGER_INDEX_SELECT", 18, 23, &umr_bitfield_default },
};
static struct umr_bitfield mmVGA_MODE_CONTROL[] = {
	 { "VGA_ATI_LINEAR", 0, 0, &umr_bitfield_default },
	 { "VGA_LUT_PALETTE_UPDATE_MODE", 4, 5, &umr_bitfield_default },
	 { "VGA_128K_APERTURE_PAGING", 8, 8, &umr_bitfield_default },
	 { "VGA_TEXT_132_COLUMNS_EN", 16, 16, &umr_bitfield_default },
	 { "VGA_DEEP_SLEEP_FORCE_EXIT", 24, 24, &umr_bitfield_default },
};
static struct umr_bitfield mmVGA_SURFACE_PITCH_SELECT[] = {
	 { "VGA_SURFACE_PITCH_SELECT", 0, 1, &umr_bitfield_default },
	 { "VGA_SURFACE_HEIGHT_SELECT", 8, 9, &umr_bitfield_default },
};
static struct umr_bitfield mmVGA_MEMORY_BASE_ADDRESS[] = {
	 { "VGA_MEMORY_BASE_ADDRESS", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmVGA_DISPBUF1_SURFACE_ADDR[] = {
	 { "VGA_DISPBUF1_SURFACE_ADDR", 0, 24, &umr_bitfield_default },
};
static struct umr_bitfield mmVGA_DISPBUF2_SURFACE_ADDR[] = {
	 { "VGA_DISPBUF2_SURFACE_ADDR", 0, 24, &umr_bitfield_default },
};
static struct umr_bitfield mmVGA_MEMORY_BASE_ADDRESS_HIGH[] = {
	 { "VGA_MEMORY_BASE_ADDRESS_HIGH", 0, 7, &umr_bitfield_default },
};
static struct umr_bitfield mmVGA_HDP_CONTROL[] = {
	 { "VGA_MEM_PAGE_SELECT_EN", 0, 0, &umr_bitfield_default },
	 { "VGA_MEMORY_DISABLE", 4, 4, &umr_bitfield_default },
	 { "VGA_RBBM_LOCK_DISABLE", 8, 8, &umr_bitfield_default },
	 { "VGA_SOFT_RESET", 16, 16, &umr_bitfield_default },
	 { "VGA_TEST_RESET_CONTROL", 24, 24, &umr_bitfield_default },
};
static struct umr_bitfield mmVGA_CACHE_CONTROL[] = {
	 { "VGA_WRITE_THROUGH_CACHE_DIS", 0, 0, &umr_bitfield_default },
	 { "VGA_READ_CACHE_DISABLE", 8, 8, &umr_bitfield_default },
	 { "VGA_READ_BUFFER_INVALIDATE", 16, 16, &umr_bitfield_default },
	 { "VGA_DCCIF_W256ONLY", 20, 20, &umr_bitfield_default },
	 { "VGA_DCCIF_WC_TIMEOUT", 24, 29, &umr_bitfield_default },
};
static struct umr_bitfield mmD1VGA_CONTROL[] = {
	 { "D1VGA_MODE_ENABLE", 0, 0, &umr_bitfield_default },
	 { "D1VGA_TIMING_SELECT", 8, 8, &umr_bitfield_default },
	 { "D1VGA_SYNC_POLARITY_SELECT", 9, 9, &umr_bitfield_default },
	 { "D1VGA_OVERSCAN_COLOR_EN", 16, 16, &umr_bitfield_default },
	 { "D1VGA_ROTATE", 24, 25, &umr_bitfield_default },
};
static struct umr_bitfield mmD2VGA_CONTROL[] = {
	 { "D2VGA_MODE_ENABLE", 0, 0, &umr_bitfield_default },
	 { "D2VGA_TIMING_SELECT", 8, 8, &umr_bitfield_default },
	 { "D2VGA_SYNC_POLARITY_SELECT", 9, 9, &umr_bitfield_default },
	 { "D2VGA_OVERSCAN_COLOR_EN", 16, 16, &umr_bitfield_default },
	 { "D2VGA_ROTATE", 24, 25, &umr_bitfield_default },
};
static struct umr_bitfield mmVGA_STATUS[] = {
	 { "VGA_MEM_ACCESS_STATUS", 0, 0, &umr_bitfield_default },
	 { "VGA_REG_ACCESS_STATUS", 1, 1, &umr_bitfield_default },
	 { "VGA_DISPLAY_SWITCH_STATUS", 2, 2, &umr_bitfield_default },
	 { "VGA_MODE_AUTO_TRIGGER_STATUS", 3, 3, &umr_bitfield_default },
};
static struct umr_bitfield mmVGA_INTERRUPT_CONTROL[] = {
	 { "VGA_MEM_ACCESS_INT_MASK", 0, 0, &umr_bitfield_default },
	 { "VGA_REG_ACCESS_INT_MASK", 8, 8, &umr_bitfield_default },
	 { "VGA_DISPLAY_SWITCH_INT_MASK", 16, 16, &umr_bitfield_default },
	 { "VGA_MODE_AUTO_TRIGGER_INT_MASK", 24, 24, &umr_bitfield_default },
};
static struct umr_bitfield mmVGA_STATUS_CLEAR[] = {
	 { "VGA_MEM_ACCESS_INT_CLEAR", 0, 0, &umr_bitfield_default },
	 { "VGA_REG_ACCESS_INT_CLEAR", 8, 8, &umr_bitfield_default },
	 { "VGA_DISPLAY_SWITCH_INT_CLEAR", 16, 16, &umr_bitfield_default },
	 { "VGA_MODE_AUTO_TRIGGER_INT_CLEAR", 24, 24, &umr_bitfield_default },
};
static struct umr_bitfield mmVGA_INTERRUPT_STATUS[] = {
	 { "VGA_MEM_ACCESS_INT_STATUS", 0, 0, &umr_bitfield_default },
	 { "VGA_REG_ACCESS_INT_STATUS", 1, 1, &umr_bitfield_default },
	 { "VGA_DISPLAY_SWITCH_INT_STATUS", 2, 2, &umr_bitfield_default },
	 { "VGA_MODE_AUTO_TRIGGER_INT_STATUS", 3, 3, &umr_bitfield_default },
};
static struct umr_bitfield mmVGA_MAIN_CONTROL[] = {
	 { "VGA_CRTC_TIMEOUT", 0, 1, &umr_bitfield_default },
	 { "VGA_RENDER_TIMEOUT_COUNT", 3, 4, &umr_bitfield_default },
	 { "VGA_VIRTUAL_VERTICAL_RETRACE_DURATION", 5, 7, &umr_bitfield_default },
	 { "VGA_READBACK_VGA_VSTATUS_SOURCE_SELECT", 8, 9, &umr_bitfield_default },
	 { "VGA_MC_WRITE_CLEAN_WAIT_DELAY", 12, 15, &umr_bitfield_default },
	 { "VGA_READBACK_NO_DISPLAY_SOURCE_SELECT", 16, 17, &umr_bitfield_default },
	 { "VGA_READBACK_CRT_INTR_SOURCE_SELECT", 24, 25, &umr_bitfield_default },
	 { "VGA_READBACK_SENSE_SWITCH_SELECT", 26, 26, &umr_bitfield_default },
	 { "VGA_EXTERNAL_DAC_SENSE", 29, 29, &umr_bitfield_default },
	 { "VGA_MAIN_TEST_VSTATUS_NO_DISPLAY_CRTC_TIMEOUT", 31, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmVGA_TEST_CONTROL[] = {
	 { "VGA_TEST_ENABLE", 0, 0, &umr_bitfield_default },
	 { "VGA_TEST_RENDER_START", 8, 8, &umr_bitfield_default },
	 { "VGA_TEST_RENDER_DONE", 16, 16, &umr_bitfield_default },
	 { "VGA_TEST_RENDER_DISPBUF_SELECT", 24, 24, &umr_bitfield_default },
};
static struct umr_bitfield mmVGA_QOS_CTRL[] = {
	 { "VGA_READ_QOS", 0, 3, &umr_bitfield_default },
	 { "VGA_WRITE_QOS", 4, 7, &umr_bitfield_default },
};
static struct umr_bitfield mmD3VGA_CONTROL[] = {
	 { "D3VGA_MODE_ENABLE", 0, 0, &umr_bitfield_default },
	 { "D3VGA_TIMING_SELECT", 8, 8, &umr_bitfield_default },
	 { "D3VGA_SYNC_POLARITY_SELECT", 9, 9, &umr_bitfield_default },
	 { "D3VGA_OVERSCAN_COLOR_EN", 16, 16, &umr_bitfield_default },
	 { "D3VGA_ROTATE", 24, 25, &umr_bitfield_default },
};
static struct umr_bitfield mmD4VGA_CONTROL[] = {
	 { "D4VGA_MODE_ENABLE", 0, 0, &umr_bitfield_default },
	 { "D4VGA_TIMING_SELECT", 8, 8, &umr_bitfield_default },
	 { "D4VGA_SYNC_POLARITY_SELECT", 9, 9, &umr_bitfield_default },
	 { "D4VGA_OVERSCAN_COLOR_EN", 16, 16, &umr_bitfield_default },
	 { "D4VGA_ROTATE", 24, 25, &umr_bitfield_default },
};
static struct umr_bitfield mmD5VGA_CONTROL[] = {
	 { "D5VGA_MODE_ENABLE", 0, 0, &umr_bitfield_default },
	 { "D5VGA_TIMING_SELECT", 8, 8, &umr_bitfield_default },
	 { "D5VGA_SYNC_POLARITY_SELECT", 9, 9, &umr_bitfield_default },
	 { "D5VGA_OVERSCAN_COLOR_EN", 16, 16, &umr_bitfield_default },
	 { "D5VGA_ROTATE", 24, 25, &umr_bitfield_default },
};
static struct umr_bitfield mmD6VGA_CONTROL[] = {
	 { "D6VGA_MODE_ENABLE", 0, 0, &umr_bitfield_default },
	 { "D6VGA_TIMING_SELECT", 8, 8, &umr_bitfield_default },
	 { "D6VGA_SYNC_POLARITY_SELECT", 9, 9, &umr_bitfield_default },
	 { "D6VGA_OVERSCAN_COLOR_EN", 16, 16, &umr_bitfield_default },
	 { "D6VGA_ROTATE", 24, 25, &umr_bitfield_default },
};
static struct umr_bitfield mmVGA_SOURCE_SELECT[] = {
	 { "VGA_SOURCE_SEL_A", 0, 2, &umr_bitfield_default },
	 { "VGA_SOURCE_SEL_B", 8, 10, &umr_bitfield_default },
};
static struct umr_bitfield mmPHYPLLA_PIXCLK_RESYNC_CNTL[] = {
	 { "PHYPLLA_PIXCLK_RESYNC_ENABLE", 0, 0, &umr_bitfield_default },
	 { "PHYPLLA_DCCG_DEEP_COLOR_CNTL", 4, 5, &umr_bitfield_default },
	 { "PHYPLLA_PIXCLK_ENABLE", 8, 8, &umr_bitfield_default },
};
static struct umr_bitfield mmPHYPLLB_PIXCLK_RESYNC_CNTL[] = {
	 { "PHYPLLB_PIXCLK_RESYNC_ENABLE", 0, 0, &umr_bitfield_default },
	 { "PHYPLLB_DCCG_DEEP_COLOR_CNTL", 4, 5, &umr_bitfield_default },
	 { "PHYPLLB_PIXCLK_ENABLE", 8, 8, &umr_bitfield_default },
};
static struct umr_bitfield mmPHYPLLC_PIXCLK_RESYNC_CNTL[] = {
	 { "PHYPLLC_PIXCLK_RESYNC_ENABLE", 0, 0, &umr_bitfield_default },
	 { "PHYPLLC_DCCG_DEEP_COLOR_CNTL", 4, 5, &umr_bitfield_default },
	 { "PHYPLLC_PIXCLK_ENABLE", 8, 8, &umr_bitfield_default },
};
static struct umr_bitfield mmPHYPLLD_PIXCLK_RESYNC_CNTL[] = {
	 { "PHYPLLD_PIXCLK_RESYNC_ENABLE", 0, 0, &umr_bitfield_default },
	 { "PHYPLLD_DCCG_DEEP_COLOR_CNTL", 4, 5, &umr_bitfield_default },
	 { "PHYPLLD_PIXCLK_ENABLE", 8, 8, &umr_bitfield_default },
};
static struct umr_bitfield mmDP_DTO_DBUF_EN[] = {
	 { "DP_DTO0_DBUF_EN", 0, 0, &umr_bitfield_default },
	 { "DP_DTO1_DBUF_EN", 1, 1, &umr_bitfield_default },
	 { "DP_DTO2_DBUF_EN", 2, 2, &umr_bitfield_default },
	 { "DP_DTO3_DBUF_EN", 3, 3, &umr_bitfield_default },
	 { "DP_DTO4_DBUF_EN", 4, 4, &umr_bitfield_default },
	 { "DP_DTO5_DBUF_EN", 5, 5, &umr_bitfield_default },
	 { "DP_DTO6_DBUF_EN", 6, 6, &umr_bitfield_default },
	 { "DP_DTO7_DBUF_EN", 7, 7, &umr_bitfield_default },
};
static struct umr_bitfield mmDPREFCLK_CGTT_BLK_CTRL_REG[] = {
	 { "DPREFCLK_TURN_ON_DELAY", 0, 3, &umr_bitfield_default },
	 { "DPREFCLK_TURN_OFF_DELAY", 4, 11, &umr_bitfield_default },
};
static struct umr_bitfield mmREFCLK_CNTL[] = {
	 { "REFCLK_CLOCK_EN", 0, 0, &umr_bitfield_default },
	 { "REFCLK_SRC_SEL", 1, 1, &umr_bitfield_default },
};
static struct umr_bitfield mmMIPI_CLK_CNTL[] = {
	 { "DSICLK_CLOCK_ENABLE", 0, 0, &umr_bitfield_default },
	 { "BYTECLK_CLOCK_ENABLE", 1, 1, &umr_bitfield_default },
	 { "ESCCLK_CLOCK_ENABLE", 2, 2, &umr_bitfield_default },
};
static struct umr_bitfield mmREFCLK_CGTT_BLK_CTRL_REG[] = {
	 { "REFCLK_TURN_ON_DELAY", 0, 3, &umr_bitfield_default },
	 { "REFCLK_TURN_OFF_DELAY", 4, 11, &umr_bitfield_default },
};
static struct umr_bitfield mmPHYPLLE_PIXCLK_RESYNC_CNTL[] = {
	 { "PHYPLLE_PIXCLK_RESYNC_ENABLE", 0, 0, &umr_bitfield_default },
	 { "PHYPLLE_DCCG_DEEP_COLOR_CNTL", 4, 5, &umr_bitfield_default },
	 { "PHYPLLE_PIXCLK_ENABLE", 8, 8, &umr_bitfield_default },
};
static struct umr_bitfield mmDCCG_PERFMON_CNTL2[] = {
	 { "DCCG_PERF_DSICLK_ENABLE", 0, 0, &umr_bitfield_default },
	 { "DCCG_PERF_REFCLK_ENABLE", 1, 1, &umr_bitfield_default },
	 { "DCCG_PERF_PIXCLK1_ENABLE", 2, 2, &umr_bitfield_default },
	 { "DCCG_PERF_PIXCLK2_ENABLE", 3, 3, &umr_bitfield_default },
	 { "DCCG_PERF_UNIPHYC_PIXCLK_ENABLE", 4, 4, &umr_bitfield_default },
	 { "DCCG_PERF_UNIPHYD_PIXCLK_ENABLE", 5, 5, &umr_bitfield_default },
	 { "DCCG_PERF_UNIPHYE_PIXCLK_ENABLE", 6, 6, &umr_bitfield_default },
	 { "DCCG_PERF_UNIPHYF_PIXCLK_ENABLE", 7, 7, &umr_bitfield_default },
	 { "DCCG_PERF_UNIPHYG_PIXCLK_ENABLE", 8, 8, &umr_bitfield_default },
};
static struct umr_bitfield mmDSICLK_CGTT_BLK_CTRL_REG[] = {
	 { "DSICLK_TURN_ON_DELAY", 0, 3, &umr_bitfield_default },
	 { "DSICLK_TURN_OFF_DELAY", 4, 11, &umr_bitfield_default },
};
static struct umr_bitfield mmDCCG_CBUS_WRCMD_DELAY[] = {
	 { "CBUS_PLL_WRCMD_DELAY", 0, 3, &umr_bitfield_default },
};
static struct umr_bitfield mmDCCG_DS_DTO_INCR[] = {
	 { "DCCG_DS_DTO_INCR", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCCG_DS_DTO_MODULO[] = {
	 { "DCCG_DS_DTO_MODULO", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCCG_DS_CNTL[] = {
	 { "DCCG_DS_ENABLE", 0, 0, &umr_bitfield_default },
	 { "DCCG_DS_REF_SRC", 4, 5, &umr_bitfield_default },
	 { "DCCG_DS_HW_CAL_ENABLE", 8, 8, &umr_bitfield_default },
	 { "DCCG_DS_ENABLED_STATUS", 9, 9, &umr_bitfield_default },
	 { "DCCG_DS_XTALIN_RATE_DIV", 16, 17, &umr_bitfield_default },
	 { "DCCG_DS_JITTER_REMOVE_DIS", 24, 24, &umr_bitfield_default },
	 { "DCCG_DS_DELAY_XTAL_SEL", 25, 25, &umr_bitfield_default },
};
static struct umr_bitfield mmDCCG_DS_HW_CAL_INTERVAL[] = {
	 { "DCCG_DS_HW_CAL_INTERVAL", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSYMCLKG_CLOCK_ENABLE[] = {
	 { "SYMCLKG_CLOCK_ENABLE", 0, 0, &umr_bitfield_default },
	 { "SYMCLKG_FE_FORCE_EN", 4, 4, &umr_bitfield_default },
	 { "SYMCLKG_FE_FORCE_SRC", 8, 10, &umr_bitfield_default },
};
static struct umr_bitfield mmDPREFCLK_CNTL[] = {
	 { "DPREFCLK_SRC_SEL", 0, 2, &umr_bitfield_default },
	 { "UNB_DB_CLK_ENABLE", 8, 8, &umr_bitfield_default },
};
static struct umr_bitfield mmAOMCLK0_CNTL[] = {
	 { "AOMCLK0_CLOCK_EN", 0, 0, &umr_bitfield_default },
};
static struct umr_bitfield mmAOMCLK1_CNTL[] = {
	 { "AOMCLK1_CLOCK_EN", 0, 0, &umr_bitfield_default },
};
static struct umr_bitfield mmAOMCLK2_CNTL[] = {
	 { "AOMCLK2_CLOCK_EN", 0, 0, &umr_bitfield_default },
};
static struct umr_bitfield mmDCCG_AUDIO_DTO2_PHASE[] = {
	 { "DCCG_AUDIO_DTO2_PHASE", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCCG_AUDIO_DTO2_MODULO[] = {
	 { "DCCG_AUDIO_DTO2_MODULO", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCE_VERSION[] = {
	 { "MAJOR_VERSION", 0, 7, &umr_bitfield_default },
	 { "MINOR_VERSION", 8, 15, &umr_bitfield_default },
};
static struct umr_bitfield mmPHYPLLG_PIXCLK_RESYNC_CNTL[] = {
	 { "PHYPLLG_PIXCLK_RESYNC_ENABLE", 0, 0, &umr_bitfield_default },
	 { "PHYPLLG_DCCG_DEEP_COLOR_CNTL", 4, 5, &umr_bitfield_default },
	 { "PHYPLLG_PIXCLK_ENABLE", 8, 8, &umr_bitfield_default },
};
static struct umr_bitfield mmDCCG_GTC_CNTL[] = {
	 { "DCCG_GTC_ENABLE", 0, 0, &umr_bitfield_default },
};
static struct umr_bitfield mmDCCG_GTC_DTO_INCR[] = {
	 { "DCCG_GTC_DTO_INCR", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCCG_GTC_DTO_MODULO[] = {
	 { "DCCG_GTC_DTO_MODULO", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCCG_GTC_CURRENT[] = {
	 { "DCCG_GTC_CURRENT", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMIPI_DTO_CNTL[] = {
	 { "MIPI_DTO_ENABLE", 0, 0, &umr_bitfield_default },
};
static struct umr_bitfield mmMIPI_DTO_PHASE[] = {
	 { "MIPI_DTO_PHASE", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMIPI_DTO_MODULO[] = {
	 { "MIPI_DTO_MODULO", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDAC_CLK_ENABLE[] = {
	 { "DACA_CLK_ENABLE", 0, 0, &umr_bitfield_default },
};
static struct umr_bitfield mmDVO_CLK_ENABLE[] = {
	 { "DVO_CLK_ENABLE", 0, 0, &umr_bitfield_default },
};
static struct umr_bitfield mmAVSYNC_COUNTER_WRITE[] = {
	 { "AVSYNC_COUNTER_WRVALUE", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmAVSYNC_COUNTER_CONTROL[] = {
	 { "AVSYNC_COUNTER_ENABLE", 0, 0, &umr_bitfield_default },
};
static struct umr_bitfield mmAVSYNC_COUNTER_READ[] = {
	 { "AVSYNC_COUNTER_RDVALUE", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMILLISECOND_TIME_BASE_DIV[] = {
	 { "MILLISECOND_TIME_BASE_DIV", 0, 16, &umr_bitfield_default },
	 { "MILLISECOND_TIME_BASE_CLOCK_SOURCE_SEL", 20, 20, &umr_bitfield_default },
};
static struct umr_bitfield mmDISPCLK_FREQ_CHANGE_CNTL[] = {
	 { "DISPCLK_STEP_DELAY", 0, 13, &umr_bitfield_default },
	 { "DISPCLK_STEP_SIZE", 16, 19, &umr_bitfield_default },
	 { "DISPCLK_FREQ_RAMP_DONE", 20, 20, &umr_bitfield_default },
	 { "DISPCLK_MAX_ERRDET_CYCLES", 25, 27, &umr_bitfield_default },
	 { "DCCG_FIFO_ERRDET_RESET", 28, 28, &umr_bitfield_default },
	 { "DCCG_FIFO_ERRDET_STATE", 29, 29, &umr_bitfield_default },
	 { "DCCG_FIFO_ERRDET_OVR_EN", 30, 30, &umr_bitfield_default },
	 { "DISPCLK_CHG_FWD_CORR_DISABLE", 31, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_MEM_GLOBAL_PWR_REQ_CNTL[] = {
	 { "DC_MEM_GLOBAL_PWR_REQ_DIS", 0, 0, &umr_bitfield_default },
};
static struct umr_bitfield mmDCCG_PERFMON_CNTL[] = {
	 { "DCCG_PERF_DISPCLK_ENABLE", 0, 0, &umr_bitfield_default },
	 { "DCCG_PERF_DPREFCLK_ENABLE", 1, 1, &umr_bitfield_default },
	 { "DCCG_PERF_UNIPHYA_PIXCLK_ENABLE", 2, 2, &umr_bitfield_default },
	 { "DCCG_PERF_UNIPHYB_PIXCLK_ENABLE", 3, 3, &umr_bitfield_default },
	 { "DCCG_PERF_PIXCLK0_ENABLE", 4, 4, &umr_bitfield_default },
	 { "DCCG_PERF_RUN", 5, 5, &umr_bitfield_default },
	 { "DCCG_PERF_MODE_VSYNC", 6, 6, &umr_bitfield_default },
	 { "DCCG_PERF_MODE_HSYNC", 7, 7, &umr_bitfield_default },
	 { "DCCG_PERF_OTG_SEL", 8, 10, &umr_bitfield_default },
	 { "DCCG_PERF_XTALIN_PULSE_DIV", 11, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCCG_GATE_DISABLE_CNTL[] = {
	 { "DISPCLK_DCCG_GATE_DISABLE", 0, 0, &umr_bitfield_default },
	 { "DISPCLK_R_DCCG_GATE_DISABLE", 1, 1, &umr_bitfield_default },
	 { "SOCCLK_GATE_DISABLE", 2, 2, &umr_bitfield_default },
	 { "DPREFCLK_GATE_DISABLE", 3, 3, &umr_bitfield_default },
	 { "DACACLK_GATE_DISABLE", 4, 4, &umr_bitfield_default },
	 { "DVOACLK_GATE_DISABLE", 6, 6, &umr_bitfield_default },
	 { "DPREFCLK_R_DCCG_GATE_DISABLE", 8, 8, &umr_bitfield_default },
	 { "DPPCLK_GATE_DISABLE", 9, 9, &umr_bitfield_default },
	 { "AOMCLK0_GATE_DISABLE", 17, 17, &umr_bitfield_default },
	 { "AOMCLK1_GATE_DISABLE", 18, 18, &umr_bitfield_default },
	 { "AOMCLK2_GATE_DISABLE", 19, 19, &umr_bitfield_default },
	 { "AUDIO_DTO2_CLK_GATE_DISABLE", 21, 21, &umr_bitfield_default },
	 { "DPREFCLK_GTC_GATE_DISABLE", 22, 22, &umr_bitfield_default },
	 { "UNB_DB_CLK_GATE_DISABLE", 23, 23, &umr_bitfield_default },
	 { "REFCLK_GATE_DISABLE", 26, 26, &umr_bitfield_default },
	 { "REFCLK_R_DIG_GATE_DISABLE", 27, 27, &umr_bitfield_default },
	 { "DSICLK_GATE_DISABLE", 28, 28, &umr_bitfield_default },
	 { "BYTECLK_GATE_DISABLE", 29, 29, &umr_bitfield_default },
	 { "ESCCLK_GATE_DISABLE", 30, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmDISPCLK_CGTT_BLK_CTRL_REG[] = {
	 { "DISPCLK_TURN_ON_DELAY", 0, 3, &umr_bitfield_default },
	 { "DISPCLK_TURN_OFF_DELAY", 4, 11, &umr_bitfield_default },
};
static struct umr_bitfield mmSOCCLK_CGTT_BLK_CTRL_REG[] = {
	 { "SOCCLK_TURN_ON_DELAY", 0, 3, &umr_bitfield_default },
	 { "SOCCLK_TURN_OFF_DELAY", 4, 11, &umr_bitfield_default },
};
static struct umr_bitfield mmDCCG_CAC_STATUS[] = {
	 { "CAC_STATUS_RDDATA", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmPIXCLK1_RESYNC_CNTL[] = {
	 { "PIXCLK1_RESYNC_ENABLE", 0, 0, &umr_bitfield_default },
	 { "DCCG_DEEP_COLOR_CNTL1", 4, 5, &umr_bitfield_default },
};
static struct umr_bitfield mmPIXCLK2_RESYNC_CNTL[] = {
	 { "PIXCLK2_RESYNC_ENABLE", 0, 0, &umr_bitfield_default },
	 { "DCCG_DEEP_COLOR_CNTL2", 4, 5, &umr_bitfield_default },
};
static struct umr_bitfield mmPIXCLK0_RESYNC_CNTL[] = {
	 { "PIXCLK0_RESYNC_ENABLE", 0, 0, &umr_bitfield_default },
	 { "DCCG_DEEP_COLOR_CNTL0", 4, 5, &umr_bitfield_default },
};
static struct umr_bitfield mmMICROSECOND_TIME_BASE_DIV[] = {
	 { "MICROSECOND_TIME_BASE_DIV", 0, 6, &umr_bitfield_default },
	 { "XTAL_REF_DIV", 8, 14, &umr_bitfield_default },
	 { "XTAL_REF_SEL", 16, 16, &umr_bitfield_default },
	 { "XTAL_REF_CLOCK_SOURCE_SEL", 17, 17, &umr_bitfield_default },
	 { "MICROSECOND_TIME_BASE_CLOCK_SOURCE_SEL", 20, 20, &umr_bitfield_default },
};
static struct umr_bitfield mmDCCG_GATE_DISABLE_CNTL2[] = {
	 { "SYMCLKA_FE_GATE_DISABLE", 0, 0, &umr_bitfield_default },
	 { "SYMCLKB_FE_GATE_DISABLE", 1, 1, &umr_bitfield_default },
	 { "SYMCLKC_FE_GATE_DISABLE", 2, 2, &umr_bitfield_default },
	 { "SYMCLKD_FE_GATE_DISABLE", 3, 3, &umr_bitfield_default },
	 { "SYMCLKE_FE_GATE_DISABLE", 4, 4, &umr_bitfield_default },
	 { "SYMCLKF_FE_GATE_DISABLE", 5, 5, &umr_bitfield_default },
	 { "SYMCLKG_FE_GATE_DISABLE", 6, 6, &umr_bitfield_default },
	 { "SYMCLKA_GATE_DISABLE", 16, 16, &umr_bitfield_default },
	 { "SYMCLKB_GATE_DISABLE", 17, 17, &umr_bitfield_default },
	 { "SYMCLKC_GATE_DISABLE", 18, 18, &umr_bitfield_default },
	 { "SYMCLKD_GATE_DISABLE", 19, 19, &umr_bitfield_default },
	 { "SYMCLKE_GATE_DISABLE", 20, 20, &umr_bitfield_default },
	 { "SYMCLKF_GATE_DISABLE", 21, 21, &umr_bitfield_default },
	 { "SYMCLKG_GATE_DISABLE", 22, 22, &umr_bitfield_default },
};
static struct umr_bitfield mmSYMCLK_CGTT_BLK_CTRL_REG[] = {
	 { "SYMCLK_TURN_ON_DELAY", 0, 3, &umr_bitfield_default },
	 { "SYMCLK_TURN_OFF_DELAY", 4, 11, &umr_bitfield_default },
};
static struct umr_bitfield mmPHYPLLF_PIXCLK_RESYNC_CNTL[] = {
	 { "PHYPLLF_PIXCLK_RESYNC_ENABLE", 0, 0, &umr_bitfield_default },
	 { "PHYPLLF_DCCG_DEEP_COLOR_CNTL", 4, 5, &umr_bitfield_default },
	 { "PHYPLLF_PIXCLK_ENABLE", 8, 8, &umr_bitfield_default },
};
static struct umr_bitfield mmDCCG_DISP_CNTL_REG[] = {
	 { "ALLOW_SR_ON_TRANS_REQ", 8, 8, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG0_PIXEL_RATE_CNTL[] = {
	 { "OTG0_PIXEL_RATE_SOURCE", 0, 1, &umr_bitfield_default },
	 { "DP_DTO0_ENABLE", 4, 4, &umr_bitfield_default },
	 { "DP_DTO0_DS_DISABLE", 5, 5, &umr_bitfield_default },
	 { "OTG0_ADD_PIXEL", 8, 8, &umr_bitfield_default },
	 { "OTG0_DROP_PIXEL", 9, 9, &umr_bitfield_default },
	 { "OTG0_DISPOUT_FIFO_ERROR", 14, 15, &umr_bitfield_default },
	 { "OTG0_DISPOUT_ERROR_COUNT", 16, 27, &umr_bitfield_default },
};
static struct umr_bitfield mmDP_DTO0_PHASE[] = {
	 { "DP_DTO0_PHASE", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDP_DTO0_MODULO[] = {
	 { "DP_DTO0_MODULO", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG0_PHYPLL_PIXEL_RATE_CNTL[] = {
	 { "OTG0_PHYPLL_PIXEL_RATE_SOURCE", 0, 2, &umr_bitfield_default },
	 { "OTG0_PIXEL_RATE_PLL_SOURCE", 4, 4, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG1_PIXEL_RATE_CNTL[] = {
	 { "OTG1_PIXEL_RATE_SOURCE", 0, 1, &umr_bitfield_default },
	 { "DP_DTO1_ENABLE", 4, 4, &umr_bitfield_default },
	 { "DP_DTO1_DS_DISABLE", 5, 5, &umr_bitfield_default },
	 { "OTG1_ADD_PIXEL", 8, 8, &umr_bitfield_default },
	 { "OTG1_DROP_PIXEL", 9, 9, &umr_bitfield_default },
	 { "OTG1_DISPOUT_FIFO_ERROR", 14, 15, &umr_bitfield_default },
	 { "OTG1_DISPOUT_ERROR_COUNT", 16, 27, &umr_bitfield_default },
};
static struct umr_bitfield mmDP_DTO1_PHASE[] = {
	 { "DP_DTO1_PHASE", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDP_DTO1_MODULO[] = {
	 { "DP_DTO1_MODULO", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG1_PHYPLL_PIXEL_RATE_CNTL[] = {
	 { "OTG1_PHYPLL_PIXEL_RATE_SOURCE", 0, 2, &umr_bitfield_default },
	 { "OTG1_PIXEL_RATE_PLL_SOURCE", 4, 4, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG2_PIXEL_RATE_CNTL[] = {
	 { "OTG2_PIXEL_RATE_SOURCE", 0, 1, &umr_bitfield_default },
	 { "DP_DTO2_ENABLE", 4, 4, &umr_bitfield_default },
	 { "DP_DTO2_DS_DISABLE", 5, 5, &umr_bitfield_default },
	 { "OTG2_ADD_PIXEL", 8, 8, &umr_bitfield_default },
	 { "OTG2_DROP_PIXEL", 9, 9, &umr_bitfield_default },
	 { "OTG2_DISPOUT_FIFO_ERROR", 14, 15, &umr_bitfield_default },
	 { "OTG2_DISPOUT_ERROR_COUNT", 16, 27, &umr_bitfield_default },
};
static struct umr_bitfield mmDP_DTO2_PHASE[] = {
	 { "DP_DTO2_PHASE", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDP_DTO2_MODULO[] = {
	 { "DP_DTO2_MODULO", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG2_PHYPLL_PIXEL_RATE_CNTL[] = {
	 { "OTG2_PHYPLL_PIXEL_RATE_SOURCE", 0, 2, &umr_bitfield_default },
	 { "OTG2_PIXEL_RATE_PLL_SOURCE", 4, 4, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG3_PIXEL_RATE_CNTL[] = {
	 { "OTG3_PIXEL_RATE_SOURCE", 0, 1, &umr_bitfield_default },
	 { "DP_DTO3_ENABLE", 4, 4, &umr_bitfield_default },
	 { "DP_DTO3_DS_DISABLE", 5, 5, &umr_bitfield_default },
	 { "OTG3_ADD_PIXEL", 8, 8, &umr_bitfield_default },
	 { "OTG3_DROP_PIXEL", 9, 9, &umr_bitfield_default },
	 { "OTG3_DISPOUT_FIFO_ERROR", 14, 15, &umr_bitfield_default },
	 { "OTG3_DISPOUT_ERROR_COUNT", 16, 27, &umr_bitfield_default },
};
static struct umr_bitfield mmDP_DTO3_PHASE[] = {
	 { "DP_DTO3_PHASE", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDP_DTO3_MODULO[] = {
	 { "DP_DTO3_MODULO", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG3_PHYPLL_PIXEL_RATE_CNTL[] = {
	 { "OTG3_PHYPLL_PIXEL_RATE_SOURCE", 0, 2, &umr_bitfield_default },
	 { "OTG3_PIXEL_RATE_PLL_SOURCE", 4, 4, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG4_PIXEL_RATE_CNTL[] = {
	 { "OTG4_PIXEL_RATE_SOURCE", 0, 1, &umr_bitfield_default },
	 { "DP_DTO4_ENABLE", 4, 4, &umr_bitfield_default },
	 { "DP_DTO4_DS_DISABLE", 5, 5, &umr_bitfield_default },
	 { "OTG4_ADD_PIXEL", 8, 8, &umr_bitfield_default },
	 { "OTG4_DROP_PIXEL", 9, 9, &umr_bitfield_default },
	 { "OTG4_DISPOUT_FIFO_ERROR", 14, 15, &umr_bitfield_default },
	 { "OTG4_DISPOUT_ERROR_COUNT", 16, 27, &umr_bitfield_default },
};
static struct umr_bitfield mmDP_DTO4_PHASE[] = {
	 { "DP_DTO4_PHASE", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDP_DTO4_MODULO[] = {
	 { "DP_DTO4_MODULO", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG4_PHYPLL_PIXEL_RATE_CNTL[] = {
	 { "OTG4_PHYPLL_PIXEL_RATE_SOURCE", 0, 2, &umr_bitfield_default },
	 { "OTG4_PIXEL_RATE_PLL_SOURCE", 4, 4, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG5_PIXEL_RATE_CNTL[] = {
	 { "OTG5_PIXEL_RATE_SOURCE", 0, 1, &umr_bitfield_default },
	 { "DP_DTO5_ENABLE", 4, 4, &umr_bitfield_default },
	 { "DP_DTO5_DS_DISABLE", 5, 5, &umr_bitfield_default },
	 { "OTG5_ADD_PIXEL", 8, 8, &umr_bitfield_default },
	 { "OTG5_DROP_PIXEL", 9, 9, &umr_bitfield_default },
	 { "OTG5_DISPOUT_FIFO_ERROR", 14, 15, &umr_bitfield_default },
	 { "OTG5_DISPOUT_ERROR_COUNT", 16, 27, &umr_bitfield_default },
};
static struct umr_bitfield mmDP_DTO5_PHASE[] = {
	 { "DP_DTO5_PHASE", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDP_DTO5_MODULO[] = {
	 { "DP_DTO5_MODULO", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG5_PHYPLL_PIXEL_RATE_CNTL[] = {
	 { "OTG5_PHYPLL_PIXEL_RATE_SOURCE", 0, 2, &umr_bitfield_default },
	 { "OTG5_PIXEL_RATE_PLL_SOURCE", 4, 4, &umr_bitfield_default },
};
static struct umr_bitfield mmDPPCLK_CGTT_BLK_CTRL_REG[] = {
	 { "DPPCLK_TURN_ON_DELAY", 0, 3, &umr_bitfield_default },
	 { "DPPCLK_TURN_OFF_DELAY", 4, 11, &umr_bitfield_default },
};
static struct umr_bitfield mmSYMCLKA_CLOCK_ENABLE[] = {
	 { "SYMCLKA_CLOCK_ENABLE", 0, 0, &umr_bitfield_default },
	 { "SYMCLKA_FE_FORCE_EN", 4, 4, &umr_bitfield_default },
	 { "SYMCLKA_FE_FORCE_SRC", 8, 10, &umr_bitfield_default },
};
static struct umr_bitfield mmSYMCLKB_CLOCK_ENABLE[] = {
	 { "SYMCLKB_CLOCK_ENABLE", 0, 0, &umr_bitfield_default },
	 { "SYMCLKB_FE_FORCE_EN", 4, 4, &umr_bitfield_default },
	 { "SYMCLKB_FE_FORCE_SRC", 8, 10, &umr_bitfield_default },
};
static struct umr_bitfield mmSYMCLKC_CLOCK_ENABLE[] = {
	 { "SYMCLKC_CLOCK_ENABLE", 0, 0, &umr_bitfield_default },
	 { "SYMCLKC_FE_FORCE_EN", 4, 4, &umr_bitfield_default },
	 { "SYMCLKC_FE_FORCE_SRC", 8, 10, &umr_bitfield_default },
};
static struct umr_bitfield mmSYMCLKD_CLOCK_ENABLE[] = {
	 { "SYMCLKD_CLOCK_ENABLE", 0, 0, &umr_bitfield_default },
	 { "SYMCLKD_FE_FORCE_EN", 4, 4, &umr_bitfield_default },
	 { "SYMCLKD_FE_FORCE_SRC", 8, 10, &umr_bitfield_default },
};
static struct umr_bitfield mmSYMCLKE_CLOCK_ENABLE[] = {
	 { "SYMCLKE_CLOCK_ENABLE", 0, 0, &umr_bitfield_default },
	 { "SYMCLKE_FE_FORCE_EN", 4, 4, &umr_bitfield_default },
	 { "SYMCLKE_FE_FORCE_SRC", 8, 10, &umr_bitfield_default },
};
static struct umr_bitfield mmSYMCLKF_CLOCK_ENABLE[] = {
	 { "SYMCLKF_CLOCK_ENABLE", 0, 0, &umr_bitfield_default },
	 { "SYMCLKF_FE_FORCE_EN", 4, 4, &umr_bitfield_default },
	 { "SYMCLKF_FE_FORCE_SRC", 8, 10, &umr_bitfield_default },
};
static struct umr_bitfield mmDCCG_SOFT_RESET[] = {
	 { "REFCLK_SOFT_RESET", 0, 0, &umr_bitfield_default },
	 { "PCIE_REFCLK_SOFT_RESET", 1, 1, &umr_bitfield_default },
	 { "SOFT_RESET_DVO", 2, 2, &umr_bitfield_default },
	 { "DVO_ENABLE_RST", 3, 3, &umr_bitfield_default },
	 { "AUDIO_DTO2_CLK_SOFT_RESET", 4, 4, &umr_bitfield_default },
	 { "DPREFCLK_SOFT_RESET", 8, 8, &umr_bitfield_default },
	 { "AMCLK0_SOFT_RESET", 12, 12, &umr_bitfield_default },
	 { "AMCLK1_SOFT_RESET", 13, 13, &umr_bitfield_default },
	 { "P0PLL_CFG_IF_SOFT_RESET", 14, 14, &umr_bitfield_default },
	 { "P1PLL_CFG_IF_SOFT_RESET", 15, 15, &umr_bitfield_default },
	 { "P2PLL_CFG_IF_SOFT_RESET", 16, 16, &umr_bitfield_default },
	 { "A0PLL_CFG_IF_SOFT_RESET", 17, 17, &umr_bitfield_default },
	 { "A1PLL_CFG_IF_SOFT_RESET", 18, 18, &umr_bitfield_default },
	 { "C0PLL_CFG_IF_SOFT_RESET", 19, 19, &umr_bitfield_default },
	 { "C1PLL_CFG_IF_SOFT_RESET", 20, 20, &umr_bitfield_default },
	 { "C2PLL_CFG_IF_SOFT_RESET", 21, 21, &umr_bitfield_default },
};
static struct umr_bitfield mmDVOACLKD_CNTL[] = {
	 { "DVOACLKD_FINE_SKEW_CNTL", 0, 2, &umr_bitfield_default },
	 { "DVOACLKD_COARSE_SKEW_CNTL", 8, 12, &umr_bitfield_default },
	 { "DVOACLKD_FINE_ADJUST_EN", 16, 16, &umr_bitfield_default },
	 { "DVOACLKD_COARSE_ADJUST_EN", 17, 17, &umr_bitfield_default },
	 { "DVOACLKD_IN_PHASE", 18, 18, &umr_bitfield_default },
};
static struct umr_bitfield mmDVOACLKC_MVP_CNTL[] = {
	 { "DVOACLKC_MVP_FINE_SKEW_CNTL", 0, 2, &umr_bitfield_default },
	 { "DVOACLKC_MVP_COARSE_SKEW_CNTL", 8, 12, &umr_bitfield_default },
	 { "DVOACLKC_MVP_FINE_ADJUST_EN", 16, 16, &umr_bitfield_default },
	 { "DVOACLKC_MVP_COARSE_ADJUST_EN", 17, 17, &umr_bitfield_default },
	 { "DVOACLKC_MVP_IN_PHASE", 18, 18, &umr_bitfield_default },
	 { "DVOACLKC_MVP_SKEW_PHASE_OVERRIDE", 20, 20, &umr_bitfield_default },
};
static struct umr_bitfield mmDVOACLKC_CNTL[] = {
	 { "DVOACLKC_FINE_SKEW_CNTL", 0, 2, &umr_bitfield_default },
	 { "DVOACLKC_COARSE_SKEW_CNTL", 8, 12, &umr_bitfield_default },
	 { "DVOACLKC_FINE_ADJUST_EN", 16, 16, &umr_bitfield_default },
	 { "DVOACLKC_COARSE_ADJUST_EN", 17, 17, &umr_bitfield_default },
	 { "DVOACLKC_IN_PHASE", 18, 18, &umr_bitfield_default },
};
static struct umr_bitfield mmDCCG_AUDIO_DTO_SOURCE[] = {
	 { "DCCG_AUDIO_DTO0_SOURCE_SEL", 0, 2, &umr_bitfield_default },
	 { "DCCG_AUDIO_DTO_SEL", 4, 5, &umr_bitfield_default },
	 { "DCCG_AUDIO_DTO2_SOURCE_SEL", 12, 13, &umr_bitfield_default },
	 { "DCCG_AUDIO_DTO2_CLOCK_EN", 16, 16, &umr_bitfield_default },
	 { "DCCG_AUDIO_DTO2_USE_512FBR_DTO", 20, 20, &umr_bitfield_default },
	 { "DCCG_AUDIO_DTO0_USE_512FBR_DTO", 24, 24, &umr_bitfield_default },
	 { "DCCG_AUDIO_DTO1_USE_512FBR_DTO", 28, 28, &umr_bitfield_default },
};
static struct umr_bitfield mmDCCG_AUDIO_DTO0_PHASE[] = {
	 { "DCCG_AUDIO_DTO0_PHASE", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCCG_AUDIO_DTO0_MODULE[] = {
	 { "DCCG_AUDIO_DTO0_MODULE", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCCG_AUDIO_DTO1_PHASE[] = {
	 { "DCCG_AUDIO_DTO1_PHASE", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCCG_AUDIO_DTO1_MODULE[] = {
	 { "DCCG_AUDIO_DTO1_MODULE", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCCG_VSYNC_OTG0_LATCH_VALUE[] = {
	 { "DCCG_VSYNC_CNT_OTG0_LATCH_VALUE", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCCG_VSYNC_OTG1_LATCH_VALUE[] = {
	 { "DCCG_VSYNC_CNT_OTG1_LATCH_VALUE", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCCG_VSYNC_OTG2_LATCH_VALUE[] = {
	 { "DCCG_VSYNC_CNT_OTG2_LATCH_VALUE", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCCG_VSYNC_OTG3_LATCH_VALUE[] = {
	 { "DCCG_VSYNC_CNT_OTG3_LATCH_VALUE", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCCG_VSYNC_OTG4_LATCH_VALUE[] = {
	 { "DCCG_VSYNC_CNT_OTG4_LATCH_VALUE", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCCG_VSYNC_OTG5_LATCH_VALUE[] = {
	 { "DCCG_VSYNC_CNT_OTG5_LATCH_VALUE", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCCG_VSYNC_CNT_CTRL[] = {
	 { "DCCG_VSYNC_CNT_ENABLE", 0, 0, &umr_bitfield_default },
	 { "DCCG_VSYNC_CNT_REFCLK_SEL", 1, 1, &umr_bitfield_default },
	 { "DCCG_VSYNC_CNT_SW_RESET", 2, 2, &umr_bitfield_default },
	 { "DCCG_VSYNC_CNT_RESET_SEL", 3, 3, &umr_bitfield_default },
	 { "DCCG_VSYNC_CNT_EXT_TRIG_SEL", 4, 7, &umr_bitfield_default },
	 { "DCCG_VSYNC_CNT_FRAME_CNT", 8, 11, &umr_bitfield_default },
	 { "DCCG_VSYNC_OTG0_LATCH_EN", 16, 16, &umr_bitfield_default },
	 { "DCCG_VSYNC_OTG1_LATCH_EN", 17, 17, &umr_bitfield_default },
	 { "DCCG_VSYNC_OTG2_LATCH_EN", 18, 18, &umr_bitfield_default },
	 { "DCCG_VSYNC_OTG3_LATCH_EN", 19, 19, &umr_bitfield_default },
	 { "DCCG_VSYNC_OTG4_LATCH_EN", 20, 20, &umr_bitfield_default },
	 { "DCCG_VSYNC_OTG5_LATCH_EN", 21, 21, &umr_bitfield_default },
	 { "DCCG_VSYNC_OTG0_VSYNC_TRIG_SEL", 24, 24, &umr_bitfield_default },
	 { "DCCG_VSYNC_OTG1_VSYNC_TRIG_SEL", 25, 25, &umr_bitfield_default },
	 { "DCCG_VSYNC_OTG2_VSYNC_TRIG_SEL", 26, 26, &umr_bitfield_default },
	 { "DCCG_VSYNC_OTG3_VSYNC_TRIG_SEL", 27, 27, &umr_bitfield_default },
	 { "DCCG_VSYNC_OTG4_VSYNC_TRIG_SEL", 28, 28, &umr_bitfield_default },
	 { "DCCG_VSYNC_OTG5_VSYNC_TRIG_SEL", 29, 29, &umr_bitfield_default },
};
static struct umr_bitfield mmDCCG_VSYNC_CNT_INT_CTRL[] = {
	 { "DCCG_VSYNC_CNT_OTG0_LATCH_INTERRUPT", 0, 0, &umr_bitfield_default },
	 { "DCCG_VSYNC_CNT_OTG0_LATCH_INTERRUPT_CLEAR", 0, 0, &umr_bitfield_default },
	 { "DCCG_VSYNC_CNT_OTG1_LATCH_INTERRUPT", 1, 1, &umr_bitfield_default },
	 { "DCCG_VSYNC_CNT_OTG1_LATCH_INTERRUPT_CLEAR", 1, 1, &umr_bitfield_default },
	 { "DCCG_VSYNC_CNT_OTG2_LATCH_INTERRUPT", 2, 2, &umr_bitfield_default },
	 { "DCCG_VSYNC_CNT_OTG2_LATCH_INTERRUPT_CLEAR", 2, 2, &umr_bitfield_default },
	 { "DCCG_VSYNC_CNT_OTG3_LATCH_INTERRUPT", 3, 3, &umr_bitfield_default },
	 { "DCCG_VSYNC_CNT_OTG3_LATCH_INTERRUPT_CLEAR", 3, 3, &umr_bitfield_default },
	 { "DCCG_VSYNC_CNT_OTG4_LATCH_INTERRUPT", 4, 4, &umr_bitfield_default },
	 { "DCCG_VSYNC_CNT_OTG4_LATCH_INTERRUPT_CLEAR", 4, 4, &umr_bitfield_default },
	 { "DCCG_VSYNC_CNT_OTG5_LATCH_INTERRUPT", 5, 5, &umr_bitfield_default },
	 { "DCCG_VSYNC_CNT_OTG5_LATCH_INTERRUPT_CLEAR", 5, 5, &umr_bitfield_default },
	 { "DCCG_VSYNC_CNT_OTG0_LATCH_MASK", 8, 8, &umr_bitfield_default },
	 { "DCCG_VSYNC_CNT_OTG1_LATCH_MASK", 9, 9, &umr_bitfield_default },
	 { "DCCG_VSYNC_CNT_OTG2_LATCH_MASK", 10, 10, &umr_bitfield_default },
	 { "DCCG_VSYNC_CNT_OTG3_LATCH_MASK", 11, 11, &umr_bitfield_default },
	 { "DCCG_VSYNC_CNT_OTG4_LATCH_MASK", 12, 12, &umr_bitfield_default },
	 { "DCCG_VSYNC_CNT_OTG5_LATCH_MASK", 13, 13, &umr_bitfield_default },
};
static struct umr_bitfield mmDCCG_TEST_CLK_SEL[] = {
	 { "DCCG_TEST_CLK_GENERICA_SEL", 0, 8, &umr_bitfield_default },
	 { "DCCG_TEST_CLK_GENERICA_INV", 12, 12, &umr_bitfield_default },
	 { "DCCG_TEST_CLK_GENERICB_SEL", 16, 24, &umr_bitfield_default },
	 { "DCCG_TEST_CLK_GENERICB_INV", 28, 28, &umr_bitfield_default },
};
static struct umr_bitfield mmDENTIST_DISPCLK_CNTL[] = {
	 { "DENTIST_DISPCLK_WDIVIDER", 0, 6, &umr_bitfield_default },
	 { "DENTIST_DISPCLK_RDIVIDER", 8, 14, &umr_bitfield_default },
	 { "DENTIST_DISPCLK_CHG_MODE", 15, 16, &umr_bitfield_default },
	 { "DENTIST_DISPCLK_CHGTOG", 17, 17, &umr_bitfield_default },
	 { "DENTIST_DISPCLK_DONETOG", 18, 18, &umr_bitfield_default },
	 { "DENTIST_DISPCLK_CHG_DONE", 19, 19, &umr_bitfield_default },
	 { "DENTIST_DPREFCLK_CHG_DONE", 20, 20, &umr_bitfield_default },
	 { "DENTIST_DPREFCLK_CHGTOG", 21, 21, &umr_bitfield_default },
	 { "DENTIST_DPREFCLK_DONETOG", 22, 22, &umr_bitfield_default },
	 { "DENTIST_DPREFCLK_WDIVIDER", 24, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_PERFMON0_PERFCOUNTER_CNTL[] = {
	 { "PERFCOUNTER_EVENT_SEL", 0, 8, &umr_bitfield_default },
	 { "PERFCOUNTER_CVALUE_SEL", 9, 11, &umr_bitfield_default },
	 { "PERFCOUNTER_INC_MODE", 12, 14, &umr_bitfield_default },
	 { "PERFCOUNTER_HW_CNTL_SEL", 15, 15, &umr_bitfield_default },
	 { "PERFCOUNTER_RUNEN_MODE", 16, 16, &umr_bitfield_default },
	 { "PERFCOUNTER_CNTOFF_START_DIS", 22, 22, &umr_bitfield_default },
	 { "PERFCOUNTER_RESTART_EN", 23, 23, &umr_bitfield_default },
	 { "PERFCOUNTER_INT_EN", 24, 24, &umr_bitfield_default },
	 { "PERFCOUNTER_OFF_MASK", 25, 25, &umr_bitfield_default },
	 { "PERFCOUNTER_ACTIVE", 26, 26, &umr_bitfield_default },
	 { "PERFCOUNTER_CNTL_SEL", 29, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_PERFMON0_PERFCOUNTER_CNTL2[] = {
	 { "PERFCOUNTER_COUNTED_VALUE_TYPE", 0, 1, &umr_bitfield_default },
	 { "PERFCOUNTER_HW_STOP1_SEL", 2, 2, &umr_bitfield_default },
	 { "PERFCOUNTER_HW_STOP2_SEL", 3, 3, &umr_bitfield_default },
	 { "PERFCOUNTER_CNTOFF_SEL", 8, 13, &umr_bitfield_default },
	 { "PERFCOUNTER_CNTL2_SEL", 29, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_PERFMON0_PERFCOUNTER_STATE[] = {
	 { "PERFCOUNTER_CNT0_STATE", 0, 1, &umr_bitfield_default },
	 { "PERFCOUNTER_STATE_SEL0", 2, 2, &umr_bitfield_default },
	 { "PERFCOUNTER_CNT1_STATE", 4, 5, &umr_bitfield_default },
	 { "PERFCOUNTER_STATE_SEL1", 6, 6, &umr_bitfield_default },
	 { "PERFCOUNTER_CNT2_STATE", 8, 9, &umr_bitfield_default },
	 { "PERFCOUNTER_STATE_SEL2", 10, 10, &umr_bitfield_default },
	 { "PERFCOUNTER_CNT3_STATE", 12, 13, &umr_bitfield_default },
	 { "PERFCOUNTER_STATE_SEL3", 14, 14, &umr_bitfield_default },
	 { "PERFCOUNTER_CNT4_STATE", 16, 17, &umr_bitfield_default },
	 { "PERFCOUNTER_STATE_SEL4", 18, 18, &umr_bitfield_default },
	 { "PERFCOUNTER_CNT5_STATE", 20, 21, &umr_bitfield_default },
	 { "PERFCOUNTER_STATE_SEL5", 22, 22, &umr_bitfield_default },
	 { "PERFCOUNTER_CNT6_STATE", 24, 25, &umr_bitfield_default },
	 { "PERFCOUNTER_STATE_SEL6", 26, 26, &umr_bitfield_default },
	 { "PERFCOUNTER_CNT7_STATE", 28, 29, &umr_bitfield_default },
	 { "PERFCOUNTER_STATE_SEL7", 30, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_PERFMON0_PERFMON_CNTL[] = {
	 { "PERFMON_STATE", 0, 1, &umr_bitfield_default },
	 { "PERFMON_RPT_COUNT", 8, 27, &umr_bitfield_default },
	 { "PERFMON_CNTOFF_AND_OR", 28, 28, &umr_bitfield_default },
	 { "PERFMON_CNTOFF_INT_EN", 29, 29, &umr_bitfield_default },
	 { "PERFMON_CNTOFF_INT_STATUS", 30, 30, &umr_bitfield_default },
	 { "PERFMON_CNTOFF_INT_ACK", 31, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_PERFMON0_PERFMON_CNTL2[] = {
	 { "PERFMON_CNTOFF_INT_TYPE", 0, 0, &umr_bitfield_default },
	 { "PERFMON_CLK_ENABLE", 1, 1, &umr_bitfield_default },
	 { "PERFMON_RUN_ENABLE_START_SEL", 2, 9, &umr_bitfield_default },
	 { "PERFMON_RUN_ENABLE_STOP_SEL", 10, 17, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_PERFMON0_PERFMON_CVALUE_INT_MISC[] = {
	 { "PERFCOUNTER_INT0_STATUS", 0, 0, &umr_bitfield_default },
	 { "PERFCOUNTER_INT1_STATUS", 1, 1, &umr_bitfield_default },
	 { "PERFCOUNTER_INT2_STATUS", 2, 2, &umr_bitfield_default },
	 { "PERFCOUNTER_INT3_STATUS", 3, 3, &umr_bitfield_default },
	 { "PERFCOUNTER_INT4_STATUS", 4, 4, &umr_bitfield_default },
	 { "PERFCOUNTER_INT5_STATUS", 5, 5, &umr_bitfield_default },
	 { "PERFCOUNTER_INT6_STATUS", 6, 6, &umr_bitfield_default },
	 { "PERFCOUNTER_INT7_STATUS", 7, 7, &umr_bitfield_default },
	 { "PERFCOUNTER_INT0_ACK", 8, 8, &umr_bitfield_default },
	 { "PERFCOUNTER_INT1_ACK", 9, 9, &umr_bitfield_default },
	 { "PERFCOUNTER_INT2_ACK", 10, 10, &umr_bitfield_default },
	 { "PERFCOUNTER_INT3_ACK", 11, 11, &umr_bitfield_default },
	 { "PERFCOUNTER_INT4_ACK", 12, 12, &umr_bitfield_default },
	 { "PERFCOUNTER_INT5_ACK", 13, 13, &umr_bitfield_default },
	 { "PERFCOUNTER_INT6_ACK", 14, 14, &umr_bitfield_default },
	 { "PERFCOUNTER_INT7_ACK", 15, 15, &umr_bitfield_default },
	 { "PERFMON_CVALUE_HI", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_PERFMON0_PERFMON_CVALUE_LOW[] = {
	 { "PERFMON_CVALUE_LOW", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_PERFMON0_PERFMON_HI[] = {
	 { "PERFMON_HI", 0, 15, &umr_bitfield_default },
	 { "PERFMON_READ_SEL", 29, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_PERFMON0_PERFMON_LOW[] = {
	 { "PERFMON_LOW", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_PERFMON1_PERFCOUNTER_CNTL[] = {
	 { "PERFCOUNTER_EVENT_SEL", 0, 8, &umr_bitfield_default },
	 { "PERFCOUNTER_CVALUE_SEL", 9, 11, &umr_bitfield_default },
	 { "PERFCOUNTER_INC_MODE", 12, 14, &umr_bitfield_default },
	 { "PERFCOUNTER_HW_CNTL_SEL", 15, 15, &umr_bitfield_default },
	 { "PERFCOUNTER_RUNEN_MODE", 16, 16, &umr_bitfield_default },
	 { "PERFCOUNTER_CNTOFF_START_DIS", 22, 22, &umr_bitfield_default },
	 { "PERFCOUNTER_RESTART_EN", 23, 23, &umr_bitfield_default },
	 { "PERFCOUNTER_INT_EN", 24, 24, &umr_bitfield_default },
	 { "PERFCOUNTER_OFF_MASK", 25, 25, &umr_bitfield_default },
	 { "PERFCOUNTER_ACTIVE", 26, 26, &umr_bitfield_default },
	 { "PERFCOUNTER_CNTL_SEL", 29, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_PERFMON1_PERFCOUNTER_CNTL2[] = {
	 { "PERFCOUNTER_COUNTED_VALUE_TYPE", 0, 1, &umr_bitfield_default },
	 { "PERFCOUNTER_HW_STOP1_SEL", 2, 2, &umr_bitfield_default },
	 { "PERFCOUNTER_HW_STOP2_SEL", 3, 3, &umr_bitfield_default },
	 { "PERFCOUNTER_CNTOFF_SEL", 8, 13, &umr_bitfield_default },
	 { "PERFCOUNTER_CNTL2_SEL", 29, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_PERFMON1_PERFCOUNTER_STATE[] = {
	 { "PERFCOUNTER_CNT0_STATE", 0, 1, &umr_bitfield_default },
	 { "PERFCOUNTER_STATE_SEL0", 2, 2, &umr_bitfield_default },
	 { "PERFCOUNTER_CNT1_STATE", 4, 5, &umr_bitfield_default },
	 { "PERFCOUNTER_STATE_SEL1", 6, 6, &umr_bitfield_default },
	 { "PERFCOUNTER_CNT2_STATE", 8, 9, &umr_bitfield_default },
	 { "PERFCOUNTER_STATE_SEL2", 10, 10, &umr_bitfield_default },
	 { "PERFCOUNTER_CNT3_STATE", 12, 13, &umr_bitfield_default },
	 { "PERFCOUNTER_STATE_SEL3", 14, 14, &umr_bitfield_default },
	 { "PERFCOUNTER_CNT4_STATE", 16, 17, &umr_bitfield_default },
	 { "PERFCOUNTER_STATE_SEL4", 18, 18, &umr_bitfield_default },
	 { "PERFCOUNTER_CNT5_STATE", 20, 21, &umr_bitfield_default },
	 { "PERFCOUNTER_STATE_SEL5", 22, 22, &umr_bitfield_default },
	 { "PERFCOUNTER_CNT6_STATE", 24, 25, &umr_bitfield_default },
	 { "PERFCOUNTER_STATE_SEL6", 26, 26, &umr_bitfield_default },
	 { "PERFCOUNTER_CNT7_STATE", 28, 29, &umr_bitfield_default },
	 { "PERFCOUNTER_STATE_SEL7", 30, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_PERFMON1_PERFMON_CNTL[] = {
	 { "PERFMON_STATE", 0, 1, &umr_bitfield_default },
	 { "PERFMON_RPT_COUNT", 8, 27, &umr_bitfield_default },
	 { "PERFMON_CNTOFF_AND_OR", 28, 28, &umr_bitfield_default },
	 { "PERFMON_CNTOFF_INT_EN", 29, 29, &umr_bitfield_default },
	 { "PERFMON_CNTOFF_INT_STATUS", 30, 30, &umr_bitfield_default },
	 { "PERFMON_CNTOFF_INT_ACK", 31, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_PERFMON1_PERFMON_CNTL2[] = {
	 { "PERFMON_CNTOFF_INT_TYPE", 0, 0, &umr_bitfield_default },
	 { "PERFMON_CLK_ENABLE", 1, 1, &umr_bitfield_default },
	 { "PERFMON_RUN_ENABLE_START_SEL", 2, 9, &umr_bitfield_default },
	 { "PERFMON_RUN_ENABLE_STOP_SEL", 10, 17, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_PERFMON1_PERFMON_CVALUE_INT_MISC[] = {
	 { "PERFCOUNTER_INT0_STATUS", 0, 0, &umr_bitfield_default },
	 { "PERFCOUNTER_INT1_STATUS", 1, 1, &umr_bitfield_default },
	 { "PERFCOUNTER_INT2_STATUS", 2, 2, &umr_bitfield_default },
	 { "PERFCOUNTER_INT3_STATUS", 3, 3, &umr_bitfield_default },
	 { "PERFCOUNTER_INT4_STATUS", 4, 4, &umr_bitfield_default },
	 { "PERFCOUNTER_INT5_STATUS", 5, 5, &umr_bitfield_default },
	 { "PERFCOUNTER_INT6_STATUS", 6, 6, &umr_bitfield_default },
	 { "PERFCOUNTER_INT7_STATUS", 7, 7, &umr_bitfield_default },
	 { "PERFCOUNTER_INT0_ACK", 8, 8, &umr_bitfield_default },
	 { "PERFCOUNTER_INT1_ACK", 9, 9, &umr_bitfield_default },
	 { "PERFCOUNTER_INT2_ACK", 10, 10, &umr_bitfield_default },
	 { "PERFCOUNTER_INT3_ACK", 11, 11, &umr_bitfield_default },
	 { "PERFCOUNTER_INT4_ACK", 12, 12, &umr_bitfield_default },
	 { "PERFCOUNTER_INT5_ACK", 13, 13, &umr_bitfield_default },
	 { "PERFCOUNTER_INT6_ACK", 14, 14, &umr_bitfield_default },
	 { "PERFCOUNTER_INT7_ACK", 15, 15, &umr_bitfield_default },
	 { "PERFMON_CVALUE_HI", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_PERFMON1_PERFMON_CVALUE_LOW[] = {
	 { "PERFMON_CVALUE_LOW", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_PERFMON1_PERFMON_HI[] = {
	 { "PERFMON_HI", 0, 15, &umr_bitfield_default },
	 { "PERFMON_READ_SEL", 29, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_PERFMON1_PERFMON_LOW[] = {
	 { "PERFMON_LOW", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmPLL_MACRO_CNTL_RESERVED0[] = {
	 { "PLL_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmPLL_MACRO_CNTL_RESERVED1[] = {
	 { "PLL_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmPLL_MACRO_CNTL_RESERVED2[] = {
	 { "PLL_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmPLL_MACRO_CNTL_RESERVED3[] = {
	 { "PLL_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmPLL_MACRO_CNTL_RESERVED4[] = {
	 { "PLL_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmPLL_MACRO_CNTL_RESERVED5[] = {
	 { "PLL_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmPLL_MACRO_CNTL_RESERVED6[] = {
	 { "PLL_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmPLL_MACRO_CNTL_RESERVED7[] = {
	 { "PLL_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmPLL_MACRO_CNTL_RESERVED8[] = {
	 { "PLL_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmPLL_MACRO_CNTL_RESERVED9[] = {
	 { "PLL_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmPLL_MACRO_CNTL_RESERVED10[] = {
	 { "PLL_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmPLL_MACRO_CNTL_RESERVED11[] = {
	 { "PLL_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmPLL_MACRO_CNTL_RESERVED12[] = {
	 { "PLL_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmPLL_MACRO_CNTL_RESERVED13[] = {
	 { "PLL_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmPLL_MACRO_CNTL_RESERVED14[] = {
	 { "PLL_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmPLL_MACRO_CNTL_RESERVED15[] = {
	 { "PLL_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmPLL_MACRO_CNTL_RESERVED16[] = {
	 { "PLL_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmPLL_MACRO_CNTL_RESERVED17[] = {
	 { "PLL_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmPLL_MACRO_CNTL_RESERVED18[] = {
	 { "PLL_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmPLL_MACRO_CNTL_RESERVED19[] = {
	 { "PLL_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmPLL_MACRO_CNTL_RESERVED20[] = {
	 { "PLL_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmPLL_MACRO_CNTL_RESERVED21[] = {
	 { "PLL_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmPLL_MACRO_CNTL_RESERVED22[] = {
	 { "PLL_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmPLL_MACRO_CNTL_RESERVED23[] = {
	 { "PLL_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmPLL_MACRO_CNTL_RESERVED24[] = {
	 { "PLL_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmPLL_MACRO_CNTL_RESERVED25[] = {
	 { "PLL_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmPLL_MACRO_CNTL_RESERVED26[] = {
	 { "PLL_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmPLL_MACRO_CNTL_RESERVED27[] = {
	 { "PLL_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmPLL_MACRO_CNTL_RESERVED28[] = {
	 { "PLL_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmPLL_MACRO_CNTL_RESERVED29[] = {
	 { "PLL_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmPLL_MACRO_CNTL_RESERVED30[] = {
	 { "PLL_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmPLL_MACRO_CNTL_RESERVED31[] = {
	 { "PLL_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmPLL_MACRO_CNTL_RESERVED32[] = {
	 { "PLL_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmPLL_MACRO_CNTL_RESERVED33[] = {
	 { "PLL_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmPLL_MACRO_CNTL_RESERVED34[] = {
	 { "PLL_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmPLL_MACRO_CNTL_RESERVED35[] = {
	 { "PLL_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmPLL_MACRO_CNTL_RESERVED36[] = {
	 { "PLL_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmPLL_MACRO_CNTL_RESERVED37[] = {
	 { "PLL_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmPLL_MACRO_CNTL_RESERVED38[] = {
	 { "PLL_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmPLL_MACRO_CNTL_RESERVED39[] = {
	 { "PLL_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmPLL_MACRO_CNTL_RESERVED40[] = {
	 { "PLL_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmPLL_MACRO_CNTL_RESERVED41[] = {
	 { "PLL_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmRBBMIF_TIMEOUT[] = {
	 { "RBBMIF_TIMEOUT_DELAY", 0, 19, &umr_bitfield_default },
	 { "RBBMIF_TIMEOUT_TO_REQ_HOLD", 20, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmRBBMIF_STATUS[] = {
	 { "RBBMIF_TIMEOUT_CLIENTS_DEC", 0, 29, &umr_bitfield_default },
};
static struct umr_bitfield mmRBBMIF_INT_STATUS[] = {
	 { "RBBMIF_TIMEOUT_OP", 28, 28, &umr_bitfield_default },
	 { "RBBMIF_TIMEOUT_RDWR_STATUS", 29, 29, &umr_bitfield_default },
	 { "RBBMIF_TIMEOUT_ACK", 30, 30, &umr_bitfield_default },
	 { "RBBMIF_TIMEOUT_MASK", 31, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmRBBMIF_TIMEOUT_DIS[] = {
	 { "CLIENT0_TIMEOUT_DIS", 0, 0, &umr_bitfield_default },
	 { "CLIENT1_TIMEOUT_DIS", 1, 1, &umr_bitfield_default },
	 { "CLIENT2_TIMEOUT_DIS", 2, 2, &umr_bitfield_default },
	 { "CLIENT3_TIMEOUT_DIS", 3, 3, &umr_bitfield_default },
	 { "CLIENT4_TIMEOUT_DIS", 4, 4, &umr_bitfield_default },
	 { "CLIENT5_TIMEOUT_DIS", 5, 5, &umr_bitfield_default },
	 { "CLIENT6_TIMEOUT_DIS", 6, 6, &umr_bitfield_default },
	 { "CLIENT7_TIMEOUT_DIS", 7, 7, &umr_bitfield_default },
	 { "CLIENT8_TIMEOUT_DIS", 8, 8, &umr_bitfield_default },
	 { "CLIENT9_TIMEOUT_DIS", 9, 9, &umr_bitfield_default },
	 { "CLIENT10_TIMEOUT_DIS", 10, 10, &umr_bitfield_default },
	 { "CLIENT11_TIMEOUT_DIS", 11, 11, &umr_bitfield_default },
	 { "CLIENT12_TIMEOUT_DIS", 12, 12, &umr_bitfield_default },
	 { "CLIENT13_TIMEOUT_DIS", 13, 13, &umr_bitfield_default },
	 { "CLIENT14_TIMEOUT_DIS", 14, 14, &umr_bitfield_default },
	 { "CLIENT15_TIMEOUT_DIS", 15, 15, &umr_bitfield_default },
	 { "CLIENT16_TIMEOUT_DIS", 16, 16, &umr_bitfield_default },
	 { "CLIENT17_TIMEOUT_DIS", 17, 17, &umr_bitfield_default },
	 { "CLIENT18_TIMEOUT_DIS", 18, 18, &umr_bitfield_default },
	 { "CLIENT19_TIMEOUT_DIS", 19, 19, &umr_bitfield_default },
	 { "CLIENT20_TIMEOUT_DIS", 20, 20, &umr_bitfield_default },
	 { "CLIENT21_TIMEOUT_DIS", 21, 21, &umr_bitfield_default },
	 { "CLIENT22_TIMEOUT_DIS", 22, 22, &umr_bitfield_default },
	 { "CLIENT23_TIMEOUT_DIS", 23, 23, &umr_bitfield_default },
	 { "CLIENT24_TIMEOUT_DIS", 24, 24, &umr_bitfield_default },
	 { "CLIENT25_TIMEOUT_DIS", 25, 25, &umr_bitfield_default },
	 { "CLIENT26_TIMEOUT_DIS", 26, 26, &umr_bitfield_default },
	 { "CLIENT27_TIMEOUT_DIS", 27, 27, &umr_bitfield_default },
	 { "CLIENT28_TIMEOUT_DIS", 28, 28, &umr_bitfield_default },
	 { "CLIENT29_TIMEOUT_DIS", 29, 29, &umr_bitfield_default },
};
static struct umr_bitfield mmRBBMIF_STATUS_FLAG[] = {
	 { "RBBMIF_STATE", 0, 1, &umr_bitfield_default },
	 { "RBBMIF_READ_TIMEOUT", 4, 4, &umr_bitfield_default },
	 { "RBBMIF_FIFO_EMPTY", 5, 5, &umr_bitfield_default },
	 { "RBBMIF_FIFO_FULL", 6, 6, &umr_bitfield_default },
	 { "RBBMIF_INVALID_ACCESS_FLAG", 8, 8, &umr_bitfield_default },
	 { "RBBMIF_INVALID_ACCESS_TYPE", 9, 11, &umr_bitfield_default },
	 { "RBBMIF_INVALID_ACCESS_ADDR", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDOMAIN0_PG_CONFIG[] = {
	 { "DOMAIN0_POWER_FORCEON", 0, 0, &umr_bitfield_default },
	 { "DOMAIN0_POWER_GATE", 8, 8, &umr_bitfield_default },
};
static struct umr_bitfield mmDOMAIN0_PG_STATUS[] = {
	 { "DOMAIN0_DESIRED_PWR_STATE", 28, 28, &umr_bitfield_default },
	 { "DOMAIN0_PGFSM_PWR_STATUS", 30, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDOMAIN1_PG_CONFIG[] = {
	 { "DOMAIN1_POWER_FORCEON", 0, 0, &umr_bitfield_default },
	 { "DOMAIN1_POWER_GATE", 8, 8, &umr_bitfield_default },
};
static struct umr_bitfield mmDOMAIN1_PG_STATUS[] = {
	 { "DOMAIN1_DESIRED_PWR_STATE", 28, 28, &umr_bitfield_default },
	 { "DOMAIN1_PGFSM_PWR_STATUS", 30, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDOMAIN2_PG_CONFIG[] = {
	 { "DOMAIN2_POWER_FORCEON", 0, 0, &umr_bitfield_default },
	 { "DOMAIN2_POWER_GATE", 8, 8, &umr_bitfield_default },
};
static struct umr_bitfield mmDOMAIN2_PG_STATUS[] = {
	 { "DOMAIN2_DESIRED_PWR_STATE", 28, 28, &umr_bitfield_default },
	 { "DOMAIN2_PGFSM_PWR_STATUS", 30, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDOMAIN3_PG_CONFIG[] = {
	 { "DOMAIN3_POWER_FORCEON", 0, 0, &umr_bitfield_default },
	 { "DOMAIN3_POWER_GATE", 8, 8, &umr_bitfield_default },
};
static struct umr_bitfield mmDOMAIN3_PG_STATUS[] = {
	 { "DOMAIN3_DESIRED_PWR_STATE", 28, 28, &umr_bitfield_default },
	 { "DOMAIN3_PGFSM_PWR_STATUS", 30, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDOMAIN4_PG_CONFIG[] = {
	 { "DOMAIN4_POWER_FORCEON", 0, 0, &umr_bitfield_default },
	 { "DOMAIN4_POWER_GATE", 8, 8, &umr_bitfield_default },
};
static struct umr_bitfield mmDOMAIN4_PG_STATUS[] = {
	 { "DOMAIN4_DESIRED_PWR_STATE", 28, 28, &umr_bitfield_default },
	 { "DOMAIN4_PGFSM_PWR_STATUS", 30, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDOMAIN5_PG_CONFIG[] = {
	 { "DOMAIN5_POWER_FORCEON", 0, 0, &umr_bitfield_default },
	 { "DOMAIN5_POWER_GATE", 8, 8, &umr_bitfield_default },
};
static struct umr_bitfield mmDOMAIN5_PG_STATUS[] = {
	 { "DOMAIN5_DESIRED_PWR_STATE", 28, 28, &umr_bitfield_default },
	 { "DOMAIN5_PGFSM_PWR_STATUS", 30, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDOMAIN6_PG_CONFIG[] = {
	 { "DOMAIN6_POWER_FORCEON", 0, 0, &umr_bitfield_default },
	 { "DOMAIN6_POWER_GATE", 8, 8, &umr_bitfield_default },
};
static struct umr_bitfield mmDOMAIN6_PG_STATUS[] = {
	 { "DOMAIN6_DESIRED_PWR_STATE", 28, 28, &umr_bitfield_default },
	 { "DOMAIN6_PGFSM_PWR_STATUS", 30, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDOMAIN7_PG_CONFIG[] = {
	 { "DOMAIN7_POWER_FORCEON", 0, 0, &umr_bitfield_default },
	 { "DOMAIN7_POWER_GATE", 8, 8, &umr_bitfield_default },
};
static struct umr_bitfield mmDOMAIN7_PG_STATUS[] = {
	 { "DOMAIN7_DESIRED_PWR_STATE", 28, 28, &umr_bitfield_default },
	 { "DOMAIN7_PGFSM_PWR_STATUS", 30, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDOMAIN8_PG_CONFIG[] = {
	 { "DOMAIN8_POWER_FORCEON", 0, 0, &umr_bitfield_default },
	 { "DOMAIN8_POWER_GATE", 8, 8, &umr_bitfield_default },
};
static struct umr_bitfield mmDOMAIN8_PG_STATUS[] = {
	 { "DOMAIN8_DESIRED_PWR_STATE", 28, 28, &umr_bitfield_default },
	 { "DOMAIN8_PGFSM_PWR_STATUS", 30, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDOMAIN9_PG_CONFIG[] = {
	 { "DOMAIN9_POWER_FORCEON", 0, 0, &umr_bitfield_default },
	 { "DOMAIN9_POWER_GATE", 8, 8, &umr_bitfield_default },
};
static struct umr_bitfield mmDOMAIN9_PG_STATUS[] = {
	 { "DOMAIN9_DESIRED_PWR_STATE", 28, 28, &umr_bitfield_default },
	 { "DOMAIN9_PGFSM_PWR_STATUS", 30, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDOMAIN10_PG_CONFIG[] = {
	 { "DOMAIN10_POWER_FORCEON", 0, 0, &umr_bitfield_default },
	 { "DOMAIN10_POWER_GATE", 8, 8, &umr_bitfield_default },
};
static struct umr_bitfield mmDOMAIN10_PG_STATUS[] = {
	 { "DOMAIN10_DESIRED_PWR_STATE", 28, 28, &umr_bitfield_default },
	 { "DOMAIN10_PGFSM_PWR_STATUS", 30, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDOMAIN11_PG_CONFIG[] = {
	 { "DOMAIN11_POWER_FORCEON", 0, 0, &umr_bitfield_default },
	 { "DOMAIN11_POWER_GATE", 8, 8, &umr_bitfield_default },
};
static struct umr_bitfield mmDOMAIN11_PG_STATUS[] = {
	 { "DOMAIN11_DESIRED_PWR_STATE", 28, 28, &umr_bitfield_default },
	 { "DOMAIN11_PGFSM_PWR_STATUS", 30, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDOMAIN12_PG_CONFIG[] = {
	 { "DOMAIN12_POWER_FORCEON", 0, 0, &umr_bitfield_default },
	 { "DOMAIN12_POWER_GATE", 8, 8, &umr_bitfield_default },
};
static struct umr_bitfield mmDOMAIN12_PG_STATUS[] = {
	 { "DOMAIN12_DESIRED_PWR_STATE", 28, 28, &umr_bitfield_default },
	 { "DOMAIN12_PGFSM_PWR_STATUS", 30, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDOMAIN13_PG_CONFIG[] = {
	 { "DOMAIN13_POWER_FORCEON", 0, 0, &umr_bitfield_default },
	 { "DOMAIN13_POWER_GATE", 8, 8, &umr_bitfield_default },
};
static struct umr_bitfield mmDOMAIN13_PG_STATUS[] = {
	 { "DOMAIN13_DESIRED_PWR_STATE", 28, 28, &umr_bitfield_default },
	 { "DOMAIN13_PGFSM_PWR_STATUS", 30, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDOMAIN14_PG_CONFIG[] = {
	 { "DOMAIN14_POWER_FORCEON", 0, 0, &umr_bitfield_default },
	 { "DOMAIN14_POWER_GATE", 8, 8, &umr_bitfield_default },
};
static struct umr_bitfield mmDOMAIN14_PG_STATUS[] = {
	 { "DOMAIN14_DESIRED_PWR_STATE", 28, 28, &umr_bitfield_default },
	 { "DOMAIN14_PGFSM_PWR_STATUS", 30, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDOMAIN15_PG_CONFIG[] = {
	 { "DOMAIN15_POWER_FORCEON", 0, 0, &umr_bitfield_default },
	 { "DOMAIN15_POWER_GATE", 8, 8, &umr_bitfield_default },
};
static struct umr_bitfield mmDOMAIN15_PG_STATUS[] = {
	 { "DOMAIN15_DESIRED_PWR_STATE", 28, 28, &umr_bitfield_default },
	 { "DOMAIN15_PGFSM_PWR_STATUS", 30, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCPG_INTERRUPT_STATUS[] = {
	 { "DOMAIN0_POWER_UP_INT_OCCURRED", 0, 0, &umr_bitfield_default },
	 { "DOMAIN0_POWER_DOWN_INT_OCCURRED", 1, 1, &umr_bitfield_default },
	 { "DOMAIN1_POWER_UP_INT_OCCURRED", 2, 2, &umr_bitfield_default },
	 { "DOMAIN1_POWER_DOWN_INT_OCCURRED", 3, 3, &umr_bitfield_default },
	 { "DOMAIN2_POWER_UP_INT_OCCURRED", 4, 4, &umr_bitfield_default },
	 { "DOMAIN2_POWER_DOWN_INT_OCCURRED", 5, 5, &umr_bitfield_default },
	 { "DOMAIN3_POWER_UP_INT_OCCURRED", 6, 6, &umr_bitfield_default },
	 { "DOMAIN3_POWER_DOWN_INT_OCCURRED", 7, 7, &umr_bitfield_default },
	 { "DOMAIN4_POWER_UP_INT_OCCURRED", 8, 8, &umr_bitfield_default },
	 { "DOMAIN4_POWER_DOWN_INT_OCCURRED", 9, 9, &umr_bitfield_default },
	 { "DOMAIN5_POWER_UP_INT_OCCURRED", 10, 10, &umr_bitfield_default },
	 { "DOMAIN5_POWER_DOWN_INT_OCCURRED", 11, 11, &umr_bitfield_default },
	 { "DOMAIN6_POWER_UP_INT_OCCURRED", 12, 12, &umr_bitfield_default },
	 { "DOMAIN6_POWER_DOWN_INT_OCCURRED", 13, 13, &umr_bitfield_default },
	 { "DOMAIN7_POWER_UP_INT_OCCURRED", 14, 14, &umr_bitfield_default },
	 { "DOMAIN7_POWER_DOWN_INT_OCCURRED", 15, 15, &umr_bitfield_default },
	 { "DOMAIN8_POWER_UP_INT_OCCURRED", 16, 16, &umr_bitfield_default },
	 { "DOMAIN8_POWER_DOWN_INT_OCCURRED", 17, 17, &umr_bitfield_default },
	 { "DOMAIN9_POWER_UP_INT_OCCURRED", 18, 18, &umr_bitfield_default },
	 { "DOMAIN9_POWER_DOWN_INT_OCCURRED", 19, 19, &umr_bitfield_default },
	 { "DOMAIN10_POWER_UP_INT_OCCURRED", 20, 20, &umr_bitfield_default },
	 { "DOMAIN10_POWER_DOWN_INT_OCCURRED", 21, 21, &umr_bitfield_default },
	 { "DOMAIN11_POWER_UP_INT_OCCURRED", 22, 22, &umr_bitfield_default },
	 { "DOMAIN11_POWER_DOWN_INT_OCCURRED", 23, 23, &umr_bitfield_default },
	 { "DOMAIN12_POWER_UP_INT_OCCURRED", 24, 24, &umr_bitfield_default },
	 { "DOMAIN12_POWER_DOWN_INT_OCCURRED", 25, 25, &umr_bitfield_default },
	 { "DOMAIN13_POWER_UP_INT_OCCURRED", 26, 26, &umr_bitfield_default },
	 { "DOMAIN13_POWER_DOWN_INT_OCCURRED", 27, 27, &umr_bitfield_default },
	 { "DOMAIN14_POWER_UP_INT_OCCURRED", 28, 28, &umr_bitfield_default },
	 { "DOMAIN14_POWER_DOWN_INT_OCCURRED", 29, 29, &umr_bitfield_default },
	 { "DOMAIN15_POWER_UP_INT_OCCURRED", 30, 30, &umr_bitfield_default },
	 { "DOMAIN15_POWER_DOWN_INT_OCCURRED", 31, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCPG_INTERRUPT_CONTROL_1[] = {
	 { "DOMAIN0_POWER_UP_INT_MASK", 0, 0, &umr_bitfield_default },
	 { "DOMAIN0_POWER_UP_INT_CLEAR", 1, 1, &umr_bitfield_default },
	 { "DOMAIN0_POWER_DOWN_INT_MASK", 2, 2, &umr_bitfield_default },
	 { "DOMAIN0_POWER_DOWN_INT_CLEAR", 3, 3, &umr_bitfield_default },
	 { "DOMAIN1_POWER_UP_INT_MASK", 4, 4, &umr_bitfield_default },
	 { "DOMAIN1_POWER_UP_INT_CLEAR", 5, 5, &umr_bitfield_default },
	 { "DOMAIN1_POWER_DOWN_INT_MASK", 6, 6, &umr_bitfield_default },
	 { "DOMAIN1_POWER_DOWN_INT_CLEAR", 7, 7, &umr_bitfield_default },
	 { "DOMAIN2_POWER_UP_INT_MASK", 8, 8, &umr_bitfield_default },
	 { "DOMAIN2_POWER_UP_INT_CLEAR", 9, 9, &umr_bitfield_default },
	 { "DOMAIN2_POWER_DOWN_INT_MASK", 10, 10, &umr_bitfield_default },
	 { "DOMAIN2_POWER_DOWN_INT_CLEAR", 11, 11, &umr_bitfield_default },
	 { "DOMAIN3_POWER_UP_INT_MASK", 12, 12, &umr_bitfield_default },
	 { "DOMAIN3_POWER_UP_INT_CLEAR", 13, 13, &umr_bitfield_default },
	 { "DOMAIN3_POWER_DOWN_INT_MASK", 14, 14, &umr_bitfield_default },
	 { "DOMAIN3_POWER_DOWN_INT_CLEAR", 15, 15, &umr_bitfield_default },
	 { "DOMAIN4_POWER_UP_INT_MASK", 16, 16, &umr_bitfield_default },
	 { "DOMAIN4_POWER_UP_INT_CLEAR", 17, 17, &umr_bitfield_default },
	 { "DOMAIN4_POWER_DOWN_INT_MASK", 18, 18, &umr_bitfield_default },
	 { "DOMAIN4_POWER_DOWN_INT_CLEAR", 19, 19, &umr_bitfield_default },
	 { "DOMAIN5_POWER_UP_INT_MASK", 20, 20, &umr_bitfield_default },
	 { "DOMAIN5_POWER_UP_INT_CLEAR", 21, 21, &umr_bitfield_default },
	 { "DOMAIN5_POWER_DOWN_INT_MASK", 22, 22, &umr_bitfield_default },
	 { "DOMAIN5_POWER_DOWN_INT_CLEAR", 23, 23, &umr_bitfield_default },
	 { "DOMAIN6_POWER_UP_INT_MASK", 24, 24, &umr_bitfield_default },
	 { "DOMAIN6_POWER_UP_INT_CLEAR", 25, 25, &umr_bitfield_default },
	 { "DOMAIN6_POWER_DOWN_INT_MASK", 26, 26, &umr_bitfield_default },
	 { "DOMAIN6_POWER_DOWN_INT_CLEAR", 27, 27, &umr_bitfield_default },
	 { "DOMAIN7_POWER_UP_INT_MASK", 28, 28, &umr_bitfield_default },
	 { "DOMAIN7_POWER_UP_INT_CLEAR", 29, 29, &umr_bitfield_default },
	 { "DOMAIN7_POWER_DOWN_INT_MASK", 30, 30, &umr_bitfield_default },
	 { "DOMAIN7_POWER_DOWN_INT_CLEAR", 31, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCPG_INTERRUPT_CONTROL_2[] = {
	 { "DOMAIN8_POWER_UP_INT_MASK", 0, 0, &umr_bitfield_default },
	 { "DOMAIN8_POWER_UP_INT_CLEAR", 1, 1, &umr_bitfield_default },
	 { "DOMAIN8_POWER_DOWN_INT_MASK", 2, 2, &umr_bitfield_default },
	 { "DOMAIN8_POWER_DOWN_INT_CLEAR", 3, 3, &umr_bitfield_default },
	 { "DOMAIN9_POWER_UP_INT_MASK", 4, 4, &umr_bitfield_default },
	 { "DOMAIN9_POWER_UP_INT_CLEAR", 5, 5, &umr_bitfield_default },
	 { "DOMAIN9_POWER_DOWN_INT_MASK", 6, 6, &umr_bitfield_default },
	 { "DOMAIN9_POWER_DOWN_INT_CLEAR", 7, 7, &umr_bitfield_default },
	 { "DOMAIN10_POWER_UP_INT_MASK", 8, 8, &umr_bitfield_default },
	 { "DOMAIN10_POWER_UP_INT_CLEAR", 9, 9, &umr_bitfield_default },
	 { "DOMAIN10_POWER_DOWN_INT_MASK", 10, 10, &umr_bitfield_default },
	 { "DOMAIN10_POWER_DOWN_INT_CLEAR", 11, 11, &umr_bitfield_default },
	 { "DOMAIN11_POWER_UP_INT_MASK", 12, 12, &umr_bitfield_default },
	 { "DOMAIN11_POWER_UP_INT_CLEAR", 13, 13, &umr_bitfield_default },
	 { "DOMAIN11_POWER_DOWN_INT_MASK", 14, 14, &umr_bitfield_default },
	 { "DOMAIN11_POWER_DOWN_INT_CLEAR", 15, 15, &umr_bitfield_default },
	 { "DOMAIN12_POWER_UP_INT_MASK", 16, 16, &umr_bitfield_default },
	 { "DOMAIN12_POWER_UP_INT_CLEAR", 17, 17, &umr_bitfield_default },
	 { "DOMAIN12_POWER_DOWN_INT_MASK", 18, 18, &umr_bitfield_default },
	 { "DOMAIN12_POWER_DOWN_INT_CLEAR", 19, 19, &umr_bitfield_default },
	 { "DOMAIN13_POWER_UP_INT_MASK", 20, 20, &umr_bitfield_default },
	 { "DOMAIN13_POWER_UP_INT_CLEAR", 21, 21, &umr_bitfield_default },
	 { "DOMAIN13_POWER_DOWN_INT_MASK", 22, 22, &umr_bitfield_default },
	 { "DOMAIN13_POWER_DOWN_INT_CLEAR", 23, 23, &umr_bitfield_default },
	 { "DOMAIN14_POWER_UP_INT_MASK", 24, 24, &umr_bitfield_default },
	 { "DOMAIN14_POWER_UP_INT_CLEAR", 25, 25, &umr_bitfield_default },
	 { "DOMAIN14_POWER_DOWN_INT_MASK", 26, 26, &umr_bitfield_default },
	 { "DOMAIN14_POWER_DOWN_INT_CLEAR", 27, 27, &umr_bitfield_default },
	 { "DOMAIN15_POWER_UP_INT_MASK", 28, 28, &umr_bitfield_default },
	 { "DOMAIN15_POWER_UP_INT_CLEAR", 29, 29, &umr_bitfield_default },
	 { "DOMAIN15_POWER_DOWN_INT_MASK", 30, 30, &umr_bitfield_default },
	 { "DOMAIN15_POWER_DOWN_INT_CLEAR", 31, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_IP_REQUEST_CNTL[] = {
	 { "IP_REQUEST_EN", 0, 0, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_PERFMON2_PERFCOUNTER_CNTL[] = {
	 { "PERFCOUNTER_EVENT_SEL", 0, 8, &umr_bitfield_default },
	 { "PERFCOUNTER_CVALUE_SEL", 9, 11, &umr_bitfield_default },
	 { "PERFCOUNTER_INC_MODE", 12, 14, &umr_bitfield_default },
	 { "PERFCOUNTER_HW_CNTL_SEL", 15, 15, &umr_bitfield_default },
	 { "PERFCOUNTER_RUNEN_MODE", 16, 16, &umr_bitfield_default },
	 { "PERFCOUNTER_CNTOFF_START_DIS", 22, 22, &umr_bitfield_default },
	 { "PERFCOUNTER_RESTART_EN", 23, 23, &umr_bitfield_default },
	 { "PERFCOUNTER_INT_EN", 24, 24, &umr_bitfield_default },
	 { "PERFCOUNTER_OFF_MASK", 25, 25, &umr_bitfield_default },
	 { "PERFCOUNTER_ACTIVE", 26, 26, &umr_bitfield_default },
	 { "PERFCOUNTER_CNTL_SEL", 29, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_PERFMON2_PERFCOUNTER_CNTL2[] = {
	 { "PERFCOUNTER_COUNTED_VALUE_TYPE", 0, 1, &umr_bitfield_default },
	 { "PERFCOUNTER_HW_STOP1_SEL", 2, 2, &umr_bitfield_default },
	 { "PERFCOUNTER_HW_STOP2_SEL", 3, 3, &umr_bitfield_default },
	 { "PERFCOUNTER_CNTOFF_SEL", 8, 13, &umr_bitfield_default },
	 { "PERFCOUNTER_CNTL2_SEL", 29, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_PERFMON2_PERFCOUNTER_STATE[] = {
	 { "PERFCOUNTER_CNT0_STATE", 0, 1, &umr_bitfield_default },
	 { "PERFCOUNTER_STATE_SEL0", 2, 2, &umr_bitfield_default },
	 { "PERFCOUNTER_CNT1_STATE", 4, 5, &umr_bitfield_default },
	 { "PERFCOUNTER_STATE_SEL1", 6, 6, &umr_bitfield_default },
	 { "PERFCOUNTER_CNT2_STATE", 8, 9, &umr_bitfield_default },
	 { "PERFCOUNTER_STATE_SEL2", 10, 10, &umr_bitfield_default },
	 { "PERFCOUNTER_CNT3_STATE", 12, 13, &umr_bitfield_default },
	 { "PERFCOUNTER_STATE_SEL3", 14, 14, &umr_bitfield_default },
	 { "PERFCOUNTER_CNT4_STATE", 16, 17, &umr_bitfield_default },
	 { "PERFCOUNTER_STATE_SEL4", 18, 18, &umr_bitfield_default },
	 { "PERFCOUNTER_CNT5_STATE", 20, 21, &umr_bitfield_default },
	 { "PERFCOUNTER_STATE_SEL5", 22, 22, &umr_bitfield_default },
	 { "PERFCOUNTER_CNT6_STATE", 24, 25, &umr_bitfield_default },
	 { "PERFCOUNTER_STATE_SEL6", 26, 26, &umr_bitfield_default },
	 { "PERFCOUNTER_CNT7_STATE", 28, 29, &umr_bitfield_default },
	 { "PERFCOUNTER_STATE_SEL7", 30, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_PERFMON2_PERFMON_CNTL[] = {
	 { "PERFMON_STATE", 0, 1, &umr_bitfield_default },
	 { "PERFMON_RPT_COUNT", 8, 27, &umr_bitfield_default },
	 { "PERFMON_CNTOFF_AND_OR", 28, 28, &umr_bitfield_default },
	 { "PERFMON_CNTOFF_INT_EN", 29, 29, &umr_bitfield_default },
	 { "PERFMON_CNTOFF_INT_STATUS", 30, 30, &umr_bitfield_default },
	 { "PERFMON_CNTOFF_INT_ACK", 31, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_PERFMON2_PERFMON_CNTL2[] = {
	 { "PERFMON_CNTOFF_INT_TYPE", 0, 0, &umr_bitfield_default },
	 { "PERFMON_CLK_ENABLE", 1, 1, &umr_bitfield_default },
	 { "PERFMON_RUN_ENABLE_START_SEL", 2, 9, &umr_bitfield_default },
	 { "PERFMON_RUN_ENABLE_STOP_SEL", 10, 17, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_PERFMON2_PERFMON_CVALUE_INT_MISC[] = {
	 { "PERFCOUNTER_INT0_STATUS", 0, 0, &umr_bitfield_default },
	 { "PERFCOUNTER_INT1_STATUS", 1, 1, &umr_bitfield_default },
	 { "PERFCOUNTER_INT2_STATUS", 2, 2, &umr_bitfield_default },
	 { "PERFCOUNTER_INT3_STATUS", 3, 3, &umr_bitfield_default },
	 { "PERFCOUNTER_INT4_STATUS", 4, 4, &umr_bitfield_default },
	 { "PERFCOUNTER_INT5_STATUS", 5, 5, &umr_bitfield_default },
	 { "PERFCOUNTER_INT6_STATUS", 6, 6, &umr_bitfield_default },
	 { "PERFCOUNTER_INT7_STATUS", 7, 7, &umr_bitfield_default },
	 { "PERFCOUNTER_INT0_ACK", 8, 8, &umr_bitfield_default },
	 { "PERFCOUNTER_INT1_ACK", 9, 9, &umr_bitfield_default },
	 { "PERFCOUNTER_INT2_ACK", 10, 10, &umr_bitfield_default },
	 { "PERFCOUNTER_INT3_ACK", 11, 11, &umr_bitfield_default },
	 { "PERFCOUNTER_INT4_ACK", 12, 12, &umr_bitfield_default },
	 { "PERFCOUNTER_INT5_ACK", 13, 13, &umr_bitfield_default },
	 { "PERFCOUNTER_INT6_ACK", 14, 14, &umr_bitfield_default },
	 { "PERFCOUNTER_INT7_ACK", 15, 15, &umr_bitfield_default },
	 { "PERFMON_CVALUE_HI", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_PERFMON2_PERFMON_CVALUE_LOW[] = {
	 { "PERFMON_CVALUE_LOW", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_PERFMON2_PERFMON_HI[] = {
	 { "PERFMON_HI", 0, 15, &umr_bitfield_default },
	 { "PERFMON_READ_SEL", 29, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_PERFMON2_PERFMON_LOW[] = {
	 { "PERFMON_LOW", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmCC_DC_PIPE_DIS[] = {
	 { "DC_PIPE_DIS", 0, 7, &umr_bitfield_default },
};
static struct umr_bitfield mmDMU_CLK_CNTL[] = {
	 { "DMU_TEST_CLK_SEL", 0, 1, &umr_bitfield_default },
	 { "DISPCLK_R_DMU_GATE_DIS", 2, 2, &umr_bitfield_default },
	 { "DISPCLK_G_DMCU_GATE_DIS", 3, 3, &umr_bitfield_default },
};
static struct umr_bitfield mmDMU_MEM_PWR_CNTL[] = {
	 { "DMCU_ERAM_MEM_PWR_MODE_SEL", 0, 0, &umr_bitfield_default },
	 { "DMCU_ERAM_MEM_PWR_FORCE", 1, 2, &umr_bitfield_default },
	 { "DMCU_ERAM_MEM_PWR_DIS", 3, 3, &umr_bitfield_default },
	 { "DMCU_ERAM_MEM_PWR_STATE", 4, 5, &umr_bitfield_default },
	 { "DMCU_IRAM_MEM_PWR_FORCE", 8, 8, &umr_bitfield_default },
	 { "DMCU_IRAM_MEM_PWR_DIS", 9, 9, &umr_bitfield_default },
	 { "DMCU_IRAM_MEM_PWR_STATE", 10, 10, &umr_bitfield_default },
};
static struct umr_bitfield mmDMCU_SMU_INTERRUPT_CNTL[] = {
	 { "DMCU_SMU_STATIC_SCREEN_INT", 0, 0, &umr_bitfield_default },
	 { "DMCU_SMU_STATIC_SCREEN_STATUS", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSMU_INTERRUPT_CONTROL[] = {
	 { "DC_SMU_INT_ENABLE", 0, 0, &umr_bitfield_default },
	 { "DC_SMU_INT_STATUS", 4, 4, &umr_bitfield_default },
	 { "DC_SMU_INT_EVENT", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDMCU_CTRL[] = {
	 { "RESET_UC", 0, 0, &umr_bitfield_default },
	 { "IGNORE_PWRMGT", 1, 1, &umr_bitfield_default },
	 { "DISABLE_IRQ_TO_UC", 2, 2, &umr_bitfield_default },
	 { "DISABLE_XIRQ_TO_UC", 3, 3, &umr_bitfield_default },
	 { "DMCU_ENABLE", 4, 4, &umr_bitfield_default },
	 { "DMCU_DYN_CLK_GATING_EN", 8, 8, &umr_bitfield_default },
	 { "UC_REG_RD_TIMEOUT", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDMCU_STATUS[] = {
	 { "UC_IN_RESET", 0, 0, &umr_bitfield_default },
	 { "UC_IN_WAIT_MODE", 1, 1, &umr_bitfield_default },
	 { "UC_IN_STOP_MODE", 2, 2, &umr_bitfield_default },
};
static struct umr_bitfield mmDMCU_PC_START_ADDR[] = {
	 { "PC_START_ADDR_LSB", 0, 7, &umr_bitfield_default },
	 { "PC_START_ADDR_MSB", 8, 15, &umr_bitfield_default },
};
static struct umr_bitfield mmDMCU_FW_START_ADDR[] = {
	 { "FW_START_ADDR_LSB", 0, 7, &umr_bitfield_default },
	 { "FW_START_ADDR_MSB", 8, 15, &umr_bitfield_default },
};
static struct umr_bitfield mmDMCU_FW_END_ADDR[] = {
	 { "FW_END_ADDR_LSB", 0, 7, &umr_bitfield_default },
	 { "FW_END_ADDR_MSB", 8, 15, &umr_bitfield_default },
};
static struct umr_bitfield mmDMCU_FW_ISR_START_ADDR[] = {
	 { "FW_ISR_START_ADDR_LSB", 0, 7, &umr_bitfield_default },
	 { "FW_ISR_START_ADDR_MSB", 8, 15, &umr_bitfield_default },
};
static struct umr_bitfield mmDMCU_FW_CS_HI[] = {
	 { "FW_CHECKSUM_HI", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDMCU_FW_CS_LO[] = {
	 { "FW_CHECKSUM_LO", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDMCU_RAM_ACCESS_CTRL[] = {
	 { "ERAM_WR_ADDR_AUTO_INC", 0, 0, &umr_bitfield_default },
	 { "ERAM_RD_ADDR_AUTO_INC", 1, 1, &umr_bitfield_default },
	 { "IRAM_WR_ADDR_AUTO_INC", 2, 2, &umr_bitfield_default },
	 { "IRAM_RD_ADDR_AUTO_INC", 3, 3, &umr_bitfield_default },
	 { "ERAM_HOST_ACCESS_EN", 4, 4, &umr_bitfield_default },
	 { "IRAM_HOST_ACCESS_EN", 5, 5, &umr_bitfield_default },
};
static struct umr_bitfield mmDMCU_ERAM_WR_CTRL[] = {
	 { "ERAM_WR_ADDR", 0, 15, &umr_bitfield_default },
	 { "ERAM_WR_BE", 16, 19, &umr_bitfield_default },
	 { "ERAM_WR_BYTE_MODE", 20, 20, &umr_bitfield_default },
};
static struct umr_bitfield mmDMCU_ERAM_WR_DATA[] = {
	 { "ERAM_WR_DATA", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDMCU_ERAM_RD_CTRL[] = {
	 { "ERAM_RD_ADDR", 0, 15, &umr_bitfield_default },
	 { "ERAM_RD_BE", 16, 19, &umr_bitfield_default },
	 { "ERAM_RD_BYTE_MODE", 20, 20, &umr_bitfield_default },
};
static struct umr_bitfield mmDMCU_ERAM_RD_DATA[] = {
	 { "ERAM_RD_DATA", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDMCU_IRAM_WR_CTRL[] = {
	 { "IRAM_WR_ADDR", 0, 9, &umr_bitfield_default },
};
static struct umr_bitfield mmDMCU_IRAM_WR_DATA[] = {
	 { "IRAM_WR_DATA", 0, 7, &umr_bitfield_default },
};
static struct umr_bitfield mmDMCU_IRAM_RD_CTRL[] = {
	 { "IRAM_RD_ADDR", 0, 9, &umr_bitfield_default },
};
static struct umr_bitfield mmDMCU_IRAM_RD_DATA[] = {
	 { "IRAM_RD_DATA", 0, 7, &umr_bitfield_default },
};
static struct umr_bitfield mmDMCU_EVENT_TRIGGER[] = {
	 { "GEN_SW_INT_TO_UC", 0, 0, &umr_bitfield_default },
	 { "UC_INTERNAL_INT_CODE", 16, 22, &umr_bitfield_default },
	 { "GEN_UC_INTERNAL_INT_TO_HOST", 23, 23, &umr_bitfield_default },
};
static struct umr_bitfield mmDMCU_UC_INTERNAL_INT_STATUS[] = {
	 { "UC_INT_IRQ_N_PIN", 0, 0, &umr_bitfield_default },
	 { "UC_INT_XIRQ_N_PIN", 1, 1, &umr_bitfield_default },
	 { "UC_INT_SOFTWARE_INTERRUPT", 2, 2, &umr_bitfield_default },
	 { "UC_INT_ILLEGAL_OPCODE_TRAP", 3, 3, &umr_bitfield_default },
	 { "UC_INT_TIMER_OUTPUT_COMPARE_4", 4, 4, &umr_bitfield_default },
	 { "UC_INT_TIMER_OUTPUT_COMPARE_3", 5, 5, &umr_bitfield_default },
	 { "UC_INT_TIMER_OUTPUT_COMPARE_2", 6, 6, &umr_bitfield_default },
	 { "UC_INT_TIMER_OUTPUT_COMPARE_1", 7, 7, &umr_bitfield_default },
	 { "UC_INT_TIMER_OVERFLOW", 8, 8, &umr_bitfield_default },
	 { "UC_INT_REAL_TIME_INTERRUPT", 9, 9, &umr_bitfield_default },
	 { "UC_INT_TIMER_INPUT_CAPTURE_4_OUTPUT_COMPARE_5", 10, 10, &umr_bitfield_default },
	 { "UC_INT_TIMER_INPUT_CAPTURE_3", 11, 11, &umr_bitfield_default },
	 { "UC_INT_TIMER_INPUT_CAPTURE_2", 12, 12, &umr_bitfield_default },
	 { "UC_INT_TIMER_INPUT_CAPTURE_1", 13, 13, &umr_bitfield_default },
	 { "UC_INT_PULSE_ACCUMULATOR_INPUT_EDGE", 14, 14, &umr_bitfield_default },
	 { "UC_INT_PULSE_ACCUMULATOR_OVERFLOW", 15, 15, &umr_bitfield_default },
};
static struct umr_bitfield mmDMCU_SS_INTERRUPT_CNTL_STATUS[] = {
	 { "STATIC_SCREEN1_INT_STATUS", 13, 13, &umr_bitfield_default },
	 { "STATIC_SCREEN1_INT_OCCURRED", 14, 14, &umr_bitfield_default },
	 { "STATIC_SCREEN1_INT_CLEAR", 14, 14, &umr_bitfield_default },
	 { "STATIC_SCREEN2_INT_STATUS", 15, 15, &umr_bitfield_default },
	 { "STATIC_SCREEN2_INT_OCCURRED", 16, 16, &umr_bitfield_default },
	 { "STATIC_SCREEN2_INT_CLEAR", 16, 16, &umr_bitfield_default },
	 { "STATIC_SCREEN3_INT_STATUS", 17, 17, &umr_bitfield_default },
	 { "STATIC_SCREEN3_INT_OCCURRED", 18, 18, &umr_bitfield_default },
	 { "STATIC_SCREEN3_INT_CLEAR", 18, 18, &umr_bitfield_default },
	 { "STATIC_SCREEN4_INT_STATUS", 19, 19, &umr_bitfield_default },
	 { "STATIC_SCREEN4_INT_OCCURRED", 20, 20, &umr_bitfield_default },
	 { "STATIC_SCREEN4_INT_CLEAR", 20, 20, &umr_bitfield_default },
	 { "STATIC_SCREEN5_INT_STATUS", 21, 21, &umr_bitfield_default },
	 { "STATIC_SCREEN5_INT_OCCURRED", 22, 22, &umr_bitfield_default },
	 { "STATIC_SCREEN5_INT_CLEAR", 22, 22, &umr_bitfield_default },
	 { "STATIC_SCREEN6_INT_STATUS", 23, 23, &umr_bitfield_default },
	 { "STATIC_SCREEN6_INT_OCCURRED", 24, 24, &umr_bitfield_default },
	 { "STATIC_SCREEN6_INT_CLEAR", 24, 24, &umr_bitfield_default },
};
static struct umr_bitfield mmDMCU_INTERRUPT_STATUS[] = {
	 { "ABM1_HG_READY_INT_OCCURRED", 0, 0, &umr_bitfield_default },
	 { "ABM1_HG_READY_INT_CLEAR", 0, 0, &umr_bitfield_default },
	 { "ABM1_LS_READY_INT_OCCURRED", 1, 1, &umr_bitfield_default },
	 { "ABM1_LS_READY_INT_CLEAR", 1, 1, &umr_bitfield_default },
	 { "ABM1_BL_UPDATE_INT_OCCURRED", 2, 2, &umr_bitfield_default },
	 { "ABM1_BL_UPDATE_INT_CLEAR", 2, 2, &umr_bitfield_default },
	 { "MCP_INT_OCCURRED", 3, 3, &umr_bitfield_default },
	 { "EXTERNAL_SW_INT_OCCURRED", 8, 8, &umr_bitfield_default },
	 { "EXTERNAL_SW_INT_CLEAR", 8, 8, &umr_bitfield_default },
	 { "SCP_INT_OCCURRED", 9, 9, &umr_bitfield_default },
	 { "UC_INTERNAL_INT_OCCURRED", 10, 10, &umr_bitfield_default },
	 { "UC_INTERNAL_INT_CLEAR", 10, 10, &umr_bitfield_default },
	 { "UC_REG_RD_TIMEOUT_INT_OCCURRED", 11, 11, &umr_bitfield_default },
	 { "UC_REG_RD_TIMEOUT_INT_CLEAR", 11, 11, &umr_bitfield_default },
	 { "DCPG_IHC_DOMAIN0_POWER_UP_INT_OCCURRED", 12, 12, &umr_bitfield_default },
	 { "DCPG_IHC_DOMAIN0_POWER_UP_INT_CLEAR", 12, 12, &umr_bitfield_default },
	 { "DCPG_IHC_DOMAIN1_POWER_UP_INT_OCCURRED", 13, 13, &umr_bitfield_default },
	 { "DCPG_IHC_DOMAIN1_POWER_UP_INT_CLEAR", 13, 13, &umr_bitfield_default },
	 { "DCPG_IHC_DOMAIN2_POWER_UP_INT_OCCURRED", 14, 14, &umr_bitfield_default },
	 { "DCPG_IHC_DOMAIN2_POWER_UP_INT_CLEAR", 14, 14, &umr_bitfield_default },
	 { "DCPG_IHC_DOMAIN3_POWER_UP_INT_OCCURRED", 15, 15, &umr_bitfield_default },
	 { "DCPG_IHC_DOMAIN3_POWER_UP_INT_CLEAR", 15, 15, &umr_bitfield_default },
	 { "DCPG_IHC_DOMAIN4_POWER_UP_INT_OCCURRED", 16, 16, &umr_bitfield_default },
	 { "DCPG_IHC_DOMAIN4_POWER_UP_INT_CLEAR", 16, 16, &umr_bitfield_default },
	 { "DCPG_IHC_DOMAIN5_POWER_UP_INT_OCCURRED", 17, 17, &umr_bitfield_default },
	 { "DCPG_IHC_DOMAIN5_POWER_UP_INT_CLEAR", 17, 17, &umr_bitfield_default },
	 { "DCPG_IHC_DOMAIN0_POWER_DOWN_INT_OCCURRED", 18, 18, &umr_bitfield_default },
	 { "DCPG_IHC_DOMAIN0_POWER_DOWN_INT_CLEAR", 18, 18, &umr_bitfield_default },
	 { "DCPG_IHC_DOMAIN1_POWER_DOWN_INT_OCCURRED", 19, 19, &umr_bitfield_default },
	 { "DCPG_IHC_DOMAIN1_POWER_DOWN_INT_CLEAR", 19, 19, &umr_bitfield_default },
	 { "DCPG_IHC_DOMAIN2_POWER_DOWN_INT_OCCURRED", 20, 20, &umr_bitfield_default },
	 { "DCPG_IHC_DOMAIN2_POWER_DOWN_INT_CLEAR", 20, 20, &umr_bitfield_default },
	 { "DCPG_IHC_DOMAIN3_POWER_DOWN_INT_OCCURRED", 21, 21, &umr_bitfield_default },
	 { "DCPG_IHC_DOMAIN3_POWER_DOWN_INT_CLEAR", 21, 21, &umr_bitfield_default },
	 { "DCPG_IHC_DOMAIN4_POWER_DOWN_INT_OCCURRED", 22, 22, &umr_bitfield_default },
	 { "DCPG_IHC_DOMAIN4_POWER_DOWN_INT_CLEAR", 22, 22, &umr_bitfield_default },
	 { "DCPG_IHC_DOMAIN5_POWER_DOWN_INT_OCCURRED", 23, 23, &umr_bitfield_default },
	 { "DCPG_IHC_DOMAIN5_POWER_DOWN_INT_CLEAR", 23, 23, &umr_bitfield_default },
	 { "VBLANK1_INT_OCCURRED", 24, 24, &umr_bitfield_default },
	 { "VBLANK1_INT_CLEAR", 24, 24, &umr_bitfield_default },
	 { "VBLANK2_INT_OCCURRED", 25, 25, &umr_bitfield_default },
	 { "VBLANK2_INT_CLEAR", 25, 25, &umr_bitfield_default },
	 { "VBLANK3_INT_OCCURRED", 26, 26, &umr_bitfield_default },
	 { "VBLANK3_INT_CLEAR", 26, 26, &umr_bitfield_default },
	 { "VBLANK4_INT_OCCURRED", 27, 27, &umr_bitfield_default },
	 { "VBLANK4_INT_CLEAR", 27, 27, &umr_bitfield_default },
	 { "VBLANK5_INT_OCCURRED", 28, 28, &umr_bitfield_default },
	 { "VBLANK5_INT_CLEAR", 28, 28, &umr_bitfield_default },
	 { "VBLANK6_INT_OCCURRED", 29, 29, &umr_bitfield_default },
	 { "VBLANK6_INT_CLEAR", 29, 29, &umr_bitfield_default },
};
static struct umr_bitfield mmDMCU_INTERRUPT_STATUS_1[] = {
	 { "OTG0_RANGE_TIMING_UPDATE_OCCURRED", 6, 6, &umr_bitfield_default },
	 { "OTG0_RANGE_TIMING_UPDATE_CLEAR", 6, 6, &umr_bitfield_default },
	 { "OTG1_RANGE_TIMING_UPDATE_OCCURRED", 7, 7, &umr_bitfield_default },
	 { "OTG1_RANGE_TIMING_UPDATE_CLEAR", 7, 7, &umr_bitfield_default },
	 { "OTG2_RANGE_TIMING_UPDATE_OCCURRED", 8, 8, &umr_bitfield_default },
	 { "OTG2_RANGE_TIMING_UPDATE_CLEAR", 8, 8, &umr_bitfield_default },
	 { "OTG3_RANGE_TIMING_UPDATE_OCCURRED", 9, 9, &umr_bitfield_default },
	 { "OTG3_RANGE_TIMING_UPDATE_CLEAR", 9, 9, &umr_bitfield_default },
	 { "OTG4_RANGE_TIMING_UPDATE_OCCURRED", 10, 10, &umr_bitfield_default },
	 { "OTG4_RANGE_TIMING_UPDATE_CLEAR", 10, 10, &umr_bitfield_default },
	 { "OTG5_RANGE_TIMING_UPDATE_OCCURRED", 11, 11, &umr_bitfield_default },
	 { "OTG5_RANGE_TIMING_UPDATE_CLEAR", 11, 11, &umr_bitfield_default },
	 { "DMCU_GENERIC_INTERRUPT_OCCURRED", 13, 13, &umr_bitfield_default },
	 { "DMCU_GENERIC_INTERRUPT_CLEAR", 13, 13, &umr_bitfield_default },
};
static struct umr_bitfield mmDMCU_INTERRUPT_TO_HOST_EN_MASK[] = {
	 { "ABM0_HG_READY_INT_MASK", 0, 0, &umr_bitfield_default },
	 { "ABM0_LS_READY_INT_MASK", 1, 1, &umr_bitfield_default },
	 { "ABM0_BL_UPDATE_INT_MASK", 2, 2, &umr_bitfield_default },
	 { "ABM1_HG_READY_INT_MASK", 3, 3, &umr_bitfield_default },
	 { "ABM1_LS_READY_INT_MASK", 4, 4, &umr_bitfield_default },
	 { "ABM1_BL_UPDATE_INT_MASK", 5, 5, &umr_bitfield_default },
	 { "SCP_INT_MASK", 9, 9, &umr_bitfield_default },
	 { "UC_INTERNAL_INT_MASK", 10, 10, &umr_bitfield_default },
	 { "UC_REG_RD_TIMEOUT_INT_MASK", 11, 11, &umr_bitfield_default },
};
static struct umr_bitfield mmDMCU_INTERRUPT_TO_UC_EN_MASK[] = {
	 { "ABM1_HG_READY_INT_TO_UC_EN", 0, 0, &umr_bitfield_default },
	 { "ABM1_LS_READY_INT_TO_UC_EN", 1, 1, &umr_bitfield_default },
	 { "ABM1_BL_UPDATE_INT_TO_UC_EN", 2, 2, &umr_bitfield_default },
	 { "MCP_INT_TO_UC_EN", 3, 3, &umr_bitfield_default },
	 { "STATIC_SCREEN1_INT_TO_UC_EN", 6, 6, &umr_bitfield_default },
	 { "STATIC_SCREEN2_INT_TO_UC_EN", 7, 7, &umr_bitfield_default },
	 { "EXTERNAL_SW_INT_TO_UC_EN", 8, 8, &umr_bitfield_default },
	 { "STATIC_SCREEN3_INT_TO_UC_EN", 9, 9, &umr_bitfield_default },
	 { "STATIC_SCREEN4_INT_TO_UC_EN", 10, 10, &umr_bitfield_default },
	 { "STATIC_SCREEN5_INT_TO_UC_EN", 11, 11, &umr_bitfield_default },
	 { "DCPG_IHC_DOMAIN0_POWER_UP_INT_TO_UC_EN", 12, 12, &umr_bitfield_default },
	 { "DCPG_IHC_DOMAIN1_POWER_UP_INT_TO_UC_EN", 13, 13, &umr_bitfield_default },
	 { "DCPG_IHC_DOMAIN2_POWER_UP_INT_TO_UC_EN", 14, 14, &umr_bitfield_default },
	 { "DCPG_IHC_DOMAIN3_POWER_UP_INT_TO_UC_EN", 15, 15, &umr_bitfield_default },
	 { "DCPG_IHC_DOMAIN4_POWER_UP_INT_TO_UC_EN", 16, 16, &umr_bitfield_default },
	 { "DCPG_IHC_DOMAIN5_POWER_UP_INT_TO_UC_EN", 17, 17, &umr_bitfield_default },
	 { "DCPG_IHC_DOMAIN0_POWER_DOWN_INT_TO_UC_EN", 18, 18, &umr_bitfield_default },
	 { "DCPG_IHC_DOMAIN1_POWER_DOWN_INT_TO_UC_EN", 19, 19, &umr_bitfield_default },
	 { "DCPG_IHC_DOMAIN2_POWER_DOWN_INT_TO_UC_EN", 20, 20, &umr_bitfield_default },
	 { "DCPG_IHC_DOMAIN3_POWER_DOWN_INT_TO_UC_EN", 21, 21, &umr_bitfield_default },
	 { "DCPG_IHC_DOMAIN4_POWER_DOWN_INT_TO_UC_EN", 22, 22, &umr_bitfield_default },
	 { "DCPG_IHC_DOMAIN5_POWER_DOWN_INT_TO_UC_EN", 23, 23, &umr_bitfield_default },
	 { "VBLANK1_INT_TO_UC_EN", 24, 24, &umr_bitfield_default },
	 { "VBLANK2_INT_TO_UC_EN", 25, 25, &umr_bitfield_default },
	 { "VBLANK3_INT_TO_UC_EN", 26, 26, &umr_bitfield_default },
	 { "VBLANK4_INT_TO_UC_EN", 27, 27, &umr_bitfield_default },
	 { "VBLANK5_INT_TO_UC_EN", 28, 28, &umr_bitfield_default },
	 { "VBLANK6_INT_TO_UC_EN", 29, 29, &umr_bitfield_default },
	 { "STATIC_SCREEN6_INT_TO_UC_EN", 30, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmDMCU_INTERRUPT_TO_UC_EN_MASK_1[] = {
	 { "OTG0_RANGE_TIMING_UPDATE_INT_TO_UC_EN", 6, 6, &umr_bitfield_default },
	 { "OTG1_RANGE_TIMING_UPDATE_INT_TO_UC_EN", 7, 7, &umr_bitfield_default },
	 { "OTG2_RANGE_TIMING_UPDATE_INT_TO_UC_EN", 8, 8, &umr_bitfield_default },
	 { "OTG3_RANGE_TIMING_UPDATE_INT_TO_UC_EN", 9, 9, &umr_bitfield_default },
	 { "OTG4_RANGE_TIMING_UPDATE_INT_TO_UC_EN", 10, 10, &umr_bitfield_default },
	 { "OTG5_RANGE_TIMING_UPDATE_INT_TO_UC_EN", 11, 11, &umr_bitfield_default },
	 { "DMCU_GENERIC_INT_TO_UC_EN", 13, 13, &umr_bitfield_default },
};
static struct umr_bitfield mmDMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL[] = {
	 { "ABM1_HG_READY_INT_XIRQ_IRQ_SEL", 0, 0, &umr_bitfield_default },
	 { "ABM1_LS_READY_INT_XIRQ_IRQ_SEL", 1, 1, &umr_bitfield_default },
	 { "ABM1_BL_UPDATE_INT_XIRQ_IRQ_SEL", 2, 2, &umr_bitfield_default },
	 { "MCP_INT_XIRQ_IRQ_SEL", 3, 3, &umr_bitfield_default },
	 { "STATIC_SCREEN1_INT_XIRQ_IRQ_SEL", 6, 6, &umr_bitfield_default },
	 { "STATIC_SCREEN2_INT_XIRQ_IRQ_SEL", 7, 7, &umr_bitfield_default },
	 { "EXTERNAL_SW_INT_XIRQ_IRQ_SEL", 8, 8, &umr_bitfield_default },
	 { "STATIC_SCREEN3_INT_XIRQ_IRQ_SEL", 9, 9, &umr_bitfield_default },
	 { "STATIC_SCREEN4_INT_XIRQ_IRQ_SEL", 10, 10, &umr_bitfield_default },
	 { "STATIC_SCREEN5_INT_XIRQ_IRQ_SEL", 11, 11, &umr_bitfield_default },
	 { "DCPG_IHC_DOMAIN0_POWER_UP_INT_XIRQ_IRQ_SEL", 12, 12, &umr_bitfield_default },
	 { "DCPG_IHC_DOMAIN1_POWER_UP_INT_XIRQ_IRQ_SEL", 13, 13, &umr_bitfield_default },
	 { "DCPG_IHC_DOMAIN2_POWER_UP_INT_XIRQ_IRQ_SEL", 14, 14, &umr_bitfield_default },
	 { "DCPG_IHC_DOMAIN3_POWER_UP_INT_XIRQ_IRQ_SEL", 15, 15, &umr_bitfield_default },
	 { "DCPG_IHC_DOMAIN4_POWER_UP_INT_XIRQ_IRQ_SEL", 16, 16, &umr_bitfield_default },
	 { "DCPG_IHC_DOMAIN5_POWER_UP_INT_XIRQ_IRQ_SEL", 17, 17, &umr_bitfield_default },
	 { "DCPG_IHC_DOMAIN0_POWER_DOWN_INT_XIRQ_IRQ_SEL", 18, 18, &umr_bitfield_default },
	 { "DCPG_IHC_DOMAIN1_POWER_DOWN_INT_XIRQ_IRQ_SEL", 19, 19, &umr_bitfield_default },
	 { "DCPG_IHC_DOMAIN2_POWER_DOWN_INT_XIRQ_IRQ_SEL", 20, 20, &umr_bitfield_default },
	 { "DCPG_IHC_DOMAIN3_POWER_DOWN_INT_XIRQ_IRQ_SEL", 21, 21, &umr_bitfield_default },
	 { "DCPG_IHC_DOMAIN4_POWER_DOWN_INT_XIRQ_IRQ_SEL", 22, 22, &umr_bitfield_default },
	 { "DCPG_IHC_DOMAIN5_POWER_DOWN_INT_XIRQ_IRQ_SEL", 23, 23, &umr_bitfield_default },
	 { "VBLANK1_INT_XIRQ_IRQ_SEL", 24, 24, &umr_bitfield_default },
	 { "VBLANK2_INT_XIRQ_IRQ_SEL", 25, 25, &umr_bitfield_default },
	 { "VBLANK3_INT_XIRQ_IRQ_SEL", 26, 26, &umr_bitfield_default },
	 { "VBLANK4_INT_XIRQ_IRQ_SEL", 27, 27, &umr_bitfield_default },
	 { "VBLANK5_INT_XIRQ_IRQ_SEL", 28, 28, &umr_bitfield_default },
	 { "VBLANK6_INT_XIRQ_IRQ_SEL", 29, 29, &umr_bitfield_default },
	 { "STATIC_SCREEN6_INT_XIRQ_IRQ_SEL", 30, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmDMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1[] = {
	 { "OTG0_RANGE_TIMING_UPDATE_INT_XIRQ_IRQ_SEL", 6, 6, &umr_bitfield_default },
	 { "OTG1_RANGE_TIMING_UPDATE_INT_XIRQ_IRQ_SEL", 7, 7, &umr_bitfield_default },
	 { "OTG2_RANGE_TIMING_UPDATE_INT_XIRQ_IRQ_SEL", 8, 8, &umr_bitfield_default },
	 { "OTG3_RANGE_TIMING_UPDATE_INT_XIRQ_IRQ_SEL", 9, 9, &umr_bitfield_default },
	 { "OTG4_RANGE_TIMING_UPDATE_INT_XIRQ_IRQ_SEL", 10, 10, &umr_bitfield_default },
	 { "OTG5_RANGE_TIMING_UPDATE_INT_XIRQ_IRQ_SEL", 11, 11, &umr_bitfield_default },
	 { "DMCU_GENERIC_INT_XIRQ_IRQ_SEL", 13, 13, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_DMCU_SCRATCH[] = {
	 { "DMCU_SCRATCH", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDMCU_INT_CNT[] = {
	 { "DMCU_ABM1_HG_READY_INT_CNT", 0, 7, &umr_bitfield_default },
	 { "DMCU_ABM1_LS_READY_INT_CNT", 8, 15, &umr_bitfield_default },
	 { "DMCU_ABM1_BL_UPDATE_INT_CNT", 16, 23, &umr_bitfield_default },
};
static struct umr_bitfield mmDMCU_FW_CHECKSUM_SMPL_BYTE_POS[] = {
	 { "DMCU_FW_CHECKSUM_LO_SMPL_BYTE_POS", 0, 1, &umr_bitfield_default },
	 { "DMCU_FW_CHECKSUM_HI_SMPL_BYTE_POS", 2, 3, &umr_bitfield_default },
};
static struct umr_bitfield mmDMCU_UC_CLK_GATING_CNTL[] = {
	 { "UC_IRAM_RD_DELAY", 0, 2, &umr_bitfield_default },
	 { "UC_ERAM_RD_DELAY", 8, 10, &umr_bitfield_default },
	 { "UC_RBBM_RD_CLK_GATING_EN", 16, 16, &umr_bitfield_default },
};
static struct umr_bitfield mmMASTER_COMM_DATA_REG1[] = {
	 { "MASTER_COMM_DATA_REG1_BYTE0", 0, 7, &umr_bitfield_default },
	 { "MASTER_COMM_DATA_REG1_BYTE1", 8, 15, &umr_bitfield_default },
	 { "MASTER_COMM_DATA_REG1_BYTE2", 16, 23, &umr_bitfield_default },
	 { "MASTER_COMM_DATA_REG1_BYTE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMASTER_COMM_DATA_REG2[] = {
	 { "MASTER_COMM_DATA_REG2_BYTE0", 0, 7, &umr_bitfield_default },
	 { "MASTER_COMM_DATA_REG2_BYTE1", 8, 15, &umr_bitfield_default },
	 { "MASTER_COMM_DATA_REG2_BYTE2", 16, 23, &umr_bitfield_default },
	 { "MASTER_COMM_DATA_REG2_BYTE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMASTER_COMM_DATA_REG3[] = {
	 { "MASTER_COMM_DATA_REG3_BYTE0", 0, 7, &umr_bitfield_default },
	 { "MASTER_COMM_DATA_REG3_BYTE1", 8, 15, &umr_bitfield_default },
	 { "MASTER_COMM_DATA_REG3_BYTE2", 16, 23, &umr_bitfield_default },
	 { "MASTER_COMM_DATA_REG3_BYTE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMASTER_COMM_CMD_REG[] = {
	 { "MASTER_COMM_CMD_REG_BYTE0", 0, 7, &umr_bitfield_default },
	 { "MASTER_COMM_CMD_REG_BYTE1", 8, 15, &umr_bitfield_default },
	 { "MASTER_COMM_CMD_REG_BYTE2", 16, 23, &umr_bitfield_default },
	 { "MASTER_COMM_CMD_REG_BYTE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMASTER_COMM_CNTL_REG[] = {
	 { "MASTER_COMM_INTERRUPT", 0, 0, &umr_bitfield_default },
};
static struct umr_bitfield mmSLAVE_COMM_DATA_REG1[] = {
	 { "SLAVE_COMM_DATA_REG1_BYTE0", 0, 7, &umr_bitfield_default },
	 { "SLAVE_COMM_DATA_REG1_BYTE1", 8, 15, &umr_bitfield_default },
	 { "SLAVE_COMM_DATA_REG1_BYTE2", 16, 23, &umr_bitfield_default },
	 { "SLAVE_COMM_DATA_REG1_BYTE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSLAVE_COMM_DATA_REG2[] = {
	 { "SLAVE_COMM_DATA_REG2_BYTE0", 0, 7, &umr_bitfield_default },
	 { "SLAVE_COMM_DATA_REG2_BYTE1", 8, 15, &umr_bitfield_default },
	 { "SLAVE_COMM_DATA_REG2_BYTE2", 16, 23, &umr_bitfield_default },
	 { "SLAVE_COMM_DATA_REG2_BYTE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSLAVE_COMM_DATA_REG3[] = {
	 { "SLAVE_COMM_DATA_REG3_BYTE0", 0, 7, &umr_bitfield_default },
	 { "SLAVE_COMM_DATA_REG3_BYTE1", 8, 15, &umr_bitfield_default },
	 { "SLAVE_COMM_DATA_REG3_BYTE2", 16, 23, &umr_bitfield_default },
	 { "SLAVE_COMM_DATA_REG3_BYTE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSLAVE_COMM_CMD_REG[] = {
	 { "SLAVE_COMM_CMD_REG_BYTE0", 0, 7, &umr_bitfield_default },
	 { "SLAVE_COMM_CMD_REG_BYTE1", 8, 15, &umr_bitfield_default },
	 { "SLAVE_COMM_CMD_REG_BYTE2", 16, 23, &umr_bitfield_default },
	 { "SLAVE_COMM_CMD_REG_BYTE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSLAVE_COMM_CNTL_REG[] = {
	 { "SLAVE_COMM_INTERRUPT", 0, 0, &umr_bitfield_default },
	 { "COMM_PORT_MSG_TO_HOST_IN_PROGRESS", 8, 8, &umr_bitfield_default },
};
static struct umr_bitfield mmDMCU_PERFMON_INTERRUPT_STATUS1[] = {
	 { "DMU_PERFMON_COUNTER_INT_OCCURRED", 0, 0, &umr_bitfield_default },
	 { "DMU_PERFMON_COUNTER_INT_CLEAR", 0, 0, &umr_bitfield_default },
	 { "DIO_PERFMON_COUNTER_INT_OCCURRED", 1, 1, &umr_bitfield_default },
	 { "DIO_PERFMON_COUNTER_INT_CLEAR", 1, 1, &umr_bitfield_default },
	 { "DCCG_PERFMON_COUNTER_INT_OCCURRED", 2, 2, &umr_bitfield_default },
	 { "DCCG_PERFMON_COUNTER_INT_CLEAR", 2, 2, &umr_bitfield_default },
};
static struct umr_bitfield mmDMCU_PERFMON_INTERRUPT_STATUS2[] = {
	 { "HUBP0_PERFMON_COUNTER_INT_OCCURRED", 0, 0, &umr_bitfield_default },
	 { "HUBP0_PERFMON_COUNTER_INT_CLEAR", 0, 0, &umr_bitfield_default },
	 { "HUBP1_PERFMON_COUNTER_INT_OCCURRED", 1, 1, &umr_bitfield_default },
	 { "HUBP1_PERFMON_COUNTER_INT_CLEAR", 1, 1, &umr_bitfield_default },
	 { "HUBP2_PERFMON_COUNTER_INT_OCCURRED", 2, 2, &umr_bitfield_default },
	 { "HUBP2_PERFMON_COUNTER_INT_CLEAR", 2, 2, &umr_bitfield_default },
	 { "HUBP3_PERFMON_COUNTER_INT_OCCURRED", 3, 3, &umr_bitfield_default },
	 { "HUBP3_PERFMON_COUNTER_INT_CLEAR", 3, 3, &umr_bitfield_default },
	 { "HUBP4_PERFMON_COUNTER_INT_OCCURRED", 4, 4, &umr_bitfield_default },
	 { "HUBP4_PERFMON_COUNTER_INT_CLEAR", 4, 4, &umr_bitfield_default },
	 { "HUBP5_PERFMON_COUNTER_INT_OCCURRED", 5, 5, &umr_bitfield_default },
	 { "HUBP5_PERFMON_COUNTER_INT_CLEAR", 5, 5, &umr_bitfield_default },
	 { "HUBP6_PERFMON_COUNTER_INT_OCCURRED", 6, 6, &umr_bitfield_default },
	 { "HUBP6_PERFMON_COUNTER_INT_CLEAR", 6, 6, &umr_bitfield_default },
	 { "HUBP7_PERFMON_COUNTER_INT_OCCURRED", 7, 7, &umr_bitfield_default },
	 { "HUBP7_PERFMON_COUNTER_INT_CLEAR", 7, 7, &umr_bitfield_default },
	 { "HUBBUB_PERFMON_COUNTER_INT_OCCURRED", 8, 8, &umr_bitfield_default },
	 { "HUBBUB_PERFMON_COUNTER_INT_CLEAR", 8, 8, &umr_bitfield_default },
};
static struct umr_bitfield mmDMCU_PERFMON_INTERRUPT_STATUS3[] = {
	 { "DPP0_PERFMON_COUNTER_INT_OCCURRED", 0, 0, &umr_bitfield_default },
	 { "DPP0_PERFMON_COUNTER_INT_CLEAR", 0, 0, &umr_bitfield_default },
	 { "DPP1_PERFMON_COUNTER_INT_OCCURRED", 1, 1, &umr_bitfield_default },
	 { "DPP1_PERFMON_COUNTER_INT_CLEAR", 1, 1, &umr_bitfield_default },
	 { "DPP2_PERFMON_COUNTER_INT_OCCURRED", 2, 2, &umr_bitfield_default },
	 { "DPP2_PERFMON_COUNTER_INT_CLEAR", 2, 2, &umr_bitfield_default },
	 { "DPP3_PERFMON_COUNTER_INT_OCCURRED", 3, 3, &umr_bitfield_default },
	 { "DPP3_PERFMON_COUNTER_INT_CLEAR", 3, 3, &umr_bitfield_default },
	 { "DPP4_PERFMON_COUNTER_INT_OCCURRED", 4, 4, &umr_bitfield_default },
	 { "DPP4_PERFMON_COUNTER_INT_CLEAR", 4, 4, &umr_bitfield_default },
	 { "DPP5_PERFMON_COUNTER_INT_OCCURRED", 5, 5, &umr_bitfield_default },
	 { "DPP5_PERFMON_COUNTER_INT_CLEAR", 5, 5, &umr_bitfield_default },
	 { "DPP6_PERFMON_COUNTER_INT_OCCURRED", 6, 6, &umr_bitfield_default },
	 { "DPP6_PERFMON_COUNTER_INT_CLEAR", 6, 6, &umr_bitfield_default },
	 { "DPP7_PERFMON_COUNTER_INT_OCCURRED", 7, 7, &umr_bitfield_default },
	 { "DPP7_PERFMON_COUNTER_INT_CLEAR", 7, 7, &umr_bitfield_default },
};
static struct umr_bitfield mmDMCU_PERFMON_INTERRUPT_STATUS4[] = {
	 { "WB0_PERFMON_COUNTER_INT_OCCURRED", 0, 0, &umr_bitfield_default },
	 { "WB0_PERFMON_COUNTER_INT_CLEAR", 0, 0, &umr_bitfield_default },
	 { "WB1_PERFMON_COUNTER_INT_OCCURRED", 1, 1, &umr_bitfield_default },
	 { "WB1_PERFMON_COUNTER_INT_CLEAR", 1, 1, &umr_bitfield_default },
	 { "DCCG_PERFMON2_COUNTER_INT_OCCURRED", 2, 2, &umr_bitfield_default },
	 { "DCCG_PERFMON2_COUNTER_INT_CLEAR", 2, 2, &umr_bitfield_default },
	 { "MMHUBBUB_PERFMON_COUNTER_INT_OCCURRED", 3, 3, &umr_bitfield_default },
	 { "MMHUBBUB_PERFMON_COUNTER_INT_CLEAR", 3, 3, &umr_bitfield_default },
};
static struct umr_bitfield mmDMCU_PERFMON_INTERRUPT_STATUS5[] = {
	 { "MPC_PERFMON_COUNTER_INT_OCCURRED", 0, 0, &umr_bitfield_default },
	 { "MPC_PERFMON_COUNTER_INT_CLEAR", 0, 0, &umr_bitfield_default },
	 { "OPP_PERFMON_COUNTER_INT_OCCURRED", 1, 1, &umr_bitfield_default },
	 { "OPP_PERFMON_COUNTER_INT_CLEAR", 1, 1, &umr_bitfield_default },
	 { "OPTC_PERFMON_COUNTER_INT_OCCURRED", 2, 2, &umr_bitfield_default },
	 { "OPTC_PERFMON_COUNTER_INT_CLEAR", 2, 2, &umr_bitfield_default },
	 { "HDA_PERFMON_COUNTER_INT_OCCURRED", 3, 3, &umr_bitfield_default },
	 { "HDA_PERFMON_COUNTER_INT_CLEAR", 3, 3, &umr_bitfield_default },
};
static struct umr_bitfield mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1[] = {
	 { "DMU_PERFMON_COUNTER_INT_TO_UC_EN", 0, 0, &umr_bitfield_default },
	 { "DIO_PERFMON_COUNTER_INT_TO_UC_EN", 1, 1, &umr_bitfield_default },
	 { "DCCG_PERFMON_COUNTER_INT_TO_UC_EN", 2, 2, &umr_bitfield_default },
};
static struct umr_bitfield mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2[] = {
	 { "HUBP0_PERFMON_COUNTER_INT_TO_UC_EN", 0, 0, &umr_bitfield_default },
	 { "HUBP1_PERFMON_COUNTER_INT_TO_UC_EN", 1, 1, &umr_bitfield_default },
	 { "HUBP2_PERFMON_COUNTER_INT_TO_UC_EN", 2, 2, &umr_bitfield_default },
	 { "HUBP3_PERFMON_COUNTER_INT_TO_UC_EN", 3, 3, &umr_bitfield_default },
	 { "HUBP4_PERFMON_COUNTER_INT_TO_UC_EN", 4, 4, &umr_bitfield_default },
	 { "HUBP5_PERFMON_COUNTER_INT_TO_UC_EN", 5, 5, &umr_bitfield_default },
	 { "HUBP6_PERFMON_COUNTER_INT_TO_UC_EN", 6, 6, &umr_bitfield_default },
	 { "HUBP7_PERFMON_COUNTER_INT_TO_UC_EN", 7, 7, &umr_bitfield_default },
	 { "HUBBUB_PERFMON_COUNTER_INT_TO_UC_EN", 8, 8, &umr_bitfield_default },
};
static struct umr_bitfield mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3[] = {
	 { "DPP0_PERFMON_COUNTER_INT_TO_UC_EN", 0, 0, &umr_bitfield_default },
	 { "DPP1_PERFMON_COUNTER_INT_TO_UC_EN", 1, 1, &umr_bitfield_default },
	 { "DPP2_PERFMON_COUNTER_INT_TO_UC_EN", 2, 2, &umr_bitfield_default },
	 { "DPP3_PERFMON_COUNTER_INT_TO_UC_EN", 3, 3, &umr_bitfield_default },
	 { "DPP4_PERFMON_COUNTER_INT_TO_UC_EN", 4, 4, &umr_bitfield_default },
	 { "DPP5_PERFMON_COUNTER_INT_TO_UC_EN", 5, 5, &umr_bitfield_default },
	 { "DPP6_PERFMON_COUNTER_INT_TO_UC_EN", 6, 6, &umr_bitfield_default },
	 { "DPP7_PERFMON_COUNTER_INT_TO_UC_EN", 7, 7, &umr_bitfield_default },
};
static struct umr_bitfield mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4[] = {
	 { "WB0_PERFMON_COUNTER_INT_TO_UC_EN", 0, 0, &umr_bitfield_default },
	 { "WB1_PERFMON_COUNTER_INT_TO_UC_EN", 1, 1, &umr_bitfield_default },
	 { "DCCG_PERFMON2_COUNTER_INT_TO_UC_EN", 2, 2, &umr_bitfield_default },
	 { "MMHUBBUB_PERFMON_COUNTER_INT_TO_UC_EN", 3, 3, &umr_bitfield_default },
};
static struct umr_bitfield mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5[] = {
	 { "MPC_PERFMON_COUNTER_INT_TO_UC_EN", 0, 0, &umr_bitfield_default },
	 { "OPP_PERFMON_COUNTER_INT_TO_UC_EN", 1, 1, &umr_bitfield_default },
	 { "OPTC_PERFMON_COUNTER_INT_TO_UC_EN", 2, 2, &umr_bitfield_default },
	 { "HDA_PERFMON_COUNTER_INT_TO_UC_EN", 3, 3, &umr_bitfield_default },
};
static struct umr_bitfield mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1[] = {
	 { "DMU_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL", 0, 0, &umr_bitfield_default },
	 { "DIO_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL", 1, 1, &umr_bitfield_default },
	 { "DCCG_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL", 2, 2, &umr_bitfield_default },
};
static struct umr_bitfield mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2[] = {
	 { "HUBP0_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL", 0, 0, &umr_bitfield_default },
	 { "HUBP1_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL", 1, 1, &umr_bitfield_default },
	 { "HUBP2_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL", 2, 2, &umr_bitfield_default },
	 { "HUBP3_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL", 3, 3, &umr_bitfield_default },
	 { "HUBP4_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL", 4, 4, &umr_bitfield_default },
	 { "HUBP5_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL", 5, 5, &umr_bitfield_default },
	 { "HUBP6_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL", 6, 6, &umr_bitfield_default },
	 { "HUBP7_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL", 7, 7, &umr_bitfield_default },
	 { "HUBBUB_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL", 8, 8, &umr_bitfield_default },
};
static struct umr_bitfield mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3[] = {
	 { "DPP0_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL", 0, 0, &umr_bitfield_default },
	 { "DPP1_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL", 1, 1, &umr_bitfield_default },
	 { "DPP2_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL", 2, 2, &umr_bitfield_default },
	 { "DPP3_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL", 3, 3, &umr_bitfield_default },
	 { "DPP4_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL", 4, 4, &umr_bitfield_default },
	 { "DPP5_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL", 5, 5, &umr_bitfield_default },
	 { "DPP6_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL", 6, 6, &umr_bitfield_default },
	 { "DPP7_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL", 7, 7, &umr_bitfield_default },
};
static struct umr_bitfield mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4[] = {
	 { "WB0_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL", 0, 0, &umr_bitfield_default },
	 { "WB1_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL", 1, 1, &umr_bitfield_default },
	 { "DCCG_PERFMON2_COUNTER_INT_XIRQ_IRQ_SEL", 2, 2, &umr_bitfield_default },
	 { "MMHUBBUB_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL", 3, 3, &umr_bitfield_default },
};
static struct umr_bitfield mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5[] = {
	 { "MPC_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL", 0, 0, &umr_bitfield_default },
	 { "OPTC_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL", 1, 1, &umr_bitfield_default },
	 { "OPP_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL", 2, 2, &umr_bitfield_default },
	 { "HDA_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL", 3, 3, &umr_bitfield_default },
};
static struct umr_bitfield mmDMCU_DPRX_INTERRUPT_STATUS1[] = {
	 { "DPRX_SD0P0_MSA_RECEIVED_INT_OCCURRED", 0, 0, &umr_bitfield_default },
	 { "DPRX_SD0P0_MSA_RECEIVED_INT_CLEAR", 0, 0, &umr_bitfield_default },
	 { "DPRX_SD0P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_OCCURRED", 1, 1, &umr_bitfield_default },
	 { "DPRX_SD0P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_CLEAR", 1, 1, &umr_bitfield_default },
	 { "DPRX_SD0P0_VERTICAL_INT0_OCCURRED", 2, 2, &umr_bitfield_default },
	 { "DPRX_SD0P0_VERTICAL_INT0_CLEAR", 2, 2, &umr_bitfield_default },
	 { "DPRX_SD0P0_VERTICAL_INT1_OCCURRED", 3, 3, &umr_bitfield_default },
	 { "DPRX_SD0P0_VERTICAL_INT1_CLEAR", 3, 3, &umr_bitfield_default },
	 { "DPRX_SD0P0_SDP_RECEIVED_INT_OCCURRED", 4, 4, &umr_bitfield_default },
	 { "DPRX_SD0P0_SDP_RECEIVED_INT_CLEAR", 4, 4, &umr_bitfield_default },
	 { "DPRX_SD1P0_MSA_RECEIVED_INT_OCCURRED", 5, 5, &umr_bitfield_default },
	 { "DPRX_SD1P0_MSA_RECEIVED_INT_CLEAR", 5, 5, &umr_bitfield_default },
	 { "DPRX_SD1P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_OCCURRED", 6, 6, &umr_bitfield_default },
	 { "DPRX_SD1P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_CLEAR", 6, 6, &umr_bitfield_default },
	 { "DPRX_SD1P0_VERTICAL_INT0_OCCURRED", 7, 7, &umr_bitfield_default },
	 { "DPRX_SD1P0_VERTICAL_INT0_CLEAR", 7, 7, &umr_bitfield_default },
	 { "DPRX_SD1P0_VERTICAL_INT1_OCCURRED", 8, 8, &umr_bitfield_default },
	 { "DPRX_SD1P0_VERTICAL_INT1_CLEAR", 8, 8, &umr_bitfield_default },
	 { "DPRX_SD1P0_SDP_RECEIVED_INT_OCCURRED", 9, 9, &umr_bitfield_default },
	 { "DPRX_SD1P0_SDP_RECEIVED_INT_CLEAR", 9, 9, &umr_bitfield_default },
	 { "DPRX_DPHY_P0_BS_INTERVAL_ERROR_THRESH_EXCEEDED_INT_OCCURRED", 10, 10, &umr_bitfield_default },
	 { "DPRX_DPHY_P0_BS_INTERVAL_ERROR_THRESH_EXCEEDED_INT_CLEAR", 10, 10, &umr_bitfield_default },
	 { "DPRX_DPHY_P0_SR_INTERVAL_ERROR_THRESH_EXCEEDED_INT_OCCURRED", 11, 11, &umr_bitfield_default },
	 { "DPRX_DPHY_P0_SR_INTERVAL_ERROR_THRESH_EXCEEDED_INT_CLEAR", 11, 11, &umr_bitfield_default },
	 { "DPRX_DPHY_P0_SYMBOL_ERROR_THRESH_EXCEEDED_INT_OCCURRED", 12, 12, &umr_bitfield_default },
	 { "DPRX_DPHY_P0_SYMBOL_ERROR_THRESH_EXCEEDED_INT_CLEAR", 12, 12, &umr_bitfield_default },
	 { "DPRX_DPHY_P0_DISPARITY_ERROR_THRESH_EXCEEDED_INT_OCCURRED", 13, 13, &umr_bitfield_default },
	 { "DPRX_DPHY_P0_DISPARITY_ERROR_THRESH_EXCEEDED_INT_CLEAR", 13, 13, &umr_bitfield_default },
	 { "DPRX_DPHY_P0_TRAINING_ERROR_THRESH_EXCEEDED_INT_OCCURRED", 14, 14, &umr_bitfield_default },
	 { "DPRX_DPHY_P0_TRAINING_ERROR_THRESH_EXCEEDED_INT_CLEAR", 14, 14, &umr_bitfield_default },
	 { "DPRX_DPHY_P0_TEST_PATTERN_ERROR_THRESH_EXCEEDED_INT_OCCURRED", 15, 15, &umr_bitfield_default },
	 { "DPRX_DPHY_P0_TEST_PATTERN_ERROR_THRESH_EXCEEDED_INT_CLEAR", 15, 15, &umr_bitfield_default },
	 { "DPRX_DPHY_P0_ECF_ERROR_THRESH_EXCEEDED_INT_OCCURRED", 16, 16, &umr_bitfield_default },
	 { "DPRX_DPHY_P0_ECF_ERROR_THRESH_EXCEEDED_INT_CLEAR", 16, 16, &umr_bitfield_default },
	 { "DPRX_DPHY_P0_DETECT_SR_LOCK_INT_OCCURRED", 17, 17, &umr_bitfield_default },
	 { "DPRX_DPHY_P0_DETECT_SR_LOCK_INT_CLEAR", 17, 17, &umr_bitfield_default },
	 { "DPRX_DPHY_P0_LOSS_OF_ALIGN_INT_OCCURRED", 18, 18, &umr_bitfield_default },
	 { "DPRX_DPHY_P0_LOSS_OF_ALIGN_INT_CLEAR", 18, 18, &umr_bitfield_default },
	 { "DPRX_DPHY_P0_LOSS_OF_DESKEW_INT_OCCURRED", 19, 19, &umr_bitfield_default },
	 { "DPRX_DPHY_P0_LOSS_OF_DESKEW_INT_CLEAR", 19, 19, &umr_bitfield_default },
	 { "DPRX_DPHY_P0_EXCESSIVE_ERROR_INT_OCCURRED", 20, 20, &umr_bitfield_default },
	 { "DPRX_DPHY_P0_EXCESSIVE_ERROR_INT_CLEAR", 20, 20, &umr_bitfield_default },
	 { "DPRX_DPHY_P0_DESKEW_FIFO_OVERFLOW_INT_OCCURRED", 21, 21, &umr_bitfield_default },
	 { "DPRX_DPHY_P0_DESKEW_FIFO_OVERFLOW_INT_CLEAR", 21, 21, &umr_bitfield_default },
	 { "DPRX_AUX_P0_AUX_INT_OCCURRED", 22, 22, &umr_bitfield_default },
	 { "DPRX_AUX_P0_AUX_INT_CLEAR", 22, 22, &umr_bitfield_default },
	 { "DPRX_AUX_P0_I2C_INT_OCCURRED", 23, 23, &umr_bitfield_default },
	 { "DPRX_AUX_P0_I2C_INT_CLEAR", 23, 23, &umr_bitfield_default },
	 { "DPRX_AUX_P0_CPU_INT_OCCURRED", 24, 24, &umr_bitfield_default },
	 { "DPRX_AUX_P0_CPU_INT_CLEAR", 24, 24, &umr_bitfield_default },
	 { "DPRX_AUX_P0_MSG1_TIMEOUT_INT_OCCURRED", 25, 25, &umr_bitfield_default },
	 { "DPRX_AUX_P0_MSG1_TIMEOUT_INT_CLEAR", 25, 25, &umr_bitfield_default },
	 { "DPRX_AUX_P0_MSG2_TIMEOUT_INT_OCCURRED", 26, 26, &umr_bitfield_default },
	 { "DPRX_AUX_P0_MSG2_TIMEOUT_INT_CLEAR", 26, 26, &umr_bitfield_default },
	 { "DPRX_AUX_P0_MSG3_TIMEOUT_INT_OCCURRED", 27, 27, &umr_bitfield_default },
	 { "DPRX_AUX_P0_MSG3_TIMEOUT_INT_CLEAR", 27, 27, &umr_bitfield_default },
	 { "DPRX_AUX_P0_MSG4_TIMEOUT_INT_OCCURRED", 28, 28, &umr_bitfield_default },
	 { "DPRX_AUX_P0_MSG4_TIMEOUT_INT_CLEAR", 28, 28, &umr_bitfield_default },
};
static struct umr_bitfield mmDMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1[] = {
	 { "DPRX_SD0P0_MSA_RECEIVED_INT_TO_UC_EN", 0, 0, &umr_bitfield_default },
	 { "DPRX_SD0P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_TO_UC_EN", 1, 1, &umr_bitfield_default },
	 { "DPRX_SD0P0_VERTICAL_INT0_TO_UC_EN", 2, 2, &umr_bitfield_default },
	 { "DPRX_SD0P0_VERTICAL_INT1_TO_UC_EN", 3, 3, &umr_bitfield_default },
	 { "DPRX_SD0P0_SDP_RECEIVED_INT_TO_UC_EN", 4, 4, &umr_bitfield_default },
	 { "DPRX_SD1P0_MSA_RECEIVED_INT_TO_UC_EN", 5, 5, &umr_bitfield_default },
	 { "DPRX_SD1P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_TO_UC_EN", 6, 6, &umr_bitfield_default },
	 { "DPRX_SD1P0_VERTICAL_INT0_TO_UC_EN", 7, 7, &umr_bitfield_default },
	 { "DPRX_SD1P0_VERTICAL_INT1_TO_UC_EN", 8, 8, &umr_bitfield_default },
	 { "DPRX_SD1P0_SDP_RECEIVED_INT_TO_UC_EN", 9, 9, &umr_bitfield_default },
	 { "DPRX_DPHY_P0_BS_INTERVAL_ERROR_THRESH_EXCEEDED_INT_TO_UC_EN", 10, 10, &umr_bitfield_default },
	 { "DPRX_DPHY_P0_SR_INTERVAL_ERROR_THRESH_EXCEEDED_INT_TO_UC_EN", 11, 11, &umr_bitfield_default },
	 { "DPRX_DPHY_P0_SYMBOL_ERROR_THRESH_EXCEEDED_INT_TO_UC_EN", 12, 12, &umr_bitfield_default },
	 { "DPRX_DPHY_P0_DISPARITY_ERROR_THRESH_EXCEEDED_INT_TO_UC_EN", 13, 13, &umr_bitfield_default },
	 { "DPRX_DPHY_P0_TRAINING_ERROR_THRESH_EXCEEDED_INT_TO_UC_EN", 14, 14, &umr_bitfield_default },
	 { "DPRX_DPHY_P0_TEST_PATTERN_ERROR_THRESH_EXCEEDED_INT_TO_UC_EN", 15, 15, &umr_bitfield_default },
	 { "DPRX_DPHY_P0_ECF_ERROR_THRESH_EXCEEDED_INT_TO_UC_EN", 16, 16, &umr_bitfield_default },
	 { "DPRX_DPHY_P0_DETECT_SR_LOCK_INT_TO_UC_EN", 17, 17, &umr_bitfield_default },
	 { "DPRX_DPHY_P0_LOSS_OF_ALIGN_INT_TO_UC_EN", 18, 18, &umr_bitfield_default },
	 { "DPRX_DPHY_P0_LOSS_OF_DESKEW_INT_TO_UC_EN", 19, 19, &umr_bitfield_default },
	 { "DPRX_DPHY_P0_EXCESSIVE_ERROR_INT_TO_UC_EN", 20, 20, &umr_bitfield_default },
	 { "DPRX_DPHY_P0_DESKEW_FIFO_OVERFLOW_INT_TO_UC_EN", 21, 21, &umr_bitfield_default },
	 { "DPRX_AUX_P0_AUX_INT_TO_UC_EN", 22, 22, &umr_bitfield_default },
	 { "DPRX_AUX_P0_I2C_INT_TO_UC_EN", 23, 23, &umr_bitfield_default },
	 { "DPRX_AUX_P0_CPU_INT_TO_UC_EN", 24, 24, &umr_bitfield_default },
	 { "DPRX_AUX_P0_MSG1_TIMEOUT_INT_TO_UC_EN", 25, 25, &umr_bitfield_default },
	 { "DPRX_AUX_P0_MSG2_TIMEOUT_INT_TO_UC_EN", 26, 26, &umr_bitfield_default },
	 { "DPRX_AUX_P0_MSG3_TIMEOUT_INT_TO_UC_EN", 27, 27, &umr_bitfield_default },
	 { "DPRX_AUX_P0_MSG4_TIMEOUT_INT_TO_UC_EN", 28, 28, &umr_bitfield_default },
};
static struct umr_bitfield mmDMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1[] = {
	 { "DPRX_SD0P0_MSA_RECEIVED_INT_XIRQ_IRQ_SEL", 0, 0, &umr_bitfield_default },
	 { "DPRX_SD0P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_XIRQ_IRQ_SEL", 1, 1, &umr_bitfield_default },
	 { "DPRX_SD0P0_VERTICAL_INT0_XIRQ_IRQ_SEL", 2, 2, &umr_bitfield_default },
	 { "DPRX_SD0P0_VERTICAL_INT1_XIRQ_IRQ_SEL", 3, 3, &umr_bitfield_default },
	 { "DPRX_SD0P0_SDP_RECEIVED_INT_XIRQ_IRQ_SEL", 4, 4, &umr_bitfield_default },
	 { "DPRX_SD1P0_MSA_RECEIVED_INT_XIRQ_IRQ_SEL", 5, 5, &umr_bitfield_default },
	 { "DPRX_SD1P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_XIRQ_IRQ_SEL", 6, 6, &umr_bitfield_default },
	 { "DPRX_SD1P0_VERTICAL_INT0_XIRQ_IRQ_SEL", 7, 7, &umr_bitfield_default },
	 { "DPRX_SD1P0_VERTICAL_INT1_XIRQ_IRQ_SEL", 8, 8, &umr_bitfield_default },
	 { "DPRX_SD1P0_SDP_RECEIVED_INT_XIRQ_IRQ_SEL", 9, 9, &umr_bitfield_default },
	 { "DPRX_DPHY_P0_BS_INTERVAL_ERROR_THRESH_EXCEEDED_INT_XIRQ_IRQ_SEL", 10, 10, &umr_bitfield_default },
	 { "DPRX_DPHY_P0_SR_INTERVAL_ERROR_THRESH_EXCEEDED_INT_XIRQ_IRQ_SEL", 11, 11, &umr_bitfield_default },
	 { "DPRX_DPHY_P0_SYMBOL_ERROR_THRESH_EXCEEDED_INT_XIRQ_IRQ_SEL", 12, 12, &umr_bitfield_default },
	 { "DPRX_DPHY_P0_DISPARITY_ERROR_THRESH_EXCEEDED_INT_XIRQ_IRQ_SEL", 13, 13, &umr_bitfield_default },
	 { "DPRX_DPHY_P0_TRAINING_ERROR_THRESH_EXCEEDED_INT_XIRQ_IRQ_SEL", 14, 14, &umr_bitfield_default },
	 { "DPRX_DPHY_P0_TEST_PATTERN_ERROR_THRESH_EXCEEDED_INT_XIRQ_IRQ_SEL", 15, 15, &umr_bitfield_default },
	 { "DPRX_DPHY_P0_ECF_ERROR_THRESH_EXCEEDED_INT_XIRQ_IRQ_SEL", 16, 16, &umr_bitfield_default },
	 { "DPRX_DPHY_P0_DETECT_SR_LOCK_INT_XIRQ_IRQ_SEL", 17, 17, &umr_bitfield_default },
	 { "DPRX_DPHY_P0_LOSS_OF_ALIGN_INT_XIRQ_IRQ_SEL", 18, 18, &umr_bitfield_default },
	 { "DPRX_DPHY_P0_LOSS_OF_DESKEW_INT_XIRQ_IRQ_SEL", 19, 19, &umr_bitfield_default },
	 { "DPRX_DPHY_P0_EXCESSIVE_ERROR_INT_XIRQ_IRQ_SEL", 20, 20, &umr_bitfield_default },
	 { "DPRX_DPHY_P0_DESKEW_FIFO_OVERFLOW_INT_XIRQ_IRQ_SEL", 21, 21, &umr_bitfield_default },
	 { "DPRX_AUX_P0_AUX_INT_XIRQ_IRQ_SEL", 22, 22, &umr_bitfield_default },
	 { "DPRX_AUX_P0_I2C_INT_XIRQ_IRQ_SEL", 23, 23, &umr_bitfield_default },
	 { "DPRX_AUX_P0_CPU_INT_XIRQ_IRQ_SEL", 24, 24, &umr_bitfield_default },
	 { "DPRX_AUX_P0_MSG1_TIMEOUT_INT_XIRQ_IRQ_SEL", 25, 25, &umr_bitfield_default },
	 { "DPRX_AUX_P0_MSG2_TIMEOUT_INT_XIRQ_IRQ_SEL", 26, 26, &umr_bitfield_default },
	 { "DPRX_AUX_P0_MSG3_TIMEOUT_INT_XIRQ_IRQ_SEL", 27, 27, &umr_bitfield_default },
	 { "DPRX_AUX_P0_MSG4_TIMEOUT_INT_XIRQ_IRQ_SEL", 28, 28, &umr_bitfield_default },
};
static struct umr_bitfield mmDMCU_INTERRUPT_STATUS_CONTINUE[] = {
	 { "DCPG_IHC_DOMAIN6_POWER_UP_INT_OCCURRED", 0, 0, &umr_bitfield_default },
	 { "DCPG_IHC_DOMAIN6_POWER_UP_INT_CLEAR", 0, 0, &umr_bitfield_default },
	 { "DCPG_IHC_DOMAIN7_POWER_UP_INT_OCCURRED", 1, 1, &umr_bitfield_default },
	 { "DCPG_IHC_DOMAIN7_POWER_UP_INT_CLEAR", 1, 1, &umr_bitfield_default },
	 { "DCPG_IHC_DOMAIN8_POWER_UP_INT_OCCURRED", 2, 2, &umr_bitfield_default },
	 { "DCPG_IHC_DOMAIN8_POWER_UP_INT_CLEAR", 2, 2, &umr_bitfield_default },
	 { "DCPG_IHC_DOMAIN9_POWER_UP_INT_OCCURRED", 3, 3, &umr_bitfield_default },
	 { "DCPG_IHC_DOMAIN9_POWER_UP_INT_CLEAR", 3, 3, &umr_bitfield_default },
	 { "DCPG_IHC_DOMAIN10_POWER_UP_INT_OCCURRED", 4, 4, &umr_bitfield_default },
	 { "DCPG_IHC_DOMAIN10_POWER_UP_INT_CLEAR", 4, 4, &umr_bitfield_default },
	 { "DCPG_IHC_DOMAIN11_POWER_UP_INT_OCCURRED", 5, 5, &umr_bitfield_default },
	 { "DCPG_IHC_DOMAIN11_POWER_UP_INT_CLEAR", 5, 5, &umr_bitfield_default },
	 { "DCPG_IHC_DOMAIN12_POWER_UP_INT_OCCURRED", 6, 6, &umr_bitfield_default },
	 { "DCPG_IHC_DOMAIN12_POWER_UP_INT_CLEAR", 6, 6, &umr_bitfield_default },
	 { "DCPG_IHC_DOMAIN13_POWER_UP_INT_OCCURRED", 7, 7, &umr_bitfield_default },
	 { "DCPG_IHC_DOMAIN13_POWER_UP_INT_CLEAR", 7, 7, &umr_bitfield_default },
	 { "DCPG_IHC_DOMAIN14_POWER_UP_INT_OCCURRED", 8, 8, &umr_bitfield_default },
	 { "DCPG_IHC_DOMAIN14_POWER_UP_INT_CLEAR", 8, 8, &umr_bitfield_default },
	 { "DCPG_IHC_DOMAIN15_POWER_UP_INT_OCCURRED", 9, 9, &umr_bitfield_default },
	 { "DCPG_IHC_DOMAIN15_POWER_UP_INT_CLEAR", 9, 9, &umr_bitfield_default },
	 { "DCPG_IHC_DOMAIN6_POWER_DOWN_INT_OCCURRED", 10, 10, &umr_bitfield_default },
	 { "DCPG_IHC_DOMAIN6_POWER_DOWN_INT_CLEAR", 10, 10, &umr_bitfield_default },
	 { "DCPG_IHC_DOMAIN7_POWER_DOWN_INT_OCCURRED", 11, 11, &umr_bitfield_default },
	 { "DCPG_IHC_DOMAIN7_POWER_DOWN_INT_CLEAR", 11, 11, &umr_bitfield_default },
	 { "DCPG_IHC_DOMAIN8_POWER_DOWN_INT_OCCURRED", 12, 12, &umr_bitfield_default },
	 { "DCPG_IHC_DOMAIN8_POWER_DOWN_INT_CLEAR", 12, 12, &umr_bitfield_default },
	 { "DCPG_IHC_DOMAIN9_POWER_DOWN_INT_OCCURRED", 13, 13, &umr_bitfield_default },
	 { "DCPG_IHC_DOMAIN9_POWER_DOWN_INT_CLEAR", 13, 13, &umr_bitfield_default },
	 { "DCPG_IHC_DOMAIN10_POWER_DOWN_INT_OCCURRED", 14, 14, &umr_bitfield_default },
	 { "DCPG_IHC_DOMAIN10_POWER_DOWN_INT_CLEAR", 14, 14, &umr_bitfield_default },
	 { "DCPG_IHC_DOMAIN11_POWER_DOWN_INT_OCCURRED", 15, 15, &umr_bitfield_default },
	 { "DCPG_IHC_DOMAIN11_POWER_DOWN_INT_CLEAR", 15, 15, &umr_bitfield_default },
	 { "DCPG_IHC_DOMAIN12_POWER_DOWN_INT_OCCURRED", 16, 16, &umr_bitfield_default },
	 { "DCPG_IHC_DOMAIN12_POWER_DOWN_INT_CLEAR", 16, 16, &umr_bitfield_default },
	 { "DCPG_IHC_DOMAIN13_POWER_DOWN_INT_OCCURRED", 17, 17, &umr_bitfield_default },
	 { "DCPG_IHC_DOMAIN13_POWER_DOWN_INT_CLEAR", 17, 17, &umr_bitfield_default },
	 { "DCPG_IHC_DOMAIN14_POWER_DOWN_INT_OCCURRED", 18, 18, &umr_bitfield_default },
	 { "DCPG_IHC_DOMAIN14_POWER_DOWN_INT_CLEAR", 18, 18, &umr_bitfield_default },
	 { "DCPG_IHC_DOMAIN15_POWER_DOWN_INT_OCCURRED", 19, 19, &umr_bitfield_default },
	 { "DCPG_IHC_DOMAIN15_POWER_DOWN_INT_CLEAR", 19, 19, &umr_bitfield_default },
	 { "DCCG_DMCU_INT_VSYNC_CNT_OTG0_OCCURRED", 20, 20, &umr_bitfield_default },
	 { "DCCG_DMCU_INT_VSYNC_CNT_OTG0_CLEAR", 20, 20, &umr_bitfield_default },
	 { "DCCG_DMCU_INT_VSYNC_CNT_OTG1_OCCURRED", 21, 21, &umr_bitfield_default },
	 { "DCCG_DMCU_INT_VSYNC_CNT_OTG1_CLEAR", 21, 21, &umr_bitfield_default },
	 { "DCCG_DMCU_INT_VSYNC_CNT_OTG2_OCCURRED", 22, 22, &umr_bitfield_default },
	 { "DCCG_DMCU_INT_VSYNC_CNT_OTG2_CLEAR", 22, 22, &umr_bitfield_default },
	 { "DCCG_DMCU_INT_VSYNC_CNT_OTG3_OCCURRED", 23, 23, &umr_bitfield_default },
	 { "DCCG_DMCU_INT_VSYNC_CNT_OTG3_CLEAR", 23, 23, &umr_bitfield_default },
	 { "DCCG_DMCU_INT_VSYNC_CNT_OTG4_OCCURRED", 24, 24, &umr_bitfield_default },
	 { "DCCG_DMCU_INT_VSYNC_CNT_OTG4_CLEAR", 24, 24, &umr_bitfield_default },
	 { "DCCG_DMCU_INT_VSYNC_CNT_OTG5_OCCURRED", 25, 25, &umr_bitfield_default },
	 { "DCCG_DMCU_INT_VSYNC_CNT_OTG5_CLEAR", 25, 25, &umr_bitfield_default },
	 { "ABM0_HG_READY_INT_OCCURRED", 26, 26, &umr_bitfield_default },
	 { "ABM0_HG_READY_INT_CLEAR", 26, 26, &umr_bitfield_default },
	 { "ABM0_LS_READY_INT_OCCURRED", 27, 27, &umr_bitfield_default },
	 { "ABM0_LS_READY_INT_CLEAR", 27, 27, &umr_bitfield_default },
	 { "ABM0_BL_UPDATE_INT_OCCURRED", 28, 28, &umr_bitfield_default },
	 { "ABM0_BL_UPDATE_INT_CLEAR", 28, 28, &umr_bitfield_default },
};
static struct umr_bitfield mmDMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE[] = {
	 { "DCPG_IHC_DOMAIN6_POWER_UP_INT_TO_UC_EN", 0, 0, &umr_bitfield_default },
	 { "DCPG_IHC_DOMAIN7_POWER_UP_INT_TO_UC_EN", 1, 1, &umr_bitfield_default },
	 { "DCPG_IHC_DOMAIN8_POWER_UP_INT_TO_UC_EN", 2, 2, &umr_bitfield_default },
	 { "DCPG_IHC_DOMAIN9_POWER_UP_INT_TO_UC_EN", 3, 3, &umr_bitfield_default },
	 { "DCPG_IHC_DOMAIN10_POWER_UP_INT_TO_UC_EN", 4, 4, &umr_bitfield_default },
	 { "DCPG_IHC_DOMAIN11_POWER_UP_INT_TO_UC_EN", 5, 5, &umr_bitfield_default },
	 { "DCPG_IHC_DOMAIN12_POWER_UP_INT_TO_UC_EN", 6, 6, &umr_bitfield_default },
	 { "DCPG_IHC_DOMAIN13_POWER_UP_INT_TO_UC_EN", 7, 7, &umr_bitfield_default },
	 { "DCPG_IHC_DOMAIN14_POWER_UP_INT_TO_UC_EN", 8, 8, &umr_bitfield_default },
	 { "DCPG_IHC_DOMAIN15_POWER_UP_INT_TO_UC_EN", 9, 9, &umr_bitfield_default },
	 { "DCPG_IHC_DOMAIN6_POWER_DOWN_INT_TO_UC_EN", 10, 10, &umr_bitfield_default },
	 { "DCPG_IHC_DOMAIN7_POWER_DOWN_INT_TO_UC_EN", 11, 11, &umr_bitfield_default },
	 { "DCPG_IHC_DOMAIN8_POWER_DOWN_INT_TO_UC_EN", 12, 12, &umr_bitfield_default },
	 { "DCPG_IHC_DOMAIN9_POWER_DOWN_INT_TO_UC_EN", 13, 13, &umr_bitfield_default },
	 { "DCPG_IHC_DOMAIN10_POWER_DOWN_INT_TO_UC_EN", 14, 14, &umr_bitfield_default },
	 { "DCPG_IHC_DOMAIN11_POWER_DOWN_INT_TO_UC_EN", 15, 15, &umr_bitfield_default },
	 { "DCPG_IHC_DOMAIN12_POWER_DOWN_INT_TO_UC_EN", 16, 16, &umr_bitfield_default },
	 { "DCPG_IHC_DOMAIN13_POWER_DOWN_INT_TO_UC_EN", 17, 17, &umr_bitfield_default },
	 { "DCPG_IHC_DOMAIN14_POWER_DOWN_INT_TO_UC_EN", 18, 18, &umr_bitfield_default },
	 { "DCPG_IHC_DOMAIN15_POWER_DOWN_INT_TO_UC_EN", 19, 19, &umr_bitfield_default },
	 { "DCCG_DMCU_INT_VSYNC_CNT_OTG0_TO_UC_EN", 20, 20, &umr_bitfield_default },
	 { "DCCG_DMCU_INT_VSYNC_CNT_OTG1_TO_UC_EN", 21, 21, &umr_bitfield_default },
	 { "DCCG_DMCU_INT_VSYNC_CNT_OTG2_TO_UC_EN", 22, 22, &umr_bitfield_default },
	 { "DCCG_DMCU_INT_VSYNC_CNT_OTG3_TO_UC_EN", 23, 23, &umr_bitfield_default },
	 { "DCCG_DMCU_INT_VSYNC_CNT_OTG4_TO_UC_EN", 24, 24, &umr_bitfield_default },
	 { "DCCG_DMCU_INT_VSYNC_CNT_OTG5_TO_UC_EN", 25, 25, &umr_bitfield_default },
	 { "ABM0_HG_READY_INT_TO_UC_EN", 26, 26, &umr_bitfield_default },
	 { "ABM0_LS_READY_INT_TO_UC_EN", 27, 27, &umr_bitfield_default },
	 { "ABM0_BL_UPDATE_INT_TO_UC_EN", 28, 28, &umr_bitfield_default },
};
static struct umr_bitfield mmDMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE[] = {
	 { "DCPG_IHC_DOMAIN6_POWER_UP_INT_XIRQ_IRQ_SEL", 0, 0, &umr_bitfield_default },
	 { "DCPG_IHC_DOMAIN7_POWER_UP_INT_XIRQ_IRQ_SEL", 1, 1, &umr_bitfield_default },
	 { "DCPG_IHC_DOMAIN8_POWER_UP_INT_XIRQ_IRQ_SEL", 2, 2, &umr_bitfield_default },
	 { "DCPG_IHC_DOMAIN9_POWER_UP_INT_XIRQ_IRQ_SEL", 3, 3, &umr_bitfield_default },
	 { "DCPG_IHC_DOMAIN10_POWER_UP_INT_XIRQ_IRQ_SEL", 4, 4, &umr_bitfield_default },
	 { "DCPG_IHC_DOMAIN11_POWER_UP_INT_XIRQ_IRQ_SEL", 5, 5, &umr_bitfield_default },
	 { "DCPG_IHC_DOMAIN12_POWER_UP_INT_XIRQ_IRQ_SEL", 6, 6, &umr_bitfield_default },
	 { "DCPG_IHC_DOMAIN13_POWER_UP_INT_XIRQ_IRQ_SEL", 7, 7, &umr_bitfield_default },
	 { "DCPG_IHC_DOMAIN14_POWER_UP_INT_XIRQ_IRQ_SEL", 8, 8, &umr_bitfield_default },
	 { "DCPG_IHC_DOMAIN15_POWER_UP_INT_XIRQ_IRQ_SEL", 9, 9, &umr_bitfield_default },
	 { "DCPG_IHC_DOMAIN6_POWER_DOWN_INT_XIRQ_IRQ_SEL", 10, 10, &umr_bitfield_default },
	 { "DCPG_IHC_DOMAIN7_POWER_DOWN_INT_XIRQ_IRQ_SEL", 11, 11, &umr_bitfield_default },
	 { "DCPG_IHC_DOMAIN8_POWER_DOWN_INT_XIRQ_IRQ_SEL", 12, 12, &umr_bitfield_default },
	 { "DCPG_IHC_DOMAIN9_POWER_DOWN_INT_XIRQ_IRQ_SEL", 13, 13, &umr_bitfield_default },
	 { "DCPG_IHC_DOMAIN10_POWER_DOWN_INT_XIRQ_IRQ_SEL", 14, 14, &umr_bitfield_default },
	 { "DCPG_IHC_DOMAIN11_POWER_DOWN_INT_XIRQ_IRQ_SEL", 15, 15, &umr_bitfield_default },
	 { "DCPG_IHC_DOMAIN12_POWER_DOWN_INT_XIRQ_IRQ_SEL", 16, 16, &umr_bitfield_default },
	 { "DCPG_IHC_DOMAIN13_POWER_DOWN_INT_XIRQ_IRQ_SEL", 17, 17, &umr_bitfield_default },
	 { "DCPG_IHC_DOMAIN14_POWER_DOWN_INT_XIRQ_IRQ_SEL", 18, 18, &umr_bitfield_default },
	 { "DCPG_IHC_DOMAIN15_POWER_DOWN_INT_XIRQ_IRQ_SEL", 19, 19, &umr_bitfield_default },
	 { "DCCG_DMCU_INT_VSYNC_CNT_OTG0_XIRQ_IRQ_SEL", 20, 20, &umr_bitfield_default },
	 { "DCCG_DMCU_INT_VSYNC_CNT_OTG1_XIRQ_IRQ_SEL", 21, 21, &umr_bitfield_default },
	 { "DCCG_DMCU_INT_VSYNC_CNT_OTG2_XIRQ_IRQ_SEL", 22, 22, &umr_bitfield_default },
	 { "DCCG_DMCU_INT_VSYNC_CNT_OTG3_XIRQ_IRQ_SEL", 23, 23, &umr_bitfield_default },
	 { "DCCG_DMCU_INT_VSYNC_CNT_OTG4_XIRQ_IRQ_SEL", 24, 24, &umr_bitfield_default },
	 { "DCCG_DMCU_INT_VSYNC_CNT_OTG5_XIRQ_IRQ_SEL", 25, 25, &umr_bitfield_default },
	 { "ABM0_HG_READY_INT_XIRQ_IRQ_SEL", 26, 26, &umr_bitfield_default },
	 { "ABM0_LS_READY_INT_XIRQ_IRQ_SEL", 27, 27, &umr_bitfield_default },
	 { "ABM0_BL_UPDATE_INT_XIRQ_IRQ_SEL", 28, 28, &umr_bitfield_default },
};
static struct umr_bitfield mmDMCU_INT_CNT_CONTINUE[] = {
	 { "DMCU_ABM0_HG_READY_INT_CNT", 0, 7, &umr_bitfield_default },
	 { "DMCU_ABM0_LS_READY_INT_CNT", 8, 15, &umr_bitfield_default },
	 { "DMCU_ABM0_BL_UPDATE_INT_CNT", 16, 23, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_GPU_TIMER_START_POSITION_V_UPDATE[] = {
	 { "DC_GPU_TIMER_START_POSITION_D1_V_UPDATE", 0, 2, &umr_bitfield_default },
	 { "DC_GPU_TIMER_START_POSITION_D2_V_UPDATE", 4, 6, &umr_bitfield_default },
	 { "DC_GPU_TIMER_START_POSITION_D3_V_UPDATE", 8, 10, &umr_bitfield_default },
	 { "DC_GPU_TIMER_START_POSITION_D4_V_UPDATE", 12, 14, &umr_bitfield_default },
	 { "DC_GPU_TIMER_START_POSITION_D5_V_UPDATE", 16, 18, &umr_bitfield_default },
	 { "DC_GPU_TIMER_START_POSITION_D6_V_UPDATE", 20, 22, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_GPU_TIMER_START_POSITION_VSTARTUP[] = {
	 { "DC_GPU_TIMER_START_POSITION_D1_VSTARTUP", 0, 2, &umr_bitfield_default },
	 { "DC_GPU_TIMER_START_POSITION_D2_VSTARTUP", 4, 6, &umr_bitfield_default },
	 { "DC_GPU_TIMER_START_POSITION_D3_VSTARTUP", 8, 10, &umr_bitfield_default },
	 { "DC_GPU_TIMER_START_POSITION_D4_VSTARTUP", 12, 14, &umr_bitfield_default },
	 { "DC_GPU_TIMER_START_POSITION_D5_VSTARTUP", 16, 18, &umr_bitfield_default },
	 { "DC_GPU_TIMER_START_POSITION_D6_VSTARTUP", 20, 22, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_GPU_TIMER_READ[] = {
	 { "DC_GPU_TIMER_READ", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_GPU_TIMER_READ_CNTL[] = {
	 { "DC_GPU_TIMER_READ_SELECT", 0, 6, &umr_bitfield_default },
	 { "DC_GPU_TIMER_START_POSITION_D1_VSYNC_NOM", 8, 10, &umr_bitfield_default },
	 { "DC_GPU_TIMER_START_POSITION_D2_VSYNC_NOM", 11, 13, &umr_bitfield_default },
	 { "DC_GPU_TIMER_START_POSITION_D3_VSYNC_NOM", 14, 16, &umr_bitfield_default },
	 { "DC_GPU_TIMER_START_POSITION_D4_VSYNC_NOM", 17, 19, &umr_bitfield_default },
	 { "DC_GPU_TIMER_START_POSITION_D5_VSYNC_NOM", 20, 22, &umr_bitfield_default },
	 { "DC_GPU_TIMER_START_POSITION_D6_VSYNC_NOM", 23, 25, &umr_bitfield_default },
};
static struct umr_bitfield mmDISP_INTERRUPT_STATUS[] = {
	 { "OPTC1_DATA_UNDERFLOW_INTERRUPT", 1, 1, &umr_bitfield_default },
	 { "OTG1_IHC_SNAPSHOT_INTERRUPT", 4, 4, &umr_bitfield_default },
	 { "OTG1_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT", 5, 5, &umr_bitfield_default },
	 { "OTG1_IHC_FORCE_COUNT_NOW_INTERRUPT", 6, 6, &umr_bitfield_default },
	 { "OTG1_IHC_TRIGA_INTERRUPT", 7, 7, &umr_bitfield_default },
	 { "OTG1_IHC_TRIGB_INTERRUPT", 8, 8, &umr_bitfield_default },
	 { "OTG1_IHC_VSYNC_NOM_INTERRUPT", 9, 9, &umr_bitfield_default },
	 { "OTG1_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT", 10, 10, &umr_bitfield_default },
	 { "DIGA_DP_FAST_TRAINING_COMPLETE_INTERRUPT", 15, 15, &umr_bitfield_default },
	 { "DIGA_DP_VID_STREAM_DISABLE_INTERRUPT", 16, 16, &umr_bitfield_default },
	 { "DC_HPD1_INTERRUPT", 17, 17, &umr_bitfield_default },
	 { "DC_HPD1_RX_INTERRUPT", 18, 18, &umr_bitfield_default },
	 { "AUX1_SW_DONE_INTERRUPT", 19, 19, &umr_bitfield_default },
	 { "AUX1_LS_DONE_INTERRUPT", 20, 20, &umr_bitfield_default },
	 { "DACA_AUTODETECT_GENERITE_INTERRUPT", 22, 22, &umr_bitfield_default },
	 { "RBBMIF_IHC_TIMEOUT_INTERRUPT", 23, 23, &umr_bitfield_default },
	 { "DC_I2C_SW_DONE_INTERRUPT", 24, 24, &umr_bitfield_default },
	 { "DMCU_UC_INTERNAL_INT", 26, 26, &umr_bitfield_default },
	 { "ABM1_HG_READY_INT", 28, 28, &umr_bitfield_default },
	 { "ABM1_LS_READY_INT", 29, 29, &umr_bitfield_default },
	 { "ABM1_BL_UPDATE_INT", 30, 30, &umr_bitfield_default },
	 { "DISP_INTERRUPT_STATUS_CONTINUE", 31, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDISP_INTERRUPT_STATUS_CONTINUE[] = {
	 { "OPTC2_DATA_UNDERFLOW_INTERRUPT", 1, 1, &umr_bitfield_default },
	 { "OTG2_IHC_SNAPSHOT_INTERRUPT", 4, 4, &umr_bitfield_default },
	 { "OTG2_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT", 5, 5, &umr_bitfield_default },
	 { "OTG2_IHC_FORCE_COUNT_NOW_INTERRUPT", 6, 6, &umr_bitfield_default },
	 { "OTG2_IHC_TRIGA_INTERRUPT", 7, 7, &umr_bitfield_default },
	 { "OTG2_IHC_TRIGB_INTERRUPT", 8, 8, &umr_bitfield_default },
	 { "OTG2_IHC_VSYNC_NOM_INTERRUPT", 9, 9, &umr_bitfield_default },
	 { "OTG2_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT", 10, 10, &umr_bitfield_default },
	 { "DIGB_DP_FAST_TRAINING_COMPLETE_INTERRUPT", 15, 15, &umr_bitfield_default },
	 { "DIGB_DP_VID_STREAM_DISABLE_INTERRUPT", 16, 16, &umr_bitfield_default },
	 { "DC_HPD2_INTERRUPT", 17, 17, &umr_bitfield_default },
	 { "DC_HPD2_RX_INTERRUPT", 18, 18, &umr_bitfield_default },
	 { "AUX2_SW_DONE_INTERRUPT", 19, 19, &umr_bitfield_default },
	 { "AUX2_LS_DONE_INTERRUPT", 20, 20, &umr_bitfield_default },
	 { "OTG1_IHC_EXT_TIMING_SYNC_LOSS_INTERRUPT", 25, 25, &umr_bitfield_default },
	 { "OTG1_IHC_EXT_TIMING_SYNC_INTERRUPT", 26, 26, &umr_bitfield_default },
	 { "OTG1_IHC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT", 27, 27, &umr_bitfield_default },
	 { "OTG1_IHC_VERTICAL_INTERRUPT0", 28, 28, &umr_bitfield_default },
	 { "OTG1_IHC_VERTICAL_INTERRUPT1", 29, 29, &umr_bitfield_default },
	 { "OTG1_IHC_VERTICAL_INTERRUPT2", 30, 30, &umr_bitfield_default },
	 { "DISP_INTERRUPT_STATUS_CONTINUE2", 31, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDISP_INTERRUPT_STATUS_CONTINUE2[] = {
	 { "OPTC3_DATA_UNDERFLOW_INTERRUPT", 1, 1, &umr_bitfield_default },
	 { "OTG3_IHC_SNAPSHOT_INTERRUPT", 4, 4, &umr_bitfield_default },
	 { "OTG3_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT", 5, 5, &umr_bitfield_default },
	 { "OTG3_IHC_FORCE_COUNT_NOW_INTERRUPT", 6, 6, &umr_bitfield_default },
	 { "OTG3_IHC_TRIGA_INTERRUPT", 7, 7, &umr_bitfield_default },
	 { "OTG3_IHC_TRIGB_INTERRUPT", 8, 8, &umr_bitfield_default },
	 { "OTG3_IHC_VSYNC_NOM_INTERRUPT", 9, 9, &umr_bitfield_default },
	 { "OTG3_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT", 10, 10, &umr_bitfield_default },
	 { "DIGC_DP_FAST_TRAINING_COMPLETE_INTERRUPT", 15, 15, &umr_bitfield_default },
	 { "DIGC_DP_VID_STREAM_DISABLE_INTERRUPT", 16, 16, &umr_bitfield_default },
	 { "DC_HPD3_INTERRUPT", 17, 17, &umr_bitfield_default },
	 { "DC_HPD3_RX_INTERRUPT", 18, 18, &umr_bitfield_default },
	 { "AUX3_SW_DONE_INTERRUPT", 19, 19, &umr_bitfield_default },
	 { "AUX3_LS_DONE_INTERRUPT", 20, 20, &umr_bitfield_default },
	 { "OTG2_IHC_EXT_TIMING_SYNC_LOSS_INTERRUPT", 25, 25, &umr_bitfield_default },
	 { "OTG2_IHC_EXT_TIMING_SYNC_INTERRUPT", 26, 26, &umr_bitfield_default },
	 { "OTG2_IHC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT", 27, 27, &umr_bitfield_default },
	 { "OTG2_IHC_VERTICAL_INTERRUPT0", 28, 28, &umr_bitfield_default },
	 { "OTG2_IHC_VERTICAL_INTERRUPT1", 29, 29, &umr_bitfield_default },
	 { "OTG2_IHC_VERTICAL_INTERRUPT2", 30, 30, &umr_bitfield_default },
	 { "DISP_INTERRUPT_STATUS_CONTINUE3", 31, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDISP_INTERRUPT_STATUS_CONTINUE3[] = {
	 { "OPTC4_DATA_UNDERFLOW_INTERRUPT", 1, 1, &umr_bitfield_default },
	 { "OTG4_IHC_SNAPSHOT_INTERRUPT", 4, 4, &umr_bitfield_default },
	 { "OTG4_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT", 5, 5, &umr_bitfield_default },
	 { "OTG4_IHC_FORCE_COUNT_NOW_INTERRUPT", 6, 6, &umr_bitfield_default },
	 { "OTG4_IHC_TRIGA_INTERRUPT", 7, 7, &umr_bitfield_default },
	 { "OTG4_IHC_TRIGB_INTERRUPT", 8, 8, &umr_bitfield_default },
	 { "OTG4_IHC_VSYNC_NOM_INTERRUPT", 9, 9, &umr_bitfield_default },
	 { "OTG4_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT", 10, 10, &umr_bitfield_default },
	 { "DIGD_DP_FAST_TRAINING_COMPLETE_INTERRUPT", 15, 15, &umr_bitfield_default },
	 { "DIGD_DP_VID_STREAM_DISABLE_INTERRUPT", 16, 16, &umr_bitfield_default },
	 { "DC_HPD4_INTERRUPT", 17, 17, &umr_bitfield_default },
	 { "DC_HPD4_RX_INTERRUPT", 18, 18, &umr_bitfield_default },
	 { "AUX4_SW_DONE_INTERRUPT", 19, 19, &umr_bitfield_default },
	 { "AUX4_LS_DONE_INTERRUPT", 20, 20, &umr_bitfield_default },
	 { "WBSCL0_HOST_CONFLICT_INTERRUPT", 23, 23, &umr_bitfield_default },
	 { "WBSCL0_DATA_OVERFLOW_INTERRUPT", 24, 24, &umr_bitfield_default },
	 { "OTG3_IHC_EXT_TIMING_SYNC_LOSS_INTERRUPT", 25, 25, &umr_bitfield_default },
	 { "OTG3_IHC_EXT_TIMING_SYNC_INTERRUPT", 26, 26, &umr_bitfield_default },
	 { "OTG3_IHC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT", 27, 27, &umr_bitfield_default },
	 { "OTG3_IHC_VERTICAL_INTERRUPT0", 28, 28, &umr_bitfield_default },
	 { "OTG3_IHC_VERTICAL_INTERRUPT1", 29, 29, &umr_bitfield_default },
	 { "OTG3_IHC_VERTICAL_INTERRUPT2", 30, 30, &umr_bitfield_default },
	 { "DISP_INTERRUPT_STATUS_CONTINUE4", 31, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDISP_INTERRUPT_STATUS_CONTINUE4[] = {
	 { "OPTC5_DATA_UNDERFLOW_INTERRUPT", 0, 0, &umr_bitfield_default },
	 { "OPTC6_DATA_UNDERFLOW_INTERRUPT", 1, 1, &umr_bitfield_default },
	 { "OTG5_IHC_SNAPSHOT_INTERRUPT", 4, 4, &umr_bitfield_default },
	 { "OTG5_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT", 5, 5, &umr_bitfield_default },
	 { "OTG5_IHC_FORCE_COUNT_NOW_INTERRUPT", 6, 6, &umr_bitfield_default },
	 { "OTG5_IHC_TRIGA_INTERRUPT", 7, 7, &umr_bitfield_default },
	 { "OTG5_IHC_TRIGB_INTERRUPT", 8, 8, &umr_bitfield_default },
	 { "OTG5_IHC_VSYNC_NOM_INTERRUPT", 9, 9, &umr_bitfield_default },
	 { "OTG5_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT", 10, 10, &umr_bitfield_default },
	 { "DIGE_DP_FAST_TRAINING_COMPLETE_INTERRUPT", 15, 15, &umr_bitfield_default },
	 { "DIGE_DP_VID_STREAM_DISABLE_INTERRUPT", 16, 16, &umr_bitfield_default },
	 { "DC_HPD5_INTERRUPT", 17, 17, &umr_bitfield_default },
	 { "DC_HPD5_RX_INTERRUPT", 18, 18, &umr_bitfield_default },
	 { "AUX5_SW_DONE_INTERRUPT", 19, 19, &umr_bitfield_default },
	 { "AUX5_LS_DONE_INTERRUPT", 20, 20, &umr_bitfield_default },
	 { "OTG4_IHC_EXT_TIMING_SYNC_LOSS_INTERRUPT", 22, 22, &umr_bitfield_default },
	 { "OTG4_IHC_EXT_TIMING_SYNC_INTERRUPT", 23, 23, &umr_bitfield_default },
	 { "OTG4_IHC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT", 24, 24, &umr_bitfield_default },
	 { "OTG5_IHC_EXT_TIMING_SYNC_LOSS_INTERRUPT", 25, 25, &umr_bitfield_default },
	 { "OTG5_IHC_EXT_TIMING_SYNC_INTERRUPT", 26, 26, &umr_bitfield_default },
	 { "OTG5_IHC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT", 27, 27, &umr_bitfield_default },
	 { "OTG4_IHC_VERTICAL_INTERRUPT0", 28, 28, &umr_bitfield_default },
	 { "OTG4_IHC_VERTICAL_INTERRUPT1", 29, 29, &umr_bitfield_default },
	 { "OTG4_IHC_VERTICAL_INTERRUPT2", 30, 30, &umr_bitfield_default },
	 { "DISP_INTERRUPT_STATUS_CONTINUE5", 31, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDISP_INTERRUPT_STATUS_CONTINUE5[] = {
	 { "OTG6_IHC_SNAPSHOT_INTERRUPT", 4, 4, &umr_bitfield_default },
	 { "OTG6_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT", 5, 5, &umr_bitfield_default },
	 { "OTG6_IHC_FORCE_COUNT_NOW_INTERRUPT", 6, 6, &umr_bitfield_default },
	 { "OTG6_IHC_TRIGA_INTERRUPT", 7, 7, &umr_bitfield_default },
	 { "OTG6_IHC_TRIGB_INTERRUPT", 8, 8, &umr_bitfield_default },
	 { "OTG6_IHC_VSYNC_NOM_INTERRUPT", 9, 9, &umr_bitfield_default },
	 { "OTG6_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT", 10, 10, &umr_bitfield_default },
	 { "DIGF_DP_FAST_TRAINING_COMPLETE_INTERRUPT", 15, 15, &umr_bitfield_default },
	 { "DIGF_DP_VID_STREAM_DISABLE_INTERRUPT", 16, 16, &umr_bitfield_default },
	 { "DC_HPD6_INTERRUPT", 17, 17, &umr_bitfield_default },
	 { "DC_HPD6_RX_INTERRUPT", 18, 18, &umr_bitfield_default },
	 { "AUX6_SW_DONE_INTERRUPT", 19, 19, &umr_bitfield_default },
	 { "AUX6_LS_DONE_INTERRUPT", 20, 20, &umr_bitfield_default },
	 { "OTG6_IHC_EXT_TIMING_SYNC_LOSS_INTERRUPT", 22, 22, &umr_bitfield_default },
	 { "OTG6_IHC_EXT_TIMING_SYNC_INTERRUPT", 23, 23, &umr_bitfield_default },
	 { "OTG6_IHC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT", 24, 24, &umr_bitfield_default },
	 { "OTG5_IHC_VERTICAL_INTERRUPT0", 25, 25, &umr_bitfield_default },
	 { "OTG5_IHC_VERTICAL_INTERRUPT1", 26, 26, &umr_bitfield_default },
	 { "OTG5_IHC_VERTICAL_INTERRUPT2", 27, 27, &umr_bitfield_default },
	 { "OTG6_IHC_VERTICAL_INTERRUPT0", 28, 28, &umr_bitfield_default },
	 { "OTG6_IHC_VERTICAL_INTERRUPT1", 29, 29, &umr_bitfield_default },
	 { "OTG6_IHC_VERTICAL_INTERRUPT2", 30, 30, &umr_bitfield_default },
	 { "DISP_INTERRUPT_STATUS_CONTINUE6", 31, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDISP_INTERRUPT_STATUS_CONTINUE6[] = {
	 { "MCIF_CWB0_IHIF_INTERRUPT", 9, 9, &umr_bitfield_default },
	 { "MCIF_CWB1_IHIF_INTERRUPT", 10, 10, &umr_bitfield_default },
	 { "AUX1_GTC_SYNC_LOCK_DONE_INTERRUPT", 17, 17, &umr_bitfield_default },
	 { "AUX1_GTC_SYNC_ERROR_INTERRUPT", 18, 18, &umr_bitfield_default },
	 { "AUX2_GTC_SYNC_LOCK_DONE_INTERRUPT", 19, 19, &umr_bitfield_default },
	 { "AUX2_GTC_SYNC_ERROR_INTERRUPT", 20, 20, &umr_bitfield_default },
	 { "AUX3_GTC_SYNC_LOCK_DONE_INTERRUPT", 21, 21, &umr_bitfield_default },
	 { "AUX3_GTC_SYNC_ERROR_INTERRUPT", 22, 22, &umr_bitfield_default },
	 { "AUX4_GTC_SYNC_LOCK_DONE_INTERRUPT", 23, 23, &umr_bitfield_default },
	 { "AUX4_GTC_SYNC_ERROR_INTERRUPT", 24, 24, &umr_bitfield_default },
	 { "AUX5_GTC_SYNC_LOCK_DONE_INTERRUPT", 25, 25, &umr_bitfield_default },
	 { "AUX5_GTC_SYNC_ERROR_INTERRUPT", 26, 26, &umr_bitfield_default },
	 { "AUX6_GTC_SYNC_LOCK_DONE_INTERRUPT", 27, 27, &umr_bitfield_default },
	 { "AUX6_GTC_SYNC_ERROR_INTERRUPT", 28, 28, &umr_bitfield_default },
	 { "MCIF_DWB0_IHIF_INTERRUPT", 29, 29, &umr_bitfield_default },
	 { "MCIF_DWB1_IHIF_INTERRUPT", 30, 30, &umr_bitfield_default },
	 { "DISP_INTERRUPT_STATUS_CONTINUE7", 31, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDISP_INTERRUPT_STATUS_CONTINUE7[] = {
	 { "DCCG_PERFMON_COUNTER0_INTERRUPT", 0, 0, &umr_bitfield_default },
	 { "DCCG_PERFMON_COUNTER1_INTERRUPT", 1, 1, &umr_bitfield_default },
	 { "DMU_PERFMON_COUNTER0_INTERRUPT", 9, 9, &umr_bitfield_default },
	 { "DMU_PERFMON_COUNTER1_INTERRUPT", 10, 10, &umr_bitfield_default },
	 { "DIO_PERFMON_COUNTER0_INTERRUPT", 18, 18, &umr_bitfield_default },
	 { "DIO_PERFMON_COUNTER1_INTERRUPT", 19, 19, &umr_bitfield_default },
	 { "WB0_PERFMON_COUNTER0_INTERRUPT", 27, 27, &umr_bitfield_default },
	 { "WB0_PERFMON_COUNTER1_INTERRUPT", 28, 28, &umr_bitfield_default },
	 { "DISP_INTERRUPT_STATUS_CONTINUE8", 31, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDISP_INTERRUPT_STATUS_CONTINUE8[] = {
	 { "DPP0_PERFMON_COUNTER0_INTERRUPT", 0, 0, &umr_bitfield_default },
	 { "DPP0_PERFMON_COUNTER1_INTERRUPT", 1, 1, &umr_bitfield_default },
	 { "DPP1_PERFMON_COUNTER0_INTERRUPT", 9, 9, &umr_bitfield_default },
	 { "DPP1_PERFMON_COUNTER1_INTERRUPT", 10, 10, &umr_bitfield_default },
	 { "DPP2_PERFMON_COUNTER0_INTERRUPT", 18, 18, &umr_bitfield_default },
	 { "DPP2_PERFMON_COUNTER1_INTERRUPT", 19, 19, &umr_bitfield_default },
	 { "DISP_INTERRUPT_STATUS_CONTINUE9", 31, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDISP_INTERRUPT_STATUS_CONTINUE9[] = {
	 { "DPP3_PERFMON_COUNTER0_INTERRUPT", 0, 0, &umr_bitfield_default },
	 { "DPP3_PERFMON_COUNTER1_INTERRUPT", 1, 1, &umr_bitfield_default },
	 { "DPP4_PERFMON_COUNTER0_INTERRUPT", 9, 9, &umr_bitfield_default },
	 { "DPP4_PERFMON_COUNTER1_INTERRUPT", 10, 10, &umr_bitfield_default },
	 { "DPP5_PERFMON_COUNTER0_INTERRUPT", 18, 18, &umr_bitfield_default },
	 { "DPP5_PERFMON_COUNTER1_INTERRUPT", 19, 19, &umr_bitfield_default },
	 { "WBSCL1_HOST_CONFLICT_INTERRUPT", 28, 28, &umr_bitfield_default },
	 { "WBSCL1_DATA_OVERFLOW_INTERRUPT", 29, 29, &umr_bitfield_default },
	 { "DISP_INTERRUPT_STATUS_CONTINUE10", 31, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDISP_INTERRUPT_STATUS_CONTINUE10[] = {
	 { "DCCG_IHC_VSYNC_OTG0_LATCH_INT", 0, 0, &umr_bitfield_default },
	 { "DCCG_IHC_VSYNC_OTG1_LATCH_INT", 1, 1, &umr_bitfield_default },
	 { "DCCG_IHC_VSYNC_OTG2_LATCH_INT", 2, 2, &umr_bitfield_default },
	 { "DCCG_IHC_VSYNC_OTG3_LATCH_INT", 3, 3, &umr_bitfield_default },
	 { "DCCG_IHC_VSYNC_OTG4_LATCH_INT", 4, 4, &umr_bitfield_default },
	 { "DCCG_IHC_VSYNC_OTG5_LATCH_INT", 5, 5, &umr_bitfield_default },
	 { "DCCG_PERFMON2_COUNTER0_INTERRUPT", 12, 12, &umr_bitfield_default },
	 { "DCCG_PERFMON2_COUNTER1_INTERRUPT", 13, 13, &umr_bitfield_default },
	 { "OTG1_IHC_RANGE_TIMING_UPDATE", 22, 22, &umr_bitfield_default },
	 { "OTG2_IHC_RANGE_TIMING_UPDATE", 23, 23, &umr_bitfield_default },
	 { "OTG3_IHC_RANGE_TIMING_UPDATE", 24, 24, &umr_bitfield_default },
	 { "OTG4_IHC_RANGE_TIMING_UPDATE", 25, 25, &umr_bitfield_default },
	 { "OTG5_IHC_RANGE_TIMING_UPDATE", 26, 26, &umr_bitfield_default },
	 { "OTG6_IHC_RANGE_TIMING_UPDATE", 27, 27, &umr_bitfield_default },
	 { "DISP_INTERRUPT_STATUS_CONTINUE11", 31, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDISP_INTERRUPT_STATUS_CONTINUE11[] = {
	 { "WB1_PERFMON_COUNTER0_INTERRUPT", 6, 6, &umr_bitfield_default },
	 { "WB1_PERFMON_COUNTER1_INTERRUPT", 7, 7, &umr_bitfield_default },
	 { "MPCC0_STALL_INTERRUPT", 15, 15, &umr_bitfield_default },
	 { "MPCC1_STALL_INTERRUPT", 16, 16, &umr_bitfield_default },
	 { "MPCC2_STALL_INTERRUPT", 17, 17, &umr_bitfield_default },
	 { "MPCC3_STALL_INTERRUPT", 18, 18, &umr_bitfield_default },
	 { "MPCC4_STALL_INTERRUPT", 19, 19, &umr_bitfield_default },
	 { "MPCC5_STALL_INTERRUPT", 20, 20, &umr_bitfield_default },
	 { "MPCC6_STALL_INTERRUPT", 21, 21, &umr_bitfield_default },
	 { "MPCC7_STALL_INTERRUPT", 22, 22, &umr_bitfield_default },
	 { "VGA_IHC_VGA_CRT_INTERRUPT", 23, 23, &umr_bitfield_default },
	 { "DISP_INTERRUPT_STATUS_CONTINUE12", 31, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDISP_INTERRUPT_STATUS_CONTINUE12[] = {
	 { "MPC_PERFMON_COUNTER0_INTERRUPT", 0, 0, &umr_bitfield_default },
	 { "MPC_PERFMON_COUNTER1_INTERRUPT", 1, 1, &umr_bitfield_default },
	 { "DPP6_PERFMON_COUNTER0_INTERRUPT", 9, 9, &umr_bitfield_default },
	 { "DPP6_PERFMON_COUNTER1_INTERRUPT", 10, 10, &umr_bitfield_default },
	 { "DPP7_PERFMON_COUNTER0_INTERRUPT", 18, 18, &umr_bitfield_default },
	 { "DPP7_PERFMON_COUNTER1_INTERRUPT", 19, 19, &umr_bitfield_default },
	 { "DISP_INTERRUPT_STATUS_CONTINUE13", 31, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDISP_INTERRUPT_STATUS_CONTINUE13[] = {
	 { "HUBBUB_PERFMON_COUNTER0_INTERRUPT", 0, 0, &umr_bitfield_default },
	 { "HUBBUB_PERFMON_COUNTER1_INTERRUPT", 1, 1, &umr_bitfield_default },
	 { "DCPG_IHC_DOMAIN0_POWER_UP_INTERRUPT", 9, 9, &umr_bitfield_default },
	 { "DCPG_IHC_DOMAIN1_POWER_UP_INTERRUPT", 10, 10, &umr_bitfield_default },
	 { "DCPG_IHC_DOMAIN2_POWER_UP_INTERRUPT", 11, 11, &umr_bitfield_default },
	 { "DCPG_IHC_DOMAIN3_POWER_UP_INTERRUPT", 12, 12, &umr_bitfield_default },
	 { "DCPG_IHC_DOMAIN4_POWER_UP_INTERRUPT", 13, 13, &umr_bitfield_default },
	 { "DCPG_IHC_DOMAIN5_POWER_UP_INTERRUPT", 14, 14, &umr_bitfield_default },
	 { "DCPG_IHC_DOMAIN6_POWER_UP_INTERRUPT", 15, 15, &umr_bitfield_default },
	 { "DCPG_IHC_DOMAIN7_POWER_UP_INTERRUPT", 16, 16, &umr_bitfield_default },
	 { "HUBP0_PERFMON_COUNTER0_INTERRUPT", 18, 18, &umr_bitfield_default },
	 { "HUBP0_PERFMON_COUNTER1_INTERRUPT", 19, 19, &umr_bitfield_default },
	 { "HUBP0_IHC_VBLANK_INTERRUPT", 27, 27, &umr_bitfield_default },
	 { "HUBP0_IHC_VLINE_INTERRUPT", 28, 28, &umr_bitfield_default },
	 { "HUBP0_IHC_VLINE2_INTERRUPT", 29, 29, &umr_bitfield_default },
	 { "HUBP0_IHC_VM_CONTEXT_ERROR_INTERRUPT", 30, 30, &umr_bitfield_default },
	 { "DISP_INTERRUPT_STATUS_CONTINUE14", 31, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDISP_INTERRUPT_STATUS_CONTINUE14[] = {
	 { "HUBP1_PERFMON_COUNTER0_INTERRUPT", 0, 0, &umr_bitfield_default },
	 { "HUBP1_PERFMON_COUNTER1_INTERRUPT", 1, 1, &umr_bitfield_default },
	 { "HUBP2_PERFMON_COUNTER0_INTERRUPT", 9, 9, &umr_bitfield_default },
	 { "HUBP2_PERFMON_COUNTER1_INTERRUPT", 10, 10, &umr_bitfield_default },
	 { "HUBP3_PERFMON_COUNTER0_INTERRUPT", 18, 18, &umr_bitfield_default },
	 { "HUBP3_PERFMON_COUNTER1_INTERRUPT", 19, 19, &umr_bitfield_default },
	 { "HUBP1_IHC_VBLANK_INTERRUPT", 27, 27, &umr_bitfield_default },
	 { "HUBP1_IHC_VLINE_INTERRUPT", 28, 28, &umr_bitfield_default },
	 { "HUBP1_IHC_VLINE2_INTERRUPT", 29, 29, &umr_bitfield_default },
	 { "HUBP1_IHC_VM_CONTEXT_ERROR_INTERRUPT", 30, 30, &umr_bitfield_default },
	 { "DISP_INTERRUPT_STATUS_CONTINUE15", 31, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDISP_INTERRUPT_STATUS_CONTINUE15[] = {
	 { "HUBP4_PERFMON_COUNTER0_INTERRUPT", 0, 0, &umr_bitfield_default },
	 { "HUBP4_PERFMON_COUNTER1_INTERRUPT", 1, 1, &umr_bitfield_default },
	 { "HUBP5_PERFMON_COUNTER0_INTERRUPT", 9, 9, &umr_bitfield_default },
	 { "HUBP5_PERFMON_COUNTER1_INTERRUPT", 10, 10, &umr_bitfield_default },
	 { "HUBP6_PERFMON_COUNTER0_INTERRUPT", 18, 18, &umr_bitfield_default },
	 { "HUBP6_PERFMON_COUNTER1_INTERRUPT", 19, 19, &umr_bitfield_default },
	 { "HUBP2_IHC_VBLANK_INTERRUPT", 27, 27, &umr_bitfield_default },
	 { "HUBP2_IHC_VLINE_INTERRUPT", 28, 28, &umr_bitfield_default },
	 { "HUBP2_IHC_VLINE2_INTERRUPT", 29, 29, &umr_bitfield_default },
	 { "HUBP2_IHC_VM_CONTEXT_ERROR_INTERRUPT", 30, 30, &umr_bitfield_default },
	 { "DISP_INTERRUPT_STATUS_CONTINUE16", 31, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDISP_INTERRUPT_STATUS_CONTINUE16[] = {
	 { "HUBP7_PERFMON_COUNTER0_INTERRUPT", 0, 0, &umr_bitfield_default },
	 { "HUBP7_PERFMON_COUNTER1_INTERRUPT", 1, 1, &umr_bitfield_default },
	 { "HUBP3_IHC_VBLANK_INTERRUPT", 9, 9, &umr_bitfield_default },
	 { "HUBP3_IHC_VLINE_INTERRUPT", 10, 10, &umr_bitfield_default },
	 { "HUBP3_IHC_VLINE2_INTERRUPT", 11, 11, &umr_bitfield_default },
	 { "HUBP4_IHC_VBLANK_INTERRUPT", 12, 12, &umr_bitfield_default },
	 { "HUBP4_IHC_VLINE_INTERRUPT", 13, 13, &umr_bitfield_default },
	 { "HUBP4_IHC_VLINE2_INTERRUPT", 14, 14, &umr_bitfield_default },
	 { "HUBP5_IHC_VBLANK_INTERRUPT", 15, 15, &umr_bitfield_default },
	 { "HUBP5_IHC_VLINE_INTERRUPT", 16, 16, &umr_bitfield_default },
	 { "HUBP5_IHC_VLINE2_INTERRUPT", 17, 17, &umr_bitfield_default },
	 { "HUBP6_IHC_VBLANK_INTERRUPT", 18, 18, &umr_bitfield_default },
	 { "HUBP6_IHC_VLINE_INTERRUPT", 19, 19, &umr_bitfield_default },
	 { "HUBP6_IHC_VLINE2_INTERRUPT", 20, 20, &umr_bitfield_default },
	 { "HUBP7_IHC_VBLANK_INTERRUPT", 21, 21, &umr_bitfield_default },
	 { "HUBP7_IHC_VLINE_INTERRUPT", 22, 22, &umr_bitfield_default },
	 { "HUBP7_IHC_VLINE2_INTERRUPT", 23, 23, &umr_bitfield_default },
	 { "HUBP3_IHC_VM_CONTEXT_ERROR_INTERRUPT", 24, 24, &umr_bitfield_default },
	 { "HUBP4_IHC_VM_CONTEXT_ERROR_INTERRUPT", 25, 25, &umr_bitfield_default },
	 { "HUBP5_IHC_VM_CONTEXT_ERROR_INTERRUPT", 26, 26, &umr_bitfield_default },
	 { "HUBP6_IHC_VM_CONTEXT_ERROR_INTERRUPT", 27, 27, &umr_bitfield_default },
	 { "HUBP7_IHC_VM_CONTEXT_ERROR_INTERRUPT", 28, 28, &umr_bitfield_default },
	 { "DISP_INTERRUPT_STATUS_CONTINUE17", 31, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDISP_INTERRUPT_STATUS_CONTINUE17[] = {
	 { "OPP_PERFMON_COUNTER0_INTERRUPT", 0, 0, &umr_bitfield_default },
	 { "OPP_PERFMON_COUNTER1_INTERRUPT", 1, 1, &umr_bitfield_default },
	 { "HUBP0_IHC_FLIP_INTERRUPT", 2, 2, &umr_bitfield_default },
	 { "HUBP1_IHC_FLIP_INTERRUPT", 3, 3, &umr_bitfield_default },
	 { "HUBP2_IHC_FLIP_INTERRUPT", 4, 4, &umr_bitfield_default },
	 { "HUBP3_IHC_FLIP_INTERRUPT", 5, 5, &umr_bitfield_default },
	 { "HUBP4_IHC_FLIP_INTERRUPT", 6, 6, &umr_bitfield_default },
	 { "HUBP5_IHC_FLIP_INTERRUPT", 7, 7, &umr_bitfield_default },
	 { "HUBP6_IHC_FLIP_INTERRUPT", 8, 8, &umr_bitfield_default },
	 { "HUBP7_IHC_FLIP_INTERRUPT", 9, 9, &umr_bitfield_default },
	 { "OPTC_PERFMON_COUNTER0_INTERRUPT", 10, 10, &umr_bitfield_default },
	 { "OPTC_PERFMON_COUNTER1_INTERRUPT", 11, 11, &umr_bitfield_default },
	 { "MMHUBBUB_PERFMON_COUNTER0_INTERRUPT", 18, 18, &umr_bitfield_default },
	 { "MMHUBBUB_PERFMON_COUNTER1_INTERRUPT", 19, 19, &umr_bitfield_default },
	 { "HUBP0_IHC_FLIP_AWAY_INTERRUPT", 20, 20, &umr_bitfield_default },
	 { "HUBP1_IHC_FLIP_AWAY_INTERRUPT", 21, 21, &umr_bitfield_default },
	 { "HUBP2_IHC_FLIP_AWAY_INTERRUPT", 22, 22, &umr_bitfield_default },
	 { "HUBP3_IHC_FLIP_AWAY_INTERRUPT", 23, 23, &umr_bitfield_default },
	 { "HUBP4_IHC_FLIP_AWAY_INTERRUPT", 24, 24, &umr_bitfield_default },
	 { "HUBP5_IHC_FLIP_AWAY_INTERRUPT", 25, 25, &umr_bitfield_default },
	 { "HUBP6_IHC_FLIP_AWAY_INTERRUPT", 26, 26, &umr_bitfield_default },
	 { "HUBP7_IHC_FLIP_AWAY_INTERRUPT", 27, 27, &umr_bitfield_default },
	 { "DISP_INTERRUPT_STATUS_CONTINUE18", 31, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDISP_INTERRUPT_STATUS_CONTINUE18[] = {
	 { "AZ_PERFMON_COUNTER0_INTERRUPT", 0, 0, &umr_bitfield_default },
	 { "AZ_PERFMON_COUNTER1_INTERRUPT", 1, 1, &umr_bitfield_default },
	 { "DCIO_DPCS_TXA_IHC_ERROR_INTERRUPT", 9, 9, &umr_bitfield_default },
	 { "DCIO_DPCS_TXB_IHC_ERROR_INTERRUPT", 10, 10, &umr_bitfield_default },
	 { "DCIO_DPCS_TXC_IHC_ERROR_INTERRUPT", 11, 11, &umr_bitfield_default },
	 { "DCIO_DPCS_TXD_IHC_ERROR_INTERRUPT", 12, 12, &umr_bitfield_default },
	 { "DCIO_DPCS_TXE_IHC_ERROR_INTERRUPT", 13, 13, &umr_bitfield_default },
	 { "DCIO_DPCS_TXF_IHC_ERROR_INTERRUPT", 14, 14, &umr_bitfield_default },
	 { "DCIO_DPCS_TXG_IHC_ERROR_INTERRUPT", 15, 15, &umr_bitfield_default },
	 { "DCIO_DPCS_RXA_IHC_ERROR_INTERRUPT", 16, 16, &umr_bitfield_default },
	 { "DCPG_IHC_DOMAIN0_POWER_DOWN_INTERRUPT", 17, 17, &umr_bitfield_default },
	 { "DCPG_IHC_DOMAIN1_POWER_DOWN_INTERRUPT", 18, 18, &umr_bitfield_default },
	 { "DCPG_IHC_DOMAIN2_POWER_DOWN_INTERRUPT", 19, 19, &umr_bitfield_default },
	 { "DCPG_IHC_DOMAIN3_POWER_DOWN_INTERRUPT", 20, 20, &umr_bitfield_default },
	 { "DCPG_IHC_DOMAIN4_POWER_DOWN_INTERRUPT", 21, 21, &umr_bitfield_default },
	 { "DCPG_IHC_DOMAIN5_POWER_DOWN_INTERRUPT", 22, 22, &umr_bitfield_default },
	 { "DCPG_IHC_DOMAIN6_POWER_DOWN_INTERRUPT", 23, 23, &umr_bitfield_default },
	 { "DCPG_IHC_DOMAIN7_POWER_DOWN_INTERRUPT", 24, 24, &umr_bitfield_default },
	 { "DISP_INTERRUPT_STATUS_CONTINUE19", 31, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDISP_INTERRUPT_STATUS_CONTINUE19[] = {
	 { "AZ_IHC_ENDPOINT0_AUDIO_FORMAT_CHANGED_INT", 0, 0, &umr_bitfield_default },
	 { "AZ_IHC_ENDPOINT1_AUDIO_FORMAT_CHANGED_INT", 1, 1, &umr_bitfield_default },
	 { "AZ_IHC_ENDPOINT2_AUDIO_FORMAT_CHANGED_INT", 2, 2, &umr_bitfield_default },
	 { "AZ_IHC_ENDPOINT3_AUDIO_FORMAT_CHANGED_INT", 3, 3, &umr_bitfield_default },
	 { "AZ_IHC_ENDPOINT4_AUDIO_FORMAT_CHANGED_INT", 4, 4, &umr_bitfield_default },
	 { "AZ_IHC_ENDPOINT5_AUDIO_FORMAT_CHANGED_INT", 5, 5, &umr_bitfield_default },
	 { "AZ_IHC_ENDPOINT6_AUDIO_FORMAT_CHANGED_INT", 6, 6, &umr_bitfield_default },
	 { "AZ_IHC_ENDPOINT7_AUDIO_FORMAT_CHANGED_INT", 7, 7, &umr_bitfield_default },
	 { "AZ_IHC_ENDPOINT0_AUDIO_ENABLED_INT", 8, 8, &umr_bitfield_default },
	 { "AZ_IHC_ENDPOINT1_AUDIO_ENABLED_INT", 9, 9, &umr_bitfield_default },
	 { "AZ_IHC_ENDPOINT2_AUDIO_ENABLED_INT", 10, 10, &umr_bitfield_default },
	 { "AZ_IHC_ENDPOINT3_AUDIO_ENABLED_INT", 11, 11, &umr_bitfield_default },
	 { "AZ_IHC_ENDPOINT4_AUDIO_ENABLED_INT", 12, 12, &umr_bitfield_default },
	 { "AZ_IHC_ENDPOINT5_AUDIO_ENABLED_INT", 13, 13, &umr_bitfield_default },
	 { "AZ_IHC_ENDPOINT6_AUDIO_ENABLED_INT", 14, 14, &umr_bitfield_default },
	 { "AZ_IHC_ENDPOINT7_AUDIO_ENABLED_INT", 15, 15, &umr_bitfield_default },
	 { "AZ_IHC_ENDPOINT0_AUDIO_DISABLED_INT", 16, 16, &umr_bitfield_default },
	 { "AZ_IHC_ENDPOINT1_AUDIO_DISABLED_INT", 17, 17, &umr_bitfield_default },
	 { "AZ_IHC_ENDPOINT2_AUDIO_DISABLED_INT", 18, 18, &umr_bitfield_default },
	 { "AZ_IHC_ENDPOINT3_AUDIO_DISABLED_INT", 19, 19, &umr_bitfield_default },
	 { "AZ_IHC_ENDPOINT4_AUDIO_DISABLED_INT", 20, 20, &umr_bitfield_default },
	 { "AZ_IHC_ENDPOINT5_AUDIO_DISABLED_INT", 21, 21, &umr_bitfield_default },
	 { "AZ_IHC_ENDPOINT6_AUDIO_DISABLED_INT", 22, 22, &umr_bitfield_default },
	 { "AZ_IHC_ENDPOINT7_AUDIO_DISABLED_INT", 23, 23, &umr_bitfield_default },
	 { "DIGG_DP_FAST_TRAINING_COMPLETE_INTERRUPT", 28, 28, &umr_bitfield_default },
	 { "DIGG_DP_VID_STREAM_DISABLE_INTERRUPT", 29, 29, &umr_bitfield_default },
	 { "DISP_INTERRUPT_STATUS_CONTINUE20", 31, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDISP_INTERRUPT_STATUS_CONTINUE20[] = {
	 { "OTG1_IHC_CPU_SS_INTERRUPT", 0, 0, &umr_bitfield_default },
	 { "OTG2_IHC_CPU_SS_INTERRUPT", 1, 1, &umr_bitfield_default },
	 { "OTG3_IHC_CPU_SS_INTERRUPT", 2, 2, &umr_bitfield_default },
	 { "OTG4_IHC_CPU_SS_INTERRUPT", 3, 3, &umr_bitfield_default },
	 { "OTG5_IHC_CPU_SS_INTERRUPT", 4, 4, &umr_bitfield_default },
	 { "OTG6_IHC_CPU_SS_INTERRUPT", 5, 5, &umr_bitfield_default },
	 { "OTG1_IHC_V_UPDATE_INTERRUPT", 6, 6, &umr_bitfield_default },
	 { "OTG2_IHC_V_UPDATE_INTERRUPT", 7, 7, &umr_bitfield_default },
	 { "OTG3_IHC_V_UPDATE_INTERRUPT", 8, 8, &umr_bitfield_default },
	 { "OTG4_IHC_V_UPDATE_INTERRUPT", 9, 9, &umr_bitfield_default },
	 { "OTG5_IHC_V_UPDATE_INTERRUPT", 10, 10, &umr_bitfield_default },
	 { "OTG6_IHC_V_UPDATE_INTERRUPT", 11, 11, &umr_bitfield_default },
	 { "OTG1_IHC_GSL_VSYNC_GAP_INTERRUPT", 12, 12, &umr_bitfield_default },
	 { "OTG2_IHC_GSL_VSYNC_GAP_INTERRUPT", 13, 13, &umr_bitfield_default },
	 { "OTG3_IHC_GSL_VSYNC_GAP_INTERRUPT", 14, 14, &umr_bitfield_default },
	 { "OTG4_IHC_GSL_VSYNC_GAP_INTERRUPT", 15, 15, &umr_bitfield_default },
	 { "OTG5_IHC_GSL_VSYNC_GAP_INTERRUPT", 16, 16, &umr_bitfield_default },
	 { "OTG6_IHC_GSL_VSYNC_GAP_INTERRUPT", 17, 17, &umr_bitfield_default },
	 { "OTG1_IHC_VSTARTUP_INTERRUPT", 18, 18, &umr_bitfield_default },
	 { "OTG2_IHC_VSTARTUP_INTERRUPT", 19, 19, &umr_bitfield_default },
	 { "OTG3_IHC_VSTARTUP_INTERRUPT", 20, 20, &umr_bitfield_default },
	 { "OTG4_IHC_VSTARTUP_INTERRUPT", 21, 21, &umr_bitfield_default },
	 { "OTG5_IHC_VSTARTUP_INTERRUPT", 22, 22, &umr_bitfield_default },
	 { "OTG6_IHC_VSTARTUP_INTERRUPT", 23, 23, &umr_bitfield_default },
	 { "OTG1_IHC_VREADY_INTERRUPT", 24, 24, &umr_bitfield_default },
	 { "OTG2_IHC_VREADY_INTERRUPT", 25, 25, &umr_bitfield_default },
	 { "OTG3_IHC_VREADY_INTERRUPT", 26, 26, &umr_bitfield_default },
	 { "OTG4_IHC_VREADY_INTERRUPT", 27, 27, &umr_bitfield_default },
	 { "OTG5_IHC_VREADY_INTERRUPT", 28, 28, &umr_bitfield_default },
	 { "OTG6_IHC_VREADY_INTERRUPT", 29, 29, &umr_bitfield_default },
	 { "DISP_INTERRUPT_STATUS_CONTINUE21", 31, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDISP_INTERRUPT_STATUS_CONTINUE21[] = {
	 { "DOUT_IHC_I2C_DDC1_HW_DONE_INTERRUPT", 0, 0, &umr_bitfield_default },
	 { "DOUT_IHC_I2C_DDC2_HW_DONE_INTERRUPT", 1, 1, &umr_bitfield_default },
	 { "DOUT_IHC_I2C_DDC3_HW_DONE_INTERRUPT", 2, 2, &umr_bitfield_default },
	 { "DOUT_IHC_I2C_DDC4_HW_DONE_INTERRUPT", 3, 3, &umr_bitfield_default },
	 { "DOUT_IHC_I2C_DDC5_HW_DONE_INTERRUPT", 4, 4, &umr_bitfield_default },
	 { "DOUT_IHC_I2C_DDC6_HW_DONE_INTERRUPT", 5, 5, &umr_bitfield_default },
	 { "DOUT_IHC_I2C_DDCVGA_HW_DONE_INTERRUPT", 6, 6, &umr_bitfield_default },
	 { "DC_I2C_DDC1_READ_REQUEST_INTERRUPT", 7, 7, &umr_bitfield_default },
	 { "DC_I2C_DDC2_READ_REQUEST_INTERRUPT", 8, 8, &umr_bitfield_default },
	 { "DC_I2C_DDC3_READ_REQUEST_INTERRUPT", 9, 9, &umr_bitfield_default },
	 { "DC_I2C_DDC4_READ_REQUEST_INTERRUPT", 10, 10, &umr_bitfield_default },
	 { "DC_I2C_DDC5_READ_REQUEST_INTERRUPT", 11, 11, &umr_bitfield_default },
	 { "DC_I2C_DDC6_READ_REQUEST_INTERRUPT", 12, 12, &umr_bitfield_default },
	 { "DC_I2C_VGA_READ_REQUEST_INTERRUPT", 13, 13, &umr_bitfield_default },
	 { "GENERIC_I2C_DDC_READ_REUEST_INTERRUPT", 14, 14, &umr_bitfield_default },
	 { "DIGH_DP_FAST_TRAINING_COMPLETE_INTERRUPT", 28, 28, &umr_bitfield_default },
	 { "DIGH_DP_VID_STREAM_DISABLE_INTERRUPT", 29, 29, &umr_bitfield_default },
	 { "DISP_INTERRUPT_STATUS_CONTINUE22", 31, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDISP_INTERRUPT_STATUS_CONTINUE22[] = {
	 { "DCPG_IHC_DOMAIN8_POWER_UP_INTERRUPT", 0, 0, &umr_bitfield_default },
	 { "DCPG_IHC_DOMAIN9_POWER_UP_INTERRUPT", 1, 1, &umr_bitfield_default },
	 { "DCPG_IHC_DOMAIN10_POWER_UP_INTERRUPT", 2, 2, &umr_bitfield_default },
	 { "DCPG_IHC_DOMAIN11_POWER_UP_INTERRUPT", 3, 3, &umr_bitfield_default },
	 { "DCPG_IHC_DOMAIN12_POWER_UP_INTERRUPT", 4, 4, &umr_bitfield_default },
	 { "DCPG_IHC_DOMAIN13_POWER_UP_INTERRUPT", 5, 5, &umr_bitfield_default },
	 { "DCPG_IHC_DOMAIN14_POWER_UP_INTERRUPT", 6, 6, &umr_bitfield_default },
	 { "DCPG_IHC_DOMAIN15_POWER_UP_INTERRUPT", 7, 7, &umr_bitfield_default },
	 { "DCPG_IHC_DOMAIN8_POWER_DOWN_INTERRUPT", 8, 8, &umr_bitfield_default },
	 { "DCPG_IHC_DOMAIN9_POWER_DOWN_INTERRUPT", 9, 9, &umr_bitfield_default },
	 { "DCPG_IHC_DOMAIN10_POWER_DOWN_INTERRUPT", 10, 10, &umr_bitfield_default },
	 { "DCPG_IHC_DOMAIN11_POWER_DOWN_INTERRUPT", 11, 11, &umr_bitfield_default },
	 { "DCPG_IHC_DOMAIN12_POWER_DOWN_INTERRUPT", 12, 12, &umr_bitfield_default },
	 { "DCPG_IHC_DOMAIN13_POWER_DOWN_INTERRUPT", 13, 13, &umr_bitfield_default },
	 { "DCPG_IHC_DOMAIN14_POWER_DOWN_INTERRUPT", 14, 14, &umr_bitfield_default },
	 { "DCPG_IHC_DOMAIN15_POWER_DOWN_INTERRUPT", 15, 15, &umr_bitfield_default },
	 { "ABM0_HG_READY_INT", 16, 16, &umr_bitfield_default },
	 { "ABM0_LS_READY_INT", 17, 17, &umr_bitfield_default },
	 { "ABM0_BL_UPDATE_INT", 18, 18, &umr_bitfield_default },
	 { "OTG0_IHC_V_UPDATE_NO_LOCK_INTERRUPT", 19, 19, &umr_bitfield_default },
	 { "OTG1_IHC_V_UPDATE_NO_LOCK_INTERRUPT", 20, 20, &umr_bitfield_default },
	 { "OTG2_IHC_V_UPDATE_NO_LOCK_INTERRUPT", 21, 21, &umr_bitfield_default },
	 { "OTG3_IHC_V_UPDATE_NO_LOCK_INTERRUPT", 22, 22, &umr_bitfield_default },
	 { "OTG4_IHC_V_UPDATE_NO_LOCK_INTERRUPT", 23, 23, &umr_bitfield_default },
	 { "OTG5_IHC_V_UPDATE_NO_LOCK_INTERRUPT", 24, 24, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_GPU_TIMER_START_POSITION_VREADY[] = {
	 { "DC_GPU_TIMER_START_POSITION_D1_VREADY", 0, 2, &umr_bitfield_default },
	 { "DC_GPU_TIMER_START_POSITION_D2_VREADY", 4, 6, &umr_bitfield_default },
	 { "DC_GPU_TIMER_START_POSITION_D3_VREADY", 8, 10, &umr_bitfield_default },
	 { "DC_GPU_TIMER_START_POSITION_D4_VREADY", 12, 14, &umr_bitfield_default },
	 { "DC_GPU_TIMER_START_POSITION_D5_VREADY", 16, 18, &umr_bitfield_default },
	 { "DC_GPU_TIMER_START_POSITION_D6_VREADY", 20, 22, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_GPU_TIMER_START_POSITION_FLIP[] = {
	 { "DC_GPU_TIMER_START_POSITION_D1_FLIP", 0, 2, &umr_bitfield_default },
	 { "DC_GPU_TIMER_START_POSITION_D2_FLIP", 4, 6, &umr_bitfield_default },
	 { "DC_GPU_TIMER_START_POSITION_D3_FLIP", 8, 10, &umr_bitfield_default },
	 { "DC_GPU_TIMER_START_POSITION_D4_FLIP", 12, 14, &umr_bitfield_default },
	 { "DC_GPU_TIMER_START_POSITION_D5_FLIP", 16, 18, &umr_bitfield_default },
	 { "DC_GPU_TIMER_START_POSITION_D6_FLIP", 20, 22, &umr_bitfield_default },
	 { "DC_GPU_TIMER_START_POSITION_D7_FLIP", 24, 26, &umr_bitfield_default },
	 { "DC_GPU_TIMER_START_POSITION_D8_FLIP", 28, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_GPU_TIMER_START_POSITION_V_UPDATE_NO_LOCK[] = {
	 { "DC_GPU_TIMER_START_POSITION_D1_V_UPDATE_NO_LOCK", 0, 2, &umr_bitfield_default },
	 { "DC_GPU_TIMER_START_POSITION_D2_V_UPDATE_NO_LOCK", 4, 6, &umr_bitfield_default },
	 { "DC_GPU_TIMER_START_POSITION_D3_V_UPDATE_NO_LOCK", 8, 10, &umr_bitfield_default },
	 { "DC_GPU_TIMER_START_POSITION_D4_V_UPDATE_NO_LOCK", 12, 14, &umr_bitfield_default },
	 { "DC_GPU_TIMER_START_POSITION_D5_V_UPDATE_NO_LOCK", 16, 18, &umr_bitfield_default },
	 { "DC_GPU_TIMER_START_POSITION_D6_V_UPDATE_NO_LOCK", 20, 22, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_GPU_TIMER_START_POSITION_FLIP_AWAY[] = {
	 { "DC_GPU_TIMER_START_POSITION_D1_FLIP_AWAY", 0, 2, &umr_bitfield_default },
	 { "DC_GPU_TIMER_START_POSITION_D2_FLIP_AWAY", 4, 6, &umr_bitfield_default },
	 { "DC_GPU_TIMER_START_POSITION_D3_FLIP_AWAY", 8, 10, &umr_bitfield_default },
	 { "DC_GPU_TIMER_START_POSITION_D4_FLIP_AWAY", 12, 14, &umr_bitfield_default },
	 { "DC_GPU_TIMER_START_POSITION_D5_FLIP_AWAY", 16, 18, &umr_bitfield_default },
	 { "DC_GPU_TIMER_START_POSITION_D6_FLIP_AWAY", 20, 22, &umr_bitfield_default },
	 { "DC_GPU_TIMER_START_POSITION_D7_FLIP_AWAY", 24, 26, &umr_bitfield_default },
	 { "DC_GPU_TIMER_START_POSITION_D8_FLIP_AWAY", 28, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmCNV0_WB_ENABLE[] = {
	 { "WB_ENABLE", 0, 0, &umr_bitfield_default },
};
static struct umr_bitfield mmCNV0_WB_EC_CONFIG[] = {
	 { "DISPCLK_R_WB_GATE_DIS", 0, 0, &umr_bitfield_default },
	 { "DISPCLK_G_WB_GATE_DIS", 1, 1, &umr_bitfield_default },
	 { "DISPCLK_G_WBSCL_GATE_DIS", 2, 2, &umr_bitfield_default },
	 { "WB_TEST_CLK_SEL", 3, 6, &umr_bitfield_default },
	 { "WB_LB_LS_DIS", 7, 7, &umr_bitfield_default },
	 { "WB_LB_SD_DIS", 8, 8, &umr_bitfield_default },
	 { "WB_LUT_LS_DIS", 9, 9, &umr_bitfield_default },
	 { "WBSCL_LB_MEM_PWR_MODE_SEL", 12, 13, &umr_bitfield_default },
	 { "WBSCL_LB_MEM_PWR_DIS", 14, 14, &umr_bitfield_default },
	 { "WBSCL_LB_MEM_PWR_FORCE", 15, 16, &umr_bitfield_default },
	 { "WBSCL_LB_MEM_PWR_STATE_SM", 17, 18, &umr_bitfield_default },
	 { "WBSCL_LB_MEM_PWR_STATE_BG", 19, 20, &umr_bitfield_default },
	 { "WBSCL_LB_MEM_PWR_STATE", 21, 22, &umr_bitfield_default },
	 { "WB_RAM_PW_SAVE_MODE", 23, 23, &umr_bitfield_default },
	 { "LB_MEM_PWR_STATE_SM", 24, 25, &umr_bitfield_default },
	 { "LB_MEM_PWR_STATE_BG", 26, 27, &umr_bitfield_default },
	 { "LB_MEM_PWR_STATE", 28, 29, &umr_bitfield_default },
	 { "LUT_MEM_PWR_STATE", 30, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmCNV0_CNV_MODE[] = {
	 { "CNV_FRAME_CAPTURE_RATE", 8, 9, &umr_bitfield_default },
	 { "CNV_WINDOW_CROP_EN", 12, 12, &umr_bitfield_default },
	 { "CNV_STEREO_TYPE", 13, 14, &umr_bitfield_default },
	 { "CNV_INTERLACED_MODE", 15, 15, &umr_bitfield_default },
	 { "CNV_EYE_SELECTION", 16, 17, &umr_bitfield_default },
	 { "CNV_STEREO_POLARITY", 18, 18, &umr_bitfield_default },
	 { "CNV_INTERLACED_FIELD_ORDER", 19, 19, &umr_bitfield_default },
	 { "CNV_STEREO_SPLIT", 20, 20, &umr_bitfield_default },
	 { "CNV_NEW_CONTENT", 24, 24, &umr_bitfield_default },
	 { "CNV_FRAME_CAPTURE_EN", 31, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmCNV0_CNV_WINDOW_START[] = {
	 { "CNV_WINDOW_START_X", 0, 11, &umr_bitfield_default },
	 { "CNV_WINDOW_START_Y", 16, 27, &umr_bitfield_default },
};
static struct umr_bitfield mmCNV0_CNV_WINDOW_SIZE[] = {
	 { "CNV_WINDOW_WIDTH", 0, 11, &umr_bitfield_default },
	 { "CNV_WINDOW_HEIGHT", 16, 27, &umr_bitfield_default },
};
static struct umr_bitfield mmCNV0_CNV_UPDATE[] = {
	 { "CNV_UPDATE_PENDING", 0, 0, &umr_bitfield_default },
	 { "CNV_UPDATE_TAKEN", 8, 8, &umr_bitfield_default },
	 { "CNV_UPDATE_LOCK", 16, 16, &umr_bitfield_default },
};
static struct umr_bitfield mmCNV0_CNV_SOURCE_SIZE[] = {
	 { "CNV_SOURCE_WIDTH", 0, 14, &umr_bitfield_default },
	 { "CNV_SOURCE_HEIGHT", 16, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmCNV0_CNV_CSC_CONTROL[] = {
	 { "CNV_CSC_BYPASS", 0, 0, &umr_bitfield_default },
};
static struct umr_bitfield mmCNV0_CNV_CSC_C11_C12[] = {
	 { "CNV_CSC_C11", 0, 12, &umr_bitfield_default },
	 { "CNV_CSC_C12", 16, 28, &umr_bitfield_default },
};
static struct umr_bitfield mmCNV0_CNV_CSC_C13_C14[] = {
	 { "CNV_CSC_C13", 0, 12, &umr_bitfield_default },
	 { "CNV_CSC_C14", 16, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmCNV0_CNV_CSC_C21_C22[] = {
	 { "CNV_CSC_C21", 0, 12, &umr_bitfield_default },
	 { "CNV_CSC_C22", 16, 28, &umr_bitfield_default },
};
static struct umr_bitfield mmCNV0_CNV_CSC_C23_C24[] = {
	 { "CNV_CSC_C23", 0, 12, &umr_bitfield_default },
	 { "CNV_CSC_C24", 16, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmCNV0_CNV_CSC_C31_C32[] = {
	 { "CNV_CSC_C31", 0, 12, &umr_bitfield_default },
	 { "CNV_CSC_C32", 16, 28, &umr_bitfield_default },
};
static struct umr_bitfield mmCNV0_CNV_CSC_C33_C34[] = {
	 { "CNV_CSC_C33", 0, 12, &umr_bitfield_default },
	 { "CNV_CSC_C34", 16, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmCNV0_CNV_CSC_ROUND_OFFSET_R[] = {
	 { "CNV_CSC_ROUND_OFFSET_R", 0, 15, &umr_bitfield_default },
};
static struct umr_bitfield mmCNV0_CNV_CSC_ROUND_OFFSET_G[] = {
	 { "CNV_CSC_ROUND_OFFSET_G", 0, 15, &umr_bitfield_default },
};
static struct umr_bitfield mmCNV0_CNV_CSC_ROUND_OFFSET_B[] = {
	 { "CNV_CSC_ROUND_OFFSET_B", 0, 15, &umr_bitfield_default },
};
static struct umr_bitfield mmCNV0_CNV_CSC_CLAMP_R[] = {
	 { "CNV_CSC_CLAMP_UPPER_R", 0, 15, &umr_bitfield_default },
	 { "CNV_CSC_CLAMP_LOWER_R", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmCNV0_CNV_CSC_CLAMP_G[] = {
	 { "CNV_CSC_CLAMP_UPPER_G", 0, 15, &umr_bitfield_default },
	 { "CNV_CSC_CLAMP_LOWER_G", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmCNV0_CNV_CSC_CLAMP_B[] = {
	 { "CNV_CSC_CLAMP_UPPER_B", 0, 15, &umr_bitfield_default },
	 { "CNV_CSC_CLAMP_LOWER_B", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmCNV0_CNV_TEST_CNTL[] = {
	 { "CNV_TEST_CRC_EN", 4, 4, &umr_bitfield_default },
	 { "CNV_TEST_CRC_CONT_EN", 8, 8, &umr_bitfield_default },
	 { "CNV_TEST_CRC_DE_ONLY", 16, 16, &umr_bitfield_default },
};
static struct umr_bitfield mmCNV0_CNV_TEST_CRC_RED[] = {
	 { "CNV_TEST_CRC_RED_MASK", 4, 15, &umr_bitfield_default },
	 { "CNV_TEST_CRC_SIG_RED", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmCNV0_CNV_TEST_CRC_GREEN[] = {
	 { "CNV_TEST_CRC_GREEN_MASK", 4, 15, &umr_bitfield_default },
	 { "CNV_TEST_CRC_SIG_GREEN", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmCNV0_CNV_TEST_CRC_BLUE[] = {
	 { "CNV_TEST_CRC_BLUE_MASK", 4, 15, &umr_bitfield_default },
	 { "CNV_TEST_CRC_SIG_BLUE", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmCNV0_CNV_INPUT_SELECT[] = {
	 { "CNV_INPUT_SRC_SELECT", 0, 1, &umr_bitfield_default },
	 { "CNV_INPUT_PIPE_SELECT", 2, 4, &umr_bitfield_default },
};
static struct umr_bitfield mmCNV0_WB_SOFT_RESET[] = {
	 { "WB_SOFT_RESET", 0, 0, &umr_bitfield_default },
};
static struct umr_bitfield mmCNV0_WB_WARM_UP_MODE_CTL1[] = {
	 { "WIDTH_WARMUP", 0, 14, &umr_bitfield_default },
	 { "HEIGHT_WARMUP", 16, 30, &umr_bitfield_default },
	 { "GMC_WARM_UP_ENABLE", 31, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmCNV0_WB_WARM_UP_MODE_CTL2[] = {
	 { "DATA_VALUE_WARMUP", 0, 7, &umr_bitfield_default },
	 { "MODE_WARMUP", 8, 8, &umr_bitfield_default },
};
static struct umr_bitfield mmWBSCL0_WBSCL_COEF_RAM_SELECT[] = {
	 { "WBSCL_COEF_RAM_TAP_PAIR_IDX", 0, 2, &umr_bitfield_default },
	 { "WBSCL_COEF_RAM_PHASE", 8, 11, &umr_bitfield_default },
	 { "WBSCL_COEF_RAM_FILTER_TYPE", 16, 17, &umr_bitfield_default },
};
static struct umr_bitfield mmWBSCL0_WBSCL_COEF_RAM_TAP_DATA[] = {
	 { "WBSCL_COEF_RAM_EVEN_TAP_COEF", 0, 13, &umr_bitfield_default },
	 { "WBSCL_COEF_RAM_EVEN_TAP_COEF_EN", 15, 15, &umr_bitfield_default },
	 { "WBSCL_COEF_RAM_ODD_TAP_COEF", 16, 29, &umr_bitfield_default },
	 { "WBSCL_COEF_RAM_ODD_TAP_COEF_EN", 31, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmWBSCL0_WBSCL_MODE[] = {
	 { "WBSCL_MODE", 0, 1, &umr_bitfield_default },
};
static struct umr_bitfield mmWBSCL0_WBSCL_TAP_CONTROL[] = {
	 { "WBSCL_V_NUM_OF_TAPS_Y_RGB", 0, 3, &umr_bitfield_default },
	 { "WBSCL_V_NUM_OF_TAPS_CBCR", 4, 7, &umr_bitfield_default },
	 { "WBSCL_H_NUM_OF_TAPS_Y_RGB", 8, 11, &umr_bitfield_default },
	 { "WBSCL_H_NUM_OF_TAPS_CBCR", 12, 15, &umr_bitfield_default },
};
static struct umr_bitfield mmWBSCL0_WBSCL_DEST_SIZE[] = {
	 { "WBSCL_DEST_HEIGHT", 0, 14, &umr_bitfield_default },
	 { "WBSCL_DEST_WIDTH", 16, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmWBSCL0_WBSCL_HORZ_FILTER_SCALE_RATIO[] = {
	 { "WBSCL_H_SCALE_RATIO", 0, 26, &umr_bitfield_default },
};
static struct umr_bitfield mmWBSCL0_WBSCL_HORZ_FILTER_INIT_Y_RGB[] = {
	 { "WBSCL_H_INIT_FRAC_Y_RGB", 0, 23, &umr_bitfield_default },
	 { "WBSCL_H_INIT_INT_Y_RGB", 24, 28, &umr_bitfield_default },
};
static struct umr_bitfield mmWBSCL0_WBSCL_HORZ_FILTER_INIT_CBCR[] = {
	 { "WBSCL_H_INIT_FRAC_CBCR", 0, 23, &umr_bitfield_default },
	 { "WBSCL_H_INIT_INT_CBCR", 24, 28, &umr_bitfield_default },
};
static struct umr_bitfield mmWBSCL0_WBSCL_VERT_FILTER_SCALE_RATIO[] = {
	 { "WBSCL_V_SCALE_RATIO", 0, 26, &umr_bitfield_default },
};
static struct umr_bitfield mmWBSCL0_WBSCL_VERT_FILTER_INIT_Y_RGB[] = {
	 { "WBSCL_V_INIT_FRAC_Y_RGB", 0, 23, &umr_bitfield_default },
	 { "WBSCL_V_INIT_INT_Y_RGB", 24, 28, &umr_bitfield_default },
};
static struct umr_bitfield mmWBSCL0_WBSCL_VERT_FILTER_INIT_CBCR[] = {
	 { "WBSCL_V_INIT_FRAC_CBCR", 0, 23, &umr_bitfield_default },
	 { "WBSCL_V_INIT_INT_CBCR", 24, 28, &umr_bitfield_default },
};
static struct umr_bitfield mmWBSCL0_WBSCL_ROUND_OFFSET[] = {
	 { "WBSCL_ROUND_OFFSET_Y_RGB", 0, 15, &umr_bitfield_default },
	 { "WBSCL_ROUND_OFFSET_CBCR", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmWBSCL0_WBSCL_CLAMP[] = {
	 { "WBSCL_CLAMP_UPPER_Y_RGB", 0, 7, &umr_bitfield_default },
	 { "WBSCL_CLAMP_LOWER_Y_RGB", 8, 15, &umr_bitfield_default },
	 { "WBSCL_CLAMP_UPPER_CBCR", 16, 23, &umr_bitfield_default },
	 { "WBSCL_CLAMP_LOWER_CBCR", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmWBSCL0_WBSCL_OVERFLOW_STATUS[] = {
	 { "WBSCL_DATA_OVERFLOW_FLAG", 0, 0, &umr_bitfield_default },
	 { "WBSCL_DATA_OVERFLOW_ACK", 8, 8, &umr_bitfield_default },
	 { "WBSCL_DATA_OVERFLOW_MASK", 12, 12, &umr_bitfield_default },
	 { "WBSCL_DATA_OVERFLOW_INT_STATUS", 16, 16, &umr_bitfield_default },
	 { "WBSCL_DATA_OVERFLOW_INT_TYPE", 20, 20, &umr_bitfield_default },
};
static struct umr_bitfield mmWBSCL0_WBSCL_COEF_RAM_CONFLICT_STATUS[] = {
	 { "WBSCL_HOST_CONFLICT_FLAG", 0, 0, &umr_bitfield_default },
	 { "WBSCL_HOST_CONFLICT_ACK", 8, 8, &umr_bitfield_default },
	 { "WBSCL_HOST_CONFLICT_MASK", 12, 12, &umr_bitfield_default },
	 { "WBSCL_HOST_CONFLICT_INT_STATUS", 16, 16, &umr_bitfield_default },
	 { "WBSCL_HOST_CONFLICT_INT_TYPE", 20, 20, &umr_bitfield_default },
};
static struct umr_bitfield mmWBSCL0_WBSCL_OUTSIDE_PIX_STRATEGY[] = {
	 { "WBSCL_OUTSIDE_PIX_STRATEGY", 0, 0, &umr_bitfield_default },
	 { "WBSCL_BLACK_COLOR_B_CB", 8, 15, &umr_bitfield_default },
	 { "WBSCL_BLACK_COLOR_G_Y", 16, 23, &umr_bitfield_default },
	 { "WBSCL_BLACK_COLOR_R_CR", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmWBSCL0_WBSCL_TEST_CNTL[] = {
	 { "WBSCL_TEST_CRC_EN", 4, 4, &umr_bitfield_default },
	 { "WBSCL_TEST_CRC_CONT_EN", 8, 8, &umr_bitfield_default },
	 { "WBSCL_TEST_CRC_DE_ONLY", 16, 16, &umr_bitfield_default },
};
static struct umr_bitfield mmWBSCL0_WBSCL_TEST_CRC_RED[] = {
	 { "WBSCL_TEST_CRC_RED_MASK", 8, 15, &umr_bitfield_default },
	 { "WBSCL_TEST_CRC_SIG_RED", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmWBSCL0_WBSCL_TEST_CRC_GREEN[] = {
	 { "WBSCL_TEST_CRC_GREEN_MASK", 0, 15, &umr_bitfield_default },
	 { "WBSCL_TEST_CRC_SIG_GREEN", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmWBSCL0_WBSCL_TEST_CRC_BLUE[] = {
	 { "WBSCL_TEST_CRC_BLUE_MASK", 8, 15, &umr_bitfield_default },
	 { "WBSCL_TEST_CRC_SIG_BLUE", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmWBSCL0_WBSCL_BACKPRESSURE_CNT_EN[] = {
	 { "WBSCL_BACKPRESSURE_CNT_EN", 0, 0, &umr_bitfield_default },
};
static struct umr_bitfield mmWBSCL0_WB_MCIF_BACKPRESSURE_CNT[] = {
	 { "WB_MCIF_Y_MAX_BACKPRESSURE", 0, 15, &umr_bitfield_default },
	 { "WB_MCIF_C_MAX_BACKPRESSURE", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmWBSCL0_WBSCL_RAM_SHUTDOWN[] = {
	 { "WBSCL_RAM_SHUTDOWN_SEL", 0, 1, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_PERFMON3_PERFCOUNTER_CNTL[] = {
	 { "PERFCOUNTER_EVENT_SEL", 0, 8, &umr_bitfield_default },
	 { "PERFCOUNTER_CVALUE_SEL", 9, 11, &umr_bitfield_default },
	 { "PERFCOUNTER_INC_MODE", 12, 14, &umr_bitfield_default },
	 { "PERFCOUNTER_HW_CNTL_SEL", 15, 15, &umr_bitfield_default },
	 { "PERFCOUNTER_RUNEN_MODE", 16, 16, &umr_bitfield_default },
	 { "PERFCOUNTER_CNTOFF_START_DIS", 22, 22, &umr_bitfield_default },
	 { "PERFCOUNTER_RESTART_EN", 23, 23, &umr_bitfield_default },
	 { "PERFCOUNTER_INT_EN", 24, 24, &umr_bitfield_default },
	 { "PERFCOUNTER_OFF_MASK", 25, 25, &umr_bitfield_default },
	 { "PERFCOUNTER_ACTIVE", 26, 26, &umr_bitfield_default },
	 { "PERFCOUNTER_CNTL_SEL", 29, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_PERFMON3_PERFCOUNTER_CNTL2[] = {
	 { "PERFCOUNTER_COUNTED_VALUE_TYPE", 0, 1, &umr_bitfield_default },
	 { "PERFCOUNTER_HW_STOP1_SEL", 2, 2, &umr_bitfield_default },
	 { "PERFCOUNTER_HW_STOP2_SEL", 3, 3, &umr_bitfield_default },
	 { "PERFCOUNTER_CNTOFF_SEL", 8, 13, &umr_bitfield_default },
	 { "PERFCOUNTER_CNTL2_SEL", 29, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_PERFMON3_PERFCOUNTER_STATE[] = {
	 { "PERFCOUNTER_CNT0_STATE", 0, 1, &umr_bitfield_default },
	 { "PERFCOUNTER_STATE_SEL0", 2, 2, &umr_bitfield_default },
	 { "PERFCOUNTER_CNT1_STATE", 4, 5, &umr_bitfield_default },
	 { "PERFCOUNTER_STATE_SEL1", 6, 6, &umr_bitfield_default },
	 { "PERFCOUNTER_CNT2_STATE", 8, 9, &umr_bitfield_default },
	 { "PERFCOUNTER_STATE_SEL2", 10, 10, &umr_bitfield_default },
	 { "PERFCOUNTER_CNT3_STATE", 12, 13, &umr_bitfield_default },
	 { "PERFCOUNTER_STATE_SEL3", 14, 14, &umr_bitfield_default },
	 { "PERFCOUNTER_CNT4_STATE", 16, 17, &umr_bitfield_default },
	 { "PERFCOUNTER_STATE_SEL4", 18, 18, &umr_bitfield_default },
	 { "PERFCOUNTER_CNT5_STATE", 20, 21, &umr_bitfield_default },
	 { "PERFCOUNTER_STATE_SEL5", 22, 22, &umr_bitfield_default },
	 { "PERFCOUNTER_CNT6_STATE", 24, 25, &umr_bitfield_default },
	 { "PERFCOUNTER_STATE_SEL6", 26, 26, &umr_bitfield_default },
	 { "PERFCOUNTER_CNT7_STATE", 28, 29, &umr_bitfield_default },
	 { "PERFCOUNTER_STATE_SEL7", 30, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_PERFMON3_PERFMON_CNTL[] = {
	 { "PERFMON_STATE", 0, 1, &umr_bitfield_default },
	 { "PERFMON_RPT_COUNT", 8, 27, &umr_bitfield_default },
	 { "PERFMON_CNTOFF_AND_OR", 28, 28, &umr_bitfield_default },
	 { "PERFMON_CNTOFF_INT_EN", 29, 29, &umr_bitfield_default },
	 { "PERFMON_CNTOFF_INT_STATUS", 30, 30, &umr_bitfield_default },
	 { "PERFMON_CNTOFF_INT_ACK", 31, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_PERFMON3_PERFMON_CNTL2[] = {
	 { "PERFMON_CNTOFF_INT_TYPE", 0, 0, &umr_bitfield_default },
	 { "PERFMON_CLK_ENABLE", 1, 1, &umr_bitfield_default },
	 { "PERFMON_RUN_ENABLE_START_SEL", 2, 9, &umr_bitfield_default },
	 { "PERFMON_RUN_ENABLE_STOP_SEL", 10, 17, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_PERFMON3_PERFMON_CVALUE_INT_MISC[] = {
	 { "PERFCOUNTER_INT0_STATUS", 0, 0, &umr_bitfield_default },
	 { "PERFCOUNTER_INT1_STATUS", 1, 1, &umr_bitfield_default },
	 { "PERFCOUNTER_INT2_STATUS", 2, 2, &umr_bitfield_default },
	 { "PERFCOUNTER_INT3_STATUS", 3, 3, &umr_bitfield_default },
	 { "PERFCOUNTER_INT4_STATUS", 4, 4, &umr_bitfield_default },
	 { "PERFCOUNTER_INT5_STATUS", 5, 5, &umr_bitfield_default },
	 { "PERFCOUNTER_INT6_STATUS", 6, 6, &umr_bitfield_default },
	 { "PERFCOUNTER_INT7_STATUS", 7, 7, &umr_bitfield_default },
	 { "PERFCOUNTER_INT0_ACK", 8, 8, &umr_bitfield_default },
	 { "PERFCOUNTER_INT1_ACK", 9, 9, &umr_bitfield_default },
	 { "PERFCOUNTER_INT2_ACK", 10, 10, &umr_bitfield_default },
	 { "PERFCOUNTER_INT3_ACK", 11, 11, &umr_bitfield_default },
	 { "PERFCOUNTER_INT4_ACK", 12, 12, &umr_bitfield_default },
	 { "PERFCOUNTER_INT5_ACK", 13, 13, &umr_bitfield_default },
	 { "PERFCOUNTER_INT6_ACK", 14, 14, &umr_bitfield_default },
	 { "PERFCOUNTER_INT7_ACK", 15, 15, &umr_bitfield_default },
	 { "PERFMON_CVALUE_HI", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_PERFMON3_PERFMON_CVALUE_LOW[] = {
	 { "PERFMON_CVALUE_LOW", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_PERFMON3_PERFMON_HI[] = {
	 { "PERFMON_HI", 0, 15, &umr_bitfield_default },
	 { "PERFMON_READ_SEL", 29, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_PERFMON3_PERFMON_LOW[] = {
	 { "PERFMON_LOW", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmCNV1_WB_ENABLE[] = {
	 { "WB_ENABLE", 0, 0, &umr_bitfield_default },
};
static struct umr_bitfield mmCNV1_WB_EC_CONFIG[] = {
	 { "DISPCLK_R_WB_GATE_DIS", 0, 0, &umr_bitfield_default },
	 { "DISPCLK_G_WB_GATE_DIS", 1, 1, &umr_bitfield_default },
	 { "DISPCLK_G_WBSCL_GATE_DIS", 2, 2, &umr_bitfield_default },
	 { "WB_TEST_CLK_SEL", 3, 6, &umr_bitfield_default },
	 { "WB_LB_LS_DIS", 7, 7, &umr_bitfield_default },
	 { "WB_LB_SD_DIS", 8, 8, &umr_bitfield_default },
	 { "WB_LUT_LS_DIS", 9, 9, &umr_bitfield_default },
	 { "WBSCL_LB_MEM_PWR_MODE_SEL", 12, 13, &umr_bitfield_default },
	 { "WBSCL_LB_MEM_PWR_DIS", 14, 14, &umr_bitfield_default },
	 { "WBSCL_LB_MEM_PWR_FORCE", 15, 16, &umr_bitfield_default },
	 { "WBSCL_LB_MEM_PWR_STATE_SM", 17, 18, &umr_bitfield_default },
	 { "WBSCL_LB_MEM_PWR_STATE_BG", 19, 20, &umr_bitfield_default },
	 { "WBSCL_LB_MEM_PWR_STATE", 21, 22, &umr_bitfield_default },
	 { "WB_RAM_PW_SAVE_MODE", 23, 23, &umr_bitfield_default },
	 { "LB_MEM_PWR_STATE_SM", 24, 25, &umr_bitfield_default },
	 { "LB_MEM_PWR_STATE_BG", 26, 27, &umr_bitfield_default },
	 { "LB_MEM_PWR_STATE", 28, 29, &umr_bitfield_default },
	 { "LUT_MEM_PWR_STATE", 30, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmCNV1_CNV_MODE[] = {
	 { "CNV_FRAME_CAPTURE_RATE", 8, 9, &umr_bitfield_default },
	 { "CNV_WINDOW_CROP_EN", 12, 12, &umr_bitfield_default },
	 { "CNV_STEREO_TYPE", 13, 14, &umr_bitfield_default },
	 { "CNV_INTERLACED_MODE", 15, 15, &umr_bitfield_default },
	 { "CNV_EYE_SELECTION", 16, 17, &umr_bitfield_default },
	 { "CNV_STEREO_POLARITY", 18, 18, &umr_bitfield_default },
	 { "CNV_INTERLACED_FIELD_ORDER", 19, 19, &umr_bitfield_default },
	 { "CNV_STEREO_SPLIT", 20, 20, &umr_bitfield_default },
	 { "CNV_NEW_CONTENT", 24, 24, &umr_bitfield_default },
	 { "CNV_FRAME_CAPTURE_EN", 31, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmCNV1_CNV_WINDOW_START[] = {
	 { "CNV_WINDOW_START_X", 0, 11, &umr_bitfield_default },
	 { "CNV_WINDOW_START_Y", 16, 27, &umr_bitfield_default },
};
static struct umr_bitfield mmCNV1_CNV_WINDOW_SIZE[] = {
	 { "CNV_WINDOW_WIDTH", 0, 11, &umr_bitfield_default },
	 { "CNV_WINDOW_HEIGHT", 16, 27, &umr_bitfield_default },
};
static struct umr_bitfield mmCNV1_CNV_UPDATE[] = {
	 { "CNV_UPDATE_PENDING", 0, 0, &umr_bitfield_default },
	 { "CNV_UPDATE_TAKEN", 8, 8, &umr_bitfield_default },
	 { "CNV_UPDATE_LOCK", 16, 16, &umr_bitfield_default },
};
static struct umr_bitfield mmCNV1_CNV_SOURCE_SIZE[] = {
	 { "CNV_SOURCE_WIDTH", 0, 14, &umr_bitfield_default },
	 { "CNV_SOURCE_HEIGHT", 16, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmCNV1_CNV_CSC_CONTROL[] = {
	 { "CNV_CSC_BYPASS", 0, 0, &umr_bitfield_default },
};
static struct umr_bitfield mmCNV1_CNV_CSC_C11_C12[] = {
	 { "CNV_CSC_C11", 0, 12, &umr_bitfield_default },
	 { "CNV_CSC_C12", 16, 28, &umr_bitfield_default },
};
static struct umr_bitfield mmCNV1_CNV_CSC_C13_C14[] = {
	 { "CNV_CSC_C13", 0, 12, &umr_bitfield_default },
	 { "CNV_CSC_C14", 16, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmCNV1_CNV_CSC_C21_C22[] = {
	 { "CNV_CSC_C21", 0, 12, &umr_bitfield_default },
	 { "CNV_CSC_C22", 16, 28, &umr_bitfield_default },
};
static struct umr_bitfield mmCNV1_CNV_CSC_C23_C24[] = {
	 { "CNV_CSC_C23", 0, 12, &umr_bitfield_default },
	 { "CNV_CSC_C24", 16, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmCNV1_CNV_CSC_C31_C32[] = {
	 { "CNV_CSC_C31", 0, 12, &umr_bitfield_default },
	 { "CNV_CSC_C32", 16, 28, &umr_bitfield_default },
};
static struct umr_bitfield mmCNV1_CNV_CSC_C33_C34[] = {
	 { "CNV_CSC_C33", 0, 12, &umr_bitfield_default },
	 { "CNV_CSC_C34", 16, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmCNV1_CNV_CSC_ROUND_OFFSET_R[] = {
	 { "CNV_CSC_ROUND_OFFSET_R", 0, 15, &umr_bitfield_default },
};
static struct umr_bitfield mmCNV1_CNV_CSC_ROUND_OFFSET_G[] = {
	 { "CNV_CSC_ROUND_OFFSET_G", 0, 15, &umr_bitfield_default },
};
static struct umr_bitfield mmCNV1_CNV_CSC_ROUND_OFFSET_B[] = {
	 { "CNV_CSC_ROUND_OFFSET_B", 0, 15, &umr_bitfield_default },
};
static struct umr_bitfield mmCNV1_CNV_CSC_CLAMP_R[] = {
	 { "CNV_CSC_CLAMP_UPPER_R", 0, 15, &umr_bitfield_default },
	 { "CNV_CSC_CLAMP_LOWER_R", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmCNV1_CNV_CSC_CLAMP_G[] = {
	 { "CNV_CSC_CLAMP_UPPER_G", 0, 15, &umr_bitfield_default },
	 { "CNV_CSC_CLAMP_LOWER_G", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmCNV1_CNV_CSC_CLAMP_B[] = {
	 { "CNV_CSC_CLAMP_UPPER_B", 0, 15, &umr_bitfield_default },
	 { "CNV_CSC_CLAMP_LOWER_B", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmCNV1_CNV_TEST_CNTL[] = {
	 { "CNV_TEST_CRC_EN", 4, 4, &umr_bitfield_default },
	 { "CNV_TEST_CRC_CONT_EN", 8, 8, &umr_bitfield_default },
	 { "CNV_TEST_CRC_DE_ONLY", 16, 16, &umr_bitfield_default },
};
static struct umr_bitfield mmCNV1_CNV_TEST_CRC_RED[] = {
	 { "CNV_TEST_CRC_RED_MASK", 4, 15, &umr_bitfield_default },
	 { "CNV_TEST_CRC_SIG_RED", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmCNV1_CNV_TEST_CRC_GREEN[] = {
	 { "CNV_TEST_CRC_GREEN_MASK", 4, 15, &umr_bitfield_default },
	 { "CNV_TEST_CRC_SIG_GREEN", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmCNV1_CNV_TEST_CRC_BLUE[] = {
	 { "CNV_TEST_CRC_BLUE_MASK", 4, 15, &umr_bitfield_default },
	 { "CNV_TEST_CRC_SIG_BLUE", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmCNV1_CNV_INPUT_SELECT[] = {
	 { "CNV_INPUT_SRC_SELECT", 0, 1, &umr_bitfield_default },
	 { "CNV_INPUT_PIPE_SELECT", 2, 4, &umr_bitfield_default },
};
static struct umr_bitfield mmCNV1_WB_SOFT_RESET[] = {
	 { "WB_SOFT_RESET", 0, 0, &umr_bitfield_default },
};
static struct umr_bitfield mmCNV1_WB_WARM_UP_MODE_CTL1[] = {
	 { "WIDTH_WARMUP", 0, 14, &umr_bitfield_default },
	 { "HEIGHT_WARMUP", 16, 30, &umr_bitfield_default },
	 { "GMC_WARM_UP_ENABLE", 31, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmCNV1_WB_WARM_UP_MODE_CTL2[] = {
	 { "DATA_VALUE_WARMUP", 0, 7, &umr_bitfield_default },
	 { "MODE_WARMUP", 8, 8, &umr_bitfield_default },
};
static struct umr_bitfield mmWBSCL1_WBSCL_COEF_RAM_SELECT[] = {
	 { "WBSCL_COEF_RAM_TAP_PAIR_IDX", 0, 2, &umr_bitfield_default },
	 { "WBSCL_COEF_RAM_PHASE", 8, 11, &umr_bitfield_default },
	 { "WBSCL_COEF_RAM_FILTER_TYPE", 16, 17, &umr_bitfield_default },
};
static struct umr_bitfield mmWBSCL1_WBSCL_COEF_RAM_TAP_DATA[] = {
	 { "WBSCL_COEF_RAM_EVEN_TAP_COEF", 0, 13, &umr_bitfield_default },
	 { "WBSCL_COEF_RAM_EVEN_TAP_COEF_EN", 15, 15, &umr_bitfield_default },
	 { "WBSCL_COEF_RAM_ODD_TAP_COEF", 16, 29, &umr_bitfield_default },
	 { "WBSCL_COEF_RAM_ODD_TAP_COEF_EN", 31, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmWBSCL1_WBSCL_MODE[] = {
	 { "WBSCL_MODE", 0, 1, &umr_bitfield_default },
};
static struct umr_bitfield mmWBSCL1_WBSCL_TAP_CONTROL[] = {
	 { "WBSCL_V_NUM_OF_TAPS_Y_RGB", 0, 3, &umr_bitfield_default },
	 { "WBSCL_V_NUM_OF_TAPS_CBCR", 4, 7, &umr_bitfield_default },
	 { "WBSCL_H_NUM_OF_TAPS_Y_RGB", 8, 11, &umr_bitfield_default },
	 { "WBSCL_H_NUM_OF_TAPS_CBCR", 12, 15, &umr_bitfield_default },
};
static struct umr_bitfield mmWBSCL1_WBSCL_DEST_SIZE[] = {
	 { "WBSCL_DEST_HEIGHT", 0, 14, &umr_bitfield_default },
	 { "WBSCL_DEST_WIDTH", 16, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmWBSCL1_WBSCL_HORZ_FILTER_SCALE_RATIO[] = {
	 { "WBSCL_H_SCALE_RATIO", 0, 26, &umr_bitfield_default },
};
static struct umr_bitfield mmWBSCL1_WBSCL_HORZ_FILTER_INIT_Y_RGB[] = {
	 { "WBSCL_H_INIT_FRAC_Y_RGB", 0, 23, &umr_bitfield_default },
	 { "WBSCL_H_INIT_INT_Y_RGB", 24, 28, &umr_bitfield_default },
};
static struct umr_bitfield mmWBSCL1_WBSCL_HORZ_FILTER_INIT_CBCR[] = {
	 { "WBSCL_H_INIT_FRAC_CBCR", 0, 23, &umr_bitfield_default },
	 { "WBSCL_H_INIT_INT_CBCR", 24, 28, &umr_bitfield_default },
};
static struct umr_bitfield mmWBSCL1_WBSCL_VERT_FILTER_SCALE_RATIO[] = {
	 { "WBSCL_V_SCALE_RATIO", 0, 26, &umr_bitfield_default },
};
static struct umr_bitfield mmWBSCL1_WBSCL_VERT_FILTER_INIT_Y_RGB[] = {
	 { "WBSCL_V_INIT_FRAC_Y_RGB", 0, 23, &umr_bitfield_default },
	 { "WBSCL_V_INIT_INT_Y_RGB", 24, 28, &umr_bitfield_default },
};
static struct umr_bitfield mmWBSCL1_WBSCL_VERT_FILTER_INIT_CBCR[] = {
	 { "WBSCL_V_INIT_FRAC_CBCR", 0, 23, &umr_bitfield_default },
	 { "WBSCL_V_INIT_INT_CBCR", 24, 28, &umr_bitfield_default },
};
static struct umr_bitfield mmWBSCL1_WBSCL_ROUND_OFFSET[] = {
	 { "WBSCL_ROUND_OFFSET_Y_RGB", 0, 15, &umr_bitfield_default },
	 { "WBSCL_ROUND_OFFSET_CBCR", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmWBSCL1_WBSCL_CLAMP[] = {
	 { "WBSCL_CLAMP_UPPER_Y_RGB", 0, 7, &umr_bitfield_default },
	 { "WBSCL_CLAMP_LOWER_Y_RGB", 8, 15, &umr_bitfield_default },
	 { "WBSCL_CLAMP_UPPER_CBCR", 16, 23, &umr_bitfield_default },
	 { "WBSCL_CLAMP_LOWER_CBCR", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmWBSCL1_WBSCL_OVERFLOW_STATUS[] = {
	 { "WBSCL_DATA_OVERFLOW_FLAG", 0, 0, &umr_bitfield_default },
	 { "WBSCL_DATA_OVERFLOW_ACK", 8, 8, &umr_bitfield_default },
	 { "WBSCL_DATA_OVERFLOW_MASK", 12, 12, &umr_bitfield_default },
	 { "WBSCL_DATA_OVERFLOW_INT_STATUS", 16, 16, &umr_bitfield_default },
	 { "WBSCL_DATA_OVERFLOW_INT_TYPE", 20, 20, &umr_bitfield_default },
};
static struct umr_bitfield mmWBSCL1_WBSCL_COEF_RAM_CONFLICT_STATUS[] = {
	 { "WBSCL_HOST_CONFLICT_FLAG", 0, 0, &umr_bitfield_default },
	 { "WBSCL_HOST_CONFLICT_ACK", 8, 8, &umr_bitfield_default },
	 { "WBSCL_HOST_CONFLICT_MASK", 12, 12, &umr_bitfield_default },
	 { "WBSCL_HOST_CONFLICT_INT_STATUS", 16, 16, &umr_bitfield_default },
	 { "WBSCL_HOST_CONFLICT_INT_TYPE", 20, 20, &umr_bitfield_default },
};
static struct umr_bitfield mmWBSCL1_WBSCL_OUTSIDE_PIX_STRATEGY[] = {
	 { "WBSCL_OUTSIDE_PIX_STRATEGY", 0, 0, &umr_bitfield_default },
	 { "WBSCL_BLACK_COLOR_B_CB", 8, 15, &umr_bitfield_default },
	 { "WBSCL_BLACK_COLOR_G_Y", 16, 23, &umr_bitfield_default },
	 { "WBSCL_BLACK_COLOR_R_CR", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmWBSCL1_WBSCL_TEST_CNTL[] = {
	 { "WBSCL_TEST_CRC_EN", 4, 4, &umr_bitfield_default },
	 { "WBSCL_TEST_CRC_CONT_EN", 8, 8, &umr_bitfield_default },
	 { "WBSCL_TEST_CRC_DE_ONLY", 16, 16, &umr_bitfield_default },
};
static struct umr_bitfield mmWBSCL1_WBSCL_TEST_CRC_RED[] = {
	 { "WBSCL_TEST_CRC_RED_MASK", 8, 15, &umr_bitfield_default },
	 { "WBSCL_TEST_CRC_SIG_RED", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmWBSCL1_WBSCL_TEST_CRC_GREEN[] = {
	 { "WBSCL_TEST_CRC_GREEN_MASK", 0, 15, &umr_bitfield_default },
	 { "WBSCL_TEST_CRC_SIG_GREEN", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmWBSCL1_WBSCL_TEST_CRC_BLUE[] = {
	 { "WBSCL_TEST_CRC_BLUE_MASK", 8, 15, &umr_bitfield_default },
	 { "WBSCL_TEST_CRC_SIG_BLUE", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmWBSCL1_WBSCL_BACKPRESSURE_CNT_EN[] = {
	 { "WBSCL_BACKPRESSURE_CNT_EN", 0, 0, &umr_bitfield_default },
};
static struct umr_bitfield mmWBSCL1_WB_MCIF_BACKPRESSURE_CNT[] = {
	 { "WB_MCIF_Y_MAX_BACKPRESSURE", 0, 15, &umr_bitfield_default },
	 { "WB_MCIF_C_MAX_BACKPRESSURE", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmWBSCL1_WBSCL_RAM_SHUTDOWN[] = {
	 { "WBSCL_RAM_SHUTDOWN_SEL", 0, 1, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_PERFMON4_PERFCOUNTER_CNTL[] = {
	 { "PERFCOUNTER_EVENT_SEL", 0, 8, &umr_bitfield_default },
	 { "PERFCOUNTER_CVALUE_SEL", 9, 11, &umr_bitfield_default },
	 { "PERFCOUNTER_INC_MODE", 12, 14, &umr_bitfield_default },
	 { "PERFCOUNTER_HW_CNTL_SEL", 15, 15, &umr_bitfield_default },
	 { "PERFCOUNTER_RUNEN_MODE", 16, 16, &umr_bitfield_default },
	 { "PERFCOUNTER_CNTOFF_START_DIS", 22, 22, &umr_bitfield_default },
	 { "PERFCOUNTER_RESTART_EN", 23, 23, &umr_bitfield_default },
	 { "PERFCOUNTER_INT_EN", 24, 24, &umr_bitfield_default },
	 { "PERFCOUNTER_OFF_MASK", 25, 25, &umr_bitfield_default },
	 { "PERFCOUNTER_ACTIVE", 26, 26, &umr_bitfield_default },
	 { "PERFCOUNTER_CNTL_SEL", 29, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_PERFMON4_PERFCOUNTER_CNTL2[] = {
	 { "PERFCOUNTER_COUNTED_VALUE_TYPE", 0, 1, &umr_bitfield_default },
	 { "PERFCOUNTER_HW_STOP1_SEL", 2, 2, &umr_bitfield_default },
	 { "PERFCOUNTER_HW_STOP2_SEL", 3, 3, &umr_bitfield_default },
	 { "PERFCOUNTER_CNTOFF_SEL", 8, 13, &umr_bitfield_default },
	 { "PERFCOUNTER_CNTL2_SEL", 29, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_PERFMON4_PERFCOUNTER_STATE[] = {
	 { "PERFCOUNTER_CNT0_STATE", 0, 1, &umr_bitfield_default },
	 { "PERFCOUNTER_STATE_SEL0", 2, 2, &umr_bitfield_default },
	 { "PERFCOUNTER_CNT1_STATE", 4, 5, &umr_bitfield_default },
	 { "PERFCOUNTER_STATE_SEL1", 6, 6, &umr_bitfield_default },
	 { "PERFCOUNTER_CNT2_STATE", 8, 9, &umr_bitfield_default },
	 { "PERFCOUNTER_STATE_SEL2", 10, 10, &umr_bitfield_default },
	 { "PERFCOUNTER_CNT3_STATE", 12, 13, &umr_bitfield_default },
	 { "PERFCOUNTER_STATE_SEL3", 14, 14, &umr_bitfield_default },
	 { "PERFCOUNTER_CNT4_STATE", 16, 17, &umr_bitfield_default },
	 { "PERFCOUNTER_STATE_SEL4", 18, 18, &umr_bitfield_default },
	 { "PERFCOUNTER_CNT5_STATE", 20, 21, &umr_bitfield_default },
	 { "PERFCOUNTER_STATE_SEL5", 22, 22, &umr_bitfield_default },
	 { "PERFCOUNTER_CNT6_STATE", 24, 25, &umr_bitfield_default },
	 { "PERFCOUNTER_STATE_SEL6", 26, 26, &umr_bitfield_default },
	 { "PERFCOUNTER_CNT7_STATE", 28, 29, &umr_bitfield_default },
	 { "PERFCOUNTER_STATE_SEL7", 30, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_PERFMON4_PERFMON_CNTL[] = {
	 { "PERFMON_STATE", 0, 1, &umr_bitfield_default },
	 { "PERFMON_RPT_COUNT", 8, 27, &umr_bitfield_default },
	 { "PERFMON_CNTOFF_AND_OR", 28, 28, &umr_bitfield_default },
	 { "PERFMON_CNTOFF_INT_EN", 29, 29, &umr_bitfield_default },
	 { "PERFMON_CNTOFF_INT_STATUS", 30, 30, &umr_bitfield_default },
	 { "PERFMON_CNTOFF_INT_ACK", 31, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_PERFMON4_PERFMON_CNTL2[] = {
	 { "PERFMON_CNTOFF_INT_TYPE", 0, 0, &umr_bitfield_default },
	 { "PERFMON_CLK_ENABLE", 1, 1, &umr_bitfield_default },
	 { "PERFMON_RUN_ENABLE_START_SEL", 2, 9, &umr_bitfield_default },
	 { "PERFMON_RUN_ENABLE_STOP_SEL", 10, 17, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_PERFMON4_PERFMON_CVALUE_INT_MISC[] = {
	 { "PERFCOUNTER_INT0_STATUS", 0, 0, &umr_bitfield_default },
	 { "PERFCOUNTER_INT1_STATUS", 1, 1, &umr_bitfield_default },
	 { "PERFCOUNTER_INT2_STATUS", 2, 2, &umr_bitfield_default },
	 { "PERFCOUNTER_INT3_STATUS", 3, 3, &umr_bitfield_default },
	 { "PERFCOUNTER_INT4_STATUS", 4, 4, &umr_bitfield_default },
	 { "PERFCOUNTER_INT5_STATUS", 5, 5, &umr_bitfield_default },
	 { "PERFCOUNTER_INT6_STATUS", 6, 6, &umr_bitfield_default },
	 { "PERFCOUNTER_INT7_STATUS", 7, 7, &umr_bitfield_default },
	 { "PERFCOUNTER_INT0_ACK", 8, 8, &umr_bitfield_default },
	 { "PERFCOUNTER_INT1_ACK", 9, 9, &umr_bitfield_default },
	 { "PERFCOUNTER_INT2_ACK", 10, 10, &umr_bitfield_default },
	 { "PERFCOUNTER_INT3_ACK", 11, 11, &umr_bitfield_default },
	 { "PERFCOUNTER_INT4_ACK", 12, 12, &umr_bitfield_default },
	 { "PERFCOUNTER_INT5_ACK", 13, 13, &umr_bitfield_default },
	 { "PERFCOUNTER_INT6_ACK", 14, 14, &umr_bitfield_default },
	 { "PERFCOUNTER_INT7_ACK", 15, 15, &umr_bitfield_default },
	 { "PERFMON_CVALUE_HI", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_PERFMON4_PERFMON_CVALUE_LOW[] = {
	 { "PERFMON_CVALUE_LOW", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_PERFMON4_PERFMON_HI[] = {
	 { "PERFMON_HI", 0, 15, &umr_bitfield_default },
	 { "PERFMON_READ_SEL", 29, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_PERFMON4_PERFMON_LOW[] = {
	 { "PERFMON_LOW", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL[] = {
	 { "MCIF_WB_BUFMGR_ENABLE", 0, 0, &umr_bitfield_default },
	 { "MCIF_WB_BUF_DUALSIZE_REQ", 1, 1, &umr_bitfield_default },
	 { "MCIF_WB_BUFMGR_SW_INT_EN", 4, 4, &umr_bitfield_default },
	 { "MCIF_WB_BUFMGR_SW_INT_ACK", 5, 5, &umr_bitfield_default },
	 { "MCIF_WB_BUFMGR_SW_SLICE_INT_EN", 6, 6, &umr_bitfield_default },
	 { "MCIF_WB_BUFMGR_SW_OVERRUN_INT_EN", 7, 7, &umr_bitfield_default },
	 { "MCIF_WB_BUFMGR_SW_LOCK", 8, 11, &umr_bitfield_default },
	 { "MCIF_WB_P_VMID", 16, 19, &umr_bitfield_default },
	 { "MCIF_WB_BUF_ADDR_FENCE_EN", 24, 24, &umr_bitfield_default },
};
static struct umr_bitfield mmMCIF_WB0_MCIF_WB_BUFMGR_CUR_LINE_R[] = {
	 { "MCIF_WB_BUFMGR_CUR_LINE_R", 0, 12, &umr_bitfield_default },
};
static struct umr_bitfield mmMCIF_WB0_MCIF_WB_BUFMGR_STATUS[] = {
	 { "MCIF_WB_BUFMGR_VCE_INT_STATUS", 0, 0, &umr_bitfield_default },
	 { "MCIF_WB_BUFMGR_SW_INT_STATUS", 1, 1, &umr_bitfield_default },
	 { "MCIF_WB_BUFMGR_SW_OVERRUN_INT_STATUS", 2, 2, &umr_bitfield_default },
	 { "MCIF_WB_BUFMGR_CUR_BUF", 4, 6, &umr_bitfield_default },
	 { "MCIF_WB_BUF_DUALSIZE_STATUS", 7, 7, &umr_bitfield_default },
	 { "MCIF_WB_BUFMGR_BUFTAG", 8, 11, &umr_bitfield_default },
	 { "MCIF_WB_BUFMGR_CUR_LINE_L", 12, 24, &umr_bitfield_default },
	 { "MCIF_WB_BUFMGR_NEXT_BUF", 28, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmMCIF_WB0_MCIF_WB_BUF_PITCH[] = {
	 { "MCIF_WB_BUF_LUMA_PITCH", 8, 15, &umr_bitfield_default },
	 { "MCIF_WB_BUF_CHROMA_PITCH", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMCIF_WB0_MCIF_WB_BUF_1_STATUS[] = {
	 { "MCIF_WB_BUF_1_ACTIVE", 0, 0, &umr_bitfield_default },
	 { "MCIF_WB_BUF_1_SW_LOCKED", 1, 1, &umr_bitfield_default },
	 { "MCIF_WB_BUF_1_VCE_LOCKED", 2, 2, &umr_bitfield_default },
	 { "MCIF_WB_BUF_1_OVERFLOW", 3, 3, &umr_bitfield_default },
	 { "MCIF_WB_BUF_1_DISABLE", 4, 4, &umr_bitfield_default },
	 { "MCIF_WB_BUF_1_MODE", 5, 7, &umr_bitfield_default },
	 { "MCIF_WB_BUF_1_BUFTAG", 8, 11, &umr_bitfield_default },
	 { "MCIF_WB_BUF_1_NXT_BUF", 12, 14, &umr_bitfield_default },
	 { "MCIF_WB_BUF_1_FIELD", 15, 15, &umr_bitfield_default },
	 { "MCIF_WB_BUF_1_CUR_LINE_L", 16, 28, &umr_bitfield_default },
	 { "MCIF_WB_BUF_1_LONG_LINE_ERROR", 29, 29, &umr_bitfield_default },
	 { "MCIF_WB_BUF_1_SHORT_LINE_ERROR", 30, 30, &umr_bitfield_default },
	 { "MCIF_WB_BUF_1_FRAME_LENGTH_ERROR", 31, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMCIF_WB0_MCIF_WB_BUF_1_STATUS2[] = {
	 { "MCIF_WB_BUF_1_CUR_LINE_R", 0, 12, &umr_bitfield_default },
	 { "MCIF_WB_BUF_1_NEW_CONTENT", 13, 13, &umr_bitfield_default },
	 { "MCIF_WB_BUF_1_COLOR_DEPTH", 14, 14, &umr_bitfield_default },
	 { "MCIF_WB_BUF_1_Y_OVERRUN", 17, 17, &umr_bitfield_default },
	 { "MCIF_WB_BUF_1_C_OVERRUN", 18, 18, &umr_bitfield_default },
};
static struct umr_bitfield mmMCIF_WB0_MCIF_WB_BUF_2_STATUS[] = {
	 { "MCIF_WB_BUF_2_ACTIVE", 0, 0, &umr_bitfield_default },
	 { "MCIF_WB_BUF_2_SW_LOCKED", 1, 1, &umr_bitfield_default },
	 { "MCIF_WB_BUF_2_VCE_LOCKED", 2, 2, &umr_bitfield_default },
	 { "MCIF_WB_BUF_2_OVERFLOW", 3, 3, &umr_bitfield_default },
	 { "MCIF_WB_BUF_2_DISABLE", 4, 4, &umr_bitfield_default },
	 { "MCIF_WB_BUF_2_MODE", 5, 7, &umr_bitfield_default },
	 { "MCIF_WB_BUF_2_BUFTAG", 8, 11, &umr_bitfield_default },
	 { "MCIF_WB_BUF_2_NXT_BUF", 12, 14, &umr_bitfield_default },
	 { "MCIF_WB_BUF_2_FIELD", 15, 15, &umr_bitfield_default },
	 { "MCIF_WB_BUF_2_CUR_LINE_L", 16, 28, &umr_bitfield_default },
	 { "MCIF_WB_BUF_2_LONG_LINE_ERROR", 29, 29, &umr_bitfield_default },
	 { "MCIF_WB_BUF_2_SHORT_LINE_ERROR", 30, 30, &umr_bitfield_default },
	 { "MCIF_WB_BUF_2_FRAME_LENGTH_ERROR", 31, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMCIF_WB0_MCIF_WB_BUF_2_STATUS2[] = {
	 { "MCIF_WB_BUF_2_CUR_LINE_R", 0, 12, &umr_bitfield_default },
	 { "MCIF_WB_BUF_2_NEW_CONTENT", 13, 13, &umr_bitfield_default },
	 { "MCIF_WB_BUF_2_COLOR_DEPTH", 14, 14, &umr_bitfield_default },
	 { "MCIF_WB_BUF_2_Y_OVERRUN", 17, 17, &umr_bitfield_default },
	 { "MCIF_WB_BUF_2_C_OVERRUN", 18, 18, &umr_bitfield_default },
};
static struct umr_bitfield mmMCIF_WB0_MCIF_WB_BUF_3_STATUS[] = {
	 { "MCIF_WB_BUF_3_ACTIVE", 0, 0, &umr_bitfield_default },
	 { "MCIF_WB_BUF_3_SW_LOCKED", 1, 1, &umr_bitfield_default },
	 { "MCIF_WB_BUF_3_VCE_LOCKED", 2, 2, &umr_bitfield_default },
	 { "MCIF_WB_BUF_3_OVERFLOW", 3, 3, &umr_bitfield_default },
	 { "MCIF_WB_BUF_3_DISABLE", 4, 4, &umr_bitfield_default },
	 { "MCIF_WB_BUF_3_MODE", 5, 7, &umr_bitfield_default },
	 { "MCIF_WB_BUF_3_BUFTAG", 8, 11, &umr_bitfield_default },
	 { "MCIF_WB_BUF_3_NXT_BUF", 12, 14, &umr_bitfield_default },
	 { "MCIF_WB_BUF_3_FIELD", 15, 15, &umr_bitfield_default },
	 { "MCIF_WB_BUF_3_CUR_LINE_L", 16, 28, &umr_bitfield_default },
	 { "MCIF_WB_BUF_3_LONG_LINE_ERROR", 29, 29, &umr_bitfield_default },
	 { "MCIF_WB_BUF_3_SHORT_LINE_ERROR", 30, 30, &umr_bitfield_default },
	 { "MCIF_WB_BUF_3_FRAME_LENGTH_ERROR", 31, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMCIF_WB0_MCIF_WB_BUF_3_STATUS2[] = {
	 { "MCIF_WB_BUF_3_CUR_LINE_R", 0, 12, &umr_bitfield_default },
	 { "MCIF_WB_BUF_3_NEW_CONTENT", 13, 13, &umr_bitfield_default },
	 { "MCIF_WB_BUF_3_COLOR_DEPTH", 14, 14, &umr_bitfield_default },
	 { "MCIF_WB_BUF_3_Y_OVERRUN", 17, 17, &umr_bitfield_default },
	 { "MCIF_WB_BUF_3_C_OVERRUN", 18, 18, &umr_bitfield_default },
};
static struct umr_bitfield mmMCIF_WB0_MCIF_WB_BUF_4_STATUS[] = {
	 { "MCIF_WB_BUF_4_ACTIVE", 0, 0, &umr_bitfield_default },
	 { "MCIF_WB_BUF_4_SW_LOCKED", 1, 1, &umr_bitfield_default },
	 { "MCIF_WB_BUF_4_VCE_LOCKED", 2, 2, &umr_bitfield_default },
	 { "MCIF_WB_BUF_4_OVERFLOW", 3, 3, &umr_bitfield_default },
	 { "MCIF_WB_BUF_4_DISABLE", 4, 4, &umr_bitfield_default },
	 { "MCIF_WB_BUF_4_MODE", 5, 7, &umr_bitfield_default },
	 { "MCIF_WB_BUF_4_BUFTAG", 8, 11, &umr_bitfield_default },
	 { "MCIF_WB_BUF_4_NXT_BUF", 12, 14, &umr_bitfield_default },
	 { "MCIF_WB_BUF_4_FIELD", 15, 15, &umr_bitfield_default },
	 { "MCIF_WB_BUF_4_CUR_LINE_L", 16, 28, &umr_bitfield_default },
	 { "MCIF_WB_BUF_4_LONG_LINE_ERROR", 29, 29, &umr_bitfield_default },
	 { "MCIF_WB_BUF_4_SHORT_LINE_ERROR", 30, 30, &umr_bitfield_default },
	 { "MCIF_WB_BUF_4_FRAME_LENGTH_ERROR", 31, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMCIF_WB0_MCIF_WB_BUF_4_STATUS2[] = {
	 { "MCIF_WB_BUF_4_CUR_LINE_R", 0, 12, &umr_bitfield_default },
	 { "MCIF_WB_BUF_4_NEW_CONTENT", 13, 13, &umr_bitfield_default },
	 { "MCIF_WB_BUF_4_COLOR_DEPTH", 14, 14, &umr_bitfield_default },
	 { "MCIF_WB_BUF_4_Y_OVERRUN", 17, 17, &umr_bitfield_default },
	 { "MCIF_WB_BUF_4_C_OVERRUN", 18, 18, &umr_bitfield_default },
};
static struct umr_bitfield mmMCIF_WB0_MCIF_WB_ARBITRATION_CONTROL[] = {
	 { "MCIF_WB_CLIENT_ARBITRATION_SLICE", 0, 1, &umr_bitfield_default },
	 { "MCIF_WB_TIME_PER_PIXEL", 22, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMCIF_WB0_MCIF_WB_SCLK_CHANGE[] = {
	 { "WM_CHANGE_ACK_FORCE_ON", 0, 0, &umr_bitfield_default },
	 { "MCIF_WB_CLI_WATERMARK_MASK", 1, 3, &umr_bitfield_default },
};
static struct umr_bitfield mmMCIF_WB0_MCIF_WB_BUF_1_ADDR_Y[] = {
	 { "MCIF_WB_BUF_1_ADDR_Y", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMCIF_WB0_MCIF_WB_BUF_1_ADDR_Y_OFFSET[] = {
	 { "MCIF_WB_BUF_1_ADDR_Y_OFFSET", 0, 17, &umr_bitfield_default },
};
static struct umr_bitfield mmMCIF_WB0_MCIF_WB_BUF_1_ADDR_C[] = {
	 { "MCIF_WB_BUF_1_ADDR_C", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMCIF_WB0_MCIF_WB_BUF_1_ADDR_C_OFFSET[] = {
	 { "MCIF_WB_BUF_1_ADDR_C_OFFSET", 0, 17, &umr_bitfield_default },
};
static struct umr_bitfield mmMCIF_WB0_MCIF_WB_BUF_2_ADDR_Y[] = {
	 { "MCIF_WB_BUF_2_ADDR_Y", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMCIF_WB0_MCIF_WB_BUF_2_ADDR_Y_OFFSET[] = {
	 { "MCIF_WB_BUF_2_ADDR_Y_OFFSET", 0, 17, &umr_bitfield_default },
};
static struct umr_bitfield mmMCIF_WB0_MCIF_WB_BUF_2_ADDR_C[] = {
	 { "MCIF_WB_BUF_2_ADDR_C", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMCIF_WB0_MCIF_WB_BUF_2_ADDR_C_OFFSET[] = {
	 { "MCIF_WB_BUF_2_ADDR_C_OFFSET", 0, 17, &umr_bitfield_default },
};
static struct umr_bitfield mmMCIF_WB0_MCIF_WB_BUF_3_ADDR_Y[] = {
	 { "MCIF_WB_BUF_3_ADDR_Y", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMCIF_WB0_MCIF_WB_BUF_3_ADDR_Y_OFFSET[] = {
	 { "MCIF_WB_BUF_3_ADDR_Y_OFFSET", 0, 17, &umr_bitfield_default },
};
static struct umr_bitfield mmMCIF_WB0_MCIF_WB_BUF_3_ADDR_C[] = {
	 { "MCIF_WB_BUF_3_ADDR_C", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMCIF_WB0_MCIF_WB_BUF_3_ADDR_C_OFFSET[] = {
	 { "MCIF_WB_BUF_3_ADDR_C_OFFSET", 0, 17, &umr_bitfield_default },
};
static struct umr_bitfield mmMCIF_WB0_MCIF_WB_BUF_4_ADDR_Y[] = {
	 { "MCIF_WB_BUF_4_ADDR_Y", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMCIF_WB0_MCIF_WB_BUF_4_ADDR_Y_OFFSET[] = {
	 { "MCIF_WB_BUF_4_ADDR_Y_OFFSET", 0, 17, &umr_bitfield_default },
};
static struct umr_bitfield mmMCIF_WB0_MCIF_WB_BUF_4_ADDR_C[] = {
	 { "MCIF_WB_BUF_4_ADDR_C", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMCIF_WB0_MCIF_WB_BUF_4_ADDR_C_OFFSET[] = {
	 { "MCIF_WB_BUF_4_ADDR_C_OFFSET", 0, 17, &umr_bitfield_default },
};
static struct umr_bitfield mmMCIF_WB0_MCIF_WB_BUFMGR_VCE_CONTROL[] = {
	 { "MCIF_WB_BUFMGR_VCE_LOCK_IGNORE", 0, 0, &umr_bitfield_default },
	 { "MCIF_WB_BUFMGR_VCE_INT_EN", 4, 4, &umr_bitfield_default },
	 { "MCIF_WB_BUFMGR_VCE_INT_ACK", 5, 5, &umr_bitfield_default },
	 { "MCIF_WB_BUFMGR_VCE_SLICE_INT_EN", 6, 6, &umr_bitfield_default },
	 { "MCIF_WB_BUFMGR_VCE_LOCK", 8, 11, &umr_bitfield_default },
	 { "MCIF_WB_BUFMGR_SLICE_SIZE", 16, 28, &umr_bitfield_default },
};
static struct umr_bitfield mmMCIF_WB0_MCIF_WB_NB_PSTATE_LATENCY_WATERMARK[] = {
	 { "NB_PSTATE_CHANGE_REFRESH_WATERMARK", 0, 16, &umr_bitfield_default },
};
static struct umr_bitfield mmMCIF_WB0_MCIF_WB_NB_PSTATE_CONTROL[] = {
	 { "NB_PSTATE_CHANGE_URGENT_DURING_REQUEST", 0, 0, &umr_bitfield_default },
	 { "NB_PSTATE_CHANGE_FORCE_ON", 1, 1, &umr_bitfield_default },
	 { "NB_PSTATE_ALLOW_FOR_URGENT", 2, 2, &umr_bitfield_default },
	 { "NB_PSTATE_CHANGE_WATERMARK_MASK", 4, 6, &umr_bitfield_default },
};
static struct umr_bitfield mmMCIF_WB0_MCIF_WB_WATERMARK[] = {
	 { "MCIF_WB_CLI_WATERMARK", 0, 15, &umr_bitfield_default },
};
static struct umr_bitfield mmMCIF_WB0_MCIF_WB_CLOCK_GATER_CONTROL[] = {
	 { "MCIF_WB_CLI_CLOCK_GATER_OVERRIDE", 0, 0, &umr_bitfield_default },
};
static struct umr_bitfield mmMCIF_WB0_MCIF_WB_WARM_UP_CNTL[] = {
	 { "MCIF_WB_PITCH_SIZE_WARMUP", 8, 15, &umr_bitfield_default },
};
static struct umr_bitfield mmMCIF_WB0_MCIF_WB_SELF_REFRESH_CONTROL[] = {
	 { "DIS_REFRESH_UNDER_NBPREQ", 0, 0, &umr_bitfield_default },
	 { "PERFRAME_SELF_REFRESH", 1, 1, &umr_bitfield_default },
};
static struct umr_bitfield mmMCIF_WB0_MULTI_LEVEL_QOS_CTRL[] = {
	 { "MAX_SCALED_TIME_TO_URGENT", 0, 21, &umr_bitfield_default },
};
static struct umr_bitfield mmMCIF_WB0_MCIF_WB_BUF_LUMA_SIZE[] = {
	 { "MCIF_WB_BUF_LUMA_SIZE", 0, 19, &umr_bitfield_default },
};
static struct umr_bitfield mmMCIF_WB0_MCIF_WB_BUF_CHROMA_SIZE[] = {
	 { "MCIF_WB_BUF_CHROMA_SIZE", 0, 19, &umr_bitfield_default },
};
static struct umr_bitfield mmMCIF_WB1_MCIF_WB_BUFMGR_SW_CONTROL[] = {
	 { "MCIF_WB_BUFMGR_ENABLE", 0, 0, &umr_bitfield_default },
	 { "MCIF_WB_BUF_DUALSIZE_REQ", 1, 1, &umr_bitfield_default },
	 { "MCIF_WB_BUFMGR_SW_INT_EN", 4, 4, &umr_bitfield_default },
	 { "MCIF_WB_BUFMGR_SW_INT_ACK", 5, 5, &umr_bitfield_default },
	 { "MCIF_WB_BUFMGR_SW_SLICE_INT_EN", 6, 6, &umr_bitfield_default },
	 { "MCIF_WB_BUFMGR_SW_OVERRUN_INT_EN", 7, 7, &umr_bitfield_default },
	 { "MCIF_WB_BUFMGR_SW_LOCK", 8, 11, &umr_bitfield_default },
	 { "MCIF_WB_P_VMID", 16, 19, &umr_bitfield_default },
	 { "MCIF_WB_BUF_ADDR_FENCE_EN", 24, 24, &umr_bitfield_default },
};
static struct umr_bitfield mmMCIF_WB1_MCIF_WB_BUFMGR_CUR_LINE_R[] = {
	 { "MCIF_WB_BUFMGR_CUR_LINE_R", 0, 12, &umr_bitfield_default },
};
static struct umr_bitfield mmMCIF_WB1_MCIF_WB_BUFMGR_STATUS[] = {
	 { "MCIF_WB_BUFMGR_VCE_INT_STATUS", 0, 0, &umr_bitfield_default },
	 { "MCIF_WB_BUFMGR_SW_INT_STATUS", 1, 1, &umr_bitfield_default },
	 { "MCIF_WB_BUFMGR_SW_OVERRUN_INT_STATUS", 2, 2, &umr_bitfield_default },
	 { "MCIF_WB_BUFMGR_CUR_BUF", 4, 6, &umr_bitfield_default },
	 { "MCIF_WB_BUF_DUALSIZE_STATUS", 7, 7, &umr_bitfield_default },
	 { "MCIF_WB_BUFMGR_BUFTAG", 8, 11, &umr_bitfield_default },
	 { "MCIF_WB_BUFMGR_CUR_LINE_L", 12, 24, &umr_bitfield_default },
	 { "MCIF_WB_BUFMGR_NEXT_BUF", 28, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmMCIF_WB1_MCIF_WB_BUF_PITCH[] = {
	 { "MCIF_WB_BUF_LUMA_PITCH", 8, 15, &umr_bitfield_default },
	 { "MCIF_WB_BUF_CHROMA_PITCH", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMCIF_WB1_MCIF_WB_BUF_1_STATUS[] = {
	 { "MCIF_WB_BUF_1_ACTIVE", 0, 0, &umr_bitfield_default },
	 { "MCIF_WB_BUF_1_SW_LOCKED", 1, 1, &umr_bitfield_default },
	 { "MCIF_WB_BUF_1_VCE_LOCKED", 2, 2, &umr_bitfield_default },
	 { "MCIF_WB_BUF_1_OVERFLOW", 3, 3, &umr_bitfield_default },
	 { "MCIF_WB_BUF_1_DISABLE", 4, 4, &umr_bitfield_default },
	 { "MCIF_WB_BUF_1_MODE", 5, 7, &umr_bitfield_default },
	 { "MCIF_WB_BUF_1_BUFTAG", 8, 11, &umr_bitfield_default },
	 { "MCIF_WB_BUF_1_NXT_BUF", 12, 14, &umr_bitfield_default },
	 { "MCIF_WB_BUF_1_FIELD", 15, 15, &umr_bitfield_default },
	 { "MCIF_WB_BUF_1_CUR_LINE_L", 16, 28, &umr_bitfield_default },
	 { "MCIF_WB_BUF_1_LONG_LINE_ERROR", 29, 29, &umr_bitfield_default },
	 { "MCIF_WB_BUF_1_SHORT_LINE_ERROR", 30, 30, &umr_bitfield_default },
	 { "MCIF_WB_BUF_1_FRAME_LENGTH_ERROR", 31, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMCIF_WB1_MCIF_WB_BUF_1_STATUS2[] = {
	 { "MCIF_WB_BUF_1_CUR_LINE_R", 0, 12, &umr_bitfield_default },
	 { "MCIF_WB_BUF_1_NEW_CONTENT", 13, 13, &umr_bitfield_default },
	 { "MCIF_WB_BUF_1_COLOR_DEPTH", 14, 14, &umr_bitfield_default },
	 { "MCIF_WB_BUF_1_Y_OVERRUN", 17, 17, &umr_bitfield_default },
	 { "MCIF_WB_BUF_1_C_OVERRUN", 18, 18, &umr_bitfield_default },
};
static struct umr_bitfield mmMCIF_WB1_MCIF_WB_BUF_2_STATUS[] = {
	 { "MCIF_WB_BUF_2_ACTIVE", 0, 0, &umr_bitfield_default },
	 { "MCIF_WB_BUF_2_SW_LOCKED", 1, 1, &umr_bitfield_default },
	 { "MCIF_WB_BUF_2_VCE_LOCKED", 2, 2, &umr_bitfield_default },
	 { "MCIF_WB_BUF_2_OVERFLOW", 3, 3, &umr_bitfield_default },
	 { "MCIF_WB_BUF_2_DISABLE", 4, 4, &umr_bitfield_default },
	 { "MCIF_WB_BUF_2_MODE", 5, 7, &umr_bitfield_default },
	 { "MCIF_WB_BUF_2_BUFTAG", 8, 11, &umr_bitfield_default },
	 { "MCIF_WB_BUF_2_NXT_BUF", 12, 14, &umr_bitfield_default },
	 { "MCIF_WB_BUF_2_FIELD", 15, 15, &umr_bitfield_default },
	 { "MCIF_WB_BUF_2_CUR_LINE_L", 16, 28, &umr_bitfield_default },
	 { "MCIF_WB_BUF_2_LONG_LINE_ERROR", 29, 29, &umr_bitfield_default },
	 { "MCIF_WB_BUF_2_SHORT_LINE_ERROR", 30, 30, &umr_bitfield_default },
	 { "MCIF_WB_BUF_2_FRAME_LENGTH_ERROR", 31, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMCIF_WB1_MCIF_WB_BUF_2_STATUS2[] = {
	 { "MCIF_WB_BUF_2_CUR_LINE_R", 0, 12, &umr_bitfield_default },
	 { "MCIF_WB_BUF_2_NEW_CONTENT", 13, 13, &umr_bitfield_default },
	 { "MCIF_WB_BUF_2_COLOR_DEPTH", 14, 14, &umr_bitfield_default },
	 { "MCIF_WB_BUF_2_Y_OVERRUN", 17, 17, &umr_bitfield_default },
	 { "MCIF_WB_BUF_2_C_OVERRUN", 18, 18, &umr_bitfield_default },
};
static struct umr_bitfield mmMCIF_WB1_MCIF_WB_BUF_3_STATUS[] = {
	 { "MCIF_WB_BUF_3_ACTIVE", 0, 0, &umr_bitfield_default },
	 { "MCIF_WB_BUF_3_SW_LOCKED", 1, 1, &umr_bitfield_default },
	 { "MCIF_WB_BUF_3_VCE_LOCKED", 2, 2, &umr_bitfield_default },
	 { "MCIF_WB_BUF_3_OVERFLOW", 3, 3, &umr_bitfield_default },
	 { "MCIF_WB_BUF_3_DISABLE", 4, 4, &umr_bitfield_default },
	 { "MCIF_WB_BUF_3_MODE", 5, 7, &umr_bitfield_default },
	 { "MCIF_WB_BUF_3_BUFTAG", 8, 11, &umr_bitfield_default },
	 { "MCIF_WB_BUF_3_NXT_BUF", 12, 14, &umr_bitfield_default },
	 { "MCIF_WB_BUF_3_FIELD", 15, 15, &umr_bitfield_default },
	 { "MCIF_WB_BUF_3_CUR_LINE_L", 16, 28, &umr_bitfield_default },
	 { "MCIF_WB_BUF_3_LONG_LINE_ERROR", 29, 29, &umr_bitfield_default },
	 { "MCIF_WB_BUF_3_SHORT_LINE_ERROR", 30, 30, &umr_bitfield_default },
	 { "MCIF_WB_BUF_3_FRAME_LENGTH_ERROR", 31, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMCIF_WB1_MCIF_WB_BUF_3_STATUS2[] = {
	 { "MCIF_WB_BUF_3_CUR_LINE_R", 0, 12, &umr_bitfield_default },
	 { "MCIF_WB_BUF_3_NEW_CONTENT", 13, 13, &umr_bitfield_default },
	 { "MCIF_WB_BUF_3_COLOR_DEPTH", 14, 14, &umr_bitfield_default },
	 { "MCIF_WB_BUF_3_Y_OVERRUN", 17, 17, &umr_bitfield_default },
	 { "MCIF_WB_BUF_3_C_OVERRUN", 18, 18, &umr_bitfield_default },
};
static struct umr_bitfield mmMCIF_WB1_MCIF_WB_BUF_4_STATUS[] = {
	 { "MCIF_WB_BUF_4_ACTIVE", 0, 0, &umr_bitfield_default },
	 { "MCIF_WB_BUF_4_SW_LOCKED", 1, 1, &umr_bitfield_default },
	 { "MCIF_WB_BUF_4_VCE_LOCKED", 2, 2, &umr_bitfield_default },
	 { "MCIF_WB_BUF_4_OVERFLOW", 3, 3, &umr_bitfield_default },
	 { "MCIF_WB_BUF_4_DISABLE", 4, 4, &umr_bitfield_default },
	 { "MCIF_WB_BUF_4_MODE", 5, 7, &umr_bitfield_default },
	 { "MCIF_WB_BUF_4_BUFTAG", 8, 11, &umr_bitfield_default },
	 { "MCIF_WB_BUF_4_NXT_BUF", 12, 14, &umr_bitfield_default },
	 { "MCIF_WB_BUF_4_FIELD", 15, 15, &umr_bitfield_default },
	 { "MCIF_WB_BUF_4_CUR_LINE_L", 16, 28, &umr_bitfield_default },
	 { "MCIF_WB_BUF_4_LONG_LINE_ERROR", 29, 29, &umr_bitfield_default },
	 { "MCIF_WB_BUF_4_SHORT_LINE_ERROR", 30, 30, &umr_bitfield_default },
	 { "MCIF_WB_BUF_4_FRAME_LENGTH_ERROR", 31, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMCIF_WB1_MCIF_WB_BUF_4_STATUS2[] = {
	 { "MCIF_WB_BUF_4_CUR_LINE_R", 0, 12, &umr_bitfield_default },
	 { "MCIF_WB_BUF_4_NEW_CONTENT", 13, 13, &umr_bitfield_default },
	 { "MCIF_WB_BUF_4_COLOR_DEPTH", 14, 14, &umr_bitfield_default },
	 { "MCIF_WB_BUF_4_Y_OVERRUN", 17, 17, &umr_bitfield_default },
	 { "MCIF_WB_BUF_4_C_OVERRUN", 18, 18, &umr_bitfield_default },
};
static struct umr_bitfield mmMCIF_WB1_MCIF_WB_ARBITRATION_CONTROL[] = {
	 { "MCIF_WB_CLIENT_ARBITRATION_SLICE", 0, 1, &umr_bitfield_default },
	 { "MCIF_WB_TIME_PER_PIXEL", 22, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMCIF_WB1_MCIF_WB_SCLK_CHANGE[] = {
	 { "WM_CHANGE_ACK_FORCE_ON", 0, 0, &umr_bitfield_default },
	 { "MCIF_WB_CLI_WATERMARK_MASK", 1, 3, &umr_bitfield_default },
};
static struct umr_bitfield mmMCIF_WB1_MCIF_WB_BUF_1_ADDR_Y[] = {
	 { "MCIF_WB_BUF_1_ADDR_Y", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMCIF_WB1_MCIF_WB_BUF_1_ADDR_Y_OFFSET[] = {
	 { "MCIF_WB_BUF_1_ADDR_Y_OFFSET", 0, 17, &umr_bitfield_default },
};
static struct umr_bitfield mmMCIF_WB1_MCIF_WB_BUF_1_ADDR_C[] = {
	 { "MCIF_WB_BUF_1_ADDR_C", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMCIF_WB1_MCIF_WB_BUF_1_ADDR_C_OFFSET[] = {
	 { "MCIF_WB_BUF_1_ADDR_C_OFFSET", 0, 17, &umr_bitfield_default },
};
static struct umr_bitfield mmMCIF_WB1_MCIF_WB_BUF_2_ADDR_Y[] = {
	 { "MCIF_WB_BUF_2_ADDR_Y", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMCIF_WB1_MCIF_WB_BUF_2_ADDR_Y_OFFSET[] = {
	 { "MCIF_WB_BUF_2_ADDR_Y_OFFSET", 0, 17, &umr_bitfield_default },
};
static struct umr_bitfield mmMCIF_WB1_MCIF_WB_BUF_2_ADDR_C[] = {
	 { "MCIF_WB_BUF_2_ADDR_C", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMCIF_WB1_MCIF_WB_BUF_2_ADDR_C_OFFSET[] = {
	 { "MCIF_WB_BUF_2_ADDR_C_OFFSET", 0, 17, &umr_bitfield_default },
};
static struct umr_bitfield mmMCIF_WB1_MCIF_WB_BUF_3_ADDR_Y[] = {
	 { "MCIF_WB_BUF_3_ADDR_Y", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMCIF_WB1_MCIF_WB_BUF_3_ADDR_Y_OFFSET[] = {
	 { "MCIF_WB_BUF_3_ADDR_Y_OFFSET", 0, 17, &umr_bitfield_default },
};
static struct umr_bitfield mmMCIF_WB1_MCIF_WB_BUF_3_ADDR_C[] = {
	 { "MCIF_WB_BUF_3_ADDR_C", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMCIF_WB1_MCIF_WB_BUF_3_ADDR_C_OFFSET[] = {
	 { "MCIF_WB_BUF_3_ADDR_C_OFFSET", 0, 17, &umr_bitfield_default },
};
static struct umr_bitfield mmMCIF_WB1_MCIF_WB_BUF_4_ADDR_Y[] = {
	 { "MCIF_WB_BUF_4_ADDR_Y", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMCIF_WB1_MCIF_WB_BUF_4_ADDR_Y_OFFSET[] = {
	 { "MCIF_WB_BUF_4_ADDR_Y_OFFSET", 0, 17, &umr_bitfield_default },
};
static struct umr_bitfield mmMCIF_WB1_MCIF_WB_BUF_4_ADDR_C[] = {
	 { "MCIF_WB_BUF_4_ADDR_C", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMCIF_WB1_MCIF_WB_BUF_4_ADDR_C_OFFSET[] = {
	 { "MCIF_WB_BUF_4_ADDR_C_OFFSET", 0, 17, &umr_bitfield_default },
};
static struct umr_bitfield mmMCIF_WB1_MCIF_WB_BUFMGR_VCE_CONTROL[] = {
	 { "MCIF_WB_BUFMGR_VCE_LOCK_IGNORE", 0, 0, &umr_bitfield_default },
	 { "MCIF_WB_BUFMGR_VCE_INT_EN", 4, 4, &umr_bitfield_default },
	 { "MCIF_WB_BUFMGR_VCE_INT_ACK", 5, 5, &umr_bitfield_default },
	 { "MCIF_WB_BUFMGR_VCE_SLICE_INT_EN", 6, 6, &umr_bitfield_default },
	 { "MCIF_WB_BUFMGR_VCE_LOCK", 8, 11, &umr_bitfield_default },
	 { "MCIF_WB_BUFMGR_SLICE_SIZE", 16, 28, &umr_bitfield_default },
};
static struct umr_bitfield mmMCIF_WB1_MCIF_WB_NB_PSTATE_LATENCY_WATERMARK[] = {
	 { "NB_PSTATE_CHANGE_REFRESH_WATERMARK", 0, 16, &umr_bitfield_default },
};
static struct umr_bitfield mmMCIF_WB1_MCIF_WB_NB_PSTATE_CONTROL[] = {
	 { "NB_PSTATE_CHANGE_URGENT_DURING_REQUEST", 0, 0, &umr_bitfield_default },
	 { "NB_PSTATE_CHANGE_FORCE_ON", 1, 1, &umr_bitfield_default },
	 { "NB_PSTATE_ALLOW_FOR_URGENT", 2, 2, &umr_bitfield_default },
	 { "NB_PSTATE_CHANGE_WATERMARK_MASK", 4, 6, &umr_bitfield_default },
};
static struct umr_bitfield mmMCIF_WB1_MCIF_WB_WATERMARK[] = {
	 { "MCIF_WB_CLI_WATERMARK", 0, 15, &umr_bitfield_default },
};
static struct umr_bitfield mmMCIF_WB1_MCIF_WB_CLOCK_GATER_CONTROL[] = {
	 { "MCIF_WB_CLI_CLOCK_GATER_OVERRIDE", 0, 0, &umr_bitfield_default },
};
static struct umr_bitfield mmMCIF_WB1_MCIF_WB_WARM_UP_CNTL[] = {
	 { "MCIF_WB_PITCH_SIZE_WARMUP", 8, 15, &umr_bitfield_default },
};
static struct umr_bitfield mmMCIF_WB1_MCIF_WB_SELF_REFRESH_CONTROL[] = {
	 { "DIS_REFRESH_UNDER_NBPREQ", 0, 0, &umr_bitfield_default },
	 { "PERFRAME_SELF_REFRESH", 1, 1, &umr_bitfield_default },
};
static struct umr_bitfield mmMCIF_WB1_MULTI_LEVEL_QOS_CTRL[] = {
	 { "MAX_SCALED_TIME_TO_URGENT", 0, 21, &umr_bitfield_default },
};
static struct umr_bitfield mmMCIF_WB1_MCIF_WB_BUF_LUMA_SIZE[] = {
	 { "MCIF_WB_BUF_LUMA_SIZE", 0, 19, &umr_bitfield_default },
};
static struct umr_bitfield mmMCIF_WB1_MCIF_WB_BUF_CHROMA_SIZE[] = {
	 { "MCIF_WB_BUF_CHROMA_SIZE", 0, 19, &umr_bitfield_default },
};
static struct umr_bitfield mmWBIF0_MISC_CTRL[] = {
	 { "MCIFWB0_WR_COMBINE_TIMEOUT_THRESH", 0, 9, &umr_bitfield_default },
	 { "MCIF_WB0_SOCCLK_DS_ENABLE", 16, 16, &umr_bitfield_default },
};
static struct umr_bitfield mmWBIF0_SMU_WM_CONTROL[] = {
	 { "MCIF_WB0_WM_CHG_SEL", 20, 21, &umr_bitfield_default },
	 { "MCIF_WB0_WM_CHG_REQ", 22, 22, &umr_bitfield_default },
	 { "MCIF_WB0_WM_CHG_ACK_INT_DIS", 24, 24, &umr_bitfield_default },
	 { "MCIF_WB0_WM_CHG_ACK_INT_STATUS", 25, 25, &umr_bitfield_default },
};
static struct umr_bitfield mmWBIF0_PHASE0_OUTSTANDING_COUNTER[] = {
	 { "MCIF_WB0_PHASE0_OUTSTANDING_COUNTER", 0, 26, &umr_bitfield_default },
};
static struct umr_bitfield mmWBIF0_PHASE1_OUTSTANDING_COUNTER[] = {
	 { "MCIF_WB0_PHASE1_OUTSTANDING_COUNTER", 0, 26, &umr_bitfield_default },
};
static struct umr_bitfield mmWBIF1_MISC_CTRL[] = {
	 { "MCIFWB1_WR_COMBINE_TIMEOUT_THRESH", 0, 9, &umr_bitfield_default },
	 { "MCIF_WB1_SOCCLK_DS_ENABLE", 16, 16, &umr_bitfield_default },
};
static struct umr_bitfield mmWBIF1_SMU_WM_CONTROL[] = {
	 { "MCIF_WB1_WM_CHG_SEL", 20, 21, &umr_bitfield_default },
	 { "MCIF_WB1_WM_CHG_REQ", 22, 22, &umr_bitfield_default },
	 { "MCIF_WB1_WM_CHG_ACK_INT_DIS", 24, 24, &umr_bitfield_default },
	 { "MCIF_WB1_WM_CHG_ACK_INT_STATUS", 25, 25, &umr_bitfield_default },
};
static struct umr_bitfield mmWBIF1_PHASE0_OUTSTANDING_COUNTER[] = {
	 { "MCIF_WB1_PHASE0_OUTSTANDING_COUNTER", 0, 26, &umr_bitfield_default },
};
static struct umr_bitfield mmWBIF1_PHASE1_OUTSTANDING_COUNTER[] = {
	 { "MCIF_WB1_PHASE1_OUTSTANDING_COUNTER", 0, 26, &umr_bitfield_default },
};
static struct umr_bitfield mmVGA_SRC_SPLIT_CNTL[] = {
	 { "VGA_SPLIT_SEL", 0, 1, &umr_bitfield_default },
};
static struct umr_bitfield mmMMHUBBUB_MEM_PWR_STATUS[] = {
	 { "MCIF_DWB0_LUMA_MEM0_PWR_STATE", 0, 1, &umr_bitfield_default },
	 { "MCIF_DWB0_LUMA_MEM1_PWR_STATE", 2, 3, &umr_bitfield_default },
	 { "MCIF_DWB0_CHROMA_MEM0_PWR_STATE", 4, 5, &umr_bitfield_default },
	 { "MCIF_DWB0_CHROMA_MEM1_PWR_STATE", 6, 7, &umr_bitfield_default },
	 { "MCIF_DWB1_LUMA_MEM0_PWR_STATE", 8, 9, &umr_bitfield_default },
	 { "MCIF_DWB1_LUMA_MEM1_PWR_STATE", 10, 11, &umr_bitfield_default },
	 { "MCIF_DWB1_CHROMA_MEM0_PWR_STATE", 12, 13, &umr_bitfield_default },
	 { "MCIF_DWB1_CHROMA_MEM1_PWR_STATE", 14, 15, &umr_bitfield_default },
	 { "VGA_MEM_PWR_STATE", 31, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMMHUBBUB_MEM_PWR_CNTL[] = {
	 { "VGA_MEM_PWR_FORCE", 0, 0, &umr_bitfield_default },
	 { "VGA_MEM_PWR_DIS", 1, 1, &umr_bitfield_default },
	 { "MCIF_DWB0_MEM_PWR_FORCE", 2, 3, &umr_bitfield_default },
	 { "MCIF_DWB0_MEM_PWR_DIS", 4, 4, &umr_bitfield_default },
	 { "MCIF_DWB0_MEM_PWR_MODE_SEL", 5, 6, &umr_bitfield_default },
	 { "MCIF_DWB0_LUMA_MEM_EN_NUM", 7, 7, &umr_bitfield_default },
	 { "MCIF_DWB0_CHROMA_MEM_EN_NUM", 8, 8, &umr_bitfield_default },
	 { "MCIF_DWB1_MEM_PWR_FORCE", 9, 10, &umr_bitfield_default },
	 { "MCIF_DWB1_MEM_PWR_DIS", 11, 11, &umr_bitfield_default },
	 { "MCIF_DWB1_MEM_PWR_MODE_SEL", 12, 13, &umr_bitfield_default },
	 { "MCIF_DWB1_LUMA_MEM_EN_NUM", 14, 14, &umr_bitfield_default },
	 { "MCIF_DWB1_CHROMA_MEM_EN_NUM", 15, 15, &umr_bitfield_default },
};
static struct umr_bitfield mmMMHUBBUB_CLOCK_CNTL[] = {
	 { "MMHUBBUB_TEST_CLK_SEL", 0, 4, &umr_bitfield_default },
	 { "DISPCLK_R_MMHUBBUB_GATE_DIS", 5, 5, &umr_bitfield_default },
	 { "DISPCLK_G_VGAIF_GATE_DIS", 6, 6, &umr_bitfield_default },
	 { "SOCCLK_G_VGAIF_GATE_DIS", 7, 7, &umr_bitfield_default },
	 { "DISPCLK_G_VGA_GATE_DIS", 8, 8, &umr_bitfield_default },
	 { "DISPCLK_G_WBIF0_GATE_DIS", 9, 9, &umr_bitfield_default },
	 { "SOCCLK_G_WBIF0_GATE_DIS", 10, 10, &umr_bitfield_default },
	 { "DISPCLK_G_WBIF1_GATE_DIS", 11, 11, &umr_bitfield_default },
	 { "SOCCLK_G_WBIF1_GATE_DIS", 12, 12, &umr_bitfield_default },
};
static struct umr_bitfield mmMMHUBBUB_SOFT_RESET[] = {
	 { "VGA_SOFT_RESET", 0, 0, &umr_bitfield_default },
	 { "VGAIF_SOFT_RESET", 1, 1, &umr_bitfield_default },
	 { "WBIF0_SOFT_RESET", 2, 2, &umr_bitfield_default },
	 { "WBIF1_SOFT_RESET", 3, 3, &umr_bitfield_default },
};
static struct umr_bitfield mmMCIF_CONTROL[] = {
	 { "MCIF_MC_LATENCY_COUNTER_ENABLE", 30, 30, &umr_bitfield_default },
	 { "MCIF_MC_LATENCY_COUNTER_URGENT_ONLY", 31, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMCIF_WRITE_COMBINE_CONTROL[] = {
	 { "MCIF_WRITE_COMBINE_TIMEOUT", 0, 9, &umr_bitfield_default },
};
static struct umr_bitfield mmMCIF_PHASE0_OUTSTANDING_COUNTER[] = {
	 { "MCIF_PHASE0_OUTSTANDING_COUNTER", 0, 26, &umr_bitfield_default },
};
static struct umr_bitfield mmMCIF_PHASE1_OUTSTANDING_COUNTER[] = {
	 { "MCIF_PHASE1_OUTSTANDING_COUNTER", 0, 26, &umr_bitfield_default },
};
static struct umr_bitfield mmMCIF_PHASE2_OUTSTANDING_COUNTER[] = {
	 { "MCIF_PHASE2_OUTSTANDING_COUNTER", 0, 26, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_PERFMON5_PERFCOUNTER_CNTL[] = {
	 { "PERFCOUNTER_EVENT_SEL", 0, 8, &umr_bitfield_default },
	 { "PERFCOUNTER_CVALUE_SEL", 9, 11, &umr_bitfield_default },
	 { "PERFCOUNTER_INC_MODE", 12, 14, &umr_bitfield_default },
	 { "PERFCOUNTER_HW_CNTL_SEL", 15, 15, &umr_bitfield_default },
	 { "PERFCOUNTER_RUNEN_MODE", 16, 16, &umr_bitfield_default },
	 { "PERFCOUNTER_CNTOFF_START_DIS", 22, 22, &umr_bitfield_default },
	 { "PERFCOUNTER_RESTART_EN", 23, 23, &umr_bitfield_default },
	 { "PERFCOUNTER_INT_EN", 24, 24, &umr_bitfield_default },
	 { "PERFCOUNTER_OFF_MASK", 25, 25, &umr_bitfield_default },
	 { "PERFCOUNTER_ACTIVE", 26, 26, &umr_bitfield_default },
	 { "PERFCOUNTER_CNTL_SEL", 29, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_PERFMON5_PERFCOUNTER_CNTL2[] = {
	 { "PERFCOUNTER_COUNTED_VALUE_TYPE", 0, 1, &umr_bitfield_default },
	 { "PERFCOUNTER_HW_STOP1_SEL", 2, 2, &umr_bitfield_default },
	 { "PERFCOUNTER_HW_STOP2_SEL", 3, 3, &umr_bitfield_default },
	 { "PERFCOUNTER_CNTOFF_SEL", 8, 13, &umr_bitfield_default },
	 { "PERFCOUNTER_CNTL2_SEL", 29, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_PERFMON5_PERFCOUNTER_STATE[] = {
	 { "PERFCOUNTER_CNT0_STATE", 0, 1, &umr_bitfield_default },
	 { "PERFCOUNTER_STATE_SEL0", 2, 2, &umr_bitfield_default },
	 { "PERFCOUNTER_CNT1_STATE", 4, 5, &umr_bitfield_default },
	 { "PERFCOUNTER_STATE_SEL1", 6, 6, &umr_bitfield_default },
	 { "PERFCOUNTER_CNT2_STATE", 8, 9, &umr_bitfield_default },
	 { "PERFCOUNTER_STATE_SEL2", 10, 10, &umr_bitfield_default },
	 { "PERFCOUNTER_CNT3_STATE", 12, 13, &umr_bitfield_default },
	 { "PERFCOUNTER_STATE_SEL3", 14, 14, &umr_bitfield_default },
	 { "PERFCOUNTER_CNT4_STATE", 16, 17, &umr_bitfield_default },
	 { "PERFCOUNTER_STATE_SEL4", 18, 18, &umr_bitfield_default },
	 { "PERFCOUNTER_CNT5_STATE", 20, 21, &umr_bitfield_default },
	 { "PERFCOUNTER_STATE_SEL5", 22, 22, &umr_bitfield_default },
	 { "PERFCOUNTER_CNT6_STATE", 24, 25, &umr_bitfield_default },
	 { "PERFCOUNTER_STATE_SEL6", 26, 26, &umr_bitfield_default },
	 { "PERFCOUNTER_CNT7_STATE", 28, 29, &umr_bitfield_default },
	 { "PERFCOUNTER_STATE_SEL7", 30, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_PERFMON5_PERFMON_CNTL[] = {
	 { "PERFMON_STATE", 0, 1, &umr_bitfield_default },
	 { "PERFMON_RPT_COUNT", 8, 27, &umr_bitfield_default },
	 { "PERFMON_CNTOFF_AND_OR", 28, 28, &umr_bitfield_default },
	 { "PERFMON_CNTOFF_INT_EN", 29, 29, &umr_bitfield_default },
	 { "PERFMON_CNTOFF_INT_STATUS", 30, 30, &umr_bitfield_default },
	 { "PERFMON_CNTOFF_INT_ACK", 31, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_PERFMON5_PERFMON_CNTL2[] = {
	 { "PERFMON_CNTOFF_INT_TYPE", 0, 0, &umr_bitfield_default },
	 { "PERFMON_CLK_ENABLE", 1, 1, &umr_bitfield_default },
	 { "PERFMON_RUN_ENABLE_START_SEL", 2, 9, &umr_bitfield_default },
	 { "PERFMON_RUN_ENABLE_STOP_SEL", 10, 17, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_PERFMON5_PERFMON_CVALUE_INT_MISC[] = {
	 { "PERFCOUNTER_INT0_STATUS", 0, 0, &umr_bitfield_default },
	 { "PERFCOUNTER_INT1_STATUS", 1, 1, &umr_bitfield_default },
	 { "PERFCOUNTER_INT2_STATUS", 2, 2, &umr_bitfield_default },
	 { "PERFCOUNTER_INT3_STATUS", 3, 3, &umr_bitfield_default },
	 { "PERFCOUNTER_INT4_STATUS", 4, 4, &umr_bitfield_default },
	 { "PERFCOUNTER_INT5_STATUS", 5, 5, &umr_bitfield_default },
	 { "PERFCOUNTER_INT6_STATUS", 6, 6, &umr_bitfield_default },
	 { "PERFCOUNTER_INT7_STATUS", 7, 7, &umr_bitfield_default },
	 { "PERFCOUNTER_INT0_ACK", 8, 8, &umr_bitfield_default },
	 { "PERFCOUNTER_INT1_ACK", 9, 9, &umr_bitfield_default },
	 { "PERFCOUNTER_INT2_ACK", 10, 10, &umr_bitfield_default },
	 { "PERFCOUNTER_INT3_ACK", 11, 11, &umr_bitfield_default },
	 { "PERFCOUNTER_INT4_ACK", 12, 12, &umr_bitfield_default },
	 { "PERFCOUNTER_INT5_ACK", 13, 13, &umr_bitfield_default },
	 { "PERFCOUNTER_INT6_ACK", 14, 14, &umr_bitfield_default },
	 { "PERFCOUNTER_INT7_ACK", 15, 15, &umr_bitfield_default },
	 { "PERFMON_CVALUE_HI", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_PERFMON5_PERFMON_CVALUE_LOW[] = {
	 { "PERFMON_CVALUE_LOW", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_PERFMON5_PERFMON_HI[] = {
	 { "PERFMON_HI", 0, 15, &umr_bitfield_default },
	 { "PERFMON_READ_SEL", 29, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_PERFMON5_PERFMON_LOW[] = {
	 { "PERFMON_LOW", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmAZF0STREAM0_AZALIA_STREAM_INDEX[] = {
	 { "AZALIA_STREAM_REG_INDEX", 0, 7, &umr_bitfield_default },
	 { "AZALIA_STREAM_REG_WRITE_EN", 8, 8, &umr_bitfield_default },
};
static struct umr_bitfield mmAZF0STREAM0_AZALIA_STREAM_DATA[] = {
	 { "AZALIA_STREAM_REG_DATA", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmAZF0STREAM1_AZALIA_STREAM_INDEX[] = {
	 { "AZALIA_STREAM_REG_INDEX", 0, 7, &umr_bitfield_default },
	 { "AZALIA_STREAM_REG_WRITE_EN", 8, 8, &umr_bitfield_default },
};
static struct umr_bitfield mmAZF0STREAM1_AZALIA_STREAM_DATA[] = {
	 { "AZALIA_STREAM_REG_DATA", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmAZF0STREAM2_AZALIA_STREAM_INDEX[] = {
	 { "AZALIA_STREAM_REG_INDEX", 0, 7, &umr_bitfield_default },
	 { "AZALIA_STREAM_REG_WRITE_EN", 8, 8, &umr_bitfield_default },
};
static struct umr_bitfield mmAZF0STREAM2_AZALIA_STREAM_DATA[] = {
	 { "AZALIA_STREAM_REG_DATA", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmAZF0STREAM3_AZALIA_STREAM_INDEX[] = {
	 { "AZALIA_STREAM_REG_INDEX", 0, 7, &umr_bitfield_default },
	 { "AZALIA_STREAM_REG_WRITE_EN", 8, 8, &umr_bitfield_default },
};
static struct umr_bitfield mmAZF0STREAM3_AZALIA_STREAM_DATA[] = {
	 { "AZALIA_STREAM_REG_DATA", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmAZF0STREAM4_AZALIA_STREAM_INDEX[] = {
	 { "AZALIA_STREAM_REG_INDEX", 0, 7, &umr_bitfield_default },
	 { "AZALIA_STREAM_REG_WRITE_EN", 8, 8, &umr_bitfield_default },
};
static struct umr_bitfield mmAZF0STREAM4_AZALIA_STREAM_DATA[] = {
	 { "AZALIA_STREAM_REG_DATA", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmAZF0STREAM5_AZALIA_STREAM_INDEX[] = {
	 { "AZALIA_STREAM_REG_INDEX", 0, 7, &umr_bitfield_default },
	 { "AZALIA_STREAM_REG_WRITE_EN", 8, 8, &umr_bitfield_default },
};
static struct umr_bitfield mmAZF0STREAM5_AZALIA_STREAM_DATA[] = {
	 { "AZALIA_STREAM_REG_DATA", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmAZF0STREAM6_AZALIA_STREAM_INDEX[] = {
	 { "AZALIA_STREAM_REG_INDEX", 0, 7, &umr_bitfield_default },
	 { "AZALIA_STREAM_REG_WRITE_EN", 8, 8, &umr_bitfield_default },
};
static struct umr_bitfield mmAZF0STREAM6_AZALIA_STREAM_DATA[] = {
	 { "AZALIA_STREAM_REG_DATA", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmAZF0STREAM7_AZALIA_STREAM_INDEX[] = {
	 { "AZALIA_STREAM_REG_INDEX", 0, 7, &umr_bitfield_default },
	 { "AZALIA_STREAM_REG_WRITE_EN", 8, 8, &umr_bitfield_default },
};
static struct umr_bitfield mmAZF0STREAM7_AZALIA_STREAM_DATA[] = {
	 { "AZALIA_STREAM_REG_DATA", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmAZ_CLOCK_CNTL[] = {
	 { "SCLK_G_STREAM_AZ_GATE_DIS", 0, 0, &umr_bitfield_default },
	 { "SCLK_R_AZ_GATE_DIS", 8, 8, &umr_bitfield_default },
	 { "SCLK_G_CNTL_AZ_GATE_DIS", 16, 16, &umr_bitfield_default },
	 { "DCIPG_TEST_CLK_SEL", 24, 28, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_PERFMON6_PERFCOUNTER_CNTL[] = {
	 { "PERFCOUNTER_EVENT_SEL", 0, 8, &umr_bitfield_default },
	 { "PERFCOUNTER_CVALUE_SEL", 9, 11, &umr_bitfield_default },
	 { "PERFCOUNTER_INC_MODE", 12, 14, &umr_bitfield_default },
	 { "PERFCOUNTER_HW_CNTL_SEL", 15, 15, &umr_bitfield_default },
	 { "PERFCOUNTER_RUNEN_MODE", 16, 16, &umr_bitfield_default },
	 { "PERFCOUNTER_CNTOFF_START_DIS", 22, 22, &umr_bitfield_default },
	 { "PERFCOUNTER_RESTART_EN", 23, 23, &umr_bitfield_default },
	 { "PERFCOUNTER_INT_EN", 24, 24, &umr_bitfield_default },
	 { "PERFCOUNTER_OFF_MASK", 25, 25, &umr_bitfield_default },
	 { "PERFCOUNTER_ACTIVE", 26, 26, &umr_bitfield_default },
	 { "PERFCOUNTER_CNTL_SEL", 29, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_PERFMON6_PERFCOUNTER_CNTL2[] = {
	 { "PERFCOUNTER_COUNTED_VALUE_TYPE", 0, 1, &umr_bitfield_default },
	 { "PERFCOUNTER_HW_STOP1_SEL", 2, 2, &umr_bitfield_default },
	 { "PERFCOUNTER_HW_STOP2_SEL", 3, 3, &umr_bitfield_default },
	 { "PERFCOUNTER_CNTOFF_SEL", 8, 13, &umr_bitfield_default },
	 { "PERFCOUNTER_CNTL2_SEL", 29, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_PERFMON6_PERFCOUNTER_STATE[] = {
	 { "PERFCOUNTER_CNT0_STATE", 0, 1, &umr_bitfield_default },
	 { "PERFCOUNTER_STATE_SEL0", 2, 2, &umr_bitfield_default },
	 { "PERFCOUNTER_CNT1_STATE", 4, 5, &umr_bitfield_default },
	 { "PERFCOUNTER_STATE_SEL1", 6, 6, &umr_bitfield_default },
	 { "PERFCOUNTER_CNT2_STATE", 8, 9, &umr_bitfield_default },
	 { "PERFCOUNTER_STATE_SEL2", 10, 10, &umr_bitfield_default },
	 { "PERFCOUNTER_CNT3_STATE", 12, 13, &umr_bitfield_default },
	 { "PERFCOUNTER_STATE_SEL3", 14, 14, &umr_bitfield_default },
	 { "PERFCOUNTER_CNT4_STATE", 16, 17, &umr_bitfield_default },
	 { "PERFCOUNTER_STATE_SEL4", 18, 18, &umr_bitfield_default },
	 { "PERFCOUNTER_CNT5_STATE", 20, 21, &umr_bitfield_default },
	 { "PERFCOUNTER_STATE_SEL5", 22, 22, &umr_bitfield_default },
	 { "PERFCOUNTER_CNT6_STATE", 24, 25, &umr_bitfield_default },
	 { "PERFCOUNTER_STATE_SEL6", 26, 26, &umr_bitfield_default },
	 { "PERFCOUNTER_CNT7_STATE", 28, 29, &umr_bitfield_default },
	 { "PERFCOUNTER_STATE_SEL7", 30, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_PERFMON6_PERFMON_CNTL[] = {
	 { "PERFMON_STATE", 0, 1, &umr_bitfield_default },
	 { "PERFMON_RPT_COUNT", 8, 27, &umr_bitfield_default },
	 { "PERFMON_CNTOFF_AND_OR", 28, 28, &umr_bitfield_default },
	 { "PERFMON_CNTOFF_INT_EN", 29, 29, &umr_bitfield_default },
	 { "PERFMON_CNTOFF_INT_STATUS", 30, 30, &umr_bitfield_default },
	 { "PERFMON_CNTOFF_INT_ACK", 31, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_PERFMON6_PERFMON_CNTL2[] = {
	 { "PERFMON_CNTOFF_INT_TYPE", 0, 0, &umr_bitfield_default },
	 { "PERFMON_CLK_ENABLE", 1, 1, &umr_bitfield_default },
	 { "PERFMON_RUN_ENABLE_START_SEL", 2, 9, &umr_bitfield_default },
	 { "PERFMON_RUN_ENABLE_STOP_SEL", 10, 17, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_PERFMON6_PERFMON_CVALUE_INT_MISC[] = {
	 { "PERFCOUNTER_INT0_STATUS", 0, 0, &umr_bitfield_default },
	 { "PERFCOUNTER_INT1_STATUS", 1, 1, &umr_bitfield_default },
	 { "PERFCOUNTER_INT2_STATUS", 2, 2, &umr_bitfield_default },
	 { "PERFCOUNTER_INT3_STATUS", 3, 3, &umr_bitfield_default },
	 { "PERFCOUNTER_INT4_STATUS", 4, 4, &umr_bitfield_default },
	 { "PERFCOUNTER_INT5_STATUS", 5, 5, &umr_bitfield_default },
	 { "PERFCOUNTER_INT6_STATUS", 6, 6, &umr_bitfield_default },
	 { "PERFCOUNTER_INT7_STATUS", 7, 7, &umr_bitfield_default },
	 { "PERFCOUNTER_INT0_ACK", 8, 8, &umr_bitfield_default },
	 { "PERFCOUNTER_INT1_ACK", 9, 9, &umr_bitfield_default },
	 { "PERFCOUNTER_INT2_ACK", 10, 10, &umr_bitfield_default },
	 { "PERFCOUNTER_INT3_ACK", 11, 11, &umr_bitfield_default },
	 { "PERFCOUNTER_INT4_ACK", 12, 12, &umr_bitfield_default },
	 { "PERFCOUNTER_INT5_ACK", 13, 13, &umr_bitfield_default },
	 { "PERFCOUNTER_INT6_ACK", 14, 14, &umr_bitfield_default },
	 { "PERFCOUNTER_INT7_ACK", 15, 15, &umr_bitfield_default },
	 { "PERFMON_CVALUE_HI", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_PERFMON6_PERFMON_CVALUE_LOW[] = {
	 { "PERFMON_CVALUE_LOW", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_PERFMON6_PERFMON_HI[] = {
	 { "PERFMON_HI", 0, 15, &umr_bitfield_default },
	 { "PERFMON_READ_SEL", 29, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_PERFMON6_PERFMON_LOW[] = {
	 { "PERFMON_LOW", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmAZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX[] = {
	 { "AZALIA_ENDPOINT_REG_INDEX", 0, 13, &umr_bitfield_default },
};
static struct umr_bitfield mmAZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA[] = {
	 { "AZALIA_ENDPOINT_REG_DATA", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmAZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_INDEX[] = {
	 { "AZALIA_ENDPOINT_REG_INDEX", 0, 13, &umr_bitfield_default },
};
static struct umr_bitfield mmAZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_DATA[] = {
	 { "AZALIA_ENDPOINT_REG_DATA", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmAZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_INDEX[] = {
	 { "AZALIA_ENDPOINT_REG_INDEX", 0, 13, &umr_bitfield_default },
};
static struct umr_bitfield mmAZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_DATA[] = {
	 { "AZALIA_ENDPOINT_REG_DATA", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmAZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_INDEX[] = {
	 { "AZALIA_ENDPOINT_REG_INDEX", 0, 13, &umr_bitfield_default },
};
static struct umr_bitfield mmAZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_DATA[] = {
	 { "AZALIA_ENDPOINT_REG_DATA", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmAZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_INDEX[] = {
	 { "AZALIA_ENDPOINT_REG_INDEX", 0, 13, &umr_bitfield_default },
};
static struct umr_bitfield mmAZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_DATA[] = {
	 { "AZALIA_ENDPOINT_REG_DATA", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmAZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_INDEX[] = {
	 { "AZALIA_ENDPOINT_REG_INDEX", 0, 13, &umr_bitfield_default },
};
static struct umr_bitfield mmAZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_DATA[] = {
	 { "AZALIA_ENDPOINT_REG_DATA", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmAZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_INDEX[] = {
	 { "AZALIA_ENDPOINT_REG_INDEX", 0, 13, &umr_bitfield_default },
};
static struct umr_bitfield mmAZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_DATA[] = {
	 { "AZALIA_ENDPOINT_REG_DATA", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmAZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_INDEX[] = {
	 { "AZALIA_ENDPOINT_REG_INDEX", 0, 13, &umr_bitfield_default },
};
static struct umr_bitfield mmAZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_DATA[] = {
	 { "AZALIA_ENDPOINT_REG_DATA", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmAZALIA_CONTROLLER_CLOCK_GATING[] = {
	 { "ENABLE_CLOCK_GATING", 0, 0, &umr_bitfield_default },
	 { "CLOCK_ON_STATE", 4, 4, &umr_bitfield_default },
};
static struct umr_bitfield mmAZALIA_AUDIO_DTO[] = {
	 { "AZALIA_AUDIO_DTO_PHASE", 0, 15, &umr_bitfield_default },
	 { "AZALIA_AUDIO_DTO_MODULE", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmAZALIA_AUDIO_DTO_CONTROL[] = {
	 { "AZALIA_AUDIO_FORCE_DTO", 8, 9, &umr_bitfield_default },
};
static struct umr_bitfield mmAZALIA_SOCCLK_CONTROL[] = {
	 { "AUDIO_STREAM_SOCCLK_DEEP_SLEEP_EXIT_EN", 1, 1, &umr_bitfield_default },
};
static struct umr_bitfield mmAZALIA_UNDERFLOW_FILLER_SAMPLE[] = {
	 { "AZALIA_UNDERFLOW_FILLER_SAMPLE", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmAZALIA_DATA_DMA_CONTROL[] = {
	 { "DATA_DMA_NON_SNOOP", 0, 1, &umr_bitfield_default },
	 { "INPUT_DATA_DMA_NON_SNOOP", 2, 3, &umr_bitfield_default },
	 { "DATA_DMA_ISOCHRONOUS", 4, 5, &umr_bitfield_default },
	 { "INPUT_DATA_DMA_ISOCHRONOUS", 6, 7, &umr_bitfield_default },
	 { "AZALIA_IOC_GENERATION_METHOD", 16, 16, &umr_bitfield_default },
	 { "AZALIA_UNDERFLOW_CONTROL", 17, 17, &umr_bitfield_default },
};
static struct umr_bitfield mmAZALIA_BDL_DMA_CONTROL[] = {
	 { "BDL_DMA_NON_SNOOP", 0, 1, &umr_bitfield_default },
	 { "INPUT_BDL_DMA_NON_SNOOP", 2, 3, &umr_bitfield_default },
	 { "BDL_DMA_ISOCHRONOUS", 4, 5, &umr_bitfield_default },
	 { "INPUT_BDL_DMA_ISOCHRONOUS", 6, 7, &umr_bitfield_default },
};
static struct umr_bitfield mmAZALIA_RIRB_AND_DP_CONTROL[] = {
	 { "RIRB_NON_SNOOP", 0, 0, &umr_bitfield_default },
	 { "DP_DMA_NON_SNOOP", 4, 4, &umr_bitfield_default },
	 { "DP_UPDATE_FREQ_DIVIDER", 5, 8, &umr_bitfield_default },
};
static struct umr_bitfield mmAZALIA_CORB_DMA_CONTROL[] = {
	 { "CORB_DMA_NON_SNOOP", 0, 0, &umr_bitfield_default },
	 { "CORB_DMA_ISOCHRONOUS", 4, 4, &umr_bitfield_default },
};
static struct umr_bitfield mmAZALIA_APPLICATION_POSITION_IN_CYCLIC_BUFFER[] = {
	 { "APPLICATION_POSITION_IN_CYCLIC_BUFFER", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmAZALIA_CYCLIC_BUFFER_SYNC[] = {
	 { "CYCLIC_BUFFER_SYNC_ENABLE", 0, 0, &umr_bitfield_default },
};
static struct umr_bitfield mmAZALIA_GLOBAL_CAPABILITIES[] = {
	 { "NUMBER_OF_SERIAL_DATA_OUTPUT_SIGNALS", 1, 2, &umr_bitfield_default },
};
static struct umr_bitfield mmAZALIA_OUTPUT_PAYLOAD_CAPABILITY[] = {
	 { "OUTPUT_PAYLOAD_CAPABILITY", 0, 15, &umr_bitfield_default },
	 { "OUTSTRMPAY", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmAZALIA_OUTPUT_STREAM_ARBITER_CONTROL[] = {
	 { "LATENCY_HIDING_LEVEL", 0, 7, &umr_bitfield_default },
	 { "SYS_MEM_ACTIVE_ENABLE", 8, 8, &umr_bitfield_default },
	 { "INPUT_LATENCY_HIDING_LEVEL", 16, 23, &umr_bitfield_default },
};
static struct umr_bitfield mmAZALIA_INPUT_PAYLOAD_CAPABILITY[] = {
	 { "INPUT_PAYLOAD_CAPABILITY", 0, 15, &umr_bitfield_default },
	 { "INSTRMPAY", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmAZALIA_INPUT_CRC0_CONTROL0[] = {
	 { "INPUT_CRC_EN", 0, 0, &umr_bitfield_default },
	 { "INPUT_CRC_BLOCK_MODE", 4, 4, &umr_bitfield_default },
	 { "INPUT_CRC_INSTANCE_SEL", 8, 10, &umr_bitfield_default },
};
static struct umr_bitfield mmAZALIA_INPUT_CRC0_CONTROL1[] = {
	 { "INPUT_CRC_BLOCK_SIZE", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmAZALIA_INPUT_CRC0_CONTROL2[] = {
	 { "INPUT_CRC_BLOCK_ITERATION", 0, 15, &umr_bitfield_default },
};
static struct umr_bitfield mmAZALIA_INPUT_CRC0_CONTROL3[] = {
	 { "INPUT_CRC_COMPLETE", 0, 0, &umr_bitfield_default },
	 { "INPUT_CRC_BLOCK_COMPLETE_PHASE", 4, 4, &umr_bitfield_default },
	 { "INPUT_CRC_CHANNEL_RESULT_SEL", 8, 10, &umr_bitfield_default },
};
static struct umr_bitfield mmAZALIA_INPUT_CRC0_RESULT[] = {
	 { "INPUT_CRC_RESULT", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmAZALIA_INPUT_CRC1_CONTROL0[] = {
	 { "INPUT_CRC_EN", 0, 0, &umr_bitfield_default },
	 { "INPUT_CRC_BLOCK_MODE", 4, 4, &umr_bitfield_default },
	 { "INPUT_CRC_INSTANCE_SEL", 8, 10, &umr_bitfield_default },
};
static struct umr_bitfield mmAZALIA_INPUT_CRC1_CONTROL1[] = {
	 { "INPUT_CRC_BLOCK_SIZE", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmAZALIA_INPUT_CRC1_CONTROL2[] = {
	 { "INPUT_CRC_BLOCK_ITERATION", 0, 15, &umr_bitfield_default },
};
static struct umr_bitfield mmAZALIA_INPUT_CRC1_CONTROL3[] = {
	 { "INPUT_CRC_COMPLETE", 0, 0, &umr_bitfield_default },
	 { "INPUT_CRC_BLOCK_COMPLETE_PHASE", 4, 4, &umr_bitfield_default },
	 { "INPUT_CRC_CHANNEL_RESULT_SEL", 8, 10, &umr_bitfield_default },
};
static struct umr_bitfield mmAZALIA_INPUT_CRC1_RESULT[] = {
	 { "INPUT_CRC_RESULT", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmAZALIA_CRC0_CONTROL0[] = {
	 { "CRC_EN", 0, 0, &umr_bitfield_default },
	 { "CRC_BLOCK_MODE", 4, 4, &umr_bitfield_default },
	 { "CRC_INSTANCE_SEL", 8, 10, &umr_bitfield_default },
	 { "CRC_SOURCE_SEL", 12, 12, &umr_bitfield_default },
};
static struct umr_bitfield mmAZALIA_CRC0_CONTROL1[] = {
	 { "CRC_BLOCK_SIZE", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmAZALIA_CRC0_CONTROL2[] = {
	 { "CRC_BLOCK_ITERATION", 0, 15, &umr_bitfield_default },
};
static struct umr_bitfield mmAZALIA_CRC0_CONTROL3[] = {
	 { "CRC_COMPLETE", 0, 0, &umr_bitfield_default },
	 { "CRC_BLOCK_COMPLETE_PHASE", 4, 4, &umr_bitfield_default },
	 { "CRC_CHANNEL_RESULT_SEL", 8, 10, &umr_bitfield_default },
};
static struct umr_bitfield mmAZALIA_CRC0_RESULT[] = {
	 { "CRC_RESULT", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmAZALIA_CRC1_CONTROL0[] = {
	 { "CRC_EN", 0, 0, &umr_bitfield_default },
	 { "CRC_BLOCK_MODE", 4, 4, &umr_bitfield_default },
	 { "CRC_INSTANCE_SEL", 8, 10, &umr_bitfield_default },
	 { "CRC_SOURCE_SEL", 12, 12, &umr_bitfield_default },
};
static struct umr_bitfield mmAZALIA_CRC1_CONTROL1[] = {
	 { "CRC_BLOCK_SIZE", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmAZALIA_CRC1_CONTROL2[] = {
	 { "CRC_BLOCK_ITERATION", 0, 15, &umr_bitfield_default },
};
static struct umr_bitfield mmAZALIA_CRC1_CONTROL3[] = {
	 { "CRC_COMPLETE", 0, 0, &umr_bitfield_default },
	 { "CRC_BLOCK_COMPLETE_PHASE", 4, 4, &umr_bitfield_default },
	 { "CRC_CHANNEL_RESULT_SEL", 8, 10, &umr_bitfield_default },
};
static struct umr_bitfield mmAZALIA_CRC1_RESULT[] = {
	 { "CRC_RESULT", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmAZALIA_MEM_PWR_CTRL[] = {
	 { "AZ_MEM_PWR_FORCE", 0, 1, &umr_bitfield_default },
	 { "AZ_MEM_PWR_DIS", 2, 2, &umr_bitfield_default },
	 { "AZ_INPUT_STREAM0_MEM_PWR_FORCE", 3, 4, &umr_bitfield_default },
	 { "AZ_INPUT_STREAM0_MEM_PWR_DIS", 5, 5, &umr_bitfield_default },
	 { "AZ_INPUT_STREAM1_MEM_PWR_FORCE", 6, 7, &umr_bitfield_default },
	 { "AZ_INPUT_STREAM1_MEM_PWR_DIS", 8, 8, &umr_bitfield_default },
	 { "AZ_INPUT_STREAM2_MEM_PWR_FORCE", 9, 10, &umr_bitfield_default },
	 { "AZ_INPUT_STREAM2_MEM_PWR_DIS", 11, 11, &umr_bitfield_default },
	 { "AZ_INPUT_STREAM3_MEM_PWR_FORCE", 12, 13, &umr_bitfield_default },
	 { "AZ_INPUT_STREAM3_MEM_PWR_DIS", 14, 14, &umr_bitfield_default },
	 { "AZ_INPUT_STREAM4_MEM_PWR_FORCE", 15, 16, &umr_bitfield_default },
	 { "AZ_INPUT_STREAM4_MEM_PWR_DIS", 17, 17, &umr_bitfield_default },
	 { "AZ_INPUT_STREAM5_MEM_PWR_FORCE", 18, 19, &umr_bitfield_default },
	 { "AZ_INPUT_STREAM5_MEM_PWR_DIS", 20, 20, &umr_bitfield_default },
	 { "AZ_MEM_PWR_MODE_SEL", 28, 29, &umr_bitfield_default },
};
static struct umr_bitfield mmAZALIA_MEM_PWR_STATUS[] = {
	 { "AZ_MEM_PWR_STATE", 0, 1, &umr_bitfield_default },
	 { "AZ_INPUT_STREAM0_MEM_PWR_STATE", 2, 3, &umr_bitfield_default },
	 { "AZ_INPUT_STREAM1_MEM_PWR_STATE", 4, 5, &umr_bitfield_default },
	 { "AZ_INPUT_STREAM2_MEM_PWR_STATE", 6, 7, &umr_bitfield_default },
	 { "AZ_INPUT_STREAM3_MEM_PWR_STATE", 8, 9, &umr_bitfield_default },
	 { "AZ_INPUT_STREAM4_MEM_PWR_STATE", 10, 11, &umr_bitfield_default },
	 { "AZ_INPUT_STREAM5_MEM_PWR_STATE", 12, 13, &umr_bitfield_default },
};
static struct umr_bitfield mmAZALIA_F0_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID[] = {
	 { "AZALIA_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmAZALIA_F0_CODEC_ROOT_PARAMETER_REVISION_ID[] = {
	 { "AZALIA_CODEC_ROOT_PARAMETER_REVISION_ID", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmAZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL[] = {
	 { "HBR_CHANNEL_COUNT", 0, 2, &umr_bitfield_default },
	 { "COMPRESSED_CHANNEL_COUNT", 4, 6, &umr_bitfield_default },
};
static struct umr_bitfield mmAZALIA_F0_CODEC_RESYNC_FIFO_CONTROL[] = {
	 { "RESYNC_FIFO_STARTUP_KEEPOUT_WINDOW", 0, 5, &umr_bitfield_default },
};
static struct umr_bitfield mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_GROUP_TYPE[] = {
	 { "AZALIA_CODEC_FUNCTION_PARAMETER_GROUP_TYPE", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES[] = {
	 { "AUDIO_RATE_CAPABILITIES", 0, 11, &umr_bitfield_default },
	 { "AUDIO_BIT_CAPABILITIES", 16, 20, &umr_bitfield_default },
};
static struct umr_bitfield mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS[] = {
	 { "AZALIA_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES[] = {
	 { "AZALIA_CODEC_FUNCTION_PARAMETER_POWER_STATES", 0, 29, &umr_bitfield_default },
	 { "CLKSTOP", 30, 30, &umr_bitfield_default },
	 { "EPSS", 31, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmAZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE[] = {
	 { "POWER_STATE_SET", 0, 3, &umr_bitfield_default },
	 { "POWER_STATE_ACT", 4, 7, &umr_bitfield_default },
	 { "CLKSTOPOK", 9, 9, &umr_bitfield_default },
	 { "POWER_STATE_SETTINGS_RESET", 10, 10, &umr_bitfield_default },
};
static struct umr_bitfield mmAZALIA_F0_CODEC_FUNCTION_CONTROL_RESET[] = {
	 { "CODEC_RESET", 0, 0, &umr_bitfield_default },
};
static struct umr_bitfield mmAZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID[] = {
	 { "SUBSYSTEM_ID_BYTE0", 0, 7, &umr_bitfield_default },
	 { "SUBSYSTEM_ID_BYTE1", 8, 15, &umr_bitfield_default },
	 { "SUBSYSTEM_ID_BYTE2", 16, 23, &umr_bitfield_default },
	 { "SUBSYSTEM_ID_BYTE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmAZALIA_F0_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION[] = {
	 { "CONVERTER_SYNCHRONIZATION", 0, 7, &umr_bitfield_default },
};
static struct umr_bitfield mmCC_RCU_DC_AUDIO_PORT_CONNECTIVITY[] = {
	 { "PORT_CONNECTIVITY", 0, 2, &umr_bitfield_default },
	 { "PORT_CONNECTIVITY_OVERRIDE_ENABLE", 4, 4, &umr_bitfield_default },
};
static struct umr_bitfield mmCC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY[] = {
	 { "INPUT_PORT_CONNECTIVITY", 0, 2, &umr_bitfield_default },
	 { "INPUT_PORT_CONNECTIVITY_OVERRIDE_ENABLE", 4, 4, &umr_bitfield_default },
};
static struct umr_bitfield mmAZALIA_F0_GTC_GROUP_OFFSET0[] = {
	 { "GTC_GROUP_OFFSET0", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmAZALIA_F0_GTC_GROUP_OFFSET1[] = {
	 { "GTC_GROUP_OFFSET1", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmAZALIA_F0_GTC_GROUP_OFFSET2[] = {
	 { "GTC_GROUP_OFFSET2", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmAZALIA_F0_GTC_GROUP_OFFSET3[] = {
	 { "GTC_GROUP_OFFSET3", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmAZALIA_F0_GTC_GROUP_OFFSET4[] = {
	 { "GTC_GROUP_OFFSET4", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmAZALIA_F0_GTC_GROUP_OFFSET5[] = {
	 { "GTC_GROUP_OFFSET5", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmAZALIA_F0_GTC_GROUP_OFFSET6[] = {
	 { "GTC_GROUP_OFFSET6", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmREG_DC_AUDIO_PORT_CONNECTIVITY[] = {
	 { "REG_PORT_CONNECTIVITY", 0, 2, &umr_bitfield_default },
	 { "REG_PORT_CONNECTIVITY_OVERRIDE_ENABLE", 4, 4, &umr_bitfield_default },
};
static struct umr_bitfield mmREG_DC_AUDIO_INPUT_PORT_CONNECTIVITY[] = {
	 { "REG_INPUT_PORT_CONNECTIVITY", 0, 2, &umr_bitfield_default },
	 { "REG_INPUT_PORT_CONNECTIVITY_OVERRIDE_ENABLE", 4, 4, &umr_bitfield_default },
};
static struct umr_bitfield mmAZF0STREAM8_AZALIA_STREAM_INDEX[] = {
	 { "AZALIA_STREAM_REG_INDEX", 0, 7, &umr_bitfield_default },
	 { "AZALIA_STREAM_REG_WRITE_EN", 8, 8, &umr_bitfield_default },
};
static struct umr_bitfield mmAZF0STREAM8_AZALIA_STREAM_DATA[] = {
	 { "AZALIA_STREAM_REG_DATA", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmAZF0STREAM9_AZALIA_STREAM_INDEX[] = {
	 { "AZALIA_STREAM_REG_INDEX", 0, 7, &umr_bitfield_default },
	 { "AZALIA_STREAM_REG_WRITE_EN", 8, 8, &umr_bitfield_default },
};
static struct umr_bitfield mmAZF0STREAM9_AZALIA_STREAM_DATA[] = {
	 { "AZALIA_STREAM_REG_DATA", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmAZF0STREAM10_AZALIA_STREAM_INDEX[] = {
	 { "AZALIA_STREAM_REG_INDEX", 0, 7, &umr_bitfield_default },
	 { "AZALIA_STREAM_REG_WRITE_EN", 8, 8, &umr_bitfield_default },
};
static struct umr_bitfield mmAZF0STREAM10_AZALIA_STREAM_DATA[] = {
	 { "AZALIA_STREAM_REG_DATA", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmAZF0STREAM11_AZALIA_STREAM_INDEX[] = {
	 { "AZALIA_STREAM_REG_INDEX", 0, 7, &umr_bitfield_default },
	 { "AZALIA_STREAM_REG_WRITE_EN", 8, 8, &umr_bitfield_default },
};
static struct umr_bitfield mmAZF0STREAM11_AZALIA_STREAM_DATA[] = {
	 { "AZALIA_STREAM_REG_DATA", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmAZF0STREAM12_AZALIA_STREAM_INDEX[] = {
	 { "AZALIA_STREAM_REG_INDEX", 0, 7, &umr_bitfield_default },
	 { "AZALIA_STREAM_REG_WRITE_EN", 8, 8, &umr_bitfield_default },
};
static struct umr_bitfield mmAZF0STREAM12_AZALIA_STREAM_DATA[] = {
	 { "AZALIA_STREAM_REG_DATA", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmAZF0STREAM13_AZALIA_STREAM_INDEX[] = {
	 { "AZALIA_STREAM_REG_INDEX", 0, 7, &umr_bitfield_default },
	 { "AZALIA_STREAM_REG_WRITE_EN", 8, 8, &umr_bitfield_default },
};
static struct umr_bitfield mmAZF0STREAM13_AZALIA_STREAM_DATA[] = {
	 { "AZALIA_STREAM_REG_DATA", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmAZF0STREAM14_AZALIA_STREAM_INDEX[] = {
	 { "AZALIA_STREAM_REG_INDEX", 0, 7, &umr_bitfield_default },
	 { "AZALIA_STREAM_REG_WRITE_EN", 8, 8, &umr_bitfield_default },
};
static struct umr_bitfield mmAZF0STREAM14_AZALIA_STREAM_DATA[] = {
	 { "AZALIA_STREAM_REG_DATA", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmAZF0STREAM15_AZALIA_STREAM_INDEX[] = {
	 { "AZALIA_STREAM_REG_INDEX", 0, 7, &umr_bitfield_default },
	 { "AZALIA_STREAM_REG_WRITE_EN", 8, 8, &umr_bitfield_default },
};
static struct umr_bitfield mmAZF0STREAM15_AZALIA_STREAM_DATA[] = {
	 { "AZALIA_STREAM_REG_DATA", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX[] = {
	 { "AZALIA_INPUT_ENDPOINT_REG_INDEX", 0, 13, &umr_bitfield_default },
};
static struct umr_bitfield mmAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA[] = {
	 { "AZALIA_INPUT_ENDPOINT_REG_DATA", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX[] = {
	 { "AZALIA_INPUT_ENDPOINT_REG_INDEX", 0, 13, &umr_bitfield_default },
};
static struct umr_bitfield mmAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA[] = {
	 { "AZALIA_INPUT_ENDPOINT_REG_DATA", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX[] = {
	 { "AZALIA_INPUT_ENDPOINT_REG_INDEX", 0, 13, &umr_bitfield_default },
};
static struct umr_bitfield mmAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA[] = {
	 { "AZALIA_INPUT_ENDPOINT_REG_DATA", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX[] = {
	 { "AZALIA_INPUT_ENDPOINT_REG_INDEX", 0, 13, &umr_bitfield_default },
};
static struct umr_bitfield mmAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA[] = {
	 { "AZALIA_INPUT_ENDPOINT_REG_DATA", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX[] = {
	 { "AZALIA_INPUT_ENDPOINT_REG_INDEX", 0, 13, &umr_bitfield_default },
};
static struct umr_bitfield mmAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA[] = {
	 { "AZALIA_INPUT_ENDPOINT_REG_DATA", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX[] = {
	 { "AZALIA_INPUT_ENDPOINT_REG_INDEX", 0, 13, &umr_bitfield_default },
};
static struct umr_bitfield mmAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA[] = {
	 { "AZALIA_INPUT_ENDPOINT_REG_DATA", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX[] = {
	 { "AZALIA_INPUT_ENDPOINT_REG_INDEX", 0, 13, &umr_bitfield_default },
};
static struct umr_bitfield mmAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA[] = {
	 { "AZALIA_INPUT_ENDPOINT_REG_DATA", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX[] = {
	 { "AZALIA_INPUT_ENDPOINT_REG_INDEX", 0, 13, &umr_bitfield_default },
};
static struct umr_bitfield mmAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA[] = {
	 { "AZALIA_INPUT_ENDPOINT_REG_DATA", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCHUBBUB_SDPIF_CFG0[] = {
	 { "SDPIF_NO_OUTSTANDING_REQ", 0, 0, &umr_bitfield_default },
	 { "SDPIF_PORT_STATUS", 1, 2, &umr_bitfield_default },
	 { "SDPIF_DATA_RESPONSE_STATUS", 3, 5, &umr_bitfield_default },
	 { "SDPIF_REQ_CREDIT_ERROR", 6, 6, &umr_bitfield_default },
	 { "SDPIF_DATA_RESPONSE_STATUS_CLEAR", 7, 7, &umr_bitfield_default },
	 { "SDPIF_REQ_CREDIT_ERROR_CLEAR", 8, 8, &umr_bitfield_default },
	 { "SDPIF_FLUSH_REQ_CREDIT_EN", 9, 9, &umr_bitfield_default },
	 { "SDPIF_REQ_CREDIT_EN", 10, 10, &umr_bitfield_default },
	 { "SDPIF_PORT_CONTROL", 11, 11, &umr_bitfield_default },
	 { "SDPIF_UNIT_ID_BITMASK", 12, 19, &umr_bitfield_default },
	 { "SDPIF_CREDIT_DISCONNECT_DELAY", 20, 25, &umr_bitfield_default },
};
static struct umr_bitfield mmDCHUBBUB_SDPIF_CFG1[] = {
	 { "SDPIF_INSIDE_FB_IO", 0, 0, &umr_bitfield_default },
	 { "SDPIF_INSIDE_FB_VC", 1, 3, &umr_bitfield_default },
	 { "SDPIF_OUTSIDE_FB_IO", 4, 4, &umr_bitfield_default },
	 { "SDPIF_OUTSIDE_FB_VC", 5, 7, &umr_bitfield_default },
};
static struct umr_bitfield mmDCHUBBUB_FORCE_IO_STATUS_0[] = {
	 { "SDPIF_FORCE_IO_STATUS", 0, 0, &umr_bitfield_default },
	 { "SDPIF_FORCE_IO_STATUS_STICKY", 1, 1, &umr_bitfield_default },
	 { "SDPIF_FORCE_IO_STATUS_CLEAR", 2, 2, &umr_bitfield_default },
	 { "SDPIF_FORCE_IO_STATUS_PIPE_ID", 3, 6, &umr_bitfield_default },
	 { "SDPIF_FORCE_IO_STATUS_REQUEST_TYPE", 7, 9, &umr_bitfield_default },
	 { "SDPIF_FORCE_IO_STATUS_ADDR_LO", 10, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCHUBBUB_FORCE_IO_STATUS_1[] = {
	 { "SDPIF_FORCE_IO_STATUS_ADDR_HI", 0, 20, &umr_bitfield_default },
};
static struct umr_bitfield mmDCHUBBUB_SDPIF_FB_BASE[] = {
	 { "SDPIF_FB_BASE", 0, 23, &umr_bitfield_default },
};
static struct umr_bitfield mmDCHUBBUB_SDPIF_FB_TOP[] = {
	 { "SDPIF_FB_TOP", 0, 23, &umr_bitfield_default },
};
static struct umr_bitfield mmDCHUBBUB_SDPIF_FB_OFFSET[] = {
	 { "SDPIF_FB_OFFSET", 0, 23, &umr_bitfield_default },
};
static struct umr_bitfield mmDCHUBBUB_SDPIF_AGP_BOT[] = {
	 { "SDPIF_AGP_BOT", 0, 25, &umr_bitfield_default },
};
static struct umr_bitfield mmDCHUBBUB_SDPIF_AGP_TOP[] = {
	 { "SDPIF_AGP_TOP", 0, 25, &umr_bitfield_default },
};
static struct umr_bitfield mmDCHUBBUB_SDPIF_AGP_BASE[] = {
	 { "SDPIF_AGP_BASE", 0, 25, &umr_bitfield_default },
};
static struct umr_bitfield mmDCHUBBUB_SDPIF_APER_BASE[] = {
	 { "SDPIF_APER_BASE", 0, 27, &umr_bitfield_default },
	 { "SDPIF_LOCK_DRAM_REGS", 28, 28, &umr_bitfield_default },
};
static struct umr_bitfield mmDCHUBBUB_SDPIF_APER_TOP[] = {
	 { "SDPIF_APER_TOP", 0, 27, &umr_bitfield_default },
};
static struct umr_bitfield mmDCHUBBUB_SDPIF_APER_DEF_0[] = {
	 { "SDPIF_APER_DEF_0", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCHUBBUB_SDPIF_APER_DEF_1[] = {
	 { "SDPIF_APER_DEF_1", 0, 3, &umr_bitfield_default },
};
static struct umr_bitfield mmDCHUBBUB_SDPIF_MMIO_CNTRL_0[] = {
	 { "SDPIF_IOMMU_EN", 0, 0, &umr_bitfield_default },
};
static struct umr_bitfield mmDCHUBBUB_SDPIF_MMIO_CNTRL_1[] = {
	 { "SDPIF_MARC_EN", 8, 8, &umr_bitfield_default },
};
static struct umr_bitfield mmDCHUBBUB_SDPIF_MMIO_CNTRL_W[] = {
	 { "SDPIF_GMC_IOMMU_BYPASS", 13, 13, &umr_bitfield_default },
};
static struct umr_bitfield mmDCHUBBUB_SDPIF_MARC_BASE_LO_0[] = {
	 { "SDPIF_MARC_BASE_LO_0", 12, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCHUBBUB_SDPIF_MARC_BASE_HI_0[] = {
	 { "SDPIF_MARC_BASE_HI_0", 0, 15, &umr_bitfield_default },
};
static struct umr_bitfield mmDCHUBBUB_SDPIF_MARC_RELOC_LO_0[] = {
	 { "SDPIF_MARC_EN_0", 0, 0, &umr_bitfield_default },
	 { "SDPIF_MARC_RELOC_LO_0", 12, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCHUBBUB_SDPIF_MARC_RELOC_HI_0[] = {
	 { "SDPIF_MARC_RELOC_HI_0", 0, 15, &umr_bitfield_default },
};
static struct umr_bitfield mmDCHUBBUB_SDPIF_MARC_LENGTH_LO_0[] = {
	 { "SDPIF_MARC_LENGTH_LO_0", 12, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCHUBBUB_SDPIF_MARC_LENGTH_HI_0[] = {
	 { "SDPIF_MARC_LENGTH_HI_0", 0, 15, &umr_bitfield_default },
};
static struct umr_bitfield mmDCHUBBUB_SDPIF_MARC_BASE_LO_1[] = {
	 { "SDPIF_MARC_BASE_LO_1", 12, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCHUBBUB_SDPIF_MARC_BASE_HI_1[] = {
	 { "SDPIF_MARC_BASE_HI_1", 0, 15, &umr_bitfield_default },
};
static struct umr_bitfield mmDCHUBBUB_SDPIF_MARC_RELOC_LO_1[] = {
	 { "SDPIF_MARC_EN_1", 0, 0, &umr_bitfield_default },
	 { "SDPIF_MARC_RELOC_LO_1", 12, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCHUBBUB_SDPIF_MARC_RELOC_HI_1[] = {
	 { "SDPIF_MARC_RELOC_HI_1", 0, 15, &umr_bitfield_default },
};
static struct umr_bitfield mmDCHUBBUB_SDPIF_MARC_LENGTH_LO_1[] = {
	 { "SDPIF_MARC_LENGTH_LO_1", 12, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCHUBBUB_SDPIF_MARC_LENGTH_HI_1[] = {
	 { "SDPIF_MARC_LENGTH_HI_1", 0, 15, &umr_bitfield_default },
};
static struct umr_bitfield mmDCHUBBUB_SDPIF_MARC_BASE_LO_2[] = {
	 { "SDPIF_MARC_BASE_LO_2", 12, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCHUBBUB_SDPIF_MARC_BASE_HI_2[] = {
	 { "SDPIF_MARC_BASE_HI_2", 0, 15, &umr_bitfield_default },
};
static struct umr_bitfield mmDCHUBBUB_SDPIF_MARC_RELOC_LO_2[] = {
	 { "SDPIF_MARC_EN_2", 0, 0, &umr_bitfield_default },
	 { "SDPIF_MARC_RELOC_LO_2", 12, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCHUBBUB_SDPIF_MARC_RELOC_HI_2[] = {
	 { "SDPIF_MARC_RELOC_HI_2", 0, 15, &umr_bitfield_default },
};
static struct umr_bitfield mmDCHUBBUB_SDPIF_MARC_LENGTH_LO_2[] = {
	 { "SDPIF_MARC_LENGTH_LO_2", 12, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCHUBBUB_SDPIF_MARC_LENGTH_HI_2[] = {
	 { "SDPIF_MARC_LENGTH_HI_2", 0, 15, &umr_bitfield_default },
};
static struct umr_bitfield mmDCHUBBUB_SDPIF_MARC_BASE_LO_3[] = {
	 { "SDPIF_MARC_BASE_LO_3", 12, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCHUBBUB_SDPIF_MARC_BASE_HI_3[] = {
	 { "SDPIF_MARC_BASE_HI_3", 0, 15, &umr_bitfield_default },
};
static struct umr_bitfield mmDCHUBBUB_SDPIF_MARC_RELOC_LO_3[] = {
	 { "SDPIF_MARC_EN_3", 0, 0, &umr_bitfield_default },
	 { "SDPIF_MARC_RELOC_LO_3", 12, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCHUBBUB_SDPIF_MARC_RELOC_HI_3[] = {
	 { "SDPIF_MARC_RELOC_HI_3", 0, 15, &umr_bitfield_default },
};
static struct umr_bitfield mmDCHUBBUB_SDPIF_MARC_LENGTH_LO_3[] = {
	 { "SDPIF_MARC_LENGTH_LO_3", 12, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCHUBBUB_SDPIF_MARC_LENGTH_HI_3[] = {
	 { "SDPIF_MARC_LENGTH_HI_3", 0, 15, &umr_bitfield_default },
};
static struct umr_bitfield mmDCHUBBUB_SDPIF_PIPE_SEC_LVL[] = {
	 { "SDPIF_PIPE0_SEC_LVL", 0, 2, &umr_bitfield_default },
	 { "SDPIF_PIPE1_SEC_LVL", 3, 5, &umr_bitfield_default },
	 { "SDPIF_PIPE2_SEC_LVL", 6, 8, &umr_bitfield_default },
	 { "SDPIF_PIPE3_SEC_LVL", 9, 11, &umr_bitfield_default },
};
static struct umr_bitfield mmDCHUBBUB_SDPIF_MEM_PWR_CTRL[] = {
	 { "DCHUBBUB_SDPIF_MEM_PWR_FORCE", 0, 1, &umr_bitfield_default },
	 { "DCHUBBUB_SDPIF_MEM_PWR_DIS", 2, 2, &umr_bitfield_default },
};
static struct umr_bitfield mmDCHUBBUB_SDPIF_MEM_PWR_STATUS[] = {
	 { "DCHUBBUB_SDPIF_MEM_PWR_STATE", 0, 1, &umr_bitfield_default },
};
static struct umr_bitfield mmDCHUBBUB_RET_PATH_DCC_CFG[] = {
	 { "DCC_VIDEO_FORMAT_EN", 0, 0, &umr_bitfield_default },
};
static struct umr_bitfield mmDCHUBBUB_RET_PATH_DCC_CFG0_0[] = {
	 { "DCC_CFG0_CONSTANT_0", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCHUBBUB_RET_PATH_DCC_CFG0_1[] = {
	 { "DCC_CFG0_CONSTANT_1", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCHUBBUB_RET_PATH_DCC_CFG1_0[] = {
	 { "DCC_CFG1_CONSTANT_0", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCHUBBUB_RET_PATH_DCC_CFG1_1[] = {
	 { "DCC_CFG1_CONSTANT_1", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCHUBBUB_RET_PATH_DCC_CFG2_0[] = {
	 { "DCC_CFG2_CONSTANT_0", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCHUBBUB_RET_PATH_DCC_CFG2_1[] = {
	 { "DCC_CFG2_CONSTANT_1", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCHUBBUB_RET_PATH_DCC_CFG3_0[] = {
	 { "DCC_CFG3_CONSTANT_0", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCHUBBUB_RET_PATH_DCC_CFG3_1[] = {
	 { "DCC_CFG3_CONSTANT_1", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCHUBBUB_RET_PATH_DCC_CFG4_0[] = {
	 { "DCC_CFG4_CONSTANT_0", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCHUBBUB_RET_PATH_DCC_CFG4_1[] = {
	 { "DCC_CFG4_CONSTANT_1", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCHUBBUB_RET_PATH_DCC_CFG5_0[] = {
	 { "DCC_CFG5_CONSTANT_0", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCHUBBUB_RET_PATH_DCC_CFG5_1[] = {
	 { "DCC_CFG5_CONSTANT_1", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCHUBBUB_RET_PATH_DCC_CFG6_0[] = {
	 { "DCC_CFG6_CONSTANT_0", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCHUBBUB_RET_PATH_DCC_CFG6_1[] = {
	 { "DCC_CFG6_CONSTANT_1", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCHUBBUB_RET_PATH_DCC_CFG7_0[] = {
	 { "DCC_CFG7_CONSTANT_0", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCHUBBUB_RET_PATH_DCC_CFG7_1[] = {
	 { "DCC_CFG7_CONSTANT_1", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCHUBBUB_RET_PATH_MEM_PWR_CTRL[] = {
	 { "DCHUBBUB_RET_PATH_MEM_PWR_FORCE", 0, 1, &umr_bitfield_default },
	 { "DCHUBBUB_RET_PATH_MEM_PWR_DIS", 2, 2, &umr_bitfield_default },
};
static struct umr_bitfield mmDCHUBBUB_RET_PATH_MEM_PWR_STATUS[] = {
	 { "DCHUBBUB_RET_PATH_MEM_PWR_STATE", 0, 1, &umr_bitfield_default },
};
static struct umr_bitfield mmDCHUBBUB_CRC_CTRL[] = {
	 { "DCHUBBUB_CRC_EN", 0, 0, &umr_bitfield_default },
	 { "DCHUBBUB_CRC_CONT_EN", 1, 1, &umr_bitfield_default },
	 { "DCHUBBUB_CRC0_ONE_SHOT_PENDING", 2, 2, &umr_bitfield_default },
	 { "DCHUBBUB_CRC1_ONE_SHOT_PENDING", 3, 3, &umr_bitfield_default },
	 { "DCHUBBUB_CRC0_SRC_SEL", 4, 5, &umr_bitfield_default },
	 { "DCHUBBUB_CRC1_SRC_SEL", 6, 7, &umr_bitfield_default },
	 { "DCHUBBUB_CRC_PIPE_SEL", 8, 11, &umr_bitfield_default },
	 { "DCHUBBUB_CRC_SURF_SEL", 12, 13, &umr_bitfield_default },
	 { "DCHUBBUB_CRC_DATA_SRC_SEL", 14, 14, &umr_bitfield_default },
};
static struct umr_bitfield mmDCHUBBUB_CRC0_VAL_R_G[] = {
	 { "DCHUBBUB_CRC0_R_CR", 0, 15, &umr_bitfield_default },
	 { "DCHUBBUB_CRC0_G_Y", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCHUBBUB_CRC0_VAL_B_A[] = {
	 { "DCHUBBUB_CRC0_B_CB", 0, 15, &umr_bitfield_default },
	 { "DCHUBBUB_CRC0_ALPHA", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCHUBBUB_CRC1_VAL_R_G[] = {
	 { "DCHUBBUB_CRC1_R_CR", 0, 15, &umr_bitfield_default },
	 { "DCHUBBUB_CRC1_G_Y", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCHUBBUB_CRC1_VAL_B_A[] = {
	 { "DCHUBBUB_CRC1_B_CB", 0, 15, &umr_bitfield_default },
	 { "DCHUBBUB_CRC1_ALPHA", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCHUBBUB_ARB_DF_REQ_OUTSTAND[] = {
	 { "DCHUBBUB_ARB_MAX_REQ_OUTSTAND", 0, 8, &umr_bitfield_default },
	 { "DCHUBBUB_ARB_MIN_REQ_OUTSTAND", 16, 24, &umr_bitfield_default },
};
static struct umr_bitfield mmDCHUBBUB_ARB_SAT_LEVEL[] = {
	 { "DCHUBBUB_ARB_SAT_LEVEL", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCHUBBUB_ARB_QOS_FORCE[] = {
	 { "DCHUBBUB_ARB_QOS_FORCE_VALUE", 0, 3, &umr_bitfield_default },
	 { "DCHUBBUB_ARB_QOS_FORCE_ENABLE", 8, 8, &umr_bitfield_default },
};
static struct umr_bitfield mmDCHUBBUB_ARB_DRAM_STATE_CNTL[] = {
	 { "DCHUBBUB_ARB_ALLOW_SELF_REFRESH_FORCE_VALUE", 0, 0, &umr_bitfield_default },
	 { "DCHUBBUB_ARB_ALLOW_SELF_REFRESH_FORCE_ENABLE", 1, 1, &umr_bitfield_default },
	 { "DCHUBBUB_ARB_ALLOW_SELF_REFRESH_FORCED_CLEAR_DISABLE", 2, 2, &umr_bitfield_default },
	 { "DCHUBBUB_ARB_ALLOW_PSTATE_CHANGE_FORCE_VALUE", 4, 4, &umr_bitfield_default },
	 { "DCHUBBUB_ARB_ALLOW_PSTATE_CHANGE_FORCE_ENABLE", 5, 5, &umr_bitfield_default },
};
static struct umr_bitfield mmDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A[] = {
	 { "DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A", 0, 20, &umr_bitfield_default },
};
static struct umr_bitfield mmDCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_A[] = {
	 { "DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_A", 0, 20, &umr_bitfield_default },
};
static struct umr_bitfield mmDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A[] = {
	 { "DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A", 0, 20, &umr_bitfield_default },
};
static struct umr_bitfield mmDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A[] = {
	 { "DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A", 0, 20, &umr_bitfield_default },
};
static struct umr_bitfield mmDCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A[] = {
	 { "DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A", 0, 20, &umr_bitfield_default },
};
static struct umr_bitfield mmDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B[] = {
	 { "DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B", 0, 20, &umr_bitfield_default },
};
static struct umr_bitfield mmDCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_B[] = {
	 { "DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_B", 0, 20, &umr_bitfield_default },
};
static struct umr_bitfield mmDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B[] = {
	 { "DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B", 0, 20, &umr_bitfield_default },
};
static struct umr_bitfield mmDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B[] = {
	 { "DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B", 0, 20, &umr_bitfield_default },
};
static struct umr_bitfield mmDCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B[] = {
	 { "DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B", 0, 20, &umr_bitfield_default },
};
static struct umr_bitfield mmDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C[] = {
	 { "DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C", 0, 20, &umr_bitfield_default },
};
static struct umr_bitfield mmDCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_C[] = {
	 { "DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_C", 0, 20, &umr_bitfield_default },
};
static struct umr_bitfield mmDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C[] = {
	 { "DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C", 0, 20, &umr_bitfield_default },
};
static struct umr_bitfield mmDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C[] = {
	 { "DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C", 0, 20, &umr_bitfield_default },
};
static struct umr_bitfield mmDCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_C[] = {
	 { "DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_C", 0, 20, &umr_bitfield_default },
};
static struct umr_bitfield mmDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D[] = {
	 { "DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D", 0, 20, &umr_bitfield_default },
};
static struct umr_bitfield mmDCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_D[] = {
	 { "DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_D", 0, 20, &umr_bitfield_default },
};
static struct umr_bitfield mmDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D[] = {
	 { "DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D", 0, 20, &umr_bitfield_default },
};
static struct umr_bitfield mmDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D[] = {
	 { "DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D", 0, 20, &umr_bitfield_default },
};
static struct umr_bitfield mmDCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D[] = {
	 { "DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D", 0, 20, &umr_bitfield_default },
};
static struct umr_bitfield mmDCHUBBUB_ARB_WATERMARK_CHANGE_CNTL[] = {
	 { "DCHUBBUB_ARB_WATERMARK_CHANGE_SELECT", 0, 1, &umr_bitfield_default },
	 { "DCHUBBUB_ARB_WATERMARK_CHANGE_DONE_INTERRUPT_DISABLE", 4, 4, &umr_bitfield_default },
	 { "DCHUBBUB_ARB_WATERMARK_CHANGE_DONE_INTERRUPT_STATUS", 5, 5, &umr_bitfield_default },
	 { "DCHUBBUB_ARB_WATERMARK_CHANGE_DONE_INTERRUPT_ACK", 6, 6, &umr_bitfield_default },
	 { "DCHUBBUB_ARB_WATERMARK_CHANGE_REQUEST", 8, 8, &umr_bitfield_default },
};
static struct umr_bitfield mmDCHUBBUB_ARB_TIMEOUT_ENABLE[] = {
	 { "DCHUBBUB_ARB_TIMEOUT_ENABLE", 0, 0, &umr_bitfield_default },
};
static struct umr_bitfield mmDCHUBBUB_GLOBAL_TIMER_CNTL[] = {
	 { "DCHUBBUB_GLOBAL_TIMER_REFDIV", 0, 3, &umr_bitfield_default },
	 { "DCHUBBUB_GLOBAL_TIMER_ENABLE", 12, 12, &umr_bitfield_default },
	 { "DCHUBBUB_GLOBAL_TIMER_INIT", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSURFACE_CHECK0_ADDRESS_LSB[] = {
	 { "SURFACE_CHECK0_ADDRESS_LSB", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSURFACE_CHECK0_ADDRESS_MSB[] = {
	 { "SURFACE_CHECK0_ADDRESS_MSB", 0, 15, &umr_bitfield_default },
	 { "CHECKER0_SURFACE_INUSE", 31, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSURFACE_CHECK1_ADDRESS_LSB[] = {
	 { "SURFACE_CHECK1_ADDRESS_LSB", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSURFACE_CHECK1_ADDRESS_MSB[] = {
	 { "SURFACE_CHECK1_ADDRESS_MSB", 0, 15, &umr_bitfield_default },
	 { "CHECKER1_SURFACE_INUSE", 31, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSURFACE_CHECK2_ADDRESS_LSB[] = {
	 { "SURFACE_CHECK2_ADDRESS_LSB", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSURFACE_CHECK2_ADDRESS_MSB[] = {
	 { "SURFACE_CHECK2_ADDRESS_MSB", 0, 15, &umr_bitfield_default },
	 { "CHECKER2_SURFACE_INUSE", 31, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSURFACE_CHECK3_ADDRESS_LSB[] = {
	 { "SURFACE_CHECK3_ADDRESS_LSB", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSURFACE_CHECK3_ADDRESS_MSB[] = {
	 { "SURFACE_CHECK3_ADDRESS_MSB", 0, 15, &umr_bitfield_default },
	 { "CHECKER3_SURFACE_INUSE", 31, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmVTG0_CONTROL[] = {
	 { "VTG0_FP2", 0, 14, &umr_bitfield_default },
	 { "VTG0_VCOUNT_INIT", 15, 29, &umr_bitfield_default },
	 { "VTG0_ENABLE", 31, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmVTG1_CONTROL[] = {
	 { "VTG1_FP2", 0, 14, &umr_bitfield_default },
	 { "VTG1_VCOUNT_INIT", 15, 29, &umr_bitfield_default },
	 { "VTG1_ENABLE", 31, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmVTG2_CONTROL[] = {
	 { "VTG2_FP2", 0, 14, &umr_bitfield_default },
	 { "VTG2_VCOUNT_INIT", 15, 29, &umr_bitfield_default },
	 { "VTG2_ENABLE", 31, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmVTG3_CONTROL[] = {
	 { "VTG3_FP2", 0, 14, &umr_bitfield_default },
	 { "VTG3_VCOUNT_INIT", 15, 29, &umr_bitfield_default },
	 { "VTG3_ENABLE", 31, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmVTG4_CONTROL[] = {
	 { "VTG4_FP2", 0, 14, &umr_bitfield_default },
	 { "VTG4_VCOUNT_INIT", 15, 29, &umr_bitfield_default },
	 { "VTG4_ENABLE", 31, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmVTG5_CONTROL[] = {
	 { "VTG5_FP2", 0, 14, &umr_bitfield_default },
	 { "VTG5_VCOUNT_INIT", 15, 29, &umr_bitfield_default },
	 { "VTG5_ENABLE", 31, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCHUBBUB_SOFT_RESET[] = {
	 { "DCHUBBUB_GLOBAL_SOFT_RESET", 0, 0, &umr_bitfield_default },
	 { "ALLOW_CSTATE_SOFT_RESET", 1, 1, &umr_bitfield_default },
	 { "GLBFLIP_SOFT_RESET", 4, 4, &umr_bitfield_default },
};
static struct umr_bitfield mmDCHUBBUB_CLOCK_CNTL[] = {
	 { "DCHUBBUB_TEST_CLK_SEL", 0, 4, &umr_bitfield_default },
	 { "DISPCLK_R_DCHUBBUB_GATE_DIS", 5, 5, &umr_bitfield_default },
	 { "DCFCLK_R_DCHUBBUB_GATE_DIS", 6, 6, &umr_bitfield_default },
};
static struct umr_bitfield mmDCFCLK_CNTL[] = {
	 { "DCFCLK_TURN_ON_DELAY", 0, 3, &umr_bitfield_default },
	 { "DCFCLK_TURN_OFF_DELAY", 4, 11, &umr_bitfield_default },
	 { "DCFCLK_GATE_DIS", 31, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL[] = {
	 { "DCHUBBUB_LATENCY_CNT_EN", 0, 0, &umr_bitfield_default },
	 { "ARB_LATENCY_PIPE_SEL", 3, 6, &umr_bitfield_default },
	 { "ARB_LATENCY_REQ_TYPE_SEL", 7, 9, &umr_bitfield_default },
	 { "DF_LATENCY_URGENT_ONLY", 10, 10, &umr_bitfield_default },
	 { "ROB_FIFO_LEVEL", 11, 20, &umr_bitfield_default },
	 { "ROB_MAX_FIFO_LEVEL", 21, 30, &umr_bitfield_default },
	 { "ROB_MAX_FIFO_LEVEL_RESET", 31, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL2[] = {
	 { "DCHUBBUB_LATENCY_FRAME_WIN_EN", 0, 0, &umr_bitfield_default },
	 { "DCHUBBUB_LATENCY_FRAME_WIN_SRC_SEL", 1, 3, &umr_bitfield_default },
	 { "DCHUBBUB_LATENCY_FRAME_WIN_DUR", 4, 11, &umr_bitfield_default },
	 { "LATENCY_SOURCE_SEL", 12, 14, &umr_bitfield_default },
};
static struct umr_bitfield mmDCHUBBUB_VLINE_SNAPSHOT[] = {
	 { "DCHUBBUB_VLINE_SNAPSHOT", 0, 0, &umr_bitfield_default },
};
static struct umr_bitfield mmDCHUBBUB_SPARE[] = {
	 { "DCHUBBUB_SPARE", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_PERFMON7_PERFCOUNTER_CNTL[] = {
	 { "PERFCOUNTER_EVENT_SEL", 0, 8, &umr_bitfield_default },
	 { "PERFCOUNTER_CVALUE_SEL", 9, 11, &umr_bitfield_default },
	 { "PERFCOUNTER_INC_MODE", 12, 14, &umr_bitfield_default },
	 { "PERFCOUNTER_HW_CNTL_SEL", 15, 15, &umr_bitfield_default },
	 { "PERFCOUNTER_RUNEN_MODE", 16, 16, &umr_bitfield_default },
	 { "PERFCOUNTER_CNTOFF_START_DIS", 22, 22, &umr_bitfield_default },
	 { "PERFCOUNTER_RESTART_EN", 23, 23, &umr_bitfield_default },
	 { "PERFCOUNTER_INT_EN", 24, 24, &umr_bitfield_default },
	 { "PERFCOUNTER_OFF_MASK", 25, 25, &umr_bitfield_default },
	 { "PERFCOUNTER_ACTIVE", 26, 26, &umr_bitfield_default },
	 { "PERFCOUNTER_CNTL_SEL", 29, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_PERFMON7_PERFCOUNTER_CNTL2[] = {
	 { "PERFCOUNTER_COUNTED_VALUE_TYPE", 0, 1, &umr_bitfield_default },
	 { "PERFCOUNTER_HW_STOP1_SEL", 2, 2, &umr_bitfield_default },
	 { "PERFCOUNTER_HW_STOP2_SEL", 3, 3, &umr_bitfield_default },
	 { "PERFCOUNTER_CNTOFF_SEL", 8, 13, &umr_bitfield_default },
	 { "PERFCOUNTER_CNTL2_SEL", 29, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_PERFMON7_PERFCOUNTER_STATE[] = {
	 { "PERFCOUNTER_CNT0_STATE", 0, 1, &umr_bitfield_default },
	 { "PERFCOUNTER_STATE_SEL0", 2, 2, &umr_bitfield_default },
	 { "PERFCOUNTER_CNT1_STATE", 4, 5, &umr_bitfield_default },
	 { "PERFCOUNTER_STATE_SEL1", 6, 6, &umr_bitfield_default },
	 { "PERFCOUNTER_CNT2_STATE", 8, 9, &umr_bitfield_default },
	 { "PERFCOUNTER_STATE_SEL2", 10, 10, &umr_bitfield_default },
	 { "PERFCOUNTER_CNT3_STATE", 12, 13, &umr_bitfield_default },
	 { "PERFCOUNTER_STATE_SEL3", 14, 14, &umr_bitfield_default },
	 { "PERFCOUNTER_CNT4_STATE", 16, 17, &umr_bitfield_default },
	 { "PERFCOUNTER_STATE_SEL4", 18, 18, &umr_bitfield_default },
	 { "PERFCOUNTER_CNT5_STATE", 20, 21, &umr_bitfield_default },
	 { "PERFCOUNTER_STATE_SEL5", 22, 22, &umr_bitfield_default },
	 { "PERFCOUNTER_CNT6_STATE", 24, 25, &umr_bitfield_default },
	 { "PERFCOUNTER_STATE_SEL6", 26, 26, &umr_bitfield_default },
	 { "PERFCOUNTER_CNT7_STATE", 28, 29, &umr_bitfield_default },
	 { "PERFCOUNTER_STATE_SEL7", 30, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_PERFMON7_PERFMON_CNTL[] = {
	 { "PERFMON_STATE", 0, 1, &umr_bitfield_default },
	 { "PERFMON_RPT_COUNT", 8, 27, &umr_bitfield_default },
	 { "PERFMON_CNTOFF_AND_OR", 28, 28, &umr_bitfield_default },
	 { "PERFMON_CNTOFF_INT_EN", 29, 29, &umr_bitfield_default },
	 { "PERFMON_CNTOFF_INT_STATUS", 30, 30, &umr_bitfield_default },
	 { "PERFMON_CNTOFF_INT_ACK", 31, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_PERFMON7_PERFMON_CNTL2[] = {
	 { "PERFMON_CNTOFF_INT_TYPE", 0, 0, &umr_bitfield_default },
	 { "PERFMON_CLK_ENABLE", 1, 1, &umr_bitfield_default },
	 { "PERFMON_RUN_ENABLE_START_SEL", 2, 9, &umr_bitfield_default },
	 { "PERFMON_RUN_ENABLE_STOP_SEL", 10, 17, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_PERFMON7_PERFMON_CVALUE_INT_MISC[] = {
	 { "PERFCOUNTER_INT0_STATUS", 0, 0, &umr_bitfield_default },
	 { "PERFCOUNTER_INT1_STATUS", 1, 1, &umr_bitfield_default },
	 { "PERFCOUNTER_INT2_STATUS", 2, 2, &umr_bitfield_default },
	 { "PERFCOUNTER_INT3_STATUS", 3, 3, &umr_bitfield_default },
	 { "PERFCOUNTER_INT4_STATUS", 4, 4, &umr_bitfield_default },
	 { "PERFCOUNTER_INT5_STATUS", 5, 5, &umr_bitfield_default },
	 { "PERFCOUNTER_INT6_STATUS", 6, 6, &umr_bitfield_default },
	 { "PERFCOUNTER_INT7_STATUS", 7, 7, &umr_bitfield_default },
	 { "PERFCOUNTER_INT0_ACK", 8, 8, &umr_bitfield_default },
	 { "PERFCOUNTER_INT1_ACK", 9, 9, &umr_bitfield_default },
	 { "PERFCOUNTER_INT2_ACK", 10, 10, &umr_bitfield_default },
	 { "PERFCOUNTER_INT3_ACK", 11, 11, &umr_bitfield_default },
	 { "PERFCOUNTER_INT4_ACK", 12, 12, &umr_bitfield_default },
	 { "PERFCOUNTER_INT5_ACK", 13, 13, &umr_bitfield_default },
	 { "PERFCOUNTER_INT6_ACK", 14, 14, &umr_bitfield_default },
	 { "PERFCOUNTER_INT7_ACK", 15, 15, &umr_bitfield_default },
	 { "PERFMON_CVALUE_HI", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_PERFMON7_PERFMON_CVALUE_LOW[] = {
	 { "PERFMON_CVALUE_LOW", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_PERFMON7_PERFMON_HI[] = {
	 { "PERFMON_HI", 0, 15, &umr_bitfield_default },
	 { "PERFMON_READ_SEL", 29, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_PERFMON7_PERFMON_LOW[] = {
	 { "PERFMON_LOW", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmHUBP0_DCSURF_SURFACE_CONFIG[] = {
	 { "SURFACE_PIXEL_FORMAT", 0, 6, &umr_bitfield_default },
	 { "ROTATION_ANGLE", 8, 9, &umr_bitfield_default },
	 { "H_MIRROR_EN", 10, 10, &umr_bitfield_default },
};
static struct umr_bitfield mmHUBP0_DCSURF_ADDR_CONFIG[] = {
	 { "NUM_PIPES", 0, 2, &umr_bitfield_default },
	 { "NUM_BANKS", 3, 5, &umr_bitfield_default },
	 { "PIPE_INTERLEAVE", 6, 7, &umr_bitfield_default },
	 { "NUM_SE", 8, 9, &umr_bitfield_default },
	 { "NUM_RB_PER_SE", 10, 11, &umr_bitfield_default },
	 { "MAX_COMPRESSED_FRAGS", 12, 13, &umr_bitfield_default },
};
static struct umr_bitfield mmHUBP0_DCSURF_TILING_CONFIG[] = {
	 { "SW_MODE", 0, 4, &umr_bitfield_default },
	 { "DIM_TYPE", 7, 8, &umr_bitfield_default },
	 { "META_LINEAR", 9, 9, &umr_bitfield_default },
	 { "RB_ALIGNED", 10, 10, &umr_bitfield_default },
	 { "PIPE_ALIGNED", 11, 11, &umr_bitfield_default },
};
static struct umr_bitfield mmHUBP0_DCSURF_PRI_VIEWPORT_START[] = {
	 { "PRI_VIEWPORT_X_START", 0, 13, &umr_bitfield_default },
	 { "PRI_VIEWPORT_Y_START", 16, 29, &umr_bitfield_default },
};
static struct umr_bitfield mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION[] = {
	 { "PRI_VIEWPORT_WIDTH", 0, 13, &umr_bitfield_default },
	 { "PRI_VIEWPORT_HEIGHT", 16, 29, &umr_bitfield_default },
};
static struct umr_bitfield mmHUBP0_DCSURF_PRI_VIEWPORT_START_C[] = {
	 { "PRI_VIEWPORT_X_START_C", 0, 13, &umr_bitfield_default },
	 { "PRI_VIEWPORT_Y_START_C", 16, 29, &umr_bitfield_default },
};
static struct umr_bitfield mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_C[] = {
	 { "PRI_VIEWPORT_WIDTH_C", 0, 13, &umr_bitfield_default },
	 { "PRI_VIEWPORT_HEIGHT_C", 16, 29, &umr_bitfield_default },
};
static struct umr_bitfield mmHUBP0_DCSURF_SEC_VIEWPORT_START[] = {
	 { "SEC_VIEWPORT_X_START", 0, 13, &umr_bitfield_default },
	 { "SEC_VIEWPORT_Y_START", 16, 29, &umr_bitfield_default },
};
static struct umr_bitfield mmHUBP0_DCSURF_SEC_VIEWPORT_DIMENSION[] = {
	 { "SEC_VIEWPORT_WIDTH", 0, 13, &umr_bitfield_default },
	 { "SEC_VIEWPORT_HEIGHT", 16, 29, &umr_bitfield_default },
};
static struct umr_bitfield mmHUBP0_DCSURF_SEC_VIEWPORT_START_C[] = {
	 { "SEC_VIEWPORT_X_START_C", 0, 13, &umr_bitfield_default },
	 { "SEC_VIEWPORT_Y_START_C", 16, 29, &umr_bitfield_default },
};
static struct umr_bitfield mmHUBP0_DCSURF_SEC_VIEWPORT_DIMENSION_C[] = {
	 { "SEC_VIEWPORT_WIDTH_C", 0, 13, &umr_bitfield_default },
	 { "SEC_VIEWPORT_HEIGHT_C", 16, 29, &umr_bitfield_default },
};
static struct umr_bitfield mmHUBP0_DCHUBP_REQ_SIZE_CONFIG[] = {
	 { "SWATH_HEIGHT", 0, 2, &umr_bitfield_default },
	 { "PTE_ROW_HEIGHT_LINEAR", 4, 6, &umr_bitfield_default },
	 { "CHUNK_SIZE", 8, 10, &umr_bitfield_default },
	 { "MIN_CHUNK_SIZE", 11, 12, &umr_bitfield_default },
	 { "META_CHUNK_SIZE", 16, 17, &umr_bitfield_default },
	 { "MIN_META_CHUNK_SIZE", 18, 19, &umr_bitfield_default },
	 { "DPTE_GROUP_SIZE", 20, 22, &umr_bitfield_default },
	 { "MPTE_GROUP_SIZE", 24, 26, &umr_bitfield_default },
};
static struct umr_bitfield mmHUBP0_DCHUBP_REQ_SIZE_CONFIG_C[] = {
	 { "SWATH_HEIGHT_C", 0, 2, &umr_bitfield_default },
	 { "PTE_ROW_HEIGHT_LINEAR_C", 4, 6, &umr_bitfield_default },
	 { "CHUNK_SIZE_C", 8, 10, &umr_bitfield_default },
	 { "MIN_CHUNK_SIZE_C", 11, 12, &umr_bitfield_default },
	 { "META_CHUNK_SIZE_C", 16, 17, &umr_bitfield_default },
	 { "MIN_META_CHUNK_SIZE_C", 18, 19, &umr_bitfield_default },
	 { "DPTE_GROUP_SIZE_C", 20, 22, &umr_bitfield_default },
	 { "MPTE_GROUP_SIZE_C", 24, 26, &umr_bitfield_default },
};
static struct umr_bitfield mmHUBP0_DCHUBP_CNTL[] = {
	 { "HUBP_BLANK_EN", 0, 0, &umr_bitfield_default },
	 { "HUBP_NO_OUTSTANDING_REQ", 1, 1, &umr_bitfield_default },
	 { "HUBP_DISABLE", 2, 2, &umr_bitfield_default },
	 { "HUBP_IN_BLANK", 3, 3, &umr_bitfield_default },
	 { "HUBP_VTG_SEL", 4, 7, &umr_bitfield_default },
	 { "HUBP_TTU_DISABLE", 12, 12, &umr_bitfield_default },
	 { "HUBP_TTU_MODE", 13, 15, &umr_bitfield_default },
	 { "HUBP_UNDERFLOW_STATUS", 28, 30, &umr_bitfield_default },
	 { "HUBP_UNDERFLOW_CLEAR", 31, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmHUBP0_HUBP_CLK_CNTL[] = {
	 { "HUBP_CLOCK_ENABLE", 0, 0, &umr_bitfield_default },
	 { "HUBP_DISPCLK_R_GATE_DIS", 4, 4, &umr_bitfield_default },
	 { "HUBP_DPPCLK_G_GATE_DIS", 8, 8, &umr_bitfield_default },
	 { "HUBP_DCFCLK_R_GATE_DIS", 12, 12, &umr_bitfield_default },
	 { "HUBP_DCFCLK_G_GATE_DIS", 16, 16, &umr_bitfield_default },
	 { "HUBP_DISPCLK_R_CLOCK_ON", 20, 20, &umr_bitfield_default },
	 { "HUBP_DPPCLK_G_CLOCK_ON", 21, 21, &umr_bitfield_default },
	 { "HUBP_DCFCLK_R_CLOCK_ON", 22, 22, &umr_bitfield_default },
	 { "HUBP_DCFCLK_G_CLOCK_ON", 23, 23, &umr_bitfield_default },
	 { "HUBP_TEST_CLK_SEL", 28, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmHUBP0_DCHUBP_VMPG_CONFIG[] = {
	 { "VMPG_SIZE", 0, 0, &umr_bitfield_default },
};
static struct umr_bitfield mmHUBP0_HUBPREQ_DEBUG_DB[] = {
	 { "HUBPREQ_DEBUG", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmHUBP0_HUBP_MEASURE_WIN_CTRL_DCFCLK[] = {
	 { "HUBP_MEASURE_WIN_EN_DCFCLK", 0, 0, &umr_bitfield_default },
	 { "HUBP_MEASURE_WIN_PERIOD_M1_DCFCLK", 4, 11, &umr_bitfield_default },
	 { "HUBP_PERFMON_START_SEL_DCFCLK", 12, 16, &umr_bitfield_default },
	 { "HUBP_PERFMON_STOP_SEL_DCFCLK", 20, 24, &umr_bitfield_default },
	 { "HUBP_MEASURE_WIN_MODE_DCFCLK", 28, 29, &umr_bitfield_default },
};
static struct umr_bitfield mmHUBP0_HUBP_MEASURE_WIN_CTRL_DPPCLK[] = {
	 { "HUBP_MEASURE_WIN_EN_DPPCLK", 0, 0, &umr_bitfield_default },
	 { "HUBP_MEASURE_WIN_SRC_SEL_DPPCLK", 1, 1, &umr_bitfield_default },
	 { "HUBP_MEASURE_WIN_PERIOD_M1_DPPCLK", 4, 11, &umr_bitfield_default },
	 { "HUBP_PERFMON_START_SEL_DPPCLK", 12, 16, &umr_bitfield_default },
	 { "HUBP_PERFMON_STOP_SEL_DPPCLK", 20, 24, &umr_bitfield_default },
};
static struct umr_bitfield mmHUBPREQ0_DCSURF_SURFACE_PITCH[] = {
	 { "PITCH", 0, 13, &umr_bitfield_default },
	 { "META_PITCH", 16, 29, &umr_bitfield_default },
};
static struct umr_bitfield mmHUBPREQ0_DCSURF_SURFACE_PITCH_C[] = {
	 { "PITCH_C", 0, 13, &umr_bitfield_default },
	 { "META_PITCH_C", 16, 29, &umr_bitfield_default },
};
static struct umr_bitfield mmHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS[] = {
	 { "PRIMARY_SURFACE_ADDRESS", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH[] = {
	 { "PRIMARY_SURFACE_ADDRESS_HIGH", 0, 15, &umr_bitfield_default },
};
static struct umr_bitfield mmHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_C[] = {
	 { "PRIMARY_SURFACE_ADDRESS_C", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C[] = {
	 { "PRIMARY_SURFACE_ADDRESS_HIGH_C", 0, 15, &umr_bitfield_default },
};
static struct umr_bitfield mmHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS[] = {
	 { "SECONDARY_SURFACE_ADDRESS", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH[] = {
	 { "SECONDARY_SURFACE_ADDRESS_HIGH", 0, 15, &umr_bitfield_default },
};
static struct umr_bitfield mmHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_C[] = {
	 { "SECONDARY_SURFACE_ADDRESS_C", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C[] = {
	 { "SECONDARY_SURFACE_ADDRESS_HIGH_C", 0, 15, &umr_bitfield_default },
};
static struct umr_bitfield mmHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS[] = {
	 { "PRIMARY_META_SURFACE_ADDRESS", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH[] = {
	 { "PRIMARY_META_SURFACE_ADDRESS_HIGH", 0, 15, &umr_bitfield_default },
};
static struct umr_bitfield mmHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C[] = {
	 { "PRIMARY_META_SURFACE_ADDRESS_C", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C[] = {
	 { "PRIMARY_META_SURFACE_ADDRESS_HIGH_C", 0, 15, &umr_bitfield_default },
};
static struct umr_bitfield mmHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS[] = {
	 { "SECONDARY_META_SURFACE_ADDRESS", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH[] = {
	 { "SECONDARY_META_SURFACE_ADDRESS_HIGH", 0, 15, &umr_bitfield_default },
};
static struct umr_bitfield mmHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C[] = {
	 { "SECONDARY_META_SURFACE_ADDRESS_C", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C[] = {
	 { "SECONDARY_META_SURFACE_ADDRESS_HIGH_C", 0, 15, &umr_bitfield_default },
};
static struct umr_bitfield mmHUBPREQ0_DCSURF_SURFACE_CONTROL[] = {
	 { "PRIMARY_SURFACE_DCC_EN", 1, 1, &umr_bitfield_default },
	 { "PRIMARY_SURFACE_DCC_IND_64B_BLK", 2, 2, &umr_bitfield_default },
	 { "PRIMARY_SURFACE_DCC_IND_64B_BLK_C", 5, 5, &umr_bitfield_default },
	 { "SECONDARY_SURFACE_DCC_EN", 9, 9, &umr_bitfield_default },
	 { "SECONDARY_SURFACE_DCC_IND_64B_BLK", 10, 10, &umr_bitfield_default },
	 { "SECONDARY_SURFACE_DCC_IND_64B_BLK_C", 13, 13, &umr_bitfield_default },
};
static struct umr_bitfield mmHUBPREQ0_DCSURF_FLIP_CONTROL[] = {
	 { "SURFACE_UPDATE_LOCK", 0, 0, &umr_bitfield_default },
	 { "SURFACE_FLIP_TYPE", 1, 1, &umr_bitfield_default },
	 { "SURFACE_FLIP_VUPDATE_SKIP_NUM", 4, 7, &umr_bitfield_default },
	 { "SURFACE_FLIP_MODE_FOR_STEREOSYNC", 12, 13, &umr_bitfield_default },
	 { "SURFACE_FLIP_IN_STEREOSYNC", 16, 16, &umr_bitfield_default },
	 { "SURFACE_FLIP_STEREO_SELECT_DISABLE", 17, 17, &umr_bitfield_default },
	 { "SURFACE_FLIP_STEREO_SELECT_POLARITY", 18, 18, &umr_bitfield_default },
	 { "SURFACE_FLIP_PENDING_DELAY", 20, 29, &umr_bitfield_default },
	 { "SURFACE_UPDATE_PENDING", 30, 30, &umr_bitfield_default },
	 { "SURFACE_FLIP_PENDING", 31, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmHUBPREQ0_DCSURF_FLIP_CONTROL2[] = {
	 { "SURFACE_UPDATE_FLIP_PENDING_MIN_TIME", 0, 7, &umr_bitfield_default },
	 { "SURFACE_UPDATE_PENDING_HIGH_EXTEND_ENABLE", 12, 12, &umr_bitfield_default },
	 { "SURFACE_FLIP_PENDING_HIGH_EXTEND_ENABLE", 13, 13, &umr_bitfield_default },
};
static struct umr_bitfield mmHUBPREQ0_DCSURF_FRAME_PACING_CONTROL[] = {
	 { "SURFACE_FRAME_PACING_ENABLE", 0, 0, &umr_bitfield_default },
	 { "SURFACE_FRAME_PACING_MODE", 1, 1, &umr_bitfield_default },
	 { "SURFACE_FRAME_PACING_QUEUE_RESET", 8, 8, &umr_bitfield_default },
	 { "SURFACE_FRAME_PACING_QUEUE_FREE_ENTRY", 24, 26, &umr_bitfield_default },
};
static struct umr_bitfield mmHUBPREQ0_DCSURF_FRAME_PACING_TIME[] = {
	 { "SURFACE_FRAME_PACING_TIME", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmHUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT[] = {
	 { "SURFACE_FLIP_INT_MASK", 0, 0, &umr_bitfield_default },
	 { "SURFACE_FLIP_INT_TYPE", 1, 1, &umr_bitfield_default },
	 { "SURFACE_FLIP_AWAY_INT_MASK", 2, 2, &umr_bitfield_default },
	 { "SURFACE_FLIP_AWAY_INT_TYPE", 3, 3, &umr_bitfield_default },
	 { "SURFACE_FLIP_CLEAR", 8, 8, &umr_bitfield_default },
	 { "SURFACE_FLIP_AWAY_CLEAR", 9, 9, &umr_bitfield_default },
	 { "SURFACE_FLIP_OCCURRED", 16, 16, &umr_bitfield_default },
	 { "SURFACE_FLIP_INT_STATUS", 17, 17, &umr_bitfield_default },
	 { "SURFACE_FLIP_AWAY_OCCURRED", 18, 18, &umr_bitfield_default },
	 { "SURFACE_FLIP_AWAY_INT_STATUS", 19, 19, &umr_bitfield_default },
};
static struct umr_bitfield mmHUBPREQ0_DCSURF_SURFACE_INUSE[] = {
	 { "SURFACE_INUSE_ADDRESS", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmHUBPREQ0_DCSURF_SURFACE_INUSE_HIGH[] = {
	 { "SURFACE_INUSE_ADDRESS_HIGH", 0, 15, &umr_bitfield_default },
};
static struct umr_bitfield mmHUBPREQ0_DCSURF_SURFACE_INUSE_C[] = {
	 { "SURFACE_INUSE_ADDRESS_C", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmHUBPREQ0_DCSURF_SURFACE_INUSE_HIGH_C[] = {
	 { "SURFACE_INUSE_ADDRESS_HIGH_C", 0, 15, &umr_bitfield_default },
};
static struct umr_bitfield mmHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE[] = {
	 { "SURFACE_EARLIEST_INUSE_ADDRESS", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH[] = {
	 { "SURFACE_EARLIEST_INUSE_ADDRESS_HIGH", 0, 15, &umr_bitfield_default },
};
static struct umr_bitfield mmHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_C[] = {
	 { "SURFACE_EARLIEST_INUSE_ADDRESS_C", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C[] = {
	 { "SURFACE_EARLIEST_INUSE_ADDRESS_HIGH_C", 0, 15, &umr_bitfield_default },
};
static struct umr_bitfield mmHUBPREQ0_DCN_EXPANSION_MODE[] = {
	 { "DRQ_EXPANSION_MODE", 0, 1, &umr_bitfield_default },
	 { "CRQ_EXPANSION_MODE", 2, 3, &umr_bitfield_default },
	 { "MRQ_EXPANSION_MODE", 4, 5, &umr_bitfield_default },
	 { "PRQ_EXPANSION_MODE", 6, 7, &umr_bitfield_default },
};
static struct umr_bitfield mmHUBPREQ0_DCN_TTU_QOS_WM[] = {
	 { "QoS_LEVEL_LOW_WM", 0, 13, &umr_bitfield_default },
	 { "QoS_LEVEL_HIGH_WM", 16, 29, &umr_bitfield_default },
};
static struct umr_bitfield mmHUBPREQ0_DCN_GLOBAL_TTU_CNTL[] = {
	 { "MIN_TTU_VBLANK", 0, 23, &umr_bitfield_default },
	 { "QoS_LEVEL_FLIP", 28, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmHUBPREQ0_DCN_SURF0_TTU_CNTL0[] = {
	 { "REFCYC_PER_REQ_DELIVERY", 0, 22, &umr_bitfield_default },
	 { "QoS_LEVEL_FIXED", 24, 27, &umr_bitfield_default },
	 { "QoS_RAMP_DISABLE", 28, 28, &umr_bitfield_default },
};
static struct umr_bitfield mmHUBPREQ0_DCN_SURF0_TTU_CNTL1[] = {
	 { "REFCYC_PER_REQ_DELIVERY_PRE", 0, 22, &umr_bitfield_default },
};
static struct umr_bitfield mmHUBPREQ0_DCN_SURF1_TTU_CNTL0[] = {
	 { "REFCYC_PER_REQ_DELIVERY", 0, 22, &umr_bitfield_default },
	 { "QoS_LEVEL_FIXED", 24, 27, &umr_bitfield_default },
	 { "QoS_RAMP_DISABLE", 28, 28, &umr_bitfield_default },
};
static struct umr_bitfield mmHUBPREQ0_DCN_SURF1_TTU_CNTL1[] = {
	 { "REFCYC_PER_REQ_DELIVERY_PRE", 0, 22, &umr_bitfield_default },
};
static struct umr_bitfield mmHUBPREQ0_DCN_CUR0_TTU_CNTL0[] = {
	 { "REFCYC_PER_REQ_DELIVERY", 0, 22, &umr_bitfield_default },
	 { "QoS_LEVEL_FIXED", 24, 27, &umr_bitfield_default },
	 { "QoS_RAMP_DISABLE", 28, 28, &umr_bitfield_default },
};
static struct umr_bitfield mmHUBPREQ0_DCN_CUR0_TTU_CNTL1[] = {
	 { "REFCYC_PER_REQ_DELIVERY_PRE", 0, 22, &umr_bitfield_default },
};
static struct umr_bitfield mmHUBPREQ0_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_LSB[] = {
	 { "MC_VM_SYSTEM_APERTURE_LOW_ADDR_LSB", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmHUBPREQ0_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_MSB[] = {
	 { "MC_VM_SYSTEM_APERTURE_LOW_ADDR_MSB", 0, 3, &umr_bitfield_default },
};
static struct umr_bitfield mmHUBPREQ0_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_LSB[] = {
	 { "MC_VM_SYSTEM_APERTURE_HIGH_ADDR_LSB", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmHUBPREQ0_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_MSB[] = {
	 { "MC_VM_SYSTEM_APERTURE_HIGH_ADDR_MSB", 0, 3, &umr_bitfield_default },
};
static struct umr_bitfield mmHUBPREQ0_DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB[] = {
	 { "MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmHUBPREQ0_DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB[] = {
	 { "MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB", 0, 3, &umr_bitfield_default },
	 { "MC_VM_SYSTEM_APERTURE_DEFAULT_SYSTEM", 28, 28, &umr_bitfield_default },
	 { "MC_VM_SYSTEM_APERTURE_DEFAULT_SNOOP", 29, 29, &umr_bitfield_default },
};
static struct umr_bitfield mmHUBPREQ0_DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_LSB[] = {
	 { "VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_LSB", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmHUBPREQ0_DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB[] = {
	 { "VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB", 0, 3, &umr_bitfield_default },
	 { "VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_SYSTEM", 28, 28, &umr_bitfield_default },
	 { "VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_SNOOP", 29, 29, &umr_bitfield_default },
	 { "VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_TMZ", 30, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmHUBPREQ0_DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LSB[] = {
	 { "VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LSB", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmHUBPREQ0_DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_MSB[] = {
	 { "VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_MSB", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmHUBPREQ0_DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LSB[] = {
	 { "VM_CONTEXT0_PAGE_TABLE_START_ADDR_LSB", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmHUBPREQ0_DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_MSB[] = {
	 { "VM_CONTEXT0_PAGE_TABLE_START_ADDR_MSB", 0, 3, &umr_bitfield_default },
};
static struct umr_bitfield mmHUBPREQ0_DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LSB[] = {
	 { "VM_CONTEXT0_PAGE_TABLE_END_ADDR_LSB", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmHUBPREQ0_DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_MSB[] = {
	 { "VM_CONTEXT0_PAGE_TABLE_END_ADDR_MSB", 0, 3, &umr_bitfield_default },
};
static struct umr_bitfield mmHUBPREQ0_DCN_VM_CONTEXT0_STATUS[] = {
	 { "DCN_VM_CONTEXT0_ERROR_STATUS", 0, 15, &umr_bitfield_default },
	 { "DCN_VM_CONTEXT0_PROTECTION_FAULT_ADDR_MSB", 24, 27, &umr_bitfield_default },
	 { "DCN_VM_CONTEXT0_ERROR_STATUS_MODE", 30, 30, &umr_bitfield_default },
	 { "DCN_VM_CONTEXT0_ERROR_STATUS_CLEAR", 31, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmHUBPREQ0_DCN_VM_CONTEXT0_PROTECTION_FAULT_ADDR_LSB[] = {
	 { "DCN_VM_CONTEXT0_PROTECTION_FAULT_ADDR_LSB", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmHUBPREQ0_DCN_VM_CONTEXT0_CNTL[] = {
	 { "PAGE_TABLE_DEPTH", 1, 2, &umr_bitfield_default },
	 { "RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT", 3, 3, &umr_bitfield_default },
	 { "RANGE_PROTECTION_FAULT_ENABLE_DEFAULT", 4, 4, &umr_bitfield_default },
	 { "VALID_PROTECTION_FAULT_ENABLE_INTERRUPT", 12, 12, &umr_bitfield_default },
	 { "VALID_PROTECTION_FAULT_ENABLE_DEFAULT", 13, 13, &umr_bitfield_default },
	 { "READ_PROTECTION_FAULT_ENABLE_INTERRUPT", 15, 15, &umr_bitfield_default },
	 { "READ_PROTECTION_FAULT_ENABLE_DEFAULT", 16, 16, &umr_bitfield_default },
};
static struct umr_bitfield mmHUBPREQ0_DCN_VM_MX_L1_TLB_CNTL[] = {
	 { "ENABLE_L1_TLB", 0, 0, &umr_bitfield_default },
	 { "SYSTEM_ACCESS_MODE", 3, 4, &umr_bitfield_default },
};
static struct umr_bitfield mmHUBPREQ0_BLANK_OFFSET_0[] = {
	 { "REFCYC_H_BLANK_END", 0, 12, &umr_bitfield_default },
	 { "DLG_V_BLANK_END", 16, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmHUBPREQ0_BLANK_OFFSET_1[] = {
	 { "MIN_DST_Y_NEXT_START", 0, 17, &umr_bitfield_default },
};
static struct umr_bitfield mmHUBPREQ0_DST_DIMENSIONS[] = {
	 { "REFCYC_PER_HTOTAL", 0, 20, &umr_bitfield_default },
};
static struct umr_bitfield mmHUBPREQ0_DST_AFTER_SCALER[] = {
	 { "REFCYC_X_AFTER_SCALER", 0, 12, &umr_bitfield_default },
	 { "DST_Y_AFTER_SCALER", 16, 18, &umr_bitfield_default },
};
static struct umr_bitfield mmHUBPREQ0_PREFETCH_SETTINS[] = {
	 { "VRATIO_PREFETCH", 0, 20, &umr_bitfield_default },
	 { "DST_Y_PREFETCH", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmHUBPREQ0_PREFETCH_SETTINS_C[] = {
	 { "VRATIO_PREFETCH_C", 0, 20, &umr_bitfield_default },
};
static struct umr_bitfield mmHUBPREQ0_VBLANK_PARAMETERS_0[] = {
	 { "DST_Y_PER_VM_VBLANK", 0, 4, &umr_bitfield_default },
	 { "DST_Y_PER_ROW_VBLANK", 8, 13, &umr_bitfield_default },
};
static struct umr_bitfield mmHUBPREQ0_VBLANK_PARAMETERS_1[] = {
	 { "REFCYC_PER_PTE_GROUP_VBLANK_L", 0, 22, &umr_bitfield_default },
};
static struct umr_bitfield mmHUBPREQ0_VBLANK_PARAMETERS_2[] = {
	 { "REFCYC_PER_PTE_GROUP_VBLANK_C", 0, 22, &umr_bitfield_default },
};
static struct umr_bitfield mmHUBPREQ0_VBLANK_PARAMETERS_3[] = {
	 { "REFCYC_PER_META_CHUNK_VBLANK_L", 0, 22, &umr_bitfield_default },
};
static struct umr_bitfield mmHUBPREQ0_VBLANK_PARAMETERS_4[] = {
	 { "REFCYC_PER_META_CHUNK_VBLANK_C", 0, 22, &umr_bitfield_default },
};
static struct umr_bitfield mmHUBPREQ0_NOM_PARAMETERS_0[] = {
	 { "DST_Y_PER_PTE_ROW_NOM_L", 0, 16, &umr_bitfield_default },
};
static struct umr_bitfield mmHUBPREQ0_NOM_PARAMETERS_1[] = {
	 { "REFCYC_PER_PTE_GROUP_NOM_L", 0, 22, &umr_bitfield_default },
};
static struct umr_bitfield mmHUBPREQ0_NOM_PARAMETERS_2[] = {
	 { "DST_Y_PER_PTE_ROW_NOM_C", 0, 16, &umr_bitfield_default },
};
static struct umr_bitfield mmHUBPREQ0_NOM_PARAMETERS_3[] = {
	 { "REFCYC_PER_PTE_GROUP_NOM_C", 0, 22, &umr_bitfield_default },
};
static struct umr_bitfield mmHUBPREQ0_NOM_PARAMETERS_4[] = {
	 { "DST_Y_PER_META_ROW_NOM_L", 0, 16, &umr_bitfield_default },
};
static struct umr_bitfield mmHUBPREQ0_NOM_PARAMETERS_5[] = {
	 { "REFCYC_PER_META_CHUNK_NOM_L", 0, 22, &umr_bitfield_default },
};
static struct umr_bitfield mmHUBPREQ0_NOM_PARAMETERS_6[] = {
	 { "DST_Y_PER_META_ROW_NOM_C", 0, 16, &umr_bitfield_default },
};
static struct umr_bitfield mmHUBPREQ0_NOM_PARAMETERS_7[] = {
	 { "REFCYC_PER_META_CHUNK_NOM_C", 0, 22, &umr_bitfield_default },
};
static struct umr_bitfield mmHUBPREQ0_PER_LINE_DELIVERY_PRE[] = {
	 { "REFCYC_PER_LINE_DELIVERY_PRE_L", 0, 12, &umr_bitfield_default },
	 { "REFCYC_PER_LINE_DELIVERY_PRE_C", 16, 28, &umr_bitfield_default },
};
static struct umr_bitfield mmHUBPREQ0_PER_LINE_DELIVERY[] = {
	 { "REFCYC_PER_LINE_DELIVERY_L", 0, 12, &umr_bitfield_default },
	 { "REFCYC_PER_LINE_DELIVERY_C", 16, 28, &umr_bitfield_default },
};
static struct umr_bitfield mmHUBPREQ0_CURSOR_SETTINS[] = {
	 { "CURSOR0_DST_Y_OFFSET", 0, 7, &umr_bitfield_default },
	 { "CURSOR0_CHUNK_HDL_ADJUST", 8, 9, &umr_bitfield_default },
};
static struct umr_bitfield mmHUBPREQ0_REF_FREQ_TO_PIX_FREQ[] = {
	 { "REF_FREQ_TO_PIX_FREQ", 0, 20, &umr_bitfield_default },
};
static struct umr_bitfield mmHUBPREQ0_HUBPREQ_MEM_PWR_CTRL[] = {
	 { "REQ_DPTE_MEM_PWR_FORCE", 0, 1, &umr_bitfield_default },
	 { "REQ_DPTE_MEM_PWR_DIS", 2, 2, &umr_bitfield_default },
	 { "REQ_MPTE_MEM_PWR_FORCE", 4, 5, &umr_bitfield_default },
	 { "REQ_MPTE_MEM_PWR_DIS", 6, 6, &umr_bitfield_default },
	 { "REQ_META_MEM_PWR_FORCE", 8, 9, &umr_bitfield_default },
	 { "REQ_META_MEM_PWR_DIS", 10, 10, &umr_bitfield_default },
	 { "REQ_DPTE_FINE_GRAIN_DIS", 16, 16, &umr_bitfield_default },
	 { "REQ_DPTE_FINE_GRAIN_DIS_C", 17, 17, &umr_bitfield_default },
	 { "REQ_META_FINE_GRAIN_DIS", 20, 20, &umr_bitfield_default },
	 { "REQ_META_FINE_GRAIN_DIS_C", 21, 21, &umr_bitfield_default },
	 { "REQ_MPTE_FINE_GRAIN_DIS", 24, 24, &umr_bitfield_default },
};
static struct umr_bitfield mmHUBPREQ0_HUBPREQ_MEM_PWR_STATUS[] = {
	 { "REQ_DPTE_MEM_PWR_STATE", 0, 1, &umr_bitfield_default },
	 { "REQ_MPTE_MEM_PWR_STATE", 2, 3, &umr_bitfield_default },
	 { "REQ_META_MEM_PWR_STATE", 4, 5, &umr_bitfield_default },
};
static struct umr_bitfield mmHUBPRET0_HUBPRET_CONTROL[] = {
	 { "DET_BUF_PLANE1_BASE_ADDRESS", 0, 11, &umr_bitfield_default },
	 { "PACK_3TO2_ELEMENT_DISABLE", 12, 12, &umr_bitfield_default },
	 { "CROSSBAR_SRC_ALPHA", 16, 17, &umr_bitfield_default },
	 { "CROSSBAR_SRC_Y_G", 18, 19, &umr_bitfield_default },
	 { "CROSSBAR_SRC_CB_B", 20, 21, &umr_bitfield_default },
	 { "CROSSBAR_SRC_CR_R", 22, 23, &umr_bitfield_default },
	 { "HUBPRET_CONTROL_SPARE", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmHUBPRET0_HUBPRET_MEM_PWR_CTRL[] = {
	 { "DET_MEM_PWR_FORCE", 0, 1, &umr_bitfield_default },
	 { "DET_MEM_PWR_DIS", 2, 2, &umr_bitfield_default },
	 { "DET_MEM_PWR_LS_MODE", 4, 5, &umr_bitfield_default },
	 { "HUBPRET_MEM_PWR_CTRL_SPARE", 8, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmHUBPRET0_HUBPRET_MEM_PWR_STATUS[] = {
	 { "DET_MEM_PWR_STATE", 0, 1, &umr_bitfield_default },
};
static struct umr_bitfield mmHUBPRET0_HUBPRET_READ_LINE_CTRL0[] = {
	 { "PIPE_READ_LINE_INTERVAL_IN_NONACTIVE", 0, 15, &umr_bitfield_default },
	 { "PIPE_READ_LINE_VBLANK_MAXIMUM", 16, 29, &umr_bitfield_default },
};
static struct umr_bitfield mmHUBPRET0_HUBPRET_READ_LINE_CTRL1[] = {
	 { "PIPE_READ_LINE_REPORTED_WHEN_REQ_DISABLED", 0, 13, &umr_bitfield_default },
	 { "HUBPRET_READ_LINE_CTRL1_SPARE", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmHUBPRET0_HUBPRET_READ_LINE0[] = {
	 { "PIPE_READ_LINE0_START", 0, 13, &umr_bitfield_default },
	 { "PIPE_READ_LINE0_END", 16, 29, &umr_bitfield_default },
};
static struct umr_bitfield mmHUBPRET0_HUBPRET_READ_LINE1[] = {
	 { "PIPE_READ_LINE1_START", 0, 13, &umr_bitfield_default },
	 { "PIPE_READ_LINE1_END", 16, 29, &umr_bitfield_default },
};
static struct umr_bitfield mmHUBPRET0_HUBPRET_INTERRUPT[] = {
	 { "PIPE_VBLANK_INT_MASK", 0, 0, &umr_bitfield_default },
	 { "PIPE_READ_LINE0_INT_MASK", 1, 1, &umr_bitfield_default },
	 { "PIPE_READ_LINE1_INT_MASK", 2, 2, &umr_bitfield_default },
	 { "PIPE_VBLANK_INT_TYPE", 4, 4, &umr_bitfield_default },
	 { "PIPE_READ_LINE0_INT_TYPE", 5, 5, &umr_bitfield_default },
	 { "PIPE_READ_LINE1_INT_TYPE", 6, 6, &umr_bitfield_default },
	 { "PIPE_VBLANK_INT_CLEAR", 8, 8, &umr_bitfield_default },
	 { "PIPE_READ_LINE0_INT_CLEAR", 9, 9, &umr_bitfield_default },
	 { "PIPE_READ_LINE1_INT_CLEAR", 10, 10, &umr_bitfield_default },
	 { "PIPE_VBLANK_STATUS", 12, 12, &umr_bitfield_default },
	 { "PIPE_READ_LINE0_STATUS", 13, 13, &umr_bitfield_default },
	 { "PIPE_READ_LINE1_STATUS", 14, 14, &umr_bitfield_default },
	 { "PIPE_VBLANK_INT_STATUS", 16, 16, &umr_bitfield_default },
	 { "PIPE_READ_LINE0_INT_STATUS", 17, 17, &umr_bitfield_default },
	 { "PIPE_READ_LINE1_INT_STATUS", 18, 18, &umr_bitfield_default },
};
static struct umr_bitfield mmHUBPRET0_HUBPRET_READ_LINE_VALUE[] = {
	 { "PIPE_READ_LINE", 0, 13, &umr_bitfield_default },
	 { "PIPE_READ_LINE_SNAPSHOT", 16, 29, &umr_bitfield_default },
};
static struct umr_bitfield mmHUBPRET0_HUBPRET_READ_LINE_STATUS[] = {
	 { "PIPE_READ_VBLANK", 0, 0, &umr_bitfield_default },
	 { "PIPE_READ_LINE0_INSIDE", 4, 4, &umr_bitfield_default },
	 { "PIPE_READ_LINE0_OUTSIDE", 5, 5, &umr_bitfield_default },
	 { "PIPE_READ_LINE1_INSIDE", 8, 8, &umr_bitfield_default },
	 { "PIPE_READ_LINE1_OUTSIDE", 10, 10, &umr_bitfield_default },
};
static struct umr_bitfield mmCURSOR0_CURSOR_CONTROL[] = {
	 { "CURSOR_ENABLE", 0, 0, &umr_bitfield_default },
	 { "CURSOR_MODE", 8, 9, &umr_bitfield_default },
	 { "CURSOR_SNOOP", 13, 13, &umr_bitfield_default },
	 { "CURSOR_SYSTEM", 14, 14, &umr_bitfield_default },
	 { "CURSOR_PITCH", 16, 17, &umr_bitfield_default },
	 { "CURSOR_XY_POSITION_ROTATION_AND_MIRRORING_BYPASS", 20, 20, &umr_bitfield_default },
	 { "CURSOR_LINES_PER_CHUNK", 24, 28, &umr_bitfield_default },
	 { "CURSOR_PERFMON_LATENCY_MEASURE_EN", 30, 30, &umr_bitfield_default },
	 { "CURSOR_PERFMON_LATENCY_MEASURE_SEL", 31, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmCURSOR0_CURSOR_SURFACE_ADDRESS[] = {
	 { "CURSOR_SURFACE_ADDRESS", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmCURSOR0_CURSOR_SURFACE_ADDRESS_HIGH[] = {
	 { "CURSOR_SURFACE_ADDRESS_HIGH", 0, 15, &umr_bitfield_default },
};
static struct umr_bitfield mmCURSOR0_CURSOR_SIZE[] = {
	 { "CURSOR_HEIGHT", 0, 8, &umr_bitfield_default },
	 { "CURSOR_WIDTH", 16, 24, &umr_bitfield_default },
};
static struct umr_bitfield mmCURSOR0_CURSOR_POSITION[] = {
	 { "CURSOR_Y_POSITION", 0, 13, &umr_bitfield_default },
	 { "CURSOR_X_POSITION", 16, 29, &umr_bitfield_default },
};
static struct umr_bitfield mmCURSOR0_CURSOR_HOT_SPOT[] = {
	 { "CURSOR_HOT_SPOT_Y", 0, 7, &umr_bitfield_default },
	 { "CURSOR_HOT_SPOT_X", 16, 23, &umr_bitfield_default },
};
static struct umr_bitfield mmCURSOR0_CURSOR_STEREO_CONTROL[] = {
	 { "CURSOR_STEREO_EN", 0, 0, &umr_bitfield_default },
	 { "CURSOR_PRIMARY_OFFSET", 4, 17, &umr_bitfield_default },
	 { "CURSOR_SECONDARY_OFFSET", 18, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmCURSOR0_CURSOR_DST_OFFSET[] = {
	 { "CURSOR_DST_X_OFFSET", 0, 12, &umr_bitfield_default },
};
static struct umr_bitfield mmCURSOR0_CURSOR_MEM_PWR_CTRL[] = {
	 { "CROB_MEM_PWR_FORCE", 0, 1, &umr_bitfield_default },
	 { "CROB_MEM_PWR_DIS", 2, 2, &umr_bitfield_default },
	 { "CROB_MEM_PWR_LS_MODE", 4, 5, &umr_bitfield_default },
};
static struct umr_bitfield mmCURSOR0_CURSOR_MEM_PWR_STATUS[] = {
	 { "CROB_MEM_PWR_STATE", 0, 1, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_PERFMON8_PERFCOUNTER_CNTL[] = {
	 { "PERFCOUNTER_EVENT_SEL", 0, 8, &umr_bitfield_default },
	 { "PERFCOUNTER_CVALUE_SEL", 9, 11, &umr_bitfield_default },
	 { "PERFCOUNTER_INC_MODE", 12, 14, &umr_bitfield_default },
	 { "PERFCOUNTER_HW_CNTL_SEL", 15, 15, &umr_bitfield_default },
	 { "PERFCOUNTER_RUNEN_MODE", 16, 16, &umr_bitfield_default },
	 { "PERFCOUNTER_CNTOFF_START_DIS", 22, 22, &umr_bitfield_default },
	 { "PERFCOUNTER_RESTART_EN", 23, 23, &umr_bitfield_default },
	 { "PERFCOUNTER_INT_EN", 24, 24, &umr_bitfield_default },
	 { "PERFCOUNTER_OFF_MASK", 25, 25, &umr_bitfield_default },
	 { "PERFCOUNTER_ACTIVE", 26, 26, &umr_bitfield_default },
	 { "PERFCOUNTER_CNTL_SEL", 29, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_PERFMON8_PERFCOUNTER_CNTL2[] = {
	 { "PERFCOUNTER_COUNTED_VALUE_TYPE", 0, 1, &umr_bitfield_default },
	 { "PERFCOUNTER_HW_STOP1_SEL", 2, 2, &umr_bitfield_default },
	 { "PERFCOUNTER_HW_STOP2_SEL", 3, 3, &umr_bitfield_default },
	 { "PERFCOUNTER_CNTOFF_SEL", 8, 13, &umr_bitfield_default },
	 { "PERFCOUNTER_CNTL2_SEL", 29, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_PERFMON8_PERFCOUNTER_STATE[] = {
	 { "PERFCOUNTER_CNT0_STATE", 0, 1, &umr_bitfield_default },
	 { "PERFCOUNTER_STATE_SEL0", 2, 2, &umr_bitfield_default },
	 { "PERFCOUNTER_CNT1_STATE", 4, 5, &umr_bitfield_default },
	 { "PERFCOUNTER_STATE_SEL1", 6, 6, &umr_bitfield_default },
	 { "PERFCOUNTER_CNT2_STATE", 8, 9, &umr_bitfield_default },
	 { "PERFCOUNTER_STATE_SEL2", 10, 10, &umr_bitfield_default },
	 { "PERFCOUNTER_CNT3_STATE", 12, 13, &umr_bitfield_default },
	 { "PERFCOUNTER_STATE_SEL3", 14, 14, &umr_bitfield_default },
	 { "PERFCOUNTER_CNT4_STATE", 16, 17, &umr_bitfield_default },
	 { "PERFCOUNTER_STATE_SEL4", 18, 18, &umr_bitfield_default },
	 { "PERFCOUNTER_CNT5_STATE", 20, 21, &umr_bitfield_default },
	 { "PERFCOUNTER_STATE_SEL5", 22, 22, &umr_bitfield_default },
	 { "PERFCOUNTER_CNT6_STATE", 24, 25, &umr_bitfield_default },
	 { "PERFCOUNTER_STATE_SEL6", 26, 26, &umr_bitfield_default },
	 { "PERFCOUNTER_CNT7_STATE", 28, 29, &umr_bitfield_default },
	 { "PERFCOUNTER_STATE_SEL7", 30, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_PERFMON8_PERFMON_CNTL[] = {
	 { "PERFMON_STATE", 0, 1, &umr_bitfield_default },
	 { "PERFMON_RPT_COUNT", 8, 27, &umr_bitfield_default },
	 { "PERFMON_CNTOFF_AND_OR", 28, 28, &umr_bitfield_default },
	 { "PERFMON_CNTOFF_INT_EN", 29, 29, &umr_bitfield_default },
	 { "PERFMON_CNTOFF_INT_STATUS", 30, 30, &umr_bitfield_default },
	 { "PERFMON_CNTOFF_INT_ACK", 31, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_PERFMON8_PERFMON_CNTL2[] = {
	 { "PERFMON_CNTOFF_INT_TYPE", 0, 0, &umr_bitfield_default },
	 { "PERFMON_CLK_ENABLE", 1, 1, &umr_bitfield_default },
	 { "PERFMON_RUN_ENABLE_START_SEL", 2, 9, &umr_bitfield_default },
	 { "PERFMON_RUN_ENABLE_STOP_SEL", 10, 17, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_PERFMON8_PERFMON_CVALUE_INT_MISC[] = {
	 { "PERFCOUNTER_INT0_STATUS", 0, 0, &umr_bitfield_default },
	 { "PERFCOUNTER_INT1_STATUS", 1, 1, &umr_bitfield_default },
	 { "PERFCOUNTER_INT2_STATUS", 2, 2, &umr_bitfield_default },
	 { "PERFCOUNTER_INT3_STATUS", 3, 3, &umr_bitfield_default },
	 { "PERFCOUNTER_INT4_STATUS", 4, 4, &umr_bitfield_default },
	 { "PERFCOUNTER_INT5_STATUS", 5, 5, &umr_bitfield_default },
	 { "PERFCOUNTER_INT6_STATUS", 6, 6, &umr_bitfield_default },
	 { "PERFCOUNTER_INT7_STATUS", 7, 7, &umr_bitfield_default },
	 { "PERFCOUNTER_INT0_ACK", 8, 8, &umr_bitfield_default },
	 { "PERFCOUNTER_INT1_ACK", 9, 9, &umr_bitfield_default },
	 { "PERFCOUNTER_INT2_ACK", 10, 10, &umr_bitfield_default },
	 { "PERFCOUNTER_INT3_ACK", 11, 11, &umr_bitfield_default },
	 { "PERFCOUNTER_INT4_ACK", 12, 12, &umr_bitfield_default },
	 { "PERFCOUNTER_INT5_ACK", 13, 13, &umr_bitfield_default },
	 { "PERFCOUNTER_INT6_ACK", 14, 14, &umr_bitfield_default },
	 { "PERFCOUNTER_INT7_ACK", 15, 15, &umr_bitfield_default },
	 { "PERFMON_CVALUE_HI", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_PERFMON8_PERFMON_CVALUE_LOW[] = {
	 { "PERFMON_CVALUE_LOW", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_PERFMON8_PERFMON_HI[] = {
	 { "PERFMON_HI", 0, 15, &umr_bitfield_default },
	 { "PERFMON_READ_SEL", 29, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_PERFMON8_PERFMON_LOW[] = {
	 { "PERFMON_LOW", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmHUBP1_DCSURF_SURFACE_CONFIG[] = {
	 { "SURFACE_PIXEL_FORMAT", 0, 6, &umr_bitfield_default },
	 { "ROTATION_ANGLE", 8, 9, &umr_bitfield_default },
	 { "H_MIRROR_EN", 10, 10, &umr_bitfield_default },
};
static struct umr_bitfield mmHUBP1_DCSURF_ADDR_CONFIG[] = {
	 { "NUM_PIPES", 0, 2, &umr_bitfield_default },
	 { "NUM_BANKS", 3, 5, &umr_bitfield_default },
	 { "PIPE_INTERLEAVE", 6, 7, &umr_bitfield_default },
	 { "NUM_SE", 8, 9, &umr_bitfield_default },
	 { "NUM_RB_PER_SE", 10, 11, &umr_bitfield_default },
	 { "MAX_COMPRESSED_FRAGS", 12, 13, &umr_bitfield_default },
};
static struct umr_bitfield mmHUBP1_DCSURF_TILING_CONFIG[] = {
	 { "SW_MODE", 0, 4, &umr_bitfield_default },
	 { "DIM_TYPE", 7, 8, &umr_bitfield_default },
	 { "META_LINEAR", 9, 9, &umr_bitfield_default },
	 { "RB_ALIGNED", 10, 10, &umr_bitfield_default },
	 { "PIPE_ALIGNED", 11, 11, &umr_bitfield_default },
};
static struct umr_bitfield mmHUBP1_DCSURF_PRI_VIEWPORT_START[] = {
	 { "PRI_VIEWPORT_X_START", 0, 13, &umr_bitfield_default },
	 { "PRI_VIEWPORT_Y_START", 16, 29, &umr_bitfield_default },
};
static struct umr_bitfield mmHUBP1_DCSURF_PRI_VIEWPORT_DIMENSION[] = {
	 { "PRI_VIEWPORT_WIDTH", 0, 13, &umr_bitfield_default },
	 { "PRI_VIEWPORT_HEIGHT", 16, 29, &umr_bitfield_default },
};
static struct umr_bitfield mmHUBP1_DCSURF_PRI_VIEWPORT_START_C[] = {
	 { "PRI_VIEWPORT_X_START_C", 0, 13, &umr_bitfield_default },
	 { "PRI_VIEWPORT_Y_START_C", 16, 29, &umr_bitfield_default },
};
static struct umr_bitfield mmHUBP1_DCSURF_PRI_VIEWPORT_DIMENSION_C[] = {
	 { "PRI_VIEWPORT_WIDTH_C", 0, 13, &umr_bitfield_default },
	 { "PRI_VIEWPORT_HEIGHT_C", 16, 29, &umr_bitfield_default },
};
static struct umr_bitfield mmHUBP1_DCSURF_SEC_VIEWPORT_START[] = {
	 { "SEC_VIEWPORT_X_START", 0, 13, &umr_bitfield_default },
	 { "SEC_VIEWPORT_Y_START", 16, 29, &umr_bitfield_default },
};
static struct umr_bitfield mmHUBP1_DCSURF_SEC_VIEWPORT_DIMENSION[] = {
	 { "SEC_VIEWPORT_WIDTH", 0, 13, &umr_bitfield_default },
	 { "SEC_VIEWPORT_HEIGHT", 16, 29, &umr_bitfield_default },
};
static struct umr_bitfield mmHUBP1_DCSURF_SEC_VIEWPORT_START_C[] = {
	 { "SEC_VIEWPORT_X_START_C", 0, 13, &umr_bitfield_default },
	 { "SEC_VIEWPORT_Y_START_C", 16, 29, &umr_bitfield_default },
};
static struct umr_bitfield mmHUBP1_DCSURF_SEC_VIEWPORT_DIMENSION_C[] = {
	 { "SEC_VIEWPORT_WIDTH_C", 0, 13, &umr_bitfield_default },
	 { "SEC_VIEWPORT_HEIGHT_C", 16, 29, &umr_bitfield_default },
};
static struct umr_bitfield mmHUBP1_DCHUBP_REQ_SIZE_CONFIG[] = {
	 { "SWATH_HEIGHT", 0, 2, &umr_bitfield_default },
	 { "PTE_ROW_HEIGHT_LINEAR", 4, 6, &umr_bitfield_default },
	 { "CHUNK_SIZE", 8, 10, &umr_bitfield_default },
	 { "MIN_CHUNK_SIZE", 11, 12, &umr_bitfield_default },
	 { "META_CHUNK_SIZE", 16, 17, &umr_bitfield_default },
	 { "MIN_META_CHUNK_SIZE", 18, 19, &umr_bitfield_default },
	 { "DPTE_GROUP_SIZE", 20, 22, &umr_bitfield_default },
	 { "MPTE_GROUP_SIZE", 24, 26, &umr_bitfield_default },
};
static struct umr_bitfield mmHUBP1_DCHUBP_REQ_SIZE_CONFIG_C[] = {
	 { "SWATH_HEIGHT_C", 0, 2, &umr_bitfield_default },
	 { "PTE_ROW_HEIGHT_LINEAR_C", 4, 6, &umr_bitfield_default },
	 { "CHUNK_SIZE_C", 8, 10, &umr_bitfield_default },
	 { "MIN_CHUNK_SIZE_C", 11, 12, &umr_bitfield_default },
	 { "META_CHUNK_SIZE_C", 16, 17, &umr_bitfield_default },
	 { "MIN_META_CHUNK_SIZE_C", 18, 19, &umr_bitfield_default },
	 { "DPTE_GROUP_SIZE_C", 20, 22, &umr_bitfield_default },
	 { "MPTE_GROUP_SIZE_C", 24, 26, &umr_bitfield_default },
};
static struct umr_bitfield mmHUBP1_DCHUBP_CNTL[] = {
	 { "HUBP_BLANK_EN", 0, 0, &umr_bitfield_default },
	 { "HUBP_NO_OUTSTANDING_REQ", 1, 1, &umr_bitfield_default },
	 { "HUBP_DISABLE", 2, 2, &umr_bitfield_default },
	 { "HUBP_IN_BLANK", 3, 3, &umr_bitfield_default },
	 { "HUBP_VTG_SEL", 4, 7, &umr_bitfield_default },
	 { "HUBP_TTU_DISABLE", 12, 12, &umr_bitfield_default },
	 { "HUBP_TTU_MODE", 13, 15, &umr_bitfield_default },
	 { "HUBP_UNDERFLOW_STATUS", 28, 30, &umr_bitfield_default },
	 { "HUBP_UNDERFLOW_CLEAR", 31, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmHUBP1_HUBP_CLK_CNTL[] = {
	 { "HUBP_CLOCK_ENABLE", 0, 0, &umr_bitfield_default },
	 { "HUBP_DISPCLK_R_GATE_DIS", 4, 4, &umr_bitfield_default },
	 { "HUBP_DPPCLK_G_GATE_DIS", 8, 8, &umr_bitfield_default },
	 { "HUBP_DCFCLK_R_GATE_DIS", 12, 12, &umr_bitfield_default },
	 { "HUBP_DCFCLK_G_GATE_DIS", 16, 16, &umr_bitfield_default },
	 { "HUBP_DISPCLK_R_CLOCK_ON", 20, 20, &umr_bitfield_default },
	 { "HUBP_DPPCLK_G_CLOCK_ON", 21, 21, &umr_bitfield_default },
	 { "HUBP_DCFCLK_R_CLOCK_ON", 22, 22, &umr_bitfield_default },
	 { "HUBP_DCFCLK_G_CLOCK_ON", 23, 23, &umr_bitfield_default },
	 { "HUBP_TEST_CLK_SEL", 28, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmHUBP1_DCHUBP_VMPG_CONFIG[] = {
	 { "VMPG_SIZE", 0, 0, &umr_bitfield_default },
};
static struct umr_bitfield mmHUBP1_HUBPREQ_DEBUG_DB[] = {
	 { "HUBPREQ_DEBUG", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmHUBP1_HUBP_MEASURE_WIN_CTRL_DCFCLK[] = {
	 { "HUBP_MEASURE_WIN_EN_DCFCLK", 0, 0, &umr_bitfield_default },
	 { "HUBP_MEASURE_WIN_PERIOD_M1_DCFCLK", 4, 11, &umr_bitfield_default },
	 { "HUBP_PERFMON_START_SEL_DCFCLK", 12, 16, &umr_bitfield_default },
	 { "HUBP_PERFMON_STOP_SEL_DCFCLK", 20, 24, &umr_bitfield_default },
	 { "HUBP_MEASURE_WIN_MODE_DCFCLK", 28, 29, &umr_bitfield_default },
};
static struct umr_bitfield mmHUBP1_HUBP_MEASURE_WIN_CTRL_DPPCLK[] = {
	 { "HUBP_MEASURE_WIN_EN_DPPCLK", 0, 0, &umr_bitfield_default },
	 { "HUBP_MEASURE_WIN_SRC_SEL_DPPCLK", 1, 1, &umr_bitfield_default },
	 { "HUBP_MEASURE_WIN_PERIOD_M1_DPPCLK", 4, 11, &umr_bitfield_default },
	 { "HUBP_PERFMON_START_SEL_DPPCLK", 12, 16, &umr_bitfield_default },
	 { "HUBP_PERFMON_STOP_SEL_DPPCLK", 20, 24, &umr_bitfield_default },
};
static struct umr_bitfield mmHUBPREQ1_DCSURF_SURFACE_PITCH[] = {
	 { "PITCH", 0, 13, &umr_bitfield_default },
	 { "META_PITCH", 16, 29, &umr_bitfield_default },
};
static struct umr_bitfield mmHUBPREQ1_DCSURF_SURFACE_PITCH_C[] = {
	 { "PITCH_C", 0, 13, &umr_bitfield_default },
	 { "META_PITCH_C", 16, 29, &umr_bitfield_default },
};
static struct umr_bitfield mmHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS[] = {
	 { "PRIMARY_SURFACE_ADDRESS", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH[] = {
	 { "PRIMARY_SURFACE_ADDRESS_HIGH", 0, 15, &umr_bitfield_default },
};
static struct umr_bitfield mmHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_C[] = {
	 { "PRIMARY_SURFACE_ADDRESS_C", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C[] = {
	 { "PRIMARY_SURFACE_ADDRESS_HIGH_C", 0, 15, &umr_bitfield_default },
};
static struct umr_bitfield mmHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS[] = {
	 { "SECONDARY_SURFACE_ADDRESS", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH[] = {
	 { "SECONDARY_SURFACE_ADDRESS_HIGH", 0, 15, &umr_bitfield_default },
};
static struct umr_bitfield mmHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_C[] = {
	 { "SECONDARY_SURFACE_ADDRESS_C", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C[] = {
	 { "SECONDARY_SURFACE_ADDRESS_HIGH_C", 0, 15, &umr_bitfield_default },
};
static struct umr_bitfield mmHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS[] = {
	 { "PRIMARY_META_SURFACE_ADDRESS", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH[] = {
	 { "PRIMARY_META_SURFACE_ADDRESS_HIGH", 0, 15, &umr_bitfield_default },
};
static struct umr_bitfield mmHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C[] = {
	 { "PRIMARY_META_SURFACE_ADDRESS_C", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C[] = {
	 { "PRIMARY_META_SURFACE_ADDRESS_HIGH_C", 0, 15, &umr_bitfield_default },
};
static struct umr_bitfield mmHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS[] = {
	 { "SECONDARY_META_SURFACE_ADDRESS", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH[] = {
	 { "SECONDARY_META_SURFACE_ADDRESS_HIGH", 0, 15, &umr_bitfield_default },
};
static struct umr_bitfield mmHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C[] = {
	 { "SECONDARY_META_SURFACE_ADDRESS_C", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C[] = {
	 { "SECONDARY_META_SURFACE_ADDRESS_HIGH_C", 0, 15, &umr_bitfield_default },
};
static struct umr_bitfield mmHUBPREQ1_DCSURF_SURFACE_CONTROL[] = {
	 { "PRIMARY_SURFACE_DCC_EN", 1, 1, &umr_bitfield_default },
	 { "PRIMARY_SURFACE_DCC_IND_64B_BLK", 2, 2, &umr_bitfield_default },
	 { "PRIMARY_SURFACE_DCC_IND_64B_BLK_C", 5, 5, &umr_bitfield_default },
	 { "SECONDARY_SURFACE_DCC_EN", 9, 9, &umr_bitfield_default },
	 { "SECONDARY_SURFACE_DCC_IND_64B_BLK", 10, 10, &umr_bitfield_default },
	 { "SECONDARY_SURFACE_DCC_IND_64B_BLK_C", 13, 13, &umr_bitfield_default },
};
static struct umr_bitfield mmHUBPREQ1_DCSURF_FLIP_CONTROL[] = {
	 { "SURFACE_UPDATE_LOCK", 0, 0, &umr_bitfield_default },
	 { "SURFACE_FLIP_TYPE", 1, 1, &umr_bitfield_default },
	 { "SURFACE_FLIP_VUPDATE_SKIP_NUM", 4, 7, &umr_bitfield_default },
	 { "SURFACE_FLIP_MODE_FOR_STEREOSYNC", 12, 13, &umr_bitfield_default },
	 { "SURFACE_FLIP_IN_STEREOSYNC", 16, 16, &umr_bitfield_default },
	 { "SURFACE_FLIP_STEREO_SELECT_DISABLE", 17, 17, &umr_bitfield_default },
	 { "SURFACE_FLIP_STEREO_SELECT_POLARITY", 18, 18, &umr_bitfield_default },
	 { "SURFACE_FLIP_PENDING_DELAY", 20, 29, &umr_bitfield_default },
	 { "SURFACE_UPDATE_PENDING", 30, 30, &umr_bitfield_default },
	 { "SURFACE_FLIP_PENDING", 31, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmHUBPREQ1_DCSURF_FLIP_CONTROL2[] = {
	 { "SURFACE_UPDATE_FLIP_PENDING_MIN_TIME", 0, 7, &umr_bitfield_default },
	 { "SURFACE_UPDATE_PENDING_HIGH_EXTEND_ENABLE", 12, 12, &umr_bitfield_default },
	 { "SURFACE_FLIP_PENDING_HIGH_EXTEND_ENABLE", 13, 13, &umr_bitfield_default },
};
static struct umr_bitfield mmHUBPREQ1_DCSURF_FRAME_PACING_CONTROL[] = {
	 { "SURFACE_FRAME_PACING_ENABLE", 0, 0, &umr_bitfield_default },
	 { "SURFACE_FRAME_PACING_MODE", 1, 1, &umr_bitfield_default },
	 { "SURFACE_FRAME_PACING_QUEUE_RESET", 8, 8, &umr_bitfield_default },
	 { "SURFACE_FRAME_PACING_QUEUE_FREE_ENTRY", 24, 26, &umr_bitfield_default },
};
static struct umr_bitfield mmHUBPREQ1_DCSURF_FRAME_PACING_TIME[] = {
	 { "SURFACE_FRAME_PACING_TIME", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmHUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT[] = {
	 { "SURFACE_FLIP_INT_MASK", 0, 0, &umr_bitfield_default },
	 { "SURFACE_FLIP_INT_TYPE", 1, 1, &umr_bitfield_default },
	 { "SURFACE_FLIP_AWAY_INT_MASK", 2, 2, &umr_bitfield_default },
	 { "SURFACE_FLIP_AWAY_INT_TYPE", 3, 3, &umr_bitfield_default },
	 { "SURFACE_FLIP_CLEAR", 8, 8, &umr_bitfield_default },
	 { "SURFACE_FLIP_AWAY_CLEAR", 9, 9, &umr_bitfield_default },
	 { "SURFACE_FLIP_OCCURRED", 16, 16, &umr_bitfield_default },
	 { "SURFACE_FLIP_INT_STATUS", 17, 17, &umr_bitfield_default },
	 { "SURFACE_FLIP_AWAY_OCCURRED", 18, 18, &umr_bitfield_default },
	 { "SURFACE_FLIP_AWAY_INT_STATUS", 19, 19, &umr_bitfield_default },
};
static struct umr_bitfield mmHUBPREQ1_DCSURF_SURFACE_INUSE[] = {
	 { "SURFACE_INUSE_ADDRESS", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmHUBPREQ1_DCSURF_SURFACE_INUSE_HIGH[] = {
	 { "SURFACE_INUSE_ADDRESS_HIGH", 0, 15, &umr_bitfield_default },
};
static struct umr_bitfield mmHUBPREQ1_DCSURF_SURFACE_INUSE_C[] = {
	 { "SURFACE_INUSE_ADDRESS_C", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmHUBPREQ1_DCSURF_SURFACE_INUSE_HIGH_C[] = {
	 { "SURFACE_INUSE_ADDRESS_HIGH_C", 0, 15, &umr_bitfield_default },
};
static struct umr_bitfield mmHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE[] = {
	 { "SURFACE_EARLIEST_INUSE_ADDRESS", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_HIGH[] = {
	 { "SURFACE_EARLIEST_INUSE_ADDRESS_HIGH", 0, 15, &umr_bitfield_default },
};
static struct umr_bitfield mmHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_C[] = {
	 { "SURFACE_EARLIEST_INUSE_ADDRESS_C", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C[] = {
	 { "SURFACE_EARLIEST_INUSE_ADDRESS_HIGH_C", 0, 15, &umr_bitfield_default },
};
static struct umr_bitfield mmHUBPREQ1_DCN_EXPANSION_MODE[] = {
	 { "DRQ_EXPANSION_MODE", 0, 1, &umr_bitfield_default },
	 { "CRQ_EXPANSION_MODE", 2, 3, &umr_bitfield_default },
	 { "MRQ_EXPANSION_MODE", 4, 5, &umr_bitfield_default },
	 { "PRQ_EXPANSION_MODE", 6, 7, &umr_bitfield_default },
};
static struct umr_bitfield mmHUBPREQ1_DCN_TTU_QOS_WM[] = {
	 { "QoS_LEVEL_LOW_WM", 0, 13, &umr_bitfield_default },
	 { "QoS_LEVEL_HIGH_WM", 16, 29, &umr_bitfield_default },
};
static struct umr_bitfield mmHUBPREQ1_DCN_GLOBAL_TTU_CNTL[] = {
	 { "MIN_TTU_VBLANK", 0, 23, &umr_bitfield_default },
	 { "QoS_LEVEL_FLIP", 28, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmHUBPREQ1_DCN_SURF0_TTU_CNTL0[] = {
	 { "REFCYC_PER_REQ_DELIVERY", 0, 22, &umr_bitfield_default },
	 { "QoS_LEVEL_FIXED", 24, 27, &umr_bitfield_default },
	 { "QoS_RAMP_DISABLE", 28, 28, &umr_bitfield_default },
};
static struct umr_bitfield mmHUBPREQ1_DCN_SURF0_TTU_CNTL1[] = {
	 { "REFCYC_PER_REQ_DELIVERY_PRE", 0, 22, &umr_bitfield_default },
};
static struct umr_bitfield mmHUBPREQ1_DCN_SURF1_TTU_CNTL0[] = {
	 { "REFCYC_PER_REQ_DELIVERY", 0, 22, &umr_bitfield_default },
	 { "QoS_LEVEL_FIXED", 24, 27, &umr_bitfield_default },
	 { "QoS_RAMP_DISABLE", 28, 28, &umr_bitfield_default },
};
static struct umr_bitfield mmHUBPREQ1_DCN_SURF1_TTU_CNTL1[] = {
	 { "REFCYC_PER_REQ_DELIVERY_PRE", 0, 22, &umr_bitfield_default },
};
static struct umr_bitfield mmHUBPREQ1_DCN_CUR0_TTU_CNTL0[] = {
	 { "REFCYC_PER_REQ_DELIVERY", 0, 22, &umr_bitfield_default },
	 { "QoS_LEVEL_FIXED", 24, 27, &umr_bitfield_default },
	 { "QoS_RAMP_DISABLE", 28, 28, &umr_bitfield_default },
};
static struct umr_bitfield mmHUBPREQ1_DCN_CUR0_TTU_CNTL1[] = {
	 { "REFCYC_PER_REQ_DELIVERY_PRE", 0, 22, &umr_bitfield_default },
};
static struct umr_bitfield mmHUBPREQ1_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_LSB[] = {
	 { "MC_VM_SYSTEM_APERTURE_LOW_ADDR_LSB", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmHUBPREQ1_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_MSB[] = {
	 { "MC_VM_SYSTEM_APERTURE_LOW_ADDR_MSB", 0, 3, &umr_bitfield_default },
};
static struct umr_bitfield mmHUBPREQ1_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_LSB[] = {
	 { "MC_VM_SYSTEM_APERTURE_HIGH_ADDR_LSB", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmHUBPREQ1_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_MSB[] = {
	 { "MC_VM_SYSTEM_APERTURE_HIGH_ADDR_MSB", 0, 3, &umr_bitfield_default },
};
static struct umr_bitfield mmHUBPREQ1_DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB[] = {
	 { "MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmHUBPREQ1_DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB[] = {
	 { "MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB", 0, 3, &umr_bitfield_default },
	 { "MC_VM_SYSTEM_APERTURE_DEFAULT_SYSTEM", 28, 28, &umr_bitfield_default },
	 { "MC_VM_SYSTEM_APERTURE_DEFAULT_SNOOP", 29, 29, &umr_bitfield_default },
};
static struct umr_bitfield mmHUBPREQ1_DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_LSB[] = {
	 { "VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_LSB", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmHUBPREQ1_DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB[] = {
	 { "VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB", 0, 3, &umr_bitfield_default },
	 { "VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_SYSTEM", 28, 28, &umr_bitfield_default },
	 { "VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_SNOOP", 29, 29, &umr_bitfield_default },
	 { "VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_TMZ", 30, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmHUBPREQ1_DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LSB[] = {
	 { "VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LSB", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmHUBPREQ1_DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_MSB[] = {
	 { "VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_MSB", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmHUBPREQ1_DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LSB[] = {
	 { "VM_CONTEXT0_PAGE_TABLE_START_ADDR_LSB", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmHUBPREQ1_DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_MSB[] = {
	 { "VM_CONTEXT0_PAGE_TABLE_START_ADDR_MSB", 0, 3, &umr_bitfield_default },
};
static struct umr_bitfield mmHUBPREQ1_DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LSB[] = {
	 { "VM_CONTEXT0_PAGE_TABLE_END_ADDR_LSB", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmHUBPREQ1_DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_MSB[] = {
	 { "VM_CONTEXT0_PAGE_TABLE_END_ADDR_MSB", 0, 3, &umr_bitfield_default },
};
static struct umr_bitfield mmHUBPREQ1_DCN_VM_CONTEXT0_STATUS[] = {
	 { "DCN_VM_CONTEXT0_ERROR_STATUS", 0, 15, &umr_bitfield_default },
	 { "DCN_VM_CONTEXT0_PROTECTION_FAULT_ADDR_MSB", 24, 27, &umr_bitfield_default },
	 { "DCN_VM_CONTEXT0_ERROR_STATUS_MODE", 30, 30, &umr_bitfield_default },
	 { "DCN_VM_CONTEXT0_ERROR_STATUS_CLEAR", 31, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmHUBPREQ1_DCN_VM_CONTEXT0_PROTECTION_FAULT_ADDR_LSB[] = {
	 { "DCN_VM_CONTEXT0_PROTECTION_FAULT_ADDR_LSB", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmHUBPREQ1_DCN_VM_CONTEXT0_CNTL[] = {
	 { "PAGE_TABLE_DEPTH", 1, 2, &umr_bitfield_default },
	 { "RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT", 3, 3, &umr_bitfield_default },
	 { "RANGE_PROTECTION_FAULT_ENABLE_DEFAULT", 4, 4, &umr_bitfield_default },
	 { "VALID_PROTECTION_FAULT_ENABLE_INTERRUPT", 12, 12, &umr_bitfield_default },
	 { "VALID_PROTECTION_FAULT_ENABLE_DEFAULT", 13, 13, &umr_bitfield_default },
	 { "READ_PROTECTION_FAULT_ENABLE_INTERRUPT", 15, 15, &umr_bitfield_default },
	 { "READ_PROTECTION_FAULT_ENABLE_DEFAULT", 16, 16, &umr_bitfield_default },
};
static struct umr_bitfield mmHUBPREQ1_DCN_VM_MX_L1_TLB_CNTL[] = {
	 { "ENABLE_L1_TLB", 0, 0, &umr_bitfield_default },
	 { "SYSTEM_ACCESS_MODE", 3, 4, &umr_bitfield_default },
};
static struct umr_bitfield mmHUBPREQ1_BLANK_OFFSET_0[] = {
	 { "REFCYC_H_BLANK_END", 0, 12, &umr_bitfield_default },
	 { "DLG_V_BLANK_END", 16, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmHUBPREQ1_BLANK_OFFSET_1[] = {
	 { "MIN_DST_Y_NEXT_START", 0, 17, &umr_bitfield_default },
};
static struct umr_bitfield mmHUBPREQ1_DST_DIMENSIONS[] = {
	 { "REFCYC_PER_HTOTAL", 0, 20, &umr_bitfield_default },
};
static struct umr_bitfield mmHUBPREQ1_DST_AFTER_SCALER[] = {
	 { "REFCYC_X_AFTER_SCALER", 0, 12, &umr_bitfield_default },
	 { "DST_Y_AFTER_SCALER", 16, 18, &umr_bitfield_default },
};
static struct umr_bitfield mmHUBPREQ1_PREFETCH_SETTINS[] = {
	 { "VRATIO_PREFETCH", 0, 20, &umr_bitfield_default },
	 { "DST_Y_PREFETCH", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmHUBPREQ1_PREFETCH_SETTINS_C[] = {
	 { "VRATIO_PREFETCH_C", 0, 20, &umr_bitfield_default },
};
static struct umr_bitfield mmHUBPREQ1_VBLANK_PARAMETERS_0[] = {
	 { "DST_Y_PER_VM_VBLANK", 0, 4, &umr_bitfield_default },
	 { "DST_Y_PER_ROW_VBLANK", 8, 13, &umr_bitfield_default },
};
static struct umr_bitfield mmHUBPREQ1_VBLANK_PARAMETERS_1[] = {
	 { "REFCYC_PER_PTE_GROUP_VBLANK_L", 0, 22, &umr_bitfield_default },
};
static struct umr_bitfield mmHUBPREQ1_VBLANK_PARAMETERS_2[] = {
	 { "REFCYC_PER_PTE_GROUP_VBLANK_C", 0, 22, &umr_bitfield_default },
};
static struct umr_bitfield mmHUBPREQ1_VBLANK_PARAMETERS_3[] = {
	 { "REFCYC_PER_META_CHUNK_VBLANK_L", 0, 22, &umr_bitfield_default },
};
static struct umr_bitfield mmHUBPREQ1_VBLANK_PARAMETERS_4[] = {
	 { "REFCYC_PER_META_CHUNK_VBLANK_C", 0, 22, &umr_bitfield_default },
};
static struct umr_bitfield mmHUBPREQ1_NOM_PARAMETERS_0[] = {
	 { "DST_Y_PER_PTE_ROW_NOM_L", 0, 16, &umr_bitfield_default },
};
static struct umr_bitfield mmHUBPREQ1_NOM_PARAMETERS_1[] = {
	 { "REFCYC_PER_PTE_GROUP_NOM_L", 0, 22, &umr_bitfield_default },
};
static struct umr_bitfield mmHUBPREQ1_NOM_PARAMETERS_2[] = {
	 { "DST_Y_PER_PTE_ROW_NOM_C", 0, 16, &umr_bitfield_default },
};
static struct umr_bitfield mmHUBPREQ1_NOM_PARAMETERS_3[] = {
	 { "REFCYC_PER_PTE_GROUP_NOM_C", 0, 22, &umr_bitfield_default },
};
static struct umr_bitfield mmHUBPREQ1_NOM_PARAMETERS_4[] = {
	 { "DST_Y_PER_META_ROW_NOM_L", 0, 16, &umr_bitfield_default },
};
static struct umr_bitfield mmHUBPREQ1_NOM_PARAMETERS_5[] = {
	 { "REFCYC_PER_META_CHUNK_NOM_L", 0, 22, &umr_bitfield_default },
};
static struct umr_bitfield mmHUBPREQ1_NOM_PARAMETERS_6[] = {
	 { "DST_Y_PER_META_ROW_NOM_C", 0, 16, &umr_bitfield_default },
};
static struct umr_bitfield mmHUBPREQ1_NOM_PARAMETERS_7[] = {
	 { "REFCYC_PER_META_CHUNK_NOM_C", 0, 22, &umr_bitfield_default },
};
static struct umr_bitfield mmHUBPREQ1_PER_LINE_DELIVERY_PRE[] = {
	 { "REFCYC_PER_LINE_DELIVERY_PRE_L", 0, 12, &umr_bitfield_default },
	 { "REFCYC_PER_LINE_DELIVERY_PRE_C", 16, 28, &umr_bitfield_default },
};
static struct umr_bitfield mmHUBPREQ1_PER_LINE_DELIVERY[] = {
	 { "REFCYC_PER_LINE_DELIVERY_L", 0, 12, &umr_bitfield_default },
	 { "REFCYC_PER_LINE_DELIVERY_C", 16, 28, &umr_bitfield_default },
};
static struct umr_bitfield mmHUBPREQ1_CURSOR_SETTINS[] = {
	 { "CURSOR0_DST_Y_OFFSET", 0, 7, &umr_bitfield_default },
	 { "CURSOR0_CHUNK_HDL_ADJUST", 8, 9, &umr_bitfield_default },
};
static struct umr_bitfield mmHUBPREQ1_REF_FREQ_TO_PIX_FREQ[] = {
	 { "REF_FREQ_TO_PIX_FREQ", 0, 20, &umr_bitfield_default },
};
static struct umr_bitfield mmHUBPREQ1_HUBPREQ_MEM_PWR_CTRL[] = {
	 { "REQ_DPTE_MEM_PWR_FORCE", 0, 1, &umr_bitfield_default },
	 { "REQ_DPTE_MEM_PWR_DIS", 2, 2, &umr_bitfield_default },
	 { "REQ_MPTE_MEM_PWR_FORCE", 4, 5, &umr_bitfield_default },
	 { "REQ_MPTE_MEM_PWR_DIS", 6, 6, &umr_bitfield_default },
	 { "REQ_META_MEM_PWR_FORCE", 8, 9, &umr_bitfield_default },
	 { "REQ_META_MEM_PWR_DIS", 10, 10, &umr_bitfield_default },
	 { "REQ_DPTE_FINE_GRAIN_DIS", 16, 16, &umr_bitfield_default },
	 { "REQ_DPTE_FINE_GRAIN_DIS_C", 17, 17, &umr_bitfield_default },
	 { "REQ_META_FINE_GRAIN_DIS", 20, 20, &umr_bitfield_default },
	 { "REQ_META_FINE_GRAIN_DIS_C", 21, 21, &umr_bitfield_default },
	 { "REQ_MPTE_FINE_GRAIN_DIS", 24, 24, &umr_bitfield_default },
};
static struct umr_bitfield mmHUBPREQ1_HUBPREQ_MEM_PWR_STATUS[] = {
	 { "REQ_DPTE_MEM_PWR_STATE", 0, 1, &umr_bitfield_default },
	 { "REQ_MPTE_MEM_PWR_STATE", 2, 3, &umr_bitfield_default },
	 { "REQ_META_MEM_PWR_STATE", 4, 5, &umr_bitfield_default },
};
static struct umr_bitfield mmHUBPRET1_HUBPRET_CONTROL[] = {
	 { "DET_BUF_PLANE1_BASE_ADDRESS", 0, 11, &umr_bitfield_default },
	 { "PACK_3TO2_ELEMENT_DISABLE", 12, 12, &umr_bitfield_default },
	 { "CROSSBAR_SRC_ALPHA", 16, 17, &umr_bitfield_default },
	 { "CROSSBAR_SRC_Y_G", 18, 19, &umr_bitfield_default },
	 { "CROSSBAR_SRC_CB_B", 20, 21, &umr_bitfield_default },
	 { "CROSSBAR_SRC_CR_R", 22, 23, &umr_bitfield_default },
	 { "HUBPRET_CONTROL_SPARE", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmHUBPRET1_HUBPRET_MEM_PWR_CTRL[] = {
	 { "DET_MEM_PWR_FORCE", 0, 1, &umr_bitfield_default },
	 { "DET_MEM_PWR_DIS", 2, 2, &umr_bitfield_default },
	 { "DET_MEM_PWR_LS_MODE", 4, 5, &umr_bitfield_default },
	 { "HUBPRET_MEM_PWR_CTRL_SPARE", 8, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmHUBPRET1_HUBPRET_MEM_PWR_STATUS[] = {
	 { "DET_MEM_PWR_STATE", 0, 1, &umr_bitfield_default },
};
static struct umr_bitfield mmHUBPRET1_HUBPRET_READ_LINE_CTRL0[] = {
	 { "PIPE_READ_LINE_INTERVAL_IN_NONACTIVE", 0, 15, &umr_bitfield_default },
	 { "PIPE_READ_LINE_VBLANK_MAXIMUM", 16, 29, &umr_bitfield_default },
};
static struct umr_bitfield mmHUBPRET1_HUBPRET_READ_LINE_CTRL1[] = {
	 { "PIPE_READ_LINE_REPORTED_WHEN_REQ_DISABLED", 0, 13, &umr_bitfield_default },
	 { "HUBPRET_READ_LINE_CTRL1_SPARE", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmHUBPRET1_HUBPRET_READ_LINE0[] = {
	 { "PIPE_READ_LINE0_START", 0, 13, &umr_bitfield_default },
	 { "PIPE_READ_LINE0_END", 16, 29, &umr_bitfield_default },
};
static struct umr_bitfield mmHUBPRET1_HUBPRET_READ_LINE1[] = {
	 { "PIPE_READ_LINE1_START", 0, 13, &umr_bitfield_default },
	 { "PIPE_READ_LINE1_END", 16, 29, &umr_bitfield_default },
};
static struct umr_bitfield mmHUBPRET1_HUBPRET_INTERRUPT[] = {
	 { "PIPE_VBLANK_INT_MASK", 0, 0, &umr_bitfield_default },
	 { "PIPE_READ_LINE0_INT_MASK", 1, 1, &umr_bitfield_default },
	 { "PIPE_READ_LINE1_INT_MASK", 2, 2, &umr_bitfield_default },
	 { "PIPE_VBLANK_INT_TYPE", 4, 4, &umr_bitfield_default },
	 { "PIPE_READ_LINE0_INT_TYPE", 5, 5, &umr_bitfield_default },
	 { "PIPE_READ_LINE1_INT_TYPE", 6, 6, &umr_bitfield_default },
	 { "PIPE_VBLANK_INT_CLEAR", 8, 8, &umr_bitfield_default },
	 { "PIPE_READ_LINE0_INT_CLEAR", 9, 9, &umr_bitfield_default },
	 { "PIPE_READ_LINE1_INT_CLEAR", 10, 10, &umr_bitfield_default },
	 { "PIPE_VBLANK_STATUS", 12, 12, &umr_bitfield_default },
	 { "PIPE_READ_LINE0_STATUS", 13, 13, &umr_bitfield_default },
	 { "PIPE_READ_LINE1_STATUS", 14, 14, &umr_bitfield_default },
	 { "PIPE_VBLANK_INT_STATUS", 16, 16, &umr_bitfield_default },
	 { "PIPE_READ_LINE0_INT_STATUS", 17, 17, &umr_bitfield_default },
	 { "PIPE_READ_LINE1_INT_STATUS", 18, 18, &umr_bitfield_default },
};
static struct umr_bitfield mmHUBPRET1_HUBPRET_READ_LINE_VALUE[] = {
	 { "PIPE_READ_LINE", 0, 13, &umr_bitfield_default },
	 { "PIPE_READ_LINE_SNAPSHOT", 16, 29, &umr_bitfield_default },
};
static struct umr_bitfield mmHUBPRET1_HUBPRET_READ_LINE_STATUS[] = {
	 { "PIPE_READ_VBLANK", 0, 0, &umr_bitfield_default },
	 { "PIPE_READ_LINE0_INSIDE", 4, 4, &umr_bitfield_default },
	 { "PIPE_READ_LINE0_OUTSIDE", 5, 5, &umr_bitfield_default },
	 { "PIPE_READ_LINE1_INSIDE", 8, 8, &umr_bitfield_default },
	 { "PIPE_READ_LINE1_OUTSIDE", 10, 10, &umr_bitfield_default },
};
static struct umr_bitfield mmCURSOR1_CURSOR_CONTROL[] = {
	 { "CURSOR_ENABLE", 0, 0, &umr_bitfield_default },
	 { "CURSOR_MODE", 8, 9, &umr_bitfield_default },
	 { "CURSOR_SNOOP", 13, 13, &umr_bitfield_default },
	 { "CURSOR_SYSTEM", 14, 14, &umr_bitfield_default },
	 { "CURSOR_PITCH", 16, 17, &umr_bitfield_default },
	 { "CURSOR_XY_POSITION_ROTATION_AND_MIRRORING_BYPASS", 20, 20, &umr_bitfield_default },
	 { "CURSOR_LINES_PER_CHUNK", 24, 28, &umr_bitfield_default },
	 { "CURSOR_PERFMON_LATENCY_MEASURE_EN", 30, 30, &umr_bitfield_default },
	 { "CURSOR_PERFMON_LATENCY_MEASURE_SEL", 31, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmCURSOR1_CURSOR_SURFACE_ADDRESS[] = {
	 { "CURSOR_SURFACE_ADDRESS", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmCURSOR1_CURSOR_SURFACE_ADDRESS_HIGH[] = {
	 { "CURSOR_SURFACE_ADDRESS_HIGH", 0, 15, &umr_bitfield_default },
};
static struct umr_bitfield mmCURSOR1_CURSOR_SIZE[] = {
	 { "CURSOR_HEIGHT", 0, 8, &umr_bitfield_default },
	 { "CURSOR_WIDTH", 16, 24, &umr_bitfield_default },
};
static struct umr_bitfield mmCURSOR1_CURSOR_POSITION[] = {
	 { "CURSOR_Y_POSITION", 0, 13, &umr_bitfield_default },
	 { "CURSOR_X_POSITION", 16, 29, &umr_bitfield_default },
};
static struct umr_bitfield mmCURSOR1_CURSOR_HOT_SPOT[] = {
	 { "CURSOR_HOT_SPOT_Y", 0, 7, &umr_bitfield_default },
	 { "CURSOR_HOT_SPOT_X", 16, 23, &umr_bitfield_default },
};
static struct umr_bitfield mmCURSOR1_CURSOR_STEREO_CONTROL[] = {
	 { "CURSOR_STEREO_EN", 0, 0, &umr_bitfield_default },
	 { "CURSOR_PRIMARY_OFFSET", 4, 17, &umr_bitfield_default },
	 { "CURSOR_SECONDARY_OFFSET", 18, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmCURSOR1_CURSOR_DST_OFFSET[] = {
	 { "CURSOR_DST_X_OFFSET", 0, 12, &umr_bitfield_default },
};
static struct umr_bitfield mmCURSOR1_CURSOR_MEM_PWR_CTRL[] = {
	 { "CROB_MEM_PWR_FORCE", 0, 1, &umr_bitfield_default },
	 { "CROB_MEM_PWR_DIS", 2, 2, &umr_bitfield_default },
	 { "CROB_MEM_PWR_LS_MODE", 4, 5, &umr_bitfield_default },
};
static struct umr_bitfield mmCURSOR1_CURSOR_MEM_PWR_STATUS[] = {
	 { "CROB_MEM_PWR_STATE", 0, 1, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_PERFMON9_PERFCOUNTER_CNTL[] = {
	 { "PERFCOUNTER_EVENT_SEL", 0, 8, &umr_bitfield_default },
	 { "PERFCOUNTER_CVALUE_SEL", 9, 11, &umr_bitfield_default },
	 { "PERFCOUNTER_INC_MODE", 12, 14, &umr_bitfield_default },
	 { "PERFCOUNTER_HW_CNTL_SEL", 15, 15, &umr_bitfield_default },
	 { "PERFCOUNTER_RUNEN_MODE", 16, 16, &umr_bitfield_default },
	 { "PERFCOUNTER_CNTOFF_START_DIS", 22, 22, &umr_bitfield_default },
	 { "PERFCOUNTER_RESTART_EN", 23, 23, &umr_bitfield_default },
	 { "PERFCOUNTER_INT_EN", 24, 24, &umr_bitfield_default },
	 { "PERFCOUNTER_OFF_MASK", 25, 25, &umr_bitfield_default },
	 { "PERFCOUNTER_ACTIVE", 26, 26, &umr_bitfield_default },
	 { "PERFCOUNTER_CNTL_SEL", 29, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_PERFMON9_PERFCOUNTER_CNTL2[] = {
	 { "PERFCOUNTER_COUNTED_VALUE_TYPE", 0, 1, &umr_bitfield_default },
	 { "PERFCOUNTER_HW_STOP1_SEL", 2, 2, &umr_bitfield_default },
	 { "PERFCOUNTER_HW_STOP2_SEL", 3, 3, &umr_bitfield_default },
	 { "PERFCOUNTER_CNTOFF_SEL", 8, 13, &umr_bitfield_default },
	 { "PERFCOUNTER_CNTL2_SEL", 29, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_PERFMON9_PERFCOUNTER_STATE[] = {
	 { "PERFCOUNTER_CNT0_STATE", 0, 1, &umr_bitfield_default },
	 { "PERFCOUNTER_STATE_SEL0", 2, 2, &umr_bitfield_default },
	 { "PERFCOUNTER_CNT1_STATE", 4, 5, &umr_bitfield_default },
	 { "PERFCOUNTER_STATE_SEL1", 6, 6, &umr_bitfield_default },
	 { "PERFCOUNTER_CNT2_STATE", 8, 9, &umr_bitfield_default },
	 { "PERFCOUNTER_STATE_SEL2", 10, 10, &umr_bitfield_default },
	 { "PERFCOUNTER_CNT3_STATE", 12, 13, &umr_bitfield_default },
	 { "PERFCOUNTER_STATE_SEL3", 14, 14, &umr_bitfield_default },
	 { "PERFCOUNTER_CNT4_STATE", 16, 17, &umr_bitfield_default },
	 { "PERFCOUNTER_STATE_SEL4", 18, 18, &umr_bitfield_default },
	 { "PERFCOUNTER_CNT5_STATE", 20, 21, &umr_bitfield_default },
	 { "PERFCOUNTER_STATE_SEL5", 22, 22, &umr_bitfield_default },
	 { "PERFCOUNTER_CNT6_STATE", 24, 25, &umr_bitfield_default },
	 { "PERFCOUNTER_STATE_SEL6", 26, 26, &umr_bitfield_default },
	 { "PERFCOUNTER_CNT7_STATE", 28, 29, &umr_bitfield_default },
	 { "PERFCOUNTER_STATE_SEL7", 30, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_PERFMON9_PERFMON_CNTL[] = {
	 { "PERFMON_STATE", 0, 1, &umr_bitfield_default },
	 { "PERFMON_RPT_COUNT", 8, 27, &umr_bitfield_default },
	 { "PERFMON_CNTOFF_AND_OR", 28, 28, &umr_bitfield_default },
	 { "PERFMON_CNTOFF_INT_EN", 29, 29, &umr_bitfield_default },
	 { "PERFMON_CNTOFF_INT_STATUS", 30, 30, &umr_bitfield_default },
	 { "PERFMON_CNTOFF_INT_ACK", 31, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_PERFMON9_PERFMON_CNTL2[] = {
	 { "PERFMON_CNTOFF_INT_TYPE", 0, 0, &umr_bitfield_default },
	 { "PERFMON_CLK_ENABLE", 1, 1, &umr_bitfield_default },
	 { "PERFMON_RUN_ENABLE_START_SEL", 2, 9, &umr_bitfield_default },
	 { "PERFMON_RUN_ENABLE_STOP_SEL", 10, 17, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_PERFMON9_PERFMON_CVALUE_INT_MISC[] = {
	 { "PERFCOUNTER_INT0_STATUS", 0, 0, &umr_bitfield_default },
	 { "PERFCOUNTER_INT1_STATUS", 1, 1, &umr_bitfield_default },
	 { "PERFCOUNTER_INT2_STATUS", 2, 2, &umr_bitfield_default },
	 { "PERFCOUNTER_INT3_STATUS", 3, 3, &umr_bitfield_default },
	 { "PERFCOUNTER_INT4_STATUS", 4, 4, &umr_bitfield_default },
	 { "PERFCOUNTER_INT5_STATUS", 5, 5, &umr_bitfield_default },
	 { "PERFCOUNTER_INT6_STATUS", 6, 6, &umr_bitfield_default },
	 { "PERFCOUNTER_INT7_STATUS", 7, 7, &umr_bitfield_default },
	 { "PERFCOUNTER_INT0_ACK", 8, 8, &umr_bitfield_default },
	 { "PERFCOUNTER_INT1_ACK", 9, 9, &umr_bitfield_default },
	 { "PERFCOUNTER_INT2_ACK", 10, 10, &umr_bitfield_default },
	 { "PERFCOUNTER_INT3_ACK", 11, 11, &umr_bitfield_default },
	 { "PERFCOUNTER_INT4_ACK", 12, 12, &umr_bitfield_default },
	 { "PERFCOUNTER_INT5_ACK", 13, 13, &umr_bitfield_default },
	 { "PERFCOUNTER_INT6_ACK", 14, 14, &umr_bitfield_default },
	 { "PERFCOUNTER_INT7_ACK", 15, 15, &umr_bitfield_default },
	 { "PERFMON_CVALUE_HI", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_PERFMON9_PERFMON_CVALUE_LOW[] = {
	 { "PERFMON_CVALUE_LOW", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_PERFMON9_PERFMON_HI[] = {
	 { "PERFMON_HI", 0, 15, &umr_bitfield_default },
	 { "PERFMON_READ_SEL", 29, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_PERFMON9_PERFMON_LOW[] = {
	 { "PERFMON_LOW", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmHUBP2_DCSURF_SURFACE_CONFIG[] = {
	 { "SURFACE_PIXEL_FORMAT", 0, 6, &umr_bitfield_default },
	 { "ROTATION_ANGLE", 8, 9, &umr_bitfield_default },
	 { "H_MIRROR_EN", 10, 10, &umr_bitfield_default },
};
static struct umr_bitfield mmHUBP2_DCSURF_ADDR_CONFIG[] = {
	 { "NUM_PIPES", 0, 2, &umr_bitfield_default },
	 { "NUM_BANKS", 3, 5, &umr_bitfield_default },
	 { "PIPE_INTERLEAVE", 6, 7, &umr_bitfield_default },
	 { "NUM_SE", 8, 9, &umr_bitfield_default },
	 { "NUM_RB_PER_SE", 10, 11, &umr_bitfield_default },
	 { "MAX_COMPRESSED_FRAGS", 12, 13, &umr_bitfield_default },
};
static struct umr_bitfield mmHUBP2_DCSURF_TILING_CONFIG[] = {
	 { "SW_MODE", 0, 4, &umr_bitfield_default },
	 { "DIM_TYPE", 7, 8, &umr_bitfield_default },
	 { "META_LINEAR", 9, 9, &umr_bitfield_default },
	 { "RB_ALIGNED", 10, 10, &umr_bitfield_default },
	 { "PIPE_ALIGNED", 11, 11, &umr_bitfield_default },
};
static struct umr_bitfield mmHUBP2_DCSURF_PRI_VIEWPORT_START[] = {
	 { "PRI_VIEWPORT_X_START", 0, 13, &umr_bitfield_default },
	 { "PRI_VIEWPORT_Y_START", 16, 29, &umr_bitfield_default },
};
static struct umr_bitfield mmHUBP2_DCSURF_PRI_VIEWPORT_DIMENSION[] = {
	 { "PRI_VIEWPORT_WIDTH", 0, 13, &umr_bitfield_default },
	 { "PRI_VIEWPORT_HEIGHT", 16, 29, &umr_bitfield_default },
};
static struct umr_bitfield mmHUBP2_DCSURF_PRI_VIEWPORT_START_C[] = {
	 { "PRI_VIEWPORT_X_START_C", 0, 13, &umr_bitfield_default },
	 { "PRI_VIEWPORT_Y_START_C", 16, 29, &umr_bitfield_default },
};
static struct umr_bitfield mmHUBP2_DCSURF_PRI_VIEWPORT_DIMENSION_C[] = {
	 { "PRI_VIEWPORT_WIDTH_C", 0, 13, &umr_bitfield_default },
	 { "PRI_VIEWPORT_HEIGHT_C", 16, 29, &umr_bitfield_default },
};
static struct umr_bitfield mmHUBP2_DCSURF_SEC_VIEWPORT_START[] = {
	 { "SEC_VIEWPORT_X_START", 0, 13, &umr_bitfield_default },
	 { "SEC_VIEWPORT_Y_START", 16, 29, &umr_bitfield_default },
};
static struct umr_bitfield mmHUBP2_DCSURF_SEC_VIEWPORT_DIMENSION[] = {
	 { "SEC_VIEWPORT_WIDTH", 0, 13, &umr_bitfield_default },
	 { "SEC_VIEWPORT_HEIGHT", 16, 29, &umr_bitfield_default },
};
static struct umr_bitfield mmHUBP2_DCSURF_SEC_VIEWPORT_START_C[] = {
	 { "SEC_VIEWPORT_X_START_C", 0, 13, &umr_bitfield_default },
	 { "SEC_VIEWPORT_Y_START_C", 16, 29, &umr_bitfield_default },
};
static struct umr_bitfield mmHUBP2_DCSURF_SEC_VIEWPORT_DIMENSION_C[] = {
	 { "SEC_VIEWPORT_WIDTH_C", 0, 13, &umr_bitfield_default },
	 { "SEC_VIEWPORT_HEIGHT_C", 16, 29, &umr_bitfield_default },
};
static struct umr_bitfield mmHUBP2_DCHUBP_REQ_SIZE_CONFIG[] = {
	 { "SWATH_HEIGHT", 0, 2, &umr_bitfield_default },
	 { "PTE_ROW_HEIGHT_LINEAR", 4, 6, &umr_bitfield_default },
	 { "CHUNK_SIZE", 8, 10, &umr_bitfield_default },
	 { "MIN_CHUNK_SIZE", 11, 12, &umr_bitfield_default },
	 { "META_CHUNK_SIZE", 16, 17, &umr_bitfield_default },
	 { "MIN_META_CHUNK_SIZE", 18, 19, &umr_bitfield_default },
	 { "DPTE_GROUP_SIZE", 20, 22, &umr_bitfield_default },
	 { "MPTE_GROUP_SIZE", 24, 26, &umr_bitfield_default },
};
static struct umr_bitfield mmHUBP2_DCHUBP_REQ_SIZE_CONFIG_C[] = {
	 { "SWATH_HEIGHT_C", 0, 2, &umr_bitfield_default },
	 { "PTE_ROW_HEIGHT_LINEAR_C", 4, 6, &umr_bitfield_default },
	 { "CHUNK_SIZE_C", 8, 10, &umr_bitfield_default },
	 { "MIN_CHUNK_SIZE_C", 11, 12, &umr_bitfield_default },
	 { "META_CHUNK_SIZE_C", 16, 17, &umr_bitfield_default },
	 { "MIN_META_CHUNK_SIZE_C", 18, 19, &umr_bitfield_default },
	 { "DPTE_GROUP_SIZE_C", 20, 22, &umr_bitfield_default },
	 { "MPTE_GROUP_SIZE_C", 24, 26, &umr_bitfield_default },
};
static struct umr_bitfield mmHUBP2_DCHUBP_CNTL[] = {
	 { "HUBP_BLANK_EN", 0, 0, &umr_bitfield_default },
	 { "HUBP_NO_OUTSTANDING_REQ", 1, 1, &umr_bitfield_default },
	 { "HUBP_DISABLE", 2, 2, &umr_bitfield_default },
	 { "HUBP_IN_BLANK", 3, 3, &umr_bitfield_default },
	 { "HUBP_VTG_SEL", 4, 7, &umr_bitfield_default },
	 { "HUBP_TTU_DISABLE", 12, 12, &umr_bitfield_default },
	 { "HUBP_TTU_MODE", 13, 15, &umr_bitfield_default },
	 { "HUBP_UNDERFLOW_STATUS", 28, 30, &umr_bitfield_default },
	 { "HUBP_UNDERFLOW_CLEAR", 31, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmHUBP2_HUBP_CLK_CNTL[] = {
	 { "HUBP_CLOCK_ENABLE", 0, 0, &umr_bitfield_default },
	 { "HUBP_DISPCLK_R_GATE_DIS", 4, 4, &umr_bitfield_default },
	 { "HUBP_DPPCLK_G_GATE_DIS", 8, 8, &umr_bitfield_default },
	 { "HUBP_DCFCLK_R_GATE_DIS", 12, 12, &umr_bitfield_default },
	 { "HUBP_DCFCLK_G_GATE_DIS", 16, 16, &umr_bitfield_default },
	 { "HUBP_DISPCLK_R_CLOCK_ON", 20, 20, &umr_bitfield_default },
	 { "HUBP_DPPCLK_G_CLOCK_ON", 21, 21, &umr_bitfield_default },
	 { "HUBP_DCFCLK_R_CLOCK_ON", 22, 22, &umr_bitfield_default },
	 { "HUBP_DCFCLK_G_CLOCK_ON", 23, 23, &umr_bitfield_default },
	 { "HUBP_TEST_CLK_SEL", 28, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmHUBP2_DCHUBP_VMPG_CONFIG[] = {
	 { "VMPG_SIZE", 0, 0, &umr_bitfield_default },
};
static struct umr_bitfield mmHUBP2_HUBPREQ_DEBUG_DB[] = {
	 { "HUBPREQ_DEBUG", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmHUBP2_HUBP_MEASURE_WIN_CTRL_DCFCLK[] = {
	 { "HUBP_MEASURE_WIN_EN_DCFCLK", 0, 0, &umr_bitfield_default },
	 { "HUBP_MEASURE_WIN_PERIOD_M1_DCFCLK", 4, 11, &umr_bitfield_default },
	 { "HUBP_PERFMON_START_SEL_DCFCLK", 12, 16, &umr_bitfield_default },
	 { "HUBP_PERFMON_STOP_SEL_DCFCLK", 20, 24, &umr_bitfield_default },
	 { "HUBP_MEASURE_WIN_MODE_DCFCLK", 28, 29, &umr_bitfield_default },
};
static struct umr_bitfield mmHUBP2_HUBP_MEASURE_WIN_CTRL_DPPCLK[] = {
	 { "HUBP_MEASURE_WIN_EN_DPPCLK", 0, 0, &umr_bitfield_default },
	 { "HUBP_MEASURE_WIN_SRC_SEL_DPPCLK", 1, 1, &umr_bitfield_default },
	 { "HUBP_MEASURE_WIN_PERIOD_M1_DPPCLK", 4, 11, &umr_bitfield_default },
	 { "HUBP_PERFMON_START_SEL_DPPCLK", 12, 16, &umr_bitfield_default },
	 { "HUBP_PERFMON_STOP_SEL_DPPCLK", 20, 24, &umr_bitfield_default },
};
static struct umr_bitfield mmHUBPREQ2_DCSURF_SURFACE_PITCH[] = {
	 { "PITCH", 0, 13, &umr_bitfield_default },
	 { "META_PITCH", 16, 29, &umr_bitfield_default },
};
static struct umr_bitfield mmHUBPREQ2_DCSURF_SURFACE_PITCH_C[] = {
	 { "PITCH_C", 0, 13, &umr_bitfield_default },
	 { "META_PITCH_C", 16, 29, &umr_bitfield_default },
};
static struct umr_bitfield mmHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS[] = {
	 { "PRIMARY_SURFACE_ADDRESS", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH[] = {
	 { "PRIMARY_SURFACE_ADDRESS_HIGH", 0, 15, &umr_bitfield_default },
};
static struct umr_bitfield mmHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_C[] = {
	 { "PRIMARY_SURFACE_ADDRESS_C", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C[] = {
	 { "PRIMARY_SURFACE_ADDRESS_HIGH_C", 0, 15, &umr_bitfield_default },
};
static struct umr_bitfield mmHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS[] = {
	 { "SECONDARY_SURFACE_ADDRESS", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH[] = {
	 { "SECONDARY_SURFACE_ADDRESS_HIGH", 0, 15, &umr_bitfield_default },
};
static struct umr_bitfield mmHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_C[] = {
	 { "SECONDARY_SURFACE_ADDRESS_C", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C[] = {
	 { "SECONDARY_SURFACE_ADDRESS_HIGH_C", 0, 15, &umr_bitfield_default },
};
static struct umr_bitfield mmHUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS[] = {
	 { "PRIMARY_META_SURFACE_ADDRESS", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmHUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH[] = {
	 { "PRIMARY_META_SURFACE_ADDRESS_HIGH", 0, 15, &umr_bitfield_default },
};
static struct umr_bitfield mmHUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C[] = {
	 { "PRIMARY_META_SURFACE_ADDRESS_C", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmHUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C[] = {
	 { "PRIMARY_META_SURFACE_ADDRESS_HIGH_C", 0, 15, &umr_bitfield_default },
};
static struct umr_bitfield mmHUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS[] = {
	 { "SECONDARY_META_SURFACE_ADDRESS", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmHUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH[] = {
	 { "SECONDARY_META_SURFACE_ADDRESS_HIGH", 0, 15, &umr_bitfield_default },
};
static struct umr_bitfield mmHUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C[] = {
	 { "SECONDARY_META_SURFACE_ADDRESS_C", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmHUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C[] = {
	 { "SECONDARY_META_SURFACE_ADDRESS_HIGH_C", 0, 15, &umr_bitfield_default },
};
static struct umr_bitfield mmHUBPREQ2_DCSURF_SURFACE_CONTROL[] = {
	 { "PRIMARY_SURFACE_DCC_EN", 1, 1, &umr_bitfield_default },
	 { "PRIMARY_SURFACE_DCC_IND_64B_BLK", 2, 2, &umr_bitfield_default },
	 { "PRIMARY_SURFACE_DCC_IND_64B_BLK_C", 5, 5, &umr_bitfield_default },
	 { "SECONDARY_SURFACE_DCC_EN", 9, 9, &umr_bitfield_default },
	 { "SECONDARY_SURFACE_DCC_IND_64B_BLK", 10, 10, &umr_bitfield_default },
	 { "SECONDARY_SURFACE_DCC_IND_64B_BLK_C", 13, 13, &umr_bitfield_default },
};
static struct umr_bitfield mmHUBPREQ2_DCSURF_FLIP_CONTROL[] = {
	 { "SURFACE_UPDATE_LOCK", 0, 0, &umr_bitfield_default },
	 { "SURFACE_FLIP_TYPE", 1, 1, &umr_bitfield_default },
	 { "SURFACE_FLIP_VUPDATE_SKIP_NUM", 4, 7, &umr_bitfield_default },
	 { "SURFACE_FLIP_MODE_FOR_STEREOSYNC", 12, 13, &umr_bitfield_default },
	 { "SURFACE_FLIP_IN_STEREOSYNC", 16, 16, &umr_bitfield_default },
	 { "SURFACE_FLIP_STEREO_SELECT_DISABLE", 17, 17, &umr_bitfield_default },
	 { "SURFACE_FLIP_STEREO_SELECT_POLARITY", 18, 18, &umr_bitfield_default },
	 { "SURFACE_FLIP_PENDING_DELAY", 20, 29, &umr_bitfield_default },
	 { "SURFACE_UPDATE_PENDING", 30, 30, &umr_bitfield_default },
	 { "SURFACE_FLIP_PENDING", 31, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmHUBPREQ2_DCSURF_FLIP_CONTROL2[] = {
	 { "SURFACE_UPDATE_FLIP_PENDING_MIN_TIME", 0, 7, &umr_bitfield_default },
	 { "SURFACE_UPDATE_PENDING_HIGH_EXTEND_ENABLE", 12, 12, &umr_bitfield_default },
	 { "SURFACE_FLIP_PENDING_HIGH_EXTEND_ENABLE", 13, 13, &umr_bitfield_default },
};
static struct umr_bitfield mmHUBPREQ2_DCSURF_FRAME_PACING_CONTROL[] = {
	 { "SURFACE_FRAME_PACING_ENABLE", 0, 0, &umr_bitfield_default },
	 { "SURFACE_FRAME_PACING_MODE", 1, 1, &umr_bitfield_default },
	 { "SURFACE_FRAME_PACING_QUEUE_RESET", 8, 8, &umr_bitfield_default },
	 { "SURFACE_FRAME_PACING_QUEUE_FREE_ENTRY", 24, 26, &umr_bitfield_default },
};
static struct umr_bitfield mmHUBPREQ2_DCSURF_FRAME_PACING_TIME[] = {
	 { "SURFACE_FRAME_PACING_TIME", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmHUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT[] = {
	 { "SURFACE_FLIP_INT_MASK", 0, 0, &umr_bitfield_default },
	 { "SURFACE_FLIP_INT_TYPE", 1, 1, &umr_bitfield_default },
	 { "SURFACE_FLIP_AWAY_INT_MASK", 2, 2, &umr_bitfield_default },
	 { "SURFACE_FLIP_AWAY_INT_TYPE", 3, 3, &umr_bitfield_default },
	 { "SURFACE_FLIP_CLEAR", 8, 8, &umr_bitfield_default },
	 { "SURFACE_FLIP_AWAY_CLEAR", 9, 9, &umr_bitfield_default },
	 { "SURFACE_FLIP_OCCURRED", 16, 16, &umr_bitfield_default },
	 { "SURFACE_FLIP_INT_STATUS", 17, 17, &umr_bitfield_default },
	 { "SURFACE_FLIP_AWAY_OCCURRED", 18, 18, &umr_bitfield_default },
	 { "SURFACE_FLIP_AWAY_INT_STATUS", 19, 19, &umr_bitfield_default },
};
static struct umr_bitfield mmHUBPREQ2_DCSURF_SURFACE_INUSE[] = {
	 { "SURFACE_INUSE_ADDRESS", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmHUBPREQ2_DCSURF_SURFACE_INUSE_HIGH[] = {
	 { "SURFACE_INUSE_ADDRESS_HIGH", 0, 15, &umr_bitfield_default },
};
static struct umr_bitfield mmHUBPREQ2_DCSURF_SURFACE_INUSE_C[] = {
	 { "SURFACE_INUSE_ADDRESS_C", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmHUBPREQ2_DCSURF_SURFACE_INUSE_HIGH_C[] = {
	 { "SURFACE_INUSE_ADDRESS_HIGH_C", 0, 15, &umr_bitfield_default },
};
static struct umr_bitfield mmHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE[] = {
	 { "SURFACE_EARLIEST_INUSE_ADDRESS", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_HIGH[] = {
	 { "SURFACE_EARLIEST_INUSE_ADDRESS_HIGH", 0, 15, &umr_bitfield_default },
};
static struct umr_bitfield mmHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_C[] = {
	 { "SURFACE_EARLIEST_INUSE_ADDRESS_C", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C[] = {
	 { "SURFACE_EARLIEST_INUSE_ADDRESS_HIGH_C", 0, 15, &umr_bitfield_default },
};
static struct umr_bitfield mmHUBPREQ2_DCN_EXPANSION_MODE[] = {
	 { "DRQ_EXPANSION_MODE", 0, 1, &umr_bitfield_default },
	 { "CRQ_EXPANSION_MODE", 2, 3, &umr_bitfield_default },
	 { "MRQ_EXPANSION_MODE", 4, 5, &umr_bitfield_default },
	 { "PRQ_EXPANSION_MODE", 6, 7, &umr_bitfield_default },
};
static struct umr_bitfield mmHUBPREQ2_DCN_TTU_QOS_WM[] = {
	 { "QoS_LEVEL_LOW_WM", 0, 13, &umr_bitfield_default },
	 { "QoS_LEVEL_HIGH_WM", 16, 29, &umr_bitfield_default },
};
static struct umr_bitfield mmHUBPREQ2_DCN_GLOBAL_TTU_CNTL[] = {
	 { "MIN_TTU_VBLANK", 0, 23, &umr_bitfield_default },
	 { "QoS_LEVEL_FLIP", 28, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmHUBPREQ2_DCN_SURF0_TTU_CNTL0[] = {
	 { "REFCYC_PER_REQ_DELIVERY", 0, 22, &umr_bitfield_default },
	 { "QoS_LEVEL_FIXED", 24, 27, &umr_bitfield_default },
	 { "QoS_RAMP_DISABLE", 28, 28, &umr_bitfield_default },
};
static struct umr_bitfield mmHUBPREQ2_DCN_SURF0_TTU_CNTL1[] = {
	 { "REFCYC_PER_REQ_DELIVERY_PRE", 0, 22, &umr_bitfield_default },
};
static struct umr_bitfield mmHUBPREQ2_DCN_SURF1_TTU_CNTL0[] = {
	 { "REFCYC_PER_REQ_DELIVERY", 0, 22, &umr_bitfield_default },
	 { "QoS_LEVEL_FIXED", 24, 27, &umr_bitfield_default },
	 { "QoS_RAMP_DISABLE", 28, 28, &umr_bitfield_default },
};
static struct umr_bitfield mmHUBPREQ2_DCN_SURF1_TTU_CNTL1[] = {
	 { "REFCYC_PER_REQ_DELIVERY_PRE", 0, 22, &umr_bitfield_default },
};
static struct umr_bitfield mmHUBPREQ2_DCN_CUR0_TTU_CNTL0[] = {
	 { "REFCYC_PER_REQ_DELIVERY", 0, 22, &umr_bitfield_default },
	 { "QoS_LEVEL_FIXED", 24, 27, &umr_bitfield_default },
	 { "QoS_RAMP_DISABLE", 28, 28, &umr_bitfield_default },
};
static struct umr_bitfield mmHUBPREQ2_DCN_CUR0_TTU_CNTL1[] = {
	 { "REFCYC_PER_REQ_DELIVERY_PRE", 0, 22, &umr_bitfield_default },
};
static struct umr_bitfield mmHUBPREQ2_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_LSB[] = {
	 { "MC_VM_SYSTEM_APERTURE_LOW_ADDR_LSB", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmHUBPREQ2_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_MSB[] = {
	 { "MC_VM_SYSTEM_APERTURE_LOW_ADDR_MSB", 0, 3, &umr_bitfield_default },
};
static struct umr_bitfield mmHUBPREQ2_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_LSB[] = {
	 { "MC_VM_SYSTEM_APERTURE_HIGH_ADDR_LSB", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmHUBPREQ2_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_MSB[] = {
	 { "MC_VM_SYSTEM_APERTURE_HIGH_ADDR_MSB", 0, 3, &umr_bitfield_default },
};
static struct umr_bitfield mmHUBPREQ2_DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB[] = {
	 { "MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmHUBPREQ2_DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB[] = {
	 { "MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB", 0, 3, &umr_bitfield_default },
	 { "MC_VM_SYSTEM_APERTURE_DEFAULT_SYSTEM", 28, 28, &umr_bitfield_default },
	 { "MC_VM_SYSTEM_APERTURE_DEFAULT_SNOOP", 29, 29, &umr_bitfield_default },
};
static struct umr_bitfield mmHUBPREQ2_DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_LSB[] = {
	 { "VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_LSB", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmHUBPREQ2_DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB[] = {
	 { "VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB", 0, 3, &umr_bitfield_default },
	 { "VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_SYSTEM", 28, 28, &umr_bitfield_default },
	 { "VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_SNOOP", 29, 29, &umr_bitfield_default },
	 { "VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_TMZ", 30, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmHUBPREQ2_DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LSB[] = {
	 { "VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LSB", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmHUBPREQ2_DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_MSB[] = {
	 { "VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_MSB", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmHUBPREQ2_DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LSB[] = {
	 { "VM_CONTEXT0_PAGE_TABLE_START_ADDR_LSB", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmHUBPREQ2_DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_MSB[] = {
	 { "VM_CONTEXT0_PAGE_TABLE_START_ADDR_MSB", 0, 3, &umr_bitfield_default },
};
static struct umr_bitfield mmHUBPREQ2_DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LSB[] = {
	 { "VM_CONTEXT0_PAGE_TABLE_END_ADDR_LSB", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmHUBPREQ2_DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_MSB[] = {
	 { "VM_CONTEXT0_PAGE_TABLE_END_ADDR_MSB", 0, 3, &umr_bitfield_default },
};
static struct umr_bitfield mmHUBPREQ2_DCN_VM_CONTEXT0_STATUS[] = {
	 { "DCN_VM_CONTEXT0_ERROR_STATUS", 0, 15, &umr_bitfield_default },
	 { "DCN_VM_CONTEXT0_PROTECTION_FAULT_ADDR_MSB", 24, 27, &umr_bitfield_default },
	 { "DCN_VM_CONTEXT0_ERROR_STATUS_MODE", 30, 30, &umr_bitfield_default },
	 { "DCN_VM_CONTEXT0_ERROR_STATUS_CLEAR", 31, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmHUBPREQ2_DCN_VM_CONTEXT0_PROTECTION_FAULT_ADDR_LSB[] = {
	 { "DCN_VM_CONTEXT0_PROTECTION_FAULT_ADDR_LSB", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmHUBPREQ2_DCN_VM_CONTEXT0_CNTL[] = {
	 { "PAGE_TABLE_DEPTH", 1, 2, &umr_bitfield_default },
	 { "RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT", 3, 3, &umr_bitfield_default },
	 { "RANGE_PROTECTION_FAULT_ENABLE_DEFAULT", 4, 4, &umr_bitfield_default },
	 { "VALID_PROTECTION_FAULT_ENABLE_INTERRUPT", 12, 12, &umr_bitfield_default },
	 { "VALID_PROTECTION_FAULT_ENABLE_DEFAULT", 13, 13, &umr_bitfield_default },
	 { "READ_PROTECTION_FAULT_ENABLE_INTERRUPT", 15, 15, &umr_bitfield_default },
	 { "READ_PROTECTION_FAULT_ENABLE_DEFAULT", 16, 16, &umr_bitfield_default },
};
static struct umr_bitfield mmHUBPREQ2_DCN_VM_MX_L1_TLB_CNTL[] = {
	 { "ENABLE_L1_TLB", 0, 0, &umr_bitfield_default },
	 { "SYSTEM_ACCESS_MODE", 3, 4, &umr_bitfield_default },
};
static struct umr_bitfield mmHUBPREQ2_BLANK_OFFSET_0[] = {
	 { "REFCYC_H_BLANK_END", 0, 12, &umr_bitfield_default },
	 { "DLG_V_BLANK_END", 16, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmHUBPREQ2_BLANK_OFFSET_1[] = {
	 { "MIN_DST_Y_NEXT_START", 0, 17, &umr_bitfield_default },
};
static struct umr_bitfield mmHUBPREQ2_DST_DIMENSIONS[] = {
	 { "REFCYC_PER_HTOTAL", 0, 20, &umr_bitfield_default },
};
static struct umr_bitfield mmHUBPREQ2_DST_AFTER_SCALER[] = {
	 { "REFCYC_X_AFTER_SCALER", 0, 12, &umr_bitfield_default },
	 { "DST_Y_AFTER_SCALER", 16, 18, &umr_bitfield_default },
};
static struct umr_bitfield mmHUBPREQ2_PREFETCH_SETTINS[] = {
	 { "VRATIO_PREFETCH", 0, 20, &umr_bitfield_default },
	 { "DST_Y_PREFETCH", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmHUBPREQ2_PREFETCH_SETTINS_C[] = {
	 { "VRATIO_PREFETCH_C", 0, 20, &umr_bitfield_default },
};
static struct umr_bitfield mmHUBPREQ2_VBLANK_PARAMETERS_0[] = {
	 { "DST_Y_PER_VM_VBLANK", 0, 4, &umr_bitfield_default },
	 { "DST_Y_PER_ROW_VBLANK", 8, 13, &umr_bitfield_default },
};
static struct umr_bitfield mmHUBPREQ2_VBLANK_PARAMETERS_1[] = {
	 { "REFCYC_PER_PTE_GROUP_VBLANK_L", 0, 22, &umr_bitfield_default },
};
static struct umr_bitfield mmHUBPREQ2_VBLANK_PARAMETERS_2[] = {
	 { "REFCYC_PER_PTE_GROUP_VBLANK_C", 0, 22, &umr_bitfield_default },
};
static struct umr_bitfield mmHUBPREQ2_VBLANK_PARAMETERS_3[] = {
	 { "REFCYC_PER_META_CHUNK_VBLANK_L", 0, 22, &umr_bitfield_default },
};
static struct umr_bitfield mmHUBPREQ2_VBLANK_PARAMETERS_4[] = {
	 { "REFCYC_PER_META_CHUNK_VBLANK_C", 0, 22, &umr_bitfield_default },
};
static struct umr_bitfield mmHUBPREQ2_NOM_PARAMETERS_0[] = {
	 { "DST_Y_PER_PTE_ROW_NOM_L", 0, 16, &umr_bitfield_default },
};
static struct umr_bitfield mmHUBPREQ2_NOM_PARAMETERS_1[] = {
	 { "REFCYC_PER_PTE_GROUP_NOM_L", 0, 22, &umr_bitfield_default },
};
static struct umr_bitfield mmHUBPREQ2_NOM_PARAMETERS_2[] = {
	 { "DST_Y_PER_PTE_ROW_NOM_C", 0, 16, &umr_bitfield_default },
};
static struct umr_bitfield mmHUBPREQ2_NOM_PARAMETERS_3[] = {
	 { "REFCYC_PER_PTE_GROUP_NOM_C", 0, 22, &umr_bitfield_default },
};
static struct umr_bitfield mmHUBPREQ2_NOM_PARAMETERS_4[] = {
	 { "DST_Y_PER_META_ROW_NOM_L", 0, 16, &umr_bitfield_default },
};
static struct umr_bitfield mmHUBPREQ2_NOM_PARAMETERS_5[] = {
	 { "REFCYC_PER_META_CHUNK_NOM_L", 0, 22, &umr_bitfield_default },
};
static struct umr_bitfield mmHUBPREQ2_NOM_PARAMETERS_6[] = {
	 { "DST_Y_PER_META_ROW_NOM_C", 0, 16, &umr_bitfield_default },
};
static struct umr_bitfield mmHUBPREQ2_NOM_PARAMETERS_7[] = {
	 { "REFCYC_PER_META_CHUNK_NOM_C", 0, 22, &umr_bitfield_default },
};
static struct umr_bitfield mmHUBPREQ2_PER_LINE_DELIVERY_PRE[] = {
	 { "REFCYC_PER_LINE_DELIVERY_PRE_L", 0, 12, &umr_bitfield_default },
	 { "REFCYC_PER_LINE_DELIVERY_PRE_C", 16, 28, &umr_bitfield_default },
};
static struct umr_bitfield mmHUBPREQ2_PER_LINE_DELIVERY[] = {
	 { "REFCYC_PER_LINE_DELIVERY_L", 0, 12, &umr_bitfield_default },
	 { "REFCYC_PER_LINE_DELIVERY_C", 16, 28, &umr_bitfield_default },
};
static struct umr_bitfield mmHUBPREQ2_CURSOR_SETTINS[] = {
	 { "CURSOR0_DST_Y_OFFSET", 0, 7, &umr_bitfield_default },
	 { "CURSOR0_CHUNK_HDL_ADJUST", 8, 9, &umr_bitfield_default },
};
static struct umr_bitfield mmHUBPREQ2_REF_FREQ_TO_PIX_FREQ[] = {
	 { "REF_FREQ_TO_PIX_FREQ", 0, 20, &umr_bitfield_default },
};
static struct umr_bitfield mmHUBPREQ2_HUBPREQ_MEM_PWR_CTRL[] = {
	 { "REQ_DPTE_MEM_PWR_FORCE", 0, 1, &umr_bitfield_default },
	 { "REQ_DPTE_MEM_PWR_DIS", 2, 2, &umr_bitfield_default },
	 { "REQ_MPTE_MEM_PWR_FORCE", 4, 5, &umr_bitfield_default },
	 { "REQ_MPTE_MEM_PWR_DIS", 6, 6, &umr_bitfield_default },
	 { "REQ_META_MEM_PWR_FORCE", 8, 9, &umr_bitfield_default },
	 { "REQ_META_MEM_PWR_DIS", 10, 10, &umr_bitfield_default },
	 { "REQ_DPTE_FINE_GRAIN_DIS", 16, 16, &umr_bitfield_default },
	 { "REQ_DPTE_FINE_GRAIN_DIS_C", 17, 17, &umr_bitfield_default },
	 { "REQ_META_FINE_GRAIN_DIS", 20, 20, &umr_bitfield_default },
	 { "REQ_META_FINE_GRAIN_DIS_C", 21, 21, &umr_bitfield_default },
	 { "REQ_MPTE_FINE_GRAIN_DIS", 24, 24, &umr_bitfield_default },
};
static struct umr_bitfield mmHUBPREQ2_HUBPREQ_MEM_PWR_STATUS[] = {
	 { "REQ_DPTE_MEM_PWR_STATE", 0, 1, &umr_bitfield_default },
	 { "REQ_MPTE_MEM_PWR_STATE", 2, 3, &umr_bitfield_default },
	 { "REQ_META_MEM_PWR_STATE", 4, 5, &umr_bitfield_default },
};
static struct umr_bitfield mmHUBPRET2_HUBPRET_CONTROL[] = {
	 { "DET_BUF_PLANE1_BASE_ADDRESS", 0, 11, &umr_bitfield_default },
	 { "PACK_3TO2_ELEMENT_DISABLE", 12, 12, &umr_bitfield_default },
	 { "CROSSBAR_SRC_ALPHA", 16, 17, &umr_bitfield_default },
	 { "CROSSBAR_SRC_Y_G", 18, 19, &umr_bitfield_default },
	 { "CROSSBAR_SRC_CB_B", 20, 21, &umr_bitfield_default },
	 { "CROSSBAR_SRC_CR_R", 22, 23, &umr_bitfield_default },
	 { "HUBPRET_CONTROL_SPARE", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmHUBPRET2_HUBPRET_MEM_PWR_CTRL[] = {
	 { "DET_MEM_PWR_FORCE", 0, 1, &umr_bitfield_default },
	 { "DET_MEM_PWR_DIS", 2, 2, &umr_bitfield_default },
	 { "DET_MEM_PWR_LS_MODE", 4, 5, &umr_bitfield_default },
	 { "HUBPRET_MEM_PWR_CTRL_SPARE", 8, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmHUBPRET2_HUBPRET_MEM_PWR_STATUS[] = {
	 { "DET_MEM_PWR_STATE", 0, 1, &umr_bitfield_default },
};
static struct umr_bitfield mmHUBPRET2_HUBPRET_READ_LINE_CTRL0[] = {
	 { "PIPE_READ_LINE_INTERVAL_IN_NONACTIVE", 0, 15, &umr_bitfield_default },
	 { "PIPE_READ_LINE_VBLANK_MAXIMUM", 16, 29, &umr_bitfield_default },
};
static struct umr_bitfield mmHUBPRET2_HUBPRET_READ_LINE_CTRL1[] = {
	 { "PIPE_READ_LINE_REPORTED_WHEN_REQ_DISABLED", 0, 13, &umr_bitfield_default },
	 { "HUBPRET_READ_LINE_CTRL1_SPARE", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmHUBPRET2_HUBPRET_READ_LINE0[] = {
	 { "PIPE_READ_LINE0_START", 0, 13, &umr_bitfield_default },
	 { "PIPE_READ_LINE0_END", 16, 29, &umr_bitfield_default },
};
static struct umr_bitfield mmHUBPRET2_HUBPRET_READ_LINE1[] = {
	 { "PIPE_READ_LINE1_START", 0, 13, &umr_bitfield_default },
	 { "PIPE_READ_LINE1_END", 16, 29, &umr_bitfield_default },
};
static struct umr_bitfield mmHUBPRET2_HUBPRET_INTERRUPT[] = {
	 { "PIPE_VBLANK_INT_MASK", 0, 0, &umr_bitfield_default },
	 { "PIPE_READ_LINE0_INT_MASK", 1, 1, &umr_bitfield_default },
	 { "PIPE_READ_LINE1_INT_MASK", 2, 2, &umr_bitfield_default },
	 { "PIPE_VBLANK_INT_TYPE", 4, 4, &umr_bitfield_default },
	 { "PIPE_READ_LINE0_INT_TYPE", 5, 5, &umr_bitfield_default },
	 { "PIPE_READ_LINE1_INT_TYPE", 6, 6, &umr_bitfield_default },
	 { "PIPE_VBLANK_INT_CLEAR", 8, 8, &umr_bitfield_default },
	 { "PIPE_READ_LINE0_INT_CLEAR", 9, 9, &umr_bitfield_default },
	 { "PIPE_READ_LINE1_INT_CLEAR", 10, 10, &umr_bitfield_default },
	 { "PIPE_VBLANK_STATUS", 12, 12, &umr_bitfield_default },
	 { "PIPE_READ_LINE0_STATUS", 13, 13, &umr_bitfield_default },
	 { "PIPE_READ_LINE1_STATUS", 14, 14, &umr_bitfield_default },
	 { "PIPE_VBLANK_INT_STATUS", 16, 16, &umr_bitfield_default },
	 { "PIPE_READ_LINE0_INT_STATUS", 17, 17, &umr_bitfield_default },
	 { "PIPE_READ_LINE1_INT_STATUS", 18, 18, &umr_bitfield_default },
};
static struct umr_bitfield mmHUBPRET2_HUBPRET_READ_LINE_VALUE[] = {
	 { "PIPE_READ_LINE", 0, 13, &umr_bitfield_default },
	 { "PIPE_READ_LINE_SNAPSHOT", 16, 29, &umr_bitfield_default },
};
static struct umr_bitfield mmHUBPRET2_HUBPRET_READ_LINE_STATUS[] = {
	 { "PIPE_READ_VBLANK", 0, 0, &umr_bitfield_default },
	 { "PIPE_READ_LINE0_INSIDE", 4, 4, &umr_bitfield_default },
	 { "PIPE_READ_LINE0_OUTSIDE", 5, 5, &umr_bitfield_default },
	 { "PIPE_READ_LINE1_INSIDE", 8, 8, &umr_bitfield_default },
	 { "PIPE_READ_LINE1_OUTSIDE", 10, 10, &umr_bitfield_default },
};
static struct umr_bitfield mmCURSOR2_CURSOR_CONTROL[] = {
	 { "CURSOR_ENABLE", 0, 0, &umr_bitfield_default },
	 { "CURSOR_MODE", 8, 9, &umr_bitfield_default },
	 { "CURSOR_SNOOP", 13, 13, &umr_bitfield_default },
	 { "CURSOR_SYSTEM", 14, 14, &umr_bitfield_default },
	 { "CURSOR_PITCH", 16, 17, &umr_bitfield_default },
	 { "CURSOR_XY_POSITION_ROTATION_AND_MIRRORING_BYPASS", 20, 20, &umr_bitfield_default },
	 { "CURSOR_LINES_PER_CHUNK", 24, 28, &umr_bitfield_default },
	 { "CURSOR_PERFMON_LATENCY_MEASURE_EN", 30, 30, &umr_bitfield_default },
	 { "CURSOR_PERFMON_LATENCY_MEASURE_SEL", 31, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmCURSOR2_CURSOR_SURFACE_ADDRESS[] = {
	 { "CURSOR_SURFACE_ADDRESS", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmCURSOR2_CURSOR_SURFACE_ADDRESS_HIGH[] = {
	 { "CURSOR_SURFACE_ADDRESS_HIGH", 0, 15, &umr_bitfield_default },
};
static struct umr_bitfield mmCURSOR2_CURSOR_SIZE[] = {
	 { "CURSOR_HEIGHT", 0, 8, &umr_bitfield_default },
	 { "CURSOR_WIDTH", 16, 24, &umr_bitfield_default },
};
static struct umr_bitfield mmCURSOR2_CURSOR_POSITION[] = {
	 { "CURSOR_Y_POSITION", 0, 13, &umr_bitfield_default },
	 { "CURSOR_X_POSITION", 16, 29, &umr_bitfield_default },
};
static struct umr_bitfield mmCURSOR2_CURSOR_HOT_SPOT[] = {
	 { "CURSOR_HOT_SPOT_Y", 0, 7, &umr_bitfield_default },
	 { "CURSOR_HOT_SPOT_X", 16, 23, &umr_bitfield_default },
};
static struct umr_bitfield mmCURSOR2_CURSOR_STEREO_CONTROL[] = {
	 { "CURSOR_STEREO_EN", 0, 0, &umr_bitfield_default },
	 { "CURSOR_PRIMARY_OFFSET", 4, 17, &umr_bitfield_default },
	 { "CURSOR_SECONDARY_OFFSET", 18, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmCURSOR2_CURSOR_DST_OFFSET[] = {
	 { "CURSOR_DST_X_OFFSET", 0, 12, &umr_bitfield_default },
};
static struct umr_bitfield mmCURSOR2_CURSOR_MEM_PWR_CTRL[] = {
	 { "CROB_MEM_PWR_FORCE", 0, 1, &umr_bitfield_default },
	 { "CROB_MEM_PWR_DIS", 2, 2, &umr_bitfield_default },
	 { "CROB_MEM_PWR_LS_MODE", 4, 5, &umr_bitfield_default },
};
static struct umr_bitfield mmCURSOR2_CURSOR_MEM_PWR_STATUS[] = {
	 { "CROB_MEM_PWR_STATE", 0, 1, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_PERFMON10_PERFCOUNTER_CNTL[] = {
	 { "PERFCOUNTER_EVENT_SEL", 0, 8, &umr_bitfield_default },
	 { "PERFCOUNTER_CVALUE_SEL", 9, 11, &umr_bitfield_default },
	 { "PERFCOUNTER_INC_MODE", 12, 14, &umr_bitfield_default },
	 { "PERFCOUNTER_HW_CNTL_SEL", 15, 15, &umr_bitfield_default },
	 { "PERFCOUNTER_RUNEN_MODE", 16, 16, &umr_bitfield_default },
	 { "PERFCOUNTER_CNTOFF_START_DIS", 22, 22, &umr_bitfield_default },
	 { "PERFCOUNTER_RESTART_EN", 23, 23, &umr_bitfield_default },
	 { "PERFCOUNTER_INT_EN", 24, 24, &umr_bitfield_default },
	 { "PERFCOUNTER_OFF_MASK", 25, 25, &umr_bitfield_default },
	 { "PERFCOUNTER_ACTIVE", 26, 26, &umr_bitfield_default },
	 { "PERFCOUNTER_CNTL_SEL", 29, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_PERFMON10_PERFCOUNTER_CNTL2[] = {
	 { "PERFCOUNTER_COUNTED_VALUE_TYPE", 0, 1, &umr_bitfield_default },
	 { "PERFCOUNTER_HW_STOP1_SEL", 2, 2, &umr_bitfield_default },
	 { "PERFCOUNTER_HW_STOP2_SEL", 3, 3, &umr_bitfield_default },
	 { "PERFCOUNTER_CNTOFF_SEL", 8, 13, &umr_bitfield_default },
	 { "PERFCOUNTER_CNTL2_SEL", 29, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_PERFMON10_PERFCOUNTER_STATE[] = {
	 { "PERFCOUNTER_CNT0_STATE", 0, 1, &umr_bitfield_default },
	 { "PERFCOUNTER_STATE_SEL0", 2, 2, &umr_bitfield_default },
	 { "PERFCOUNTER_CNT1_STATE", 4, 5, &umr_bitfield_default },
	 { "PERFCOUNTER_STATE_SEL1", 6, 6, &umr_bitfield_default },
	 { "PERFCOUNTER_CNT2_STATE", 8, 9, &umr_bitfield_default },
	 { "PERFCOUNTER_STATE_SEL2", 10, 10, &umr_bitfield_default },
	 { "PERFCOUNTER_CNT3_STATE", 12, 13, &umr_bitfield_default },
	 { "PERFCOUNTER_STATE_SEL3", 14, 14, &umr_bitfield_default },
	 { "PERFCOUNTER_CNT4_STATE", 16, 17, &umr_bitfield_default },
	 { "PERFCOUNTER_STATE_SEL4", 18, 18, &umr_bitfield_default },
	 { "PERFCOUNTER_CNT5_STATE", 20, 21, &umr_bitfield_default },
	 { "PERFCOUNTER_STATE_SEL5", 22, 22, &umr_bitfield_default },
	 { "PERFCOUNTER_CNT6_STATE", 24, 25, &umr_bitfield_default },
	 { "PERFCOUNTER_STATE_SEL6", 26, 26, &umr_bitfield_default },
	 { "PERFCOUNTER_CNT7_STATE", 28, 29, &umr_bitfield_default },
	 { "PERFCOUNTER_STATE_SEL7", 30, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_PERFMON10_PERFMON_CNTL[] = {
	 { "PERFMON_STATE", 0, 1, &umr_bitfield_default },
	 { "PERFMON_RPT_COUNT", 8, 27, &umr_bitfield_default },
	 { "PERFMON_CNTOFF_AND_OR", 28, 28, &umr_bitfield_default },
	 { "PERFMON_CNTOFF_INT_EN", 29, 29, &umr_bitfield_default },
	 { "PERFMON_CNTOFF_INT_STATUS", 30, 30, &umr_bitfield_default },
	 { "PERFMON_CNTOFF_INT_ACK", 31, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_PERFMON10_PERFMON_CNTL2[] = {
	 { "PERFMON_CNTOFF_INT_TYPE", 0, 0, &umr_bitfield_default },
	 { "PERFMON_CLK_ENABLE", 1, 1, &umr_bitfield_default },
	 { "PERFMON_RUN_ENABLE_START_SEL", 2, 9, &umr_bitfield_default },
	 { "PERFMON_RUN_ENABLE_STOP_SEL", 10, 17, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_PERFMON10_PERFMON_CVALUE_INT_MISC[] = {
	 { "PERFCOUNTER_INT0_STATUS", 0, 0, &umr_bitfield_default },
	 { "PERFCOUNTER_INT1_STATUS", 1, 1, &umr_bitfield_default },
	 { "PERFCOUNTER_INT2_STATUS", 2, 2, &umr_bitfield_default },
	 { "PERFCOUNTER_INT3_STATUS", 3, 3, &umr_bitfield_default },
	 { "PERFCOUNTER_INT4_STATUS", 4, 4, &umr_bitfield_default },
	 { "PERFCOUNTER_INT5_STATUS", 5, 5, &umr_bitfield_default },
	 { "PERFCOUNTER_INT6_STATUS", 6, 6, &umr_bitfield_default },
	 { "PERFCOUNTER_INT7_STATUS", 7, 7, &umr_bitfield_default },
	 { "PERFCOUNTER_INT0_ACK", 8, 8, &umr_bitfield_default },
	 { "PERFCOUNTER_INT1_ACK", 9, 9, &umr_bitfield_default },
	 { "PERFCOUNTER_INT2_ACK", 10, 10, &umr_bitfield_default },
	 { "PERFCOUNTER_INT3_ACK", 11, 11, &umr_bitfield_default },
	 { "PERFCOUNTER_INT4_ACK", 12, 12, &umr_bitfield_default },
	 { "PERFCOUNTER_INT5_ACK", 13, 13, &umr_bitfield_default },
	 { "PERFCOUNTER_INT6_ACK", 14, 14, &umr_bitfield_default },
	 { "PERFCOUNTER_INT7_ACK", 15, 15, &umr_bitfield_default },
	 { "PERFMON_CVALUE_HI", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_PERFMON10_PERFMON_CVALUE_LOW[] = {
	 { "PERFMON_CVALUE_LOW", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_PERFMON10_PERFMON_HI[] = {
	 { "PERFMON_HI", 0, 15, &umr_bitfield_default },
	 { "PERFMON_READ_SEL", 29, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_PERFMON10_PERFMON_LOW[] = {
	 { "PERFMON_LOW", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmHUBP3_DCSURF_SURFACE_CONFIG[] = {
	 { "SURFACE_PIXEL_FORMAT", 0, 6, &umr_bitfield_default },
	 { "ROTATION_ANGLE", 8, 9, &umr_bitfield_default },
	 { "H_MIRROR_EN", 10, 10, &umr_bitfield_default },
};
static struct umr_bitfield mmHUBP3_DCSURF_ADDR_CONFIG[] = {
	 { "NUM_PIPES", 0, 2, &umr_bitfield_default },
	 { "NUM_BANKS", 3, 5, &umr_bitfield_default },
	 { "PIPE_INTERLEAVE", 6, 7, &umr_bitfield_default },
	 { "NUM_SE", 8, 9, &umr_bitfield_default },
	 { "NUM_RB_PER_SE", 10, 11, &umr_bitfield_default },
	 { "MAX_COMPRESSED_FRAGS", 12, 13, &umr_bitfield_default },
};
static struct umr_bitfield mmHUBP3_DCSURF_TILING_CONFIG[] = {
	 { "SW_MODE", 0, 4, &umr_bitfield_default },
	 { "DIM_TYPE", 7, 8, &umr_bitfield_default },
	 { "META_LINEAR", 9, 9, &umr_bitfield_default },
	 { "RB_ALIGNED", 10, 10, &umr_bitfield_default },
	 { "PIPE_ALIGNED", 11, 11, &umr_bitfield_default },
};
static struct umr_bitfield mmHUBP3_DCSURF_PRI_VIEWPORT_START[] = {
	 { "PRI_VIEWPORT_X_START", 0, 13, &umr_bitfield_default },
	 { "PRI_VIEWPORT_Y_START", 16, 29, &umr_bitfield_default },
};
static struct umr_bitfield mmHUBP3_DCSURF_PRI_VIEWPORT_DIMENSION[] = {
	 { "PRI_VIEWPORT_WIDTH", 0, 13, &umr_bitfield_default },
	 { "PRI_VIEWPORT_HEIGHT", 16, 29, &umr_bitfield_default },
};
static struct umr_bitfield mmHUBP3_DCSURF_PRI_VIEWPORT_START_C[] = {
	 { "PRI_VIEWPORT_X_START_C", 0, 13, &umr_bitfield_default },
	 { "PRI_VIEWPORT_Y_START_C", 16, 29, &umr_bitfield_default },
};
static struct umr_bitfield mmHUBP3_DCSURF_PRI_VIEWPORT_DIMENSION_C[] = {
	 { "PRI_VIEWPORT_WIDTH_C", 0, 13, &umr_bitfield_default },
	 { "PRI_VIEWPORT_HEIGHT_C", 16, 29, &umr_bitfield_default },
};
static struct umr_bitfield mmHUBP3_DCSURF_SEC_VIEWPORT_START[] = {
	 { "SEC_VIEWPORT_X_START", 0, 13, &umr_bitfield_default },
	 { "SEC_VIEWPORT_Y_START", 16, 29, &umr_bitfield_default },
};
static struct umr_bitfield mmHUBP3_DCSURF_SEC_VIEWPORT_DIMENSION[] = {
	 { "SEC_VIEWPORT_WIDTH", 0, 13, &umr_bitfield_default },
	 { "SEC_VIEWPORT_HEIGHT", 16, 29, &umr_bitfield_default },
};
static struct umr_bitfield mmHUBP3_DCSURF_SEC_VIEWPORT_START_C[] = {
	 { "SEC_VIEWPORT_X_START_C", 0, 13, &umr_bitfield_default },
	 { "SEC_VIEWPORT_Y_START_C", 16, 29, &umr_bitfield_default },
};
static struct umr_bitfield mmHUBP3_DCSURF_SEC_VIEWPORT_DIMENSION_C[] = {
	 { "SEC_VIEWPORT_WIDTH_C", 0, 13, &umr_bitfield_default },
	 { "SEC_VIEWPORT_HEIGHT_C", 16, 29, &umr_bitfield_default },
};
static struct umr_bitfield mmHUBP3_DCHUBP_REQ_SIZE_CONFIG[] = {
	 { "SWATH_HEIGHT", 0, 2, &umr_bitfield_default },
	 { "PTE_ROW_HEIGHT_LINEAR", 4, 6, &umr_bitfield_default },
	 { "CHUNK_SIZE", 8, 10, &umr_bitfield_default },
	 { "MIN_CHUNK_SIZE", 11, 12, &umr_bitfield_default },
	 { "META_CHUNK_SIZE", 16, 17, &umr_bitfield_default },
	 { "MIN_META_CHUNK_SIZE", 18, 19, &umr_bitfield_default },
	 { "DPTE_GROUP_SIZE", 20, 22, &umr_bitfield_default },
	 { "MPTE_GROUP_SIZE", 24, 26, &umr_bitfield_default },
};
static struct umr_bitfield mmHUBP3_DCHUBP_REQ_SIZE_CONFIG_C[] = {
	 { "SWATH_HEIGHT_C", 0, 2, &umr_bitfield_default },
	 { "PTE_ROW_HEIGHT_LINEAR_C", 4, 6, &umr_bitfield_default },
	 { "CHUNK_SIZE_C", 8, 10, &umr_bitfield_default },
	 { "MIN_CHUNK_SIZE_C", 11, 12, &umr_bitfield_default },
	 { "META_CHUNK_SIZE_C", 16, 17, &umr_bitfield_default },
	 { "MIN_META_CHUNK_SIZE_C", 18, 19, &umr_bitfield_default },
	 { "DPTE_GROUP_SIZE_C", 20, 22, &umr_bitfield_default },
	 { "MPTE_GROUP_SIZE_C", 24, 26, &umr_bitfield_default },
};
static struct umr_bitfield mmHUBP3_DCHUBP_CNTL[] = {
	 { "HUBP_BLANK_EN", 0, 0, &umr_bitfield_default },
	 { "HUBP_NO_OUTSTANDING_REQ", 1, 1, &umr_bitfield_default },
	 { "HUBP_DISABLE", 2, 2, &umr_bitfield_default },
	 { "HUBP_IN_BLANK", 3, 3, &umr_bitfield_default },
	 { "HUBP_VTG_SEL", 4, 7, &umr_bitfield_default },
	 { "HUBP_TTU_DISABLE", 12, 12, &umr_bitfield_default },
	 { "HUBP_TTU_MODE", 13, 15, &umr_bitfield_default },
	 { "HUBP_UNDERFLOW_STATUS", 28, 30, &umr_bitfield_default },
	 { "HUBP_UNDERFLOW_CLEAR", 31, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmHUBP3_HUBP_CLK_CNTL[] = {
	 { "HUBP_CLOCK_ENABLE", 0, 0, &umr_bitfield_default },
	 { "HUBP_DISPCLK_R_GATE_DIS", 4, 4, &umr_bitfield_default },
	 { "HUBP_DPPCLK_G_GATE_DIS", 8, 8, &umr_bitfield_default },
	 { "HUBP_DCFCLK_R_GATE_DIS", 12, 12, &umr_bitfield_default },
	 { "HUBP_DCFCLK_G_GATE_DIS", 16, 16, &umr_bitfield_default },
	 { "HUBP_DISPCLK_R_CLOCK_ON", 20, 20, &umr_bitfield_default },
	 { "HUBP_DPPCLK_G_CLOCK_ON", 21, 21, &umr_bitfield_default },
	 { "HUBP_DCFCLK_R_CLOCK_ON", 22, 22, &umr_bitfield_default },
	 { "HUBP_DCFCLK_G_CLOCK_ON", 23, 23, &umr_bitfield_default },
	 { "HUBP_TEST_CLK_SEL", 28, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmHUBP3_DCHUBP_VMPG_CONFIG[] = {
	 { "VMPG_SIZE", 0, 0, &umr_bitfield_default },
};
static struct umr_bitfield mmHUBP3_HUBPREQ_DEBUG_DB[] = {
	 { "HUBPREQ_DEBUG", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmHUBP3_HUBP_MEASURE_WIN_CTRL_DCFCLK[] = {
	 { "HUBP_MEASURE_WIN_EN_DCFCLK", 0, 0, &umr_bitfield_default },
	 { "HUBP_MEASURE_WIN_PERIOD_M1_DCFCLK", 4, 11, &umr_bitfield_default },
	 { "HUBP_PERFMON_START_SEL_DCFCLK", 12, 16, &umr_bitfield_default },
	 { "HUBP_PERFMON_STOP_SEL_DCFCLK", 20, 24, &umr_bitfield_default },
	 { "HUBP_MEASURE_WIN_MODE_DCFCLK", 28, 29, &umr_bitfield_default },
};
static struct umr_bitfield mmHUBP3_HUBP_MEASURE_WIN_CTRL_DPPCLK[] = {
	 { "HUBP_MEASURE_WIN_EN_DPPCLK", 0, 0, &umr_bitfield_default },
	 { "HUBP_MEASURE_WIN_SRC_SEL_DPPCLK", 1, 1, &umr_bitfield_default },
	 { "HUBP_MEASURE_WIN_PERIOD_M1_DPPCLK", 4, 11, &umr_bitfield_default },
	 { "HUBP_PERFMON_START_SEL_DPPCLK", 12, 16, &umr_bitfield_default },
	 { "HUBP_PERFMON_STOP_SEL_DPPCLK", 20, 24, &umr_bitfield_default },
};
static struct umr_bitfield mmHUBPREQ3_DCSURF_SURFACE_PITCH[] = {
	 { "PITCH", 0, 13, &umr_bitfield_default },
	 { "META_PITCH", 16, 29, &umr_bitfield_default },
};
static struct umr_bitfield mmHUBPREQ3_DCSURF_SURFACE_PITCH_C[] = {
	 { "PITCH_C", 0, 13, &umr_bitfield_default },
	 { "META_PITCH_C", 16, 29, &umr_bitfield_default },
};
static struct umr_bitfield mmHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS[] = {
	 { "PRIMARY_SURFACE_ADDRESS", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH[] = {
	 { "PRIMARY_SURFACE_ADDRESS_HIGH", 0, 15, &umr_bitfield_default },
};
static struct umr_bitfield mmHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_C[] = {
	 { "PRIMARY_SURFACE_ADDRESS_C", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C[] = {
	 { "PRIMARY_SURFACE_ADDRESS_HIGH_C", 0, 15, &umr_bitfield_default },
};
static struct umr_bitfield mmHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS[] = {
	 { "SECONDARY_SURFACE_ADDRESS", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH[] = {
	 { "SECONDARY_SURFACE_ADDRESS_HIGH", 0, 15, &umr_bitfield_default },
};
static struct umr_bitfield mmHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_C[] = {
	 { "SECONDARY_SURFACE_ADDRESS_C", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C[] = {
	 { "SECONDARY_SURFACE_ADDRESS_HIGH_C", 0, 15, &umr_bitfield_default },
};
static struct umr_bitfield mmHUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS[] = {
	 { "PRIMARY_META_SURFACE_ADDRESS", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmHUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH[] = {
	 { "PRIMARY_META_SURFACE_ADDRESS_HIGH", 0, 15, &umr_bitfield_default },
};
static struct umr_bitfield mmHUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C[] = {
	 { "PRIMARY_META_SURFACE_ADDRESS_C", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmHUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C[] = {
	 { "PRIMARY_META_SURFACE_ADDRESS_HIGH_C", 0, 15, &umr_bitfield_default },
};
static struct umr_bitfield mmHUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS[] = {
	 { "SECONDARY_META_SURFACE_ADDRESS", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmHUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH[] = {
	 { "SECONDARY_META_SURFACE_ADDRESS_HIGH", 0, 15, &umr_bitfield_default },
};
static struct umr_bitfield mmHUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C[] = {
	 { "SECONDARY_META_SURFACE_ADDRESS_C", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmHUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C[] = {
	 { "SECONDARY_META_SURFACE_ADDRESS_HIGH_C", 0, 15, &umr_bitfield_default },
};
static struct umr_bitfield mmHUBPREQ3_DCSURF_SURFACE_CONTROL[] = {
	 { "PRIMARY_SURFACE_DCC_EN", 1, 1, &umr_bitfield_default },
	 { "PRIMARY_SURFACE_DCC_IND_64B_BLK", 2, 2, &umr_bitfield_default },
	 { "PRIMARY_SURFACE_DCC_IND_64B_BLK_C", 5, 5, &umr_bitfield_default },
	 { "SECONDARY_SURFACE_DCC_EN", 9, 9, &umr_bitfield_default },
	 { "SECONDARY_SURFACE_DCC_IND_64B_BLK", 10, 10, &umr_bitfield_default },
	 { "SECONDARY_SURFACE_DCC_IND_64B_BLK_C", 13, 13, &umr_bitfield_default },
};
static struct umr_bitfield mmHUBPREQ3_DCSURF_FLIP_CONTROL[] = {
	 { "SURFACE_UPDATE_LOCK", 0, 0, &umr_bitfield_default },
	 { "SURFACE_FLIP_TYPE", 1, 1, &umr_bitfield_default },
	 { "SURFACE_FLIP_VUPDATE_SKIP_NUM", 4, 7, &umr_bitfield_default },
	 { "SURFACE_FLIP_MODE_FOR_STEREOSYNC", 12, 13, &umr_bitfield_default },
	 { "SURFACE_FLIP_IN_STEREOSYNC", 16, 16, &umr_bitfield_default },
	 { "SURFACE_FLIP_STEREO_SELECT_DISABLE", 17, 17, &umr_bitfield_default },
	 { "SURFACE_FLIP_STEREO_SELECT_POLARITY", 18, 18, &umr_bitfield_default },
	 { "SURFACE_FLIP_PENDING_DELAY", 20, 29, &umr_bitfield_default },
	 { "SURFACE_UPDATE_PENDING", 30, 30, &umr_bitfield_default },
	 { "SURFACE_FLIP_PENDING", 31, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmHUBPREQ3_DCSURF_FLIP_CONTROL2[] = {
	 { "SURFACE_UPDATE_FLIP_PENDING_MIN_TIME", 0, 7, &umr_bitfield_default },
	 { "SURFACE_UPDATE_PENDING_HIGH_EXTEND_ENABLE", 12, 12, &umr_bitfield_default },
	 { "SURFACE_FLIP_PENDING_HIGH_EXTEND_ENABLE", 13, 13, &umr_bitfield_default },
};
static struct umr_bitfield mmHUBPREQ3_DCSURF_FRAME_PACING_CONTROL[] = {
	 { "SURFACE_FRAME_PACING_ENABLE", 0, 0, &umr_bitfield_default },
	 { "SURFACE_FRAME_PACING_MODE", 1, 1, &umr_bitfield_default },
	 { "SURFACE_FRAME_PACING_QUEUE_RESET", 8, 8, &umr_bitfield_default },
	 { "SURFACE_FRAME_PACING_QUEUE_FREE_ENTRY", 24, 26, &umr_bitfield_default },
};
static struct umr_bitfield mmHUBPREQ3_DCSURF_FRAME_PACING_TIME[] = {
	 { "SURFACE_FRAME_PACING_TIME", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmHUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT[] = {
	 { "SURFACE_FLIP_INT_MASK", 0, 0, &umr_bitfield_default },
	 { "SURFACE_FLIP_INT_TYPE", 1, 1, &umr_bitfield_default },
	 { "SURFACE_FLIP_AWAY_INT_MASK", 2, 2, &umr_bitfield_default },
	 { "SURFACE_FLIP_AWAY_INT_TYPE", 3, 3, &umr_bitfield_default },
	 { "SURFACE_FLIP_CLEAR", 8, 8, &umr_bitfield_default },
	 { "SURFACE_FLIP_AWAY_CLEAR", 9, 9, &umr_bitfield_default },
	 { "SURFACE_FLIP_OCCURRED", 16, 16, &umr_bitfield_default },
	 { "SURFACE_FLIP_INT_STATUS", 17, 17, &umr_bitfield_default },
	 { "SURFACE_FLIP_AWAY_OCCURRED", 18, 18, &umr_bitfield_default },
	 { "SURFACE_FLIP_AWAY_INT_STATUS", 19, 19, &umr_bitfield_default },
};
static struct umr_bitfield mmHUBPREQ3_DCSURF_SURFACE_INUSE[] = {
	 { "SURFACE_INUSE_ADDRESS", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmHUBPREQ3_DCSURF_SURFACE_INUSE_HIGH[] = {
	 { "SURFACE_INUSE_ADDRESS_HIGH", 0, 15, &umr_bitfield_default },
};
static struct umr_bitfield mmHUBPREQ3_DCSURF_SURFACE_INUSE_C[] = {
	 { "SURFACE_INUSE_ADDRESS_C", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmHUBPREQ3_DCSURF_SURFACE_INUSE_HIGH_C[] = {
	 { "SURFACE_INUSE_ADDRESS_HIGH_C", 0, 15, &umr_bitfield_default },
};
static struct umr_bitfield mmHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE[] = {
	 { "SURFACE_EARLIEST_INUSE_ADDRESS", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_HIGH[] = {
	 { "SURFACE_EARLIEST_INUSE_ADDRESS_HIGH", 0, 15, &umr_bitfield_default },
};
static struct umr_bitfield mmHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_C[] = {
	 { "SURFACE_EARLIEST_INUSE_ADDRESS_C", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C[] = {
	 { "SURFACE_EARLIEST_INUSE_ADDRESS_HIGH_C", 0, 15, &umr_bitfield_default },
};
static struct umr_bitfield mmHUBPREQ3_DCN_EXPANSION_MODE[] = {
	 { "DRQ_EXPANSION_MODE", 0, 1, &umr_bitfield_default },
	 { "CRQ_EXPANSION_MODE", 2, 3, &umr_bitfield_default },
	 { "MRQ_EXPANSION_MODE", 4, 5, &umr_bitfield_default },
	 { "PRQ_EXPANSION_MODE", 6, 7, &umr_bitfield_default },
};
static struct umr_bitfield mmHUBPREQ3_DCN_TTU_QOS_WM[] = {
	 { "QoS_LEVEL_LOW_WM", 0, 13, &umr_bitfield_default },
	 { "QoS_LEVEL_HIGH_WM", 16, 29, &umr_bitfield_default },
};
static struct umr_bitfield mmHUBPREQ3_DCN_GLOBAL_TTU_CNTL[] = {
	 { "MIN_TTU_VBLANK", 0, 23, &umr_bitfield_default },
	 { "QoS_LEVEL_FLIP", 28, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmHUBPREQ3_DCN_SURF0_TTU_CNTL0[] = {
	 { "REFCYC_PER_REQ_DELIVERY", 0, 22, &umr_bitfield_default },
	 { "QoS_LEVEL_FIXED", 24, 27, &umr_bitfield_default },
	 { "QoS_RAMP_DISABLE", 28, 28, &umr_bitfield_default },
};
static struct umr_bitfield mmHUBPREQ3_DCN_SURF0_TTU_CNTL1[] = {
	 { "REFCYC_PER_REQ_DELIVERY_PRE", 0, 22, &umr_bitfield_default },
};
static struct umr_bitfield mmHUBPREQ3_DCN_SURF1_TTU_CNTL0[] = {
	 { "REFCYC_PER_REQ_DELIVERY", 0, 22, &umr_bitfield_default },
	 { "QoS_LEVEL_FIXED", 24, 27, &umr_bitfield_default },
	 { "QoS_RAMP_DISABLE", 28, 28, &umr_bitfield_default },
};
static struct umr_bitfield mmHUBPREQ3_DCN_SURF1_TTU_CNTL1[] = {
	 { "REFCYC_PER_REQ_DELIVERY_PRE", 0, 22, &umr_bitfield_default },
};
static struct umr_bitfield mmHUBPREQ3_DCN_CUR0_TTU_CNTL0[] = {
	 { "REFCYC_PER_REQ_DELIVERY", 0, 22, &umr_bitfield_default },
	 { "QoS_LEVEL_FIXED", 24, 27, &umr_bitfield_default },
	 { "QoS_RAMP_DISABLE", 28, 28, &umr_bitfield_default },
};
static struct umr_bitfield mmHUBPREQ3_DCN_CUR0_TTU_CNTL1[] = {
	 { "REFCYC_PER_REQ_DELIVERY_PRE", 0, 22, &umr_bitfield_default },
};
static struct umr_bitfield mmHUBPREQ3_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_LSB[] = {
	 { "MC_VM_SYSTEM_APERTURE_LOW_ADDR_LSB", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmHUBPREQ3_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_MSB[] = {
	 { "MC_VM_SYSTEM_APERTURE_LOW_ADDR_MSB", 0, 3, &umr_bitfield_default },
};
static struct umr_bitfield mmHUBPREQ3_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_LSB[] = {
	 { "MC_VM_SYSTEM_APERTURE_HIGH_ADDR_LSB", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmHUBPREQ3_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_MSB[] = {
	 { "MC_VM_SYSTEM_APERTURE_HIGH_ADDR_MSB", 0, 3, &umr_bitfield_default },
};
static struct umr_bitfield mmHUBPREQ3_DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB[] = {
	 { "MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmHUBPREQ3_DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB[] = {
	 { "MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB", 0, 3, &umr_bitfield_default },
	 { "MC_VM_SYSTEM_APERTURE_DEFAULT_SYSTEM", 28, 28, &umr_bitfield_default },
	 { "MC_VM_SYSTEM_APERTURE_DEFAULT_SNOOP", 29, 29, &umr_bitfield_default },
};
static struct umr_bitfield mmHUBPREQ3_DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_LSB[] = {
	 { "VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_LSB", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmHUBPREQ3_DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB[] = {
	 { "VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB", 0, 3, &umr_bitfield_default },
	 { "VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_SYSTEM", 28, 28, &umr_bitfield_default },
	 { "VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_SNOOP", 29, 29, &umr_bitfield_default },
	 { "VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_TMZ", 30, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmHUBPREQ3_DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LSB[] = {
	 { "VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LSB", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmHUBPREQ3_DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_MSB[] = {
	 { "VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_MSB", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmHUBPREQ3_DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LSB[] = {
	 { "VM_CONTEXT0_PAGE_TABLE_START_ADDR_LSB", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmHUBPREQ3_DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_MSB[] = {
	 { "VM_CONTEXT0_PAGE_TABLE_START_ADDR_MSB", 0, 3, &umr_bitfield_default },
};
static struct umr_bitfield mmHUBPREQ3_DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LSB[] = {
	 { "VM_CONTEXT0_PAGE_TABLE_END_ADDR_LSB", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmHUBPREQ3_DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_MSB[] = {
	 { "VM_CONTEXT0_PAGE_TABLE_END_ADDR_MSB", 0, 3, &umr_bitfield_default },
};
static struct umr_bitfield mmHUBPREQ3_DCN_VM_CONTEXT0_STATUS[] = {
	 { "DCN_VM_CONTEXT0_ERROR_STATUS", 0, 15, &umr_bitfield_default },
	 { "DCN_VM_CONTEXT0_PROTECTION_FAULT_ADDR_MSB", 24, 27, &umr_bitfield_default },
	 { "DCN_VM_CONTEXT0_ERROR_STATUS_MODE", 30, 30, &umr_bitfield_default },
	 { "DCN_VM_CONTEXT0_ERROR_STATUS_CLEAR", 31, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmHUBPREQ3_DCN_VM_CONTEXT0_PROTECTION_FAULT_ADDR_LSB[] = {
	 { "DCN_VM_CONTEXT0_PROTECTION_FAULT_ADDR_LSB", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmHUBPREQ3_DCN_VM_CONTEXT0_CNTL[] = {
	 { "PAGE_TABLE_DEPTH", 1, 2, &umr_bitfield_default },
	 { "RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT", 3, 3, &umr_bitfield_default },
	 { "RANGE_PROTECTION_FAULT_ENABLE_DEFAULT", 4, 4, &umr_bitfield_default },
	 { "VALID_PROTECTION_FAULT_ENABLE_INTERRUPT", 12, 12, &umr_bitfield_default },
	 { "VALID_PROTECTION_FAULT_ENABLE_DEFAULT", 13, 13, &umr_bitfield_default },
	 { "READ_PROTECTION_FAULT_ENABLE_INTERRUPT", 15, 15, &umr_bitfield_default },
	 { "READ_PROTECTION_FAULT_ENABLE_DEFAULT", 16, 16, &umr_bitfield_default },
};
static struct umr_bitfield mmHUBPREQ3_DCN_VM_MX_L1_TLB_CNTL[] = {
	 { "ENABLE_L1_TLB", 0, 0, &umr_bitfield_default },
	 { "SYSTEM_ACCESS_MODE", 3, 4, &umr_bitfield_default },
};
static struct umr_bitfield mmHUBPREQ3_BLANK_OFFSET_0[] = {
	 { "REFCYC_H_BLANK_END", 0, 12, &umr_bitfield_default },
	 { "DLG_V_BLANK_END", 16, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmHUBPREQ3_BLANK_OFFSET_1[] = {
	 { "MIN_DST_Y_NEXT_START", 0, 17, &umr_bitfield_default },
};
static struct umr_bitfield mmHUBPREQ3_DST_DIMENSIONS[] = {
	 { "REFCYC_PER_HTOTAL", 0, 20, &umr_bitfield_default },
};
static struct umr_bitfield mmHUBPREQ3_DST_AFTER_SCALER[] = {
	 { "REFCYC_X_AFTER_SCALER", 0, 12, &umr_bitfield_default },
	 { "DST_Y_AFTER_SCALER", 16, 18, &umr_bitfield_default },
};
static struct umr_bitfield mmHUBPREQ3_PREFETCH_SETTINS[] = {
	 { "VRATIO_PREFETCH", 0, 20, &umr_bitfield_default },
	 { "DST_Y_PREFETCH", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmHUBPREQ3_PREFETCH_SETTINS_C[] = {
	 { "VRATIO_PREFETCH_C", 0, 20, &umr_bitfield_default },
};
static struct umr_bitfield mmHUBPREQ3_VBLANK_PARAMETERS_0[] = {
	 { "DST_Y_PER_VM_VBLANK", 0, 4, &umr_bitfield_default },
	 { "DST_Y_PER_ROW_VBLANK", 8, 13, &umr_bitfield_default },
};
static struct umr_bitfield mmHUBPREQ3_VBLANK_PARAMETERS_1[] = {
	 { "REFCYC_PER_PTE_GROUP_VBLANK_L", 0, 22, &umr_bitfield_default },
};
static struct umr_bitfield mmHUBPREQ3_VBLANK_PARAMETERS_2[] = {
	 { "REFCYC_PER_PTE_GROUP_VBLANK_C", 0, 22, &umr_bitfield_default },
};
static struct umr_bitfield mmHUBPREQ3_VBLANK_PARAMETERS_3[] = {
	 { "REFCYC_PER_META_CHUNK_VBLANK_L", 0, 22, &umr_bitfield_default },
};
static struct umr_bitfield mmHUBPREQ3_VBLANK_PARAMETERS_4[] = {
	 { "REFCYC_PER_META_CHUNK_VBLANK_C", 0, 22, &umr_bitfield_default },
};
static struct umr_bitfield mmHUBPREQ3_NOM_PARAMETERS_0[] = {
	 { "DST_Y_PER_PTE_ROW_NOM_L", 0, 16, &umr_bitfield_default },
};
static struct umr_bitfield mmHUBPREQ3_NOM_PARAMETERS_1[] = {
	 { "REFCYC_PER_PTE_GROUP_NOM_L", 0, 22, &umr_bitfield_default },
};
static struct umr_bitfield mmHUBPREQ3_NOM_PARAMETERS_2[] = {
	 { "DST_Y_PER_PTE_ROW_NOM_C", 0, 16, &umr_bitfield_default },
};
static struct umr_bitfield mmHUBPREQ3_NOM_PARAMETERS_3[] = {
	 { "REFCYC_PER_PTE_GROUP_NOM_C", 0, 22, &umr_bitfield_default },
};
static struct umr_bitfield mmHUBPREQ3_NOM_PARAMETERS_4[] = {
	 { "DST_Y_PER_META_ROW_NOM_L", 0, 16, &umr_bitfield_default },
};
static struct umr_bitfield mmHUBPREQ3_NOM_PARAMETERS_5[] = {
	 { "REFCYC_PER_META_CHUNK_NOM_L", 0, 22, &umr_bitfield_default },
};
static struct umr_bitfield mmHUBPREQ3_NOM_PARAMETERS_6[] = {
	 { "DST_Y_PER_META_ROW_NOM_C", 0, 16, &umr_bitfield_default },
};
static struct umr_bitfield mmHUBPREQ3_NOM_PARAMETERS_7[] = {
	 { "REFCYC_PER_META_CHUNK_NOM_C", 0, 22, &umr_bitfield_default },
};
static struct umr_bitfield mmHUBPREQ3_PER_LINE_DELIVERY_PRE[] = {
	 { "REFCYC_PER_LINE_DELIVERY_PRE_L", 0, 12, &umr_bitfield_default },
	 { "REFCYC_PER_LINE_DELIVERY_PRE_C", 16, 28, &umr_bitfield_default },
};
static struct umr_bitfield mmHUBPREQ3_PER_LINE_DELIVERY[] = {
	 { "REFCYC_PER_LINE_DELIVERY_L", 0, 12, &umr_bitfield_default },
	 { "REFCYC_PER_LINE_DELIVERY_C", 16, 28, &umr_bitfield_default },
};
static struct umr_bitfield mmHUBPREQ3_CURSOR_SETTINS[] = {
	 { "CURSOR0_DST_Y_OFFSET", 0, 7, &umr_bitfield_default },
	 { "CURSOR0_CHUNK_HDL_ADJUST", 8, 9, &umr_bitfield_default },
};
static struct umr_bitfield mmHUBPREQ3_REF_FREQ_TO_PIX_FREQ[] = {
	 { "REF_FREQ_TO_PIX_FREQ", 0, 20, &umr_bitfield_default },
};
static struct umr_bitfield mmHUBPREQ3_HUBPREQ_MEM_PWR_CTRL[] = {
	 { "REQ_DPTE_MEM_PWR_FORCE", 0, 1, &umr_bitfield_default },
	 { "REQ_DPTE_MEM_PWR_DIS", 2, 2, &umr_bitfield_default },
	 { "REQ_MPTE_MEM_PWR_FORCE", 4, 5, &umr_bitfield_default },
	 { "REQ_MPTE_MEM_PWR_DIS", 6, 6, &umr_bitfield_default },
	 { "REQ_META_MEM_PWR_FORCE", 8, 9, &umr_bitfield_default },
	 { "REQ_META_MEM_PWR_DIS", 10, 10, &umr_bitfield_default },
	 { "REQ_DPTE_FINE_GRAIN_DIS", 16, 16, &umr_bitfield_default },
	 { "REQ_DPTE_FINE_GRAIN_DIS_C", 17, 17, &umr_bitfield_default },
	 { "REQ_META_FINE_GRAIN_DIS", 20, 20, &umr_bitfield_default },
	 { "REQ_META_FINE_GRAIN_DIS_C", 21, 21, &umr_bitfield_default },
	 { "REQ_MPTE_FINE_GRAIN_DIS", 24, 24, &umr_bitfield_default },
};
static struct umr_bitfield mmHUBPREQ3_HUBPREQ_MEM_PWR_STATUS[] = {
	 { "REQ_DPTE_MEM_PWR_STATE", 0, 1, &umr_bitfield_default },
	 { "REQ_MPTE_MEM_PWR_STATE", 2, 3, &umr_bitfield_default },
	 { "REQ_META_MEM_PWR_STATE", 4, 5, &umr_bitfield_default },
};
static struct umr_bitfield mmHUBPRET3_HUBPRET_CONTROL[] = {
	 { "DET_BUF_PLANE1_BASE_ADDRESS", 0, 11, &umr_bitfield_default },
	 { "PACK_3TO2_ELEMENT_DISABLE", 12, 12, &umr_bitfield_default },
	 { "CROSSBAR_SRC_ALPHA", 16, 17, &umr_bitfield_default },
	 { "CROSSBAR_SRC_Y_G", 18, 19, &umr_bitfield_default },
	 { "CROSSBAR_SRC_CB_B", 20, 21, &umr_bitfield_default },
	 { "CROSSBAR_SRC_CR_R", 22, 23, &umr_bitfield_default },
	 { "HUBPRET_CONTROL_SPARE", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmHUBPRET3_HUBPRET_MEM_PWR_CTRL[] = {
	 { "DET_MEM_PWR_FORCE", 0, 1, &umr_bitfield_default },
	 { "DET_MEM_PWR_DIS", 2, 2, &umr_bitfield_default },
	 { "DET_MEM_PWR_LS_MODE", 4, 5, &umr_bitfield_default },
	 { "HUBPRET_MEM_PWR_CTRL_SPARE", 8, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmHUBPRET3_HUBPRET_MEM_PWR_STATUS[] = {
	 { "DET_MEM_PWR_STATE", 0, 1, &umr_bitfield_default },
};
static struct umr_bitfield mmHUBPRET3_HUBPRET_READ_LINE_CTRL0[] = {
	 { "PIPE_READ_LINE_INTERVAL_IN_NONACTIVE", 0, 15, &umr_bitfield_default },
	 { "PIPE_READ_LINE_VBLANK_MAXIMUM", 16, 29, &umr_bitfield_default },
};
static struct umr_bitfield mmHUBPRET3_HUBPRET_READ_LINE_CTRL1[] = {
	 { "PIPE_READ_LINE_REPORTED_WHEN_REQ_DISABLED", 0, 13, &umr_bitfield_default },
	 { "HUBPRET_READ_LINE_CTRL1_SPARE", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmHUBPRET3_HUBPRET_READ_LINE0[] = {
	 { "PIPE_READ_LINE0_START", 0, 13, &umr_bitfield_default },
	 { "PIPE_READ_LINE0_END", 16, 29, &umr_bitfield_default },
};
static struct umr_bitfield mmHUBPRET3_HUBPRET_READ_LINE1[] = {
	 { "PIPE_READ_LINE1_START", 0, 13, &umr_bitfield_default },
	 { "PIPE_READ_LINE1_END", 16, 29, &umr_bitfield_default },
};
static struct umr_bitfield mmHUBPRET3_HUBPRET_INTERRUPT[] = {
	 { "PIPE_VBLANK_INT_MASK", 0, 0, &umr_bitfield_default },
	 { "PIPE_READ_LINE0_INT_MASK", 1, 1, &umr_bitfield_default },
	 { "PIPE_READ_LINE1_INT_MASK", 2, 2, &umr_bitfield_default },
	 { "PIPE_VBLANK_INT_TYPE", 4, 4, &umr_bitfield_default },
	 { "PIPE_READ_LINE0_INT_TYPE", 5, 5, &umr_bitfield_default },
	 { "PIPE_READ_LINE1_INT_TYPE", 6, 6, &umr_bitfield_default },
	 { "PIPE_VBLANK_INT_CLEAR", 8, 8, &umr_bitfield_default },
	 { "PIPE_READ_LINE0_INT_CLEAR", 9, 9, &umr_bitfield_default },
	 { "PIPE_READ_LINE1_INT_CLEAR", 10, 10, &umr_bitfield_default },
	 { "PIPE_VBLANK_STATUS", 12, 12, &umr_bitfield_default },
	 { "PIPE_READ_LINE0_STATUS", 13, 13, &umr_bitfield_default },
	 { "PIPE_READ_LINE1_STATUS", 14, 14, &umr_bitfield_default },
	 { "PIPE_VBLANK_INT_STATUS", 16, 16, &umr_bitfield_default },
	 { "PIPE_READ_LINE0_INT_STATUS", 17, 17, &umr_bitfield_default },
	 { "PIPE_READ_LINE1_INT_STATUS", 18, 18, &umr_bitfield_default },
};
static struct umr_bitfield mmHUBPRET3_HUBPRET_READ_LINE_VALUE[] = {
	 { "PIPE_READ_LINE", 0, 13, &umr_bitfield_default },
	 { "PIPE_READ_LINE_SNAPSHOT", 16, 29, &umr_bitfield_default },
};
static struct umr_bitfield mmHUBPRET3_HUBPRET_READ_LINE_STATUS[] = {
	 { "PIPE_READ_VBLANK", 0, 0, &umr_bitfield_default },
	 { "PIPE_READ_LINE0_INSIDE", 4, 4, &umr_bitfield_default },
	 { "PIPE_READ_LINE0_OUTSIDE", 5, 5, &umr_bitfield_default },
	 { "PIPE_READ_LINE1_INSIDE", 8, 8, &umr_bitfield_default },
	 { "PIPE_READ_LINE1_OUTSIDE", 10, 10, &umr_bitfield_default },
};
static struct umr_bitfield mmCURSOR3_CURSOR_CONTROL[] = {
	 { "CURSOR_ENABLE", 0, 0, &umr_bitfield_default },
	 { "CURSOR_MODE", 8, 9, &umr_bitfield_default },
	 { "CURSOR_SNOOP", 13, 13, &umr_bitfield_default },
	 { "CURSOR_SYSTEM", 14, 14, &umr_bitfield_default },
	 { "CURSOR_PITCH", 16, 17, &umr_bitfield_default },
	 { "CURSOR_XY_POSITION_ROTATION_AND_MIRRORING_BYPASS", 20, 20, &umr_bitfield_default },
	 { "CURSOR_LINES_PER_CHUNK", 24, 28, &umr_bitfield_default },
	 { "CURSOR_PERFMON_LATENCY_MEASURE_EN", 30, 30, &umr_bitfield_default },
	 { "CURSOR_PERFMON_LATENCY_MEASURE_SEL", 31, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmCURSOR3_CURSOR_SURFACE_ADDRESS[] = {
	 { "CURSOR_SURFACE_ADDRESS", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmCURSOR3_CURSOR_SURFACE_ADDRESS_HIGH[] = {
	 { "CURSOR_SURFACE_ADDRESS_HIGH", 0, 15, &umr_bitfield_default },
};
static struct umr_bitfield mmCURSOR3_CURSOR_SIZE[] = {
	 { "CURSOR_HEIGHT", 0, 8, &umr_bitfield_default },
	 { "CURSOR_WIDTH", 16, 24, &umr_bitfield_default },
};
static struct umr_bitfield mmCURSOR3_CURSOR_POSITION[] = {
	 { "CURSOR_Y_POSITION", 0, 13, &umr_bitfield_default },
	 { "CURSOR_X_POSITION", 16, 29, &umr_bitfield_default },
};
static struct umr_bitfield mmCURSOR3_CURSOR_HOT_SPOT[] = {
	 { "CURSOR_HOT_SPOT_Y", 0, 7, &umr_bitfield_default },
	 { "CURSOR_HOT_SPOT_X", 16, 23, &umr_bitfield_default },
};
static struct umr_bitfield mmCURSOR3_CURSOR_STEREO_CONTROL[] = {
	 { "CURSOR_STEREO_EN", 0, 0, &umr_bitfield_default },
	 { "CURSOR_PRIMARY_OFFSET", 4, 17, &umr_bitfield_default },
	 { "CURSOR_SECONDARY_OFFSET", 18, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmCURSOR3_CURSOR_DST_OFFSET[] = {
	 { "CURSOR_DST_X_OFFSET", 0, 12, &umr_bitfield_default },
};
static struct umr_bitfield mmCURSOR3_CURSOR_MEM_PWR_CTRL[] = {
	 { "CROB_MEM_PWR_FORCE", 0, 1, &umr_bitfield_default },
	 { "CROB_MEM_PWR_DIS", 2, 2, &umr_bitfield_default },
	 { "CROB_MEM_PWR_LS_MODE", 4, 5, &umr_bitfield_default },
};
static struct umr_bitfield mmCURSOR3_CURSOR_MEM_PWR_STATUS[] = {
	 { "CROB_MEM_PWR_STATE", 0, 1, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_PERFMON11_PERFCOUNTER_CNTL[] = {
	 { "PERFCOUNTER_EVENT_SEL", 0, 8, &umr_bitfield_default },
	 { "PERFCOUNTER_CVALUE_SEL", 9, 11, &umr_bitfield_default },
	 { "PERFCOUNTER_INC_MODE", 12, 14, &umr_bitfield_default },
	 { "PERFCOUNTER_HW_CNTL_SEL", 15, 15, &umr_bitfield_default },
	 { "PERFCOUNTER_RUNEN_MODE", 16, 16, &umr_bitfield_default },
	 { "PERFCOUNTER_CNTOFF_START_DIS", 22, 22, &umr_bitfield_default },
	 { "PERFCOUNTER_RESTART_EN", 23, 23, &umr_bitfield_default },
	 { "PERFCOUNTER_INT_EN", 24, 24, &umr_bitfield_default },
	 { "PERFCOUNTER_OFF_MASK", 25, 25, &umr_bitfield_default },
	 { "PERFCOUNTER_ACTIVE", 26, 26, &umr_bitfield_default },
	 { "PERFCOUNTER_CNTL_SEL", 29, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_PERFMON11_PERFCOUNTER_CNTL2[] = {
	 { "PERFCOUNTER_COUNTED_VALUE_TYPE", 0, 1, &umr_bitfield_default },
	 { "PERFCOUNTER_HW_STOP1_SEL", 2, 2, &umr_bitfield_default },
	 { "PERFCOUNTER_HW_STOP2_SEL", 3, 3, &umr_bitfield_default },
	 { "PERFCOUNTER_CNTOFF_SEL", 8, 13, &umr_bitfield_default },
	 { "PERFCOUNTER_CNTL2_SEL", 29, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_PERFMON11_PERFCOUNTER_STATE[] = {
	 { "PERFCOUNTER_CNT0_STATE", 0, 1, &umr_bitfield_default },
	 { "PERFCOUNTER_STATE_SEL0", 2, 2, &umr_bitfield_default },
	 { "PERFCOUNTER_CNT1_STATE", 4, 5, &umr_bitfield_default },
	 { "PERFCOUNTER_STATE_SEL1", 6, 6, &umr_bitfield_default },
	 { "PERFCOUNTER_CNT2_STATE", 8, 9, &umr_bitfield_default },
	 { "PERFCOUNTER_STATE_SEL2", 10, 10, &umr_bitfield_default },
	 { "PERFCOUNTER_CNT3_STATE", 12, 13, &umr_bitfield_default },
	 { "PERFCOUNTER_STATE_SEL3", 14, 14, &umr_bitfield_default },
	 { "PERFCOUNTER_CNT4_STATE", 16, 17, &umr_bitfield_default },
	 { "PERFCOUNTER_STATE_SEL4", 18, 18, &umr_bitfield_default },
	 { "PERFCOUNTER_CNT5_STATE", 20, 21, &umr_bitfield_default },
	 { "PERFCOUNTER_STATE_SEL5", 22, 22, &umr_bitfield_default },
	 { "PERFCOUNTER_CNT6_STATE", 24, 25, &umr_bitfield_default },
	 { "PERFCOUNTER_STATE_SEL6", 26, 26, &umr_bitfield_default },
	 { "PERFCOUNTER_CNT7_STATE", 28, 29, &umr_bitfield_default },
	 { "PERFCOUNTER_STATE_SEL7", 30, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_PERFMON11_PERFMON_CNTL[] = {
	 { "PERFMON_STATE", 0, 1, &umr_bitfield_default },
	 { "PERFMON_RPT_COUNT", 8, 27, &umr_bitfield_default },
	 { "PERFMON_CNTOFF_AND_OR", 28, 28, &umr_bitfield_default },
	 { "PERFMON_CNTOFF_INT_EN", 29, 29, &umr_bitfield_default },
	 { "PERFMON_CNTOFF_INT_STATUS", 30, 30, &umr_bitfield_default },
	 { "PERFMON_CNTOFF_INT_ACK", 31, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_PERFMON11_PERFMON_CNTL2[] = {
	 { "PERFMON_CNTOFF_INT_TYPE", 0, 0, &umr_bitfield_default },
	 { "PERFMON_CLK_ENABLE", 1, 1, &umr_bitfield_default },
	 { "PERFMON_RUN_ENABLE_START_SEL", 2, 9, &umr_bitfield_default },
	 { "PERFMON_RUN_ENABLE_STOP_SEL", 10, 17, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_PERFMON11_PERFMON_CVALUE_INT_MISC[] = {
	 { "PERFCOUNTER_INT0_STATUS", 0, 0, &umr_bitfield_default },
	 { "PERFCOUNTER_INT1_STATUS", 1, 1, &umr_bitfield_default },
	 { "PERFCOUNTER_INT2_STATUS", 2, 2, &umr_bitfield_default },
	 { "PERFCOUNTER_INT3_STATUS", 3, 3, &umr_bitfield_default },
	 { "PERFCOUNTER_INT4_STATUS", 4, 4, &umr_bitfield_default },
	 { "PERFCOUNTER_INT5_STATUS", 5, 5, &umr_bitfield_default },
	 { "PERFCOUNTER_INT6_STATUS", 6, 6, &umr_bitfield_default },
	 { "PERFCOUNTER_INT7_STATUS", 7, 7, &umr_bitfield_default },
	 { "PERFCOUNTER_INT0_ACK", 8, 8, &umr_bitfield_default },
	 { "PERFCOUNTER_INT1_ACK", 9, 9, &umr_bitfield_default },
	 { "PERFCOUNTER_INT2_ACK", 10, 10, &umr_bitfield_default },
	 { "PERFCOUNTER_INT3_ACK", 11, 11, &umr_bitfield_default },
	 { "PERFCOUNTER_INT4_ACK", 12, 12, &umr_bitfield_default },
	 { "PERFCOUNTER_INT5_ACK", 13, 13, &umr_bitfield_default },
	 { "PERFCOUNTER_INT6_ACK", 14, 14, &umr_bitfield_default },
	 { "PERFCOUNTER_INT7_ACK", 15, 15, &umr_bitfield_default },
	 { "PERFMON_CVALUE_HI", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_PERFMON11_PERFMON_CVALUE_LOW[] = {
	 { "PERFMON_CVALUE_LOW", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_PERFMON11_PERFMON_HI[] = {
	 { "PERFMON_HI", 0, 15, &umr_bitfield_default },
	 { "PERFMON_READ_SEL", 29, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_PERFMON11_PERFMON_LOW[] = {
	 { "PERFMON_LOW", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDPP_TOP0_DPP_CONTROL[] = {
	 { "DPP_CLOCK_ENABLE", 4, 4, &umr_bitfield_default },
	 { "DPPCLK_G_GATE_DISABLE", 8, 8, &umr_bitfield_default },
	 { "DPPCLK_G_DYN_GATE_DISABLE", 10, 10, &umr_bitfield_default },
	 { "DPPCLK_G_DSCL_GATE_DISABLE", 12, 12, &umr_bitfield_default },
	 { "DPPCLK_R_GATE_DISABLE", 16, 16, &umr_bitfield_default },
	 { "DISPCLK_R_GATE_DISABLE", 18, 18, &umr_bitfield_default },
	 { "DISPCLK_G_GATE_DISABLE", 20, 20, &umr_bitfield_default },
	 { "DPPCLK_RATE_CONTROL", 24, 24, &umr_bitfield_default },
	 { "DPP_TEST_CLK_SEL", 28, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmDPP_TOP0_DPP_SOFT_RESET[] = {
	 { "CNVC_SOFT_RESET", 0, 0, &umr_bitfield_default },
	 { "DSCL_SOFT_RESET", 4, 4, &umr_bitfield_default },
	 { "CM_SOFT_RESET", 8, 8, &umr_bitfield_default },
	 { "OBUF_SOFT_RESET", 12, 12, &umr_bitfield_default },
};
static struct umr_bitfield mmDPP_TOP0_DPP_CRC_VAL_R_G[] = {
	 { "DPP_CRC_R_CR", 0, 15, &umr_bitfield_default },
	 { "DPP_CRC_G_Y", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDPP_TOP0_DPP_CRC_VAL_B_A[] = {
	 { "DPP_CRC_B_CB", 0, 15, &umr_bitfield_default },
	 { "DPP_CRC_ALPHA", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDPP_TOP0_DPP_CRC_CTRL[] = {
	 { "DPP_CRC_EN", 0, 0, &umr_bitfield_default },
	 { "DPP_CRC_CONT_EN", 1, 1, &umr_bitfield_default },
	 { "DPP_CRC_ONE_SHOT_PENDING", 2, 2, &umr_bitfield_default },
	 { "DPP_CRC_420_COMP_SEL", 3, 3, &umr_bitfield_default },
	 { "DPP_CRC_SRC_SEL", 4, 5, &umr_bitfield_default },
	 { "DPP_CRC_STEREO_EN", 7, 7, &umr_bitfield_default },
	 { "DPP_CRC_STEREO_MODE", 8, 9, &umr_bitfield_default },
	 { "DPP_CRC_INTERLACE_MODE", 10, 11, &umr_bitfield_default },
	 { "DPP_CRC_PIX_FORMAT_SEL", 12, 14, &umr_bitfield_default },
	 { "DPP_CRC_CURSOR_FORMAT_SEL", 15, 15, &umr_bitfield_default },
	 { "DPP_CRC_MASK", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDPP_TOP0_HOST_READ_CONTROL[] = {
	 { "HOST_READ_RATE_CONTROL", 0, 7, &umr_bitfield_default },
};
static struct umr_bitfield mmCNVC_CFG0_CNVC_SURFACE_PIXEL_FORMAT[] = {
	 { "CNVC_SURFACE_PIXEL_FORMAT", 0, 6, &umr_bitfield_default },
};
static struct umr_bitfield mmCNVC_CFG0_FORMAT_CONTROL[] = {
	 { "FORMAT_EXPANSION_MODE", 0, 0, &umr_bitfield_default },
	 { "FORMAT_CNV16", 4, 4, &umr_bitfield_default },
	 { "ALPHA_EN", 8, 8, &umr_bitfield_default },
	 { "CNVC_BYPASS", 12, 12, &umr_bitfield_default },
	 { "OUTPUT_FP", 16, 16, &umr_bitfield_default },
	 { "CNVC_UPDATE_PENDING", 20, 20, &umr_bitfield_default },
};
static struct umr_bitfield mmCNVC_CFG0_FCNV_FP_SCALE_BIAS[] = {
	 { "FCNV_FP_SCALE", 0, 15, &umr_bitfield_default },
	 { "FCNV_FP_BIAS", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmCNVC_CFG0_DENORM_CONTROL[] = {
	 { "DENORM_SCALE", 0, 14, &umr_bitfield_default },
	 { "CLAMP_POSITIVE", 15, 15, &umr_bitfield_default },
	 { "DENORM_BIAS", 16, 30, &umr_bitfield_default },
	 { "DENORM_TRUNCATE", 31, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmCNVC_CFG0_COLOR_KEYER_CONTROL[] = {
	 { "COLOR_KEYER_EN", 0, 0, &umr_bitfield_default },
	 { "COLOR_KEYER_MODE", 4, 5, &umr_bitfield_default },
};
static struct umr_bitfield mmCNVC_CFG0_COLOR_KEYER_ALPHA[] = {
	 { "COLOR_KEYER_ALPHA_LOW", 0, 15, &umr_bitfield_default },
	 { "COLOR_KEYER_ALPHA_HIGH", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmCNVC_CFG0_COLOR_KEYER_RED[] = {
	 { "COLOR_KEYER_RED_LOW", 0, 15, &umr_bitfield_default },
	 { "COLOR_KEYER_RED_HIGH", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmCNVC_CFG0_COLOR_KEYER_GREEN[] = {
	 { "COLOR_KEYER_GREEN_LOW", 0, 15, &umr_bitfield_default },
	 { "COLOR_KEYER_GREEN_HIGH", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmCNVC_CFG0_COLOR_KEYER_BLUE[] = {
	 { "COLOR_KEYER_BLUE_LOW", 0, 15, &umr_bitfield_default },
	 { "COLOR_KEYER_BLUE_HIGH", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmCNVC_CUR0_CURSOR0_CONTROL[] = {
	 { "CUR0_ENABLE", 0, 0, &umr_bitfield_default },
	 { "CUR0_EXPANSION_MODE", 1, 1, &umr_bitfield_default },
	 { "CUR0_INVERT_MODE", 2, 2, &umr_bitfield_default },
	 { "CUR0_MODE", 4, 5, &umr_bitfield_default },
	 { "CUR0_UPDATE_PENDING", 6, 6, &umr_bitfield_default },
	 { "CUR0_MAX", 8, 19, &umr_bitfield_default },
	 { "CUR0_MIN", 20, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmCNVC_CUR0_CURSOR0_COLOR0[] = {
	 { "CUR0_COLOR0", 0, 23, &umr_bitfield_default },
};
static struct umr_bitfield mmCNVC_CUR0_CURSOR0_COLOR1[] = {
	 { "CUR0_COLOR1", 0, 23, &umr_bitfield_default },
};
static struct umr_bitfield mmCNVC_CUR0_CURSOR0_FP_SCALE_BIAS[] = {
	 { "CUR0_FP_SCALE", 0, 15, &umr_bitfield_default },
	 { "CUR0_FP_BIAS", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDSCL0_SCL_COEF_RAM_TAP_SELECT[] = {
	 { "SCL_COEF_RAM_TAP_PAIR_IDX", 0, 1, &umr_bitfield_default },
	 { "SCL_COEF_RAM_PHASE", 8, 13, &umr_bitfield_default },
	 { "SCL_COEF_RAM_FILTER_TYPE", 16, 18, &umr_bitfield_default },
};
static struct umr_bitfield mmDSCL0_SCL_COEF_RAM_TAP_DATA[] = {
	 { "SCL_COEF_RAM_EVEN_TAP_COEF", 0, 13, &umr_bitfield_default },
	 { "SCL_COEF_RAM_EVEN_TAP_COEF_EN", 15, 15, &umr_bitfield_default },
	 { "SCL_COEF_RAM_ODD_TAP_COEF", 16, 29, &umr_bitfield_default },
	 { "SCL_COEF_RAM_ODD_TAP_COEF_EN", 31, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDSCL0_SCL_MODE[] = {
	 { "DSCL_MODE", 0, 2, &umr_bitfield_default },
	 { "SCL_COEF_RAM_SELECT", 8, 8, &umr_bitfield_default },
	 { "SCL_COEF_RAM_SELECT_CURRENT", 12, 12, &umr_bitfield_default },
	 { "SCL_CHROMA_COEF_MODE", 16, 16, &umr_bitfield_default },
	 { "SCL_ALPHA_COEF_MODE", 20, 20, &umr_bitfield_default },
	 { "SCL_COEF_RAM_SELECT_RD", 24, 24, &umr_bitfield_default },
};
static struct umr_bitfield mmDSCL0_SCL_TAP_CONTROL[] = {
	 { "SCL_V_NUM_TAPS", 0, 2, &umr_bitfield_default },
	 { "SCL_H_NUM_TAPS", 4, 6, &umr_bitfield_default },
	 { "SCL_V_NUM_TAPS_C", 8, 10, &umr_bitfield_default },
	 { "SCL_H_NUM_TAPS_C", 12, 14, &umr_bitfield_default },
};
static struct umr_bitfield mmDSCL0_DSCL_CONTROL[] = {
	 { "SCL_BOUNDARY_MODE", 0, 0, &umr_bitfield_default },
};
static struct umr_bitfield mmDSCL0_DSCL_2TAP_CONTROL[] = {
	 { "SCL_H_2TAP_HARDCODE_COEF_EN", 0, 0, &umr_bitfield_default },
	 { "SCL_H_2TAP_SHARP_EN", 4, 4, &umr_bitfield_default },
	 { "SCL_H_2TAP_SHARP_FACTOR", 8, 10, &umr_bitfield_default },
	 { "SCL_V_2TAP_HARDCODE_COEF_EN", 16, 16, &umr_bitfield_default },
	 { "SCL_V_2TAP_SHARP_EN", 20, 20, &umr_bitfield_default },
	 { "SCL_V_2TAP_SHARP_FACTOR", 24, 26, &umr_bitfield_default },
};
static struct umr_bitfield mmDSCL0_SCL_MANUAL_REPLICATE_CONTROL[] = {
	 { "SCL_V_MANUAL_REPLICATE_FACTOR", 0, 3, &umr_bitfield_default },
	 { "SCL_H_MANUAL_REPLICATE_FACTOR", 8, 11, &umr_bitfield_default },
};
static struct umr_bitfield mmDSCL0_SCL_HORZ_FILTER_SCALE_RATIO[] = {
	 { "SCL_H_SCALE_RATIO", 0, 25, &umr_bitfield_default },
};
static struct umr_bitfield mmDSCL0_SCL_HORZ_FILTER_INIT[] = {
	 { "SCL_H_INIT_FRAC", 0, 23, &umr_bitfield_default },
	 { "SCL_H_INIT_INT", 24, 27, &umr_bitfield_default },
};
static struct umr_bitfield mmDSCL0_SCL_HORZ_FILTER_SCALE_RATIO_C[] = {
	 { "SCL_H_SCALE_RATIO_C", 0, 25, &umr_bitfield_default },
};
static struct umr_bitfield mmDSCL0_SCL_HORZ_FILTER_INIT_C[] = {
	 { "SCL_H_INIT_FRAC_C", 0, 23, &umr_bitfield_default },
	 { "SCL_H_INIT_INT_C", 24, 27, &umr_bitfield_default },
};
static struct umr_bitfield mmDSCL0_SCL_VERT_FILTER_SCALE_RATIO[] = {
	 { "SCL_V_SCALE_RATIO", 0, 25, &umr_bitfield_default },
};
static struct umr_bitfield mmDSCL0_SCL_VERT_FILTER_INIT[] = {
	 { "SCL_V_INIT_FRAC", 0, 23, &umr_bitfield_default },
	 { "SCL_V_INIT_INT", 24, 27, &umr_bitfield_default },
};
static struct umr_bitfield mmDSCL0_SCL_VERT_FILTER_INIT_BOT[] = {
	 { "SCL_V_INIT_FRAC_BOT", 0, 23, &umr_bitfield_default },
	 { "SCL_V_INIT_INT_BOT", 24, 27, &umr_bitfield_default },
};
static struct umr_bitfield mmDSCL0_SCL_VERT_FILTER_SCALE_RATIO_C[] = {
	 { "SCL_V_SCALE_RATIO_C", 0, 25, &umr_bitfield_default },
};
static struct umr_bitfield mmDSCL0_SCL_VERT_FILTER_INIT_C[] = {
	 { "SCL_V_INIT_FRAC_C", 0, 23, &umr_bitfield_default },
	 { "SCL_V_INIT_INT_C", 24, 27, &umr_bitfield_default },
};
static struct umr_bitfield mmDSCL0_SCL_VERT_FILTER_INIT_BOT_C[] = {
	 { "SCL_V_INIT_FRAC_BOT_C", 0, 23, &umr_bitfield_default },
	 { "SCL_V_INIT_INT_BOT_C", 24, 27, &umr_bitfield_default },
};
static struct umr_bitfield mmDSCL0_SCL_BLACK_OFFSET[] = {
	 { "SCL_BLACK_OFFSET_RGB_Y", 0, 15, &umr_bitfield_default },
	 { "SCL_BLACK_OFFSET_CBCR", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDSCL0_DSCL_UPDATE[] = {
	 { "SCL_UPDATE_PENDING", 0, 0, &umr_bitfield_default },
};
static struct umr_bitfield mmDSCL0_DSCL_AUTOCAL[] = {
	 { "AUTOCAL_MODE", 0, 1, &umr_bitfield_default },
	 { "AUTOCAL_NUM_PIPE", 8, 9, &umr_bitfield_default },
	 { "AUTOCAL_PIPE_ID", 12, 13, &umr_bitfield_default },
};
static struct umr_bitfield mmDSCL0_DSCL_EXT_OVERSCAN_LEFT_RIGHT[] = {
	 { "EXT_OVERSCAN_RIGHT", 0, 12, &umr_bitfield_default },
	 { "EXT_OVERSCAN_LEFT", 16, 28, &umr_bitfield_default },
};
static struct umr_bitfield mmDSCL0_DSCL_EXT_OVERSCAN_TOP_BOTTOM[] = {
	 { "EXT_OVERSCAN_BOTTOM", 0, 12, &umr_bitfield_default },
	 { "EXT_OVERSCAN_TOP", 16, 28, &umr_bitfield_default },
};
static struct umr_bitfield mmDSCL0_OTG_H_BLANK[] = {
	 { "OTG_H_BLANK_START", 0, 13, &umr_bitfield_default },
	 { "OTG_H_BLANK_END", 16, 29, &umr_bitfield_default },
};
static struct umr_bitfield mmDSCL0_OTG_V_BLANK[] = {
	 { "OTG_V_BLANK_START", 0, 13, &umr_bitfield_default },
	 { "OTG_V_BLANK_END", 16, 29, &umr_bitfield_default },
};
static struct umr_bitfield mmDSCL0_RECOUT_START[] = {
	 { "RECOUT_START_X", 0, 12, &umr_bitfield_default },
	 { "RECOUT_START_Y", 16, 28, &umr_bitfield_default },
};
static struct umr_bitfield mmDSCL0_RECOUT_SIZE[] = {
	 { "RECOUT_WIDTH", 0, 13, &umr_bitfield_default },
	 { "RECOUT_HEIGHT", 16, 29, &umr_bitfield_default },
};
static struct umr_bitfield mmDSCL0_MPC_SIZE[] = {
	 { "MPC_WIDTH", 0, 13, &umr_bitfield_default },
	 { "MPC_HEIGHT", 16, 29, &umr_bitfield_default },
};
static struct umr_bitfield mmDSCL0_LB_DATA_FORMAT[] = {
	 { "PIXEL_DEPTH", 0, 1, &umr_bitfield_default },
	 { "PIXEL_EXPAN_MODE", 8, 8, &umr_bitfield_default },
	 { "PIXEL_REDUCE_MODE", 12, 12, &umr_bitfield_default },
	 { "DYNAMIC_PIXEL_DEPTH", 16, 16, &umr_bitfield_default },
	 { "DITHER_EN", 20, 20, &umr_bitfield_default },
	 { "INTERLEAVE_EN", 24, 24, &umr_bitfield_default },
	 { "ALPHA_EN", 31, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDSCL0_LB_MEMORY_CTRL[] = {
	 { "MEMORY_CONFIG", 0, 1, &umr_bitfield_default },
	 { "LB_MAX_PARTITIONS", 8, 13, &umr_bitfield_default },
	 { "LB_NUM_PARTITIONS", 16, 22, &umr_bitfield_default },
	 { "LB_NUM_PARTITIONS_C", 24, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmDSCL0_LB_V_COUNTER[] = {
	 { "V_COUNTER", 0, 12, &umr_bitfield_default },
	 { "V_COUNTER_C", 16, 28, &umr_bitfield_default },
};
static struct umr_bitfield mmDSCL0_DSCL_MEM_PWR_CTRL[] = {
	 { "LUT_MEM_PWR_FORCE", 0, 1, &umr_bitfield_default },
	 { "LUT_MEM_PWR_DIS", 2, 2, &umr_bitfield_default },
	 { "LB_G1_MEM_PWR_FORCE", 4, 5, &umr_bitfield_default },
	 { "LB_G1_MEM_PWR_DIS", 6, 6, &umr_bitfield_default },
	 { "LB_G2_MEM_PWR_FORCE", 8, 9, &umr_bitfield_default },
	 { "LB_G2_MEM_PWR_DIS", 10, 10, &umr_bitfield_default },
	 { "LB_G3_MEM_PWR_FORCE", 12, 13, &umr_bitfield_default },
	 { "LB_G3_MEM_PWR_DIS", 14, 14, &umr_bitfield_default },
	 { "LB_G4_MEM_PWR_FORCE", 16, 17, &umr_bitfield_default },
	 { "LB_G4_MEM_PWR_DIS", 18, 18, &umr_bitfield_default },
	 { "LB_G5_MEM_PWR_FORCE", 20, 21, &umr_bitfield_default },
	 { "LB_G5_MEM_PWR_DIS", 22, 22, &umr_bitfield_default },
	 { "LB_G6_MEM_PWR_FORCE", 24, 25, &umr_bitfield_default },
	 { "LB_G6_MEM_PWR_DIS", 26, 26, &umr_bitfield_default },
};
static struct umr_bitfield mmDSCL0_DSCL_MEM_PWR_STATUS[] = {
	 { "LUT_MEM_PWR_STATE", 0, 1, &umr_bitfield_default },
	 { "LB_G1_MEM_PWR_STATE", 2, 3, &umr_bitfield_default },
	 { "LB_G2_MEM_PWR_STATE", 4, 5, &umr_bitfield_default },
	 { "LB_G3_MEM_PWR_STATE", 6, 7, &umr_bitfield_default },
	 { "LB_G4_MEM_PWR_STATE", 8, 9, &umr_bitfield_default },
	 { "LB_G5_MEM_PWR_STATE", 10, 11, &umr_bitfield_default },
	 { "LB_G6_MEM_PWR_STATE", 12, 13, &umr_bitfield_default },
};
static struct umr_bitfield mmDSCL0_OBUF_CONTROL[] = {
	 { "OBUF_BYPASS", 0, 0, &umr_bitfield_default },
	 { "OBUF_USE_FULL_BUFFER", 4, 4, &umr_bitfield_default },
	 { "OBUF_H_2X_UPSCALE_EN", 8, 8, &umr_bitfield_default },
	 { "OBUF_IS_HALF_RECOUT_WIDTH", 12, 12, &umr_bitfield_default },
	 { "OBUF_H_2X_COEF_PHASE0_SEL", 16, 16, &umr_bitfield_default },
	 { "OBUF_H_2X_COEF_PHASE1_SEL", 24, 24, &umr_bitfield_default },
	 { "OBUF_OUT_HOLD_CNT", 28, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDSCL0_OBUF_MEM_PWR_CTRL[] = {
	 { "OBUF_MEM_PWR_FORCE", 0, 1, &umr_bitfield_default },
	 { "OBUF_MEM_PWR_DIS", 2, 2, &umr_bitfield_default },
	 { "OBUF_MEM_PWR_STATE", 16, 17, &umr_bitfield_default },
};
static struct umr_bitfield mmCM0_CM_CONTROL[] = {
	 { "CM_BYPASS_EN", 0, 0, &umr_bitfield_default },
	 { "CM_UPDATE_PENDING", 8, 8, &umr_bitfield_default },
};
static struct umr_bitfield mmCM0_CM_COMA_C11_C12[] = {
	 { "CM_COMA_C11", 0, 15, &umr_bitfield_default },
	 { "CM_COMA_C12", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmCM0_CM_COMA_C13_C14[] = {
	 { "CM_COMA_C13", 0, 15, &umr_bitfield_default },
	 { "CM_COMA_C14", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmCM0_CM_COMA_C21_C22[] = {
	 { "CM_COMA_C21", 0, 15, &umr_bitfield_default },
	 { "CM_COMA_C22", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmCM0_CM_COMA_C23_C24[] = {
	 { "CM_COMA_C23", 0, 15, &umr_bitfield_default },
	 { "CM_COMA_C24", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmCM0_CM_COMA_C31_C32[] = {
	 { "CM_COMA_C31", 0, 15, &umr_bitfield_default },
	 { "CM_COMA_C32", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmCM0_CM_COMA_C33_C34[] = {
	 { "CM_COMA_C33", 0, 15, &umr_bitfield_default },
	 { "CM_COMA_C34", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmCM0_CM_COMB_C11_C12[] = {
	 { "CM_COMB_C11", 0, 15, &umr_bitfield_default },
	 { "CM_COMB_C12", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmCM0_CM_COMB_C13_C14[] = {
	 { "CM_COMB_C13", 0, 15, &umr_bitfield_default },
	 { "CM_COMB_C14", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmCM0_CM_COMB_C21_C22[] = {
	 { "CM_COMB_C21", 0, 15, &umr_bitfield_default },
	 { "CM_COMB_C22", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmCM0_CM_COMB_C23_C24[] = {
	 { "CM_COMB_C23", 0, 15, &umr_bitfield_default },
	 { "CM_COMB_C24", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmCM0_CM_COMB_C31_C32[] = {
	 { "CM_COMB_C31", 0, 15, &umr_bitfield_default },
	 { "CM_COMB_C32", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmCM0_CM_COMB_C33_C34[] = {
	 { "CM_COMB_C33", 0, 15, &umr_bitfield_default },
	 { "CM_COMB_C34", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmCM0_CM_IGAM_CONTROL[] = {
	 { "CM_IGAM_LUT_MODE", 0, 1, &umr_bitfield_default },
	 { "CM_IGAM_LUT_DATA_SIGNED_EN_B", 2, 2, &umr_bitfield_default },
	 { "CM_IGAM_LUT_DATA_SIGNED_EN_G", 3, 3, &umr_bitfield_default },
	 { "CM_IGAM_LUT_DATA_SIGNED_EN_R", 4, 4, &umr_bitfield_default },
	 { "CM_IGAM_LUT_INC_B", 5, 8, &umr_bitfield_default },
	 { "CM_IGAM_LUT_INC_G", 9, 12, &umr_bitfield_default },
	 { "CM_IGAM_LUT_INC_R", 13, 16, &umr_bitfield_default },
	 { "CM_IGAM_LUT_FORMAT_B", 17, 18, &umr_bitfield_default },
	 { "CM_IGAM_LUT_FORMAT_G", 19, 20, &umr_bitfield_default },
	 { "CM_IGAM_LUT_FORMAT_R", 21, 22, &umr_bitfield_default },
	 { "CM_IGAM_LUT_B_FLOAT_POINT_EN", 23, 23, &umr_bitfield_default },
	 { "CM_IGAM_LUT_G_FLOAT_POINT_EN", 24, 24, &umr_bitfield_default },
	 { "CM_IGAM_LUT_R_FLOAT_POINT_EN", 25, 25, &umr_bitfield_default },
	 { "CM_IGAM_INPUT_FORMAT", 26, 27, &umr_bitfield_default },
};
static struct umr_bitfield mmCM0_CM_IGAM_LUT_RW_CONTROL[] = {
	 { "CM_IGAM_LUT_RW_MODE", 0, 0, &umr_bitfield_default },
	 { "CM_IGAM_LUT_WRITE_EN_MASK", 4, 6, &umr_bitfield_default },
	 { "CM_IGAM_LUT_SEL", 8, 8, &umr_bitfield_default },
	 { "CM_IGAM_LUT_HOST_EN", 12, 12, &umr_bitfield_default },
	 { "CM_IGAM_DGAM_CONFIG_STATUS", 16, 19, &umr_bitfield_default },
};
static struct umr_bitfield mmCM0_CM_IGAM_LUT_RW_INDEX[] = {
	 { "CM_IGAM_LUT_RW_INDEX", 0, 7, &umr_bitfield_default },
};
static struct umr_bitfield mmCM0_CM_IGAM_LUT_SEQ_COLOR[] = {
	 { "CM_IGAM_LUT_SEQ_COLOR", 0, 15, &umr_bitfield_default },
};
static struct umr_bitfield mmCM0_CM_IGAM_LUT_30_COLOR[] = {
	 { "CM_IGAM_LUT_10_BLUE", 0, 9, &umr_bitfield_default },
	 { "CM_IGAM_LUT_10_GREEN", 10, 19, &umr_bitfield_default },
	 { "CM_IGAM_LUT_10_RED", 20, 29, &umr_bitfield_default },
};
static struct umr_bitfield mmCM0_CM_IGAM_LUT_PWL_DATA[] = {
	 { "CM_IGAM_LUT_PWL_BASE", 0, 15, &umr_bitfield_default },
	 { "CM_IGAM_LUT_PWL_DELTA", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmCM0_CM_IGAM_LUT_AUTOFILL[] = {
	 { "CM_IGAM_LUT_AUTOFILL", 0, 0, &umr_bitfield_default },
	 { "CM_IGAM_LUT_AUTOFILL_DONE", 4, 4, &umr_bitfield_default },
};
static struct umr_bitfield mmCM0_CM_IGAM_LUT_BW_OFFSET_BLUE[] = {
	 { "CM_IGAM_LUT_BLACK_OFFSET_BLUE", 0, 15, &umr_bitfield_default },
	 { "CM_IGAM_LUT_WHITE_OFFSET_BLUE", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmCM0_CM_IGAM_LUT_BW_OFFSET_GREEN[] = {
	 { "CM_IGAM_LUT_BLACK_OFFSET_GREEN", 0, 15, &umr_bitfield_default },
	 { "CM_IGAM_LUT_WHITE_OFFSET_GREEN", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmCM0_CM_IGAM_LUT_BW_OFFSET_RED[] = {
	 { "CM_IGAM_LUT_BLACK_OFFSET_RED", 0, 15, &umr_bitfield_default },
	 { "CM_IGAM_LUT_WHITE_OFFSET_RED", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmCM0_CM_ICSC_CONTROL[] = {
	 { "CM_ICSC_MODE", 0, 1, &umr_bitfield_default },
};
static struct umr_bitfield mmCM0_CM_ICSC_C11_C12[] = {
	 { "CM_ICSC_C11", 0, 15, &umr_bitfield_default },
	 { "CM_ICSC_C12", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmCM0_CM_ICSC_C13_C14[] = {
	 { "CM_ICSC_C13", 0, 15, &umr_bitfield_default },
	 { "CM_ICSC_C14", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmCM0_CM_ICSC_C21_C22[] = {
	 { "CM_ICSC_C21", 0, 15, &umr_bitfield_default },
	 { "CM_ICSC_C22", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmCM0_CM_ICSC_C23_C24[] = {
	 { "CM_ICSC_C23", 0, 15, &umr_bitfield_default },
	 { "CM_ICSC_C24", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmCM0_CM_ICSC_C31_C32[] = {
	 { "CM_ICSC_C31", 0, 15, &umr_bitfield_default },
	 { "CM_ICSC_C32", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmCM0_CM_ICSC_C33_C34[] = {
	 { "CM_ICSC_C33", 0, 15, &umr_bitfield_default },
	 { "CM_ICSC_C34", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmCM0_CM_GAMUT_REMAP_CONTROL[] = {
	 { "CM_GAMUT_REMAP_MODE", 0, 1, &umr_bitfield_default },
};
static struct umr_bitfield mmCM0_CM_GAMUT_REMAP_C11_C12[] = {
	 { "CM_GAMUT_REMAP_C11", 0, 15, &umr_bitfield_default },
	 { "CM_GAMUT_REMAP_C12", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmCM0_CM_GAMUT_REMAP_C13_C14[] = {
	 { "CM_GAMUT_REMAP_C13", 0, 15, &umr_bitfield_default },
	 { "CM_GAMUT_REMAP_C14", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmCM0_CM_GAMUT_REMAP_C21_C22[] = {
	 { "CM_GAMUT_REMAP_C21", 0, 15, &umr_bitfield_default },
	 { "CM_GAMUT_REMAP_C22", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmCM0_CM_GAMUT_REMAP_C23_C24[] = {
	 { "CM_GAMUT_REMAP_C23", 0, 15, &umr_bitfield_default },
	 { "CM_GAMUT_REMAP_C24", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmCM0_CM_GAMUT_REMAP_C31_C32[] = {
	 { "CM_GAMUT_REMAP_C31", 0, 15, &umr_bitfield_default },
	 { "CM_GAMUT_REMAP_C32", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmCM0_CM_GAMUT_REMAP_C33_C34[] = {
	 { "CM_GAMUT_REMAP_C33", 0, 15, &umr_bitfield_default },
	 { "CM_GAMUT_REMAP_C34", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmCM0_CM_OCSC_CONTROL[] = {
	 { "CM_OCSC_MODE", 0, 2, &umr_bitfield_default },
};
static struct umr_bitfield mmCM0_CM_OCSC_C11_C12[] = {
	 { "CM_OCSC_C11", 0, 15, &umr_bitfield_default },
	 { "CM_OCSC_C12", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmCM0_CM_OCSC_C13_C14[] = {
	 { "CM_OCSC_C13", 0, 15, &umr_bitfield_default },
	 { "CM_OCSC_C14", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmCM0_CM_OCSC_C21_C22[] = {
	 { "CM_OCSC_C21", 0, 15, &umr_bitfield_default },
	 { "CM_OCSC_C22", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmCM0_CM_OCSC_C23_C24[] = {
	 { "CM_OCSC_C23", 0, 15, &umr_bitfield_default },
	 { "CM_OCSC_C24", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmCM0_CM_OCSC_C31_C32[] = {
	 { "CM_OCSC_C31", 0, 15, &umr_bitfield_default },
	 { "CM_OCSC_C32", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmCM0_CM_OCSC_C33_C34[] = {
	 { "CM_OCSC_C33", 0, 15, &umr_bitfield_default },
	 { "CM_OCSC_C34", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmCM0_CM_BNS_VALUES_R[] = {
	 { "CM_BNS_BIAS_R", 0, 15, &umr_bitfield_default },
	 { "CM_BNS_SCALE_R", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmCM0_CM_BNS_VALUES_G[] = {
	 { "CM_BNS_BIAS_G", 0, 15, &umr_bitfield_default },
	 { "CM_BNS_SCALE_G", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmCM0_CM_BNS_VALUES_B[] = {
	 { "CM_BNS_BIAS_B", 0, 15, &umr_bitfield_default },
	 { "CM_BNS_SCALE_B", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmCM0_CM_DGAM_CONTROL[] = {
	 { "CM_DGAM_LUT_MODE", 0, 2, &umr_bitfield_default },
};
static struct umr_bitfield mmCM0_CM_DGAM_LUT_INDEX[] = {
	 { "CM_DGAM_LUT_INDEX", 0, 8, &umr_bitfield_default },
};
static struct umr_bitfield mmCM0_CM_DGAM_LUT_DATA[] = {
	 { "CM_DGAM_LUT_DATA", 0, 18, &umr_bitfield_default },
};
static struct umr_bitfield mmCM0_CM_DGAM_LUT_WRITE_EN_MASK[] = {
	 { "CM_DGAM_LUT_WRITE_EN_MASK", 0, 2, &umr_bitfield_default },
	 { "CM_DGAM_LUT_WRITE_SEL", 4, 4, &umr_bitfield_default },
};
static struct umr_bitfield mmCM0_CM_DGAM_RAMA_START_CNTL_B[] = {
	 { "CM_DGAM_RAMA_EXP_REGION_START_B", 0, 17, &umr_bitfield_default },
	 { "CM_DGAM_RAMA_EXP_REGION_START_SEGMENT_B", 20, 26, &umr_bitfield_default },
};
static struct umr_bitfield mmCM0_CM_DGAM_RAMA_START_CNTL_G[] = {
	 { "CM_DGAM_RAMA_EXP_REGION_START_G", 0, 17, &umr_bitfield_default },
	 { "CM_DGAM_RAMA_EXP_REGION_START_SEGMENT_G", 20, 26, &umr_bitfield_default },
};
static struct umr_bitfield mmCM0_CM_DGAM_RAMA_START_CNTL_R[] = {
	 { "CM_DGAM_RAMA_EXP_REGION_START_R", 0, 17, &umr_bitfield_default },
	 { "CM_DGAM_RAMA_EXP_REGION_START_SEGMENT_R", 20, 26, &umr_bitfield_default },
};
static struct umr_bitfield mmCM0_CM_DGAM_RAMA_SLOPE_CNTL_B[] = {
	 { "CM_DGAM_RAMA_EXP_REGION_LINEAR_SLOPE_B", 0, 17, &umr_bitfield_default },
};
static struct umr_bitfield mmCM0_CM_DGAM_RAMA_SLOPE_CNTL_G[] = {
	 { "CM_DGAM_RAMA_EXP_REGION_LINEAR_SLOPE_G", 0, 17, &umr_bitfield_default },
};
static struct umr_bitfield mmCM0_CM_DGAM_RAMA_SLOPE_CNTL_R[] = {
	 { "CM_DGAM_RAMA_EXP_REGION_LINEAR_SLOPE_R", 0, 17, &umr_bitfield_default },
};
static struct umr_bitfield mmCM0_CM_DGAM_RAMA_END_CNTL1_B[] = {
	 { "CM_DGAM_RAMA_EXP_REGION_END_B", 0, 15, &umr_bitfield_default },
};
static struct umr_bitfield mmCM0_CM_DGAM_RAMA_END_CNTL2_B[] = {
	 { "CM_DGAM_RAMA_EXP_REGION_END_SLOPE_B", 0, 15, &umr_bitfield_default },
	 { "CM_DGAM_RAMA_EXP_REGION_END_BASE_B", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmCM0_CM_DGAM_RAMA_END_CNTL1_G[] = {
	 { "CM_DGAM_RAMA_EXP_REGION_END_G", 0, 15, &umr_bitfield_default },
};
static struct umr_bitfield mmCM0_CM_DGAM_RAMA_END_CNTL2_G[] = {
	 { "CM_DGAM_RAMA_EXP_REGION_END_SLOPE_G", 0, 15, &umr_bitfield_default },
	 { "CM_DGAM_RAMA_EXP_REGION_END_BASE_G", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmCM0_CM_DGAM_RAMA_END_CNTL1_R[] = {
	 { "CM_DGAM_RAMA_EXP_REGION_END_R", 0, 15, &umr_bitfield_default },
};
static struct umr_bitfield mmCM0_CM_DGAM_RAMA_END_CNTL2_R[] = {
	 { "CM_DGAM_RAMA_EXP_REGION_END_SLOPE_R", 0, 15, &umr_bitfield_default },
	 { "CM_DGAM_RAMA_EXP_REGION_END_BASE_R", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmCM0_CM_DGAM_RAMA_REGION_0_1[] = {
	 { "CM_DGAM_RAMA_EXP_REGION0_LUT_OFFSET", 0, 8, &umr_bitfield_default },
	 { "CM_DGAM_RAMA_EXP_REGION0_NUM_SEGMENTS", 12, 14, &umr_bitfield_default },
	 { "CM_DGAM_RAMA_EXP_REGION1_LUT_OFFSET", 16, 24, &umr_bitfield_default },
	 { "CM_DGAM_RAMA_EXP_REGION1_NUM_SEGMENTS", 28, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmCM0_CM_DGAM_RAMA_REGION_2_3[] = {
	 { "CM_DGAM_RAMA_EXP_REGION2_LUT_OFFSET", 0, 8, &umr_bitfield_default },
	 { "CM_DGAM_RAMA_EXP_REGION2_NUM_SEGMENTS", 12, 14, &umr_bitfield_default },
	 { "CM_DGAM_RAMA_EXP_REGION3_LUT_OFFSET", 16, 24, &umr_bitfield_default },
	 { "CM_DGAM_RAMA_EXP_REGION3_NUM_SEGMENTS", 28, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmCM0_CM_DGAM_RAMA_REGION_4_5[] = {
	 { "CM_DGAM_RAMA_EXP_REGION4_LUT_OFFSET", 0, 8, &umr_bitfield_default },
	 { "CM_DGAM_RAMA_EXP_REGION4_NUM_SEGMENTS", 12, 14, &umr_bitfield_default },
	 { "CM_DGAM_RAMA_EXP_REGION5_LUT_OFFSET", 16, 24, &umr_bitfield_default },
	 { "CM_DGAM_RAMA_EXP_REGION5_NUM_SEGMENTS", 28, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmCM0_CM_DGAM_RAMA_REGION_6_7[] = {
	 { "CM_DGAM_RAMA_EXP_REGION6_LUT_OFFSET", 0, 8, &umr_bitfield_default },
	 { "CM_DGAM_RAMA_EXP_REGION6_NUM_SEGMENTS", 12, 14, &umr_bitfield_default },
	 { "CM_DGAM_RAMA_EXP_REGION7_LUT_OFFSET", 16, 24, &umr_bitfield_default },
	 { "CM_DGAM_RAMA_EXP_REGION7_NUM_SEGMENTS", 28, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmCM0_CM_DGAM_RAMA_REGION_8_9[] = {
	 { "CM_DGAM_RAMA_EXP_REGION8_LUT_OFFSET", 0, 8, &umr_bitfield_default },
	 { "CM_DGAM_RAMA_EXP_REGION8_NUM_SEGMENTS", 12, 14, &umr_bitfield_default },
	 { "CM_DGAM_RAMA_EXP_REGION9_LUT_OFFSET", 16, 24, &umr_bitfield_default },
	 { "CM_DGAM_RAMA_EXP_REGION9_NUM_SEGMENTS", 28, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmCM0_CM_DGAM_RAMA_REGION_10_11[] = {
	 { "CM_DGAM_RAMA_EXP_REGION10_LUT_OFFSET", 0, 8, &umr_bitfield_default },
	 { "CM_DGAM_RAMA_EXP_REGION10_NUM_SEGMENTS", 12, 14, &umr_bitfield_default },
	 { "CM_DGAM_RAMA_EXP_REGION11_LUT_OFFSET", 16, 24, &umr_bitfield_default },
	 { "CM_DGAM_RAMA_EXP_REGION11_NUM_SEGMENTS", 28, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmCM0_CM_DGAM_RAMA_REGION_12_13[] = {
	 { "CM_DGAM_RAMA_EXP_REGION12_LUT_OFFSET", 0, 8, &umr_bitfield_default },
	 { "CM_DGAM_RAMA_EXP_REGION12_NUM_SEGMENTS", 12, 14, &umr_bitfield_default },
	 { "CM_DGAM_RAMA_EXP_REGION13_LUT_OFFSET", 16, 24, &umr_bitfield_default },
	 { "CM_DGAM_RAMA_EXP_REGION13_NUM_SEGMENTS", 28, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmCM0_CM_DGAM_RAMA_REGION_14_15[] = {
	 { "CM_DGAM_RAMA_EXP_REGION14_LUT_OFFSET", 0, 8, &umr_bitfield_default },
	 { "CM_DGAM_RAMA_EXP_REGION14_NUM_SEGMENTS", 12, 14, &umr_bitfield_default },
	 { "CM_DGAM_RAMA_EXP_REGION15_LUT_OFFSET", 16, 24, &umr_bitfield_default },
	 { "CM_DGAM_RAMA_EXP_REGION15_NUM_SEGMENTS", 28, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmCM0_CM_DGAM_RAMB_START_CNTL_B[] = {
	 { "CM_DGAM_RAMB_EXP_REGION_START_B", 0, 17, &umr_bitfield_default },
	 { "CM_DGAM_RAMB_EXP_REGION_START_SEGMENT_B", 20, 26, &umr_bitfield_default },
};
static struct umr_bitfield mmCM0_CM_DGAM_RAMB_START_CNTL_G[] = {
	 { "CM_DGAM_RAMB_EXP_REGION_START_G", 0, 17, &umr_bitfield_default },
	 { "CM_DGAM_RAMB_EXP_REGION_START_SEGMENT_G", 20, 26, &umr_bitfield_default },
};
static struct umr_bitfield mmCM0_CM_DGAM_RAMB_START_CNTL_R[] = {
	 { "CM_DGAM_RAMB_EXP_REGION_START_R", 0, 17, &umr_bitfield_default },
	 { "CM_DGAM_RAMB_EXP_REGION_START_SEGMENT_R", 20, 26, &umr_bitfield_default },
};
static struct umr_bitfield mmCM0_CM_DGAM_RAMB_SLOPE_CNTL_B[] = {
	 { "CM_DGAM_RAMB_EXP_REGION_LINEAR_SLOPE_B", 0, 17, &umr_bitfield_default },
};
static struct umr_bitfield mmCM0_CM_DGAM_RAMB_SLOPE_CNTL_G[] = {
	 { "CM_DGAM_RAMB_EXP_REGION_LINEAR_SLOPE_G", 0, 17, &umr_bitfield_default },
};
static struct umr_bitfield mmCM0_CM_DGAM_RAMB_SLOPE_CNTL_R[] = {
	 { "CM_DGAM_RAMB_EXP_REGION_LINEAR_SLOPE_R", 0, 17, &umr_bitfield_default },
};
static struct umr_bitfield mmCM0_CM_DGAM_RAMB_END_CNTL1_B[] = {
	 { "CM_DGAM_RAMB_EXP_REGION_END_B", 0, 15, &umr_bitfield_default },
};
static struct umr_bitfield mmCM0_CM_DGAM_RAMB_END_CNTL2_B[] = {
	 { "CM_DGAM_RAMB_EXP_REGION_END_SLOPE_B", 0, 15, &umr_bitfield_default },
	 { "CM_DGAM_RAMB_EXP_REGION_END_BASE_B", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmCM0_CM_DGAM_RAMB_END_CNTL1_G[] = {
	 { "CM_DGAM_RAMB_EXP_REGION_END_G", 0, 15, &umr_bitfield_default },
};
static struct umr_bitfield mmCM0_CM_DGAM_RAMB_END_CNTL2_G[] = {
	 { "CM_DGAM_RAMB_EXP_REGION_END_SLOPE_G", 0, 15, &umr_bitfield_default },
	 { "CM_DGAM_RAMB_EXP_REGION_END_BASE_G", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmCM0_CM_DGAM_RAMB_END_CNTL1_R[] = {
	 { "CM_DGAM_RAMB_EXP_REGION_END_R", 0, 15, &umr_bitfield_default },
};
static struct umr_bitfield mmCM0_CM_DGAM_RAMB_END_CNTL2_R[] = {
	 { "CM_DGAM_RAMB_EXP_REGION_END_SLOPE_R", 0, 15, &umr_bitfield_default },
	 { "CM_DGAM_RAMB_EXP_REGION_END_BASE_R", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmCM0_CM_DGAM_RAMB_REGION_0_1[] = {
	 { "CM_DGAM_RAMB_EXP_REGION0_LUT_OFFSET", 0, 8, &umr_bitfield_default },
	 { "CM_DGAM_RAMB_EXP_REGION0_NUM_SEGMENTS", 12, 14, &umr_bitfield_default },
	 { "CM_DGAM_RAMB_EXP_REGION1_LUT_OFFSET", 16, 24, &umr_bitfield_default },
	 { "CM_DGAM_RAMB_EXP_REGION1_NUM_SEGMENTS", 28, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmCM0_CM_DGAM_RAMB_REGION_2_3[] = {
	 { "CM_DGAM_RAMB_EXP_REGION2_LUT_OFFSET", 0, 8, &umr_bitfield_default },
	 { "CM_DGAM_RAMB_EXP_REGION2_NUM_SEGMENTS", 12, 14, &umr_bitfield_default },
	 { "CM_DGAM_RAMB_EXP_REGION3_LUT_OFFSET", 16, 24, &umr_bitfield_default },
	 { "CM_DGAM_RAMB_EXP_REGION3_NUM_SEGMENTS", 28, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmCM0_CM_DGAM_RAMB_REGION_4_5[] = {
	 { "CM_DGAM_RAMB_EXP_REGION4_LUT_OFFSET", 0, 8, &umr_bitfield_default },
	 { "CM_DGAM_RAMB_EXP_REGION4_NUM_SEGMENTS", 12, 14, &umr_bitfield_default },
	 { "CM_DGAM_RAMB_EXP_REGION5_LUT_OFFSET", 16, 24, &umr_bitfield_default },
	 { "CM_DGAM_RAMB_EXP_REGION5_NUM_SEGMENTS", 28, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmCM0_CM_DGAM_RAMB_REGION_6_7[] = {
	 { "CM_DGAM_RAMB_EXP_REGION6_LUT_OFFSET", 0, 8, &umr_bitfield_default },
	 { "CM_DGAM_RAMB_EXP_REGION6_NUM_SEGMENTS", 12, 14, &umr_bitfield_default },
	 { "CM_DGAM_RAMB_EXP_REGION7_LUT_OFFSET", 16, 24, &umr_bitfield_default },
	 { "CM_DGAM_RAMB_EXP_REGION7_NUM_SEGMENTS", 28, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmCM0_CM_DGAM_RAMB_REGION_8_9[] = {
	 { "CM_DGAM_RAMB_EXP_REGION8_LUT_OFFSET", 0, 8, &umr_bitfield_default },
	 { "CM_DGAM_RAMB_EXP_REGION8_NUM_SEGMENTS", 12, 14, &umr_bitfield_default },
	 { "CM_DGAM_RAMB_EXP_REGION9_LUT_OFFSET", 16, 24, &umr_bitfield_default },
	 { "CM_DGAM_RAMB_EXP_REGION9_NUM_SEGMENTS", 28, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmCM0_CM_DGAM_RAMB_REGION_10_11[] = {
	 { "CM_DGAM_RAMB_EXP_REGION10_LUT_OFFSET", 0, 8, &umr_bitfield_default },
	 { "CM_DGAM_RAMB_EXP_REGION10_NUM_SEGMENTS", 12, 14, &umr_bitfield_default },
	 { "CM_DGAM_RAMB_EXP_REGION11_LUT_OFFSET", 16, 24, &umr_bitfield_default },
	 { "CM_DGAM_RAMB_EXP_REGION11_NUM_SEGMENTS", 28, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmCM0_CM_DGAM_RAMB_REGION_12_13[] = {
	 { "CM_DGAM_RAMB_EXP_REGION12_LUT_OFFSET", 0, 8, &umr_bitfield_default },
	 { "CM_DGAM_RAMB_EXP_REGION12_NUM_SEGMENTS", 12, 14, &umr_bitfield_default },
	 { "CM_DGAM_RAMB_EXP_REGION13_LUT_OFFSET", 16, 24, &umr_bitfield_default },
	 { "CM_DGAM_RAMB_EXP_REGION13_NUM_SEGMENTS", 28, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmCM0_CM_DGAM_RAMB_REGION_14_15[] = {
	 { "CM_DGAM_RAMB_EXP_REGION14_LUT_OFFSET", 0, 8, &umr_bitfield_default },
	 { "CM_DGAM_RAMB_EXP_REGION14_NUM_SEGMENTS", 12, 14, &umr_bitfield_default },
	 { "CM_DGAM_RAMB_EXP_REGION15_LUT_OFFSET", 16, 24, &umr_bitfield_default },
	 { "CM_DGAM_RAMB_EXP_REGION15_NUM_SEGMENTS", 28, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmCM0_CM_RGAM_CONTROL[] = {
	 { "CM_RGAM_LUT_MODE", 0, 2, &umr_bitfield_default },
};
static struct umr_bitfield mmCM0_CM_RGAM_LUT_INDEX[] = {
	 { "CM_RGAM_LUT_INDEX", 0, 8, &umr_bitfield_default },
};
static struct umr_bitfield mmCM0_CM_RGAM_LUT_DATA[] = {
	 { "CM_RGAM_LUT_DATA", 0, 18, &umr_bitfield_default },
};
static struct umr_bitfield mmCM0_CM_RGAM_LUT_WRITE_EN_MASK[] = {
	 { "CM_RGAM_LUT_WRITE_EN_MASK", 0, 2, &umr_bitfield_default },
	 { "CM_RGAM_LUT_WRITE_SEL", 4, 4, &umr_bitfield_default },
	 { "CM_RGAM_CONFIG_STATUS", 8, 10, &umr_bitfield_default },
};
static struct umr_bitfield mmCM0_CM_RGAM_RAMA_START_CNTL_B[] = {
	 { "CM_RGAM_RAMA_EXP_REGION_START_B", 0, 17, &umr_bitfield_default },
	 { "CM_RGAM_RAMA_EXP_REGION_START_SEGMENT_B", 20, 26, &umr_bitfield_default },
};
static struct umr_bitfield mmCM0_CM_RGAM_RAMA_START_CNTL_G[] = {
	 { "CM_RGAM_RAMA_EXP_REGION_START_G", 0, 17, &umr_bitfield_default },
	 { "CM_RGAM_RAMA_EXP_REGION_START_SEGMENT_G", 20, 26, &umr_bitfield_default },
};
static struct umr_bitfield mmCM0_CM_RGAM_RAMA_START_CNTL_R[] = {
	 { "CM_RGAM_RAMA_EXP_REGION_START_R", 0, 17, &umr_bitfield_default },
	 { "CM_RGAM_RAMA_EXP_REGION_START_SEGMENT_R", 20, 26, &umr_bitfield_default },
};
static struct umr_bitfield mmCM0_CM_RGAM_RAMA_SLOPE_CNTL_B[] = {
	 { "CM_RGAM_RAMA_EXP_REGION_LINEAR_SLOPE_B", 0, 17, &umr_bitfield_default },
};
static struct umr_bitfield mmCM0_CM_RGAM_RAMA_SLOPE_CNTL_G[] = {
	 { "CM_RGAM_RAMA_EXP_REGION_LINEAR_SLOPE_G", 0, 17, &umr_bitfield_default },
};
static struct umr_bitfield mmCM0_CM_RGAM_RAMA_SLOPE_CNTL_R[] = {
	 { "CM_RGAM_RAMA_EXP_REGION_LINEAR_SLOPE_R", 0, 17, &umr_bitfield_default },
};
static struct umr_bitfield mmCM0_CM_RGAM_RAMA_END_CNTL1_B[] = {
	 { "CM_RGAM_RAMA_EXP_REGION_END_B", 0, 15, &umr_bitfield_default },
};
static struct umr_bitfield mmCM0_CM_RGAM_RAMA_END_CNTL2_B[] = {
	 { "CM_RGAM_RAMA_EXP_REGION_END_SLOPE_B", 0, 15, &umr_bitfield_default },
	 { "CM_RGAM_RAMA_EXP_REGION_END_BASE_B", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmCM0_CM_RGAM_RAMA_END_CNTL1_G[] = {
	 { "CM_RGAM_RAMA_EXP_REGION_END_G", 0, 15, &umr_bitfield_default },
};
static struct umr_bitfield mmCM0_CM_RGAM_RAMA_END_CNTL2_G[] = {
	 { "CM_RGAM_RAMA_EXP_REGION_END_SLOPE_G", 0, 15, &umr_bitfield_default },
	 { "CM_RGAM_RAMA_EXP_REGION_END_BASE_G", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmCM0_CM_RGAM_RAMA_END_CNTL1_R[] = {
	 { "CM_RGAM_RAMA_EXP_REGION_END_R", 0, 15, &umr_bitfield_default },
};
static struct umr_bitfield mmCM0_CM_RGAM_RAMA_END_CNTL2_R[] = {
	 { "CM_RGAM_RAMA_EXP_REGION_END_SLOPE_R", 0, 15, &umr_bitfield_default },
	 { "CM_RGAM_RAMA_EXP_REGION_END_BASE_R", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmCM0_CM_RGAM_RAMA_REGION_0_1[] = {
	 { "CM_RGAM_RAMA_EXP_REGION0_LUT_OFFSET", 0, 8, &umr_bitfield_default },
	 { "CM_RGAM_RAMA_EXP_REGION0_NUM_SEGMENTS", 12, 14, &umr_bitfield_default },
	 { "CM_RGAM_RAMA_EXP_REGION1_LUT_OFFSET", 16, 24, &umr_bitfield_default },
	 { "CM_RGAM_RAMA_EXP_REGION1_NUM_SEGMENTS", 28, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmCM0_CM_RGAM_RAMA_REGION_2_3[] = {
	 { "CM_RGAM_RAMA_EXP_REGION2_LUT_OFFSET", 0, 8, &umr_bitfield_default },
	 { "CM_RGAM_RAMA_EXP_REGION2_NUM_SEGMENTS", 12, 14, &umr_bitfield_default },
	 { "CM_RGAM_RAMA_EXP_REGION3_LUT_OFFSET", 16, 24, &umr_bitfield_default },
	 { "CM_RGAM_RAMA_EXP_REGION3_NUM_SEGMENTS", 28, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmCM0_CM_RGAM_RAMA_REGION_4_5[] = {
	 { "CM_RGAM_RAMA_EXP_REGION4_LUT_OFFSET", 0, 8, &umr_bitfield_default },
	 { "CM_RGAM_RAMA_EXP_REGION4_NUM_SEGMENTS", 12, 14, &umr_bitfield_default },
	 { "CM_RGAM_RAMA_EXP_REGION5_LUT_OFFSET", 16, 24, &umr_bitfield_default },
	 { "CM_RGAM_RAMA_EXP_REGION5_NUM_SEGMENTS", 28, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmCM0_CM_RGAM_RAMA_REGION_6_7[] = {
	 { "CM_RGAM_RAMA_EXP_REGION6_LUT_OFFSET", 0, 8, &umr_bitfield_default },
	 { "CM_RGAM_RAMA_EXP_REGION6_NUM_SEGMENTS", 12, 14, &umr_bitfield_default },
	 { "CM_RGAM_RAMA_EXP_REGION7_LUT_OFFSET", 16, 24, &umr_bitfield_default },
	 { "CM_RGAM_RAMA_EXP_REGION7_NUM_SEGMENTS", 28, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmCM0_CM_RGAM_RAMA_REGION_8_9[] = {
	 { "CM_RGAM_RAMA_EXP_REGION8_LUT_OFFSET", 0, 8, &umr_bitfield_default },
	 { "CM_RGAM_RAMA_EXP_REGION8_NUM_SEGMENTS", 12, 14, &umr_bitfield_default },
	 { "CM_RGAM_RAMA_EXP_REGION9_LUT_OFFSET", 16, 24, &umr_bitfield_default },
	 { "CM_RGAM_RAMA_EXP_REGION9_NUM_SEGMENTS", 28, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmCM0_CM_RGAM_RAMA_REGION_10_11[] = {
	 { "CM_RGAM_RAMA_EXP_REGION10_LUT_OFFSET", 0, 8, &umr_bitfield_default },
	 { "CM_RGAM_RAMA_EXP_REGION10_NUM_SEGMENTS", 12, 14, &umr_bitfield_default },
	 { "CM_RGAM_RAMA_EXP_REGION11_LUT_OFFSET", 16, 24, &umr_bitfield_default },
	 { "CM_RGAM_RAMA_EXP_REGION11_NUM_SEGMENTS", 28, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmCM0_CM_RGAM_RAMA_REGION_12_13[] = {
	 { "CM_RGAM_RAMA_EXP_REGION12_LUT_OFFSET", 0, 8, &umr_bitfield_default },
	 { "CM_RGAM_RAMA_EXP_REGION12_NUM_SEGMENTS", 12, 14, &umr_bitfield_default },
	 { "CM_RGAM_RAMA_EXP_REGION13_LUT_OFFSET", 16, 24, &umr_bitfield_default },
	 { "CM_RGAM_RAMA_EXP_REGION13_NUM_SEGMENTS", 28, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmCM0_CM_RGAM_RAMA_REGION_14_15[] = {
	 { "CM_RGAM_RAMA_EXP_REGION14_LUT_OFFSET", 0, 8, &umr_bitfield_default },
	 { "CM_RGAM_RAMA_EXP_REGION14_NUM_SEGMENTS", 12, 14, &umr_bitfield_default },
	 { "CM_RGAM_RAMA_EXP_REGION15_LUT_OFFSET", 16, 24, &umr_bitfield_default },
	 { "CM_RGAM_RAMA_EXP_REGION15_NUM_SEGMENTS", 28, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmCM0_CM_RGAM_RAMA_REGION_16_17[] = {
	 { "CM_RGAM_RAMA_EXP_REGION16_LUT_OFFSET", 0, 8, &umr_bitfield_default },
	 { "CM_RGAM_RAMA_EXP_REGION16_NUM_SEGMENTS", 12, 14, &umr_bitfield_default },
	 { "CM_RGAM_RAMA_EXP_REGION17_LUT_OFFSET", 16, 24, &umr_bitfield_default },
	 { "CM_RGAM_RAMA_EXP_REGION17_NUM_SEGMENTS", 28, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmCM0_CM_RGAM_RAMA_REGION_18_19[] = {
	 { "CM_RGAM_RAMA_EXP_REGION18_LUT_OFFSET", 0, 8, &umr_bitfield_default },
	 { "CM_RGAM_RAMA_EXP_REGION18_NUM_SEGMENTS", 12, 14, &umr_bitfield_default },
	 { "CM_RGAM_RAMA_EXP_REGION19_LUT_OFFSET", 16, 24, &umr_bitfield_default },
	 { "CM_RGAM_RAMA_EXP_REGION19_NUM_SEGMENTS", 28, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmCM0_CM_RGAM_RAMA_REGION_20_21[] = {
	 { "CM_RGAM_RAMA_EXP_REGION20_LUT_OFFSET", 0, 8, &umr_bitfield_default },
	 { "CM_RGAM_RAMA_EXP_REGION20_NUM_SEGMENTS", 12, 14, &umr_bitfield_default },
	 { "CM_RGAM_RAMA_EXP_REGION21_LUT_OFFSET", 16, 24, &umr_bitfield_default },
	 { "CM_RGAM_RAMA_EXP_REGION21_NUM_SEGMENTS", 28, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmCM0_CM_RGAM_RAMA_REGION_22_23[] = {
	 { "CM_RGAM_RAMA_EXP_REGION22_LUT_OFFSET", 0, 8, &umr_bitfield_default },
	 { "CM_RGAM_RAMA_EXP_REGION22_NUM_SEGMENTS", 12, 14, &umr_bitfield_default },
	 { "CM_RGAM_RAMA_EXP_REGION23_LUT_OFFSET", 16, 24, &umr_bitfield_default },
	 { "CM_RGAM_RAMA_EXP_REGION23_NUM_SEGMENTS", 28, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmCM0_CM_RGAM_RAMA_REGION_24_25[] = {
	 { "CM_RGAM_RAMA_EXP_REGION24_LUT_OFFSET", 0, 8, &umr_bitfield_default },
	 { "CM_RGAM_RAMA_EXP_REGION24_NUM_SEGMENTS", 12, 14, &umr_bitfield_default },
	 { "CM_RGAM_RAMA_EXP_REGION25_LUT_OFFSET", 16, 24, &umr_bitfield_default },
	 { "CM_RGAM_RAMA_EXP_REGION25_NUM_SEGMENTS", 28, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmCM0_CM_RGAM_RAMA_REGION_26_27[] = {
	 { "CM_RGAM_RAMA_EXP_REGION26_LUT_OFFSET", 0, 8, &umr_bitfield_default },
	 { "CM_RGAM_RAMA_EXP_REGION26_NUM_SEGMENTS", 12, 14, &umr_bitfield_default },
	 { "CM_RGAM_RAMA_EXP_REGION27_LUT_OFFSET", 16, 24, &umr_bitfield_default },
	 { "CM_RGAM_RAMA_EXP_REGION27_NUM_SEGMENTS", 28, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmCM0_CM_RGAM_RAMA_REGION_28_29[] = {
	 { "CM_RGAM_RAMA_EXP_REGION28_LUT_OFFSET", 0, 8, &umr_bitfield_default },
	 { "CM_RGAM_RAMA_EXP_REGION28_NUM_SEGMENTS", 12, 14, &umr_bitfield_default },
	 { "CM_RGAM_RAMA_EXP_REGION29_LUT_OFFSET", 16, 24, &umr_bitfield_default },
	 { "CM_RGAM_RAMA_EXP_REGION29_NUM_SEGMENTS", 28, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmCM0_CM_RGAM_RAMA_REGION_30_31[] = {
	 { "CM_RGAM_RAMA_EXP_REGION30_LUT_OFFSET", 0, 8, &umr_bitfield_default },
	 { "CM_RGAM_RAMA_EXP_REGION30_NUM_SEGMENTS", 12, 14, &umr_bitfield_default },
	 { "CM_RGAM_RAMA_EXP_REGION31_LUT_OFFSET", 16, 24, &umr_bitfield_default },
	 { "CM_RGAM_RAMA_EXP_REGION31_NUM_SEGMENTS", 28, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmCM0_CM_RGAM_RAMA_REGION_32_33[] = {
	 { "CM_RGAM_RAMA_EXP_REGION32_LUT_OFFSET", 0, 8, &umr_bitfield_default },
	 { "CM_RGAM_RAMA_EXP_REGION32_NUM_SEGMENTS", 12, 14, &umr_bitfield_default },
	 { "CM_RGAM_RAMA_EXP_REGION33_LUT_OFFSET", 16, 24, &umr_bitfield_default },
	 { "CM_RGAM_RAMA_EXP_REGION33_NUM_SEGMENTS", 28, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmCM0_CM_RGAM_RAMB_START_CNTL_B[] = {
	 { "CM_RGAM_RAMB_EXP_REGION_START_B", 0, 17, &umr_bitfield_default },
	 { "CM_RGAM_RAMB_EXP_REGION_START_SEGMENT_B", 20, 26, &umr_bitfield_default },
};
static struct umr_bitfield mmCM0_CM_RGAM_RAMB_START_CNTL_G[] = {
	 { "CM_RGAM_RAMB_EXP_REGION_START_G", 0, 17, &umr_bitfield_default },
	 { "CM_RGAM_RAMB_EXP_REGION_START_SEGMENT_G", 20, 26, &umr_bitfield_default },
};
static struct umr_bitfield mmCM0_CM_RGAM_RAMB_START_CNTL_R[] = {
	 { "CM_RGAM_RAMB_EXP_REGION_START_R", 0, 17, &umr_bitfield_default },
	 { "CM_RGAM_RAMB_EXP_REGION_START_SEGMENT_R", 20, 26, &umr_bitfield_default },
};
static struct umr_bitfield mmCM0_CM_RGAM_RAMB_SLOPE_CNTL_B[] = {
	 { "CM_RGAM_RAMB_EXP_REGION_LINEAR_SLOPE_B", 0, 17, &umr_bitfield_default },
};
static struct umr_bitfield mmCM0_CM_RGAM_RAMB_SLOPE_CNTL_G[] = {
	 { "CM_RGAM_RAMB_EXP_REGION_LINEAR_SLOPE_G", 0, 17, &umr_bitfield_default },
};
static struct umr_bitfield mmCM0_CM_RGAM_RAMB_SLOPE_CNTL_R[] = {
	 { "CM_RGAM_RAMB_EXP_REGION_LINEAR_SLOPE_R", 0, 17, &umr_bitfield_default },
};
static struct umr_bitfield mmCM0_CM_RGAM_RAMB_END_CNTL1_B[] = {
	 { "CM_RGAM_RAMB_EXP_REGION_END_B", 0, 15, &umr_bitfield_default },
};
static struct umr_bitfield mmCM0_CM_RGAM_RAMB_END_CNTL2_B[] = {
	 { "CM_RGAM_RAMB_EXP_REGION_END_SLOPE_B", 0, 15, &umr_bitfield_default },
	 { "CM_RGAM_RAMB_EXP_REGION_END_BASE_B", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmCM0_CM_RGAM_RAMB_END_CNTL1_G[] = {
	 { "CM_RGAM_RAMB_EXP_REGION_END_G", 0, 15, &umr_bitfield_default },
};
static struct umr_bitfield mmCM0_CM_RGAM_RAMB_END_CNTL2_G[] = {
	 { "CM_RGAM_RAMB_EXP_REGION_END_SLOPE_G", 0, 15, &umr_bitfield_default },
	 { "CM_RGAM_RAMB_EXP_REGION_END_BASE_G", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmCM0_CM_RGAM_RAMB_END_CNTL1_R[] = {
	 { "CM_RGAM_RAMB_EXP_REGION_END_R", 0, 15, &umr_bitfield_default },
};
static struct umr_bitfield mmCM0_CM_RGAM_RAMB_END_CNTL2_R[] = {
	 { "CM_RGAM_RAMB_EXP_REGION_END_SLOPE_R", 0, 15, &umr_bitfield_default },
	 { "CM_RGAM_RAMB_EXP_REGION_END_BASE_R", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmCM0_CM_RGAM_RAMB_REGION_0_1[] = {
	 { "CM_RGAM_RAMB_EXP_REGION0_LUT_OFFSET", 0, 8, &umr_bitfield_default },
	 { "CM_RGAM_RAMB_EXP_REGION0_NUM_SEGMENTS", 12, 14, &umr_bitfield_default },
	 { "CM_RGAM_RAMB_EXP_REGION1_LUT_OFFSET", 16, 24, &umr_bitfield_default },
	 { "CM_RGAM_RAMB_EXP_REGION1_NUM_SEGMENTS", 28, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmCM0_CM_RGAM_RAMB_REGION_2_3[] = {
	 { "CM_RGAM_RAMB_EXP_REGION2_LUT_OFFSET", 0, 8, &umr_bitfield_default },
	 { "CM_RGAM_RAMB_EXP_REGION2_NUM_SEGMENTS", 12, 14, &umr_bitfield_default },
	 { "CM_RGAM_RAMB_EXP_REGION3_LUT_OFFSET", 16, 24, &umr_bitfield_default },
	 { "CM_RGAM_RAMB_EXP_REGION3_NUM_SEGMENTS", 28, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmCM0_CM_RGAM_RAMB_REGION_4_5[] = {
	 { "CM_RGAM_RAMB_EXP_REGION4_LUT_OFFSET", 0, 8, &umr_bitfield_default },
	 { "CM_RGAM_RAMB_EXP_REGION4_NUM_SEGMENTS", 12, 14, &umr_bitfield_default },
	 { "CM_RGAM_RAMB_EXP_REGION5_LUT_OFFSET", 16, 24, &umr_bitfield_default },
	 { "CM_RGAM_RAMB_EXP_REGION5_NUM_SEGMENTS", 28, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmCM0_CM_RGAM_RAMB_REGION_6_7[] = {
	 { "CM_RGAM_RAMB_EXP_REGION6_LUT_OFFSET", 0, 8, &umr_bitfield_default },
	 { "CM_RGAM_RAMB_EXP_REGION6_NUM_SEGMENTS", 12, 14, &umr_bitfield_default },
	 { "CM_RGAM_RAMB_EXP_REGION7_LUT_OFFSET", 16, 24, &umr_bitfield_default },
	 { "CM_RGAM_RAMB_EXP_REGION7_NUM_SEGMENTS", 28, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmCM0_CM_RGAM_RAMB_REGION_8_9[] = {
	 { "CM_RGAM_RAMB_EXP_REGION8_LUT_OFFSET", 0, 8, &umr_bitfield_default },
	 { "CM_RGAM_RAMB_EXP_REGION8_NUM_SEGMENTS", 12, 14, &umr_bitfield_default },
	 { "CM_RGAM_RAMB_EXP_REGION9_LUT_OFFSET", 16, 24, &umr_bitfield_default },
	 { "CM_RGAM_RAMB_EXP_REGION9_NUM_SEGMENTS", 28, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmCM0_CM_RGAM_RAMB_REGION_10_11[] = {
	 { "CM_RGAM_RAMB_EXP_REGION10_LUT_OFFSET", 0, 8, &umr_bitfield_default },
	 { "CM_RGAM_RAMB_EXP_REGION10_NUM_SEGMENTS", 12, 14, &umr_bitfield_default },
	 { "CM_RGAM_RAMB_EXP_REGION11_LUT_OFFSET", 16, 24, &umr_bitfield_default },
	 { "CM_RGAM_RAMB_EXP_REGION11_NUM_SEGMENTS", 28, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmCM0_CM_RGAM_RAMB_REGION_12_13[] = {
	 { "CM_RGAM_RAMB_EXP_REGION12_LUT_OFFSET", 0, 8, &umr_bitfield_default },
	 { "CM_RGAM_RAMB_EXP_REGION12_NUM_SEGMENTS", 12, 14, &umr_bitfield_default },
	 { "CM_RGAM_RAMB_EXP_REGION13_LUT_OFFSET", 16, 24, &umr_bitfield_default },
	 { "CM_RGAM_RAMB_EXP_REGION13_NUM_SEGMENTS", 28, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmCM0_CM_RGAM_RAMB_REGION_14_15[] = {
	 { "CM_RGAM_RAMB_EXP_REGION14_LUT_OFFSET", 0, 8, &umr_bitfield_default },
	 { "CM_RGAM_RAMB_EXP_REGION14_NUM_SEGMENTS", 12, 14, &umr_bitfield_default },
	 { "CM_RGAM_RAMB_EXP_REGION15_LUT_OFFSET", 16, 24, &umr_bitfield_default },
	 { "CM_RGAM_RAMB_EXP_REGION15_NUM_SEGMENTS", 28, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmCM0_CM_RGAM_RAMB_REGION_16_17[] = {
	 { "CM_RGAM_RAMB_EXP_REGION16_LUT_OFFSET", 0, 8, &umr_bitfield_default },
	 { "CM_RGAM_RAMB_EXP_REGION16_NUM_SEGMENTS", 12, 14, &umr_bitfield_default },
	 { "CM_RGAM_RAMB_EXP_REGION17_LUT_OFFSET", 16, 24, &umr_bitfield_default },
	 { "CM_RGAM_RAMB_EXP_REGION17_NUM_SEGMENTS", 28, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmCM0_CM_RGAM_RAMB_REGION_18_19[] = {
	 { "CM_RGAM_RAMB_EXP_REGION18_LUT_OFFSET", 0, 8, &umr_bitfield_default },
	 { "CM_RGAM_RAMB_EXP_REGION18_NUM_SEGMENTS", 12, 14, &umr_bitfield_default },
	 { "CM_RGAM_RAMB_EXP_REGION19_LUT_OFFSET", 16, 24, &umr_bitfield_default },
	 { "CM_RGAM_RAMB_EXP_REGION19_NUM_SEGMENTS", 28, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmCM0_CM_RGAM_RAMB_REGION_20_21[] = {
	 { "CM_RGAM_RAMB_EXP_REGION20_LUT_OFFSET", 0, 8, &umr_bitfield_default },
	 { "CM_RGAM_RAMB_EXP_REGION20_NUM_SEGMENTS", 12, 14, &umr_bitfield_default },
	 { "CM_RGAM_RAMB_EXP_REGION21_LUT_OFFSET", 16, 24, &umr_bitfield_default },
	 { "CM_RGAM_RAMB_EXP_REGION21_NUM_SEGMENTS", 28, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmCM0_CM_RGAM_RAMB_REGION_22_23[] = {
	 { "CM_RGAM_RAMB_EXP_REGION22_LUT_OFFSET", 0, 8, &umr_bitfield_default },
	 { "CM_RGAM_RAMB_EXP_REGION22_NUM_SEGMENTS", 12, 14, &umr_bitfield_default },
	 { "CM_RGAM_RAMB_EXP_REGION23_LUT_OFFSET", 16, 24, &umr_bitfield_default },
	 { "CM_RGAM_RAMB_EXP_REGION23_NUM_SEGMENTS", 28, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmCM0_CM_RGAM_RAMB_REGION_24_25[] = {
	 { "CM_RGAM_RAMB_EXP_REGION24_LUT_OFFSET", 0, 8, &umr_bitfield_default },
	 { "CM_RGAM_RAMB_EXP_REGION24_NUM_SEGMENTS", 12, 14, &umr_bitfield_default },
	 { "CM_RGAM_RAMB_EXP_REGION25_LUT_OFFSET", 16, 24, &umr_bitfield_default },
	 { "CM_RGAM_RAMB_EXP_REGION25_NUM_SEGMENTS", 28, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmCM0_CM_RGAM_RAMB_REGION_26_27[] = {
	 { "CM_RGAM_RAMB_EXP_REGION26_LUT_OFFSET", 0, 8, &umr_bitfield_default },
	 { "CM_RGAM_RAMB_EXP_REGION26_NUM_SEGMENTS", 12, 14, &umr_bitfield_default },
	 { "CM_RGAM_RAMB_EXP_REGION27_LUT_OFFSET", 16, 24, &umr_bitfield_default },
	 { "CM_RGAM_RAMB_EXP_REGION27_NUM_SEGMENTS", 28, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmCM0_CM_RGAM_RAMB_REGION_28_29[] = {
	 { "CM_RGAM_RAMB_EXP_REGION28_LUT_OFFSET", 0, 8, &umr_bitfield_default },
	 { "CM_RGAM_RAMB_EXP_REGION28_NUM_SEGMENTS", 12, 14, &umr_bitfield_default },
	 { "CM_RGAM_RAMB_EXP_REGION29_LUT_OFFSET", 16, 24, &umr_bitfield_default },
	 { "CM_RGAM_RAMB_EXP_REGION29_NUM_SEGMENTS", 28, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmCM0_CM_RGAM_RAMB_REGION_30_31[] = {
	 { "CM_RGAM_RAMB_EXP_REGION30_LUT_OFFSET", 0, 8, &umr_bitfield_default },
	 { "CM_RGAM_RAMB_EXP_REGION30_NUM_SEGMENTS", 12, 14, &umr_bitfield_default },
	 { "CM_RGAM_RAMB_EXP_REGION31_LUT_OFFSET", 16, 24, &umr_bitfield_default },
	 { "CM_RGAM_RAMB_EXP_REGION31_NUM_SEGMENTS", 28, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmCM0_CM_RGAM_RAMB_REGION_32_33[] = {
	 { "CM_RGAM_RAMB_EXP_REGION32_LUT_OFFSET", 0, 8, &umr_bitfield_default },
	 { "CM_RGAM_RAMB_EXP_REGION32_NUM_SEGMENTS", 12, 14, &umr_bitfield_default },
	 { "CM_RGAM_RAMB_EXP_REGION33_LUT_OFFSET", 16, 24, &umr_bitfield_default },
	 { "CM_RGAM_RAMB_EXP_REGION33_NUM_SEGMENTS", 28, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmCM0_CM_HDR_MULT_COEF[] = {
	 { "CM_HDR_MULT_COEF", 0, 18, &umr_bitfield_default },
};
static struct umr_bitfield mmCM0_CM_RANGE_CLAMP_CONTROL_R[] = {
	 { "CM_RANGE_CLAMP_MAX_R", 0, 15, &umr_bitfield_default },
	 { "CM_RANGE_CLAMP_MIN_R", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmCM0_CM_RANGE_CLAMP_CONTROL_G[] = {
	 { "CM_RANGE_CLAMP_MAX_G", 0, 15, &umr_bitfield_default },
	 { "CM_RANGE_CLAMP_MIN_G", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmCM0_CM_RANGE_CLAMP_CONTROL_B[] = {
	 { "CM_RANGE_CLAMP_MAX_B", 0, 15, &umr_bitfield_default },
	 { "CM_RANGE_CLAMP_MIN_B", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmCM0_CM_DENORM_CONTROL[] = {
	 { "CM_DENORM_MODE", 0, 2, &umr_bitfield_default },
	 { "CM_DENORM_ROUND_CLAMP", 4, 4, &umr_bitfield_default },
};
static struct umr_bitfield mmCM0_CM_CMOUT_CONTROL[] = {
	 { "CM_CMOUT_ROUND_TRUNC_MODE", 0, 3, &umr_bitfield_default },
	 { "CM_CMOUT_SPATIAL_DITHER_EN", 4, 4, &umr_bitfield_default },
	 { "CM_CMOUT_SPATIAL_DITHER_MODE", 8, 9, &umr_bitfield_default },
	 { "CM_CMOUT_SPATIAL_DITHER_DEPTH", 12, 13, &umr_bitfield_default },
	 { "CM_CMOUT_FRAME_RANDOM_ENABLE", 16, 16, &umr_bitfield_default },
	 { "CM_CMOUT_RGB_RANDOM_EN", 20, 20, &umr_bitfield_default },
	 { "CM_CMOUT_HIGHPASS_RANDOM_ENABLE", 24, 24, &umr_bitfield_default },
};
static struct umr_bitfield mmCM0_CM_CMOUT_RANDOM_SEEDS[] = {
	 { "CM_CMOUT_RAND_R_SEED", 0, 7, &umr_bitfield_default },
	 { "CM_CMOUT_RAND_G_SEED", 8, 15, &umr_bitfield_default },
	 { "CM_CMOUT_RAND_B_SEED", 16, 23, &umr_bitfield_default },
};
static struct umr_bitfield mmCM0_CM_MEM_PWR_CTRL[] = {
	 { "SHARED_MEM_PWR_FORCE", 0, 1, &umr_bitfield_default },
	 { "SHARED_MEM_PWR_DIS", 2, 2, &umr_bitfield_default },
	 { "RGAM_MEM_PWR_FORCE", 4, 5, &umr_bitfield_default },
	 { "RGAM_MEM_PWR_DIS", 6, 6, &umr_bitfield_default },
};
static struct umr_bitfield mmCM0_CM_MEM_PWR_STATUS[] = {
	 { "SHARED_MEM_PWR_STATE", 0, 1, &umr_bitfield_default },
	 { "RGAM_MEM_PWR_STATE", 2, 3, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_PERFMON12_PERFCOUNTER_CNTL[] = {
	 { "PERFCOUNTER_EVENT_SEL", 0, 8, &umr_bitfield_default },
	 { "PERFCOUNTER_CVALUE_SEL", 9, 11, &umr_bitfield_default },
	 { "PERFCOUNTER_INC_MODE", 12, 14, &umr_bitfield_default },
	 { "PERFCOUNTER_HW_CNTL_SEL", 15, 15, &umr_bitfield_default },
	 { "PERFCOUNTER_RUNEN_MODE", 16, 16, &umr_bitfield_default },
	 { "PERFCOUNTER_CNTOFF_START_DIS", 22, 22, &umr_bitfield_default },
	 { "PERFCOUNTER_RESTART_EN", 23, 23, &umr_bitfield_default },
	 { "PERFCOUNTER_INT_EN", 24, 24, &umr_bitfield_default },
	 { "PERFCOUNTER_OFF_MASK", 25, 25, &umr_bitfield_default },
	 { "PERFCOUNTER_ACTIVE", 26, 26, &umr_bitfield_default },
	 { "PERFCOUNTER_CNTL_SEL", 29, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_PERFMON12_PERFCOUNTER_CNTL2[] = {
	 { "PERFCOUNTER_COUNTED_VALUE_TYPE", 0, 1, &umr_bitfield_default },
	 { "PERFCOUNTER_HW_STOP1_SEL", 2, 2, &umr_bitfield_default },
	 { "PERFCOUNTER_HW_STOP2_SEL", 3, 3, &umr_bitfield_default },
	 { "PERFCOUNTER_CNTOFF_SEL", 8, 13, &umr_bitfield_default },
	 { "PERFCOUNTER_CNTL2_SEL", 29, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_PERFMON12_PERFCOUNTER_STATE[] = {
	 { "PERFCOUNTER_CNT0_STATE", 0, 1, &umr_bitfield_default },
	 { "PERFCOUNTER_STATE_SEL0", 2, 2, &umr_bitfield_default },
	 { "PERFCOUNTER_CNT1_STATE", 4, 5, &umr_bitfield_default },
	 { "PERFCOUNTER_STATE_SEL1", 6, 6, &umr_bitfield_default },
	 { "PERFCOUNTER_CNT2_STATE", 8, 9, &umr_bitfield_default },
	 { "PERFCOUNTER_STATE_SEL2", 10, 10, &umr_bitfield_default },
	 { "PERFCOUNTER_CNT3_STATE", 12, 13, &umr_bitfield_default },
	 { "PERFCOUNTER_STATE_SEL3", 14, 14, &umr_bitfield_default },
	 { "PERFCOUNTER_CNT4_STATE", 16, 17, &umr_bitfield_default },
	 { "PERFCOUNTER_STATE_SEL4", 18, 18, &umr_bitfield_default },
	 { "PERFCOUNTER_CNT5_STATE", 20, 21, &umr_bitfield_default },
	 { "PERFCOUNTER_STATE_SEL5", 22, 22, &umr_bitfield_default },
	 { "PERFCOUNTER_CNT6_STATE", 24, 25, &umr_bitfield_default },
	 { "PERFCOUNTER_STATE_SEL6", 26, 26, &umr_bitfield_default },
	 { "PERFCOUNTER_CNT7_STATE", 28, 29, &umr_bitfield_default },
	 { "PERFCOUNTER_STATE_SEL7", 30, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_PERFMON12_PERFMON_CNTL[] = {
	 { "PERFMON_STATE", 0, 1, &umr_bitfield_default },
	 { "PERFMON_RPT_COUNT", 8, 27, &umr_bitfield_default },
	 { "PERFMON_CNTOFF_AND_OR", 28, 28, &umr_bitfield_default },
	 { "PERFMON_CNTOFF_INT_EN", 29, 29, &umr_bitfield_default },
	 { "PERFMON_CNTOFF_INT_STATUS", 30, 30, &umr_bitfield_default },
	 { "PERFMON_CNTOFF_INT_ACK", 31, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_PERFMON12_PERFMON_CNTL2[] = {
	 { "PERFMON_CNTOFF_INT_TYPE", 0, 0, &umr_bitfield_default },
	 { "PERFMON_CLK_ENABLE", 1, 1, &umr_bitfield_default },
	 { "PERFMON_RUN_ENABLE_START_SEL", 2, 9, &umr_bitfield_default },
	 { "PERFMON_RUN_ENABLE_STOP_SEL", 10, 17, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_PERFMON12_PERFMON_CVALUE_INT_MISC[] = {
	 { "PERFCOUNTER_INT0_STATUS", 0, 0, &umr_bitfield_default },
	 { "PERFCOUNTER_INT1_STATUS", 1, 1, &umr_bitfield_default },
	 { "PERFCOUNTER_INT2_STATUS", 2, 2, &umr_bitfield_default },
	 { "PERFCOUNTER_INT3_STATUS", 3, 3, &umr_bitfield_default },
	 { "PERFCOUNTER_INT4_STATUS", 4, 4, &umr_bitfield_default },
	 { "PERFCOUNTER_INT5_STATUS", 5, 5, &umr_bitfield_default },
	 { "PERFCOUNTER_INT6_STATUS", 6, 6, &umr_bitfield_default },
	 { "PERFCOUNTER_INT7_STATUS", 7, 7, &umr_bitfield_default },
	 { "PERFCOUNTER_INT0_ACK", 8, 8, &umr_bitfield_default },
	 { "PERFCOUNTER_INT1_ACK", 9, 9, &umr_bitfield_default },
	 { "PERFCOUNTER_INT2_ACK", 10, 10, &umr_bitfield_default },
	 { "PERFCOUNTER_INT3_ACK", 11, 11, &umr_bitfield_default },
	 { "PERFCOUNTER_INT4_ACK", 12, 12, &umr_bitfield_default },
	 { "PERFCOUNTER_INT5_ACK", 13, 13, &umr_bitfield_default },
	 { "PERFCOUNTER_INT6_ACK", 14, 14, &umr_bitfield_default },
	 { "PERFCOUNTER_INT7_ACK", 15, 15, &umr_bitfield_default },
	 { "PERFMON_CVALUE_HI", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_PERFMON12_PERFMON_CVALUE_LOW[] = {
	 { "PERFMON_CVALUE_LOW", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_PERFMON12_PERFMON_HI[] = {
	 { "PERFMON_HI", 0, 15, &umr_bitfield_default },
	 { "PERFMON_READ_SEL", 29, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_PERFMON12_PERFMON_LOW[] = {
	 { "PERFMON_LOW", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDPP_TOP1_DPP_CONTROL[] = {
	 { "DPP_CLOCK_ENABLE", 4, 4, &umr_bitfield_default },
	 { "DPPCLK_G_GATE_DISABLE", 8, 8, &umr_bitfield_default },
	 { "DPPCLK_G_DYN_GATE_DISABLE", 10, 10, &umr_bitfield_default },
	 { "DPPCLK_G_DSCL_GATE_DISABLE", 12, 12, &umr_bitfield_default },
	 { "DPPCLK_R_GATE_DISABLE", 16, 16, &umr_bitfield_default },
	 { "DISPCLK_R_GATE_DISABLE", 18, 18, &umr_bitfield_default },
	 { "DISPCLK_G_GATE_DISABLE", 20, 20, &umr_bitfield_default },
	 { "DPPCLK_RATE_CONTROL", 24, 24, &umr_bitfield_default },
	 { "DPP_TEST_CLK_SEL", 28, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmDPP_TOP1_DPP_SOFT_RESET[] = {
	 { "CNVC_SOFT_RESET", 0, 0, &umr_bitfield_default },
	 { "DSCL_SOFT_RESET", 4, 4, &umr_bitfield_default },
	 { "CM_SOFT_RESET", 8, 8, &umr_bitfield_default },
	 { "OBUF_SOFT_RESET", 12, 12, &umr_bitfield_default },
};
static struct umr_bitfield mmDPP_TOP1_DPP_CRC_VAL_R_G[] = {
	 { "DPP_CRC_R_CR", 0, 15, &umr_bitfield_default },
	 { "DPP_CRC_G_Y", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDPP_TOP1_DPP_CRC_VAL_B_A[] = {
	 { "DPP_CRC_B_CB", 0, 15, &umr_bitfield_default },
	 { "DPP_CRC_ALPHA", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDPP_TOP1_DPP_CRC_CTRL[] = {
	 { "DPP_CRC_EN", 0, 0, &umr_bitfield_default },
	 { "DPP_CRC_CONT_EN", 1, 1, &umr_bitfield_default },
	 { "DPP_CRC_ONE_SHOT_PENDING", 2, 2, &umr_bitfield_default },
	 { "DPP_CRC_420_COMP_SEL", 3, 3, &umr_bitfield_default },
	 { "DPP_CRC_SRC_SEL", 4, 5, &umr_bitfield_default },
	 { "DPP_CRC_STEREO_EN", 7, 7, &umr_bitfield_default },
	 { "DPP_CRC_STEREO_MODE", 8, 9, &umr_bitfield_default },
	 { "DPP_CRC_INTERLACE_MODE", 10, 11, &umr_bitfield_default },
	 { "DPP_CRC_PIX_FORMAT_SEL", 12, 14, &umr_bitfield_default },
	 { "DPP_CRC_CURSOR_FORMAT_SEL", 15, 15, &umr_bitfield_default },
	 { "DPP_CRC_MASK", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDPP_TOP1_HOST_READ_CONTROL[] = {
	 { "HOST_READ_RATE_CONTROL", 0, 7, &umr_bitfield_default },
};
static struct umr_bitfield mmCNVC_CFG1_CNVC_SURFACE_PIXEL_FORMAT[] = {
	 { "CNVC_SURFACE_PIXEL_FORMAT", 0, 6, &umr_bitfield_default },
};
static struct umr_bitfield mmCNVC_CFG1_FORMAT_CONTROL[] = {
	 { "FORMAT_EXPANSION_MODE", 0, 0, &umr_bitfield_default },
	 { "FORMAT_CNV16", 4, 4, &umr_bitfield_default },
	 { "ALPHA_EN", 8, 8, &umr_bitfield_default },
	 { "CNVC_BYPASS", 12, 12, &umr_bitfield_default },
	 { "OUTPUT_FP", 16, 16, &umr_bitfield_default },
	 { "CNVC_UPDATE_PENDING", 20, 20, &umr_bitfield_default },
};
static struct umr_bitfield mmCNVC_CFG1_FCNV_FP_SCALE_BIAS[] = {
	 { "FCNV_FP_SCALE", 0, 15, &umr_bitfield_default },
	 { "FCNV_FP_BIAS", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmCNVC_CFG1_DENORM_CONTROL[] = {
	 { "DENORM_SCALE", 0, 14, &umr_bitfield_default },
	 { "CLAMP_POSITIVE", 15, 15, &umr_bitfield_default },
	 { "DENORM_BIAS", 16, 30, &umr_bitfield_default },
	 { "DENORM_TRUNCATE", 31, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmCNVC_CFG1_COLOR_KEYER_CONTROL[] = {
	 { "COLOR_KEYER_EN", 0, 0, &umr_bitfield_default },
	 { "COLOR_KEYER_MODE", 4, 5, &umr_bitfield_default },
};
static struct umr_bitfield mmCNVC_CFG1_COLOR_KEYER_ALPHA[] = {
	 { "COLOR_KEYER_ALPHA_LOW", 0, 15, &umr_bitfield_default },
	 { "COLOR_KEYER_ALPHA_HIGH", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmCNVC_CFG1_COLOR_KEYER_RED[] = {
	 { "COLOR_KEYER_RED_LOW", 0, 15, &umr_bitfield_default },
	 { "COLOR_KEYER_RED_HIGH", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmCNVC_CFG1_COLOR_KEYER_GREEN[] = {
	 { "COLOR_KEYER_GREEN_LOW", 0, 15, &umr_bitfield_default },
	 { "COLOR_KEYER_GREEN_HIGH", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmCNVC_CFG1_COLOR_KEYER_BLUE[] = {
	 { "COLOR_KEYER_BLUE_LOW", 0, 15, &umr_bitfield_default },
	 { "COLOR_KEYER_BLUE_HIGH", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmCNVC_CUR1_CURSOR0_CONTROL[] = {
	 { "CUR0_ENABLE", 0, 0, &umr_bitfield_default },
	 { "CUR0_EXPANSION_MODE", 1, 1, &umr_bitfield_default },
	 { "CUR0_INVERT_MODE", 2, 2, &umr_bitfield_default },
	 { "CUR0_MODE", 4, 5, &umr_bitfield_default },
	 { "CUR0_UPDATE_PENDING", 6, 6, &umr_bitfield_default },
	 { "CUR0_MAX", 8, 19, &umr_bitfield_default },
	 { "CUR0_MIN", 20, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmCNVC_CUR1_CURSOR0_COLOR0[] = {
	 { "CUR0_COLOR0", 0, 23, &umr_bitfield_default },
};
static struct umr_bitfield mmCNVC_CUR1_CURSOR0_COLOR1[] = {
	 { "CUR0_COLOR1", 0, 23, &umr_bitfield_default },
};
static struct umr_bitfield mmCNVC_CUR1_CURSOR0_FP_SCALE_BIAS[] = {
	 { "CUR0_FP_SCALE", 0, 15, &umr_bitfield_default },
	 { "CUR0_FP_BIAS", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDSCL1_SCL_COEF_RAM_TAP_SELECT[] = {
	 { "SCL_COEF_RAM_TAP_PAIR_IDX", 0, 1, &umr_bitfield_default },
	 { "SCL_COEF_RAM_PHASE", 8, 13, &umr_bitfield_default },
	 { "SCL_COEF_RAM_FILTER_TYPE", 16, 18, &umr_bitfield_default },
};
static struct umr_bitfield mmDSCL1_SCL_COEF_RAM_TAP_DATA[] = {
	 { "SCL_COEF_RAM_EVEN_TAP_COEF", 0, 13, &umr_bitfield_default },
	 { "SCL_COEF_RAM_EVEN_TAP_COEF_EN", 15, 15, &umr_bitfield_default },
	 { "SCL_COEF_RAM_ODD_TAP_COEF", 16, 29, &umr_bitfield_default },
	 { "SCL_COEF_RAM_ODD_TAP_COEF_EN", 31, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDSCL1_SCL_MODE[] = {
	 { "DSCL_MODE", 0, 2, &umr_bitfield_default },
	 { "SCL_COEF_RAM_SELECT", 8, 8, &umr_bitfield_default },
	 { "SCL_COEF_RAM_SELECT_CURRENT", 12, 12, &umr_bitfield_default },
	 { "SCL_CHROMA_COEF_MODE", 16, 16, &umr_bitfield_default },
	 { "SCL_ALPHA_COEF_MODE", 20, 20, &umr_bitfield_default },
	 { "SCL_COEF_RAM_SELECT_RD", 24, 24, &umr_bitfield_default },
};
static struct umr_bitfield mmDSCL1_SCL_TAP_CONTROL[] = {
	 { "SCL_V_NUM_TAPS", 0, 2, &umr_bitfield_default },
	 { "SCL_H_NUM_TAPS", 4, 6, &umr_bitfield_default },
	 { "SCL_V_NUM_TAPS_C", 8, 10, &umr_bitfield_default },
	 { "SCL_H_NUM_TAPS_C", 12, 14, &umr_bitfield_default },
};
static struct umr_bitfield mmDSCL1_DSCL_CONTROL[] = {
	 { "SCL_BOUNDARY_MODE", 0, 0, &umr_bitfield_default },
};
static struct umr_bitfield mmDSCL1_DSCL_2TAP_CONTROL[] = {
	 { "SCL_H_2TAP_HARDCODE_COEF_EN", 0, 0, &umr_bitfield_default },
	 { "SCL_H_2TAP_SHARP_EN", 4, 4, &umr_bitfield_default },
	 { "SCL_H_2TAP_SHARP_FACTOR", 8, 10, &umr_bitfield_default },
	 { "SCL_V_2TAP_HARDCODE_COEF_EN", 16, 16, &umr_bitfield_default },
	 { "SCL_V_2TAP_SHARP_EN", 20, 20, &umr_bitfield_default },
	 { "SCL_V_2TAP_SHARP_FACTOR", 24, 26, &umr_bitfield_default },
};
static struct umr_bitfield mmDSCL1_SCL_MANUAL_REPLICATE_CONTROL[] = {
	 { "SCL_V_MANUAL_REPLICATE_FACTOR", 0, 3, &umr_bitfield_default },
	 { "SCL_H_MANUAL_REPLICATE_FACTOR", 8, 11, &umr_bitfield_default },
};
static struct umr_bitfield mmDSCL1_SCL_HORZ_FILTER_SCALE_RATIO[] = {
	 { "SCL_H_SCALE_RATIO", 0, 25, &umr_bitfield_default },
};
static struct umr_bitfield mmDSCL1_SCL_HORZ_FILTER_INIT[] = {
	 { "SCL_H_INIT_FRAC", 0, 23, &umr_bitfield_default },
	 { "SCL_H_INIT_INT", 24, 27, &umr_bitfield_default },
};
static struct umr_bitfield mmDSCL1_SCL_HORZ_FILTER_SCALE_RATIO_C[] = {
	 { "SCL_H_SCALE_RATIO_C", 0, 25, &umr_bitfield_default },
};
static struct umr_bitfield mmDSCL1_SCL_HORZ_FILTER_INIT_C[] = {
	 { "SCL_H_INIT_FRAC_C", 0, 23, &umr_bitfield_default },
	 { "SCL_H_INIT_INT_C", 24, 27, &umr_bitfield_default },
};
static struct umr_bitfield mmDSCL1_SCL_VERT_FILTER_SCALE_RATIO[] = {
	 { "SCL_V_SCALE_RATIO", 0, 25, &umr_bitfield_default },
};
static struct umr_bitfield mmDSCL1_SCL_VERT_FILTER_INIT[] = {
	 { "SCL_V_INIT_FRAC", 0, 23, &umr_bitfield_default },
	 { "SCL_V_INIT_INT", 24, 27, &umr_bitfield_default },
};
static struct umr_bitfield mmDSCL1_SCL_VERT_FILTER_INIT_BOT[] = {
	 { "SCL_V_INIT_FRAC_BOT", 0, 23, &umr_bitfield_default },
	 { "SCL_V_INIT_INT_BOT", 24, 27, &umr_bitfield_default },
};
static struct umr_bitfield mmDSCL1_SCL_VERT_FILTER_SCALE_RATIO_C[] = {
	 { "SCL_V_SCALE_RATIO_C", 0, 25, &umr_bitfield_default },
};
static struct umr_bitfield mmDSCL1_SCL_VERT_FILTER_INIT_C[] = {
	 { "SCL_V_INIT_FRAC_C", 0, 23, &umr_bitfield_default },
	 { "SCL_V_INIT_INT_C", 24, 27, &umr_bitfield_default },
};
static struct umr_bitfield mmDSCL1_SCL_VERT_FILTER_INIT_BOT_C[] = {
	 { "SCL_V_INIT_FRAC_BOT_C", 0, 23, &umr_bitfield_default },
	 { "SCL_V_INIT_INT_BOT_C", 24, 27, &umr_bitfield_default },
};
static struct umr_bitfield mmDSCL1_SCL_BLACK_OFFSET[] = {
	 { "SCL_BLACK_OFFSET_RGB_Y", 0, 15, &umr_bitfield_default },
	 { "SCL_BLACK_OFFSET_CBCR", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDSCL1_DSCL_UPDATE[] = {
	 { "SCL_UPDATE_PENDING", 0, 0, &umr_bitfield_default },
};
static struct umr_bitfield mmDSCL1_DSCL_AUTOCAL[] = {
	 { "AUTOCAL_MODE", 0, 1, &umr_bitfield_default },
	 { "AUTOCAL_NUM_PIPE", 8, 9, &umr_bitfield_default },
	 { "AUTOCAL_PIPE_ID", 12, 13, &umr_bitfield_default },
};
static struct umr_bitfield mmDSCL1_DSCL_EXT_OVERSCAN_LEFT_RIGHT[] = {
	 { "EXT_OVERSCAN_RIGHT", 0, 12, &umr_bitfield_default },
	 { "EXT_OVERSCAN_LEFT", 16, 28, &umr_bitfield_default },
};
static struct umr_bitfield mmDSCL1_DSCL_EXT_OVERSCAN_TOP_BOTTOM[] = {
	 { "EXT_OVERSCAN_BOTTOM", 0, 12, &umr_bitfield_default },
	 { "EXT_OVERSCAN_TOP", 16, 28, &umr_bitfield_default },
};
static struct umr_bitfield mmDSCL1_OTG_H_BLANK[] = {
	 { "OTG_H_BLANK_START", 0, 13, &umr_bitfield_default },
	 { "OTG_H_BLANK_END", 16, 29, &umr_bitfield_default },
};
static struct umr_bitfield mmDSCL1_OTG_V_BLANK[] = {
	 { "OTG_V_BLANK_START", 0, 13, &umr_bitfield_default },
	 { "OTG_V_BLANK_END", 16, 29, &umr_bitfield_default },
};
static struct umr_bitfield mmDSCL1_RECOUT_START[] = {
	 { "RECOUT_START_X", 0, 12, &umr_bitfield_default },
	 { "RECOUT_START_Y", 16, 28, &umr_bitfield_default },
};
static struct umr_bitfield mmDSCL1_RECOUT_SIZE[] = {
	 { "RECOUT_WIDTH", 0, 13, &umr_bitfield_default },
	 { "RECOUT_HEIGHT", 16, 29, &umr_bitfield_default },
};
static struct umr_bitfield mmDSCL1_MPC_SIZE[] = {
	 { "MPC_WIDTH", 0, 13, &umr_bitfield_default },
	 { "MPC_HEIGHT", 16, 29, &umr_bitfield_default },
};
static struct umr_bitfield mmDSCL1_LB_DATA_FORMAT[] = {
	 { "PIXEL_DEPTH", 0, 1, &umr_bitfield_default },
	 { "PIXEL_EXPAN_MODE", 8, 8, &umr_bitfield_default },
	 { "PIXEL_REDUCE_MODE", 12, 12, &umr_bitfield_default },
	 { "DYNAMIC_PIXEL_DEPTH", 16, 16, &umr_bitfield_default },
	 { "DITHER_EN", 20, 20, &umr_bitfield_default },
	 { "INTERLEAVE_EN", 24, 24, &umr_bitfield_default },
	 { "ALPHA_EN", 31, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDSCL1_LB_MEMORY_CTRL[] = {
	 { "MEMORY_CONFIG", 0, 1, &umr_bitfield_default },
	 { "LB_MAX_PARTITIONS", 8, 13, &umr_bitfield_default },
	 { "LB_NUM_PARTITIONS", 16, 22, &umr_bitfield_default },
	 { "LB_NUM_PARTITIONS_C", 24, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmDSCL1_LB_V_COUNTER[] = {
	 { "V_COUNTER", 0, 12, &umr_bitfield_default },
	 { "V_COUNTER_C", 16, 28, &umr_bitfield_default },
};
static struct umr_bitfield mmDSCL1_DSCL_MEM_PWR_CTRL[] = {
	 { "LUT_MEM_PWR_FORCE", 0, 1, &umr_bitfield_default },
	 { "LUT_MEM_PWR_DIS", 2, 2, &umr_bitfield_default },
	 { "LB_G1_MEM_PWR_FORCE", 4, 5, &umr_bitfield_default },
	 { "LB_G1_MEM_PWR_DIS", 6, 6, &umr_bitfield_default },
	 { "LB_G2_MEM_PWR_FORCE", 8, 9, &umr_bitfield_default },
	 { "LB_G2_MEM_PWR_DIS", 10, 10, &umr_bitfield_default },
	 { "LB_G3_MEM_PWR_FORCE", 12, 13, &umr_bitfield_default },
	 { "LB_G3_MEM_PWR_DIS", 14, 14, &umr_bitfield_default },
	 { "LB_G4_MEM_PWR_FORCE", 16, 17, &umr_bitfield_default },
	 { "LB_G4_MEM_PWR_DIS", 18, 18, &umr_bitfield_default },
	 { "LB_G5_MEM_PWR_FORCE", 20, 21, &umr_bitfield_default },
	 { "LB_G5_MEM_PWR_DIS", 22, 22, &umr_bitfield_default },
	 { "LB_G6_MEM_PWR_FORCE", 24, 25, &umr_bitfield_default },
	 { "LB_G6_MEM_PWR_DIS", 26, 26, &umr_bitfield_default },
};
static struct umr_bitfield mmDSCL1_DSCL_MEM_PWR_STATUS[] = {
	 { "LUT_MEM_PWR_STATE", 0, 1, &umr_bitfield_default },
	 { "LB_G1_MEM_PWR_STATE", 2, 3, &umr_bitfield_default },
	 { "LB_G2_MEM_PWR_STATE", 4, 5, &umr_bitfield_default },
	 { "LB_G3_MEM_PWR_STATE", 6, 7, &umr_bitfield_default },
	 { "LB_G4_MEM_PWR_STATE", 8, 9, &umr_bitfield_default },
	 { "LB_G5_MEM_PWR_STATE", 10, 11, &umr_bitfield_default },
	 { "LB_G6_MEM_PWR_STATE", 12, 13, &umr_bitfield_default },
};
static struct umr_bitfield mmDSCL1_OBUF_CONTROL[] = {
	 { "OBUF_BYPASS", 0, 0, &umr_bitfield_default },
	 { "OBUF_USE_FULL_BUFFER", 4, 4, &umr_bitfield_default },
	 { "OBUF_H_2X_UPSCALE_EN", 8, 8, &umr_bitfield_default },
	 { "OBUF_IS_HALF_RECOUT_WIDTH", 12, 12, &umr_bitfield_default },
	 { "OBUF_H_2X_COEF_PHASE0_SEL", 16, 16, &umr_bitfield_default },
	 { "OBUF_H_2X_COEF_PHASE1_SEL", 24, 24, &umr_bitfield_default },
	 { "OBUF_OUT_HOLD_CNT", 28, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDSCL1_OBUF_MEM_PWR_CTRL[] = {
	 { "OBUF_MEM_PWR_FORCE", 0, 1, &umr_bitfield_default },
	 { "OBUF_MEM_PWR_DIS", 2, 2, &umr_bitfield_default },
	 { "OBUF_MEM_PWR_STATE", 16, 17, &umr_bitfield_default },
};
static struct umr_bitfield mmCM1_CM_CONTROL[] = {
	 { "CM_BYPASS_EN", 0, 0, &umr_bitfield_default },
	 { "CM_UPDATE_PENDING", 8, 8, &umr_bitfield_default },
};
static struct umr_bitfield mmCM1_CM_COMA_C11_C12[] = {
	 { "CM_COMA_C11", 0, 15, &umr_bitfield_default },
	 { "CM_COMA_C12", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmCM1_CM_COMA_C13_C14[] = {
	 { "CM_COMA_C13", 0, 15, &umr_bitfield_default },
	 { "CM_COMA_C14", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmCM1_CM_COMA_C21_C22[] = {
	 { "CM_COMA_C21", 0, 15, &umr_bitfield_default },
	 { "CM_COMA_C22", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmCM1_CM_COMA_C23_C24[] = {
	 { "CM_COMA_C23", 0, 15, &umr_bitfield_default },
	 { "CM_COMA_C24", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmCM1_CM_COMA_C31_C32[] = {
	 { "CM_COMA_C31", 0, 15, &umr_bitfield_default },
	 { "CM_COMA_C32", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmCM1_CM_COMA_C33_C34[] = {
	 { "CM_COMA_C33", 0, 15, &umr_bitfield_default },
	 { "CM_COMA_C34", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmCM1_CM_COMB_C11_C12[] = {
	 { "CM_COMB_C11", 0, 15, &umr_bitfield_default },
	 { "CM_COMB_C12", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmCM1_CM_COMB_C13_C14[] = {
	 { "CM_COMB_C13", 0, 15, &umr_bitfield_default },
	 { "CM_COMB_C14", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmCM1_CM_COMB_C21_C22[] = {
	 { "CM_COMB_C21", 0, 15, &umr_bitfield_default },
	 { "CM_COMB_C22", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmCM1_CM_COMB_C23_C24[] = {
	 { "CM_COMB_C23", 0, 15, &umr_bitfield_default },
	 { "CM_COMB_C24", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmCM1_CM_COMB_C31_C32[] = {
	 { "CM_COMB_C31", 0, 15, &umr_bitfield_default },
	 { "CM_COMB_C32", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmCM1_CM_COMB_C33_C34[] = {
	 { "CM_COMB_C33", 0, 15, &umr_bitfield_default },
	 { "CM_COMB_C34", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmCM1_CM_IGAM_CONTROL[] = {
	 { "CM_IGAM_LUT_MODE", 0, 1, &umr_bitfield_default },
	 { "CM_IGAM_LUT_DATA_SIGNED_EN_B", 2, 2, &umr_bitfield_default },
	 { "CM_IGAM_LUT_DATA_SIGNED_EN_G", 3, 3, &umr_bitfield_default },
	 { "CM_IGAM_LUT_DATA_SIGNED_EN_R", 4, 4, &umr_bitfield_default },
	 { "CM_IGAM_LUT_INC_B", 5, 8, &umr_bitfield_default },
	 { "CM_IGAM_LUT_INC_G", 9, 12, &umr_bitfield_default },
	 { "CM_IGAM_LUT_INC_R", 13, 16, &umr_bitfield_default },
	 { "CM_IGAM_LUT_FORMAT_B", 17, 18, &umr_bitfield_default },
	 { "CM_IGAM_LUT_FORMAT_G", 19, 20, &umr_bitfield_default },
	 { "CM_IGAM_LUT_FORMAT_R", 21, 22, &umr_bitfield_default },
	 { "CM_IGAM_LUT_B_FLOAT_POINT_EN", 23, 23, &umr_bitfield_default },
	 { "CM_IGAM_LUT_G_FLOAT_POINT_EN", 24, 24, &umr_bitfield_default },
	 { "CM_IGAM_LUT_R_FLOAT_POINT_EN", 25, 25, &umr_bitfield_default },
	 { "CM_IGAM_INPUT_FORMAT", 26, 27, &umr_bitfield_default },
};
static struct umr_bitfield mmCM1_CM_IGAM_LUT_RW_CONTROL[] = {
	 { "CM_IGAM_LUT_RW_MODE", 0, 0, &umr_bitfield_default },
	 { "CM_IGAM_LUT_WRITE_EN_MASK", 4, 6, &umr_bitfield_default },
	 { "CM_IGAM_LUT_SEL", 8, 8, &umr_bitfield_default },
	 { "CM_IGAM_LUT_HOST_EN", 12, 12, &umr_bitfield_default },
	 { "CM_IGAM_DGAM_CONFIG_STATUS", 16, 19, &umr_bitfield_default },
};
static struct umr_bitfield mmCM1_CM_IGAM_LUT_RW_INDEX[] = {
	 { "CM_IGAM_LUT_RW_INDEX", 0, 7, &umr_bitfield_default },
};
static struct umr_bitfield mmCM1_CM_IGAM_LUT_SEQ_COLOR[] = {
	 { "CM_IGAM_LUT_SEQ_COLOR", 0, 15, &umr_bitfield_default },
};
static struct umr_bitfield mmCM1_CM_IGAM_LUT_30_COLOR[] = {
	 { "CM_IGAM_LUT_10_BLUE", 0, 9, &umr_bitfield_default },
	 { "CM_IGAM_LUT_10_GREEN", 10, 19, &umr_bitfield_default },
	 { "CM_IGAM_LUT_10_RED", 20, 29, &umr_bitfield_default },
};
static struct umr_bitfield mmCM1_CM_IGAM_LUT_PWL_DATA[] = {
	 { "CM_IGAM_LUT_PWL_BASE", 0, 15, &umr_bitfield_default },
	 { "CM_IGAM_LUT_PWL_DELTA", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmCM1_CM_IGAM_LUT_AUTOFILL[] = {
	 { "CM_IGAM_LUT_AUTOFILL", 0, 0, &umr_bitfield_default },
	 { "CM_IGAM_LUT_AUTOFILL_DONE", 4, 4, &umr_bitfield_default },
};
static struct umr_bitfield mmCM1_CM_IGAM_LUT_BW_OFFSET_BLUE[] = {
	 { "CM_IGAM_LUT_BLACK_OFFSET_BLUE", 0, 15, &umr_bitfield_default },
	 { "CM_IGAM_LUT_WHITE_OFFSET_BLUE", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmCM1_CM_IGAM_LUT_BW_OFFSET_GREEN[] = {
	 { "CM_IGAM_LUT_BLACK_OFFSET_GREEN", 0, 15, &umr_bitfield_default },
	 { "CM_IGAM_LUT_WHITE_OFFSET_GREEN", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmCM1_CM_IGAM_LUT_BW_OFFSET_RED[] = {
	 { "CM_IGAM_LUT_BLACK_OFFSET_RED", 0, 15, &umr_bitfield_default },
	 { "CM_IGAM_LUT_WHITE_OFFSET_RED", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmCM1_CM_ICSC_CONTROL[] = {
	 { "CM_ICSC_MODE", 0, 1, &umr_bitfield_default },
};
static struct umr_bitfield mmCM1_CM_ICSC_C11_C12[] = {
	 { "CM_ICSC_C11", 0, 15, &umr_bitfield_default },
	 { "CM_ICSC_C12", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmCM1_CM_ICSC_C13_C14[] = {
	 { "CM_ICSC_C13", 0, 15, &umr_bitfield_default },
	 { "CM_ICSC_C14", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmCM1_CM_ICSC_C21_C22[] = {
	 { "CM_ICSC_C21", 0, 15, &umr_bitfield_default },
	 { "CM_ICSC_C22", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmCM1_CM_ICSC_C23_C24[] = {
	 { "CM_ICSC_C23", 0, 15, &umr_bitfield_default },
	 { "CM_ICSC_C24", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmCM1_CM_ICSC_C31_C32[] = {
	 { "CM_ICSC_C31", 0, 15, &umr_bitfield_default },
	 { "CM_ICSC_C32", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmCM1_CM_ICSC_C33_C34[] = {
	 { "CM_ICSC_C33", 0, 15, &umr_bitfield_default },
	 { "CM_ICSC_C34", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmCM1_CM_GAMUT_REMAP_CONTROL[] = {
	 { "CM_GAMUT_REMAP_MODE", 0, 1, &umr_bitfield_default },
};
static struct umr_bitfield mmCM1_CM_GAMUT_REMAP_C11_C12[] = {
	 { "CM_GAMUT_REMAP_C11", 0, 15, &umr_bitfield_default },
	 { "CM_GAMUT_REMAP_C12", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmCM1_CM_GAMUT_REMAP_C13_C14[] = {
	 { "CM_GAMUT_REMAP_C13", 0, 15, &umr_bitfield_default },
	 { "CM_GAMUT_REMAP_C14", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmCM1_CM_GAMUT_REMAP_C21_C22[] = {
	 { "CM_GAMUT_REMAP_C21", 0, 15, &umr_bitfield_default },
	 { "CM_GAMUT_REMAP_C22", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmCM1_CM_GAMUT_REMAP_C23_C24[] = {
	 { "CM_GAMUT_REMAP_C23", 0, 15, &umr_bitfield_default },
	 { "CM_GAMUT_REMAP_C24", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmCM1_CM_GAMUT_REMAP_C31_C32[] = {
	 { "CM_GAMUT_REMAP_C31", 0, 15, &umr_bitfield_default },
	 { "CM_GAMUT_REMAP_C32", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmCM1_CM_GAMUT_REMAP_C33_C34[] = {
	 { "CM_GAMUT_REMAP_C33", 0, 15, &umr_bitfield_default },
	 { "CM_GAMUT_REMAP_C34", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmCM1_CM_OCSC_CONTROL[] = {
	 { "CM_OCSC_MODE", 0, 2, &umr_bitfield_default },
};
static struct umr_bitfield mmCM1_CM_OCSC_C11_C12[] = {
	 { "CM_OCSC_C11", 0, 15, &umr_bitfield_default },
	 { "CM_OCSC_C12", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmCM1_CM_OCSC_C13_C14[] = {
	 { "CM_OCSC_C13", 0, 15, &umr_bitfield_default },
	 { "CM_OCSC_C14", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmCM1_CM_OCSC_C21_C22[] = {
	 { "CM_OCSC_C21", 0, 15, &umr_bitfield_default },
	 { "CM_OCSC_C22", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmCM1_CM_OCSC_C23_C24[] = {
	 { "CM_OCSC_C23", 0, 15, &umr_bitfield_default },
	 { "CM_OCSC_C24", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmCM1_CM_OCSC_C31_C32[] = {
	 { "CM_OCSC_C31", 0, 15, &umr_bitfield_default },
	 { "CM_OCSC_C32", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmCM1_CM_OCSC_C33_C34[] = {
	 { "CM_OCSC_C33", 0, 15, &umr_bitfield_default },
	 { "CM_OCSC_C34", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmCM1_CM_BNS_VALUES_R[] = {
	 { "CM_BNS_BIAS_R", 0, 15, &umr_bitfield_default },
	 { "CM_BNS_SCALE_R", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmCM1_CM_BNS_VALUES_G[] = {
	 { "CM_BNS_BIAS_G", 0, 15, &umr_bitfield_default },
	 { "CM_BNS_SCALE_G", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmCM1_CM_BNS_VALUES_B[] = {
	 { "CM_BNS_BIAS_B", 0, 15, &umr_bitfield_default },
	 { "CM_BNS_SCALE_B", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmCM1_CM_DGAM_CONTROL[] = {
	 { "CM_DGAM_LUT_MODE", 0, 2, &umr_bitfield_default },
};
static struct umr_bitfield mmCM1_CM_DGAM_LUT_INDEX[] = {
	 { "CM_DGAM_LUT_INDEX", 0, 8, &umr_bitfield_default },
};
static struct umr_bitfield mmCM1_CM_DGAM_LUT_DATA[] = {
	 { "CM_DGAM_LUT_DATA", 0, 18, &umr_bitfield_default },
};
static struct umr_bitfield mmCM1_CM_DGAM_LUT_WRITE_EN_MASK[] = {
	 { "CM_DGAM_LUT_WRITE_EN_MASK", 0, 2, &umr_bitfield_default },
	 { "CM_DGAM_LUT_WRITE_SEL", 4, 4, &umr_bitfield_default },
};
static struct umr_bitfield mmCM1_CM_DGAM_RAMA_START_CNTL_B[] = {
	 { "CM_DGAM_RAMA_EXP_REGION_START_B", 0, 17, &umr_bitfield_default },
	 { "CM_DGAM_RAMA_EXP_REGION_START_SEGMENT_B", 20, 26, &umr_bitfield_default },
};
static struct umr_bitfield mmCM1_CM_DGAM_RAMA_START_CNTL_G[] = {
	 { "CM_DGAM_RAMA_EXP_REGION_START_G", 0, 17, &umr_bitfield_default },
	 { "CM_DGAM_RAMA_EXP_REGION_START_SEGMENT_G", 20, 26, &umr_bitfield_default },
};
static struct umr_bitfield mmCM1_CM_DGAM_RAMA_START_CNTL_R[] = {
	 { "CM_DGAM_RAMA_EXP_REGION_START_R", 0, 17, &umr_bitfield_default },
	 { "CM_DGAM_RAMA_EXP_REGION_START_SEGMENT_R", 20, 26, &umr_bitfield_default },
};
static struct umr_bitfield mmCM1_CM_DGAM_RAMA_SLOPE_CNTL_B[] = {
	 { "CM_DGAM_RAMA_EXP_REGION_LINEAR_SLOPE_B", 0, 17, &umr_bitfield_default },
};
static struct umr_bitfield mmCM1_CM_DGAM_RAMA_SLOPE_CNTL_G[] = {
	 { "CM_DGAM_RAMA_EXP_REGION_LINEAR_SLOPE_G", 0, 17, &umr_bitfield_default },
};
static struct umr_bitfield mmCM1_CM_DGAM_RAMA_SLOPE_CNTL_R[] = {
	 { "CM_DGAM_RAMA_EXP_REGION_LINEAR_SLOPE_R", 0, 17, &umr_bitfield_default },
};
static struct umr_bitfield mmCM1_CM_DGAM_RAMA_END_CNTL1_B[] = {
	 { "CM_DGAM_RAMA_EXP_REGION_END_B", 0, 15, &umr_bitfield_default },
};
static struct umr_bitfield mmCM1_CM_DGAM_RAMA_END_CNTL2_B[] = {
	 { "CM_DGAM_RAMA_EXP_REGION_END_SLOPE_B", 0, 15, &umr_bitfield_default },
	 { "CM_DGAM_RAMA_EXP_REGION_END_BASE_B", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmCM1_CM_DGAM_RAMA_END_CNTL1_G[] = {
	 { "CM_DGAM_RAMA_EXP_REGION_END_G", 0, 15, &umr_bitfield_default },
};
static struct umr_bitfield mmCM1_CM_DGAM_RAMA_END_CNTL2_G[] = {
	 { "CM_DGAM_RAMA_EXP_REGION_END_SLOPE_G", 0, 15, &umr_bitfield_default },
	 { "CM_DGAM_RAMA_EXP_REGION_END_BASE_G", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmCM1_CM_DGAM_RAMA_END_CNTL1_R[] = {
	 { "CM_DGAM_RAMA_EXP_REGION_END_R", 0, 15, &umr_bitfield_default },
};
static struct umr_bitfield mmCM1_CM_DGAM_RAMA_END_CNTL2_R[] = {
	 { "CM_DGAM_RAMA_EXP_REGION_END_SLOPE_R", 0, 15, &umr_bitfield_default },
	 { "CM_DGAM_RAMA_EXP_REGION_END_BASE_R", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmCM1_CM_DGAM_RAMA_REGION_0_1[] = {
	 { "CM_DGAM_RAMA_EXP_REGION0_LUT_OFFSET", 0, 8, &umr_bitfield_default },
	 { "CM_DGAM_RAMA_EXP_REGION0_NUM_SEGMENTS", 12, 14, &umr_bitfield_default },
	 { "CM_DGAM_RAMA_EXP_REGION1_LUT_OFFSET", 16, 24, &umr_bitfield_default },
	 { "CM_DGAM_RAMA_EXP_REGION1_NUM_SEGMENTS", 28, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmCM1_CM_DGAM_RAMA_REGION_2_3[] = {
	 { "CM_DGAM_RAMA_EXP_REGION2_LUT_OFFSET", 0, 8, &umr_bitfield_default },
	 { "CM_DGAM_RAMA_EXP_REGION2_NUM_SEGMENTS", 12, 14, &umr_bitfield_default },
	 { "CM_DGAM_RAMA_EXP_REGION3_LUT_OFFSET", 16, 24, &umr_bitfield_default },
	 { "CM_DGAM_RAMA_EXP_REGION3_NUM_SEGMENTS", 28, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmCM1_CM_DGAM_RAMA_REGION_4_5[] = {
	 { "CM_DGAM_RAMA_EXP_REGION4_LUT_OFFSET", 0, 8, &umr_bitfield_default },
	 { "CM_DGAM_RAMA_EXP_REGION4_NUM_SEGMENTS", 12, 14, &umr_bitfield_default },
	 { "CM_DGAM_RAMA_EXP_REGION5_LUT_OFFSET", 16, 24, &umr_bitfield_default },
	 { "CM_DGAM_RAMA_EXP_REGION5_NUM_SEGMENTS", 28, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmCM1_CM_DGAM_RAMA_REGION_6_7[] = {
	 { "CM_DGAM_RAMA_EXP_REGION6_LUT_OFFSET", 0, 8, &umr_bitfield_default },
	 { "CM_DGAM_RAMA_EXP_REGION6_NUM_SEGMENTS", 12, 14, &umr_bitfield_default },
	 { "CM_DGAM_RAMA_EXP_REGION7_LUT_OFFSET", 16, 24, &umr_bitfield_default },
	 { "CM_DGAM_RAMA_EXP_REGION7_NUM_SEGMENTS", 28, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmCM1_CM_DGAM_RAMA_REGION_8_9[] = {
	 { "CM_DGAM_RAMA_EXP_REGION8_LUT_OFFSET", 0, 8, &umr_bitfield_default },
	 { "CM_DGAM_RAMA_EXP_REGION8_NUM_SEGMENTS", 12, 14, &umr_bitfield_default },
	 { "CM_DGAM_RAMA_EXP_REGION9_LUT_OFFSET", 16, 24, &umr_bitfield_default },
	 { "CM_DGAM_RAMA_EXP_REGION9_NUM_SEGMENTS", 28, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmCM1_CM_DGAM_RAMA_REGION_10_11[] = {
	 { "CM_DGAM_RAMA_EXP_REGION10_LUT_OFFSET", 0, 8, &umr_bitfield_default },
	 { "CM_DGAM_RAMA_EXP_REGION10_NUM_SEGMENTS", 12, 14, &umr_bitfield_default },
	 { "CM_DGAM_RAMA_EXP_REGION11_LUT_OFFSET", 16, 24, &umr_bitfield_default },
	 { "CM_DGAM_RAMA_EXP_REGION11_NUM_SEGMENTS", 28, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmCM1_CM_DGAM_RAMA_REGION_12_13[] = {
	 { "CM_DGAM_RAMA_EXP_REGION12_LUT_OFFSET", 0, 8, &umr_bitfield_default },
	 { "CM_DGAM_RAMA_EXP_REGION12_NUM_SEGMENTS", 12, 14, &umr_bitfield_default },
	 { "CM_DGAM_RAMA_EXP_REGION13_LUT_OFFSET", 16, 24, &umr_bitfield_default },
	 { "CM_DGAM_RAMA_EXP_REGION13_NUM_SEGMENTS", 28, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmCM1_CM_DGAM_RAMA_REGION_14_15[] = {
	 { "CM_DGAM_RAMA_EXP_REGION14_LUT_OFFSET", 0, 8, &umr_bitfield_default },
	 { "CM_DGAM_RAMA_EXP_REGION14_NUM_SEGMENTS", 12, 14, &umr_bitfield_default },
	 { "CM_DGAM_RAMA_EXP_REGION15_LUT_OFFSET", 16, 24, &umr_bitfield_default },
	 { "CM_DGAM_RAMA_EXP_REGION15_NUM_SEGMENTS", 28, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmCM1_CM_DGAM_RAMB_START_CNTL_B[] = {
	 { "CM_DGAM_RAMB_EXP_REGION_START_B", 0, 17, &umr_bitfield_default },
	 { "CM_DGAM_RAMB_EXP_REGION_START_SEGMENT_B", 20, 26, &umr_bitfield_default },
};
static struct umr_bitfield mmCM1_CM_DGAM_RAMB_START_CNTL_G[] = {
	 { "CM_DGAM_RAMB_EXP_REGION_START_G", 0, 17, &umr_bitfield_default },
	 { "CM_DGAM_RAMB_EXP_REGION_START_SEGMENT_G", 20, 26, &umr_bitfield_default },
};
static struct umr_bitfield mmCM1_CM_DGAM_RAMB_START_CNTL_R[] = {
	 { "CM_DGAM_RAMB_EXP_REGION_START_R", 0, 17, &umr_bitfield_default },
	 { "CM_DGAM_RAMB_EXP_REGION_START_SEGMENT_R", 20, 26, &umr_bitfield_default },
};
static struct umr_bitfield mmCM1_CM_DGAM_RAMB_SLOPE_CNTL_B[] = {
	 { "CM_DGAM_RAMB_EXP_REGION_LINEAR_SLOPE_B", 0, 17, &umr_bitfield_default },
};
static struct umr_bitfield mmCM1_CM_DGAM_RAMB_SLOPE_CNTL_G[] = {
	 { "CM_DGAM_RAMB_EXP_REGION_LINEAR_SLOPE_G", 0, 17, &umr_bitfield_default },
};
static struct umr_bitfield mmCM1_CM_DGAM_RAMB_SLOPE_CNTL_R[] = {
	 { "CM_DGAM_RAMB_EXP_REGION_LINEAR_SLOPE_R", 0, 17, &umr_bitfield_default },
};
static struct umr_bitfield mmCM1_CM_DGAM_RAMB_END_CNTL1_B[] = {
	 { "CM_DGAM_RAMB_EXP_REGION_END_B", 0, 15, &umr_bitfield_default },
};
static struct umr_bitfield mmCM1_CM_DGAM_RAMB_END_CNTL2_B[] = {
	 { "CM_DGAM_RAMB_EXP_REGION_END_SLOPE_B", 0, 15, &umr_bitfield_default },
	 { "CM_DGAM_RAMB_EXP_REGION_END_BASE_B", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmCM1_CM_DGAM_RAMB_END_CNTL1_G[] = {
	 { "CM_DGAM_RAMB_EXP_REGION_END_G", 0, 15, &umr_bitfield_default },
};
static struct umr_bitfield mmCM1_CM_DGAM_RAMB_END_CNTL2_G[] = {
	 { "CM_DGAM_RAMB_EXP_REGION_END_SLOPE_G", 0, 15, &umr_bitfield_default },
	 { "CM_DGAM_RAMB_EXP_REGION_END_BASE_G", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmCM1_CM_DGAM_RAMB_END_CNTL1_R[] = {
	 { "CM_DGAM_RAMB_EXP_REGION_END_R", 0, 15, &umr_bitfield_default },
};
static struct umr_bitfield mmCM1_CM_DGAM_RAMB_END_CNTL2_R[] = {
	 { "CM_DGAM_RAMB_EXP_REGION_END_SLOPE_R", 0, 15, &umr_bitfield_default },
	 { "CM_DGAM_RAMB_EXP_REGION_END_BASE_R", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmCM1_CM_DGAM_RAMB_REGION_0_1[] = {
	 { "CM_DGAM_RAMB_EXP_REGION0_LUT_OFFSET", 0, 8, &umr_bitfield_default },
	 { "CM_DGAM_RAMB_EXP_REGION0_NUM_SEGMENTS", 12, 14, &umr_bitfield_default },
	 { "CM_DGAM_RAMB_EXP_REGION1_LUT_OFFSET", 16, 24, &umr_bitfield_default },
	 { "CM_DGAM_RAMB_EXP_REGION1_NUM_SEGMENTS", 28, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmCM1_CM_DGAM_RAMB_REGION_2_3[] = {
	 { "CM_DGAM_RAMB_EXP_REGION2_LUT_OFFSET", 0, 8, &umr_bitfield_default },
	 { "CM_DGAM_RAMB_EXP_REGION2_NUM_SEGMENTS", 12, 14, &umr_bitfield_default },
	 { "CM_DGAM_RAMB_EXP_REGION3_LUT_OFFSET", 16, 24, &umr_bitfield_default },
	 { "CM_DGAM_RAMB_EXP_REGION3_NUM_SEGMENTS", 28, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmCM1_CM_DGAM_RAMB_REGION_4_5[] = {
	 { "CM_DGAM_RAMB_EXP_REGION4_LUT_OFFSET", 0, 8, &umr_bitfield_default },
	 { "CM_DGAM_RAMB_EXP_REGION4_NUM_SEGMENTS", 12, 14, &umr_bitfield_default },
	 { "CM_DGAM_RAMB_EXP_REGION5_LUT_OFFSET", 16, 24, &umr_bitfield_default },
	 { "CM_DGAM_RAMB_EXP_REGION5_NUM_SEGMENTS", 28, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmCM1_CM_DGAM_RAMB_REGION_6_7[] = {
	 { "CM_DGAM_RAMB_EXP_REGION6_LUT_OFFSET", 0, 8, &umr_bitfield_default },
	 { "CM_DGAM_RAMB_EXP_REGION6_NUM_SEGMENTS", 12, 14, &umr_bitfield_default },
	 { "CM_DGAM_RAMB_EXP_REGION7_LUT_OFFSET", 16, 24, &umr_bitfield_default },
	 { "CM_DGAM_RAMB_EXP_REGION7_NUM_SEGMENTS", 28, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmCM1_CM_DGAM_RAMB_REGION_8_9[] = {
	 { "CM_DGAM_RAMB_EXP_REGION8_LUT_OFFSET", 0, 8, &umr_bitfield_default },
	 { "CM_DGAM_RAMB_EXP_REGION8_NUM_SEGMENTS", 12, 14, &umr_bitfield_default },
	 { "CM_DGAM_RAMB_EXP_REGION9_LUT_OFFSET", 16, 24, &umr_bitfield_default },
	 { "CM_DGAM_RAMB_EXP_REGION9_NUM_SEGMENTS", 28, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmCM1_CM_DGAM_RAMB_REGION_10_11[] = {
	 { "CM_DGAM_RAMB_EXP_REGION10_LUT_OFFSET", 0, 8, &umr_bitfield_default },
	 { "CM_DGAM_RAMB_EXP_REGION10_NUM_SEGMENTS", 12, 14, &umr_bitfield_default },
	 { "CM_DGAM_RAMB_EXP_REGION11_LUT_OFFSET", 16, 24, &umr_bitfield_default },
	 { "CM_DGAM_RAMB_EXP_REGION11_NUM_SEGMENTS", 28, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmCM1_CM_DGAM_RAMB_REGION_12_13[] = {
	 { "CM_DGAM_RAMB_EXP_REGION12_LUT_OFFSET", 0, 8, &umr_bitfield_default },
	 { "CM_DGAM_RAMB_EXP_REGION12_NUM_SEGMENTS", 12, 14, &umr_bitfield_default },
	 { "CM_DGAM_RAMB_EXP_REGION13_LUT_OFFSET", 16, 24, &umr_bitfield_default },
	 { "CM_DGAM_RAMB_EXP_REGION13_NUM_SEGMENTS", 28, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmCM1_CM_DGAM_RAMB_REGION_14_15[] = {
	 { "CM_DGAM_RAMB_EXP_REGION14_LUT_OFFSET", 0, 8, &umr_bitfield_default },
	 { "CM_DGAM_RAMB_EXP_REGION14_NUM_SEGMENTS", 12, 14, &umr_bitfield_default },
	 { "CM_DGAM_RAMB_EXP_REGION15_LUT_OFFSET", 16, 24, &umr_bitfield_default },
	 { "CM_DGAM_RAMB_EXP_REGION15_NUM_SEGMENTS", 28, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmCM1_CM_RGAM_CONTROL[] = {
	 { "CM_RGAM_LUT_MODE", 0, 2, &umr_bitfield_default },
};
static struct umr_bitfield mmCM1_CM_RGAM_LUT_INDEX[] = {
	 { "CM_RGAM_LUT_INDEX", 0, 8, &umr_bitfield_default },
};
static struct umr_bitfield mmCM1_CM_RGAM_LUT_DATA[] = {
	 { "CM_RGAM_LUT_DATA", 0, 18, &umr_bitfield_default },
};
static struct umr_bitfield mmCM1_CM_RGAM_LUT_WRITE_EN_MASK[] = {
	 { "CM_RGAM_LUT_WRITE_EN_MASK", 0, 2, &umr_bitfield_default },
	 { "CM_RGAM_LUT_WRITE_SEL", 4, 4, &umr_bitfield_default },
	 { "CM_RGAM_CONFIG_STATUS", 8, 10, &umr_bitfield_default },
};
static struct umr_bitfield mmCM1_CM_RGAM_RAMA_START_CNTL_B[] = {
	 { "CM_RGAM_RAMA_EXP_REGION_START_B", 0, 17, &umr_bitfield_default },
	 { "CM_RGAM_RAMA_EXP_REGION_START_SEGMENT_B", 20, 26, &umr_bitfield_default },
};
static struct umr_bitfield mmCM1_CM_RGAM_RAMA_START_CNTL_G[] = {
	 { "CM_RGAM_RAMA_EXP_REGION_START_G", 0, 17, &umr_bitfield_default },
	 { "CM_RGAM_RAMA_EXP_REGION_START_SEGMENT_G", 20, 26, &umr_bitfield_default },
};
static struct umr_bitfield mmCM1_CM_RGAM_RAMA_START_CNTL_R[] = {
	 { "CM_RGAM_RAMA_EXP_REGION_START_R", 0, 17, &umr_bitfield_default },
	 { "CM_RGAM_RAMA_EXP_REGION_START_SEGMENT_R", 20, 26, &umr_bitfield_default },
};
static struct umr_bitfield mmCM1_CM_RGAM_RAMA_SLOPE_CNTL_B[] = {
	 { "CM_RGAM_RAMA_EXP_REGION_LINEAR_SLOPE_B", 0, 17, &umr_bitfield_default },
};
static struct umr_bitfield mmCM1_CM_RGAM_RAMA_SLOPE_CNTL_G[] = {
	 { "CM_RGAM_RAMA_EXP_REGION_LINEAR_SLOPE_G", 0, 17, &umr_bitfield_default },
};
static struct umr_bitfield mmCM1_CM_RGAM_RAMA_SLOPE_CNTL_R[] = {
	 { "CM_RGAM_RAMA_EXP_REGION_LINEAR_SLOPE_R", 0, 17, &umr_bitfield_default },
};
static struct umr_bitfield mmCM1_CM_RGAM_RAMA_END_CNTL1_B[] = {
	 { "CM_RGAM_RAMA_EXP_REGION_END_B", 0, 15, &umr_bitfield_default },
};
static struct umr_bitfield mmCM1_CM_RGAM_RAMA_END_CNTL2_B[] = {
	 { "CM_RGAM_RAMA_EXP_REGION_END_SLOPE_B", 0, 15, &umr_bitfield_default },
	 { "CM_RGAM_RAMA_EXP_REGION_END_BASE_B", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmCM1_CM_RGAM_RAMA_END_CNTL1_G[] = {
	 { "CM_RGAM_RAMA_EXP_REGION_END_G", 0, 15, &umr_bitfield_default },
};
static struct umr_bitfield mmCM1_CM_RGAM_RAMA_END_CNTL2_G[] = {
	 { "CM_RGAM_RAMA_EXP_REGION_END_SLOPE_G", 0, 15, &umr_bitfield_default },
	 { "CM_RGAM_RAMA_EXP_REGION_END_BASE_G", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmCM1_CM_RGAM_RAMA_END_CNTL1_R[] = {
	 { "CM_RGAM_RAMA_EXP_REGION_END_R", 0, 15, &umr_bitfield_default },
};
static struct umr_bitfield mmCM1_CM_RGAM_RAMA_END_CNTL2_R[] = {
	 { "CM_RGAM_RAMA_EXP_REGION_END_SLOPE_R", 0, 15, &umr_bitfield_default },
	 { "CM_RGAM_RAMA_EXP_REGION_END_BASE_R", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmCM1_CM_RGAM_RAMA_REGION_0_1[] = {
	 { "CM_RGAM_RAMA_EXP_REGION0_LUT_OFFSET", 0, 8, &umr_bitfield_default },
	 { "CM_RGAM_RAMA_EXP_REGION0_NUM_SEGMENTS", 12, 14, &umr_bitfield_default },
	 { "CM_RGAM_RAMA_EXP_REGION1_LUT_OFFSET", 16, 24, &umr_bitfield_default },
	 { "CM_RGAM_RAMA_EXP_REGION1_NUM_SEGMENTS", 28, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmCM1_CM_RGAM_RAMA_REGION_2_3[] = {
	 { "CM_RGAM_RAMA_EXP_REGION2_LUT_OFFSET", 0, 8, &umr_bitfield_default },
	 { "CM_RGAM_RAMA_EXP_REGION2_NUM_SEGMENTS", 12, 14, &umr_bitfield_default },
	 { "CM_RGAM_RAMA_EXP_REGION3_LUT_OFFSET", 16, 24, &umr_bitfield_default },
	 { "CM_RGAM_RAMA_EXP_REGION3_NUM_SEGMENTS", 28, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmCM1_CM_RGAM_RAMA_REGION_4_5[] = {
	 { "CM_RGAM_RAMA_EXP_REGION4_LUT_OFFSET", 0, 8, &umr_bitfield_default },
	 { "CM_RGAM_RAMA_EXP_REGION4_NUM_SEGMENTS", 12, 14, &umr_bitfield_default },
	 { "CM_RGAM_RAMA_EXP_REGION5_LUT_OFFSET", 16, 24, &umr_bitfield_default },
	 { "CM_RGAM_RAMA_EXP_REGION5_NUM_SEGMENTS", 28, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmCM1_CM_RGAM_RAMA_REGION_6_7[] = {
	 { "CM_RGAM_RAMA_EXP_REGION6_LUT_OFFSET", 0, 8, &umr_bitfield_default },
	 { "CM_RGAM_RAMA_EXP_REGION6_NUM_SEGMENTS", 12, 14, &umr_bitfield_default },
	 { "CM_RGAM_RAMA_EXP_REGION7_LUT_OFFSET", 16, 24, &umr_bitfield_default },
	 { "CM_RGAM_RAMA_EXP_REGION7_NUM_SEGMENTS", 28, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmCM1_CM_RGAM_RAMA_REGION_8_9[] = {
	 { "CM_RGAM_RAMA_EXP_REGION8_LUT_OFFSET", 0, 8, &umr_bitfield_default },
	 { "CM_RGAM_RAMA_EXP_REGION8_NUM_SEGMENTS", 12, 14, &umr_bitfield_default },
	 { "CM_RGAM_RAMA_EXP_REGION9_LUT_OFFSET", 16, 24, &umr_bitfield_default },
	 { "CM_RGAM_RAMA_EXP_REGION9_NUM_SEGMENTS", 28, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmCM1_CM_RGAM_RAMA_REGION_10_11[] = {
	 { "CM_RGAM_RAMA_EXP_REGION10_LUT_OFFSET", 0, 8, &umr_bitfield_default },
	 { "CM_RGAM_RAMA_EXP_REGION10_NUM_SEGMENTS", 12, 14, &umr_bitfield_default },
	 { "CM_RGAM_RAMA_EXP_REGION11_LUT_OFFSET", 16, 24, &umr_bitfield_default },
	 { "CM_RGAM_RAMA_EXP_REGION11_NUM_SEGMENTS", 28, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmCM1_CM_RGAM_RAMA_REGION_12_13[] = {
	 { "CM_RGAM_RAMA_EXP_REGION12_LUT_OFFSET", 0, 8, &umr_bitfield_default },
	 { "CM_RGAM_RAMA_EXP_REGION12_NUM_SEGMENTS", 12, 14, &umr_bitfield_default },
	 { "CM_RGAM_RAMA_EXP_REGION13_LUT_OFFSET", 16, 24, &umr_bitfield_default },
	 { "CM_RGAM_RAMA_EXP_REGION13_NUM_SEGMENTS", 28, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmCM1_CM_RGAM_RAMA_REGION_14_15[] = {
	 { "CM_RGAM_RAMA_EXP_REGION14_LUT_OFFSET", 0, 8, &umr_bitfield_default },
	 { "CM_RGAM_RAMA_EXP_REGION14_NUM_SEGMENTS", 12, 14, &umr_bitfield_default },
	 { "CM_RGAM_RAMA_EXP_REGION15_LUT_OFFSET", 16, 24, &umr_bitfield_default },
	 { "CM_RGAM_RAMA_EXP_REGION15_NUM_SEGMENTS", 28, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmCM1_CM_RGAM_RAMA_REGION_16_17[] = {
	 { "CM_RGAM_RAMA_EXP_REGION16_LUT_OFFSET", 0, 8, &umr_bitfield_default },
	 { "CM_RGAM_RAMA_EXP_REGION16_NUM_SEGMENTS", 12, 14, &umr_bitfield_default },
	 { "CM_RGAM_RAMA_EXP_REGION17_LUT_OFFSET", 16, 24, &umr_bitfield_default },
	 { "CM_RGAM_RAMA_EXP_REGION17_NUM_SEGMENTS", 28, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmCM1_CM_RGAM_RAMA_REGION_18_19[] = {
	 { "CM_RGAM_RAMA_EXP_REGION18_LUT_OFFSET", 0, 8, &umr_bitfield_default },
	 { "CM_RGAM_RAMA_EXP_REGION18_NUM_SEGMENTS", 12, 14, &umr_bitfield_default },
	 { "CM_RGAM_RAMA_EXP_REGION19_LUT_OFFSET", 16, 24, &umr_bitfield_default },
	 { "CM_RGAM_RAMA_EXP_REGION19_NUM_SEGMENTS", 28, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmCM1_CM_RGAM_RAMA_REGION_20_21[] = {
	 { "CM_RGAM_RAMA_EXP_REGION20_LUT_OFFSET", 0, 8, &umr_bitfield_default },
	 { "CM_RGAM_RAMA_EXP_REGION20_NUM_SEGMENTS", 12, 14, &umr_bitfield_default },
	 { "CM_RGAM_RAMA_EXP_REGION21_LUT_OFFSET", 16, 24, &umr_bitfield_default },
	 { "CM_RGAM_RAMA_EXP_REGION21_NUM_SEGMENTS", 28, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmCM1_CM_RGAM_RAMA_REGION_22_23[] = {
	 { "CM_RGAM_RAMA_EXP_REGION22_LUT_OFFSET", 0, 8, &umr_bitfield_default },
	 { "CM_RGAM_RAMA_EXP_REGION22_NUM_SEGMENTS", 12, 14, &umr_bitfield_default },
	 { "CM_RGAM_RAMA_EXP_REGION23_LUT_OFFSET", 16, 24, &umr_bitfield_default },
	 { "CM_RGAM_RAMA_EXP_REGION23_NUM_SEGMENTS", 28, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmCM1_CM_RGAM_RAMA_REGION_24_25[] = {
	 { "CM_RGAM_RAMA_EXP_REGION24_LUT_OFFSET", 0, 8, &umr_bitfield_default },
	 { "CM_RGAM_RAMA_EXP_REGION24_NUM_SEGMENTS", 12, 14, &umr_bitfield_default },
	 { "CM_RGAM_RAMA_EXP_REGION25_LUT_OFFSET", 16, 24, &umr_bitfield_default },
	 { "CM_RGAM_RAMA_EXP_REGION25_NUM_SEGMENTS", 28, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmCM1_CM_RGAM_RAMA_REGION_26_27[] = {
	 { "CM_RGAM_RAMA_EXP_REGION26_LUT_OFFSET", 0, 8, &umr_bitfield_default },
	 { "CM_RGAM_RAMA_EXP_REGION26_NUM_SEGMENTS", 12, 14, &umr_bitfield_default },
	 { "CM_RGAM_RAMA_EXP_REGION27_LUT_OFFSET", 16, 24, &umr_bitfield_default },
	 { "CM_RGAM_RAMA_EXP_REGION27_NUM_SEGMENTS", 28, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmCM1_CM_RGAM_RAMA_REGION_28_29[] = {
	 { "CM_RGAM_RAMA_EXP_REGION28_LUT_OFFSET", 0, 8, &umr_bitfield_default },
	 { "CM_RGAM_RAMA_EXP_REGION28_NUM_SEGMENTS", 12, 14, &umr_bitfield_default },
	 { "CM_RGAM_RAMA_EXP_REGION29_LUT_OFFSET", 16, 24, &umr_bitfield_default },
	 { "CM_RGAM_RAMA_EXP_REGION29_NUM_SEGMENTS", 28, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmCM1_CM_RGAM_RAMA_REGION_30_31[] = {
	 { "CM_RGAM_RAMA_EXP_REGION30_LUT_OFFSET", 0, 8, &umr_bitfield_default },
	 { "CM_RGAM_RAMA_EXP_REGION30_NUM_SEGMENTS", 12, 14, &umr_bitfield_default },
	 { "CM_RGAM_RAMA_EXP_REGION31_LUT_OFFSET", 16, 24, &umr_bitfield_default },
	 { "CM_RGAM_RAMA_EXP_REGION31_NUM_SEGMENTS", 28, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmCM1_CM_RGAM_RAMA_REGION_32_33[] = {
	 { "CM_RGAM_RAMA_EXP_REGION32_LUT_OFFSET", 0, 8, &umr_bitfield_default },
	 { "CM_RGAM_RAMA_EXP_REGION32_NUM_SEGMENTS", 12, 14, &umr_bitfield_default },
	 { "CM_RGAM_RAMA_EXP_REGION33_LUT_OFFSET", 16, 24, &umr_bitfield_default },
	 { "CM_RGAM_RAMA_EXP_REGION33_NUM_SEGMENTS", 28, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmCM1_CM_RGAM_RAMB_START_CNTL_B[] = {
	 { "CM_RGAM_RAMB_EXP_REGION_START_B", 0, 17, &umr_bitfield_default },
	 { "CM_RGAM_RAMB_EXP_REGION_START_SEGMENT_B", 20, 26, &umr_bitfield_default },
};
static struct umr_bitfield mmCM1_CM_RGAM_RAMB_START_CNTL_G[] = {
	 { "CM_RGAM_RAMB_EXP_REGION_START_G", 0, 17, &umr_bitfield_default },
	 { "CM_RGAM_RAMB_EXP_REGION_START_SEGMENT_G", 20, 26, &umr_bitfield_default },
};
static struct umr_bitfield mmCM1_CM_RGAM_RAMB_START_CNTL_R[] = {
	 { "CM_RGAM_RAMB_EXP_REGION_START_R", 0, 17, &umr_bitfield_default },
	 { "CM_RGAM_RAMB_EXP_REGION_START_SEGMENT_R", 20, 26, &umr_bitfield_default },
};
static struct umr_bitfield mmCM1_CM_RGAM_RAMB_SLOPE_CNTL_B[] = {
	 { "CM_RGAM_RAMB_EXP_REGION_LINEAR_SLOPE_B", 0, 17, &umr_bitfield_default },
};
static struct umr_bitfield mmCM1_CM_RGAM_RAMB_SLOPE_CNTL_G[] = {
	 { "CM_RGAM_RAMB_EXP_REGION_LINEAR_SLOPE_G", 0, 17, &umr_bitfield_default },
};
static struct umr_bitfield mmCM1_CM_RGAM_RAMB_SLOPE_CNTL_R[] = {
	 { "CM_RGAM_RAMB_EXP_REGION_LINEAR_SLOPE_R", 0, 17, &umr_bitfield_default },
};
static struct umr_bitfield mmCM1_CM_RGAM_RAMB_END_CNTL1_B[] = {
	 { "CM_RGAM_RAMB_EXP_REGION_END_B", 0, 15, &umr_bitfield_default },
};
static struct umr_bitfield mmCM1_CM_RGAM_RAMB_END_CNTL2_B[] = {
	 { "CM_RGAM_RAMB_EXP_REGION_END_SLOPE_B", 0, 15, &umr_bitfield_default },
	 { "CM_RGAM_RAMB_EXP_REGION_END_BASE_B", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmCM1_CM_RGAM_RAMB_END_CNTL1_G[] = {
	 { "CM_RGAM_RAMB_EXP_REGION_END_G", 0, 15, &umr_bitfield_default },
};
static struct umr_bitfield mmCM1_CM_RGAM_RAMB_END_CNTL2_G[] = {
	 { "CM_RGAM_RAMB_EXP_REGION_END_SLOPE_G", 0, 15, &umr_bitfield_default },
	 { "CM_RGAM_RAMB_EXP_REGION_END_BASE_G", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmCM1_CM_RGAM_RAMB_END_CNTL1_R[] = {
	 { "CM_RGAM_RAMB_EXP_REGION_END_R", 0, 15, &umr_bitfield_default },
};
static struct umr_bitfield mmCM1_CM_RGAM_RAMB_END_CNTL2_R[] = {
	 { "CM_RGAM_RAMB_EXP_REGION_END_SLOPE_R", 0, 15, &umr_bitfield_default },
	 { "CM_RGAM_RAMB_EXP_REGION_END_BASE_R", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmCM1_CM_RGAM_RAMB_REGION_0_1[] = {
	 { "CM_RGAM_RAMB_EXP_REGION0_LUT_OFFSET", 0, 8, &umr_bitfield_default },
	 { "CM_RGAM_RAMB_EXP_REGION0_NUM_SEGMENTS", 12, 14, &umr_bitfield_default },
	 { "CM_RGAM_RAMB_EXP_REGION1_LUT_OFFSET", 16, 24, &umr_bitfield_default },
	 { "CM_RGAM_RAMB_EXP_REGION1_NUM_SEGMENTS", 28, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmCM1_CM_RGAM_RAMB_REGION_2_3[] = {
	 { "CM_RGAM_RAMB_EXP_REGION2_LUT_OFFSET", 0, 8, &umr_bitfield_default },
	 { "CM_RGAM_RAMB_EXP_REGION2_NUM_SEGMENTS", 12, 14, &umr_bitfield_default },
	 { "CM_RGAM_RAMB_EXP_REGION3_LUT_OFFSET", 16, 24, &umr_bitfield_default },
	 { "CM_RGAM_RAMB_EXP_REGION3_NUM_SEGMENTS", 28, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmCM1_CM_RGAM_RAMB_REGION_4_5[] = {
	 { "CM_RGAM_RAMB_EXP_REGION4_LUT_OFFSET", 0, 8, &umr_bitfield_default },
	 { "CM_RGAM_RAMB_EXP_REGION4_NUM_SEGMENTS", 12, 14, &umr_bitfield_default },
	 { "CM_RGAM_RAMB_EXP_REGION5_LUT_OFFSET", 16, 24, &umr_bitfield_default },
	 { "CM_RGAM_RAMB_EXP_REGION5_NUM_SEGMENTS", 28, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmCM1_CM_RGAM_RAMB_REGION_6_7[] = {
	 { "CM_RGAM_RAMB_EXP_REGION6_LUT_OFFSET", 0, 8, &umr_bitfield_default },
	 { "CM_RGAM_RAMB_EXP_REGION6_NUM_SEGMENTS", 12, 14, &umr_bitfield_default },
	 { "CM_RGAM_RAMB_EXP_REGION7_LUT_OFFSET", 16, 24, &umr_bitfield_default },
	 { "CM_RGAM_RAMB_EXP_REGION7_NUM_SEGMENTS", 28, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmCM1_CM_RGAM_RAMB_REGION_8_9[] = {
	 { "CM_RGAM_RAMB_EXP_REGION8_LUT_OFFSET", 0, 8, &umr_bitfield_default },
	 { "CM_RGAM_RAMB_EXP_REGION8_NUM_SEGMENTS", 12, 14, &umr_bitfield_default },
	 { "CM_RGAM_RAMB_EXP_REGION9_LUT_OFFSET", 16, 24, &umr_bitfield_default },
	 { "CM_RGAM_RAMB_EXP_REGION9_NUM_SEGMENTS", 28, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmCM1_CM_RGAM_RAMB_REGION_10_11[] = {
	 { "CM_RGAM_RAMB_EXP_REGION10_LUT_OFFSET", 0, 8, &umr_bitfield_default },
	 { "CM_RGAM_RAMB_EXP_REGION10_NUM_SEGMENTS", 12, 14, &umr_bitfield_default },
	 { "CM_RGAM_RAMB_EXP_REGION11_LUT_OFFSET", 16, 24, &umr_bitfield_default },
	 { "CM_RGAM_RAMB_EXP_REGION11_NUM_SEGMENTS", 28, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmCM1_CM_RGAM_RAMB_REGION_12_13[] = {
	 { "CM_RGAM_RAMB_EXP_REGION12_LUT_OFFSET", 0, 8, &umr_bitfield_default },
	 { "CM_RGAM_RAMB_EXP_REGION12_NUM_SEGMENTS", 12, 14, &umr_bitfield_default },
	 { "CM_RGAM_RAMB_EXP_REGION13_LUT_OFFSET", 16, 24, &umr_bitfield_default },
	 { "CM_RGAM_RAMB_EXP_REGION13_NUM_SEGMENTS", 28, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmCM1_CM_RGAM_RAMB_REGION_14_15[] = {
	 { "CM_RGAM_RAMB_EXP_REGION14_LUT_OFFSET", 0, 8, &umr_bitfield_default },
	 { "CM_RGAM_RAMB_EXP_REGION14_NUM_SEGMENTS", 12, 14, &umr_bitfield_default },
	 { "CM_RGAM_RAMB_EXP_REGION15_LUT_OFFSET", 16, 24, &umr_bitfield_default },
	 { "CM_RGAM_RAMB_EXP_REGION15_NUM_SEGMENTS", 28, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmCM1_CM_RGAM_RAMB_REGION_16_17[] = {
	 { "CM_RGAM_RAMB_EXP_REGION16_LUT_OFFSET", 0, 8, &umr_bitfield_default },
	 { "CM_RGAM_RAMB_EXP_REGION16_NUM_SEGMENTS", 12, 14, &umr_bitfield_default },
	 { "CM_RGAM_RAMB_EXP_REGION17_LUT_OFFSET", 16, 24, &umr_bitfield_default },
	 { "CM_RGAM_RAMB_EXP_REGION17_NUM_SEGMENTS", 28, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmCM1_CM_RGAM_RAMB_REGION_18_19[] = {
	 { "CM_RGAM_RAMB_EXP_REGION18_LUT_OFFSET", 0, 8, &umr_bitfield_default },
	 { "CM_RGAM_RAMB_EXP_REGION18_NUM_SEGMENTS", 12, 14, &umr_bitfield_default },
	 { "CM_RGAM_RAMB_EXP_REGION19_LUT_OFFSET", 16, 24, &umr_bitfield_default },
	 { "CM_RGAM_RAMB_EXP_REGION19_NUM_SEGMENTS", 28, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmCM1_CM_RGAM_RAMB_REGION_20_21[] = {
	 { "CM_RGAM_RAMB_EXP_REGION20_LUT_OFFSET", 0, 8, &umr_bitfield_default },
	 { "CM_RGAM_RAMB_EXP_REGION20_NUM_SEGMENTS", 12, 14, &umr_bitfield_default },
	 { "CM_RGAM_RAMB_EXP_REGION21_LUT_OFFSET", 16, 24, &umr_bitfield_default },
	 { "CM_RGAM_RAMB_EXP_REGION21_NUM_SEGMENTS", 28, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmCM1_CM_RGAM_RAMB_REGION_22_23[] = {
	 { "CM_RGAM_RAMB_EXP_REGION22_LUT_OFFSET", 0, 8, &umr_bitfield_default },
	 { "CM_RGAM_RAMB_EXP_REGION22_NUM_SEGMENTS", 12, 14, &umr_bitfield_default },
	 { "CM_RGAM_RAMB_EXP_REGION23_LUT_OFFSET", 16, 24, &umr_bitfield_default },
	 { "CM_RGAM_RAMB_EXP_REGION23_NUM_SEGMENTS", 28, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmCM1_CM_RGAM_RAMB_REGION_24_25[] = {
	 { "CM_RGAM_RAMB_EXP_REGION24_LUT_OFFSET", 0, 8, &umr_bitfield_default },
	 { "CM_RGAM_RAMB_EXP_REGION24_NUM_SEGMENTS", 12, 14, &umr_bitfield_default },
	 { "CM_RGAM_RAMB_EXP_REGION25_LUT_OFFSET", 16, 24, &umr_bitfield_default },
	 { "CM_RGAM_RAMB_EXP_REGION25_NUM_SEGMENTS", 28, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmCM1_CM_RGAM_RAMB_REGION_26_27[] = {
	 { "CM_RGAM_RAMB_EXP_REGION26_LUT_OFFSET", 0, 8, &umr_bitfield_default },
	 { "CM_RGAM_RAMB_EXP_REGION26_NUM_SEGMENTS", 12, 14, &umr_bitfield_default },
	 { "CM_RGAM_RAMB_EXP_REGION27_LUT_OFFSET", 16, 24, &umr_bitfield_default },
	 { "CM_RGAM_RAMB_EXP_REGION27_NUM_SEGMENTS", 28, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmCM1_CM_RGAM_RAMB_REGION_28_29[] = {
	 { "CM_RGAM_RAMB_EXP_REGION28_LUT_OFFSET", 0, 8, &umr_bitfield_default },
	 { "CM_RGAM_RAMB_EXP_REGION28_NUM_SEGMENTS", 12, 14, &umr_bitfield_default },
	 { "CM_RGAM_RAMB_EXP_REGION29_LUT_OFFSET", 16, 24, &umr_bitfield_default },
	 { "CM_RGAM_RAMB_EXP_REGION29_NUM_SEGMENTS", 28, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmCM1_CM_RGAM_RAMB_REGION_30_31[] = {
	 { "CM_RGAM_RAMB_EXP_REGION30_LUT_OFFSET", 0, 8, &umr_bitfield_default },
	 { "CM_RGAM_RAMB_EXP_REGION30_NUM_SEGMENTS", 12, 14, &umr_bitfield_default },
	 { "CM_RGAM_RAMB_EXP_REGION31_LUT_OFFSET", 16, 24, &umr_bitfield_default },
	 { "CM_RGAM_RAMB_EXP_REGION31_NUM_SEGMENTS", 28, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmCM1_CM_RGAM_RAMB_REGION_32_33[] = {
	 { "CM_RGAM_RAMB_EXP_REGION32_LUT_OFFSET", 0, 8, &umr_bitfield_default },
	 { "CM_RGAM_RAMB_EXP_REGION32_NUM_SEGMENTS", 12, 14, &umr_bitfield_default },
	 { "CM_RGAM_RAMB_EXP_REGION33_LUT_OFFSET", 16, 24, &umr_bitfield_default },
	 { "CM_RGAM_RAMB_EXP_REGION33_NUM_SEGMENTS", 28, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmCM1_CM_HDR_MULT_COEF[] = {
	 { "CM_HDR_MULT_COEF", 0, 18, &umr_bitfield_default },
};
static struct umr_bitfield mmCM1_CM_RANGE_CLAMP_CONTROL_R[] = {
	 { "CM_RANGE_CLAMP_MAX_R", 0, 15, &umr_bitfield_default },
	 { "CM_RANGE_CLAMP_MIN_R", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmCM1_CM_RANGE_CLAMP_CONTROL_G[] = {
	 { "CM_RANGE_CLAMP_MAX_G", 0, 15, &umr_bitfield_default },
	 { "CM_RANGE_CLAMP_MIN_G", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmCM1_CM_RANGE_CLAMP_CONTROL_B[] = {
	 { "CM_RANGE_CLAMP_MAX_B", 0, 15, &umr_bitfield_default },
	 { "CM_RANGE_CLAMP_MIN_B", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmCM1_CM_DENORM_CONTROL[] = {
	 { "CM_DENORM_MODE", 0, 2, &umr_bitfield_default },
	 { "CM_DENORM_ROUND_CLAMP", 4, 4, &umr_bitfield_default },
};
static struct umr_bitfield mmCM1_CM_CMOUT_CONTROL[] = {
	 { "CM_CMOUT_ROUND_TRUNC_MODE", 0, 3, &umr_bitfield_default },
	 { "CM_CMOUT_SPATIAL_DITHER_EN", 4, 4, &umr_bitfield_default },
	 { "CM_CMOUT_SPATIAL_DITHER_MODE", 8, 9, &umr_bitfield_default },
	 { "CM_CMOUT_SPATIAL_DITHER_DEPTH", 12, 13, &umr_bitfield_default },
	 { "CM_CMOUT_FRAME_RANDOM_ENABLE", 16, 16, &umr_bitfield_default },
	 { "CM_CMOUT_RGB_RANDOM_EN", 20, 20, &umr_bitfield_default },
	 { "CM_CMOUT_HIGHPASS_RANDOM_ENABLE", 24, 24, &umr_bitfield_default },
};
static struct umr_bitfield mmCM1_CM_CMOUT_RANDOM_SEEDS[] = {
	 { "CM_CMOUT_RAND_R_SEED", 0, 7, &umr_bitfield_default },
	 { "CM_CMOUT_RAND_G_SEED", 8, 15, &umr_bitfield_default },
	 { "CM_CMOUT_RAND_B_SEED", 16, 23, &umr_bitfield_default },
};
static struct umr_bitfield mmCM1_CM_MEM_PWR_CTRL[] = {
	 { "SHARED_MEM_PWR_FORCE", 0, 1, &umr_bitfield_default },
	 { "SHARED_MEM_PWR_DIS", 2, 2, &umr_bitfield_default },
	 { "RGAM_MEM_PWR_FORCE", 4, 5, &umr_bitfield_default },
	 { "RGAM_MEM_PWR_DIS", 6, 6, &umr_bitfield_default },
};
static struct umr_bitfield mmCM1_CM_MEM_PWR_STATUS[] = {
	 { "SHARED_MEM_PWR_STATE", 0, 1, &umr_bitfield_default },
	 { "RGAM_MEM_PWR_STATE", 2, 3, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_PERFMON13_PERFCOUNTER_CNTL[] = {
	 { "PERFCOUNTER_EVENT_SEL", 0, 8, &umr_bitfield_default },
	 { "PERFCOUNTER_CVALUE_SEL", 9, 11, &umr_bitfield_default },
	 { "PERFCOUNTER_INC_MODE", 12, 14, &umr_bitfield_default },
	 { "PERFCOUNTER_HW_CNTL_SEL", 15, 15, &umr_bitfield_default },
	 { "PERFCOUNTER_RUNEN_MODE", 16, 16, &umr_bitfield_default },
	 { "PERFCOUNTER_CNTOFF_START_DIS", 22, 22, &umr_bitfield_default },
	 { "PERFCOUNTER_RESTART_EN", 23, 23, &umr_bitfield_default },
	 { "PERFCOUNTER_INT_EN", 24, 24, &umr_bitfield_default },
	 { "PERFCOUNTER_OFF_MASK", 25, 25, &umr_bitfield_default },
	 { "PERFCOUNTER_ACTIVE", 26, 26, &umr_bitfield_default },
	 { "PERFCOUNTER_CNTL_SEL", 29, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_PERFMON13_PERFCOUNTER_CNTL2[] = {
	 { "PERFCOUNTER_COUNTED_VALUE_TYPE", 0, 1, &umr_bitfield_default },
	 { "PERFCOUNTER_HW_STOP1_SEL", 2, 2, &umr_bitfield_default },
	 { "PERFCOUNTER_HW_STOP2_SEL", 3, 3, &umr_bitfield_default },
	 { "PERFCOUNTER_CNTOFF_SEL", 8, 13, &umr_bitfield_default },
	 { "PERFCOUNTER_CNTL2_SEL", 29, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_PERFMON13_PERFCOUNTER_STATE[] = {
	 { "PERFCOUNTER_CNT0_STATE", 0, 1, &umr_bitfield_default },
	 { "PERFCOUNTER_STATE_SEL0", 2, 2, &umr_bitfield_default },
	 { "PERFCOUNTER_CNT1_STATE", 4, 5, &umr_bitfield_default },
	 { "PERFCOUNTER_STATE_SEL1", 6, 6, &umr_bitfield_default },
	 { "PERFCOUNTER_CNT2_STATE", 8, 9, &umr_bitfield_default },
	 { "PERFCOUNTER_STATE_SEL2", 10, 10, &umr_bitfield_default },
	 { "PERFCOUNTER_CNT3_STATE", 12, 13, &umr_bitfield_default },
	 { "PERFCOUNTER_STATE_SEL3", 14, 14, &umr_bitfield_default },
	 { "PERFCOUNTER_CNT4_STATE", 16, 17, &umr_bitfield_default },
	 { "PERFCOUNTER_STATE_SEL4", 18, 18, &umr_bitfield_default },
	 { "PERFCOUNTER_CNT5_STATE", 20, 21, &umr_bitfield_default },
	 { "PERFCOUNTER_STATE_SEL5", 22, 22, &umr_bitfield_default },
	 { "PERFCOUNTER_CNT6_STATE", 24, 25, &umr_bitfield_default },
	 { "PERFCOUNTER_STATE_SEL6", 26, 26, &umr_bitfield_default },
	 { "PERFCOUNTER_CNT7_STATE", 28, 29, &umr_bitfield_default },
	 { "PERFCOUNTER_STATE_SEL7", 30, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_PERFMON13_PERFMON_CNTL[] = {
	 { "PERFMON_STATE", 0, 1, &umr_bitfield_default },
	 { "PERFMON_RPT_COUNT", 8, 27, &umr_bitfield_default },
	 { "PERFMON_CNTOFF_AND_OR", 28, 28, &umr_bitfield_default },
	 { "PERFMON_CNTOFF_INT_EN", 29, 29, &umr_bitfield_default },
	 { "PERFMON_CNTOFF_INT_STATUS", 30, 30, &umr_bitfield_default },
	 { "PERFMON_CNTOFF_INT_ACK", 31, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_PERFMON13_PERFMON_CNTL2[] = {
	 { "PERFMON_CNTOFF_INT_TYPE", 0, 0, &umr_bitfield_default },
	 { "PERFMON_CLK_ENABLE", 1, 1, &umr_bitfield_default },
	 { "PERFMON_RUN_ENABLE_START_SEL", 2, 9, &umr_bitfield_default },
	 { "PERFMON_RUN_ENABLE_STOP_SEL", 10, 17, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_PERFMON13_PERFMON_CVALUE_INT_MISC[] = {
	 { "PERFCOUNTER_INT0_STATUS", 0, 0, &umr_bitfield_default },
	 { "PERFCOUNTER_INT1_STATUS", 1, 1, &umr_bitfield_default },
	 { "PERFCOUNTER_INT2_STATUS", 2, 2, &umr_bitfield_default },
	 { "PERFCOUNTER_INT3_STATUS", 3, 3, &umr_bitfield_default },
	 { "PERFCOUNTER_INT4_STATUS", 4, 4, &umr_bitfield_default },
	 { "PERFCOUNTER_INT5_STATUS", 5, 5, &umr_bitfield_default },
	 { "PERFCOUNTER_INT6_STATUS", 6, 6, &umr_bitfield_default },
	 { "PERFCOUNTER_INT7_STATUS", 7, 7, &umr_bitfield_default },
	 { "PERFCOUNTER_INT0_ACK", 8, 8, &umr_bitfield_default },
	 { "PERFCOUNTER_INT1_ACK", 9, 9, &umr_bitfield_default },
	 { "PERFCOUNTER_INT2_ACK", 10, 10, &umr_bitfield_default },
	 { "PERFCOUNTER_INT3_ACK", 11, 11, &umr_bitfield_default },
	 { "PERFCOUNTER_INT4_ACK", 12, 12, &umr_bitfield_default },
	 { "PERFCOUNTER_INT5_ACK", 13, 13, &umr_bitfield_default },
	 { "PERFCOUNTER_INT6_ACK", 14, 14, &umr_bitfield_default },
	 { "PERFCOUNTER_INT7_ACK", 15, 15, &umr_bitfield_default },
	 { "PERFMON_CVALUE_HI", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_PERFMON13_PERFMON_CVALUE_LOW[] = {
	 { "PERFMON_CVALUE_LOW", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_PERFMON13_PERFMON_HI[] = {
	 { "PERFMON_HI", 0, 15, &umr_bitfield_default },
	 { "PERFMON_READ_SEL", 29, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_PERFMON13_PERFMON_LOW[] = {
	 { "PERFMON_LOW", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDPP_TOP2_DPP_CONTROL[] = {
	 { "DPP_CLOCK_ENABLE", 4, 4, &umr_bitfield_default },
	 { "DPPCLK_G_GATE_DISABLE", 8, 8, &umr_bitfield_default },
	 { "DPPCLK_G_DYN_GATE_DISABLE", 10, 10, &umr_bitfield_default },
	 { "DPPCLK_G_DSCL_GATE_DISABLE", 12, 12, &umr_bitfield_default },
	 { "DPPCLK_R_GATE_DISABLE", 16, 16, &umr_bitfield_default },
	 { "DISPCLK_R_GATE_DISABLE", 18, 18, &umr_bitfield_default },
	 { "DISPCLK_G_GATE_DISABLE", 20, 20, &umr_bitfield_default },
	 { "DPPCLK_RATE_CONTROL", 24, 24, &umr_bitfield_default },
	 { "DPP_TEST_CLK_SEL", 28, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmDPP_TOP2_DPP_SOFT_RESET[] = {
	 { "CNVC_SOFT_RESET", 0, 0, &umr_bitfield_default },
	 { "DSCL_SOFT_RESET", 4, 4, &umr_bitfield_default },
	 { "CM_SOFT_RESET", 8, 8, &umr_bitfield_default },
	 { "OBUF_SOFT_RESET", 12, 12, &umr_bitfield_default },
};
static struct umr_bitfield mmDPP_TOP2_DPP_CRC_VAL_R_G[] = {
	 { "DPP_CRC_R_CR", 0, 15, &umr_bitfield_default },
	 { "DPP_CRC_G_Y", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDPP_TOP2_DPP_CRC_VAL_B_A[] = {
	 { "DPP_CRC_B_CB", 0, 15, &umr_bitfield_default },
	 { "DPP_CRC_ALPHA", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDPP_TOP2_DPP_CRC_CTRL[] = {
	 { "DPP_CRC_EN", 0, 0, &umr_bitfield_default },
	 { "DPP_CRC_CONT_EN", 1, 1, &umr_bitfield_default },
	 { "DPP_CRC_ONE_SHOT_PENDING", 2, 2, &umr_bitfield_default },
	 { "DPP_CRC_420_COMP_SEL", 3, 3, &umr_bitfield_default },
	 { "DPP_CRC_SRC_SEL", 4, 5, &umr_bitfield_default },
	 { "DPP_CRC_STEREO_EN", 7, 7, &umr_bitfield_default },
	 { "DPP_CRC_STEREO_MODE", 8, 9, &umr_bitfield_default },
	 { "DPP_CRC_INTERLACE_MODE", 10, 11, &umr_bitfield_default },
	 { "DPP_CRC_PIX_FORMAT_SEL", 12, 14, &umr_bitfield_default },
	 { "DPP_CRC_CURSOR_FORMAT_SEL", 15, 15, &umr_bitfield_default },
	 { "DPP_CRC_MASK", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDPP_TOP2_HOST_READ_CONTROL[] = {
	 { "HOST_READ_RATE_CONTROL", 0, 7, &umr_bitfield_default },
};
static struct umr_bitfield mmCNVC_CFG2_CNVC_SURFACE_PIXEL_FORMAT[] = {
	 { "CNVC_SURFACE_PIXEL_FORMAT", 0, 6, &umr_bitfield_default },
};
static struct umr_bitfield mmCNVC_CFG2_FORMAT_CONTROL[] = {
	 { "FORMAT_EXPANSION_MODE", 0, 0, &umr_bitfield_default },
	 { "FORMAT_CNV16", 4, 4, &umr_bitfield_default },
	 { "ALPHA_EN", 8, 8, &umr_bitfield_default },
	 { "CNVC_BYPASS", 12, 12, &umr_bitfield_default },
	 { "OUTPUT_FP", 16, 16, &umr_bitfield_default },
	 { "CNVC_UPDATE_PENDING", 20, 20, &umr_bitfield_default },
};
static struct umr_bitfield mmCNVC_CFG2_FCNV_FP_SCALE_BIAS[] = {
	 { "FCNV_FP_SCALE", 0, 15, &umr_bitfield_default },
	 { "FCNV_FP_BIAS", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmCNVC_CFG2_DENORM_CONTROL[] = {
	 { "DENORM_SCALE", 0, 14, &umr_bitfield_default },
	 { "CLAMP_POSITIVE", 15, 15, &umr_bitfield_default },
	 { "DENORM_BIAS", 16, 30, &umr_bitfield_default },
	 { "DENORM_TRUNCATE", 31, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmCNVC_CFG2_COLOR_KEYER_CONTROL[] = {
	 { "COLOR_KEYER_EN", 0, 0, &umr_bitfield_default },
	 { "COLOR_KEYER_MODE", 4, 5, &umr_bitfield_default },
};
static struct umr_bitfield mmCNVC_CFG2_COLOR_KEYER_ALPHA[] = {
	 { "COLOR_KEYER_ALPHA_LOW", 0, 15, &umr_bitfield_default },
	 { "COLOR_KEYER_ALPHA_HIGH", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmCNVC_CFG2_COLOR_KEYER_RED[] = {
	 { "COLOR_KEYER_RED_LOW", 0, 15, &umr_bitfield_default },
	 { "COLOR_KEYER_RED_HIGH", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmCNVC_CFG2_COLOR_KEYER_GREEN[] = {
	 { "COLOR_KEYER_GREEN_LOW", 0, 15, &umr_bitfield_default },
	 { "COLOR_KEYER_GREEN_HIGH", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmCNVC_CFG2_COLOR_KEYER_BLUE[] = {
	 { "COLOR_KEYER_BLUE_LOW", 0, 15, &umr_bitfield_default },
	 { "COLOR_KEYER_BLUE_HIGH", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmCNVC_CUR2_CURSOR0_CONTROL[] = {
	 { "CUR0_ENABLE", 0, 0, &umr_bitfield_default },
	 { "CUR0_EXPANSION_MODE", 1, 1, &umr_bitfield_default },
	 { "CUR0_INVERT_MODE", 2, 2, &umr_bitfield_default },
	 { "CUR0_MODE", 4, 5, &umr_bitfield_default },
	 { "CUR0_UPDATE_PENDING", 6, 6, &umr_bitfield_default },
	 { "CUR0_MAX", 8, 19, &umr_bitfield_default },
	 { "CUR0_MIN", 20, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmCNVC_CUR2_CURSOR0_COLOR0[] = {
	 { "CUR0_COLOR0", 0, 23, &umr_bitfield_default },
};
static struct umr_bitfield mmCNVC_CUR2_CURSOR0_COLOR1[] = {
	 { "CUR0_COLOR1", 0, 23, &umr_bitfield_default },
};
static struct umr_bitfield mmCNVC_CUR2_CURSOR0_FP_SCALE_BIAS[] = {
	 { "CUR0_FP_SCALE", 0, 15, &umr_bitfield_default },
	 { "CUR0_FP_BIAS", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDSCL2_SCL_COEF_RAM_TAP_SELECT[] = {
	 { "SCL_COEF_RAM_TAP_PAIR_IDX", 0, 1, &umr_bitfield_default },
	 { "SCL_COEF_RAM_PHASE", 8, 13, &umr_bitfield_default },
	 { "SCL_COEF_RAM_FILTER_TYPE", 16, 18, &umr_bitfield_default },
};
static struct umr_bitfield mmDSCL2_SCL_COEF_RAM_TAP_DATA[] = {
	 { "SCL_COEF_RAM_EVEN_TAP_COEF", 0, 13, &umr_bitfield_default },
	 { "SCL_COEF_RAM_EVEN_TAP_COEF_EN", 15, 15, &umr_bitfield_default },
	 { "SCL_COEF_RAM_ODD_TAP_COEF", 16, 29, &umr_bitfield_default },
	 { "SCL_COEF_RAM_ODD_TAP_COEF_EN", 31, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDSCL2_SCL_MODE[] = {
	 { "DSCL_MODE", 0, 2, &umr_bitfield_default },
	 { "SCL_COEF_RAM_SELECT", 8, 8, &umr_bitfield_default },
	 { "SCL_COEF_RAM_SELECT_CURRENT", 12, 12, &umr_bitfield_default },
	 { "SCL_CHROMA_COEF_MODE", 16, 16, &umr_bitfield_default },
	 { "SCL_ALPHA_COEF_MODE", 20, 20, &umr_bitfield_default },
	 { "SCL_COEF_RAM_SELECT_RD", 24, 24, &umr_bitfield_default },
};
static struct umr_bitfield mmDSCL2_SCL_TAP_CONTROL[] = {
	 { "SCL_V_NUM_TAPS", 0, 2, &umr_bitfield_default },
	 { "SCL_H_NUM_TAPS", 4, 6, &umr_bitfield_default },
	 { "SCL_V_NUM_TAPS_C", 8, 10, &umr_bitfield_default },
	 { "SCL_H_NUM_TAPS_C", 12, 14, &umr_bitfield_default },
};
static struct umr_bitfield mmDSCL2_DSCL_CONTROL[] = {
	 { "SCL_BOUNDARY_MODE", 0, 0, &umr_bitfield_default },
};
static struct umr_bitfield mmDSCL2_DSCL_2TAP_CONTROL[] = {
	 { "SCL_H_2TAP_HARDCODE_COEF_EN", 0, 0, &umr_bitfield_default },
	 { "SCL_H_2TAP_SHARP_EN", 4, 4, &umr_bitfield_default },
	 { "SCL_H_2TAP_SHARP_FACTOR", 8, 10, &umr_bitfield_default },
	 { "SCL_V_2TAP_HARDCODE_COEF_EN", 16, 16, &umr_bitfield_default },
	 { "SCL_V_2TAP_SHARP_EN", 20, 20, &umr_bitfield_default },
	 { "SCL_V_2TAP_SHARP_FACTOR", 24, 26, &umr_bitfield_default },
};
static struct umr_bitfield mmDSCL2_SCL_MANUAL_REPLICATE_CONTROL[] = {
	 { "SCL_V_MANUAL_REPLICATE_FACTOR", 0, 3, &umr_bitfield_default },
	 { "SCL_H_MANUAL_REPLICATE_FACTOR", 8, 11, &umr_bitfield_default },
};
static struct umr_bitfield mmDSCL2_SCL_HORZ_FILTER_SCALE_RATIO[] = {
	 { "SCL_H_SCALE_RATIO", 0, 25, &umr_bitfield_default },
};
static struct umr_bitfield mmDSCL2_SCL_HORZ_FILTER_INIT[] = {
	 { "SCL_H_INIT_FRAC", 0, 23, &umr_bitfield_default },
	 { "SCL_H_INIT_INT", 24, 27, &umr_bitfield_default },
};
static struct umr_bitfield mmDSCL2_SCL_HORZ_FILTER_SCALE_RATIO_C[] = {
	 { "SCL_H_SCALE_RATIO_C", 0, 25, &umr_bitfield_default },
};
static struct umr_bitfield mmDSCL2_SCL_HORZ_FILTER_INIT_C[] = {
	 { "SCL_H_INIT_FRAC_C", 0, 23, &umr_bitfield_default },
	 { "SCL_H_INIT_INT_C", 24, 27, &umr_bitfield_default },
};
static struct umr_bitfield mmDSCL2_SCL_VERT_FILTER_SCALE_RATIO[] = {
	 { "SCL_V_SCALE_RATIO", 0, 25, &umr_bitfield_default },
};
static struct umr_bitfield mmDSCL2_SCL_VERT_FILTER_INIT[] = {
	 { "SCL_V_INIT_FRAC", 0, 23, &umr_bitfield_default },
	 { "SCL_V_INIT_INT", 24, 27, &umr_bitfield_default },
};
static struct umr_bitfield mmDSCL2_SCL_VERT_FILTER_INIT_BOT[] = {
	 { "SCL_V_INIT_FRAC_BOT", 0, 23, &umr_bitfield_default },
	 { "SCL_V_INIT_INT_BOT", 24, 27, &umr_bitfield_default },
};
static struct umr_bitfield mmDSCL2_SCL_VERT_FILTER_SCALE_RATIO_C[] = {
	 { "SCL_V_SCALE_RATIO_C", 0, 25, &umr_bitfield_default },
};
static struct umr_bitfield mmDSCL2_SCL_VERT_FILTER_INIT_C[] = {
	 { "SCL_V_INIT_FRAC_C", 0, 23, &umr_bitfield_default },
	 { "SCL_V_INIT_INT_C", 24, 27, &umr_bitfield_default },
};
static struct umr_bitfield mmDSCL2_SCL_VERT_FILTER_INIT_BOT_C[] = {
	 { "SCL_V_INIT_FRAC_BOT_C", 0, 23, &umr_bitfield_default },
	 { "SCL_V_INIT_INT_BOT_C", 24, 27, &umr_bitfield_default },
};
static struct umr_bitfield mmDSCL2_SCL_BLACK_OFFSET[] = {
	 { "SCL_BLACK_OFFSET_RGB_Y", 0, 15, &umr_bitfield_default },
	 { "SCL_BLACK_OFFSET_CBCR", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDSCL2_DSCL_UPDATE[] = {
	 { "SCL_UPDATE_PENDING", 0, 0, &umr_bitfield_default },
};
static struct umr_bitfield mmDSCL2_DSCL_AUTOCAL[] = {
	 { "AUTOCAL_MODE", 0, 1, &umr_bitfield_default },
	 { "AUTOCAL_NUM_PIPE", 8, 9, &umr_bitfield_default },
	 { "AUTOCAL_PIPE_ID", 12, 13, &umr_bitfield_default },
};
static struct umr_bitfield mmDSCL2_DSCL_EXT_OVERSCAN_LEFT_RIGHT[] = {
	 { "EXT_OVERSCAN_RIGHT", 0, 12, &umr_bitfield_default },
	 { "EXT_OVERSCAN_LEFT", 16, 28, &umr_bitfield_default },
};
static struct umr_bitfield mmDSCL2_DSCL_EXT_OVERSCAN_TOP_BOTTOM[] = {
	 { "EXT_OVERSCAN_BOTTOM", 0, 12, &umr_bitfield_default },
	 { "EXT_OVERSCAN_TOP", 16, 28, &umr_bitfield_default },
};
static struct umr_bitfield mmDSCL2_OTG_H_BLANK[] = {
	 { "OTG_H_BLANK_START", 0, 13, &umr_bitfield_default },
	 { "OTG_H_BLANK_END", 16, 29, &umr_bitfield_default },
};
static struct umr_bitfield mmDSCL2_OTG_V_BLANK[] = {
	 { "OTG_V_BLANK_START", 0, 13, &umr_bitfield_default },
	 { "OTG_V_BLANK_END", 16, 29, &umr_bitfield_default },
};
static struct umr_bitfield mmDSCL2_RECOUT_START[] = {
	 { "RECOUT_START_X", 0, 12, &umr_bitfield_default },
	 { "RECOUT_START_Y", 16, 28, &umr_bitfield_default },
};
static struct umr_bitfield mmDSCL2_RECOUT_SIZE[] = {
	 { "RECOUT_WIDTH", 0, 13, &umr_bitfield_default },
	 { "RECOUT_HEIGHT", 16, 29, &umr_bitfield_default },
};
static struct umr_bitfield mmDSCL2_MPC_SIZE[] = {
	 { "MPC_WIDTH", 0, 13, &umr_bitfield_default },
	 { "MPC_HEIGHT", 16, 29, &umr_bitfield_default },
};
static struct umr_bitfield mmDSCL2_LB_DATA_FORMAT[] = {
	 { "PIXEL_DEPTH", 0, 1, &umr_bitfield_default },
	 { "PIXEL_EXPAN_MODE", 8, 8, &umr_bitfield_default },
	 { "PIXEL_REDUCE_MODE", 12, 12, &umr_bitfield_default },
	 { "DYNAMIC_PIXEL_DEPTH", 16, 16, &umr_bitfield_default },
	 { "DITHER_EN", 20, 20, &umr_bitfield_default },
	 { "INTERLEAVE_EN", 24, 24, &umr_bitfield_default },
	 { "ALPHA_EN", 31, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDSCL2_LB_MEMORY_CTRL[] = {
	 { "MEMORY_CONFIG", 0, 1, &umr_bitfield_default },
	 { "LB_MAX_PARTITIONS", 8, 13, &umr_bitfield_default },
	 { "LB_NUM_PARTITIONS", 16, 22, &umr_bitfield_default },
	 { "LB_NUM_PARTITIONS_C", 24, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmDSCL2_LB_V_COUNTER[] = {
	 { "V_COUNTER", 0, 12, &umr_bitfield_default },
	 { "V_COUNTER_C", 16, 28, &umr_bitfield_default },
};
static struct umr_bitfield mmDSCL2_DSCL_MEM_PWR_CTRL[] = {
	 { "LUT_MEM_PWR_FORCE", 0, 1, &umr_bitfield_default },
	 { "LUT_MEM_PWR_DIS", 2, 2, &umr_bitfield_default },
	 { "LB_G1_MEM_PWR_FORCE", 4, 5, &umr_bitfield_default },
	 { "LB_G1_MEM_PWR_DIS", 6, 6, &umr_bitfield_default },
	 { "LB_G2_MEM_PWR_FORCE", 8, 9, &umr_bitfield_default },
	 { "LB_G2_MEM_PWR_DIS", 10, 10, &umr_bitfield_default },
	 { "LB_G3_MEM_PWR_FORCE", 12, 13, &umr_bitfield_default },
	 { "LB_G3_MEM_PWR_DIS", 14, 14, &umr_bitfield_default },
	 { "LB_G4_MEM_PWR_FORCE", 16, 17, &umr_bitfield_default },
	 { "LB_G4_MEM_PWR_DIS", 18, 18, &umr_bitfield_default },
	 { "LB_G5_MEM_PWR_FORCE", 20, 21, &umr_bitfield_default },
	 { "LB_G5_MEM_PWR_DIS", 22, 22, &umr_bitfield_default },
	 { "LB_G6_MEM_PWR_FORCE", 24, 25, &umr_bitfield_default },
	 { "LB_G6_MEM_PWR_DIS", 26, 26, &umr_bitfield_default },
};
static struct umr_bitfield mmDSCL2_DSCL_MEM_PWR_STATUS[] = {
	 { "LUT_MEM_PWR_STATE", 0, 1, &umr_bitfield_default },
	 { "LB_G1_MEM_PWR_STATE", 2, 3, &umr_bitfield_default },
	 { "LB_G2_MEM_PWR_STATE", 4, 5, &umr_bitfield_default },
	 { "LB_G3_MEM_PWR_STATE", 6, 7, &umr_bitfield_default },
	 { "LB_G4_MEM_PWR_STATE", 8, 9, &umr_bitfield_default },
	 { "LB_G5_MEM_PWR_STATE", 10, 11, &umr_bitfield_default },
	 { "LB_G6_MEM_PWR_STATE", 12, 13, &umr_bitfield_default },
};
static struct umr_bitfield mmDSCL2_OBUF_CONTROL[] = {
	 { "OBUF_BYPASS", 0, 0, &umr_bitfield_default },
	 { "OBUF_USE_FULL_BUFFER", 4, 4, &umr_bitfield_default },
	 { "OBUF_H_2X_UPSCALE_EN", 8, 8, &umr_bitfield_default },
	 { "OBUF_IS_HALF_RECOUT_WIDTH", 12, 12, &umr_bitfield_default },
	 { "OBUF_H_2X_COEF_PHASE0_SEL", 16, 16, &umr_bitfield_default },
	 { "OBUF_H_2X_COEF_PHASE1_SEL", 24, 24, &umr_bitfield_default },
	 { "OBUF_OUT_HOLD_CNT", 28, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDSCL2_OBUF_MEM_PWR_CTRL[] = {
	 { "OBUF_MEM_PWR_FORCE", 0, 1, &umr_bitfield_default },
	 { "OBUF_MEM_PWR_DIS", 2, 2, &umr_bitfield_default },
	 { "OBUF_MEM_PWR_STATE", 16, 17, &umr_bitfield_default },
};
static struct umr_bitfield mmCM2_CM_CONTROL[] = {
	 { "CM_BYPASS_EN", 0, 0, &umr_bitfield_default },
	 { "CM_UPDATE_PENDING", 8, 8, &umr_bitfield_default },
};
static struct umr_bitfield mmCM2_CM_COMA_C11_C12[] = {
	 { "CM_COMA_C11", 0, 15, &umr_bitfield_default },
	 { "CM_COMA_C12", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmCM2_CM_COMA_C13_C14[] = {
	 { "CM_COMA_C13", 0, 15, &umr_bitfield_default },
	 { "CM_COMA_C14", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmCM2_CM_COMA_C21_C22[] = {
	 { "CM_COMA_C21", 0, 15, &umr_bitfield_default },
	 { "CM_COMA_C22", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmCM2_CM_COMA_C23_C24[] = {
	 { "CM_COMA_C23", 0, 15, &umr_bitfield_default },
	 { "CM_COMA_C24", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmCM2_CM_COMA_C31_C32[] = {
	 { "CM_COMA_C31", 0, 15, &umr_bitfield_default },
	 { "CM_COMA_C32", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmCM2_CM_COMA_C33_C34[] = {
	 { "CM_COMA_C33", 0, 15, &umr_bitfield_default },
	 { "CM_COMA_C34", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmCM2_CM_COMB_C11_C12[] = {
	 { "CM_COMB_C11", 0, 15, &umr_bitfield_default },
	 { "CM_COMB_C12", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmCM2_CM_COMB_C13_C14[] = {
	 { "CM_COMB_C13", 0, 15, &umr_bitfield_default },
	 { "CM_COMB_C14", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmCM2_CM_COMB_C21_C22[] = {
	 { "CM_COMB_C21", 0, 15, &umr_bitfield_default },
	 { "CM_COMB_C22", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmCM2_CM_COMB_C23_C24[] = {
	 { "CM_COMB_C23", 0, 15, &umr_bitfield_default },
	 { "CM_COMB_C24", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmCM2_CM_COMB_C31_C32[] = {
	 { "CM_COMB_C31", 0, 15, &umr_bitfield_default },
	 { "CM_COMB_C32", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmCM2_CM_COMB_C33_C34[] = {
	 { "CM_COMB_C33", 0, 15, &umr_bitfield_default },
	 { "CM_COMB_C34", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmCM2_CM_IGAM_CONTROL[] = {
	 { "CM_IGAM_LUT_MODE", 0, 1, &umr_bitfield_default },
	 { "CM_IGAM_LUT_DATA_SIGNED_EN_B", 2, 2, &umr_bitfield_default },
	 { "CM_IGAM_LUT_DATA_SIGNED_EN_G", 3, 3, &umr_bitfield_default },
	 { "CM_IGAM_LUT_DATA_SIGNED_EN_R", 4, 4, &umr_bitfield_default },
	 { "CM_IGAM_LUT_INC_B", 5, 8, &umr_bitfield_default },
	 { "CM_IGAM_LUT_INC_G", 9, 12, &umr_bitfield_default },
	 { "CM_IGAM_LUT_INC_R", 13, 16, &umr_bitfield_default },
	 { "CM_IGAM_LUT_FORMAT_B", 17, 18, &umr_bitfield_default },
	 { "CM_IGAM_LUT_FORMAT_G", 19, 20, &umr_bitfield_default },
	 { "CM_IGAM_LUT_FORMAT_R", 21, 22, &umr_bitfield_default },
	 { "CM_IGAM_LUT_B_FLOAT_POINT_EN", 23, 23, &umr_bitfield_default },
	 { "CM_IGAM_LUT_G_FLOAT_POINT_EN", 24, 24, &umr_bitfield_default },
	 { "CM_IGAM_LUT_R_FLOAT_POINT_EN", 25, 25, &umr_bitfield_default },
	 { "CM_IGAM_INPUT_FORMAT", 26, 27, &umr_bitfield_default },
};
static struct umr_bitfield mmCM2_CM_IGAM_LUT_RW_CONTROL[] = {
	 { "CM_IGAM_LUT_RW_MODE", 0, 0, &umr_bitfield_default },
	 { "CM_IGAM_LUT_WRITE_EN_MASK", 4, 6, &umr_bitfield_default },
	 { "CM_IGAM_LUT_SEL", 8, 8, &umr_bitfield_default },
	 { "CM_IGAM_LUT_HOST_EN", 12, 12, &umr_bitfield_default },
	 { "CM_IGAM_DGAM_CONFIG_STATUS", 16, 19, &umr_bitfield_default },
};
static struct umr_bitfield mmCM2_CM_IGAM_LUT_RW_INDEX[] = {
	 { "CM_IGAM_LUT_RW_INDEX", 0, 7, &umr_bitfield_default },
};
static struct umr_bitfield mmCM2_CM_IGAM_LUT_SEQ_COLOR[] = {
	 { "CM_IGAM_LUT_SEQ_COLOR", 0, 15, &umr_bitfield_default },
};
static struct umr_bitfield mmCM2_CM_IGAM_LUT_30_COLOR[] = {
	 { "CM_IGAM_LUT_10_BLUE", 0, 9, &umr_bitfield_default },
	 { "CM_IGAM_LUT_10_GREEN", 10, 19, &umr_bitfield_default },
	 { "CM_IGAM_LUT_10_RED", 20, 29, &umr_bitfield_default },
};
static struct umr_bitfield mmCM2_CM_IGAM_LUT_PWL_DATA[] = {
	 { "CM_IGAM_LUT_PWL_BASE", 0, 15, &umr_bitfield_default },
	 { "CM_IGAM_LUT_PWL_DELTA", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmCM2_CM_IGAM_LUT_AUTOFILL[] = {
	 { "CM_IGAM_LUT_AUTOFILL", 0, 0, &umr_bitfield_default },
	 { "CM_IGAM_LUT_AUTOFILL_DONE", 4, 4, &umr_bitfield_default },
};
static struct umr_bitfield mmCM2_CM_IGAM_LUT_BW_OFFSET_BLUE[] = {
	 { "CM_IGAM_LUT_BLACK_OFFSET_BLUE", 0, 15, &umr_bitfield_default },
	 { "CM_IGAM_LUT_WHITE_OFFSET_BLUE", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmCM2_CM_IGAM_LUT_BW_OFFSET_GREEN[] = {
	 { "CM_IGAM_LUT_BLACK_OFFSET_GREEN", 0, 15, &umr_bitfield_default },
	 { "CM_IGAM_LUT_WHITE_OFFSET_GREEN", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmCM2_CM_IGAM_LUT_BW_OFFSET_RED[] = {
	 { "CM_IGAM_LUT_BLACK_OFFSET_RED", 0, 15, &umr_bitfield_default },
	 { "CM_IGAM_LUT_WHITE_OFFSET_RED", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmCM2_CM_ICSC_CONTROL[] = {
	 { "CM_ICSC_MODE", 0, 1, &umr_bitfield_default },
};
static struct umr_bitfield mmCM2_CM_ICSC_C11_C12[] = {
	 { "CM_ICSC_C11", 0, 15, &umr_bitfield_default },
	 { "CM_ICSC_C12", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmCM2_CM_ICSC_C13_C14[] = {
	 { "CM_ICSC_C13", 0, 15, &umr_bitfield_default },
	 { "CM_ICSC_C14", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmCM2_CM_ICSC_C21_C22[] = {
	 { "CM_ICSC_C21", 0, 15, &umr_bitfield_default },
	 { "CM_ICSC_C22", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmCM2_CM_ICSC_C23_C24[] = {
	 { "CM_ICSC_C23", 0, 15, &umr_bitfield_default },
	 { "CM_ICSC_C24", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmCM2_CM_ICSC_C31_C32[] = {
	 { "CM_ICSC_C31", 0, 15, &umr_bitfield_default },
	 { "CM_ICSC_C32", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmCM2_CM_ICSC_C33_C34[] = {
	 { "CM_ICSC_C33", 0, 15, &umr_bitfield_default },
	 { "CM_ICSC_C34", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmCM2_CM_GAMUT_REMAP_CONTROL[] = {
	 { "CM_GAMUT_REMAP_MODE", 0, 1, &umr_bitfield_default },
};
static struct umr_bitfield mmCM2_CM_GAMUT_REMAP_C11_C12[] = {
	 { "CM_GAMUT_REMAP_C11", 0, 15, &umr_bitfield_default },
	 { "CM_GAMUT_REMAP_C12", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmCM2_CM_GAMUT_REMAP_C13_C14[] = {
	 { "CM_GAMUT_REMAP_C13", 0, 15, &umr_bitfield_default },
	 { "CM_GAMUT_REMAP_C14", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmCM2_CM_GAMUT_REMAP_C21_C22[] = {
	 { "CM_GAMUT_REMAP_C21", 0, 15, &umr_bitfield_default },
	 { "CM_GAMUT_REMAP_C22", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmCM2_CM_GAMUT_REMAP_C23_C24[] = {
	 { "CM_GAMUT_REMAP_C23", 0, 15, &umr_bitfield_default },
	 { "CM_GAMUT_REMAP_C24", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmCM2_CM_GAMUT_REMAP_C31_C32[] = {
	 { "CM_GAMUT_REMAP_C31", 0, 15, &umr_bitfield_default },
	 { "CM_GAMUT_REMAP_C32", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmCM2_CM_GAMUT_REMAP_C33_C34[] = {
	 { "CM_GAMUT_REMAP_C33", 0, 15, &umr_bitfield_default },
	 { "CM_GAMUT_REMAP_C34", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmCM2_CM_OCSC_CONTROL[] = {
	 { "CM_OCSC_MODE", 0, 2, &umr_bitfield_default },
};
static struct umr_bitfield mmCM2_CM_OCSC_C11_C12[] = {
	 { "CM_OCSC_C11", 0, 15, &umr_bitfield_default },
	 { "CM_OCSC_C12", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmCM2_CM_OCSC_C13_C14[] = {
	 { "CM_OCSC_C13", 0, 15, &umr_bitfield_default },
	 { "CM_OCSC_C14", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmCM2_CM_OCSC_C21_C22[] = {
	 { "CM_OCSC_C21", 0, 15, &umr_bitfield_default },
	 { "CM_OCSC_C22", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmCM2_CM_OCSC_C23_C24[] = {
	 { "CM_OCSC_C23", 0, 15, &umr_bitfield_default },
	 { "CM_OCSC_C24", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmCM2_CM_OCSC_C31_C32[] = {
	 { "CM_OCSC_C31", 0, 15, &umr_bitfield_default },
	 { "CM_OCSC_C32", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmCM2_CM_OCSC_C33_C34[] = {
	 { "CM_OCSC_C33", 0, 15, &umr_bitfield_default },
	 { "CM_OCSC_C34", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmCM2_CM_BNS_VALUES_R[] = {
	 { "CM_BNS_BIAS_R", 0, 15, &umr_bitfield_default },
	 { "CM_BNS_SCALE_R", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmCM2_CM_BNS_VALUES_G[] = {
	 { "CM_BNS_BIAS_G", 0, 15, &umr_bitfield_default },
	 { "CM_BNS_SCALE_G", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmCM2_CM_BNS_VALUES_B[] = {
	 { "CM_BNS_BIAS_B", 0, 15, &umr_bitfield_default },
	 { "CM_BNS_SCALE_B", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmCM2_CM_DGAM_CONTROL[] = {
	 { "CM_DGAM_LUT_MODE", 0, 2, &umr_bitfield_default },
};
static struct umr_bitfield mmCM2_CM_DGAM_LUT_INDEX[] = {
	 { "CM_DGAM_LUT_INDEX", 0, 8, &umr_bitfield_default },
};
static struct umr_bitfield mmCM2_CM_DGAM_LUT_DATA[] = {
	 { "CM_DGAM_LUT_DATA", 0, 18, &umr_bitfield_default },
};
static struct umr_bitfield mmCM2_CM_DGAM_LUT_WRITE_EN_MASK[] = {
	 { "CM_DGAM_LUT_WRITE_EN_MASK", 0, 2, &umr_bitfield_default },
	 { "CM_DGAM_LUT_WRITE_SEL", 4, 4, &umr_bitfield_default },
};
static struct umr_bitfield mmCM2_CM_DGAM_RAMA_START_CNTL_B[] = {
	 { "CM_DGAM_RAMA_EXP_REGION_START_B", 0, 17, &umr_bitfield_default },
	 { "CM_DGAM_RAMA_EXP_REGION_START_SEGMENT_B", 20, 26, &umr_bitfield_default },
};
static struct umr_bitfield mmCM2_CM_DGAM_RAMA_START_CNTL_G[] = {
	 { "CM_DGAM_RAMA_EXP_REGION_START_G", 0, 17, &umr_bitfield_default },
	 { "CM_DGAM_RAMA_EXP_REGION_START_SEGMENT_G", 20, 26, &umr_bitfield_default },
};
static struct umr_bitfield mmCM2_CM_DGAM_RAMA_START_CNTL_R[] = {
	 { "CM_DGAM_RAMA_EXP_REGION_START_R", 0, 17, &umr_bitfield_default },
	 { "CM_DGAM_RAMA_EXP_REGION_START_SEGMENT_R", 20, 26, &umr_bitfield_default },
};
static struct umr_bitfield mmCM2_CM_DGAM_RAMA_SLOPE_CNTL_B[] = {
	 { "CM_DGAM_RAMA_EXP_REGION_LINEAR_SLOPE_B", 0, 17, &umr_bitfield_default },
};
static struct umr_bitfield mmCM2_CM_DGAM_RAMA_SLOPE_CNTL_G[] = {
	 { "CM_DGAM_RAMA_EXP_REGION_LINEAR_SLOPE_G", 0, 17, &umr_bitfield_default },
};
static struct umr_bitfield mmCM2_CM_DGAM_RAMA_SLOPE_CNTL_R[] = {
	 { "CM_DGAM_RAMA_EXP_REGION_LINEAR_SLOPE_R", 0, 17, &umr_bitfield_default },
};
static struct umr_bitfield mmCM2_CM_DGAM_RAMA_END_CNTL1_B[] = {
	 { "CM_DGAM_RAMA_EXP_REGION_END_B", 0, 15, &umr_bitfield_default },
};
static struct umr_bitfield mmCM2_CM_DGAM_RAMA_END_CNTL2_B[] = {
	 { "CM_DGAM_RAMA_EXP_REGION_END_SLOPE_B", 0, 15, &umr_bitfield_default },
	 { "CM_DGAM_RAMA_EXP_REGION_END_BASE_B", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmCM2_CM_DGAM_RAMA_END_CNTL1_G[] = {
	 { "CM_DGAM_RAMA_EXP_REGION_END_G", 0, 15, &umr_bitfield_default },
};
static struct umr_bitfield mmCM2_CM_DGAM_RAMA_END_CNTL2_G[] = {
	 { "CM_DGAM_RAMA_EXP_REGION_END_SLOPE_G", 0, 15, &umr_bitfield_default },
	 { "CM_DGAM_RAMA_EXP_REGION_END_BASE_G", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmCM2_CM_DGAM_RAMA_END_CNTL1_R[] = {
	 { "CM_DGAM_RAMA_EXP_REGION_END_R", 0, 15, &umr_bitfield_default },
};
static struct umr_bitfield mmCM2_CM_DGAM_RAMA_END_CNTL2_R[] = {
	 { "CM_DGAM_RAMA_EXP_REGION_END_SLOPE_R", 0, 15, &umr_bitfield_default },
	 { "CM_DGAM_RAMA_EXP_REGION_END_BASE_R", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmCM2_CM_DGAM_RAMA_REGION_0_1[] = {
	 { "CM_DGAM_RAMA_EXP_REGION0_LUT_OFFSET", 0, 8, &umr_bitfield_default },
	 { "CM_DGAM_RAMA_EXP_REGION0_NUM_SEGMENTS", 12, 14, &umr_bitfield_default },
	 { "CM_DGAM_RAMA_EXP_REGION1_LUT_OFFSET", 16, 24, &umr_bitfield_default },
	 { "CM_DGAM_RAMA_EXP_REGION1_NUM_SEGMENTS", 28, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmCM2_CM_DGAM_RAMA_REGION_2_3[] = {
	 { "CM_DGAM_RAMA_EXP_REGION2_LUT_OFFSET", 0, 8, &umr_bitfield_default },
	 { "CM_DGAM_RAMA_EXP_REGION2_NUM_SEGMENTS", 12, 14, &umr_bitfield_default },
	 { "CM_DGAM_RAMA_EXP_REGION3_LUT_OFFSET", 16, 24, &umr_bitfield_default },
	 { "CM_DGAM_RAMA_EXP_REGION3_NUM_SEGMENTS", 28, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmCM2_CM_DGAM_RAMA_REGION_4_5[] = {
	 { "CM_DGAM_RAMA_EXP_REGION4_LUT_OFFSET", 0, 8, &umr_bitfield_default },
	 { "CM_DGAM_RAMA_EXP_REGION4_NUM_SEGMENTS", 12, 14, &umr_bitfield_default },
	 { "CM_DGAM_RAMA_EXP_REGION5_LUT_OFFSET", 16, 24, &umr_bitfield_default },
	 { "CM_DGAM_RAMA_EXP_REGION5_NUM_SEGMENTS", 28, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmCM2_CM_DGAM_RAMA_REGION_6_7[] = {
	 { "CM_DGAM_RAMA_EXP_REGION6_LUT_OFFSET", 0, 8, &umr_bitfield_default },
	 { "CM_DGAM_RAMA_EXP_REGION6_NUM_SEGMENTS", 12, 14, &umr_bitfield_default },
	 { "CM_DGAM_RAMA_EXP_REGION7_LUT_OFFSET", 16, 24, &umr_bitfield_default },
	 { "CM_DGAM_RAMA_EXP_REGION7_NUM_SEGMENTS", 28, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmCM2_CM_DGAM_RAMA_REGION_8_9[] = {
	 { "CM_DGAM_RAMA_EXP_REGION8_LUT_OFFSET", 0, 8, &umr_bitfield_default },
	 { "CM_DGAM_RAMA_EXP_REGION8_NUM_SEGMENTS", 12, 14, &umr_bitfield_default },
	 { "CM_DGAM_RAMA_EXP_REGION9_LUT_OFFSET", 16, 24, &umr_bitfield_default },
	 { "CM_DGAM_RAMA_EXP_REGION9_NUM_SEGMENTS", 28, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmCM2_CM_DGAM_RAMA_REGION_10_11[] = {
	 { "CM_DGAM_RAMA_EXP_REGION10_LUT_OFFSET", 0, 8, &umr_bitfield_default },
	 { "CM_DGAM_RAMA_EXP_REGION10_NUM_SEGMENTS", 12, 14, &umr_bitfield_default },
	 { "CM_DGAM_RAMA_EXP_REGION11_LUT_OFFSET", 16, 24, &umr_bitfield_default },
	 { "CM_DGAM_RAMA_EXP_REGION11_NUM_SEGMENTS", 28, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmCM2_CM_DGAM_RAMA_REGION_12_13[] = {
	 { "CM_DGAM_RAMA_EXP_REGION12_LUT_OFFSET", 0, 8, &umr_bitfield_default },
	 { "CM_DGAM_RAMA_EXP_REGION12_NUM_SEGMENTS", 12, 14, &umr_bitfield_default },
	 { "CM_DGAM_RAMA_EXP_REGION13_LUT_OFFSET", 16, 24, &umr_bitfield_default },
	 { "CM_DGAM_RAMA_EXP_REGION13_NUM_SEGMENTS", 28, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmCM2_CM_DGAM_RAMA_REGION_14_15[] = {
	 { "CM_DGAM_RAMA_EXP_REGION14_LUT_OFFSET", 0, 8, &umr_bitfield_default },
	 { "CM_DGAM_RAMA_EXP_REGION14_NUM_SEGMENTS", 12, 14, &umr_bitfield_default },
	 { "CM_DGAM_RAMA_EXP_REGION15_LUT_OFFSET", 16, 24, &umr_bitfield_default },
	 { "CM_DGAM_RAMA_EXP_REGION15_NUM_SEGMENTS", 28, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmCM2_CM_DGAM_RAMB_START_CNTL_B[] = {
	 { "CM_DGAM_RAMB_EXP_REGION_START_B", 0, 17, &umr_bitfield_default },
	 { "CM_DGAM_RAMB_EXP_REGION_START_SEGMENT_B", 20, 26, &umr_bitfield_default },
};
static struct umr_bitfield mmCM2_CM_DGAM_RAMB_START_CNTL_G[] = {
	 { "CM_DGAM_RAMB_EXP_REGION_START_G", 0, 17, &umr_bitfield_default },
	 { "CM_DGAM_RAMB_EXP_REGION_START_SEGMENT_G", 20, 26, &umr_bitfield_default },
};
static struct umr_bitfield mmCM2_CM_DGAM_RAMB_START_CNTL_R[] = {
	 { "CM_DGAM_RAMB_EXP_REGION_START_R", 0, 17, &umr_bitfield_default },
	 { "CM_DGAM_RAMB_EXP_REGION_START_SEGMENT_R", 20, 26, &umr_bitfield_default },
};
static struct umr_bitfield mmCM2_CM_DGAM_RAMB_SLOPE_CNTL_B[] = {
	 { "CM_DGAM_RAMB_EXP_REGION_LINEAR_SLOPE_B", 0, 17, &umr_bitfield_default },
};
static struct umr_bitfield mmCM2_CM_DGAM_RAMB_SLOPE_CNTL_G[] = {
	 { "CM_DGAM_RAMB_EXP_REGION_LINEAR_SLOPE_G", 0, 17, &umr_bitfield_default },
};
static struct umr_bitfield mmCM2_CM_DGAM_RAMB_SLOPE_CNTL_R[] = {
	 { "CM_DGAM_RAMB_EXP_REGION_LINEAR_SLOPE_R", 0, 17, &umr_bitfield_default },
};
static struct umr_bitfield mmCM2_CM_DGAM_RAMB_END_CNTL1_B[] = {
	 { "CM_DGAM_RAMB_EXP_REGION_END_B", 0, 15, &umr_bitfield_default },
};
static struct umr_bitfield mmCM2_CM_DGAM_RAMB_END_CNTL2_B[] = {
	 { "CM_DGAM_RAMB_EXP_REGION_END_SLOPE_B", 0, 15, &umr_bitfield_default },
	 { "CM_DGAM_RAMB_EXP_REGION_END_BASE_B", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmCM2_CM_DGAM_RAMB_END_CNTL1_G[] = {
	 { "CM_DGAM_RAMB_EXP_REGION_END_G", 0, 15, &umr_bitfield_default },
};
static struct umr_bitfield mmCM2_CM_DGAM_RAMB_END_CNTL2_G[] = {
	 { "CM_DGAM_RAMB_EXP_REGION_END_SLOPE_G", 0, 15, &umr_bitfield_default },
	 { "CM_DGAM_RAMB_EXP_REGION_END_BASE_G", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmCM2_CM_DGAM_RAMB_END_CNTL1_R[] = {
	 { "CM_DGAM_RAMB_EXP_REGION_END_R", 0, 15, &umr_bitfield_default },
};
static struct umr_bitfield mmCM2_CM_DGAM_RAMB_END_CNTL2_R[] = {
	 { "CM_DGAM_RAMB_EXP_REGION_END_SLOPE_R", 0, 15, &umr_bitfield_default },
	 { "CM_DGAM_RAMB_EXP_REGION_END_BASE_R", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmCM2_CM_DGAM_RAMB_REGION_0_1[] = {
	 { "CM_DGAM_RAMB_EXP_REGION0_LUT_OFFSET", 0, 8, &umr_bitfield_default },
	 { "CM_DGAM_RAMB_EXP_REGION0_NUM_SEGMENTS", 12, 14, &umr_bitfield_default },
	 { "CM_DGAM_RAMB_EXP_REGION1_LUT_OFFSET", 16, 24, &umr_bitfield_default },
	 { "CM_DGAM_RAMB_EXP_REGION1_NUM_SEGMENTS", 28, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmCM2_CM_DGAM_RAMB_REGION_2_3[] = {
	 { "CM_DGAM_RAMB_EXP_REGION2_LUT_OFFSET", 0, 8, &umr_bitfield_default },
	 { "CM_DGAM_RAMB_EXP_REGION2_NUM_SEGMENTS", 12, 14, &umr_bitfield_default },
	 { "CM_DGAM_RAMB_EXP_REGION3_LUT_OFFSET", 16, 24, &umr_bitfield_default },
	 { "CM_DGAM_RAMB_EXP_REGION3_NUM_SEGMENTS", 28, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmCM2_CM_DGAM_RAMB_REGION_4_5[] = {
	 { "CM_DGAM_RAMB_EXP_REGION4_LUT_OFFSET", 0, 8, &umr_bitfield_default },
	 { "CM_DGAM_RAMB_EXP_REGION4_NUM_SEGMENTS", 12, 14, &umr_bitfield_default },
	 { "CM_DGAM_RAMB_EXP_REGION5_LUT_OFFSET", 16, 24, &umr_bitfield_default },
	 { "CM_DGAM_RAMB_EXP_REGION5_NUM_SEGMENTS", 28, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmCM2_CM_DGAM_RAMB_REGION_6_7[] = {
	 { "CM_DGAM_RAMB_EXP_REGION6_LUT_OFFSET", 0, 8, &umr_bitfield_default },
	 { "CM_DGAM_RAMB_EXP_REGION6_NUM_SEGMENTS", 12, 14, &umr_bitfield_default },
	 { "CM_DGAM_RAMB_EXP_REGION7_LUT_OFFSET", 16, 24, &umr_bitfield_default },
	 { "CM_DGAM_RAMB_EXP_REGION7_NUM_SEGMENTS", 28, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmCM2_CM_DGAM_RAMB_REGION_8_9[] = {
	 { "CM_DGAM_RAMB_EXP_REGION8_LUT_OFFSET", 0, 8, &umr_bitfield_default },
	 { "CM_DGAM_RAMB_EXP_REGION8_NUM_SEGMENTS", 12, 14, &umr_bitfield_default },
	 { "CM_DGAM_RAMB_EXP_REGION9_LUT_OFFSET", 16, 24, &umr_bitfield_default },
	 { "CM_DGAM_RAMB_EXP_REGION9_NUM_SEGMENTS", 28, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmCM2_CM_DGAM_RAMB_REGION_10_11[] = {
	 { "CM_DGAM_RAMB_EXP_REGION10_LUT_OFFSET", 0, 8, &umr_bitfield_default },
	 { "CM_DGAM_RAMB_EXP_REGION10_NUM_SEGMENTS", 12, 14, &umr_bitfield_default },
	 { "CM_DGAM_RAMB_EXP_REGION11_LUT_OFFSET", 16, 24, &umr_bitfield_default },
	 { "CM_DGAM_RAMB_EXP_REGION11_NUM_SEGMENTS", 28, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmCM2_CM_DGAM_RAMB_REGION_12_13[] = {
	 { "CM_DGAM_RAMB_EXP_REGION12_LUT_OFFSET", 0, 8, &umr_bitfield_default },
	 { "CM_DGAM_RAMB_EXP_REGION12_NUM_SEGMENTS", 12, 14, &umr_bitfield_default },
	 { "CM_DGAM_RAMB_EXP_REGION13_LUT_OFFSET", 16, 24, &umr_bitfield_default },
	 { "CM_DGAM_RAMB_EXP_REGION13_NUM_SEGMENTS", 28, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmCM2_CM_DGAM_RAMB_REGION_14_15[] = {
	 { "CM_DGAM_RAMB_EXP_REGION14_LUT_OFFSET", 0, 8, &umr_bitfield_default },
	 { "CM_DGAM_RAMB_EXP_REGION14_NUM_SEGMENTS", 12, 14, &umr_bitfield_default },
	 { "CM_DGAM_RAMB_EXP_REGION15_LUT_OFFSET", 16, 24, &umr_bitfield_default },
	 { "CM_DGAM_RAMB_EXP_REGION15_NUM_SEGMENTS", 28, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmCM2_CM_RGAM_CONTROL[] = {
	 { "CM_RGAM_LUT_MODE", 0, 2, &umr_bitfield_default },
};
static struct umr_bitfield mmCM2_CM_RGAM_LUT_INDEX[] = {
	 { "CM_RGAM_LUT_INDEX", 0, 8, &umr_bitfield_default },
};
static struct umr_bitfield mmCM2_CM_RGAM_LUT_DATA[] = {
	 { "CM_RGAM_LUT_DATA", 0, 18, &umr_bitfield_default },
};
static struct umr_bitfield mmCM2_CM_RGAM_LUT_WRITE_EN_MASK[] = {
	 { "CM_RGAM_LUT_WRITE_EN_MASK", 0, 2, &umr_bitfield_default },
	 { "CM_RGAM_LUT_WRITE_SEL", 4, 4, &umr_bitfield_default },
	 { "CM_RGAM_CONFIG_STATUS", 8, 10, &umr_bitfield_default },
};
static struct umr_bitfield mmCM2_CM_RGAM_RAMA_START_CNTL_B[] = {
	 { "CM_RGAM_RAMA_EXP_REGION_START_B", 0, 17, &umr_bitfield_default },
	 { "CM_RGAM_RAMA_EXP_REGION_START_SEGMENT_B", 20, 26, &umr_bitfield_default },
};
static struct umr_bitfield mmCM2_CM_RGAM_RAMA_START_CNTL_G[] = {
	 { "CM_RGAM_RAMA_EXP_REGION_START_G", 0, 17, &umr_bitfield_default },
	 { "CM_RGAM_RAMA_EXP_REGION_START_SEGMENT_G", 20, 26, &umr_bitfield_default },
};
static struct umr_bitfield mmCM2_CM_RGAM_RAMA_START_CNTL_R[] = {
	 { "CM_RGAM_RAMA_EXP_REGION_START_R", 0, 17, &umr_bitfield_default },
	 { "CM_RGAM_RAMA_EXP_REGION_START_SEGMENT_R", 20, 26, &umr_bitfield_default },
};
static struct umr_bitfield mmCM2_CM_RGAM_RAMA_SLOPE_CNTL_B[] = {
	 { "CM_RGAM_RAMA_EXP_REGION_LINEAR_SLOPE_B", 0, 17, &umr_bitfield_default },
};
static struct umr_bitfield mmCM2_CM_RGAM_RAMA_SLOPE_CNTL_G[] = {
	 { "CM_RGAM_RAMA_EXP_REGION_LINEAR_SLOPE_G", 0, 17, &umr_bitfield_default },
};
static struct umr_bitfield mmCM2_CM_RGAM_RAMA_SLOPE_CNTL_R[] = {
	 { "CM_RGAM_RAMA_EXP_REGION_LINEAR_SLOPE_R", 0, 17, &umr_bitfield_default },
};
static struct umr_bitfield mmCM2_CM_RGAM_RAMA_END_CNTL1_B[] = {
	 { "CM_RGAM_RAMA_EXP_REGION_END_B", 0, 15, &umr_bitfield_default },
};
static struct umr_bitfield mmCM2_CM_RGAM_RAMA_END_CNTL2_B[] = {
	 { "CM_RGAM_RAMA_EXP_REGION_END_SLOPE_B", 0, 15, &umr_bitfield_default },
	 { "CM_RGAM_RAMA_EXP_REGION_END_BASE_B", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmCM2_CM_RGAM_RAMA_END_CNTL1_G[] = {
	 { "CM_RGAM_RAMA_EXP_REGION_END_G", 0, 15, &umr_bitfield_default },
};
static struct umr_bitfield mmCM2_CM_RGAM_RAMA_END_CNTL2_G[] = {
	 { "CM_RGAM_RAMA_EXP_REGION_END_SLOPE_G", 0, 15, &umr_bitfield_default },
	 { "CM_RGAM_RAMA_EXP_REGION_END_BASE_G", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmCM2_CM_RGAM_RAMA_END_CNTL1_R[] = {
	 { "CM_RGAM_RAMA_EXP_REGION_END_R", 0, 15, &umr_bitfield_default },
};
static struct umr_bitfield mmCM2_CM_RGAM_RAMA_END_CNTL2_R[] = {
	 { "CM_RGAM_RAMA_EXP_REGION_END_SLOPE_R", 0, 15, &umr_bitfield_default },
	 { "CM_RGAM_RAMA_EXP_REGION_END_BASE_R", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmCM2_CM_RGAM_RAMA_REGION_0_1[] = {
	 { "CM_RGAM_RAMA_EXP_REGION0_LUT_OFFSET", 0, 8, &umr_bitfield_default },
	 { "CM_RGAM_RAMA_EXP_REGION0_NUM_SEGMENTS", 12, 14, &umr_bitfield_default },
	 { "CM_RGAM_RAMA_EXP_REGION1_LUT_OFFSET", 16, 24, &umr_bitfield_default },
	 { "CM_RGAM_RAMA_EXP_REGION1_NUM_SEGMENTS", 28, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmCM2_CM_RGAM_RAMA_REGION_2_3[] = {
	 { "CM_RGAM_RAMA_EXP_REGION2_LUT_OFFSET", 0, 8, &umr_bitfield_default },
	 { "CM_RGAM_RAMA_EXP_REGION2_NUM_SEGMENTS", 12, 14, &umr_bitfield_default },
	 { "CM_RGAM_RAMA_EXP_REGION3_LUT_OFFSET", 16, 24, &umr_bitfield_default },
	 { "CM_RGAM_RAMA_EXP_REGION3_NUM_SEGMENTS", 28, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmCM2_CM_RGAM_RAMA_REGION_4_5[] = {
	 { "CM_RGAM_RAMA_EXP_REGION4_LUT_OFFSET", 0, 8, &umr_bitfield_default },
	 { "CM_RGAM_RAMA_EXP_REGION4_NUM_SEGMENTS", 12, 14, &umr_bitfield_default },
	 { "CM_RGAM_RAMA_EXP_REGION5_LUT_OFFSET", 16, 24, &umr_bitfield_default },
	 { "CM_RGAM_RAMA_EXP_REGION5_NUM_SEGMENTS", 28, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmCM2_CM_RGAM_RAMA_REGION_6_7[] = {
	 { "CM_RGAM_RAMA_EXP_REGION6_LUT_OFFSET", 0, 8, &umr_bitfield_default },
	 { "CM_RGAM_RAMA_EXP_REGION6_NUM_SEGMENTS", 12, 14, &umr_bitfield_default },
	 { "CM_RGAM_RAMA_EXP_REGION7_LUT_OFFSET", 16, 24, &umr_bitfield_default },
	 { "CM_RGAM_RAMA_EXP_REGION7_NUM_SEGMENTS", 28, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmCM2_CM_RGAM_RAMA_REGION_8_9[] = {
	 { "CM_RGAM_RAMA_EXP_REGION8_LUT_OFFSET", 0, 8, &umr_bitfield_default },
	 { "CM_RGAM_RAMA_EXP_REGION8_NUM_SEGMENTS", 12, 14, &umr_bitfield_default },
	 { "CM_RGAM_RAMA_EXP_REGION9_LUT_OFFSET", 16, 24, &umr_bitfield_default },
	 { "CM_RGAM_RAMA_EXP_REGION9_NUM_SEGMENTS", 28, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmCM2_CM_RGAM_RAMA_REGION_10_11[] = {
	 { "CM_RGAM_RAMA_EXP_REGION10_LUT_OFFSET", 0, 8, &umr_bitfield_default },
	 { "CM_RGAM_RAMA_EXP_REGION10_NUM_SEGMENTS", 12, 14, &umr_bitfield_default },
	 { "CM_RGAM_RAMA_EXP_REGION11_LUT_OFFSET", 16, 24, &umr_bitfield_default },
	 { "CM_RGAM_RAMA_EXP_REGION11_NUM_SEGMENTS", 28, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmCM2_CM_RGAM_RAMA_REGION_12_13[] = {
	 { "CM_RGAM_RAMA_EXP_REGION12_LUT_OFFSET", 0, 8, &umr_bitfield_default },
	 { "CM_RGAM_RAMA_EXP_REGION12_NUM_SEGMENTS", 12, 14, &umr_bitfield_default },
	 { "CM_RGAM_RAMA_EXP_REGION13_LUT_OFFSET", 16, 24, &umr_bitfield_default },
	 { "CM_RGAM_RAMA_EXP_REGION13_NUM_SEGMENTS", 28, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmCM2_CM_RGAM_RAMA_REGION_14_15[] = {
	 { "CM_RGAM_RAMA_EXP_REGION14_LUT_OFFSET", 0, 8, &umr_bitfield_default },
	 { "CM_RGAM_RAMA_EXP_REGION14_NUM_SEGMENTS", 12, 14, &umr_bitfield_default },
	 { "CM_RGAM_RAMA_EXP_REGION15_LUT_OFFSET", 16, 24, &umr_bitfield_default },
	 { "CM_RGAM_RAMA_EXP_REGION15_NUM_SEGMENTS", 28, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmCM2_CM_RGAM_RAMA_REGION_16_17[] = {
	 { "CM_RGAM_RAMA_EXP_REGION16_LUT_OFFSET", 0, 8, &umr_bitfield_default },
	 { "CM_RGAM_RAMA_EXP_REGION16_NUM_SEGMENTS", 12, 14, &umr_bitfield_default },
	 { "CM_RGAM_RAMA_EXP_REGION17_LUT_OFFSET", 16, 24, &umr_bitfield_default },
	 { "CM_RGAM_RAMA_EXP_REGION17_NUM_SEGMENTS", 28, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmCM2_CM_RGAM_RAMA_REGION_18_19[] = {
	 { "CM_RGAM_RAMA_EXP_REGION18_LUT_OFFSET", 0, 8, &umr_bitfield_default },
	 { "CM_RGAM_RAMA_EXP_REGION18_NUM_SEGMENTS", 12, 14, &umr_bitfield_default },
	 { "CM_RGAM_RAMA_EXP_REGION19_LUT_OFFSET", 16, 24, &umr_bitfield_default },
	 { "CM_RGAM_RAMA_EXP_REGION19_NUM_SEGMENTS", 28, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmCM2_CM_RGAM_RAMA_REGION_20_21[] = {
	 { "CM_RGAM_RAMA_EXP_REGION20_LUT_OFFSET", 0, 8, &umr_bitfield_default },
	 { "CM_RGAM_RAMA_EXP_REGION20_NUM_SEGMENTS", 12, 14, &umr_bitfield_default },
	 { "CM_RGAM_RAMA_EXP_REGION21_LUT_OFFSET", 16, 24, &umr_bitfield_default },
	 { "CM_RGAM_RAMA_EXP_REGION21_NUM_SEGMENTS", 28, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmCM2_CM_RGAM_RAMA_REGION_22_23[] = {
	 { "CM_RGAM_RAMA_EXP_REGION22_LUT_OFFSET", 0, 8, &umr_bitfield_default },
	 { "CM_RGAM_RAMA_EXP_REGION22_NUM_SEGMENTS", 12, 14, &umr_bitfield_default },
	 { "CM_RGAM_RAMA_EXP_REGION23_LUT_OFFSET", 16, 24, &umr_bitfield_default },
	 { "CM_RGAM_RAMA_EXP_REGION23_NUM_SEGMENTS", 28, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmCM2_CM_RGAM_RAMA_REGION_24_25[] = {
	 { "CM_RGAM_RAMA_EXP_REGION24_LUT_OFFSET", 0, 8, &umr_bitfield_default },
	 { "CM_RGAM_RAMA_EXP_REGION24_NUM_SEGMENTS", 12, 14, &umr_bitfield_default },
	 { "CM_RGAM_RAMA_EXP_REGION25_LUT_OFFSET", 16, 24, &umr_bitfield_default },
	 { "CM_RGAM_RAMA_EXP_REGION25_NUM_SEGMENTS", 28, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmCM2_CM_RGAM_RAMA_REGION_26_27[] = {
	 { "CM_RGAM_RAMA_EXP_REGION26_LUT_OFFSET", 0, 8, &umr_bitfield_default },
	 { "CM_RGAM_RAMA_EXP_REGION26_NUM_SEGMENTS", 12, 14, &umr_bitfield_default },
	 { "CM_RGAM_RAMA_EXP_REGION27_LUT_OFFSET", 16, 24, &umr_bitfield_default },
	 { "CM_RGAM_RAMA_EXP_REGION27_NUM_SEGMENTS", 28, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmCM2_CM_RGAM_RAMA_REGION_28_29[] = {
	 { "CM_RGAM_RAMA_EXP_REGION28_LUT_OFFSET", 0, 8, &umr_bitfield_default },
	 { "CM_RGAM_RAMA_EXP_REGION28_NUM_SEGMENTS", 12, 14, &umr_bitfield_default },
	 { "CM_RGAM_RAMA_EXP_REGION29_LUT_OFFSET", 16, 24, &umr_bitfield_default },
	 { "CM_RGAM_RAMA_EXP_REGION29_NUM_SEGMENTS", 28, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmCM2_CM_RGAM_RAMA_REGION_30_31[] = {
	 { "CM_RGAM_RAMA_EXP_REGION30_LUT_OFFSET", 0, 8, &umr_bitfield_default },
	 { "CM_RGAM_RAMA_EXP_REGION30_NUM_SEGMENTS", 12, 14, &umr_bitfield_default },
	 { "CM_RGAM_RAMA_EXP_REGION31_LUT_OFFSET", 16, 24, &umr_bitfield_default },
	 { "CM_RGAM_RAMA_EXP_REGION31_NUM_SEGMENTS", 28, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmCM2_CM_RGAM_RAMA_REGION_32_33[] = {
	 { "CM_RGAM_RAMA_EXP_REGION32_LUT_OFFSET", 0, 8, &umr_bitfield_default },
	 { "CM_RGAM_RAMA_EXP_REGION32_NUM_SEGMENTS", 12, 14, &umr_bitfield_default },
	 { "CM_RGAM_RAMA_EXP_REGION33_LUT_OFFSET", 16, 24, &umr_bitfield_default },
	 { "CM_RGAM_RAMA_EXP_REGION33_NUM_SEGMENTS", 28, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmCM2_CM_RGAM_RAMB_START_CNTL_B[] = {
	 { "CM_RGAM_RAMB_EXP_REGION_START_B", 0, 17, &umr_bitfield_default },
	 { "CM_RGAM_RAMB_EXP_REGION_START_SEGMENT_B", 20, 26, &umr_bitfield_default },
};
static struct umr_bitfield mmCM2_CM_RGAM_RAMB_START_CNTL_G[] = {
	 { "CM_RGAM_RAMB_EXP_REGION_START_G", 0, 17, &umr_bitfield_default },
	 { "CM_RGAM_RAMB_EXP_REGION_START_SEGMENT_G", 20, 26, &umr_bitfield_default },
};
static struct umr_bitfield mmCM2_CM_RGAM_RAMB_START_CNTL_R[] = {
	 { "CM_RGAM_RAMB_EXP_REGION_START_R", 0, 17, &umr_bitfield_default },
	 { "CM_RGAM_RAMB_EXP_REGION_START_SEGMENT_R", 20, 26, &umr_bitfield_default },
};
static struct umr_bitfield mmCM2_CM_RGAM_RAMB_SLOPE_CNTL_B[] = {
	 { "CM_RGAM_RAMB_EXP_REGION_LINEAR_SLOPE_B", 0, 17, &umr_bitfield_default },
};
static struct umr_bitfield mmCM2_CM_RGAM_RAMB_SLOPE_CNTL_G[] = {
	 { "CM_RGAM_RAMB_EXP_REGION_LINEAR_SLOPE_G", 0, 17, &umr_bitfield_default },
};
static struct umr_bitfield mmCM2_CM_RGAM_RAMB_SLOPE_CNTL_R[] = {
	 { "CM_RGAM_RAMB_EXP_REGION_LINEAR_SLOPE_R", 0, 17, &umr_bitfield_default },
};
static struct umr_bitfield mmCM2_CM_RGAM_RAMB_END_CNTL1_B[] = {
	 { "CM_RGAM_RAMB_EXP_REGION_END_B", 0, 15, &umr_bitfield_default },
};
static struct umr_bitfield mmCM2_CM_RGAM_RAMB_END_CNTL2_B[] = {
	 { "CM_RGAM_RAMB_EXP_REGION_END_SLOPE_B", 0, 15, &umr_bitfield_default },
	 { "CM_RGAM_RAMB_EXP_REGION_END_BASE_B", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmCM2_CM_RGAM_RAMB_END_CNTL1_G[] = {
	 { "CM_RGAM_RAMB_EXP_REGION_END_G", 0, 15, &umr_bitfield_default },
};
static struct umr_bitfield mmCM2_CM_RGAM_RAMB_END_CNTL2_G[] = {
	 { "CM_RGAM_RAMB_EXP_REGION_END_SLOPE_G", 0, 15, &umr_bitfield_default },
	 { "CM_RGAM_RAMB_EXP_REGION_END_BASE_G", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmCM2_CM_RGAM_RAMB_END_CNTL1_R[] = {
	 { "CM_RGAM_RAMB_EXP_REGION_END_R", 0, 15, &umr_bitfield_default },
};
static struct umr_bitfield mmCM2_CM_RGAM_RAMB_END_CNTL2_R[] = {
	 { "CM_RGAM_RAMB_EXP_REGION_END_SLOPE_R", 0, 15, &umr_bitfield_default },
	 { "CM_RGAM_RAMB_EXP_REGION_END_BASE_R", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmCM2_CM_RGAM_RAMB_REGION_0_1[] = {
	 { "CM_RGAM_RAMB_EXP_REGION0_LUT_OFFSET", 0, 8, &umr_bitfield_default },
	 { "CM_RGAM_RAMB_EXP_REGION0_NUM_SEGMENTS", 12, 14, &umr_bitfield_default },
	 { "CM_RGAM_RAMB_EXP_REGION1_LUT_OFFSET", 16, 24, &umr_bitfield_default },
	 { "CM_RGAM_RAMB_EXP_REGION1_NUM_SEGMENTS", 28, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmCM2_CM_RGAM_RAMB_REGION_2_3[] = {
	 { "CM_RGAM_RAMB_EXP_REGION2_LUT_OFFSET", 0, 8, &umr_bitfield_default },
	 { "CM_RGAM_RAMB_EXP_REGION2_NUM_SEGMENTS", 12, 14, &umr_bitfield_default },
	 { "CM_RGAM_RAMB_EXP_REGION3_LUT_OFFSET", 16, 24, &umr_bitfield_default },
	 { "CM_RGAM_RAMB_EXP_REGION3_NUM_SEGMENTS", 28, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmCM2_CM_RGAM_RAMB_REGION_4_5[] = {
	 { "CM_RGAM_RAMB_EXP_REGION4_LUT_OFFSET", 0, 8, &umr_bitfield_default },
	 { "CM_RGAM_RAMB_EXP_REGION4_NUM_SEGMENTS", 12, 14, &umr_bitfield_default },
	 { "CM_RGAM_RAMB_EXP_REGION5_LUT_OFFSET", 16, 24, &umr_bitfield_default },
	 { "CM_RGAM_RAMB_EXP_REGION5_NUM_SEGMENTS", 28, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmCM2_CM_RGAM_RAMB_REGION_6_7[] = {
	 { "CM_RGAM_RAMB_EXP_REGION6_LUT_OFFSET", 0, 8, &umr_bitfield_default },
	 { "CM_RGAM_RAMB_EXP_REGION6_NUM_SEGMENTS", 12, 14, &umr_bitfield_default },
	 { "CM_RGAM_RAMB_EXP_REGION7_LUT_OFFSET", 16, 24, &umr_bitfield_default },
	 { "CM_RGAM_RAMB_EXP_REGION7_NUM_SEGMENTS", 28, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmCM2_CM_RGAM_RAMB_REGION_8_9[] = {
	 { "CM_RGAM_RAMB_EXP_REGION8_LUT_OFFSET", 0, 8, &umr_bitfield_default },
	 { "CM_RGAM_RAMB_EXP_REGION8_NUM_SEGMENTS", 12, 14, &umr_bitfield_default },
	 { "CM_RGAM_RAMB_EXP_REGION9_LUT_OFFSET", 16, 24, &umr_bitfield_default },
	 { "CM_RGAM_RAMB_EXP_REGION9_NUM_SEGMENTS", 28, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmCM2_CM_RGAM_RAMB_REGION_10_11[] = {
	 { "CM_RGAM_RAMB_EXP_REGION10_LUT_OFFSET", 0, 8, &umr_bitfield_default },
	 { "CM_RGAM_RAMB_EXP_REGION10_NUM_SEGMENTS", 12, 14, &umr_bitfield_default },
	 { "CM_RGAM_RAMB_EXP_REGION11_LUT_OFFSET", 16, 24, &umr_bitfield_default },
	 { "CM_RGAM_RAMB_EXP_REGION11_NUM_SEGMENTS", 28, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmCM2_CM_RGAM_RAMB_REGION_12_13[] = {
	 { "CM_RGAM_RAMB_EXP_REGION12_LUT_OFFSET", 0, 8, &umr_bitfield_default },
	 { "CM_RGAM_RAMB_EXP_REGION12_NUM_SEGMENTS", 12, 14, &umr_bitfield_default },
	 { "CM_RGAM_RAMB_EXP_REGION13_LUT_OFFSET", 16, 24, &umr_bitfield_default },
	 { "CM_RGAM_RAMB_EXP_REGION13_NUM_SEGMENTS", 28, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmCM2_CM_RGAM_RAMB_REGION_14_15[] = {
	 { "CM_RGAM_RAMB_EXP_REGION14_LUT_OFFSET", 0, 8, &umr_bitfield_default },
	 { "CM_RGAM_RAMB_EXP_REGION14_NUM_SEGMENTS", 12, 14, &umr_bitfield_default },
	 { "CM_RGAM_RAMB_EXP_REGION15_LUT_OFFSET", 16, 24, &umr_bitfield_default },
	 { "CM_RGAM_RAMB_EXP_REGION15_NUM_SEGMENTS", 28, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmCM2_CM_RGAM_RAMB_REGION_16_17[] = {
	 { "CM_RGAM_RAMB_EXP_REGION16_LUT_OFFSET", 0, 8, &umr_bitfield_default },
	 { "CM_RGAM_RAMB_EXP_REGION16_NUM_SEGMENTS", 12, 14, &umr_bitfield_default },
	 { "CM_RGAM_RAMB_EXP_REGION17_LUT_OFFSET", 16, 24, &umr_bitfield_default },
	 { "CM_RGAM_RAMB_EXP_REGION17_NUM_SEGMENTS", 28, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmCM2_CM_RGAM_RAMB_REGION_18_19[] = {
	 { "CM_RGAM_RAMB_EXP_REGION18_LUT_OFFSET", 0, 8, &umr_bitfield_default },
	 { "CM_RGAM_RAMB_EXP_REGION18_NUM_SEGMENTS", 12, 14, &umr_bitfield_default },
	 { "CM_RGAM_RAMB_EXP_REGION19_LUT_OFFSET", 16, 24, &umr_bitfield_default },
	 { "CM_RGAM_RAMB_EXP_REGION19_NUM_SEGMENTS", 28, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmCM2_CM_RGAM_RAMB_REGION_20_21[] = {
	 { "CM_RGAM_RAMB_EXP_REGION20_LUT_OFFSET", 0, 8, &umr_bitfield_default },
	 { "CM_RGAM_RAMB_EXP_REGION20_NUM_SEGMENTS", 12, 14, &umr_bitfield_default },
	 { "CM_RGAM_RAMB_EXP_REGION21_LUT_OFFSET", 16, 24, &umr_bitfield_default },
	 { "CM_RGAM_RAMB_EXP_REGION21_NUM_SEGMENTS", 28, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmCM2_CM_RGAM_RAMB_REGION_22_23[] = {
	 { "CM_RGAM_RAMB_EXP_REGION22_LUT_OFFSET", 0, 8, &umr_bitfield_default },
	 { "CM_RGAM_RAMB_EXP_REGION22_NUM_SEGMENTS", 12, 14, &umr_bitfield_default },
	 { "CM_RGAM_RAMB_EXP_REGION23_LUT_OFFSET", 16, 24, &umr_bitfield_default },
	 { "CM_RGAM_RAMB_EXP_REGION23_NUM_SEGMENTS", 28, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmCM2_CM_RGAM_RAMB_REGION_24_25[] = {
	 { "CM_RGAM_RAMB_EXP_REGION24_LUT_OFFSET", 0, 8, &umr_bitfield_default },
	 { "CM_RGAM_RAMB_EXP_REGION24_NUM_SEGMENTS", 12, 14, &umr_bitfield_default },
	 { "CM_RGAM_RAMB_EXP_REGION25_LUT_OFFSET", 16, 24, &umr_bitfield_default },
	 { "CM_RGAM_RAMB_EXP_REGION25_NUM_SEGMENTS", 28, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmCM2_CM_RGAM_RAMB_REGION_26_27[] = {
	 { "CM_RGAM_RAMB_EXP_REGION26_LUT_OFFSET", 0, 8, &umr_bitfield_default },
	 { "CM_RGAM_RAMB_EXP_REGION26_NUM_SEGMENTS", 12, 14, &umr_bitfield_default },
	 { "CM_RGAM_RAMB_EXP_REGION27_LUT_OFFSET", 16, 24, &umr_bitfield_default },
	 { "CM_RGAM_RAMB_EXP_REGION27_NUM_SEGMENTS", 28, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmCM2_CM_RGAM_RAMB_REGION_28_29[] = {
	 { "CM_RGAM_RAMB_EXP_REGION28_LUT_OFFSET", 0, 8, &umr_bitfield_default },
	 { "CM_RGAM_RAMB_EXP_REGION28_NUM_SEGMENTS", 12, 14, &umr_bitfield_default },
	 { "CM_RGAM_RAMB_EXP_REGION29_LUT_OFFSET", 16, 24, &umr_bitfield_default },
	 { "CM_RGAM_RAMB_EXP_REGION29_NUM_SEGMENTS", 28, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmCM2_CM_RGAM_RAMB_REGION_30_31[] = {
	 { "CM_RGAM_RAMB_EXP_REGION30_LUT_OFFSET", 0, 8, &umr_bitfield_default },
	 { "CM_RGAM_RAMB_EXP_REGION30_NUM_SEGMENTS", 12, 14, &umr_bitfield_default },
	 { "CM_RGAM_RAMB_EXP_REGION31_LUT_OFFSET", 16, 24, &umr_bitfield_default },
	 { "CM_RGAM_RAMB_EXP_REGION31_NUM_SEGMENTS", 28, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmCM2_CM_RGAM_RAMB_REGION_32_33[] = {
	 { "CM_RGAM_RAMB_EXP_REGION32_LUT_OFFSET", 0, 8, &umr_bitfield_default },
	 { "CM_RGAM_RAMB_EXP_REGION32_NUM_SEGMENTS", 12, 14, &umr_bitfield_default },
	 { "CM_RGAM_RAMB_EXP_REGION33_LUT_OFFSET", 16, 24, &umr_bitfield_default },
	 { "CM_RGAM_RAMB_EXP_REGION33_NUM_SEGMENTS", 28, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmCM2_CM_HDR_MULT_COEF[] = {
	 { "CM_HDR_MULT_COEF", 0, 18, &umr_bitfield_default },
};
static struct umr_bitfield mmCM2_CM_RANGE_CLAMP_CONTROL_R[] = {
	 { "CM_RANGE_CLAMP_MAX_R", 0, 15, &umr_bitfield_default },
	 { "CM_RANGE_CLAMP_MIN_R", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmCM2_CM_RANGE_CLAMP_CONTROL_G[] = {
	 { "CM_RANGE_CLAMP_MAX_G", 0, 15, &umr_bitfield_default },
	 { "CM_RANGE_CLAMP_MIN_G", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmCM2_CM_RANGE_CLAMP_CONTROL_B[] = {
	 { "CM_RANGE_CLAMP_MAX_B", 0, 15, &umr_bitfield_default },
	 { "CM_RANGE_CLAMP_MIN_B", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmCM2_CM_DENORM_CONTROL[] = {
	 { "CM_DENORM_MODE", 0, 2, &umr_bitfield_default },
	 { "CM_DENORM_ROUND_CLAMP", 4, 4, &umr_bitfield_default },
};
static struct umr_bitfield mmCM2_CM_CMOUT_CONTROL[] = {
	 { "CM_CMOUT_ROUND_TRUNC_MODE", 0, 3, &umr_bitfield_default },
	 { "CM_CMOUT_SPATIAL_DITHER_EN", 4, 4, &umr_bitfield_default },
	 { "CM_CMOUT_SPATIAL_DITHER_MODE", 8, 9, &umr_bitfield_default },
	 { "CM_CMOUT_SPATIAL_DITHER_DEPTH", 12, 13, &umr_bitfield_default },
	 { "CM_CMOUT_FRAME_RANDOM_ENABLE", 16, 16, &umr_bitfield_default },
	 { "CM_CMOUT_RGB_RANDOM_EN", 20, 20, &umr_bitfield_default },
	 { "CM_CMOUT_HIGHPASS_RANDOM_ENABLE", 24, 24, &umr_bitfield_default },
};
static struct umr_bitfield mmCM2_CM_CMOUT_RANDOM_SEEDS[] = {
	 { "CM_CMOUT_RAND_R_SEED", 0, 7, &umr_bitfield_default },
	 { "CM_CMOUT_RAND_G_SEED", 8, 15, &umr_bitfield_default },
	 { "CM_CMOUT_RAND_B_SEED", 16, 23, &umr_bitfield_default },
};
static struct umr_bitfield mmCM2_CM_MEM_PWR_CTRL[] = {
	 { "SHARED_MEM_PWR_FORCE", 0, 1, &umr_bitfield_default },
	 { "SHARED_MEM_PWR_DIS", 2, 2, &umr_bitfield_default },
	 { "RGAM_MEM_PWR_FORCE", 4, 5, &umr_bitfield_default },
	 { "RGAM_MEM_PWR_DIS", 6, 6, &umr_bitfield_default },
};
static struct umr_bitfield mmCM2_CM_MEM_PWR_STATUS[] = {
	 { "SHARED_MEM_PWR_STATE", 0, 1, &umr_bitfield_default },
	 { "RGAM_MEM_PWR_STATE", 2, 3, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_PERFMON14_PERFCOUNTER_CNTL[] = {
	 { "PERFCOUNTER_EVENT_SEL", 0, 8, &umr_bitfield_default },
	 { "PERFCOUNTER_CVALUE_SEL", 9, 11, &umr_bitfield_default },
	 { "PERFCOUNTER_INC_MODE", 12, 14, &umr_bitfield_default },
	 { "PERFCOUNTER_HW_CNTL_SEL", 15, 15, &umr_bitfield_default },
	 { "PERFCOUNTER_RUNEN_MODE", 16, 16, &umr_bitfield_default },
	 { "PERFCOUNTER_CNTOFF_START_DIS", 22, 22, &umr_bitfield_default },
	 { "PERFCOUNTER_RESTART_EN", 23, 23, &umr_bitfield_default },
	 { "PERFCOUNTER_INT_EN", 24, 24, &umr_bitfield_default },
	 { "PERFCOUNTER_OFF_MASK", 25, 25, &umr_bitfield_default },
	 { "PERFCOUNTER_ACTIVE", 26, 26, &umr_bitfield_default },
	 { "PERFCOUNTER_CNTL_SEL", 29, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_PERFMON14_PERFCOUNTER_CNTL2[] = {
	 { "PERFCOUNTER_COUNTED_VALUE_TYPE", 0, 1, &umr_bitfield_default },
	 { "PERFCOUNTER_HW_STOP1_SEL", 2, 2, &umr_bitfield_default },
	 { "PERFCOUNTER_HW_STOP2_SEL", 3, 3, &umr_bitfield_default },
	 { "PERFCOUNTER_CNTOFF_SEL", 8, 13, &umr_bitfield_default },
	 { "PERFCOUNTER_CNTL2_SEL", 29, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_PERFMON14_PERFCOUNTER_STATE[] = {
	 { "PERFCOUNTER_CNT0_STATE", 0, 1, &umr_bitfield_default },
	 { "PERFCOUNTER_STATE_SEL0", 2, 2, &umr_bitfield_default },
	 { "PERFCOUNTER_CNT1_STATE", 4, 5, &umr_bitfield_default },
	 { "PERFCOUNTER_STATE_SEL1", 6, 6, &umr_bitfield_default },
	 { "PERFCOUNTER_CNT2_STATE", 8, 9, &umr_bitfield_default },
	 { "PERFCOUNTER_STATE_SEL2", 10, 10, &umr_bitfield_default },
	 { "PERFCOUNTER_CNT3_STATE", 12, 13, &umr_bitfield_default },
	 { "PERFCOUNTER_STATE_SEL3", 14, 14, &umr_bitfield_default },
	 { "PERFCOUNTER_CNT4_STATE", 16, 17, &umr_bitfield_default },
	 { "PERFCOUNTER_STATE_SEL4", 18, 18, &umr_bitfield_default },
	 { "PERFCOUNTER_CNT5_STATE", 20, 21, &umr_bitfield_default },
	 { "PERFCOUNTER_STATE_SEL5", 22, 22, &umr_bitfield_default },
	 { "PERFCOUNTER_CNT6_STATE", 24, 25, &umr_bitfield_default },
	 { "PERFCOUNTER_STATE_SEL6", 26, 26, &umr_bitfield_default },
	 { "PERFCOUNTER_CNT7_STATE", 28, 29, &umr_bitfield_default },
	 { "PERFCOUNTER_STATE_SEL7", 30, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_PERFMON14_PERFMON_CNTL[] = {
	 { "PERFMON_STATE", 0, 1, &umr_bitfield_default },
	 { "PERFMON_RPT_COUNT", 8, 27, &umr_bitfield_default },
	 { "PERFMON_CNTOFF_AND_OR", 28, 28, &umr_bitfield_default },
	 { "PERFMON_CNTOFF_INT_EN", 29, 29, &umr_bitfield_default },
	 { "PERFMON_CNTOFF_INT_STATUS", 30, 30, &umr_bitfield_default },
	 { "PERFMON_CNTOFF_INT_ACK", 31, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_PERFMON14_PERFMON_CNTL2[] = {
	 { "PERFMON_CNTOFF_INT_TYPE", 0, 0, &umr_bitfield_default },
	 { "PERFMON_CLK_ENABLE", 1, 1, &umr_bitfield_default },
	 { "PERFMON_RUN_ENABLE_START_SEL", 2, 9, &umr_bitfield_default },
	 { "PERFMON_RUN_ENABLE_STOP_SEL", 10, 17, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_PERFMON14_PERFMON_CVALUE_INT_MISC[] = {
	 { "PERFCOUNTER_INT0_STATUS", 0, 0, &umr_bitfield_default },
	 { "PERFCOUNTER_INT1_STATUS", 1, 1, &umr_bitfield_default },
	 { "PERFCOUNTER_INT2_STATUS", 2, 2, &umr_bitfield_default },
	 { "PERFCOUNTER_INT3_STATUS", 3, 3, &umr_bitfield_default },
	 { "PERFCOUNTER_INT4_STATUS", 4, 4, &umr_bitfield_default },
	 { "PERFCOUNTER_INT5_STATUS", 5, 5, &umr_bitfield_default },
	 { "PERFCOUNTER_INT6_STATUS", 6, 6, &umr_bitfield_default },
	 { "PERFCOUNTER_INT7_STATUS", 7, 7, &umr_bitfield_default },
	 { "PERFCOUNTER_INT0_ACK", 8, 8, &umr_bitfield_default },
	 { "PERFCOUNTER_INT1_ACK", 9, 9, &umr_bitfield_default },
	 { "PERFCOUNTER_INT2_ACK", 10, 10, &umr_bitfield_default },
	 { "PERFCOUNTER_INT3_ACK", 11, 11, &umr_bitfield_default },
	 { "PERFCOUNTER_INT4_ACK", 12, 12, &umr_bitfield_default },
	 { "PERFCOUNTER_INT5_ACK", 13, 13, &umr_bitfield_default },
	 { "PERFCOUNTER_INT6_ACK", 14, 14, &umr_bitfield_default },
	 { "PERFCOUNTER_INT7_ACK", 15, 15, &umr_bitfield_default },
	 { "PERFMON_CVALUE_HI", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_PERFMON14_PERFMON_CVALUE_LOW[] = {
	 { "PERFMON_CVALUE_LOW", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_PERFMON14_PERFMON_HI[] = {
	 { "PERFMON_HI", 0, 15, &umr_bitfield_default },
	 { "PERFMON_READ_SEL", 29, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_PERFMON14_PERFMON_LOW[] = {
	 { "PERFMON_LOW", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDPP_TOP3_DPP_CONTROL[] = {
	 { "DPP_CLOCK_ENABLE", 4, 4, &umr_bitfield_default },
	 { "DPPCLK_G_GATE_DISABLE", 8, 8, &umr_bitfield_default },
	 { "DPPCLK_G_DYN_GATE_DISABLE", 10, 10, &umr_bitfield_default },
	 { "DPPCLK_G_DSCL_GATE_DISABLE", 12, 12, &umr_bitfield_default },
	 { "DPPCLK_R_GATE_DISABLE", 16, 16, &umr_bitfield_default },
	 { "DISPCLK_R_GATE_DISABLE", 18, 18, &umr_bitfield_default },
	 { "DISPCLK_G_GATE_DISABLE", 20, 20, &umr_bitfield_default },
	 { "DPPCLK_RATE_CONTROL", 24, 24, &umr_bitfield_default },
	 { "DPP_TEST_CLK_SEL", 28, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmDPP_TOP3_DPP_SOFT_RESET[] = {
	 { "CNVC_SOFT_RESET", 0, 0, &umr_bitfield_default },
	 { "DSCL_SOFT_RESET", 4, 4, &umr_bitfield_default },
	 { "CM_SOFT_RESET", 8, 8, &umr_bitfield_default },
	 { "OBUF_SOFT_RESET", 12, 12, &umr_bitfield_default },
};
static struct umr_bitfield mmDPP_TOP3_DPP_CRC_VAL_R_G[] = {
	 { "DPP_CRC_R_CR", 0, 15, &umr_bitfield_default },
	 { "DPP_CRC_G_Y", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDPP_TOP3_DPP_CRC_VAL_B_A[] = {
	 { "DPP_CRC_B_CB", 0, 15, &umr_bitfield_default },
	 { "DPP_CRC_ALPHA", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDPP_TOP3_DPP_CRC_CTRL[] = {
	 { "DPP_CRC_EN", 0, 0, &umr_bitfield_default },
	 { "DPP_CRC_CONT_EN", 1, 1, &umr_bitfield_default },
	 { "DPP_CRC_ONE_SHOT_PENDING", 2, 2, &umr_bitfield_default },
	 { "DPP_CRC_420_COMP_SEL", 3, 3, &umr_bitfield_default },
	 { "DPP_CRC_SRC_SEL", 4, 5, &umr_bitfield_default },
	 { "DPP_CRC_STEREO_EN", 7, 7, &umr_bitfield_default },
	 { "DPP_CRC_STEREO_MODE", 8, 9, &umr_bitfield_default },
	 { "DPP_CRC_INTERLACE_MODE", 10, 11, &umr_bitfield_default },
	 { "DPP_CRC_PIX_FORMAT_SEL", 12, 14, &umr_bitfield_default },
	 { "DPP_CRC_CURSOR_FORMAT_SEL", 15, 15, &umr_bitfield_default },
	 { "DPP_CRC_MASK", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDPP_TOP3_HOST_READ_CONTROL[] = {
	 { "HOST_READ_RATE_CONTROL", 0, 7, &umr_bitfield_default },
};
static struct umr_bitfield mmCNVC_CFG3_CNVC_SURFACE_PIXEL_FORMAT[] = {
	 { "CNVC_SURFACE_PIXEL_FORMAT", 0, 6, &umr_bitfield_default },
};
static struct umr_bitfield mmCNVC_CFG3_FORMAT_CONTROL[] = {
	 { "FORMAT_EXPANSION_MODE", 0, 0, &umr_bitfield_default },
	 { "FORMAT_CNV16", 4, 4, &umr_bitfield_default },
	 { "ALPHA_EN", 8, 8, &umr_bitfield_default },
	 { "CNVC_BYPASS", 12, 12, &umr_bitfield_default },
	 { "OUTPUT_FP", 16, 16, &umr_bitfield_default },
	 { "CNVC_UPDATE_PENDING", 20, 20, &umr_bitfield_default },
};
static struct umr_bitfield mmCNVC_CFG3_FCNV_FP_SCALE_BIAS[] = {
	 { "FCNV_FP_SCALE", 0, 15, &umr_bitfield_default },
	 { "FCNV_FP_BIAS", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmCNVC_CFG3_DENORM_CONTROL[] = {
	 { "DENORM_SCALE", 0, 14, &umr_bitfield_default },
	 { "CLAMP_POSITIVE", 15, 15, &umr_bitfield_default },
	 { "DENORM_BIAS", 16, 30, &umr_bitfield_default },
	 { "DENORM_TRUNCATE", 31, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmCNVC_CFG3_COLOR_KEYER_CONTROL[] = {
	 { "COLOR_KEYER_EN", 0, 0, &umr_bitfield_default },
	 { "COLOR_KEYER_MODE", 4, 5, &umr_bitfield_default },
};
static struct umr_bitfield mmCNVC_CFG3_COLOR_KEYER_ALPHA[] = {
	 { "COLOR_KEYER_ALPHA_LOW", 0, 15, &umr_bitfield_default },
	 { "COLOR_KEYER_ALPHA_HIGH", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmCNVC_CFG3_COLOR_KEYER_RED[] = {
	 { "COLOR_KEYER_RED_LOW", 0, 15, &umr_bitfield_default },
	 { "COLOR_KEYER_RED_HIGH", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmCNVC_CFG3_COLOR_KEYER_GREEN[] = {
	 { "COLOR_KEYER_GREEN_LOW", 0, 15, &umr_bitfield_default },
	 { "COLOR_KEYER_GREEN_HIGH", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmCNVC_CFG3_COLOR_KEYER_BLUE[] = {
	 { "COLOR_KEYER_BLUE_LOW", 0, 15, &umr_bitfield_default },
	 { "COLOR_KEYER_BLUE_HIGH", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmCNVC_CUR3_CURSOR0_CONTROL[] = {
	 { "CUR0_ENABLE", 0, 0, &umr_bitfield_default },
	 { "CUR0_EXPANSION_MODE", 1, 1, &umr_bitfield_default },
	 { "CUR0_INVERT_MODE", 2, 2, &umr_bitfield_default },
	 { "CUR0_MODE", 4, 5, &umr_bitfield_default },
	 { "CUR0_UPDATE_PENDING", 6, 6, &umr_bitfield_default },
	 { "CUR0_MAX", 8, 19, &umr_bitfield_default },
	 { "CUR0_MIN", 20, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmCNVC_CUR3_CURSOR0_COLOR0[] = {
	 { "CUR0_COLOR0", 0, 23, &umr_bitfield_default },
};
static struct umr_bitfield mmCNVC_CUR3_CURSOR0_COLOR1[] = {
	 { "CUR0_COLOR1", 0, 23, &umr_bitfield_default },
};
static struct umr_bitfield mmCNVC_CUR3_CURSOR0_FP_SCALE_BIAS[] = {
	 { "CUR0_FP_SCALE", 0, 15, &umr_bitfield_default },
	 { "CUR0_FP_BIAS", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDSCL3_SCL_COEF_RAM_TAP_SELECT[] = {
	 { "SCL_COEF_RAM_TAP_PAIR_IDX", 0, 1, &umr_bitfield_default },
	 { "SCL_COEF_RAM_PHASE", 8, 13, &umr_bitfield_default },
	 { "SCL_COEF_RAM_FILTER_TYPE", 16, 18, &umr_bitfield_default },
};
static struct umr_bitfield mmDSCL3_SCL_COEF_RAM_TAP_DATA[] = {
	 { "SCL_COEF_RAM_EVEN_TAP_COEF", 0, 13, &umr_bitfield_default },
	 { "SCL_COEF_RAM_EVEN_TAP_COEF_EN", 15, 15, &umr_bitfield_default },
	 { "SCL_COEF_RAM_ODD_TAP_COEF", 16, 29, &umr_bitfield_default },
	 { "SCL_COEF_RAM_ODD_TAP_COEF_EN", 31, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDSCL3_SCL_MODE[] = {
	 { "DSCL_MODE", 0, 2, &umr_bitfield_default },
	 { "SCL_COEF_RAM_SELECT", 8, 8, &umr_bitfield_default },
	 { "SCL_COEF_RAM_SELECT_CURRENT", 12, 12, &umr_bitfield_default },
	 { "SCL_CHROMA_COEF_MODE", 16, 16, &umr_bitfield_default },
	 { "SCL_ALPHA_COEF_MODE", 20, 20, &umr_bitfield_default },
	 { "SCL_COEF_RAM_SELECT_RD", 24, 24, &umr_bitfield_default },
};
static struct umr_bitfield mmDSCL3_SCL_TAP_CONTROL[] = {
	 { "SCL_V_NUM_TAPS", 0, 2, &umr_bitfield_default },
	 { "SCL_H_NUM_TAPS", 4, 6, &umr_bitfield_default },
	 { "SCL_V_NUM_TAPS_C", 8, 10, &umr_bitfield_default },
	 { "SCL_H_NUM_TAPS_C", 12, 14, &umr_bitfield_default },
};
static struct umr_bitfield mmDSCL3_DSCL_CONTROL[] = {
	 { "SCL_BOUNDARY_MODE", 0, 0, &umr_bitfield_default },
};
static struct umr_bitfield mmDSCL3_DSCL_2TAP_CONTROL[] = {
	 { "SCL_H_2TAP_HARDCODE_COEF_EN", 0, 0, &umr_bitfield_default },
	 { "SCL_H_2TAP_SHARP_EN", 4, 4, &umr_bitfield_default },
	 { "SCL_H_2TAP_SHARP_FACTOR", 8, 10, &umr_bitfield_default },
	 { "SCL_V_2TAP_HARDCODE_COEF_EN", 16, 16, &umr_bitfield_default },
	 { "SCL_V_2TAP_SHARP_EN", 20, 20, &umr_bitfield_default },
	 { "SCL_V_2TAP_SHARP_FACTOR", 24, 26, &umr_bitfield_default },
};
static struct umr_bitfield mmDSCL3_SCL_MANUAL_REPLICATE_CONTROL[] = {
	 { "SCL_V_MANUAL_REPLICATE_FACTOR", 0, 3, &umr_bitfield_default },
	 { "SCL_H_MANUAL_REPLICATE_FACTOR", 8, 11, &umr_bitfield_default },
};
static struct umr_bitfield mmDSCL3_SCL_HORZ_FILTER_SCALE_RATIO[] = {
	 { "SCL_H_SCALE_RATIO", 0, 25, &umr_bitfield_default },
};
static struct umr_bitfield mmDSCL3_SCL_HORZ_FILTER_INIT[] = {
	 { "SCL_H_INIT_FRAC", 0, 23, &umr_bitfield_default },
	 { "SCL_H_INIT_INT", 24, 27, &umr_bitfield_default },
};
static struct umr_bitfield mmDSCL3_SCL_HORZ_FILTER_SCALE_RATIO_C[] = {
	 { "SCL_H_SCALE_RATIO_C", 0, 25, &umr_bitfield_default },
};
static struct umr_bitfield mmDSCL3_SCL_HORZ_FILTER_INIT_C[] = {
	 { "SCL_H_INIT_FRAC_C", 0, 23, &umr_bitfield_default },
	 { "SCL_H_INIT_INT_C", 24, 27, &umr_bitfield_default },
};
static struct umr_bitfield mmDSCL3_SCL_VERT_FILTER_SCALE_RATIO[] = {
	 { "SCL_V_SCALE_RATIO", 0, 25, &umr_bitfield_default },
};
static struct umr_bitfield mmDSCL3_SCL_VERT_FILTER_INIT[] = {
	 { "SCL_V_INIT_FRAC", 0, 23, &umr_bitfield_default },
	 { "SCL_V_INIT_INT", 24, 27, &umr_bitfield_default },
};
static struct umr_bitfield mmDSCL3_SCL_VERT_FILTER_INIT_BOT[] = {
	 { "SCL_V_INIT_FRAC_BOT", 0, 23, &umr_bitfield_default },
	 { "SCL_V_INIT_INT_BOT", 24, 27, &umr_bitfield_default },
};
static struct umr_bitfield mmDSCL3_SCL_VERT_FILTER_SCALE_RATIO_C[] = {
	 { "SCL_V_SCALE_RATIO_C", 0, 25, &umr_bitfield_default },
};
static struct umr_bitfield mmDSCL3_SCL_VERT_FILTER_INIT_C[] = {
	 { "SCL_V_INIT_FRAC_C", 0, 23, &umr_bitfield_default },
	 { "SCL_V_INIT_INT_C", 24, 27, &umr_bitfield_default },
};
static struct umr_bitfield mmDSCL3_SCL_VERT_FILTER_INIT_BOT_C[] = {
	 { "SCL_V_INIT_FRAC_BOT_C", 0, 23, &umr_bitfield_default },
	 { "SCL_V_INIT_INT_BOT_C", 24, 27, &umr_bitfield_default },
};
static struct umr_bitfield mmDSCL3_SCL_BLACK_OFFSET[] = {
	 { "SCL_BLACK_OFFSET_RGB_Y", 0, 15, &umr_bitfield_default },
	 { "SCL_BLACK_OFFSET_CBCR", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDSCL3_DSCL_UPDATE[] = {
	 { "SCL_UPDATE_PENDING", 0, 0, &umr_bitfield_default },
};
static struct umr_bitfield mmDSCL3_DSCL_AUTOCAL[] = {
	 { "AUTOCAL_MODE", 0, 1, &umr_bitfield_default },
	 { "AUTOCAL_NUM_PIPE", 8, 9, &umr_bitfield_default },
	 { "AUTOCAL_PIPE_ID", 12, 13, &umr_bitfield_default },
};
static struct umr_bitfield mmDSCL3_DSCL_EXT_OVERSCAN_LEFT_RIGHT[] = {
	 { "EXT_OVERSCAN_RIGHT", 0, 12, &umr_bitfield_default },
	 { "EXT_OVERSCAN_LEFT", 16, 28, &umr_bitfield_default },
};
static struct umr_bitfield mmDSCL3_DSCL_EXT_OVERSCAN_TOP_BOTTOM[] = {
	 { "EXT_OVERSCAN_BOTTOM", 0, 12, &umr_bitfield_default },
	 { "EXT_OVERSCAN_TOP", 16, 28, &umr_bitfield_default },
};
static struct umr_bitfield mmDSCL3_OTG_H_BLANK[] = {
	 { "OTG_H_BLANK_START", 0, 13, &umr_bitfield_default },
	 { "OTG_H_BLANK_END", 16, 29, &umr_bitfield_default },
};
static struct umr_bitfield mmDSCL3_OTG_V_BLANK[] = {
	 { "OTG_V_BLANK_START", 0, 13, &umr_bitfield_default },
	 { "OTG_V_BLANK_END", 16, 29, &umr_bitfield_default },
};
static struct umr_bitfield mmDSCL3_RECOUT_START[] = {
	 { "RECOUT_START_X", 0, 12, &umr_bitfield_default },
	 { "RECOUT_START_Y", 16, 28, &umr_bitfield_default },
};
static struct umr_bitfield mmDSCL3_RECOUT_SIZE[] = {
	 { "RECOUT_WIDTH", 0, 13, &umr_bitfield_default },
	 { "RECOUT_HEIGHT", 16, 29, &umr_bitfield_default },
};
static struct umr_bitfield mmDSCL3_MPC_SIZE[] = {
	 { "MPC_WIDTH", 0, 13, &umr_bitfield_default },
	 { "MPC_HEIGHT", 16, 29, &umr_bitfield_default },
};
static struct umr_bitfield mmDSCL3_LB_DATA_FORMAT[] = {
	 { "PIXEL_DEPTH", 0, 1, &umr_bitfield_default },
	 { "PIXEL_EXPAN_MODE", 8, 8, &umr_bitfield_default },
	 { "PIXEL_REDUCE_MODE", 12, 12, &umr_bitfield_default },
	 { "DYNAMIC_PIXEL_DEPTH", 16, 16, &umr_bitfield_default },
	 { "DITHER_EN", 20, 20, &umr_bitfield_default },
	 { "INTERLEAVE_EN", 24, 24, &umr_bitfield_default },
	 { "ALPHA_EN", 31, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDSCL3_LB_MEMORY_CTRL[] = {
	 { "MEMORY_CONFIG", 0, 1, &umr_bitfield_default },
	 { "LB_MAX_PARTITIONS", 8, 13, &umr_bitfield_default },
	 { "LB_NUM_PARTITIONS", 16, 22, &umr_bitfield_default },
	 { "LB_NUM_PARTITIONS_C", 24, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmDSCL3_LB_V_COUNTER[] = {
	 { "V_COUNTER", 0, 12, &umr_bitfield_default },
	 { "V_COUNTER_C", 16, 28, &umr_bitfield_default },
};
static struct umr_bitfield mmDSCL3_DSCL_MEM_PWR_CTRL[] = {
	 { "LUT_MEM_PWR_FORCE", 0, 1, &umr_bitfield_default },
	 { "LUT_MEM_PWR_DIS", 2, 2, &umr_bitfield_default },
	 { "LB_G1_MEM_PWR_FORCE", 4, 5, &umr_bitfield_default },
	 { "LB_G1_MEM_PWR_DIS", 6, 6, &umr_bitfield_default },
	 { "LB_G2_MEM_PWR_FORCE", 8, 9, &umr_bitfield_default },
	 { "LB_G2_MEM_PWR_DIS", 10, 10, &umr_bitfield_default },
	 { "LB_G3_MEM_PWR_FORCE", 12, 13, &umr_bitfield_default },
	 { "LB_G3_MEM_PWR_DIS", 14, 14, &umr_bitfield_default },
	 { "LB_G4_MEM_PWR_FORCE", 16, 17, &umr_bitfield_default },
	 { "LB_G4_MEM_PWR_DIS", 18, 18, &umr_bitfield_default },
	 { "LB_G5_MEM_PWR_FORCE", 20, 21, &umr_bitfield_default },
	 { "LB_G5_MEM_PWR_DIS", 22, 22, &umr_bitfield_default },
	 { "LB_G6_MEM_PWR_FORCE", 24, 25, &umr_bitfield_default },
	 { "LB_G6_MEM_PWR_DIS", 26, 26, &umr_bitfield_default },
};
static struct umr_bitfield mmDSCL3_DSCL_MEM_PWR_STATUS[] = {
	 { "LUT_MEM_PWR_STATE", 0, 1, &umr_bitfield_default },
	 { "LB_G1_MEM_PWR_STATE", 2, 3, &umr_bitfield_default },
	 { "LB_G2_MEM_PWR_STATE", 4, 5, &umr_bitfield_default },
	 { "LB_G3_MEM_PWR_STATE", 6, 7, &umr_bitfield_default },
	 { "LB_G4_MEM_PWR_STATE", 8, 9, &umr_bitfield_default },
	 { "LB_G5_MEM_PWR_STATE", 10, 11, &umr_bitfield_default },
	 { "LB_G6_MEM_PWR_STATE", 12, 13, &umr_bitfield_default },
};
static struct umr_bitfield mmDSCL3_OBUF_CONTROL[] = {
	 { "OBUF_BYPASS", 0, 0, &umr_bitfield_default },
	 { "OBUF_USE_FULL_BUFFER", 4, 4, &umr_bitfield_default },
	 { "OBUF_H_2X_UPSCALE_EN", 8, 8, &umr_bitfield_default },
	 { "OBUF_IS_HALF_RECOUT_WIDTH", 12, 12, &umr_bitfield_default },
	 { "OBUF_H_2X_COEF_PHASE0_SEL", 16, 16, &umr_bitfield_default },
	 { "OBUF_H_2X_COEF_PHASE1_SEL", 24, 24, &umr_bitfield_default },
	 { "OBUF_OUT_HOLD_CNT", 28, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDSCL3_OBUF_MEM_PWR_CTRL[] = {
	 { "OBUF_MEM_PWR_FORCE", 0, 1, &umr_bitfield_default },
	 { "OBUF_MEM_PWR_DIS", 2, 2, &umr_bitfield_default },
	 { "OBUF_MEM_PWR_STATE", 16, 17, &umr_bitfield_default },
};
static struct umr_bitfield mmCM3_CM_CONTROL[] = {
	 { "CM_BYPASS_EN", 0, 0, &umr_bitfield_default },
	 { "CM_UPDATE_PENDING", 8, 8, &umr_bitfield_default },
};
static struct umr_bitfield mmCM3_CM_COMA_C11_C12[] = {
	 { "CM_COMA_C11", 0, 15, &umr_bitfield_default },
	 { "CM_COMA_C12", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmCM3_CM_COMA_C13_C14[] = {
	 { "CM_COMA_C13", 0, 15, &umr_bitfield_default },
	 { "CM_COMA_C14", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmCM3_CM_COMA_C21_C22[] = {
	 { "CM_COMA_C21", 0, 15, &umr_bitfield_default },
	 { "CM_COMA_C22", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmCM3_CM_COMA_C23_C24[] = {
	 { "CM_COMA_C23", 0, 15, &umr_bitfield_default },
	 { "CM_COMA_C24", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmCM3_CM_COMA_C31_C32[] = {
	 { "CM_COMA_C31", 0, 15, &umr_bitfield_default },
	 { "CM_COMA_C32", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmCM3_CM_COMA_C33_C34[] = {
	 { "CM_COMA_C33", 0, 15, &umr_bitfield_default },
	 { "CM_COMA_C34", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmCM3_CM_COMB_C11_C12[] = {
	 { "CM_COMB_C11", 0, 15, &umr_bitfield_default },
	 { "CM_COMB_C12", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmCM3_CM_COMB_C13_C14[] = {
	 { "CM_COMB_C13", 0, 15, &umr_bitfield_default },
	 { "CM_COMB_C14", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmCM3_CM_COMB_C21_C22[] = {
	 { "CM_COMB_C21", 0, 15, &umr_bitfield_default },
	 { "CM_COMB_C22", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmCM3_CM_COMB_C23_C24[] = {
	 { "CM_COMB_C23", 0, 15, &umr_bitfield_default },
	 { "CM_COMB_C24", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmCM3_CM_COMB_C31_C32[] = {
	 { "CM_COMB_C31", 0, 15, &umr_bitfield_default },
	 { "CM_COMB_C32", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmCM3_CM_COMB_C33_C34[] = {
	 { "CM_COMB_C33", 0, 15, &umr_bitfield_default },
	 { "CM_COMB_C34", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmCM3_CM_IGAM_CONTROL[] = {
	 { "CM_IGAM_LUT_MODE", 0, 1, &umr_bitfield_default },
	 { "CM_IGAM_LUT_DATA_SIGNED_EN_B", 2, 2, &umr_bitfield_default },
	 { "CM_IGAM_LUT_DATA_SIGNED_EN_G", 3, 3, &umr_bitfield_default },
	 { "CM_IGAM_LUT_DATA_SIGNED_EN_R", 4, 4, &umr_bitfield_default },
	 { "CM_IGAM_LUT_INC_B", 5, 8, &umr_bitfield_default },
	 { "CM_IGAM_LUT_INC_G", 9, 12, &umr_bitfield_default },
	 { "CM_IGAM_LUT_INC_R", 13, 16, &umr_bitfield_default },
	 { "CM_IGAM_LUT_FORMAT_B", 17, 18, &umr_bitfield_default },
	 { "CM_IGAM_LUT_FORMAT_G", 19, 20, &umr_bitfield_default },
	 { "CM_IGAM_LUT_FORMAT_R", 21, 22, &umr_bitfield_default },
	 { "CM_IGAM_LUT_B_FLOAT_POINT_EN", 23, 23, &umr_bitfield_default },
	 { "CM_IGAM_LUT_G_FLOAT_POINT_EN", 24, 24, &umr_bitfield_default },
	 { "CM_IGAM_LUT_R_FLOAT_POINT_EN", 25, 25, &umr_bitfield_default },
	 { "CM_IGAM_INPUT_FORMAT", 26, 27, &umr_bitfield_default },
};
static struct umr_bitfield mmCM3_CM_IGAM_LUT_RW_CONTROL[] = {
	 { "CM_IGAM_LUT_RW_MODE", 0, 0, &umr_bitfield_default },
	 { "CM_IGAM_LUT_WRITE_EN_MASK", 4, 6, &umr_bitfield_default },
	 { "CM_IGAM_LUT_SEL", 8, 8, &umr_bitfield_default },
	 { "CM_IGAM_LUT_HOST_EN", 12, 12, &umr_bitfield_default },
	 { "CM_IGAM_DGAM_CONFIG_STATUS", 16, 19, &umr_bitfield_default },
};
static struct umr_bitfield mmCM3_CM_IGAM_LUT_RW_INDEX[] = {
	 { "CM_IGAM_LUT_RW_INDEX", 0, 7, &umr_bitfield_default },
};
static struct umr_bitfield mmCM3_CM_IGAM_LUT_SEQ_COLOR[] = {
	 { "CM_IGAM_LUT_SEQ_COLOR", 0, 15, &umr_bitfield_default },
};
static struct umr_bitfield mmCM3_CM_IGAM_LUT_30_COLOR[] = {
	 { "CM_IGAM_LUT_10_BLUE", 0, 9, &umr_bitfield_default },
	 { "CM_IGAM_LUT_10_GREEN", 10, 19, &umr_bitfield_default },
	 { "CM_IGAM_LUT_10_RED", 20, 29, &umr_bitfield_default },
};
static struct umr_bitfield mmCM3_CM_IGAM_LUT_PWL_DATA[] = {
	 { "CM_IGAM_LUT_PWL_BASE", 0, 15, &umr_bitfield_default },
	 { "CM_IGAM_LUT_PWL_DELTA", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmCM3_CM_IGAM_LUT_AUTOFILL[] = {
	 { "CM_IGAM_LUT_AUTOFILL", 0, 0, &umr_bitfield_default },
	 { "CM_IGAM_LUT_AUTOFILL_DONE", 4, 4, &umr_bitfield_default },
};
static struct umr_bitfield mmCM3_CM_IGAM_LUT_BW_OFFSET_BLUE[] = {
	 { "CM_IGAM_LUT_BLACK_OFFSET_BLUE", 0, 15, &umr_bitfield_default },
	 { "CM_IGAM_LUT_WHITE_OFFSET_BLUE", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmCM3_CM_IGAM_LUT_BW_OFFSET_GREEN[] = {
	 { "CM_IGAM_LUT_BLACK_OFFSET_GREEN", 0, 15, &umr_bitfield_default },
	 { "CM_IGAM_LUT_WHITE_OFFSET_GREEN", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmCM3_CM_IGAM_LUT_BW_OFFSET_RED[] = {
	 { "CM_IGAM_LUT_BLACK_OFFSET_RED", 0, 15, &umr_bitfield_default },
	 { "CM_IGAM_LUT_WHITE_OFFSET_RED", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmCM3_CM_ICSC_CONTROL[] = {
	 { "CM_ICSC_MODE", 0, 1, &umr_bitfield_default },
};
static struct umr_bitfield mmCM3_CM_ICSC_C11_C12[] = {
	 { "CM_ICSC_C11", 0, 15, &umr_bitfield_default },
	 { "CM_ICSC_C12", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmCM3_CM_ICSC_C13_C14[] = {
	 { "CM_ICSC_C13", 0, 15, &umr_bitfield_default },
	 { "CM_ICSC_C14", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmCM3_CM_ICSC_C21_C22[] = {
	 { "CM_ICSC_C21", 0, 15, &umr_bitfield_default },
	 { "CM_ICSC_C22", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmCM3_CM_ICSC_C23_C24[] = {
	 { "CM_ICSC_C23", 0, 15, &umr_bitfield_default },
	 { "CM_ICSC_C24", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmCM3_CM_ICSC_C31_C32[] = {
	 { "CM_ICSC_C31", 0, 15, &umr_bitfield_default },
	 { "CM_ICSC_C32", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmCM3_CM_ICSC_C33_C34[] = {
	 { "CM_ICSC_C33", 0, 15, &umr_bitfield_default },
	 { "CM_ICSC_C34", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmCM3_CM_GAMUT_REMAP_CONTROL[] = {
	 { "CM_GAMUT_REMAP_MODE", 0, 1, &umr_bitfield_default },
};
static struct umr_bitfield mmCM3_CM_GAMUT_REMAP_C11_C12[] = {
	 { "CM_GAMUT_REMAP_C11", 0, 15, &umr_bitfield_default },
	 { "CM_GAMUT_REMAP_C12", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmCM3_CM_GAMUT_REMAP_C13_C14[] = {
	 { "CM_GAMUT_REMAP_C13", 0, 15, &umr_bitfield_default },
	 { "CM_GAMUT_REMAP_C14", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmCM3_CM_GAMUT_REMAP_C21_C22[] = {
	 { "CM_GAMUT_REMAP_C21", 0, 15, &umr_bitfield_default },
	 { "CM_GAMUT_REMAP_C22", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmCM3_CM_GAMUT_REMAP_C23_C24[] = {
	 { "CM_GAMUT_REMAP_C23", 0, 15, &umr_bitfield_default },
	 { "CM_GAMUT_REMAP_C24", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmCM3_CM_GAMUT_REMAP_C31_C32[] = {
	 { "CM_GAMUT_REMAP_C31", 0, 15, &umr_bitfield_default },
	 { "CM_GAMUT_REMAP_C32", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmCM3_CM_GAMUT_REMAP_C33_C34[] = {
	 { "CM_GAMUT_REMAP_C33", 0, 15, &umr_bitfield_default },
	 { "CM_GAMUT_REMAP_C34", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmCM3_CM_OCSC_CONTROL[] = {
	 { "CM_OCSC_MODE", 0, 2, &umr_bitfield_default },
};
static struct umr_bitfield mmCM3_CM_OCSC_C11_C12[] = {
	 { "CM_OCSC_C11", 0, 15, &umr_bitfield_default },
	 { "CM_OCSC_C12", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmCM3_CM_OCSC_C13_C14[] = {
	 { "CM_OCSC_C13", 0, 15, &umr_bitfield_default },
	 { "CM_OCSC_C14", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmCM3_CM_OCSC_C21_C22[] = {
	 { "CM_OCSC_C21", 0, 15, &umr_bitfield_default },
	 { "CM_OCSC_C22", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmCM3_CM_OCSC_C23_C24[] = {
	 { "CM_OCSC_C23", 0, 15, &umr_bitfield_default },
	 { "CM_OCSC_C24", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmCM3_CM_OCSC_C31_C32[] = {
	 { "CM_OCSC_C31", 0, 15, &umr_bitfield_default },
	 { "CM_OCSC_C32", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmCM3_CM_OCSC_C33_C34[] = {
	 { "CM_OCSC_C33", 0, 15, &umr_bitfield_default },
	 { "CM_OCSC_C34", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmCM3_CM_BNS_VALUES_R[] = {
	 { "CM_BNS_BIAS_R", 0, 15, &umr_bitfield_default },
	 { "CM_BNS_SCALE_R", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmCM3_CM_BNS_VALUES_G[] = {
	 { "CM_BNS_BIAS_G", 0, 15, &umr_bitfield_default },
	 { "CM_BNS_SCALE_G", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmCM3_CM_BNS_VALUES_B[] = {
	 { "CM_BNS_BIAS_B", 0, 15, &umr_bitfield_default },
	 { "CM_BNS_SCALE_B", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmCM3_CM_DGAM_CONTROL[] = {
	 { "CM_DGAM_LUT_MODE", 0, 2, &umr_bitfield_default },
};
static struct umr_bitfield mmCM3_CM_DGAM_LUT_INDEX[] = {
	 { "CM_DGAM_LUT_INDEX", 0, 8, &umr_bitfield_default },
};
static struct umr_bitfield mmCM3_CM_DGAM_LUT_DATA[] = {
	 { "CM_DGAM_LUT_DATA", 0, 18, &umr_bitfield_default },
};
static struct umr_bitfield mmCM3_CM_DGAM_LUT_WRITE_EN_MASK[] = {
	 { "CM_DGAM_LUT_WRITE_EN_MASK", 0, 2, &umr_bitfield_default },
	 { "CM_DGAM_LUT_WRITE_SEL", 4, 4, &umr_bitfield_default },
};
static struct umr_bitfield mmCM3_CM_DGAM_RAMA_START_CNTL_B[] = {
	 { "CM_DGAM_RAMA_EXP_REGION_START_B", 0, 17, &umr_bitfield_default },
	 { "CM_DGAM_RAMA_EXP_REGION_START_SEGMENT_B", 20, 26, &umr_bitfield_default },
};
static struct umr_bitfield mmCM3_CM_DGAM_RAMA_START_CNTL_G[] = {
	 { "CM_DGAM_RAMA_EXP_REGION_START_G", 0, 17, &umr_bitfield_default },
	 { "CM_DGAM_RAMA_EXP_REGION_START_SEGMENT_G", 20, 26, &umr_bitfield_default },
};
static struct umr_bitfield mmCM3_CM_DGAM_RAMA_START_CNTL_R[] = {
	 { "CM_DGAM_RAMA_EXP_REGION_START_R", 0, 17, &umr_bitfield_default },
	 { "CM_DGAM_RAMA_EXP_REGION_START_SEGMENT_R", 20, 26, &umr_bitfield_default },
};
static struct umr_bitfield mmCM3_CM_DGAM_RAMA_SLOPE_CNTL_B[] = {
	 { "CM_DGAM_RAMA_EXP_REGION_LINEAR_SLOPE_B", 0, 17, &umr_bitfield_default },
};
static struct umr_bitfield mmCM3_CM_DGAM_RAMA_SLOPE_CNTL_G[] = {
	 { "CM_DGAM_RAMA_EXP_REGION_LINEAR_SLOPE_G", 0, 17, &umr_bitfield_default },
};
static struct umr_bitfield mmCM3_CM_DGAM_RAMA_SLOPE_CNTL_R[] = {
	 { "CM_DGAM_RAMA_EXP_REGION_LINEAR_SLOPE_R", 0, 17, &umr_bitfield_default },
};
static struct umr_bitfield mmCM3_CM_DGAM_RAMA_END_CNTL1_B[] = {
	 { "CM_DGAM_RAMA_EXP_REGION_END_B", 0, 15, &umr_bitfield_default },
};
static struct umr_bitfield mmCM3_CM_DGAM_RAMA_END_CNTL2_B[] = {
	 { "CM_DGAM_RAMA_EXP_REGION_END_SLOPE_B", 0, 15, &umr_bitfield_default },
	 { "CM_DGAM_RAMA_EXP_REGION_END_BASE_B", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmCM3_CM_DGAM_RAMA_END_CNTL1_G[] = {
	 { "CM_DGAM_RAMA_EXP_REGION_END_G", 0, 15, &umr_bitfield_default },
};
static struct umr_bitfield mmCM3_CM_DGAM_RAMA_END_CNTL2_G[] = {
	 { "CM_DGAM_RAMA_EXP_REGION_END_SLOPE_G", 0, 15, &umr_bitfield_default },
	 { "CM_DGAM_RAMA_EXP_REGION_END_BASE_G", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmCM3_CM_DGAM_RAMA_END_CNTL1_R[] = {
	 { "CM_DGAM_RAMA_EXP_REGION_END_R", 0, 15, &umr_bitfield_default },
};
static struct umr_bitfield mmCM3_CM_DGAM_RAMA_END_CNTL2_R[] = {
	 { "CM_DGAM_RAMA_EXP_REGION_END_SLOPE_R", 0, 15, &umr_bitfield_default },
	 { "CM_DGAM_RAMA_EXP_REGION_END_BASE_R", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmCM3_CM_DGAM_RAMA_REGION_0_1[] = {
	 { "CM_DGAM_RAMA_EXP_REGION0_LUT_OFFSET", 0, 8, &umr_bitfield_default },
	 { "CM_DGAM_RAMA_EXP_REGION0_NUM_SEGMENTS", 12, 14, &umr_bitfield_default },
	 { "CM_DGAM_RAMA_EXP_REGION1_LUT_OFFSET", 16, 24, &umr_bitfield_default },
	 { "CM_DGAM_RAMA_EXP_REGION1_NUM_SEGMENTS", 28, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmCM3_CM_DGAM_RAMA_REGION_2_3[] = {
	 { "CM_DGAM_RAMA_EXP_REGION2_LUT_OFFSET", 0, 8, &umr_bitfield_default },
	 { "CM_DGAM_RAMA_EXP_REGION2_NUM_SEGMENTS", 12, 14, &umr_bitfield_default },
	 { "CM_DGAM_RAMA_EXP_REGION3_LUT_OFFSET", 16, 24, &umr_bitfield_default },
	 { "CM_DGAM_RAMA_EXP_REGION3_NUM_SEGMENTS", 28, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmCM3_CM_DGAM_RAMA_REGION_4_5[] = {
	 { "CM_DGAM_RAMA_EXP_REGION4_LUT_OFFSET", 0, 8, &umr_bitfield_default },
	 { "CM_DGAM_RAMA_EXP_REGION4_NUM_SEGMENTS", 12, 14, &umr_bitfield_default },
	 { "CM_DGAM_RAMA_EXP_REGION5_LUT_OFFSET", 16, 24, &umr_bitfield_default },
	 { "CM_DGAM_RAMA_EXP_REGION5_NUM_SEGMENTS", 28, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmCM3_CM_DGAM_RAMA_REGION_6_7[] = {
	 { "CM_DGAM_RAMA_EXP_REGION6_LUT_OFFSET", 0, 8, &umr_bitfield_default },
	 { "CM_DGAM_RAMA_EXP_REGION6_NUM_SEGMENTS", 12, 14, &umr_bitfield_default },
	 { "CM_DGAM_RAMA_EXP_REGION7_LUT_OFFSET", 16, 24, &umr_bitfield_default },
	 { "CM_DGAM_RAMA_EXP_REGION7_NUM_SEGMENTS", 28, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmCM3_CM_DGAM_RAMA_REGION_8_9[] = {
	 { "CM_DGAM_RAMA_EXP_REGION8_LUT_OFFSET", 0, 8, &umr_bitfield_default },
	 { "CM_DGAM_RAMA_EXP_REGION8_NUM_SEGMENTS", 12, 14, &umr_bitfield_default },
	 { "CM_DGAM_RAMA_EXP_REGION9_LUT_OFFSET", 16, 24, &umr_bitfield_default },
	 { "CM_DGAM_RAMA_EXP_REGION9_NUM_SEGMENTS", 28, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmCM3_CM_DGAM_RAMA_REGION_10_11[] = {
	 { "CM_DGAM_RAMA_EXP_REGION10_LUT_OFFSET", 0, 8, &umr_bitfield_default },
	 { "CM_DGAM_RAMA_EXP_REGION10_NUM_SEGMENTS", 12, 14, &umr_bitfield_default },
	 { "CM_DGAM_RAMA_EXP_REGION11_LUT_OFFSET", 16, 24, &umr_bitfield_default },
	 { "CM_DGAM_RAMA_EXP_REGION11_NUM_SEGMENTS", 28, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmCM3_CM_DGAM_RAMA_REGION_12_13[] = {
	 { "CM_DGAM_RAMA_EXP_REGION12_LUT_OFFSET", 0, 8, &umr_bitfield_default },
	 { "CM_DGAM_RAMA_EXP_REGION12_NUM_SEGMENTS", 12, 14, &umr_bitfield_default },
	 { "CM_DGAM_RAMA_EXP_REGION13_LUT_OFFSET", 16, 24, &umr_bitfield_default },
	 { "CM_DGAM_RAMA_EXP_REGION13_NUM_SEGMENTS", 28, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmCM3_CM_DGAM_RAMA_REGION_14_15[] = {
	 { "CM_DGAM_RAMA_EXP_REGION14_LUT_OFFSET", 0, 8, &umr_bitfield_default },
	 { "CM_DGAM_RAMA_EXP_REGION14_NUM_SEGMENTS", 12, 14, &umr_bitfield_default },
	 { "CM_DGAM_RAMA_EXP_REGION15_LUT_OFFSET", 16, 24, &umr_bitfield_default },
	 { "CM_DGAM_RAMA_EXP_REGION15_NUM_SEGMENTS", 28, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmCM3_CM_DGAM_RAMB_START_CNTL_B[] = {
	 { "CM_DGAM_RAMB_EXP_REGION_START_B", 0, 17, &umr_bitfield_default },
	 { "CM_DGAM_RAMB_EXP_REGION_START_SEGMENT_B", 20, 26, &umr_bitfield_default },
};
static struct umr_bitfield mmCM3_CM_DGAM_RAMB_START_CNTL_G[] = {
	 { "CM_DGAM_RAMB_EXP_REGION_START_G", 0, 17, &umr_bitfield_default },
	 { "CM_DGAM_RAMB_EXP_REGION_START_SEGMENT_G", 20, 26, &umr_bitfield_default },
};
static struct umr_bitfield mmCM3_CM_DGAM_RAMB_START_CNTL_R[] = {
	 { "CM_DGAM_RAMB_EXP_REGION_START_R", 0, 17, &umr_bitfield_default },
	 { "CM_DGAM_RAMB_EXP_REGION_START_SEGMENT_R", 20, 26, &umr_bitfield_default },
};
static struct umr_bitfield mmCM3_CM_DGAM_RAMB_SLOPE_CNTL_B[] = {
	 { "CM_DGAM_RAMB_EXP_REGION_LINEAR_SLOPE_B", 0, 17, &umr_bitfield_default },
};
static struct umr_bitfield mmCM3_CM_DGAM_RAMB_SLOPE_CNTL_G[] = {
	 { "CM_DGAM_RAMB_EXP_REGION_LINEAR_SLOPE_G", 0, 17, &umr_bitfield_default },
};
static struct umr_bitfield mmCM3_CM_DGAM_RAMB_SLOPE_CNTL_R[] = {
	 { "CM_DGAM_RAMB_EXP_REGION_LINEAR_SLOPE_R", 0, 17, &umr_bitfield_default },
};
static struct umr_bitfield mmCM3_CM_DGAM_RAMB_END_CNTL1_B[] = {
	 { "CM_DGAM_RAMB_EXP_REGION_END_B", 0, 15, &umr_bitfield_default },
};
static struct umr_bitfield mmCM3_CM_DGAM_RAMB_END_CNTL2_B[] = {
	 { "CM_DGAM_RAMB_EXP_REGION_END_SLOPE_B", 0, 15, &umr_bitfield_default },
	 { "CM_DGAM_RAMB_EXP_REGION_END_BASE_B", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmCM3_CM_DGAM_RAMB_END_CNTL1_G[] = {
	 { "CM_DGAM_RAMB_EXP_REGION_END_G", 0, 15, &umr_bitfield_default },
};
static struct umr_bitfield mmCM3_CM_DGAM_RAMB_END_CNTL2_G[] = {
	 { "CM_DGAM_RAMB_EXP_REGION_END_SLOPE_G", 0, 15, &umr_bitfield_default },
	 { "CM_DGAM_RAMB_EXP_REGION_END_BASE_G", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmCM3_CM_DGAM_RAMB_END_CNTL1_R[] = {
	 { "CM_DGAM_RAMB_EXP_REGION_END_R", 0, 15, &umr_bitfield_default },
};
static struct umr_bitfield mmCM3_CM_DGAM_RAMB_END_CNTL2_R[] = {
	 { "CM_DGAM_RAMB_EXP_REGION_END_SLOPE_R", 0, 15, &umr_bitfield_default },
	 { "CM_DGAM_RAMB_EXP_REGION_END_BASE_R", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmCM3_CM_DGAM_RAMB_REGION_0_1[] = {
	 { "CM_DGAM_RAMB_EXP_REGION0_LUT_OFFSET", 0, 8, &umr_bitfield_default },
	 { "CM_DGAM_RAMB_EXP_REGION0_NUM_SEGMENTS", 12, 14, &umr_bitfield_default },
	 { "CM_DGAM_RAMB_EXP_REGION1_LUT_OFFSET", 16, 24, &umr_bitfield_default },
	 { "CM_DGAM_RAMB_EXP_REGION1_NUM_SEGMENTS", 28, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmCM3_CM_DGAM_RAMB_REGION_2_3[] = {
	 { "CM_DGAM_RAMB_EXP_REGION2_LUT_OFFSET", 0, 8, &umr_bitfield_default },
	 { "CM_DGAM_RAMB_EXP_REGION2_NUM_SEGMENTS", 12, 14, &umr_bitfield_default },
	 { "CM_DGAM_RAMB_EXP_REGION3_LUT_OFFSET", 16, 24, &umr_bitfield_default },
	 { "CM_DGAM_RAMB_EXP_REGION3_NUM_SEGMENTS", 28, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmCM3_CM_DGAM_RAMB_REGION_4_5[] = {
	 { "CM_DGAM_RAMB_EXP_REGION4_LUT_OFFSET", 0, 8, &umr_bitfield_default },
	 { "CM_DGAM_RAMB_EXP_REGION4_NUM_SEGMENTS", 12, 14, &umr_bitfield_default },
	 { "CM_DGAM_RAMB_EXP_REGION5_LUT_OFFSET", 16, 24, &umr_bitfield_default },
	 { "CM_DGAM_RAMB_EXP_REGION5_NUM_SEGMENTS", 28, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmCM3_CM_DGAM_RAMB_REGION_6_7[] = {
	 { "CM_DGAM_RAMB_EXP_REGION6_LUT_OFFSET", 0, 8, &umr_bitfield_default },
	 { "CM_DGAM_RAMB_EXP_REGION6_NUM_SEGMENTS", 12, 14, &umr_bitfield_default },
	 { "CM_DGAM_RAMB_EXP_REGION7_LUT_OFFSET", 16, 24, &umr_bitfield_default },
	 { "CM_DGAM_RAMB_EXP_REGION7_NUM_SEGMENTS", 28, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmCM3_CM_DGAM_RAMB_REGION_8_9[] = {
	 { "CM_DGAM_RAMB_EXP_REGION8_LUT_OFFSET", 0, 8, &umr_bitfield_default },
	 { "CM_DGAM_RAMB_EXP_REGION8_NUM_SEGMENTS", 12, 14, &umr_bitfield_default },
	 { "CM_DGAM_RAMB_EXP_REGION9_LUT_OFFSET", 16, 24, &umr_bitfield_default },
	 { "CM_DGAM_RAMB_EXP_REGION9_NUM_SEGMENTS", 28, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmCM3_CM_DGAM_RAMB_REGION_10_11[] = {
	 { "CM_DGAM_RAMB_EXP_REGION10_LUT_OFFSET", 0, 8, &umr_bitfield_default },
	 { "CM_DGAM_RAMB_EXP_REGION10_NUM_SEGMENTS", 12, 14, &umr_bitfield_default },
	 { "CM_DGAM_RAMB_EXP_REGION11_LUT_OFFSET", 16, 24, &umr_bitfield_default },
	 { "CM_DGAM_RAMB_EXP_REGION11_NUM_SEGMENTS", 28, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmCM3_CM_DGAM_RAMB_REGION_12_13[] = {
	 { "CM_DGAM_RAMB_EXP_REGION12_LUT_OFFSET", 0, 8, &umr_bitfield_default },
	 { "CM_DGAM_RAMB_EXP_REGION12_NUM_SEGMENTS", 12, 14, &umr_bitfield_default },
	 { "CM_DGAM_RAMB_EXP_REGION13_LUT_OFFSET", 16, 24, &umr_bitfield_default },
	 { "CM_DGAM_RAMB_EXP_REGION13_NUM_SEGMENTS", 28, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmCM3_CM_DGAM_RAMB_REGION_14_15[] = {
	 { "CM_DGAM_RAMB_EXP_REGION14_LUT_OFFSET", 0, 8, &umr_bitfield_default },
	 { "CM_DGAM_RAMB_EXP_REGION14_NUM_SEGMENTS", 12, 14, &umr_bitfield_default },
	 { "CM_DGAM_RAMB_EXP_REGION15_LUT_OFFSET", 16, 24, &umr_bitfield_default },
	 { "CM_DGAM_RAMB_EXP_REGION15_NUM_SEGMENTS", 28, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmCM3_CM_RGAM_CONTROL[] = {
	 { "CM_RGAM_LUT_MODE", 0, 2, &umr_bitfield_default },
};
static struct umr_bitfield mmCM3_CM_RGAM_LUT_INDEX[] = {
	 { "CM_RGAM_LUT_INDEX", 0, 8, &umr_bitfield_default },
};
static struct umr_bitfield mmCM3_CM_RGAM_LUT_DATA[] = {
	 { "CM_RGAM_LUT_DATA", 0, 18, &umr_bitfield_default },
};
static struct umr_bitfield mmCM3_CM_RGAM_LUT_WRITE_EN_MASK[] = {
	 { "CM_RGAM_LUT_WRITE_EN_MASK", 0, 2, &umr_bitfield_default },
	 { "CM_RGAM_LUT_WRITE_SEL", 4, 4, &umr_bitfield_default },
	 { "CM_RGAM_CONFIG_STATUS", 8, 10, &umr_bitfield_default },
};
static struct umr_bitfield mmCM3_CM_RGAM_RAMA_START_CNTL_B[] = {
	 { "CM_RGAM_RAMA_EXP_REGION_START_B", 0, 17, &umr_bitfield_default },
	 { "CM_RGAM_RAMA_EXP_REGION_START_SEGMENT_B", 20, 26, &umr_bitfield_default },
};
static struct umr_bitfield mmCM3_CM_RGAM_RAMA_START_CNTL_G[] = {
	 { "CM_RGAM_RAMA_EXP_REGION_START_G", 0, 17, &umr_bitfield_default },
	 { "CM_RGAM_RAMA_EXP_REGION_START_SEGMENT_G", 20, 26, &umr_bitfield_default },
};
static struct umr_bitfield mmCM3_CM_RGAM_RAMA_START_CNTL_R[] = {
	 { "CM_RGAM_RAMA_EXP_REGION_START_R", 0, 17, &umr_bitfield_default },
	 { "CM_RGAM_RAMA_EXP_REGION_START_SEGMENT_R", 20, 26, &umr_bitfield_default },
};
static struct umr_bitfield mmCM3_CM_RGAM_RAMA_SLOPE_CNTL_B[] = {
	 { "CM_RGAM_RAMA_EXP_REGION_LINEAR_SLOPE_B", 0, 17, &umr_bitfield_default },
};
static struct umr_bitfield mmCM3_CM_RGAM_RAMA_SLOPE_CNTL_G[] = {
	 { "CM_RGAM_RAMA_EXP_REGION_LINEAR_SLOPE_G", 0, 17, &umr_bitfield_default },
};
static struct umr_bitfield mmCM3_CM_RGAM_RAMA_SLOPE_CNTL_R[] = {
	 { "CM_RGAM_RAMA_EXP_REGION_LINEAR_SLOPE_R", 0, 17, &umr_bitfield_default },
};
static struct umr_bitfield mmCM3_CM_RGAM_RAMA_END_CNTL1_B[] = {
	 { "CM_RGAM_RAMA_EXP_REGION_END_B", 0, 15, &umr_bitfield_default },
};
static struct umr_bitfield mmCM3_CM_RGAM_RAMA_END_CNTL2_B[] = {
	 { "CM_RGAM_RAMA_EXP_REGION_END_SLOPE_B", 0, 15, &umr_bitfield_default },
	 { "CM_RGAM_RAMA_EXP_REGION_END_BASE_B", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmCM3_CM_RGAM_RAMA_END_CNTL1_G[] = {
	 { "CM_RGAM_RAMA_EXP_REGION_END_G", 0, 15, &umr_bitfield_default },
};
static struct umr_bitfield mmCM3_CM_RGAM_RAMA_END_CNTL2_G[] = {
	 { "CM_RGAM_RAMA_EXP_REGION_END_SLOPE_G", 0, 15, &umr_bitfield_default },
	 { "CM_RGAM_RAMA_EXP_REGION_END_BASE_G", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmCM3_CM_RGAM_RAMA_END_CNTL1_R[] = {
	 { "CM_RGAM_RAMA_EXP_REGION_END_R", 0, 15, &umr_bitfield_default },
};
static struct umr_bitfield mmCM3_CM_RGAM_RAMA_END_CNTL2_R[] = {
	 { "CM_RGAM_RAMA_EXP_REGION_END_SLOPE_R", 0, 15, &umr_bitfield_default },
	 { "CM_RGAM_RAMA_EXP_REGION_END_BASE_R", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmCM3_CM_RGAM_RAMA_REGION_0_1[] = {
	 { "CM_RGAM_RAMA_EXP_REGION0_LUT_OFFSET", 0, 8, &umr_bitfield_default },
	 { "CM_RGAM_RAMA_EXP_REGION0_NUM_SEGMENTS", 12, 14, &umr_bitfield_default },
	 { "CM_RGAM_RAMA_EXP_REGION1_LUT_OFFSET", 16, 24, &umr_bitfield_default },
	 { "CM_RGAM_RAMA_EXP_REGION1_NUM_SEGMENTS", 28, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmCM3_CM_RGAM_RAMA_REGION_2_3[] = {
	 { "CM_RGAM_RAMA_EXP_REGION2_LUT_OFFSET", 0, 8, &umr_bitfield_default },
	 { "CM_RGAM_RAMA_EXP_REGION2_NUM_SEGMENTS", 12, 14, &umr_bitfield_default },
	 { "CM_RGAM_RAMA_EXP_REGION3_LUT_OFFSET", 16, 24, &umr_bitfield_default },
	 { "CM_RGAM_RAMA_EXP_REGION3_NUM_SEGMENTS", 28, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmCM3_CM_RGAM_RAMA_REGION_4_5[] = {
	 { "CM_RGAM_RAMA_EXP_REGION4_LUT_OFFSET", 0, 8, &umr_bitfield_default },
	 { "CM_RGAM_RAMA_EXP_REGION4_NUM_SEGMENTS", 12, 14, &umr_bitfield_default },
	 { "CM_RGAM_RAMA_EXP_REGION5_LUT_OFFSET", 16, 24, &umr_bitfield_default },
	 { "CM_RGAM_RAMA_EXP_REGION5_NUM_SEGMENTS", 28, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmCM3_CM_RGAM_RAMA_REGION_6_7[] = {
	 { "CM_RGAM_RAMA_EXP_REGION6_LUT_OFFSET", 0, 8, &umr_bitfield_default },
	 { "CM_RGAM_RAMA_EXP_REGION6_NUM_SEGMENTS", 12, 14, &umr_bitfield_default },
	 { "CM_RGAM_RAMA_EXP_REGION7_LUT_OFFSET", 16, 24, &umr_bitfield_default },
	 { "CM_RGAM_RAMA_EXP_REGION7_NUM_SEGMENTS", 28, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmCM3_CM_RGAM_RAMA_REGION_8_9[] = {
	 { "CM_RGAM_RAMA_EXP_REGION8_LUT_OFFSET", 0, 8, &umr_bitfield_default },
	 { "CM_RGAM_RAMA_EXP_REGION8_NUM_SEGMENTS", 12, 14, &umr_bitfield_default },
	 { "CM_RGAM_RAMA_EXP_REGION9_LUT_OFFSET", 16, 24, &umr_bitfield_default },
	 { "CM_RGAM_RAMA_EXP_REGION9_NUM_SEGMENTS", 28, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmCM3_CM_RGAM_RAMA_REGION_10_11[] = {
	 { "CM_RGAM_RAMA_EXP_REGION10_LUT_OFFSET", 0, 8, &umr_bitfield_default },
	 { "CM_RGAM_RAMA_EXP_REGION10_NUM_SEGMENTS", 12, 14, &umr_bitfield_default },
	 { "CM_RGAM_RAMA_EXP_REGION11_LUT_OFFSET", 16, 24, &umr_bitfield_default },
	 { "CM_RGAM_RAMA_EXP_REGION11_NUM_SEGMENTS", 28, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmCM3_CM_RGAM_RAMA_REGION_12_13[] = {
	 { "CM_RGAM_RAMA_EXP_REGION12_LUT_OFFSET", 0, 8, &umr_bitfield_default },
	 { "CM_RGAM_RAMA_EXP_REGION12_NUM_SEGMENTS", 12, 14, &umr_bitfield_default },
	 { "CM_RGAM_RAMA_EXP_REGION13_LUT_OFFSET", 16, 24, &umr_bitfield_default },
	 { "CM_RGAM_RAMA_EXP_REGION13_NUM_SEGMENTS", 28, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmCM3_CM_RGAM_RAMA_REGION_14_15[] = {
	 { "CM_RGAM_RAMA_EXP_REGION14_LUT_OFFSET", 0, 8, &umr_bitfield_default },
	 { "CM_RGAM_RAMA_EXP_REGION14_NUM_SEGMENTS", 12, 14, &umr_bitfield_default },
	 { "CM_RGAM_RAMA_EXP_REGION15_LUT_OFFSET", 16, 24, &umr_bitfield_default },
	 { "CM_RGAM_RAMA_EXP_REGION15_NUM_SEGMENTS", 28, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmCM3_CM_RGAM_RAMA_REGION_16_17[] = {
	 { "CM_RGAM_RAMA_EXP_REGION16_LUT_OFFSET", 0, 8, &umr_bitfield_default },
	 { "CM_RGAM_RAMA_EXP_REGION16_NUM_SEGMENTS", 12, 14, &umr_bitfield_default },
	 { "CM_RGAM_RAMA_EXP_REGION17_LUT_OFFSET", 16, 24, &umr_bitfield_default },
	 { "CM_RGAM_RAMA_EXP_REGION17_NUM_SEGMENTS", 28, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmCM3_CM_RGAM_RAMA_REGION_18_19[] = {
	 { "CM_RGAM_RAMA_EXP_REGION18_LUT_OFFSET", 0, 8, &umr_bitfield_default },
	 { "CM_RGAM_RAMA_EXP_REGION18_NUM_SEGMENTS", 12, 14, &umr_bitfield_default },
	 { "CM_RGAM_RAMA_EXP_REGION19_LUT_OFFSET", 16, 24, &umr_bitfield_default },
	 { "CM_RGAM_RAMA_EXP_REGION19_NUM_SEGMENTS", 28, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmCM3_CM_RGAM_RAMA_REGION_20_21[] = {
	 { "CM_RGAM_RAMA_EXP_REGION20_LUT_OFFSET", 0, 8, &umr_bitfield_default },
	 { "CM_RGAM_RAMA_EXP_REGION20_NUM_SEGMENTS", 12, 14, &umr_bitfield_default },
	 { "CM_RGAM_RAMA_EXP_REGION21_LUT_OFFSET", 16, 24, &umr_bitfield_default },
	 { "CM_RGAM_RAMA_EXP_REGION21_NUM_SEGMENTS", 28, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmCM3_CM_RGAM_RAMA_REGION_22_23[] = {
	 { "CM_RGAM_RAMA_EXP_REGION22_LUT_OFFSET", 0, 8, &umr_bitfield_default },
	 { "CM_RGAM_RAMA_EXP_REGION22_NUM_SEGMENTS", 12, 14, &umr_bitfield_default },
	 { "CM_RGAM_RAMA_EXP_REGION23_LUT_OFFSET", 16, 24, &umr_bitfield_default },
	 { "CM_RGAM_RAMA_EXP_REGION23_NUM_SEGMENTS", 28, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmCM3_CM_RGAM_RAMA_REGION_24_25[] = {
	 { "CM_RGAM_RAMA_EXP_REGION24_LUT_OFFSET", 0, 8, &umr_bitfield_default },
	 { "CM_RGAM_RAMA_EXP_REGION24_NUM_SEGMENTS", 12, 14, &umr_bitfield_default },
	 { "CM_RGAM_RAMA_EXP_REGION25_LUT_OFFSET", 16, 24, &umr_bitfield_default },
	 { "CM_RGAM_RAMA_EXP_REGION25_NUM_SEGMENTS", 28, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmCM3_CM_RGAM_RAMA_REGION_26_27[] = {
	 { "CM_RGAM_RAMA_EXP_REGION26_LUT_OFFSET", 0, 8, &umr_bitfield_default },
	 { "CM_RGAM_RAMA_EXP_REGION26_NUM_SEGMENTS", 12, 14, &umr_bitfield_default },
	 { "CM_RGAM_RAMA_EXP_REGION27_LUT_OFFSET", 16, 24, &umr_bitfield_default },
	 { "CM_RGAM_RAMA_EXP_REGION27_NUM_SEGMENTS", 28, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmCM3_CM_RGAM_RAMA_REGION_28_29[] = {
	 { "CM_RGAM_RAMA_EXP_REGION28_LUT_OFFSET", 0, 8, &umr_bitfield_default },
	 { "CM_RGAM_RAMA_EXP_REGION28_NUM_SEGMENTS", 12, 14, &umr_bitfield_default },
	 { "CM_RGAM_RAMA_EXP_REGION29_LUT_OFFSET", 16, 24, &umr_bitfield_default },
	 { "CM_RGAM_RAMA_EXP_REGION29_NUM_SEGMENTS", 28, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmCM3_CM_RGAM_RAMA_REGION_30_31[] = {
	 { "CM_RGAM_RAMA_EXP_REGION30_LUT_OFFSET", 0, 8, &umr_bitfield_default },
	 { "CM_RGAM_RAMA_EXP_REGION30_NUM_SEGMENTS", 12, 14, &umr_bitfield_default },
	 { "CM_RGAM_RAMA_EXP_REGION31_LUT_OFFSET", 16, 24, &umr_bitfield_default },
	 { "CM_RGAM_RAMA_EXP_REGION31_NUM_SEGMENTS", 28, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmCM3_CM_RGAM_RAMA_REGION_32_33[] = {
	 { "CM_RGAM_RAMA_EXP_REGION32_LUT_OFFSET", 0, 8, &umr_bitfield_default },
	 { "CM_RGAM_RAMA_EXP_REGION32_NUM_SEGMENTS", 12, 14, &umr_bitfield_default },
	 { "CM_RGAM_RAMA_EXP_REGION33_LUT_OFFSET", 16, 24, &umr_bitfield_default },
	 { "CM_RGAM_RAMA_EXP_REGION33_NUM_SEGMENTS", 28, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmCM3_CM_RGAM_RAMB_START_CNTL_B[] = {
	 { "CM_RGAM_RAMB_EXP_REGION_START_B", 0, 17, &umr_bitfield_default },
	 { "CM_RGAM_RAMB_EXP_REGION_START_SEGMENT_B", 20, 26, &umr_bitfield_default },
};
static struct umr_bitfield mmCM3_CM_RGAM_RAMB_START_CNTL_G[] = {
	 { "CM_RGAM_RAMB_EXP_REGION_START_G", 0, 17, &umr_bitfield_default },
	 { "CM_RGAM_RAMB_EXP_REGION_START_SEGMENT_G", 20, 26, &umr_bitfield_default },
};
static struct umr_bitfield mmCM3_CM_RGAM_RAMB_START_CNTL_R[] = {
	 { "CM_RGAM_RAMB_EXP_REGION_START_R", 0, 17, &umr_bitfield_default },
	 { "CM_RGAM_RAMB_EXP_REGION_START_SEGMENT_R", 20, 26, &umr_bitfield_default },
};
static struct umr_bitfield mmCM3_CM_RGAM_RAMB_SLOPE_CNTL_B[] = {
	 { "CM_RGAM_RAMB_EXP_REGION_LINEAR_SLOPE_B", 0, 17, &umr_bitfield_default },
};
static struct umr_bitfield mmCM3_CM_RGAM_RAMB_SLOPE_CNTL_G[] = {
	 { "CM_RGAM_RAMB_EXP_REGION_LINEAR_SLOPE_G", 0, 17, &umr_bitfield_default },
};
static struct umr_bitfield mmCM3_CM_RGAM_RAMB_SLOPE_CNTL_R[] = {
	 { "CM_RGAM_RAMB_EXP_REGION_LINEAR_SLOPE_R", 0, 17, &umr_bitfield_default },
};
static struct umr_bitfield mmCM3_CM_RGAM_RAMB_END_CNTL1_B[] = {
	 { "CM_RGAM_RAMB_EXP_REGION_END_B", 0, 15, &umr_bitfield_default },
};
static struct umr_bitfield mmCM3_CM_RGAM_RAMB_END_CNTL2_B[] = {
	 { "CM_RGAM_RAMB_EXP_REGION_END_SLOPE_B", 0, 15, &umr_bitfield_default },
	 { "CM_RGAM_RAMB_EXP_REGION_END_BASE_B", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmCM3_CM_RGAM_RAMB_END_CNTL1_G[] = {
	 { "CM_RGAM_RAMB_EXP_REGION_END_G", 0, 15, &umr_bitfield_default },
};
static struct umr_bitfield mmCM3_CM_RGAM_RAMB_END_CNTL2_G[] = {
	 { "CM_RGAM_RAMB_EXP_REGION_END_SLOPE_G", 0, 15, &umr_bitfield_default },
	 { "CM_RGAM_RAMB_EXP_REGION_END_BASE_G", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmCM3_CM_RGAM_RAMB_END_CNTL1_R[] = {
	 { "CM_RGAM_RAMB_EXP_REGION_END_R", 0, 15, &umr_bitfield_default },
};
static struct umr_bitfield mmCM3_CM_RGAM_RAMB_END_CNTL2_R[] = {
	 { "CM_RGAM_RAMB_EXP_REGION_END_SLOPE_R", 0, 15, &umr_bitfield_default },
	 { "CM_RGAM_RAMB_EXP_REGION_END_BASE_R", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmCM3_CM_RGAM_RAMB_REGION_0_1[] = {
	 { "CM_RGAM_RAMB_EXP_REGION0_LUT_OFFSET", 0, 8, &umr_bitfield_default },
	 { "CM_RGAM_RAMB_EXP_REGION0_NUM_SEGMENTS", 12, 14, &umr_bitfield_default },
	 { "CM_RGAM_RAMB_EXP_REGION1_LUT_OFFSET", 16, 24, &umr_bitfield_default },
	 { "CM_RGAM_RAMB_EXP_REGION1_NUM_SEGMENTS", 28, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmCM3_CM_RGAM_RAMB_REGION_2_3[] = {
	 { "CM_RGAM_RAMB_EXP_REGION2_LUT_OFFSET", 0, 8, &umr_bitfield_default },
	 { "CM_RGAM_RAMB_EXP_REGION2_NUM_SEGMENTS", 12, 14, &umr_bitfield_default },
	 { "CM_RGAM_RAMB_EXP_REGION3_LUT_OFFSET", 16, 24, &umr_bitfield_default },
	 { "CM_RGAM_RAMB_EXP_REGION3_NUM_SEGMENTS", 28, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmCM3_CM_RGAM_RAMB_REGION_4_5[] = {
	 { "CM_RGAM_RAMB_EXP_REGION4_LUT_OFFSET", 0, 8, &umr_bitfield_default },
	 { "CM_RGAM_RAMB_EXP_REGION4_NUM_SEGMENTS", 12, 14, &umr_bitfield_default },
	 { "CM_RGAM_RAMB_EXP_REGION5_LUT_OFFSET", 16, 24, &umr_bitfield_default },
	 { "CM_RGAM_RAMB_EXP_REGION5_NUM_SEGMENTS", 28, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmCM3_CM_RGAM_RAMB_REGION_6_7[] = {
	 { "CM_RGAM_RAMB_EXP_REGION6_LUT_OFFSET", 0, 8, &umr_bitfield_default },
	 { "CM_RGAM_RAMB_EXP_REGION6_NUM_SEGMENTS", 12, 14, &umr_bitfield_default },
	 { "CM_RGAM_RAMB_EXP_REGION7_LUT_OFFSET", 16, 24, &umr_bitfield_default },
	 { "CM_RGAM_RAMB_EXP_REGION7_NUM_SEGMENTS", 28, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmCM3_CM_RGAM_RAMB_REGION_8_9[] = {
	 { "CM_RGAM_RAMB_EXP_REGION8_LUT_OFFSET", 0, 8, &umr_bitfield_default },
	 { "CM_RGAM_RAMB_EXP_REGION8_NUM_SEGMENTS", 12, 14, &umr_bitfield_default },
	 { "CM_RGAM_RAMB_EXP_REGION9_LUT_OFFSET", 16, 24, &umr_bitfield_default },
	 { "CM_RGAM_RAMB_EXP_REGION9_NUM_SEGMENTS", 28, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmCM3_CM_RGAM_RAMB_REGION_10_11[] = {
	 { "CM_RGAM_RAMB_EXP_REGION10_LUT_OFFSET", 0, 8, &umr_bitfield_default },
	 { "CM_RGAM_RAMB_EXP_REGION10_NUM_SEGMENTS", 12, 14, &umr_bitfield_default },
	 { "CM_RGAM_RAMB_EXP_REGION11_LUT_OFFSET", 16, 24, &umr_bitfield_default },
	 { "CM_RGAM_RAMB_EXP_REGION11_NUM_SEGMENTS", 28, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmCM3_CM_RGAM_RAMB_REGION_12_13[] = {
	 { "CM_RGAM_RAMB_EXP_REGION12_LUT_OFFSET", 0, 8, &umr_bitfield_default },
	 { "CM_RGAM_RAMB_EXP_REGION12_NUM_SEGMENTS", 12, 14, &umr_bitfield_default },
	 { "CM_RGAM_RAMB_EXP_REGION13_LUT_OFFSET", 16, 24, &umr_bitfield_default },
	 { "CM_RGAM_RAMB_EXP_REGION13_NUM_SEGMENTS", 28, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmCM3_CM_RGAM_RAMB_REGION_14_15[] = {
	 { "CM_RGAM_RAMB_EXP_REGION14_LUT_OFFSET", 0, 8, &umr_bitfield_default },
	 { "CM_RGAM_RAMB_EXP_REGION14_NUM_SEGMENTS", 12, 14, &umr_bitfield_default },
	 { "CM_RGAM_RAMB_EXP_REGION15_LUT_OFFSET", 16, 24, &umr_bitfield_default },
	 { "CM_RGAM_RAMB_EXP_REGION15_NUM_SEGMENTS", 28, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmCM3_CM_RGAM_RAMB_REGION_16_17[] = {
	 { "CM_RGAM_RAMB_EXP_REGION16_LUT_OFFSET", 0, 8, &umr_bitfield_default },
	 { "CM_RGAM_RAMB_EXP_REGION16_NUM_SEGMENTS", 12, 14, &umr_bitfield_default },
	 { "CM_RGAM_RAMB_EXP_REGION17_LUT_OFFSET", 16, 24, &umr_bitfield_default },
	 { "CM_RGAM_RAMB_EXP_REGION17_NUM_SEGMENTS", 28, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmCM3_CM_RGAM_RAMB_REGION_18_19[] = {
	 { "CM_RGAM_RAMB_EXP_REGION18_LUT_OFFSET", 0, 8, &umr_bitfield_default },
	 { "CM_RGAM_RAMB_EXP_REGION18_NUM_SEGMENTS", 12, 14, &umr_bitfield_default },
	 { "CM_RGAM_RAMB_EXP_REGION19_LUT_OFFSET", 16, 24, &umr_bitfield_default },
	 { "CM_RGAM_RAMB_EXP_REGION19_NUM_SEGMENTS", 28, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmCM3_CM_RGAM_RAMB_REGION_20_21[] = {
	 { "CM_RGAM_RAMB_EXP_REGION20_LUT_OFFSET", 0, 8, &umr_bitfield_default },
	 { "CM_RGAM_RAMB_EXP_REGION20_NUM_SEGMENTS", 12, 14, &umr_bitfield_default },
	 { "CM_RGAM_RAMB_EXP_REGION21_LUT_OFFSET", 16, 24, &umr_bitfield_default },
	 { "CM_RGAM_RAMB_EXP_REGION21_NUM_SEGMENTS", 28, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmCM3_CM_RGAM_RAMB_REGION_22_23[] = {
	 { "CM_RGAM_RAMB_EXP_REGION22_LUT_OFFSET", 0, 8, &umr_bitfield_default },
	 { "CM_RGAM_RAMB_EXP_REGION22_NUM_SEGMENTS", 12, 14, &umr_bitfield_default },
	 { "CM_RGAM_RAMB_EXP_REGION23_LUT_OFFSET", 16, 24, &umr_bitfield_default },
	 { "CM_RGAM_RAMB_EXP_REGION23_NUM_SEGMENTS", 28, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmCM3_CM_RGAM_RAMB_REGION_24_25[] = {
	 { "CM_RGAM_RAMB_EXP_REGION24_LUT_OFFSET", 0, 8, &umr_bitfield_default },
	 { "CM_RGAM_RAMB_EXP_REGION24_NUM_SEGMENTS", 12, 14, &umr_bitfield_default },
	 { "CM_RGAM_RAMB_EXP_REGION25_LUT_OFFSET", 16, 24, &umr_bitfield_default },
	 { "CM_RGAM_RAMB_EXP_REGION25_NUM_SEGMENTS", 28, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmCM3_CM_RGAM_RAMB_REGION_26_27[] = {
	 { "CM_RGAM_RAMB_EXP_REGION26_LUT_OFFSET", 0, 8, &umr_bitfield_default },
	 { "CM_RGAM_RAMB_EXP_REGION26_NUM_SEGMENTS", 12, 14, &umr_bitfield_default },
	 { "CM_RGAM_RAMB_EXP_REGION27_LUT_OFFSET", 16, 24, &umr_bitfield_default },
	 { "CM_RGAM_RAMB_EXP_REGION27_NUM_SEGMENTS", 28, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmCM3_CM_RGAM_RAMB_REGION_28_29[] = {
	 { "CM_RGAM_RAMB_EXP_REGION28_LUT_OFFSET", 0, 8, &umr_bitfield_default },
	 { "CM_RGAM_RAMB_EXP_REGION28_NUM_SEGMENTS", 12, 14, &umr_bitfield_default },
	 { "CM_RGAM_RAMB_EXP_REGION29_LUT_OFFSET", 16, 24, &umr_bitfield_default },
	 { "CM_RGAM_RAMB_EXP_REGION29_NUM_SEGMENTS", 28, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmCM3_CM_RGAM_RAMB_REGION_30_31[] = {
	 { "CM_RGAM_RAMB_EXP_REGION30_LUT_OFFSET", 0, 8, &umr_bitfield_default },
	 { "CM_RGAM_RAMB_EXP_REGION30_NUM_SEGMENTS", 12, 14, &umr_bitfield_default },
	 { "CM_RGAM_RAMB_EXP_REGION31_LUT_OFFSET", 16, 24, &umr_bitfield_default },
	 { "CM_RGAM_RAMB_EXP_REGION31_NUM_SEGMENTS", 28, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmCM3_CM_RGAM_RAMB_REGION_32_33[] = {
	 { "CM_RGAM_RAMB_EXP_REGION32_LUT_OFFSET", 0, 8, &umr_bitfield_default },
	 { "CM_RGAM_RAMB_EXP_REGION32_NUM_SEGMENTS", 12, 14, &umr_bitfield_default },
	 { "CM_RGAM_RAMB_EXP_REGION33_LUT_OFFSET", 16, 24, &umr_bitfield_default },
	 { "CM_RGAM_RAMB_EXP_REGION33_NUM_SEGMENTS", 28, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmCM3_CM_HDR_MULT_COEF[] = {
	 { "CM_HDR_MULT_COEF", 0, 18, &umr_bitfield_default },
};
static struct umr_bitfield mmCM3_CM_RANGE_CLAMP_CONTROL_R[] = {
	 { "CM_RANGE_CLAMP_MAX_R", 0, 15, &umr_bitfield_default },
	 { "CM_RANGE_CLAMP_MIN_R", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmCM3_CM_RANGE_CLAMP_CONTROL_G[] = {
	 { "CM_RANGE_CLAMP_MAX_G", 0, 15, &umr_bitfield_default },
	 { "CM_RANGE_CLAMP_MIN_G", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmCM3_CM_RANGE_CLAMP_CONTROL_B[] = {
	 { "CM_RANGE_CLAMP_MAX_B", 0, 15, &umr_bitfield_default },
	 { "CM_RANGE_CLAMP_MIN_B", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmCM3_CM_DENORM_CONTROL[] = {
	 { "CM_DENORM_MODE", 0, 2, &umr_bitfield_default },
	 { "CM_DENORM_ROUND_CLAMP", 4, 4, &umr_bitfield_default },
};
static struct umr_bitfield mmCM3_CM_CMOUT_CONTROL[] = {
	 { "CM_CMOUT_ROUND_TRUNC_MODE", 0, 3, &umr_bitfield_default },
	 { "CM_CMOUT_SPATIAL_DITHER_EN", 4, 4, &umr_bitfield_default },
	 { "CM_CMOUT_SPATIAL_DITHER_MODE", 8, 9, &umr_bitfield_default },
	 { "CM_CMOUT_SPATIAL_DITHER_DEPTH", 12, 13, &umr_bitfield_default },
	 { "CM_CMOUT_FRAME_RANDOM_ENABLE", 16, 16, &umr_bitfield_default },
	 { "CM_CMOUT_RGB_RANDOM_EN", 20, 20, &umr_bitfield_default },
	 { "CM_CMOUT_HIGHPASS_RANDOM_ENABLE", 24, 24, &umr_bitfield_default },
};
static struct umr_bitfield mmCM3_CM_CMOUT_RANDOM_SEEDS[] = {
	 { "CM_CMOUT_RAND_R_SEED", 0, 7, &umr_bitfield_default },
	 { "CM_CMOUT_RAND_G_SEED", 8, 15, &umr_bitfield_default },
	 { "CM_CMOUT_RAND_B_SEED", 16, 23, &umr_bitfield_default },
};
static struct umr_bitfield mmCM3_CM_MEM_PWR_CTRL[] = {
	 { "SHARED_MEM_PWR_FORCE", 0, 1, &umr_bitfield_default },
	 { "SHARED_MEM_PWR_DIS", 2, 2, &umr_bitfield_default },
	 { "RGAM_MEM_PWR_FORCE", 4, 5, &umr_bitfield_default },
	 { "RGAM_MEM_PWR_DIS", 6, 6, &umr_bitfield_default },
};
static struct umr_bitfield mmCM3_CM_MEM_PWR_STATUS[] = {
	 { "SHARED_MEM_PWR_STATE", 0, 1, &umr_bitfield_default },
	 { "RGAM_MEM_PWR_STATE", 2, 3, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_PERFMON15_PERFCOUNTER_CNTL[] = {
	 { "PERFCOUNTER_EVENT_SEL", 0, 8, &umr_bitfield_default },
	 { "PERFCOUNTER_CVALUE_SEL", 9, 11, &umr_bitfield_default },
	 { "PERFCOUNTER_INC_MODE", 12, 14, &umr_bitfield_default },
	 { "PERFCOUNTER_HW_CNTL_SEL", 15, 15, &umr_bitfield_default },
	 { "PERFCOUNTER_RUNEN_MODE", 16, 16, &umr_bitfield_default },
	 { "PERFCOUNTER_CNTOFF_START_DIS", 22, 22, &umr_bitfield_default },
	 { "PERFCOUNTER_RESTART_EN", 23, 23, &umr_bitfield_default },
	 { "PERFCOUNTER_INT_EN", 24, 24, &umr_bitfield_default },
	 { "PERFCOUNTER_OFF_MASK", 25, 25, &umr_bitfield_default },
	 { "PERFCOUNTER_ACTIVE", 26, 26, &umr_bitfield_default },
	 { "PERFCOUNTER_CNTL_SEL", 29, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_PERFMON15_PERFCOUNTER_CNTL2[] = {
	 { "PERFCOUNTER_COUNTED_VALUE_TYPE", 0, 1, &umr_bitfield_default },
	 { "PERFCOUNTER_HW_STOP1_SEL", 2, 2, &umr_bitfield_default },
	 { "PERFCOUNTER_HW_STOP2_SEL", 3, 3, &umr_bitfield_default },
	 { "PERFCOUNTER_CNTOFF_SEL", 8, 13, &umr_bitfield_default },
	 { "PERFCOUNTER_CNTL2_SEL", 29, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_PERFMON15_PERFCOUNTER_STATE[] = {
	 { "PERFCOUNTER_CNT0_STATE", 0, 1, &umr_bitfield_default },
	 { "PERFCOUNTER_STATE_SEL0", 2, 2, &umr_bitfield_default },
	 { "PERFCOUNTER_CNT1_STATE", 4, 5, &umr_bitfield_default },
	 { "PERFCOUNTER_STATE_SEL1", 6, 6, &umr_bitfield_default },
	 { "PERFCOUNTER_CNT2_STATE", 8, 9, &umr_bitfield_default },
	 { "PERFCOUNTER_STATE_SEL2", 10, 10, &umr_bitfield_default },
	 { "PERFCOUNTER_CNT3_STATE", 12, 13, &umr_bitfield_default },
	 { "PERFCOUNTER_STATE_SEL3", 14, 14, &umr_bitfield_default },
	 { "PERFCOUNTER_CNT4_STATE", 16, 17, &umr_bitfield_default },
	 { "PERFCOUNTER_STATE_SEL4", 18, 18, &umr_bitfield_default },
	 { "PERFCOUNTER_CNT5_STATE", 20, 21, &umr_bitfield_default },
	 { "PERFCOUNTER_STATE_SEL5", 22, 22, &umr_bitfield_default },
	 { "PERFCOUNTER_CNT6_STATE", 24, 25, &umr_bitfield_default },
	 { "PERFCOUNTER_STATE_SEL6", 26, 26, &umr_bitfield_default },
	 { "PERFCOUNTER_CNT7_STATE", 28, 29, &umr_bitfield_default },
	 { "PERFCOUNTER_STATE_SEL7", 30, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_PERFMON15_PERFMON_CNTL[] = {
	 { "PERFMON_STATE", 0, 1, &umr_bitfield_default },
	 { "PERFMON_RPT_COUNT", 8, 27, &umr_bitfield_default },
	 { "PERFMON_CNTOFF_AND_OR", 28, 28, &umr_bitfield_default },
	 { "PERFMON_CNTOFF_INT_EN", 29, 29, &umr_bitfield_default },
	 { "PERFMON_CNTOFF_INT_STATUS", 30, 30, &umr_bitfield_default },
	 { "PERFMON_CNTOFF_INT_ACK", 31, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_PERFMON15_PERFMON_CNTL2[] = {
	 { "PERFMON_CNTOFF_INT_TYPE", 0, 0, &umr_bitfield_default },
	 { "PERFMON_CLK_ENABLE", 1, 1, &umr_bitfield_default },
	 { "PERFMON_RUN_ENABLE_START_SEL", 2, 9, &umr_bitfield_default },
	 { "PERFMON_RUN_ENABLE_STOP_SEL", 10, 17, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_PERFMON15_PERFMON_CVALUE_INT_MISC[] = {
	 { "PERFCOUNTER_INT0_STATUS", 0, 0, &umr_bitfield_default },
	 { "PERFCOUNTER_INT1_STATUS", 1, 1, &umr_bitfield_default },
	 { "PERFCOUNTER_INT2_STATUS", 2, 2, &umr_bitfield_default },
	 { "PERFCOUNTER_INT3_STATUS", 3, 3, &umr_bitfield_default },
	 { "PERFCOUNTER_INT4_STATUS", 4, 4, &umr_bitfield_default },
	 { "PERFCOUNTER_INT5_STATUS", 5, 5, &umr_bitfield_default },
	 { "PERFCOUNTER_INT6_STATUS", 6, 6, &umr_bitfield_default },
	 { "PERFCOUNTER_INT7_STATUS", 7, 7, &umr_bitfield_default },
	 { "PERFCOUNTER_INT0_ACK", 8, 8, &umr_bitfield_default },
	 { "PERFCOUNTER_INT1_ACK", 9, 9, &umr_bitfield_default },
	 { "PERFCOUNTER_INT2_ACK", 10, 10, &umr_bitfield_default },
	 { "PERFCOUNTER_INT3_ACK", 11, 11, &umr_bitfield_default },
	 { "PERFCOUNTER_INT4_ACK", 12, 12, &umr_bitfield_default },
	 { "PERFCOUNTER_INT5_ACK", 13, 13, &umr_bitfield_default },
	 { "PERFCOUNTER_INT6_ACK", 14, 14, &umr_bitfield_default },
	 { "PERFCOUNTER_INT7_ACK", 15, 15, &umr_bitfield_default },
	 { "PERFMON_CVALUE_HI", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_PERFMON15_PERFMON_CVALUE_LOW[] = {
	 { "PERFMON_CVALUE_LOW", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_PERFMON15_PERFMON_HI[] = {
	 { "PERFMON_HI", 0, 15, &umr_bitfield_default },
	 { "PERFMON_READ_SEL", 29, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_PERFMON15_PERFMON_LOW[] = {
	 { "PERFMON_LOW", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMPCC0_MPCC_TOP_SEL[] = {
	 { "MPCC_TOP_SEL", 0, 3, &umr_bitfield_default },
};
static struct umr_bitfield mmMPCC0_MPCC_BOT_SEL[] = {
	 { "MPCC_BOT_SEL", 0, 3, &umr_bitfield_default },
};
static struct umr_bitfield mmMPCC0_MPCC_OPP_ID[] = {
	 { "MPCC_OPP_ID", 0, 3, &umr_bitfield_default },
};
static struct umr_bitfield mmMPCC0_MPCC_CONTROL[] = {
	 { "MPCC_MODE", 0, 1, &umr_bitfield_default },
	 { "MPCC_ALPHA_BLND_MODE", 4, 5, &umr_bitfield_default },
	 { "MPCC_ALPHA_MULTIPLIED_MODE", 6, 6, &umr_bitfield_default },
	 { "MPCC_BLND_ACTIVE_OVERLAP_ONLY", 7, 7, &umr_bitfield_default },
	 { "MPCC_GLOBAL_ALPHA", 16, 23, &umr_bitfield_default },
	 { "MPCC_GLOBAL_GAIN", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMPCC0_MPCC_SM_CONTROL[] = {
	 { "MPCC_SM_EN", 0, 0, &umr_bitfield_default },
	 { "MPCC_SM_MODE", 1, 3, &umr_bitfield_default },
	 { "MPCC_SM_FRAME_ALT", 4, 4, &umr_bitfield_default },
	 { "MPCC_SM_FIELD_ALT", 5, 5, &umr_bitfield_default },
	 { "MPCC_SM_FORCE_NEXT_FRAME_POL", 8, 9, &umr_bitfield_default },
	 { "MPCC_SM_FORCE_NEXT_TOP_POL", 16, 17, &umr_bitfield_default },
	 { "MPCC_SM_CURRENT_FRAME_POL", 24, 24, &umr_bitfield_default },
};
static struct umr_bitfield mmMPCC0_MPCC_UPDATE_LOCK_SEL[] = {
	 { "MPCC_UPDATE_LOCK_SEL", 0, 3, &umr_bitfield_default },
	 { "MPCC_UPDATE_LOCKED_STATUS", 4, 7, &umr_bitfield_default },
};
static struct umr_bitfield mmMPCC0_MPCC_TOP_OFFSET[] = {
	 { "MPCC_TOP_OFFSET_L", 0, 11, &umr_bitfield_default },
	 { "MPCC_TOP_OFFSET_C", 16, 27, &umr_bitfield_default },
};
static struct umr_bitfield mmMPCC0_MPCC_BOT_OFFSET[] = {
	 { "MPCC_BOT_OFFSET_L", 0, 11, &umr_bitfield_default },
	 { "MPCC_BOT_OFFSET_C", 16, 27, &umr_bitfield_default },
};
static struct umr_bitfield mmMPCC0_MPCC_OFFSET[] = {
	 { "MPCC_OFFSET_L", 0, 11, &umr_bitfield_default },
	 { "MPCC_OFFSET_C", 16, 27, &umr_bitfield_default },
};
static struct umr_bitfield mmMPCC0_MPCC_BG_R_CR[] = {
	 { "MPCC_BG_R_CR", 0, 11, &umr_bitfield_default },
};
static struct umr_bitfield mmMPCC0_MPCC_BG_G_Y[] = {
	 { "MPCC_BG_G_Y", 0, 11, &umr_bitfield_default },
};
static struct umr_bitfield mmMPCC0_MPCC_BG_B_CB[] = {
	 { "MPCC_BG_B_CB", 0, 11, &umr_bitfield_default },
};
static struct umr_bitfield mmMPCC0_MPCC_STALL_STATUS[] = {
	 { "MPCC_STALL_INT_OCCURED", 0, 0, &umr_bitfield_default },
	 { "MPCC_STALL_INT_ACK", 8, 8, &umr_bitfield_default },
	 { "MPCC_STALL_INT_MASK", 12, 12, &umr_bitfield_default },
	 { "MPCC_STALL_INFO", 16, 17, &umr_bitfield_default },
};
static struct umr_bitfield mmMPCC0_MPCC_STATUS[] = {
	 { "MPCC_IDLE", 0, 0, &umr_bitfield_default },
	 { "MPCC_BUSY", 1, 1, &umr_bitfield_default },
	 { "DPP_MPCC_EOL_MISSED", 16, 16, &umr_bitfield_default },
	 { "DPP_MPCC_MULTI_EOL", 17, 17, &umr_bitfield_default },
	 { "DPP_MPCC_EOF_MISSED", 18, 18, &umr_bitfield_default },
	 { "DPP_MPCC_MULTI_EOF", 19, 19, &umr_bitfield_default },
	 { "DPP_MPCC_LESS_PIXEL", 20, 20, &umr_bitfield_default },
	 { "DPP_MPCC_MORE_PIXEL", 21, 21, &umr_bitfield_default },
	 { "DPP_MPCC_LESS_LINES", 22, 22, &umr_bitfield_default },
	 { "DPP_MPCC_MORE_LINES", 23, 23, &umr_bitfield_default },
	 { "DPP_MPCC_INPUT_CHECK_ENABLE", 30, 30, &umr_bitfield_default },
	 { "DPP_MPCC_EXCEPTION_ACK", 31, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMPCC1_MPCC_TOP_SEL[] = {
	 { "MPCC_TOP_SEL", 0, 3, &umr_bitfield_default },
};
static struct umr_bitfield mmMPCC1_MPCC_BOT_SEL[] = {
	 { "MPCC_BOT_SEL", 0, 3, &umr_bitfield_default },
};
static struct umr_bitfield mmMPCC1_MPCC_OPP_ID[] = {
	 { "MPCC_OPP_ID", 0, 3, &umr_bitfield_default },
};
static struct umr_bitfield mmMPCC1_MPCC_CONTROL[] = {
	 { "MPCC_MODE", 0, 1, &umr_bitfield_default },
	 { "MPCC_ALPHA_BLND_MODE", 4, 5, &umr_bitfield_default },
	 { "MPCC_ALPHA_MULTIPLIED_MODE", 6, 6, &umr_bitfield_default },
	 { "MPCC_BLND_ACTIVE_OVERLAP_ONLY", 7, 7, &umr_bitfield_default },
	 { "MPCC_GLOBAL_ALPHA", 16, 23, &umr_bitfield_default },
	 { "MPCC_GLOBAL_GAIN", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMPCC1_MPCC_SM_CONTROL[] = {
	 { "MPCC_SM_EN", 0, 0, &umr_bitfield_default },
	 { "MPCC_SM_MODE", 1, 3, &umr_bitfield_default },
	 { "MPCC_SM_FRAME_ALT", 4, 4, &umr_bitfield_default },
	 { "MPCC_SM_FIELD_ALT", 5, 5, &umr_bitfield_default },
	 { "MPCC_SM_FORCE_NEXT_FRAME_POL", 8, 9, &umr_bitfield_default },
	 { "MPCC_SM_FORCE_NEXT_TOP_POL", 16, 17, &umr_bitfield_default },
	 { "MPCC_SM_CURRENT_FRAME_POL", 24, 24, &umr_bitfield_default },
};
static struct umr_bitfield mmMPCC1_MPCC_UPDATE_LOCK_SEL[] = {
	 { "MPCC_UPDATE_LOCK_SEL", 0, 3, &umr_bitfield_default },
	 { "MPCC_UPDATE_LOCKED_STATUS", 4, 7, &umr_bitfield_default },
};
static struct umr_bitfield mmMPCC1_MPCC_TOP_OFFSET[] = {
	 { "MPCC_TOP_OFFSET_L", 0, 11, &umr_bitfield_default },
	 { "MPCC_TOP_OFFSET_C", 16, 27, &umr_bitfield_default },
};
static struct umr_bitfield mmMPCC1_MPCC_BOT_OFFSET[] = {
	 { "MPCC_BOT_OFFSET_L", 0, 11, &umr_bitfield_default },
	 { "MPCC_BOT_OFFSET_C", 16, 27, &umr_bitfield_default },
};
static struct umr_bitfield mmMPCC1_MPCC_OFFSET[] = {
	 { "MPCC_OFFSET_L", 0, 11, &umr_bitfield_default },
	 { "MPCC_OFFSET_C", 16, 27, &umr_bitfield_default },
};
static struct umr_bitfield mmMPCC1_MPCC_BG_R_CR[] = {
	 { "MPCC_BG_R_CR", 0, 11, &umr_bitfield_default },
};
static struct umr_bitfield mmMPCC1_MPCC_BG_G_Y[] = {
	 { "MPCC_BG_G_Y", 0, 11, &umr_bitfield_default },
};
static struct umr_bitfield mmMPCC1_MPCC_BG_B_CB[] = {
	 { "MPCC_BG_B_CB", 0, 11, &umr_bitfield_default },
};
static struct umr_bitfield mmMPCC1_MPCC_STALL_STATUS[] = {
	 { "MPCC_STALL_INT_OCCURED", 0, 0, &umr_bitfield_default },
	 { "MPCC_STALL_INT_ACK", 8, 8, &umr_bitfield_default },
	 { "MPCC_STALL_INT_MASK", 12, 12, &umr_bitfield_default },
	 { "MPCC_STALL_INFO", 16, 17, &umr_bitfield_default },
};
static struct umr_bitfield mmMPCC1_MPCC_STATUS[] = {
	 { "MPCC_IDLE", 0, 0, &umr_bitfield_default },
	 { "MPCC_BUSY", 1, 1, &umr_bitfield_default },
	 { "DPP_MPCC_EOL_MISSED", 16, 16, &umr_bitfield_default },
	 { "DPP_MPCC_MULTI_EOL", 17, 17, &umr_bitfield_default },
	 { "DPP_MPCC_EOF_MISSED", 18, 18, &umr_bitfield_default },
	 { "DPP_MPCC_MULTI_EOF", 19, 19, &umr_bitfield_default },
	 { "DPP_MPCC_LESS_PIXEL", 20, 20, &umr_bitfield_default },
	 { "DPP_MPCC_MORE_PIXEL", 21, 21, &umr_bitfield_default },
	 { "DPP_MPCC_LESS_LINES", 22, 22, &umr_bitfield_default },
	 { "DPP_MPCC_MORE_LINES", 23, 23, &umr_bitfield_default },
	 { "DPP_MPCC_INPUT_CHECK_ENABLE", 30, 30, &umr_bitfield_default },
	 { "DPP_MPCC_EXCEPTION_ACK", 31, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMPCC2_MPCC_TOP_SEL[] = {
	 { "MPCC_TOP_SEL", 0, 3, &umr_bitfield_default },
};
static struct umr_bitfield mmMPCC2_MPCC_BOT_SEL[] = {
	 { "MPCC_BOT_SEL", 0, 3, &umr_bitfield_default },
};
static struct umr_bitfield mmMPCC2_MPCC_OPP_ID[] = {
	 { "MPCC_OPP_ID", 0, 3, &umr_bitfield_default },
};
static struct umr_bitfield mmMPCC2_MPCC_CONTROL[] = {
	 { "MPCC_MODE", 0, 1, &umr_bitfield_default },
	 { "MPCC_ALPHA_BLND_MODE", 4, 5, &umr_bitfield_default },
	 { "MPCC_ALPHA_MULTIPLIED_MODE", 6, 6, &umr_bitfield_default },
	 { "MPCC_BLND_ACTIVE_OVERLAP_ONLY", 7, 7, &umr_bitfield_default },
	 { "MPCC_GLOBAL_ALPHA", 16, 23, &umr_bitfield_default },
	 { "MPCC_GLOBAL_GAIN", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMPCC2_MPCC_SM_CONTROL[] = {
	 { "MPCC_SM_EN", 0, 0, &umr_bitfield_default },
	 { "MPCC_SM_MODE", 1, 3, &umr_bitfield_default },
	 { "MPCC_SM_FRAME_ALT", 4, 4, &umr_bitfield_default },
	 { "MPCC_SM_FIELD_ALT", 5, 5, &umr_bitfield_default },
	 { "MPCC_SM_FORCE_NEXT_FRAME_POL", 8, 9, &umr_bitfield_default },
	 { "MPCC_SM_FORCE_NEXT_TOP_POL", 16, 17, &umr_bitfield_default },
	 { "MPCC_SM_CURRENT_FRAME_POL", 24, 24, &umr_bitfield_default },
};
static struct umr_bitfield mmMPCC2_MPCC_UPDATE_LOCK_SEL[] = {
	 { "MPCC_UPDATE_LOCK_SEL", 0, 3, &umr_bitfield_default },
	 { "MPCC_UPDATE_LOCKED_STATUS", 4, 7, &umr_bitfield_default },
};
static struct umr_bitfield mmMPCC2_MPCC_TOP_OFFSET[] = {
	 { "MPCC_TOP_OFFSET_L", 0, 11, &umr_bitfield_default },
	 { "MPCC_TOP_OFFSET_C", 16, 27, &umr_bitfield_default },
};
static struct umr_bitfield mmMPCC2_MPCC_BOT_OFFSET[] = {
	 { "MPCC_BOT_OFFSET_L", 0, 11, &umr_bitfield_default },
	 { "MPCC_BOT_OFFSET_C", 16, 27, &umr_bitfield_default },
};
static struct umr_bitfield mmMPCC2_MPCC_OFFSET[] = {
	 { "MPCC_OFFSET_L", 0, 11, &umr_bitfield_default },
	 { "MPCC_OFFSET_C", 16, 27, &umr_bitfield_default },
};
static struct umr_bitfield mmMPCC2_MPCC_BG_R_CR[] = {
	 { "MPCC_BG_R_CR", 0, 11, &umr_bitfield_default },
};
static struct umr_bitfield mmMPCC2_MPCC_BG_G_Y[] = {
	 { "MPCC_BG_G_Y", 0, 11, &umr_bitfield_default },
};
static struct umr_bitfield mmMPCC2_MPCC_BG_B_CB[] = {
	 { "MPCC_BG_B_CB", 0, 11, &umr_bitfield_default },
};
static struct umr_bitfield mmMPCC2_MPCC_STALL_STATUS[] = {
	 { "MPCC_STALL_INT_OCCURED", 0, 0, &umr_bitfield_default },
	 { "MPCC_STALL_INT_ACK", 8, 8, &umr_bitfield_default },
	 { "MPCC_STALL_INT_MASK", 12, 12, &umr_bitfield_default },
	 { "MPCC_STALL_INFO", 16, 17, &umr_bitfield_default },
};
static struct umr_bitfield mmMPCC2_MPCC_STATUS[] = {
	 { "MPCC_IDLE", 0, 0, &umr_bitfield_default },
	 { "MPCC_BUSY", 1, 1, &umr_bitfield_default },
	 { "DPP_MPCC_EOL_MISSED", 16, 16, &umr_bitfield_default },
	 { "DPP_MPCC_MULTI_EOL", 17, 17, &umr_bitfield_default },
	 { "DPP_MPCC_EOF_MISSED", 18, 18, &umr_bitfield_default },
	 { "DPP_MPCC_MULTI_EOF", 19, 19, &umr_bitfield_default },
	 { "DPP_MPCC_LESS_PIXEL", 20, 20, &umr_bitfield_default },
	 { "DPP_MPCC_MORE_PIXEL", 21, 21, &umr_bitfield_default },
	 { "DPP_MPCC_LESS_LINES", 22, 22, &umr_bitfield_default },
	 { "DPP_MPCC_MORE_LINES", 23, 23, &umr_bitfield_default },
	 { "DPP_MPCC_INPUT_CHECK_ENABLE", 30, 30, &umr_bitfield_default },
	 { "DPP_MPCC_EXCEPTION_ACK", 31, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMPCC3_MPCC_TOP_SEL[] = {
	 { "MPCC_TOP_SEL", 0, 3, &umr_bitfield_default },
};
static struct umr_bitfield mmMPCC3_MPCC_BOT_SEL[] = {
	 { "MPCC_BOT_SEL", 0, 3, &umr_bitfield_default },
};
static struct umr_bitfield mmMPCC3_MPCC_OPP_ID[] = {
	 { "MPCC_OPP_ID", 0, 3, &umr_bitfield_default },
};
static struct umr_bitfield mmMPCC3_MPCC_CONTROL[] = {
	 { "MPCC_MODE", 0, 1, &umr_bitfield_default },
	 { "MPCC_ALPHA_BLND_MODE", 4, 5, &umr_bitfield_default },
	 { "MPCC_ALPHA_MULTIPLIED_MODE", 6, 6, &umr_bitfield_default },
	 { "MPCC_BLND_ACTIVE_OVERLAP_ONLY", 7, 7, &umr_bitfield_default },
	 { "MPCC_GLOBAL_ALPHA", 16, 23, &umr_bitfield_default },
	 { "MPCC_GLOBAL_GAIN", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMPCC3_MPCC_SM_CONTROL[] = {
	 { "MPCC_SM_EN", 0, 0, &umr_bitfield_default },
	 { "MPCC_SM_MODE", 1, 3, &umr_bitfield_default },
	 { "MPCC_SM_FRAME_ALT", 4, 4, &umr_bitfield_default },
	 { "MPCC_SM_FIELD_ALT", 5, 5, &umr_bitfield_default },
	 { "MPCC_SM_FORCE_NEXT_FRAME_POL", 8, 9, &umr_bitfield_default },
	 { "MPCC_SM_FORCE_NEXT_TOP_POL", 16, 17, &umr_bitfield_default },
	 { "MPCC_SM_CURRENT_FRAME_POL", 24, 24, &umr_bitfield_default },
};
static struct umr_bitfield mmMPCC3_MPCC_UPDATE_LOCK_SEL[] = {
	 { "MPCC_UPDATE_LOCK_SEL", 0, 3, &umr_bitfield_default },
	 { "MPCC_UPDATE_LOCKED_STATUS", 4, 7, &umr_bitfield_default },
};
static struct umr_bitfield mmMPCC3_MPCC_TOP_OFFSET[] = {
	 { "MPCC_TOP_OFFSET_L", 0, 11, &umr_bitfield_default },
	 { "MPCC_TOP_OFFSET_C", 16, 27, &umr_bitfield_default },
};
static struct umr_bitfield mmMPCC3_MPCC_BOT_OFFSET[] = {
	 { "MPCC_BOT_OFFSET_L", 0, 11, &umr_bitfield_default },
	 { "MPCC_BOT_OFFSET_C", 16, 27, &umr_bitfield_default },
};
static struct umr_bitfield mmMPCC3_MPCC_OFFSET[] = {
	 { "MPCC_OFFSET_L", 0, 11, &umr_bitfield_default },
	 { "MPCC_OFFSET_C", 16, 27, &umr_bitfield_default },
};
static struct umr_bitfield mmMPCC3_MPCC_BG_R_CR[] = {
	 { "MPCC_BG_R_CR", 0, 11, &umr_bitfield_default },
};
static struct umr_bitfield mmMPCC3_MPCC_BG_G_Y[] = {
	 { "MPCC_BG_G_Y", 0, 11, &umr_bitfield_default },
};
static struct umr_bitfield mmMPCC3_MPCC_BG_B_CB[] = {
	 { "MPCC_BG_B_CB", 0, 11, &umr_bitfield_default },
};
static struct umr_bitfield mmMPCC3_MPCC_STALL_STATUS[] = {
	 { "MPCC_STALL_INT_OCCURED", 0, 0, &umr_bitfield_default },
	 { "MPCC_STALL_INT_ACK", 8, 8, &umr_bitfield_default },
	 { "MPCC_STALL_INT_MASK", 12, 12, &umr_bitfield_default },
	 { "MPCC_STALL_INFO", 16, 17, &umr_bitfield_default },
};
static struct umr_bitfield mmMPCC3_MPCC_STATUS[] = {
	 { "MPCC_IDLE", 0, 0, &umr_bitfield_default },
	 { "MPCC_BUSY", 1, 1, &umr_bitfield_default },
	 { "DPP_MPCC_EOL_MISSED", 16, 16, &umr_bitfield_default },
	 { "DPP_MPCC_MULTI_EOL", 17, 17, &umr_bitfield_default },
	 { "DPP_MPCC_EOF_MISSED", 18, 18, &umr_bitfield_default },
	 { "DPP_MPCC_MULTI_EOF", 19, 19, &umr_bitfield_default },
	 { "DPP_MPCC_LESS_PIXEL", 20, 20, &umr_bitfield_default },
	 { "DPP_MPCC_MORE_PIXEL", 21, 21, &umr_bitfield_default },
	 { "DPP_MPCC_LESS_LINES", 22, 22, &umr_bitfield_default },
	 { "DPP_MPCC_MORE_LINES", 23, 23, &umr_bitfield_default },
	 { "DPP_MPCC_INPUT_CHECK_ENABLE", 30, 30, &umr_bitfield_default },
	 { "DPP_MPCC_EXCEPTION_ACK", 31, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMPC_CLOCK_CONTROL[] = {
	 { "DISPCLK_R_GATE_DISABLE", 1, 1, &umr_bitfield_default },
	 { "MPC_TEST_CLK_SEL", 4, 5, &umr_bitfield_default },
};
static struct umr_bitfield mmMPC_SOFT_RESET[] = {
	 { "MPCC0_SOFT_RESET", 0, 0, &umr_bitfield_default },
	 { "MPCC1_SOFT_RESET", 1, 1, &umr_bitfield_default },
	 { "MPCC2_SOFT_RESET", 2, 2, &umr_bitfield_default },
	 { "MPCC3_SOFT_RESET", 3, 3, &umr_bitfield_default },
	 { "MPC_SFR0_SOFT_RESET", 10, 10, &umr_bitfield_default },
	 { "MPC_SFR1_SOFT_RESET", 11, 11, &umr_bitfield_default },
	 { "MPC_SFR2_SOFT_RESET", 12, 12, &umr_bitfield_default },
	 { "MPC_SFR3_SOFT_RESET", 13, 13, &umr_bitfield_default },
	 { "MPC_SFT0_SOFT_RESET", 20, 20, &umr_bitfield_default },
	 { "MPC_SFT1_SOFT_RESET", 21, 21, &umr_bitfield_default },
	 { "MPC_SFT2_SOFT_RESET", 22, 22, &umr_bitfield_default },
	 { "MPC_SFT3_SOFT_RESET", 23, 23, &umr_bitfield_default },
	 { "MPC_SOFT_RESET", 31, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMPC_CRC_CTRL[] = {
	 { "MPC_CRC_EN", 0, 0, &umr_bitfield_default },
	 { "MPC_CRC_CONT_EN", 4, 4, &umr_bitfield_default },
	 { "MPC_CRC_STEREO_MODE", 8, 9, &umr_bitfield_default },
	 { "MPC_CRC_STEREO_EN", 10, 10, &umr_bitfield_default },
	 { "MPC_CRC_INTERLACE_MODE", 12, 13, &umr_bitfield_default },
	 { "MPC_CRC_SRC_SEL", 24, 25, &umr_bitfield_default },
	 { "MPC_CRC_ONE_SHOT_PENDING", 28, 28, &umr_bitfield_default },
	 { "MPC_CRC_UPDATE_LOCK", 31, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMPC_CRC_SEL_CONTROL[] = {
	 { "MPC_CRC_DPP_SEL", 0, 3, &umr_bitfield_default },
	 { "MPC_CRC_OPP_SEL", 4, 7, &umr_bitfield_default },
	 { "MPC_CRC_MASK", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMPC_CRC_RESULT_AR[] = {
	 { "MPC_CRC_RESULT_A", 0, 15, &umr_bitfield_default },
	 { "MPC_CRC_RESULT_R", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMPC_CRC_RESULT_GB[] = {
	 { "MPC_CRC_RESULT_G", 0, 15, &umr_bitfield_default },
	 { "MPC_CRC_RESULT_B", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMPC_CRC_RESULT_C[] = {
	 { "MPC_CRC_RESULT_C", 0, 15, &umr_bitfield_default },
};
static struct umr_bitfield mmMPC_PERFMON_EVENT_CTRL[] = {
	 { "MPC_PERFMON_EVENT_EN", 0, 0, &umr_bitfield_default },
};
static struct umr_bitfield mmMPC_BYPASS_BG_AR[] = {
	 { "MPC_BYPASS_BG_ALPHA", 0, 15, &umr_bitfield_default },
	 { "MPC_BYPASS_BG_R_CR", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMPC_BYPASS_BG_GB[] = {
	 { "MPC_BYPASS_BG_G_Y", 0, 15, &umr_bitfield_default },
	 { "MPC_BYPASS_BG_B_CB", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMPC_OUT0_MUX[] = {
	 { "MPC_OUT_MUX", 0, 3, &umr_bitfield_default },
};
static struct umr_bitfield mmMPC_OUT1_MUX[] = {
	 { "MPC_OUT_MUX", 0, 3, &umr_bitfield_default },
};
static struct umr_bitfield mmMPC_OUT2_MUX[] = {
	 { "MPC_OUT_MUX", 0, 3, &umr_bitfield_default },
};
static struct umr_bitfield mmMPC_OUT3_MUX[] = {
	 { "MPC_OUT_MUX", 0, 3, &umr_bitfield_default },
};
static struct umr_bitfield mmMPC_STALL_GRACE_WINDOW[] = {
	 { "MPC_STALL_GRACE_WINDOW_PERIOD", 0, 7, &umr_bitfield_default },
};
static struct umr_bitfield mmADR_CFG_VUPDATE_LOCK_SET0[] = {
	 { "ADR_CFG_VUPDATE_LOCK_SET", 0, 0, &umr_bitfield_default },
	 { "CFG_VUPDATE_LOCK_SET", 4, 4, &umr_bitfield_default },
};
static struct umr_bitfield mmADR_VUPDATE_LOCK_SET0[] = {
	 { "ADR_VUPDATE_LOCK_SET", 0, 0, &umr_bitfield_default },
};
static struct umr_bitfield mmCUR0_VUPDATE_LOCK_SET0[] = {
	 { "CUR0_VUPDATE_LOCK_SET", 0, 0, &umr_bitfield_default },
};
static struct umr_bitfield mmCUR1_VUPDATE_LOCK_SET0[] = {
	 { "CUR1_VUPDATE_LOCK_SET", 0, 0, &umr_bitfield_default },
};
static struct umr_bitfield mmADR_CFG_VUPDATE_LOCK_SET1[] = {
	 { "ADR_CFG_VUPDATE_LOCK_SET", 0, 0, &umr_bitfield_default },
	 { "CFG_VUPDATE_LOCK_SET", 4, 4, &umr_bitfield_default },
};
static struct umr_bitfield mmADR_VUPDATE_LOCK_SET1[] = {
	 { "ADR_VUPDATE_LOCK_SET", 0, 0, &umr_bitfield_default },
};
static struct umr_bitfield mmCUR0_VUPDATE_LOCK_SET1[] = {
	 { "CUR0_VUPDATE_LOCK_SET", 0, 0, &umr_bitfield_default },
};
static struct umr_bitfield mmCUR1_VUPDATE_LOCK_SET1[] = {
	 { "CUR1_VUPDATE_LOCK_SET", 0, 0, &umr_bitfield_default },
};
static struct umr_bitfield mmADR_CFG_VUPDATE_LOCK_SET2[] = {
	 { "ADR_CFG_VUPDATE_LOCK_SET", 0, 0, &umr_bitfield_default },
	 { "CFG_VUPDATE_LOCK_SET", 4, 4, &umr_bitfield_default },
};
static struct umr_bitfield mmADR_VUPDATE_LOCK_SET2[] = {
	 { "ADR_VUPDATE_LOCK_SET", 0, 0, &umr_bitfield_default },
};
static struct umr_bitfield mmCUR0_VUPDATE_LOCK_SET2[] = {
	 { "CUR0_VUPDATE_LOCK_SET", 0, 0, &umr_bitfield_default },
};
static struct umr_bitfield mmCUR1_VUPDATE_LOCK_SET2[] = {
	 { "CUR1_VUPDATE_LOCK_SET", 0, 0, &umr_bitfield_default },
};
static struct umr_bitfield mmADR_CFG_VUPDATE_LOCK_SET3[] = {
	 { "ADR_CFG_VUPDATE_LOCK_SET", 0, 0, &umr_bitfield_default },
	 { "CFG_VUPDATE_LOCK_SET", 4, 4, &umr_bitfield_default },
};
static struct umr_bitfield mmADR_VUPDATE_LOCK_SET3[] = {
	 { "ADR_VUPDATE_LOCK_SET", 0, 0, &umr_bitfield_default },
};
static struct umr_bitfield mmCUR0_VUPDATE_LOCK_SET3[] = {
	 { "CUR0_VUPDATE_LOCK_SET", 0, 0, &umr_bitfield_default },
};
static struct umr_bitfield mmCUR1_VUPDATE_LOCK_SET3[] = {
	 { "CUR1_VUPDATE_LOCK_SET", 0, 0, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_PERFMON16_PERFCOUNTER_CNTL[] = {
	 { "PERFCOUNTER_EVENT_SEL", 0, 8, &umr_bitfield_default },
	 { "PERFCOUNTER_CVALUE_SEL", 9, 11, &umr_bitfield_default },
	 { "PERFCOUNTER_INC_MODE", 12, 14, &umr_bitfield_default },
	 { "PERFCOUNTER_HW_CNTL_SEL", 15, 15, &umr_bitfield_default },
	 { "PERFCOUNTER_RUNEN_MODE", 16, 16, &umr_bitfield_default },
	 { "PERFCOUNTER_CNTOFF_START_DIS", 22, 22, &umr_bitfield_default },
	 { "PERFCOUNTER_RESTART_EN", 23, 23, &umr_bitfield_default },
	 { "PERFCOUNTER_INT_EN", 24, 24, &umr_bitfield_default },
	 { "PERFCOUNTER_OFF_MASK", 25, 25, &umr_bitfield_default },
	 { "PERFCOUNTER_ACTIVE", 26, 26, &umr_bitfield_default },
	 { "PERFCOUNTER_CNTL_SEL", 29, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_PERFMON16_PERFCOUNTER_CNTL2[] = {
	 { "PERFCOUNTER_COUNTED_VALUE_TYPE", 0, 1, &umr_bitfield_default },
	 { "PERFCOUNTER_HW_STOP1_SEL", 2, 2, &umr_bitfield_default },
	 { "PERFCOUNTER_HW_STOP2_SEL", 3, 3, &umr_bitfield_default },
	 { "PERFCOUNTER_CNTOFF_SEL", 8, 13, &umr_bitfield_default },
	 { "PERFCOUNTER_CNTL2_SEL", 29, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_PERFMON16_PERFCOUNTER_STATE[] = {
	 { "PERFCOUNTER_CNT0_STATE", 0, 1, &umr_bitfield_default },
	 { "PERFCOUNTER_STATE_SEL0", 2, 2, &umr_bitfield_default },
	 { "PERFCOUNTER_CNT1_STATE", 4, 5, &umr_bitfield_default },
	 { "PERFCOUNTER_STATE_SEL1", 6, 6, &umr_bitfield_default },
	 { "PERFCOUNTER_CNT2_STATE", 8, 9, &umr_bitfield_default },
	 { "PERFCOUNTER_STATE_SEL2", 10, 10, &umr_bitfield_default },
	 { "PERFCOUNTER_CNT3_STATE", 12, 13, &umr_bitfield_default },
	 { "PERFCOUNTER_STATE_SEL3", 14, 14, &umr_bitfield_default },
	 { "PERFCOUNTER_CNT4_STATE", 16, 17, &umr_bitfield_default },
	 { "PERFCOUNTER_STATE_SEL4", 18, 18, &umr_bitfield_default },
	 { "PERFCOUNTER_CNT5_STATE", 20, 21, &umr_bitfield_default },
	 { "PERFCOUNTER_STATE_SEL5", 22, 22, &umr_bitfield_default },
	 { "PERFCOUNTER_CNT6_STATE", 24, 25, &umr_bitfield_default },
	 { "PERFCOUNTER_STATE_SEL6", 26, 26, &umr_bitfield_default },
	 { "PERFCOUNTER_CNT7_STATE", 28, 29, &umr_bitfield_default },
	 { "PERFCOUNTER_STATE_SEL7", 30, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_PERFMON16_PERFMON_CNTL[] = {
	 { "PERFMON_STATE", 0, 1, &umr_bitfield_default },
	 { "PERFMON_RPT_COUNT", 8, 27, &umr_bitfield_default },
	 { "PERFMON_CNTOFF_AND_OR", 28, 28, &umr_bitfield_default },
	 { "PERFMON_CNTOFF_INT_EN", 29, 29, &umr_bitfield_default },
	 { "PERFMON_CNTOFF_INT_STATUS", 30, 30, &umr_bitfield_default },
	 { "PERFMON_CNTOFF_INT_ACK", 31, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_PERFMON16_PERFMON_CNTL2[] = {
	 { "PERFMON_CNTOFF_INT_TYPE", 0, 0, &umr_bitfield_default },
	 { "PERFMON_CLK_ENABLE", 1, 1, &umr_bitfield_default },
	 { "PERFMON_RUN_ENABLE_START_SEL", 2, 9, &umr_bitfield_default },
	 { "PERFMON_RUN_ENABLE_STOP_SEL", 10, 17, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_PERFMON16_PERFMON_CVALUE_INT_MISC[] = {
	 { "PERFCOUNTER_INT0_STATUS", 0, 0, &umr_bitfield_default },
	 { "PERFCOUNTER_INT1_STATUS", 1, 1, &umr_bitfield_default },
	 { "PERFCOUNTER_INT2_STATUS", 2, 2, &umr_bitfield_default },
	 { "PERFCOUNTER_INT3_STATUS", 3, 3, &umr_bitfield_default },
	 { "PERFCOUNTER_INT4_STATUS", 4, 4, &umr_bitfield_default },
	 { "PERFCOUNTER_INT5_STATUS", 5, 5, &umr_bitfield_default },
	 { "PERFCOUNTER_INT6_STATUS", 6, 6, &umr_bitfield_default },
	 { "PERFCOUNTER_INT7_STATUS", 7, 7, &umr_bitfield_default },
	 { "PERFCOUNTER_INT0_ACK", 8, 8, &umr_bitfield_default },
	 { "PERFCOUNTER_INT1_ACK", 9, 9, &umr_bitfield_default },
	 { "PERFCOUNTER_INT2_ACK", 10, 10, &umr_bitfield_default },
	 { "PERFCOUNTER_INT3_ACK", 11, 11, &umr_bitfield_default },
	 { "PERFCOUNTER_INT4_ACK", 12, 12, &umr_bitfield_default },
	 { "PERFCOUNTER_INT5_ACK", 13, 13, &umr_bitfield_default },
	 { "PERFCOUNTER_INT6_ACK", 14, 14, &umr_bitfield_default },
	 { "PERFCOUNTER_INT7_ACK", 15, 15, &umr_bitfield_default },
	 { "PERFMON_CVALUE_HI", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_PERFMON16_PERFMON_CVALUE_LOW[] = {
	 { "PERFMON_CVALUE_LOW", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_PERFMON16_PERFMON_HI[] = {
	 { "PERFMON_HI", 0, 15, &umr_bitfield_default },
	 { "PERFMON_READ_SEL", 29, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_PERFMON16_PERFMON_LOW[] = {
	 { "PERFMON_LOW", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmABM0_BL1_PWM_AMBIENT_LIGHT_LEVEL[] = {
	 { "BL1_PWM_AMBIENT_LIGHT_LEVEL", 0, 16, &umr_bitfield_default },
};
static struct umr_bitfield mmABM0_BL1_PWM_USER_LEVEL[] = {
	 { "BL1_PWM_USER_LEVEL", 0, 16, &umr_bitfield_default },
};
static struct umr_bitfield mmABM0_BL1_PWM_TARGET_ABM_LEVEL[] = {
	 { "BL1_PWM_TARGET_ABM_LEVEL", 0, 16, &umr_bitfield_default },
};
static struct umr_bitfield mmABM0_BL1_PWM_CURRENT_ABM_LEVEL[] = {
	 { "BL1_PWM_CURRENT_ABM_LEVEL", 0, 16, &umr_bitfield_default },
};
static struct umr_bitfield mmABM0_BL1_PWM_FINAL_DUTY_CYCLE[] = {
	 { "BL1_PWM_FINAL_DUTY_CYCLE", 0, 16, &umr_bitfield_default },
};
static struct umr_bitfield mmABM0_BL1_PWM_MINIMUM_DUTY_CYCLE[] = {
	 { "BL1_PWM_MINIMUM_DUTY_CYCLE", 0, 16, &umr_bitfield_default },
};
static struct umr_bitfield mmABM0_BL1_PWM_ABM_CNTL[] = {
	 { "BL1_PWM_USE_ABM_EN", 0, 0, &umr_bitfield_default },
	 { "BL1_PWM_USE_AMBIENT_LEVEL_EN", 1, 1, &umr_bitfield_default },
	 { "BL1_PWM_AUTO_UPDATE_CURRENT_ABM_LEVEL_EN", 2, 2, &umr_bitfield_default },
	 { "BL1_PWM_AUTO_CALC_FINAL_DUTY_CYCLE_EN", 3, 3, &umr_bitfield_default },
	 { "BL1_PWM_AUTO_UPDATE_CURRENT_ABM_STEP_SIZE", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmABM0_BL1_PWM_BL_UPDATE_SAMPLE_RATE[] = {
	 { "BL1_PWM_BL_UPDATE_SAMPLE_RATE_COUNT_EN", 0, 0, &umr_bitfield_default },
	 { "BL1_PWM_BL_UPDATE_RESET_SAMPLE_RATE_FRAME_COUNTER", 1, 1, &umr_bitfield_default },
	 { "BL1_PWM_BL_UPDATE_SAMPLE_RATE_FRAME_COUNT", 8, 15, &umr_bitfield_default },
	 { "BL1_PWM_BL_UPDATE_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET", 16, 23, &umr_bitfield_default },
	 { "ABM1_HGLS_REG_LOCK", 31, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmABM0_BL1_PWM_GRP2_REG_LOCK[] = {
	 { "BL1_PWM_GRP2_REG_LOCK", 0, 0, &umr_bitfield_default },
	 { "BL1_PWM_GRP2_REG_UPDATE_PENDING", 8, 8, &umr_bitfield_default },
	 { "BL1_PWM_GRP2_UPDATE_AT_FRAME_START", 16, 16, &umr_bitfield_default },
	 { "BL1_PWM_GRP2_FRAME_START_DISP_SEL", 17, 19, &umr_bitfield_default },
	 { "BL1_PWM_GRP2_READBACK_DB_REG_VALUE_EN", 24, 24, &umr_bitfield_default },
	 { "BL1_PWM_GRP2_IGNORE_MASTER_LOCK_EN", 31, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmABM0_DC_ABM1_CNTL[] = {
	 { "ABM1_EN", 0, 0, &umr_bitfield_default },
	 { "ABM1_SOURCE_SELECT", 8, 10, &umr_bitfield_default },
};
static struct umr_bitfield mmABM0_DC_ABM1_IPCSC_COEFF_SEL[] = {
	 { "ABM1_IPCSC_COEFF_SEL_B", 0, 3, &umr_bitfield_default },
	 { "ABM1_IPCSC_COEFF_SEL_G", 8, 11, &umr_bitfield_default },
	 { "ABM1_IPCSC_COEFF_SEL_R", 16, 19, &umr_bitfield_default },
	 { "ABM1_HGLS_REG_LOCK", 31, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmABM0_DC_ABM1_ACE_OFFSET_SLOPE_0[] = {
	 { "ABM1_ACE_SLOPE_0", 0, 14, &umr_bitfield_default },
	 { "ABM1_ACE_OFFSET_0", 16, 26, &umr_bitfield_default },
	 { "ABM1_ACE_LOCK", 31, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmABM0_DC_ABM1_ACE_OFFSET_SLOPE_1[] = {
	 { "ABM1_ACE_SLOPE_1", 0, 14, &umr_bitfield_default },
	 { "ABM1_ACE_OFFSET_1", 16, 26, &umr_bitfield_default },
	 { "ABM1_ACE_LOCK", 31, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmABM0_DC_ABM1_ACE_OFFSET_SLOPE_2[] = {
	 { "ABM1_ACE_SLOPE_2", 0, 14, &umr_bitfield_default },
	 { "ABM1_ACE_OFFSET_2", 16, 26, &umr_bitfield_default },
	 { "ABM1_ACE_LOCK", 31, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmABM0_DC_ABM1_ACE_OFFSET_SLOPE_3[] = {
	 { "ABM1_ACE_SLOPE_3", 0, 14, &umr_bitfield_default },
	 { "ABM1_ACE_OFFSET_3", 16, 26, &umr_bitfield_default },
	 { "ABM1_ACE_LOCK", 31, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmABM0_DC_ABM1_ACE_OFFSET_SLOPE_4[] = {
	 { "ABM1_ACE_SLOPE_4", 0, 14, &umr_bitfield_default },
	 { "ABM1_ACE_OFFSET_4", 16, 26, &umr_bitfield_default },
	 { "ABM1_ACE_LOCK", 31, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmABM0_DC_ABM1_ACE_THRES_12[] = {
	 { "ABM1_ACE_THRES_1", 0, 9, &umr_bitfield_default },
	 { "ABM1_ACE_THRES_2", 16, 25, &umr_bitfield_default },
	 { "ABM1_ACE_LOCK", 31, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmABM0_DC_ABM1_ACE_THRES_34[] = {
	 { "ABM1_ACE_THRES_3", 0, 9, &umr_bitfield_default },
	 { "ABM1_ACE_THRES_4", 16, 25, &umr_bitfield_default },
	 { "ABM1_ACE_IGNORE_MASTER_LOCK_EN", 28, 28, &umr_bitfield_default },
	 { "ABM1_ACE_READBACK_DB_REG_VALUE_EN", 29, 29, &umr_bitfield_default },
	 { "ABM1_ACE_DBUF_REG_UPDATE_PENDING", 30, 30, &umr_bitfield_default },
	 { "ABM1_ACE_LOCK", 31, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmABM0_DC_ABM1_ACE_CNTL_MISC[] = {
	 { "ABM1_ACE_REG_WR_MISSED_FRAME", 0, 0, &umr_bitfield_default },
	 { "ABM1_ACE_REG_WR_MISSED_FRAME_CLEAR", 8, 8, &umr_bitfield_default },
};
static struct umr_bitfield mmABM0_DC_ABM1_HGLS_REG_READ_PROGRESS[] = {
	 { "ABM1_HG_REG_READ_IN_PROGRESS", 0, 0, &umr_bitfield_default },
	 { "ABM1_LS_REG_READ_IN_PROGRESS", 1, 1, &umr_bitfield_default },
	 { "ABM1_BL_REG_READ_IN_PROGRESS", 2, 2, &umr_bitfield_default },
	 { "ABM1_HG_REG_READ_MISSED_FRAME", 8, 8, &umr_bitfield_default },
	 { "ABM1_LS_REG_READ_MISSED_FRAME", 9, 9, &umr_bitfield_default },
	 { "ABM1_BL_REG_READ_MISSED_FRAME", 10, 10, &umr_bitfield_default },
	 { "ABM1_HG_REG_READ_MISSED_FRAME_CLEAR", 16, 16, &umr_bitfield_default },
	 { "ABM1_LS_REG_READ_MISSED_FRAME_CLEAR", 24, 24, &umr_bitfield_default },
	 { "ABM1_BL_REG_READ_MISSED_FRAME_CLEAR", 31, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmABM0_DC_ABM1_HG_MISC_CTRL[] = {
	 { "ABM1_HG_NUM_OF_BINS_SEL", 0, 1, &umr_bitfield_default },
	 { "ABM1_HG_VMAX_SEL", 8, 8, &umr_bitfield_default },
	 { "ABM1_HG_FINE_MODE_BIN_SEL", 12, 12, &umr_bitfield_default },
	 { "ABM1_HG_BIN_BITWIDTH_SIZE_SEL", 16, 17, &umr_bitfield_default },
	 { "ABM1_OVR_SCAN_PIXEL_PROCESS_EN", 20, 20, &umr_bitfield_default },
	 { "ABM1_DBUF_HGLS_READBACK_DB_REG_VALUE_EN", 23, 23, &umr_bitfield_default },
	 { "ABM1_DBUF_HGLS_REG_FRAME_START_DISP_SEL", 24, 26, &umr_bitfield_default },
	 { "ABM1_DBUF_HGLS_REG_UPDATE_AT_FRAME_START", 28, 28, &umr_bitfield_default },
	 { "ABM1_HGLS_IGNORE_MASTER_LOCK_EN", 29, 29, &umr_bitfield_default },
	 { "ABM1_DBUF_HGLS_REG_UPDATE_PENDING", 30, 30, &umr_bitfield_default },
	 { "ABM1_HGLS_REG_LOCK", 31, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmABM0_DC_ABM1_LS_SUM_OF_LUMA[] = {
	 { "ABM1_LS_SUM_OF_LUMA", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmABM0_DC_ABM1_LS_MIN_MAX_LUMA[] = {
	 { "ABM1_LS_MIN_LUMA", 0, 9, &umr_bitfield_default },
	 { "ABM1_LS_MAX_LUMA", 16, 25, &umr_bitfield_default },
};
static struct umr_bitfield mmABM0_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA[] = {
	 { "ABM1_LS_FILTERED_MIN_LUMA", 0, 9, &umr_bitfield_default },
	 { "ABM1_LS_FILTERED_MAX_LUMA", 16, 25, &umr_bitfield_default },
};
static struct umr_bitfield mmABM0_DC_ABM1_LS_PIXEL_COUNT[] = {
	 { "ABM1_LS_PIXEL_COUNT", 0, 23, &umr_bitfield_default },
	 { "ABM1_LS_SUM_OF_LUMA_MSB", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmABM0_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES[] = {
	 { "ABM1_LS_MIN_PIXEL_VALUE_THRES", 0, 9, &umr_bitfield_default },
	 { "ABM1_LS_MAX_PIXEL_VALUE_THRES", 16, 25, &umr_bitfield_default },
	 { "ABM1_HGLS_REG_LOCK", 31, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmABM0_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT[] = {
	 { "ABM1_LS_MIN_PIXEL_VALUE_COUNT", 0, 23, &umr_bitfield_default },
};
static struct umr_bitfield mmABM0_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT[] = {
	 { "ABM1_LS_MAX_PIXEL_VALUE_COUNT", 0, 23, &umr_bitfield_default },
};
static struct umr_bitfield mmABM0_DC_ABM1_HG_SAMPLE_RATE[] = {
	 { "ABM1_HG_SAMPLE_RATE_COUNT_EN", 0, 0, &umr_bitfield_default },
	 { "ABM1_HG_RESET_SAMPLE_RATE_FRAME_COUNTER", 1, 1, &umr_bitfield_default },
	 { "ABM1_HG_SAMPLE_RATE_FRAME_COUNT", 8, 15, &umr_bitfield_default },
	 { "ABM1_HG_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET", 16, 23, &umr_bitfield_default },
	 { "ABM1_HGLS_REG_LOCK", 31, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmABM0_DC_ABM1_LS_SAMPLE_RATE[] = {
	 { "ABM1_LS_SAMPLE_RATE_COUNT_EN", 0, 0, &umr_bitfield_default },
	 { "ABM1_LS_RESET_SAMPLE_RATE_FRAME_COUNTER", 1, 1, &umr_bitfield_default },
	 { "ABM1_LS_SAMPLE_RATE_FRAME_COUNT", 8, 15, &umr_bitfield_default },
	 { "ABM1_LS_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET", 16, 23, &umr_bitfield_default },
	 { "ABM1_HGLS_REG_LOCK", 31, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmABM0_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG[] = {
	 { "ABM1_HG_BIN_1_32_SHIFT_FLAG", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmABM0_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX[] = {
	 { "ABM1_HG_BIN_1_8_SHIFT_INDEX", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmABM0_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX[] = {
	 { "ABM1_HG_BIN_9_16_SHIFT_INDEX", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmABM0_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX[] = {
	 { "ABM1_HG_BIN_17_24_SHIFT_INDEX", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmABM0_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX[] = {
	 { "ABM1_HG_BIN_25_32_SHIFT_INDEX", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmABM0_DC_ABM1_HG_RESULT_1[] = {
	 { "ABM1_HG_RESULT_1", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmABM0_DC_ABM1_HG_RESULT_2[] = {
	 { "ABM1_HG_RESULT_2", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmABM0_DC_ABM1_HG_RESULT_3[] = {
	 { "ABM1_HG_RESULT_3", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmABM0_DC_ABM1_HG_RESULT_4[] = {
	 { "ABM1_HG_RESULT_4", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmABM0_DC_ABM1_HG_RESULT_5[] = {
	 { "ABM1_HG_RESULT_5", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmABM0_DC_ABM1_HG_RESULT_6[] = {
	 { "ABM1_HG_RESULT_6", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmABM0_DC_ABM1_HG_RESULT_7[] = {
	 { "ABM1_HG_RESULT_7", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmABM0_DC_ABM1_HG_RESULT_8[] = {
	 { "ABM1_HG_RESULT_8", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmABM0_DC_ABM1_HG_RESULT_9[] = {
	 { "ABM1_HG_RESULT_9", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmABM0_DC_ABM1_HG_RESULT_10[] = {
	 { "ABM1_HG_RESULT_10", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmABM0_DC_ABM1_HG_RESULT_11[] = {
	 { "ABM1_HG_RESULT_11", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmABM0_DC_ABM1_HG_RESULT_12[] = {
	 { "ABM1_HG_RESULT_12", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmABM0_DC_ABM1_HG_RESULT_13[] = {
	 { "ABM1_HG_RESULT_13", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmABM0_DC_ABM1_HG_RESULT_14[] = {
	 { "ABM1_HG_RESULT_14", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmABM0_DC_ABM1_HG_RESULT_15[] = {
	 { "ABM1_HG_RESULT_15", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmABM0_DC_ABM1_HG_RESULT_16[] = {
	 { "ABM1_HG_RESULT_16", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmABM0_DC_ABM1_HG_RESULT_17[] = {
	 { "ABM1_HG_RESULT_17", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmABM0_DC_ABM1_HG_RESULT_18[] = {
	 { "ABM1_HG_RESULT_18", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmABM0_DC_ABM1_HG_RESULT_19[] = {
	 { "ABM1_HG_RESULT_19", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmABM0_DC_ABM1_HG_RESULT_20[] = {
	 { "ABM1_HG_RESULT_20", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmABM0_DC_ABM1_HG_RESULT_21[] = {
	 { "ABM1_HG_RESULT_21", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmABM0_DC_ABM1_HG_RESULT_22[] = {
	 { "ABM1_HG_RESULT_22", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmABM0_DC_ABM1_HG_RESULT_23[] = {
	 { "ABM1_HG_RESULT_23", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmABM0_DC_ABM1_HG_RESULT_24[] = {
	 { "ABM1_HG_RESULT_24", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmABM0_DC_ABM1_BL_MASTER_LOCK[] = {
	 { "ABM1_BL_MASTER_LOCK", 31, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmABM1_BL1_PWM_AMBIENT_LIGHT_LEVEL[] = {
	 { "BL1_PWM_AMBIENT_LIGHT_LEVEL", 0, 16, &umr_bitfield_default },
};
static struct umr_bitfield mmABM1_BL1_PWM_USER_LEVEL[] = {
	 { "BL1_PWM_USER_LEVEL", 0, 16, &umr_bitfield_default },
};
static struct umr_bitfield mmABM1_BL1_PWM_TARGET_ABM_LEVEL[] = {
	 { "BL1_PWM_TARGET_ABM_LEVEL", 0, 16, &umr_bitfield_default },
};
static struct umr_bitfield mmABM1_BL1_PWM_CURRENT_ABM_LEVEL[] = {
	 { "BL1_PWM_CURRENT_ABM_LEVEL", 0, 16, &umr_bitfield_default },
};
static struct umr_bitfield mmABM1_BL1_PWM_FINAL_DUTY_CYCLE[] = {
	 { "BL1_PWM_FINAL_DUTY_CYCLE", 0, 16, &umr_bitfield_default },
};
static struct umr_bitfield mmABM1_BL1_PWM_MINIMUM_DUTY_CYCLE[] = {
	 { "BL1_PWM_MINIMUM_DUTY_CYCLE", 0, 16, &umr_bitfield_default },
};
static struct umr_bitfield mmABM1_BL1_PWM_ABM_CNTL[] = {
	 { "BL1_PWM_USE_ABM_EN", 0, 0, &umr_bitfield_default },
	 { "BL1_PWM_USE_AMBIENT_LEVEL_EN", 1, 1, &umr_bitfield_default },
	 { "BL1_PWM_AUTO_UPDATE_CURRENT_ABM_LEVEL_EN", 2, 2, &umr_bitfield_default },
	 { "BL1_PWM_AUTO_CALC_FINAL_DUTY_CYCLE_EN", 3, 3, &umr_bitfield_default },
	 { "BL1_PWM_AUTO_UPDATE_CURRENT_ABM_STEP_SIZE", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmABM1_BL1_PWM_BL_UPDATE_SAMPLE_RATE[] = {
	 { "BL1_PWM_BL_UPDATE_SAMPLE_RATE_COUNT_EN", 0, 0, &umr_bitfield_default },
	 { "BL1_PWM_BL_UPDATE_RESET_SAMPLE_RATE_FRAME_COUNTER", 1, 1, &umr_bitfield_default },
	 { "BL1_PWM_BL_UPDATE_SAMPLE_RATE_FRAME_COUNT", 8, 15, &umr_bitfield_default },
	 { "BL1_PWM_BL_UPDATE_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET", 16, 23, &umr_bitfield_default },
	 { "ABM1_HGLS_REG_LOCK", 31, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmABM1_BL1_PWM_GRP2_REG_LOCK[] = {
	 { "BL1_PWM_GRP2_REG_LOCK", 0, 0, &umr_bitfield_default },
	 { "BL1_PWM_GRP2_REG_UPDATE_PENDING", 8, 8, &umr_bitfield_default },
	 { "BL1_PWM_GRP2_UPDATE_AT_FRAME_START", 16, 16, &umr_bitfield_default },
	 { "BL1_PWM_GRP2_FRAME_START_DISP_SEL", 17, 19, &umr_bitfield_default },
	 { "BL1_PWM_GRP2_READBACK_DB_REG_VALUE_EN", 24, 24, &umr_bitfield_default },
	 { "BL1_PWM_GRP2_IGNORE_MASTER_LOCK_EN", 31, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmABM1_DC_ABM1_CNTL[] = {
	 { "ABM1_EN", 0, 0, &umr_bitfield_default },
	 { "ABM1_SOURCE_SELECT", 8, 10, &umr_bitfield_default },
};
static struct umr_bitfield mmABM1_DC_ABM1_IPCSC_COEFF_SEL[] = {
	 { "ABM1_IPCSC_COEFF_SEL_B", 0, 3, &umr_bitfield_default },
	 { "ABM1_IPCSC_COEFF_SEL_G", 8, 11, &umr_bitfield_default },
	 { "ABM1_IPCSC_COEFF_SEL_R", 16, 19, &umr_bitfield_default },
	 { "ABM1_HGLS_REG_LOCK", 31, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmABM1_DC_ABM1_ACE_OFFSET_SLOPE_0[] = {
	 { "ABM1_ACE_SLOPE_0", 0, 14, &umr_bitfield_default },
	 { "ABM1_ACE_OFFSET_0", 16, 26, &umr_bitfield_default },
	 { "ABM1_ACE_LOCK", 31, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmABM1_DC_ABM1_ACE_OFFSET_SLOPE_1[] = {
	 { "ABM1_ACE_SLOPE_1", 0, 14, &umr_bitfield_default },
	 { "ABM1_ACE_OFFSET_1", 16, 26, &umr_bitfield_default },
	 { "ABM1_ACE_LOCK", 31, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmABM1_DC_ABM1_ACE_OFFSET_SLOPE_2[] = {
	 { "ABM1_ACE_SLOPE_2", 0, 14, &umr_bitfield_default },
	 { "ABM1_ACE_OFFSET_2", 16, 26, &umr_bitfield_default },
	 { "ABM1_ACE_LOCK", 31, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmABM1_DC_ABM1_ACE_OFFSET_SLOPE_3[] = {
	 { "ABM1_ACE_SLOPE_3", 0, 14, &umr_bitfield_default },
	 { "ABM1_ACE_OFFSET_3", 16, 26, &umr_bitfield_default },
	 { "ABM1_ACE_LOCK", 31, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmABM1_DC_ABM1_ACE_OFFSET_SLOPE_4[] = {
	 { "ABM1_ACE_SLOPE_4", 0, 14, &umr_bitfield_default },
	 { "ABM1_ACE_OFFSET_4", 16, 26, &umr_bitfield_default },
	 { "ABM1_ACE_LOCK", 31, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmABM1_DC_ABM1_ACE_THRES_12[] = {
	 { "ABM1_ACE_THRES_1", 0, 9, &umr_bitfield_default },
	 { "ABM1_ACE_THRES_2", 16, 25, &umr_bitfield_default },
	 { "ABM1_ACE_LOCK", 31, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmABM1_DC_ABM1_ACE_THRES_34[] = {
	 { "ABM1_ACE_THRES_3", 0, 9, &umr_bitfield_default },
	 { "ABM1_ACE_THRES_4", 16, 25, &umr_bitfield_default },
	 { "ABM1_ACE_IGNORE_MASTER_LOCK_EN", 28, 28, &umr_bitfield_default },
	 { "ABM1_ACE_READBACK_DB_REG_VALUE_EN", 29, 29, &umr_bitfield_default },
	 { "ABM1_ACE_DBUF_REG_UPDATE_PENDING", 30, 30, &umr_bitfield_default },
	 { "ABM1_ACE_LOCK", 31, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmABM1_DC_ABM1_ACE_CNTL_MISC[] = {
	 { "ABM1_ACE_REG_WR_MISSED_FRAME", 0, 0, &umr_bitfield_default },
	 { "ABM1_ACE_REG_WR_MISSED_FRAME_CLEAR", 8, 8, &umr_bitfield_default },
};
static struct umr_bitfield mmABM1_DC_ABM1_HGLS_REG_READ_PROGRESS[] = {
	 { "ABM1_HG_REG_READ_IN_PROGRESS", 0, 0, &umr_bitfield_default },
	 { "ABM1_LS_REG_READ_IN_PROGRESS", 1, 1, &umr_bitfield_default },
	 { "ABM1_BL_REG_READ_IN_PROGRESS", 2, 2, &umr_bitfield_default },
	 { "ABM1_HG_REG_READ_MISSED_FRAME", 8, 8, &umr_bitfield_default },
	 { "ABM1_LS_REG_READ_MISSED_FRAME", 9, 9, &umr_bitfield_default },
	 { "ABM1_BL_REG_READ_MISSED_FRAME", 10, 10, &umr_bitfield_default },
	 { "ABM1_HG_REG_READ_MISSED_FRAME_CLEAR", 16, 16, &umr_bitfield_default },
	 { "ABM1_LS_REG_READ_MISSED_FRAME_CLEAR", 24, 24, &umr_bitfield_default },
	 { "ABM1_BL_REG_READ_MISSED_FRAME_CLEAR", 31, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmABM1_DC_ABM1_HG_MISC_CTRL[] = {
	 { "ABM1_HG_NUM_OF_BINS_SEL", 0, 1, &umr_bitfield_default },
	 { "ABM1_HG_VMAX_SEL", 8, 8, &umr_bitfield_default },
	 { "ABM1_HG_FINE_MODE_BIN_SEL", 12, 12, &umr_bitfield_default },
	 { "ABM1_HG_BIN_BITWIDTH_SIZE_SEL", 16, 17, &umr_bitfield_default },
	 { "ABM1_OVR_SCAN_PIXEL_PROCESS_EN", 20, 20, &umr_bitfield_default },
	 { "ABM1_DBUF_HGLS_READBACK_DB_REG_VALUE_EN", 23, 23, &umr_bitfield_default },
	 { "ABM1_DBUF_HGLS_REG_FRAME_START_DISP_SEL", 24, 26, &umr_bitfield_default },
	 { "ABM1_DBUF_HGLS_REG_UPDATE_AT_FRAME_START", 28, 28, &umr_bitfield_default },
	 { "ABM1_HGLS_IGNORE_MASTER_LOCK_EN", 29, 29, &umr_bitfield_default },
	 { "ABM1_DBUF_HGLS_REG_UPDATE_PENDING", 30, 30, &umr_bitfield_default },
	 { "ABM1_HGLS_REG_LOCK", 31, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmABM1_DC_ABM1_LS_SUM_OF_LUMA[] = {
	 { "ABM1_LS_SUM_OF_LUMA", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmABM1_DC_ABM1_LS_MIN_MAX_LUMA[] = {
	 { "ABM1_LS_MIN_LUMA", 0, 9, &umr_bitfield_default },
	 { "ABM1_LS_MAX_LUMA", 16, 25, &umr_bitfield_default },
};
static struct umr_bitfield mmABM1_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA[] = {
	 { "ABM1_LS_FILTERED_MIN_LUMA", 0, 9, &umr_bitfield_default },
	 { "ABM1_LS_FILTERED_MAX_LUMA", 16, 25, &umr_bitfield_default },
};
static struct umr_bitfield mmABM1_DC_ABM1_LS_PIXEL_COUNT[] = {
	 { "ABM1_LS_PIXEL_COUNT", 0, 23, &umr_bitfield_default },
	 { "ABM1_LS_SUM_OF_LUMA_MSB", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmABM1_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES[] = {
	 { "ABM1_LS_MIN_PIXEL_VALUE_THRES", 0, 9, &umr_bitfield_default },
	 { "ABM1_LS_MAX_PIXEL_VALUE_THRES", 16, 25, &umr_bitfield_default },
	 { "ABM1_HGLS_REG_LOCK", 31, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmABM1_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT[] = {
	 { "ABM1_LS_MIN_PIXEL_VALUE_COUNT", 0, 23, &umr_bitfield_default },
};
static struct umr_bitfield mmABM1_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT[] = {
	 { "ABM1_LS_MAX_PIXEL_VALUE_COUNT", 0, 23, &umr_bitfield_default },
};
static struct umr_bitfield mmABM1_DC_ABM1_HG_SAMPLE_RATE[] = {
	 { "ABM1_HG_SAMPLE_RATE_COUNT_EN", 0, 0, &umr_bitfield_default },
	 { "ABM1_HG_RESET_SAMPLE_RATE_FRAME_COUNTER", 1, 1, &umr_bitfield_default },
	 { "ABM1_HG_SAMPLE_RATE_FRAME_COUNT", 8, 15, &umr_bitfield_default },
	 { "ABM1_HG_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET", 16, 23, &umr_bitfield_default },
	 { "ABM1_HGLS_REG_LOCK", 31, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmABM1_DC_ABM1_LS_SAMPLE_RATE[] = {
	 { "ABM1_LS_SAMPLE_RATE_COUNT_EN", 0, 0, &umr_bitfield_default },
	 { "ABM1_LS_RESET_SAMPLE_RATE_FRAME_COUNTER", 1, 1, &umr_bitfield_default },
	 { "ABM1_LS_SAMPLE_RATE_FRAME_COUNT", 8, 15, &umr_bitfield_default },
	 { "ABM1_LS_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET", 16, 23, &umr_bitfield_default },
	 { "ABM1_HGLS_REG_LOCK", 31, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmABM1_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG[] = {
	 { "ABM1_HG_BIN_1_32_SHIFT_FLAG", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmABM1_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX[] = {
	 { "ABM1_HG_BIN_1_8_SHIFT_INDEX", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmABM1_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX[] = {
	 { "ABM1_HG_BIN_9_16_SHIFT_INDEX", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmABM1_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX[] = {
	 { "ABM1_HG_BIN_17_24_SHIFT_INDEX", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmABM1_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX[] = {
	 { "ABM1_HG_BIN_25_32_SHIFT_INDEX", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmABM1_DC_ABM1_HG_RESULT_1[] = {
	 { "ABM1_HG_RESULT_1", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmABM1_DC_ABM1_HG_RESULT_2[] = {
	 { "ABM1_HG_RESULT_2", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmABM1_DC_ABM1_HG_RESULT_3[] = {
	 { "ABM1_HG_RESULT_3", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmABM1_DC_ABM1_HG_RESULT_4[] = {
	 { "ABM1_HG_RESULT_4", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmABM1_DC_ABM1_HG_RESULT_5[] = {
	 { "ABM1_HG_RESULT_5", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmABM1_DC_ABM1_HG_RESULT_6[] = {
	 { "ABM1_HG_RESULT_6", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmABM1_DC_ABM1_HG_RESULT_7[] = {
	 { "ABM1_HG_RESULT_7", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmABM1_DC_ABM1_HG_RESULT_8[] = {
	 { "ABM1_HG_RESULT_8", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmABM1_DC_ABM1_HG_RESULT_9[] = {
	 { "ABM1_HG_RESULT_9", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmABM1_DC_ABM1_HG_RESULT_10[] = {
	 { "ABM1_HG_RESULT_10", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmABM1_DC_ABM1_HG_RESULT_11[] = {
	 { "ABM1_HG_RESULT_11", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmABM1_DC_ABM1_HG_RESULT_12[] = {
	 { "ABM1_HG_RESULT_12", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmABM1_DC_ABM1_HG_RESULT_13[] = {
	 { "ABM1_HG_RESULT_13", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmABM1_DC_ABM1_HG_RESULT_14[] = {
	 { "ABM1_HG_RESULT_14", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmABM1_DC_ABM1_HG_RESULT_15[] = {
	 { "ABM1_HG_RESULT_15", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmABM1_DC_ABM1_HG_RESULT_16[] = {
	 { "ABM1_HG_RESULT_16", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmABM1_DC_ABM1_HG_RESULT_17[] = {
	 { "ABM1_HG_RESULT_17", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmABM1_DC_ABM1_HG_RESULT_18[] = {
	 { "ABM1_HG_RESULT_18", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmABM1_DC_ABM1_HG_RESULT_19[] = {
	 { "ABM1_HG_RESULT_19", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmABM1_DC_ABM1_HG_RESULT_20[] = {
	 { "ABM1_HG_RESULT_20", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmABM1_DC_ABM1_HG_RESULT_21[] = {
	 { "ABM1_HG_RESULT_21", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmABM1_DC_ABM1_HG_RESULT_22[] = {
	 { "ABM1_HG_RESULT_22", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmABM1_DC_ABM1_HG_RESULT_23[] = {
	 { "ABM1_HG_RESULT_23", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmABM1_DC_ABM1_HG_RESULT_24[] = {
	 { "ABM1_HG_RESULT_24", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmABM1_DC_ABM1_BL_MASTER_LOCK[] = {
	 { "ABM1_BL_MASTER_LOCK", 31, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmFMT0_FMT_CLAMP_COMPONENT_R[] = {
	 { "FMT_CLAMP_LOWER_R", 0, 15, &umr_bitfield_default },
	 { "FMT_CLAMP_UPPER_R", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmFMT0_FMT_CLAMP_COMPONENT_G[] = {
	 { "FMT_CLAMP_LOWER_G", 0, 15, &umr_bitfield_default },
	 { "FMT_CLAMP_UPPER_G", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmFMT0_FMT_CLAMP_COMPONENT_B[] = {
	 { "FMT_CLAMP_LOWER_B", 0, 15, &umr_bitfield_default },
	 { "FMT_CLAMP_UPPER_B", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmFMT0_FMT_DYNAMIC_EXP_CNTL[] = {
	 { "FMT_DYNAMIC_EXP_EN", 0, 0, &umr_bitfield_default },
	 { "FMT_DYNAMIC_EXP_MODE", 4, 4, &umr_bitfield_default },
};
static struct umr_bitfield mmFMT0_FMT_CONTROL[] = {
	 { "FMT_STEREOSYNC_OVERRIDE", 0, 0, &umr_bitfield_default },
	 { "FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX", 8, 11, &umr_bitfield_default },
	 { "FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP", 12, 13, &umr_bitfield_default },
	 { "FMT_PIXEL_ENCODING", 16, 17, &umr_bitfield_default },
	 { "FMT_SUBSAMPLING_MODE", 18, 19, &umr_bitfield_default },
	 { "FMT_SUBSAMPLING_ORDER", 20, 20, &umr_bitfield_default },
	 { "FMT_CBCR_BIT_REDUCTION_BYPASS", 21, 21, &umr_bitfield_default },
	 { "FMT_DOUBLE_BUFFER_REG_UPDATE_PENDING", 24, 24, &umr_bitfield_default },
};
static struct umr_bitfield mmFMT0_FMT_BIT_DEPTH_CONTROL[] = {
	 { "FMT_TRUNCATE_EN", 0, 0, &umr_bitfield_default },
	 { "FMT_TRUNCATE_MODE", 1, 1, &umr_bitfield_default },
	 { "FMT_TRUNCATE_DEPTH", 4, 5, &umr_bitfield_default },
	 { "FMT_SPATIAL_DITHER_EN", 8, 8, &umr_bitfield_default },
	 { "FMT_SPATIAL_DITHER_MODE", 9, 10, &umr_bitfield_default },
	 { "FMT_SPATIAL_DITHER_DEPTH", 11, 12, &umr_bitfield_default },
	 { "FMT_FRAME_RANDOM_ENABLE", 13, 13, &umr_bitfield_default },
	 { "FMT_RGB_RANDOM_ENABLE", 14, 14, &umr_bitfield_default },
	 { "FMT_HIGHPASS_RANDOM_ENABLE", 15, 15, &umr_bitfield_default },
	 { "FMT_TEMPORAL_DITHER_EN", 16, 16, &umr_bitfield_default },
	 { "FMT_TEMPORAL_DITHER_DEPTH", 17, 18, &umr_bitfield_default },
	 { "FMT_TEMPORAL_DITHER_OFFSET", 21, 22, &umr_bitfield_default },
	 { "FMT_TEMPORAL_LEVEL", 24, 24, &umr_bitfield_default },
	 { "FMT_TEMPORAL_DITHER_RESET", 25, 25, &umr_bitfield_default },
	 { "FMT_25FRC_SEL", 26, 27, &umr_bitfield_default },
	 { "FMT_50FRC_SEL", 28, 29, &umr_bitfield_default },
	 { "FMT_75FRC_SEL", 30, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmFMT0_FMT_DITHER_RAND_R_SEED[] = {
	 { "FMT_RAND_R_SEED", 0, 7, &umr_bitfield_default },
	 { "FMT_OFFSET_R_CR", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmFMT0_FMT_DITHER_RAND_G_SEED[] = {
	 { "FMT_RAND_G_SEED", 0, 7, &umr_bitfield_default },
	 { "FMT_OFFSET_G_Y", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmFMT0_FMT_DITHER_RAND_B_SEED[] = {
	 { "FMT_RAND_B_SEED", 0, 7, &umr_bitfield_default },
	 { "FMT_OFFSET_B_CB", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmFMT0_FMT_CLAMP_CNTL[] = {
	 { "FMT_CLAMP_DATA_EN", 0, 0, &umr_bitfield_default },
	 { "FMT_CLAMP_COLOR_FORMAT", 16, 18, &umr_bitfield_default },
};
static struct umr_bitfield mmFMT0_FMT_SIDE_BY_SIDE_STEREO_CONTROL[] = {
	 { "FMT_SIDE_BY_SIDE_STEREO_ACTIVE_WIDTH", 0, 12, &umr_bitfield_default },
};
static struct umr_bitfield mmFMT0_FMT_MAP420_MEMORY_CONTROL[] = {
	 { "FMT_MAP420MEM_PWR_FORCE", 0, 1, &umr_bitfield_default },
	 { "FMT_MAP420MEM_PWR_DIS", 4, 4, &umr_bitfield_default },
	 { "FMT_MAP420MEM_PWR_STATE", 8, 9, &umr_bitfield_default },
};
static struct umr_bitfield mmOPPBUF0_OPPBUF_CONTROL[] = {
	 { "OPPBUF_ACTIVE_WIDTH", 0, 13, &umr_bitfield_default },
	 { "OPPBUF_DISPLAY_SEGMENTATION", 16, 18, &umr_bitfield_default },
	 { "OPPBUF_OVERLAP_PIXEL_NUM", 20, 23, &umr_bitfield_default },
	 { "OPPBUF_PIXEL_REPETITION", 24, 27, &umr_bitfield_default },
	 { "OPPBUF_DOUBLE_BUFFER_PENDING", 28, 28, &umr_bitfield_default },
};
static struct umr_bitfield mmOPPBUF0_OPPBUF_3D_PARAMETERS_0[] = {
	 { "OPPBUF_3D_VACT_SPACE1_SIZE", 0, 9, &umr_bitfield_default },
	 { "OPPBUF_3D_VACT_SPACE2_SIZE", 10, 19, &umr_bitfield_default },
	 { "OPPBUF_DUMMY_DATA_R", 20, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmOPPBUF0_OPPBUF_3D_PARAMETERS_1[] = {
	 { "OPPBUF_DUMMY_DATA_G", 0, 11, &umr_bitfield_default },
	 { "OPPBUF_DUMMY_DATA_B", 16, 27, &umr_bitfield_default },
};
static struct umr_bitfield mmOPP_PIPE0_OPP_PIPE_CONTROL[] = {
	 { "OPP_PIPE_CLOCK_EN", 0, 0, &umr_bitfield_default },
	 { "OPP_PIPE_CLOCK_ON", 1, 1, &umr_bitfield_default },
	 { "OPP_PIPE_DIGITAL_BYPASS_EN", 4, 4, &umr_bitfield_default },
};
static struct umr_bitfield mmOPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL[] = {
	 { "OPP_PIPE_CRC_EN", 0, 0, &umr_bitfield_default },
	 { "OPP_PIPE_CRC_CONT_EN", 4, 4, &umr_bitfield_default },
	 { "OPP_PIPE_CRC_STEREO_MODE", 8, 9, &umr_bitfield_default },
	 { "OPP_PIPE_CRC_STEREO_EN", 10, 10, &umr_bitfield_default },
	 { "OPP_PIPE_CRC_INTERLACE_MODE", 12, 13, &umr_bitfield_default },
	 { "OPP_PIPE_CRC_INTERLACE_EN", 14, 14, &umr_bitfield_default },
	 { "OPP_PIPE_CRC_PIXEL_SELECT", 20, 21, &umr_bitfield_default },
	 { "OPP_PIPE_CRC_SOURCE_SELECT", 24, 24, &umr_bitfield_default },
	 { "OPP_PIPE_CRC_ONE_SHOT_PENDING", 28, 28, &umr_bitfield_default },
};
static struct umr_bitfield mmOPP_PIPE_CRC0_OPP_PIPE_CRC_MASK[] = {
	 { "OPP_PIPE_CRC_MASK", 0, 15, &umr_bitfield_default },
};
static struct umr_bitfield mmOPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT0[] = {
	 { "OPP_PIPE_CRC_RESULT_A", 0, 15, &umr_bitfield_default },
	 { "OPP_PIPE_CRC_RESULT_R", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmOPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT1[] = {
	 { "OPP_PIPE_CRC_RESULT_G", 0, 15, &umr_bitfield_default },
	 { "OPP_PIPE_CRC_RESULT_B", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmOPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT2[] = {
	 { "OPP_PIPE_CRC_RESULT_C", 0, 15, &umr_bitfield_default },
};
static struct umr_bitfield mmFMT1_FMT_CLAMP_COMPONENT_R[] = {
	 { "FMT_CLAMP_LOWER_R", 0, 15, &umr_bitfield_default },
	 { "FMT_CLAMP_UPPER_R", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmFMT1_FMT_CLAMP_COMPONENT_G[] = {
	 { "FMT_CLAMP_LOWER_G", 0, 15, &umr_bitfield_default },
	 { "FMT_CLAMP_UPPER_G", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmFMT1_FMT_CLAMP_COMPONENT_B[] = {
	 { "FMT_CLAMP_LOWER_B", 0, 15, &umr_bitfield_default },
	 { "FMT_CLAMP_UPPER_B", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmFMT1_FMT_DYNAMIC_EXP_CNTL[] = {
	 { "FMT_DYNAMIC_EXP_EN", 0, 0, &umr_bitfield_default },
	 { "FMT_DYNAMIC_EXP_MODE", 4, 4, &umr_bitfield_default },
};
static struct umr_bitfield mmFMT1_FMT_CONTROL[] = {
	 { "FMT_STEREOSYNC_OVERRIDE", 0, 0, &umr_bitfield_default },
	 { "FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX", 8, 11, &umr_bitfield_default },
	 { "FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP", 12, 13, &umr_bitfield_default },
	 { "FMT_PIXEL_ENCODING", 16, 17, &umr_bitfield_default },
	 { "FMT_SUBSAMPLING_MODE", 18, 19, &umr_bitfield_default },
	 { "FMT_SUBSAMPLING_ORDER", 20, 20, &umr_bitfield_default },
	 { "FMT_CBCR_BIT_REDUCTION_BYPASS", 21, 21, &umr_bitfield_default },
	 { "FMT_DOUBLE_BUFFER_REG_UPDATE_PENDING", 24, 24, &umr_bitfield_default },
};
static struct umr_bitfield mmFMT1_FMT_BIT_DEPTH_CONTROL[] = {
	 { "FMT_TRUNCATE_EN", 0, 0, &umr_bitfield_default },
	 { "FMT_TRUNCATE_MODE", 1, 1, &umr_bitfield_default },
	 { "FMT_TRUNCATE_DEPTH", 4, 5, &umr_bitfield_default },
	 { "FMT_SPATIAL_DITHER_EN", 8, 8, &umr_bitfield_default },
	 { "FMT_SPATIAL_DITHER_MODE", 9, 10, &umr_bitfield_default },
	 { "FMT_SPATIAL_DITHER_DEPTH", 11, 12, &umr_bitfield_default },
	 { "FMT_FRAME_RANDOM_ENABLE", 13, 13, &umr_bitfield_default },
	 { "FMT_RGB_RANDOM_ENABLE", 14, 14, &umr_bitfield_default },
	 { "FMT_HIGHPASS_RANDOM_ENABLE", 15, 15, &umr_bitfield_default },
	 { "FMT_TEMPORAL_DITHER_EN", 16, 16, &umr_bitfield_default },
	 { "FMT_TEMPORAL_DITHER_DEPTH", 17, 18, &umr_bitfield_default },
	 { "FMT_TEMPORAL_DITHER_OFFSET", 21, 22, &umr_bitfield_default },
	 { "FMT_TEMPORAL_LEVEL", 24, 24, &umr_bitfield_default },
	 { "FMT_TEMPORAL_DITHER_RESET", 25, 25, &umr_bitfield_default },
	 { "FMT_25FRC_SEL", 26, 27, &umr_bitfield_default },
	 { "FMT_50FRC_SEL", 28, 29, &umr_bitfield_default },
	 { "FMT_75FRC_SEL", 30, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmFMT1_FMT_DITHER_RAND_R_SEED[] = {
	 { "FMT_RAND_R_SEED", 0, 7, &umr_bitfield_default },
	 { "FMT_OFFSET_R_CR", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmFMT1_FMT_DITHER_RAND_G_SEED[] = {
	 { "FMT_RAND_G_SEED", 0, 7, &umr_bitfield_default },
	 { "FMT_OFFSET_G_Y", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmFMT1_FMT_DITHER_RAND_B_SEED[] = {
	 { "FMT_RAND_B_SEED", 0, 7, &umr_bitfield_default },
	 { "FMT_OFFSET_B_CB", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmFMT1_FMT_CLAMP_CNTL[] = {
	 { "FMT_CLAMP_DATA_EN", 0, 0, &umr_bitfield_default },
	 { "FMT_CLAMP_COLOR_FORMAT", 16, 18, &umr_bitfield_default },
};
static struct umr_bitfield mmFMT1_FMT_SIDE_BY_SIDE_STEREO_CONTROL[] = {
	 { "FMT_SIDE_BY_SIDE_STEREO_ACTIVE_WIDTH", 0, 12, &umr_bitfield_default },
};
static struct umr_bitfield mmFMT1_FMT_MAP420_MEMORY_CONTROL[] = {
	 { "FMT_MAP420MEM_PWR_FORCE", 0, 1, &umr_bitfield_default },
	 { "FMT_MAP420MEM_PWR_DIS", 4, 4, &umr_bitfield_default },
	 { "FMT_MAP420MEM_PWR_STATE", 8, 9, &umr_bitfield_default },
};
static struct umr_bitfield mmOPPBUF1_OPPBUF_CONTROL[] = {
	 { "OPPBUF_ACTIVE_WIDTH", 0, 13, &umr_bitfield_default },
	 { "OPPBUF_DISPLAY_SEGMENTATION", 16, 18, &umr_bitfield_default },
	 { "OPPBUF_OVERLAP_PIXEL_NUM", 20, 23, &umr_bitfield_default },
	 { "OPPBUF_PIXEL_REPETITION", 24, 27, &umr_bitfield_default },
	 { "OPPBUF_DOUBLE_BUFFER_PENDING", 28, 28, &umr_bitfield_default },
};
static struct umr_bitfield mmOPPBUF1_OPPBUF_3D_PARAMETERS_0[] = {
	 { "OPPBUF_3D_VACT_SPACE1_SIZE", 0, 9, &umr_bitfield_default },
	 { "OPPBUF_3D_VACT_SPACE2_SIZE", 10, 19, &umr_bitfield_default },
	 { "OPPBUF_DUMMY_DATA_R", 20, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmOPPBUF1_OPPBUF_3D_PARAMETERS_1[] = {
	 { "OPPBUF_DUMMY_DATA_G", 0, 11, &umr_bitfield_default },
	 { "OPPBUF_DUMMY_DATA_B", 16, 27, &umr_bitfield_default },
};
static struct umr_bitfield mmOPP_PIPE1_OPP_PIPE_CONTROL[] = {
	 { "OPP_PIPE_CLOCK_EN", 0, 0, &umr_bitfield_default },
	 { "OPP_PIPE_CLOCK_ON", 1, 1, &umr_bitfield_default },
	 { "OPP_PIPE_DIGITAL_BYPASS_EN", 4, 4, &umr_bitfield_default },
};
static struct umr_bitfield mmOPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL[] = {
	 { "OPP_PIPE_CRC_EN", 0, 0, &umr_bitfield_default },
	 { "OPP_PIPE_CRC_CONT_EN", 4, 4, &umr_bitfield_default },
	 { "OPP_PIPE_CRC_STEREO_MODE", 8, 9, &umr_bitfield_default },
	 { "OPP_PIPE_CRC_STEREO_EN", 10, 10, &umr_bitfield_default },
	 { "OPP_PIPE_CRC_INTERLACE_MODE", 12, 13, &umr_bitfield_default },
	 { "OPP_PIPE_CRC_INTERLACE_EN", 14, 14, &umr_bitfield_default },
	 { "OPP_PIPE_CRC_PIXEL_SELECT", 20, 21, &umr_bitfield_default },
	 { "OPP_PIPE_CRC_SOURCE_SELECT", 24, 24, &umr_bitfield_default },
	 { "OPP_PIPE_CRC_ONE_SHOT_PENDING", 28, 28, &umr_bitfield_default },
};
static struct umr_bitfield mmOPP_PIPE_CRC1_OPP_PIPE_CRC_MASK[] = {
	 { "OPP_PIPE_CRC_MASK", 0, 15, &umr_bitfield_default },
};
static struct umr_bitfield mmOPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT0[] = {
	 { "OPP_PIPE_CRC_RESULT_A", 0, 15, &umr_bitfield_default },
	 { "OPP_PIPE_CRC_RESULT_R", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmOPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT1[] = {
	 { "OPP_PIPE_CRC_RESULT_G", 0, 15, &umr_bitfield_default },
	 { "OPP_PIPE_CRC_RESULT_B", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmOPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT2[] = {
	 { "OPP_PIPE_CRC_RESULT_C", 0, 15, &umr_bitfield_default },
};
static struct umr_bitfield mmFMT2_FMT_CLAMP_COMPONENT_R[] = {
	 { "FMT_CLAMP_LOWER_R", 0, 15, &umr_bitfield_default },
	 { "FMT_CLAMP_UPPER_R", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmFMT2_FMT_CLAMP_COMPONENT_G[] = {
	 { "FMT_CLAMP_LOWER_G", 0, 15, &umr_bitfield_default },
	 { "FMT_CLAMP_UPPER_G", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmFMT2_FMT_CLAMP_COMPONENT_B[] = {
	 { "FMT_CLAMP_LOWER_B", 0, 15, &umr_bitfield_default },
	 { "FMT_CLAMP_UPPER_B", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmFMT2_FMT_DYNAMIC_EXP_CNTL[] = {
	 { "FMT_DYNAMIC_EXP_EN", 0, 0, &umr_bitfield_default },
	 { "FMT_DYNAMIC_EXP_MODE", 4, 4, &umr_bitfield_default },
};
static struct umr_bitfield mmFMT2_FMT_CONTROL[] = {
	 { "FMT_STEREOSYNC_OVERRIDE", 0, 0, &umr_bitfield_default },
	 { "FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX", 8, 11, &umr_bitfield_default },
	 { "FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP", 12, 13, &umr_bitfield_default },
	 { "FMT_PIXEL_ENCODING", 16, 17, &umr_bitfield_default },
	 { "FMT_SUBSAMPLING_MODE", 18, 19, &umr_bitfield_default },
	 { "FMT_SUBSAMPLING_ORDER", 20, 20, &umr_bitfield_default },
	 { "FMT_CBCR_BIT_REDUCTION_BYPASS", 21, 21, &umr_bitfield_default },
	 { "FMT_DOUBLE_BUFFER_REG_UPDATE_PENDING", 24, 24, &umr_bitfield_default },
};
static struct umr_bitfield mmFMT2_FMT_BIT_DEPTH_CONTROL[] = {
	 { "FMT_TRUNCATE_EN", 0, 0, &umr_bitfield_default },
	 { "FMT_TRUNCATE_MODE", 1, 1, &umr_bitfield_default },
	 { "FMT_TRUNCATE_DEPTH", 4, 5, &umr_bitfield_default },
	 { "FMT_SPATIAL_DITHER_EN", 8, 8, &umr_bitfield_default },
	 { "FMT_SPATIAL_DITHER_MODE", 9, 10, &umr_bitfield_default },
	 { "FMT_SPATIAL_DITHER_DEPTH", 11, 12, &umr_bitfield_default },
	 { "FMT_FRAME_RANDOM_ENABLE", 13, 13, &umr_bitfield_default },
	 { "FMT_RGB_RANDOM_ENABLE", 14, 14, &umr_bitfield_default },
	 { "FMT_HIGHPASS_RANDOM_ENABLE", 15, 15, &umr_bitfield_default },
	 { "FMT_TEMPORAL_DITHER_EN", 16, 16, &umr_bitfield_default },
	 { "FMT_TEMPORAL_DITHER_DEPTH", 17, 18, &umr_bitfield_default },
	 { "FMT_TEMPORAL_DITHER_OFFSET", 21, 22, &umr_bitfield_default },
	 { "FMT_TEMPORAL_LEVEL", 24, 24, &umr_bitfield_default },
	 { "FMT_TEMPORAL_DITHER_RESET", 25, 25, &umr_bitfield_default },
	 { "FMT_25FRC_SEL", 26, 27, &umr_bitfield_default },
	 { "FMT_50FRC_SEL", 28, 29, &umr_bitfield_default },
	 { "FMT_75FRC_SEL", 30, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmFMT2_FMT_DITHER_RAND_R_SEED[] = {
	 { "FMT_RAND_R_SEED", 0, 7, &umr_bitfield_default },
	 { "FMT_OFFSET_R_CR", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmFMT2_FMT_DITHER_RAND_G_SEED[] = {
	 { "FMT_RAND_G_SEED", 0, 7, &umr_bitfield_default },
	 { "FMT_OFFSET_G_Y", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmFMT2_FMT_DITHER_RAND_B_SEED[] = {
	 { "FMT_RAND_B_SEED", 0, 7, &umr_bitfield_default },
	 { "FMT_OFFSET_B_CB", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmFMT2_FMT_CLAMP_CNTL[] = {
	 { "FMT_CLAMP_DATA_EN", 0, 0, &umr_bitfield_default },
	 { "FMT_CLAMP_COLOR_FORMAT", 16, 18, &umr_bitfield_default },
};
static struct umr_bitfield mmFMT2_FMT_SIDE_BY_SIDE_STEREO_CONTROL[] = {
	 { "FMT_SIDE_BY_SIDE_STEREO_ACTIVE_WIDTH", 0, 12, &umr_bitfield_default },
};
static struct umr_bitfield mmFMT2_FMT_MAP420_MEMORY_CONTROL[] = {
	 { "FMT_MAP420MEM_PWR_FORCE", 0, 1, &umr_bitfield_default },
	 { "FMT_MAP420MEM_PWR_DIS", 4, 4, &umr_bitfield_default },
	 { "FMT_MAP420MEM_PWR_STATE", 8, 9, &umr_bitfield_default },
};
static struct umr_bitfield mmOPPBUF2_OPPBUF_CONTROL[] = {
	 { "OPPBUF_ACTIVE_WIDTH", 0, 13, &umr_bitfield_default },
	 { "OPPBUF_DISPLAY_SEGMENTATION", 16, 18, &umr_bitfield_default },
	 { "OPPBUF_OVERLAP_PIXEL_NUM", 20, 23, &umr_bitfield_default },
	 { "OPPBUF_PIXEL_REPETITION", 24, 27, &umr_bitfield_default },
	 { "OPPBUF_DOUBLE_BUFFER_PENDING", 28, 28, &umr_bitfield_default },
};
static struct umr_bitfield mmOPPBUF2_OPPBUF_3D_PARAMETERS_0[] = {
	 { "OPPBUF_3D_VACT_SPACE1_SIZE", 0, 9, &umr_bitfield_default },
	 { "OPPBUF_3D_VACT_SPACE2_SIZE", 10, 19, &umr_bitfield_default },
	 { "OPPBUF_DUMMY_DATA_R", 20, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmOPPBUF2_OPPBUF_3D_PARAMETERS_1[] = {
	 { "OPPBUF_DUMMY_DATA_G", 0, 11, &umr_bitfield_default },
	 { "OPPBUF_DUMMY_DATA_B", 16, 27, &umr_bitfield_default },
};
static struct umr_bitfield mmOPP_PIPE2_OPP_PIPE_CONTROL[] = {
	 { "OPP_PIPE_CLOCK_EN", 0, 0, &umr_bitfield_default },
	 { "OPP_PIPE_CLOCK_ON", 1, 1, &umr_bitfield_default },
	 { "OPP_PIPE_DIGITAL_BYPASS_EN", 4, 4, &umr_bitfield_default },
};
static struct umr_bitfield mmOPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL[] = {
	 { "OPP_PIPE_CRC_EN", 0, 0, &umr_bitfield_default },
	 { "OPP_PIPE_CRC_CONT_EN", 4, 4, &umr_bitfield_default },
	 { "OPP_PIPE_CRC_STEREO_MODE", 8, 9, &umr_bitfield_default },
	 { "OPP_PIPE_CRC_STEREO_EN", 10, 10, &umr_bitfield_default },
	 { "OPP_PIPE_CRC_INTERLACE_MODE", 12, 13, &umr_bitfield_default },
	 { "OPP_PIPE_CRC_INTERLACE_EN", 14, 14, &umr_bitfield_default },
	 { "OPP_PIPE_CRC_PIXEL_SELECT", 20, 21, &umr_bitfield_default },
	 { "OPP_PIPE_CRC_SOURCE_SELECT", 24, 24, &umr_bitfield_default },
	 { "OPP_PIPE_CRC_ONE_SHOT_PENDING", 28, 28, &umr_bitfield_default },
};
static struct umr_bitfield mmOPP_PIPE_CRC2_OPP_PIPE_CRC_MASK[] = {
	 { "OPP_PIPE_CRC_MASK", 0, 15, &umr_bitfield_default },
};
static struct umr_bitfield mmOPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT0[] = {
	 { "OPP_PIPE_CRC_RESULT_A", 0, 15, &umr_bitfield_default },
	 { "OPP_PIPE_CRC_RESULT_R", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmOPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT1[] = {
	 { "OPP_PIPE_CRC_RESULT_G", 0, 15, &umr_bitfield_default },
	 { "OPP_PIPE_CRC_RESULT_B", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmOPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT2[] = {
	 { "OPP_PIPE_CRC_RESULT_C", 0, 15, &umr_bitfield_default },
};
static struct umr_bitfield mmFMT3_FMT_CLAMP_COMPONENT_R[] = {
	 { "FMT_CLAMP_LOWER_R", 0, 15, &umr_bitfield_default },
	 { "FMT_CLAMP_UPPER_R", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmFMT3_FMT_CLAMP_COMPONENT_G[] = {
	 { "FMT_CLAMP_LOWER_G", 0, 15, &umr_bitfield_default },
	 { "FMT_CLAMP_UPPER_G", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmFMT3_FMT_CLAMP_COMPONENT_B[] = {
	 { "FMT_CLAMP_LOWER_B", 0, 15, &umr_bitfield_default },
	 { "FMT_CLAMP_UPPER_B", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmFMT3_FMT_DYNAMIC_EXP_CNTL[] = {
	 { "FMT_DYNAMIC_EXP_EN", 0, 0, &umr_bitfield_default },
	 { "FMT_DYNAMIC_EXP_MODE", 4, 4, &umr_bitfield_default },
};
static struct umr_bitfield mmFMT3_FMT_CONTROL[] = {
	 { "FMT_STEREOSYNC_OVERRIDE", 0, 0, &umr_bitfield_default },
	 { "FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX", 8, 11, &umr_bitfield_default },
	 { "FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP", 12, 13, &umr_bitfield_default },
	 { "FMT_PIXEL_ENCODING", 16, 17, &umr_bitfield_default },
	 { "FMT_SUBSAMPLING_MODE", 18, 19, &umr_bitfield_default },
	 { "FMT_SUBSAMPLING_ORDER", 20, 20, &umr_bitfield_default },
	 { "FMT_CBCR_BIT_REDUCTION_BYPASS", 21, 21, &umr_bitfield_default },
	 { "FMT_DOUBLE_BUFFER_REG_UPDATE_PENDING", 24, 24, &umr_bitfield_default },
};
static struct umr_bitfield mmFMT3_FMT_BIT_DEPTH_CONTROL[] = {
	 { "FMT_TRUNCATE_EN", 0, 0, &umr_bitfield_default },
	 { "FMT_TRUNCATE_MODE", 1, 1, &umr_bitfield_default },
	 { "FMT_TRUNCATE_DEPTH", 4, 5, &umr_bitfield_default },
	 { "FMT_SPATIAL_DITHER_EN", 8, 8, &umr_bitfield_default },
	 { "FMT_SPATIAL_DITHER_MODE", 9, 10, &umr_bitfield_default },
	 { "FMT_SPATIAL_DITHER_DEPTH", 11, 12, &umr_bitfield_default },
	 { "FMT_FRAME_RANDOM_ENABLE", 13, 13, &umr_bitfield_default },
	 { "FMT_RGB_RANDOM_ENABLE", 14, 14, &umr_bitfield_default },
	 { "FMT_HIGHPASS_RANDOM_ENABLE", 15, 15, &umr_bitfield_default },
	 { "FMT_TEMPORAL_DITHER_EN", 16, 16, &umr_bitfield_default },
	 { "FMT_TEMPORAL_DITHER_DEPTH", 17, 18, &umr_bitfield_default },
	 { "FMT_TEMPORAL_DITHER_OFFSET", 21, 22, &umr_bitfield_default },
	 { "FMT_TEMPORAL_LEVEL", 24, 24, &umr_bitfield_default },
	 { "FMT_TEMPORAL_DITHER_RESET", 25, 25, &umr_bitfield_default },
	 { "FMT_25FRC_SEL", 26, 27, &umr_bitfield_default },
	 { "FMT_50FRC_SEL", 28, 29, &umr_bitfield_default },
	 { "FMT_75FRC_SEL", 30, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmFMT3_FMT_DITHER_RAND_R_SEED[] = {
	 { "FMT_RAND_R_SEED", 0, 7, &umr_bitfield_default },
	 { "FMT_OFFSET_R_CR", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmFMT3_FMT_DITHER_RAND_G_SEED[] = {
	 { "FMT_RAND_G_SEED", 0, 7, &umr_bitfield_default },
	 { "FMT_OFFSET_G_Y", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmFMT3_FMT_DITHER_RAND_B_SEED[] = {
	 { "FMT_RAND_B_SEED", 0, 7, &umr_bitfield_default },
	 { "FMT_OFFSET_B_CB", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmFMT3_FMT_CLAMP_CNTL[] = {
	 { "FMT_CLAMP_DATA_EN", 0, 0, &umr_bitfield_default },
	 { "FMT_CLAMP_COLOR_FORMAT", 16, 18, &umr_bitfield_default },
};
static struct umr_bitfield mmFMT3_FMT_SIDE_BY_SIDE_STEREO_CONTROL[] = {
	 { "FMT_SIDE_BY_SIDE_STEREO_ACTIVE_WIDTH", 0, 12, &umr_bitfield_default },
};
static struct umr_bitfield mmFMT3_FMT_MAP420_MEMORY_CONTROL[] = {
	 { "FMT_MAP420MEM_PWR_FORCE", 0, 1, &umr_bitfield_default },
	 { "FMT_MAP420MEM_PWR_DIS", 4, 4, &umr_bitfield_default },
	 { "FMT_MAP420MEM_PWR_STATE", 8, 9, &umr_bitfield_default },
};
static struct umr_bitfield mmOPPBUF3_OPPBUF_CONTROL[] = {
	 { "OPPBUF_ACTIVE_WIDTH", 0, 13, &umr_bitfield_default },
	 { "OPPBUF_DISPLAY_SEGMENTATION", 16, 18, &umr_bitfield_default },
	 { "OPPBUF_OVERLAP_PIXEL_NUM", 20, 23, &umr_bitfield_default },
	 { "OPPBUF_PIXEL_REPETITION", 24, 27, &umr_bitfield_default },
	 { "OPPBUF_DOUBLE_BUFFER_PENDING", 28, 28, &umr_bitfield_default },
};
static struct umr_bitfield mmOPPBUF3_OPPBUF_3D_PARAMETERS_0[] = {
	 { "OPPBUF_3D_VACT_SPACE1_SIZE", 0, 9, &umr_bitfield_default },
	 { "OPPBUF_3D_VACT_SPACE2_SIZE", 10, 19, &umr_bitfield_default },
	 { "OPPBUF_DUMMY_DATA_R", 20, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmOPPBUF3_OPPBUF_3D_PARAMETERS_1[] = {
	 { "OPPBUF_DUMMY_DATA_G", 0, 11, &umr_bitfield_default },
	 { "OPPBUF_DUMMY_DATA_B", 16, 27, &umr_bitfield_default },
};
static struct umr_bitfield mmOPP_PIPE3_OPP_PIPE_CONTROL[] = {
	 { "OPP_PIPE_CLOCK_EN", 0, 0, &umr_bitfield_default },
	 { "OPP_PIPE_CLOCK_ON", 1, 1, &umr_bitfield_default },
	 { "OPP_PIPE_DIGITAL_BYPASS_EN", 4, 4, &umr_bitfield_default },
};
static struct umr_bitfield mmOPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL[] = {
	 { "OPP_PIPE_CRC_EN", 0, 0, &umr_bitfield_default },
	 { "OPP_PIPE_CRC_CONT_EN", 4, 4, &umr_bitfield_default },
	 { "OPP_PIPE_CRC_STEREO_MODE", 8, 9, &umr_bitfield_default },
	 { "OPP_PIPE_CRC_STEREO_EN", 10, 10, &umr_bitfield_default },
	 { "OPP_PIPE_CRC_INTERLACE_MODE", 12, 13, &umr_bitfield_default },
	 { "OPP_PIPE_CRC_INTERLACE_EN", 14, 14, &umr_bitfield_default },
	 { "OPP_PIPE_CRC_PIXEL_SELECT", 20, 21, &umr_bitfield_default },
	 { "OPP_PIPE_CRC_SOURCE_SELECT", 24, 24, &umr_bitfield_default },
	 { "OPP_PIPE_CRC_ONE_SHOT_PENDING", 28, 28, &umr_bitfield_default },
};
static struct umr_bitfield mmOPP_PIPE_CRC3_OPP_PIPE_CRC_MASK[] = {
	 { "OPP_PIPE_CRC_MASK", 0, 15, &umr_bitfield_default },
};
static struct umr_bitfield mmOPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT0[] = {
	 { "OPP_PIPE_CRC_RESULT_A", 0, 15, &umr_bitfield_default },
	 { "OPP_PIPE_CRC_RESULT_R", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmOPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT1[] = {
	 { "OPP_PIPE_CRC_RESULT_G", 0, 15, &umr_bitfield_default },
	 { "OPP_PIPE_CRC_RESULT_B", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmOPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT2[] = {
	 { "OPP_PIPE_CRC_RESULT_C", 0, 15, &umr_bitfield_default },
};
static struct umr_bitfield mmFMT4_FMT_CLAMP_COMPONENT_R[] = {
	 { "FMT_CLAMP_LOWER_R", 0, 15, &umr_bitfield_default },
	 { "FMT_CLAMP_UPPER_R", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmFMT4_FMT_CLAMP_COMPONENT_G[] = {
	 { "FMT_CLAMP_LOWER_G", 0, 15, &umr_bitfield_default },
	 { "FMT_CLAMP_UPPER_G", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmFMT4_FMT_CLAMP_COMPONENT_B[] = {
	 { "FMT_CLAMP_LOWER_B", 0, 15, &umr_bitfield_default },
	 { "FMT_CLAMP_UPPER_B", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmFMT4_FMT_DYNAMIC_EXP_CNTL[] = {
	 { "FMT_DYNAMIC_EXP_EN", 0, 0, &umr_bitfield_default },
	 { "FMT_DYNAMIC_EXP_MODE", 4, 4, &umr_bitfield_default },
};
static struct umr_bitfield mmFMT4_FMT_CONTROL[] = {
	 { "FMT_STEREOSYNC_OVERRIDE", 0, 0, &umr_bitfield_default },
	 { "FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX", 8, 11, &umr_bitfield_default },
	 { "FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP", 12, 13, &umr_bitfield_default },
	 { "FMT_PIXEL_ENCODING", 16, 17, &umr_bitfield_default },
	 { "FMT_SUBSAMPLING_MODE", 18, 19, &umr_bitfield_default },
	 { "FMT_SUBSAMPLING_ORDER", 20, 20, &umr_bitfield_default },
	 { "FMT_CBCR_BIT_REDUCTION_BYPASS", 21, 21, &umr_bitfield_default },
	 { "FMT_DOUBLE_BUFFER_REG_UPDATE_PENDING", 24, 24, &umr_bitfield_default },
};
static struct umr_bitfield mmFMT4_FMT_BIT_DEPTH_CONTROL[] = {
	 { "FMT_TRUNCATE_EN", 0, 0, &umr_bitfield_default },
	 { "FMT_TRUNCATE_MODE", 1, 1, &umr_bitfield_default },
	 { "FMT_TRUNCATE_DEPTH", 4, 5, &umr_bitfield_default },
	 { "FMT_SPATIAL_DITHER_EN", 8, 8, &umr_bitfield_default },
	 { "FMT_SPATIAL_DITHER_MODE", 9, 10, &umr_bitfield_default },
	 { "FMT_SPATIAL_DITHER_DEPTH", 11, 12, &umr_bitfield_default },
	 { "FMT_FRAME_RANDOM_ENABLE", 13, 13, &umr_bitfield_default },
	 { "FMT_RGB_RANDOM_ENABLE", 14, 14, &umr_bitfield_default },
	 { "FMT_HIGHPASS_RANDOM_ENABLE", 15, 15, &umr_bitfield_default },
	 { "FMT_TEMPORAL_DITHER_EN", 16, 16, &umr_bitfield_default },
	 { "FMT_TEMPORAL_DITHER_DEPTH", 17, 18, &umr_bitfield_default },
	 { "FMT_TEMPORAL_DITHER_OFFSET", 21, 22, &umr_bitfield_default },
	 { "FMT_TEMPORAL_LEVEL", 24, 24, &umr_bitfield_default },
	 { "FMT_TEMPORAL_DITHER_RESET", 25, 25, &umr_bitfield_default },
	 { "FMT_25FRC_SEL", 26, 27, &umr_bitfield_default },
	 { "FMT_50FRC_SEL", 28, 29, &umr_bitfield_default },
	 { "FMT_75FRC_SEL", 30, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmFMT4_FMT_DITHER_RAND_R_SEED[] = {
	 { "FMT_RAND_R_SEED", 0, 7, &umr_bitfield_default },
	 { "FMT_OFFSET_R_CR", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmFMT4_FMT_DITHER_RAND_G_SEED[] = {
	 { "FMT_RAND_G_SEED", 0, 7, &umr_bitfield_default },
	 { "FMT_OFFSET_G_Y", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmFMT4_FMT_DITHER_RAND_B_SEED[] = {
	 { "FMT_RAND_B_SEED", 0, 7, &umr_bitfield_default },
	 { "FMT_OFFSET_B_CB", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmFMT4_FMT_CLAMP_CNTL[] = {
	 { "FMT_CLAMP_DATA_EN", 0, 0, &umr_bitfield_default },
	 { "FMT_CLAMP_COLOR_FORMAT", 16, 18, &umr_bitfield_default },
};
static struct umr_bitfield mmFMT4_FMT_SIDE_BY_SIDE_STEREO_CONTROL[] = {
	 { "FMT_SIDE_BY_SIDE_STEREO_ACTIVE_WIDTH", 0, 12, &umr_bitfield_default },
};
static struct umr_bitfield mmFMT4_FMT_MAP420_MEMORY_CONTROL[] = {
	 { "FMT_MAP420MEM_PWR_FORCE", 0, 1, &umr_bitfield_default },
	 { "FMT_MAP420MEM_PWR_DIS", 4, 4, &umr_bitfield_default },
	 { "FMT_MAP420MEM_PWR_STATE", 8, 9, &umr_bitfield_default },
};
static struct umr_bitfield mmOPPBUF4_OPPBUF_CONTROL[] = {
	 { "OPPBUF_ACTIVE_WIDTH", 0, 13, &umr_bitfield_default },
	 { "OPPBUF_DISPLAY_SEGMENTATION", 16, 18, &umr_bitfield_default },
	 { "OPPBUF_OVERLAP_PIXEL_NUM", 20, 23, &umr_bitfield_default },
	 { "OPPBUF_PIXEL_REPETITION", 24, 27, &umr_bitfield_default },
	 { "OPPBUF_DOUBLE_BUFFER_PENDING", 28, 28, &umr_bitfield_default },
};
static struct umr_bitfield mmOPPBUF4_OPPBUF_3D_PARAMETERS_0[] = {
	 { "OPPBUF_3D_VACT_SPACE1_SIZE", 0, 9, &umr_bitfield_default },
	 { "OPPBUF_3D_VACT_SPACE2_SIZE", 10, 19, &umr_bitfield_default },
	 { "OPPBUF_DUMMY_DATA_R", 20, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmOPPBUF4_OPPBUF_3D_PARAMETERS_1[] = {
	 { "OPPBUF_DUMMY_DATA_G", 0, 11, &umr_bitfield_default },
	 { "OPPBUF_DUMMY_DATA_B", 16, 27, &umr_bitfield_default },
};
static struct umr_bitfield mmOPP_PIPE4_OPP_PIPE_CONTROL[] = {
	 { "OPP_PIPE_CLOCK_EN", 0, 0, &umr_bitfield_default },
	 { "OPP_PIPE_CLOCK_ON", 1, 1, &umr_bitfield_default },
	 { "OPP_PIPE_DIGITAL_BYPASS_EN", 4, 4, &umr_bitfield_default },
};
static struct umr_bitfield mmOPP_PIPE_CRC4_OPP_PIPE_CRC_CONTROL[] = {
	 { "OPP_PIPE_CRC_EN", 0, 0, &umr_bitfield_default },
	 { "OPP_PIPE_CRC_CONT_EN", 4, 4, &umr_bitfield_default },
	 { "OPP_PIPE_CRC_STEREO_MODE", 8, 9, &umr_bitfield_default },
	 { "OPP_PIPE_CRC_STEREO_EN", 10, 10, &umr_bitfield_default },
	 { "OPP_PIPE_CRC_INTERLACE_MODE", 12, 13, &umr_bitfield_default },
	 { "OPP_PIPE_CRC_INTERLACE_EN", 14, 14, &umr_bitfield_default },
	 { "OPP_PIPE_CRC_PIXEL_SELECT", 20, 21, &umr_bitfield_default },
	 { "OPP_PIPE_CRC_SOURCE_SELECT", 24, 24, &umr_bitfield_default },
	 { "OPP_PIPE_CRC_ONE_SHOT_PENDING", 28, 28, &umr_bitfield_default },
};
static struct umr_bitfield mmOPP_PIPE_CRC4_OPP_PIPE_CRC_MASK[] = {
	 { "OPP_PIPE_CRC_MASK", 0, 15, &umr_bitfield_default },
};
static struct umr_bitfield mmOPP_PIPE_CRC4_OPP_PIPE_CRC_RESULT0[] = {
	 { "OPP_PIPE_CRC_RESULT_A", 0, 15, &umr_bitfield_default },
	 { "OPP_PIPE_CRC_RESULT_R", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmOPP_PIPE_CRC4_OPP_PIPE_CRC_RESULT1[] = {
	 { "OPP_PIPE_CRC_RESULT_G", 0, 15, &umr_bitfield_default },
	 { "OPP_PIPE_CRC_RESULT_B", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmOPP_PIPE_CRC4_OPP_PIPE_CRC_RESULT2[] = {
	 { "OPP_PIPE_CRC_RESULT_C", 0, 15, &umr_bitfield_default },
};
static struct umr_bitfield mmFMT5_FMT_CLAMP_COMPONENT_R[] = {
	 { "FMT_CLAMP_LOWER_R", 0, 15, &umr_bitfield_default },
	 { "FMT_CLAMP_UPPER_R", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmFMT5_FMT_CLAMP_COMPONENT_G[] = {
	 { "FMT_CLAMP_LOWER_G", 0, 15, &umr_bitfield_default },
	 { "FMT_CLAMP_UPPER_G", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmFMT5_FMT_CLAMP_COMPONENT_B[] = {
	 { "FMT_CLAMP_LOWER_B", 0, 15, &umr_bitfield_default },
	 { "FMT_CLAMP_UPPER_B", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmFMT5_FMT_DYNAMIC_EXP_CNTL[] = {
	 { "FMT_DYNAMIC_EXP_EN", 0, 0, &umr_bitfield_default },
	 { "FMT_DYNAMIC_EXP_MODE", 4, 4, &umr_bitfield_default },
};
static struct umr_bitfield mmFMT5_FMT_CONTROL[] = {
	 { "FMT_STEREOSYNC_OVERRIDE", 0, 0, &umr_bitfield_default },
	 { "FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX", 8, 11, &umr_bitfield_default },
	 { "FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP", 12, 13, &umr_bitfield_default },
	 { "FMT_PIXEL_ENCODING", 16, 17, &umr_bitfield_default },
	 { "FMT_SUBSAMPLING_MODE", 18, 19, &umr_bitfield_default },
	 { "FMT_SUBSAMPLING_ORDER", 20, 20, &umr_bitfield_default },
	 { "FMT_CBCR_BIT_REDUCTION_BYPASS", 21, 21, &umr_bitfield_default },
	 { "FMT_DOUBLE_BUFFER_REG_UPDATE_PENDING", 24, 24, &umr_bitfield_default },
};
static struct umr_bitfield mmFMT5_FMT_BIT_DEPTH_CONTROL[] = {
	 { "FMT_TRUNCATE_EN", 0, 0, &umr_bitfield_default },
	 { "FMT_TRUNCATE_MODE", 1, 1, &umr_bitfield_default },
	 { "FMT_TRUNCATE_DEPTH", 4, 5, &umr_bitfield_default },
	 { "FMT_SPATIAL_DITHER_EN", 8, 8, &umr_bitfield_default },
	 { "FMT_SPATIAL_DITHER_MODE", 9, 10, &umr_bitfield_default },
	 { "FMT_SPATIAL_DITHER_DEPTH", 11, 12, &umr_bitfield_default },
	 { "FMT_FRAME_RANDOM_ENABLE", 13, 13, &umr_bitfield_default },
	 { "FMT_RGB_RANDOM_ENABLE", 14, 14, &umr_bitfield_default },
	 { "FMT_HIGHPASS_RANDOM_ENABLE", 15, 15, &umr_bitfield_default },
	 { "FMT_TEMPORAL_DITHER_EN", 16, 16, &umr_bitfield_default },
	 { "FMT_TEMPORAL_DITHER_DEPTH", 17, 18, &umr_bitfield_default },
	 { "FMT_TEMPORAL_DITHER_OFFSET", 21, 22, &umr_bitfield_default },
	 { "FMT_TEMPORAL_LEVEL", 24, 24, &umr_bitfield_default },
	 { "FMT_TEMPORAL_DITHER_RESET", 25, 25, &umr_bitfield_default },
	 { "FMT_25FRC_SEL", 26, 27, &umr_bitfield_default },
	 { "FMT_50FRC_SEL", 28, 29, &umr_bitfield_default },
	 { "FMT_75FRC_SEL", 30, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmFMT5_FMT_DITHER_RAND_R_SEED[] = {
	 { "FMT_RAND_R_SEED", 0, 7, &umr_bitfield_default },
	 { "FMT_OFFSET_R_CR", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmFMT5_FMT_DITHER_RAND_G_SEED[] = {
	 { "FMT_RAND_G_SEED", 0, 7, &umr_bitfield_default },
	 { "FMT_OFFSET_G_Y", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmFMT5_FMT_DITHER_RAND_B_SEED[] = {
	 { "FMT_RAND_B_SEED", 0, 7, &umr_bitfield_default },
	 { "FMT_OFFSET_B_CB", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmFMT5_FMT_CLAMP_CNTL[] = {
	 { "FMT_CLAMP_DATA_EN", 0, 0, &umr_bitfield_default },
	 { "FMT_CLAMP_COLOR_FORMAT", 16, 18, &umr_bitfield_default },
};
static struct umr_bitfield mmFMT5_FMT_SIDE_BY_SIDE_STEREO_CONTROL[] = {
	 { "FMT_SIDE_BY_SIDE_STEREO_ACTIVE_WIDTH", 0, 12, &umr_bitfield_default },
};
static struct umr_bitfield mmFMT5_FMT_MAP420_MEMORY_CONTROL[] = {
	 { "FMT_MAP420MEM_PWR_FORCE", 0, 1, &umr_bitfield_default },
	 { "FMT_MAP420MEM_PWR_DIS", 4, 4, &umr_bitfield_default },
	 { "FMT_MAP420MEM_PWR_STATE", 8, 9, &umr_bitfield_default },
};
static struct umr_bitfield mmOPPBUF5_OPPBUF_CONTROL[] = {
	 { "OPPBUF_ACTIVE_WIDTH", 0, 13, &umr_bitfield_default },
	 { "OPPBUF_DISPLAY_SEGMENTATION", 16, 18, &umr_bitfield_default },
	 { "OPPBUF_OVERLAP_PIXEL_NUM", 20, 23, &umr_bitfield_default },
	 { "OPPBUF_PIXEL_REPETITION", 24, 27, &umr_bitfield_default },
	 { "OPPBUF_DOUBLE_BUFFER_PENDING", 28, 28, &umr_bitfield_default },
};
static struct umr_bitfield mmOPPBUF5_OPPBUF_3D_PARAMETERS_0[] = {
	 { "OPPBUF_3D_VACT_SPACE1_SIZE", 0, 9, &umr_bitfield_default },
	 { "OPPBUF_3D_VACT_SPACE2_SIZE", 10, 19, &umr_bitfield_default },
	 { "OPPBUF_DUMMY_DATA_R", 20, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmOPPBUF5_OPPBUF_3D_PARAMETERS_1[] = {
	 { "OPPBUF_DUMMY_DATA_G", 0, 11, &umr_bitfield_default },
	 { "OPPBUF_DUMMY_DATA_B", 16, 27, &umr_bitfield_default },
};
static struct umr_bitfield mmOPP_PIPE5_OPP_PIPE_CONTROL[] = {
	 { "OPP_PIPE_CLOCK_EN", 0, 0, &umr_bitfield_default },
	 { "OPP_PIPE_CLOCK_ON", 1, 1, &umr_bitfield_default },
	 { "OPP_PIPE_DIGITAL_BYPASS_EN", 4, 4, &umr_bitfield_default },
};
static struct umr_bitfield mmOPP_PIPE_CRC5_OPP_PIPE_CRC_CONTROL[] = {
	 { "OPP_PIPE_CRC_EN", 0, 0, &umr_bitfield_default },
	 { "OPP_PIPE_CRC_CONT_EN", 4, 4, &umr_bitfield_default },
	 { "OPP_PIPE_CRC_STEREO_MODE", 8, 9, &umr_bitfield_default },
	 { "OPP_PIPE_CRC_STEREO_EN", 10, 10, &umr_bitfield_default },
	 { "OPP_PIPE_CRC_INTERLACE_MODE", 12, 13, &umr_bitfield_default },
	 { "OPP_PIPE_CRC_INTERLACE_EN", 14, 14, &umr_bitfield_default },
	 { "OPP_PIPE_CRC_PIXEL_SELECT", 20, 21, &umr_bitfield_default },
	 { "OPP_PIPE_CRC_SOURCE_SELECT", 24, 24, &umr_bitfield_default },
	 { "OPP_PIPE_CRC_ONE_SHOT_PENDING", 28, 28, &umr_bitfield_default },
};
static struct umr_bitfield mmOPP_PIPE_CRC5_OPP_PIPE_CRC_MASK[] = {
	 { "OPP_PIPE_CRC_MASK", 0, 15, &umr_bitfield_default },
};
static struct umr_bitfield mmOPP_PIPE_CRC5_OPP_PIPE_CRC_RESULT0[] = {
	 { "OPP_PIPE_CRC_RESULT_A", 0, 15, &umr_bitfield_default },
	 { "OPP_PIPE_CRC_RESULT_R", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmOPP_PIPE_CRC5_OPP_PIPE_CRC_RESULT1[] = {
	 { "OPP_PIPE_CRC_RESULT_G", 0, 15, &umr_bitfield_default },
	 { "OPP_PIPE_CRC_RESULT_B", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmOPP_PIPE_CRC5_OPP_PIPE_CRC_RESULT2[] = {
	 { "OPP_PIPE_CRC_RESULT_C", 0, 15, &umr_bitfield_default },
};
static struct umr_bitfield mmOPP_TOP_CLK_CONTROL[] = {
	 { "OPP_DISPCLK_R_GATE_DIS", 0, 0, &umr_bitfield_default },
	 { "OPP_DISPCLK_G_ABM_GATE_DIS", 4, 4, &umr_bitfield_default },
	 { "OPP_TEST_CLK_SEL", 8, 11, &umr_bitfield_default },
	 { "OPP_ABM0_CLOCK_ON", 12, 12, &umr_bitfield_default },
	 { "OPP_ABM1_CLOCK_ON", 13, 13, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_PERFMON17_PERFCOUNTER_CNTL[] = {
	 { "PERFCOUNTER_EVENT_SEL", 0, 8, &umr_bitfield_default },
	 { "PERFCOUNTER_CVALUE_SEL", 9, 11, &umr_bitfield_default },
	 { "PERFCOUNTER_INC_MODE", 12, 14, &umr_bitfield_default },
	 { "PERFCOUNTER_HW_CNTL_SEL", 15, 15, &umr_bitfield_default },
	 { "PERFCOUNTER_RUNEN_MODE", 16, 16, &umr_bitfield_default },
	 { "PERFCOUNTER_CNTOFF_START_DIS", 22, 22, &umr_bitfield_default },
	 { "PERFCOUNTER_RESTART_EN", 23, 23, &umr_bitfield_default },
	 { "PERFCOUNTER_INT_EN", 24, 24, &umr_bitfield_default },
	 { "PERFCOUNTER_OFF_MASK", 25, 25, &umr_bitfield_default },
	 { "PERFCOUNTER_ACTIVE", 26, 26, &umr_bitfield_default },
	 { "PERFCOUNTER_CNTL_SEL", 29, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_PERFMON17_PERFCOUNTER_CNTL2[] = {
	 { "PERFCOUNTER_COUNTED_VALUE_TYPE", 0, 1, &umr_bitfield_default },
	 { "PERFCOUNTER_HW_STOP1_SEL", 2, 2, &umr_bitfield_default },
	 { "PERFCOUNTER_HW_STOP2_SEL", 3, 3, &umr_bitfield_default },
	 { "PERFCOUNTER_CNTOFF_SEL", 8, 13, &umr_bitfield_default },
	 { "PERFCOUNTER_CNTL2_SEL", 29, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_PERFMON17_PERFCOUNTER_STATE[] = {
	 { "PERFCOUNTER_CNT0_STATE", 0, 1, &umr_bitfield_default },
	 { "PERFCOUNTER_STATE_SEL0", 2, 2, &umr_bitfield_default },
	 { "PERFCOUNTER_CNT1_STATE", 4, 5, &umr_bitfield_default },
	 { "PERFCOUNTER_STATE_SEL1", 6, 6, &umr_bitfield_default },
	 { "PERFCOUNTER_CNT2_STATE", 8, 9, &umr_bitfield_default },
	 { "PERFCOUNTER_STATE_SEL2", 10, 10, &umr_bitfield_default },
	 { "PERFCOUNTER_CNT3_STATE", 12, 13, &umr_bitfield_default },
	 { "PERFCOUNTER_STATE_SEL3", 14, 14, &umr_bitfield_default },
	 { "PERFCOUNTER_CNT4_STATE", 16, 17, &umr_bitfield_default },
	 { "PERFCOUNTER_STATE_SEL4", 18, 18, &umr_bitfield_default },
	 { "PERFCOUNTER_CNT5_STATE", 20, 21, &umr_bitfield_default },
	 { "PERFCOUNTER_STATE_SEL5", 22, 22, &umr_bitfield_default },
	 { "PERFCOUNTER_CNT6_STATE", 24, 25, &umr_bitfield_default },
	 { "PERFCOUNTER_STATE_SEL6", 26, 26, &umr_bitfield_default },
	 { "PERFCOUNTER_CNT7_STATE", 28, 29, &umr_bitfield_default },
	 { "PERFCOUNTER_STATE_SEL7", 30, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_PERFMON17_PERFMON_CNTL[] = {
	 { "PERFMON_STATE", 0, 1, &umr_bitfield_default },
	 { "PERFMON_RPT_COUNT", 8, 27, &umr_bitfield_default },
	 { "PERFMON_CNTOFF_AND_OR", 28, 28, &umr_bitfield_default },
	 { "PERFMON_CNTOFF_INT_EN", 29, 29, &umr_bitfield_default },
	 { "PERFMON_CNTOFF_INT_STATUS", 30, 30, &umr_bitfield_default },
	 { "PERFMON_CNTOFF_INT_ACK", 31, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_PERFMON17_PERFMON_CNTL2[] = {
	 { "PERFMON_CNTOFF_INT_TYPE", 0, 0, &umr_bitfield_default },
	 { "PERFMON_CLK_ENABLE", 1, 1, &umr_bitfield_default },
	 { "PERFMON_RUN_ENABLE_START_SEL", 2, 9, &umr_bitfield_default },
	 { "PERFMON_RUN_ENABLE_STOP_SEL", 10, 17, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_PERFMON17_PERFMON_CVALUE_INT_MISC[] = {
	 { "PERFCOUNTER_INT0_STATUS", 0, 0, &umr_bitfield_default },
	 { "PERFCOUNTER_INT1_STATUS", 1, 1, &umr_bitfield_default },
	 { "PERFCOUNTER_INT2_STATUS", 2, 2, &umr_bitfield_default },
	 { "PERFCOUNTER_INT3_STATUS", 3, 3, &umr_bitfield_default },
	 { "PERFCOUNTER_INT4_STATUS", 4, 4, &umr_bitfield_default },
	 { "PERFCOUNTER_INT5_STATUS", 5, 5, &umr_bitfield_default },
	 { "PERFCOUNTER_INT6_STATUS", 6, 6, &umr_bitfield_default },
	 { "PERFCOUNTER_INT7_STATUS", 7, 7, &umr_bitfield_default },
	 { "PERFCOUNTER_INT0_ACK", 8, 8, &umr_bitfield_default },
	 { "PERFCOUNTER_INT1_ACK", 9, 9, &umr_bitfield_default },
	 { "PERFCOUNTER_INT2_ACK", 10, 10, &umr_bitfield_default },
	 { "PERFCOUNTER_INT3_ACK", 11, 11, &umr_bitfield_default },
	 { "PERFCOUNTER_INT4_ACK", 12, 12, &umr_bitfield_default },
	 { "PERFCOUNTER_INT5_ACK", 13, 13, &umr_bitfield_default },
	 { "PERFCOUNTER_INT6_ACK", 14, 14, &umr_bitfield_default },
	 { "PERFCOUNTER_INT7_ACK", 15, 15, &umr_bitfield_default },
	 { "PERFMON_CVALUE_HI", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_PERFMON17_PERFMON_CVALUE_LOW[] = {
	 { "PERFMON_CVALUE_LOW", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_PERFMON17_PERFMON_HI[] = {
	 { "PERFMON_HI", 0, 15, &umr_bitfield_default },
	 { "PERFMON_READ_SEL", 29, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_PERFMON17_PERFMON_LOW[] = {
	 { "PERFMON_LOW", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmODM0_OPTC_INPUT_GLOBAL_CONTROL[] = {
	 { "OPTC_INPUT_SOFT_RESET", 0, 0, &umr_bitfield_default },
	 { "OPTC_UNDERFLOW_INT_EN", 8, 8, &umr_bitfield_default },
	 { "OPTC_UNDERFLOW_INT_TYPE", 9, 9, &umr_bitfield_default },
	 { "OPTC_UNDERFLOW_OCCURRED_STATUS", 10, 10, &umr_bitfield_default },
	 { "OPTC_UNDERFLOW_INT_STATUS", 11, 11, &umr_bitfield_default },
	 { "OPTC_UNDERFLOW_CLEAR", 12, 12, &umr_bitfield_default },
};
static struct umr_bitfield mmODM0_OPTC_DATA_SOURCE_SELECT[] = {
	 { "OPTC_SRC_SEL", 8, 10, &umr_bitfield_default },
};
static struct umr_bitfield mmODM0_OPTC_INPUT_CLOCK_CONTROL[] = {
	 { "OPTC_INPUT_CLK_GATE_DIS", 0, 0, &umr_bitfield_default },
	 { "OPTC_INPUT_CLK_EN", 1, 1, &umr_bitfield_default },
	 { "OPTC_INPUT_CLK_ON", 2, 2, &umr_bitfield_default },
};
static struct umr_bitfield mmODM0_OPTC_INPUT_SPARE_REGISTER[] = {
	 { "OPTC_INPUT_SPARE_REG", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmODM1_OPTC_INPUT_GLOBAL_CONTROL[] = {
	 { "OPTC_INPUT_SOFT_RESET", 0, 0, &umr_bitfield_default },
	 { "OPTC_UNDERFLOW_INT_EN", 8, 8, &umr_bitfield_default },
	 { "OPTC_UNDERFLOW_INT_TYPE", 9, 9, &umr_bitfield_default },
	 { "OPTC_UNDERFLOW_OCCURRED_STATUS", 10, 10, &umr_bitfield_default },
	 { "OPTC_UNDERFLOW_INT_STATUS", 11, 11, &umr_bitfield_default },
	 { "OPTC_UNDERFLOW_CLEAR", 12, 12, &umr_bitfield_default },
};
static struct umr_bitfield mmODM1_OPTC_DATA_SOURCE_SELECT[] = {
	 { "OPTC_SRC_SEL", 8, 10, &umr_bitfield_default },
};
static struct umr_bitfield mmODM1_OPTC_INPUT_CLOCK_CONTROL[] = {
	 { "OPTC_INPUT_CLK_GATE_DIS", 0, 0, &umr_bitfield_default },
	 { "OPTC_INPUT_CLK_EN", 1, 1, &umr_bitfield_default },
	 { "OPTC_INPUT_CLK_ON", 2, 2, &umr_bitfield_default },
};
static struct umr_bitfield mmODM1_OPTC_INPUT_SPARE_REGISTER[] = {
	 { "OPTC_INPUT_SPARE_REG", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmODM2_OPTC_INPUT_GLOBAL_CONTROL[] = {
	 { "OPTC_INPUT_SOFT_RESET", 0, 0, &umr_bitfield_default },
	 { "OPTC_UNDERFLOW_INT_EN", 8, 8, &umr_bitfield_default },
	 { "OPTC_UNDERFLOW_INT_TYPE", 9, 9, &umr_bitfield_default },
	 { "OPTC_UNDERFLOW_OCCURRED_STATUS", 10, 10, &umr_bitfield_default },
	 { "OPTC_UNDERFLOW_INT_STATUS", 11, 11, &umr_bitfield_default },
	 { "OPTC_UNDERFLOW_CLEAR", 12, 12, &umr_bitfield_default },
};
static struct umr_bitfield mmODM2_OPTC_DATA_SOURCE_SELECT[] = {
	 { "OPTC_SRC_SEL", 8, 10, &umr_bitfield_default },
};
static struct umr_bitfield mmODM2_OPTC_INPUT_CLOCK_CONTROL[] = {
	 { "OPTC_INPUT_CLK_GATE_DIS", 0, 0, &umr_bitfield_default },
	 { "OPTC_INPUT_CLK_EN", 1, 1, &umr_bitfield_default },
	 { "OPTC_INPUT_CLK_ON", 2, 2, &umr_bitfield_default },
};
static struct umr_bitfield mmODM2_OPTC_INPUT_SPARE_REGISTER[] = {
	 { "OPTC_INPUT_SPARE_REG", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmODM3_OPTC_INPUT_GLOBAL_CONTROL[] = {
	 { "OPTC_INPUT_SOFT_RESET", 0, 0, &umr_bitfield_default },
	 { "OPTC_UNDERFLOW_INT_EN", 8, 8, &umr_bitfield_default },
	 { "OPTC_UNDERFLOW_INT_TYPE", 9, 9, &umr_bitfield_default },
	 { "OPTC_UNDERFLOW_OCCURRED_STATUS", 10, 10, &umr_bitfield_default },
	 { "OPTC_UNDERFLOW_INT_STATUS", 11, 11, &umr_bitfield_default },
	 { "OPTC_UNDERFLOW_CLEAR", 12, 12, &umr_bitfield_default },
};
static struct umr_bitfield mmODM3_OPTC_DATA_SOURCE_SELECT[] = {
	 { "OPTC_SRC_SEL", 8, 10, &umr_bitfield_default },
};
static struct umr_bitfield mmODM3_OPTC_INPUT_CLOCK_CONTROL[] = {
	 { "OPTC_INPUT_CLK_GATE_DIS", 0, 0, &umr_bitfield_default },
	 { "OPTC_INPUT_CLK_EN", 1, 1, &umr_bitfield_default },
	 { "OPTC_INPUT_CLK_ON", 2, 2, &umr_bitfield_default },
};
static struct umr_bitfield mmODM3_OPTC_INPUT_SPARE_REGISTER[] = {
	 { "OPTC_INPUT_SPARE_REG", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmODM4_OPTC_INPUT_GLOBAL_CONTROL[] = {
	 { "OPTC_INPUT_SOFT_RESET", 0, 0, &umr_bitfield_default },
	 { "OPTC_UNDERFLOW_INT_EN", 8, 8, &umr_bitfield_default },
	 { "OPTC_UNDERFLOW_INT_TYPE", 9, 9, &umr_bitfield_default },
	 { "OPTC_UNDERFLOW_OCCURRED_STATUS", 10, 10, &umr_bitfield_default },
	 { "OPTC_UNDERFLOW_INT_STATUS", 11, 11, &umr_bitfield_default },
	 { "OPTC_UNDERFLOW_CLEAR", 12, 12, &umr_bitfield_default },
};
static struct umr_bitfield mmODM4_OPTC_DATA_SOURCE_SELECT[] = {
	 { "OPTC_SRC_SEL", 8, 10, &umr_bitfield_default },
};
static struct umr_bitfield mmODM4_OPTC_INPUT_CLOCK_CONTROL[] = {
	 { "OPTC_INPUT_CLK_GATE_DIS", 0, 0, &umr_bitfield_default },
	 { "OPTC_INPUT_CLK_EN", 1, 1, &umr_bitfield_default },
	 { "OPTC_INPUT_CLK_ON", 2, 2, &umr_bitfield_default },
};
static struct umr_bitfield mmODM4_OPTC_INPUT_SPARE_REGISTER[] = {
	 { "OPTC_INPUT_SPARE_REG", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmODM5_OPTC_INPUT_GLOBAL_CONTROL[] = {
	 { "OPTC_INPUT_SOFT_RESET", 0, 0, &umr_bitfield_default },
	 { "OPTC_UNDERFLOW_INT_EN", 8, 8, &umr_bitfield_default },
	 { "OPTC_UNDERFLOW_INT_TYPE", 9, 9, &umr_bitfield_default },
	 { "OPTC_UNDERFLOW_OCCURRED_STATUS", 10, 10, &umr_bitfield_default },
	 { "OPTC_UNDERFLOW_INT_STATUS", 11, 11, &umr_bitfield_default },
	 { "OPTC_UNDERFLOW_CLEAR", 12, 12, &umr_bitfield_default },
};
static struct umr_bitfield mmODM5_OPTC_DATA_SOURCE_SELECT[] = {
	 { "OPTC_SRC_SEL", 8, 10, &umr_bitfield_default },
};
static struct umr_bitfield mmODM5_OPTC_INPUT_CLOCK_CONTROL[] = {
	 { "OPTC_INPUT_CLK_GATE_DIS", 0, 0, &umr_bitfield_default },
	 { "OPTC_INPUT_CLK_EN", 1, 1, &umr_bitfield_default },
	 { "OPTC_INPUT_CLK_ON", 2, 2, &umr_bitfield_default },
};
static struct umr_bitfield mmODM5_OPTC_INPUT_SPARE_REGISTER[] = {
	 { "OPTC_INPUT_SPARE_REG", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG0_OTG_H_TOTAL[] = {
	 { "OTG_H_TOTAL", 0, 14, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG0_OTG_H_BLANK_START_END[] = {
	 { "OTG_H_BLANK_START", 0, 14, &umr_bitfield_default },
	 { "OTG_H_BLANK_END", 16, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG0_OTG_H_SYNC_A[] = {
	 { "OTG_H_SYNC_A_START", 0, 14, &umr_bitfield_default },
	 { "OTG_H_SYNC_A_END", 16, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG0_OTG_H_SYNC_A_CNTL[] = {
	 { "OTG_H_SYNC_A_POL", 0, 0, &umr_bitfield_default },
	 { "OTG_COMP_SYNC_A_EN", 16, 16, &umr_bitfield_default },
	 { "OTG_H_SYNC_A_CUTOFF", 17, 17, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG0_OTG_H_TIMING_CNTL[] = {
	 { "OTG_H_TIMING_DIV_BY2", 0, 0, &umr_bitfield_default },
	 { "OTG_H_TIMING_DIV_BY2_UPDATE_MODE", 8, 8, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG0_OTG_V_TOTAL[] = {
	 { "OTG_V_TOTAL", 0, 14, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG0_OTG_V_TOTAL_MIN[] = {
	 { "OTG_V_TOTAL_MIN", 0, 14, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG0_OTG_V_TOTAL_MAX[] = {
	 { "OTG_V_TOTAL_MAX", 0, 14, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG0_OTG_V_TOTAL_MID[] = {
	 { "OTG_V_TOTAL_MID", 0, 14, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG0_OTG_V_TOTAL_CONTROL[] = {
	 { "OTG_V_TOTAL_MIN_SEL", 0, 0, &umr_bitfield_default },
	 { "OTG_V_TOTAL_MAX_SEL", 1, 1, &umr_bitfield_default },
	 { "OTG_VTOTAL_MID_REPLACING_MAX_EN", 2, 2, &umr_bitfield_default },
	 { "OTG_VTOTAL_MID_REPLACING_MIN_EN", 3, 3, &umr_bitfield_default },
	 { "OTG_FORCE_LOCK_ON_EVENT", 4, 4, &umr_bitfield_default },
	 { "OTG_SET_V_TOTAL_MIN_MASK_EN", 7, 7, &umr_bitfield_default },
	 { "OTG_VTOTAL_MID_FRAME_NUM", 8, 15, &umr_bitfield_default },
	 { "OTG_SET_V_TOTAL_MIN_MASK", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG0_OTG_V_TOTAL_INT_STATUS[] = {
	 { "OTG_SET_V_TOTAL_MIN_EVENT_OCCURED", 0, 0, &umr_bitfield_default },
	 { "OTG_SET_V_TOTAL_MIN_EVENT_OCCURED_INT", 4, 4, &umr_bitfield_default },
	 { "OTG_SET_V_TOTAL_MIN_EVENT_OCCURED_ACK", 8, 8, &umr_bitfield_default },
	 { "OTG_SET_V_TOTAL_MIN_EVENT_OCCURED_MSK", 12, 12, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG0_OTG_VSYNC_NOM_INT_STATUS[] = {
	 { "OTG_VSYNC_NOM", 0, 0, &umr_bitfield_default },
	 { "OTG_VSYNC_NOM_INT_CLEAR", 4, 4, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG0_OTG_V_BLANK_START_END[] = {
	 { "OTG_V_BLANK_START", 0, 14, &umr_bitfield_default },
	 { "OTG_V_BLANK_END", 16, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG0_OTG_V_SYNC_A[] = {
	 { "OTG_V_SYNC_A_START", 0, 14, &umr_bitfield_default },
	 { "OTG_V_SYNC_A_END", 16, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG0_OTG_V_SYNC_A_CNTL[] = {
	 { "OTG_V_SYNC_A_POL", 0, 0, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG0_OTG_TRIGA_CNTL[] = {
	 { "OTG_TRIGA_SOURCE_SELECT", 0, 4, &umr_bitfield_default },
	 { "OTG_TRIGA_SOURCE_PIPE_SELECT", 5, 7, &umr_bitfield_default },
	 { "OTG_TRIGA_POLARITY_SELECT", 8, 10, &umr_bitfield_default },
	 { "OTG_TRIGA_RESYNC_BYPASS_EN", 11, 11, &umr_bitfield_default },
	 { "OTG_TRIGA_INPUT_STATUS", 12, 12, &umr_bitfield_default },
	 { "OTG_TRIGA_POLARITY_STATUS", 13, 13, &umr_bitfield_default },
	 { "OTG_TRIGA_OCCURRED", 14, 14, &umr_bitfield_default },
	 { "OTG_TRIGA_RISING_EDGE_DETECT_CNTL", 16, 17, &umr_bitfield_default },
	 { "OTG_TRIGA_FALLING_EDGE_DETECT_CNTL", 18, 19, &umr_bitfield_default },
	 { "OTG_TRIGA_FREQUENCY_SELECT", 20, 21, &umr_bitfield_default },
	 { "OTG_TRIGA_DELAY", 24, 28, &umr_bitfield_default },
	 { "OTG_TRIGA_CLEAR", 31, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG0_OTG_TRIGA_MANUAL_TRIG[] = {
	 { "OTG_TRIGA_MANUAL_TRIG", 0, 0, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG0_OTG_TRIGB_CNTL[] = {
	 { "OTG_TRIGB_SOURCE_SELECT", 0, 4, &umr_bitfield_default },
	 { "OTG_TRIGB_SOURCE_PIPE_SELECT", 5, 7, &umr_bitfield_default },
	 { "OTG_TRIGB_POLARITY_SELECT", 8, 10, &umr_bitfield_default },
	 { "OTG_TRIGB_RESYNC_BYPASS_EN", 11, 11, &umr_bitfield_default },
	 { "OTG_TRIGB_INPUT_STATUS", 12, 12, &umr_bitfield_default },
	 { "OTG_TRIGB_POLARITY_STATUS", 13, 13, &umr_bitfield_default },
	 { "OTG_TRIGB_OCCURRED", 14, 14, &umr_bitfield_default },
	 { "OTG_TRIGB_RISING_EDGE_DETECT_CNTL", 16, 17, &umr_bitfield_default },
	 { "OTG_TRIGB_FALLING_EDGE_DETECT_CNTL", 18, 19, &umr_bitfield_default },
	 { "OTG_TRIGB_FREQUENCY_SELECT", 20, 21, &umr_bitfield_default },
	 { "OTG_TRIGB_DELAY", 24, 28, &umr_bitfield_default },
	 { "OTG_TRIGB_CLEAR", 31, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG0_OTG_TRIGB_MANUAL_TRIG[] = {
	 { "OTG_TRIGB_MANUAL_TRIG", 0, 0, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG0_OTG_FORCE_COUNT_NOW_CNTL[] = {
	 { "OTG_FORCE_COUNT_NOW_MODE", 0, 1, &umr_bitfield_default },
	 { "OTG_FORCE_COUNT_NOW_CHECK", 4, 4, &umr_bitfield_default },
	 { "OTG_FORCE_COUNT_NOW_TRIG_SEL", 8, 8, &umr_bitfield_default },
	 { "OTG_FORCE_COUNT_NOW_OCCURRED", 16, 16, &umr_bitfield_default },
	 { "OTG_FORCE_COUNT_NOW_CLEAR", 24, 24, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG0_OTG_FLOW_CONTROL[] = {
	 { "OTG_FLOW_CONTROL_SOURCE_SELECT", 0, 4, &umr_bitfield_default },
	 { "OTG_FLOW_CONTROL_POLARITY", 8, 8, &umr_bitfield_default },
	 { "OTG_FLOW_CONTROL_GRANULARITY", 16, 16, &umr_bitfield_default },
	 { "OTG_FLOW_CONTROL_INPUT_STATUS", 24, 24, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG0_OTG_STEREO_FORCE_NEXT_EYE[] = {
	 { "OTG_STEREO_FORCE_NEXT_EYE", 0, 1, &umr_bitfield_default },
	 { "OTG_AVSYNC_FRAME_COUNTER", 8, 15, &umr_bitfield_default },
	 { "OTG_AVSYNC_LINE_COUNTER", 16, 28, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG0_OTG_AVSYNC_COUNTER[] = {
	 { "OTG_AVSYNC_COUNTER", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG0_OTG_CONTROL[] = {
	 { "OTG_MASTER_EN", 0, 0, &umr_bitfield_default },
	 { "OTG_DISABLE_POINT_CNTL", 8, 9, &umr_bitfield_default },
	 { "OTG_START_POINT_CNTL", 12, 12, &umr_bitfield_default },
	 { "OTG_FIELD_NUMBER_CNTL", 13, 13, &umr_bitfield_default },
	 { "OTG_FIELD_NUMBER_POLARITY", 14, 14, &umr_bitfield_default },
	 { "OTG_CURRENT_MASTER_EN_STATE", 16, 16, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG0_OTG_BLANK_CONTROL[] = {
	 { "OTG_CURRENT_BLANK_STATE", 0, 0, &umr_bitfield_default },
	 { "OTG_BLANK_DATA_EN", 8, 8, &umr_bitfield_default },
	 { "OTG_BLANK_DE_MODE", 16, 16, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG0_OTG_PIPE_ABORT_CONTROL[] = {
	 { "OTG_PIPE_ABORT", 0, 0, &umr_bitfield_default },
	 { "OTG_PIPE_ABORT_DONE", 8, 8, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG0_OTG_INTERLACE_CONTROL[] = {
	 { "OTG_INTERLACE_ENABLE", 0, 0, &umr_bitfield_default },
	 { "OTG_INTERLACE_FORCE_NEXT_FIELD", 16, 17, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG0_OTG_INTERLACE_STATUS[] = {
	 { "OTG_INTERLACE_CURRENT_FIELD", 0, 0, &umr_bitfield_default },
	 { "OTG_INTERLACE_NEXT_FIELD", 1, 1, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG0_OTG_FIELD_INDICATION_CONTROL[] = {
	 { "OTG_FIELD_INDICATION_OUTPUT_POLARITY", 0, 0, &umr_bitfield_default },
	 { "OTG_FIELD_ALIGNMENT", 1, 1, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG0_OTG_PIXEL_DATA_READBACK0[] = {
	 { "OTG_PIXEL_DATA_BLUE_CB", 0, 15, &umr_bitfield_default },
	 { "OTG_PIXEL_DATA_GREEN_Y", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG0_OTG_PIXEL_DATA_READBACK1[] = {
	 { "OTG_PIXEL_DATA_RED_CR", 0, 15, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG0_OTG_STATUS[] = {
	 { "OTG_V_BLANK", 0, 0, &umr_bitfield_default },
	 { "OTG_V_ACTIVE_DISP", 1, 1, &umr_bitfield_default },
	 { "OTG_V_SYNC_A", 2, 2, &umr_bitfield_default },
	 { "OTG_V_UPDATE", 3, 3, &umr_bitfield_default },
	 { "OTG_V_BLANK_3D_STRUCTURE", 5, 5, &umr_bitfield_default },
	 { "OTG_H_BLANK", 16, 16, &umr_bitfield_default },
	 { "OTG_H_ACTIVE_DISP", 17, 17, &umr_bitfield_default },
	 { "OTG_H_SYNC_A", 18, 18, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG0_OTG_STATUS_POSITION[] = {
	 { "OTG_VERT_COUNT", 0, 14, &umr_bitfield_default },
	 { "OTG_HORZ_COUNT", 16, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG0_OTG_NOM_VERT_POSITION[] = {
	 { "OTG_VERT_COUNT_NOM", 0, 14, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG0_OTG_STATUS_FRAME_COUNT[] = {
	 { "OTG_FRAME_COUNT", 0, 23, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG0_OTG_STATUS_VF_COUNT[] = {
	 { "OTG_VF_COUNT", 0, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG0_OTG_STATUS_HV_COUNT[] = {
	 { "OTG_HV_COUNT", 0, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG0_OTG_COUNT_CONTROL[] = {
	 { "OTG_HORZ_COUNT_BY2_EN", 0, 0, &umr_bitfield_default },
	 { "OTG_HORZ_REPETITION_COUNT", 1, 4, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG0_OTG_COUNT_RESET[] = {
	 { "OTG_RESET_FRAME_COUNT", 0, 0, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG0_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE[] = {
	 { "OTG_MANUAL_FORCE_VSYNC_NEXT_LINE", 0, 0, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG0_OTG_VERT_SYNC_CONTROL[] = {
	 { "OTG_FORCE_VSYNC_NEXT_LINE_OCCURRED", 0, 0, &umr_bitfield_default },
	 { "OTG_FORCE_VSYNC_NEXT_LINE_CLEAR", 8, 8, &umr_bitfield_default },
	 { "OTG_AUTO_FORCE_VSYNC_MODE", 16, 17, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG0_OTG_STEREO_STATUS[] = {
	 { "OTG_STEREO_CURRENT_EYE", 0, 0, &umr_bitfield_default },
	 { "OTG_STEREO_SYNC_OUTPUT", 8, 8, &umr_bitfield_default },
	 { "OTG_STEREO_SYNC_SELECT", 16, 16, &umr_bitfield_default },
	 { "OTG_STEREO_EYE_FLAG", 20, 20, &umr_bitfield_default },
	 { "OTG_STEREO_FORCE_NEXT_EYE_PENDING", 24, 25, &umr_bitfield_default },
	 { "OTG_CURRENT_3D_STRUCTURE_STATE", 30, 30, &umr_bitfield_default },
	 { "OTG_CURRENT_STEREOSYNC_EN_STATE", 31, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG0_OTG_STEREO_CONTROL[] = {
	 { "OTG_STEREO_SYNC_OUTPUT_LINE_NUM", 0, 14, &umr_bitfield_default },
	 { "OTG_STEREO_SYNC_OUTPUT_POLARITY", 15, 15, &umr_bitfield_default },
	 { "OTG_STEREO_EYE_FLAG_POLARITY", 17, 17, &umr_bitfield_default },
	 { "OTG_DISABLE_STEREOSYNC_OUTPUT_FOR_DP", 18, 18, &umr_bitfield_default },
	 { "OTG_DISABLE_FIELD_NUM", 19, 19, &umr_bitfield_default },
	 { "OTG_DISABLE_V_BLANK_FOR_DP_FIX", 20, 20, &umr_bitfield_default },
	 { "OTG_STEREO_EN", 24, 24, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG0_OTG_SNAPSHOT_STATUS[] = {
	 { "OTG_SNAPSHOT_OCCURRED", 0, 0, &umr_bitfield_default },
	 { "OTG_SNAPSHOT_CLEAR", 1, 1, &umr_bitfield_default },
	 { "OTG_SNAPSHOT_MANUAL_TRIGGER", 2, 2, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG0_OTG_SNAPSHOT_CONTROL[] = {
	 { "OTG_AUTO_SNAPSHOT_TRIG_SEL", 0, 1, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG0_OTG_SNAPSHOT_POSITION[] = {
	 { "OTG_SNAPSHOT_VERT_COUNT", 0, 14, &umr_bitfield_default },
	 { "OTG_SNAPSHOT_HORZ_COUNT", 16, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG0_OTG_SNAPSHOT_FRAME[] = {
	 { "OTG_SNAPSHOT_FRAME_COUNT", 0, 23, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG0_OTG_INTERRUPT_CONTROL[] = {
	 { "OTG_SNAPSHOT_INT_MSK", 0, 0, &umr_bitfield_default },
	 { "OTG_SNAPSHOT_INT_TYPE", 1, 1, &umr_bitfield_default },
	 { "OTG_FORCE_COUNT_NOW_INT_MSK", 8, 8, &umr_bitfield_default },
	 { "OTG_FORCE_COUNT_NOW_INT_TYPE", 9, 9, &umr_bitfield_default },
	 { "OTG_FORCE_VSYNC_NEXT_LINE_INT_MSK", 16, 16, &umr_bitfield_default },
	 { "OTG_FORCE_VSYNC_NEXT_LINE_INT_TYPE", 17, 17, &umr_bitfield_default },
	 { "OTG_TRIGA_INT_MSK", 24, 24, &umr_bitfield_default },
	 { "OTG_TRIGB_INT_MSK", 25, 25, &umr_bitfield_default },
	 { "OTG_TRIGA_INT_TYPE", 26, 26, &umr_bitfield_default },
	 { "OTG_TRIGB_INT_TYPE", 27, 27, &umr_bitfield_default },
	 { "OTG_VSYNC_NOM_INT_MSK", 28, 28, &umr_bitfield_default },
	 { "OTG_VSYNC_NOM_INT_TYPE", 29, 29, &umr_bitfield_default },
	 { "OTG_GSL_VSYNC_GAP_INT_MSK", 30, 30, &umr_bitfield_default },
	 { "OTG_GSL_VSYNC_GAP_INT_TYPE", 31, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG0_OTG_UPDATE_LOCK[] = {
	 { "OTG_UPDATE_LOCK", 0, 0, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG0_OTG_DOUBLE_BUFFER_CONTROL[] = {
	 { "OTG_UPDATE_PENDING", 0, 0, &umr_bitfield_default },
	 { "OTG_H_TIMING_DIV_BY2_DB_UPDATE_PENDING", 2, 2, &umr_bitfield_default },
	 { "OTG_BLANK_DATA_EN_UPDATE_PENDING", 3, 3, &umr_bitfield_default },
	 { "OTG_RANGE_TIMING_DBUF_UPDATE_PENDING", 4, 4, &umr_bitfield_default },
	 { "OTG_TIMING_DB_UPDATE_PENDING", 5, 5, &umr_bitfield_default },
	 { "OTG_3D_CTRL_DB_UPDATE_PENDING", 6, 6, &umr_bitfield_default },
	 { "OTG_3D_STRUCTURE_EN_DB_UPDATE_PENDING", 7, 7, &umr_bitfield_default },
	 { "OTG_UPDATE_INSTANTLY", 8, 8, &umr_bitfield_default },
	 { "OTG_BLANK_DATA_DOUBLE_BUFFER_EN", 16, 16, &umr_bitfield_default },
	 { "OTG_RANGE_TIMING_DBUF_UPDATE_MODE", 24, 25, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG0_OTG_TEST_PATTERN_CONTROL[] = {
	 { "OTG_TEST_PATTERN_EN", 0, 0, &umr_bitfield_default },
	 { "OTG_TEST_PATTERN_MODE", 8, 10, &umr_bitfield_default },
	 { "OTG_TEST_PATTERN_DYNAMIC_RANGE", 16, 16, &umr_bitfield_default },
	 { "OTG_TEST_PATTERN_COLOR_FORMAT", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG0_OTG_TEST_PATTERN_PARAMETERS[] = {
	 { "OTG_TEST_PATTERN_INC0", 0, 3, &umr_bitfield_default },
	 { "OTG_TEST_PATTERN_INC1", 4, 7, &umr_bitfield_default },
	 { "OTG_TEST_PATTERN_VRES", 8, 11, &umr_bitfield_default },
	 { "OTG_TEST_PATTERN_HRES", 12, 15, &umr_bitfield_default },
	 { "OTG_TEST_PATTERN_RAMP0_OFFSET", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG0_OTG_TEST_PATTERN_COLOR[] = {
	 { "OTG_TEST_PATTERN_DATA", 0, 15, &umr_bitfield_default },
	 { "OTG_TEST_PATTERN_MASK", 16, 21, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG0_OTG_MASTER_EN[] = {
	 { "OTG_MASTER_EN", 0, 0, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG0_OTG_BLANK_DATA_COLOR[] = {
	 { "OTG_BLANK_DATA_COLOR_BLUE_CB", 0, 9, &umr_bitfield_default },
	 { "OTG_BLANK_DATA_COLOR_GREEN_Y", 10, 19, &umr_bitfield_default },
	 { "OTG_BLANK_DATA_COLOR_RED_CR", 20, 29, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG0_OTG_BLANK_DATA_COLOR_EXT[] = {
	 { "OTG_BLANK_DATA_COLOR_BLUE_CB_EXT", 0, 5, &umr_bitfield_default },
	 { "OTG_BLANK_DATA_COLOR_GREEN_Y_EXT", 8, 13, &umr_bitfield_default },
	 { "OTG_BLANK_DATA_COLOR_RED_CR_EXT", 16, 21, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG0_OTG_BLACK_COLOR[] = {
	 { "OTG_BLACK_COLOR_B_CB", 0, 9, &umr_bitfield_default },
	 { "OTG_BLACK_COLOR_G_Y", 10, 19, &umr_bitfield_default },
	 { "OTG_BLACK_COLOR_R_CR", 20, 29, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG0_OTG_BLACK_COLOR_EXT[] = {
	 { "OTG_BLACK_COLOR_B_CB_EXT", 0, 5, &umr_bitfield_default },
	 { "OTG_BLACK_COLOR_G_Y_EXT", 8, 13, &umr_bitfield_default },
	 { "OTG_BLACK_COLOR_R_CR_EXT", 16, 21, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG0_OTG_VERTICAL_INTERRUPT0_POSITION[] = {
	 { "OTG_VERTICAL_INTERRUPT0_LINE_START", 0, 14, &umr_bitfield_default },
	 { "OTG_VERTICAL_INTERRUPT0_LINE_END", 16, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG0_OTG_VERTICAL_INTERRUPT0_CONTROL[] = {
	 { "OTG_VERTICAL_INTERRUPT0_OUTPUT_POLARITY", 4, 4, &umr_bitfield_default },
	 { "OTG_VERTICAL_INTERRUPT0_INT_ENABLE", 8, 8, &umr_bitfield_default },
	 { "OTG_VERTICAL_INTERRUPT0_STATUS", 12, 12, &umr_bitfield_default },
	 { "OTG_VERTICAL_INTERRUPT0_INT_STATUS", 16, 16, &umr_bitfield_default },
	 { "OTG_VERTICAL_INTERRUPT0_CLEAR", 20, 20, &umr_bitfield_default },
	 { "OTG_VERTICAL_INTERRUPT0_INT_TYPE", 24, 24, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG0_OTG_VERTICAL_INTERRUPT1_POSITION[] = {
	 { "OTG_VERTICAL_INTERRUPT1_LINE_START", 0, 14, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG0_OTG_VERTICAL_INTERRUPT1_CONTROL[] = {
	 { "OTG_VERTICAL_INTERRUPT1_INT_ENABLE", 8, 8, &umr_bitfield_default },
	 { "OTG_VERTICAL_INTERRUPT1_STATUS", 12, 12, &umr_bitfield_default },
	 { "OTG_VERTICAL_INTERRUPT1_INT_STATUS", 16, 16, &umr_bitfield_default },
	 { "OTG_VERTICAL_INTERRUPT1_CLEAR", 20, 20, &umr_bitfield_default },
	 { "OTG_VERTICAL_INTERRUPT1_INT_TYPE", 24, 24, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG0_OTG_VERTICAL_INTERRUPT2_POSITION[] = {
	 { "OTG_VERTICAL_INTERRUPT2_LINE_START", 0, 14, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG0_OTG_VERTICAL_INTERRUPT2_CONTROL[] = {
	 { "OTG_VERTICAL_INTERRUPT2_INT_ENABLE", 8, 8, &umr_bitfield_default },
	 { "OTG_VERTICAL_INTERRUPT2_STATUS", 12, 12, &umr_bitfield_default },
	 { "OTG_VERTICAL_INTERRUPT2_INT_STATUS", 16, 16, &umr_bitfield_default },
	 { "OTG_VERTICAL_INTERRUPT2_CLEAR", 20, 20, &umr_bitfield_default },
	 { "OTG_VERTICAL_INTERRUPT2_INT_TYPE", 24, 24, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG0_OTG_CRC_CNTL[] = {
	 { "OTG_CRC_EN", 0, 0, &umr_bitfield_default },
	 { "OTG_CRC_DUAL_LINK_EN", 1, 1, &umr_bitfield_default },
	 { "OTG_CRC_DUAL_LINK_MODE", 2, 2, &umr_bitfield_default },
	 { "OTG_CRC_BLANK_ONLY", 3, 3, &umr_bitfield_default },
	 { "OTG_CRC_CONT_EN", 4, 4, &umr_bitfield_default },
	 { "OTG_CRC_CAPTURE_START_SEL", 5, 6, &umr_bitfield_default },
	 { "OTG_CRC_STEREO_MODE", 8, 9, &umr_bitfield_default },
	 { "OTG_CRC_INTERLACE_MODE", 12, 13, &umr_bitfield_default },
	 { "OTG_CRC_MULTI_STREAM_MODE", 16, 18, &umr_bitfield_default },
	 { "OTG_CRC_USE_NEW_AND_REPEATED_PIXELS", 19, 19, &umr_bitfield_default },
	 { "OTG_CRC0_SELECT", 20, 22, &umr_bitfield_default },
	 { "OTG_CRC1_SELECT", 24, 26, &umr_bitfield_default },
	 { "OTG_ONE_SHOT_CRC0_PENDING", 28, 28, &umr_bitfield_default },
	 { "OTG_ONE_SHOT_CRC1_PENDING", 29, 29, &umr_bitfield_default },
	 { "OTG_ONE_SHOT_CRC2_PENDING", 30, 30, &umr_bitfield_default },
	 { "OTG_ONE_SHOT_CRC3_PENDING", 31, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG0_OTG_CRC0_WINDOWA_X_CONTROL[] = {
	 { "OTG_CRC0_WINDOWA_X_START", 0, 14, &umr_bitfield_default },
	 { "OTG_CRC0_WINDOWA_X_END", 16, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG0_OTG_CRC0_WINDOWA_Y_CONTROL[] = {
	 { "OTG_CRC0_WINDOWA_Y_START", 0, 14, &umr_bitfield_default },
	 { "OTG_CRC0_WINDOWA_Y_END", 16, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG0_OTG_CRC0_WINDOWB_X_CONTROL[] = {
	 { "OTG_CRC0_WINDOWB_X_START", 0, 14, &umr_bitfield_default },
	 { "OTG_CRC0_WINDOWB_X_END", 16, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG0_OTG_CRC0_WINDOWB_Y_CONTROL[] = {
	 { "OTG_CRC0_WINDOWB_Y_START", 0, 14, &umr_bitfield_default },
	 { "OTG_CRC0_WINDOWB_Y_END", 16, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG0_OTG_CRC0_DATA_RG[] = {
	 { "CRC0_R_CR", 0, 15, &umr_bitfield_default },
	 { "CRC0_G_Y", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG0_OTG_CRC0_DATA_B[] = {
	 { "CRC0_B_CB", 0, 15, &umr_bitfield_default },
	 { "CRC0_C", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG0_OTG_CRC1_WINDOWA_X_CONTROL[] = {
	 { "OTG_CRC1_WINDOWA_X_START", 0, 14, &umr_bitfield_default },
	 { "OTG_CRC1_WINDOWA_X_END", 16, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG0_OTG_CRC1_WINDOWA_Y_CONTROL[] = {
	 { "OTG_CRC1_WINDOWA_Y_START", 0, 14, &umr_bitfield_default },
	 { "OTG_CRC1_WINDOWA_Y_END", 16, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG0_OTG_CRC1_WINDOWB_X_CONTROL[] = {
	 { "OTG_CRC1_WINDOWB_X_START", 0, 14, &umr_bitfield_default },
	 { "OTG_CRC1_WINDOWB_X_END", 16, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG0_OTG_CRC1_WINDOWB_Y_CONTROL[] = {
	 { "OTG_CRC1_WINDOWB_Y_START", 0, 14, &umr_bitfield_default },
	 { "OTG_CRC1_WINDOWB_Y_END", 16, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG0_OTG_CRC1_DATA_RG[] = {
	 { "CRC1_R_CR", 0, 15, &umr_bitfield_default },
	 { "CRC1_G_Y", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG0_OTG_CRC1_DATA_B[] = {
	 { "CRC1_B_CB", 0, 15, &umr_bitfield_default },
	 { "CRC1_C", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG0_OTG_CRC2_DATA_RG[] = {
	 { "CRC2_R_CR", 0, 15, &umr_bitfield_default },
	 { "CRC2_G_Y", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG0_OTG_CRC2_DATA_B[] = {
	 { "CRC2_B_CB", 0, 15, &umr_bitfield_default },
	 { "CRC2_C", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG0_OTG_CRC3_DATA_RG[] = {
	 { "CRC3_R_CR", 0, 15, &umr_bitfield_default },
	 { "CRC3_G_Y", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG0_OTG_CRC3_DATA_B[] = {
	 { "CRC3_B_CB", 0, 15, &umr_bitfield_default },
	 { "CRC3_C", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG0_OTG_CRC_SIG_RED_GREEN_MASK[] = {
	 { "OTG_CRC_SIG_RED_MASK", 0, 15, &umr_bitfield_default },
	 { "OTG_CRC_SIG_GREEN_MASK", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG0_OTG_CRC_SIG_BLUE_CONTROL_MASK[] = {
	 { "OTG_CRC_SIG_BLUE_MASK", 0, 15, &umr_bitfield_default },
	 { "OTG_CRC_SIG_CONTROL_MASK", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG0_OTG_STATIC_SCREEN_CONTROL[] = {
	 { "OTG_STATIC_SCREEN_EVENT_MASK", 0, 15, &umr_bitfield_default },
	 { "OTG_STATIC_SCREEN_FRAME_COUNT", 16, 23, &umr_bitfield_default },
	 { "OTG_CPU_SS_INT_ENABLE", 24, 24, &umr_bitfield_default },
	 { "OTG_SS_STATUS", 25, 25, &umr_bitfield_default },
	 { "OTG_CPU_SS_INT_STATUS", 26, 26, &umr_bitfield_default },
	 { "OTG_CPU_SS_INT_CLEAR", 27, 27, &umr_bitfield_default },
	 { "OTG_CPU_SS_INT_TYPE", 28, 28, &umr_bitfield_default },
	 { "OTG_STATIC_SCREEN_OVERRIDE", 30, 30, &umr_bitfield_default },
	 { "OTG_STATIC_SCREEN_OVERRIDE_VALUE", 31, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG0_OTG_3D_STRUCTURE_CONTROL[] = {
	 { "OTG_3D_STRUCTURE_EN", 0, 0, &umr_bitfield_default },
	 { "OTG_3D_STRUCTURE_V_UPDATE_MODE", 8, 9, &umr_bitfield_default },
	 { "OTG_3D_STRUCTURE_STEREO_SEL_OVR", 12, 12, &umr_bitfield_default },
	 { "OTG_3D_STRUCTURE_F_COUNT_RESET", 16, 16, &umr_bitfield_default },
	 { "OTG_3D_STRUCTURE_F_COUNT_RESET_PENDING", 17, 17, &umr_bitfield_default },
	 { "OTG_3D_STRUCTURE_F_COUNT", 18, 19, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG0_OTG_GSL_VSYNC_GAP[] = {
	 { "OTG_GSL_VSYNC_GAP_LIMIT", 0, 7, &umr_bitfield_default },
	 { "OTG_GSL_VSYNC_GAP_DELAY", 8, 15, &umr_bitfield_default },
	 { "OTG_GSL_VSYNC_GAP_SOURCE_SEL", 16, 16, &umr_bitfield_default },
	 { "OTG_GSL_VSYNC_GAP_MODE", 17, 18, &umr_bitfield_default },
	 { "OTG_GSL_VSYNC_GAP_CLEAR", 19, 19, &umr_bitfield_default },
	 { "OTG_GSL_VSYNC_GAP_OCCURRED", 20, 20, &umr_bitfield_default },
	 { "OTG_GSL_VSYNC_GAP_MASTER_FASTER", 23, 23, &umr_bitfield_default },
	 { "OTG_GSL_VSYNC_GAP", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG0_OTG_MASTER_UPDATE_MODE[] = {
	 { "MASTER_UPDATE_INTERLACED_MODE", 0, 1, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG0_OTG_CLOCK_CONTROL[] = {
	 { "OTG_CLOCK_EN", 0, 0, &umr_bitfield_default },
	 { "OTG_CLOCK_GATE_DIS", 1, 1, &umr_bitfield_default },
	 { "OTG_SOFT_RESET", 4, 4, &umr_bitfield_default },
	 { "OTG_CLOCK_ON", 8, 8, &umr_bitfield_default },
	 { "OTG_BUSY", 16, 16, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG0_OTG_VSTARTUP_PARAM[] = {
	 { "VSTARTUP_START", 0, 9, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG0_OTG_VUPDATE_PARAM[] = {
	 { "VUPDATE_OFFSET", 0, 15, &umr_bitfield_default },
	 { "VUPDATE_WIDTH", 16, 25, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG0_OTG_VREADY_PARAM[] = {
	 { "VREADY_OFFSET", 0, 15, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG0_OTG_GLOBAL_SYNC_STATUS[] = {
	 { "VSTARTUP_INT_EN", 0, 0, &umr_bitfield_default },
	 { "VSTARTUP_INT_TYPE", 1, 1, &umr_bitfield_default },
	 { "VSTARTUP_EVENT_OCCURRED", 2, 2, &umr_bitfield_default },
	 { "VSTARTUP_INT_STATUS", 3, 3, &umr_bitfield_default },
	 { "VSTARTUP_EVENT_CLEAR", 4, 4, &umr_bitfield_default },
	 { "VUPDATE_INT_EN", 5, 5, &umr_bitfield_default },
	 { "VUPDATE_INT_TYPE", 6, 6, &umr_bitfield_default },
	 { "VUPDATE_INT_POSITION_SEL", 7, 7, &umr_bitfield_default },
	 { "VUPDATE_EVENT_OCCURRED", 8, 8, &umr_bitfield_default },
	 { "VUPDATE_INT_STATUS", 9, 9, &umr_bitfield_default },
	 { "VUPDATE_EVENT_CLEAR", 10, 10, &umr_bitfield_default },
	 { "VUPDATE_STATUS", 11, 11, &umr_bitfield_default },
	 { "VUPDATE_NO_LOCK_INT_EN", 12, 12, &umr_bitfield_default },
	 { "VUPDATE_NO_LOCK_INT_TYPE", 13, 13, &umr_bitfield_default },
	 { "VUPDATE_NO_LOCK_EVENT_OCCURRED", 14, 14, &umr_bitfield_default },
	 { "VUPDATE_NO_LOCK_INT_STATUS", 15, 15, &umr_bitfield_default },
	 { "VUPDATE_NO_LOCK_EVENT_CLEAR", 16, 16, &umr_bitfield_default },
	 { "VUPDATE_NO_LOCK_STATUS", 17, 17, &umr_bitfield_default },
	 { "VREADY_INT_EN", 18, 18, &umr_bitfield_default },
	 { "VREADY_INT_TYPE", 19, 19, &umr_bitfield_default },
	 { "VREADY_EVENT_OCCURRED", 20, 20, &umr_bitfield_default },
	 { "VREADY_INT_STATUS", 21, 21, &umr_bitfield_default },
	 { "VREADY_EVENT_CLEAR", 22, 22, &umr_bitfield_default },
	 { "STEREO_SELECT_STATUS", 24, 24, &umr_bitfield_default },
	 { "FIELD_NUMBER_STATUS", 25, 25, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG0_OTG_MASTER_UPDATE_LOCK[] = {
	 { "OTG_MASTER_UPDATE_LOCK", 0, 0, &umr_bitfield_default },
	 { "UPDATE_LOCK_STATUS", 8, 8, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG0_OTG_GSL_CONTROL[] = {
	 { "OTG_GSL0_EN", 0, 0, &umr_bitfield_default },
	 { "OTG_GSL1_EN", 1, 1, &umr_bitfield_default },
	 { "OTG_GSL2_EN", 2, 2, &umr_bitfield_default },
	 { "OTG_GSL_MASTER_EN", 3, 3, &umr_bitfield_default },
	 { "OTG_GSL_FORCE_DELAY", 16, 20, &umr_bitfield_default },
	 { "OTG_GSL_CHECK_ALL_FIELDS", 28, 28, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG0_OTG_GSL_WINDOW_X[] = {
	 { "OTG_GSL_WINDOW_START_X", 0, 14, &umr_bitfield_default },
	 { "OTG_GSL_WINDOW_END_X", 16, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG0_OTG_GSL_WINDOW_Y[] = {
	 { "OTG_GSL_WINDOW_START_Y", 0, 14, &umr_bitfield_default },
	 { "OTG_GSL_WINDOW_END_Y", 16, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG0_OTG_VUPDATE_KEEPOUT[] = {
	 { "MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_START_OFFSET", 0, 15, &umr_bitfield_default },
	 { "MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_END_OFFSET", 16, 25, &umr_bitfield_default },
	 { "OTG_MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_EN", 31, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG0_OTG_GLOBAL_CONTROL0[] = {
	 { "OTG_MASTER_UPDATE_LOCK_HTOTAL_KEEPOUT", 0, 7, &umr_bitfield_default },
	 { "OTG_MASTER_UPDATE_LOCK_HTOTAL_KEEPOUT_EN", 8, 8, &umr_bitfield_default },
	 { "OTG_MASTER_UPDATE_LOCK_SEL", 25, 27, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG0_OTG_GLOBAL_CONTROL1[] = {
	 { "MASTER_UPDATE_LOCK_DB_X", 0, 14, &umr_bitfield_default },
	 { "MASTER_UPDATE_LOCK_DB_Y", 16, 30, &umr_bitfield_default },
	 { "MASTER_UPDATE_LOCK_DB_EN", 31, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG0_OTG_GLOBAL_CONTROL2[] = {
	 { "DIG_UPDATE_LOCATION", 0, 9, &umr_bitfield_default },
	 { "GLOBAL_UPDATE_LOCK_EN", 10, 10, &umr_bitfield_default },
	 { "MANUAL_FLOW_CONTROL_SEL", 16, 18, &umr_bitfield_default },
	 { "DCCG_VUPDATE_MODE", 31, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG0_OTG_GLOBAL_CONTROL3[] = {
	 { "MASTER_UPDATE_LOCK_DB_FIELD", 0, 1, &umr_bitfield_default },
	 { "MASTER_UPDATE_LOCK_DB_STEREO_SEL", 4, 5, &umr_bitfield_default },
	 { "MASTER_UPDATE_LOCK_DB_FIELD_STEREO_FLAG_SEL", 8, 8, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG0_OTG_TRIG_MANUAL_CONTROL[] = {
	 { "TRIG_MANUAL_CONTROL", 0, 0, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG0_OTG_MANUAL_FLOW_CONTROL[] = {
	 { "MANUAL_FLOW_CONTROL", 0, 0, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG0_OTG_RANGE_TIMING_INT_STATUS[] = {
	 { "OTG_RANGE_TIMING_UPDATE_OCCURRED", 0, 0, &umr_bitfield_default },
	 { "OTG_RANGE_TIMING_UPDATE_OCCURRED_INT", 4, 4, &umr_bitfield_default },
	 { "OTG_RANGE_TIMING_UPDATE_OCCURRED_CLEAR", 8, 8, &umr_bitfield_default },
	 { "OTG_RANGE_TIMING_UPDATE_OCCURRED_INT_MSK", 12, 12, &umr_bitfield_default },
	 { "OTG_RANGE_TIMING_UPDATE_OCCURRED_INT_TYPE", 16, 16, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG0_OTG_DRR_CONTROL[] = {
	 { "OTG_DRR_AVERAGE_FRAME", 0, 2, &umr_bitfield_default },
	 { "OTG_V_TOTAL_LAST_USED_BY_DRR", 16, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG0_OTG_REQUEST_CONTROL[] = {
	 { "OTG_REQUEST_MODE_FOR_H_DUPLICATE", 0, 0, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG0_OTG_SPARE_REGISTER[] = {
	 { "OTG_SPARE_REG", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG1_OTG_H_TOTAL[] = {
	 { "OTG_H_TOTAL", 0, 14, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG1_OTG_H_BLANK_START_END[] = {
	 { "OTG_H_BLANK_START", 0, 14, &umr_bitfield_default },
	 { "OTG_H_BLANK_END", 16, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG1_OTG_H_SYNC_A[] = {
	 { "OTG_H_SYNC_A_START", 0, 14, &umr_bitfield_default },
	 { "OTG_H_SYNC_A_END", 16, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG1_OTG_H_SYNC_A_CNTL[] = {
	 { "OTG_H_SYNC_A_POL", 0, 0, &umr_bitfield_default },
	 { "OTG_COMP_SYNC_A_EN", 16, 16, &umr_bitfield_default },
	 { "OTG_H_SYNC_A_CUTOFF", 17, 17, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG1_OTG_H_TIMING_CNTL[] = {
	 { "OTG_H_TIMING_DIV_BY2", 0, 0, &umr_bitfield_default },
	 { "OTG_H_TIMING_DIV_BY2_UPDATE_MODE", 8, 8, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG1_OTG_V_TOTAL[] = {
	 { "OTG_V_TOTAL", 0, 14, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG1_OTG_V_TOTAL_MIN[] = {
	 { "OTG_V_TOTAL_MIN", 0, 14, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG1_OTG_V_TOTAL_MAX[] = {
	 { "OTG_V_TOTAL_MAX", 0, 14, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG1_OTG_V_TOTAL_MID[] = {
	 { "OTG_V_TOTAL_MID", 0, 14, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG1_OTG_V_TOTAL_CONTROL[] = {
	 { "OTG_V_TOTAL_MIN_SEL", 0, 0, &umr_bitfield_default },
	 { "OTG_V_TOTAL_MAX_SEL", 1, 1, &umr_bitfield_default },
	 { "OTG_VTOTAL_MID_REPLACING_MAX_EN", 2, 2, &umr_bitfield_default },
	 { "OTG_VTOTAL_MID_REPLACING_MIN_EN", 3, 3, &umr_bitfield_default },
	 { "OTG_FORCE_LOCK_ON_EVENT", 4, 4, &umr_bitfield_default },
	 { "OTG_SET_V_TOTAL_MIN_MASK_EN", 7, 7, &umr_bitfield_default },
	 { "OTG_VTOTAL_MID_FRAME_NUM", 8, 15, &umr_bitfield_default },
	 { "OTG_SET_V_TOTAL_MIN_MASK", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG1_OTG_V_TOTAL_INT_STATUS[] = {
	 { "OTG_SET_V_TOTAL_MIN_EVENT_OCCURED", 0, 0, &umr_bitfield_default },
	 { "OTG_SET_V_TOTAL_MIN_EVENT_OCCURED_INT", 4, 4, &umr_bitfield_default },
	 { "OTG_SET_V_TOTAL_MIN_EVENT_OCCURED_ACK", 8, 8, &umr_bitfield_default },
	 { "OTG_SET_V_TOTAL_MIN_EVENT_OCCURED_MSK", 12, 12, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG1_OTG_VSYNC_NOM_INT_STATUS[] = {
	 { "OTG_VSYNC_NOM", 0, 0, &umr_bitfield_default },
	 { "OTG_VSYNC_NOM_INT_CLEAR", 4, 4, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG1_OTG_V_BLANK_START_END[] = {
	 { "OTG_V_BLANK_START", 0, 14, &umr_bitfield_default },
	 { "OTG_V_BLANK_END", 16, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG1_OTG_V_SYNC_A[] = {
	 { "OTG_V_SYNC_A_START", 0, 14, &umr_bitfield_default },
	 { "OTG_V_SYNC_A_END", 16, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG1_OTG_V_SYNC_A_CNTL[] = {
	 { "OTG_V_SYNC_A_POL", 0, 0, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG1_OTG_TRIGA_CNTL[] = {
	 { "OTG_TRIGA_SOURCE_SELECT", 0, 4, &umr_bitfield_default },
	 { "OTG_TRIGA_SOURCE_PIPE_SELECT", 5, 7, &umr_bitfield_default },
	 { "OTG_TRIGA_POLARITY_SELECT", 8, 10, &umr_bitfield_default },
	 { "OTG_TRIGA_RESYNC_BYPASS_EN", 11, 11, &umr_bitfield_default },
	 { "OTG_TRIGA_INPUT_STATUS", 12, 12, &umr_bitfield_default },
	 { "OTG_TRIGA_POLARITY_STATUS", 13, 13, &umr_bitfield_default },
	 { "OTG_TRIGA_OCCURRED", 14, 14, &umr_bitfield_default },
	 { "OTG_TRIGA_RISING_EDGE_DETECT_CNTL", 16, 17, &umr_bitfield_default },
	 { "OTG_TRIGA_FALLING_EDGE_DETECT_CNTL", 18, 19, &umr_bitfield_default },
	 { "OTG_TRIGA_FREQUENCY_SELECT", 20, 21, &umr_bitfield_default },
	 { "OTG_TRIGA_DELAY", 24, 28, &umr_bitfield_default },
	 { "OTG_TRIGA_CLEAR", 31, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG1_OTG_TRIGA_MANUAL_TRIG[] = {
	 { "OTG_TRIGA_MANUAL_TRIG", 0, 0, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG1_OTG_TRIGB_CNTL[] = {
	 { "OTG_TRIGB_SOURCE_SELECT", 0, 4, &umr_bitfield_default },
	 { "OTG_TRIGB_SOURCE_PIPE_SELECT", 5, 7, &umr_bitfield_default },
	 { "OTG_TRIGB_POLARITY_SELECT", 8, 10, &umr_bitfield_default },
	 { "OTG_TRIGB_RESYNC_BYPASS_EN", 11, 11, &umr_bitfield_default },
	 { "OTG_TRIGB_INPUT_STATUS", 12, 12, &umr_bitfield_default },
	 { "OTG_TRIGB_POLARITY_STATUS", 13, 13, &umr_bitfield_default },
	 { "OTG_TRIGB_OCCURRED", 14, 14, &umr_bitfield_default },
	 { "OTG_TRIGB_RISING_EDGE_DETECT_CNTL", 16, 17, &umr_bitfield_default },
	 { "OTG_TRIGB_FALLING_EDGE_DETECT_CNTL", 18, 19, &umr_bitfield_default },
	 { "OTG_TRIGB_FREQUENCY_SELECT", 20, 21, &umr_bitfield_default },
	 { "OTG_TRIGB_DELAY", 24, 28, &umr_bitfield_default },
	 { "OTG_TRIGB_CLEAR", 31, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG1_OTG_TRIGB_MANUAL_TRIG[] = {
	 { "OTG_TRIGB_MANUAL_TRIG", 0, 0, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG1_OTG_FORCE_COUNT_NOW_CNTL[] = {
	 { "OTG_FORCE_COUNT_NOW_MODE", 0, 1, &umr_bitfield_default },
	 { "OTG_FORCE_COUNT_NOW_CHECK", 4, 4, &umr_bitfield_default },
	 { "OTG_FORCE_COUNT_NOW_TRIG_SEL", 8, 8, &umr_bitfield_default },
	 { "OTG_FORCE_COUNT_NOW_OCCURRED", 16, 16, &umr_bitfield_default },
	 { "OTG_FORCE_COUNT_NOW_CLEAR", 24, 24, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG1_OTG_FLOW_CONTROL[] = {
	 { "OTG_FLOW_CONTROL_SOURCE_SELECT", 0, 4, &umr_bitfield_default },
	 { "OTG_FLOW_CONTROL_POLARITY", 8, 8, &umr_bitfield_default },
	 { "OTG_FLOW_CONTROL_GRANULARITY", 16, 16, &umr_bitfield_default },
	 { "OTG_FLOW_CONTROL_INPUT_STATUS", 24, 24, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG1_OTG_STEREO_FORCE_NEXT_EYE[] = {
	 { "OTG_STEREO_FORCE_NEXT_EYE", 0, 1, &umr_bitfield_default },
	 { "OTG_AVSYNC_FRAME_COUNTER", 8, 15, &umr_bitfield_default },
	 { "OTG_AVSYNC_LINE_COUNTER", 16, 28, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG1_OTG_AVSYNC_COUNTER[] = {
	 { "OTG_AVSYNC_COUNTER", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG1_OTG_CONTROL[] = {
	 { "OTG_MASTER_EN", 0, 0, &umr_bitfield_default },
	 { "OTG_DISABLE_POINT_CNTL", 8, 9, &umr_bitfield_default },
	 { "OTG_START_POINT_CNTL", 12, 12, &umr_bitfield_default },
	 { "OTG_FIELD_NUMBER_CNTL", 13, 13, &umr_bitfield_default },
	 { "OTG_FIELD_NUMBER_POLARITY", 14, 14, &umr_bitfield_default },
	 { "OTG_CURRENT_MASTER_EN_STATE", 16, 16, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG1_OTG_BLANK_CONTROL[] = {
	 { "OTG_CURRENT_BLANK_STATE", 0, 0, &umr_bitfield_default },
	 { "OTG_BLANK_DATA_EN", 8, 8, &umr_bitfield_default },
	 { "OTG_BLANK_DE_MODE", 16, 16, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG1_OTG_PIPE_ABORT_CONTROL[] = {
	 { "OTG_PIPE_ABORT", 0, 0, &umr_bitfield_default },
	 { "OTG_PIPE_ABORT_DONE", 8, 8, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG1_OTG_INTERLACE_CONTROL[] = {
	 { "OTG_INTERLACE_ENABLE", 0, 0, &umr_bitfield_default },
	 { "OTG_INTERLACE_FORCE_NEXT_FIELD", 16, 17, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG1_OTG_INTERLACE_STATUS[] = {
	 { "OTG_INTERLACE_CURRENT_FIELD", 0, 0, &umr_bitfield_default },
	 { "OTG_INTERLACE_NEXT_FIELD", 1, 1, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG1_OTG_FIELD_INDICATION_CONTROL[] = {
	 { "OTG_FIELD_INDICATION_OUTPUT_POLARITY", 0, 0, &umr_bitfield_default },
	 { "OTG_FIELD_ALIGNMENT", 1, 1, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG1_OTG_PIXEL_DATA_READBACK0[] = {
	 { "OTG_PIXEL_DATA_BLUE_CB", 0, 15, &umr_bitfield_default },
	 { "OTG_PIXEL_DATA_GREEN_Y", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG1_OTG_PIXEL_DATA_READBACK1[] = {
	 { "OTG_PIXEL_DATA_RED_CR", 0, 15, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG1_OTG_STATUS[] = {
	 { "OTG_V_BLANK", 0, 0, &umr_bitfield_default },
	 { "OTG_V_ACTIVE_DISP", 1, 1, &umr_bitfield_default },
	 { "OTG_V_SYNC_A", 2, 2, &umr_bitfield_default },
	 { "OTG_V_UPDATE", 3, 3, &umr_bitfield_default },
	 { "OTG_V_BLANK_3D_STRUCTURE", 5, 5, &umr_bitfield_default },
	 { "OTG_H_BLANK", 16, 16, &umr_bitfield_default },
	 { "OTG_H_ACTIVE_DISP", 17, 17, &umr_bitfield_default },
	 { "OTG_H_SYNC_A", 18, 18, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG1_OTG_STATUS_POSITION[] = {
	 { "OTG_VERT_COUNT", 0, 14, &umr_bitfield_default },
	 { "OTG_HORZ_COUNT", 16, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG1_OTG_NOM_VERT_POSITION[] = {
	 { "OTG_VERT_COUNT_NOM", 0, 14, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG1_OTG_STATUS_FRAME_COUNT[] = {
	 { "OTG_FRAME_COUNT", 0, 23, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG1_OTG_STATUS_VF_COUNT[] = {
	 { "OTG_VF_COUNT", 0, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG1_OTG_STATUS_HV_COUNT[] = {
	 { "OTG_HV_COUNT", 0, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG1_OTG_COUNT_CONTROL[] = {
	 { "OTG_HORZ_COUNT_BY2_EN", 0, 0, &umr_bitfield_default },
	 { "OTG_HORZ_REPETITION_COUNT", 1, 4, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG1_OTG_COUNT_RESET[] = {
	 { "OTG_RESET_FRAME_COUNT", 0, 0, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG1_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE[] = {
	 { "OTG_MANUAL_FORCE_VSYNC_NEXT_LINE", 0, 0, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG1_OTG_VERT_SYNC_CONTROL[] = {
	 { "OTG_FORCE_VSYNC_NEXT_LINE_OCCURRED", 0, 0, &umr_bitfield_default },
	 { "OTG_FORCE_VSYNC_NEXT_LINE_CLEAR", 8, 8, &umr_bitfield_default },
	 { "OTG_AUTO_FORCE_VSYNC_MODE", 16, 17, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG1_OTG_STEREO_STATUS[] = {
	 { "OTG_STEREO_CURRENT_EYE", 0, 0, &umr_bitfield_default },
	 { "OTG_STEREO_SYNC_OUTPUT", 8, 8, &umr_bitfield_default },
	 { "OTG_STEREO_SYNC_SELECT", 16, 16, &umr_bitfield_default },
	 { "OTG_STEREO_EYE_FLAG", 20, 20, &umr_bitfield_default },
	 { "OTG_STEREO_FORCE_NEXT_EYE_PENDING", 24, 25, &umr_bitfield_default },
	 { "OTG_CURRENT_3D_STRUCTURE_STATE", 30, 30, &umr_bitfield_default },
	 { "OTG_CURRENT_STEREOSYNC_EN_STATE", 31, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG1_OTG_STEREO_CONTROL[] = {
	 { "OTG_STEREO_SYNC_OUTPUT_LINE_NUM", 0, 14, &umr_bitfield_default },
	 { "OTG_STEREO_SYNC_OUTPUT_POLARITY", 15, 15, &umr_bitfield_default },
	 { "OTG_STEREO_EYE_FLAG_POLARITY", 17, 17, &umr_bitfield_default },
	 { "OTG_DISABLE_STEREOSYNC_OUTPUT_FOR_DP", 18, 18, &umr_bitfield_default },
	 { "OTG_DISABLE_FIELD_NUM", 19, 19, &umr_bitfield_default },
	 { "OTG_DISABLE_V_BLANK_FOR_DP_FIX", 20, 20, &umr_bitfield_default },
	 { "OTG_STEREO_EN", 24, 24, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG1_OTG_SNAPSHOT_STATUS[] = {
	 { "OTG_SNAPSHOT_OCCURRED", 0, 0, &umr_bitfield_default },
	 { "OTG_SNAPSHOT_CLEAR", 1, 1, &umr_bitfield_default },
	 { "OTG_SNAPSHOT_MANUAL_TRIGGER", 2, 2, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG1_OTG_SNAPSHOT_CONTROL[] = {
	 { "OTG_AUTO_SNAPSHOT_TRIG_SEL", 0, 1, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG1_OTG_SNAPSHOT_POSITION[] = {
	 { "OTG_SNAPSHOT_VERT_COUNT", 0, 14, &umr_bitfield_default },
	 { "OTG_SNAPSHOT_HORZ_COUNT", 16, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG1_OTG_SNAPSHOT_FRAME[] = {
	 { "OTG_SNAPSHOT_FRAME_COUNT", 0, 23, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG1_OTG_INTERRUPT_CONTROL[] = {
	 { "OTG_SNAPSHOT_INT_MSK", 0, 0, &umr_bitfield_default },
	 { "OTG_SNAPSHOT_INT_TYPE", 1, 1, &umr_bitfield_default },
	 { "OTG_FORCE_COUNT_NOW_INT_MSK", 8, 8, &umr_bitfield_default },
	 { "OTG_FORCE_COUNT_NOW_INT_TYPE", 9, 9, &umr_bitfield_default },
	 { "OTG_FORCE_VSYNC_NEXT_LINE_INT_MSK", 16, 16, &umr_bitfield_default },
	 { "OTG_FORCE_VSYNC_NEXT_LINE_INT_TYPE", 17, 17, &umr_bitfield_default },
	 { "OTG_TRIGA_INT_MSK", 24, 24, &umr_bitfield_default },
	 { "OTG_TRIGB_INT_MSK", 25, 25, &umr_bitfield_default },
	 { "OTG_TRIGA_INT_TYPE", 26, 26, &umr_bitfield_default },
	 { "OTG_TRIGB_INT_TYPE", 27, 27, &umr_bitfield_default },
	 { "OTG_VSYNC_NOM_INT_MSK", 28, 28, &umr_bitfield_default },
	 { "OTG_VSYNC_NOM_INT_TYPE", 29, 29, &umr_bitfield_default },
	 { "OTG_GSL_VSYNC_GAP_INT_MSK", 30, 30, &umr_bitfield_default },
	 { "OTG_GSL_VSYNC_GAP_INT_TYPE", 31, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG1_OTG_UPDATE_LOCK[] = {
	 { "OTG_UPDATE_LOCK", 0, 0, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG1_OTG_DOUBLE_BUFFER_CONTROL[] = {
	 { "OTG_UPDATE_PENDING", 0, 0, &umr_bitfield_default },
	 { "OTG_H_TIMING_DIV_BY2_DB_UPDATE_PENDING", 2, 2, &umr_bitfield_default },
	 { "OTG_BLANK_DATA_EN_UPDATE_PENDING", 3, 3, &umr_bitfield_default },
	 { "OTG_RANGE_TIMING_DBUF_UPDATE_PENDING", 4, 4, &umr_bitfield_default },
	 { "OTG_TIMING_DB_UPDATE_PENDING", 5, 5, &umr_bitfield_default },
	 { "OTG_3D_CTRL_DB_UPDATE_PENDING", 6, 6, &umr_bitfield_default },
	 { "OTG_3D_STRUCTURE_EN_DB_UPDATE_PENDING", 7, 7, &umr_bitfield_default },
	 { "OTG_UPDATE_INSTANTLY", 8, 8, &umr_bitfield_default },
	 { "OTG_BLANK_DATA_DOUBLE_BUFFER_EN", 16, 16, &umr_bitfield_default },
	 { "OTG_RANGE_TIMING_DBUF_UPDATE_MODE", 24, 25, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG1_OTG_TEST_PATTERN_CONTROL[] = {
	 { "OTG_TEST_PATTERN_EN", 0, 0, &umr_bitfield_default },
	 { "OTG_TEST_PATTERN_MODE", 8, 10, &umr_bitfield_default },
	 { "OTG_TEST_PATTERN_DYNAMIC_RANGE", 16, 16, &umr_bitfield_default },
	 { "OTG_TEST_PATTERN_COLOR_FORMAT", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG1_OTG_TEST_PATTERN_PARAMETERS[] = {
	 { "OTG_TEST_PATTERN_INC0", 0, 3, &umr_bitfield_default },
	 { "OTG_TEST_PATTERN_INC1", 4, 7, &umr_bitfield_default },
	 { "OTG_TEST_PATTERN_VRES", 8, 11, &umr_bitfield_default },
	 { "OTG_TEST_PATTERN_HRES", 12, 15, &umr_bitfield_default },
	 { "OTG_TEST_PATTERN_RAMP0_OFFSET", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG1_OTG_TEST_PATTERN_COLOR[] = {
	 { "OTG_TEST_PATTERN_DATA", 0, 15, &umr_bitfield_default },
	 { "OTG_TEST_PATTERN_MASK", 16, 21, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG1_OTG_MASTER_EN[] = {
	 { "OTG_MASTER_EN", 0, 0, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG1_OTG_BLANK_DATA_COLOR[] = {
	 { "OTG_BLANK_DATA_COLOR_BLUE_CB", 0, 9, &umr_bitfield_default },
	 { "OTG_BLANK_DATA_COLOR_GREEN_Y", 10, 19, &umr_bitfield_default },
	 { "OTG_BLANK_DATA_COLOR_RED_CR", 20, 29, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG1_OTG_BLANK_DATA_COLOR_EXT[] = {
	 { "OTG_BLANK_DATA_COLOR_BLUE_CB_EXT", 0, 5, &umr_bitfield_default },
	 { "OTG_BLANK_DATA_COLOR_GREEN_Y_EXT", 8, 13, &umr_bitfield_default },
	 { "OTG_BLANK_DATA_COLOR_RED_CR_EXT", 16, 21, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG1_OTG_BLACK_COLOR[] = {
	 { "OTG_BLACK_COLOR_B_CB", 0, 9, &umr_bitfield_default },
	 { "OTG_BLACK_COLOR_G_Y", 10, 19, &umr_bitfield_default },
	 { "OTG_BLACK_COLOR_R_CR", 20, 29, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG1_OTG_BLACK_COLOR_EXT[] = {
	 { "OTG_BLACK_COLOR_B_CB_EXT", 0, 5, &umr_bitfield_default },
	 { "OTG_BLACK_COLOR_G_Y_EXT", 8, 13, &umr_bitfield_default },
	 { "OTG_BLACK_COLOR_R_CR_EXT", 16, 21, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG1_OTG_VERTICAL_INTERRUPT0_POSITION[] = {
	 { "OTG_VERTICAL_INTERRUPT0_LINE_START", 0, 14, &umr_bitfield_default },
	 { "OTG_VERTICAL_INTERRUPT0_LINE_END", 16, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG1_OTG_VERTICAL_INTERRUPT0_CONTROL[] = {
	 { "OTG_VERTICAL_INTERRUPT0_OUTPUT_POLARITY", 4, 4, &umr_bitfield_default },
	 { "OTG_VERTICAL_INTERRUPT0_INT_ENABLE", 8, 8, &umr_bitfield_default },
	 { "OTG_VERTICAL_INTERRUPT0_STATUS", 12, 12, &umr_bitfield_default },
	 { "OTG_VERTICAL_INTERRUPT0_INT_STATUS", 16, 16, &umr_bitfield_default },
	 { "OTG_VERTICAL_INTERRUPT0_CLEAR", 20, 20, &umr_bitfield_default },
	 { "OTG_VERTICAL_INTERRUPT0_INT_TYPE", 24, 24, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG1_OTG_VERTICAL_INTERRUPT1_POSITION[] = {
	 { "OTG_VERTICAL_INTERRUPT1_LINE_START", 0, 14, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG1_OTG_VERTICAL_INTERRUPT1_CONTROL[] = {
	 { "OTG_VERTICAL_INTERRUPT1_INT_ENABLE", 8, 8, &umr_bitfield_default },
	 { "OTG_VERTICAL_INTERRUPT1_STATUS", 12, 12, &umr_bitfield_default },
	 { "OTG_VERTICAL_INTERRUPT1_INT_STATUS", 16, 16, &umr_bitfield_default },
	 { "OTG_VERTICAL_INTERRUPT1_CLEAR", 20, 20, &umr_bitfield_default },
	 { "OTG_VERTICAL_INTERRUPT1_INT_TYPE", 24, 24, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG1_OTG_VERTICAL_INTERRUPT2_POSITION[] = {
	 { "OTG_VERTICAL_INTERRUPT2_LINE_START", 0, 14, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG1_OTG_VERTICAL_INTERRUPT2_CONTROL[] = {
	 { "OTG_VERTICAL_INTERRUPT2_INT_ENABLE", 8, 8, &umr_bitfield_default },
	 { "OTG_VERTICAL_INTERRUPT2_STATUS", 12, 12, &umr_bitfield_default },
	 { "OTG_VERTICAL_INTERRUPT2_INT_STATUS", 16, 16, &umr_bitfield_default },
	 { "OTG_VERTICAL_INTERRUPT2_CLEAR", 20, 20, &umr_bitfield_default },
	 { "OTG_VERTICAL_INTERRUPT2_INT_TYPE", 24, 24, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG1_OTG_CRC_CNTL[] = {
	 { "OTG_CRC_EN", 0, 0, &umr_bitfield_default },
	 { "OTG_CRC_DUAL_LINK_EN", 1, 1, &umr_bitfield_default },
	 { "OTG_CRC_DUAL_LINK_MODE", 2, 2, &umr_bitfield_default },
	 { "OTG_CRC_BLANK_ONLY", 3, 3, &umr_bitfield_default },
	 { "OTG_CRC_CONT_EN", 4, 4, &umr_bitfield_default },
	 { "OTG_CRC_CAPTURE_START_SEL", 5, 6, &umr_bitfield_default },
	 { "OTG_CRC_STEREO_MODE", 8, 9, &umr_bitfield_default },
	 { "OTG_CRC_INTERLACE_MODE", 12, 13, &umr_bitfield_default },
	 { "OTG_CRC_MULTI_STREAM_MODE", 16, 18, &umr_bitfield_default },
	 { "OTG_CRC_USE_NEW_AND_REPEATED_PIXELS", 19, 19, &umr_bitfield_default },
	 { "OTG_CRC0_SELECT", 20, 22, &umr_bitfield_default },
	 { "OTG_CRC1_SELECT", 24, 26, &umr_bitfield_default },
	 { "OTG_ONE_SHOT_CRC0_PENDING", 28, 28, &umr_bitfield_default },
	 { "OTG_ONE_SHOT_CRC1_PENDING", 29, 29, &umr_bitfield_default },
	 { "OTG_ONE_SHOT_CRC2_PENDING", 30, 30, &umr_bitfield_default },
	 { "OTG_ONE_SHOT_CRC3_PENDING", 31, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG1_OTG_CRC0_WINDOWA_X_CONTROL[] = {
	 { "OTG_CRC0_WINDOWA_X_START", 0, 14, &umr_bitfield_default },
	 { "OTG_CRC0_WINDOWA_X_END", 16, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG1_OTG_CRC0_WINDOWA_Y_CONTROL[] = {
	 { "OTG_CRC0_WINDOWA_Y_START", 0, 14, &umr_bitfield_default },
	 { "OTG_CRC0_WINDOWA_Y_END", 16, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG1_OTG_CRC0_WINDOWB_X_CONTROL[] = {
	 { "OTG_CRC0_WINDOWB_X_START", 0, 14, &umr_bitfield_default },
	 { "OTG_CRC0_WINDOWB_X_END", 16, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG1_OTG_CRC0_WINDOWB_Y_CONTROL[] = {
	 { "OTG_CRC0_WINDOWB_Y_START", 0, 14, &umr_bitfield_default },
	 { "OTG_CRC0_WINDOWB_Y_END", 16, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG1_OTG_CRC0_DATA_RG[] = {
	 { "CRC0_R_CR", 0, 15, &umr_bitfield_default },
	 { "CRC0_G_Y", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG1_OTG_CRC0_DATA_B[] = {
	 { "CRC0_B_CB", 0, 15, &umr_bitfield_default },
	 { "CRC0_C", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG1_OTG_CRC1_WINDOWA_X_CONTROL[] = {
	 { "OTG_CRC1_WINDOWA_X_START", 0, 14, &umr_bitfield_default },
	 { "OTG_CRC1_WINDOWA_X_END", 16, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG1_OTG_CRC1_WINDOWA_Y_CONTROL[] = {
	 { "OTG_CRC1_WINDOWA_Y_START", 0, 14, &umr_bitfield_default },
	 { "OTG_CRC1_WINDOWA_Y_END", 16, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG1_OTG_CRC1_WINDOWB_X_CONTROL[] = {
	 { "OTG_CRC1_WINDOWB_X_START", 0, 14, &umr_bitfield_default },
	 { "OTG_CRC1_WINDOWB_X_END", 16, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG1_OTG_CRC1_WINDOWB_Y_CONTROL[] = {
	 { "OTG_CRC1_WINDOWB_Y_START", 0, 14, &umr_bitfield_default },
	 { "OTG_CRC1_WINDOWB_Y_END", 16, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG1_OTG_CRC1_DATA_RG[] = {
	 { "CRC1_R_CR", 0, 15, &umr_bitfield_default },
	 { "CRC1_G_Y", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG1_OTG_CRC1_DATA_B[] = {
	 { "CRC1_B_CB", 0, 15, &umr_bitfield_default },
	 { "CRC1_C", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG1_OTG_CRC2_DATA_RG[] = {
	 { "CRC2_R_CR", 0, 15, &umr_bitfield_default },
	 { "CRC2_G_Y", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG1_OTG_CRC2_DATA_B[] = {
	 { "CRC2_B_CB", 0, 15, &umr_bitfield_default },
	 { "CRC2_C", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG1_OTG_CRC3_DATA_RG[] = {
	 { "CRC3_R_CR", 0, 15, &umr_bitfield_default },
	 { "CRC3_G_Y", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG1_OTG_CRC3_DATA_B[] = {
	 { "CRC3_B_CB", 0, 15, &umr_bitfield_default },
	 { "CRC3_C", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG1_OTG_CRC_SIG_RED_GREEN_MASK[] = {
	 { "OTG_CRC_SIG_RED_MASK", 0, 15, &umr_bitfield_default },
	 { "OTG_CRC_SIG_GREEN_MASK", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG1_OTG_CRC_SIG_BLUE_CONTROL_MASK[] = {
	 { "OTG_CRC_SIG_BLUE_MASK", 0, 15, &umr_bitfield_default },
	 { "OTG_CRC_SIG_CONTROL_MASK", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG1_OTG_STATIC_SCREEN_CONTROL[] = {
	 { "OTG_STATIC_SCREEN_EVENT_MASK", 0, 15, &umr_bitfield_default },
	 { "OTG_STATIC_SCREEN_FRAME_COUNT", 16, 23, &umr_bitfield_default },
	 { "OTG_CPU_SS_INT_ENABLE", 24, 24, &umr_bitfield_default },
	 { "OTG_SS_STATUS", 25, 25, &umr_bitfield_default },
	 { "OTG_CPU_SS_INT_STATUS", 26, 26, &umr_bitfield_default },
	 { "OTG_CPU_SS_INT_CLEAR", 27, 27, &umr_bitfield_default },
	 { "OTG_CPU_SS_INT_TYPE", 28, 28, &umr_bitfield_default },
	 { "OTG_STATIC_SCREEN_OVERRIDE", 30, 30, &umr_bitfield_default },
	 { "OTG_STATIC_SCREEN_OVERRIDE_VALUE", 31, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG1_OTG_3D_STRUCTURE_CONTROL[] = {
	 { "OTG_3D_STRUCTURE_EN", 0, 0, &umr_bitfield_default },
	 { "OTG_3D_STRUCTURE_V_UPDATE_MODE", 8, 9, &umr_bitfield_default },
	 { "OTG_3D_STRUCTURE_STEREO_SEL_OVR", 12, 12, &umr_bitfield_default },
	 { "OTG_3D_STRUCTURE_F_COUNT_RESET", 16, 16, &umr_bitfield_default },
	 { "OTG_3D_STRUCTURE_F_COUNT_RESET_PENDING", 17, 17, &umr_bitfield_default },
	 { "OTG_3D_STRUCTURE_F_COUNT", 18, 19, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG1_OTG_GSL_VSYNC_GAP[] = {
	 { "OTG_GSL_VSYNC_GAP_LIMIT", 0, 7, &umr_bitfield_default },
	 { "OTG_GSL_VSYNC_GAP_DELAY", 8, 15, &umr_bitfield_default },
	 { "OTG_GSL_VSYNC_GAP_SOURCE_SEL", 16, 16, &umr_bitfield_default },
	 { "OTG_GSL_VSYNC_GAP_MODE", 17, 18, &umr_bitfield_default },
	 { "OTG_GSL_VSYNC_GAP_CLEAR", 19, 19, &umr_bitfield_default },
	 { "OTG_GSL_VSYNC_GAP_OCCURRED", 20, 20, &umr_bitfield_default },
	 { "OTG_GSL_VSYNC_GAP_MASTER_FASTER", 23, 23, &umr_bitfield_default },
	 { "OTG_GSL_VSYNC_GAP", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG1_OTG_MASTER_UPDATE_MODE[] = {
	 { "MASTER_UPDATE_INTERLACED_MODE", 0, 1, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG1_OTG_CLOCK_CONTROL[] = {
	 { "OTG_CLOCK_EN", 0, 0, &umr_bitfield_default },
	 { "OTG_CLOCK_GATE_DIS", 1, 1, &umr_bitfield_default },
	 { "OTG_SOFT_RESET", 4, 4, &umr_bitfield_default },
	 { "OTG_CLOCK_ON", 8, 8, &umr_bitfield_default },
	 { "OTG_BUSY", 16, 16, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG1_OTG_VSTARTUP_PARAM[] = {
	 { "VSTARTUP_START", 0, 9, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG1_OTG_VUPDATE_PARAM[] = {
	 { "VUPDATE_OFFSET", 0, 15, &umr_bitfield_default },
	 { "VUPDATE_WIDTH", 16, 25, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG1_OTG_VREADY_PARAM[] = {
	 { "VREADY_OFFSET", 0, 15, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG1_OTG_GLOBAL_SYNC_STATUS[] = {
	 { "VSTARTUP_INT_EN", 0, 0, &umr_bitfield_default },
	 { "VSTARTUP_INT_TYPE", 1, 1, &umr_bitfield_default },
	 { "VSTARTUP_EVENT_OCCURRED", 2, 2, &umr_bitfield_default },
	 { "VSTARTUP_INT_STATUS", 3, 3, &umr_bitfield_default },
	 { "VSTARTUP_EVENT_CLEAR", 4, 4, &umr_bitfield_default },
	 { "VUPDATE_INT_EN", 5, 5, &umr_bitfield_default },
	 { "VUPDATE_INT_TYPE", 6, 6, &umr_bitfield_default },
	 { "VUPDATE_INT_POSITION_SEL", 7, 7, &umr_bitfield_default },
	 { "VUPDATE_EVENT_OCCURRED", 8, 8, &umr_bitfield_default },
	 { "VUPDATE_INT_STATUS", 9, 9, &umr_bitfield_default },
	 { "VUPDATE_EVENT_CLEAR", 10, 10, &umr_bitfield_default },
	 { "VUPDATE_STATUS", 11, 11, &umr_bitfield_default },
	 { "VUPDATE_NO_LOCK_INT_EN", 12, 12, &umr_bitfield_default },
	 { "VUPDATE_NO_LOCK_INT_TYPE", 13, 13, &umr_bitfield_default },
	 { "VUPDATE_NO_LOCK_EVENT_OCCURRED", 14, 14, &umr_bitfield_default },
	 { "VUPDATE_NO_LOCK_INT_STATUS", 15, 15, &umr_bitfield_default },
	 { "VUPDATE_NO_LOCK_EVENT_CLEAR", 16, 16, &umr_bitfield_default },
	 { "VUPDATE_NO_LOCK_STATUS", 17, 17, &umr_bitfield_default },
	 { "VREADY_INT_EN", 18, 18, &umr_bitfield_default },
	 { "VREADY_INT_TYPE", 19, 19, &umr_bitfield_default },
	 { "VREADY_EVENT_OCCURRED", 20, 20, &umr_bitfield_default },
	 { "VREADY_INT_STATUS", 21, 21, &umr_bitfield_default },
	 { "VREADY_EVENT_CLEAR", 22, 22, &umr_bitfield_default },
	 { "STEREO_SELECT_STATUS", 24, 24, &umr_bitfield_default },
	 { "FIELD_NUMBER_STATUS", 25, 25, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG1_OTG_MASTER_UPDATE_LOCK[] = {
	 { "OTG_MASTER_UPDATE_LOCK", 0, 0, &umr_bitfield_default },
	 { "UPDATE_LOCK_STATUS", 8, 8, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG1_OTG_GSL_CONTROL[] = {
	 { "OTG_GSL0_EN", 0, 0, &umr_bitfield_default },
	 { "OTG_GSL1_EN", 1, 1, &umr_bitfield_default },
	 { "OTG_GSL2_EN", 2, 2, &umr_bitfield_default },
	 { "OTG_GSL_MASTER_EN", 3, 3, &umr_bitfield_default },
	 { "OTG_GSL_FORCE_DELAY", 16, 20, &umr_bitfield_default },
	 { "OTG_GSL_CHECK_ALL_FIELDS", 28, 28, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG1_OTG_GSL_WINDOW_X[] = {
	 { "OTG_GSL_WINDOW_START_X", 0, 14, &umr_bitfield_default },
	 { "OTG_GSL_WINDOW_END_X", 16, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG1_OTG_GSL_WINDOW_Y[] = {
	 { "OTG_GSL_WINDOW_START_Y", 0, 14, &umr_bitfield_default },
	 { "OTG_GSL_WINDOW_END_Y", 16, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG1_OTG_VUPDATE_KEEPOUT[] = {
	 { "MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_START_OFFSET", 0, 15, &umr_bitfield_default },
	 { "MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_END_OFFSET", 16, 25, &umr_bitfield_default },
	 { "OTG_MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_EN", 31, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG1_OTG_GLOBAL_CONTROL0[] = {
	 { "OTG_MASTER_UPDATE_LOCK_HTOTAL_KEEPOUT", 0, 7, &umr_bitfield_default },
	 { "OTG_MASTER_UPDATE_LOCK_HTOTAL_KEEPOUT_EN", 8, 8, &umr_bitfield_default },
	 { "OTG_MASTER_UPDATE_LOCK_SEL", 25, 27, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG1_OTG_GLOBAL_CONTROL1[] = {
	 { "MASTER_UPDATE_LOCK_DB_X", 0, 14, &umr_bitfield_default },
	 { "MASTER_UPDATE_LOCK_DB_Y", 16, 30, &umr_bitfield_default },
	 { "MASTER_UPDATE_LOCK_DB_EN", 31, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG1_OTG_GLOBAL_CONTROL2[] = {
	 { "DIG_UPDATE_LOCATION", 0, 9, &umr_bitfield_default },
	 { "GLOBAL_UPDATE_LOCK_EN", 10, 10, &umr_bitfield_default },
	 { "MANUAL_FLOW_CONTROL_SEL", 16, 18, &umr_bitfield_default },
	 { "DCCG_VUPDATE_MODE", 31, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG1_OTG_GLOBAL_CONTROL3[] = {
	 { "MASTER_UPDATE_LOCK_DB_FIELD", 0, 1, &umr_bitfield_default },
	 { "MASTER_UPDATE_LOCK_DB_STEREO_SEL", 4, 5, &umr_bitfield_default },
	 { "MASTER_UPDATE_LOCK_DB_FIELD_STEREO_FLAG_SEL", 8, 8, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG1_OTG_TRIG_MANUAL_CONTROL[] = {
	 { "TRIG_MANUAL_CONTROL", 0, 0, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG1_OTG_MANUAL_FLOW_CONTROL[] = {
	 { "MANUAL_FLOW_CONTROL", 0, 0, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG1_OTG_RANGE_TIMING_INT_STATUS[] = {
	 { "OTG_RANGE_TIMING_UPDATE_OCCURRED", 0, 0, &umr_bitfield_default },
	 { "OTG_RANGE_TIMING_UPDATE_OCCURRED_INT", 4, 4, &umr_bitfield_default },
	 { "OTG_RANGE_TIMING_UPDATE_OCCURRED_CLEAR", 8, 8, &umr_bitfield_default },
	 { "OTG_RANGE_TIMING_UPDATE_OCCURRED_INT_MSK", 12, 12, &umr_bitfield_default },
	 { "OTG_RANGE_TIMING_UPDATE_OCCURRED_INT_TYPE", 16, 16, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG1_OTG_DRR_CONTROL[] = {
	 { "OTG_DRR_AVERAGE_FRAME", 0, 2, &umr_bitfield_default },
	 { "OTG_V_TOTAL_LAST_USED_BY_DRR", 16, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG1_OTG_REQUEST_CONTROL[] = {
	 { "OTG_REQUEST_MODE_FOR_H_DUPLICATE", 0, 0, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG1_OTG_SPARE_REGISTER[] = {
	 { "OTG_SPARE_REG", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG2_OTG_H_TOTAL[] = {
	 { "OTG_H_TOTAL", 0, 14, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG2_OTG_H_BLANK_START_END[] = {
	 { "OTG_H_BLANK_START", 0, 14, &umr_bitfield_default },
	 { "OTG_H_BLANK_END", 16, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG2_OTG_H_SYNC_A[] = {
	 { "OTG_H_SYNC_A_START", 0, 14, &umr_bitfield_default },
	 { "OTG_H_SYNC_A_END", 16, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG2_OTG_H_SYNC_A_CNTL[] = {
	 { "OTG_H_SYNC_A_POL", 0, 0, &umr_bitfield_default },
	 { "OTG_COMP_SYNC_A_EN", 16, 16, &umr_bitfield_default },
	 { "OTG_H_SYNC_A_CUTOFF", 17, 17, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG2_OTG_H_TIMING_CNTL[] = {
	 { "OTG_H_TIMING_DIV_BY2", 0, 0, &umr_bitfield_default },
	 { "OTG_H_TIMING_DIV_BY2_UPDATE_MODE", 8, 8, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG2_OTG_V_TOTAL[] = {
	 { "OTG_V_TOTAL", 0, 14, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG2_OTG_V_TOTAL_MIN[] = {
	 { "OTG_V_TOTAL_MIN", 0, 14, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG2_OTG_V_TOTAL_MAX[] = {
	 { "OTG_V_TOTAL_MAX", 0, 14, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG2_OTG_V_TOTAL_MID[] = {
	 { "OTG_V_TOTAL_MID", 0, 14, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG2_OTG_V_TOTAL_CONTROL[] = {
	 { "OTG_V_TOTAL_MIN_SEL", 0, 0, &umr_bitfield_default },
	 { "OTG_V_TOTAL_MAX_SEL", 1, 1, &umr_bitfield_default },
	 { "OTG_VTOTAL_MID_REPLACING_MAX_EN", 2, 2, &umr_bitfield_default },
	 { "OTG_VTOTAL_MID_REPLACING_MIN_EN", 3, 3, &umr_bitfield_default },
	 { "OTG_FORCE_LOCK_ON_EVENT", 4, 4, &umr_bitfield_default },
	 { "OTG_SET_V_TOTAL_MIN_MASK_EN", 7, 7, &umr_bitfield_default },
	 { "OTG_VTOTAL_MID_FRAME_NUM", 8, 15, &umr_bitfield_default },
	 { "OTG_SET_V_TOTAL_MIN_MASK", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG2_OTG_V_TOTAL_INT_STATUS[] = {
	 { "OTG_SET_V_TOTAL_MIN_EVENT_OCCURED", 0, 0, &umr_bitfield_default },
	 { "OTG_SET_V_TOTAL_MIN_EVENT_OCCURED_INT", 4, 4, &umr_bitfield_default },
	 { "OTG_SET_V_TOTAL_MIN_EVENT_OCCURED_ACK", 8, 8, &umr_bitfield_default },
	 { "OTG_SET_V_TOTAL_MIN_EVENT_OCCURED_MSK", 12, 12, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG2_OTG_VSYNC_NOM_INT_STATUS[] = {
	 { "OTG_VSYNC_NOM", 0, 0, &umr_bitfield_default },
	 { "OTG_VSYNC_NOM_INT_CLEAR", 4, 4, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG2_OTG_V_BLANK_START_END[] = {
	 { "OTG_V_BLANK_START", 0, 14, &umr_bitfield_default },
	 { "OTG_V_BLANK_END", 16, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG2_OTG_V_SYNC_A[] = {
	 { "OTG_V_SYNC_A_START", 0, 14, &umr_bitfield_default },
	 { "OTG_V_SYNC_A_END", 16, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG2_OTG_V_SYNC_A_CNTL[] = {
	 { "OTG_V_SYNC_A_POL", 0, 0, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG2_OTG_TRIGA_CNTL[] = {
	 { "OTG_TRIGA_SOURCE_SELECT", 0, 4, &umr_bitfield_default },
	 { "OTG_TRIGA_SOURCE_PIPE_SELECT", 5, 7, &umr_bitfield_default },
	 { "OTG_TRIGA_POLARITY_SELECT", 8, 10, &umr_bitfield_default },
	 { "OTG_TRIGA_RESYNC_BYPASS_EN", 11, 11, &umr_bitfield_default },
	 { "OTG_TRIGA_INPUT_STATUS", 12, 12, &umr_bitfield_default },
	 { "OTG_TRIGA_POLARITY_STATUS", 13, 13, &umr_bitfield_default },
	 { "OTG_TRIGA_OCCURRED", 14, 14, &umr_bitfield_default },
	 { "OTG_TRIGA_RISING_EDGE_DETECT_CNTL", 16, 17, &umr_bitfield_default },
	 { "OTG_TRIGA_FALLING_EDGE_DETECT_CNTL", 18, 19, &umr_bitfield_default },
	 { "OTG_TRIGA_FREQUENCY_SELECT", 20, 21, &umr_bitfield_default },
	 { "OTG_TRIGA_DELAY", 24, 28, &umr_bitfield_default },
	 { "OTG_TRIGA_CLEAR", 31, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG2_OTG_TRIGA_MANUAL_TRIG[] = {
	 { "OTG_TRIGA_MANUAL_TRIG", 0, 0, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG2_OTG_TRIGB_CNTL[] = {
	 { "OTG_TRIGB_SOURCE_SELECT", 0, 4, &umr_bitfield_default },
	 { "OTG_TRIGB_SOURCE_PIPE_SELECT", 5, 7, &umr_bitfield_default },
	 { "OTG_TRIGB_POLARITY_SELECT", 8, 10, &umr_bitfield_default },
	 { "OTG_TRIGB_RESYNC_BYPASS_EN", 11, 11, &umr_bitfield_default },
	 { "OTG_TRIGB_INPUT_STATUS", 12, 12, &umr_bitfield_default },
	 { "OTG_TRIGB_POLARITY_STATUS", 13, 13, &umr_bitfield_default },
	 { "OTG_TRIGB_OCCURRED", 14, 14, &umr_bitfield_default },
	 { "OTG_TRIGB_RISING_EDGE_DETECT_CNTL", 16, 17, &umr_bitfield_default },
	 { "OTG_TRIGB_FALLING_EDGE_DETECT_CNTL", 18, 19, &umr_bitfield_default },
	 { "OTG_TRIGB_FREQUENCY_SELECT", 20, 21, &umr_bitfield_default },
	 { "OTG_TRIGB_DELAY", 24, 28, &umr_bitfield_default },
	 { "OTG_TRIGB_CLEAR", 31, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG2_OTG_TRIGB_MANUAL_TRIG[] = {
	 { "OTG_TRIGB_MANUAL_TRIG", 0, 0, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG2_OTG_FORCE_COUNT_NOW_CNTL[] = {
	 { "OTG_FORCE_COUNT_NOW_MODE", 0, 1, &umr_bitfield_default },
	 { "OTG_FORCE_COUNT_NOW_CHECK", 4, 4, &umr_bitfield_default },
	 { "OTG_FORCE_COUNT_NOW_TRIG_SEL", 8, 8, &umr_bitfield_default },
	 { "OTG_FORCE_COUNT_NOW_OCCURRED", 16, 16, &umr_bitfield_default },
	 { "OTG_FORCE_COUNT_NOW_CLEAR", 24, 24, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG2_OTG_FLOW_CONTROL[] = {
	 { "OTG_FLOW_CONTROL_SOURCE_SELECT", 0, 4, &umr_bitfield_default },
	 { "OTG_FLOW_CONTROL_POLARITY", 8, 8, &umr_bitfield_default },
	 { "OTG_FLOW_CONTROL_GRANULARITY", 16, 16, &umr_bitfield_default },
	 { "OTG_FLOW_CONTROL_INPUT_STATUS", 24, 24, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG2_OTG_STEREO_FORCE_NEXT_EYE[] = {
	 { "OTG_STEREO_FORCE_NEXT_EYE", 0, 1, &umr_bitfield_default },
	 { "OTG_AVSYNC_FRAME_COUNTER", 8, 15, &umr_bitfield_default },
	 { "OTG_AVSYNC_LINE_COUNTER", 16, 28, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG2_OTG_AVSYNC_COUNTER[] = {
	 { "OTG_AVSYNC_COUNTER", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG2_OTG_CONTROL[] = {
	 { "OTG_MASTER_EN", 0, 0, &umr_bitfield_default },
	 { "OTG_DISABLE_POINT_CNTL", 8, 9, &umr_bitfield_default },
	 { "OTG_START_POINT_CNTL", 12, 12, &umr_bitfield_default },
	 { "OTG_FIELD_NUMBER_CNTL", 13, 13, &umr_bitfield_default },
	 { "OTG_FIELD_NUMBER_POLARITY", 14, 14, &umr_bitfield_default },
	 { "OTG_CURRENT_MASTER_EN_STATE", 16, 16, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG2_OTG_BLANK_CONTROL[] = {
	 { "OTG_CURRENT_BLANK_STATE", 0, 0, &umr_bitfield_default },
	 { "OTG_BLANK_DATA_EN", 8, 8, &umr_bitfield_default },
	 { "OTG_BLANK_DE_MODE", 16, 16, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG2_OTG_PIPE_ABORT_CONTROL[] = {
	 { "OTG_PIPE_ABORT", 0, 0, &umr_bitfield_default },
	 { "OTG_PIPE_ABORT_DONE", 8, 8, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG2_OTG_INTERLACE_CONTROL[] = {
	 { "OTG_INTERLACE_ENABLE", 0, 0, &umr_bitfield_default },
	 { "OTG_INTERLACE_FORCE_NEXT_FIELD", 16, 17, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG2_OTG_INTERLACE_STATUS[] = {
	 { "OTG_INTERLACE_CURRENT_FIELD", 0, 0, &umr_bitfield_default },
	 { "OTG_INTERLACE_NEXT_FIELD", 1, 1, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG2_OTG_FIELD_INDICATION_CONTROL[] = {
	 { "OTG_FIELD_INDICATION_OUTPUT_POLARITY", 0, 0, &umr_bitfield_default },
	 { "OTG_FIELD_ALIGNMENT", 1, 1, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG2_OTG_PIXEL_DATA_READBACK0[] = {
	 { "OTG_PIXEL_DATA_BLUE_CB", 0, 15, &umr_bitfield_default },
	 { "OTG_PIXEL_DATA_GREEN_Y", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG2_OTG_PIXEL_DATA_READBACK1[] = {
	 { "OTG_PIXEL_DATA_RED_CR", 0, 15, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG2_OTG_STATUS[] = {
	 { "OTG_V_BLANK", 0, 0, &umr_bitfield_default },
	 { "OTG_V_ACTIVE_DISP", 1, 1, &umr_bitfield_default },
	 { "OTG_V_SYNC_A", 2, 2, &umr_bitfield_default },
	 { "OTG_V_UPDATE", 3, 3, &umr_bitfield_default },
	 { "OTG_V_BLANK_3D_STRUCTURE", 5, 5, &umr_bitfield_default },
	 { "OTG_H_BLANK", 16, 16, &umr_bitfield_default },
	 { "OTG_H_ACTIVE_DISP", 17, 17, &umr_bitfield_default },
	 { "OTG_H_SYNC_A", 18, 18, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG2_OTG_STATUS_POSITION[] = {
	 { "OTG_VERT_COUNT", 0, 14, &umr_bitfield_default },
	 { "OTG_HORZ_COUNT", 16, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG2_OTG_NOM_VERT_POSITION[] = {
	 { "OTG_VERT_COUNT_NOM", 0, 14, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG2_OTG_STATUS_FRAME_COUNT[] = {
	 { "OTG_FRAME_COUNT", 0, 23, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG2_OTG_STATUS_VF_COUNT[] = {
	 { "OTG_VF_COUNT", 0, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG2_OTG_STATUS_HV_COUNT[] = {
	 { "OTG_HV_COUNT", 0, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG2_OTG_COUNT_CONTROL[] = {
	 { "OTG_HORZ_COUNT_BY2_EN", 0, 0, &umr_bitfield_default },
	 { "OTG_HORZ_REPETITION_COUNT", 1, 4, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG2_OTG_COUNT_RESET[] = {
	 { "OTG_RESET_FRAME_COUNT", 0, 0, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG2_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE[] = {
	 { "OTG_MANUAL_FORCE_VSYNC_NEXT_LINE", 0, 0, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG2_OTG_VERT_SYNC_CONTROL[] = {
	 { "OTG_FORCE_VSYNC_NEXT_LINE_OCCURRED", 0, 0, &umr_bitfield_default },
	 { "OTG_FORCE_VSYNC_NEXT_LINE_CLEAR", 8, 8, &umr_bitfield_default },
	 { "OTG_AUTO_FORCE_VSYNC_MODE", 16, 17, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG2_OTG_STEREO_STATUS[] = {
	 { "OTG_STEREO_CURRENT_EYE", 0, 0, &umr_bitfield_default },
	 { "OTG_STEREO_SYNC_OUTPUT", 8, 8, &umr_bitfield_default },
	 { "OTG_STEREO_SYNC_SELECT", 16, 16, &umr_bitfield_default },
	 { "OTG_STEREO_EYE_FLAG", 20, 20, &umr_bitfield_default },
	 { "OTG_STEREO_FORCE_NEXT_EYE_PENDING", 24, 25, &umr_bitfield_default },
	 { "OTG_CURRENT_3D_STRUCTURE_STATE", 30, 30, &umr_bitfield_default },
	 { "OTG_CURRENT_STEREOSYNC_EN_STATE", 31, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG2_OTG_STEREO_CONTROL[] = {
	 { "OTG_STEREO_SYNC_OUTPUT_LINE_NUM", 0, 14, &umr_bitfield_default },
	 { "OTG_STEREO_SYNC_OUTPUT_POLARITY", 15, 15, &umr_bitfield_default },
	 { "OTG_STEREO_EYE_FLAG_POLARITY", 17, 17, &umr_bitfield_default },
	 { "OTG_DISABLE_STEREOSYNC_OUTPUT_FOR_DP", 18, 18, &umr_bitfield_default },
	 { "OTG_DISABLE_FIELD_NUM", 19, 19, &umr_bitfield_default },
	 { "OTG_DISABLE_V_BLANK_FOR_DP_FIX", 20, 20, &umr_bitfield_default },
	 { "OTG_STEREO_EN", 24, 24, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG2_OTG_SNAPSHOT_STATUS[] = {
	 { "OTG_SNAPSHOT_OCCURRED", 0, 0, &umr_bitfield_default },
	 { "OTG_SNAPSHOT_CLEAR", 1, 1, &umr_bitfield_default },
	 { "OTG_SNAPSHOT_MANUAL_TRIGGER", 2, 2, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG2_OTG_SNAPSHOT_CONTROL[] = {
	 { "OTG_AUTO_SNAPSHOT_TRIG_SEL", 0, 1, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG2_OTG_SNAPSHOT_POSITION[] = {
	 { "OTG_SNAPSHOT_VERT_COUNT", 0, 14, &umr_bitfield_default },
	 { "OTG_SNAPSHOT_HORZ_COUNT", 16, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG2_OTG_SNAPSHOT_FRAME[] = {
	 { "OTG_SNAPSHOT_FRAME_COUNT", 0, 23, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG2_OTG_INTERRUPT_CONTROL[] = {
	 { "OTG_SNAPSHOT_INT_MSK", 0, 0, &umr_bitfield_default },
	 { "OTG_SNAPSHOT_INT_TYPE", 1, 1, &umr_bitfield_default },
	 { "OTG_FORCE_COUNT_NOW_INT_MSK", 8, 8, &umr_bitfield_default },
	 { "OTG_FORCE_COUNT_NOW_INT_TYPE", 9, 9, &umr_bitfield_default },
	 { "OTG_FORCE_VSYNC_NEXT_LINE_INT_MSK", 16, 16, &umr_bitfield_default },
	 { "OTG_FORCE_VSYNC_NEXT_LINE_INT_TYPE", 17, 17, &umr_bitfield_default },
	 { "OTG_TRIGA_INT_MSK", 24, 24, &umr_bitfield_default },
	 { "OTG_TRIGB_INT_MSK", 25, 25, &umr_bitfield_default },
	 { "OTG_TRIGA_INT_TYPE", 26, 26, &umr_bitfield_default },
	 { "OTG_TRIGB_INT_TYPE", 27, 27, &umr_bitfield_default },
	 { "OTG_VSYNC_NOM_INT_MSK", 28, 28, &umr_bitfield_default },
	 { "OTG_VSYNC_NOM_INT_TYPE", 29, 29, &umr_bitfield_default },
	 { "OTG_GSL_VSYNC_GAP_INT_MSK", 30, 30, &umr_bitfield_default },
	 { "OTG_GSL_VSYNC_GAP_INT_TYPE", 31, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG2_OTG_UPDATE_LOCK[] = {
	 { "OTG_UPDATE_LOCK", 0, 0, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG2_OTG_DOUBLE_BUFFER_CONTROL[] = {
	 { "OTG_UPDATE_PENDING", 0, 0, &umr_bitfield_default },
	 { "OTG_H_TIMING_DIV_BY2_DB_UPDATE_PENDING", 2, 2, &umr_bitfield_default },
	 { "OTG_BLANK_DATA_EN_UPDATE_PENDING", 3, 3, &umr_bitfield_default },
	 { "OTG_RANGE_TIMING_DBUF_UPDATE_PENDING", 4, 4, &umr_bitfield_default },
	 { "OTG_TIMING_DB_UPDATE_PENDING", 5, 5, &umr_bitfield_default },
	 { "OTG_3D_CTRL_DB_UPDATE_PENDING", 6, 6, &umr_bitfield_default },
	 { "OTG_3D_STRUCTURE_EN_DB_UPDATE_PENDING", 7, 7, &umr_bitfield_default },
	 { "OTG_UPDATE_INSTANTLY", 8, 8, &umr_bitfield_default },
	 { "OTG_BLANK_DATA_DOUBLE_BUFFER_EN", 16, 16, &umr_bitfield_default },
	 { "OTG_RANGE_TIMING_DBUF_UPDATE_MODE", 24, 25, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG2_OTG_TEST_PATTERN_CONTROL[] = {
	 { "OTG_TEST_PATTERN_EN", 0, 0, &umr_bitfield_default },
	 { "OTG_TEST_PATTERN_MODE", 8, 10, &umr_bitfield_default },
	 { "OTG_TEST_PATTERN_DYNAMIC_RANGE", 16, 16, &umr_bitfield_default },
	 { "OTG_TEST_PATTERN_COLOR_FORMAT", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG2_OTG_TEST_PATTERN_PARAMETERS[] = {
	 { "OTG_TEST_PATTERN_INC0", 0, 3, &umr_bitfield_default },
	 { "OTG_TEST_PATTERN_INC1", 4, 7, &umr_bitfield_default },
	 { "OTG_TEST_PATTERN_VRES", 8, 11, &umr_bitfield_default },
	 { "OTG_TEST_PATTERN_HRES", 12, 15, &umr_bitfield_default },
	 { "OTG_TEST_PATTERN_RAMP0_OFFSET", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG2_OTG_TEST_PATTERN_COLOR[] = {
	 { "OTG_TEST_PATTERN_DATA", 0, 15, &umr_bitfield_default },
	 { "OTG_TEST_PATTERN_MASK", 16, 21, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG2_OTG_MASTER_EN[] = {
	 { "OTG_MASTER_EN", 0, 0, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG2_OTG_BLANK_DATA_COLOR[] = {
	 { "OTG_BLANK_DATA_COLOR_BLUE_CB", 0, 9, &umr_bitfield_default },
	 { "OTG_BLANK_DATA_COLOR_GREEN_Y", 10, 19, &umr_bitfield_default },
	 { "OTG_BLANK_DATA_COLOR_RED_CR", 20, 29, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG2_OTG_BLANK_DATA_COLOR_EXT[] = {
	 { "OTG_BLANK_DATA_COLOR_BLUE_CB_EXT", 0, 5, &umr_bitfield_default },
	 { "OTG_BLANK_DATA_COLOR_GREEN_Y_EXT", 8, 13, &umr_bitfield_default },
	 { "OTG_BLANK_DATA_COLOR_RED_CR_EXT", 16, 21, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG2_OTG_BLACK_COLOR[] = {
	 { "OTG_BLACK_COLOR_B_CB", 0, 9, &umr_bitfield_default },
	 { "OTG_BLACK_COLOR_G_Y", 10, 19, &umr_bitfield_default },
	 { "OTG_BLACK_COLOR_R_CR", 20, 29, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG2_OTG_BLACK_COLOR_EXT[] = {
	 { "OTG_BLACK_COLOR_B_CB_EXT", 0, 5, &umr_bitfield_default },
	 { "OTG_BLACK_COLOR_G_Y_EXT", 8, 13, &umr_bitfield_default },
	 { "OTG_BLACK_COLOR_R_CR_EXT", 16, 21, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG2_OTG_VERTICAL_INTERRUPT0_POSITION[] = {
	 { "OTG_VERTICAL_INTERRUPT0_LINE_START", 0, 14, &umr_bitfield_default },
	 { "OTG_VERTICAL_INTERRUPT0_LINE_END", 16, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG2_OTG_VERTICAL_INTERRUPT0_CONTROL[] = {
	 { "OTG_VERTICAL_INTERRUPT0_OUTPUT_POLARITY", 4, 4, &umr_bitfield_default },
	 { "OTG_VERTICAL_INTERRUPT0_INT_ENABLE", 8, 8, &umr_bitfield_default },
	 { "OTG_VERTICAL_INTERRUPT0_STATUS", 12, 12, &umr_bitfield_default },
	 { "OTG_VERTICAL_INTERRUPT0_INT_STATUS", 16, 16, &umr_bitfield_default },
	 { "OTG_VERTICAL_INTERRUPT0_CLEAR", 20, 20, &umr_bitfield_default },
	 { "OTG_VERTICAL_INTERRUPT0_INT_TYPE", 24, 24, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG2_OTG_VERTICAL_INTERRUPT1_POSITION[] = {
	 { "OTG_VERTICAL_INTERRUPT1_LINE_START", 0, 14, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG2_OTG_VERTICAL_INTERRUPT1_CONTROL[] = {
	 { "OTG_VERTICAL_INTERRUPT1_INT_ENABLE", 8, 8, &umr_bitfield_default },
	 { "OTG_VERTICAL_INTERRUPT1_STATUS", 12, 12, &umr_bitfield_default },
	 { "OTG_VERTICAL_INTERRUPT1_INT_STATUS", 16, 16, &umr_bitfield_default },
	 { "OTG_VERTICAL_INTERRUPT1_CLEAR", 20, 20, &umr_bitfield_default },
	 { "OTG_VERTICAL_INTERRUPT1_INT_TYPE", 24, 24, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG2_OTG_VERTICAL_INTERRUPT2_POSITION[] = {
	 { "OTG_VERTICAL_INTERRUPT2_LINE_START", 0, 14, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG2_OTG_VERTICAL_INTERRUPT2_CONTROL[] = {
	 { "OTG_VERTICAL_INTERRUPT2_INT_ENABLE", 8, 8, &umr_bitfield_default },
	 { "OTG_VERTICAL_INTERRUPT2_STATUS", 12, 12, &umr_bitfield_default },
	 { "OTG_VERTICAL_INTERRUPT2_INT_STATUS", 16, 16, &umr_bitfield_default },
	 { "OTG_VERTICAL_INTERRUPT2_CLEAR", 20, 20, &umr_bitfield_default },
	 { "OTG_VERTICAL_INTERRUPT2_INT_TYPE", 24, 24, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG2_OTG_CRC_CNTL[] = {
	 { "OTG_CRC_EN", 0, 0, &umr_bitfield_default },
	 { "OTG_CRC_DUAL_LINK_EN", 1, 1, &umr_bitfield_default },
	 { "OTG_CRC_DUAL_LINK_MODE", 2, 2, &umr_bitfield_default },
	 { "OTG_CRC_BLANK_ONLY", 3, 3, &umr_bitfield_default },
	 { "OTG_CRC_CONT_EN", 4, 4, &umr_bitfield_default },
	 { "OTG_CRC_CAPTURE_START_SEL", 5, 6, &umr_bitfield_default },
	 { "OTG_CRC_STEREO_MODE", 8, 9, &umr_bitfield_default },
	 { "OTG_CRC_INTERLACE_MODE", 12, 13, &umr_bitfield_default },
	 { "OTG_CRC_MULTI_STREAM_MODE", 16, 18, &umr_bitfield_default },
	 { "OTG_CRC_USE_NEW_AND_REPEATED_PIXELS", 19, 19, &umr_bitfield_default },
	 { "OTG_CRC0_SELECT", 20, 22, &umr_bitfield_default },
	 { "OTG_CRC1_SELECT", 24, 26, &umr_bitfield_default },
	 { "OTG_ONE_SHOT_CRC0_PENDING", 28, 28, &umr_bitfield_default },
	 { "OTG_ONE_SHOT_CRC1_PENDING", 29, 29, &umr_bitfield_default },
	 { "OTG_ONE_SHOT_CRC2_PENDING", 30, 30, &umr_bitfield_default },
	 { "OTG_ONE_SHOT_CRC3_PENDING", 31, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG2_OTG_CRC0_WINDOWA_X_CONTROL[] = {
	 { "OTG_CRC0_WINDOWA_X_START", 0, 14, &umr_bitfield_default },
	 { "OTG_CRC0_WINDOWA_X_END", 16, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG2_OTG_CRC0_WINDOWA_Y_CONTROL[] = {
	 { "OTG_CRC0_WINDOWA_Y_START", 0, 14, &umr_bitfield_default },
	 { "OTG_CRC0_WINDOWA_Y_END", 16, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG2_OTG_CRC0_WINDOWB_X_CONTROL[] = {
	 { "OTG_CRC0_WINDOWB_X_START", 0, 14, &umr_bitfield_default },
	 { "OTG_CRC0_WINDOWB_X_END", 16, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG2_OTG_CRC0_WINDOWB_Y_CONTROL[] = {
	 { "OTG_CRC0_WINDOWB_Y_START", 0, 14, &umr_bitfield_default },
	 { "OTG_CRC0_WINDOWB_Y_END", 16, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG2_OTG_CRC0_DATA_RG[] = {
	 { "CRC0_R_CR", 0, 15, &umr_bitfield_default },
	 { "CRC0_G_Y", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG2_OTG_CRC0_DATA_B[] = {
	 { "CRC0_B_CB", 0, 15, &umr_bitfield_default },
	 { "CRC0_C", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG2_OTG_CRC1_WINDOWA_X_CONTROL[] = {
	 { "OTG_CRC1_WINDOWA_X_START", 0, 14, &umr_bitfield_default },
	 { "OTG_CRC1_WINDOWA_X_END", 16, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG2_OTG_CRC1_WINDOWA_Y_CONTROL[] = {
	 { "OTG_CRC1_WINDOWA_Y_START", 0, 14, &umr_bitfield_default },
	 { "OTG_CRC1_WINDOWA_Y_END", 16, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG2_OTG_CRC1_WINDOWB_X_CONTROL[] = {
	 { "OTG_CRC1_WINDOWB_X_START", 0, 14, &umr_bitfield_default },
	 { "OTG_CRC1_WINDOWB_X_END", 16, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG2_OTG_CRC1_WINDOWB_Y_CONTROL[] = {
	 { "OTG_CRC1_WINDOWB_Y_START", 0, 14, &umr_bitfield_default },
	 { "OTG_CRC1_WINDOWB_Y_END", 16, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG2_OTG_CRC1_DATA_RG[] = {
	 { "CRC1_R_CR", 0, 15, &umr_bitfield_default },
	 { "CRC1_G_Y", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG2_OTG_CRC1_DATA_B[] = {
	 { "CRC1_B_CB", 0, 15, &umr_bitfield_default },
	 { "CRC1_C", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG2_OTG_CRC2_DATA_RG[] = {
	 { "CRC2_R_CR", 0, 15, &umr_bitfield_default },
	 { "CRC2_G_Y", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG2_OTG_CRC2_DATA_B[] = {
	 { "CRC2_B_CB", 0, 15, &umr_bitfield_default },
	 { "CRC2_C", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG2_OTG_CRC3_DATA_RG[] = {
	 { "CRC3_R_CR", 0, 15, &umr_bitfield_default },
	 { "CRC3_G_Y", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG2_OTG_CRC3_DATA_B[] = {
	 { "CRC3_B_CB", 0, 15, &umr_bitfield_default },
	 { "CRC3_C", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG2_OTG_CRC_SIG_RED_GREEN_MASK[] = {
	 { "OTG_CRC_SIG_RED_MASK", 0, 15, &umr_bitfield_default },
	 { "OTG_CRC_SIG_GREEN_MASK", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG2_OTG_CRC_SIG_BLUE_CONTROL_MASK[] = {
	 { "OTG_CRC_SIG_BLUE_MASK", 0, 15, &umr_bitfield_default },
	 { "OTG_CRC_SIG_CONTROL_MASK", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG2_OTG_STATIC_SCREEN_CONTROL[] = {
	 { "OTG_STATIC_SCREEN_EVENT_MASK", 0, 15, &umr_bitfield_default },
	 { "OTG_STATIC_SCREEN_FRAME_COUNT", 16, 23, &umr_bitfield_default },
	 { "OTG_CPU_SS_INT_ENABLE", 24, 24, &umr_bitfield_default },
	 { "OTG_SS_STATUS", 25, 25, &umr_bitfield_default },
	 { "OTG_CPU_SS_INT_STATUS", 26, 26, &umr_bitfield_default },
	 { "OTG_CPU_SS_INT_CLEAR", 27, 27, &umr_bitfield_default },
	 { "OTG_CPU_SS_INT_TYPE", 28, 28, &umr_bitfield_default },
	 { "OTG_STATIC_SCREEN_OVERRIDE", 30, 30, &umr_bitfield_default },
	 { "OTG_STATIC_SCREEN_OVERRIDE_VALUE", 31, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG2_OTG_3D_STRUCTURE_CONTROL[] = {
	 { "OTG_3D_STRUCTURE_EN", 0, 0, &umr_bitfield_default },
	 { "OTG_3D_STRUCTURE_V_UPDATE_MODE", 8, 9, &umr_bitfield_default },
	 { "OTG_3D_STRUCTURE_STEREO_SEL_OVR", 12, 12, &umr_bitfield_default },
	 { "OTG_3D_STRUCTURE_F_COUNT_RESET", 16, 16, &umr_bitfield_default },
	 { "OTG_3D_STRUCTURE_F_COUNT_RESET_PENDING", 17, 17, &umr_bitfield_default },
	 { "OTG_3D_STRUCTURE_F_COUNT", 18, 19, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG2_OTG_GSL_VSYNC_GAP[] = {
	 { "OTG_GSL_VSYNC_GAP_LIMIT", 0, 7, &umr_bitfield_default },
	 { "OTG_GSL_VSYNC_GAP_DELAY", 8, 15, &umr_bitfield_default },
	 { "OTG_GSL_VSYNC_GAP_SOURCE_SEL", 16, 16, &umr_bitfield_default },
	 { "OTG_GSL_VSYNC_GAP_MODE", 17, 18, &umr_bitfield_default },
	 { "OTG_GSL_VSYNC_GAP_CLEAR", 19, 19, &umr_bitfield_default },
	 { "OTG_GSL_VSYNC_GAP_OCCURRED", 20, 20, &umr_bitfield_default },
	 { "OTG_GSL_VSYNC_GAP_MASTER_FASTER", 23, 23, &umr_bitfield_default },
	 { "OTG_GSL_VSYNC_GAP", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG2_OTG_MASTER_UPDATE_MODE[] = {
	 { "MASTER_UPDATE_INTERLACED_MODE", 0, 1, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG2_OTG_CLOCK_CONTROL[] = {
	 { "OTG_CLOCK_EN", 0, 0, &umr_bitfield_default },
	 { "OTG_CLOCK_GATE_DIS", 1, 1, &umr_bitfield_default },
	 { "OTG_SOFT_RESET", 4, 4, &umr_bitfield_default },
	 { "OTG_CLOCK_ON", 8, 8, &umr_bitfield_default },
	 { "OTG_BUSY", 16, 16, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG2_OTG_VSTARTUP_PARAM[] = {
	 { "VSTARTUP_START", 0, 9, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG2_OTG_VUPDATE_PARAM[] = {
	 { "VUPDATE_OFFSET", 0, 15, &umr_bitfield_default },
	 { "VUPDATE_WIDTH", 16, 25, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG2_OTG_VREADY_PARAM[] = {
	 { "VREADY_OFFSET", 0, 15, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG2_OTG_GLOBAL_SYNC_STATUS[] = {
	 { "VSTARTUP_INT_EN", 0, 0, &umr_bitfield_default },
	 { "VSTARTUP_INT_TYPE", 1, 1, &umr_bitfield_default },
	 { "VSTARTUP_EVENT_OCCURRED", 2, 2, &umr_bitfield_default },
	 { "VSTARTUP_INT_STATUS", 3, 3, &umr_bitfield_default },
	 { "VSTARTUP_EVENT_CLEAR", 4, 4, &umr_bitfield_default },
	 { "VUPDATE_INT_EN", 5, 5, &umr_bitfield_default },
	 { "VUPDATE_INT_TYPE", 6, 6, &umr_bitfield_default },
	 { "VUPDATE_INT_POSITION_SEL", 7, 7, &umr_bitfield_default },
	 { "VUPDATE_EVENT_OCCURRED", 8, 8, &umr_bitfield_default },
	 { "VUPDATE_INT_STATUS", 9, 9, &umr_bitfield_default },
	 { "VUPDATE_EVENT_CLEAR", 10, 10, &umr_bitfield_default },
	 { "VUPDATE_STATUS", 11, 11, &umr_bitfield_default },
	 { "VUPDATE_NO_LOCK_INT_EN", 12, 12, &umr_bitfield_default },
	 { "VUPDATE_NO_LOCK_INT_TYPE", 13, 13, &umr_bitfield_default },
	 { "VUPDATE_NO_LOCK_EVENT_OCCURRED", 14, 14, &umr_bitfield_default },
	 { "VUPDATE_NO_LOCK_INT_STATUS", 15, 15, &umr_bitfield_default },
	 { "VUPDATE_NO_LOCK_EVENT_CLEAR", 16, 16, &umr_bitfield_default },
	 { "VUPDATE_NO_LOCK_STATUS", 17, 17, &umr_bitfield_default },
	 { "VREADY_INT_EN", 18, 18, &umr_bitfield_default },
	 { "VREADY_INT_TYPE", 19, 19, &umr_bitfield_default },
	 { "VREADY_EVENT_OCCURRED", 20, 20, &umr_bitfield_default },
	 { "VREADY_INT_STATUS", 21, 21, &umr_bitfield_default },
	 { "VREADY_EVENT_CLEAR", 22, 22, &umr_bitfield_default },
	 { "STEREO_SELECT_STATUS", 24, 24, &umr_bitfield_default },
	 { "FIELD_NUMBER_STATUS", 25, 25, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG2_OTG_MASTER_UPDATE_LOCK[] = {
	 { "OTG_MASTER_UPDATE_LOCK", 0, 0, &umr_bitfield_default },
	 { "UPDATE_LOCK_STATUS", 8, 8, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG2_OTG_GSL_CONTROL[] = {
	 { "OTG_GSL0_EN", 0, 0, &umr_bitfield_default },
	 { "OTG_GSL1_EN", 1, 1, &umr_bitfield_default },
	 { "OTG_GSL2_EN", 2, 2, &umr_bitfield_default },
	 { "OTG_GSL_MASTER_EN", 3, 3, &umr_bitfield_default },
	 { "OTG_GSL_FORCE_DELAY", 16, 20, &umr_bitfield_default },
	 { "OTG_GSL_CHECK_ALL_FIELDS", 28, 28, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG2_OTG_GSL_WINDOW_X[] = {
	 { "OTG_GSL_WINDOW_START_X", 0, 14, &umr_bitfield_default },
	 { "OTG_GSL_WINDOW_END_X", 16, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG2_OTG_GSL_WINDOW_Y[] = {
	 { "OTG_GSL_WINDOW_START_Y", 0, 14, &umr_bitfield_default },
	 { "OTG_GSL_WINDOW_END_Y", 16, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG2_OTG_VUPDATE_KEEPOUT[] = {
	 { "MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_START_OFFSET", 0, 15, &umr_bitfield_default },
	 { "MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_END_OFFSET", 16, 25, &umr_bitfield_default },
	 { "OTG_MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_EN", 31, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG2_OTG_GLOBAL_CONTROL0[] = {
	 { "OTG_MASTER_UPDATE_LOCK_HTOTAL_KEEPOUT", 0, 7, &umr_bitfield_default },
	 { "OTG_MASTER_UPDATE_LOCK_HTOTAL_KEEPOUT_EN", 8, 8, &umr_bitfield_default },
	 { "OTG_MASTER_UPDATE_LOCK_SEL", 25, 27, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG2_OTG_GLOBAL_CONTROL1[] = {
	 { "MASTER_UPDATE_LOCK_DB_X", 0, 14, &umr_bitfield_default },
	 { "MASTER_UPDATE_LOCK_DB_Y", 16, 30, &umr_bitfield_default },
	 { "MASTER_UPDATE_LOCK_DB_EN", 31, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG2_OTG_GLOBAL_CONTROL2[] = {
	 { "DIG_UPDATE_LOCATION", 0, 9, &umr_bitfield_default },
	 { "GLOBAL_UPDATE_LOCK_EN", 10, 10, &umr_bitfield_default },
	 { "MANUAL_FLOW_CONTROL_SEL", 16, 18, &umr_bitfield_default },
	 { "DCCG_VUPDATE_MODE", 31, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG2_OTG_GLOBAL_CONTROL3[] = {
	 { "MASTER_UPDATE_LOCK_DB_FIELD", 0, 1, &umr_bitfield_default },
	 { "MASTER_UPDATE_LOCK_DB_STEREO_SEL", 4, 5, &umr_bitfield_default },
	 { "MASTER_UPDATE_LOCK_DB_FIELD_STEREO_FLAG_SEL", 8, 8, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG2_OTG_TRIG_MANUAL_CONTROL[] = {
	 { "TRIG_MANUAL_CONTROL", 0, 0, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG2_OTG_MANUAL_FLOW_CONTROL[] = {
	 { "MANUAL_FLOW_CONTROL", 0, 0, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG2_OTG_RANGE_TIMING_INT_STATUS[] = {
	 { "OTG_RANGE_TIMING_UPDATE_OCCURRED", 0, 0, &umr_bitfield_default },
	 { "OTG_RANGE_TIMING_UPDATE_OCCURRED_INT", 4, 4, &umr_bitfield_default },
	 { "OTG_RANGE_TIMING_UPDATE_OCCURRED_CLEAR", 8, 8, &umr_bitfield_default },
	 { "OTG_RANGE_TIMING_UPDATE_OCCURRED_INT_MSK", 12, 12, &umr_bitfield_default },
	 { "OTG_RANGE_TIMING_UPDATE_OCCURRED_INT_TYPE", 16, 16, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG2_OTG_DRR_CONTROL[] = {
	 { "OTG_DRR_AVERAGE_FRAME", 0, 2, &umr_bitfield_default },
	 { "OTG_V_TOTAL_LAST_USED_BY_DRR", 16, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG2_OTG_REQUEST_CONTROL[] = {
	 { "OTG_REQUEST_MODE_FOR_H_DUPLICATE", 0, 0, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG2_OTG_SPARE_REGISTER[] = {
	 { "OTG_SPARE_REG", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG3_OTG_H_TOTAL[] = {
	 { "OTG_H_TOTAL", 0, 14, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG3_OTG_H_BLANK_START_END[] = {
	 { "OTG_H_BLANK_START", 0, 14, &umr_bitfield_default },
	 { "OTG_H_BLANK_END", 16, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG3_OTG_H_SYNC_A[] = {
	 { "OTG_H_SYNC_A_START", 0, 14, &umr_bitfield_default },
	 { "OTG_H_SYNC_A_END", 16, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG3_OTG_H_SYNC_A_CNTL[] = {
	 { "OTG_H_SYNC_A_POL", 0, 0, &umr_bitfield_default },
	 { "OTG_COMP_SYNC_A_EN", 16, 16, &umr_bitfield_default },
	 { "OTG_H_SYNC_A_CUTOFF", 17, 17, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG3_OTG_H_TIMING_CNTL[] = {
	 { "OTG_H_TIMING_DIV_BY2", 0, 0, &umr_bitfield_default },
	 { "OTG_H_TIMING_DIV_BY2_UPDATE_MODE", 8, 8, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG3_OTG_V_TOTAL[] = {
	 { "OTG_V_TOTAL", 0, 14, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG3_OTG_V_TOTAL_MIN[] = {
	 { "OTG_V_TOTAL_MIN", 0, 14, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG3_OTG_V_TOTAL_MAX[] = {
	 { "OTG_V_TOTAL_MAX", 0, 14, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG3_OTG_V_TOTAL_MID[] = {
	 { "OTG_V_TOTAL_MID", 0, 14, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG3_OTG_V_TOTAL_CONTROL[] = {
	 { "OTG_V_TOTAL_MIN_SEL", 0, 0, &umr_bitfield_default },
	 { "OTG_V_TOTAL_MAX_SEL", 1, 1, &umr_bitfield_default },
	 { "OTG_VTOTAL_MID_REPLACING_MAX_EN", 2, 2, &umr_bitfield_default },
	 { "OTG_VTOTAL_MID_REPLACING_MIN_EN", 3, 3, &umr_bitfield_default },
	 { "OTG_FORCE_LOCK_ON_EVENT", 4, 4, &umr_bitfield_default },
	 { "OTG_SET_V_TOTAL_MIN_MASK_EN", 7, 7, &umr_bitfield_default },
	 { "OTG_VTOTAL_MID_FRAME_NUM", 8, 15, &umr_bitfield_default },
	 { "OTG_SET_V_TOTAL_MIN_MASK", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG3_OTG_V_TOTAL_INT_STATUS[] = {
	 { "OTG_SET_V_TOTAL_MIN_EVENT_OCCURED", 0, 0, &umr_bitfield_default },
	 { "OTG_SET_V_TOTAL_MIN_EVENT_OCCURED_INT", 4, 4, &umr_bitfield_default },
	 { "OTG_SET_V_TOTAL_MIN_EVENT_OCCURED_ACK", 8, 8, &umr_bitfield_default },
	 { "OTG_SET_V_TOTAL_MIN_EVENT_OCCURED_MSK", 12, 12, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG3_OTG_VSYNC_NOM_INT_STATUS[] = {
	 { "OTG_VSYNC_NOM", 0, 0, &umr_bitfield_default },
	 { "OTG_VSYNC_NOM_INT_CLEAR", 4, 4, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG3_OTG_V_BLANK_START_END[] = {
	 { "OTG_V_BLANK_START", 0, 14, &umr_bitfield_default },
	 { "OTG_V_BLANK_END", 16, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG3_OTG_V_SYNC_A[] = {
	 { "OTG_V_SYNC_A_START", 0, 14, &umr_bitfield_default },
	 { "OTG_V_SYNC_A_END", 16, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG3_OTG_V_SYNC_A_CNTL[] = {
	 { "OTG_V_SYNC_A_POL", 0, 0, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG3_OTG_TRIGA_CNTL[] = {
	 { "OTG_TRIGA_SOURCE_SELECT", 0, 4, &umr_bitfield_default },
	 { "OTG_TRIGA_SOURCE_PIPE_SELECT", 5, 7, &umr_bitfield_default },
	 { "OTG_TRIGA_POLARITY_SELECT", 8, 10, &umr_bitfield_default },
	 { "OTG_TRIGA_RESYNC_BYPASS_EN", 11, 11, &umr_bitfield_default },
	 { "OTG_TRIGA_INPUT_STATUS", 12, 12, &umr_bitfield_default },
	 { "OTG_TRIGA_POLARITY_STATUS", 13, 13, &umr_bitfield_default },
	 { "OTG_TRIGA_OCCURRED", 14, 14, &umr_bitfield_default },
	 { "OTG_TRIGA_RISING_EDGE_DETECT_CNTL", 16, 17, &umr_bitfield_default },
	 { "OTG_TRIGA_FALLING_EDGE_DETECT_CNTL", 18, 19, &umr_bitfield_default },
	 { "OTG_TRIGA_FREQUENCY_SELECT", 20, 21, &umr_bitfield_default },
	 { "OTG_TRIGA_DELAY", 24, 28, &umr_bitfield_default },
	 { "OTG_TRIGA_CLEAR", 31, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG3_OTG_TRIGA_MANUAL_TRIG[] = {
	 { "OTG_TRIGA_MANUAL_TRIG", 0, 0, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG3_OTG_TRIGB_CNTL[] = {
	 { "OTG_TRIGB_SOURCE_SELECT", 0, 4, &umr_bitfield_default },
	 { "OTG_TRIGB_SOURCE_PIPE_SELECT", 5, 7, &umr_bitfield_default },
	 { "OTG_TRIGB_POLARITY_SELECT", 8, 10, &umr_bitfield_default },
	 { "OTG_TRIGB_RESYNC_BYPASS_EN", 11, 11, &umr_bitfield_default },
	 { "OTG_TRIGB_INPUT_STATUS", 12, 12, &umr_bitfield_default },
	 { "OTG_TRIGB_POLARITY_STATUS", 13, 13, &umr_bitfield_default },
	 { "OTG_TRIGB_OCCURRED", 14, 14, &umr_bitfield_default },
	 { "OTG_TRIGB_RISING_EDGE_DETECT_CNTL", 16, 17, &umr_bitfield_default },
	 { "OTG_TRIGB_FALLING_EDGE_DETECT_CNTL", 18, 19, &umr_bitfield_default },
	 { "OTG_TRIGB_FREQUENCY_SELECT", 20, 21, &umr_bitfield_default },
	 { "OTG_TRIGB_DELAY", 24, 28, &umr_bitfield_default },
	 { "OTG_TRIGB_CLEAR", 31, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG3_OTG_TRIGB_MANUAL_TRIG[] = {
	 { "OTG_TRIGB_MANUAL_TRIG", 0, 0, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG3_OTG_FORCE_COUNT_NOW_CNTL[] = {
	 { "OTG_FORCE_COUNT_NOW_MODE", 0, 1, &umr_bitfield_default },
	 { "OTG_FORCE_COUNT_NOW_CHECK", 4, 4, &umr_bitfield_default },
	 { "OTG_FORCE_COUNT_NOW_TRIG_SEL", 8, 8, &umr_bitfield_default },
	 { "OTG_FORCE_COUNT_NOW_OCCURRED", 16, 16, &umr_bitfield_default },
	 { "OTG_FORCE_COUNT_NOW_CLEAR", 24, 24, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG3_OTG_FLOW_CONTROL[] = {
	 { "OTG_FLOW_CONTROL_SOURCE_SELECT", 0, 4, &umr_bitfield_default },
	 { "OTG_FLOW_CONTROL_POLARITY", 8, 8, &umr_bitfield_default },
	 { "OTG_FLOW_CONTROL_GRANULARITY", 16, 16, &umr_bitfield_default },
	 { "OTG_FLOW_CONTROL_INPUT_STATUS", 24, 24, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG3_OTG_STEREO_FORCE_NEXT_EYE[] = {
	 { "OTG_STEREO_FORCE_NEXT_EYE", 0, 1, &umr_bitfield_default },
	 { "OTG_AVSYNC_FRAME_COUNTER", 8, 15, &umr_bitfield_default },
	 { "OTG_AVSYNC_LINE_COUNTER", 16, 28, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG3_OTG_AVSYNC_COUNTER[] = {
	 { "OTG_AVSYNC_COUNTER", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG3_OTG_CONTROL[] = {
	 { "OTG_MASTER_EN", 0, 0, &umr_bitfield_default },
	 { "OTG_DISABLE_POINT_CNTL", 8, 9, &umr_bitfield_default },
	 { "OTG_START_POINT_CNTL", 12, 12, &umr_bitfield_default },
	 { "OTG_FIELD_NUMBER_CNTL", 13, 13, &umr_bitfield_default },
	 { "OTG_FIELD_NUMBER_POLARITY", 14, 14, &umr_bitfield_default },
	 { "OTG_CURRENT_MASTER_EN_STATE", 16, 16, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG3_OTG_BLANK_CONTROL[] = {
	 { "OTG_CURRENT_BLANK_STATE", 0, 0, &umr_bitfield_default },
	 { "OTG_BLANK_DATA_EN", 8, 8, &umr_bitfield_default },
	 { "OTG_BLANK_DE_MODE", 16, 16, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG3_OTG_PIPE_ABORT_CONTROL[] = {
	 { "OTG_PIPE_ABORT", 0, 0, &umr_bitfield_default },
	 { "OTG_PIPE_ABORT_DONE", 8, 8, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG3_OTG_INTERLACE_CONTROL[] = {
	 { "OTG_INTERLACE_ENABLE", 0, 0, &umr_bitfield_default },
	 { "OTG_INTERLACE_FORCE_NEXT_FIELD", 16, 17, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG3_OTG_INTERLACE_STATUS[] = {
	 { "OTG_INTERLACE_CURRENT_FIELD", 0, 0, &umr_bitfield_default },
	 { "OTG_INTERLACE_NEXT_FIELD", 1, 1, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG3_OTG_FIELD_INDICATION_CONTROL[] = {
	 { "OTG_FIELD_INDICATION_OUTPUT_POLARITY", 0, 0, &umr_bitfield_default },
	 { "OTG_FIELD_ALIGNMENT", 1, 1, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG3_OTG_PIXEL_DATA_READBACK0[] = {
	 { "OTG_PIXEL_DATA_BLUE_CB", 0, 15, &umr_bitfield_default },
	 { "OTG_PIXEL_DATA_GREEN_Y", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG3_OTG_PIXEL_DATA_READBACK1[] = {
	 { "OTG_PIXEL_DATA_RED_CR", 0, 15, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG3_OTG_STATUS[] = {
	 { "OTG_V_BLANK", 0, 0, &umr_bitfield_default },
	 { "OTG_V_ACTIVE_DISP", 1, 1, &umr_bitfield_default },
	 { "OTG_V_SYNC_A", 2, 2, &umr_bitfield_default },
	 { "OTG_V_UPDATE", 3, 3, &umr_bitfield_default },
	 { "OTG_V_BLANK_3D_STRUCTURE", 5, 5, &umr_bitfield_default },
	 { "OTG_H_BLANK", 16, 16, &umr_bitfield_default },
	 { "OTG_H_ACTIVE_DISP", 17, 17, &umr_bitfield_default },
	 { "OTG_H_SYNC_A", 18, 18, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG3_OTG_STATUS_POSITION[] = {
	 { "OTG_VERT_COUNT", 0, 14, &umr_bitfield_default },
	 { "OTG_HORZ_COUNT", 16, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG3_OTG_NOM_VERT_POSITION[] = {
	 { "OTG_VERT_COUNT_NOM", 0, 14, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG3_OTG_STATUS_FRAME_COUNT[] = {
	 { "OTG_FRAME_COUNT", 0, 23, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG3_OTG_STATUS_VF_COUNT[] = {
	 { "OTG_VF_COUNT", 0, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG3_OTG_STATUS_HV_COUNT[] = {
	 { "OTG_HV_COUNT", 0, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG3_OTG_COUNT_CONTROL[] = {
	 { "OTG_HORZ_COUNT_BY2_EN", 0, 0, &umr_bitfield_default },
	 { "OTG_HORZ_REPETITION_COUNT", 1, 4, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG3_OTG_COUNT_RESET[] = {
	 { "OTG_RESET_FRAME_COUNT", 0, 0, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG3_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE[] = {
	 { "OTG_MANUAL_FORCE_VSYNC_NEXT_LINE", 0, 0, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG3_OTG_VERT_SYNC_CONTROL[] = {
	 { "OTG_FORCE_VSYNC_NEXT_LINE_OCCURRED", 0, 0, &umr_bitfield_default },
	 { "OTG_FORCE_VSYNC_NEXT_LINE_CLEAR", 8, 8, &umr_bitfield_default },
	 { "OTG_AUTO_FORCE_VSYNC_MODE", 16, 17, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG3_OTG_STEREO_STATUS[] = {
	 { "OTG_STEREO_CURRENT_EYE", 0, 0, &umr_bitfield_default },
	 { "OTG_STEREO_SYNC_OUTPUT", 8, 8, &umr_bitfield_default },
	 { "OTG_STEREO_SYNC_SELECT", 16, 16, &umr_bitfield_default },
	 { "OTG_STEREO_EYE_FLAG", 20, 20, &umr_bitfield_default },
	 { "OTG_STEREO_FORCE_NEXT_EYE_PENDING", 24, 25, &umr_bitfield_default },
	 { "OTG_CURRENT_3D_STRUCTURE_STATE", 30, 30, &umr_bitfield_default },
	 { "OTG_CURRENT_STEREOSYNC_EN_STATE", 31, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG3_OTG_STEREO_CONTROL[] = {
	 { "OTG_STEREO_SYNC_OUTPUT_LINE_NUM", 0, 14, &umr_bitfield_default },
	 { "OTG_STEREO_SYNC_OUTPUT_POLARITY", 15, 15, &umr_bitfield_default },
	 { "OTG_STEREO_EYE_FLAG_POLARITY", 17, 17, &umr_bitfield_default },
	 { "OTG_DISABLE_STEREOSYNC_OUTPUT_FOR_DP", 18, 18, &umr_bitfield_default },
	 { "OTG_DISABLE_FIELD_NUM", 19, 19, &umr_bitfield_default },
	 { "OTG_DISABLE_V_BLANK_FOR_DP_FIX", 20, 20, &umr_bitfield_default },
	 { "OTG_STEREO_EN", 24, 24, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG3_OTG_SNAPSHOT_STATUS[] = {
	 { "OTG_SNAPSHOT_OCCURRED", 0, 0, &umr_bitfield_default },
	 { "OTG_SNAPSHOT_CLEAR", 1, 1, &umr_bitfield_default },
	 { "OTG_SNAPSHOT_MANUAL_TRIGGER", 2, 2, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG3_OTG_SNAPSHOT_CONTROL[] = {
	 { "OTG_AUTO_SNAPSHOT_TRIG_SEL", 0, 1, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG3_OTG_SNAPSHOT_POSITION[] = {
	 { "OTG_SNAPSHOT_VERT_COUNT", 0, 14, &umr_bitfield_default },
	 { "OTG_SNAPSHOT_HORZ_COUNT", 16, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG3_OTG_SNAPSHOT_FRAME[] = {
	 { "OTG_SNAPSHOT_FRAME_COUNT", 0, 23, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG3_OTG_INTERRUPT_CONTROL[] = {
	 { "OTG_SNAPSHOT_INT_MSK", 0, 0, &umr_bitfield_default },
	 { "OTG_SNAPSHOT_INT_TYPE", 1, 1, &umr_bitfield_default },
	 { "OTG_FORCE_COUNT_NOW_INT_MSK", 8, 8, &umr_bitfield_default },
	 { "OTG_FORCE_COUNT_NOW_INT_TYPE", 9, 9, &umr_bitfield_default },
	 { "OTG_FORCE_VSYNC_NEXT_LINE_INT_MSK", 16, 16, &umr_bitfield_default },
	 { "OTG_FORCE_VSYNC_NEXT_LINE_INT_TYPE", 17, 17, &umr_bitfield_default },
	 { "OTG_TRIGA_INT_MSK", 24, 24, &umr_bitfield_default },
	 { "OTG_TRIGB_INT_MSK", 25, 25, &umr_bitfield_default },
	 { "OTG_TRIGA_INT_TYPE", 26, 26, &umr_bitfield_default },
	 { "OTG_TRIGB_INT_TYPE", 27, 27, &umr_bitfield_default },
	 { "OTG_VSYNC_NOM_INT_MSK", 28, 28, &umr_bitfield_default },
	 { "OTG_VSYNC_NOM_INT_TYPE", 29, 29, &umr_bitfield_default },
	 { "OTG_GSL_VSYNC_GAP_INT_MSK", 30, 30, &umr_bitfield_default },
	 { "OTG_GSL_VSYNC_GAP_INT_TYPE", 31, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG3_OTG_UPDATE_LOCK[] = {
	 { "OTG_UPDATE_LOCK", 0, 0, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG3_OTG_DOUBLE_BUFFER_CONTROL[] = {
	 { "OTG_UPDATE_PENDING", 0, 0, &umr_bitfield_default },
	 { "OTG_H_TIMING_DIV_BY2_DB_UPDATE_PENDING", 2, 2, &umr_bitfield_default },
	 { "OTG_BLANK_DATA_EN_UPDATE_PENDING", 3, 3, &umr_bitfield_default },
	 { "OTG_RANGE_TIMING_DBUF_UPDATE_PENDING", 4, 4, &umr_bitfield_default },
	 { "OTG_TIMING_DB_UPDATE_PENDING", 5, 5, &umr_bitfield_default },
	 { "OTG_3D_CTRL_DB_UPDATE_PENDING", 6, 6, &umr_bitfield_default },
	 { "OTG_3D_STRUCTURE_EN_DB_UPDATE_PENDING", 7, 7, &umr_bitfield_default },
	 { "OTG_UPDATE_INSTANTLY", 8, 8, &umr_bitfield_default },
	 { "OTG_BLANK_DATA_DOUBLE_BUFFER_EN", 16, 16, &umr_bitfield_default },
	 { "OTG_RANGE_TIMING_DBUF_UPDATE_MODE", 24, 25, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG3_OTG_TEST_PATTERN_CONTROL[] = {
	 { "OTG_TEST_PATTERN_EN", 0, 0, &umr_bitfield_default },
	 { "OTG_TEST_PATTERN_MODE", 8, 10, &umr_bitfield_default },
	 { "OTG_TEST_PATTERN_DYNAMIC_RANGE", 16, 16, &umr_bitfield_default },
	 { "OTG_TEST_PATTERN_COLOR_FORMAT", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG3_OTG_TEST_PATTERN_PARAMETERS[] = {
	 { "OTG_TEST_PATTERN_INC0", 0, 3, &umr_bitfield_default },
	 { "OTG_TEST_PATTERN_INC1", 4, 7, &umr_bitfield_default },
	 { "OTG_TEST_PATTERN_VRES", 8, 11, &umr_bitfield_default },
	 { "OTG_TEST_PATTERN_HRES", 12, 15, &umr_bitfield_default },
	 { "OTG_TEST_PATTERN_RAMP0_OFFSET", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG3_OTG_TEST_PATTERN_COLOR[] = {
	 { "OTG_TEST_PATTERN_DATA", 0, 15, &umr_bitfield_default },
	 { "OTG_TEST_PATTERN_MASK", 16, 21, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG3_OTG_MASTER_EN[] = {
	 { "OTG_MASTER_EN", 0, 0, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG3_OTG_BLANK_DATA_COLOR[] = {
	 { "OTG_BLANK_DATA_COLOR_BLUE_CB", 0, 9, &umr_bitfield_default },
	 { "OTG_BLANK_DATA_COLOR_GREEN_Y", 10, 19, &umr_bitfield_default },
	 { "OTG_BLANK_DATA_COLOR_RED_CR", 20, 29, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG3_OTG_BLANK_DATA_COLOR_EXT[] = {
	 { "OTG_BLANK_DATA_COLOR_BLUE_CB_EXT", 0, 5, &umr_bitfield_default },
	 { "OTG_BLANK_DATA_COLOR_GREEN_Y_EXT", 8, 13, &umr_bitfield_default },
	 { "OTG_BLANK_DATA_COLOR_RED_CR_EXT", 16, 21, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG3_OTG_BLACK_COLOR[] = {
	 { "OTG_BLACK_COLOR_B_CB", 0, 9, &umr_bitfield_default },
	 { "OTG_BLACK_COLOR_G_Y", 10, 19, &umr_bitfield_default },
	 { "OTG_BLACK_COLOR_R_CR", 20, 29, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG3_OTG_BLACK_COLOR_EXT[] = {
	 { "OTG_BLACK_COLOR_B_CB_EXT", 0, 5, &umr_bitfield_default },
	 { "OTG_BLACK_COLOR_G_Y_EXT", 8, 13, &umr_bitfield_default },
	 { "OTG_BLACK_COLOR_R_CR_EXT", 16, 21, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG3_OTG_VERTICAL_INTERRUPT0_POSITION[] = {
	 { "OTG_VERTICAL_INTERRUPT0_LINE_START", 0, 14, &umr_bitfield_default },
	 { "OTG_VERTICAL_INTERRUPT0_LINE_END", 16, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG3_OTG_VERTICAL_INTERRUPT0_CONTROL[] = {
	 { "OTG_VERTICAL_INTERRUPT0_OUTPUT_POLARITY", 4, 4, &umr_bitfield_default },
	 { "OTG_VERTICAL_INTERRUPT0_INT_ENABLE", 8, 8, &umr_bitfield_default },
	 { "OTG_VERTICAL_INTERRUPT0_STATUS", 12, 12, &umr_bitfield_default },
	 { "OTG_VERTICAL_INTERRUPT0_INT_STATUS", 16, 16, &umr_bitfield_default },
	 { "OTG_VERTICAL_INTERRUPT0_CLEAR", 20, 20, &umr_bitfield_default },
	 { "OTG_VERTICAL_INTERRUPT0_INT_TYPE", 24, 24, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG3_OTG_VERTICAL_INTERRUPT1_POSITION[] = {
	 { "OTG_VERTICAL_INTERRUPT1_LINE_START", 0, 14, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG3_OTG_VERTICAL_INTERRUPT1_CONTROL[] = {
	 { "OTG_VERTICAL_INTERRUPT1_INT_ENABLE", 8, 8, &umr_bitfield_default },
	 { "OTG_VERTICAL_INTERRUPT1_STATUS", 12, 12, &umr_bitfield_default },
	 { "OTG_VERTICAL_INTERRUPT1_INT_STATUS", 16, 16, &umr_bitfield_default },
	 { "OTG_VERTICAL_INTERRUPT1_CLEAR", 20, 20, &umr_bitfield_default },
	 { "OTG_VERTICAL_INTERRUPT1_INT_TYPE", 24, 24, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG3_OTG_VERTICAL_INTERRUPT2_POSITION[] = {
	 { "OTG_VERTICAL_INTERRUPT2_LINE_START", 0, 14, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG3_OTG_VERTICAL_INTERRUPT2_CONTROL[] = {
	 { "OTG_VERTICAL_INTERRUPT2_INT_ENABLE", 8, 8, &umr_bitfield_default },
	 { "OTG_VERTICAL_INTERRUPT2_STATUS", 12, 12, &umr_bitfield_default },
	 { "OTG_VERTICAL_INTERRUPT2_INT_STATUS", 16, 16, &umr_bitfield_default },
	 { "OTG_VERTICAL_INTERRUPT2_CLEAR", 20, 20, &umr_bitfield_default },
	 { "OTG_VERTICAL_INTERRUPT2_INT_TYPE", 24, 24, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG3_OTG_CRC_CNTL[] = {
	 { "OTG_CRC_EN", 0, 0, &umr_bitfield_default },
	 { "OTG_CRC_DUAL_LINK_EN", 1, 1, &umr_bitfield_default },
	 { "OTG_CRC_DUAL_LINK_MODE", 2, 2, &umr_bitfield_default },
	 { "OTG_CRC_BLANK_ONLY", 3, 3, &umr_bitfield_default },
	 { "OTG_CRC_CONT_EN", 4, 4, &umr_bitfield_default },
	 { "OTG_CRC_CAPTURE_START_SEL", 5, 6, &umr_bitfield_default },
	 { "OTG_CRC_STEREO_MODE", 8, 9, &umr_bitfield_default },
	 { "OTG_CRC_INTERLACE_MODE", 12, 13, &umr_bitfield_default },
	 { "OTG_CRC_MULTI_STREAM_MODE", 16, 18, &umr_bitfield_default },
	 { "OTG_CRC_USE_NEW_AND_REPEATED_PIXELS", 19, 19, &umr_bitfield_default },
	 { "OTG_CRC0_SELECT", 20, 22, &umr_bitfield_default },
	 { "OTG_CRC1_SELECT", 24, 26, &umr_bitfield_default },
	 { "OTG_ONE_SHOT_CRC0_PENDING", 28, 28, &umr_bitfield_default },
	 { "OTG_ONE_SHOT_CRC1_PENDING", 29, 29, &umr_bitfield_default },
	 { "OTG_ONE_SHOT_CRC2_PENDING", 30, 30, &umr_bitfield_default },
	 { "OTG_ONE_SHOT_CRC3_PENDING", 31, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG3_OTG_CRC0_WINDOWA_X_CONTROL[] = {
	 { "OTG_CRC0_WINDOWA_X_START", 0, 14, &umr_bitfield_default },
	 { "OTG_CRC0_WINDOWA_X_END", 16, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG3_OTG_CRC0_WINDOWA_Y_CONTROL[] = {
	 { "OTG_CRC0_WINDOWA_Y_START", 0, 14, &umr_bitfield_default },
	 { "OTG_CRC0_WINDOWA_Y_END", 16, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG3_OTG_CRC0_WINDOWB_X_CONTROL[] = {
	 { "OTG_CRC0_WINDOWB_X_START", 0, 14, &umr_bitfield_default },
	 { "OTG_CRC0_WINDOWB_X_END", 16, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG3_OTG_CRC0_WINDOWB_Y_CONTROL[] = {
	 { "OTG_CRC0_WINDOWB_Y_START", 0, 14, &umr_bitfield_default },
	 { "OTG_CRC0_WINDOWB_Y_END", 16, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG3_OTG_CRC0_DATA_RG[] = {
	 { "CRC0_R_CR", 0, 15, &umr_bitfield_default },
	 { "CRC0_G_Y", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG3_OTG_CRC0_DATA_B[] = {
	 { "CRC0_B_CB", 0, 15, &umr_bitfield_default },
	 { "CRC0_C", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG3_OTG_CRC1_WINDOWA_X_CONTROL[] = {
	 { "OTG_CRC1_WINDOWA_X_START", 0, 14, &umr_bitfield_default },
	 { "OTG_CRC1_WINDOWA_X_END", 16, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG3_OTG_CRC1_WINDOWA_Y_CONTROL[] = {
	 { "OTG_CRC1_WINDOWA_Y_START", 0, 14, &umr_bitfield_default },
	 { "OTG_CRC1_WINDOWA_Y_END", 16, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG3_OTG_CRC1_WINDOWB_X_CONTROL[] = {
	 { "OTG_CRC1_WINDOWB_X_START", 0, 14, &umr_bitfield_default },
	 { "OTG_CRC1_WINDOWB_X_END", 16, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG3_OTG_CRC1_WINDOWB_Y_CONTROL[] = {
	 { "OTG_CRC1_WINDOWB_Y_START", 0, 14, &umr_bitfield_default },
	 { "OTG_CRC1_WINDOWB_Y_END", 16, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG3_OTG_CRC1_DATA_RG[] = {
	 { "CRC1_R_CR", 0, 15, &umr_bitfield_default },
	 { "CRC1_G_Y", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG3_OTG_CRC1_DATA_B[] = {
	 { "CRC1_B_CB", 0, 15, &umr_bitfield_default },
	 { "CRC1_C", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG3_OTG_CRC2_DATA_RG[] = {
	 { "CRC2_R_CR", 0, 15, &umr_bitfield_default },
	 { "CRC2_G_Y", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG3_OTG_CRC2_DATA_B[] = {
	 { "CRC2_B_CB", 0, 15, &umr_bitfield_default },
	 { "CRC2_C", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG3_OTG_CRC3_DATA_RG[] = {
	 { "CRC3_R_CR", 0, 15, &umr_bitfield_default },
	 { "CRC3_G_Y", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG3_OTG_CRC3_DATA_B[] = {
	 { "CRC3_B_CB", 0, 15, &umr_bitfield_default },
	 { "CRC3_C", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG3_OTG_CRC_SIG_RED_GREEN_MASK[] = {
	 { "OTG_CRC_SIG_RED_MASK", 0, 15, &umr_bitfield_default },
	 { "OTG_CRC_SIG_GREEN_MASK", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG3_OTG_CRC_SIG_BLUE_CONTROL_MASK[] = {
	 { "OTG_CRC_SIG_BLUE_MASK", 0, 15, &umr_bitfield_default },
	 { "OTG_CRC_SIG_CONTROL_MASK", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG3_OTG_STATIC_SCREEN_CONTROL[] = {
	 { "OTG_STATIC_SCREEN_EVENT_MASK", 0, 15, &umr_bitfield_default },
	 { "OTG_STATIC_SCREEN_FRAME_COUNT", 16, 23, &umr_bitfield_default },
	 { "OTG_CPU_SS_INT_ENABLE", 24, 24, &umr_bitfield_default },
	 { "OTG_SS_STATUS", 25, 25, &umr_bitfield_default },
	 { "OTG_CPU_SS_INT_STATUS", 26, 26, &umr_bitfield_default },
	 { "OTG_CPU_SS_INT_CLEAR", 27, 27, &umr_bitfield_default },
	 { "OTG_CPU_SS_INT_TYPE", 28, 28, &umr_bitfield_default },
	 { "OTG_STATIC_SCREEN_OVERRIDE", 30, 30, &umr_bitfield_default },
	 { "OTG_STATIC_SCREEN_OVERRIDE_VALUE", 31, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG3_OTG_3D_STRUCTURE_CONTROL[] = {
	 { "OTG_3D_STRUCTURE_EN", 0, 0, &umr_bitfield_default },
	 { "OTG_3D_STRUCTURE_V_UPDATE_MODE", 8, 9, &umr_bitfield_default },
	 { "OTG_3D_STRUCTURE_STEREO_SEL_OVR", 12, 12, &umr_bitfield_default },
	 { "OTG_3D_STRUCTURE_F_COUNT_RESET", 16, 16, &umr_bitfield_default },
	 { "OTG_3D_STRUCTURE_F_COUNT_RESET_PENDING", 17, 17, &umr_bitfield_default },
	 { "OTG_3D_STRUCTURE_F_COUNT", 18, 19, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG3_OTG_GSL_VSYNC_GAP[] = {
	 { "OTG_GSL_VSYNC_GAP_LIMIT", 0, 7, &umr_bitfield_default },
	 { "OTG_GSL_VSYNC_GAP_DELAY", 8, 15, &umr_bitfield_default },
	 { "OTG_GSL_VSYNC_GAP_SOURCE_SEL", 16, 16, &umr_bitfield_default },
	 { "OTG_GSL_VSYNC_GAP_MODE", 17, 18, &umr_bitfield_default },
	 { "OTG_GSL_VSYNC_GAP_CLEAR", 19, 19, &umr_bitfield_default },
	 { "OTG_GSL_VSYNC_GAP_OCCURRED", 20, 20, &umr_bitfield_default },
	 { "OTG_GSL_VSYNC_GAP_MASTER_FASTER", 23, 23, &umr_bitfield_default },
	 { "OTG_GSL_VSYNC_GAP", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG3_OTG_MASTER_UPDATE_MODE[] = {
	 { "MASTER_UPDATE_INTERLACED_MODE", 0, 1, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG3_OTG_CLOCK_CONTROL[] = {
	 { "OTG_CLOCK_EN", 0, 0, &umr_bitfield_default },
	 { "OTG_CLOCK_GATE_DIS", 1, 1, &umr_bitfield_default },
	 { "OTG_SOFT_RESET", 4, 4, &umr_bitfield_default },
	 { "OTG_CLOCK_ON", 8, 8, &umr_bitfield_default },
	 { "OTG_BUSY", 16, 16, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG3_OTG_VSTARTUP_PARAM[] = {
	 { "VSTARTUP_START", 0, 9, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG3_OTG_VUPDATE_PARAM[] = {
	 { "VUPDATE_OFFSET", 0, 15, &umr_bitfield_default },
	 { "VUPDATE_WIDTH", 16, 25, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG3_OTG_VREADY_PARAM[] = {
	 { "VREADY_OFFSET", 0, 15, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG3_OTG_GLOBAL_SYNC_STATUS[] = {
	 { "VSTARTUP_INT_EN", 0, 0, &umr_bitfield_default },
	 { "VSTARTUP_INT_TYPE", 1, 1, &umr_bitfield_default },
	 { "VSTARTUP_EVENT_OCCURRED", 2, 2, &umr_bitfield_default },
	 { "VSTARTUP_INT_STATUS", 3, 3, &umr_bitfield_default },
	 { "VSTARTUP_EVENT_CLEAR", 4, 4, &umr_bitfield_default },
	 { "VUPDATE_INT_EN", 5, 5, &umr_bitfield_default },
	 { "VUPDATE_INT_TYPE", 6, 6, &umr_bitfield_default },
	 { "VUPDATE_INT_POSITION_SEL", 7, 7, &umr_bitfield_default },
	 { "VUPDATE_EVENT_OCCURRED", 8, 8, &umr_bitfield_default },
	 { "VUPDATE_INT_STATUS", 9, 9, &umr_bitfield_default },
	 { "VUPDATE_EVENT_CLEAR", 10, 10, &umr_bitfield_default },
	 { "VUPDATE_STATUS", 11, 11, &umr_bitfield_default },
	 { "VUPDATE_NO_LOCK_INT_EN", 12, 12, &umr_bitfield_default },
	 { "VUPDATE_NO_LOCK_INT_TYPE", 13, 13, &umr_bitfield_default },
	 { "VUPDATE_NO_LOCK_EVENT_OCCURRED", 14, 14, &umr_bitfield_default },
	 { "VUPDATE_NO_LOCK_INT_STATUS", 15, 15, &umr_bitfield_default },
	 { "VUPDATE_NO_LOCK_EVENT_CLEAR", 16, 16, &umr_bitfield_default },
	 { "VUPDATE_NO_LOCK_STATUS", 17, 17, &umr_bitfield_default },
	 { "VREADY_INT_EN", 18, 18, &umr_bitfield_default },
	 { "VREADY_INT_TYPE", 19, 19, &umr_bitfield_default },
	 { "VREADY_EVENT_OCCURRED", 20, 20, &umr_bitfield_default },
	 { "VREADY_INT_STATUS", 21, 21, &umr_bitfield_default },
	 { "VREADY_EVENT_CLEAR", 22, 22, &umr_bitfield_default },
	 { "STEREO_SELECT_STATUS", 24, 24, &umr_bitfield_default },
	 { "FIELD_NUMBER_STATUS", 25, 25, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG3_OTG_MASTER_UPDATE_LOCK[] = {
	 { "OTG_MASTER_UPDATE_LOCK", 0, 0, &umr_bitfield_default },
	 { "UPDATE_LOCK_STATUS", 8, 8, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG3_OTG_GSL_CONTROL[] = {
	 { "OTG_GSL0_EN", 0, 0, &umr_bitfield_default },
	 { "OTG_GSL1_EN", 1, 1, &umr_bitfield_default },
	 { "OTG_GSL2_EN", 2, 2, &umr_bitfield_default },
	 { "OTG_GSL_MASTER_EN", 3, 3, &umr_bitfield_default },
	 { "OTG_GSL_FORCE_DELAY", 16, 20, &umr_bitfield_default },
	 { "OTG_GSL_CHECK_ALL_FIELDS", 28, 28, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG3_OTG_GSL_WINDOW_X[] = {
	 { "OTG_GSL_WINDOW_START_X", 0, 14, &umr_bitfield_default },
	 { "OTG_GSL_WINDOW_END_X", 16, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG3_OTG_GSL_WINDOW_Y[] = {
	 { "OTG_GSL_WINDOW_START_Y", 0, 14, &umr_bitfield_default },
	 { "OTG_GSL_WINDOW_END_Y", 16, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG3_OTG_VUPDATE_KEEPOUT[] = {
	 { "MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_START_OFFSET", 0, 15, &umr_bitfield_default },
	 { "MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_END_OFFSET", 16, 25, &umr_bitfield_default },
	 { "OTG_MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_EN", 31, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG3_OTG_GLOBAL_CONTROL0[] = {
	 { "OTG_MASTER_UPDATE_LOCK_HTOTAL_KEEPOUT", 0, 7, &umr_bitfield_default },
	 { "OTG_MASTER_UPDATE_LOCK_HTOTAL_KEEPOUT_EN", 8, 8, &umr_bitfield_default },
	 { "OTG_MASTER_UPDATE_LOCK_SEL", 25, 27, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG3_OTG_GLOBAL_CONTROL1[] = {
	 { "MASTER_UPDATE_LOCK_DB_X", 0, 14, &umr_bitfield_default },
	 { "MASTER_UPDATE_LOCK_DB_Y", 16, 30, &umr_bitfield_default },
	 { "MASTER_UPDATE_LOCK_DB_EN", 31, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG3_OTG_GLOBAL_CONTROL2[] = {
	 { "DIG_UPDATE_LOCATION", 0, 9, &umr_bitfield_default },
	 { "GLOBAL_UPDATE_LOCK_EN", 10, 10, &umr_bitfield_default },
	 { "MANUAL_FLOW_CONTROL_SEL", 16, 18, &umr_bitfield_default },
	 { "DCCG_VUPDATE_MODE", 31, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG3_OTG_GLOBAL_CONTROL3[] = {
	 { "MASTER_UPDATE_LOCK_DB_FIELD", 0, 1, &umr_bitfield_default },
	 { "MASTER_UPDATE_LOCK_DB_STEREO_SEL", 4, 5, &umr_bitfield_default },
	 { "MASTER_UPDATE_LOCK_DB_FIELD_STEREO_FLAG_SEL", 8, 8, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG3_OTG_TRIG_MANUAL_CONTROL[] = {
	 { "TRIG_MANUAL_CONTROL", 0, 0, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG3_OTG_MANUAL_FLOW_CONTROL[] = {
	 { "MANUAL_FLOW_CONTROL", 0, 0, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG3_OTG_RANGE_TIMING_INT_STATUS[] = {
	 { "OTG_RANGE_TIMING_UPDATE_OCCURRED", 0, 0, &umr_bitfield_default },
	 { "OTG_RANGE_TIMING_UPDATE_OCCURRED_INT", 4, 4, &umr_bitfield_default },
	 { "OTG_RANGE_TIMING_UPDATE_OCCURRED_CLEAR", 8, 8, &umr_bitfield_default },
	 { "OTG_RANGE_TIMING_UPDATE_OCCURRED_INT_MSK", 12, 12, &umr_bitfield_default },
	 { "OTG_RANGE_TIMING_UPDATE_OCCURRED_INT_TYPE", 16, 16, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG3_OTG_DRR_CONTROL[] = {
	 { "OTG_DRR_AVERAGE_FRAME", 0, 2, &umr_bitfield_default },
	 { "OTG_V_TOTAL_LAST_USED_BY_DRR", 16, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG3_OTG_REQUEST_CONTROL[] = {
	 { "OTG_REQUEST_MODE_FOR_H_DUPLICATE", 0, 0, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG3_OTG_SPARE_REGISTER[] = {
	 { "OTG_SPARE_REG", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG4_OTG_H_TOTAL[] = {
	 { "OTG_H_TOTAL", 0, 14, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG4_OTG_H_BLANK_START_END[] = {
	 { "OTG_H_BLANK_START", 0, 14, &umr_bitfield_default },
	 { "OTG_H_BLANK_END", 16, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG4_OTG_H_SYNC_A[] = {
	 { "OTG_H_SYNC_A_START", 0, 14, &umr_bitfield_default },
	 { "OTG_H_SYNC_A_END", 16, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG4_OTG_H_SYNC_A_CNTL[] = {
	 { "OTG_H_SYNC_A_POL", 0, 0, &umr_bitfield_default },
	 { "OTG_COMP_SYNC_A_EN", 16, 16, &umr_bitfield_default },
	 { "OTG_H_SYNC_A_CUTOFF", 17, 17, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG4_OTG_H_TIMING_CNTL[] = {
	 { "OTG_H_TIMING_DIV_BY2", 0, 0, &umr_bitfield_default },
	 { "OTG_H_TIMING_DIV_BY2_UPDATE_MODE", 8, 8, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG4_OTG_V_TOTAL[] = {
	 { "OTG_V_TOTAL", 0, 14, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG4_OTG_V_TOTAL_MIN[] = {
	 { "OTG_V_TOTAL_MIN", 0, 14, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG4_OTG_V_TOTAL_MAX[] = {
	 { "OTG_V_TOTAL_MAX", 0, 14, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG4_OTG_V_TOTAL_MID[] = {
	 { "OTG_V_TOTAL_MID", 0, 14, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG4_OTG_V_TOTAL_CONTROL[] = {
	 { "OTG_V_TOTAL_MIN_SEL", 0, 0, &umr_bitfield_default },
	 { "OTG_V_TOTAL_MAX_SEL", 1, 1, &umr_bitfield_default },
	 { "OTG_VTOTAL_MID_REPLACING_MAX_EN", 2, 2, &umr_bitfield_default },
	 { "OTG_VTOTAL_MID_REPLACING_MIN_EN", 3, 3, &umr_bitfield_default },
	 { "OTG_FORCE_LOCK_ON_EVENT", 4, 4, &umr_bitfield_default },
	 { "OTG_SET_V_TOTAL_MIN_MASK_EN", 7, 7, &umr_bitfield_default },
	 { "OTG_VTOTAL_MID_FRAME_NUM", 8, 15, &umr_bitfield_default },
	 { "OTG_SET_V_TOTAL_MIN_MASK", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG4_OTG_V_TOTAL_INT_STATUS[] = {
	 { "OTG_SET_V_TOTAL_MIN_EVENT_OCCURED", 0, 0, &umr_bitfield_default },
	 { "OTG_SET_V_TOTAL_MIN_EVENT_OCCURED_INT", 4, 4, &umr_bitfield_default },
	 { "OTG_SET_V_TOTAL_MIN_EVENT_OCCURED_ACK", 8, 8, &umr_bitfield_default },
	 { "OTG_SET_V_TOTAL_MIN_EVENT_OCCURED_MSK", 12, 12, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG4_OTG_VSYNC_NOM_INT_STATUS[] = {
	 { "OTG_VSYNC_NOM", 0, 0, &umr_bitfield_default },
	 { "OTG_VSYNC_NOM_INT_CLEAR", 4, 4, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG4_OTG_V_BLANK_START_END[] = {
	 { "OTG_V_BLANK_START", 0, 14, &umr_bitfield_default },
	 { "OTG_V_BLANK_END", 16, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG4_OTG_V_SYNC_A[] = {
	 { "OTG_V_SYNC_A_START", 0, 14, &umr_bitfield_default },
	 { "OTG_V_SYNC_A_END", 16, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG4_OTG_V_SYNC_A_CNTL[] = {
	 { "OTG_V_SYNC_A_POL", 0, 0, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG4_OTG_TRIGA_CNTL[] = {
	 { "OTG_TRIGA_SOURCE_SELECT", 0, 4, &umr_bitfield_default },
	 { "OTG_TRIGA_SOURCE_PIPE_SELECT", 5, 7, &umr_bitfield_default },
	 { "OTG_TRIGA_POLARITY_SELECT", 8, 10, &umr_bitfield_default },
	 { "OTG_TRIGA_RESYNC_BYPASS_EN", 11, 11, &umr_bitfield_default },
	 { "OTG_TRIGA_INPUT_STATUS", 12, 12, &umr_bitfield_default },
	 { "OTG_TRIGA_POLARITY_STATUS", 13, 13, &umr_bitfield_default },
	 { "OTG_TRIGA_OCCURRED", 14, 14, &umr_bitfield_default },
	 { "OTG_TRIGA_RISING_EDGE_DETECT_CNTL", 16, 17, &umr_bitfield_default },
	 { "OTG_TRIGA_FALLING_EDGE_DETECT_CNTL", 18, 19, &umr_bitfield_default },
	 { "OTG_TRIGA_FREQUENCY_SELECT", 20, 21, &umr_bitfield_default },
	 { "OTG_TRIGA_DELAY", 24, 28, &umr_bitfield_default },
	 { "OTG_TRIGA_CLEAR", 31, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG4_OTG_TRIGA_MANUAL_TRIG[] = {
	 { "OTG_TRIGA_MANUAL_TRIG", 0, 0, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG4_OTG_TRIGB_CNTL[] = {
	 { "OTG_TRIGB_SOURCE_SELECT", 0, 4, &umr_bitfield_default },
	 { "OTG_TRIGB_SOURCE_PIPE_SELECT", 5, 7, &umr_bitfield_default },
	 { "OTG_TRIGB_POLARITY_SELECT", 8, 10, &umr_bitfield_default },
	 { "OTG_TRIGB_RESYNC_BYPASS_EN", 11, 11, &umr_bitfield_default },
	 { "OTG_TRIGB_INPUT_STATUS", 12, 12, &umr_bitfield_default },
	 { "OTG_TRIGB_POLARITY_STATUS", 13, 13, &umr_bitfield_default },
	 { "OTG_TRIGB_OCCURRED", 14, 14, &umr_bitfield_default },
	 { "OTG_TRIGB_RISING_EDGE_DETECT_CNTL", 16, 17, &umr_bitfield_default },
	 { "OTG_TRIGB_FALLING_EDGE_DETECT_CNTL", 18, 19, &umr_bitfield_default },
	 { "OTG_TRIGB_FREQUENCY_SELECT", 20, 21, &umr_bitfield_default },
	 { "OTG_TRIGB_DELAY", 24, 28, &umr_bitfield_default },
	 { "OTG_TRIGB_CLEAR", 31, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG4_OTG_TRIGB_MANUAL_TRIG[] = {
	 { "OTG_TRIGB_MANUAL_TRIG", 0, 0, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG4_OTG_FORCE_COUNT_NOW_CNTL[] = {
	 { "OTG_FORCE_COUNT_NOW_MODE", 0, 1, &umr_bitfield_default },
	 { "OTG_FORCE_COUNT_NOW_CHECK", 4, 4, &umr_bitfield_default },
	 { "OTG_FORCE_COUNT_NOW_TRIG_SEL", 8, 8, &umr_bitfield_default },
	 { "OTG_FORCE_COUNT_NOW_OCCURRED", 16, 16, &umr_bitfield_default },
	 { "OTG_FORCE_COUNT_NOW_CLEAR", 24, 24, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG4_OTG_FLOW_CONTROL[] = {
	 { "OTG_FLOW_CONTROL_SOURCE_SELECT", 0, 4, &umr_bitfield_default },
	 { "OTG_FLOW_CONTROL_POLARITY", 8, 8, &umr_bitfield_default },
	 { "OTG_FLOW_CONTROL_GRANULARITY", 16, 16, &umr_bitfield_default },
	 { "OTG_FLOW_CONTROL_INPUT_STATUS", 24, 24, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG4_OTG_STEREO_FORCE_NEXT_EYE[] = {
	 { "OTG_STEREO_FORCE_NEXT_EYE", 0, 1, &umr_bitfield_default },
	 { "OTG_AVSYNC_FRAME_COUNTER", 8, 15, &umr_bitfield_default },
	 { "OTG_AVSYNC_LINE_COUNTER", 16, 28, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG4_OTG_AVSYNC_COUNTER[] = {
	 { "OTG_AVSYNC_COUNTER", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG4_OTG_CONTROL[] = {
	 { "OTG_MASTER_EN", 0, 0, &umr_bitfield_default },
	 { "OTG_DISABLE_POINT_CNTL", 8, 9, &umr_bitfield_default },
	 { "OTG_START_POINT_CNTL", 12, 12, &umr_bitfield_default },
	 { "OTG_FIELD_NUMBER_CNTL", 13, 13, &umr_bitfield_default },
	 { "OTG_FIELD_NUMBER_POLARITY", 14, 14, &umr_bitfield_default },
	 { "OTG_CURRENT_MASTER_EN_STATE", 16, 16, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG4_OTG_BLANK_CONTROL[] = {
	 { "OTG_CURRENT_BLANK_STATE", 0, 0, &umr_bitfield_default },
	 { "OTG_BLANK_DATA_EN", 8, 8, &umr_bitfield_default },
	 { "OTG_BLANK_DE_MODE", 16, 16, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG4_OTG_PIPE_ABORT_CONTROL[] = {
	 { "OTG_PIPE_ABORT", 0, 0, &umr_bitfield_default },
	 { "OTG_PIPE_ABORT_DONE", 8, 8, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG4_OTG_INTERLACE_CONTROL[] = {
	 { "OTG_INTERLACE_ENABLE", 0, 0, &umr_bitfield_default },
	 { "OTG_INTERLACE_FORCE_NEXT_FIELD", 16, 17, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG4_OTG_INTERLACE_STATUS[] = {
	 { "OTG_INTERLACE_CURRENT_FIELD", 0, 0, &umr_bitfield_default },
	 { "OTG_INTERLACE_NEXT_FIELD", 1, 1, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG4_OTG_FIELD_INDICATION_CONTROL[] = {
	 { "OTG_FIELD_INDICATION_OUTPUT_POLARITY", 0, 0, &umr_bitfield_default },
	 { "OTG_FIELD_ALIGNMENT", 1, 1, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG4_OTG_PIXEL_DATA_READBACK0[] = {
	 { "OTG_PIXEL_DATA_BLUE_CB", 0, 15, &umr_bitfield_default },
	 { "OTG_PIXEL_DATA_GREEN_Y", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG4_OTG_PIXEL_DATA_READBACK1[] = {
	 { "OTG_PIXEL_DATA_RED_CR", 0, 15, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG4_OTG_STATUS[] = {
	 { "OTG_V_BLANK", 0, 0, &umr_bitfield_default },
	 { "OTG_V_ACTIVE_DISP", 1, 1, &umr_bitfield_default },
	 { "OTG_V_SYNC_A", 2, 2, &umr_bitfield_default },
	 { "OTG_V_UPDATE", 3, 3, &umr_bitfield_default },
	 { "OTG_V_BLANK_3D_STRUCTURE", 5, 5, &umr_bitfield_default },
	 { "OTG_H_BLANK", 16, 16, &umr_bitfield_default },
	 { "OTG_H_ACTIVE_DISP", 17, 17, &umr_bitfield_default },
	 { "OTG_H_SYNC_A", 18, 18, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG4_OTG_STATUS_POSITION[] = {
	 { "OTG_VERT_COUNT", 0, 14, &umr_bitfield_default },
	 { "OTG_HORZ_COUNT", 16, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG4_OTG_NOM_VERT_POSITION[] = {
	 { "OTG_VERT_COUNT_NOM", 0, 14, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG4_OTG_STATUS_FRAME_COUNT[] = {
	 { "OTG_FRAME_COUNT", 0, 23, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG4_OTG_STATUS_VF_COUNT[] = {
	 { "OTG_VF_COUNT", 0, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG4_OTG_STATUS_HV_COUNT[] = {
	 { "OTG_HV_COUNT", 0, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG4_OTG_COUNT_CONTROL[] = {
	 { "OTG_HORZ_COUNT_BY2_EN", 0, 0, &umr_bitfield_default },
	 { "OTG_HORZ_REPETITION_COUNT", 1, 4, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG4_OTG_COUNT_RESET[] = {
	 { "OTG_RESET_FRAME_COUNT", 0, 0, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG4_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE[] = {
	 { "OTG_MANUAL_FORCE_VSYNC_NEXT_LINE", 0, 0, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG4_OTG_VERT_SYNC_CONTROL[] = {
	 { "OTG_FORCE_VSYNC_NEXT_LINE_OCCURRED", 0, 0, &umr_bitfield_default },
	 { "OTG_FORCE_VSYNC_NEXT_LINE_CLEAR", 8, 8, &umr_bitfield_default },
	 { "OTG_AUTO_FORCE_VSYNC_MODE", 16, 17, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG4_OTG_STEREO_STATUS[] = {
	 { "OTG_STEREO_CURRENT_EYE", 0, 0, &umr_bitfield_default },
	 { "OTG_STEREO_SYNC_OUTPUT", 8, 8, &umr_bitfield_default },
	 { "OTG_STEREO_SYNC_SELECT", 16, 16, &umr_bitfield_default },
	 { "OTG_STEREO_EYE_FLAG", 20, 20, &umr_bitfield_default },
	 { "OTG_STEREO_FORCE_NEXT_EYE_PENDING", 24, 25, &umr_bitfield_default },
	 { "OTG_CURRENT_3D_STRUCTURE_STATE", 30, 30, &umr_bitfield_default },
	 { "OTG_CURRENT_STEREOSYNC_EN_STATE", 31, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG4_OTG_STEREO_CONTROL[] = {
	 { "OTG_STEREO_SYNC_OUTPUT_LINE_NUM", 0, 14, &umr_bitfield_default },
	 { "OTG_STEREO_SYNC_OUTPUT_POLARITY", 15, 15, &umr_bitfield_default },
	 { "OTG_STEREO_EYE_FLAG_POLARITY", 17, 17, &umr_bitfield_default },
	 { "OTG_DISABLE_STEREOSYNC_OUTPUT_FOR_DP", 18, 18, &umr_bitfield_default },
	 { "OTG_DISABLE_FIELD_NUM", 19, 19, &umr_bitfield_default },
	 { "OTG_DISABLE_V_BLANK_FOR_DP_FIX", 20, 20, &umr_bitfield_default },
	 { "OTG_STEREO_EN", 24, 24, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG4_OTG_SNAPSHOT_STATUS[] = {
	 { "OTG_SNAPSHOT_OCCURRED", 0, 0, &umr_bitfield_default },
	 { "OTG_SNAPSHOT_CLEAR", 1, 1, &umr_bitfield_default },
	 { "OTG_SNAPSHOT_MANUAL_TRIGGER", 2, 2, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG4_OTG_SNAPSHOT_CONTROL[] = {
	 { "OTG_AUTO_SNAPSHOT_TRIG_SEL", 0, 1, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG4_OTG_SNAPSHOT_POSITION[] = {
	 { "OTG_SNAPSHOT_VERT_COUNT", 0, 14, &umr_bitfield_default },
	 { "OTG_SNAPSHOT_HORZ_COUNT", 16, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG4_OTG_SNAPSHOT_FRAME[] = {
	 { "OTG_SNAPSHOT_FRAME_COUNT", 0, 23, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG4_OTG_INTERRUPT_CONTROL[] = {
	 { "OTG_SNAPSHOT_INT_MSK", 0, 0, &umr_bitfield_default },
	 { "OTG_SNAPSHOT_INT_TYPE", 1, 1, &umr_bitfield_default },
	 { "OTG_FORCE_COUNT_NOW_INT_MSK", 8, 8, &umr_bitfield_default },
	 { "OTG_FORCE_COUNT_NOW_INT_TYPE", 9, 9, &umr_bitfield_default },
	 { "OTG_FORCE_VSYNC_NEXT_LINE_INT_MSK", 16, 16, &umr_bitfield_default },
	 { "OTG_FORCE_VSYNC_NEXT_LINE_INT_TYPE", 17, 17, &umr_bitfield_default },
	 { "OTG_TRIGA_INT_MSK", 24, 24, &umr_bitfield_default },
	 { "OTG_TRIGB_INT_MSK", 25, 25, &umr_bitfield_default },
	 { "OTG_TRIGA_INT_TYPE", 26, 26, &umr_bitfield_default },
	 { "OTG_TRIGB_INT_TYPE", 27, 27, &umr_bitfield_default },
	 { "OTG_VSYNC_NOM_INT_MSK", 28, 28, &umr_bitfield_default },
	 { "OTG_VSYNC_NOM_INT_TYPE", 29, 29, &umr_bitfield_default },
	 { "OTG_GSL_VSYNC_GAP_INT_MSK", 30, 30, &umr_bitfield_default },
	 { "OTG_GSL_VSYNC_GAP_INT_TYPE", 31, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG4_OTG_UPDATE_LOCK[] = {
	 { "OTG_UPDATE_LOCK", 0, 0, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG4_OTG_DOUBLE_BUFFER_CONTROL[] = {
	 { "OTG_UPDATE_PENDING", 0, 0, &umr_bitfield_default },
	 { "OTG_H_TIMING_DIV_BY2_DB_UPDATE_PENDING", 2, 2, &umr_bitfield_default },
	 { "OTG_BLANK_DATA_EN_UPDATE_PENDING", 3, 3, &umr_bitfield_default },
	 { "OTG_RANGE_TIMING_DBUF_UPDATE_PENDING", 4, 4, &umr_bitfield_default },
	 { "OTG_TIMING_DB_UPDATE_PENDING", 5, 5, &umr_bitfield_default },
	 { "OTG_3D_CTRL_DB_UPDATE_PENDING", 6, 6, &umr_bitfield_default },
	 { "OTG_3D_STRUCTURE_EN_DB_UPDATE_PENDING", 7, 7, &umr_bitfield_default },
	 { "OTG_UPDATE_INSTANTLY", 8, 8, &umr_bitfield_default },
	 { "OTG_BLANK_DATA_DOUBLE_BUFFER_EN", 16, 16, &umr_bitfield_default },
	 { "OTG_RANGE_TIMING_DBUF_UPDATE_MODE", 24, 25, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG4_OTG_TEST_PATTERN_CONTROL[] = {
	 { "OTG_TEST_PATTERN_EN", 0, 0, &umr_bitfield_default },
	 { "OTG_TEST_PATTERN_MODE", 8, 10, &umr_bitfield_default },
	 { "OTG_TEST_PATTERN_DYNAMIC_RANGE", 16, 16, &umr_bitfield_default },
	 { "OTG_TEST_PATTERN_COLOR_FORMAT", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG4_OTG_TEST_PATTERN_PARAMETERS[] = {
	 { "OTG_TEST_PATTERN_INC0", 0, 3, &umr_bitfield_default },
	 { "OTG_TEST_PATTERN_INC1", 4, 7, &umr_bitfield_default },
	 { "OTG_TEST_PATTERN_VRES", 8, 11, &umr_bitfield_default },
	 { "OTG_TEST_PATTERN_HRES", 12, 15, &umr_bitfield_default },
	 { "OTG_TEST_PATTERN_RAMP0_OFFSET", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG4_OTG_TEST_PATTERN_COLOR[] = {
	 { "OTG_TEST_PATTERN_DATA", 0, 15, &umr_bitfield_default },
	 { "OTG_TEST_PATTERN_MASK", 16, 21, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG4_OTG_MASTER_EN[] = {
	 { "OTG_MASTER_EN", 0, 0, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG4_OTG_BLANK_DATA_COLOR[] = {
	 { "OTG_BLANK_DATA_COLOR_BLUE_CB", 0, 9, &umr_bitfield_default },
	 { "OTG_BLANK_DATA_COLOR_GREEN_Y", 10, 19, &umr_bitfield_default },
	 { "OTG_BLANK_DATA_COLOR_RED_CR", 20, 29, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG4_OTG_BLANK_DATA_COLOR_EXT[] = {
	 { "OTG_BLANK_DATA_COLOR_BLUE_CB_EXT", 0, 5, &umr_bitfield_default },
	 { "OTG_BLANK_DATA_COLOR_GREEN_Y_EXT", 8, 13, &umr_bitfield_default },
	 { "OTG_BLANK_DATA_COLOR_RED_CR_EXT", 16, 21, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG4_OTG_BLACK_COLOR[] = {
	 { "OTG_BLACK_COLOR_B_CB", 0, 9, &umr_bitfield_default },
	 { "OTG_BLACK_COLOR_G_Y", 10, 19, &umr_bitfield_default },
	 { "OTG_BLACK_COLOR_R_CR", 20, 29, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG4_OTG_BLACK_COLOR_EXT[] = {
	 { "OTG_BLACK_COLOR_B_CB_EXT", 0, 5, &umr_bitfield_default },
	 { "OTG_BLACK_COLOR_G_Y_EXT", 8, 13, &umr_bitfield_default },
	 { "OTG_BLACK_COLOR_R_CR_EXT", 16, 21, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG4_OTG_VERTICAL_INTERRUPT0_POSITION[] = {
	 { "OTG_VERTICAL_INTERRUPT0_LINE_START", 0, 14, &umr_bitfield_default },
	 { "OTG_VERTICAL_INTERRUPT0_LINE_END", 16, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG4_OTG_VERTICAL_INTERRUPT0_CONTROL[] = {
	 { "OTG_VERTICAL_INTERRUPT0_OUTPUT_POLARITY", 4, 4, &umr_bitfield_default },
	 { "OTG_VERTICAL_INTERRUPT0_INT_ENABLE", 8, 8, &umr_bitfield_default },
	 { "OTG_VERTICAL_INTERRUPT0_STATUS", 12, 12, &umr_bitfield_default },
	 { "OTG_VERTICAL_INTERRUPT0_INT_STATUS", 16, 16, &umr_bitfield_default },
	 { "OTG_VERTICAL_INTERRUPT0_CLEAR", 20, 20, &umr_bitfield_default },
	 { "OTG_VERTICAL_INTERRUPT0_INT_TYPE", 24, 24, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG4_OTG_VERTICAL_INTERRUPT1_POSITION[] = {
	 { "OTG_VERTICAL_INTERRUPT1_LINE_START", 0, 14, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG4_OTG_VERTICAL_INTERRUPT1_CONTROL[] = {
	 { "OTG_VERTICAL_INTERRUPT1_INT_ENABLE", 8, 8, &umr_bitfield_default },
	 { "OTG_VERTICAL_INTERRUPT1_STATUS", 12, 12, &umr_bitfield_default },
	 { "OTG_VERTICAL_INTERRUPT1_INT_STATUS", 16, 16, &umr_bitfield_default },
	 { "OTG_VERTICAL_INTERRUPT1_CLEAR", 20, 20, &umr_bitfield_default },
	 { "OTG_VERTICAL_INTERRUPT1_INT_TYPE", 24, 24, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG4_OTG_VERTICAL_INTERRUPT2_POSITION[] = {
	 { "OTG_VERTICAL_INTERRUPT2_LINE_START", 0, 14, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG4_OTG_VERTICAL_INTERRUPT2_CONTROL[] = {
	 { "OTG_VERTICAL_INTERRUPT2_INT_ENABLE", 8, 8, &umr_bitfield_default },
	 { "OTG_VERTICAL_INTERRUPT2_STATUS", 12, 12, &umr_bitfield_default },
	 { "OTG_VERTICAL_INTERRUPT2_INT_STATUS", 16, 16, &umr_bitfield_default },
	 { "OTG_VERTICAL_INTERRUPT2_CLEAR", 20, 20, &umr_bitfield_default },
	 { "OTG_VERTICAL_INTERRUPT2_INT_TYPE", 24, 24, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG4_OTG_CRC_CNTL[] = {
	 { "OTG_CRC_EN", 0, 0, &umr_bitfield_default },
	 { "OTG_CRC_DUAL_LINK_EN", 1, 1, &umr_bitfield_default },
	 { "OTG_CRC_DUAL_LINK_MODE", 2, 2, &umr_bitfield_default },
	 { "OTG_CRC_BLANK_ONLY", 3, 3, &umr_bitfield_default },
	 { "OTG_CRC_CONT_EN", 4, 4, &umr_bitfield_default },
	 { "OTG_CRC_CAPTURE_START_SEL", 5, 6, &umr_bitfield_default },
	 { "OTG_CRC_STEREO_MODE", 8, 9, &umr_bitfield_default },
	 { "OTG_CRC_INTERLACE_MODE", 12, 13, &umr_bitfield_default },
	 { "OTG_CRC_MULTI_STREAM_MODE", 16, 18, &umr_bitfield_default },
	 { "OTG_CRC_USE_NEW_AND_REPEATED_PIXELS", 19, 19, &umr_bitfield_default },
	 { "OTG_CRC0_SELECT", 20, 22, &umr_bitfield_default },
	 { "OTG_CRC1_SELECT", 24, 26, &umr_bitfield_default },
	 { "OTG_ONE_SHOT_CRC0_PENDING", 28, 28, &umr_bitfield_default },
	 { "OTG_ONE_SHOT_CRC1_PENDING", 29, 29, &umr_bitfield_default },
	 { "OTG_ONE_SHOT_CRC2_PENDING", 30, 30, &umr_bitfield_default },
	 { "OTG_ONE_SHOT_CRC3_PENDING", 31, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG4_OTG_CRC0_WINDOWA_X_CONTROL[] = {
	 { "OTG_CRC0_WINDOWA_X_START", 0, 14, &umr_bitfield_default },
	 { "OTG_CRC0_WINDOWA_X_END", 16, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG4_OTG_CRC0_WINDOWA_Y_CONTROL[] = {
	 { "OTG_CRC0_WINDOWA_Y_START", 0, 14, &umr_bitfield_default },
	 { "OTG_CRC0_WINDOWA_Y_END", 16, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG4_OTG_CRC0_WINDOWB_X_CONTROL[] = {
	 { "OTG_CRC0_WINDOWB_X_START", 0, 14, &umr_bitfield_default },
	 { "OTG_CRC0_WINDOWB_X_END", 16, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG4_OTG_CRC0_WINDOWB_Y_CONTROL[] = {
	 { "OTG_CRC0_WINDOWB_Y_START", 0, 14, &umr_bitfield_default },
	 { "OTG_CRC0_WINDOWB_Y_END", 16, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG4_OTG_CRC0_DATA_RG[] = {
	 { "CRC0_R_CR", 0, 15, &umr_bitfield_default },
	 { "CRC0_G_Y", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG4_OTG_CRC0_DATA_B[] = {
	 { "CRC0_B_CB", 0, 15, &umr_bitfield_default },
	 { "CRC0_C", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG4_OTG_CRC1_WINDOWA_X_CONTROL[] = {
	 { "OTG_CRC1_WINDOWA_X_START", 0, 14, &umr_bitfield_default },
	 { "OTG_CRC1_WINDOWA_X_END", 16, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG4_OTG_CRC1_WINDOWA_Y_CONTROL[] = {
	 { "OTG_CRC1_WINDOWA_Y_START", 0, 14, &umr_bitfield_default },
	 { "OTG_CRC1_WINDOWA_Y_END", 16, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG4_OTG_CRC1_WINDOWB_X_CONTROL[] = {
	 { "OTG_CRC1_WINDOWB_X_START", 0, 14, &umr_bitfield_default },
	 { "OTG_CRC1_WINDOWB_X_END", 16, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG4_OTG_CRC1_WINDOWB_Y_CONTROL[] = {
	 { "OTG_CRC1_WINDOWB_Y_START", 0, 14, &umr_bitfield_default },
	 { "OTG_CRC1_WINDOWB_Y_END", 16, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG4_OTG_CRC1_DATA_RG[] = {
	 { "CRC1_R_CR", 0, 15, &umr_bitfield_default },
	 { "CRC1_G_Y", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG4_OTG_CRC1_DATA_B[] = {
	 { "CRC1_B_CB", 0, 15, &umr_bitfield_default },
	 { "CRC1_C", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG4_OTG_CRC2_DATA_RG[] = {
	 { "CRC2_R_CR", 0, 15, &umr_bitfield_default },
	 { "CRC2_G_Y", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG4_OTG_CRC2_DATA_B[] = {
	 { "CRC2_B_CB", 0, 15, &umr_bitfield_default },
	 { "CRC2_C", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG4_OTG_CRC3_DATA_RG[] = {
	 { "CRC3_R_CR", 0, 15, &umr_bitfield_default },
	 { "CRC3_G_Y", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG4_OTG_CRC3_DATA_B[] = {
	 { "CRC3_B_CB", 0, 15, &umr_bitfield_default },
	 { "CRC3_C", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG4_OTG_CRC_SIG_RED_GREEN_MASK[] = {
	 { "OTG_CRC_SIG_RED_MASK", 0, 15, &umr_bitfield_default },
	 { "OTG_CRC_SIG_GREEN_MASK", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG4_OTG_CRC_SIG_BLUE_CONTROL_MASK[] = {
	 { "OTG_CRC_SIG_BLUE_MASK", 0, 15, &umr_bitfield_default },
	 { "OTG_CRC_SIG_CONTROL_MASK", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG4_OTG_STATIC_SCREEN_CONTROL[] = {
	 { "OTG_STATIC_SCREEN_EVENT_MASK", 0, 15, &umr_bitfield_default },
	 { "OTG_STATIC_SCREEN_FRAME_COUNT", 16, 23, &umr_bitfield_default },
	 { "OTG_CPU_SS_INT_ENABLE", 24, 24, &umr_bitfield_default },
	 { "OTG_SS_STATUS", 25, 25, &umr_bitfield_default },
	 { "OTG_CPU_SS_INT_STATUS", 26, 26, &umr_bitfield_default },
	 { "OTG_CPU_SS_INT_CLEAR", 27, 27, &umr_bitfield_default },
	 { "OTG_CPU_SS_INT_TYPE", 28, 28, &umr_bitfield_default },
	 { "OTG_STATIC_SCREEN_OVERRIDE", 30, 30, &umr_bitfield_default },
	 { "OTG_STATIC_SCREEN_OVERRIDE_VALUE", 31, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG4_OTG_3D_STRUCTURE_CONTROL[] = {
	 { "OTG_3D_STRUCTURE_EN", 0, 0, &umr_bitfield_default },
	 { "OTG_3D_STRUCTURE_V_UPDATE_MODE", 8, 9, &umr_bitfield_default },
	 { "OTG_3D_STRUCTURE_STEREO_SEL_OVR", 12, 12, &umr_bitfield_default },
	 { "OTG_3D_STRUCTURE_F_COUNT_RESET", 16, 16, &umr_bitfield_default },
	 { "OTG_3D_STRUCTURE_F_COUNT_RESET_PENDING", 17, 17, &umr_bitfield_default },
	 { "OTG_3D_STRUCTURE_F_COUNT", 18, 19, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG4_OTG_GSL_VSYNC_GAP[] = {
	 { "OTG_GSL_VSYNC_GAP_LIMIT", 0, 7, &umr_bitfield_default },
	 { "OTG_GSL_VSYNC_GAP_DELAY", 8, 15, &umr_bitfield_default },
	 { "OTG_GSL_VSYNC_GAP_SOURCE_SEL", 16, 16, &umr_bitfield_default },
	 { "OTG_GSL_VSYNC_GAP_MODE", 17, 18, &umr_bitfield_default },
	 { "OTG_GSL_VSYNC_GAP_CLEAR", 19, 19, &umr_bitfield_default },
	 { "OTG_GSL_VSYNC_GAP_OCCURRED", 20, 20, &umr_bitfield_default },
	 { "OTG_GSL_VSYNC_GAP_MASTER_FASTER", 23, 23, &umr_bitfield_default },
	 { "OTG_GSL_VSYNC_GAP", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG4_OTG_MASTER_UPDATE_MODE[] = {
	 { "MASTER_UPDATE_INTERLACED_MODE", 0, 1, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG4_OTG_CLOCK_CONTROL[] = {
	 { "OTG_CLOCK_EN", 0, 0, &umr_bitfield_default },
	 { "OTG_CLOCK_GATE_DIS", 1, 1, &umr_bitfield_default },
	 { "OTG_SOFT_RESET", 4, 4, &umr_bitfield_default },
	 { "OTG_CLOCK_ON", 8, 8, &umr_bitfield_default },
	 { "OTG_BUSY", 16, 16, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG4_OTG_VSTARTUP_PARAM[] = {
	 { "VSTARTUP_START", 0, 9, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG4_OTG_VUPDATE_PARAM[] = {
	 { "VUPDATE_OFFSET", 0, 15, &umr_bitfield_default },
	 { "VUPDATE_WIDTH", 16, 25, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG4_OTG_VREADY_PARAM[] = {
	 { "VREADY_OFFSET", 0, 15, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG4_OTG_GLOBAL_SYNC_STATUS[] = {
	 { "VSTARTUP_INT_EN", 0, 0, &umr_bitfield_default },
	 { "VSTARTUP_INT_TYPE", 1, 1, &umr_bitfield_default },
	 { "VSTARTUP_EVENT_OCCURRED", 2, 2, &umr_bitfield_default },
	 { "VSTARTUP_INT_STATUS", 3, 3, &umr_bitfield_default },
	 { "VSTARTUP_EVENT_CLEAR", 4, 4, &umr_bitfield_default },
	 { "VUPDATE_INT_EN", 5, 5, &umr_bitfield_default },
	 { "VUPDATE_INT_TYPE", 6, 6, &umr_bitfield_default },
	 { "VUPDATE_INT_POSITION_SEL", 7, 7, &umr_bitfield_default },
	 { "VUPDATE_EVENT_OCCURRED", 8, 8, &umr_bitfield_default },
	 { "VUPDATE_INT_STATUS", 9, 9, &umr_bitfield_default },
	 { "VUPDATE_EVENT_CLEAR", 10, 10, &umr_bitfield_default },
	 { "VUPDATE_STATUS", 11, 11, &umr_bitfield_default },
	 { "VUPDATE_NO_LOCK_INT_EN", 12, 12, &umr_bitfield_default },
	 { "VUPDATE_NO_LOCK_INT_TYPE", 13, 13, &umr_bitfield_default },
	 { "VUPDATE_NO_LOCK_EVENT_OCCURRED", 14, 14, &umr_bitfield_default },
	 { "VUPDATE_NO_LOCK_INT_STATUS", 15, 15, &umr_bitfield_default },
	 { "VUPDATE_NO_LOCK_EVENT_CLEAR", 16, 16, &umr_bitfield_default },
	 { "VUPDATE_NO_LOCK_STATUS", 17, 17, &umr_bitfield_default },
	 { "VREADY_INT_EN", 18, 18, &umr_bitfield_default },
	 { "VREADY_INT_TYPE", 19, 19, &umr_bitfield_default },
	 { "VREADY_EVENT_OCCURRED", 20, 20, &umr_bitfield_default },
	 { "VREADY_INT_STATUS", 21, 21, &umr_bitfield_default },
	 { "VREADY_EVENT_CLEAR", 22, 22, &umr_bitfield_default },
	 { "STEREO_SELECT_STATUS", 24, 24, &umr_bitfield_default },
	 { "FIELD_NUMBER_STATUS", 25, 25, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG4_OTG_MASTER_UPDATE_LOCK[] = {
	 { "OTG_MASTER_UPDATE_LOCK", 0, 0, &umr_bitfield_default },
	 { "UPDATE_LOCK_STATUS", 8, 8, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG4_OTG_GSL_CONTROL[] = {
	 { "OTG_GSL0_EN", 0, 0, &umr_bitfield_default },
	 { "OTG_GSL1_EN", 1, 1, &umr_bitfield_default },
	 { "OTG_GSL2_EN", 2, 2, &umr_bitfield_default },
	 { "OTG_GSL_MASTER_EN", 3, 3, &umr_bitfield_default },
	 { "OTG_GSL_FORCE_DELAY", 16, 20, &umr_bitfield_default },
	 { "OTG_GSL_CHECK_ALL_FIELDS", 28, 28, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG4_OTG_GSL_WINDOW_X[] = {
	 { "OTG_GSL_WINDOW_START_X", 0, 14, &umr_bitfield_default },
	 { "OTG_GSL_WINDOW_END_X", 16, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG4_OTG_GSL_WINDOW_Y[] = {
	 { "OTG_GSL_WINDOW_START_Y", 0, 14, &umr_bitfield_default },
	 { "OTG_GSL_WINDOW_END_Y", 16, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG4_OTG_VUPDATE_KEEPOUT[] = {
	 { "MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_START_OFFSET", 0, 15, &umr_bitfield_default },
	 { "MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_END_OFFSET", 16, 25, &umr_bitfield_default },
	 { "OTG_MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_EN", 31, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG4_OTG_GLOBAL_CONTROL0[] = {
	 { "OTG_MASTER_UPDATE_LOCK_HTOTAL_KEEPOUT", 0, 7, &umr_bitfield_default },
	 { "OTG_MASTER_UPDATE_LOCK_HTOTAL_KEEPOUT_EN", 8, 8, &umr_bitfield_default },
	 { "OTG_MASTER_UPDATE_LOCK_SEL", 25, 27, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG4_OTG_GLOBAL_CONTROL1[] = {
	 { "MASTER_UPDATE_LOCK_DB_X", 0, 14, &umr_bitfield_default },
	 { "MASTER_UPDATE_LOCK_DB_Y", 16, 30, &umr_bitfield_default },
	 { "MASTER_UPDATE_LOCK_DB_EN", 31, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG4_OTG_GLOBAL_CONTROL2[] = {
	 { "DIG_UPDATE_LOCATION", 0, 9, &umr_bitfield_default },
	 { "GLOBAL_UPDATE_LOCK_EN", 10, 10, &umr_bitfield_default },
	 { "MANUAL_FLOW_CONTROL_SEL", 16, 18, &umr_bitfield_default },
	 { "DCCG_VUPDATE_MODE", 31, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG4_OTG_GLOBAL_CONTROL3[] = {
	 { "MASTER_UPDATE_LOCK_DB_FIELD", 0, 1, &umr_bitfield_default },
	 { "MASTER_UPDATE_LOCK_DB_STEREO_SEL", 4, 5, &umr_bitfield_default },
	 { "MASTER_UPDATE_LOCK_DB_FIELD_STEREO_FLAG_SEL", 8, 8, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG4_OTG_TRIG_MANUAL_CONTROL[] = {
	 { "TRIG_MANUAL_CONTROL", 0, 0, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG4_OTG_MANUAL_FLOW_CONTROL[] = {
	 { "MANUAL_FLOW_CONTROL", 0, 0, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG4_OTG_RANGE_TIMING_INT_STATUS[] = {
	 { "OTG_RANGE_TIMING_UPDATE_OCCURRED", 0, 0, &umr_bitfield_default },
	 { "OTG_RANGE_TIMING_UPDATE_OCCURRED_INT", 4, 4, &umr_bitfield_default },
	 { "OTG_RANGE_TIMING_UPDATE_OCCURRED_CLEAR", 8, 8, &umr_bitfield_default },
	 { "OTG_RANGE_TIMING_UPDATE_OCCURRED_INT_MSK", 12, 12, &umr_bitfield_default },
	 { "OTG_RANGE_TIMING_UPDATE_OCCURRED_INT_TYPE", 16, 16, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG4_OTG_DRR_CONTROL[] = {
	 { "OTG_DRR_AVERAGE_FRAME", 0, 2, &umr_bitfield_default },
	 { "OTG_V_TOTAL_LAST_USED_BY_DRR", 16, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG4_OTG_REQUEST_CONTROL[] = {
	 { "OTG_REQUEST_MODE_FOR_H_DUPLICATE", 0, 0, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG4_OTG_SPARE_REGISTER[] = {
	 { "OTG_SPARE_REG", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG5_OTG_H_TOTAL[] = {
	 { "OTG_H_TOTAL", 0, 14, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG5_OTG_H_BLANK_START_END[] = {
	 { "OTG_H_BLANK_START", 0, 14, &umr_bitfield_default },
	 { "OTG_H_BLANK_END", 16, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG5_OTG_H_SYNC_A[] = {
	 { "OTG_H_SYNC_A_START", 0, 14, &umr_bitfield_default },
	 { "OTG_H_SYNC_A_END", 16, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG5_OTG_H_SYNC_A_CNTL[] = {
	 { "OTG_H_SYNC_A_POL", 0, 0, &umr_bitfield_default },
	 { "OTG_COMP_SYNC_A_EN", 16, 16, &umr_bitfield_default },
	 { "OTG_H_SYNC_A_CUTOFF", 17, 17, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG5_OTG_H_TIMING_CNTL[] = {
	 { "OTG_H_TIMING_DIV_BY2", 0, 0, &umr_bitfield_default },
	 { "OTG_H_TIMING_DIV_BY2_UPDATE_MODE", 8, 8, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG5_OTG_V_TOTAL[] = {
	 { "OTG_V_TOTAL", 0, 14, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG5_OTG_V_TOTAL_MIN[] = {
	 { "OTG_V_TOTAL_MIN", 0, 14, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG5_OTG_V_TOTAL_MAX[] = {
	 { "OTG_V_TOTAL_MAX", 0, 14, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG5_OTG_V_TOTAL_MID[] = {
	 { "OTG_V_TOTAL_MID", 0, 14, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG5_OTG_V_TOTAL_CONTROL[] = {
	 { "OTG_V_TOTAL_MIN_SEL", 0, 0, &umr_bitfield_default },
	 { "OTG_V_TOTAL_MAX_SEL", 1, 1, &umr_bitfield_default },
	 { "OTG_VTOTAL_MID_REPLACING_MAX_EN", 2, 2, &umr_bitfield_default },
	 { "OTG_VTOTAL_MID_REPLACING_MIN_EN", 3, 3, &umr_bitfield_default },
	 { "OTG_FORCE_LOCK_ON_EVENT", 4, 4, &umr_bitfield_default },
	 { "OTG_SET_V_TOTAL_MIN_MASK_EN", 7, 7, &umr_bitfield_default },
	 { "OTG_VTOTAL_MID_FRAME_NUM", 8, 15, &umr_bitfield_default },
	 { "OTG_SET_V_TOTAL_MIN_MASK", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG5_OTG_V_TOTAL_INT_STATUS[] = {
	 { "OTG_SET_V_TOTAL_MIN_EVENT_OCCURED", 0, 0, &umr_bitfield_default },
	 { "OTG_SET_V_TOTAL_MIN_EVENT_OCCURED_INT", 4, 4, &umr_bitfield_default },
	 { "OTG_SET_V_TOTAL_MIN_EVENT_OCCURED_ACK", 8, 8, &umr_bitfield_default },
	 { "OTG_SET_V_TOTAL_MIN_EVENT_OCCURED_MSK", 12, 12, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG5_OTG_VSYNC_NOM_INT_STATUS[] = {
	 { "OTG_VSYNC_NOM", 0, 0, &umr_bitfield_default },
	 { "OTG_VSYNC_NOM_INT_CLEAR", 4, 4, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG5_OTG_V_BLANK_START_END[] = {
	 { "OTG_V_BLANK_START", 0, 14, &umr_bitfield_default },
	 { "OTG_V_BLANK_END", 16, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG5_OTG_V_SYNC_A[] = {
	 { "OTG_V_SYNC_A_START", 0, 14, &umr_bitfield_default },
	 { "OTG_V_SYNC_A_END", 16, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG5_OTG_V_SYNC_A_CNTL[] = {
	 { "OTG_V_SYNC_A_POL", 0, 0, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG5_OTG_TRIGA_CNTL[] = {
	 { "OTG_TRIGA_SOURCE_SELECT", 0, 4, &umr_bitfield_default },
	 { "OTG_TRIGA_SOURCE_PIPE_SELECT", 5, 7, &umr_bitfield_default },
	 { "OTG_TRIGA_POLARITY_SELECT", 8, 10, &umr_bitfield_default },
	 { "OTG_TRIGA_RESYNC_BYPASS_EN", 11, 11, &umr_bitfield_default },
	 { "OTG_TRIGA_INPUT_STATUS", 12, 12, &umr_bitfield_default },
	 { "OTG_TRIGA_POLARITY_STATUS", 13, 13, &umr_bitfield_default },
	 { "OTG_TRIGA_OCCURRED", 14, 14, &umr_bitfield_default },
	 { "OTG_TRIGA_RISING_EDGE_DETECT_CNTL", 16, 17, &umr_bitfield_default },
	 { "OTG_TRIGA_FALLING_EDGE_DETECT_CNTL", 18, 19, &umr_bitfield_default },
	 { "OTG_TRIGA_FREQUENCY_SELECT", 20, 21, &umr_bitfield_default },
	 { "OTG_TRIGA_DELAY", 24, 28, &umr_bitfield_default },
	 { "OTG_TRIGA_CLEAR", 31, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG5_OTG_TRIGA_MANUAL_TRIG[] = {
	 { "OTG_TRIGA_MANUAL_TRIG", 0, 0, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG5_OTG_TRIGB_CNTL[] = {
	 { "OTG_TRIGB_SOURCE_SELECT", 0, 4, &umr_bitfield_default },
	 { "OTG_TRIGB_SOURCE_PIPE_SELECT", 5, 7, &umr_bitfield_default },
	 { "OTG_TRIGB_POLARITY_SELECT", 8, 10, &umr_bitfield_default },
	 { "OTG_TRIGB_RESYNC_BYPASS_EN", 11, 11, &umr_bitfield_default },
	 { "OTG_TRIGB_INPUT_STATUS", 12, 12, &umr_bitfield_default },
	 { "OTG_TRIGB_POLARITY_STATUS", 13, 13, &umr_bitfield_default },
	 { "OTG_TRIGB_OCCURRED", 14, 14, &umr_bitfield_default },
	 { "OTG_TRIGB_RISING_EDGE_DETECT_CNTL", 16, 17, &umr_bitfield_default },
	 { "OTG_TRIGB_FALLING_EDGE_DETECT_CNTL", 18, 19, &umr_bitfield_default },
	 { "OTG_TRIGB_FREQUENCY_SELECT", 20, 21, &umr_bitfield_default },
	 { "OTG_TRIGB_DELAY", 24, 28, &umr_bitfield_default },
	 { "OTG_TRIGB_CLEAR", 31, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG5_OTG_TRIGB_MANUAL_TRIG[] = {
	 { "OTG_TRIGB_MANUAL_TRIG", 0, 0, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG5_OTG_FORCE_COUNT_NOW_CNTL[] = {
	 { "OTG_FORCE_COUNT_NOW_MODE", 0, 1, &umr_bitfield_default },
	 { "OTG_FORCE_COUNT_NOW_CHECK", 4, 4, &umr_bitfield_default },
	 { "OTG_FORCE_COUNT_NOW_TRIG_SEL", 8, 8, &umr_bitfield_default },
	 { "OTG_FORCE_COUNT_NOW_OCCURRED", 16, 16, &umr_bitfield_default },
	 { "OTG_FORCE_COUNT_NOW_CLEAR", 24, 24, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG5_OTG_FLOW_CONTROL[] = {
	 { "OTG_FLOW_CONTROL_SOURCE_SELECT", 0, 4, &umr_bitfield_default },
	 { "OTG_FLOW_CONTROL_POLARITY", 8, 8, &umr_bitfield_default },
	 { "OTG_FLOW_CONTROL_GRANULARITY", 16, 16, &umr_bitfield_default },
	 { "OTG_FLOW_CONTROL_INPUT_STATUS", 24, 24, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG5_OTG_STEREO_FORCE_NEXT_EYE[] = {
	 { "OTG_STEREO_FORCE_NEXT_EYE", 0, 1, &umr_bitfield_default },
	 { "OTG_AVSYNC_FRAME_COUNTER", 8, 15, &umr_bitfield_default },
	 { "OTG_AVSYNC_LINE_COUNTER", 16, 28, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG5_OTG_AVSYNC_COUNTER[] = {
	 { "OTG_AVSYNC_COUNTER", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG5_OTG_CONTROL[] = {
	 { "OTG_MASTER_EN", 0, 0, &umr_bitfield_default },
	 { "OTG_DISABLE_POINT_CNTL", 8, 9, &umr_bitfield_default },
	 { "OTG_START_POINT_CNTL", 12, 12, &umr_bitfield_default },
	 { "OTG_FIELD_NUMBER_CNTL", 13, 13, &umr_bitfield_default },
	 { "OTG_FIELD_NUMBER_POLARITY", 14, 14, &umr_bitfield_default },
	 { "OTG_CURRENT_MASTER_EN_STATE", 16, 16, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG5_OTG_BLANK_CONTROL[] = {
	 { "OTG_CURRENT_BLANK_STATE", 0, 0, &umr_bitfield_default },
	 { "OTG_BLANK_DATA_EN", 8, 8, &umr_bitfield_default },
	 { "OTG_BLANK_DE_MODE", 16, 16, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG5_OTG_PIPE_ABORT_CONTROL[] = {
	 { "OTG_PIPE_ABORT", 0, 0, &umr_bitfield_default },
	 { "OTG_PIPE_ABORT_DONE", 8, 8, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG5_OTG_INTERLACE_CONTROL[] = {
	 { "OTG_INTERLACE_ENABLE", 0, 0, &umr_bitfield_default },
	 { "OTG_INTERLACE_FORCE_NEXT_FIELD", 16, 17, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG5_OTG_INTERLACE_STATUS[] = {
	 { "OTG_INTERLACE_CURRENT_FIELD", 0, 0, &umr_bitfield_default },
	 { "OTG_INTERLACE_NEXT_FIELD", 1, 1, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG5_OTG_FIELD_INDICATION_CONTROL[] = {
	 { "OTG_FIELD_INDICATION_OUTPUT_POLARITY", 0, 0, &umr_bitfield_default },
	 { "OTG_FIELD_ALIGNMENT", 1, 1, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG5_OTG_PIXEL_DATA_READBACK0[] = {
	 { "OTG_PIXEL_DATA_BLUE_CB", 0, 15, &umr_bitfield_default },
	 { "OTG_PIXEL_DATA_GREEN_Y", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG5_OTG_PIXEL_DATA_READBACK1[] = {
	 { "OTG_PIXEL_DATA_RED_CR", 0, 15, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG5_OTG_STATUS[] = {
	 { "OTG_V_BLANK", 0, 0, &umr_bitfield_default },
	 { "OTG_V_ACTIVE_DISP", 1, 1, &umr_bitfield_default },
	 { "OTG_V_SYNC_A", 2, 2, &umr_bitfield_default },
	 { "OTG_V_UPDATE", 3, 3, &umr_bitfield_default },
	 { "OTG_V_BLANK_3D_STRUCTURE", 5, 5, &umr_bitfield_default },
	 { "OTG_H_BLANK", 16, 16, &umr_bitfield_default },
	 { "OTG_H_ACTIVE_DISP", 17, 17, &umr_bitfield_default },
	 { "OTG_H_SYNC_A", 18, 18, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG5_OTG_STATUS_POSITION[] = {
	 { "OTG_VERT_COUNT", 0, 14, &umr_bitfield_default },
	 { "OTG_HORZ_COUNT", 16, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG5_OTG_NOM_VERT_POSITION[] = {
	 { "OTG_VERT_COUNT_NOM", 0, 14, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG5_OTG_STATUS_FRAME_COUNT[] = {
	 { "OTG_FRAME_COUNT", 0, 23, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG5_OTG_STATUS_VF_COUNT[] = {
	 { "OTG_VF_COUNT", 0, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG5_OTG_STATUS_HV_COUNT[] = {
	 { "OTG_HV_COUNT", 0, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG5_OTG_COUNT_CONTROL[] = {
	 { "OTG_HORZ_COUNT_BY2_EN", 0, 0, &umr_bitfield_default },
	 { "OTG_HORZ_REPETITION_COUNT", 1, 4, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG5_OTG_COUNT_RESET[] = {
	 { "OTG_RESET_FRAME_COUNT", 0, 0, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG5_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE[] = {
	 { "OTG_MANUAL_FORCE_VSYNC_NEXT_LINE", 0, 0, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG5_OTG_VERT_SYNC_CONTROL[] = {
	 { "OTG_FORCE_VSYNC_NEXT_LINE_OCCURRED", 0, 0, &umr_bitfield_default },
	 { "OTG_FORCE_VSYNC_NEXT_LINE_CLEAR", 8, 8, &umr_bitfield_default },
	 { "OTG_AUTO_FORCE_VSYNC_MODE", 16, 17, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG5_OTG_STEREO_STATUS[] = {
	 { "OTG_STEREO_CURRENT_EYE", 0, 0, &umr_bitfield_default },
	 { "OTG_STEREO_SYNC_OUTPUT", 8, 8, &umr_bitfield_default },
	 { "OTG_STEREO_SYNC_SELECT", 16, 16, &umr_bitfield_default },
	 { "OTG_STEREO_EYE_FLAG", 20, 20, &umr_bitfield_default },
	 { "OTG_STEREO_FORCE_NEXT_EYE_PENDING", 24, 25, &umr_bitfield_default },
	 { "OTG_CURRENT_3D_STRUCTURE_STATE", 30, 30, &umr_bitfield_default },
	 { "OTG_CURRENT_STEREOSYNC_EN_STATE", 31, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG5_OTG_STEREO_CONTROL[] = {
	 { "OTG_STEREO_SYNC_OUTPUT_LINE_NUM", 0, 14, &umr_bitfield_default },
	 { "OTG_STEREO_SYNC_OUTPUT_POLARITY", 15, 15, &umr_bitfield_default },
	 { "OTG_STEREO_EYE_FLAG_POLARITY", 17, 17, &umr_bitfield_default },
	 { "OTG_DISABLE_STEREOSYNC_OUTPUT_FOR_DP", 18, 18, &umr_bitfield_default },
	 { "OTG_DISABLE_FIELD_NUM", 19, 19, &umr_bitfield_default },
	 { "OTG_DISABLE_V_BLANK_FOR_DP_FIX", 20, 20, &umr_bitfield_default },
	 { "OTG_STEREO_EN", 24, 24, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG5_OTG_SNAPSHOT_STATUS[] = {
	 { "OTG_SNAPSHOT_OCCURRED", 0, 0, &umr_bitfield_default },
	 { "OTG_SNAPSHOT_CLEAR", 1, 1, &umr_bitfield_default },
	 { "OTG_SNAPSHOT_MANUAL_TRIGGER", 2, 2, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG5_OTG_SNAPSHOT_CONTROL[] = {
	 { "OTG_AUTO_SNAPSHOT_TRIG_SEL", 0, 1, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG5_OTG_SNAPSHOT_POSITION[] = {
	 { "OTG_SNAPSHOT_VERT_COUNT", 0, 14, &umr_bitfield_default },
	 { "OTG_SNAPSHOT_HORZ_COUNT", 16, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG5_OTG_SNAPSHOT_FRAME[] = {
	 { "OTG_SNAPSHOT_FRAME_COUNT", 0, 23, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG5_OTG_INTERRUPT_CONTROL[] = {
	 { "OTG_SNAPSHOT_INT_MSK", 0, 0, &umr_bitfield_default },
	 { "OTG_SNAPSHOT_INT_TYPE", 1, 1, &umr_bitfield_default },
	 { "OTG_FORCE_COUNT_NOW_INT_MSK", 8, 8, &umr_bitfield_default },
	 { "OTG_FORCE_COUNT_NOW_INT_TYPE", 9, 9, &umr_bitfield_default },
	 { "OTG_FORCE_VSYNC_NEXT_LINE_INT_MSK", 16, 16, &umr_bitfield_default },
	 { "OTG_FORCE_VSYNC_NEXT_LINE_INT_TYPE", 17, 17, &umr_bitfield_default },
	 { "OTG_TRIGA_INT_MSK", 24, 24, &umr_bitfield_default },
	 { "OTG_TRIGB_INT_MSK", 25, 25, &umr_bitfield_default },
	 { "OTG_TRIGA_INT_TYPE", 26, 26, &umr_bitfield_default },
	 { "OTG_TRIGB_INT_TYPE", 27, 27, &umr_bitfield_default },
	 { "OTG_VSYNC_NOM_INT_MSK", 28, 28, &umr_bitfield_default },
	 { "OTG_VSYNC_NOM_INT_TYPE", 29, 29, &umr_bitfield_default },
	 { "OTG_GSL_VSYNC_GAP_INT_MSK", 30, 30, &umr_bitfield_default },
	 { "OTG_GSL_VSYNC_GAP_INT_TYPE", 31, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG5_OTG_UPDATE_LOCK[] = {
	 { "OTG_UPDATE_LOCK", 0, 0, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG5_OTG_DOUBLE_BUFFER_CONTROL[] = {
	 { "OTG_UPDATE_PENDING", 0, 0, &umr_bitfield_default },
	 { "OTG_H_TIMING_DIV_BY2_DB_UPDATE_PENDING", 2, 2, &umr_bitfield_default },
	 { "OTG_BLANK_DATA_EN_UPDATE_PENDING", 3, 3, &umr_bitfield_default },
	 { "OTG_RANGE_TIMING_DBUF_UPDATE_PENDING", 4, 4, &umr_bitfield_default },
	 { "OTG_TIMING_DB_UPDATE_PENDING", 5, 5, &umr_bitfield_default },
	 { "OTG_3D_CTRL_DB_UPDATE_PENDING", 6, 6, &umr_bitfield_default },
	 { "OTG_3D_STRUCTURE_EN_DB_UPDATE_PENDING", 7, 7, &umr_bitfield_default },
	 { "OTG_UPDATE_INSTANTLY", 8, 8, &umr_bitfield_default },
	 { "OTG_BLANK_DATA_DOUBLE_BUFFER_EN", 16, 16, &umr_bitfield_default },
	 { "OTG_RANGE_TIMING_DBUF_UPDATE_MODE", 24, 25, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG5_OTG_TEST_PATTERN_CONTROL[] = {
	 { "OTG_TEST_PATTERN_EN", 0, 0, &umr_bitfield_default },
	 { "OTG_TEST_PATTERN_MODE", 8, 10, &umr_bitfield_default },
	 { "OTG_TEST_PATTERN_DYNAMIC_RANGE", 16, 16, &umr_bitfield_default },
	 { "OTG_TEST_PATTERN_COLOR_FORMAT", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG5_OTG_TEST_PATTERN_PARAMETERS[] = {
	 { "OTG_TEST_PATTERN_INC0", 0, 3, &umr_bitfield_default },
	 { "OTG_TEST_PATTERN_INC1", 4, 7, &umr_bitfield_default },
	 { "OTG_TEST_PATTERN_VRES", 8, 11, &umr_bitfield_default },
	 { "OTG_TEST_PATTERN_HRES", 12, 15, &umr_bitfield_default },
	 { "OTG_TEST_PATTERN_RAMP0_OFFSET", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG5_OTG_TEST_PATTERN_COLOR[] = {
	 { "OTG_TEST_PATTERN_DATA", 0, 15, &umr_bitfield_default },
	 { "OTG_TEST_PATTERN_MASK", 16, 21, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG5_OTG_MASTER_EN[] = {
	 { "OTG_MASTER_EN", 0, 0, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG5_OTG_BLANK_DATA_COLOR[] = {
	 { "OTG_BLANK_DATA_COLOR_BLUE_CB", 0, 9, &umr_bitfield_default },
	 { "OTG_BLANK_DATA_COLOR_GREEN_Y", 10, 19, &umr_bitfield_default },
	 { "OTG_BLANK_DATA_COLOR_RED_CR", 20, 29, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG5_OTG_BLANK_DATA_COLOR_EXT[] = {
	 { "OTG_BLANK_DATA_COLOR_BLUE_CB_EXT", 0, 5, &umr_bitfield_default },
	 { "OTG_BLANK_DATA_COLOR_GREEN_Y_EXT", 8, 13, &umr_bitfield_default },
	 { "OTG_BLANK_DATA_COLOR_RED_CR_EXT", 16, 21, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG5_OTG_BLACK_COLOR[] = {
	 { "OTG_BLACK_COLOR_B_CB", 0, 9, &umr_bitfield_default },
	 { "OTG_BLACK_COLOR_G_Y", 10, 19, &umr_bitfield_default },
	 { "OTG_BLACK_COLOR_R_CR", 20, 29, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG5_OTG_BLACK_COLOR_EXT[] = {
	 { "OTG_BLACK_COLOR_B_CB_EXT", 0, 5, &umr_bitfield_default },
	 { "OTG_BLACK_COLOR_G_Y_EXT", 8, 13, &umr_bitfield_default },
	 { "OTG_BLACK_COLOR_R_CR_EXT", 16, 21, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG5_OTG_VERTICAL_INTERRUPT0_POSITION[] = {
	 { "OTG_VERTICAL_INTERRUPT0_LINE_START", 0, 14, &umr_bitfield_default },
	 { "OTG_VERTICAL_INTERRUPT0_LINE_END", 16, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG5_OTG_VERTICAL_INTERRUPT0_CONTROL[] = {
	 { "OTG_VERTICAL_INTERRUPT0_OUTPUT_POLARITY", 4, 4, &umr_bitfield_default },
	 { "OTG_VERTICAL_INTERRUPT0_INT_ENABLE", 8, 8, &umr_bitfield_default },
	 { "OTG_VERTICAL_INTERRUPT0_STATUS", 12, 12, &umr_bitfield_default },
	 { "OTG_VERTICAL_INTERRUPT0_INT_STATUS", 16, 16, &umr_bitfield_default },
	 { "OTG_VERTICAL_INTERRUPT0_CLEAR", 20, 20, &umr_bitfield_default },
	 { "OTG_VERTICAL_INTERRUPT0_INT_TYPE", 24, 24, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG5_OTG_VERTICAL_INTERRUPT1_POSITION[] = {
	 { "OTG_VERTICAL_INTERRUPT1_LINE_START", 0, 14, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG5_OTG_VERTICAL_INTERRUPT1_CONTROL[] = {
	 { "OTG_VERTICAL_INTERRUPT1_INT_ENABLE", 8, 8, &umr_bitfield_default },
	 { "OTG_VERTICAL_INTERRUPT1_STATUS", 12, 12, &umr_bitfield_default },
	 { "OTG_VERTICAL_INTERRUPT1_INT_STATUS", 16, 16, &umr_bitfield_default },
	 { "OTG_VERTICAL_INTERRUPT1_CLEAR", 20, 20, &umr_bitfield_default },
	 { "OTG_VERTICAL_INTERRUPT1_INT_TYPE", 24, 24, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG5_OTG_VERTICAL_INTERRUPT2_POSITION[] = {
	 { "OTG_VERTICAL_INTERRUPT2_LINE_START", 0, 14, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG5_OTG_VERTICAL_INTERRUPT2_CONTROL[] = {
	 { "OTG_VERTICAL_INTERRUPT2_INT_ENABLE", 8, 8, &umr_bitfield_default },
	 { "OTG_VERTICAL_INTERRUPT2_STATUS", 12, 12, &umr_bitfield_default },
	 { "OTG_VERTICAL_INTERRUPT2_INT_STATUS", 16, 16, &umr_bitfield_default },
	 { "OTG_VERTICAL_INTERRUPT2_CLEAR", 20, 20, &umr_bitfield_default },
	 { "OTG_VERTICAL_INTERRUPT2_INT_TYPE", 24, 24, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG5_OTG_CRC_CNTL[] = {
	 { "OTG_CRC_EN", 0, 0, &umr_bitfield_default },
	 { "OTG_CRC_DUAL_LINK_EN", 1, 1, &umr_bitfield_default },
	 { "OTG_CRC_DUAL_LINK_MODE", 2, 2, &umr_bitfield_default },
	 { "OTG_CRC_BLANK_ONLY", 3, 3, &umr_bitfield_default },
	 { "OTG_CRC_CONT_EN", 4, 4, &umr_bitfield_default },
	 { "OTG_CRC_CAPTURE_START_SEL", 5, 6, &umr_bitfield_default },
	 { "OTG_CRC_STEREO_MODE", 8, 9, &umr_bitfield_default },
	 { "OTG_CRC_INTERLACE_MODE", 12, 13, &umr_bitfield_default },
	 { "OTG_CRC_MULTI_STREAM_MODE", 16, 18, &umr_bitfield_default },
	 { "OTG_CRC_USE_NEW_AND_REPEATED_PIXELS", 19, 19, &umr_bitfield_default },
	 { "OTG_CRC0_SELECT", 20, 22, &umr_bitfield_default },
	 { "OTG_CRC1_SELECT", 24, 26, &umr_bitfield_default },
	 { "OTG_ONE_SHOT_CRC0_PENDING", 28, 28, &umr_bitfield_default },
	 { "OTG_ONE_SHOT_CRC1_PENDING", 29, 29, &umr_bitfield_default },
	 { "OTG_ONE_SHOT_CRC2_PENDING", 30, 30, &umr_bitfield_default },
	 { "OTG_ONE_SHOT_CRC3_PENDING", 31, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG5_OTG_CRC0_WINDOWA_X_CONTROL[] = {
	 { "OTG_CRC0_WINDOWA_X_START", 0, 14, &umr_bitfield_default },
	 { "OTG_CRC0_WINDOWA_X_END", 16, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG5_OTG_CRC0_WINDOWA_Y_CONTROL[] = {
	 { "OTG_CRC0_WINDOWA_Y_START", 0, 14, &umr_bitfield_default },
	 { "OTG_CRC0_WINDOWA_Y_END", 16, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG5_OTG_CRC0_WINDOWB_X_CONTROL[] = {
	 { "OTG_CRC0_WINDOWB_X_START", 0, 14, &umr_bitfield_default },
	 { "OTG_CRC0_WINDOWB_X_END", 16, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG5_OTG_CRC0_WINDOWB_Y_CONTROL[] = {
	 { "OTG_CRC0_WINDOWB_Y_START", 0, 14, &umr_bitfield_default },
	 { "OTG_CRC0_WINDOWB_Y_END", 16, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG5_OTG_CRC0_DATA_RG[] = {
	 { "CRC0_R_CR", 0, 15, &umr_bitfield_default },
	 { "CRC0_G_Y", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG5_OTG_CRC0_DATA_B[] = {
	 { "CRC0_B_CB", 0, 15, &umr_bitfield_default },
	 { "CRC0_C", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG5_OTG_CRC1_WINDOWA_X_CONTROL[] = {
	 { "OTG_CRC1_WINDOWA_X_START", 0, 14, &umr_bitfield_default },
	 { "OTG_CRC1_WINDOWA_X_END", 16, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG5_OTG_CRC1_WINDOWA_Y_CONTROL[] = {
	 { "OTG_CRC1_WINDOWA_Y_START", 0, 14, &umr_bitfield_default },
	 { "OTG_CRC1_WINDOWA_Y_END", 16, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG5_OTG_CRC1_WINDOWB_X_CONTROL[] = {
	 { "OTG_CRC1_WINDOWB_X_START", 0, 14, &umr_bitfield_default },
	 { "OTG_CRC1_WINDOWB_X_END", 16, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG5_OTG_CRC1_WINDOWB_Y_CONTROL[] = {
	 { "OTG_CRC1_WINDOWB_Y_START", 0, 14, &umr_bitfield_default },
	 { "OTG_CRC1_WINDOWB_Y_END", 16, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG5_OTG_CRC1_DATA_RG[] = {
	 { "CRC1_R_CR", 0, 15, &umr_bitfield_default },
	 { "CRC1_G_Y", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG5_OTG_CRC1_DATA_B[] = {
	 { "CRC1_B_CB", 0, 15, &umr_bitfield_default },
	 { "CRC1_C", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG5_OTG_CRC2_DATA_RG[] = {
	 { "CRC2_R_CR", 0, 15, &umr_bitfield_default },
	 { "CRC2_G_Y", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG5_OTG_CRC2_DATA_B[] = {
	 { "CRC2_B_CB", 0, 15, &umr_bitfield_default },
	 { "CRC2_C", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG5_OTG_CRC3_DATA_RG[] = {
	 { "CRC3_R_CR", 0, 15, &umr_bitfield_default },
	 { "CRC3_G_Y", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG5_OTG_CRC3_DATA_B[] = {
	 { "CRC3_B_CB", 0, 15, &umr_bitfield_default },
	 { "CRC3_C", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG5_OTG_CRC_SIG_RED_GREEN_MASK[] = {
	 { "OTG_CRC_SIG_RED_MASK", 0, 15, &umr_bitfield_default },
	 { "OTG_CRC_SIG_GREEN_MASK", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG5_OTG_CRC_SIG_BLUE_CONTROL_MASK[] = {
	 { "OTG_CRC_SIG_BLUE_MASK", 0, 15, &umr_bitfield_default },
	 { "OTG_CRC_SIG_CONTROL_MASK", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG5_OTG_STATIC_SCREEN_CONTROL[] = {
	 { "OTG_STATIC_SCREEN_EVENT_MASK", 0, 15, &umr_bitfield_default },
	 { "OTG_STATIC_SCREEN_FRAME_COUNT", 16, 23, &umr_bitfield_default },
	 { "OTG_CPU_SS_INT_ENABLE", 24, 24, &umr_bitfield_default },
	 { "OTG_SS_STATUS", 25, 25, &umr_bitfield_default },
	 { "OTG_CPU_SS_INT_STATUS", 26, 26, &umr_bitfield_default },
	 { "OTG_CPU_SS_INT_CLEAR", 27, 27, &umr_bitfield_default },
	 { "OTG_CPU_SS_INT_TYPE", 28, 28, &umr_bitfield_default },
	 { "OTG_STATIC_SCREEN_OVERRIDE", 30, 30, &umr_bitfield_default },
	 { "OTG_STATIC_SCREEN_OVERRIDE_VALUE", 31, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG5_OTG_3D_STRUCTURE_CONTROL[] = {
	 { "OTG_3D_STRUCTURE_EN", 0, 0, &umr_bitfield_default },
	 { "OTG_3D_STRUCTURE_V_UPDATE_MODE", 8, 9, &umr_bitfield_default },
	 { "OTG_3D_STRUCTURE_STEREO_SEL_OVR", 12, 12, &umr_bitfield_default },
	 { "OTG_3D_STRUCTURE_F_COUNT_RESET", 16, 16, &umr_bitfield_default },
	 { "OTG_3D_STRUCTURE_F_COUNT_RESET_PENDING", 17, 17, &umr_bitfield_default },
	 { "OTG_3D_STRUCTURE_F_COUNT", 18, 19, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG5_OTG_GSL_VSYNC_GAP[] = {
	 { "OTG_GSL_VSYNC_GAP_LIMIT", 0, 7, &umr_bitfield_default },
	 { "OTG_GSL_VSYNC_GAP_DELAY", 8, 15, &umr_bitfield_default },
	 { "OTG_GSL_VSYNC_GAP_SOURCE_SEL", 16, 16, &umr_bitfield_default },
	 { "OTG_GSL_VSYNC_GAP_MODE", 17, 18, &umr_bitfield_default },
	 { "OTG_GSL_VSYNC_GAP_CLEAR", 19, 19, &umr_bitfield_default },
	 { "OTG_GSL_VSYNC_GAP_OCCURRED", 20, 20, &umr_bitfield_default },
	 { "OTG_GSL_VSYNC_GAP_MASTER_FASTER", 23, 23, &umr_bitfield_default },
	 { "OTG_GSL_VSYNC_GAP", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG5_OTG_MASTER_UPDATE_MODE[] = {
	 { "MASTER_UPDATE_INTERLACED_MODE", 0, 1, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG5_OTG_CLOCK_CONTROL[] = {
	 { "OTG_CLOCK_EN", 0, 0, &umr_bitfield_default },
	 { "OTG_CLOCK_GATE_DIS", 1, 1, &umr_bitfield_default },
	 { "OTG_SOFT_RESET", 4, 4, &umr_bitfield_default },
	 { "OTG_CLOCK_ON", 8, 8, &umr_bitfield_default },
	 { "OTG_BUSY", 16, 16, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG5_OTG_VSTARTUP_PARAM[] = {
	 { "VSTARTUP_START", 0, 9, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG5_OTG_VUPDATE_PARAM[] = {
	 { "VUPDATE_OFFSET", 0, 15, &umr_bitfield_default },
	 { "VUPDATE_WIDTH", 16, 25, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG5_OTG_VREADY_PARAM[] = {
	 { "VREADY_OFFSET", 0, 15, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG5_OTG_GLOBAL_SYNC_STATUS[] = {
	 { "VSTARTUP_INT_EN", 0, 0, &umr_bitfield_default },
	 { "VSTARTUP_INT_TYPE", 1, 1, &umr_bitfield_default },
	 { "VSTARTUP_EVENT_OCCURRED", 2, 2, &umr_bitfield_default },
	 { "VSTARTUP_INT_STATUS", 3, 3, &umr_bitfield_default },
	 { "VSTARTUP_EVENT_CLEAR", 4, 4, &umr_bitfield_default },
	 { "VUPDATE_INT_EN", 5, 5, &umr_bitfield_default },
	 { "VUPDATE_INT_TYPE", 6, 6, &umr_bitfield_default },
	 { "VUPDATE_INT_POSITION_SEL", 7, 7, &umr_bitfield_default },
	 { "VUPDATE_EVENT_OCCURRED", 8, 8, &umr_bitfield_default },
	 { "VUPDATE_INT_STATUS", 9, 9, &umr_bitfield_default },
	 { "VUPDATE_EVENT_CLEAR", 10, 10, &umr_bitfield_default },
	 { "VUPDATE_STATUS", 11, 11, &umr_bitfield_default },
	 { "VUPDATE_NO_LOCK_INT_EN", 12, 12, &umr_bitfield_default },
	 { "VUPDATE_NO_LOCK_INT_TYPE", 13, 13, &umr_bitfield_default },
	 { "VUPDATE_NO_LOCK_EVENT_OCCURRED", 14, 14, &umr_bitfield_default },
	 { "VUPDATE_NO_LOCK_INT_STATUS", 15, 15, &umr_bitfield_default },
	 { "VUPDATE_NO_LOCK_EVENT_CLEAR", 16, 16, &umr_bitfield_default },
	 { "VUPDATE_NO_LOCK_STATUS", 17, 17, &umr_bitfield_default },
	 { "VREADY_INT_EN", 18, 18, &umr_bitfield_default },
	 { "VREADY_INT_TYPE", 19, 19, &umr_bitfield_default },
	 { "VREADY_EVENT_OCCURRED", 20, 20, &umr_bitfield_default },
	 { "VREADY_INT_STATUS", 21, 21, &umr_bitfield_default },
	 { "VREADY_EVENT_CLEAR", 22, 22, &umr_bitfield_default },
	 { "STEREO_SELECT_STATUS", 24, 24, &umr_bitfield_default },
	 { "FIELD_NUMBER_STATUS", 25, 25, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG5_OTG_MASTER_UPDATE_LOCK[] = {
	 { "OTG_MASTER_UPDATE_LOCK", 0, 0, &umr_bitfield_default },
	 { "UPDATE_LOCK_STATUS", 8, 8, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG5_OTG_GSL_CONTROL[] = {
	 { "OTG_GSL0_EN", 0, 0, &umr_bitfield_default },
	 { "OTG_GSL1_EN", 1, 1, &umr_bitfield_default },
	 { "OTG_GSL2_EN", 2, 2, &umr_bitfield_default },
	 { "OTG_GSL_MASTER_EN", 3, 3, &umr_bitfield_default },
	 { "OTG_GSL_FORCE_DELAY", 16, 20, &umr_bitfield_default },
	 { "OTG_GSL_CHECK_ALL_FIELDS", 28, 28, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG5_OTG_GSL_WINDOW_X[] = {
	 { "OTG_GSL_WINDOW_START_X", 0, 14, &umr_bitfield_default },
	 { "OTG_GSL_WINDOW_END_X", 16, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG5_OTG_GSL_WINDOW_Y[] = {
	 { "OTG_GSL_WINDOW_START_Y", 0, 14, &umr_bitfield_default },
	 { "OTG_GSL_WINDOW_END_Y", 16, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG5_OTG_VUPDATE_KEEPOUT[] = {
	 { "MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_START_OFFSET", 0, 15, &umr_bitfield_default },
	 { "MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_END_OFFSET", 16, 25, &umr_bitfield_default },
	 { "OTG_MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_EN", 31, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG5_OTG_GLOBAL_CONTROL0[] = {
	 { "OTG_MASTER_UPDATE_LOCK_HTOTAL_KEEPOUT", 0, 7, &umr_bitfield_default },
	 { "OTG_MASTER_UPDATE_LOCK_HTOTAL_KEEPOUT_EN", 8, 8, &umr_bitfield_default },
	 { "OTG_MASTER_UPDATE_LOCK_SEL", 25, 27, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG5_OTG_GLOBAL_CONTROL1[] = {
	 { "MASTER_UPDATE_LOCK_DB_X", 0, 14, &umr_bitfield_default },
	 { "MASTER_UPDATE_LOCK_DB_Y", 16, 30, &umr_bitfield_default },
	 { "MASTER_UPDATE_LOCK_DB_EN", 31, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG5_OTG_GLOBAL_CONTROL2[] = {
	 { "DIG_UPDATE_LOCATION", 0, 9, &umr_bitfield_default },
	 { "GLOBAL_UPDATE_LOCK_EN", 10, 10, &umr_bitfield_default },
	 { "MANUAL_FLOW_CONTROL_SEL", 16, 18, &umr_bitfield_default },
	 { "DCCG_VUPDATE_MODE", 31, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG5_OTG_GLOBAL_CONTROL3[] = {
	 { "MASTER_UPDATE_LOCK_DB_FIELD", 0, 1, &umr_bitfield_default },
	 { "MASTER_UPDATE_LOCK_DB_STEREO_SEL", 4, 5, &umr_bitfield_default },
	 { "MASTER_UPDATE_LOCK_DB_FIELD_STEREO_FLAG_SEL", 8, 8, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG5_OTG_TRIG_MANUAL_CONTROL[] = {
	 { "TRIG_MANUAL_CONTROL", 0, 0, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG5_OTG_MANUAL_FLOW_CONTROL[] = {
	 { "MANUAL_FLOW_CONTROL", 0, 0, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG5_OTG_RANGE_TIMING_INT_STATUS[] = {
	 { "OTG_RANGE_TIMING_UPDATE_OCCURRED", 0, 0, &umr_bitfield_default },
	 { "OTG_RANGE_TIMING_UPDATE_OCCURRED_INT", 4, 4, &umr_bitfield_default },
	 { "OTG_RANGE_TIMING_UPDATE_OCCURRED_CLEAR", 8, 8, &umr_bitfield_default },
	 { "OTG_RANGE_TIMING_UPDATE_OCCURRED_INT_MSK", 12, 12, &umr_bitfield_default },
	 { "OTG_RANGE_TIMING_UPDATE_OCCURRED_INT_TYPE", 16, 16, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG5_OTG_DRR_CONTROL[] = {
	 { "OTG_DRR_AVERAGE_FRAME", 0, 2, &umr_bitfield_default },
	 { "OTG_V_TOTAL_LAST_USED_BY_DRR", 16, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG5_OTG_REQUEST_CONTROL[] = {
	 { "OTG_REQUEST_MODE_FOR_H_DUPLICATE", 0, 0, &umr_bitfield_default },
};
static struct umr_bitfield mmOTG5_OTG_SPARE_REGISTER[] = {
	 { "OTG_SPARE_REG", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDWB_SOURCE_SELECT[] = {
	 { "OPTC_DWB0_SOURCE_SELECT", 0, 2, &umr_bitfield_default },
	 { "OPTC_DWB1_SOURCE_SELECT", 3, 5, &umr_bitfield_default },
};
static struct umr_bitfield mmGSL_SOURCE_SELECT[] = {
	 { "GSL0_READY_SOURCE_SEL", 0, 2, &umr_bitfield_default },
	 { "GSL1_READY_SOURCE_SEL", 4, 6, &umr_bitfield_default },
	 { "GSL2_READY_SOURCE_SEL", 8, 10, &umr_bitfield_default },
	 { "GSL_TIMING_SYNC_SEL", 16, 18, &umr_bitfield_default },
};
static struct umr_bitfield mmOPTC_CLOCK_CONTROL[] = {
	 { "OPTC_DISPCLK_R_GATE_DIS", 0, 0, &umr_bitfield_default },
	 { "OPTC_DISPCLK_R_CLOCK_ON", 1, 1, &umr_bitfield_default },
	 { "OPTC_TEST_CLK_SEL", 8, 11, &umr_bitfield_default },
};
static struct umr_bitfield mmOPTC_MISC_SPARE_REGISTER[] = {
	 { "OPTC_MISC_SPARE_REG", 0, 7, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_PERFMON18_PERFCOUNTER_CNTL[] = {
	 { "PERFCOUNTER_EVENT_SEL", 0, 8, &umr_bitfield_default },
	 { "PERFCOUNTER_CVALUE_SEL", 9, 11, &umr_bitfield_default },
	 { "PERFCOUNTER_INC_MODE", 12, 14, &umr_bitfield_default },
	 { "PERFCOUNTER_HW_CNTL_SEL", 15, 15, &umr_bitfield_default },
	 { "PERFCOUNTER_RUNEN_MODE", 16, 16, &umr_bitfield_default },
	 { "PERFCOUNTER_CNTOFF_START_DIS", 22, 22, &umr_bitfield_default },
	 { "PERFCOUNTER_RESTART_EN", 23, 23, &umr_bitfield_default },
	 { "PERFCOUNTER_INT_EN", 24, 24, &umr_bitfield_default },
	 { "PERFCOUNTER_OFF_MASK", 25, 25, &umr_bitfield_default },
	 { "PERFCOUNTER_ACTIVE", 26, 26, &umr_bitfield_default },
	 { "PERFCOUNTER_CNTL_SEL", 29, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_PERFMON18_PERFCOUNTER_CNTL2[] = {
	 { "PERFCOUNTER_COUNTED_VALUE_TYPE", 0, 1, &umr_bitfield_default },
	 { "PERFCOUNTER_HW_STOP1_SEL", 2, 2, &umr_bitfield_default },
	 { "PERFCOUNTER_HW_STOP2_SEL", 3, 3, &umr_bitfield_default },
	 { "PERFCOUNTER_CNTOFF_SEL", 8, 13, &umr_bitfield_default },
	 { "PERFCOUNTER_CNTL2_SEL", 29, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_PERFMON18_PERFCOUNTER_STATE[] = {
	 { "PERFCOUNTER_CNT0_STATE", 0, 1, &umr_bitfield_default },
	 { "PERFCOUNTER_STATE_SEL0", 2, 2, &umr_bitfield_default },
	 { "PERFCOUNTER_CNT1_STATE", 4, 5, &umr_bitfield_default },
	 { "PERFCOUNTER_STATE_SEL1", 6, 6, &umr_bitfield_default },
	 { "PERFCOUNTER_CNT2_STATE", 8, 9, &umr_bitfield_default },
	 { "PERFCOUNTER_STATE_SEL2", 10, 10, &umr_bitfield_default },
	 { "PERFCOUNTER_CNT3_STATE", 12, 13, &umr_bitfield_default },
	 { "PERFCOUNTER_STATE_SEL3", 14, 14, &umr_bitfield_default },
	 { "PERFCOUNTER_CNT4_STATE", 16, 17, &umr_bitfield_default },
	 { "PERFCOUNTER_STATE_SEL4", 18, 18, &umr_bitfield_default },
	 { "PERFCOUNTER_CNT5_STATE", 20, 21, &umr_bitfield_default },
	 { "PERFCOUNTER_STATE_SEL5", 22, 22, &umr_bitfield_default },
	 { "PERFCOUNTER_CNT6_STATE", 24, 25, &umr_bitfield_default },
	 { "PERFCOUNTER_STATE_SEL6", 26, 26, &umr_bitfield_default },
	 { "PERFCOUNTER_CNT7_STATE", 28, 29, &umr_bitfield_default },
	 { "PERFCOUNTER_STATE_SEL7", 30, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_PERFMON18_PERFMON_CNTL[] = {
	 { "PERFMON_STATE", 0, 1, &umr_bitfield_default },
	 { "PERFMON_RPT_COUNT", 8, 27, &umr_bitfield_default },
	 { "PERFMON_CNTOFF_AND_OR", 28, 28, &umr_bitfield_default },
	 { "PERFMON_CNTOFF_INT_EN", 29, 29, &umr_bitfield_default },
	 { "PERFMON_CNTOFF_INT_STATUS", 30, 30, &umr_bitfield_default },
	 { "PERFMON_CNTOFF_INT_ACK", 31, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_PERFMON18_PERFMON_CNTL2[] = {
	 { "PERFMON_CNTOFF_INT_TYPE", 0, 0, &umr_bitfield_default },
	 { "PERFMON_CLK_ENABLE", 1, 1, &umr_bitfield_default },
	 { "PERFMON_RUN_ENABLE_START_SEL", 2, 9, &umr_bitfield_default },
	 { "PERFMON_RUN_ENABLE_STOP_SEL", 10, 17, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_PERFMON18_PERFMON_CVALUE_INT_MISC[] = {
	 { "PERFCOUNTER_INT0_STATUS", 0, 0, &umr_bitfield_default },
	 { "PERFCOUNTER_INT1_STATUS", 1, 1, &umr_bitfield_default },
	 { "PERFCOUNTER_INT2_STATUS", 2, 2, &umr_bitfield_default },
	 { "PERFCOUNTER_INT3_STATUS", 3, 3, &umr_bitfield_default },
	 { "PERFCOUNTER_INT4_STATUS", 4, 4, &umr_bitfield_default },
	 { "PERFCOUNTER_INT5_STATUS", 5, 5, &umr_bitfield_default },
	 { "PERFCOUNTER_INT6_STATUS", 6, 6, &umr_bitfield_default },
	 { "PERFCOUNTER_INT7_STATUS", 7, 7, &umr_bitfield_default },
	 { "PERFCOUNTER_INT0_ACK", 8, 8, &umr_bitfield_default },
	 { "PERFCOUNTER_INT1_ACK", 9, 9, &umr_bitfield_default },
	 { "PERFCOUNTER_INT2_ACK", 10, 10, &umr_bitfield_default },
	 { "PERFCOUNTER_INT3_ACK", 11, 11, &umr_bitfield_default },
	 { "PERFCOUNTER_INT4_ACK", 12, 12, &umr_bitfield_default },
	 { "PERFCOUNTER_INT5_ACK", 13, 13, &umr_bitfield_default },
	 { "PERFCOUNTER_INT6_ACK", 14, 14, &umr_bitfield_default },
	 { "PERFCOUNTER_INT7_ACK", 15, 15, &umr_bitfield_default },
	 { "PERFMON_CVALUE_HI", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_PERFMON18_PERFMON_CVALUE_LOW[] = {
	 { "PERFMON_CVALUE_LOW", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_PERFMON18_PERFMON_HI[] = {
	 { "PERFMON_HI", 0, 15, &umr_bitfield_default },
	 { "PERFMON_READ_SEL", 29, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_PERFMON18_PERFMON_LOW[] = {
	 { "PERFMON_LOW", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDAC_ENABLE[] = {
	 { "DAC_ENABLE", 0, 0, &umr_bitfield_default },
	 { "DAC_RESYNC_FIFO_ENABLE", 1, 1, &umr_bitfield_default },
	 { "DAC_RESYNC_FIFO_POINTER_SKEW", 2, 3, &umr_bitfield_default },
	 { "DAC_RESYNC_FIFO_ERROR", 4, 4, &umr_bitfield_default },
	 { "DAC_RESYNC_FIFO_ERROR_ACK", 5, 5, &umr_bitfield_default },
	 { "DAC_RESYNC_FIFO_TVOUT_SIM", 8, 8, &umr_bitfield_default },
};
static struct umr_bitfield mmDAC_SOURCE_SELECT[] = {
	 { "DAC_SOURCE_SELECT", 0, 2, &umr_bitfield_default },
	 { "DAC_TV_SELECT", 3, 3, &umr_bitfield_default },
};
static struct umr_bitfield mmDAC_CRC_EN[] = {
	 { "DAC_CRC_EN", 0, 0, &umr_bitfield_default },
	 { "DAC_CRC_CONT_EN", 16, 16, &umr_bitfield_default },
};
static struct umr_bitfield mmDAC_CRC_CONTROL[] = {
	 { "DAC_CRC_FIELD", 0, 0, &umr_bitfield_default },
	 { "DAC_CRC_ONLY_BLANKB", 8, 8, &umr_bitfield_default },
};
static struct umr_bitfield mmDAC_CRC_SIG_RGB_MASK[] = {
	 { "DAC_CRC_SIG_BLUE_MASK", 0, 9, &umr_bitfield_default },
	 { "DAC_CRC_SIG_GREEN_MASK", 10, 19, &umr_bitfield_default },
	 { "DAC_CRC_SIG_RED_MASK", 20, 29, &umr_bitfield_default },
};
static struct umr_bitfield mmDAC_CRC_SIG_CONTROL_MASK[] = {
	 { "DAC_CRC_SIG_CONTROL_MASK", 0, 5, &umr_bitfield_default },
};
static struct umr_bitfield mmDAC_CRC_SIG_RGB[] = {
	 { "DAC_CRC_SIG_BLUE", 0, 9, &umr_bitfield_default },
	 { "DAC_CRC_SIG_GREEN", 10, 19, &umr_bitfield_default },
	 { "DAC_CRC_SIG_RED", 20, 29, &umr_bitfield_default },
};
static struct umr_bitfield mmDAC_CRC_SIG_CONTROL[] = {
	 { "DAC_CRC_SIG_CONTROL", 0, 5, &umr_bitfield_default },
};
static struct umr_bitfield mmDAC_SYNC_TRISTATE_CONTROL[] = {
	 { "DAC_HSYNCA_TRISTATE", 0, 0, &umr_bitfield_default },
	 { "DAC_VSYNCA_TRISTATE", 8, 8, &umr_bitfield_default },
	 { "DAC_SYNCA_TRISTATE", 16, 16, &umr_bitfield_default },
};
static struct umr_bitfield mmDAC_STEREOSYNC_SELECT[] = {
	 { "DAC_STEREOSYNC_SELECT", 0, 2, &umr_bitfield_default },
};
static struct umr_bitfield mmDAC_AUTODETECT_CONTROL[] = {
	 { "DAC_AUTODETECT_MODE", 0, 1, &umr_bitfield_default },
	 { "DAC_AUTODETECT_FRAME_TIME_COUNTER", 8, 15, &umr_bitfield_default },
	 { "DAC_AUTODETECT_CHECK_MASK", 16, 18, &umr_bitfield_default },
};
static struct umr_bitfield mmDAC_AUTODETECT_CONTROL2[] = {
	 { "DAC_AUTODETECT_POWERUP_COUNTER", 0, 7, &umr_bitfield_default },
	 { "DAC_AUTODETECT_TESTMODE", 8, 8, &umr_bitfield_default },
};
static struct umr_bitfield mmDAC_AUTODETECT_CONTROL3[] = {
	 { "DAC_AUTODET_COMPARATOR_IN_DELAY", 0, 7, &umr_bitfield_default },
	 { "DAC_AUTODET_COMPARATOR_OUT_DELAY", 8, 15, &umr_bitfield_default },
};
static struct umr_bitfield mmDAC_AUTODETECT_STATUS[] = {
	 { "DAC_AUTODETECT_STATUS", 0, 0, &umr_bitfield_default },
	 { "DAC_AUTODETECT_CONNECT", 4, 4, &umr_bitfield_default },
	 { "DAC_AUTODETECT_RED_SENSE", 8, 9, &umr_bitfield_default },
	 { "DAC_AUTODETECT_GREEN_SENSE", 16, 17, &umr_bitfield_default },
	 { "DAC_AUTODETECT_BLUE_SENSE", 24, 25, &umr_bitfield_default },
};
static struct umr_bitfield mmDAC_AUTODETECT_INT_CONTROL[] = {
	 { "DAC_AUTODETECT_ACK", 0, 0, &umr_bitfield_default },
	 { "DAC_AUTODETECT_INT_ENABLE", 16, 16, &umr_bitfield_default },
};
static struct umr_bitfield mmDAC_FORCE_OUTPUT_CNTL[] = {
	 { "DAC_FORCE_DATA_EN", 0, 0, &umr_bitfield_default },
	 { "DAC_FORCE_DATA_SEL", 8, 10, &umr_bitfield_default },
	 { "DAC_FORCE_DATA_ON_BLANKB_ONLY", 24, 24, &umr_bitfield_default },
};
static struct umr_bitfield mmDAC_FORCE_DATA[] = {
	 { "DAC_FORCE_DATA", 0, 9, &umr_bitfield_default },
};
static struct umr_bitfield mmDAC_POWERDOWN[] = {
	 { "DAC_POWERDOWN", 0, 0, &umr_bitfield_default },
	 { "DAC_POWERDOWN_BLUE", 8, 8, &umr_bitfield_default },
	 { "DAC_POWERDOWN_GREEN", 16, 16, &umr_bitfield_default },
	 { "DAC_POWERDOWN_RED", 24, 24, &umr_bitfield_default },
};
static struct umr_bitfield mmDAC_CONTROL[] = {
	 { "DAC_DFORCE_EN", 0, 0, &umr_bitfield_default },
	 { "DAC_TV_ENABLE", 8, 8, &umr_bitfield_default },
	 { "DAC_ZSCALE_SHIFT", 16, 16, &umr_bitfield_default },
};
static struct umr_bitfield mmDAC_COMPARATOR_ENABLE[] = {
	 { "DAC_COMP_DDET_REF_EN", 0, 0, &umr_bitfield_default },
	 { "DAC_COMP_SDET_REF_EN", 8, 8, &umr_bitfield_default },
	 { "DAC_R_ASYNC_ENABLE", 16, 16, &umr_bitfield_default },
	 { "DAC_G_ASYNC_ENABLE", 17, 17, &umr_bitfield_default },
	 { "DAC_B_ASYNC_ENABLE", 18, 18, &umr_bitfield_default },
};
static struct umr_bitfield mmDAC_COMPARATOR_OUTPUT[] = {
	 { "DAC_COMPARATOR_OUTPUT", 0, 0, &umr_bitfield_default },
	 { "DAC_COMPARATOR_OUTPUT_BLUE", 1, 1, &umr_bitfield_default },
	 { "DAC_COMPARATOR_OUTPUT_GREEN", 2, 2, &umr_bitfield_default },
	 { "DAC_COMPARATOR_OUTPUT_RED", 3, 3, &umr_bitfield_default },
};
static struct umr_bitfield mmDAC_PWR_CNTL[] = {
	 { "DAC_BG_MODE", 0, 1, &umr_bitfield_default },
	 { "DAC_PWRCNTL", 16, 17, &umr_bitfield_default },
};
static struct umr_bitfield mmDAC_DFT_CONFIG[] = {
	 { "DAC_DFT_CONFIG", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDAC_FIFO_STATUS[] = {
	 { "DAC_FIFO_USE_OVERWRITE_LEVEL", 1, 1, &umr_bitfield_default },
	 { "DAC_FIFO_OVERWRITE_LEVEL", 2, 7, &umr_bitfield_default },
	 { "DAC_FIFO_CAL_AVERAGE_LEVEL", 10, 15, &umr_bitfield_default },
	 { "DAC_FIFO_MAXIMUM_LEVEL", 16, 19, &umr_bitfield_default },
	 { "DAC_FIFO_MINIMUM_LEVEL", 22, 25, &umr_bitfield_default },
	 { "DAC_FIFO_CALIBRATED", 29, 29, &umr_bitfield_default },
	 { "DAC_FIFO_FORCE_RECAL_AVERAGE", 30, 30, &umr_bitfield_default },
	 { "DAC_FIFO_FORCE_RECOMP_MINMAX", 31, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_I2C_CONTROL[] = {
	 { "DC_I2C_GO", 0, 0, &umr_bitfield_default },
	 { "DC_I2C_SOFT_RESET", 1, 1, &umr_bitfield_default },
	 { "DC_I2C_SEND_RESET", 2, 2, &umr_bitfield_default },
	 { "DC_I2C_SW_STATUS_RESET", 3, 3, &umr_bitfield_default },
	 { "DC_I2C_DDC_SELECT", 8, 10, &umr_bitfield_default },
	 { "DC_I2C_TRANSACTION_COUNT", 20, 21, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_I2C_ARBITRATION[] = {
	 { "DC_I2C_SW_PRIORITY", 0, 1, &umr_bitfield_default },
	 { "DC_I2C_REG_RW_CNTL_STATUS", 2, 3, &umr_bitfield_default },
	 { "DC_I2C_NO_QUEUED_SW_GO", 4, 4, &umr_bitfield_default },
	 { "DC_I2C_ABORT_HW_XFER", 8, 8, &umr_bitfield_default },
	 { "DC_I2C_ABORT_SW_XFER", 12, 12, &umr_bitfield_default },
	 { "DC_I2C_SW_USE_I2C_REG_REQ", 20, 20, &umr_bitfield_default },
	 { "DC_I2C_SW_DONE_USING_I2C_REG", 21, 21, &umr_bitfield_default },
	 { "DC_I2C_DMCU_USE_I2C_REG_REQ", 24, 24, &umr_bitfield_default },
	 { "DC_I2C_DMCU_DONE_USING_I2C_REG", 25, 25, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_I2C_INTERRUPT_CONTROL[] = {
	 { "DC_I2C_SW_DONE_INT", 0, 0, &umr_bitfield_default },
	 { "DC_I2C_SW_DONE_ACK", 1, 1, &umr_bitfield_default },
	 { "DC_I2C_SW_DONE_MASK", 2, 2, &umr_bitfield_default },
	 { "DC_I2C_DDC1_HW_DONE_INT", 4, 4, &umr_bitfield_default },
	 { "DC_I2C_DDC1_HW_DONE_ACK", 5, 5, &umr_bitfield_default },
	 { "DC_I2C_DDC1_HW_DONE_MASK", 6, 6, &umr_bitfield_default },
	 { "DC_I2C_DDC2_HW_DONE_INT", 8, 8, &umr_bitfield_default },
	 { "DC_I2C_DDC2_HW_DONE_ACK", 9, 9, &umr_bitfield_default },
	 { "DC_I2C_DDC2_HW_DONE_MASK", 10, 10, &umr_bitfield_default },
	 { "DC_I2C_DDC3_HW_DONE_INT", 12, 12, &umr_bitfield_default },
	 { "DC_I2C_DDC3_HW_DONE_ACK", 13, 13, &umr_bitfield_default },
	 { "DC_I2C_DDC3_HW_DONE_MASK", 14, 14, &umr_bitfield_default },
	 { "DC_I2C_DDC4_HW_DONE_INT", 16, 16, &umr_bitfield_default },
	 { "DC_I2C_DDC4_HW_DONE_ACK", 17, 17, &umr_bitfield_default },
	 { "DC_I2C_DDC4_HW_DONE_MASK", 18, 18, &umr_bitfield_default },
	 { "DC_I2C_DDC5_HW_DONE_INT", 20, 20, &umr_bitfield_default },
	 { "DC_I2C_DDC5_HW_DONE_ACK", 21, 21, &umr_bitfield_default },
	 { "DC_I2C_DDC5_HW_DONE_MASK", 22, 22, &umr_bitfield_default },
	 { "DC_I2C_DDC6_HW_DONE_INT", 24, 24, &umr_bitfield_default },
	 { "DC_I2C_DDC6_HW_DONE_ACK", 25, 25, &umr_bitfield_default },
	 { "DC_I2C_DDC6_HW_DONE_MASK", 26, 26, &umr_bitfield_default },
	 { "DC_I2C_DDCVGA_HW_DONE_INT", 27, 27, &umr_bitfield_default },
	 { "DC_I2C_DDCVGA_HW_DONE_ACK", 28, 28, &umr_bitfield_default },
	 { "DC_I2C_DDCVGA_HW_DONE_MASK", 29, 29, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_I2C_SW_STATUS[] = {
	 { "DC_I2C_SW_STATUS", 0, 1, &umr_bitfield_default },
	 { "DC_I2C_SW_DONE", 2, 2, &umr_bitfield_default },
	 { "DC_I2C_SW_ABORTED", 4, 4, &umr_bitfield_default },
	 { "DC_I2C_SW_TIMEOUT", 5, 5, &umr_bitfield_default },
	 { "DC_I2C_SW_INTERRUPTED", 6, 6, &umr_bitfield_default },
	 { "DC_I2C_SW_BUFFER_OVERFLOW", 7, 7, &umr_bitfield_default },
	 { "DC_I2C_SW_STOPPED_ON_NACK", 8, 8, &umr_bitfield_default },
	 { "DC_I2C_SW_NACK0", 12, 12, &umr_bitfield_default },
	 { "DC_I2C_SW_NACK1", 13, 13, &umr_bitfield_default },
	 { "DC_I2C_SW_NACK2", 14, 14, &umr_bitfield_default },
	 { "DC_I2C_SW_NACK3", 15, 15, &umr_bitfield_default },
	 { "DC_I2C_SW_REQ", 18, 18, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_I2C_DDC1_HW_STATUS[] = {
	 { "DC_I2C_DDC1_HW_STATUS", 0, 1, &umr_bitfield_default },
	 { "DC_I2C_DDC1_HW_DONE", 3, 3, &umr_bitfield_default },
	 { "DC_I2C_DDC1_HW_REQ", 16, 16, &umr_bitfield_default },
	 { "DC_I2C_DDC1_HW_URG", 17, 17, &umr_bitfield_default },
	 { "DC_I2C_DDC1_EDID_DETECT_STATUS", 20, 20, &umr_bitfield_default },
	 { "DC_I2C_DDC1_EDID_DETECT_NUM_VALID_TRIES", 24, 27, &umr_bitfield_default },
	 { "DC_I2C_DDC1_EDID_DETECT_STATE", 28, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_I2C_DDC2_HW_STATUS[] = {
	 { "DC_I2C_DDC2_HW_STATUS", 0, 1, &umr_bitfield_default },
	 { "DC_I2C_DDC2_HW_DONE", 3, 3, &umr_bitfield_default },
	 { "DC_I2C_DDC2_HW_REQ", 16, 16, &umr_bitfield_default },
	 { "DC_I2C_DDC2_HW_URG", 17, 17, &umr_bitfield_default },
	 { "DC_I2C_DDC2_EDID_DETECT_STATUS", 20, 20, &umr_bitfield_default },
	 { "DC_I2C_DDC2_EDID_DETECT_NUM_VALID_TRIES", 24, 27, &umr_bitfield_default },
	 { "DC_I2C_DDC2_EDID_DETECT_STATE", 28, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_I2C_DDC3_HW_STATUS[] = {
	 { "DC_I2C_DDC3_HW_STATUS", 0, 1, &umr_bitfield_default },
	 { "DC_I2C_DDC3_HW_DONE", 3, 3, &umr_bitfield_default },
	 { "DC_I2C_DDC3_HW_REQ", 16, 16, &umr_bitfield_default },
	 { "DC_I2C_DDC3_HW_URG", 17, 17, &umr_bitfield_default },
	 { "DC_I2C_DDC3_EDID_DETECT_STATUS", 20, 20, &umr_bitfield_default },
	 { "DC_I2C_DDC3_EDID_DETECT_NUM_VALID_TRIES", 24, 27, &umr_bitfield_default },
	 { "DC_I2C_DDC3_EDID_DETECT_STATE", 28, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_I2C_DDC4_HW_STATUS[] = {
	 { "DC_I2C_DDC4_HW_STATUS", 0, 1, &umr_bitfield_default },
	 { "DC_I2C_DDC4_HW_DONE", 3, 3, &umr_bitfield_default },
	 { "DC_I2C_DDC4_HW_REQ", 16, 16, &umr_bitfield_default },
	 { "DC_I2C_DDC4_HW_URG", 17, 17, &umr_bitfield_default },
	 { "DC_I2C_DDC4_EDID_DETECT_STATUS", 20, 20, &umr_bitfield_default },
	 { "DC_I2C_DDC4_EDID_DETECT_NUM_VALID_TRIES", 24, 27, &umr_bitfield_default },
	 { "DC_I2C_DDC4_EDID_DETECT_STATE", 28, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_I2C_DDC5_HW_STATUS[] = {
	 { "DC_I2C_DDC5_HW_STATUS", 0, 1, &umr_bitfield_default },
	 { "DC_I2C_DDC5_HW_DONE", 3, 3, &umr_bitfield_default },
	 { "DC_I2C_DDC5_HW_REQ", 16, 16, &umr_bitfield_default },
	 { "DC_I2C_DDC5_HW_URG", 17, 17, &umr_bitfield_default },
	 { "DC_I2C_DDC5_EDID_DETECT_STATUS", 20, 20, &umr_bitfield_default },
	 { "DC_I2C_DDC5_EDID_DETECT_NUM_VALID_TRIES", 24, 27, &umr_bitfield_default },
	 { "DC_I2C_DDC5_EDID_DETECT_STATE", 28, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_I2C_DDC6_HW_STATUS[] = {
	 { "DC_I2C_DDC6_HW_STATUS", 0, 1, &umr_bitfield_default },
	 { "DC_I2C_DDC6_HW_DONE", 3, 3, &umr_bitfield_default },
	 { "DC_I2C_DDC6_HW_REQ", 16, 16, &umr_bitfield_default },
	 { "DC_I2C_DDC6_HW_URG", 17, 17, &umr_bitfield_default },
	 { "DC_I2C_DDC6_EDID_DETECT_STATUS", 20, 20, &umr_bitfield_default },
	 { "DC_I2C_DDC6_EDID_DETECT_NUM_VALID_TRIES", 24, 27, &umr_bitfield_default },
	 { "DC_I2C_DDC6_EDID_DETECT_STATE", 28, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_I2C_DDC1_SPEED[] = {
	 { "DC_I2C_DDC1_THRESHOLD", 0, 1, &umr_bitfield_default },
	 { "DC_I2C_DDC1_DISABLE_FILTER_DURING_STALL", 4, 4, &umr_bitfield_default },
	 { "DC_I2C_DDC1_START_STOP_TIMING_CNTL", 8, 9, &umr_bitfield_default },
	 { "DC_I2C_DDC1_PRESCALE", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_I2C_DDC1_SETUP[] = {
	 { "DC_I2C_DDC1_DATA_DRIVE_EN", 0, 0, &umr_bitfield_default },
	 { "DC_I2C_DDC1_DATA_DRIVE_SEL", 1, 1, &umr_bitfield_default },
	 { "DC_I2C_DDC1_EDID_DETECT_ENABLE", 4, 4, &umr_bitfield_default },
	 { "DC_I2C_DDC1_EDID_DETECT_MODE", 5, 5, &umr_bitfield_default },
	 { "DC_I2C_DDC1_ENABLE", 6, 6, &umr_bitfield_default },
	 { "DC_I2C_DDC1_CLK_DRIVE_EN", 7, 7, &umr_bitfield_default },
	 { "DC_I2C_DDC1_INTRA_BYTE_DELAY", 8, 15, &umr_bitfield_default },
	 { "DC_I2C_DDC1_INTRA_TRANSACTION_DELAY", 16, 23, &umr_bitfield_default },
	 { "DC_I2C_DDC1_TIME_LIMIT", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_I2C_DDC2_SPEED[] = {
	 { "DC_I2C_DDC2_THRESHOLD", 0, 1, &umr_bitfield_default },
	 { "DC_I2C_DDC2_DISABLE_FILTER_DURING_STALL", 4, 4, &umr_bitfield_default },
	 { "DC_I2C_DDC2_START_STOP_TIMING_CNTL", 8, 9, &umr_bitfield_default },
	 { "DC_I2C_DDC2_PRESCALE", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_I2C_DDC2_SETUP[] = {
	 { "DC_I2C_DDC2_DATA_DRIVE_EN", 0, 0, &umr_bitfield_default },
	 { "DC_I2C_DDC2_DATA_DRIVE_SEL", 1, 1, &umr_bitfield_default },
	 { "DC_I2C_DDC2_EDID_DETECT_ENABLE", 4, 4, &umr_bitfield_default },
	 { "DC_I2C_DDC2_EDID_DETECT_MODE", 5, 5, &umr_bitfield_default },
	 { "DC_I2C_DDC2_ENABLE", 6, 6, &umr_bitfield_default },
	 { "DC_I2C_DDC2_CLK_DRIVE_EN", 7, 7, &umr_bitfield_default },
	 { "DC_I2C_DDC2_INTRA_BYTE_DELAY", 8, 15, &umr_bitfield_default },
	 { "DC_I2C_DDC2_INTRA_TRANSACTION_DELAY", 16, 23, &umr_bitfield_default },
	 { "DC_I2C_DDC2_TIME_LIMIT", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_I2C_DDC3_SPEED[] = {
	 { "DC_I2C_DDC3_THRESHOLD", 0, 1, &umr_bitfield_default },
	 { "DC_I2C_DDC3_DISABLE_FILTER_DURING_STALL", 4, 4, &umr_bitfield_default },
	 { "DC_I2C_DDC3_START_STOP_TIMING_CNTL", 8, 9, &umr_bitfield_default },
	 { "DC_I2C_DDC3_PRESCALE", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_I2C_DDC3_SETUP[] = {
	 { "DC_I2C_DDC3_DATA_DRIVE_EN", 0, 0, &umr_bitfield_default },
	 { "DC_I2C_DDC3_DATA_DRIVE_SEL", 1, 1, &umr_bitfield_default },
	 { "DC_I2C_DDC3_EDID_DETECT_ENABLE", 4, 4, &umr_bitfield_default },
	 { "DC_I2C_DDC3_EDID_DETECT_MODE", 5, 5, &umr_bitfield_default },
	 { "DC_I2C_DDC3_ENABLE", 6, 6, &umr_bitfield_default },
	 { "DC_I2C_DDC3_CLK_DRIVE_EN", 7, 7, &umr_bitfield_default },
	 { "DC_I2C_DDC3_INTRA_BYTE_DELAY", 8, 15, &umr_bitfield_default },
	 { "DC_I2C_DDC3_INTRA_TRANSACTION_DELAY", 16, 23, &umr_bitfield_default },
	 { "DC_I2C_DDC3_TIME_LIMIT", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_I2C_DDC4_SPEED[] = {
	 { "DC_I2C_DDC4_THRESHOLD", 0, 1, &umr_bitfield_default },
	 { "DC_I2C_DDC4_DISABLE_FILTER_DURING_STALL", 4, 4, &umr_bitfield_default },
	 { "DC_I2C_DDC4_START_STOP_TIMING_CNTL", 8, 9, &umr_bitfield_default },
	 { "DC_I2C_DDC4_PRESCALE", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_I2C_DDC4_SETUP[] = {
	 { "DC_I2C_DDC4_DATA_DRIVE_EN", 0, 0, &umr_bitfield_default },
	 { "DC_I2C_DDC4_DATA_DRIVE_SEL", 1, 1, &umr_bitfield_default },
	 { "DC_I2C_DDC4_EDID_DETECT_ENABLE", 4, 4, &umr_bitfield_default },
	 { "DC_I2C_DDC4_EDID_DETECT_MODE", 5, 5, &umr_bitfield_default },
	 { "DC_I2C_DDC4_ENABLE", 6, 6, &umr_bitfield_default },
	 { "DC_I2C_DDC4_CLK_DRIVE_EN", 7, 7, &umr_bitfield_default },
	 { "DC_I2C_DDC4_INTRA_BYTE_DELAY", 8, 15, &umr_bitfield_default },
	 { "DC_I2C_DDC4_INTRA_TRANSACTION_DELAY", 16, 23, &umr_bitfield_default },
	 { "DC_I2C_DDC4_TIME_LIMIT", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_I2C_DDC5_SPEED[] = {
	 { "DC_I2C_DDC5_THRESHOLD", 0, 1, &umr_bitfield_default },
	 { "DC_I2C_DDC5_DISABLE_FILTER_DURING_STALL", 4, 4, &umr_bitfield_default },
	 { "DC_I2C_DDC5_START_STOP_TIMING_CNTL", 8, 9, &umr_bitfield_default },
	 { "DC_I2C_DDC5_PRESCALE", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_I2C_DDC5_SETUP[] = {
	 { "DC_I2C_DDC5_DATA_DRIVE_EN", 0, 0, &umr_bitfield_default },
	 { "DC_I2C_DDC5_DATA_DRIVE_SEL", 1, 1, &umr_bitfield_default },
	 { "DC_I2C_DDC5_EDID_DETECT_ENABLE", 4, 4, &umr_bitfield_default },
	 { "DC_I2C_DDC5_EDID_DETECT_MODE", 5, 5, &umr_bitfield_default },
	 { "DC_I2C_DDC5_ENABLE", 6, 6, &umr_bitfield_default },
	 { "DC_I2C_DDC5_CLK_DRIVE_EN", 7, 7, &umr_bitfield_default },
	 { "DC_I2C_DDC5_INTRA_BYTE_DELAY", 8, 15, &umr_bitfield_default },
	 { "DC_I2C_DDC5_INTRA_TRANSACTION_DELAY", 16, 23, &umr_bitfield_default },
	 { "DC_I2C_DDC5_TIME_LIMIT", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_I2C_DDC6_SPEED[] = {
	 { "DC_I2C_DDC6_THRESHOLD", 0, 1, &umr_bitfield_default },
	 { "DC_I2C_DDC6_DISABLE_FILTER_DURING_STALL", 4, 4, &umr_bitfield_default },
	 { "DC_I2C_DDC6_START_STOP_TIMING_CNTL", 8, 9, &umr_bitfield_default },
	 { "DC_I2C_DDC6_PRESCALE", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_I2C_DDC6_SETUP[] = {
	 { "DC_I2C_DDC6_DATA_DRIVE_EN", 0, 0, &umr_bitfield_default },
	 { "DC_I2C_DDC6_DATA_DRIVE_SEL", 1, 1, &umr_bitfield_default },
	 { "DC_I2C_DDC6_EDID_DETECT_ENABLE", 4, 4, &umr_bitfield_default },
	 { "DC_I2C_DDC6_EDID_DETECT_MODE", 5, 5, &umr_bitfield_default },
	 { "DC_I2C_DDC6_ENABLE", 6, 6, &umr_bitfield_default },
	 { "DC_I2C_DDC6_CLK_DRIVE_EN", 7, 7, &umr_bitfield_default },
	 { "DC_I2C_DDC6_INTRA_BYTE_DELAY", 8, 15, &umr_bitfield_default },
	 { "DC_I2C_DDC6_INTRA_TRANSACTION_DELAY", 16, 23, &umr_bitfield_default },
	 { "DC_I2C_DDC6_TIME_LIMIT", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_I2C_TRANSACTION0[] = {
	 { "DC_I2C_RW0", 0, 0, &umr_bitfield_default },
	 { "DC_I2C_STOP_ON_NACK0", 8, 8, &umr_bitfield_default },
	 { "DC_I2C_START0", 12, 12, &umr_bitfield_default },
	 { "DC_I2C_STOP0", 13, 13, &umr_bitfield_default },
	 { "DC_I2C_COUNT0", 16, 25, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_I2C_TRANSACTION1[] = {
	 { "DC_I2C_RW1", 0, 0, &umr_bitfield_default },
	 { "DC_I2C_STOP_ON_NACK1", 8, 8, &umr_bitfield_default },
	 { "DC_I2C_START1", 12, 12, &umr_bitfield_default },
	 { "DC_I2C_STOP1", 13, 13, &umr_bitfield_default },
	 { "DC_I2C_COUNT1", 16, 25, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_I2C_TRANSACTION2[] = {
	 { "DC_I2C_RW2", 0, 0, &umr_bitfield_default },
	 { "DC_I2C_STOP_ON_NACK2", 8, 8, &umr_bitfield_default },
	 { "DC_I2C_START2", 12, 12, &umr_bitfield_default },
	 { "DC_I2C_STOP2", 13, 13, &umr_bitfield_default },
	 { "DC_I2C_COUNT2", 16, 25, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_I2C_TRANSACTION3[] = {
	 { "DC_I2C_RW3", 0, 0, &umr_bitfield_default },
	 { "DC_I2C_STOP_ON_NACK3", 8, 8, &umr_bitfield_default },
	 { "DC_I2C_START3", 12, 12, &umr_bitfield_default },
	 { "DC_I2C_STOP3", 13, 13, &umr_bitfield_default },
	 { "DC_I2C_COUNT3", 16, 25, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_I2C_DATA[] = {
	 { "DC_I2C_DATA_RW", 0, 0, &umr_bitfield_default },
	 { "DC_I2C_DATA", 8, 15, &umr_bitfield_default },
	 { "DC_I2C_INDEX", 16, 25, &umr_bitfield_default },
	 { "DC_I2C_INDEX_WRITE", 31, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_I2C_DDCVGA_HW_STATUS[] = {
	 { "DC_I2C_DDCVGA_HW_STATUS", 0, 1, &umr_bitfield_default },
	 { "DC_I2C_DDCVGA_HW_DONE", 3, 3, &umr_bitfield_default },
	 { "DC_I2C_DDCVGA_HW_REQ", 16, 16, &umr_bitfield_default },
	 { "DC_I2C_DDCVGA_HW_URG", 17, 17, &umr_bitfield_default },
	 { "DC_I2C_DDCVGA_EDID_DETECT_STATUS", 20, 20, &umr_bitfield_default },
	 { "DC_I2C_DDCVGA_EDID_DETECT_NUM_VALID_TRIES", 24, 27, &umr_bitfield_default },
	 { "DC_I2C_DDCVGA_EDID_DETECT_STATE", 28, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_I2C_DDCVGA_SPEED[] = {
	 { "DC_I2C_DDCVGA_THRESHOLD", 0, 1, &umr_bitfield_default },
	 { "DC_I2C_DDCVGA_DISABLE_FILTER_DURING_STALL", 4, 4, &umr_bitfield_default },
	 { "DC_I2C_DDCVGA_START_STOP_TIMING_CNTL", 8, 9, &umr_bitfield_default },
	 { "DC_I2C_DDCVGA_PRESCALE", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_I2C_DDCVGA_SETUP[] = {
	 { "DC_I2C_DDCVGA_DATA_DRIVE_EN", 0, 0, &umr_bitfield_default },
	 { "DC_I2C_DDCVGA_DATA_DRIVE_SEL", 1, 1, &umr_bitfield_default },
	 { "DC_I2C_DDCVGA_EDID_DETECT_ENABLE", 4, 4, &umr_bitfield_default },
	 { "DC_I2C_DDCVGA_EDID_DETECT_MODE", 5, 5, &umr_bitfield_default },
	 { "DC_I2C_DDCVGA_ENABLE", 6, 6, &umr_bitfield_default },
	 { "DC_I2C_DDCVGA_CLK_DRIVE_EN", 7, 7, &umr_bitfield_default },
	 { "DC_I2C_DDCVGA_INTRA_BYTE_DELAY", 8, 15, &umr_bitfield_default },
	 { "DC_I2C_DDCVGA_INTRA_TRANSACTION_DELAY", 16, 23, &umr_bitfield_default },
	 { "DC_I2C_DDCVGA_TIME_LIMIT", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_I2C_EDID_DETECT_CTRL[] = {
	 { "DC_I2C_EDID_DETECT_WAIT_TIME", 0, 15, &umr_bitfield_default },
	 { "DC_I2C_EDID_DETECT_NUM_TRIES_UNTIL_VALID", 20, 23, &umr_bitfield_default },
	 { "DC_I2C_EDID_DETECT_SEND_RESET", 28, 28, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_I2C_READ_REQUEST_INTERRUPT[] = {
	 { "DC_I2C_DDC1_READ_REQUEST_OCCURRED", 0, 0, &umr_bitfield_default },
	 { "DC_I2C_DDC1_READ_REQUEST_INT", 1, 1, &umr_bitfield_default },
	 { "DC_I2C_DDC1_READ_REQUEST_ACK", 2, 2, &umr_bitfield_default },
	 { "DC_I2C_DDC1_READ_REQUEST_MASK", 3, 3, &umr_bitfield_default },
	 { "DC_I2C_DDC2_READ_REQUEST_OCCURRED", 4, 4, &umr_bitfield_default },
	 { "DC_I2C_DDC2_READ_REQUEST_INT", 5, 5, &umr_bitfield_default },
	 { "DC_I2C_DDC2_READ_REQUEST_ACK", 6, 6, &umr_bitfield_default },
	 { "DC_I2C_DDC2_READ_REQUEST_MASK", 7, 7, &umr_bitfield_default },
	 { "DC_I2C_DDC3_READ_REQUEST_OCCURRED", 8, 8, &umr_bitfield_default },
	 { "DC_I2C_DDC3_READ_REQUEST_INT", 9, 9, &umr_bitfield_default },
	 { "DC_I2C_DDC3_READ_REQUEST_ACK", 10, 10, &umr_bitfield_default },
	 { "DC_I2C_DDC3_READ_REQUEST_MASK", 11, 11, &umr_bitfield_default },
	 { "DC_I2C_DDC4_READ_REQUEST_OCCURRED", 12, 12, &umr_bitfield_default },
	 { "DC_I2C_DDC4_READ_REQUEST_INT", 13, 13, &umr_bitfield_default },
	 { "DC_I2C_DDC4_READ_REQUEST_ACK", 14, 14, &umr_bitfield_default },
	 { "DC_I2C_DDC4_READ_REQUEST_MASK", 15, 15, &umr_bitfield_default },
	 { "DC_I2C_DDC5_READ_REQUEST_OCCURRED", 16, 16, &umr_bitfield_default },
	 { "DC_I2C_DDC5_READ_REQUEST_INT", 17, 17, &umr_bitfield_default },
	 { "DC_I2C_DDC5_READ_REQUEST_ACK", 18, 18, &umr_bitfield_default },
	 { "DC_I2C_DDC5_READ_REQUEST_MASK", 19, 19, &umr_bitfield_default },
	 { "DC_I2C_DDC6_READ_REQUEST_OCCURRED", 20, 20, &umr_bitfield_default },
	 { "DC_I2C_DDC6_READ_REQUEST_INT", 21, 21, &umr_bitfield_default },
	 { "DC_I2C_DDC6_READ_REQUEST_ACK", 22, 22, &umr_bitfield_default },
	 { "DC_I2C_DDC6_READ_REQUEST_MASK", 23, 23, &umr_bitfield_default },
	 { "DC_I2C_DDCVGA_READ_REQUEST_OCCURRED", 24, 24, &umr_bitfield_default },
	 { "DC_I2C_DDCVGA_READ_REQUEST_INT", 25, 25, &umr_bitfield_default },
	 { "DC_I2C_DDCVGA_READ_REQUEST_ACK", 26, 26, &umr_bitfield_default },
	 { "DC_I2C_DDCVGA_READ_REQUEST_MASK", 27, 27, &umr_bitfield_default },
	 { "DC_I2C_DDC_READ_REQUEST_ACK_ENABLE", 30, 30, &umr_bitfield_default },
	 { "DC_I2C_DDC_READ_REQUEST_INT_TYPE", 31, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmGENERIC_I2C_CONTROL[] = {
	 { "GENERIC_I2C_GO", 0, 0, &umr_bitfield_default },
	 { "GENERIC_I2C_SOFT_RESET", 1, 1, &umr_bitfield_default },
	 { "GENERIC_I2C_SEND_RESET", 2, 2, &umr_bitfield_default },
	 { "GENERIC_I2C_ENABLE", 3, 3, &umr_bitfield_default },
};
static struct umr_bitfield mmGENERIC_I2C_INTERRUPT_CONTROL[] = {
	 { "GENERIC_I2C_DONE_INT", 0, 0, &umr_bitfield_default },
	 { "GENERIC_I2C_DONE_ACK", 1, 1, &umr_bitfield_default },
	 { "GENERIC_I2C_DONE_MASK", 2, 2, &umr_bitfield_default },
};
static struct umr_bitfield mmGENERIC_I2C_STATUS[] = {
	 { "GENERIC_I2C_STATUS", 0, 3, &umr_bitfield_default },
	 { "GENERIC_I2C_DONE", 4, 4, &umr_bitfield_default },
	 { "GENERIC_I2C_ABORTED", 5, 5, &umr_bitfield_default },
	 { "GENERIC_I2C_TIMEOUT", 6, 6, &umr_bitfield_default },
	 { "GENERIC_I2C_STOPPED_ON_NACK", 9, 9, &umr_bitfield_default },
	 { "GENERIC_I2C_NACK", 10, 10, &umr_bitfield_default },
};
static struct umr_bitfield mmGENERIC_I2C_SPEED[] = {
	 { "GENERIC_I2C_THRESHOLD", 0, 1, &umr_bitfield_default },
	 { "GENERIC_I2C_DISABLE_FILTER_DURING_STALL", 4, 4, &umr_bitfield_default },
	 { "GENERIC_I2C_START_STOP_TIMING_CNTL", 8, 9, &umr_bitfield_default },
	 { "GENERIC_I2C_PRESCALE", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmGENERIC_I2C_SETUP[] = {
	 { "GENERIC_I2C_DATA_DRIVE_EN", 0, 0, &umr_bitfield_default },
	 { "GENERIC_I2C_DATA_DRIVE_SEL", 1, 1, &umr_bitfield_default },
	 { "GENERIC_I2C_CLK_DRIVE_EN", 7, 7, &umr_bitfield_default },
	 { "GENERIC_I2C_INTRA_BYTE_DELAY", 8, 15, &umr_bitfield_default },
	 { "GENERIC_I2C_TIME_LIMIT", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmGENERIC_I2C_TRANSACTION[] = {
	 { "GENERIC_I2C_RW", 0, 0, &umr_bitfield_default },
	 { "GENERIC_I2C_STOP_ON_NACK", 8, 8, &umr_bitfield_default },
	 { "GENERIC_I2C_ACK_ON_READ", 9, 9, &umr_bitfield_default },
	 { "GENERIC_I2C_START", 12, 12, &umr_bitfield_default },
	 { "GENERIC_I2C_STOP", 13, 13, &umr_bitfield_default },
	 { "GENERIC_I2C_COUNT", 16, 19, &umr_bitfield_default },
};
static struct umr_bitfield mmGENERIC_I2C_DATA[] = {
	 { "GENERIC_I2C_DATA_RW", 0, 0, &umr_bitfield_default },
	 { "GENERIC_I2C_DATA", 8, 15, &umr_bitfield_default },
	 { "GENERIC_I2C_INDEX", 16, 19, &umr_bitfield_default },
	 { "GENERIC_I2C_INDEX_WRITE", 31, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmGENERIC_I2C_PIN_SELECTION[] = {
	 { "GENERIC_I2C_SCL_PIN_SEL", 0, 6, &umr_bitfield_default },
	 { "GENERIC_I2C_SDA_PIN_SEL", 8, 14, &umr_bitfield_default },
};
static struct umr_bitfield mmDIO_SCRATCH0[] = {
	 { "DIO_SCRATCH0", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDIO_SCRATCH1[] = {
	 { "DIO_SCRATCH1", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDIO_SCRATCH2[] = {
	 { "DIO_SCRATCH2", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDIO_SCRATCH3[] = {
	 { "DIO_SCRATCH3", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDIO_SCRATCH4[] = {
	 { "DIO_SCRATCH4", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDIO_SCRATCH5[] = {
	 { "DIO_SCRATCH5", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDIO_SCRATCH6[] = {
	 { "DIO_SCRATCH6", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDIO_SCRATCH7[] = {
	 { "DIO_SCRATCH7", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCE_VCE_CONTROL[] = {
	 { "DC_VCE_AUDIO_STREAM_SELECT", 4, 6, &umr_bitfield_default },
};
static struct umr_bitfield mmDIO_MEM_PWR_STATUS[] = {
	 { "I2C_MEM_PWR_STATE", 0, 0, &umr_bitfield_default },
	 { "DPA_MEM_PWR_STATE", 3, 3, &umr_bitfield_default },
	 { "DPB_MEM_PWR_STATE", 4, 4, &umr_bitfield_default },
	 { "DPC_MEM_PWR_STATE", 5, 5, &umr_bitfield_default },
	 { "DPD_MEM_PWR_STATE", 6, 6, &umr_bitfield_default },
	 { "DPE_MEM_PWR_STATE", 7, 7, &umr_bitfield_default },
	 { "DPF_MEM_PWR_STATE", 8, 8, &umr_bitfield_default },
	 { "DPG_MEM_PWR_STATE", 9, 9, &umr_bitfield_default },
	 { "HDMI0_MEM_PWR_STATE", 10, 11, &umr_bitfield_default },
	 { "HDMI1_MEM_PWR_STATE", 12, 13, &umr_bitfield_default },
	 { "HDMI2_MEM_PWR_STATE", 14, 15, &umr_bitfield_default },
	 { "HDMI3_MEM_PWR_STATE", 16, 17, &umr_bitfield_default },
	 { "HDMI4_MEM_PWR_STATE", 18, 19, &umr_bitfield_default },
	 { "HDMI5_MEM_PWR_STATE", 20, 21, &umr_bitfield_default },
	 { "HDMI6_MEM_PWR_STATE", 22, 23, &umr_bitfield_default },
};
static struct umr_bitfield mmDIO_MEM_PWR_CTRL[] = {
	 { "I2C_LIGHT_SLEEP_FORCE", 0, 0, &umr_bitfield_default },
	 { "I2C_LIGHT_SLEEP_DIS", 1, 1, &umr_bitfield_default },
	 { "DPA_LIGHT_SLEEP_DIS", 4, 4, &umr_bitfield_default },
	 { "DPB_LIGHT_SLEEP_DIS", 5, 5, &umr_bitfield_default },
	 { "DPC_LIGHT_SLEEP_DIS", 6, 6, &umr_bitfield_default },
	 { "DPD_LIGHT_SLEEP_DIS", 7, 7, &umr_bitfield_default },
	 { "DPE_LIGHT_SLEEP_DIS", 8, 8, &umr_bitfield_default },
	 { "DPF_LIGHT_SLEEP_DIS", 9, 9, &umr_bitfield_default },
	 { "DPG_LIGHT_SLEEP_DIS", 10, 10, &umr_bitfield_default },
	 { "HDMI0_MEM_PWR_FORCE", 11, 12, &umr_bitfield_default },
	 { "HDMI0_MEM_PWR_DIS", 13, 13, &umr_bitfield_default },
	 { "HDMI1_MEM_PWR_FORCE", 14, 15, &umr_bitfield_default },
	 { "HDMI1_MEM_PWR_DIS", 16, 16, &umr_bitfield_default },
	 { "HDMI2_MEM_PWR_FORCE", 17, 18, &umr_bitfield_default },
	 { "HDMI2_MEM_PWR_DIS", 19, 19, &umr_bitfield_default },
	 { "HDMI3_MEM_PWR_FORCE", 20, 21, &umr_bitfield_default },
	 { "HDMI3_MEM_PWR_DIS", 22, 22, &umr_bitfield_default },
	 { "HDMI4_MEM_PWR_FORCE", 23, 24, &umr_bitfield_default },
	 { "HDMI4_MEM_PWR_DIS", 25, 25, &umr_bitfield_default },
	 { "HDMI5_MEM_PWR_FORCE", 26, 27, &umr_bitfield_default },
	 { "HDMI5_MEM_PWR_DIS", 28, 28, &umr_bitfield_default },
	 { "HDMI6_MEM_PWR_FORCE", 29, 30, &umr_bitfield_default },
	 { "HDMI6_MEM_PWR_DIS", 31, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDIO_MEM_PWR_CTRL2[] = {
	 { "HDMI_MEM_PWR_MODE_SEL", 0, 1, &umr_bitfield_default },
	 { "AFMT0_LIGHT_SLEEP_DIS", 4, 4, &umr_bitfield_default },
	 { "AFMT0_LIGHT_SLEEP_FORCE", 5, 5, &umr_bitfield_default },
	 { "AFMT1_LIGHT_SLEEP_DIS", 6, 6, &umr_bitfield_default },
	 { "AFMT1_LIGHT_SLEEP_FORCE", 7, 7, &umr_bitfield_default },
	 { "AFMT2_LIGHT_SLEEP_DIS", 8, 8, &umr_bitfield_default },
	 { "AFMT2_LIGHT_SLEEP_FORCE", 9, 9, &umr_bitfield_default },
	 { "AFMT3_LIGHT_SLEEP_DIS", 10, 10, &umr_bitfield_default },
	 { "AFMT3_LIGHT_SLEEP_FORCE", 11, 11, &umr_bitfield_default },
	 { "AFMT4_LIGHT_SLEEP_DIS", 12, 12, &umr_bitfield_default },
	 { "AFMT4_LIGHT_SLEEP_FORCE", 13, 13, &umr_bitfield_default },
	 { "AFMT5_LIGHT_SLEEP_DIS", 14, 14, &umr_bitfield_default },
	 { "AFMT5_LIGHT_SLEEP_FORCE", 15, 15, &umr_bitfield_default },
	 { "DPA_LIGHT_SLEEP_FORCE", 24, 24, &umr_bitfield_default },
	 { "DPB_LIGHT_SLEEP_FORCE", 25, 25, &umr_bitfield_default },
	 { "DPC_LIGHT_SLEEP_FORCE", 26, 26, &umr_bitfield_default },
	 { "DPD_LIGHT_SLEEP_FORCE", 27, 27, &umr_bitfield_default },
	 { "DPE_LIGHT_SLEEP_FORCE", 28, 28, &umr_bitfield_default },
	 { "DPF_LIGHT_SLEEP_FORCE", 29, 29, &umr_bitfield_default },
	 { "DPG_LIGHT_SLEEP_FORCE", 30, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmDIO_CLK_CNTL[] = {
	 { "DISPCLK_R_DIO_GATE_DIS", 5, 5, &umr_bitfield_default },
	 { "DISPCLK_G_DVO_GATE_DIS", 7, 7, &umr_bitfield_default },
	 { "DISPCLK_G_DACA_GATE_DIS", 8, 8, &umr_bitfield_default },
	 { "REFCLK_R_DIO_GATE_DIS", 10, 10, &umr_bitfield_default },
	 { "DISPCLK_G_DIGA_GATE_DIS", 24, 24, &umr_bitfield_default },
	 { "DISPCLK_G_DIGB_GATE_DIS", 25, 25, &umr_bitfield_default },
	 { "DISPCLK_G_DIGC_GATE_DIS", 26, 26, &umr_bitfield_default },
	 { "DISPCLK_G_DIGD_GATE_DIS", 27, 27, &umr_bitfield_default },
	 { "DISPCLK_G_DIGE_GATE_DIS", 28, 28, &umr_bitfield_default },
	 { "DISPCLK_G_DIGF_GATE_DIS", 29, 29, &umr_bitfield_default },
	 { "DISPCLK_G_DIGG_GATE_DIS", 30, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmDIO_POWER_MANAGEMENT_CNTL[] = {
	 { "PM_ASSERT_RESET", 0, 0, &umr_bitfield_default },
	 { "PM_ALL_BUSY_OFF", 8, 8, &umr_bitfield_default },
};
static struct umr_bitfield mmDIO_STEREOSYNC_SEL[] = {
	 { "GENERICA_STEREOSYNC_SEL", 0, 2, &umr_bitfield_default },
	 { "GENERICB_STEREOSYNC_SEL", 16, 18, &umr_bitfield_default },
};
static struct umr_bitfield mmDIO_SOFT_RESET[] = {
	 { "DACA_SOFT_RESET", 0, 0, &umr_bitfield_default },
	 { "I2S0_SPDIF0_SOFT_RESET", 4, 4, &umr_bitfield_default },
	 { "I2S1_SOFT_RESET", 5, 5, &umr_bitfield_default },
	 { "SPDIF1_SOFT_RESET", 6, 6, &umr_bitfield_default },
	 { "DB_CLK_SOFT_RESET", 12, 12, &umr_bitfield_default },
	 { "DVO_SOFT_RESET", 27, 27, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG_SOFT_RESET[] = {
	 { "DIGA_FE_SOFT_RESET", 0, 0, &umr_bitfield_default },
	 { "DIGA_BE_SOFT_RESET", 1, 1, &umr_bitfield_default },
	 { "DIGB_FE_SOFT_RESET", 4, 4, &umr_bitfield_default },
	 { "DIGB_BE_SOFT_RESET", 5, 5, &umr_bitfield_default },
	 { "DIGC_FE_SOFT_RESET", 8, 8, &umr_bitfield_default },
	 { "DIGC_BE_SOFT_RESET", 9, 9, &umr_bitfield_default },
	 { "DIGD_FE_SOFT_RESET", 12, 12, &umr_bitfield_default },
	 { "DIGD_BE_SOFT_RESET", 13, 13, &umr_bitfield_default },
	 { "DIGE_FE_SOFT_RESET", 16, 16, &umr_bitfield_default },
	 { "DIGE_BE_SOFT_RESET", 17, 17, &umr_bitfield_default },
	 { "DIGF_FE_SOFT_RESET", 20, 20, &umr_bitfield_default },
	 { "DIGF_BE_SOFT_RESET", 21, 21, &umr_bitfield_default },
	 { "DIGG_FE_SOFT_RESET", 24, 24, &umr_bitfield_default },
	 { "DIGG_BE_SOFT_RESET", 25, 25, &umr_bitfield_default },
};
static struct umr_bitfield mmDIO_MEM_PWR_STATUS1[] = {
	 { "AFMT0_MEM_PWR_STATE", 0, 0, &umr_bitfield_default },
	 { "AFMT1_MEM_PWR_STATE", 2, 2, &umr_bitfield_default },
	 { "AFMT2_MEM_PWR_STATE", 4, 4, &umr_bitfield_default },
	 { "AFMT3_MEM_PWR_STATE", 6, 6, &umr_bitfield_default },
	 { "AFMT4_MEM_PWR_STATE", 8, 8, &umr_bitfield_default },
	 { "AFMT5_MEM_PWR_STATE", 10, 10, &umr_bitfield_default },
};
static struct umr_bitfield mmDIO_CLK_CNTL2[] = {
	 { "DIO_TEST_CLK_SEL", 0, 6, &umr_bitfield_default },
	 { "SOCCLK_G_AFMTA_GATE_DIS", 7, 7, &umr_bitfield_default },
	 { "SOCCLK_G_AFMTB_GATE_DIS", 8, 8, &umr_bitfield_default },
	 { "SOCCLK_G_AFMTC_GATE_DIS", 9, 9, &umr_bitfield_default },
	 { "SOCCLK_G_AFMTD_GATE_DIS", 10, 10, &umr_bitfield_default },
	 { "SOCCLK_G_AFMTE_GATE_DIS", 11, 11, &umr_bitfield_default },
	 { "SOCCLK_G_AFMTF_GATE_DIS", 12, 12, &umr_bitfield_default },
	 { "SOCCLK_G_AFMTG_GATE_DIS", 13, 13, &umr_bitfield_default },
	 { "SYMCLKA_FE_G_AFMT_GATE_DIS", 17, 17, &umr_bitfield_default },
	 { "SYMCLKB_FE_G_AFMT_GATE_DIS", 18, 18, &umr_bitfield_default },
	 { "SYMCLKC_FE_G_AFMT_GATE_DIS", 19, 19, &umr_bitfield_default },
	 { "SYMCLKD_FE_G_AFMT_GATE_DIS", 20, 20, &umr_bitfield_default },
	 { "SYMCLKE_FE_G_AFMT_GATE_DIS", 21, 21, &umr_bitfield_default },
	 { "SYMCLKF_FE_G_AFMT_GATE_DIS", 22, 22, &umr_bitfield_default },
	 { "SYMCLKG_FE_G_AFMT_GATE_DIS", 23, 23, &umr_bitfield_default },
};
static struct umr_bitfield mmDIO_CLK_CNTL3[] = {
	 { "SYMCLKA_FE_G_TMDS_GATE_DIS", 0, 0, &umr_bitfield_default },
	 { "SYMCLKB_FE_G_TMDS_GATE_DIS", 1, 1, &umr_bitfield_default },
	 { "SYMCLKC_FE_G_TMDS_GATE_DIS", 2, 2, &umr_bitfield_default },
	 { "SYMCLKD_FE_G_TMDS_GATE_DIS", 3, 3, &umr_bitfield_default },
	 { "SYMCLKE_FE_G_TMDS_GATE_DIS", 4, 4, &umr_bitfield_default },
	 { "SYMCLKF_FE_G_TMDS_GATE_DIS", 5, 5, &umr_bitfield_default },
	 { "SYMCLKG_FE_G_TMDS_GATE_DIS", 6, 6, &umr_bitfield_default },
	 { "SYMCLKA_G_TMDS_GATE_DIS", 10, 10, &umr_bitfield_default },
	 { "SYMCLKB_G_TMDS_GATE_DIS", 11, 11, &umr_bitfield_default },
	 { "SYMCLKC_G_TMDS_GATE_DIS", 12, 12, &umr_bitfield_default },
	 { "SYMCLKD_G_TMDS_GATE_DIS", 13, 13, &umr_bitfield_default },
	 { "SYMCLKE_G_TMDS_GATE_DIS", 14, 14, &umr_bitfield_default },
	 { "SYMCLKF_G_TMDS_GATE_DIS", 15, 15, &umr_bitfield_default },
	 { "SYMCLKG_G_TMDS_GATE_DIS", 16, 16, &umr_bitfield_default },
};
static struct umr_bitfield mmDIO_HDMI_RXSTATUS_TIMER_CONTROL[] = {
	 { "DIO_HDMI_RXSTATUS_TIMER_ENABLE", 0, 0, &umr_bitfield_default },
	 { "DIO_HDMI_RXSTATUS_TIMER_TYPE", 4, 4, &umr_bitfield_default },
	 { "DIO_HDMI_RXSTATUS_TIMER_STATUS", 8, 8, &umr_bitfield_default },
	 { "DIO_HDMI_RXSTATUS_TIMER_MASK", 12, 12, &umr_bitfield_default },
	 { "DIO_HDMI_RXSTATUS_TIMER_INTERVAL", 16, 27, &umr_bitfield_default },
};
static struct umr_bitfield mmDIO_PSP_INTERRUPT_STATUS[] = {
	 { "DIO_PSP_INTERRUPT_STATUS", 0, 0, &umr_bitfield_default },
	 { "DIO_PSP_INTERRUPT_MESSAGE", 1, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDIO_PSP_INTERRUPT_CLEAR[] = {
	 { "DIO_PSP_INTERRUPT_CLEAR", 0, 0, &umr_bitfield_default },
};
static struct umr_bitfield mmDIO_GENERIC_INTERRUPT_MESSAGE[] = {
	 { "DIO_GENERIC_INTERRUPT_STATUS", 0, 0, &umr_bitfield_default },
	 { "DIO_GENERIC_INTERRUPT_MESSAGE", 1, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDIO_GENERIC_INTERRUPT_CLEAR[] = {
	 { "DIO_GENERIC_INTERRUPT_CLEAR", 0, 0, &umr_bitfield_default },
};
static struct umr_bitfield mmHPD0_DC_HPD_INT_STATUS[] = {
	 { "DC_HPD_INT_STATUS", 0, 0, &umr_bitfield_default },
	 { "DC_HPD_SENSE", 1, 1, &umr_bitfield_default },
	 { "DC_HPD_SENSE_DELAYED", 4, 4, &umr_bitfield_default },
	 { "DC_HPD_RX_INT_STATUS", 8, 8, &umr_bitfield_default },
	 { "DC_HPD_TOGGLE_FILT_CON_TIMER_VAL", 12, 19, &umr_bitfield_default },
	 { "DC_HPD_TOGGLE_FILT_DISCON_TIMER_VAL", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmHPD0_DC_HPD_INT_CONTROL[] = {
	 { "DC_HPD_INT_ACK", 0, 0, &umr_bitfield_default },
	 { "DC_HPD_INT_POLARITY", 8, 8, &umr_bitfield_default },
	 { "DC_HPD_INT_EN", 16, 16, &umr_bitfield_default },
	 { "DC_HPD_RX_INT_ACK", 20, 20, &umr_bitfield_default },
	 { "DC_HPD_RX_INT_EN", 24, 24, &umr_bitfield_default },
};
static struct umr_bitfield mmHPD0_DC_HPD_CONTROL[] = {
	 { "DC_HPD_CONNECTION_TIMER", 0, 12, &umr_bitfield_default },
	 { "DC_HPD_RX_INT_TIMER", 16, 25, &umr_bitfield_default },
	 { "DC_HPD_EN", 28, 28, &umr_bitfield_default },
};
static struct umr_bitfield mmHPD0_DC_HPD_FAST_TRAIN_CNTL[] = {
	 { "DC_HPD_CONNECT_AUX_TX_DELAY", 0, 7, &umr_bitfield_default },
	 { "DC_HPD_CONNECT_FAST_TRAIN_DELAY", 12, 19, &umr_bitfield_default },
	 { "DC_HPD_CONNECT_AUX_TX_EN", 24, 24, &umr_bitfield_default },
	 { "DC_HPD_CONNECT_FAST_TRAIN_EN", 28, 28, &umr_bitfield_default },
};
static struct umr_bitfield mmHPD0_DC_HPD_TOGGLE_FILT_CNTL[] = {
	 { "DC_HPD_CONNECT_INT_DELAY", 0, 7, &umr_bitfield_default },
	 { "DC_HPD_DISCONNECT_INT_DELAY", 20, 27, &umr_bitfield_default },
};
static struct umr_bitfield mmHPD1_DC_HPD_INT_STATUS[] = {
	 { "DC_HPD_INT_STATUS", 0, 0, &umr_bitfield_default },
	 { "DC_HPD_SENSE", 1, 1, &umr_bitfield_default },
	 { "DC_HPD_SENSE_DELAYED", 4, 4, &umr_bitfield_default },
	 { "DC_HPD_RX_INT_STATUS", 8, 8, &umr_bitfield_default },
	 { "DC_HPD_TOGGLE_FILT_CON_TIMER_VAL", 12, 19, &umr_bitfield_default },
	 { "DC_HPD_TOGGLE_FILT_DISCON_TIMER_VAL", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmHPD1_DC_HPD_INT_CONTROL[] = {
	 { "DC_HPD_INT_ACK", 0, 0, &umr_bitfield_default },
	 { "DC_HPD_INT_POLARITY", 8, 8, &umr_bitfield_default },
	 { "DC_HPD_INT_EN", 16, 16, &umr_bitfield_default },
	 { "DC_HPD_RX_INT_ACK", 20, 20, &umr_bitfield_default },
	 { "DC_HPD_RX_INT_EN", 24, 24, &umr_bitfield_default },
};
static struct umr_bitfield mmHPD1_DC_HPD_CONTROL[] = {
	 { "DC_HPD_CONNECTION_TIMER", 0, 12, &umr_bitfield_default },
	 { "DC_HPD_RX_INT_TIMER", 16, 25, &umr_bitfield_default },
	 { "DC_HPD_EN", 28, 28, &umr_bitfield_default },
};
static struct umr_bitfield mmHPD1_DC_HPD_FAST_TRAIN_CNTL[] = {
	 { "DC_HPD_CONNECT_AUX_TX_DELAY", 0, 7, &umr_bitfield_default },
	 { "DC_HPD_CONNECT_FAST_TRAIN_DELAY", 12, 19, &umr_bitfield_default },
	 { "DC_HPD_CONNECT_AUX_TX_EN", 24, 24, &umr_bitfield_default },
	 { "DC_HPD_CONNECT_FAST_TRAIN_EN", 28, 28, &umr_bitfield_default },
};
static struct umr_bitfield mmHPD1_DC_HPD_TOGGLE_FILT_CNTL[] = {
	 { "DC_HPD_CONNECT_INT_DELAY", 0, 7, &umr_bitfield_default },
	 { "DC_HPD_DISCONNECT_INT_DELAY", 20, 27, &umr_bitfield_default },
};
static struct umr_bitfield mmHPD2_DC_HPD_INT_STATUS[] = {
	 { "DC_HPD_INT_STATUS", 0, 0, &umr_bitfield_default },
	 { "DC_HPD_SENSE", 1, 1, &umr_bitfield_default },
	 { "DC_HPD_SENSE_DELAYED", 4, 4, &umr_bitfield_default },
	 { "DC_HPD_RX_INT_STATUS", 8, 8, &umr_bitfield_default },
	 { "DC_HPD_TOGGLE_FILT_CON_TIMER_VAL", 12, 19, &umr_bitfield_default },
	 { "DC_HPD_TOGGLE_FILT_DISCON_TIMER_VAL", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmHPD2_DC_HPD_INT_CONTROL[] = {
	 { "DC_HPD_INT_ACK", 0, 0, &umr_bitfield_default },
	 { "DC_HPD_INT_POLARITY", 8, 8, &umr_bitfield_default },
	 { "DC_HPD_INT_EN", 16, 16, &umr_bitfield_default },
	 { "DC_HPD_RX_INT_ACK", 20, 20, &umr_bitfield_default },
	 { "DC_HPD_RX_INT_EN", 24, 24, &umr_bitfield_default },
};
static struct umr_bitfield mmHPD2_DC_HPD_CONTROL[] = {
	 { "DC_HPD_CONNECTION_TIMER", 0, 12, &umr_bitfield_default },
	 { "DC_HPD_RX_INT_TIMER", 16, 25, &umr_bitfield_default },
	 { "DC_HPD_EN", 28, 28, &umr_bitfield_default },
};
static struct umr_bitfield mmHPD2_DC_HPD_FAST_TRAIN_CNTL[] = {
	 { "DC_HPD_CONNECT_AUX_TX_DELAY", 0, 7, &umr_bitfield_default },
	 { "DC_HPD_CONNECT_FAST_TRAIN_DELAY", 12, 19, &umr_bitfield_default },
	 { "DC_HPD_CONNECT_AUX_TX_EN", 24, 24, &umr_bitfield_default },
	 { "DC_HPD_CONNECT_FAST_TRAIN_EN", 28, 28, &umr_bitfield_default },
};
static struct umr_bitfield mmHPD2_DC_HPD_TOGGLE_FILT_CNTL[] = {
	 { "DC_HPD_CONNECT_INT_DELAY", 0, 7, &umr_bitfield_default },
	 { "DC_HPD_DISCONNECT_INT_DELAY", 20, 27, &umr_bitfield_default },
};
static struct umr_bitfield mmHPD3_DC_HPD_INT_STATUS[] = {
	 { "DC_HPD_INT_STATUS", 0, 0, &umr_bitfield_default },
	 { "DC_HPD_SENSE", 1, 1, &umr_bitfield_default },
	 { "DC_HPD_SENSE_DELAYED", 4, 4, &umr_bitfield_default },
	 { "DC_HPD_RX_INT_STATUS", 8, 8, &umr_bitfield_default },
	 { "DC_HPD_TOGGLE_FILT_CON_TIMER_VAL", 12, 19, &umr_bitfield_default },
	 { "DC_HPD_TOGGLE_FILT_DISCON_TIMER_VAL", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmHPD3_DC_HPD_INT_CONTROL[] = {
	 { "DC_HPD_INT_ACK", 0, 0, &umr_bitfield_default },
	 { "DC_HPD_INT_POLARITY", 8, 8, &umr_bitfield_default },
	 { "DC_HPD_INT_EN", 16, 16, &umr_bitfield_default },
	 { "DC_HPD_RX_INT_ACK", 20, 20, &umr_bitfield_default },
	 { "DC_HPD_RX_INT_EN", 24, 24, &umr_bitfield_default },
};
static struct umr_bitfield mmHPD3_DC_HPD_CONTROL[] = {
	 { "DC_HPD_CONNECTION_TIMER", 0, 12, &umr_bitfield_default },
	 { "DC_HPD_RX_INT_TIMER", 16, 25, &umr_bitfield_default },
	 { "DC_HPD_EN", 28, 28, &umr_bitfield_default },
};
static struct umr_bitfield mmHPD3_DC_HPD_FAST_TRAIN_CNTL[] = {
	 { "DC_HPD_CONNECT_AUX_TX_DELAY", 0, 7, &umr_bitfield_default },
	 { "DC_HPD_CONNECT_FAST_TRAIN_DELAY", 12, 19, &umr_bitfield_default },
	 { "DC_HPD_CONNECT_AUX_TX_EN", 24, 24, &umr_bitfield_default },
	 { "DC_HPD_CONNECT_FAST_TRAIN_EN", 28, 28, &umr_bitfield_default },
};
static struct umr_bitfield mmHPD3_DC_HPD_TOGGLE_FILT_CNTL[] = {
	 { "DC_HPD_CONNECT_INT_DELAY", 0, 7, &umr_bitfield_default },
	 { "DC_HPD_DISCONNECT_INT_DELAY", 20, 27, &umr_bitfield_default },
};
static struct umr_bitfield mmHPD4_DC_HPD_INT_STATUS[] = {
	 { "DC_HPD_INT_STATUS", 0, 0, &umr_bitfield_default },
	 { "DC_HPD_SENSE", 1, 1, &umr_bitfield_default },
	 { "DC_HPD_SENSE_DELAYED", 4, 4, &umr_bitfield_default },
	 { "DC_HPD_RX_INT_STATUS", 8, 8, &umr_bitfield_default },
	 { "DC_HPD_TOGGLE_FILT_CON_TIMER_VAL", 12, 19, &umr_bitfield_default },
	 { "DC_HPD_TOGGLE_FILT_DISCON_TIMER_VAL", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmHPD4_DC_HPD_INT_CONTROL[] = {
	 { "DC_HPD_INT_ACK", 0, 0, &umr_bitfield_default },
	 { "DC_HPD_INT_POLARITY", 8, 8, &umr_bitfield_default },
	 { "DC_HPD_INT_EN", 16, 16, &umr_bitfield_default },
	 { "DC_HPD_RX_INT_ACK", 20, 20, &umr_bitfield_default },
	 { "DC_HPD_RX_INT_EN", 24, 24, &umr_bitfield_default },
};
static struct umr_bitfield mmHPD4_DC_HPD_CONTROL[] = {
	 { "DC_HPD_CONNECTION_TIMER", 0, 12, &umr_bitfield_default },
	 { "DC_HPD_RX_INT_TIMER", 16, 25, &umr_bitfield_default },
	 { "DC_HPD_EN", 28, 28, &umr_bitfield_default },
};
static struct umr_bitfield mmHPD4_DC_HPD_FAST_TRAIN_CNTL[] = {
	 { "DC_HPD_CONNECT_AUX_TX_DELAY", 0, 7, &umr_bitfield_default },
	 { "DC_HPD_CONNECT_FAST_TRAIN_DELAY", 12, 19, &umr_bitfield_default },
	 { "DC_HPD_CONNECT_AUX_TX_EN", 24, 24, &umr_bitfield_default },
	 { "DC_HPD_CONNECT_FAST_TRAIN_EN", 28, 28, &umr_bitfield_default },
};
static struct umr_bitfield mmHPD4_DC_HPD_TOGGLE_FILT_CNTL[] = {
	 { "DC_HPD_CONNECT_INT_DELAY", 0, 7, &umr_bitfield_default },
	 { "DC_HPD_DISCONNECT_INT_DELAY", 20, 27, &umr_bitfield_default },
};
static struct umr_bitfield mmHPD5_DC_HPD_INT_STATUS[] = {
	 { "DC_HPD_INT_STATUS", 0, 0, &umr_bitfield_default },
	 { "DC_HPD_SENSE", 1, 1, &umr_bitfield_default },
	 { "DC_HPD_SENSE_DELAYED", 4, 4, &umr_bitfield_default },
	 { "DC_HPD_RX_INT_STATUS", 8, 8, &umr_bitfield_default },
	 { "DC_HPD_TOGGLE_FILT_CON_TIMER_VAL", 12, 19, &umr_bitfield_default },
	 { "DC_HPD_TOGGLE_FILT_DISCON_TIMER_VAL", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmHPD5_DC_HPD_INT_CONTROL[] = {
	 { "DC_HPD_INT_ACK", 0, 0, &umr_bitfield_default },
	 { "DC_HPD_INT_POLARITY", 8, 8, &umr_bitfield_default },
	 { "DC_HPD_INT_EN", 16, 16, &umr_bitfield_default },
	 { "DC_HPD_RX_INT_ACK", 20, 20, &umr_bitfield_default },
	 { "DC_HPD_RX_INT_EN", 24, 24, &umr_bitfield_default },
};
static struct umr_bitfield mmHPD5_DC_HPD_CONTROL[] = {
	 { "DC_HPD_CONNECTION_TIMER", 0, 12, &umr_bitfield_default },
	 { "DC_HPD_RX_INT_TIMER", 16, 25, &umr_bitfield_default },
	 { "DC_HPD_EN", 28, 28, &umr_bitfield_default },
};
static struct umr_bitfield mmHPD5_DC_HPD_FAST_TRAIN_CNTL[] = {
	 { "DC_HPD_CONNECT_AUX_TX_DELAY", 0, 7, &umr_bitfield_default },
	 { "DC_HPD_CONNECT_FAST_TRAIN_DELAY", 12, 19, &umr_bitfield_default },
	 { "DC_HPD_CONNECT_AUX_TX_EN", 24, 24, &umr_bitfield_default },
	 { "DC_HPD_CONNECT_FAST_TRAIN_EN", 28, 28, &umr_bitfield_default },
};
static struct umr_bitfield mmHPD5_DC_HPD_TOGGLE_FILT_CNTL[] = {
	 { "DC_HPD_CONNECT_INT_DELAY", 0, 7, &umr_bitfield_default },
	 { "DC_HPD_DISCONNECT_INT_DELAY", 20, 27, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_PERFMON19_PERFCOUNTER_CNTL[] = {
	 { "PERFCOUNTER_EVENT_SEL", 0, 8, &umr_bitfield_default },
	 { "PERFCOUNTER_CVALUE_SEL", 9, 11, &umr_bitfield_default },
	 { "PERFCOUNTER_INC_MODE", 12, 14, &umr_bitfield_default },
	 { "PERFCOUNTER_HW_CNTL_SEL", 15, 15, &umr_bitfield_default },
	 { "PERFCOUNTER_RUNEN_MODE", 16, 16, &umr_bitfield_default },
	 { "PERFCOUNTER_CNTOFF_START_DIS", 22, 22, &umr_bitfield_default },
	 { "PERFCOUNTER_RESTART_EN", 23, 23, &umr_bitfield_default },
	 { "PERFCOUNTER_INT_EN", 24, 24, &umr_bitfield_default },
	 { "PERFCOUNTER_OFF_MASK", 25, 25, &umr_bitfield_default },
	 { "PERFCOUNTER_ACTIVE", 26, 26, &umr_bitfield_default },
	 { "PERFCOUNTER_CNTL_SEL", 29, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_PERFMON19_PERFCOUNTER_CNTL2[] = {
	 { "PERFCOUNTER_COUNTED_VALUE_TYPE", 0, 1, &umr_bitfield_default },
	 { "PERFCOUNTER_HW_STOP1_SEL", 2, 2, &umr_bitfield_default },
	 { "PERFCOUNTER_HW_STOP2_SEL", 3, 3, &umr_bitfield_default },
	 { "PERFCOUNTER_CNTOFF_SEL", 8, 13, &umr_bitfield_default },
	 { "PERFCOUNTER_CNTL2_SEL", 29, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_PERFMON19_PERFCOUNTER_STATE[] = {
	 { "PERFCOUNTER_CNT0_STATE", 0, 1, &umr_bitfield_default },
	 { "PERFCOUNTER_STATE_SEL0", 2, 2, &umr_bitfield_default },
	 { "PERFCOUNTER_CNT1_STATE", 4, 5, &umr_bitfield_default },
	 { "PERFCOUNTER_STATE_SEL1", 6, 6, &umr_bitfield_default },
	 { "PERFCOUNTER_CNT2_STATE", 8, 9, &umr_bitfield_default },
	 { "PERFCOUNTER_STATE_SEL2", 10, 10, &umr_bitfield_default },
	 { "PERFCOUNTER_CNT3_STATE", 12, 13, &umr_bitfield_default },
	 { "PERFCOUNTER_STATE_SEL3", 14, 14, &umr_bitfield_default },
	 { "PERFCOUNTER_CNT4_STATE", 16, 17, &umr_bitfield_default },
	 { "PERFCOUNTER_STATE_SEL4", 18, 18, &umr_bitfield_default },
	 { "PERFCOUNTER_CNT5_STATE", 20, 21, &umr_bitfield_default },
	 { "PERFCOUNTER_STATE_SEL5", 22, 22, &umr_bitfield_default },
	 { "PERFCOUNTER_CNT6_STATE", 24, 25, &umr_bitfield_default },
	 { "PERFCOUNTER_STATE_SEL6", 26, 26, &umr_bitfield_default },
	 { "PERFCOUNTER_CNT7_STATE", 28, 29, &umr_bitfield_default },
	 { "PERFCOUNTER_STATE_SEL7", 30, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_PERFMON19_PERFMON_CNTL[] = {
	 { "PERFMON_STATE", 0, 1, &umr_bitfield_default },
	 { "PERFMON_RPT_COUNT", 8, 27, &umr_bitfield_default },
	 { "PERFMON_CNTOFF_AND_OR", 28, 28, &umr_bitfield_default },
	 { "PERFMON_CNTOFF_INT_EN", 29, 29, &umr_bitfield_default },
	 { "PERFMON_CNTOFF_INT_STATUS", 30, 30, &umr_bitfield_default },
	 { "PERFMON_CNTOFF_INT_ACK", 31, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_PERFMON19_PERFMON_CNTL2[] = {
	 { "PERFMON_CNTOFF_INT_TYPE", 0, 0, &umr_bitfield_default },
	 { "PERFMON_CLK_ENABLE", 1, 1, &umr_bitfield_default },
	 { "PERFMON_RUN_ENABLE_START_SEL", 2, 9, &umr_bitfield_default },
	 { "PERFMON_RUN_ENABLE_STOP_SEL", 10, 17, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_PERFMON19_PERFMON_CVALUE_INT_MISC[] = {
	 { "PERFCOUNTER_INT0_STATUS", 0, 0, &umr_bitfield_default },
	 { "PERFCOUNTER_INT1_STATUS", 1, 1, &umr_bitfield_default },
	 { "PERFCOUNTER_INT2_STATUS", 2, 2, &umr_bitfield_default },
	 { "PERFCOUNTER_INT3_STATUS", 3, 3, &umr_bitfield_default },
	 { "PERFCOUNTER_INT4_STATUS", 4, 4, &umr_bitfield_default },
	 { "PERFCOUNTER_INT5_STATUS", 5, 5, &umr_bitfield_default },
	 { "PERFCOUNTER_INT6_STATUS", 6, 6, &umr_bitfield_default },
	 { "PERFCOUNTER_INT7_STATUS", 7, 7, &umr_bitfield_default },
	 { "PERFCOUNTER_INT0_ACK", 8, 8, &umr_bitfield_default },
	 { "PERFCOUNTER_INT1_ACK", 9, 9, &umr_bitfield_default },
	 { "PERFCOUNTER_INT2_ACK", 10, 10, &umr_bitfield_default },
	 { "PERFCOUNTER_INT3_ACK", 11, 11, &umr_bitfield_default },
	 { "PERFCOUNTER_INT4_ACK", 12, 12, &umr_bitfield_default },
	 { "PERFCOUNTER_INT5_ACK", 13, 13, &umr_bitfield_default },
	 { "PERFCOUNTER_INT6_ACK", 14, 14, &umr_bitfield_default },
	 { "PERFCOUNTER_INT7_ACK", 15, 15, &umr_bitfield_default },
	 { "PERFMON_CVALUE_HI", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_PERFMON19_PERFMON_CVALUE_LOW[] = {
	 { "PERFMON_CVALUE_LOW", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_PERFMON19_PERFMON_HI[] = {
	 { "PERFMON_HI", 0, 15, &umr_bitfield_default },
	 { "PERFMON_READ_SEL", 29, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_PERFMON19_PERFMON_LOW[] = {
	 { "PERFMON_LOW", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDP_AUX0_AUX_CONTROL[] = {
	 { "AUX_EN", 0, 0, &umr_bitfield_default },
	 { "AUX_RESET", 4, 4, &umr_bitfield_default },
	 { "AUX_RESET_DONE", 5, 5, &umr_bitfield_default },
	 { "AUX_LS_READ_EN", 8, 8, &umr_bitfield_default },
	 { "AUX_LS_UPDATE_DISABLE", 12, 12, &umr_bitfield_default },
	 { "AUX_IGNORE_HPD_DISCON", 16, 16, &umr_bitfield_default },
	 { "AUX_MODE_DET_EN", 18, 18, &umr_bitfield_default },
	 { "AUX_HPD_SEL", 20, 22, &umr_bitfield_default },
	 { "AUX_IMPCAL_REQ_EN", 24, 24, &umr_bitfield_default },
	 { "AUX_TEST_MODE", 28, 28, &umr_bitfield_default },
	 { "AUX_DEGLITCH_EN", 29, 29, &umr_bitfield_default },
	 { "SPARE_0", 30, 30, &umr_bitfield_default },
	 { "SPARE_1", 31, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDP_AUX0_AUX_SW_CONTROL[] = {
	 { "AUX_SW_GO", 0, 0, &umr_bitfield_default },
	 { "AUX_LS_READ_TRIG", 2, 2, &umr_bitfield_default },
	 { "AUX_SW_START_DELAY", 4, 7, &umr_bitfield_default },
	 { "AUX_SW_WR_BYTES", 16, 20, &umr_bitfield_default },
};
static struct umr_bitfield mmDP_AUX0_AUX_ARB_CONTROL[] = {
	 { "AUX_ARB_PRIORITY", 0, 1, &umr_bitfield_default },
	 { "AUX_REG_RW_CNTL_STATUS", 2, 3, &umr_bitfield_default },
	 { "AUX_NO_QUEUED_SW_GO", 8, 8, &umr_bitfield_default },
	 { "AUX_NO_QUEUED_LS_GO", 10, 10, &umr_bitfield_default },
	 { "AUX_SW_USE_AUX_REG_REQ", 16, 16, &umr_bitfield_default },
	 { "AUX_SW_PENDING_USE_AUX_REG_REQ", 16, 16, &umr_bitfield_default },
	 { "AUX_SW_DONE_USING_AUX_REG", 17, 17, &umr_bitfield_default },
	 { "AUX_DMCU_USE_AUX_REG_REQ", 24, 24, &umr_bitfield_default },
	 { "AUX_DMCU_PENDING_USE_AUX_REG_REQ", 24, 24, &umr_bitfield_default },
	 { "AUX_DMCU_DONE_USING_AUX_REG", 25, 25, &umr_bitfield_default },
};
static struct umr_bitfield mmDP_AUX0_AUX_INTERRUPT_CONTROL[] = {
	 { "AUX_SW_DONE_INT", 0, 0, &umr_bitfield_default },
	 { "AUX_SW_DONE_ACK", 1, 1, &umr_bitfield_default },
	 { "AUX_SW_DONE_MASK", 2, 2, &umr_bitfield_default },
	 { "AUX_LS_DONE_INT", 4, 4, &umr_bitfield_default },
	 { "AUX_LS_DONE_ACK", 5, 5, &umr_bitfield_default },
	 { "AUX_LS_DONE_MASK", 6, 6, &umr_bitfield_default },
	 { "AUX_GTC_SYNC_LOCK_DONE_INT", 8, 8, &umr_bitfield_default },
	 { "AUX_GTC_SYNC_LOCK_DONE_ACK", 9, 9, &umr_bitfield_default },
	 { "AUX_GTC_SYNC_LOCK_DONE_INT_MASK", 10, 10, &umr_bitfield_default },
	 { "AUX_GTC_SYNC_ERROR_INT", 12, 12, &umr_bitfield_default },
	 { "AUX_GTC_SYNC_ERROR_ACK", 13, 13, &umr_bitfield_default },
	 { "AUX_GTC_SYNC_ERROR_INT_MASK", 14, 14, &umr_bitfield_default },
};
static struct umr_bitfield mmDP_AUX0_AUX_SW_STATUS[] = {
	 { "AUX_SW_DONE", 0, 0, &umr_bitfield_default },
	 { "AUX_SW_REQ", 1, 1, &umr_bitfield_default },
	 { "AUX_SW_RX_TIMEOUT_STATE", 4, 6, &umr_bitfield_default },
	 { "AUX_SW_RX_TIMEOUT", 7, 7, &umr_bitfield_default },
	 { "AUX_SW_RX_OVERFLOW", 8, 8, &umr_bitfield_default },
	 { "AUX_SW_HPD_DISCON", 9, 9, &umr_bitfield_default },
	 { "AUX_SW_RX_PARTIAL_BYTE", 10, 10, &umr_bitfield_default },
	 { "AUX_SW_NON_AUX_MODE", 11, 11, &umr_bitfield_default },
	 { "AUX_SW_RX_MIN_COUNT_VIOL", 12, 12, &umr_bitfield_default },
	 { "AUX_SW_RX_INVALID_STOP", 14, 14, &umr_bitfield_default },
	 { "AUX_SW_RX_SYNC_INVALID_L", 17, 17, &umr_bitfield_default },
	 { "AUX_SW_RX_SYNC_INVALID_H", 18, 18, &umr_bitfield_default },
	 { "AUX_SW_RX_INVALID_START", 19, 19, &umr_bitfield_default },
	 { "AUX_SW_RX_RECV_NO_DET", 20, 20, &umr_bitfield_default },
	 { "AUX_SW_RX_RECV_INVALID_H", 22, 22, &umr_bitfield_default },
	 { "AUX_SW_RX_RECV_INVALID_L", 23, 23, &umr_bitfield_default },
	 { "AUX_SW_REPLY_BYTE_COUNT", 24, 28, &umr_bitfield_default },
	 { "AUX_ARB_STATUS", 30, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDP_AUX0_AUX_LS_STATUS[] = {
	 { "AUX_LS_DONE", 0, 0, &umr_bitfield_default },
	 { "AUX_LS_REQ", 1, 1, &umr_bitfield_default },
	 { "AUX_LS_RX_TIMEOUT_STATE", 4, 6, &umr_bitfield_default },
	 { "AUX_LS_RX_TIMEOUT", 7, 7, &umr_bitfield_default },
	 { "AUX_LS_RX_OVERFLOW", 8, 8, &umr_bitfield_default },
	 { "AUX_LS_HPD_DISCON", 9, 9, &umr_bitfield_default },
	 { "AUX_LS_RX_PARTIAL_BYTE", 10, 10, &umr_bitfield_default },
	 { "AUX_LS_NON_AUX_MODE", 11, 11, &umr_bitfield_default },
	 { "AUX_LS_RX_MIN_COUNT_VIOL", 12, 12, &umr_bitfield_default },
	 { "AUX_LS_RX_INVALID_STOP", 14, 14, &umr_bitfield_default },
	 { "AUX_LS_RX_SYNC_INVALID_L", 17, 17, &umr_bitfield_default },
	 { "AUX_LS_RX_SYNC_INVALID_H", 18, 18, &umr_bitfield_default },
	 { "AUX_LS_RX_INVALID_START", 19, 19, &umr_bitfield_default },
	 { "AUX_LS_RX_RECV_NO_DET", 20, 20, &umr_bitfield_default },
	 { "AUX_LS_RX_RECV_INVALID_H", 22, 22, &umr_bitfield_default },
	 { "AUX_LS_RX_RECV_INVALID_L", 23, 23, &umr_bitfield_default },
	 { "AUX_LS_REPLY_BYTE_COUNT", 24, 28, &umr_bitfield_default },
	 { "AUX_LS_CP_IRQ", 29, 29, &umr_bitfield_default },
	 { "AUX_LS_UPDATED", 30, 30, &umr_bitfield_default },
	 { "AUX_LS_UPDATED_ACK", 31, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDP_AUX0_AUX_SW_DATA[] = {
	 { "AUX_SW_DATA_RW", 0, 0, &umr_bitfield_default },
	 { "AUX_SW_DATA", 8, 15, &umr_bitfield_default },
	 { "AUX_SW_INDEX", 16, 20, &umr_bitfield_default },
	 { "AUX_SW_AUTOINCREMENT_DISABLE", 31, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDP_AUX0_AUX_LS_DATA[] = {
	 { "AUX_LS_DATA", 8, 15, &umr_bitfield_default },
	 { "AUX_LS_INDEX", 16, 20, &umr_bitfield_default },
};
static struct umr_bitfield mmDP_AUX0_AUX_DPHY_TX_REF_CONTROL[] = {
	 { "AUX_TX_REF_SEL", 0, 0, &umr_bitfield_default },
	 { "AUX_TX_RATE", 4, 5, &umr_bitfield_default },
	 { "AUX_TX_REF_DIV", 16, 24, &umr_bitfield_default },
};
static struct umr_bitfield mmDP_AUX0_AUX_DPHY_TX_CONTROL[] = {
	 { "AUX_TX_PRECHARGE_LEN", 0, 2, &umr_bitfield_default },
	 { "AUX_TX_PRECHARGE_SYMBOLS", 8, 13, &umr_bitfield_default },
	 { "AUX_MODE_DET_CHECK_DELAY", 16, 18, &umr_bitfield_default },
};
static struct umr_bitfield mmDP_AUX0_AUX_DPHY_RX_CONTROL0[] = {
	 { "AUX_RX_START_WINDOW", 4, 6, &umr_bitfield_default },
	 { "AUX_RX_RECEIVE_WINDOW", 8, 10, &umr_bitfield_default },
	 { "AUX_RX_HALF_SYM_DETECT_LEN", 12, 13, &umr_bitfield_default },
	 { "AUX_RX_TRANSITION_FILTER_EN", 16, 16, &umr_bitfield_default },
	 { "AUX_RX_ALLOW_BELOW_THRESHOLD_PHASE_DETECT", 17, 17, &umr_bitfield_default },
	 { "AUX_RX_ALLOW_BELOW_THRESHOLD_START", 18, 18, &umr_bitfield_default },
	 { "AUX_RX_ALLOW_BELOW_THRESHOLD_STOP", 19, 19, &umr_bitfield_default },
	 { "AUX_RX_PHASE_DETECT_LEN", 20, 21, &umr_bitfield_default },
	 { "AUX_RX_TIMEOUT_LEN", 24, 26, &umr_bitfield_default },
	 { "AUX_RX_DETECTION_THRESHOLD", 28, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmDP_AUX0_AUX_DPHY_RX_CONTROL1[] = {
	 { "AUX_RX_PRECHARGE_SKIP", 0, 7, &umr_bitfield_default },
};
static struct umr_bitfield mmDP_AUX0_AUX_DPHY_TX_STATUS[] = {
	 { "AUX_TX_ACTIVE", 0, 0, &umr_bitfield_default },
	 { "AUX_TX_STATE", 4, 6, &umr_bitfield_default },
	 { "AUX_TX_HALF_SYM_PERIOD", 16, 24, &umr_bitfield_default },
};
static struct umr_bitfield mmDP_AUX0_AUX_DPHY_RX_STATUS[] = {
	 { "AUX_RX_STATE", 0, 2, &umr_bitfield_default },
	 { "AUX_RX_SYNC_VALID_COUNT", 8, 12, &umr_bitfield_default },
	 { "AUX_RX_HALF_SYM_PERIOD_FRACT", 16, 20, &umr_bitfield_default },
	 { "AUX_RX_HALF_SYM_PERIOD", 21, 29, &umr_bitfield_default },
};
static struct umr_bitfield mmDP_AUX0_AUX_GTC_SYNC_ERROR_CONTROL[] = {
	 { "AUX_GTC_POTENTIAL_ERROR_THRESHOLD", 0, 4, &umr_bitfield_default },
	 { "AUX_GTC_DEFINITE_ERROR_THRESHOLD", 8, 12, &umr_bitfield_default },
	 { "AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_LEN", 16, 17, &umr_bitfield_default },
	 { "AUX_GTC_SYNC_NUM_RETRY_FOR_LOCK_MAINT", 20, 21, &umr_bitfield_default },
};
static struct umr_bitfield mmDP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS[] = {
	 { "AUX_GTC_SYNC_LOCK_ACQ_COMPLETE", 0, 0, &umr_bitfield_default },
	 { "AUX_GTC_SYNC_LOCK_LOST", 4, 4, &umr_bitfield_default },
	 { "AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_OCCURRED", 8, 8, &umr_bitfield_default },
	 { "AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_STATE", 9, 12, &umr_bitfield_default },
	 { "AUX_GTC_SYNC_PHASE_ADJUST_TIME_VIOL", 16, 16, &umr_bitfield_default },
	 { "AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED", 20, 20, &umr_bitfield_default },
	 { "AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED_ACK", 21, 21, &umr_bitfield_default },
	 { "AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED", 22, 22, &umr_bitfield_default },
	 { "AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED_ACK", 23, 23, &umr_bitfield_default },
	 { "AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED", 24, 24, &umr_bitfield_default },
	 { "AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED_ACK", 25, 25, &umr_bitfield_default },
	 { "AUX_GTC_SYNC_CTRL_STATE", 28, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDP_AUX0_AUX_GTC_SYNC_STATUS[] = {
	 { "AUX_GTC_SYNC_DONE", 0, 0, &umr_bitfield_default },
	 { "AUX_GTC_SYNC_REQ", 1, 1, &umr_bitfield_default },
	 { "AUX_GTC_SYNC_RX_TIMEOUT_STATE", 4, 6, &umr_bitfield_default },
	 { "AUX_GTC_SYNC_TIMEOUT", 7, 7, &umr_bitfield_default },
	 { "AUX_GTC_SYNC_RX_OVERFLOW", 8, 8, &umr_bitfield_default },
	 { "AUX_GTC_SYNC_HPD_DISCON", 9, 9, &umr_bitfield_default },
	 { "AUX_GTC_SYNC_RX_PARTIAL_BYTE", 10, 10, &umr_bitfield_default },
	 { "AUX_GTC_SYNC_NON_AUX_MODE", 11, 11, &umr_bitfield_default },
	 { "AUX_GTC_SYNC_RX_MIN_COUNT_VIOL", 12, 12, &umr_bitfield_default },
	 { "AUX_GTC_SYNC_RX_INVALID_STOP", 14, 14, &umr_bitfield_default },
	 { "AUX_GTC_SYNC_RX_SYNC_INVALID_L", 17, 17, &umr_bitfield_default },
	 { "AUX_GTC_SYNC_RX_SYNC_INVALID_H", 18, 18, &umr_bitfield_default },
	 { "AUX_GTC_SYNC_RX_INVALID_START", 19, 19, &umr_bitfield_default },
	 { "AUX_GTC_SYNC_RX_RECV_NO_DET", 20, 20, &umr_bitfield_default },
	 { "AUX_GTC_SYNC_RX_RECV_INVALID_H", 22, 22, &umr_bitfield_default },
	 { "AUX_GTC_SYNC_RX_RECV_INVALID_L", 23, 23, &umr_bitfield_default },
	 { "AUX_GTC_SYNC_REPLY_BYTE_COUNT", 24, 28, &umr_bitfield_default },
	 { "AUX_GTC_SYNC_NACKED", 29, 29, &umr_bitfield_default },
	 { "AUX_GTC_MASTER_REQ_BY_RX", 30, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmDP_AUX1_AUX_CONTROL[] = {
	 { "AUX_EN", 0, 0, &umr_bitfield_default },
	 { "AUX_RESET", 4, 4, &umr_bitfield_default },
	 { "AUX_RESET_DONE", 5, 5, &umr_bitfield_default },
	 { "AUX_LS_READ_EN", 8, 8, &umr_bitfield_default },
	 { "AUX_LS_UPDATE_DISABLE", 12, 12, &umr_bitfield_default },
	 { "AUX_IGNORE_HPD_DISCON", 16, 16, &umr_bitfield_default },
	 { "AUX_MODE_DET_EN", 18, 18, &umr_bitfield_default },
	 { "AUX_HPD_SEL", 20, 22, &umr_bitfield_default },
	 { "AUX_IMPCAL_REQ_EN", 24, 24, &umr_bitfield_default },
	 { "AUX_TEST_MODE", 28, 28, &umr_bitfield_default },
	 { "AUX_DEGLITCH_EN", 29, 29, &umr_bitfield_default },
	 { "SPARE_0", 30, 30, &umr_bitfield_default },
	 { "SPARE_1", 31, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDP_AUX1_AUX_SW_CONTROL[] = {
	 { "AUX_SW_GO", 0, 0, &umr_bitfield_default },
	 { "AUX_LS_READ_TRIG", 2, 2, &umr_bitfield_default },
	 { "AUX_SW_START_DELAY", 4, 7, &umr_bitfield_default },
	 { "AUX_SW_WR_BYTES", 16, 20, &umr_bitfield_default },
};
static struct umr_bitfield mmDP_AUX1_AUX_ARB_CONTROL[] = {
	 { "AUX_ARB_PRIORITY", 0, 1, &umr_bitfield_default },
	 { "AUX_REG_RW_CNTL_STATUS", 2, 3, &umr_bitfield_default },
	 { "AUX_NO_QUEUED_SW_GO", 8, 8, &umr_bitfield_default },
	 { "AUX_NO_QUEUED_LS_GO", 10, 10, &umr_bitfield_default },
	 { "AUX_SW_USE_AUX_REG_REQ", 16, 16, &umr_bitfield_default },
	 { "AUX_SW_PENDING_USE_AUX_REG_REQ", 16, 16, &umr_bitfield_default },
	 { "AUX_SW_DONE_USING_AUX_REG", 17, 17, &umr_bitfield_default },
	 { "AUX_DMCU_USE_AUX_REG_REQ", 24, 24, &umr_bitfield_default },
	 { "AUX_DMCU_PENDING_USE_AUX_REG_REQ", 24, 24, &umr_bitfield_default },
	 { "AUX_DMCU_DONE_USING_AUX_REG", 25, 25, &umr_bitfield_default },
};
static struct umr_bitfield mmDP_AUX1_AUX_INTERRUPT_CONTROL[] = {
	 { "AUX_SW_DONE_INT", 0, 0, &umr_bitfield_default },
	 { "AUX_SW_DONE_ACK", 1, 1, &umr_bitfield_default },
	 { "AUX_SW_DONE_MASK", 2, 2, &umr_bitfield_default },
	 { "AUX_LS_DONE_INT", 4, 4, &umr_bitfield_default },
	 { "AUX_LS_DONE_ACK", 5, 5, &umr_bitfield_default },
	 { "AUX_LS_DONE_MASK", 6, 6, &umr_bitfield_default },
	 { "AUX_GTC_SYNC_LOCK_DONE_INT", 8, 8, &umr_bitfield_default },
	 { "AUX_GTC_SYNC_LOCK_DONE_ACK", 9, 9, &umr_bitfield_default },
	 { "AUX_GTC_SYNC_LOCK_DONE_INT_MASK", 10, 10, &umr_bitfield_default },
	 { "AUX_GTC_SYNC_ERROR_INT", 12, 12, &umr_bitfield_default },
	 { "AUX_GTC_SYNC_ERROR_ACK", 13, 13, &umr_bitfield_default },
	 { "AUX_GTC_SYNC_ERROR_INT_MASK", 14, 14, &umr_bitfield_default },
};
static struct umr_bitfield mmDP_AUX1_AUX_SW_STATUS[] = {
	 { "AUX_SW_DONE", 0, 0, &umr_bitfield_default },
	 { "AUX_SW_REQ", 1, 1, &umr_bitfield_default },
	 { "AUX_SW_RX_TIMEOUT_STATE", 4, 6, &umr_bitfield_default },
	 { "AUX_SW_RX_TIMEOUT", 7, 7, &umr_bitfield_default },
	 { "AUX_SW_RX_OVERFLOW", 8, 8, &umr_bitfield_default },
	 { "AUX_SW_HPD_DISCON", 9, 9, &umr_bitfield_default },
	 { "AUX_SW_RX_PARTIAL_BYTE", 10, 10, &umr_bitfield_default },
	 { "AUX_SW_NON_AUX_MODE", 11, 11, &umr_bitfield_default },
	 { "AUX_SW_RX_MIN_COUNT_VIOL", 12, 12, &umr_bitfield_default },
	 { "AUX_SW_RX_INVALID_STOP", 14, 14, &umr_bitfield_default },
	 { "AUX_SW_RX_SYNC_INVALID_L", 17, 17, &umr_bitfield_default },
	 { "AUX_SW_RX_SYNC_INVALID_H", 18, 18, &umr_bitfield_default },
	 { "AUX_SW_RX_INVALID_START", 19, 19, &umr_bitfield_default },
	 { "AUX_SW_RX_RECV_NO_DET", 20, 20, &umr_bitfield_default },
	 { "AUX_SW_RX_RECV_INVALID_H", 22, 22, &umr_bitfield_default },
	 { "AUX_SW_RX_RECV_INVALID_L", 23, 23, &umr_bitfield_default },
	 { "AUX_SW_REPLY_BYTE_COUNT", 24, 28, &umr_bitfield_default },
	 { "AUX_ARB_STATUS", 30, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDP_AUX1_AUX_LS_STATUS[] = {
	 { "AUX_LS_DONE", 0, 0, &umr_bitfield_default },
	 { "AUX_LS_REQ", 1, 1, &umr_bitfield_default },
	 { "AUX_LS_RX_TIMEOUT_STATE", 4, 6, &umr_bitfield_default },
	 { "AUX_LS_RX_TIMEOUT", 7, 7, &umr_bitfield_default },
	 { "AUX_LS_RX_OVERFLOW", 8, 8, &umr_bitfield_default },
	 { "AUX_LS_HPD_DISCON", 9, 9, &umr_bitfield_default },
	 { "AUX_LS_RX_PARTIAL_BYTE", 10, 10, &umr_bitfield_default },
	 { "AUX_LS_NON_AUX_MODE", 11, 11, &umr_bitfield_default },
	 { "AUX_LS_RX_MIN_COUNT_VIOL", 12, 12, &umr_bitfield_default },
	 { "AUX_LS_RX_INVALID_STOP", 14, 14, &umr_bitfield_default },
	 { "AUX_LS_RX_SYNC_INVALID_L", 17, 17, &umr_bitfield_default },
	 { "AUX_LS_RX_SYNC_INVALID_H", 18, 18, &umr_bitfield_default },
	 { "AUX_LS_RX_INVALID_START", 19, 19, &umr_bitfield_default },
	 { "AUX_LS_RX_RECV_NO_DET", 20, 20, &umr_bitfield_default },
	 { "AUX_LS_RX_RECV_INVALID_H", 22, 22, &umr_bitfield_default },
	 { "AUX_LS_RX_RECV_INVALID_L", 23, 23, &umr_bitfield_default },
	 { "AUX_LS_REPLY_BYTE_COUNT", 24, 28, &umr_bitfield_default },
	 { "AUX_LS_CP_IRQ", 29, 29, &umr_bitfield_default },
	 { "AUX_LS_UPDATED", 30, 30, &umr_bitfield_default },
	 { "AUX_LS_UPDATED_ACK", 31, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDP_AUX1_AUX_SW_DATA[] = {
	 { "AUX_SW_DATA_RW", 0, 0, &umr_bitfield_default },
	 { "AUX_SW_DATA", 8, 15, &umr_bitfield_default },
	 { "AUX_SW_INDEX", 16, 20, &umr_bitfield_default },
	 { "AUX_SW_AUTOINCREMENT_DISABLE", 31, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDP_AUX1_AUX_LS_DATA[] = {
	 { "AUX_LS_DATA", 8, 15, &umr_bitfield_default },
	 { "AUX_LS_INDEX", 16, 20, &umr_bitfield_default },
};
static struct umr_bitfield mmDP_AUX1_AUX_DPHY_TX_REF_CONTROL[] = {
	 { "AUX_TX_REF_SEL", 0, 0, &umr_bitfield_default },
	 { "AUX_TX_RATE", 4, 5, &umr_bitfield_default },
	 { "AUX_TX_REF_DIV", 16, 24, &umr_bitfield_default },
};
static struct umr_bitfield mmDP_AUX1_AUX_DPHY_TX_CONTROL[] = {
	 { "AUX_TX_PRECHARGE_LEN", 0, 2, &umr_bitfield_default },
	 { "AUX_TX_PRECHARGE_SYMBOLS", 8, 13, &umr_bitfield_default },
	 { "AUX_MODE_DET_CHECK_DELAY", 16, 18, &umr_bitfield_default },
};
static struct umr_bitfield mmDP_AUX1_AUX_DPHY_RX_CONTROL0[] = {
	 { "AUX_RX_START_WINDOW", 4, 6, &umr_bitfield_default },
	 { "AUX_RX_RECEIVE_WINDOW", 8, 10, &umr_bitfield_default },
	 { "AUX_RX_HALF_SYM_DETECT_LEN", 12, 13, &umr_bitfield_default },
	 { "AUX_RX_TRANSITION_FILTER_EN", 16, 16, &umr_bitfield_default },
	 { "AUX_RX_ALLOW_BELOW_THRESHOLD_PHASE_DETECT", 17, 17, &umr_bitfield_default },
	 { "AUX_RX_ALLOW_BELOW_THRESHOLD_START", 18, 18, &umr_bitfield_default },
	 { "AUX_RX_ALLOW_BELOW_THRESHOLD_STOP", 19, 19, &umr_bitfield_default },
	 { "AUX_RX_PHASE_DETECT_LEN", 20, 21, &umr_bitfield_default },
	 { "AUX_RX_TIMEOUT_LEN", 24, 26, &umr_bitfield_default },
	 { "AUX_RX_DETECTION_THRESHOLD", 28, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmDP_AUX1_AUX_DPHY_RX_CONTROL1[] = {
	 { "AUX_RX_PRECHARGE_SKIP", 0, 7, &umr_bitfield_default },
};
static struct umr_bitfield mmDP_AUX1_AUX_DPHY_TX_STATUS[] = {
	 { "AUX_TX_ACTIVE", 0, 0, &umr_bitfield_default },
	 { "AUX_TX_STATE", 4, 6, &umr_bitfield_default },
	 { "AUX_TX_HALF_SYM_PERIOD", 16, 24, &umr_bitfield_default },
};
static struct umr_bitfield mmDP_AUX1_AUX_DPHY_RX_STATUS[] = {
	 { "AUX_RX_STATE", 0, 2, &umr_bitfield_default },
	 { "AUX_RX_SYNC_VALID_COUNT", 8, 12, &umr_bitfield_default },
	 { "AUX_RX_HALF_SYM_PERIOD_FRACT", 16, 20, &umr_bitfield_default },
	 { "AUX_RX_HALF_SYM_PERIOD", 21, 29, &umr_bitfield_default },
};
static struct umr_bitfield mmDP_AUX1_AUX_GTC_SYNC_ERROR_CONTROL[] = {
	 { "AUX_GTC_POTENTIAL_ERROR_THRESHOLD", 0, 4, &umr_bitfield_default },
	 { "AUX_GTC_DEFINITE_ERROR_THRESHOLD", 8, 12, &umr_bitfield_default },
	 { "AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_LEN", 16, 17, &umr_bitfield_default },
	 { "AUX_GTC_SYNC_NUM_RETRY_FOR_LOCK_MAINT", 20, 21, &umr_bitfield_default },
};
static struct umr_bitfield mmDP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS[] = {
	 { "AUX_GTC_SYNC_LOCK_ACQ_COMPLETE", 0, 0, &umr_bitfield_default },
	 { "AUX_GTC_SYNC_LOCK_LOST", 4, 4, &umr_bitfield_default },
	 { "AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_OCCURRED", 8, 8, &umr_bitfield_default },
	 { "AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_STATE", 9, 12, &umr_bitfield_default },
	 { "AUX_GTC_SYNC_PHASE_ADJUST_TIME_VIOL", 16, 16, &umr_bitfield_default },
	 { "AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED", 20, 20, &umr_bitfield_default },
	 { "AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED_ACK", 21, 21, &umr_bitfield_default },
	 { "AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED", 22, 22, &umr_bitfield_default },
	 { "AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED_ACK", 23, 23, &umr_bitfield_default },
	 { "AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED", 24, 24, &umr_bitfield_default },
	 { "AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED_ACK", 25, 25, &umr_bitfield_default },
	 { "AUX_GTC_SYNC_CTRL_STATE", 28, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDP_AUX1_AUX_GTC_SYNC_STATUS[] = {
	 { "AUX_GTC_SYNC_DONE", 0, 0, &umr_bitfield_default },
	 { "AUX_GTC_SYNC_REQ", 1, 1, &umr_bitfield_default },
	 { "AUX_GTC_SYNC_RX_TIMEOUT_STATE", 4, 6, &umr_bitfield_default },
	 { "AUX_GTC_SYNC_TIMEOUT", 7, 7, &umr_bitfield_default },
	 { "AUX_GTC_SYNC_RX_OVERFLOW", 8, 8, &umr_bitfield_default },
	 { "AUX_GTC_SYNC_HPD_DISCON", 9, 9, &umr_bitfield_default },
	 { "AUX_GTC_SYNC_RX_PARTIAL_BYTE", 10, 10, &umr_bitfield_default },
	 { "AUX_GTC_SYNC_NON_AUX_MODE", 11, 11, &umr_bitfield_default },
	 { "AUX_GTC_SYNC_RX_MIN_COUNT_VIOL", 12, 12, &umr_bitfield_default },
	 { "AUX_GTC_SYNC_RX_INVALID_STOP", 14, 14, &umr_bitfield_default },
	 { "AUX_GTC_SYNC_RX_SYNC_INVALID_L", 17, 17, &umr_bitfield_default },
	 { "AUX_GTC_SYNC_RX_SYNC_INVALID_H", 18, 18, &umr_bitfield_default },
	 { "AUX_GTC_SYNC_RX_INVALID_START", 19, 19, &umr_bitfield_default },
	 { "AUX_GTC_SYNC_RX_RECV_NO_DET", 20, 20, &umr_bitfield_default },
	 { "AUX_GTC_SYNC_RX_RECV_INVALID_H", 22, 22, &umr_bitfield_default },
	 { "AUX_GTC_SYNC_RX_RECV_INVALID_L", 23, 23, &umr_bitfield_default },
	 { "AUX_GTC_SYNC_REPLY_BYTE_COUNT", 24, 28, &umr_bitfield_default },
	 { "AUX_GTC_SYNC_NACKED", 29, 29, &umr_bitfield_default },
	 { "AUX_GTC_MASTER_REQ_BY_RX", 30, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmDP_AUX2_AUX_CONTROL[] = {
	 { "AUX_EN", 0, 0, &umr_bitfield_default },
	 { "AUX_RESET", 4, 4, &umr_bitfield_default },
	 { "AUX_RESET_DONE", 5, 5, &umr_bitfield_default },
	 { "AUX_LS_READ_EN", 8, 8, &umr_bitfield_default },
	 { "AUX_LS_UPDATE_DISABLE", 12, 12, &umr_bitfield_default },
	 { "AUX_IGNORE_HPD_DISCON", 16, 16, &umr_bitfield_default },
	 { "AUX_MODE_DET_EN", 18, 18, &umr_bitfield_default },
	 { "AUX_HPD_SEL", 20, 22, &umr_bitfield_default },
	 { "AUX_IMPCAL_REQ_EN", 24, 24, &umr_bitfield_default },
	 { "AUX_TEST_MODE", 28, 28, &umr_bitfield_default },
	 { "AUX_DEGLITCH_EN", 29, 29, &umr_bitfield_default },
	 { "SPARE_0", 30, 30, &umr_bitfield_default },
	 { "SPARE_1", 31, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDP_AUX2_AUX_SW_CONTROL[] = {
	 { "AUX_SW_GO", 0, 0, &umr_bitfield_default },
	 { "AUX_LS_READ_TRIG", 2, 2, &umr_bitfield_default },
	 { "AUX_SW_START_DELAY", 4, 7, &umr_bitfield_default },
	 { "AUX_SW_WR_BYTES", 16, 20, &umr_bitfield_default },
};
static struct umr_bitfield mmDP_AUX2_AUX_ARB_CONTROL[] = {
	 { "AUX_ARB_PRIORITY", 0, 1, &umr_bitfield_default },
	 { "AUX_REG_RW_CNTL_STATUS", 2, 3, &umr_bitfield_default },
	 { "AUX_NO_QUEUED_SW_GO", 8, 8, &umr_bitfield_default },
	 { "AUX_NO_QUEUED_LS_GO", 10, 10, &umr_bitfield_default },
	 { "AUX_SW_USE_AUX_REG_REQ", 16, 16, &umr_bitfield_default },
	 { "AUX_SW_PENDING_USE_AUX_REG_REQ", 16, 16, &umr_bitfield_default },
	 { "AUX_SW_DONE_USING_AUX_REG", 17, 17, &umr_bitfield_default },
	 { "AUX_DMCU_USE_AUX_REG_REQ", 24, 24, &umr_bitfield_default },
	 { "AUX_DMCU_PENDING_USE_AUX_REG_REQ", 24, 24, &umr_bitfield_default },
	 { "AUX_DMCU_DONE_USING_AUX_REG", 25, 25, &umr_bitfield_default },
};
static struct umr_bitfield mmDP_AUX2_AUX_INTERRUPT_CONTROL[] = {
	 { "AUX_SW_DONE_INT", 0, 0, &umr_bitfield_default },
	 { "AUX_SW_DONE_ACK", 1, 1, &umr_bitfield_default },
	 { "AUX_SW_DONE_MASK", 2, 2, &umr_bitfield_default },
	 { "AUX_LS_DONE_INT", 4, 4, &umr_bitfield_default },
	 { "AUX_LS_DONE_ACK", 5, 5, &umr_bitfield_default },
	 { "AUX_LS_DONE_MASK", 6, 6, &umr_bitfield_default },
	 { "AUX_GTC_SYNC_LOCK_DONE_INT", 8, 8, &umr_bitfield_default },
	 { "AUX_GTC_SYNC_LOCK_DONE_ACK", 9, 9, &umr_bitfield_default },
	 { "AUX_GTC_SYNC_LOCK_DONE_INT_MASK", 10, 10, &umr_bitfield_default },
	 { "AUX_GTC_SYNC_ERROR_INT", 12, 12, &umr_bitfield_default },
	 { "AUX_GTC_SYNC_ERROR_ACK", 13, 13, &umr_bitfield_default },
	 { "AUX_GTC_SYNC_ERROR_INT_MASK", 14, 14, &umr_bitfield_default },
};
static struct umr_bitfield mmDP_AUX2_AUX_SW_STATUS[] = {
	 { "AUX_SW_DONE", 0, 0, &umr_bitfield_default },
	 { "AUX_SW_REQ", 1, 1, &umr_bitfield_default },
	 { "AUX_SW_RX_TIMEOUT_STATE", 4, 6, &umr_bitfield_default },
	 { "AUX_SW_RX_TIMEOUT", 7, 7, &umr_bitfield_default },
	 { "AUX_SW_RX_OVERFLOW", 8, 8, &umr_bitfield_default },
	 { "AUX_SW_HPD_DISCON", 9, 9, &umr_bitfield_default },
	 { "AUX_SW_RX_PARTIAL_BYTE", 10, 10, &umr_bitfield_default },
	 { "AUX_SW_NON_AUX_MODE", 11, 11, &umr_bitfield_default },
	 { "AUX_SW_RX_MIN_COUNT_VIOL", 12, 12, &umr_bitfield_default },
	 { "AUX_SW_RX_INVALID_STOP", 14, 14, &umr_bitfield_default },
	 { "AUX_SW_RX_SYNC_INVALID_L", 17, 17, &umr_bitfield_default },
	 { "AUX_SW_RX_SYNC_INVALID_H", 18, 18, &umr_bitfield_default },
	 { "AUX_SW_RX_INVALID_START", 19, 19, &umr_bitfield_default },
	 { "AUX_SW_RX_RECV_NO_DET", 20, 20, &umr_bitfield_default },
	 { "AUX_SW_RX_RECV_INVALID_H", 22, 22, &umr_bitfield_default },
	 { "AUX_SW_RX_RECV_INVALID_L", 23, 23, &umr_bitfield_default },
	 { "AUX_SW_REPLY_BYTE_COUNT", 24, 28, &umr_bitfield_default },
	 { "AUX_ARB_STATUS", 30, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDP_AUX2_AUX_LS_STATUS[] = {
	 { "AUX_LS_DONE", 0, 0, &umr_bitfield_default },
	 { "AUX_LS_REQ", 1, 1, &umr_bitfield_default },
	 { "AUX_LS_RX_TIMEOUT_STATE", 4, 6, &umr_bitfield_default },
	 { "AUX_LS_RX_TIMEOUT", 7, 7, &umr_bitfield_default },
	 { "AUX_LS_RX_OVERFLOW", 8, 8, &umr_bitfield_default },
	 { "AUX_LS_HPD_DISCON", 9, 9, &umr_bitfield_default },
	 { "AUX_LS_RX_PARTIAL_BYTE", 10, 10, &umr_bitfield_default },
	 { "AUX_LS_NON_AUX_MODE", 11, 11, &umr_bitfield_default },
	 { "AUX_LS_RX_MIN_COUNT_VIOL", 12, 12, &umr_bitfield_default },
	 { "AUX_LS_RX_INVALID_STOP", 14, 14, &umr_bitfield_default },
	 { "AUX_LS_RX_SYNC_INVALID_L", 17, 17, &umr_bitfield_default },
	 { "AUX_LS_RX_SYNC_INVALID_H", 18, 18, &umr_bitfield_default },
	 { "AUX_LS_RX_INVALID_START", 19, 19, &umr_bitfield_default },
	 { "AUX_LS_RX_RECV_NO_DET", 20, 20, &umr_bitfield_default },
	 { "AUX_LS_RX_RECV_INVALID_H", 22, 22, &umr_bitfield_default },
	 { "AUX_LS_RX_RECV_INVALID_L", 23, 23, &umr_bitfield_default },
	 { "AUX_LS_REPLY_BYTE_COUNT", 24, 28, &umr_bitfield_default },
	 { "AUX_LS_CP_IRQ", 29, 29, &umr_bitfield_default },
	 { "AUX_LS_UPDATED", 30, 30, &umr_bitfield_default },
	 { "AUX_LS_UPDATED_ACK", 31, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDP_AUX2_AUX_SW_DATA[] = {
	 { "AUX_SW_DATA_RW", 0, 0, &umr_bitfield_default },
	 { "AUX_SW_DATA", 8, 15, &umr_bitfield_default },
	 { "AUX_SW_INDEX", 16, 20, &umr_bitfield_default },
	 { "AUX_SW_AUTOINCREMENT_DISABLE", 31, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDP_AUX2_AUX_LS_DATA[] = {
	 { "AUX_LS_DATA", 8, 15, &umr_bitfield_default },
	 { "AUX_LS_INDEX", 16, 20, &umr_bitfield_default },
};
static struct umr_bitfield mmDP_AUX2_AUX_DPHY_TX_REF_CONTROL[] = {
	 { "AUX_TX_REF_SEL", 0, 0, &umr_bitfield_default },
	 { "AUX_TX_RATE", 4, 5, &umr_bitfield_default },
	 { "AUX_TX_REF_DIV", 16, 24, &umr_bitfield_default },
};
static struct umr_bitfield mmDP_AUX2_AUX_DPHY_TX_CONTROL[] = {
	 { "AUX_TX_PRECHARGE_LEN", 0, 2, &umr_bitfield_default },
	 { "AUX_TX_PRECHARGE_SYMBOLS", 8, 13, &umr_bitfield_default },
	 { "AUX_MODE_DET_CHECK_DELAY", 16, 18, &umr_bitfield_default },
};
static struct umr_bitfield mmDP_AUX2_AUX_DPHY_RX_CONTROL0[] = {
	 { "AUX_RX_START_WINDOW", 4, 6, &umr_bitfield_default },
	 { "AUX_RX_RECEIVE_WINDOW", 8, 10, &umr_bitfield_default },
	 { "AUX_RX_HALF_SYM_DETECT_LEN", 12, 13, &umr_bitfield_default },
	 { "AUX_RX_TRANSITION_FILTER_EN", 16, 16, &umr_bitfield_default },
	 { "AUX_RX_ALLOW_BELOW_THRESHOLD_PHASE_DETECT", 17, 17, &umr_bitfield_default },
	 { "AUX_RX_ALLOW_BELOW_THRESHOLD_START", 18, 18, &umr_bitfield_default },
	 { "AUX_RX_ALLOW_BELOW_THRESHOLD_STOP", 19, 19, &umr_bitfield_default },
	 { "AUX_RX_PHASE_DETECT_LEN", 20, 21, &umr_bitfield_default },
	 { "AUX_RX_TIMEOUT_LEN", 24, 26, &umr_bitfield_default },
	 { "AUX_RX_DETECTION_THRESHOLD", 28, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmDP_AUX2_AUX_DPHY_RX_CONTROL1[] = {
	 { "AUX_RX_PRECHARGE_SKIP", 0, 7, &umr_bitfield_default },
};
static struct umr_bitfield mmDP_AUX2_AUX_DPHY_TX_STATUS[] = {
	 { "AUX_TX_ACTIVE", 0, 0, &umr_bitfield_default },
	 { "AUX_TX_STATE", 4, 6, &umr_bitfield_default },
	 { "AUX_TX_HALF_SYM_PERIOD", 16, 24, &umr_bitfield_default },
};
static struct umr_bitfield mmDP_AUX2_AUX_DPHY_RX_STATUS[] = {
	 { "AUX_RX_STATE", 0, 2, &umr_bitfield_default },
	 { "AUX_RX_SYNC_VALID_COUNT", 8, 12, &umr_bitfield_default },
	 { "AUX_RX_HALF_SYM_PERIOD_FRACT", 16, 20, &umr_bitfield_default },
	 { "AUX_RX_HALF_SYM_PERIOD", 21, 29, &umr_bitfield_default },
};
static struct umr_bitfield mmDP_AUX2_AUX_GTC_SYNC_ERROR_CONTROL[] = {
	 { "AUX_GTC_POTENTIAL_ERROR_THRESHOLD", 0, 4, &umr_bitfield_default },
	 { "AUX_GTC_DEFINITE_ERROR_THRESHOLD", 8, 12, &umr_bitfield_default },
	 { "AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_LEN", 16, 17, &umr_bitfield_default },
	 { "AUX_GTC_SYNC_NUM_RETRY_FOR_LOCK_MAINT", 20, 21, &umr_bitfield_default },
};
static struct umr_bitfield mmDP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS[] = {
	 { "AUX_GTC_SYNC_LOCK_ACQ_COMPLETE", 0, 0, &umr_bitfield_default },
	 { "AUX_GTC_SYNC_LOCK_LOST", 4, 4, &umr_bitfield_default },
	 { "AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_OCCURRED", 8, 8, &umr_bitfield_default },
	 { "AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_STATE", 9, 12, &umr_bitfield_default },
	 { "AUX_GTC_SYNC_PHASE_ADJUST_TIME_VIOL", 16, 16, &umr_bitfield_default },
	 { "AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED", 20, 20, &umr_bitfield_default },
	 { "AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED_ACK", 21, 21, &umr_bitfield_default },
	 { "AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED", 22, 22, &umr_bitfield_default },
	 { "AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED_ACK", 23, 23, &umr_bitfield_default },
	 { "AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED", 24, 24, &umr_bitfield_default },
	 { "AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED_ACK", 25, 25, &umr_bitfield_default },
	 { "AUX_GTC_SYNC_CTRL_STATE", 28, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDP_AUX2_AUX_GTC_SYNC_STATUS[] = {
	 { "AUX_GTC_SYNC_DONE", 0, 0, &umr_bitfield_default },
	 { "AUX_GTC_SYNC_REQ", 1, 1, &umr_bitfield_default },
	 { "AUX_GTC_SYNC_RX_TIMEOUT_STATE", 4, 6, &umr_bitfield_default },
	 { "AUX_GTC_SYNC_TIMEOUT", 7, 7, &umr_bitfield_default },
	 { "AUX_GTC_SYNC_RX_OVERFLOW", 8, 8, &umr_bitfield_default },
	 { "AUX_GTC_SYNC_HPD_DISCON", 9, 9, &umr_bitfield_default },
	 { "AUX_GTC_SYNC_RX_PARTIAL_BYTE", 10, 10, &umr_bitfield_default },
	 { "AUX_GTC_SYNC_NON_AUX_MODE", 11, 11, &umr_bitfield_default },
	 { "AUX_GTC_SYNC_RX_MIN_COUNT_VIOL", 12, 12, &umr_bitfield_default },
	 { "AUX_GTC_SYNC_RX_INVALID_STOP", 14, 14, &umr_bitfield_default },
	 { "AUX_GTC_SYNC_RX_SYNC_INVALID_L", 17, 17, &umr_bitfield_default },
	 { "AUX_GTC_SYNC_RX_SYNC_INVALID_H", 18, 18, &umr_bitfield_default },
	 { "AUX_GTC_SYNC_RX_INVALID_START", 19, 19, &umr_bitfield_default },
	 { "AUX_GTC_SYNC_RX_RECV_NO_DET", 20, 20, &umr_bitfield_default },
	 { "AUX_GTC_SYNC_RX_RECV_INVALID_H", 22, 22, &umr_bitfield_default },
	 { "AUX_GTC_SYNC_RX_RECV_INVALID_L", 23, 23, &umr_bitfield_default },
	 { "AUX_GTC_SYNC_REPLY_BYTE_COUNT", 24, 28, &umr_bitfield_default },
	 { "AUX_GTC_SYNC_NACKED", 29, 29, &umr_bitfield_default },
	 { "AUX_GTC_MASTER_REQ_BY_RX", 30, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmDP_AUX3_AUX_CONTROL[] = {
	 { "AUX_EN", 0, 0, &umr_bitfield_default },
	 { "AUX_RESET", 4, 4, &umr_bitfield_default },
	 { "AUX_RESET_DONE", 5, 5, &umr_bitfield_default },
	 { "AUX_LS_READ_EN", 8, 8, &umr_bitfield_default },
	 { "AUX_LS_UPDATE_DISABLE", 12, 12, &umr_bitfield_default },
	 { "AUX_IGNORE_HPD_DISCON", 16, 16, &umr_bitfield_default },
	 { "AUX_MODE_DET_EN", 18, 18, &umr_bitfield_default },
	 { "AUX_HPD_SEL", 20, 22, &umr_bitfield_default },
	 { "AUX_IMPCAL_REQ_EN", 24, 24, &umr_bitfield_default },
	 { "AUX_TEST_MODE", 28, 28, &umr_bitfield_default },
	 { "AUX_DEGLITCH_EN", 29, 29, &umr_bitfield_default },
	 { "SPARE_0", 30, 30, &umr_bitfield_default },
	 { "SPARE_1", 31, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDP_AUX3_AUX_SW_CONTROL[] = {
	 { "AUX_SW_GO", 0, 0, &umr_bitfield_default },
	 { "AUX_LS_READ_TRIG", 2, 2, &umr_bitfield_default },
	 { "AUX_SW_START_DELAY", 4, 7, &umr_bitfield_default },
	 { "AUX_SW_WR_BYTES", 16, 20, &umr_bitfield_default },
};
static struct umr_bitfield mmDP_AUX3_AUX_ARB_CONTROL[] = {
	 { "AUX_ARB_PRIORITY", 0, 1, &umr_bitfield_default },
	 { "AUX_REG_RW_CNTL_STATUS", 2, 3, &umr_bitfield_default },
	 { "AUX_NO_QUEUED_SW_GO", 8, 8, &umr_bitfield_default },
	 { "AUX_NO_QUEUED_LS_GO", 10, 10, &umr_bitfield_default },
	 { "AUX_SW_USE_AUX_REG_REQ", 16, 16, &umr_bitfield_default },
	 { "AUX_SW_PENDING_USE_AUX_REG_REQ", 16, 16, &umr_bitfield_default },
	 { "AUX_SW_DONE_USING_AUX_REG", 17, 17, &umr_bitfield_default },
	 { "AUX_DMCU_USE_AUX_REG_REQ", 24, 24, &umr_bitfield_default },
	 { "AUX_DMCU_PENDING_USE_AUX_REG_REQ", 24, 24, &umr_bitfield_default },
	 { "AUX_DMCU_DONE_USING_AUX_REG", 25, 25, &umr_bitfield_default },
};
static struct umr_bitfield mmDP_AUX3_AUX_INTERRUPT_CONTROL[] = {
	 { "AUX_SW_DONE_INT", 0, 0, &umr_bitfield_default },
	 { "AUX_SW_DONE_ACK", 1, 1, &umr_bitfield_default },
	 { "AUX_SW_DONE_MASK", 2, 2, &umr_bitfield_default },
	 { "AUX_LS_DONE_INT", 4, 4, &umr_bitfield_default },
	 { "AUX_LS_DONE_ACK", 5, 5, &umr_bitfield_default },
	 { "AUX_LS_DONE_MASK", 6, 6, &umr_bitfield_default },
	 { "AUX_GTC_SYNC_LOCK_DONE_INT", 8, 8, &umr_bitfield_default },
	 { "AUX_GTC_SYNC_LOCK_DONE_ACK", 9, 9, &umr_bitfield_default },
	 { "AUX_GTC_SYNC_LOCK_DONE_INT_MASK", 10, 10, &umr_bitfield_default },
	 { "AUX_GTC_SYNC_ERROR_INT", 12, 12, &umr_bitfield_default },
	 { "AUX_GTC_SYNC_ERROR_ACK", 13, 13, &umr_bitfield_default },
	 { "AUX_GTC_SYNC_ERROR_INT_MASK", 14, 14, &umr_bitfield_default },
};
static struct umr_bitfield mmDP_AUX3_AUX_SW_STATUS[] = {
	 { "AUX_SW_DONE", 0, 0, &umr_bitfield_default },
	 { "AUX_SW_REQ", 1, 1, &umr_bitfield_default },
	 { "AUX_SW_RX_TIMEOUT_STATE", 4, 6, &umr_bitfield_default },
	 { "AUX_SW_RX_TIMEOUT", 7, 7, &umr_bitfield_default },
	 { "AUX_SW_RX_OVERFLOW", 8, 8, &umr_bitfield_default },
	 { "AUX_SW_HPD_DISCON", 9, 9, &umr_bitfield_default },
	 { "AUX_SW_RX_PARTIAL_BYTE", 10, 10, &umr_bitfield_default },
	 { "AUX_SW_NON_AUX_MODE", 11, 11, &umr_bitfield_default },
	 { "AUX_SW_RX_MIN_COUNT_VIOL", 12, 12, &umr_bitfield_default },
	 { "AUX_SW_RX_INVALID_STOP", 14, 14, &umr_bitfield_default },
	 { "AUX_SW_RX_SYNC_INVALID_L", 17, 17, &umr_bitfield_default },
	 { "AUX_SW_RX_SYNC_INVALID_H", 18, 18, &umr_bitfield_default },
	 { "AUX_SW_RX_INVALID_START", 19, 19, &umr_bitfield_default },
	 { "AUX_SW_RX_RECV_NO_DET", 20, 20, &umr_bitfield_default },
	 { "AUX_SW_RX_RECV_INVALID_H", 22, 22, &umr_bitfield_default },
	 { "AUX_SW_RX_RECV_INVALID_L", 23, 23, &umr_bitfield_default },
	 { "AUX_SW_REPLY_BYTE_COUNT", 24, 28, &umr_bitfield_default },
	 { "AUX_ARB_STATUS", 30, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDP_AUX3_AUX_LS_STATUS[] = {
	 { "AUX_LS_DONE", 0, 0, &umr_bitfield_default },
	 { "AUX_LS_REQ", 1, 1, &umr_bitfield_default },
	 { "AUX_LS_RX_TIMEOUT_STATE", 4, 6, &umr_bitfield_default },
	 { "AUX_LS_RX_TIMEOUT", 7, 7, &umr_bitfield_default },
	 { "AUX_LS_RX_OVERFLOW", 8, 8, &umr_bitfield_default },
	 { "AUX_LS_HPD_DISCON", 9, 9, &umr_bitfield_default },
	 { "AUX_LS_RX_PARTIAL_BYTE", 10, 10, &umr_bitfield_default },
	 { "AUX_LS_NON_AUX_MODE", 11, 11, &umr_bitfield_default },
	 { "AUX_LS_RX_MIN_COUNT_VIOL", 12, 12, &umr_bitfield_default },
	 { "AUX_LS_RX_INVALID_STOP", 14, 14, &umr_bitfield_default },
	 { "AUX_LS_RX_SYNC_INVALID_L", 17, 17, &umr_bitfield_default },
	 { "AUX_LS_RX_SYNC_INVALID_H", 18, 18, &umr_bitfield_default },
	 { "AUX_LS_RX_INVALID_START", 19, 19, &umr_bitfield_default },
	 { "AUX_LS_RX_RECV_NO_DET", 20, 20, &umr_bitfield_default },
	 { "AUX_LS_RX_RECV_INVALID_H", 22, 22, &umr_bitfield_default },
	 { "AUX_LS_RX_RECV_INVALID_L", 23, 23, &umr_bitfield_default },
	 { "AUX_LS_REPLY_BYTE_COUNT", 24, 28, &umr_bitfield_default },
	 { "AUX_LS_CP_IRQ", 29, 29, &umr_bitfield_default },
	 { "AUX_LS_UPDATED", 30, 30, &umr_bitfield_default },
	 { "AUX_LS_UPDATED_ACK", 31, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDP_AUX3_AUX_SW_DATA[] = {
	 { "AUX_SW_DATA_RW", 0, 0, &umr_bitfield_default },
	 { "AUX_SW_DATA", 8, 15, &umr_bitfield_default },
	 { "AUX_SW_INDEX", 16, 20, &umr_bitfield_default },
	 { "AUX_SW_AUTOINCREMENT_DISABLE", 31, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDP_AUX3_AUX_LS_DATA[] = {
	 { "AUX_LS_DATA", 8, 15, &umr_bitfield_default },
	 { "AUX_LS_INDEX", 16, 20, &umr_bitfield_default },
};
static struct umr_bitfield mmDP_AUX3_AUX_DPHY_TX_REF_CONTROL[] = {
	 { "AUX_TX_REF_SEL", 0, 0, &umr_bitfield_default },
	 { "AUX_TX_RATE", 4, 5, &umr_bitfield_default },
	 { "AUX_TX_REF_DIV", 16, 24, &umr_bitfield_default },
};
static struct umr_bitfield mmDP_AUX3_AUX_DPHY_TX_CONTROL[] = {
	 { "AUX_TX_PRECHARGE_LEN", 0, 2, &umr_bitfield_default },
	 { "AUX_TX_PRECHARGE_SYMBOLS", 8, 13, &umr_bitfield_default },
	 { "AUX_MODE_DET_CHECK_DELAY", 16, 18, &umr_bitfield_default },
};
static struct umr_bitfield mmDP_AUX3_AUX_DPHY_RX_CONTROL0[] = {
	 { "AUX_RX_START_WINDOW", 4, 6, &umr_bitfield_default },
	 { "AUX_RX_RECEIVE_WINDOW", 8, 10, &umr_bitfield_default },
	 { "AUX_RX_HALF_SYM_DETECT_LEN", 12, 13, &umr_bitfield_default },
	 { "AUX_RX_TRANSITION_FILTER_EN", 16, 16, &umr_bitfield_default },
	 { "AUX_RX_ALLOW_BELOW_THRESHOLD_PHASE_DETECT", 17, 17, &umr_bitfield_default },
	 { "AUX_RX_ALLOW_BELOW_THRESHOLD_START", 18, 18, &umr_bitfield_default },
	 { "AUX_RX_ALLOW_BELOW_THRESHOLD_STOP", 19, 19, &umr_bitfield_default },
	 { "AUX_RX_PHASE_DETECT_LEN", 20, 21, &umr_bitfield_default },
	 { "AUX_RX_TIMEOUT_LEN", 24, 26, &umr_bitfield_default },
	 { "AUX_RX_DETECTION_THRESHOLD", 28, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmDP_AUX3_AUX_DPHY_RX_CONTROL1[] = {
	 { "AUX_RX_PRECHARGE_SKIP", 0, 7, &umr_bitfield_default },
};
static struct umr_bitfield mmDP_AUX3_AUX_DPHY_TX_STATUS[] = {
	 { "AUX_TX_ACTIVE", 0, 0, &umr_bitfield_default },
	 { "AUX_TX_STATE", 4, 6, &umr_bitfield_default },
	 { "AUX_TX_HALF_SYM_PERIOD", 16, 24, &umr_bitfield_default },
};
static struct umr_bitfield mmDP_AUX3_AUX_DPHY_RX_STATUS[] = {
	 { "AUX_RX_STATE", 0, 2, &umr_bitfield_default },
	 { "AUX_RX_SYNC_VALID_COUNT", 8, 12, &umr_bitfield_default },
	 { "AUX_RX_HALF_SYM_PERIOD_FRACT", 16, 20, &umr_bitfield_default },
	 { "AUX_RX_HALF_SYM_PERIOD", 21, 29, &umr_bitfield_default },
};
static struct umr_bitfield mmDP_AUX3_AUX_GTC_SYNC_ERROR_CONTROL[] = {
	 { "AUX_GTC_POTENTIAL_ERROR_THRESHOLD", 0, 4, &umr_bitfield_default },
	 { "AUX_GTC_DEFINITE_ERROR_THRESHOLD", 8, 12, &umr_bitfield_default },
	 { "AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_LEN", 16, 17, &umr_bitfield_default },
	 { "AUX_GTC_SYNC_NUM_RETRY_FOR_LOCK_MAINT", 20, 21, &umr_bitfield_default },
};
static struct umr_bitfield mmDP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS[] = {
	 { "AUX_GTC_SYNC_LOCK_ACQ_COMPLETE", 0, 0, &umr_bitfield_default },
	 { "AUX_GTC_SYNC_LOCK_LOST", 4, 4, &umr_bitfield_default },
	 { "AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_OCCURRED", 8, 8, &umr_bitfield_default },
	 { "AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_STATE", 9, 12, &umr_bitfield_default },
	 { "AUX_GTC_SYNC_PHASE_ADJUST_TIME_VIOL", 16, 16, &umr_bitfield_default },
	 { "AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED", 20, 20, &umr_bitfield_default },
	 { "AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED_ACK", 21, 21, &umr_bitfield_default },
	 { "AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED", 22, 22, &umr_bitfield_default },
	 { "AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED_ACK", 23, 23, &umr_bitfield_default },
	 { "AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED", 24, 24, &umr_bitfield_default },
	 { "AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED_ACK", 25, 25, &umr_bitfield_default },
	 { "AUX_GTC_SYNC_CTRL_STATE", 28, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDP_AUX3_AUX_GTC_SYNC_STATUS[] = {
	 { "AUX_GTC_SYNC_DONE", 0, 0, &umr_bitfield_default },
	 { "AUX_GTC_SYNC_REQ", 1, 1, &umr_bitfield_default },
	 { "AUX_GTC_SYNC_RX_TIMEOUT_STATE", 4, 6, &umr_bitfield_default },
	 { "AUX_GTC_SYNC_TIMEOUT", 7, 7, &umr_bitfield_default },
	 { "AUX_GTC_SYNC_RX_OVERFLOW", 8, 8, &umr_bitfield_default },
	 { "AUX_GTC_SYNC_HPD_DISCON", 9, 9, &umr_bitfield_default },
	 { "AUX_GTC_SYNC_RX_PARTIAL_BYTE", 10, 10, &umr_bitfield_default },
	 { "AUX_GTC_SYNC_NON_AUX_MODE", 11, 11, &umr_bitfield_default },
	 { "AUX_GTC_SYNC_RX_MIN_COUNT_VIOL", 12, 12, &umr_bitfield_default },
	 { "AUX_GTC_SYNC_RX_INVALID_STOP", 14, 14, &umr_bitfield_default },
	 { "AUX_GTC_SYNC_RX_SYNC_INVALID_L", 17, 17, &umr_bitfield_default },
	 { "AUX_GTC_SYNC_RX_SYNC_INVALID_H", 18, 18, &umr_bitfield_default },
	 { "AUX_GTC_SYNC_RX_INVALID_START", 19, 19, &umr_bitfield_default },
	 { "AUX_GTC_SYNC_RX_RECV_NO_DET", 20, 20, &umr_bitfield_default },
	 { "AUX_GTC_SYNC_RX_RECV_INVALID_H", 22, 22, &umr_bitfield_default },
	 { "AUX_GTC_SYNC_RX_RECV_INVALID_L", 23, 23, &umr_bitfield_default },
	 { "AUX_GTC_SYNC_REPLY_BYTE_COUNT", 24, 28, &umr_bitfield_default },
	 { "AUX_GTC_SYNC_NACKED", 29, 29, &umr_bitfield_default },
	 { "AUX_GTC_MASTER_REQ_BY_RX", 30, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmDP_AUX4_AUX_CONTROL[] = {
	 { "AUX_EN", 0, 0, &umr_bitfield_default },
	 { "AUX_RESET", 4, 4, &umr_bitfield_default },
	 { "AUX_RESET_DONE", 5, 5, &umr_bitfield_default },
	 { "AUX_LS_READ_EN", 8, 8, &umr_bitfield_default },
	 { "AUX_LS_UPDATE_DISABLE", 12, 12, &umr_bitfield_default },
	 { "AUX_IGNORE_HPD_DISCON", 16, 16, &umr_bitfield_default },
	 { "AUX_MODE_DET_EN", 18, 18, &umr_bitfield_default },
	 { "AUX_HPD_SEL", 20, 22, &umr_bitfield_default },
	 { "AUX_IMPCAL_REQ_EN", 24, 24, &umr_bitfield_default },
	 { "AUX_TEST_MODE", 28, 28, &umr_bitfield_default },
	 { "AUX_DEGLITCH_EN", 29, 29, &umr_bitfield_default },
	 { "SPARE_0", 30, 30, &umr_bitfield_default },
	 { "SPARE_1", 31, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDP_AUX4_AUX_SW_CONTROL[] = {
	 { "AUX_SW_GO", 0, 0, &umr_bitfield_default },
	 { "AUX_LS_READ_TRIG", 2, 2, &umr_bitfield_default },
	 { "AUX_SW_START_DELAY", 4, 7, &umr_bitfield_default },
	 { "AUX_SW_WR_BYTES", 16, 20, &umr_bitfield_default },
};
static struct umr_bitfield mmDP_AUX4_AUX_ARB_CONTROL[] = {
	 { "AUX_ARB_PRIORITY", 0, 1, &umr_bitfield_default },
	 { "AUX_REG_RW_CNTL_STATUS", 2, 3, &umr_bitfield_default },
	 { "AUX_NO_QUEUED_SW_GO", 8, 8, &umr_bitfield_default },
	 { "AUX_NO_QUEUED_LS_GO", 10, 10, &umr_bitfield_default },
	 { "AUX_SW_USE_AUX_REG_REQ", 16, 16, &umr_bitfield_default },
	 { "AUX_SW_PENDING_USE_AUX_REG_REQ", 16, 16, &umr_bitfield_default },
	 { "AUX_SW_DONE_USING_AUX_REG", 17, 17, &umr_bitfield_default },
	 { "AUX_DMCU_USE_AUX_REG_REQ", 24, 24, &umr_bitfield_default },
	 { "AUX_DMCU_PENDING_USE_AUX_REG_REQ", 24, 24, &umr_bitfield_default },
	 { "AUX_DMCU_DONE_USING_AUX_REG", 25, 25, &umr_bitfield_default },
};
static struct umr_bitfield mmDP_AUX4_AUX_INTERRUPT_CONTROL[] = {
	 { "AUX_SW_DONE_INT", 0, 0, &umr_bitfield_default },
	 { "AUX_SW_DONE_ACK", 1, 1, &umr_bitfield_default },
	 { "AUX_SW_DONE_MASK", 2, 2, &umr_bitfield_default },
	 { "AUX_LS_DONE_INT", 4, 4, &umr_bitfield_default },
	 { "AUX_LS_DONE_ACK", 5, 5, &umr_bitfield_default },
	 { "AUX_LS_DONE_MASK", 6, 6, &umr_bitfield_default },
	 { "AUX_GTC_SYNC_LOCK_DONE_INT", 8, 8, &umr_bitfield_default },
	 { "AUX_GTC_SYNC_LOCK_DONE_ACK", 9, 9, &umr_bitfield_default },
	 { "AUX_GTC_SYNC_LOCK_DONE_INT_MASK", 10, 10, &umr_bitfield_default },
	 { "AUX_GTC_SYNC_ERROR_INT", 12, 12, &umr_bitfield_default },
	 { "AUX_GTC_SYNC_ERROR_ACK", 13, 13, &umr_bitfield_default },
	 { "AUX_GTC_SYNC_ERROR_INT_MASK", 14, 14, &umr_bitfield_default },
};
static struct umr_bitfield mmDP_AUX4_AUX_SW_STATUS[] = {
	 { "AUX_SW_DONE", 0, 0, &umr_bitfield_default },
	 { "AUX_SW_REQ", 1, 1, &umr_bitfield_default },
	 { "AUX_SW_RX_TIMEOUT_STATE", 4, 6, &umr_bitfield_default },
	 { "AUX_SW_RX_TIMEOUT", 7, 7, &umr_bitfield_default },
	 { "AUX_SW_RX_OVERFLOW", 8, 8, &umr_bitfield_default },
	 { "AUX_SW_HPD_DISCON", 9, 9, &umr_bitfield_default },
	 { "AUX_SW_RX_PARTIAL_BYTE", 10, 10, &umr_bitfield_default },
	 { "AUX_SW_NON_AUX_MODE", 11, 11, &umr_bitfield_default },
	 { "AUX_SW_RX_MIN_COUNT_VIOL", 12, 12, &umr_bitfield_default },
	 { "AUX_SW_RX_INVALID_STOP", 14, 14, &umr_bitfield_default },
	 { "AUX_SW_RX_SYNC_INVALID_L", 17, 17, &umr_bitfield_default },
	 { "AUX_SW_RX_SYNC_INVALID_H", 18, 18, &umr_bitfield_default },
	 { "AUX_SW_RX_INVALID_START", 19, 19, &umr_bitfield_default },
	 { "AUX_SW_RX_RECV_NO_DET", 20, 20, &umr_bitfield_default },
	 { "AUX_SW_RX_RECV_INVALID_H", 22, 22, &umr_bitfield_default },
	 { "AUX_SW_RX_RECV_INVALID_L", 23, 23, &umr_bitfield_default },
	 { "AUX_SW_REPLY_BYTE_COUNT", 24, 28, &umr_bitfield_default },
	 { "AUX_ARB_STATUS", 30, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDP_AUX4_AUX_LS_STATUS[] = {
	 { "AUX_LS_DONE", 0, 0, &umr_bitfield_default },
	 { "AUX_LS_REQ", 1, 1, &umr_bitfield_default },
	 { "AUX_LS_RX_TIMEOUT_STATE", 4, 6, &umr_bitfield_default },
	 { "AUX_LS_RX_TIMEOUT", 7, 7, &umr_bitfield_default },
	 { "AUX_LS_RX_OVERFLOW", 8, 8, &umr_bitfield_default },
	 { "AUX_LS_HPD_DISCON", 9, 9, &umr_bitfield_default },
	 { "AUX_LS_RX_PARTIAL_BYTE", 10, 10, &umr_bitfield_default },
	 { "AUX_LS_NON_AUX_MODE", 11, 11, &umr_bitfield_default },
	 { "AUX_LS_RX_MIN_COUNT_VIOL", 12, 12, &umr_bitfield_default },
	 { "AUX_LS_RX_INVALID_STOP", 14, 14, &umr_bitfield_default },
	 { "AUX_LS_RX_SYNC_INVALID_L", 17, 17, &umr_bitfield_default },
	 { "AUX_LS_RX_SYNC_INVALID_H", 18, 18, &umr_bitfield_default },
	 { "AUX_LS_RX_INVALID_START", 19, 19, &umr_bitfield_default },
	 { "AUX_LS_RX_RECV_NO_DET", 20, 20, &umr_bitfield_default },
	 { "AUX_LS_RX_RECV_INVALID_H", 22, 22, &umr_bitfield_default },
	 { "AUX_LS_RX_RECV_INVALID_L", 23, 23, &umr_bitfield_default },
	 { "AUX_LS_REPLY_BYTE_COUNT", 24, 28, &umr_bitfield_default },
	 { "AUX_LS_CP_IRQ", 29, 29, &umr_bitfield_default },
	 { "AUX_LS_UPDATED", 30, 30, &umr_bitfield_default },
	 { "AUX_LS_UPDATED_ACK", 31, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDP_AUX4_AUX_SW_DATA[] = {
	 { "AUX_SW_DATA_RW", 0, 0, &umr_bitfield_default },
	 { "AUX_SW_DATA", 8, 15, &umr_bitfield_default },
	 { "AUX_SW_INDEX", 16, 20, &umr_bitfield_default },
	 { "AUX_SW_AUTOINCREMENT_DISABLE", 31, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDP_AUX4_AUX_LS_DATA[] = {
	 { "AUX_LS_DATA", 8, 15, &umr_bitfield_default },
	 { "AUX_LS_INDEX", 16, 20, &umr_bitfield_default },
};
static struct umr_bitfield mmDP_AUX4_AUX_DPHY_TX_REF_CONTROL[] = {
	 { "AUX_TX_REF_SEL", 0, 0, &umr_bitfield_default },
	 { "AUX_TX_RATE", 4, 5, &umr_bitfield_default },
	 { "AUX_TX_REF_DIV", 16, 24, &umr_bitfield_default },
};
static struct umr_bitfield mmDP_AUX4_AUX_DPHY_TX_CONTROL[] = {
	 { "AUX_TX_PRECHARGE_LEN", 0, 2, &umr_bitfield_default },
	 { "AUX_TX_PRECHARGE_SYMBOLS", 8, 13, &umr_bitfield_default },
	 { "AUX_MODE_DET_CHECK_DELAY", 16, 18, &umr_bitfield_default },
};
static struct umr_bitfield mmDP_AUX4_AUX_DPHY_RX_CONTROL0[] = {
	 { "AUX_RX_START_WINDOW", 4, 6, &umr_bitfield_default },
	 { "AUX_RX_RECEIVE_WINDOW", 8, 10, &umr_bitfield_default },
	 { "AUX_RX_HALF_SYM_DETECT_LEN", 12, 13, &umr_bitfield_default },
	 { "AUX_RX_TRANSITION_FILTER_EN", 16, 16, &umr_bitfield_default },
	 { "AUX_RX_ALLOW_BELOW_THRESHOLD_PHASE_DETECT", 17, 17, &umr_bitfield_default },
	 { "AUX_RX_ALLOW_BELOW_THRESHOLD_START", 18, 18, &umr_bitfield_default },
	 { "AUX_RX_ALLOW_BELOW_THRESHOLD_STOP", 19, 19, &umr_bitfield_default },
	 { "AUX_RX_PHASE_DETECT_LEN", 20, 21, &umr_bitfield_default },
	 { "AUX_RX_TIMEOUT_LEN", 24, 26, &umr_bitfield_default },
	 { "AUX_RX_DETECTION_THRESHOLD", 28, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmDP_AUX4_AUX_DPHY_RX_CONTROL1[] = {
	 { "AUX_RX_PRECHARGE_SKIP", 0, 7, &umr_bitfield_default },
};
static struct umr_bitfield mmDP_AUX4_AUX_DPHY_TX_STATUS[] = {
	 { "AUX_TX_ACTIVE", 0, 0, &umr_bitfield_default },
	 { "AUX_TX_STATE", 4, 6, &umr_bitfield_default },
	 { "AUX_TX_HALF_SYM_PERIOD", 16, 24, &umr_bitfield_default },
};
static struct umr_bitfield mmDP_AUX4_AUX_DPHY_RX_STATUS[] = {
	 { "AUX_RX_STATE", 0, 2, &umr_bitfield_default },
	 { "AUX_RX_SYNC_VALID_COUNT", 8, 12, &umr_bitfield_default },
	 { "AUX_RX_HALF_SYM_PERIOD_FRACT", 16, 20, &umr_bitfield_default },
	 { "AUX_RX_HALF_SYM_PERIOD", 21, 29, &umr_bitfield_default },
};
static struct umr_bitfield mmDP_AUX4_AUX_GTC_SYNC_ERROR_CONTROL[] = {
	 { "AUX_GTC_POTENTIAL_ERROR_THRESHOLD", 0, 4, &umr_bitfield_default },
	 { "AUX_GTC_DEFINITE_ERROR_THRESHOLD", 8, 12, &umr_bitfield_default },
	 { "AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_LEN", 16, 17, &umr_bitfield_default },
	 { "AUX_GTC_SYNC_NUM_RETRY_FOR_LOCK_MAINT", 20, 21, &umr_bitfield_default },
};
static struct umr_bitfield mmDP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS[] = {
	 { "AUX_GTC_SYNC_LOCK_ACQ_COMPLETE", 0, 0, &umr_bitfield_default },
	 { "AUX_GTC_SYNC_LOCK_LOST", 4, 4, &umr_bitfield_default },
	 { "AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_OCCURRED", 8, 8, &umr_bitfield_default },
	 { "AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_STATE", 9, 12, &umr_bitfield_default },
	 { "AUX_GTC_SYNC_PHASE_ADJUST_TIME_VIOL", 16, 16, &umr_bitfield_default },
	 { "AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED", 20, 20, &umr_bitfield_default },
	 { "AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED_ACK", 21, 21, &umr_bitfield_default },
	 { "AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED", 22, 22, &umr_bitfield_default },
	 { "AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED_ACK", 23, 23, &umr_bitfield_default },
	 { "AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED", 24, 24, &umr_bitfield_default },
	 { "AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED_ACK", 25, 25, &umr_bitfield_default },
	 { "AUX_GTC_SYNC_CTRL_STATE", 28, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDP_AUX4_AUX_GTC_SYNC_STATUS[] = {
	 { "AUX_GTC_SYNC_DONE", 0, 0, &umr_bitfield_default },
	 { "AUX_GTC_SYNC_REQ", 1, 1, &umr_bitfield_default },
	 { "AUX_GTC_SYNC_RX_TIMEOUT_STATE", 4, 6, &umr_bitfield_default },
	 { "AUX_GTC_SYNC_TIMEOUT", 7, 7, &umr_bitfield_default },
	 { "AUX_GTC_SYNC_RX_OVERFLOW", 8, 8, &umr_bitfield_default },
	 { "AUX_GTC_SYNC_HPD_DISCON", 9, 9, &umr_bitfield_default },
	 { "AUX_GTC_SYNC_RX_PARTIAL_BYTE", 10, 10, &umr_bitfield_default },
	 { "AUX_GTC_SYNC_NON_AUX_MODE", 11, 11, &umr_bitfield_default },
	 { "AUX_GTC_SYNC_RX_MIN_COUNT_VIOL", 12, 12, &umr_bitfield_default },
	 { "AUX_GTC_SYNC_RX_INVALID_STOP", 14, 14, &umr_bitfield_default },
	 { "AUX_GTC_SYNC_RX_SYNC_INVALID_L", 17, 17, &umr_bitfield_default },
	 { "AUX_GTC_SYNC_RX_SYNC_INVALID_H", 18, 18, &umr_bitfield_default },
	 { "AUX_GTC_SYNC_RX_INVALID_START", 19, 19, &umr_bitfield_default },
	 { "AUX_GTC_SYNC_RX_RECV_NO_DET", 20, 20, &umr_bitfield_default },
	 { "AUX_GTC_SYNC_RX_RECV_INVALID_H", 22, 22, &umr_bitfield_default },
	 { "AUX_GTC_SYNC_RX_RECV_INVALID_L", 23, 23, &umr_bitfield_default },
	 { "AUX_GTC_SYNC_REPLY_BYTE_COUNT", 24, 28, &umr_bitfield_default },
	 { "AUX_GTC_SYNC_NACKED", 29, 29, &umr_bitfield_default },
	 { "AUX_GTC_MASTER_REQ_BY_RX", 30, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmDP_AUX5_AUX_CONTROL[] = {
	 { "AUX_EN", 0, 0, &umr_bitfield_default },
	 { "AUX_RESET", 4, 4, &umr_bitfield_default },
	 { "AUX_RESET_DONE", 5, 5, &umr_bitfield_default },
	 { "AUX_LS_READ_EN", 8, 8, &umr_bitfield_default },
	 { "AUX_LS_UPDATE_DISABLE", 12, 12, &umr_bitfield_default },
	 { "AUX_IGNORE_HPD_DISCON", 16, 16, &umr_bitfield_default },
	 { "AUX_MODE_DET_EN", 18, 18, &umr_bitfield_default },
	 { "AUX_HPD_SEL", 20, 22, &umr_bitfield_default },
	 { "AUX_IMPCAL_REQ_EN", 24, 24, &umr_bitfield_default },
	 { "AUX_TEST_MODE", 28, 28, &umr_bitfield_default },
	 { "AUX_DEGLITCH_EN", 29, 29, &umr_bitfield_default },
	 { "SPARE_0", 30, 30, &umr_bitfield_default },
	 { "SPARE_1", 31, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDP_AUX5_AUX_SW_CONTROL[] = {
	 { "AUX_SW_GO", 0, 0, &umr_bitfield_default },
	 { "AUX_LS_READ_TRIG", 2, 2, &umr_bitfield_default },
	 { "AUX_SW_START_DELAY", 4, 7, &umr_bitfield_default },
	 { "AUX_SW_WR_BYTES", 16, 20, &umr_bitfield_default },
};
static struct umr_bitfield mmDP_AUX5_AUX_ARB_CONTROL[] = {
	 { "AUX_ARB_PRIORITY", 0, 1, &umr_bitfield_default },
	 { "AUX_REG_RW_CNTL_STATUS", 2, 3, &umr_bitfield_default },
	 { "AUX_NO_QUEUED_SW_GO", 8, 8, &umr_bitfield_default },
	 { "AUX_NO_QUEUED_LS_GO", 10, 10, &umr_bitfield_default },
	 { "AUX_SW_USE_AUX_REG_REQ", 16, 16, &umr_bitfield_default },
	 { "AUX_SW_PENDING_USE_AUX_REG_REQ", 16, 16, &umr_bitfield_default },
	 { "AUX_SW_DONE_USING_AUX_REG", 17, 17, &umr_bitfield_default },
	 { "AUX_DMCU_USE_AUX_REG_REQ", 24, 24, &umr_bitfield_default },
	 { "AUX_DMCU_PENDING_USE_AUX_REG_REQ", 24, 24, &umr_bitfield_default },
	 { "AUX_DMCU_DONE_USING_AUX_REG", 25, 25, &umr_bitfield_default },
};
static struct umr_bitfield mmDP_AUX5_AUX_INTERRUPT_CONTROL[] = {
	 { "AUX_SW_DONE_INT", 0, 0, &umr_bitfield_default },
	 { "AUX_SW_DONE_ACK", 1, 1, &umr_bitfield_default },
	 { "AUX_SW_DONE_MASK", 2, 2, &umr_bitfield_default },
	 { "AUX_LS_DONE_INT", 4, 4, &umr_bitfield_default },
	 { "AUX_LS_DONE_ACK", 5, 5, &umr_bitfield_default },
	 { "AUX_LS_DONE_MASK", 6, 6, &umr_bitfield_default },
	 { "AUX_GTC_SYNC_LOCK_DONE_INT", 8, 8, &umr_bitfield_default },
	 { "AUX_GTC_SYNC_LOCK_DONE_ACK", 9, 9, &umr_bitfield_default },
	 { "AUX_GTC_SYNC_LOCK_DONE_INT_MASK", 10, 10, &umr_bitfield_default },
	 { "AUX_GTC_SYNC_ERROR_INT", 12, 12, &umr_bitfield_default },
	 { "AUX_GTC_SYNC_ERROR_ACK", 13, 13, &umr_bitfield_default },
	 { "AUX_GTC_SYNC_ERROR_INT_MASK", 14, 14, &umr_bitfield_default },
};
static struct umr_bitfield mmDP_AUX5_AUX_SW_STATUS[] = {
	 { "AUX_SW_DONE", 0, 0, &umr_bitfield_default },
	 { "AUX_SW_REQ", 1, 1, &umr_bitfield_default },
	 { "AUX_SW_RX_TIMEOUT_STATE", 4, 6, &umr_bitfield_default },
	 { "AUX_SW_RX_TIMEOUT", 7, 7, &umr_bitfield_default },
	 { "AUX_SW_RX_OVERFLOW", 8, 8, &umr_bitfield_default },
	 { "AUX_SW_HPD_DISCON", 9, 9, &umr_bitfield_default },
	 { "AUX_SW_RX_PARTIAL_BYTE", 10, 10, &umr_bitfield_default },
	 { "AUX_SW_NON_AUX_MODE", 11, 11, &umr_bitfield_default },
	 { "AUX_SW_RX_MIN_COUNT_VIOL", 12, 12, &umr_bitfield_default },
	 { "AUX_SW_RX_INVALID_STOP", 14, 14, &umr_bitfield_default },
	 { "AUX_SW_RX_SYNC_INVALID_L", 17, 17, &umr_bitfield_default },
	 { "AUX_SW_RX_SYNC_INVALID_H", 18, 18, &umr_bitfield_default },
	 { "AUX_SW_RX_INVALID_START", 19, 19, &umr_bitfield_default },
	 { "AUX_SW_RX_RECV_NO_DET", 20, 20, &umr_bitfield_default },
	 { "AUX_SW_RX_RECV_INVALID_H", 22, 22, &umr_bitfield_default },
	 { "AUX_SW_RX_RECV_INVALID_L", 23, 23, &umr_bitfield_default },
	 { "AUX_SW_REPLY_BYTE_COUNT", 24, 28, &umr_bitfield_default },
	 { "AUX_ARB_STATUS", 30, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDP_AUX5_AUX_LS_STATUS[] = {
	 { "AUX_LS_DONE", 0, 0, &umr_bitfield_default },
	 { "AUX_LS_REQ", 1, 1, &umr_bitfield_default },
	 { "AUX_LS_RX_TIMEOUT_STATE", 4, 6, &umr_bitfield_default },
	 { "AUX_LS_RX_TIMEOUT", 7, 7, &umr_bitfield_default },
	 { "AUX_LS_RX_OVERFLOW", 8, 8, &umr_bitfield_default },
	 { "AUX_LS_HPD_DISCON", 9, 9, &umr_bitfield_default },
	 { "AUX_LS_RX_PARTIAL_BYTE", 10, 10, &umr_bitfield_default },
	 { "AUX_LS_NON_AUX_MODE", 11, 11, &umr_bitfield_default },
	 { "AUX_LS_RX_MIN_COUNT_VIOL", 12, 12, &umr_bitfield_default },
	 { "AUX_LS_RX_INVALID_STOP", 14, 14, &umr_bitfield_default },
	 { "AUX_LS_RX_SYNC_INVALID_L", 17, 17, &umr_bitfield_default },
	 { "AUX_LS_RX_SYNC_INVALID_H", 18, 18, &umr_bitfield_default },
	 { "AUX_LS_RX_INVALID_START", 19, 19, &umr_bitfield_default },
	 { "AUX_LS_RX_RECV_NO_DET", 20, 20, &umr_bitfield_default },
	 { "AUX_LS_RX_RECV_INVALID_H", 22, 22, &umr_bitfield_default },
	 { "AUX_LS_RX_RECV_INVALID_L", 23, 23, &umr_bitfield_default },
	 { "AUX_LS_REPLY_BYTE_COUNT", 24, 28, &umr_bitfield_default },
	 { "AUX_LS_CP_IRQ", 29, 29, &umr_bitfield_default },
	 { "AUX_LS_UPDATED", 30, 30, &umr_bitfield_default },
	 { "AUX_LS_UPDATED_ACK", 31, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDP_AUX5_AUX_SW_DATA[] = {
	 { "AUX_SW_DATA_RW", 0, 0, &umr_bitfield_default },
	 { "AUX_SW_DATA", 8, 15, &umr_bitfield_default },
	 { "AUX_SW_INDEX", 16, 20, &umr_bitfield_default },
	 { "AUX_SW_AUTOINCREMENT_DISABLE", 31, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDP_AUX5_AUX_LS_DATA[] = {
	 { "AUX_LS_DATA", 8, 15, &umr_bitfield_default },
	 { "AUX_LS_INDEX", 16, 20, &umr_bitfield_default },
};
static struct umr_bitfield mmDP_AUX5_AUX_DPHY_TX_REF_CONTROL[] = {
	 { "AUX_TX_REF_SEL", 0, 0, &umr_bitfield_default },
	 { "AUX_TX_RATE", 4, 5, &umr_bitfield_default },
	 { "AUX_TX_REF_DIV", 16, 24, &umr_bitfield_default },
};
static struct umr_bitfield mmDP_AUX5_AUX_DPHY_TX_CONTROL[] = {
	 { "AUX_TX_PRECHARGE_LEN", 0, 2, &umr_bitfield_default },
	 { "AUX_TX_PRECHARGE_SYMBOLS", 8, 13, &umr_bitfield_default },
	 { "AUX_MODE_DET_CHECK_DELAY", 16, 18, &umr_bitfield_default },
};
static struct umr_bitfield mmDP_AUX5_AUX_DPHY_RX_CONTROL0[] = {
	 { "AUX_RX_START_WINDOW", 4, 6, &umr_bitfield_default },
	 { "AUX_RX_RECEIVE_WINDOW", 8, 10, &umr_bitfield_default },
	 { "AUX_RX_HALF_SYM_DETECT_LEN", 12, 13, &umr_bitfield_default },
	 { "AUX_RX_TRANSITION_FILTER_EN", 16, 16, &umr_bitfield_default },
	 { "AUX_RX_ALLOW_BELOW_THRESHOLD_PHASE_DETECT", 17, 17, &umr_bitfield_default },
	 { "AUX_RX_ALLOW_BELOW_THRESHOLD_START", 18, 18, &umr_bitfield_default },
	 { "AUX_RX_ALLOW_BELOW_THRESHOLD_STOP", 19, 19, &umr_bitfield_default },
	 { "AUX_RX_PHASE_DETECT_LEN", 20, 21, &umr_bitfield_default },
	 { "AUX_RX_TIMEOUT_LEN", 24, 26, &umr_bitfield_default },
	 { "AUX_RX_DETECTION_THRESHOLD", 28, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmDP_AUX5_AUX_DPHY_RX_CONTROL1[] = {
	 { "AUX_RX_PRECHARGE_SKIP", 0, 7, &umr_bitfield_default },
};
static struct umr_bitfield mmDP_AUX5_AUX_DPHY_TX_STATUS[] = {
	 { "AUX_TX_ACTIVE", 0, 0, &umr_bitfield_default },
	 { "AUX_TX_STATE", 4, 6, &umr_bitfield_default },
	 { "AUX_TX_HALF_SYM_PERIOD", 16, 24, &umr_bitfield_default },
};
static struct umr_bitfield mmDP_AUX5_AUX_DPHY_RX_STATUS[] = {
	 { "AUX_RX_STATE", 0, 2, &umr_bitfield_default },
	 { "AUX_RX_SYNC_VALID_COUNT", 8, 12, &umr_bitfield_default },
	 { "AUX_RX_HALF_SYM_PERIOD_FRACT", 16, 20, &umr_bitfield_default },
	 { "AUX_RX_HALF_SYM_PERIOD", 21, 29, &umr_bitfield_default },
};
static struct umr_bitfield mmDP_AUX5_AUX_GTC_SYNC_ERROR_CONTROL[] = {
	 { "AUX_GTC_POTENTIAL_ERROR_THRESHOLD", 0, 4, &umr_bitfield_default },
	 { "AUX_GTC_DEFINITE_ERROR_THRESHOLD", 8, 12, &umr_bitfield_default },
	 { "AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_LEN", 16, 17, &umr_bitfield_default },
	 { "AUX_GTC_SYNC_NUM_RETRY_FOR_LOCK_MAINT", 20, 21, &umr_bitfield_default },
};
static struct umr_bitfield mmDP_AUX5_AUX_GTC_SYNC_CONTROLLER_STATUS[] = {
	 { "AUX_GTC_SYNC_LOCK_ACQ_COMPLETE", 0, 0, &umr_bitfield_default },
	 { "AUX_GTC_SYNC_LOCK_LOST", 4, 4, &umr_bitfield_default },
	 { "AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_OCCURRED", 8, 8, &umr_bitfield_default },
	 { "AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_STATE", 9, 12, &umr_bitfield_default },
	 { "AUX_GTC_SYNC_PHASE_ADJUST_TIME_VIOL", 16, 16, &umr_bitfield_default },
	 { "AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED", 20, 20, &umr_bitfield_default },
	 { "AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED_ACK", 21, 21, &umr_bitfield_default },
	 { "AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED", 22, 22, &umr_bitfield_default },
	 { "AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED_ACK", 23, 23, &umr_bitfield_default },
	 { "AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED", 24, 24, &umr_bitfield_default },
	 { "AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED_ACK", 25, 25, &umr_bitfield_default },
	 { "AUX_GTC_SYNC_CTRL_STATE", 28, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDP_AUX5_AUX_GTC_SYNC_STATUS[] = {
	 { "AUX_GTC_SYNC_DONE", 0, 0, &umr_bitfield_default },
	 { "AUX_GTC_SYNC_REQ", 1, 1, &umr_bitfield_default },
	 { "AUX_GTC_SYNC_RX_TIMEOUT_STATE", 4, 6, &umr_bitfield_default },
	 { "AUX_GTC_SYNC_TIMEOUT", 7, 7, &umr_bitfield_default },
	 { "AUX_GTC_SYNC_RX_OVERFLOW", 8, 8, &umr_bitfield_default },
	 { "AUX_GTC_SYNC_HPD_DISCON", 9, 9, &umr_bitfield_default },
	 { "AUX_GTC_SYNC_RX_PARTIAL_BYTE", 10, 10, &umr_bitfield_default },
	 { "AUX_GTC_SYNC_NON_AUX_MODE", 11, 11, &umr_bitfield_default },
	 { "AUX_GTC_SYNC_RX_MIN_COUNT_VIOL", 12, 12, &umr_bitfield_default },
	 { "AUX_GTC_SYNC_RX_INVALID_STOP", 14, 14, &umr_bitfield_default },
	 { "AUX_GTC_SYNC_RX_SYNC_INVALID_L", 17, 17, &umr_bitfield_default },
	 { "AUX_GTC_SYNC_RX_SYNC_INVALID_H", 18, 18, &umr_bitfield_default },
	 { "AUX_GTC_SYNC_RX_INVALID_START", 19, 19, &umr_bitfield_default },
	 { "AUX_GTC_SYNC_RX_RECV_NO_DET", 20, 20, &umr_bitfield_default },
	 { "AUX_GTC_SYNC_RX_RECV_INVALID_H", 22, 22, &umr_bitfield_default },
	 { "AUX_GTC_SYNC_RX_RECV_INVALID_L", 23, 23, &umr_bitfield_default },
	 { "AUX_GTC_SYNC_REPLY_BYTE_COUNT", 24, 28, &umr_bitfield_default },
	 { "AUX_GTC_SYNC_NACKED", 29, 29, &umr_bitfield_default },
	 { "AUX_GTC_MASTER_REQ_BY_RX", 30, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmDP_AUX6_AUX_CONTROL[] = {
	 { "AUX_EN", 0, 0, &umr_bitfield_default },
	 { "AUX_RESET", 4, 4, &umr_bitfield_default },
	 { "AUX_RESET_DONE", 5, 5, &umr_bitfield_default },
	 { "AUX_LS_READ_EN", 8, 8, &umr_bitfield_default },
	 { "AUX_LS_UPDATE_DISABLE", 12, 12, &umr_bitfield_default },
	 { "AUX_IGNORE_HPD_DISCON", 16, 16, &umr_bitfield_default },
	 { "AUX_MODE_DET_EN", 18, 18, &umr_bitfield_default },
	 { "AUX_HPD_SEL", 20, 22, &umr_bitfield_default },
	 { "AUX_IMPCAL_REQ_EN", 24, 24, &umr_bitfield_default },
	 { "AUX_TEST_MODE", 28, 28, &umr_bitfield_default },
	 { "AUX_DEGLITCH_EN", 29, 29, &umr_bitfield_default },
	 { "SPARE_0", 30, 30, &umr_bitfield_default },
	 { "SPARE_1", 31, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDP_AUX6_AUX_SW_CONTROL[] = {
	 { "AUX_SW_GO", 0, 0, &umr_bitfield_default },
	 { "AUX_LS_READ_TRIG", 2, 2, &umr_bitfield_default },
	 { "AUX_SW_START_DELAY", 4, 7, &umr_bitfield_default },
	 { "AUX_SW_WR_BYTES", 16, 20, &umr_bitfield_default },
};
static struct umr_bitfield mmDP_AUX6_AUX_ARB_CONTROL[] = {
	 { "AUX_ARB_PRIORITY", 0, 1, &umr_bitfield_default },
	 { "AUX_REG_RW_CNTL_STATUS", 2, 3, &umr_bitfield_default },
	 { "AUX_NO_QUEUED_SW_GO", 8, 8, &umr_bitfield_default },
	 { "AUX_NO_QUEUED_LS_GO", 10, 10, &umr_bitfield_default },
	 { "AUX_SW_USE_AUX_REG_REQ", 16, 16, &umr_bitfield_default },
	 { "AUX_SW_PENDING_USE_AUX_REG_REQ", 16, 16, &umr_bitfield_default },
	 { "AUX_SW_DONE_USING_AUX_REG", 17, 17, &umr_bitfield_default },
	 { "AUX_DMCU_USE_AUX_REG_REQ", 24, 24, &umr_bitfield_default },
	 { "AUX_DMCU_PENDING_USE_AUX_REG_REQ", 24, 24, &umr_bitfield_default },
	 { "AUX_DMCU_DONE_USING_AUX_REG", 25, 25, &umr_bitfield_default },
};
static struct umr_bitfield mmDP_AUX6_AUX_INTERRUPT_CONTROL[] = {
	 { "AUX_SW_DONE_INT", 0, 0, &umr_bitfield_default },
	 { "AUX_SW_DONE_ACK", 1, 1, &umr_bitfield_default },
	 { "AUX_SW_DONE_MASK", 2, 2, &umr_bitfield_default },
	 { "AUX_LS_DONE_INT", 4, 4, &umr_bitfield_default },
	 { "AUX_LS_DONE_ACK", 5, 5, &umr_bitfield_default },
	 { "AUX_LS_DONE_MASK", 6, 6, &umr_bitfield_default },
	 { "AUX_GTC_SYNC_LOCK_DONE_INT", 8, 8, &umr_bitfield_default },
	 { "AUX_GTC_SYNC_LOCK_DONE_ACK", 9, 9, &umr_bitfield_default },
	 { "AUX_GTC_SYNC_LOCK_DONE_INT_MASK", 10, 10, &umr_bitfield_default },
	 { "AUX_GTC_SYNC_ERROR_INT", 12, 12, &umr_bitfield_default },
	 { "AUX_GTC_SYNC_ERROR_ACK", 13, 13, &umr_bitfield_default },
	 { "AUX_GTC_SYNC_ERROR_INT_MASK", 14, 14, &umr_bitfield_default },
};
static struct umr_bitfield mmDP_AUX6_AUX_SW_STATUS[] = {
	 { "AUX_SW_DONE", 0, 0, &umr_bitfield_default },
	 { "AUX_SW_REQ", 1, 1, &umr_bitfield_default },
	 { "AUX_SW_RX_TIMEOUT_STATE", 4, 6, &umr_bitfield_default },
	 { "AUX_SW_RX_TIMEOUT", 7, 7, &umr_bitfield_default },
	 { "AUX_SW_RX_OVERFLOW", 8, 8, &umr_bitfield_default },
	 { "AUX_SW_HPD_DISCON", 9, 9, &umr_bitfield_default },
	 { "AUX_SW_RX_PARTIAL_BYTE", 10, 10, &umr_bitfield_default },
	 { "AUX_SW_NON_AUX_MODE", 11, 11, &umr_bitfield_default },
	 { "AUX_SW_RX_MIN_COUNT_VIOL", 12, 12, &umr_bitfield_default },
	 { "AUX_SW_RX_INVALID_STOP", 14, 14, &umr_bitfield_default },
	 { "AUX_SW_RX_SYNC_INVALID_L", 17, 17, &umr_bitfield_default },
	 { "AUX_SW_RX_SYNC_INVALID_H", 18, 18, &umr_bitfield_default },
	 { "AUX_SW_RX_INVALID_START", 19, 19, &umr_bitfield_default },
	 { "AUX_SW_RX_RECV_NO_DET", 20, 20, &umr_bitfield_default },
	 { "AUX_SW_RX_RECV_INVALID_H", 22, 22, &umr_bitfield_default },
	 { "AUX_SW_RX_RECV_INVALID_L", 23, 23, &umr_bitfield_default },
	 { "AUX_SW_REPLY_BYTE_COUNT", 24, 28, &umr_bitfield_default },
	 { "AUX_ARB_STATUS", 30, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDP_AUX6_AUX_LS_STATUS[] = {
	 { "AUX_LS_DONE", 0, 0, &umr_bitfield_default },
	 { "AUX_LS_REQ", 1, 1, &umr_bitfield_default },
	 { "AUX_LS_RX_TIMEOUT_STATE", 4, 6, &umr_bitfield_default },
	 { "AUX_LS_RX_TIMEOUT", 7, 7, &umr_bitfield_default },
	 { "AUX_LS_RX_OVERFLOW", 8, 8, &umr_bitfield_default },
	 { "AUX_LS_HPD_DISCON", 9, 9, &umr_bitfield_default },
	 { "AUX_LS_RX_PARTIAL_BYTE", 10, 10, &umr_bitfield_default },
	 { "AUX_LS_NON_AUX_MODE", 11, 11, &umr_bitfield_default },
	 { "AUX_LS_RX_MIN_COUNT_VIOL", 12, 12, &umr_bitfield_default },
	 { "AUX_LS_RX_INVALID_STOP", 14, 14, &umr_bitfield_default },
	 { "AUX_LS_RX_SYNC_INVALID_L", 17, 17, &umr_bitfield_default },
	 { "AUX_LS_RX_SYNC_INVALID_H", 18, 18, &umr_bitfield_default },
	 { "AUX_LS_RX_INVALID_START", 19, 19, &umr_bitfield_default },
	 { "AUX_LS_RX_RECV_NO_DET", 20, 20, &umr_bitfield_default },
	 { "AUX_LS_RX_RECV_INVALID_H", 22, 22, &umr_bitfield_default },
	 { "AUX_LS_RX_RECV_INVALID_L", 23, 23, &umr_bitfield_default },
	 { "AUX_LS_REPLY_BYTE_COUNT", 24, 28, &umr_bitfield_default },
	 { "AUX_LS_CP_IRQ", 29, 29, &umr_bitfield_default },
	 { "AUX_LS_UPDATED", 30, 30, &umr_bitfield_default },
	 { "AUX_LS_UPDATED_ACK", 31, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDP_AUX6_AUX_SW_DATA[] = {
	 { "AUX_SW_DATA_RW", 0, 0, &umr_bitfield_default },
	 { "AUX_SW_DATA", 8, 15, &umr_bitfield_default },
	 { "AUX_SW_INDEX", 16, 20, &umr_bitfield_default },
	 { "AUX_SW_AUTOINCREMENT_DISABLE", 31, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDP_AUX6_AUX_LS_DATA[] = {
	 { "AUX_LS_DATA", 8, 15, &umr_bitfield_default },
	 { "AUX_LS_INDEX", 16, 20, &umr_bitfield_default },
};
static struct umr_bitfield mmDP_AUX6_AUX_DPHY_TX_REF_CONTROL[] = {
	 { "AUX_TX_REF_SEL", 0, 0, &umr_bitfield_default },
	 { "AUX_TX_RATE", 4, 5, &umr_bitfield_default },
	 { "AUX_TX_REF_DIV", 16, 24, &umr_bitfield_default },
};
static struct umr_bitfield mmDP_AUX6_AUX_DPHY_TX_CONTROL[] = {
	 { "AUX_TX_PRECHARGE_LEN", 0, 2, &umr_bitfield_default },
	 { "AUX_TX_PRECHARGE_SYMBOLS", 8, 13, &umr_bitfield_default },
	 { "AUX_MODE_DET_CHECK_DELAY", 16, 18, &umr_bitfield_default },
};
static struct umr_bitfield mmDP_AUX6_AUX_DPHY_RX_CONTROL0[] = {
	 { "AUX_RX_START_WINDOW", 4, 6, &umr_bitfield_default },
	 { "AUX_RX_RECEIVE_WINDOW", 8, 10, &umr_bitfield_default },
	 { "AUX_RX_HALF_SYM_DETECT_LEN", 12, 13, &umr_bitfield_default },
	 { "AUX_RX_TRANSITION_FILTER_EN", 16, 16, &umr_bitfield_default },
	 { "AUX_RX_ALLOW_BELOW_THRESHOLD_PHASE_DETECT", 17, 17, &umr_bitfield_default },
	 { "AUX_RX_ALLOW_BELOW_THRESHOLD_START", 18, 18, &umr_bitfield_default },
	 { "AUX_RX_ALLOW_BELOW_THRESHOLD_STOP", 19, 19, &umr_bitfield_default },
	 { "AUX_RX_PHASE_DETECT_LEN", 20, 21, &umr_bitfield_default },
	 { "AUX_RX_TIMEOUT_LEN", 24, 26, &umr_bitfield_default },
	 { "AUX_RX_DETECTION_THRESHOLD", 28, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmDP_AUX6_AUX_DPHY_RX_CONTROL1[] = {
	 { "AUX_RX_PRECHARGE_SKIP", 0, 7, &umr_bitfield_default },
};
static struct umr_bitfield mmDP_AUX6_AUX_DPHY_TX_STATUS[] = {
	 { "AUX_TX_ACTIVE", 0, 0, &umr_bitfield_default },
	 { "AUX_TX_STATE", 4, 6, &umr_bitfield_default },
	 { "AUX_TX_HALF_SYM_PERIOD", 16, 24, &umr_bitfield_default },
};
static struct umr_bitfield mmDP_AUX6_AUX_DPHY_RX_STATUS[] = {
	 { "AUX_RX_STATE", 0, 2, &umr_bitfield_default },
	 { "AUX_RX_SYNC_VALID_COUNT", 8, 12, &umr_bitfield_default },
	 { "AUX_RX_HALF_SYM_PERIOD_FRACT", 16, 20, &umr_bitfield_default },
	 { "AUX_RX_HALF_SYM_PERIOD", 21, 29, &umr_bitfield_default },
};
static struct umr_bitfield mmDP_AUX6_AUX_GTC_SYNC_ERROR_CONTROL[] = {
	 { "AUX_GTC_POTENTIAL_ERROR_THRESHOLD", 0, 4, &umr_bitfield_default },
	 { "AUX_GTC_DEFINITE_ERROR_THRESHOLD", 8, 12, &umr_bitfield_default },
	 { "AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_LEN", 16, 17, &umr_bitfield_default },
	 { "AUX_GTC_SYNC_NUM_RETRY_FOR_LOCK_MAINT", 20, 21, &umr_bitfield_default },
};
static struct umr_bitfield mmDP_AUX6_AUX_GTC_SYNC_CONTROLLER_STATUS[] = {
	 { "AUX_GTC_SYNC_LOCK_ACQ_COMPLETE", 0, 0, &umr_bitfield_default },
	 { "AUX_GTC_SYNC_LOCK_LOST", 4, 4, &umr_bitfield_default },
	 { "AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_OCCURRED", 8, 8, &umr_bitfield_default },
	 { "AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_STATE", 9, 12, &umr_bitfield_default },
	 { "AUX_GTC_SYNC_PHASE_ADJUST_TIME_VIOL", 16, 16, &umr_bitfield_default },
	 { "AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED", 20, 20, &umr_bitfield_default },
	 { "AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED_ACK", 21, 21, &umr_bitfield_default },
	 { "AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED", 22, 22, &umr_bitfield_default },
	 { "AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED_ACK", 23, 23, &umr_bitfield_default },
	 { "AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED", 24, 24, &umr_bitfield_default },
	 { "AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED_ACK", 25, 25, &umr_bitfield_default },
	 { "AUX_GTC_SYNC_CTRL_STATE", 28, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDP_AUX6_AUX_GTC_SYNC_STATUS[] = {
	 { "AUX_GTC_SYNC_DONE", 0, 0, &umr_bitfield_default },
	 { "AUX_GTC_SYNC_REQ", 1, 1, &umr_bitfield_default },
	 { "AUX_GTC_SYNC_RX_TIMEOUT_STATE", 4, 6, &umr_bitfield_default },
	 { "AUX_GTC_SYNC_TIMEOUT", 7, 7, &umr_bitfield_default },
	 { "AUX_GTC_SYNC_RX_OVERFLOW", 8, 8, &umr_bitfield_default },
	 { "AUX_GTC_SYNC_HPD_DISCON", 9, 9, &umr_bitfield_default },
	 { "AUX_GTC_SYNC_RX_PARTIAL_BYTE", 10, 10, &umr_bitfield_default },
	 { "AUX_GTC_SYNC_NON_AUX_MODE", 11, 11, &umr_bitfield_default },
	 { "AUX_GTC_SYNC_RX_MIN_COUNT_VIOL", 12, 12, &umr_bitfield_default },
	 { "AUX_GTC_SYNC_RX_INVALID_STOP", 14, 14, &umr_bitfield_default },
	 { "AUX_GTC_SYNC_RX_SYNC_INVALID_L", 17, 17, &umr_bitfield_default },
	 { "AUX_GTC_SYNC_RX_SYNC_INVALID_H", 18, 18, &umr_bitfield_default },
	 { "AUX_GTC_SYNC_RX_INVALID_START", 19, 19, &umr_bitfield_default },
	 { "AUX_GTC_SYNC_RX_RECV_NO_DET", 20, 20, &umr_bitfield_default },
	 { "AUX_GTC_SYNC_RX_RECV_INVALID_H", 22, 22, &umr_bitfield_default },
	 { "AUX_GTC_SYNC_RX_RECV_INVALID_L", 23, 23, &umr_bitfield_default },
	 { "AUX_GTC_SYNC_REPLY_BYTE_COUNT", 24, 28, &umr_bitfield_default },
	 { "AUX_GTC_SYNC_NACKED", 29, 29, &umr_bitfield_default },
	 { "AUX_GTC_MASTER_REQ_BY_RX", 30, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG0_DIG_FE_CNTL[] = {
	 { "DIG_SOURCE_SELECT", 0, 2, &umr_bitfield_default },
	 { "DIG_STEREOSYNC_SELECT", 4, 6, &umr_bitfield_default },
	 { "DIG_STEREOSYNC_GATE_EN", 8, 8, &umr_bitfield_default },
	 { "DIG_START", 10, 10, &umr_bitfield_default },
	 { "DIG_DIGITAL_BYPASS_SELECT", 12, 14, &umr_bitfield_default },
	 { "DIG_SYMCLK_FE_ON", 24, 24, &umr_bitfield_default },
	 { "TMDS_PIXEL_ENCODING", 28, 28, &umr_bitfield_default },
	 { "TMDS_COLOR_FORMAT", 30, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG0_DIG_OUTPUT_CRC_CNTL[] = {
	 { "DIG_OUTPUT_CRC_EN", 0, 0, &umr_bitfield_default },
	 { "DIG_OUTPUT_CRC_LINK_SEL", 4, 4, &umr_bitfield_default },
	 { "DIG_OUTPUT_CRC_DATA_SEL", 8, 9, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG0_DIG_OUTPUT_CRC_RESULT[] = {
	 { "DIG_OUTPUT_CRC_RESULT", 0, 29, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG0_DIG_CLOCK_PATTERN[] = {
	 { "DIG_CLOCK_PATTERN", 0, 9, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG0_DIG_TEST_PATTERN[] = {
	 { "DIG_TEST_PATTERN_OUT_EN", 0, 0, &umr_bitfield_default },
	 { "DIG_HALF_CLOCK_PATTERN_SEL", 1, 1, &umr_bitfield_default },
	 { "DIG_RANDOM_PATTERN_OUT_EN", 4, 4, &umr_bitfield_default },
	 { "DIG_RANDOM_PATTERN_RESET", 5, 5, &umr_bitfield_default },
	 { "DIG_TEST_PATTERN_EXTERNAL_RESET_EN", 6, 6, &umr_bitfield_default },
	 { "DIG_STATIC_TEST_PATTERN", 16, 25, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG0_DIG_RANDOM_PATTERN_SEED[] = {
	 { "DIG_RANDOM_PATTERN_SEED", 0, 23, &umr_bitfield_default },
	 { "DIG_RAN_PAT_DURING_DE_ONLY", 24, 24, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG0_DIG_FIFO_STATUS[] = {
	 { "DIG_FIFO_LEVEL_ERROR", 0, 0, &umr_bitfield_default },
	 { "DIG_FIFO_USE_OVERWRITE_LEVEL", 1, 1, &umr_bitfield_default },
	 { "DIG_FIFO_OVERWRITE_LEVEL", 2, 7, &umr_bitfield_default },
	 { "DIG_FIFO_ERROR_ACK", 8, 8, &umr_bitfield_default },
	 { "DIG_FIFO_CAL_AVERAGE_LEVEL", 10, 15, &umr_bitfield_default },
	 { "DIG_FIFO_MAXIMUM_LEVEL", 16, 20, &umr_bitfield_default },
	 { "DIG_FIFO_MINIMUM_LEVEL", 22, 25, &umr_bitfield_default },
	 { "DIG_FIFO_READ_CLOCK_SRC", 26, 26, &umr_bitfield_default },
	 { "DIG_FIFO_CALIBRATED", 29, 29, &umr_bitfield_default },
	 { "DIG_FIFO_FORCE_RECAL_AVERAGE", 30, 30, &umr_bitfield_default },
	 { "DIG_FIFO_FORCE_RECOMP_MINMAX", 31, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG0_HDMI_CONTROL[] = {
	 { "HDMI_KEEPOUT_MODE", 0, 0, &umr_bitfield_default },
	 { "HDMI_DATA_SCRAMBLE_EN", 1, 1, &umr_bitfield_default },
	 { "HDMI_CLOCK_CHANNEL_RATE", 2, 2, &umr_bitfield_default },
	 { "HDMI_NO_EXTRA_NULL_PACKET_FILLED", 3, 3, &umr_bitfield_default },
	 { "HDMI_PACKET_GEN_VERSION", 4, 4, &umr_bitfield_default },
	 { "HDMI_ERROR_ACK", 8, 8, &umr_bitfield_default },
	 { "HDMI_ERROR_MASK", 9, 9, &umr_bitfield_default },
	 { "HDMI_DEEP_COLOR_ENABLE", 24, 24, &umr_bitfield_default },
	 { "HDMI_DEEP_COLOR_DEPTH", 28, 29, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG0_HDMI_STATUS[] = {
	 { "HDMI_ACTIVE_AVMUTE", 0, 0, &umr_bitfield_default },
	 { "HDMI_AUDIO_PACKET_ERROR", 16, 16, &umr_bitfield_default },
	 { "HDMI_VBI_PACKET_ERROR", 20, 20, &umr_bitfield_default },
	 { "HDMI_ERROR_INT", 27, 27, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG0_HDMI_AUDIO_PACKET_CONTROL[] = {
	 { "HDMI_AUDIO_DELAY_EN", 4, 5, &umr_bitfield_default },
	 { "HDMI_AUDIO_PACKETS_PER_LINE", 16, 20, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG0_HDMI_ACR_PACKET_CONTROL[] = {
	 { "HDMI_ACR_SEND", 0, 0, &umr_bitfield_default },
	 { "HDMI_ACR_CONT", 1, 1, &umr_bitfield_default },
	 { "HDMI_ACR_SELECT", 4, 5, &umr_bitfield_default },
	 { "HDMI_ACR_SOURCE", 8, 8, &umr_bitfield_default },
	 { "HDMI_ACR_AUTO_SEND", 12, 12, &umr_bitfield_default },
	 { "HDMI_ACR_N_MULTIPLE", 16, 18, &umr_bitfield_default },
	 { "HDMI_ACR_AUDIO_PRIORITY", 31, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG0_HDMI_VBI_PACKET_CONTROL[] = {
	 { "HDMI_NULL_SEND", 0, 0, &umr_bitfield_default },
	 { "HDMI_GC_SEND", 4, 4, &umr_bitfield_default },
	 { "HDMI_GC_CONT", 5, 5, &umr_bitfield_default },
	 { "HDMI_ISRC_SEND", 8, 8, &umr_bitfield_default },
	 { "HDMI_ISRC_CONT", 9, 9, &umr_bitfield_default },
	 { "HDMI_ISRC_LINE", 16, 21, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG0_HDMI_INFOFRAME_CONTROL0[] = {
	 { "HDMI_AUDIO_INFO_SEND", 4, 4, &umr_bitfield_default },
	 { "HDMI_AUDIO_INFO_CONT", 5, 5, &umr_bitfield_default },
	 { "HDMI_MPEG_INFO_SEND", 8, 8, &umr_bitfield_default },
	 { "HDMI_MPEG_INFO_CONT", 9, 9, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG0_HDMI_INFOFRAME_CONTROL1[] = {
	 { "HDMI_AUDIO_INFO_LINE", 8, 13, &umr_bitfield_default },
	 { "HDMI_MPEG_INFO_LINE", 16, 21, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG0_HDMI_GENERIC_PACKET_CONTROL0[] = {
	 { "HDMI_GENERIC0_SEND", 0, 0, &umr_bitfield_default },
	 { "HDMI_GENERIC0_CONT", 1, 1, &umr_bitfield_default },
	 { "HDMI_GENERIC1_SEND", 4, 4, &umr_bitfield_default },
	 { "HDMI_GENERIC1_CONT", 5, 5, &umr_bitfield_default },
	 { "HDMI_GENERIC0_LINE", 16, 21, &umr_bitfield_default },
	 { "HDMI_GENERIC1_LINE", 24, 29, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG0_HDMI_GC[] = {
	 { "HDMI_GC_AVMUTE", 0, 0, &umr_bitfield_default },
	 { "HDMI_GC_AVMUTE_CONT", 2, 2, &umr_bitfield_default },
	 { "HDMI_DEFAULT_PHASE", 4, 4, &umr_bitfield_default },
	 { "HDMI_PACKING_PHASE", 8, 11, &umr_bitfield_default },
	 { "HDMI_PACKING_PHASE_OVERRIDE", 12, 12, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG0_AFMT_AUDIO_PACKET_CONTROL2[] = {
	 { "AFMT_AUDIO_LAYOUT_OVRD", 0, 0, &umr_bitfield_default },
	 { "AFMT_AUDIO_LAYOUT_SELECT", 1, 1, &umr_bitfield_default },
	 { "AFMT_AUDIO_CHANNEL_ENABLE", 8, 15, &umr_bitfield_default },
	 { "AFMT_DP_AUDIO_STREAM_ID", 16, 23, &umr_bitfield_default },
	 { "AFMT_HBR_ENABLE_OVRD", 24, 24, &umr_bitfield_default },
	 { "AFMT_60958_OSF_OVRD", 28, 28, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG0_AFMT_ISRC1_0[] = {
	 { "AFMT_ISRC_STATUS", 0, 2, &umr_bitfield_default },
	 { "AFMT_ISRC_CONTINUE", 6, 6, &umr_bitfield_default },
	 { "AFMT_ISRC_VALID", 7, 7, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG0_AFMT_ISRC1_1[] = {
	 { "AFMT_UPC_EAN_ISRC0", 0, 7, &umr_bitfield_default },
	 { "AFMT_UPC_EAN_ISRC1", 8, 15, &umr_bitfield_default },
	 { "AFMT_UPC_EAN_ISRC2", 16, 23, &umr_bitfield_default },
	 { "AFMT_UPC_EAN_ISRC3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG0_AFMT_ISRC1_2[] = {
	 { "AFMT_UPC_EAN_ISRC4", 0, 7, &umr_bitfield_default },
	 { "AFMT_UPC_EAN_ISRC5", 8, 15, &umr_bitfield_default },
	 { "AFMT_UPC_EAN_ISRC6", 16, 23, &umr_bitfield_default },
	 { "AFMT_UPC_EAN_ISRC7", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG0_AFMT_ISRC1_3[] = {
	 { "AFMT_UPC_EAN_ISRC8", 0, 7, &umr_bitfield_default },
	 { "AFMT_UPC_EAN_ISRC9", 8, 15, &umr_bitfield_default },
	 { "AFMT_UPC_EAN_ISRC10", 16, 23, &umr_bitfield_default },
	 { "AFMT_UPC_EAN_ISRC11", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG0_AFMT_ISRC1_4[] = {
	 { "AFMT_UPC_EAN_ISRC12", 0, 7, &umr_bitfield_default },
	 { "AFMT_UPC_EAN_ISRC13", 8, 15, &umr_bitfield_default },
	 { "AFMT_UPC_EAN_ISRC14", 16, 23, &umr_bitfield_default },
	 { "AFMT_UPC_EAN_ISRC15", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG0_AFMT_ISRC2_0[] = {
	 { "AFMT_UPC_EAN_ISRC16", 0, 7, &umr_bitfield_default },
	 { "AFMT_UPC_EAN_ISRC17", 8, 15, &umr_bitfield_default },
	 { "AFMT_UPC_EAN_ISRC18", 16, 23, &umr_bitfield_default },
	 { "AFMT_UPC_EAN_ISRC19", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG0_AFMT_ISRC2_1[] = {
	 { "AFMT_UPC_EAN_ISRC20", 0, 7, &umr_bitfield_default },
	 { "AFMT_UPC_EAN_ISRC21", 8, 15, &umr_bitfield_default },
	 { "AFMT_UPC_EAN_ISRC22", 16, 23, &umr_bitfield_default },
	 { "AFMT_UPC_EAN_ISRC23", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG0_AFMT_ISRC2_2[] = {
	 { "AFMT_UPC_EAN_ISRC24", 0, 7, &umr_bitfield_default },
	 { "AFMT_UPC_EAN_ISRC25", 8, 15, &umr_bitfield_default },
	 { "AFMT_UPC_EAN_ISRC26", 16, 23, &umr_bitfield_default },
	 { "AFMT_UPC_EAN_ISRC27", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG0_AFMT_ISRC2_3[] = {
	 { "AFMT_UPC_EAN_ISRC28", 0, 7, &umr_bitfield_default },
	 { "AFMT_UPC_EAN_ISRC29", 8, 15, &umr_bitfield_default },
	 { "AFMT_UPC_EAN_ISRC30", 16, 23, &umr_bitfield_default },
	 { "AFMT_UPC_EAN_ISRC31", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG0_HDMI_GENERIC_PACKET_CONTROL2[] = {
	 { "HDMI_GENERIC4_SEND", 0, 0, &umr_bitfield_default },
	 { "HDMI_GENERIC4_CONT", 1, 1, &umr_bitfield_default },
	 { "HDMI_GENERIC5_SEND", 4, 4, &umr_bitfield_default },
	 { "HDMI_GENERIC5_CONT", 5, 5, &umr_bitfield_default },
	 { "HDMI_GENERIC4_LINE", 16, 21, &umr_bitfield_default },
	 { "HDMI_GENERIC5_LINE", 24, 29, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG0_HDMI_GENERIC_PACKET_CONTROL3[] = {
	 { "HDMI_GENERIC6_SEND", 0, 0, &umr_bitfield_default },
	 { "HDMI_GENERIC6_CONT", 1, 1, &umr_bitfield_default },
	 { "HDMI_GENERIC7_SEND", 4, 4, &umr_bitfield_default },
	 { "HDMI_GENERIC7_CONT", 5, 5, &umr_bitfield_default },
	 { "HDMI_GENERIC6_LINE", 16, 21, &umr_bitfield_default },
	 { "HDMI_GENERIC7_LINE", 24, 29, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG0_HDMI_DB_CONTROL[] = {
	 { "HDMI_DB_PENDING", 0, 0, &umr_bitfield_default },
	 { "HDMI_DB_TAKEN", 4, 4, &umr_bitfield_default },
	 { "HDMI_DB_TAKEN_CLR", 5, 5, &umr_bitfield_default },
	 { "HDMI_DB_LOCK", 8, 8, &umr_bitfield_default },
	 { "HDMI_DB_DISABLE", 12, 12, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG0_AFMT_MPEG_INFO0[] = {
	 { "AFMT_MPEG_INFO_CHECKSUM", 0, 7, &umr_bitfield_default },
	 { "AFMT_MPEG_INFO_MB0", 8, 15, &umr_bitfield_default },
	 { "AFMT_MPEG_INFO_MB1", 16, 23, &umr_bitfield_default },
	 { "AFMT_MPEG_INFO_MB2", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG0_AFMT_MPEG_INFO1[] = {
	 { "AFMT_MPEG_INFO_MB3", 0, 7, &umr_bitfield_default },
	 { "AFMT_MPEG_INFO_MF", 8, 9, &umr_bitfield_default },
	 { "AFMT_MPEG_INFO_FR", 12, 12, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG0_AFMT_GENERIC_HDR[] = {
	 { "AFMT_GENERIC_HB0", 0, 7, &umr_bitfield_default },
	 { "AFMT_GENERIC_HB1", 8, 15, &umr_bitfield_default },
	 { "AFMT_GENERIC_HB2", 16, 23, &umr_bitfield_default },
	 { "AFMT_GENERIC_HB3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG0_AFMT_GENERIC_0[] = {
	 { "AFMT_GENERIC_BYTE0", 0, 7, &umr_bitfield_default },
	 { "AFMT_GENERIC_BYTE1", 8, 15, &umr_bitfield_default },
	 { "AFMT_GENERIC_BYTE2", 16, 23, &umr_bitfield_default },
	 { "AFMT_GENERIC_BYTE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG0_AFMT_GENERIC_1[] = {
	 { "AFMT_GENERIC_BYTE4", 0, 7, &umr_bitfield_default },
	 { "AFMT_GENERIC_BYTE5", 8, 15, &umr_bitfield_default },
	 { "AFMT_GENERIC_BYTE6", 16, 23, &umr_bitfield_default },
	 { "AFMT_GENERIC_BYTE7", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG0_AFMT_GENERIC_2[] = {
	 { "AFMT_GENERIC_BYTE8", 0, 7, &umr_bitfield_default },
	 { "AFMT_GENERIC_BYTE9", 8, 15, &umr_bitfield_default },
	 { "AFMT_GENERIC_BYTE10", 16, 23, &umr_bitfield_default },
	 { "AFMT_GENERIC_BYTE11", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG0_AFMT_GENERIC_3[] = {
	 { "AFMT_GENERIC_BYTE12", 0, 7, &umr_bitfield_default },
	 { "AFMT_GENERIC_BYTE13", 8, 15, &umr_bitfield_default },
	 { "AFMT_GENERIC_BYTE14", 16, 23, &umr_bitfield_default },
	 { "AFMT_GENERIC_BYTE15", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG0_AFMT_GENERIC_4[] = {
	 { "AFMT_GENERIC_BYTE16", 0, 7, &umr_bitfield_default },
	 { "AFMT_GENERIC_BYTE17", 8, 15, &umr_bitfield_default },
	 { "AFMT_GENERIC_BYTE18", 16, 23, &umr_bitfield_default },
	 { "AFMT_GENERIC_BYTE19", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG0_AFMT_GENERIC_5[] = {
	 { "AFMT_GENERIC_BYTE20", 0, 7, &umr_bitfield_default },
	 { "AFMT_GENERIC_BYTE21", 8, 15, &umr_bitfield_default },
	 { "AFMT_GENERIC_BYTE22", 16, 23, &umr_bitfield_default },
	 { "AFMT_GENERIC_BYTE23", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG0_AFMT_GENERIC_6[] = {
	 { "AFMT_GENERIC_BYTE24", 0, 7, &umr_bitfield_default },
	 { "AFMT_GENERIC_BYTE25", 8, 15, &umr_bitfield_default },
	 { "AFMT_GENERIC_BYTE26", 16, 23, &umr_bitfield_default },
	 { "AFMT_GENERIC_BYTE27", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG0_AFMT_GENERIC_7[] = {
	 { "AFMT_GENERIC_BYTE28", 0, 7, &umr_bitfield_default },
	 { "AFMT_GENERIC_BYTE29", 8, 15, &umr_bitfield_default },
	 { "AFMT_GENERIC_BYTE30", 16, 23, &umr_bitfield_default },
	 { "AFMT_GENERIC_BYTE31", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG0_HDMI_GENERIC_PACKET_CONTROL1[] = {
	 { "HDMI_GENERIC2_SEND", 0, 0, &umr_bitfield_default },
	 { "HDMI_GENERIC2_CONT", 1, 1, &umr_bitfield_default },
	 { "HDMI_GENERIC3_SEND", 4, 4, &umr_bitfield_default },
	 { "HDMI_GENERIC3_CONT", 5, 5, &umr_bitfield_default },
	 { "HDMI_GENERIC2_LINE", 16, 21, &umr_bitfield_default },
	 { "HDMI_GENERIC3_LINE", 24, 29, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG0_HDMI_ACR_32_0[] = {
	 { "HDMI_ACR_CTS_32", 12, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG0_HDMI_ACR_32_1[] = {
	 { "HDMI_ACR_N_32", 0, 19, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG0_HDMI_ACR_44_0[] = {
	 { "HDMI_ACR_CTS_44", 12, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG0_HDMI_ACR_44_1[] = {
	 { "HDMI_ACR_N_44", 0, 19, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG0_HDMI_ACR_48_0[] = {
	 { "HDMI_ACR_CTS_48", 12, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG0_HDMI_ACR_48_1[] = {
	 { "HDMI_ACR_N_48", 0, 19, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG0_HDMI_ACR_STATUS_0[] = {
	 { "HDMI_ACR_CTS", 12, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG0_HDMI_ACR_STATUS_1[] = {
	 { "HDMI_ACR_N", 0, 19, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG0_AFMT_AUDIO_INFO0[] = {
	 { "AFMT_AUDIO_INFO_CHECKSUM", 0, 7, &umr_bitfield_default },
	 { "AFMT_AUDIO_INFO_CC", 8, 10, &umr_bitfield_default },
	 { "AFMT_AUDIO_INFO_CT", 11, 14, &umr_bitfield_default },
	 { "AFMT_AUDIO_INFO_CHECKSUM_OFFSET", 16, 23, &umr_bitfield_default },
	 { "AFMT_AUDIO_INFO_CXT", 24, 28, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG0_AFMT_AUDIO_INFO1[] = {
	 { "AFMT_AUDIO_INFO_CA", 0, 7, &umr_bitfield_default },
	 { "AFMT_AUDIO_INFO_LSV", 11, 14, &umr_bitfield_default },
	 { "AFMT_AUDIO_INFO_DM_INH", 15, 15, &umr_bitfield_default },
	 { "AFMT_AUDIO_INFO_LFEPBL", 16, 17, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG0_AFMT_60958_0[] = {
	 { "AFMT_60958_CS_A", 0, 0, &umr_bitfield_default },
	 { "AFMT_60958_CS_B", 1, 1, &umr_bitfield_default },
	 { "AFMT_60958_CS_C", 2, 2, &umr_bitfield_default },
	 { "AFMT_60958_CS_D", 3, 5, &umr_bitfield_default },
	 { "AFMT_60958_CS_MODE", 6, 7, &umr_bitfield_default },
	 { "AFMT_60958_CS_CATEGORY_CODE", 8, 15, &umr_bitfield_default },
	 { "AFMT_60958_CS_SOURCE_NUMBER", 16, 19, &umr_bitfield_default },
	 { "AFMT_60958_CS_CHANNEL_NUMBER_L", 20, 23, &umr_bitfield_default },
	 { "AFMT_60958_CS_SAMPLING_FREQUENCY", 24, 27, &umr_bitfield_default },
	 { "AFMT_60958_CS_CLOCK_ACCURACY", 28, 29, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG0_AFMT_60958_1[] = {
	 { "AFMT_60958_CS_WORD_LENGTH", 0, 3, &umr_bitfield_default },
	 { "AFMT_60958_CS_ORIGINAL_SAMPLING_FREQUENCY", 4, 7, &umr_bitfield_default },
	 { "AFMT_60958_VALID_L", 16, 16, &umr_bitfield_default },
	 { "AFMT_60958_VALID_R", 18, 18, &umr_bitfield_default },
	 { "AFMT_60958_CS_CHANNEL_NUMBER_R", 20, 23, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG0_AFMT_AUDIO_CRC_CONTROL[] = {
	 { "AFMT_AUDIO_CRC_EN", 0, 0, &umr_bitfield_default },
	 { "AFMT_AUDIO_CRC_CONT", 4, 4, &umr_bitfield_default },
	 { "AFMT_AUDIO_CRC_SOURCE", 8, 8, &umr_bitfield_default },
	 { "AFMT_AUDIO_CRC_CH_SEL", 12, 15, &umr_bitfield_default },
	 { "AFMT_AUDIO_CRC_COUNT", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG0_AFMT_RAMP_CONTROL0[] = {
	 { "AFMT_RAMP_MAX_COUNT", 0, 23, &umr_bitfield_default },
	 { "AFMT_RAMP_DATA_SIGN", 31, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG0_AFMT_RAMP_CONTROL1[] = {
	 { "AFMT_RAMP_MIN_COUNT", 0, 23, &umr_bitfield_default },
	 { "AFMT_AUDIO_TEST_CH_DISABLE", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG0_AFMT_RAMP_CONTROL2[] = {
	 { "AFMT_RAMP_INC_COUNT", 0, 23, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG0_AFMT_RAMP_CONTROL3[] = {
	 { "AFMT_RAMP_DEC_COUNT", 0, 23, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG0_AFMT_60958_2[] = {
	 { "AFMT_60958_CS_CHANNEL_NUMBER_2", 0, 3, &umr_bitfield_default },
	 { "AFMT_60958_CS_CHANNEL_NUMBER_3", 4, 7, &umr_bitfield_default },
	 { "AFMT_60958_CS_CHANNEL_NUMBER_4", 8, 11, &umr_bitfield_default },
	 { "AFMT_60958_CS_CHANNEL_NUMBER_5", 12, 15, &umr_bitfield_default },
	 { "AFMT_60958_CS_CHANNEL_NUMBER_6", 16, 19, &umr_bitfield_default },
	 { "AFMT_60958_CS_CHANNEL_NUMBER_7", 20, 23, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG0_AFMT_AUDIO_CRC_RESULT[] = {
	 { "AFMT_AUDIO_CRC_DONE", 0, 0, &umr_bitfield_default },
	 { "AFMT_AUDIO_CRC", 8, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG0_AFMT_STATUS[] = {
	 { "AFMT_AUDIO_ENABLE", 4, 4, &umr_bitfield_default },
	 { "AFMT_AZ_HBR_ENABLE", 8, 8, &umr_bitfield_default },
	 { "AFMT_AUDIO_FIFO_OVERFLOW", 24, 24, &umr_bitfield_default },
	 { "AFMT_AZ_AUDIO_ENABLE_CHG", 30, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG0_AFMT_AUDIO_PACKET_CONTROL[] = {
	 { "AFMT_AUDIO_SAMPLE_SEND", 0, 0, &umr_bitfield_default },
	 { "AFMT_RESET_FIFO_WHEN_AUDIO_DIS", 11, 11, &umr_bitfield_default },
	 { "AFMT_AUDIO_TEST_EN", 12, 12, &umr_bitfield_default },
	 { "AFMT_AUDIO_TEST_MODE", 14, 14, &umr_bitfield_default },
	 { "AFMT_AUDIO_FIFO_OVERFLOW_ACK", 23, 23, &umr_bitfield_default },
	 { "AFMT_AUDIO_CHANNEL_SWAP", 24, 24, &umr_bitfield_default },
	 { "AFMT_60958_CS_UPDATE", 26, 26, &umr_bitfield_default },
	 { "AFMT_AZ_AUDIO_ENABLE_CHG_ACK", 30, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG0_AFMT_VBI_PACKET_CONTROL[] = {
	 { "AFMT_GENERIC_LOCK_STATUS", 8, 8, &umr_bitfield_default },
	 { "AFMT_GENERIC_CONFLICT", 16, 16, &umr_bitfield_default },
	 { "AFMT_GENERIC_CONFLICT_CLR", 17, 17, &umr_bitfield_default },
	 { "AFMT_GENERIC_INDEX", 28, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG0_AFMT_INFOFRAME_CONTROL0[] = {
	 { "AFMT_AUDIO_INFO_SOURCE", 6, 6, &umr_bitfield_default },
	 { "AFMT_AUDIO_INFO_UPDATE", 7, 7, &umr_bitfield_default },
	 { "AFMT_MPEG_INFO_UPDATE", 10, 10, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG0_AFMT_AUDIO_SRC_CONTROL[] = {
	 { "AFMT_AUDIO_SRC_SELECT", 0, 2, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG0_DIG_BE_CNTL[] = {
	 { "DIG_DUAL_LINK_ENABLE", 0, 0, &umr_bitfield_default },
	 { "DIG_SWAP", 1, 1, &umr_bitfield_default },
	 { "DIG_FE_SOURCE_SELECT", 8, 14, &umr_bitfield_default },
	 { "DIG_MODE", 16, 18, &umr_bitfield_default },
	 { "DIG_HPD_SELECT", 28, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG0_DIG_BE_EN_CNTL[] = {
	 { "DIG_ENABLE", 0, 0, &umr_bitfield_default },
	 { "DIG_SYMCLK_BE_ON", 8, 8, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG0_TMDS_CNTL[] = {
	 { "TMDS_SYNC_PHASE", 0, 0, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG0_TMDS_CONTROL_CHAR[] = {
	 { "TMDS_CONTROL_CHAR0_OUT_EN", 0, 0, &umr_bitfield_default },
	 { "TMDS_CONTROL_CHAR1_OUT_EN", 1, 1, &umr_bitfield_default },
	 { "TMDS_CONTROL_CHAR2_OUT_EN", 2, 2, &umr_bitfield_default },
	 { "TMDS_CONTROL_CHAR3_OUT_EN", 3, 3, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG0_TMDS_CONTROL0_FEEDBACK[] = {
	 { "TMDS_CONTROL0_FEEDBACK_SELECT", 0, 1, &umr_bitfield_default },
	 { "TMDS_CONTROL0_FEEDBACK_DELAY", 8, 9, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG0_TMDS_STEREOSYNC_CTL_SEL[] = {
	 { "TMDS_STEREOSYNC_CTL_SEL", 0, 1, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG0_TMDS_SYNC_CHAR_PATTERN_0_1[] = {
	 { "TMDS_SYNC_CHAR_PATTERN0", 0, 9, &umr_bitfield_default },
	 { "TMDS_SYNC_CHAR_PATTERN1", 16, 25, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG0_TMDS_SYNC_CHAR_PATTERN_2_3[] = {
	 { "TMDS_SYNC_CHAR_PATTERN2", 0, 9, &umr_bitfield_default },
	 { "TMDS_SYNC_CHAR_PATTERN3", 16, 25, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG0_TMDS_CTL_BITS[] = {
	 { "TMDS_CTL0", 0, 0, &umr_bitfield_default },
	 { "TMDS_CTL1", 8, 8, &umr_bitfield_default },
	 { "TMDS_CTL2", 16, 16, &umr_bitfield_default },
	 { "TMDS_CTL3", 24, 24, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG0_TMDS_DCBALANCER_CONTROL[] = {
	 { "TMDS_DCBALANCER_EN", 0, 0, &umr_bitfield_default },
	 { "TMDS_DCBALANCER_TEST_EN", 8, 8, &umr_bitfield_default },
	 { "TMDS_DCBALANCER_TEST_IN", 16, 19, &umr_bitfield_default },
	 { "TMDS_DCBALANCER_FORCE", 24, 24, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG0_TMDS_CTL0_1_GEN_CNTL[] = {
	 { "TMDS_CTL0_DATA_SEL", 0, 3, &umr_bitfield_default },
	 { "TMDS_CTL0_DATA_DELAY", 4, 6, &umr_bitfield_default },
	 { "TMDS_CTL0_DATA_INVERT", 7, 7, &umr_bitfield_default },
	 { "TMDS_CTL0_DATA_MODULATION", 8, 9, &umr_bitfield_default },
	 { "TMDS_CTL0_USE_FEEDBACK_PATH", 10, 10, &umr_bitfield_default },
	 { "TMDS_CTL0_FB_SYNC_CONT", 11, 11, &umr_bitfield_default },
	 { "TMDS_CTL0_PATTERN_OUT_EN", 12, 12, &umr_bitfield_default },
	 { "TMDS_CTL1_DATA_SEL", 16, 19, &umr_bitfield_default },
	 { "TMDS_CTL1_DATA_DELAY", 20, 22, &umr_bitfield_default },
	 { "TMDS_CTL1_DATA_INVERT", 23, 23, &umr_bitfield_default },
	 { "TMDS_CTL1_DATA_MODULATION", 24, 25, &umr_bitfield_default },
	 { "TMDS_CTL1_USE_FEEDBACK_PATH", 26, 26, &umr_bitfield_default },
	 { "TMDS_CTL1_FB_SYNC_CONT", 27, 27, &umr_bitfield_default },
	 { "TMDS_CTL1_PATTERN_OUT_EN", 28, 28, &umr_bitfield_default },
	 { "TMDS_2BIT_COUNTER_EN", 31, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG0_TMDS_CTL2_3_GEN_CNTL[] = {
	 { "TMDS_CTL2_DATA_SEL", 0, 3, &umr_bitfield_default },
	 { "TMDS_CTL2_DATA_DELAY", 4, 6, &umr_bitfield_default },
	 { "TMDS_CTL2_DATA_INVERT", 7, 7, &umr_bitfield_default },
	 { "TMDS_CTL2_DATA_MODULATION", 8, 9, &umr_bitfield_default },
	 { "TMDS_CTL2_USE_FEEDBACK_PATH", 10, 10, &umr_bitfield_default },
	 { "TMDS_CTL2_FB_SYNC_CONT", 11, 11, &umr_bitfield_default },
	 { "TMDS_CTL2_PATTERN_OUT_EN", 12, 12, &umr_bitfield_default },
	 { "TMDS_CTL3_DATA_SEL", 16, 19, &umr_bitfield_default },
	 { "TMDS_CTL3_DATA_DELAY", 20, 22, &umr_bitfield_default },
	 { "TMDS_CTL3_DATA_INVERT", 23, 23, &umr_bitfield_default },
	 { "TMDS_CTL3_DATA_MODULATION", 24, 25, &umr_bitfield_default },
	 { "TMDS_CTL3_USE_FEEDBACK_PATH", 26, 26, &umr_bitfield_default },
	 { "TMDS_CTL3_FB_SYNC_CONT", 27, 27, &umr_bitfield_default },
	 { "TMDS_CTL3_PATTERN_OUT_EN", 28, 28, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG0_DIG_VERSION[] = {
	 { "DIG_TYPE", 0, 0, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG0_DIG_LANE_ENABLE[] = {
	 { "DIG_LANE0EN", 0, 0, &umr_bitfield_default },
	 { "DIG_LANE1EN", 1, 1, &umr_bitfield_default },
	 { "DIG_LANE2EN", 2, 2, &umr_bitfield_default },
	 { "DIG_LANE3EN", 3, 3, &umr_bitfield_default },
	 { "DIG_CLK_EN", 8, 8, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG0_AFMT_CNTL[] = {
	 { "AFMT_AUDIO_CLOCK_EN", 0, 0, &umr_bitfield_default },
	 { "AFMT_AUDIO_CLOCK_ON", 8, 8, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG0_AFMT_VBI_PACKET_CONTROL1[] = {
	 { "AFMT_GENERIC0_FRAME_UPDATE", 0, 0, &umr_bitfield_default },
	 { "AFMT_GENERIC0_FRAME_UPDATE_PENDING", 1, 1, &umr_bitfield_default },
	 { "AFMT_GENERIC0_IMMEDIATE_UPDATE", 2, 2, &umr_bitfield_default },
	 { "AFMT_GENERIC0_IMMEDIATE_UPDATE_PENDING", 3, 3, &umr_bitfield_default },
	 { "AFMT_GENERIC1_FRAME_UPDATE", 4, 4, &umr_bitfield_default },
	 { "AFMT_GENERIC1_FRAME_UPDATE_PENDING", 5, 5, &umr_bitfield_default },
	 { "AFMT_GENERIC1_IMMEDIATE_UPDATE", 6, 6, &umr_bitfield_default },
	 { "AFMT_GENERIC1_IMMEDIATE_UPDATE_PENDING", 7, 7, &umr_bitfield_default },
	 { "AFMT_GENERIC2_FRAME_UPDATE", 8, 8, &umr_bitfield_default },
	 { "AFMT_GENERIC2_FRAME_UPDATE_PENDING", 9, 9, &umr_bitfield_default },
	 { "AFMT_GENERIC2_IMMEDIATE_UPDATE", 10, 10, &umr_bitfield_default },
	 { "AFMT_GENERIC2_IMMEDIATE_UPDATE_PENDING", 11, 11, &umr_bitfield_default },
	 { "AFMT_GENERIC3_FRAME_UPDATE", 12, 12, &umr_bitfield_default },
	 { "AFMT_GENERIC3_FRAME_UPDATE_PENDING", 13, 13, &umr_bitfield_default },
	 { "AFMT_GENERIC3_IMMEDIATE_UPDATE", 14, 14, &umr_bitfield_default },
	 { "AFMT_GENERIC3_IMMEDIATE_UPDATE_PENDING", 15, 15, &umr_bitfield_default },
	 { "AFMT_GENERIC4_FRAME_UPDATE", 16, 16, &umr_bitfield_default },
	 { "AFMT_GENERIC4_FRAME_UPDATE_PENDING", 17, 17, &umr_bitfield_default },
	 { "AFMT_GENERIC4_IMMEDIATE_UPDATE", 18, 18, &umr_bitfield_default },
	 { "AFMT_GENERIC4_IMMEDIATE_UPDATE_PENDING", 19, 19, &umr_bitfield_default },
	 { "AFMT_GENERIC5_FRAME_UPDATE", 20, 20, &umr_bitfield_default },
	 { "AFMT_GENERIC5_FRAME_UPDATE_PENDING", 21, 21, &umr_bitfield_default },
	 { "AFMT_GENERIC5_IMMEDIATE_UPDATE", 22, 22, &umr_bitfield_default },
	 { "AFMT_GENERIC5_IMMEDIATE_UPDATE_PENDING", 23, 23, &umr_bitfield_default },
	 { "AFMT_GENERIC6_FRAME_UPDATE", 24, 24, &umr_bitfield_default },
	 { "AFMT_GENERIC6_FRAME_UPDATE_PENDING", 25, 25, &umr_bitfield_default },
	 { "AFMT_GENERIC6_IMMEDIATE_UPDATE", 26, 26, &umr_bitfield_default },
	 { "AFMT_GENERIC6_IMMEDIATE_UPDATE_PENDING", 27, 27, &umr_bitfield_default },
	 { "AFMT_GENERIC7_FRAME_UPDATE", 28, 28, &umr_bitfield_default },
	 { "AFMT_GENERIC7_FRAME_UPDATE_PENDING", 29, 29, &umr_bitfield_default },
	 { "AFMT_GENERIC7_IMMEDIATE_UPDATE", 30, 30, &umr_bitfield_default },
	 { "AFMT_GENERIC7_IMMEDIATE_UPDATE_PENDING", 31, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDP0_DP_LINK_CNTL[] = {
	 { "DP_LINK_TRAINING_COMPLETE", 4, 4, &umr_bitfield_default },
	 { "DP_LINK_STATUS", 8, 8, &umr_bitfield_default },
	 { "DP_EMBEDDED_PANEL_MODE", 17, 17, &umr_bitfield_default },
};
static struct umr_bitfield mmDP0_DP_PIXEL_FORMAT[] = {
	 { "DP_PIXEL_ENCODING", 0, 2, &umr_bitfield_default },
	 { "DP_COMPONENT_DEPTH", 24, 26, &umr_bitfield_default },
	 { "DP_PIXEL_COMBINE", 28, 29, &umr_bitfield_default },
};
static struct umr_bitfield mmDP0_DP_MSA_COLORIMETRY[] = {
	 { "DP_MSA_MISC0", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDP0_DP_CONFIG[] = {
	 { "DP_UDI_LANES", 0, 1, &umr_bitfield_default },
};
static struct umr_bitfield mmDP0_DP_VID_STREAM_CNTL[] = {
	 { "DP_VID_STREAM_ENABLE", 0, 0, &umr_bitfield_default },
	 { "DP_VID_STREAM_DIS_DEFER", 8, 9, &umr_bitfield_default },
	 { "DP_VID_STREAM_STATUS", 16, 16, &umr_bitfield_default },
	 { "DP_VID_STREAM_CHANGE_KEEPOUT", 20, 20, &umr_bitfield_default },
};
static struct umr_bitfield mmDP0_DP_STEER_FIFO[] = {
	 { "DP_STEER_FIFO_RESET", 0, 0, &umr_bitfield_default },
	 { "DP_STEER_OVERFLOW_FLAG", 4, 4, &umr_bitfield_default },
	 { "DP_STEER_OVERFLOW_INT", 5, 5, &umr_bitfield_default },
	 { "DP_STEER_OVERFLOW_ACK", 6, 6, &umr_bitfield_default },
	 { "DP_STEER_OVERFLOW_MASK", 7, 7, &umr_bitfield_default },
	 { "DP_TU_OVERFLOW_FLAG", 8, 8, &umr_bitfield_default },
	 { "DP_TU_OVERFLOW_ACK", 12, 12, &umr_bitfield_default },
};
static struct umr_bitfield mmDP0_DP_MSA_MISC[] = {
	 { "DP_MSA_MISC1", 0, 7, &umr_bitfield_default },
	 { "DP_MSA_MISC2", 8, 15, &umr_bitfield_default },
	 { "DP_MSA_MISC3", 16, 23, &umr_bitfield_default },
	 { "DP_MSA_MISC4", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDP0_DP_VID_TIMING[] = {
	 { "DP_VID_M_N_DOUBLE_BUFFER_MODE", 4, 4, &umr_bitfield_default },
	 { "DP_VID_M_N_GEN_EN", 8, 8, &umr_bitfield_default },
	 { "DP_VID_N_MUL", 10, 11, &umr_bitfield_default },
	 { "DP_VID_M_DIV", 12, 13, &umr_bitfield_default },
	 { "DP_VID_N_DIV", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDP0_DP_VID_N[] = {
	 { "DP_VID_N", 0, 23, &umr_bitfield_default },
};
static struct umr_bitfield mmDP0_DP_VID_M[] = {
	 { "DP_VID_M", 0, 23, &umr_bitfield_default },
};
static struct umr_bitfield mmDP0_DP_LINK_FRAMING_CNTL[] = {
	 { "DP_IDLE_BS_INTERVAL", 0, 17, &umr_bitfield_default },
	 { "DP_VBID_DISABLE", 24, 24, &umr_bitfield_default },
	 { "DP_VID_ENHANCED_FRAME_MODE", 28, 28, &umr_bitfield_default },
};
static struct umr_bitfield mmDP0_DP_HBR2_EYE_PATTERN[] = {
	 { "DP_HBR2_EYE_PATTERN_ENABLE", 0, 0, &umr_bitfield_default },
};
static struct umr_bitfield mmDP0_DP_VID_MSA_VBID[] = {
	 { "DP_VID_MSA_LOCATION", 0, 11, &umr_bitfield_default },
	 { "DP_VID_VBID_FIELD_POL", 24, 24, &umr_bitfield_default },
};
static struct umr_bitfield mmDP0_DP_VID_INTERRUPT_CNTL[] = {
	 { "DP_VID_STREAM_DISABLE_INT", 0, 0, &umr_bitfield_default },
	 { "DP_VID_STREAM_DISABLE_ACK", 1, 1, &umr_bitfield_default },
	 { "DP_VID_STREAM_DISABLE_MASK", 2, 2, &umr_bitfield_default },
};
static struct umr_bitfield mmDP0_DP_DPHY_CNTL[] = {
	 { "DPHY_ATEST_SEL_LANE0", 0, 0, &umr_bitfield_default },
	 { "DPHY_ATEST_SEL_LANE1", 1, 1, &umr_bitfield_default },
	 { "DPHY_ATEST_SEL_LANE2", 2, 2, &umr_bitfield_default },
	 { "DPHY_ATEST_SEL_LANE3", 3, 3, &umr_bitfield_default },
	 { "DPHY_BYPASS", 16, 16, &umr_bitfield_default },
	 { "DPHY_SKEW_BYPASS", 24, 24, &umr_bitfield_default },
};
static struct umr_bitfield mmDP0_DP_DPHY_TRAINING_PATTERN_SEL[] = {
	 { "DPHY_TRAINING_PATTERN_SEL", 0, 1, &umr_bitfield_default },
};
static struct umr_bitfield mmDP0_DP_DPHY_SYM0[] = {
	 { "DPHY_SYM1", 0, 9, &umr_bitfield_default },
	 { "DPHY_SYM2", 10, 19, &umr_bitfield_default },
	 { "DPHY_SYM3", 20, 29, &umr_bitfield_default },
};
static struct umr_bitfield mmDP0_DP_DPHY_SYM1[] = {
	 { "DPHY_SYM4", 0, 9, &umr_bitfield_default },
	 { "DPHY_SYM5", 10, 19, &umr_bitfield_default },
	 { "DPHY_SYM6", 20, 29, &umr_bitfield_default },
};
static struct umr_bitfield mmDP0_DP_DPHY_SYM2[] = {
	 { "DPHY_SYM7", 0, 9, &umr_bitfield_default },
	 { "DPHY_SYM8", 10, 19, &umr_bitfield_default },
};
static struct umr_bitfield mmDP0_DP_DPHY_8B10B_CNTL[] = {
	 { "DPHY_8B10B_RESET", 8, 8, &umr_bitfield_default },
	 { "DPHY_8B10B_EXT_DISP", 16, 16, &umr_bitfield_default },
	 { "DPHY_8B10B_CUR_DISP", 24, 24, &umr_bitfield_default },
};
static struct umr_bitfield mmDP0_DP_DPHY_PRBS_CNTL[] = {
	 { "DPHY_PRBS_EN", 0, 0, &umr_bitfield_default },
	 { "DPHY_PRBS_SEL", 4, 5, &umr_bitfield_default },
	 { "DPHY_PRBS_SEED", 8, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmDP0_DP_DPHY_SCRAM_CNTL[] = {
	 { "DPHY_SCRAMBLER_DIS", 0, 0, &umr_bitfield_default },
	 { "DPHY_SCRAMBLER_ADVANCE", 4, 4, &umr_bitfield_default },
	 { "DPHY_SCRAMBLER_BS_COUNT", 8, 17, &umr_bitfield_default },
	 { "DPHY_SCRAMBLER_KCODE", 24, 24, &umr_bitfield_default },
};
static struct umr_bitfield mmDP0_DP_DPHY_CRC_EN[] = {
	 { "DPHY_CRC_EN", 0, 0, &umr_bitfield_default },
	 { "DPHY_CRC_CONT_EN", 4, 4, &umr_bitfield_default },
	 { "DPHY_CRC_RESULT_VALID", 8, 8, &umr_bitfield_default },
};
static struct umr_bitfield mmDP0_DP_DPHY_CRC_CNTL[] = {
	 { "DPHY_CRC_FIELD", 0, 0, &umr_bitfield_default },
	 { "DPHY_CRC_SEL", 4, 5, &umr_bitfield_default },
	 { "DPHY_CRC_MASK", 16, 23, &umr_bitfield_default },
};
static struct umr_bitfield mmDP0_DP_DPHY_CRC_RESULT[] = {
	 { "DPHY_CRC_RESULT", 0, 7, &umr_bitfield_default },
	 { "DPHY_CRC_RESULT1", 8, 15, &umr_bitfield_default },
	 { "DPHY_CRC_RESULT2", 16, 23, &umr_bitfield_default },
	 { "DPHY_CRC_RESULT3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDP0_DP_DPHY_CRC_MST_CNTL[] = {
	 { "DPHY_CRC_MST_FIRST_SLOT", 0, 5, &umr_bitfield_default },
	 { "DPHY_CRC_MST_LAST_SLOT", 8, 13, &umr_bitfield_default },
};
static struct umr_bitfield mmDP0_DP_DPHY_CRC_MST_STATUS[] = {
	 { "DPHY_CRC_MST_PHASE_LOCK", 0, 0, &umr_bitfield_default },
	 { "DPHY_CRC_MST_PHASE_ERROR", 8, 8, &umr_bitfield_default },
	 { "DPHY_CRC_MST_PHASE_ERROR_ACK", 16, 16, &umr_bitfield_default },
};
static struct umr_bitfield mmDP0_DP_DPHY_FAST_TRAINING[] = {
	 { "DPHY_RX_FAST_TRAINING_CAPABLE", 0, 0, &umr_bitfield_default },
	 { "DPHY_SW_FAST_TRAINING_START", 1, 1, &umr_bitfield_default },
	 { "DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN", 2, 2, &umr_bitfield_default },
	 { "DPHY_FAST_TRAINING_TP1_TIME", 8, 19, &umr_bitfield_default },
	 { "DPHY_FAST_TRAINING_TP2_TIME", 20, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDP0_DP_DPHY_FAST_TRAINING_STATUS[] = {
	 { "DPHY_FAST_TRAINING_STATE", 0, 2, &umr_bitfield_default },
	 { "DPHY_FAST_TRAINING_COMPLETE_OCCURRED", 4, 4, &umr_bitfield_default },
	 { "DPHY_FAST_TRAINING_COMPLETE_MASK", 8, 8, &umr_bitfield_default },
	 { "DPHY_FAST_TRAINING_COMPLETE_ACK", 12, 12, &umr_bitfield_default },
};
static struct umr_bitfield mmDP0_DP_SEC_CNTL[] = {
	 { "DP_SEC_STREAM_ENABLE", 0, 0, &umr_bitfield_default },
	 { "DP_SEC_ASP_ENABLE", 4, 4, &umr_bitfield_default },
	 { "DP_SEC_ATP_ENABLE", 8, 8, &umr_bitfield_default },
	 { "DP_SEC_AIP_ENABLE", 12, 12, &umr_bitfield_default },
	 { "DP_SEC_ACM_ENABLE", 16, 16, &umr_bitfield_default },
	 { "DP_SEC_GSP0_ENABLE", 20, 20, &umr_bitfield_default },
	 { "DP_SEC_GSP1_ENABLE", 21, 21, &umr_bitfield_default },
	 { "DP_SEC_GSP2_ENABLE", 22, 22, &umr_bitfield_default },
	 { "DP_SEC_GSP3_ENABLE", 23, 23, &umr_bitfield_default },
	 { "DP_SEC_GSP4_ENABLE", 24, 24, &umr_bitfield_default },
	 { "DP_SEC_GSP5_ENABLE", 25, 25, &umr_bitfield_default },
	 { "DP_SEC_GSP6_ENABLE", 26, 26, &umr_bitfield_default },
	 { "DP_SEC_GSP7_ENABLE", 27, 27, &umr_bitfield_default },
	 { "DP_SEC_MPG_ENABLE", 28, 28, &umr_bitfield_default },
};
static struct umr_bitfield mmDP0_DP_SEC_CNTL1[] = {
	 { "DP_SEC_ISRC_ENABLE", 0, 0, &umr_bitfield_default },
	 { "DP_SEC_GSP0_PRIORITY", 4, 4, &umr_bitfield_default },
	 { "DP_SEC_GSP0_SEND", 5, 5, &umr_bitfield_default },
	 { "DP_SEC_GSP0_SEND_PENDING", 6, 6, &umr_bitfield_default },
	 { "DP_SEC_GSP0_SEND_DEADLINE_MISSED", 7, 7, &umr_bitfield_default },
	 { "DP_SEC_GSP0_SEND_ANY_LINE", 8, 8, &umr_bitfield_default },
	 { "DP_SEC_GSP0_LINE_NUM", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDP0_DP_SEC_FRAMING1[] = {
	 { "DP_SEC_FRAME_START_LOCATION", 0, 11, &umr_bitfield_default },
	 { "DP_SEC_VBLANK_TRANSMIT_WIDTH", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDP0_DP_SEC_FRAMING2[] = {
	 { "DP_SEC_START_POSITION", 0, 15, &umr_bitfield_default },
	 { "DP_SEC_HBLANK_TRANSMIT_WIDTH", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDP0_DP_SEC_FRAMING3[] = {
	 { "DP_SEC_IDLE_FRAME_SIZE", 0, 13, &umr_bitfield_default },
	 { "DP_SEC_IDLE_TRANSMIT_WIDTH", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDP0_DP_SEC_FRAMING4[] = {
	 { "DP_SEC_COLLISION_STATUS", 20, 20, &umr_bitfield_default },
	 { "DP_SEC_COLLISION_ACK", 24, 24, &umr_bitfield_default },
	 { "DP_SEC_AUDIO_MUTE", 28, 28, &umr_bitfield_default },
	 { "DP_SEC_AUDIO_MUTE_STATUS", 29, 29, &umr_bitfield_default },
};
static struct umr_bitfield mmDP0_DP_SEC_AUD_N[] = {
	 { "DP_SEC_AUD_N", 0, 23, &umr_bitfield_default },
};
static struct umr_bitfield mmDP0_DP_SEC_AUD_N_READBACK[] = {
	 { "DP_SEC_AUD_N_READBACK", 0, 23, &umr_bitfield_default },
};
static struct umr_bitfield mmDP0_DP_SEC_AUD_M[] = {
	 { "DP_SEC_AUD_M", 0, 23, &umr_bitfield_default },
};
static struct umr_bitfield mmDP0_DP_SEC_AUD_M_READBACK[] = {
	 { "DP_SEC_AUD_M_READBACK", 0, 23, &umr_bitfield_default },
};
static struct umr_bitfield mmDP0_DP_SEC_TIMESTAMP[] = {
	 { "DP_SEC_TIMESTAMP_MODE", 0, 0, &umr_bitfield_default },
};
static struct umr_bitfield mmDP0_DP_SEC_PACKET_CNTL[] = {
	 { "DP_SEC_ASP_CODING_TYPE", 1, 3, &umr_bitfield_default },
	 { "DP_SEC_ASP_PRIORITY", 4, 4, &umr_bitfield_default },
	 { "DP_SEC_VERSION", 8, 13, &umr_bitfield_default },
	 { "DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE", 16, 16, &umr_bitfield_default },
};
static struct umr_bitfield mmDP0_DP_MSE_RATE_CNTL[] = {
	 { "DP_MSE_RATE_Y", 0, 25, &umr_bitfield_default },
	 { "DP_MSE_RATE_X", 26, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDP0_DP_MSE_RATE_UPDATE[] = {
	 { "DP_MSE_RATE_UPDATE_PENDING", 0, 0, &umr_bitfield_default },
};
static struct umr_bitfield mmDP0_DP_MSE_SAT0[] = {
	 { "DP_MSE_SAT_SRC0", 0, 2, &umr_bitfield_default },
	 { "DP_MSE_SAT_SLOT_COUNT0", 8, 13, &umr_bitfield_default },
	 { "DP_MSE_SAT_SRC1", 16, 18, &umr_bitfield_default },
	 { "DP_MSE_SAT_SLOT_COUNT1", 24, 29, &umr_bitfield_default },
};
static struct umr_bitfield mmDP0_DP_MSE_SAT1[] = {
	 { "DP_MSE_SAT_SRC2", 0, 2, &umr_bitfield_default },
	 { "DP_MSE_SAT_SLOT_COUNT2", 8, 13, &umr_bitfield_default },
	 { "DP_MSE_SAT_SRC3", 16, 18, &umr_bitfield_default },
	 { "DP_MSE_SAT_SLOT_COUNT3", 24, 29, &umr_bitfield_default },
};
static struct umr_bitfield mmDP0_DP_MSE_SAT2[] = {
	 { "DP_MSE_SAT_SRC4", 0, 2, &umr_bitfield_default },
	 { "DP_MSE_SAT_SLOT_COUNT4", 8, 13, &umr_bitfield_default },
	 { "DP_MSE_SAT_SRC5", 16, 18, &umr_bitfield_default },
	 { "DP_MSE_SAT_SLOT_COUNT5", 24, 29, &umr_bitfield_default },
};
static struct umr_bitfield mmDP0_DP_MSE_SAT_UPDATE[] = {
	 { "DP_MSE_SAT_UPDATE", 0, 1, &umr_bitfield_default },
	 { "DP_MSE_16_MTP_KEEPOUT", 8, 8, &umr_bitfield_default },
};
static struct umr_bitfield mmDP0_DP_MSE_LINK_TIMING[] = {
	 { "DP_MSE_LINK_FRAME", 0, 9, &umr_bitfield_default },
	 { "DP_MSE_LINK_LINE", 16, 17, &umr_bitfield_default },
};
static struct umr_bitfield mmDP0_DP_MSE_MISC_CNTL[] = {
	 { "DP_MSE_BLANK_CODE", 0, 0, &umr_bitfield_default },
	 { "DP_MSE_TIMESTAMP_MODE", 4, 4, &umr_bitfield_default },
	 { "DP_MSE_ZERO_ENCODER", 8, 8, &umr_bitfield_default },
};
static struct umr_bitfield mmDP0_DP_DPHY_BS_SR_SWAP_CNTL[] = {
	 { "DPHY_LOAD_BS_COUNT", 0, 9, &umr_bitfield_default },
	 { "DPHY_BS_SR_SWAP_DONE", 15, 15, &umr_bitfield_default },
	 { "DPHY_LOAD_BS_COUNT_START", 16, 16, &umr_bitfield_default },
};
static struct umr_bitfield mmDP0_DP_DPHY_HBR2_PATTERN_CONTROL[] = {
	 { "DP_DPHY_HBR2_PATTERN_CONTROL", 0, 2, &umr_bitfield_default },
};
static struct umr_bitfield mmDP0_DP_MSE_SAT0_STATUS[] = {
	 { "DP_MSE_SAT_SRC0_STATUS", 0, 2, &umr_bitfield_default },
	 { "DP_MSE_SAT_SLOT_COUNT0_STATUS", 8, 13, &umr_bitfield_default },
	 { "DP_MSE_SAT_SRC1_STATUS", 16, 18, &umr_bitfield_default },
	 { "DP_MSE_SAT_SLOT_COUNT1_STATUS", 24, 29, &umr_bitfield_default },
};
static struct umr_bitfield mmDP0_DP_MSE_SAT1_STATUS[] = {
	 { "DP_MSE_SAT_SRC2_STATUS", 0, 2, &umr_bitfield_default },
	 { "DP_MSE_SAT_SLOT_COUNT2_STATUS", 8, 13, &umr_bitfield_default },
	 { "DP_MSE_SAT_SRC3_STATUS", 16, 18, &umr_bitfield_default },
	 { "DP_MSE_SAT_SLOT_COUNT3_STATUS", 24, 29, &umr_bitfield_default },
};
static struct umr_bitfield mmDP0_DP_MSE_SAT2_STATUS[] = {
	 { "DP_MSE_SAT_SRC4_STATUS", 0, 2, &umr_bitfield_default },
	 { "DP_MSE_SAT_SLOT_COUNT4_STATUS", 8, 13, &umr_bitfield_default },
	 { "DP_MSE_SAT_SRC5_STATUS", 16, 18, &umr_bitfield_default },
	 { "DP_MSE_SAT_SLOT_COUNT5_STATUS", 24, 29, &umr_bitfield_default },
};
static struct umr_bitfield mmDP0_DP_MSA_TIMING_PARAM1[] = {
	 { "DP_MSA_VTOTAL", 0, 15, &umr_bitfield_default },
	 { "DP_MSA_HTOTAL", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDP0_DP_MSA_TIMING_PARAM2[] = {
	 { "DP_MSA_VSTART", 0, 15, &umr_bitfield_default },
	 { "DP_MSA_HSTART", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDP0_DP_MSA_TIMING_PARAM3[] = {
	 { "DP_MSA_VSYNCWIDTH", 0, 14, &umr_bitfield_default },
	 { "DP_MSA_VSYNCPOLARITY", 15, 15, &umr_bitfield_default },
	 { "DP_MSA_HSYNCWIDTH", 16, 30, &umr_bitfield_default },
	 { "DP_MSA_HSYNCPOLARITY", 31, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDP0_DP_MSA_TIMING_PARAM4[] = {
	 { "DP_MSA_VHEIGHT", 0, 15, &umr_bitfield_default },
	 { "DP_MSA_HWIDTH", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDP0_DP_MSO_CNTL[] = {
	 { "DP_MSO_NUM_OF_SSTLINK", 0, 1, &umr_bitfield_default },
	 { "DP_MSO_SEC_STREAM_ENABLE", 4, 7, &umr_bitfield_default },
	 { "DP_MSO_SEC_ASP_ENABLE", 8, 11, &umr_bitfield_default },
	 { "DP_MSO_SEC_ATP_ENABLE", 12, 15, &umr_bitfield_default },
	 { "DP_MSO_SEC_AIP_ENABLE", 16, 19, &umr_bitfield_default },
	 { "DP_MSO_SEC_ACM_ENABLE", 20, 23, &umr_bitfield_default },
	 { "DP_MSO_SEC_GSP0_ENABLE", 24, 27, &umr_bitfield_default },
	 { "DP_MSO_SEC_GSP1_ENABLE", 28, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDP0_DP_MSO_CNTL1[] = {
	 { "DP_MSO_SEC_GSP2_ENABLE", 0, 3, &umr_bitfield_default },
	 { "DP_MSO_SEC_GSP3_ENABLE", 4, 7, &umr_bitfield_default },
	 { "DP_MSO_SEC_GSP4_ENABLE", 8, 11, &umr_bitfield_default },
	 { "DP_MSO_SEC_GSP5_ENABLE", 12, 15, &umr_bitfield_default },
	 { "DP_MSO_SEC_GSP6_ENABLE", 16, 19, &umr_bitfield_default },
	 { "DP_MSO_SEC_GSP7_ENABLE", 20, 23, &umr_bitfield_default },
	 { "DP_MSO_SEC_MPG_ENABLE", 24, 27, &umr_bitfield_default },
	 { "DP_MSO_SEC_ISRC_ENABLE", 28, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDP0_DP_DSC_CNTL[] = {
	 { "DP_DSC_EN", 0, 0, &umr_bitfield_default },
};
static struct umr_bitfield mmDP0_DP_SEC_CNTL2[] = {
	 { "DP_SEC_GSP1_SEND", 0, 0, &umr_bitfield_default },
	 { "DP_SEC_GSP1_SEND_PENDING", 1, 1, &umr_bitfield_default },
	 { "DP_SEC_GSP1_SEND_DEADLINE_MISSED", 2, 2, &umr_bitfield_default },
	 { "DP_SEC_GSP1_SEND_ANY_LINE", 3, 3, &umr_bitfield_default },
	 { "DP_SEC_GSP2_SEND", 4, 4, &umr_bitfield_default },
	 { "DP_SEC_GSP2_SEND_PENDING", 5, 5, &umr_bitfield_default },
	 { "DP_SEC_GSP2_SEND_DEADLINE_MISSED", 6, 6, &umr_bitfield_default },
	 { "DP_SEC_GSP2_SEND_ANY_LINE", 7, 7, &umr_bitfield_default },
	 { "DP_SEC_GSP3_SEND", 8, 8, &umr_bitfield_default },
	 { "DP_SEC_GSP3_SEND_PENDING", 9, 9, &umr_bitfield_default },
	 { "DP_SEC_GSP3_SEND_DEADLINE_MISSED", 10, 10, &umr_bitfield_default },
	 { "DP_SEC_GSP3_SEND_ANY_LINE", 11, 11, &umr_bitfield_default },
	 { "DP_SEC_GSP4_SEND", 12, 12, &umr_bitfield_default },
	 { "DP_SEC_GSP4_SEND_PENDING", 13, 13, &umr_bitfield_default },
	 { "DP_SEC_GSP4_SEND_DEADLINE_MISSED", 14, 14, &umr_bitfield_default },
	 { "DP_SEC_GSP4_SEND_ANY_LINE", 15, 15, &umr_bitfield_default },
	 { "DP_SEC_GSP5_SEND", 16, 16, &umr_bitfield_default },
	 { "DP_SEC_GSP5_SEND_PENDING", 17, 17, &umr_bitfield_default },
	 { "DP_SEC_GSP5_SEND_DEADLINE_MISSED", 18, 18, &umr_bitfield_default },
	 { "DP_SEC_GSP5_SEND_ANY_LINE", 19, 19, &umr_bitfield_default },
	 { "DP_SEC_GSP6_SEND", 20, 20, &umr_bitfield_default },
	 { "DP_SEC_GSP6_SEND_PENDING", 21, 21, &umr_bitfield_default },
	 { "DP_SEC_GSP6_SEND_DEADLINE_MISSED", 22, 22, &umr_bitfield_default },
	 { "DP_SEC_GSP6_SEND_ANY_LINE", 23, 23, &umr_bitfield_default },
	 { "DP_SEC_GSP7_SEND", 24, 24, &umr_bitfield_default },
	 { "DP_SEC_GSP7_SEND_PENDING", 25, 25, &umr_bitfield_default },
	 { "DP_SEC_GSP7_SEND_DEADLINE_MISSED", 26, 26, &umr_bitfield_default },
	 { "DP_SEC_GSP7_SEND_ANY_LINE", 27, 27, &umr_bitfield_default },
	 { "DP_SEC_GSP7_PPS", 28, 28, &umr_bitfield_default },
};
static struct umr_bitfield mmDP0_DP_SEC_CNTL3[] = {
	 { "DP_SEC_GSP1_LINE_NUM", 0, 15, &umr_bitfield_default },
	 { "DP_SEC_GSP2_LINE_NUM", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDP0_DP_SEC_CNTL4[] = {
	 { "DP_SEC_GSP3_LINE_NUM", 0, 15, &umr_bitfield_default },
	 { "DP_SEC_GSP4_LINE_NUM", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDP0_DP_SEC_CNTL5[] = {
	 { "DP_SEC_GSP5_LINE_NUM", 0, 15, &umr_bitfield_default },
	 { "DP_SEC_GSP6_LINE_NUM", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDP0_DP_SEC_CNTL6[] = {
	 { "DP_SEC_GSP7_LINE_NUM", 0, 15, &umr_bitfield_default },
};
static struct umr_bitfield mmDP0_DP_SEC_CNTL7[] = {
	 { "DP_SEC_GSP0_SEND_ACTIVE", 0, 0, &umr_bitfield_default },
	 { "DP_SEC_GSP1_SEND_ACTIVE", 4, 4, &umr_bitfield_default },
	 { "DP_SEC_GSP2_SEND_ACTIVE", 8, 8, &umr_bitfield_default },
	 { "DP_SEC_GSP3_SEND_ACTIVE", 12, 12, &umr_bitfield_default },
	 { "DP_SEC_GSP4_SEND_ACTIVE", 16, 16, &umr_bitfield_default },
	 { "DP_SEC_GSP5_SEND_ACTIVE", 20, 20, &umr_bitfield_default },
	 { "DP_SEC_GSP6_SEND_ACTIVE", 24, 24, &umr_bitfield_default },
	 { "DP_SEC_GSP7_SEND_ACTIVE", 28, 28, &umr_bitfield_default },
};
static struct umr_bitfield mmDP0_DP_DB_CNTL[] = {
	 { "DP_DB_PENDING", 0, 0, &umr_bitfield_default },
	 { "DP_DB_TAKEN", 4, 4, &umr_bitfield_default },
	 { "DP_DB_TAKEN_CLR", 5, 5, &umr_bitfield_default },
	 { "DP_DB_LOCK", 8, 8, &umr_bitfield_default },
	 { "DP_DB_DISABLE", 12, 12, &umr_bitfield_default },
};
static struct umr_bitfield mmDP0_DP_MSA_VBID_MISC[] = {
	 { "DP_MSA_MISC1_STEREOSYNC_OVERRIDE", 0, 1, &umr_bitfield_default },
	 { "DP_MSA_MISC1_STEREOSYNC_OVERRIDE_EN", 4, 4, &umr_bitfield_default },
	 { "DP_VBID1_OVERRIDE", 8, 8, &umr_bitfield_default },
	 { "DP_VBID2_OVERRIDE", 9, 9, &umr_bitfield_default },
	 { "DP_VBID1_OVERRIDE_EN", 12, 12, &umr_bitfield_default },
	 { "DP_VBID2_OVERRIDE_EN", 13, 13, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG1_DIG_FE_CNTL[] = {
	 { "DIG_SOURCE_SELECT", 0, 2, &umr_bitfield_default },
	 { "DIG_STEREOSYNC_SELECT", 4, 6, &umr_bitfield_default },
	 { "DIG_STEREOSYNC_GATE_EN", 8, 8, &umr_bitfield_default },
	 { "DIG_START", 10, 10, &umr_bitfield_default },
	 { "DIG_DIGITAL_BYPASS_SELECT", 12, 14, &umr_bitfield_default },
	 { "DIG_SYMCLK_FE_ON", 24, 24, &umr_bitfield_default },
	 { "TMDS_PIXEL_ENCODING", 28, 28, &umr_bitfield_default },
	 { "TMDS_COLOR_FORMAT", 30, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG1_DIG_OUTPUT_CRC_CNTL[] = {
	 { "DIG_OUTPUT_CRC_EN", 0, 0, &umr_bitfield_default },
	 { "DIG_OUTPUT_CRC_LINK_SEL", 4, 4, &umr_bitfield_default },
	 { "DIG_OUTPUT_CRC_DATA_SEL", 8, 9, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG1_DIG_OUTPUT_CRC_RESULT[] = {
	 { "DIG_OUTPUT_CRC_RESULT", 0, 29, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG1_DIG_CLOCK_PATTERN[] = {
	 { "DIG_CLOCK_PATTERN", 0, 9, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG1_DIG_TEST_PATTERN[] = {
	 { "DIG_TEST_PATTERN_OUT_EN", 0, 0, &umr_bitfield_default },
	 { "DIG_HALF_CLOCK_PATTERN_SEL", 1, 1, &umr_bitfield_default },
	 { "DIG_RANDOM_PATTERN_OUT_EN", 4, 4, &umr_bitfield_default },
	 { "DIG_RANDOM_PATTERN_RESET", 5, 5, &umr_bitfield_default },
	 { "DIG_TEST_PATTERN_EXTERNAL_RESET_EN", 6, 6, &umr_bitfield_default },
	 { "DIG_STATIC_TEST_PATTERN", 16, 25, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG1_DIG_RANDOM_PATTERN_SEED[] = {
	 { "DIG_RANDOM_PATTERN_SEED", 0, 23, &umr_bitfield_default },
	 { "DIG_RAN_PAT_DURING_DE_ONLY", 24, 24, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG1_DIG_FIFO_STATUS[] = {
	 { "DIG_FIFO_LEVEL_ERROR", 0, 0, &umr_bitfield_default },
	 { "DIG_FIFO_USE_OVERWRITE_LEVEL", 1, 1, &umr_bitfield_default },
	 { "DIG_FIFO_OVERWRITE_LEVEL", 2, 7, &umr_bitfield_default },
	 { "DIG_FIFO_ERROR_ACK", 8, 8, &umr_bitfield_default },
	 { "DIG_FIFO_CAL_AVERAGE_LEVEL", 10, 15, &umr_bitfield_default },
	 { "DIG_FIFO_MAXIMUM_LEVEL", 16, 20, &umr_bitfield_default },
	 { "DIG_FIFO_MINIMUM_LEVEL", 22, 25, &umr_bitfield_default },
	 { "DIG_FIFO_READ_CLOCK_SRC", 26, 26, &umr_bitfield_default },
	 { "DIG_FIFO_CALIBRATED", 29, 29, &umr_bitfield_default },
	 { "DIG_FIFO_FORCE_RECAL_AVERAGE", 30, 30, &umr_bitfield_default },
	 { "DIG_FIFO_FORCE_RECOMP_MINMAX", 31, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG1_HDMI_CONTROL[] = {
	 { "HDMI_KEEPOUT_MODE", 0, 0, &umr_bitfield_default },
	 { "HDMI_DATA_SCRAMBLE_EN", 1, 1, &umr_bitfield_default },
	 { "HDMI_CLOCK_CHANNEL_RATE", 2, 2, &umr_bitfield_default },
	 { "HDMI_NO_EXTRA_NULL_PACKET_FILLED", 3, 3, &umr_bitfield_default },
	 { "HDMI_PACKET_GEN_VERSION", 4, 4, &umr_bitfield_default },
	 { "HDMI_ERROR_ACK", 8, 8, &umr_bitfield_default },
	 { "HDMI_ERROR_MASK", 9, 9, &umr_bitfield_default },
	 { "HDMI_DEEP_COLOR_ENABLE", 24, 24, &umr_bitfield_default },
	 { "HDMI_DEEP_COLOR_DEPTH", 28, 29, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG1_HDMI_STATUS[] = {
	 { "HDMI_ACTIVE_AVMUTE", 0, 0, &umr_bitfield_default },
	 { "HDMI_AUDIO_PACKET_ERROR", 16, 16, &umr_bitfield_default },
	 { "HDMI_VBI_PACKET_ERROR", 20, 20, &umr_bitfield_default },
	 { "HDMI_ERROR_INT", 27, 27, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG1_HDMI_AUDIO_PACKET_CONTROL[] = {
	 { "HDMI_AUDIO_DELAY_EN", 4, 5, &umr_bitfield_default },
	 { "HDMI_AUDIO_PACKETS_PER_LINE", 16, 20, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG1_HDMI_ACR_PACKET_CONTROL[] = {
	 { "HDMI_ACR_SEND", 0, 0, &umr_bitfield_default },
	 { "HDMI_ACR_CONT", 1, 1, &umr_bitfield_default },
	 { "HDMI_ACR_SELECT", 4, 5, &umr_bitfield_default },
	 { "HDMI_ACR_SOURCE", 8, 8, &umr_bitfield_default },
	 { "HDMI_ACR_AUTO_SEND", 12, 12, &umr_bitfield_default },
	 { "HDMI_ACR_N_MULTIPLE", 16, 18, &umr_bitfield_default },
	 { "HDMI_ACR_AUDIO_PRIORITY", 31, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG1_HDMI_VBI_PACKET_CONTROL[] = {
	 { "HDMI_NULL_SEND", 0, 0, &umr_bitfield_default },
	 { "HDMI_GC_SEND", 4, 4, &umr_bitfield_default },
	 { "HDMI_GC_CONT", 5, 5, &umr_bitfield_default },
	 { "HDMI_ISRC_SEND", 8, 8, &umr_bitfield_default },
	 { "HDMI_ISRC_CONT", 9, 9, &umr_bitfield_default },
	 { "HDMI_ISRC_LINE", 16, 21, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG1_HDMI_INFOFRAME_CONTROL0[] = {
	 { "HDMI_AUDIO_INFO_SEND", 4, 4, &umr_bitfield_default },
	 { "HDMI_AUDIO_INFO_CONT", 5, 5, &umr_bitfield_default },
	 { "HDMI_MPEG_INFO_SEND", 8, 8, &umr_bitfield_default },
	 { "HDMI_MPEG_INFO_CONT", 9, 9, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG1_HDMI_INFOFRAME_CONTROL1[] = {
	 { "HDMI_AUDIO_INFO_LINE", 8, 13, &umr_bitfield_default },
	 { "HDMI_MPEG_INFO_LINE", 16, 21, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG1_HDMI_GENERIC_PACKET_CONTROL0[] = {
	 { "HDMI_GENERIC0_SEND", 0, 0, &umr_bitfield_default },
	 { "HDMI_GENERIC0_CONT", 1, 1, &umr_bitfield_default },
	 { "HDMI_GENERIC1_SEND", 4, 4, &umr_bitfield_default },
	 { "HDMI_GENERIC1_CONT", 5, 5, &umr_bitfield_default },
	 { "HDMI_GENERIC0_LINE", 16, 21, &umr_bitfield_default },
	 { "HDMI_GENERIC1_LINE", 24, 29, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG1_HDMI_GC[] = {
	 { "HDMI_GC_AVMUTE", 0, 0, &umr_bitfield_default },
	 { "HDMI_GC_AVMUTE_CONT", 2, 2, &umr_bitfield_default },
	 { "HDMI_DEFAULT_PHASE", 4, 4, &umr_bitfield_default },
	 { "HDMI_PACKING_PHASE", 8, 11, &umr_bitfield_default },
	 { "HDMI_PACKING_PHASE_OVERRIDE", 12, 12, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG1_AFMT_AUDIO_PACKET_CONTROL2[] = {
	 { "AFMT_AUDIO_LAYOUT_OVRD", 0, 0, &umr_bitfield_default },
	 { "AFMT_AUDIO_LAYOUT_SELECT", 1, 1, &umr_bitfield_default },
	 { "AFMT_AUDIO_CHANNEL_ENABLE", 8, 15, &umr_bitfield_default },
	 { "AFMT_DP_AUDIO_STREAM_ID", 16, 23, &umr_bitfield_default },
	 { "AFMT_HBR_ENABLE_OVRD", 24, 24, &umr_bitfield_default },
	 { "AFMT_60958_OSF_OVRD", 28, 28, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG1_AFMT_ISRC1_0[] = {
	 { "AFMT_ISRC_STATUS", 0, 2, &umr_bitfield_default },
	 { "AFMT_ISRC_CONTINUE", 6, 6, &umr_bitfield_default },
	 { "AFMT_ISRC_VALID", 7, 7, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG1_AFMT_ISRC1_1[] = {
	 { "AFMT_UPC_EAN_ISRC0", 0, 7, &umr_bitfield_default },
	 { "AFMT_UPC_EAN_ISRC1", 8, 15, &umr_bitfield_default },
	 { "AFMT_UPC_EAN_ISRC2", 16, 23, &umr_bitfield_default },
	 { "AFMT_UPC_EAN_ISRC3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG1_AFMT_ISRC1_2[] = {
	 { "AFMT_UPC_EAN_ISRC4", 0, 7, &umr_bitfield_default },
	 { "AFMT_UPC_EAN_ISRC5", 8, 15, &umr_bitfield_default },
	 { "AFMT_UPC_EAN_ISRC6", 16, 23, &umr_bitfield_default },
	 { "AFMT_UPC_EAN_ISRC7", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG1_AFMT_ISRC1_3[] = {
	 { "AFMT_UPC_EAN_ISRC8", 0, 7, &umr_bitfield_default },
	 { "AFMT_UPC_EAN_ISRC9", 8, 15, &umr_bitfield_default },
	 { "AFMT_UPC_EAN_ISRC10", 16, 23, &umr_bitfield_default },
	 { "AFMT_UPC_EAN_ISRC11", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG1_AFMT_ISRC1_4[] = {
	 { "AFMT_UPC_EAN_ISRC12", 0, 7, &umr_bitfield_default },
	 { "AFMT_UPC_EAN_ISRC13", 8, 15, &umr_bitfield_default },
	 { "AFMT_UPC_EAN_ISRC14", 16, 23, &umr_bitfield_default },
	 { "AFMT_UPC_EAN_ISRC15", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG1_AFMT_ISRC2_0[] = {
	 { "AFMT_UPC_EAN_ISRC16", 0, 7, &umr_bitfield_default },
	 { "AFMT_UPC_EAN_ISRC17", 8, 15, &umr_bitfield_default },
	 { "AFMT_UPC_EAN_ISRC18", 16, 23, &umr_bitfield_default },
	 { "AFMT_UPC_EAN_ISRC19", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG1_AFMT_ISRC2_1[] = {
	 { "AFMT_UPC_EAN_ISRC20", 0, 7, &umr_bitfield_default },
	 { "AFMT_UPC_EAN_ISRC21", 8, 15, &umr_bitfield_default },
	 { "AFMT_UPC_EAN_ISRC22", 16, 23, &umr_bitfield_default },
	 { "AFMT_UPC_EAN_ISRC23", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG1_AFMT_ISRC2_2[] = {
	 { "AFMT_UPC_EAN_ISRC24", 0, 7, &umr_bitfield_default },
	 { "AFMT_UPC_EAN_ISRC25", 8, 15, &umr_bitfield_default },
	 { "AFMT_UPC_EAN_ISRC26", 16, 23, &umr_bitfield_default },
	 { "AFMT_UPC_EAN_ISRC27", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG1_AFMT_ISRC2_3[] = {
	 { "AFMT_UPC_EAN_ISRC28", 0, 7, &umr_bitfield_default },
	 { "AFMT_UPC_EAN_ISRC29", 8, 15, &umr_bitfield_default },
	 { "AFMT_UPC_EAN_ISRC30", 16, 23, &umr_bitfield_default },
	 { "AFMT_UPC_EAN_ISRC31", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG1_HDMI_GENERIC_PACKET_CONTROL2[] = {
	 { "HDMI_GENERIC4_SEND", 0, 0, &umr_bitfield_default },
	 { "HDMI_GENERIC4_CONT", 1, 1, &umr_bitfield_default },
	 { "HDMI_GENERIC5_SEND", 4, 4, &umr_bitfield_default },
	 { "HDMI_GENERIC5_CONT", 5, 5, &umr_bitfield_default },
	 { "HDMI_GENERIC4_LINE", 16, 21, &umr_bitfield_default },
	 { "HDMI_GENERIC5_LINE", 24, 29, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG1_HDMI_GENERIC_PACKET_CONTROL3[] = {
	 { "HDMI_GENERIC6_SEND", 0, 0, &umr_bitfield_default },
	 { "HDMI_GENERIC6_CONT", 1, 1, &umr_bitfield_default },
	 { "HDMI_GENERIC7_SEND", 4, 4, &umr_bitfield_default },
	 { "HDMI_GENERIC7_CONT", 5, 5, &umr_bitfield_default },
	 { "HDMI_GENERIC6_LINE", 16, 21, &umr_bitfield_default },
	 { "HDMI_GENERIC7_LINE", 24, 29, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG1_HDMI_DB_CONTROL[] = {
	 { "HDMI_DB_PENDING", 0, 0, &umr_bitfield_default },
	 { "HDMI_DB_TAKEN", 4, 4, &umr_bitfield_default },
	 { "HDMI_DB_TAKEN_CLR", 5, 5, &umr_bitfield_default },
	 { "HDMI_DB_LOCK", 8, 8, &umr_bitfield_default },
	 { "HDMI_DB_DISABLE", 12, 12, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG1_AFMT_MPEG_INFO0[] = {
	 { "AFMT_MPEG_INFO_CHECKSUM", 0, 7, &umr_bitfield_default },
	 { "AFMT_MPEG_INFO_MB0", 8, 15, &umr_bitfield_default },
	 { "AFMT_MPEG_INFO_MB1", 16, 23, &umr_bitfield_default },
	 { "AFMT_MPEG_INFO_MB2", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG1_AFMT_MPEG_INFO1[] = {
	 { "AFMT_MPEG_INFO_MB3", 0, 7, &umr_bitfield_default },
	 { "AFMT_MPEG_INFO_MF", 8, 9, &umr_bitfield_default },
	 { "AFMT_MPEG_INFO_FR", 12, 12, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG1_AFMT_GENERIC_HDR[] = {
	 { "AFMT_GENERIC_HB0", 0, 7, &umr_bitfield_default },
	 { "AFMT_GENERIC_HB1", 8, 15, &umr_bitfield_default },
	 { "AFMT_GENERIC_HB2", 16, 23, &umr_bitfield_default },
	 { "AFMT_GENERIC_HB3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG1_AFMT_GENERIC_0[] = {
	 { "AFMT_GENERIC_BYTE0", 0, 7, &umr_bitfield_default },
	 { "AFMT_GENERIC_BYTE1", 8, 15, &umr_bitfield_default },
	 { "AFMT_GENERIC_BYTE2", 16, 23, &umr_bitfield_default },
	 { "AFMT_GENERIC_BYTE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG1_AFMT_GENERIC_1[] = {
	 { "AFMT_GENERIC_BYTE4", 0, 7, &umr_bitfield_default },
	 { "AFMT_GENERIC_BYTE5", 8, 15, &umr_bitfield_default },
	 { "AFMT_GENERIC_BYTE6", 16, 23, &umr_bitfield_default },
	 { "AFMT_GENERIC_BYTE7", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG1_AFMT_GENERIC_2[] = {
	 { "AFMT_GENERIC_BYTE8", 0, 7, &umr_bitfield_default },
	 { "AFMT_GENERIC_BYTE9", 8, 15, &umr_bitfield_default },
	 { "AFMT_GENERIC_BYTE10", 16, 23, &umr_bitfield_default },
	 { "AFMT_GENERIC_BYTE11", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG1_AFMT_GENERIC_3[] = {
	 { "AFMT_GENERIC_BYTE12", 0, 7, &umr_bitfield_default },
	 { "AFMT_GENERIC_BYTE13", 8, 15, &umr_bitfield_default },
	 { "AFMT_GENERIC_BYTE14", 16, 23, &umr_bitfield_default },
	 { "AFMT_GENERIC_BYTE15", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG1_AFMT_GENERIC_4[] = {
	 { "AFMT_GENERIC_BYTE16", 0, 7, &umr_bitfield_default },
	 { "AFMT_GENERIC_BYTE17", 8, 15, &umr_bitfield_default },
	 { "AFMT_GENERIC_BYTE18", 16, 23, &umr_bitfield_default },
	 { "AFMT_GENERIC_BYTE19", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG1_AFMT_GENERIC_5[] = {
	 { "AFMT_GENERIC_BYTE20", 0, 7, &umr_bitfield_default },
	 { "AFMT_GENERIC_BYTE21", 8, 15, &umr_bitfield_default },
	 { "AFMT_GENERIC_BYTE22", 16, 23, &umr_bitfield_default },
	 { "AFMT_GENERIC_BYTE23", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG1_AFMT_GENERIC_6[] = {
	 { "AFMT_GENERIC_BYTE24", 0, 7, &umr_bitfield_default },
	 { "AFMT_GENERIC_BYTE25", 8, 15, &umr_bitfield_default },
	 { "AFMT_GENERIC_BYTE26", 16, 23, &umr_bitfield_default },
	 { "AFMT_GENERIC_BYTE27", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG1_AFMT_GENERIC_7[] = {
	 { "AFMT_GENERIC_BYTE28", 0, 7, &umr_bitfield_default },
	 { "AFMT_GENERIC_BYTE29", 8, 15, &umr_bitfield_default },
	 { "AFMT_GENERIC_BYTE30", 16, 23, &umr_bitfield_default },
	 { "AFMT_GENERIC_BYTE31", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG1_HDMI_GENERIC_PACKET_CONTROL1[] = {
	 { "HDMI_GENERIC2_SEND", 0, 0, &umr_bitfield_default },
	 { "HDMI_GENERIC2_CONT", 1, 1, &umr_bitfield_default },
	 { "HDMI_GENERIC3_SEND", 4, 4, &umr_bitfield_default },
	 { "HDMI_GENERIC3_CONT", 5, 5, &umr_bitfield_default },
	 { "HDMI_GENERIC2_LINE", 16, 21, &umr_bitfield_default },
	 { "HDMI_GENERIC3_LINE", 24, 29, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG1_HDMI_ACR_32_0[] = {
	 { "HDMI_ACR_CTS_32", 12, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG1_HDMI_ACR_32_1[] = {
	 { "HDMI_ACR_N_32", 0, 19, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG1_HDMI_ACR_44_0[] = {
	 { "HDMI_ACR_CTS_44", 12, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG1_HDMI_ACR_44_1[] = {
	 { "HDMI_ACR_N_44", 0, 19, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG1_HDMI_ACR_48_0[] = {
	 { "HDMI_ACR_CTS_48", 12, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG1_HDMI_ACR_48_1[] = {
	 { "HDMI_ACR_N_48", 0, 19, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG1_HDMI_ACR_STATUS_0[] = {
	 { "HDMI_ACR_CTS", 12, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG1_HDMI_ACR_STATUS_1[] = {
	 { "HDMI_ACR_N", 0, 19, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG1_AFMT_AUDIO_INFO0[] = {
	 { "AFMT_AUDIO_INFO_CHECKSUM", 0, 7, &umr_bitfield_default },
	 { "AFMT_AUDIO_INFO_CC", 8, 10, &umr_bitfield_default },
	 { "AFMT_AUDIO_INFO_CT", 11, 14, &umr_bitfield_default },
	 { "AFMT_AUDIO_INFO_CHECKSUM_OFFSET", 16, 23, &umr_bitfield_default },
	 { "AFMT_AUDIO_INFO_CXT", 24, 28, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG1_AFMT_AUDIO_INFO1[] = {
	 { "AFMT_AUDIO_INFO_CA", 0, 7, &umr_bitfield_default },
	 { "AFMT_AUDIO_INFO_LSV", 11, 14, &umr_bitfield_default },
	 { "AFMT_AUDIO_INFO_DM_INH", 15, 15, &umr_bitfield_default },
	 { "AFMT_AUDIO_INFO_LFEPBL", 16, 17, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG1_AFMT_60958_0[] = {
	 { "AFMT_60958_CS_A", 0, 0, &umr_bitfield_default },
	 { "AFMT_60958_CS_B", 1, 1, &umr_bitfield_default },
	 { "AFMT_60958_CS_C", 2, 2, &umr_bitfield_default },
	 { "AFMT_60958_CS_D", 3, 5, &umr_bitfield_default },
	 { "AFMT_60958_CS_MODE", 6, 7, &umr_bitfield_default },
	 { "AFMT_60958_CS_CATEGORY_CODE", 8, 15, &umr_bitfield_default },
	 { "AFMT_60958_CS_SOURCE_NUMBER", 16, 19, &umr_bitfield_default },
	 { "AFMT_60958_CS_CHANNEL_NUMBER_L", 20, 23, &umr_bitfield_default },
	 { "AFMT_60958_CS_SAMPLING_FREQUENCY", 24, 27, &umr_bitfield_default },
	 { "AFMT_60958_CS_CLOCK_ACCURACY", 28, 29, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG1_AFMT_60958_1[] = {
	 { "AFMT_60958_CS_WORD_LENGTH", 0, 3, &umr_bitfield_default },
	 { "AFMT_60958_CS_ORIGINAL_SAMPLING_FREQUENCY", 4, 7, &umr_bitfield_default },
	 { "AFMT_60958_VALID_L", 16, 16, &umr_bitfield_default },
	 { "AFMT_60958_VALID_R", 18, 18, &umr_bitfield_default },
	 { "AFMT_60958_CS_CHANNEL_NUMBER_R", 20, 23, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG1_AFMT_AUDIO_CRC_CONTROL[] = {
	 { "AFMT_AUDIO_CRC_EN", 0, 0, &umr_bitfield_default },
	 { "AFMT_AUDIO_CRC_CONT", 4, 4, &umr_bitfield_default },
	 { "AFMT_AUDIO_CRC_SOURCE", 8, 8, &umr_bitfield_default },
	 { "AFMT_AUDIO_CRC_CH_SEL", 12, 15, &umr_bitfield_default },
	 { "AFMT_AUDIO_CRC_COUNT", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG1_AFMT_RAMP_CONTROL0[] = {
	 { "AFMT_RAMP_MAX_COUNT", 0, 23, &umr_bitfield_default },
	 { "AFMT_RAMP_DATA_SIGN", 31, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG1_AFMT_RAMP_CONTROL1[] = {
	 { "AFMT_RAMP_MIN_COUNT", 0, 23, &umr_bitfield_default },
	 { "AFMT_AUDIO_TEST_CH_DISABLE", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG1_AFMT_RAMP_CONTROL2[] = {
	 { "AFMT_RAMP_INC_COUNT", 0, 23, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG1_AFMT_RAMP_CONTROL3[] = {
	 { "AFMT_RAMP_DEC_COUNT", 0, 23, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG1_AFMT_60958_2[] = {
	 { "AFMT_60958_CS_CHANNEL_NUMBER_2", 0, 3, &umr_bitfield_default },
	 { "AFMT_60958_CS_CHANNEL_NUMBER_3", 4, 7, &umr_bitfield_default },
	 { "AFMT_60958_CS_CHANNEL_NUMBER_4", 8, 11, &umr_bitfield_default },
	 { "AFMT_60958_CS_CHANNEL_NUMBER_5", 12, 15, &umr_bitfield_default },
	 { "AFMT_60958_CS_CHANNEL_NUMBER_6", 16, 19, &umr_bitfield_default },
	 { "AFMT_60958_CS_CHANNEL_NUMBER_7", 20, 23, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG1_AFMT_AUDIO_CRC_RESULT[] = {
	 { "AFMT_AUDIO_CRC_DONE", 0, 0, &umr_bitfield_default },
	 { "AFMT_AUDIO_CRC", 8, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG1_AFMT_STATUS[] = {
	 { "AFMT_AUDIO_ENABLE", 4, 4, &umr_bitfield_default },
	 { "AFMT_AZ_HBR_ENABLE", 8, 8, &umr_bitfield_default },
	 { "AFMT_AUDIO_FIFO_OVERFLOW", 24, 24, &umr_bitfield_default },
	 { "AFMT_AZ_AUDIO_ENABLE_CHG", 30, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG1_AFMT_AUDIO_PACKET_CONTROL[] = {
	 { "AFMT_AUDIO_SAMPLE_SEND", 0, 0, &umr_bitfield_default },
	 { "AFMT_RESET_FIFO_WHEN_AUDIO_DIS", 11, 11, &umr_bitfield_default },
	 { "AFMT_AUDIO_TEST_EN", 12, 12, &umr_bitfield_default },
	 { "AFMT_AUDIO_TEST_MODE", 14, 14, &umr_bitfield_default },
	 { "AFMT_AUDIO_FIFO_OVERFLOW_ACK", 23, 23, &umr_bitfield_default },
	 { "AFMT_AUDIO_CHANNEL_SWAP", 24, 24, &umr_bitfield_default },
	 { "AFMT_60958_CS_UPDATE", 26, 26, &umr_bitfield_default },
	 { "AFMT_AZ_AUDIO_ENABLE_CHG_ACK", 30, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG1_AFMT_VBI_PACKET_CONTROL[] = {
	 { "AFMT_GENERIC_LOCK_STATUS", 8, 8, &umr_bitfield_default },
	 { "AFMT_GENERIC_CONFLICT", 16, 16, &umr_bitfield_default },
	 { "AFMT_GENERIC_CONFLICT_CLR", 17, 17, &umr_bitfield_default },
	 { "AFMT_GENERIC_INDEX", 28, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG1_AFMT_INFOFRAME_CONTROL0[] = {
	 { "AFMT_AUDIO_INFO_SOURCE", 6, 6, &umr_bitfield_default },
	 { "AFMT_AUDIO_INFO_UPDATE", 7, 7, &umr_bitfield_default },
	 { "AFMT_MPEG_INFO_UPDATE", 10, 10, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG1_AFMT_AUDIO_SRC_CONTROL[] = {
	 { "AFMT_AUDIO_SRC_SELECT", 0, 2, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG1_DIG_BE_CNTL[] = {
	 { "DIG_DUAL_LINK_ENABLE", 0, 0, &umr_bitfield_default },
	 { "DIG_SWAP", 1, 1, &umr_bitfield_default },
	 { "DIG_FE_SOURCE_SELECT", 8, 14, &umr_bitfield_default },
	 { "DIG_MODE", 16, 18, &umr_bitfield_default },
	 { "DIG_HPD_SELECT", 28, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG1_DIG_BE_EN_CNTL[] = {
	 { "DIG_ENABLE", 0, 0, &umr_bitfield_default },
	 { "DIG_SYMCLK_BE_ON", 8, 8, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG1_TMDS_CNTL[] = {
	 { "TMDS_SYNC_PHASE", 0, 0, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG1_TMDS_CONTROL_CHAR[] = {
	 { "TMDS_CONTROL_CHAR0_OUT_EN", 0, 0, &umr_bitfield_default },
	 { "TMDS_CONTROL_CHAR1_OUT_EN", 1, 1, &umr_bitfield_default },
	 { "TMDS_CONTROL_CHAR2_OUT_EN", 2, 2, &umr_bitfield_default },
	 { "TMDS_CONTROL_CHAR3_OUT_EN", 3, 3, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG1_TMDS_CONTROL0_FEEDBACK[] = {
	 { "TMDS_CONTROL0_FEEDBACK_SELECT", 0, 1, &umr_bitfield_default },
	 { "TMDS_CONTROL0_FEEDBACK_DELAY", 8, 9, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG1_TMDS_STEREOSYNC_CTL_SEL[] = {
	 { "TMDS_STEREOSYNC_CTL_SEL", 0, 1, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG1_TMDS_SYNC_CHAR_PATTERN_0_1[] = {
	 { "TMDS_SYNC_CHAR_PATTERN0", 0, 9, &umr_bitfield_default },
	 { "TMDS_SYNC_CHAR_PATTERN1", 16, 25, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG1_TMDS_SYNC_CHAR_PATTERN_2_3[] = {
	 { "TMDS_SYNC_CHAR_PATTERN2", 0, 9, &umr_bitfield_default },
	 { "TMDS_SYNC_CHAR_PATTERN3", 16, 25, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG1_TMDS_CTL_BITS[] = {
	 { "TMDS_CTL0", 0, 0, &umr_bitfield_default },
	 { "TMDS_CTL1", 8, 8, &umr_bitfield_default },
	 { "TMDS_CTL2", 16, 16, &umr_bitfield_default },
	 { "TMDS_CTL3", 24, 24, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG1_TMDS_DCBALANCER_CONTROL[] = {
	 { "TMDS_DCBALANCER_EN", 0, 0, &umr_bitfield_default },
	 { "TMDS_DCBALANCER_TEST_EN", 8, 8, &umr_bitfield_default },
	 { "TMDS_DCBALANCER_TEST_IN", 16, 19, &umr_bitfield_default },
	 { "TMDS_DCBALANCER_FORCE", 24, 24, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG1_TMDS_CTL0_1_GEN_CNTL[] = {
	 { "TMDS_CTL0_DATA_SEL", 0, 3, &umr_bitfield_default },
	 { "TMDS_CTL0_DATA_DELAY", 4, 6, &umr_bitfield_default },
	 { "TMDS_CTL0_DATA_INVERT", 7, 7, &umr_bitfield_default },
	 { "TMDS_CTL0_DATA_MODULATION", 8, 9, &umr_bitfield_default },
	 { "TMDS_CTL0_USE_FEEDBACK_PATH", 10, 10, &umr_bitfield_default },
	 { "TMDS_CTL0_FB_SYNC_CONT", 11, 11, &umr_bitfield_default },
	 { "TMDS_CTL0_PATTERN_OUT_EN", 12, 12, &umr_bitfield_default },
	 { "TMDS_CTL1_DATA_SEL", 16, 19, &umr_bitfield_default },
	 { "TMDS_CTL1_DATA_DELAY", 20, 22, &umr_bitfield_default },
	 { "TMDS_CTL1_DATA_INVERT", 23, 23, &umr_bitfield_default },
	 { "TMDS_CTL1_DATA_MODULATION", 24, 25, &umr_bitfield_default },
	 { "TMDS_CTL1_USE_FEEDBACK_PATH", 26, 26, &umr_bitfield_default },
	 { "TMDS_CTL1_FB_SYNC_CONT", 27, 27, &umr_bitfield_default },
	 { "TMDS_CTL1_PATTERN_OUT_EN", 28, 28, &umr_bitfield_default },
	 { "TMDS_2BIT_COUNTER_EN", 31, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG1_TMDS_CTL2_3_GEN_CNTL[] = {
	 { "TMDS_CTL2_DATA_SEL", 0, 3, &umr_bitfield_default },
	 { "TMDS_CTL2_DATA_DELAY", 4, 6, &umr_bitfield_default },
	 { "TMDS_CTL2_DATA_INVERT", 7, 7, &umr_bitfield_default },
	 { "TMDS_CTL2_DATA_MODULATION", 8, 9, &umr_bitfield_default },
	 { "TMDS_CTL2_USE_FEEDBACK_PATH", 10, 10, &umr_bitfield_default },
	 { "TMDS_CTL2_FB_SYNC_CONT", 11, 11, &umr_bitfield_default },
	 { "TMDS_CTL2_PATTERN_OUT_EN", 12, 12, &umr_bitfield_default },
	 { "TMDS_CTL3_DATA_SEL", 16, 19, &umr_bitfield_default },
	 { "TMDS_CTL3_DATA_DELAY", 20, 22, &umr_bitfield_default },
	 { "TMDS_CTL3_DATA_INVERT", 23, 23, &umr_bitfield_default },
	 { "TMDS_CTL3_DATA_MODULATION", 24, 25, &umr_bitfield_default },
	 { "TMDS_CTL3_USE_FEEDBACK_PATH", 26, 26, &umr_bitfield_default },
	 { "TMDS_CTL3_FB_SYNC_CONT", 27, 27, &umr_bitfield_default },
	 { "TMDS_CTL3_PATTERN_OUT_EN", 28, 28, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG1_DIG_VERSION[] = {
	 { "DIG_TYPE", 0, 0, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG1_DIG_LANE_ENABLE[] = {
	 { "DIG_LANE0EN", 0, 0, &umr_bitfield_default },
	 { "DIG_LANE1EN", 1, 1, &umr_bitfield_default },
	 { "DIG_LANE2EN", 2, 2, &umr_bitfield_default },
	 { "DIG_LANE3EN", 3, 3, &umr_bitfield_default },
	 { "DIG_CLK_EN", 8, 8, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG1_AFMT_CNTL[] = {
	 { "AFMT_AUDIO_CLOCK_EN", 0, 0, &umr_bitfield_default },
	 { "AFMT_AUDIO_CLOCK_ON", 8, 8, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG1_AFMT_VBI_PACKET_CONTROL1[] = {
	 { "AFMT_GENERIC0_FRAME_UPDATE", 0, 0, &umr_bitfield_default },
	 { "AFMT_GENERIC0_FRAME_UPDATE_PENDING", 1, 1, &umr_bitfield_default },
	 { "AFMT_GENERIC0_IMMEDIATE_UPDATE", 2, 2, &umr_bitfield_default },
	 { "AFMT_GENERIC0_IMMEDIATE_UPDATE_PENDING", 3, 3, &umr_bitfield_default },
	 { "AFMT_GENERIC1_FRAME_UPDATE", 4, 4, &umr_bitfield_default },
	 { "AFMT_GENERIC1_FRAME_UPDATE_PENDING", 5, 5, &umr_bitfield_default },
	 { "AFMT_GENERIC1_IMMEDIATE_UPDATE", 6, 6, &umr_bitfield_default },
	 { "AFMT_GENERIC1_IMMEDIATE_UPDATE_PENDING", 7, 7, &umr_bitfield_default },
	 { "AFMT_GENERIC2_FRAME_UPDATE", 8, 8, &umr_bitfield_default },
	 { "AFMT_GENERIC2_FRAME_UPDATE_PENDING", 9, 9, &umr_bitfield_default },
	 { "AFMT_GENERIC2_IMMEDIATE_UPDATE", 10, 10, &umr_bitfield_default },
	 { "AFMT_GENERIC2_IMMEDIATE_UPDATE_PENDING", 11, 11, &umr_bitfield_default },
	 { "AFMT_GENERIC3_FRAME_UPDATE", 12, 12, &umr_bitfield_default },
	 { "AFMT_GENERIC3_FRAME_UPDATE_PENDING", 13, 13, &umr_bitfield_default },
	 { "AFMT_GENERIC3_IMMEDIATE_UPDATE", 14, 14, &umr_bitfield_default },
	 { "AFMT_GENERIC3_IMMEDIATE_UPDATE_PENDING", 15, 15, &umr_bitfield_default },
	 { "AFMT_GENERIC4_FRAME_UPDATE", 16, 16, &umr_bitfield_default },
	 { "AFMT_GENERIC4_FRAME_UPDATE_PENDING", 17, 17, &umr_bitfield_default },
	 { "AFMT_GENERIC4_IMMEDIATE_UPDATE", 18, 18, &umr_bitfield_default },
	 { "AFMT_GENERIC4_IMMEDIATE_UPDATE_PENDING", 19, 19, &umr_bitfield_default },
	 { "AFMT_GENERIC5_FRAME_UPDATE", 20, 20, &umr_bitfield_default },
	 { "AFMT_GENERIC5_FRAME_UPDATE_PENDING", 21, 21, &umr_bitfield_default },
	 { "AFMT_GENERIC5_IMMEDIATE_UPDATE", 22, 22, &umr_bitfield_default },
	 { "AFMT_GENERIC5_IMMEDIATE_UPDATE_PENDING", 23, 23, &umr_bitfield_default },
	 { "AFMT_GENERIC6_FRAME_UPDATE", 24, 24, &umr_bitfield_default },
	 { "AFMT_GENERIC6_FRAME_UPDATE_PENDING", 25, 25, &umr_bitfield_default },
	 { "AFMT_GENERIC6_IMMEDIATE_UPDATE", 26, 26, &umr_bitfield_default },
	 { "AFMT_GENERIC6_IMMEDIATE_UPDATE_PENDING", 27, 27, &umr_bitfield_default },
	 { "AFMT_GENERIC7_FRAME_UPDATE", 28, 28, &umr_bitfield_default },
	 { "AFMT_GENERIC7_FRAME_UPDATE_PENDING", 29, 29, &umr_bitfield_default },
	 { "AFMT_GENERIC7_IMMEDIATE_UPDATE", 30, 30, &umr_bitfield_default },
	 { "AFMT_GENERIC7_IMMEDIATE_UPDATE_PENDING", 31, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDP1_DP_LINK_CNTL[] = {
	 { "DP_LINK_TRAINING_COMPLETE", 4, 4, &umr_bitfield_default },
	 { "DP_LINK_STATUS", 8, 8, &umr_bitfield_default },
	 { "DP_EMBEDDED_PANEL_MODE", 17, 17, &umr_bitfield_default },
};
static struct umr_bitfield mmDP1_DP_PIXEL_FORMAT[] = {
	 { "DP_PIXEL_ENCODING", 0, 2, &umr_bitfield_default },
	 { "DP_COMPONENT_DEPTH", 24, 26, &umr_bitfield_default },
	 { "DP_PIXEL_COMBINE", 28, 29, &umr_bitfield_default },
};
static struct umr_bitfield mmDP1_DP_MSA_COLORIMETRY[] = {
	 { "DP_MSA_MISC0", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDP1_DP_CONFIG[] = {
	 { "DP_UDI_LANES", 0, 1, &umr_bitfield_default },
};
static struct umr_bitfield mmDP1_DP_VID_STREAM_CNTL[] = {
	 { "DP_VID_STREAM_ENABLE", 0, 0, &umr_bitfield_default },
	 { "DP_VID_STREAM_DIS_DEFER", 8, 9, &umr_bitfield_default },
	 { "DP_VID_STREAM_STATUS", 16, 16, &umr_bitfield_default },
	 { "DP_VID_STREAM_CHANGE_KEEPOUT", 20, 20, &umr_bitfield_default },
};
static struct umr_bitfield mmDP1_DP_STEER_FIFO[] = {
	 { "DP_STEER_FIFO_RESET", 0, 0, &umr_bitfield_default },
	 { "DP_STEER_OVERFLOW_FLAG", 4, 4, &umr_bitfield_default },
	 { "DP_STEER_OVERFLOW_INT", 5, 5, &umr_bitfield_default },
	 { "DP_STEER_OVERFLOW_ACK", 6, 6, &umr_bitfield_default },
	 { "DP_STEER_OVERFLOW_MASK", 7, 7, &umr_bitfield_default },
	 { "DP_TU_OVERFLOW_FLAG", 8, 8, &umr_bitfield_default },
	 { "DP_TU_OVERFLOW_ACK", 12, 12, &umr_bitfield_default },
};
static struct umr_bitfield mmDP1_DP_MSA_MISC[] = {
	 { "DP_MSA_MISC1", 0, 7, &umr_bitfield_default },
	 { "DP_MSA_MISC2", 8, 15, &umr_bitfield_default },
	 { "DP_MSA_MISC3", 16, 23, &umr_bitfield_default },
	 { "DP_MSA_MISC4", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDP1_DP_VID_TIMING[] = {
	 { "DP_VID_M_N_DOUBLE_BUFFER_MODE", 4, 4, &umr_bitfield_default },
	 { "DP_VID_M_N_GEN_EN", 8, 8, &umr_bitfield_default },
	 { "DP_VID_N_MUL", 10, 11, &umr_bitfield_default },
	 { "DP_VID_M_DIV", 12, 13, &umr_bitfield_default },
	 { "DP_VID_N_DIV", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDP1_DP_VID_N[] = {
	 { "DP_VID_N", 0, 23, &umr_bitfield_default },
};
static struct umr_bitfield mmDP1_DP_VID_M[] = {
	 { "DP_VID_M", 0, 23, &umr_bitfield_default },
};
static struct umr_bitfield mmDP1_DP_LINK_FRAMING_CNTL[] = {
	 { "DP_IDLE_BS_INTERVAL", 0, 17, &umr_bitfield_default },
	 { "DP_VBID_DISABLE", 24, 24, &umr_bitfield_default },
	 { "DP_VID_ENHANCED_FRAME_MODE", 28, 28, &umr_bitfield_default },
};
static struct umr_bitfield mmDP1_DP_HBR2_EYE_PATTERN[] = {
	 { "DP_HBR2_EYE_PATTERN_ENABLE", 0, 0, &umr_bitfield_default },
};
static struct umr_bitfield mmDP1_DP_VID_MSA_VBID[] = {
	 { "DP_VID_MSA_LOCATION", 0, 11, &umr_bitfield_default },
	 { "DP_VID_VBID_FIELD_POL", 24, 24, &umr_bitfield_default },
};
static struct umr_bitfield mmDP1_DP_VID_INTERRUPT_CNTL[] = {
	 { "DP_VID_STREAM_DISABLE_INT", 0, 0, &umr_bitfield_default },
	 { "DP_VID_STREAM_DISABLE_ACK", 1, 1, &umr_bitfield_default },
	 { "DP_VID_STREAM_DISABLE_MASK", 2, 2, &umr_bitfield_default },
};
static struct umr_bitfield mmDP1_DP_DPHY_CNTL[] = {
	 { "DPHY_ATEST_SEL_LANE0", 0, 0, &umr_bitfield_default },
	 { "DPHY_ATEST_SEL_LANE1", 1, 1, &umr_bitfield_default },
	 { "DPHY_ATEST_SEL_LANE2", 2, 2, &umr_bitfield_default },
	 { "DPHY_ATEST_SEL_LANE3", 3, 3, &umr_bitfield_default },
	 { "DPHY_BYPASS", 16, 16, &umr_bitfield_default },
	 { "DPHY_SKEW_BYPASS", 24, 24, &umr_bitfield_default },
};
static struct umr_bitfield mmDP1_DP_DPHY_TRAINING_PATTERN_SEL[] = {
	 { "DPHY_TRAINING_PATTERN_SEL", 0, 1, &umr_bitfield_default },
};
static struct umr_bitfield mmDP1_DP_DPHY_SYM0[] = {
	 { "DPHY_SYM1", 0, 9, &umr_bitfield_default },
	 { "DPHY_SYM2", 10, 19, &umr_bitfield_default },
	 { "DPHY_SYM3", 20, 29, &umr_bitfield_default },
};
static struct umr_bitfield mmDP1_DP_DPHY_SYM1[] = {
	 { "DPHY_SYM4", 0, 9, &umr_bitfield_default },
	 { "DPHY_SYM5", 10, 19, &umr_bitfield_default },
	 { "DPHY_SYM6", 20, 29, &umr_bitfield_default },
};
static struct umr_bitfield mmDP1_DP_DPHY_SYM2[] = {
	 { "DPHY_SYM7", 0, 9, &umr_bitfield_default },
	 { "DPHY_SYM8", 10, 19, &umr_bitfield_default },
};
static struct umr_bitfield mmDP1_DP_DPHY_8B10B_CNTL[] = {
	 { "DPHY_8B10B_RESET", 8, 8, &umr_bitfield_default },
	 { "DPHY_8B10B_EXT_DISP", 16, 16, &umr_bitfield_default },
	 { "DPHY_8B10B_CUR_DISP", 24, 24, &umr_bitfield_default },
};
static struct umr_bitfield mmDP1_DP_DPHY_PRBS_CNTL[] = {
	 { "DPHY_PRBS_EN", 0, 0, &umr_bitfield_default },
	 { "DPHY_PRBS_SEL", 4, 5, &umr_bitfield_default },
	 { "DPHY_PRBS_SEED", 8, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmDP1_DP_DPHY_SCRAM_CNTL[] = {
	 { "DPHY_SCRAMBLER_DIS", 0, 0, &umr_bitfield_default },
	 { "DPHY_SCRAMBLER_ADVANCE", 4, 4, &umr_bitfield_default },
	 { "DPHY_SCRAMBLER_BS_COUNT", 8, 17, &umr_bitfield_default },
	 { "DPHY_SCRAMBLER_KCODE", 24, 24, &umr_bitfield_default },
};
static struct umr_bitfield mmDP1_DP_DPHY_CRC_EN[] = {
	 { "DPHY_CRC_EN", 0, 0, &umr_bitfield_default },
	 { "DPHY_CRC_CONT_EN", 4, 4, &umr_bitfield_default },
	 { "DPHY_CRC_RESULT_VALID", 8, 8, &umr_bitfield_default },
};
static struct umr_bitfield mmDP1_DP_DPHY_CRC_CNTL[] = {
	 { "DPHY_CRC_FIELD", 0, 0, &umr_bitfield_default },
	 { "DPHY_CRC_SEL", 4, 5, &umr_bitfield_default },
	 { "DPHY_CRC_MASK", 16, 23, &umr_bitfield_default },
};
static struct umr_bitfield mmDP1_DP_DPHY_CRC_RESULT[] = {
	 { "DPHY_CRC_RESULT", 0, 7, &umr_bitfield_default },
	 { "DPHY_CRC_RESULT1", 8, 15, &umr_bitfield_default },
	 { "DPHY_CRC_RESULT2", 16, 23, &umr_bitfield_default },
	 { "DPHY_CRC_RESULT3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDP1_DP_DPHY_CRC_MST_CNTL[] = {
	 { "DPHY_CRC_MST_FIRST_SLOT", 0, 5, &umr_bitfield_default },
	 { "DPHY_CRC_MST_LAST_SLOT", 8, 13, &umr_bitfield_default },
};
static struct umr_bitfield mmDP1_DP_DPHY_CRC_MST_STATUS[] = {
	 { "DPHY_CRC_MST_PHASE_LOCK", 0, 0, &umr_bitfield_default },
	 { "DPHY_CRC_MST_PHASE_ERROR", 8, 8, &umr_bitfield_default },
	 { "DPHY_CRC_MST_PHASE_ERROR_ACK", 16, 16, &umr_bitfield_default },
};
static struct umr_bitfield mmDP1_DP_DPHY_FAST_TRAINING[] = {
	 { "DPHY_RX_FAST_TRAINING_CAPABLE", 0, 0, &umr_bitfield_default },
	 { "DPHY_SW_FAST_TRAINING_START", 1, 1, &umr_bitfield_default },
	 { "DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN", 2, 2, &umr_bitfield_default },
	 { "DPHY_FAST_TRAINING_TP1_TIME", 8, 19, &umr_bitfield_default },
	 { "DPHY_FAST_TRAINING_TP2_TIME", 20, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDP1_DP_DPHY_FAST_TRAINING_STATUS[] = {
	 { "DPHY_FAST_TRAINING_STATE", 0, 2, &umr_bitfield_default },
	 { "DPHY_FAST_TRAINING_COMPLETE_OCCURRED", 4, 4, &umr_bitfield_default },
	 { "DPHY_FAST_TRAINING_COMPLETE_MASK", 8, 8, &umr_bitfield_default },
	 { "DPHY_FAST_TRAINING_COMPLETE_ACK", 12, 12, &umr_bitfield_default },
};
static struct umr_bitfield mmDP1_DP_SEC_CNTL[] = {
	 { "DP_SEC_STREAM_ENABLE", 0, 0, &umr_bitfield_default },
	 { "DP_SEC_ASP_ENABLE", 4, 4, &umr_bitfield_default },
	 { "DP_SEC_ATP_ENABLE", 8, 8, &umr_bitfield_default },
	 { "DP_SEC_AIP_ENABLE", 12, 12, &umr_bitfield_default },
	 { "DP_SEC_ACM_ENABLE", 16, 16, &umr_bitfield_default },
	 { "DP_SEC_GSP0_ENABLE", 20, 20, &umr_bitfield_default },
	 { "DP_SEC_GSP1_ENABLE", 21, 21, &umr_bitfield_default },
	 { "DP_SEC_GSP2_ENABLE", 22, 22, &umr_bitfield_default },
	 { "DP_SEC_GSP3_ENABLE", 23, 23, &umr_bitfield_default },
	 { "DP_SEC_GSP4_ENABLE", 24, 24, &umr_bitfield_default },
	 { "DP_SEC_GSP5_ENABLE", 25, 25, &umr_bitfield_default },
	 { "DP_SEC_GSP6_ENABLE", 26, 26, &umr_bitfield_default },
	 { "DP_SEC_GSP7_ENABLE", 27, 27, &umr_bitfield_default },
	 { "DP_SEC_MPG_ENABLE", 28, 28, &umr_bitfield_default },
};
static struct umr_bitfield mmDP1_DP_SEC_CNTL1[] = {
	 { "DP_SEC_ISRC_ENABLE", 0, 0, &umr_bitfield_default },
	 { "DP_SEC_GSP0_PRIORITY", 4, 4, &umr_bitfield_default },
	 { "DP_SEC_GSP0_SEND", 5, 5, &umr_bitfield_default },
	 { "DP_SEC_GSP0_SEND_PENDING", 6, 6, &umr_bitfield_default },
	 { "DP_SEC_GSP0_SEND_DEADLINE_MISSED", 7, 7, &umr_bitfield_default },
	 { "DP_SEC_GSP0_SEND_ANY_LINE", 8, 8, &umr_bitfield_default },
	 { "DP_SEC_GSP0_LINE_NUM", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDP1_DP_SEC_FRAMING1[] = {
	 { "DP_SEC_FRAME_START_LOCATION", 0, 11, &umr_bitfield_default },
	 { "DP_SEC_VBLANK_TRANSMIT_WIDTH", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDP1_DP_SEC_FRAMING2[] = {
	 { "DP_SEC_START_POSITION", 0, 15, &umr_bitfield_default },
	 { "DP_SEC_HBLANK_TRANSMIT_WIDTH", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDP1_DP_SEC_FRAMING3[] = {
	 { "DP_SEC_IDLE_FRAME_SIZE", 0, 13, &umr_bitfield_default },
	 { "DP_SEC_IDLE_TRANSMIT_WIDTH", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDP1_DP_SEC_FRAMING4[] = {
	 { "DP_SEC_COLLISION_STATUS", 20, 20, &umr_bitfield_default },
	 { "DP_SEC_COLLISION_ACK", 24, 24, &umr_bitfield_default },
	 { "DP_SEC_AUDIO_MUTE", 28, 28, &umr_bitfield_default },
	 { "DP_SEC_AUDIO_MUTE_STATUS", 29, 29, &umr_bitfield_default },
};
static struct umr_bitfield mmDP1_DP_SEC_AUD_N[] = {
	 { "DP_SEC_AUD_N", 0, 23, &umr_bitfield_default },
};
static struct umr_bitfield mmDP1_DP_SEC_AUD_N_READBACK[] = {
	 { "DP_SEC_AUD_N_READBACK", 0, 23, &umr_bitfield_default },
};
static struct umr_bitfield mmDP1_DP_SEC_AUD_M[] = {
	 { "DP_SEC_AUD_M", 0, 23, &umr_bitfield_default },
};
static struct umr_bitfield mmDP1_DP_SEC_AUD_M_READBACK[] = {
	 { "DP_SEC_AUD_M_READBACK", 0, 23, &umr_bitfield_default },
};
static struct umr_bitfield mmDP1_DP_SEC_TIMESTAMP[] = {
	 { "DP_SEC_TIMESTAMP_MODE", 0, 0, &umr_bitfield_default },
};
static struct umr_bitfield mmDP1_DP_SEC_PACKET_CNTL[] = {
	 { "DP_SEC_ASP_CODING_TYPE", 1, 3, &umr_bitfield_default },
	 { "DP_SEC_ASP_PRIORITY", 4, 4, &umr_bitfield_default },
	 { "DP_SEC_VERSION", 8, 13, &umr_bitfield_default },
	 { "DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE", 16, 16, &umr_bitfield_default },
};
static struct umr_bitfield mmDP1_DP_MSE_RATE_CNTL[] = {
	 { "DP_MSE_RATE_Y", 0, 25, &umr_bitfield_default },
	 { "DP_MSE_RATE_X", 26, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDP1_DP_MSE_RATE_UPDATE[] = {
	 { "DP_MSE_RATE_UPDATE_PENDING", 0, 0, &umr_bitfield_default },
};
static struct umr_bitfield mmDP1_DP_MSE_SAT0[] = {
	 { "DP_MSE_SAT_SRC0", 0, 2, &umr_bitfield_default },
	 { "DP_MSE_SAT_SLOT_COUNT0", 8, 13, &umr_bitfield_default },
	 { "DP_MSE_SAT_SRC1", 16, 18, &umr_bitfield_default },
	 { "DP_MSE_SAT_SLOT_COUNT1", 24, 29, &umr_bitfield_default },
};
static struct umr_bitfield mmDP1_DP_MSE_SAT1[] = {
	 { "DP_MSE_SAT_SRC2", 0, 2, &umr_bitfield_default },
	 { "DP_MSE_SAT_SLOT_COUNT2", 8, 13, &umr_bitfield_default },
	 { "DP_MSE_SAT_SRC3", 16, 18, &umr_bitfield_default },
	 { "DP_MSE_SAT_SLOT_COUNT3", 24, 29, &umr_bitfield_default },
};
static struct umr_bitfield mmDP1_DP_MSE_SAT2[] = {
	 { "DP_MSE_SAT_SRC4", 0, 2, &umr_bitfield_default },
	 { "DP_MSE_SAT_SLOT_COUNT4", 8, 13, &umr_bitfield_default },
	 { "DP_MSE_SAT_SRC5", 16, 18, &umr_bitfield_default },
	 { "DP_MSE_SAT_SLOT_COUNT5", 24, 29, &umr_bitfield_default },
};
static struct umr_bitfield mmDP1_DP_MSE_SAT_UPDATE[] = {
	 { "DP_MSE_SAT_UPDATE", 0, 1, &umr_bitfield_default },
	 { "DP_MSE_16_MTP_KEEPOUT", 8, 8, &umr_bitfield_default },
};
static struct umr_bitfield mmDP1_DP_MSE_LINK_TIMING[] = {
	 { "DP_MSE_LINK_FRAME", 0, 9, &umr_bitfield_default },
	 { "DP_MSE_LINK_LINE", 16, 17, &umr_bitfield_default },
};
static struct umr_bitfield mmDP1_DP_MSE_MISC_CNTL[] = {
	 { "DP_MSE_BLANK_CODE", 0, 0, &umr_bitfield_default },
	 { "DP_MSE_TIMESTAMP_MODE", 4, 4, &umr_bitfield_default },
	 { "DP_MSE_ZERO_ENCODER", 8, 8, &umr_bitfield_default },
};
static struct umr_bitfield mmDP1_DP_DPHY_BS_SR_SWAP_CNTL[] = {
	 { "DPHY_LOAD_BS_COUNT", 0, 9, &umr_bitfield_default },
	 { "DPHY_BS_SR_SWAP_DONE", 15, 15, &umr_bitfield_default },
	 { "DPHY_LOAD_BS_COUNT_START", 16, 16, &umr_bitfield_default },
};
static struct umr_bitfield mmDP1_DP_DPHY_HBR2_PATTERN_CONTROL[] = {
	 { "DP_DPHY_HBR2_PATTERN_CONTROL", 0, 2, &umr_bitfield_default },
};
static struct umr_bitfield mmDP1_DP_MSE_SAT0_STATUS[] = {
	 { "DP_MSE_SAT_SRC0_STATUS", 0, 2, &umr_bitfield_default },
	 { "DP_MSE_SAT_SLOT_COUNT0_STATUS", 8, 13, &umr_bitfield_default },
	 { "DP_MSE_SAT_SRC1_STATUS", 16, 18, &umr_bitfield_default },
	 { "DP_MSE_SAT_SLOT_COUNT1_STATUS", 24, 29, &umr_bitfield_default },
};
static struct umr_bitfield mmDP1_DP_MSE_SAT1_STATUS[] = {
	 { "DP_MSE_SAT_SRC2_STATUS", 0, 2, &umr_bitfield_default },
	 { "DP_MSE_SAT_SLOT_COUNT2_STATUS", 8, 13, &umr_bitfield_default },
	 { "DP_MSE_SAT_SRC3_STATUS", 16, 18, &umr_bitfield_default },
	 { "DP_MSE_SAT_SLOT_COUNT3_STATUS", 24, 29, &umr_bitfield_default },
};
static struct umr_bitfield mmDP1_DP_MSE_SAT2_STATUS[] = {
	 { "DP_MSE_SAT_SRC4_STATUS", 0, 2, &umr_bitfield_default },
	 { "DP_MSE_SAT_SLOT_COUNT4_STATUS", 8, 13, &umr_bitfield_default },
	 { "DP_MSE_SAT_SRC5_STATUS", 16, 18, &umr_bitfield_default },
	 { "DP_MSE_SAT_SLOT_COUNT5_STATUS", 24, 29, &umr_bitfield_default },
};
static struct umr_bitfield mmDP1_DP_MSA_TIMING_PARAM1[] = {
	 { "DP_MSA_VTOTAL", 0, 15, &umr_bitfield_default },
	 { "DP_MSA_HTOTAL", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDP1_DP_MSA_TIMING_PARAM2[] = {
	 { "DP_MSA_VSTART", 0, 15, &umr_bitfield_default },
	 { "DP_MSA_HSTART", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDP1_DP_MSA_TIMING_PARAM3[] = {
	 { "DP_MSA_VSYNCWIDTH", 0, 14, &umr_bitfield_default },
	 { "DP_MSA_VSYNCPOLARITY", 15, 15, &umr_bitfield_default },
	 { "DP_MSA_HSYNCWIDTH", 16, 30, &umr_bitfield_default },
	 { "DP_MSA_HSYNCPOLARITY", 31, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDP1_DP_MSA_TIMING_PARAM4[] = {
	 { "DP_MSA_VHEIGHT", 0, 15, &umr_bitfield_default },
	 { "DP_MSA_HWIDTH", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDP1_DP_MSO_CNTL[] = {
	 { "DP_MSO_NUM_OF_SSTLINK", 0, 1, &umr_bitfield_default },
	 { "DP_MSO_SEC_STREAM_ENABLE", 4, 7, &umr_bitfield_default },
	 { "DP_MSO_SEC_ASP_ENABLE", 8, 11, &umr_bitfield_default },
	 { "DP_MSO_SEC_ATP_ENABLE", 12, 15, &umr_bitfield_default },
	 { "DP_MSO_SEC_AIP_ENABLE", 16, 19, &umr_bitfield_default },
	 { "DP_MSO_SEC_ACM_ENABLE", 20, 23, &umr_bitfield_default },
	 { "DP_MSO_SEC_GSP0_ENABLE", 24, 27, &umr_bitfield_default },
	 { "DP_MSO_SEC_GSP1_ENABLE", 28, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDP1_DP_MSO_CNTL1[] = {
	 { "DP_MSO_SEC_GSP2_ENABLE", 0, 3, &umr_bitfield_default },
	 { "DP_MSO_SEC_GSP3_ENABLE", 4, 7, &umr_bitfield_default },
	 { "DP_MSO_SEC_GSP4_ENABLE", 8, 11, &umr_bitfield_default },
	 { "DP_MSO_SEC_GSP5_ENABLE", 12, 15, &umr_bitfield_default },
	 { "DP_MSO_SEC_GSP6_ENABLE", 16, 19, &umr_bitfield_default },
	 { "DP_MSO_SEC_GSP7_ENABLE", 20, 23, &umr_bitfield_default },
	 { "DP_MSO_SEC_MPG_ENABLE", 24, 27, &umr_bitfield_default },
	 { "DP_MSO_SEC_ISRC_ENABLE", 28, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDP1_DP_DSC_CNTL[] = {
	 { "DP_DSC_EN", 0, 0, &umr_bitfield_default },
};
static struct umr_bitfield mmDP1_DP_SEC_CNTL2[] = {
	 { "DP_SEC_GSP1_SEND", 0, 0, &umr_bitfield_default },
	 { "DP_SEC_GSP1_SEND_PENDING", 1, 1, &umr_bitfield_default },
	 { "DP_SEC_GSP1_SEND_DEADLINE_MISSED", 2, 2, &umr_bitfield_default },
	 { "DP_SEC_GSP1_SEND_ANY_LINE", 3, 3, &umr_bitfield_default },
	 { "DP_SEC_GSP2_SEND", 4, 4, &umr_bitfield_default },
	 { "DP_SEC_GSP2_SEND_PENDING", 5, 5, &umr_bitfield_default },
	 { "DP_SEC_GSP2_SEND_DEADLINE_MISSED", 6, 6, &umr_bitfield_default },
	 { "DP_SEC_GSP2_SEND_ANY_LINE", 7, 7, &umr_bitfield_default },
	 { "DP_SEC_GSP3_SEND", 8, 8, &umr_bitfield_default },
	 { "DP_SEC_GSP3_SEND_PENDING", 9, 9, &umr_bitfield_default },
	 { "DP_SEC_GSP3_SEND_DEADLINE_MISSED", 10, 10, &umr_bitfield_default },
	 { "DP_SEC_GSP3_SEND_ANY_LINE", 11, 11, &umr_bitfield_default },
	 { "DP_SEC_GSP4_SEND", 12, 12, &umr_bitfield_default },
	 { "DP_SEC_GSP4_SEND_PENDING", 13, 13, &umr_bitfield_default },
	 { "DP_SEC_GSP4_SEND_DEADLINE_MISSED", 14, 14, &umr_bitfield_default },
	 { "DP_SEC_GSP4_SEND_ANY_LINE", 15, 15, &umr_bitfield_default },
	 { "DP_SEC_GSP5_SEND", 16, 16, &umr_bitfield_default },
	 { "DP_SEC_GSP5_SEND_PENDING", 17, 17, &umr_bitfield_default },
	 { "DP_SEC_GSP5_SEND_DEADLINE_MISSED", 18, 18, &umr_bitfield_default },
	 { "DP_SEC_GSP5_SEND_ANY_LINE", 19, 19, &umr_bitfield_default },
	 { "DP_SEC_GSP6_SEND", 20, 20, &umr_bitfield_default },
	 { "DP_SEC_GSP6_SEND_PENDING", 21, 21, &umr_bitfield_default },
	 { "DP_SEC_GSP6_SEND_DEADLINE_MISSED", 22, 22, &umr_bitfield_default },
	 { "DP_SEC_GSP6_SEND_ANY_LINE", 23, 23, &umr_bitfield_default },
	 { "DP_SEC_GSP7_SEND", 24, 24, &umr_bitfield_default },
	 { "DP_SEC_GSP7_SEND_PENDING", 25, 25, &umr_bitfield_default },
	 { "DP_SEC_GSP7_SEND_DEADLINE_MISSED", 26, 26, &umr_bitfield_default },
	 { "DP_SEC_GSP7_SEND_ANY_LINE", 27, 27, &umr_bitfield_default },
	 { "DP_SEC_GSP7_PPS", 28, 28, &umr_bitfield_default },
};
static struct umr_bitfield mmDP1_DP_SEC_CNTL3[] = {
	 { "DP_SEC_GSP1_LINE_NUM", 0, 15, &umr_bitfield_default },
	 { "DP_SEC_GSP2_LINE_NUM", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDP1_DP_SEC_CNTL4[] = {
	 { "DP_SEC_GSP3_LINE_NUM", 0, 15, &umr_bitfield_default },
	 { "DP_SEC_GSP4_LINE_NUM", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDP1_DP_SEC_CNTL5[] = {
	 { "DP_SEC_GSP5_LINE_NUM", 0, 15, &umr_bitfield_default },
	 { "DP_SEC_GSP6_LINE_NUM", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDP1_DP_SEC_CNTL6[] = {
	 { "DP_SEC_GSP7_LINE_NUM", 0, 15, &umr_bitfield_default },
};
static struct umr_bitfield mmDP1_DP_SEC_CNTL7[] = {
	 { "DP_SEC_GSP0_SEND_ACTIVE", 0, 0, &umr_bitfield_default },
	 { "DP_SEC_GSP1_SEND_ACTIVE", 4, 4, &umr_bitfield_default },
	 { "DP_SEC_GSP2_SEND_ACTIVE", 8, 8, &umr_bitfield_default },
	 { "DP_SEC_GSP3_SEND_ACTIVE", 12, 12, &umr_bitfield_default },
	 { "DP_SEC_GSP4_SEND_ACTIVE", 16, 16, &umr_bitfield_default },
	 { "DP_SEC_GSP5_SEND_ACTIVE", 20, 20, &umr_bitfield_default },
	 { "DP_SEC_GSP6_SEND_ACTIVE", 24, 24, &umr_bitfield_default },
	 { "DP_SEC_GSP7_SEND_ACTIVE", 28, 28, &umr_bitfield_default },
};
static struct umr_bitfield mmDP1_DP_DB_CNTL[] = {
	 { "DP_DB_PENDING", 0, 0, &umr_bitfield_default },
	 { "DP_DB_TAKEN", 4, 4, &umr_bitfield_default },
	 { "DP_DB_TAKEN_CLR", 5, 5, &umr_bitfield_default },
	 { "DP_DB_LOCK", 8, 8, &umr_bitfield_default },
	 { "DP_DB_DISABLE", 12, 12, &umr_bitfield_default },
};
static struct umr_bitfield mmDP1_DP_MSA_VBID_MISC[] = {
	 { "DP_MSA_MISC1_STEREOSYNC_OVERRIDE", 0, 1, &umr_bitfield_default },
	 { "DP_MSA_MISC1_STEREOSYNC_OVERRIDE_EN", 4, 4, &umr_bitfield_default },
	 { "DP_VBID1_OVERRIDE", 8, 8, &umr_bitfield_default },
	 { "DP_VBID2_OVERRIDE", 9, 9, &umr_bitfield_default },
	 { "DP_VBID1_OVERRIDE_EN", 12, 12, &umr_bitfield_default },
	 { "DP_VBID2_OVERRIDE_EN", 13, 13, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG2_DIG_FE_CNTL[] = {
	 { "DIG_SOURCE_SELECT", 0, 2, &umr_bitfield_default },
	 { "DIG_STEREOSYNC_SELECT", 4, 6, &umr_bitfield_default },
	 { "DIG_STEREOSYNC_GATE_EN", 8, 8, &umr_bitfield_default },
	 { "DIG_START", 10, 10, &umr_bitfield_default },
	 { "DIG_DIGITAL_BYPASS_SELECT", 12, 14, &umr_bitfield_default },
	 { "DIG_SYMCLK_FE_ON", 24, 24, &umr_bitfield_default },
	 { "TMDS_PIXEL_ENCODING", 28, 28, &umr_bitfield_default },
	 { "TMDS_COLOR_FORMAT", 30, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG2_DIG_OUTPUT_CRC_CNTL[] = {
	 { "DIG_OUTPUT_CRC_EN", 0, 0, &umr_bitfield_default },
	 { "DIG_OUTPUT_CRC_LINK_SEL", 4, 4, &umr_bitfield_default },
	 { "DIG_OUTPUT_CRC_DATA_SEL", 8, 9, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG2_DIG_OUTPUT_CRC_RESULT[] = {
	 { "DIG_OUTPUT_CRC_RESULT", 0, 29, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG2_DIG_CLOCK_PATTERN[] = {
	 { "DIG_CLOCK_PATTERN", 0, 9, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG2_DIG_TEST_PATTERN[] = {
	 { "DIG_TEST_PATTERN_OUT_EN", 0, 0, &umr_bitfield_default },
	 { "DIG_HALF_CLOCK_PATTERN_SEL", 1, 1, &umr_bitfield_default },
	 { "DIG_RANDOM_PATTERN_OUT_EN", 4, 4, &umr_bitfield_default },
	 { "DIG_RANDOM_PATTERN_RESET", 5, 5, &umr_bitfield_default },
	 { "DIG_TEST_PATTERN_EXTERNAL_RESET_EN", 6, 6, &umr_bitfield_default },
	 { "DIG_STATIC_TEST_PATTERN", 16, 25, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG2_DIG_RANDOM_PATTERN_SEED[] = {
	 { "DIG_RANDOM_PATTERN_SEED", 0, 23, &umr_bitfield_default },
	 { "DIG_RAN_PAT_DURING_DE_ONLY", 24, 24, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG2_DIG_FIFO_STATUS[] = {
	 { "DIG_FIFO_LEVEL_ERROR", 0, 0, &umr_bitfield_default },
	 { "DIG_FIFO_USE_OVERWRITE_LEVEL", 1, 1, &umr_bitfield_default },
	 { "DIG_FIFO_OVERWRITE_LEVEL", 2, 7, &umr_bitfield_default },
	 { "DIG_FIFO_ERROR_ACK", 8, 8, &umr_bitfield_default },
	 { "DIG_FIFO_CAL_AVERAGE_LEVEL", 10, 15, &umr_bitfield_default },
	 { "DIG_FIFO_MAXIMUM_LEVEL", 16, 20, &umr_bitfield_default },
	 { "DIG_FIFO_MINIMUM_LEVEL", 22, 25, &umr_bitfield_default },
	 { "DIG_FIFO_READ_CLOCK_SRC", 26, 26, &umr_bitfield_default },
	 { "DIG_FIFO_CALIBRATED", 29, 29, &umr_bitfield_default },
	 { "DIG_FIFO_FORCE_RECAL_AVERAGE", 30, 30, &umr_bitfield_default },
	 { "DIG_FIFO_FORCE_RECOMP_MINMAX", 31, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG2_HDMI_CONTROL[] = {
	 { "HDMI_KEEPOUT_MODE", 0, 0, &umr_bitfield_default },
	 { "HDMI_DATA_SCRAMBLE_EN", 1, 1, &umr_bitfield_default },
	 { "HDMI_CLOCK_CHANNEL_RATE", 2, 2, &umr_bitfield_default },
	 { "HDMI_NO_EXTRA_NULL_PACKET_FILLED", 3, 3, &umr_bitfield_default },
	 { "HDMI_PACKET_GEN_VERSION", 4, 4, &umr_bitfield_default },
	 { "HDMI_ERROR_ACK", 8, 8, &umr_bitfield_default },
	 { "HDMI_ERROR_MASK", 9, 9, &umr_bitfield_default },
	 { "HDMI_DEEP_COLOR_ENABLE", 24, 24, &umr_bitfield_default },
	 { "HDMI_DEEP_COLOR_DEPTH", 28, 29, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG2_HDMI_STATUS[] = {
	 { "HDMI_ACTIVE_AVMUTE", 0, 0, &umr_bitfield_default },
	 { "HDMI_AUDIO_PACKET_ERROR", 16, 16, &umr_bitfield_default },
	 { "HDMI_VBI_PACKET_ERROR", 20, 20, &umr_bitfield_default },
	 { "HDMI_ERROR_INT", 27, 27, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG2_HDMI_AUDIO_PACKET_CONTROL[] = {
	 { "HDMI_AUDIO_DELAY_EN", 4, 5, &umr_bitfield_default },
	 { "HDMI_AUDIO_PACKETS_PER_LINE", 16, 20, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG2_HDMI_ACR_PACKET_CONTROL[] = {
	 { "HDMI_ACR_SEND", 0, 0, &umr_bitfield_default },
	 { "HDMI_ACR_CONT", 1, 1, &umr_bitfield_default },
	 { "HDMI_ACR_SELECT", 4, 5, &umr_bitfield_default },
	 { "HDMI_ACR_SOURCE", 8, 8, &umr_bitfield_default },
	 { "HDMI_ACR_AUTO_SEND", 12, 12, &umr_bitfield_default },
	 { "HDMI_ACR_N_MULTIPLE", 16, 18, &umr_bitfield_default },
	 { "HDMI_ACR_AUDIO_PRIORITY", 31, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG2_HDMI_VBI_PACKET_CONTROL[] = {
	 { "HDMI_NULL_SEND", 0, 0, &umr_bitfield_default },
	 { "HDMI_GC_SEND", 4, 4, &umr_bitfield_default },
	 { "HDMI_GC_CONT", 5, 5, &umr_bitfield_default },
	 { "HDMI_ISRC_SEND", 8, 8, &umr_bitfield_default },
	 { "HDMI_ISRC_CONT", 9, 9, &umr_bitfield_default },
	 { "HDMI_ISRC_LINE", 16, 21, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG2_HDMI_INFOFRAME_CONTROL0[] = {
	 { "HDMI_AUDIO_INFO_SEND", 4, 4, &umr_bitfield_default },
	 { "HDMI_AUDIO_INFO_CONT", 5, 5, &umr_bitfield_default },
	 { "HDMI_MPEG_INFO_SEND", 8, 8, &umr_bitfield_default },
	 { "HDMI_MPEG_INFO_CONT", 9, 9, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG2_HDMI_INFOFRAME_CONTROL1[] = {
	 { "HDMI_AUDIO_INFO_LINE", 8, 13, &umr_bitfield_default },
	 { "HDMI_MPEG_INFO_LINE", 16, 21, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG2_HDMI_GENERIC_PACKET_CONTROL0[] = {
	 { "HDMI_GENERIC0_SEND", 0, 0, &umr_bitfield_default },
	 { "HDMI_GENERIC0_CONT", 1, 1, &umr_bitfield_default },
	 { "HDMI_GENERIC1_SEND", 4, 4, &umr_bitfield_default },
	 { "HDMI_GENERIC1_CONT", 5, 5, &umr_bitfield_default },
	 { "HDMI_GENERIC0_LINE", 16, 21, &umr_bitfield_default },
	 { "HDMI_GENERIC1_LINE", 24, 29, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG2_HDMI_GC[] = {
	 { "HDMI_GC_AVMUTE", 0, 0, &umr_bitfield_default },
	 { "HDMI_GC_AVMUTE_CONT", 2, 2, &umr_bitfield_default },
	 { "HDMI_DEFAULT_PHASE", 4, 4, &umr_bitfield_default },
	 { "HDMI_PACKING_PHASE", 8, 11, &umr_bitfield_default },
	 { "HDMI_PACKING_PHASE_OVERRIDE", 12, 12, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG2_AFMT_AUDIO_PACKET_CONTROL2[] = {
	 { "AFMT_AUDIO_LAYOUT_OVRD", 0, 0, &umr_bitfield_default },
	 { "AFMT_AUDIO_LAYOUT_SELECT", 1, 1, &umr_bitfield_default },
	 { "AFMT_AUDIO_CHANNEL_ENABLE", 8, 15, &umr_bitfield_default },
	 { "AFMT_DP_AUDIO_STREAM_ID", 16, 23, &umr_bitfield_default },
	 { "AFMT_HBR_ENABLE_OVRD", 24, 24, &umr_bitfield_default },
	 { "AFMT_60958_OSF_OVRD", 28, 28, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG2_AFMT_ISRC1_0[] = {
	 { "AFMT_ISRC_STATUS", 0, 2, &umr_bitfield_default },
	 { "AFMT_ISRC_CONTINUE", 6, 6, &umr_bitfield_default },
	 { "AFMT_ISRC_VALID", 7, 7, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG2_AFMT_ISRC1_1[] = {
	 { "AFMT_UPC_EAN_ISRC0", 0, 7, &umr_bitfield_default },
	 { "AFMT_UPC_EAN_ISRC1", 8, 15, &umr_bitfield_default },
	 { "AFMT_UPC_EAN_ISRC2", 16, 23, &umr_bitfield_default },
	 { "AFMT_UPC_EAN_ISRC3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG2_AFMT_ISRC1_2[] = {
	 { "AFMT_UPC_EAN_ISRC4", 0, 7, &umr_bitfield_default },
	 { "AFMT_UPC_EAN_ISRC5", 8, 15, &umr_bitfield_default },
	 { "AFMT_UPC_EAN_ISRC6", 16, 23, &umr_bitfield_default },
	 { "AFMT_UPC_EAN_ISRC7", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG2_AFMT_ISRC1_3[] = {
	 { "AFMT_UPC_EAN_ISRC8", 0, 7, &umr_bitfield_default },
	 { "AFMT_UPC_EAN_ISRC9", 8, 15, &umr_bitfield_default },
	 { "AFMT_UPC_EAN_ISRC10", 16, 23, &umr_bitfield_default },
	 { "AFMT_UPC_EAN_ISRC11", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG2_AFMT_ISRC1_4[] = {
	 { "AFMT_UPC_EAN_ISRC12", 0, 7, &umr_bitfield_default },
	 { "AFMT_UPC_EAN_ISRC13", 8, 15, &umr_bitfield_default },
	 { "AFMT_UPC_EAN_ISRC14", 16, 23, &umr_bitfield_default },
	 { "AFMT_UPC_EAN_ISRC15", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG2_AFMT_ISRC2_0[] = {
	 { "AFMT_UPC_EAN_ISRC16", 0, 7, &umr_bitfield_default },
	 { "AFMT_UPC_EAN_ISRC17", 8, 15, &umr_bitfield_default },
	 { "AFMT_UPC_EAN_ISRC18", 16, 23, &umr_bitfield_default },
	 { "AFMT_UPC_EAN_ISRC19", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG2_AFMT_ISRC2_1[] = {
	 { "AFMT_UPC_EAN_ISRC20", 0, 7, &umr_bitfield_default },
	 { "AFMT_UPC_EAN_ISRC21", 8, 15, &umr_bitfield_default },
	 { "AFMT_UPC_EAN_ISRC22", 16, 23, &umr_bitfield_default },
	 { "AFMT_UPC_EAN_ISRC23", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG2_AFMT_ISRC2_2[] = {
	 { "AFMT_UPC_EAN_ISRC24", 0, 7, &umr_bitfield_default },
	 { "AFMT_UPC_EAN_ISRC25", 8, 15, &umr_bitfield_default },
	 { "AFMT_UPC_EAN_ISRC26", 16, 23, &umr_bitfield_default },
	 { "AFMT_UPC_EAN_ISRC27", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG2_AFMT_ISRC2_3[] = {
	 { "AFMT_UPC_EAN_ISRC28", 0, 7, &umr_bitfield_default },
	 { "AFMT_UPC_EAN_ISRC29", 8, 15, &umr_bitfield_default },
	 { "AFMT_UPC_EAN_ISRC30", 16, 23, &umr_bitfield_default },
	 { "AFMT_UPC_EAN_ISRC31", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG2_HDMI_GENERIC_PACKET_CONTROL2[] = {
	 { "HDMI_GENERIC4_SEND", 0, 0, &umr_bitfield_default },
	 { "HDMI_GENERIC4_CONT", 1, 1, &umr_bitfield_default },
	 { "HDMI_GENERIC5_SEND", 4, 4, &umr_bitfield_default },
	 { "HDMI_GENERIC5_CONT", 5, 5, &umr_bitfield_default },
	 { "HDMI_GENERIC4_LINE", 16, 21, &umr_bitfield_default },
	 { "HDMI_GENERIC5_LINE", 24, 29, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG2_HDMI_GENERIC_PACKET_CONTROL3[] = {
	 { "HDMI_GENERIC6_SEND", 0, 0, &umr_bitfield_default },
	 { "HDMI_GENERIC6_CONT", 1, 1, &umr_bitfield_default },
	 { "HDMI_GENERIC7_SEND", 4, 4, &umr_bitfield_default },
	 { "HDMI_GENERIC7_CONT", 5, 5, &umr_bitfield_default },
	 { "HDMI_GENERIC6_LINE", 16, 21, &umr_bitfield_default },
	 { "HDMI_GENERIC7_LINE", 24, 29, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG2_HDMI_DB_CONTROL[] = {
	 { "HDMI_DB_PENDING", 0, 0, &umr_bitfield_default },
	 { "HDMI_DB_TAKEN", 4, 4, &umr_bitfield_default },
	 { "HDMI_DB_TAKEN_CLR", 5, 5, &umr_bitfield_default },
	 { "HDMI_DB_LOCK", 8, 8, &umr_bitfield_default },
	 { "HDMI_DB_DISABLE", 12, 12, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG2_AFMT_MPEG_INFO0[] = {
	 { "AFMT_MPEG_INFO_CHECKSUM", 0, 7, &umr_bitfield_default },
	 { "AFMT_MPEG_INFO_MB0", 8, 15, &umr_bitfield_default },
	 { "AFMT_MPEG_INFO_MB1", 16, 23, &umr_bitfield_default },
	 { "AFMT_MPEG_INFO_MB2", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG2_AFMT_MPEG_INFO1[] = {
	 { "AFMT_MPEG_INFO_MB3", 0, 7, &umr_bitfield_default },
	 { "AFMT_MPEG_INFO_MF", 8, 9, &umr_bitfield_default },
	 { "AFMT_MPEG_INFO_FR", 12, 12, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG2_AFMT_GENERIC_HDR[] = {
	 { "AFMT_GENERIC_HB0", 0, 7, &umr_bitfield_default },
	 { "AFMT_GENERIC_HB1", 8, 15, &umr_bitfield_default },
	 { "AFMT_GENERIC_HB2", 16, 23, &umr_bitfield_default },
	 { "AFMT_GENERIC_HB3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG2_AFMT_GENERIC_0[] = {
	 { "AFMT_GENERIC_BYTE0", 0, 7, &umr_bitfield_default },
	 { "AFMT_GENERIC_BYTE1", 8, 15, &umr_bitfield_default },
	 { "AFMT_GENERIC_BYTE2", 16, 23, &umr_bitfield_default },
	 { "AFMT_GENERIC_BYTE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG2_AFMT_GENERIC_1[] = {
	 { "AFMT_GENERIC_BYTE4", 0, 7, &umr_bitfield_default },
	 { "AFMT_GENERIC_BYTE5", 8, 15, &umr_bitfield_default },
	 { "AFMT_GENERIC_BYTE6", 16, 23, &umr_bitfield_default },
	 { "AFMT_GENERIC_BYTE7", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG2_AFMT_GENERIC_2[] = {
	 { "AFMT_GENERIC_BYTE8", 0, 7, &umr_bitfield_default },
	 { "AFMT_GENERIC_BYTE9", 8, 15, &umr_bitfield_default },
	 { "AFMT_GENERIC_BYTE10", 16, 23, &umr_bitfield_default },
	 { "AFMT_GENERIC_BYTE11", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG2_AFMT_GENERIC_3[] = {
	 { "AFMT_GENERIC_BYTE12", 0, 7, &umr_bitfield_default },
	 { "AFMT_GENERIC_BYTE13", 8, 15, &umr_bitfield_default },
	 { "AFMT_GENERIC_BYTE14", 16, 23, &umr_bitfield_default },
	 { "AFMT_GENERIC_BYTE15", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG2_AFMT_GENERIC_4[] = {
	 { "AFMT_GENERIC_BYTE16", 0, 7, &umr_bitfield_default },
	 { "AFMT_GENERIC_BYTE17", 8, 15, &umr_bitfield_default },
	 { "AFMT_GENERIC_BYTE18", 16, 23, &umr_bitfield_default },
	 { "AFMT_GENERIC_BYTE19", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG2_AFMT_GENERIC_5[] = {
	 { "AFMT_GENERIC_BYTE20", 0, 7, &umr_bitfield_default },
	 { "AFMT_GENERIC_BYTE21", 8, 15, &umr_bitfield_default },
	 { "AFMT_GENERIC_BYTE22", 16, 23, &umr_bitfield_default },
	 { "AFMT_GENERIC_BYTE23", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG2_AFMT_GENERIC_6[] = {
	 { "AFMT_GENERIC_BYTE24", 0, 7, &umr_bitfield_default },
	 { "AFMT_GENERIC_BYTE25", 8, 15, &umr_bitfield_default },
	 { "AFMT_GENERIC_BYTE26", 16, 23, &umr_bitfield_default },
	 { "AFMT_GENERIC_BYTE27", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG2_AFMT_GENERIC_7[] = {
	 { "AFMT_GENERIC_BYTE28", 0, 7, &umr_bitfield_default },
	 { "AFMT_GENERIC_BYTE29", 8, 15, &umr_bitfield_default },
	 { "AFMT_GENERIC_BYTE30", 16, 23, &umr_bitfield_default },
	 { "AFMT_GENERIC_BYTE31", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG2_HDMI_GENERIC_PACKET_CONTROL1[] = {
	 { "HDMI_GENERIC2_SEND", 0, 0, &umr_bitfield_default },
	 { "HDMI_GENERIC2_CONT", 1, 1, &umr_bitfield_default },
	 { "HDMI_GENERIC3_SEND", 4, 4, &umr_bitfield_default },
	 { "HDMI_GENERIC3_CONT", 5, 5, &umr_bitfield_default },
	 { "HDMI_GENERIC2_LINE", 16, 21, &umr_bitfield_default },
	 { "HDMI_GENERIC3_LINE", 24, 29, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG2_HDMI_ACR_32_0[] = {
	 { "HDMI_ACR_CTS_32", 12, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG2_HDMI_ACR_32_1[] = {
	 { "HDMI_ACR_N_32", 0, 19, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG2_HDMI_ACR_44_0[] = {
	 { "HDMI_ACR_CTS_44", 12, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG2_HDMI_ACR_44_1[] = {
	 { "HDMI_ACR_N_44", 0, 19, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG2_HDMI_ACR_48_0[] = {
	 { "HDMI_ACR_CTS_48", 12, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG2_HDMI_ACR_48_1[] = {
	 { "HDMI_ACR_N_48", 0, 19, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG2_HDMI_ACR_STATUS_0[] = {
	 { "HDMI_ACR_CTS", 12, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG2_HDMI_ACR_STATUS_1[] = {
	 { "HDMI_ACR_N", 0, 19, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG2_AFMT_AUDIO_INFO0[] = {
	 { "AFMT_AUDIO_INFO_CHECKSUM", 0, 7, &umr_bitfield_default },
	 { "AFMT_AUDIO_INFO_CC", 8, 10, &umr_bitfield_default },
	 { "AFMT_AUDIO_INFO_CT", 11, 14, &umr_bitfield_default },
	 { "AFMT_AUDIO_INFO_CHECKSUM_OFFSET", 16, 23, &umr_bitfield_default },
	 { "AFMT_AUDIO_INFO_CXT", 24, 28, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG2_AFMT_AUDIO_INFO1[] = {
	 { "AFMT_AUDIO_INFO_CA", 0, 7, &umr_bitfield_default },
	 { "AFMT_AUDIO_INFO_LSV", 11, 14, &umr_bitfield_default },
	 { "AFMT_AUDIO_INFO_DM_INH", 15, 15, &umr_bitfield_default },
	 { "AFMT_AUDIO_INFO_LFEPBL", 16, 17, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG2_AFMT_60958_0[] = {
	 { "AFMT_60958_CS_A", 0, 0, &umr_bitfield_default },
	 { "AFMT_60958_CS_B", 1, 1, &umr_bitfield_default },
	 { "AFMT_60958_CS_C", 2, 2, &umr_bitfield_default },
	 { "AFMT_60958_CS_D", 3, 5, &umr_bitfield_default },
	 { "AFMT_60958_CS_MODE", 6, 7, &umr_bitfield_default },
	 { "AFMT_60958_CS_CATEGORY_CODE", 8, 15, &umr_bitfield_default },
	 { "AFMT_60958_CS_SOURCE_NUMBER", 16, 19, &umr_bitfield_default },
	 { "AFMT_60958_CS_CHANNEL_NUMBER_L", 20, 23, &umr_bitfield_default },
	 { "AFMT_60958_CS_SAMPLING_FREQUENCY", 24, 27, &umr_bitfield_default },
	 { "AFMT_60958_CS_CLOCK_ACCURACY", 28, 29, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG2_AFMT_60958_1[] = {
	 { "AFMT_60958_CS_WORD_LENGTH", 0, 3, &umr_bitfield_default },
	 { "AFMT_60958_CS_ORIGINAL_SAMPLING_FREQUENCY", 4, 7, &umr_bitfield_default },
	 { "AFMT_60958_VALID_L", 16, 16, &umr_bitfield_default },
	 { "AFMT_60958_VALID_R", 18, 18, &umr_bitfield_default },
	 { "AFMT_60958_CS_CHANNEL_NUMBER_R", 20, 23, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG2_AFMT_AUDIO_CRC_CONTROL[] = {
	 { "AFMT_AUDIO_CRC_EN", 0, 0, &umr_bitfield_default },
	 { "AFMT_AUDIO_CRC_CONT", 4, 4, &umr_bitfield_default },
	 { "AFMT_AUDIO_CRC_SOURCE", 8, 8, &umr_bitfield_default },
	 { "AFMT_AUDIO_CRC_CH_SEL", 12, 15, &umr_bitfield_default },
	 { "AFMT_AUDIO_CRC_COUNT", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG2_AFMT_RAMP_CONTROL0[] = {
	 { "AFMT_RAMP_MAX_COUNT", 0, 23, &umr_bitfield_default },
	 { "AFMT_RAMP_DATA_SIGN", 31, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG2_AFMT_RAMP_CONTROL1[] = {
	 { "AFMT_RAMP_MIN_COUNT", 0, 23, &umr_bitfield_default },
	 { "AFMT_AUDIO_TEST_CH_DISABLE", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG2_AFMT_RAMP_CONTROL2[] = {
	 { "AFMT_RAMP_INC_COUNT", 0, 23, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG2_AFMT_RAMP_CONTROL3[] = {
	 { "AFMT_RAMP_DEC_COUNT", 0, 23, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG2_AFMT_60958_2[] = {
	 { "AFMT_60958_CS_CHANNEL_NUMBER_2", 0, 3, &umr_bitfield_default },
	 { "AFMT_60958_CS_CHANNEL_NUMBER_3", 4, 7, &umr_bitfield_default },
	 { "AFMT_60958_CS_CHANNEL_NUMBER_4", 8, 11, &umr_bitfield_default },
	 { "AFMT_60958_CS_CHANNEL_NUMBER_5", 12, 15, &umr_bitfield_default },
	 { "AFMT_60958_CS_CHANNEL_NUMBER_6", 16, 19, &umr_bitfield_default },
	 { "AFMT_60958_CS_CHANNEL_NUMBER_7", 20, 23, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG2_AFMT_AUDIO_CRC_RESULT[] = {
	 { "AFMT_AUDIO_CRC_DONE", 0, 0, &umr_bitfield_default },
	 { "AFMT_AUDIO_CRC", 8, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG2_AFMT_STATUS[] = {
	 { "AFMT_AUDIO_ENABLE", 4, 4, &umr_bitfield_default },
	 { "AFMT_AZ_HBR_ENABLE", 8, 8, &umr_bitfield_default },
	 { "AFMT_AUDIO_FIFO_OVERFLOW", 24, 24, &umr_bitfield_default },
	 { "AFMT_AZ_AUDIO_ENABLE_CHG", 30, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG2_AFMT_AUDIO_PACKET_CONTROL[] = {
	 { "AFMT_AUDIO_SAMPLE_SEND", 0, 0, &umr_bitfield_default },
	 { "AFMT_RESET_FIFO_WHEN_AUDIO_DIS", 11, 11, &umr_bitfield_default },
	 { "AFMT_AUDIO_TEST_EN", 12, 12, &umr_bitfield_default },
	 { "AFMT_AUDIO_TEST_MODE", 14, 14, &umr_bitfield_default },
	 { "AFMT_AUDIO_FIFO_OVERFLOW_ACK", 23, 23, &umr_bitfield_default },
	 { "AFMT_AUDIO_CHANNEL_SWAP", 24, 24, &umr_bitfield_default },
	 { "AFMT_60958_CS_UPDATE", 26, 26, &umr_bitfield_default },
	 { "AFMT_AZ_AUDIO_ENABLE_CHG_ACK", 30, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG2_AFMT_VBI_PACKET_CONTROL[] = {
	 { "AFMT_GENERIC_LOCK_STATUS", 8, 8, &umr_bitfield_default },
	 { "AFMT_GENERIC_CONFLICT", 16, 16, &umr_bitfield_default },
	 { "AFMT_GENERIC_CONFLICT_CLR", 17, 17, &umr_bitfield_default },
	 { "AFMT_GENERIC_INDEX", 28, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG2_AFMT_INFOFRAME_CONTROL0[] = {
	 { "AFMT_AUDIO_INFO_SOURCE", 6, 6, &umr_bitfield_default },
	 { "AFMT_AUDIO_INFO_UPDATE", 7, 7, &umr_bitfield_default },
	 { "AFMT_MPEG_INFO_UPDATE", 10, 10, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG2_AFMT_AUDIO_SRC_CONTROL[] = {
	 { "AFMT_AUDIO_SRC_SELECT", 0, 2, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG2_DIG_BE_CNTL[] = {
	 { "DIG_DUAL_LINK_ENABLE", 0, 0, &umr_bitfield_default },
	 { "DIG_SWAP", 1, 1, &umr_bitfield_default },
	 { "DIG_FE_SOURCE_SELECT", 8, 14, &umr_bitfield_default },
	 { "DIG_MODE", 16, 18, &umr_bitfield_default },
	 { "DIG_HPD_SELECT", 28, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG2_DIG_BE_EN_CNTL[] = {
	 { "DIG_ENABLE", 0, 0, &umr_bitfield_default },
	 { "DIG_SYMCLK_BE_ON", 8, 8, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG2_TMDS_CNTL[] = {
	 { "TMDS_SYNC_PHASE", 0, 0, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG2_TMDS_CONTROL_CHAR[] = {
	 { "TMDS_CONTROL_CHAR0_OUT_EN", 0, 0, &umr_bitfield_default },
	 { "TMDS_CONTROL_CHAR1_OUT_EN", 1, 1, &umr_bitfield_default },
	 { "TMDS_CONTROL_CHAR2_OUT_EN", 2, 2, &umr_bitfield_default },
	 { "TMDS_CONTROL_CHAR3_OUT_EN", 3, 3, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG2_TMDS_CONTROL0_FEEDBACK[] = {
	 { "TMDS_CONTROL0_FEEDBACK_SELECT", 0, 1, &umr_bitfield_default },
	 { "TMDS_CONTROL0_FEEDBACK_DELAY", 8, 9, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG2_TMDS_STEREOSYNC_CTL_SEL[] = {
	 { "TMDS_STEREOSYNC_CTL_SEL", 0, 1, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG2_TMDS_SYNC_CHAR_PATTERN_0_1[] = {
	 { "TMDS_SYNC_CHAR_PATTERN0", 0, 9, &umr_bitfield_default },
	 { "TMDS_SYNC_CHAR_PATTERN1", 16, 25, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG2_TMDS_SYNC_CHAR_PATTERN_2_3[] = {
	 { "TMDS_SYNC_CHAR_PATTERN2", 0, 9, &umr_bitfield_default },
	 { "TMDS_SYNC_CHAR_PATTERN3", 16, 25, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG2_TMDS_CTL_BITS[] = {
	 { "TMDS_CTL0", 0, 0, &umr_bitfield_default },
	 { "TMDS_CTL1", 8, 8, &umr_bitfield_default },
	 { "TMDS_CTL2", 16, 16, &umr_bitfield_default },
	 { "TMDS_CTL3", 24, 24, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG2_TMDS_DCBALANCER_CONTROL[] = {
	 { "TMDS_DCBALANCER_EN", 0, 0, &umr_bitfield_default },
	 { "TMDS_DCBALANCER_TEST_EN", 8, 8, &umr_bitfield_default },
	 { "TMDS_DCBALANCER_TEST_IN", 16, 19, &umr_bitfield_default },
	 { "TMDS_DCBALANCER_FORCE", 24, 24, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG2_TMDS_CTL0_1_GEN_CNTL[] = {
	 { "TMDS_CTL0_DATA_SEL", 0, 3, &umr_bitfield_default },
	 { "TMDS_CTL0_DATA_DELAY", 4, 6, &umr_bitfield_default },
	 { "TMDS_CTL0_DATA_INVERT", 7, 7, &umr_bitfield_default },
	 { "TMDS_CTL0_DATA_MODULATION", 8, 9, &umr_bitfield_default },
	 { "TMDS_CTL0_USE_FEEDBACK_PATH", 10, 10, &umr_bitfield_default },
	 { "TMDS_CTL0_FB_SYNC_CONT", 11, 11, &umr_bitfield_default },
	 { "TMDS_CTL0_PATTERN_OUT_EN", 12, 12, &umr_bitfield_default },
	 { "TMDS_CTL1_DATA_SEL", 16, 19, &umr_bitfield_default },
	 { "TMDS_CTL1_DATA_DELAY", 20, 22, &umr_bitfield_default },
	 { "TMDS_CTL1_DATA_INVERT", 23, 23, &umr_bitfield_default },
	 { "TMDS_CTL1_DATA_MODULATION", 24, 25, &umr_bitfield_default },
	 { "TMDS_CTL1_USE_FEEDBACK_PATH", 26, 26, &umr_bitfield_default },
	 { "TMDS_CTL1_FB_SYNC_CONT", 27, 27, &umr_bitfield_default },
	 { "TMDS_CTL1_PATTERN_OUT_EN", 28, 28, &umr_bitfield_default },
	 { "TMDS_2BIT_COUNTER_EN", 31, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG2_TMDS_CTL2_3_GEN_CNTL[] = {
	 { "TMDS_CTL2_DATA_SEL", 0, 3, &umr_bitfield_default },
	 { "TMDS_CTL2_DATA_DELAY", 4, 6, &umr_bitfield_default },
	 { "TMDS_CTL2_DATA_INVERT", 7, 7, &umr_bitfield_default },
	 { "TMDS_CTL2_DATA_MODULATION", 8, 9, &umr_bitfield_default },
	 { "TMDS_CTL2_USE_FEEDBACK_PATH", 10, 10, &umr_bitfield_default },
	 { "TMDS_CTL2_FB_SYNC_CONT", 11, 11, &umr_bitfield_default },
	 { "TMDS_CTL2_PATTERN_OUT_EN", 12, 12, &umr_bitfield_default },
	 { "TMDS_CTL3_DATA_SEL", 16, 19, &umr_bitfield_default },
	 { "TMDS_CTL3_DATA_DELAY", 20, 22, &umr_bitfield_default },
	 { "TMDS_CTL3_DATA_INVERT", 23, 23, &umr_bitfield_default },
	 { "TMDS_CTL3_DATA_MODULATION", 24, 25, &umr_bitfield_default },
	 { "TMDS_CTL3_USE_FEEDBACK_PATH", 26, 26, &umr_bitfield_default },
	 { "TMDS_CTL3_FB_SYNC_CONT", 27, 27, &umr_bitfield_default },
	 { "TMDS_CTL3_PATTERN_OUT_EN", 28, 28, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG2_DIG_VERSION[] = {
	 { "DIG_TYPE", 0, 0, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG2_DIG_LANE_ENABLE[] = {
	 { "DIG_LANE0EN", 0, 0, &umr_bitfield_default },
	 { "DIG_LANE1EN", 1, 1, &umr_bitfield_default },
	 { "DIG_LANE2EN", 2, 2, &umr_bitfield_default },
	 { "DIG_LANE3EN", 3, 3, &umr_bitfield_default },
	 { "DIG_CLK_EN", 8, 8, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG2_AFMT_CNTL[] = {
	 { "AFMT_AUDIO_CLOCK_EN", 0, 0, &umr_bitfield_default },
	 { "AFMT_AUDIO_CLOCK_ON", 8, 8, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG2_AFMT_VBI_PACKET_CONTROL1[] = {
	 { "AFMT_GENERIC0_FRAME_UPDATE", 0, 0, &umr_bitfield_default },
	 { "AFMT_GENERIC0_FRAME_UPDATE_PENDING", 1, 1, &umr_bitfield_default },
	 { "AFMT_GENERIC0_IMMEDIATE_UPDATE", 2, 2, &umr_bitfield_default },
	 { "AFMT_GENERIC0_IMMEDIATE_UPDATE_PENDING", 3, 3, &umr_bitfield_default },
	 { "AFMT_GENERIC1_FRAME_UPDATE", 4, 4, &umr_bitfield_default },
	 { "AFMT_GENERIC1_FRAME_UPDATE_PENDING", 5, 5, &umr_bitfield_default },
	 { "AFMT_GENERIC1_IMMEDIATE_UPDATE", 6, 6, &umr_bitfield_default },
	 { "AFMT_GENERIC1_IMMEDIATE_UPDATE_PENDING", 7, 7, &umr_bitfield_default },
	 { "AFMT_GENERIC2_FRAME_UPDATE", 8, 8, &umr_bitfield_default },
	 { "AFMT_GENERIC2_FRAME_UPDATE_PENDING", 9, 9, &umr_bitfield_default },
	 { "AFMT_GENERIC2_IMMEDIATE_UPDATE", 10, 10, &umr_bitfield_default },
	 { "AFMT_GENERIC2_IMMEDIATE_UPDATE_PENDING", 11, 11, &umr_bitfield_default },
	 { "AFMT_GENERIC3_FRAME_UPDATE", 12, 12, &umr_bitfield_default },
	 { "AFMT_GENERIC3_FRAME_UPDATE_PENDING", 13, 13, &umr_bitfield_default },
	 { "AFMT_GENERIC3_IMMEDIATE_UPDATE", 14, 14, &umr_bitfield_default },
	 { "AFMT_GENERIC3_IMMEDIATE_UPDATE_PENDING", 15, 15, &umr_bitfield_default },
	 { "AFMT_GENERIC4_FRAME_UPDATE", 16, 16, &umr_bitfield_default },
	 { "AFMT_GENERIC4_FRAME_UPDATE_PENDING", 17, 17, &umr_bitfield_default },
	 { "AFMT_GENERIC4_IMMEDIATE_UPDATE", 18, 18, &umr_bitfield_default },
	 { "AFMT_GENERIC4_IMMEDIATE_UPDATE_PENDING", 19, 19, &umr_bitfield_default },
	 { "AFMT_GENERIC5_FRAME_UPDATE", 20, 20, &umr_bitfield_default },
	 { "AFMT_GENERIC5_FRAME_UPDATE_PENDING", 21, 21, &umr_bitfield_default },
	 { "AFMT_GENERIC5_IMMEDIATE_UPDATE", 22, 22, &umr_bitfield_default },
	 { "AFMT_GENERIC5_IMMEDIATE_UPDATE_PENDING", 23, 23, &umr_bitfield_default },
	 { "AFMT_GENERIC6_FRAME_UPDATE", 24, 24, &umr_bitfield_default },
	 { "AFMT_GENERIC6_FRAME_UPDATE_PENDING", 25, 25, &umr_bitfield_default },
	 { "AFMT_GENERIC6_IMMEDIATE_UPDATE", 26, 26, &umr_bitfield_default },
	 { "AFMT_GENERIC6_IMMEDIATE_UPDATE_PENDING", 27, 27, &umr_bitfield_default },
	 { "AFMT_GENERIC7_FRAME_UPDATE", 28, 28, &umr_bitfield_default },
	 { "AFMT_GENERIC7_FRAME_UPDATE_PENDING", 29, 29, &umr_bitfield_default },
	 { "AFMT_GENERIC7_IMMEDIATE_UPDATE", 30, 30, &umr_bitfield_default },
	 { "AFMT_GENERIC7_IMMEDIATE_UPDATE_PENDING", 31, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDP2_DP_LINK_CNTL[] = {
	 { "DP_LINK_TRAINING_COMPLETE", 4, 4, &umr_bitfield_default },
	 { "DP_LINK_STATUS", 8, 8, &umr_bitfield_default },
	 { "DP_EMBEDDED_PANEL_MODE", 17, 17, &umr_bitfield_default },
};
static struct umr_bitfield mmDP2_DP_PIXEL_FORMAT[] = {
	 { "DP_PIXEL_ENCODING", 0, 2, &umr_bitfield_default },
	 { "DP_COMPONENT_DEPTH", 24, 26, &umr_bitfield_default },
	 { "DP_PIXEL_COMBINE", 28, 29, &umr_bitfield_default },
};
static struct umr_bitfield mmDP2_DP_MSA_COLORIMETRY[] = {
	 { "DP_MSA_MISC0", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDP2_DP_CONFIG[] = {
	 { "DP_UDI_LANES", 0, 1, &umr_bitfield_default },
};
static struct umr_bitfield mmDP2_DP_VID_STREAM_CNTL[] = {
	 { "DP_VID_STREAM_ENABLE", 0, 0, &umr_bitfield_default },
	 { "DP_VID_STREAM_DIS_DEFER", 8, 9, &umr_bitfield_default },
	 { "DP_VID_STREAM_STATUS", 16, 16, &umr_bitfield_default },
	 { "DP_VID_STREAM_CHANGE_KEEPOUT", 20, 20, &umr_bitfield_default },
};
static struct umr_bitfield mmDP2_DP_STEER_FIFO[] = {
	 { "DP_STEER_FIFO_RESET", 0, 0, &umr_bitfield_default },
	 { "DP_STEER_OVERFLOW_FLAG", 4, 4, &umr_bitfield_default },
	 { "DP_STEER_OVERFLOW_INT", 5, 5, &umr_bitfield_default },
	 { "DP_STEER_OVERFLOW_ACK", 6, 6, &umr_bitfield_default },
	 { "DP_STEER_OVERFLOW_MASK", 7, 7, &umr_bitfield_default },
	 { "DP_TU_OVERFLOW_FLAG", 8, 8, &umr_bitfield_default },
	 { "DP_TU_OVERFLOW_ACK", 12, 12, &umr_bitfield_default },
};
static struct umr_bitfield mmDP2_DP_MSA_MISC[] = {
	 { "DP_MSA_MISC1", 0, 7, &umr_bitfield_default },
	 { "DP_MSA_MISC2", 8, 15, &umr_bitfield_default },
	 { "DP_MSA_MISC3", 16, 23, &umr_bitfield_default },
	 { "DP_MSA_MISC4", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDP2_DP_VID_TIMING[] = {
	 { "DP_VID_M_N_DOUBLE_BUFFER_MODE", 4, 4, &umr_bitfield_default },
	 { "DP_VID_M_N_GEN_EN", 8, 8, &umr_bitfield_default },
	 { "DP_VID_N_MUL", 10, 11, &umr_bitfield_default },
	 { "DP_VID_M_DIV", 12, 13, &umr_bitfield_default },
	 { "DP_VID_N_DIV", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDP2_DP_VID_N[] = {
	 { "DP_VID_N", 0, 23, &umr_bitfield_default },
};
static struct umr_bitfield mmDP2_DP_VID_M[] = {
	 { "DP_VID_M", 0, 23, &umr_bitfield_default },
};
static struct umr_bitfield mmDP2_DP_LINK_FRAMING_CNTL[] = {
	 { "DP_IDLE_BS_INTERVAL", 0, 17, &umr_bitfield_default },
	 { "DP_VBID_DISABLE", 24, 24, &umr_bitfield_default },
	 { "DP_VID_ENHANCED_FRAME_MODE", 28, 28, &umr_bitfield_default },
};
static struct umr_bitfield mmDP2_DP_HBR2_EYE_PATTERN[] = {
	 { "DP_HBR2_EYE_PATTERN_ENABLE", 0, 0, &umr_bitfield_default },
};
static struct umr_bitfield mmDP2_DP_VID_MSA_VBID[] = {
	 { "DP_VID_MSA_LOCATION", 0, 11, &umr_bitfield_default },
	 { "DP_VID_VBID_FIELD_POL", 24, 24, &umr_bitfield_default },
};
static struct umr_bitfield mmDP2_DP_VID_INTERRUPT_CNTL[] = {
	 { "DP_VID_STREAM_DISABLE_INT", 0, 0, &umr_bitfield_default },
	 { "DP_VID_STREAM_DISABLE_ACK", 1, 1, &umr_bitfield_default },
	 { "DP_VID_STREAM_DISABLE_MASK", 2, 2, &umr_bitfield_default },
};
static struct umr_bitfield mmDP2_DP_DPHY_CNTL[] = {
	 { "DPHY_ATEST_SEL_LANE0", 0, 0, &umr_bitfield_default },
	 { "DPHY_ATEST_SEL_LANE1", 1, 1, &umr_bitfield_default },
	 { "DPHY_ATEST_SEL_LANE2", 2, 2, &umr_bitfield_default },
	 { "DPHY_ATEST_SEL_LANE3", 3, 3, &umr_bitfield_default },
	 { "DPHY_BYPASS", 16, 16, &umr_bitfield_default },
	 { "DPHY_SKEW_BYPASS", 24, 24, &umr_bitfield_default },
};
static struct umr_bitfield mmDP2_DP_DPHY_TRAINING_PATTERN_SEL[] = {
	 { "DPHY_TRAINING_PATTERN_SEL", 0, 1, &umr_bitfield_default },
};
static struct umr_bitfield mmDP2_DP_DPHY_SYM0[] = {
	 { "DPHY_SYM1", 0, 9, &umr_bitfield_default },
	 { "DPHY_SYM2", 10, 19, &umr_bitfield_default },
	 { "DPHY_SYM3", 20, 29, &umr_bitfield_default },
};
static struct umr_bitfield mmDP2_DP_DPHY_SYM1[] = {
	 { "DPHY_SYM4", 0, 9, &umr_bitfield_default },
	 { "DPHY_SYM5", 10, 19, &umr_bitfield_default },
	 { "DPHY_SYM6", 20, 29, &umr_bitfield_default },
};
static struct umr_bitfield mmDP2_DP_DPHY_SYM2[] = {
	 { "DPHY_SYM7", 0, 9, &umr_bitfield_default },
	 { "DPHY_SYM8", 10, 19, &umr_bitfield_default },
};
static struct umr_bitfield mmDP2_DP_DPHY_8B10B_CNTL[] = {
	 { "DPHY_8B10B_RESET", 8, 8, &umr_bitfield_default },
	 { "DPHY_8B10B_EXT_DISP", 16, 16, &umr_bitfield_default },
	 { "DPHY_8B10B_CUR_DISP", 24, 24, &umr_bitfield_default },
};
static struct umr_bitfield mmDP2_DP_DPHY_PRBS_CNTL[] = {
	 { "DPHY_PRBS_EN", 0, 0, &umr_bitfield_default },
	 { "DPHY_PRBS_SEL", 4, 5, &umr_bitfield_default },
	 { "DPHY_PRBS_SEED", 8, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmDP2_DP_DPHY_SCRAM_CNTL[] = {
	 { "DPHY_SCRAMBLER_DIS", 0, 0, &umr_bitfield_default },
	 { "DPHY_SCRAMBLER_ADVANCE", 4, 4, &umr_bitfield_default },
	 { "DPHY_SCRAMBLER_BS_COUNT", 8, 17, &umr_bitfield_default },
	 { "DPHY_SCRAMBLER_KCODE", 24, 24, &umr_bitfield_default },
};
static struct umr_bitfield mmDP2_DP_DPHY_CRC_EN[] = {
	 { "DPHY_CRC_EN", 0, 0, &umr_bitfield_default },
	 { "DPHY_CRC_CONT_EN", 4, 4, &umr_bitfield_default },
	 { "DPHY_CRC_RESULT_VALID", 8, 8, &umr_bitfield_default },
};
static struct umr_bitfield mmDP2_DP_DPHY_CRC_CNTL[] = {
	 { "DPHY_CRC_FIELD", 0, 0, &umr_bitfield_default },
	 { "DPHY_CRC_SEL", 4, 5, &umr_bitfield_default },
	 { "DPHY_CRC_MASK", 16, 23, &umr_bitfield_default },
};
static struct umr_bitfield mmDP2_DP_DPHY_CRC_RESULT[] = {
	 { "DPHY_CRC_RESULT", 0, 7, &umr_bitfield_default },
	 { "DPHY_CRC_RESULT1", 8, 15, &umr_bitfield_default },
	 { "DPHY_CRC_RESULT2", 16, 23, &umr_bitfield_default },
	 { "DPHY_CRC_RESULT3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDP2_DP_DPHY_CRC_MST_CNTL[] = {
	 { "DPHY_CRC_MST_FIRST_SLOT", 0, 5, &umr_bitfield_default },
	 { "DPHY_CRC_MST_LAST_SLOT", 8, 13, &umr_bitfield_default },
};
static struct umr_bitfield mmDP2_DP_DPHY_CRC_MST_STATUS[] = {
	 { "DPHY_CRC_MST_PHASE_LOCK", 0, 0, &umr_bitfield_default },
	 { "DPHY_CRC_MST_PHASE_ERROR", 8, 8, &umr_bitfield_default },
	 { "DPHY_CRC_MST_PHASE_ERROR_ACK", 16, 16, &umr_bitfield_default },
};
static struct umr_bitfield mmDP2_DP_DPHY_FAST_TRAINING[] = {
	 { "DPHY_RX_FAST_TRAINING_CAPABLE", 0, 0, &umr_bitfield_default },
	 { "DPHY_SW_FAST_TRAINING_START", 1, 1, &umr_bitfield_default },
	 { "DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN", 2, 2, &umr_bitfield_default },
	 { "DPHY_FAST_TRAINING_TP1_TIME", 8, 19, &umr_bitfield_default },
	 { "DPHY_FAST_TRAINING_TP2_TIME", 20, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDP2_DP_DPHY_FAST_TRAINING_STATUS[] = {
	 { "DPHY_FAST_TRAINING_STATE", 0, 2, &umr_bitfield_default },
	 { "DPHY_FAST_TRAINING_COMPLETE_OCCURRED", 4, 4, &umr_bitfield_default },
	 { "DPHY_FAST_TRAINING_COMPLETE_MASK", 8, 8, &umr_bitfield_default },
	 { "DPHY_FAST_TRAINING_COMPLETE_ACK", 12, 12, &umr_bitfield_default },
};
static struct umr_bitfield mmDP2_DP_SEC_CNTL[] = {
	 { "DP_SEC_STREAM_ENABLE", 0, 0, &umr_bitfield_default },
	 { "DP_SEC_ASP_ENABLE", 4, 4, &umr_bitfield_default },
	 { "DP_SEC_ATP_ENABLE", 8, 8, &umr_bitfield_default },
	 { "DP_SEC_AIP_ENABLE", 12, 12, &umr_bitfield_default },
	 { "DP_SEC_ACM_ENABLE", 16, 16, &umr_bitfield_default },
	 { "DP_SEC_GSP0_ENABLE", 20, 20, &umr_bitfield_default },
	 { "DP_SEC_GSP1_ENABLE", 21, 21, &umr_bitfield_default },
	 { "DP_SEC_GSP2_ENABLE", 22, 22, &umr_bitfield_default },
	 { "DP_SEC_GSP3_ENABLE", 23, 23, &umr_bitfield_default },
	 { "DP_SEC_GSP4_ENABLE", 24, 24, &umr_bitfield_default },
	 { "DP_SEC_GSP5_ENABLE", 25, 25, &umr_bitfield_default },
	 { "DP_SEC_GSP6_ENABLE", 26, 26, &umr_bitfield_default },
	 { "DP_SEC_GSP7_ENABLE", 27, 27, &umr_bitfield_default },
	 { "DP_SEC_MPG_ENABLE", 28, 28, &umr_bitfield_default },
};
static struct umr_bitfield mmDP2_DP_SEC_CNTL1[] = {
	 { "DP_SEC_ISRC_ENABLE", 0, 0, &umr_bitfield_default },
	 { "DP_SEC_GSP0_PRIORITY", 4, 4, &umr_bitfield_default },
	 { "DP_SEC_GSP0_SEND", 5, 5, &umr_bitfield_default },
	 { "DP_SEC_GSP0_SEND_PENDING", 6, 6, &umr_bitfield_default },
	 { "DP_SEC_GSP0_SEND_DEADLINE_MISSED", 7, 7, &umr_bitfield_default },
	 { "DP_SEC_GSP0_SEND_ANY_LINE", 8, 8, &umr_bitfield_default },
	 { "DP_SEC_GSP0_LINE_NUM", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDP2_DP_SEC_FRAMING1[] = {
	 { "DP_SEC_FRAME_START_LOCATION", 0, 11, &umr_bitfield_default },
	 { "DP_SEC_VBLANK_TRANSMIT_WIDTH", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDP2_DP_SEC_FRAMING2[] = {
	 { "DP_SEC_START_POSITION", 0, 15, &umr_bitfield_default },
	 { "DP_SEC_HBLANK_TRANSMIT_WIDTH", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDP2_DP_SEC_FRAMING3[] = {
	 { "DP_SEC_IDLE_FRAME_SIZE", 0, 13, &umr_bitfield_default },
	 { "DP_SEC_IDLE_TRANSMIT_WIDTH", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDP2_DP_SEC_FRAMING4[] = {
	 { "DP_SEC_COLLISION_STATUS", 20, 20, &umr_bitfield_default },
	 { "DP_SEC_COLLISION_ACK", 24, 24, &umr_bitfield_default },
	 { "DP_SEC_AUDIO_MUTE", 28, 28, &umr_bitfield_default },
	 { "DP_SEC_AUDIO_MUTE_STATUS", 29, 29, &umr_bitfield_default },
};
static struct umr_bitfield mmDP2_DP_SEC_AUD_N[] = {
	 { "DP_SEC_AUD_N", 0, 23, &umr_bitfield_default },
};
static struct umr_bitfield mmDP2_DP_SEC_AUD_N_READBACK[] = {
	 { "DP_SEC_AUD_N_READBACK", 0, 23, &umr_bitfield_default },
};
static struct umr_bitfield mmDP2_DP_SEC_AUD_M[] = {
	 { "DP_SEC_AUD_M", 0, 23, &umr_bitfield_default },
};
static struct umr_bitfield mmDP2_DP_SEC_AUD_M_READBACK[] = {
	 { "DP_SEC_AUD_M_READBACK", 0, 23, &umr_bitfield_default },
};
static struct umr_bitfield mmDP2_DP_SEC_TIMESTAMP[] = {
	 { "DP_SEC_TIMESTAMP_MODE", 0, 0, &umr_bitfield_default },
};
static struct umr_bitfield mmDP2_DP_SEC_PACKET_CNTL[] = {
	 { "DP_SEC_ASP_CODING_TYPE", 1, 3, &umr_bitfield_default },
	 { "DP_SEC_ASP_PRIORITY", 4, 4, &umr_bitfield_default },
	 { "DP_SEC_VERSION", 8, 13, &umr_bitfield_default },
	 { "DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE", 16, 16, &umr_bitfield_default },
};
static struct umr_bitfield mmDP2_DP_MSE_RATE_CNTL[] = {
	 { "DP_MSE_RATE_Y", 0, 25, &umr_bitfield_default },
	 { "DP_MSE_RATE_X", 26, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDP2_DP_MSE_RATE_UPDATE[] = {
	 { "DP_MSE_RATE_UPDATE_PENDING", 0, 0, &umr_bitfield_default },
};
static struct umr_bitfield mmDP2_DP_MSE_SAT0[] = {
	 { "DP_MSE_SAT_SRC0", 0, 2, &umr_bitfield_default },
	 { "DP_MSE_SAT_SLOT_COUNT0", 8, 13, &umr_bitfield_default },
	 { "DP_MSE_SAT_SRC1", 16, 18, &umr_bitfield_default },
	 { "DP_MSE_SAT_SLOT_COUNT1", 24, 29, &umr_bitfield_default },
};
static struct umr_bitfield mmDP2_DP_MSE_SAT1[] = {
	 { "DP_MSE_SAT_SRC2", 0, 2, &umr_bitfield_default },
	 { "DP_MSE_SAT_SLOT_COUNT2", 8, 13, &umr_bitfield_default },
	 { "DP_MSE_SAT_SRC3", 16, 18, &umr_bitfield_default },
	 { "DP_MSE_SAT_SLOT_COUNT3", 24, 29, &umr_bitfield_default },
};
static struct umr_bitfield mmDP2_DP_MSE_SAT2[] = {
	 { "DP_MSE_SAT_SRC4", 0, 2, &umr_bitfield_default },
	 { "DP_MSE_SAT_SLOT_COUNT4", 8, 13, &umr_bitfield_default },
	 { "DP_MSE_SAT_SRC5", 16, 18, &umr_bitfield_default },
	 { "DP_MSE_SAT_SLOT_COUNT5", 24, 29, &umr_bitfield_default },
};
static struct umr_bitfield mmDP2_DP_MSE_SAT_UPDATE[] = {
	 { "DP_MSE_SAT_UPDATE", 0, 1, &umr_bitfield_default },
	 { "DP_MSE_16_MTP_KEEPOUT", 8, 8, &umr_bitfield_default },
};
static struct umr_bitfield mmDP2_DP_MSE_LINK_TIMING[] = {
	 { "DP_MSE_LINK_FRAME", 0, 9, &umr_bitfield_default },
	 { "DP_MSE_LINK_LINE", 16, 17, &umr_bitfield_default },
};
static struct umr_bitfield mmDP2_DP_MSE_MISC_CNTL[] = {
	 { "DP_MSE_BLANK_CODE", 0, 0, &umr_bitfield_default },
	 { "DP_MSE_TIMESTAMP_MODE", 4, 4, &umr_bitfield_default },
	 { "DP_MSE_ZERO_ENCODER", 8, 8, &umr_bitfield_default },
};
static struct umr_bitfield mmDP2_DP_DPHY_BS_SR_SWAP_CNTL[] = {
	 { "DPHY_LOAD_BS_COUNT", 0, 9, &umr_bitfield_default },
	 { "DPHY_BS_SR_SWAP_DONE", 15, 15, &umr_bitfield_default },
	 { "DPHY_LOAD_BS_COUNT_START", 16, 16, &umr_bitfield_default },
};
static struct umr_bitfield mmDP2_DP_DPHY_HBR2_PATTERN_CONTROL[] = {
	 { "DP_DPHY_HBR2_PATTERN_CONTROL", 0, 2, &umr_bitfield_default },
};
static struct umr_bitfield mmDP2_DP_MSE_SAT0_STATUS[] = {
	 { "DP_MSE_SAT_SRC0_STATUS", 0, 2, &umr_bitfield_default },
	 { "DP_MSE_SAT_SLOT_COUNT0_STATUS", 8, 13, &umr_bitfield_default },
	 { "DP_MSE_SAT_SRC1_STATUS", 16, 18, &umr_bitfield_default },
	 { "DP_MSE_SAT_SLOT_COUNT1_STATUS", 24, 29, &umr_bitfield_default },
};
static struct umr_bitfield mmDP2_DP_MSE_SAT1_STATUS[] = {
	 { "DP_MSE_SAT_SRC2_STATUS", 0, 2, &umr_bitfield_default },
	 { "DP_MSE_SAT_SLOT_COUNT2_STATUS", 8, 13, &umr_bitfield_default },
	 { "DP_MSE_SAT_SRC3_STATUS", 16, 18, &umr_bitfield_default },
	 { "DP_MSE_SAT_SLOT_COUNT3_STATUS", 24, 29, &umr_bitfield_default },
};
static struct umr_bitfield mmDP2_DP_MSE_SAT2_STATUS[] = {
	 { "DP_MSE_SAT_SRC4_STATUS", 0, 2, &umr_bitfield_default },
	 { "DP_MSE_SAT_SLOT_COUNT4_STATUS", 8, 13, &umr_bitfield_default },
	 { "DP_MSE_SAT_SRC5_STATUS", 16, 18, &umr_bitfield_default },
	 { "DP_MSE_SAT_SLOT_COUNT5_STATUS", 24, 29, &umr_bitfield_default },
};
static struct umr_bitfield mmDP2_DP_MSA_TIMING_PARAM1[] = {
	 { "DP_MSA_VTOTAL", 0, 15, &umr_bitfield_default },
	 { "DP_MSA_HTOTAL", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDP2_DP_MSA_TIMING_PARAM2[] = {
	 { "DP_MSA_VSTART", 0, 15, &umr_bitfield_default },
	 { "DP_MSA_HSTART", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDP2_DP_MSA_TIMING_PARAM3[] = {
	 { "DP_MSA_VSYNCWIDTH", 0, 14, &umr_bitfield_default },
	 { "DP_MSA_VSYNCPOLARITY", 15, 15, &umr_bitfield_default },
	 { "DP_MSA_HSYNCWIDTH", 16, 30, &umr_bitfield_default },
	 { "DP_MSA_HSYNCPOLARITY", 31, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDP2_DP_MSA_TIMING_PARAM4[] = {
	 { "DP_MSA_VHEIGHT", 0, 15, &umr_bitfield_default },
	 { "DP_MSA_HWIDTH", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDP2_DP_MSO_CNTL[] = {
	 { "DP_MSO_NUM_OF_SSTLINK", 0, 1, &umr_bitfield_default },
	 { "DP_MSO_SEC_STREAM_ENABLE", 4, 7, &umr_bitfield_default },
	 { "DP_MSO_SEC_ASP_ENABLE", 8, 11, &umr_bitfield_default },
	 { "DP_MSO_SEC_ATP_ENABLE", 12, 15, &umr_bitfield_default },
	 { "DP_MSO_SEC_AIP_ENABLE", 16, 19, &umr_bitfield_default },
	 { "DP_MSO_SEC_ACM_ENABLE", 20, 23, &umr_bitfield_default },
	 { "DP_MSO_SEC_GSP0_ENABLE", 24, 27, &umr_bitfield_default },
	 { "DP_MSO_SEC_GSP1_ENABLE", 28, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDP2_DP_MSO_CNTL1[] = {
	 { "DP_MSO_SEC_GSP2_ENABLE", 0, 3, &umr_bitfield_default },
	 { "DP_MSO_SEC_GSP3_ENABLE", 4, 7, &umr_bitfield_default },
	 { "DP_MSO_SEC_GSP4_ENABLE", 8, 11, &umr_bitfield_default },
	 { "DP_MSO_SEC_GSP5_ENABLE", 12, 15, &umr_bitfield_default },
	 { "DP_MSO_SEC_GSP6_ENABLE", 16, 19, &umr_bitfield_default },
	 { "DP_MSO_SEC_GSP7_ENABLE", 20, 23, &umr_bitfield_default },
	 { "DP_MSO_SEC_MPG_ENABLE", 24, 27, &umr_bitfield_default },
	 { "DP_MSO_SEC_ISRC_ENABLE", 28, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDP2_DP_DSC_CNTL[] = {
	 { "DP_DSC_EN", 0, 0, &umr_bitfield_default },
};
static struct umr_bitfield mmDP2_DP_SEC_CNTL2[] = {
	 { "DP_SEC_GSP1_SEND", 0, 0, &umr_bitfield_default },
	 { "DP_SEC_GSP1_SEND_PENDING", 1, 1, &umr_bitfield_default },
	 { "DP_SEC_GSP1_SEND_DEADLINE_MISSED", 2, 2, &umr_bitfield_default },
	 { "DP_SEC_GSP1_SEND_ANY_LINE", 3, 3, &umr_bitfield_default },
	 { "DP_SEC_GSP2_SEND", 4, 4, &umr_bitfield_default },
	 { "DP_SEC_GSP2_SEND_PENDING", 5, 5, &umr_bitfield_default },
	 { "DP_SEC_GSP2_SEND_DEADLINE_MISSED", 6, 6, &umr_bitfield_default },
	 { "DP_SEC_GSP2_SEND_ANY_LINE", 7, 7, &umr_bitfield_default },
	 { "DP_SEC_GSP3_SEND", 8, 8, &umr_bitfield_default },
	 { "DP_SEC_GSP3_SEND_PENDING", 9, 9, &umr_bitfield_default },
	 { "DP_SEC_GSP3_SEND_DEADLINE_MISSED", 10, 10, &umr_bitfield_default },
	 { "DP_SEC_GSP3_SEND_ANY_LINE", 11, 11, &umr_bitfield_default },
	 { "DP_SEC_GSP4_SEND", 12, 12, &umr_bitfield_default },
	 { "DP_SEC_GSP4_SEND_PENDING", 13, 13, &umr_bitfield_default },
	 { "DP_SEC_GSP4_SEND_DEADLINE_MISSED", 14, 14, &umr_bitfield_default },
	 { "DP_SEC_GSP4_SEND_ANY_LINE", 15, 15, &umr_bitfield_default },
	 { "DP_SEC_GSP5_SEND", 16, 16, &umr_bitfield_default },
	 { "DP_SEC_GSP5_SEND_PENDING", 17, 17, &umr_bitfield_default },
	 { "DP_SEC_GSP5_SEND_DEADLINE_MISSED", 18, 18, &umr_bitfield_default },
	 { "DP_SEC_GSP5_SEND_ANY_LINE", 19, 19, &umr_bitfield_default },
	 { "DP_SEC_GSP6_SEND", 20, 20, &umr_bitfield_default },
	 { "DP_SEC_GSP6_SEND_PENDING", 21, 21, &umr_bitfield_default },
	 { "DP_SEC_GSP6_SEND_DEADLINE_MISSED", 22, 22, &umr_bitfield_default },
	 { "DP_SEC_GSP6_SEND_ANY_LINE", 23, 23, &umr_bitfield_default },
	 { "DP_SEC_GSP7_SEND", 24, 24, &umr_bitfield_default },
	 { "DP_SEC_GSP7_SEND_PENDING", 25, 25, &umr_bitfield_default },
	 { "DP_SEC_GSP7_SEND_DEADLINE_MISSED", 26, 26, &umr_bitfield_default },
	 { "DP_SEC_GSP7_SEND_ANY_LINE", 27, 27, &umr_bitfield_default },
	 { "DP_SEC_GSP7_PPS", 28, 28, &umr_bitfield_default },
};
static struct umr_bitfield mmDP2_DP_SEC_CNTL3[] = {
	 { "DP_SEC_GSP1_LINE_NUM", 0, 15, &umr_bitfield_default },
	 { "DP_SEC_GSP2_LINE_NUM", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDP2_DP_SEC_CNTL4[] = {
	 { "DP_SEC_GSP3_LINE_NUM", 0, 15, &umr_bitfield_default },
	 { "DP_SEC_GSP4_LINE_NUM", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDP2_DP_SEC_CNTL5[] = {
	 { "DP_SEC_GSP5_LINE_NUM", 0, 15, &umr_bitfield_default },
	 { "DP_SEC_GSP6_LINE_NUM", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDP2_DP_SEC_CNTL6[] = {
	 { "DP_SEC_GSP7_LINE_NUM", 0, 15, &umr_bitfield_default },
};
static struct umr_bitfield mmDP2_DP_SEC_CNTL7[] = {
	 { "DP_SEC_GSP0_SEND_ACTIVE", 0, 0, &umr_bitfield_default },
	 { "DP_SEC_GSP1_SEND_ACTIVE", 4, 4, &umr_bitfield_default },
	 { "DP_SEC_GSP2_SEND_ACTIVE", 8, 8, &umr_bitfield_default },
	 { "DP_SEC_GSP3_SEND_ACTIVE", 12, 12, &umr_bitfield_default },
	 { "DP_SEC_GSP4_SEND_ACTIVE", 16, 16, &umr_bitfield_default },
	 { "DP_SEC_GSP5_SEND_ACTIVE", 20, 20, &umr_bitfield_default },
	 { "DP_SEC_GSP6_SEND_ACTIVE", 24, 24, &umr_bitfield_default },
	 { "DP_SEC_GSP7_SEND_ACTIVE", 28, 28, &umr_bitfield_default },
};
static struct umr_bitfield mmDP2_DP_DB_CNTL[] = {
	 { "DP_DB_PENDING", 0, 0, &umr_bitfield_default },
	 { "DP_DB_TAKEN", 4, 4, &umr_bitfield_default },
	 { "DP_DB_TAKEN_CLR", 5, 5, &umr_bitfield_default },
	 { "DP_DB_LOCK", 8, 8, &umr_bitfield_default },
	 { "DP_DB_DISABLE", 12, 12, &umr_bitfield_default },
};
static struct umr_bitfield mmDP2_DP_MSA_VBID_MISC[] = {
	 { "DP_MSA_MISC1_STEREOSYNC_OVERRIDE", 0, 1, &umr_bitfield_default },
	 { "DP_MSA_MISC1_STEREOSYNC_OVERRIDE_EN", 4, 4, &umr_bitfield_default },
	 { "DP_VBID1_OVERRIDE", 8, 8, &umr_bitfield_default },
	 { "DP_VBID2_OVERRIDE", 9, 9, &umr_bitfield_default },
	 { "DP_VBID1_OVERRIDE_EN", 12, 12, &umr_bitfield_default },
	 { "DP_VBID2_OVERRIDE_EN", 13, 13, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG3_DIG_FE_CNTL[] = {
	 { "DIG_SOURCE_SELECT", 0, 2, &umr_bitfield_default },
	 { "DIG_STEREOSYNC_SELECT", 4, 6, &umr_bitfield_default },
	 { "DIG_STEREOSYNC_GATE_EN", 8, 8, &umr_bitfield_default },
	 { "DIG_START", 10, 10, &umr_bitfield_default },
	 { "DIG_DIGITAL_BYPASS_SELECT", 12, 14, &umr_bitfield_default },
	 { "DIG_SYMCLK_FE_ON", 24, 24, &umr_bitfield_default },
	 { "TMDS_PIXEL_ENCODING", 28, 28, &umr_bitfield_default },
	 { "TMDS_COLOR_FORMAT", 30, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG3_DIG_OUTPUT_CRC_CNTL[] = {
	 { "DIG_OUTPUT_CRC_EN", 0, 0, &umr_bitfield_default },
	 { "DIG_OUTPUT_CRC_LINK_SEL", 4, 4, &umr_bitfield_default },
	 { "DIG_OUTPUT_CRC_DATA_SEL", 8, 9, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG3_DIG_OUTPUT_CRC_RESULT[] = {
	 { "DIG_OUTPUT_CRC_RESULT", 0, 29, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG3_DIG_CLOCK_PATTERN[] = {
	 { "DIG_CLOCK_PATTERN", 0, 9, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG3_DIG_TEST_PATTERN[] = {
	 { "DIG_TEST_PATTERN_OUT_EN", 0, 0, &umr_bitfield_default },
	 { "DIG_HALF_CLOCK_PATTERN_SEL", 1, 1, &umr_bitfield_default },
	 { "DIG_RANDOM_PATTERN_OUT_EN", 4, 4, &umr_bitfield_default },
	 { "DIG_RANDOM_PATTERN_RESET", 5, 5, &umr_bitfield_default },
	 { "DIG_TEST_PATTERN_EXTERNAL_RESET_EN", 6, 6, &umr_bitfield_default },
	 { "DIG_STATIC_TEST_PATTERN", 16, 25, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG3_DIG_RANDOM_PATTERN_SEED[] = {
	 { "DIG_RANDOM_PATTERN_SEED", 0, 23, &umr_bitfield_default },
	 { "DIG_RAN_PAT_DURING_DE_ONLY", 24, 24, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG3_DIG_FIFO_STATUS[] = {
	 { "DIG_FIFO_LEVEL_ERROR", 0, 0, &umr_bitfield_default },
	 { "DIG_FIFO_USE_OVERWRITE_LEVEL", 1, 1, &umr_bitfield_default },
	 { "DIG_FIFO_OVERWRITE_LEVEL", 2, 7, &umr_bitfield_default },
	 { "DIG_FIFO_ERROR_ACK", 8, 8, &umr_bitfield_default },
	 { "DIG_FIFO_CAL_AVERAGE_LEVEL", 10, 15, &umr_bitfield_default },
	 { "DIG_FIFO_MAXIMUM_LEVEL", 16, 20, &umr_bitfield_default },
	 { "DIG_FIFO_MINIMUM_LEVEL", 22, 25, &umr_bitfield_default },
	 { "DIG_FIFO_READ_CLOCK_SRC", 26, 26, &umr_bitfield_default },
	 { "DIG_FIFO_CALIBRATED", 29, 29, &umr_bitfield_default },
	 { "DIG_FIFO_FORCE_RECAL_AVERAGE", 30, 30, &umr_bitfield_default },
	 { "DIG_FIFO_FORCE_RECOMP_MINMAX", 31, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG3_HDMI_CONTROL[] = {
	 { "HDMI_KEEPOUT_MODE", 0, 0, &umr_bitfield_default },
	 { "HDMI_DATA_SCRAMBLE_EN", 1, 1, &umr_bitfield_default },
	 { "HDMI_CLOCK_CHANNEL_RATE", 2, 2, &umr_bitfield_default },
	 { "HDMI_NO_EXTRA_NULL_PACKET_FILLED", 3, 3, &umr_bitfield_default },
	 { "HDMI_PACKET_GEN_VERSION", 4, 4, &umr_bitfield_default },
	 { "HDMI_ERROR_ACK", 8, 8, &umr_bitfield_default },
	 { "HDMI_ERROR_MASK", 9, 9, &umr_bitfield_default },
	 { "HDMI_DEEP_COLOR_ENABLE", 24, 24, &umr_bitfield_default },
	 { "HDMI_DEEP_COLOR_DEPTH", 28, 29, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG3_HDMI_STATUS[] = {
	 { "HDMI_ACTIVE_AVMUTE", 0, 0, &umr_bitfield_default },
	 { "HDMI_AUDIO_PACKET_ERROR", 16, 16, &umr_bitfield_default },
	 { "HDMI_VBI_PACKET_ERROR", 20, 20, &umr_bitfield_default },
	 { "HDMI_ERROR_INT", 27, 27, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG3_HDMI_AUDIO_PACKET_CONTROL[] = {
	 { "HDMI_AUDIO_DELAY_EN", 4, 5, &umr_bitfield_default },
	 { "HDMI_AUDIO_PACKETS_PER_LINE", 16, 20, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG3_HDMI_ACR_PACKET_CONTROL[] = {
	 { "HDMI_ACR_SEND", 0, 0, &umr_bitfield_default },
	 { "HDMI_ACR_CONT", 1, 1, &umr_bitfield_default },
	 { "HDMI_ACR_SELECT", 4, 5, &umr_bitfield_default },
	 { "HDMI_ACR_SOURCE", 8, 8, &umr_bitfield_default },
	 { "HDMI_ACR_AUTO_SEND", 12, 12, &umr_bitfield_default },
	 { "HDMI_ACR_N_MULTIPLE", 16, 18, &umr_bitfield_default },
	 { "HDMI_ACR_AUDIO_PRIORITY", 31, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG3_HDMI_VBI_PACKET_CONTROL[] = {
	 { "HDMI_NULL_SEND", 0, 0, &umr_bitfield_default },
	 { "HDMI_GC_SEND", 4, 4, &umr_bitfield_default },
	 { "HDMI_GC_CONT", 5, 5, &umr_bitfield_default },
	 { "HDMI_ISRC_SEND", 8, 8, &umr_bitfield_default },
	 { "HDMI_ISRC_CONT", 9, 9, &umr_bitfield_default },
	 { "HDMI_ISRC_LINE", 16, 21, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG3_HDMI_INFOFRAME_CONTROL0[] = {
	 { "HDMI_AUDIO_INFO_SEND", 4, 4, &umr_bitfield_default },
	 { "HDMI_AUDIO_INFO_CONT", 5, 5, &umr_bitfield_default },
	 { "HDMI_MPEG_INFO_SEND", 8, 8, &umr_bitfield_default },
	 { "HDMI_MPEG_INFO_CONT", 9, 9, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG3_HDMI_INFOFRAME_CONTROL1[] = {
	 { "HDMI_AUDIO_INFO_LINE", 8, 13, &umr_bitfield_default },
	 { "HDMI_MPEG_INFO_LINE", 16, 21, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG3_HDMI_GENERIC_PACKET_CONTROL0[] = {
	 { "HDMI_GENERIC0_SEND", 0, 0, &umr_bitfield_default },
	 { "HDMI_GENERIC0_CONT", 1, 1, &umr_bitfield_default },
	 { "HDMI_GENERIC1_SEND", 4, 4, &umr_bitfield_default },
	 { "HDMI_GENERIC1_CONT", 5, 5, &umr_bitfield_default },
	 { "HDMI_GENERIC0_LINE", 16, 21, &umr_bitfield_default },
	 { "HDMI_GENERIC1_LINE", 24, 29, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG3_HDMI_GC[] = {
	 { "HDMI_GC_AVMUTE", 0, 0, &umr_bitfield_default },
	 { "HDMI_GC_AVMUTE_CONT", 2, 2, &umr_bitfield_default },
	 { "HDMI_DEFAULT_PHASE", 4, 4, &umr_bitfield_default },
	 { "HDMI_PACKING_PHASE", 8, 11, &umr_bitfield_default },
	 { "HDMI_PACKING_PHASE_OVERRIDE", 12, 12, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG3_AFMT_AUDIO_PACKET_CONTROL2[] = {
	 { "AFMT_AUDIO_LAYOUT_OVRD", 0, 0, &umr_bitfield_default },
	 { "AFMT_AUDIO_LAYOUT_SELECT", 1, 1, &umr_bitfield_default },
	 { "AFMT_AUDIO_CHANNEL_ENABLE", 8, 15, &umr_bitfield_default },
	 { "AFMT_DP_AUDIO_STREAM_ID", 16, 23, &umr_bitfield_default },
	 { "AFMT_HBR_ENABLE_OVRD", 24, 24, &umr_bitfield_default },
	 { "AFMT_60958_OSF_OVRD", 28, 28, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG3_AFMT_ISRC1_0[] = {
	 { "AFMT_ISRC_STATUS", 0, 2, &umr_bitfield_default },
	 { "AFMT_ISRC_CONTINUE", 6, 6, &umr_bitfield_default },
	 { "AFMT_ISRC_VALID", 7, 7, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG3_AFMT_ISRC1_1[] = {
	 { "AFMT_UPC_EAN_ISRC0", 0, 7, &umr_bitfield_default },
	 { "AFMT_UPC_EAN_ISRC1", 8, 15, &umr_bitfield_default },
	 { "AFMT_UPC_EAN_ISRC2", 16, 23, &umr_bitfield_default },
	 { "AFMT_UPC_EAN_ISRC3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG3_AFMT_ISRC1_2[] = {
	 { "AFMT_UPC_EAN_ISRC4", 0, 7, &umr_bitfield_default },
	 { "AFMT_UPC_EAN_ISRC5", 8, 15, &umr_bitfield_default },
	 { "AFMT_UPC_EAN_ISRC6", 16, 23, &umr_bitfield_default },
	 { "AFMT_UPC_EAN_ISRC7", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG3_AFMT_ISRC1_3[] = {
	 { "AFMT_UPC_EAN_ISRC8", 0, 7, &umr_bitfield_default },
	 { "AFMT_UPC_EAN_ISRC9", 8, 15, &umr_bitfield_default },
	 { "AFMT_UPC_EAN_ISRC10", 16, 23, &umr_bitfield_default },
	 { "AFMT_UPC_EAN_ISRC11", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG3_AFMT_ISRC1_4[] = {
	 { "AFMT_UPC_EAN_ISRC12", 0, 7, &umr_bitfield_default },
	 { "AFMT_UPC_EAN_ISRC13", 8, 15, &umr_bitfield_default },
	 { "AFMT_UPC_EAN_ISRC14", 16, 23, &umr_bitfield_default },
	 { "AFMT_UPC_EAN_ISRC15", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG3_AFMT_ISRC2_0[] = {
	 { "AFMT_UPC_EAN_ISRC16", 0, 7, &umr_bitfield_default },
	 { "AFMT_UPC_EAN_ISRC17", 8, 15, &umr_bitfield_default },
	 { "AFMT_UPC_EAN_ISRC18", 16, 23, &umr_bitfield_default },
	 { "AFMT_UPC_EAN_ISRC19", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG3_AFMT_ISRC2_1[] = {
	 { "AFMT_UPC_EAN_ISRC20", 0, 7, &umr_bitfield_default },
	 { "AFMT_UPC_EAN_ISRC21", 8, 15, &umr_bitfield_default },
	 { "AFMT_UPC_EAN_ISRC22", 16, 23, &umr_bitfield_default },
	 { "AFMT_UPC_EAN_ISRC23", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG3_AFMT_ISRC2_2[] = {
	 { "AFMT_UPC_EAN_ISRC24", 0, 7, &umr_bitfield_default },
	 { "AFMT_UPC_EAN_ISRC25", 8, 15, &umr_bitfield_default },
	 { "AFMT_UPC_EAN_ISRC26", 16, 23, &umr_bitfield_default },
	 { "AFMT_UPC_EAN_ISRC27", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG3_AFMT_ISRC2_3[] = {
	 { "AFMT_UPC_EAN_ISRC28", 0, 7, &umr_bitfield_default },
	 { "AFMT_UPC_EAN_ISRC29", 8, 15, &umr_bitfield_default },
	 { "AFMT_UPC_EAN_ISRC30", 16, 23, &umr_bitfield_default },
	 { "AFMT_UPC_EAN_ISRC31", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG3_HDMI_GENERIC_PACKET_CONTROL2[] = {
	 { "HDMI_GENERIC4_SEND", 0, 0, &umr_bitfield_default },
	 { "HDMI_GENERIC4_CONT", 1, 1, &umr_bitfield_default },
	 { "HDMI_GENERIC5_SEND", 4, 4, &umr_bitfield_default },
	 { "HDMI_GENERIC5_CONT", 5, 5, &umr_bitfield_default },
	 { "HDMI_GENERIC4_LINE", 16, 21, &umr_bitfield_default },
	 { "HDMI_GENERIC5_LINE", 24, 29, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG3_HDMI_GENERIC_PACKET_CONTROL3[] = {
	 { "HDMI_GENERIC6_SEND", 0, 0, &umr_bitfield_default },
	 { "HDMI_GENERIC6_CONT", 1, 1, &umr_bitfield_default },
	 { "HDMI_GENERIC7_SEND", 4, 4, &umr_bitfield_default },
	 { "HDMI_GENERIC7_CONT", 5, 5, &umr_bitfield_default },
	 { "HDMI_GENERIC6_LINE", 16, 21, &umr_bitfield_default },
	 { "HDMI_GENERIC7_LINE", 24, 29, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG3_HDMI_DB_CONTROL[] = {
	 { "HDMI_DB_PENDING", 0, 0, &umr_bitfield_default },
	 { "HDMI_DB_TAKEN", 4, 4, &umr_bitfield_default },
	 { "HDMI_DB_TAKEN_CLR", 5, 5, &umr_bitfield_default },
	 { "HDMI_DB_LOCK", 8, 8, &umr_bitfield_default },
	 { "HDMI_DB_DISABLE", 12, 12, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG3_AFMT_MPEG_INFO0[] = {
	 { "AFMT_MPEG_INFO_CHECKSUM", 0, 7, &umr_bitfield_default },
	 { "AFMT_MPEG_INFO_MB0", 8, 15, &umr_bitfield_default },
	 { "AFMT_MPEG_INFO_MB1", 16, 23, &umr_bitfield_default },
	 { "AFMT_MPEG_INFO_MB2", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG3_AFMT_MPEG_INFO1[] = {
	 { "AFMT_MPEG_INFO_MB3", 0, 7, &umr_bitfield_default },
	 { "AFMT_MPEG_INFO_MF", 8, 9, &umr_bitfield_default },
	 { "AFMT_MPEG_INFO_FR", 12, 12, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG3_AFMT_GENERIC_HDR[] = {
	 { "AFMT_GENERIC_HB0", 0, 7, &umr_bitfield_default },
	 { "AFMT_GENERIC_HB1", 8, 15, &umr_bitfield_default },
	 { "AFMT_GENERIC_HB2", 16, 23, &umr_bitfield_default },
	 { "AFMT_GENERIC_HB3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG3_AFMT_GENERIC_0[] = {
	 { "AFMT_GENERIC_BYTE0", 0, 7, &umr_bitfield_default },
	 { "AFMT_GENERIC_BYTE1", 8, 15, &umr_bitfield_default },
	 { "AFMT_GENERIC_BYTE2", 16, 23, &umr_bitfield_default },
	 { "AFMT_GENERIC_BYTE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG3_AFMT_GENERIC_1[] = {
	 { "AFMT_GENERIC_BYTE4", 0, 7, &umr_bitfield_default },
	 { "AFMT_GENERIC_BYTE5", 8, 15, &umr_bitfield_default },
	 { "AFMT_GENERIC_BYTE6", 16, 23, &umr_bitfield_default },
	 { "AFMT_GENERIC_BYTE7", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG3_AFMT_GENERIC_2[] = {
	 { "AFMT_GENERIC_BYTE8", 0, 7, &umr_bitfield_default },
	 { "AFMT_GENERIC_BYTE9", 8, 15, &umr_bitfield_default },
	 { "AFMT_GENERIC_BYTE10", 16, 23, &umr_bitfield_default },
	 { "AFMT_GENERIC_BYTE11", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG3_AFMT_GENERIC_3[] = {
	 { "AFMT_GENERIC_BYTE12", 0, 7, &umr_bitfield_default },
	 { "AFMT_GENERIC_BYTE13", 8, 15, &umr_bitfield_default },
	 { "AFMT_GENERIC_BYTE14", 16, 23, &umr_bitfield_default },
	 { "AFMT_GENERIC_BYTE15", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG3_AFMT_GENERIC_4[] = {
	 { "AFMT_GENERIC_BYTE16", 0, 7, &umr_bitfield_default },
	 { "AFMT_GENERIC_BYTE17", 8, 15, &umr_bitfield_default },
	 { "AFMT_GENERIC_BYTE18", 16, 23, &umr_bitfield_default },
	 { "AFMT_GENERIC_BYTE19", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG3_AFMT_GENERIC_5[] = {
	 { "AFMT_GENERIC_BYTE20", 0, 7, &umr_bitfield_default },
	 { "AFMT_GENERIC_BYTE21", 8, 15, &umr_bitfield_default },
	 { "AFMT_GENERIC_BYTE22", 16, 23, &umr_bitfield_default },
	 { "AFMT_GENERIC_BYTE23", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG3_AFMT_GENERIC_6[] = {
	 { "AFMT_GENERIC_BYTE24", 0, 7, &umr_bitfield_default },
	 { "AFMT_GENERIC_BYTE25", 8, 15, &umr_bitfield_default },
	 { "AFMT_GENERIC_BYTE26", 16, 23, &umr_bitfield_default },
	 { "AFMT_GENERIC_BYTE27", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG3_AFMT_GENERIC_7[] = {
	 { "AFMT_GENERIC_BYTE28", 0, 7, &umr_bitfield_default },
	 { "AFMT_GENERIC_BYTE29", 8, 15, &umr_bitfield_default },
	 { "AFMT_GENERIC_BYTE30", 16, 23, &umr_bitfield_default },
	 { "AFMT_GENERIC_BYTE31", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG3_HDMI_GENERIC_PACKET_CONTROL1[] = {
	 { "HDMI_GENERIC2_SEND", 0, 0, &umr_bitfield_default },
	 { "HDMI_GENERIC2_CONT", 1, 1, &umr_bitfield_default },
	 { "HDMI_GENERIC3_SEND", 4, 4, &umr_bitfield_default },
	 { "HDMI_GENERIC3_CONT", 5, 5, &umr_bitfield_default },
	 { "HDMI_GENERIC2_LINE", 16, 21, &umr_bitfield_default },
	 { "HDMI_GENERIC3_LINE", 24, 29, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG3_HDMI_ACR_32_0[] = {
	 { "HDMI_ACR_CTS_32", 12, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG3_HDMI_ACR_32_1[] = {
	 { "HDMI_ACR_N_32", 0, 19, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG3_HDMI_ACR_44_0[] = {
	 { "HDMI_ACR_CTS_44", 12, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG3_HDMI_ACR_44_1[] = {
	 { "HDMI_ACR_N_44", 0, 19, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG3_HDMI_ACR_48_0[] = {
	 { "HDMI_ACR_CTS_48", 12, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG3_HDMI_ACR_48_1[] = {
	 { "HDMI_ACR_N_48", 0, 19, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG3_HDMI_ACR_STATUS_0[] = {
	 { "HDMI_ACR_CTS", 12, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG3_HDMI_ACR_STATUS_1[] = {
	 { "HDMI_ACR_N", 0, 19, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG3_AFMT_AUDIO_INFO0[] = {
	 { "AFMT_AUDIO_INFO_CHECKSUM", 0, 7, &umr_bitfield_default },
	 { "AFMT_AUDIO_INFO_CC", 8, 10, &umr_bitfield_default },
	 { "AFMT_AUDIO_INFO_CT", 11, 14, &umr_bitfield_default },
	 { "AFMT_AUDIO_INFO_CHECKSUM_OFFSET", 16, 23, &umr_bitfield_default },
	 { "AFMT_AUDIO_INFO_CXT", 24, 28, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG3_AFMT_AUDIO_INFO1[] = {
	 { "AFMT_AUDIO_INFO_CA", 0, 7, &umr_bitfield_default },
	 { "AFMT_AUDIO_INFO_LSV", 11, 14, &umr_bitfield_default },
	 { "AFMT_AUDIO_INFO_DM_INH", 15, 15, &umr_bitfield_default },
	 { "AFMT_AUDIO_INFO_LFEPBL", 16, 17, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG3_AFMT_60958_0[] = {
	 { "AFMT_60958_CS_A", 0, 0, &umr_bitfield_default },
	 { "AFMT_60958_CS_B", 1, 1, &umr_bitfield_default },
	 { "AFMT_60958_CS_C", 2, 2, &umr_bitfield_default },
	 { "AFMT_60958_CS_D", 3, 5, &umr_bitfield_default },
	 { "AFMT_60958_CS_MODE", 6, 7, &umr_bitfield_default },
	 { "AFMT_60958_CS_CATEGORY_CODE", 8, 15, &umr_bitfield_default },
	 { "AFMT_60958_CS_SOURCE_NUMBER", 16, 19, &umr_bitfield_default },
	 { "AFMT_60958_CS_CHANNEL_NUMBER_L", 20, 23, &umr_bitfield_default },
	 { "AFMT_60958_CS_SAMPLING_FREQUENCY", 24, 27, &umr_bitfield_default },
	 { "AFMT_60958_CS_CLOCK_ACCURACY", 28, 29, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG3_AFMT_60958_1[] = {
	 { "AFMT_60958_CS_WORD_LENGTH", 0, 3, &umr_bitfield_default },
	 { "AFMT_60958_CS_ORIGINAL_SAMPLING_FREQUENCY", 4, 7, &umr_bitfield_default },
	 { "AFMT_60958_VALID_L", 16, 16, &umr_bitfield_default },
	 { "AFMT_60958_VALID_R", 18, 18, &umr_bitfield_default },
	 { "AFMT_60958_CS_CHANNEL_NUMBER_R", 20, 23, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG3_AFMT_AUDIO_CRC_CONTROL[] = {
	 { "AFMT_AUDIO_CRC_EN", 0, 0, &umr_bitfield_default },
	 { "AFMT_AUDIO_CRC_CONT", 4, 4, &umr_bitfield_default },
	 { "AFMT_AUDIO_CRC_SOURCE", 8, 8, &umr_bitfield_default },
	 { "AFMT_AUDIO_CRC_CH_SEL", 12, 15, &umr_bitfield_default },
	 { "AFMT_AUDIO_CRC_COUNT", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG3_AFMT_RAMP_CONTROL0[] = {
	 { "AFMT_RAMP_MAX_COUNT", 0, 23, &umr_bitfield_default },
	 { "AFMT_RAMP_DATA_SIGN", 31, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG3_AFMT_RAMP_CONTROL1[] = {
	 { "AFMT_RAMP_MIN_COUNT", 0, 23, &umr_bitfield_default },
	 { "AFMT_AUDIO_TEST_CH_DISABLE", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG3_AFMT_RAMP_CONTROL2[] = {
	 { "AFMT_RAMP_INC_COUNT", 0, 23, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG3_AFMT_RAMP_CONTROL3[] = {
	 { "AFMT_RAMP_DEC_COUNT", 0, 23, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG3_AFMT_60958_2[] = {
	 { "AFMT_60958_CS_CHANNEL_NUMBER_2", 0, 3, &umr_bitfield_default },
	 { "AFMT_60958_CS_CHANNEL_NUMBER_3", 4, 7, &umr_bitfield_default },
	 { "AFMT_60958_CS_CHANNEL_NUMBER_4", 8, 11, &umr_bitfield_default },
	 { "AFMT_60958_CS_CHANNEL_NUMBER_5", 12, 15, &umr_bitfield_default },
	 { "AFMT_60958_CS_CHANNEL_NUMBER_6", 16, 19, &umr_bitfield_default },
	 { "AFMT_60958_CS_CHANNEL_NUMBER_7", 20, 23, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG3_AFMT_AUDIO_CRC_RESULT[] = {
	 { "AFMT_AUDIO_CRC_DONE", 0, 0, &umr_bitfield_default },
	 { "AFMT_AUDIO_CRC", 8, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG3_AFMT_STATUS[] = {
	 { "AFMT_AUDIO_ENABLE", 4, 4, &umr_bitfield_default },
	 { "AFMT_AZ_HBR_ENABLE", 8, 8, &umr_bitfield_default },
	 { "AFMT_AUDIO_FIFO_OVERFLOW", 24, 24, &umr_bitfield_default },
	 { "AFMT_AZ_AUDIO_ENABLE_CHG", 30, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG3_AFMT_AUDIO_PACKET_CONTROL[] = {
	 { "AFMT_AUDIO_SAMPLE_SEND", 0, 0, &umr_bitfield_default },
	 { "AFMT_RESET_FIFO_WHEN_AUDIO_DIS", 11, 11, &umr_bitfield_default },
	 { "AFMT_AUDIO_TEST_EN", 12, 12, &umr_bitfield_default },
	 { "AFMT_AUDIO_TEST_MODE", 14, 14, &umr_bitfield_default },
	 { "AFMT_AUDIO_FIFO_OVERFLOW_ACK", 23, 23, &umr_bitfield_default },
	 { "AFMT_AUDIO_CHANNEL_SWAP", 24, 24, &umr_bitfield_default },
	 { "AFMT_60958_CS_UPDATE", 26, 26, &umr_bitfield_default },
	 { "AFMT_AZ_AUDIO_ENABLE_CHG_ACK", 30, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG3_AFMT_VBI_PACKET_CONTROL[] = {
	 { "AFMT_GENERIC_LOCK_STATUS", 8, 8, &umr_bitfield_default },
	 { "AFMT_GENERIC_CONFLICT", 16, 16, &umr_bitfield_default },
	 { "AFMT_GENERIC_CONFLICT_CLR", 17, 17, &umr_bitfield_default },
	 { "AFMT_GENERIC_INDEX", 28, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG3_AFMT_INFOFRAME_CONTROL0[] = {
	 { "AFMT_AUDIO_INFO_SOURCE", 6, 6, &umr_bitfield_default },
	 { "AFMT_AUDIO_INFO_UPDATE", 7, 7, &umr_bitfield_default },
	 { "AFMT_MPEG_INFO_UPDATE", 10, 10, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG3_AFMT_AUDIO_SRC_CONTROL[] = {
	 { "AFMT_AUDIO_SRC_SELECT", 0, 2, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG3_DIG_BE_CNTL[] = {
	 { "DIG_DUAL_LINK_ENABLE", 0, 0, &umr_bitfield_default },
	 { "DIG_SWAP", 1, 1, &umr_bitfield_default },
	 { "DIG_FE_SOURCE_SELECT", 8, 14, &umr_bitfield_default },
	 { "DIG_MODE", 16, 18, &umr_bitfield_default },
	 { "DIG_HPD_SELECT", 28, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG3_DIG_BE_EN_CNTL[] = {
	 { "DIG_ENABLE", 0, 0, &umr_bitfield_default },
	 { "DIG_SYMCLK_BE_ON", 8, 8, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG3_TMDS_CNTL[] = {
	 { "TMDS_SYNC_PHASE", 0, 0, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG3_TMDS_CONTROL_CHAR[] = {
	 { "TMDS_CONTROL_CHAR0_OUT_EN", 0, 0, &umr_bitfield_default },
	 { "TMDS_CONTROL_CHAR1_OUT_EN", 1, 1, &umr_bitfield_default },
	 { "TMDS_CONTROL_CHAR2_OUT_EN", 2, 2, &umr_bitfield_default },
	 { "TMDS_CONTROL_CHAR3_OUT_EN", 3, 3, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG3_TMDS_CONTROL0_FEEDBACK[] = {
	 { "TMDS_CONTROL0_FEEDBACK_SELECT", 0, 1, &umr_bitfield_default },
	 { "TMDS_CONTROL0_FEEDBACK_DELAY", 8, 9, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG3_TMDS_STEREOSYNC_CTL_SEL[] = {
	 { "TMDS_STEREOSYNC_CTL_SEL", 0, 1, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG3_TMDS_SYNC_CHAR_PATTERN_0_1[] = {
	 { "TMDS_SYNC_CHAR_PATTERN0", 0, 9, &umr_bitfield_default },
	 { "TMDS_SYNC_CHAR_PATTERN1", 16, 25, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG3_TMDS_SYNC_CHAR_PATTERN_2_3[] = {
	 { "TMDS_SYNC_CHAR_PATTERN2", 0, 9, &umr_bitfield_default },
	 { "TMDS_SYNC_CHAR_PATTERN3", 16, 25, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG3_TMDS_CTL_BITS[] = {
	 { "TMDS_CTL0", 0, 0, &umr_bitfield_default },
	 { "TMDS_CTL1", 8, 8, &umr_bitfield_default },
	 { "TMDS_CTL2", 16, 16, &umr_bitfield_default },
	 { "TMDS_CTL3", 24, 24, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG3_TMDS_DCBALANCER_CONTROL[] = {
	 { "TMDS_DCBALANCER_EN", 0, 0, &umr_bitfield_default },
	 { "TMDS_DCBALANCER_TEST_EN", 8, 8, &umr_bitfield_default },
	 { "TMDS_DCBALANCER_TEST_IN", 16, 19, &umr_bitfield_default },
	 { "TMDS_DCBALANCER_FORCE", 24, 24, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG3_TMDS_CTL0_1_GEN_CNTL[] = {
	 { "TMDS_CTL0_DATA_SEL", 0, 3, &umr_bitfield_default },
	 { "TMDS_CTL0_DATA_DELAY", 4, 6, &umr_bitfield_default },
	 { "TMDS_CTL0_DATA_INVERT", 7, 7, &umr_bitfield_default },
	 { "TMDS_CTL0_DATA_MODULATION", 8, 9, &umr_bitfield_default },
	 { "TMDS_CTL0_USE_FEEDBACK_PATH", 10, 10, &umr_bitfield_default },
	 { "TMDS_CTL0_FB_SYNC_CONT", 11, 11, &umr_bitfield_default },
	 { "TMDS_CTL0_PATTERN_OUT_EN", 12, 12, &umr_bitfield_default },
	 { "TMDS_CTL1_DATA_SEL", 16, 19, &umr_bitfield_default },
	 { "TMDS_CTL1_DATA_DELAY", 20, 22, &umr_bitfield_default },
	 { "TMDS_CTL1_DATA_INVERT", 23, 23, &umr_bitfield_default },
	 { "TMDS_CTL1_DATA_MODULATION", 24, 25, &umr_bitfield_default },
	 { "TMDS_CTL1_USE_FEEDBACK_PATH", 26, 26, &umr_bitfield_default },
	 { "TMDS_CTL1_FB_SYNC_CONT", 27, 27, &umr_bitfield_default },
	 { "TMDS_CTL1_PATTERN_OUT_EN", 28, 28, &umr_bitfield_default },
	 { "TMDS_2BIT_COUNTER_EN", 31, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG3_TMDS_CTL2_3_GEN_CNTL[] = {
	 { "TMDS_CTL2_DATA_SEL", 0, 3, &umr_bitfield_default },
	 { "TMDS_CTL2_DATA_DELAY", 4, 6, &umr_bitfield_default },
	 { "TMDS_CTL2_DATA_INVERT", 7, 7, &umr_bitfield_default },
	 { "TMDS_CTL2_DATA_MODULATION", 8, 9, &umr_bitfield_default },
	 { "TMDS_CTL2_USE_FEEDBACK_PATH", 10, 10, &umr_bitfield_default },
	 { "TMDS_CTL2_FB_SYNC_CONT", 11, 11, &umr_bitfield_default },
	 { "TMDS_CTL2_PATTERN_OUT_EN", 12, 12, &umr_bitfield_default },
	 { "TMDS_CTL3_DATA_SEL", 16, 19, &umr_bitfield_default },
	 { "TMDS_CTL3_DATA_DELAY", 20, 22, &umr_bitfield_default },
	 { "TMDS_CTL3_DATA_INVERT", 23, 23, &umr_bitfield_default },
	 { "TMDS_CTL3_DATA_MODULATION", 24, 25, &umr_bitfield_default },
	 { "TMDS_CTL3_USE_FEEDBACK_PATH", 26, 26, &umr_bitfield_default },
	 { "TMDS_CTL3_FB_SYNC_CONT", 27, 27, &umr_bitfield_default },
	 { "TMDS_CTL3_PATTERN_OUT_EN", 28, 28, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG3_DIG_VERSION[] = {
	 { "DIG_TYPE", 0, 0, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG3_DIG_LANE_ENABLE[] = {
	 { "DIG_LANE0EN", 0, 0, &umr_bitfield_default },
	 { "DIG_LANE1EN", 1, 1, &umr_bitfield_default },
	 { "DIG_LANE2EN", 2, 2, &umr_bitfield_default },
	 { "DIG_LANE3EN", 3, 3, &umr_bitfield_default },
	 { "DIG_CLK_EN", 8, 8, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG3_AFMT_CNTL[] = {
	 { "AFMT_AUDIO_CLOCK_EN", 0, 0, &umr_bitfield_default },
	 { "AFMT_AUDIO_CLOCK_ON", 8, 8, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG3_AFMT_VBI_PACKET_CONTROL1[] = {
	 { "AFMT_GENERIC0_FRAME_UPDATE", 0, 0, &umr_bitfield_default },
	 { "AFMT_GENERIC0_FRAME_UPDATE_PENDING", 1, 1, &umr_bitfield_default },
	 { "AFMT_GENERIC0_IMMEDIATE_UPDATE", 2, 2, &umr_bitfield_default },
	 { "AFMT_GENERIC0_IMMEDIATE_UPDATE_PENDING", 3, 3, &umr_bitfield_default },
	 { "AFMT_GENERIC1_FRAME_UPDATE", 4, 4, &umr_bitfield_default },
	 { "AFMT_GENERIC1_FRAME_UPDATE_PENDING", 5, 5, &umr_bitfield_default },
	 { "AFMT_GENERIC1_IMMEDIATE_UPDATE", 6, 6, &umr_bitfield_default },
	 { "AFMT_GENERIC1_IMMEDIATE_UPDATE_PENDING", 7, 7, &umr_bitfield_default },
	 { "AFMT_GENERIC2_FRAME_UPDATE", 8, 8, &umr_bitfield_default },
	 { "AFMT_GENERIC2_FRAME_UPDATE_PENDING", 9, 9, &umr_bitfield_default },
	 { "AFMT_GENERIC2_IMMEDIATE_UPDATE", 10, 10, &umr_bitfield_default },
	 { "AFMT_GENERIC2_IMMEDIATE_UPDATE_PENDING", 11, 11, &umr_bitfield_default },
	 { "AFMT_GENERIC3_FRAME_UPDATE", 12, 12, &umr_bitfield_default },
	 { "AFMT_GENERIC3_FRAME_UPDATE_PENDING", 13, 13, &umr_bitfield_default },
	 { "AFMT_GENERIC3_IMMEDIATE_UPDATE", 14, 14, &umr_bitfield_default },
	 { "AFMT_GENERIC3_IMMEDIATE_UPDATE_PENDING", 15, 15, &umr_bitfield_default },
	 { "AFMT_GENERIC4_FRAME_UPDATE", 16, 16, &umr_bitfield_default },
	 { "AFMT_GENERIC4_FRAME_UPDATE_PENDING", 17, 17, &umr_bitfield_default },
	 { "AFMT_GENERIC4_IMMEDIATE_UPDATE", 18, 18, &umr_bitfield_default },
	 { "AFMT_GENERIC4_IMMEDIATE_UPDATE_PENDING", 19, 19, &umr_bitfield_default },
	 { "AFMT_GENERIC5_FRAME_UPDATE", 20, 20, &umr_bitfield_default },
	 { "AFMT_GENERIC5_FRAME_UPDATE_PENDING", 21, 21, &umr_bitfield_default },
	 { "AFMT_GENERIC5_IMMEDIATE_UPDATE", 22, 22, &umr_bitfield_default },
	 { "AFMT_GENERIC5_IMMEDIATE_UPDATE_PENDING", 23, 23, &umr_bitfield_default },
	 { "AFMT_GENERIC6_FRAME_UPDATE", 24, 24, &umr_bitfield_default },
	 { "AFMT_GENERIC6_FRAME_UPDATE_PENDING", 25, 25, &umr_bitfield_default },
	 { "AFMT_GENERIC6_IMMEDIATE_UPDATE", 26, 26, &umr_bitfield_default },
	 { "AFMT_GENERIC6_IMMEDIATE_UPDATE_PENDING", 27, 27, &umr_bitfield_default },
	 { "AFMT_GENERIC7_FRAME_UPDATE", 28, 28, &umr_bitfield_default },
	 { "AFMT_GENERIC7_FRAME_UPDATE_PENDING", 29, 29, &umr_bitfield_default },
	 { "AFMT_GENERIC7_IMMEDIATE_UPDATE", 30, 30, &umr_bitfield_default },
	 { "AFMT_GENERIC7_IMMEDIATE_UPDATE_PENDING", 31, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDP3_DP_LINK_CNTL[] = {
	 { "DP_LINK_TRAINING_COMPLETE", 4, 4, &umr_bitfield_default },
	 { "DP_LINK_STATUS", 8, 8, &umr_bitfield_default },
	 { "DP_EMBEDDED_PANEL_MODE", 17, 17, &umr_bitfield_default },
};
static struct umr_bitfield mmDP3_DP_PIXEL_FORMAT[] = {
	 { "DP_PIXEL_ENCODING", 0, 2, &umr_bitfield_default },
	 { "DP_COMPONENT_DEPTH", 24, 26, &umr_bitfield_default },
	 { "DP_PIXEL_COMBINE", 28, 29, &umr_bitfield_default },
};
static struct umr_bitfield mmDP3_DP_MSA_COLORIMETRY[] = {
	 { "DP_MSA_MISC0", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDP3_DP_CONFIG[] = {
	 { "DP_UDI_LANES", 0, 1, &umr_bitfield_default },
};
static struct umr_bitfield mmDP3_DP_VID_STREAM_CNTL[] = {
	 { "DP_VID_STREAM_ENABLE", 0, 0, &umr_bitfield_default },
	 { "DP_VID_STREAM_DIS_DEFER", 8, 9, &umr_bitfield_default },
	 { "DP_VID_STREAM_STATUS", 16, 16, &umr_bitfield_default },
	 { "DP_VID_STREAM_CHANGE_KEEPOUT", 20, 20, &umr_bitfield_default },
};
static struct umr_bitfield mmDP3_DP_STEER_FIFO[] = {
	 { "DP_STEER_FIFO_RESET", 0, 0, &umr_bitfield_default },
	 { "DP_STEER_OVERFLOW_FLAG", 4, 4, &umr_bitfield_default },
	 { "DP_STEER_OVERFLOW_INT", 5, 5, &umr_bitfield_default },
	 { "DP_STEER_OVERFLOW_ACK", 6, 6, &umr_bitfield_default },
	 { "DP_STEER_OVERFLOW_MASK", 7, 7, &umr_bitfield_default },
	 { "DP_TU_OVERFLOW_FLAG", 8, 8, &umr_bitfield_default },
	 { "DP_TU_OVERFLOW_ACK", 12, 12, &umr_bitfield_default },
};
static struct umr_bitfield mmDP3_DP_MSA_MISC[] = {
	 { "DP_MSA_MISC1", 0, 7, &umr_bitfield_default },
	 { "DP_MSA_MISC2", 8, 15, &umr_bitfield_default },
	 { "DP_MSA_MISC3", 16, 23, &umr_bitfield_default },
	 { "DP_MSA_MISC4", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDP3_DP_VID_TIMING[] = {
	 { "DP_VID_M_N_DOUBLE_BUFFER_MODE", 4, 4, &umr_bitfield_default },
	 { "DP_VID_M_N_GEN_EN", 8, 8, &umr_bitfield_default },
	 { "DP_VID_N_MUL", 10, 11, &umr_bitfield_default },
	 { "DP_VID_M_DIV", 12, 13, &umr_bitfield_default },
	 { "DP_VID_N_DIV", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDP3_DP_VID_N[] = {
	 { "DP_VID_N", 0, 23, &umr_bitfield_default },
};
static struct umr_bitfield mmDP3_DP_VID_M[] = {
	 { "DP_VID_M", 0, 23, &umr_bitfield_default },
};
static struct umr_bitfield mmDP3_DP_LINK_FRAMING_CNTL[] = {
	 { "DP_IDLE_BS_INTERVAL", 0, 17, &umr_bitfield_default },
	 { "DP_VBID_DISABLE", 24, 24, &umr_bitfield_default },
	 { "DP_VID_ENHANCED_FRAME_MODE", 28, 28, &umr_bitfield_default },
};
static struct umr_bitfield mmDP3_DP_HBR2_EYE_PATTERN[] = {
	 { "DP_HBR2_EYE_PATTERN_ENABLE", 0, 0, &umr_bitfield_default },
};
static struct umr_bitfield mmDP3_DP_VID_MSA_VBID[] = {
	 { "DP_VID_MSA_LOCATION", 0, 11, &umr_bitfield_default },
	 { "DP_VID_VBID_FIELD_POL", 24, 24, &umr_bitfield_default },
};
static struct umr_bitfield mmDP3_DP_VID_INTERRUPT_CNTL[] = {
	 { "DP_VID_STREAM_DISABLE_INT", 0, 0, &umr_bitfield_default },
	 { "DP_VID_STREAM_DISABLE_ACK", 1, 1, &umr_bitfield_default },
	 { "DP_VID_STREAM_DISABLE_MASK", 2, 2, &umr_bitfield_default },
};
static struct umr_bitfield mmDP3_DP_DPHY_CNTL[] = {
	 { "DPHY_ATEST_SEL_LANE0", 0, 0, &umr_bitfield_default },
	 { "DPHY_ATEST_SEL_LANE1", 1, 1, &umr_bitfield_default },
	 { "DPHY_ATEST_SEL_LANE2", 2, 2, &umr_bitfield_default },
	 { "DPHY_ATEST_SEL_LANE3", 3, 3, &umr_bitfield_default },
	 { "DPHY_BYPASS", 16, 16, &umr_bitfield_default },
	 { "DPHY_SKEW_BYPASS", 24, 24, &umr_bitfield_default },
};
static struct umr_bitfield mmDP3_DP_DPHY_TRAINING_PATTERN_SEL[] = {
	 { "DPHY_TRAINING_PATTERN_SEL", 0, 1, &umr_bitfield_default },
};
static struct umr_bitfield mmDP3_DP_DPHY_SYM0[] = {
	 { "DPHY_SYM1", 0, 9, &umr_bitfield_default },
	 { "DPHY_SYM2", 10, 19, &umr_bitfield_default },
	 { "DPHY_SYM3", 20, 29, &umr_bitfield_default },
};
static struct umr_bitfield mmDP3_DP_DPHY_SYM1[] = {
	 { "DPHY_SYM4", 0, 9, &umr_bitfield_default },
	 { "DPHY_SYM5", 10, 19, &umr_bitfield_default },
	 { "DPHY_SYM6", 20, 29, &umr_bitfield_default },
};
static struct umr_bitfield mmDP3_DP_DPHY_SYM2[] = {
	 { "DPHY_SYM7", 0, 9, &umr_bitfield_default },
	 { "DPHY_SYM8", 10, 19, &umr_bitfield_default },
};
static struct umr_bitfield mmDP3_DP_DPHY_8B10B_CNTL[] = {
	 { "DPHY_8B10B_RESET", 8, 8, &umr_bitfield_default },
	 { "DPHY_8B10B_EXT_DISP", 16, 16, &umr_bitfield_default },
	 { "DPHY_8B10B_CUR_DISP", 24, 24, &umr_bitfield_default },
};
static struct umr_bitfield mmDP3_DP_DPHY_PRBS_CNTL[] = {
	 { "DPHY_PRBS_EN", 0, 0, &umr_bitfield_default },
	 { "DPHY_PRBS_SEL", 4, 5, &umr_bitfield_default },
	 { "DPHY_PRBS_SEED", 8, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmDP3_DP_DPHY_SCRAM_CNTL[] = {
	 { "DPHY_SCRAMBLER_DIS", 0, 0, &umr_bitfield_default },
	 { "DPHY_SCRAMBLER_ADVANCE", 4, 4, &umr_bitfield_default },
	 { "DPHY_SCRAMBLER_BS_COUNT", 8, 17, &umr_bitfield_default },
	 { "DPHY_SCRAMBLER_KCODE", 24, 24, &umr_bitfield_default },
};
static struct umr_bitfield mmDP3_DP_DPHY_CRC_EN[] = {
	 { "DPHY_CRC_EN", 0, 0, &umr_bitfield_default },
	 { "DPHY_CRC_CONT_EN", 4, 4, &umr_bitfield_default },
	 { "DPHY_CRC_RESULT_VALID", 8, 8, &umr_bitfield_default },
};
static struct umr_bitfield mmDP3_DP_DPHY_CRC_CNTL[] = {
	 { "DPHY_CRC_FIELD", 0, 0, &umr_bitfield_default },
	 { "DPHY_CRC_SEL", 4, 5, &umr_bitfield_default },
	 { "DPHY_CRC_MASK", 16, 23, &umr_bitfield_default },
};
static struct umr_bitfield mmDP3_DP_DPHY_CRC_RESULT[] = {
	 { "DPHY_CRC_RESULT", 0, 7, &umr_bitfield_default },
	 { "DPHY_CRC_RESULT1", 8, 15, &umr_bitfield_default },
	 { "DPHY_CRC_RESULT2", 16, 23, &umr_bitfield_default },
	 { "DPHY_CRC_RESULT3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDP3_DP_DPHY_CRC_MST_CNTL[] = {
	 { "DPHY_CRC_MST_FIRST_SLOT", 0, 5, &umr_bitfield_default },
	 { "DPHY_CRC_MST_LAST_SLOT", 8, 13, &umr_bitfield_default },
};
static struct umr_bitfield mmDP3_DP_DPHY_CRC_MST_STATUS[] = {
	 { "DPHY_CRC_MST_PHASE_LOCK", 0, 0, &umr_bitfield_default },
	 { "DPHY_CRC_MST_PHASE_ERROR", 8, 8, &umr_bitfield_default },
	 { "DPHY_CRC_MST_PHASE_ERROR_ACK", 16, 16, &umr_bitfield_default },
};
static struct umr_bitfield mmDP3_DP_DPHY_FAST_TRAINING[] = {
	 { "DPHY_RX_FAST_TRAINING_CAPABLE", 0, 0, &umr_bitfield_default },
	 { "DPHY_SW_FAST_TRAINING_START", 1, 1, &umr_bitfield_default },
	 { "DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN", 2, 2, &umr_bitfield_default },
	 { "DPHY_FAST_TRAINING_TP1_TIME", 8, 19, &umr_bitfield_default },
	 { "DPHY_FAST_TRAINING_TP2_TIME", 20, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDP3_DP_DPHY_FAST_TRAINING_STATUS[] = {
	 { "DPHY_FAST_TRAINING_STATE", 0, 2, &umr_bitfield_default },
	 { "DPHY_FAST_TRAINING_COMPLETE_OCCURRED", 4, 4, &umr_bitfield_default },
	 { "DPHY_FAST_TRAINING_COMPLETE_MASK", 8, 8, &umr_bitfield_default },
	 { "DPHY_FAST_TRAINING_COMPLETE_ACK", 12, 12, &umr_bitfield_default },
};
static struct umr_bitfield mmDP3_DP_SEC_CNTL[] = {
	 { "DP_SEC_STREAM_ENABLE", 0, 0, &umr_bitfield_default },
	 { "DP_SEC_ASP_ENABLE", 4, 4, &umr_bitfield_default },
	 { "DP_SEC_ATP_ENABLE", 8, 8, &umr_bitfield_default },
	 { "DP_SEC_AIP_ENABLE", 12, 12, &umr_bitfield_default },
	 { "DP_SEC_ACM_ENABLE", 16, 16, &umr_bitfield_default },
	 { "DP_SEC_GSP0_ENABLE", 20, 20, &umr_bitfield_default },
	 { "DP_SEC_GSP1_ENABLE", 21, 21, &umr_bitfield_default },
	 { "DP_SEC_GSP2_ENABLE", 22, 22, &umr_bitfield_default },
	 { "DP_SEC_GSP3_ENABLE", 23, 23, &umr_bitfield_default },
	 { "DP_SEC_GSP4_ENABLE", 24, 24, &umr_bitfield_default },
	 { "DP_SEC_GSP5_ENABLE", 25, 25, &umr_bitfield_default },
	 { "DP_SEC_GSP6_ENABLE", 26, 26, &umr_bitfield_default },
	 { "DP_SEC_GSP7_ENABLE", 27, 27, &umr_bitfield_default },
	 { "DP_SEC_MPG_ENABLE", 28, 28, &umr_bitfield_default },
};
static struct umr_bitfield mmDP3_DP_SEC_CNTL1[] = {
	 { "DP_SEC_ISRC_ENABLE", 0, 0, &umr_bitfield_default },
	 { "DP_SEC_GSP0_PRIORITY", 4, 4, &umr_bitfield_default },
	 { "DP_SEC_GSP0_SEND", 5, 5, &umr_bitfield_default },
	 { "DP_SEC_GSP0_SEND_PENDING", 6, 6, &umr_bitfield_default },
	 { "DP_SEC_GSP0_SEND_DEADLINE_MISSED", 7, 7, &umr_bitfield_default },
	 { "DP_SEC_GSP0_SEND_ANY_LINE", 8, 8, &umr_bitfield_default },
	 { "DP_SEC_GSP0_LINE_NUM", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDP3_DP_SEC_FRAMING1[] = {
	 { "DP_SEC_FRAME_START_LOCATION", 0, 11, &umr_bitfield_default },
	 { "DP_SEC_VBLANK_TRANSMIT_WIDTH", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDP3_DP_SEC_FRAMING2[] = {
	 { "DP_SEC_START_POSITION", 0, 15, &umr_bitfield_default },
	 { "DP_SEC_HBLANK_TRANSMIT_WIDTH", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDP3_DP_SEC_FRAMING3[] = {
	 { "DP_SEC_IDLE_FRAME_SIZE", 0, 13, &umr_bitfield_default },
	 { "DP_SEC_IDLE_TRANSMIT_WIDTH", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDP3_DP_SEC_FRAMING4[] = {
	 { "DP_SEC_COLLISION_STATUS", 20, 20, &umr_bitfield_default },
	 { "DP_SEC_COLLISION_ACK", 24, 24, &umr_bitfield_default },
	 { "DP_SEC_AUDIO_MUTE", 28, 28, &umr_bitfield_default },
	 { "DP_SEC_AUDIO_MUTE_STATUS", 29, 29, &umr_bitfield_default },
};
static struct umr_bitfield mmDP3_DP_SEC_AUD_N[] = {
	 { "DP_SEC_AUD_N", 0, 23, &umr_bitfield_default },
};
static struct umr_bitfield mmDP3_DP_SEC_AUD_N_READBACK[] = {
	 { "DP_SEC_AUD_N_READBACK", 0, 23, &umr_bitfield_default },
};
static struct umr_bitfield mmDP3_DP_SEC_AUD_M[] = {
	 { "DP_SEC_AUD_M", 0, 23, &umr_bitfield_default },
};
static struct umr_bitfield mmDP3_DP_SEC_AUD_M_READBACK[] = {
	 { "DP_SEC_AUD_M_READBACK", 0, 23, &umr_bitfield_default },
};
static struct umr_bitfield mmDP3_DP_SEC_TIMESTAMP[] = {
	 { "DP_SEC_TIMESTAMP_MODE", 0, 0, &umr_bitfield_default },
};
static struct umr_bitfield mmDP3_DP_SEC_PACKET_CNTL[] = {
	 { "DP_SEC_ASP_CODING_TYPE", 1, 3, &umr_bitfield_default },
	 { "DP_SEC_ASP_PRIORITY", 4, 4, &umr_bitfield_default },
	 { "DP_SEC_VERSION", 8, 13, &umr_bitfield_default },
	 { "DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE", 16, 16, &umr_bitfield_default },
};
static struct umr_bitfield mmDP3_DP_MSE_RATE_CNTL[] = {
	 { "DP_MSE_RATE_Y", 0, 25, &umr_bitfield_default },
	 { "DP_MSE_RATE_X", 26, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDP3_DP_MSE_RATE_UPDATE[] = {
	 { "DP_MSE_RATE_UPDATE_PENDING", 0, 0, &umr_bitfield_default },
};
static struct umr_bitfield mmDP3_DP_MSE_SAT0[] = {
	 { "DP_MSE_SAT_SRC0", 0, 2, &umr_bitfield_default },
	 { "DP_MSE_SAT_SLOT_COUNT0", 8, 13, &umr_bitfield_default },
	 { "DP_MSE_SAT_SRC1", 16, 18, &umr_bitfield_default },
	 { "DP_MSE_SAT_SLOT_COUNT1", 24, 29, &umr_bitfield_default },
};
static struct umr_bitfield mmDP3_DP_MSE_SAT1[] = {
	 { "DP_MSE_SAT_SRC2", 0, 2, &umr_bitfield_default },
	 { "DP_MSE_SAT_SLOT_COUNT2", 8, 13, &umr_bitfield_default },
	 { "DP_MSE_SAT_SRC3", 16, 18, &umr_bitfield_default },
	 { "DP_MSE_SAT_SLOT_COUNT3", 24, 29, &umr_bitfield_default },
};
static struct umr_bitfield mmDP3_DP_MSE_SAT2[] = {
	 { "DP_MSE_SAT_SRC4", 0, 2, &umr_bitfield_default },
	 { "DP_MSE_SAT_SLOT_COUNT4", 8, 13, &umr_bitfield_default },
	 { "DP_MSE_SAT_SRC5", 16, 18, &umr_bitfield_default },
	 { "DP_MSE_SAT_SLOT_COUNT5", 24, 29, &umr_bitfield_default },
};
static struct umr_bitfield mmDP3_DP_MSE_SAT_UPDATE[] = {
	 { "DP_MSE_SAT_UPDATE", 0, 1, &umr_bitfield_default },
	 { "DP_MSE_16_MTP_KEEPOUT", 8, 8, &umr_bitfield_default },
};
static struct umr_bitfield mmDP3_DP_MSE_LINK_TIMING[] = {
	 { "DP_MSE_LINK_FRAME", 0, 9, &umr_bitfield_default },
	 { "DP_MSE_LINK_LINE", 16, 17, &umr_bitfield_default },
};
static struct umr_bitfield mmDP3_DP_MSE_MISC_CNTL[] = {
	 { "DP_MSE_BLANK_CODE", 0, 0, &umr_bitfield_default },
	 { "DP_MSE_TIMESTAMP_MODE", 4, 4, &umr_bitfield_default },
	 { "DP_MSE_ZERO_ENCODER", 8, 8, &umr_bitfield_default },
};
static struct umr_bitfield mmDP3_DP_DPHY_BS_SR_SWAP_CNTL[] = {
	 { "DPHY_LOAD_BS_COUNT", 0, 9, &umr_bitfield_default },
	 { "DPHY_BS_SR_SWAP_DONE", 15, 15, &umr_bitfield_default },
	 { "DPHY_LOAD_BS_COUNT_START", 16, 16, &umr_bitfield_default },
};
static struct umr_bitfield mmDP3_DP_DPHY_HBR2_PATTERN_CONTROL[] = {
	 { "DP_DPHY_HBR2_PATTERN_CONTROL", 0, 2, &umr_bitfield_default },
};
static struct umr_bitfield mmDP3_DP_MSE_SAT0_STATUS[] = {
	 { "DP_MSE_SAT_SRC0_STATUS", 0, 2, &umr_bitfield_default },
	 { "DP_MSE_SAT_SLOT_COUNT0_STATUS", 8, 13, &umr_bitfield_default },
	 { "DP_MSE_SAT_SRC1_STATUS", 16, 18, &umr_bitfield_default },
	 { "DP_MSE_SAT_SLOT_COUNT1_STATUS", 24, 29, &umr_bitfield_default },
};
static struct umr_bitfield mmDP3_DP_MSE_SAT1_STATUS[] = {
	 { "DP_MSE_SAT_SRC2_STATUS", 0, 2, &umr_bitfield_default },
	 { "DP_MSE_SAT_SLOT_COUNT2_STATUS", 8, 13, &umr_bitfield_default },
	 { "DP_MSE_SAT_SRC3_STATUS", 16, 18, &umr_bitfield_default },
	 { "DP_MSE_SAT_SLOT_COUNT3_STATUS", 24, 29, &umr_bitfield_default },
};
static struct umr_bitfield mmDP3_DP_MSE_SAT2_STATUS[] = {
	 { "DP_MSE_SAT_SRC4_STATUS", 0, 2, &umr_bitfield_default },
	 { "DP_MSE_SAT_SLOT_COUNT4_STATUS", 8, 13, &umr_bitfield_default },
	 { "DP_MSE_SAT_SRC5_STATUS", 16, 18, &umr_bitfield_default },
	 { "DP_MSE_SAT_SLOT_COUNT5_STATUS", 24, 29, &umr_bitfield_default },
};
static struct umr_bitfield mmDP3_DP_MSA_TIMING_PARAM1[] = {
	 { "DP_MSA_VTOTAL", 0, 15, &umr_bitfield_default },
	 { "DP_MSA_HTOTAL", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDP3_DP_MSA_TIMING_PARAM2[] = {
	 { "DP_MSA_VSTART", 0, 15, &umr_bitfield_default },
	 { "DP_MSA_HSTART", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDP3_DP_MSA_TIMING_PARAM3[] = {
	 { "DP_MSA_VSYNCWIDTH", 0, 14, &umr_bitfield_default },
	 { "DP_MSA_VSYNCPOLARITY", 15, 15, &umr_bitfield_default },
	 { "DP_MSA_HSYNCWIDTH", 16, 30, &umr_bitfield_default },
	 { "DP_MSA_HSYNCPOLARITY", 31, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDP3_DP_MSA_TIMING_PARAM4[] = {
	 { "DP_MSA_VHEIGHT", 0, 15, &umr_bitfield_default },
	 { "DP_MSA_HWIDTH", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDP3_DP_MSO_CNTL[] = {
	 { "DP_MSO_NUM_OF_SSTLINK", 0, 1, &umr_bitfield_default },
	 { "DP_MSO_SEC_STREAM_ENABLE", 4, 7, &umr_bitfield_default },
	 { "DP_MSO_SEC_ASP_ENABLE", 8, 11, &umr_bitfield_default },
	 { "DP_MSO_SEC_ATP_ENABLE", 12, 15, &umr_bitfield_default },
	 { "DP_MSO_SEC_AIP_ENABLE", 16, 19, &umr_bitfield_default },
	 { "DP_MSO_SEC_ACM_ENABLE", 20, 23, &umr_bitfield_default },
	 { "DP_MSO_SEC_GSP0_ENABLE", 24, 27, &umr_bitfield_default },
	 { "DP_MSO_SEC_GSP1_ENABLE", 28, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDP3_DP_MSO_CNTL1[] = {
	 { "DP_MSO_SEC_GSP2_ENABLE", 0, 3, &umr_bitfield_default },
	 { "DP_MSO_SEC_GSP3_ENABLE", 4, 7, &umr_bitfield_default },
	 { "DP_MSO_SEC_GSP4_ENABLE", 8, 11, &umr_bitfield_default },
	 { "DP_MSO_SEC_GSP5_ENABLE", 12, 15, &umr_bitfield_default },
	 { "DP_MSO_SEC_GSP6_ENABLE", 16, 19, &umr_bitfield_default },
	 { "DP_MSO_SEC_GSP7_ENABLE", 20, 23, &umr_bitfield_default },
	 { "DP_MSO_SEC_MPG_ENABLE", 24, 27, &umr_bitfield_default },
	 { "DP_MSO_SEC_ISRC_ENABLE", 28, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDP3_DP_DSC_CNTL[] = {
	 { "DP_DSC_EN", 0, 0, &umr_bitfield_default },
};
static struct umr_bitfield mmDP3_DP_SEC_CNTL2[] = {
	 { "DP_SEC_GSP1_SEND", 0, 0, &umr_bitfield_default },
	 { "DP_SEC_GSP1_SEND_PENDING", 1, 1, &umr_bitfield_default },
	 { "DP_SEC_GSP1_SEND_DEADLINE_MISSED", 2, 2, &umr_bitfield_default },
	 { "DP_SEC_GSP1_SEND_ANY_LINE", 3, 3, &umr_bitfield_default },
	 { "DP_SEC_GSP2_SEND", 4, 4, &umr_bitfield_default },
	 { "DP_SEC_GSP2_SEND_PENDING", 5, 5, &umr_bitfield_default },
	 { "DP_SEC_GSP2_SEND_DEADLINE_MISSED", 6, 6, &umr_bitfield_default },
	 { "DP_SEC_GSP2_SEND_ANY_LINE", 7, 7, &umr_bitfield_default },
	 { "DP_SEC_GSP3_SEND", 8, 8, &umr_bitfield_default },
	 { "DP_SEC_GSP3_SEND_PENDING", 9, 9, &umr_bitfield_default },
	 { "DP_SEC_GSP3_SEND_DEADLINE_MISSED", 10, 10, &umr_bitfield_default },
	 { "DP_SEC_GSP3_SEND_ANY_LINE", 11, 11, &umr_bitfield_default },
	 { "DP_SEC_GSP4_SEND", 12, 12, &umr_bitfield_default },
	 { "DP_SEC_GSP4_SEND_PENDING", 13, 13, &umr_bitfield_default },
	 { "DP_SEC_GSP4_SEND_DEADLINE_MISSED", 14, 14, &umr_bitfield_default },
	 { "DP_SEC_GSP4_SEND_ANY_LINE", 15, 15, &umr_bitfield_default },
	 { "DP_SEC_GSP5_SEND", 16, 16, &umr_bitfield_default },
	 { "DP_SEC_GSP5_SEND_PENDING", 17, 17, &umr_bitfield_default },
	 { "DP_SEC_GSP5_SEND_DEADLINE_MISSED", 18, 18, &umr_bitfield_default },
	 { "DP_SEC_GSP5_SEND_ANY_LINE", 19, 19, &umr_bitfield_default },
	 { "DP_SEC_GSP6_SEND", 20, 20, &umr_bitfield_default },
	 { "DP_SEC_GSP6_SEND_PENDING", 21, 21, &umr_bitfield_default },
	 { "DP_SEC_GSP6_SEND_DEADLINE_MISSED", 22, 22, &umr_bitfield_default },
	 { "DP_SEC_GSP6_SEND_ANY_LINE", 23, 23, &umr_bitfield_default },
	 { "DP_SEC_GSP7_SEND", 24, 24, &umr_bitfield_default },
	 { "DP_SEC_GSP7_SEND_PENDING", 25, 25, &umr_bitfield_default },
	 { "DP_SEC_GSP7_SEND_DEADLINE_MISSED", 26, 26, &umr_bitfield_default },
	 { "DP_SEC_GSP7_SEND_ANY_LINE", 27, 27, &umr_bitfield_default },
	 { "DP_SEC_GSP7_PPS", 28, 28, &umr_bitfield_default },
};
static struct umr_bitfield mmDP3_DP_SEC_CNTL3[] = {
	 { "DP_SEC_GSP1_LINE_NUM", 0, 15, &umr_bitfield_default },
	 { "DP_SEC_GSP2_LINE_NUM", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDP3_DP_SEC_CNTL4[] = {
	 { "DP_SEC_GSP3_LINE_NUM", 0, 15, &umr_bitfield_default },
	 { "DP_SEC_GSP4_LINE_NUM", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDP3_DP_SEC_CNTL5[] = {
	 { "DP_SEC_GSP5_LINE_NUM", 0, 15, &umr_bitfield_default },
	 { "DP_SEC_GSP6_LINE_NUM", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDP3_DP_SEC_CNTL6[] = {
	 { "DP_SEC_GSP7_LINE_NUM", 0, 15, &umr_bitfield_default },
};
static struct umr_bitfield mmDP3_DP_SEC_CNTL7[] = {
	 { "DP_SEC_GSP0_SEND_ACTIVE", 0, 0, &umr_bitfield_default },
	 { "DP_SEC_GSP1_SEND_ACTIVE", 4, 4, &umr_bitfield_default },
	 { "DP_SEC_GSP2_SEND_ACTIVE", 8, 8, &umr_bitfield_default },
	 { "DP_SEC_GSP3_SEND_ACTIVE", 12, 12, &umr_bitfield_default },
	 { "DP_SEC_GSP4_SEND_ACTIVE", 16, 16, &umr_bitfield_default },
	 { "DP_SEC_GSP5_SEND_ACTIVE", 20, 20, &umr_bitfield_default },
	 { "DP_SEC_GSP6_SEND_ACTIVE", 24, 24, &umr_bitfield_default },
	 { "DP_SEC_GSP7_SEND_ACTIVE", 28, 28, &umr_bitfield_default },
};
static struct umr_bitfield mmDP3_DP_DB_CNTL[] = {
	 { "DP_DB_PENDING", 0, 0, &umr_bitfield_default },
	 { "DP_DB_TAKEN", 4, 4, &umr_bitfield_default },
	 { "DP_DB_TAKEN_CLR", 5, 5, &umr_bitfield_default },
	 { "DP_DB_LOCK", 8, 8, &umr_bitfield_default },
	 { "DP_DB_DISABLE", 12, 12, &umr_bitfield_default },
};
static struct umr_bitfield mmDP3_DP_MSA_VBID_MISC[] = {
	 { "DP_MSA_MISC1_STEREOSYNC_OVERRIDE", 0, 1, &umr_bitfield_default },
	 { "DP_MSA_MISC1_STEREOSYNC_OVERRIDE_EN", 4, 4, &umr_bitfield_default },
	 { "DP_VBID1_OVERRIDE", 8, 8, &umr_bitfield_default },
	 { "DP_VBID2_OVERRIDE", 9, 9, &umr_bitfield_default },
	 { "DP_VBID1_OVERRIDE_EN", 12, 12, &umr_bitfield_default },
	 { "DP_VBID2_OVERRIDE_EN", 13, 13, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG4_DIG_FE_CNTL[] = {
	 { "DIG_SOURCE_SELECT", 0, 2, &umr_bitfield_default },
	 { "DIG_STEREOSYNC_SELECT", 4, 6, &umr_bitfield_default },
	 { "DIG_STEREOSYNC_GATE_EN", 8, 8, &umr_bitfield_default },
	 { "DIG_START", 10, 10, &umr_bitfield_default },
	 { "DIG_DIGITAL_BYPASS_SELECT", 12, 14, &umr_bitfield_default },
	 { "DIG_SYMCLK_FE_ON", 24, 24, &umr_bitfield_default },
	 { "TMDS_PIXEL_ENCODING", 28, 28, &umr_bitfield_default },
	 { "TMDS_COLOR_FORMAT", 30, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG4_DIG_OUTPUT_CRC_CNTL[] = {
	 { "DIG_OUTPUT_CRC_EN", 0, 0, &umr_bitfield_default },
	 { "DIG_OUTPUT_CRC_LINK_SEL", 4, 4, &umr_bitfield_default },
	 { "DIG_OUTPUT_CRC_DATA_SEL", 8, 9, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG4_DIG_OUTPUT_CRC_RESULT[] = {
	 { "DIG_OUTPUT_CRC_RESULT", 0, 29, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG4_DIG_CLOCK_PATTERN[] = {
	 { "DIG_CLOCK_PATTERN", 0, 9, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG4_DIG_TEST_PATTERN[] = {
	 { "DIG_TEST_PATTERN_OUT_EN", 0, 0, &umr_bitfield_default },
	 { "DIG_HALF_CLOCK_PATTERN_SEL", 1, 1, &umr_bitfield_default },
	 { "DIG_RANDOM_PATTERN_OUT_EN", 4, 4, &umr_bitfield_default },
	 { "DIG_RANDOM_PATTERN_RESET", 5, 5, &umr_bitfield_default },
	 { "DIG_TEST_PATTERN_EXTERNAL_RESET_EN", 6, 6, &umr_bitfield_default },
	 { "DIG_STATIC_TEST_PATTERN", 16, 25, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG4_DIG_RANDOM_PATTERN_SEED[] = {
	 { "DIG_RANDOM_PATTERN_SEED", 0, 23, &umr_bitfield_default },
	 { "DIG_RAN_PAT_DURING_DE_ONLY", 24, 24, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG4_DIG_FIFO_STATUS[] = {
	 { "DIG_FIFO_LEVEL_ERROR", 0, 0, &umr_bitfield_default },
	 { "DIG_FIFO_USE_OVERWRITE_LEVEL", 1, 1, &umr_bitfield_default },
	 { "DIG_FIFO_OVERWRITE_LEVEL", 2, 7, &umr_bitfield_default },
	 { "DIG_FIFO_ERROR_ACK", 8, 8, &umr_bitfield_default },
	 { "DIG_FIFO_CAL_AVERAGE_LEVEL", 10, 15, &umr_bitfield_default },
	 { "DIG_FIFO_MAXIMUM_LEVEL", 16, 20, &umr_bitfield_default },
	 { "DIG_FIFO_MINIMUM_LEVEL", 22, 25, &umr_bitfield_default },
	 { "DIG_FIFO_READ_CLOCK_SRC", 26, 26, &umr_bitfield_default },
	 { "DIG_FIFO_CALIBRATED", 29, 29, &umr_bitfield_default },
	 { "DIG_FIFO_FORCE_RECAL_AVERAGE", 30, 30, &umr_bitfield_default },
	 { "DIG_FIFO_FORCE_RECOMP_MINMAX", 31, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG4_HDMI_CONTROL[] = {
	 { "HDMI_KEEPOUT_MODE", 0, 0, &umr_bitfield_default },
	 { "HDMI_DATA_SCRAMBLE_EN", 1, 1, &umr_bitfield_default },
	 { "HDMI_CLOCK_CHANNEL_RATE", 2, 2, &umr_bitfield_default },
	 { "HDMI_NO_EXTRA_NULL_PACKET_FILLED", 3, 3, &umr_bitfield_default },
	 { "HDMI_PACKET_GEN_VERSION", 4, 4, &umr_bitfield_default },
	 { "HDMI_ERROR_ACK", 8, 8, &umr_bitfield_default },
	 { "HDMI_ERROR_MASK", 9, 9, &umr_bitfield_default },
	 { "HDMI_DEEP_COLOR_ENABLE", 24, 24, &umr_bitfield_default },
	 { "HDMI_DEEP_COLOR_DEPTH", 28, 29, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG4_HDMI_STATUS[] = {
	 { "HDMI_ACTIVE_AVMUTE", 0, 0, &umr_bitfield_default },
	 { "HDMI_AUDIO_PACKET_ERROR", 16, 16, &umr_bitfield_default },
	 { "HDMI_VBI_PACKET_ERROR", 20, 20, &umr_bitfield_default },
	 { "HDMI_ERROR_INT", 27, 27, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG4_HDMI_AUDIO_PACKET_CONTROL[] = {
	 { "HDMI_AUDIO_DELAY_EN", 4, 5, &umr_bitfield_default },
	 { "HDMI_AUDIO_PACKETS_PER_LINE", 16, 20, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG4_HDMI_ACR_PACKET_CONTROL[] = {
	 { "HDMI_ACR_SEND", 0, 0, &umr_bitfield_default },
	 { "HDMI_ACR_CONT", 1, 1, &umr_bitfield_default },
	 { "HDMI_ACR_SELECT", 4, 5, &umr_bitfield_default },
	 { "HDMI_ACR_SOURCE", 8, 8, &umr_bitfield_default },
	 { "HDMI_ACR_AUTO_SEND", 12, 12, &umr_bitfield_default },
	 { "HDMI_ACR_N_MULTIPLE", 16, 18, &umr_bitfield_default },
	 { "HDMI_ACR_AUDIO_PRIORITY", 31, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG4_HDMI_VBI_PACKET_CONTROL[] = {
	 { "HDMI_NULL_SEND", 0, 0, &umr_bitfield_default },
	 { "HDMI_GC_SEND", 4, 4, &umr_bitfield_default },
	 { "HDMI_GC_CONT", 5, 5, &umr_bitfield_default },
	 { "HDMI_ISRC_SEND", 8, 8, &umr_bitfield_default },
	 { "HDMI_ISRC_CONT", 9, 9, &umr_bitfield_default },
	 { "HDMI_ISRC_LINE", 16, 21, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG4_HDMI_INFOFRAME_CONTROL0[] = {
	 { "HDMI_AUDIO_INFO_SEND", 4, 4, &umr_bitfield_default },
	 { "HDMI_AUDIO_INFO_CONT", 5, 5, &umr_bitfield_default },
	 { "HDMI_MPEG_INFO_SEND", 8, 8, &umr_bitfield_default },
	 { "HDMI_MPEG_INFO_CONT", 9, 9, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG4_HDMI_INFOFRAME_CONTROL1[] = {
	 { "HDMI_AUDIO_INFO_LINE", 8, 13, &umr_bitfield_default },
	 { "HDMI_MPEG_INFO_LINE", 16, 21, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG4_HDMI_GENERIC_PACKET_CONTROL0[] = {
	 { "HDMI_GENERIC0_SEND", 0, 0, &umr_bitfield_default },
	 { "HDMI_GENERIC0_CONT", 1, 1, &umr_bitfield_default },
	 { "HDMI_GENERIC1_SEND", 4, 4, &umr_bitfield_default },
	 { "HDMI_GENERIC1_CONT", 5, 5, &umr_bitfield_default },
	 { "HDMI_GENERIC0_LINE", 16, 21, &umr_bitfield_default },
	 { "HDMI_GENERIC1_LINE", 24, 29, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG4_HDMI_GC[] = {
	 { "HDMI_GC_AVMUTE", 0, 0, &umr_bitfield_default },
	 { "HDMI_GC_AVMUTE_CONT", 2, 2, &umr_bitfield_default },
	 { "HDMI_DEFAULT_PHASE", 4, 4, &umr_bitfield_default },
	 { "HDMI_PACKING_PHASE", 8, 11, &umr_bitfield_default },
	 { "HDMI_PACKING_PHASE_OVERRIDE", 12, 12, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG4_AFMT_AUDIO_PACKET_CONTROL2[] = {
	 { "AFMT_AUDIO_LAYOUT_OVRD", 0, 0, &umr_bitfield_default },
	 { "AFMT_AUDIO_LAYOUT_SELECT", 1, 1, &umr_bitfield_default },
	 { "AFMT_AUDIO_CHANNEL_ENABLE", 8, 15, &umr_bitfield_default },
	 { "AFMT_DP_AUDIO_STREAM_ID", 16, 23, &umr_bitfield_default },
	 { "AFMT_HBR_ENABLE_OVRD", 24, 24, &umr_bitfield_default },
	 { "AFMT_60958_OSF_OVRD", 28, 28, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG4_AFMT_ISRC1_0[] = {
	 { "AFMT_ISRC_STATUS", 0, 2, &umr_bitfield_default },
	 { "AFMT_ISRC_CONTINUE", 6, 6, &umr_bitfield_default },
	 { "AFMT_ISRC_VALID", 7, 7, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG4_AFMT_ISRC1_1[] = {
	 { "AFMT_UPC_EAN_ISRC0", 0, 7, &umr_bitfield_default },
	 { "AFMT_UPC_EAN_ISRC1", 8, 15, &umr_bitfield_default },
	 { "AFMT_UPC_EAN_ISRC2", 16, 23, &umr_bitfield_default },
	 { "AFMT_UPC_EAN_ISRC3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG4_AFMT_ISRC1_2[] = {
	 { "AFMT_UPC_EAN_ISRC4", 0, 7, &umr_bitfield_default },
	 { "AFMT_UPC_EAN_ISRC5", 8, 15, &umr_bitfield_default },
	 { "AFMT_UPC_EAN_ISRC6", 16, 23, &umr_bitfield_default },
	 { "AFMT_UPC_EAN_ISRC7", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG4_AFMT_ISRC1_3[] = {
	 { "AFMT_UPC_EAN_ISRC8", 0, 7, &umr_bitfield_default },
	 { "AFMT_UPC_EAN_ISRC9", 8, 15, &umr_bitfield_default },
	 { "AFMT_UPC_EAN_ISRC10", 16, 23, &umr_bitfield_default },
	 { "AFMT_UPC_EAN_ISRC11", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG4_AFMT_ISRC1_4[] = {
	 { "AFMT_UPC_EAN_ISRC12", 0, 7, &umr_bitfield_default },
	 { "AFMT_UPC_EAN_ISRC13", 8, 15, &umr_bitfield_default },
	 { "AFMT_UPC_EAN_ISRC14", 16, 23, &umr_bitfield_default },
	 { "AFMT_UPC_EAN_ISRC15", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG4_AFMT_ISRC2_0[] = {
	 { "AFMT_UPC_EAN_ISRC16", 0, 7, &umr_bitfield_default },
	 { "AFMT_UPC_EAN_ISRC17", 8, 15, &umr_bitfield_default },
	 { "AFMT_UPC_EAN_ISRC18", 16, 23, &umr_bitfield_default },
	 { "AFMT_UPC_EAN_ISRC19", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG4_AFMT_ISRC2_1[] = {
	 { "AFMT_UPC_EAN_ISRC20", 0, 7, &umr_bitfield_default },
	 { "AFMT_UPC_EAN_ISRC21", 8, 15, &umr_bitfield_default },
	 { "AFMT_UPC_EAN_ISRC22", 16, 23, &umr_bitfield_default },
	 { "AFMT_UPC_EAN_ISRC23", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG4_AFMT_ISRC2_2[] = {
	 { "AFMT_UPC_EAN_ISRC24", 0, 7, &umr_bitfield_default },
	 { "AFMT_UPC_EAN_ISRC25", 8, 15, &umr_bitfield_default },
	 { "AFMT_UPC_EAN_ISRC26", 16, 23, &umr_bitfield_default },
	 { "AFMT_UPC_EAN_ISRC27", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG4_AFMT_ISRC2_3[] = {
	 { "AFMT_UPC_EAN_ISRC28", 0, 7, &umr_bitfield_default },
	 { "AFMT_UPC_EAN_ISRC29", 8, 15, &umr_bitfield_default },
	 { "AFMT_UPC_EAN_ISRC30", 16, 23, &umr_bitfield_default },
	 { "AFMT_UPC_EAN_ISRC31", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG4_HDMI_GENERIC_PACKET_CONTROL2[] = {
	 { "HDMI_GENERIC4_SEND", 0, 0, &umr_bitfield_default },
	 { "HDMI_GENERIC4_CONT", 1, 1, &umr_bitfield_default },
	 { "HDMI_GENERIC5_SEND", 4, 4, &umr_bitfield_default },
	 { "HDMI_GENERIC5_CONT", 5, 5, &umr_bitfield_default },
	 { "HDMI_GENERIC4_LINE", 16, 21, &umr_bitfield_default },
	 { "HDMI_GENERIC5_LINE", 24, 29, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG4_HDMI_GENERIC_PACKET_CONTROL3[] = {
	 { "HDMI_GENERIC6_SEND", 0, 0, &umr_bitfield_default },
	 { "HDMI_GENERIC6_CONT", 1, 1, &umr_bitfield_default },
	 { "HDMI_GENERIC7_SEND", 4, 4, &umr_bitfield_default },
	 { "HDMI_GENERIC7_CONT", 5, 5, &umr_bitfield_default },
	 { "HDMI_GENERIC6_LINE", 16, 21, &umr_bitfield_default },
	 { "HDMI_GENERIC7_LINE", 24, 29, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG4_HDMI_DB_CONTROL[] = {
	 { "HDMI_DB_PENDING", 0, 0, &umr_bitfield_default },
	 { "HDMI_DB_TAKEN", 4, 4, &umr_bitfield_default },
	 { "HDMI_DB_TAKEN_CLR", 5, 5, &umr_bitfield_default },
	 { "HDMI_DB_LOCK", 8, 8, &umr_bitfield_default },
	 { "HDMI_DB_DISABLE", 12, 12, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG4_AFMT_MPEG_INFO0[] = {
	 { "AFMT_MPEG_INFO_CHECKSUM", 0, 7, &umr_bitfield_default },
	 { "AFMT_MPEG_INFO_MB0", 8, 15, &umr_bitfield_default },
	 { "AFMT_MPEG_INFO_MB1", 16, 23, &umr_bitfield_default },
	 { "AFMT_MPEG_INFO_MB2", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG4_AFMT_MPEG_INFO1[] = {
	 { "AFMT_MPEG_INFO_MB3", 0, 7, &umr_bitfield_default },
	 { "AFMT_MPEG_INFO_MF", 8, 9, &umr_bitfield_default },
	 { "AFMT_MPEG_INFO_FR", 12, 12, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG4_AFMT_GENERIC_HDR[] = {
	 { "AFMT_GENERIC_HB0", 0, 7, &umr_bitfield_default },
	 { "AFMT_GENERIC_HB1", 8, 15, &umr_bitfield_default },
	 { "AFMT_GENERIC_HB2", 16, 23, &umr_bitfield_default },
	 { "AFMT_GENERIC_HB3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG4_AFMT_GENERIC_0[] = {
	 { "AFMT_GENERIC_BYTE0", 0, 7, &umr_bitfield_default },
	 { "AFMT_GENERIC_BYTE1", 8, 15, &umr_bitfield_default },
	 { "AFMT_GENERIC_BYTE2", 16, 23, &umr_bitfield_default },
	 { "AFMT_GENERIC_BYTE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG4_AFMT_GENERIC_1[] = {
	 { "AFMT_GENERIC_BYTE4", 0, 7, &umr_bitfield_default },
	 { "AFMT_GENERIC_BYTE5", 8, 15, &umr_bitfield_default },
	 { "AFMT_GENERIC_BYTE6", 16, 23, &umr_bitfield_default },
	 { "AFMT_GENERIC_BYTE7", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG4_AFMT_GENERIC_2[] = {
	 { "AFMT_GENERIC_BYTE8", 0, 7, &umr_bitfield_default },
	 { "AFMT_GENERIC_BYTE9", 8, 15, &umr_bitfield_default },
	 { "AFMT_GENERIC_BYTE10", 16, 23, &umr_bitfield_default },
	 { "AFMT_GENERIC_BYTE11", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG4_AFMT_GENERIC_3[] = {
	 { "AFMT_GENERIC_BYTE12", 0, 7, &umr_bitfield_default },
	 { "AFMT_GENERIC_BYTE13", 8, 15, &umr_bitfield_default },
	 { "AFMT_GENERIC_BYTE14", 16, 23, &umr_bitfield_default },
	 { "AFMT_GENERIC_BYTE15", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG4_AFMT_GENERIC_4[] = {
	 { "AFMT_GENERIC_BYTE16", 0, 7, &umr_bitfield_default },
	 { "AFMT_GENERIC_BYTE17", 8, 15, &umr_bitfield_default },
	 { "AFMT_GENERIC_BYTE18", 16, 23, &umr_bitfield_default },
	 { "AFMT_GENERIC_BYTE19", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG4_AFMT_GENERIC_5[] = {
	 { "AFMT_GENERIC_BYTE20", 0, 7, &umr_bitfield_default },
	 { "AFMT_GENERIC_BYTE21", 8, 15, &umr_bitfield_default },
	 { "AFMT_GENERIC_BYTE22", 16, 23, &umr_bitfield_default },
	 { "AFMT_GENERIC_BYTE23", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG4_AFMT_GENERIC_6[] = {
	 { "AFMT_GENERIC_BYTE24", 0, 7, &umr_bitfield_default },
	 { "AFMT_GENERIC_BYTE25", 8, 15, &umr_bitfield_default },
	 { "AFMT_GENERIC_BYTE26", 16, 23, &umr_bitfield_default },
	 { "AFMT_GENERIC_BYTE27", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG4_AFMT_GENERIC_7[] = {
	 { "AFMT_GENERIC_BYTE28", 0, 7, &umr_bitfield_default },
	 { "AFMT_GENERIC_BYTE29", 8, 15, &umr_bitfield_default },
	 { "AFMT_GENERIC_BYTE30", 16, 23, &umr_bitfield_default },
	 { "AFMT_GENERIC_BYTE31", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG4_HDMI_GENERIC_PACKET_CONTROL1[] = {
	 { "HDMI_GENERIC2_SEND", 0, 0, &umr_bitfield_default },
	 { "HDMI_GENERIC2_CONT", 1, 1, &umr_bitfield_default },
	 { "HDMI_GENERIC3_SEND", 4, 4, &umr_bitfield_default },
	 { "HDMI_GENERIC3_CONT", 5, 5, &umr_bitfield_default },
	 { "HDMI_GENERIC2_LINE", 16, 21, &umr_bitfield_default },
	 { "HDMI_GENERIC3_LINE", 24, 29, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG4_HDMI_ACR_32_0[] = {
	 { "HDMI_ACR_CTS_32", 12, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG4_HDMI_ACR_32_1[] = {
	 { "HDMI_ACR_N_32", 0, 19, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG4_HDMI_ACR_44_0[] = {
	 { "HDMI_ACR_CTS_44", 12, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG4_HDMI_ACR_44_1[] = {
	 { "HDMI_ACR_N_44", 0, 19, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG4_HDMI_ACR_48_0[] = {
	 { "HDMI_ACR_CTS_48", 12, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG4_HDMI_ACR_48_1[] = {
	 { "HDMI_ACR_N_48", 0, 19, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG4_HDMI_ACR_STATUS_0[] = {
	 { "HDMI_ACR_CTS", 12, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG4_HDMI_ACR_STATUS_1[] = {
	 { "HDMI_ACR_N", 0, 19, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG4_AFMT_AUDIO_INFO0[] = {
	 { "AFMT_AUDIO_INFO_CHECKSUM", 0, 7, &umr_bitfield_default },
	 { "AFMT_AUDIO_INFO_CC", 8, 10, &umr_bitfield_default },
	 { "AFMT_AUDIO_INFO_CT", 11, 14, &umr_bitfield_default },
	 { "AFMT_AUDIO_INFO_CHECKSUM_OFFSET", 16, 23, &umr_bitfield_default },
	 { "AFMT_AUDIO_INFO_CXT", 24, 28, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG4_AFMT_AUDIO_INFO1[] = {
	 { "AFMT_AUDIO_INFO_CA", 0, 7, &umr_bitfield_default },
	 { "AFMT_AUDIO_INFO_LSV", 11, 14, &umr_bitfield_default },
	 { "AFMT_AUDIO_INFO_DM_INH", 15, 15, &umr_bitfield_default },
	 { "AFMT_AUDIO_INFO_LFEPBL", 16, 17, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG4_AFMT_60958_0[] = {
	 { "AFMT_60958_CS_A", 0, 0, &umr_bitfield_default },
	 { "AFMT_60958_CS_B", 1, 1, &umr_bitfield_default },
	 { "AFMT_60958_CS_C", 2, 2, &umr_bitfield_default },
	 { "AFMT_60958_CS_D", 3, 5, &umr_bitfield_default },
	 { "AFMT_60958_CS_MODE", 6, 7, &umr_bitfield_default },
	 { "AFMT_60958_CS_CATEGORY_CODE", 8, 15, &umr_bitfield_default },
	 { "AFMT_60958_CS_SOURCE_NUMBER", 16, 19, &umr_bitfield_default },
	 { "AFMT_60958_CS_CHANNEL_NUMBER_L", 20, 23, &umr_bitfield_default },
	 { "AFMT_60958_CS_SAMPLING_FREQUENCY", 24, 27, &umr_bitfield_default },
	 { "AFMT_60958_CS_CLOCK_ACCURACY", 28, 29, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG4_AFMT_60958_1[] = {
	 { "AFMT_60958_CS_WORD_LENGTH", 0, 3, &umr_bitfield_default },
	 { "AFMT_60958_CS_ORIGINAL_SAMPLING_FREQUENCY", 4, 7, &umr_bitfield_default },
	 { "AFMT_60958_VALID_L", 16, 16, &umr_bitfield_default },
	 { "AFMT_60958_VALID_R", 18, 18, &umr_bitfield_default },
	 { "AFMT_60958_CS_CHANNEL_NUMBER_R", 20, 23, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG4_AFMT_AUDIO_CRC_CONTROL[] = {
	 { "AFMT_AUDIO_CRC_EN", 0, 0, &umr_bitfield_default },
	 { "AFMT_AUDIO_CRC_CONT", 4, 4, &umr_bitfield_default },
	 { "AFMT_AUDIO_CRC_SOURCE", 8, 8, &umr_bitfield_default },
	 { "AFMT_AUDIO_CRC_CH_SEL", 12, 15, &umr_bitfield_default },
	 { "AFMT_AUDIO_CRC_COUNT", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG4_AFMT_RAMP_CONTROL0[] = {
	 { "AFMT_RAMP_MAX_COUNT", 0, 23, &umr_bitfield_default },
	 { "AFMT_RAMP_DATA_SIGN", 31, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG4_AFMT_RAMP_CONTROL1[] = {
	 { "AFMT_RAMP_MIN_COUNT", 0, 23, &umr_bitfield_default },
	 { "AFMT_AUDIO_TEST_CH_DISABLE", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG4_AFMT_RAMP_CONTROL2[] = {
	 { "AFMT_RAMP_INC_COUNT", 0, 23, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG4_AFMT_RAMP_CONTROL3[] = {
	 { "AFMT_RAMP_DEC_COUNT", 0, 23, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG4_AFMT_60958_2[] = {
	 { "AFMT_60958_CS_CHANNEL_NUMBER_2", 0, 3, &umr_bitfield_default },
	 { "AFMT_60958_CS_CHANNEL_NUMBER_3", 4, 7, &umr_bitfield_default },
	 { "AFMT_60958_CS_CHANNEL_NUMBER_4", 8, 11, &umr_bitfield_default },
	 { "AFMT_60958_CS_CHANNEL_NUMBER_5", 12, 15, &umr_bitfield_default },
	 { "AFMT_60958_CS_CHANNEL_NUMBER_6", 16, 19, &umr_bitfield_default },
	 { "AFMT_60958_CS_CHANNEL_NUMBER_7", 20, 23, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG4_AFMT_AUDIO_CRC_RESULT[] = {
	 { "AFMT_AUDIO_CRC_DONE", 0, 0, &umr_bitfield_default },
	 { "AFMT_AUDIO_CRC", 8, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG4_AFMT_STATUS[] = {
	 { "AFMT_AUDIO_ENABLE", 4, 4, &umr_bitfield_default },
	 { "AFMT_AZ_HBR_ENABLE", 8, 8, &umr_bitfield_default },
	 { "AFMT_AUDIO_FIFO_OVERFLOW", 24, 24, &umr_bitfield_default },
	 { "AFMT_AZ_AUDIO_ENABLE_CHG", 30, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG4_AFMT_AUDIO_PACKET_CONTROL[] = {
	 { "AFMT_AUDIO_SAMPLE_SEND", 0, 0, &umr_bitfield_default },
	 { "AFMT_RESET_FIFO_WHEN_AUDIO_DIS", 11, 11, &umr_bitfield_default },
	 { "AFMT_AUDIO_TEST_EN", 12, 12, &umr_bitfield_default },
	 { "AFMT_AUDIO_TEST_MODE", 14, 14, &umr_bitfield_default },
	 { "AFMT_AUDIO_FIFO_OVERFLOW_ACK", 23, 23, &umr_bitfield_default },
	 { "AFMT_AUDIO_CHANNEL_SWAP", 24, 24, &umr_bitfield_default },
	 { "AFMT_60958_CS_UPDATE", 26, 26, &umr_bitfield_default },
	 { "AFMT_AZ_AUDIO_ENABLE_CHG_ACK", 30, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG4_AFMT_VBI_PACKET_CONTROL[] = {
	 { "AFMT_GENERIC_LOCK_STATUS", 8, 8, &umr_bitfield_default },
	 { "AFMT_GENERIC_CONFLICT", 16, 16, &umr_bitfield_default },
	 { "AFMT_GENERIC_CONFLICT_CLR", 17, 17, &umr_bitfield_default },
	 { "AFMT_GENERIC_INDEX", 28, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG4_AFMT_INFOFRAME_CONTROL0[] = {
	 { "AFMT_AUDIO_INFO_SOURCE", 6, 6, &umr_bitfield_default },
	 { "AFMT_AUDIO_INFO_UPDATE", 7, 7, &umr_bitfield_default },
	 { "AFMT_MPEG_INFO_UPDATE", 10, 10, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG4_AFMT_AUDIO_SRC_CONTROL[] = {
	 { "AFMT_AUDIO_SRC_SELECT", 0, 2, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG4_DIG_BE_CNTL[] = {
	 { "DIG_DUAL_LINK_ENABLE", 0, 0, &umr_bitfield_default },
	 { "DIG_SWAP", 1, 1, &umr_bitfield_default },
	 { "DIG_FE_SOURCE_SELECT", 8, 14, &umr_bitfield_default },
	 { "DIG_MODE", 16, 18, &umr_bitfield_default },
	 { "DIG_HPD_SELECT", 28, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG4_DIG_BE_EN_CNTL[] = {
	 { "DIG_ENABLE", 0, 0, &umr_bitfield_default },
	 { "DIG_SYMCLK_BE_ON", 8, 8, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG4_TMDS_CNTL[] = {
	 { "TMDS_SYNC_PHASE", 0, 0, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG4_TMDS_CONTROL_CHAR[] = {
	 { "TMDS_CONTROL_CHAR0_OUT_EN", 0, 0, &umr_bitfield_default },
	 { "TMDS_CONTROL_CHAR1_OUT_EN", 1, 1, &umr_bitfield_default },
	 { "TMDS_CONTROL_CHAR2_OUT_EN", 2, 2, &umr_bitfield_default },
	 { "TMDS_CONTROL_CHAR3_OUT_EN", 3, 3, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG4_TMDS_CONTROL0_FEEDBACK[] = {
	 { "TMDS_CONTROL0_FEEDBACK_SELECT", 0, 1, &umr_bitfield_default },
	 { "TMDS_CONTROL0_FEEDBACK_DELAY", 8, 9, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG4_TMDS_STEREOSYNC_CTL_SEL[] = {
	 { "TMDS_STEREOSYNC_CTL_SEL", 0, 1, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG4_TMDS_SYNC_CHAR_PATTERN_0_1[] = {
	 { "TMDS_SYNC_CHAR_PATTERN0", 0, 9, &umr_bitfield_default },
	 { "TMDS_SYNC_CHAR_PATTERN1", 16, 25, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG4_TMDS_SYNC_CHAR_PATTERN_2_3[] = {
	 { "TMDS_SYNC_CHAR_PATTERN2", 0, 9, &umr_bitfield_default },
	 { "TMDS_SYNC_CHAR_PATTERN3", 16, 25, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG4_TMDS_CTL_BITS[] = {
	 { "TMDS_CTL0", 0, 0, &umr_bitfield_default },
	 { "TMDS_CTL1", 8, 8, &umr_bitfield_default },
	 { "TMDS_CTL2", 16, 16, &umr_bitfield_default },
	 { "TMDS_CTL3", 24, 24, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG4_TMDS_DCBALANCER_CONTROL[] = {
	 { "TMDS_DCBALANCER_EN", 0, 0, &umr_bitfield_default },
	 { "TMDS_DCBALANCER_TEST_EN", 8, 8, &umr_bitfield_default },
	 { "TMDS_DCBALANCER_TEST_IN", 16, 19, &umr_bitfield_default },
	 { "TMDS_DCBALANCER_FORCE", 24, 24, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG4_TMDS_CTL0_1_GEN_CNTL[] = {
	 { "TMDS_CTL0_DATA_SEL", 0, 3, &umr_bitfield_default },
	 { "TMDS_CTL0_DATA_DELAY", 4, 6, &umr_bitfield_default },
	 { "TMDS_CTL0_DATA_INVERT", 7, 7, &umr_bitfield_default },
	 { "TMDS_CTL0_DATA_MODULATION", 8, 9, &umr_bitfield_default },
	 { "TMDS_CTL0_USE_FEEDBACK_PATH", 10, 10, &umr_bitfield_default },
	 { "TMDS_CTL0_FB_SYNC_CONT", 11, 11, &umr_bitfield_default },
	 { "TMDS_CTL0_PATTERN_OUT_EN", 12, 12, &umr_bitfield_default },
	 { "TMDS_CTL1_DATA_SEL", 16, 19, &umr_bitfield_default },
	 { "TMDS_CTL1_DATA_DELAY", 20, 22, &umr_bitfield_default },
	 { "TMDS_CTL1_DATA_INVERT", 23, 23, &umr_bitfield_default },
	 { "TMDS_CTL1_DATA_MODULATION", 24, 25, &umr_bitfield_default },
	 { "TMDS_CTL1_USE_FEEDBACK_PATH", 26, 26, &umr_bitfield_default },
	 { "TMDS_CTL1_FB_SYNC_CONT", 27, 27, &umr_bitfield_default },
	 { "TMDS_CTL1_PATTERN_OUT_EN", 28, 28, &umr_bitfield_default },
	 { "TMDS_2BIT_COUNTER_EN", 31, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG4_TMDS_CTL2_3_GEN_CNTL[] = {
	 { "TMDS_CTL2_DATA_SEL", 0, 3, &umr_bitfield_default },
	 { "TMDS_CTL2_DATA_DELAY", 4, 6, &umr_bitfield_default },
	 { "TMDS_CTL2_DATA_INVERT", 7, 7, &umr_bitfield_default },
	 { "TMDS_CTL2_DATA_MODULATION", 8, 9, &umr_bitfield_default },
	 { "TMDS_CTL2_USE_FEEDBACK_PATH", 10, 10, &umr_bitfield_default },
	 { "TMDS_CTL2_FB_SYNC_CONT", 11, 11, &umr_bitfield_default },
	 { "TMDS_CTL2_PATTERN_OUT_EN", 12, 12, &umr_bitfield_default },
	 { "TMDS_CTL3_DATA_SEL", 16, 19, &umr_bitfield_default },
	 { "TMDS_CTL3_DATA_DELAY", 20, 22, &umr_bitfield_default },
	 { "TMDS_CTL3_DATA_INVERT", 23, 23, &umr_bitfield_default },
	 { "TMDS_CTL3_DATA_MODULATION", 24, 25, &umr_bitfield_default },
	 { "TMDS_CTL3_USE_FEEDBACK_PATH", 26, 26, &umr_bitfield_default },
	 { "TMDS_CTL3_FB_SYNC_CONT", 27, 27, &umr_bitfield_default },
	 { "TMDS_CTL3_PATTERN_OUT_EN", 28, 28, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG4_DIG_VERSION[] = {
	 { "DIG_TYPE", 0, 0, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG4_DIG_LANE_ENABLE[] = {
	 { "DIG_LANE0EN", 0, 0, &umr_bitfield_default },
	 { "DIG_LANE1EN", 1, 1, &umr_bitfield_default },
	 { "DIG_LANE2EN", 2, 2, &umr_bitfield_default },
	 { "DIG_LANE3EN", 3, 3, &umr_bitfield_default },
	 { "DIG_CLK_EN", 8, 8, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG4_AFMT_CNTL[] = {
	 { "AFMT_AUDIO_CLOCK_EN", 0, 0, &umr_bitfield_default },
	 { "AFMT_AUDIO_CLOCK_ON", 8, 8, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG4_AFMT_VBI_PACKET_CONTROL1[] = {
	 { "AFMT_GENERIC0_FRAME_UPDATE", 0, 0, &umr_bitfield_default },
	 { "AFMT_GENERIC0_FRAME_UPDATE_PENDING", 1, 1, &umr_bitfield_default },
	 { "AFMT_GENERIC0_IMMEDIATE_UPDATE", 2, 2, &umr_bitfield_default },
	 { "AFMT_GENERIC0_IMMEDIATE_UPDATE_PENDING", 3, 3, &umr_bitfield_default },
	 { "AFMT_GENERIC1_FRAME_UPDATE", 4, 4, &umr_bitfield_default },
	 { "AFMT_GENERIC1_FRAME_UPDATE_PENDING", 5, 5, &umr_bitfield_default },
	 { "AFMT_GENERIC1_IMMEDIATE_UPDATE", 6, 6, &umr_bitfield_default },
	 { "AFMT_GENERIC1_IMMEDIATE_UPDATE_PENDING", 7, 7, &umr_bitfield_default },
	 { "AFMT_GENERIC2_FRAME_UPDATE", 8, 8, &umr_bitfield_default },
	 { "AFMT_GENERIC2_FRAME_UPDATE_PENDING", 9, 9, &umr_bitfield_default },
	 { "AFMT_GENERIC2_IMMEDIATE_UPDATE", 10, 10, &umr_bitfield_default },
	 { "AFMT_GENERIC2_IMMEDIATE_UPDATE_PENDING", 11, 11, &umr_bitfield_default },
	 { "AFMT_GENERIC3_FRAME_UPDATE", 12, 12, &umr_bitfield_default },
	 { "AFMT_GENERIC3_FRAME_UPDATE_PENDING", 13, 13, &umr_bitfield_default },
	 { "AFMT_GENERIC3_IMMEDIATE_UPDATE", 14, 14, &umr_bitfield_default },
	 { "AFMT_GENERIC3_IMMEDIATE_UPDATE_PENDING", 15, 15, &umr_bitfield_default },
	 { "AFMT_GENERIC4_FRAME_UPDATE", 16, 16, &umr_bitfield_default },
	 { "AFMT_GENERIC4_FRAME_UPDATE_PENDING", 17, 17, &umr_bitfield_default },
	 { "AFMT_GENERIC4_IMMEDIATE_UPDATE", 18, 18, &umr_bitfield_default },
	 { "AFMT_GENERIC4_IMMEDIATE_UPDATE_PENDING", 19, 19, &umr_bitfield_default },
	 { "AFMT_GENERIC5_FRAME_UPDATE", 20, 20, &umr_bitfield_default },
	 { "AFMT_GENERIC5_FRAME_UPDATE_PENDING", 21, 21, &umr_bitfield_default },
	 { "AFMT_GENERIC5_IMMEDIATE_UPDATE", 22, 22, &umr_bitfield_default },
	 { "AFMT_GENERIC5_IMMEDIATE_UPDATE_PENDING", 23, 23, &umr_bitfield_default },
	 { "AFMT_GENERIC6_FRAME_UPDATE", 24, 24, &umr_bitfield_default },
	 { "AFMT_GENERIC6_FRAME_UPDATE_PENDING", 25, 25, &umr_bitfield_default },
	 { "AFMT_GENERIC6_IMMEDIATE_UPDATE", 26, 26, &umr_bitfield_default },
	 { "AFMT_GENERIC6_IMMEDIATE_UPDATE_PENDING", 27, 27, &umr_bitfield_default },
	 { "AFMT_GENERIC7_FRAME_UPDATE", 28, 28, &umr_bitfield_default },
	 { "AFMT_GENERIC7_FRAME_UPDATE_PENDING", 29, 29, &umr_bitfield_default },
	 { "AFMT_GENERIC7_IMMEDIATE_UPDATE", 30, 30, &umr_bitfield_default },
	 { "AFMT_GENERIC7_IMMEDIATE_UPDATE_PENDING", 31, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDP4_DP_LINK_CNTL[] = {
	 { "DP_LINK_TRAINING_COMPLETE", 4, 4, &umr_bitfield_default },
	 { "DP_LINK_STATUS", 8, 8, &umr_bitfield_default },
	 { "DP_EMBEDDED_PANEL_MODE", 17, 17, &umr_bitfield_default },
};
static struct umr_bitfield mmDP4_DP_PIXEL_FORMAT[] = {
	 { "DP_PIXEL_ENCODING", 0, 2, &umr_bitfield_default },
	 { "DP_COMPONENT_DEPTH", 24, 26, &umr_bitfield_default },
	 { "DP_PIXEL_COMBINE", 28, 29, &umr_bitfield_default },
};
static struct umr_bitfield mmDP4_DP_MSA_COLORIMETRY[] = {
	 { "DP_MSA_MISC0", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDP4_DP_CONFIG[] = {
	 { "DP_UDI_LANES", 0, 1, &umr_bitfield_default },
};
static struct umr_bitfield mmDP4_DP_VID_STREAM_CNTL[] = {
	 { "DP_VID_STREAM_ENABLE", 0, 0, &umr_bitfield_default },
	 { "DP_VID_STREAM_DIS_DEFER", 8, 9, &umr_bitfield_default },
	 { "DP_VID_STREAM_STATUS", 16, 16, &umr_bitfield_default },
	 { "DP_VID_STREAM_CHANGE_KEEPOUT", 20, 20, &umr_bitfield_default },
};
static struct umr_bitfield mmDP4_DP_STEER_FIFO[] = {
	 { "DP_STEER_FIFO_RESET", 0, 0, &umr_bitfield_default },
	 { "DP_STEER_OVERFLOW_FLAG", 4, 4, &umr_bitfield_default },
	 { "DP_STEER_OVERFLOW_INT", 5, 5, &umr_bitfield_default },
	 { "DP_STEER_OVERFLOW_ACK", 6, 6, &umr_bitfield_default },
	 { "DP_STEER_OVERFLOW_MASK", 7, 7, &umr_bitfield_default },
	 { "DP_TU_OVERFLOW_FLAG", 8, 8, &umr_bitfield_default },
	 { "DP_TU_OVERFLOW_ACK", 12, 12, &umr_bitfield_default },
};
static struct umr_bitfield mmDP4_DP_MSA_MISC[] = {
	 { "DP_MSA_MISC1", 0, 7, &umr_bitfield_default },
	 { "DP_MSA_MISC2", 8, 15, &umr_bitfield_default },
	 { "DP_MSA_MISC3", 16, 23, &umr_bitfield_default },
	 { "DP_MSA_MISC4", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDP4_DP_VID_TIMING[] = {
	 { "DP_VID_M_N_DOUBLE_BUFFER_MODE", 4, 4, &umr_bitfield_default },
	 { "DP_VID_M_N_GEN_EN", 8, 8, &umr_bitfield_default },
	 { "DP_VID_N_MUL", 10, 11, &umr_bitfield_default },
	 { "DP_VID_M_DIV", 12, 13, &umr_bitfield_default },
	 { "DP_VID_N_DIV", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDP4_DP_VID_N[] = {
	 { "DP_VID_N", 0, 23, &umr_bitfield_default },
};
static struct umr_bitfield mmDP4_DP_VID_M[] = {
	 { "DP_VID_M", 0, 23, &umr_bitfield_default },
};
static struct umr_bitfield mmDP4_DP_LINK_FRAMING_CNTL[] = {
	 { "DP_IDLE_BS_INTERVAL", 0, 17, &umr_bitfield_default },
	 { "DP_VBID_DISABLE", 24, 24, &umr_bitfield_default },
	 { "DP_VID_ENHANCED_FRAME_MODE", 28, 28, &umr_bitfield_default },
};
static struct umr_bitfield mmDP4_DP_HBR2_EYE_PATTERN[] = {
	 { "DP_HBR2_EYE_PATTERN_ENABLE", 0, 0, &umr_bitfield_default },
};
static struct umr_bitfield mmDP4_DP_VID_MSA_VBID[] = {
	 { "DP_VID_MSA_LOCATION", 0, 11, &umr_bitfield_default },
	 { "DP_VID_VBID_FIELD_POL", 24, 24, &umr_bitfield_default },
};
static struct umr_bitfield mmDP4_DP_VID_INTERRUPT_CNTL[] = {
	 { "DP_VID_STREAM_DISABLE_INT", 0, 0, &umr_bitfield_default },
	 { "DP_VID_STREAM_DISABLE_ACK", 1, 1, &umr_bitfield_default },
	 { "DP_VID_STREAM_DISABLE_MASK", 2, 2, &umr_bitfield_default },
};
static struct umr_bitfield mmDP4_DP_DPHY_CNTL[] = {
	 { "DPHY_ATEST_SEL_LANE0", 0, 0, &umr_bitfield_default },
	 { "DPHY_ATEST_SEL_LANE1", 1, 1, &umr_bitfield_default },
	 { "DPHY_ATEST_SEL_LANE2", 2, 2, &umr_bitfield_default },
	 { "DPHY_ATEST_SEL_LANE3", 3, 3, &umr_bitfield_default },
	 { "DPHY_BYPASS", 16, 16, &umr_bitfield_default },
	 { "DPHY_SKEW_BYPASS", 24, 24, &umr_bitfield_default },
};
static struct umr_bitfield mmDP4_DP_DPHY_TRAINING_PATTERN_SEL[] = {
	 { "DPHY_TRAINING_PATTERN_SEL", 0, 1, &umr_bitfield_default },
};
static struct umr_bitfield mmDP4_DP_DPHY_SYM0[] = {
	 { "DPHY_SYM1", 0, 9, &umr_bitfield_default },
	 { "DPHY_SYM2", 10, 19, &umr_bitfield_default },
	 { "DPHY_SYM3", 20, 29, &umr_bitfield_default },
};
static struct umr_bitfield mmDP4_DP_DPHY_SYM1[] = {
	 { "DPHY_SYM4", 0, 9, &umr_bitfield_default },
	 { "DPHY_SYM5", 10, 19, &umr_bitfield_default },
	 { "DPHY_SYM6", 20, 29, &umr_bitfield_default },
};
static struct umr_bitfield mmDP4_DP_DPHY_SYM2[] = {
	 { "DPHY_SYM7", 0, 9, &umr_bitfield_default },
	 { "DPHY_SYM8", 10, 19, &umr_bitfield_default },
};
static struct umr_bitfield mmDP4_DP_DPHY_8B10B_CNTL[] = {
	 { "DPHY_8B10B_RESET", 8, 8, &umr_bitfield_default },
	 { "DPHY_8B10B_EXT_DISP", 16, 16, &umr_bitfield_default },
	 { "DPHY_8B10B_CUR_DISP", 24, 24, &umr_bitfield_default },
};
static struct umr_bitfield mmDP4_DP_DPHY_PRBS_CNTL[] = {
	 { "DPHY_PRBS_EN", 0, 0, &umr_bitfield_default },
	 { "DPHY_PRBS_SEL", 4, 5, &umr_bitfield_default },
	 { "DPHY_PRBS_SEED", 8, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmDP4_DP_DPHY_SCRAM_CNTL[] = {
	 { "DPHY_SCRAMBLER_DIS", 0, 0, &umr_bitfield_default },
	 { "DPHY_SCRAMBLER_ADVANCE", 4, 4, &umr_bitfield_default },
	 { "DPHY_SCRAMBLER_BS_COUNT", 8, 17, &umr_bitfield_default },
	 { "DPHY_SCRAMBLER_KCODE", 24, 24, &umr_bitfield_default },
};
static struct umr_bitfield mmDP4_DP_DPHY_CRC_EN[] = {
	 { "DPHY_CRC_EN", 0, 0, &umr_bitfield_default },
	 { "DPHY_CRC_CONT_EN", 4, 4, &umr_bitfield_default },
	 { "DPHY_CRC_RESULT_VALID", 8, 8, &umr_bitfield_default },
};
static struct umr_bitfield mmDP4_DP_DPHY_CRC_CNTL[] = {
	 { "DPHY_CRC_FIELD", 0, 0, &umr_bitfield_default },
	 { "DPHY_CRC_SEL", 4, 5, &umr_bitfield_default },
	 { "DPHY_CRC_MASK", 16, 23, &umr_bitfield_default },
};
static struct umr_bitfield mmDP4_DP_DPHY_CRC_RESULT[] = {
	 { "DPHY_CRC_RESULT", 0, 7, &umr_bitfield_default },
	 { "DPHY_CRC_RESULT1", 8, 15, &umr_bitfield_default },
	 { "DPHY_CRC_RESULT2", 16, 23, &umr_bitfield_default },
	 { "DPHY_CRC_RESULT3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDP4_DP_DPHY_CRC_MST_CNTL[] = {
	 { "DPHY_CRC_MST_FIRST_SLOT", 0, 5, &umr_bitfield_default },
	 { "DPHY_CRC_MST_LAST_SLOT", 8, 13, &umr_bitfield_default },
};
static struct umr_bitfield mmDP4_DP_DPHY_CRC_MST_STATUS[] = {
	 { "DPHY_CRC_MST_PHASE_LOCK", 0, 0, &umr_bitfield_default },
	 { "DPHY_CRC_MST_PHASE_ERROR", 8, 8, &umr_bitfield_default },
	 { "DPHY_CRC_MST_PHASE_ERROR_ACK", 16, 16, &umr_bitfield_default },
};
static struct umr_bitfield mmDP4_DP_DPHY_FAST_TRAINING[] = {
	 { "DPHY_RX_FAST_TRAINING_CAPABLE", 0, 0, &umr_bitfield_default },
	 { "DPHY_SW_FAST_TRAINING_START", 1, 1, &umr_bitfield_default },
	 { "DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN", 2, 2, &umr_bitfield_default },
	 { "DPHY_FAST_TRAINING_TP1_TIME", 8, 19, &umr_bitfield_default },
	 { "DPHY_FAST_TRAINING_TP2_TIME", 20, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDP4_DP_DPHY_FAST_TRAINING_STATUS[] = {
	 { "DPHY_FAST_TRAINING_STATE", 0, 2, &umr_bitfield_default },
	 { "DPHY_FAST_TRAINING_COMPLETE_OCCURRED", 4, 4, &umr_bitfield_default },
	 { "DPHY_FAST_TRAINING_COMPLETE_MASK", 8, 8, &umr_bitfield_default },
	 { "DPHY_FAST_TRAINING_COMPLETE_ACK", 12, 12, &umr_bitfield_default },
};
static struct umr_bitfield mmDP4_DP_SEC_CNTL[] = {
	 { "DP_SEC_STREAM_ENABLE", 0, 0, &umr_bitfield_default },
	 { "DP_SEC_ASP_ENABLE", 4, 4, &umr_bitfield_default },
	 { "DP_SEC_ATP_ENABLE", 8, 8, &umr_bitfield_default },
	 { "DP_SEC_AIP_ENABLE", 12, 12, &umr_bitfield_default },
	 { "DP_SEC_ACM_ENABLE", 16, 16, &umr_bitfield_default },
	 { "DP_SEC_GSP0_ENABLE", 20, 20, &umr_bitfield_default },
	 { "DP_SEC_GSP1_ENABLE", 21, 21, &umr_bitfield_default },
	 { "DP_SEC_GSP2_ENABLE", 22, 22, &umr_bitfield_default },
	 { "DP_SEC_GSP3_ENABLE", 23, 23, &umr_bitfield_default },
	 { "DP_SEC_GSP4_ENABLE", 24, 24, &umr_bitfield_default },
	 { "DP_SEC_GSP5_ENABLE", 25, 25, &umr_bitfield_default },
	 { "DP_SEC_GSP6_ENABLE", 26, 26, &umr_bitfield_default },
	 { "DP_SEC_GSP7_ENABLE", 27, 27, &umr_bitfield_default },
	 { "DP_SEC_MPG_ENABLE", 28, 28, &umr_bitfield_default },
};
static struct umr_bitfield mmDP4_DP_SEC_CNTL1[] = {
	 { "DP_SEC_ISRC_ENABLE", 0, 0, &umr_bitfield_default },
	 { "DP_SEC_GSP0_PRIORITY", 4, 4, &umr_bitfield_default },
	 { "DP_SEC_GSP0_SEND", 5, 5, &umr_bitfield_default },
	 { "DP_SEC_GSP0_SEND_PENDING", 6, 6, &umr_bitfield_default },
	 { "DP_SEC_GSP0_SEND_DEADLINE_MISSED", 7, 7, &umr_bitfield_default },
	 { "DP_SEC_GSP0_SEND_ANY_LINE", 8, 8, &umr_bitfield_default },
	 { "DP_SEC_GSP0_LINE_NUM", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDP4_DP_SEC_FRAMING1[] = {
	 { "DP_SEC_FRAME_START_LOCATION", 0, 11, &umr_bitfield_default },
	 { "DP_SEC_VBLANK_TRANSMIT_WIDTH", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDP4_DP_SEC_FRAMING2[] = {
	 { "DP_SEC_START_POSITION", 0, 15, &umr_bitfield_default },
	 { "DP_SEC_HBLANK_TRANSMIT_WIDTH", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDP4_DP_SEC_FRAMING3[] = {
	 { "DP_SEC_IDLE_FRAME_SIZE", 0, 13, &umr_bitfield_default },
	 { "DP_SEC_IDLE_TRANSMIT_WIDTH", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDP4_DP_SEC_FRAMING4[] = {
	 { "DP_SEC_COLLISION_STATUS", 20, 20, &umr_bitfield_default },
	 { "DP_SEC_COLLISION_ACK", 24, 24, &umr_bitfield_default },
	 { "DP_SEC_AUDIO_MUTE", 28, 28, &umr_bitfield_default },
	 { "DP_SEC_AUDIO_MUTE_STATUS", 29, 29, &umr_bitfield_default },
};
static struct umr_bitfield mmDP4_DP_SEC_AUD_N[] = {
	 { "DP_SEC_AUD_N", 0, 23, &umr_bitfield_default },
};
static struct umr_bitfield mmDP4_DP_SEC_AUD_N_READBACK[] = {
	 { "DP_SEC_AUD_N_READBACK", 0, 23, &umr_bitfield_default },
};
static struct umr_bitfield mmDP4_DP_SEC_AUD_M[] = {
	 { "DP_SEC_AUD_M", 0, 23, &umr_bitfield_default },
};
static struct umr_bitfield mmDP4_DP_SEC_AUD_M_READBACK[] = {
	 { "DP_SEC_AUD_M_READBACK", 0, 23, &umr_bitfield_default },
};
static struct umr_bitfield mmDP4_DP_SEC_TIMESTAMP[] = {
	 { "DP_SEC_TIMESTAMP_MODE", 0, 0, &umr_bitfield_default },
};
static struct umr_bitfield mmDP4_DP_SEC_PACKET_CNTL[] = {
	 { "DP_SEC_ASP_CODING_TYPE", 1, 3, &umr_bitfield_default },
	 { "DP_SEC_ASP_PRIORITY", 4, 4, &umr_bitfield_default },
	 { "DP_SEC_VERSION", 8, 13, &umr_bitfield_default },
	 { "DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE", 16, 16, &umr_bitfield_default },
};
static struct umr_bitfield mmDP4_DP_MSE_RATE_CNTL[] = {
	 { "DP_MSE_RATE_Y", 0, 25, &umr_bitfield_default },
	 { "DP_MSE_RATE_X", 26, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDP4_DP_MSE_RATE_UPDATE[] = {
	 { "DP_MSE_RATE_UPDATE_PENDING", 0, 0, &umr_bitfield_default },
};
static struct umr_bitfield mmDP4_DP_MSE_SAT0[] = {
	 { "DP_MSE_SAT_SRC0", 0, 2, &umr_bitfield_default },
	 { "DP_MSE_SAT_SLOT_COUNT0", 8, 13, &umr_bitfield_default },
	 { "DP_MSE_SAT_SRC1", 16, 18, &umr_bitfield_default },
	 { "DP_MSE_SAT_SLOT_COUNT1", 24, 29, &umr_bitfield_default },
};
static struct umr_bitfield mmDP4_DP_MSE_SAT1[] = {
	 { "DP_MSE_SAT_SRC2", 0, 2, &umr_bitfield_default },
	 { "DP_MSE_SAT_SLOT_COUNT2", 8, 13, &umr_bitfield_default },
	 { "DP_MSE_SAT_SRC3", 16, 18, &umr_bitfield_default },
	 { "DP_MSE_SAT_SLOT_COUNT3", 24, 29, &umr_bitfield_default },
};
static struct umr_bitfield mmDP4_DP_MSE_SAT2[] = {
	 { "DP_MSE_SAT_SRC4", 0, 2, &umr_bitfield_default },
	 { "DP_MSE_SAT_SLOT_COUNT4", 8, 13, &umr_bitfield_default },
	 { "DP_MSE_SAT_SRC5", 16, 18, &umr_bitfield_default },
	 { "DP_MSE_SAT_SLOT_COUNT5", 24, 29, &umr_bitfield_default },
};
static struct umr_bitfield mmDP4_DP_MSE_SAT_UPDATE[] = {
	 { "DP_MSE_SAT_UPDATE", 0, 1, &umr_bitfield_default },
	 { "DP_MSE_16_MTP_KEEPOUT", 8, 8, &umr_bitfield_default },
};
static struct umr_bitfield mmDP4_DP_MSE_LINK_TIMING[] = {
	 { "DP_MSE_LINK_FRAME", 0, 9, &umr_bitfield_default },
	 { "DP_MSE_LINK_LINE", 16, 17, &umr_bitfield_default },
};
static struct umr_bitfield mmDP4_DP_MSE_MISC_CNTL[] = {
	 { "DP_MSE_BLANK_CODE", 0, 0, &umr_bitfield_default },
	 { "DP_MSE_TIMESTAMP_MODE", 4, 4, &umr_bitfield_default },
	 { "DP_MSE_ZERO_ENCODER", 8, 8, &umr_bitfield_default },
};
static struct umr_bitfield mmDP4_DP_DPHY_BS_SR_SWAP_CNTL[] = {
	 { "DPHY_LOAD_BS_COUNT", 0, 9, &umr_bitfield_default },
	 { "DPHY_BS_SR_SWAP_DONE", 15, 15, &umr_bitfield_default },
	 { "DPHY_LOAD_BS_COUNT_START", 16, 16, &umr_bitfield_default },
};
static struct umr_bitfield mmDP4_DP_DPHY_HBR2_PATTERN_CONTROL[] = {
	 { "DP_DPHY_HBR2_PATTERN_CONTROL", 0, 2, &umr_bitfield_default },
};
static struct umr_bitfield mmDP4_DP_MSE_SAT0_STATUS[] = {
	 { "DP_MSE_SAT_SRC0_STATUS", 0, 2, &umr_bitfield_default },
	 { "DP_MSE_SAT_SLOT_COUNT0_STATUS", 8, 13, &umr_bitfield_default },
	 { "DP_MSE_SAT_SRC1_STATUS", 16, 18, &umr_bitfield_default },
	 { "DP_MSE_SAT_SLOT_COUNT1_STATUS", 24, 29, &umr_bitfield_default },
};
static struct umr_bitfield mmDP4_DP_MSE_SAT1_STATUS[] = {
	 { "DP_MSE_SAT_SRC2_STATUS", 0, 2, &umr_bitfield_default },
	 { "DP_MSE_SAT_SLOT_COUNT2_STATUS", 8, 13, &umr_bitfield_default },
	 { "DP_MSE_SAT_SRC3_STATUS", 16, 18, &umr_bitfield_default },
	 { "DP_MSE_SAT_SLOT_COUNT3_STATUS", 24, 29, &umr_bitfield_default },
};
static struct umr_bitfield mmDP4_DP_MSE_SAT2_STATUS[] = {
	 { "DP_MSE_SAT_SRC4_STATUS", 0, 2, &umr_bitfield_default },
	 { "DP_MSE_SAT_SLOT_COUNT4_STATUS", 8, 13, &umr_bitfield_default },
	 { "DP_MSE_SAT_SRC5_STATUS", 16, 18, &umr_bitfield_default },
	 { "DP_MSE_SAT_SLOT_COUNT5_STATUS", 24, 29, &umr_bitfield_default },
};
static struct umr_bitfield mmDP4_DP_MSA_TIMING_PARAM1[] = {
	 { "DP_MSA_VTOTAL", 0, 15, &umr_bitfield_default },
	 { "DP_MSA_HTOTAL", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDP4_DP_MSA_TIMING_PARAM2[] = {
	 { "DP_MSA_VSTART", 0, 15, &umr_bitfield_default },
	 { "DP_MSA_HSTART", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDP4_DP_MSA_TIMING_PARAM3[] = {
	 { "DP_MSA_VSYNCWIDTH", 0, 14, &umr_bitfield_default },
	 { "DP_MSA_VSYNCPOLARITY", 15, 15, &umr_bitfield_default },
	 { "DP_MSA_HSYNCWIDTH", 16, 30, &umr_bitfield_default },
	 { "DP_MSA_HSYNCPOLARITY", 31, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDP4_DP_MSA_TIMING_PARAM4[] = {
	 { "DP_MSA_VHEIGHT", 0, 15, &umr_bitfield_default },
	 { "DP_MSA_HWIDTH", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDP4_DP_MSO_CNTL[] = {
	 { "DP_MSO_NUM_OF_SSTLINK", 0, 1, &umr_bitfield_default },
	 { "DP_MSO_SEC_STREAM_ENABLE", 4, 7, &umr_bitfield_default },
	 { "DP_MSO_SEC_ASP_ENABLE", 8, 11, &umr_bitfield_default },
	 { "DP_MSO_SEC_ATP_ENABLE", 12, 15, &umr_bitfield_default },
	 { "DP_MSO_SEC_AIP_ENABLE", 16, 19, &umr_bitfield_default },
	 { "DP_MSO_SEC_ACM_ENABLE", 20, 23, &umr_bitfield_default },
	 { "DP_MSO_SEC_GSP0_ENABLE", 24, 27, &umr_bitfield_default },
	 { "DP_MSO_SEC_GSP1_ENABLE", 28, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDP4_DP_MSO_CNTL1[] = {
	 { "DP_MSO_SEC_GSP2_ENABLE", 0, 3, &umr_bitfield_default },
	 { "DP_MSO_SEC_GSP3_ENABLE", 4, 7, &umr_bitfield_default },
	 { "DP_MSO_SEC_GSP4_ENABLE", 8, 11, &umr_bitfield_default },
	 { "DP_MSO_SEC_GSP5_ENABLE", 12, 15, &umr_bitfield_default },
	 { "DP_MSO_SEC_GSP6_ENABLE", 16, 19, &umr_bitfield_default },
	 { "DP_MSO_SEC_GSP7_ENABLE", 20, 23, &umr_bitfield_default },
	 { "DP_MSO_SEC_MPG_ENABLE", 24, 27, &umr_bitfield_default },
	 { "DP_MSO_SEC_ISRC_ENABLE", 28, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDP4_DP_DSC_CNTL[] = {
	 { "DP_DSC_EN", 0, 0, &umr_bitfield_default },
};
static struct umr_bitfield mmDP4_DP_SEC_CNTL2[] = {
	 { "DP_SEC_GSP1_SEND", 0, 0, &umr_bitfield_default },
	 { "DP_SEC_GSP1_SEND_PENDING", 1, 1, &umr_bitfield_default },
	 { "DP_SEC_GSP1_SEND_DEADLINE_MISSED", 2, 2, &umr_bitfield_default },
	 { "DP_SEC_GSP1_SEND_ANY_LINE", 3, 3, &umr_bitfield_default },
	 { "DP_SEC_GSP2_SEND", 4, 4, &umr_bitfield_default },
	 { "DP_SEC_GSP2_SEND_PENDING", 5, 5, &umr_bitfield_default },
	 { "DP_SEC_GSP2_SEND_DEADLINE_MISSED", 6, 6, &umr_bitfield_default },
	 { "DP_SEC_GSP2_SEND_ANY_LINE", 7, 7, &umr_bitfield_default },
	 { "DP_SEC_GSP3_SEND", 8, 8, &umr_bitfield_default },
	 { "DP_SEC_GSP3_SEND_PENDING", 9, 9, &umr_bitfield_default },
	 { "DP_SEC_GSP3_SEND_DEADLINE_MISSED", 10, 10, &umr_bitfield_default },
	 { "DP_SEC_GSP3_SEND_ANY_LINE", 11, 11, &umr_bitfield_default },
	 { "DP_SEC_GSP4_SEND", 12, 12, &umr_bitfield_default },
	 { "DP_SEC_GSP4_SEND_PENDING", 13, 13, &umr_bitfield_default },
	 { "DP_SEC_GSP4_SEND_DEADLINE_MISSED", 14, 14, &umr_bitfield_default },
	 { "DP_SEC_GSP4_SEND_ANY_LINE", 15, 15, &umr_bitfield_default },
	 { "DP_SEC_GSP5_SEND", 16, 16, &umr_bitfield_default },
	 { "DP_SEC_GSP5_SEND_PENDING", 17, 17, &umr_bitfield_default },
	 { "DP_SEC_GSP5_SEND_DEADLINE_MISSED", 18, 18, &umr_bitfield_default },
	 { "DP_SEC_GSP5_SEND_ANY_LINE", 19, 19, &umr_bitfield_default },
	 { "DP_SEC_GSP6_SEND", 20, 20, &umr_bitfield_default },
	 { "DP_SEC_GSP6_SEND_PENDING", 21, 21, &umr_bitfield_default },
	 { "DP_SEC_GSP6_SEND_DEADLINE_MISSED", 22, 22, &umr_bitfield_default },
	 { "DP_SEC_GSP6_SEND_ANY_LINE", 23, 23, &umr_bitfield_default },
	 { "DP_SEC_GSP7_SEND", 24, 24, &umr_bitfield_default },
	 { "DP_SEC_GSP7_SEND_PENDING", 25, 25, &umr_bitfield_default },
	 { "DP_SEC_GSP7_SEND_DEADLINE_MISSED", 26, 26, &umr_bitfield_default },
	 { "DP_SEC_GSP7_SEND_ANY_LINE", 27, 27, &umr_bitfield_default },
	 { "DP_SEC_GSP7_PPS", 28, 28, &umr_bitfield_default },
};
static struct umr_bitfield mmDP4_DP_SEC_CNTL3[] = {
	 { "DP_SEC_GSP1_LINE_NUM", 0, 15, &umr_bitfield_default },
	 { "DP_SEC_GSP2_LINE_NUM", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDP4_DP_SEC_CNTL4[] = {
	 { "DP_SEC_GSP3_LINE_NUM", 0, 15, &umr_bitfield_default },
	 { "DP_SEC_GSP4_LINE_NUM", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDP4_DP_SEC_CNTL5[] = {
	 { "DP_SEC_GSP5_LINE_NUM", 0, 15, &umr_bitfield_default },
	 { "DP_SEC_GSP6_LINE_NUM", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDP4_DP_SEC_CNTL6[] = {
	 { "DP_SEC_GSP7_LINE_NUM", 0, 15, &umr_bitfield_default },
};
static struct umr_bitfield mmDP4_DP_SEC_CNTL7[] = {
	 { "DP_SEC_GSP0_SEND_ACTIVE", 0, 0, &umr_bitfield_default },
	 { "DP_SEC_GSP1_SEND_ACTIVE", 4, 4, &umr_bitfield_default },
	 { "DP_SEC_GSP2_SEND_ACTIVE", 8, 8, &umr_bitfield_default },
	 { "DP_SEC_GSP3_SEND_ACTIVE", 12, 12, &umr_bitfield_default },
	 { "DP_SEC_GSP4_SEND_ACTIVE", 16, 16, &umr_bitfield_default },
	 { "DP_SEC_GSP5_SEND_ACTIVE", 20, 20, &umr_bitfield_default },
	 { "DP_SEC_GSP6_SEND_ACTIVE", 24, 24, &umr_bitfield_default },
	 { "DP_SEC_GSP7_SEND_ACTIVE", 28, 28, &umr_bitfield_default },
};
static struct umr_bitfield mmDP4_DP_DB_CNTL[] = {
	 { "DP_DB_PENDING", 0, 0, &umr_bitfield_default },
	 { "DP_DB_TAKEN", 4, 4, &umr_bitfield_default },
	 { "DP_DB_TAKEN_CLR", 5, 5, &umr_bitfield_default },
	 { "DP_DB_LOCK", 8, 8, &umr_bitfield_default },
	 { "DP_DB_DISABLE", 12, 12, &umr_bitfield_default },
};
static struct umr_bitfield mmDP4_DP_MSA_VBID_MISC[] = {
	 { "DP_MSA_MISC1_STEREOSYNC_OVERRIDE", 0, 1, &umr_bitfield_default },
	 { "DP_MSA_MISC1_STEREOSYNC_OVERRIDE_EN", 4, 4, &umr_bitfield_default },
	 { "DP_VBID1_OVERRIDE", 8, 8, &umr_bitfield_default },
	 { "DP_VBID2_OVERRIDE", 9, 9, &umr_bitfield_default },
	 { "DP_VBID1_OVERRIDE_EN", 12, 12, &umr_bitfield_default },
	 { "DP_VBID2_OVERRIDE_EN", 13, 13, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG5_DIG_FE_CNTL[] = {
	 { "DIG_SOURCE_SELECT", 0, 2, &umr_bitfield_default },
	 { "DIG_STEREOSYNC_SELECT", 4, 6, &umr_bitfield_default },
	 { "DIG_STEREOSYNC_GATE_EN", 8, 8, &umr_bitfield_default },
	 { "DIG_START", 10, 10, &umr_bitfield_default },
	 { "DIG_DIGITAL_BYPASS_SELECT", 12, 14, &umr_bitfield_default },
	 { "DIG_SYMCLK_FE_ON", 24, 24, &umr_bitfield_default },
	 { "TMDS_PIXEL_ENCODING", 28, 28, &umr_bitfield_default },
	 { "TMDS_COLOR_FORMAT", 30, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG5_DIG_OUTPUT_CRC_CNTL[] = {
	 { "DIG_OUTPUT_CRC_EN", 0, 0, &umr_bitfield_default },
	 { "DIG_OUTPUT_CRC_LINK_SEL", 4, 4, &umr_bitfield_default },
	 { "DIG_OUTPUT_CRC_DATA_SEL", 8, 9, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG5_DIG_OUTPUT_CRC_RESULT[] = {
	 { "DIG_OUTPUT_CRC_RESULT", 0, 29, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG5_DIG_CLOCK_PATTERN[] = {
	 { "DIG_CLOCK_PATTERN", 0, 9, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG5_DIG_TEST_PATTERN[] = {
	 { "DIG_TEST_PATTERN_OUT_EN", 0, 0, &umr_bitfield_default },
	 { "DIG_HALF_CLOCK_PATTERN_SEL", 1, 1, &umr_bitfield_default },
	 { "DIG_RANDOM_PATTERN_OUT_EN", 4, 4, &umr_bitfield_default },
	 { "DIG_RANDOM_PATTERN_RESET", 5, 5, &umr_bitfield_default },
	 { "DIG_TEST_PATTERN_EXTERNAL_RESET_EN", 6, 6, &umr_bitfield_default },
	 { "DIG_STATIC_TEST_PATTERN", 16, 25, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG5_DIG_RANDOM_PATTERN_SEED[] = {
	 { "DIG_RANDOM_PATTERN_SEED", 0, 23, &umr_bitfield_default },
	 { "DIG_RAN_PAT_DURING_DE_ONLY", 24, 24, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG5_DIG_FIFO_STATUS[] = {
	 { "DIG_FIFO_LEVEL_ERROR", 0, 0, &umr_bitfield_default },
	 { "DIG_FIFO_USE_OVERWRITE_LEVEL", 1, 1, &umr_bitfield_default },
	 { "DIG_FIFO_OVERWRITE_LEVEL", 2, 7, &umr_bitfield_default },
	 { "DIG_FIFO_ERROR_ACK", 8, 8, &umr_bitfield_default },
	 { "DIG_FIFO_CAL_AVERAGE_LEVEL", 10, 15, &umr_bitfield_default },
	 { "DIG_FIFO_MAXIMUM_LEVEL", 16, 20, &umr_bitfield_default },
	 { "DIG_FIFO_MINIMUM_LEVEL", 22, 25, &umr_bitfield_default },
	 { "DIG_FIFO_READ_CLOCK_SRC", 26, 26, &umr_bitfield_default },
	 { "DIG_FIFO_CALIBRATED", 29, 29, &umr_bitfield_default },
	 { "DIG_FIFO_FORCE_RECAL_AVERAGE", 30, 30, &umr_bitfield_default },
	 { "DIG_FIFO_FORCE_RECOMP_MINMAX", 31, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG5_HDMI_CONTROL[] = {
	 { "HDMI_KEEPOUT_MODE", 0, 0, &umr_bitfield_default },
	 { "HDMI_DATA_SCRAMBLE_EN", 1, 1, &umr_bitfield_default },
	 { "HDMI_CLOCK_CHANNEL_RATE", 2, 2, &umr_bitfield_default },
	 { "HDMI_NO_EXTRA_NULL_PACKET_FILLED", 3, 3, &umr_bitfield_default },
	 { "HDMI_PACKET_GEN_VERSION", 4, 4, &umr_bitfield_default },
	 { "HDMI_ERROR_ACK", 8, 8, &umr_bitfield_default },
	 { "HDMI_ERROR_MASK", 9, 9, &umr_bitfield_default },
	 { "HDMI_DEEP_COLOR_ENABLE", 24, 24, &umr_bitfield_default },
	 { "HDMI_DEEP_COLOR_DEPTH", 28, 29, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG5_HDMI_STATUS[] = {
	 { "HDMI_ACTIVE_AVMUTE", 0, 0, &umr_bitfield_default },
	 { "HDMI_AUDIO_PACKET_ERROR", 16, 16, &umr_bitfield_default },
	 { "HDMI_VBI_PACKET_ERROR", 20, 20, &umr_bitfield_default },
	 { "HDMI_ERROR_INT", 27, 27, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG5_HDMI_AUDIO_PACKET_CONTROL[] = {
	 { "HDMI_AUDIO_DELAY_EN", 4, 5, &umr_bitfield_default },
	 { "HDMI_AUDIO_PACKETS_PER_LINE", 16, 20, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG5_HDMI_ACR_PACKET_CONTROL[] = {
	 { "HDMI_ACR_SEND", 0, 0, &umr_bitfield_default },
	 { "HDMI_ACR_CONT", 1, 1, &umr_bitfield_default },
	 { "HDMI_ACR_SELECT", 4, 5, &umr_bitfield_default },
	 { "HDMI_ACR_SOURCE", 8, 8, &umr_bitfield_default },
	 { "HDMI_ACR_AUTO_SEND", 12, 12, &umr_bitfield_default },
	 { "HDMI_ACR_N_MULTIPLE", 16, 18, &umr_bitfield_default },
	 { "HDMI_ACR_AUDIO_PRIORITY", 31, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG5_HDMI_VBI_PACKET_CONTROL[] = {
	 { "HDMI_NULL_SEND", 0, 0, &umr_bitfield_default },
	 { "HDMI_GC_SEND", 4, 4, &umr_bitfield_default },
	 { "HDMI_GC_CONT", 5, 5, &umr_bitfield_default },
	 { "HDMI_ISRC_SEND", 8, 8, &umr_bitfield_default },
	 { "HDMI_ISRC_CONT", 9, 9, &umr_bitfield_default },
	 { "HDMI_ISRC_LINE", 16, 21, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG5_HDMI_INFOFRAME_CONTROL0[] = {
	 { "HDMI_AUDIO_INFO_SEND", 4, 4, &umr_bitfield_default },
	 { "HDMI_AUDIO_INFO_CONT", 5, 5, &umr_bitfield_default },
	 { "HDMI_MPEG_INFO_SEND", 8, 8, &umr_bitfield_default },
	 { "HDMI_MPEG_INFO_CONT", 9, 9, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG5_HDMI_INFOFRAME_CONTROL1[] = {
	 { "HDMI_AUDIO_INFO_LINE", 8, 13, &umr_bitfield_default },
	 { "HDMI_MPEG_INFO_LINE", 16, 21, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG5_HDMI_GENERIC_PACKET_CONTROL0[] = {
	 { "HDMI_GENERIC0_SEND", 0, 0, &umr_bitfield_default },
	 { "HDMI_GENERIC0_CONT", 1, 1, &umr_bitfield_default },
	 { "HDMI_GENERIC1_SEND", 4, 4, &umr_bitfield_default },
	 { "HDMI_GENERIC1_CONT", 5, 5, &umr_bitfield_default },
	 { "HDMI_GENERIC0_LINE", 16, 21, &umr_bitfield_default },
	 { "HDMI_GENERIC1_LINE", 24, 29, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG5_HDMI_GC[] = {
	 { "HDMI_GC_AVMUTE", 0, 0, &umr_bitfield_default },
	 { "HDMI_GC_AVMUTE_CONT", 2, 2, &umr_bitfield_default },
	 { "HDMI_DEFAULT_PHASE", 4, 4, &umr_bitfield_default },
	 { "HDMI_PACKING_PHASE", 8, 11, &umr_bitfield_default },
	 { "HDMI_PACKING_PHASE_OVERRIDE", 12, 12, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG5_AFMT_AUDIO_PACKET_CONTROL2[] = {
	 { "AFMT_AUDIO_LAYOUT_OVRD", 0, 0, &umr_bitfield_default },
	 { "AFMT_AUDIO_LAYOUT_SELECT", 1, 1, &umr_bitfield_default },
	 { "AFMT_AUDIO_CHANNEL_ENABLE", 8, 15, &umr_bitfield_default },
	 { "AFMT_DP_AUDIO_STREAM_ID", 16, 23, &umr_bitfield_default },
	 { "AFMT_HBR_ENABLE_OVRD", 24, 24, &umr_bitfield_default },
	 { "AFMT_60958_OSF_OVRD", 28, 28, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG5_AFMT_ISRC1_0[] = {
	 { "AFMT_ISRC_STATUS", 0, 2, &umr_bitfield_default },
	 { "AFMT_ISRC_CONTINUE", 6, 6, &umr_bitfield_default },
	 { "AFMT_ISRC_VALID", 7, 7, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG5_AFMT_ISRC1_1[] = {
	 { "AFMT_UPC_EAN_ISRC0", 0, 7, &umr_bitfield_default },
	 { "AFMT_UPC_EAN_ISRC1", 8, 15, &umr_bitfield_default },
	 { "AFMT_UPC_EAN_ISRC2", 16, 23, &umr_bitfield_default },
	 { "AFMT_UPC_EAN_ISRC3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG5_AFMT_ISRC1_2[] = {
	 { "AFMT_UPC_EAN_ISRC4", 0, 7, &umr_bitfield_default },
	 { "AFMT_UPC_EAN_ISRC5", 8, 15, &umr_bitfield_default },
	 { "AFMT_UPC_EAN_ISRC6", 16, 23, &umr_bitfield_default },
	 { "AFMT_UPC_EAN_ISRC7", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG5_AFMT_ISRC1_3[] = {
	 { "AFMT_UPC_EAN_ISRC8", 0, 7, &umr_bitfield_default },
	 { "AFMT_UPC_EAN_ISRC9", 8, 15, &umr_bitfield_default },
	 { "AFMT_UPC_EAN_ISRC10", 16, 23, &umr_bitfield_default },
	 { "AFMT_UPC_EAN_ISRC11", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG5_AFMT_ISRC1_4[] = {
	 { "AFMT_UPC_EAN_ISRC12", 0, 7, &umr_bitfield_default },
	 { "AFMT_UPC_EAN_ISRC13", 8, 15, &umr_bitfield_default },
	 { "AFMT_UPC_EAN_ISRC14", 16, 23, &umr_bitfield_default },
	 { "AFMT_UPC_EAN_ISRC15", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG5_AFMT_ISRC2_0[] = {
	 { "AFMT_UPC_EAN_ISRC16", 0, 7, &umr_bitfield_default },
	 { "AFMT_UPC_EAN_ISRC17", 8, 15, &umr_bitfield_default },
	 { "AFMT_UPC_EAN_ISRC18", 16, 23, &umr_bitfield_default },
	 { "AFMT_UPC_EAN_ISRC19", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG5_AFMT_ISRC2_1[] = {
	 { "AFMT_UPC_EAN_ISRC20", 0, 7, &umr_bitfield_default },
	 { "AFMT_UPC_EAN_ISRC21", 8, 15, &umr_bitfield_default },
	 { "AFMT_UPC_EAN_ISRC22", 16, 23, &umr_bitfield_default },
	 { "AFMT_UPC_EAN_ISRC23", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG5_AFMT_ISRC2_2[] = {
	 { "AFMT_UPC_EAN_ISRC24", 0, 7, &umr_bitfield_default },
	 { "AFMT_UPC_EAN_ISRC25", 8, 15, &umr_bitfield_default },
	 { "AFMT_UPC_EAN_ISRC26", 16, 23, &umr_bitfield_default },
	 { "AFMT_UPC_EAN_ISRC27", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG5_AFMT_ISRC2_3[] = {
	 { "AFMT_UPC_EAN_ISRC28", 0, 7, &umr_bitfield_default },
	 { "AFMT_UPC_EAN_ISRC29", 8, 15, &umr_bitfield_default },
	 { "AFMT_UPC_EAN_ISRC30", 16, 23, &umr_bitfield_default },
	 { "AFMT_UPC_EAN_ISRC31", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG5_HDMI_GENERIC_PACKET_CONTROL2[] = {
	 { "HDMI_GENERIC4_SEND", 0, 0, &umr_bitfield_default },
	 { "HDMI_GENERIC4_CONT", 1, 1, &umr_bitfield_default },
	 { "HDMI_GENERIC5_SEND", 4, 4, &umr_bitfield_default },
	 { "HDMI_GENERIC5_CONT", 5, 5, &umr_bitfield_default },
	 { "HDMI_GENERIC4_LINE", 16, 21, &umr_bitfield_default },
	 { "HDMI_GENERIC5_LINE", 24, 29, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG5_HDMI_GENERIC_PACKET_CONTROL3[] = {
	 { "HDMI_GENERIC6_SEND", 0, 0, &umr_bitfield_default },
	 { "HDMI_GENERIC6_CONT", 1, 1, &umr_bitfield_default },
	 { "HDMI_GENERIC7_SEND", 4, 4, &umr_bitfield_default },
	 { "HDMI_GENERIC7_CONT", 5, 5, &umr_bitfield_default },
	 { "HDMI_GENERIC6_LINE", 16, 21, &umr_bitfield_default },
	 { "HDMI_GENERIC7_LINE", 24, 29, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG5_HDMI_DB_CONTROL[] = {
	 { "HDMI_DB_PENDING", 0, 0, &umr_bitfield_default },
	 { "HDMI_DB_TAKEN", 4, 4, &umr_bitfield_default },
	 { "HDMI_DB_TAKEN_CLR", 5, 5, &umr_bitfield_default },
	 { "HDMI_DB_LOCK", 8, 8, &umr_bitfield_default },
	 { "HDMI_DB_DISABLE", 12, 12, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG5_AFMT_MPEG_INFO0[] = {
	 { "AFMT_MPEG_INFO_CHECKSUM", 0, 7, &umr_bitfield_default },
	 { "AFMT_MPEG_INFO_MB0", 8, 15, &umr_bitfield_default },
	 { "AFMT_MPEG_INFO_MB1", 16, 23, &umr_bitfield_default },
	 { "AFMT_MPEG_INFO_MB2", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG5_AFMT_MPEG_INFO1[] = {
	 { "AFMT_MPEG_INFO_MB3", 0, 7, &umr_bitfield_default },
	 { "AFMT_MPEG_INFO_MF", 8, 9, &umr_bitfield_default },
	 { "AFMT_MPEG_INFO_FR", 12, 12, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG5_AFMT_GENERIC_HDR[] = {
	 { "AFMT_GENERIC_HB0", 0, 7, &umr_bitfield_default },
	 { "AFMT_GENERIC_HB1", 8, 15, &umr_bitfield_default },
	 { "AFMT_GENERIC_HB2", 16, 23, &umr_bitfield_default },
	 { "AFMT_GENERIC_HB3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG5_AFMT_GENERIC_0[] = {
	 { "AFMT_GENERIC_BYTE0", 0, 7, &umr_bitfield_default },
	 { "AFMT_GENERIC_BYTE1", 8, 15, &umr_bitfield_default },
	 { "AFMT_GENERIC_BYTE2", 16, 23, &umr_bitfield_default },
	 { "AFMT_GENERIC_BYTE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG5_AFMT_GENERIC_1[] = {
	 { "AFMT_GENERIC_BYTE4", 0, 7, &umr_bitfield_default },
	 { "AFMT_GENERIC_BYTE5", 8, 15, &umr_bitfield_default },
	 { "AFMT_GENERIC_BYTE6", 16, 23, &umr_bitfield_default },
	 { "AFMT_GENERIC_BYTE7", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG5_AFMT_GENERIC_2[] = {
	 { "AFMT_GENERIC_BYTE8", 0, 7, &umr_bitfield_default },
	 { "AFMT_GENERIC_BYTE9", 8, 15, &umr_bitfield_default },
	 { "AFMT_GENERIC_BYTE10", 16, 23, &umr_bitfield_default },
	 { "AFMT_GENERIC_BYTE11", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG5_AFMT_GENERIC_3[] = {
	 { "AFMT_GENERIC_BYTE12", 0, 7, &umr_bitfield_default },
	 { "AFMT_GENERIC_BYTE13", 8, 15, &umr_bitfield_default },
	 { "AFMT_GENERIC_BYTE14", 16, 23, &umr_bitfield_default },
	 { "AFMT_GENERIC_BYTE15", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG5_AFMT_GENERIC_4[] = {
	 { "AFMT_GENERIC_BYTE16", 0, 7, &umr_bitfield_default },
	 { "AFMT_GENERIC_BYTE17", 8, 15, &umr_bitfield_default },
	 { "AFMT_GENERIC_BYTE18", 16, 23, &umr_bitfield_default },
	 { "AFMT_GENERIC_BYTE19", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG5_AFMT_GENERIC_5[] = {
	 { "AFMT_GENERIC_BYTE20", 0, 7, &umr_bitfield_default },
	 { "AFMT_GENERIC_BYTE21", 8, 15, &umr_bitfield_default },
	 { "AFMT_GENERIC_BYTE22", 16, 23, &umr_bitfield_default },
	 { "AFMT_GENERIC_BYTE23", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG5_AFMT_GENERIC_6[] = {
	 { "AFMT_GENERIC_BYTE24", 0, 7, &umr_bitfield_default },
	 { "AFMT_GENERIC_BYTE25", 8, 15, &umr_bitfield_default },
	 { "AFMT_GENERIC_BYTE26", 16, 23, &umr_bitfield_default },
	 { "AFMT_GENERIC_BYTE27", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG5_AFMT_GENERIC_7[] = {
	 { "AFMT_GENERIC_BYTE28", 0, 7, &umr_bitfield_default },
	 { "AFMT_GENERIC_BYTE29", 8, 15, &umr_bitfield_default },
	 { "AFMT_GENERIC_BYTE30", 16, 23, &umr_bitfield_default },
	 { "AFMT_GENERIC_BYTE31", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG5_HDMI_GENERIC_PACKET_CONTROL1[] = {
	 { "HDMI_GENERIC2_SEND", 0, 0, &umr_bitfield_default },
	 { "HDMI_GENERIC2_CONT", 1, 1, &umr_bitfield_default },
	 { "HDMI_GENERIC3_SEND", 4, 4, &umr_bitfield_default },
	 { "HDMI_GENERIC3_CONT", 5, 5, &umr_bitfield_default },
	 { "HDMI_GENERIC2_LINE", 16, 21, &umr_bitfield_default },
	 { "HDMI_GENERIC3_LINE", 24, 29, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG5_HDMI_ACR_32_0[] = {
	 { "HDMI_ACR_CTS_32", 12, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG5_HDMI_ACR_32_1[] = {
	 { "HDMI_ACR_N_32", 0, 19, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG5_HDMI_ACR_44_0[] = {
	 { "HDMI_ACR_CTS_44", 12, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG5_HDMI_ACR_44_1[] = {
	 { "HDMI_ACR_N_44", 0, 19, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG5_HDMI_ACR_48_0[] = {
	 { "HDMI_ACR_CTS_48", 12, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG5_HDMI_ACR_48_1[] = {
	 { "HDMI_ACR_N_48", 0, 19, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG5_HDMI_ACR_STATUS_0[] = {
	 { "HDMI_ACR_CTS", 12, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG5_HDMI_ACR_STATUS_1[] = {
	 { "HDMI_ACR_N", 0, 19, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG5_AFMT_AUDIO_INFO0[] = {
	 { "AFMT_AUDIO_INFO_CHECKSUM", 0, 7, &umr_bitfield_default },
	 { "AFMT_AUDIO_INFO_CC", 8, 10, &umr_bitfield_default },
	 { "AFMT_AUDIO_INFO_CT", 11, 14, &umr_bitfield_default },
	 { "AFMT_AUDIO_INFO_CHECKSUM_OFFSET", 16, 23, &umr_bitfield_default },
	 { "AFMT_AUDIO_INFO_CXT", 24, 28, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG5_AFMT_AUDIO_INFO1[] = {
	 { "AFMT_AUDIO_INFO_CA", 0, 7, &umr_bitfield_default },
	 { "AFMT_AUDIO_INFO_LSV", 11, 14, &umr_bitfield_default },
	 { "AFMT_AUDIO_INFO_DM_INH", 15, 15, &umr_bitfield_default },
	 { "AFMT_AUDIO_INFO_LFEPBL", 16, 17, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG5_AFMT_60958_0[] = {
	 { "AFMT_60958_CS_A", 0, 0, &umr_bitfield_default },
	 { "AFMT_60958_CS_B", 1, 1, &umr_bitfield_default },
	 { "AFMT_60958_CS_C", 2, 2, &umr_bitfield_default },
	 { "AFMT_60958_CS_D", 3, 5, &umr_bitfield_default },
	 { "AFMT_60958_CS_MODE", 6, 7, &umr_bitfield_default },
	 { "AFMT_60958_CS_CATEGORY_CODE", 8, 15, &umr_bitfield_default },
	 { "AFMT_60958_CS_SOURCE_NUMBER", 16, 19, &umr_bitfield_default },
	 { "AFMT_60958_CS_CHANNEL_NUMBER_L", 20, 23, &umr_bitfield_default },
	 { "AFMT_60958_CS_SAMPLING_FREQUENCY", 24, 27, &umr_bitfield_default },
	 { "AFMT_60958_CS_CLOCK_ACCURACY", 28, 29, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG5_AFMT_60958_1[] = {
	 { "AFMT_60958_CS_WORD_LENGTH", 0, 3, &umr_bitfield_default },
	 { "AFMT_60958_CS_ORIGINAL_SAMPLING_FREQUENCY", 4, 7, &umr_bitfield_default },
	 { "AFMT_60958_VALID_L", 16, 16, &umr_bitfield_default },
	 { "AFMT_60958_VALID_R", 18, 18, &umr_bitfield_default },
	 { "AFMT_60958_CS_CHANNEL_NUMBER_R", 20, 23, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG5_AFMT_AUDIO_CRC_CONTROL[] = {
	 { "AFMT_AUDIO_CRC_EN", 0, 0, &umr_bitfield_default },
	 { "AFMT_AUDIO_CRC_CONT", 4, 4, &umr_bitfield_default },
	 { "AFMT_AUDIO_CRC_SOURCE", 8, 8, &umr_bitfield_default },
	 { "AFMT_AUDIO_CRC_CH_SEL", 12, 15, &umr_bitfield_default },
	 { "AFMT_AUDIO_CRC_COUNT", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG5_AFMT_RAMP_CONTROL0[] = {
	 { "AFMT_RAMP_MAX_COUNT", 0, 23, &umr_bitfield_default },
	 { "AFMT_RAMP_DATA_SIGN", 31, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG5_AFMT_RAMP_CONTROL1[] = {
	 { "AFMT_RAMP_MIN_COUNT", 0, 23, &umr_bitfield_default },
	 { "AFMT_AUDIO_TEST_CH_DISABLE", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG5_AFMT_RAMP_CONTROL2[] = {
	 { "AFMT_RAMP_INC_COUNT", 0, 23, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG5_AFMT_RAMP_CONTROL3[] = {
	 { "AFMT_RAMP_DEC_COUNT", 0, 23, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG5_AFMT_60958_2[] = {
	 { "AFMT_60958_CS_CHANNEL_NUMBER_2", 0, 3, &umr_bitfield_default },
	 { "AFMT_60958_CS_CHANNEL_NUMBER_3", 4, 7, &umr_bitfield_default },
	 { "AFMT_60958_CS_CHANNEL_NUMBER_4", 8, 11, &umr_bitfield_default },
	 { "AFMT_60958_CS_CHANNEL_NUMBER_5", 12, 15, &umr_bitfield_default },
	 { "AFMT_60958_CS_CHANNEL_NUMBER_6", 16, 19, &umr_bitfield_default },
	 { "AFMT_60958_CS_CHANNEL_NUMBER_7", 20, 23, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG5_AFMT_AUDIO_CRC_RESULT[] = {
	 { "AFMT_AUDIO_CRC_DONE", 0, 0, &umr_bitfield_default },
	 { "AFMT_AUDIO_CRC", 8, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG5_AFMT_STATUS[] = {
	 { "AFMT_AUDIO_ENABLE", 4, 4, &umr_bitfield_default },
	 { "AFMT_AZ_HBR_ENABLE", 8, 8, &umr_bitfield_default },
	 { "AFMT_AUDIO_FIFO_OVERFLOW", 24, 24, &umr_bitfield_default },
	 { "AFMT_AZ_AUDIO_ENABLE_CHG", 30, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG5_AFMT_AUDIO_PACKET_CONTROL[] = {
	 { "AFMT_AUDIO_SAMPLE_SEND", 0, 0, &umr_bitfield_default },
	 { "AFMT_RESET_FIFO_WHEN_AUDIO_DIS", 11, 11, &umr_bitfield_default },
	 { "AFMT_AUDIO_TEST_EN", 12, 12, &umr_bitfield_default },
	 { "AFMT_AUDIO_TEST_MODE", 14, 14, &umr_bitfield_default },
	 { "AFMT_AUDIO_FIFO_OVERFLOW_ACK", 23, 23, &umr_bitfield_default },
	 { "AFMT_AUDIO_CHANNEL_SWAP", 24, 24, &umr_bitfield_default },
	 { "AFMT_60958_CS_UPDATE", 26, 26, &umr_bitfield_default },
	 { "AFMT_AZ_AUDIO_ENABLE_CHG_ACK", 30, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG5_AFMT_VBI_PACKET_CONTROL[] = {
	 { "AFMT_GENERIC_LOCK_STATUS", 8, 8, &umr_bitfield_default },
	 { "AFMT_GENERIC_CONFLICT", 16, 16, &umr_bitfield_default },
	 { "AFMT_GENERIC_CONFLICT_CLR", 17, 17, &umr_bitfield_default },
	 { "AFMT_GENERIC_INDEX", 28, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG5_AFMT_INFOFRAME_CONTROL0[] = {
	 { "AFMT_AUDIO_INFO_SOURCE", 6, 6, &umr_bitfield_default },
	 { "AFMT_AUDIO_INFO_UPDATE", 7, 7, &umr_bitfield_default },
	 { "AFMT_MPEG_INFO_UPDATE", 10, 10, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG5_AFMT_AUDIO_SRC_CONTROL[] = {
	 { "AFMT_AUDIO_SRC_SELECT", 0, 2, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG5_DIG_BE_CNTL[] = {
	 { "DIG_DUAL_LINK_ENABLE", 0, 0, &umr_bitfield_default },
	 { "DIG_SWAP", 1, 1, &umr_bitfield_default },
	 { "DIG_FE_SOURCE_SELECT", 8, 14, &umr_bitfield_default },
	 { "DIG_MODE", 16, 18, &umr_bitfield_default },
	 { "DIG_HPD_SELECT", 28, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG5_DIG_BE_EN_CNTL[] = {
	 { "DIG_ENABLE", 0, 0, &umr_bitfield_default },
	 { "DIG_SYMCLK_BE_ON", 8, 8, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG5_TMDS_CNTL[] = {
	 { "TMDS_SYNC_PHASE", 0, 0, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG5_TMDS_CONTROL_CHAR[] = {
	 { "TMDS_CONTROL_CHAR0_OUT_EN", 0, 0, &umr_bitfield_default },
	 { "TMDS_CONTROL_CHAR1_OUT_EN", 1, 1, &umr_bitfield_default },
	 { "TMDS_CONTROL_CHAR2_OUT_EN", 2, 2, &umr_bitfield_default },
	 { "TMDS_CONTROL_CHAR3_OUT_EN", 3, 3, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG5_TMDS_CONTROL0_FEEDBACK[] = {
	 { "TMDS_CONTROL0_FEEDBACK_SELECT", 0, 1, &umr_bitfield_default },
	 { "TMDS_CONTROL0_FEEDBACK_DELAY", 8, 9, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG5_TMDS_STEREOSYNC_CTL_SEL[] = {
	 { "TMDS_STEREOSYNC_CTL_SEL", 0, 1, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG5_TMDS_SYNC_CHAR_PATTERN_0_1[] = {
	 { "TMDS_SYNC_CHAR_PATTERN0", 0, 9, &umr_bitfield_default },
	 { "TMDS_SYNC_CHAR_PATTERN1", 16, 25, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG5_TMDS_SYNC_CHAR_PATTERN_2_3[] = {
	 { "TMDS_SYNC_CHAR_PATTERN2", 0, 9, &umr_bitfield_default },
	 { "TMDS_SYNC_CHAR_PATTERN3", 16, 25, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG5_TMDS_CTL_BITS[] = {
	 { "TMDS_CTL0", 0, 0, &umr_bitfield_default },
	 { "TMDS_CTL1", 8, 8, &umr_bitfield_default },
	 { "TMDS_CTL2", 16, 16, &umr_bitfield_default },
	 { "TMDS_CTL3", 24, 24, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG5_TMDS_DCBALANCER_CONTROL[] = {
	 { "TMDS_DCBALANCER_EN", 0, 0, &umr_bitfield_default },
	 { "TMDS_DCBALANCER_TEST_EN", 8, 8, &umr_bitfield_default },
	 { "TMDS_DCBALANCER_TEST_IN", 16, 19, &umr_bitfield_default },
	 { "TMDS_DCBALANCER_FORCE", 24, 24, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG5_TMDS_CTL0_1_GEN_CNTL[] = {
	 { "TMDS_CTL0_DATA_SEL", 0, 3, &umr_bitfield_default },
	 { "TMDS_CTL0_DATA_DELAY", 4, 6, &umr_bitfield_default },
	 { "TMDS_CTL0_DATA_INVERT", 7, 7, &umr_bitfield_default },
	 { "TMDS_CTL0_DATA_MODULATION", 8, 9, &umr_bitfield_default },
	 { "TMDS_CTL0_USE_FEEDBACK_PATH", 10, 10, &umr_bitfield_default },
	 { "TMDS_CTL0_FB_SYNC_CONT", 11, 11, &umr_bitfield_default },
	 { "TMDS_CTL0_PATTERN_OUT_EN", 12, 12, &umr_bitfield_default },
	 { "TMDS_CTL1_DATA_SEL", 16, 19, &umr_bitfield_default },
	 { "TMDS_CTL1_DATA_DELAY", 20, 22, &umr_bitfield_default },
	 { "TMDS_CTL1_DATA_INVERT", 23, 23, &umr_bitfield_default },
	 { "TMDS_CTL1_DATA_MODULATION", 24, 25, &umr_bitfield_default },
	 { "TMDS_CTL1_USE_FEEDBACK_PATH", 26, 26, &umr_bitfield_default },
	 { "TMDS_CTL1_FB_SYNC_CONT", 27, 27, &umr_bitfield_default },
	 { "TMDS_CTL1_PATTERN_OUT_EN", 28, 28, &umr_bitfield_default },
	 { "TMDS_2BIT_COUNTER_EN", 31, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG5_TMDS_CTL2_3_GEN_CNTL[] = {
	 { "TMDS_CTL2_DATA_SEL", 0, 3, &umr_bitfield_default },
	 { "TMDS_CTL2_DATA_DELAY", 4, 6, &umr_bitfield_default },
	 { "TMDS_CTL2_DATA_INVERT", 7, 7, &umr_bitfield_default },
	 { "TMDS_CTL2_DATA_MODULATION", 8, 9, &umr_bitfield_default },
	 { "TMDS_CTL2_USE_FEEDBACK_PATH", 10, 10, &umr_bitfield_default },
	 { "TMDS_CTL2_FB_SYNC_CONT", 11, 11, &umr_bitfield_default },
	 { "TMDS_CTL2_PATTERN_OUT_EN", 12, 12, &umr_bitfield_default },
	 { "TMDS_CTL3_DATA_SEL", 16, 19, &umr_bitfield_default },
	 { "TMDS_CTL3_DATA_DELAY", 20, 22, &umr_bitfield_default },
	 { "TMDS_CTL3_DATA_INVERT", 23, 23, &umr_bitfield_default },
	 { "TMDS_CTL3_DATA_MODULATION", 24, 25, &umr_bitfield_default },
	 { "TMDS_CTL3_USE_FEEDBACK_PATH", 26, 26, &umr_bitfield_default },
	 { "TMDS_CTL3_FB_SYNC_CONT", 27, 27, &umr_bitfield_default },
	 { "TMDS_CTL3_PATTERN_OUT_EN", 28, 28, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG5_DIG_VERSION[] = {
	 { "DIG_TYPE", 0, 0, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG5_DIG_LANE_ENABLE[] = {
	 { "DIG_LANE0EN", 0, 0, &umr_bitfield_default },
	 { "DIG_LANE1EN", 1, 1, &umr_bitfield_default },
	 { "DIG_LANE2EN", 2, 2, &umr_bitfield_default },
	 { "DIG_LANE3EN", 3, 3, &umr_bitfield_default },
	 { "DIG_CLK_EN", 8, 8, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG5_AFMT_CNTL[] = {
	 { "AFMT_AUDIO_CLOCK_EN", 0, 0, &umr_bitfield_default },
	 { "AFMT_AUDIO_CLOCK_ON", 8, 8, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG5_AFMT_VBI_PACKET_CONTROL1[] = {
	 { "AFMT_GENERIC0_FRAME_UPDATE", 0, 0, &umr_bitfield_default },
	 { "AFMT_GENERIC0_FRAME_UPDATE_PENDING", 1, 1, &umr_bitfield_default },
	 { "AFMT_GENERIC0_IMMEDIATE_UPDATE", 2, 2, &umr_bitfield_default },
	 { "AFMT_GENERIC0_IMMEDIATE_UPDATE_PENDING", 3, 3, &umr_bitfield_default },
	 { "AFMT_GENERIC1_FRAME_UPDATE", 4, 4, &umr_bitfield_default },
	 { "AFMT_GENERIC1_FRAME_UPDATE_PENDING", 5, 5, &umr_bitfield_default },
	 { "AFMT_GENERIC1_IMMEDIATE_UPDATE", 6, 6, &umr_bitfield_default },
	 { "AFMT_GENERIC1_IMMEDIATE_UPDATE_PENDING", 7, 7, &umr_bitfield_default },
	 { "AFMT_GENERIC2_FRAME_UPDATE", 8, 8, &umr_bitfield_default },
	 { "AFMT_GENERIC2_FRAME_UPDATE_PENDING", 9, 9, &umr_bitfield_default },
	 { "AFMT_GENERIC2_IMMEDIATE_UPDATE", 10, 10, &umr_bitfield_default },
	 { "AFMT_GENERIC2_IMMEDIATE_UPDATE_PENDING", 11, 11, &umr_bitfield_default },
	 { "AFMT_GENERIC3_FRAME_UPDATE", 12, 12, &umr_bitfield_default },
	 { "AFMT_GENERIC3_FRAME_UPDATE_PENDING", 13, 13, &umr_bitfield_default },
	 { "AFMT_GENERIC3_IMMEDIATE_UPDATE", 14, 14, &umr_bitfield_default },
	 { "AFMT_GENERIC3_IMMEDIATE_UPDATE_PENDING", 15, 15, &umr_bitfield_default },
	 { "AFMT_GENERIC4_FRAME_UPDATE", 16, 16, &umr_bitfield_default },
	 { "AFMT_GENERIC4_FRAME_UPDATE_PENDING", 17, 17, &umr_bitfield_default },
	 { "AFMT_GENERIC4_IMMEDIATE_UPDATE", 18, 18, &umr_bitfield_default },
	 { "AFMT_GENERIC4_IMMEDIATE_UPDATE_PENDING", 19, 19, &umr_bitfield_default },
	 { "AFMT_GENERIC5_FRAME_UPDATE", 20, 20, &umr_bitfield_default },
	 { "AFMT_GENERIC5_FRAME_UPDATE_PENDING", 21, 21, &umr_bitfield_default },
	 { "AFMT_GENERIC5_IMMEDIATE_UPDATE", 22, 22, &umr_bitfield_default },
	 { "AFMT_GENERIC5_IMMEDIATE_UPDATE_PENDING", 23, 23, &umr_bitfield_default },
	 { "AFMT_GENERIC6_FRAME_UPDATE", 24, 24, &umr_bitfield_default },
	 { "AFMT_GENERIC6_FRAME_UPDATE_PENDING", 25, 25, &umr_bitfield_default },
	 { "AFMT_GENERIC6_IMMEDIATE_UPDATE", 26, 26, &umr_bitfield_default },
	 { "AFMT_GENERIC6_IMMEDIATE_UPDATE_PENDING", 27, 27, &umr_bitfield_default },
	 { "AFMT_GENERIC7_FRAME_UPDATE", 28, 28, &umr_bitfield_default },
	 { "AFMT_GENERIC7_FRAME_UPDATE_PENDING", 29, 29, &umr_bitfield_default },
	 { "AFMT_GENERIC7_IMMEDIATE_UPDATE", 30, 30, &umr_bitfield_default },
	 { "AFMT_GENERIC7_IMMEDIATE_UPDATE_PENDING", 31, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDP5_DP_LINK_CNTL[] = {
	 { "DP_LINK_TRAINING_COMPLETE", 4, 4, &umr_bitfield_default },
	 { "DP_LINK_STATUS", 8, 8, &umr_bitfield_default },
	 { "DP_EMBEDDED_PANEL_MODE", 17, 17, &umr_bitfield_default },
};
static struct umr_bitfield mmDP5_DP_PIXEL_FORMAT[] = {
	 { "DP_PIXEL_ENCODING", 0, 2, &umr_bitfield_default },
	 { "DP_COMPONENT_DEPTH", 24, 26, &umr_bitfield_default },
	 { "DP_PIXEL_COMBINE", 28, 29, &umr_bitfield_default },
};
static struct umr_bitfield mmDP5_DP_MSA_COLORIMETRY[] = {
	 { "DP_MSA_MISC0", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDP5_DP_CONFIG[] = {
	 { "DP_UDI_LANES", 0, 1, &umr_bitfield_default },
};
static struct umr_bitfield mmDP5_DP_VID_STREAM_CNTL[] = {
	 { "DP_VID_STREAM_ENABLE", 0, 0, &umr_bitfield_default },
	 { "DP_VID_STREAM_DIS_DEFER", 8, 9, &umr_bitfield_default },
	 { "DP_VID_STREAM_STATUS", 16, 16, &umr_bitfield_default },
	 { "DP_VID_STREAM_CHANGE_KEEPOUT", 20, 20, &umr_bitfield_default },
};
static struct umr_bitfield mmDP5_DP_STEER_FIFO[] = {
	 { "DP_STEER_FIFO_RESET", 0, 0, &umr_bitfield_default },
	 { "DP_STEER_OVERFLOW_FLAG", 4, 4, &umr_bitfield_default },
	 { "DP_STEER_OVERFLOW_INT", 5, 5, &umr_bitfield_default },
	 { "DP_STEER_OVERFLOW_ACK", 6, 6, &umr_bitfield_default },
	 { "DP_STEER_OVERFLOW_MASK", 7, 7, &umr_bitfield_default },
	 { "DP_TU_OVERFLOW_FLAG", 8, 8, &umr_bitfield_default },
	 { "DP_TU_OVERFLOW_ACK", 12, 12, &umr_bitfield_default },
};
static struct umr_bitfield mmDP5_DP_MSA_MISC[] = {
	 { "DP_MSA_MISC1", 0, 7, &umr_bitfield_default },
	 { "DP_MSA_MISC2", 8, 15, &umr_bitfield_default },
	 { "DP_MSA_MISC3", 16, 23, &umr_bitfield_default },
	 { "DP_MSA_MISC4", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDP5_DP_VID_TIMING[] = {
	 { "DP_VID_M_N_DOUBLE_BUFFER_MODE", 4, 4, &umr_bitfield_default },
	 { "DP_VID_M_N_GEN_EN", 8, 8, &umr_bitfield_default },
	 { "DP_VID_N_MUL", 10, 11, &umr_bitfield_default },
	 { "DP_VID_M_DIV", 12, 13, &umr_bitfield_default },
	 { "DP_VID_N_DIV", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDP5_DP_VID_N[] = {
	 { "DP_VID_N", 0, 23, &umr_bitfield_default },
};
static struct umr_bitfield mmDP5_DP_VID_M[] = {
	 { "DP_VID_M", 0, 23, &umr_bitfield_default },
};
static struct umr_bitfield mmDP5_DP_LINK_FRAMING_CNTL[] = {
	 { "DP_IDLE_BS_INTERVAL", 0, 17, &umr_bitfield_default },
	 { "DP_VBID_DISABLE", 24, 24, &umr_bitfield_default },
	 { "DP_VID_ENHANCED_FRAME_MODE", 28, 28, &umr_bitfield_default },
};
static struct umr_bitfield mmDP5_DP_HBR2_EYE_PATTERN[] = {
	 { "DP_HBR2_EYE_PATTERN_ENABLE", 0, 0, &umr_bitfield_default },
};
static struct umr_bitfield mmDP5_DP_VID_MSA_VBID[] = {
	 { "DP_VID_MSA_LOCATION", 0, 11, &umr_bitfield_default },
	 { "DP_VID_VBID_FIELD_POL", 24, 24, &umr_bitfield_default },
};
static struct umr_bitfield mmDP5_DP_VID_INTERRUPT_CNTL[] = {
	 { "DP_VID_STREAM_DISABLE_INT", 0, 0, &umr_bitfield_default },
	 { "DP_VID_STREAM_DISABLE_ACK", 1, 1, &umr_bitfield_default },
	 { "DP_VID_STREAM_DISABLE_MASK", 2, 2, &umr_bitfield_default },
};
static struct umr_bitfield mmDP5_DP_DPHY_CNTL[] = {
	 { "DPHY_ATEST_SEL_LANE0", 0, 0, &umr_bitfield_default },
	 { "DPHY_ATEST_SEL_LANE1", 1, 1, &umr_bitfield_default },
	 { "DPHY_ATEST_SEL_LANE2", 2, 2, &umr_bitfield_default },
	 { "DPHY_ATEST_SEL_LANE3", 3, 3, &umr_bitfield_default },
	 { "DPHY_BYPASS", 16, 16, &umr_bitfield_default },
	 { "DPHY_SKEW_BYPASS", 24, 24, &umr_bitfield_default },
};
static struct umr_bitfield mmDP5_DP_DPHY_TRAINING_PATTERN_SEL[] = {
	 { "DPHY_TRAINING_PATTERN_SEL", 0, 1, &umr_bitfield_default },
};
static struct umr_bitfield mmDP5_DP_DPHY_SYM0[] = {
	 { "DPHY_SYM1", 0, 9, &umr_bitfield_default },
	 { "DPHY_SYM2", 10, 19, &umr_bitfield_default },
	 { "DPHY_SYM3", 20, 29, &umr_bitfield_default },
};
static struct umr_bitfield mmDP5_DP_DPHY_SYM1[] = {
	 { "DPHY_SYM4", 0, 9, &umr_bitfield_default },
	 { "DPHY_SYM5", 10, 19, &umr_bitfield_default },
	 { "DPHY_SYM6", 20, 29, &umr_bitfield_default },
};
static struct umr_bitfield mmDP5_DP_DPHY_SYM2[] = {
	 { "DPHY_SYM7", 0, 9, &umr_bitfield_default },
	 { "DPHY_SYM8", 10, 19, &umr_bitfield_default },
};
static struct umr_bitfield mmDP5_DP_DPHY_8B10B_CNTL[] = {
	 { "DPHY_8B10B_RESET", 8, 8, &umr_bitfield_default },
	 { "DPHY_8B10B_EXT_DISP", 16, 16, &umr_bitfield_default },
	 { "DPHY_8B10B_CUR_DISP", 24, 24, &umr_bitfield_default },
};
static struct umr_bitfield mmDP5_DP_DPHY_PRBS_CNTL[] = {
	 { "DPHY_PRBS_EN", 0, 0, &umr_bitfield_default },
	 { "DPHY_PRBS_SEL", 4, 5, &umr_bitfield_default },
	 { "DPHY_PRBS_SEED", 8, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmDP5_DP_DPHY_SCRAM_CNTL[] = {
	 { "DPHY_SCRAMBLER_DIS", 0, 0, &umr_bitfield_default },
	 { "DPHY_SCRAMBLER_ADVANCE", 4, 4, &umr_bitfield_default },
	 { "DPHY_SCRAMBLER_BS_COUNT", 8, 17, &umr_bitfield_default },
	 { "DPHY_SCRAMBLER_KCODE", 24, 24, &umr_bitfield_default },
};
static struct umr_bitfield mmDP5_DP_DPHY_CRC_EN[] = {
	 { "DPHY_CRC_EN", 0, 0, &umr_bitfield_default },
	 { "DPHY_CRC_CONT_EN", 4, 4, &umr_bitfield_default },
	 { "DPHY_CRC_RESULT_VALID", 8, 8, &umr_bitfield_default },
};
static struct umr_bitfield mmDP5_DP_DPHY_CRC_CNTL[] = {
	 { "DPHY_CRC_FIELD", 0, 0, &umr_bitfield_default },
	 { "DPHY_CRC_SEL", 4, 5, &umr_bitfield_default },
	 { "DPHY_CRC_MASK", 16, 23, &umr_bitfield_default },
};
static struct umr_bitfield mmDP5_DP_DPHY_CRC_RESULT[] = {
	 { "DPHY_CRC_RESULT", 0, 7, &umr_bitfield_default },
	 { "DPHY_CRC_RESULT1", 8, 15, &umr_bitfield_default },
	 { "DPHY_CRC_RESULT2", 16, 23, &umr_bitfield_default },
	 { "DPHY_CRC_RESULT3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDP5_DP_DPHY_CRC_MST_CNTL[] = {
	 { "DPHY_CRC_MST_FIRST_SLOT", 0, 5, &umr_bitfield_default },
	 { "DPHY_CRC_MST_LAST_SLOT", 8, 13, &umr_bitfield_default },
};
static struct umr_bitfield mmDP5_DP_DPHY_CRC_MST_STATUS[] = {
	 { "DPHY_CRC_MST_PHASE_LOCK", 0, 0, &umr_bitfield_default },
	 { "DPHY_CRC_MST_PHASE_ERROR", 8, 8, &umr_bitfield_default },
	 { "DPHY_CRC_MST_PHASE_ERROR_ACK", 16, 16, &umr_bitfield_default },
};
static struct umr_bitfield mmDP5_DP_DPHY_FAST_TRAINING[] = {
	 { "DPHY_RX_FAST_TRAINING_CAPABLE", 0, 0, &umr_bitfield_default },
	 { "DPHY_SW_FAST_TRAINING_START", 1, 1, &umr_bitfield_default },
	 { "DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN", 2, 2, &umr_bitfield_default },
	 { "DPHY_FAST_TRAINING_TP1_TIME", 8, 19, &umr_bitfield_default },
	 { "DPHY_FAST_TRAINING_TP2_TIME", 20, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDP5_DP_DPHY_FAST_TRAINING_STATUS[] = {
	 { "DPHY_FAST_TRAINING_STATE", 0, 2, &umr_bitfield_default },
	 { "DPHY_FAST_TRAINING_COMPLETE_OCCURRED", 4, 4, &umr_bitfield_default },
	 { "DPHY_FAST_TRAINING_COMPLETE_MASK", 8, 8, &umr_bitfield_default },
	 { "DPHY_FAST_TRAINING_COMPLETE_ACK", 12, 12, &umr_bitfield_default },
};
static struct umr_bitfield mmDP5_DP_SEC_CNTL[] = {
	 { "DP_SEC_STREAM_ENABLE", 0, 0, &umr_bitfield_default },
	 { "DP_SEC_ASP_ENABLE", 4, 4, &umr_bitfield_default },
	 { "DP_SEC_ATP_ENABLE", 8, 8, &umr_bitfield_default },
	 { "DP_SEC_AIP_ENABLE", 12, 12, &umr_bitfield_default },
	 { "DP_SEC_ACM_ENABLE", 16, 16, &umr_bitfield_default },
	 { "DP_SEC_GSP0_ENABLE", 20, 20, &umr_bitfield_default },
	 { "DP_SEC_GSP1_ENABLE", 21, 21, &umr_bitfield_default },
	 { "DP_SEC_GSP2_ENABLE", 22, 22, &umr_bitfield_default },
	 { "DP_SEC_GSP3_ENABLE", 23, 23, &umr_bitfield_default },
	 { "DP_SEC_GSP4_ENABLE", 24, 24, &umr_bitfield_default },
	 { "DP_SEC_GSP5_ENABLE", 25, 25, &umr_bitfield_default },
	 { "DP_SEC_GSP6_ENABLE", 26, 26, &umr_bitfield_default },
	 { "DP_SEC_GSP7_ENABLE", 27, 27, &umr_bitfield_default },
	 { "DP_SEC_MPG_ENABLE", 28, 28, &umr_bitfield_default },
};
static struct umr_bitfield mmDP5_DP_SEC_CNTL1[] = {
	 { "DP_SEC_ISRC_ENABLE", 0, 0, &umr_bitfield_default },
	 { "DP_SEC_GSP0_PRIORITY", 4, 4, &umr_bitfield_default },
	 { "DP_SEC_GSP0_SEND", 5, 5, &umr_bitfield_default },
	 { "DP_SEC_GSP0_SEND_PENDING", 6, 6, &umr_bitfield_default },
	 { "DP_SEC_GSP0_SEND_DEADLINE_MISSED", 7, 7, &umr_bitfield_default },
	 { "DP_SEC_GSP0_SEND_ANY_LINE", 8, 8, &umr_bitfield_default },
	 { "DP_SEC_GSP0_LINE_NUM", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDP5_DP_SEC_FRAMING1[] = {
	 { "DP_SEC_FRAME_START_LOCATION", 0, 11, &umr_bitfield_default },
	 { "DP_SEC_VBLANK_TRANSMIT_WIDTH", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDP5_DP_SEC_FRAMING2[] = {
	 { "DP_SEC_START_POSITION", 0, 15, &umr_bitfield_default },
	 { "DP_SEC_HBLANK_TRANSMIT_WIDTH", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDP5_DP_SEC_FRAMING3[] = {
	 { "DP_SEC_IDLE_FRAME_SIZE", 0, 13, &umr_bitfield_default },
	 { "DP_SEC_IDLE_TRANSMIT_WIDTH", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDP5_DP_SEC_FRAMING4[] = {
	 { "DP_SEC_COLLISION_STATUS", 20, 20, &umr_bitfield_default },
	 { "DP_SEC_COLLISION_ACK", 24, 24, &umr_bitfield_default },
	 { "DP_SEC_AUDIO_MUTE", 28, 28, &umr_bitfield_default },
	 { "DP_SEC_AUDIO_MUTE_STATUS", 29, 29, &umr_bitfield_default },
};
static struct umr_bitfield mmDP5_DP_SEC_AUD_N[] = {
	 { "DP_SEC_AUD_N", 0, 23, &umr_bitfield_default },
};
static struct umr_bitfield mmDP5_DP_SEC_AUD_N_READBACK[] = {
	 { "DP_SEC_AUD_N_READBACK", 0, 23, &umr_bitfield_default },
};
static struct umr_bitfield mmDP5_DP_SEC_AUD_M[] = {
	 { "DP_SEC_AUD_M", 0, 23, &umr_bitfield_default },
};
static struct umr_bitfield mmDP5_DP_SEC_AUD_M_READBACK[] = {
	 { "DP_SEC_AUD_M_READBACK", 0, 23, &umr_bitfield_default },
};
static struct umr_bitfield mmDP5_DP_SEC_TIMESTAMP[] = {
	 { "DP_SEC_TIMESTAMP_MODE", 0, 0, &umr_bitfield_default },
};
static struct umr_bitfield mmDP5_DP_SEC_PACKET_CNTL[] = {
	 { "DP_SEC_ASP_CODING_TYPE", 1, 3, &umr_bitfield_default },
	 { "DP_SEC_ASP_PRIORITY", 4, 4, &umr_bitfield_default },
	 { "DP_SEC_VERSION", 8, 13, &umr_bitfield_default },
	 { "DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE", 16, 16, &umr_bitfield_default },
};
static struct umr_bitfield mmDP5_DP_MSE_RATE_CNTL[] = {
	 { "DP_MSE_RATE_Y", 0, 25, &umr_bitfield_default },
	 { "DP_MSE_RATE_X", 26, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDP5_DP_MSE_RATE_UPDATE[] = {
	 { "DP_MSE_RATE_UPDATE_PENDING", 0, 0, &umr_bitfield_default },
};
static struct umr_bitfield mmDP5_DP_MSE_SAT0[] = {
	 { "DP_MSE_SAT_SRC0", 0, 2, &umr_bitfield_default },
	 { "DP_MSE_SAT_SLOT_COUNT0", 8, 13, &umr_bitfield_default },
	 { "DP_MSE_SAT_SRC1", 16, 18, &umr_bitfield_default },
	 { "DP_MSE_SAT_SLOT_COUNT1", 24, 29, &umr_bitfield_default },
};
static struct umr_bitfield mmDP5_DP_MSE_SAT1[] = {
	 { "DP_MSE_SAT_SRC2", 0, 2, &umr_bitfield_default },
	 { "DP_MSE_SAT_SLOT_COUNT2", 8, 13, &umr_bitfield_default },
	 { "DP_MSE_SAT_SRC3", 16, 18, &umr_bitfield_default },
	 { "DP_MSE_SAT_SLOT_COUNT3", 24, 29, &umr_bitfield_default },
};
static struct umr_bitfield mmDP5_DP_MSE_SAT2[] = {
	 { "DP_MSE_SAT_SRC4", 0, 2, &umr_bitfield_default },
	 { "DP_MSE_SAT_SLOT_COUNT4", 8, 13, &umr_bitfield_default },
	 { "DP_MSE_SAT_SRC5", 16, 18, &umr_bitfield_default },
	 { "DP_MSE_SAT_SLOT_COUNT5", 24, 29, &umr_bitfield_default },
};
static struct umr_bitfield mmDP5_DP_MSE_SAT_UPDATE[] = {
	 { "DP_MSE_SAT_UPDATE", 0, 1, &umr_bitfield_default },
	 { "DP_MSE_16_MTP_KEEPOUT", 8, 8, &umr_bitfield_default },
};
static struct umr_bitfield mmDP5_DP_MSE_LINK_TIMING[] = {
	 { "DP_MSE_LINK_FRAME", 0, 9, &umr_bitfield_default },
	 { "DP_MSE_LINK_LINE", 16, 17, &umr_bitfield_default },
};
static struct umr_bitfield mmDP5_DP_MSE_MISC_CNTL[] = {
	 { "DP_MSE_BLANK_CODE", 0, 0, &umr_bitfield_default },
	 { "DP_MSE_TIMESTAMP_MODE", 4, 4, &umr_bitfield_default },
	 { "DP_MSE_ZERO_ENCODER", 8, 8, &umr_bitfield_default },
};
static struct umr_bitfield mmDP5_DP_DPHY_BS_SR_SWAP_CNTL[] = {
	 { "DPHY_LOAD_BS_COUNT", 0, 9, &umr_bitfield_default },
	 { "DPHY_BS_SR_SWAP_DONE", 15, 15, &umr_bitfield_default },
	 { "DPHY_LOAD_BS_COUNT_START", 16, 16, &umr_bitfield_default },
};
static struct umr_bitfield mmDP5_DP_DPHY_HBR2_PATTERN_CONTROL[] = {
	 { "DP_DPHY_HBR2_PATTERN_CONTROL", 0, 2, &umr_bitfield_default },
};
static struct umr_bitfield mmDP5_DP_MSE_SAT0_STATUS[] = {
	 { "DP_MSE_SAT_SRC0_STATUS", 0, 2, &umr_bitfield_default },
	 { "DP_MSE_SAT_SLOT_COUNT0_STATUS", 8, 13, &umr_bitfield_default },
	 { "DP_MSE_SAT_SRC1_STATUS", 16, 18, &umr_bitfield_default },
	 { "DP_MSE_SAT_SLOT_COUNT1_STATUS", 24, 29, &umr_bitfield_default },
};
static struct umr_bitfield mmDP5_DP_MSE_SAT1_STATUS[] = {
	 { "DP_MSE_SAT_SRC2_STATUS", 0, 2, &umr_bitfield_default },
	 { "DP_MSE_SAT_SLOT_COUNT2_STATUS", 8, 13, &umr_bitfield_default },
	 { "DP_MSE_SAT_SRC3_STATUS", 16, 18, &umr_bitfield_default },
	 { "DP_MSE_SAT_SLOT_COUNT3_STATUS", 24, 29, &umr_bitfield_default },
};
static struct umr_bitfield mmDP5_DP_MSE_SAT2_STATUS[] = {
	 { "DP_MSE_SAT_SRC4_STATUS", 0, 2, &umr_bitfield_default },
	 { "DP_MSE_SAT_SLOT_COUNT4_STATUS", 8, 13, &umr_bitfield_default },
	 { "DP_MSE_SAT_SRC5_STATUS", 16, 18, &umr_bitfield_default },
	 { "DP_MSE_SAT_SLOT_COUNT5_STATUS", 24, 29, &umr_bitfield_default },
};
static struct umr_bitfield mmDP5_DP_MSA_TIMING_PARAM1[] = {
	 { "DP_MSA_VTOTAL", 0, 15, &umr_bitfield_default },
	 { "DP_MSA_HTOTAL", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDP5_DP_MSA_TIMING_PARAM2[] = {
	 { "DP_MSA_VSTART", 0, 15, &umr_bitfield_default },
	 { "DP_MSA_HSTART", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDP5_DP_MSA_TIMING_PARAM3[] = {
	 { "DP_MSA_VSYNCWIDTH", 0, 14, &umr_bitfield_default },
	 { "DP_MSA_VSYNCPOLARITY", 15, 15, &umr_bitfield_default },
	 { "DP_MSA_HSYNCWIDTH", 16, 30, &umr_bitfield_default },
	 { "DP_MSA_HSYNCPOLARITY", 31, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDP5_DP_MSA_TIMING_PARAM4[] = {
	 { "DP_MSA_VHEIGHT", 0, 15, &umr_bitfield_default },
	 { "DP_MSA_HWIDTH", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDP5_DP_MSO_CNTL[] = {
	 { "DP_MSO_NUM_OF_SSTLINK", 0, 1, &umr_bitfield_default },
	 { "DP_MSO_SEC_STREAM_ENABLE", 4, 7, &umr_bitfield_default },
	 { "DP_MSO_SEC_ASP_ENABLE", 8, 11, &umr_bitfield_default },
	 { "DP_MSO_SEC_ATP_ENABLE", 12, 15, &umr_bitfield_default },
	 { "DP_MSO_SEC_AIP_ENABLE", 16, 19, &umr_bitfield_default },
	 { "DP_MSO_SEC_ACM_ENABLE", 20, 23, &umr_bitfield_default },
	 { "DP_MSO_SEC_GSP0_ENABLE", 24, 27, &umr_bitfield_default },
	 { "DP_MSO_SEC_GSP1_ENABLE", 28, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDP5_DP_MSO_CNTL1[] = {
	 { "DP_MSO_SEC_GSP2_ENABLE", 0, 3, &umr_bitfield_default },
	 { "DP_MSO_SEC_GSP3_ENABLE", 4, 7, &umr_bitfield_default },
	 { "DP_MSO_SEC_GSP4_ENABLE", 8, 11, &umr_bitfield_default },
	 { "DP_MSO_SEC_GSP5_ENABLE", 12, 15, &umr_bitfield_default },
	 { "DP_MSO_SEC_GSP6_ENABLE", 16, 19, &umr_bitfield_default },
	 { "DP_MSO_SEC_GSP7_ENABLE", 20, 23, &umr_bitfield_default },
	 { "DP_MSO_SEC_MPG_ENABLE", 24, 27, &umr_bitfield_default },
	 { "DP_MSO_SEC_ISRC_ENABLE", 28, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDP5_DP_DSC_CNTL[] = {
	 { "DP_DSC_EN", 0, 0, &umr_bitfield_default },
};
static struct umr_bitfield mmDP5_DP_SEC_CNTL2[] = {
	 { "DP_SEC_GSP1_SEND", 0, 0, &umr_bitfield_default },
	 { "DP_SEC_GSP1_SEND_PENDING", 1, 1, &umr_bitfield_default },
	 { "DP_SEC_GSP1_SEND_DEADLINE_MISSED", 2, 2, &umr_bitfield_default },
	 { "DP_SEC_GSP1_SEND_ANY_LINE", 3, 3, &umr_bitfield_default },
	 { "DP_SEC_GSP2_SEND", 4, 4, &umr_bitfield_default },
	 { "DP_SEC_GSP2_SEND_PENDING", 5, 5, &umr_bitfield_default },
	 { "DP_SEC_GSP2_SEND_DEADLINE_MISSED", 6, 6, &umr_bitfield_default },
	 { "DP_SEC_GSP2_SEND_ANY_LINE", 7, 7, &umr_bitfield_default },
	 { "DP_SEC_GSP3_SEND", 8, 8, &umr_bitfield_default },
	 { "DP_SEC_GSP3_SEND_PENDING", 9, 9, &umr_bitfield_default },
	 { "DP_SEC_GSP3_SEND_DEADLINE_MISSED", 10, 10, &umr_bitfield_default },
	 { "DP_SEC_GSP3_SEND_ANY_LINE", 11, 11, &umr_bitfield_default },
	 { "DP_SEC_GSP4_SEND", 12, 12, &umr_bitfield_default },
	 { "DP_SEC_GSP4_SEND_PENDING", 13, 13, &umr_bitfield_default },
	 { "DP_SEC_GSP4_SEND_DEADLINE_MISSED", 14, 14, &umr_bitfield_default },
	 { "DP_SEC_GSP4_SEND_ANY_LINE", 15, 15, &umr_bitfield_default },
	 { "DP_SEC_GSP5_SEND", 16, 16, &umr_bitfield_default },
	 { "DP_SEC_GSP5_SEND_PENDING", 17, 17, &umr_bitfield_default },
	 { "DP_SEC_GSP5_SEND_DEADLINE_MISSED", 18, 18, &umr_bitfield_default },
	 { "DP_SEC_GSP5_SEND_ANY_LINE", 19, 19, &umr_bitfield_default },
	 { "DP_SEC_GSP6_SEND", 20, 20, &umr_bitfield_default },
	 { "DP_SEC_GSP6_SEND_PENDING", 21, 21, &umr_bitfield_default },
	 { "DP_SEC_GSP6_SEND_DEADLINE_MISSED", 22, 22, &umr_bitfield_default },
	 { "DP_SEC_GSP6_SEND_ANY_LINE", 23, 23, &umr_bitfield_default },
	 { "DP_SEC_GSP7_SEND", 24, 24, &umr_bitfield_default },
	 { "DP_SEC_GSP7_SEND_PENDING", 25, 25, &umr_bitfield_default },
	 { "DP_SEC_GSP7_SEND_DEADLINE_MISSED", 26, 26, &umr_bitfield_default },
	 { "DP_SEC_GSP7_SEND_ANY_LINE", 27, 27, &umr_bitfield_default },
	 { "DP_SEC_GSP7_PPS", 28, 28, &umr_bitfield_default },
};
static struct umr_bitfield mmDP5_DP_SEC_CNTL3[] = {
	 { "DP_SEC_GSP1_LINE_NUM", 0, 15, &umr_bitfield_default },
	 { "DP_SEC_GSP2_LINE_NUM", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDP5_DP_SEC_CNTL4[] = {
	 { "DP_SEC_GSP3_LINE_NUM", 0, 15, &umr_bitfield_default },
	 { "DP_SEC_GSP4_LINE_NUM", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDP5_DP_SEC_CNTL5[] = {
	 { "DP_SEC_GSP5_LINE_NUM", 0, 15, &umr_bitfield_default },
	 { "DP_SEC_GSP6_LINE_NUM", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDP5_DP_SEC_CNTL6[] = {
	 { "DP_SEC_GSP7_LINE_NUM", 0, 15, &umr_bitfield_default },
};
static struct umr_bitfield mmDP5_DP_SEC_CNTL7[] = {
	 { "DP_SEC_GSP0_SEND_ACTIVE", 0, 0, &umr_bitfield_default },
	 { "DP_SEC_GSP1_SEND_ACTIVE", 4, 4, &umr_bitfield_default },
	 { "DP_SEC_GSP2_SEND_ACTIVE", 8, 8, &umr_bitfield_default },
	 { "DP_SEC_GSP3_SEND_ACTIVE", 12, 12, &umr_bitfield_default },
	 { "DP_SEC_GSP4_SEND_ACTIVE", 16, 16, &umr_bitfield_default },
	 { "DP_SEC_GSP5_SEND_ACTIVE", 20, 20, &umr_bitfield_default },
	 { "DP_SEC_GSP6_SEND_ACTIVE", 24, 24, &umr_bitfield_default },
	 { "DP_SEC_GSP7_SEND_ACTIVE", 28, 28, &umr_bitfield_default },
};
static struct umr_bitfield mmDP5_DP_DB_CNTL[] = {
	 { "DP_DB_PENDING", 0, 0, &umr_bitfield_default },
	 { "DP_DB_TAKEN", 4, 4, &umr_bitfield_default },
	 { "DP_DB_TAKEN_CLR", 5, 5, &umr_bitfield_default },
	 { "DP_DB_LOCK", 8, 8, &umr_bitfield_default },
	 { "DP_DB_DISABLE", 12, 12, &umr_bitfield_default },
};
static struct umr_bitfield mmDP5_DP_MSA_VBID_MISC[] = {
	 { "DP_MSA_MISC1_STEREOSYNC_OVERRIDE", 0, 1, &umr_bitfield_default },
	 { "DP_MSA_MISC1_STEREOSYNC_OVERRIDE_EN", 4, 4, &umr_bitfield_default },
	 { "DP_VBID1_OVERRIDE", 8, 8, &umr_bitfield_default },
	 { "DP_VBID2_OVERRIDE", 9, 9, &umr_bitfield_default },
	 { "DP_VBID1_OVERRIDE_EN", 12, 12, &umr_bitfield_default },
	 { "DP_VBID2_OVERRIDE_EN", 13, 13, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG6_DIG_FE_CNTL[] = {
	 { "DIG_SOURCE_SELECT", 0, 2, &umr_bitfield_default },
	 { "DIG_STEREOSYNC_SELECT", 4, 6, &umr_bitfield_default },
	 { "DIG_STEREOSYNC_GATE_EN", 8, 8, &umr_bitfield_default },
	 { "DIG_START", 10, 10, &umr_bitfield_default },
	 { "DIG_DIGITAL_BYPASS_SELECT", 12, 14, &umr_bitfield_default },
	 { "DIG_SYMCLK_FE_ON", 24, 24, &umr_bitfield_default },
	 { "TMDS_PIXEL_ENCODING", 28, 28, &umr_bitfield_default },
	 { "TMDS_COLOR_FORMAT", 30, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG6_DIG_OUTPUT_CRC_CNTL[] = {
	 { "DIG_OUTPUT_CRC_EN", 0, 0, &umr_bitfield_default },
	 { "DIG_OUTPUT_CRC_LINK_SEL", 4, 4, &umr_bitfield_default },
	 { "DIG_OUTPUT_CRC_DATA_SEL", 8, 9, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG6_DIG_OUTPUT_CRC_RESULT[] = {
	 { "DIG_OUTPUT_CRC_RESULT", 0, 29, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG6_DIG_CLOCK_PATTERN[] = {
	 { "DIG_CLOCK_PATTERN", 0, 9, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG6_DIG_TEST_PATTERN[] = {
	 { "DIG_TEST_PATTERN_OUT_EN", 0, 0, &umr_bitfield_default },
	 { "DIG_HALF_CLOCK_PATTERN_SEL", 1, 1, &umr_bitfield_default },
	 { "DIG_RANDOM_PATTERN_OUT_EN", 4, 4, &umr_bitfield_default },
	 { "DIG_RANDOM_PATTERN_RESET", 5, 5, &umr_bitfield_default },
	 { "DIG_TEST_PATTERN_EXTERNAL_RESET_EN", 6, 6, &umr_bitfield_default },
	 { "DIG_STATIC_TEST_PATTERN", 16, 25, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG6_DIG_RANDOM_PATTERN_SEED[] = {
	 { "DIG_RANDOM_PATTERN_SEED", 0, 23, &umr_bitfield_default },
	 { "DIG_RAN_PAT_DURING_DE_ONLY", 24, 24, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG6_DIG_FIFO_STATUS[] = {
	 { "DIG_FIFO_LEVEL_ERROR", 0, 0, &umr_bitfield_default },
	 { "DIG_FIFO_USE_OVERWRITE_LEVEL", 1, 1, &umr_bitfield_default },
	 { "DIG_FIFO_OVERWRITE_LEVEL", 2, 7, &umr_bitfield_default },
	 { "DIG_FIFO_ERROR_ACK", 8, 8, &umr_bitfield_default },
	 { "DIG_FIFO_CAL_AVERAGE_LEVEL", 10, 15, &umr_bitfield_default },
	 { "DIG_FIFO_MAXIMUM_LEVEL", 16, 20, &umr_bitfield_default },
	 { "DIG_FIFO_MINIMUM_LEVEL", 22, 25, &umr_bitfield_default },
	 { "DIG_FIFO_READ_CLOCK_SRC", 26, 26, &umr_bitfield_default },
	 { "DIG_FIFO_CALIBRATED", 29, 29, &umr_bitfield_default },
	 { "DIG_FIFO_FORCE_RECAL_AVERAGE", 30, 30, &umr_bitfield_default },
	 { "DIG_FIFO_FORCE_RECOMP_MINMAX", 31, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG6_HDMI_CONTROL[] = {
	 { "HDMI_KEEPOUT_MODE", 0, 0, &umr_bitfield_default },
	 { "HDMI_DATA_SCRAMBLE_EN", 1, 1, &umr_bitfield_default },
	 { "HDMI_CLOCK_CHANNEL_RATE", 2, 2, &umr_bitfield_default },
	 { "HDMI_NO_EXTRA_NULL_PACKET_FILLED", 3, 3, &umr_bitfield_default },
	 { "HDMI_PACKET_GEN_VERSION", 4, 4, &umr_bitfield_default },
	 { "HDMI_ERROR_ACK", 8, 8, &umr_bitfield_default },
	 { "HDMI_ERROR_MASK", 9, 9, &umr_bitfield_default },
	 { "HDMI_DEEP_COLOR_ENABLE", 24, 24, &umr_bitfield_default },
	 { "HDMI_DEEP_COLOR_DEPTH", 28, 29, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG6_HDMI_STATUS[] = {
	 { "HDMI_ACTIVE_AVMUTE", 0, 0, &umr_bitfield_default },
	 { "HDMI_AUDIO_PACKET_ERROR", 16, 16, &umr_bitfield_default },
	 { "HDMI_VBI_PACKET_ERROR", 20, 20, &umr_bitfield_default },
	 { "HDMI_ERROR_INT", 27, 27, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG6_HDMI_AUDIO_PACKET_CONTROL[] = {
	 { "HDMI_AUDIO_DELAY_EN", 4, 5, &umr_bitfield_default },
	 { "HDMI_AUDIO_PACKETS_PER_LINE", 16, 20, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG6_HDMI_ACR_PACKET_CONTROL[] = {
	 { "HDMI_ACR_SEND", 0, 0, &umr_bitfield_default },
	 { "HDMI_ACR_CONT", 1, 1, &umr_bitfield_default },
	 { "HDMI_ACR_SELECT", 4, 5, &umr_bitfield_default },
	 { "HDMI_ACR_SOURCE", 8, 8, &umr_bitfield_default },
	 { "HDMI_ACR_AUTO_SEND", 12, 12, &umr_bitfield_default },
	 { "HDMI_ACR_N_MULTIPLE", 16, 18, &umr_bitfield_default },
	 { "HDMI_ACR_AUDIO_PRIORITY", 31, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG6_HDMI_VBI_PACKET_CONTROL[] = {
	 { "HDMI_NULL_SEND", 0, 0, &umr_bitfield_default },
	 { "HDMI_GC_SEND", 4, 4, &umr_bitfield_default },
	 { "HDMI_GC_CONT", 5, 5, &umr_bitfield_default },
	 { "HDMI_ISRC_SEND", 8, 8, &umr_bitfield_default },
	 { "HDMI_ISRC_CONT", 9, 9, &umr_bitfield_default },
	 { "HDMI_ISRC_LINE", 16, 21, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG6_HDMI_INFOFRAME_CONTROL0[] = {
	 { "HDMI_AUDIO_INFO_SEND", 4, 4, &umr_bitfield_default },
	 { "HDMI_AUDIO_INFO_CONT", 5, 5, &umr_bitfield_default },
	 { "HDMI_MPEG_INFO_SEND", 8, 8, &umr_bitfield_default },
	 { "HDMI_MPEG_INFO_CONT", 9, 9, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG6_HDMI_INFOFRAME_CONTROL1[] = {
	 { "HDMI_AUDIO_INFO_LINE", 8, 13, &umr_bitfield_default },
	 { "HDMI_MPEG_INFO_LINE", 16, 21, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG6_HDMI_GENERIC_PACKET_CONTROL0[] = {
	 { "HDMI_GENERIC0_SEND", 0, 0, &umr_bitfield_default },
	 { "HDMI_GENERIC0_CONT", 1, 1, &umr_bitfield_default },
	 { "HDMI_GENERIC1_SEND", 4, 4, &umr_bitfield_default },
	 { "HDMI_GENERIC1_CONT", 5, 5, &umr_bitfield_default },
	 { "HDMI_GENERIC0_LINE", 16, 21, &umr_bitfield_default },
	 { "HDMI_GENERIC1_LINE", 24, 29, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG6_HDMI_GC[] = {
	 { "HDMI_GC_AVMUTE", 0, 0, &umr_bitfield_default },
	 { "HDMI_GC_AVMUTE_CONT", 2, 2, &umr_bitfield_default },
	 { "HDMI_DEFAULT_PHASE", 4, 4, &umr_bitfield_default },
	 { "HDMI_PACKING_PHASE", 8, 11, &umr_bitfield_default },
	 { "HDMI_PACKING_PHASE_OVERRIDE", 12, 12, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG6_AFMT_AUDIO_PACKET_CONTROL2[] = {
	 { "AFMT_AUDIO_LAYOUT_OVRD", 0, 0, &umr_bitfield_default },
	 { "AFMT_AUDIO_LAYOUT_SELECT", 1, 1, &umr_bitfield_default },
	 { "AFMT_AUDIO_CHANNEL_ENABLE", 8, 15, &umr_bitfield_default },
	 { "AFMT_DP_AUDIO_STREAM_ID", 16, 23, &umr_bitfield_default },
	 { "AFMT_HBR_ENABLE_OVRD", 24, 24, &umr_bitfield_default },
	 { "AFMT_60958_OSF_OVRD", 28, 28, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG6_AFMT_ISRC1_0[] = {
	 { "AFMT_ISRC_STATUS", 0, 2, &umr_bitfield_default },
	 { "AFMT_ISRC_CONTINUE", 6, 6, &umr_bitfield_default },
	 { "AFMT_ISRC_VALID", 7, 7, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG6_AFMT_ISRC1_1[] = {
	 { "AFMT_UPC_EAN_ISRC0", 0, 7, &umr_bitfield_default },
	 { "AFMT_UPC_EAN_ISRC1", 8, 15, &umr_bitfield_default },
	 { "AFMT_UPC_EAN_ISRC2", 16, 23, &umr_bitfield_default },
	 { "AFMT_UPC_EAN_ISRC3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG6_AFMT_ISRC1_2[] = {
	 { "AFMT_UPC_EAN_ISRC4", 0, 7, &umr_bitfield_default },
	 { "AFMT_UPC_EAN_ISRC5", 8, 15, &umr_bitfield_default },
	 { "AFMT_UPC_EAN_ISRC6", 16, 23, &umr_bitfield_default },
	 { "AFMT_UPC_EAN_ISRC7", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG6_AFMT_ISRC1_3[] = {
	 { "AFMT_UPC_EAN_ISRC8", 0, 7, &umr_bitfield_default },
	 { "AFMT_UPC_EAN_ISRC9", 8, 15, &umr_bitfield_default },
	 { "AFMT_UPC_EAN_ISRC10", 16, 23, &umr_bitfield_default },
	 { "AFMT_UPC_EAN_ISRC11", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG6_AFMT_ISRC1_4[] = {
	 { "AFMT_UPC_EAN_ISRC12", 0, 7, &umr_bitfield_default },
	 { "AFMT_UPC_EAN_ISRC13", 8, 15, &umr_bitfield_default },
	 { "AFMT_UPC_EAN_ISRC14", 16, 23, &umr_bitfield_default },
	 { "AFMT_UPC_EAN_ISRC15", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG6_AFMT_ISRC2_0[] = {
	 { "AFMT_UPC_EAN_ISRC16", 0, 7, &umr_bitfield_default },
	 { "AFMT_UPC_EAN_ISRC17", 8, 15, &umr_bitfield_default },
	 { "AFMT_UPC_EAN_ISRC18", 16, 23, &umr_bitfield_default },
	 { "AFMT_UPC_EAN_ISRC19", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG6_AFMT_ISRC2_1[] = {
	 { "AFMT_UPC_EAN_ISRC20", 0, 7, &umr_bitfield_default },
	 { "AFMT_UPC_EAN_ISRC21", 8, 15, &umr_bitfield_default },
	 { "AFMT_UPC_EAN_ISRC22", 16, 23, &umr_bitfield_default },
	 { "AFMT_UPC_EAN_ISRC23", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG6_AFMT_ISRC2_2[] = {
	 { "AFMT_UPC_EAN_ISRC24", 0, 7, &umr_bitfield_default },
	 { "AFMT_UPC_EAN_ISRC25", 8, 15, &umr_bitfield_default },
	 { "AFMT_UPC_EAN_ISRC26", 16, 23, &umr_bitfield_default },
	 { "AFMT_UPC_EAN_ISRC27", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG6_AFMT_ISRC2_3[] = {
	 { "AFMT_UPC_EAN_ISRC28", 0, 7, &umr_bitfield_default },
	 { "AFMT_UPC_EAN_ISRC29", 8, 15, &umr_bitfield_default },
	 { "AFMT_UPC_EAN_ISRC30", 16, 23, &umr_bitfield_default },
	 { "AFMT_UPC_EAN_ISRC31", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG6_HDMI_GENERIC_PACKET_CONTROL2[] = {
	 { "HDMI_GENERIC4_SEND", 0, 0, &umr_bitfield_default },
	 { "HDMI_GENERIC4_CONT", 1, 1, &umr_bitfield_default },
	 { "HDMI_GENERIC5_SEND", 4, 4, &umr_bitfield_default },
	 { "HDMI_GENERIC5_CONT", 5, 5, &umr_bitfield_default },
	 { "HDMI_GENERIC4_LINE", 16, 21, &umr_bitfield_default },
	 { "HDMI_GENERIC5_LINE", 24, 29, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG6_HDMI_GENERIC_PACKET_CONTROL3[] = {
	 { "HDMI_GENERIC6_SEND", 0, 0, &umr_bitfield_default },
	 { "HDMI_GENERIC6_CONT", 1, 1, &umr_bitfield_default },
	 { "HDMI_GENERIC7_SEND", 4, 4, &umr_bitfield_default },
	 { "HDMI_GENERIC7_CONT", 5, 5, &umr_bitfield_default },
	 { "HDMI_GENERIC6_LINE", 16, 21, &umr_bitfield_default },
	 { "HDMI_GENERIC7_LINE", 24, 29, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG6_HDMI_DB_CONTROL[] = {
	 { "HDMI_DB_PENDING", 0, 0, &umr_bitfield_default },
	 { "HDMI_DB_TAKEN", 4, 4, &umr_bitfield_default },
	 { "HDMI_DB_TAKEN_CLR", 5, 5, &umr_bitfield_default },
	 { "HDMI_DB_LOCK", 8, 8, &umr_bitfield_default },
	 { "HDMI_DB_DISABLE", 12, 12, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG6_AFMT_MPEG_INFO0[] = {
	 { "AFMT_MPEG_INFO_CHECKSUM", 0, 7, &umr_bitfield_default },
	 { "AFMT_MPEG_INFO_MB0", 8, 15, &umr_bitfield_default },
	 { "AFMT_MPEG_INFO_MB1", 16, 23, &umr_bitfield_default },
	 { "AFMT_MPEG_INFO_MB2", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG6_AFMT_MPEG_INFO1[] = {
	 { "AFMT_MPEG_INFO_MB3", 0, 7, &umr_bitfield_default },
	 { "AFMT_MPEG_INFO_MF", 8, 9, &umr_bitfield_default },
	 { "AFMT_MPEG_INFO_FR", 12, 12, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG6_AFMT_GENERIC_HDR[] = {
	 { "AFMT_GENERIC_HB0", 0, 7, &umr_bitfield_default },
	 { "AFMT_GENERIC_HB1", 8, 15, &umr_bitfield_default },
	 { "AFMT_GENERIC_HB2", 16, 23, &umr_bitfield_default },
	 { "AFMT_GENERIC_HB3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG6_AFMT_GENERIC_0[] = {
	 { "AFMT_GENERIC_BYTE0", 0, 7, &umr_bitfield_default },
	 { "AFMT_GENERIC_BYTE1", 8, 15, &umr_bitfield_default },
	 { "AFMT_GENERIC_BYTE2", 16, 23, &umr_bitfield_default },
	 { "AFMT_GENERIC_BYTE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG6_AFMT_GENERIC_1[] = {
	 { "AFMT_GENERIC_BYTE4", 0, 7, &umr_bitfield_default },
	 { "AFMT_GENERIC_BYTE5", 8, 15, &umr_bitfield_default },
	 { "AFMT_GENERIC_BYTE6", 16, 23, &umr_bitfield_default },
	 { "AFMT_GENERIC_BYTE7", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG6_AFMT_GENERIC_2[] = {
	 { "AFMT_GENERIC_BYTE8", 0, 7, &umr_bitfield_default },
	 { "AFMT_GENERIC_BYTE9", 8, 15, &umr_bitfield_default },
	 { "AFMT_GENERIC_BYTE10", 16, 23, &umr_bitfield_default },
	 { "AFMT_GENERIC_BYTE11", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG6_AFMT_GENERIC_3[] = {
	 { "AFMT_GENERIC_BYTE12", 0, 7, &umr_bitfield_default },
	 { "AFMT_GENERIC_BYTE13", 8, 15, &umr_bitfield_default },
	 { "AFMT_GENERIC_BYTE14", 16, 23, &umr_bitfield_default },
	 { "AFMT_GENERIC_BYTE15", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG6_AFMT_GENERIC_4[] = {
	 { "AFMT_GENERIC_BYTE16", 0, 7, &umr_bitfield_default },
	 { "AFMT_GENERIC_BYTE17", 8, 15, &umr_bitfield_default },
	 { "AFMT_GENERIC_BYTE18", 16, 23, &umr_bitfield_default },
	 { "AFMT_GENERIC_BYTE19", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG6_AFMT_GENERIC_5[] = {
	 { "AFMT_GENERIC_BYTE20", 0, 7, &umr_bitfield_default },
	 { "AFMT_GENERIC_BYTE21", 8, 15, &umr_bitfield_default },
	 { "AFMT_GENERIC_BYTE22", 16, 23, &umr_bitfield_default },
	 { "AFMT_GENERIC_BYTE23", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG6_AFMT_GENERIC_6[] = {
	 { "AFMT_GENERIC_BYTE24", 0, 7, &umr_bitfield_default },
	 { "AFMT_GENERIC_BYTE25", 8, 15, &umr_bitfield_default },
	 { "AFMT_GENERIC_BYTE26", 16, 23, &umr_bitfield_default },
	 { "AFMT_GENERIC_BYTE27", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG6_AFMT_GENERIC_7[] = {
	 { "AFMT_GENERIC_BYTE28", 0, 7, &umr_bitfield_default },
	 { "AFMT_GENERIC_BYTE29", 8, 15, &umr_bitfield_default },
	 { "AFMT_GENERIC_BYTE30", 16, 23, &umr_bitfield_default },
	 { "AFMT_GENERIC_BYTE31", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG6_HDMI_GENERIC_PACKET_CONTROL1[] = {
	 { "HDMI_GENERIC2_SEND", 0, 0, &umr_bitfield_default },
	 { "HDMI_GENERIC2_CONT", 1, 1, &umr_bitfield_default },
	 { "HDMI_GENERIC3_SEND", 4, 4, &umr_bitfield_default },
	 { "HDMI_GENERIC3_CONT", 5, 5, &umr_bitfield_default },
	 { "HDMI_GENERIC2_LINE", 16, 21, &umr_bitfield_default },
	 { "HDMI_GENERIC3_LINE", 24, 29, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG6_HDMI_ACR_32_0[] = {
	 { "HDMI_ACR_CTS_32", 12, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG6_HDMI_ACR_32_1[] = {
	 { "HDMI_ACR_N_32", 0, 19, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG6_HDMI_ACR_44_0[] = {
	 { "HDMI_ACR_CTS_44", 12, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG6_HDMI_ACR_44_1[] = {
	 { "HDMI_ACR_N_44", 0, 19, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG6_HDMI_ACR_48_0[] = {
	 { "HDMI_ACR_CTS_48", 12, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG6_HDMI_ACR_48_1[] = {
	 { "HDMI_ACR_N_48", 0, 19, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG6_HDMI_ACR_STATUS_0[] = {
	 { "HDMI_ACR_CTS", 12, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG6_HDMI_ACR_STATUS_1[] = {
	 { "HDMI_ACR_N", 0, 19, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG6_AFMT_AUDIO_INFO0[] = {
	 { "AFMT_AUDIO_INFO_CHECKSUM", 0, 7, &umr_bitfield_default },
	 { "AFMT_AUDIO_INFO_CC", 8, 10, &umr_bitfield_default },
	 { "AFMT_AUDIO_INFO_CT", 11, 14, &umr_bitfield_default },
	 { "AFMT_AUDIO_INFO_CHECKSUM_OFFSET", 16, 23, &umr_bitfield_default },
	 { "AFMT_AUDIO_INFO_CXT", 24, 28, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG6_AFMT_AUDIO_INFO1[] = {
	 { "AFMT_AUDIO_INFO_CA", 0, 7, &umr_bitfield_default },
	 { "AFMT_AUDIO_INFO_LSV", 11, 14, &umr_bitfield_default },
	 { "AFMT_AUDIO_INFO_DM_INH", 15, 15, &umr_bitfield_default },
	 { "AFMT_AUDIO_INFO_LFEPBL", 16, 17, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG6_AFMT_60958_0[] = {
	 { "AFMT_60958_CS_A", 0, 0, &umr_bitfield_default },
	 { "AFMT_60958_CS_B", 1, 1, &umr_bitfield_default },
	 { "AFMT_60958_CS_C", 2, 2, &umr_bitfield_default },
	 { "AFMT_60958_CS_D", 3, 5, &umr_bitfield_default },
	 { "AFMT_60958_CS_MODE", 6, 7, &umr_bitfield_default },
	 { "AFMT_60958_CS_CATEGORY_CODE", 8, 15, &umr_bitfield_default },
	 { "AFMT_60958_CS_SOURCE_NUMBER", 16, 19, &umr_bitfield_default },
	 { "AFMT_60958_CS_CHANNEL_NUMBER_L", 20, 23, &umr_bitfield_default },
	 { "AFMT_60958_CS_SAMPLING_FREQUENCY", 24, 27, &umr_bitfield_default },
	 { "AFMT_60958_CS_CLOCK_ACCURACY", 28, 29, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG6_AFMT_60958_1[] = {
	 { "AFMT_60958_CS_WORD_LENGTH", 0, 3, &umr_bitfield_default },
	 { "AFMT_60958_CS_ORIGINAL_SAMPLING_FREQUENCY", 4, 7, &umr_bitfield_default },
	 { "AFMT_60958_VALID_L", 16, 16, &umr_bitfield_default },
	 { "AFMT_60958_VALID_R", 18, 18, &umr_bitfield_default },
	 { "AFMT_60958_CS_CHANNEL_NUMBER_R", 20, 23, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG6_AFMT_AUDIO_CRC_CONTROL[] = {
	 { "AFMT_AUDIO_CRC_EN", 0, 0, &umr_bitfield_default },
	 { "AFMT_AUDIO_CRC_CONT", 4, 4, &umr_bitfield_default },
	 { "AFMT_AUDIO_CRC_SOURCE", 8, 8, &umr_bitfield_default },
	 { "AFMT_AUDIO_CRC_CH_SEL", 12, 15, &umr_bitfield_default },
	 { "AFMT_AUDIO_CRC_COUNT", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG6_AFMT_RAMP_CONTROL0[] = {
	 { "AFMT_RAMP_MAX_COUNT", 0, 23, &umr_bitfield_default },
	 { "AFMT_RAMP_DATA_SIGN", 31, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG6_AFMT_RAMP_CONTROL1[] = {
	 { "AFMT_RAMP_MIN_COUNT", 0, 23, &umr_bitfield_default },
	 { "AFMT_AUDIO_TEST_CH_DISABLE", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG6_AFMT_RAMP_CONTROL2[] = {
	 { "AFMT_RAMP_INC_COUNT", 0, 23, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG6_AFMT_RAMP_CONTROL3[] = {
	 { "AFMT_RAMP_DEC_COUNT", 0, 23, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG6_AFMT_60958_2[] = {
	 { "AFMT_60958_CS_CHANNEL_NUMBER_2", 0, 3, &umr_bitfield_default },
	 { "AFMT_60958_CS_CHANNEL_NUMBER_3", 4, 7, &umr_bitfield_default },
	 { "AFMT_60958_CS_CHANNEL_NUMBER_4", 8, 11, &umr_bitfield_default },
	 { "AFMT_60958_CS_CHANNEL_NUMBER_5", 12, 15, &umr_bitfield_default },
	 { "AFMT_60958_CS_CHANNEL_NUMBER_6", 16, 19, &umr_bitfield_default },
	 { "AFMT_60958_CS_CHANNEL_NUMBER_7", 20, 23, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG6_AFMT_AUDIO_CRC_RESULT[] = {
	 { "AFMT_AUDIO_CRC_DONE", 0, 0, &umr_bitfield_default },
	 { "AFMT_AUDIO_CRC", 8, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG6_AFMT_STATUS[] = {
	 { "AFMT_AUDIO_ENABLE", 4, 4, &umr_bitfield_default },
	 { "AFMT_AZ_HBR_ENABLE", 8, 8, &umr_bitfield_default },
	 { "AFMT_AUDIO_FIFO_OVERFLOW", 24, 24, &umr_bitfield_default },
	 { "AFMT_AZ_AUDIO_ENABLE_CHG", 30, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG6_AFMT_AUDIO_PACKET_CONTROL[] = {
	 { "AFMT_AUDIO_SAMPLE_SEND", 0, 0, &umr_bitfield_default },
	 { "AFMT_RESET_FIFO_WHEN_AUDIO_DIS", 11, 11, &umr_bitfield_default },
	 { "AFMT_AUDIO_TEST_EN", 12, 12, &umr_bitfield_default },
	 { "AFMT_AUDIO_TEST_MODE", 14, 14, &umr_bitfield_default },
	 { "AFMT_AUDIO_FIFO_OVERFLOW_ACK", 23, 23, &umr_bitfield_default },
	 { "AFMT_AUDIO_CHANNEL_SWAP", 24, 24, &umr_bitfield_default },
	 { "AFMT_60958_CS_UPDATE", 26, 26, &umr_bitfield_default },
	 { "AFMT_AZ_AUDIO_ENABLE_CHG_ACK", 30, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG6_AFMT_VBI_PACKET_CONTROL[] = {
	 { "AFMT_GENERIC_LOCK_STATUS", 8, 8, &umr_bitfield_default },
	 { "AFMT_GENERIC_CONFLICT", 16, 16, &umr_bitfield_default },
	 { "AFMT_GENERIC_CONFLICT_CLR", 17, 17, &umr_bitfield_default },
	 { "AFMT_GENERIC_INDEX", 28, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG6_AFMT_INFOFRAME_CONTROL0[] = {
	 { "AFMT_AUDIO_INFO_SOURCE", 6, 6, &umr_bitfield_default },
	 { "AFMT_AUDIO_INFO_UPDATE", 7, 7, &umr_bitfield_default },
	 { "AFMT_MPEG_INFO_UPDATE", 10, 10, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG6_AFMT_AUDIO_SRC_CONTROL[] = {
	 { "AFMT_AUDIO_SRC_SELECT", 0, 2, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG6_DIG_BE_CNTL[] = {
	 { "DIG_DUAL_LINK_ENABLE", 0, 0, &umr_bitfield_default },
	 { "DIG_SWAP", 1, 1, &umr_bitfield_default },
	 { "DIG_FE_SOURCE_SELECT", 8, 14, &umr_bitfield_default },
	 { "DIG_MODE", 16, 18, &umr_bitfield_default },
	 { "DIG_HPD_SELECT", 28, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG6_DIG_BE_EN_CNTL[] = {
	 { "DIG_ENABLE", 0, 0, &umr_bitfield_default },
	 { "DIG_SYMCLK_BE_ON", 8, 8, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG6_TMDS_CNTL[] = {
	 { "TMDS_SYNC_PHASE", 0, 0, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG6_TMDS_CONTROL_CHAR[] = {
	 { "TMDS_CONTROL_CHAR0_OUT_EN", 0, 0, &umr_bitfield_default },
	 { "TMDS_CONTROL_CHAR1_OUT_EN", 1, 1, &umr_bitfield_default },
	 { "TMDS_CONTROL_CHAR2_OUT_EN", 2, 2, &umr_bitfield_default },
	 { "TMDS_CONTROL_CHAR3_OUT_EN", 3, 3, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG6_TMDS_CONTROL0_FEEDBACK[] = {
	 { "TMDS_CONTROL0_FEEDBACK_SELECT", 0, 1, &umr_bitfield_default },
	 { "TMDS_CONTROL0_FEEDBACK_DELAY", 8, 9, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG6_TMDS_STEREOSYNC_CTL_SEL[] = {
	 { "TMDS_STEREOSYNC_CTL_SEL", 0, 1, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG6_TMDS_SYNC_CHAR_PATTERN_0_1[] = {
	 { "TMDS_SYNC_CHAR_PATTERN0", 0, 9, &umr_bitfield_default },
	 { "TMDS_SYNC_CHAR_PATTERN1", 16, 25, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG6_TMDS_SYNC_CHAR_PATTERN_2_3[] = {
	 { "TMDS_SYNC_CHAR_PATTERN2", 0, 9, &umr_bitfield_default },
	 { "TMDS_SYNC_CHAR_PATTERN3", 16, 25, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG6_TMDS_CTL_BITS[] = {
	 { "TMDS_CTL0", 0, 0, &umr_bitfield_default },
	 { "TMDS_CTL1", 8, 8, &umr_bitfield_default },
	 { "TMDS_CTL2", 16, 16, &umr_bitfield_default },
	 { "TMDS_CTL3", 24, 24, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG6_TMDS_DCBALANCER_CONTROL[] = {
	 { "TMDS_DCBALANCER_EN", 0, 0, &umr_bitfield_default },
	 { "TMDS_DCBALANCER_TEST_EN", 8, 8, &umr_bitfield_default },
	 { "TMDS_DCBALANCER_TEST_IN", 16, 19, &umr_bitfield_default },
	 { "TMDS_DCBALANCER_FORCE", 24, 24, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG6_TMDS_CTL0_1_GEN_CNTL[] = {
	 { "TMDS_CTL0_DATA_SEL", 0, 3, &umr_bitfield_default },
	 { "TMDS_CTL0_DATA_DELAY", 4, 6, &umr_bitfield_default },
	 { "TMDS_CTL0_DATA_INVERT", 7, 7, &umr_bitfield_default },
	 { "TMDS_CTL0_DATA_MODULATION", 8, 9, &umr_bitfield_default },
	 { "TMDS_CTL0_USE_FEEDBACK_PATH", 10, 10, &umr_bitfield_default },
	 { "TMDS_CTL0_FB_SYNC_CONT", 11, 11, &umr_bitfield_default },
	 { "TMDS_CTL0_PATTERN_OUT_EN", 12, 12, &umr_bitfield_default },
	 { "TMDS_CTL1_DATA_SEL", 16, 19, &umr_bitfield_default },
	 { "TMDS_CTL1_DATA_DELAY", 20, 22, &umr_bitfield_default },
	 { "TMDS_CTL1_DATA_INVERT", 23, 23, &umr_bitfield_default },
	 { "TMDS_CTL1_DATA_MODULATION", 24, 25, &umr_bitfield_default },
	 { "TMDS_CTL1_USE_FEEDBACK_PATH", 26, 26, &umr_bitfield_default },
	 { "TMDS_CTL1_FB_SYNC_CONT", 27, 27, &umr_bitfield_default },
	 { "TMDS_CTL1_PATTERN_OUT_EN", 28, 28, &umr_bitfield_default },
	 { "TMDS_2BIT_COUNTER_EN", 31, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG6_TMDS_CTL2_3_GEN_CNTL[] = {
	 { "TMDS_CTL2_DATA_SEL", 0, 3, &umr_bitfield_default },
	 { "TMDS_CTL2_DATA_DELAY", 4, 6, &umr_bitfield_default },
	 { "TMDS_CTL2_DATA_INVERT", 7, 7, &umr_bitfield_default },
	 { "TMDS_CTL2_DATA_MODULATION", 8, 9, &umr_bitfield_default },
	 { "TMDS_CTL2_USE_FEEDBACK_PATH", 10, 10, &umr_bitfield_default },
	 { "TMDS_CTL2_FB_SYNC_CONT", 11, 11, &umr_bitfield_default },
	 { "TMDS_CTL2_PATTERN_OUT_EN", 12, 12, &umr_bitfield_default },
	 { "TMDS_CTL3_DATA_SEL", 16, 19, &umr_bitfield_default },
	 { "TMDS_CTL3_DATA_DELAY", 20, 22, &umr_bitfield_default },
	 { "TMDS_CTL3_DATA_INVERT", 23, 23, &umr_bitfield_default },
	 { "TMDS_CTL3_DATA_MODULATION", 24, 25, &umr_bitfield_default },
	 { "TMDS_CTL3_USE_FEEDBACK_PATH", 26, 26, &umr_bitfield_default },
	 { "TMDS_CTL3_FB_SYNC_CONT", 27, 27, &umr_bitfield_default },
	 { "TMDS_CTL3_PATTERN_OUT_EN", 28, 28, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG6_DIG_VERSION[] = {
	 { "DIG_TYPE", 0, 0, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG6_DIG_LANE_ENABLE[] = {
	 { "DIG_LANE0EN", 0, 0, &umr_bitfield_default },
	 { "DIG_LANE1EN", 1, 1, &umr_bitfield_default },
	 { "DIG_LANE2EN", 2, 2, &umr_bitfield_default },
	 { "DIG_LANE3EN", 3, 3, &umr_bitfield_default },
	 { "DIG_CLK_EN", 8, 8, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG6_AFMT_CNTL[] = {
	 { "AFMT_AUDIO_CLOCK_EN", 0, 0, &umr_bitfield_default },
	 { "AFMT_AUDIO_CLOCK_ON", 8, 8, &umr_bitfield_default },
};
static struct umr_bitfield mmDIG6_AFMT_VBI_PACKET_CONTROL1[] = {
	 { "AFMT_GENERIC0_FRAME_UPDATE", 0, 0, &umr_bitfield_default },
	 { "AFMT_GENERIC0_FRAME_UPDATE_PENDING", 1, 1, &umr_bitfield_default },
	 { "AFMT_GENERIC0_IMMEDIATE_UPDATE", 2, 2, &umr_bitfield_default },
	 { "AFMT_GENERIC0_IMMEDIATE_UPDATE_PENDING", 3, 3, &umr_bitfield_default },
	 { "AFMT_GENERIC1_FRAME_UPDATE", 4, 4, &umr_bitfield_default },
	 { "AFMT_GENERIC1_FRAME_UPDATE_PENDING", 5, 5, &umr_bitfield_default },
	 { "AFMT_GENERIC1_IMMEDIATE_UPDATE", 6, 6, &umr_bitfield_default },
	 { "AFMT_GENERIC1_IMMEDIATE_UPDATE_PENDING", 7, 7, &umr_bitfield_default },
	 { "AFMT_GENERIC2_FRAME_UPDATE", 8, 8, &umr_bitfield_default },
	 { "AFMT_GENERIC2_FRAME_UPDATE_PENDING", 9, 9, &umr_bitfield_default },
	 { "AFMT_GENERIC2_IMMEDIATE_UPDATE", 10, 10, &umr_bitfield_default },
	 { "AFMT_GENERIC2_IMMEDIATE_UPDATE_PENDING", 11, 11, &umr_bitfield_default },
	 { "AFMT_GENERIC3_FRAME_UPDATE", 12, 12, &umr_bitfield_default },
	 { "AFMT_GENERIC3_FRAME_UPDATE_PENDING", 13, 13, &umr_bitfield_default },
	 { "AFMT_GENERIC3_IMMEDIATE_UPDATE", 14, 14, &umr_bitfield_default },
	 { "AFMT_GENERIC3_IMMEDIATE_UPDATE_PENDING", 15, 15, &umr_bitfield_default },
	 { "AFMT_GENERIC4_FRAME_UPDATE", 16, 16, &umr_bitfield_default },
	 { "AFMT_GENERIC4_FRAME_UPDATE_PENDING", 17, 17, &umr_bitfield_default },
	 { "AFMT_GENERIC4_IMMEDIATE_UPDATE", 18, 18, &umr_bitfield_default },
	 { "AFMT_GENERIC4_IMMEDIATE_UPDATE_PENDING", 19, 19, &umr_bitfield_default },
	 { "AFMT_GENERIC5_FRAME_UPDATE", 20, 20, &umr_bitfield_default },
	 { "AFMT_GENERIC5_FRAME_UPDATE_PENDING", 21, 21, &umr_bitfield_default },
	 { "AFMT_GENERIC5_IMMEDIATE_UPDATE", 22, 22, &umr_bitfield_default },
	 { "AFMT_GENERIC5_IMMEDIATE_UPDATE_PENDING", 23, 23, &umr_bitfield_default },
	 { "AFMT_GENERIC6_FRAME_UPDATE", 24, 24, &umr_bitfield_default },
	 { "AFMT_GENERIC6_FRAME_UPDATE_PENDING", 25, 25, &umr_bitfield_default },
	 { "AFMT_GENERIC6_IMMEDIATE_UPDATE", 26, 26, &umr_bitfield_default },
	 { "AFMT_GENERIC6_IMMEDIATE_UPDATE_PENDING", 27, 27, &umr_bitfield_default },
	 { "AFMT_GENERIC7_FRAME_UPDATE", 28, 28, &umr_bitfield_default },
	 { "AFMT_GENERIC7_FRAME_UPDATE_PENDING", 29, 29, &umr_bitfield_default },
	 { "AFMT_GENERIC7_IMMEDIATE_UPDATE", 30, 30, &umr_bitfield_default },
	 { "AFMT_GENERIC7_IMMEDIATE_UPDATE_PENDING", 31, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDP6_DP_LINK_CNTL[] = {
	 { "DP_LINK_TRAINING_COMPLETE", 4, 4, &umr_bitfield_default },
	 { "DP_LINK_STATUS", 8, 8, &umr_bitfield_default },
	 { "DP_EMBEDDED_PANEL_MODE", 17, 17, &umr_bitfield_default },
};
static struct umr_bitfield mmDP6_DP_PIXEL_FORMAT[] = {
	 { "DP_PIXEL_ENCODING", 0, 2, &umr_bitfield_default },
	 { "DP_COMPONENT_DEPTH", 24, 26, &umr_bitfield_default },
	 { "DP_PIXEL_COMBINE", 28, 29, &umr_bitfield_default },
};
static struct umr_bitfield mmDP6_DP_MSA_COLORIMETRY[] = {
	 { "DP_MSA_MISC0", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDP6_DP_CONFIG[] = {
	 { "DP_UDI_LANES", 0, 1, &umr_bitfield_default },
};
static struct umr_bitfield mmDP6_DP_VID_STREAM_CNTL[] = {
	 { "DP_VID_STREAM_ENABLE", 0, 0, &umr_bitfield_default },
	 { "DP_VID_STREAM_DIS_DEFER", 8, 9, &umr_bitfield_default },
	 { "DP_VID_STREAM_STATUS", 16, 16, &umr_bitfield_default },
	 { "DP_VID_STREAM_CHANGE_KEEPOUT", 20, 20, &umr_bitfield_default },
};
static struct umr_bitfield mmDP6_DP_STEER_FIFO[] = {
	 { "DP_STEER_FIFO_RESET", 0, 0, &umr_bitfield_default },
	 { "DP_STEER_OVERFLOW_FLAG", 4, 4, &umr_bitfield_default },
	 { "DP_STEER_OVERFLOW_INT", 5, 5, &umr_bitfield_default },
	 { "DP_STEER_OVERFLOW_ACK", 6, 6, &umr_bitfield_default },
	 { "DP_STEER_OVERFLOW_MASK", 7, 7, &umr_bitfield_default },
	 { "DP_TU_OVERFLOW_FLAG", 8, 8, &umr_bitfield_default },
	 { "DP_TU_OVERFLOW_ACK", 12, 12, &umr_bitfield_default },
};
static struct umr_bitfield mmDP6_DP_MSA_MISC[] = {
	 { "DP_MSA_MISC1", 0, 7, &umr_bitfield_default },
	 { "DP_MSA_MISC2", 8, 15, &umr_bitfield_default },
	 { "DP_MSA_MISC3", 16, 23, &umr_bitfield_default },
	 { "DP_MSA_MISC4", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDP6_DP_VID_TIMING[] = {
	 { "DP_VID_M_N_DOUBLE_BUFFER_MODE", 4, 4, &umr_bitfield_default },
	 { "DP_VID_M_N_GEN_EN", 8, 8, &umr_bitfield_default },
	 { "DP_VID_N_MUL", 10, 11, &umr_bitfield_default },
	 { "DP_VID_M_DIV", 12, 13, &umr_bitfield_default },
	 { "DP_VID_N_DIV", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDP6_DP_VID_N[] = {
	 { "DP_VID_N", 0, 23, &umr_bitfield_default },
};
static struct umr_bitfield mmDP6_DP_VID_M[] = {
	 { "DP_VID_M", 0, 23, &umr_bitfield_default },
};
static struct umr_bitfield mmDP6_DP_LINK_FRAMING_CNTL[] = {
	 { "DP_IDLE_BS_INTERVAL", 0, 17, &umr_bitfield_default },
	 { "DP_VBID_DISABLE", 24, 24, &umr_bitfield_default },
	 { "DP_VID_ENHANCED_FRAME_MODE", 28, 28, &umr_bitfield_default },
};
static struct umr_bitfield mmDP6_DP_HBR2_EYE_PATTERN[] = {
	 { "DP_HBR2_EYE_PATTERN_ENABLE", 0, 0, &umr_bitfield_default },
};
static struct umr_bitfield mmDP6_DP_VID_MSA_VBID[] = {
	 { "DP_VID_MSA_LOCATION", 0, 11, &umr_bitfield_default },
	 { "DP_VID_VBID_FIELD_POL", 24, 24, &umr_bitfield_default },
};
static struct umr_bitfield mmDP6_DP_VID_INTERRUPT_CNTL[] = {
	 { "DP_VID_STREAM_DISABLE_INT", 0, 0, &umr_bitfield_default },
	 { "DP_VID_STREAM_DISABLE_ACK", 1, 1, &umr_bitfield_default },
	 { "DP_VID_STREAM_DISABLE_MASK", 2, 2, &umr_bitfield_default },
};
static struct umr_bitfield mmDP6_DP_DPHY_CNTL[] = {
	 { "DPHY_ATEST_SEL_LANE0", 0, 0, &umr_bitfield_default },
	 { "DPHY_ATEST_SEL_LANE1", 1, 1, &umr_bitfield_default },
	 { "DPHY_ATEST_SEL_LANE2", 2, 2, &umr_bitfield_default },
	 { "DPHY_ATEST_SEL_LANE3", 3, 3, &umr_bitfield_default },
	 { "DPHY_BYPASS", 16, 16, &umr_bitfield_default },
	 { "DPHY_SKEW_BYPASS", 24, 24, &umr_bitfield_default },
};
static struct umr_bitfield mmDP6_DP_DPHY_TRAINING_PATTERN_SEL[] = {
	 { "DPHY_TRAINING_PATTERN_SEL", 0, 1, &umr_bitfield_default },
};
static struct umr_bitfield mmDP6_DP_DPHY_SYM0[] = {
	 { "DPHY_SYM1", 0, 9, &umr_bitfield_default },
	 { "DPHY_SYM2", 10, 19, &umr_bitfield_default },
	 { "DPHY_SYM3", 20, 29, &umr_bitfield_default },
};
static struct umr_bitfield mmDP6_DP_DPHY_SYM1[] = {
	 { "DPHY_SYM4", 0, 9, &umr_bitfield_default },
	 { "DPHY_SYM5", 10, 19, &umr_bitfield_default },
	 { "DPHY_SYM6", 20, 29, &umr_bitfield_default },
};
static struct umr_bitfield mmDP6_DP_DPHY_SYM2[] = {
	 { "DPHY_SYM7", 0, 9, &umr_bitfield_default },
	 { "DPHY_SYM8", 10, 19, &umr_bitfield_default },
};
static struct umr_bitfield mmDP6_DP_DPHY_8B10B_CNTL[] = {
	 { "DPHY_8B10B_RESET", 8, 8, &umr_bitfield_default },
	 { "DPHY_8B10B_EXT_DISP", 16, 16, &umr_bitfield_default },
	 { "DPHY_8B10B_CUR_DISP", 24, 24, &umr_bitfield_default },
};
static struct umr_bitfield mmDP6_DP_DPHY_PRBS_CNTL[] = {
	 { "DPHY_PRBS_EN", 0, 0, &umr_bitfield_default },
	 { "DPHY_PRBS_SEL", 4, 5, &umr_bitfield_default },
	 { "DPHY_PRBS_SEED", 8, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmDP6_DP_DPHY_SCRAM_CNTL[] = {
	 { "DPHY_SCRAMBLER_DIS", 0, 0, &umr_bitfield_default },
	 { "DPHY_SCRAMBLER_ADVANCE", 4, 4, &umr_bitfield_default },
	 { "DPHY_SCRAMBLER_BS_COUNT", 8, 17, &umr_bitfield_default },
	 { "DPHY_SCRAMBLER_KCODE", 24, 24, &umr_bitfield_default },
};
static struct umr_bitfield mmDP6_DP_DPHY_CRC_EN[] = {
	 { "DPHY_CRC_EN", 0, 0, &umr_bitfield_default },
	 { "DPHY_CRC_CONT_EN", 4, 4, &umr_bitfield_default },
	 { "DPHY_CRC_RESULT_VALID", 8, 8, &umr_bitfield_default },
};
static struct umr_bitfield mmDP6_DP_DPHY_CRC_CNTL[] = {
	 { "DPHY_CRC_FIELD", 0, 0, &umr_bitfield_default },
	 { "DPHY_CRC_SEL", 4, 5, &umr_bitfield_default },
	 { "DPHY_CRC_MASK", 16, 23, &umr_bitfield_default },
};
static struct umr_bitfield mmDP6_DP_DPHY_CRC_RESULT[] = {
	 { "DPHY_CRC_RESULT", 0, 7, &umr_bitfield_default },
	 { "DPHY_CRC_RESULT1", 8, 15, &umr_bitfield_default },
	 { "DPHY_CRC_RESULT2", 16, 23, &umr_bitfield_default },
	 { "DPHY_CRC_RESULT3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDP6_DP_DPHY_CRC_MST_CNTL[] = {
	 { "DPHY_CRC_MST_FIRST_SLOT", 0, 5, &umr_bitfield_default },
	 { "DPHY_CRC_MST_LAST_SLOT", 8, 13, &umr_bitfield_default },
};
static struct umr_bitfield mmDP6_DP_DPHY_CRC_MST_STATUS[] = {
	 { "DPHY_CRC_MST_PHASE_LOCK", 0, 0, &umr_bitfield_default },
	 { "DPHY_CRC_MST_PHASE_ERROR", 8, 8, &umr_bitfield_default },
	 { "DPHY_CRC_MST_PHASE_ERROR_ACK", 16, 16, &umr_bitfield_default },
};
static struct umr_bitfield mmDP6_DP_DPHY_FAST_TRAINING[] = {
	 { "DPHY_RX_FAST_TRAINING_CAPABLE", 0, 0, &umr_bitfield_default },
	 { "DPHY_SW_FAST_TRAINING_START", 1, 1, &umr_bitfield_default },
	 { "DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN", 2, 2, &umr_bitfield_default },
	 { "DPHY_FAST_TRAINING_TP1_TIME", 8, 19, &umr_bitfield_default },
	 { "DPHY_FAST_TRAINING_TP2_TIME", 20, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDP6_DP_DPHY_FAST_TRAINING_STATUS[] = {
	 { "DPHY_FAST_TRAINING_STATE", 0, 2, &umr_bitfield_default },
	 { "DPHY_FAST_TRAINING_COMPLETE_OCCURRED", 4, 4, &umr_bitfield_default },
	 { "DPHY_FAST_TRAINING_COMPLETE_MASK", 8, 8, &umr_bitfield_default },
	 { "DPHY_FAST_TRAINING_COMPLETE_ACK", 12, 12, &umr_bitfield_default },
};
static struct umr_bitfield mmDP6_DP_SEC_CNTL[] = {
	 { "DP_SEC_STREAM_ENABLE", 0, 0, &umr_bitfield_default },
	 { "DP_SEC_ASP_ENABLE", 4, 4, &umr_bitfield_default },
	 { "DP_SEC_ATP_ENABLE", 8, 8, &umr_bitfield_default },
	 { "DP_SEC_AIP_ENABLE", 12, 12, &umr_bitfield_default },
	 { "DP_SEC_ACM_ENABLE", 16, 16, &umr_bitfield_default },
	 { "DP_SEC_GSP0_ENABLE", 20, 20, &umr_bitfield_default },
	 { "DP_SEC_GSP1_ENABLE", 21, 21, &umr_bitfield_default },
	 { "DP_SEC_GSP2_ENABLE", 22, 22, &umr_bitfield_default },
	 { "DP_SEC_GSP3_ENABLE", 23, 23, &umr_bitfield_default },
	 { "DP_SEC_GSP4_ENABLE", 24, 24, &umr_bitfield_default },
	 { "DP_SEC_GSP5_ENABLE", 25, 25, &umr_bitfield_default },
	 { "DP_SEC_GSP6_ENABLE", 26, 26, &umr_bitfield_default },
	 { "DP_SEC_GSP7_ENABLE", 27, 27, &umr_bitfield_default },
	 { "DP_SEC_MPG_ENABLE", 28, 28, &umr_bitfield_default },
};
static struct umr_bitfield mmDP6_DP_SEC_CNTL1[] = {
	 { "DP_SEC_ISRC_ENABLE", 0, 0, &umr_bitfield_default },
	 { "DP_SEC_GSP0_PRIORITY", 4, 4, &umr_bitfield_default },
	 { "DP_SEC_GSP0_SEND", 5, 5, &umr_bitfield_default },
	 { "DP_SEC_GSP0_SEND_PENDING", 6, 6, &umr_bitfield_default },
	 { "DP_SEC_GSP0_SEND_DEADLINE_MISSED", 7, 7, &umr_bitfield_default },
	 { "DP_SEC_GSP0_SEND_ANY_LINE", 8, 8, &umr_bitfield_default },
	 { "DP_SEC_GSP0_LINE_NUM", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDP6_DP_SEC_FRAMING1[] = {
	 { "DP_SEC_FRAME_START_LOCATION", 0, 11, &umr_bitfield_default },
	 { "DP_SEC_VBLANK_TRANSMIT_WIDTH", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDP6_DP_SEC_FRAMING2[] = {
	 { "DP_SEC_START_POSITION", 0, 15, &umr_bitfield_default },
	 { "DP_SEC_HBLANK_TRANSMIT_WIDTH", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDP6_DP_SEC_FRAMING3[] = {
	 { "DP_SEC_IDLE_FRAME_SIZE", 0, 13, &umr_bitfield_default },
	 { "DP_SEC_IDLE_TRANSMIT_WIDTH", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDP6_DP_SEC_FRAMING4[] = {
	 { "DP_SEC_COLLISION_STATUS", 20, 20, &umr_bitfield_default },
	 { "DP_SEC_COLLISION_ACK", 24, 24, &umr_bitfield_default },
	 { "DP_SEC_AUDIO_MUTE", 28, 28, &umr_bitfield_default },
	 { "DP_SEC_AUDIO_MUTE_STATUS", 29, 29, &umr_bitfield_default },
};
static struct umr_bitfield mmDP6_DP_SEC_AUD_N[] = {
	 { "DP_SEC_AUD_N", 0, 23, &umr_bitfield_default },
};
static struct umr_bitfield mmDP6_DP_SEC_AUD_N_READBACK[] = {
	 { "DP_SEC_AUD_N_READBACK", 0, 23, &umr_bitfield_default },
};
static struct umr_bitfield mmDP6_DP_SEC_AUD_M[] = {
	 { "DP_SEC_AUD_M", 0, 23, &umr_bitfield_default },
};
static struct umr_bitfield mmDP6_DP_SEC_AUD_M_READBACK[] = {
	 { "DP_SEC_AUD_M_READBACK", 0, 23, &umr_bitfield_default },
};
static struct umr_bitfield mmDP6_DP_SEC_TIMESTAMP[] = {
	 { "DP_SEC_TIMESTAMP_MODE", 0, 0, &umr_bitfield_default },
};
static struct umr_bitfield mmDP6_DP_SEC_PACKET_CNTL[] = {
	 { "DP_SEC_ASP_CODING_TYPE", 1, 3, &umr_bitfield_default },
	 { "DP_SEC_ASP_PRIORITY", 4, 4, &umr_bitfield_default },
	 { "DP_SEC_VERSION", 8, 13, &umr_bitfield_default },
	 { "DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE", 16, 16, &umr_bitfield_default },
};
static struct umr_bitfield mmDP6_DP_MSE_RATE_CNTL[] = {
	 { "DP_MSE_RATE_Y", 0, 25, &umr_bitfield_default },
	 { "DP_MSE_RATE_X", 26, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDP6_DP_MSE_RATE_UPDATE[] = {
	 { "DP_MSE_RATE_UPDATE_PENDING", 0, 0, &umr_bitfield_default },
};
static struct umr_bitfield mmDP6_DP_MSE_SAT0[] = {
	 { "DP_MSE_SAT_SRC0", 0, 2, &umr_bitfield_default },
	 { "DP_MSE_SAT_SLOT_COUNT0", 8, 13, &umr_bitfield_default },
	 { "DP_MSE_SAT_SRC1", 16, 18, &umr_bitfield_default },
	 { "DP_MSE_SAT_SLOT_COUNT1", 24, 29, &umr_bitfield_default },
};
static struct umr_bitfield mmDP6_DP_MSE_SAT1[] = {
	 { "DP_MSE_SAT_SRC2", 0, 2, &umr_bitfield_default },
	 { "DP_MSE_SAT_SLOT_COUNT2", 8, 13, &umr_bitfield_default },
	 { "DP_MSE_SAT_SRC3", 16, 18, &umr_bitfield_default },
	 { "DP_MSE_SAT_SLOT_COUNT3", 24, 29, &umr_bitfield_default },
};
static struct umr_bitfield mmDP6_DP_MSE_SAT2[] = {
	 { "DP_MSE_SAT_SRC4", 0, 2, &umr_bitfield_default },
	 { "DP_MSE_SAT_SLOT_COUNT4", 8, 13, &umr_bitfield_default },
	 { "DP_MSE_SAT_SRC5", 16, 18, &umr_bitfield_default },
	 { "DP_MSE_SAT_SLOT_COUNT5", 24, 29, &umr_bitfield_default },
};
static struct umr_bitfield mmDP6_DP_MSE_SAT_UPDATE[] = {
	 { "DP_MSE_SAT_UPDATE", 0, 1, &umr_bitfield_default },
	 { "DP_MSE_16_MTP_KEEPOUT", 8, 8, &umr_bitfield_default },
};
static struct umr_bitfield mmDP6_DP_MSE_LINK_TIMING[] = {
	 { "DP_MSE_LINK_FRAME", 0, 9, &umr_bitfield_default },
	 { "DP_MSE_LINK_LINE", 16, 17, &umr_bitfield_default },
};
static struct umr_bitfield mmDP6_DP_MSE_MISC_CNTL[] = {
	 { "DP_MSE_BLANK_CODE", 0, 0, &umr_bitfield_default },
	 { "DP_MSE_TIMESTAMP_MODE", 4, 4, &umr_bitfield_default },
	 { "DP_MSE_ZERO_ENCODER", 8, 8, &umr_bitfield_default },
};
static struct umr_bitfield mmDP6_DP_DPHY_BS_SR_SWAP_CNTL[] = {
	 { "DPHY_LOAD_BS_COUNT", 0, 9, &umr_bitfield_default },
	 { "DPHY_BS_SR_SWAP_DONE", 15, 15, &umr_bitfield_default },
	 { "DPHY_LOAD_BS_COUNT_START", 16, 16, &umr_bitfield_default },
};
static struct umr_bitfield mmDP6_DP_DPHY_HBR2_PATTERN_CONTROL[] = {
	 { "DP_DPHY_HBR2_PATTERN_CONTROL", 0, 2, &umr_bitfield_default },
};
static struct umr_bitfield mmDP6_DP_MSE_SAT0_STATUS[] = {
	 { "DP_MSE_SAT_SRC0_STATUS", 0, 2, &umr_bitfield_default },
	 { "DP_MSE_SAT_SLOT_COUNT0_STATUS", 8, 13, &umr_bitfield_default },
	 { "DP_MSE_SAT_SRC1_STATUS", 16, 18, &umr_bitfield_default },
	 { "DP_MSE_SAT_SLOT_COUNT1_STATUS", 24, 29, &umr_bitfield_default },
};
static struct umr_bitfield mmDP6_DP_MSE_SAT1_STATUS[] = {
	 { "DP_MSE_SAT_SRC2_STATUS", 0, 2, &umr_bitfield_default },
	 { "DP_MSE_SAT_SLOT_COUNT2_STATUS", 8, 13, &umr_bitfield_default },
	 { "DP_MSE_SAT_SRC3_STATUS", 16, 18, &umr_bitfield_default },
	 { "DP_MSE_SAT_SLOT_COUNT3_STATUS", 24, 29, &umr_bitfield_default },
};
static struct umr_bitfield mmDP6_DP_MSE_SAT2_STATUS[] = {
	 { "DP_MSE_SAT_SRC4_STATUS", 0, 2, &umr_bitfield_default },
	 { "DP_MSE_SAT_SLOT_COUNT4_STATUS", 8, 13, &umr_bitfield_default },
	 { "DP_MSE_SAT_SRC5_STATUS", 16, 18, &umr_bitfield_default },
	 { "DP_MSE_SAT_SLOT_COUNT5_STATUS", 24, 29, &umr_bitfield_default },
};
static struct umr_bitfield mmDP6_DP_MSA_TIMING_PARAM1[] = {
	 { "DP_MSA_VTOTAL", 0, 15, &umr_bitfield_default },
	 { "DP_MSA_HTOTAL", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDP6_DP_MSA_TIMING_PARAM2[] = {
	 { "DP_MSA_VSTART", 0, 15, &umr_bitfield_default },
	 { "DP_MSA_HSTART", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDP6_DP_MSA_TIMING_PARAM3[] = {
	 { "DP_MSA_VSYNCWIDTH", 0, 14, &umr_bitfield_default },
	 { "DP_MSA_VSYNCPOLARITY", 15, 15, &umr_bitfield_default },
	 { "DP_MSA_HSYNCWIDTH", 16, 30, &umr_bitfield_default },
	 { "DP_MSA_HSYNCPOLARITY", 31, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDP6_DP_MSA_TIMING_PARAM4[] = {
	 { "DP_MSA_VHEIGHT", 0, 15, &umr_bitfield_default },
	 { "DP_MSA_HWIDTH", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDP6_DP_MSO_CNTL[] = {
	 { "DP_MSO_NUM_OF_SSTLINK", 0, 1, &umr_bitfield_default },
	 { "DP_MSO_SEC_STREAM_ENABLE", 4, 7, &umr_bitfield_default },
	 { "DP_MSO_SEC_ASP_ENABLE", 8, 11, &umr_bitfield_default },
	 { "DP_MSO_SEC_ATP_ENABLE", 12, 15, &umr_bitfield_default },
	 { "DP_MSO_SEC_AIP_ENABLE", 16, 19, &umr_bitfield_default },
	 { "DP_MSO_SEC_ACM_ENABLE", 20, 23, &umr_bitfield_default },
	 { "DP_MSO_SEC_GSP0_ENABLE", 24, 27, &umr_bitfield_default },
	 { "DP_MSO_SEC_GSP1_ENABLE", 28, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDP6_DP_MSO_CNTL1[] = {
	 { "DP_MSO_SEC_GSP2_ENABLE", 0, 3, &umr_bitfield_default },
	 { "DP_MSO_SEC_GSP3_ENABLE", 4, 7, &umr_bitfield_default },
	 { "DP_MSO_SEC_GSP4_ENABLE", 8, 11, &umr_bitfield_default },
	 { "DP_MSO_SEC_GSP5_ENABLE", 12, 15, &umr_bitfield_default },
	 { "DP_MSO_SEC_GSP6_ENABLE", 16, 19, &umr_bitfield_default },
	 { "DP_MSO_SEC_GSP7_ENABLE", 20, 23, &umr_bitfield_default },
	 { "DP_MSO_SEC_MPG_ENABLE", 24, 27, &umr_bitfield_default },
	 { "DP_MSO_SEC_ISRC_ENABLE", 28, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDP6_DP_DSC_CNTL[] = {
	 { "DP_DSC_EN", 0, 0, &umr_bitfield_default },
};
static struct umr_bitfield mmDP6_DP_SEC_CNTL2[] = {
	 { "DP_SEC_GSP1_SEND", 0, 0, &umr_bitfield_default },
	 { "DP_SEC_GSP1_SEND_PENDING", 1, 1, &umr_bitfield_default },
	 { "DP_SEC_GSP1_SEND_DEADLINE_MISSED", 2, 2, &umr_bitfield_default },
	 { "DP_SEC_GSP1_SEND_ANY_LINE", 3, 3, &umr_bitfield_default },
	 { "DP_SEC_GSP2_SEND", 4, 4, &umr_bitfield_default },
	 { "DP_SEC_GSP2_SEND_PENDING", 5, 5, &umr_bitfield_default },
	 { "DP_SEC_GSP2_SEND_DEADLINE_MISSED", 6, 6, &umr_bitfield_default },
	 { "DP_SEC_GSP2_SEND_ANY_LINE", 7, 7, &umr_bitfield_default },
	 { "DP_SEC_GSP3_SEND", 8, 8, &umr_bitfield_default },
	 { "DP_SEC_GSP3_SEND_PENDING", 9, 9, &umr_bitfield_default },
	 { "DP_SEC_GSP3_SEND_DEADLINE_MISSED", 10, 10, &umr_bitfield_default },
	 { "DP_SEC_GSP3_SEND_ANY_LINE", 11, 11, &umr_bitfield_default },
	 { "DP_SEC_GSP4_SEND", 12, 12, &umr_bitfield_default },
	 { "DP_SEC_GSP4_SEND_PENDING", 13, 13, &umr_bitfield_default },
	 { "DP_SEC_GSP4_SEND_DEADLINE_MISSED", 14, 14, &umr_bitfield_default },
	 { "DP_SEC_GSP4_SEND_ANY_LINE", 15, 15, &umr_bitfield_default },
	 { "DP_SEC_GSP5_SEND", 16, 16, &umr_bitfield_default },
	 { "DP_SEC_GSP5_SEND_PENDING", 17, 17, &umr_bitfield_default },
	 { "DP_SEC_GSP5_SEND_DEADLINE_MISSED", 18, 18, &umr_bitfield_default },
	 { "DP_SEC_GSP5_SEND_ANY_LINE", 19, 19, &umr_bitfield_default },
	 { "DP_SEC_GSP6_SEND", 20, 20, &umr_bitfield_default },
	 { "DP_SEC_GSP6_SEND_PENDING", 21, 21, &umr_bitfield_default },
	 { "DP_SEC_GSP6_SEND_DEADLINE_MISSED", 22, 22, &umr_bitfield_default },
	 { "DP_SEC_GSP6_SEND_ANY_LINE", 23, 23, &umr_bitfield_default },
	 { "DP_SEC_GSP7_SEND", 24, 24, &umr_bitfield_default },
	 { "DP_SEC_GSP7_SEND_PENDING", 25, 25, &umr_bitfield_default },
	 { "DP_SEC_GSP7_SEND_DEADLINE_MISSED", 26, 26, &umr_bitfield_default },
	 { "DP_SEC_GSP7_SEND_ANY_LINE", 27, 27, &umr_bitfield_default },
	 { "DP_SEC_GSP7_PPS", 28, 28, &umr_bitfield_default },
};
static struct umr_bitfield mmDP6_DP_SEC_CNTL3[] = {
	 { "DP_SEC_GSP1_LINE_NUM", 0, 15, &umr_bitfield_default },
	 { "DP_SEC_GSP2_LINE_NUM", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDP6_DP_SEC_CNTL4[] = {
	 { "DP_SEC_GSP3_LINE_NUM", 0, 15, &umr_bitfield_default },
	 { "DP_SEC_GSP4_LINE_NUM", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDP6_DP_SEC_CNTL5[] = {
	 { "DP_SEC_GSP5_LINE_NUM", 0, 15, &umr_bitfield_default },
	 { "DP_SEC_GSP6_LINE_NUM", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDP6_DP_SEC_CNTL6[] = {
	 { "DP_SEC_GSP7_LINE_NUM", 0, 15, &umr_bitfield_default },
};
static struct umr_bitfield mmDP6_DP_SEC_CNTL7[] = {
	 { "DP_SEC_GSP0_SEND_ACTIVE", 0, 0, &umr_bitfield_default },
	 { "DP_SEC_GSP1_SEND_ACTIVE", 4, 4, &umr_bitfield_default },
	 { "DP_SEC_GSP2_SEND_ACTIVE", 8, 8, &umr_bitfield_default },
	 { "DP_SEC_GSP3_SEND_ACTIVE", 12, 12, &umr_bitfield_default },
	 { "DP_SEC_GSP4_SEND_ACTIVE", 16, 16, &umr_bitfield_default },
	 { "DP_SEC_GSP5_SEND_ACTIVE", 20, 20, &umr_bitfield_default },
	 { "DP_SEC_GSP6_SEND_ACTIVE", 24, 24, &umr_bitfield_default },
	 { "DP_SEC_GSP7_SEND_ACTIVE", 28, 28, &umr_bitfield_default },
};
static struct umr_bitfield mmDP6_DP_DB_CNTL[] = {
	 { "DP_DB_PENDING", 0, 0, &umr_bitfield_default },
	 { "DP_DB_TAKEN", 4, 4, &umr_bitfield_default },
	 { "DP_DB_TAKEN_CLR", 5, 5, &umr_bitfield_default },
	 { "DP_DB_LOCK", 8, 8, &umr_bitfield_default },
	 { "DP_DB_DISABLE", 12, 12, &umr_bitfield_default },
};
static struct umr_bitfield mmDP6_DP_MSA_VBID_MISC[] = {
	 { "DP_MSA_MISC1_STEREOSYNC_OVERRIDE", 0, 1, &umr_bitfield_default },
	 { "DP_MSA_MISC1_STEREOSYNC_OVERRIDE_EN", 4, 4, &umr_bitfield_default },
	 { "DP_VBID1_OVERRIDE", 8, 8, &umr_bitfield_default },
	 { "DP_VBID2_OVERRIDE", 9, 9, &umr_bitfield_default },
	 { "DP_VBID1_OVERRIDE_EN", 12, 12, &umr_bitfield_default },
	 { "DP_VBID2_OVERRIDE_EN", 13, 13, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_GENERICA[] = {
	 { "GENERICA_EN", 0, 0, &umr_bitfield_default },
	 { "GENERICA_SEL", 7, 11, &umr_bitfield_default },
	 { "GENERICA_UNIPHY_REFDIV_CLK_SEL", 12, 15, &umr_bitfield_default },
	 { "GENERICA_UNIPHY_FBDIV_CLK_SEL", 16, 19, &umr_bitfield_default },
	 { "GENERICA_UNIPHY_FBDIV_SSC_CLK_SEL", 20, 23, &umr_bitfield_default },
	 { "GENERICA_UNIPHY_FBDIV_CLK_DIV2_SEL", 24, 27, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_GENERICB[] = {
	 { "GENERICB_EN", 0, 0, &umr_bitfield_default },
	 { "GENERICB_SEL", 8, 11, &umr_bitfield_default },
	 { "GENERICB_UNIPHY_REFDIV_CLK_SEL", 12, 15, &umr_bitfield_default },
	 { "GENERICB_UNIPHY_FBDIV_CLK_SEL", 16, 19, &umr_bitfield_default },
	 { "GENERICB_UNIPHY_FBDIV_SSC_CLK_SEL", 20, 23, &umr_bitfield_default },
	 { "GENERICB_UNIPHY_FBDIV_CLK_DIV2_SEL", 24, 27, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_REF_CLK_CNTL[] = {
	 { "HSYNCA_OUTPUT_SEL", 0, 1, &umr_bitfield_default },
	 { "GENLK_CLK_OUTPUT_SEL", 8, 9, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_GPIO_DEBUG[] = {
	 { "DC_GPIO_VIP_DEBUG", 0, 0, &umr_bitfield_default },
	 { "DC_GPIO_MACRO_DEBUG", 8, 9, &umr_bitfield_default },
	 { "DC_GPIO_CHIP_DEBUG_OUT_PIN_SEL", 16, 16, &umr_bitfield_default },
	 { "DC_GPIO_DEBUG_BUS_FLOP_EN", 17, 17, &umr_bitfield_default },
	 { "DPRX_LOOPBACK_ENABLE", 31, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmUNIPHYA_LINK_CNTL[] = {
	 { "UNIPHY_PFREQCHG", 0, 0, &umr_bitfield_default },
	 { "UNIPHY_PIXVLD_RESET", 4, 4, &umr_bitfield_default },
	 { "UNIPHY_MINIMUM_PIXVLD_LOW_DURATION", 8, 10, &umr_bitfield_default },
	 { "UNIPHY_CHANNEL0_INVERT", 12, 12, &umr_bitfield_default },
	 { "UNIPHY_CHANNEL1_INVERT", 13, 13, &umr_bitfield_default },
	 { "UNIPHY_CHANNEL2_INVERT", 14, 14, &umr_bitfield_default },
	 { "UNIPHY_CHANNEL3_INVERT", 15, 15, &umr_bitfield_default },
	 { "UNIPHY_LANE_STAGGER_DELAY", 20, 22, &umr_bitfield_default },
	 { "UNIPHY_LINK_ENABLE_HPD_MASK", 24, 25, &umr_bitfield_default },
};
static struct umr_bitfield mmUNIPHYA_CHANNEL_XBAR_CNTL[] = {
	 { "UNIPHY_CHANNEL0_XBAR_SOURCE", 0, 1, &umr_bitfield_default },
	 { "UNIPHY_CHANNEL1_XBAR_SOURCE", 8, 9, &umr_bitfield_default },
	 { "UNIPHY_CHANNEL2_XBAR_SOURCE", 16, 17, &umr_bitfield_default },
	 { "UNIPHY_CHANNEL3_XBAR_SOURCE", 24, 25, &umr_bitfield_default },
	 { "UNIPHY_LINK_ENABLE", 28, 28, &umr_bitfield_default },
};
static struct umr_bitfield mmUNIPHYB_LINK_CNTL[] = {
	 { "UNIPHY_PFREQCHG", 0, 0, &umr_bitfield_default },
	 { "UNIPHY_PIXVLD_RESET", 4, 4, &umr_bitfield_default },
	 { "UNIPHY_MINIMUM_PIXVLD_LOW_DURATION", 8, 10, &umr_bitfield_default },
	 { "UNIPHY_CHANNEL0_INVERT", 12, 12, &umr_bitfield_default },
	 { "UNIPHY_CHANNEL1_INVERT", 13, 13, &umr_bitfield_default },
	 { "UNIPHY_CHANNEL2_INVERT", 14, 14, &umr_bitfield_default },
	 { "UNIPHY_CHANNEL3_INVERT", 15, 15, &umr_bitfield_default },
	 { "UNIPHY_LANE_STAGGER_DELAY", 20, 22, &umr_bitfield_default },
	 { "UNIPHY_LINK_ENABLE_HPD_MASK", 24, 25, &umr_bitfield_default },
};
static struct umr_bitfield mmUNIPHYB_CHANNEL_XBAR_CNTL[] = {
	 { "UNIPHY_CHANNEL0_XBAR_SOURCE", 0, 1, &umr_bitfield_default },
	 { "UNIPHY_CHANNEL1_XBAR_SOURCE", 8, 9, &umr_bitfield_default },
	 { "UNIPHY_CHANNEL2_XBAR_SOURCE", 16, 17, &umr_bitfield_default },
	 { "UNIPHY_CHANNEL3_XBAR_SOURCE", 24, 25, &umr_bitfield_default },
	 { "UNIPHY_LINK_ENABLE", 28, 28, &umr_bitfield_default },
};
static struct umr_bitfield mmUNIPHYC_LINK_CNTL[] = {
	 { "UNIPHY_PFREQCHG", 0, 0, &umr_bitfield_default },
	 { "UNIPHY_PIXVLD_RESET", 4, 4, &umr_bitfield_default },
	 { "UNIPHY_MINIMUM_PIXVLD_LOW_DURATION", 8, 10, &umr_bitfield_default },
	 { "UNIPHY_CHANNEL0_INVERT", 12, 12, &umr_bitfield_default },
	 { "UNIPHY_CHANNEL1_INVERT", 13, 13, &umr_bitfield_default },
	 { "UNIPHY_CHANNEL2_INVERT", 14, 14, &umr_bitfield_default },
	 { "UNIPHY_CHANNEL3_INVERT", 15, 15, &umr_bitfield_default },
	 { "UNIPHY_LANE_STAGGER_DELAY", 20, 22, &umr_bitfield_default },
	 { "UNIPHY_LINK_ENABLE_HPD_MASK", 24, 25, &umr_bitfield_default },
};
static struct umr_bitfield mmUNIPHYC_CHANNEL_XBAR_CNTL[] = {
	 { "UNIPHY_CHANNEL0_XBAR_SOURCE", 0, 1, &umr_bitfield_default },
	 { "UNIPHY_CHANNEL1_XBAR_SOURCE", 8, 9, &umr_bitfield_default },
	 { "UNIPHY_CHANNEL2_XBAR_SOURCE", 16, 17, &umr_bitfield_default },
	 { "UNIPHY_CHANNEL3_XBAR_SOURCE", 24, 25, &umr_bitfield_default },
	 { "UNIPHY_LINK_ENABLE", 28, 28, &umr_bitfield_default },
};
static struct umr_bitfield mmUNIPHYD_LINK_CNTL[] = {
	 { "UNIPHY_PFREQCHG", 0, 0, &umr_bitfield_default },
	 { "UNIPHY_PIXVLD_RESET", 4, 4, &umr_bitfield_default },
	 { "UNIPHY_MINIMUM_PIXVLD_LOW_DURATION", 8, 10, &umr_bitfield_default },
	 { "UNIPHY_CHANNEL0_INVERT", 12, 12, &umr_bitfield_default },
	 { "UNIPHY_CHANNEL1_INVERT", 13, 13, &umr_bitfield_default },
	 { "UNIPHY_CHANNEL2_INVERT", 14, 14, &umr_bitfield_default },
	 { "UNIPHY_CHANNEL3_INVERT", 15, 15, &umr_bitfield_default },
	 { "UNIPHY_LANE_STAGGER_DELAY", 20, 22, &umr_bitfield_default },
	 { "UNIPHY_LINK_ENABLE_HPD_MASK", 24, 25, &umr_bitfield_default },
};
static struct umr_bitfield mmUNIPHYD_CHANNEL_XBAR_CNTL[] = {
	 { "UNIPHY_CHANNEL0_XBAR_SOURCE", 0, 1, &umr_bitfield_default },
	 { "UNIPHY_CHANNEL1_XBAR_SOURCE", 8, 9, &umr_bitfield_default },
	 { "UNIPHY_CHANNEL2_XBAR_SOURCE", 16, 17, &umr_bitfield_default },
	 { "UNIPHY_CHANNEL3_XBAR_SOURCE", 24, 25, &umr_bitfield_default },
	 { "UNIPHY_LINK_ENABLE", 28, 28, &umr_bitfield_default },
};
static struct umr_bitfield mmUNIPHYE_LINK_CNTL[] = {
	 { "UNIPHY_PFREQCHG", 0, 0, &umr_bitfield_default },
	 { "UNIPHY_PIXVLD_RESET", 4, 4, &umr_bitfield_default },
	 { "UNIPHY_MINIMUM_PIXVLD_LOW_DURATION", 8, 10, &umr_bitfield_default },
	 { "UNIPHY_CHANNEL0_INVERT", 12, 12, &umr_bitfield_default },
	 { "UNIPHY_CHANNEL1_INVERT", 13, 13, &umr_bitfield_default },
	 { "UNIPHY_CHANNEL2_INVERT", 14, 14, &umr_bitfield_default },
	 { "UNIPHY_CHANNEL3_INVERT", 15, 15, &umr_bitfield_default },
	 { "UNIPHY_LANE_STAGGER_DELAY", 20, 22, &umr_bitfield_default },
	 { "UNIPHY_LINK_ENABLE_HPD_MASK", 24, 25, &umr_bitfield_default },
};
static struct umr_bitfield mmUNIPHYE_CHANNEL_XBAR_CNTL[] = {
	 { "UNIPHY_CHANNEL0_XBAR_SOURCE", 0, 1, &umr_bitfield_default },
	 { "UNIPHY_CHANNEL1_XBAR_SOURCE", 8, 9, &umr_bitfield_default },
	 { "UNIPHY_CHANNEL2_XBAR_SOURCE", 16, 17, &umr_bitfield_default },
	 { "UNIPHY_CHANNEL3_XBAR_SOURCE", 24, 25, &umr_bitfield_default },
	 { "UNIPHY_LINK_ENABLE", 28, 28, &umr_bitfield_default },
};
static struct umr_bitfield mmUNIPHYF_LINK_CNTL[] = {
	 { "UNIPHY_PFREQCHG", 0, 0, &umr_bitfield_default },
	 { "UNIPHY_PIXVLD_RESET", 4, 4, &umr_bitfield_default },
	 { "UNIPHY_MINIMUM_PIXVLD_LOW_DURATION", 8, 10, &umr_bitfield_default },
	 { "UNIPHY_CHANNEL0_INVERT", 12, 12, &umr_bitfield_default },
	 { "UNIPHY_CHANNEL1_INVERT", 13, 13, &umr_bitfield_default },
	 { "UNIPHY_CHANNEL2_INVERT", 14, 14, &umr_bitfield_default },
	 { "UNIPHY_CHANNEL3_INVERT", 15, 15, &umr_bitfield_default },
	 { "UNIPHY_LANE_STAGGER_DELAY", 20, 22, &umr_bitfield_default },
	 { "UNIPHY_LINK_ENABLE_HPD_MASK", 24, 25, &umr_bitfield_default },
};
static struct umr_bitfield mmUNIPHYF_CHANNEL_XBAR_CNTL[] = {
	 { "UNIPHY_CHANNEL0_XBAR_SOURCE", 0, 1, &umr_bitfield_default },
	 { "UNIPHY_CHANNEL1_XBAR_SOURCE", 8, 9, &umr_bitfield_default },
	 { "UNIPHY_CHANNEL2_XBAR_SOURCE", 16, 17, &umr_bitfield_default },
	 { "UNIPHY_CHANNEL3_XBAR_SOURCE", 24, 25, &umr_bitfield_default },
	 { "UNIPHY_LINK_ENABLE", 28, 28, &umr_bitfield_default },
};
static struct umr_bitfield mmUNIPHYG_LINK_CNTL[] = {
	 { "UNIPHY_PFREQCHG", 0, 0, &umr_bitfield_default },
	 { "UNIPHY_PIXVLD_RESET", 4, 4, &umr_bitfield_default },
	 { "UNIPHY_MINIMUM_PIXVLD_LOW_DURATION", 8, 10, &umr_bitfield_default },
	 { "UNIPHY_CHANNEL0_INVERT", 12, 12, &umr_bitfield_default },
	 { "UNIPHY_CHANNEL1_INVERT", 13, 13, &umr_bitfield_default },
	 { "UNIPHY_CHANNEL2_INVERT", 14, 14, &umr_bitfield_default },
	 { "UNIPHY_CHANNEL3_INVERT", 15, 15, &umr_bitfield_default },
	 { "UNIPHY_LANE_STAGGER_DELAY", 20, 22, &umr_bitfield_default },
	 { "UNIPHY_LINK_ENABLE_HPD_MASK", 24, 25, &umr_bitfield_default },
};
static struct umr_bitfield mmUNIPHYG_CHANNEL_XBAR_CNTL[] = {
	 { "UNIPHY_CHANNEL0_XBAR_SOURCE", 0, 1, &umr_bitfield_default },
	 { "UNIPHY_CHANNEL1_XBAR_SOURCE", 8, 9, &umr_bitfield_default },
	 { "UNIPHY_CHANNEL2_XBAR_SOURCE", 16, 17, &umr_bitfield_default },
	 { "UNIPHY_CHANNEL3_XBAR_SOURCE", 24, 25, &umr_bitfield_default },
	 { "UNIPHY_LINK_ENABLE", 28, 28, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_WRCMD_DELAY[] = {
	 { "UNIPHY_DELAY", 0, 3, &umr_bitfield_default },
	 { "DAC_DELAY", 4, 7, &umr_bitfield_default },
	 { "DPHY_DELAY", 8, 11, &umr_bitfield_default },
	 { "DCRXPHY_DELAY", 12, 15, &umr_bitfield_default },
	 { "ZCAL_DELAY", 16, 19, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_DVODATA_CONFIG[] = {
	 { "VIP_MUX_EN", 19, 19, &umr_bitfield_default },
	 { "VIP_ALTER_MAPPING_EN", 20, 20, &umr_bitfield_default },
	 { "DVO_ALTER_MAPPING_EN", 21, 21, &umr_bitfield_default },
};
static struct umr_bitfield mmLVTMA_PWRSEQ_CNTL[] = {
	 { "LVTMA_PWRSEQ_EN", 0, 0, &umr_bitfield_default },
	 { "LVTMA_PWRSEQ_DISABLE_SYNCEN_CONTROL_OF_TX_EN", 1, 1, &umr_bitfield_default },
	 { "LVTMA_PWRSEQ_TARGET_STATE", 4, 4, &umr_bitfield_default },
	 { "LVTMA_SYNCEN", 8, 8, &umr_bitfield_default },
	 { "LVTMA_SYNCEN_OVRD", 9, 9, &umr_bitfield_default },
	 { "LVTMA_SYNCEN_POL", 10, 10, &umr_bitfield_default },
	 { "LVTMA_DIGON", 16, 16, &umr_bitfield_default },
	 { "LVTMA_DIGON_OVRD", 17, 17, &umr_bitfield_default },
	 { "LVTMA_DIGON_POL", 18, 18, &umr_bitfield_default },
	 { "LVTMA_BLON", 24, 24, &umr_bitfield_default },
	 { "LVTMA_BLON_OVRD", 25, 25, &umr_bitfield_default },
	 { "LVTMA_BLON_POL", 26, 26, &umr_bitfield_default },
};
static struct umr_bitfield mmLVTMA_PWRSEQ_STATE[] = {
	 { "LVTMA_PWRSEQ_TARGET_STATE_R", 0, 0, &umr_bitfield_default },
	 { "LVTMA_PWRSEQ_DIGON", 1, 1, &umr_bitfield_default },
	 { "LVTMA_PWRSEQ_SYNCEN", 2, 2, &umr_bitfield_default },
	 { "LVTMA_PWRSEQ_BLON", 3, 3, &umr_bitfield_default },
	 { "LVTMA_PWRSEQ_DONE", 4, 4, &umr_bitfield_default },
	 { "LVTMA_PWRSEQ_STATE", 8, 11, &umr_bitfield_default },
};
static struct umr_bitfield mmLVTMA_PWRSEQ_REF_DIV[] = {
	 { "LVTMA_PWRSEQ_REF_DIV", 0, 11, &umr_bitfield_default },
	 { "BL_PWM_REF_DIV", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmLVTMA_PWRSEQ_DELAY1[] = {
	 { "LVTMA_PWRUP_DELAY1", 0, 7, &umr_bitfield_default },
	 { "LVTMA_PWRUP_DELAY2", 8, 15, &umr_bitfield_default },
	 { "LVTMA_PWRDN_DELAY1", 16, 23, &umr_bitfield_default },
	 { "LVTMA_PWRDN_DELAY2", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmLVTMA_PWRSEQ_DELAY2[] = {
	 { "LVTMA_PWRDN_MIN_LENGTH", 0, 7, &umr_bitfield_default },
	 { "LVTMA_PWRUP_DELAY3", 8, 15, &umr_bitfield_default },
	 { "LVTMA_PWRDN_DELAY3", 16, 23, &umr_bitfield_default },
	 { "LVTMA_VARY_BL_OVERRIDE_EN", 24, 24, &umr_bitfield_default },
};
static struct umr_bitfield mmBL_PWM_CNTL[] = {
	 { "BL_ACTIVE_INT_FRAC_CNT", 0, 15, &umr_bitfield_default },
	 { "BL_PWM_FRACTIONAL_EN", 30, 30, &umr_bitfield_default },
	 { "BL_PWM_EN", 31, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmBL_PWM_CNTL2[] = {
	 { "BL_PWM_POST_FRAME_START_DELAY_BEFORE_UPDATE", 0, 15, &umr_bitfield_default },
	 { "BL_PWM_OVERRIDE_BL_OUT_ENABLE", 30, 30, &umr_bitfield_default },
	 { "BL_PWM_OVERRIDE_LVTMA_PWRSEQ_EN", 31, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmBL_PWM_PERIOD_CNTL[] = {
	 { "BL_PWM_PERIOD", 0, 15, &umr_bitfield_default },
	 { "BL_PWM_PERIOD_BITCNT", 16, 19, &umr_bitfield_default },
};
static struct umr_bitfield mmBL_PWM_GRP1_REG_LOCK[] = {
	 { "BL_PWM_GRP1_REG_LOCK", 0, 0, &umr_bitfield_default },
	 { "BL_PWM_GRP1_REG_UPDATE_PENDING", 8, 8, &umr_bitfield_default },
	 { "BL_PWM_GRP1_UPDATE_AT_FRAME_START", 16, 16, &umr_bitfield_default },
	 { "BL_PWM_GRP1_FRAME_START_DISP_SEL", 17, 19, &umr_bitfield_default },
	 { "BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN", 24, 24, &umr_bitfield_default },
	 { "BL_PWM_GRP1_IGNORE_MASTER_LOCK_EN", 31, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_GSL_GENLK_PAD_CNTL[] = {
	 { "DCIO_GENLK_CLK_GSL_FLIP_READY_SEL", 4, 5, &umr_bitfield_default },
	 { "DCIO_GENLK_CLK_GSL_MASK", 8, 9, &umr_bitfield_default },
	 { "DCIO_GENLK_VSYNC_GSL_FLIP_READY_SEL", 20, 21, &umr_bitfield_default },
	 { "DCIO_GENLK_VSYNC_GSL_MASK", 24, 25, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_GSL_SWAPLOCK_PAD_CNTL[] = {
	 { "DCIO_SWAPLOCK_A_GSL_FLIP_READY_SEL", 4, 5, &umr_bitfield_default },
	 { "DCIO_SWAPLOCK_A_GSL_MASK", 8, 9, &umr_bitfield_default },
	 { "DCIO_SWAPLOCK_B_GSL_FLIP_READY_SEL", 20, 21, &umr_bitfield_default },
	 { "DCIO_SWAPLOCK_B_GSL_MASK", 24, 25, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_CLOCK_CNTL[] = {
	 { "DCIO_TEST_CLK_SEL", 0, 4, &umr_bitfield_default },
	 { "DISPCLK_R_DCIO_GATE_DIS", 5, 5, &umr_bitfield_default },
};
static struct umr_bitfield mmDIO_OTG_EXT_VSYNC_CNTL[] = {
	 { "DIO_OTG0_EXT_VSYNC_MUX", 0, 2, &umr_bitfield_default },
	 { "DIO_OTG1_EXT_VSYNC_MUX", 4, 6, &umr_bitfield_default },
	 { "DIO_OTG2_EXT_VSYNC_MUX", 8, 10, &umr_bitfield_default },
	 { "DIO_OTG3_EXT_VSYNC_MUX", 12, 14, &umr_bitfield_default },
	 { "DIO_OTG4_EXT_VSYNC_MUX", 16, 18, &umr_bitfield_default },
	 { "DIO_OTG5_EXT_VSYNC_MUX", 20, 22, &umr_bitfield_default },
	 { "DIO_SWAPLOCKB_EXT_VSYNC_MASK", 24, 26, &umr_bitfield_default },
	 { "DIO_GENERICB_EXT_VSYNC_MASK", 28, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_SOFT_RESET[] = {
	 { "UNIPHYA_SOFT_RESET", 0, 0, &umr_bitfield_default },
	 { "DSYNCA_SOFT_RESET", 1, 1, &umr_bitfield_default },
	 { "UNIPHYB_SOFT_RESET", 2, 2, &umr_bitfield_default },
	 { "DSYNCB_SOFT_RESET", 3, 3, &umr_bitfield_default },
	 { "UNIPHYC_SOFT_RESET", 4, 4, &umr_bitfield_default },
	 { "DSYNCC_SOFT_RESET", 5, 5, &umr_bitfield_default },
	 { "UNIPHYD_SOFT_RESET", 6, 6, &umr_bitfield_default },
	 { "DSYNCD_SOFT_RESET", 7, 7, &umr_bitfield_default },
	 { "UNIPHYE_SOFT_RESET", 8, 8, &umr_bitfield_default },
	 { "DSYNCE_SOFT_RESET", 9, 9, &umr_bitfield_default },
	 { "UNIPHYF_SOFT_RESET", 10, 10, &umr_bitfield_default },
	 { "DSYNCF_SOFT_RESET", 11, 11, &umr_bitfield_default },
	 { "UNIPHYG_SOFT_RESET", 12, 12, &umr_bitfield_default },
	 { "DSYNCG_SOFT_RESET", 13, 13, &umr_bitfield_default },
	 { "DACA_SOFT_RESET", 16, 16, &umr_bitfield_default },
	 { "DCRXPHY_SOFT_RESET", 20, 20, &umr_bitfield_default },
	 { "DPHY_SOFT_RESET", 24, 24, &umr_bitfield_default },
	 { "ZCAL_SOFT_RESET", 26, 26, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_DPHY_SEL[] = {
	 { "DPHY_LANE0_SEL", 0, 1, &umr_bitfield_default },
	 { "DPHY_LANE1_SEL", 2, 3, &umr_bitfield_default },
	 { "DPHY_LANE2_SEL", 4, 5, &umr_bitfield_default },
	 { "DPHY_LANE3_SEL", 6, 7, &umr_bitfield_default },
};
static struct umr_bitfield mmUNIPHY_IMPCAL_LINKA[] = {
	 { "UNIPHY_IMPCAL_ENABLE_LINKA", 0, 0, &umr_bitfield_default },
	 { "UNIPHY_IMPCAL_CALOUT_LINKA", 8, 8, &umr_bitfield_default },
	 { "UNIPHY_CALOUT_ERROR_LINKA", 9, 9, &umr_bitfield_default },
	 { "UNIPHY_CALOUT_ERROR_LINKA_AK", 10, 10, &umr_bitfield_default },
	 { "UNIPHY_IMPCAL_VALUE_LINKA", 16, 19, &umr_bitfield_default },
	 { "UNIPHY_IMPCAL_STEP_DELAY_LINKA", 20, 23, &umr_bitfield_default },
	 { "UNIPHY_IMPCAL_OVERRIDE_LINKA", 24, 27, &umr_bitfield_default },
	 { "UNIPHY_IMPCAL_OVERRIDE_ENABLE_LINKA", 28, 28, &umr_bitfield_default },
	 { "UNIPHY_IMPCAL_SEL_LINKA", 30, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmUNIPHY_IMPCAL_LINKB[] = {
	 { "UNIPHY_IMPCAL_ENABLE_LINKB", 0, 0, &umr_bitfield_default },
	 { "UNIPHY_IMPCAL_CALOUT_LINKB", 8, 8, &umr_bitfield_default },
	 { "UNIPHY_CALOUT_ERROR_LINKB", 9, 9, &umr_bitfield_default },
	 { "UNIPHY_CALOUT_ERROR_LINKB_AK", 10, 10, &umr_bitfield_default },
	 { "UNIPHY_IMPCAL_VALUE_LINKB", 16, 19, &umr_bitfield_default },
	 { "UNIPHY_IMPCAL_STEP_DELAY_LINKB", 20, 23, &umr_bitfield_default },
	 { "UNIPHY_IMPCAL_OVERRIDE_LINKB", 24, 27, &umr_bitfield_default },
	 { "UNIPHY_IMPCAL_OVERRIDE_ENABLE_LINKB", 28, 28, &umr_bitfield_default },
	 { "UNIPHY_IMPCAL_SEL_LINKB", 30, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmUNIPHY_IMPCAL_PERIOD[] = {
	 { "UNIPHY_IMPCAL_PERIOD", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmAUXP_IMPCAL[] = {
	 { "AUXP_IMPCAL_ENABLE", 0, 0, &umr_bitfield_default },
	 { "AUXP_IMPCAL_CALOUT", 8, 8, &umr_bitfield_default },
	 { "AUXP_CALOUT_ERROR", 9, 9, &umr_bitfield_default },
	 { "AUXP_CALOUT_ERROR_AK", 10, 10, &umr_bitfield_default },
	 { "AUXP_IMPCAL_VALUE", 16, 19, &umr_bitfield_default },
	 { "AUXP_IMPCAL_STEP_DELAY", 20, 23, &umr_bitfield_default },
	 { "AUXP_IMPCAL_OVERRIDE", 24, 27, &umr_bitfield_default },
	 { "AUXP_IMPCAL_OVERRIDE_ENABLE", 28, 28, &umr_bitfield_default },
};
static struct umr_bitfield mmAUXN_IMPCAL[] = {
	 { "AUXN_IMPCAL_ENABLE", 0, 0, &umr_bitfield_default },
	 { "AUXN_IMPCAL_CALOUT", 8, 8, &umr_bitfield_default },
	 { "AUXN_CALOUT_ERROR", 9, 9, &umr_bitfield_default },
	 { "AUXN_CALOUT_ERROR_AK", 10, 10, &umr_bitfield_default },
	 { "AUXN_IMPCAL_VALUE", 16, 19, &umr_bitfield_default },
	 { "AUXN_IMPCAL_STEP_DELAY", 20, 23, &umr_bitfield_default },
	 { "AUXN_IMPCAL_OVERRIDE", 24, 27, &umr_bitfield_default },
	 { "AUXN_IMPCAL_OVERRIDE_ENABLE", 28, 28, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_IMPCAL_CNTL[] = {
	 { "CALR_CNTL_OVERRIDE", 0, 3, &umr_bitfield_default },
	 { "IMPCAL_SOFT_RESET", 5, 5, &umr_bitfield_default },
	 { "IMPCAL_STATUS", 8, 9, &umr_bitfield_default },
	 { "IMPCAL_ARB_STATE", 12, 14, &umr_bitfield_default },
	 { "AUX_IMPCAL_INTERVAL", 15, 18, &umr_bitfield_default },
};
static struct umr_bitfield mmUNIPHY_IMPCAL_PSW_AB[] = {
	 { "UNIPHY_IMPCAL_PSW_LINKA", 0, 14, &umr_bitfield_default },
	 { "UNIPHY_IMPCAL_PSW_LINKB", 16, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmUNIPHY_IMPCAL_LINKC[] = {
	 { "UNIPHY_IMPCAL_ENABLE_LINKC", 0, 0, &umr_bitfield_default },
	 { "UNIPHY_IMPCAL_CALOUT_LINKC", 8, 8, &umr_bitfield_default },
	 { "UNIPHY_CALOUT_ERROR_LINKC", 9, 9, &umr_bitfield_default },
	 { "UNIPHY_CALOUT_ERROR_LINKC_AK", 10, 10, &umr_bitfield_default },
	 { "UNIPHY_IMPCAL_VALUE_LINKC", 16, 19, &umr_bitfield_default },
	 { "UNIPHY_IMPCAL_STEP_DELAY_LINKC", 20, 23, &umr_bitfield_default },
	 { "UNIPHY_IMPCAL_OVERRIDE_LINKC", 24, 27, &umr_bitfield_default },
	 { "UNIPHY_IMPCAL_OVERRIDE_ENABLE_LINKC", 28, 28, &umr_bitfield_default },
	 { "UNIPHY_IMPCAL_SEL_LINKC", 30, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmUNIPHY_IMPCAL_LINKD[] = {
	 { "UNIPHY_IMPCAL_ENABLE_LINKD", 0, 0, &umr_bitfield_default },
	 { "UNIPHY_IMPCAL_CALOUT_LINKD", 8, 8, &umr_bitfield_default },
	 { "UNIPHY_CALOUT_ERROR_LINKD", 9, 9, &umr_bitfield_default },
	 { "UNIPHY_CALOUT_ERROR_LINKD_AK", 10, 10, &umr_bitfield_default },
	 { "UNIPHY_IMPCAL_VALUE_LINKD", 16, 19, &umr_bitfield_default },
	 { "UNIPHY_IMPCAL_STEP_DELAY_LINKD", 20, 23, &umr_bitfield_default },
	 { "UNIPHY_IMPCAL_OVERRIDE_LINKD", 24, 27, &umr_bitfield_default },
	 { "UNIPHY_IMPCAL_OVERRIDE_ENABLE_LINKD", 28, 28, &umr_bitfield_default },
	 { "UNIPHY_IMPCAL_SEL_LINKD", 30, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_IMPCAL_CNTL_CD[] = {
	 { "CALR_CNTL_OVERRIDE", 0, 3, &umr_bitfield_default },
	 { "IMPCAL_SOFT_RESET", 5, 5, &umr_bitfield_default },
	 { "IMPCAL_STATUS", 8, 9, &umr_bitfield_default },
	 { "IMPCAL_ARB_STATE", 12, 14, &umr_bitfield_default },
};
static struct umr_bitfield mmUNIPHY_IMPCAL_PSW_CD[] = {
	 { "UNIPHY_IMPCAL_PSW_LINKC", 0, 14, &umr_bitfield_default },
	 { "UNIPHY_IMPCAL_PSW_LINKD", 16, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmUNIPHY_IMPCAL_LINKE[] = {
	 { "UNIPHY_IMPCAL_ENABLE_LINKE", 0, 0, &umr_bitfield_default },
	 { "UNIPHY_IMPCAL_CALOUT_LINKE", 8, 8, &umr_bitfield_default },
	 { "UNIPHY_CALOUT_ERROR_LINKE", 9, 9, &umr_bitfield_default },
	 { "UNIPHY_CALOUT_ERROR_LINKE_AK", 10, 10, &umr_bitfield_default },
	 { "UNIPHY_IMPCAL_VALUE_LINKE", 16, 19, &umr_bitfield_default },
	 { "UNIPHY_IMPCAL_STEP_DELAY_LINKE", 20, 23, &umr_bitfield_default },
	 { "UNIPHY_IMPCAL_OVERRIDE_LINKE", 24, 27, &umr_bitfield_default },
	 { "UNIPHY_IMPCAL_OVERRIDE_ENABLE_LINKE", 28, 28, &umr_bitfield_default },
	 { "UNIPHY_IMPCAL_SEL_LINKE", 30, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmUNIPHY_IMPCAL_LINKF[] = {
	 { "UNIPHY_IMPCAL_ENABLE_LINKF", 0, 0, &umr_bitfield_default },
	 { "UNIPHY_IMPCAL_CALOUT_LINKF", 8, 8, &umr_bitfield_default },
	 { "UNIPHY_CALOUT_ERROR_LINKF", 9, 9, &umr_bitfield_default },
	 { "UNIPHY_CALOUT_ERROR_LINKF_AK", 10, 10, &umr_bitfield_default },
	 { "UNIPHY_IMPCAL_VALUE_LINKF", 16, 19, &umr_bitfield_default },
	 { "UNIPHY_IMPCAL_STEP_DELAY_LINKF", 20, 23, &umr_bitfield_default },
	 { "UNIPHY_IMPCAL_OVERRIDE_LINKF", 24, 27, &umr_bitfield_default },
	 { "UNIPHY_IMPCAL_OVERRIDE_ENABLE_LINKF", 28, 28, &umr_bitfield_default },
	 { "UNIPHY_IMPCAL_SEL_LINKF", 30, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_IMPCAL_CNTL_EF[] = {
	 { "CALR_CNTL_OVERRIDE", 0, 3, &umr_bitfield_default },
	 { "IMPCAL_SOFT_RESET", 5, 5, &umr_bitfield_default },
	 { "IMPCAL_STATUS", 8, 9, &umr_bitfield_default },
	 { "IMPCAL_ARB_STATE", 12, 14, &umr_bitfield_default },
};
static struct umr_bitfield mmUNIPHY_IMPCAL_PSW_EF[] = {
	 { "UNIPHY_IMPCAL_PSW_LINKE", 0, 14, &umr_bitfield_default },
	 { "UNIPHY_IMPCAL_PSW_LINKF", 16, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_DPCS_TX_INTERRUPT[] = {
	 { "DCIO_DPCS_TXA_INT_TYPE", 0, 0, &umr_bitfield_default },
	 { "DCIO_DPCS_TXA_INT_MASK", 1, 1, &umr_bitfield_default },
	 { "DCIO_DPCS_TXA_INT_OCCUR", 2, 2, &umr_bitfield_default },
	 { "DCIO_DPCS_TXB_INT_TYPE", 3, 3, &umr_bitfield_default },
	 { "DCIO_DPCS_TXB_INT_MASK", 4, 4, &umr_bitfield_default },
	 { "DCIO_DPCS_TXB_INT_OCCUR", 5, 5, &umr_bitfield_default },
	 { "DCIO_DPCS_TXC_INT_TYPE", 6, 6, &umr_bitfield_default },
	 { "DCIO_DPCS_TXC_INT_MASK", 7, 7, &umr_bitfield_default },
	 { "DCIO_DPCS_TXC_INT_OCCUR", 8, 8, &umr_bitfield_default },
	 { "DCIO_DPCS_TXD_INT_TYPE", 9, 9, &umr_bitfield_default },
	 { "DCIO_DPCS_TXD_INT_MASK", 10, 10, &umr_bitfield_default },
	 { "DCIO_DPCS_TXD_INT_OCCUR", 11, 11, &umr_bitfield_default },
	 { "DCIO_DPCS_TXE_INT_TYPE", 12, 12, &umr_bitfield_default },
	 { "DCIO_DPCS_TXE_INT_MASK", 13, 13, &umr_bitfield_default },
	 { "DCIO_DPCS_TXE_INT_OCCUR", 14, 14, &umr_bitfield_default },
	 { "DCIO_DPCS_TXF_INT_TYPE", 15, 15, &umr_bitfield_default },
	 { "DCIO_DPCS_TXF_INT_MASK", 16, 16, &umr_bitfield_default },
	 { "DCIO_DPCS_TXF_INT_OCCUR", 17, 17, &umr_bitfield_default },
	 { "DCIO_DPCS_TXG_INT_TYPE", 18, 18, &umr_bitfield_default },
	 { "DCIO_DPCS_TXG_INT_MASK", 19, 19, &umr_bitfield_default },
	 { "DCIO_DPCS_TXG_INT_OCCUR", 20, 20, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_DPCS_RX_INTERRUPT[] = {
	 { "DCIO_DPCS_RXA_INT_TYPE", 0, 0, &umr_bitfield_default },
	 { "DCIO_DPCS_RXA_INT_MASK", 1, 1, &umr_bitfield_default },
	 { "DCIO_DPCS_RXA_INT_OCCUR", 2, 2, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_SEMAPHORE0[] = {
	 { "DCIO_SEMAPHORE0_REQ", 0, 15, &umr_bitfield_default },
	 { "DCIO_SEMAPHORE0_GNT", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_SEMAPHORE1[] = {
	 { "DCIO_SEMAPHORE1_REQ", 0, 15, &umr_bitfield_default },
	 { "DCIO_SEMAPHORE1_GNT", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_SEMAPHORE2[] = {
	 { "DCIO_SEMAPHORE2_REQ", 0, 15, &umr_bitfield_default },
	 { "DCIO_SEMAPHORE2_GNT", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_SEMAPHORE3[] = {
	 { "DCIO_SEMAPHORE3_REQ", 0, 15, &umr_bitfield_default },
	 { "DCIO_SEMAPHORE3_GNT", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_SEMAPHORE4[] = {
	 { "DCIO_SEMAPHORE4_REQ", 0, 15, &umr_bitfield_default },
	 { "DCIO_SEMAPHORE4_GNT", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_SEMAPHORE5[] = {
	 { "DCIO_SEMAPHORE5_REQ", 0, 15, &umr_bitfield_default },
	 { "DCIO_SEMAPHORE5_GNT", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_SEMAPHORE6[] = {
	 { "DCIO_SEMAPHORE6_REQ", 0, 15, &umr_bitfield_default },
	 { "DCIO_SEMAPHORE6_GNT", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_SEMAPHORE7[] = {
	 { "DCIO_SEMAPHORE7_REQ", 0, 15, &umr_bitfield_default },
	 { "DCIO_SEMAPHORE7_GNT", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_USBC_FLIP_EN_SEL[] = {
	 { "DCIO_UNIPHYA_USBC_FLIP_EN_SEL", 0, 2, &umr_bitfield_default },
	 { "DCIO_UNIPHYB_USBC_FLIP_EN_SEL", 4, 6, &umr_bitfield_default },
	 { "DCIO_UNIPHYC_USBC_FLIP_EN_SEL", 8, 10, &umr_bitfield_default },
	 { "DCIO_UNIPHYD_USBC_FLIP_EN_SEL", 12, 14, &umr_bitfield_default },
	 { "DCIO_UNIPHYE_USBC_FLIP_EN_SEL", 16, 18, &umr_bitfield_default },
	 { "DCIO_UNIPHYF_USBC_FLIP_EN_SEL", 20, 22, &umr_bitfield_default },
	 { "DCIO_FCH_DC_LINKA_USBC_DP_FLIP_EN", 24, 24, &umr_bitfield_default },
	 { "DCIO_FCH_DC_LINKB_USBC_DP_FLIP_EN", 25, 25, &umr_bitfield_default },
	 { "DCIO_FCH_DC_LINKC_USBC_DP_FLIP_EN", 26, 26, &umr_bitfield_default },
	 { "DCIO_FCH_DC_LINKD_USBC_DP_FLIP_EN", 27, 27, &umr_bitfield_default },
	 { "DCIO_FCH_DC_LINKE_USBC_DP_FLIP_EN", 28, 28, &umr_bitfield_default },
	 { "DCIO_FCH_DC_LINKF_USBC_DP_FLIP_EN", 29, 29, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_GPIO_GENERIC_MASK[] = {
	 { "DC_GPIO_GENERICA_MASK", 0, 0, &umr_bitfield_default },
	 { "DC_GPIO_GENERICA_PD_DIS", 1, 1, &umr_bitfield_default },
	 { "DC_GPIO_GENERICA_RECV", 2, 3, &umr_bitfield_default },
	 { "DC_GPIO_GENERICB_MASK", 4, 4, &umr_bitfield_default },
	 { "DC_GPIO_GENERICB_PD_DIS", 5, 5, &umr_bitfield_default },
	 { "DC_GPIO_GENERICB_RECV", 6, 7, &umr_bitfield_default },
	 { "DC_GPIO_GENERICC_MASK", 8, 8, &umr_bitfield_default },
	 { "DC_GPIO_GENERICC_PD_DIS", 9, 9, &umr_bitfield_default },
	 { "DC_GPIO_GENERICC_RECV", 10, 11, &umr_bitfield_default },
	 { "DC_GPIO_GENERICD_MASK", 12, 12, &umr_bitfield_default },
	 { "DC_GPIO_GENERICD_PD_DIS", 13, 13, &umr_bitfield_default },
	 { "DC_GPIO_GENERICD_RECV", 14, 15, &umr_bitfield_default },
	 { "DC_GPIO_GENERICE_MASK", 16, 16, &umr_bitfield_default },
	 { "DC_GPIO_GENERICE_PD_DIS", 17, 17, &umr_bitfield_default },
	 { "DC_GPIO_GENERICE_RECV", 18, 19, &umr_bitfield_default },
	 { "DC_GPIO_GENERICF_MASK", 20, 20, &umr_bitfield_default },
	 { "DC_GPIO_GENERICF_PD_DIS", 21, 21, &umr_bitfield_default },
	 { "DC_GPIO_GENERICF_RECV", 22, 23, &umr_bitfield_default },
	 { "DC_GPIO_GENERICG_MASK", 24, 24, &umr_bitfield_default },
	 { "DC_GPIO_GENERICG_PD_DIS", 25, 25, &umr_bitfield_default },
	 { "DC_GPIO_GENERICG_RECV", 26, 27, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_GPIO_GENERIC_A[] = {
	 { "DC_GPIO_GENERICA_A", 0, 0, &umr_bitfield_default },
	 { "DC_GPIO_GENERICB_A", 8, 8, &umr_bitfield_default },
	 { "DC_GPIO_GENERICC_A", 16, 16, &umr_bitfield_default },
	 { "DC_GPIO_GENERICD_A", 20, 20, &umr_bitfield_default },
	 { "DC_GPIO_GENERICE_A", 21, 21, &umr_bitfield_default },
	 { "DC_GPIO_GENERICF_A", 22, 22, &umr_bitfield_default },
	 { "DC_GPIO_GENERICG_A", 23, 23, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_GPIO_GENERIC_EN[] = {
	 { "DC_GPIO_GENERICA_EN", 0, 0, &umr_bitfield_default },
	 { "DC_GPIO_GENERICB_EN", 8, 8, &umr_bitfield_default },
	 { "DC_GPIO_GENERICC_EN", 16, 16, &umr_bitfield_default },
	 { "DC_GPIO_GENERICD_EN", 20, 20, &umr_bitfield_default },
	 { "DC_GPIO_GENERICE_EN", 21, 21, &umr_bitfield_default },
	 { "DC_GPIO_GENERICF_EN", 22, 22, &umr_bitfield_default },
	 { "DC_GPIO_GENERICG_EN", 23, 23, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_GPIO_GENERIC_Y[] = {
	 { "DC_GPIO_GENERICA_Y", 0, 0, &umr_bitfield_default },
	 { "DC_GPIO_GENERICB_Y", 8, 8, &umr_bitfield_default },
	 { "DC_GPIO_GENERICC_Y", 16, 16, &umr_bitfield_default },
	 { "DC_GPIO_GENERICD_Y", 20, 20, &umr_bitfield_default },
	 { "DC_GPIO_GENERICE_Y", 21, 21, &umr_bitfield_default },
	 { "DC_GPIO_GENERICF_Y", 22, 22, &umr_bitfield_default },
	 { "DC_GPIO_GENERICG_Y", 23, 23, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_GPIO_DVODATA_MASK[] = {
	 { "DC_GPIO_DVODATA_MASK", 0, 23, &umr_bitfield_default },
	 { "DC_GPIO_DVOCNTL_MASK", 24, 28, &umr_bitfield_default },
	 { "DC_GPIO_DVOCLK_MASK", 29, 29, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_GPIO_DVODATA_A[] = {
	 { "DC_GPIO_DVODATA_A", 0, 23, &umr_bitfield_default },
	 { "DC_GPIO_DVOCNTL_A", 24, 28, &umr_bitfield_default },
	 { "DC_GPIO_DVOCLK_A", 29, 29, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_GPIO_DVODATA_EN[] = {
	 { "DC_GPIO_DVODATA_EN", 0, 23, &umr_bitfield_default },
	 { "DC_GPIO_DVOCNTL_EN", 24, 28, &umr_bitfield_default },
	 { "DC_GPIO_DVOCLK_EN", 29, 29, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_GPIO_DVODATA_Y[] = {
	 { "DC_GPIO_DVODATA_Y", 0, 23, &umr_bitfield_default },
	 { "DC_GPIO_DVOCNTL_Y", 24, 28, &umr_bitfield_default },
	 { "DC_GPIO_DVOCLK_Y", 29, 29, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_GPIO_DDC1_MASK[] = {
	 { "DC_GPIO_DDC1CLK_MASK", 0, 0, &umr_bitfield_default },
	 { "DC_GPIO_DDC1CLK_PD_EN", 4, 4, &umr_bitfield_default },
	 { "DC_GPIO_DDC1CLK_RECV", 6, 6, &umr_bitfield_default },
	 { "DC_GPIO_DDC1DATA_MASK", 8, 8, &umr_bitfield_default },
	 { "DC_GPIO_DDC1DATA_PD_EN", 12, 12, &umr_bitfield_default },
	 { "DC_GPIO_DDC1DATA_RECV", 14, 14, &umr_bitfield_default },
	 { "AUX_PAD1_MODE", 16, 16, &umr_bitfield_default },
	 { "AUX1_POL", 20, 20, &umr_bitfield_default },
	 { "ALLOW_HW_DDC1_PD_EN", 22, 22, &umr_bitfield_default },
	 { "DC_GPIO_DDC1CLK_STR", 24, 27, &umr_bitfield_default },
	 { "DC_GPIO_DDC1DATA_STR", 28, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_GPIO_DDC1_A[] = {
	 { "DC_GPIO_DDC1CLK_A", 0, 0, &umr_bitfield_default },
	 { "DC_GPIO_DDC1DATA_A", 8, 8, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_GPIO_DDC1_EN[] = {
	 { "DC_GPIO_DDC1CLK_EN", 0, 0, &umr_bitfield_default },
	 { "DC_GPIO_DDC1DATA_EN", 8, 8, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_GPIO_DDC1_Y[] = {
	 { "DC_GPIO_DDC1CLK_Y", 0, 0, &umr_bitfield_default },
	 { "DC_GPIO_DDC1DATA_Y", 8, 8, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_GPIO_DDC2_MASK[] = {
	 { "DC_GPIO_DDC2CLK_MASK", 0, 0, &umr_bitfield_default },
	 { "DC_GPIO_DDC2CLK_PD_EN", 4, 4, &umr_bitfield_default },
	 { "DC_GPIO_DDC2CLK_RECV", 6, 6, &umr_bitfield_default },
	 { "DC_GPIO_DDC2DATA_MASK", 8, 8, &umr_bitfield_default },
	 { "DC_GPIO_DDC2DATA_PD_EN", 12, 12, &umr_bitfield_default },
	 { "DC_GPIO_DDC2DATA_RECV", 14, 14, &umr_bitfield_default },
	 { "AUX_PAD2_MODE", 16, 16, &umr_bitfield_default },
	 { "AUX2_POL", 20, 20, &umr_bitfield_default },
	 { "ALLOW_HW_DDC2_PD_EN", 22, 22, &umr_bitfield_default },
	 { "DC_GPIO_DDC2CLK_STR", 24, 27, &umr_bitfield_default },
	 { "DC_GPIO_DDC2DATA_STR", 28, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_GPIO_DDC2_A[] = {
	 { "DC_GPIO_DDC2CLK_A", 0, 0, &umr_bitfield_default },
	 { "DC_GPIO_DDC2DATA_A", 8, 8, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_GPIO_DDC2_EN[] = {
	 { "DC_GPIO_DDC2CLK_EN", 0, 0, &umr_bitfield_default },
	 { "DC_GPIO_DDC2DATA_EN", 8, 8, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_GPIO_DDC2_Y[] = {
	 { "DC_GPIO_DDC2CLK_Y", 0, 0, &umr_bitfield_default },
	 { "DC_GPIO_DDC2DATA_Y", 8, 8, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_GPIO_DDC3_MASK[] = {
	 { "DC_GPIO_DDC3CLK_MASK", 0, 0, &umr_bitfield_default },
	 { "DC_GPIO_DDC3CLK_PD_EN", 4, 4, &umr_bitfield_default },
	 { "DC_GPIO_DDC3CLK_RECV", 6, 6, &umr_bitfield_default },
	 { "DC_GPIO_DDC3DATA_MASK", 8, 8, &umr_bitfield_default },
	 { "DC_GPIO_DDC3DATA_PD_EN", 12, 12, &umr_bitfield_default },
	 { "DC_GPIO_DDC3DATA_RECV", 14, 14, &umr_bitfield_default },
	 { "AUX_PAD3_MODE", 16, 16, &umr_bitfield_default },
	 { "AUX3_POL", 20, 20, &umr_bitfield_default },
	 { "ALLOW_HW_DDC3_PD_EN", 22, 22, &umr_bitfield_default },
	 { "DC_GPIO_DDC3CLK_STR", 24, 27, &umr_bitfield_default },
	 { "DC_GPIO_DDC3DATA_STR", 28, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_GPIO_DDC3_A[] = {
	 { "DC_GPIO_DDC3CLK_A", 0, 0, &umr_bitfield_default },
	 { "DC_GPIO_DDC3DATA_A", 8, 8, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_GPIO_DDC3_EN[] = {
	 { "DC_GPIO_DDC3CLK_EN", 0, 0, &umr_bitfield_default },
	 { "DC_GPIO_DDC3DATA_EN", 8, 8, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_GPIO_DDC3_Y[] = {
	 { "DC_GPIO_DDC3CLK_Y", 0, 0, &umr_bitfield_default },
	 { "DC_GPIO_DDC3DATA_Y", 8, 8, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_GPIO_DDC4_MASK[] = {
	 { "DC_GPIO_DDC4CLK_MASK", 0, 0, &umr_bitfield_default },
	 { "DC_GPIO_DDC4CLK_PD_EN", 4, 4, &umr_bitfield_default },
	 { "DC_GPIO_DDC4CLK_RECV", 6, 6, &umr_bitfield_default },
	 { "DC_GPIO_DDC4DATA_MASK", 8, 8, &umr_bitfield_default },
	 { "DC_GPIO_DDC4DATA_PD_EN", 12, 12, &umr_bitfield_default },
	 { "DC_GPIO_DDC4DATA_RECV", 14, 14, &umr_bitfield_default },
	 { "AUX_PAD4_MODE", 16, 16, &umr_bitfield_default },
	 { "AUX4_POL", 20, 20, &umr_bitfield_default },
	 { "ALLOW_HW_DDC4_PD_EN", 22, 22, &umr_bitfield_default },
	 { "DC_GPIO_DDC4CLK_STR", 24, 27, &umr_bitfield_default },
	 { "DC_GPIO_DDC4DATA_STR", 28, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_GPIO_DDC4_A[] = {
	 { "DC_GPIO_DDC4CLK_A", 0, 0, &umr_bitfield_default },
	 { "DC_GPIO_DDC4DATA_A", 8, 8, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_GPIO_DDC4_EN[] = {
	 { "DC_GPIO_DDC4CLK_EN", 0, 0, &umr_bitfield_default },
	 { "DC_GPIO_DDC4DATA_EN", 8, 8, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_GPIO_DDC4_Y[] = {
	 { "DC_GPIO_DDC4CLK_Y", 0, 0, &umr_bitfield_default },
	 { "DC_GPIO_DDC4DATA_Y", 8, 8, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_GPIO_DDC5_MASK[] = {
	 { "DC_GPIO_DDC5CLK_MASK", 0, 0, &umr_bitfield_default },
	 { "DC_GPIO_DDC5CLK_PD_EN", 4, 4, &umr_bitfield_default },
	 { "DC_GPIO_DDC5CLK_RECV", 6, 6, &umr_bitfield_default },
	 { "DC_GPIO_DDC5DATA_MASK", 8, 8, &umr_bitfield_default },
	 { "DC_GPIO_DDC5DATA_PD_EN", 12, 12, &umr_bitfield_default },
	 { "DC_GPIO_DDC5DATA_RECV", 14, 14, &umr_bitfield_default },
	 { "AUX_PAD5_MODE", 16, 16, &umr_bitfield_default },
	 { "AUX5_POL", 20, 20, &umr_bitfield_default },
	 { "ALLOW_HW_DDC5_PD_EN", 22, 22, &umr_bitfield_default },
	 { "DC_GPIO_DDC5CLK_STR", 24, 27, &umr_bitfield_default },
	 { "DC_GPIO_DDC5DATA_STR", 28, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_GPIO_DDC5_A[] = {
	 { "DC_GPIO_DDC5CLK_A", 0, 0, &umr_bitfield_default },
	 { "DC_GPIO_DDC5DATA_A", 8, 8, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_GPIO_DDC5_EN[] = {
	 { "DC_GPIO_DDC5CLK_EN", 0, 0, &umr_bitfield_default },
	 { "DC_GPIO_DDC5DATA_EN", 8, 8, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_GPIO_DDC5_Y[] = {
	 { "DC_GPIO_DDC5CLK_Y", 0, 0, &umr_bitfield_default },
	 { "DC_GPIO_DDC5DATA_Y", 8, 8, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_GPIO_DDC6_MASK[] = {
	 { "DC_GPIO_DDC6CLK_MASK", 0, 0, &umr_bitfield_default },
	 { "DC_GPIO_DDC6CLK_PD_EN", 4, 4, &umr_bitfield_default },
	 { "DC_GPIO_DDC6CLK_RECV", 6, 6, &umr_bitfield_default },
	 { "DC_GPIO_DDC6DATA_MASK", 8, 8, &umr_bitfield_default },
	 { "DC_GPIO_DDC6DATA_PD_EN", 12, 12, &umr_bitfield_default },
	 { "DC_GPIO_DDC6DATA_RECV", 14, 14, &umr_bitfield_default },
	 { "AUX_PAD6_MODE", 16, 16, &umr_bitfield_default },
	 { "AUX6_POL", 20, 20, &umr_bitfield_default },
	 { "ALLOW_HW_DDC6_PD_EN", 22, 22, &umr_bitfield_default },
	 { "DC_GPIO_DDC6CLK_STR", 24, 27, &umr_bitfield_default },
	 { "DC_GPIO_DDC6DATA_STR", 28, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_GPIO_DDC6_A[] = {
	 { "DC_GPIO_DDC6CLK_A", 0, 0, &umr_bitfield_default },
	 { "DC_GPIO_DDC6DATA_A", 8, 8, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_GPIO_DDC6_EN[] = {
	 { "DC_GPIO_DDC6CLK_EN", 0, 0, &umr_bitfield_default },
	 { "DC_GPIO_DDC6DATA_EN", 8, 8, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_GPIO_DDC6_Y[] = {
	 { "DC_GPIO_DDC6CLK_Y", 0, 0, &umr_bitfield_default },
	 { "DC_GPIO_DDC6DATA_Y", 8, 8, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_GPIO_DDCVGA_MASK[] = {
	 { "DC_GPIO_DDCVGACLK_MASK", 0, 0, &umr_bitfield_default },
	 { "DC_GPIO_DDCVGACLK_RECV", 6, 6, &umr_bitfield_default },
	 { "DC_GPIO_DDCVGADATA_MASK", 8, 8, &umr_bitfield_default },
	 { "DC_GPIO_DDCVGADATA_PD_EN", 12, 12, &umr_bitfield_default },
	 { "DC_GPIO_DDCVGADATA_RECV", 14, 14, &umr_bitfield_default },
	 { "AUX_PADVGA_MODE", 16, 16, &umr_bitfield_default },
	 { "AUXVGA_POL", 20, 20, &umr_bitfield_default },
	 { "ALLOW_HW_DDCVGA_PD_EN", 22, 22, &umr_bitfield_default },
	 { "DC_GPIO_DDCVGACLK_STR", 24, 27, &umr_bitfield_default },
	 { "DC_GPIO_DDCVGADATA_STR", 28, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_GPIO_DDCVGA_A[] = {
	 { "DC_GPIO_DDCVGACLK_A", 0, 0, &umr_bitfield_default },
	 { "DC_GPIO_DDCVGADATA_A", 8, 8, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_GPIO_DDCVGA_EN[] = {
	 { "DC_GPIO_DDCVGACLK_EN", 0, 0, &umr_bitfield_default },
	 { "DC_GPIO_DDCVGADATA_EN", 8, 8, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_GPIO_DDCVGA_Y[] = {
	 { "DC_GPIO_DDCVGACLK_Y", 0, 0, &umr_bitfield_default },
	 { "DC_GPIO_DDCVGADATA_Y", 8, 8, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_GPIO_SYNCA_MASK[] = {
	 { "DC_GPIO_HSYNCA_MASK", 0, 0, &umr_bitfield_default },
	 { "DC_GPIO_HSYNCA_PD_DIS", 4, 4, &umr_bitfield_default },
	 { "DC_GPIO_HSYNCA_RECV", 6, 7, &umr_bitfield_default },
	 { "DC_GPIO_VSYNCA_MASK", 8, 8, &umr_bitfield_default },
	 { "DC_GPIO_VSYNCA_PD_DIS", 12, 12, &umr_bitfield_default },
	 { "DC_GPIO_VSYNCA_RECV", 14, 15, &umr_bitfield_default },
	 { "DC_GPIO_HSYNCA_OPTC_HSYNC_MASK", 24, 26, &umr_bitfield_default },
	 { "DC_GPIO_VSYNCA_OPTC_VSYNC_MASK", 28, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_GPIO_SYNCA_A[] = {
	 { "DC_GPIO_HSYNCA_A", 0, 0, &umr_bitfield_default },
	 { "DC_GPIO_VSYNCA_A", 8, 8, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_GPIO_SYNCA_EN[] = {
	 { "DC_GPIO_HSYNCA_EN", 0, 0, &umr_bitfield_default },
	 { "DC_GPIO_VSYNCA_EN", 8, 8, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_GPIO_SYNCA_Y[] = {
	 { "DC_GPIO_HSYNCA_Y", 0, 0, &umr_bitfield_default },
	 { "DC_GPIO_VSYNCA_Y", 8, 8, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_GPIO_GENLK_MASK[] = {
	 { "DC_GPIO_GENLK_CLK_MASK", 0, 0, &umr_bitfield_default },
	 { "DC_GPIO_GENLK_CLK_PD_DIS", 1, 1, &umr_bitfield_default },
	 { "DC_GPIO_GENLK_CLK_PU_EN", 3, 3, &umr_bitfield_default },
	 { "DC_GPIO_GENLK_CLK_RECV", 4, 5, &umr_bitfield_default },
	 { "DC_GPIO_GENLK_VSYNC_MASK", 8, 8, &umr_bitfield_default },
	 { "DC_GPIO_GENLK_VSYNC_PD_DIS", 9, 9, &umr_bitfield_default },
	 { "DC_GPIO_GENLK_VSYNC_PU_EN", 11, 11, &umr_bitfield_default },
	 { "DC_GPIO_GENLK_VSYNC_RECV", 12, 13, &umr_bitfield_default },
	 { "DC_GPIO_SWAPLOCK_A_MASK", 16, 16, &umr_bitfield_default },
	 { "DC_GPIO_SWAPLOCK_A_PD_DIS", 17, 17, &umr_bitfield_default },
	 { "DC_GPIO_SWAPLOCK_A_PU_EN", 19, 19, &umr_bitfield_default },
	 { "DC_GPIO_SWAPLOCK_A_RECV", 20, 21, &umr_bitfield_default },
	 { "DC_GPIO_SWAPLOCK_B_MASK", 24, 24, &umr_bitfield_default },
	 { "DC_GPIO_SWAPLOCK_B_PD_DIS", 25, 25, &umr_bitfield_default },
	 { "DC_GPIO_SWAPLOCK_B_PU_EN", 27, 27, &umr_bitfield_default },
	 { "DC_GPIO_SWAPLOCK_B_RECV", 28, 29, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_GPIO_GENLK_A[] = {
	 { "DC_GPIO_GENLK_CLK_A", 0, 0, &umr_bitfield_default },
	 { "DC_GPIO_GENLK_VSYNC_A", 8, 8, &umr_bitfield_default },
	 { "DC_GPIO_SWAPLOCK_A_A", 16, 16, &umr_bitfield_default },
	 { "DC_GPIO_SWAPLOCK_B_A", 24, 24, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_GPIO_GENLK_EN[] = {
	 { "DC_GPIO_GENLK_CLK_EN", 0, 0, &umr_bitfield_default },
	 { "DC_GPIO_GENLK_VSYNC_EN", 8, 8, &umr_bitfield_default },
	 { "DC_GPIO_SWAPLOCK_A_EN", 16, 16, &umr_bitfield_default },
	 { "DC_GPIO_SWAPLOCK_B_EN", 24, 24, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_GPIO_GENLK_Y[] = {
	 { "DC_GPIO_GENLK_CLK_Y", 0, 0, &umr_bitfield_default },
	 { "DC_GPIO_GENLK_VSYNC_Y", 8, 8, &umr_bitfield_default },
	 { "DC_GPIO_SWAPLOCK_A_Y", 16, 16, &umr_bitfield_default },
	 { "DC_GPIO_SWAPLOCK_B_Y", 24, 24, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_GPIO_HPD_MASK[] = {
	 { "DC_GPIO_HPD1_MASK", 0, 0, &umr_bitfield_default },
	 { "DC_GPIO_RX_HPD_MASK", 1, 1, &umr_bitfield_default },
	 { "DC_GPIO_RX_HPD_PD_DIS", 2, 2, &umr_bitfield_default },
	 { "DC_GPIO_RX_HPD_RX_SEL", 3, 3, &umr_bitfield_default },
	 { "DC_GPIO_HPD1_PD_DIS", 4, 4, &umr_bitfield_default },
	 { "DC_GPIO_HPD1_RECV", 6, 7, &umr_bitfield_default },
	 { "DC_GPIO_HPD2_MASK", 8, 8, &umr_bitfield_default },
	 { "DC_GPIO_HPD2_PD_DIS", 9, 9, &umr_bitfield_default },
	 { "DC_GPIO_HPD2_RECV", 10, 11, &umr_bitfield_default },
	 { "DC_GPIO_HPD3_MASK", 16, 16, &umr_bitfield_default },
	 { "DC_GPIO_HPD3_PD_DIS", 17, 17, &umr_bitfield_default },
	 { "DC_GPIO_HPD3_RECV", 18, 19, &umr_bitfield_default },
	 { "DC_GPIO_HPD4_MASK", 20, 20, &umr_bitfield_default },
	 { "DC_GPIO_HPD4_PD_DIS", 21, 21, &umr_bitfield_default },
	 { "DC_GPIO_HPD4_RECV", 22, 23, &umr_bitfield_default },
	 { "DC_GPIO_HPD5_MASK", 24, 24, &umr_bitfield_default },
	 { "DC_GPIO_HPD5_PD_DIS", 25, 25, &umr_bitfield_default },
	 { "DC_GPIO_HPD5_RECV", 26, 27, &umr_bitfield_default },
	 { "DC_GPIO_HPD6_MASK", 28, 28, &umr_bitfield_default },
	 { "DC_GPIO_HPD6_PD_DIS", 29, 29, &umr_bitfield_default },
	 { "DC_GPIO_HPD6_RECV", 30, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_GPIO_HPD_A[] = {
	 { "DC_GPIO_HPD1_A", 0, 0, &umr_bitfield_default },
	 { "DC_GPIO_HPD2_A", 8, 8, &umr_bitfield_default },
	 { "DC_GPIO_HPD3_A", 16, 16, &umr_bitfield_default },
	 { "DC_GPIO_HPD4_A", 24, 24, &umr_bitfield_default },
	 { "DC_GPIO_HPD5_A", 26, 26, &umr_bitfield_default },
	 { "DC_GPIO_HPD6_A", 28, 28, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_GPIO_HPD_EN[] = {
	 { "DC_GPIO_HPD1_EN", 0, 0, &umr_bitfield_default },
	 { "HPD1_SCHMEN_PI", 1, 1, &umr_bitfield_default },
	 { "HPD1_SLEWNCORE", 2, 2, &umr_bitfield_default },
	 { "RX_HPD_SCHMEN_PI", 3, 3, &umr_bitfield_default },
	 { "RX_HPD_SLEWNCORE", 4, 4, &umr_bitfield_default },
	 { "HPD12_SPARE0", 5, 5, &umr_bitfield_default },
	 { "HPD1_SEL0", 6, 6, &umr_bitfield_default },
	 { "RX_HPD_SEL0", 7, 7, &umr_bitfield_default },
	 { "DC_GPIO_HPD2_EN", 8, 8, &umr_bitfield_default },
	 { "HPD2_SCHMEN_PI", 9, 9, &umr_bitfield_default },
	 { "HPD12_SPARE1", 10, 10, &umr_bitfield_default },
	 { "DC_GPIO_HPD3_EN", 16, 16, &umr_bitfield_default },
	 { "HPD3_SCHMEN_PI", 17, 17, &umr_bitfield_default },
	 { "HPD34_SPARE0", 18, 18, &umr_bitfield_default },
	 { "DC_GPIO_HPD4_EN", 20, 20, &umr_bitfield_default },
	 { "HPD4_SCHMEN_PI", 21, 21, &umr_bitfield_default },
	 { "HPD34_SPARE1", 22, 22, &umr_bitfield_default },
	 { "DC_GPIO_HPD5_EN", 24, 24, &umr_bitfield_default },
	 { "HPD5_SCHMEN_PI", 25, 25, &umr_bitfield_default },
	 { "HPD56_SPARE0", 26, 26, &umr_bitfield_default },
	 { "DC_GPIO_HPD6_EN", 28, 28, &umr_bitfield_default },
	 { "HPD6_SCHMEN_PI", 29, 29, &umr_bitfield_default },
	 { "HPD56_SPARE1", 30, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_GPIO_HPD_Y[] = {
	 { "DC_GPIO_HPD1_Y", 0, 0, &umr_bitfield_default },
	 { "DC_GPIO_HPD2_Y", 8, 8, &umr_bitfield_default },
	 { "DC_GPIO_HPD3_Y", 16, 16, &umr_bitfield_default },
	 { "DC_GPIO_HPD4_Y", 24, 24, &umr_bitfield_default },
	 { "DC_GPIO_HPD5_Y", 26, 26, &umr_bitfield_default },
	 { "DC_GPIO_HPD6_Y", 28, 28, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_GPIO_PWRSEQ_MASK[] = {
	 { "DC_GPIO_BLON_MASK", 0, 0, &umr_bitfield_default },
	 { "DC_GPIO_BLON_PD_DIS", 4, 4, &umr_bitfield_default },
	 { "DC_GPIO_BLON_RECV", 6, 7, &umr_bitfield_default },
	 { "DC_GPIO_DIGON_MASK", 8, 8, &umr_bitfield_default },
	 { "DC_GPIO_DIGON_PD_DIS", 12, 12, &umr_bitfield_default },
	 { "DC_GPIO_DIGON_RECV", 14, 15, &umr_bitfield_default },
	 { "DC_GPIO_ENA_BL_MASK", 16, 16, &umr_bitfield_default },
	 { "DC_GPIO_ENA_BL_PD_DIS", 20, 20, &umr_bitfield_default },
	 { "DC_GPIO_ENA_BL_RECV", 22, 23, &umr_bitfield_default },
	 { "DC_GPIO_VSYNC_IN_MASK", 24, 24, &umr_bitfield_default },
	 { "DC_GPIO_VSYNC_IN_PD_DIS", 25, 25, &umr_bitfield_default },
	 { "DC_GPIO_VSYNC_IN_RECV", 26, 26, &umr_bitfield_default },
	 { "DC_GPIO_HSYNC_IN_MASK", 28, 28, &umr_bitfield_default },
	 { "DC_GPIO_HSYNC_IN_PD_DIS", 29, 29, &umr_bitfield_default },
	 { "DC_GPIO_HSYNC_IN_RECV", 30, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_GPIO_PWRSEQ_A[] = {
	 { "DC_GPIO_BLON_A", 0, 0, &umr_bitfield_default },
	 { "DC_GPIO_DIGON_A", 8, 8, &umr_bitfield_default },
	 { "DC_GPIO_ENA_BL_A", 16, 16, &umr_bitfield_default },
	 { "DC_GPIO_VSYNC_IN_A", 24, 24, &umr_bitfield_default },
	 { "DC_GPIO_HSYNC_IN_A", 31, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_GPIO_PWRSEQ_EN[] = {
	 { "DC_GPIO_BLON_EN", 0, 0, &umr_bitfield_default },
	 { "DC_GPIO_VARY_BL_GENERICA_EN", 1, 1, &umr_bitfield_default },
	 { "DC_GPIO_DIGON_EN", 8, 8, &umr_bitfield_default },
	 { "DC_GPIO_ENA_BL_EN", 16, 16, &umr_bitfield_default },
	 { "DC_GPIO_VSYNC_IN_EN", 24, 24, &umr_bitfield_default },
	 { "DC_GPIO_HSYNC_IN_EN", 31, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_GPIO_PWRSEQ_Y[] = {
	 { "DC_GPIO_BLON_Y", 0, 0, &umr_bitfield_default },
	 { "DC_GPIO_DIGON_Y", 8, 8, &umr_bitfield_default },
	 { "DC_GPIO_ENA_BL_Y", 16, 16, &umr_bitfield_default },
	 { "DC_GPIO_VSYNC_IN", 24, 24, &umr_bitfield_default },
	 { "DC_GPIO_HSYNC_IN", 31, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_GPIO_PAD_STRENGTH_1[] = {
	 { "GENLK_STRENGTH_SN", 0, 3, &umr_bitfield_default },
	 { "GENLK_STRENGTH_SP", 4, 7, &umr_bitfield_default },
	 { "RX_HPD_STRENGTH_SN", 8, 11, &umr_bitfield_default },
	 { "RX_HPD_STRENGTH_SP", 12, 15, &umr_bitfield_default },
	 { "TX_HPD_STRENGTH_SN", 16, 19, &umr_bitfield_default },
	 { "TX_HPD_STRENGTH_SP", 20, 23, &umr_bitfield_default },
	 { "SYNC_STRENGTH_SN", 24, 27, &umr_bitfield_default },
	 { "SYNC_STRENGTH_SP", 28, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_GPIO_PAD_STRENGTH_2[] = {
	 { "STRENGTH_SN", 0, 3, &umr_bitfield_default },
	 { "STRENGTH_SP", 4, 7, &umr_bitfield_default },
	 { "EXT_RESET_DRVSTRENGTH", 8, 10, &umr_bitfield_default },
	 { "REF_27_DRVSTRENGTH", 12, 14, &umr_bitfield_default },
	 { "PWRSEQ_STRENGTH_SN", 16, 19, &umr_bitfield_default },
	 { "PWRSEQ_STRENGTH_SP", 20, 23, &umr_bitfield_default },
	 { "REF_27_SRC_SEL", 30, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmPHY_AUX_CNTL[] = {
	 { "AUXSLAVE_PAD_SLEWN", 0, 0, &umr_bitfield_default },
	 { "AUXSLAVE_PAD_WAKE", 1, 1, &umr_bitfield_default },
	 { "AUXSLAVE_PAD_RXSEL", 2, 2, &umr_bitfield_default },
	 { "AUXSLAVE_PAD_MODE", 3, 3, &umr_bitfield_default },
	 { "DDCSLAVE_DATA_PD_EN", 4, 4, &umr_bitfield_default },
	 { "DDCSLAVE_DATA_EN", 5, 5, &umr_bitfield_default },
	 { "DDCSLAVE_CLK_PD_EN", 6, 6, &umr_bitfield_default },
	 { "DDCSLAVE_CLK_EN", 7, 7, &umr_bitfield_default },
	 { "AUX_PAD_SLEWN", 12, 12, &umr_bitfield_default },
	 { "AUXSLAVE_CLK_PD_EN", 13, 13, &umr_bitfield_default },
	 { "AUX_PAD_WAKE", 14, 14, &umr_bitfield_default },
	 { "AUX_PAD_RXSEL", 16, 17, &umr_bitfield_default },
	 { "AUX_CAL_BIASENTST", 20, 22, &umr_bitfield_default },
	 { "AUX_CAL_RESBIASEN", 23, 23, &umr_bitfield_default },
	 { "AUX_CAL_SPARE", 24, 25, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_GPIO_I2CPAD_MASK[] = {
	 { "DC_GPIO_SCL_MASK", 0, 0, &umr_bitfield_default },
	 { "DC_GPIO_SCL_PD_DIS", 1, 1, &umr_bitfield_default },
	 { "DC_GPIO_SCL_RECV", 2, 2, &umr_bitfield_default },
	 { "DC_GPIO_SDA_MASK", 4, 4, &umr_bitfield_default },
	 { "DC_GPIO_SDA_PD_DIS", 5, 5, &umr_bitfield_default },
	 { "DC_GPIO_SDA_RECV", 6, 6, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_GPIO_I2CPAD_A[] = {
	 { "DC_GPIO_SCL_A", 0, 0, &umr_bitfield_default },
	 { "DC_GPIO_SDA_A", 1, 1, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_GPIO_I2CPAD_EN[] = {
	 { "DC_GPIO_SCL_EN", 0, 0, &umr_bitfield_default },
	 { "DC_GPIO_SDA_EN", 1, 1, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_GPIO_I2CPAD_Y[] = {
	 { "DC_GPIO_SCL_Y", 0, 0, &umr_bitfield_default },
	 { "DC_GPIO_SDA_Y", 1, 1, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_GPIO_I2CPAD_STRENGTH[] = {
	 { "I2C_STRENGTH_SN", 0, 3, &umr_bitfield_default },
	 { "I2C_STRENGTH_SP", 4, 7, &umr_bitfield_default },
};
static struct umr_bitfield mmDVO_STRENGTH_CONTROL[] = {
	 { "DVO_SP", 0, 3, &umr_bitfield_default },
	 { "DVO_SN", 4, 7, &umr_bitfield_default },
	 { "DVOCLK_SP", 8, 11, &umr_bitfield_default },
	 { "DVOCLK_SN", 12, 15, &umr_bitfield_default },
	 { "DVO_DRVSTRENGTH", 16, 18, &umr_bitfield_default },
	 { "DVOCLK_DRVSTRENGTH", 20, 22, &umr_bitfield_default },
	 { "FLDO_VITNE_DRVSTRENGTH", 24, 26, &umr_bitfield_default },
	 { "DVO_LSB_VMODE", 28, 28, &umr_bitfield_default },
	 { "DVO_MSB_VMODE", 29, 29, &umr_bitfield_default },
};
static struct umr_bitfield mmDVO_VREF_CONTROL[] = {
	 { "DVO_VREFPON", 0, 0, &umr_bitfield_default },
	 { "DVO_VREFSEL", 1, 1, &umr_bitfield_default },
	 { "DVO_VREFCAL", 4, 7, &umr_bitfield_default },
};
static struct umr_bitfield mmDVO_SKEW_ADJUST[] = {
	 { "DVO_SKEW_ADJUST", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_GPIO_I2S_SPDIF_MASK[] = {
	 { "DC_GPIO_I2SDATA0_MASK", 0, 3, &umr_bitfield_default },
	 { "DC_GPIO_MCLK0_MASK", 4, 4, &umr_bitfield_default },
	 { "DC_GPIO_BCLK0_MASK", 5, 5, &umr_bitfield_default },
	 { "DC_GPIO_LRCK0_MASK", 6, 6, &umr_bitfield_default },
	 { "DC_GPIO_SPDIF0_MASK", 7, 7, &umr_bitfield_default },
	 { "DC_GPIO_I2SDATA1_MASK", 8, 8, &umr_bitfield_default },
	 { "DC_GPIO_MCLK1_MASK", 9, 9, &umr_bitfield_default },
	 { "DC_GPIO_BCLK1_MASK", 10, 10, &umr_bitfield_default },
	 { "DC_GPIO_LRCK1_MASK", 11, 11, &umr_bitfield_default },
	 { "DC_GPIO_SPDIF1_MASK", 12, 12, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_GPIO_I2S_SPDIF_A[] = {
	 { "DC_GPIO_I2SDATA0_A", 0, 3, &umr_bitfield_default },
	 { "DC_GPIO_MCLK0_A", 4, 4, &umr_bitfield_default },
	 { "DC_GPIO_BCLK0_A", 5, 5, &umr_bitfield_default },
	 { "DC_GPIO_LRCK0_A", 6, 6, &umr_bitfield_default },
	 { "DC_GPIO_SPDIF0_A", 7, 7, &umr_bitfield_default },
	 { "DC_GPIO_I2SDATA1_A", 8, 8, &umr_bitfield_default },
	 { "DC_GPIO_MCLK1_A", 9, 9, &umr_bitfield_default },
	 { "DC_GPIO_BCLK1_A", 10, 10, &umr_bitfield_default },
	 { "DC_GPIO_LRCK1_A", 11, 11, &umr_bitfield_default },
	 { "DC_GPIO_SPDIF1_A", 12, 12, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_GPIO_I2S_SPDIF_EN[] = {
	 { "DC_GPIO_I2SDATA0_EN", 0, 3, &umr_bitfield_default },
	 { "DC_GPIO_MCLK0_EN", 4, 4, &umr_bitfield_default },
	 { "DC_GPIO_BCLK0_EN", 5, 5, &umr_bitfield_default },
	 { "DC_GPIO_LRCK0_EN", 6, 6, &umr_bitfield_default },
	 { "DC_GPIO_SPDIF0_EN", 7, 7, &umr_bitfield_default },
	 { "DC_GPIO_I2SDATA1_EN", 8, 8, &umr_bitfield_default },
	 { "DC_GPIO_MCLK1_EN", 9, 9, &umr_bitfield_default },
	 { "DC_GPIO_BCLK1_EN", 10, 10, &umr_bitfield_default },
	 { "DC_GPIO_LRCK1_EN", 11, 11, &umr_bitfield_default },
	 { "DC_GPIO_SPDIF1_EN", 12, 12, &umr_bitfield_default },
	 { "SPDIF1_APORT", 13, 13, &umr_bitfield_default },
	 { "SPDIF1_PU", 14, 14, &umr_bitfield_default },
	 { "SPDIF1_RXSEL", 15, 15, &umr_bitfield_default },
	 { "SPDIF1_SCHMEN", 16, 16, &umr_bitfield_default },
	 { "SPDIF1_SMODE_EN", 17, 17, &umr_bitfield_default },
	 { "SPDIF1_IMODE", 18, 18, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_GPIO_I2S_SPDIF_Y[] = {
	 { "DC_GPIO_I2SDATA0_Y", 0, 3, &umr_bitfield_default },
	 { "DC_GPIO_MCLK0_Y", 4, 4, &umr_bitfield_default },
	 { "DC_GPIO_BCLK0_Y", 5, 5, &umr_bitfield_default },
	 { "DC_GPIO_LRCK0_Y", 6, 6, &umr_bitfield_default },
	 { "DC_GPIO_SPDIF0_Y", 7, 7, &umr_bitfield_default },
	 { "DC_GPIO_I2SDATA1_Y", 8, 8, &umr_bitfield_default },
	 { "DC_GPIO_MCLK1_Y", 9, 9, &umr_bitfield_default },
	 { "DC_GPIO_BCLK1_Y", 10, 10, &umr_bitfield_default },
	 { "DC_GPIO_LRCK1_Y", 11, 11, &umr_bitfield_default },
	 { "DC_GPIO_SPDIF1_Y", 12, 12, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_GPIO_I2S_SPDIF_STRENGTH[] = {
	 { "I2S0_DRVSTRENGTH", 0, 2, &umr_bitfield_default },
	 { "SPDIF0_DRVSTRENGTH_SN", 8, 10, &umr_bitfield_default },
	 { "SPDIF0_DRVSTRENGTH_SP", 11, 13, &umr_bitfield_default },
	 { "I2S1_DRVSTRENGTH", 16, 18, &umr_bitfield_default },
	 { "SPDIF1_DRVSTRENGTH_SN", 24, 26, &umr_bitfield_default },
	 { "SPDIF1_DRVSTRENGTH_SP", 27, 29, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_GPIO_TX12_EN[] = {
	 { "DC_GPIO_BLON_TX12_EN", 0, 0, &umr_bitfield_default },
	 { "DC_GPIO_DIGON_TX12_EN", 1, 1, &umr_bitfield_default },
	 { "DC_GPIO_ENA_BL_TX12_EN", 2, 2, &umr_bitfield_default },
	 { "DC_GPIO_GENERICA_TX12_EN", 3, 3, &umr_bitfield_default },
	 { "DC_GPIO_GENERICB_TX12_EN", 4, 4, &umr_bitfield_default },
	 { "DC_GPIO_GENERICC_TX12_EN", 5, 5, &umr_bitfield_default },
	 { "DC_GPIO_GENERICD_TX12_EN", 6, 6, &umr_bitfield_default },
	 { "DC_GPIO_GENERICE_TX12_EN", 7, 7, &umr_bitfield_default },
	 { "DC_GPIO_GENERICF_TX12_EN", 8, 8, &umr_bitfield_default },
	 { "DC_GPIO_GENERICG_TX12_EN", 9, 9, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_GPIO_AUX_CTRL_0[] = {
	 { "DC_GPIO_AUX1_FALLSLEWSEL", 0, 1, &umr_bitfield_default },
	 { "DC_GPIO_AUX2_FALLSLEWSEL", 2, 3, &umr_bitfield_default },
	 { "DC_GPIO_AUX3_FALLSLEWSEL", 4, 5, &umr_bitfield_default },
	 { "DC_GPIO_AUX4_FALLSLEWSEL", 6, 7, &umr_bitfield_default },
	 { "DC_GPIO_AUX5_FALLSLEWSEL", 8, 9, &umr_bitfield_default },
	 { "DC_GPIO_AUX6_FALLSLEWSEL", 10, 11, &umr_bitfield_default },
	 { "DC_GPIO_DDCVGA_FALLSLEWSEL", 12, 13, &umr_bitfield_default },
	 { "DC_GPIO_GENI2C_FALLSLEWSEL", 14, 15, &umr_bitfield_default },
	 { "DC_GPIO_AUX1_SPIKERCEN", 16, 16, &umr_bitfield_default },
	 { "DC_GPIO_AUX2_SPIKERCEN", 17, 17, &umr_bitfield_default },
	 { "DC_GPIO_AUX3_SPIKERCEN", 18, 18, &umr_bitfield_default },
	 { "DC_GPIO_AUX4_SPIKERCEN", 19, 19, &umr_bitfield_default },
	 { "DC_GPIO_AUX5_SPIKERCEN", 20, 20, &umr_bitfield_default },
	 { "DC_GPIO_AUX6_SPIKERCEN", 21, 21, &umr_bitfield_default },
	 { "DC_GPIO_DDCVGA_SPIKERCEN", 22, 22, &umr_bitfield_default },
	 { "DC_GPIO_GENI2C_SPIKERCEN", 23, 23, &umr_bitfield_default },
	 { "DC_GPIO_AUX1_SPIKERCSEL", 24, 24, &umr_bitfield_default },
	 { "DC_GPIO_AUX2_SPIKERCSEL", 25, 25, &umr_bitfield_default },
	 { "DC_GPIO_AUX3_SPIKERCSEL", 26, 26, &umr_bitfield_default },
	 { "DC_GPIO_AUX4_SPIKERCSEL", 27, 27, &umr_bitfield_default },
	 { "DC_GPIO_AUX5_SPIKERCSEL", 28, 28, &umr_bitfield_default },
	 { "DC_GPIO_AUX6_SPIKERCSEL", 29, 29, &umr_bitfield_default },
	 { "DC_GPIO_DDCVGA_SPIKERCSEL", 30, 30, &umr_bitfield_default },
	 { "DC_GPIO_GENI2C_SPIKERCSEL", 31, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_GPIO_AUX_CTRL_1[] = {
	 { "DC_GPIO_AUX_CSEL_0P9", 0, 0, &umr_bitfield_default },
	 { "DC_GPIO_AUX_CSEL_1P1", 1, 1, &umr_bitfield_default },
	 { "DC_GPIO_AUX_RSEL_0P9", 2, 2, &umr_bitfield_default },
	 { "DC_GPIO_AUX_RSEL_1P1", 3, 3, &umr_bitfield_default },
	 { "DC_GPIO_I2C_CSEL_0P9", 4, 4, &umr_bitfield_default },
	 { "DC_GPIO_I2C_CSEL_1P1", 5, 5, &umr_bitfield_default },
	 { "DC_GPIO_I2C_RSEL_0P9", 6, 6, &umr_bitfield_default },
	 { "DC_GPIO_I2C_RSEL_1P1", 7, 7, &umr_bitfield_default },
	 { "DC_GPIO_AUX_BIASCRTEN", 8, 8, &umr_bitfield_default },
	 { "DC_GPIO_I2C_BIASCRTEN", 9, 9, &umr_bitfield_default },
	 { "DC_GPIO_AUX_RESBIASEN", 10, 10, &umr_bitfield_default },
	 { "DC_GPIO_I2C_RESBIASEN", 11, 11, &umr_bitfield_default },
	 { "DC_GPIO_AUX1_COMPSEL", 12, 12, &umr_bitfield_default },
	 { "DC_GPIO_GENI2C_COMPSEL", 13, 13, &umr_bitfield_default },
	 { "DC_GPIO_DDCVGA_SPARE", 14, 15, &umr_bitfield_default },
	 { "DC_GPIO_GENI2C_SPARE", 16, 17, &umr_bitfield_default },
	 { "DC_GPIO_DDCVGA_SLEWN", 18, 18, &umr_bitfield_default },
	 { "DC_GPIO_GENI2C_SLEWN", 19, 19, &umr_bitfield_default },
	 { "DC_GPIO_DDCVGA_RXSEL", 20, 21, &umr_bitfield_default },
	 { "DC_GPIO_GENI2C_RXSEL", 22, 23, &umr_bitfield_default },
	 { "DC_GPIO_GENI2C_PDEN", 24, 24, &umr_bitfield_default },
	 { "DC_GPIO_AUX2_COMPSEL", 25, 25, &umr_bitfield_default },
	 { "DC_GPIO_AUX3_COMPSEL", 26, 26, &umr_bitfield_default },
	 { "DC_GPIO_AUX4_COMPSEL", 27, 27, &umr_bitfield_default },
	 { "DC_GPIO_AUX5_COMPSEL", 28, 28, &umr_bitfield_default },
	 { "DC_GPIO_AUX6_COMPSEL", 29, 29, &umr_bitfield_default },
	 { "DC_GPIO_DDCVGA_COMPSEL", 30, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_GPIO_AUX_CTRL_2[] = {
	 { "DC_GPIO_HPD12_FALLSLEWSEL", 0, 1, &umr_bitfield_default },
	 { "DC_GPIO_HPD34_FALLSLEWSEL", 2, 3, &umr_bitfield_default },
	 { "DC_GPIO_HPD56_FALLSLEWSEL", 4, 5, &umr_bitfield_default },
	 { "DC_GPIO_HPD12_SPIKERCEN", 8, 8, &umr_bitfield_default },
	 { "DC_GPIO_HPD34_SPIKERCEN", 9, 9, &umr_bitfield_default },
	 { "DC_GPIO_HPD56_SPIKERCEN", 10, 10, &umr_bitfield_default },
	 { "DC_GPIO_HPD12_SPIKERCSEL", 12, 12, &umr_bitfield_default },
	 { "DC_GPIO_HPD34_SPIKERCSEL", 13, 13, &umr_bitfield_default },
	 { "DC_GPIO_HPD56_SPIKERCSEL", 14, 14, &umr_bitfield_default },
	 { "DC_GPIO_HPD_CSEL_0P9", 16, 16, &umr_bitfield_default },
	 { "DC_GPIO_HPD_CSEL_1P1", 17, 17, &umr_bitfield_default },
	 { "DC_GPIO_HPD_RSEL_0P9", 18, 18, &umr_bitfield_default },
	 { "DC_GPIO_HPD_RSEL_1P1", 19, 19, &umr_bitfield_default },
	 { "DC_GPIO_HPD_BIASCRTEN", 20, 20, &umr_bitfield_default },
	 { "DC_GPIO_HPD12_SLEWN", 24, 24, &umr_bitfield_default },
	 { "DC_GPIO_HPD34_SLEWN", 25, 25, &umr_bitfield_default },
	 { "DC_GPIO_HPD56_SLEWN", 26, 26, &umr_bitfield_default },
	 { "DC_GPIO_HPD_RESBIASEN", 27, 27, &umr_bitfield_default },
	 { "DC_GPIO_HPD12_COMPSEL", 28, 28, &umr_bitfield_default },
	 { "DC_GPIO_HPD34_COMPSEL", 29, 29, &umr_bitfield_default },
	 { "DC_GPIO_HPD56_COMPSEL", 30, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_GPIO_RXEN[] = {
	 { "DC_GPIO_GENERICA_RXEN", 0, 0, &umr_bitfield_default },
	 { "DC_GPIO_GENERICB_RXEN", 1, 1, &umr_bitfield_default },
	 { "DC_GPIO_GENERICC_RXEN", 2, 2, &umr_bitfield_default },
	 { "DC_GPIO_GENERICD_RXEN", 3, 3, &umr_bitfield_default },
	 { "DC_GPIO_GENERICE_RXEN", 4, 4, &umr_bitfield_default },
	 { "DC_GPIO_GENERICF_RXEN", 5, 5, &umr_bitfield_default },
	 { "DC_GPIO_GENERICG_RXEN", 6, 6, &umr_bitfield_default },
	 { "DC_GPIO_HSYNCA_RXEN", 8, 8, &umr_bitfield_default },
	 { "DC_GPIO_VSYNCA_RXEN", 9, 9, &umr_bitfield_default },
	 { "DC_GPIO_GENLK_CLK_RXEN", 10, 10, &umr_bitfield_default },
	 { "DC_GPIO_GENLK_VSYNC_RXEN", 11, 11, &umr_bitfield_default },
	 { "DC_GPIO_SWAPLOCK_A_RXEN", 12, 12, &umr_bitfield_default },
	 { "DC_GPIO_SWAPLOCK_B_RXEN", 13, 13, &umr_bitfield_default },
	 { "DC_GPIO_HPD1_RXEN", 14, 14, &umr_bitfield_default },
	 { "DC_GPIO_HPD2_RXEN", 15, 15, &umr_bitfield_default },
	 { "DC_GPIO_HPD3_RXEN", 16, 16, &umr_bitfield_default },
	 { "DC_GPIO_HPD4_RXEN", 17, 17, &umr_bitfield_default },
	 { "DC_GPIO_HPD5_RXEN", 18, 18, &umr_bitfield_default },
	 { "DC_GPIO_HPD6_RXEN", 19, 19, &umr_bitfield_default },
	 { "DC_GPIO_BLON_RXEN", 20, 20, &umr_bitfield_default },
	 { "DC_GPIO_DIGON_RXEN", 21, 21, &umr_bitfield_default },
	 { "DC_GPIO_ENA_BL_RXEN", 22, 22, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_GPIO_PULLUPEN[] = {
	 { "DC_GPIO_GENERICA_PU_EN", 0, 0, &umr_bitfield_default },
	 { "DC_GPIO_GENERICB_PU_EN", 1, 1, &umr_bitfield_default },
	 { "DC_GPIO_GENERICC_PU_EN", 2, 2, &umr_bitfield_default },
	 { "DC_GPIO_GENERICD_PU_EN", 3, 3, &umr_bitfield_default },
	 { "DC_GPIO_GENERICE_PU_EN", 4, 4, &umr_bitfield_default },
	 { "DC_GPIO_GENERICF_PU_EN", 5, 5, &umr_bitfield_default },
	 { "DC_GPIO_GENERICG_PU_EN", 6, 6, &umr_bitfield_default },
	 { "DC_GPIO_HSYNCA_PU_EN", 8, 8, &umr_bitfield_default },
	 { "DC_GPIO_VSYNCA_PU_EN", 9, 9, &umr_bitfield_default },
	 { "DC_GPIO_HPD1_PU_EN", 14, 14, &umr_bitfield_default },
	 { "DC_GPIO_BLON_PU_EN", 20, 20, &umr_bitfield_default },
	 { "DC_GPIO_DIGON_PU_EN", 21, 21, &umr_bitfield_default },
	 { "DC_GPIO_ENA_BL_PU_EN", 22, 22, &umr_bitfield_default },
};
static struct umr_bitfield mmDAC_MACRO_CNTL_RESERVED0[] = {
	 { "DAC_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDAC_MACRO_CNTL_RESERVED1[] = {
	 { "DAC_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDAC_MACRO_CNTL_RESERVED2[] = {
	 { "DAC_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDAC_MACRO_CNTL_RESERVED3[] = {
	 { "DAC_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED0[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED1[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED2[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED3[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED4[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED5[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED6[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED7[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED8[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED9[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED10[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED11[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED12[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED13[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED14[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED15[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED16[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED17[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED18[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED19[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED20[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED21[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED22[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED23[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED24[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED25[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED26[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED27[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED28[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED29[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED30[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED31[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED32[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED33[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED34[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED35[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED36[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED37[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED38[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED39[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED40[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED41[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED42[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED43[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED44[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED45[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED46[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED47[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED48[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED49[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED50[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED51[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED52[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED53[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED54[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED55[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED56[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED57[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED58[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED59[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED60[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED61[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED62[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED63[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED64[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED65[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED66[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED67[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED68[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED69[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED70[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED71[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED72[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED73[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED74[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED75[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED76[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED77[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED78[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED79[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED80[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED81[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED82[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED83[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED84[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED85[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED86[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED87[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED88[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED89[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED90[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED91[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED92[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED93[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED94[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED95[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED96[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED97[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED98[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED99[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED100[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED101[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED102[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED103[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED104[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED105[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED106[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED107[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED108[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED109[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED110[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED111[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED112[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED113[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED114[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED115[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED116[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED117[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED118[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED119[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED120[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED121[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED122[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED123[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED124[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED125[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED126[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED127[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED128[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED129[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED130[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED131[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED132[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED133[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED134[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED135[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED136[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED137[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED138[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED139[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED140[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED141[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED142[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED143[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED144[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED145[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED146[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED147[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED148[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED149[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED150[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED151[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED152[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED153[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED154[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED155[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED156[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED157[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED158[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED159[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_COMBOPHYCMREGS0_COMMON_FUSE1[] = {
	 { "fuse1_valid", 0, 0, &umr_bitfield_default },
	 { "fuse1_unpopulated0", 1, 2, &umr_bitfield_default },
	 { "fuse1_ron_override_val", 3, 8, &umr_bitfield_default },
	 { "fuse1_unpopulated1", 9, 9, &umr_bitfield_default },
	 { "fuse1_ron_ctl", 10, 11, &umr_bitfield_default },
	 { "fuse1_unpopulated2", 12, 12, &umr_bitfield_default },
	 { "fuse1_rtt_override_val", 13, 18, &umr_bitfield_default },
	 { "fuse1_unpopulated3", 19, 19, &umr_bitfield_default },
	 { "fuse1_rtt_ctl", 20, 21, &umr_bitfield_default },
	 { "fuse1_refresh_cal_en", 22, 22, &umr_bitfield_default },
	 { "fuse1_spare", 23, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_COMBOPHYCMREGS0_COMMON_FUSE2[] = {
	 { "fuse2_valid", 0, 0, &umr_bitfield_default },
	 { "fuse2_unpopulated", 1, 8, &umr_bitfield_default },
	 { "fuse2_tx_fifo_ptr", 9, 13, &umr_bitfield_default },
	 { "fuse2_spare", 14, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_COMBOPHYCMREGS0_COMMON_FUSE3[] = {
	 { "fuse3_valid", 0, 0, &umr_bitfield_default },
	 { "fuse3_unpopulated", 1, 9, &umr_bitfield_default },
	 { "fuse3_ei_det_thresh_sel", 10, 12, &umr_bitfield_default },
	 { "cdr_dac_safeval_sel", 13, 15, &umr_bitfield_default },
	 { "cdr_freq_lock_timer", 16, 17, &umr_bitfield_default },
	 { "cdr_cal_dac_stpsz", 18, 19, &umr_bitfield_default },
	 { "cdr_byp_init_val", 20, 20, &umr_bitfield_default },
	 { "cdr_icostart_sel", 21, 21, &umr_bitfield_default },
	 { "cdr_bbweight", 22, 25, &umr_bitfield_default },
	 { "cdr_cur_mirr_ratio", 26, 28, &umr_bitfield_default },
	 { "fuse3_spare", 29, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_COMBOPHYCMREGS0_COMMON_MAR_DEEMPH_NOM[] = {
	 { "tx_margin_nom", 0, 7, &umr_bitfield_default },
	 { "deemph_gen1_nom", 8, 15, &umr_bitfield_default },
	 { "deemph35_gen2_nom", 16, 23, &umr_bitfield_default },
	 { "deemph60_gen2_nom", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_COMBOPHYCMREGS0_COMMON_LANE_PWRMGMT[] = {
	 { "pgdelay", 0, 3, &umr_bitfield_default },
	 { "pgmask", 4, 9, &umr_bitfield_default },
	 { "vprot_en", 11, 11, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_COMBOPHYCMREGS0_COMMON_TXCNTRL[] = {
	 { "rdptr_rst_val_gen3", 0, 4, &umr_bitfield_default },
	 { "clkgate_dis", 5, 5, &umr_bitfield_default },
	 { "slew_rate_ctl_gen1", 6, 8, &umr_bitfield_default },
	 { "slew_rate_ctl_gen2", 9, 11, &umr_bitfield_default },
	 { "slew_rate_ctl_gen3", 12, 14, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_COMBOPHYCMREGS0_COMMON_TMDP[] = {
	 { "tmdp_spare", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_COMBOPHYCMREGS0_COMMON_LANE_RESETS[] = {
	 { "lane_0_reset_l", 0, 0, &umr_bitfield_default },
	 { "lane_1_reset_l", 1, 1, &umr_bitfield_default },
	 { "lane_2_reset_l", 2, 2, &umr_bitfield_default },
	 { "lane_3_reset_l", 3, 3, &umr_bitfield_default },
	 { "lane_4_reset_l", 4, 4, &umr_bitfield_default },
	 { "lane_5_reset_l", 5, 5, &umr_bitfield_default },
	 { "lane_6_reset_l", 6, 6, &umr_bitfield_default },
	 { "lane_7_reset_l", 7, 7, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_COMBOPHYCMREGS0_COMMON_ZCALCODE_CTRL[] = {
	 { "zcalcode_override", 0, 0, &umr_bitfield_default },
	 { "tx_binary_code_override_val", 1, 5, &umr_bitfield_default },
	 { "rx_therm_code_override_val", 6, 20, &umr_bitfield_default },
	 { "tx_driver_fifty_ohms", 21, 21, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_COMBOPHYCMREGS0_COMMON_DISP_RFU1[] = {
	 { "rfu_value1", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_COMBOPHYCMREGS0_COMMON_DISP_RFU2[] = {
	 { "rfu_value2", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_COMBOPHYCMREGS0_COMMON_DISP_RFU3[] = {
	 { "rfu_value3", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_COMBOPHYCMREGS0_COMMON_DISP_RFU4[] = {
	 { "rfu_value4", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_COMBOPHYCMREGS0_COMMON_DISP_RFU5[] = {
	 { "rfu_value5", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_COMBOPHYCMREGS0_COMMON_DISP_RFU6[] = {
	 { "rfu_value6", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_COMBOPHYCMREGS0_COMMON_DISP_RFU7[] = {
	 { "rfu_value7", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_COMBOPHYTXREGS0_CMD_BUS_TX_CONTROL_LANE0[] = {
	 { "tx_pwr", 0, 2, &umr_bitfield_default },
	 { "tx_pg_en", 3, 4, &umr_bitfield_default },
	 { "tx_rdy", 8, 8, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_COMBOPHYTXREGS0_MARGIN_DEEMPH_LANE0[] = {
	 { "txmarg_sel", 0, 2, &umr_bitfield_default },
	 { "deemph_sel", 3, 4, &umr_bitfield_default },
	 { "tx_margin_en", 5, 5, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE0[] = {
	 { "twosym_en", 1, 2, &umr_bitfield_default },
	 { "link_speed", 3, 4, &umr_bitfield_default },
	 { "gang_mode", 5, 7, &umr_bitfield_default },
	 { "max_linkrate", 8, 9, &umr_bitfield_default },
	 { "pcs_freq", 10, 11, &umr_bitfield_default },
	 { "pcs_clken", 12, 12, &umr_bitfield_default },
	 { "pcs_clkdone", 13, 13, &umr_bitfield_default },
	 { "pll1_always_on", 14, 14, &umr_bitfield_default },
	 { "rdclk_div2_en", 15, 15, &umr_bitfield_default },
	 { "tx_boost_adj", 16, 19, &umr_bitfield_default },
	 { "tx_boost_en", 20, 20, &umr_bitfield_default },
	 { "tx_binary_ron_code_offset", 22, 23, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_COMBOPHYTXREGS0_TX_DISP_RFU0_LANE0[] = {
	 { "rfu_value0", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_COMBOPHYTXREGS0_TX_DISP_RFU1_LANE0[] = {
	 { "rfu_value1", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_COMBOPHYTXREGS0_TX_DISP_RFU2_LANE0[] = {
	 { "rfu_value2", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_COMBOPHYTXREGS0_TX_DISP_RFU3_LANE0[] = {
	 { "rfu_value3", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_COMBOPHYTXREGS0_TX_DISP_RFU4_LANE0[] = {
	 { "rfu_value4", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_COMBOPHYTXREGS0_TX_DISP_RFU5_LANE0[] = {
	 { "rfu_value5", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_COMBOPHYTXREGS0_TX_DISP_RFU6_LANE0[] = {
	 { "rfu_value6", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_COMBOPHYTXREGS0_TX_DISP_RFU7_LANE0[] = {
	 { "rfu_value7", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_COMBOPHYTXREGS0_TX_DISP_RFU8_LANE0[] = {
	 { "rfu_value8", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_COMBOPHYTXREGS0_TX_DISP_RFU9_LANE0[] = {
	 { "rfu_value9", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_COMBOPHYTXREGS0_TX_DISP_RFU10_LANE0[] = {
	 { "rfu_value10", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_COMBOPHYTXREGS0_TX_DISP_RFU11_LANE0[] = {
	 { "rfu_value11", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_COMBOPHYTXREGS0_TX_DISP_RFU12_LANE0[] = {
	 { "rfu_value12", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_COMBOPHYTXREGS0_CMD_BUS_TX_CONTROL_LANE1[] = {
	 { "tx_pwr", 0, 2, &umr_bitfield_default },
	 { "tx_pg_en", 3, 4, &umr_bitfield_default },
	 { "tx_rdy", 8, 8, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_COMBOPHYTXREGS0_MARGIN_DEEMPH_LANE1[] = {
	 { "txmarg_sel", 0, 2, &umr_bitfield_default },
	 { "deemph_sel", 3, 4, &umr_bitfield_default },
	 { "tx_margin_en", 5, 5, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE1[] = {
	 { "twosym_en", 1, 2, &umr_bitfield_default },
	 { "link_speed", 3, 4, &umr_bitfield_default },
	 { "gang_mode", 5, 7, &umr_bitfield_default },
	 { "max_linkrate", 8, 9, &umr_bitfield_default },
	 { "pcs_freq", 10, 11, &umr_bitfield_default },
	 { "pcs_clken", 12, 12, &umr_bitfield_default },
	 { "pcs_clkdone", 13, 13, &umr_bitfield_default },
	 { "pll1_always_on", 14, 14, &umr_bitfield_default },
	 { "rdclk_div2_en", 15, 15, &umr_bitfield_default },
	 { "tx_boost_adj", 16, 19, &umr_bitfield_default },
	 { "tx_boost_en", 20, 20, &umr_bitfield_default },
	 { "tx_binary_ron_code_offset", 22, 23, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_COMBOPHYTXREGS0_TX_DISP_RFU0_LANE1[] = {
	 { "rfu_value0", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_COMBOPHYTXREGS0_TX_DISP_RFU1_LANE1[] = {
	 { "rfu_value1", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_COMBOPHYTXREGS0_TX_DISP_RFU2_LANE1[] = {
	 { "rfu_value2", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_COMBOPHYTXREGS0_TX_DISP_RFU3_LANE1[] = {
	 { "rfu_value3", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_COMBOPHYTXREGS0_TX_DISP_RFU4_LANE1[] = {
	 { "rfu_value4", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_COMBOPHYTXREGS0_TX_DISP_RFU5_LANE1[] = {
	 { "rfu_value5", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_COMBOPHYTXREGS0_TX_DISP_RFU6_LANE1[] = {
	 { "rfu_value6", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_COMBOPHYTXREGS0_TX_DISP_RFU7_LANE1[] = {
	 { "rfu_value7", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_COMBOPHYTXREGS0_TX_DISP_RFU8_LANE1[] = {
	 { "rfu_value8", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_COMBOPHYTXREGS0_TX_DISP_RFU9_LANE1[] = {
	 { "rfu_value9", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_COMBOPHYTXREGS0_TX_DISP_RFU10_LANE1[] = {
	 { "rfu_value10", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_COMBOPHYTXREGS0_TX_DISP_RFU11_LANE1[] = {
	 { "rfu_value11", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_COMBOPHYTXREGS0_TX_DISP_RFU12_LANE1[] = {
	 { "rfu_value12", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_COMBOPHYTXREGS0_CMD_BUS_TX_CONTROL_LANE2[] = {
	 { "tx_pwr", 0, 2, &umr_bitfield_default },
	 { "tx_pg_en", 3, 4, &umr_bitfield_default },
	 { "tx_rdy", 8, 8, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_COMBOPHYTXREGS0_MARGIN_DEEMPH_LANE2[] = {
	 { "txmarg_sel", 0, 2, &umr_bitfield_default },
	 { "deemph_sel", 3, 4, &umr_bitfield_default },
	 { "tx_margin_en", 5, 5, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE2[] = {
	 { "twosym_en", 1, 2, &umr_bitfield_default },
	 { "link_speed", 3, 4, &umr_bitfield_default },
	 { "gang_mode", 5, 7, &umr_bitfield_default },
	 { "max_linkrate", 8, 9, &umr_bitfield_default },
	 { "pcs_freq", 10, 11, &umr_bitfield_default },
	 { "pcs_clken", 12, 12, &umr_bitfield_default },
	 { "pcs_clkdone", 13, 13, &umr_bitfield_default },
	 { "pll1_always_on", 14, 14, &umr_bitfield_default },
	 { "rdclk_div2_en", 15, 15, &umr_bitfield_default },
	 { "tx_boost_adj", 16, 19, &umr_bitfield_default },
	 { "tx_boost_en", 20, 20, &umr_bitfield_default },
	 { "tx_binary_ron_code_offset", 22, 23, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_COMBOPHYTXREGS0_TX_DISP_RFU0_LANE2[] = {
	 { "rfu_value0", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_COMBOPHYTXREGS0_TX_DISP_RFU1_LANE2[] = {
	 { "rfu_value1", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_COMBOPHYTXREGS0_TX_DISP_RFU2_LANE2[] = {
	 { "rfu_value2", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_COMBOPHYTXREGS0_TX_DISP_RFU3_LANE2[] = {
	 { "rfu_value3", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_COMBOPHYTXREGS0_TX_DISP_RFU4_LANE2[] = {
	 { "rfu_value4", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_COMBOPHYTXREGS0_TX_DISP_RFU5_LANE2[] = {
	 { "rfu_value5", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_COMBOPHYTXREGS0_TX_DISP_RFU6_LANE2[] = {
	 { "rfu_value6", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_COMBOPHYTXREGS0_TX_DISP_RFU7_LANE2[] = {
	 { "rfu_value7", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_COMBOPHYTXREGS0_TX_DISP_RFU8_LANE2[] = {
	 { "rfu_value8", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_COMBOPHYTXREGS0_TX_DISP_RFU9_LANE2[] = {
	 { "rfu_value9", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_COMBOPHYTXREGS0_TX_DISP_RFU10_LANE2[] = {
	 { "rfu_value10", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_COMBOPHYTXREGS0_TX_DISP_RFU11_LANE2[] = {
	 { "rfu_value11", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_COMBOPHYTXREGS0_TX_DISP_RFU12_LANE2[] = {
	 { "rfu_value12", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_COMBOPHYTXREGS0_CMD_BUS_TX_CONTROL_LANE3[] = {
	 { "tx_pwr", 0, 2, &umr_bitfield_default },
	 { "tx_pg_en", 3, 4, &umr_bitfield_default },
	 { "tx_rdy", 8, 8, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_COMBOPHYTXREGS0_MARGIN_DEEMPH_LANE3[] = {
	 { "txmarg_sel", 0, 2, &umr_bitfield_default },
	 { "deemph_sel", 3, 4, &umr_bitfield_default },
	 { "tx_margin_en", 5, 5, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE3[] = {
	 { "twosym_en", 1, 2, &umr_bitfield_default },
	 { "link_speed", 3, 4, &umr_bitfield_default },
	 { "gang_mode", 5, 7, &umr_bitfield_default },
	 { "max_linkrate", 8, 9, &umr_bitfield_default },
	 { "pcs_freq", 10, 11, &umr_bitfield_default },
	 { "pcs_clken", 12, 12, &umr_bitfield_default },
	 { "pcs_clkdone", 13, 13, &umr_bitfield_default },
	 { "pll1_always_on", 14, 14, &umr_bitfield_default },
	 { "rdclk_div2_en", 15, 15, &umr_bitfield_default },
	 { "tx_boost_adj", 16, 19, &umr_bitfield_default },
	 { "tx_boost_en", 20, 20, &umr_bitfield_default },
	 { "tx_binary_ron_code_offset", 22, 23, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_COMBOPHYTXREGS0_TX_DISP_RFU0_LANE3[] = {
	 { "rfu_value0", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_COMBOPHYTXREGS0_TX_DISP_RFU1_LANE3[] = {
	 { "rfu_value1", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_COMBOPHYTXREGS0_TX_DISP_RFU2_LANE3[] = {
	 { "rfu_value2", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_COMBOPHYTXREGS0_TX_DISP_RFU3_LANE3[] = {
	 { "rfu_value3", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_COMBOPHYTXREGS0_TX_DISP_RFU4_LANE3[] = {
	 { "rfu_value4", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_COMBOPHYTXREGS0_TX_DISP_RFU5_LANE3[] = {
	 { "rfu_value5", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_COMBOPHYTXREGS0_TX_DISP_RFU6_LANE3[] = {
	 { "rfu_value6", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_COMBOPHYTXREGS0_TX_DISP_RFU7_LANE3[] = {
	 { "rfu_value7", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_COMBOPHYTXREGS0_TX_DISP_RFU8_LANE3[] = {
	 { "rfu_value8", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_COMBOPHYTXREGS0_TX_DISP_RFU9_LANE3[] = {
	 { "rfu_value9", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_COMBOPHYTXREGS0_TX_DISP_RFU10_LANE3[] = {
	 { "rfu_value10", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_COMBOPHYTXREGS0_TX_DISP_RFU11_LANE3[] = {
	 { "rfu_value11", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_COMBOPHYTXREGS0_TX_DISP_RFU12_LANE3[] = {
	 { "rfu_value12", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_COMBOPHYPLLREGS0_FREQ_CTRL0[] = {
	 { "fcw0_frac", 0, 15, &umr_bitfield_default },
	 { "fcw0_int", 16, 24, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_COMBOPHYPLLREGS0_FREQ_CTRL1[] = {
	 { "fcw1_frac", 0, 15, &umr_bitfield_default },
	 { "fcw1_int", 16, 24, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_COMBOPHYPLLREGS0_FREQ_CTRL2[] = {
	 { "fcw_denom", 0, 15, &umr_bitfield_default },
	 { "fcw_slew_frac", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_COMBOPHYPLLREGS0_FREQ_CTRL3[] = {
	 { "refclk_div", 0, 1, &umr_bitfield_default },
	 { "vco_pre_div", 3, 4, &umr_bitfield_default },
	 { "fracn_en", 6, 6, &umr_bitfield_default },
	 { "ssc_en", 8, 8, &umr_bitfield_default },
	 { "fcw_sel", 10, 10, &umr_bitfield_default },
	 { "freq_jump_en", 12, 12, &umr_bitfield_default },
	 { "tdc_resolution", 16, 23, &umr_bitfield_default },
	 { "dpll_cfg_1", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_COMBOPHYPLLREGS0_BW_CTRL_COARSE[] = {
	 { "gi_coarse_mant", 0, 1, &umr_bitfield_default },
	 { "gi_coarse_exp", 2, 5, &umr_bitfield_default },
	 { "gp_coarse_mant", 7, 10, &umr_bitfield_default },
	 { "gp_coarse_exp", 12, 15, &umr_bitfield_default },
	 { "nctl_coarse_res", 17, 22, &umr_bitfield_default },
	 { "nctl_coarse_frac_res", 24, 25, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_COMBOPHYPLLREGS0_BW_CTRL_FINE[] = {
	 { "dpll_cfg_3", 0, 9, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_COMBOPHYPLLREGS0_CAL_CTRL[] = {
	 { "bypass_freq_lock", 0, 0, &umr_bitfield_default },
	 { "tdc_cal_en", 1, 1, &umr_bitfield_default },
	 { "tdc_cal_ctrl", 3, 8, &umr_bitfield_default },
	 { "meas_win_sel", 9, 10, &umr_bitfield_default },
	 { "kdco_cal_dis", 11, 11, &umr_bitfield_default },
	 { "kdco_ratio", 13, 20, &umr_bitfield_default },
	 { "kdco_incr_cal_dis", 22, 22, &umr_bitfield_default },
	 { "nctl_adj_dis", 23, 23, &umr_bitfield_default },
	 { "refclk_rate", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_COMBOPHYPLLREGS0_LOOP_CTRL[] = {
	 { "fbdiv_mask_en", 0, 0, &umr_bitfield_default },
	 { "fb_slip_dis", 2, 2, &umr_bitfield_default },
	 { "clk_tdc_sel", 4, 5, &umr_bitfield_default },
	 { "clk_nctl_sel", 7, 8, &umr_bitfield_default },
	 { "sig_del_patt_sel", 10, 10, &umr_bitfield_default },
	 { "nctl_sig_del_dis", 12, 12, &umr_bitfield_default },
	 { "fbclk_track_refclk", 14, 14, &umr_bitfield_default },
	 { "prbs_en", 16, 16, &umr_bitfield_default },
	 { "tdc_clk_gate_en", 18, 18, &umr_bitfield_default },
	 { "phase_offset", 20, 26, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_COMBOPHYPLLREGS0_VREG_CFG[] = {
	 { "bleeder_ac", 0, 0, &umr_bitfield_default },
	 { "bleeder_en", 1, 1, &umr_bitfield_default },
	 { "is_1p2", 2, 2, &umr_bitfield_default },
	 { "reg_obs_sel", 3, 4, &umr_bitfield_default },
	 { "reg_on_mode", 5, 6, &umr_bitfield_default },
	 { "rlad_tap_sel", 7, 10, &umr_bitfield_default },
	 { "reg_off_hi", 11, 11, &umr_bitfield_default },
	 { "reg_off_lo", 12, 12, &umr_bitfield_default },
	 { "scale_driver", 13, 14, &umr_bitfield_default },
	 { "sel_bump", 15, 15, &umr_bitfield_default },
	 { "sel_rladder_x", 16, 16, &umr_bitfield_default },
	 { "short_rc_filt_x", 17, 17, &umr_bitfield_default },
	 { "vref_pwr_on", 18, 18, &umr_bitfield_default },
	 { "dpll_cfg_2", 20, 27, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_COMBOPHYPLLREGS0_OBSERVE0[] = {
	 { "lock_det_tdc_steps", 0, 4, &umr_bitfield_default },
	 { "clear_sticky_lock", 6, 6, &umr_bitfield_default },
	 { "lock_det_dis", 8, 8, &umr_bitfield_default },
	 { "dco_cfg", 10, 17, &umr_bitfield_default },
	 { "anaobs_sel", 21, 23, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_COMBOPHYPLLREGS0_OBSERVE1[] = {
	 { "digobs_sel", 0, 3, &umr_bitfield_default },
	 { "digobs_trig_sel", 5, 8, &umr_bitfield_default },
	 { "digobs_div", 10, 11, &umr_bitfield_default },
	 { "digobs_trig_div", 13, 14, &umr_bitfield_default },
	 { "lock_timer", 16, 29, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_COMBOPHYPLLREGS0_DFT_OUT[] = {
	 { "dft_data", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_COMBOPHYPLLREGS0_PLL_WRAP_CNTRL1[] = {
	 { "wrap_cfg_sel_clk", 0, 1, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_COMBOPHYPLLREGS0_PLL_WRAP_CNTRL[] = {
	 { "wrap_cfg_pll_freq_programming_ovveride", 0, 0, &umr_bitfield_default },
	 { "wrap_cfg_pll_pwr_state_ovrride", 1, 1, &umr_bitfield_default },
	 { "wrap_cfg_pll_pwr_state", 2, 3, &umr_bitfield_default },
	 { "wrap_cfg_tx_pdiv_val", 5, 7, &umr_bitfield_default },
	 { "wrap_cfg_tx_pixdiv_val", 8, 8, &umr_bitfield_default },
	 { "wrap_cfg_cml_cmos_sel", 10, 10, &umr_bitfield_default },
	 { "wrap_cfg_pll_rdy", 13, 13, &umr_bitfield_default },
	 { "wrap_cfg_pll_update", 14, 14, &umr_bitfield_default },
	 { "wrap_cfg_ref_values_chg", 15, 15, &umr_bitfield_default },
	 { "wrap_cfg_clk_gate_w_rdy", 16, 16, &umr_bitfield_default },
	 { "wrap_cfg_pll_dsm_sel", 17, 19, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED0[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED1[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED2[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED3[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED4[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED5[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED6[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED7[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED8[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED9[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED10[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED11[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED12[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED13[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED14[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED15[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED16[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED17[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED18[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED19[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED20[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED21[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED22[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED23[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED24[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED25[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED26[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED27[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED28[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED29[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED30[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED31[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED32[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED33[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED34[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED35[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED36[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED37[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED38[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED39[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED40[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED41[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED42[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED43[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED44[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED45[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED46[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED47[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED48[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED49[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED50[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED51[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED52[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED53[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED54[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED55[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED56[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED57[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED58[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED59[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED60[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED61[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED62[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED63[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED64[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED65[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED66[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED67[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED68[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED69[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED70[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED71[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED72[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED73[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED74[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED75[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED76[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED77[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED78[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED79[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED80[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED81[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED82[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED83[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED84[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED85[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED86[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED87[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED88[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED89[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED90[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED91[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED92[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED93[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED94[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED95[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED96[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED97[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED98[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED99[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED100[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED101[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED102[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED103[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED104[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED105[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED106[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED107[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED108[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED109[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED110[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED111[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED112[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED113[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED114[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED115[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED116[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED117[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED118[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED119[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED120[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED121[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED122[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED123[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED124[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED125[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED126[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED127[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED128[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED129[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED130[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED131[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED132[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED133[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED134[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED135[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED136[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED137[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED138[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED139[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED140[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED141[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED142[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED143[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED144[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED145[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED146[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED147[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED148[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED149[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED150[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED151[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED152[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED153[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED154[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED155[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED156[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED157[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED158[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED159[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_COMBOPHYCMREGS1_COMMON_FUSE1[] = {
	 { "fuse1_valid", 0, 0, &umr_bitfield_default },
	 { "fuse1_unpopulated0", 1, 2, &umr_bitfield_default },
	 { "fuse1_ron_override_val", 3, 8, &umr_bitfield_default },
	 { "fuse1_unpopulated1", 9, 9, &umr_bitfield_default },
	 { "fuse1_ron_ctl", 10, 11, &umr_bitfield_default },
	 { "fuse1_unpopulated2", 12, 12, &umr_bitfield_default },
	 { "fuse1_rtt_override_val", 13, 18, &umr_bitfield_default },
	 { "fuse1_unpopulated3", 19, 19, &umr_bitfield_default },
	 { "fuse1_rtt_ctl", 20, 21, &umr_bitfield_default },
	 { "fuse1_refresh_cal_en", 22, 22, &umr_bitfield_default },
	 { "fuse1_spare", 23, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_COMBOPHYCMREGS1_COMMON_FUSE2[] = {
	 { "fuse2_valid", 0, 0, &umr_bitfield_default },
	 { "fuse2_unpopulated", 1, 8, &umr_bitfield_default },
	 { "fuse2_tx_fifo_ptr", 9, 13, &umr_bitfield_default },
	 { "fuse2_spare", 14, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_COMBOPHYCMREGS1_COMMON_FUSE3[] = {
	 { "fuse3_valid", 0, 0, &umr_bitfield_default },
	 { "fuse3_unpopulated", 1, 9, &umr_bitfield_default },
	 { "fuse3_ei_det_thresh_sel", 10, 12, &umr_bitfield_default },
	 { "cdr_dac_safeval_sel", 13, 15, &umr_bitfield_default },
	 { "cdr_freq_lock_timer", 16, 17, &umr_bitfield_default },
	 { "cdr_cal_dac_stpsz", 18, 19, &umr_bitfield_default },
	 { "cdr_byp_init_val", 20, 20, &umr_bitfield_default },
	 { "cdr_icostart_sel", 21, 21, &umr_bitfield_default },
	 { "cdr_bbweight", 22, 25, &umr_bitfield_default },
	 { "cdr_cur_mirr_ratio", 26, 28, &umr_bitfield_default },
	 { "fuse3_spare", 29, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_COMBOPHYCMREGS1_COMMON_MAR_DEEMPH_NOM[] = {
	 { "tx_margin_nom", 0, 7, &umr_bitfield_default },
	 { "deemph_gen1_nom", 8, 15, &umr_bitfield_default },
	 { "deemph35_gen2_nom", 16, 23, &umr_bitfield_default },
	 { "deemph60_gen2_nom", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_COMBOPHYCMREGS1_COMMON_LANE_PWRMGMT[] = {
	 { "pgdelay", 0, 3, &umr_bitfield_default },
	 { "pgmask", 4, 9, &umr_bitfield_default },
	 { "vprot_en", 11, 11, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_COMBOPHYCMREGS1_COMMON_TXCNTRL[] = {
	 { "rdptr_rst_val_gen3", 0, 4, &umr_bitfield_default },
	 { "clkgate_dis", 5, 5, &umr_bitfield_default },
	 { "slew_rate_ctl_gen1", 6, 8, &umr_bitfield_default },
	 { "slew_rate_ctl_gen2", 9, 11, &umr_bitfield_default },
	 { "slew_rate_ctl_gen3", 12, 14, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_COMBOPHYCMREGS1_COMMON_TMDP[] = {
	 { "tmdp_spare", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_COMBOPHYCMREGS1_COMMON_LANE_RESETS[] = {
	 { "lane_0_reset_l", 0, 0, &umr_bitfield_default },
	 { "lane_1_reset_l", 1, 1, &umr_bitfield_default },
	 { "lane_2_reset_l", 2, 2, &umr_bitfield_default },
	 { "lane_3_reset_l", 3, 3, &umr_bitfield_default },
	 { "lane_4_reset_l", 4, 4, &umr_bitfield_default },
	 { "lane_5_reset_l", 5, 5, &umr_bitfield_default },
	 { "lane_6_reset_l", 6, 6, &umr_bitfield_default },
	 { "lane_7_reset_l", 7, 7, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_COMBOPHYCMREGS1_COMMON_ZCALCODE_CTRL[] = {
	 { "zcalcode_override", 0, 0, &umr_bitfield_default },
	 { "tx_binary_code_override_val", 1, 5, &umr_bitfield_default },
	 { "rx_therm_code_override_val", 6, 20, &umr_bitfield_default },
	 { "tx_driver_fifty_ohms", 21, 21, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_COMBOPHYCMREGS1_COMMON_DISP_RFU1[] = {
	 { "rfu_value1", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_COMBOPHYCMREGS1_COMMON_DISP_RFU2[] = {
	 { "rfu_value2", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_COMBOPHYCMREGS1_COMMON_DISP_RFU3[] = {
	 { "rfu_value3", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_COMBOPHYCMREGS1_COMMON_DISP_RFU4[] = {
	 { "rfu_value4", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_COMBOPHYCMREGS1_COMMON_DISP_RFU5[] = {
	 { "rfu_value5", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_COMBOPHYCMREGS1_COMMON_DISP_RFU6[] = {
	 { "rfu_value6", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_COMBOPHYCMREGS1_COMMON_DISP_RFU7[] = {
	 { "rfu_value7", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_COMBOPHYTXREGS1_CMD_BUS_TX_CONTROL_LANE0[] = {
	 { "tx_pwr", 0, 2, &umr_bitfield_default },
	 { "tx_pg_en", 3, 4, &umr_bitfield_default },
	 { "tx_rdy", 8, 8, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_COMBOPHYTXREGS1_MARGIN_DEEMPH_LANE0[] = {
	 { "txmarg_sel", 0, 2, &umr_bitfield_default },
	 { "deemph_sel", 3, 4, &umr_bitfield_default },
	 { "tx_margin_en", 5, 5, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE0[] = {
	 { "twosym_en", 1, 2, &umr_bitfield_default },
	 { "link_speed", 3, 4, &umr_bitfield_default },
	 { "gang_mode", 5, 7, &umr_bitfield_default },
	 { "max_linkrate", 8, 9, &umr_bitfield_default },
	 { "pcs_freq", 10, 11, &umr_bitfield_default },
	 { "pcs_clken", 12, 12, &umr_bitfield_default },
	 { "pcs_clkdone", 13, 13, &umr_bitfield_default },
	 { "pll1_always_on", 14, 14, &umr_bitfield_default },
	 { "rdclk_div2_en", 15, 15, &umr_bitfield_default },
	 { "tx_boost_adj", 16, 19, &umr_bitfield_default },
	 { "tx_boost_en", 20, 20, &umr_bitfield_default },
	 { "tx_binary_ron_code_offset", 22, 23, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_COMBOPHYTXREGS1_TX_DISP_RFU0_LANE0[] = {
	 { "rfu_value0", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_COMBOPHYTXREGS1_TX_DISP_RFU1_LANE0[] = {
	 { "rfu_value1", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_COMBOPHYTXREGS1_TX_DISP_RFU2_LANE0[] = {
	 { "rfu_value2", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_COMBOPHYTXREGS1_TX_DISP_RFU3_LANE0[] = {
	 { "rfu_value3", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_COMBOPHYTXREGS1_TX_DISP_RFU4_LANE0[] = {
	 { "rfu_value4", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_COMBOPHYTXREGS1_TX_DISP_RFU5_LANE0[] = {
	 { "rfu_value5", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_COMBOPHYTXREGS1_TX_DISP_RFU6_LANE0[] = {
	 { "rfu_value6", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_COMBOPHYTXREGS1_TX_DISP_RFU7_LANE0[] = {
	 { "rfu_value7", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_COMBOPHYTXREGS1_TX_DISP_RFU8_LANE0[] = {
	 { "rfu_value8", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_COMBOPHYTXREGS1_TX_DISP_RFU9_LANE0[] = {
	 { "rfu_value9", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_COMBOPHYTXREGS1_TX_DISP_RFU10_LANE0[] = {
	 { "rfu_value10", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_COMBOPHYTXREGS1_TX_DISP_RFU11_LANE0[] = {
	 { "rfu_value11", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_COMBOPHYTXREGS1_TX_DISP_RFU12_LANE0[] = {
	 { "rfu_value12", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_COMBOPHYTXREGS1_CMD_BUS_TX_CONTROL_LANE1[] = {
	 { "tx_pwr", 0, 2, &umr_bitfield_default },
	 { "tx_pg_en", 3, 4, &umr_bitfield_default },
	 { "tx_rdy", 8, 8, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_COMBOPHYTXREGS1_MARGIN_DEEMPH_LANE1[] = {
	 { "txmarg_sel", 0, 2, &umr_bitfield_default },
	 { "deemph_sel", 3, 4, &umr_bitfield_default },
	 { "tx_margin_en", 5, 5, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE1[] = {
	 { "twosym_en", 1, 2, &umr_bitfield_default },
	 { "link_speed", 3, 4, &umr_bitfield_default },
	 { "gang_mode", 5, 7, &umr_bitfield_default },
	 { "max_linkrate", 8, 9, &umr_bitfield_default },
	 { "pcs_freq", 10, 11, &umr_bitfield_default },
	 { "pcs_clken", 12, 12, &umr_bitfield_default },
	 { "pcs_clkdone", 13, 13, &umr_bitfield_default },
	 { "pll1_always_on", 14, 14, &umr_bitfield_default },
	 { "rdclk_div2_en", 15, 15, &umr_bitfield_default },
	 { "tx_boost_adj", 16, 19, &umr_bitfield_default },
	 { "tx_boost_en", 20, 20, &umr_bitfield_default },
	 { "tx_binary_ron_code_offset", 22, 23, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_COMBOPHYTXREGS1_TX_DISP_RFU0_LANE1[] = {
	 { "rfu_value0", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_COMBOPHYTXREGS1_TX_DISP_RFU1_LANE1[] = {
	 { "rfu_value1", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_COMBOPHYTXREGS1_TX_DISP_RFU2_LANE1[] = {
	 { "rfu_value2", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_COMBOPHYTXREGS1_TX_DISP_RFU3_LANE1[] = {
	 { "rfu_value3", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_COMBOPHYTXREGS1_TX_DISP_RFU4_LANE1[] = {
	 { "rfu_value4", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_COMBOPHYTXREGS1_TX_DISP_RFU5_LANE1[] = {
	 { "rfu_value5", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_COMBOPHYTXREGS1_TX_DISP_RFU6_LANE1[] = {
	 { "rfu_value6", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_COMBOPHYTXREGS1_TX_DISP_RFU7_LANE1[] = {
	 { "rfu_value7", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_COMBOPHYTXREGS1_TX_DISP_RFU8_LANE1[] = {
	 { "rfu_value8", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_COMBOPHYTXREGS1_TX_DISP_RFU9_LANE1[] = {
	 { "rfu_value9", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_COMBOPHYTXREGS1_TX_DISP_RFU10_LANE1[] = {
	 { "rfu_value10", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_COMBOPHYTXREGS1_TX_DISP_RFU11_LANE1[] = {
	 { "rfu_value11", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_COMBOPHYTXREGS1_TX_DISP_RFU12_LANE1[] = {
	 { "rfu_value12", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_COMBOPHYTXREGS1_CMD_BUS_TX_CONTROL_LANE2[] = {
	 { "tx_pwr", 0, 2, &umr_bitfield_default },
	 { "tx_pg_en", 3, 4, &umr_bitfield_default },
	 { "tx_rdy", 8, 8, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_COMBOPHYTXREGS1_MARGIN_DEEMPH_LANE2[] = {
	 { "txmarg_sel", 0, 2, &umr_bitfield_default },
	 { "deemph_sel", 3, 4, &umr_bitfield_default },
	 { "tx_margin_en", 5, 5, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE2[] = {
	 { "twosym_en", 1, 2, &umr_bitfield_default },
	 { "link_speed", 3, 4, &umr_bitfield_default },
	 { "gang_mode", 5, 7, &umr_bitfield_default },
	 { "max_linkrate", 8, 9, &umr_bitfield_default },
	 { "pcs_freq", 10, 11, &umr_bitfield_default },
	 { "pcs_clken", 12, 12, &umr_bitfield_default },
	 { "pcs_clkdone", 13, 13, &umr_bitfield_default },
	 { "pll1_always_on", 14, 14, &umr_bitfield_default },
	 { "rdclk_div2_en", 15, 15, &umr_bitfield_default },
	 { "tx_boost_adj", 16, 19, &umr_bitfield_default },
	 { "tx_boost_en", 20, 20, &umr_bitfield_default },
	 { "tx_binary_ron_code_offset", 22, 23, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_COMBOPHYTXREGS1_TX_DISP_RFU0_LANE2[] = {
	 { "rfu_value0", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_COMBOPHYTXREGS1_TX_DISP_RFU1_LANE2[] = {
	 { "rfu_value1", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_COMBOPHYTXREGS1_TX_DISP_RFU2_LANE2[] = {
	 { "rfu_value2", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_COMBOPHYTXREGS1_TX_DISP_RFU3_LANE2[] = {
	 { "rfu_value3", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_COMBOPHYTXREGS1_TX_DISP_RFU4_LANE2[] = {
	 { "rfu_value4", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_COMBOPHYTXREGS1_TX_DISP_RFU5_LANE2[] = {
	 { "rfu_value5", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_COMBOPHYTXREGS1_TX_DISP_RFU6_LANE2[] = {
	 { "rfu_value6", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_COMBOPHYTXREGS1_TX_DISP_RFU7_LANE2[] = {
	 { "rfu_value7", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_COMBOPHYTXREGS1_TX_DISP_RFU8_LANE2[] = {
	 { "rfu_value8", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_COMBOPHYTXREGS1_TX_DISP_RFU9_LANE2[] = {
	 { "rfu_value9", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_COMBOPHYTXREGS1_TX_DISP_RFU10_LANE2[] = {
	 { "rfu_value10", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_COMBOPHYTXREGS1_TX_DISP_RFU11_LANE2[] = {
	 { "rfu_value11", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_COMBOPHYTXREGS1_TX_DISP_RFU12_LANE2[] = {
	 { "rfu_value12", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_COMBOPHYTXREGS1_CMD_BUS_TX_CONTROL_LANE3[] = {
	 { "tx_pwr", 0, 2, &umr_bitfield_default },
	 { "tx_pg_en", 3, 4, &umr_bitfield_default },
	 { "tx_rdy", 8, 8, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_COMBOPHYTXREGS1_MARGIN_DEEMPH_LANE3[] = {
	 { "txmarg_sel", 0, 2, &umr_bitfield_default },
	 { "deemph_sel", 3, 4, &umr_bitfield_default },
	 { "tx_margin_en", 5, 5, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE3[] = {
	 { "twosym_en", 1, 2, &umr_bitfield_default },
	 { "link_speed", 3, 4, &umr_bitfield_default },
	 { "gang_mode", 5, 7, &umr_bitfield_default },
	 { "max_linkrate", 8, 9, &umr_bitfield_default },
	 { "pcs_freq", 10, 11, &umr_bitfield_default },
	 { "pcs_clken", 12, 12, &umr_bitfield_default },
	 { "pcs_clkdone", 13, 13, &umr_bitfield_default },
	 { "pll1_always_on", 14, 14, &umr_bitfield_default },
	 { "rdclk_div2_en", 15, 15, &umr_bitfield_default },
	 { "tx_boost_adj", 16, 19, &umr_bitfield_default },
	 { "tx_boost_en", 20, 20, &umr_bitfield_default },
	 { "tx_binary_ron_code_offset", 22, 23, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_COMBOPHYTXREGS1_TX_DISP_RFU0_LANE3[] = {
	 { "rfu_value0", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_COMBOPHYTXREGS1_TX_DISP_RFU1_LANE3[] = {
	 { "rfu_value1", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_COMBOPHYTXREGS1_TX_DISP_RFU2_LANE3[] = {
	 { "rfu_value2", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_COMBOPHYTXREGS1_TX_DISP_RFU3_LANE3[] = {
	 { "rfu_value3", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_COMBOPHYTXREGS1_TX_DISP_RFU4_LANE3[] = {
	 { "rfu_value4", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_COMBOPHYTXREGS1_TX_DISP_RFU5_LANE3[] = {
	 { "rfu_value5", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_COMBOPHYTXREGS1_TX_DISP_RFU6_LANE3[] = {
	 { "rfu_value6", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_COMBOPHYTXREGS1_TX_DISP_RFU7_LANE3[] = {
	 { "rfu_value7", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_COMBOPHYTXREGS1_TX_DISP_RFU8_LANE3[] = {
	 { "rfu_value8", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_COMBOPHYTXREGS1_TX_DISP_RFU9_LANE3[] = {
	 { "rfu_value9", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_COMBOPHYTXREGS1_TX_DISP_RFU10_LANE3[] = {
	 { "rfu_value10", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_COMBOPHYTXREGS1_TX_DISP_RFU11_LANE3[] = {
	 { "rfu_value11", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_COMBOPHYTXREGS1_TX_DISP_RFU12_LANE3[] = {
	 { "rfu_value12", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_COMBOPHYPLLREGS1_FREQ_CTRL0[] = {
	 { "fcw0_frac", 0, 15, &umr_bitfield_default },
	 { "fcw0_int", 16, 24, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_COMBOPHYPLLREGS1_FREQ_CTRL1[] = {
	 { "fcw1_frac", 0, 15, &umr_bitfield_default },
	 { "fcw1_int", 16, 24, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_COMBOPHYPLLREGS1_FREQ_CTRL2[] = {
	 { "fcw_denom", 0, 15, &umr_bitfield_default },
	 { "fcw_slew_frac", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_COMBOPHYPLLREGS1_FREQ_CTRL3[] = {
	 { "refclk_div", 0, 1, &umr_bitfield_default },
	 { "vco_pre_div", 3, 4, &umr_bitfield_default },
	 { "fracn_en", 6, 6, &umr_bitfield_default },
	 { "ssc_en", 8, 8, &umr_bitfield_default },
	 { "fcw_sel", 10, 10, &umr_bitfield_default },
	 { "freq_jump_en", 12, 12, &umr_bitfield_default },
	 { "tdc_resolution", 16, 23, &umr_bitfield_default },
	 { "dpll_cfg_1", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_COMBOPHYPLLREGS1_BW_CTRL_COARSE[] = {
	 { "gi_coarse_mant", 0, 1, &umr_bitfield_default },
	 { "gi_coarse_exp", 2, 5, &umr_bitfield_default },
	 { "gp_coarse_mant", 7, 10, &umr_bitfield_default },
	 { "gp_coarse_exp", 12, 15, &umr_bitfield_default },
	 { "nctl_coarse_res", 17, 22, &umr_bitfield_default },
	 { "nctl_coarse_frac_res", 24, 25, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_COMBOPHYPLLREGS1_BW_CTRL_FINE[] = {
	 { "dpll_cfg_3", 0, 9, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_COMBOPHYPLLREGS1_CAL_CTRL[] = {
	 { "bypass_freq_lock", 0, 0, &umr_bitfield_default },
	 { "tdc_cal_en", 1, 1, &umr_bitfield_default },
	 { "tdc_cal_ctrl", 3, 8, &umr_bitfield_default },
	 { "meas_win_sel", 9, 10, &umr_bitfield_default },
	 { "kdco_cal_dis", 11, 11, &umr_bitfield_default },
	 { "kdco_ratio", 13, 20, &umr_bitfield_default },
	 { "kdco_incr_cal_dis", 22, 22, &umr_bitfield_default },
	 { "nctl_adj_dis", 23, 23, &umr_bitfield_default },
	 { "refclk_rate", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_COMBOPHYPLLREGS1_LOOP_CTRL[] = {
	 { "fbdiv_mask_en", 0, 0, &umr_bitfield_default },
	 { "fb_slip_dis", 2, 2, &umr_bitfield_default },
	 { "clk_tdc_sel", 4, 5, &umr_bitfield_default },
	 { "clk_nctl_sel", 7, 8, &umr_bitfield_default },
	 { "sig_del_patt_sel", 10, 10, &umr_bitfield_default },
	 { "nctl_sig_del_dis", 12, 12, &umr_bitfield_default },
	 { "fbclk_track_refclk", 14, 14, &umr_bitfield_default },
	 { "prbs_en", 16, 16, &umr_bitfield_default },
	 { "tdc_clk_gate_en", 18, 18, &umr_bitfield_default },
	 { "phase_offset", 20, 26, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_COMBOPHYPLLREGS1_VREG_CFG[] = {
	 { "bleeder_ac", 0, 0, &umr_bitfield_default },
	 { "bleeder_en", 1, 1, &umr_bitfield_default },
	 { "is_1p2", 2, 2, &umr_bitfield_default },
	 { "reg_obs_sel", 3, 4, &umr_bitfield_default },
	 { "reg_on_mode", 5, 6, &umr_bitfield_default },
	 { "rlad_tap_sel", 7, 10, &umr_bitfield_default },
	 { "reg_off_hi", 11, 11, &umr_bitfield_default },
	 { "reg_off_lo", 12, 12, &umr_bitfield_default },
	 { "scale_driver", 13, 14, &umr_bitfield_default },
	 { "sel_bump", 15, 15, &umr_bitfield_default },
	 { "sel_rladder_x", 16, 16, &umr_bitfield_default },
	 { "short_rc_filt_x", 17, 17, &umr_bitfield_default },
	 { "vref_pwr_on", 18, 18, &umr_bitfield_default },
	 { "dpll_cfg_2", 20, 27, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_COMBOPHYPLLREGS1_OBSERVE0[] = {
	 { "lock_det_tdc_steps", 0, 4, &umr_bitfield_default },
	 { "clear_sticky_lock", 6, 6, &umr_bitfield_default },
	 { "lock_det_dis", 8, 8, &umr_bitfield_default },
	 { "dco_cfg", 10, 17, &umr_bitfield_default },
	 { "anaobs_sel", 21, 23, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_COMBOPHYPLLREGS1_OBSERVE1[] = {
	 { "digobs_sel", 0, 3, &umr_bitfield_default },
	 { "digobs_trig_sel", 5, 8, &umr_bitfield_default },
	 { "digobs_div", 10, 11, &umr_bitfield_default },
	 { "digobs_trig_div", 13, 14, &umr_bitfield_default },
	 { "lock_timer", 16, 29, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_COMBOPHYPLLREGS1_DFT_OUT[] = {
	 { "dft_data", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_COMBOPHYPLLREGS1_PLL_WRAP_CNTRL1[] = {
	 { "wrap_cfg_sel_clk", 0, 1, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_COMBOPHYPLLREGS1_PLL_WRAP_CNTRL[] = {
	 { "wrap_cfg_pll_freq_programming_ovveride", 0, 0, &umr_bitfield_default },
	 { "wrap_cfg_pll_pwr_state_ovrride", 1, 1, &umr_bitfield_default },
	 { "wrap_cfg_pll_pwr_state", 2, 3, &umr_bitfield_default },
	 { "wrap_cfg_tx_pdiv_val", 5, 7, &umr_bitfield_default },
	 { "wrap_cfg_tx_pixdiv_val", 8, 8, &umr_bitfield_default },
	 { "wrap_cfg_cml_cmos_sel", 10, 10, &umr_bitfield_default },
	 { "wrap_cfg_pll_rdy", 13, 13, &umr_bitfield_default },
	 { "wrap_cfg_pll_update", 14, 14, &umr_bitfield_default },
	 { "wrap_cfg_ref_values_chg", 15, 15, &umr_bitfield_default },
	 { "wrap_cfg_clk_gate_w_rdy", 16, 16, &umr_bitfield_default },
	 { "wrap_cfg_pll_dsm_sel", 17, 19, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED0[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED1[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED2[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED3[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED4[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED5[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED6[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED7[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED8[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED9[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED10[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED11[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED12[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED13[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED14[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED15[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED16[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED17[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED18[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED19[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED20[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED21[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED22[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED23[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED24[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED25[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED26[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED27[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED28[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED29[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED30[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED31[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED32[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED33[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED34[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED35[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED36[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED37[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED38[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED39[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED40[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED41[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED42[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED43[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED44[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED45[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED46[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED47[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED48[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED49[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED50[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED51[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED52[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED53[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED54[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED55[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED56[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED57[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED58[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED59[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED60[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED61[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED62[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED63[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED64[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED65[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED66[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED67[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED68[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED69[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED70[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED71[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED72[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED73[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED74[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED75[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED76[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED77[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED78[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED79[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED80[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED81[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED82[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED83[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED84[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED85[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED86[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED87[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED88[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED89[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED90[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED91[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED92[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED93[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED94[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED95[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED96[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED97[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED98[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED99[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED100[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED101[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED102[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED103[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED104[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED105[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED106[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED107[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED108[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED109[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED110[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED111[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED112[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED113[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED114[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED115[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED116[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED117[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED118[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED119[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED120[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED121[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED122[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED123[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED124[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED125[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED126[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED127[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED128[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED129[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED130[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED131[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED132[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED133[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED134[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED135[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED136[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED137[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED138[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED139[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED140[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED141[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED142[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED143[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED144[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED145[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED146[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED147[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED148[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED149[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED150[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED151[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED152[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED153[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED154[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED155[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED156[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED157[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED158[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED159[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_COMBOPHYCMREGS2_COMMON_FUSE1[] = {
	 { "fuse1_valid", 0, 0, &umr_bitfield_default },
	 { "fuse1_unpopulated0", 1, 2, &umr_bitfield_default },
	 { "fuse1_ron_override_val", 3, 8, &umr_bitfield_default },
	 { "fuse1_unpopulated1", 9, 9, &umr_bitfield_default },
	 { "fuse1_ron_ctl", 10, 11, &umr_bitfield_default },
	 { "fuse1_unpopulated2", 12, 12, &umr_bitfield_default },
	 { "fuse1_rtt_override_val", 13, 18, &umr_bitfield_default },
	 { "fuse1_unpopulated3", 19, 19, &umr_bitfield_default },
	 { "fuse1_rtt_ctl", 20, 21, &umr_bitfield_default },
	 { "fuse1_refresh_cal_en", 22, 22, &umr_bitfield_default },
	 { "fuse1_spare", 23, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_COMBOPHYCMREGS2_COMMON_FUSE2[] = {
	 { "fuse2_valid", 0, 0, &umr_bitfield_default },
	 { "fuse2_unpopulated", 1, 8, &umr_bitfield_default },
	 { "fuse2_tx_fifo_ptr", 9, 13, &umr_bitfield_default },
	 { "fuse2_spare", 14, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_COMBOPHYCMREGS2_COMMON_FUSE3[] = {
	 { "fuse3_valid", 0, 0, &umr_bitfield_default },
	 { "fuse3_unpopulated", 1, 9, &umr_bitfield_default },
	 { "fuse3_ei_det_thresh_sel", 10, 12, &umr_bitfield_default },
	 { "cdr_dac_safeval_sel", 13, 15, &umr_bitfield_default },
	 { "cdr_freq_lock_timer", 16, 17, &umr_bitfield_default },
	 { "cdr_cal_dac_stpsz", 18, 19, &umr_bitfield_default },
	 { "cdr_byp_init_val", 20, 20, &umr_bitfield_default },
	 { "cdr_icostart_sel", 21, 21, &umr_bitfield_default },
	 { "cdr_bbweight", 22, 25, &umr_bitfield_default },
	 { "cdr_cur_mirr_ratio", 26, 28, &umr_bitfield_default },
	 { "fuse3_spare", 29, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_COMBOPHYCMREGS2_COMMON_MAR_DEEMPH_NOM[] = {
	 { "tx_margin_nom", 0, 7, &umr_bitfield_default },
	 { "deemph_gen1_nom", 8, 15, &umr_bitfield_default },
	 { "deemph35_gen2_nom", 16, 23, &umr_bitfield_default },
	 { "deemph60_gen2_nom", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_COMBOPHYCMREGS2_COMMON_LANE_PWRMGMT[] = {
	 { "pgdelay", 0, 3, &umr_bitfield_default },
	 { "pgmask", 4, 9, &umr_bitfield_default },
	 { "vprot_en", 11, 11, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_COMBOPHYCMREGS2_COMMON_TXCNTRL[] = {
	 { "rdptr_rst_val_gen3", 0, 4, &umr_bitfield_default },
	 { "clkgate_dis", 5, 5, &umr_bitfield_default },
	 { "slew_rate_ctl_gen1", 6, 8, &umr_bitfield_default },
	 { "slew_rate_ctl_gen2", 9, 11, &umr_bitfield_default },
	 { "slew_rate_ctl_gen3", 12, 14, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_COMBOPHYCMREGS2_COMMON_TMDP[] = {
	 { "tmdp_spare", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_COMBOPHYCMREGS2_COMMON_LANE_RESETS[] = {
	 { "lane_0_reset_l", 0, 0, &umr_bitfield_default },
	 { "lane_1_reset_l", 1, 1, &umr_bitfield_default },
	 { "lane_2_reset_l", 2, 2, &umr_bitfield_default },
	 { "lane_3_reset_l", 3, 3, &umr_bitfield_default },
	 { "lane_4_reset_l", 4, 4, &umr_bitfield_default },
	 { "lane_5_reset_l", 5, 5, &umr_bitfield_default },
	 { "lane_6_reset_l", 6, 6, &umr_bitfield_default },
	 { "lane_7_reset_l", 7, 7, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_COMBOPHYCMREGS2_COMMON_ZCALCODE_CTRL[] = {
	 { "zcalcode_override", 0, 0, &umr_bitfield_default },
	 { "tx_binary_code_override_val", 1, 5, &umr_bitfield_default },
	 { "rx_therm_code_override_val", 6, 20, &umr_bitfield_default },
	 { "tx_driver_fifty_ohms", 21, 21, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_COMBOPHYCMREGS2_COMMON_DISP_RFU1[] = {
	 { "rfu_value1", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_COMBOPHYCMREGS2_COMMON_DISP_RFU2[] = {
	 { "rfu_value2", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_COMBOPHYCMREGS2_COMMON_DISP_RFU3[] = {
	 { "rfu_value3", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_COMBOPHYCMREGS2_COMMON_DISP_RFU4[] = {
	 { "rfu_value4", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_COMBOPHYCMREGS2_COMMON_DISP_RFU5[] = {
	 { "rfu_value5", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_COMBOPHYCMREGS2_COMMON_DISP_RFU6[] = {
	 { "rfu_value6", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_COMBOPHYCMREGS2_COMMON_DISP_RFU7[] = {
	 { "rfu_value7", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_COMBOPHYTXREGS2_CMD_BUS_TX_CONTROL_LANE0[] = {
	 { "tx_pwr", 0, 2, &umr_bitfield_default },
	 { "tx_pg_en", 3, 4, &umr_bitfield_default },
	 { "tx_rdy", 8, 8, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_COMBOPHYTXREGS2_MARGIN_DEEMPH_LANE0[] = {
	 { "txmarg_sel", 0, 2, &umr_bitfield_default },
	 { "deemph_sel", 3, 4, &umr_bitfield_default },
	 { "tx_margin_en", 5, 5, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE0[] = {
	 { "twosym_en", 1, 2, &umr_bitfield_default },
	 { "link_speed", 3, 4, &umr_bitfield_default },
	 { "gang_mode", 5, 7, &umr_bitfield_default },
	 { "max_linkrate", 8, 9, &umr_bitfield_default },
	 { "pcs_freq", 10, 11, &umr_bitfield_default },
	 { "pcs_clken", 12, 12, &umr_bitfield_default },
	 { "pcs_clkdone", 13, 13, &umr_bitfield_default },
	 { "pll1_always_on", 14, 14, &umr_bitfield_default },
	 { "rdclk_div2_en", 15, 15, &umr_bitfield_default },
	 { "tx_boost_adj", 16, 19, &umr_bitfield_default },
	 { "tx_boost_en", 20, 20, &umr_bitfield_default },
	 { "tx_binary_ron_code_offset", 22, 23, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_COMBOPHYTXREGS2_TX_DISP_RFU0_LANE0[] = {
	 { "rfu_value0", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_COMBOPHYTXREGS2_TX_DISP_RFU1_LANE0[] = {
	 { "rfu_value1", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_COMBOPHYTXREGS2_TX_DISP_RFU2_LANE0[] = {
	 { "rfu_value2", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_COMBOPHYTXREGS2_TX_DISP_RFU3_LANE0[] = {
	 { "rfu_value3", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_COMBOPHYTXREGS2_TX_DISP_RFU4_LANE0[] = {
	 { "rfu_value4", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_COMBOPHYTXREGS2_TX_DISP_RFU5_LANE0[] = {
	 { "rfu_value5", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_COMBOPHYTXREGS2_TX_DISP_RFU6_LANE0[] = {
	 { "rfu_value6", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_COMBOPHYTXREGS2_TX_DISP_RFU7_LANE0[] = {
	 { "rfu_value7", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_COMBOPHYTXREGS2_TX_DISP_RFU8_LANE0[] = {
	 { "rfu_value8", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_COMBOPHYTXREGS2_TX_DISP_RFU9_LANE0[] = {
	 { "rfu_value9", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_COMBOPHYTXREGS2_TX_DISP_RFU10_LANE0[] = {
	 { "rfu_value10", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_COMBOPHYTXREGS2_TX_DISP_RFU11_LANE0[] = {
	 { "rfu_value11", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_COMBOPHYTXREGS2_TX_DISP_RFU12_LANE0[] = {
	 { "rfu_value12", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_COMBOPHYTXREGS2_CMD_BUS_TX_CONTROL_LANE1[] = {
	 { "tx_pwr", 0, 2, &umr_bitfield_default },
	 { "tx_pg_en", 3, 4, &umr_bitfield_default },
	 { "tx_rdy", 8, 8, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_COMBOPHYTXREGS2_MARGIN_DEEMPH_LANE1[] = {
	 { "txmarg_sel", 0, 2, &umr_bitfield_default },
	 { "deemph_sel", 3, 4, &umr_bitfield_default },
	 { "tx_margin_en", 5, 5, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE1[] = {
	 { "twosym_en", 1, 2, &umr_bitfield_default },
	 { "link_speed", 3, 4, &umr_bitfield_default },
	 { "gang_mode", 5, 7, &umr_bitfield_default },
	 { "max_linkrate", 8, 9, &umr_bitfield_default },
	 { "pcs_freq", 10, 11, &umr_bitfield_default },
	 { "pcs_clken", 12, 12, &umr_bitfield_default },
	 { "pcs_clkdone", 13, 13, &umr_bitfield_default },
	 { "pll1_always_on", 14, 14, &umr_bitfield_default },
	 { "rdclk_div2_en", 15, 15, &umr_bitfield_default },
	 { "tx_boost_adj", 16, 19, &umr_bitfield_default },
	 { "tx_boost_en", 20, 20, &umr_bitfield_default },
	 { "tx_binary_ron_code_offset", 22, 23, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_COMBOPHYTXREGS2_TX_DISP_RFU0_LANE1[] = {
	 { "rfu_value0", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_COMBOPHYTXREGS2_TX_DISP_RFU1_LANE1[] = {
	 { "rfu_value1", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_COMBOPHYTXREGS2_TX_DISP_RFU2_LANE1[] = {
	 { "rfu_value2", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_COMBOPHYTXREGS2_TX_DISP_RFU3_LANE1[] = {
	 { "rfu_value3", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_COMBOPHYTXREGS2_TX_DISP_RFU4_LANE1[] = {
	 { "rfu_value4", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_COMBOPHYTXREGS2_TX_DISP_RFU5_LANE1[] = {
	 { "rfu_value5", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_COMBOPHYTXREGS2_TX_DISP_RFU6_LANE1[] = {
	 { "rfu_value6", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_COMBOPHYTXREGS2_TX_DISP_RFU7_LANE1[] = {
	 { "rfu_value7", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_COMBOPHYTXREGS2_TX_DISP_RFU8_LANE1[] = {
	 { "rfu_value8", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_COMBOPHYTXREGS2_TX_DISP_RFU9_LANE1[] = {
	 { "rfu_value9", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_COMBOPHYTXREGS2_TX_DISP_RFU10_LANE1[] = {
	 { "rfu_value10", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_COMBOPHYTXREGS2_TX_DISP_RFU11_LANE1[] = {
	 { "rfu_value11", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_COMBOPHYTXREGS2_TX_DISP_RFU12_LANE1[] = {
	 { "rfu_value12", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_COMBOPHYTXREGS2_CMD_BUS_TX_CONTROL_LANE2[] = {
	 { "tx_pwr", 0, 2, &umr_bitfield_default },
	 { "tx_pg_en", 3, 4, &umr_bitfield_default },
	 { "tx_rdy", 8, 8, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_COMBOPHYTXREGS2_MARGIN_DEEMPH_LANE2[] = {
	 { "txmarg_sel", 0, 2, &umr_bitfield_default },
	 { "deemph_sel", 3, 4, &umr_bitfield_default },
	 { "tx_margin_en", 5, 5, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE2[] = {
	 { "twosym_en", 1, 2, &umr_bitfield_default },
	 { "link_speed", 3, 4, &umr_bitfield_default },
	 { "gang_mode", 5, 7, &umr_bitfield_default },
	 { "max_linkrate", 8, 9, &umr_bitfield_default },
	 { "pcs_freq", 10, 11, &umr_bitfield_default },
	 { "pcs_clken", 12, 12, &umr_bitfield_default },
	 { "pcs_clkdone", 13, 13, &umr_bitfield_default },
	 { "pll1_always_on", 14, 14, &umr_bitfield_default },
	 { "rdclk_div2_en", 15, 15, &umr_bitfield_default },
	 { "tx_boost_adj", 16, 19, &umr_bitfield_default },
	 { "tx_boost_en", 20, 20, &umr_bitfield_default },
	 { "tx_binary_ron_code_offset", 22, 23, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_COMBOPHYTXREGS2_TX_DISP_RFU0_LANE2[] = {
	 { "rfu_value0", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_COMBOPHYTXREGS2_TX_DISP_RFU1_LANE2[] = {
	 { "rfu_value1", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_COMBOPHYTXREGS2_TX_DISP_RFU2_LANE2[] = {
	 { "rfu_value2", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_COMBOPHYTXREGS2_TX_DISP_RFU3_LANE2[] = {
	 { "rfu_value3", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_COMBOPHYTXREGS2_TX_DISP_RFU4_LANE2[] = {
	 { "rfu_value4", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_COMBOPHYTXREGS2_TX_DISP_RFU5_LANE2[] = {
	 { "rfu_value5", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_COMBOPHYTXREGS2_TX_DISP_RFU6_LANE2[] = {
	 { "rfu_value6", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_COMBOPHYTXREGS2_TX_DISP_RFU7_LANE2[] = {
	 { "rfu_value7", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_COMBOPHYTXREGS2_TX_DISP_RFU8_LANE2[] = {
	 { "rfu_value8", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_COMBOPHYTXREGS2_TX_DISP_RFU9_LANE2[] = {
	 { "rfu_value9", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_COMBOPHYTXREGS2_TX_DISP_RFU10_LANE2[] = {
	 { "rfu_value10", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_COMBOPHYTXREGS2_TX_DISP_RFU11_LANE2[] = {
	 { "rfu_value11", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_COMBOPHYTXREGS2_TX_DISP_RFU12_LANE2[] = {
	 { "rfu_value12", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_COMBOPHYTXREGS2_CMD_BUS_TX_CONTROL_LANE3[] = {
	 { "tx_pwr", 0, 2, &umr_bitfield_default },
	 { "tx_pg_en", 3, 4, &umr_bitfield_default },
	 { "tx_rdy", 8, 8, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_COMBOPHYTXREGS2_MARGIN_DEEMPH_LANE3[] = {
	 { "txmarg_sel", 0, 2, &umr_bitfield_default },
	 { "deemph_sel", 3, 4, &umr_bitfield_default },
	 { "tx_margin_en", 5, 5, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE3[] = {
	 { "twosym_en", 1, 2, &umr_bitfield_default },
	 { "link_speed", 3, 4, &umr_bitfield_default },
	 { "gang_mode", 5, 7, &umr_bitfield_default },
	 { "max_linkrate", 8, 9, &umr_bitfield_default },
	 { "pcs_freq", 10, 11, &umr_bitfield_default },
	 { "pcs_clken", 12, 12, &umr_bitfield_default },
	 { "pcs_clkdone", 13, 13, &umr_bitfield_default },
	 { "pll1_always_on", 14, 14, &umr_bitfield_default },
	 { "rdclk_div2_en", 15, 15, &umr_bitfield_default },
	 { "tx_boost_adj", 16, 19, &umr_bitfield_default },
	 { "tx_boost_en", 20, 20, &umr_bitfield_default },
	 { "tx_binary_ron_code_offset", 22, 23, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_COMBOPHYTXREGS2_TX_DISP_RFU0_LANE3[] = {
	 { "rfu_value0", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_COMBOPHYTXREGS2_TX_DISP_RFU1_LANE3[] = {
	 { "rfu_value1", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_COMBOPHYTXREGS2_TX_DISP_RFU2_LANE3[] = {
	 { "rfu_value2", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_COMBOPHYTXREGS2_TX_DISP_RFU3_LANE3[] = {
	 { "rfu_value3", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_COMBOPHYTXREGS2_TX_DISP_RFU4_LANE3[] = {
	 { "rfu_value4", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_COMBOPHYTXREGS2_TX_DISP_RFU5_LANE3[] = {
	 { "rfu_value5", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_COMBOPHYTXREGS2_TX_DISP_RFU6_LANE3[] = {
	 { "rfu_value6", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_COMBOPHYTXREGS2_TX_DISP_RFU7_LANE3[] = {
	 { "rfu_value7", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_COMBOPHYTXREGS2_TX_DISP_RFU8_LANE3[] = {
	 { "rfu_value8", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_COMBOPHYTXREGS2_TX_DISP_RFU9_LANE3[] = {
	 { "rfu_value9", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_COMBOPHYTXREGS2_TX_DISP_RFU10_LANE3[] = {
	 { "rfu_value10", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_COMBOPHYTXREGS2_TX_DISP_RFU11_LANE3[] = {
	 { "rfu_value11", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_COMBOPHYTXREGS2_TX_DISP_RFU12_LANE3[] = {
	 { "rfu_value12", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_COMBOPHYPLLREGS2_FREQ_CTRL0[] = {
	 { "fcw0_frac", 0, 15, &umr_bitfield_default },
	 { "fcw0_int", 16, 24, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_COMBOPHYPLLREGS2_FREQ_CTRL1[] = {
	 { "fcw1_frac", 0, 15, &umr_bitfield_default },
	 { "fcw1_int", 16, 24, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_COMBOPHYPLLREGS2_FREQ_CTRL2[] = {
	 { "fcw_denom", 0, 15, &umr_bitfield_default },
	 { "fcw_slew_frac", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_COMBOPHYPLLREGS2_FREQ_CTRL3[] = {
	 { "refclk_div", 0, 1, &umr_bitfield_default },
	 { "vco_pre_div", 3, 4, &umr_bitfield_default },
	 { "fracn_en", 6, 6, &umr_bitfield_default },
	 { "ssc_en", 8, 8, &umr_bitfield_default },
	 { "fcw_sel", 10, 10, &umr_bitfield_default },
	 { "freq_jump_en", 12, 12, &umr_bitfield_default },
	 { "tdc_resolution", 16, 23, &umr_bitfield_default },
	 { "dpll_cfg_1", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_COMBOPHYPLLREGS2_BW_CTRL_COARSE[] = {
	 { "gi_coarse_mant", 0, 1, &umr_bitfield_default },
	 { "gi_coarse_exp", 2, 5, &umr_bitfield_default },
	 { "gp_coarse_mant", 7, 10, &umr_bitfield_default },
	 { "gp_coarse_exp", 12, 15, &umr_bitfield_default },
	 { "nctl_coarse_res", 17, 22, &umr_bitfield_default },
	 { "nctl_coarse_frac_res", 24, 25, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_COMBOPHYPLLREGS2_BW_CTRL_FINE[] = {
	 { "dpll_cfg_3", 0, 9, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_COMBOPHYPLLREGS2_CAL_CTRL[] = {
	 { "bypass_freq_lock", 0, 0, &umr_bitfield_default },
	 { "tdc_cal_en", 1, 1, &umr_bitfield_default },
	 { "tdc_cal_ctrl", 3, 8, &umr_bitfield_default },
	 { "meas_win_sel", 9, 10, &umr_bitfield_default },
	 { "kdco_cal_dis", 11, 11, &umr_bitfield_default },
	 { "kdco_ratio", 13, 20, &umr_bitfield_default },
	 { "kdco_incr_cal_dis", 22, 22, &umr_bitfield_default },
	 { "nctl_adj_dis", 23, 23, &umr_bitfield_default },
	 { "refclk_rate", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_COMBOPHYPLLREGS2_LOOP_CTRL[] = {
	 { "fbdiv_mask_en", 0, 0, &umr_bitfield_default },
	 { "fb_slip_dis", 2, 2, &umr_bitfield_default },
	 { "clk_tdc_sel", 4, 5, &umr_bitfield_default },
	 { "clk_nctl_sel", 7, 8, &umr_bitfield_default },
	 { "sig_del_patt_sel", 10, 10, &umr_bitfield_default },
	 { "nctl_sig_del_dis", 12, 12, &umr_bitfield_default },
	 { "fbclk_track_refclk", 14, 14, &umr_bitfield_default },
	 { "prbs_en", 16, 16, &umr_bitfield_default },
	 { "tdc_clk_gate_en", 18, 18, &umr_bitfield_default },
	 { "phase_offset", 20, 26, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_COMBOPHYPLLREGS2_VREG_CFG[] = {
	 { "bleeder_ac", 0, 0, &umr_bitfield_default },
	 { "bleeder_en", 1, 1, &umr_bitfield_default },
	 { "is_1p2", 2, 2, &umr_bitfield_default },
	 { "reg_obs_sel", 3, 4, &umr_bitfield_default },
	 { "reg_on_mode", 5, 6, &umr_bitfield_default },
	 { "rlad_tap_sel", 7, 10, &umr_bitfield_default },
	 { "reg_off_hi", 11, 11, &umr_bitfield_default },
	 { "reg_off_lo", 12, 12, &umr_bitfield_default },
	 { "scale_driver", 13, 14, &umr_bitfield_default },
	 { "sel_bump", 15, 15, &umr_bitfield_default },
	 { "sel_rladder_x", 16, 16, &umr_bitfield_default },
	 { "short_rc_filt_x", 17, 17, &umr_bitfield_default },
	 { "vref_pwr_on", 18, 18, &umr_bitfield_default },
	 { "dpll_cfg_2", 20, 27, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_COMBOPHYPLLREGS2_OBSERVE0[] = {
	 { "lock_det_tdc_steps", 0, 4, &umr_bitfield_default },
	 { "clear_sticky_lock", 6, 6, &umr_bitfield_default },
	 { "lock_det_dis", 8, 8, &umr_bitfield_default },
	 { "dco_cfg", 10, 17, &umr_bitfield_default },
	 { "anaobs_sel", 21, 23, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_COMBOPHYPLLREGS2_OBSERVE1[] = {
	 { "digobs_sel", 0, 3, &umr_bitfield_default },
	 { "digobs_trig_sel", 5, 8, &umr_bitfield_default },
	 { "digobs_div", 10, 11, &umr_bitfield_default },
	 { "digobs_trig_div", 13, 14, &umr_bitfield_default },
	 { "lock_timer", 16, 29, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_COMBOPHYPLLREGS2_DFT_OUT[] = {
	 { "dft_data", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_COMBOPHYPLLREGS2_PLL_WRAP_CNTRL1[] = {
	 { "wrap_cfg_sel_clk", 0, 1, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_COMBOPHYPLLREGS2_PLL_WRAP_CNTRL[] = {
	 { "wrap_cfg_pll_freq_programming_ovveride", 0, 0, &umr_bitfield_default },
	 { "wrap_cfg_pll_pwr_state_ovrride", 1, 1, &umr_bitfield_default },
	 { "wrap_cfg_pll_pwr_state", 2, 3, &umr_bitfield_default },
	 { "wrap_cfg_tx_pdiv_val", 5, 7, &umr_bitfield_default },
	 { "wrap_cfg_tx_pixdiv_val", 8, 8, &umr_bitfield_default },
	 { "wrap_cfg_cml_cmos_sel", 10, 10, &umr_bitfield_default },
	 { "wrap_cfg_pll_rdy", 13, 13, &umr_bitfield_default },
	 { "wrap_cfg_pll_update", 14, 14, &umr_bitfield_default },
	 { "wrap_cfg_ref_values_chg", 15, 15, &umr_bitfield_default },
	 { "wrap_cfg_clk_gate_w_rdy", 16, 16, &umr_bitfield_default },
	 { "wrap_cfg_pll_dsm_sel", 17, 19, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED0[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED1[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED2[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED3[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED4[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED5[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED6[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED7[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED8[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED9[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED10[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED11[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED12[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED13[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED14[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED15[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED16[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED17[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED18[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED19[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED20[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED21[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED22[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED23[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED24[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED25[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED26[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED27[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED28[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED29[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED30[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED31[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED32[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED33[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED34[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED35[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED36[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED37[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED38[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED39[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED40[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED41[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED42[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED43[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED44[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED45[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED46[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED47[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED48[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED49[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED50[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED51[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED52[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED53[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED54[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED55[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED56[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED57[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED58[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED59[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED60[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED61[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED62[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED63[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED64[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED65[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED66[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED67[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED68[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED69[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED70[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED71[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED72[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED73[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED74[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED75[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED76[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED77[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED78[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED79[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED80[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED81[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED82[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED83[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED84[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED85[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED86[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED87[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED88[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED89[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED90[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED91[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED92[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED93[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED94[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED95[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED96[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED97[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED98[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED99[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED100[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED101[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED102[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED103[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED104[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED105[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED106[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED107[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED108[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED109[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED110[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED111[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED112[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED113[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED114[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED115[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED116[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED117[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED118[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED119[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED120[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED121[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED122[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED123[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED124[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED125[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED126[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED127[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED128[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED129[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED130[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED131[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED132[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED133[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED134[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED135[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED136[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED137[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED138[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED139[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED140[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED141[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED142[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED143[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED144[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED145[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED146[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED147[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED148[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED149[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED150[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED151[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED152[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED153[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED154[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED155[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED156[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED157[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED158[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED159[] = {
	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_COMBOPHYCMREGS3_COMMON_FUSE1[] = {
	 { "fuse1_valid", 0, 0, &umr_bitfield_default },
	 { "fuse1_unpopulated0", 1, 2, &umr_bitfield_default },
	 { "fuse1_ron_override_val", 3, 8, &umr_bitfield_default },
	 { "fuse1_unpopulated1", 9, 9, &umr_bitfield_default },
	 { "fuse1_ron_ctl", 10, 11, &umr_bitfield_default },
	 { "fuse1_unpopulated2", 12, 12, &umr_bitfield_default },
	 { "fuse1_rtt_override_val", 13, 18, &umr_bitfield_default },
	 { "fuse1_unpopulated3", 19, 19, &umr_bitfield_default },
	 { "fuse1_rtt_ctl", 20, 21, &umr_bitfield_default },
	 { "fuse1_refresh_cal_en", 22, 22, &umr_bitfield_default },
	 { "fuse1_spare", 23, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_COMBOPHYCMREGS3_COMMON_FUSE2[] = {
	 { "fuse2_valid", 0, 0, &umr_bitfield_default },
	 { "fuse2_unpopulated", 1, 8, &umr_bitfield_default },
	 { "fuse2_tx_fifo_ptr", 9, 13, &umr_bitfield_default },
	 { "fuse2_spare", 14, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_COMBOPHYCMREGS3_COMMON_FUSE3[] = {
	 { "fuse3_valid", 0, 0, &umr_bitfield_default },
	 { "fuse3_unpopulated", 1, 9, &umr_bitfield_default },
	 { "fuse3_ei_det_thresh_sel", 10, 12, &umr_bitfield_default },
	 { "cdr_dac_safeval_sel", 13, 15, &umr_bitfield_default },
	 { "cdr_freq_lock_timer", 16, 17, &umr_bitfield_default },
	 { "cdr_cal_dac_stpsz", 18, 19, &umr_bitfield_default },
	 { "cdr_byp_init_val", 20, 20, &umr_bitfield_default },
	 { "cdr_icostart_sel", 21, 21, &umr_bitfield_default },
	 { "cdr_bbweight", 22, 25, &umr_bitfield_default },
	 { "cdr_cur_mirr_ratio", 26, 28, &umr_bitfield_default },
	 { "fuse3_spare", 29, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_COMBOPHYCMREGS3_COMMON_MAR_DEEMPH_NOM[] = {
	 { "tx_margin_nom", 0, 7, &umr_bitfield_default },
	 { "deemph_gen1_nom", 8, 15, &umr_bitfield_default },
	 { "deemph35_gen2_nom", 16, 23, &umr_bitfield_default },
	 { "deemph60_gen2_nom", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_COMBOPHYCMREGS3_COMMON_LANE_PWRMGMT[] = {
	 { "pgdelay", 0, 3, &umr_bitfield_default },
	 { "pgmask", 4, 9, &umr_bitfield_default },
	 { "vprot_en", 11, 11, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_COMBOPHYCMREGS3_COMMON_TXCNTRL[] = {
	 { "rdptr_rst_val_gen3", 0, 4, &umr_bitfield_default },
	 { "clkgate_dis", 5, 5, &umr_bitfield_default },
	 { "slew_rate_ctl_gen1", 6, 8, &umr_bitfield_default },
	 { "slew_rate_ctl_gen2", 9, 11, &umr_bitfield_default },
	 { "slew_rate_ctl_gen3", 12, 14, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_COMBOPHYCMREGS3_COMMON_TMDP[] = {
	 { "tmdp_spare", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_COMBOPHYCMREGS3_COMMON_LANE_RESETS[] = {
	 { "lane_0_reset_l", 0, 0, &umr_bitfield_default },
	 { "lane_1_reset_l", 1, 1, &umr_bitfield_default },
	 { "lane_2_reset_l", 2, 2, &umr_bitfield_default },
	 { "lane_3_reset_l", 3, 3, &umr_bitfield_default },
	 { "lane_4_reset_l", 4, 4, &umr_bitfield_default },
	 { "lane_5_reset_l", 5, 5, &umr_bitfield_default },
	 { "lane_6_reset_l", 6, 6, &umr_bitfield_default },
	 { "lane_7_reset_l", 7, 7, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_COMBOPHYCMREGS3_COMMON_ZCALCODE_CTRL[] = {
	 { "zcalcode_override", 0, 0, &umr_bitfield_default },
	 { "tx_binary_code_override_val", 1, 5, &umr_bitfield_default },
	 { "rx_therm_code_override_val", 6, 20, &umr_bitfield_default },
	 { "tx_driver_fifty_ohms", 21, 21, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_COMBOPHYCMREGS3_COMMON_DISP_RFU1[] = {
	 { "rfu_value1", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_COMBOPHYCMREGS3_COMMON_DISP_RFU2[] = {
	 { "rfu_value2", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_COMBOPHYCMREGS3_COMMON_DISP_RFU3[] = {
	 { "rfu_value3", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_COMBOPHYCMREGS3_COMMON_DISP_RFU4[] = {
	 { "rfu_value4", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_COMBOPHYCMREGS3_COMMON_DISP_RFU5[] = {
	 { "rfu_value5", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_COMBOPHYCMREGS3_COMMON_DISP_RFU6[] = {
	 { "rfu_value6", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_COMBOPHYCMREGS3_COMMON_DISP_RFU7[] = {
	 { "rfu_value7", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_COMBOPHYTXREGS3_CMD_BUS_TX_CONTROL_LANE0[] = {
	 { "tx_pwr", 0, 2, &umr_bitfield_default },
	 { "tx_pg_en", 3, 4, &umr_bitfield_default },
	 { "tx_rdy", 8, 8, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_COMBOPHYTXREGS3_MARGIN_DEEMPH_LANE0[] = {
	 { "txmarg_sel", 0, 2, &umr_bitfield_default },
	 { "deemph_sel", 3, 4, &umr_bitfield_default },
	 { "tx_margin_en", 5, 5, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE0[] = {
	 { "twosym_en", 1, 2, &umr_bitfield_default },
	 { "link_speed", 3, 4, &umr_bitfield_default },
	 { "gang_mode", 5, 7, &umr_bitfield_default },
	 { "max_linkrate", 8, 9, &umr_bitfield_default },
	 { "pcs_freq", 10, 11, &umr_bitfield_default },
	 { "pcs_clken", 12, 12, &umr_bitfield_default },
	 { "pcs_clkdone", 13, 13, &umr_bitfield_default },
	 { "pll1_always_on", 14, 14, &umr_bitfield_default },
	 { "rdclk_div2_en", 15, 15, &umr_bitfield_default },
	 { "tx_boost_adj", 16, 19, &umr_bitfield_default },
	 { "tx_boost_en", 20, 20, &umr_bitfield_default },
	 { "tx_binary_ron_code_offset", 22, 23, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_COMBOPHYTXREGS3_TX_DISP_RFU0_LANE0[] = {
	 { "rfu_value0", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_COMBOPHYTXREGS3_TX_DISP_RFU1_LANE0[] = {
	 { "rfu_value1", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_COMBOPHYTXREGS3_TX_DISP_RFU2_LANE0[] = {
	 { "rfu_value2", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_COMBOPHYTXREGS3_TX_DISP_RFU3_LANE0[] = {
	 { "rfu_value3", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_COMBOPHYTXREGS3_TX_DISP_RFU4_LANE0[] = {
	 { "rfu_value4", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_COMBOPHYTXREGS3_TX_DISP_RFU5_LANE0[] = {
	 { "rfu_value5", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_COMBOPHYTXREGS3_TX_DISP_RFU6_LANE0[] = {
	 { "rfu_value6", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_COMBOPHYTXREGS3_TX_DISP_RFU7_LANE0[] = {
	 { "rfu_value7", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_COMBOPHYTXREGS3_TX_DISP_RFU8_LANE0[] = {
	 { "rfu_value8", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_COMBOPHYTXREGS3_TX_DISP_RFU9_LANE0[] = {
	 { "rfu_value9", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_COMBOPHYTXREGS3_TX_DISP_RFU10_LANE0[] = {
	 { "rfu_value10", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_COMBOPHYTXREGS3_TX_DISP_RFU11_LANE0[] = {
	 { "rfu_value11", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_COMBOPHYTXREGS3_TX_DISP_RFU12_LANE0[] = {
	 { "rfu_value12", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_COMBOPHYTXREGS3_CMD_BUS_TX_CONTROL_LANE1[] = {
	 { "tx_pwr", 0, 2, &umr_bitfield_default },
	 { "tx_pg_en", 3, 4, &umr_bitfield_default },
	 { "tx_rdy", 8, 8, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_COMBOPHYTXREGS3_MARGIN_DEEMPH_LANE1[] = {
	 { "txmarg_sel", 0, 2, &umr_bitfield_default },
	 { "deemph_sel", 3, 4, &umr_bitfield_default },
	 { "tx_margin_en", 5, 5, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE1[] = {
	 { "twosym_en", 1, 2, &umr_bitfield_default },
	 { "link_speed", 3, 4, &umr_bitfield_default },
	 { "gang_mode", 5, 7, &umr_bitfield_default },
	 { "max_linkrate", 8, 9, &umr_bitfield_default },
	 { "pcs_freq", 10, 11, &umr_bitfield_default },
	 { "pcs_clken", 12, 12, &umr_bitfield_default },
	 { "pcs_clkdone", 13, 13, &umr_bitfield_default },
	 { "pll1_always_on", 14, 14, &umr_bitfield_default },
	 { "rdclk_div2_en", 15, 15, &umr_bitfield_default },
	 { "tx_boost_adj", 16, 19, &umr_bitfield_default },
	 { "tx_boost_en", 20, 20, &umr_bitfield_default },
	 { "tx_binary_ron_code_offset", 22, 23, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_COMBOPHYTXREGS3_TX_DISP_RFU0_LANE1[] = {
	 { "rfu_value0", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_COMBOPHYTXREGS3_TX_DISP_RFU1_LANE1[] = {
	 { "rfu_value1", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_COMBOPHYTXREGS3_TX_DISP_RFU2_LANE1[] = {
	 { "rfu_value2", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_COMBOPHYTXREGS3_TX_DISP_RFU3_LANE1[] = {
	 { "rfu_value3", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_COMBOPHYTXREGS3_TX_DISP_RFU4_LANE1[] = {
	 { "rfu_value4", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_COMBOPHYTXREGS3_TX_DISP_RFU5_LANE1[] = {
	 { "rfu_value5", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_COMBOPHYTXREGS3_TX_DISP_RFU6_LANE1[] = {
	 { "rfu_value6", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_COMBOPHYTXREGS3_TX_DISP_RFU7_LANE1[] = {
	 { "rfu_value7", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_COMBOPHYTXREGS3_TX_DISP_RFU8_LANE1[] = {
	 { "rfu_value8", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_COMBOPHYTXREGS3_TX_DISP_RFU9_LANE1[] = {
	 { "rfu_value9", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_COMBOPHYTXREGS3_TX_DISP_RFU10_LANE1[] = {
	 { "rfu_value10", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_COMBOPHYTXREGS3_TX_DISP_RFU11_LANE1[] = {
	 { "rfu_value11", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_COMBOPHYTXREGS3_TX_DISP_RFU12_LANE1[] = {
	 { "rfu_value12", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_COMBOPHYTXREGS3_CMD_BUS_TX_CONTROL_LANE2[] = {
	 { "tx_pwr", 0, 2, &umr_bitfield_default },
	 { "tx_pg_en", 3, 4, &umr_bitfield_default },
	 { "tx_rdy", 8, 8, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_COMBOPHYTXREGS3_MARGIN_DEEMPH_LANE2[] = {
	 { "txmarg_sel", 0, 2, &umr_bitfield_default },
	 { "deemph_sel", 3, 4, &umr_bitfield_default },
	 { "tx_margin_en", 5, 5, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE2[] = {
	 { "twosym_en", 1, 2, &umr_bitfield_default },
	 { "link_speed", 3, 4, &umr_bitfield_default },
	 { "gang_mode", 5, 7, &umr_bitfield_default },
	 { "max_linkrate", 8, 9, &umr_bitfield_default },
	 { "pcs_freq", 10, 11, &umr_bitfield_default },
	 { "pcs_clken", 12, 12, &umr_bitfield_default },
	 { "pcs_clkdone", 13, 13, &umr_bitfield_default },
	 { "pll1_always_on", 14, 14, &umr_bitfield_default },
	 { "rdclk_div2_en", 15, 15, &umr_bitfield_default },
	 { "tx_boost_adj", 16, 19, &umr_bitfield_default },
	 { "tx_boost_en", 20, 20, &umr_bitfield_default },
	 { "tx_binary_ron_code_offset", 22, 23, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_COMBOPHYTXREGS3_TX_DISP_RFU0_LANE2[] = {
	 { "rfu_value0", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_COMBOPHYTXREGS3_TX_DISP_RFU1_LANE2[] = {
	 { "rfu_value1", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_COMBOPHYTXREGS3_TX_DISP_RFU2_LANE2[] = {
	 { "rfu_value2", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_COMBOPHYTXREGS3_TX_DISP_RFU3_LANE2[] = {
	 { "rfu_value3", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_COMBOPHYTXREGS3_TX_DISP_RFU4_LANE2[] = {
	 { "rfu_value4", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_COMBOPHYTXREGS3_TX_DISP_RFU5_LANE2[] = {
	 { "rfu_value5", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_COMBOPHYTXREGS3_TX_DISP_RFU6_LANE2[] = {
	 { "rfu_value6", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_COMBOPHYTXREGS3_TX_DISP_RFU7_LANE2[] = {
	 { "rfu_value7", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_COMBOPHYTXREGS3_TX_DISP_RFU8_LANE2[] = {
	 { "rfu_value8", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_COMBOPHYTXREGS3_TX_DISP_RFU9_LANE2[] = {
	 { "rfu_value9", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_COMBOPHYTXREGS3_TX_DISP_RFU10_LANE2[] = {
	 { "rfu_value10", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_COMBOPHYTXREGS3_TX_DISP_RFU11_LANE2[] = {
	 { "rfu_value11", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_COMBOPHYTXREGS3_TX_DISP_RFU12_LANE2[] = {
	 { "rfu_value12", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_COMBOPHYTXREGS3_CMD_BUS_TX_CONTROL_LANE3[] = {
	 { "tx_pwr", 0, 2, &umr_bitfield_default },
	 { "tx_pg_en", 3, 4, &umr_bitfield_default },
	 { "tx_rdy", 8, 8, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_COMBOPHYTXREGS3_MARGIN_DEEMPH_LANE3[] = {
	 { "txmarg_sel", 0, 2, &umr_bitfield_default },
	 { "deemph_sel", 3, 4, &umr_bitfield_default },
	 { "tx_margin_en", 5, 5, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE3[] = {
	 { "twosym_en", 1, 2, &umr_bitfield_default },
	 { "link_speed", 3, 4, &umr_bitfield_default },
	 { "gang_mode", 5, 7, &umr_bitfield_default },
	 { "max_linkrate", 8, 9, &umr_bitfield_default },
	 { "pcs_freq", 10, 11, &umr_bitfield_default },
	 { "pcs_clken", 12, 12, &umr_bitfield_default },
	 { "pcs_clkdone", 13, 13, &umr_bitfield_default },
	 { "pll1_always_on", 14, 14, &umr_bitfield_default },
	 { "rdclk_div2_en", 15, 15, &umr_bitfield_default },
	 { "tx_boost_adj", 16, 19, &umr_bitfield_default },
	 { "tx_boost_en", 20, 20, &umr_bitfield_default },
	 { "tx_binary_ron_code_offset", 22, 23, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_COMBOPHYTXREGS3_TX_DISP_RFU0_LANE3[] = {
	 { "rfu_value0", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_COMBOPHYTXREGS3_TX_DISP_RFU1_LANE3[] = {
	 { "rfu_value1", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_COMBOPHYTXREGS3_TX_DISP_RFU2_LANE3[] = {
	 { "rfu_value2", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_COMBOPHYTXREGS3_TX_DISP_RFU3_LANE3[] = {
	 { "rfu_value3", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_COMBOPHYTXREGS3_TX_DISP_RFU4_LANE3[] = {
	 { "rfu_value4", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_COMBOPHYTXREGS3_TX_DISP_RFU5_LANE3[] = {
	 { "rfu_value5", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_COMBOPHYTXREGS3_TX_DISP_RFU6_LANE3[] = {
	 { "rfu_value6", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_COMBOPHYTXREGS3_TX_DISP_RFU7_LANE3[] = {
	 { "rfu_value7", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_COMBOPHYTXREGS3_TX_DISP_RFU8_LANE3[] = {
	 { "rfu_value8", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_COMBOPHYTXREGS3_TX_DISP_RFU9_LANE3[] = {
	 { "rfu_value9", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_COMBOPHYTXREGS3_TX_DISP_RFU10_LANE3[] = {
	 { "rfu_value10", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_COMBOPHYTXREGS3_TX_DISP_RFU11_LANE3[] = {
	 { "rfu_value11", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_COMBOPHYTXREGS3_TX_DISP_RFU12_LANE3[] = {
	 { "rfu_value12", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_COMBOPHYPLLREGS3_FREQ_CTRL0[] = {
	 { "fcw0_frac", 0, 15, &umr_bitfield_default },
	 { "fcw0_int", 16, 24, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_COMBOPHYPLLREGS3_FREQ_CTRL1[] = {
	 { "fcw1_frac", 0, 15, &umr_bitfield_default },
	 { "fcw1_int", 16, 24, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_COMBOPHYPLLREGS3_FREQ_CTRL2[] = {
	 { "fcw_denom", 0, 15, &umr_bitfield_default },
	 { "fcw_slew_frac", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_COMBOPHYPLLREGS3_FREQ_CTRL3[] = {
	 { "refclk_div", 0, 1, &umr_bitfield_default },
	 { "vco_pre_div", 3, 4, &umr_bitfield_default },
	 { "fracn_en", 6, 6, &umr_bitfield_default },
	 { "ssc_en", 8, 8, &umr_bitfield_default },
	 { "fcw_sel", 10, 10, &umr_bitfield_default },
	 { "freq_jump_en", 12, 12, &umr_bitfield_default },
	 { "tdc_resolution", 16, 23, &umr_bitfield_default },
	 { "dpll_cfg_1", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_COMBOPHYPLLREGS3_BW_CTRL_COARSE[] = {
	 { "gi_coarse_mant", 0, 1, &umr_bitfield_default },
	 { "gi_coarse_exp", 2, 5, &umr_bitfield_default },
	 { "gp_coarse_mant", 7, 10, &umr_bitfield_default },
	 { "gp_coarse_exp", 12, 15, &umr_bitfield_default },
	 { "nctl_coarse_res", 17, 22, &umr_bitfield_default },
	 { "nctl_coarse_frac_res", 24, 25, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_COMBOPHYPLLREGS3_BW_CTRL_FINE[] = {
	 { "dpll_cfg_3", 0, 9, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_COMBOPHYPLLREGS3_CAL_CTRL[] = {
	 { "bypass_freq_lock", 0, 0, &umr_bitfield_default },
	 { "tdc_cal_en", 1, 1, &umr_bitfield_default },
	 { "tdc_cal_ctrl", 3, 8, &umr_bitfield_default },
	 { "meas_win_sel", 9, 10, &umr_bitfield_default },
	 { "kdco_cal_dis", 11, 11, &umr_bitfield_default },
	 { "kdco_ratio", 13, 20, &umr_bitfield_default },
	 { "kdco_incr_cal_dis", 22, 22, &umr_bitfield_default },
	 { "nctl_adj_dis", 23, 23, &umr_bitfield_default },
	 { "refclk_rate", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_COMBOPHYPLLREGS3_LOOP_CTRL[] = {
	 { "fbdiv_mask_en", 0, 0, &umr_bitfield_default },
	 { "fb_slip_dis", 2, 2, &umr_bitfield_default },
	 { "clk_tdc_sel", 4, 5, &umr_bitfield_default },
	 { "clk_nctl_sel", 7, 8, &umr_bitfield_default },
	 { "sig_del_patt_sel", 10, 10, &umr_bitfield_default },
	 { "nctl_sig_del_dis", 12, 12, &umr_bitfield_default },
	 { "fbclk_track_refclk", 14, 14, &umr_bitfield_default },
	 { "prbs_en", 16, 16, &umr_bitfield_default },
	 { "tdc_clk_gate_en", 18, 18, &umr_bitfield_default },
	 { "phase_offset", 20, 26, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_COMBOPHYPLLREGS3_VREG_CFG[] = {
	 { "bleeder_ac", 0, 0, &umr_bitfield_default },
	 { "bleeder_en", 1, 1, &umr_bitfield_default },
	 { "is_1p2", 2, 2, &umr_bitfield_default },
	 { "reg_obs_sel", 3, 4, &umr_bitfield_default },
	 { "reg_on_mode", 5, 6, &umr_bitfield_default },
	 { "rlad_tap_sel", 7, 10, &umr_bitfield_default },
	 { "reg_off_hi", 11, 11, &umr_bitfield_default },
	 { "reg_off_lo", 12, 12, &umr_bitfield_default },
	 { "scale_driver", 13, 14, &umr_bitfield_default },
	 { "sel_bump", 15, 15, &umr_bitfield_default },
	 { "sel_rladder_x", 16, 16, &umr_bitfield_default },
	 { "short_rc_filt_x", 17, 17, &umr_bitfield_default },
	 { "vref_pwr_on", 18, 18, &umr_bitfield_default },
	 { "dpll_cfg_2", 20, 27, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_COMBOPHYPLLREGS3_OBSERVE0[] = {
	 { "lock_det_tdc_steps", 0, 4, &umr_bitfield_default },
	 { "clear_sticky_lock", 6, 6, &umr_bitfield_default },
	 { "lock_det_dis", 8, 8, &umr_bitfield_default },
	 { "dco_cfg", 10, 17, &umr_bitfield_default },
	 { "anaobs_sel", 21, 23, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_COMBOPHYPLLREGS3_OBSERVE1[] = {
	 { "digobs_sel", 0, 3, &umr_bitfield_default },
	 { "digobs_trig_sel", 5, 8, &umr_bitfield_default },
	 { "digobs_div", 10, 11, &umr_bitfield_default },
	 { "digobs_trig_div", 13, 14, &umr_bitfield_default },
	 { "lock_timer", 16, 29, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_COMBOPHYPLLREGS3_DFT_OUT[] = {
	 { "dft_data", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_COMBOPHYPLLREGS3_PLL_WRAP_CNTRL1[] = {
	 { "wrap_cfg_sel_clk", 0, 1, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_COMBOPHYPLLREGS3_PLL_WRAP_CNTRL[] = {
	 { "wrap_cfg_pll_freq_programming_ovveride", 0, 0, &umr_bitfield_default },
	 { "wrap_cfg_pll_pwr_state_ovrride", 1, 1, &umr_bitfield_default },
	 { "wrap_cfg_pll_pwr_state", 2, 3, &umr_bitfield_default },
	 { "wrap_cfg_tx_pdiv_val", 5, 7, &umr_bitfield_default },
	 { "wrap_cfg_tx_pixdiv_val", 8, 8, &umr_bitfield_default },
	 { "wrap_cfg_cml_cmos_sel", 10, 10, &umr_bitfield_default },
	 { "wrap_cfg_pll_rdy", 13, 13, &umr_bitfield_default },
	 { "wrap_cfg_pll_update", 14, 14, &umr_bitfield_default },
	 { "wrap_cfg_ref_values_chg", 15, 15, &umr_bitfield_default },
	 { "wrap_cfg_clk_gate_w_rdy", 16, 16, &umr_bitfield_default },
	 { "wrap_cfg_pll_dsm_sel", 17, 19, &umr_bitfield_default },
};
static struct umr_bitfield mmZCAL_MACRO_CNTL_RESERVED0[] = {
	 { "ZCAL_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmZCAL_MACRO_CNTL_RESERVED1[] = {
	 { "ZCAL_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmZCAL_MACRO_CNTL_RESERVED2[] = {
	 { "ZCAL_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmZCAL_MACRO_CNTL_RESERVED3[] = {
	 { "ZCAL_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmZCAL_MACRO_CNTL_RESERVED4[] = {
	 { "ZCAL_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmCOMP_EN_CTL[] = {
	 { "comp_en", 0, 0, &umr_bitfield_default },
	 { "comp_en_override", 2, 2, &umr_bitfield_default },
	 { "comp_done", 4, 4, &umr_bitfield_default },
	 { "zcal_code_override", 6, 6, &umr_bitfield_default },
	 { "zcal_cal_rtt", 7, 7, &umr_bitfield_default },
	 { "zcal_base_en", 8, 8, &umr_bitfield_default },
	 { "zcal_ht_rtt_sel", 9, 9, &umr_bitfield_default },
	 { "zcal_code", 10, 14, &umr_bitfield_default },
	 { "zcal_ron_cal_mode", 16, 16, &umr_bitfield_default },
	 { "zcal_ana_dbg_sel", 17, 18, &umr_bitfield_default },
	 { "cfg_cml_cmos_sel", 19, 19, &umr_bitfield_default },
	 { "dsm_sel", 20, 23, &umr_bitfield_default },
};
static struct umr_bitfield mmCOMP_EN_DFX[] = {
	 { "autocal_ron_code", 0, 4, &umr_bitfield_default },
	 { "autocal_rtt_code", 5, 9, &umr_bitfield_default },
	 { "pre_fused_ron_code", 11, 15, &umr_bitfield_default },
	 { "pre_fused_rtt_code", 16, 20, &umr_bitfield_default },
	 { "broadcast_ron_code", 22, 26, &umr_bitfield_default },
	 { "broadcast_rtt_code", 27, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmZCAL_FUSES[] = {
	 { "fuse_valid", 0, 0, &umr_bitfield_default },
	 { "fuse_ron_override_val", 3, 8, &umr_bitfield_default },
	 { "fuse_ron_ctl", 10, 11, &umr_bitfield_default },
	 { "fuse_rtt_override_val", 13, 18, &umr_bitfield_default },
	 { "fuse_rtt_ctl", 20, 21, &umr_bitfield_default },
	 { "fuse_refresh_cal_en", 22, 22, &umr_bitfield_default },
	 { "fuse_spare", 23, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixSEQ00[] = {
	 { "SEQ_RST0B", 0, 0, &umr_bitfield_default },
	 { "SEQ_RST1B", 1, 1, &umr_bitfield_default },
};
static struct umr_bitfield ixSEQ01[] = {
	 { "SEQ_DOT8", 0, 0, &umr_bitfield_default },
	 { "SEQ_SHIFT2", 2, 2, &umr_bitfield_default },
	 { "SEQ_PCLKBY2", 3, 3, &umr_bitfield_default },
	 { "SEQ_SHIFT4", 4, 4, &umr_bitfield_default },
	 { "SEQ_MAXBW", 5, 5, &umr_bitfield_default },
};
static struct umr_bitfield ixSEQ02[] = {
	 { "SEQ_MAP0_EN", 0, 0, &umr_bitfield_default },
	 { "SEQ_MAP1_EN", 1, 1, &umr_bitfield_default },
	 { "SEQ_MAP2_EN", 2, 2, &umr_bitfield_default },
	 { "SEQ_MAP3_EN", 3, 3, &umr_bitfield_default },
};
static struct umr_bitfield ixSEQ03[] = {
	 { "SEQ_FONT_B1", 0, 0, &umr_bitfield_default },
	 { "SEQ_FONT_B2", 1, 1, &umr_bitfield_default },
	 { "SEQ_FONT_A1", 2, 2, &umr_bitfield_default },
	 { "SEQ_FONT_A2", 3, 3, &umr_bitfield_default },
	 { "SEQ_FONT_B0", 4, 4, &umr_bitfield_default },
	 { "SEQ_FONT_A0", 5, 5, &umr_bitfield_default },
};
static struct umr_bitfield ixSEQ04[] = {
	 { "SEQ_256K", 1, 1, &umr_bitfield_default },
	 { "SEQ_ODDEVEN", 2, 2, &umr_bitfield_default },
	 { "SEQ_CHAIN", 3, 3, &umr_bitfield_default },
};
static struct umr_bitfield ixCRT00[] = {
	 { "H_TOTAL", 0, 7, &umr_bitfield_default },
};
static struct umr_bitfield ixCRT01[] = {
	 { "H_DISP_END", 0, 7, &umr_bitfield_default },
};
static struct umr_bitfield ixCRT02[] = {
	 { "H_BLANK_START", 0, 7, &umr_bitfield_default },
};
static struct umr_bitfield ixCRT03[] = {
	 { "H_BLANK_END", 0, 4, &umr_bitfield_default },
	 { "H_DE_SKEW", 5, 6, &umr_bitfield_default },
	 { "CR10CR11_R_DIS_B", 7, 7, &umr_bitfield_default },
};
static struct umr_bitfield ixCRT04[] = {
	 { "H_SYNC_START", 0, 7, &umr_bitfield_default },
};
static struct umr_bitfield ixCRT05[] = {
	 { "H_SYNC_END", 0, 4, &umr_bitfield_default },
	 { "H_SYNC_SKEW", 5, 6, &umr_bitfield_default },
	 { "H_BLANK_END_B5", 7, 7, &umr_bitfield_default },
};
static struct umr_bitfield ixCRT06[] = {
	 { "V_TOTAL", 0, 7, &umr_bitfield_default },
};
static struct umr_bitfield ixCRT07[] = {
	 { "V_TOTAL_B8", 0, 0, &umr_bitfield_default },
	 { "V_DISP_END_B8", 1, 1, &umr_bitfield_default },
	 { "V_SYNC_START_B8", 2, 2, &umr_bitfield_default },
	 { "V_BLANK_START_B8", 3, 3, &umr_bitfield_default },
	 { "LINE_CMP_B8", 4, 4, &umr_bitfield_default },
	 { "V_TOTAL_B9", 5, 5, &umr_bitfield_default },
	 { "V_DISP_END_B9", 6, 6, &umr_bitfield_default },
	 { "V_SYNC_START_B9", 7, 7, &umr_bitfield_default },
};
static struct umr_bitfield ixCRT08[] = {
	 { "ROW_SCAN_START", 0, 4, &umr_bitfield_default },
	 { "BYTE_PAN", 5, 6, &umr_bitfield_default },
};
static struct umr_bitfield ixCRT09[] = {
	 { "MAX_ROW_SCAN", 0, 4, &umr_bitfield_default },
	 { "V_BLANK_START_B9", 5, 5, &umr_bitfield_default },
	 { "LINE_CMP_B9", 6, 6, &umr_bitfield_default },
	 { "DOUBLE_CHAR_HEIGHT", 7, 7, &umr_bitfield_default },
};
static struct umr_bitfield ixCRT0A[] = {
	 { "CURSOR_START", 0, 4, &umr_bitfield_default },
	 { "CURSOR_DISABLE", 5, 5, &umr_bitfield_default },
};
static struct umr_bitfield ixCRT0B[] = {
	 { "CURSOR_END", 0, 4, &umr_bitfield_default },
	 { "CURSOR_SKEW", 5, 6, &umr_bitfield_default },
};
static struct umr_bitfield ixCRT0C[] = {
	 { "DISP_START", 0, 7, &umr_bitfield_default },
};
static struct umr_bitfield ixCRT0D[] = {
	 { "DISP_START", 0, 7, &umr_bitfield_default },
};
static struct umr_bitfield ixCRT0E[] = {
	 { "CURSOR_LOC_HI", 0, 7, &umr_bitfield_default },
};
static struct umr_bitfield ixCRT0F[] = {
	 { "CURSOR_LOC_LO", 0, 7, &umr_bitfield_default },
};
static struct umr_bitfield ixCRT10[] = {
	 { "V_SYNC_START", 0, 7, &umr_bitfield_default },
};
static struct umr_bitfield ixCRT11[] = {
	 { "V_SYNC_END", 0, 3, &umr_bitfield_default },
	 { "V_INTR_CLR", 4, 4, &umr_bitfield_default },
	 { "V_INTR_EN", 5, 5, &umr_bitfield_default },
	 { "SEL5_REFRESH_CYC", 6, 6, &umr_bitfield_default },
	 { "C0T7_WR_ONLY", 7, 7, &umr_bitfield_default },
};
static struct umr_bitfield ixCRT12[] = {
	 { "V_DISP_END", 0, 7, &umr_bitfield_default },
};
static struct umr_bitfield ixCRT13[] = {
	 { "DISP_PITCH", 0, 7, &umr_bitfield_default },
};
static struct umr_bitfield ixCRT14[] = {
	 { "UNDRLN_LOC", 0, 4, &umr_bitfield_default },
	 { "ADDR_CNT_BY4", 5, 5, &umr_bitfield_default },
	 { "DOUBLE_WORD", 6, 6, &umr_bitfield_default },
};
static struct umr_bitfield ixCRT15[] = {
	 { "V_BLANK_START", 0, 7, &umr_bitfield_default },
};
static struct umr_bitfield ixCRT16[] = {
	 { "V_BLANK_END", 0, 7, &umr_bitfield_default },
};
static struct umr_bitfield ixCRT17[] = {
	 { "RA0_AS_A13B", 0, 0, &umr_bitfield_default },
	 { "RA1_AS_A14B", 1, 1, &umr_bitfield_default },
	 { "VCOUNT_BY2", 2, 2, &umr_bitfield_default },
	 { "ADDR_CNT_BY2", 3, 3, &umr_bitfield_default },
	 { "WRAP_A15TOA0", 5, 5, &umr_bitfield_default },
	 { "BYTE_MODE", 6, 6, &umr_bitfield_default },
	 { "CRTC_SYNC_EN", 7, 7, &umr_bitfield_default },
};
static struct umr_bitfield ixCRT18[] = {
	 { "LINE_CMP", 0, 7, &umr_bitfield_default },
};
static struct umr_bitfield ixCRT1E[] = {
	 { "GRPH_DEC_RD1", 1, 1, &umr_bitfield_default },
};
static struct umr_bitfield ixCRT1F[] = {
	 { "GRPH_DEC_RD0", 0, 7, &umr_bitfield_default },
};
static struct umr_bitfield ixCRT22[] = {
	 { "GRPH_LATCH_DATA", 0, 7, &umr_bitfield_default },
};
static struct umr_bitfield ixGRA00[] = {
	 { "GRPH_SET_RESET0", 0, 0, &umr_bitfield_default },
	 { "GRPH_SET_RESET1", 1, 1, &umr_bitfield_default },
	 { "GRPH_SET_RESET2", 2, 2, &umr_bitfield_default },
	 { "GRPH_SET_RESET3", 3, 3, &umr_bitfield_default },
};
static struct umr_bitfield ixGRA01[] = {
	 { "GRPH_SET_RESET_ENA0", 0, 0, &umr_bitfield_default },
	 { "GRPH_SET_RESET_ENA1", 1, 1, &umr_bitfield_default },
	 { "GRPH_SET_RESET_ENA2", 2, 2, &umr_bitfield_default },
	 { "GRPH_SET_RESET_ENA3", 3, 3, &umr_bitfield_default },
};
static struct umr_bitfield ixGRA02[] = {
	 { "GRPH_CCOMP", 0, 3, &umr_bitfield_default },
};
static struct umr_bitfield ixGRA03[] = {
	 { "GRPH_ROTATE", 0, 2, &umr_bitfield_default },
	 { "GRPH_FN_SEL", 3, 4, &umr_bitfield_default },
};
static struct umr_bitfield ixGRA04[] = {
	 { "GRPH_RMAP", 0, 1, &umr_bitfield_default },
};
static struct umr_bitfield ixGRA05[] = {
	 { "GRPH_WRITE_MODE", 0, 1, &umr_bitfield_default },
	 { "GRPH_READ1", 3, 3, &umr_bitfield_default },
	 { "CGA_ODDEVEN", 4, 4, &umr_bitfield_default },
	 { "GRPH_OES", 5, 5, &umr_bitfield_default },
	 { "GRPH_PACK", 6, 6, &umr_bitfield_default },
};
static struct umr_bitfield ixGRA06[] = {
	 { "GRPH_GRAPHICS", 0, 0, &umr_bitfield_default },
	 { "GRPH_ODDEVEN", 1, 1, &umr_bitfield_default },
	 { "GRPH_ADRSEL", 2, 3, &umr_bitfield_default },
};
static struct umr_bitfield ixGRA07[] = {
	 { "GRPH_XCARE0", 0, 0, &umr_bitfield_default },
	 { "GRPH_XCARE1", 1, 1, &umr_bitfield_default },
	 { "GRPH_XCARE2", 2, 2, &umr_bitfield_default },
	 { "GRPH_XCARE3", 3, 3, &umr_bitfield_default },
};
static struct umr_bitfield ixGRA08[] = {
	 { "GRPH_BMSK", 0, 7, &umr_bitfield_default },
};
static struct umr_bitfield ixATTR00[] = {
	 { "ATTR_PAL", 0, 5, &umr_bitfield_default },
};
static struct umr_bitfield ixATTR01[] = {
	 { "ATTR_PAL", 0, 5, &umr_bitfield_default },
};
static struct umr_bitfield ixATTR02[] = {
	 { "ATTR_PAL", 0, 5, &umr_bitfield_default },
};
static struct umr_bitfield ixATTR03[] = {
	 { "ATTR_PAL", 0, 5, &umr_bitfield_default },
};
static struct umr_bitfield ixATTR04[] = {
	 { "ATTR_PAL", 0, 5, &umr_bitfield_default },
};
static struct umr_bitfield ixATTR05[] = {
	 { "ATTR_PAL", 0, 5, &umr_bitfield_default },
};
static struct umr_bitfield ixATTR06[] = {
	 { "ATTR_PAL", 0, 5, &umr_bitfield_default },
};
static struct umr_bitfield ixATTR07[] = {
	 { "ATTR_PAL", 0, 5, &umr_bitfield_default },
};
static struct umr_bitfield ixATTR08[] = {
	 { "ATTR_PAL", 0, 5, &umr_bitfield_default },
};
static struct umr_bitfield ixATTR09[] = {
	 { "ATTR_PAL", 0, 5, &umr_bitfield_default },
};
static struct umr_bitfield ixATTR0A[] = {
	 { "ATTR_PAL", 0, 5, &umr_bitfield_default },
};
static struct umr_bitfield ixATTR0B[] = {
	 { "ATTR_PAL", 0, 5, &umr_bitfield_default },
};
static struct umr_bitfield ixATTR0C[] = {
	 { "ATTR_PAL", 0, 5, &umr_bitfield_default },
};
static struct umr_bitfield ixATTR0D[] = {
	 { "ATTR_PAL", 0, 5, &umr_bitfield_default },
};
static struct umr_bitfield ixATTR0E[] = {
	 { "ATTR_PAL", 0, 5, &umr_bitfield_default },
};
static struct umr_bitfield ixATTR0F[] = {
	 { "ATTR_PAL", 0, 5, &umr_bitfield_default },
};
static struct umr_bitfield ixATTR10[] = {
	 { "ATTR_GRPH_MODE", 0, 0, &umr_bitfield_default },
	 { "ATTR_MONO_EN", 1, 1, &umr_bitfield_default },
	 { "ATTR_LGRPH_EN", 2, 2, &umr_bitfield_default },
	 { "ATTR_BLINK_EN", 3, 3, &umr_bitfield_default },
	 { "ATTR_PANTOPONLY", 5, 5, &umr_bitfield_default },
	 { "ATTR_PCLKBY2", 6, 6, &umr_bitfield_default },
	 { "ATTR_CSEL_EN", 7, 7, &umr_bitfield_default },
};
static struct umr_bitfield ixATTR11[] = {
	 { "ATTR_OVSC", 0, 7, &umr_bitfield_default },
};
static struct umr_bitfield ixATTR12[] = {
	 { "ATTR_MAP_EN", 0, 3, &umr_bitfield_default },
	 { "ATTR_VSMUX", 4, 5, &umr_bitfield_default },
};
static struct umr_bitfield ixATTR13[] = {
	 { "ATTR_PPAN", 0, 3, &umr_bitfield_default },
};
static struct umr_bitfield ixATTR14[] = {
	 { "ATTR_CSEL1", 0, 1, &umr_bitfield_default },
	 { "ATTR_CSEL2", 2, 3, &umr_bitfield_default },
};
static struct umr_bitfield ixAZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT[] = {
	 { "NUMBER_OF_CHANNELS", 0, 3, &umr_bitfield_default },
	 { "BITS_PER_SAMPLE", 4, 6, &umr_bitfield_default },
	 { "SAMPLE_BASE_DIVISOR", 8, 10, &umr_bitfield_default },
	 { "SAMPLE_BASE_MULTIPLE", 11, 13, &umr_bitfield_default },
	 { "SAMPLE_BASE_RATE", 14, 14, &umr_bitfield_default },
	 { "STREAM_TYPE", 15, 15, &umr_bitfield_default },
	 { "STREAM_TYPE_R", 15, 15, &umr_bitfield_default },
};
static struct umr_bitfield ixAZALIA_F2_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID[] = {
	 { "CHANNEL_ID", 0, 3, &umr_bitfield_default },
	 { "STREAM_ID", 4, 7, &umr_bitfield_default },
};
static struct umr_bitfield ixAZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER[] = {
	 { "DIGEN", 0, 0, &umr_bitfield_default },
	 { "V", 1, 1, &umr_bitfield_default },
	 { "VCFG", 2, 2, &umr_bitfield_default },
	 { "PRE", 3, 3, &umr_bitfield_default },
	 { "COPY", 4, 4, &umr_bitfield_default },
	 { "NON_AUDIO", 5, 5, &umr_bitfield_default },
	 { "PRO", 6, 6, &umr_bitfield_default },
	 { "L", 7, 7, &umr_bitfield_default },
	 { "CC", 8, 14, &umr_bitfield_default },
	 { "KEEPALIVE", 23, 23, &umr_bitfield_default },
};
static struct umr_bitfield ixAZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_2[] = {
	 { "CC", 0, 6, &umr_bitfield_default },
};
static struct umr_bitfield ixAZALIA_F2_CODEC_CONVERTER_STRIPE_CONTROL[] = {
	 { "STRIPE_CONTROL", 0, 1, &umr_bitfield_default },
	 { "STRIPE_CAPABILITY", 20, 22, &umr_bitfield_default },
};
static struct umr_bitfield ixAZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3[] = {
	 { "KEEPALIVE", 7, 7, &umr_bitfield_default },
};
static struct umr_bitfield ixAZALIA_F2_CODEC_CONVERTER_CONTROL_RAMP_RATE[] = {
	 { "RAMP_RATE", 0, 7, &umr_bitfield_default },
};
static struct umr_bitfield ixAZALIA_F2_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING[] = {
	 { "PRESENTATION_TIME_EMBEDDING_ENABLE", 0, 0, &umr_bitfield_default },
	 { "PRESENTATION_TIME_OFFSET_CHANGED", 1, 1, &umr_bitfield_default },
	 { "PRESENTATION_TIME_EMBEDDING_GROUP", 4, 6, &umr_bitfield_default },
};
static struct umr_bitfield ixAZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES[] = {
	 { "AUDIO_CHANNEL_CAPABILITIES", 0, 0, &umr_bitfield_default },
	 { "INPUT_AMPLIFIER_PRESENT", 1, 1, &umr_bitfield_default },
	 { "OUTPUT_AMPLIFIER_PRESENT", 2, 2, &umr_bitfield_default },
	 { "AMPLIFIER_PARAMETER_OVERRIDE", 3, 3, &umr_bitfield_default },
	 { "FORMAT_OVERRIDE", 4, 4, &umr_bitfield_default },
	 { "STRIPE", 5, 5, &umr_bitfield_default },
	 { "PROCESSING_WIDGET", 6, 6, &umr_bitfield_default },
	 { "UNSOLICITED_RESPONSE_CAPABILITY", 7, 7, &umr_bitfield_default },
	 { "CONNECTION_LIST", 8, 8, &umr_bitfield_default },
	 { "DIGITAL", 9, 9, &umr_bitfield_default },
	 { "POWER_CONTROL", 10, 10, &umr_bitfield_default },
	 { "LR_SWAP", 11, 11, &umr_bitfield_default },
	 { "AUDIO_WIDGET_CAPABILITIES_DELAY", 16, 19, &umr_bitfield_default },
	 { "TYPE", 20, 23, &umr_bitfield_default },
};
static struct umr_bitfield ixAZALIA_F2_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES[] = {
	 { "AUDIO_RATE_CAPABILITIES", 0, 11, &umr_bitfield_default },
	 { "AUDIO_BIT_CAPABILITIES", 16, 20, &umr_bitfield_default },
};
static struct umr_bitfield ixAZALIA_F2_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS[] = {
	 { "STREAM_FORMATS", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONNECTION_LIST_ENTRY[] = {
	 { "CONNECTION_LIST_ENTRY", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixAZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL[] = {
	 { "OUT_ENABLE", 6, 6, &umr_bitfield_default },
};
static struct umr_bitfield ixAZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE[] = {
	 { "TAG", 0, 5, &umr_bitfield_default },
	 { "ENABLE", 7, 7, &umr_bitfield_default },
};
static struct umr_bitfield ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE[] = {
	 { "IMPEDANCE_SENSE", 0, 30, &umr_bitfield_default },
	 { "PRESENCE_DETECT", 31, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT[] = {
	 { "SEQUENCE", 0, 3, &umr_bitfield_default },
	 { "DEFAULT_ASSOCIATION", 4, 7, &umr_bitfield_default },
	 { "MISC", 8, 11, &umr_bitfield_default },
	 { "COLOR", 12, 15, &umr_bitfield_default },
	 { "CONNECTION_TYPE", 16, 19, &umr_bitfield_default },
	 { "DEFAULT_DEVICE", 20, 23, &umr_bitfield_default },
	 { "LOCATION", 24, 29, &umr_bitfield_default },
	 { "PORT_CONNECTIVITY", 30, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2[] = {
	 { "MISC", 0, 3, &umr_bitfield_default },
	 { "COLOR", 4, 7, &umr_bitfield_default },
};
static struct umr_bitfield ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3[] = {
	 { "CONNECTION_TYPE", 0, 3, &umr_bitfield_default },
	 { "DEFAULT_DEVICE", 4, 7, &umr_bitfield_default },
};
static struct umr_bitfield ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4[] = {
	 { "LOCATION", 0, 5, &umr_bitfield_default },
	 { "PORT_CONNECTIVITY", 6, 7, &umr_bitfield_default },
};
static struct umr_bitfield ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION[] = {
	 { "SPEAKER_ALLOCATION", 0, 6, &umr_bitfield_default },
	 { "HDMI_CONNECTION", 8, 8, &umr_bitfield_default },
	 { "DP_CONNECTION", 9, 9, &umr_bitfield_default },
	 { "EXTRA_CONNECTION_INFO", 10, 15, &umr_bitfield_default },
};
static struct umr_bitfield ixAZALIA_F2_CODEC_PIN_CONTROL_CHANNEL_ALLOCATION[] = {
	 { "CHANNEL_ALLOCATION", 0, 7, &umr_bitfield_default },
};
static struct umr_bitfield ixAZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO[] = {
	 { "LFE_PLAYBACK_LEVEL", 0, 1, &umr_bitfield_default },
	 { "LEVEL_SHIFT", 3, 6, &umr_bitfield_default },
	 { "DOWN_MIX_INHIBIT", 7, 7, &umr_bitfield_default },
};
static struct umr_bitfield ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR[] = {
	 { "MAX_CHANNELS", 0, 2, &umr_bitfield_default },
	 { "FORMAT_CODE", 3, 6, &umr_bitfield_default },
	 { "SUPPORTED_FREQUENCIES", 8, 15, &umr_bitfield_default },
	 { "DESCRIPTOR_BYTE_2", 16, 23, &umr_bitfield_default },
	 { "SUPPORTED_FREQUENCIES_STEREO", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_DATA[] = {
	 { "DESCRIPTOR", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE[] = {
	 { "MULTICHANNEL01_ENABLE", 0, 0, &umr_bitfield_default },
	 { "MULTICHANNEL01_MUTE", 1, 1, &umr_bitfield_default },
	 { "MULTICHANNEL01_CHANNEL_ID", 4, 7, &umr_bitfield_default },
};
static struct umr_bitfield ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE[] = {
	 { "MULTICHANNEL23_ENABLE", 0, 0, &umr_bitfield_default },
	 { "MULTICHANNEL23_MUTE", 1, 1, &umr_bitfield_default },
	 { "MULTICHANNEL23_CHANNEL_ID", 4, 7, &umr_bitfield_default },
};
static struct umr_bitfield ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE[] = {
	 { "MULTICHANNEL45_ENABLE", 0, 0, &umr_bitfield_default },
	 { "MULTICHANNEL45_MUTE", 1, 1, &umr_bitfield_default },
	 { "MULTICHANNEL45_CHANNEL_ID", 4, 7, &umr_bitfield_default },
};
static struct umr_bitfield ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE[] = {
	 { "MULTICHANNEL67_ENABLE", 0, 0, &umr_bitfield_default },
	 { "MULTICHANNEL67_MUTE", 1, 1, &umr_bitfield_default },
	 { "MULTICHANNEL67_CHANNEL_ID", 4, 7, &umr_bitfield_default },
};
static struct umr_bitfield ixAZALIA_F2_CODEC_PIN_CONTROL_LIPSYNC[] = {
	 { "VIDEO_LIPSYNC", 0, 7, &umr_bitfield_default },
	 { "AUDIO_LIPSYNC", 8, 15, &umr_bitfield_default },
};
static struct umr_bitfield ixAZALIA_F2_CODEC_PIN_CONTROL_HBR[] = {
	 { "HBR_CAPABLE", 0, 0, &umr_bitfield_default },
	 { "HBR_ENABLE", 4, 4, &umr_bitfield_default },
};
static struct umr_bitfield ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_INDEX[] = {
	 { "SINK_INFO_INDEX", 0, 7, &umr_bitfield_default },
};
static struct umr_bitfield ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_DATA[] = {
	 { "SINK_DATA", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE[] = {
	 { "MULTICHANNEL1_ENABLE", 0, 0, &umr_bitfield_default },
	 { "MULTICHANNEL1_MUTE", 1, 1, &umr_bitfield_default },
	 { "MULTICHANNEL1_CHANNEL_ID", 4, 7, &umr_bitfield_default },
};
static struct umr_bitfield ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE[] = {
	 { "MULTICHANNEL3_ENABLE", 0, 0, &umr_bitfield_default },
	 { "MULTICHANNEL3_MUTE", 1, 1, &umr_bitfield_default },
	 { "MULTICHANNEL3_CHANNEL_ID", 4, 7, &umr_bitfield_default },
};
static struct umr_bitfield ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE[] = {
	 { "MULTICHANNEL5_ENABLE", 0, 0, &umr_bitfield_default },
	 { "MULTICHANNEL5_MUTE", 1, 1, &umr_bitfield_default },
	 { "MULTICHANNEL5_CHANNEL_ID", 4, 7, &umr_bitfield_default },
};
static struct umr_bitfield ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE[] = {
	 { "MULTICHANNEL7_ENABLE", 0, 0, &umr_bitfield_default },
	 { "MULTICHANNEL7_MUTE", 1, 1, &umr_bitfield_default },
	 { "MULTICHANNEL7_CHANNEL_ID", 4, 7, &umr_bitfield_default },
};
static struct umr_bitfield ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE[] = {
	 { "MULTICHANNEL_MODE", 0, 0, &umr_bitfield_default },
};
static struct umr_bitfield ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_0[] = {
	 { "IEC_60958_CS_MODE", 0, 1, &umr_bitfield_default },
	 { "IEC_60958_CS_SOURCE_NUMBER", 2, 5, &umr_bitfield_default },
};
static struct umr_bitfield ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1[] = {
	 { "IEC_60958_CS_CLOCK_ACCURACY", 0, 1, &umr_bitfield_default },
	 { "IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN", 2, 2, &umr_bitfield_default },
	 { "IEC_60958_CS_WORD_LENGTH", 3, 6, &umr_bitfield_default },
	 { "IEC_60958_CS_WORD_LENGTH_OVRRD_EN", 7, 7, &umr_bitfield_default },
};
static struct umr_bitfield ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_2[] = {
	 { "IEC_60958_CS_SAMPLING_FREQUENCY", 0, 5, &umr_bitfield_default },
	 { "IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN", 6, 6, &umr_bitfield_default },
};
static struct umr_bitfield ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_3[] = {
	 { "IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY", 0, 3, &umr_bitfield_default },
	 { "IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN", 4, 4, &umr_bitfield_default },
};
static struct umr_bitfield ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4[] = {
	 { "IEC_60958_CS_SAMPLING_FREQUENCY_COEFF", 0, 3, &umr_bitfield_default },
	 { "IEC_60958_CS_MPEG_SURROUND_INFO", 4, 4, &umr_bitfield_default },
	 { "IEC_60958_CS_CGMS_A", 5, 6, &umr_bitfield_default },
	 { "IEC_60958_CS_CGMS_A_VALID", 7, 7, &umr_bitfield_default },
};
static struct umr_bitfield ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_5[] = {
	 { "IEC_60958_CS_CHANNEL_NUMBER_L", 0, 3, &umr_bitfield_default },
	 { "IEC_60958_CS_CHANNEL_NUMBER_R", 4, 7, &umr_bitfield_default },
};
static struct umr_bitfield ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_6[] = {
	 { "IEC_60958_CS_CHANNEL_NUMBER_2", 0, 3, &umr_bitfield_default },
	 { "IEC_60958_CS_CHANNEL_NUMBER_3", 4, 7, &umr_bitfield_default },
};
static struct umr_bitfield ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_7[] = {
	 { "IEC_60958_CS_CHANNEL_NUMBER_4", 0, 3, &umr_bitfield_default },
	 { "IEC_60958_CS_CHANNEL_NUMBER_5", 4, 7, &umr_bitfield_default },
};
static struct umr_bitfield ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_8[] = {
	 { "IEC_60958_CS_CHANNEL_NUMBER_6", 0, 3, &umr_bitfield_default },
	 { "IEC_60958_CS_CHANNEL_NUMBER_7", 4, 7, &umr_bitfield_default },
};
static struct umr_bitfield ixAZALIA_F2_CODEC_PIN_ASSOCIATION_INFO[] = {
	 { "ASSOCIATION_INFO", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixAZALIA_F2_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS[] = {
	 { "OUTPUT_ACTIVE", 0, 0, &umr_bitfield_default },
};
static struct umr_bitfield ixAZALIA_F2_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL[] = {
	 { "LPIB_SNAPSHOT_LOCK", 0, 0, &umr_bitfield_default },
	 { "CYCLIC_BUFFER_WRAP_COUNT", 8, 15, &umr_bitfield_default },
};
static struct umr_bitfield ixAZALIA_F2_CODEC_PIN_CONTROL_LPIB[] = {
	 { "LPIB", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixAZALIA_F2_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT[] = {
	 { "LPIB_TIMER_SNAPSHOT", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixAZALIA_F2_CODEC_PIN_CONTROL_CODING_TYPE[] = {
	 { "CODING_TYPE", 0, 7, &umr_bitfield_default },
};
static struct umr_bitfield ixAZALIA_F2_CODEC_PIN_CONTROL_FORMAT_CHANGED[] = {
	 { "FORMAT_CHANGED", 0, 0, &umr_bitfield_default },
	 { "FORMAT_CHANGED_ACK_UR_ENABLE", 1, 1, &umr_bitfield_default },
	 { "FORMAT_CHANGE_REASON", 8, 15, &umr_bitfield_default },
	 { "FORMAT_CHANGE_RESPONSE", 16, 23, &umr_bitfield_default },
};
static struct umr_bitfield ixAZALIA_F2_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION[] = {
	 { "WIRELESS_DISPLAY_IDENTIFICATION", 0, 1, &umr_bitfield_default },
};
static struct umr_bitfield ixAZALIA_F2_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE[] = {
	 { "REMOTE_KEEP_ALIVE_ENABLE", 0, 0, &umr_bitfield_default },
	 { "REMOTE_KEEP_ALIVE_CAPABILITY", 4, 4, &umr_bitfield_default },
};
static struct umr_bitfield ixAZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES[] = {
	 { "AUDIO_CHANNEL_CAPABILITIES", 0, 0, &umr_bitfield_default },
	 { "INPUT_AMPLIFIER_PRESENT", 1, 1, &umr_bitfield_default },
	 { "OUTPUT_AMPLIFIER_PRESENT", 2, 2, &umr_bitfield_default },
	 { "AMPLIFIER_PARAMETER_OVERRIDE", 3, 3, &umr_bitfield_default },
	 { "STRIPE", 5, 5, &umr_bitfield_default },
	 { "PROCESSING_WIDGET", 6, 6, &umr_bitfield_default },
	 { "UNSOLICITED_RESPONSE_CAPABILITY", 7, 7, &umr_bitfield_default },
	 { "CONNECTION_LIST", 8, 8, &umr_bitfield_default },
	 { "DIGITAL", 9, 9, &umr_bitfield_default },
	 { "POWER_CONTROL", 10, 10, &umr_bitfield_default },
	 { "LR_SWAP", 11, 11, &umr_bitfield_default },
	 { "AUDIO_WIDGET_CAPABILITIES_DELAY", 16, 19, &umr_bitfield_default },
	 { "TYPE", 20, 23, &umr_bitfield_default },
};
static struct umr_bitfield ixAZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES[] = {
	 { "IMPEDANCE_SENSE_CAPABLE", 0, 0, &umr_bitfield_default },
	 { "TRIGGER_REQUIRED", 1, 1, &umr_bitfield_default },
	 { "JACK_DETECTION_CAPABILITY", 2, 2, &umr_bitfield_default },
	 { "HEADPHONE_DRIVE_CAPABLE", 3, 3, &umr_bitfield_default },
	 { "OUTPUT_CAPABLE", 4, 4, &umr_bitfield_default },
	 { "INPUT_CAPABLE", 5, 5, &umr_bitfield_default },
	 { "BALANCED_I_O_PINS", 6, 6, &umr_bitfield_default },
	 { "HDMI", 7, 7, &umr_bitfield_default },
	 { "VREF_CONTROL", 8, 15, &umr_bitfield_default },
	 { "EAPD_CAPABLE", 16, 16, &umr_bitfield_default },
	 { "DP", 24, 24, &umr_bitfield_default },
};
static struct umr_bitfield ixAZALIA_F2_CODEC_PIN_PARAMETER_CONNECTION_LIST_LENGTH[] = {
	 { "CONNECTION_LIST_LENGTH", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixAUDIO_DESCRIPTOR0[] = {
	 { "MAX_CHANNELS", 0, 2, &umr_bitfield_default },
	 { "SUPPORTED_FREQUENCIES", 8, 15, &umr_bitfield_default },
	 { "DESCRIPTOR_BYTE_2", 16, 23, &umr_bitfield_default },
	 { "SUPPORTED_FREQUENCIES_STEREO", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixAUDIO_DESCRIPTOR1[] = {
	 { "MAX_CHANNELS", 0, 2, &umr_bitfield_default },
	 { "SUPPORTED_FREQUENCIES", 8, 15, &umr_bitfield_default },
	 { "DESCRIPTOR_BYTE_2", 16, 23, &umr_bitfield_default },
	 { "SUPPORTED_FREQUENCIES_STEREO", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixAUDIO_DESCRIPTOR2[] = {
	 { "MAX_CHANNELS", 0, 2, &umr_bitfield_default },
	 { "SUPPORTED_FREQUENCIES", 8, 15, &umr_bitfield_default },
	 { "DESCRIPTOR_BYTE_2", 16, 23, &umr_bitfield_default },
	 { "SUPPORTED_FREQUENCIES_STEREO", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixAUDIO_DESCRIPTOR3[] = {
	 { "MAX_CHANNELS", 0, 2, &umr_bitfield_default },
	 { "SUPPORTED_FREQUENCIES", 8, 15, &umr_bitfield_default },
	 { "DESCRIPTOR_BYTE_2", 16, 23, &umr_bitfield_default },
	 { "SUPPORTED_FREQUENCIES_STEREO", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixAUDIO_DESCRIPTOR4[] = {
	 { "MAX_CHANNELS", 0, 2, &umr_bitfield_default },
	 { "SUPPORTED_FREQUENCIES", 8, 15, &umr_bitfield_default },
	 { "DESCRIPTOR_BYTE_2", 16, 23, &umr_bitfield_default },
	 { "SUPPORTED_FREQUENCIES_STEREO", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixAUDIO_DESCRIPTOR5[] = {
	 { "MAX_CHANNELS", 0, 2, &umr_bitfield_default },
	 { "SUPPORTED_FREQUENCIES", 8, 15, &umr_bitfield_default },
	 { "DESCRIPTOR_BYTE_2", 16, 23, &umr_bitfield_default },
	 { "SUPPORTED_FREQUENCIES_STEREO", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixAUDIO_DESCRIPTOR6[] = {
	 { "MAX_CHANNELS", 0, 2, &umr_bitfield_default },
	 { "SUPPORTED_FREQUENCIES", 8, 15, &umr_bitfield_default },
	 { "DESCRIPTOR_BYTE_2", 16, 23, &umr_bitfield_default },
	 { "SUPPORTED_FREQUENCIES_STEREO", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixAUDIO_DESCRIPTOR7[] = {
	 { "MAX_CHANNELS", 0, 2, &umr_bitfield_default },
	 { "SUPPORTED_FREQUENCIES", 8, 15, &umr_bitfield_default },
	 { "DESCRIPTOR_BYTE_2", 16, 23, &umr_bitfield_default },
	 { "SUPPORTED_FREQUENCIES_STEREO", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixAUDIO_DESCRIPTOR8[] = {
	 { "MAX_CHANNELS", 0, 2, &umr_bitfield_default },
	 { "SUPPORTED_FREQUENCIES", 8, 15, &umr_bitfield_default },
	 { "DESCRIPTOR_BYTE_2", 16, 23, &umr_bitfield_default },
	 { "SUPPORTED_FREQUENCIES_STEREO", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixAUDIO_DESCRIPTOR9[] = {
	 { "MAX_CHANNELS", 0, 2, &umr_bitfield_default },
	 { "SUPPORTED_FREQUENCIES", 8, 15, &umr_bitfield_default },
	 { "DESCRIPTOR_BYTE_2", 16, 23, &umr_bitfield_default },
	 { "SUPPORTED_FREQUENCIES_STEREO", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixAUDIO_DESCRIPTOR10[] = {
	 { "MAX_CHANNELS", 0, 2, &umr_bitfield_default },
	 { "SUPPORTED_FREQUENCIES", 8, 15, &umr_bitfield_default },
	 { "DESCRIPTOR_BYTE_2", 16, 23, &umr_bitfield_default },
	 { "SUPPORTED_FREQUENCIES_STEREO", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixAUDIO_DESCRIPTOR11[] = {
	 { "MAX_CHANNELS", 0, 2, &umr_bitfield_default },
	 { "SUPPORTED_FREQUENCIES", 8, 15, &umr_bitfield_default },
	 { "DESCRIPTOR_BYTE_2", 16, 23, &umr_bitfield_default },
	 { "SUPPORTED_FREQUENCIES_STEREO", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixAUDIO_DESCRIPTOR12[] = {
	 { "MAX_CHANNELS", 0, 2, &umr_bitfield_default },
	 { "SUPPORTED_FREQUENCIES", 8, 15, &umr_bitfield_default },
	 { "DESCRIPTOR_BYTE_2", 16, 23, &umr_bitfield_default },
	 { "SUPPORTED_FREQUENCIES_STEREO", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixAUDIO_DESCRIPTOR13[] = {
	 { "MAX_CHANNELS", 0, 2, &umr_bitfield_default },
	 { "SUPPORTED_FREQUENCIES", 8, 15, &umr_bitfield_default },
	 { "DESCRIPTOR_BYTE_2", 16, 23, &umr_bitfield_default },
	 { "SUPPORTED_FREQUENCIES_STEREO", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixAZALIA_F2_CODEC_PIN_CONTROL_MANUFACTURER_ID[] = {
	 { "MANUFACTURER_ID", 0, 15, &umr_bitfield_default },
};
static struct umr_bitfield ixAZALIA_F2_CODEC_PIN_CONTROL_PRODUCT_ID[] = {
	 { "PRODUCT_ID", 0, 15, &umr_bitfield_default },
};
static struct umr_bitfield ixAZALIA_F2_CODEC_PIN_CONTROL_SINK_DESCRIPTION_LEN[] = {
	 { "SINK_DESCRIPTION_LEN", 0, 7, &umr_bitfield_default },
};
static struct umr_bitfield ixAZALIA_F2_CODEC_PIN_CONTROL_PORTID0[] = {
	 { "PORTID", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixAZALIA_F2_CODEC_PIN_CONTROL_PORTID1[] = {
	 { "PORTID", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixSINK_DESCRIPTION0[] = {
	 { "DESCRIPTION", 0, 7, &umr_bitfield_default },
};
static struct umr_bitfield ixSINK_DESCRIPTION1[] = {
	 { "DESCRIPTION", 0, 7, &umr_bitfield_default },
};
static struct umr_bitfield ixSINK_DESCRIPTION2[] = {
	 { "DESCRIPTION", 0, 7, &umr_bitfield_default },
};
static struct umr_bitfield ixSINK_DESCRIPTION3[] = {
	 { "DESCRIPTION", 0, 7, &umr_bitfield_default },
};
static struct umr_bitfield ixSINK_DESCRIPTION4[] = {
	 { "DESCRIPTION", 0, 7, &umr_bitfield_default },
};
static struct umr_bitfield ixSINK_DESCRIPTION5[] = {
	 { "DESCRIPTION", 0, 7, &umr_bitfield_default },
};
static struct umr_bitfield ixSINK_DESCRIPTION6[] = {
	 { "DESCRIPTION", 0, 7, &umr_bitfield_default },
};
static struct umr_bitfield ixSINK_DESCRIPTION7[] = {
	 { "DESCRIPTION", 0, 7, &umr_bitfield_default },
};
static struct umr_bitfield ixSINK_DESCRIPTION8[] = {
	 { "DESCRIPTION", 0, 7, &umr_bitfield_default },
};
static struct umr_bitfield ixSINK_DESCRIPTION9[] = {
	 { "DESCRIPTION", 0, 7, &umr_bitfield_default },
};
static struct umr_bitfield ixSINK_DESCRIPTION10[] = {
	 { "DESCRIPTION", 0, 7, &umr_bitfield_default },
};
static struct umr_bitfield ixSINK_DESCRIPTION11[] = {
	 { "DESCRIPTION", 0, 7, &umr_bitfield_default },
};
static struct umr_bitfield ixSINK_DESCRIPTION12[] = {
	 { "DESCRIPTION", 0, 7, &umr_bitfield_default },
};
static struct umr_bitfield ixSINK_DESCRIPTION13[] = {
	 { "DESCRIPTION", 0, 7, &umr_bitfield_default },
};
static struct umr_bitfield ixSINK_DESCRIPTION14[] = {
	 { "DESCRIPTION", 0, 7, &umr_bitfield_default },
};
static struct umr_bitfield ixSINK_DESCRIPTION15[] = {
	 { "DESCRIPTION", 0, 7, &umr_bitfield_default },
};
static struct umr_bitfield ixSINK_DESCRIPTION16[] = {
	 { "DESCRIPTION", 0, 7, &umr_bitfield_default },
};
static struct umr_bitfield ixSINK_DESCRIPTION17[] = {
	 { "DESCRIPTION", 0, 7, &umr_bitfield_default },
};
static struct umr_bitfield ixAZALIA_INPUT_CRC0_CHANNEL0[] = {
	 { "INPUT_CRC_CHANNEL0", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixAZALIA_INPUT_CRC0_CHANNEL1[] = {
	 { "INPUT_CRC_CHANNEL1", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixAZALIA_INPUT_CRC0_CHANNEL2[] = {
	 { "INPUT_CRC_CHANNEL2", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixAZALIA_INPUT_CRC0_CHANNEL3[] = {
	 { "INPUT_CRC_CHANNEL3", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixAZALIA_INPUT_CRC0_CHANNEL4[] = {
	 { "INPUT_CRC_CHANNEL4", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixAZALIA_INPUT_CRC0_CHANNEL5[] = {
	 { "INPUT_CRC_CHANNEL5", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixAZALIA_INPUT_CRC0_CHANNEL6[] = {
	 { "INPUT_CRC_CHANNEL6", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixAZALIA_INPUT_CRC0_CHANNEL7[] = {
	 { "INPUT_CRC_CHANNEL7", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixAZALIA_INPUT_CRC1_CHANNEL0[] = {
	 { "INPUT_CRC_CHANNEL0", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixAZALIA_INPUT_CRC1_CHANNEL1[] = {
	 { "INPUT_CRC_CHANNEL1", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixAZALIA_INPUT_CRC1_CHANNEL2[] = {
	 { "INPUT_CRC_CHANNEL2", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixAZALIA_INPUT_CRC1_CHANNEL3[] = {
	 { "INPUT_CRC_CHANNEL3", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixAZALIA_INPUT_CRC1_CHANNEL4[] = {
	 { "INPUT_CRC_CHANNEL4", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixAZALIA_INPUT_CRC1_CHANNEL5[] = {
	 { "INPUT_CRC_CHANNEL5", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixAZALIA_INPUT_CRC1_CHANNEL6[] = {
	 { "INPUT_CRC_CHANNEL6", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixAZALIA_INPUT_CRC1_CHANNEL7[] = {
	 { "INPUT_CRC_CHANNEL7", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixAZALIA_CRC0_CHANNEL0[] = {
	 { "CRC_CHANNEL0", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixAZALIA_CRC0_CHANNEL1[] = {
	 { "CRC_CHANNEL1", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixAZALIA_CRC0_CHANNEL2[] = {
	 { "CRC_CHANNEL2", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixAZALIA_CRC0_CHANNEL3[] = {
	 { "CRC_CHANNEL3", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixAZALIA_CRC0_CHANNEL4[] = {
	 { "CRC_CHANNEL4", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixAZALIA_CRC0_CHANNEL5[] = {
	 { "CRC_CHANNEL5", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixAZALIA_CRC0_CHANNEL6[] = {
	 { "CRC_CHANNEL6", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixAZALIA_CRC0_CHANNEL7[] = {
	 { "CRC_CHANNEL7", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixAZALIA_CRC1_CHANNEL0[] = {
	 { "CRC_CHANNEL0", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixAZALIA_CRC1_CHANNEL1[] = {
	 { "CRC_CHANNEL1", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixAZALIA_CRC1_CHANNEL2[] = {
	 { "CRC_CHANNEL2", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixAZALIA_CRC1_CHANNEL3[] = {
	 { "CRC_CHANNEL3", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixAZALIA_CRC1_CHANNEL4[] = {
	 { "CRC_CHANNEL4", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixAZALIA_CRC1_CHANNEL5[] = {
	 { "CRC_CHANNEL5", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixAZALIA_CRC1_CHANNEL6[] = {
	 { "CRC_CHANNEL6", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixAZALIA_CRC1_CHANNEL7[] = {
	 { "CRC_CHANNEL7", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixAZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT[] = {
	 { "NUMBER_OF_CHANNELS", 0, 3, &umr_bitfield_default },
	 { "BITS_PER_SAMPLE", 4, 6, &umr_bitfield_default },
	 { "SAMPLE_BASE_DIVISOR", 8, 10, &umr_bitfield_default },
	 { "SAMPLE_BASE_MULTIPLE", 11, 13, &umr_bitfield_default },
	 { "SAMPLE_BASE_RATE", 14, 14, &umr_bitfield_default },
	 { "STREAM_TYPE", 15, 15, &umr_bitfield_default },
};
static struct umr_bitfield ixAZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID[] = {
	 { "CHANNEL_ID", 0, 3, &umr_bitfield_default },
	 { "STREAM_ID", 4, 7, &umr_bitfield_default },
};
static struct umr_bitfield ixAZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER[] = {
	 { "DIGEN", 0, 0, &umr_bitfield_default },
	 { "V", 1, 1, &umr_bitfield_default },
	 { "VCFG", 2, 2, &umr_bitfield_default },
	 { "PRE", 3, 3, &umr_bitfield_default },
	 { "COPY", 4, 4, &umr_bitfield_default },
	 { "NON_AUDIO", 5, 5, &umr_bitfield_default },
	 { "PRO", 6, 6, &umr_bitfield_default },
	 { "L", 7, 7, &umr_bitfield_default },
	 { "CC", 8, 14, &umr_bitfield_default },
	 { "KEEPALIVE", 23, 23, &umr_bitfield_default },
};
static struct umr_bitfield ixAZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES[] = {
	 { "AUDIO_CHANNEL_CAPABILITIES", 0, 0, &umr_bitfield_default },
	 { "INPUT_AMPLIFIER_PRESENT", 1, 1, &umr_bitfield_default },
	 { "OUTPUT_AMPLIFIER_PRESENT", 2, 2, &umr_bitfield_default },
	 { "AMPLIFIER_PARAMETER_OVERRIDE", 3, 3, &umr_bitfield_default },
	 { "FORMAT_OVERRIDE", 4, 4, &umr_bitfield_default },
	 { "STRIPE", 5, 5, &umr_bitfield_default },
	 { "PROCESSING_WIDGET", 6, 6, &umr_bitfield_default },
	 { "UNSOLICITED_RESPONSE_CAPABILITY", 7, 7, &umr_bitfield_default },
	 { "CONNECTION_LIST", 8, 8, &umr_bitfield_default },
	 { "DIGITAL", 9, 9, &umr_bitfield_default },
	 { "POWER_CONTROL", 10, 10, &umr_bitfield_default },
	 { "LR_SWAP", 11, 11, &umr_bitfield_default },
	 { "AUDIO_WIDGET_CAPABILITIES_DELAY", 16, 19, &umr_bitfield_default },
	 { "TYPE", 20, 23, &umr_bitfield_default },
};
static struct umr_bitfield ixAZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES[] = {
	 { "AUDIO_RATE_CAPABILITIES", 0, 11, &umr_bitfield_default },
	 { "AUDIO_BIT_CAPABILITIES", 16, 20, &umr_bitfield_default },
};
static struct umr_bitfield ixAZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS[] = {
	 { "STREAM_FORMATS", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL[] = {
	 { "IN_ENABLE", 5, 5, &umr_bitfield_default },
};
static struct umr_bitfield ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE[] = {
	 { "TAG", 0, 5, &umr_bitfield_default },
	 { "ENABLE", 7, 7, &umr_bitfield_default },
};
static struct umr_bitfield ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_PIN_SENSE[] = {
	 { "IMPEDANCE_SENSE", 0, 30, &umr_bitfield_default },
	 { "PRESENCE_DETECT", 31, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT[] = {
	 { "SEQUENCE", 0, 3, &umr_bitfield_default },
	 { "DEFAULT_ASSOCIATION", 4, 7, &umr_bitfield_default },
	 { "MISC", 8, 11, &umr_bitfield_default },
	 { "COLOR", 12, 15, &umr_bitfield_default },
	 { "CONNECTION_TYPE", 16, 19, &umr_bitfield_default },
	 { "DEFAULT_DEVICE", 20, 23, &umr_bitfield_default },
	 { "LOCATION", 24, 29, &umr_bitfield_default },
	 { "PORT_CONNECTIVITY", 30, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2[] = {
	 { "MISC", 0, 3, &umr_bitfield_default },
	 { "COLOR", 4, 7, &umr_bitfield_default },
};
static struct umr_bitfield ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3[] = {
	 { "CONNECTION_TYPE", 0, 3, &umr_bitfield_default },
	 { "DEFAULT_DEVICE", 4, 7, &umr_bitfield_default },
};
static struct umr_bitfield ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4[] = {
	 { "LOCATION", 0, 5, &umr_bitfield_default },
	 { "PORT_CONNECTIVITY", 6, 7, &umr_bitfield_default },
};
static struct umr_bitfield ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION[] = {
	 { "CHANNEL_ALLOCATION", 0, 7, &umr_bitfield_default },
};
static struct umr_bitfield ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE[] = {
	 { "MULTICHANNEL0_ENABLE", 0, 0, &umr_bitfield_default },
	 { "MULTICHANNEL0_MUTE", 1, 1, &umr_bitfield_default },
	 { "MULTICHANNEL0_CHANNEL_ID", 4, 7, &umr_bitfield_default },
};
static struct umr_bitfield ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE[] = {
	 { "MULTICHANNEL2_ENABLE", 0, 0, &umr_bitfield_default },
	 { "MULTICHANNEL2_MUTE", 1, 1, &umr_bitfield_default },
	 { "MULTICHANNEL2_CHANNEL_ID", 4, 7, &umr_bitfield_default },
};
static struct umr_bitfield ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE[] = {
	 { "MULTICHANNEL4_ENABLE", 0, 0, &umr_bitfield_default },
	 { "MULTICHANNEL4_MUTE", 1, 1, &umr_bitfield_default },
	 { "MULTICHANNEL4_CHANNEL_ID", 4, 7, &umr_bitfield_default },
};
static struct umr_bitfield ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE[] = {
	 { "MULTICHANNEL6_ENABLE", 0, 0, &umr_bitfield_default },
	 { "MULTICHANNEL6_MUTE", 1, 1, &umr_bitfield_default },
	 { "MULTICHANNEL6_CHANNEL_ID", 4, 7, &umr_bitfield_default },
};
static struct umr_bitfield ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_HBR[] = {
	 { "HBR_CAPABLE", 0, 0, &umr_bitfield_default },
	 { "HBR_ENABLE", 4, 4, &umr_bitfield_default },
};
static struct umr_bitfield ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE[] = {
	 { "MULTICHANNEL1_ENABLE", 0, 0, &umr_bitfield_default },
	 { "MULTICHANNEL1_MUTE", 1, 1, &umr_bitfield_default },
	 { "MULTICHANNEL1_CHANNEL_ID", 4, 7, &umr_bitfield_default },
};
static struct umr_bitfield ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE[] = {
	 { "MULTICHANNEL3_ENABLE", 0, 0, &umr_bitfield_default },
	 { "MULTICHANNEL3_MUTE", 1, 1, &umr_bitfield_default },
	 { "MULTICHANNEL3_CHANNEL_ID", 4, 7, &umr_bitfield_default },
};
static struct umr_bitfield ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE[] = {
	 { "MULTICHANNEL5_ENABLE", 0, 0, &umr_bitfield_default },
	 { "MULTICHANNEL5_MUTE", 1, 1, &umr_bitfield_default },
	 { "MULTICHANNEL5_CHANNEL_ID", 4, 7, &umr_bitfield_default },
};
static struct umr_bitfield ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE[] = {
	 { "MULTICHANNEL7_ENABLE", 0, 0, &umr_bitfield_default },
	 { "MULTICHANNEL7_MUTE", 1, 1, &umr_bitfield_default },
	 { "MULTICHANNEL7_CHANNEL_ID", 4, 7, &umr_bitfield_default },
};
static struct umr_bitfield ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL[] = {
	 { "LPIB_SNAPSHOT_LOCK", 0, 0, &umr_bitfield_default },
	 { "CYCLIC_BUFFER_WRAP_COUNT", 8, 15, &umr_bitfield_default },
};
static struct umr_bitfield ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB[] = {
	 { "LPIB", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT[] = {
	 { "LPIB_TIMER_SNAPSHOT", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL[] = {
	 { "INPUT_ACTIVITY", 0, 0, &umr_bitfield_default },
	 { "CHANNEL_LAYOUT", 1, 2, &umr_bitfield_default },
	 { "INPUT_ACTIVITY_UR_ENABLE", 4, 4, &umr_bitfield_default },
	 { "INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE", 5, 5, &umr_bitfield_default },
};
static struct umr_bitfield ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_INFOFRAME[] = {
	 { "CHANNEL_COUNT", 0, 2, &umr_bitfield_default },
	 { "CHANNEL_ALLOCATION", 8, 15, &umr_bitfield_default },
	 { "INFOFRAME_BYTE_5", 16, 23, &umr_bitfield_default },
	 { "INFOFRAME_VALID", 31, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_STATUS_L[] = {
	 { "CHANNEL_STATUS_L", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_STATUS_H[] = {
	 { "CHANNEL_STATUS_H", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixAZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES[] = {
	 { "AUDIO_CHANNEL_CAPABILITIES", 0, 0, &umr_bitfield_default },
	 { "INPUT_AMPLIFIER_PRESENT", 1, 1, &umr_bitfield_default },
	 { "OUTPUT_AMPLIFIER_PRESENT", 2, 2, &umr_bitfield_default },
	 { "AMPLIFIER_PARAMETER_OVERRIDE", 3, 3, &umr_bitfield_default },
	 { "STRIPE", 5, 5, &umr_bitfield_default },
	 { "PROCESSING_WIDGET", 6, 6, &umr_bitfield_default },
	 { "UNSOLICITED_RESPONSE_CAPABILITY", 7, 7, &umr_bitfield_default },
	 { "CONNECTION_LIST", 8, 8, &umr_bitfield_default },
	 { "DIGITAL", 9, 9, &umr_bitfield_default },
	 { "POWER_CONTROL", 10, 10, &umr_bitfield_default },
	 { "LR_SWAP", 11, 11, &umr_bitfield_default },
	 { "AUDIO_WIDGET_CAPABILITIES_DELAY", 16, 19, &umr_bitfield_default },
	 { "TYPE", 20, 23, &umr_bitfield_default },
};
static struct umr_bitfield ixAZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES[] = {
	 { "IMPEDANCE_SENSE_CAPABLE", 0, 0, &umr_bitfield_default },
	 { "TRIGGER_REQUIRED", 1, 1, &umr_bitfield_default },
	 { "JACK_DETECTION_CAPABILITY", 2, 2, &umr_bitfield_default },
	 { "HEADPHONE_DRIVE_CAPABLE", 3, 3, &umr_bitfield_default },
	 { "OUTPUT_CAPABLE", 4, 4, &umr_bitfield_default },
	 { "INPUT_CAPABLE", 5, 5, &umr_bitfield_default },
	 { "BALANCED_I_O_PINS", 6, 6, &umr_bitfield_default },
	 { "HDMI", 7, 7, &umr_bitfield_default },
	 { "VREF_CONTROL", 8, 15, &umr_bitfield_default },
	 { "EAPD_CAPABLE", 16, 16, &umr_bitfield_default },
	 { "DP", 24, 24, &umr_bitfield_default },
};
static struct umr_bitfield ixAZALIA_F2_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID[] = {
	 { "AZALIA_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixAZALIA_F2_CODEC_ROOT_PARAMETER_REVISION_ID[] = {
	 { "AZALIA_CODEC_ROOT_PARAMETER_REVISION_ID", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixAZALIA_F2_CODEC_ROOT_PARAMETER_SUBORDINATE_NODE_COUNT[] = {
	 { "AZALIA_CODEC_ROOT_PARAMETER_SUBORDINATE_NODE_COUNT", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixAZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE[] = {
	 { "POWER_STATE_SET", 0, 3, &umr_bitfield_default },
	 { "POWER_STATE_ACT", 4, 7, &umr_bitfield_default },
	 { "CLKSTOPOK", 9, 9, &umr_bitfield_default },
	 { "POWER_STATE_SETTINGS_RESET", 10, 10, &umr_bitfield_default },
};
static struct umr_bitfield ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID[] = {
	 { "SUBSYSTEM_ID_BYTE0", 0, 7, &umr_bitfield_default },
	 { "SUBSYSTEM_ID_BYTE1", 8, 15, &umr_bitfield_default },
	 { "SUBSYSTEM_ID_BYTE2", 16, 23, &umr_bitfield_default },
	 { "SUBSYSTEM_ID_BYTE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_2[] = {
	 { "SUBSYSTEM_ID_BYTE1", 0, 7, &umr_bitfield_default },
};
static struct umr_bitfield ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_3[] = {
	 { "SUBSYSTEM_ID_BYTE2", 0, 7, &umr_bitfield_default },
};
static struct umr_bitfield ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_4[] = {
	 { "SUBSYSTEM_ID_BYTE3", 0, 7, &umr_bitfield_default },
};
static struct umr_bitfield ixAZALIA_F2_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION[] = {
	 { "CONVERTER_SYNCHRONIZATION", 0, 7, &umr_bitfield_default },
};
static struct umr_bitfield ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESET[] = {
	 { "CODEC_RESET", 0, 0, &umr_bitfield_default },
};
static struct umr_bitfield ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_SUBORDINATE_NODE_COUNT[] = {
	 { "AZALIA_CODEC_FUNCTION_PARAMETER_SUBORDINATE_NODE_COUNT", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_GROUP_TYPE[] = {
	 { "AZALIA_CODEC_FUNCTION_PARAMETER_GROUP_TYPE", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES[] = {
	 { "AUDIO_RATE_CAPABILITIES", 0, 11, &umr_bitfield_default },
	 { "AUDIO_BIT_CAPABILITIES", 16, 20, &umr_bitfield_default },
};
static struct umr_bitfield ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS[] = {
	 { "AZALIA_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES[] = {
	 { "AZALIA_CODEC_FUNCTION_PARAMETER_POWER_STATES", 0, 29, &umr_bitfield_default },
	 { "CLKSTOP", 30, 30, &umr_bitfield_default },
	 { "EPSS", 31, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0STREAM0_AZALIA_FIFO_SIZE_CONTROL[] = {
	 { "MIN_FIFO_SIZE", 0, 6, &umr_bitfield_default },
	 { "MAX_FIFO_SIZE", 8, 14, &umr_bitfield_default },
	 { "MAX_LATENCY_SUPPORT", 16, 23, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0STREAM0_AZALIA_LATENCY_COUNTER_CONTROL[] = {
	 { "AZALIA_LATENCY_COUNTER_RESET", 0, 0, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0STREAM0_AZALIA_WORSTCASE_LATENCY_COUNT[] = {
	 { "AZALIA_WORSTCASE_LATENCY_COUNT", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0STREAM0_AZALIA_CUMULATIVE_LATENCY_COUNT[] = {
	 { "AZALIA_CUMULATIVE_LATENCY_COUNT", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0STREAM0_AZALIA_CUMULATIVE_REQUEST_COUNT[] = {
	 { "AZALIA_CUMULATIVE_REQUEST_COUNT", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0STREAM1_AZALIA_FIFO_SIZE_CONTROL[] = {
	 { "MIN_FIFO_SIZE", 0, 6, &umr_bitfield_default },
	 { "MAX_FIFO_SIZE", 8, 14, &umr_bitfield_default },
	 { "MAX_LATENCY_SUPPORT", 16, 23, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0STREAM1_AZALIA_LATENCY_COUNTER_CONTROL[] = {
	 { "AZALIA_LATENCY_COUNTER_RESET", 0, 0, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0STREAM1_AZALIA_WORSTCASE_LATENCY_COUNT[] = {
	 { "AZALIA_WORSTCASE_LATENCY_COUNT", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0STREAM1_AZALIA_CUMULATIVE_LATENCY_COUNT[] = {
	 { "AZALIA_CUMULATIVE_LATENCY_COUNT", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0STREAM1_AZALIA_CUMULATIVE_REQUEST_COUNT[] = {
	 { "AZALIA_CUMULATIVE_REQUEST_COUNT", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0STREAM2_AZALIA_FIFO_SIZE_CONTROL[] = {
	 { "MIN_FIFO_SIZE", 0, 6, &umr_bitfield_default },
	 { "MAX_FIFO_SIZE", 8, 14, &umr_bitfield_default },
	 { "MAX_LATENCY_SUPPORT", 16, 23, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0STREAM2_AZALIA_LATENCY_COUNTER_CONTROL[] = {
	 { "AZALIA_LATENCY_COUNTER_RESET", 0, 0, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0STREAM2_AZALIA_WORSTCASE_LATENCY_COUNT[] = {
	 { "AZALIA_WORSTCASE_LATENCY_COUNT", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0STREAM2_AZALIA_CUMULATIVE_LATENCY_COUNT[] = {
	 { "AZALIA_CUMULATIVE_LATENCY_COUNT", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0STREAM2_AZALIA_CUMULATIVE_REQUEST_COUNT[] = {
	 { "AZALIA_CUMULATIVE_REQUEST_COUNT", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0STREAM3_AZALIA_FIFO_SIZE_CONTROL[] = {
	 { "MIN_FIFO_SIZE", 0, 6, &umr_bitfield_default },
	 { "MAX_FIFO_SIZE", 8, 14, &umr_bitfield_default },
	 { "MAX_LATENCY_SUPPORT", 16, 23, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0STREAM3_AZALIA_LATENCY_COUNTER_CONTROL[] = {
	 { "AZALIA_LATENCY_COUNTER_RESET", 0, 0, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0STREAM3_AZALIA_WORSTCASE_LATENCY_COUNT[] = {
	 { "AZALIA_WORSTCASE_LATENCY_COUNT", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0STREAM3_AZALIA_CUMULATIVE_LATENCY_COUNT[] = {
	 { "AZALIA_CUMULATIVE_LATENCY_COUNT", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0STREAM3_AZALIA_CUMULATIVE_REQUEST_COUNT[] = {
	 { "AZALIA_CUMULATIVE_REQUEST_COUNT", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0STREAM4_AZALIA_FIFO_SIZE_CONTROL[] = {
	 { "MIN_FIFO_SIZE", 0, 6, &umr_bitfield_default },
	 { "MAX_FIFO_SIZE", 8, 14, &umr_bitfield_default },
	 { "MAX_LATENCY_SUPPORT", 16, 23, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0STREAM4_AZALIA_LATENCY_COUNTER_CONTROL[] = {
	 { "AZALIA_LATENCY_COUNTER_RESET", 0, 0, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0STREAM4_AZALIA_WORSTCASE_LATENCY_COUNT[] = {
	 { "AZALIA_WORSTCASE_LATENCY_COUNT", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0STREAM4_AZALIA_CUMULATIVE_LATENCY_COUNT[] = {
	 { "AZALIA_CUMULATIVE_LATENCY_COUNT", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0STREAM4_AZALIA_CUMULATIVE_REQUEST_COUNT[] = {
	 { "AZALIA_CUMULATIVE_REQUEST_COUNT", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0STREAM5_AZALIA_FIFO_SIZE_CONTROL[] = {
	 { "MIN_FIFO_SIZE", 0, 6, &umr_bitfield_default },
	 { "MAX_FIFO_SIZE", 8, 14, &umr_bitfield_default },
	 { "MAX_LATENCY_SUPPORT", 16, 23, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0STREAM5_AZALIA_LATENCY_COUNTER_CONTROL[] = {
	 { "AZALIA_LATENCY_COUNTER_RESET", 0, 0, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0STREAM5_AZALIA_WORSTCASE_LATENCY_COUNT[] = {
	 { "AZALIA_WORSTCASE_LATENCY_COUNT", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0STREAM5_AZALIA_CUMULATIVE_LATENCY_COUNT[] = {
	 { "AZALIA_CUMULATIVE_LATENCY_COUNT", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0STREAM5_AZALIA_CUMULATIVE_REQUEST_COUNT[] = {
	 { "AZALIA_CUMULATIVE_REQUEST_COUNT", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0STREAM6_AZALIA_FIFO_SIZE_CONTROL[] = {
	 { "MIN_FIFO_SIZE", 0, 6, &umr_bitfield_default },
	 { "MAX_FIFO_SIZE", 8, 14, &umr_bitfield_default },
	 { "MAX_LATENCY_SUPPORT", 16, 23, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0STREAM6_AZALIA_LATENCY_COUNTER_CONTROL[] = {
	 { "AZALIA_LATENCY_COUNTER_RESET", 0, 0, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0STREAM6_AZALIA_WORSTCASE_LATENCY_COUNT[] = {
	 { "AZALIA_WORSTCASE_LATENCY_COUNT", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0STREAM6_AZALIA_CUMULATIVE_LATENCY_COUNT[] = {
	 { "AZALIA_CUMULATIVE_LATENCY_COUNT", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0STREAM6_AZALIA_CUMULATIVE_REQUEST_COUNT[] = {
	 { "AZALIA_CUMULATIVE_REQUEST_COUNT", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0STREAM7_AZALIA_FIFO_SIZE_CONTROL[] = {
	 { "MIN_FIFO_SIZE", 0, 6, &umr_bitfield_default },
	 { "MAX_FIFO_SIZE", 8, 14, &umr_bitfield_default },
	 { "MAX_LATENCY_SUPPORT", 16, 23, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0STREAM7_AZALIA_LATENCY_COUNTER_CONTROL[] = {
	 { "AZALIA_LATENCY_COUNTER_RESET", 0, 0, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0STREAM7_AZALIA_WORSTCASE_LATENCY_COUNT[] = {
	 { "AZALIA_WORSTCASE_LATENCY_COUNT", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0STREAM7_AZALIA_CUMULATIVE_LATENCY_COUNT[] = {
	 { "AZALIA_CUMULATIVE_LATENCY_COUNT", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0STREAM7_AZALIA_CUMULATIVE_REQUEST_COUNT[] = {
	 { "AZALIA_CUMULATIVE_REQUEST_COUNT", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0STREAM8_AZALIA_FIFO_SIZE_CONTROL[] = {
	 { "MIN_FIFO_SIZE", 0, 6, &umr_bitfield_default },
	 { "MAX_FIFO_SIZE", 8, 14, &umr_bitfield_default },
	 { "MAX_LATENCY_SUPPORT", 16, 23, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0STREAM8_AZALIA_LATENCY_COUNTER_CONTROL[] = {
	 { "AZALIA_LATENCY_COUNTER_RESET", 0, 0, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0STREAM8_AZALIA_WORSTCASE_LATENCY_COUNT[] = {
	 { "AZALIA_WORSTCASE_LATENCY_COUNT", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0STREAM8_AZALIA_CUMULATIVE_LATENCY_COUNT[] = {
	 { "AZALIA_CUMULATIVE_LATENCY_COUNT", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0STREAM8_AZALIA_CUMULATIVE_REQUEST_COUNT[] = {
	 { "AZALIA_CUMULATIVE_REQUEST_COUNT", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0STREAM9_AZALIA_FIFO_SIZE_CONTROL[] = {
	 { "MIN_FIFO_SIZE", 0, 6, &umr_bitfield_default },
	 { "MAX_FIFO_SIZE", 8, 14, &umr_bitfield_default },
	 { "MAX_LATENCY_SUPPORT", 16, 23, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0STREAM9_AZALIA_LATENCY_COUNTER_CONTROL[] = {
	 { "AZALIA_LATENCY_COUNTER_RESET", 0, 0, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0STREAM9_AZALIA_WORSTCASE_LATENCY_COUNT[] = {
	 { "AZALIA_WORSTCASE_LATENCY_COUNT", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0STREAM9_AZALIA_CUMULATIVE_LATENCY_COUNT[] = {
	 { "AZALIA_CUMULATIVE_LATENCY_COUNT", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0STREAM9_AZALIA_CUMULATIVE_REQUEST_COUNT[] = {
	 { "AZALIA_CUMULATIVE_REQUEST_COUNT", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0STREAM10_AZALIA_FIFO_SIZE_CONTROL[] = {
	 { "MIN_FIFO_SIZE", 0, 6, &umr_bitfield_default },
	 { "MAX_FIFO_SIZE", 8, 14, &umr_bitfield_default },
	 { "MAX_LATENCY_SUPPORT", 16, 23, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0STREAM10_AZALIA_LATENCY_COUNTER_CONTROL[] = {
	 { "AZALIA_LATENCY_COUNTER_RESET", 0, 0, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0STREAM10_AZALIA_WORSTCASE_LATENCY_COUNT[] = {
	 { "AZALIA_WORSTCASE_LATENCY_COUNT", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0STREAM10_AZALIA_CUMULATIVE_LATENCY_COUNT[] = {
	 { "AZALIA_CUMULATIVE_LATENCY_COUNT", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0STREAM10_AZALIA_CUMULATIVE_REQUEST_COUNT[] = {
	 { "AZALIA_CUMULATIVE_REQUEST_COUNT", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0STREAM11_AZALIA_FIFO_SIZE_CONTROL[] = {
	 { "MIN_FIFO_SIZE", 0, 6, &umr_bitfield_default },
	 { "MAX_FIFO_SIZE", 8, 14, &umr_bitfield_default },
	 { "MAX_LATENCY_SUPPORT", 16, 23, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0STREAM11_AZALIA_LATENCY_COUNTER_CONTROL[] = {
	 { "AZALIA_LATENCY_COUNTER_RESET", 0, 0, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0STREAM11_AZALIA_WORSTCASE_LATENCY_COUNT[] = {
	 { "AZALIA_WORSTCASE_LATENCY_COUNT", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0STREAM11_AZALIA_CUMULATIVE_LATENCY_COUNT[] = {
	 { "AZALIA_CUMULATIVE_LATENCY_COUNT", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0STREAM11_AZALIA_CUMULATIVE_REQUEST_COUNT[] = {
	 { "AZALIA_CUMULATIVE_REQUEST_COUNT", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0STREAM12_AZALIA_FIFO_SIZE_CONTROL[] = {
	 { "MIN_FIFO_SIZE", 0, 6, &umr_bitfield_default },
	 { "MAX_FIFO_SIZE", 8, 14, &umr_bitfield_default },
	 { "MAX_LATENCY_SUPPORT", 16, 23, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0STREAM12_AZALIA_LATENCY_COUNTER_CONTROL[] = {
	 { "AZALIA_LATENCY_COUNTER_RESET", 0, 0, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0STREAM12_AZALIA_WORSTCASE_LATENCY_COUNT[] = {
	 { "AZALIA_WORSTCASE_LATENCY_COUNT", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0STREAM12_AZALIA_CUMULATIVE_LATENCY_COUNT[] = {
	 { "AZALIA_CUMULATIVE_LATENCY_COUNT", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0STREAM12_AZALIA_CUMULATIVE_REQUEST_COUNT[] = {
	 { "AZALIA_CUMULATIVE_REQUEST_COUNT", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0STREAM13_AZALIA_FIFO_SIZE_CONTROL[] = {
	 { "MIN_FIFO_SIZE", 0, 6, &umr_bitfield_default },
	 { "MAX_FIFO_SIZE", 8, 14, &umr_bitfield_default },
	 { "MAX_LATENCY_SUPPORT", 16, 23, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0STREAM13_AZALIA_LATENCY_COUNTER_CONTROL[] = {
	 { "AZALIA_LATENCY_COUNTER_RESET", 0, 0, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0STREAM13_AZALIA_WORSTCASE_LATENCY_COUNT[] = {
	 { "AZALIA_WORSTCASE_LATENCY_COUNT", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0STREAM13_AZALIA_CUMULATIVE_LATENCY_COUNT[] = {
	 { "AZALIA_CUMULATIVE_LATENCY_COUNT", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0STREAM13_AZALIA_CUMULATIVE_REQUEST_COUNT[] = {
	 { "AZALIA_CUMULATIVE_REQUEST_COUNT", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0STREAM14_AZALIA_FIFO_SIZE_CONTROL[] = {
	 { "MIN_FIFO_SIZE", 0, 6, &umr_bitfield_default },
	 { "MAX_FIFO_SIZE", 8, 14, &umr_bitfield_default },
	 { "MAX_LATENCY_SUPPORT", 16, 23, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0STREAM14_AZALIA_LATENCY_COUNTER_CONTROL[] = {
	 { "AZALIA_LATENCY_COUNTER_RESET", 0, 0, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0STREAM14_AZALIA_WORSTCASE_LATENCY_COUNT[] = {
	 { "AZALIA_WORSTCASE_LATENCY_COUNT", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0STREAM14_AZALIA_CUMULATIVE_LATENCY_COUNT[] = {
	 { "AZALIA_CUMULATIVE_LATENCY_COUNT", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0STREAM14_AZALIA_CUMULATIVE_REQUEST_COUNT[] = {
	 { "AZALIA_CUMULATIVE_REQUEST_COUNT", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0STREAM15_AZALIA_FIFO_SIZE_CONTROL[] = {
	 { "MIN_FIFO_SIZE", 0, 6, &umr_bitfield_default },
	 { "MAX_FIFO_SIZE", 8, 14, &umr_bitfield_default },
	 { "MAX_LATENCY_SUPPORT", 16, 23, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0STREAM15_AZALIA_LATENCY_COUNTER_CONTROL[] = {
	 { "AZALIA_LATENCY_COUNTER_RESET", 0, 0, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0STREAM15_AZALIA_WORSTCASE_LATENCY_COUNT[] = {
	 { "AZALIA_WORSTCASE_LATENCY_COUNT", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0STREAM15_AZALIA_CUMULATIVE_LATENCY_COUNT[] = {
	 { "AZALIA_CUMULATIVE_LATENCY_COUNT", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0STREAM15_AZALIA_CUMULATIVE_REQUEST_COUNT[] = {
	 { "AZALIA_CUMULATIVE_REQUEST_COUNT", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES[] = {
	 { "AUDIO_CHANNEL_CAPABILITIES", 0, 0, &umr_bitfield_default },
	 { "INPUT_AMPLIFIER_PRESENT", 1, 1, &umr_bitfield_default },
	 { "OUTPUT_AMPLIFIER_PRESENT", 2, 2, &umr_bitfield_default },
	 { "AMPLIFIER_PARAMETER_OVERRIDE", 3, 3, &umr_bitfield_default },
	 { "FORMAT_OVERRIDE", 4, 4, &umr_bitfield_default },
	 { "STRIPE", 5, 5, &umr_bitfield_default },
	 { "PROCESSING_WIDGET", 6, 6, &umr_bitfield_default },
	 { "UNSOLICITED_RESPONSE_CAPABILITY", 7, 7, &umr_bitfield_default },
	 { "CONNECTION_LIST", 8, 8, &umr_bitfield_default },
	 { "DIGITAL", 9, 9, &umr_bitfield_default },
	 { "POWER_CONTROL", 10, 10, &umr_bitfield_default },
	 { "LR_SWAP", 11, 11, &umr_bitfield_default },
	 { "AUDIO_WIDGET_CAPABILITIES_DELAY", 16, 19, &umr_bitfield_default },
	 { "TYPE", 20, 23, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT[] = {
	 { "NUMBER_OF_CHANNELS", 0, 3, &umr_bitfield_default },
	 { "BITS_PER_SAMPLE", 4, 6, &umr_bitfield_default },
	 { "SAMPLE_BASE_DIVISOR", 8, 10, &umr_bitfield_default },
	 { "SAMPLE_BASE_MULTIPLE", 11, 13, &umr_bitfield_default },
	 { "SAMPLE_BASE_RATE", 14, 14, &umr_bitfield_default },
	 { "STREAM_TYPE", 15, 15, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID[] = {
	 { "CHANNEL_ID", 0, 3, &umr_bitfield_default },
	 { "STREAM_ID", 4, 7, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER[] = {
	 { "DIGEN", 0, 0, &umr_bitfield_default },
	 { "V", 1, 1, &umr_bitfield_default },
	 { "VCFG", 2, 2, &umr_bitfield_default },
	 { "PRE", 3, 3, &umr_bitfield_default },
	 { "COPY", 4, 4, &umr_bitfield_default },
	 { "NON_AUDIO", 5, 5, &umr_bitfield_default },
	 { "PRO", 6, 6, &umr_bitfield_default },
	 { "L", 7, 7, &umr_bitfield_default },
	 { "CC", 8, 14, &umr_bitfield_default },
	 { "KEEPALIVE", 23, 23, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS[] = {
	 { "STREAM_FORMATS", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES[] = {
	 { "AUDIO_RATE_CAPABILITIES", 0, 11, &umr_bitfield_default },
	 { "AUDIO_BIT_CAPABILITIES", 16, 20, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL[] = {
	 { "STRIPE_CONTROL", 0, 1, &umr_bitfield_default },
	 { "STRIPE_CAPABILITY", 20, 22, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE[] = {
	 { "RAMP_RATE", 0, 7, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING[] = {
	 { "PRESENTATION_TIME_EMBEDDING_ENABLE", 0, 0, &umr_bitfield_default },
	 { "PRESENTATION_TIME_OFFSET_CHANGED", 1, 1, &umr_bitfield_default },
	 { "CLEAR_GTC_COUNTER_MIN_MAX_DELTA", 2, 2, &umr_bitfield_default },
	 { "PRESENTATION_TIME_EMBEDDING_GROUP", 4, 6, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA[] = {
	 { "GTC_COUNTER_DELTA", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN[] = {
	 { "GTC_COUNTER_DELTA_MIN", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX[] = {
	 { "GTC_COUNTER_DELTA_MAX", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES[] = {
	 { "AUDIO_CHANNEL_CAPABILITIES", 0, 0, &umr_bitfield_default },
	 { "INPUT_AMPLIFIER_PRESENT", 1, 1, &umr_bitfield_default },
	 { "OUTPUT_AMPLIFIER_PRESENT", 2, 2, &umr_bitfield_default },
	 { "AMPLIFIER_PARAMETER_OVERRIDE", 3, 3, &umr_bitfield_default },
	 { "STRIPE", 5, 5, &umr_bitfield_default },
	 { "PROCESSING_WIDGET", 6, 6, &umr_bitfield_default },
	 { "UNSOLICITED_RESPONSE_CAPABILITY", 7, 7, &umr_bitfield_default },
	 { "CONNECTION_LIST", 8, 8, &umr_bitfield_default },
	 { "DIGITAL", 9, 9, &umr_bitfield_default },
	 { "POWER_CONTROL", 10, 10, &umr_bitfield_default },
	 { "LR_SWAP", 11, 11, &umr_bitfield_default },
	 { "AUDIO_WIDGET_CAPABILITIES_DELAY", 16, 19, &umr_bitfield_default },
	 { "TYPE", 20, 23, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES[] = {
	 { "IMPEDANCE_SENSE_CAPABLE", 0, 0, &umr_bitfield_default },
	 { "TRIGGER_REQUIRED", 1, 1, &umr_bitfield_default },
	 { "JACK_DETECTION_CAPABILITY", 2, 2, &umr_bitfield_default },
	 { "HEADPHONE_DRIVE_CAPABLE", 3, 3, &umr_bitfield_default },
	 { "OUTPUT_CAPABLE", 4, 4, &umr_bitfield_default },
	 { "INPUT_CAPABLE", 5, 5, &umr_bitfield_default },
	 { "BALANCED_I_O_PINS", 6, 6, &umr_bitfield_default },
	 { "HDMI", 7, 7, &umr_bitfield_default },
	 { "VREF_CONTROL", 8, 15, &umr_bitfield_default },
	 { "EAPD_CAPABLE", 16, 16, &umr_bitfield_default },
	 { "DP", 24, 24, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE[] = {
	 { "TAG", 0, 5, &umr_bitfield_default },
	 { "ENABLE", 7, 7, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE[] = {
	 { "IMPEDANCE_SENSE", 0, 30, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL[] = {
	 { "OUT_ENABLE", 6, 6, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER[] = {
	 { "SPEAKER_ALLOCATION", 0, 6, &umr_bitfield_default },
	 { "CHANNEL_ALLOCATION", 8, 15, &umr_bitfield_default },
	 { "HDMI_CONNECTION", 16, 16, &umr_bitfield_default },
	 { "DP_CONNECTION", 17, 17, &umr_bitfield_default },
	 { "EXTRA_CONNECTION_INFO", 18, 23, &umr_bitfield_default },
	 { "LFE_PLAYBACK_LEVEL", 24, 25, &umr_bitfield_default },
	 { "LEVEL_SHIFT", 27, 30, &umr_bitfield_default },
	 { "DOWN_MIX_INHIBIT", 31, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0[] = {
	 { "MAX_CHANNELS", 0, 2, &umr_bitfield_default },
	 { "SUPPORTED_FREQUENCIES", 8, 15, &umr_bitfield_default },
	 { "DESCRIPTOR_BYTE_2", 16, 23, &umr_bitfield_default },
	 { "SUPPORTED_FREQUENCIES_STEREO", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1[] = {
	 { "MAX_CHANNELS", 0, 2, &umr_bitfield_default },
	 { "SUPPORTED_FREQUENCIES", 8, 15, &umr_bitfield_default },
	 { "DESCRIPTOR_BYTE_2", 16, 23, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2[] = {
	 { "MAX_CHANNELS", 0, 2, &umr_bitfield_default },
	 { "SUPPORTED_FREQUENCIES", 8, 15, &umr_bitfield_default },
	 { "DESCRIPTOR_BYTE_2", 16, 23, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3[] = {
	 { "MAX_CHANNELS", 0, 2, &umr_bitfield_default },
	 { "SUPPORTED_FREQUENCIES", 8, 15, &umr_bitfield_default },
	 { "DESCRIPTOR_BYTE_2", 16, 23, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4[] = {
	 { "MAX_CHANNELS", 0, 2, &umr_bitfield_default },
	 { "SUPPORTED_FREQUENCIES", 8, 15, &umr_bitfield_default },
	 { "DESCRIPTOR_BYTE_2", 16, 23, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5[] = {
	 { "MAX_CHANNELS", 0, 2, &umr_bitfield_default },
	 { "SUPPORTED_FREQUENCIES", 8, 15, &umr_bitfield_default },
	 { "DESCRIPTOR_BYTE_2", 16, 23, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6[] = {
	 { "MAX_CHANNELS", 0, 2, &umr_bitfield_default },
	 { "SUPPORTED_FREQUENCIES", 8, 15, &umr_bitfield_default },
	 { "DESCRIPTOR_BYTE_2", 16, 23, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7[] = {
	 { "MAX_CHANNELS", 0, 2, &umr_bitfield_default },
	 { "SUPPORTED_FREQUENCIES", 8, 15, &umr_bitfield_default },
	 { "DESCRIPTOR_BYTE_2", 16, 23, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8[] = {
	 { "MAX_CHANNELS", 0, 2, &umr_bitfield_default },
	 { "SUPPORTED_FREQUENCIES", 8, 15, &umr_bitfield_default },
	 { "DESCRIPTOR_BYTE_2", 16, 23, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9[] = {
	 { "MAX_CHANNELS", 0, 2, &umr_bitfield_default },
	 { "SUPPORTED_FREQUENCIES", 8, 15, &umr_bitfield_default },
	 { "DESCRIPTOR_BYTE_2", 16, 23, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10[] = {
	 { "MAX_CHANNELS", 0, 2, &umr_bitfield_default },
	 { "SUPPORTED_FREQUENCIES", 8, 15, &umr_bitfield_default },
	 { "DESCRIPTOR_BYTE_2", 16, 23, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11[] = {
	 { "MAX_CHANNELS", 0, 2, &umr_bitfield_default },
	 { "SUPPORTED_FREQUENCIES", 8, 15, &umr_bitfield_default },
	 { "DESCRIPTOR_BYTE_2", 16, 23, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12[] = {
	 { "MAX_CHANNELS", 0, 2, &umr_bitfield_default },
	 { "SUPPORTED_FREQUENCIES", 8, 15, &umr_bitfield_default },
	 { "DESCRIPTOR_BYTE_2", 16, 23, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13[] = {
	 { "MAX_CHANNELS", 0, 2, &umr_bitfield_default },
	 { "SUPPORTED_FREQUENCIES", 8, 15, &umr_bitfield_default },
	 { "DESCRIPTOR_BYTE_2", 16, 23, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE[] = {
	 { "MULTICHANNEL01_ENABLE", 0, 0, &umr_bitfield_default },
	 { "MULTICHANNEL01_MUTE", 1, 1, &umr_bitfield_default },
	 { "MULTICHANNEL01_CHANNEL_ID", 4, 7, &umr_bitfield_default },
	 { "MULTICHANNEL23_ENABLE", 8, 8, &umr_bitfield_default },
	 { "MULTICHANNEL23_MUTE", 9, 9, &umr_bitfield_default },
	 { "MULTICHANNEL23_CHANNEL_ID", 12, 15, &umr_bitfield_default },
	 { "MULTICHANNEL45_ENABLE", 16, 16, &umr_bitfield_default },
	 { "MULTICHANNEL45_MUTE", 17, 17, &umr_bitfield_default },
	 { "MULTICHANNEL45_CHANNEL_ID", 20, 23, &umr_bitfield_default },
	 { "MULTICHANNEL67_ENABLE", 24, 24, &umr_bitfield_default },
	 { "MULTICHANNEL67_MUTE", 25, 25, &umr_bitfield_default },
	 { "MULTICHANNEL67_CHANNEL_ID", 28, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC[] = {
	 { "VIDEO_LIPSYNC", 0, 7, &umr_bitfield_default },
	 { "AUDIO_LIPSYNC", 8, 15, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR[] = {
	 { "HBR_CAPABLE", 0, 0, &umr_bitfield_default },
	 { "HBR_ENABLE", 4, 4, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0[] = {
	 { "MANUFACTURER_ID", 0, 15, &umr_bitfield_default },
	 { "PRODUCT_ID", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1[] = {
	 { "SINK_DESCRIPTION_LEN", 0, 7, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2[] = {
	 { "PORT_ID0", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3[] = {
	 { "PORT_ID1", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4[] = {
	 { "DESCRIPTION0", 0, 7, &umr_bitfield_default },
	 { "DESCRIPTION1", 8, 15, &umr_bitfield_default },
	 { "DESCRIPTION2", 16, 23, &umr_bitfield_default },
	 { "DESCRIPTION3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5[] = {
	 { "DESCRIPTION4", 0, 7, &umr_bitfield_default },
	 { "DESCRIPTION5", 8, 15, &umr_bitfield_default },
	 { "DESCRIPTION6", 16, 23, &umr_bitfield_default },
	 { "DESCRIPTION7", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6[] = {
	 { "DESCRIPTION8", 0, 7, &umr_bitfield_default },
	 { "DESCRIPTION9", 8, 15, &umr_bitfield_default },
	 { "DESCRIPTION10", 16, 23, &umr_bitfield_default },
	 { "DESCRIPTION11", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7[] = {
	 { "DESCRIPTION12", 0, 7, &umr_bitfield_default },
	 { "DESCRIPTION13", 8, 15, &umr_bitfield_default },
	 { "DESCRIPTION14", 16, 23, &umr_bitfield_default },
	 { "DESCRIPTION15", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8[] = {
	 { "DESCRIPTION16", 0, 7, &umr_bitfield_default },
	 { "DESCRIPTION17", 8, 15, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL[] = {
	 { "CLOCK_GATING_DISABLE", 0, 0, &umr_bitfield_default },
	 { "CLOCK_ON_STATE", 4, 4, &umr_bitfield_default },
	 { "AUDIO_ENABLED", 31, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE[] = {
	 { "UNSOLICITED_RESPONSE_PAYLOAD", 0, 25, &umr_bitfield_default },
	 { "UNSOLICITED_RESPONSE_FORCE", 28, 28, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT[] = {
	 { "SEQUENCE", 0, 3, &umr_bitfield_default },
	 { "DEFAULT_ASSOCIATION", 4, 7, &umr_bitfield_default },
	 { "MISC", 8, 11, &umr_bitfield_default },
	 { "COLOR", 12, 15, &umr_bitfield_default },
	 { "CONNECTION_TYPE", 16, 19, &umr_bitfield_default },
	 { "DEFAULT_DEVICE", 20, 23, &umr_bitfield_default },
	 { "LOCATION", 24, 29, &umr_bitfield_default },
	 { "PORT_CONNECTIVITY", 30, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2[] = {
	 { "MULTICHANNEL1_ENABLE", 0, 0, &umr_bitfield_default },
	 { "MULTICHANNEL1_MUTE", 1, 1, &umr_bitfield_default },
	 { "MULTICHANNEL1_CHANNEL_ID", 4, 7, &umr_bitfield_default },
	 { "MULTICHANNEL3_ENABLE", 8, 8, &umr_bitfield_default },
	 { "MULTICHANNEL3_MUTE", 9, 9, &umr_bitfield_default },
	 { "MULTICHANNEL3_CHANNEL_ID", 12, 15, &umr_bitfield_default },
	 { "MULTICHANNEL5_ENABLE", 16, 16, &umr_bitfield_default },
	 { "MULTICHANNEL5_MUTE", 17, 17, &umr_bitfield_default },
	 { "MULTICHANNEL5_CHANNEL_ID", 20, 23, &umr_bitfield_default },
	 { "MULTICHANNEL7_ENABLE", 24, 24, &umr_bitfield_default },
	 { "MULTICHANNEL7_MUTE", 25, 25, &umr_bitfield_default },
	 { "MULTICHANNEL7_CHANNEL_ID", 28, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE[] = {
	 { "MULTICHANNEL_MODE", 0, 0, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0[] = {
	 { "IEC_60958_CS_MODE", 0, 1, &umr_bitfield_default },
	 { "IEC_60958_CS_SOURCE_NUMBER", 2, 5, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1[] = {
	 { "IEC_60958_CS_CLOCK_ACCURACY", 0, 1, &umr_bitfield_default },
	 { "IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN", 2, 2, &umr_bitfield_default },
	 { "IEC_60958_CS_WORD_LENGTH", 3, 6, &umr_bitfield_default },
	 { "IEC_60958_CS_WORD_LENGTH_OVRRD_EN", 7, 7, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2[] = {
	 { "IEC_60958_CS_SAMPLING_FREQUENCY", 0, 5, &umr_bitfield_default },
	 { "IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN", 6, 6, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3[] = {
	 { "IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY", 0, 3, &umr_bitfield_default },
	 { "IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN", 4, 4, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4[] = {
	 { "IEC_60958_CS_SAMPLING_FREQUENCY_COEFF", 0, 3, &umr_bitfield_default },
	 { "IEC_60958_CS_MPEG_SURROUND_INFO", 4, 4, &umr_bitfield_default },
	 { "IEC_60958_CS_CGMS_A", 5, 6, &umr_bitfield_default },
	 { "IEC_60958_CS_CGMS_A_VALID", 7, 7, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5[] = {
	 { "IEC_60958_CS_CHANNEL_NUMBER_L", 0, 3, &umr_bitfield_default },
	 { "IEC_60958_CS_CHANNEL_NUMBER_R", 4, 7, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6[] = {
	 { "IEC_60958_CS_CHANNEL_NUMBER_2", 0, 3, &umr_bitfield_default },
	 { "IEC_60958_CS_CHANNEL_NUMBER_3", 4, 7, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7[] = {
	 { "IEC_60958_CS_CHANNEL_NUMBER_4", 0, 3, &umr_bitfield_default },
	 { "IEC_60958_CS_CHANNEL_NUMBER_5", 4, 7, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8[] = {
	 { "IEC_60958_CS_CHANNEL_NUMBER_6", 0, 3, &umr_bitfield_default },
	 { "IEC_60958_CS_CHANNEL_NUMBER_7", 4, 7, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO[] = {
	 { "ASSOCIATION_INFO", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS[] = {
	 { "OUTPUT_ACTIVE", 0, 0, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL[] = {
	 { "LPIB_SNAPSHOT_LOCK", 0, 0, &umr_bitfield_default },
	 { "CYCLIC_BUFFER_WRAP_COUNT", 8, 15, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB[] = {
	 { "LPIB", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT[] = {
	 { "LPIB_TIMER_SNAPSHOT", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE[] = {
	 { "CODING_TYPE", 0, 7, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED[] = {
	 { "FORMAT_CHANGED", 0, 0, &umr_bitfield_default },
	 { "FORMAT_CHANGED_ACK_UR_ENABLE", 1, 1, &umr_bitfield_default },
	 { "FORMAT_CHANGE_REASON", 8, 15, &umr_bitfield_default },
	 { "FORMAT_CHANGE_RESPONSE", 16, 23, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION[] = {
	 { "WIRELESS_DISPLAY_IDENTIFICATION", 0, 1, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE[] = {
	 { "REMOTE_KEEP_ALIVE_ENABLE", 0, 0, &umr_bitfield_default },
	 { "REMOTE_KEEP_ALIVE_CAPABILITY", 4, 4, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT0_AZALIA_F0_AUDIO_ENABLE_STATUS[] = {
	 { "AUDIO_ENABLE_STATUS", 0, 0, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT0_AZALIA_F0_AUDIO_ENABLED_INT_STATUS[] = {
	 { "AUDIO_ENABLED_FLAG", 0, 0, &umr_bitfield_default },
	 { "AUDIO_ENABLED_MASK", 4, 4, &umr_bitfield_default },
	 { "AUDIO_ENABLED_TYPE", 8, 8, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT0_AZALIA_F0_AUDIO_DISABLED_INT_STATUS[] = {
	 { "AUDIO_DISABLED_FLAG", 0, 0, &umr_bitfield_default },
	 { "AUDIO_DISABLED_MASK", 4, 4, &umr_bitfield_default },
	 { "AUDIO_DISABLED_TYPE", 8, 8, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT0_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS[] = {
	 { "AUDIO_FORMAT_CHANGED_FLAG", 0, 0, &umr_bitfield_default },
	 { "AUDIO_FORMAT_CHANGED_MASK", 4, 4, &umr_bitfield_default },
	 { "AUDIO_FORMAT_CHANGED_TYPE", 8, 8, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES[] = {
	 { "AUDIO_CHANNEL_CAPABILITIES", 0, 0, &umr_bitfield_default },
	 { "INPUT_AMPLIFIER_PRESENT", 1, 1, &umr_bitfield_default },
	 { "OUTPUT_AMPLIFIER_PRESENT", 2, 2, &umr_bitfield_default },
	 { "AMPLIFIER_PARAMETER_OVERRIDE", 3, 3, &umr_bitfield_default },
	 { "FORMAT_OVERRIDE", 4, 4, &umr_bitfield_default },
	 { "STRIPE", 5, 5, &umr_bitfield_default },
	 { "PROCESSING_WIDGET", 6, 6, &umr_bitfield_default },
	 { "UNSOLICITED_RESPONSE_CAPABILITY", 7, 7, &umr_bitfield_default },
	 { "CONNECTION_LIST", 8, 8, &umr_bitfield_default },
	 { "DIGITAL", 9, 9, &umr_bitfield_default },
	 { "POWER_CONTROL", 10, 10, &umr_bitfield_default },
	 { "LR_SWAP", 11, 11, &umr_bitfield_default },
	 { "AUDIO_WIDGET_CAPABILITIES_DELAY", 16, 19, &umr_bitfield_default },
	 { "TYPE", 20, 23, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT[] = {
	 { "NUMBER_OF_CHANNELS", 0, 3, &umr_bitfield_default },
	 { "BITS_PER_SAMPLE", 4, 6, &umr_bitfield_default },
	 { "SAMPLE_BASE_DIVISOR", 8, 10, &umr_bitfield_default },
	 { "SAMPLE_BASE_MULTIPLE", 11, 13, &umr_bitfield_default },
	 { "SAMPLE_BASE_RATE", 14, 14, &umr_bitfield_default },
	 { "STREAM_TYPE", 15, 15, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID[] = {
	 { "CHANNEL_ID", 0, 3, &umr_bitfield_default },
	 { "STREAM_ID", 4, 7, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER[] = {
	 { "DIGEN", 0, 0, &umr_bitfield_default },
	 { "V", 1, 1, &umr_bitfield_default },
	 { "VCFG", 2, 2, &umr_bitfield_default },
	 { "PRE", 3, 3, &umr_bitfield_default },
	 { "COPY", 4, 4, &umr_bitfield_default },
	 { "NON_AUDIO", 5, 5, &umr_bitfield_default },
	 { "PRO", 6, 6, &umr_bitfield_default },
	 { "L", 7, 7, &umr_bitfield_default },
	 { "CC", 8, 14, &umr_bitfield_default },
	 { "KEEPALIVE", 23, 23, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS[] = {
	 { "STREAM_FORMATS", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES[] = {
	 { "AUDIO_RATE_CAPABILITIES", 0, 11, &umr_bitfield_default },
	 { "AUDIO_BIT_CAPABILITIES", 16, 20, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL[] = {
	 { "STRIPE_CONTROL", 0, 1, &umr_bitfield_default },
	 { "STRIPE_CAPABILITY", 20, 22, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE[] = {
	 { "RAMP_RATE", 0, 7, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING[] = {
	 { "PRESENTATION_TIME_EMBEDDING_ENABLE", 0, 0, &umr_bitfield_default },
	 { "PRESENTATION_TIME_OFFSET_CHANGED", 1, 1, &umr_bitfield_default },
	 { "CLEAR_GTC_COUNTER_MIN_MAX_DELTA", 2, 2, &umr_bitfield_default },
	 { "PRESENTATION_TIME_EMBEDDING_GROUP", 4, 6, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA[] = {
	 { "GTC_COUNTER_DELTA", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN[] = {
	 { "GTC_COUNTER_DELTA_MIN", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX[] = {
	 { "GTC_COUNTER_DELTA_MAX", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES[] = {
	 { "AUDIO_CHANNEL_CAPABILITIES", 0, 0, &umr_bitfield_default },
	 { "INPUT_AMPLIFIER_PRESENT", 1, 1, &umr_bitfield_default },
	 { "OUTPUT_AMPLIFIER_PRESENT", 2, 2, &umr_bitfield_default },
	 { "AMPLIFIER_PARAMETER_OVERRIDE", 3, 3, &umr_bitfield_default },
	 { "STRIPE", 5, 5, &umr_bitfield_default },
	 { "PROCESSING_WIDGET", 6, 6, &umr_bitfield_default },
	 { "UNSOLICITED_RESPONSE_CAPABILITY", 7, 7, &umr_bitfield_default },
	 { "CONNECTION_LIST", 8, 8, &umr_bitfield_default },
	 { "DIGITAL", 9, 9, &umr_bitfield_default },
	 { "POWER_CONTROL", 10, 10, &umr_bitfield_default },
	 { "LR_SWAP", 11, 11, &umr_bitfield_default },
	 { "AUDIO_WIDGET_CAPABILITIES_DELAY", 16, 19, &umr_bitfield_default },
	 { "TYPE", 20, 23, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES[] = {
	 { "IMPEDANCE_SENSE_CAPABLE", 0, 0, &umr_bitfield_default },
	 { "TRIGGER_REQUIRED", 1, 1, &umr_bitfield_default },
	 { "JACK_DETECTION_CAPABILITY", 2, 2, &umr_bitfield_default },
	 { "HEADPHONE_DRIVE_CAPABLE", 3, 3, &umr_bitfield_default },
	 { "OUTPUT_CAPABLE", 4, 4, &umr_bitfield_default },
	 { "INPUT_CAPABLE", 5, 5, &umr_bitfield_default },
	 { "BALANCED_I_O_PINS", 6, 6, &umr_bitfield_default },
	 { "HDMI", 7, 7, &umr_bitfield_default },
	 { "VREF_CONTROL", 8, 15, &umr_bitfield_default },
	 { "EAPD_CAPABLE", 16, 16, &umr_bitfield_default },
	 { "DP", 24, 24, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE[] = {
	 { "TAG", 0, 5, &umr_bitfield_default },
	 { "ENABLE", 7, 7, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE[] = {
	 { "IMPEDANCE_SENSE", 0, 30, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL[] = {
	 { "OUT_ENABLE", 6, 6, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER[] = {
	 { "SPEAKER_ALLOCATION", 0, 6, &umr_bitfield_default },
	 { "CHANNEL_ALLOCATION", 8, 15, &umr_bitfield_default },
	 { "HDMI_CONNECTION", 16, 16, &umr_bitfield_default },
	 { "DP_CONNECTION", 17, 17, &umr_bitfield_default },
	 { "EXTRA_CONNECTION_INFO", 18, 23, &umr_bitfield_default },
	 { "LFE_PLAYBACK_LEVEL", 24, 25, &umr_bitfield_default },
	 { "LEVEL_SHIFT", 27, 30, &umr_bitfield_default },
	 { "DOWN_MIX_INHIBIT", 31, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0[] = {
	 { "MAX_CHANNELS", 0, 2, &umr_bitfield_default },
	 { "SUPPORTED_FREQUENCIES", 8, 15, &umr_bitfield_default },
	 { "DESCRIPTOR_BYTE_2", 16, 23, &umr_bitfield_default },
	 { "SUPPORTED_FREQUENCIES_STEREO", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1[] = {
	 { "MAX_CHANNELS", 0, 2, &umr_bitfield_default },
	 { "SUPPORTED_FREQUENCIES", 8, 15, &umr_bitfield_default },
	 { "DESCRIPTOR_BYTE_2", 16, 23, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2[] = {
	 { "MAX_CHANNELS", 0, 2, &umr_bitfield_default },
	 { "SUPPORTED_FREQUENCIES", 8, 15, &umr_bitfield_default },
	 { "DESCRIPTOR_BYTE_2", 16, 23, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3[] = {
	 { "MAX_CHANNELS", 0, 2, &umr_bitfield_default },
	 { "SUPPORTED_FREQUENCIES", 8, 15, &umr_bitfield_default },
	 { "DESCRIPTOR_BYTE_2", 16, 23, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4[] = {
	 { "MAX_CHANNELS", 0, 2, &umr_bitfield_default },
	 { "SUPPORTED_FREQUENCIES", 8, 15, &umr_bitfield_default },
	 { "DESCRIPTOR_BYTE_2", 16, 23, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5[] = {
	 { "MAX_CHANNELS", 0, 2, &umr_bitfield_default },
	 { "SUPPORTED_FREQUENCIES", 8, 15, &umr_bitfield_default },
	 { "DESCRIPTOR_BYTE_2", 16, 23, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6[] = {
	 { "MAX_CHANNELS", 0, 2, &umr_bitfield_default },
	 { "SUPPORTED_FREQUENCIES", 8, 15, &umr_bitfield_default },
	 { "DESCRIPTOR_BYTE_2", 16, 23, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7[] = {
	 { "MAX_CHANNELS", 0, 2, &umr_bitfield_default },
	 { "SUPPORTED_FREQUENCIES", 8, 15, &umr_bitfield_default },
	 { "DESCRIPTOR_BYTE_2", 16, 23, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8[] = {
	 { "MAX_CHANNELS", 0, 2, &umr_bitfield_default },
	 { "SUPPORTED_FREQUENCIES", 8, 15, &umr_bitfield_default },
	 { "DESCRIPTOR_BYTE_2", 16, 23, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9[] = {
	 { "MAX_CHANNELS", 0, 2, &umr_bitfield_default },
	 { "SUPPORTED_FREQUENCIES", 8, 15, &umr_bitfield_default },
	 { "DESCRIPTOR_BYTE_2", 16, 23, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10[] = {
	 { "MAX_CHANNELS", 0, 2, &umr_bitfield_default },
	 { "SUPPORTED_FREQUENCIES", 8, 15, &umr_bitfield_default },
	 { "DESCRIPTOR_BYTE_2", 16, 23, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11[] = {
	 { "MAX_CHANNELS", 0, 2, &umr_bitfield_default },
	 { "SUPPORTED_FREQUENCIES", 8, 15, &umr_bitfield_default },
	 { "DESCRIPTOR_BYTE_2", 16, 23, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12[] = {
	 { "MAX_CHANNELS", 0, 2, &umr_bitfield_default },
	 { "SUPPORTED_FREQUENCIES", 8, 15, &umr_bitfield_default },
	 { "DESCRIPTOR_BYTE_2", 16, 23, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13[] = {
	 { "MAX_CHANNELS", 0, 2, &umr_bitfield_default },
	 { "SUPPORTED_FREQUENCIES", 8, 15, &umr_bitfield_default },
	 { "DESCRIPTOR_BYTE_2", 16, 23, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE[] = {
	 { "MULTICHANNEL01_ENABLE", 0, 0, &umr_bitfield_default },
	 { "MULTICHANNEL01_MUTE", 1, 1, &umr_bitfield_default },
	 { "MULTICHANNEL01_CHANNEL_ID", 4, 7, &umr_bitfield_default },
	 { "MULTICHANNEL23_ENABLE", 8, 8, &umr_bitfield_default },
	 { "MULTICHANNEL23_MUTE", 9, 9, &umr_bitfield_default },
	 { "MULTICHANNEL23_CHANNEL_ID", 12, 15, &umr_bitfield_default },
	 { "MULTICHANNEL45_ENABLE", 16, 16, &umr_bitfield_default },
	 { "MULTICHANNEL45_MUTE", 17, 17, &umr_bitfield_default },
	 { "MULTICHANNEL45_CHANNEL_ID", 20, 23, &umr_bitfield_default },
	 { "MULTICHANNEL67_ENABLE", 24, 24, &umr_bitfield_default },
	 { "MULTICHANNEL67_MUTE", 25, 25, &umr_bitfield_default },
	 { "MULTICHANNEL67_CHANNEL_ID", 28, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC[] = {
	 { "VIDEO_LIPSYNC", 0, 7, &umr_bitfield_default },
	 { "AUDIO_LIPSYNC", 8, 15, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR[] = {
	 { "HBR_CAPABLE", 0, 0, &umr_bitfield_default },
	 { "HBR_ENABLE", 4, 4, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0[] = {
	 { "MANUFACTURER_ID", 0, 15, &umr_bitfield_default },
	 { "PRODUCT_ID", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1[] = {
	 { "SINK_DESCRIPTION_LEN", 0, 7, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2[] = {
	 { "PORT_ID0", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3[] = {
	 { "PORT_ID1", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4[] = {
	 { "DESCRIPTION0", 0, 7, &umr_bitfield_default },
	 { "DESCRIPTION1", 8, 15, &umr_bitfield_default },
	 { "DESCRIPTION2", 16, 23, &umr_bitfield_default },
	 { "DESCRIPTION3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5[] = {
	 { "DESCRIPTION4", 0, 7, &umr_bitfield_default },
	 { "DESCRIPTION5", 8, 15, &umr_bitfield_default },
	 { "DESCRIPTION6", 16, 23, &umr_bitfield_default },
	 { "DESCRIPTION7", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6[] = {
	 { "DESCRIPTION8", 0, 7, &umr_bitfield_default },
	 { "DESCRIPTION9", 8, 15, &umr_bitfield_default },
	 { "DESCRIPTION10", 16, 23, &umr_bitfield_default },
	 { "DESCRIPTION11", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7[] = {
	 { "DESCRIPTION12", 0, 7, &umr_bitfield_default },
	 { "DESCRIPTION13", 8, 15, &umr_bitfield_default },
	 { "DESCRIPTION14", 16, 23, &umr_bitfield_default },
	 { "DESCRIPTION15", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8[] = {
	 { "DESCRIPTION16", 0, 7, &umr_bitfield_default },
	 { "DESCRIPTION17", 8, 15, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL[] = {
	 { "CLOCK_GATING_DISABLE", 0, 0, &umr_bitfield_default },
	 { "CLOCK_ON_STATE", 4, 4, &umr_bitfield_default },
	 { "AUDIO_ENABLED", 31, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE[] = {
	 { "UNSOLICITED_RESPONSE_PAYLOAD", 0, 25, &umr_bitfield_default },
	 { "UNSOLICITED_RESPONSE_FORCE", 28, 28, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT[] = {
	 { "SEQUENCE", 0, 3, &umr_bitfield_default },
	 { "DEFAULT_ASSOCIATION", 4, 7, &umr_bitfield_default },
	 { "MISC", 8, 11, &umr_bitfield_default },
	 { "COLOR", 12, 15, &umr_bitfield_default },
	 { "CONNECTION_TYPE", 16, 19, &umr_bitfield_default },
	 { "DEFAULT_DEVICE", 20, 23, &umr_bitfield_default },
	 { "LOCATION", 24, 29, &umr_bitfield_default },
	 { "PORT_CONNECTIVITY", 30, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2[] = {
	 { "MULTICHANNEL1_ENABLE", 0, 0, &umr_bitfield_default },
	 { "MULTICHANNEL1_MUTE", 1, 1, &umr_bitfield_default },
	 { "MULTICHANNEL1_CHANNEL_ID", 4, 7, &umr_bitfield_default },
	 { "MULTICHANNEL3_ENABLE", 8, 8, &umr_bitfield_default },
	 { "MULTICHANNEL3_MUTE", 9, 9, &umr_bitfield_default },
	 { "MULTICHANNEL3_CHANNEL_ID", 12, 15, &umr_bitfield_default },
	 { "MULTICHANNEL5_ENABLE", 16, 16, &umr_bitfield_default },
	 { "MULTICHANNEL5_MUTE", 17, 17, &umr_bitfield_default },
	 { "MULTICHANNEL5_CHANNEL_ID", 20, 23, &umr_bitfield_default },
	 { "MULTICHANNEL7_ENABLE", 24, 24, &umr_bitfield_default },
	 { "MULTICHANNEL7_MUTE", 25, 25, &umr_bitfield_default },
	 { "MULTICHANNEL7_CHANNEL_ID", 28, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE[] = {
	 { "MULTICHANNEL_MODE", 0, 0, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0[] = {
	 { "IEC_60958_CS_MODE", 0, 1, &umr_bitfield_default },
	 { "IEC_60958_CS_SOURCE_NUMBER", 2, 5, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1[] = {
	 { "IEC_60958_CS_CLOCK_ACCURACY", 0, 1, &umr_bitfield_default },
	 { "IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN", 2, 2, &umr_bitfield_default },
	 { "IEC_60958_CS_WORD_LENGTH", 3, 6, &umr_bitfield_default },
	 { "IEC_60958_CS_WORD_LENGTH_OVRRD_EN", 7, 7, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2[] = {
	 { "IEC_60958_CS_SAMPLING_FREQUENCY", 0, 5, &umr_bitfield_default },
	 { "IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN", 6, 6, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3[] = {
	 { "IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY", 0, 3, &umr_bitfield_default },
	 { "IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN", 4, 4, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4[] = {
	 { "IEC_60958_CS_SAMPLING_FREQUENCY_COEFF", 0, 3, &umr_bitfield_default },
	 { "IEC_60958_CS_MPEG_SURROUND_INFO", 4, 4, &umr_bitfield_default },
	 { "IEC_60958_CS_CGMS_A", 5, 6, &umr_bitfield_default },
	 { "IEC_60958_CS_CGMS_A_VALID", 7, 7, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5[] = {
	 { "IEC_60958_CS_CHANNEL_NUMBER_L", 0, 3, &umr_bitfield_default },
	 { "IEC_60958_CS_CHANNEL_NUMBER_R", 4, 7, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6[] = {
	 { "IEC_60958_CS_CHANNEL_NUMBER_2", 0, 3, &umr_bitfield_default },
	 { "IEC_60958_CS_CHANNEL_NUMBER_3", 4, 7, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7[] = {
	 { "IEC_60958_CS_CHANNEL_NUMBER_4", 0, 3, &umr_bitfield_default },
	 { "IEC_60958_CS_CHANNEL_NUMBER_5", 4, 7, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8[] = {
	 { "IEC_60958_CS_CHANNEL_NUMBER_6", 0, 3, &umr_bitfield_default },
	 { "IEC_60958_CS_CHANNEL_NUMBER_7", 4, 7, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO[] = {
	 { "ASSOCIATION_INFO", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS[] = {
	 { "OUTPUT_ACTIVE", 0, 0, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL[] = {
	 { "LPIB_SNAPSHOT_LOCK", 0, 0, &umr_bitfield_default },
	 { "CYCLIC_BUFFER_WRAP_COUNT", 8, 15, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB[] = {
	 { "LPIB", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT[] = {
	 { "LPIB_TIMER_SNAPSHOT", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE[] = {
	 { "CODING_TYPE", 0, 7, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED[] = {
	 { "FORMAT_CHANGED", 0, 0, &umr_bitfield_default },
	 { "FORMAT_CHANGED_ACK_UR_ENABLE", 1, 1, &umr_bitfield_default },
	 { "FORMAT_CHANGE_REASON", 8, 15, &umr_bitfield_default },
	 { "FORMAT_CHANGE_RESPONSE", 16, 23, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION[] = {
	 { "WIRELESS_DISPLAY_IDENTIFICATION", 0, 1, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE[] = {
	 { "REMOTE_KEEP_ALIVE_ENABLE", 0, 0, &umr_bitfield_default },
	 { "REMOTE_KEEP_ALIVE_CAPABILITY", 4, 4, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT1_AZALIA_F0_AUDIO_ENABLE_STATUS[] = {
	 { "AUDIO_ENABLE_STATUS", 0, 0, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT1_AZALIA_F0_AUDIO_ENABLED_INT_STATUS[] = {
	 { "AUDIO_ENABLED_FLAG", 0, 0, &umr_bitfield_default },
	 { "AUDIO_ENABLED_MASK", 4, 4, &umr_bitfield_default },
	 { "AUDIO_ENABLED_TYPE", 8, 8, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT1_AZALIA_F0_AUDIO_DISABLED_INT_STATUS[] = {
	 { "AUDIO_DISABLED_FLAG", 0, 0, &umr_bitfield_default },
	 { "AUDIO_DISABLED_MASK", 4, 4, &umr_bitfield_default },
	 { "AUDIO_DISABLED_TYPE", 8, 8, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT1_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS[] = {
	 { "AUDIO_FORMAT_CHANGED_FLAG", 0, 0, &umr_bitfield_default },
	 { "AUDIO_FORMAT_CHANGED_MASK", 4, 4, &umr_bitfield_default },
	 { "AUDIO_FORMAT_CHANGED_TYPE", 8, 8, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES[] = {
	 { "AUDIO_CHANNEL_CAPABILITIES", 0, 0, &umr_bitfield_default },
	 { "INPUT_AMPLIFIER_PRESENT", 1, 1, &umr_bitfield_default },
	 { "OUTPUT_AMPLIFIER_PRESENT", 2, 2, &umr_bitfield_default },
	 { "AMPLIFIER_PARAMETER_OVERRIDE", 3, 3, &umr_bitfield_default },
	 { "FORMAT_OVERRIDE", 4, 4, &umr_bitfield_default },
	 { "STRIPE", 5, 5, &umr_bitfield_default },
	 { "PROCESSING_WIDGET", 6, 6, &umr_bitfield_default },
	 { "UNSOLICITED_RESPONSE_CAPABILITY", 7, 7, &umr_bitfield_default },
	 { "CONNECTION_LIST", 8, 8, &umr_bitfield_default },
	 { "DIGITAL", 9, 9, &umr_bitfield_default },
	 { "POWER_CONTROL", 10, 10, &umr_bitfield_default },
	 { "LR_SWAP", 11, 11, &umr_bitfield_default },
	 { "AUDIO_WIDGET_CAPABILITIES_DELAY", 16, 19, &umr_bitfield_default },
	 { "TYPE", 20, 23, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT[] = {
	 { "NUMBER_OF_CHANNELS", 0, 3, &umr_bitfield_default },
	 { "BITS_PER_SAMPLE", 4, 6, &umr_bitfield_default },
	 { "SAMPLE_BASE_DIVISOR", 8, 10, &umr_bitfield_default },
	 { "SAMPLE_BASE_MULTIPLE", 11, 13, &umr_bitfield_default },
	 { "SAMPLE_BASE_RATE", 14, 14, &umr_bitfield_default },
	 { "STREAM_TYPE", 15, 15, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID[] = {
	 { "CHANNEL_ID", 0, 3, &umr_bitfield_default },
	 { "STREAM_ID", 4, 7, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER[] = {
	 { "DIGEN", 0, 0, &umr_bitfield_default },
	 { "V", 1, 1, &umr_bitfield_default },
	 { "VCFG", 2, 2, &umr_bitfield_default },
	 { "PRE", 3, 3, &umr_bitfield_default },
	 { "COPY", 4, 4, &umr_bitfield_default },
	 { "NON_AUDIO", 5, 5, &umr_bitfield_default },
	 { "PRO", 6, 6, &umr_bitfield_default },
	 { "L", 7, 7, &umr_bitfield_default },
	 { "CC", 8, 14, &umr_bitfield_default },
	 { "KEEPALIVE", 23, 23, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS[] = {
	 { "STREAM_FORMATS", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES[] = {
	 { "AUDIO_RATE_CAPABILITIES", 0, 11, &umr_bitfield_default },
	 { "AUDIO_BIT_CAPABILITIES", 16, 20, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL[] = {
	 { "STRIPE_CONTROL", 0, 1, &umr_bitfield_default },
	 { "STRIPE_CAPABILITY", 20, 22, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE[] = {
	 { "RAMP_RATE", 0, 7, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING[] = {
	 { "PRESENTATION_TIME_EMBEDDING_ENABLE", 0, 0, &umr_bitfield_default },
	 { "PRESENTATION_TIME_OFFSET_CHANGED", 1, 1, &umr_bitfield_default },
	 { "CLEAR_GTC_COUNTER_MIN_MAX_DELTA", 2, 2, &umr_bitfield_default },
	 { "PRESENTATION_TIME_EMBEDDING_GROUP", 4, 6, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA[] = {
	 { "GTC_COUNTER_DELTA", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN[] = {
	 { "GTC_COUNTER_DELTA_MIN", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX[] = {
	 { "GTC_COUNTER_DELTA_MAX", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES[] = {
	 { "AUDIO_CHANNEL_CAPABILITIES", 0, 0, &umr_bitfield_default },
	 { "INPUT_AMPLIFIER_PRESENT", 1, 1, &umr_bitfield_default },
	 { "OUTPUT_AMPLIFIER_PRESENT", 2, 2, &umr_bitfield_default },
	 { "AMPLIFIER_PARAMETER_OVERRIDE", 3, 3, &umr_bitfield_default },
	 { "STRIPE", 5, 5, &umr_bitfield_default },
	 { "PROCESSING_WIDGET", 6, 6, &umr_bitfield_default },
	 { "UNSOLICITED_RESPONSE_CAPABILITY", 7, 7, &umr_bitfield_default },
	 { "CONNECTION_LIST", 8, 8, &umr_bitfield_default },
	 { "DIGITAL", 9, 9, &umr_bitfield_default },
	 { "POWER_CONTROL", 10, 10, &umr_bitfield_default },
	 { "LR_SWAP", 11, 11, &umr_bitfield_default },
	 { "AUDIO_WIDGET_CAPABILITIES_DELAY", 16, 19, &umr_bitfield_default },
	 { "TYPE", 20, 23, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES[] = {
	 { "IMPEDANCE_SENSE_CAPABLE", 0, 0, &umr_bitfield_default },
	 { "TRIGGER_REQUIRED", 1, 1, &umr_bitfield_default },
	 { "JACK_DETECTION_CAPABILITY", 2, 2, &umr_bitfield_default },
	 { "HEADPHONE_DRIVE_CAPABLE", 3, 3, &umr_bitfield_default },
	 { "OUTPUT_CAPABLE", 4, 4, &umr_bitfield_default },
	 { "INPUT_CAPABLE", 5, 5, &umr_bitfield_default },
	 { "BALANCED_I_O_PINS", 6, 6, &umr_bitfield_default },
	 { "HDMI", 7, 7, &umr_bitfield_default },
	 { "VREF_CONTROL", 8, 15, &umr_bitfield_default },
	 { "EAPD_CAPABLE", 16, 16, &umr_bitfield_default },
	 { "DP", 24, 24, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE[] = {
	 { "TAG", 0, 5, &umr_bitfield_default },
	 { "ENABLE", 7, 7, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE[] = {
	 { "IMPEDANCE_SENSE", 0, 30, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL[] = {
	 { "OUT_ENABLE", 6, 6, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER[] = {
	 { "SPEAKER_ALLOCATION", 0, 6, &umr_bitfield_default },
	 { "CHANNEL_ALLOCATION", 8, 15, &umr_bitfield_default },
	 { "HDMI_CONNECTION", 16, 16, &umr_bitfield_default },
	 { "DP_CONNECTION", 17, 17, &umr_bitfield_default },
	 { "EXTRA_CONNECTION_INFO", 18, 23, &umr_bitfield_default },
	 { "LFE_PLAYBACK_LEVEL", 24, 25, &umr_bitfield_default },
	 { "LEVEL_SHIFT", 27, 30, &umr_bitfield_default },
	 { "DOWN_MIX_INHIBIT", 31, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0[] = {
	 { "MAX_CHANNELS", 0, 2, &umr_bitfield_default },
	 { "SUPPORTED_FREQUENCIES", 8, 15, &umr_bitfield_default },
	 { "DESCRIPTOR_BYTE_2", 16, 23, &umr_bitfield_default },
	 { "SUPPORTED_FREQUENCIES_STEREO", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1[] = {
	 { "MAX_CHANNELS", 0, 2, &umr_bitfield_default },
	 { "SUPPORTED_FREQUENCIES", 8, 15, &umr_bitfield_default },
	 { "DESCRIPTOR_BYTE_2", 16, 23, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2[] = {
	 { "MAX_CHANNELS", 0, 2, &umr_bitfield_default },
	 { "SUPPORTED_FREQUENCIES", 8, 15, &umr_bitfield_default },
	 { "DESCRIPTOR_BYTE_2", 16, 23, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3[] = {
	 { "MAX_CHANNELS", 0, 2, &umr_bitfield_default },
	 { "SUPPORTED_FREQUENCIES", 8, 15, &umr_bitfield_default },
	 { "DESCRIPTOR_BYTE_2", 16, 23, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4[] = {
	 { "MAX_CHANNELS", 0, 2, &umr_bitfield_default },
	 { "SUPPORTED_FREQUENCIES", 8, 15, &umr_bitfield_default },
	 { "DESCRIPTOR_BYTE_2", 16, 23, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5[] = {
	 { "MAX_CHANNELS", 0, 2, &umr_bitfield_default },
	 { "SUPPORTED_FREQUENCIES", 8, 15, &umr_bitfield_default },
	 { "DESCRIPTOR_BYTE_2", 16, 23, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6[] = {
	 { "MAX_CHANNELS", 0, 2, &umr_bitfield_default },
	 { "SUPPORTED_FREQUENCIES", 8, 15, &umr_bitfield_default },
	 { "DESCRIPTOR_BYTE_2", 16, 23, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7[] = {
	 { "MAX_CHANNELS", 0, 2, &umr_bitfield_default },
	 { "SUPPORTED_FREQUENCIES", 8, 15, &umr_bitfield_default },
	 { "DESCRIPTOR_BYTE_2", 16, 23, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8[] = {
	 { "MAX_CHANNELS", 0, 2, &umr_bitfield_default },
	 { "SUPPORTED_FREQUENCIES", 8, 15, &umr_bitfield_default },
	 { "DESCRIPTOR_BYTE_2", 16, 23, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9[] = {
	 { "MAX_CHANNELS", 0, 2, &umr_bitfield_default },
	 { "SUPPORTED_FREQUENCIES", 8, 15, &umr_bitfield_default },
	 { "DESCRIPTOR_BYTE_2", 16, 23, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10[] = {
	 { "MAX_CHANNELS", 0, 2, &umr_bitfield_default },
	 { "SUPPORTED_FREQUENCIES", 8, 15, &umr_bitfield_default },
	 { "DESCRIPTOR_BYTE_2", 16, 23, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11[] = {
	 { "MAX_CHANNELS", 0, 2, &umr_bitfield_default },
	 { "SUPPORTED_FREQUENCIES", 8, 15, &umr_bitfield_default },
	 { "DESCRIPTOR_BYTE_2", 16, 23, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12[] = {
	 { "MAX_CHANNELS", 0, 2, &umr_bitfield_default },
	 { "SUPPORTED_FREQUENCIES", 8, 15, &umr_bitfield_default },
	 { "DESCRIPTOR_BYTE_2", 16, 23, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13[] = {
	 { "MAX_CHANNELS", 0, 2, &umr_bitfield_default },
	 { "SUPPORTED_FREQUENCIES", 8, 15, &umr_bitfield_default },
	 { "DESCRIPTOR_BYTE_2", 16, 23, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE[] = {
	 { "MULTICHANNEL01_ENABLE", 0, 0, &umr_bitfield_default },
	 { "MULTICHANNEL01_MUTE", 1, 1, &umr_bitfield_default },
	 { "MULTICHANNEL01_CHANNEL_ID", 4, 7, &umr_bitfield_default },
	 { "MULTICHANNEL23_ENABLE", 8, 8, &umr_bitfield_default },
	 { "MULTICHANNEL23_MUTE", 9, 9, &umr_bitfield_default },
	 { "MULTICHANNEL23_CHANNEL_ID", 12, 15, &umr_bitfield_default },
	 { "MULTICHANNEL45_ENABLE", 16, 16, &umr_bitfield_default },
	 { "MULTICHANNEL45_MUTE", 17, 17, &umr_bitfield_default },
	 { "MULTICHANNEL45_CHANNEL_ID", 20, 23, &umr_bitfield_default },
	 { "MULTICHANNEL67_ENABLE", 24, 24, &umr_bitfield_default },
	 { "MULTICHANNEL67_MUTE", 25, 25, &umr_bitfield_default },
	 { "MULTICHANNEL67_CHANNEL_ID", 28, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC[] = {
	 { "VIDEO_LIPSYNC", 0, 7, &umr_bitfield_default },
	 { "AUDIO_LIPSYNC", 8, 15, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR[] = {
	 { "HBR_CAPABLE", 0, 0, &umr_bitfield_default },
	 { "HBR_ENABLE", 4, 4, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0[] = {
	 { "MANUFACTURER_ID", 0, 15, &umr_bitfield_default },
	 { "PRODUCT_ID", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1[] = {
	 { "SINK_DESCRIPTION_LEN", 0, 7, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2[] = {
	 { "PORT_ID0", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3[] = {
	 { "PORT_ID1", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4[] = {
	 { "DESCRIPTION0", 0, 7, &umr_bitfield_default },
	 { "DESCRIPTION1", 8, 15, &umr_bitfield_default },
	 { "DESCRIPTION2", 16, 23, &umr_bitfield_default },
	 { "DESCRIPTION3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5[] = {
	 { "DESCRIPTION4", 0, 7, &umr_bitfield_default },
	 { "DESCRIPTION5", 8, 15, &umr_bitfield_default },
	 { "DESCRIPTION6", 16, 23, &umr_bitfield_default },
	 { "DESCRIPTION7", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6[] = {
	 { "DESCRIPTION8", 0, 7, &umr_bitfield_default },
	 { "DESCRIPTION9", 8, 15, &umr_bitfield_default },
	 { "DESCRIPTION10", 16, 23, &umr_bitfield_default },
	 { "DESCRIPTION11", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7[] = {
	 { "DESCRIPTION12", 0, 7, &umr_bitfield_default },
	 { "DESCRIPTION13", 8, 15, &umr_bitfield_default },
	 { "DESCRIPTION14", 16, 23, &umr_bitfield_default },
	 { "DESCRIPTION15", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8[] = {
	 { "DESCRIPTION16", 0, 7, &umr_bitfield_default },
	 { "DESCRIPTION17", 8, 15, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL[] = {
	 { "CLOCK_GATING_DISABLE", 0, 0, &umr_bitfield_default },
	 { "CLOCK_ON_STATE", 4, 4, &umr_bitfield_default },
	 { "AUDIO_ENABLED", 31, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE[] = {
	 { "UNSOLICITED_RESPONSE_PAYLOAD", 0, 25, &umr_bitfield_default },
	 { "UNSOLICITED_RESPONSE_FORCE", 28, 28, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT[] = {
	 { "SEQUENCE", 0, 3, &umr_bitfield_default },
	 { "DEFAULT_ASSOCIATION", 4, 7, &umr_bitfield_default },
	 { "MISC", 8, 11, &umr_bitfield_default },
	 { "COLOR", 12, 15, &umr_bitfield_default },
	 { "CONNECTION_TYPE", 16, 19, &umr_bitfield_default },
	 { "DEFAULT_DEVICE", 20, 23, &umr_bitfield_default },
	 { "LOCATION", 24, 29, &umr_bitfield_default },
	 { "PORT_CONNECTIVITY", 30, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2[] = {
	 { "MULTICHANNEL1_ENABLE", 0, 0, &umr_bitfield_default },
	 { "MULTICHANNEL1_MUTE", 1, 1, &umr_bitfield_default },
	 { "MULTICHANNEL1_CHANNEL_ID", 4, 7, &umr_bitfield_default },
	 { "MULTICHANNEL3_ENABLE", 8, 8, &umr_bitfield_default },
	 { "MULTICHANNEL3_MUTE", 9, 9, &umr_bitfield_default },
	 { "MULTICHANNEL3_CHANNEL_ID", 12, 15, &umr_bitfield_default },
	 { "MULTICHANNEL5_ENABLE", 16, 16, &umr_bitfield_default },
	 { "MULTICHANNEL5_MUTE", 17, 17, &umr_bitfield_default },
	 { "MULTICHANNEL5_CHANNEL_ID", 20, 23, &umr_bitfield_default },
	 { "MULTICHANNEL7_ENABLE", 24, 24, &umr_bitfield_default },
	 { "MULTICHANNEL7_MUTE", 25, 25, &umr_bitfield_default },
	 { "MULTICHANNEL7_CHANNEL_ID", 28, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE[] = {
	 { "MULTICHANNEL_MODE", 0, 0, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0[] = {
	 { "IEC_60958_CS_MODE", 0, 1, &umr_bitfield_default },
	 { "IEC_60958_CS_SOURCE_NUMBER", 2, 5, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1[] = {
	 { "IEC_60958_CS_CLOCK_ACCURACY", 0, 1, &umr_bitfield_default },
	 { "IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN", 2, 2, &umr_bitfield_default },
	 { "IEC_60958_CS_WORD_LENGTH", 3, 6, &umr_bitfield_default },
	 { "IEC_60958_CS_WORD_LENGTH_OVRRD_EN", 7, 7, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2[] = {
	 { "IEC_60958_CS_SAMPLING_FREQUENCY", 0, 5, &umr_bitfield_default },
	 { "IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN", 6, 6, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3[] = {
	 { "IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY", 0, 3, &umr_bitfield_default },
	 { "IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN", 4, 4, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4[] = {
	 { "IEC_60958_CS_SAMPLING_FREQUENCY_COEFF", 0, 3, &umr_bitfield_default },
	 { "IEC_60958_CS_MPEG_SURROUND_INFO", 4, 4, &umr_bitfield_default },
	 { "IEC_60958_CS_CGMS_A", 5, 6, &umr_bitfield_default },
	 { "IEC_60958_CS_CGMS_A_VALID", 7, 7, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5[] = {
	 { "IEC_60958_CS_CHANNEL_NUMBER_L", 0, 3, &umr_bitfield_default },
	 { "IEC_60958_CS_CHANNEL_NUMBER_R", 4, 7, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6[] = {
	 { "IEC_60958_CS_CHANNEL_NUMBER_2", 0, 3, &umr_bitfield_default },
	 { "IEC_60958_CS_CHANNEL_NUMBER_3", 4, 7, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7[] = {
	 { "IEC_60958_CS_CHANNEL_NUMBER_4", 0, 3, &umr_bitfield_default },
	 { "IEC_60958_CS_CHANNEL_NUMBER_5", 4, 7, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8[] = {
	 { "IEC_60958_CS_CHANNEL_NUMBER_6", 0, 3, &umr_bitfield_default },
	 { "IEC_60958_CS_CHANNEL_NUMBER_7", 4, 7, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO[] = {
	 { "ASSOCIATION_INFO", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS[] = {
	 { "OUTPUT_ACTIVE", 0, 0, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL[] = {
	 { "LPIB_SNAPSHOT_LOCK", 0, 0, &umr_bitfield_default },
	 { "CYCLIC_BUFFER_WRAP_COUNT", 8, 15, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB[] = {
	 { "LPIB", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT[] = {
	 { "LPIB_TIMER_SNAPSHOT", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE[] = {
	 { "CODING_TYPE", 0, 7, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED[] = {
	 { "FORMAT_CHANGED", 0, 0, &umr_bitfield_default },
	 { "FORMAT_CHANGED_ACK_UR_ENABLE", 1, 1, &umr_bitfield_default },
	 { "FORMAT_CHANGE_REASON", 8, 15, &umr_bitfield_default },
	 { "FORMAT_CHANGE_RESPONSE", 16, 23, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION[] = {
	 { "WIRELESS_DISPLAY_IDENTIFICATION", 0, 1, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE[] = {
	 { "REMOTE_KEEP_ALIVE_ENABLE", 0, 0, &umr_bitfield_default },
	 { "REMOTE_KEEP_ALIVE_CAPABILITY", 4, 4, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT2_AZALIA_F0_AUDIO_ENABLE_STATUS[] = {
	 { "AUDIO_ENABLE_STATUS", 0, 0, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT2_AZALIA_F0_AUDIO_ENABLED_INT_STATUS[] = {
	 { "AUDIO_ENABLED_FLAG", 0, 0, &umr_bitfield_default },
	 { "AUDIO_ENABLED_MASK", 4, 4, &umr_bitfield_default },
	 { "AUDIO_ENABLED_TYPE", 8, 8, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT2_AZALIA_F0_AUDIO_DISABLED_INT_STATUS[] = {
	 { "AUDIO_DISABLED_FLAG", 0, 0, &umr_bitfield_default },
	 { "AUDIO_DISABLED_MASK", 4, 4, &umr_bitfield_default },
	 { "AUDIO_DISABLED_TYPE", 8, 8, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT2_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS[] = {
	 { "AUDIO_FORMAT_CHANGED_FLAG", 0, 0, &umr_bitfield_default },
	 { "AUDIO_FORMAT_CHANGED_MASK", 4, 4, &umr_bitfield_default },
	 { "AUDIO_FORMAT_CHANGED_TYPE", 8, 8, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES[] = {
	 { "AUDIO_CHANNEL_CAPABILITIES", 0, 0, &umr_bitfield_default },
	 { "INPUT_AMPLIFIER_PRESENT", 1, 1, &umr_bitfield_default },
	 { "OUTPUT_AMPLIFIER_PRESENT", 2, 2, &umr_bitfield_default },
	 { "AMPLIFIER_PARAMETER_OVERRIDE", 3, 3, &umr_bitfield_default },
	 { "FORMAT_OVERRIDE", 4, 4, &umr_bitfield_default },
	 { "STRIPE", 5, 5, &umr_bitfield_default },
	 { "PROCESSING_WIDGET", 6, 6, &umr_bitfield_default },
	 { "UNSOLICITED_RESPONSE_CAPABILITY", 7, 7, &umr_bitfield_default },
	 { "CONNECTION_LIST", 8, 8, &umr_bitfield_default },
	 { "DIGITAL", 9, 9, &umr_bitfield_default },
	 { "POWER_CONTROL", 10, 10, &umr_bitfield_default },
	 { "LR_SWAP", 11, 11, &umr_bitfield_default },
	 { "AUDIO_WIDGET_CAPABILITIES_DELAY", 16, 19, &umr_bitfield_default },
	 { "TYPE", 20, 23, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT[] = {
	 { "NUMBER_OF_CHANNELS", 0, 3, &umr_bitfield_default },
	 { "BITS_PER_SAMPLE", 4, 6, &umr_bitfield_default },
	 { "SAMPLE_BASE_DIVISOR", 8, 10, &umr_bitfield_default },
	 { "SAMPLE_BASE_MULTIPLE", 11, 13, &umr_bitfield_default },
	 { "SAMPLE_BASE_RATE", 14, 14, &umr_bitfield_default },
	 { "STREAM_TYPE", 15, 15, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID[] = {
	 { "CHANNEL_ID", 0, 3, &umr_bitfield_default },
	 { "STREAM_ID", 4, 7, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER[] = {
	 { "DIGEN", 0, 0, &umr_bitfield_default },
	 { "V", 1, 1, &umr_bitfield_default },
	 { "VCFG", 2, 2, &umr_bitfield_default },
	 { "PRE", 3, 3, &umr_bitfield_default },
	 { "COPY", 4, 4, &umr_bitfield_default },
	 { "NON_AUDIO", 5, 5, &umr_bitfield_default },
	 { "PRO", 6, 6, &umr_bitfield_default },
	 { "L", 7, 7, &umr_bitfield_default },
	 { "CC", 8, 14, &umr_bitfield_default },
	 { "KEEPALIVE", 23, 23, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS[] = {
	 { "STREAM_FORMATS", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES[] = {
	 { "AUDIO_RATE_CAPABILITIES", 0, 11, &umr_bitfield_default },
	 { "AUDIO_BIT_CAPABILITIES", 16, 20, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL[] = {
	 { "STRIPE_CONTROL", 0, 1, &umr_bitfield_default },
	 { "STRIPE_CAPABILITY", 20, 22, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE[] = {
	 { "RAMP_RATE", 0, 7, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING[] = {
	 { "PRESENTATION_TIME_EMBEDDING_ENABLE", 0, 0, &umr_bitfield_default },
	 { "PRESENTATION_TIME_OFFSET_CHANGED", 1, 1, &umr_bitfield_default },
	 { "CLEAR_GTC_COUNTER_MIN_MAX_DELTA", 2, 2, &umr_bitfield_default },
	 { "PRESENTATION_TIME_EMBEDDING_GROUP", 4, 6, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA[] = {
	 { "GTC_COUNTER_DELTA", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN[] = {
	 { "GTC_COUNTER_DELTA_MIN", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX[] = {
	 { "GTC_COUNTER_DELTA_MAX", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES[] = {
	 { "AUDIO_CHANNEL_CAPABILITIES", 0, 0, &umr_bitfield_default },
	 { "INPUT_AMPLIFIER_PRESENT", 1, 1, &umr_bitfield_default },
	 { "OUTPUT_AMPLIFIER_PRESENT", 2, 2, &umr_bitfield_default },
	 { "AMPLIFIER_PARAMETER_OVERRIDE", 3, 3, &umr_bitfield_default },
	 { "STRIPE", 5, 5, &umr_bitfield_default },
	 { "PROCESSING_WIDGET", 6, 6, &umr_bitfield_default },
	 { "UNSOLICITED_RESPONSE_CAPABILITY", 7, 7, &umr_bitfield_default },
	 { "CONNECTION_LIST", 8, 8, &umr_bitfield_default },
	 { "DIGITAL", 9, 9, &umr_bitfield_default },
	 { "POWER_CONTROL", 10, 10, &umr_bitfield_default },
	 { "LR_SWAP", 11, 11, &umr_bitfield_default },
	 { "AUDIO_WIDGET_CAPABILITIES_DELAY", 16, 19, &umr_bitfield_default },
	 { "TYPE", 20, 23, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES[] = {
	 { "IMPEDANCE_SENSE_CAPABLE", 0, 0, &umr_bitfield_default },
	 { "TRIGGER_REQUIRED", 1, 1, &umr_bitfield_default },
	 { "JACK_DETECTION_CAPABILITY", 2, 2, &umr_bitfield_default },
	 { "HEADPHONE_DRIVE_CAPABLE", 3, 3, &umr_bitfield_default },
	 { "OUTPUT_CAPABLE", 4, 4, &umr_bitfield_default },
	 { "INPUT_CAPABLE", 5, 5, &umr_bitfield_default },
	 { "BALANCED_I_O_PINS", 6, 6, &umr_bitfield_default },
	 { "HDMI", 7, 7, &umr_bitfield_default },
	 { "VREF_CONTROL", 8, 15, &umr_bitfield_default },
	 { "EAPD_CAPABLE", 16, 16, &umr_bitfield_default },
	 { "DP", 24, 24, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE[] = {
	 { "TAG", 0, 5, &umr_bitfield_default },
	 { "ENABLE", 7, 7, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE[] = {
	 { "IMPEDANCE_SENSE", 0, 30, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL[] = {
	 { "OUT_ENABLE", 6, 6, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER[] = {
	 { "SPEAKER_ALLOCATION", 0, 6, &umr_bitfield_default },
	 { "CHANNEL_ALLOCATION", 8, 15, &umr_bitfield_default },
	 { "HDMI_CONNECTION", 16, 16, &umr_bitfield_default },
	 { "DP_CONNECTION", 17, 17, &umr_bitfield_default },
	 { "EXTRA_CONNECTION_INFO", 18, 23, &umr_bitfield_default },
	 { "LFE_PLAYBACK_LEVEL", 24, 25, &umr_bitfield_default },
	 { "LEVEL_SHIFT", 27, 30, &umr_bitfield_default },
	 { "DOWN_MIX_INHIBIT", 31, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0[] = {
	 { "MAX_CHANNELS", 0, 2, &umr_bitfield_default },
	 { "SUPPORTED_FREQUENCIES", 8, 15, &umr_bitfield_default },
	 { "DESCRIPTOR_BYTE_2", 16, 23, &umr_bitfield_default },
	 { "SUPPORTED_FREQUENCIES_STEREO", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1[] = {
	 { "MAX_CHANNELS", 0, 2, &umr_bitfield_default },
	 { "SUPPORTED_FREQUENCIES", 8, 15, &umr_bitfield_default },
	 { "DESCRIPTOR_BYTE_2", 16, 23, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2[] = {
	 { "MAX_CHANNELS", 0, 2, &umr_bitfield_default },
	 { "SUPPORTED_FREQUENCIES", 8, 15, &umr_bitfield_default },
	 { "DESCRIPTOR_BYTE_2", 16, 23, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3[] = {
	 { "MAX_CHANNELS", 0, 2, &umr_bitfield_default },
	 { "SUPPORTED_FREQUENCIES", 8, 15, &umr_bitfield_default },
	 { "DESCRIPTOR_BYTE_2", 16, 23, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4[] = {
	 { "MAX_CHANNELS", 0, 2, &umr_bitfield_default },
	 { "SUPPORTED_FREQUENCIES", 8, 15, &umr_bitfield_default },
	 { "DESCRIPTOR_BYTE_2", 16, 23, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5[] = {
	 { "MAX_CHANNELS", 0, 2, &umr_bitfield_default },
	 { "SUPPORTED_FREQUENCIES", 8, 15, &umr_bitfield_default },
	 { "DESCRIPTOR_BYTE_2", 16, 23, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6[] = {
	 { "MAX_CHANNELS", 0, 2, &umr_bitfield_default },
	 { "SUPPORTED_FREQUENCIES", 8, 15, &umr_bitfield_default },
	 { "DESCRIPTOR_BYTE_2", 16, 23, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7[] = {
	 { "MAX_CHANNELS", 0, 2, &umr_bitfield_default },
	 { "SUPPORTED_FREQUENCIES", 8, 15, &umr_bitfield_default },
	 { "DESCRIPTOR_BYTE_2", 16, 23, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8[] = {
	 { "MAX_CHANNELS", 0, 2, &umr_bitfield_default },
	 { "SUPPORTED_FREQUENCIES", 8, 15, &umr_bitfield_default },
	 { "DESCRIPTOR_BYTE_2", 16, 23, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9[] = {
	 { "MAX_CHANNELS", 0, 2, &umr_bitfield_default },
	 { "SUPPORTED_FREQUENCIES", 8, 15, &umr_bitfield_default },
	 { "DESCRIPTOR_BYTE_2", 16, 23, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10[] = {
	 { "MAX_CHANNELS", 0, 2, &umr_bitfield_default },
	 { "SUPPORTED_FREQUENCIES", 8, 15, &umr_bitfield_default },
	 { "DESCRIPTOR_BYTE_2", 16, 23, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11[] = {
	 { "MAX_CHANNELS", 0, 2, &umr_bitfield_default },
	 { "SUPPORTED_FREQUENCIES", 8, 15, &umr_bitfield_default },
	 { "DESCRIPTOR_BYTE_2", 16, 23, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12[] = {
	 { "MAX_CHANNELS", 0, 2, &umr_bitfield_default },
	 { "SUPPORTED_FREQUENCIES", 8, 15, &umr_bitfield_default },
	 { "DESCRIPTOR_BYTE_2", 16, 23, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13[] = {
	 { "MAX_CHANNELS", 0, 2, &umr_bitfield_default },
	 { "SUPPORTED_FREQUENCIES", 8, 15, &umr_bitfield_default },
	 { "DESCRIPTOR_BYTE_2", 16, 23, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE[] = {
	 { "MULTICHANNEL01_ENABLE", 0, 0, &umr_bitfield_default },
	 { "MULTICHANNEL01_MUTE", 1, 1, &umr_bitfield_default },
	 { "MULTICHANNEL01_CHANNEL_ID", 4, 7, &umr_bitfield_default },
	 { "MULTICHANNEL23_ENABLE", 8, 8, &umr_bitfield_default },
	 { "MULTICHANNEL23_MUTE", 9, 9, &umr_bitfield_default },
	 { "MULTICHANNEL23_CHANNEL_ID", 12, 15, &umr_bitfield_default },
	 { "MULTICHANNEL45_ENABLE", 16, 16, &umr_bitfield_default },
	 { "MULTICHANNEL45_MUTE", 17, 17, &umr_bitfield_default },
	 { "MULTICHANNEL45_CHANNEL_ID", 20, 23, &umr_bitfield_default },
	 { "MULTICHANNEL67_ENABLE", 24, 24, &umr_bitfield_default },
	 { "MULTICHANNEL67_MUTE", 25, 25, &umr_bitfield_default },
	 { "MULTICHANNEL67_CHANNEL_ID", 28, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC[] = {
	 { "VIDEO_LIPSYNC", 0, 7, &umr_bitfield_default },
	 { "AUDIO_LIPSYNC", 8, 15, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR[] = {
	 { "HBR_CAPABLE", 0, 0, &umr_bitfield_default },
	 { "HBR_ENABLE", 4, 4, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0[] = {
	 { "MANUFACTURER_ID", 0, 15, &umr_bitfield_default },
	 { "PRODUCT_ID", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1[] = {
	 { "SINK_DESCRIPTION_LEN", 0, 7, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2[] = {
	 { "PORT_ID0", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3[] = {
	 { "PORT_ID1", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4[] = {
	 { "DESCRIPTION0", 0, 7, &umr_bitfield_default },
	 { "DESCRIPTION1", 8, 15, &umr_bitfield_default },
	 { "DESCRIPTION2", 16, 23, &umr_bitfield_default },
	 { "DESCRIPTION3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5[] = {
	 { "DESCRIPTION4", 0, 7, &umr_bitfield_default },
	 { "DESCRIPTION5", 8, 15, &umr_bitfield_default },
	 { "DESCRIPTION6", 16, 23, &umr_bitfield_default },
	 { "DESCRIPTION7", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6[] = {
	 { "DESCRIPTION8", 0, 7, &umr_bitfield_default },
	 { "DESCRIPTION9", 8, 15, &umr_bitfield_default },
	 { "DESCRIPTION10", 16, 23, &umr_bitfield_default },
	 { "DESCRIPTION11", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7[] = {
	 { "DESCRIPTION12", 0, 7, &umr_bitfield_default },
	 { "DESCRIPTION13", 8, 15, &umr_bitfield_default },
	 { "DESCRIPTION14", 16, 23, &umr_bitfield_default },
	 { "DESCRIPTION15", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8[] = {
	 { "DESCRIPTION16", 0, 7, &umr_bitfield_default },
	 { "DESCRIPTION17", 8, 15, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL[] = {
	 { "CLOCK_GATING_DISABLE", 0, 0, &umr_bitfield_default },
	 { "CLOCK_ON_STATE", 4, 4, &umr_bitfield_default },
	 { "AUDIO_ENABLED", 31, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE[] = {
	 { "UNSOLICITED_RESPONSE_PAYLOAD", 0, 25, &umr_bitfield_default },
	 { "UNSOLICITED_RESPONSE_FORCE", 28, 28, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT[] = {
	 { "SEQUENCE", 0, 3, &umr_bitfield_default },
	 { "DEFAULT_ASSOCIATION", 4, 7, &umr_bitfield_default },
	 { "MISC", 8, 11, &umr_bitfield_default },
	 { "COLOR", 12, 15, &umr_bitfield_default },
	 { "CONNECTION_TYPE", 16, 19, &umr_bitfield_default },
	 { "DEFAULT_DEVICE", 20, 23, &umr_bitfield_default },
	 { "LOCATION", 24, 29, &umr_bitfield_default },
	 { "PORT_CONNECTIVITY", 30, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2[] = {
	 { "MULTICHANNEL1_ENABLE", 0, 0, &umr_bitfield_default },
	 { "MULTICHANNEL1_MUTE", 1, 1, &umr_bitfield_default },
	 { "MULTICHANNEL1_CHANNEL_ID", 4, 7, &umr_bitfield_default },
	 { "MULTICHANNEL3_ENABLE", 8, 8, &umr_bitfield_default },
	 { "MULTICHANNEL3_MUTE", 9, 9, &umr_bitfield_default },
	 { "MULTICHANNEL3_CHANNEL_ID", 12, 15, &umr_bitfield_default },
	 { "MULTICHANNEL5_ENABLE", 16, 16, &umr_bitfield_default },
	 { "MULTICHANNEL5_MUTE", 17, 17, &umr_bitfield_default },
	 { "MULTICHANNEL5_CHANNEL_ID", 20, 23, &umr_bitfield_default },
	 { "MULTICHANNEL7_ENABLE", 24, 24, &umr_bitfield_default },
	 { "MULTICHANNEL7_MUTE", 25, 25, &umr_bitfield_default },
	 { "MULTICHANNEL7_CHANNEL_ID", 28, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE[] = {
	 { "MULTICHANNEL_MODE", 0, 0, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0[] = {
	 { "IEC_60958_CS_MODE", 0, 1, &umr_bitfield_default },
	 { "IEC_60958_CS_SOURCE_NUMBER", 2, 5, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1[] = {
	 { "IEC_60958_CS_CLOCK_ACCURACY", 0, 1, &umr_bitfield_default },
	 { "IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN", 2, 2, &umr_bitfield_default },
	 { "IEC_60958_CS_WORD_LENGTH", 3, 6, &umr_bitfield_default },
	 { "IEC_60958_CS_WORD_LENGTH_OVRRD_EN", 7, 7, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2[] = {
	 { "IEC_60958_CS_SAMPLING_FREQUENCY", 0, 5, &umr_bitfield_default },
	 { "IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN", 6, 6, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3[] = {
	 { "IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY", 0, 3, &umr_bitfield_default },
	 { "IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN", 4, 4, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4[] = {
	 { "IEC_60958_CS_SAMPLING_FREQUENCY_COEFF", 0, 3, &umr_bitfield_default },
	 { "IEC_60958_CS_MPEG_SURROUND_INFO", 4, 4, &umr_bitfield_default },
	 { "IEC_60958_CS_CGMS_A", 5, 6, &umr_bitfield_default },
	 { "IEC_60958_CS_CGMS_A_VALID", 7, 7, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5[] = {
	 { "IEC_60958_CS_CHANNEL_NUMBER_L", 0, 3, &umr_bitfield_default },
	 { "IEC_60958_CS_CHANNEL_NUMBER_R", 4, 7, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6[] = {
	 { "IEC_60958_CS_CHANNEL_NUMBER_2", 0, 3, &umr_bitfield_default },
	 { "IEC_60958_CS_CHANNEL_NUMBER_3", 4, 7, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7[] = {
	 { "IEC_60958_CS_CHANNEL_NUMBER_4", 0, 3, &umr_bitfield_default },
	 { "IEC_60958_CS_CHANNEL_NUMBER_5", 4, 7, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8[] = {
	 { "IEC_60958_CS_CHANNEL_NUMBER_6", 0, 3, &umr_bitfield_default },
	 { "IEC_60958_CS_CHANNEL_NUMBER_7", 4, 7, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO[] = {
	 { "ASSOCIATION_INFO", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS[] = {
	 { "OUTPUT_ACTIVE", 0, 0, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL[] = {
	 { "LPIB_SNAPSHOT_LOCK", 0, 0, &umr_bitfield_default },
	 { "CYCLIC_BUFFER_WRAP_COUNT", 8, 15, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB[] = {
	 { "LPIB", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT[] = {
	 { "LPIB_TIMER_SNAPSHOT", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE[] = {
	 { "CODING_TYPE", 0, 7, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED[] = {
	 { "FORMAT_CHANGED", 0, 0, &umr_bitfield_default },
	 { "FORMAT_CHANGED_ACK_UR_ENABLE", 1, 1, &umr_bitfield_default },
	 { "FORMAT_CHANGE_REASON", 8, 15, &umr_bitfield_default },
	 { "FORMAT_CHANGE_RESPONSE", 16, 23, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION[] = {
	 { "WIRELESS_DISPLAY_IDENTIFICATION", 0, 1, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE[] = {
	 { "REMOTE_KEEP_ALIVE_ENABLE", 0, 0, &umr_bitfield_default },
	 { "REMOTE_KEEP_ALIVE_CAPABILITY", 4, 4, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT3_AZALIA_F0_AUDIO_ENABLE_STATUS[] = {
	 { "AUDIO_ENABLE_STATUS", 0, 0, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT3_AZALIA_F0_AUDIO_ENABLED_INT_STATUS[] = {
	 { "AUDIO_ENABLED_FLAG", 0, 0, &umr_bitfield_default },
	 { "AUDIO_ENABLED_MASK", 4, 4, &umr_bitfield_default },
	 { "AUDIO_ENABLED_TYPE", 8, 8, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT3_AZALIA_F0_AUDIO_DISABLED_INT_STATUS[] = {
	 { "AUDIO_DISABLED_FLAG", 0, 0, &umr_bitfield_default },
	 { "AUDIO_DISABLED_MASK", 4, 4, &umr_bitfield_default },
	 { "AUDIO_DISABLED_TYPE", 8, 8, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT3_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS[] = {
	 { "AUDIO_FORMAT_CHANGED_FLAG", 0, 0, &umr_bitfield_default },
	 { "AUDIO_FORMAT_CHANGED_MASK", 4, 4, &umr_bitfield_default },
	 { "AUDIO_FORMAT_CHANGED_TYPE", 8, 8, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES[] = {
	 { "AUDIO_CHANNEL_CAPABILITIES", 0, 0, &umr_bitfield_default },
	 { "INPUT_AMPLIFIER_PRESENT", 1, 1, &umr_bitfield_default },
	 { "OUTPUT_AMPLIFIER_PRESENT", 2, 2, &umr_bitfield_default },
	 { "AMPLIFIER_PARAMETER_OVERRIDE", 3, 3, &umr_bitfield_default },
	 { "FORMAT_OVERRIDE", 4, 4, &umr_bitfield_default },
	 { "STRIPE", 5, 5, &umr_bitfield_default },
	 { "PROCESSING_WIDGET", 6, 6, &umr_bitfield_default },
	 { "UNSOLICITED_RESPONSE_CAPABILITY", 7, 7, &umr_bitfield_default },
	 { "CONNECTION_LIST", 8, 8, &umr_bitfield_default },
	 { "DIGITAL", 9, 9, &umr_bitfield_default },
	 { "POWER_CONTROL", 10, 10, &umr_bitfield_default },
	 { "LR_SWAP", 11, 11, &umr_bitfield_default },
	 { "AUDIO_WIDGET_CAPABILITIES_DELAY", 16, 19, &umr_bitfield_default },
	 { "TYPE", 20, 23, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT[] = {
	 { "NUMBER_OF_CHANNELS", 0, 3, &umr_bitfield_default },
	 { "BITS_PER_SAMPLE", 4, 6, &umr_bitfield_default },
	 { "SAMPLE_BASE_DIVISOR", 8, 10, &umr_bitfield_default },
	 { "SAMPLE_BASE_MULTIPLE", 11, 13, &umr_bitfield_default },
	 { "SAMPLE_BASE_RATE", 14, 14, &umr_bitfield_default },
	 { "STREAM_TYPE", 15, 15, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID[] = {
	 { "CHANNEL_ID", 0, 3, &umr_bitfield_default },
	 { "STREAM_ID", 4, 7, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER[] = {
	 { "DIGEN", 0, 0, &umr_bitfield_default },
	 { "V", 1, 1, &umr_bitfield_default },
	 { "VCFG", 2, 2, &umr_bitfield_default },
	 { "PRE", 3, 3, &umr_bitfield_default },
	 { "COPY", 4, 4, &umr_bitfield_default },
	 { "NON_AUDIO", 5, 5, &umr_bitfield_default },
	 { "PRO", 6, 6, &umr_bitfield_default },
	 { "L", 7, 7, &umr_bitfield_default },
	 { "CC", 8, 14, &umr_bitfield_default },
	 { "KEEPALIVE", 23, 23, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS[] = {
	 { "STREAM_FORMATS", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES[] = {
	 { "AUDIO_RATE_CAPABILITIES", 0, 11, &umr_bitfield_default },
	 { "AUDIO_BIT_CAPABILITIES", 16, 20, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL[] = {
	 { "STRIPE_CONTROL", 0, 1, &umr_bitfield_default },
	 { "STRIPE_CAPABILITY", 20, 22, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE[] = {
	 { "RAMP_RATE", 0, 7, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING[] = {
	 { "PRESENTATION_TIME_EMBEDDING_ENABLE", 0, 0, &umr_bitfield_default },
	 { "PRESENTATION_TIME_OFFSET_CHANGED", 1, 1, &umr_bitfield_default },
	 { "CLEAR_GTC_COUNTER_MIN_MAX_DELTA", 2, 2, &umr_bitfield_default },
	 { "PRESENTATION_TIME_EMBEDDING_GROUP", 4, 6, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA[] = {
	 { "GTC_COUNTER_DELTA", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN[] = {
	 { "GTC_COUNTER_DELTA_MIN", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX[] = {
	 { "GTC_COUNTER_DELTA_MAX", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES[] = {
	 { "AUDIO_CHANNEL_CAPABILITIES", 0, 0, &umr_bitfield_default },
	 { "INPUT_AMPLIFIER_PRESENT", 1, 1, &umr_bitfield_default },
	 { "OUTPUT_AMPLIFIER_PRESENT", 2, 2, &umr_bitfield_default },
	 { "AMPLIFIER_PARAMETER_OVERRIDE", 3, 3, &umr_bitfield_default },
	 { "STRIPE", 5, 5, &umr_bitfield_default },
	 { "PROCESSING_WIDGET", 6, 6, &umr_bitfield_default },
	 { "UNSOLICITED_RESPONSE_CAPABILITY", 7, 7, &umr_bitfield_default },
	 { "CONNECTION_LIST", 8, 8, &umr_bitfield_default },
	 { "DIGITAL", 9, 9, &umr_bitfield_default },
	 { "POWER_CONTROL", 10, 10, &umr_bitfield_default },
	 { "LR_SWAP", 11, 11, &umr_bitfield_default },
	 { "AUDIO_WIDGET_CAPABILITIES_DELAY", 16, 19, &umr_bitfield_default },
	 { "TYPE", 20, 23, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES[] = {
	 { "IMPEDANCE_SENSE_CAPABLE", 0, 0, &umr_bitfield_default },
	 { "TRIGGER_REQUIRED", 1, 1, &umr_bitfield_default },
	 { "JACK_DETECTION_CAPABILITY", 2, 2, &umr_bitfield_default },
	 { "HEADPHONE_DRIVE_CAPABLE", 3, 3, &umr_bitfield_default },
	 { "OUTPUT_CAPABLE", 4, 4, &umr_bitfield_default },
	 { "INPUT_CAPABLE", 5, 5, &umr_bitfield_default },
	 { "BALANCED_I_O_PINS", 6, 6, &umr_bitfield_default },
	 { "HDMI", 7, 7, &umr_bitfield_default },
	 { "VREF_CONTROL", 8, 15, &umr_bitfield_default },
	 { "EAPD_CAPABLE", 16, 16, &umr_bitfield_default },
	 { "DP", 24, 24, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE[] = {
	 { "TAG", 0, 5, &umr_bitfield_default },
	 { "ENABLE", 7, 7, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE[] = {
	 { "IMPEDANCE_SENSE", 0, 30, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL[] = {
	 { "OUT_ENABLE", 6, 6, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER[] = {
	 { "SPEAKER_ALLOCATION", 0, 6, &umr_bitfield_default },
	 { "CHANNEL_ALLOCATION", 8, 15, &umr_bitfield_default },
	 { "HDMI_CONNECTION", 16, 16, &umr_bitfield_default },
	 { "DP_CONNECTION", 17, 17, &umr_bitfield_default },
	 { "EXTRA_CONNECTION_INFO", 18, 23, &umr_bitfield_default },
	 { "LFE_PLAYBACK_LEVEL", 24, 25, &umr_bitfield_default },
	 { "LEVEL_SHIFT", 27, 30, &umr_bitfield_default },
	 { "DOWN_MIX_INHIBIT", 31, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0[] = {
	 { "MAX_CHANNELS", 0, 2, &umr_bitfield_default },
	 { "SUPPORTED_FREQUENCIES", 8, 15, &umr_bitfield_default },
	 { "DESCRIPTOR_BYTE_2", 16, 23, &umr_bitfield_default },
	 { "SUPPORTED_FREQUENCIES_STEREO", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1[] = {
	 { "MAX_CHANNELS", 0, 2, &umr_bitfield_default },
	 { "SUPPORTED_FREQUENCIES", 8, 15, &umr_bitfield_default },
	 { "DESCRIPTOR_BYTE_2", 16, 23, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2[] = {
	 { "MAX_CHANNELS", 0, 2, &umr_bitfield_default },
	 { "SUPPORTED_FREQUENCIES", 8, 15, &umr_bitfield_default },
	 { "DESCRIPTOR_BYTE_2", 16, 23, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3[] = {
	 { "MAX_CHANNELS", 0, 2, &umr_bitfield_default },
	 { "SUPPORTED_FREQUENCIES", 8, 15, &umr_bitfield_default },
	 { "DESCRIPTOR_BYTE_2", 16, 23, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4[] = {
	 { "MAX_CHANNELS", 0, 2, &umr_bitfield_default },
	 { "SUPPORTED_FREQUENCIES", 8, 15, &umr_bitfield_default },
	 { "DESCRIPTOR_BYTE_2", 16, 23, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5[] = {
	 { "MAX_CHANNELS", 0, 2, &umr_bitfield_default },
	 { "SUPPORTED_FREQUENCIES", 8, 15, &umr_bitfield_default },
	 { "DESCRIPTOR_BYTE_2", 16, 23, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6[] = {
	 { "MAX_CHANNELS", 0, 2, &umr_bitfield_default },
	 { "SUPPORTED_FREQUENCIES", 8, 15, &umr_bitfield_default },
	 { "DESCRIPTOR_BYTE_2", 16, 23, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7[] = {
	 { "MAX_CHANNELS", 0, 2, &umr_bitfield_default },
	 { "SUPPORTED_FREQUENCIES", 8, 15, &umr_bitfield_default },
	 { "DESCRIPTOR_BYTE_2", 16, 23, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8[] = {
	 { "MAX_CHANNELS", 0, 2, &umr_bitfield_default },
	 { "SUPPORTED_FREQUENCIES", 8, 15, &umr_bitfield_default },
	 { "DESCRIPTOR_BYTE_2", 16, 23, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9[] = {
	 { "MAX_CHANNELS", 0, 2, &umr_bitfield_default },
	 { "SUPPORTED_FREQUENCIES", 8, 15, &umr_bitfield_default },
	 { "DESCRIPTOR_BYTE_2", 16, 23, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10[] = {
	 { "MAX_CHANNELS", 0, 2, &umr_bitfield_default },
	 { "SUPPORTED_FREQUENCIES", 8, 15, &umr_bitfield_default },
	 { "DESCRIPTOR_BYTE_2", 16, 23, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11[] = {
	 { "MAX_CHANNELS", 0, 2, &umr_bitfield_default },
	 { "SUPPORTED_FREQUENCIES", 8, 15, &umr_bitfield_default },
	 { "DESCRIPTOR_BYTE_2", 16, 23, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12[] = {
	 { "MAX_CHANNELS", 0, 2, &umr_bitfield_default },
	 { "SUPPORTED_FREQUENCIES", 8, 15, &umr_bitfield_default },
	 { "DESCRIPTOR_BYTE_2", 16, 23, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13[] = {
	 { "MAX_CHANNELS", 0, 2, &umr_bitfield_default },
	 { "SUPPORTED_FREQUENCIES", 8, 15, &umr_bitfield_default },
	 { "DESCRIPTOR_BYTE_2", 16, 23, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE[] = {
	 { "MULTICHANNEL01_ENABLE", 0, 0, &umr_bitfield_default },
	 { "MULTICHANNEL01_MUTE", 1, 1, &umr_bitfield_default },
	 { "MULTICHANNEL01_CHANNEL_ID", 4, 7, &umr_bitfield_default },
	 { "MULTICHANNEL23_ENABLE", 8, 8, &umr_bitfield_default },
	 { "MULTICHANNEL23_MUTE", 9, 9, &umr_bitfield_default },
	 { "MULTICHANNEL23_CHANNEL_ID", 12, 15, &umr_bitfield_default },
	 { "MULTICHANNEL45_ENABLE", 16, 16, &umr_bitfield_default },
	 { "MULTICHANNEL45_MUTE", 17, 17, &umr_bitfield_default },
	 { "MULTICHANNEL45_CHANNEL_ID", 20, 23, &umr_bitfield_default },
	 { "MULTICHANNEL67_ENABLE", 24, 24, &umr_bitfield_default },
	 { "MULTICHANNEL67_MUTE", 25, 25, &umr_bitfield_default },
	 { "MULTICHANNEL67_CHANNEL_ID", 28, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC[] = {
	 { "VIDEO_LIPSYNC", 0, 7, &umr_bitfield_default },
	 { "AUDIO_LIPSYNC", 8, 15, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR[] = {
	 { "HBR_CAPABLE", 0, 0, &umr_bitfield_default },
	 { "HBR_ENABLE", 4, 4, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0[] = {
	 { "MANUFACTURER_ID", 0, 15, &umr_bitfield_default },
	 { "PRODUCT_ID", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1[] = {
	 { "SINK_DESCRIPTION_LEN", 0, 7, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2[] = {
	 { "PORT_ID0", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3[] = {
	 { "PORT_ID1", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4[] = {
	 { "DESCRIPTION0", 0, 7, &umr_bitfield_default },
	 { "DESCRIPTION1", 8, 15, &umr_bitfield_default },
	 { "DESCRIPTION2", 16, 23, &umr_bitfield_default },
	 { "DESCRIPTION3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5[] = {
	 { "DESCRIPTION4", 0, 7, &umr_bitfield_default },
	 { "DESCRIPTION5", 8, 15, &umr_bitfield_default },
	 { "DESCRIPTION6", 16, 23, &umr_bitfield_default },
	 { "DESCRIPTION7", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6[] = {
	 { "DESCRIPTION8", 0, 7, &umr_bitfield_default },
	 { "DESCRIPTION9", 8, 15, &umr_bitfield_default },
	 { "DESCRIPTION10", 16, 23, &umr_bitfield_default },
	 { "DESCRIPTION11", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7[] = {
	 { "DESCRIPTION12", 0, 7, &umr_bitfield_default },
	 { "DESCRIPTION13", 8, 15, &umr_bitfield_default },
	 { "DESCRIPTION14", 16, 23, &umr_bitfield_default },
	 { "DESCRIPTION15", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8[] = {
	 { "DESCRIPTION16", 0, 7, &umr_bitfield_default },
	 { "DESCRIPTION17", 8, 15, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL[] = {
	 { "CLOCK_GATING_DISABLE", 0, 0, &umr_bitfield_default },
	 { "CLOCK_ON_STATE", 4, 4, &umr_bitfield_default },
	 { "AUDIO_ENABLED", 31, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE[] = {
	 { "UNSOLICITED_RESPONSE_PAYLOAD", 0, 25, &umr_bitfield_default },
	 { "UNSOLICITED_RESPONSE_FORCE", 28, 28, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT[] = {
	 { "SEQUENCE", 0, 3, &umr_bitfield_default },
	 { "DEFAULT_ASSOCIATION", 4, 7, &umr_bitfield_default },
	 { "MISC", 8, 11, &umr_bitfield_default },
	 { "COLOR", 12, 15, &umr_bitfield_default },
	 { "CONNECTION_TYPE", 16, 19, &umr_bitfield_default },
	 { "DEFAULT_DEVICE", 20, 23, &umr_bitfield_default },
	 { "LOCATION", 24, 29, &umr_bitfield_default },
	 { "PORT_CONNECTIVITY", 30, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2[] = {
	 { "MULTICHANNEL1_ENABLE", 0, 0, &umr_bitfield_default },
	 { "MULTICHANNEL1_MUTE", 1, 1, &umr_bitfield_default },
	 { "MULTICHANNEL1_CHANNEL_ID", 4, 7, &umr_bitfield_default },
	 { "MULTICHANNEL3_ENABLE", 8, 8, &umr_bitfield_default },
	 { "MULTICHANNEL3_MUTE", 9, 9, &umr_bitfield_default },
	 { "MULTICHANNEL3_CHANNEL_ID", 12, 15, &umr_bitfield_default },
	 { "MULTICHANNEL5_ENABLE", 16, 16, &umr_bitfield_default },
	 { "MULTICHANNEL5_MUTE", 17, 17, &umr_bitfield_default },
	 { "MULTICHANNEL5_CHANNEL_ID", 20, 23, &umr_bitfield_default },
	 { "MULTICHANNEL7_ENABLE", 24, 24, &umr_bitfield_default },
	 { "MULTICHANNEL7_MUTE", 25, 25, &umr_bitfield_default },
	 { "MULTICHANNEL7_CHANNEL_ID", 28, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE[] = {
	 { "MULTICHANNEL_MODE", 0, 0, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0[] = {
	 { "IEC_60958_CS_MODE", 0, 1, &umr_bitfield_default },
	 { "IEC_60958_CS_SOURCE_NUMBER", 2, 5, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1[] = {
	 { "IEC_60958_CS_CLOCK_ACCURACY", 0, 1, &umr_bitfield_default },
	 { "IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN", 2, 2, &umr_bitfield_default },
	 { "IEC_60958_CS_WORD_LENGTH", 3, 6, &umr_bitfield_default },
	 { "IEC_60958_CS_WORD_LENGTH_OVRRD_EN", 7, 7, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2[] = {
	 { "IEC_60958_CS_SAMPLING_FREQUENCY", 0, 5, &umr_bitfield_default },
	 { "IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN", 6, 6, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3[] = {
	 { "IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY", 0, 3, &umr_bitfield_default },
	 { "IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN", 4, 4, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4[] = {
	 { "IEC_60958_CS_SAMPLING_FREQUENCY_COEFF", 0, 3, &umr_bitfield_default },
	 { "IEC_60958_CS_MPEG_SURROUND_INFO", 4, 4, &umr_bitfield_default },
	 { "IEC_60958_CS_CGMS_A", 5, 6, &umr_bitfield_default },
	 { "IEC_60958_CS_CGMS_A_VALID", 7, 7, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5[] = {
	 { "IEC_60958_CS_CHANNEL_NUMBER_L", 0, 3, &umr_bitfield_default },
	 { "IEC_60958_CS_CHANNEL_NUMBER_R", 4, 7, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6[] = {
	 { "IEC_60958_CS_CHANNEL_NUMBER_2", 0, 3, &umr_bitfield_default },
	 { "IEC_60958_CS_CHANNEL_NUMBER_3", 4, 7, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7[] = {
	 { "IEC_60958_CS_CHANNEL_NUMBER_4", 0, 3, &umr_bitfield_default },
	 { "IEC_60958_CS_CHANNEL_NUMBER_5", 4, 7, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8[] = {
	 { "IEC_60958_CS_CHANNEL_NUMBER_6", 0, 3, &umr_bitfield_default },
	 { "IEC_60958_CS_CHANNEL_NUMBER_7", 4, 7, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO[] = {
	 { "ASSOCIATION_INFO", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS[] = {
	 { "OUTPUT_ACTIVE", 0, 0, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL[] = {
	 { "LPIB_SNAPSHOT_LOCK", 0, 0, &umr_bitfield_default },
	 { "CYCLIC_BUFFER_WRAP_COUNT", 8, 15, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB[] = {
	 { "LPIB", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT[] = {
	 { "LPIB_TIMER_SNAPSHOT", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE[] = {
	 { "CODING_TYPE", 0, 7, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED[] = {
	 { "FORMAT_CHANGED", 0, 0, &umr_bitfield_default },
	 { "FORMAT_CHANGED_ACK_UR_ENABLE", 1, 1, &umr_bitfield_default },
	 { "FORMAT_CHANGE_REASON", 8, 15, &umr_bitfield_default },
	 { "FORMAT_CHANGE_RESPONSE", 16, 23, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION[] = {
	 { "WIRELESS_DISPLAY_IDENTIFICATION", 0, 1, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE[] = {
	 { "REMOTE_KEEP_ALIVE_ENABLE", 0, 0, &umr_bitfield_default },
	 { "REMOTE_KEEP_ALIVE_CAPABILITY", 4, 4, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT4_AZALIA_F0_AUDIO_ENABLE_STATUS[] = {
	 { "AUDIO_ENABLE_STATUS", 0, 0, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT4_AZALIA_F0_AUDIO_ENABLED_INT_STATUS[] = {
	 { "AUDIO_ENABLED_FLAG", 0, 0, &umr_bitfield_default },
	 { "AUDIO_ENABLED_MASK", 4, 4, &umr_bitfield_default },
	 { "AUDIO_ENABLED_TYPE", 8, 8, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT4_AZALIA_F0_AUDIO_DISABLED_INT_STATUS[] = {
	 { "AUDIO_DISABLED_FLAG", 0, 0, &umr_bitfield_default },
	 { "AUDIO_DISABLED_MASK", 4, 4, &umr_bitfield_default },
	 { "AUDIO_DISABLED_TYPE", 8, 8, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT4_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS[] = {
	 { "AUDIO_FORMAT_CHANGED_FLAG", 0, 0, &umr_bitfield_default },
	 { "AUDIO_FORMAT_CHANGED_MASK", 4, 4, &umr_bitfield_default },
	 { "AUDIO_FORMAT_CHANGED_TYPE", 8, 8, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES[] = {
	 { "AUDIO_CHANNEL_CAPABILITIES", 0, 0, &umr_bitfield_default },
	 { "INPUT_AMPLIFIER_PRESENT", 1, 1, &umr_bitfield_default },
	 { "OUTPUT_AMPLIFIER_PRESENT", 2, 2, &umr_bitfield_default },
	 { "AMPLIFIER_PARAMETER_OVERRIDE", 3, 3, &umr_bitfield_default },
	 { "FORMAT_OVERRIDE", 4, 4, &umr_bitfield_default },
	 { "STRIPE", 5, 5, &umr_bitfield_default },
	 { "PROCESSING_WIDGET", 6, 6, &umr_bitfield_default },
	 { "UNSOLICITED_RESPONSE_CAPABILITY", 7, 7, &umr_bitfield_default },
	 { "CONNECTION_LIST", 8, 8, &umr_bitfield_default },
	 { "DIGITAL", 9, 9, &umr_bitfield_default },
	 { "POWER_CONTROL", 10, 10, &umr_bitfield_default },
	 { "LR_SWAP", 11, 11, &umr_bitfield_default },
	 { "AUDIO_WIDGET_CAPABILITIES_DELAY", 16, 19, &umr_bitfield_default },
	 { "TYPE", 20, 23, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT[] = {
	 { "NUMBER_OF_CHANNELS", 0, 3, &umr_bitfield_default },
	 { "BITS_PER_SAMPLE", 4, 6, &umr_bitfield_default },
	 { "SAMPLE_BASE_DIVISOR", 8, 10, &umr_bitfield_default },
	 { "SAMPLE_BASE_MULTIPLE", 11, 13, &umr_bitfield_default },
	 { "SAMPLE_BASE_RATE", 14, 14, &umr_bitfield_default },
	 { "STREAM_TYPE", 15, 15, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID[] = {
	 { "CHANNEL_ID", 0, 3, &umr_bitfield_default },
	 { "STREAM_ID", 4, 7, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER[] = {
	 { "DIGEN", 0, 0, &umr_bitfield_default },
	 { "V", 1, 1, &umr_bitfield_default },
	 { "VCFG", 2, 2, &umr_bitfield_default },
	 { "PRE", 3, 3, &umr_bitfield_default },
	 { "COPY", 4, 4, &umr_bitfield_default },
	 { "NON_AUDIO", 5, 5, &umr_bitfield_default },
	 { "PRO", 6, 6, &umr_bitfield_default },
	 { "L", 7, 7, &umr_bitfield_default },
	 { "CC", 8, 14, &umr_bitfield_default },
	 { "KEEPALIVE", 23, 23, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS[] = {
	 { "STREAM_FORMATS", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES[] = {
	 { "AUDIO_RATE_CAPABILITIES", 0, 11, &umr_bitfield_default },
	 { "AUDIO_BIT_CAPABILITIES", 16, 20, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL[] = {
	 { "STRIPE_CONTROL", 0, 1, &umr_bitfield_default },
	 { "STRIPE_CAPABILITY", 20, 22, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE[] = {
	 { "RAMP_RATE", 0, 7, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING[] = {
	 { "PRESENTATION_TIME_EMBEDDING_ENABLE", 0, 0, &umr_bitfield_default },
	 { "PRESENTATION_TIME_OFFSET_CHANGED", 1, 1, &umr_bitfield_default },
	 { "CLEAR_GTC_COUNTER_MIN_MAX_DELTA", 2, 2, &umr_bitfield_default },
	 { "PRESENTATION_TIME_EMBEDDING_GROUP", 4, 6, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA[] = {
	 { "GTC_COUNTER_DELTA", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN[] = {
	 { "GTC_COUNTER_DELTA_MIN", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX[] = {
	 { "GTC_COUNTER_DELTA_MAX", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES[] = {
	 { "AUDIO_CHANNEL_CAPABILITIES", 0, 0, &umr_bitfield_default },
	 { "INPUT_AMPLIFIER_PRESENT", 1, 1, &umr_bitfield_default },
	 { "OUTPUT_AMPLIFIER_PRESENT", 2, 2, &umr_bitfield_default },
	 { "AMPLIFIER_PARAMETER_OVERRIDE", 3, 3, &umr_bitfield_default },
	 { "STRIPE", 5, 5, &umr_bitfield_default },
	 { "PROCESSING_WIDGET", 6, 6, &umr_bitfield_default },
	 { "UNSOLICITED_RESPONSE_CAPABILITY", 7, 7, &umr_bitfield_default },
	 { "CONNECTION_LIST", 8, 8, &umr_bitfield_default },
	 { "DIGITAL", 9, 9, &umr_bitfield_default },
	 { "POWER_CONTROL", 10, 10, &umr_bitfield_default },
	 { "LR_SWAP", 11, 11, &umr_bitfield_default },
	 { "AUDIO_WIDGET_CAPABILITIES_DELAY", 16, 19, &umr_bitfield_default },
	 { "TYPE", 20, 23, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES[] = {
	 { "IMPEDANCE_SENSE_CAPABLE", 0, 0, &umr_bitfield_default },
	 { "TRIGGER_REQUIRED", 1, 1, &umr_bitfield_default },
	 { "JACK_DETECTION_CAPABILITY", 2, 2, &umr_bitfield_default },
	 { "HEADPHONE_DRIVE_CAPABLE", 3, 3, &umr_bitfield_default },
	 { "OUTPUT_CAPABLE", 4, 4, &umr_bitfield_default },
	 { "INPUT_CAPABLE", 5, 5, &umr_bitfield_default },
	 { "BALANCED_I_O_PINS", 6, 6, &umr_bitfield_default },
	 { "HDMI", 7, 7, &umr_bitfield_default },
	 { "VREF_CONTROL", 8, 15, &umr_bitfield_default },
	 { "EAPD_CAPABLE", 16, 16, &umr_bitfield_default },
	 { "DP", 24, 24, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE[] = {
	 { "TAG", 0, 5, &umr_bitfield_default },
	 { "ENABLE", 7, 7, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE[] = {
	 { "IMPEDANCE_SENSE", 0, 30, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL[] = {
	 { "OUT_ENABLE", 6, 6, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER[] = {
	 { "SPEAKER_ALLOCATION", 0, 6, &umr_bitfield_default },
	 { "CHANNEL_ALLOCATION", 8, 15, &umr_bitfield_default },
	 { "HDMI_CONNECTION", 16, 16, &umr_bitfield_default },
	 { "DP_CONNECTION", 17, 17, &umr_bitfield_default },
	 { "EXTRA_CONNECTION_INFO", 18, 23, &umr_bitfield_default },
	 { "LFE_PLAYBACK_LEVEL", 24, 25, &umr_bitfield_default },
	 { "LEVEL_SHIFT", 27, 30, &umr_bitfield_default },
	 { "DOWN_MIX_INHIBIT", 31, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0[] = {
	 { "MAX_CHANNELS", 0, 2, &umr_bitfield_default },
	 { "SUPPORTED_FREQUENCIES", 8, 15, &umr_bitfield_default },
	 { "DESCRIPTOR_BYTE_2", 16, 23, &umr_bitfield_default },
	 { "SUPPORTED_FREQUENCIES_STEREO", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1[] = {
	 { "MAX_CHANNELS", 0, 2, &umr_bitfield_default },
	 { "SUPPORTED_FREQUENCIES", 8, 15, &umr_bitfield_default },
	 { "DESCRIPTOR_BYTE_2", 16, 23, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2[] = {
	 { "MAX_CHANNELS", 0, 2, &umr_bitfield_default },
	 { "SUPPORTED_FREQUENCIES", 8, 15, &umr_bitfield_default },
	 { "DESCRIPTOR_BYTE_2", 16, 23, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3[] = {
	 { "MAX_CHANNELS", 0, 2, &umr_bitfield_default },
	 { "SUPPORTED_FREQUENCIES", 8, 15, &umr_bitfield_default },
	 { "DESCRIPTOR_BYTE_2", 16, 23, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4[] = {
	 { "MAX_CHANNELS", 0, 2, &umr_bitfield_default },
	 { "SUPPORTED_FREQUENCIES", 8, 15, &umr_bitfield_default },
	 { "DESCRIPTOR_BYTE_2", 16, 23, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5[] = {
	 { "MAX_CHANNELS", 0, 2, &umr_bitfield_default },
	 { "SUPPORTED_FREQUENCIES", 8, 15, &umr_bitfield_default },
	 { "DESCRIPTOR_BYTE_2", 16, 23, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6[] = {
	 { "MAX_CHANNELS", 0, 2, &umr_bitfield_default },
	 { "SUPPORTED_FREQUENCIES", 8, 15, &umr_bitfield_default },
	 { "DESCRIPTOR_BYTE_2", 16, 23, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7[] = {
	 { "MAX_CHANNELS", 0, 2, &umr_bitfield_default },
	 { "SUPPORTED_FREQUENCIES", 8, 15, &umr_bitfield_default },
	 { "DESCRIPTOR_BYTE_2", 16, 23, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8[] = {
	 { "MAX_CHANNELS", 0, 2, &umr_bitfield_default },
	 { "SUPPORTED_FREQUENCIES", 8, 15, &umr_bitfield_default },
	 { "DESCRIPTOR_BYTE_2", 16, 23, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9[] = {
	 { "MAX_CHANNELS", 0, 2, &umr_bitfield_default },
	 { "SUPPORTED_FREQUENCIES", 8, 15, &umr_bitfield_default },
	 { "DESCRIPTOR_BYTE_2", 16, 23, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10[] = {
	 { "MAX_CHANNELS", 0, 2, &umr_bitfield_default },
	 { "SUPPORTED_FREQUENCIES", 8, 15, &umr_bitfield_default },
	 { "DESCRIPTOR_BYTE_2", 16, 23, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11[] = {
	 { "MAX_CHANNELS", 0, 2, &umr_bitfield_default },
	 { "SUPPORTED_FREQUENCIES", 8, 15, &umr_bitfield_default },
	 { "DESCRIPTOR_BYTE_2", 16, 23, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12[] = {
	 { "MAX_CHANNELS", 0, 2, &umr_bitfield_default },
	 { "SUPPORTED_FREQUENCIES", 8, 15, &umr_bitfield_default },
	 { "DESCRIPTOR_BYTE_2", 16, 23, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13[] = {
	 { "MAX_CHANNELS", 0, 2, &umr_bitfield_default },
	 { "SUPPORTED_FREQUENCIES", 8, 15, &umr_bitfield_default },
	 { "DESCRIPTOR_BYTE_2", 16, 23, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE[] = {
	 { "MULTICHANNEL01_ENABLE", 0, 0, &umr_bitfield_default },
	 { "MULTICHANNEL01_MUTE", 1, 1, &umr_bitfield_default },
	 { "MULTICHANNEL01_CHANNEL_ID", 4, 7, &umr_bitfield_default },
	 { "MULTICHANNEL23_ENABLE", 8, 8, &umr_bitfield_default },
	 { "MULTICHANNEL23_MUTE", 9, 9, &umr_bitfield_default },
	 { "MULTICHANNEL23_CHANNEL_ID", 12, 15, &umr_bitfield_default },
	 { "MULTICHANNEL45_ENABLE", 16, 16, &umr_bitfield_default },
	 { "MULTICHANNEL45_MUTE", 17, 17, &umr_bitfield_default },
	 { "MULTICHANNEL45_CHANNEL_ID", 20, 23, &umr_bitfield_default },
	 { "MULTICHANNEL67_ENABLE", 24, 24, &umr_bitfield_default },
	 { "MULTICHANNEL67_MUTE", 25, 25, &umr_bitfield_default },
	 { "MULTICHANNEL67_CHANNEL_ID", 28, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC[] = {
	 { "VIDEO_LIPSYNC", 0, 7, &umr_bitfield_default },
	 { "AUDIO_LIPSYNC", 8, 15, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR[] = {
	 { "HBR_CAPABLE", 0, 0, &umr_bitfield_default },
	 { "HBR_ENABLE", 4, 4, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0[] = {
	 { "MANUFACTURER_ID", 0, 15, &umr_bitfield_default },
	 { "PRODUCT_ID", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1[] = {
	 { "SINK_DESCRIPTION_LEN", 0, 7, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2[] = {
	 { "PORT_ID0", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3[] = {
	 { "PORT_ID1", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4[] = {
	 { "DESCRIPTION0", 0, 7, &umr_bitfield_default },
	 { "DESCRIPTION1", 8, 15, &umr_bitfield_default },
	 { "DESCRIPTION2", 16, 23, &umr_bitfield_default },
	 { "DESCRIPTION3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5[] = {
	 { "DESCRIPTION4", 0, 7, &umr_bitfield_default },
	 { "DESCRIPTION5", 8, 15, &umr_bitfield_default },
	 { "DESCRIPTION6", 16, 23, &umr_bitfield_default },
	 { "DESCRIPTION7", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6[] = {
	 { "DESCRIPTION8", 0, 7, &umr_bitfield_default },
	 { "DESCRIPTION9", 8, 15, &umr_bitfield_default },
	 { "DESCRIPTION10", 16, 23, &umr_bitfield_default },
	 { "DESCRIPTION11", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7[] = {
	 { "DESCRIPTION12", 0, 7, &umr_bitfield_default },
	 { "DESCRIPTION13", 8, 15, &umr_bitfield_default },
	 { "DESCRIPTION14", 16, 23, &umr_bitfield_default },
	 { "DESCRIPTION15", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8[] = {
	 { "DESCRIPTION16", 0, 7, &umr_bitfield_default },
	 { "DESCRIPTION17", 8, 15, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL[] = {
	 { "CLOCK_GATING_DISABLE", 0, 0, &umr_bitfield_default },
	 { "CLOCK_ON_STATE", 4, 4, &umr_bitfield_default },
	 { "AUDIO_ENABLED", 31, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE[] = {
	 { "UNSOLICITED_RESPONSE_PAYLOAD", 0, 25, &umr_bitfield_default },
	 { "UNSOLICITED_RESPONSE_FORCE", 28, 28, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT[] = {
	 { "SEQUENCE", 0, 3, &umr_bitfield_default },
	 { "DEFAULT_ASSOCIATION", 4, 7, &umr_bitfield_default },
	 { "MISC", 8, 11, &umr_bitfield_default },
	 { "COLOR", 12, 15, &umr_bitfield_default },
	 { "CONNECTION_TYPE", 16, 19, &umr_bitfield_default },
	 { "DEFAULT_DEVICE", 20, 23, &umr_bitfield_default },
	 { "LOCATION", 24, 29, &umr_bitfield_default },
	 { "PORT_CONNECTIVITY", 30, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2[] = {
	 { "MULTICHANNEL1_ENABLE", 0, 0, &umr_bitfield_default },
	 { "MULTICHANNEL1_MUTE", 1, 1, &umr_bitfield_default },
	 { "MULTICHANNEL1_CHANNEL_ID", 4, 7, &umr_bitfield_default },
	 { "MULTICHANNEL3_ENABLE", 8, 8, &umr_bitfield_default },
	 { "MULTICHANNEL3_MUTE", 9, 9, &umr_bitfield_default },
	 { "MULTICHANNEL3_CHANNEL_ID", 12, 15, &umr_bitfield_default },
	 { "MULTICHANNEL5_ENABLE", 16, 16, &umr_bitfield_default },
	 { "MULTICHANNEL5_MUTE", 17, 17, &umr_bitfield_default },
	 { "MULTICHANNEL5_CHANNEL_ID", 20, 23, &umr_bitfield_default },
	 { "MULTICHANNEL7_ENABLE", 24, 24, &umr_bitfield_default },
	 { "MULTICHANNEL7_MUTE", 25, 25, &umr_bitfield_default },
	 { "MULTICHANNEL7_CHANNEL_ID", 28, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE[] = {
	 { "MULTICHANNEL_MODE", 0, 0, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0[] = {
	 { "IEC_60958_CS_MODE", 0, 1, &umr_bitfield_default },
	 { "IEC_60958_CS_SOURCE_NUMBER", 2, 5, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1[] = {
	 { "IEC_60958_CS_CLOCK_ACCURACY", 0, 1, &umr_bitfield_default },
	 { "IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN", 2, 2, &umr_bitfield_default },
	 { "IEC_60958_CS_WORD_LENGTH", 3, 6, &umr_bitfield_default },
	 { "IEC_60958_CS_WORD_LENGTH_OVRRD_EN", 7, 7, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2[] = {
	 { "IEC_60958_CS_SAMPLING_FREQUENCY", 0, 5, &umr_bitfield_default },
	 { "IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN", 6, 6, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3[] = {
	 { "IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY", 0, 3, &umr_bitfield_default },
	 { "IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN", 4, 4, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4[] = {
	 { "IEC_60958_CS_SAMPLING_FREQUENCY_COEFF", 0, 3, &umr_bitfield_default },
	 { "IEC_60958_CS_MPEG_SURROUND_INFO", 4, 4, &umr_bitfield_default },
	 { "IEC_60958_CS_CGMS_A", 5, 6, &umr_bitfield_default },
	 { "IEC_60958_CS_CGMS_A_VALID", 7, 7, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5[] = {
	 { "IEC_60958_CS_CHANNEL_NUMBER_L", 0, 3, &umr_bitfield_default },
	 { "IEC_60958_CS_CHANNEL_NUMBER_R", 4, 7, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6[] = {
	 { "IEC_60958_CS_CHANNEL_NUMBER_2", 0, 3, &umr_bitfield_default },
	 { "IEC_60958_CS_CHANNEL_NUMBER_3", 4, 7, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7[] = {
	 { "IEC_60958_CS_CHANNEL_NUMBER_4", 0, 3, &umr_bitfield_default },
	 { "IEC_60958_CS_CHANNEL_NUMBER_5", 4, 7, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8[] = {
	 { "IEC_60958_CS_CHANNEL_NUMBER_6", 0, 3, &umr_bitfield_default },
	 { "IEC_60958_CS_CHANNEL_NUMBER_7", 4, 7, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO[] = {
	 { "ASSOCIATION_INFO", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS[] = {
	 { "OUTPUT_ACTIVE", 0, 0, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL[] = {
	 { "LPIB_SNAPSHOT_LOCK", 0, 0, &umr_bitfield_default },
	 { "CYCLIC_BUFFER_WRAP_COUNT", 8, 15, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB[] = {
	 { "LPIB", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT[] = {
	 { "LPIB_TIMER_SNAPSHOT", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE[] = {
	 { "CODING_TYPE", 0, 7, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED[] = {
	 { "FORMAT_CHANGED", 0, 0, &umr_bitfield_default },
	 { "FORMAT_CHANGED_ACK_UR_ENABLE", 1, 1, &umr_bitfield_default },
	 { "FORMAT_CHANGE_REASON", 8, 15, &umr_bitfield_default },
	 { "FORMAT_CHANGE_RESPONSE", 16, 23, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION[] = {
	 { "WIRELESS_DISPLAY_IDENTIFICATION", 0, 1, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE[] = {
	 { "REMOTE_KEEP_ALIVE_ENABLE", 0, 0, &umr_bitfield_default },
	 { "REMOTE_KEEP_ALIVE_CAPABILITY", 4, 4, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT5_AZALIA_F0_AUDIO_ENABLE_STATUS[] = {
	 { "AUDIO_ENABLE_STATUS", 0, 0, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT5_AZALIA_F0_AUDIO_ENABLED_INT_STATUS[] = {
	 { "AUDIO_ENABLED_FLAG", 0, 0, &umr_bitfield_default },
	 { "AUDIO_ENABLED_MASK", 4, 4, &umr_bitfield_default },
	 { "AUDIO_ENABLED_TYPE", 8, 8, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT5_AZALIA_F0_AUDIO_DISABLED_INT_STATUS[] = {
	 { "AUDIO_DISABLED_FLAG", 0, 0, &umr_bitfield_default },
	 { "AUDIO_DISABLED_MASK", 4, 4, &umr_bitfield_default },
	 { "AUDIO_DISABLED_TYPE", 8, 8, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT5_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS[] = {
	 { "AUDIO_FORMAT_CHANGED_FLAG", 0, 0, &umr_bitfield_default },
	 { "AUDIO_FORMAT_CHANGED_MASK", 4, 4, &umr_bitfield_default },
	 { "AUDIO_FORMAT_CHANGED_TYPE", 8, 8, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES[] = {
	 { "AUDIO_CHANNEL_CAPABILITIES", 0, 0, &umr_bitfield_default },
	 { "INPUT_AMPLIFIER_PRESENT", 1, 1, &umr_bitfield_default },
	 { "OUTPUT_AMPLIFIER_PRESENT", 2, 2, &umr_bitfield_default },
	 { "AMPLIFIER_PARAMETER_OVERRIDE", 3, 3, &umr_bitfield_default },
	 { "FORMAT_OVERRIDE", 4, 4, &umr_bitfield_default },
	 { "STRIPE", 5, 5, &umr_bitfield_default },
	 { "PROCESSING_WIDGET", 6, 6, &umr_bitfield_default },
	 { "UNSOLICITED_RESPONSE_CAPABILITY", 7, 7, &umr_bitfield_default },
	 { "CONNECTION_LIST", 8, 8, &umr_bitfield_default },
	 { "DIGITAL", 9, 9, &umr_bitfield_default },
	 { "POWER_CONTROL", 10, 10, &umr_bitfield_default },
	 { "LR_SWAP", 11, 11, &umr_bitfield_default },
	 { "AUDIO_WIDGET_CAPABILITIES_DELAY", 16, 19, &umr_bitfield_default },
	 { "TYPE", 20, 23, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT[] = {
	 { "NUMBER_OF_CHANNELS", 0, 3, &umr_bitfield_default },
	 { "BITS_PER_SAMPLE", 4, 6, &umr_bitfield_default },
	 { "SAMPLE_BASE_DIVISOR", 8, 10, &umr_bitfield_default },
	 { "SAMPLE_BASE_MULTIPLE", 11, 13, &umr_bitfield_default },
	 { "SAMPLE_BASE_RATE", 14, 14, &umr_bitfield_default },
	 { "STREAM_TYPE", 15, 15, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID[] = {
	 { "CHANNEL_ID", 0, 3, &umr_bitfield_default },
	 { "STREAM_ID", 4, 7, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER[] = {
	 { "DIGEN", 0, 0, &umr_bitfield_default },
	 { "V", 1, 1, &umr_bitfield_default },
	 { "VCFG", 2, 2, &umr_bitfield_default },
	 { "PRE", 3, 3, &umr_bitfield_default },
	 { "COPY", 4, 4, &umr_bitfield_default },
	 { "NON_AUDIO", 5, 5, &umr_bitfield_default },
	 { "PRO", 6, 6, &umr_bitfield_default },
	 { "L", 7, 7, &umr_bitfield_default },
	 { "CC", 8, 14, &umr_bitfield_default },
	 { "KEEPALIVE", 23, 23, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS[] = {
	 { "STREAM_FORMATS", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES[] = {
	 { "AUDIO_RATE_CAPABILITIES", 0, 11, &umr_bitfield_default },
	 { "AUDIO_BIT_CAPABILITIES", 16, 20, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL[] = {
	 { "STRIPE_CONTROL", 0, 1, &umr_bitfield_default },
	 { "STRIPE_CAPABILITY", 20, 22, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE[] = {
	 { "RAMP_RATE", 0, 7, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING[] = {
	 { "PRESENTATION_TIME_EMBEDDING_ENABLE", 0, 0, &umr_bitfield_default },
	 { "PRESENTATION_TIME_OFFSET_CHANGED", 1, 1, &umr_bitfield_default },
	 { "CLEAR_GTC_COUNTER_MIN_MAX_DELTA", 2, 2, &umr_bitfield_default },
	 { "PRESENTATION_TIME_EMBEDDING_GROUP", 4, 6, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA[] = {
	 { "GTC_COUNTER_DELTA", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN[] = {
	 { "GTC_COUNTER_DELTA_MIN", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX[] = {
	 { "GTC_COUNTER_DELTA_MAX", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES[] = {
	 { "AUDIO_CHANNEL_CAPABILITIES", 0, 0, &umr_bitfield_default },
	 { "INPUT_AMPLIFIER_PRESENT", 1, 1, &umr_bitfield_default },
	 { "OUTPUT_AMPLIFIER_PRESENT", 2, 2, &umr_bitfield_default },
	 { "AMPLIFIER_PARAMETER_OVERRIDE", 3, 3, &umr_bitfield_default },
	 { "STRIPE", 5, 5, &umr_bitfield_default },
	 { "PROCESSING_WIDGET", 6, 6, &umr_bitfield_default },
	 { "UNSOLICITED_RESPONSE_CAPABILITY", 7, 7, &umr_bitfield_default },
	 { "CONNECTION_LIST", 8, 8, &umr_bitfield_default },
	 { "DIGITAL", 9, 9, &umr_bitfield_default },
	 { "POWER_CONTROL", 10, 10, &umr_bitfield_default },
	 { "LR_SWAP", 11, 11, &umr_bitfield_default },
	 { "AUDIO_WIDGET_CAPABILITIES_DELAY", 16, 19, &umr_bitfield_default },
	 { "TYPE", 20, 23, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES[] = {
	 { "IMPEDANCE_SENSE_CAPABLE", 0, 0, &umr_bitfield_default },
	 { "TRIGGER_REQUIRED", 1, 1, &umr_bitfield_default },
	 { "JACK_DETECTION_CAPABILITY", 2, 2, &umr_bitfield_default },
	 { "HEADPHONE_DRIVE_CAPABLE", 3, 3, &umr_bitfield_default },
	 { "OUTPUT_CAPABLE", 4, 4, &umr_bitfield_default },
	 { "INPUT_CAPABLE", 5, 5, &umr_bitfield_default },
	 { "BALANCED_I_O_PINS", 6, 6, &umr_bitfield_default },
	 { "HDMI", 7, 7, &umr_bitfield_default },
	 { "VREF_CONTROL", 8, 15, &umr_bitfield_default },
	 { "EAPD_CAPABLE", 16, 16, &umr_bitfield_default },
	 { "DP", 24, 24, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE[] = {
	 { "TAG", 0, 5, &umr_bitfield_default },
	 { "ENABLE", 7, 7, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE[] = {
	 { "IMPEDANCE_SENSE", 0, 30, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL[] = {
	 { "OUT_ENABLE", 6, 6, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER[] = {
	 { "SPEAKER_ALLOCATION", 0, 6, &umr_bitfield_default },
	 { "CHANNEL_ALLOCATION", 8, 15, &umr_bitfield_default },
	 { "HDMI_CONNECTION", 16, 16, &umr_bitfield_default },
	 { "DP_CONNECTION", 17, 17, &umr_bitfield_default },
	 { "EXTRA_CONNECTION_INFO", 18, 23, &umr_bitfield_default },
	 { "LFE_PLAYBACK_LEVEL", 24, 25, &umr_bitfield_default },
	 { "LEVEL_SHIFT", 27, 30, &umr_bitfield_default },
	 { "DOWN_MIX_INHIBIT", 31, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0[] = {
	 { "MAX_CHANNELS", 0, 2, &umr_bitfield_default },
	 { "SUPPORTED_FREQUENCIES", 8, 15, &umr_bitfield_default },
	 { "DESCRIPTOR_BYTE_2", 16, 23, &umr_bitfield_default },
	 { "SUPPORTED_FREQUENCIES_STEREO", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1[] = {
	 { "MAX_CHANNELS", 0, 2, &umr_bitfield_default },
	 { "SUPPORTED_FREQUENCIES", 8, 15, &umr_bitfield_default },
	 { "DESCRIPTOR_BYTE_2", 16, 23, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2[] = {
	 { "MAX_CHANNELS", 0, 2, &umr_bitfield_default },
	 { "SUPPORTED_FREQUENCIES", 8, 15, &umr_bitfield_default },
	 { "DESCRIPTOR_BYTE_2", 16, 23, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3[] = {
	 { "MAX_CHANNELS", 0, 2, &umr_bitfield_default },
	 { "SUPPORTED_FREQUENCIES", 8, 15, &umr_bitfield_default },
	 { "DESCRIPTOR_BYTE_2", 16, 23, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4[] = {
	 { "MAX_CHANNELS", 0, 2, &umr_bitfield_default },
	 { "SUPPORTED_FREQUENCIES", 8, 15, &umr_bitfield_default },
	 { "DESCRIPTOR_BYTE_2", 16, 23, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5[] = {
	 { "MAX_CHANNELS", 0, 2, &umr_bitfield_default },
	 { "SUPPORTED_FREQUENCIES", 8, 15, &umr_bitfield_default },
	 { "DESCRIPTOR_BYTE_2", 16, 23, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6[] = {
	 { "MAX_CHANNELS", 0, 2, &umr_bitfield_default },
	 { "SUPPORTED_FREQUENCIES", 8, 15, &umr_bitfield_default },
	 { "DESCRIPTOR_BYTE_2", 16, 23, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7[] = {
	 { "MAX_CHANNELS", 0, 2, &umr_bitfield_default },
	 { "SUPPORTED_FREQUENCIES", 8, 15, &umr_bitfield_default },
	 { "DESCRIPTOR_BYTE_2", 16, 23, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8[] = {
	 { "MAX_CHANNELS", 0, 2, &umr_bitfield_default },
	 { "SUPPORTED_FREQUENCIES", 8, 15, &umr_bitfield_default },
	 { "DESCRIPTOR_BYTE_2", 16, 23, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9[] = {
	 { "MAX_CHANNELS", 0, 2, &umr_bitfield_default },
	 { "SUPPORTED_FREQUENCIES", 8, 15, &umr_bitfield_default },
	 { "DESCRIPTOR_BYTE_2", 16, 23, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10[] = {
	 { "MAX_CHANNELS", 0, 2, &umr_bitfield_default },
	 { "SUPPORTED_FREQUENCIES", 8, 15, &umr_bitfield_default },
	 { "DESCRIPTOR_BYTE_2", 16, 23, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11[] = {
	 { "MAX_CHANNELS", 0, 2, &umr_bitfield_default },
	 { "SUPPORTED_FREQUENCIES", 8, 15, &umr_bitfield_default },
	 { "DESCRIPTOR_BYTE_2", 16, 23, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12[] = {
	 { "MAX_CHANNELS", 0, 2, &umr_bitfield_default },
	 { "SUPPORTED_FREQUENCIES", 8, 15, &umr_bitfield_default },
	 { "DESCRIPTOR_BYTE_2", 16, 23, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13[] = {
	 { "MAX_CHANNELS", 0, 2, &umr_bitfield_default },
	 { "SUPPORTED_FREQUENCIES", 8, 15, &umr_bitfield_default },
	 { "DESCRIPTOR_BYTE_2", 16, 23, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE[] = {
	 { "MULTICHANNEL01_ENABLE", 0, 0, &umr_bitfield_default },
	 { "MULTICHANNEL01_MUTE", 1, 1, &umr_bitfield_default },
	 { "MULTICHANNEL01_CHANNEL_ID", 4, 7, &umr_bitfield_default },
	 { "MULTICHANNEL23_ENABLE", 8, 8, &umr_bitfield_default },
	 { "MULTICHANNEL23_MUTE", 9, 9, &umr_bitfield_default },
	 { "MULTICHANNEL23_CHANNEL_ID", 12, 15, &umr_bitfield_default },
	 { "MULTICHANNEL45_ENABLE", 16, 16, &umr_bitfield_default },
	 { "MULTICHANNEL45_MUTE", 17, 17, &umr_bitfield_default },
	 { "MULTICHANNEL45_CHANNEL_ID", 20, 23, &umr_bitfield_default },
	 { "MULTICHANNEL67_ENABLE", 24, 24, &umr_bitfield_default },
	 { "MULTICHANNEL67_MUTE", 25, 25, &umr_bitfield_default },
	 { "MULTICHANNEL67_CHANNEL_ID", 28, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC[] = {
	 { "VIDEO_LIPSYNC", 0, 7, &umr_bitfield_default },
	 { "AUDIO_LIPSYNC", 8, 15, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR[] = {
	 { "HBR_CAPABLE", 0, 0, &umr_bitfield_default },
	 { "HBR_ENABLE", 4, 4, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0[] = {
	 { "MANUFACTURER_ID", 0, 15, &umr_bitfield_default },
	 { "PRODUCT_ID", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1[] = {
	 { "SINK_DESCRIPTION_LEN", 0, 7, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2[] = {
	 { "PORT_ID0", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3[] = {
	 { "PORT_ID1", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4[] = {
	 { "DESCRIPTION0", 0, 7, &umr_bitfield_default },
	 { "DESCRIPTION1", 8, 15, &umr_bitfield_default },
	 { "DESCRIPTION2", 16, 23, &umr_bitfield_default },
	 { "DESCRIPTION3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5[] = {
	 { "DESCRIPTION4", 0, 7, &umr_bitfield_default },
	 { "DESCRIPTION5", 8, 15, &umr_bitfield_default },
	 { "DESCRIPTION6", 16, 23, &umr_bitfield_default },
	 { "DESCRIPTION7", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6[] = {
	 { "DESCRIPTION8", 0, 7, &umr_bitfield_default },
	 { "DESCRIPTION9", 8, 15, &umr_bitfield_default },
	 { "DESCRIPTION10", 16, 23, &umr_bitfield_default },
	 { "DESCRIPTION11", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7[] = {
	 { "DESCRIPTION12", 0, 7, &umr_bitfield_default },
	 { "DESCRIPTION13", 8, 15, &umr_bitfield_default },
	 { "DESCRIPTION14", 16, 23, &umr_bitfield_default },
	 { "DESCRIPTION15", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8[] = {
	 { "DESCRIPTION16", 0, 7, &umr_bitfield_default },
	 { "DESCRIPTION17", 8, 15, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL[] = {
	 { "CLOCK_GATING_DISABLE", 0, 0, &umr_bitfield_default },
	 { "CLOCK_ON_STATE", 4, 4, &umr_bitfield_default },
	 { "AUDIO_ENABLED", 31, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE[] = {
	 { "UNSOLICITED_RESPONSE_PAYLOAD", 0, 25, &umr_bitfield_default },
	 { "UNSOLICITED_RESPONSE_FORCE", 28, 28, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT[] = {
	 { "SEQUENCE", 0, 3, &umr_bitfield_default },
	 { "DEFAULT_ASSOCIATION", 4, 7, &umr_bitfield_default },
	 { "MISC", 8, 11, &umr_bitfield_default },
	 { "COLOR", 12, 15, &umr_bitfield_default },
	 { "CONNECTION_TYPE", 16, 19, &umr_bitfield_default },
	 { "DEFAULT_DEVICE", 20, 23, &umr_bitfield_default },
	 { "LOCATION", 24, 29, &umr_bitfield_default },
	 { "PORT_CONNECTIVITY", 30, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2[] = {
	 { "MULTICHANNEL1_ENABLE", 0, 0, &umr_bitfield_default },
	 { "MULTICHANNEL1_MUTE", 1, 1, &umr_bitfield_default },
	 { "MULTICHANNEL1_CHANNEL_ID", 4, 7, &umr_bitfield_default },
	 { "MULTICHANNEL3_ENABLE", 8, 8, &umr_bitfield_default },
	 { "MULTICHANNEL3_MUTE", 9, 9, &umr_bitfield_default },
	 { "MULTICHANNEL3_CHANNEL_ID", 12, 15, &umr_bitfield_default },
	 { "MULTICHANNEL5_ENABLE", 16, 16, &umr_bitfield_default },
	 { "MULTICHANNEL5_MUTE", 17, 17, &umr_bitfield_default },
	 { "MULTICHANNEL5_CHANNEL_ID", 20, 23, &umr_bitfield_default },
	 { "MULTICHANNEL7_ENABLE", 24, 24, &umr_bitfield_default },
	 { "MULTICHANNEL7_MUTE", 25, 25, &umr_bitfield_default },
	 { "MULTICHANNEL7_CHANNEL_ID", 28, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE[] = {
	 { "MULTICHANNEL_MODE", 0, 0, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0[] = {
	 { "IEC_60958_CS_MODE", 0, 1, &umr_bitfield_default },
	 { "IEC_60958_CS_SOURCE_NUMBER", 2, 5, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1[] = {
	 { "IEC_60958_CS_CLOCK_ACCURACY", 0, 1, &umr_bitfield_default },
	 { "IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN", 2, 2, &umr_bitfield_default },
	 { "IEC_60958_CS_WORD_LENGTH", 3, 6, &umr_bitfield_default },
	 { "IEC_60958_CS_WORD_LENGTH_OVRRD_EN", 7, 7, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2[] = {
	 { "IEC_60958_CS_SAMPLING_FREQUENCY", 0, 5, &umr_bitfield_default },
	 { "IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN", 6, 6, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3[] = {
	 { "IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY", 0, 3, &umr_bitfield_default },
	 { "IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN", 4, 4, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4[] = {
	 { "IEC_60958_CS_SAMPLING_FREQUENCY_COEFF", 0, 3, &umr_bitfield_default },
	 { "IEC_60958_CS_MPEG_SURROUND_INFO", 4, 4, &umr_bitfield_default },
	 { "IEC_60958_CS_CGMS_A", 5, 6, &umr_bitfield_default },
	 { "IEC_60958_CS_CGMS_A_VALID", 7, 7, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5[] = {
	 { "IEC_60958_CS_CHANNEL_NUMBER_L", 0, 3, &umr_bitfield_default },
	 { "IEC_60958_CS_CHANNEL_NUMBER_R", 4, 7, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6[] = {
	 { "IEC_60958_CS_CHANNEL_NUMBER_2", 0, 3, &umr_bitfield_default },
	 { "IEC_60958_CS_CHANNEL_NUMBER_3", 4, 7, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7[] = {
	 { "IEC_60958_CS_CHANNEL_NUMBER_4", 0, 3, &umr_bitfield_default },
	 { "IEC_60958_CS_CHANNEL_NUMBER_5", 4, 7, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8[] = {
	 { "IEC_60958_CS_CHANNEL_NUMBER_6", 0, 3, &umr_bitfield_default },
	 { "IEC_60958_CS_CHANNEL_NUMBER_7", 4, 7, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO[] = {
	 { "ASSOCIATION_INFO", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS[] = {
	 { "OUTPUT_ACTIVE", 0, 0, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL[] = {
	 { "LPIB_SNAPSHOT_LOCK", 0, 0, &umr_bitfield_default },
	 { "CYCLIC_BUFFER_WRAP_COUNT", 8, 15, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB[] = {
	 { "LPIB", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT[] = {
	 { "LPIB_TIMER_SNAPSHOT", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE[] = {
	 { "CODING_TYPE", 0, 7, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED[] = {
	 { "FORMAT_CHANGED", 0, 0, &umr_bitfield_default },
	 { "FORMAT_CHANGED_ACK_UR_ENABLE", 1, 1, &umr_bitfield_default },
	 { "FORMAT_CHANGE_REASON", 8, 15, &umr_bitfield_default },
	 { "FORMAT_CHANGE_RESPONSE", 16, 23, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION[] = {
	 { "WIRELESS_DISPLAY_IDENTIFICATION", 0, 1, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE[] = {
	 { "REMOTE_KEEP_ALIVE_ENABLE", 0, 0, &umr_bitfield_default },
	 { "REMOTE_KEEP_ALIVE_CAPABILITY", 4, 4, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT6_AZALIA_F0_AUDIO_ENABLE_STATUS[] = {
	 { "AUDIO_ENABLE_STATUS", 0, 0, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT6_AZALIA_F0_AUDIO_ENABLED_INT_STATUS[] = {
	 { "AUDIO_ENABLED_FLAG", 0, 0, &umr_bitfield_default },
	 { "AUDIO_ENABLED_MASK", 4, 4, &umr_bitfield_default },
	 { "AUDIO_ENABLED_TYPE", 8, 8, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT6_AZALIA_F0_AUDIO_DISABLED_INT_STATUS[] = {
	 { "AUDIO_DISABLED_FLAG", 0, 0, &umr_bitfield_default },
	 { "AUDIO_DISABLED_MASK", 4, 4, &umr_bitfield_default },
	 { "AUDIO_DISABLED_TYPE", 8, 8, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT6_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS[] = {
	 { "AUDIO_FORMAT_CHANGED_FLAG", 0, 0, &umr_bitfield_default },
	 { "AUDIO_FORMAT_CHANGED_MASK", 4, 4, &umr_bitfield_default },
	 { "AUDIO_FORMAT_CHANGED_TYPE", 8, 8, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES[] = {
	 { "AUDIO_CHANNEL_CAPABILITIES", 0, 0, &umr_bitfield_default },
	 { "INPUT_AMPLIFIER_PRESENT", 1, 1, &umr_bitfield_default },
	 { "OUTPUT_AMPLIFIER_PRESENT", 2, 2, &umr_bitfield_default },
	 { "AMPLIFIER_PARAMETER_OVERRIDE", 3, 3, &umr_bitfield_default },
	 { "FORMAT_OVERRIDE", 4, 4, &umr_bitfield_default },
	 { "STRIPE", 5, 5, &umr_bitfield_default },
	 { "PROCESSING_WIDGET", 6, 6, &umr_bitfield_default },
	 { "UNSOLICITED_RESPONSE_CAPABILITY", 7, 7, &umr_bitfield_default },
	 { "CONNECTION_LIST", 8, 8, &umr_bitfield_default },
	 { "DIGITAL", 9, 9, &umr_bitfield_default },
	 { "POWER_CONTROL", 10, 10, &umr_bitfield_default },
	 { "LR_SWAP", 11, 11, &umr_bitfield_default },
	 { "AUDIO_WIDGET_CAPABILITIES_DELAY", 16, 19, &umr_bitfield_default },
	 { "TYPE", 20, 23, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT[] = {
	 { "NUMBER_OF_CHANNELS", 0, 3, &umr_bitfield_default },
	 { "BITS_PER_SAMPLE", 4, 6, &umr_bitfield_default },
	 { "SAMPLE_BASE_DIVISOR", 8, 10, &umr_bitfield_default },
	 { "SAMPLE_BASE_MULTIPLE", 11, 13, &umr_bitfield_default },
	 { "SAMPLE_BASE_RATE", 14, 14, &umr_bitfield_default },
	 { "STREAM_TYPE", 15, 15, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID[] = {
	 { "CHANNEL_ID", 0, 3, &umr_bitfield_default },
	 { "STREAM_ID", 4, 7, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER[] = {
	 { "DIGEN", 0, 0, &umr_bitfield_default },
	 { "V", 1, 1, &umr_bitfield_default },
	 { "VCFG", 2, 2, &umr_bitfield_default },
	 { "PRE", 3, 3, &umr_bitfield_default },
	 { "COPY", 4, 4, &umr_bitfield_default },
	 { "NON_AUDIO", 5, 5, &umr_bitfield_default },
	 { "PRO", 6, 6, &umr_bitfield_default },
	 { "L", 7, 7, &umr_bitfield_default },
	 { "CC", 8, 14, &umr_bitfield_default },
	 { "KEEPALIVE", 23, 23, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS[] = {
	 { "STREAM_FORMATS", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES[] = {
	 { "AUDIO_RATE_CAPABILITIES", 0, 11, &umr_bitfield_default },
	 { "AUDIO_BIT_CAPABILITIES", 16, 20, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL[] = {
	 { "STRIPE_CONTROL", 0, 1, &umr_bitfield_default },
	 { "STRIPE_CAPABILITY", 20, 22, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE[] = {
	 { "RAMP_RATE", 0, 7, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING[] = {
	 { "PRESENTATION_TIME_EMBEDDING_ENABLE", 0, 0, &umr_bitfield_default },
	 { "PRESENTATION_TIME_OFFSET_CHANGED", 1, 1, &umr_bitfield_default },
	 { "CLEAR_GTC_COUNTER_MIN_MAX_DELTA", 2, 2, &umr_bitfield_default },
	 { "PRESENTATION_TIME_EMBEDDING_GROUP", 4, 6, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA[] = {
	 { "GTC_COUNTER_DELTA", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN[] = {
	 { "GTC_COUNTER_DELTA_MIN", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX[] = {
	 { "GTC_COUNTER_DELTA_MAX", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES[] = {
	 { "AUDIO_CHANNEL_CAPABILITIES", 0, 0, &umr_bitfield_default },
	 { "INPUT_AMPLIFIER_PRESENT", 1, 1, &umr_bitfield_default },
	 { "OUTPUT_AMPLIFIER_PRESENT", 2, 2, &umr_bitfield_default },
	 { "AMPLIFIER_PARAMETER_OVERRIDE", 3, 3, &umr_bitfield_default },
	 { "STRIPE", 5, 5, &umr_bitfield_default },
	 { "PROCESSING_WIDGET", 6, 6, &umr_bitfield_default },
	 { "UNSOLICITED_RESPONSE_CAPABILITY", 7, 7, &umr_bitfield_default },
	 { "CONNECTION_LIST", 8, 8, &umr_bitfield_default },
	 { "DIGITAL", 9, 9, &umr_bitfield_default },
	 { "POWER_CONTROL", 10, 10, &umr_bitfield_default },
	 { "LR_SWAP", 11, 11, &umr_bitfield_default },
	 { "AUDIO_WIDGET_CAPABILITIES_DELAY", 16, 19, &umr_bitfield_default },
	 { "TYPE", 20, 23, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES[] = {
	 { "IMPEDANCE_SENSE_CAPABLE", 0, 0, &umr_bitfield_default },
	 { "TRIGGER_REQUIRED", 1, 1, &umr_bitfield_default },
	 { "JACK_DETECTION_CAPABILITY", 2, 2, &umr_bitfield_default },
	 { "HEADPHONE_DRIVE_CAPABLE", 3, 3, &umr_bitfield_default },
	 { "OUTPUT_CAPABLE", 4, 4, &umr_bitfield_default },
	 { "INPUT_CAPABLE", 5, 5, &umr_bitfield_default },
	 { "BALANCED_I_O_PINS", 6, 6, &umr_bitfield_default },
	 { "HDMI", 7, 7, &umr_bitfield_default },
	 { "VREF_CONTROL", 8, 15, &umr_bitfield_default },
	 { "EAPD_CAPABLE", 16, 16, &umr_bitfield_default },
	 { "DP", 24, 24, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE[] = {
	 { "TAG", 0, 5, &umr_bitfield_default },
	 { "ENABLE", 7, 7, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE[] = {
	 { "IMPEDANCE_SENSE", 0, 30, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL[] = {
	 { "OUT_ENABLE", 6, 6, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER[] = {
	 { "SPEAKER_ALLOCATION", 0, 6, &umr_bitfield_default },
	 { "CHANNEL_ALLOCATION", 8, 15, &umr_bitfield_default },
	 { "HDMI_CONNECTION", 16, 16, &umr_bitfield_default },
	 { "DP_CONNECTION", 17, 17, &umr_bitfield_default },
	 { "EXTRA_CONNECTION_INFO", 18, 23, &umr_bitfield_default },
	 { "LFE_PLAYBACK_LEVEL", 24, 25, &umr_bitfield_default },
	 { "LEVEL_SHIFT", 27, 30, &umr_bitfield_default },
	 { "DOWN_MIX_INHIBIT", 31, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0[] = {
	 { "MAX_CHANNELS", 0, 2, &umr_bitfield_default },
	 { "SUPPORTED_FREQUENCIES", 8, 15, &umr_bitfield_default },
	 { "DESCRIPTOR_BYTE_2", 16, 23, &umr_bitfield_default },
	 { "SUPPORTED_FREQUENCIES_STEREO", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1[] = {
	 { "MAX_CHANNELS", 0, 2, &umr_bitfield_default },
	 { "SUPPORTED_FREQUENCIES", 8, 15, &umr_bitfield_default },
	 { "DESCRIPTOR_BYTE_2", 16, 23, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2[] = {
	 { "MAX_CHANNELS", 0, 2, &umr_bitfield_default },
	 { "SUPPORTED_FREQUENCIES", 8, 15, &umr_bitfield_default },
	 { "DESCRIPTOR_BYTE_2", 16, 23, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3[] = {
	 { "MAX_CHANNELS", 0, 2, &umr_bitfield_default },
	 { "SUPPORTED_FREQUENCIES", 8, 15, &umr_bitfield_default },
	 { "DESCRIPTOR_BYTE_2", 16, 23, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4[] = {
	 { "MAX_CHANNELS", 0, 2, &umr_bitfield_default },
	 { "SUPPORTED_FREQUENCIES", 8, 15, &umr_bitfield_default },
	 { "DESCRIPTOR_BYTE_2", 16, 23, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5[] = {
	 { "MAX_CHANNELS", 0, 2, &umr_bitfield_default },
	 { "SUPPORTED_FREQUENCIES", 8, 15, &umr_bitfield_default },
	 { "DESCRIPTOR_BYTE_2", 16, 23, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6[] = {
	 { "MAX_CHANNELS", 0, 2, &umr_bitfield_default },
	 { "SUPPORTED_FREQUENCIES", 8, 15, &umr_bitfield_default },
	 { "DESCRIPTOR_BYTE_2", 16, 23, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7[] = {
	 { "MAX_CHANNELS", 0, 2, &umr_bitfield_default },
	 { "SUPPORTED_FREQUENCIES", 8, 15, &umr_bitfield_default },
	 { "DESCRIPTOR_BYTE_2", 16, 23, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8[] = {
	 { "MAX_CHANNELS", 0, 2, &umr_bitfield_default },
	 { "SUPPORTED_FREQUENCIES", 8, 15, &umr_bitfield_default },
	 { "DESCRIPTOR_BYTE_2", 16, 23, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9[] = {
	 { "MAX_CHANNELS", 0, 2, &umr_bitfield_default },
	 { "SUPPORTED_FREQUENCIES", 8, 15, &umr_bitfield_default },
	 { "DESCRIPTOR_BYTE_2", 16, 23, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10[] = {
	 { "MAX_CHANNELS", 0, 2, &umr_bitfield_default },
	 { "SUPPORTED_FREQUENCIES", 8, 15, &umr_bitfield_default },
	 { "DESCRIPTOR_BYTE_2", 16, 23, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11[] = {
	 { "MAX_CHANNELS", 0, 2, &umr_bitfield_default },
	 { "SUPPORTED_FREQUENCIES", 8, 15, &umr_bitfield_default },
	 { "DESCRIPTOR_BYTE_2", 16, 23, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12[] = {
	 { "MAX_CHANNELS", 0, 2, &umr_bitfield_default },
	 { "SUPPORTED_FREQUENCIES", 8, 15, &umr_bitfield_default },
	 { "DESCRIPTOR_BYTE_2", 16, 23, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13[] = {
	 { "MAX_CHANNELS", 0, 2, &umr_bitfield_default },
	 { "SUPPORTED_FREQUENCIES", 8, 15, &umr_bitfield_default },
	 { "DESCRIPTOR_BYTE_2", 16, 23, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE[] = {
	 { "MULTICHANNEL01_ENABLE", 0, 0, &umr_bitfield_default },
	 { "MULTICHANNEL01_MUTE", 1, 1, &umr_bitfield_default },
	 { "MULTICHANNEL01_CHANNEL_ID", 4, 7, &umr_bitfield_default },
	 { "MULTICHANNEL23_ENABLE", 8, 8, &umr_bitfield_default },
	 { "MULTICHANNEL23_MUTE", 9, 9, &umr_bitfield_default },
	 { "MULTICHANNEL23_CHANNEL_ID", 12, 15, &umr_bitfield_default },
	 { "MULTICHANNEL45_ENABLE", 16, 16, &umr_bitfield_default },
	 { "MULTICHANNEL45_MUTE", 17, 17, &umr_bitfield_default },
	 { "MULTICHANNEL45_CHANNEL_ID", 20, 23, &umr_bitfield_default },
	 { "MULTICHANNEL67_ENABLE", 24, 24, &umr_bitfield_default },
	 { "MULTICHANNEL67_MUTE", 25, 25, &umr_bitfield_default },
	 { "MULTICHANNEL67_CHANNEL_ID", 28, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC[] = {
	 { "VIDEO_LIPSYNC", 0, 7, &umr_bitfield_default },
	 { "AUDIO_LIPSYNC", 8, 15, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR[] = {
	 { "HBR_CAPABLE", 0, 0, &umr_bitfield_default },
	 { "HBR_ENABLE", 4, 4, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0[] = {
	 { "MANUFACTURER_ID", 0, 15, &umr_bitfield_default },
	 { "PRODUCT_ID", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1[] = {
	 { "SINK_DESCRIPTION_LEN", 0, 7, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2[] = {
	 { "PORT_ID0", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3[] = {
	 { "PORT_ID1", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4[] = {
	 { "DESCRIPTION0", 0, 7, &umr_bitfield_default },
	 { "DESCRIPTION1", 8, 15, &umr_bitfield_default },
	 { "DESCRIPTION2", 16, 23, &umr_bitfield_default },
	 { "DESCRIPTION3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5[] = {
	 { "DESCRIPTION4", 0, 7, &umr_bitfield_default },
	 { "DESCRIPTION5", 8, 15, &umr_bitfield_default },
	 { "DESCRIPTION6", 16, 23, &umr_bitfield_default },
	 { "DESCRIPTION7", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6[] = {
	 { "DESCRIPTION8", 0, 7, &umr_bitfield_default },
	 { "DESCRIPTION9", 8, 15, &umr_bitfield_default },
	 { "DESCRIPTION10", 16, 23, &umr_bitfield_default },
	 { "DESCRIPTION11", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7[] = {
	 { "DESCRIPTION12", 0, 7, &umr_bitfield_default },
	 { "DESCRIPTION13", 8, 15, &umr_bitfield_default },
	 { "DESCRIPTION14", 16, 23, &umr_bitfield_default },
	 { "DESCRIPTION15", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8[] = {
	 { "DESCRIPTION16", 0, 7, &umr_bitfield_default },
	 { "DESCRIPTION17", 8, 15, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL[] = {
	 { "CLOCK_GATING_DISABLE", 0, 0, &umr_bitfield_default },
	 { "CLOCK_ON_STATE", 4, 4, &umr_bitfield_default },
	 { "AUDIO_ENABLED", 31, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE[] = {
	 { "UNSOLICITED_RESPONSE_PAYLOAD", 0, 25, &umr_bitfield_default },
	 { "UNSOLICITED_RESPONSE_FORCE", 28, 28, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT[] = {
	 { "SEQUENCE", 0, 3, &umr_bitfield_default },
	 { "DEFAULT_ASSOCIATION", 4, 7, &umr_bitfield_default },
	 { "MISC", 8, 11, &umr_bitfield_default },
	 { "COLOR", 12, 15, &umr_bitfield_default },
	 { "CONNECTION_TYPE", 16, 19, &umr_bitfield_default },
	 { "DEFAULT_DEVICE", 20, 23, &umr_bitfield_default },
	 { "LOCATION", 24, 29, &umr_bitfield_default },
	 { "PORT_CONNECTIVITY", 30, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2[] = {
	 { "MULTICHANNEL1_ENABLE", 0, 0, &umr_bitfield_default },
	 { "MULTICHANNEL1_MUTE", 1, 1, &umr_bitfield_default },
	 { "MULTICHANNEL1_CHANNEL_ID", 4, 7, &umr_bitfield_default },
	 { "MULTICHANNEL3_ENABLE", 8, 8, &umr_bitfield_default },
	 { "MULTICHANNEL3_MUTE", 9, 9, &umr_bitfield_default },
	 { "MULTICHANNEL3_CHANNEL_ID", 12, 15, &umr_bitfield_default },
	 { "MULTICHANNEL5_ENABLE", 16, 16, &umr_bitfield_default },
	 { "MULTICHANNEL5_MUTE", 17, 17, &umr_bitfield_default },
	 { "MULTICHANNEL5_CHANNEL_ID", 20, 23, &umr_bitfield_default },
	 { "MULTICHANNEL7_ENABLE", 24, 24, &umr_bitfield_default },
	 { "MULTICHANNEL7_MUTE", 25, 25, &umr_bitfield_default },
	 { "MULTICHANNEL7_CHANNEL_ID", 28, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE[] = {
	 { "MULTICHANNEL_MODE", 0, 0, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0[] = {
	 { "IEC_60958_CS_MODE", 0, 1, &umr_bitfield_default },
	 { "IEC_60958_CS_SOURCE_NUMBER", 2, 5, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1[] = {
	 { "IEC_60958_CS_CLOCK_ACCURACY", 0, 1, &umr_bitfield_default },
	 { "IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN", 2, 2, &umr_bitfield_default },
	 { "IEC_60958_CS_WORD_LENGTH", 3, 6, &umr_bitfield_default },
	 { "IEC_60958_CS_WORD_LENGTH_OVRRD_EN", 7, 7, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2[] = {
	 { "IEC_60958_CS_SAMPLING_FREQUENCY", 0, 5, &umr_bitfield_default },
	 { "IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN", 6, 6, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3[] = {
	 { "IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY", 0, 3, &umr_bitfield_default },
	 { "IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN", 4, 4, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4[] = {
	 { "IEC_60958_CS_SAMPLING_FREQUENCY_COEFF", 0, 3, &umr_bitfield_default },
	 { "IEC_60958_CS_MPEG_SURROUND_INFO", 4, 4, &umr_bitfield_default },
	 { "IEC_60958_CS_CGMS_A", 5, 6, &umr_bitfield_default },
	 { "IEC_60958_CS_CGMS_A_VALID", 7, 7, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5[] = {
	 { "IEC_60958_CS_CHANNEL_NUMBER_L", 0, 3, &umr_bitfield_default },
	 { "IEC_60958_CS_CHANNEL_NUMBER_R", 4, 7, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6[] = {
	 { "IEC_60958_CS_CHANNEL_NUMBER_2", 0, 3, &umr_bitfield_default },
	 { "IEC_60958_CS_CHANNEL_NUMBER_3", 4, 7, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7[] = {
	 { "IEC_60958_CS_CHANNEL_NUMBER_4", 0, 3, &umr_bitfield_default },
	 { "IEC_60958_CS_CHANNEL_NUMBER_5", 4, 7, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8[] = {
	 { "IEC_60958_CS_CHANNEL_NUMBER_6", 0, 3, &umr_bitfield_default },
	 { "IEC_60958_CS_CHANNEL_NUMBER_7", 4, 7, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO[] = {
	 { "ASSOCIATION_INFO", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS[] = {
	 { "OUTPUT_ACTIVE", 0, 0, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL[] = {
	 { "LPIB_SNAPSHOT_LOCK", 0, 0, &umr_bitfield_default },
	 { "CYCLIC_BUFFER_WRAP_COUNT", 8, 15, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB[] = {
	 { "LPIB", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT[] = {
	 { "LPIB_TIMER_SNAPSHOT", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE[] = {
	 { "CODING_TYPE", 0, 7, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED[] = {
	 { "FORMAT_CHANGED", 0, 0, &umr_bitfield_default },
	 { "FORMAT_CHANGED_ACK_UR_ENABLE", 1, 1, &umr_bitfield_default },
	 { "FORMAT_CHANGE_REASON", 8, 15, &umr_bitfield_default },
	 { "FORMAT_CHANGE_RESPONSE", 16, 23, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION[] = {
	 { "WIRELESS_DISPLAY_IDENTIFICATION", 0, 1, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE[] = {
	 { "REMOTE_KEEP_ALIVE_ENABLE", 0, 0, &umr_bitfield_default },
	 { "REMOTE_KEEP_ALIVE_CAPABILITY", 4, 4, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT7_AZALIA_F0_AUDIO_ENABLE_STATUS[] = {
	 { "AUDIO_ENABLE_STATUS", 0, 0, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT7_AZALIA_F0_AUDIO_ENABLED_INT_STATUS[] = {
	 { "AUDIO_ENABLED_FLAG", 0, 0, &umr_bitfield_default },
	 { "AUDIO_ENABLED_MASK", 4, 4, &umr_bitfield_default },
	 { "AUDIO_ENABLED_TYPE", 8, 8, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT7_AZALIA_F0_AUDIO_DISABLED_INT_STATUS[] = {
	 { "AUDIO_DISABLED_FLAG", 0, 0, &umr_bitfield_default },
	 { "AUDIO_DISABLED_MASK", 4, 4, &umr_bitfield_default },
	 { "AUDIO_DISABLED_TYPE", 8, 8, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0ENDPOINT7_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS[] = {
	 { "AUDIO_FORMAT_CHANGED_FLAG", 0, 0, &umr_bitfield_default },
	 { "AUDIO_FORMAT_CHANGED_MASK", 4, 4, &umr_bitfield_default },
	 { "AUDIO_FORMAT_CHANGED_TYPE", 8, 8, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES[] = {
	 { "AUDIO_CHANNEL_CAPABILITIES", 0, 0, &umr_bitfield_default },
	 { "INPUT_AMPLIFIER_PRESENT", 1, 1, &umr_bitfield_default },
	 { "OUTPUT_AMPLIFIER_PRESENT", 2, 2, &umr_bitfield_default },
	 { "AMPLIFIER_PARAMETER_OVERRIDE", 3, 3, &umr_bitfield_default },
	 { "FORMAT_OVERRIDE", 4, 4, &umr_bitfield_default },
	 { "STRIPE", 5, 5, &umr_bitfield_default },
	 { "PROCESSING_WIDGET", 6, 6, &umr_bitfield_default },
	 { "UNSOLICITED_RESPONSE_CAPABILITY", 7, 7, &umr_bitfield_default },
	 { "CONNECTION_LIST", 8, 8, &umr_bitfield_default },
	 { "DIGITAL", 9, 9, &umr_bitfield_default },
	 { "POWER_CONTROL", 10, 10, &umr_bitfield_default },
	 { "LR_SWAP", 11, 11, &umr_bitfield_default },
	 { "AUDIO_WIDGET_CAPABILITIES_DELAY", 16, 19, &umr_bitfield_default },
	 { "TYPE", 20, 23, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT[] = {
	 { "NUMBER_OF_CHANNELS", 0, 3, &umr_bitfield_default },
	 { "BITS_PER_SAMPLE", 4, 6, &umr_bitfield_default },
	 { "SAMPLE_BASE_DIVISOR", 8, 10, &umr_bitfield_default },
	 { "SAMPLE_BASE_MULTIPLE", 11, 13, &umr_bitfield_default },
	 { "SAMPLE_BASE_RATE", 14, 14, &umr_bitfield_default },
	 { "STREAM_TYPE", 15, 15, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID[] = {
	 { "CHANNEL_ID", 0, 3, &umr_bitfield_default },
	 { "STREAM_ID", 4, 7, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER[] = {
	 { "DIGEN", 0, 0, &umr_bitfield_default },
	 { "V", 1, 1, &umr_bitfield_default },
	 { "VCFG", 2, 2, &umr_bitfield_default },
	 { "PRE", 3, 3, &umr_bitfield_default },
	 { "COPY", 4, 4, &umr_bitfield_default },
	 { "NON_AUDIO", 5, 5, &umr_bitfield_default },
	 { "PRO", 6, 6, &umr_bitfield_default },
	 { "L", 7, 7, &umr_bitfield_default },
	 { "CC", 8, 14, &umr_bitfield_default },
	 { "KEEPALIVE", 23, 23, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS[] = {
	 { "STREAM_FORMATS", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES[] = {
	 { "AUDIO_RATE_CAPABILITIES", 0, 11, &umr_bitfield_default },
	 { "AUDIO_BIT_CAPABILITIES", 16, 20, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES[] = {
	 { "AUDIO_CHANNEL_CAPABILITIES", 0, 0, &umr_bitfield_default },
	 { "INPUT_AMPLIFIER_PRESENT", 1, 1, &umr_bitfield_default },
	 { "OUTPUT_AMPLIFIER_PRESENT", 2, 2, &umr_bitfield_default },
	 { "AMPLIFIER_PARAMETER_OVERRIDE", 3, 3, &umr_bitfield_default },
	 { "STRIPE", 5, 5, &umr_bitfield_default },
	 { "PROCESSING_WIDGET", 6, 6, &umr_bitfield_default },
	 { "UNSOLICITED_RESPONSE_CAPABILITY", 7, 7, &umr_bitfield_default },
	 { "CONNECTION_LIST", 8, 8, &umr_bitfield_default },
	 { "DIGITAL", 9, 9, &umr_bitfield_default },
	 { "POWER_CONTROL", 10, 10, &umr_bitfield_default },
	 { "LR_SWAP", 11, 11, &umr_bitfield_default },
	 { "AUDIO_WIDGET_CAPABILITIES_DELAY", 16, 19, &umr_bitfield_default },
	 { "TYPE", 20, 23, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES[] = {
	 { "IMPEDANCE_SENSE_CAPABLE", 0, 0, &umr_bitfield_default },
	 { "TRIGGER_REQUIRED", 1, 1, &umr_bitfield_default },
	 { "JACK_DETECTION_CAPABILITY", 2, 2, &umr_bitfield_default },
	 { "HEADPHONE_DRIVE_CAPABLE", 3, 3, &umr_bitfield_default },
	 { "OUTPUT_CAPABLE", 4, 4, &umr_bitfield_default },
	 { "INPUT_CAPABLE", 5, 5, &umr_bitfield_default },
	 { "BALANCED_I_O_PINS", 6, 6, &umr_bitfield_default },
	 { "HDMI", 7, 7, &umr_bitfield_default },
	 { "VREF_CONTROL", 8, 15, &umr_bitfield_default },
	 { "EAPD_CAPABLE", 16, 16, &umr_bitfield_default },
	 { "DP", 24, 24, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE[] = {
	 { "TAG", 0, 5, &umr_bitfield_default },
	 { "ENABLE", 7, 7, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE[] = {
	 { "IMPEDANCE_SENSE", 0, 30, &umr_bitfield_default },
	 { "PRESENCE_DETECT", 31, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL[] = {
	 { "IN_ENABLE", 5, 5, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE[] = {
	 { "MULTICHANNEL0_ENABLE", 0, 0, &umr_bitfield_default },
	 { "MULTICHANNEL0_MUTE", 1, 1, &umr_bitfield_default },
	 { "MULTICHANNEL0_CHANNEL_ID", 4, 7, &umr_bitfield_default },
	 { "MULTICHANNEL1_ENABLE", 8, 8, &umr_bitfield_default },
	 { "MULTICHANNEL1_MUTE", 9, 9, &umr_bitfield_default },
	 { "MULTICHANNEL1_CHANNEL_ID", 12, 15, &umr_bitfield_default },
	 { "MULTICHANNEL2_ENABLE", 16, 16, &umr_bitfield_default },
	 { "MULTICHANNEL2_MUTE", 17, 17, &umr_bitfield_default },
	 { "MULTICHANNEL2_CHANNEL_ID", 20, 23, &umr_bitfield_default },
	 { "MULTICHANNEL3_ENABLE", 24, 24, &umr_bitfield_default },
	 { "MULTICHANNEL3_MUTE", 25, 25, &umr_bitfield_default },
	 { "MULTICHANNEL3_CHANNEL_ID", 28, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2[] = {
	 { "MULTICHANNEL4_ENABLE", 0, 0, &umr_bitfield_default },
	 { "MULTICHANNEL4_MUTE", 1, 1, &umr_bitfield_default },
	 { "MULTICHANNEL4_CHANNEL_ID", 4, 7, &umr_bitfield_default },
	 { "MULTICHANNEL5_ENABLE", 8, 8, &umr_bitfield_default },
	 { "MULTICHANNEL5_MUTE", 9, 9, &umr_bitfield_default },
	 { "MULTICHANNEL5_CHANNEL_ID", 12, 15, &umr_bitfield_default },
	 { "MULTICHANNEL6_ENABLE", 16, 16, &umr_bitfield_default },
	 { "MULTICHANNEL6_MUTE", 17, 17, &umr_bitfield_default },
	 { "MULTICHANNEL6_CHANNEL_ID", 20, 23, &umr_bitfield_default },
	 { "MULTICHANNEL7_ENABLE", 24, 24, &umr_bitfield_default },
	 { "MULTICHANNEL7_MUTE", 25, 25, &umr_bitfield_default },
	 { "MULTICHANNEL7_CHANNEL_ID", 28, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR[] = {
	 { "HBR_CAPABLE", 0, 0, &umr_bitfield_default },
	 { "HBR_ENABLE", 4, 4, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION[] = {
	 { "CHANNEL_ALLOCATION", 0, 7, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL[] = {
	 { "CLOCK_GATING_DISABLE", 0, 0, &umr_bitfield_default },
	 { "CLOCK_ON_STATE", 4, 4, &umr_bitfield_default },
	 { "AUDIO_ENABLED", 31, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE[] = {
	 { "UNSOLICITED_RESPONSE_PAYLOAD", 0, 25, &umr_bitfield_default },
	 { "UNSOLICITED_RESPONSE_FORCE", 28, 28, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT[] = {
	 { "SEQUENCE", 0, 3, &umr_bitfield_default },
	 { "DEFAULT_ASSOCIATION", 4, 7, &umr_bitfield_default },
	 { "MISC", 8, 11, &umr_bitfield_default },
	 { "COLOR", 12, 15, &umr_bitfield_default },
	 { "CONNECTION_TYPE", 16, 19, &umr_bitfield_default },
	 { "DEFAULT_DEVICE", 20, 23, &umr_bitfield_default },
	 { "LOCATION", 24, 29, &umr_bitfield_default },
	 { "PORT_CONNECTIVITY", 30, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL[] = {
	 { "LPIB_SNAPSHOT_LOCK", 0, 0, &umr_bitfield_default },
	 { "CYCLIC_BUFFER_WRAP_COUNT", 8, 15, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB[] = {
	 { "LPIB", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT[] = {
	 { "LPIB_TIMER_SNAPSHOT", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL[] = {
	 { "INPUT_ACTIVITY", 0, 0, &umr_bitfield_default },
	 { "CHANNEL_LAYOUT", 1, 2, &umr_bitfield_default },
	 { "INPUT_ACTIVITY_UR_ENABLE", 4, 4, &umr_bitfield_default },
	 { "INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE", 5, 5, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME[] = {
	 { "CHANNEL_COUNT", 0, 2, &umr_bitfield_default },
	 { "CHANNEL_ALLOCATION", 8, 15, &umr_bitfield_default },
	 { "INFOFRAME_BYTE_5", 16, 23, &umr_bitfield_default },
	 { "INFOFRAME_VALID", 31, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES[] = {
	 { "AUDIO_CHANNEL_CAPABILITIES", 0, 0, &umr_bitfield_default },
	 { "INPUT_AMPLIFIER_PRESENT", 1, 1, &umr_bitfield_default },
	 { "OUTPUT_AMPLIFIER_PRESENT", 2, 2, &umr_bitfield_default },
	 { "AMPLIFIER_PARAMETER_OVERRIDE", 3, 3, &umr_bitfield_default },
	 { "FORMAT_OVERRIDE", 4, 4, &umr_bitfield_default },
	 { "STRIPE", 5, 5, &umr_bitfield_default },
	 { "PROCESSING_WIDGET", 6, 6, &umr_bitfield_default },
	 { "UNSOLICITED_RESPONSE_CAPABILITY", 7, 7, &umr_bitfield_default },
	 { "CONNECTION_LIST", 8, 8, &umr_bitfield_default },
	 { "DIGITAL", 9, 9, &umr_bitfield_default },
	 { "POWER_CONTROL", 10, 10, &umr_bitfield_default },
	 { "LR_SWAP", 11, 11, &umr_bitfield_default },
	 { "AUDIO_WIDGET_CAPABILITIES_DELAY", 16, 19, &umr_bitfield_default },
	 { "TYPE", 20, 23, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT[] = {
	 { "NUMBER_OF_CHANNELS", 0, 3, &umr_bitfield_default },
	 { "BITS_PER_SAMPLE", 4, 6, &umr_bitfield_default },
	 { "SAMPLE_BASE_DIVISOR", 8, 10, &umr_bitfield_default },
	 { "SAMPLE_BASE_MULTIPLE", 11, 13, &umr_bitfield_default },
	 { "SAMPLE_BASE_RATE", 14, 14, &umr_bitfield_default },
	 { "STREAM_TYPE", 15, 15, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID[] = {
	 { "CHANNEL_ID", 0, 3, &umr_bitfield_default },
	 { "STREAM_ID", 4, 7, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER[] = {
	 { "DIGEN", 0, 0, &umr_bitfield_default },
	 { "V", 1, 1, &umr_bitfield_default },
	 { "VCFG", 2, 2, &umr_bitfield_default },
	 { "PRE", 3, 3, &umr_bitfield_default },
	 { "COPY", 4, 4, &umr_bitfield_default },
	 { "NON_AUDIO", 5, 5, &umr_bitfield_default },
	 { "PRO", 6, 6, &umr_bitfield_default },
	 { "L", 7, 7, &umr_bitfield_default },
	 { "CC", 8, 14, &umr_bitfield_default },
	 { "KEEPALIVE", 23, 23, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS[] = {
	 { "STREAM_FORMATS", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES[] = {
	 { "AUDIO_RATE_CAPABILITIES", 0, 11, &umr_bitfield_default },
	 { "AUDIO_BIT_CAPABILITIES", 16, 20, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES[] = {
	 { "AUDIO_CHANNEL_CAPABILITIES", 0, 0, &umr_bitfield_default },
	 { "INPUT_AMPLIFIER_PRESENT", 1, 1, &umr_bitfield_default },
	 { "OUTPUT_AMPLIFIER_PRESENT", 2, 2, &umr_bitfield_default },
	 { "AMPLIFIER_PARAMETER_OVERRIDE", 3, 3, &umr_bitfield_default },
	 { "STRIPE", 5, 5, &umr_bitfield_default },
	 { "PROCESSING_WIDGET", 6, 6, &umr_bitfield_default },
	 { "UNSOLICITED_RESPONSE_CAPABILITY", 7, 7, &umr_bitfield_default },
	 { "CONNECTION_LIST", 8, 8, &umr_bitfield_default },
	 { "DIGITAL", 9, 9, &umr_bitfield_default },
	 { "POWER_CONTROL", 10, 10, &umr_bitfield_default },
	 { "LR_SWAP", 11, 11, &umr_bitfield_default },
	 { "AUDIO_WIDGET_CAPABILITIES_DELAY", 16, 19, &umr_bitfield_default },
	 { "TYPE", 20, 23, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES[] = {
	 { "IMPEDANCE_SENSE_CAPABLE", 0, 0, &umr_bitfield_default },
	 { "TRIGGER_REQUIRED", 1, 1, &umr_bitfield_default },
	 { "JACK_DETECTION_CAPABILITY", 2, 2, &umr_bitfield_default },
	 { "HEADPHONE_DRIVE_CAPABLE", 3, 3, &umr_bitfield_default },
	 { "OUTPUT_CAPABLE", 4, 4, &umr_bitfield_default },
	 { "INPUT_CAPABLE", 5, 5, &umr_bitfield_default },
	 { "BALANCED_I_O_PINS", 6, 6, &umr_bitfield_default },
	 { "HDMI", 7, 7, &umr_bitfield_default },
	 { "VREF_CONTROL", 8, 15, &umr_bitfield_default },
	 { "EAPD_CAPABLE", 16, 16, &umr_bitfield_default },
	 { "DP", 24, 24, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE[] = {
	 { "TAG", 0, 5, &umr_bitfield_default },
	 { "ENABLE", 7, 7, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE[] = {
	 { "IMPEDANCE_SENSE", 0, 30, &umr_bitfield_default },
	 { "PRESENCE_DETECT", 31, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL[] = {
	 { "IN_ENABLE", 5, 5, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE[] = {
	 { "MULTICHANNEL0_ENABLE", 0, 0, &umr_bitfield_default },
	 { "MULTICHANNEL0_MUTE", 1, 1, &umr_bitfield_default },
	 { "MULTICHANNEL0_CHANNEL_ID", 4, 7, &umr_bitfield_default },
	 { "MULTICHANNEL1_ENABLE", 8, 8, &umr_bitfield_default },
	 { "MULTICHANNEL1_MUTE", 9, 9, &umr_bitfield_default },
	 { "MULTICHANNEL1_CHANNEL_ID", 12, 15, &umr_bitfield_default },
	 { "MULTICHANNEL2_ENABLE", 16, 16, &umr_bitfield_default },
	 { "MULTICHANNEL2_MUTE", 17, 17, &umr_bitfield_default },
	 { "MULTICHANNEL2_CHANNEL_ID", 20, 23, &umr_bitfield_default },
	 { "MULTICHANNEL3_ENABLE", 24, 24, &umr_bitfield_default },
	 { "MULTICHANNEL3_MUTE", 25, 25, &umr_bitfield_default },
	 { "MULTICHANNEL3_CHANNEL_ID", 28, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2[] = {
	 { "MULTICHANNEL4_ENABLE", 0, 0, &umr_bitfield_default },
	 { "MULTICHANNEL4_MUTE", 1, 1, &umr_bitfield_default },
	 { "MULTICHANNEL4_CHANNEL_ID", 4, 7, &umr_bitfield_default },
	 { "MULTICHANNEL5_ENABLE", 8, 8, &umr_bitfield_default },
	 { "MULTICHANNEL5_MUTE", 9, 9, &umr_bitfield_default },
	 { "MULTICHANNEL5_CHANNEL_ID", 12, 15, &umr_bitfield_default },
	 { "MULTICHANNEL6_ENABLE", 16, 16, &umr_bitfield_default },
	 { "MULTICHANNEL6_MUTE", 17, 17, &umr_bitfield_default },
	 { "MULTICHANNEL6_CHANNEL_ID", 20, 23, &umr_bitfield_default },
	 { "MULTICHANNEL7_ENABLE", 24, 24, &umr_bitfield_default },
	 { "MULTICHANNEL7_MUTE", 25, 25, &umr_bitfield_default },
	 { "MULTICHANNEL7_CHANNEL_ID", 28, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR[] = {
	 { "HBR_CAPABLE", 0, 0, &umr_bitfield_default },
	 { "HBR_ENABLE", 4, 4, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION[] = {
	 { "CHANNEL_ALLOCATION", 0, 7, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL[] = {
	 { "CLOCK_GATING_DISABLE", 0, 0, &umr_bitfield_default },
	 { "CLOCK_ON_STATE", 4, 4, &umr_bitfield_default },
	 { "AUDIO_ENABLED", 31, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE[] = {
	 { "UNSOLICITED_RESPONSE_PAYLOAD", 0, 25, &umr_bitfield_default },
	 { "UNSOLICITED_RESPONSE_FORCE", 28, 28, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT[] = {
	 { "SEQUENCE", 0, 3, &umr_bitfield_default },
	 { "DEFAULT_ASSOCIATION", 4, 7, &umr_bitfield_default },
	 { "MISC", 8, 11, &umr_bitfield_default },
	 { "COLOR", 12, 15, &umr_bitfield_default },
	 { "CONNECTION_TYPE", 16, 19, &umr_bitfield_default },
	 { "DEFAULT_DEVICE", 20, 23, &umr_bitfield_default },
	 { "LOCATION", 24, 29, &umr_bitfield_default },
	 { "PORT_CONNECTIVITY", 30, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL[] = {
	 { "LPIB_SNAPSHOT_LOCK", 0, 0, &umr_bitfield_default },
	 { "CYCLIC_BUFFER_WRAP_COUNT", 8, 15, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB[] = {
	 { "LPIB", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT[] = {
	 { "LPIB_TIMER_SNAPSHOT", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL[] = {
	 { "INPUT_ACTIVITY", 0, 0, &umr_bitfield_default },
	 { "CHANNEL_LAYOUT", 1, 2, &umr_bitfield_default },
	 { "INPUT_ACTIVITY_UR_ENABLE", 4, 4, &umr_bitfield_default },
	 { "INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE", 5, 5, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME[] = {
	 { "CHANNEL_COUNT", 0, 2, &umr_bitfield_default },
	 { "CHANNEL_ALLOCATION", 8, 15, &umr_bitfield_default },
	 { "INFOFRAME_BYTE_5", 16, 23, &umr_bitfield_default },
	 { "INFOFRAME_VALID", 31, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES[] = {
	 { "AUDIO_CHANNEL_CAPABILITIES", 0, 0, &umr_bitfield_default },
	 { "INPUT_AMPLIFIER_PRESENT", 1, 1, &umr_bitfield_default },
	 { "OUTPUT_AMPLIFIER_PRESENT", 2, 2, &umr_bitfield_default },
	 { "AMPLIFIER_PARAMETER_OVERRIDE", 3, 3, &umr_bitfield_default },
	 { "FORMAT_OVERRIDE", 4, 4, &umr_bitfield_default },
	 { "STRIPE", 5, 5, &umr_bitfield_default },
	 { "PROCESSING_WIDGET", 6, 6, &umr_bitfield_default },
	 { "UNSOLICITED_RESPONSE_CAPABILITY", 7, 7, &umr_bitfield_default },
	 { "CONNECTION_LIST", 8, 8, &umr_bitfield_default },
	 { "DIGITAL", 9, 9, &umr_bitfield_default },
	 { "POWER_CONTROL", 10, 10, &umr_bitfield_default },
	 { "LR_SWAP", 11, 11, &umr_bitfield_default },
	 { "AUDIO_WIDGET_CAPABILITIES_DELAY", 16, 19, &umr_bitfield_default },
	 { "TYPE", 20, 23, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT[] = {
	 { "NUMBER_OF_CHANNELS", 0, 3, &umr_bitfield_default },
	 { "BITS_PER_SAMPLE", 4, 6, &umr_bitfield_default },
	 { "SAMPLE_BASE_DIVISOR", 8, 10, &umr_bitfield_default },
	 { "SAMPLE_BASE_MULTIPLE", 11, 13, &umr_bitfield_default },
	 { "SAMPLE_BASE_RATE", 14, 14, &umr_bitfield_default },
	 { "STREAM_TYPE", 15, 15, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID[] = {
	 { "CHANNEL_ID", 0, 3, &umr_bitfield_default },
	 { "STREAM_ID", 4, 7, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER[] = {
	 { "DIGEN", 0, 0, &umr_bitfield_default },
	 { "V", 1, 1, &umr_bitfield_default },
	 { "VCFG", 2, 2, &umr_bitfield_default },
	 { "PRE", 3, 3, &umr_bitfield_default },
	 { "COPY", 4, 4, &umr_bitfield_default },
	 { "NON_AUDIO", 5, 5, &umr_bitfield_default },
	 { "PRO", 6, 6, &umr_bitfield_default },
	 { "L", 7, 7, &umr_bitfield_default },
	 { "CC", 8, 14, &umr_bitfield_default },
	 { "KEEPALIVE", 23, 23, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS[] = {
	 { "STREAM_FORMATS", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES[] = {
	 { "AUDIO_RATE_CAPABILITIES", 0, 11, &umr_bitfield_default },
	 { "AUDIO_BIT_CAPABILITIES", 16, 20, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES[] = {
	 { "AUDIO_CHANNEL_CAPABILITIES", 0, 0, &umr_bitfield_default },
	 { "INPUT_AMPLIFIER_PRESENT", 1, 1, &umr_bitfield_default },
	 { "OUTPUT_AMPLIFIER_PRESENT", 2, 2, &umr_bitfield_default },
	 { "AMPLIFIER_PARAMETER_OVERRIDE", 3, 3, &umr_bitfield_default },
	 { "STRIPE", 5, 5, &umr_bitfield_default },
	 { "PROCESSING_WIDGET", 6, 6, &umr_bitfield_default },
	 { "UNSOLICITED_RESPONSE_CAPABILITY", 7, 7, &umr_bitfield_default },
	 { "CONNECTION_LIST", 8, 8, &umr_bitfield_default },
	 { "DIGITAL", 9, 9, &umr_bitfield_default },
	 { "POWER_CONTROL", 10, 10, &umr_bitfield_default },
	 { "LR_SWAP", 11, 11, &umr_bitfield_default },
	 { "AUDIO_WIDGET_CAPABILITIES_DELAY", 16, 19, &umr_bitfield_default },
	 { "TYPE", 20, 23, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES[] = {
	 { "IMPEDANCE_SENSE_CAPABLE", 0, 0, &umr_bitfield_default },
	 { "TRIGGER_REQUIRED", 1, 1, &umr_bitfield_default },
	 { "JACK_DETECTION_CAPABILITY", 2, 2, &umr_bitfield_default },
	 { "HEADPHONE_DRIVE_CAPABLE", 3, 3, &umr_bitfield_default },
	 { "OUTPUT_CAPABLE", 4, 4, &umr_bitfield_default },
	 { "INPUT_CAPABLE", 5, 5, &umr_bitfield_default },
	 { "BALANCED_I_O_PINS", 6, 6, &umr_bitfield_default },
	 { "HDMI", 7, 7, &umr_bitfield_default },
	 { "VREF_CONTROL", 8, 15, &umr_bitfield_default },
	 { "EAPD_CAPABLE", 16, 16, &umr_bitfield_default },
	 { "DP", 24, 24, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE[] = {
	 { "TAG", 0, 5, &umr_bitfield_default },
	 { "ENABLE", 7, 7, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE[] = {
	 { "IMPEDANCE_SENSE", 0, 30, &umr_bitfield_default },
	 { "PRESENCE_DETECT", 31, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL[] = {
	 { "IN_ENABLE", 5, 5, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE[] = {
	 { "MULTICHANNEL0_ENABLE", 0, 0, &umr_bitfield_default },
	 { "MULTICHANNEL0_MUTE", 1, 1, &umr_bitfield_default },
	 { "MULTICHANNEL0_CHANNEL_ID", 4, 7, &umr_bitfield_default },
	 { "MULTICHANNEL1_ENABLE", 8, 8, &umr_bitfield_default },
	 { "MULTICHANNEL1_MUTE", 9, 9, &umr_bitfield_default },
	 { "MULTICHANNEL1_CHANNEL_ID", 12, 15, &umr_bitfield_default },
	 { "MULTICHANNEL2_ENABLE", 16, 16, &umr_bitfield_default },
	 { "MULTICHANNEL2_MUTE", 17, 17, &umr_bitfield_default },
	 { "MULTICHANNEL2_CHANNEL_ID", 20, 23, &umr_bitfield_default },
	 { "MULTICHANNEL3_ENABLE", 24, 24, &umr_bitfield_default },
	 { "MULTICHANNEL3_MUTE", 25, 25, &umr_bitfield_default },
	 { "MULTICHANNEL3_CHANNEL_ID", 28, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2[] = {
	 { "MULTICHANNEL4_ENABLE", 0, 0, &umr_bitfield_default },
	 { "MULTICHANNEL4_MUTE", 1, 1, &umr_bitfield_default },
	 { "MULTICHANNEL4_CHANNEL_ID", 4, 7, &umr_bitfield_default },
	 { "MULTICHANNEL5_ENABLE", 8, 8, &umr_bitfield_default },
	 { "MULTICHANNEL5_MUTE", 9, 9, &umr_bitfield_default },
	 { "MULTICHANNEL5_CHANNEL_ID", 12, 15, &umr_bitfield_default },
	 { "MULTICHANNEL6_ENABLE", 16, 16, &umr_bitfield_default },
	 { "MULTICHANNEL6_MUTE", 17, 17, &umr_bitfield_default },
	 { "MULTICHANNEL6_CHANNEL_ID", 20, 23, &umr_bitfield_default },
	 { "MULTICHANNEL7_ENABLE", 24, 24, &umr_bitfield_default },
	 { "MULTICHANNEL7_MUTE", 25, 25, &umr_bitfield_default },
	 { "MULTICHANNEL7_CHANNEL_ID", 28, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR[] = {
	 { "HBR_CAPABLE", 0, 0, &umr_bitfield_default },
	 { "HBR_ENABLE", 4, 4, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION[] = {
	 { "CHANNEL_ALLOCATION", 0, 7, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL[] = {
	 { "CLOCK_GATING_DISABLE", 0, 0, &umr_bitfield_default },
	 { "CLOCK_ON_STATE", 4, 4, &umr_bitfield_default },
	 { "AUDIO_ENABLED", 31, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE[] = {
	 { "UNSOLICITED_RESPONSE_PAYLOAD", 0, 25, &umr_bitfield_default },
	 { "UNSOLICITED_RESPONSE_FORCE", 28, 28, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT[] = {
	 { "SEQUENCE", 0, 3, &umr_bitfield_default },
	 { "DEFAULT_ASSOCIATION", 4, 7, &umr_bitfield_default },
	 { "MISC", 8, 11, &umr_bitfield_default },
	 { "COLOR", 12, 15, &umr_bitfield_default },
	 { "CONNECTION_TYPE", 16, 19, &umr_bitfield_default },
	 { "DEFAULT_DEVICE", 20, 23, &umr_bitfield_default },
	 { "LOCATION", 24, 29, &umr_bitfield_default },
	 { "PORT_CONNECTIVITY", 30, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL[] = {
	 { "LPIB_SNAPSHOT_LOCK", 0, 0, &umr_bitfield_default },
	 { "CYCLIC_BUFFER_WRAP_COUNT", 8, 15, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB[] = {
	 { "LPIB", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT[] = {
	 { "LPIB_TIMER_SNAPSHOT", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL[] = {
	 { "INPUT_ACTIVITY", 0, 0, &umr_bitfield_default },
	 { "CHANNEL_LAYOUT", 1, 2, &umr_bitfield_default },
	 { "INPUT_ACTIVITY_UR_ENABLE", 4, 4, &umr_bitfield_default },
	 { "INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE", 5, 5, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME[] = {
	 { "CHANNEL_COUNT", 0, 2, &umr_bitfield_default },
	 { "CHANNEL_ALLOCATION", 8, 15, &umr_bitfield_default },
	 { "INFOFRAME_BYTE_5", 16, 23, &umr_bitfield_default },
	 { "INFOFRAME_VALID", 31, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES[] = {
	 { "AUDIO_CHANNEL_CAPABILITIES", 0, 0, &umr_bitfield_default },
	 { "INPUT_AMPLIFIER_PRESENT", 1, 1, &umr_bitfield_default },
	 { "OUTPUT_AMPLIFIER_PRESENT", 2, 2, &umr_bitfield_default },
	 { "AMPLIFIER_PARAMETER_OVERRIDE", 3, 3, &umr_bitfield_default },
	 { "FORMAT_OVERRIDE", 4, 4, &umr_bitfield_default },
	 { "STRIPE", 5, 5, &umr_bitfield_default },
	 { "PROCESSING_WIDGET", 6, 6, &umr_bitfield_default },
	 { "UNSOLICITED_RESPONSE_CAPABILITY", 7, 7, &umr_bitfield_default },
	 { "CONNECTION_LIST", 8, 8, &umr_bitfield_default },
	 { "DIGITAL", 9, 9, &umr_bitfield_default },
	 { "POWER_CONTROL", 10, 10, &umr_bitfield_default },
	 { "LR_SWAP", 11, 11, &umr_bitfield_default },
	 { "AUDIO_WIDGET_CAPABILITIES_DELAY", 16, 19, &umr_bitfield_default },
	 { "TYPE", 20, 23, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT[] = {
	 { "NUMBER_OF_CHANNELS", 0, 3, &umr_bitfield_default },
	 { "BITS_PER_SAMPLE", 4, 6, &umr_bitfield_default },
	 { "SAMPLE_BASE_DIVISOR", 8, 10, &umr_bitfield_default },
	 { "SAMPLE_BASE_MULTIPLE", 11, 13, &umr_bitfield_default },
	 { "SAMPLE_BASE_RATE", 14, 14, &umr_bitfield_default },
	 { "STREAM_TYPE", 15, 15, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID[] = {
	 { "CHANNEL_ID", 0, 3, &umr_bitfield_default },
	 { "STREAM_ID", 4, 7, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER[] = {
	 { "DIGEN", 0, 0, &umr_bitfield_default },
	 { "V", 1, 1, &umr_bitfield_default },
	 { "VCFG", 2, 2, &umr_bitfield_default },
	 { "PRE", 3, 3, &umr_bitfield_default },
	 { "COPY", 4, 4, &umr_bitfield_default },
	 { "NON_AUDIO", 5, 5, &umr_bitfield_default },
	 { "PRO", 6, 6, &umr_bitfield_default },
	 { "L", 7, 7, &umr_bitfield_default },
	 { "CC", 8, 14, &umr_bitfield_default },
	 { "KEEPALIVE", 23, 23, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS[] = {
	 { "STREAM_FORMATS", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES[] = {
	 { "AUDIO_RATE_CAPABILITIES", 0, 11, &umr_bitfield_default },
	 { "AUDIO_BIT_CAPABILITIES", 16, 20, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES[] = {
	 { "AUDIO_CHANNEL_CAPABILITIES", 0, 0, &umr_bitfield_default },
	 { "INPUT_AMPLIFIER_PRESENT", 1, 1, &umr_bitfield_default },
	 { "OUTPUT_AMPLIFIER_PRESENT", 2, 2, &umr_bitfield_default },
	 { "AMPLIFIER_PARAMETER_OVERRIDE", 3, 3, &umr_bitfield_default },
	 { "STRIPE", 5, 5, &umr_bitfield_default },
	 { "PROCESSING_WIDGET", 6, 6, &umr_bitfield_default },
	 { "UNSOLICITED_RESPONSE_CAPABILITY", 7, 7, &umr_bitfield_default },
	 { "CONNECTION_LIST", 8, 8, &umr_bitfield_default },
	 { "DIGITAL", 9, 9, &umr_bitfield_default },
	 { "POWER_CONTROL", 10, 10, &umr_bitfield_default },
	 { "LR_SWAP", 11, 11, &umr_bitfield_default },
	 { "AUDIO_WIDGET_CAPABILITIES_DELAY", 16, 19, &umr_bitfield_default },
	 { "TYPE", 20, 23, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES[] = {
	 { "IMPEDANCE_SENSE_CAPABLE", 0, 0, &umr_bitfield_default },
	 { "TRIGGER_REQUIRED", 1, 1, &umr_bitfield_default },
	 { "JACK_DETECTION_CAPABILITY", 2, 2, &umr_bitfield_default },
	 { "HEADPHONE_DRIVE_CAPABLE", 3, 3, &umr_bitfield_default },
	 { "OUTPUT_CAPABLE", 4, 4, &umr_bitfield_default },
	 { "INPUT_CAPABLE", 5, 5, &umr_bitfield_default },
	 { "BALANCED_I_O_PINS", 6, 6, &umr_bitfield_default },
	 { "HDMI", 7, 7, &umr_bitfield_default },
	 { "VREF_CONTROL", 8, 15, &umr_bitfield_default },
	 { "EAPD_CAPABLE", 16, 16, &umr_bitfield_default },
	 { "DP", 24, 24, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE[] = {
	 { "TAG", 0, 5, &umr_bitfield_default },
	 { "ENABLE", 7, 7, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE[] = {
	 { "IMPEDANCE_SENSE", 0, 30, &umr_bitfield_default },
	 { "PRESENCE_DETECT", 31, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL[] = {
	 { "IN_ENABLE", 5, 5, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE[] = {
	 { "MULTICHANNEL0_ENABLE", 0, 0, &umr_bitfield_default },
	 { "MULTICHANNEL0_MUTE", 1, 1, &umr_bitfield_default },
	 { "MULTICHANNEL0_CHANNEL_ID", 4, 7, &umr_bitfield_default },
	 { "MULTICHANNEL1_ENABLE", 8, 8, &umr_bitfield_default },
	 { "MULTICHANNEL1_MUTE", 9, 9, &umr_bitfield_default },
	 { "MULTICHANNEL1_CHANNEL_ID", 12, 15, &umr_bitfield_default },
	 { "MULTICHANNEL2_ENABLE", 16, 16, &umr_bitfield_default },
	 { "MULTICHANNEL2_MUTE", 17, 17, &umr_bitfield_default },
	 { "MULTICHANNEL2_CHANNEL_ID", 20, 23, &umr_bitfield_default },
	 { "MULTICHANNEL3_ENABLE", 24, 24, &umr_bitfield_default },
	 { "MULTICHANNEL3_MUTE", 25, 25, &umr_bitfield_default },
	 { "MULTICHANNEL3_CHANNEL_ID", 28, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2[] = {
	 { "MULTICHANNEL4_ENABLE", 0, 0, &umr_bitfield_default },
	 { "MULTICHANNEL4_MUTE", 1, 1, &umr_bitfield_default },
	 { "MULTICHANNEL4_CHANNEL_ID", 4, 7, &umr_bitfield_default },
	 { "MULTICHANNEL5_ENABLE", 8, 8, &umr_bitfield_default },
	 { "MULTICHANNEL5_MUTE", 9, 9, &umr_bitfield_default },
	 { "MULTICHANNEL5_CHANNEL_ID", 12, 15, &umr_bitfield_default },
	 { "MULTICHANNEL6_ENABLE", 16, 16, &umr_bitfield_default },
	 { "MULTICHANNEL6_MUTE", 17, 17, &umr_bitfield_default },
	 { "MULTICHANNEL6_CHANNEL_ID", 20, 23, &umr_bitfield_default },
	 { "MULTICHANNEL7_ENABLE", 24, 24, &umr_bitfield_default },
	 { "MULTICHANNEL7_MUTE", 25, 25, &umr_bitfield_default },
	 { "MULTICHANNEL7_CHANNEL_ID", 28, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR[] = {
	 { "HBR_CAPABLE", 0, 0, &umr_bitfield_default },
	 { "HBR_ENABLE", 4, 4, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION[] = {
	 { "CHANNEL_ALLOCATION", 0, 7, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL[] = {
	 { "CLOCK_GATING_DISABLE", 0, 0, &umr_bitfield_default },
	 { "CLOCK_ON_STATE", 4, 4, &umr_bitfield_default },
	 { "AUDIO_ENABLED", 31, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE[] = {
	 { "UNSOLICITED_RESPONSE_PAYLOAD", 0, 25, &umr_bitfield_default },
	 { "UNSOLICITED_RESPONSE_FORCE", 28, 28, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT[] = {
	 { "SEQUENCE", 0, 3, &umr_bitfield_default },
	 { "DEFAULT_ASSOCIATION", 4, 7, &umr_bitfield_default },
	 { "MISC", 8, 11, &umr_bitfield_default },
	 { "COLOR", 12, 15, &umr_bitfield_default },
	 { "CONNECTION_TYPE", 16, 19, &umr_bitfield_default },
	 { "DEFAULT_DEVICE", 20, 23, &umr_bitfield_default },
	 { "LOCATION", 24, 29, &umr_bitfield_default },
	 { "PORT_CONNECTIVITY", 30, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL[] = {
	 { "LPIB_SNAPSHOT_LOCK", 0, 0, &umr_bitfield_default },
	 { "CYCLIC_BUFFER_WRAP_COUNT", 8, 15, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB[] = {
	 { "LPIB", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT[] = {
	 { "LPIB_TIMER_SNAPSHOT", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL[] = {
	 { "INPUT_ACTIVITY", 0, 0, &umr_bitfield_default },
	 { "CHANNEL_LAYOUT", 1, 2, &umr_bitfield_default },
	 { "INPUT_ACTIVITY_UR_ENABLE", 4, 4, &umr_bitfield_default },
	 { "INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE", 5, 5, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME[] = {
	 { "CHANNEL_COUNT", 0, 2, &umr_bitfield_default },
	 { "CHANNEL_ALLOCATION", 8, 15, &umr_bitfield_default },
	 { "INFOFRAME_BYTE_5", 16, 23, &umr_bitfield_default },
	 { "INFOFRAME_VALID", 31, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES[] = {
	 { "AUDIO_CHANNEL_CAPABILITIES", 0, 0, &umr_bitfield_default },
	 { "INPUT_AMPLIFIER_PRESENT", 1, 1, &umr_bitfield_default },
	 { "OUTPUT_AMPLIFIER_PRESENT", 2, 2, &umr_bitfield_default },
	 { "AMPLIFIER_PARAMETER_OVERRIDE", 3, 3, &umr_bitfield_default },
	 { "FORMAT_OVERRIDE", 4, 4, &umr_bitfield_default },
	 { "STRIPE", 5, 5, &umr_bitfield_default },
	 { "PROCESSING_WIDGET", 6, 6, &umr_bitfield_default },
	 { "UNSOLICITED_RESPONSE_CAPABILITY", 7, 7, &umr_bitfield_default },
	 { "CONNECTION_LIST", 8, 8, &umr_bitfield_default },
	 { "DIGITAL", 9, 9, &umr_bitfield_default },
	 { "POWER_CONTROL", 10, 10, &umr_bitfield_default },
	 { "LR_SWAP", 11, 11, &umr_bitfield_default },
	 { "AUDIO_WIDGET_CAPABILITIES_DELAY", 16, 19, &umr_bitfield_default },
	 { "TYPE", 20, 23, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT[] = {
	 { "NUMBER_OF_CHANNELS", 0, 3, &umr_bitfield_default },
	 { "BITS_PER_SAMPLE", 4, 6, &umr_bitfield_default },
	 { "SAMPLE_BASE_DIVISOR", 8, 10, &umr_bitfield_default },
	 { "SAMPLE_BASE_MULTIPLE", 11, 13, &umr_bitfield_default },
	 { "SAMPLE_BASE_RATE", 14, 14, &umr_bitfield_default },
	 { "STREAM_TYPE", 15, 15, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID[] = {
	 { "CHANNEL_ID", 0, 3, &umr_bitfield_default },
	 { "STREAM_ID", 4, 7, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER[] = {
	 { "DIGEN", 0, 0, &umr_bitfield_default },
	 { "V", 1, 1, &umr_bitfield_default },
	 { "VCFG", 2, 2, &umr_bitfield_default },
	 { "PRE", 3, 3, &umr_bitfield_default },
	 { "COPY", 4, 4, &umr_bitfield_default },
	 { "NON_AUDIO", 5, 5, &umr_bitfield_default },
	 { "PRO", 6, 6, &umr_bitfield_default },
	 { "L", 7, 7, &umr_bitfield_default },
	 { "CC", 8, 14, &umr_bitfield_default },
	 { "KEEPALIVE", 23, 23, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS[] = {
	 { "STREAM_FORMATS", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES[] = {
	 { "AUDIO_RATE_CAPABILITIES", 0, 11, &umr_bitfield_default },
	 { "AUDIO_BIT_CAPABILITIES", 16, 20, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES[] = {
	 { "AUDIO_CHANNEL_CAPABILITIES", 0, 0, &umr_bitfield_default },
	 { "INPUT_AMPLIFIER_PRESENT", 1, 1, &umr_bitfield_default },
	 { "OUTPUT_AMPLIFIER_PRESENT", 2, 2, &umr_bitfield_default },
	 { "AMPLIFIER_PARAMETER_OVERRIDE", 3, 3, &umr_bitfield_default },
	 { "STRIPE", 5, 5, &umr_bitfield_default },
	 { "PROCESSING_WIDGET", 6, 6, &umr_bitfield_default },
	 { "UNSOLICITED_RESPONSE_CAPABILITY", 7, 7, &umr_bitfield_default },
	 { "CONNECTION_LIST", 8, 8, &umr_bitfield_default },
	 { "DIGITAL", 9, 9, &umr_bitfield_default },
	 { "POWER_CONTROL", 10, 10, &umr_bitfield_default },
	 { "LR_SWAP", 11, 11, &umr_bitfield_default },
	 { "AUDIO_WIDGET_CAPABILITIES_DELAY", 16, 19, &umr_bitfield_default },
	 { "TYPE", 20, 23, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES[] = {
	 { "IMPEDANCE_SENSE_CAPABLE", 0, 0, &umr_bitfield_default },
	 { "TRIGGER_REQUIRED", 1, 1, &umr_bitfield_default },
	 { "JACK_DETECTION_CAPABILITY", 2, 2, &umr_bitfield_default },
	 { "HEADPHONE_DRIVE_CAPABLE", 3, 3, &umr_bitfield_default },
	 { "OUTPUT_CAPABLE", 4, 4, &umr_bitfield_default },
	 { "INPUT_CAPABLE", 5, 5, &umr_bitfield_default },
	 { "BALANCED_I_O_PINS", 6, 6, &umr_bitfield_default },
	 { "HDMI", 7, 7, &umr_bitfield_default },
	 { "VREF_CONTROL", 8, 15, &umr_bitfield_default },
	 { "EAPD_CAPABLE", 16, 16, &umr_bitfield_default },
	 { "DP", 24, 24, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE[] = {
	 { "TAG", 0, 5, &umr_bitfield_default },
	 { "ENABLE", 7, 7, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE[] = {
	 { "IMPEDANCE_SENSE", 0, 30, &umr_bitfield_default },
	 { "PRESENCE_DETECT", 31, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL[] = {
	 { "IN_ENABLE", 5, 5, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE[] = {
	 { "MULTICHANNEL0_ENABLE", 0, 0, &umr_bitfield_default },
	 { "MULTICHANNEL0_MUTE", 1, 1, &umr_bitfield_default },
	 { "MULTICHANNEL0_CHANNEL_ID", 4, 7, &umr_bitfield_default },
	 { "MULTICHANNEL1_ENABLE", 8, 8, &umr_bitfield_default },
	 { "MULTICHANNEL1_MUTE", 9, 9, &umr_bitfield_default },
	 { "MULTICHANNEL1_CHANNEL_ID", 12, 15, &umr_bitfield_default },
	 { "MULTICHANNEL2_ENABLE", 16, 16, &umr_bitfield_default },
	 { "MULTICHANNEL2_MUTE", 17, 17, &umr_bitfield_default },
	 { "MULTICHANNEL2_CHANNEL_ID", 20, 23, &umr_bitfield_default },
	 { "MULTICHANNEL3_ENABLE", 24, 24, &umr_bitfield_default },
	 { "MULTICHANNEL3_MUTE", 25, 25, &umr_bitfield_default },
	 { "MULTICHANNEL3_CHANNEL_ID", 28, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2[] = {
	 { "MULTICHANNEL4_ENABLE", 0, 0, &umr_bitfield_default },
	 { "MULTICHANNEL4_MUTE", 1, 1, &umr_bitfield_default },
	 { "MULTICHANNEL4_CHANNEL_ID", 4, 7, &umr_bitfield_default },
	 { "MULTICHANNEL5_ENABLE", 8, 8, &umr_bitfield_default },
	 { "MULTICHANNEL5_MUTE", 9, 9, &umr_bitfield_default },
	 { "MULTICHANNEL5_CHANNEL_ID", 12, 15, &umr_bitfield_default },
	 { "MULTICHANNEL6_ENABLE", 16, 16, &umr_bitfield_default },
	 { "MULTICHANNEL6_MUTE", 17, 17, &umr_bitfield_default },
	 { "MULTICHANNEL6_CHANNEL_ID", 20, 23, &umr_bitfield_default },
	 { "MULTICHANNEL7_ENABLE", 24, 24, &umr_bitfield_default },
	 { "MULTICHANNEL7_MUTE", 25, 25, &umr_bitfield_default },
	 { "MULTICHANNEL7_CHANNEL_ID", 28, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR[] = {
	 { "HBR_CAPABLE", 0, 0, &umr_bitfield_default },
	 { "HBR_ENABLE", 4, 4, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION[] = {
	 { "CHANNEL_ALLOCATION", 0, 7, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL[] = {
	 { "CLOCK_GATING_DISABLE", 0, 0, &umr_bitfield_default },
	 { "CLOCK_ON_STATE", 4, 4, &umr_bitfield_default },
	 { "AUDIO_ENABLED", 31, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE[] = {
	 { "UNSOLICITED_RESPONSE_PAYLOAD", 0, 25, &umr_bitfield_default },
	 { "UNSOLICITED_RESPONSE_FORCE", 28, 28, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT[] = {
	 { "SEQUENCE", 0, 3, &umr_bitfield_default },
	 { "DEFAULT_ASSOCIATION", 4, 7, &umr_bitfield_default },
	 { "MISC", 8, 11, &umr_bitfield_default },
	 { "COLOR", 12, 15, &umr_bitfield_default },
	 { "CONNECTION_TYPE", 16, 19, &umr_bitfield_default },
	 { "DEFAULT_DEVICE", 20, 23, &umr_bitfield_default },
	 { "LOCATION", 24, 29, &umr_bitfield_default },
	 { "PORT_CONNECTIVITY", 30, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL[] = {
	 { "LPIB_SNAPSHOT_LOCK", 0, 0, &umr_bitfield_default },
	 { "CYCLIC_BUFFER_WRAP_COUNT", 8, 15, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB[] = {
	 { "LPIB", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT[] = {
	 { "LPIB_TIMER_SNAPSHOT", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL[] = {
	 { "INPUT_ACTIVITY", 0, 0, &umr_bitfield_default },
	 { "CHANNEL_LAYOUT", 1, 2, &umr_bitfield_default },
	 { "INPUT_ACTIVITY_UR_ENABLE", 4, 4, &umr_bitfield_default },
	 { "INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE", 5, 5, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME[] = {
	 { "CHANNEL_COUNT", 0, 2, &umr_bitfield_default },
	 { "CHANNEL_ALLOCATION", 8, 15, &umr_bitfield_default },
	 { "INFOFRAME_BYTE_5", 16, 23, &umr_bitfield_default },
	 { "INFOFRAME_VALID", 31, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES[] = {
	 { "AUDIO_CHANNEL_CAPABILITIES", 0, 0, &umr_bitfield_default },
	 { "INPUT_AMPLIFIER_PRESENT", 1, 1, &umr_bitfield_default },
	 { "OUTPUT_AMPLIFIER_PRESENT", 2, 2, &umr_bitfield_default },
	 { "AMPLIFIER_PARAMETER_OVERRIDE", 3, 3, &umr_bitfield_default },
	 { "FORMAT_OVERRIDE", 4, 4, &umr_bitfield_default },
	 { "STRIPE", 5, 5, &umr_bitfield_default },
	 { "PROCESSING_WIDGET", 6, 6, &umr_bitfield_default },
	 { "UNSOLICITED_RESPONSE_CAPABILITY", 7, 7, &umr_bitfield_default },
	 { "CONNECTION_LIST", 8, 8, &umr_bitfield_default },
	 { "DIGITAL", 9, 9, &umr_bitfield_default },
	 { "POWER_CONTROL", 10, 10, &umr_bitfield_default },
	 { "LR_SWAP", 11, 11, &umr_bitfield_default },
	 { "AUDIO_WIDGET_CAPABILITIES_DELAY", 16, 19, &umr_bitfield_default },
	 { "TYPE", 20, 23, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT[] = {
	 { "NUMBER_OF_CHANNELS", 0, 3, &umr_bitfield_default },
	 { "BITS_PER_SAMPLE", 4, 6, &umr_bitfield_default },
	 { "SAMPLE_BASE_DIVISOR", 8, 10, &umr_bitfield_default },
	 { "SAMPLE_BASE_MULTIPLE", 11, 13, &umr_bitfield_default },
	 { "SAMPLE_BASE_RATE", 14, 14, &umr_bitfield_default },
	 { "STREAM_TYPE", 15, 15, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID[] = {
	 { "CHANNEL_ID", 0, 3, &umr_bitfield_default },
	 { "STREAM_ID", 4, 7, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER[] = {
	 { "DIGEN", 0, 0, &umr_bitfield_default },
	 { "V", 1, 1, &umr_bitfield_default },
	 { "VCFG", 2, 2, &umr_bitfield_default },
	 { "PRE", 3, 3, &umr_bitfield_default },
	 { "COPY", 4, 4, &umr_bitfield_default },
	 { "NON_AUDIO", 5, 5, &umr_bitfield_default },
	 { "PRO", 6, 6, &umr_bitfield_default },
	 { "L", 7, 7, &umr_bitfield_default },
	 { "CC", 8, 14, &umr_bitfield_default },
	 { "KEEPALIVE", 23, 23, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS[] = {
	 { "STREAM_FORMATS", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES[] = {
	 { "AUDIO_RATE_CAPABILITIES", 0, 11, &umr_bitfield_default },
	 { "AUDIO_BIT_CAPABILITIES", 16, 20, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES[] = {
	 { "AUDIO_CHANNEL_CAPABILITIES", 0, 0, &umr_bitfield_default },
	 { "INPUT_AMPLIFIER_PRESENT", 1, 1, &umr_bitfield_default },
	 { "OUTPUT_AMPLIFIER_PRESENT", 2, 2, &umr_bitfield_default },
	 { "AMPLIFIER_PARAMETER_OVERRIDE", 3, 3, &umr_bitfield_default },
	 { "STRIPE", 5, 5, &umr_bitfield_default },
	 { "PROCESSING_WIDGET", 6, 6, &umr_bitfield_default },
	 { "UNSOLICITED_RESPONSE_CAPABILITY", 7, 7, &umr_bitfield_default },
	 { "CONNECTION_LIST", 8, 8, &umr_bitfield_default },
	 { "DIGITAL", 9, 9, &umr_bitfield_default },
	 { "POWER_CONTROL", 10, 10, &umr_bitfield_default },
	 { "LR_SWAP", 11, 11, &umr_bitfield_default },
	 { "AUDIO_WIDGET_CAPABILITIES_DELAY", 16, 19, &umr_bitfield_default },
	 { "TYPE", 20, 23, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES[] = {
	 { "IMPEDANCE_SENSE_CAPABLE", 0, 0, &umr_bitfield_default },
	 { "TRIGGER_REQUIRED", 1, 1, &umr_bitfield_default },
	 { "JACK_DETECTION_CAPABILITY", 2, 2, &umr_bitfield_default },
	 { "HEADPHONE_DRIVE_CAPABLE", 3, 3, &umr_bitfield_default },
	 { "OUTPUT_CAPABLE", 4, 4, &umr_bitfield_default },
	 { "INPUT_CAPABLE", 5, 5, &umr_bitfield_default },
	 { "BALANCED_I_O_PINS", 6, 6, &umr_bitfield_default },
	 { "HDMI", 7, 7, &umr_bitfield_default },
	 { "VREF_CONTROL", 8, 15, &umr_bitfield_default },
	 { "EAPD_CAPABLE", 16, 16, &umr_bitfield_default },
	 { "DP", 24, 24, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE[] = {
	 { "TAG", 0, 5, &umr_bitfield_default },
	 { "ENABLE", 7, 7, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE[] = {
	 { "IMPEDANCE_SENSE", 0, 30, &umr_bitfield_default },
	 { "PRESENCE_DETECT", 31, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL[] = {
	 { "IN_ENABLE", 5, 5, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE[] = {
	 { "MULTICHANNEL0_ENABLE", 0, 0, &umr_bitfield_default },
	 { "MULTICHANNEL0_MUTE", 1, 1, &umr_bitfield_default },
	 { "MULTICHANNEL0_CHANNEL_ID", 4, 7, &umr_bitfield_default },
	 { "MULTICHANNEL1_ENABLE", 8, 8, &umr_bitfield_default },
	 { "MULTICHANNEL1_MUTE", 9, 9, &umr_bitfield_default },
	 { "MULTICHANNEL1_CHANNEL_ID", 12, 15, &umr_bitfield_default },
	 { "MULTICHANNEL2_ENABLE", 16, 16, &umr_bitfield_default },
	 { "MULTICHANNEL2_MUTE", 17, 17, &umr_bitfield_default },
	 { "MULTICHANNEL2_CHANNEL_ID", 20, 23, &umr_bitfield_default },
	 { "MULTICHANNEL3_ENABLE", 24, 24, &umr_bitfield_default },
	 { "MULTICHANNEL3_MUTE", 25, 25, &umr_bitfield_default },
	 { "MULTICHANNEL3_CHANNEL_ID", 28, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2[] = {
	 { "MULTICHANNEL4_ENABLE", 0, 0, &umr_bitfield_default },
	 { "MULTICHANNEL4_MUTE", 1, 1, &umr_bitfield_default },
	 { "MULTICHANNEL4_CHANNEL_ID", 4, 7, &umr_bitfield_default },
	 { "MULTICHANNEL5_ENABLE", 8, 8, &umr_bitfield_default },
	 { "MULTICHANNEL5_MUTE", 9, 9, &umr_bitfield_default },
	 { "MULTICHANNEL5_CHANNEL_ID", 12, 15, &umr_bitfield_default },
	 { "MULTICHANNEL6_ENABLE", 16, 16, &umr_bitfield_default },
	 { "MULTICHANNEL6_MUTE", 17, 17, &umr_bitfield_default },
	 { "MULTICHANNEL6_CHANNEL_ID", 20, 23, &umr_bitfield_default },
	 { "MULTICHANNEL7_ENABLE", 24, 24, &umr_bitfield_default },
	 { "MULTICHANNEL7_MUTE", 25, 25, &umr_bitfield_default },
	 { "MULTICHANNEL7_CHANNEL_ID", 28, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR[] = {
	 { "HBR_CAPABLE", 0, 0, &umr_bitfield_default },
	 { "HBR_ENABLE", 4, 4, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION[] = {
	 { "CHANNEL_ALLOCATION", 0, 7, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL[] = {
	 { "CLOCK_GATING_DISABLE", 0, 0, &umr_bitfield_default },
	 { "CLOCK_ON_STATE", 4, 4, &umr_bitfield_default },
	 { "AUDIO_ENABLED", 31, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE[] = {
	 { "UNSOLICITED_RESPONSE_PAYLOAD", 0, 25, &umr_bitfield_default },
	 { "UNSOLICITED_RESPONSE_FORCE", 28, 28, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT[] = {
	 { "SEQUENCE", 0, 3, &umr_bitfield_default },
	 { "DEFAULT_ASSOCIATION", 4, 7, &umr_bitfield_default },
	 { "MISC", 8, 11, &umr_bitfield_default },
	 { "COLOR", 12, 15, &umr_bitfield_default },
	 { "CONNECTION_TYPE", 16, 19, &umr_bitfield_default },
	 { "DEFAULT_DEVICE", 20, 23, &umr_bitfield_default },
	 { "LOCATION", 24, 29, &umr_bitfield_default },
	 { "PORT_CONNECTIVITY", 30, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL[] = {
	 { "LPIB_SNAPSHOT_LOCK", 0, 0, &umr_bitfield_default },
	 { "CYCLIC_BUFFER_WRAP_COUNT", 8, 15, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB[] = {
	 { "LPIB", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT[] = {
	 { "LPIB_TIMER_SNAPSHOT", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL[] = {
	 { "INPUT_ACTIVITY", 0, 0, &umr_bitfield_default },
	 { "CHANNEL_LAYOUT", 1, 2, &umr_bitfield_default },
	 { "INPUT_ACTIVITY_UR_ENABLE", 4, 4, &umr_bitfield_default },
	 { "INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE", 5, 5, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME[] = {
	 { "CHANNEL_COUNT", 0, 2, &umr_bitfield_default },
	 { "CHANNEL_ALLOCATION", 8, 15, &umr_bitfield_default },
	 { "INFOFRAME_BYTE_5", 16, 23, &umr_bitfield_default },
	 { "INFOFRAME_VALID", 31, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES[] = {
	 { "AUDIO_CHANNEL_CAPABILITIES", 0, 0, &umr_bitfield_default },
	 { "INPUT_AMPLIFIER_PRESENT", 1, 1, &umr_bitfield_default },
	 { "OUTPUT_AMPLIFIER_PRESENT", 2, 2, &umr_bitfield_default },
	 { "AMPLIFIER_PARAMETER_OVERRIDE", 3, 3, &umr_bitfield_default },
	 { "FORMAT_OVERRIDE", 4, 4, &umr_bitfield_default },
	 { "STRIPE", 5, 5, &umr_bitfield_default },
	 { "PROCESSING_WIDGET", 6, 6, &umr_bitfield_default },
	 { "UNSOLICITED_RESPONSE_CAPABILITY", 7, 7, &umr_bitfield_default },
	 { "CONNECTION_LIST", 8, 8, &umr_bitfield_default },
	 { "DIGITAL", 9, 9, &umr_bitfield_default },
	 { "POWER_CONTROL", 10, 10, &umr_bitfield_default },
	 { "LR_SWAP", 11, 11, &umr_bitfield_default },
	 { "AUDIO_WIDGET_CAPABILITIES_DELAY", 16, 19, &umr_bitfield_default },
	 { "TYPE", 20, 23, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT[] = {
	 { "NUMBER_OF_CHANNELS", 0, 3, &umr_bitfield_default },
	 { "BITS_PER_SAMPLE", 4, 6, &umr_bitfield_default },
	 { "SAMPLE_BASE_DIVISOR", 8, 10, &umr_bitfield_default },
	 { "SAMPLE_BASE_MULTIPLE", 11, 13, &umr_bitfield_default },
	 { "SAMPLE_BASE_RATE", 14, 14, &umr_bitfield_default },
	 { "STREAM_TYPE", 15, 15, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID[] = {
	 { "CHANNEL_ID", 0, 3, &umr_bitfield_default },
	 { "STREAM_ID", 4, 7, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER[] = {
	 { "DIGEN", 0, 0, &umr_bitfield_default },
	 { "V", 1, 1, &umr_bitfield_default },
	 { "VCFG", 2, 2, &umr_bitfield_default },
	 { "PRE", 3, 3, &umr_bitfield_default },
	 { "COPY", 4, 4, &umr_bitfield_default },
	 { "NON_AUDIO", 5, 5, &umr_bitfield_default },
	 { "PRO", 6, 6, &umr_bitfield_default },
	 { "L", 7, 7, &umr_bitfield_default },
	 { "CC", 8, 14, &umr_bitfield_default },
	 { "KEEPALIVE", 23, 23, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS[] = {
	 { "STREAM_FORMATS", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES[] = {
	 { "AUDIO_RATE_CAPABILITIES", 0, 11, &umr_bitfield_default },
	 { "AUDIO_BIT_CAPABILITIES", 16, 20, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES[] = {
	 { "AUDIO_CHANNEL_CAPABILITIES", 0, 0, &umr_bitfield_default },
	 { "INPUT_AMPLIFIER_PRESENT", 1, 1, &umr_bitfield_default },
	 { "OUTPUT_AMPLIFIER_PRESENT", 2, 2, &umr_bitfield_default },
	 { "AMPLIFIER_PARAMETER_OVERRIDE", 3, 3, &umr_bitfield_default },
	 { "STRIPE", 5, 5, &umr_bitfield_default },
	 { "PROCESSING_WIDGET", 6, 6, &umr_bitfield_default },
	 { "UNSOLICITED_RESPONSE_CAPABILITY", 7, 7, &umr_bitfield_default },
	 { "CONNECTION_LIST", 8, 8, &umr_bitfield_default },
	 { "DIGITAL", 9, 9, &umr_bitfield_default },
	 { "POWER_CONTROL", 10, 10, &umr_bitfield_default },
	 { "LR_SWAP", 11, 11, &umr_bitfield_default },
	 { "AUDIO_WIDGET_CAPABILITIES_DELAY", 16, 19, &umr_bitfield_default },
	 { "TYPE", 20, 23, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES[] = {
	 { "IMPEDANCE_SENSE_CAPABLE", 0, 0, &umr_bitfield_default },
	 { "TRIGGER_REQUIRED", 1, 1, &umr_bitfield_default },
	 { "JACK_DETECTION_CAPABILITY", 2, 2, &umr_bitfield_default },
	 { "HEADPHONE_DRIVE_CAPABLE", 3, 3, &umr_bitfield_default },
	 { "OUTPUT_CAPABLE", 4, 4, &umr_bitfield_default },
	 { "INPUT_CAPABLE", 5, 5, &umr_bitfield_default },
	 { "BALANCED_I_O_PINS", 6, 6, &umr_bitfield_default },
	 { "HDMI", 7, 7, &umr_bitfield_default },
	 { "VREF_CONTROL", 8, 15, &umr_bitfield_default },
	 { "EAPD_CAPABLE", 16, 16, &umr_bitfield_default },
	 { "DP", 24, 24, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE[] = {
	 { "TAG", 0, 5, &umr_bitfield_default },
	 { "ENABLE", 7, 7, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE[] = {
	 { "IMPEDANCE_SENSE", 0, 30, &umr_bitfield_default },
	 { "PRESENCE_DETECT", 31, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL[] = {
	 { "IN_ENABLE", 5, 5, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE[] = {
	 { "MULTICHANNEL0_ENABLE", 0, 0, &umr_bitfield_default },
	 { "MULTICHANNEL0_MUTE", 1, 1, &umr_bitfield_default },
	 { "MULTICHANNEL0_CHANNEL_ID", 4, 7, &umr_bitfield_default },
	 { "MULTICHANNEL1_ENABLE", 8, 8, &umr_bitfield_default },
	 { "MULTICHANNEL1_MUTE", 9, 9, &umr_bitfield_default },
	 { "MULTICHANNEL1_CHANNEL_ID", 12, 15, &umr_bitfield_default },
	 { "MULTICHANNEL2_ENABLE", 16, 16, &umr_bitfield_default },
	 { "MULTICHANNEL2_MUTE", 17, 17, &umr_bitfield_default },
	 { "MULTICHANNEL2_CHANNEL_ID", 20, 23, &umr_bitfield_default },
	 { "MULTICHANNEL3_ENABLE", 24, 24, &umr_bitfield_default },
	 { "MULTICHANNEL3_MUTE", 25, 25, &umr_bitfield_default },
	 { "MULTICHANNEL3_CHANNEL_ID", 28, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2[] = {
	 { "MULTICHANNEL4_ENABLE", 0, 0, &umr_bitfield_default },
	 { "MULTICHANNEL4_MUTE", 1, 1, &umr_bitfield_default },
	 { "MULTICHANNEL4_CHANNEL_ID", 4, 7, &umr_bitfield_default },
	 { "MULTICHANNEL5_ENABLE", 8, 8, &umr_bitfield_default },
	 { "MULTICHANNEL5_MUTE", 9, 9, &umr_bitfield_default },
	 { "MULTICHANNEL5_CHANNEL_ID", 12, 15, &umr_bitfield_default },
	 { "MULTICHANNEL6_ENABLE", 16, 16, &umr_bitfield_default },
	 { "MULTICHANNEL6_MUTE", 17, 17, &umr_bitfield_default },
	 { "MULTICHANNEL6_CHANNEL_ID", 20, 23, &umr_bitfield_default },
	 { "MULTICHANNEL7_ENABLE", 24, 24, &umr_bitfield_default },
	 { "MULTICHANNEL7_MUTE", 25, 25, &umr_bitfield_default },
	 { "MULTICHANNEL7_CHANNEL_ID", 28, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR[] = {
	 { "HBR_CAPABLE", 0, 0, &umr_bitfield_default },
	 { "HBR_ENABLE", 4, 4, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION[] = {
	 { "CHANNEL_ALLOCATION", 0, 7, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL[] = {
	 { "CLOCK_GATING_DISABLE", 0, 0, &umr_bitfield_default },
	 { "CLOCK_ON_STATE", 4, 4, &umr_bitfield_default },
	 { "AUDIO_ENABLED", 31, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE[] = {
	 { "UNSOLICITED_RESPONSE_PAYLOAD", 0, 25, &umr_bitfield_default },
	 { "UNSOLICITED_RESPONSE_FORCE", 28, 28, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT[] = {
	 { "SEQUENCE", 0, 3, &umr_bitfield_default },
	 { "DEFAULT_ASSOCIATION", 4, 7, &umr_bitfield_default },
	 { "MISC", 8, 11, &umr_bitfield_default },
	 { "COLOR", 12, 15, &umr_bitfield_default },
	 { "CONNECTION_TYPE", 16, 19, &umr_bitfield_default },
	 { "DEFAULT_DEVICE", 20, 23, &umr_bitfield_default },
	 { "LOCATION", 24, 29, &umr_bitfield_default },
	 { "PORT_CONNECTIVITY", 30, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL[] = {
	 { "LPIB_SNAPSHOT_LOCK", 0, 0, &umr_bitfield_default },
	 { "CYCLIC_BUFFER_WRAP_COUNT", 8, 15, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB[] = {
	 { "LPIB", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT[] = {
	 { "LPIB_TIMER_SNAPSHOT", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL[] = {
	 { "INPUT_ACTIVITY", 0, 0, &umr_bitfield_default },
	 { "CHANNEL_LAYOUT", 1, 2, &umr_bitfield_default },
	 { "INPUT_ACTIVITY_UR_ENABLE", 4, 4, &umr_bitfield_default },
	 { "INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE", 5, 5, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME[] = {
	 { "CHANNEL_COUNT", 0, 2, &umr_bitfield_default },
	 { "CHANNEL_ALLOCATION", 8, 15, &umr_bitfield_default },
	 { "INFOFRAME_BYTE_5", 16, 23, &umr_bitfield_default },
	 { "INFOFRAME_VALID", 31, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES[] = {
	 { "AUDIO_CHANNEL_CAPABILITIES", 0, 0, &umr_bitfield_default },
	 { "INPUT_AMPLIFIER_PRESENT", 1, 1, &umr_bitfield_default },
	 { "OUTPUT_AMPLIFIER_PRESENT", 2, 2, &umr_bitfield_default },
	 { "AMPLIFIER_PARAMETER_OVERRIDE", 3, 3, &umr_bitfield_default },
	 { "FORMAT_OVERRIDE", 4, 4, &umr_bitfield_default },
	 { "STRIPE", 5, 5, &umr_bitfield_default },
	 { "PROCESSING_WIDGET", 6, 6, &umr_bitfield_default },
	 { "UNSOLICITED_RESPONSE_CAPABILITY", 7, 7, &umr_bitfield_default },
	 { "CONNECTION_LIST", 8, 8, &umr_bitfield_default },
	 { "DIGITAL", 9, 9, &umr_bitfield_default },
	 { "POWER_CONTROL", 10, 10, &umr_bitfield_default },
	 { "LR_SWAP", 11, 11, &umr_bitfield_default },
	 { "AUDIO_WIDGET_CAPABILITIES_DELAY", 16, 19, &umr_bitfield_default },
	 { "TYPE", 20, 23, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT[] = {
	 { "NUMBER_OF_CHANNELS", 0, 3, &umr_bitfield_default },
	 { "BITS_PER_SAMPLE", 4, 6, &umr_bitfield_default },
	 { "SAMPLE_BASE_DIVISOR", 8, 10, &umr_bitfield_default },
	 { "SAMPLE_BASE_MULTIPLE", 11, 13, &umr_bitfield_default },
	 { "SAMPLE_BASE_RATE", 14, 14, &umr_bitfield_default },
	 { "STREAM_TYPE", 15, 15, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID[] = {
	 { "CHANNEL_ID", 0, 3, &umr_bitfield_default },
	 { "STREAM_ID", 4, 7, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER[] = {
	 { "DIGEN", 0, 0, &umr_bitfield_default },
	 { "V", 1, 1, &umr_bitfield_default },
	 { "VCFG", 2, 2, &umr_bitfield_default },
	 { "PRE", 3, 3, &umr_bitfield_default },
	 { "COPY", 4, 4, &umr_bitfield_default },
	 { "NON_AUDIO", 5, 5, &umr_bitfield_default },
	 { "PRO", 6, 6, &umr_bitfield_default },
	 { "L", 7, 7, &umr_bitfield_default },
	 { "CC", 8, 14, &umr_bitfield_default },
	 { "KEEPALIVE", 23, 23, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS[] = {
	 { "STREAM_FORMATS", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES[] = {
	 { "AUDIO_RATE_CAPABILITIES", 0, 11, &umr_bitfield_default },
	 { "AUDIO_BIT_CAPABILITIES", 16, 20, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES[] = {
	 { "AUDIO_CHANNEL_CAPABILITIES", 0, 0, &umr_bitfield_default },
	 { "INPUT_AMPLIFIER_PRESENT", 1, 1, &umr_bitfield_default },
	 { "OUTPUT_AMPLIFIER_PRESENT", 2, 2, &umr_bitfield_default },
	 { "AMPLIFIER_PARAMETER_OVERRIDE", 3, 3, &umr_bitfield_default },
	 { "STRIPE", 5, 5, &umr_bitfield_default },
	 { "PROCESSING_WIDGET", 6, 6, &umr_bitfield_default },
	 { "UNSOLICITED_RESPONSE_CAPABILITY", 7, 7, &umr_bitfield_default },
	 { "CONNECTION_LIST", 8, 8, &umr_bitfield_default },
	 { "DIGITAL", 9, 9, &umr_bitfield_default },
	 { "POWER_CONTROL", 10, 10, &umr_bitfield_default },
	 { "LR_SWAP", 11, 11, &umr_bitfield_default },
	 { "AUDIO_WIDGET_CAPABILITIES_DELAY", 16, 19, &umr_bitfield_default },
	 { "TYPE", 20, 23, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES[] = {
	 { "IMPEDANCE_SENSE_CAPABLE", 0, 0, &umr_bitfield_default },
	 { "TRIGGER_REQUIRED", 1, 1, &umr_bitfield_default },
	 { "JACK_DETECTION_CAPABILITY", 2, 2, &umr_bitfield_default },
	 { "HEADPHONE_DRIVE_CAPABLE", 3, 3, &umr_bitfield_default },
	 { "OUTPUT_CAPABLE", 4, 4, &umr_bitfield_default },
	 { "INPUT_CAPABLE", 5, 5, &umr_bitfield_default },
	 { "BALANCED_I_O_PINS", 6, 6, &umr_bitfield_default },
	 { "HDMI", 7, 7, &umr_bitfield_default },
	 { "VREF_CONTROL", 8, 15, &umr_bitfield_default },
	 { "EAPD_CAPABLE", 16, 16, &umr_bitfield_default },
	 { "DP", 24, 24, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE[] = {
	 { "TAG", 0, 5, &umr_bitfield_default },
	 { "ENABLE", 7, 7, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE[] = {
	 { "IMPEDANCE_SENSE", 0, 30, &umr_bitfield_default },
	 { "PRESENCE_DETECT", 31, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL[] = {
	 { "IN_ENABLE", 5, 5, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE[] = {
	 { "MULTICHANNEL0_ENABLE", 0, 0, &umr_bitfield_default },
	 { "MULTICHANNEL0_MUTE", 1, 1, &umr_bitfield_default },
	 { "MULTICHANNEL0_CHANNEL_ID", 4, 7, &umr_bitfield_default },
	 { "MULTICHANNEL1_ENABLE", 8, 8, &umr_bitfield_default },
	 { "MULTICHANNEL1_MUTE", 9, 9, &umr_bitfield_default },
	 { "MULTICHANNEL1_CHANNEL_ID", 12, 15, &umr_bitfield_default },
	 { "MULTICHANNEL2_ENABLE", 16, 16, &umr_bitfield_default },
	 { "MULTICHANNEL2_MUTE", 17, 17, &umr_bitfield_default },
	 { "MULTICHANNEL2_CHANNEL_ID", 20, 23, &umr_bitfield_default },
	 { "MULTICHANNEL3_ENABLE", 24, 24, &umr_bitfield_default },
	 { "MULTICHANNEL3_MUTE", 25, 25, &umr_bitfield_default },
	 { "MULTICHANNEL3_CHANNEL_ID", 28, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2[] = {
	 { "MULTICHANNEL4_ENABLE", 0, 0, &umr_bitfield_default },
	 { "MULTICHANNEL4_MUTE", 1, 1, &umr_bitfield_default },
	 { "MULTICHANNEL4_CHANNEL_ID", 4, 7, &umr_bitfield_default },
	 { "MULTICHANNEL5_ENABLE", 8, 8, &umr_bitfield_default },
	 { "MULTICHANNEL5_MUTE", 9, 9, &umr_bitfield_default },
	 { "MULTICHANNEL5_CHANNEL_ID", 12, 15, &umr_bitfield_default },
	 { "MULTICHANNEL6_ENABLE", 16, 16, &umr_bitfield_default },
	 { "MULTICHANNEL6_MUTE", 17, 17, &umr_bitfield_default },
	 { "MULTICHANNEL6_CHANNEL_ID", 20, 23, &umr_bitfield_default },
	 { "MULTICHANNEL7_ENABLE", 24, 24, &umr_bitfield_default },
	 { "MULTICHANNEL7_MUTE", 25, 25, &umr_bitfield_default },
	 { "MULTICHANNEL7_CHANNEL_ID", 28, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR[] = {
	 { "HBR_CAPABLE", 0, 0, &umr_bitfield_default },
	 { "HBR_ENABLE", 4, 4, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION[] = {
	 { "CHANNEL_ALLOCATION", 0, 7, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL[] = {
	 { "CLOCK_GATING_DISABLE", 0, 0, &umr_bitfield_default },
	 { "CLOCK_ON_STATE", 4, 4, &umr_bitfield_default },
	 { "AUDIO_ENABLED", 31, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE[] = {
	 { "UNSOLICITED_RESPONSE_PAYLOAD", 0, 25, &umr_bitfield_default },
	 { "UNSOLICITED_RESPONSE_FORCE", 28, 28, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT[] = {
	 { "SEQUENCE", 0, 3, &umr_bitfield_default },
	 { "DEFAULT_ASSOCIATION", 4, 7, &umr_bitfield_default },
	 { "MISC", 8, 11, &umr_bitfield_default },
	 { "COLOR", 12, 15, &umr_bitfield_default },
	 { "CONNECTION_TYPE", 16, 19, &umr_bitfield_default },
	 { "DEFAULT_DEVICE", 20, 23, &umr_bitfield_default },
	 { "LOCATION", 24, 29, &umr_bitfield_default },
	 { "PORT_CONNECTIVITY", 30, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL[] = {
	 { "LPIB_SNAPSHOT_LOCK", 0, 0, &umr_bitfield_default },
	 { "CYCLIC_BUFFER_WRAP_COUNT", 8, 15, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB[] = {
	 { "LPIB", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT[] = {
	 { "LPIB_TIMER_SNAPSHOT", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL[] = {
	 { "INPUT_ACTIVITY", 0, 0, &umr_bitfield_default },
	 { "CHANNEL_LAYOUT", 1, 2, &umr_bitfield_default },
	 { "INPUT_ACTIVITY_UR_ENABLE", 4, 4, &umr_bitfield_default },
	 { "INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE", 5, 5, &umr_bitfield_default },
};
static struct umr_bitfield ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME[] = {
	 { "CHANNEL_COUNT", 0, 2, &umr_bitfield_default },
	 { "CHANNEL_ALLOCATION", 8, 15, &umr_bitfield_default },
	 { "INFOFRAME_BYTE_5", 16, 23, &umr_bitfield_default },
	 { "INFOFRAME_VALID", 31, 31, &umr_bitfield_default },
};