static struct umr_bitfield ixMC_IO_DEBUG_UP_0[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_UP_1[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_UP_2[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_UP_3[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_UP_4[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_UP_5[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_UP_6[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_UP_7[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_UP_8[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_UP_9[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_UP_10[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_UP_11[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_UP_12[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_UP_13[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_UP_14[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_UP_15[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_UP_16[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_UP_17[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_UP_18[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_UP_19[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_UP_20[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_UP_21[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_UP_22[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_UP_23[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_UP_24[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_UP_25[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_UP_26[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_UP_27[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_UP_28[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_UP_29[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_UP_30[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_UP_31[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_UP_32[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_UP_33[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_UP_34[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_UP_35[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_UP_36[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_UP_37[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_UP_38[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_UP_39[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_UP_40[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_UP_41[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_UP_42[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_UP_43[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_UP_44[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_UP_45[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_UP_46[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_UP_47[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_UP_48[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_UP_49[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_UP_50[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_UP_51[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_UP_52[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_UP_53[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_UP_54[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_UP_55[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_UP_56[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_UP_57[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_UP_58[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_UP_59[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_UP_60[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_UP_61[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_UP_62[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_UP_63[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_UP_64[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_UP_65[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_UP_66[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_UP_67[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_UP_68[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_UP_69[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_UP_70[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_UP_71[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_UP_72[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_UP_73[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_UP_74[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_UP_75[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_UP_76[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_UP_77[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_UP_78[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_UP_79[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_UP_80[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_UP_81[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_UP_82[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_UP_83[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_UP_84[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_UP_85[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_UP_86[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_UP_87[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_UP_88[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_UP_89[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_UP_90[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_UP_91[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_UP_92[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_UP_93[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_UP_94[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_UP_95[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_UP_96[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_UP_97[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_UP_98[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_UP_99[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_UP_100[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_UP_101[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_UP_102[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_UP_103[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_UP_104[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_UP_105[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_UP_106[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_UP_107[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_UP_108[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_UP_109[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_UP_110[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_UP_111[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_UP_112[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_UP_113[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_UP_114[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_UP_115[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_UP_116[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_UP_117[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_UP_118[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_UP_119[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_UP_120[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_UP_121[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_UP_122[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_UP_123[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_UP_124[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_UP_125[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_UP_126[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_UP_127[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_UP_128[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_UP_129[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_UP_130[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_UP_131[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_UP_132[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_UP_133[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_UP_134[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_UP_135[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_UP_136[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_UP_137[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_UP_138[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_UP_139[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_UP_140[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_UP_141[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_UP_142[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_UP_143[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_UP_144[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_UP_145[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_UP_146[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_UP_147[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_UP_148[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_UP_149[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_UP_150[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_UP_151[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_UP_152[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_UP_153[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_UP_154[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_UP_155[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_UP_156[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_UP_157[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_UP_158[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_UP_159[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_DQB0L_MISC_D0[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_DQB0H_MISC_D0[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_DQB1L_MISC_D0[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_DQB1H_MISC_D0[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_DQB2L_MISC_D0[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_DQB2H_MISC_D0[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_DQB3L_MISC_D0[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_DQB3H_MISC_D0[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_DBI_MISC_D0[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_EDC_MISC_D0[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_WCK_MISC_D0[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_CK_MISC_D0[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_ADDRL_MISC_D0[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_ADDRH_MISC_D0[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_ACMD_MISC_D0[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_CMD_MISC_D0[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_DQB0L_MISC_D1[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_DQB0H_MISC_D1[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_DQB1L_MISC_D1[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_DQB1H_MISC_D1[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_DQB2L_MISC_D1[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_DQB2H_MISC_D1[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_DQB3L_MISC_D1[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_DQB3H_MISC_D1[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_DBI_MISC_D1[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_EDC_MISC_D1[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_WCK_MISC_D1[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_CK_MISC_D1[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_ADDRL_MISC_D1[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_ADDRH_MISC_D1[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_ACMD_MISC_D1[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_CMD_MISC_D1[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_DQB0L_CLKSEL_D0[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_DQB0H_CLKSEL_D0[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_DQB1L_CLKSEL_D0[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_DQB1H_CLKSEL_D0[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_DQB2L_CLKSEL_D0[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_DQB2H_CLKSEL_D0[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_DQB3L_CLKSEL_D0[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_DQB3H_CLKSEL_D0[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_DBI_CLKSEL_D0[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_EDC_CLKSEL_D0[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_WCK_CLKSEL_D0[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_CK_CLKSEL_D0[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_ADDRL_CLKSEL_D0[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_ADDRH_CLKSEL_D0[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_ACMD_CLKSEL_D0[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_CMD_CLKSEL_D0[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_DQB0L_CLKSEL_D1[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_DQB0H_CLKSEL_D1[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_DQB1L_CLKSEL_D1[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_DQB1H_CLKSEL_D1[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_DQB2L_CLKSEL_D1[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_DQB2H_CLKSEL_D1[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_DQB3L_CLKSEL_D1[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_DQB3H_CLKSEL_D1[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_DBI_CLKSEL_D1[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_EDC_CLKSEL_D1[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_WCK_CLKSEL_D1[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_CK_CLKSEL_D1[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_ADDRL_CLKSEL_D1[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_ADDRH_CLKSEL_D1[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_ACMD_CLKSEL_D1[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_CMD_CLKSEL_D1[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_DQB0L_OFSCAL_D0[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_DQB0H_OFSCAL_D0[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_DQB1L_OFSCAL_D0[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_DQB1H_OFSCAL_D0[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_DQB2L_OFSCAL_D0[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_DQB2H_OFSCAL_D0[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_DQB3L_OFSCAL_D0[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_DQB3H_OFSCAL_D0[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_DBI_OFSCAL_D0[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_EDC_OFSCAL_D0[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_WCK_OFSCAL_D0[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_EDC_RX_EQ_PM_D0[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_EDC_RX_DYN_PM_D0[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_EDC_CDR_PHSIZE_D0[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_ACMD_OFSCAL_D0[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_CMD_OFSCAL_D0[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_DQB0L_OFSCAL_D1[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_DQB0H_OFSCAL_D1[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_DQB1L_OFSCAL_D1[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_DQB1H_OFSCAL_D1[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_DQB2L_OFSCAL_D1[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_DQB2H_OFSCAL_D1[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_DQB3L_OFSCAL_D1[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_DQB3H_OFSCAL_D1[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_DBI_OFSCAL_D1[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_EDC_OFSCAL_D1[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_WCK_OFSCAL_D1[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_EDC_RX_EQ_PM_D1[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_EDC_RX_DYN_PM_D1[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_EDC_CDR_PHSIZE_D1[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_ACMD_OFSCAL_D1[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_CMD_OFSCAL_D1[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_DQB0L_RXPHASE_D0[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_DQB0H_RXPHASE_D0[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_DQB1L_RXPHASE_D0[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_DQB1H_RXPHASE_D0[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_DQB2L_RXPHASE_D0[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_DQB2H_RXPHASE_D0[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_DQB3L_RXPHASE_D0[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_DQB3H_RXPHASE_D0[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_DBI_RXPHASE_D0[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_EDC_RXPHASE_D0[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_WCK_RXPHASE_D0[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_CK_RXPHASE_D0[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_ADDRL_RXPHASE_D0[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_ADDRH_RXPHASE_D0[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_ACMD_RXPHASE_D0[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_CMD_RXPHASE_D0[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_DQB0L_RXPHASE_D1[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_DQB0H_RXPHASE_D1[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_DQB1L_RXPHASE_D1[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_DQB1H_RXPHASE_D1[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_DQB2L_RXPHASE_D1[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_DQB2H_RXPHASE_D1[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_DQB3L_RXPHASE_D1[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_DQB3H_RXPHASE_D1[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_DBI_RXPHASE_D1[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_EDC_RXPHASE_D1[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_WCK_RXPHASE_D1[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_CK_RXPHASE_D1[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_ADDRL_RXPHASE_D1[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_ADDRH_RXPHASE_D1[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_ACMD_RXPHASE_D1[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_CMD_RXPHASE_D1[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_DQB0L_TXPHASE_D0[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_DQB0H_TXPHASE_D0[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_DQB1L_TXPHASE_D0[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_DQB1H_TXPHASE_D0[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_DQB2L_TXPHASE_D0[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_DQB2H_TXPHASE_D0[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_DQB3L_TXPHASE_D0[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_DQB3H_TXPHASE_D0[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_DBI_TXPHASE_D0[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_EDC_TXPHASE_D0[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_WCK_TXPHASE_D0[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_CK_TXPHASE_D0[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_ADDRL_TXPHASE_D0[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_ADDRH_TXPHASE_D0[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_ACMD_TXPHASE_D0[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_CMD_TXPHASE_D0[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_DQB0L_TXPHASE_D1[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_DQB0H_TXPHASE_D1[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_DQB1L_TXPHASE_D1[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_DQB1H_TXPHASE_D1[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_DQB2L_TXPHASE_D1[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_DQB2H_TXPHASE_D1[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_DQB3L_TXPHASE_D1[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_DQB3H_TXPHASE_D1[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_DBI_TXPHASE_D1[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_EDC_TXPHASE_D1[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_WCK_TXPHASE_D1[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_CK_TXPHASE_D1[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_ADDRL_TXPHASE_D1[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_ADDRH_TXPHASE_D1[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_ACMD_TXPHASE_D1[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_CMD_TXPHASE_D1[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_DQB0L_RX_VREF_CAL_D0[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_DQB0H_RX_VREF_CAL_D0[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_DQB1L_RX_VREF_CAL_D0[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_DQB1H_RX_VREF_CAL_D0[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_DQB2L_RX_VREF_CAL_D0[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_DQB2H_RX_VREF_CAL_D0[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_DQB3L_RX_VREF_CAL_D0[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_DQB3H_RX_VREF_CAL_D0[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_DBI_RX_VREF_CAL_D0[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_EDC_RX_VREF_CAL_D0[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_WCK_RX_VREF_CAL_D0[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_DQB0_CDR_PHSIZE_D0[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_DQB1_CDR_PHSIZE_D0[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_DQB2_CDR_PHSIZE_D0[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_DQB3_CDR_PHSIZE_D0[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_DBI_CDR_PHSIZE_D0[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_DQB0L_RX_VREF_CAL_D1[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_DQB0H_RX_VREF_CAL_D1[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_DQB1L_RX_VREF_CAL_D1[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_DQB1H_RX_VREF_CAL_D1[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_DQB2L_RX_VREF_CAL_D1[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_DQB2H_RX_VREF_CAL_D1[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_DQB3L_RX_VREF_CAL_D1[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_DQB3H_RX_VREF_CAL_D1[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_DBI_RX_VREF_CAL_D1[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_EDC_RX_VREF_CAL_D1[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_WCK_RX_VREF_CAL_D1[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_DQB0_CDR_PHSIZE_D1[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_DQB1_CDR_PHSIZE_D1[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_DQB2_CDR_PHSIZE_D1[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_DQB3_CDR_PHSIZE_D1[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_DBI_CDR_PHSIZE_D1[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_DQB0L_TXSLF_D0[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_DQB0H_TXSLF_D0[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_DQB1L_TXSLF_D0[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_DQB1H_TXSLF_D0[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_DQB2L_TXSLF_D0[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_DQB2H_TXSLF_D0[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_DQB3L_TXSLF_D0[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_DQB3H_TXSLF_D0[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_DBI_TXSLF_D0[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_EDC_TXSLF_D0[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_WCK_TXSLF_D0[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_CK_TXSLF_D0[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_ADDRL_TXSLF_D0[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_ADDRH_TXSLF_D0[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_ACMD_TXSLF_D0[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_CMD_TXSLF_D0[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_DQB0L_TXSLF_D1[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_DQB0H_TXSLF_D1[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_DQB1L_TXSLF_D1[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_DQB1H_TXSLF_D1[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_DQB2L_TXSLF_D1[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_DQB2H_TXSLF_D1[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_DQB3L_TXSLF_D1[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_DQB3H_TXSLF_D1[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_DBI_TXSLF_D1[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_EDC_TXSLF_D1[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_WCK_TXSLF_D1[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_CK_TXSLF_D1[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_ADDRL_TXSLF_D1[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_ADDRH_TXSLF_D1[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_ACMD_TXSLF_D1[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_CMD_TXSLF_D1[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_DQB0L_TXBST_PD_D0[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_DQB0H_TXBST_PD_D0[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_DQB1L_TXBST_PD_D0[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_DQB1H_TXBST_PD_D0[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_DQB2L_TXBST_PD_D0[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_DQB2H_TXBST_PD_D0[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_DQB3L_TXBST_PD_D0[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_DQB3H_TXBST_PD_D0[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_DBI_TXBST_PD_D0[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_EDC_TXBST_PD_D0[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_WCK_TXBST_PD_D0[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_CK_TXBST_PD_D0[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_ADDRL_TXBST_PD_D0[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_ADDRH_TXBST_PD_D0[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_ACMD_TXBST_PD_D0[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_CMD_TXBST_PD_D0[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_DQB0L_TXBST_PD_D1[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_DQB0H_TXBST_PD_D1[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_DQB1L_TXBST_PD_D1[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_DQB1H_TXBST_PD_D1[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_DQB2L_TXBST_PD_D1[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_DQB2H_TXBST_PD_D1[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_DQB3L_TXBST_PD_D1[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_DQB3H_TXBST_PD_D1[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_DBI_TXBST_PD_D1[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_EDC_TXBST_PD_D1[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_WCK_TXBST_PD_D1[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_CK_TXBST_PD_D1[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_ADDRL_TXBST_PD_D1[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_ADDRH_TXBST_PD_D1[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_ACMD_TXBST_PD_D1[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_CMD_TXBST_PD_D1[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_DQB0L_TXBST_PU_D0[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_DQB0H_TXBST_PU_D0[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_DQB1L_TXBST_PU_D0[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_DQB1H_TXBST_PU_D0[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_DQB2L_TXBST_PU_D0[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_DQB2H_TXBST_PU_D0[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_DQB3L_TXBST_PU_D0[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_DQB3H_TXBST_PU_D0[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_DBI_TXBST_PU_D0[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_EDC_TXBST_PU_D0[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_WCK_TXBST_PU_D0[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_CK_TXBST_PU_D0[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_ADDRL_TXBST_PU_D0[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_ADDRH_TXBST_PU_D0[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_ACMD_TXBST_PU_D0[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_CMD_TXBST_PU_D0[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_DQB0L_TXBST_PU_D1[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_DQB0H_TXBST_PU_D1[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_DQB1L_TXBST_PU_D1[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_DQB1H_TXBST_PU_D1[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_DQB2L_TXBST_PU_D1[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_DQB2H_TXBST_PU_D1[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_DQB3L_TXBST_PU_D1[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_DQB3H_TXBST_PU_D1[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_DBI_TXBST_PU_D1[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_EDC_TXBST_PU_D1[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_WCK_TXBST_PU_D1[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_CK_TXBST_PU_D1[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_ADDRL_TXBST_PU_D1[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_ADDRH_TXBST_PU_D1[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_ACMD_TXBST_PU_D1[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_CMD_TXBST_PU_D1[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_DQB0L_RX_EQ_D0[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_DQB0H_RX_EQ_D0[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_DQB1L_RX_EQ_D0[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_DQB1H_RX_EQ_D0[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_DQB2L_RX_EQ_D0[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_DQB2H_RX_EQ_D0[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_DQB3L_RX_EQ_D0[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_DQB3H_RX_EQ_D0[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_DBI_RX_EQ_D0[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_EDC_RX_EQ_D0[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_WCK_RX_EQ_D0[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_DQ0_RX_EQ_PM_D0[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_DQ1_RX_EQ_PM_D0[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_DQ0_RX_DYN_PM_D0[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_DQ1_RX_DYN_PM_D0[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_CMD_RX_EQ_D0[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_DQB0L_RX_EQ_D1[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_DQB0H_RX_EQ_D1[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_DQB1L_RX_EQ_D1[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_DQB1H_RX_EQ_D1[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_DQB2L_RX_EQ_D1[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_DQB2H_RX_EQ_D1[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_DQB3L_RX_EQ_D1[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_DQB3H_RX_EQ_D1[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_DBI_RX_EQ_D1[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_EDC_RX_EQ_D1[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_WCK_RX_EQ_D1[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_DQ0_RX_EQ_PM_D1[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_DQ1_RX_EQ_PM_D1[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_DQ0_RX_DYN_PM_D1[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_DQ1_RX_DYN_PM_D1[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_CMD_RX_EQ_D1[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_WCDR_MISC_D0[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_WCDR_CLKSEL_D0[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_WCDR_OFSCAL_D0[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_WCDR_RXPHASE_D0[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_WCDR_TXPHASE_D0[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_WCDR_RX_VREF_CAL_D0[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_WCDR_TXSLF_D0[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_WCDR_TXBST_PD_D0[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_WCDR_TXBST_PU_D0[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_WCDR_RX_EQ_D0[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_WCDR_CDR_PHSIZE_D0[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_WCDR_RX_EQ_PM_D0[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_WCDR_RX_DYN_PM_D0[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_WCDR_MISC_D1[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_WCDR_CLKSEL_D1[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_WCDR_OFSCAL_D1[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_WCDR_RXPHASE_D1[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_WCDR_TXPHASE_D1[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_WCDR_RX_VREF_CAL_D1[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_WCDR_TXSLF_D1[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_WCDR_TXBST_PD_D1[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_WCDR_TXBST_PU_D1[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_WCDR_RX_EQ_D1[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_WCDR_CDR_PHSIZE_D1[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_WCDR_RX_EQ_PM_D1[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMC_IO_DEBUG_WCDR_RX_DYN_PM_D1[] = {
	 { "VALUE0", 0, 7, &umr_bitfield_default },
	 { "VALUE1", 8, 15, &umr_bitfield_default },
	 { "VALUE2", 16, 23, &umr_bitfield_default },
	 { "VALUE3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmVM_L2_CNTL[] = {
	 { "CONTEXT1_IDENTITY_ACCESS_MODE", 19, 20, &umr_bitfield_default },
	 { "EFFECTIVE_L2_QUEUE_SIZE", 15, 17, &umr_bitfield_default },
	 { "ENABLE_L2_CACHE", 0, 0, &umr_bitfield_default },
	 { "ENABLE_L2_FRAGMENT_PROCESSING", 1, 1, &umr_bitfield_default },
	 { "ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE", 10, 10, &umr_bitfield_default },
	 { "ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE", 9, 9, &umr_bitfield_default },
	 { "IDENTITY_MODE_FRAGMENT_SIZE", 21, 25, &umr_bitfield_default },
	 { "L2_CACHE_4K_SWAP_TAG_INDEX_LSBS", 26, 27, &umr_bitfield_default },
	 { "L2_CACHE_BIGK_SWAP_TAG_INDEX_LSBS", 28, 30, &umr_bitfield_default },
	 { "L2_CACHE_PDE_ENDIAN_SWAP_MODE", 4, 5, &umr_bitfield_default },
	 { "L2_CACHE_PTE_ENDIAN_SWAP_MODE", 2, 3, &umr_bitfield_default },
	 { "L2_PDE0_CACHE_SPLIT_MODE", 12, 14, &umr_bitfield_default },
	 { "L2_PDE0_CACHE_TAG_GENERATION_MODE", 8, 8, &umr_bitfield_default },
	 { "PDE_FAULT_CLASSIFICATION", 18, 18, &umr_bitfield_default },
};
static struct umr_bitfield mmVM_L2_CNTL2[] = {
	 { "DISABLE_BIGK_CACHE_OPTIMIZATION", 22, 22, &umr_bitfield_default },
	 { "DISABLE_INVALIDATE_PER_DOMAIN", 21, 21, &umr_bitfield_default },
	 { "INVALIDATE_ALL_L1_TLBS", 0, 0, &umr_bitfield_default },
	 { "INVALIDATE_CACHE_MODE", 26, 27, &umr_bitfield_default },
	 { "INVALIDATE_L2_CACHE", 1, 1, &umr_bitfield_default },
	 { "L2_CACHE_BIGK_VMID_MODE", 23, 25, &umr_bitfield_default },
};
static struct umr_bitfield mmVM_L2_CNTL3[] = {
	 { "BANK_SELECT", 0, 5, &umr_bitfield_default },
	 { "L2_CACHE_4K_EFFECTIVE_SIZE", 21, 23, &umr_bitfield_default },
	 { "L2_CACHE_4K_FORCE_MISS", 28, 28, &umr_bitfield_default },
	 { "L2_CACHE_BIGK_ASSOCIATIVITY", 20, 20, &umr_bitfield_default },
	 { "L2_CACHE_BIGK_EFFECTIVE_SIZE", 24, 27, &umr_bitfield_default },
	 { "L2_CACHE_BIGK_FORCE_MISS", 29, 29, &umr_bitfield_default },
	 { "L2_CACHE_BIGK_FRAGMENT_SIZE", 15, 19, &umr_bitfield_default },
	 { "L2_CACHE_UPDATE_MODE", 6, 7, &umr_bitfield_default },
	 { "L2_CACHE_UPDATE_WILDCARD_REFERENCE_VALUE", 8, 12, &umr_bitfield_default },
};
static struct umr_bitfield mmVM_L2_STATUS[] = {
	 { "CONTEXT_DOMAIN_BUSY", 1, 16, &umr_bitfield_default },
	 { "L2_BUSY", 0, 0, &umr_bitfield_default },
};
static struct umr_bitfield mmVM_CONTEXT0_CNTL[] = {
	 { "DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT", 7, 7, &umr_bitfield_default },
	 { "DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT", 6, 6, &umr_bitfield_default },
	 { "ENABLE_CONTEXT", 0, 0, &umr_bitfield_default },
	 { "PAGE_TABLE_BLOCK_SIZE", 24, 27, &umr_bitfield_default },
	 { "PAGE_TABLE_DEPTH", 1, 2, &umr_bitfield_default },
	 { "PDE0_PROTECTION_FAULT_ENABLE_DEFAULT", 10, 10, &umr_bitfield_default },
	 { "PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT", 9, 9, &umr_bitfield_default },
	 { "PDE0_PROTECTION_FAULT_ENABLE_SAVE", 11, 11, &umr_bitfield_default },
	 { "PRIVILEGED_PROTECTION_FAULT_ENABLE_DEFAULT", 22, 22, &umr_bitfield_default },
	 { "PRIVILEGED_PROTECTION_FAULT_ENABLE_INTERRUPT", 21, 21, &umr_bitfield_default },
	 { "PRIVILEGED_PROTECTION_FAULT_ENABLE_SAVE", 23, 23, &umr_bitfield_default },
	 { "RANGE_PROTECTION_FAULT_ENABLE_DEFAULT", 4, 4, &umr_bitfield_default },
	 { "RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT", 3, 3, &umr_bitfield_default },
	 { "READ_PROTECTION_FAULT_ENABLE_DEFAULT", 16, 16, &umr_bitfield_default },
	 { "READ_PROTECTION_FAULT_ENABLE_INTERRUPT", 15, 15, &umr_bitfield_default },
	 { "READ_PROTECTION_FAULT_ENABLE_SAVE", 17, 17, &umr_bitfield_default },
	 { "VALID_PROTECTION_FAULT_ENABLE_DEFAULT", 13, 13, &umr_bitfield_default },
	 { "VALID_PROTECTION_FAULT_ENABLE_INTERRUPT", 12, 12, &umr_bitfield_default },
	 { "VALID_PROTECTION_FAULT_ENABLE_SAVE", 14, 14, &umr_bitfield_default },
	 { "WRITE_PROTECTION_FAULT_ENABLE_DEFAULT", 19, 19, &umr_bitfield_default },
	 { "WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT", 18, 18, &umr_bitfield_default },
	 { "WRITE_PROTECTION_FAULT_ENABLE_SAVE", 20, 20, &umr_bitfield_default },
};
static struct umr_bitfield mmVM_CONTEXT1_CNTL[] = {
	 { "DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT", 7, 7, &umr_bitfield_default },
	 { "DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT", 6, 6, &umr_bitfield_default },
	 { "ENABLE_CONTEXT", 0, 0, &umr_bitfield_default },
	 { "PAGE_TABLE_BLOCK_SIZE", 24, 27, &umr_bitfield_default },
	 { "PAGE_TABLE_DEPTH", 1, 2, &umr_bitfield_default },
	 { "PDE0_PROTECTION_FAULT_ENABLE_DEFAULT", 10, 10, &umr_bitfield_default },
	 { "PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT", 9, 9, &umr_bitfield_default },
	 { "PDE0_PROTECTION_FAULT_ENABLE_SAVE", 11, 11, &umr_bitfield_default },
	 { "PRIVILEGED_PROTECTION_FAULT_ENABLE_DEFAULT", 22, 22, &umr_bitfield_default },
	 { "PRIVILEGED_PROTECTION_FAULT_ENABLE_INTERRUPT", 21, 21, &umr_bitfield_default },
	 { "PRIVILEGED_PROTECTION_FAULT_ENABLE_SAVE", 23, 23, &umr_bitfield_default },
	 { "RANGE_PROTECTION_FAULT_ENABLE_DEFAULT", 4, 4, &umr_bitfield_default },
	 { "RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT", 3, 3, &umr_bitfield_default },
	 { "READ_PROTECTION_FAULT_ENABLE_DEFAULT", 16, 16, &umr_bitfield_default },
	 { "READ_PROTECTION_FAULT_ENABLE_INTERRUPT", 15, 15, &umr_bitfield_default },
	 { "READ_PROTECTION_FAULT_ENABLE_SAVE", 17, 17, &umr_bitfield_default },
	 { "VALID_PROTECTION_FAULT_ENABLE_DEFAULT", 13, 13, &umr_bitfield_default },
	 { "VALID_PROTECTION_FAULT_ENABLE_INTERRUPT", 12, 12, &umr_bitfield_default },
	 { "VALID_PROTECTION_FAULT_ENABLE_SAVE", 14, 14, &umr_bitfield_default },
	 { "WRITE_PROTECTION_FAULT_ENABLE_DEFAULT", 19, 19, &umr_bitfield_default },
	 { "WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT", 18, 18, &umr_bitfield_default },
	 { "WRITE_PROTECTION_FAULT_ENABLE_SAVE", 20, 20, &umr_bitfield_default },
};
static struct umr_bitfield mmVM_DUMMY_PAGE_FAULT_CNTL[] = {
	 { "DUMMY_PAGE_ADDRESS_LOGICAL", 1, 1, &umr_bitfield_default },
	 { "DUMMY_PAGE_COMPARE_MASK", 2, 3, &umr_bitfield_default },
	 { "DUMMY_PAGE_FAULT_ENABLE", 0, 0, &umr_bitfield_default },
};
static struct umr_bitfield mmVM_DUMMY_PAGE_FAULT_ADDR[] = {
	 { "DUMMY_PAGE_ADDR", 0, 27, &umr_bitfield_default },
};
static struct umr_bitfield mmVM_CONTEXT0_CNTL2[] = {
	 { "ALLOW_SUBSEQUENT_PROTECTION_FAULT_STATUS_ADDR_UPDATES", 3, 3, &umr_bitfield_default },
	 { "CLEAR_PROTECTION_FAULT_STATUS_ADDR", 0, 0, &umr_bitfield_default },
	 { "ENABLE_CLEAR_PROTECTION_FAULT_STATUS_ADDR_WHEN_INVALIDATE_CONTEXT", 1, 1, &umr_bitfield_default },
	 { "ENABLE_INTERRUPT_PROCESSING_FOR_SUBSEQUENT_FAULTS_PER_CONTEXT", 2, 2, &umr_bitfield_default },
	 { "WAIT_FOR_IDLE_WHEN_INVALIDATE", 4, 4, &umr_bitfield_default },
};
static struct umr_bitfield mmVM_CONTEXT1_CNTL2[] = {
	 { "ALLOW_SUBSEQUENT_PROTECTION_FAULT_STATUS_ADDR_UPDATES", 3, 3, &umr_bitfield_default },
	 { "CLEAR_PROTECTION_FAULT_STATUS_ADDR", 0, 0, &umr_bitfield_default },
	 { "ENABLE_CLEAR_PROTECTION_FAULT_STATUS_ADDR_WHEN_INVALIDATE_CONTEXT", 1, 1, &umr_bitfield_default },
	 { "ENABLE_INTERRUPT_PROCESSING_FOR_SUBSEQUENT_FAULTS_PER_CONTEXT", 2, 2, &umr_bitfield_default },
	 { "WAIT_FOR_IDLE_WHEN_INVALIDATE", 4, 4, &umr_bitfield_default },
};
static struct umr_bitfield mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR[] = {
	 { "PHYSICAL_PAGE_NUMBER", 0, 27, &umr_bitfield_default },
};
static struct umr_bitfield mmVM_CONTEXT9_PAGE_TABLE_BASE_ADDR[] = {
	 { "PHYSICAL_PAGE_NUMBER", 0, 27, &umr_bitfield_default },
};
static struct umr_bitfield mmVM_CONTEXT10_PAGE_TABLE_BASE_ADDR[] = {
	 { "PHYSICAL_PAGE_NUMBER", 0, 27, &umr_bitfield_default },
};
static struct umr_bitfield mmVM_CONTEXT11_PAGE_TABLE_BASE_ADDR[] = {
	 { "PHYSICAL_PAGE_NUMBER", 0, 27, &umr_bitfield_default },
};
static struct umr_bitfield mmVM_CONTEXT12_PAGE_TABLE_BASE_ADDR[] = {
	 { "PHYSICAL_PAGE_NUMBER", 0, 27, &umr_bitfield_default },
};
static struct umr_bitfield mmVM_CONTEXT13_PAGE_TABLE_BASE_ADDR[] = {
	 { "PHYSICAL_PAGE_NUMBER", 0, 27, &umr_bitfield_default },
};
static struct umr_bitfield mmVM_CONTEXT14_PAGE_TABLE_BASE_ADDR[] = {
	 { "PHYSICAL_PAGE_NUMBER", 0, 27, &umr_bitfield_default },
};
static struct umr_bitfield mmVM_CONTEXT15_PAGE_TABLE_BASE_ADDR[] = {
	 { "PHYSICAL_PAGE_NUMBER", 0, 27, &umr_bitfield_default },
};
static struct umr_bitfield mmVM_INVALIDATE_REQUEST[] = {
	 { "INVALIDATE_DOMAIN_0", 0, 0, &umr_bitfield_default },
	 { "INVALIDATE_DOMAIN_10", 10, 10, &umr_bitfield_default },
	 { "INVALIDATE_DOMAIN_11", 11, 11, &umr_bitfield_default },
	 { "INVALIDATE_DOMAIN_12", 12, 12, &umr_bitfield_default },
	 { "INVALIDATE_DOMAIN_13", 13, 13, &umr_bitfield_default },
	 { "INVALIDATE_DOMAIN_14", 14, 14, &umr_bitfield_default },
	 { "INVALIDATE_DOMAIN_15", 15, 15, &umr_bitfield_default },
	 { "INVALIDATE_DOMAIN_1", 1, 1, &umr_bitfield_default },
	 { "INVALIDATE_DOMAIN_2", 2, 2, &umr_bitfield_default },
	 { "INVALIDATE_DOMAIN_3", 3, 3, &umr_bitfield_default },
	 { "INVALIDATE_DOMAIN_4", 4, 4, &umr_bitfield_default },
	 { "INVALIDATE_DOMAIN_5", 5, 5, &umr_bitfield_default },
	 { "INVALIDATE_DOMAIN_6", 6, 6, &umr_bitfield_default },
	 { "INVALIDATE_DOMAIN_7", 7, 7, &umr_bitfield_default },
	 { "INVALIDATE_DOMAIN_8", 8, 8, &umr_bitfield_default },
	 { "INVALIDATE_DOMAIN_9", 9, 9, &umr_bitfield_default },
};
static struct umr_bitfield mmVM_INVALIDATE_RESPONSE[] = {
	 { "DOMAIN_INVALIDATED_0", 0, 0, &umr_bitfield_default },
	 { "DOMAIN_INVALIDATED_10", 10, 10, &umr_bitfield_default },
	 { "DOMAIN_INVALIDATED_11", 11, 11, &umr_bitfield_default },
	 { "DOMAIN_INVALIDATED_12", 12, 12, &umr_bitfield_default },
	 { "DOMAIN_INVALIDATED_13", 13, 13, &umr_bitfield_default },
	 { "DOMAIN_INVALIDATED_14", 14, 14, &umr_bitfield_default },
	 { "DOMAIN_INVALIDATED_15", 15, 15, &umr_bitfield_default },
	 { "DOMAIN_INVALIDATED_1", 1, 1, &umr_bitfield_default },
	 { "DOMAIN_INVALIDATED_2", 2, 2, &umr_bitfield_default },
	 { "DOMAIN_INVALIDATED_3", 3, 3, &umr_bitfield_default },
	 { "DOMAIN_INVALIDATED_4", 4, 4, &umr_bitfield_default },
	 { "DOMAIN_INVALIDATED_5", 5, 5, &umr_bitfield_default },
	 { "DOMAIN_INVALIDATED_6", 6, 6, &umr_bitfield_default },
	 { "DOMAIN_INVALIDATED_7", 7, 7, &umr_bitfield_default },
	 { "DOMAIN_INVALIDATED_8", 8, 8, &umr_bitfield_default },
	 { "DOMAIN_INVALIDATED_9", 9, 9, &umr_bitfield_default },
};
static struct umr_bitfield mmVM_PRT_APERTURE0_LOW_ADDR[] = {
	 { "LOGICAL_PAGE_NUMBER", 0, 27, &umr_bitfield_default },
};
static struct umr_bitfield mmVM_PRT_APERTURE1_LOW_ADDR[] = {
	 { "LOGICAL_PAGE_NUMBER", 0, 27, &umr_bitfield_default },
};
static struct umr_bitfield mmVM_PRT_APERTURE2_LOW_ADDR[] = {
	 { "LOGICAL_PAGE_NUMBER", 0, 27, &umr_bitfield_default },
};
static struct umr_bitfield mmVM_PRT_APERTURE3_LOW_ADDR[] = {
	 { "LOGICAL_PAGE_NUMBER", 0, 27, &umr_bitfield_default },
};
static struct umr_bitfield mmVM_PRT_APERTURE0_HIGH_ADDR[] = {
	 { "LOGICAL_PAGE_NUMBER", 0, 27, &umr_bitfield_default },
};
static struct umr_bitfield mmVM_PRT_APERTURE1_HIGH_ADDR[] = {
	 { "LOGICAL_PAGE_NUMBER", 0, 27, &umr_bitfield_default },
};
static struct umr_bitfield mmVM_PRT_APERTURE2_HIGH_ADDR[] = {
	 { "LOGICAL_PAGE_NUMBER", 0, 27, &umr_bitfield_default },
};
static struct umr_bitfield mmVM_PRT_APERTURE3_HIGH_ADDR[] = {
	 { "LOGICAL_PAGE_NUMBER", 0, 27, &umr_bitfield_default },
};
static struct umr_bitfield mmVM_PRT_CNTL[] = {
	 { "L1_TLB_STORE_INVALID_ENTRIES", 3, 3, &umr_bitfield_default },
	 { "L2_CACHE_STORE_INVALID_ENTRIES", 2, 2, &umr_bitfield_default },
	 { "CB_DISABLE_FAULT_ON_UNMAPPED_ACCESS", 0, 0, &umr_bitfield_default },
	 { "TC_DISABLE_FAULT_ON_UNMAPPED_ACCESS", 1, 1, &umr_bitfield_default },
};
static struct umr_bitfield mmVM_CONTEXTS_DISABLE[] = {
	 { "DISABLE_CONTEXT_0", 0, 0, &umr_bitfield_default },
	 { "DISABLE_CONTEXT_10", 10, 10, &umr_bitfield_default },
	 { "DISABLE_CONTEXT_11", 11, 11, &umr_bitfield_default },
	 { "DISABLE_CONTEXT_12", 12, 12, &umr_bitfield_default },
	 { "DISABLE_CONTEXT_13", 13, 13, &umr_bitfield_default },
	 { "DISABLE_CONTEXT_14", 14, 14, &umr_bitfield_default },
	 { "DISABLE_CONTEXT_15", 15, 15, &umr_bitfield_default },
	 { "DISABLE_CONTEXT_1", 1, 1, &umr_bitfield_default },
	 { "DISABLE_CONTEXT_2", 2, 2, &umr_bitfield_default },
	 { "DISABLE_CONTEXT_3", 3, 3, &umr_bitfield_default },
	 { "DISABLE_CONTEXT_4", 4, 4, &umr_bitfield_default },
	 { "DISABLE_CONTEXT_5", 5, 5, &umr_bitfield_default },
	 { "DISABLE_CONTEXT_6", 6, 6, &umr_bitfield_default },
	 { "DISABLE_CONTEXT_7", 7, 7, &umr_bitfield_default },
	 { "DISABLE_CONTEXT_8", 8, 8, &umr_bitfield_default },
	 { "DISABLE_CONTEXT_9", 9, 9, &umr_bitfield_default },
};
static struct umr_bitfield mmVM_CONTEXT0_PROTECTION_FAULT_STATUS[] = {
	 { "MEMORY_CLIENT_ID", 12, 19, &umr_bitfield_default },
	 { "MEMORY_CLIENT_RW", 24, 24, &umr_bitfield_default },
	 { "PROTECTIONS", 0, 7, &umr_bitfield_default },
	 { "VMID", 25, 28, &umr_bitfield_default },
};
static struct umr_bitfield mmVM_CONTEXT1_PROTECTION_FAULT_STATUS[] = {
	 { "MEMORY_CLIENT_ID", 12, 19, &umr_bitfield_default },
	 { "MEMORY_CLIENT_RW", 24, 24, &umr_bitfield_default },
	 { "PROTECTIONS", 0, 7, &umr_bitfield_default },
	 { "VMID", 25, 28, &umr_bitfield_default },
};
static struct umr_bitfield mmVM_CONTEXT0_PROTECTION_FAULT_ADDR[] = {
	 { "LOGICAL_PAGE_ADDR", 0, 27, &umr_bitfield_default },
};
static struct umr_bitfield mmVM_CONTEXT1_PROTECTION_FAULT_ADDR[] = {
	 { "LOGICAL_PAGE_ADDR", 0, 27, &umr_bitfield_default },
};
static struct umr_bitfield mmVM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR[] = {
	 { "PHYSICAL_PAGE_ADDR", 0, 27, &umr_bitfield_default },
};
static struct umr_bitfield mmVM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR[] = {
	 { "PHYSICAL_PAGE_ADDR", 0, 27, &umr_bitfield_default },
};
static struct umr_bitfield mmVM_FAULT_CLIENT_ID[] = {
	 { "MEMORY_CLIENT", 0, 8, &umr_bitfield_default },
	 { "MEMORY_CLIENT_MASK", 9, 17, &umr_bitfield_default },
};
static struct umr_bitfield mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR[] = {
	 { "PHYSICAL_PAGE_NUMBER", 0, 27, &umr_bitfield_default },
};
static struct umr_bitfield mmVM_CONTEXT1_PAGE_TABLE_BASE_ADDR[] = {
	 { "PHYSICAL_PAGE_NUMBER", 0, 27, &umr_bitfield_default },
};
static struct umr_bitfield mmVM_CONTEXT2_PAGE_TABLE_BASE_ADDR[] = {
	 { "PHYSICAL_PAGE_NUMBER", 0, 27, &umr_bitfield_default },
};
static struct umr_bitfield mmVM_CONTEXT3_PAGE_TABLE_BASE_ADDR[] = {
	 { "PHYSICAL_PAGE_NUMBER", 0, 27, &umr_bitfield_default },
};
static struct umr_bitfield mmVM_CONTEXT4_PAGE_TABLE_BASE_ADDR[] = {
	 { "PHYSICAL_PAGE_NUMBER", 0, 27, &umr_bitfield_default },
};
static struct umr_bitfield mmVM_CONTEXT5_PAGE_TABLE_BASE_ADDR[] = {
	 { "PHYSICAL_PAGE_NUMBER", 0, 27, &umr_bitfield_default },
};
static struct umr_bitfield mmVM_CONTEXT6_PAGE_TABLE_BASE_ADDR[] = {
	 { "PHYSICAL_PAGE_NUMBER", 0, 27, &umr_bitfield_default },
};
static struct umr_bitfield mmVM_CONTEXT7_PAGE_TABLE_BASE_ADDR[] = {
	 { "PHYSICAL_PAGE_NUMBER", 0, 27, &umr_bitfield_default },
};
static struct umr_bitfield mmVM_CONTEXT0_PAGE_TABLE_START_ADDR[] = {
	 { "LOGICAL_PAGE_NUMBER", 0, 27, &umr_bitfield_default },
};
static struct umr_bitfield mmVM_CONTEXT1_PAGE_TABLE_START_ADDR[] = {
	 { "LOGICAL_PAGE_NUMBER", 0, 27, &umr_bitfield_default },
};
static struct umr_bitfield mmVM_CONTEXT0_PAGE_TABLE_END_ADDR[] = {
	 { "LOGICAL_PAGE_NUMBER", 0, 27, &umr_bitfield_default },
};
static struct umr_bitfield mmVM_CONTEXT1_PAGE_TABLE_END_ADDR[] = {
	 { "LOGICAL_PAGE_NUMBER", 0, 27, &umr_bitfield_default },
};
static struct umr_bitfield mmVM_DEBUG[] = {
	 { "FLAGS", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmVM_L2_CG[] = {
	 { "ENABLE", 18, 18, &umr_bitfield_default },
	 { "MEM_LS_ENABLE", 19, 19, &umr_bitfield_default },
	 { "OFFDLY", 6, 11, &umr_bitfield_default },
};
static struct umr_bitfield mmVM_L2_BANK_SELECT_MASKA[] = {
	 { "BANK_SELECT_MASK", 0, 27, &umr_bitfield_default },
};
static struct umr_bitfield mmVM_L2_BANK_SELECT_MASKB[] = {
	 { "BANK_SELECT_MASK", 0, 7, &umr_bitfield_default },
};
static struct umr_bitfield mmVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR[] = {
	 { "LOGICAL_PAGE_NUMBER", 0, 27, &umr_bitfield_default },
};
static struct umr_bitfield mmVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR[] = {
	 { "LOGICAL_PAGE_NUMBER", 0, 27, &umr_bitfield_default },
};
static struct umr_bitfield mmVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET[] = {
	 { "PHYSICAL_PAGE_OFFSET", 0, 27, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_CONFIG[] = {
	 { "MCC_INDEX_MODE_ENABLE", 31, 31, &umr_bitfield_default },
	 { "MCDW_WR_ENABLE", 0, 0, &umr_bitfield_default },
	 { "MCDX_WR_ENABLE", 1, 1, &umr_bitfield_default },
	 { "MCDY_WR_ENABLE", 2, 2, &umr_bitfield_default },
	 { "MCDZ_WR_ENABLE", 3, 3, &umr_bitfield_default },
	 { "MC_RD_ENABLE", 4, 5, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_SHARED_CHMAP[] = {
	 { "CHAN0", 0, 3, &umr_bitfield_default },
	 { "CHAN1", 4, 7, &umr_bitfield_default },
	 { "CHAN2", 8, 11, &umr_bitfield_default },
	 { "NOOFCHAN", 12, 15, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_SHARED_CHREMAP[] = {
	 { "CHAN0", 0, 2, &umr_bitfield_default },
	 { "CHAN1", 3, 5, &umr_bitfield_default },
	 { "CHAN2", 6, 8, &umr_bitfield_default },
	 { "CHAN3", 9, 11, &umr_bitfield_default },
	 { "CHAN4", 12, 14, &umr_bitfield_default },
	 { "CHAN5", 15, 17, &umr_bitfield_default },
	 { "CHAN6", 18, 20, &umr_bitfield_default },
	 { "CHAN7", 21, 23, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_RD_GRP_GFX[] = {
	 { "CP", 0, 3, &umr_bitfield_default },
	 { "XDMAM", 16, 19, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_WR_GRP_GFX[] = {
	 { "CP", 0, 3, &umr_bitfield_default },
	 { "XDMA", 12, 15, &umr_bitfield_default },
	 { "XDMAM", 16, 19, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_RD_GRP_SYS[] = {
	 { "DMIF", 12, 15, &umr_bitfield_default },
	 { "MCIF", 16, 19, &umr_bitfield_default },
	 { "RLC", 0, 3, &umr_bitfield_default },
	 { "SMU", 20, 23, &umr_bitfield_default },
	 { "VCE", 24, 27, &umr_bitfield_default },
	 { "VCEU", 28, 31, &umr_bitfield_default },
	 { "VMC", 4, 7, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_WR_GRP_SYS[] = {
	 { "IH", 0, 3, &umr_bitfield_default },
	 { "MCIF", 4, 7, &umr_bitfield_default },
	 { "RLC", 8, 11, &umr_bitfield_default },
	 { "SMU", 20, 23, &umr_bitfield_default },
	 { "VCE", 24, 27, &umr_bitfield_default },
	 { "VCEU", 28, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_RD_GRP_OTH[] = {
	 { "HDP", 8, 11, &umr_bitfield_default },
	 { "SEM", 12, 15, &umr_bitfield_default },
	 { "UMC", 16, 19, &umr_bitfield_default },
	 { "UVD_EXT0", 0, 3, &umr_bitfield_default },
	 { "UVD_EXT1", 24, 27, &umr_bitfield_default },
	 { "UVD", 20, 23, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_WR_GRP_OTH[] = {
	 { "HDP", 8, 11, &umr_bitfield_default },
	 { "SEM", 12, 15, &umr_bitfield_default },
	 { "UMC", 16, 19, &umr_bitfield_default },
	 { "UVD_EXT0", 0, 3, &umr_bitfield_default },
	 { "UVD_EXT1", 28, 31, &umr_bitfield_default },
	 { "UVD", 20, 23, &umr_bitfield_default },
	 { "XDP", 24, 27, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_VM_FB_LOCATION[] = {
	 { "FB_BASE", 0, 15, &umr_bitfield_default },
	 { "FB_TOP", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_VM_AGP_TOP[] = {
	 { "AGP_TOP", 0, 17, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_VM_AGP_BOT[] = {
	 { "AGP_BOT", 0, 17, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_VM_AGP_BASE[] = {
	 { "AGP_BASE", 0, 17, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_VM_SYSTEM_APERTURE_LOW_ADDR[] = {
	 { "LOGICAL_PAGE_NUMBER", 0, 27, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR[] = {
	 { "LOGICAL_PAGE_NUMBER", 0, 27, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR[] = {
	 { "PHYSICAL_PAGE_NUMBER", 0, 27, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_VM_DC_WRITE_CNTL[] = {
	 { "DC_MEMORY_WRITE_LOCAL", 8, 8, &umr_bitfield_default },
	 { "DC_MEMORY_WRITE_SYSTEM", 9, 9, &umr_bitfield_default },
	 { "DC_WRITE_HIT_REGION_0_MODE", 0, 1, &umr_bitfield_default },
	 { "DC_WRITE_HIT_REGION_1_MODE", 2, 3, &umr_bitfield_default },
	 { "DC_WRITE_HIT_REGION_2_MODE", 4, 5, &umr_bitfield_default },
	 { "DC_WRITE_HIT_REGION_3_MODE", 6, 7, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_VM_DC_WRITE_HIT_REGION_0_LOW_ADDR[] = {
	 { "PHYSICAL_ADDRESS", 0, 27, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_VM_DC_WRITE_HIT_REGION_1_LOW_ADDR[] = {
	 { "PHYSICAL_ADDRESS", 0, 27, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_VM_DC_WRITE_HIT_REGION_2_LOW_ADDR[] = {
	 { "PHYSICAL_ADDRESS", 0, 27, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_VM_DC_WRITE_HIT_REGION_3_LOW_ADDR[] = {
	 { "PHYSICAL_ADDRESS", 0, 27, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_VM_DC_WRITE_HIT_REGION_0_HIGH_ADDR[] = {
	 { "PHYSICAL_ADDRESS", 0, 27, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_VM_DC_WRITE_HIT_REGION_1_HIGH_ADDR[] = {
	 { "PHYSICAL_ADDRESS", 0, 27, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_VM_DC_WRITE_HIT_REGION_2_HIGH_ADDR[] = {
	 { "PHYSICAL_ADDRESS", 0, 27, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_VM_DC_WRITE_HIT_REGION_3_HIGH_ADDR[] = {
	 { "PHYSICAL_ADDRESS", 0, 27, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_VM_MX_L1_TLB_CNTL[] = {
	 { "ECO_BITS", 7, 10, &umr_bitfield_default },
	 { "ENABLE_ADVANCED_DRIVER_MODEL", 6, 6, &umr_bitfield_default },
	 { "ENABLE_L1_FRAGMENT_PROCESSING", 1, 1, &umr_bitfield_default },
	 { "ENABLE_L1_TLB", 0, 0, &umr_bitfield_default },
	 { "SYSTEM_ACCESS_MODE", 3, 4, &umr_bitfield_default },
	 { "SYSTEM_APERTURE_UNMAPPED_ACCESS", 5, 5, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_VM_FB_OFFSET[] = {
	 { "FB_OFFSET", 0, 17, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_CONFIG_MCD[] = {
	 { "MCD0_WR_ENABLE", 0, 0, &umr_bitfield_default },
	 { "MCD1_WR_ENABLE", 1, 1, &umr_bitfield_default },
	 { "MCD2_WR_ENABLE", 2, 2, &umr_bitfield_default },
	 { "MCD3_WR_ENABLE", 3, 3, &umr_bitfield_default },
	 { "MCD4_WR_ENABLE", 4, 4, &umr_bitfield_default },
	 { "MCD5_WR_ENABLE", 5, 5, &umr_bitfield_default },
	 { "MCD_INDEX_MODE_ENABLE", 31, 31, &umr_bitfield_default },
	 { "MC_RD_ENABLE", 8, 10, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_CG_CONFIG_MCD[] = {
	 { "INDEX", 13, 28, &umr_bitfield_default },
	 { "MCD0_WR_ENABLE", 0, 0, &umr_bitfield_default },
	 { "MCD1_WR_ENABLE", 1, 1, &umr_bitfield_default },
	 { "MCD2_WR_ENABLE", 2, 2, &umr_bitfield_default },
	 { "MCD3_WR_ENABLE", 3, 3, &umr_bitfield_default },
	 { "MCD4_WR_ENABLE", 4, 4, &umr_bitfield_default },
	 { "MCD5_WR_ENABLE", 5, 5, &umr_bitfield_default },
	 { "MC_RD_ENABLE", 8, 10, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_MEM_POWER_LS[] = {
	 { "LS_HOLD", 6, 11, &umr_bitfield_default },
	 { "LS_SETUP", 0, 5, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_SHARED_BLACKOUT_CNTL[] = {
	 { "BLACKOUT_MODE", 0, 2, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_HUB_MISC_POWER[] = {
	 { "PM_BLACKOUT_CNTL", 3, 4, &umr_bitfield_default },
	 { "SRBM_GATE_OVERRIDE", 2, 2, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_HUB_MISC_HUB_CG[] = {
	 { "ENABLE", 18, 18, &umr_bitfield_default },
	 { "MEM_LS_ENABLE", 19, 19, &umr_bitfield_default },
	 { "OFFDLY", 6, 11, &umr_bitfield_default },
	 { "ONDLY", 0, 5, &umr_bitfield_default },
	 { "RDYDLY", 12, 17, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_HUB_MISC_VM_CG[] = {
	 { "ENABLE", 18, 18, &umr_bitfield_default },
	 { "MEM_LS_ENABLE", 19, 19, &umr_bitfield_default },
	 { "OFFDLY", 6, 11, &umr_bitfield_default },
	 { "ONDLY", 0, 5, &umr_bitfield_default },
	 { "RDYDLY", 12, 17, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_HUB_MISC_SIP_CG[] = {
	 { "ENABLE", 18, 18, &umr_bitfield_default },
	 { "MEM_LS_ENABLE", 19, 19, &umr_bitfield_default },
	 { "OFFDLY", 6, 11, &umr_bitfield_default },
	 { "ONDLY", 0, 5, &umr_bitfield_default },
	 { "RDYDLY", 12, 17, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_HUB_MISC_DBG[] = {
	 { "SELECT0", 0, 3, &umr_bitfield_default },
	 { "SELECT1", 4, 7, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_HUB_MISC_STATUS[] = {
	 { "GFX_BUSY", 13, 13, &umr_bitfield_default },
	 { "OUTSTANDING_HUB_RDREQ", 2, 2, &umr_bitfield_default },
	 { "OUTSTANDING_HUB_RDRET", 3, 3, &umr_bitfield_default },
	 { "OUTSTANDING_HUB_WRREQ", 4, 4, &umr_bitfield_default },
	 { "OUTSTANDING_HUB_WRRET", 5, 5, &umr_bitfield_default },
	 { "OUTSTANDING_MCD_READ", 8, 8, &umr_bitfield_default },
	 { "OUTSTANDING_MCD_WRITE", 9, 9, &umr_bitfield_default },
	 { "OUTSTANDING_READ", 0, 0, &umr_bitfield_default },
	 { "OUTSTANDING_RPB_READ", 6, 6, &umr_bitfield_default },
	 { "OUTSTANDING_RPB_WRITE", 7, 7, &umr_bitfield_default },
	 { "OUTSTANDING_WRITE", 1, 1, &umr_bitfield_default },
	 { "READ_DEADLOCK_WARNING", 12, 12, &umr_bitfield_default },
	 { "RPB_BUSY", 10, 10, &umr_bitfield_default },
	 { "WRITE_DEADLOCK_WARNING", 11, 11, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_HUB_MISC_OVERRIDE[] = {
	 { "IDLE", 0, 1, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_HUB_MISC_FRAMING[] = {
	 { "BITS", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_HUB_WDP_CNTL[] = {
	 { "DEBUG_REG", 5, 12, &umr_bitfield_default },
	 { "DISABLE_SELF_INIT_GBL0", 13, 13, &umr_bitfield_default },
	 { "DISABLE_SELF_INIT_GBL1", 14, 14, &umr_bitfield_default },
	 { "DISABLE_SELF_INIT_INTERNAL", 15, 15, &umr_bitfield_default },
	 { "DISP_WAIT_EOP", 18, 18, &umr_bitfield_default },
	 { "FAIR_CH_SW", 16, 16, &umr_bitfield_default },
	 { "JUMPAHEAD_GBL0", 1, 1, &umr_bitfield_default },
	 { "JUMPAHEAD_GBL1", 2, 2, &umr_bitfield_default },
	 { "JUMPAHEAD_INTERNAL", 3, 3, &umr_bitfield_default },
	 { "LCLWRREQ_BYPASS", 17, 17, &umr_bitfield_default },
	 { "MCD_WAIT_EOP", 19, 19, &umr_bitfield_default },
	 { "OVERRIDE_STALL_ENABLE", 4, 4, &umr_bitfield_default },
	 { "SIP_WAIT_EOP", 20, 20, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_HUB_WDP_ERR[] = {
	 { "MGPU1_TARG_SYS", 0, 0, &umr_bitfield_default },
	 { "MGPU2_TARG_SYS", 1, 1, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_HUB_WDP_BP[] = {
	 { "ENABLE", 0, 0, &umr_bitfield_default },
	 { "RDRET", 1, 17, &umr_bitfield_default },
	 { "WRREQ", 18, 29, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_HUB_WDP_STATUS[] = {
	 { "GBL0_BYPASS_STOR_FULL", 7, 7, &umr_bitfield_default },
	 { "GBL0_STOR_FULL", 6, 6, &umr_bitfield_default },
	 { "GBL0_VM_FULL", 5, 5, &umr_bitfield_default },
	 { "GBL1_BYPASS_STOR_FULL", 10, 10, &umr_bitfield_default },
	 { "GBL1_STOR_FULL", 9, 9, &umr_bitfield_default },
	 { "GBL1_VM_FULL", 8, 8, &umr_bitfield_default },
	 { "MCDW_RD_AVAIL", 1, 1, &umr_bitfield_default },
	 { "MCDW_WR_AVAIL", 11, 11, &umr_bitfield_default },
	 { "MCDX_RD_AVAIL", 2, 2, &umr_bitfield_default },
	 { "MCDX_WR_AVAIL", 12, 12, &umr_bitfield_default },
	 { "MCDY_RD_AVAIL", 3, 3, &umr_bitfield_default },
	 { "MCDY_WR_AVAIL", 13, 13, &umr_bitfield_default },
	 { "MCDZ_RD_AVAIL", 4, 4, &umr_bitfield_default },
	 { "MCDZ_WR_AVAIL", 14, 14, &umr_bitfield_default },
	 { "SIP_AVAIL", 0, 0, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_HUB_RDREQ_STATUS[] = {
	 { "GBL0_BYPASS_STOR_FULL", 7, 7, &umr_bitfield_default },
	 { "GBL0_STOR_FULL", 6, 6, &umr_bitfield_default },
	 { "GBL0_VM_FULL", 5, 5, &umr_bitfield_default },
	 { "GBL1_BYPASS_STOR_FULL", 10, 10, &umr_bitfield_default },
	 { "GBL1_STOR_FULL", 9, 9, &umr_bitfield_default },
	 { "GBL1_VM_FULL", 8, 8, &umr_bitfield_default },
	 { "MCDW_RD_AVAIL", 1, 1, &umr_bitfield_default },
	 { "MCDX_RD_AVAIL", 2, 2, &umr_bitfield_default },
	 { "MCDY_RD_AVAIL", 3, 3, &umr_bitfield_default },
	 { "MCDZ_RD_AVAIL", 4, 4, &umr_bitfield_default },
	 { "PWRXPRESS_ERR", 11, 11, &umr_bitfield_default },
	 { "SIP_AVAIL", 0, 0, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_HUB_WRRET_STATUS[] = {
	 { "MCDW_AVAIL", 0, 0, &umr_bitfield_default },
	 { "MCDX_AVAIL", 1, 1, &umr_bitfield_default },
	 { "MCDY_AVAIL", 2, 2, &umr_bitfield_default },
	 { "MCDZ_AVAIL", 3, 3, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_HUB_RDREQ_CNTL[] = {
	 { "BREAK_HDP_DEADLOCK", 9, 9, &umr_bitfield_default },
	 { "DEBUG_REG", 10, 16, &umr_bitfield_default },
	 { "DISABLE_SELF_INIT_GBL0", 17, 17, &umr_bitfield_default },
	 { "DISABLE_SELF_INIT_GBL1", 18, 18, &umr_bitfield_default },
	 { "JUMPAHEAD_GBL0", 2, 2, &umr_bitfield_default },
	 { "JUMPAHEAD_GBL1", 3, 3, &umr_bitfield_default },
	 { "MCDW_STALL_MODE", 5, 5, &umr_bitfield_default },
	 { "MCDX_STALL_MODE", 6, 6, &umr_bitfield_default },
	 { "MCDY_STALL_MODE", 7, 7, &umr_bitfield_default },
	 { "MCDZ_STALL_MODE", 8, 8, &umr_bitfield_default },
	 { "OVERRIDE_STALL_ENABLE", 4, 4, &umr_bitfield_default },
	 { "PWRXPRESS_MODE", 19, 19, &umr_bitfield_default },
	 { "REMOTE_BLACKOUT", 0, 0, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_HUB_WRRET_CNTL[] = {
	 { "BP_ENABLE", 21, 21, &umr_bitfield_default },
	 { "BP", 1, 20, &umr_bitfield_default },
	 { "DEBUG_REG", 22, 29, &umr_bitfield_default },
	 { "DISABLE_SELF_INIT", 30, 30, &umr_bitfield_default },
	 { "FAIR_CH_SW", 31, 31, &umr_bitfield_default },
	 { "JUMPAHEAD", 0, 0, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_HUB_RDREQ_WTM_CNTL[] = {
	 { "GROUP0_DECREMENT", 0, 2, &umr_bitfield_default },
	 { "GROUP1_DECREMENT", 3, 5, &umr_bitfield_default },
	 { "GROUP2_DECREMENT", 6, 8, &umr_bitfield_default },
	 { "GROUP3_DECREMENT", 9, 11, &umr_bitfield_default },
	 { "GROUP4_DECREMENT", 12, 14, &umr_bitfield_default },
	 { "GROUP5_DECREMENT", 15, 17, &umr_bitfield_default },
	 { "GROUP6_DECREMENT", 18, 20, &umr_bitfield_default },
	 { "GROUP7_DECREMENT", 21, 23, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_HUB_WDP_WTM_CNTL[] = {
	 { "GROUP0_DECREMENT", 0, 2, &umr_bitfield_default },
	 { "GROUP1_DECREMENT", 3, 5, &umr_bitfield_default },
	 { "GROUP2_DECREMENT", 6, 8, &umr_bitfield_default },
	 { "GROUP3_DECREMENT", 9, 11, &umr_bitfield_default },
	 { "GROUP4_DECREMENT", 12, 14, &umr_bitfield_default },
	 { "GROUP5_DECREMENT", 15, 17, &umr_bitfield_default },
	 { "GROUP6_DECREMENT", 18, 20, &umr_bitfield_default },
	 { "GROUP7_DECREMENT", 21, 23, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_HUB_WDP_CREDITS[] = {
	 { "STOR0", 16, 23, &umr_bitfield_default },
	 { "STOR1", 24, 31, &umr_bitfield_default },
	 { "VM0", 0, 7, &umr_bitfield_default },
	 { "VM1", 8, 15, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_HUB_WDP_MGPU2[] = {
	 { "CID2", 0, 7, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_HUB_WDP_GBL0[] = {
	 { "LAZY_TIMER", 4, 7, &umr_bitfield_default },
	 { "MAXBURST", 0, 3, &umr_bitfield_default },
	 { "STALL_MODE", 16, 16, &umr_bitfield_default },
	 { "STALL_THRESHOLD", 8, 15, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_HUB_WDP_GBL1[] = {
	 { "LAZY_TIMER", 4, 7, &umr_bitfield_default },
	 { "MAXBURST", 0, 3, &umr_bitfield_default },
	 { "STALL_MODE", 16, 16, &umr_bitfield_default },
	 { "STALL_THRESHOLD", 8, 15, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_HUB_WDP_MGPU[] = {
	 { "CID", 8, 15, &umr_bitfield_default },
	 { "ENABLE", 23, 23, &umr_bitfield_default },
	 { "MGPU_PRIORITY_TIME", 16, 22, &umr_bitfield_default },
	 { "OTH_PRIORITY_TIME", 24, 30, &umr_bitfield_default },
	 { "STOR", 0, 7, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_HUB_RDREQ_CREDITS[] = {
	 { "STOR0", 16, 23, &umr_bitfield_default },
	 { "STOR1", 24, 31, &umr_bitfield_default },
	 { "VM0", 0, 7, &umr_bitfield_default },
	 { "VM1", 8, 15, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_HUB_RDREQ_CREDITS2[] = {
	 { "STOR1_PRI", 0, 7, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_HUB_SHARED_DAGB_DLY[] = {
	 { "CLI", 16, 20, &umr_bitfield_default },
	 { "DLY", 0, 5, &umr_bitfield_default },
	 { "POS", 24, 28, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_HUB_MISC_IDLE_STATUS[] = {
	 { "OUTSTANDING_CP_READ", 0, 0, &umr_bitfield_default },
	 { "OUTSTANDING_CP_WRITE", 1, 1, &umr_bitfield_default },
	 { "OUTSTANDING_DISP_READ", 10, 10, &umr_bitfield_default },
	 { "OUTSTANDING_DISP_WRITE", 11, 11, &umr_bitfield_default },
	 { "OUTSTANDING_GFX_READ", 2, 2, &umr_bitfield_default },
	 { "OUTSTANDING_GFX_WRITE", 3, 3, &umr_bitfield_default },
	 { "OUTSTANDING_HDP_READ", 16, 16, &umr_bitfield_default },
	 { "OUTSTANDING_HDP_WRITE", 17, 17, &umr_bitfield_default },
	 { "OUTSTANDING_OTH_READ", 18, 18, &umr_bitfield_default },
	 { "OUTSTANDING_OTH_WRITE", 19, 19, &umr_bitfield_default },
	 { "OUTSTANDING_RLC_READ", 6, 6, &umr_bitfield_default },
	 { "OUTSTANDING_RLC_WRITE", 7, 7, &umr_bitfield_default },
	 { "OUTSTANDING_SMU_READ", 14, 14, &umr_bitfield_default },
	 { "OUTSTANDING_SMU_WRITE", 15, 15, &umr_bitfield_default },
	 { "OUTSTANDING_UVD_READ", 12, 12, &umr_bitfield_default },
	 { "OUTSTANDING_UVD_WRITE", 13, 13, &umr_bitfield_default },
	 { "OUTSTANDING_VCE_READ", 24, 24, &umr_bitfield_default },
	 { "OUTSTANDING_VCE_WRITE", 25, 25, &umr_bitfield_default },
	 { "OUTSTANDING_VMC_READ", 20, 20, &umr_bitfield_default },
	 { "OUTSTANDING_VMC_WRITE", 21, 21, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_HUB_RDREQ_DMIF_LIMIT[] = {
	 { "ENABLE", 0, 1, &umr_bitfield_default },
	 { "LIMIT_COUNT", 2, 6, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_HUB_RDREQ_MCDW[] = {
	 { "ASK_CREDITS", 11, 17, &umr_bitfield_default },
	 { "BLACKOUT_EXEMPT", 1, 1, &umr_bitfield_default },
	 { "BUS", 2, 2, &umr_bitfield_default },
	 { "DISPLAY_CREDITS", 18, 24, &umr_bitfield_default },
	 { "ENABLE", 0, 0, &umr_bitfield_default },
	 { "LAZY_TIMER", 7, 10, &umr_bitfield_default },
	 { "MAXBURST", 3, 6, &umr_bitfield_default },
	 { "STALL_THRESHOLD", 25, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_HUB_RDREQ_MCDX[] = {
	 { "ASK_CREDITS", 11, 17, &umr_bitfield_default },
	 { "BLACKOUT_EXEMPT", 1, 1, &umr_bitfield_default },
	 { "BUS", 2, 2, &umr_bitfield_default },
	 { "DISPLAY_CREDITS", 18, 24, &umr_bitfield_default },
	 { "ENABLE", 0, 0, &umr_bitfield_default },
	 { "LAZY_TIMER", 7, 10, &umr_bitfield_default },
	 { "MAXBURST", 3, 6, &umr_bitfield_default },
	 { "STALL_THRESHOLD", 25, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_HUB_RDREQ_MCDY[] = {
	 { "ASK_CREDITS", 11, 17, &umr_bitfield_default },
	 { "BLACKOUT_EXEMPT", 1, 1, &umr_bitfield_default },
	 { "BUS", 2, 2, &umr_bitfield_default },
	 { "DISPLAY_CREDITS", 18, 24, &umr_bitfield_default },
	 { "ENABLE", 0, 0, &umr_bitfield_default },
	 { "LAZY_TIMER", 7, 10, &umr_bitfield_default },
	 { "MAXBURST", 3, 6, &umr_bitfield_default },
	 { "STALL_THRESHOLD", 25, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_HUB_RDREQ_MCDZ[] = {
	 { "ASK_CREDITS", 11, 17, &umr_bitfield_default },
	 { "BLACKOUT_EXEMPT", 1, 1, &umr_bitfield_default },
	 { "BUS", 2, 2, &umr_bitfield_default },
	 { "DISPLAY_CREDITS", 18, 24, &umr_bitfield_default },
	 { "ENABLE", 0, 0, &umr_bitfield_default },
	 { "LAZY_TIMER", 7, 10, &umr_bitfield_default },
	 { "MAXBURST", 3, 6, &umr_bitfield_default },
	 { "STALL_THRESHOLD", 25, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_HUB_RDREQ_SIP[] = {
	 { "ASK_CREDITS", 0, 6, &umr_bitfield_default },
	 { "DISPLAY_CREDITS", 8, 14, &umr_bitfield_default },
	 { "DUMMY", 7, 7, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_HUB_RDREQ_GBL0[] = {
	 { "STALL_THRESHOLD", 0, 7, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_HUB_RDREQ_GBL1[] = {
	 { "STALL_THRESHOLD", 0, 7, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_HUB_RDREQ_SMU[] = {
	 { "BLACKOUT_EXEMPT", 3, 3, &umr_bitfield_default },
	 { "ENABLE", 0, 0, &umr_bitfield_default },
	 { "LAZY_TIMER", 11, 14, &umr_bitfield_default },
	 { "MAXBURST", 7, 10, &umr_bitfield_default },
	 { "PRESCALE", 1, 2, &umr_bitfield_default },
	 { "STALL_MODE", 4, 5, &umr_bitfield_default },
	 { "STALL_OVERRIDE", 6, 6, &umr_bitfield_default },
	 { "STALL_OVERRIDE_WTM", 15, 15, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_HUB_RDREQ_HDP[] = {
	 { "BLACKOUT_EXEMPT", 3, 3, &umr_bitfield_default },
	 { "ENABLE", 0, 0, &umr_bitfield_default },
	 { "LAZY_TIMER", 11, 14, &umr_bitfield_default },
	 { "MAXBURST", 7, 10, &umr_bitfield_default },
	 { "PRESCALE", 1, 2, &umr_bitfield_default },
	 { "STALL_MODE", 4, 5, &umr_bitfield_default },
	 { "STALL_OVERRIDE", 6, 6, &umr_bitfield_default },
	 { "STALL_OVERRIDE_WTM", 15, 15, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_HUB_RDREQ_RLC[] = {
	 { "BLACKOUT_EXEMPT", 3, 3, &umr_bitfield_default },
	 { "ENABLE", 0, 0, &umr_bitfield_default },
	 { "LAZY_TIMER", 11, 14, &umr_bitfield_default },
	 { "MAXBURST", 7, 10, &umr_bitfield_default },
	 { "PRESCALE", 1, 2, &umr_bitfield_default },
	 { "STALL_MODE", 4, 5, &umr_bitfield_default },
	 { "STALL_OVERRIDE", 6, 6, &umr_bitfield_default },
	 { "STALL_OVERRIDE_WTM", 15, 15, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_HUB_RDREQ_SEM[] = {
	 { "BLACKOUT_EXEMPT", 3, 3, &umr_bitfield_default },
	 { "ENABLE", 0, 0, &umr_bitfield_default },
	 { "LAZY_TIMER", 11, 14, &umr_bitfield_default },
	 { "MAXBURST", 7, 10, &umr_bitfield_default },
	 { "PRESCALE", 1, 2, &umr_bitfield_default },
	 { "STALL_MODE", 4, 5, &umr_bitfield_default },
	 { "STALL_OVERRIDE", 6, 6, &umr_bitfield_default },
	 { "STALL_OVERRIDE_WTM", 15, 15, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_HUB_RDREQ_VCE[] = {
	 { "BLACKOUT_EXEMPT", 3, 3, &umr_bitfield_default },
	 { "ENABLE", 0, 0, &umr_bitfield_default },
	 { "LAZY_TIMER", 11, 14, &umr_bitfield_default },
	 { "MAXBURST", 7, 10, &umr_bitfield_default },
	 { "PRESCALE", 1, 2, &umr_bitfield_default },
	 { "STALL_MODE", 4, 5, &umr_bitfield_default },
	 { "STALL_OVERRIDE", 6, 6, &umr_bitfield_default },
	 { "STALL_OVERRIDE_WTM", 15, 15, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_HUB_RDREQ_UMC[] = {
	 { "BLACKOUT_EXEMPT", 3, 3, &umr_bitfield_default },
	 { "ENABLE", 0, 0, &umr_bitfield_default },
	 { "LAZY_TIMER", 11, 14, &umr_bitfield_default },
	 { "MAXBURST", 7, 10, &umr_bitfield_default },
	 { "PRESCALE", 1, 2, &umr_bitfield_default },
	 { "STALL_MODE", 4, 5, &umr_bitfield_default },
	 { "STALL_OVERRIDE", 6, 6, &umr_bitfield_default },
	 { "STALL_OVERRIDE_WTM", 15, 15, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_HUB_RDREQ_UVD[] = {
	 { "BLACKOUT_EXEMPT", 3, 3, &umr_bitfield_default },
	 { "ENABLE", 0, 0, &umr_bitfield_default },
	 { "LAZY_TIMER", 11, 14, &umr_bitfield_default },
	 { "MAXBURST", 7, 10, &umr_bitfield_default },
	 { "PRESCALE", 1, 2, &umr_bitfield_default },
	 { "STALL_MODE", 4, 5, &umr_bitfield_default },
	 { "STALL_OVERRIDE", 6, 6, &umr_bitfield_default },
	 { "STALL_OVERRIDE_WTM", 15, 15, &umr_bitfield_default },
	 { "VM_BYPASS", 16, 16, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_HUB_RDREQ_DMIF[] = {
	 { "BLACKOUT_EXEMPT", 3, 3, &umr_bitfield_default },
	 { "ENABLE", 0, 0, &umr_bitfield_default },
	 { "LAZY_TIMER", 11, 14, &umr_bitfield_default },
	 { "MAXBURST", 7, 10, &umr_bitfield_default },
	 { "PRESCALE", 1, 2, &umr_bitfield_default },
	 { "STALL_MODE", 4, 5, &umr_bitfield_default },
	 { "STALL_OVERRIDE", 6, 6, &umr_bitfield_default },
	 { "STALL_OVERRIDE_WTM", 15, 15, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_HUB_RDREQ_MCIF[] = {
	 { "BLACKOUT_EXEMPT", 3, 3, &umr_bitfield_default },
	 { "ENABLE", 0, 0, &umr_bitfield_default },
	 { "LAZY_TIMER", 11, 14, &umr_bitfield_default },
	 { "MAXBURST", 7, 10, &umr_bitfield_default },
	 { "PRESCALE", 1, 2, &umr_bitfield_default },
	 { "STALL_MODE", 4, 5, &umr_bitfield_default },
	 { "STALL_OVERRIDE", 6, 6, &umr_bitfield_default },
	 { "STALL_OVERRIDE_WTM", 15, 15, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_HUB_RDREQ_VMC[] = {
	 { "BLACKOUT_EXEMPT", 3, 3, &umr_bitfield_default },
	 { "ENABLE", 0, 0, &umr_bitfield_default },
	 { "LAZY_TIMER", 11, 14, &umr_bitfield_default },
	 { "MAXBURST", 7, 10, &umr_bitfield_default },
	 { "PRESCALE", 1, 2, &umr_bitfield_default },
	 { "STALL_MODE", 4, 5, &umr_bitfield_default },
	 { "STALL_OVERRIDE", 6, 6, &umr_bitfield_default },
	 { "STALL_OVERRIDE_WTM", 15, 15, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_HUB_RDREQ_VCEU[] = {
	 { "BLACKOUT_EXEMPT", 3, 3, &umr_bitfield_default },
	 { "ENABLE", 0, 0, &umr_bitfield_default },
	 { "LAZY_TIMER", 11, 14, &umr_bitfield_default },
	 { "MAXBURST", 7, 10, &umr_bitfield_default },
	 { "PRESCALE", 1, 2, &umr_bitfield_default },
	 { "STALL_MODE", 4, 5, &umr_bitfield_default },
	 { "STALL_OVERRIDE", 6, 6, &umr_bitfield_default },
	 { "STALL_OVERRIDE_WTM", 15, 15, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_HUB_WDP_MCDW[] = {
	 { "ASK_CREDITS", 7, 12, &umr_bitfield_default },
	 { "ASK_CREDITS_W", 24, 30, &umr_bitfield_default },
	 { "BLACKOUT_EXEMPT", 1, 1, &umr_bitfield_default },
	 { "ENABLE", 0, 0, &umr_bitfield_default },
	 { "LAZY_TIMER", 13, 16, &umr_bitfield_default },
	 { "MAXBURST", 3, 6, &umr_bitfield_default },
	 { "STALL_MODE", 2, 2, &umr_bitfield_default },
	 { "STALL_THRESHOLD", 17, 23, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_HUB_WDP_MCDX[] = {
	 { "ASK_CREDITS", 7, 12, &umr_bitfield_default },
	 { "ASK_CREDITS_W", 24, 30, &umr_bitfield_default },
	 { "BLACKOUT_EXEMPT", 1, 1, &umr_bitfield_default },
	 { "ENABLE", 0, 0, &umr_bitfield_default },
	 { "LAZY_TIMER", 13, 16, &umr_bitfield_default },
	 { "MAXBURST", 3, 6, &umr_bitfield_default },
	 { "STALL_MODE", 2, 2, &umr_bitfield_default },
	 { "STALL_THRESHOLD", 17, 23, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_HUB_WDP_MCDY[] = {
	 { "ASK_CREDITS", 7, 12, &umr_bitfield_default },
	 { "ASK_CREDITS_W", 24, 30, &umr_bitfield_default },
	 { "BLACKOUT_EXEMPT", 1, 1, &umr_bitfield_default },
	 { "ENABLE", 0, 0, &umr_bitfield_default },
	 { "LAZY_TIMER", 13, 16, &umr_bitfield_default },
	 { "MAXBURST", 3, 6, &umr_bitfield_default },
	 { "STALL_MODE", 2, 2, &umr_bitfield_default },
	 { "STALL_THRESHOLD", 17, 23, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_HUB_WDP_MCDZ[] = {
	 { "ASK_CREDITS", 7, 12, &umr_bitfield_default },
	 { "ASK_CREDITS_W", 24, 30, &umr_bitfield_default },
	 { "BLACKOUT_EXEMPT", 1, 1, &umr_bitfield_default },
	 { "ENABLE", 0, 0, &umr_bitfield_default },
	 { "LAZY_TIMER", 13, 16, &umr_bitfield_default },
	 { "MAXBURST", 3, 6, &umr_bitfield_default },
	 { "STALL_MODE", 2, 2, &umr_bitfield_default },
	 { "STALL_THRESHOLD", 17, 23, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_HUB_WDP_SIP[] = {
	 { "ASK_CREDITS", 2, 8, &umr_bitfield_default },
	 { "STALL_MODE", 0, 1, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_HUB_WDP_SH0[] = {
	 { "BLACKOUT_EXEMPT", 3, 3, &umr_bitfield_default },
	 { "ENABLE", 0, 0, &umr_bitfield_default },
	 { "LAZY_TIMER", 11, 14, &umr_bitfield_default },
	 { "MAXBURST", 7, 10, &umr_bitfield_default },
	 { "PRESCALE", 1, 2, &umr_bitfield_default },
	 { "STALL_MODE", 4, 5, &umr_bitfield_default },
	 { "STALL_OVERRIDE", 6, 6, &umr_bitfield_default },
	 { "STALL_OVERRIDE_WTM", 15, 15, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_HUB_WDP_MCIF[] = {
	 { "BLACKOUT_EXEMPT", 3, 3, &umr_bitfield_default },
	 { "ENABLE", 0, 0, &umr_bitfield_default },
	 { "LAZY_TIMER", 11, 14, &umr_bitfield_default },
	 { "MAXBURST", 7, 10, &umr_bitfield_default },
	 { "PRESCALE", 1, 2, &umr_bitfield_default },
	 { "STALL_MODE", 4, 5, &umr_bitfield_default },
	 { "STALL_OVERRIDE", 6, 6, &umr_bitfield_default },
	 { "STALL_OVERRIDE_WTM", 15, 15, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_HUB_WDP_VCE[] = {
	 { "BLACKOUT_EXEMPT", 3, 3, &umr_bitfield_default },
	 { "ENABLE", 0, 0, &umr_bitfield_default },
	 { "LAZY_TIMER", 11, 14, &umr_bitfield_default },
	 { "MAXBURST", 7, 10, &umr_bitfield_default },
	 { "PRESCALE", 1, 2, &umr_bitfield_default },
	 { "STALL_MODE", 4, 5, &umr_bitfield_default },
	 { "STALL_OVERRIDE", 6, 6, &umr_bitfield_default },
	 { "STALL_OVERRIDE_WTM", 15, 15, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_HUB_WDP_XDP[] = {
	 { "BLACKOUT_EXEMPT", 3, 3, &umr_bitfield_default },
	 { "ENABLE", 0, 0, &umr_bitfield_default },
	 { "LAZY_TIMER", 11, 14, &umr_bitfield_default },
	 { "MAXBURST", 7, 10, &umr_bitfield_default },
	 { "PRESCALE", 1, 2, &umr_bitfield_default },
	 { "STALL_MODE", 4, 5, &umr_bitfield_default },
	 { "STALL_OVERRIDE", 6, 6, &umr_bitfield_default },
	 { "STALL_OVERRIDE_WTM", 15, 15, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_HUB_WDP_IH[] = {
	 { "BLACKOUT_EXEMPT", 3, 3, &umr_bitfield_default },
	 { "ENABLE", 0, 0, &umr_bitfield_default },
	 { "LAZY_TIMER", 11, 14, &umr_bitfield_default },
	 { "MAXBURST", 7, 10, &umr_bitfield_default },
	 { "PRESCALE", 1, 2, &umr_bitfield_default },
	 { "STALL_MODE", 4, 5, &umr_bitfield_default },
	 { "STALL_OVERRIDE", 6, 6, &umr_bitfield_default },
	 { "STALL_OVERRIDE_WTM", 15, 15, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_HUB_WDP_RLC[] = {
	 { "BLACKOUT_EXEMPT", 3, 3, &umr_bitfield_default },
	 { "ENABLE", 0, 0, &umr_bitfield_default },
	 { "LAZY_TIMER", 11, 14, &umr_bitfield_default },
	 { "MAXBURST", 7, 10, &umr_bitfield_default },
	 { "PRESCALE", 1, 2, &umr_bitfield_default },
	 { "STALL_MODE", 4, 5, &umr_bitfield_default },
	 { "STALL_OVERRIDE", 6, 6, &umr_bitfield_default },
	 { "STALL_OVERRIDE_WTM", 15, 15, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_HUB_WDP_SEM[] = {
	 { "BLACKOUT_EXEMPT", 3, 3, &umr_bitfield_default },
	 { "ENABLE", 0, 0, &umr_bitfield_default },
	 { "LAZY_TIMER", 11, 14, &umr_bitfield_default },
	 { "MAXBURST", 7, 10, &umr_bitfield_default },
	 { "PRESCALE", 1, 2, &umr_bitfield_default },
	 { "STALL_MODE", 4, 5, &umr_bitfield_default },
	 { "STALL_OVERRIDE", 6, 6, &umr_bitfield_default },
	 { "STALL_OVERRIDE_WTM", 15, 15, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_HUB_WDP_SMU[] = {
	 { "BLACKOUT_EXEMPT", 3, 3, &umr_bitfield_default },
	 { "ENABLE", 0, 0, &umr_bitfield_default },
	 { "LAZY_TIMER", 11, 14, &umr_bitfield_default },
	 { "MAXBURST", 7, 10, &umr_bitfield_default },
	 { "PRESCALE", 1, 2, &umr_bitfield_default },
	 { "STALL_MODE", 4, 5, &umr_bitfield_default },
	 { "STALL_OVERRIDE", 6, 6, &umr_bitfield_default },
	 { "STALL_OVERRIDE_WTM", 15, 15, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_HUB_WDP_SH1[] = {
	 { "BLACKOUT_EXEMPT", 3, 3, &umr_bitfield_default },
	 { "ENABLE", 0, 0, &umr_bitfield_default },
	 { "LAZY_TIMER", 11, 14, &umr_bitfield_default },
	 { "MAXBURST", 7, 10, &umr_bitfield_default },
	 { "PRESCALE", 1, 2, &umr_bitfield_default },
	 { "STALL_MODE", 4, 5, &umr_bitfield_default },
	 { "STALL_OVERRIDE", 6, 6, &umr_bitfield_default },
	 { "STALL_OVERRIDE_WTM", 15, 15, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_HUB_WDP_UMC[] = {
	 { "BLACKOUT_EXEMPT", 3, 3, &umr_bitfield_default },
	 { "ENABLE", 0, 0, &umr_bitfield_default },
	 { "LAZY_TIMER", 11, 14, &umr_bitfield_default },
	 { "MAXBURST", 7, 10, &umr_bitfield_default },
	 { "PRESCALE", 1, 2, &umr_bitfield_default },
	 { "STALL_MODE", 4, 5, &umr_bitfield_default },
	 { "STALL_OVERRIDE", 6, 6, &umr_bitfield_default },
	 { "STALL_OVERRIDE_WTM", 15, 15, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_HUB_WDP_UVD[] = {
	 { "BLACKOUT_EXEMPT", 3, 3, &umr_bitfield_default },
	 { "ENABLE", 0, 0, &umr_bitfield_default },
	 { "LAZY_TIMER", 11, 14, &umr_bitfield_default },
	 { "MAXBURST", 7, 10, &umr_bitfield_default },
	 { "PRESCALE", 1, 2, &umr_bitfield_default },
	 { "STALL_MODE", 4, 5, &umr_bitfield_default },
	 { "STALL_OVERRIDE", 6, 6, &umr_bitfield_default },
	 { "STALL_OVERRIDE_WTM", 15, 15, &umr_bitfield_default },
	 { "VM_BYPASS", 16, 16, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_HUB_WDP_HDP[] = {
	 { "BLACKOUT_EXEMPT", 3, 3, &umr_bitfield_default },
	 { "ENABLE", 0, 0, &umr_bitfield_default },
	 { "LAZY_TIMER", 11, 14, &umr_bitfield_default },
	 { "MAXBURST", 7, 10, &umr_bitfield_default },
	 { "PRESCALE", 1, 2, &umr_bitfield_default },
	 { "STALL_MODE", 4, 5, &umr_bitfield_default },
	 { "STALL_OVERRIDE", 6, 6, &umr_bitfield_default },
	 { "STALL_OVERRIDE_WTM", 15, 15, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_HUB_WRRET_MCDW[] = {
	 { "CREDIT_COUNT", 1, 7, &umr_bitfield_default },
	 { "STALL_MODE", 0, 0, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_HUB_WRRET_MCDX[] = {
	 { "CREDIT_COUNT", 1, 7, &umr_bitfield_default },
	 { "STALL_MODE", 0, 0, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_HUB_WRRET_MCDY[] = {
	 { "CREDIT_COUNT", 1, 7, &umr_bitfield_default },
	 { "STALL_MODE", 0, 0, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_HUB_WRRET_MCDZ[] = {
	 { "CREDIT_COUNT", 1, 7, &umr_bitfield_default },
	 { "STALL_MODE", 0, 0, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_HUB_WDP_VCEU[] = {
	 { "BLACKOUT_EXEMPT", 3, 3, &umr_bitfield_default },
	 { "ENABLE", 0, 0, &umr_bitfield_default },
	 { "LAZY_TIMER", 11, 14, &umr_bitfield_default },
	 { "MAXBURST", 7, 10, &umr_bitfield_default },
	 { "PRESCALE", 1, 2, &umr_bitfield_default },
	 { "STALL_MODE", 4, 5, &umr_bitfield_default },
	 { "STALL_OVERRIDE", 6, 6, &umr_bitfield_default },
	 { "STALL_OVERRIDE_WTM", 15, 15, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_HUB_WDP_XDMAM[] = {
	 { "BLACKOUT_EXEMPT", 3, 3, &umr_bitfield_default },
	 { "BYPASS_AVAIL_OVERRIDE", 16, 16, &umr_bitfield_default },
	 { "ENABLE", 0, 0, &umr_bitfield_default },
	 { "LAZY_TIMER", 11, 14, &umr_bitfield_default },
	 { "MAXBURST", 7, 10, &umr_bitfield_default },
	 { "PRESCALE", 1, 2, &umr_bitfield_default },
	 { "STALL_MODE", 4, 5, &umr_bitfield_default },
	 { "STALL_OVERRIDE", 6, 6, &umr_bitfield_default },
	 { "STALL_OVERRIDE_WTM", 15, 15, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_HUB_WDP_XDMA[] = {
	 { "BLACKOUT_EXEMPT", 3, 3, &umr_bitfield_default },
	 { "BYPASS_AVAIL_OVERRIDE", 16, 16, &umr_bitfield_default },
	 { "ENABLE", 0, 0, &umr_bitfield_default },
	 { "LAZY_TIMER", 11, 14, &umr_bitfield_default },
	 { "MAXBURST", 7, 10, &umr_bitfield_default },
	 { "PRESCALE", 1, 2, &umr_bitfield_default },
	 { "STALL_MODE", 4, 5, &umr_bitfield_default },
	 { "STALL_OVERRIDE", 6, 6, &umr_bitfield_default },
	 { "STALL_OVERRIDE_WTM", 15, 15, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_HUB_RDREQ_XDMAM[] = {
	 { "BLACKOUT_EXEMPT", 3, 3, &umr_bitfield_default },
	 { "ENABLE", 0, 0, &umr_bitfield_default },
	 { "LAZY_TIMER", 11, 14, &umr_bitfield_default },
	 { "MAXBURST", 7, 10, &umr_bitfield_default },
	 { "PRESCALE", 1, 2, &umr_bitfield_default },
	 { "STALL_MODE", 4, 5, &umr_bitfield_default },
	 { "STALL_OVERRIDE", 6, 6, &umr_bitfield_default },
	 { "STALL_OVERRIDE_WTM", 15, 15, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_VM_MB_L1_TLB0_DEBUG[] = {
	 { "EFFECTIVE_L1_QUEUE_SIZE", 12, 14, &umr_bitfield_default },
	 { "EFFECTIVE_L1_TLB_SIZE", 9, 11, &umr_bitfield_default },
	 { "INVALIDATE_L1_TLB", 0, 0, &umr_bitfield_default },
	 { "L1_TLB_DEBUG", 15, 18, &umr_bitfield_default },
	 { "SEND_FREE_AT_RTN", 8, 8, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_VM_MB_L1_TLB2_DEBUG[] = {
	 { "EFFECTIVE_L1_QUEUE_SIZE", 12, 14, &umr_bitfield_default },
	 { "EFFECTIVE_L1_TLB_SIZE", 9, 11, &umr_bitfield_default },
	 { "INVALIDATE_L1_TLB", 0, 0, &umr_bitfield_default },
	 { "L1_TLB_DEBUG", 15, 18, &umr_bitfield_default },
	 { "SEND_FREE_AT_RTN", 8, 8, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_VM_MB_L1_TLB0_STATUS[] = {
	 { "BUSY", 0, 0, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_VM_MB_L1_TLB1_STATUS[] = {
	 { "BUSY", 0, 0, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_VM_MB_L1_TLB2_STATUS[] = {
	 { "BUSY", 0, 0, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_VM_MB_L2ARBITER_L2_CREDITS[] = {
	 { "L2_IF_CREDITS", 0, 5, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_VM_MB_L1_TLB3_DEBUG[] = {
	 { "EFFECTIVE_L1_QUEUE_SIZE", 12, 14, &umr_bitfield_default },
	 { "EFFECTIVE_L1_TLB_SIZE", 9, 11, &umr_bitfield_default },
	 { "INVALIDATE_L1_TLB", 0, 0, &umr_bitfield_default },
	 { "L1_TLB_DEBUG", 15, 18, &umr_bitfield_default },
	 { "SEND_FREE_AT_RTN", 8, 8, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_VM_MB_L1_TLB3_STATUS[] = {
	 { "BUSY", 0, 0, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_XPB_RTR_SRC_APRTR0[] = {
	 { "BASE_ADDR", 0, 24, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_XPB_RTR_SRC_APRTR1[] = {
	 { "BASE_ADDR", 0, 24, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_XPB_RTR_SRC_APRTR2[] = {
	 { "BASE_ADDR", 0, 24, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_XPB_RTR_SRC_APRTR3[] = {
	 { "BASE_ADDR", 0, 24, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_XPB_RTR_SRC_APRTR4[] = {
	 { "BASE_ADDR", 0, 24, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_XPB_RTR_SRC_APRTR5[] = {
	 { "BASE_ADDR", 0, 24, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_XPB_RTR_SRC_APRTR6[] = {
	 { "BASE_ADDR", 0, 24, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_XPB_RTR_SRC_APRTR7[] = {
	 { "BASE_ADDR", 0, 24, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_XPB_RTR_SRC_APRTR8[] = {
	 { "BASE_ADDR", 0, 24, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_XPB_RTR_SRC_APRTR9[] = {
	 { "BASE_ADDR", 0, 24, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_XPB_XDMA_RTR_SRC_APRTR0[] = {
	 { "BASE_ADDR", 0, 24, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_XPB_XDMA_RTR_SRC_APRTR1[] = {
	 { "BASE_ADDR", 0, 24, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_XPB_XDMA_RTR_SRC_APRTR2[] = {
	 { "BASE_ADDR", 0, 24, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_XPB_XDMA_RTR_SRC_APRTR3[] = {
	 { "BASE_ADDR", 0, 24, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_XPB_RTR_DEST_MAP0[] = {
	 { "APRTR_SIZE", 26, 30, &umr_bitfield_default },
	 { "DEST_OFFSET", 1, 19, &umr_bitfield_default },
	 { "DEST_SEL", 20, 23, &umr_bitfield_default },
	 { "DEST_SEL_RPB", 24, 24, &umr_bitfield_default },
	 { "NMR", 0, 0, &umr_bitfield_default },
	 { "SIDE_OK", 25, 25, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_XPB_RTR_DEST_MAP1[] = {
	 { "APRTR_SIZE", 26, 30, &umr_bitfield_default },
	 { "DEST_OFFSET", 1, 19, &umr_bitfield_default },
	 { "DEST_SEL", 20, 23, &umr_bitfield_default },
	 { "DEST_SEL_RPB", 24, 24, &umr_bitfield_default },
	 { "NMR", 0, 0, &umr_bitfield_default },
	 { "SIDE_OK", 25, 25, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_XPB_RTR_DEST_MAP2[] = {
	 { "APRTR_SIZE", 26, 30, &umr_bitfield_default },
	 { "DEST_OFFSET", 1, 19, &umr_bitfield_default },
	 { "DEST_SEL", 20, 23, &umr_bitfield_default },
	 { "DEST_SEL_RPB", 24, 24, &umr_bitfield_default },
	 { "NMR", 0, 0, &umr_bitfield_default },
	 { "SIDE_OK", 25, 25, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_XPB_RTR_DEST_MAP3[] = {
	 { "APRTR_SIZE", 26, 30, &umr_bitfield_default },
	 { "DEST_OFFSET", 1, 19, &umr_bitfield_default },
	 { "DEST_SEL", 20, 23, &umr_bitfield_default },
	 { "DEST_SEL_RPB", 24, 24, &umr_bitfield_default },
	 { "NMR", 0, 0, &umr_bitfield_default },
	 { "SIDE_OK", 25, 25, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_XPB_RTR_DEST_MAP4[] = {
	 { "APRTR_SIZE", 26, 30, &umr_bitfield_default },
	 { "DEST_OFFSET", 1, 19, &umr_bitfield_default },
	 { "DEST_SEL", 20, 23, &umr_bitfield_default },
	 { "DEST_SEL_RPB", 24, 24, &umr_bitfield_default },
	 { "NMR", 0, 0, &umr_bitfield_default },
	 { "SIDE_OK", 25, 25, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_XPB_RTR_DEST_MAP5[] = {
	 { "APRTR_SIZE", 26, 30, &umr_bitfield_default },
	 { "DEST_OFFSET", 1, 19, &umr_bitfield_default },
	 { "DEST_SEL", 20, 23, &umr_bitfield_default },
	 { "DEST_SEL_RPB", 24, 24, &umr_bitfield_default },
	 { "NMR", 0, 0, &umr_bitfield_default },
	 { "SIDE_OK", 25, 25, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_XPB_RTR_DEST_MAP6[] = {
	 { "APRTR_SIZE", 26, 30, &umr_bitfield_default },
	 { "DEST_OFFSET", 1, 19, &umr_bitfield_default },
	 { "DEST_SEL", 20, 23, &umr_bitfield_default },
	 { "DEST_SEL_RPB", 24, 24, &umr_bitfield_default },
	 { "NMR", 0, 0, &umr_bitfield_default },
	 { "SIDE_OK", 25, 25, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_XPB_RTR_DEST_MAP7[] = {
	 { "APRTR_SIZE", 26, 30, &umr_bitfield_default },
	 { "DEST_OFFSET", 1, 19, &umr_bitfield_default },
	 { "DEST_SEL", 20, 23, &umr_bitfield_default },
	 { "DEST_SEL_RPB", 24, 24, &umr_bitfield_default },
	 { "NMR", 0, 0, &umr_bitfield_default },
	 { "SIDE_OK", 25, 25, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_XPB_RTR_DEST_MAP8[] = {
	 { "APRTR_SIZE", 26, 30, &umr_bitfield_default },
	 { "DEST_OFFSET", 1, 19, &umr_bitfield_default },
	 { "DEST_SEL", 20, 23, &umr_bitfield_default },
	 { "DEST_SEL_RPB", 24, 24, &umr_bitfield_default },
	 { "NMR", 0, 0, &umr_bitfield_default },
	 { "SIDE_OK", 25, 25, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_XPB_RTR_DEST_MAP9[] = {
	 { "APRTR_SIZE", 26, 30, &umr_bitfield_default },
	 { "DEST_OFFSET", 1, 19, &umr_bitfield_default },
	 { "DEST_SEL", 20, 23, &umr_bitfield_default },
	 { "DEST_SEL_RPB", 24, 24, &umr_bitfield_default },
	 { "NMR", 0, 0, &umr_bitfield_default },
	 { "SIDE_OK", 25, 25, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_XPB_XDMA_RTR_DEST_MAP0[] = {
	 { "APRTR_SIZE", 26, 30, &umr_bitfield_default },
	 { "DEST_OFFSET", 1, 19, &umr_bitfield_default },
	 { "DEST_SEL", 20, 23, &umr_bitfield_default },
	 { "DEST_SEL_RPB", 24, 24, &umr_bitfield_default },
	 { "NMR", 0, 0, &umr_bitfield_default },
	 { "SIDE_OK", 25, 25, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_XPB_XDMA_RTR_DEST_MAP1[] = {
	 { "APRTR_SIZE", 26, 30, &umr_bitfield_default },
	 { "DEST_OFFSET", 1, 19, &umr_bitfield_default },
	 { "DEST_SEL", 20, 23, &umr_bitfield_default },
	 { "DEST_SEL_RPB", 24, 24, &umr_bitfield_default },
	 { "NMR", 0, 0, &umr_bitfield_default },
	 { "SIDE_OK", 25, 25, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_XPB_XDMA_RTR_DEST_MAP2[] = {
	 { "APRTR_SIZE", 26, 30, &umr_bitfield_default },
	 { "DEST_OFFSET", 1, 19, &umr_bitfield_default },
	 { "DEST_SEL", 20, 23, &umr_bitfield_default },
	 { "DEST_SEL_RPB", 24, 24, &umr_bitfield_default },
	 { "NMR", 0, 0, &umr_bitfield_default },
	 { "SIDE_OK", 25, 25, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_XPB_XDMA_RTR_DEST_MAP3[] = {
	 { "APRTR_SIZE", 26, 30, &umr_bitfield_default },
	 { "DEST_OFFSET", 1, 19, &umr_bitfield_default },
	 { "DEST_SEL", 20, 23, &umr_bitfield_default },
	 { "DEST_SEL_RPB", 24, 24, &umr_bitfield_default },
	 { "NMR", 0, 0, &umr_bitfield_default },
	 { "SIDE_OK", 25, 25, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_XPB_CLG_CFG0[] = {
	 { "HOST_FLUSH", 10, 13, &umr_bitfield_default },
	 { "LB_TYPE", 4, 6, &umr_bitfield_default },
	 { "P2P_BAR", 7, 9, &umr_bitfield_default },
	 { "SIDE_FLUSH", 14, 17, &umr_bitfield_default },
	 { "WCB_NUM", 0, 3, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_XPB_CLG_CFG1[] = {
	 { "HOST_FLUSH", 10, 13, &umr_bitfield_default },
	 { "LB_TYPE", 4, 6, &umr_bitfield_default },
	 { "P2P_BAR", 7, 9, &umr_bitfield_default },
	 { "SIDE_FLUSH", 14, 17, &umr_bitfield_default },
	 { "WCB_NUM", 0, 3, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_XPB_CLG_CFG2[] = {
	 { "HOST_FLUSH", 10, 13, &umr_bitfield_default },
	 { "LB_TYPE", 4, 6, &umr_bitfield_default },
	 { "P2P_BAR", 7, 9, &umr_bitfield_default },
	 { "SIDE_FLUSH", 14, 17, &umr_bitfield_default },
	 { "WCB_NUM", 0, 3, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_XPB_CLG_CFG3[] = {
	 { "HOST_FLUSH", 10, 13, &umr_bitfield_default },
	 { "LB_TYPE", 4, 6, &umr_bitfield_default },
	 { "P2P_BAR", 7, 9, &umr_bitfield_default },
	 { "SIDE_FLUSH", 14, 17, &umr_bitfield_default },
	 { "WCB_NUM", 0, 3, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_XPB_CLG_CFG4[] = {
	 { "HOST_FLUSH", 10, 13, &umr_bitfield_default },
	 { "LB_TYPE", 4, 6, &umr_bitfield_default },
	 { "P2P_BAR", 7, 9, &umr_bitfield_default },
	 { "SIDE_FLUSH", 14, 17, &umr_bitfield_default },
	 { "WCB_NUM", 0, 3, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_XPB_CLG_CFG5[] = {
	 { "HOST_FLUSH", 10, 13, &umr_bitfield_default },
	 { "LB_TYPE", 4, 6, &umr_bitfield_default },
	 { "P2P_BAR", 7, 9, &umr_bitfield_default },
	 { "SIDE_FLUSH", 14, 17, &umr_bitfield_default },
	 { "WCB_NUM", 0, 3, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_XPB_CLG_CFG6[] = {
	 { "HOST_FLUSH", 10, 13, &umr_bitfield_default },
	 { "LB_TYPE", 4, 6, &umr_bitfield_default },
	 { "P2P_BAR", 7, 9, &umr_bitfield_default },
	 { "SIDE_FLUSH", 14, 17, &umr_bitfield_default },
	 { "WCB_NUM", 0, 3, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_XPB_CLG_CFG7[] = {
	 { "HOST_FLUSH", 10, 13, &umr_bitfield_default },
	 { "LB_TYPE", 4, 6, &umr_bitfield_default },
	 { "P2P_BAR", 7, 9, &umr_bitfield_default },
	 { "SIDE_FLUSH", 14, 17, &umr_bitfield_default },
	 { "WCB_NUM", 0, 3, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_XPB_CLG_CFG8[] = {
	 { "HOST_FLUSH", 10, 13, &umr_bitfield_default },
	 { "LB_TYPE", 4, 6, &umr_bitfield_default },
	 { "P2P_BAR", 7, 9, &umr_bitfield_default },
	 { "SIDE_FLUSH", 14, 17, &umr_bitfield_default },
	 { "WCB_NUM", 0, 3, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_XPB_CLG_CFG9[] = {
	 { "HOST_FLUSH", 10, 13, &umr_bitfield_default },
	 { "LB_TYPE", 4, 6, &umr_bitfield_default },
	 { "P2P_BAR", 7, 9, &umr_bitfield_default },
	 { "SIDE_FLUSH", 14, 17, &umr_bitfield_default },
	 { "WCB_NUM", 0, 3, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_XPB_CLG_CFG10[] = {
	 { "HOST_FLUSH", 10, 13, &umr_bitfield_default },
	 { "LB_TYPE", 4, 6, &umr_bitfield_default },
	 { "P2P_BAR", 7, 9, &umr_bitfield_default },
	 { "SIDE_FLUSH", 14, 17, &umr_bitfield_default },
	 { "WCB_NUM", 0, 3, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_XPB_CLG_CFG11[] = {
	 { "HOST_FLUSH", 10, 13, &umr_bitfield_default },
	 { "LB_TYPE", 4, 6, &umr_bitfield_default },
	 { "P2P_BAR", 7, 9, &umr_bitfield_default },
	 { "SIDE_FLUSH", 14, 17, &umr_bitfield_default },
	 { "WCB_NUM", 0, 3, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_XPB_CLG_CFG12[] = {
	 { "HOST_FLUSH", 10, 13, &umr_bitfield_default },
	 { "LB_TYPE", 4, 6, &umr_bitfield_default },
	 { "P2P_BAR", 7, 9, &umr_bitfield_default },
	 { "SIDE_FLUSH", 14, 17, &umr_bitfield_default },
	 { "WCB_NUM", 0, 3, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_XPB_CLG_CFG13[] = {
	 { "HOST_FLUSH", 10, 13, &umr_bitfield_default },
	 { "LB_TYPE", 4, 6, &umr_bitfield_default },
	 { "P2P_BAR", 7, 9, &umr_bitfield_default },
	 { "SIDE_FLUSH", 14, 17, &umr_bitfield_default },
	 { "WCB_NUM", 0, 3, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_XPB_CLG_CFG14[] = {
	 { "HOST_FLUSH", 10, 13, &umr_bitfield_default },
	 { "LB_TYPE", 4, 6, &umr_bitfield_default },
	 { "P2P_BAR", 7, 9, &umr_bitfield_default },
	 { "SIDE_FLUSH", 14, 17, &umr_bitfield_default },
	 { "WCB_NUM", 0, 3, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_XPB_CLG_CFG15[] = {
	 { "HOST_FLUSH", 10, 13, &umr_bitfield_default },
	 { "LB_TYPE", 4, 6, &umr_bitfield_default },
	 { "P2P_BAR", 7, 9, &umr_bitfield_default },
	 { "SIDE_FLUSH", 14, 17, &umr_bitfield_default },
	 { "WCB_NUM", 0, 3, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_XPB_CLG_CFG16[] = {
	 { "HOST_FLUSH", 10, 13, &umr_bitfield_default },
	 { "LB_TYPE", 4, 6, &umr_bitfield_default },
	 { "P2P_BAR", 7, 9, &umr_bitfield_default },
	 { "SIDE_FLUSH", 14, 17, &umr_bitfield_default },
	 { "WCB_NUM", 0, 3, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_XPB_CLG_CFG17[] = {
	 { "HOST_FLUSH", 10, 13, &umr_bitfield_default },
	 { "LB_TYPE", 4, 6, &umr_bitfield_default },
	 { "P2P_BAR", 7, 9, &umr_bitfield_default },
	 { "SIDE_FLUSH", 14, 17, &umr_bitfield_default },
	 { "WCB_NUM", 0, 3, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_XPB_CLG_CFG18[] = {
	 { "HOST_FLUSH", 10, 13, &umr_bitfield_default },
	 { "LB_TYPE", 4, 6, &umr_bitfield_default },
	 { "P2P_BAR", 7, 9, &umr_bitfield_default },
	 { "SIDE_FLUSH", 14, 17, &umr_bitfield_default },
	 { "WCB_NUM", 0, 3, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_XPB_CLG_CFG19[] = {
	 { "HOST_FLUSH", 10, 13, &umr_bitfield_default },
	 { "LB_TYPE", 4, 6, &umr_bitfield_default },
	 { "P2P_BAR", 7, 9, &umr_bitfield_default },
	 { "SIDE_FLUSH", 14, 17, &umr_bitfield_default },
	 { "WCB_NUM", 0, 3, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_XPB_CLG_EXTRA[] = {
	 { "CMP0", 0, 7, &umr_bitfield_default },
	 { "CMP1", 17, 24, &umr_bitfield_default },
	 { "MSK0", 8, 15, &umr_bitfield_default },
	 { "VLD0", 16, 16, &umr_bitfield_default },
	 { "VLD1", 25, 25, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_XPB_LB_ADDR[] = {
	 { "CMP0", 0, 9, &umr_bitfield_default },
	 { "CMP1", 20, 25, &umr_bitfield_default },
	 { "MASK0", 10, 19, &umr_bitfield_default },
	 { "MASK1", 26, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_XPB_UNC_THRESH_HST[] = {
	 { "CHANGE_PREF", 0, 5, &umr_bitfield_default },
	 { "STRONG_PREF", 6, 11, &umr_bitfield_default },
	 { "USE_UNFULL", 12, 17, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_XPB_UNC_THRESH_SID[] = {
	 { "CHANGE_PREF", 0, 5, &umr_bitfield_default },
	 { "STRONG_PREF", 6, 11, &umr_bitfield_default },
	 { "USE_UNFULL", 12, 17, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_XPB_WCB_STS[] = {
	 { "PBUF_VLD", 0, 15, &umr_bitfield_default },
	 { "WCB_HST_DATA_BUF_CNT", 16, 22, &umr_bitfield_default },
	 { "WCB_SID_DATA_BUF_CNT", 23, 29, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_XPB_WCB_CFG[] = {
	 { "HST_MAX", 16, 17, &umr_bitfield_default },
	 { "SID_MAX", 18, 19, &umr_bitfield_default },
	 { "TIMEOUT", 0, 15, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_XPB_P2P_BAR_CFG[] = {
	 { "ADDR_SIZE", 0, 3, &umr_bitfield_default },
	 { "ATC_TRANSLATED", 12, 12, &umr_bitfield_default },
	 { "COMPRESS_DIS", 8, 8, &umr_bitfield_default },
	 { "RD_EN", 11, 11, &umr_bitfield_default },
	 { "REGBAR_FROM_SYSBAR", 10, 10, &umr_bitfield_default },
	 { "SEND_BAR", 4, 5, &umr_bitfield_default },
	 { "SEND_DIS", 7, 7, &umr_bitfield_default },
	 { "SNOOP", 6, 6, &umr_bitfield_default },
	 { "UPDATE_DIS", 9, 9, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_XPB_P2P_BAR0[] = {
	 { "ADDRESS", 16, 31, &umr_bitfield_default },
	 { "COMPRESS_DIS", 14, 14, &umr_bitfield_default },
	 { "HOST_FLUSH", 0, 3, &umr_bitfield_default },
	 { "MEM_SYS_BAR", 8, 11, &umr_bitfield_default },
	 { "REG_SYS_BAR", 4, 7, &umr_bitfield_default },
	 { "RESERVED", 15, 15, &umr_bitfield_default },
	 { "SEND_DIS", 13, 13, &umr_bitfield_default },
	 { "VALID", 12, 12, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_XPB_P2P_BAR1[] = {
	 { "ADDRESS", 16, 31, &umr_bitfield_default },
	 { "COMPRESS_DIS", 14, 14, &umr_bitfield_default },
	 { "HOST_FLUSH", 0, 3, &umr_bitfield_default },
	 { "MEM_SYS_BAR", 8, 11, &umr_bitfield_default },
	 { "REG_SYS_BAR", 4, 7, &umr_bitfield_default },
	 { "RESERVED", 15, 15, &umr_bitfield_default },
	 { "SEND_DIS", 13, 13, &umr_bitfield_default },
	 { "VALID", 12, 12, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_XPB_P2P_BAR2[] = {
	 { "ADDRESS", 16, 31, &umr_bitfield_default },
	 { "COMPRESS_DIS", 14, 14, &umr_bitfield_default },
	 { "HOST_FLUSH", 0, 3, &umr_bitfield_default },
	 { "MEM_SYS_BAR", 8, 11, &umr_bitfield_default },
	 { "REG_SYS_BAR", 4, 7, &umr_bitfield_default },
	 { "RESERVED", 15, 15, &umr_bitfield_default },
	 { "SEND_DIS", 13, 13, &umr_bitfield_default },
	 { "VALID", 12, 12, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_XPB_P2P_BAR3[] = {
	 { "ADDRESS", 16, 31, &umr_bitfield_default },
	 { "COMPRESS_DIS", 14, 14, &umr_bitfield_default },
	 { "HOST_FLUSH", 0, 3, &umr_bitfield_default },
	 { "MEM_SYS_BAR", 8, 11, &umr_bitfield_default },
	 { "REG_SYS_BAR", 4, 7, &umr_bitfield_default },
	 { "RESERVED", 15, 15, &umr_bitfield_default },
	 { "SEND_DIS", 13, 13, &umr_bitfield_default },
	 { "VALID", 12, 12, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_XPB_P2P_BAR4[] = {
	 { "ADDRESS", 16, 31, &umr_bitfield_default },
	 { "COMPRESS_DIS", 14, 14, &umr_bitfield_default },
	 { "HOST_FLUSH", 0, 3, &umr_bitfield_default },
	 { "MEM_SYS_BAR", 8, 11, &umr_bitfield_default },
	 { "REG_SYS_BAR", 4, 7, &umr_bitfield_default },
	 { "RESERVED", 15, 15, &umr_bitfield_default },
	 { "SEND_DIS", 13, 13, &umr_bitfield_default },
	 { "VALID", 12, 12, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_XPB_P2P_BAR5[] = {
	 { "ADDRESS", 16, 31, &umr_bitfield_default },
	 { "COMPRESS_DIS", 14, 14, &umr_bitfield_default },
	 { "HOST_FLUSH", 0, 3, &umr_bitfield_default },
	 { "MEM_SYS_BAR", 8, 11, &umr_bitfield_default },
	 { "REG_SYS_BAR", 4, 7, &umr_bitfield_default },
	 { "RESERVED", 15, 15, &umr_bitfield_default },
	 { "SEND_DIS", 13, 13, &umr_bitfield_default },
	 { "VALID", 12, 12, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_XPB_P2P_BAR6[] = {
	 { "ADDRESS", 16, 31, &umr_bitfield_default },
	 { "COMPRESS_DIS", 14, 14, &umr_bitfield_default },
	 { "HOST_FLUSH", 0, 3, &umr_bitfield_default },
	 { "MEM_SYS_BAR", 8, 11, &umr_bitfield_default },
	 { "REG_SYS_BAR", 4, 7, &umr_bitfield_default },
	 { "RESERVED", 15, 15, &umr_bitfield_default },
	 { "SEND_DIS", 13, 13, &umr_bitfield_default },
	 { "VALID", 12, 12, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_XPB_P2P_BAR7[] = {
	 { "ADDRESS", 16, 31, &umr_bitfield_default },
	 { "COMPRESS_DIS", 14, 14, &umr_bitfield_default },
	 { "HOST_FLUSH", 0, 3, &umr_bitfield_default },
	 { "MEM_SYS_BAR", 8, 11, &umr_bitfield_default },
	 { "REG_SYS_BAR", 4, 7, &umr_bitfield_default },
	 { "RESERVED", 15, 15, &umr_bitfield_default },
	 { "SEND_DIS", 13, 13, &umr_bitfield_default },
	 { "VALID", 12, 12, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_XPB_P2P_BAR_SETUP[] = {
	 { "ADDRESS", 16, 31, &umr_bitfield_default },
	 { "COMPRESS_DIS", 14, 14, &umr_bitfield_default },
	 { "REG_SYS_BAR", 8, 11, &umr_bitfield_default },
	 { "RESERVED", 15, 15, &umr_bitfield_default },
	 { "SEL", 0, 7, &umr_bitfield_default },
	 { "SEND_DIS", 13, 13, &umr_bitfield_default },
	 { "VALID", 12, 12, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_XPB_P2P_BAR_DEBUG[] = {
	 { "HOST_FLUSH", 8, 11, &umr_bitfield_default },
	 { "MEM_SYS_BAR", 12, 15, &umr_bitfield_default },
	 { "SEL", 0, 7, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_XPB_P2P_BAR_DELTA_ABOVE[] = {
	 { "DELTA", 8, 27, &umr_bitfield_default },
	 { "EN", 0, 7, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_XPB_P2P_BAR_DELTA_BELOW[] = {
	 { "DELTA", 8, 27, &umr_bitfield_default },
	 { "EN", 0, 7, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_XPB_PEER_SYS_BAR0[] = {
	 { "ADDR", 2, 26, &umr_bitfield_default },
	 { "SIDE_OK", 1, 1, &umr_bitfield_default },
	 { "VALID", 0, 0, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_XPB_PEER_SYS_BAR1[] = {
	 { "ADDR", 2, 26, &umr_bitfield_default },
	 { "SIDE_OK", 1, 1, &umr_bitfield_default },
	 { "VALID", 0, 0, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_XPB_PEER_SYS_BAR2[] = {
	 { "ADDR", 2, 26, &umr_bitfield_default },
	 { "SIDE_OK", 1, 1, &umr_bitfield_default },
	 { "VALID", 0, 0, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_XPB_PEER_SYS_BAR3[] = {
	 { "ADDR", 2, 26, &umr_bitfield_default },
	 { "SIDE_OK", 1, 1, &umr_bitfield_default },
	 { "VALID", 0, 0, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_XPB_PEER_SYS_BAR4[] = {
	 { "ADDR", 2, 26, &umr_bitfield_default },
	 { "SIDE_OK", 1, 1, &umr_bitfield_default },
	 { "VALID", 0, 0, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_XPB_PEER_SYS_BAR5[] = {
	 { "ADDR", 2, 26, &umr_bitfield_default },
	 { "SIDE_OK", 1, 1, &umr_bitfield_default },
	 { "VALID", 0, 0, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_XPB_PEER_SYS_BAR6[] = {
	 { "ADDR", 2, 26, &umr_bitfield_default },
	 { "SIDE_OK", 1, 1, &umr_bitfield_default },
	 { "VALID", 0, 0, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_XPB_PEER_SYS_BAR7[] = {
	 { "ADDR", 2, 26, &umr_bitfield_default },
	 { "SIDE_OK", 1, 1, &umr_bitfield_default },
	 { "VALID", 0, 0, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_XPB_PEER_SYS_BAR8[] = {
	 { "ADDR", 2, 26, &umr_bitfield_default },
	 { "SIDE_OK", 1, 1, &umr_bitfield_default },
	 { "VALID", 0, 0, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_XPB_PEER_SYS_BAR9[] = {
	 { "ADDR", 2, 26, &umr_bitfield_default },
	 { "SIDE_OK", 1, 1, &umr_bitfield_default },
	 { "VALID", 0, 0, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_XPB_XDMA_PEER_SYS_BAR0[] = {
	 { "ADDR", 2, 26, &umr_bitfield_default },
	 { "SIDE_OK", 1, 1, &umr_bitfield_default },
	 { "VALID", 0, 0, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_XPB_XDMA_PEER_SYS_BAR1[] = {
	 { "ADDR", 2, 26, &umr_bitfield_default },
	 { "SIDE_OK", 1, 1, &umr_bitfield_default },
	 { "VALID", 0, 0, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_XPB_XDMA_PEER_SYS_BAR2[] = {
	 { "ADDR", 2, 26, &umr_bitfield_default },
	 { "SIDE_OK", 1, 1, &umr_bitfield_default },
	 { "VALID", 0, 0, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_XPB_XDMA_PEER_SYS_BAR3[] = {
	 { "ADDR", 2, 26, &umr_bitfield_default },
	 { "SIDE_OK", 1, 1, &umr_bitfield_default },
	 { "VALID", 0, 0, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_XPB_CLK_GAT[] = {
	 { "ENABLE", 18, 18, &umr_bitfield_default },
	 { "MEM_LS_ENABLE", 19, 19, &umr_bitfield_default },
	 { "OFFDLY", 6, 11, &umr_bitfield_default },
	 { "ONDLY", 0, 5, &umr_bitfield_default },
	 { "RDYDLY", 12, 17, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_XPB_INTF_CFG[] = {
	 { "BIF_MEM_SNOOP_SEL", 25, 25, &umr_bitfield_default },
	 { "BIF_MEM_SNOOP_VAL", 26, 26, &umr_bitfield_default },
	 { "BIF_REG_SNOOP_SEL", 23, 23, &umr_bitfield_default },
	 { "BIF_REG_SNOOP_VAL", 24, 24, &umr_bitfield_default },
	 { "MC_WRRET_ASK", 8, 15, &umr_bitfield_default },
	 { "RPB_WRREQ_CRD", 0, 7, &umr_bitfield_default },
	 { "XSP_ORDERING_SEL", 30, 30, &umr_bitfield_default },
	 { "XSP_ORDERING_VAL", 31, 31, &umr_bitfield_default },
	 { "XSP_REQ_CRD", 16, 22, &umr_bitfield_default },
	 { "XSP_SNOOP_SEL", 27, 28, &umr_bitfield_default },
	 { "XSP_SNOOP_VAL", 29, 29, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_XPB_INTF_STS[] = {
	 { "CNS_BUF_BUSY", 18, 18, &umr_bitfield_default },
	 { "CNS_BUF_FULL", 17, 17, &umr_bitfield_default },
	 { "HOP_ATTR_BUF_FULL", 16, 16, &umr_bitfield_default },
	 { "HOP_DATA_BUF_FULL", 15, 15, &umr_bitfield_default },
	 { "RPB_RDREQ_CRD", 19, 26, &umr_bitfield_default },
	 { "RPB_WRREQ_CRD", 0, 7, &umr_bitfield_default },
	 { "XSP_REQ_CRD", 8, 14, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_XPB_PIPE_STS[] = {
	 { "RET_BUF_FULL", 23, 23, &umr_bitfield_default },
	 { "WCB_ANY_PBUF", 0, 0, &umr_bitfield_default },
	 { "WCB_HST_DATA_BUF_CNT", 1, 7, &umr_bitfield_default },
	 { "WCB_HST_DATA_OBUF_FULL", 21, 21, &umr_bitfield_default },
	 { "WCB_HST_RD_PTR_BUF_FULL", 15, 15, &umr_bitfield_default },
	 { "WCB_HST_REQ_FIFO_FULL", 17, 17, &umr_bitfield_default },
	 { "WCB_HST_REQ_OBUF_FULL", 19, 19, &umr_bitfield_default },
	 { "WCB_SID_DATA_BUF_CNT", 8, 14, &umr_bitfield_default },
	 { "WCB_SID_DATA_OBUF_FULL", 22, 22, &umr_bitfield_default },
	 { "WCB_SID_RD_PTR_BUF_FULL", 16, 16, &umr_bitfield_default },
	 { "WCB_SID_REQ_FIFO_FULL", 18, 18, &umr_bitfield_default },
	 { "WCB_SID_REQ_OBUF_FULL", 20, 20, &umr_bitfield_default },
	 { "XPB_CLK_BUSY_BITS", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_XPB_SUB_CTRL[] = {
	 { "RESET_CGR", 19, 19, &umr_bitfield_default },
	 { "RESET_CNS", 10, 10, &umr_bitfield_default },
	 { "RESET_HOP", 16, 16, &umr_bitfield_default },
	 { "RESET_HST", 15, 15, &umr_bitfield_default },
	 { "RESET_MAP", 13, 13, &umr_bitfield_default },
	 { "RESET_RET", 12, 12, &umr_bitfield_default },
	 { "RESET_RTR", 11, 11, &umr_bitfield_default },
	 { "RESET_SID", 17, 17, &umr_bitfield_default },
	 { "RESET_SRB", 18, 18, &umr_bitfield_default },
	 { "RESET_WCB", 14, 14, &umr_bitfield_default },
	 { "STALL_CNS_RTR_REQ", 1, 1, &umr_bitfield_default },
	 { "STALL_HST_HOP_REQ", 8, 8, &umr_bitfield_default },
	 { "STALL_MAP_WCB_REQ", 4, 4, &umr_bitfield_default },
	 { "STALL_MC_XSP_REQ_SEND", 6, 6, &umr_bitfield_default },
	 { "STALL_RTR_MAP_REQ", 3, 3, &umr_bitfield_default },
	 { "STALL_RTR_RPB_WRREQ", 2, 2, &umr_bitfield_default },
	 { "STALL_WCB_HST_REQ", 7, 7, &umr_bitfield_default },
	 { "STALL_WCB_SID_REQ", 5, 5, &umr_bitfield_default },
	 { "STALL_XPB_RPB_REQ_ATTR", 9, 9, &umr_bitfield_default },
	 { "WRREQ_BYPASS_XPB", 0, 0, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_XPB_MAP_INVERT_FLUSH_NUM_LSB[] = {
	 { "ALTER_FLUSH_NUM", 0, 15, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_XPB_PERF_KNOBS[] = {
	 { "CNS_FIFO_DEPTH", 0, 5, &umr_bitfield_default },
	 { "WCB_HST_FIFO_DEPTH", 6, 11, &umr_bitfield_default },
	 { "WCB_SID_FIFO_DEPTH", 12, 17, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_XPB_STICKY[] = {
	 { "BITS", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_XPB_STICKY_W1C[] = {
	 { "BITS", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_XPB_MISC_CFG[] = {
	 { "FIELDNAME0", 0, 7, &umr_bitfield_default },
	 { "FIELDNAME1", 8, 15, &umr_bitfield_default },
	 { "FIELDNAME2", 16, 23, &umr_bitfield_default },
	 { "FIELDNAME3", 24, 30, &umr_bitfield_default },
	 { "TRIGGERNAME", 31, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_XPB_CLG_CFG20[] = {
	 { "HOST_FLUSH", 10, 13, &umr_bitfield_default },
	 { "LB_TYPE", 4, 6, &umr_bitfield_default },
	 { "P2P_BAR", 7, 9, &umr_bitfield_default },
	 { "SIDE_FLUSH", 14, 17, &umr_bitfield_default },
	 { "WCB_NUM", 0, 3, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_XPB_CLG_CFG21[] = {
	 { "HOST_FLUSH", 10, 13, &umr_bitfield_default },
	 { "LB_TYPE", 4, 6, &umr_bitfield_default },
	 { "P2P_BAR", 7, 9, &umr_bitfield_default },
	 { "SIDE_FLUSH", 14, 17, &umr_bitfield_default },
	 { "WCB_NUM", 0, 3, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_XPB_CLG_CFG22[] = {
	 { "HOST_FLUSH", 10, 13, &umr_bitfield_default },
	 { "LB_TYPE", 4, 6, &umr_bitfield_default },
	 { "P2P_BAR", 7, 9, &umr_bitfield_default },
	 { "SIDE_FLUSH", 14, 17, &umr_bitfield_default },
	 { "WCB_NUM", 0, 3, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_XPB_CLG_CFG23[] = {
	 { "HOST_FLUSH", 10, 13, &umr_bitfield_default },
	 { "LB_TYPE", 4, 6, &umr_bitfield_default },
	 { "P2P_BAR", 7, 9, &umr_bitfield_default },
	 { "SIDE_FLUSH", 14, 17, &umr_bitfield_default },
	 { "WCB_NUM", 0, 3, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_XPB_CLG_CFG24[] = {
	 { "HOST_FLUSH", 10, 13, &umr_bitfield_default },
	 { "LB_TYPE", 4, 6, &umr_bitfield_default },
	 { "P2P_BAR", 7, 9, &umr_bitfield_default },
	 { "SIDE_FLUSH", 14, 17, &umr_bitfield_default },
	 { "WCB_NUM", 0, 3, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_XPB_CLG_CFG25[] = {
	 { "HOST_FLUSH", 10, 13, &umr_bitfield_default },
	 { "LB_TYPE", 4, 6, &umr_bitfield_default },
	 { "P2P_BAR", 7, 9, &umr_bitfield_default },
	 { "SIDE_FLUSH", 14, 17, &umr_bitfield_default },
	 { "WCB_NUM", 0, 3, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_XPB_CLG_CFG26[] = {
	 { "HOST_FLUSH", 10, 13, &umr_bitfield_default },
	 { "LB_TYPE", 4, 6, &umr_bitfield_default },
	 { "P2P_BAR", 7, 9, &umr_bitfield_default },
	 { "SIDE_FLUSH", 14, 17, &umr_bitfield_default },
	 { "WCB_NUM", 0, 3, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_XPB_CLG_CFG27[] = {
	 { "HOST_FLUSH", 10, 13, &umr_bitfield_default },
	 { "LB_TYPE", 4, 6, &umr_bitfield_default },
	 { "P2P_BAR", 7, 9, &umr_bitfield_default },
	 { "SIDE_FLUSH", 14, 17, &umr_bitfield_default },
	 { "WCB_NUM", 0, 3, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_XPB_CLG_CFG28[] = {
	 { "HOST_FLUSH", 10, 13, &umr_bitfield_default },
	 { "LB_TYPE", 4, 6, &umr_bitfield_default },
	 { "P2P_BAR", 7, 9, &umr_bitfield_default },
	 { "SIDE_FLUSH", 14, 17, &umr_bitfield_default },
	 { "WCB_NUM", 0, 3, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_XPB_CLG_CFG29[] = {
	 { "HOST_FLUSH", 10, 13, &umr_bitfield_default },
	 { "LB_TYPE", 4, 6, &umr_bitfield_default },
	 { "P2P_BAR", 7, 9, &umr_bitfield_default },
	 { "SIDE_FLUSH", 14, 17, &umr_bitfield_default },
	 { "WCB_NUM", 0, 3, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_XPB_CLG_CFG30[] = {
	 { "HOST_FLUSH", 10, 13, &umr_bitfield_default },
	 { "LB_TYPE", 4, 6, &umr_bitfield_default },
	 { "P2P_BAR", 7, 9, &umr_bitfield_default },
	 { "SIDE_FLUSH", 14, 17, &umr_bitfield_default },
	 { "WCB_NUM", 0, 3, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_XPB_CLG_CFG31[] = {
	 { "HOST_FLUSH", 10, 13, &umr_bitfield_default },
	 { "LB_TYPE", 4, 6, &umr_bitfield_default },
	 { "P2P_BAR", 7, 9, &umr_bitfield_default },
	 { "SIDE_FLUSH", 14, 17, &umr_bitfield_default },
	 { "WCB_NUM", 0, 3, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_XPB_INTF_CFG2[] = {
	 { "RPB_RDREQ_CRD", 0, 7, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_XPB_CLG_EXTRA_RD[] = {
	 { "CMP0", 0, 7, &umr_bitfield_default },
	 { "CMP1", 17, 24, &umr_bitfield_default },
	 { "MSK0", 8, 15, &umr_bitfield_default },
	 { "VLD0", 16, 16, &umr_bitfield_default },
	 { "VLD1", 25, 25, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_XPB_CLG_CFG32[] = {
	 { "HOST_FLUSH", 10, 13, &umr_bitfield_default },
	 { "LB_TYPE", 4, 6, &umr_bitfield_default },
	 { "P2P_BAR", 7, 9, &umr_bitfield_default },
	 { "SIDE_FLUSH", 14, 17, &umr_bitfield_default },
	 { "WCB_NUM", 0, 3, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_XPB_CLG_CFG33[] = {
	 { "HOST_FLUSH", 10, 13, &umr_bitfield_default },
	 { "LB_TYPE", 4, 6, &umr_bitfield_default },
	 { "P2P_BAR", 7, 9, &umr_bitfield_default },
	 { "SIDE_FLUSH", 14, 17, &umr_bitfield_default },
	 { "WCB_NUM", 0, 3, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_XPB_CLG_CFG34[] = {
	 { "HOST_FLUSH", 10, 13, &umr_bitfield_default },
	 { "LB_TYPE", 4, 6, &umr_bitfield_default },
	 { "P2P_BAR", 7, 9, &umr_bitfield_default },
	 { "SIDE_FLUSH", 14, 17, &umr_bitfield_default },
	 { "WCB_NUM", 0, 3, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_XPB_CLG_CFG35[] = {
	 { "HOST_FLUSH", 10, 13, &umr_bitfield_default },
	 { "LB_TYPE", 4, 6, &umr_bitfield_default },
	 { "P2P_BAR", 7, 9, &umr_bitfield_default },
	 { "SIDE_FLUSH", 14, 17, &umr_bitfield_default },
	 { "WCB_NUM", 0, 3, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_XPB_CLG_CFG36[] = {
	 { "HOST_FLUSH", 10, 13, &umr_bitfield_default },
	 { "LB_TYPE", 4, 6, &umr_bitfield_default },
	 { "P2P_BAR", 7, 9, &umr_bitfield_default },
	 { "SIDE_FLUSH", 14, 17, &umr_bitfield_default },
	 { "WCB_NUM", 0, 3, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_RPB_CONF[] = {
	 { "RPB_RD_PCIE_ORDER", 16, 16, &umr_bitfield_default },
	 { "RPB_WR_PCIE_ORDER", 17, 17, &umr_bitfield_default },
	 { "XPB_PCIE_ORDER", 15, 15, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_RPB_IF_CONF[] = {
	 { "OUTSTANDING_WRRET_ASK", 8, 15, &umr_bitfield_default },
	 { "RPB_BIF_CREDITS", 0, 7, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_RPB_DBG1[] = {
	 { "DEBUG_BITS", 20, 31, &umr_bitfield_default },
	 { "RPB_BIF_OUTSTANDING_RD_32B", 8, 19, &umr_bitfield_default },
	 { "RPB_BIF_OUTSTANDING_RD", 0, 7, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_RPB_EFF_CNTL[] = {
	 { "RD_LAZY_TIMER", 8, 15, &umr_bitfield_default },
	 { "WR_LAZY_TIMER", 0, 7, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_RPB_ARB_CNTL[] = {
	 { "ATC_SWITCH_NUM", 16, 23, &umr_bitfield_default },
	 { "RD_SWITCH_NUM", 8, 15, &umr_bitfield_default },
	 { "WR_SWITCH_NUM", 0, 7, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_RPB_BIF_CNTL[] = {
	 { "ARB_SWITCH_NUM", 0, 7, &umr_bitfield_default },
	 { "XPB_SWITCH_NUM", 8, 15, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_RPB_WR_SWITCH_CNTL[] = {
	 { "QUEUE0_SWITCH_NUM", 0, 7, &umr_bitfield_default },
	 { "QUEUE1_SWITCH_NUM", 8, 15, &umr_bitfield_default },
	 { "QUEUE2_SWITCH_NUM", 16, 23, &umr_bitfield_default },
	 { "QUEUE3_SWITCH_NUM", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_RPB_WR_COMBINE_CNTL[] = {
	 { "WC_ALIGN", 7, 7, &umr_bitfield_default },
	 { "WC_ENABLE", 0, 0, &umr_bitfield_default },
	 { "WC_FLUSH_TIMER", 3, 6, &umr_bitfield_default },
	 { "WC_MAX_PACKET_SIZE", 1, 2, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_RPB_RD_SWITCH_CNTL[] = {
	 { "QUEUE0_SWITCH_NUM", 0, 7, &umr_bitfield_default },
	 { "QUEUE1_SWITCH_NUM", 8, 15, &umr_bitfield_default },
	 { "QUEUE2_SWITCH_NUM", 16, 23, &umr_bitfield_default },
	 { "QUEUE3_SWITCH_NUM", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_RPB_CID_QUEUE_WR[] = {
	 { "CLIENT_ID", 0, 7, &umr_bitfield_default },
	 { "READ_QUEUE", 11, 12, &umr_bitfield_default },
	 { "UPDATE", 13, 13, &umr_bitfield_default },
	 { "UPDATE_MODE", 8, 8, &umr_bitfield_default },
	 { "WRITE_QUEUE", 9, 10, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_RPB_CID_QUEUE_RD[] = {
	 { "CLIENT_ID", 0, 7, &umr_bitfield_default },
	 { "READ_QUEUE", 10, 11, &umr_bitfield_default },
	 { "WRITE_QUEUE", 8, 9, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_RPB_PERF_COUNTER_CNTL[] = {
	 { "CLEAR_ALL_PERF_COUNTERS", 3, 3, &umr_bitfield_default },
	 { "CLEAR_SELECTED_PERF_COUNTER", 2, 2, &umr_bitfield_default },
	 { "ENABLE_PERF_COUNTERS", 5, 8, &umr_bitfield_default },
	 { "PERF_COUNTER_ASSIGN_0", 9, 13, &umr_bitfield_default },
	 { "PERF_COUNTER_ASSIGN_1", 14, 18, &umr_bitfield_default },
	 { "PERF_COUNTER_ASSIGN_2", 19, 23, &umr_bitfield_default },
	 { "PERF_COUNTER_ASSIGN_3", 24, 28, &umr_bitfield_default },
	 { "PERF_COUNTER_SELECT", 0, 1, &umr_bitfield_default },
	 { "STOP_ON_COUNTER_SATURATION", 4, 4, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_RPB_PERF_COUNTER_STATUS[] = {
	 { "PERFORMANCE_COUNTER_VALUE", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_RPB_CID_QUEUE_EX[] = {
	 { "OFFSET", 1, 5, &umr_bitfield_default },
	 { "START", 0, 0, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_RPB_CID_QUEUE_EX_DATA[] = {
	 { "READ_ENTRIES", 16, 31, &umr_bitfield_default },
	 { "WRITE_ENTRIES", 0, 15, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_CITF_XTRA_ENABLE[] = {
	 { "ARB_DBG", 8, 11, &umr_bitfield_default },
	 { "CB1_RD", 0, 0, &umr_bitfield_default },
	 { "CB1_WR", 1, 1, &umr_bitfield_default },
	 { "DB1_RD", 2, 2, &umr_bitfield_default },
	 { "DB1_WR", 3, 3, &umr_bitfield_default },
	 { "TC2_RD", 4, 4, &umr_bitfield_default },
	 { "TC2_WR", 12, 12, &umr_bitfield_default },
};
static struct umr_bitfield mmCC_MC_MAX_CHANNEL[] = {
	 { "NOOFCHAN", 1, 4, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_CG_CONFIG[] = {
	 { "INDEX", 6, 21, &umr_bitfield_default },
	 { "MCDW_WR_ENABLE", 0, 0, &umr_bitfield_default },
	 { "MCDX_WR_ENABLE", 1, 1, &umr_bitfield_default },
	 { "MCDY_WR_ENABLE", 2, 2, &umr_bitfield_default },
	 { "MCDZ_WR_ENABLE", 3, 3, &umr_bitfield_default },
	 { "MC_RD_ENABLE", 4, 5, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_CITF_CNTL[] = {
	 { "EXEMPTPM", 3, 3, &umr_bitfield_default },
	 { "GFX_IDLE_OVERRIDE", 4, 5, &umr_bitfield_default },
	 { "IGNOREPM", 2, 2, &umr_bitfield_default },
	 { "MCD_SRBM_MASK_ENABLE", 6, 6, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_CITF_CREDITS_VM[] = {
	 { "READ_ALL", 0, 5, &umr_bitfield_default },
	 { "WRITE_ALL", 6, 11, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_CITF_CREDITS_ARB_RD[] = {
	 { "HUB_PRI", 25, 25, &umr_bitfield_default },
	 { "LCL_PRI", 24, 24, &umr_bitfield_default },
	 { "READ_HUB", 8, 15, &umr_bitfield_default },
	 { "READ_LCL", 0, 7, &umr_bitfield_default },
	 { "READ_PRI", 16, 23, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_CITF_CREDITS_ARB_WR[] = {
	 { "HUB_PRI", 16, 16, &umr_bitfield_default },
	 { "LCL_PRI", 17, 17, &umr_bitfield_default },
	 { "WRITE_HUB", 8, 15, &umr_bitfield_default },
	 { "WRITE_LCL", 0, 7, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_CITF_DAGB_CNTL[] = {
	 { "CENTER_RD_MAX_BURST", 1, 4, &umr_bitfield_default },
	 { "CENTER_WR_MAX_BURST", 6, 9, &umr_bitfield_default },
	 { "DISABLE_SELF_INIT", 5, 5, &umr_bitfield_default },
	 { "JUMP_AHEAD", 0, 0, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_CITF_INT_CREDITS[] = {
	 { "CNTR_RD_HUB_HP", 18, 23, &umr_bitfield_default },
	 { "CNTR_RD_HUB_LP", 12, 17, &umr_bitfield_default },
	 { "CNTR_RD_LCL", 24, 29, &umr_bitfield_default },
	 { "REMRDRET", 0, 5, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_CITF_RET_MODE[] = {
	 { "INORDER_RD", 0, 0, &umr_bitfield_default },
	 { "INORDER_WR", 1, 1, &umr_bitfield_default },
	 { "LCLPRI_RD", 4, 4, &umr_bitfield_default },
	 { "LCLPRI_WR", 5, 5, &umr_bitfield_default },
	 { "REMPRI_RD", 2, 2, &umr_bitfield_default },
	 { "REMPRI_WR", 3, 3, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_CITF_DAGB_DLY[] = {
	 { "CLI", 16, 20, &umr_bitfield_default },
	 { "DLY", 0, 4, &umr_bitfield_default },
	 { "POS", 24, 28, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_RD_GRP_EXT[] = {
	 { "DBSTEN0", 0, 3, &umr_bitfield_default },
	 { "TC0", 4, 7, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_WR_GRP_EXT[] = {
	 { "DBSTEN0", 0, 3, &umr_bitfield_default },
	 { "TC0", 4, 7, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_CITF_REMREQ[] = {
	 { "CREDITS_ENABLE", 14, 14, &umr_bitfield_default },
	 { "READ_CREDITS", 0, 6, &umr_bitfield_default },
	 { "WRITE_CREDITS", 7, 13, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_WR_TC0[] = {
	 { "BLACKOUT_EXEMPT", 3, 3, &umr_bitfield_default },
	 { "ENABLE", 0, 0, &umr_bitfield_default },
	 { "LAZY_TIMER", 11, 14, &umr_bitfield_default },
	 { "MAX_BURST", 7, 10, &umr_bitfield_default },
	 { "PRESCALE", 1, 2, &umr_bitfield_default },
	 { "STALL_MODE", 4, 5, &umr_bitfield_default },
	 { "STALL_OVERRIDE", 6, 6, &umr_bitfield_default },
	 { "STALL_OVERRIDE_WTM", 15, 15, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_WR_TC1[] = {
	 { "BLACKOUT_EXEMPT", 3, 3, &umr_bitfield_default },
	 { "ENABLE", 0, 0, &umr_bitfield_default },
	 { "LAZY_TIMER", 11, 14, &umr_bitfield_default },
	 { "MAX_BURST", 7, 10, &umr_bitfield_default },
	 { "PRESCALE", 1, 2, &umr_bitfield_default },
	 { "STALL_MODE", 4, 5, &umr_bitfield_default },
	 { "STALL_OVERRIDE", 6, 6, &umr_bitfield_default },
	 { "STALL_OVERRIDE_WTM", 15, 15, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_CITF_INT_CREDITS_WR[] = {
	 { "CNTR_WR_HUB", 0, 5, &umr_bitfield_default },
	 { "CNTR_WR_LCL", 6, 11, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_CITF_WTM_RD_CNTL[] = {
	 { "DISABLE_REMOTE", 24, 24, &umr_bitfield_default },
	 { "GROUP0_DECREMENT", 0, 2, &umr_bitfield_default },
	 { "GROUP1_DECREMENT", 3, 5, &umr_bitfield_default },
	 { "GROUP2_DECREMENT", 6, 8, &umr_bitfield_default },
	 { "GROUP3_DECREMENT", 9, 11, &umr_bitfield_default },
	 { "GROUP4_DECREMENT", 12, 14, &umr_bitfield_default },
	 { "GROUP5_DECREMENT", 15, 17, &umr_bitfield_default },
	 { "GROUP6_DECREMENT", 18, 20, &umr_bitfield_default },
	 { "GROUP7_DECREMENT", 21, 23, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_CITF_WTM_WR_CNTL[] = {
	 { "DISABLE_REMOTE", 24, 24, &umr_bitfield_default },
	 { "GROUP0_DECREMENT", 0, 2, &umr_bitfield_default },
	 { "GROUP1_DECREMENT", 3, 5, &umr_bitfield_default },
	 { "GROUP2_DECREMENT", 6, 8, &umr_bitfield_default },
	 { "GROUP3_DECREMENT", 9, 11, &umr_bitfield_default },
	 { "GROUP4_DECREMENT", 12, 14, &umr_bitfield_default },
	 { "GROUP5_DECREMENT", 15, 17, &umr_bitfield_default },
	 { "GROUP6_DECREMENT", 18, 20, &umr_bitfield_default },
	 { "GROUP7_DECREMENT", 21, 23, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_RD_CB[] = {
	 { "BLACKOUT_EXEMPT", 3, 3, &umr_bitfield_default },
	 { "ENABLE", 0, 0, &umr_bitfield_default },
	 { "LAZY_TIMER", 11, 14, &umr_bitfield_default },
	 { "MAX_BURST", 7, 10, &umr_bitfield_default },
	 { "PRESCALE", 1, 2, &umr_bitfield_default },
	 { "STALL_MODE", 4, 5, &umr_bitfield_default },
	 { "STALL_OVERRIDE", 6, 6, &umr_bitfield_default },
	 { "STALL_OVERRIDE_WTM", 15, 15, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_RD_DB[] = {
	 { "BLACKOUT_EXEMPT", 3, 3, &umr_bitfield_default },
	 { "ENABLE", 0, 0, &umr_bitfield_default },
	 { "LAZY_TIMER", 11, 14, &umr_bitfield_default },
	 { "MAX_BURST", 7, 10, &umr_bitfield_default },
	 { "PRESCALE", 1, 2, &umr_bitfield_default },
	 { "STALL_MODE", 4, 5, &umr_bitfield_default },
	 { "STALL_OVERRIDE", 6, 6, &umr_bitfield_default },
	 { "STALL_OVERRIDE_WTM", 15, 15, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_RD_TC0[] = {
	 { "BLACKOUT_EXEMPT", 3, 3, &umr_bitfield_default },
	 { "ENABLE", 0, 0, &umr_bitfield_default },
	 { "LAZY_TIMER", 11, 14, &umr_bitfield_default },
	 { "MAX_BURST", 7, 10, &umr_bitfield_default },
	 { "PRESCALE", 1, 2, &umr_bitfield_default },
	 { "STALL_MODE", 4, 5, &umr_bitfield_default },
	 { "STALL_OVERRIDE", 6, 6, &umr_bitfield_default },
	 { "STALL_OVERRIDE_WTM", 15, 15, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_RD_TC1[] = {
	 { "BLACKOUT_EXEMPT", 3, 3, &umr_bitfield_default },
	 { "ENABLE", 0, 0, &umr_bitfield_default },
	 { "LAZY_TIMER", 11, 14, &umr_bitfield_default },
	 { "MAX_BURST", 7, 10, &umr_bitfield_default },
	 { "PRESCALE", 1, 2, &umr_bitfield_default },
	 { "STALL_MODE", 4, 5, &umr_bitfield_default },
	 { "STALL_OVERRIDE", 6, 6, &umr_bitfield_default },
	 { "STALL_OVERRIDE_WTM", 15, 15, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_RD_HUB[] = {
	 { "BLACKOUT_EXEMPT", 3, 3, &umr_bitfield_default },
	 { "ENABLE", 0, 0, &umr_bitfield_default },
	 { "LAZY_TIMER", 11, 14, &umr_bitfield_default },
	 { "MAX_BURST", 7, 10, &umr_bitfield_default },
	 { "PRESCALE", 1, 2, &umr_bitfield_default },
	 { "STALL_MODE", 4, 5, &umr_bitfield_default },
	 { "STALL_OVERRIDE", 6, 6, &umr_bitfield_default },
	 { "STALL_OVERRIDE_WTM", 15, 15, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_WR_CB[] = {
	 { "BLACKOUT_EXEMPT", 3, 3, &umr_bitfield_default },
	 { "ENABLE", 0, 0, &umr_bitfield_default },
	 { "LAZY_TIMER", 11, 14, &umr_bitfield_default },
	 { "MAX_BURST", 7, 10, &umr_bitfield_default },
	 { "PRESCALE", 1, 2, &umr_bitfield_default },
	 { "STALL_MODE", 4, 5, &umr_bitfield_default },
	 { "STALL_OVERRIDE", 6, 6, &umr_bitfield_default },
	 { "STALL_OVERRIDE_WTM", 15, 15, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_WR_DB[] = {
	 { "BLACKOUT_EXEMPT", 3, 3, &umr_bitfield_default },
	 { "ENABLE", 0, 0, &umr_bitfield_default },
	 { "LAZY_TIMER", 11, 14, &umr_bitfield_default },
	 { "MAX_BURST", 7, 10, &umr_bitfield_default },
	 { "PRESCALE", 1, 2, &umr_bitfield_default },
	 { "STALL_MODE", 4, 5, &umr_bitfield_default },
	 { "STALL_OVERRIDE", 6, 6, &umr_bitfield_default },
	 { "STALL_OVERRIDE_WTM", 15, 15, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_WR_HUB[] = {
	 { "BLACKOUT_EXEMPT", 3, 3, &umr_bitfield_default },
	 { "ENABLE", 0, 0, &umr_bitfield_default },
	 { "LAZY_TIMER", 11, 14, &umr_bitfield_default },
	 { "MAX_BURST", 7, 10, &umr_bitfield_default },
	 { "PRESCALE", 1, 2, &umr_bitfield_default },
	 { "STALL_MODE", 4, 5, &umr_bitfield_default },
	 { "STALL_OVERRIDE", 6, 6, &umr_bitfield_default },
	 { "STALL_OVERRIDE_WTM", 15, 15, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_CITF_CREDITS_XBAR[] = {
	 { "READ_LCL", 0, 7, &umr_bitfield_default },
	 { "WRITE_LCL", 8, 15, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_RD_GRP_LCL[] = {
	 { "CB0", 12, 15, &umr_bitfield_default },
	 { "CBCMASK0", 16, 19, &umr_bitfield_default },
	 { "CBFMASK0", 20, 23, &umr_bitfield_default },
	 { "DB0", 24, 27, &umr_bitfield_default },
	 { "DBHTILE0", 28, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_WR_GRP_LCL[] = {
	 { "CB0", 0, 3, &umr_bitfield_default },
	 { "CBCMASK0", 4, 7, &umr_bitfield_default },
	 { "CBFMASK0", 8, 11, &umr_bitfield_default },
	 { "CBIMMED0", 28, 31, &umr_bitfield_default },
	 { "DB0", 12, 15, &umr_bitfield_default },
	 { "DBHTILE0", 16, 19, &umr_bitfield_default },
	 { "SX0", 20, 23, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_CITF_PERF_MON_CNTL2[] = {
	 { "CID", 0, 8, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_CITF_PERF_MON_RSLT2[] = {
	 { "CB_RD_BUSY", 6, 6, &umr_bitfield_default },
	 { "CB_WR_BUSY", 12, 12, &umr_bitfield_default },
	 { "DB_RD_BUSY", 7, 7, &umr_bitfield_default },
	 { "DB_WR_BUSY", 13, 13, &umr_bitfield_default },
	 { "SX_WR_BUSY", 14, 14, &umr_bitfield_default },
	 { "TC0_RD_BUSY", 8, 8, &umr_bitfield_default },
	 { "TC0_WR_BUSY", 16, 16, &umr_bitfield_default },
	 { "TC1_RD_BUSY", 10, 10, &umr_bitfield_default },
	 { "TC1_WR_BUSY", 17, 17, &umr_bitfield_default },
	 { "TC2_RD_BUSY", 15, 15, &umr_bitfield_default },
	 { "TC2_WR_BUSY", 18, 18, &umr_bitfield_default },
	 { "VC0_RD_BUSY", 9, 9, &umr_bitfield_default },
	 { "VC1_RD_BUSY", 11, 11, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_CITF_MISC_RD_CG[] = {
	 { "ENABLE", 18, 18, &umr_bitfield_default },
	 { "MEM_LS_ENABLE", 19, 19, &umr_bitfield_default },
	 { "OFFDLY", 6, 11, &umr_bitfield_default },
	 { "ONDLY", 0, 5, &umr_bitfield_default },
	 { "RDYDLY", 12, 17, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_CITF_MISC_WR_CG[] = {
	 { "ENABLE", 18, 18, &umr_bitfield_default },
	 { "MEM_LS_ENABLE", 19, 19, &umr_bitfield_default },
	 { "OFFDLY", 6, 11, &umr_bitfield_default },
	 { "ONDLY", 0, 5, &umr_bitfield_default },
	 { "RDYDLY", 12, 17, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_CITF_MISC_VM_CG[] = {
	 { "ENABLE", 18, 18, &umr_bitfield_default },
	 { "MEM_LS_ENABLE", 19, 19, &umr_bitfield_default },
	 { "OFFDLY", 6, 11, &umr_bitfield_default },
	 { "ONDLY", 0, 5, &umr_bitfield_default },
	 { "RDYDLY", 12, 17, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_VM_MD_L1_TLB0_DEBUG[] = {
	 { "EFFECTIVE_L1_QUEUE_SIZE", 12, 14, &umr_bitfield_default },
	 { "EFFECTIVE_L1_TLB_SIZE", 9, 11, &umr_bitfield_default },
	 { "INVALIDATE_L1_TLB", 0, 0, &umr_bitfield_default },
	 { "L1_TLB_DEBUG", 15, 18, &umr_bitfield_default },
	 { "SEND_FREE_AT_RTN", 8, 8, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_VM_MD_L1_TLB1_DEBUG[] = {
	 { "EFFECTIVE_L1_QUEUE_SIZE", 12, 14, &umr_bitfield_default },
	 { "EFFECTIVE_L1_TLB_SIZE", 9, 11, &umr_bitfield_default },
	 { "INVALIDATE_L1_TLB", 0, 0, &umr_bitfield_default },
	 { "L1_TLB_DEBUG", 15, 18, &umr_bitfield_default },
	 { "SEND_FREE_AT_RTN", 8, 8, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_VM_MD_L1_TLB2_DEBUG[] = {
	 { "EFFECTIVE_L1_QUEUE_SIZE", 12, 14, &umr_bitfield_default },
	 { "EFFECTIVE_L1_TLB_SIZE", 9, 11, &umr_bitfield_default },
	 { "INVALIDATE_L1_TLB", 0, 0, &umr_bitfield_default },
	 { "L1_TLB_DEBUG", 15, 18, &umr_bitfield_default },
	 { "SEND_FREE_AT_RTN", 8, 8, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_VM_MD_L1_TLB0_STATUS[] = {
	 { "BUSY", 0, 0, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_VM_MD_L1_TLB1_STATUS[] = {
	 { "BUSY", 0, 0, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_VM_MD_L1_TLB2_STATUS[] = {
	 { "BUSY", 0, 0, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_VM_MD_L2ARBITER_L2_CREDITS[] = {
	 { "L2_IF_CREDITS", 0, 5, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_VM_MD_L1_TLB3_DEBUG[] = {
	 { "EFFECTIVE_L1_QUEUE_SIZE", 12, 14, &umr_bitfield_default },
	 { "EFFECTIVE_L1_TLB_SIZE", 9, 11, &umr_bitfield_default },
	 { "INVALIDATE_L1_TLB", 0, 0, &umr_bitfield_default },
	 { "L1_TLB_DEBUG", 15, 18, &umr_bitfield_default },
	 { "SEND_FREE_AT_RTN", 8, 8, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_VM_MD_L1_TLB3_STATUS[] = {
	 { "BUSY", 0, 0, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_ARB_FED_CNTL[] = {
	 { "KEEP_POISON_IN_PAGE", 4, 4, &umr_bitfield_default },
	 { "MODE", 0, 1, &umr_bitfield_default },
	 { "WR_ERR", 2, 3, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_ARB_GECC2_STATUS[] = {
	 { "CORR_CLEAR0", 8, 8, &umr_bitfield_default },
	 { "CORR_CLEAR1", 12, 12, &umr_bitfield_default },
	 { "CORR_STS0", 0, 0, &umr_bitfield_default },
	 { "CORR_STS1", 4, 4, &umr_bitfield_default },
	 { "FED_CLEAR0", 10, 10, &umr_bitfield_default },
	 { "FED_CLEAR1", 14, 14, &umr_bitfield_default },
	 { "FED_STS0", 2, 2, &umr_bitfield_default },
	 { "FED_STS1", 6, 6, &umr_bitfield_default },
	 { "RSVD0", 3, 3, &umr_bitfield_default },
	 { "RSVD1", 7, 7, &umr_bitfield_default },
	 { "RSVD2", 11, 11, &umr_bitfield_default },
	 { "UNCORR_CLEAR0", 9, 9, &umr_bitfield_default },
	 { "UNCORR_CLEAR1", 13, 13, &umr_bitfield_default },
	 { "UNCORR_STS0", 1, 1, &umr_bitfield_default },
	 { "UNCORR_STS1", 5, 5, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_ARB_GECC2_MISC[] = {
	 { "STREAK_BREAK", 0, 3, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_ARB_GECC2_DEBUG[] = {
	 { "DATA_FIELD", 3, 4, &umr_bitfield_default },
	 { "DIRECTION", 2, 2, &umr_bitfield_default },
	 { "NUM_ERR_BITS", 0, 1, &umr_bitfield_default },
	 { "SW_INJECTION", 5, 5, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_ARB_GECC2_DEBUG2[] = {
	 { "ERR0_START", 8, 15, &umr_bitfield_default },
	 { "ERR1_START", 16, 23, &umr_bitfield_default },
	 { "ERR2_START", 24, 31, &umr_bitfield_default },
	 { "PERIOD", 0, 7, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_ARB_GECC2[] = {
	 { "CLOSE_BANK_RMW", 14, 14, &umr_bitfield_default },
	 { "COLFIFO_WATER", 15, 20, &umr_bitfield_default },
	 { "ECC_MODE", 1, 2, &umr_bitfield_default },
	 { "ENABLE", 0, 0, &umr_bitfield_default },
	 { "EXOR_BANK_SEL", 5, 6, &umr_bitfield_default },
	 { "NO_GECC_CLI", 7, 10, &umr_bitfield_default },
	 { "PAGE_BIT0", 3, 4, &umr_bitfield_default },
	 { "READ_ERR", 11, 13, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_ARB_GECC2_CLI[] = {
	 { "NO_GECC_CLI0", 0, 7, &umr_bitfield_default },
	 { "NO_GECC_CLI1", 8, 15, &umr_bitfield_default },
	 { "NO_GECC_CLI2", 16, 23, &umr_bitfield_default },
	 { "NO_GECC_CLI3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_ARB_WCDR_2[] = {
	 { "DEBUG_0", 9, 9, &umr_bitfield_default },
	 { "DEBUG_1", 10, 10, &umr_bitfield_default },
	 { "DEBUG_2", 11, 11, &umr_bitfield_default },
	 { "DEBUG_3", 12, 12, &umr_bitfield_default },
	 { "DEBUG_4", 13, 13, &umr_bitfield_default },
	 { "DEBUG_5", 14, 14, &umr_bitfield_default },
	 { "WPRE_INC_STEP", 0, 3, &umr_bitfield_default },
	 { "WPRE_MIN_THRESHOLD", 4, 8, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_ARB_RTT_DATA[] = {
	 { "PATTERN", 0, 7, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_ARB_RTT_CNTL0[] = {
	 { "BREAK_ON_HARSH", 8, 8, &umr_bitfield_default },
	 { "BREAK_ON_URGENTRD", 9, 9, &umr_bitfield_default },
	 { "BREAK_ON_URGENTWR", 10, 10, &umr_bitfield_default },
	 { "DATA_CNTL", 24, 24, &umr_bitfield_default },
	 { "DEBUG_RSV_0", 15, 15, &umr_bitfield_default },
	 { "DEBUG_RSV_1", 16, 16, &umr_bitfield_default },
	 { "DEBUG_RSV_2", 17, 17, &umr_bitfield_default },
	 { "DEBUG_RSV_3", 18, 18, &umr_bitfield_default },
	 { "DEBUG_RSV_4", 19, 19, &umr_bitfield_default },
	 { "DEBUG_RSV_5", 20, 20, &umr_bitfield_default },
	 { "DEBUG_RSV_6", 21, 21, &umr_bitfield_default },
	 { "DEBUG_RSV_7", 22, 22, &umr_bitfield_default },
	 { "DEBUG_RSV_8", 23, 23, &umr_bitfield_default },
	 { "ENABLE", 0, 0, &umr_bitfield_default },
	 { "FLUSH_ON_ENTER", 4, 4, &umr_bitfield_default },
	 { "HARSH_START", 5, 5, &umr_bitfield_default },
	 { "NEIGHBOR_BIT", 25, 25, &umr_bitfield_default },
	 { "START_IDLE", 1, 1, &umr_bitfield_default },
	 { "START_R2W", 2, 3, &umr_bitfield_default },
	 { "START_R2W_RFSH", 14, 14, &umr_bitfield_default },
	 { "TPS_HARSH_PRIORITY", 6, 6, &umr_bitfield_default },
	 { "TRAIN_PERIOD", 11, 13, &umr_bitfield_default },
	 { "TWRT_HARSH_PRIORITY", 7, 7, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_ARB_RTT_CNTL1[] = {
	 { "WINDOW_DEC_THRESHOLD", 13, 19, &umr_bitfield_default },
	 { "WINDOW_INC_THRESHOLD", 6, 12, &umr_bitfield_default },
	 { "WINDOW_SIZE", 0, 4, &umr_bitfield_default },
	 { "WINDOW_SIZE_MAX", 20, 24, &umr_bitfield_default },
	 { "WINDOW_SIZE_MIN", 25, 29, &umr_bitfield_default },
	 { "WINDOW_UPDATE_COUNT", 30, 31, &umr_bitfield_default },
	 { "WINDOW_UPDATE", 5, 5, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_ARB_RTT_CNTL2[] = {
	 { "FILTER_CNTL", 13, 13, &umr_bitfield_default },
	 { "PHASE_ADJUST_SIZE", 12, 12, &umr_bitfield_default },
	 { "PHASE_ADJUST_THRESHOLD", 6, 11, &umr_bitfield_default },
	 { "SAMPLE_CNT", 0, 5, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_ARB_RTT_DEBUG[] = {
	 { "DEBUG_BYTE_CH0", 0, 1, &umr_bitfield_default },
	 { "DEBUG_BYTE_CH1", 2, 3, &umr_bitfield_default },
	 { "SHIFTED_PHASE_CH0", 4, 11, &umr_bitfield_default },
	 { "SHIFTED_PHASE_CH1", 17, 24, &umr_bitfield_default },
	 { "WINDOW_SIZE_CH0", 12, 16, &umr_bitfield_default },
	 { "WINDOW_SIZE_CH1", 25, 29, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_ARB_CAC_CNTL[] = {
	 { "ALLOW_OVERFLOW", 13, 13, &umr_bitfield_default },
	 { "ENABLE", 0, 0, &umr_bitfield_default },
	 { "READ_WEIGHT", 1, 6, &umr_bitfield_default },
	 { "WRITE_WEIGHT", 7, 12, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_ARB_MISC2[] = {
	 { "ARB_DEBUG29", 29, 29, &umr_bitfield_default },
	 { "GECC", 18, 18, &umr_bitfield_default },
	 { "GECC_RST", 19, 19, &umr_bitfield_default },
	 { "GECC_STATUS", 20, 20, &umr_bitfield_default },
	 { "POP_IDLE_REPLAY", 11, 11, &umr_bitfield_default },
	 { "RDRET_NO_BP", 13, 13, &umr_bitfield_default },
	 { "RDRET_NO_REORDERING", 12, 12, &umr_bitfield_default },
	 { "RDRET_SEQ_SKID", 14, 17, &umr_bitfield_default },
	 { "REPLAY_DEBUG", 28, 28, &umr_bitfield_default },
	 { "SEQ_RDY_POP_IDLE", 30, 30, &umr_bitfield_default },
	 { "TAGFIFO_THRESHOLD", 21, 24, &umr_bitfield_default },
	 { "TCCDL4_BANKBIT3_XOR_COLBIT4", 6, 6, &umr_bitfield_default },
	 { "TCCDL4_BANKBIT3_XOR_COLBIT5", 7, 7, &umr_bitfield_default },
	 { "TCCDL4_BANKBIT3_XOR_COLBIT6", 8, 8, &umr_bitfield_default },
	 { "TCCDL4_BANKBIT3_XOR_COLBIT7", 9, 9, &umr_bitfield_default },
	 { "TCCDL4_BANKBIT3_XOR_COLBIT8", 10, 10, &umr_bitfield_default },
	 { "TCCDL4_BANKBIT3_XOR_ENABLE", 5, 5, &umr_bitfield_default },
	 { "TCCDL4_REPLAY_EOB", 31, 31, &umr_bitfield_default },
	 { "WCDR_REPLAY_MASKCNT", 25, 27, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_ARB_MISC[] = {
	 { "CALI_ENABLE", 20, 20, &umr_bitfield_default },
	 { "CALI_RATES", 21, 22, &umr_bitfield_default },
	 { "CHAN_COUPLE", 3, 10, &umr_bitfield_default },
	 { "DISPURG_NOSW2WR", 24, 24, &umr_bitfield_default },
	 { "DISPURG_STALL", 25, 25, &umr_bitfield_default },
	 { "DISPURG_THROTTLE", 26, 29, &umr_bitfield_default },
	 { "DISPURGVLD_NOWRT", 23, 23, &umr_bitfield_default },
	 { "HARSHNESS", 11, 18, &umr_bitfield_default },
	 { "IDLE_RFSH", 1, 1, &umr_bitfield_default },
	 { "SMART_RDWR_SW", 19, 19, &umr_bitfield_default },
	 { "STICKY_RFSH", 0, 0, &umr_bitfield_default },
	 { "STUTTER_RFSH", 2, 2, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_ARB_BANKMAP[] = {
	 { "BANK0", 0, 3, &umr_bitfield_default },
	 { "BANK1", 4, 7, &umr_bitfield_default },
	 { "BANK2", 8, 11, &umr_bitfield_default },
	 { "BANK3", 12, 15, &umr_bitfield_default },
	 { "RANK", 16, 19, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_ARB_RAMCFG[] = {
	 { "CHANSIZE", 8, 8, &umr_bitfield_default },
	 { "NOOFBANK", 0, 1, &umr_bitfield_default },
	 { "NOOFCOLS", 6, 7, &umr_bitfield_default },
	 { "NOOFGROUPS", 12, 12, &umr_bitfield_default },
	 { "NOOFRANKS", 2, 2, &umr_bitfield_default },
	 { "NOOFROWS", 3, 5, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_ARB_POP[] = {
	 { "ALLOW_EOB_BY_WRRET_STALL", 19, 19, &umr_bitfield_default },
	 { "ENABLE_ARB", 0, 0, &umr_bitfield_default },
	 { "ENABLE_TWO_PAGE", 18, 18, &umr_bitfield_default },
	 { "POP_DEPTH", 2, 5, &umr_bitfield_default },
	 { "QUICK_STOP", 17, 17, &umr_bitfield_default },
	 { "SKID_DEPTH", 12, 14, &umr_bitfield_default },
	 { "SPEC_OPEN", 1, 1, &umr_bitfield_default },
	 { "WAIT_AFTER_RFSH", 15, 16, &umr_bitfield_default },
	 { "WRDATAINDEX_DEPTH", 6, 11, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_ARB_MINCLKS[] = {
	 { "ARB_RW_SWITCH", 16, 16, &umr_bitfield_default },
	 { "READ_CLKS", 0, 7, &umr_bitfield_default },
	 { "WRITE_CLKS", 8, 15, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_ARB_SQM_CNTL[] = {
	 { "DYN_SQM_ENABLE", 8, 8, &umr_bitfield_default },
	 { "MIN_PENAL", 0, 7, &umr_bitfield_default },
	 { "RATIO_DEBUG", 24, 31, &umr_bitfield_default },
	 { "RATIO", 16, 23, &umr_bitfield_default },
	 { "SQM_RESERVE", 9, 15, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_ARB_ADDR_HASH[] = {
	 { "BANK_XOR_ENABLE", 0, 3, &umr_bitfield_default },
	 { "COL_XOR", 4, 11, &umr_bitfield_default },
	 { "ROW_XOR", 12, 27, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_ARB_DRAM_TIMING[] = {
	 { "ACTRD", 0, 7, &umr_bitfield_default },
	 { "ACTWR", 8, 15, &umr_bitfield_default },
	 { "RASMACTRD", 16, 23, &umr_bitfield_default },
	 { "RASMACTWR", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_ARB_DRAM_TIMING2[] = {
	 { "BUS_TURN", 24, 28, &umr_bitfield_default },
	 { "RAS2RAS", 0, 7, &umr_bitfield_default },
	 { "RP", 8, 15, &umr_bitfield_default },
	 { "WRPLUSRP", 16, 23, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_ARB_WTM_CNTL_RD[] = {
	 { "ALLOW_STUTTER_GRP0", 3, 3, &umr_bitfield_default },
	 { "ALLOW_STUTTER_GRP1", 4, 4, &umr_bitfield_default },
	 { "ALLOW_STUTTER_GRP2", 5, 5, &umr_bitfield_default },
	 { "ALLOW_STUTTER_GRP3", 6, 6, &umr_bitfield_default },
	 { "ALLOW_STUTTER_GRP4", 7, 7, &umr_bitfield_default },
	 { "ALLOW_STUTTER_GRP5", 8, 8, &umr_bitfield_default },
	 { "ALLOW_STUTTER_GRP6", 9, 9, &umr_bitfield_default },
	 { "ALLOW_STUTTER_GRP7", 10, 10, &umr_bitfield_default },
	 { "HARSH_PRI", 2, 2, &umr_bitfield_default },
	 { "WTMODE", 0, 1, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_ARB_WTM_CNTL_WR[] = {
	 { "ALLOW_STUTTER_GRP0", 3, 3, &umr_bitfield_default },
	 { "ALLOW_STUTTER_GRP1", 4, 4, &umr_bitfield_default },
	 { "ALLOW_STUTTER_GRP2", 5, 5, &umr_bitfield_default },
	 { "ALLOW_STUTTER_GRP3", 6, 6, &umr_bitfield_default },
	 { "ALLOW_STUTTER_GRP4", 7, 7, &umr_bitfield_default },
	 { "ALLOW_STUTTER_GRP5", 8, 8, &umr_bitfield_default },
	 { "ALLOW_STUTTER_GRP6", 9, 9, &umr_bitfield_default },
	 { "ALLOW_STUTTER_GRP7", 10, 10, &umr_bitfield_default },
	 { "HARSH_PRI", 2, 2, &umr_bitfield_default },
	 { "WTMODE", 0, 1, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_ARB_WTM_GRPWT_RD[] = {
	 { "GRP0", 0, 1, &umr_bitfield_default },
	 { "GRP1", 2, 3, &umr_bitfield_default },
	 { "GRP2", 4, 5, &umr_bitfield_default },
	 { "GRP3", 6, 7, &umr_bitfield_default },
	 { "GRP4", 8, 9, &umr_bitfield_default },
	 { "GRP5", 10, 11, &umr_bitfield_default },
	 { "GRP6", 12, 13, &umr_bitfield_default },
	 { "GRP7", 14, 15, &umr_bitfield_default },
	 { "GRP_EXT", 16, 23, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_ARB_WTM_GRPWT_WR[] = {
	 { "GRP0", 0, 1, &umr_bitfield_default },
	 { "GRP1", 2, 3, &umr_bitfield_default },
	 { "GRP2", 4, 5, &umr_bitfield_default },
	 { "GRP3", 6, 7, &umr_bitfield_default },
	 { "GRP4", 8, 9, &umr_bitfield_default },
	 { "GRP5", 10, 11, &umr_bitfield_default },
	 { "GRP6", 12, 13, &umr_bitfield_default },
	 { "GRP7", 14, 15, &umr_bitfield_default },
	 { "GRP_EXT", 16, 23, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_ARB_TM_CNTL_RD[] = {
	 { "BANK_SELECT", 1, 2, &umr_bitfield_default },
	 { "GROUPBY_RANK", 0, 0, &umr_bitfield_default },
	 { "MATCH_BANK", 4, 4, &umr_bitfield_default },
	 { "MATCH_RANK", 3, 3, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_ARB_TM_CNTL_WR[] = {
	 { "BANK_SELECT", 1, 2, &umr_bitfield_default },
	 { "GROUPBY_RANK", 0, 0, &umr_bitfield_default },
	 { "MATCH_BANK", 4, 4, &umr_bitfield_default },
	 { "MATCH_RANK", 3, 3, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_ARB_LAZY0_RD[] = {
	 { "GROUP0", 0, 7, &umr_bitfield_default },
	 { "GROUP1", 8, 15, &umr_bitfield_default },
	 { "GROUP2", 16, 23, &umr_bitfield_default },
	 { "GROUP3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_ARB_LAZY0_WR[] = {
	 { "GROUP0", 0, 7, &umr_bitfield_default },
	 { "GROUP1", 8, 15, &umr_bitfield_default },
	 { "GROUP2", 16, 23, &umr_bitfield_default },
	 { "GROUP3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_ARB_LAZY1_RD[] = {
	 { "GROUP4", 0, 7, &umr_bitfield_default },
	 { "GROUP5", 8, 15, &umr_bitfield_default },
	 { "GROUP6", 16, 23, &umr_bitfield_default },
	 { "GROUP7", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_ARB_LAZY1_WR[] = {
	 { "GROUP4", 0, 7, &umr_bitfield_default },
	 { "GROUP5", 8, 15, &umr_bitfield_default },
	 { "GROUP6", 16, 23, &umr_bitfield_default },
	 { "GROUP7", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_ARB_AGE_RD[] = {
	 { "DIVIDE_GROUP0", 24, 24, &umr_bitfield_default },
	 { "DIVIDE_GROUP1", 25, 25, &umr_bitfield_default },
	 { "DIVIDE_GROUP2", 26, 26, &umr_bitfield_default },
	 { "DIVIDE_GROUP3", 27, 27, &umr_bitfield_default },
	 { "DIVIDE_GROUP4", 28, 28, &umr_bitfield_default },
	 { "DIVIDE_GROUP5", 29, 29, &umr_bitfield_default },
	 { "DIVIDE_GROUP6", 30, 30, &umr_bitfield_default },
	 { "DIVIDE_GROUP7", 31, 31, &umr_bitfield_default },
	 { "ENABLE_GROUP0", 16, 16, &umr_bitfield_default },
	 { "ENABLE_GROUP1", 17, 17, &umr_bitfield_default },
	 { "ENABLE_GROUP2", 18, 18, &umr_bitfield_default },
	 { "ENABLE_GROUP3", 19, 19, &umr_bitfield_default },
	 { "ENABLE_GROUP4", 20, 20, &umr_bitfield_default },
	 { "ENABLE_GROUP5", 21, 21, &umr_bitfield_default },
	 { "ENABLE_GROUP6", 22, 22, &umr_bitfield_default },
	 { "ENABLE_GROUP7", 23, 23, &umr_bitfield_default },
	 { "RATE_GROUP0", 0, 1, &umr_bitfield_default },
	 { "RATE_GROUP1", 2, 3, &umr_bitfield_default },
	 { "RATE_GROUP2", 4, 5, &umr_bitfield_default },
	 { "RATE_GROUP3", 6, 7, &umr_bitfield_default },
	 { "RATE_GROUP4", 8, 9, &umr_bitfield_default },
	 { "RATE_GROUP5", 10, 11, &umr_bitfield_default },
	 { "RATE_GROUP6", 12, 13, &umr_bitfield_default },
	 { "RATE_GROUP7", 14, 15, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_ARB_AGE_WR[] = {
	 { "DIVIDE_GROUP0", 24, 24, &umr_bitfield_default },
	 { "DIVIDE_GROUP1", 25, 25, &umr_bitfield_default },
	 { "DIVIDE_GROUP2", 26, 26, &umr_bitfield_default },
	 { "DIVIDE_GROUP3", 27, 27, &umr_bitfield_default },
	 { "DIVIDE_GROUP4", 28, 28, &umr_bitfield_default },
	 { "DIVIDE_GROUP5", 29, 29, &umr_bitfield_default },
	 { "DIVIDE_GROUP6", 30, 30, &umr_bitfield_default },
	 { "DIVIDE_GROUP7", 31, 31, &umr_bitfield_default },
	 { "ENABLE_GROUP0", 16, 16, &umr_bitfield_default },
	 { "ENABLE_GROUP1", 17, 17, &umr_bitfield_default },
	 { "ENABLE_GROUP2", 18, 18, &umr_bitfield_default },
	 { "ENABLE_GROUP3", 19, 19, &umr_bitfield_default },
	 { "ENABLE_GROUP4", 20, 20, &umr_bitfield_default },
	 { "ENABLE_GROUP5", 21, 21, &umr_bitfield_default },
	 { "ENABLE_GROUP6", 22, 22, &umr_bitfield_default },
	 { "ENABLE_GROUP7", 23, 23, &umr_bitfield_default },
	 { "RATE_GROUP0", 0, 1, &umr_bitfield_default },
	 { "RATE_GROUP1", 2, 3, &umr_bitfield_default },
	 { "RATE_GROUP2", 4, 5, &umr_bitfield_default },
	 { "RATE_GROUP3", 6, 7, &umr_bitfield_default },
	 { "RATE_GROUP4", 8, 9, &umr_bitfield_default },
	 { "RATE_GROUP5", 10, 11, &umr_bitfield_default },
	 { "RATE_GROUP6", 12, 13, &umr_bitfield_default },
	 { "RATE_GROUP7", 14, 15, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_ARB_RFSH_CNTL[] = {
	 { "ACCUM", 11, 11, &umr_bitfield_default },
	 { "ENABLE", 0, 0, &umr_bitfield_default },
	 { "URG0", 1, 5, &umr_bitfield_default },
	 { "URG1", 6, 10, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_ARB_RFSH_RATE[] = {
	 { "POWERMODE0", 0, 7, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_ARB_PM_CNTL[] = {
	 { "BLKOUT_ON_D1", 5, 5, &umr_bitfield_default },
	 { "IDLE_CNT", 20, 23, &umr_bitfield_default },
	 { "IDLE_ON_D1", 6, 6, &umr_bitfield_default },
	 { "IDLE_ON_D2", 18, 18, &umr_bitfield_default },
	 { "IDLE_ON_D3", 19, 19, &umr_bitfield_default },
	 { "OVERRIDE_CGSTATE", 0, 1, &umr_bitfield_default },
	 { "OVRR_CGRFSH", 2, 2, &umr_bitfield_default },
	 { "OVRR_CGSQM", 3, 3, &umr_bitfield_default },
	 { "OVRR_PM", 7, 7, &umr_bitfield_default },
	 { "OVRR_PM_STATE", 8, 9, &umr_bitfield_default },
	 { "OVRR_RD", 10, 10, &umr_bitfield_default },
	 { "OVRR_RD_STATE", 11, 11, &umr_bitfield_default },
	 { "OVRR_RFSH", 14, 14, &umr_bitfield_default },
	 { "OVRR_RFSH_STATE", 15, 15, &umr_bitfield_default },
	 { "OVRR_WR", 12, 12, &umr_bitfield_default },
	 { "OVRR_WR_STATE", 13, 13, &umr_bitfield_default },
	 { "SRFSH_ON_D1", 4, 4, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_ARB_GDEC_RD_CNTL[] = {
	 { "PAGEBIT0", 0, 3, &umr_bitfield_default },
	 { "PAGEBIT1", 4, 7, &umr_bitfield_default },
	 { "REM_DEFAULT_GRP", 10, 13, &umr_bitfield_default },
	 { "USE_RANK", 8, 8, &umr_bitfield_default },
	 { "USE_RSNO", 9, 9, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_ARB_GDEC_WR_CNTL[] = {
	 { "PAGEBIT0", 0, 3, &umr_bitfield_default },
	 { "PAGEBIT1", 4, 7, &umr_bitfield_default },
	 { "REM_DEFAULT_GRP", 10, 13, &umr_bitfield_default },
	 { "USE_RANK", 8, 8, &umr_bitfield_default },
	 { "USE_RSNO", 9, 9, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_ARB_LM_RD[] = {
	 { "BANKGROUP_CONFIG", 21, 23, &umr_bitfield_default },
	 { "ENABLE_TWO_LIST", 18, 18, &umr_bitfield_default },
	 { "POPIDLE_RST_TWOLIST", 19, 19, &umr_bitfield_default },
	 { "SKID1_RST_TWOLIST", 20, 20, &umr_bitfield_default },
	 { "STREAK_BREAK", 16, 16, &umr_bitfield_default },
	 { "STREAK_LIMIT", 0, 7, &umr_bitfield_default },
	 { "STREAK_LIMIT_UBER", 8, 15, &umr_bitfield_default },
	 { "STREAK_UBER", 17, 17, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_ARB_LM_WR[] = {
	 { "BANKGROUP_CONFIG", 21, 23, &umr_bitfield_default },
	 { "ENABLE_TWO_LIST", 18, 18, &umr_bitfield_default },
	 { "POPIDLE_RST_TWOLIST", 19, 19, &umr_bitfield_default },
	 { "SKID1_RST_TWOLIST", 20, 20, &umr_bitfield_default },
	 { "STREAK_BREAK", 16, 16, &umr_bitfield_default },
	 { "STREAK_LIMIT", 0, 7, &umr_bitfield_default },
	 { "STREAK_LIMIT_UBER", 8, 15, &umr_bitfield_default },
	 { "STREAK_UBER", 17, 17, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_ARB_REMREQ[] = {
	 { "RD_WATER", 0, 7, &umr_bitfield_default },
	 { "WR_LAZY_TIMER", 20, 23, &umr_bitfield_default },
	 { "WR_MAXBURST_SIZE", 16, 19, &umr_bitfield_default },
	 { "WR_WATER", 8, 15, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_ARB_REPLAY[] = {
	 { "BOS_ENABLE_WAIT_CYC", 7, 7, &umr_bitfield_default },
	 { "BOS_WAIT_CYC", 8, 14, &umr_bitfield_default },
	 { "BREAK_ON_STALL", 6, 6, &umr_bitfield_default },
	 { "ENABLE_RD", 0, 0, &umr_bitfield_default },
	 { "ENABLE_WR", 1, 1, &umr_bitfield_default },
	 { "IGNORE_WR_CDC", 5, 5, &umr_bitfield_default },
	 { "RAW_ENABLE", 4, 4, &umr_bitfield_default },
	 { "WAW_ENABLE", 3, 3, &umr_bitfield_default },
	 { "WRACK_MODE", 2, 2, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_ARB_RET_CREDITS_RD[] = {
	 { "DISP", 16, 23, &umr_bitfield_default },
	 { "HUB", 8, 15, &umr_bitfield_default },
	 { "LCL", 0, 7, &umr_bitfield_default },
	 { "RETURN_CREDIT", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_ARB_RET_CREDITS_WR[] = {
	 { "HUB", 8, 15, &umr_bitfield_default },
	 { "LCL", 0, 7, &umr_bitfield_default },
	 { "RETURN_CREDIT", 16, 23, &umr_bitfield_default },
	 { "WRRET_SEQ_SKID", 24, 27, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_ARB_CG[] = {
	 { "CG_ARB_REQ", 0, 7, &umr_bitfield_default },
	 { "CG_ARB_RESP", 8, 15, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_ARB_WCDR[] = {
	 { "IDLE_BURST", 7, 12, &umr_bitfield_default },
	 { "IDLE_BURST_MODE", 13, 13, &umr_bitfield_default },
	 { "IDLE_DEGLITCH_ENABLE", 16, 16, &umr_bitfield_default },
	 { "IDLE_ENABLE", 0, 0, &umr_bitfield_default },
	 { "IDLE_PERIOD", 2, 6, &umr_bitfield_default },
	 { "IDLE_WAKEUP", 14, 15, &umr_bitfield_default },
	 { "SEQ_IDLE", 1, 1, &umr_bitfield_default },
	 { "WPRE_ENABLE", 17, 17, &umr_bitfield_default },
	 { "WPRE_INC_READ", 25, 25, &umr_bitfield_default },
	 { "WPRE_INC_SEQIDLE", 27, 27, &umr_bitfield_default },
	 { "WPRE_INC_SKIDIDLE", 26, 26, &umr_bitfield_default },
	 { "WPRE_MAX_BURST", 22, 24, &umr_bitfield_default },
	 { "WPRE_THRESHOLD", 18, 21, &umr_bitfield_default },
	 { "WPRE_TWOPAGE", 28, 28, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_ARB_DRAM_TIMING_1[] = {
	 { "ACTRD", 0, 7, &umr_bitfield_default },
	 { "ACTWR", 8, 15, &umr_bitfield_default },
	 { "RASMACTRD", 16, 23, &umr_bitfield_default },
	 { "RASMACTWR", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_ARB_DRAM_TIMING2_1[] = {
	 { "BUS_TURN", 24, 28, &umr_bitfield_default },
	 { "RAS2RAS", 0, 7, &umr_bitfield_default },
	 { "RP", 8, 15, &umr_bitfield_default },
	 { "WRPLUSRP", 16, 23, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_ARB_BURST_TIME[] = {
	 { "STATE0", 0, 4, &umr_bitfield_default },
	 { "STATE1", 5, 9, &umr_bitfield_default },
	 { "STATE2", 10, 14, &umr_bitfield_default },
	 { "STATE3", 15, 19, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_BIST_CNTL[] = {
	 { "ADR_MODE", 5, 5, &umr_bitfield_default },
	 { "DAT_MODE", 6, 6, &umr_bitfield_default },
	 { "DONE", 30, 30, &umr_bitfield_default },
	 { "ENABLE_D0", 12, 12, &umr_bitfield_default },
	 { "ENABLE_D1", 13, 13, &umr_bitfield_default },
	 { "LOAD_RTDATA_CH", 14, 14, &umr_bitfield_default },
	 { "LOAD_RTDATA", 31, 31, &umr_bitfield_default },
	 { "LOOP_CNT", 16, 27, &umr_bitfield_default },
	 { "LOOP", 10, 11, &umr_bitfield_default },
	 { "MOP_MODE", 4, 4, &umr_bitfield_default },
	 { "PTR_RST_D0", 2, 2, &umr_bitfield_default },
	 { "PTR_RST_D1", 3, 3, &umr_bitfield_default },
	 { "RESET", 0, 0, &umr_bitfield_default },
	 { "RUN", 1, 1, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_BIST_AUTO_CNTL[] = {
	 { "ADR_GEN", 4, 7, &umr_bitfield_default },
	 { "ADR_RESET", 25, 25, &umr_bitfield_default },
	 { "LFSR_KEY", 8, 23, &umr_bitfield_default },
	 { "LFSR_RESET", 24, 24, &umr_bitfield_default },
	 { "MOP", 0, 1, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_BIST_DIR_CNTL[] = {
	 { "CMD_RTR_D0", 6, 6, &umr_bitfield_default },
	 { "CMD_RTR_D1", 8, 8, &umr_bitfield_default },
	 { "DATA_LOAD", 5, 5, &umr_bitfield_default },
	 { "DAT_RTR_D0", 7, 7, &umr_bitfield_default },
	 { "DAT_RTR_D1", 9, 9, &umr_bitfield_default },
	 { "EOB", 3, 3, &umr_bitfield_default },
	 { "MOP3", 10, 10, &umr_bitfield_default },
	 { "MOP_LOAD", 4, 4, &umr_bitfield_default },
	 { "MOP", 0, 2, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_BIST_SADDR[] = {
	 { "BANK", 24, 27, &umr_bitfield_default },
	 { "COLH", 29, 29, &umr_bitfield_default },
	 { "COL", 0, 9, &umr_bitfield_default },
	 { "RANK", 28, 28, &umr_bitfield_default },
	 { "ROWH", 30, 31, &umr_bitfield_default },
	 { "ROW", 10, 23, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_BIST_EADDR[] = {
	 { "BANK", 24, 27, &umr_bitfield_default },
	 { "COLH", 29, 29, &umr_bitfield_default },
	 { "COL", 0, 9, &umr_bitfield_default },
	 { "RANK", 28, 28, &umr_bitfield_default },
	 { "ROWH", 30, 31, &umr_bitfield_default },
	 { "ROW", 10, 23, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_BIST_DATA_WORD0[] = {
	 { "DATA", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_BIST_DATA_WORD1[] = {
	 { "DATA", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_BIST_DATA_WORD2[] = {
	 { "DATA", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_BIST_DATA_WORD3[] = {
	 { "DATA", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_BIST_DATA_WORD4[] = {
	 { "DATA", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_BIST_DATA_WORD5[] = {
	 { "DATA", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_BIST_DATA_WORD6[] = {
	 { "DATA", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_BIST_DATA_WORD7[] = {
	 { "DATA", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_BIST_DATA_MASK[] = {
	 { "MASK", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_BIST_MISMATCH_ADDR[] = {
	 { "BANK", 24, 27, &umr_bitfield_default },
	 { "COLH", 29, 29, &umr_bitfield_default },
	 { "COL", 0, 9, &umr_bitfield_default },
	 { "RANK", 28, 28, &umr_bitfield_default },
	 { "ROWH", 30, 31, &umr_bitfield_default },
	 { "ROW", 10, 23, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_BIST_RDATA_WORD0[] = {
	 { "RDATA", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_BIST_RDATA_WORD1[] = {
	 { "RDATA", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_BIST_RDATA_WORD2[] = {
	 { "RDATA", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_BIST_RDATA_WORD3[] = {
	 { "RDATA", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_BIST_RDATA_WORD4[] = {
	 { "RDATA", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_BIST_RDATA_WORD5[] = {
	 { "RDATA", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_BIST_RDATA_WORD6[] = {
	 { "RDATA", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_BIST_RDATA_WORD7[] = {
	 { "RDATA", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_BIST_RDATA_MASK[] = {
	 { "MASK", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_BIST_RDATA_EDC[] = {
	 { "EDC", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_SEQ_RESERVE_0_S[] = {
	 { "SCLK_FIELD", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_SEQ_RESERVE_1_S[] = {
	 { "SCLK_FIELD", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_SEQ_STATUS_S[] = {
	 { "SEQ0_ARB_CMD_FIFO_FULL", 4, 4, &umr_bitfield_default },
	 { "SEQ0_ARB_DATA_FIFO_FULL", 0, 0, &umr_bitfield_default },
	 { "SEQ0_RS_DATA_FIFO_EMPTY", 8, 8, &umr_bitfield_default },
	 { "SEQ1_ARB_CMD_FIFO_FULL", 5, 5, &umr_bitfield_default },
	 { "SEQ1_ARB_DATA_FIFO_FULL", 1, 1, &umr_bitfield_default },
	 { "SEQ1_RS_DATA_FIFO_EMPTY", 9, 9, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_CG_DATAPORT[] = {
	 { "DATA_FIELD", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_SEQ_MPLL_OVERRIDE[] = {
	 { "AD_PLL_RESET_OVERRIDE", 0, 0, &umr_bitfield_default },
	 { "ATGM_CLK_SEL_OVERRIDE", 5, 5, &umr_bitfield_default },
	 { "DQ_0_0_PLL_RESET_OVERRIDE", 1, 1, &umr_bitfield_default },
	 { "DQ_0_1_PLL_RESET_OVERRIDE", 2, 2, &umr_bitfield_default },
	 { "DQ_1_0_PLL_RESET_OVERRIDE", 3, 3, &umr_bitfield_default },
	 { "DQ_1_1_PLL_RESET_OVERRIDE", 4, 4, &umr_bitfield_default },
	 { "TEST_BYPASS_CLK_EN_OVERRIDE", 6, 6, &umr_bitfield_default },
	 { "TEST_BYPASS_CLK_SEL_OVERRIDE", 7, 7, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_SEQ_CNTL[] = {
	 { "ARB_REQCMD_WMK", 20, 23, &umr_bitfield_default },
	 { "ARB_REQDAT_WMK", 24, 27, &umr_bitfield_default },
	 { "ARB_RTDAT_WMK", 28, 31, &umr_bitfield_default },
	 { "BANKGROUP_ENB", 18, 18, &umr_bitfield_default },
	 { "BANKGROUP_SIZE", 17, 17, &umr_bitfield_default },
	 { "CHANNEL_DISABLE", 8, 9, &umr_bitfield_default },
	 { "DAT_INV", 6, 6, &umr_bitfield_default },
	 { "MEM_ADDR_MAP_BANK", 2, 3, &umr_bitfield_default },
	 { "MEM_ADDR_MAP_COLS", 0, 1, &umr_bitfield_default },
	 { "MSK_DF1", 7, 7, &umr_bitfield_default },
	 { "MSKOFF_DAT_TH", 15, 15, &umr_bitfield_default },
	 { "MSKOFF_DAT_TL", 14, 14, &umr_bitfield_default },
	 { "RET_HOLD_EOP", 16, 16, &umr_bitfield_default },
	 { "RTR_OVERRIDE", 19, 19, &umr_bitfield_default },
	 { "SAFE_MODE", 4, 5, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_SEQ_DRAM[] = {
	 { "ADR_2CK", 0, 0, &umr_bitfield_default },
	 { "ADR_DF1", 2, 2, &umr_bitfield_default },
	 { "ADR_MUX", 1, 1, &umr_bitfield_default },
	 { "AP8", 3, 3, &umr_bitfield_default },
	 { "BO4", 14, 14, &umr_bitfield_default },
	 { "CKE_ACT", 13, 13, &umr_bitfield_default },
	 { "CKE_DYN", 12, 12, &umr_bitfield_default },
	 { "DAT_DF1", 4, 4, &umr_bitfield_default },
	 { "DAT_INV", 24, 24, &umr_bitfield_default },
	 { "DLL_CLR", 15, 15, &umr_bitfield_default },
	 { "DLL_CNT", 16, 23, &umr_bitfield_default },
	 { "DQM_ACT", 7, 7, &umr_bitfield_default },
	 { "DQM_DF1", 6, 6, &umr_bitfield_default },
	 { "DQS_DF1", 5, 5, &umr_bitfield_default },
	 { "INV_ACM", 25, 25, &umr_bitfield_default },
	 { "ODT_ACT", 27, 27, &umr_bitfield_default },
	 { "ODT_ENB", 26, 26, &umr_bitfield_default },
	 { "RST_CTL", 28, 28, &umr_bitfield_default },
	 { "STB_CNT", 8, 11, &umr_bitfield_default },
	 { "TRI_CKE", 30, 30, &umr_bitfield_default },
	 { "TRI_MIO_DYN", 29, 29, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_SEQ_DRAM_2[] = {
	 { "ADBI_ACT", 26, 26, &umr_bitfield_default },
	 { "ADBI_DF1", 25, 25, &umr_bitfield_default },
	 { "ADR_DBI_ACM", 2, 2, &umr_bitfield_default },
	 { "ADR_DBI", 1, 1, &umr_bitfield_default },
	 { "ADR_DDR", 0, 0, &umr_bitfield_default },
	 { "BNK_MRS", 13, 13, &umr_bitfield_default },
	 { "CMD_QDR", 3, 3, &umr_bitfield_default },
	 { "CS_BY16", 31, 31, &umr_bitfield_default },
	 { "DAT_QDR", 4, 4, &umr_bitfield_default },
	 { "DBI_ACT", 28, 28, &umr_bitfield_default },
	 { "DBI_DF1", 27, 27, &umr_bitfield_default },
	 { "DBI_EDC_DF1", 29, 29, &umr_bitfield_default },
	 { "DBI_OVR", 14, 14, &umr_bitfield_default },
	 { "DLL_EST", 12, 12, &umr_bitfield_default },
	 { "DQM_EST", 7, 7, &umr_bitfield_default },
	 { "PCH_BNK", 24, 24, &umr_bitfield_default },
	 { "PLL_CLR", 11, 11, &umr_bitfield_default },
	 { "PLL_CNT", 16, 23, &umr_bitfield_default },
	 { "PLL_EST", 10, 10, &umr_bitfield_default },
	 { "RDAT_EDC", 6, 6, &umr_bitfield_default },
	 { "RD_DQS", 8, 8, &umr_bitfield_default },
	 { "TESTCHIP_EN", 30, 30, &umr_bitfield_default },
	 { "TRI_CLK", 15, 15, &umr_bitfield_default },
	 { "WDAT_EDC", 5, 5, &umr_bitfield_default },
	 { "WR_DQS", 9, 9, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_SEQ_RAS_TIMING[] = {
	 { "TRCDRA", 15, 19, &umr_bitfield_default },
	 { "TRCDR", 10, 14, &umr_bitfield_default },
	 { "TRCDWA", 5, 9, &umr_bitfield_default },
	 { "TRCDW", 0, 4, &umr_bitfield_default },
	 { "TRC", 24, 30, &umr_bitfield_default },
	 { "TRRD", 20, 23, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_SEQ_CAS_TIMING[] = {
	 { "TCCDL", 9, 11, &umr_bitfield_default },
	 { "TCL", 24, 28, &umr_bitfield_default },
	 { "TNOPR", 2, 3, &umr_bitfield_default },
	 { "TNOPW", 0, 1, &umr_bitfield_default },
	 { "TR2R", 12, 15, &umr_bitfield_default },
	 { "TR2W", 4, 8, &umr_bitfield_default },
	 { "TW2R", 16, 20, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_SEQ_MISC_TIMING[] = {
	 { "TRFC", 20, 28, &umr_bitfield_default },
	 { "TRP", 15, 19, &umr_bitfield_default },
	 { "TRP_RDA", 8, 13, &umr_bitfield_default },
	 { "TRP_WRA", 0, 5, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_SEQ_MISC_TIMING2[] = {
	 { "FAW", 8, 12, &umr_bitfield_default },
	 { "PA2RDATA", 0, 2, &umr_bitfield_default },
	 { "PA2WDATA", 4, 6, &umr_bitfield_default },
	 { "T32AW", 21, 24, &umr_bitfield_default },
	 { "TREDC", 13, 15, &umr_bitfield_default },
	 { "TWDATATR", 28, 31, &umr_bitfield_default },
	 { "TWEDC", 16, 20, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_SEQ_PMG_TIMING[] = {
	 { "SEQ_IDLE", 18, 20, &umr_bitfield_default },
	 { "SEQ_IDLE_SS", 24, 31, &umr_bitfield_default },
	 { "TCKE", 12, 17, &umr_bitfield_default },
	 { "TCKE_PULSE", 8, 11, &umr_bitfield_default },
	 { "TCKE_PULSE_MSB", 23, 23, &umr_bitfield_default },
	 { "TCKSRE", 0, 2, &umr_bitfield_default },
	 { "TCKSRX", 4, 6, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_SEQ_RD_CTL_D0[] = {
	 { "RBS_DLY", 20, 24, &umr_bitfield_default },
	 { "RBS_WEDC_DLY", 25, 29, &umr_bitfield_default },
	 { "RCV_DLY", 0, 2, &umr_bitfield_default },
	 { "RCV_EXT", 3, 7, &umr_bitfield_default },
	 { "RST_HLD", 12, 15, &umr_bitfield_default },
	 { "RST_SEL", 8, 9, &umr_bitfield_default },
	 { "RXDPWRON_DLY", 10, 11, &umr_bitfield_default },
	 { "STR_PRE", 16, 16, &umr_bitfield_default },
	 { "STR_PST", 17, 17, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_SEQ_RD_CTL_D1[] = {
	 { "RBS_DLY", 20, 24, &umr_bitfield_default },
	 { "RBS_WEDC_DLY", 25, 29, &umr_bitfield_default },
	 { "RCV_DLY", 0, 2, &umr_bitfield_default },
	 { "RCV_EXT", 3, 7, &umr_bitfield_default },
	 { "RST_HLD", 12, 15, &umr_bitfield_default },
	 { "RST_SEL", 8, 9, &umr_bitfield_default },
	 { "RXDPWRON_DLY", 10, 11, &umr_bitfield_default },
	 { "STR_PRE", 16, 16, &umr_bitfield_default },
	 { "STR_PST", 17, 17, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_SEQ_WR_CTL_D0[] = {
	 { "ADR_2Y_DLY", 10, 10, &umr_bitfield_default },
	 { "ADR_DLY", 29, 29, &umr_bitfield_default },
	 { "CMD_2Y_DLY", 11, 11, &umr_bitfield_default },
	 { "CMD_DLY", 30, 30, &umr_bitfield_default },
	 { "DAT_2Y_DLY", 9, 9, &umr_bitfield_default },
	 { "DAT_DLY", 0, 3, &umr_bitfield_default },
	 { "DQS_DLY", 4, 7, &umr_bitfield_default },
	 { "DQS_XTR", 8, 8, &umr_bitfield_default },
	 { "ODT_DLY", 24, 27, &umr_bitfield_default },
	 { "ODT_EXT", 28, 28, &umr_bitfield_default },
	 { "OEN_DLY", 12, 15, &umr_bitfield_default },
	 { "OEN_EXT", 16, 19, &umr_bitfield_default },
	 { "OEN_SEL", 20, 21, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_SEQ_WR_CTL_D1[] = {
	 { "ADR_2Y_DLY", 10, 10, &umr_bitfield_default },
	 { "ADR_DLY", 29, 29, &umr_bitfield_default },
	 { "CMD_2Y_DLY", 11, 11, &umr_bitfield_default },
	 { "CMD_DLY", 30, 30, &umr_bitfield_default },
	 { "DAT_2Y_DLY", 9, 9, &umr_bitfield_default },
	 { "DAT_DLY", 0, 3, &umr_bitfield_default },
	 { "DQS_DLY", 4, 7, &umr_bitfield_default },
	 { "DQS_XTR", 8, 8, &umr_bitfield_default },
	 { "ODT_DLY", 24, 27, &umr_bitfield_default },
	 { "ODT_EXT", 28, 28, &umr_bitfield_default },
	 { "OEN_DLY", 12, 15, &umr_bitfield_default },
	 { "OEN_EXT", 16, 19, &umr_bitfield_default },
	 { "OEN_SEL", 20, 21, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_SEQ_CMD[] = {
	 { "ADR", 0, 15, &umr_bitfield_default },
	 { "ADR_MSB0", 29, 29, &umr_bitfield_default },
	 { "ADR_MSB1", 28, 28, &umr_bitfield_default },
	 { "CHAN0", 24, 24, &umr_bitfield_default },
	 { "CHAN1", 25, 25, &umr_bitfield_default },
	 { "CSB", 21, 22, &umr_bitfield_default },
	 { "END", 20, 20, &umr_bitfield_default },
	 { "MOP", 16, 19, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_SEQ_SUP_CNTL[] = {
	 { "BKPT_CLEAR", 7, 7, &umr_bitfield_default },
	 { "FAST_WRITE", 6, 6, &umr_bitfield_default },
	 { "PGM_CHKSUM", 23, 31, &umr_bitfield_default },
	 { "PGM_READ", 5, 5, &umr_bitfield_default },
	 { "PGM_WRITE", 4, 4, &umr_bitfield_default },
	 { "RESET_PC", 3, 3, &umr_bitfield_default },
	 { "RUN", 0, 0, &umr_bitfield_default },
	 { "SINGLE_STEP", 1, 1, &umr_bitfield_default },
	 { "SW_WAKE", 2, 2, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_SEQ_SUP_PGM[] = {
	 { "CNTL", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_PMG_AUTO_CMD[] = {
	 { "ADR", 0, 16, &umr_bitfield_default },
	 { "ADR_MSB0", 29, 29, &umr_bitfield_default },
	 { "ADR_MSB1", 28, 28, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_PMG_AUTO_CFG[] = {
	 { "DLL_CNT", 24, 31, &umr_bitfield_default },
	 { "EXIT_ALLOW_STOP", 11, 11, &umr_bitfield_default },
	 { "MRS_WAIT_CNT", 16, 19, &umr_bitfield_default },
	 { "PREA_SRX", 13, 13, &umr_bitfield_default },
	 { "RFS_SRX", 12, 12, &umr_bitfield_default },
	 { "RST_MRS", 1, 1, &umr_bitfield_default },
	 { "RXPDNB", 22, 22, &umr_bitfield_default },
	 { "SCDS_MODE", 10, 10, &umr_bitfield_default },
	 { "SELFREFR_COMMIT_0", 15, 15, &umr_bitfield_default },
	 { "SELFREFR_COMMIT_1", 23, 23, &umr_bitfield_default },
	 { "SS_ALWAYS_SLF", 8, 8, &umr_bitfield_default },
	 { "SS_S_SLF", 9, 9, &umr_bitfield_default },
	 { "STUTTER_EN", 14, 14, &umr_bitfield_default },
	 { "SYC_CLK", 0, 0, &umr_bitfield_default },
	 { "TRI_MIO", 2, 2, &umr_bitfield_default },
	 { "WRITE_DURING_DLOCK", 20, 20, &umr_bitfield_default },
	 { "XSR_TMR", 4, 7, &umr_bitfield_default },
	 { "YCLK_ON", 21, 21, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_IMP_CNTL[] = {
	 { "CAL_PWRON", 31, 31, &umr_bitfield_default },
	 { "CAL_VREF", 16, 22, &umr_bitfield_default },
	 { "CAL_VREFMODE", 6, 6, &umr_bitfield_default },
	 { "CAL_VREF_SEL", 5, 5, &umr_bitfield_default },
	 { "CAL_WHEN_IDLE", 29, 29, &umr_bitfield_default },
	 { "CAL_WHEN_REFRESH", 30, 30, &umr_bitfield_default },
	 { "CLEAR_TIMEOUT_ERR", 9, 9, &umr_bitfield_default },
	 { "MEM_IO_SAMPLE_CNT", 13, 15, &umr_bitfield_default },
	 { "MEM_IO_UPDATE_RATE", 0, 4, &umr_bitfield_default },
	 { "TIMEOUT_ERR", 8, 8, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_IMP_DEBUG[] = {
	 { "DEBUG_CAL_DONE", 31, 31, &umr_bitfield_default },
	 { "DEBUG_CAL_EN", 28, 28, &umr_bitfield_default },
	 { "DEBUG_CAL_INTR", 30, 30, &umr_bitfield_default },
	 { "DEBUG_CAL_START", 29, 29, &umr_bitfield_default },
	 { "PMVCAL_RESERVED", 16, 27, &umr_bitfield_default },
	 { "TIMEOUT_CNTR", 8, 15, &umr_bitfield_default },
	 { "TSTARTUP_CNTR", 0, 7, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_IMP_STATUS[] = {
	 { "NSTR_ACCUM_VAL", 24, 31, &umr_bitfield_default },
	 { "NSTR_CAL", 16, 23, &umr_bitfield_default },
	 { "PSTR_ACCUM_VAL", 8, 15, &umr_bitfield_default },
	 { "PSTR_CAL", 0, 7, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_SEQ_WCDR_CTRL[] = {
	 { "AREF_EN", 14, 14, &umr_bitfield_default },
	 { "PRBS_EN", 20, 20, &umr_bitfield_default },
	 { "PRBS_RST", 21, 21, &umr_bitfield_default },
	 { "PREAMBLE", 24, 27, &umr_bitfield_default },
	 { "PRE_MASK", 28, 31, &umr_bitfield_default },
	 { "RD_EN", 13, 13, &umr_bitfield_default },
	 { "TRAIN_EN", 15, 15, &umr_bitfield_default },
	 { "TWCDRL", 16, 19, &umr_bitfield_default },
	 { "WCDR_PRE", 0, 7, &umr_bitfield_default },
	 { "WCDR_TIM", 8, 11, &umr_bitfield_default },
	 { "WR_EN", 12, 12, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_SEQ_TRAIN_WAKEUP_CNTL[] = {
	 { "AUTO_REFRESH_ADDR_TRAIN", 8, 8, &umr_bitfield_default },
	 { "AUTO_REFRESH_READ_TRAIN", 10, 10, &umr_bitfield_default },
	 { "AUTO_REFRESH_WAKEUP_EARLY", 20, 20, &umr_bitfield_default },
	 { "AUTO_REFRESH_WCK_TRAIN", 9, 9, &umr_bitfield_default },
	 { "AUTO_REFRESH_WRITE_TRAIN", 11, 11, &umr_bitfield_default },
	 { "BLOCK_ARB_RD_D0", 24, 24, &umr_bitfield_default },
	 { "BLOCK_ARB_RD_D1", 26, 26, &umr_bitfield_default },
	 { "BLOCK_ARB_WR_D0", 25, 25, &umr_bitfield_default },
	 { "BLOCK_ARB_WR_D1", 27, 27, &umr_bitfield_default },
	 { "BOOT_UP_ADDR_TRAIN", 0, 0, &umr_bitfield_default },
	 { "BOOT_UP_READ_TRAIN", 2, 2, &umr_bitfield_default },
	 { "BOOT_UP_WCK_TRAIN", 1, 1, &umr_bitfield_default },
	 { "BOOT_UP_WRITE_TRAIN", 3, 3, &umr_bitfield_default },
	 { "DISP_ASTOP_WAKEUP", 29, 29, &umr_bitfield_default },
	 { "READ_ECC_ADDR_TRAIN", 16, 16, &umr_bitfield_default },
	 { "READ_ECC_READ_TRAIN", 18, 18, &umr_bitfield_default },
	 { "READ_ECC_WCK_TRAIN", 17, 17, &umr_bitfield_default },
	 { "READ_ECC_WRITE_TRAIN", 19, 19, &umr_bitfield_default },
	 { "SELF_REFRESH_ADDR_TRAIN", 4, 4, &umr_bitfield_default },
	 { "SELF_REFRESH_READ_TRAIN", 6, 6, &umr_bitfield_default },
	 { "SELF_REFRESH_WCK_TRAIN", 5, 5, &umr_bitfield_default },
	 { "SELF_REFRESH_WRITE_TRAIN", 7, 7, &umr_bitfield_default },
	 { "STOP_WCK_D0", 21, 21, &umr_bitfield_default },
	 { "STOP_WCK_D1", 22, 22, &umr_bitfield_default },
	 { "SW_WAKEUP", 28, 28, &umr_bitfield_default },
	 { "TRAIN_DONE_D0", 30, 30, &umr_bitfield_default },
	 { "TRAIN_DONE_D1", 31, 31, &umr_bitfield_default },
	 { "WRITE_ECC_ADDR_TRAIN", 12, 12, &umr_bitfield_default },
	 { "WRITE_ECC_READ_TRAIN", 14, 14, &umr_bitfield_default },
	 { "WRITE_ECC_WCK_TRAIN", 13, 13, &umr_bitfield_default },
	 { "WRITE_ECC_WRITE_TRAIN", 15, 15, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_SEQ_TRAIN_EDC_THRESHOLD[] = {
	 { "READ_EDC_THRESHOLD", 16, 31, &umr_bitfield_default },
	 { "WRITE_EDC_THRESHOLD", 0, 15, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_SEQ_TRAIN_WAKEUP_EDGE[] = {
	 { "ALLOWSTOP0_WAKEUP", 18, 18, &umr_bitfield_default },
	 { "ALLOWSTOP1_WAKEUP", 19, 19, &umr_bitfield_default },
	 { "ALLOWSTOPB0_WAKEUP", 21, 21, &umr_bitfield_default },
	 { "ALLOWSTOPB1_WAKEUP", 22, 22, &umr_bitfield_default },
	 { "D0_ARF_WAKEUP", 0, 0, &umr_bitfield_default },
	 { "D0_CMD_FIFO_READY_WAKEUP", 8, 8, &umr_bitfield_default },
	 { "D0_DATA_FIFO_READY_WAKEUP", 10, 10, &umr_bitfield_default },
	 { "D0_IDLEH_WAKEUP", 24, 24, &umr_bitfield_default },
	 { "D0_REDC_WAKEUP", 2, 2, &umr_bitfield_default },
	 { "D0_WEDC_WAKEUP", 4, 4, &umr_bitfield_default },
	 { "D1_ARF_WAKEUP", 1, 1, &umr_bitfield_default },
	 { "D1_CMD_FIFO_READY_WAKEUP", 9, 9, &umr_bitfield_default },
	 { "D1_DATA_FIFO_READY_WAKEUP", 11, 11, &umr_bitfield_default },
	 { "D1_IDLEH_WAKEUP", 25, 25, &umr_bitfield_default },
	 { "D1_REDC_WAKEUP", 3, 3, &umr_bitfield_default },
	 { "D1_WEDC_WAKEUP", 5, 5, &umr_bitfield_default },
	 { "DPM_LPT_WAKEUP", 23, 23, &umr_bitfield_default },
	 { "DPM_WAKEUP", 20, 20, &umr_bitfield_default },
	 { "MCLK_FREQ_CHANGE_WAKEUP", 6, 6, &umr_bitfield_default },
	 { "PHY_PG_WAKEUP", 26, 26, &umr_bitfield_default },
	 { "RESERVE0_WAKEUP", 13, 13, &umr_bitfield_default },
	 { "SCLK_SRBM_READY_WAKEUP", 7, 7, &umr_bitfield_default },
	 { "SOFTWARE_WAKEUP_WAKEUP", 12, 12, &umr_bitfield_default },
	 { "TCG_DONE_WAKEUP", 17, 17, &umr_bitfield_default },
	 { "TIMER_DONE_WAKEUP", 15, 15, &umr_bitfield_default },
	 { "TSM_DONE_WAKEUP", 14, 14, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_SEQ_TRAIN_WAKEUP_MASK[] = {
	 { "ALLOWSTOP0_WAKEUP", 18, 18, &umr_bitfield_default },
	 { "ALLOWSTOP1_WAKEUP", 19, 19, &umr_bitfield_default },
	 { "ALLOWSTOPB0_WAKEUP", 21, 21, &umr_bitfield_default },
	 { "ALLOWSTOPB1_WAKEUP", 22, 22, &umr_bitfield_default },
	 { "D0_ARF_WAKEUP", 0, 0, &umr_bitfield_default },
	 { "D0_CMD_FIFO_READY_WAKEUP", 8, 8, &umr_bitfield_default },
	 { "D0_DATA_FIFO_READY_WAKEUP", 10, 10, &umr_bitfield_default },
	 { "D0_IDLEH_WAKEUP", 24, 24, &umr_bitfield_default },
	 { "D0_REDC_WAKEUP", 2, 2, &umr_bitfield_default },
	 { "D0_WEDC_WAKEUP", 4, 4, &umr_bitfield_default },
	 { "D1_ARF_WAKEUP", 1, 1, &umr_bitfield_default },
	 { "D1_CMD_FIFO_READY_WAKEUP", 9, 9, &umr_bitfield_default },
	 { "D1_DATA_FIFO_READY_WAKEUP", 11, 11, &umr_bitfield_default },
	 { "D1_IDLEH_WAKEUP", 25, 25, &umr_bitfield_default },
	 { "D1_REDC_WAKEUP", 3, 3, &umr_bitfield_default },
	 { "D1_WEDC_WAKEUP", 5, 5, &umr_bitfield_default },
	 { "DPM_LPT_WAKEUP", 23, 23, &umr_bitfield_default },
	 { "DPM_WAKEUP", 20, 20, &umr_bitfield_default },
	 { "MCLK_FREQ_CHANGE_WAKEUP", 6, 6, &umr_bitfield_default },
	 { "PHY_PG_WAKEUP", 26, 26, &umr_bitfield_default },
	 { "RESERVE0_WAKEUP", 13, 13, &umr_bitfield_default },
	 { "SCLK_SRBM_READY_WAKEUP", 7, 7, &umr_bitfield_default },
	 { "SOFTWARE_WAKEUP_WAKEUP", 12, 12, &umr_bitfield_default },
	 { "TCG_DONE_WAKEUP", 17, 17, &umr_bitfield_default },
	 { "TIMER_DONE_WAKEUP", 15, 15, &umr_bitfield_default },
	 { "TSM_DONE_WAKEUP", 14, 14, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_SEQ_TRAIN_CAPTURE[] = {
	 { "ALLOWSTOP0_WAKEUP", 18, 18, &umr_bitfield_default },
	 { "ALLOWSTOP1_WAKEUP", 19, 19, &umr_bitfield_default },
	 { "ALLOWSTOPB0_WAKEUP", 21, 21, &umr_bitfield_default },
	 { "ALLOWSTOPB1_WAKEUP", 22, 22, &umr_bitfield_default },
	 { "D0_ARF_WAKEUP", 0, 0, &umr_bitfield_default },
	 { "D0_CMD_FIFO_READY_WAKEUP", 8, 8, &umr_bitfield_default },
	 { "D0_DATA_FIFO_READY_WAKEUP", 10, 10, &umr_bitfield_default },
	 { "D0_IDLEH_WAKEUP", 24, 24, &umr_bitfield_default },
	 { "D0_REDC_WAKEUP", 2, 2, &umr_bitfield_default },
	 { "D0_WEDC_WAKEUP", 4, 4, &umr_bitfield_default },
	 { "D1_ARF_WAKEUP", 1, 1, &umr_bitfield_default },
	 { "D1_CMD_FIFO_READY_WAKEUP", 9, 9, &umr_bitfield_default },
	 { "D1_DATA_FIFO_READY_WAKEUP", 11, 11, &umr_bitfield_default },
	 { "D1_IDLEH_WAKEUP", 25, 25, &umr_bitfield_default },
	 { "D1_REDC_WAKEUP", 3, 3, &umr_bitfield_default },
	 { "D1_WEDC_WAKEUP", 5, 5, &umr_bitfield_default },
	 { "DPM_LPT_WAKEUP", 23, 23, &umr_bitfield_default },
	 { "DPM_WAKEUP", 20, 20, &umr_bitfield_default },
	 { "MCLK_FREQ_CHANGE_WAKEUP", 6, 6, &umr_bitfield_default },
	 { "PHY_PG_WAKEUP", 26, 26, &umr_bitfield_default },
	 { "RESERVE0_WAKEUP", 13, 13, &umr_bitfield_default },
	 { "SCLK_SRBM_READY_WAKEUP", 7, 7, &umr_bitfield_default },
	 { "SOFTWARE_WAKEUP_WAKEUP", 12, 12, &umr_bitfield_default },
	 { "TCG_DONE_WAKEUP", 17, 17, &umr_bitfield_default },
	 { "TIMER_DONE_WAKEUP", 15, 15, &umr_bitfield_default },
	 { "TSM_DONE_WAKEUP", 14, 14, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_SEQ_TRAIN_WAKEUP_CLEAR[] = {
	 { "ALLOWSTOP0_WAKEUP", 18, 18, &umr_bitfield_default },
	 { "ALLOWSTOP1_WAKEUP", 19, 19, &umr_bitfield_default },
	 { "ALLOWSTOPB0_WAKEUP", 21, 21, &umr_bitfield_default },
	 { "ALLOWSTOPB1_WAKEUP", 22, 22, &umr_bitfield_default },
	 { "CLEARALL", 16, 16, &umr_bitfield_default },
	 { "D0_ARF_WAKEUP", 0, 0, &umr_bitfield_default },
	 { "D0_CMD_FIFO_READY_WAKEUP", 8, 8, &umr_bitfield_default },
	 { "D0_DATA_FIFO_READY_WAKEUP", 10, 10, &umr_bitfield_default },
	 { "D0_IDLEH_WAKEUP", 24, 24, &umr_bitfield_default },
	 { "D0_REDC_WAKEUP", 2, 2, &umr_bitfield_default },
	 { "D0_WEDC_WAKEUP", 4, 4, &umr_bitfield_default },
	 { "D1_ARF_WAKEUP", 1, 1, &umr_bitfield_default },
	 { "D1_CMD_FIFO_READY_WAKEUP", 9, 9, &umr_bitfield_default },
	 { "D1_DATA_FIFO_READY_WAKEUP", 11, 11, &umr_bitfield_default },
	 { "D1_IDLEH_WAKEUP", 25, 25, &umr_bitfield_default },
	 { "D1_REDC_WAKEUP", 3, 3, &umr_bitfield_default },
	 { "D1_WEDC_WAKEUP", 5, 5, &umr_bitfield_default },
	 { "DPM_LPT_WAKEUP", 23, 23, &umr_bitfield_default },
	 { "DPM_WAKEUP", 20, 20, &umr_bitfield_default },
	 { "MCLK_FREQ_CHANGE_WAKEUP", 6, 6, &umr_bitfield_default },
	 { "PHY_PG_WAKEUP", 26, 26, &umr_bitfield_default },
	 { "RESERVE0_WAKEUP", 13, 13, &umr_bitfield_default },
	 { "SCLK_SRBM_READY_WAKEUP", 7, 7, &umr_bitfield_default },
	 { "SOFTWARE_WAKEUP_WAKEUP", 12, 12, &umr_bitfield_default },
	 { "TCG_DONE_WAKEUP", 17, 17, &umr_bitfield_default },
	 { "TIMER_DONE_WAKEUP", 15, 15, &umr_bitfield_default },
	 { "TSM_DONE_WAKEUP", 14, 14, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_SEQ_TRAIN_TIMING[] = {
	 { "TARF2T", 5, 9, &umr_bitfield_default },
	 { "TLD2LD", 15, 19, &umr_bitfield_default },
	 { "TT2ROW", 10, 14, &umr_bitfield_default },
	 { "TWT2RT", 0, 4, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_TRAIN_EDCCDR_R_D0[] = {
	 { "EDC0", 0, 7, &umr_bitfield_default },
	 { "EDC1", 8, 15, &umr_bitfield_default },
	 { "EDC2", 16, 23, &umr_bitfield_default },
	 { "EDC3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_TRAIN_EDCCDR_R_D1[] = {
	 { "EDC0", 0, 7, &umr_bitfield_default },
	 { "EDC1", 8, 15, &umr_bitfield_default },
	 { "EDC2", 16, 23, &umr_bitfield_default },
	 { "EDC3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_TRAIN_PRBSERR_0_D0[] = {
	 { "DQ_STATUS", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_TRAIN_PRBSERR_1_D0[] = {
	 { "DBI_STATUS", 0, 3, &umr_bitfield_default },
	 { "EDC_STATUS", 4, 7, &umr_bitfield_default },
	 { "PMA_PRBSCLR", 28, 28, &umr_bitfield_default },
	 { "PMD0_PRBSCLR", 29, 29, &umr_bitfield_default },
	 { "PMD1_PRBSCLR", 30, 30, &umr_bitfield_default },
	 { "WCDR_STATUS", 12, 15, &umr_bitfield_default },
	 { "WCK_STATUS", 8, 11, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_TRAIN_EDC_STATUS_D0[] = {
	 { "REDC_CNT", 16, 31, &umr_bitfield_default },
	 { "WEDC_CNT", 0, 15, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_TRAIN_PRBSERR_0_D1[] = {
	 { "DQ_STATUS", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_TRAIN_PRBSERR_1_D1[] = {
	 { "DBI_STATUS", 0, 3, &umr_bitfield_default },
	 { "EDC_STATUS", 4, 7, &umr_bitfield_default },
	 { "PMA_PRBSCLR", 28, 28, &umr_bitfield_default },
	 { "PMD0_PRBSCLR", 29, 29, &umr_bitfield_default },
	 { "PMD1_PRBSCLR", 30, 30, &umr_bitfield_default },
	 { "WCDR_STATUS", 12, 15, &umr_bitfield_default },
	 { "WCK_STATUS", 8, 11, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_TRAIN_EDC_STATUS_D1[] = {
	 { "REDC_CNT", 16, 31, &umr_bitfield_default },
	 { "WEDC_CNT", 0, 15, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_IO_TXCNTL_DPHY0_D0[] = {
	 { "BIASSEL", 0, 1, &umr_bitfield_default },
	 { "DRVDUTY", 2, 3, &umr_bitfield_default },
	 { "EDCTX_CLKGATE_EN", 25, 25, &umr_bitfield_default },
	 { "EMPH", 6, 6, &umr_bitfield_default },
	 { "LOWCMEN", 4, 4, &umr_bitfield_default },
	 { "NDRV", 20, 23, &umr_bitfield_default },
	 { "NTERM", 12, 15, &umr_bitfield_default },
	 { "PDRV", 16, 19, &umr_bitfield_default },
	 { "PLL_LOOPBCK", 27, 27, &umr_bitfield_default },
	 { "PTERM", 8, 11, &umr_bitfield_default },
	 { "QDR", 5, 5, &umr_bitfield_default },
	 { "TSTEN", 24, 24, &umr_bitfield_default },
	 { "TXBYPASS_DATA", 28, 31, &umr_bitfield_default },
	 { "TXBYPASS", 26, 26, &umr_bitfield_default },
	 { "TXPD", 7, 7, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_IO_TXCNTL_DPHY1_D0[] = {
	 { "BIASSEL", 0, 1, &umr_bitfield_default },
	 { "DRVDUTY", 2, 3, &umr_bitfield_default },
	 { "EDCTX_CLKGATE_EN", 25, 25, &umr_bitfield_default },
	 { "EMPH", 6, 6, &umr_bitfield_default },
	 { "LOWCMEN", 4, 4, &umr_bitfield_default },
	 { "NDRV", 20, 23, &umr_bitfield_default },
	 { "NTERM", 12, 15, &umr_bitfield_default },
	 { "PDRV", 16, 19, &umr_bitfield_default },
	 { "PLL_LOOPBCK", 27, 27, &umr_bitfield_default },
	 { "PTERM", 8, 11, &umr_bitfield_default },
	 { "QDR", 5, 5, &umr_bitfield_default },
	 { "TSTEN", 24, 24, &umr_bitfield_default },
	 { "TXBYPASS_DATA", 28, 31, &umr_bitfield_default },
	 { "TXBYPASS", 26, 26, &umr_bitfield_default },
	 { "TXPD", 7, 7, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_IO_TXCNTL_APHY_D0[] = {
	 { "BIASSEL", 0, 1, &umr_bitfield_default },
	 { "CKE_BIT", 30, 30, &umr_bitfield_default },
	 { "CKE_SEL", 31, 31, &umr_bitfield_default },
	 { "DRVDUTY", 2, 3, &umr_bitfield_default },
	 { "EMPH", 6, 6, &umr_bitfield_default },
	 { "LOWCMEN", 4, 4, &umr_bitfield_default },
	 { "NDRV", 20, 22, &umr_bitfield_default },
	 { "PDRV", 16, 19, &umr_bitfield_default },
	 { "PMA_LOOPBACK", 13, 15, &umr_bitfield_default },
	 { "PTERM", 8, 11, &umr_bitfield_default },
	 { "QDR", 5, 5, &umr_bitfield_default },
	 { "TSTEN", 24, 24, &umr_bitfield_default },
	 { "TXBPASS_SEL", 12, 12, &umr_bitfield_default },
	 { "TXBYPASS_DATA", 27, 29, &umr_bitfield_default },
	 { "TXBYPASS", 26, 26, &umr_bitfield_default },
	 { "TXPD", 7, 7, &umr_bitfield_default },
	 { "TXRESET", 25, 25, &umr_bitfield_default },
	 { "YCLKON", 23, 23, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_IO_RXCNTL_DPHY0_D0[] = {
	 { "DLL_ADJ_B0", 20, 22, &umr_bitfield_default },
	 { "DLL_ADJ_B1", 24, 26, &umr_bitfield_default },
	 { "DLL_ADJ_M", 28, 28, &umr_bitfield_default },
	 { "DLL_BW_CTRL", 30, 31, &umr_bitfield_default },
	 { "RCVSEL", 2, 2, &umr_bitfield_default },
	 { "REFCLK_PWRON", 29, 29, &umr_bitfield_default },
	 { "RXBIASSEL", 0, 1, &umr_bitfield_default },
	 { "RXDPWRON_DLY", 4, 5, &umr_bitfield_default },
	 { "RXLP", 7, 7, &umr_bitfield_default },
	 { "RXPDNB", 6, 6, &umr_bitfield_default },
	 { "RX_PEAKSEL", 18, 19, &umr_bitfield_default },
	 { "VREFCAL", 8, 11, &umr_bitfield_default },
	 { "VREFCAL_STR", 12, 15, &umr_bitfield_default },
	 { "VREFPDNB", 3, 3, &umr_bitfield_default },
	 { "VREFSEL", 16, 16, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_IO_RXCNTL_DPHY1_D0[] = {
	 { "DLL_ADJ_B0", 20, 22, &umr_bitfield_default },
	 { "DLL_ADJ_B1", 24, 26, &umr_bitfield_default },
	 { "DLL_ADJ_M", 28, 28, &umr_bitfield_default },
	 { "DLL_BW_CTRL", 30, 31, &umr_bitfield_default },
	 { "RCVSEL", 2, 2, &umr_bitfield_default },
	 { "REFCLK_PWRON", 29, 29, &umr_bitfield_default },
	 { "RXBIASSEL", 0, 1, &umr_bitfield_default },
	 { "RXDPWRON_DLY", 4, 5, &umr_bitfield_default },
	 { "RXLP", 7, 7, &umr_bitfield_default },
	 { "RXPDNB", 6, 6, &umr_bitfield_default },
	 { "RX_PEAKSEL", 18, 19, &umr_bitfield_default },
	 { "VREFCAL", 8, 11, &umr_bitfield_default },
	 { "VREFCAL_STR", 12, 15, &umr_bitfield_default },
	 { "VREFPDNB", 3, 3, &umr_bitfield_default },
	 { "VREFSEL", 16, 16, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_IO_DPHY_STR_CNTL_D0[] = {
	 { "CAL_SEL", 26, 27, &umr_bitfield_default },
	 { "LOAD_D_STR", 28, 28, &umr_bitfield_default },
	 { "LOAD_S_STR", 29, 29, &umr_bitfield_default },
	 { "NSTR_OFF_D", 6, 11, &umr_bitfield_default },
	 { "NSTR_OFF_S", 18, 23, &umr_bitfield_default },
	 { "PSTR_OFF_D", 0, 5, &umr_bitfield_default },
	 { "PSTR_OFF_S", 12, 17, &umr_bitfield_default },
	 { "USE_D_CAL", 24, 24, &umr_bitfield_default },
	 { "USE_S_CAL", 25, 25, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_IO_TXCNTL_DPHY0_D1[] = {
	 { "BIASSEL", 0, 1, &umr_bitfield_default },
	 { "DRVDUTY", 2, 3, &umr_bitfield_default },
	 { "EDCTX_CLKGATE_EN", 25, 25, &umr_bitfield_default },
	 { "EMPH", 6, 6, &umr_bitfield_default },
	 { "LOWCMEN", 4, 4, &umr_bitfield_default },
	 { "NDRV", 20, 23, &umr_bitfield_default },
	 { "NTERM", 12, 15, &umr_bitfield_default },
	 { "PDRV", 16, 19, &umr_bitfield_default },
	 { "PLL_LOOPBCK", 27, 27, &umr_bitfield_default },
	 { "PTERM", 8, 11, &umr_bitfield_default },
	 { "QDR", 5, 5, &umr_bitfield_default },
	 { "TSTEN", 24, 24, &umr_bitfield_default },
	 { "TXBYPASS_DATA", 28, 31, &umr_bitfield_default },
	 { "TXBYPASS", 26, 26, &umr_bitfield_default },
	 { "TXPD", 7, 7, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_IO_TXCNTL_DPHY1_D1[] = {
	 { "BIASSEL", 0, 1, &umr_bitfield_default },
	 { "DRVDUTY", 2, 3, &umr_bitfield_default },
	 { "EDCTX_CLKGATE_EN", 25, 25, &umr_bitfield_default },
	 { "EMPH", 6, 6, &umr_bitfield_default },
	 { "LOWCMEN", 4, 4, &umr_bitfield_default },
	 { "NDRV", 20, 23, &umr_bitfield_default },
	 { "NTERM", 12, 15, &umr_bitfield_default },
	 { "PDRV", 16, 19, &umr_bitfield_default },
	 { "PLL_LOOPBCK", 27, 27, &umr_bitfield_default },
	 { "PTERM", 8, 11, &umr_bitfield_default },
	 { "QDR", 5, 5, &umr_bitfield_default },
	 { "TSTEN", 24, 24, &umr_bitfield_default },
	 { "TXBYPASS_DATA", 28, 31, &umr_bitfield_default },
	 { "TXBYPASS", 26, 26, &umr_bitfield_default },
	 { "TXPD", 7, 7, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_IO_TXCNTL_APHY_D1[] = {
	 { "BIASSEL", 0, 1, &umr_bitfield_default },
	 { "CKE_BIT", 30, 30, &umr_bitfield_default },
	 { "CKE_SEL", 31, 31, &umr_bitfield_default },
	 { "DRVDUTY", 2, 3, &umr_bitfield_default },
	 { "EMPH", 6, 6, &umr_bitfield_default },
	 { "LOWCMEN", 4, 4, &umr_bitfield_default },
	 { "NDRV", 20, 22, &umr_bitfield_default },
	 { "PDRV", 16, 19, &umr_bitfield_default },
	 { "PMA_LOOPBACK", 13, 15, &umr_bitfield_default },
	 { "PTERM", 8, 11, &umr_bitfield_default },
	 { "QDR", 5, 5, &umr_bitfield_default },
	 { "TSTEN", 24, 24, &umr_bitfield_default },
	 { "TXBPASS_SEL", 12, 12, &umr_bitfield_default },
	 { "TXBYPASS_DATA", 27, 29, &umr_bitfield_default },
	 { "TXBYPASS", 26, 26, &umr_bitfield_default },
	 { "TXPD", 7, 7, &umr_bitfield_default },
	 { "TXRESET", 25, 25, &umr_bitfield_default },
	 { "YCLKON", 23, 23, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_IO_RXCNTL_DPHY0_D1[] = {
	 { "DLL_ADJ_B0", 20, 22, &umr_bitfield_default },
	 { "DLL_ADJ_B1", 24, 26, &umr_bitfield_default },
	 { "DLL_ADJ_M", 28, 28, &umr_bitfield_default },
	 { "DLL_BW_CTRL", 30, 31, &umr_bitfield_default },
	 { "RCVSEL", 2, 2, &umr_bitfield_default },
	 { "REFCLK_PWRON", 29, 29, &umr_bitfield_default },
	 { "RXBIASSEL", 0, 1, &umr_bitfield_default },
	 { "RXDPWRON_DLY", 4, 5, &umr_bitfield_default },
	 { "RXLP", 7, 7, &umr_bitfield_default },
	 { "RXPDNB", 6, 6, &umr_bitfield_default },
	 { "RX_PEAKSEL", 18, 19, &umr_bitfield_default },
	 { "VREFCAL", 8, 11, &umr_bitfield_default },
	 { "VREFCAL_STR", 12, 15, &umr_bitfield_default },
	 { "VREFPDNB", 3, 3, &umr_bitfield_default },
	 { "VREFSEL", 16, 16, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_IO_RXCNTL_DPHY1_D1[] = {
	 { "DLL_ADJ_B0", 20, 22, &umr_bitfield_default },
	 { "DLL_ADJ_B1", 24, 26, &umr_bitfield_default },
	 { "DLL_ADJ_M", 28, 28, &umr_bitfield_default },
	 { "DLL_BW_CTRL", 30, 31, &umr_bitfield_default },
	 { "RCVSEL", 2, 2, &umr_bitfield_default },
	 { "REFCLK_PWRON", 29, 29, &umr_bitfield_default },
	 { "RXBIASSEL", 0, 1, &umr_bitfield_default },
	 { "RXDPWRON_DLY", 4, 5, &umr_bitfield_default },
	 { "RXLP", 7, 7, &umr_bitfield_default },
	 { "RXPDNB", 6, 6, &umr_bitfield_default },
	 { "RX_PEAKSEL", 18, 19, &umr_bitfield_default },
	 { "VREFCAL", 8, 11, &umr_bitfield_default },
	 { "VREFCAL_STR", 12, 15, &umr_bitfield_default },
	 { "VREFPDNB", 3, 3, &umr_bitfield_default },
	 { "VREFSEL", 16, 16, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_IO_DPHY_STR_CNTL_D1[] = {
	 { "CAL_SEL", 26, 27, &umr_bitfield_default },
	 { "LOAD_D_STR", 28, 28, &umr_bitfield_default },
	 { "LOAD_S_STR", 29, 29, &umr_bitfield_default },
	 { "NSTR_OFF_D", 6, 11, &umr_bitfield_default },
	 { "NSTR_OFF_S", 18, 23, &umr_bitfield_default },
	 { "PSTR_OFF_D", 0, 5, &umr_bitfield_default },
	 { "PSTR_OFF_S", 12, 17, &umr_bitfield_default },
	 { "USE_D_CAL", 24, 24, &umr_bitfield_default },
	 { "USE_S_CAL", 25, 25, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_IO_CDRCNTL_D0[] = {
	 { "DQRXCDREN_B0", 22, 22, &umr_bitfield_default },
	 { "DQRXCDREN_B1", 23, 23, &umr_bitfield_default },
	 { "DQRXSEL_B0", 28, 28, &umr_bitfield_default },
	 { "DQRXSEL_B1", 29, 29, &umr_bitfield_default },
	 { "DQTXCDREN_B0", 20, 20, &umr_bitfield_default },
	 { "DQTXCDREN_B1", 21, 21, &umr_bitfield_default },
	 { "DQTXSEL_B0", 30, 30, &umr_bitfield_default },
	 { "DQTXSEL_B1", 31, 31, &umr_bitfield_default },
	 { "RXCDRBYPASS_B01", 10, 10, &umr_bitfield_default },
	 { "RXCDRBYPASS_B23", 11, 11, &umr_bitfield_default },
	 { "RXCDREN_B01", 8, 8, &umr_bitfield_default },
	 { "RXCDREN_B23", 9, 9, &umr_bitfield_default },
	 { "RXPHASE1_B01", 12, 15, &umr_bitfield_default },
	 { "RXPHASE1_B23", 16, 19, &umr_bitfield_default },
	 { "RXPHASE_B01", 0, 3, &umr_bitfield_default },
	 { "RXPHASE_B23", 4, 7, &umr_bitfield_default },
	 { "WCDREDC_B0", 26, 26, &umr_bitfield_default },
	 { "WCDREDC_B1", 27, 27, &umr_bitfield_default },
	 { "WCDRRXCDREN_B0", 24, 24, &umr_bitfield_default },
	 { "WCDRRXCDREN_B1", 25, 25, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_IO_CDRCNTL_D1[] = {
	 { "DQRXCDREN_B0", 22, 22, &umr_bitfield_default },
	 { "DQRXCDREN_B1", 23, 23, &umr_bitfield_default },
	 { "DQRXSEL_B0", 28, 28, &umr_bitfield_default },
	 { "DQRXSEL_B1", 29, 29, &umr_bitfield_default },
	 { "DQTXCDREN_B0", 20, 20, &umr_bitfield_default },
	 { "DQTXCDREN_B1", 21, 21, &umr_bitfield_default },
	 { "DQTXSEL_B0", 30, 30, &umr_bitfield_default },
	 { "DQTXSEL_B1", 31, 31, &umr_bitfield_default },
	 { "RXCDRBYPASS_B01", 10, 10, &umr_bitfield_default },
	 { "RXCDRBYPASS_B23", 11, 11, &umr_bitfield_default },
	 { "RXCDREN_B01", 8, 8, &umr_bitfield_default },
	 { "RXCDREN_B23", 9, 9, &umr_bitfield_default },
	 { "RXPHASE1_B01", 12, 15, &umr_bitfield_default },
	 { "RXPHASE1_B23", 16, 19, &umr_bitfield_default },
	 { "RXPHASE_B01", 0, 3, &umr_bitfield_default },
	 { "RXPHASE_B23", 4, 7, &umr_bitfield_default },
	 { "WCDREDC_B0", 26, 26, &umr_bitfield_default },
	 { "WCDREDC_B1", 27, 27, &umr_bitfield_default },
	 { "WCDRRXCDREN_B0", 24, 24, &umr_bitfield_default },
	 { "WCDRRXCDREN_B1", 25, 25, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_SEQ_FIFO_CTL[] = {
	 { "CG_DIS_D0", 8, 8, &umr_bitfield_default },
	 { "CG_DIS_D1", 9, 9, &umr_bitfield_default },
	 { "R_LD_INIT", 4, 5, &umr_bitfield_default },
	 { "R_SYC_SEL", 6, 7, &umr_bitfield_default },
	 { "SYC_DLY", 12, 14, &umr_bitfield_default },
	 { "W_ASYC_EXT", 16, 17, &umr_bitfield_default },
	 { "W_DSYC_EXT", 18, 19, &umr_bitfield_default },
	 { "W_LD_INIT_D0", 0, 1, &umr_bitfield_default },
	 { "W_LD_INIT_D1", 10, 11, &umr_bitfield_default },
	 { "W_SYC_SEL", 2, 3, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_SEQ_TXFRAMING_BYTE0_D0[] = {
	 { "DQ0", 0, 3, &umr_bitfield_default },
	 { "DQ1", 4, 7, &umr_bitfield_default },
	 { "DQ2", 8, 11, &umr_bitfield_default },
	 { "DQ3", 12, 15, &umr_bitfield_default },
	 { "DQ4", 16, 19, &umr_bitfield_default },
	 { "DQ5", 20, 23, &umr_bitfield_default },
	 { "DQ6", 24, 27, &umr_bitfield_default },
	 { "DQ7", 28, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_SEQ_TXFRAMING_BYTE1_D0[] = {
	 { "DQ0", 0, 3, &umr_bitfield_default },
	 { "DQ1", 4, 7, &umr_bitfield_default },
	 { "DQ2", 8, 11, &umr_bitfield_default },
	 { "DQ3", 12, 15, &umr_bitfield_default },
	 { "DQ4", 16, 19, &umr_bitfield_default },
	 { "DQ5", 20, 23, &umr_bitfield_default },
	 { "DQ6", 24, 27, &umr_bitfield_default },
	 { "DQ7", 28, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_SEQ_TXFRAMING_BYTE2_D0[] = {
	 { "DQ0", 0, 3, &umr_bitfield_default },
	 { "DQ1", 4, 7, &umr_bitfield_default },
	 { "DQ2", 8, 11, &umr_bitfield_default },
	 { "DQ3", 12, 15, &umr_bitfield_default },
	 { "DQ4", 16, 19, &umr_bitfield_default },
	 { "DQ5", 20, 23, &umr_bitfield_default },
	 { "DQ6", 24, 27, &umr_bitfield_default },
	 { "DQ7", 28, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_SEQ_TXFRAMING_BYTE3_D0[] = {
	 { "DQ0", 0, 3, &umr_bitfield_default },
	 { "DQ1", 4, 7, &umr_bitfield_default },
	 { "DQ2", 8, 11, &umr_bitfield_default },
	 { "DQ3", 12, 15, &umr_bitfield_default },
	 { "DQ4", 16, 19, &umr_bitfield_default },
	 { "DQ5", 20, 23, &umr_bitfield_default },
	 { "DQ6", 24, 27, &umr_bitfield_default },
	 { "DQ7", 28, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_SEQ_TXFRAMING_DBI_D0[] = {
	 { "DBI0", 0, 3, &umr_bitfield_default },
	 { "DBI1", 4, 7, &umr_bitfield_default },
	 { "DBI2", 8, 11, &umr_bitfield_default },
	 { "DBI3", 12, 15, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_SEQ_TXFRAMING_EDC_D0[] = {
	 { "EDC0", 0, 3, &umr_bitfield_default },
	 { "EDC1", 4, 7, &umr_bitfield_default },
	 { "EDC2", 8, 11, &umr_bitfield_default },
	 { "EDC3", 12, 15, &umr_bitfield_default },
	 { "WCDR0", 16, 19, &umr_bitfield_default },
	 { "WCDR1", 20, 23, &umr_bitfield_default },
	 { "WCDR2", 24, 27, &umr_bitfield_default },
	 { "WCDR3", 28, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_SEQ_TXFRAMING_FCK_D0[] = {
	 { "FCK0", 0, 3, &umr_bitfield_default },
	 { "FCK1", 4, 7, &umr_bitfield_default },
	 { "FCK2", 8, 11, &umr_bitfield_default },
	 { "FCK3", 12, 15, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_SEQ_MISC8[] = {
	 { "VALUE", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_SEQ_TXFRAMING_BYTE0_D1[] = {
	 { "DQ0", 0, 3, &umr_bitfield_default },
	 { "DQ1", 4, 7, &umr_bitfield_default },
	 { "DQ2", 8, 11, &umr_bitfield_default },
	 { "DQ3", 12, 15, &umr_bitfield_default },
	 { "DQ4", 16, 19, &umr_bitfield_default },
	 { "DQ5", 20, 23, &umr_bitfield_default },
	 { "DQ6", 24, 27, &umr_bitfield_default },
	 { "DQ7", 28, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_SEQ_TXFRAMING_BYTE1_D1[] = {
	 { "DQ0", 0, 3, &umr_bitfield_default },
	 { "DQ1", 4, 7, &umr_bitfield_default },
	 { "DQ2", 8, 11, &umr_bitfield_default },
	 { "DQ3", 12, 15, &umr_bitfield_default },
	 { "DQ4", 16, 19, &umr_bitfield_default },
	 { "DQ5", 20, 23, &umr_bitfield_default },
	 { "DQ6", 24, 27, &umr_bitfield_default },
	 { "DQ7", 28, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_SEQ_TXFRAMING_BYTE2_D1[] = {
	 { "DQ0", 0, 3, &umr_bitfield_default },
	 { "DQ1", 4, 7, &umr_bitfield_default },
	 { "DQ2", 8, 11, &umr_bitfield_default },
	 { "DQ3", 12, 15, &umr_bitfield_default },
	 { "DQ4", 16, 19, &umr_bitfield_default },
	 { "DQ5", 20, 23, &umr_bitfield_default },
	 { "DQ6", 24, 27, &umr_bitfield_default },
	 { "DQ7", 28, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_SEQ_TXFRAMING_BYTE3_D1[] = {
	 { "DQ0", 0, 3, &umr_bitfield_default },
	 { "DQ1", 4, 7, &umr_bitfield_default },
	 { "DQ2", 8, 11, &umr_bitfield_default },
	 { "DQ3", 12, 15, &umr_bitfield_default },
	 { "DQ4", 16, 19, &umr_bitfield_default },
	 { "DQ5", 20, 23, &umr_bitfield_default },
	 { "DQ6", 24, 27, &umr_bitfield_default },
	 { "DQ7", 28, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_SEQ_TXFRAMING_DBI_D1[] = {
	 { "DBI0", 0, 3, &umr_bitfield_default },
	 { "DBI1", 4, 7, &umr_bitfield_default },
	 { "DBI2", 8, 11, &umr_bitfield_default },
	 { "DBI3", 12, 15, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_SEQ_TXFRAMING_EDC_D1[] = {
	 { "EDC0", 0, 3, &umr_bitfield_default },
	 { "EDC1", 4, 7, &umr_bitfield_default },
	 { "EDC2", 8, 11, &umr_bitfield_default },
	 { "EDC3", 12, 15, &umr_bitfield_default },
	 { "WCDR0", 16, 19, &umr_bitfield_default },
	 { "WCDR1", 20, 23, &umr_bitfield_default },
	 { "WCDR2", 24, 27, &umr_bitfield_default },
	 { "WCDR3", 28, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_SEQ_TXFRAMING_FCK_D1[] = {
	 { "FCK0", 0, 3, &umr_bitfield_default },
	 { "FCK1", 4, 7, &umr_bitfield_default },
	 { "FCK2", 8, 11, &umr_bitfield_default },
	 { "FCK3", 12, 15, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_SEQ_RXFRAMING_BYTE0_D0[] = {
	 { "DQ0", 0, 3, &umr_bitfield_default },
	 { "DQ1", 4, 7, &umr_bitfield_default },
	 { "DQ2", 8, 11, &umr_bitfield_default },
	 { "DQ3", 12, 15, &umr_bitfield_default },
	 { "DQ4", 16, 19, &umr_bitfield_default },
	 { "DQ5", 20, 23, &umr_bitfield_default },
	 { "DQ6", 24, 27, &umr_bitfield_default },
	 { "DQ7", 28, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_SEQ_RXFRAMING_BYTE1_D0[] = {
	 { "DQ0", 0, 3, &umr_bitfield_default },
	 { "DQ1", 4, 7, &umr_bitfield_default },
	 { "DQ2", 8, 11, &umr_bitfield_default },
	 { "DQ3", 12, 15, &umr_bitfield_default },
	 { "DQ4", 16, 19, &umr_bitfield_default },
	 { "DQ5", 20, 23, &umr_bitfield_default },
	 { "DQ6", 24, 27, &umr_bitfield_default },
	 { "DQ7", 28, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_SEQ_RXFRAMING_BYTE2_D0[] = {
	 { "DQ0", 0, 3, &umr_bitfield_default },
	 { "DQ1", 4, 7, &umr_bitfield_default },
	 { "DQ2", 8, 11, &umr_bitfield_default },
	 { "DQ3", 12, 15, &umr_bitfield_default },
	 { "DQ4", 16, 19, &umr_bitfield_default },
	 { "DQ5", 20, 23, &umr_bitfield_default },
	 { "DQ6", 24, 27, &umr_bitfield_default },
	 { "DQ7", 28, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_SEQ_RXFRAMING_BYTE3_D0[] = {
	 { "DQ0", 0, 3, &umr_bitfield_default },
	 { "DQ1", 4, 7, &umr_bitfield_default },
	 { "DQ2", 8, 11, &umr_bitfield_default },
	 { "DQ3", 12, 15, &umr_bitfield_default },
	 { "DQ4", 16, 19, &umr_bitfield_default },
	 { "DQ5", 20, 23, &umr_bitfield_default },
	 { "DQ6", 24, 27, &umr_bitfield_default },
	 { "DQ7", 28, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_SEQ_RXFRAMING_DBI_D0[] = {
	 { "DBI0", 0, 3, &umr_bitfield_default },
	 { "DBI1", 4, 7, &umr_bitfield_default },
	 { "DBI2", 8, 11, &umr_bitfield_default },
	 { "DBI3", 12, 15, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_SEQ_RXFRAMING_EDC_D0[] = {
	 { "EDC0", 0, 3, &umr_bitfield_default },
	 { "EDC1", 4, 7, &umr_bitfield_default },
	 { "EDC2", 8, 11, &umr_bitfield_default },
	 { "EDC3", 12, 15, &umr_bitfield_default },
	 { "WCDR0", 16, 19, &umr_bitfield_default },
	 { "WCDR1", 20, 23, &umr_bitfield_default },
	 { "WCDR2", 24, 27, &umr_bitfield_default },
	 { "WCDR3", 28, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_SEQ_RXFRAMING_BYTE0_D1[] = {
	 { "DQ0", 0, 3, &umr_bitfield_default },
	 { "DQ1", 4, 7, &umr_bitfield_default },
	 { "DQ2", 8, 11, &umr_bitfield_default },
	 { "DQ3", 12, 15, &umr_bitfield_default },
	 { "DQ4", 16, 19, &umr_bitfield_default },
	 { "DQ5", 20, 23, &umr_bitfield_default },
	 { "DQ6", 24, 27, &umr_bitfield_default },
	 { "DQ7", 28, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_SEQ_RXFRAMING_BYTE1_D1[] = {
	 { "DQ0", 0, 3, &umr_bitfield_default },
	 { "DQ1", 4, 7, &umr_bitfield_default },
	 { "DQ2", 8, 11, &umr_bitfield_default },
	 { "DQ3", 12, 15, &umr_bitfield_default },
	 { "DQ4", 16, 19, &umr_bitfield_default },
	 { "DQ5", 20, 23, &umr_bitfield_default },
	 { "DQ6", 24, 27, &umr_bitfield_default },
	 { "DQ7", 28, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_SEQ_RXFRAMING_BYTE2_D1[] = {
	 { "DQ0", 0, 3, &umr_bitfield_default },
	 { "DQ1", 4, 7, &umr_bitfield_default },
	 { "DQ2", 8, 11, &umr_bitfield_default },
	 { "DQ3", 12, 15, &umr_bitfield_default },
	 { "DQ4", 16, 19, &umr_bitfield_default },
	 { "DQ5", 20, 23, &umr_bitfield_default },
	 { "DQ6", 24, 27, &umr_bitfield_default },
	 { "DQ7", 28, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_SEQ_RXFRAMING_BYTE3_D1[] = {
	 { "DQ0", 0, 3, &umr_bitfield_default },
	 { "DQ1", 4, 7, &umr_bitfield_default },
	 { "DQ2", 8, 11, &umr_bitfield_default },
	 { "DQ3", 12, 15, &umr_bitfield_default },
	 { "DQ4", 16, 19, &umr_bitfield_default },
	 { "DQ5", 20, 23, &umr_bitfield_default },
	 { "DQ6", 24, 27, &umr_bitfield_default },
	 { "DQ7", 28, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_SEQ_RXFRAMING_DBI_D1[] = {
	 { "DBI0", 0, 3, &umr_bitfield_default },
	 { "DBI1", 4, 7, &umr_bitfield_default },
	 { "DBI2", 8, 11, &umr_bitfield_default },
	 { "DBI3", 12, 15, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_SEQ_RXFRAMING_EDC_D1[] = {
	 { "EDC0", 0, 3, &umr_bitfield_default },
	 { "EDC1", 4, 7, &umr_bitfield_default },
	 { "EDC2", 8, 11, &umr_bitfield_default },
	 { "EDC3", 12, 15, &umr_bitfield_default },
	 { "WCDR0", 16, 19, &umr_bitfield_default },
	 { "WCDR1", 20, 23, &umr_bitfield_default },
	 { "WCDR2", 24, 27, &umr_bitfield_default },
	 { "WCDR3", 28, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_IO_PAD_CNTL[] = {
	 { "ATBEN", 24, 29, &umr_bitfield_default },
	 { "ATBSEL_D0", 31, 31, &umr_bitfield_default },
	 { "ATBSEL_D1", 30, 30, &umr_bitfield_default },
	 { "ATBSEL", 20, 23, &umr_bitfield_default },
	 { "MEM_IO_IMP_MAX", 8, 15, &umr_bitfield_default },
	 { "MEM_IO_IMP_MIN", 0, 7, &umr_bitfield_default },
	 { "OVL_YCLKON_D0", 18, 18, &umr_bitfield_default },
	 { "OVL_YCLKON_D1", 19, 19, &umr_bitfield_default },
	 { "RXPHASE_GRAY", 17, 17, &umr_bitfield_default },
	 { "TXPHASE_GRAY", 16, 16, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_IO_PAD_CNTL_D0[] = {
	 { "CK_AUTO_EN", 20, 20, &umr_bitfield_default },
	 { "CK_DELAY_N", 22, 23, &umr_bitfield_default },
	 { "CK_DELAY_P", 24, 25, &umr_bitfield_default },
	 { "CK_DELAY_SEL", 21, 21, &umr_bitfield_default },
	 { "DELAY_ADR_SYNC", 4, 4, &umr_bitfield_default },
	 { "DELAY_CLK_SYNC", 2, 2, &umr_bitfield_default },
	 { "DELAY_CMD_SYNC", 3, 3, &umr_bitfield_default },
	 { "DIFF_STR", 29, 29, &umr_bitfield_default },
	 { "DISABLE_ADR", 13, 13, &umr_bitfield_default },
	 { "DISABLE_CMD", 12, 12, &umr_bitfield_default },
	 { "EN_RD_STR_DLY", 11, 11, &umr_bitfield_default },
	 { "FORCE_EN_RD_STR", 10, 10, &umr_bitfield_default },
	 { "GDDR_PWRON", 30, 30, &umr_bitfield_default },
	 { "MEM_FALL_OUT_ADR", 9, 9, &umr_bitfield_default },
	 { "MEM_FALL_OUT_CLK", 7, 7, &umr_bitfield_default },
	 { "MEM_FALL_OUT_CMD", 8, 8, &umr_bitfield_default },
	 { "TXPWROFF_CKE", 27, 27, &umr_bitfield_default },
	 { "TXPWROFF_CLK", 31, 31, &umr_bitfield_default },
	 { "UNI_STR", 28, 28, &umr_bitfield_default },
	 { "VREFI_EN", 14, 14, &umr_bitfield_default },
	 { "VREFI_SEL", 15, 19, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_IO_PAD_CNTL_D1[] = {
	 { "CK_AUTO_EN", 20, 20, &umr_bitfield_default },
	 { "CK_DELAY_N", 22, 23, &umr_bitfield_default },
	 { "CK_DELAY_P", 24, 25, &umr_bitfield_default },
	 { "CK_DELAY_SEL", 21, 21, &umr_bitfield_default },
	 { "DELAY_ADR_SYNC", 4, 4, &umr_bitfield_default },
	 { "DELAY_CLK_SYNC", 2, 2, &umr_bitfield_default },
	 { "DELAY_CMD_SYNC", 3, 3, &umr_bitfield_default },
	 { "DELAY_DATA_SYNC", 0, 0, &umr_bitfield_default },
	 { "DELAY_STR_SYNC", 1, 1, &umr_bitfield_default },
	 { "DIFF_STR", 29, 29, &umr_bitfield_default },
	 { "DISABLE_ADR", 13, 13, &umr_bitfield_default },
	 { "DISABLE_CMD", 12, 12, &umr_bitfield_default },
	 { "EN_RD_STR_DLY", 11, 11, &umr_bitfield_default },
	 { "FORCE_EN_RD_STR", 10, 10, &umr_bitfield_default },
	 { "GDDR_PWRON", 30, 30, &umr_bitfield_default },
	 { "MEM_FALL_OUT_ADR", 9, 9, &umr_bitfield_default },
	 { "MEM_FALL_OUT_CLK", 7, 7, &umr_bitfield_default },
	 { "MEM_FALL_OUT_CMD", 8, 8, &umr_bitfield_default },
	 { "MEM_FALL_OUT_DATA", 5, 5, &umr_bitfield_default },
	 { "MEM_FALL_OUT_STR", 6, 6, &umr_bitfield_default },
	 { "TXPWROFF_CKE", 27, 27, &umr_bitfield_default },
	 { "TXPWROFF_CLK", 31, 31, &umr_bitfield_default },
	 { "UNI_STR", 28, 28, &umr_bitfield_default },
	 { "VREFI_EN", 14, 14, &umr_bitfield_default },
	 { "VREFI_SEL", 15, 19, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_NPL_STATUS[] = {
	 { "D0_NDELAY", 2, 3, &umr_bitfield_default },
	 { "D0_NEARLY", 5, 5, &umr_bitfield_default },
	 { "D0_PDELAY", 0, 1, &umr_bitfield_default },
	 { "D0_PEARLY", 4, 4, &umr_bitfield_default },
	 { "D1_NDELAY", 8, 9, &umr_bitfield_default },
	 { "D1_NEARLY", 11, 11, &umr_bitfield_default },
	 { "D1_PDELAY", 6, 7, &umr_bitfield_default },
	 { "D1_PEARLY", 10, 10, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_SEQ_PERF_CNTL[] = {
	 { "CNTL", 30, 31, &umr_bitfield_default },
	 { "MONITOR_PERIOD", 0, 29, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_SEQ_PERF_SEQ_CTL[] = {
	 { "SEL_A", 0, 3, &umr_bitfield_default },
	 { "SEL_B", 4, 7, &umr_bitfield_default },
	 { "SEL_CH0_C", 8, 11, &umr_bitfield_default },
	 { "SEL_CH0_D", 12, 15, &umr_bitfield_default },
	 { "SEL_CH1_A", 16, 19, &umr_bitfield_default },
	 { "SEL_CH1_B", 20, 23, &umr_bitfield_default },
	 { "SEL_CH1_C", 24, 27, &umr_bitfield_default },
	 { "SEL_CH1_D", 28, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_SEQ_PERF_SEQ_CNT_A_I0[] = {
	 { "VALUE", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_SEQ_PERF_SEQ_CNT_A_I1[] = {
	 { "VALUE", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_SEQ_PERF_SEQ_CNT_B_I0[] = {
	 { "VALUE", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_SEQ_PERF_SEQ_CNT_B_I1[] = {
	 { "VALUE", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_SEQ_STATUS_M[] = {
	 { "CMD_RDY_D0", 2, 2, &umr_bitfield_default },
	 { "CMD_RDY_D1", 3, 3, &umr_bitfield_default },
	 { "PMG_FSMSTATE", 20, 24, &umr_bitfield_default },
	 { "PMG_PWRSTATE", 16, 16, &umr_bitfield_default },
	 { "PWRUP_COMPL_D0", 0, 0, &umr_bitfield_default },
	 { "PWRUP_COMPL_D1", 1, 1, &umr_bitfield_default },
	 { "SEQ0_ARB_CMD_FIFO_EMPTY", 8, 8, &umr_bitfield_default },
	 { "SEQ0_BUSY_HYS", 25, 25, &umr_bitfield_default },
	 { "SEQ0_BUSY", 14, 14, &umr_bitfield_default },
	 { "SEQ0_RS_DATA_FIFO_FULL", 12, 12, &umr_bitfield_default },
	 { "SEQ1_ARB_CMD_FIFO_EMPTY", 9, 9, &umr_bitfield_default },
	 { "SEQ1_BUSY_HYS", 26, 26, &umr_bitfield_default },
	 { "SEQ1_BUSY", 15, 15, &umr_bitfield_default },
	 { "SEQ1_RS_DATA_FIFO_FULL", 13, 13, &umr_bitfield_default },
	 { "SLF_D0", 4, 4, &umr_bitfield_default },
	 { "SLF_D1", 5, 5, &umr_bitfield_default },
	 { "SS_SLF_D0", 6, 6, &umr_bitfield_default },
	 { "SS_SLF_D1", 7, 7, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_SEQ_VENDOR_ID_I0[] = {
	 { "VALUE", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_SEQ_VENDOR_ID_I1[] = {
	 { "VALUE", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_SEQ_MISC0[] = {
	 { "VALUE", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_SEQ_MISC1[] = {
	 { "VALUE", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_SEQ_RESERVE_M[] = {
	 { "MCLK_FIELD", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_PMG_CMD_EMRS[] = {
	 { "ADR", 0, 15, &umr_bitfield_default },
	 { "ADR_MSB0", 29, 29, &umr_bitfield_default },
	 { "ADR_MSB1", 28, 28, &umr_bitfield_default },
	 { "BNK_MSB", 19, 19, &umr_bitfield_default },
	 { "CSB", 21, 22, &umr_bitfield_default },
	 { "END", 20, 20, &umr_bitfield_default },
	 { "MOP", 16, 18, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_PMG_CFG[] = {
	 { "DPM_WAKE", 10, 10, &umr_bitfield_default },
	 { "EARLY_ACK_ACPI", 22, 22, &umr_bitfield_default },
	 { "MRS_WAIT_CNT", 16, 19, &umr_bitfield_default },
	 { "PREA_SRX", 13, 13, &umr_bitfield_default },
	 { "RFS_SRX", 12, 12, &umr_bitfield_default },
	 { "RST_EMRS", 2, 2, &umr_bitfield_default },
	 { "RST_MRS1", 8, 8, &umr_bitfield_default },
	 { "RST_MRS2", 9, 9, &umr_bitfield_default },
	 { "RST_MRS", 1, 1, &umr_bitfield_default },
	 { "RXPDNB", 25, 25, &umr_bitfield_default },
	 { "SYC_CLK", 0, 0, &umr_bitfield_default },
	 { "TRI_MIO", 3, 3, &umr_bitfield_default },
	 { "WRITE_DURING_DLOCK", 20, 20, &umr_bitfield_default },
	 { "XSR_TMR", 4, 7, &umr_bitfield_default },
	 { "YCLK_ON", 21, 21, &umr_bitfield_default },
	 { "ZQCL_SEND", 26, 27, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_SEQ_SUP_GP2_STAT[] = {
	 { "STATUS", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_SEQ_SUP_GP3_STAT[] = {
	 { "STATUS", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_SEQ_SUP_IR_STAT[] = {
	 { "STATUS", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_SEQ_SUP_DEC_STAT[] = {
	 { "STATUS", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_SEQ_SUP_PGM_STAT[] = {
	 { "STATUS", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_SEQ_SUP_R_PGM[] = {
	 { "PGM", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_SEQ_MISC3[] = {
	 { "VALUE", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_SEQ_MISC4[] = {
	 { "VALUE", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_BIST_CMP_CNTL[] = {
	 { "CMP", 16, 17, &umr_bitfield_default },
	 { "CMP_MASK_BIT", 4, 11, &umr_bitfield_default },
	 { "CMP_MASK_BYTE", 0, 3, &umr_bitfield_default },
	 { "DATA_STORE_MODE", 20, 21, &umr_bitfield_default },
	 { "DATA_STORE_SEL", 13, 13, &umr_bitfield_default },
	 { "DAT_MODE", 18, 18, &umr_bitfield_default },
	 { "EDC_STORE_MODE", 19, 19, &umr_bitfield_default },
	 { "EDC_STORE_SEL", 14, 14, &umr_bitfield_default },
	 { "ENABLE_CMD_FIFO", 15, 15, &umr_bitfield_default },
	 { "LOAD_RTEDC", 12, 12, &umr_bitfield_default },
	 { "MISMATCH_CNT", 22, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_BIST_CMD_CNTL[] = {
	 { "CMD_ISSUE_LOOP", 2, 2, &umr_bitfield_default },
	 { "CMD_ISSUE_MODE", 1, 1, &umr_bitfield_default },
	 { "CMD_ISSUE_MODE_U", 16, 16, &umr_bitfield_default },
	 { "CMD_ISSUE_RUN", 17, 17, &umr_bitfield_default },
	 { "DONE", 31, 31, &umr_bitfield_default },
	 { "ENABLE_D0", 28, 28, &umr_bitfield_default },
	 { "ENABLE_D1", 29, 29, &umr_bitfield_default },
	 { "LOOP_CNT_MAX", 4, 15, &umr_bitfield_default },
	 { "LOOP_CNT_RD", 18, 27, &umr_bitfield_default },
	 { "LOOP_END_CONDITION", 3, 3, &umr_bitfield_default },
	 { "RESET", 0, 0, &umr_bitfield_default },
	 { "STATUS_CH", 30, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_SEQ_SUP_GP0_STAT[] = {
	 { "STATUS", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_SEQ_SUP_GP1_STAT[] = {
	 { "STATUS", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_SEQ_IO_DEBUG_INDEX[] = {
	 { "IO_DEBUG_INDEX", 0, 8, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_SEQ_IO_DEBUG_DATA[] = {
	 { "IO_DEBUG_DATA", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_SEQ_BYTE_REMAP_D0[] = {
	 { "BYTE0", 0, 1, &umr_bitfield_default },
	 { "BYTE1", 2, 3, &umr_bitfield_default },
	 { "BYTE2", 4, 5, &umr_bitfield_default },
	 { "BYTE3", 6, 7, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_SEQ_BYTE_REMAP_D1[] = {
	 { "BYTE0", 0, 1, &umr_bitfield_default },
	 { "BYTE1", 2, 3, &umr_bitfield_default },
	 { "BYTE2", 4, 5, &umr_bitfield_default },
	 { "BYTE3", 6, 7, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_SEQ_MISC5[] = {
	 { "VALUE", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_SEQ_MISC6[] = {
	 { "VALUE", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_IO_APHY_STR_CNTL_D0[] = {
	 { "CAL_SEL", 26, 27, &umr_bitfield_default },
	 { "LOAD_A_STR", 28, 28, &umr_bitfield_default },
	 { "LOAD_D_RD_STR", 29, 29, &umr_bitfield_default },
	 { "NSTR_OFF_A", 6, 11, &umr_bitfield_default },
	 { "PSTR_OFF_A", 0, 5, &umr_bitfield_default },
	 { "PSTR_OFF_D_RD", 12, 17, &umr_bitfield_default },
	 { "USE_A_CAL", 24, 24, &umr_bitfield_default },
	 { "USE_D_RD_CAL", 25, 25, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_IO_APHY_STR_CNTL_D1[] = {
	 { "CAL_SEL", 26, 27, &umr_bitfield_default },
	 { "LOAD_A_STR", 28, 28, &umr_bitfield_default },
	 { "LOAD_D_RD_STR", 29, 29, &umr_bitfield_default },
	 { "NSTR_OFF_A", 6, 11, &umr_bitfield_default },
	 { "PSTR_OFF_A", 0, 5, &umr_bitfield_default },
	 { "PSTR_OFF_D_RD", 12, 17, &umr_bitfield_default },
	 { "USE_A_CAL", 24, 24, &umr_bitfield_default },
	 { "USE_D_RD_CAL", 25, 25, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_SEQ_MISC7[] = {
	 { "VALUE", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_SEQ_CG[] = {
	 { "CG_SEQ_REQ", 0, 7, &umr_bitfield_default },
	 { "CG_SEQ_RESP", 8, 15, &umr_bitfield_default },
	 { "SEQ_CG_REQ", 16, 23, &umr_bitfield_default },
	 { "SEQ_CG_RESP", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_SEQ_RAS_TIMING_LP[] = {
	 { "TRCDRA", 15, 19, &umr_bitfield_default },
	 { "TRCDR", 10, 14, &umr_bitfield_default },
	 { "TRCDWA", 5, 9, &umr_bitfield_default },
	 { "TRCDW", 0, 4, &umr_bitfield_default },
	 { "TRC", 24, 30, &umr_bitfield_default },
	 { "TRRD", 20, 23, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_SEQ_CAS_TIMING_LP[] = {
	 { "TCCDL", 9, 11, &umr_bitfield_default },
	 { "TCL", 24, 28, &umr_bitfield_default },
	 { "TNOPR", 2, 3, &umr_bitfield_default },
	 { "TNOPW", 0, 1, &umr_bitfield_default },
	 { "TR2R", 12, 15, &umr_bitfield_default },
	 { "TR2W", 4, 8, &umr_bitfield_default },
	 { "TW2R", 16, 20, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_SEQ_MISC_TIMING_LP[] = {
	 { "TRFC", 20, 28, &umr_bitfield_default },
	 { "TRP", 15, 19, &umr_bitfield_default },
	 { "TRP_RDA", 8, 13, &umr_bitfield_default },
	 { "TRP_WRA", 0, 5, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_SEQ_MISC_TIMING2_LP[] = {
	 { "FAW", 8, 12, &umr_bitfield_default },
	 { "PA2RDATA", 0, 2, &umr_bitfield_default },
	 { "PA2WDATA", 4, 6, &umr_bitfield_default },
	 { "TADR", 21, 23, &umr_bitfield_default },
	 { "TFCKTR", 24, 27, &umr_bitfield_default },
	 { "TREDC", 13, 15, &umr_bitfield_default },
	 { "TWDATATR", 28, 31, &umr_bitfield_default },
	 { "TWEDC", 16, 20, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_SEQ_WR_CTL_D0_LP[] = {
	 { "ADR_2Y_DLY", 10, 10, &umr_bitfield_default },
	 { "ADR_DLY", 29, 29, &umr_bitfield_default },
	 { "CMD_2Y_DLY", 11, 11, &umr_bitfield_default },
	 { "CMD_DLY", 30, 30, &umr_bitfield_default },
	 { "DAT_2Y_DLY", 9, 9, &umr_bitfield_default },
	 { "DAT_DLY", 0, 3, &umr_bitfield_default },
	 { "DQS_DLY", 4, 7, &umr_bitfield_default },
	 { "DQS_XTR", 8, 8, &umr_bitfield_default },
	 { "ODT_DLY", 24, 27, &umr_bitfield_default },
	 { "ODT_EXT", 28, 28, &umr_bitfield_default },
	 { "OEN_DLY", 12, 15, &umr_bitfield_default },
	 { "OEN_EXT", 16, 19, &umr_bitfield_default },
	 { "OEN_SEL", 20, 21, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_SEQ_WR_CTL_D1_LP[] = {
	 { "ADR_2Y_DLY", 10, 10, &umr_bitfield_default },
	 { "ADR_DLY", 29, 29, &umr_bitfield_default },
	 { "CMD_2Y_DLY", 11, 11, &umr_bitfield_default },
	 { "CMD_DLY", 30, 30, &umr_bitfield_default },
	 { "DAT_2Y_DLY", 9, 9, &umr_bitfield_default },
	 { "DAT_DLY", 0, 3, &umr_bitfield_default },
	 { "DQS_DLY", 4, 7, &umr_bitfield_default },
	 { "DQS_XTR", 8, 8, &umr_bitfield_default },
	 { "ODT_DLY", 24, 27, &umr_bitfield_default },
	 { "ODT_EXT", 28, 28, &umr_bitfield_default },
	 { "OEN_DLY", 12, 15, &umr_bitfield_default },
	 { "OEN_EXT", 16, 19, &umr_bitfield_default },
	 { "OEN_SEL", 20, 21, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_SEQ_PMG_CMD_EMRS_LP[] = {
	 { "ADR", 0, 15, &umr_bitfield_default },
	 { "ADR_MSB0", 29, 29, &umr_bitfield_default },
	 { "ADR_MSB1", 28, 28, &umr_bitfield_default },
	 { "BNK_MSB", 19, 19, &umr_bitfield_default },
	 { "CSB", 21, 22, &umr_bitfield_default },
	 { "END", 20, 20, &umr_bitfield_default },
	 { "MOP", 16, 18, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_SEQ_PMG_CMD_MRS_LP[] = {
	 { "ADR", 0, 15, &umr_bitfield_default },
	 { "ADR_MSB0", 29, 29, &umr_bitfield_default },
	 { "ADR_MSB1", 28, 28, &umr_bitfield_default },
	 { "BNK_MSB", 19, 19, &umr_bitfield_default },
	 { "CSB", 21, 22, &umr_bitfield_default },
	 { "END", 20, 20, &umr_bitfield_default },
	 { "MOP", 16, 18, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_SEQ_BIT_REMAP_B0_D0[] = {
	 { "BIT0", 0, 2, &umr_bitfield_default },
	 { "BIT1", 3, 5, &umr_bitfield_default },
	 { "BIT2", 6, 8, &umr_bitfield_default },
	 { "BIT3", 9, 11, &umr_bitfield_default },
	 { "BIT4", 12, 14, &umr_bitfield_default },
	 { "BIT5", 15, 17, &umr_bitfield_default },
	 { "BIT6", 18, 20, &umr_bitfield_default },
	 { "BIT7", 21, 23, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_SEQ_BIT_REMAP_B1_D0[] = {
	 { "BIT0", 0, 2, &umr_bitfield_default },
	 { "BIT1", 3, 5, &umr_bitfield_default },
	 { "BIT2", 6, 8, &umr_bitfield_default },
	 { "BIT3", 9, 11, &umr_bitfield_default },
	 { "BIT4", 12, 14, &umr_bitfield_default },
	 { "BIT5", 15, 17, &umr_bitfield_default },
	 { "BIT6", 18, 20, &umr_bitfield_default },
	 { "BIT7", 21, 23, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_SEQ_BIT_REMAP_B2_D0[] = {
	 { "BIT0", 0, 2, &umr_bitfield_default },
	 { "BIT1", 3, 5, &umr_bitfield_default },
	 { "BIT2", 6, 8, &umr_bitfield_default },
	 { "BIT3", 9, 11, &umr_bitfield_default },
	 { "BIT4", 12, 14, &umr_bitfield_default },
	 { "BIT5", 15, 17, &umr_bitfield_default },
	 { "BIT6", 18, 20, &umr_bitfield_default },
	 { "BIT7", 21, 23, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_SEQ_BIT_REMAP_B3_D0[] = {
	 { "BIT0", 0, 2, &umr_bitfield_default },
	 { "BIT1", 3, 5, &umr_bitfield_default },
	 { "BIT2", 6, 8, &umr_bitfield_default },
	 { "BIT3", 9, 11, &umr_bitfield_default },
	 { "BIT4", 12, 14, &umr_bitfield_default },
	 { "BIT5", 15, 17, &umr_bitfield_default },
	 { "BIT6", 18, 20, &umr_bitfield_default },
	 { "BIT7", 21, 23, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_SEQ_BIT_REMAP_B0_D1[] = {
	 { "BIT0", 0, 2, &umr_bitfield_default },
	 { "BIT1", 3, 5, &umr_bitfield_default },
	 { "BIT2", 6, 8, &umr_bitfield_default },
	 { "BIT3", 9, 11, &umr_bitfield_default },
	 { "BIT4", 12, 14, &umr_bitfield_default },
	 { "BIT5", 15, 17, &umr_bitfield_default },
	 { "BIT6", 18, 20, &umr_bitfield_default },
	 { "BIT7", 21, 23, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_SEQ_BIT_REMAP_B1_D1[] = {
	 { "BIT0", 0, 2, &umr_bitfield_default },
	 { "BIT1", 3, 5, &umr_bitfield_default },
	 { "BIT2", 6, 8, &umr_bitfield_default },
	 { "BIT3", 9, 11, &umr_bitfield_default },
	 { "BIT4", 12, 14, &umr_bitfield_default },
	 { "BIT5", 15, 17, &umr_bitfield_default },
	 { "BIT6", 18, 20, &umr_bitfield_default },
	 { "BIT7", 21, 23, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_SEQ_BIT_REMAP_B2_D1[] = {
	 { "BIT0", 0, 2, &umr_bitfield_default },
	 { "BIT1", 3, 5, &umr_bitfield_default },
	 { "BIT2", 6, 8, &umr_bitfield_default },
	 { "BIT3", 9, 11, &umr_bitfield_default },
	 { "BIT4", 12, 14, &umr_bitfield_default },
	 { "BIT5", 15, 17, &umr_bitfield_default },
	 { "BIT6", 18, 20, &umr_bitfield_default },
	 { "BIT7", 21, 23, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_SEQ_BIT_REMAP_B3_D1[] = {
	 { "BIT0", 0, 2, &umr_bitfield_default },
	 { "BIT1", 3, 5, &umr_bitfield_default },
	 { "BIT2", 6, 8, &umr_bitfield_default },
	 { "BIT3", 9, 11, &umr_bitfield_default },
	 { "BIT4", 12, 14, &umr_bitfield_default },
	 { "BIT5", 15, 17, &umr_bitfield_default },
	 { "BIT6", 18, 20, &umr_bitfield_default },
	 { "BIT7", 21, 23, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_PMG_CMD_MRS[] = {
	 { "ADR", 0, 15, &umr_bitfield_default },
	 { "ADR_MSB0", 29, 29, &umr_bitfield_default },
	 { "ADR_MSB1", 28, 28, &umr_bitfield_default },
	 { "BNK_MSB", 19, 19, &umr_bitfield_default },
	 { "CSB", 21, 22, &umr_bitfield_default },
	 { "END", 20, 20, &umr_bitfield_default },
	 { "MOP", 16, 18, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_SEQ_IO_RWORD0[] = {
	 { "RDATA", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_SEQ_IO_RWORD1[] = {
	 { "RDATA", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_SEQ_IO_RWORD2[] = {
	 { "RDATA", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_SEQ_IO_RWORD3[] = {
	 { "RDATA", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_SEQ_IO_RWORD4[] = {
	 { "RDATA", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_SEQ_IO_RWORD5[] = {
	 { "RDATA", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_SEQ_IO_RWORD6[] = {
	 { "RDATA", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_SEQ_IO_RWORD7[] = {
	 { "RDATA", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_SEQ_IO_RDBI[] = {
	 { "MASK", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_SEQ_IO_REDC[] = {
	 { "EDC", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_BIST_CMP_CNTL_2[] = {
	 { "DATA_STORE_CNT", 0, 4, &umr_bitfield_default },
	 { "DATA_STORE_CNT_RST", 8, 8, &umr_bitfield_default },
	 { "EDC_STORE_CNT", 12, 16, &umr_bitfield_default },
	 { "EDC_STORE_CNT_RST", 20, 20, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_SEQ_IO_RESERVE_D0[] = {
	 { "APHY_RSV", 24, 31, &umr_bitfield_default },
	 { "DPHY0_RSV", 0, 11, &umr_bitfield_default },
	 { "DPHY1_RSV", 12, 23, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_SEQ_IO_RESERVE_D1[] = {
	 { "APHY_RSV", 24, 31, &umr_bitfield_default },
	 { "DPHY0_RSV", 0, 11, &umr_bitfield_default },
	 { "DPHY1_RSV", 12, 23, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_SEQ_PMG_PG_HWCNTL[] = {
	 { "ACAO", 18, 18, &umr_bitfield_default },
	 { "AC_DLY", 8, 9, &umr_bitfield_default },
	 { "D_DLY", 6, 7, &umr_bitfield_default },
	 { "G_DLY", 10, 13, &umr_bitfield_default },
	 { "PWRGATE_EN", 0, 0, &umr_bitfield_default },
	 { "RXAO", 17, 17, &umr_bitfield_default },
	 { "STAGGER_EN", 1, 1, &umr_bitfield_default },
	 { "TPGCG", 2, 5, &umr_bitfield_default },
	 { "TXAO", 16, 16, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_SEQ_PMG_PG_SWCNTL_0[] = {
	 { "GMCON_SR_COMMIT", 31, 31, &umr_bitfield_default },
	 { "PMA0_AC_ENB", 16, 16, &umr_bitfield_default },
	 { "PMD0_DBI_RX_ENB", 5, 5, &umr_bitfield_default },
	 { "PMD0_DBI_TX_ENB", 1, 1, &umr_bitfield_default },
	 { "PMD0_DQ_RX_ENB", 4, 4, &umr_bitfield_default },
	 { "PMD0_DQ_TX_ENB", 0, 0, &umr_bitfield_default },
	 { "PMD0_EDC_RX_ENB", 6, 6, &umr_bitfield_default },
	 { "PMD0_EDC_TX_ENB", 2, 2, &umr_bitfield_default },
	 { "PMD0_WCLKX_RX_ENB", 7, 7, &umr_bitfield_default },
	 { "PMD0_WCLKX_TX_ENB", 3, 3, &umr_bitfield_default },
	 { "PMD1_DBI_RX_ENB", 13, 13, &umr_bitfield_default },
	 { "PMD1_DBI_TX_ENB", 9, 9, &umr_bitfield_default },
	 { "PMD1_DQ_RX_ENB", 12, 12, &umr_bitfield_default },
	 { "PMD1_DQ_TX_ENB", 8, 8, &umr_bitfield_default },
	 { "PMD1_EDC_RX_ENB", 14, 14, &umr_bitfield_default },
	 { "PMD1_EDC_TX_ENB", 10, 10, &umr_bitfield_default },
	 { "PMD1_WCLKX_RX_ENB", 15, 15, &umr_bitfield_default },
	 { "PMD1_WCLKX_TX_ENB", 11, 11, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_SEQ_PMG_PG_SWCNTL_1[] = {
	 { "GMCON_SR_COMMIT", 31, 31, &umr_bitfield_default },
	 { "PMA1_AC_ENB", 16, 16, &umr_bitfield_default },
	 { "PMD2_DBI_RX_ENB", 5, 5, &umr_bitfield_default },
	 { "PMD2_DBI_TX_ENB", 1, 1, &umr_bitfield_default },
	 { "PMD2_DQ_RX_ENB", 4, 4, &umr_bitfield_default },
	 { "PMD2_DQ_TX_ENB", 0, 0, &umr_bitfield_default },
	 { "PMD2_EDC_RX_ENB", 6, 6, &umr_bitfield_default },
	 { "PMD2_EDC_TX_ENB", 2, 2, &umr_bitfield_default },
	 { "PMD2_WCLKX_RX_ENB", 7, 7, &umr_bitfield_default },
	 { "PMD2_WCLKX_TX_ENB", 3, 3, &umr_bitfield_default },
	 { "PMD3_DBI_RX_ENB", 13, 13, &umr_bitfield_default },
	 { "PMD3_DBI_TX_ENB", 9, 9, &umr_bitfield_default },
	 { "PMD3_DQ_RX_ENB", 12, 12, &umr_bitfield_default },
	 { "PMD3_DQ_TX_ENB", 8, 8, &umr_bitfield_default },
	 { "PMD3_EDC_RX_ENB", 14, 14, &umr_bitfield_default },
	 { "PMD3_EDC_TX_ENB", 10, 10, &umr_bitfield_default },
	 { "PMD3_WCLKX_RX_ENB", 15, 15, &umr_bitfield_default },
	 { "PMD3_WCLKX_TX_ENB", 11, 11, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_IMP_DQ_STATUS[] = {
	 { "CH0_DQ_NSTR", 8, 15, &umr_bitfield_default },
	 { "CH0_DQ_PSTR", 0, 7, &umr_bitfield_default },
	 { "CH1_DQ_NSTR", 24, 31, &umr_bitfield_default },
	 { "CH1_DQ_PSTR", 16, 23, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_SEQ_TCG_CNTL[] = {
	 { "AREF_BOTH", 26, 26, &umr_bitfield_default },
	 { "AREF_LAST", 25, 25, &umr_bitfield_default },
	 { "BURST_NUM", 19, 21, &umr_bitfield_default },
	 { "DATA_CNT", 12, 15, &umr_bitfield_default },
	 { "DONE", 31, 31, &umr_bitfield_default },
	 { "ENABLE_D0", 1, 1, &umr_bitfield_default },
	 { "ENABLE_D1", 2, 2, &umr_bitfield_default },
	 { "FRAME_TRAIN", 18, 18, &umr_bitfield_default },
	 { "INFINITE_CMD", 7, 7, &umr_bitfield_default },
	 { "ISSUE_AREF", 22, 22, &umr_bitfield_default },
	 { "LOAD_FIFO", 16, 16, &umr_bitfield_default },
	 { "MOP", 8, 11, &umr_bitfield_default },
	 { "NFIFO", 4, 6, &umr_bitfield_default },
	 { "RESET", 0, 0, &umr_bitfield_default },
	 { "SHORT_LDFF", 17, 17, &umr_bitfield_default },
	 { "START", 3, 3, &umr_bitfield_default },
	 { "TXDBI_CNTL", 23, 23, &umr_bitfield_default },
	 { "VPTR_MASK", 24, 24, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_SEQ_TSM_CTRL[] = {
	 { "CAPTURE_START", 1, 1, &umr_bitfield_default },
	 { "DIRECTION", 5, 5, &umr_bitfield_default },
	 { "DONE", 2, 2, &umr_bitfield_default },
	 { "ERR", 3, 3, &umr_bitfield_default },
	 { "INVERT", 6, 6, &umr_bitfield_default },
	 { "MASK_BITS", 7, 7, &umr_bitfield_default },
	 { "POINTER", 16, 31, &umr_bitfield_default },
	 { "ROT_INV", 10, 10, &umr_bitfield_default },
	 { "START", 0, 0, &umr_bitfield_default },
	 { "STEP", 4, 4, &umr_bitfield_default },
	 { "UPDATE_LOOP", 8, 9, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_SEQ_TSM_GCNT[] = {
	 { "COMP_VALUE", 16, 31, &umr_bitfield_default },
	 { "FALSE_ACT", 4, 7, &umr_bitfield_default },
	 { "TESTS", 8, 15, &umr_bitfield_default },
	 { "TRUE_ACT", 0, 3, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_SEQ_TSM_OCNT[] = {
	 { "CMP_VALUE", 16, 31, &umr_bitfield_default },
	 { "FALSE_ACT", 4, 7, &umr_bitfield_default },
	 { "TESTS", 8, 15, &umr_bitfield_default },
	 { "TRUE_ACT", 0, 3, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_SEQ_TSM_NCNT[] = {
	 { "FALSE_ACT", 4, 7, &umr_bitfield_default },
	 { "NIBBLE_SKIP", 24, 27, &umr_bitfield_default },
	 { "RANGE_HIGH", 20, 23, &umr_bitfield_default },
	 { "RANGE_LOW", 16, 19, &umr_bitfield_default },
	 { "TESTS", 8, 15, &umr_bitfield_default },
	 { "TRUE_ACT", 0, 3, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_SEQ_TSM_BCNT[] = {
	 { "BCNT_TESTS", 8, 15, &umr_bitfield_default },
	 { "COMP_VALUE", 16, 23, &umr_bitfield_default },
	 { "DONE_TESTS", 24, 31, &umr_bitfield_default },
	 { "FALSE_ACT", 4, 7, &umr_bitfield_default },
	 { "TRUE_ACT", 0, 3, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_SEQ_TSM_FLAG[] = {
	 { "ERROR_TESTS", 24, 31, &umr_bitfield_default },
	 { "FALSE_ACT", 4, 7, &umr_bitfield_default },
	 { "FLAG_TESTS", 8, 15, &umr_bitfield_default },
	 { "NBBL_MASK", 16, 19, &umr_bitfield_default },
	 { "TRUE_ACT", 0, 3, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_SEQ_TSM_UPDATE[] = {
	 { "AREF_COUNT", 16, 23, &umr_bitfield_default },
	 { "CAPTR_TESTS", 24, 31, &umr_bitfield_default },
	 { "FALSE_ACT", 4, 7, &umr_bitfield_default },
	 { "TRUE_ACT", 0, 3, &umr_bitfield_default },
	 { "UPDT_TESTS", 8, 15, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_SEQ_TSM_EDC[] = {
	 { "EDC", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_SEQ_TSM_DBI[] = {
	 { "DBI", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_SEQ_RD_CTL_D0_LP[] = {
	 { "RBS_DLY", 20, 24, &umr_bitfield_default },
	 { "RBS_WEDC_DLY", 25, 29, &umr_bitfield_default },
	 { "RCV_DLY", 0, 2, &umr_bitfield_default },
	 { "RCV_EXT", 3, 7, &umr_bitfield_default },
	 { "RST_HLD", 12, 15, &umr_bitfield_default },
	 { "RST_SEL", 8, 9, &umr_bitfield_default },
	 { "RXDPWRON_DLY", 10, 11, &umr_bitfield_default },
	 { "STR_PRE", 16, 16, &umr_bitfield_default },
	 { "STR_PST", 17, 17, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_SEQ_RD_CTL_D1_LP[] = {
	 { "RBS_DLY", 20, 24, &umr_bitfield_default },
	 { "RBS_WEDC_DLY", 25, 29, &umr_bitfield_default },
	 { "RCV_DLY", 0, 2, &umr_bitfield_default },
	 { "RCV_EXT", 3, 7, &umr_bitfield_default },
	 { "RST_HLD", 12, 15, &umr_bitfield_default },
	 { "RST_SEL", 8, 9, &umr_bitfield_default },
	 { "RXDPWRON_DLY", 10, 11, &umr_bitfield_default },
	 { "STR_PRE", 16, 16, &umr_bitfield_default },
	 { "STR_PST", 17, 17, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_SEQ_TIMER_WR[] = {
	 { "COUNTER", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_SEQ_TIMER_RD[] = {
	 { "COUNTER", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_SEQ_DRAM_ERROR_INSERTION[] = {
	 { "RX", 16, 31, &umr_bitfield_default },
	 { "TX", 0, 15, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_PHY_TIMING_D0[] = {
	 { "RXC0_DLY", 0, 3, &umr_bitfield_default },
	 { "RXC0_EXT", 4, 7, &umr_bitfield_default },
	 { "RXC1_DLY", 8, 11, &umr_bitfield_default },
	 { "RXC1_EXT", 12, 15, &umr_bitfield_default },
	 { "TXC0_DLY", 16, 18, &umr_bitfield_default },
	 { "TXC0_EXT", 20, 23, &umr_bitfield_default },
	 { "TXC1_DLY", 24, 26, &umr_bitfield_default },
	 { "TXC1_EXT", 28, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_PHY_TIMING_D1[] = {
	 { "RXC0_DLY", 0, 3, &umr_bitfield_default },
	 { "RXC0_EXT", 4, 7, &umr_bitfield_default },
	 { "RXC1_DLY", 8, 11, &umr_bitfield_default },
	 { "RXC1_EXT", 12, 15, &umr_bitfield_default },
	 { "TXC0_DLY", 16, 18, &umr_bitfield_default },
	 { "TXC0_EXT", 20, 23, &umr_bitfield_default },
	 { "TXC1_DLY", 24, 26, &umr_bitfield_default },
	 { "TXC1_EXT", 28, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_PHY_TIMING_2[] = {
	 { "ADR_CLKEN_D0", 18, 18, &umr_bitfield_default },
	 { "ADR_CLKEN_D1", 19, 19, &umr_bitfield_default },
	 { "IND_LD_CNT", 0, 6, &umr_bitfield_default },
	 { "RXC0_FRC", 12, 12, &umr_bitfield_default },
	 { "RXC0_INV", 8, 8, &umr_bitfield_default },
	 { "RXC1_FRC", 13, 13, &umr_bitfield_default },
	 { "RXC1_INV", 9, 9, &umr_bitfield_default },
	 { "TXC0_FRC", 14, 14, &umr_bitfield_default },
	 { "TXC0_INV", 10, 10, &umr_bitfield_default },
	 { "TXC1_FRC", 15, 15, &umr_bitfield_default },
	 { "TXC1_INV", 11, 11, &umr_bitfield_default },
	 { "TX_CDREN_D0", 16, 16, &umr_bitfield_default },
	 { "TX_CDREN_D1", 17, 17, &umr_bitfield_default },
	 { "WR_DLY", 20, 23, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_SEQ_TSM_DEBUG_INDEX[] = {
	 { "TSM_DEBUG_INDEX", 0, 4, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_SEQ_TSM_DEBUG_DATA[] = {
	 { "TSM_DEBUG_DATA", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_PMG_CMD_MRS1[] = {
	 { "ADR", 0, 15, &umr_bitfield_default },
	 { "ADR_MSB0", 29, 29, &umr_bitfield_default },
	 { "ADR_MSB1", 28, 28, &umr_bitfield_default },
	 { "BNK_MSB", 19, 19, &umr_bitfield_default },
	 { "CSB", 21, 22, &umr_bitfield_default },
	 { "END", 20, 20, &umr_bitfield_default },
	 { "MOP", 16, 18, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_SEQ_PMG_CMD_MRS1_LP[] = {
	 { "ADR", 0, 15, &umr_bitfield_default },
	 { "ADR_MSB0", 29, 29, &umr_bitfield_default },
	 { "ADR_MSB1", 28, 28, &umr_bitfield_default },
	 { "BNK_MSB", 19, 19, &umr_bitfield_default },
	 { "CSB", 21, 22, &umr_bitfield_default },
	 { "END", 20, 20, &umr_bitfield_default },
	 { "MOP", 16, 18, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_SEQ_PMG_TIMING_LP[] = {
	 { "SEQ_IDLE", 18, 20, &umr_bitfield_default },
	 { "SEQ_IDLE_SS", 24, 31, &umr_bitfield_default },
	 { "TCKE", 12, 17, &umr_bitfield_default },
	 { "TCKE_PULSE", 8, 11, &umr_bitfield_default },
	 { "TCKE_PULSE_MSB", 23, 23, &umr_bitfield_default },
	 { "TCKSRE", 0, 2, &umr_bitfield_default },
	 { "TCKSRX", 4, 6, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_SEQ_CNTL_2[] = {
	 { "ARB_RTDAT_WMK_MSB", 8, 9, &umr_bitfield_default },
	 { "DRST_NSTR", 10, 15, &umr_bitfield_default },
	 { "DRST_PSTR", 16, 21, &umr_bitfield_default },
	 { "PLL_RX_PWRON_D0", 24, 27, &umr_bitfield_default },
	 { "PLL_RX_PWRON_D1", 28, 31, &umr_bitfield_default },
	 { "PLL_TX_PWRON_D0", 22, 22, &umr_bitfield_default },
	 { "PLL_TX_PWRON_D1", 23, 23, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_SEQ_WR_CTL_2[] = {
	 { "DAT_DLY_H_D0", 0, 0, &umr_bitfield_default },
	 { "DAT_DLY_H_D1", 3, 3, &umr_bitfield_default },
	 { "DQS_DLY_H_D0", 1, 1, &umr_bitfield_default },
	 { "DQS_DLY_H_D1", 4, 4, &umr_bitfield_default },
	 { "OEN_DLY_H_D0", 2, 2, &umr_bitfield_default },
	 { "OEN_DLY_H_D1", 5, 5, &umr_bitfield_default },
	 { "WCDR_EN", 6, 6, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_SEQ_WR_CTL_2_LP[] = {
	 { "DAT_DLY_H_D0", 0, 0, &umr_bitfield_default },
	 { "DAT_DLY_H_D1", 3, 3, &umr_bitfield_default },
	 { "DQS_DLY_H_D0", 1, 1, &umr_bitfield_default },
	 { "DQS_DLY_H_D1", 4, 4, &umr_bitfield_default },
	 { "OEN_DLY_H_D0", 2, 2, &umr_bitfield_default },
	 { "OEN_DLY_H_D1", 5, 5, &umr_bitfield_default },
	 { "WCDR_EN", 6, 6, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_PMG_CMD_MRS2[] = {
	 { "ADR", 0, 15, &umr_bitfield_default },
	 { "ADR_MSB0", 29, 29, &umr_bitfield_default },
	 { "ADR_MSB1", 28, 28, &umr_bitfield_default },
	 { "BNK_MSB", 19, 19, &umr_bitfield_default },
	 { "CSB", 21, 22, &umr_bitfield_default },
	 { "END", 20, 20, &umr_bitfield_default },
	 { "MOP", 16, 18, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_SEQ_PMG_CMD_MRS2_LP[] = {
	 { "ADR", 0, 15, &umr_bitfield_default },
	 { "ADR_MSB0", 29, 29, &umr_bitfield_default },
	 { "ADR_MSB1", 28, 28, &umr_bitfield_default },
	 { "BNK_MSB", 19, 19, &umr_bitfield_default },
	 { "CSB", 21, 22, &umr_bitfield_default },
	 { "END", 20, 20, &umr_bitfield_default },
	 { "MOP", 16, 18, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_SEQ_PERF_SEQ_CNT_C_I0[] = {
	 { "VALUE", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_SEQ_PERF_SEQ_CNT_C_I1[] = {
	 { "VALUE", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_SEQ_PERF_SEQ_CNT_D_I0[] = {
	 { "VALUE", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_SEQ_PERF_SEQ_CNT_D_I1[] = {
	 { "VALUE", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_IO_CDRCNTL1_D0[] = {
	 { "DQ_RXPHASE_B0", 0, 7, &umr_bitfield_default },
	 { "DQ_RXPHASE_B1", 8, 15, &umr_bitfield_default },
	 { "WCDR_TXPHASE_B0", 16, 23, &umr_bitfield_default },
	 { "WCDR_TXPHASE_B1", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_IO_CDRCNTL1_D1[] = {
	 { "DQ_RXPHASE_B0", 0, 7, &umr_bitfield_default },
	 { "DQ_RXPHASE_B1", 8, 15, &umr_bitfield_default },
	 { "WCDR_TXPHASE_B0", 16, 23, &umr_bitfield_default },
	 { "WCDR_TXPHASE_B1", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_IO_RXCNTL1_DPHY0_D0[] = {
	 { "DLL_RSV", 28, 31, &umr_bitfield_default },
	 { "PMD_LOOPBACK", 25, 27, &umr_bitfield_default },
	 { "VREFCAL1_MSB", 0, 3, &umr_bitfield_default },
	 { "VREFCAL2_MSB", 4, 7, &umr_bitfield_default },
	 { "VREFCAL3", 8, 15, &umr_bitfield_default },
	 { "VREFPDNB_1", 18, 18, &umr_bitfield_default },
	 { "VREFSEL2", 16, 16, &umr_bitfield_default },
	 { "VREFSEL3", 17, 17, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_IO_RXCNTL1_DPHY1_D0[] = {
	 { "DLL_RSV", 28, 31, &umr_bitfield_default },
	 { "PMD_LOOPBACK", 25, 27, &umr_bitfield_default },
	 { "VREFCAL1_MSB", 0, 3, &umr_bitfield_default },
	 { "VREFCAL2_MSB", 4, 7, &umr_bitfield_default },
	 { "VREFCAL3", 8, 15, &umr_bitfield_default },
	 { "VREFPDNB_1", 18, 18, &umr_bitfield_default },
	 { "VREFSEL2", 16, 16, &umr_bitfield_default },
	 { "VREFSEL3", 17, 17, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_IO_RXCNTL1_DPHY0_D1[] = {
	 { "DLL_RSV", 28, 31, &umr_bitfield_default },
	 { "PMD_LOOPBACK", 25, 27, &umr_bitfield_default },
	 { "VREFCAL1_MSB", 0, 3, &umr_bitfield_default },
	 { "VREFCAL2_MSB", 4, 7, &umr_bitfield_default },
	 { "VREFCAL3", 8, 15, &umr_bitfield_default },
	 { "VREFPDNB_1", 18, 18, &umr_bitfield_default },
	 { "VREFSEL2", 16, 16, &umr_bitfield_default },
	 { "VREFSEL3", 17, 17, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_IO_RXCNTL1_DPHY1_D1[] = {
	 { "DLL_RSV", 28, 31, &umr_bitfield_default },
	 { "PMD_LOOPBACK", 25, 27, &umr_bitfield_default },
	 { "VREFCAL1_MSB", 0, 3, &umr_bitfield_default },
	 { "VREFCAL2_MSB", 4, 7, &umr_bitfield_default },
	 { "VREFCAL3", 8, 15, &umr_bitfield_default },
	 { "VREFPDNB_1", 18, 18, &umr_bitfield_default },
	 { "VREFSEL2", 16, 16, &umr_bitfield_default },
	 { "VREFSEL3", 17, 17, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_SEQ_TSM_WCDR[] = {
	 { "WCDR", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_IO_CDRCNTL2_D0[] = {
	 { "CDR_FB_SEL0", 0, 0, &umr_bitfield_default },
	 { "CDR_FB_SEL1", 1, 1, &umr_bitfield_default },
	 { "EDC_RXEN_OVR0", 2, 2, &umr_bitfield_default },
	 { "EDC_RXEN_OVR1", 3, 3, &umr_bitfield_default },
	 { "TXCDRBYPASS0", 4, 4, &umr_bitfield_default },
	 { "TXCDRBYPASS1", 5, 5, &umr_bitfield_default },
	 { "WCK_RXEN_OVR0", 6, 6, &umr_bitfield_default },
	 { "WCK_RXEN_OVR1", 7, 7, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_IO_CDRCNTL2_D1[] = {
	 { "CDR_FB_SEL0", 0, 0, &umr_bitfield_default },
	 { "CDR_FB_SEL1", 1, 1, &umr_bitfield_default },
	 { "EDC_RXEN_OVR0", 2, 2, &umr_bitfield_default },
	 { "EDC_RXEN_OVR1", 3, 3, &umr_bitfield_default },
	 { "TXCDRBYPASS0", 4, 4, &umr_bitfield_default },
	 { "TXCDRBYPASS1", 5, 5, &umr_bitfield_default },
	 { "WCK_RXEN_OVR0", 6, 6, &umr_bitfield_default },
	 { "WCK_RXEN_OVR1", 7, 7, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_SEQ_TSM_MISC[] = {
	 { "WCDR_MASK", 16, 19, &umr_bitfield_default },
	 { "WCDR_PTR", 0, 15, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_SEQ_MISC9[] = {
	 { "VALUE", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMCLK_PWRMGT_CNTL[] = {
	 { "DLL_READY", 6, 6, &umr_bitfield_default },
	 { "DLL_READY_READ", 24, 24, &umr_bitfield_default },
	 { "DLL_SPEED", 0, 4, &umr_bitfield_default },
	 { "MC_INT_CNTL", 7, 7, &umr_bitfield_default },
	 { "MRDCK0_PDNB", 8, 8, &umr_bitfield_default },
	 { "MRDCK0_RESET", 16, 16, &umr_bitfield_default },
	 { "MRDCK1_PDNB", 9, 9, &umr_bitfield_default },
	 { "MRDCK1_RESET", 17, 17, &umr_bitfield_default },
};
static struct umr_bitfield mmDLL_CNTL[] = {
	 { "DLL_LOCK_TIME", 12, 21, &umr_bitfield_default },
	 { "DLL_RESET_TIME", 0, 9, &umr_bitfield_default },
	 { "MRDCK0_BYPASS", 24, 24, &umr_bitfield_default },
	 { "MRDCK1_BYPASS", 25, 25, &umr_bitfield_default },
	 { "PWR2_MODE", 26, 26, &umr_bitfield_default },
};
static struct umr_bitfield mmMPLL_SEQ_UCODE_1[] = {
	 { "INSTR0", 0, 3, &umr_bitfield_default },
	 { "INSTR1", 4, 7, &umr_bitfield_default },
	 { "INSTR2", 8, 11, &umr_bitfield_default },
	 { "INSTR3", 12, 15, &umr_bitfield_default },
	 { "INSTR4", 16, 19, &umr_bitfield_default },
	 { "INSTR5", 20, 23, &umr_bitfield_default },
	 { "INSTR6", 24, 27, &umr_bitfield_default },
	 { "INSTR7", 28, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMPLL_SEQ_UCODE_2[] = {
	 { "INSTR10", 8, 11, &umr_bitfield_default },
	 { "INSTR11", 12, 15, &umr_bitfield_default },
	 { "INSTR12", 16, 19, &umr_bitfield_default },
	 { "INSTR13", 20, 23, &umr_bitfield_default },
	 { "INSTR14", 24, 27, &umr_bitfield_default },
	 { "INSTR15", 28, 31, &umr_bitfield_default },
	 { "INSTR8", 0, 3, &umr_bitfield_default },
	 { "INSTR9", 4, 7, &umr_bitfield_default },
};
static struct umr_bitfield mmMPLL_CNTL_MODE[] = {
	 { "FAST_LOCK_CNTRL", 21, 22, &umr_bitfield_default },
	 { "FAST_LOCK_EN", 20, 20, &umr_bitfield_default },
	 { "FORCE_TESTMODE", 17, 17, &umr_bitfield_default },
	 { "GLOBAL_MPLL_RESET", 31, 31, &umr_bitfield_default },
	 { "INSTR_DELAY", 0, 7, &umr_bitfield_default },
	 { "MPLL_CHG_STATUS", 16, 16, &umr_bitfield_default },
	 { "MPLL_CTLREQ", 14, 14, &umr_bitfield_default },
	 { "MPLL_MCLK_SEL", 11, 11, &umr_bitfield_default },
	 { "MPLL_SW_DIR_CONTROL", 8, 8, &umr_bitfield_default },
	 { "QDR", 13, 13, &umr_bitfield_default },
	 { "SPARE_1", 12, 12, &umr_bitfield_default },
	 { "SPARE_2", 23, 23, &umr_bitfield_default },
	 { "SPARE_3", 28, 30, &umr_bitfield_default },
	 { "SS_DSMODE_EN", 26, 26, &umr_bitfield_default },
	 { "SS_SSEN", 24, 25, &umr_bitfield_default },
	 { "VTOI_BIAS_CNTRL", 27, 27, &umr_bitfield_default },
};
static struct umr_bitfield mmMPLL_FUNC_CNTL[] = {
	 { "BG_100ADJ", 8, 11, &umr_bitfield_default },
	 { "BG_135ADJ", 16, 19, &umr_bitfield_default },
	 { "BWCTRL", 20, 27, &umr_bitfield_default },
	 { "REG_BIAS", 30, 31, &umr_bitfield_default },
	 { "SPARE_0", 5, 5, &umr_bitfield_default },
};
static struct umr_bitfield mmMPLL_FUNC_CNTL_1[] = {
	 { "CLKF", 16, 27, &umr_bitfield_default },
	 { "CLKFRAC", 4, 15, &umr_bitfield_default },
	 { "SPARE_0", 2, 3, &umr_bitfield_default },
	 { "SPARE_1", 28, 31, &umr_bitfield_default },
	 { "VCO_MODE", 0, 1, &umr_bitfield_default },
};
static struct umr_bitfield mmMPLL_FUNC_CNTL_2[] = {
	 { "BACKUP_2", 17, 19, &umr_bitfield_default },
	 { "BACKUP", 27, 31, &umr_bitfield_default },
	 { "LF_CNTRL", 20, 26, &umr_bitfield_default },
	 { "MPLL_UNLOCK_CLEAR", 7, 7, &umr_bitfield_default },
	 { "PFD_RESET_CNTRL", 12, 13, &umr_bitfield_default },
	 { "RESET_EN", 2, 2, &umr_bitfield_default },
	 { "RESET_TIMER", 10, 11, &umr_bitfield_default },
	 { "TEST_BYPCLK_EN", 3, 3, &umr_bitfield_default },
	 { "TEST_BYPCLK_SRC", 4, 4, &umr_bitfield_default },
	 { "TEST_BYPMCLK", 6, 6, &umr_bitfield_default },
	 { "TEST_FBDIV_FRAC_BYPASS", 5, 5, &umr_bitfield_default },
	 { "TEST_FBDIV_SSC_BYPASS", 9, 9, &umr_bitfield_default },
	 { "TEST_VCTL_CNTRL", 8, 8, &umr_bitfield_default },
	 { "TEST_VCTL_EN", 1, 1, &umr_bitfield_default },
	 { "VCTRLADC_EN", 0, 0, &umr_bitfield_default },
};
static struct umr_bitfield mmMPLL_AD_FUNC_CNTL[] = {
	 { "SPARE", 3, 31, &umr_bitfield_default },
	 { "YCLK_POST_DIV", 0, 2, &umr_bitfield_default },
};
static struct umr_bitfield mmMPLL_DQ_FUNC_CNTL[] = {
	 { "SPARE_0", 3, 3, &umr_bitfield_default },
	 { "SPARE", 5, 31, &umr_bitfield_default },
	 { "YCLK_POST_DIV", 0, 2, &umr_bitfield_default },
	 { "YCLK_SEL", 4, 4, &umr_bitfield_default },
};
static struct umr_bitfield mmMPLL_TIME[] = {
	 { "MPLL_LOCK_TIME", 0, 15, &umr_bitfield_default },
	 { "MPLL_RESET_TIME", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMPLL_SS1[] = {
	 { "CLKV", 0, 25, &umr_bitfield_default },
	 { "SPARE", 26, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMPLL_SS2[] = {
	 { "CLKS", 0, 11, &umr_bitfield_default },
	 { "SPARE", 12, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMPLL_CONTROL[] = {
	 { "AD_BG_PWRON", 12, 12, &umr_bitfield_default },
	 { "AD_PLL_PWRON", 13, 13, &umr_bitfield_default },
	 { "AD_PLL_RESET", 14, 14, &umr_bitfield_default },
	 { "DQ_0_0_BG_PWRON", 16, 16, &umr_bitfield_default },
	 { "DQ_0_0_PLL_PWRON", 17, 17, &umr_bitfield_default },
	 { "DQ_0_0_PLL_RESET", 18, 18, &umr_bitfield_default },
	 { "DQ_0_1_BG_PWRON", 20, 20, &umr_bitfield_default },
	 { "DQ_0_1_PLL_PWRON", 21, 21, &umr_bitfield_default },
	 { "DQ_0_1_PLL_RESET", 22, 22, &umr_bitfield_default },
	 { "DQ_1_0_BG_PWRON", 24, 24, &umr_bitfield_default },
	 { "DQ_1_0_PLL_PWRON", 25, 25, &umr_bitfield_default },
	 { "DQ_1_0_PLL_RESET", 26, 26, &umr_bitfield_default },
	 { "DQ_1_1_BG_PWRON", 28, 28, &umr_bitfield_default },
	 { "DQ_1_1_PLL_PWRON", 29, 29, &umr_bitfield_default },
	 { "DQ_1_1_PLL_RESET", 30, 30, &umr_bitfield_default },
	 { "GDDR_PWRON", 0, 0, &umr_bitfield_default },
	 { "PLL_BUF_PWRON_TX", 2, 2, &umr_bitfield_default },
	 { "REFCLK_PWRON", 1, 1, &umr_bitfield_default },
	 { "SPARE_AD_0", 15, 15, &umr_bitfield_default },
	 { "SPARE_DQ_0_0", 19, 19, &umr_bitfield_default },
	 { "SPARE_DQ_0_1", 23, 23, &umr_bitfield_default },
	 { "SPARE_DQ_1_0", 27, 27, &umr_bitfield_default },
	 { "SPARE_DQ_1_1", 31, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMPLL_AD_STATUS[] = {
	 { "FREQ_LOCK", 18, 18, &umr_bitfield_default },
	 { "FREQ_UNLOCK_STICKY", 19, 19, &umr_bitfield_default },
	 { "OINT_RESET", 17, 17, &umr_bitfield_default },
	 { "TEST_FBDIV_FRAC", 4, 6, &umr_bitfield_default },
	 { "TEST_FBDIV_INT", 7, 16, &umr_bitfield_default },
	 { "VCTRLADC", 0, 2, &umr_bitfield_default },
};
static struct umr_bitfield mmMPLL_DQ_0_0_STATUS[] = {
	 { "FREQ_LOCK", 18, 18, &umr_bitfield_default },
	 { "FREQ_UNLOCK_STICKY", 19, 19, &umr_bitfield_default },
	 { "OINT_RESET", 17, 17, &umr_bitfield_default },
	 { "TEST_FBDIV_FRAC", 4, 6, &umr_bitfield_default },
	 { "TEST_FBDIV_INT", 7, 16, &umr_bitfield_default },
	 { "VCTRLADC", 0, 2, &umr_bitfield_default },
};
static struct umr_bitfield mmMPLL_DQ_0_1_STATUS[] = {
	 { "FREQ_LOCK", 18, 18, &umr_bitfield_default },
	 { "FREQ_UNLOCK_STICKY", 19, 19, &umr_bitfield_default },
	 { "OINT_RESET", 17, 17, &umr_bitfield_default },
	 { "TEST_FBDIV_FRAC", 4, 6, &umr_bitfield_default },
	 { "TEST_FBDIV_INT", 7, 16, &umr_bitfield_default },
	 { "VCTRLADC", 0, 2, &umr_bitfield_default },
};
static struct umr_bitfield mmMPLL_DQ_1_0_STATUS[] = {
	 { "FREQ_LOCK", 18, 18, &umr_bitfield_default },
	 { "FREQ_UNLOCK_STICKY", 19, 19, &umr_bitfield_default },
	 { "OINT_RESET", 17, 17, &umr_bitfield_default },
	 { "TEST_FBDIV_FRAC", 4, 6, &umr_bitfield_default },
	 { "TEST_FBDIV_INT", 7, 16, &umr_bitfield_default },
	 { "VCTRLADC", 0, 2, &umr_bitfield_default },
};
static struct umr_bitfield mmMPLL_DQ_1_1_STATUS[] = {
	 { "FREQ_LOCK", 18, 18, &umr_bitfield_default },
	 { "FREQ_UNLOCK_STICKY", 19, 19, &umr_bitfield_default },
	 { "OINT_RESET", 17, 17, &umr_bitfield_default },
	 { "TEST_FBDIV_FRAC", 4, 6, &umr_bitfield_default },
	 { "TEST_FBDIV_INT", 7, 16, &umr_bitfield_default },
	 { "VCTRLADC", 0, 2, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_TRAIN_PRBSERR_2_D0[] = {
	 { "ABI_STATUS", 28, 28, &umr_bitfield_default },
	 { "ADDR_STATUS", 16, 25, &umr_bitfield_default },
	 { "CAS_STATUS", 10, 10, &umr_bitfield_default },
	 { "CKB_STATUS", 1, 1, &umr_bitfield_default },
	 { "CKE_STATUS", 8, 8, &umr_bitfield_default },
	 { "CK_STATUS", 0, 0, &umr_bitfield_default },
	 { "CS_STATUS", 4, 5, &umr_bitfield_default },
	 { "RAS_STATUS", 9, 9, &umr_bitfield_default },
	 { "WE_STATUS", 11, 11, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_TRAIN_PRBSERR_2_D1[] = {
	 { "ABI_STATUS", 28, 28, &umr_bitfield_default },
	 { "ADDR_STATUS", 16, 25, &umr_bitfield_default },
	 { "CAS_STATUS", 10, 10, &umr_bitfield_default },
	 { "CKB_STATUS", 1, 1, &umr_bitfield_default },
	 { "CKE_STATUS", 8, 8, &umr_bitfield_default },
	 { "CK_STATUS", 0, 0, &umr_bitfield_default },
	 { "CS_STATUS", 4, 5, &umr_bitfield_default },
	 { "RAS_STATUS", 9, 9, &umr_bitfield_default },
	 { "WE_STATUS", 11, 11, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_SEQ_PERF_CNTL_1[] = {
	 { "PAUSE", 0, 0, &umr_bitfield_default },
	 { "SEL_A_MSB", 8, 8, &umr_bitfield_default },
	 { "SEL_B_MSB", 9, 9, &umr_bitfield_default },
	 { "SEL_CH0_C_MSB", 10, 10, &umr_bitfield_default },
	 { "SEL_CH0_D_MSB", 11, 11, &umr_bitfield_default },
	 { "SEL_CH1_A_MSB", 12, 12, &umr_bitfield_default },
	 { "SEL_CH1_B_MSB", 13, 13, &umr_bitfield_default },
	 { "SEL_CH1_C_MSB", 14, 14, &umr_bitfield_default },
	 { "SEL_CH1_D_MSB", 15, 15, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_SEQ_TRAIN_EDC_THRESHOLD2[] = {
	 { "THRESHOLD_PERIOD", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_SEQ_TRAIN_EDC_THRESHOLD3[] = {
	 { "CH0_LINK_RETRAIN_IN_PROGRESS", 8, 8, &umr_bitfield_default },
	 { "CH0_LINK_RETRAIN_STATUS", 0, 0, &umr_bitfield_default },
	 { "CH1_LINK_RETRAIN_IN_PROGRESS", 9, 9, &umr_bitfield_default },
	 { "CH1_LINK_RETRAIN_STATUS", 1, 1, &umr_bitfield_default },
	 { "CLEAR_RETRAIN_STATUS", 2, 2, &umr_bitfield_default },
	 { "RETRAIN_MONITOR", 4, 5, &umr_bitfield_default },
	 { "RETRAIN_VBI", 3, 3, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_XBAR_ADDR_DEC[] = {
	 { "GECC", 1, 1, &umr_bitfield_default },
	 { "NO_DIV_BY_3", 0, 0, &umr_bitfield_default },
	 { "RB_SPLIT_COLHI", 3, 3, &umr_bitfield_default },
	 { "RB_SPLIT", 2, 2, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_XBAR_REMOTE[] = {
	 { "RDREQ_EN_GOQ", 1, 1, &umr_bitfield_default },
	 { "WRREQ_EN_GOQ", 0, 0, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_XBAR_WRREQ_CREDIT[] = {
	 { "OUT0", 0, 7, &umr_bitfield_default },
	 { "OUT1", 8, 15, &umr_bitfield_default },
	 { "OUT2", 16, 23, &umr_bitfield_default },
	 { "OUT3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_XBAR_RDREQ_CREDIT[] = {
	 { "OUT0", 0, 7, &umr_bitfield_default },
	 { "OUT1", 8, 15, &umr_bitfield_default },
	 { "OUT2", 16, 23, &umr_bitfield_default },
	 { "OUT3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_XBAR_RDREQ_PRI_CREDIT[] = {
	 { "OUT0", 0, 7, &umr_bitfield_default },
	 { "OUT1", 8, 15, &umr_bitfield_default },
	 { "OUT2", 16, 23, &umr_bitfield_default },
	 { "OUT3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_XBAR_WRRET_CREDIT1[] = {
	 { "OUT0", 0, 7, &umr_bitfield_default },
	 { "OUT1", 8, 15, &umr_bitfield_default },
	 { "OUT2", 16, 23, &umr_bitfield_default },
	 { "OUT3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_XBAR_WRRET_CREDIT2[] = {
	 { "OUT4", 0, 7, &umr_bitfield_default },
	 { "OUT5", 8, 15, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_XBAR_RDRET_CREDIT1[] = {
	 { "OUT0", 0, 7, &umr_bitfield_default },
	 { "OUT1", 8, 15, &umr_bitfield_default },
	 { "OUT2", 16, 23, &umr_bitfield_default },
	 { "OUT3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_XBAR_RDRET_CREDIT2[] = {
	 { "HUB_LP_RDRET_SKID", 16, 23, &umr_bitfield_default },
	 { "OUT4", 0, 7, &umr_bitfield_default },
	 { "OUT5", 8, 15, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_XBAR_RDRET_PRI_CREDIT1[] = {
	 { "OUT0", 0, 7, &umr_bitfield_default },
	 { "OUT1", 8, 15, &umr_bitfield_default },
	 { "OUT2", 16, 23, &umr_bitfield_default },
	 { "OUT3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_XBAR_RDRET_PRI_CREDIT2[] = {
	 { "OUT4", 0, 7, &umr_bitfield_default },
	 { "OUT5", 8, 15, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_XBAR_CHTRIREMAP[] = {
	 { "CH0", 0, 1, &umr_bitfield_default },
	 { "CH1", 2, 3, &umr_bitfield_default },
	 { "CH2", 4, 5, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_XBAR_TWOCHAN[] = {
	 { "CH0", 1, 2, &umr_bitfield_default },
	 { "CH1", 3, 4, &umr_bitfield_default },
	 { "DISABLE_ONEPORT", 0, 0, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_XBAR_ARB[] = {
	 { "BREAK_BURST_CID_CHANGE", 2, 2, &umr_bitfield_default },
	 { "DISABLE_HUB_STALL_HIGHEST", 1, 1, &umr_bitfield_default },
	 { "HUBRD_HIGHEST", 0, 0, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_XBAR_ARB_MAX_BURST[] = {
	 { "RD_PORT0", 0, 3, &umr_bitfield_default },
	 { "RD_PORT1", 4, 7, &umr_bitfield_default },
	 { "RD_PORT2", 8, 11, &umr_bitfield_default },
	 { "RD_PORT3", 12, 15, &umr_bitfield_default },
	 { "WR_PORT0", 16, 19, &umr_bitfield_default },
	 { "WR_PORT1", 20, 23, &umr_bitfield_default },
	 { "WR_PORT2", 24, 27, &umr_bitfield_default },
	 { "WR_PORT3", 28, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_XBAR_PERF_MON_CNTL0[] = {
	 { "ALLOW_WRAP", 28, 28, &umr_bitfield_default },
	 { "START_MODE", 24, 25, &umr_bitfield_default },
	 { "START_THRESH", 0, 11, &umr_bitfield_default },
	 { "STOP_MODE", 26, 27, &umr_bitfield_default },
	 { "STOP_THRESH", 12, 23, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_XBAR_PERF_MON_CNTL1[] = {
	 { "START_TRIG_ID", 8, 15, &umr_bitfield_default },
	 { "STOP_TRIG_ID", 16, 23, &umr_bitfield_default },
	 { "THRESH_CNTR_ID", 0, 7, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_XBAR_PERF_MON_CNTL2[] = {
	 { "MON0_ID", 0, 7, &umr_bitfield_default },
	 { "MON1_ID", 8, 15, &umr_bitfield_default },
	 { "MON2_ID", 16, 23, &umr_bitfield_default },
	 { "MON3_ID", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_XBAR_PERF_MON_RSLT0[] = {
	 { "COUNT", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_XBAR_PERF_MON_RSLT1[] = {
	 { "COUNT", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_XBAR_PERF_MON_RSLT2[] = {
	 { "COUNT", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_XBAR_PERF_MON_RSLT3[] = {
	 { "COUNT", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_XBAR_PERF_MON_MAX_THSH[] = {
	 { "MON0", 0, 7, &umr_bitfield_default },
	 { "MON1", 8, 15, &umr_bitfield_default },
	 { "MON2", 16, 23, &umr_bitfield_default },
	 { "MON3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_XBAR_SPARE0[] = {
	 { "BIT", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_XBAR_SPARE1[] = {
	 { "BIT", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmATC_VM_APERTURE0_LOW_ADDR[] = {
	 { "VIRTUAL_PAGE_NUMBER", 0, 27, &umr_bitfield_default },
};
static struct umr_bitfield mmATC_VM_APERTURE1_LOW_ADDR[] = {
	 { "VIRTUAL_PAGE_NUMBER", 0, 27, &umr_bitfield_default },
};
static struct umr_bitfield mmATC_VM_APERTURE0_HIGH_ADDR[] = {
	 { "VIRTUAL_PAGE_NUMBER", 0, 27, &umr_bitfield_default },
};
static struct umr_bitfield mmATC_VM_APERTURE1_HIGH_ADDR[] = {
	 { "VIRTUAL_PAGE_NUMBER", 0, 27, &umr_bitfield_default },
};
static struct umr_bitfield mmATC_VM_APERTURE0_CNTL[] = {
	 { "ATS_ACCESS_MODE", 0, 1, &umr_bitfield_default },
};
static struct umr_bitfield mmATC_VM_APERTURE1_CNTL[] = {
	 { "ATS_ACCESS_MODE", 0, 1, &umr_bitfield_default },
};
static struct umr_bitfield mmATC_VM_APERTURE0_CNTL2[] = {
	 { "VMIDS_USING_RANGE", 0, 15, &umr_bitfield_default },
};
static struct umr_bitfield mmATC_VM_APERTURE1_CNTL2[] = {
	 { "VMIDS_USING_RANGE", 0, 15, &umr_bitfield_default },
};
static struct umr_bitfield mmATC_ATS_CNTL[] = {
	 { "CREDITS_ATS_RPB", 8, 13, &umr_bitfield_default },
	 { "DEBUG_ECO", 16, 19, &umr_bitfield_default },
	 { "DISABLE_ATC", 0, 0, &umr_bitfield_default },
	 { "DISABLE_PASID", 2, 2, &umr_bitfield_default },
	 { "DISABLE_PRI", 1, 1, &umr_bitfield_default },
};
static struct umr_bitfield mmATC_ATS_DEBUG[] = {
	 { "ADDRESS_TRANSLATION_REQUEST_WRITE_PERMS", 2, 2, &umr_bitfield_default },
	 { "DISALLOW_ERR_TO_DONE", 14, 14, &umr_bitfield_default },
	 { "EXE_BIT", 7, 7, &umr_bitfield_default },
	 { "IDENT_RETURN", 1, 1, &umr_bitfield_default },
	 { "IGNORE_FED", 15, 15, &umr_bitfield_default },
	 { "INVALIDATE_ALL", 0, 0, &umr_bitfield_default },
	 { "INVALIDATION_REQUESTS_DISALLOWED_WHEN_ATC_IS_DISABLED", 16, 16, &umr_bitfield_default },
	 { "NUM_REQUESTS_AT_ERR", 10, 13, &umr_bitfield_default },
	 { "PAGE_REQUEST_PERMS", 8, 8, &umr_bitfield_default },
	 { "PAGE_REQUESTS_USE_RELAXED_ORDERING", 5, 5, &umr_bitfield_default },
	 { "PRIV_BIT", 6, 6, &umr_bitfield_default },
	 { "UNTRANSLATED_ONLY_REQUESTS_CARRY_SIZE", 9, 9, &umr_bitfield_default },
};
static struct umr_bitfield mmATC_ATS_FAULT_DEBUG[] = {
	 { "ALLOW_SUBSEQUENT_FAULT_STATUS_ADDR_UPDATES", 8, 8, &umr_bitfield_default },
	 { "CLEAR_FAULT_STATUS_ADDR", 16, 16, &umr_bitfield_default },
	 { "CREDITS_ATS_IH", 0, 4, &umr_bitfield_default },
};
static struct umr_bitfield mmATC_ATS_STATUS[] = {
	 { "BUSY", 0, 0, &umr_bitfield_default },
	 { "CRASHED", 1, 1, &umr_bitfield_default },
	 { "DEADLOCK_DETECTION", 2, 2, &umr_bitfield_default },
};
static struct umr_bitfield mmATC_ATS_FAULT_CNTL[] = {
	 { "FAULT_CRASH_TABLE", 20, 25, &umr_bitfield_default },
	 { "FAULT_INTERRUPT_TABLE", 10, 15, &umr_bitfield_default },
	 { "FAULT_REGISTER_LOG", 0, 5, &umr_bitfield_default },
};
static struct umr_bitfield mmATC_ATS_FAULT_STATUS_INFO[] = {
	 { "EXTRA_INFO2", 16, 16, &umr_bitfield_default },
	 { "EXTRA_INFO", 15, 15, &umr_bitfield_default },
	 { "FAULT_TYPE", 0, 5, &umr_bitfield_default },
	 { "INVALIDATION", 17, 17, &umr_bitfield_default },
	 { "PAGE_ADDR_HIGH", 24, 27, &umr_bitfield_default },
	 { "PAGE_REQUEST", 18, 18, &umr_bitfield_default },
	 { "STATUS", 19, 23, &umr_bitfield_default },
	 { "VMID", 10, 14, &umr_bitfield_default },
};
static struct umr_bitfield mmATC_ATS_FAULT_STATUS_ADDR[] = {
	 { "PAGE_ADDR", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmATC_ATS_DEFAULT_PAGE_LOW[] = {
	 { "DEFAULT_PAGE", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmATC_ATS_DEFAULT_PAGE_CNTL[] = {
	 { "DEFAULT_PAGE_HIGH", 2, 5, &umr_bitfield_default },
	 { "SEND_DEFAULT_PAGE", 0, 0, &umr_bitfield_default },
};
static struct umr_bitfield mmATC_MISC_CG[] = {
	 { "ENABLE", 18, 18, &umr_bitfield_default },
	 { "MEM_LS_ENABLE", 19, 19, &umr_bitfield_default },
	 { "OFFDLY", 6, 11, &umr_bitfield_default },
};
static struct umr_bitfield mmATC_L2_CNTL[] = {
	 { "NUMBER_OF_TRANSLATION_READ_REQUESTS", 0, 1, &umr_bitfield_default },
	 { "NUMBER_OF_TRANSLATION_READS_DEPENDS_ON_ADDR_MOD", 10, 10, &umr_bitfield_default },
	 { "NUMBER_OF_TRANSLATION_WRITE_REQUESTS", 4, 5, &umr_bitfield_default },
	 { "NUMBER_OF_TRANSLATION_WRITES_DEPENDS_ON_ADDR_MOD", 11, 11, &umr_bitfield_default },
};
static struct umr_bitfield mmATC_L2_DEBUG[] = {
	 { "CREDITS_L2_ATS", 0, 5, &umr_bitfield_default },
};
static struct umr_bitfield mmATC_L1_CNTL[] = {
	 { "DONT_NEED_ATS_BEHAVIOR", 0, 1, &umr_bitfield_default },
	 { "NEED_ATS_BEHAVIOR", 2, 2, &umr_bitfield_default },
	 { "NEED_ATS_SNOOP_DEFAULT", 4, 4, &umr_bitfield_default },
};
static struct umr_bitfield mmATC_L1_ADDRESS_OFFSET[] = {
	 { "LOGICAL_ADDRESS", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmATC_L1RD_DEBUG_TLB[] = {
	 { "CREDITS_L1_L2", 12, 17, &umr_bitfield_default },
	 { "CREDITS_L1_RPB", 20, 27, &umr_bitfield_default },
	 { "DEBUG_ECO", 28, 29, &umr_bitfield_default },
	 { "DISABLE_FRAGMENTS", 0, 0, &umr_bitfield_default },
	 { "EFFECTIVE_CAM_SIZE", 4, 7, &umr_bitfield_default },
	 { "EFFECTIVE_WORK_QUEUE_SIZE", 8, 10, &umr_bitfield_default },
	 { "INVALIDATE_ALL", 30, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmATC_L1WR_DEBUG_TLB[] = {
	 { "CREDITS_L1_L2", 12, 17, &umr_bitfield_default },
	 { "CREDITS_L1_RPB", 20, 27, &umr_bitfield_default },
	 { "DEBUG_ECO", 28, 29, &umr_bitfield_default },
	 { "DISABLE_FRAGMENTS", 0, 0, &umr_bitfield_default },
	 { "EFFECTIVE_CAM_SIZE", 4, 7, &umr_bitfield_default },
	 { "EFFECTIVE_WORK_QUEUE_SIZE", 8, 10, &umr_bitfield_default },
	 { "INVALIDATE_ALL", 30, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmATC_L1RD_STATUS[] = {
	 { "BAD_NEED_ATS", 8, 8, &umr_bitfield_default },
	 { "BUSY", 0, 0, &umr_bitfield_default },
	 { "DEADLOCK_DETECTION", 1, 1, &umr_bitfield_default },
};
static struct umr_bitfield mmATC_L1WR_STATUS[] = {
	 { "BAD_NEED_ATS", 8, 8, &umr_bitfield_default },
	 { "BUSY", 0, 0, &umr_bitfield_default },
	 { "DEADLOCK_DETECTION", 1, 1, &umr_bitfield_default },
};
static struct umr_bitfield mmATC_VMID_PASID_MAPPING_UPDATE_STATUS[] = {
	 { "VMID0_REMAPPING_FINISHED", 0, 0, &umr_bitfield_default },
	 { "VMID10_REMAPPING_FINISHED", 10, 10, &umr_bitfield_default },
	 { "VMID11_REMAPPING_FINISHED", 11, 11, &umr_bitfield_default },
	 { "VMID12_REMAPPING_FINISHED", 12, 12, &umr_bitfield_default },
	 { "VMID13_REMAPPING_FINISHED", 13, 13, &umr_bitfield_default },
	 { "VMID14_REMAPPING_FINISHED", 14, 14, &umr_bitfield_default },
	 { "VMID15_REMAPPING_FINISHED", 15, 15, &umr_bitfield_default },
	 { "VMID1_REMAPPING_FINISHED", 1, 1, &umr_bitfield_default },
	 { "VMID2_REMAPPING_FINISHED", 2, 2, &umr_bitfield_default },
	 { "VMID3_REMAPPING_FINISHED", 3, 3, &umr_bitfield_default },
	 { "VMID4_REMAPPING_FINISHED", 4, 4, &umr_bitfield_default },
	 { "VMID5_REMAPPING_FINISHED", 5, 5, &umr_bitfield_default },
	 { "VMID6_REMAPPING_FINISHED", 6, 6, &umr_bitfield_default },
	 { "VMID7_REMAPPING_FINISHED", 7, 7, &umr_bitfield_default },
	 { "VMID8_REMAPPING_FINISHED", 8, 8, &umr_bitfield_default },
	 { "VMID9_REMAPPING_FINISHED", 9, 9, &umr_bitfield_default },
};
static struct umr_bitfield mmATC_VMID0_PASID_MAPPING[] = {
	 { "PASID", 0, 15, &umr_bitfield_default },
	 { "VALID", 31, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmATC_VMID1_PASID_MAPPING[] = {
	 { "PASID", 0, 15, &umr_bitfield_default },
	 { "VALID", 31, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmATC_VMID2_PASID_MAPPING[] = {
	 { "PASID", 0, 15, &umr_bitfield_default },
	 { "VALID", 31, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmATC_VMID3_PASID_MAPPING[] = {
	 { "PASID", 0, 15, &umr_bitfield_default },
	 { "VALID", 31, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmATC_VMID4_PASID_MAPPING[] = {
	 { "PASID", 0, 15, &umr_bitfield_default },
	 { "VALID", 31, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmATC_VMID5_PASID_MAPPING[] = {
	 { "PASID", 0, 15, &umr_bitfield_default },
	 { "VALID", 31, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmATC_VMID6_PASID_MAPPING[] = {
	 { "PASID", 0, 15, &umr_bitfield_default },
	 { "VALID", 31, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmATC_VMID7_PASID_MAPPING[] = {
	 { "PASID", 0, 15, &umr_bitfield_default },
	 { "VALID", 31, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmATC_VMID8_PASID_MAPPING[] = {
	 { "PASID", 0, 15, &umr_bitfield_default },
	 { "VALID", 31, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmATC_VMID9_PASID_MAPPING[] = {
	 { "PASID", 0, 15, &umr_bitfield_default },
	 { "VALID", 31, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmATC_VMID10_PASID_MAPPING[] = {
	 { "PASID", 0, 15, &umr_bitfield_default },
	 { "VALID", 31, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmATC_VMID11_PASID_MAPPING[] = {
	 { "PASID", 0, 15, &umr_bitfield_default },
	 { "VALID", 31, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmATC_VMID12_PASID_MAPPING[] = {
	 { "PASID", 0, 15, &umr_bitfield_default },
	 { "VALID", 31, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmATC_VMID13_PASID_MAPPING[] = {
	 { "PASID", 0, 15, &umr_bitfield_default },
	 { "VALID", 31, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmATC_VMID14_PASID_MAPPING[] = {
	 { "PASID", 0, 15, &umr_bitfield_default },
	 { "VALID", 31, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmATC_VMID15_PASID_MAPPING[] = {
	 { "PASID", 0, 15, &umr_bitfield_default },
	 { "VALID", 31, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmGMCON_RENG_RAM_INDEX[] = {
	 { "RENG_RAM_INDEX", 0, 9, &umr_bitfield_default },
};
static struct umr_bitfield mmGMCON_RENG_RAM_DATA[] = {
	 { "RENG_RAM_DATA", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmGMCON_RENG_EXECUTE[] = {
	 { "RENG_EXECUTE_DSP_END_PTR", 12, 21, &umr_bitfield_default },
	 { "RENG_EXECUTE_END_PTR", 22, 31, &umr_bitfield_default },
	 { "RENG_EXECUTE_NOW", 1, 1, &umr_bitfield_default },
	 { "RENG_EXECUTE_NOW_START_PTR", 2, 11, &umr_bitfield_default },
	 { "RENG_EXECUTE_ON_PWR_UP", 0, 0, &umr_bitfield_default },
};
static struct umr_bitfield mmGMCON_MISC[] = {
	 { "ALLOW_DEEP_SLEEP_MODE", 28, 29, &umr_bitfield_default },
	 { "CRITICAL_REGS_LOCK", 27, 27, &umr_bitfield_default },
	 { "RENG_EXECUTE_NOW_MODE", 10, 10, &umr_bitfield_default },
	 { "RENG_EXECUTE_ON_REG_UPDATE", 11, 11, &umr_bitfield_default },
	 { "RENG_SRBM_CREDITS_MCD", 12, 15, &umr_bitfield_default },
	 { "STCTRL_DISABLE_ALLOW_SR", 25, 25, &umr_bitfield_default },
	 { "STCTRL_DISABLE_GMC_OFFLINE", 26, 26, &umr_bitfield_default },
	 { "STCTRL_FORCE_ALLOW_SR", 30, 30, &umr_bitfield_default },
	 { "STCTRL_GMC_IDLE_THRESHOLD", 17, 18, &umr_bitfield_default },
	 { "STCTRL_IGNORE_ALLOW_STOP", 22, 22, &umr_bitfield_default },
	 { "STCTRL_IGNORE_PRE_SR", 21, 21, &umr_bitfield_default },
	 { "STCTRL_IGNORE_PROTECTION_FAULT", 24, 24, &umr_bitfield_default },
	 { "STCTRL_IGNORE_SR_COMMIT", 23, 23, &umr_bitfield_default },
	 { "STCTRL_SRBM_IDLE_THRESHOLD", 19, 20, &umr_bitfield_default },
	 { "STCTRL_STUTTER_EN", 16, 16, &umr_bitfield_default },
};
static struct umr_bitfield mmGMCON_MISC2[] = {
	 { "RENG_MEM_POWER_CTRL_OVERRIDE0", 0, 2, &umr_bitfield_default },
	 { "RENG_MEM_POWER_CTRL_OVERRIDE1", 3, 5, &umr_bitfield_default },
	 { "RENG_SR_HOLD_THRESHOLD", 10, 15, &umr_bitfield_default },
	 { "STCTRL_EXTEND_GMC_OFFLINE", 29, 29, &umr_bitfield_default },
	 { "STCTRL_IGNORE_ARB_BUSY", 28, 28, &umr_bitfield_default },
	 { "STCTRL_LPT_TARGET", 16, 27, &umr_bitfield_default },
};
static struct umr_bitfield mmGMCON_STCTRL_REGISTER_SAVE_RANGE0[] = {
	 { "STCTRL_REGISTER_SAVE_BASE0", 0, 15, &umr_bitfield_default },
	 { "STCTRL_REGISTER_SAVE_LIMIT0", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmGMCON_STCTRL_REGISTER_SAVE_RANGE1[] = {
	 { "STCTRL_REGISTER_SAVE_BASE1", 0, 15, &umr_bitfield_default },
	 { "STCTRL_REGISTER_SAVE_LIMIT1", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmGMCON_STCTRL_REGISTER_SAVE_RANGE2[] = {
	 { "STCTRL_REGISTER_SAVE_BASE2", 0, 15, &umr_bitfield_default },
	 { "STCTRL_REGISTER_SAVE_LIMIT2", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmGMCON_STCTRL_REGISTER_SAVE_EXCL_SET0[] = {
	 { "STCTRL_REGISTER_SAVE_EXCL0", 0, 15, &umr_bitfield_default },
	 { "STCTRL_REGISTER_SAVE_EXCL1", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmGMCON_STCTRL_REGISTER_SAVE_EXCL_SET1[] = {
	 { "STCTRL_REGISTER_SAVE_EXCL2", 0, 15, &umr_bitfield_default },
	 { "STCTRL_REGISTER_SAVE_EXCL3", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmGMCON_PERF_MON_CNTL0[] = {
	 { "ALLOW_WRAP", 28, 28, &umr_bitfield_default },
	 { "START_MODE", 24, 25, &umr_bitfield_default },
	 { "START_THRESH", 0, 11, &umr_bitfield_default },
	 { "STOP_MODE", 26, 27, &umr_bitfield_default },
	 { "STOP_THRESH", 12, 23, &umr_bitfield_default },
};
static struct umr_bitfield mmGMCON_PERF_MON_CNTL1[] = {
	 { "MON0_ID", 18, 23, &umr_bitfield_default },
	 { "MON1_ID", 24, 29, &umr_bitfield_default },
	 { "START_TRIG_ID", 6, 11, &umr_bitfield_default },
	 { "STOP_TRIG_ID", 12, 17, &umr_bitfield_default },
	 { "THRESH_CNTR_ID", 0, 5, &umr_bitfield_default },
};
static struct umr_bitfield mmGMCON_PERF_MON_RSLT0[] = {
	 { "COUNT", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmGMCON_PERF_MON_RSLT1[] = {
	 { "COUNT", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmGMCON_PGFSM_CONFIG[] = {
	 { "FSM_ADDR", 0, 7, &umr_bitfield_default },
	 { "P1_SELECT", 10, 10, &umr_bitfield_default },
	 { "P2_SELECT", 11, 11, &umr_bitfield_default },
	 { "POWER_DOWN", 8, 8, &umr_bitfield_default },
	 { "POWER_UP", 9, 9, &umr_bitfield_default },
	 { "READ", 13, 13, &umr_bitfield_default },
	 { "REG_ADDR", 28, 31, &umr_bitfield_default },
	 { "RSRVD", 14, 26, &umr_bitfield_default },
	 { "SRBM_OVERRIDE", 27, 27, &umr_bitfield_default },
	 { "WRITE", 12, 12, &umr_bitfield_default },
};
static struct umr_bitfield mmGMCON_PGFSM_WRITE[] = {
	 { "WRITE_VALUE", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmGMCON_PGFSM_READ[] = {
	 { "PGFSM_SELECT", 24, 27, &umr_bitfield_default },
	 { "READ_VALUE", 0, 23, &umr_bitfield_default },
	 { "SERDES_MASTER_BUSY", 28, 28, &umr_bitfield_default },
};
static struct umr_bitfield mmGMCON_MISC3[] = {
	 { "RENG_DISABLE_MCC", 0, 5, &umr_bitfield_default },
	 { "RENG_DISABLE_MCD", 6, 11, &umr_bitfield_default },
	 { "STCTRL_FORCE_PGFSM_CMD_DONE", 12, 23, &umr_bitfield_default },
};
static struct umr_bitfield mmGMCON_DEBUG[] = {
	 { "GFX_CLEAR", 1, 1, &umr_bitfield_default },
	 { "GFX_STALL", 0, 0, &umr_bitfield_default },
	 { "MISC_FLAGS", 2, 29, &umr_bitfield_default },
};