static struct umr_bitfield mmDAGB0_RDCLI0[] = {
	 { "VIRT_CHAN", 0, 2, &umr_bitfield_default },
	 { "CHECK_TLB_CREDIT", 3, 3, &umr_bitfield_default },
	 { "URG_HIGH", 4, 7, &umr_bitfield_default },
	 { "URG_LOW", 8, 11, &umr_bitfield_default },
	 { "MAX_BW_ENABLE", 12, 12, &umr_bitfield_default },
	 { "MAX_BW", 13, 20, &umr_bitfield_default },
	 { "MIN_BW_ENABLE", 21, 21, &umr_bitfield_default },
	 { "MIN_BW", 22, 24, &umr_bitfield_default },
	 { "OSD_LIMITER_ENABLE", 25, 25, &umr_bitfield_default },
	 { "MAX_OSD", 26, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDAGB0_RDCLI1[] = {
	 { "VIRT_CHAN", 0, 2, &umr_bitfield_default },
	 { "CHECK_TLB_CREDIT", 3, 3, &umr_bitfield_default },
	 { "URG_HIGH", 4, 7, &umr_bitfield_default },
	 { "URG_LOW", 8, 11, &umr_bitfield_default },
	 { "MAX_BW_ENABLE", 12, 12, &umr_bitfield_default },
	 { "MAX_BW", 13, 20, &umr_bitfield_default },
	 { "MIN_BW_ENABLE", 21, 21, &umr_bitfield_default },
	 { "MIN_BW", 22, 24, &umr_bitfield_default },
	 { "OSD_LIMITER_ENABLE", 25, 25, &umr_bitfield_default },
	 { "MAX_OSD", 26, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDAGB0_RDCLI2[] = {
	 { "VIRT_CHAN", 0, 2, &umr_bitfield_default },
	 { "CHECK_TLB_CREDIT", 3, 3, &umr_bitfield_default },
	 { "URG_HIGH", 4, 7, &umr_bitfield_default },
	 { "URG_LOW", 8, 11, &umr_bitfield_default },
	 { "MAX_BW_ENABLE", 12, 12, &umr_bitfield_default },
	 { "MAX_BW", 13, 20, &umr_bitfield_default },
	 { "MIN_BW_ENABLE", 21, 21, &umr_bitfield_default },
	 { "MIN_BW", 22, 24, &umr_bitfield_default },
	 { "OSD_LIMITER_ENABLE", 25, 25, &umr_bitfield_default },
	 { "MAX_OSD", 26, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDAGB0_RDCLI3[] = {
	 { "VIRT_CHAN", 0, 2, &umr_bitfield_default },
	 { "CHECK_TLB_CREDIT", 3, 3, &umr_bitfield_default },
	 { "URG_HIGH", 4, 7, &umr_bitfield_default },
	 { "URG_LOW", 8, 11, &umr_bitfield_default },
	 { "MAX_BW_ENABLE", 12, 12, &umr_bitfield_default },
	 { "MAX_BW", 13, 20, &umr_bitfield_default },
	 { "MIN_BW_ENABLE", 21, 21, &umr_bitfield_default },
	 { "MIN_BW", 22, 24, &umr_bitfield_default },
	 { "OSD_LIMITER_ENABLE", 25, 25, &umr_bitfield_default },
	 { "MAX_OSD", 26, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDAGB0_RDCLI4[] = {
	 { "VIRT_CHAN", 0, 2, &umr_bitfield_default },
	 { "CHECK_TLB_CREDIT", 3, 3, &umr_bitfield_default },
	 { "URG_HIGH", 4, 7, &umr_bitfield_default },
	 { "URG_LOW", 8, 11, &umr_bitfield_default },
	 { "MAX_BW_ENABLE", 12, 12, &umr_bitfield_default },
	 { "MAX_BW", 13, 20, &umr_bitfield_default },
	 { "MIN_BW_ENABLE", 21, 21, &umr_bitfield_default },
	 { "MIN_BW", 22, 24, &umr_bitfield_default },
	 { "OSD_LIMITER_ENABLE", 25, 25, &umr_bitfield_default },
	 { "MAX_OSD", 26, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDAGB0_RDCLI5[] = {
	 { "VIRT_CHAN", 0, 2, &umr_bitfield_default },
	 { "CHECK_TLB_CREDIT", 3, 3, &umr_bitfield_default },
	 { "URG_HIGH", 4, 7, &umr_bitfield_default },
	 { "URG_LOW", 8, 11, &umr_bitfield_default },
	 { "MAX_BW_ENABLE", 12, 12, &umr_bitfield_default },
	 { "MAX_BW", 13, 20, &umr_bitfield_default },
	 { "MIN_BW_ENABLE", 21, 21, &umr_bitfield_default },
	 { "MIN_BW", 22, 24, &umr_bitfield_default },
	 { "OSD_LIMITER_ENABLE", 25, 25, &umr_bitfield_default },
	 { "MAX_OSD", 26, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDAGB0_RDCLI6[] = {
	 { "VIRT_CHAN", 0, 2, &umr_bitfield_default },
	 { "CHECK_TLB_CREDIT", 3, 3, &umr_bitfield_default },
	 { "URG_HIGH", 4, 7, &umr_bitfield_default },
	 { "URG_LOW", 8, 11, &umr_bitfield_default },
	 { "MAX_BW_ENABLE", 12, 12, &umr_bitfield_default },
	 { "MAX_BW", 13, 20, &umr_bitfield_default },
	 { "MIN_BW_ENABLE", 21, 21, &umr_bitfield_default },
	 { "MIN_BW", 22, 24, &umr_bitfield_default },
	 { "OSD_LIMITER_ENABLE", 25, 25, &umr_bitfield_default },
	 { "MAX_OSD", 26, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDAGB0_RDCLI7[] = {
	 { "VIRT_CHAN", 0, 2, &umr_bitfield_default },
	 { "CHECK_TLB_CREDIT", 3, 3, &umr_bitfield_default },
	 { "URG_HIGH", 4, 7, &umr_bitfield_default },
	 { "URG_LOW", 8, 11, &umr_bitfield_default },
	 { "MAX_BW_ENABLE", 12, 12, &umr_bitfield_default },
	 { "MAX_BW", 13, 20, &umr_bitfield_default },
	 { "MIN_BW_ENABLE", 21, 21, &umr_bitfield_default },
	 { "MIN_BW", 22, 24, &umr_bitfield_default },
	 { "OSD_LIMITER_ENABLE", 25, 25, &umr_bitfield_default },
	 { "MAX_OSD", 26, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDAGB0_RDCLI8[] = {
	 { "VIRT_CHAN", 0, 2, &umr_bitfield_default },
	 { "CHECK_TLB_CREDIT", 3, 3, &umr_bitfield_default },
	 { "URG_HIGH", 4, 7, &umr_bitfield_default },
	 { "URG_LOW", 8, 11, &umr_bitfield_default },
	 { "MAX_BW_ENABLE", 12, 12, &umr_bitfield_default },
	 { "MAX_BW", 13, 20, &umr_bitfield_default },
	 { "MIN_BW_ENABLE", 21, 21, &umr_bitfield_default },
	 { "MIN_BW", 22, 24, &umr_bitfield_default },
	 { "OSD_LIMITER_ENABLE", 25, 25, &umr_bitfield_default },
	 { "MAX_OSD", 26, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDAGB0_RDCLI9[] = {
	 { "VIRT_CHAN", 0, 2, &umr_bitfield_default },
	 { "CHECK_TLB_CREDIT", 3, 3, &umr_bitfield_default },
	 { "URG_HIGH", 4, 7, &umr_bitfield_default },
	 { "URG_LOW", 8, 11, &umr_bitfield_default },
	 { "MAX_BW_ENABLE", 12, 12, &umr_bitfield_default },
	 { "MAX_BW", 13, 20, &umr_bitfield_default },
	 { "MIN_BW_ENABLE", 21, 21, &umr_bitfield_default },
	 { "MIN_BW", 22, 24, &umr_bitfield_default },
	 { "OSD_LIMITER_ENABLE", 25, 25, &umr_bitfield_default },
	 { "MAX_OSD", 26, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDAGB0_RDCLI10[] = {
	 { "VIRT_CHAN", 0, 2, &umr_bitfield_default },
	 { "CHECK_TLB_CREDIT", 3, 3, &umr_bitfield_default },
	 { "URG_HIGH", 4, 7, &umr_bitfield_default },
	 { "URG_LOW", 8, 11, &umr_bitfield_default },
	 { "MAX_BW_ENABLE", 12, 12, &umr_bitfield_default },
	 { "MAX_BW", 13, 20, &umr_bitfield_default },
	 { "MIN_BW_ENABLE", 21, 21, &umr_bitfield_default },
	 { "MIN_BW", 22, 24, &umr_bitfield_default },
	 { "OSD_LIMITER_ENABLE", 25, 25, &umr_bitfield_default },
	 { "MAX_OSD", 26, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDAGB0_RDCLI11[] = {
	 { "VIRT_CHAN", 0, 2, &umr_bitfield_default },
	 { "CHECK_TLB_CREDIT", 3, 3, &umr_bitfield_default },
	 { "URG_HIGH", 4, 7, &umr_bitfield_default },
	 { "URG_LOW", 8, 11, &umr_bitfield_default },
	 { "MAX_BW_ENABLE", 12, 12, &umr_bitfield_default },
	 { "MAX_BW", 13, 20, &umr_bitfield_default },
	 { "MIN_BW_ENABLE", 21, 21, &umr_bitfield_default },
	 { "MIN_BW", 22, 24, &umr_bitfield_default },
	 { "OSD_LIMITER_ENABLE", 25, 25, &umr_bitfield_default },
	 { "MAX_OSD", 26, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDAGB0_RDCLI12[] = {
	 { "VIRT_CHAN", 0, 2, &umr_bitfield_default },
	 { "CHECK_TLB_CREDIT", 3, 3, &umr_bitfield_default },
	 { "URG_HIGH", 4, 7, &umr_bitfield_default },
	 { "URG_LOW", 8, 11, &umr_bitfield_default },
	 { "MAX_BW_ENABLE", 12, 12, &umr_bitfield_default },
	 { "MAX_BW", 13, 20, &umr_bitfield_default },
	 { "MIN_BW_ENABLE", 21, 21, &umr_bitfield_default },
	 { "MIN_BW", 22, 24, &umr_bitfield_default },
	 { "OSD_LIMITER_ENABLE", 25, 25, &umr_bitfield_default },
	 { "MAX_OSD", 26, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDAGB0_RDCLI13[] = {
	 { "VIRT_CHAN", 0, 2, &umr_bitfield_default },
	 { "CHECK_TLB_CREDIT", 3, 3, &umr_bitfield_default },
	 { "URG_HIGH", 4, 7, &umr_bitfield_default },
	 { "URG_LOW", 8, 11, &umr_bitfield_default },
	 { "MAX_BW_ENABLE", 12, 12, &umr_bitfield_default },
	 { "MAX_BW", 13, 20, &umr_bitfield_default },
	 { "MIN_BW_ENABLE", 21, 21, &umr_bitfield_default },
	 { "MIN_BW", 22, 24, &umr_bitfield_default },
	 { "OSD_LIMITER_ENABLE", 25, 25, &umr_bitfield_default },
	 { "MAX_OSD", 26, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDAGB0_RDCLI14[] = {
	 { "VIRT_CHAN", 0, 2, &umr_bitfield_default },
	 { "CHECK_TLB_CREDIT", 3, 3, &umr_bitfield_default },
	 { "URG_HIGH", 4, 7, &umr_bitfield_default },
	 { "URG_LOW", 8, 11, &umr_bitfield_default },
	 { "MAX_BW_ENABLE", 12, 12, &umr_bitfield_default },
	 { "MAX_BW", 13, 20, &umr_bitfield_default },
	 { "MIN_BW_ENABLE", 21, 21, &umr_bitfield_default },
	 { "MIN_BW", 22, 24, &umr_bitfield_default },
	 { "OSD_LIMITER_ENABLE", 25, 25, &umr_bitfield_default },
	 { "MAX_OSD", 26, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDAGB0_RDCLI15[] = {
	 { "VIRT_CHAN", 0, 2, &umr_bitfield_default },
	 { "CHECK_TLB_CREDIT", 3, 3, &umr_bitfield_default },
	 { "URG_HIGH", 4, 7, &umr_bitfield_default },
	 { "URG_LOW", 8, 11, &umr_bitfield_default },
	 { "MAX_BW_ENABLE", 12, 12, &umr_bitfield_default },
	 { "MAX_BW", 13, 20, &umr_bitfield_default },
	 { "MIN_BW_ENABLE", 21, 21, &umr_bitfield_default },
	 { "MIN_BW", 22, 24, &umr_bitfield_default },
	 { "OSD_LIMITER_ENABLE", 25, 25, &umr_bitfield_default },
	 { "MAX_OSD", 26, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDAGB0_RD_CNTL[] = {
	 { "SCLK_FREQ", 0, 3, &umr_bitfield_default },
	 { "CLI_MAX_BW_WINDOW", 4, 9, &umr_bitfield_default },
	 { "VC_MAX_BW_WINDOW", 10, 15, &umr_bitfield_default },
	 { "IO_LEVEL_OVERRIDE_ENABLE", 16, 16, &umr_bitfield_default },
	 { "IO_LEVEL", 17, 19, &umr_bitfield_default },
	 { "IO_LEVEL_COMPLY_VC", 20, 22, &umr_bitfield_default },
	 { "SHARE_VC_NUM", 23, 25, &umr_bitfield_default },
};
static struct umr_bitfield mmDAGB0_RD_GMI_CNTL[] = {
	 { "EA_CREDIT", 0, 5, &umr_bitfield_default },
	 { "LEVEL", 6, 8, &umr_bitfield_default },
	 { "MAX_BURST", 9, 12, &umr_bitfield_default },
	 { "LAZY_TIMER", 13, 16, &umr_bitfield_default },
};
static struct umr_bitfield mmDAGB0_RD_ADDR_DAGB[] = {
	 { "DAGB_ENABLE", 0, 2, &umr_bitfield_default },
	 { "ENABLE_JUMP_AHEAD", 3, 5, &umr_bitfield_default },
	 { "DISABLE_SELF_INIT", 6, 6, &umr_bitfield_default },
	 { "WHOAMI", 7, 12, &umr_bitfield_default },
};
static struct umr_bitfield mmDAGB0_RD_OUTPUT_DAGB_MAX_BURST[] = {
	 { "VC0", 0, 3, &umr_bitfield_default },
	 { "VC1", 4, 7, &umr_bitfield_default },
	 { "VC2", 8, 11, &umr_bitfield_default },
	 { "VC3", 12, 15, &umr_bitfield_default },
	 { "VC4", 16, 19, &umr_bitfield_default },
	 { "VC5", 20, 23, &umr_bitfield_default },
	 { "VC6", 24, 27, &umr_bitfield_default },
	 { "VC7", 28, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDAGB0_RD_OUTPUT_DAGB_LAZY_TIMER[] = {
	 { "VC0", 0, 3, &umr_bitfield_default },
	 { "VC1", 4, 7, &umr_bitfield_default },
	 { "VC2", 8, 11, &umr_bitfield_default },
	 { "VC3", 12, 15, &umr_bitfield_default },
	 { "VC4", 16, 19, &umr_bitfield_default },
	 { "VC5", 20, 23, &umr_bitfield_default },
	 { "VC6", 24, 27, &umr_bitfield_default },
	 { "VC7", 28, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDAGB0_RD_CGTT_CLK_CTRL[] = {
	 { "ON_DELAY", 0, 3, &umr_bitfield_default },
	 { "OFF_HYSTERESIS", 4, 11, &umr_bitfield_default },
	 { "SOFT_STALL_OVERRIDE", 22, 22, &umr_bitfield_default },
	 { "LS_OVERRIDE", 27, 27, &umr_bitfield_default },
	 { "LS_OVERRIDE_WRITE", 28, 28, &umr_bitfield_default },
	 { "LS_OVERRIDE_READ", 29, 29, &umr_bitfield_default },
	 { "LS_OVERRIDE_RETURN", 30, 30, &umr_bitfield_default },
	 { "LS_OVERRIDE_REGISTER", 31, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDAGB0_L1TLB_RD_CGTT_CLK_CTRL[] = {
	 { "ON_DELAY", 0, 3, &umr_bitfield_default },
	 { "OFF_HYSTERESIS", 4, 11, &umr_bitfield_default },
	 { "SOFT_STALL_OVERRIDE", 22, 22, &umr_bitfield_default },
	 { "LS_OVERRIDE", 27, 27, &umr_bitfield_default },
	 { "LS_OVERRIDE_WRITE", 28, 28, &umr_bitfield_default },
	 { "LS_OVERRIDE_READ", 29, 29, &umr_bitfield_default },
	 { "LS_OVERRIDE_RETURN", 30, 30, &umr_bitfield_default },
	 { "LS_OVERRIDE_REGISTER", 31, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDAGB0_ATCVM_RD_CGTT_CLK_CTRL[] = {
	 { "ON_DELAY", 0, 3, &umr_bitfield_default },
	 { "OFF_HYSTERESIS", 4, 11, &umr_bitfield_default },
	 { "SOFT_STALL_OVERRIDE", 22, 22, &umr_bitfield_default },
	 { "LS_OVERRIDE", 27, 27, &umr_bitfield_default },
	 { "LS_OVERRIDE_WRITE", 28, 28, &umr_bitfield_default },
	 { "LS_OVERRIDE_READ", 29, 29, &umr_bitfield_default },
	 { "LS_OVERRIDE_RETURN", 30, 30, &umr_bitfield_default },
	 { "LS_OVERRIDE_REGISTER", 31, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDAGB0_RD_ADDR_DAGB_MAX_BURST0[] = {
	 { "CLIENT0", 0, 3, &umr_bitfield_default },
	 { "CLIENT1", 4, 7, &umr_bitfield_default },
	 { "CLIENT2", 8, 11, &umr_bitfield_default },
	 { "CLIENT3", 12, 15, &umr_bitfield_default },
	 { "CLIENT4", 16, 19, &umr_bitfield_default },
	 { "CLIENT5", 20, 23, &umr_bitfield_default },
	 { "CLIENT6", 24, 27, &umr_bitfield_default },
	 { "CLIENT7", 28, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDAGB0_RD_ADDR_DAGB_LAZY_TIMER0[] = {
	 { "CLIENT0", 0, 3, &umr_bitfield_default },
	 { "CLIENT1", 4, 7, &umr_bitfield_default },
	 { "CLIENT2", 8, 11, &umr_bitfield_default },
	 { "CLIENT3", 12, 15, &umr_bitfield_default },
	 { "CLIENT4", 16, 19, &umr_bitfield_default },
	 { "CLIENT5", 20, 23, &umr_bitfield_default },
	 { "CLIENT6", 24, 27, &umr_bitfield_default },
	 { "CLIENT7", 28, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDAGB0_RD_ADDR_DAGB_MAX_BURST1[] = {
	 { "CLIENT8", 0, 3, &umr_bitfield_default },
	 { "CLIENT9", 4, 7, &umr_bitfield_default },
	 { "CLIENT10", 8, 11, &umr_bitfield_default },
	 { "CLIENT11", 12, 15, &umr_bitfield_default },
	 { "CLIENT12", 16, 19, &umr_bitfield_default },
	 { "CLIENT13", 20, 23, &umr_bitfield_default },
	 { "CLIENT14", 24, 27, &umr_bitfield_default },
	 { "CLIENT15", 28, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDAGB0_RD_ADDR_DAGB_LAZY_TIMER1[] = {
	 { "CLIENT8", 0, 3, &umr_bitfield_default },
	 { "CLIENT9", 4, 7, &umr_bitfield_default },
	 { "CLIENT10", 8, 11, &umr_bitfield_default },
	 { "CLIENT11", 12, 15, &umr_bitfield_default },
	 { "CLIENT12", 16, 19, &umr_bitfield_default },
	 { "CLIENT13", 20, 23, &umr_bitfield_default },
	 { "CLIENT14", 24, 27, &umr_bitfield_default },
	 { "CLIENT15", 28, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDAGB0_RD_VC0_CNTL[] = {
	 { "STOR_CREDIT", 0, 4, &umr_bitfield_default },
	 { "EA_CREDIT", 5, 10, &umr_bitfield_default },
	 { "MAX_BW_ENABLE", 11, 11, &umr_bitfield_default },
	 { "MAX_BW", 12, 19, &umr_bitfield_default },
	 { "MIN_BW_ENABLE", 20, 20, &umr_bitfield_default },
	 { "MIN_BW", 21, 23, &umr_bitfield_default },
	 { "OSD_LIMITER_ENABLE", 24, 24, &umr_bitfield_default },
	 { "MAX_OSD", 25, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDAGB0_RD_VC1_CNTL[] = {
	 { "STOR_CREDIT", 0, 4, &umr_bitfield_default },
	 { "EA_CREDIT", 5, 10, &umr_bitfield_default },
	 { "MAX_BW_ENABLE", 11, 11, &umr_bitfield_default },
	 { "MAX_BW", 12, 19, &umr_bitfield_default },
	 { "MIN_BW_ENABLE", 20, 20, &umr_bitfield_default },
	 { "MIN_BW", 21, 23, &umr_bitfield_default },
	 { "OSD_LIMITER_ENABLE", 24, 24, &umr_bitfield_default },
	 { "MAX_OSD", 25, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDAGB0_RD_VC2_CNTL[] = {
	 { "STOR_CREDIT", 0, 4, &umr_bitfield_default },
	 { "EA_CREDIT", 5, 10, &umr_bitfield_default },
	 { "MAX_BW_ENABLE", 11, 11, &umr_bitfield_default },
	 { "MAX_BW", 12, 19, &umr_bitfield_default },
	 { "MIN_BW_ENABLE", 20, 20, &umr_bitfield_default },
	 { "MIN_BW", 21, 23, &umr_bitfield_default },
	 { "OSD_LIMITER_ENABLE", 24, 24, &umr_bitfield_default },
	 { "MAX_OSD", 25, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDAGB0_RD_VC3_CNTL[] = {
	 { "STOR_CREDIT", 0, 4, &umr_bitfield_default },
	 { "EA_CREDIT", 5, 10, &umr_bitfield_default },
	 { "MAX_BW_ENABLE", 11, 11, &umr_bitfield_default },
	 { "MAX_BW", 12, 19, &umr_bitfield_default },
	 { "MIN_BW_ENABLE", 20, 20, &umr_bitfield_default },
	 { "MIN_BW", 21, 23, &umr_bitfield_default },
	 { "OSD_LIMITER_ENABLE", 24, 24, &umr_bitfield_default },
	 { "MAX_OSD", 25, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDAGB0_RD_VC4_CNTL[] = {
	 { "STOR_CREDIT", 0, 4, &umr_bitfield_default },
	 { "EA_CREDIT", 5, 10, &umr_bitfield_default },
	 { "MAX_BW_ENABLE", 11, 11, &umr_bitfield_default },
	 { "MAX_BW", 12, 19, &umr_bitfield_default },
	 { "MIN_BW_ENABLE", 20, 20, &umr_bitfield_default },
	 { "MIN_BW", 21, 23, &umr_bitfield_default },
	 { "OSD_LIMITER_ENABLE", 24, 24, &umr_bitfield_default },
	 { "MAX_OSD", 25, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDAGB0_RD_VC5_CNTL[] = {
	 { "STOR_CREDIT", 0, 4, &umr_bitfield_default },
	 { "EA_CREDIT", 5, 10, &umr_bitfield_default },
	 { "MAX_BW_ENABLE", 11, 11, &umr_bitfield_default },
	 { "MAX_BW", 12, 19, &umr_bitfield_default },
	 { "MIN_BW_ENABLE", 20, 20, &umr_bitfield_default },
	 { "MIN_BW", 21, 23, &umr_bitfield_default },
	 { "OSD_LIMITER_ENABLE", 24, 24, &umr_bitfield_default },
	 { "MAX_OSD", 25, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDAGB0_RD_VC6_CNTL[] = {
	 { "STOR_CREDIT", 0, 4, &umr_bitfield_default },
	 { "EA_CREDIT", 5, 10, &umr_bitfield_default },
	 { "MAX_BW_ENABLE", 11, 11, &umr_bitfield_default },
	 { "MAX_BW", 12, 19, &umr_bitfield_default },
	 { "MIN_BW_ENABLE", 20, 20, &umr_bitfield_default },
	 { "MIN_BW", 21, 23, &umr_bitfield_default },
	 { "OSD_LIMITER_ENABLE", 24, 24, &umr_bitfield_default },
	 { "MAX_OSD", 25, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDAGB0_RD_VC7_CNTL[] = {
	 { "STOR_CREDIT", 0, 4, &umr_bitfield_default },
	 { "EA_CREDIT", 5, 10, &umr_bitfield_default },
	 { "MAX_BW_ENABLE", 11, 11, &umr_bitfield_default },
	 { "MAX_BW", 12, 19, &umr_bitfield_default },
	 { "MIN_BW_ENABLE", 20, 20, &umr_bitfield_default },
	 { "MIN_BW", 21, 23, &umr_bitfield_default },
	 { "OSD_LIMITER_ENABLE", 24, 24, &umr_bitfield_default },
	 { "MAX_OSD", 25, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDAGB0_RD_CNTL_MISC[] = {
	 { "STOR_POOL_CREDIT", 0, 5, &umr_bitfield_default },
	 { "EA_POOL_CREDIT", 6, 12, &umr_bitfield_default },
	 { "IO_EA_CREDIT", 13, 18, &umr_bitfield_default },
	 { "STOR_CC_LEGACY_MODE", 19, 19, &umr_bitfield_default },
	 { "EA_CC_LEGACY_MODE", 20, 20, &umr_bitfield_default },
	 { "UTCL2_CID", 21, 25, &umr_bitfield_default },
};
static struct umr_bitfield mmDAGB0_RD_TLB_CREDIT[] = {
	 { "TLB0", 0, 4, &umr_bitfield_default },
	 { "TLB1", 5, 9, &umr_bitfield_default },
	 { "TLB2", 10, 14, &umr_bitfield_default },
	 { "TLB3", 15, 19, &umr_bitfield_default },
	 { "TLB4", 20, 24, &umr_bitfield_default },
	 { "TLB5", 25, 29, &umr_bitfield_default },
};
static struct umr_bitfield mmDAGB0_RDCLI_ASK_PENDING[] = {
	 { "BUSY", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDAGB0_RDCLI_GO_PENDING[] = {
	 { "BUSY", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDAGB0_RDCLI_GBLSEND_PENDING[] = {
	 { "BUSY", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDAGB0_RDCLI_TLB_PENDING[] = {
	 { "BUSY", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDAGB0_RDCLI_OARB_PENDING[] = {
	 { "BUSY", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDAGB0_RDCLI_OSD_PENDING[] = {
	 { "BUSY", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDAGB0_WRCLI0[] = {
	 { "VIRT_CHAN", 0, 2, &umr_bitfield_default },
	 { "CHECK_TLB_CREDIT", 3, 3, &umr_bitfield_default },
	 { "URG_HIGH", 4, 7, &umr_bitfield_default },
	 { "URG_LOW", 8, 11, &umr_bitfield_default },
	 { "MAX_BW_ENABLE", 12, 12, &umr_bitfield_default },
	 { "MAX_BW", 13, 20, &umr_bitfield_default },
	 { "MIN_BW_ENABLE", 21, 21, &umr_bitfield_default },
	 { "MIN_BW", 22, 24, &umr_bitfield_default },
	 { "OSD_LIMITER_ENABLE", 25, 25, &umr_bitfield_default },
	 { "MAX_OSD", 26, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDAGB0_WRCLI1[] = {
	 { "VIRT_CHAN", 0, 2, &umr_bitfield_default },
	 { "CHECK_TLB_CREDIT", 3, 3, &umr_bitfield_default },
	 { "URG_HIGH", 4, 7, &umr_bitfield_default },
	 { "URG_LOW", 8, 11, &umr_bitfield_default },
	 { "MAX_BW_ENABLE", 12, 12, &umr_bitfield_default },
	 { "MAX_BW", 13, 20, &umr_bitfield_default },
	 { "MIN_BW_ENABLE", 21, 21, &umr_bitfield_default },
	 { "MIN_BW", 22, 24, &umr_bitfield_default },
	 { "OSD_LIMITER_ENABLE", 25, 25, &umr_bitfield_default },
	 { "MAX_OSD", 26, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDAGB0_WRCLI2[] = {
	 { "VIRT_CHAN", 0, 2, &umr_bitfield_default },
	 { "CHECK_TLB_CREDIT", 3, 3, &umr_bitfield_default },
	 { "URG_HIGH", 4, 7, &umr_bitfield_default },
	 { "URG_LOW", 8, 11, &umr_bitfield_default },
	 { "MAX_BW_ENABLE", 12, 12, &umr_bitfield_default },
	 { "MAX_BW", 13, 20, &umr_bitfield_default },
	 { "MIN_BW_ENABLE", 21, 21, &umr_bitfield_default },
	 { "MIN_BW", 22, 24, &umr_bitfield_default },
	 { "OSD_LIMITER_ENABLE", 25, 25, &umr_bitfield_default },
	 { "MAX_OSD", 26, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDAGB0_WRCLI3[] = {
	 { "VIRT_CHAN", 0, 2, &umr_bitfield_default },
	 { "CHECK_TLB_CREDIT", 3, 3, &umr_bitfield_default },
	 { "URG_HIGH", 4, 7, &umr_bitfield_default },
	 { "URG_LOW", 8, 11, &umr_bitfield_default },
	 { "MAX_BW_ENABLE", 12, 12, &umr_bitfield_default },
	 { "MAX_BW", 13, 20, &umr_bitfield_default },
	 { "MIN_BW_ENABLE", 21, 21, &umr_bitfield_default },
	 { "MIN_BW", 22, 24, &umr_bitfield_default },
	 { "OSD_LIMITER_ENABLE", 25, 25, &umr_bitfield_default },
	 { "MAX_OSD", 26, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDAGB0_WRCLI4[] = {
	 { "VIRT_CHAN", 0, 2, &umr_bitfield_default },
	 { "CHECK_TLB_CREDIT", 3, 3, &umr_bitfield_default },
	 { "URG_HIGH", 4, 7, &umr_bitfield_default },
	 { "URG_LOW", 8, 11, &umr_bitfield_default },
	 { "MAX_BW_ENABLE", 12, 12, &umr_bitfield_default },
	 { "MAX_BW", 13, 20, &umr_bitfield_default },
	 { "MIN_BW_ENABLE", 21, 21, &umr_bitfield_default },
	 { "MIN_BW", 22, 24, &umr_bitfield_default },
	 { "OSD_LIMITER_ENABLE", 25, 25, &umr_bitfield_default },
	 { "MAX_OSD", 26, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDAGB0_WRCLI5[] = {
	 { "VIRT_CHAN", 0, 2, &umr_bitfield_default },
	 { "CHECK_TLB_CREDIT", 3, 3, &umr_bitfield_default },
	 { "URG_HIGH", 4, 7, &umr_bitfield_default },
	 { "URG_LOW", 8, 11, &umr_bitfield_default },
	 { "MAX_BW_ENABLE", 12, 12, &umr_bitfield_default },
	 { "MAX_BW", 13, 20, &umr_bitfield_default },
	 { "MIN_BW_ENABLE", 21, 21, &umr_bitfield_default },
	 { "MIN_BW", 22, 24, &umr_bitfield_default },
	 { "OSD_LIMITER_ENABLE", 25, 25, &umr_bitfield_default },
	 { "MAX_OSD", 26, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDAGB0_WRCLI6[] = {
	 { "VIRT_CHAN", 0, 2, &umr_bitfield_default },
	 { "CHECK_TLB_CREDIT", 3, 3, &umr_bitfield_default },
	 { "URG_HIGH", 4, 7, &umr_bitfield_default },
	 { "URG_LOW", 8, 11, &umr_bitfield_default },
	 { "MAX_BW_ENABLE", 12, 12, &umr_bitfield_default },
	 { "MAX_BW", 13, 20, &umr_bitfield_default },
	 { "MIN_BW_ENABLE", 21, 21, &umr_bitfield_default },
	 { "MIN_BW", 22, 24, &umr_bitfield_default },
	 { "OSD_LIMITER_ENABLE", 25, 25, &umr_bitfield_default },
	 { "MAX_OSD", 26, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDAGB0_WRCLI7[] = {
	 { "VIRT_CHAN", 0, 2, &umr_bitfield_default },
	 { "CHECK_TLB_CREDIT", 3, 3, &umr_bitfield_default },
	 { "URG_HIGH", 4, 7, &umr_bitfield_default },
	 { "URG_LOW", 8, 11, &umr_bitfield_default },
	 { "MAX_BW_ENABLE", 12, 12, &umr_bitfield_default },
	 { "MAX_BW", 13, 20, &umr_bitfield_default },
	 { "MIN_BW_ENABLE", 21, 21, &umr_bitfield_default },
	 { "MIN_BW", 22, 24, &umr_bitfield_default },
	 { "OSD_LIMITER_ENABLE", 25, 25, &umr_bitfield_default },
	 { "MAX_OSD", 26, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDAGB0_WRCLI8[] = {
	 { "VIRT_CHAN", 0, 2, &umr_bitfield_default },
	 { "CHECK_TLB_CREDIT", 3, 3, &umr_bitfield_default },
	 { "URG_HIGH", 4, 7, &umr_bitfield_default },
	 { "URG_LOW", 8, 11, &umr_bitfield_default },
	 { "MAX_BW_ENABLE", 12, 12, &umr_bitfield_default },
	 { "MAX_BW", 13, 20, &umr_bitfield_default },
	 { "MIN_BW_ENABLE", 21, 21, &umr_bitfield_default },
	 { "MIN_BW", 22, 24, &umr_bitfield_default },
	 { "OSD_LIMITER_ENABLE", 25, 25, &umr_bitfield_default },
	 { "MAX_OSD", 26, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDAGB0_WRCLI9[] = {
	 { "VIRT_CHAN", 0, 2, &umr_bitfield_default },
	 { "CHECK_TLB_CREDIT", 3, 3, &umr_bitfield_default },
	 { "URG_HIGH", 4, 7, &umr_bitfield_default },
	 { "URG_LOW", 8, 11, &umr_bitfield_default },
	 { "MAX_BW_ENABLE", 12, 12, &umr_bitfield_default },
	 { "MAX_BW", 13, 20, &umr_bitfield_default },
	 { "MIN_BW_ENABLE", 21, 21, &umr_bitfield_default },
	 { "MIN_BW", 22, 24, &umr_bitfield_default },
	 { "OSD_LIMITER_ENABLE", 25, 25, &umr_bitfield_default },
	 { "MAX_OSD", 26, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDAGB0_WRCLI10[] = {
	 { "VIRT_CHAN", 0, 2, &umr_bitfield_default },
	 { "CHECK_TLB_CREDIT", 3, 3, &umr_bitfield_default },
	 { "URG_HIGH", 4, 7, &umr_bitfield_default },
	 { "URG_LOW", 8, 11, &umr_bitfield_default },
	 { "MAX_BW_ENABLE", 12, 12, &umr_bitfield_default },
	 { "MAX_BW", 13, 20, &umr_bitfield_default },
	 { "MIN_BW_ENABLE", 21, 21, &umr_bitfield_default },
	 { "MIN_BW", 22, 24, &umr_bitfield_default },
	 { "OSD_LIMITER_ENABLE", 25, 25, &umr_bitfield_default },
	 { "MAX_OSD", 26, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDAGB0_WRCLI11[] = {
	 { "VIRT_CHAN", 0, 2, &umr_bitfield_default },
	 { "CHECK_TLB_CREDIT", 3, 3, &umr_bitfield_default },
	 { "URG_HIGH", 4, 7, &umr_bitfield_default },
	 { "URG_LOW", 8, 11, &umr_bitfield_default },
	 { "MAX_BW_ENABLE", 12, 12, &umr_bitfield_default },
	 { "MAX_BW", 13, 20, &umr_bitfield_default },
	 { "MIN_BW_ENABLE", 21, 21, &umr_bitfield_default },
	 { "MIN_BW", 22, 24, &umr_bitfield_default },
	 { "OSD_LIMITER_ENABLE", 25, 25, &umr_bitfield_default },
	 { "MAX_OSD", 26, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDAGB0_WRCLI12[] = {
	 { "VIRT_CHAN", 0, 2, &umr_bitfield_default },
	 { "CHECK_TLB_CREDIT", 3, 3, &umr_bitfield_default },
	 { "URG_HIGH", 4, 7, &umr_bitfield_default },
	 { "URG_LOW", 8, 11, &umr_bitfield_default },
	 { "MAX_BW_ENABLE", 12, 12, &umr_bitfield_default },
	 { "MAX_BW", 13, 20, &umr_bitfield_default },
	 { "MIN_BW_ENABLE", 21, 21, &umr_bitfield_default },
	 { "MIN_BW", 22, 24, &umr_bitfield_default },
	 { "OSD_LIMITER_ENABLE", 25, 25, &umr_bitfield_default },
	 { "MAX_OSD", 26, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDAGB0_WRCLI13[] = {
	 { "VIRT_CHAN", 0, 2, &umr_bitfield_default },
	 { "CHECK_TLB_CREDIT", 3, 3, &umr_bitfield_default },
	 { "URG_HIGH", 4, 7, &umr_bitfield_default },
	 { "URG_LOW", 8, 11, &umr_bitfield_default },
	 { "MAX_BW_ENABLE", 12, 12, &umr_bitfield_default },
	 { "MAX_BW", 13, 20, &umr_bitfield_default },
	 { "MIN_BW_ENABLE", 21, 21, &umr_bitfield_default },
	 { "MIN_BW", 22, 24, &umr_bitfield_default },
	 { "OSD_LIMITER_ENABLE", 25, 25, &umr_bitfield_default },
	 { "MAX_OSD", 26, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDAGB0_WRCLI14[] = {
	 { "VIRT_CHAN", 0, 2, &umr_bitfield_default },
	 { "CHECK_TLB_CREDIT", 3, 3, &umr_bitfield_default },
	 { "URG_HIGH", 4, 7, &umr_bitfield_default },
	 { "URG_LOW", 8, 11, &umr_bitfield_default },
	 { "MAX_BW_ENABLE", 12, 12, &umr_bitfield_default },
	 { "MAX_BW", 13, 20, &umr_bitfield_default },
	 { "MIN_BW_ENABLE", 21, 21, &umr_bitfield_default },
	 { "MIN_BW", 22, 24, &umr_bitfield_default },
	 { "OSD_LIMITER_ENABLE", 25, 25, &umr_bitfield_default },
	 { "MAX_OSD", 26, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDAGB0_WRCLI15[] = {
	 { "VIRT_CHAN", 0, 2, &umr_bitfield_default },
	 { "CHECK_TLB_CREDIT", 3, 3, &umr_bitfield_default },
	 { "URG_HIGH", 4, 7, &umr_bitfield_default },
	 { "URG_LOW", 8, 11, &umr_bitfield_default },
	 { "MAX_BW_ENABLE", 12, 12, &umr_bitfield_default },
	 { "MAX_BW", 13, 20, &umr_bitfield_default },
	 { "MIN_BW_ENABLE", 21, 21, &umr_bitfield_default },
	 { "MIN_BW", 22, 24, &umr_bitfield_default },
	 { "OSD_LIMITER_ENABLE", 25, 25, &umr_bitfield_default },
	 { "MAX_OSD", 26, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDAGB0_WR_CNTL[] = {
	 { "SCLK_FREQ", 0, 3, &umr_bitfield_default },
	 { "CLI_MAX_BW_WINDOW", 4, 9, &umr_bitfield_default },
	 { "VC_MAX_BW_WINDOW", 10, 15, &umr_bitfield_default },
	 { "IO_LEVEL_OVERRIDE_ENABLE", 16, 16, &umr_bitfield_default },
	 { "IO_LEVEL", 17, 19, &umr_bitfield_default },
	 { "IO_LEVEL_COMPLY_VC", 20, 22, &umr_bitfield_default },
	 { "SHARE_VC_NUM", 23, 25, &umr_bitfield_default },
};
static struct umr_bitfield mmDAGB0_WR_GMI_CNTL[] = {
	 { "EA_CREDIT", 0, 5, &umr_bitfield_default },
	 { "LEVEL", 6, 8, &umr_bitfield_default },
	 { "MAX_BURST", 9, 12, &umr_bitfield_default },
	 { "LAZY_TIMER", 13, 16, &umr_bitfield_default },
};
static struct umr_bitfield mmDAGB0_WR_ADDR_DAGB[] = {
	 { "DAGB_ENABLE", 0, 2, &umr_bitfield_default },
	 { "ENABLE_JUMP_AHEAD", 3, 5, &umr_bitfield_default },
	 { "DISABLE_SELF_INIT", 6, 6, &umr_bitfield_default },
	 { "WHOAMI", 7, 12, &umr_bitfield_default },
};
static struct umr_bitfield mmDAGB0_WR_OUTPUT_DAGB_MAX_BURST[] = {
	 { "VC0", 0, 3, &umr_bitfield_default },
	 { "VC1", 4, 7, &umr_bitfield_default },
	 { "VC2", 8, 11, &umr_bitfield_default },
	 { "VC3", 12, 15, &umr_bitfield_default },
	 { "VC4", 16, 19, &umr_bitfield_default },
	 { "VC5", 20, 23, &umr_bitfield_default },
	 { "VC6", 24, 27, &umr_bitfield_default },
	 { "VC7", 28, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDAGB0_WR_OUTPUT_DAGB_LAZY_TIMER[] = {
	 { "VC0", 0, 3, &umr_bitfield_default },
	 { "VC1", 4, 7, &umr_bitfield_default },
	 { "VC2", 8, 11, &umr_bitfield_default },
	 { "VC3", 12, 15, &umr_bitfield_default },
	 { "VC4", 16, 19, &umr_bitfield_default },
	 { "VC5", 20, 23, &umr_bitfield_default },
	 { "VC6", 24, 27, &umr_bitfield_default },
	 { "VC7", 28, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDAGB0_WR_CGTT_CLK_CTRL[] = {
	 { "ON_DELAY", 0, 3, &umr_bitfield_default },
	 { "OFF_HYSTERESIS", 4, 11, &umr_bitfield_default },
	 { "SOFT_STALL_OVERRIDE", 22, 22, &umr_bitfield_default },
	 { "LS_OVERRIDE", 27, 27, &umr_bitfield_default },
	 { "LS_OVERRIDE_WRITE", 28, 28, &umr_bitfield_default },
	 { "LS_OVERRIDE_READ", 29, 29, &umr_bitfield_default },
	 { "LS_OVERRIDE_RETURN", 30, 30, &umr_bitfield_default },
	 { "LS_OVERRIDE_REGISTER", 31, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDAGB0_L1TLB_WR_CGTT_CLK_CTRL[] = {
	 { "ON_DELAY", 0, 3, &umr_bitfield_default },
	 { "OFF_HYSTERESIS", 4, 11, &umr_bitfield_default },
	 { "SOFT_STALL_OVERRIDE", 22, 22, &umr_bitfield_default },
	 { "LS_OVERRIDE", 27, 27, &umr_bitfield_default },
	 { "LS_OVERRIDE_WRITE", 28, 28, &umr_bitfield_default },
	 { "LS_OVERRIDE_READ", 29, 29, &umr_bitfield_default },
	 { "LS_OVERRIDE_RETURN", 30, 30, &umr_bitfield_default },
	 { "LS_OVERRIDE_REGISTER", 31, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDAGB0_ATCVM_WR_CGTT_CLK_CTRL[] = {
	 { "ON_DELAY", 0, 3, &umr_bitfield_default },
	 { "OFF_HYSTERESIS", 4, 11, &umr_bitfield_default },
	 { "SOFT_STALL_OVERRIDE", 22, 22, &umr_bitfield_default },
	 { "LS_OVERRIDE", 27, 27, &umr_bitfield_default },
	 { "LS_OVERRIDE_WRITE", 28, 28, &umr_bitfield_default },
	 { "LS_OVERRIDE_READ", 29, 29, &umr_bitfield_default },
	 { "LS_OVERRIDE_RETURN", 30, 30, &umr_bitfield_default },
	 { "LS_OVERRIDE_REGISTER", 31, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDAGB0_WR_ADDR_DAGB_MAX_BURST0[] = {
	 { "CLIENT0", 0, 3, &umr_bitfield_default },
	 { "CLIENT1", 4, 7, &umr_bitfield_default },
	 { "CLIENT2", 8, 11, &umr_bitfield_default },
	 { "CLIENT3", 12, 15, &umr_bitfield_default },
	 { "CLIENT4", 16, 19, &umr_bitfield_default },
	 { "CLIENT5", 20, 23, &umr_bitfield_default },
	 { "CLIENT6", 24, 27, &umr_bitfield_default },
	 { "CLIENT7", 28, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDAGB0_WR_ADDR_DAGB_LAZY_TIMER0[] = {
	 { "CLIENT0", 0, 3, &umr_bitfield_default },
	 { "CLIENT1", 4, 7, &umr_bitfield_default },
	 { "CLIENT2", 8, 11, &umr_bitfield_default },
	 { "CLIENT3", 12, 15, &umr_bitfield_default },
	 { "CLIENT4", 16, 19, &umr_bitfield_default },
	 { "CLIENT5", 20, 23, &umr_bitfield_default },
	 { "CLIENT6", 24, 27, &umr_bitfield_default },
	 { "CLIENT7", 28, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDAGB0_WR_ADDR_DAGB_MAX_BURST1[] = {
	 { "CLIENT8", 0, 3, &umr_bitfield_default },
	 { "CLIENT9", 4, 7, &umr_bitfield_default },
	 { "CLIENT10", 8, 11, &umr_bitfield_default },
	 { "CLIENT11", 12, 15, &umr_bitfield_default },
	 { "CLIENT12", 16, 19, &umr_bitfield_default },
	 { "CLIENT13", 20, 23, &umr_bitfield_default },
	 { "CLIENT14", 24, 27, &umr_bitfield_default },
	 { "CLIENT15", 28, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDAGB0_WR_ADDR_DAGB_LAZY_TIMER1[] = {
	 { "CLIENT8", 0, 3, &umr_bitfield_default },
	 { "CLIENT9", 4, 7, &umr_bitfield_default },
	 { "CLIENT10", 8, 11, &umr_bitfield_default },
	 { "CLIENT11", 12, 15, &umr_bitfield_default },
	 { "CLIENT12", 16, 19, &umr_bitfield_default },
	 { "CLIENT13", 20, 23, &umr_bitfield_default },
	 { "CLIENT14", 24, 27, &umr_bitfield_default },
	 { "CLIENT15", 28, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDAGB0_WR_DATA_DAGB[] = {
	 { "DAGB_ENABLE", 0, 2, &umr_bitfield_default },
	 { "ENABLE_JUMP_AHEAD", 3, 5, &umr_bitfield_default },
	 { "DISABLE_SELF_INIT", 6, 6, &umr_bitfield_default },
	 { "WHOAMI", 7, 12, &umr_bitfield_default },
};
static struct umr_bitfield mmDAGB0_WR_DATA_DAGB_MAX_BURST0[] = {
	 { "CLIENT0", 0, 3, &umr_bitfield_default },
	 { "CLIENT1", 4, 7, &umr_bitfield_default },
	 { "CLIENT2", 8, 11, &umr_bitfield_default },
	 { "CLIENT3", 12, 15, &umr_bitfield_default },
	 { "CLIENT4", 16, 19, &umr_bitfield_default },
	 { "CLIENT5", 20, 23, &umr_bitfield_default },
	 { "CLIENT6", 24, 27, &umr_bitfield_default },
	 { "CLIENT7", 28, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDAGB0_WR_DATA_DAGB_LAZY_TIMER0[] = {
	 { "CLIENT0", 0, 3, &umr_bitfield_default },
	 { "CLIENT1", 4, 7, &umr_bitfield_default },
	 { "CLIENT2", 8, 11, &umr_bitfield_default },
	 { "CLIENT3", 12, 15, &umr_bitfield_default },
	 { "CLIENT4", 16, 19, &umr_bitfield_default },
	 { "CLIENT5", 20, 23, &umr_bitfield_default },
	 { "CLIENT6", 24, 27, &umr_bitfield_default },
	 { "CLIENT7", 28, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDAGB0_WR_DATA_DAGB_MAX_BURST1[] = {
	 { "CLIENT8", 0, 3, &umr_bitfield_default },
	 { "CLIENT9", 4, 7, &umr_bitfield_default },
	 { "CLIENT10", 8, 11, &umr_bitfield_default },
	 { "CLIENT11", 12, 15, &umr_bitfield_default },
	 { "CLIENT12", 16, 19, &umr_bitfield_default },
	 { "CLIENT13", 20, 23, &umr_bitfield_default },
	 { "CLIENT14", 24, 27, &umr_bitfield_default },
	 { "CLIENT15", 28, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDAGB0_WR_DATA_DAGB_LAZY_TIMER1[] = {
	 { "CLIENT8", 0, 3, &umr_bitfield_default },
	 { "CLIENT9", 4, 7, &umr_bitfield_default },
	 { "CLIENT10", 8, 11, &umr_bitfield_default },
	 { "CLIENT11", 12, 15, &umr_bitfield_default },
	 { "CLIENT12", 16, 19, &umr_bitfield_default },
	 { "CLIENT13", 20, 23, &umr_bitfield_default },
	 { "CLIENT14", 24, 27, &umr_bitfield_default },
	 { "CLIENT15", 28, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDAGB0_WR_VC0_CNTL[] = {
	 { "STOR_CREDIT", 0, 4, &umr_bitfield_default },
	 { "EA_CREDIT", 5, 10, &umr_bitfield_default },
	 { "MAX_BW_ENABLE", 11, 11, &umr_bitfield_default },
	 { "MAX_BW", 12, 19, &umr_bitfield_default },
	 { "MIN_BW_ENABLE", 20, 20, &umr_bitfield_default },
	 { "MIN_BW", 21, 23, &umr_bitfield_default },
	 { "OSD_LIMITER_ENABLE", 24, 24, &umr_bitfield_default },
	 { "MAX_OSD", 25, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDAGB0_WR_VC1_CNTL[] = {
	 { "STOR_CREDIT", 0, 4, &umr_bitfield_default },
	 { "EA_CREDIT", 5, 10, &umr_bitfield_default },
	 { "MAX_BW_ENABLE", 11, 11, &umr_bitfield_default },
	 { "MAX_BW", 12, 19, &umr_bitfield_default },
	 { "MIN_BW_ENABLE", 20, 20, &umr_bitfield_default },
	 { "MIN_BW", 21, 23, &umr_bitfield_default },
	 { "OSD_LIMITER_ENABLE", 24, 24, &umr_bitfield_default },
	 { "MAX_OSD", 25, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDAGB0_WR_VC2_CNTL[] = {
	 { "STOR_CREDIT", 0, 4, &umr_bitfield_default },
	 { "EA_CREDIT", 5, 10, &umr_bitfield_default },
	 { "MAX_BW_ENABLE", 11, 11, &umr_bitfield_default },
	 { "MAX_BW", 12, 19, &umr_bitfield_default },
	 { "MIN_BW_ENABLE", 20, 20, &umr_bitfield_default },
	 { "MIN_BW", 21, 23, &umr_bitfield_default },
	 { "OSD_LIMITER_ENABLE", 24, 24, &umr_bitfield_default },
	 { "MAX_OSD", 25, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDAGB0_WR_VC3_CNTL[] = {
	 { "STOR_CREDIT", 0, 4, &umr_bitfield_default },
	 { "EA_CREDIT", 5, 10, &umr_bitfield_default },
	 { "MAX_BW_ENABLE", 11, 11, &umr_bitfield_default },
	 { "MAX_BW", 12, 19, &umr_bitfield_default },
	 { "MIN_BW_ENABLE", 20, 20, &umr_bitfield_default },
	 { "MIN_BW", 21, 23, &umr_bitfield_default },
	 { "OSD_LIMITER_ENABLE", 24, 24, &umr_bitfield_default },
	 { "MAX_OSD", 25, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDAGB0_WR_VC4_CNTL[] = {
	 { "STOR_CREDIT", 0, 4, &umr_bitfield_default },
	 { "EA_CREDIT", 5, 10, &umr_bitfield_default },
	 { "MAX_BW_ENABLE", 11, 11, &umr_bitfield_default },
	 { "MAX_BW", 12, 19, &umr_bitfield_default },
	 { "MIN_BW_ENABLE", 20, 20, &umr_bitfield_default },
	 { "MIN_BW", 21, 23, &umr_bitfield_default },
	 { "OSD_LIMITER_ENABLE", 24, 24, &umr_bitfield_default },
	 { "MAX_OSD", 25, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDAGB0_WR_VC5_CNTL[] = {
	 { "STOR_CREDIT", 0, 4, &umr_bitfield_default },
	 { "EA_CREDIT", 5, 10, &umr_bitfield_default },
	 { "MAX_BW_ENABLE", 11, 11, &umr_bitfield_default },
	 { "MAX_BW", 12, 19, &umr_bitfield_default },
	 { "MIN_BW_ENABLE", 20, 20, &umr_bitfield_default },
	 { "MIN_BW", 21, 23, &umr_bitfield_default },
	 { "OSD_LIMITER_ENABLE", 24, 24, &umr_bitfield_default },
	 { "MAX_OSD", 25, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDAGB0_WR_VC6_CNTL[] = {
	 { "STOR_CREDIT", 0, 4, &umr_bitfield_default },
	 { "EA_CREDIT", 5, 10, &umr_bitfield_default },
	 { "MAX_BW_ENABLE", 11, 11, &umr_bitfield_default },
	 { "MAX_BW", 12, 19, &umr_bitfield_default },
	 { "MIN_BW_ENABLE", 20, 20, &umr_bitfield_default },
	 { "MIN_BW", 21, 23, &umr_bitfield_default },
	 { "OSD_LIMITER_ENABLE", 24, 24, &umr_bitfield_default },
	 { "MAX_OSD", 25, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDAGB0_WR_VC7_CNTL[] = {
	 { "STOR_CREDIT", 0, 4, &umr_bitfield_default },
	 { "EA_CREDIT", 5, 10, &umr_bitfield_default },
	 { "MAX_BW_ENABLE", 11, 11, &umr_bitfield_default },
	 { "MAX_BW", 12, 19, &umr_bitfield_default },
	 { "MIN_BW_ENABLE", 20, 20, &umr_bitfield_default },
	 { "MIN_BW", 21, 23, &umr_bitfield_default },
	 { "OSD_LIMITER_ENABLE", 24, 24, &umr_bitfield_default },
	 { "MAX_OSD", 25, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDAGB0_WR_CNTL_MISC[] = {
	 { "STOR_POOL_CREDIT", 0, 5, &umr_bitfield_default },
	 { "EA_POOL_CREDIT", 6, 12, &umr_bitfield_default },
	 { "IO_EA_CREDIT", 13, 18, &umr_bitfield_default },
	 { "STOR_CC_LEGACY_MODE", 19, 19, &umr_bitfield_default },
	 { "EA_CC_LEGACY_MODE", 20, 20, &umr_bitfield_default },
	 { "UTCL2_CID", 21, 25, &umr_bitfield_default },
};
static struct umr_bitfield mmDAGB0_WR_TLB_CREDIT[] = {
	 { "TLB0", 0, 4, &umr_bitfield_default },
	 { "TLB1", 5, 9, &umr_bitfield_default },
	 { "TLB2", 10, 14, &umr_bitfield_default },
	 { "TLB3", 15, 19, &umr_bitfield_default },
	 { "TLB4", 20, 24, &umr_bitfield_default },
	 { "TLB5", 25, 29, &umr_bitfield_default },
};
static struct umr_bitfield mmDAGB0_WR_DATA_CREDIT[] = {
	 { "DLOCK_VC_CREDITS", 0, 7, &umr_bitfield_default },
	 { "LARGE_BURST_CREDITS", 8, 15, &umr_bitfield_default },
	 { "MIDDLE_BURST_CREDITS", 16, 23, &umr_bitfield_default },
	 { "SMALL_BURST_CREDITS", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDAGB0_WR_MISC_CREDIT[] = {
	 { "ATOMIC_CREDIT", 0, 5, &umr_bitfield_default },
	 { "DLOCK_VC_NUM", 6, 8, &umr_bitfield_default },
	 { "OSD_CREDIT", 9, 15, &umr_bitfield_default },
	 { "OSD_DLOCK_CREDIT", 16, 22, &umr_bitfield_default },
};
static struct umr_bitfield mmDAGB0_WRCLI_ASK_PENDING[] = {
	 { "BUSY", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDAGB0_WRCLI_GO_PENDING[] = {
	 { "BUSY", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDAGB0_WRCLI_GBLSEND_PENDING[] = {
	 { "BUSY", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDAGB0_WRCLI_TLB_PENDING[] = {
	 { "BUSY", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDAGB0_WRCLI_OARB_PENDING[] = {
	 { "BUSY", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDAGB0_WRCLI_OSD_PENDING[] = {
	 { "BUSY", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDAGB0_WRCLI_DBUS_ASK_PENDING[] = {
	 { "BUSY", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDAGB0_WRCLI_DBUS_GO_PENDING[] = {
	 { "BUSY", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDAGB0_DAGB_DLY[] = {
	 { "DLY", 0, 7, &umr_bitfield_default },
	 { "CLI", 8, 15, &umr_bitfield_default },
	 { "POS", 16, 19, &umr_bitfield_default },
};
static struct umr_bitfield mmDAGB0_CNTL_MISC[] = {
	 { "EA_VC0_REMAP", 0, 2, &umr_bitfield_default },
	 { "EA_VC1_REMAP", 3, 5, &umr_bitfield_default },
	 { "EA_VC2_REMAP", 6, 8, &umr_bitfield_default },
	 { "EA_VC3_REMAP", 9, 11, &umr_bitfield_default },
	 { "EA_VC4_REMAP", 12, 14, &umr_bitfield_default },
	 { "EA_VC5_REMAP", 15, 17, &umr_bitfield_default },
	 { "EA_VC6_REMAP", 18, 20, &umr_bitfield_default },
	 { "EA_VC7_REMAP", 21, 23, &umr_bitfield_default },
	 { "BW_INIT_CYCLE", 24, 29, &umr_bitfield_default },
	 { "BW_RW_GAP_CYCLE", 30, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDAGB0_CNTL_MISC2[] = {
	 { "URG_BOOST_ENABLE", 0, 0, &umr_bitfield_default },
	 { "URG_HALT_ENABLE", 1, 1, &umr_bitfield_default },
	 { "DISABLE_WRREQ_CG", 2, 2, &umr_bitfield_default },
	 { "DISABLE_WRRET_CG", 3, 3, &umr_bitfield_default },
	 { "DISABLE_RDREQ_CG", 4, 4, &umr_bitfield_default },
	 { "DISABLE_RDRET_CG", 5, 5, &umr_bitfield_default },
	 { "DISABLE_TLBWR_CG", 6, 6, &umr_bitfield_default },
	 { "DISABLE_TLBRD_CG", 7, 7, &umr_bitfield_default },
	 { "DISABLE_EAWRREQ_BUSY", 8, 8, &umr_bitfield_default },
	 { "DISABLE_EARDREQ_BUSY", 9, 9, &umr_bitfield_default },
	 { "SWAP_CTL", 10, 10, &umr_bitfield_default },
};
static struct umr_bitfield mmDAGB0_FIFO_EMPTY[] = {
	 { "EMPTY", 0, 23, &umr_bitfield_default },
};
static struct umr_bitfield mmDAGB0_FIFO_FULL[] = {
	 { "FULL", 0, 22, &umr_bitfield_default },
};
static struct umr_bitfield mmDAGB0_WR_CREDITS_FULL[] = {
	 { "FULL", 0, 18, &umr_bitfield_default },
};
static struct umr_bitfield mmDAGB0_RD_CREDITS_FULL[] = {
	 { "FULL", 0, 17, &umr_bitfield_default },
};
static struct umr_bitfield mmDAGB0_PERFCOUNTER_LO[] = {
	 { "COUNTER_LO", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDAGB0_PERFCOUNTER_HI[] = {
	 { "COUNTER_HI", 0, 15, &umr_bitfield_default },
	 { "COMPARE_VALUE", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDAGB0_PERFCOUNTER0_CFG[] = {
	 { "PERF_SEL", 0, 7, &umr_bitfield_default },
	 { "PERF_SEL_END", 8, 15, &umr_bitfield_default },
	 { "PERF_MODE", 24, 27, &umr_bitfield_default },
	 { "ENABLE", 28, 28, &umr_bitfield_default },
	 { "CLEAR", 29, 29, &umr_bitfield_default },
};
static struct umr_bitfield mmDAGB0_PERFCOUNTER1_CFG[] = {
	 { "PERF_SEL", 0, 7, &umr_bitfield_default },
	 { "PERF_SEL_END", 8, 15, &umr_bitfield_default },
	 { "PERF_MODE", 24, 27, &umr_bitfield_default },
	 { "ENABLE", 28, 28, &umr_bitfield_default },
	 { "CLEAR", 29, 29, &umr_bitfield_default },
};
static struct umr_bitfield mmDAGB0_PERFCOUNTER2_CFG[] = {
	 { "PERF_SEL", 0, 7, &umr_bitfield_default },
	 { "PERF_SEL_END", 8, 15, &umr_bitfield_default },
	 { "PERF_MODE", 24, 27, &umr_bitfield_default },
	 { "ENABLE", 28, 28, &umr_bitfield_default },
	 { "CLEAR", 29, 29, &umr_bitfield_default },
};
static struct umr_bitfield mmDAGB0_PERFCOUNTER_RSLT_CNTL[] = {
	 { "PERF_COUNTER_SELECT", 0, 3, &umr_bitfield_default },
	 { "START_TRIGGER", 8, 15, &umr_bitfield_default },
	 { "STOP_TRIGGER", 16, 23, &umr_bitfield_default },
	 { "ENABLE_ANY", 24, 24, &umr_bitfield_default },
	 { "CLEAR_ALL", 25, 25, &umr_bitfield_default },
	 { "STOP_ALL_ON_SATURATE", 26, 26, &umr_bitfield_default },
};
static struct umr_bitfield mmDAGB0_RESERVE0[] = {
	 { "RESERVE", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDAGB0_RESERVE1[] = {
	 { "RESERVE", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDAGB0_RESERVE2[] = {
	 { "RESERVE", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDAGB0_RESERVE3[] = {
	 { "RESERVE", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDAGB0_RESERVE4[] = {
	 { "RESERVE", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDAGB0_RESERVE5[] = {
	 { "RESERVE", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDAGB0_RESERVE6[] = {
	 { "RESERVE", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDAGB0_RESERVE7[] = {
	 { "RESERVE", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDAGB0_RESERVE8[] = {
	 { "RESERVE", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDAGB0_RESERVE9[] = {
	 { "RESERVE", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDAGB0_RESERVE10[] = {
	 { "RESERVE", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDAGB0_RESERVE11[] = {
	 { "RESERVE", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDAGB0_RESERVE12[] = {
	 { "RESERVE", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDAGB0_RESERVE13[] = {
	 { "RESERVE", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDAGB0_RESERVE14[] = {
	 { "RESERVE", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDAGB0_RESERVE15[] = {
	 { "RESERVE", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDAGB0_RESERVE16[] = {
	 { "RESERVE", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDAGB0_RESERVE17[] = {
	 { "RESERVE", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDAGB1_RDCLI0[] = {
	 { "VIRT_CHAN", 0, 2, &umr_bitfield_default },
	 { "CHECK_TLB_CREDIT", 3, 3, &umr_bitfield_default },
	 { "URG_HIGH", 4, 7, &umr_bitfield_default },
	 { "URG_LOW", 8, 11, &umr_bitfield_default },
	 { "MAX_BW_ENABLE", 12, 12, &umr_bitfield_default },
	 { "MAX_BW", 13, 20, &umr_bitfield_default },
	 { "MIN_BW_ENABLE", 21, 21, &umr_bitfield_default },
	 { "MIN_BW", 22, 24, &umr_bitfield_default },
	 { "OSD_LIMITER_ENABLE", 25, 25, &umr_bitfield_default },
	 { "MAX_OSD", 26, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDAGB1_RDCLI1[] = {
	 { "VIRT_CHAN", 0, 2, &umr_bitfield_default },
	 { "CHECK_TLB_CREDIT", 3, 3, &umr_bitfield_default },
	 { "URG_HIGH", 4, 7, &umr_bitfield_default },
	 { "URG_LOW", 8, 11, &umr_bitfield_default },
	 { "MAX_BW_ENABLE", 12, 12, &umr_bitfield_default },
	 { "MAX_BW", 13, 20, &umr_bitfield_default },
	 { "MIN_BW_ENABLE", 21, 21, &umr_bitfield_default },
	 { "MIN_BW", 22, 24, &umr_bitfield_default },
	 { "OSD_LIMITER_ENABLE", 25, 25, &umr_bitfield_default },
	 { "MAX_OSD", 26, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDAGB1_RDCLI2[] = {
	 { "VIRT_CHAN", 0, 2, &umr_bitfield_default },
	 { "CHECK_TLB_CREDIT", 3, 3, &umr_bitfield_default },
	 { "URG_HIGH", 4, 7, &umr_bitfield_default },
	 { "URG_LOW", 8, 11, &umr_bitfield_default },
	 { "MAX_BW_ENABLE", 12, 12, &umr_bitfield_default },
	 { "MAX_BW", 13, 20, &umr_bitfield_default },
	 { "MIN_BW_ENABLE", 21, 21, &umr_bitfield_default },
	 { "MIN_BW", 22, 24, &umr_bitfield_default },
	 { "OSD_LIMITER_ENABLE", 25, 25, &umr_bitfield_default },
	 { "MAX_OSD", 26, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDAGB1_RDCLI3[] = {
	 { "VIRT_CHAN", 0, 2, &umr_bitfield_default },
	 { "CHECK_TLB_CREDIT", 3, 3, &umr_bitfield_default },
	 { "URG_HIGH", 4, 7, &umr_bitfield_default },
	 { "URG_LOW", 8, 11, &umr_bitfield_default },
	 { "MAX_BW_ENABLE", 12, 12, &umr_bitfield_default },
	 { "MAX_BW", 13, 20, &umr_bitfield_default },
	 { "MIN_BW_ENABLE", 21, 21, &umr_bitfield_default },
	 { "MIN_BW", 22, 24, &umr_bitfield_default },
	 { "OSD_LIMITER_ENABLE", 25, 25, &umr_bitfield_default },
	 { "MAX_OSD", 26, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDAGB1_RDCLI4[] = {
	 { "VIRT_CHAN", 0, 2, &umr_bitfield_default },
	 { "CHECK_TLB_CREDIT", 3, 3, &umr_bitfield_default },
	 { "URG_HIGH", 4, 7, &umr_bitfield_default },
	 { "URG_LOW", 8, 11, &umr_bitfield_default },
	 { "MAX_BW_ENABLE", 12, 12, &umr_bitfield_default },
	 { "MAX_BW", 13, 20, &umr_bitfield_default },
	 { "MIN_BW_ENABLE", 21, 21, &umr_bitfield_default },
	 { "MIN_BW", 22, 24, &umr_bitfield_default },
	 { "OSD_LIMITER_ENABLE", 25, 25, &umr_bitfield_default },
	 { "MAX_OSD", 26, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDAGB1_RDCLI5[] = {
	 { "VIRT_CHAN", 0, 2, &umr_bitfield_default },
	 { "CHECK_TLB_CREDIT", 3, 3, &umr_bitfield_default },
	 { "URG_HIGH", 4, 7, &umr_bitfield_default },
	 { "URG_LOW", 8, 11, &umr_bitfield_default },
	 { "MAX_BW_ENABLE", 12, 12, &umr_bitfield_default },
	 { "MAX_BW", 13, 20, &umr_bitfield_default },
	 { "MIN_BW_ENABLE", 21, 21, &umr_bitfield_default },
	 { "MIN_BW", 22, 24, &umr_bitfield_default },
	 { "OSD_LIMITER_ENABLE", 25, 25, &umr_bitfield_default },
	 { "MAX_OSD", 26, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDAGB1_RDCLI6[] = {
	 { "VIRT_CHAN", 0, 2, &umr_bitfield_default },
	 { "CHECK_TLB_CREDIT", 3, 3, &umr_bitfield_default },
	 { "URG_HIGH", 4, 7, &umr_bitfield_default },
	 { "URG_LOW", 8, 11, &umr_bitfield_default },
	 { "MAX_BW_ENABLE", 12, 12, &umr_bitfield_default },
	 { "MAX_BW", 13, 20, &umr_bitfield_default },
	 { "MIN_BW_ENABLE", 21, 21, &umr_bitfield_default },
	 { "MIN_BW", 22, 24, &umr_bitfield_default },
	 { "OSD_LIMITER_ENABLE", 25, 25, &umr_bitfield_default },
	 { "MAX_OSD", 26, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDAGB1_RDCLI7[] = {
	 { "VIRT_CHAN", 0, 2, &umr_bitfield_default },
	 { "CHECK_TLB_CREDIT", 3, 3, &umr_bitfield_default },
	 { "URG_HIGH", 4, 7, &umr_bitfield_default },
	 { "URG_LOW", 8, 11, &umr_bitfield_default },
	 { "MAX_BW_ENABLE", 12, 12, &umr_bitfield_default },
	 { "MAX_BW", 13, 20, &umr_bitfield_default },
	 { "MIN_BW_ENABLE", 21, 21, &umr_bitfield_default },
	 { "MIN_BW", 22, 24, &umr_bitfield_default },
	 { "OSD_LIMITER_ENABLE", 25, 25, &umr_bitfield_default },
	 { "MAX_OSD", 26, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDAGB1_RDCLI8[] = {
	 { "VIRT_CHAN", 0, 2, &umr_bitfield_default },
	 { "CHECK_TLB_CREDIT", 3, 3, &umr_bitfield_default },
	 { "URG_HIGH", 4, 7, &umr_bitfield_default },
	 { "URG_LOW", 8, 11, &umr_bitfield_default },
	 { "MAX_BW_ENABLE", 12, 12, &umr_bitfield_default },
	 { "MAX_BW", 13, 20, &umr_bitfield_default },
	 { "MIN_BW_ENABLE", 21, 21, &umr_bitfield_default },
	 { "MIN_BW", 22, 24, &umr_bitfield_default },
	 { "OSD_LIMITER_ENABLE", 25, 25, &umr_bitfield_default },
	 { "MAX_OSD", 26, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDAGB1_RDCLI9[] = {
	 { "VIRT_CHAN", 0, 2, &umr_bitfield_default },
	 { "CHECK_TLB_CREDIT", 3, 3, &umr_bitfield_default },
	 { "URG_HIGH", 4, 7, &umr_bitfield_default },
	 { "URG_LOW", 8, 11, &umr_bitfield_default },
	 { "MAX_BW_ENABLE", 12, 12, &umr_bitfield_default },
	 { "MAX_BW", 13, 20, &umr_bitfield_default },
	 { "MIN_BW_ENABLE", 21, 21, &umr_bitfield_default },
	 { "MIN_BW", 22, 24, &umr_bitfield_default },
	 { "OSD_LIMITER_ENABLE", 25, 25, &umr_bitfield_default },
	 { "MAX_OSD", 26, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDAGB1_RDCLI10[] = {
	 { "VIRT_CHAN", 0, 2, &umr_bitfield_default },
	 { "CHECK_TLB_CREDIT", 3, 3, &umr_bitfield_default },
	 { "URG_HIGH", 4, 7, &umr_bitfield_default },
	 { "URG_LOW", 8, 11, &umr_bitfield_default },
	 { "MAX_BW_ENABLE", 12, 12, &umr_bitfield_default },
	 { "MAX_BW", 13, 20, &umr_bitfield_default },
	 { "MIN_BW_ENABLE", 21, 21, &umr_bitfield_default },
	 { "MIN_BW", 22, 24, &umr_bitfield_default },
	 { "OSD_LIMITER_ENABLE", 25, 25, &umr_bitfield_default },
	 { "MAX_OSD", 26, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDAGB1_RDCLI11[] = {
	 { "VIRT_CHAN", 0, 2, &umr_bitfield_default },
	 { "CHECK_TLB_CREDIT", 3, 3, &umr_bitfield_default },
	 { "URG_HIGH", 4, 7, &umr_bitfield_default },
	 { "URG_LOW", 8, 11, &umr_bitfield_default },
	 { "MAX_BW_ENABLE", 12, 12, &umr_bitfield_default },
	 { "MAX_BW", 13, 20, &umr_bitfield_default },
	 { "MIN_BW_ENABLE", 21, 21, &umr_bitfield_default },
	 { "MIN_BW", 22, 24, &umr_bitfield_default },
	 { "OSD_LIMITER_ENABLE", 25, 25, &umr_bitfield_default },
	 { "MAX_OSD", 26, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDAGB1_RDCLI12[] = {
	 { "VIRT_CHAN", 0, 2, &umr_bitfield_default },
	 { "CHECK_TLB_CREDIT", 3, 3, &umr_bitfield_default },
	 { "URG_HIGH", 4, 7, &umr_bitfield_default },
	 { "URG_LOW", 8, 11, &umr_bitfield_default },
	 { "MAX_BW_ENABLE", 12, 12, &umr_bitfield_default },
	 { "MAX_BW", 13, 20, &umr_bitfield_default },
	 { "MIN_BW_ENABLE", 21, 21, &umr_bitfield_default },
	 { "MIN_BW", 22, 24, &umr_bitfield_default },
	 { "OSD_LIMITER_ENABLE", 25, 25, &umr_bitfield_default },
	 { "MAX_OSD", 26, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDAGB1_RDCLI13[] = {
	 { "VIRT_CHAN", 0, 2, &umr_bitfield_default },
	 { "CHECK_TLB_CREDIT", 3, 3, &umr_bitfield_default },
	 { "URG_HIGH", 4, 7, &umr_bitfield_default },
	 { "URG_LOW", 8, 11, &umr_bitfield_default },
	 { "MAX_BW_ENABLE", 12, 12, &umr_bitfield_default },
	 { "MAX_BW", 13, 20, &umr_bitfield_default },
	 { "MIN_BW_ENABLE", 21, 21, &umr_bitfield_default },
	 { "MIN_BW", 22, 24, &umr_bitfield_default },
	 { "OSD_LIMITER_ENABLE", 25, 25, &umr_bitfield_default },
	 { "MAX_OSD", 26, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDAGB1_RDCLI14[] = {
	 { "VIRT_CHAN", 0, 2, &umr_bitfield_default },
	 { "CHECK_TLB_CREDIT", 3, 3, &umr_bitfield_default },
	 { "URG_HIGH", 4, 7, &umr_bitfield_default },
	 { "URG_LOW", 8, 11, &umr_bitfield_default },
	 { "MAX_BW_ENABLE", 12, 12, &umr_bitfield_default },
	 { "MAX_BW", 13, 20, &umr_bitfield_default },
	 { "MIN_BW_ENABLE", 21, 21, &umr_bitfield_default },
	 { "MIN_BW", 22, 24, &umr_bitfield_default },
	 { "OSD_LIMITER_ENABLE", 25, 25, &umr_bitfield_default },
	 { "MAX_OSD", 26, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDAGB1_RDCLI15[] = {
	 { "VIRT_CHAN", 0, 2, &umr_bitfield_default },
	 { "CHECK_TLB_CREDIT", 3, 3, &umr_bitfield_default },
	 { "URG_HIGH", 4, 7, &umr_bitfield_default },
	 { "URG_LOW", 8, 11, &umr_bitfield_default },
	 { "MAX_BW_ENABLE", 12, 12, &umr_bitfield_default },
	 { "MAX_BW", 13, 20, &umr_bitfield_default },
	 { "MIN_BW_ENABLE", 21, 21, &umr_bitfield_default },
	 { "MIN_BW", 22, 24, &umr_bitfield_default },
	 { "OSD_LIMITER_ENABLE", 25, 25, &umr_bitfield_default },
	 { "MAX_OSD", 26, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDAGB1_RD_CNTL[] = {
	 { "SCLK_FREQ", 0, 3, &umr_bitfield_default },
	 { "CLI_MAX_BW_WINDOW", 4, 9, &umr_bitfield_default },
	 { "VC_MAX_BW_WINDOW", 10, 15, &umr_bitfield_default },
	 { "IO_LEVEL_OVERRIDE_ENABLE", 16, 16, &umr_bitfield_default },
	 { "IO_LEVEL", 17, 19, &umr_bitfield_default },
	 { "IO_LEVEL_COMPLY_VC", 20, 22, &umr_bitfield_default },
	 { "SHARE_VC_NUM", 23, 25, &umr_bitfield_default },
};
static struct umr_bitfield mmDAGB1_RD_GMI_CNTL[] = {
	 { "EA_CREDIT", 0, 5, &umr_bitfield_default },
	 { "LEVEL", 6, 8, &umr_bitfield_default },
	 { "MAX_BURST", 9, 12, &umr_bitfield_default },
	 { "LAZY_TIMER", 13, 16, &umr_bitfield_default },
};
static struct umr_bitfield mmDAGB1_RD_ADDR_DAGB[] = {
	 { "DAGB_ENABLE", 0, 2, &umr_bitfield_default },
	 { "ENABLE_JUMP_AHEAD", 3, 5, &umr_bitfield_default },
	 { "DISABLE_SELF_INIT", 6, 6, &umr_bitfield_default },
	 { "WHOAMI", 7, 12, &umr_bitfield_default },
};
static struct umr_bitfield mmDAGB1_RD_OUTPUT_DAGB_MAX_BURST[] = {
	 { "VC0", 0, 3, &umr_bitfield_default },
	 { "VC1", 4, 7, &umr_bitfield_default },
	 { "VC2", 8, 11, &umr_bitfield_default },
	 { "VC3", 12, 15, &umr_bitfield_default },
	 { "VC4", 16, 19, &umr_bitfield_default },
	 { "VC5", 20, 23, &umr_bitfield_default },
	 { "VC6", 24, 27, &umr_bitfield_default },
	 { "VC7", 28, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDAGB1_RD_OUTPUT_DAGB_LAZY_TIMER[] = {
	 { "VC0", 0, 3, &umr_bitfield_default },
	 { "VC1", 4, 7, &umr_bitfield_default },
	 { "VC2", 8, 11, &umr_bitfield_default },
	 { "VC3", 12, 15, &umr_bitfield_default },
	 { "VC4", 16, 19, &umr_bitfield_default },
	 { "VC5", 20, 23, &umr_bitfield_default },
	 { "VC6", 24, 27, &umr_bitfield_default },
	 { "VC7", 28, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDAGB1_RD_CGTT_CLK_CTRL[] = {
	 { "ON_DELAY", 0, 3, &umr_bitfield_default },
	 { "OFF_HYSTERESIS", 4, 11, &umr_bitfield_default },
	 { "SOFT_STALL_OVERRIDE", 22, 22, &umr_bitfield_default },
	 { "LS_OVERRIDE", 27, 27, &umr_bitfield_default },
	 { "LS_OVERRIDE_WRITE", 28, 28, &umr_bitfield_default },
	 { "LS_OVERRIDE_READ", 29, 29, &umr_bitfield_default },
	 { "LS_OVERRIDE_RETURN", 30, 30, &umr_bitfield_default },
	 { "LS_OVERRIDE_REGISTER", 31, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDAGB1_L1TLB_RD_CGTT_CLK_CTRL[] = {
	 { "ON_DELAY", 0, 3, &umr_bitfield_default },
	 { "OFF_HYSTERESIS", 4, 11, &umr_bitfield_default },
	 { "SOFT_STALL_OVERRIDE", 22, 22, &umr_bitfield_default },
	 { "LS_OVERRIDE", 27, 27, &umr_bitfield_default },
	 { "LS_OVERRIDE_WRITE", 28, 28, &umr_bitfield_default },
	 { "LS_OVERRIDE_READ", 29, 29, &umr_bitfield_default },
	 { "LS_OVERRIDE_RETURN", 30, 30, &umr_bitfield_default },
	 { "LS_OVERRIDE_REGISTER", 31, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDAGB1_ATCVM_RD_CGTT_CLK_CTRL[] = {
	 { "ON_DELAY", 0, 3, &umr_bitfield_default },
	 { "OFF_HYSTERESIS", 4, 11, &umr_bitfield_default },
	 { "SOFT_STALL_OVERRIDE", 22, 22, &umr_bitfield_default },
	 { "LS_OVERRIDE", 27, 27, &umr_bitfield_default },
	 { "LS_OVERRIDE_WRITE", 28, 28, &umr_bitfield_default },
	 { "LS_OVERRIDE_READ", 29, 29, &umr_bitfield_default },
	 { "LS_OVERRIDE_RETURN", 30, 30, &umr_bitfield_default },
	 { "LS_OVERRIDE_REGISTER", 31, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDAGB1_RD_ADDR_DAGB_MAX_BURST0[] = {
	 { "CLIENT0", 0, 3, &umr_bitfield_default },
	 { "CLIENT1", 4, 7, &umr_bitfield_default },
	 { "CLIENT2", 8, 11, &umr_bitfield_default },
	 { "CLIENT3", 12, 15, &umr_bitfield_default },
	 { "CLIENT4", 16, 19, &umr_bitfield_default },
	 { "CLIENT5", 20, 23, &umr_bitfield_default },
	 { "CLIENT6", 24, 27, &umr_bitfield_default },
	 { "CLIENT7", 28, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDAGB1_RD_ADDR_DAGB_LAZY_TIMER0[] = {
	 { "CLIENT0", 0, 3, &umr_bitfield_default },
	 { "CLIENT1", 4, 7, &umr_bitfield_default },
	 { "CLIENT2", 8, 11, &umr_bitfield_default },
	 { "CLIENT3", 12, 15, &umr_bitfield_default },
	 { "CLIENT4", 16, 19, &umr_bitfield_default },
	 { "CLIENT5", 20, 23, &umr_bitfield_default },
	 { "CLIENT6", 24, 27, &umr_bitfield_default },
	 { "CLIENT7", 28, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDAGB1_RD_ADDR_DAGB_MAX_BURST1[] = {
	 { "CLIENT8", 0, 3, &umr_bitfield_default },
	 { "CLIENT9", 4, 7, &umr_bitfield_default },
	 { "CLIENT10", 8, 11, &umr_bitfield_default },
	 { "CLIENT11", 12, 15, &umr_bitfield_default },
	 { "CLIENT12", 16, 19, &umr_bitfield_default },
	 { "CLIENT13", 20, 23, &umr_bitfield_default },
	 { "CLIENT14", 24, 27, &umr_bitfield_default },
	 { "CLIENT15", 28, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDAGB1_RD_ADDR_DAGB_LAZY_TIMER1[] = {
	 { "CLIENT8", 0, 3, &umr_bitfield_default },
	 { "CLIENT9", 4, 7, &umr_bitfield_default },
	 { "CLIENT10", 8, 11, &umr_bitfield_default },
	 { "CLIENT11", 12, 15, &umr_bitfield_default },
	 { "CLIENT12", 16, 19, &umr_bitfield_default },
	 { "CLIENT13", 20, 23, &umr_bitfield_default },
	 { "CLIENT14", 24, 27, &umr_bitfield_default },
	 { "CLIENT15", 28, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDAGB1_RD_VC0_CNTL[] = {
	 { "STOR_CREDIT", 0, 4, &umr_bitfield_default },
	 { "EA_CREDIT", 5, 10, &umr_bitfield_default },
	 { "MAX_BW_ENABLE", 11, 11, &umr_bitfield_default },
	 { "MAX_BW", 12, 19, &umr_bitfield_default },
	 { "MIN_BW_ENABLE", 20, 20, &umr_bitfield_default },
	 { "MIN_BW", 21, 23, &umr_bitfield_default },
	 { "OSD_LIMITER_ENABLE", 24, 24, &umr_bitfield_default },
	 { "MAX_OSD", 25, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDAGB1_RD_VC1_CNTL[] = {
	 { "STOR_CREDIT", 0, 4, &umr_bitfield_default },
	 { "EA_CREDIT", 5, 10, &umr_bitfield_default },
	 { "MAX_BW_ENABLE", 11, 11, &umr_bitfield_default },
	 { "MAX_BW", 12, 19, &umr_bitfield_default },
	 { "MIN_BW_ENABLE", 20, 20, &umr_bitfield_default },
	 { "MIN_BW", 21, 23, &umr_bitfield_default },
	 { "OSD_LIMITER_ENABLE", 24, 24, &umr_bitfield_default },
	 { "MAX_OSD", 25, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDAGB1_RD_VC2_CNTL[] = {
	 { "STOR_CREDIT", 0, 4, &umr_bitfield_default },
	 { "EA_CREDIT", 5, 10, &umr_bitfield_default },
	 { "MAX_BW_ENABLE", 11, 11, &umr_bitfield_default },
	 { "MAX_BW", 12, 19, &umr_bitfield_default },
	 { "MIN_BW_ENABLE", 20, 20, &umr_bitfield_default },
	 { "MIN_BW", 21, 23, &umr_bitfield_default },
	 { "OSD_LIMITER_ENABLE", 24, 24, &umr_bitfield_default },
	 { "MAX_OSD", 25, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDAGB1_RD_VC3_CNTL[] = {
	 { "STOR_CREDIT", 0, 4, &umr_bitfield_default },
	 { "EA_CREDIT", 5, 10, &umr_bitfield_default },
	 { "MAX_BW_ENABLE", 11, 11, &umr_bitfield_default },
	 { "MAX_BW", 12, 19, &umr_bitfield_default },
	 { "MIN_BW_ENABLE", 20, 20, &umr_bitfield_default },
	 { "MIN_BW", 21, 23, &umr_bitfield_default },
	 { "OSD_LIMITER_ENABLE", 24, 24, &umr_bitfield_default },
	 { "MAX_OSD", 25, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDAGB1_RD_VC4_CNTL[] = {
	 { "STOR_CREDIT", 0, 4, &umr_bitfield_default },
	 { "EA_CREDIT", 5, 10, &umr_bitfield_default },
	 { "MAX_BW_ENABLE", 11, 11, &umr_bitfield_default },
	 { "MAX_BW", 12, 19, &umr_bitfield_default },
	 { "MIN_BW_ENABLE", 20, 20, &umr_bitfield_default },
	 { "MIN_BW", 21, 23, &umr_bitfield_default },
	 { "OSD_LIMITER_ENABLE", 24, 24, &umr_bitfield_default },
	 { "MAX_OSD", 25, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDAGB1_RD_VC5_CNTL[] = {
	 { "STOR_CREDIT", 0, 4, &umr_bitfield_default },
	 { "EA_CREDIT", 5, 10, &umr_bitfield_default },
	 { "MAX_BW_ENABLE", 11, 11, &umr_bitfield_default },
	 { "MAX_BW", 12, 19, &umr_bitfield_default },
	 { "MIN_BW_ENABLE", 20, 20, &umr_bitfield_default },
	 { "MIN_BW", 21, 23, &umr_bitfield_default },
	 { "OSD_LIMITER_ENABLE", 24, 24, &umr_bitfield_default },
	 { "MAX_OSD", 25, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDAGB1_RD_VC6_CNTL[] = {
	 { "STOR_CREDIT", 0, 4, &umr_bitfield_default },
	 { "EA_CREDIT", 5, 10, &umr_bitfield_default },
	 { "MAX_BW_ENABLE", 11, 11, &umr_bitfield_default },
	 { "MAX_BW", 12, 19, &umr_bitfield_default },
	 { "MIN_BW_ENABLE", 20, 20, &umr_bitfield_default },
	 { "MIN_BW", 21, 23, &umr_bitfield_default },
	 { "OSD_LIMITER_ENABLE", 24, 24, &umr_bitfield_default },
	 { "MAX_OSD", 25, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDAGB1_RD_VC7_CNTL[] = {
	 { "STOR_CREDIT", 0, 4, &umr_bitfield_default },
	 { "EA_CREDIT", 5, 10, &umr_bitfield_default },
	 { "MAX_BW_ENABLE", 11, 11, &umr_bitfield_default },
	 { "MAX_BW", 12, 19, &umr_bitfield_default },
	 { "MIN_BW_ENABLE", 20, 20, &umr_bitfield_default },
	 { "MIN_BW", 21, 23, &umr_bitfield_default },
	 { "OSD_LIMITER_ENABLE", 24, 24, &umr_bitfield_default },
	 { "MAX_OSD", 25, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDAGB1_RD_CNTL_MISC[] = {
	 { "STOR_POOL_CREDIT", 0, 5, &umr_bitfield_default },
	 { "EA_POOL_CREDIT", 6, 12, &umr_bitfield_default },
	 { "IO_EA_CREDIT", 13, 18, &umr_bitfield_default },
	 { "STOR_CC_LEGACY_MODE", 19, 19, &umr_bitfield_default },
	 { "EA_CC_LEGACY_MODE", 20, 20, &umr_bitfield_default },
	 { "UTCL2_CID", 21, 25, &umr_bitfield_default },
};
static struct umr_bitfield mmDAGB1_RD_TLB_CREDIT[] = {
	 { "TLB0", 0, 4, &umr_bitfield_default },
	 { "TLB1", 5, 9, &umr_bitfield_default },
	 { "TLB2", 10, 14, &umr_bitfield_default },
	 { "TLB3", 15, 19, &umr_bitfield_default },
	 { "TLB4", 20, 24, &umr_bitfield_default },
	 { "TLB5", 25, 29, &umr_bitfield_default },
};
static struct umr_bitfield mmDAGB1_RDCLI_ASK_PENDING[] = {
	 { "BUSY", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDAGB1_RDCLI_GO_PENDING[] = {
	 { "BUSY", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDAGB1_RDCLI_GBLSEND_PENDING[] = {
	 { "BUSY", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDAGB1_RDCLI_TLB_PENDING[] = {
	 { "BUSY", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDAGB1_RDCLI_OARB_PENDING[] = {
	 { "BUSY", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDAGB1_RDCLI_OSD_PENDING[] = {
	 { "BUSY", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDAGB1_WRCLI0[] = {
	 { "VIRT_CHAN", 0, 2, &umr_bitfield_default },
	 { "CHECK_TLB_CREDIT", 3, 3, &umr_bitfield_default },
	 { "URG_HIGH", 4, 7, &umr_bitfield_default },
	 { "URG_LOW", 8, 11, &umr_bitfield_default },
	 { "MAX_BW_ENABLE", 12, 12, &umr_bitfield_default },
	 { "MAX_BW", 13, 20, &umr_bitfield_default },
	 { "MIN_BW_ENABLE", 21, 21, &umr_bitfield_default },
	 { "MIN_BW", 22, 24, &umr_bitfield_default },
	 { "OSD_LIMITER_ENABLE", 25, 25, &umr_bitfield_default },
	 { "MAX_OSD", 26, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDAGB1_WRCLI1[] = {
	 { "VIRT_CHAN", 0, 2, &umr_bitfield_default },
	 { "CHECK_TLB_CREDIT", 3, 3, &umr_bitfield_default },
	 { "URG_HIGH", 4, 7, &umr_bitfield_default },
	 { "URG_LOW", 8, 11, &umr_bitfield_default },
	 { "MAX_BW_ENABLE", 12, 12, &umr_bitfield_default },
	 { "MAX_BW", 13, 20, &umr_bitfield_default },
	 { "MIN_BW_ENABLE", 21, 21, &umr_bitfield_default },
	 { "MIN_BW", 22, 24, &umr_bitfield_default },
	 { "OSD_LIMITER_ENABLE", 25, 25, &umr_bitfield_default },
	 { "MAX_OSD", 26, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDAGB1_WRCLI2[] = {
	 { "VIRT_CHAN", 0, 2, &umr_bitfield_default },
	 { "CHECK_TLB_CREDIT", 3, 3, &umr_bitfield_default },
	 { "URG_HIGH", 4, 7, &umr_bitfield_default },
	 { "URG_LOW", 8, 11, &umr_bitfield_default },
	 { "MAX_BW_ENABLE", 12, 12, &umr_bitfield_default },
	 { "MAX_BW", 13, 20, &umr_bitfield_default },
	 { "MIN_BW_ENABLE", 21, 21, &umr_bitfield_default },
	 { "MIN_BW", 22, 24, &umr_bitfield_default },
	 { "OSD_LIMITER_ENABLE", 25, 25, &umr_bitfield_default },
	 { "MAX_OSD", 26, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDAGB1_WRCLI3[] = {
	 { "VIRT_CHAN", 0, 2, &umr_bitfield_default },
	 { "CHECK_TLB_CREDIT", 3, 3, &umr_bitfield_default },
	 { "URG_HIGH", 4, 7, &umr_bitfield_default },
	 { "URG_LOW", 8, 11, &umr_bitfield_default },
	 { "MAX_BW_ENABLE", 12, 12, &umr_bitfield_default },
	 { "MAX_BW", 13, 20, &umr_bitfield_default },
	 { "MIN_BW_ENABLE", 21, 21, &umr_bitfield_default },
	 { "MIN_BW", 22, 24, &umr_bitfield_default },
	 { "OSD_LIMITER_ENABLE", 25, 25, &umr_bitfield_default },
	 { "MAX_OSD", 26, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDAGB1_WRCLI4[] = {
	 { "VIRT_CHAN", 0, 2, &umr_bitfield_default },
	 { "CHECK_TLB_CREDIT", 3, 3, &umr_bitfield_default },
	 { "URG_HIGH", 4, 7, &umr_bitfield_default },
	 { "URG_LOW", 8, 11, &umr_bitfield_default },
	 { "MAX_BW_ENABLE", 12, 12, &umr_bitfield_default },
	 { "MAX_BW", 13, 20, &umr_bitfield_default },
	 { "MIN_BW_ENABLE", 21, 21, &umr_bitfield_default },
	 { "MIN_BW", 22, 24, &umr_bitfield_default },
	 { "OSD_LIMITER_ENABLE", 25, 25, &umr_bitfield_default },
	 { "MAX_OSD", 26, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDAGB1_WRCLI5[] = {
	 { "VIRT_CHAN", 0, 2, &umr_bitfield_default },
	 { "CHECK_TLB_CREDIT", 3, 3, &umr_bitfield_default },
	 { "URG_HIGH", 4, 7, &umr_bitfield_default },
	 { "URG_LOW", 8, 11, &umr_bitfield_default },
	 { "MAX_BW_ENABLE", 12, 12, &umr_bitfield_default },
	 { "MAX_BW", 13, 20, &umr_bitfield_default },
	 { "MIN_BW_ENABLE", 21, 21, &umr_bitfield_default },
	 { "MIN_BW", 22, 24, &umr_bitfield_default },
	 { "OSD_LIMITER_ENABLE", 25, 25, &umr_bitfield_default },
	 { "MAX_OSD", 26, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDAGB1_WRCLI6[] = {
	 { "VIRT_CHAN", 0, 2, &umr_bitfield_default },
	 { "CHECK_TLB_CREDIT", 3, 3, &umr_bitfield_default },
	 { "URG_HIGH", 4, 7, &umr_bitfield_default },
	 { "URG_LOW", 8, 11, &umr_bitfield_default },
	 { "MAX_BW_ENABLE", 12, 12, &umr_bitfield_default },
	 { "MAX_BW", 13, 20, &umr_bitfield_default },
	 { "MIN_BW_ENABLE", 21, 21, &umr_bitfield_default },
	 { "MIN_BW", 22, 24, &umr_bitfield_default },
	 { "OSD_LIMITER_ENABLE", 25, 25, &umr_bitfield_default },
	 { "MAX_OSD", 26, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDAGB1_WRCLI7[] = {
	 { "VIRT_CHAN", 0, 2, &umr_bitfield_default },
	 { "CHECK_TLB_CREDIT", 3, 3, &umr_bitfield_default },
	 { "URG_HIGH", 4, 7, &umr_bitfield_default },
	 { "URG_LOW", 8, 11, &umr_bitfield_default },
	 { "MAX_BW_ENABLE", 12, 12, &umr_bitfield_default },
	 { "MAX_BW", 13, 20, &umr_bitfield_default },
	 { "MIN_BW_ENABLE", 21, 21, &umr_bitfield_default },
	 { "MIN_BW", 22, 24, &umr_bitfield_default },
	 { "OSD_LIMITER_ENABLE", 25, 25, &umr_bitfield_default },
	 { "MAX_OSD", 26, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDAGB1_WRCLI8[] = {
	 { "VIRT_CHAN", 0, 2, &umr_bitfield_default },
	 { "CHECK_TLB_CREDIT", 3, 3, &umr_bitfield_default },
	 { "URG_HIGH", 4, 7, &umr_bitfield_default },
	 { "URG_LOW", 8, 11, &umr_bitfield_default },
	 { "MAX_BW_ENABLE", 12, 12, &umr_bitfield_default },
	 { "MAX_BW", 13, 20, &umr_bitfield_default },
	 { "MIN_BW_ENABLE", 21, 21, &umr_bitfield_default },
	 { "MIN_BW", 22, 24, &umr_bitfield_default },
	 { "OSD_LIMITER_ENABLE", 25, 25, &umr_bitfield_default },
	 { "MAX_OSD", 26, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDAGB1_WRCLI9[] = {
	 { "VIRT_CHAN", 0, 2, &umr_bitfield_default },
	 { "CHECK_TLB_CREDIT", 3, 3, &umr_bitfield_default },
	 { "URG_HIGH", 4, 7, &umr_bitfield_default },
	 { "URG_LOW", 8, 11, &umr_bitfield_default },
	 { "MAX_BW_ENABLE", 12, 12, &umr_bitfield_default },
	 { "MAX_BW", 13, 20, &umr_bitfield_default },
	 { "MIN_BW_ENABLE", 21, 21, &umr_bitfield_default },
	 { "MIN_BW", 22, 24, &umr_bitfield_default },
	 { "OSD_LIMITER_ENABLE", 25, 25, &umr_bitfield_default },
	 { "MAX_OSD", 26, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDAGB1_WRCLI10[] = {
	 { "VIRT_CHAN", 0, 2, &umr_bitfield_default },
	 { "CHECK_TLB_CREDIT", 3, 3, &umr_bitfield_default },
	 { "URG_HIGH", 4, 7, &umr_bitfield_default },
	 { "URG_LOW", 8, 11, &umr_bitfield_default },
	 { "MAX_BW_ENABLE", 12, 12, &umr_bitfield_default },
	 { "MAX_BW", 13, 20, &umr_bitfield_default },
	 { "MIN_BW_ENABLE", 21, 21, &umr_bitfield_default },
	 { "MIN_BW", 22, 24, &umr_bitfield_default },
	 { "OSD_LIMITER_ENABLE", 25, 25, &umr_bitfield_default },
	 { "MAX_OSD", 26, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDAGB1_WRCLI11[] = {
	 { "VIRT_CHAN", 0, 2, &umr_bitfield_default },
	 { "CHECK_TLB_CREDIT", 3, 3, &umr_bitfield_default },
	 { "URG_HIGH", 4, 7, &umr_bitfield_default },
	 { "URG_LOW", 8, 11, &umr_bitfield_default },
	 { "MAX_BW_ENABLE", 12, 12, &umr_bitfield_default },
	 { "MAX_BW", 13, 20, &umr_bitfield_default },
	 { "MIN_BW_ENABLE", 21, 21, &umr_bitfield_default },
	 { "MIN_BW", 22, 24, &umr_bitfield_default },
	 { "OSD_LIMITER_ENABLE", 25, 25, &umr_bitfield_default },
	 { "MAX_OSD", 26, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDAGB1_WRCLI12[] = {
	 { "VIRT_CHAN", 0, 2, &umr_bitfield_default },
	 { "CHECK_TLB_CREDIT", 3, 3, &umr_bitfield_default },
	 { "URG_HIGH", 4, 7, &umr_bitfield_default },
	 { "URG_LOW", 8, 11, &umr_bitfield_default },
	 { "MAX_BW_ENABLE", 12, 12, &umr_bitfield_default },
	 { "MAX_BW", 13, 20, &umr_bitfield_default },
	 { "MIN_BW_ENABLE", 21, 21, &umr_bitfield_default },
	 { "MIN_BW", 22, 24, &umr_bitfield_default },
	 { "OSD_LIMITER_ENABLE", 25, 25, &umr_bitfield_default },
	 { "MAX_OSD", 26, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDAGB1_WRCLI13[] = {
	 { "VIRT_CHAN", 0, 2, &umr_bitfield_default },
	 { "CHECK_TLB_CREDIT", 3, 3, &umr_bitfield_default },
	 { "URG_HIGH", 4, 7, &umr_bitfield_default },
	 { "URG_LOW", 8, 11, &umr_bitfield_default },
	 { "MAX_BW_ENABLE", 12, 12, &umr_bitfield_default },
	 { "MAX_BW", 13, 20, &umr_bitfield_default },
	 { "MIN_BW_ENABLE", 21, 21, &umr_bitfield_default },
	 { "MIN_BW", 22, 24, &umr_bitfield_default },
	 { "OSD_LIMITER_ENABLE", 25, 25, &umr_bitfield_default },
	 { "MAX_OSD", 26, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDAGB1_WRCLI14[] = {
	 { "VIRT_CHAN", 0, 2, &umr_bitfield_default },
	 { "CHECK_TLB_CREDIT", 3, 3, &umr_bitfield_default },
	 { "URG_HIGH", 4, 7, &umr_bitfield_default },
	 { "URG_LOW", 8, 11, &umr_bitfield_default },
	 { "MAX_BW_ENABLE", 12, 12, &umr_bitfield_default },
	 { "MAX_BW", 13, 20, &umr_bitfield_default },
	 { "MIN_BW_ENABLE", 21, 21, &umr_bitfield_default },
	 { "MIN_BW", 22, 24, &umr_bitfield_default },
	 { "OSD_LIMITER_ENABLE", 25, 25, &umr_bitfield_default },
	 { "MAX_OSD", 26, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDAGB1_WRCLI15[] = {
	 { "VIRT_CHAN", 0, 2, &umr_bitfield_default },
	 { "CHECK_TLB_CREDIT", 3, 3, &umr_bitfield_default },
	 { "URG_HIGH", 4, 7, &umr_bitfield_default },
	 { "URG_LOW", 8, 11, &umr_bitfield_default },
	 { "MAX_BW_ENABLE", 12, 12, &umr_bitfield_default },
	 { "MAX_BW", 13, 20, &umr_bitfield_default },
	 { "MIN_BW_ENABLE", 21, 21, &umr_bitfield_default },
	 { "MIN_BW", 22, 24, &umr_bitfield_default },
	 { "OSD_LIMITER_ENABLE", 25, 25, &umr_bitfield_default },
	 { "MAX_OSD", 26, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDAGB1_WR_CNTL[] = {
	 { "SCLK_FREQ", 0, 3, &umr_bitfield_default },
	 { "CLI_MAX_BW_WINDOW", 4, 9, &umr_bitfield_default },
	 { "VC_MAX_BW_WINDOW", 10, 15, &umr_bitfield_default },
	 { "IO_LEVEL_OVERRIDE_ENABLE", 16, 16, &umr_bitfield_default },
	 { "IO_LEVEL", 17, 19, &umr_bitfield_default },
	 { "IO_LEVEL_COMPLY_VC", 20, 22, &umr_bitfield_default },
	 { "SHARE_VC_NUM", 23, 25, &umr_bitfield_default },
};
static struct umr_bitfield mmDAGB1_WR_GMI_CNTL[] = {
	 { "EA_CREDIT", 0, 5, &umr_bitfield_default },
	 { "LEVEL", 6, 8, &umr_bitfield_default },
	 { "MAX_BURST", 9, 12, &umr_bitfield_default },
	 { "LAZY_TIMER", 13, 16, &umr_bitfield_default },
};
static struct umr_bitfield mmDAGB1_WR_ADDR_DAGB[] = {
	 { "DAGB_ENABLE", 0, 2, &umr_bitfield_default },
	 { "ENABLE_JUMP_AHEAD", 3, 5, &umr_bitfield_default },
	 { "DISABLE_SELF_INIT", 6, 6, &umr_bitfield_default },
	 { "WHOAMI", 7, 12, &umr_bitfield_default },
};
static struct umr_bitfield mmDAGB1_WR_OUTPUT_DAGB_MAX_BURST[] = {
	 { "VC0", 0, 3, &umr_bitfield_default },
	 { "VC1", 4, 7, &umr_bitfield_default },
	 { "VC2", 8, 11, &umr_bitfield_default },
	 { "VC3", 12, 15, &umr_bitfield_default },
	 { "VC4", 16, 19, &umr_bitfield_default },
	 { "VC5", 20, 23, &umr_bitfield_default },
	 { "VC6", 24, 27, &umr_bitfield_default },
	 { "VC7", 28, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDAGB1_WR_OUTPUT_DAGB_LAZY_TIMER[] = {
	 { "VC0", 0, 3, &umr_bitfield_default },
	 { "VC1", 4, 7, &umr_bitfield_default },
	 { "VC2", 8, 11, &umr_bitfield_default },
	 { "VC3", 12, 15, &umr_bitfield_default },
	 { "VC4", 16, 19, &umr_bitfield_default },
	 { "VC5", 20, 23, &umr_bitfield_default },
	 { "VC6", 24, 27, &umr_bitfield_default },
	 { "VC7", 28, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDAGB1_WR_CGTT_CLK_CTRL[] = {
	 { "ON_DELAY", 0, 3, &umr_bitfield_default },
	 { "OFF_HYSTERESIS", 4, 11, &umr_bitfield_default },
	 { "SOFT_STALL_OVERRIDE", 22, 22, &umr_bitfield_default },
	 { "LS_OVERRIDE", 27, 27, &umr_bitfield_default },
	 { "LS_OVERRIDE_WRITE", 28, 28, &umr_bitfield_default },
	 { "LS_OVERRIDE_READ", 29, 29, &umr_bitfield_default },
	 { "LS_OVERRIDE_RETURN", 30, 30, &umr_bitfield_default },
	 { "LS_OVERRIDE_REGISTER", 31, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDAGB1_L1TLB_WR_CGTT_CLK_CTRL[] = {
	 { "ON_DELAY", 0, 3, &umr_bitfield_default },
	 { "OFF_HYSTERESIS", 4, 11, &umr_bitfield_default },
	 { "SOFT_STALL_OVERRIDE", 22, 22, &umr_bitfield_default },
	 { "LS_OVERRIDE", 27, 27, &umr_bitfield_default },
	 { "LS_OVERRIDE_WRITE", 28, 28, &umr_bitfield_default },
	 { "LS_OVERRIDE_READ", 29, 29, &umr_bitfield_default },
	 { "LS_OVERRIDE_RETURN", 30, 30, &umr_bitfield_default },
	 { "LS_OVERRIDE_REGISTER", 31, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDAGB1_ATCVM_WR_CGTT_CLK_CTRL[] = {
	 { "ON_DELAY", 0, 3, &umr_bitfield_default },
	 { "OFF_HYSTERESIS", 4, 11, &umr_bitfield_default },
	 { "SOFT_STALL_OVERRIDE", 22, 22, &umr_bitfield_default },
	 { "LS_OVERRIDE", 27, 27, &umr_bitfield_default },
	 { "LS_OVERRIDE_WRITE", 28, 28, &umr_bitfield_default },
	 { "LS_OVERRIDE_READ", 29, 29, &umr_bitfield_default },
	 { "LS_OVERRIDE_RETURN", 30, 30, &umr_bitfield_default },
	 { "LS_OVERRIDE_REGISTER", 31, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDAGB1_WR_ADDR_DAGB_MAX_BURST0[] = {
	 { "CLIENT0", 0, 3, &umr_bitfield_default },
	 { "CLIENT1", 4, 7, &umr_bitfield_default },
	 { "CLIENT2", 8, 11, &umr_bitfield_default },
	 { "CLIENT3", 12, 15, &umr_bitfield_default },
	 { "CLIENT4", 16, 19, &umr_bitfield_default },
	 { "CLIENT5", 20, 23, &umr_bitfield_default },
	 { "CLIENT6", 24, 27, &umr_bitfield_default },
	 { "CLIENT7", 28, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDAGB1_WR_ADDR_DAGB_LAZY_TIMER0[] = {
	 { "CLIENT0", 0, 3, &umr_bitfield_default },
	 { "CLIENT1", 4, 7, &umr_bitfield_default },
	 { "CLIENT2", 8, 11, &umr_bitfield_default },
	 { "CLIENT3", 12, 15, &umr_bitfield_default },
	 { "CLIENT4", 16, 19, &umr_bitfield_default },
	 { "CLIENT5", 20, 23, &umr_bitfield_default },
	 { "CLIENT6", 24, 27, &umr_bitfield_default },
	 { "CLIENT7", 28, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDAGB1_WR_ADDR_DAGB_MAX_BURST1[] = {
	 { "CLIENT8", 0, 3, &umr_bitfield_default },
	 { "CLIENT9", 4, 7, &umr_bitfield_default },
	 { "CLIENT10", 8, 11, &umr_bitfield_default },
	 { "CLIENT11", 12, 15, &umr_bitfield_default },
	 { "CLIENT12", 16, 19, &umr_bitfield_default },
	 { "CLIENT13", 20, 23, &umr_bitfield_default },
	 { "CLIENT14", 24, 27, &umr_bitfield_default },
	 { "CLIENT15", 28, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDAGB1_WR_ADDR_DAGB_LAZY_TIMER1[] = {
	 { "CLIENT8", 0, 3, &umr_bitfield_default },
	 { "CLIENT9", 4, 7, &umr_bitfield_default },
	 { "CLIENT10", 8, 11, &umr_bitfield_default },
	 { "CLIENT11", 12, 15, &umr_bitfield_default },
	 { "CLIENT12", 16, 19, &umr_bitfield_default },
	 { "CLIENT13", 20, 23, &umr_bitfield_default },
	 { "CLIENT14", 24, 27, &umr_bitfield_default },
	 { "CLIENT15", 28, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDAGB1_WR_DATA_DAGB[] = {
	 { "DAGB_ENABLE", 0, 2, &umr_bitfield_default },
	 { "ENABLE_JUMP_AHEAD", 3, 5, &umr_bitfield_default },
	 { "DISABLE_SELF_INIT", 6, 6, &umr_bitfield_default },
	 { "WHOAMI", 7, 12, &umr_bitfield_default },
};
static struct umr_bitfield mmDAGB1_WR_DATA_DAGB_MAX_BURST0[] = {
	 { "CLIENT0", 0, 3, &umr_bitfield_default },
	 { "CLIENT1", 4, 7, &umr_bitfield_default },
	 { "CLIENT2", 8, 11, &umr_bitfield_default },
	 { "CLIENT3", 12, 15, &umr_bitfield_default },
	 { "CLIENT4", 16, 19, &umr_bitfield_default },
	 { "CLIENT5", 20, 23, &umr_bitfield_default },
	 { "CLIENT6", 24, 27, &umr_bitfield_default },
	 { "CLIENT7", 28, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDAGB1_WR_DATA_DAGB_LAZY_TIMER0[] = {
	 { "CLIENT0", 0, 3, &umr_bitfield_default },
	 { "CLIENT1", 4, 7, &umr_bitfield_default },
	 { "CLIENT2", 8, 11, &umr_bitfield_default },
	 { "CLIENT3", 12, 15, &umr_bitfield_default },
	 { "CLIENT4", 16, 19, &umr_bitfield_default },
	 { "CLIENT5", 20, 23, &umr_bitfield_default },
	 { "CLIENT6", 24, 27, &umr_bitfield_default },
	 { "CLIENT7", 28, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDAGB1_WR_DATA_DAGB_MAX_BURST1[] = {
	 { "CLIENT8", 0, 3, &umr_bitfield_default },
	 { "CLIENT9", 4, 7, &umr_bitfield_default },
	 { "CLIENT10", 8, 11, &umr_bitfield_default },
	 { "CLIENT11", 12, 15, &umr_bitfield_default },
	 { "CLIENT12", 16, 19, &umr_bitfield_default },
	 { "CLIENT13", 20, 23, &umr_bitfield_default },
	 { "CLIENT14", 24, 27, &umr_bitfield_default },
	 { "CLIENT15", 28, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDAGB1_WR_DATA_DAGB_LAZY_TIMER1[] = {
	 { "CLIENT8", 0, 3, &umr_bitfield_default },
	 { "CLIENT9", 4, 7, &umr_bitfield_default },
	 { "CLIENT10", 8, 11, &umr_bitfield_default },
	 { "CLIENT11", 12, 15, &umr_bitfield_default },
	 { "CLIENT12", 16, 19, &umr_bitfield_default },
	 { "CLIENT13", 20, 23, &umr_bitfield_default },
	 { "CLIENT14", 24, 27, &umr_bitfield_default },
	 { "CLIENT15", 28, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDAGB1_WR_VC0_CNTL[] = {
	 { "STOR_CREDIT", 0, 4, &umr_bitfield_default },
	 { "EA_CREDIT", 5, 10, &umr_bitfield_default },
	 { "MAX_BW_ENABLE", 11, 11, &umr_bitfield_default },
	 { "MAX_BW", 12, 19, &umr_bitfield_default },
	 { "MIN_BW_ENABLE", 20, 20, &umr_bitfield_default },
	 { "MIN_BW", 21, 23, &umr_bitfield_default },
	 { "OSD_LIMITER_ENABLE", 24, 24, &umr_bitfield_default },
	 { "MAX_OSD", 25, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDAGB1_WR_VC1_CNTL[] = {
	 { "STOR_CREDIT", 0, 4, &umr_bitfield_default },
	 { "EA_CREDIT", 5, 10, &umr_bitfield_default },
	 { "MAX_BW_ENABLE", 11, 11, &umr_bitfield_default },
	 { "MAX_BW", 12, 19, &umr_bitfield_default },
	 { "MIN_BW_ENABLE", 20, 20, &umr_bitfield_default },
	 { "MIN_BW", 21, 23, &umr_bitfield_default },
	 { "OSD_LIMITER_ENABLE", 24, 24, &umr_bitfield_default },
	 { "MAX_OSD", 25, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDAGB1_WR_VC2_CNTL[] = {
	 { "STOR_CREDIT", 0, 4, &umr_bitfield_default },
	 { "EA_CREDIT", 5, 10, &umr_bitfield_default },
	 { "MAX_BW_ENABLE", 11, 11, &umr_bitfield_default },
	 { "MAX_BW", 12, 19, &umr_bitfield_default },
	 { "MIN_BW_ENABLE", 20, 20, &umr_bitfield_default },
	 { "MIN_BW", 21, 23, &umr_bitfield_default },
	 { "OSD_LIMITER_ENABLE", 24, 24, &umr_bitfield_default },
	 { "MAX_OSD", 25, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDAGB1_WR_VC3_CNTL[] = {
	 { "STOR_CREDIT", 0, 4, &umr_bitfield_default },
	 { "EA_CREDIT", 5, 10, &umr_bitfield_default },
	 { "MAX_BW_ENABLE", 11, 11, &umr_bitfield_default },
	 { "MAX_BW", 12, 19, &umr_bitfield_default },
	 { "MIN_BW_ENABLE", 20, 20, &umr_bitfield_default },
	 { "MIN_BW", 21, 23, &umr_bitfield_default },
	 { "OSD_LIMITER_ENABLE", 24, 24, &umr_bitfield_default },
	 { "MAX_OSD", 25, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDAGB1_WR_VC4_CNTL[] = {
	 { "STOR_CREDIT", 0, 4, &umr_bitfield_default },
	 { "EA_CREDIT", 5, 10, &umr_bitfield_default },
	 { "MAX_BW_ENABLE", 11, 11, &umr_bitfield_default },
	 { "MAX_BW", 12, 19, &umr_bitfield_default },
	 { "MIN_BW_ENABLE", 20, 20, &umr_bitfield_default },
	 { "MIN_BW", 21, 23, &umr_bitfield_default },
	 { "OSD_LIMITER_ENABLE", 24, 24, &umr_bitfield_default },
	 { "MAX_OSD", 25, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDAGB1_WR_VC5_CNTL[] = {
	 { "STOR_CREDIT", 0, 4, &umr_bitfield_default },
	 { "EA_CREDIT", 5, 10, &umr_bitfield_default },
	 { "MAX_BW_ENABLE", 11, 11, &umr_bitfield_default },
	 { "MAX_BW", 12, 19, &umr_bitfield_default },
	 { "MIN_BW_ENABLE", 20, 20, &umr_bitfield_default },
	 { "MIN_BW", 21, 23, &umr_bitfield_default },
	 { "OSD_LIMITER_ENABLE", 24, 24, &umr_bitfield_default },
	 { "MAX_OSD", 25, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDAGB1_WR_VC6_CNTL[] = {
	 { "STOR_CREDIT", 0, 4, &umr_bitfield_default },
	 { "EA_CREDIT", 5, 10, &umr_bitfield_default },
	 { "MAX_BW_ENABLE", 11, 11, &umr_bitfield_default },
	 { "MAX_BW", 12, 19, &umr_bitfield_default },
	 { "MIN_BW_ENABLE", 20, 20, &umr_bitfield_default },
	 { "MIN_BW", 21, 23, &umr_bitfield_default },
	 { "OSD_LIMITER_ENABLE", 24, 24, &umr_bitfield_default },
	 { "MAX_OSD", 25, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDAGB1_WR_VC7_CNTL[] = {
	 { "STOR_CREDIT", 0, 4, &umr_bitfield_default },
	 { "EA_CREDIT", 5, 10, &umr_bitfield_default },
	 { "MAX_BW_ENABLE", 11, 11, &umr_bitfield_default },
	 { "MAX_BW", 12, 19, &umr_bitfield_default },
	 { "MIN_BW_ENABLE", 20, 20, &umr_bitfield_default },
	 { "MIN_BW", 21, 23, &umr_bitfield_default },
	 { "OSD_LIMITER_ENABLE", 24, 24, &umr_bitfield_default },
	 { "MAX_OSD", 25, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDAGB1_WR_CNTL_MISC[] = {
	 { "STOR_POOL_CREDIT", 0, 5, &umr_bitfield_default },
	 { "EA_POOL_CREDIT", 6, 12, &umr_bitfield_default },
	 { "IO_EA_CREDIT", 13, 18, &umr_bitfield_default },
	 { "STOR_CC_LEGACY_MODE", 19, 19, &umr_bitfield_default },
	 { "EA_CC_LEGACY_MODE", 20, 20, &umr_bitfield_default },
	 { "UTCL2_CID", 21, 25, &umr_bitfield_default },
};
static struct umr_bitfield mmDAGB1_WR_TLB_CREDIT[] = {
	 { "TLB0", 0, 4, &umr_bitfield_default },
	 { "TLB1", 5, 9, &umr_bitfield_default },
	 { "TLB2", 10, 14, &umr_bitfield_default },
	 { "TLB3", 15, 19, &umr_bitfield_default },
	 { "TLB4", 20, 24, &umr_bitfield_default },
	 { "TLB5", 25, 29, &umr_bitfield_default },
};
static struct umr_bitfield mmDAGB1_WR_DATA_CREDIT[] = {
	 { "DLOCK_VC_CREDITS", 0, 7, &umr_bitfield_default },
	 { "LARGE_BURST_CREDITS", 8, 15, &umr_bitfield_default },
	 { "MIDDLE_BURST_CREDITS", 16, 23, &umr_bitfield_default },
	 { "SMALL_BURST_CREDITS", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDAGB1_WR_MISC_CREDIT[] = {
	 { "ATOMIC_CREDIT", 0, 5, &umr_bitfield_default },
	 { "DLOCK_VC_NUM", 6, 8, &umr_bitfield_default },
	 { "OSD_CREDIT", 9, 15, &umr_bitfield_default },
	 { "OSD_DLOCK_CREDIT", 16, 22, &umr_bitfield_default },
};
static struct umr_bitfield mmDAGB1_WRCLI_ASK_PENDING[] = {
	 { "BUSY", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDAGB1_WRCLI_GO_PENDING[] = {
	 { "BUSY", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDAGB1_WRCLI_GBLSEND_PENDING[] = {
	 { "BUSY", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDAGB1_WRCLI_TLB_PENDING[] = {
	 { "BUSY", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDAGB1_WRCLI_OARB_PENDING[] = {
	 { "BUSY", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDAGB1_WRCLI_OSD_PENDING[] = {
	 { "BUSY", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDAGB1_WRCLI_DBUS_ASK_PENDING[] = {
	 { "BUSY", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDAGB1_WRCLI_DBUS_GO_PENDING[] = {
	 { "BUSY", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDAGB1_DAGB_DLY[] = {
	 { "DLY", 0, 7, &umr_bitfield_default },
	 { "CLI", 8, 15, &umr_bitfield_default },
	 { "POS", 16, 19, &umr_bitfield_default },
};
static struct umr_bitfield mmDAGB1_CNTL_MISC[] = {
	 { "EA_VC0_REMAP", 0, 2, &umr_bitfield_default },
	 { "EA_VC1_REMAP", 3, 5, &umr_bitfield_default },
	 { "EA_VC2_REMAP", 6, 8, &umr_bitfield_default },
	 { "EA_VC3_REMAP", 9, 11, &umr_bitfield_default },
	 { "EA_VC4_REMAP", 12, 14, &umr_bitfield_default },
	 { "EA_VC5_REMAP", 15, 17, &umr_bitfield_default },
	 { "EA_VC6_REMAP", 18, 20, &umr_bitfield_default },
	 { "EA_VC7_REMAP", 21, 23, &umr_bitfield_default },
	 { "BW_INIT_CYCLE", 24, 29, &umr_bitfield_default },
	 { "BW_RW_GAP_CYCLE", 30, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDAGB1_CNTL_MISC2[] = {
	 { "URG_BOOST_ENABLE", 0, 0, &umr_bitfield_default },
	 { "URG_HALT_ENABLE", 1, 1, &umr_bitfield_default },
	 { "DISABLE_WRREQ_CG", 2, 2, &umr_bitfield_default },
	 { "DISABLE_WRRET_CG", 3, 3, &umr_bitfield_default },
	 { "DISABLE_RDREQ_CG", 4, 4, &umr_bitfield_default },
	 { "DISABLE_RDRET_CG", 5, 5, &umr_bitfield_default },
	 { "DISABLE_TLBWR_CG", 6, 6, &umr_bitfield_default },
	 { "DISABLE_TLBRD_CG", 7, 7, &umr_bitfield_default },
	 { "DISABLE_EAWRREQ_BUSY", 8, 8, &umr_bitfield_default },
	 { "DISABLE_EARDREQ_BUSY", 9, 9, &umr_bitfield_default },
	 { "SWAP_CTL", 10, 10, &umr_bitfield_default },
};
static struct umr_bitfield mmDAGB1_FIFO_EMPTY[] = {
	 { "EMPTY", 0, 23, &umr_bitfield_default },
};
static struct umr_bitfield mmDAGB1_FIFO_FULL[] = {
	 { "FULL", 0, 22, &umr_bitfield_default },
};
static struct umr_bitfield mmDAGB1_WR_CREDITS_FULL[] = {
	 { "FULL", 0, 18, &umr_bitfield_default },
};
static struct umr_bitfield mmDAGB1_RD_CREDITS_FULL[] = {
	 { "FULL", 0, 17, &umr_bitfield_default },
};
static struct umr_bitfield mmDAGB1_PERFCOUNTER_LO[] = {
	 { "COUNTER_LO", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDAGB1_PERFCOUNTER_HI[] = {
	 { "COUNTER_HI", 0, 15, &umr_bitfield_default },
	 { "COMPARE_VALUE", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDAGB1_PERFCOUNTER0_CFG[] = {
	 { "PERF_SEL", 0, 7, &umr_bitfield_default },
	 { "PERF_SEL_END", 8, 15, &umr_bitfield_default },
	 { "PERF_MODE", 24, 27, &umr_bitfield_default },
	 { "ENABLE", 28, 28, &umr_bitfield_default },
	 { "CLEAR", 29, 29, &umr_bitfield_default },
};
static struct umr_bitfield mmDAGB1_PERFCOUNTER1_CFG[] = {
	 { "PERF_SEL", 0, 7, &umr_bitfield_default },
	 { "PERF_SEL_END", 8, 15, &umr_bitfield_default },
	 { "PERF_MODE", 24, 27, &umr_bitfield_default },
	 { "ENABLE", 28, 28, &umr_bitfield_default },
	 { "CLEAR", 29, 29, &umr_bitfield_default },
};
static struct umr_bitfield mmDAGB1_PERFCOUNTER2_CFG[] = {
	 { "PERF_SEL", 0, 7, &umr_bitfield_default },
	 { "PERF_SEL_END", 8, 15, &umr_bitfield_default },
	 { "PERF_MODE", 24, 27, &umr_bitfield_default },
	 { "ENABLE", 28, 28, &umr_bitfield_default },
	 { "CLEAR", 29, 29, &umr_bitfield_default },
};
static struct umr_bitfield mmDAGB1_PERFCOUNTER_RSLT_CNTL[] = {
	 { "PERF_COUNTER_SELECT", 0, 3, &umr_bitfield_default },
	 { "START_TRIGGER", 8, 15, &umr_bitfield_default },
	 { "STOP_TRIGGER", 16, 23, &umr_bitfield_default },
	 { "ENABLE_ANY", 24, 24, &umr_bitfield_default },
	 { "CLEAR_ALL", 25, 25, &umr_bitfield_default },
	 { "STOP_ALL_ON_SATURATE", 26, 26, &umr_bitfield_default },
};
static struct umr_bitfield mmDAGB1_RESERVE0[] = {
	 { "RESERVE", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDAGB1_RESERVE1[] = {
	 { "RESERVE", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDAGB1_RESERVE2[] = {
	 { "RESERVE", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDAGB1_RESERVE3[] = {
	 { "RESERVE", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDAGB1_RESERVE4[] = {
	 { "RESERVE", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDAGB1_RESERVE5[] = {
	 { "RESERVE", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDAGB1_RESERVE6[] = {
	 { "RESERVE", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDAGB1_RESERVE7[] = {
	 { "RESERVE", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDAGB1_RESERVE8[] = {
	 { "RESERVE", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDAGB1_RESERVE9[] = {
	 { "RESERVE", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDAGB1_RESERVE10[] = {
	 { "RESERVE", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDAGB1_RESERVE11[] = {
	 { "RESERVE", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDAGB1_RESERVE12[] = {
	 { "RESERVE", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDAGB1_RESERVE13[] = {
	 { "RESERVE", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDAGB1_RESERVE14[] = {
	 { "RESERVE", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDAGB1_RESERVE15[] = {
	 { "RESERVE", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDAGB1_RESERVE16[] = {
	 { "RESERVE", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDAGB1_RESERVE17[] = {
	 { "RESERVE", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMMEA0_DRAM_RD_CLI2GRP_MAP0[] = {
	 { "CID0_GROUP", 0, 1, &umr_bitfield_default },
	 { "CID1_GROUP", 2, 3, &umr_bitfield_default },
	 { "CID2_GROUP", 4, 5, &umr_bitfield_default },
	 { "CID3_GROUP", 6, 7, &umr_bitfield_default },
	 { "CID4_GROUP", 8, 9, &umr_bitfield_default },
	 { "CID5_GROUP", 10, 11, &umr_bitfield_default },
	 { "CID6_GROUP", 12, 13, &umr_bitfield_default },
	 { "CID7_GROUP", 14, 15, &umr_bitfield_default },
	 { "CID8_GROUP", 16, 17, &umr_bitfield_default },
	 { "CID9_GROUP", 18, 19, &umr_bitfield_default },
	 { "CID10_GROUP", 20, 21, &umr_bitfield_default },
	 { "CID11_GROUP", 22, 23, &umr_bitfield_default },
	 { "CID12_GROUP", 24, 25, &umr_bitfield_default },
	 { "CID13_GROUP", 26, 27, &umr_bitfield_default },
	 { "CID14_GROUP", 28, 29, &umr_bitfield_default },
	 { "CID15_GROUP", 30, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMMEA0_DRAM_RD_CLI2GRP_MAP1[] = {
	 { "CID16_GROUP", 0, 1, &umr_bitfield_default },
	 { "CID17_GROUP", 2, 3, &umr_bitfield_default },
	 { "CID18_GROUP", 4, 5, &umr_bitfield_default },
	 { "CID19_GROUP", 6, 7, &umr_bitfield_default },
	 { "CID20_GROUP", 8, 9, &umr_bitfield_default },
	 { "CID21_GROUP", 10, 11, &umr_bitfield_default },
	 { "CID22_GROUP", 12, 13, &umr_bitfield_default },
	 { "CID23_GROUP", 14, 15, &umr_bitfield_default },
	 { "CID24_GROUP", 16, 17, &umr_bitfield_default },
	 { "CID25_GROUP", 18, 19, &umr_bitfield_default },
	 { "CID26_GROUP", 20, 21, &umr_bitfield_default },
	 { "CID27_GROUP", 22, 23, &umr_bitfield_default },
	 { "CID28_GROUP", 24, 25, &umr_bitfield_default },
	 { "CID29_GROUP", 26, 27, &umr_bitfield_default },
	 { "CID30_GROUP", 28, 29, &umr_bitfield_default },
	 { "CID31_GROUP", 30, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMMEA0_DRAM_WR_CLI2GRP_MAP0[] = {
	 { "CID0_GROUP", 0, 1, &umr_bitfield_default },
	 { "CID1_GROUP", 2, 3, &umr_bitfield_default },
	 { "CID2_GROUP", 4, 5, &umr_bitfield_default },
	 { "CID3_GROUP", 6, 7, &umr_bitfield_default },
	 { "CID4_GROUP", 8, 9, &umr_bitfield_default },
	 { "CID5_GROUP", 10, 11, &umr_bitfield_default },
	 { "CID6_GROUP", 12, 13, &umr_bitfield_default },
	 { "CID7_GROUP", 14, 15, &umr_bitfield_default },
	 { "CID8_GROUP", 16, 17, &umr_bitfield_default },
	 { "CID9_GROUP", 18, 19, &umr_bitfield_default },
	 { "CID10_GROUP", 20, 21, &umr_bitfield_default },
	 { "CID11_GROUP", 22, 23, &umr_bitfield_default },
	 { "CID12_GROUP", 24, 25, &umr_bitfield_default },
	 { "CID13_GROUP", 26, 27, &umr_bitfield_default },
	 { "CID14_GROUP", 28, 29, &umr_bitfield_default },
	 { "CID15_GROUP", 30, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMMEA0_DRAM_WR_CLI2GRP_MAP1[] = {
	 { "CID16_GROUP", 0, 1, &umr_bitfield_default },
	 { "CID17_GROUP", 2, 3, &umr_bitfield_default },
	 { "CID18_GROUP", 4, 5, &umr_bitfield_default },
	 { "CID19_GROUP", 6, 7, &umr_bitfield_default },
	 { "CID20_GROUP", 8, 9, &umr_bitfield_default },
	 { "CID21_GROUP", 10, 11, &umr_bitfield_default },
	 { "CID22_GROUP", 12, 13, &umr_bitfield_default },
	 { "CID23_GROUP", 14, 15, &umr_bitfield_default },
	 { "CID24_GROUP", 16, 17, &umr_bitfield_default },
	 { "CID25_GROUP", 18, 19, &umr_bitfield_default },
	 { "CID26_GROUP", 20, 21, &umr_bitfield_default },
	 { "CID27_GROUP", 22, 23, &umr_bitfield_default },
	 { "CID28_GROUP", 24, 25, &umr_bitfield_default },
	 { "CID29_GROUP", 26, 27, &umr_bitfield_default },
	 { "CID30_GROUP", 28, 29, &umr_bitfield_default },
	 { "CID31_GROUP", 30, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMMEA0_DRAM_RD_GRP2VC_MAP[] = {
	 { "GROUP0_VC", 0, 2, &umr_bitfield_default },
	 { "GROUP1_VC", 3, 5, &umr_bitfield_default },
	 { "GROUP2_VC", 6, 8, &umr_bitfield_default },
	 { "GROUP3_VC", 9, 11, &umr_bitfield_default },
};
static struct umr_bitfield mmMMEA0_DRAM_WR_GRP2VC_MAP[] = {
	 { "GROUP0_VC", 0, 2, &umr_bitfield_default },
	 { "GROUP1_VC", 3, 5, &umr_bitfield_default },
	 { "GROUP2_VC", 6, 8, &umr_bitfield_default },
	 { "GROUP3_VC", 9, 11, &umr_bitfield_default },
};
static struct umr_bitfield mmMMEA0_DRAM_RD_LAZY[] = {
	 { "GROUP0_DELAY", 0, 2, &umr_bitfield_default },
	 { "GROUP1_DELAY", 3, 5, &umr_bitfield_default },
	 { "GROUP2_DELAY", 6, 8, &umr_bitfield_default },
	 { "GROUP3_DELAY", 9, 11, &umr_bitfield_default },
};
static struct umr_bitfield mmMMEA0_DRAM_WR_LAZY[] = {
	 { "GROUP0_DELAY", 0, 2, &umr_bitfield_default },
	 { "GROUP1_DELAY", 3, 5, &umr_bitfield_default },
	 { "GROUP2_DELAY", 6, 8, &umr_bitfield_default },
	 { "GROUP3_DELAY", 9, 11, &umr_bitfield_default },
};
static struct umr_bitfield mmMMEA0_DRAM_RD_CAM_CNTL[] = {
	 { "DEPTH_GROUP0", 0, 3, &umr_bitfield_default },
	 { "DEPTH_GROUP1", 4, 7, &umr_bitfield_default },
	 { "DEPTH_GROUP2", 8, 11, &umr_bitfield_default },
	 { "DEPTH_GROUP3", 12, 15, &umr_bitfield_default },
	 { "REORDER_LIMIT_GROUP0", 16, 18, &umr_bitfield_default },
	 { "REORDER_LIMIT_GROUP1", 19, 21, &umr_bitfield_default },
	 { "REORDER_LIMIT_GROUP2", 22, 24, &umr_bitfield_default },
	 { "REORDER_LIMIT_GROUP3", 25, 27, &umr_bitfield_default },
};
static struct umr_bitfield mmMMEA0_DRAM_WR_CAM_CNTL[] = {
	 { "DEPTH_GROUP0", 0, 3, &umr_bitfield_default },
	 { "DEPTH_GROUP1", 4, 7, &umr_bitfield_default },
	 { "DEPTH_GROUP2", 8, 11, &umr_bitfield_default },
	 { "DEPTH_GROUP3", 12, 15, &umr_bitfield_default },
	 { "REORDER_LIMIT_GROUP0", 16, 18, &umr_bitfield_default },
	 { "REORDER_LIMIT_GROUP1", 19, 21, &umr_bitfield_default },
	 { "REORDER_LIMIT_GROUP2", 22, 24, &umr_bitfield_default },
	 { "REORDER_LIMIT_GROUP3", 25, 27, &umr_bitfield_default },
};
static struct umr_bitfield mmMMEA0_DRAM_PAGE_BURST[] = {
	 { "RD_LIMIT_LO", 0, 7, &umr_bitfield_default },
	 { "RD_LIMIT_HI", 8, 15, &umr_bitfield_default },
	 { "WR_LIMIT_LO", 16, 23, &umr_bitfield_default },
	 { "WR_LIMIT_HI", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMMEA0_DRAM_RD_PRI_AGE[] = {
	 { "GROUP0_AGING_RATE", 0, 2, &umr_bitfield_default },
	 { "GROUP1_AGING_RATE", 3, 5, &umr_bitfield_default },
	 { "GROUP2_AGING_RATE", 6, 8, &umr_bitfield_default },
	 { "GROUP3_AGING_RATE", 9, 11, &umr_bitfield_default },
	 { "GROUP0_AGE_COEFFICIENT", 12, 14, &umr_bitfield_default },
	 { "GROUP1_AGE_COEFFICIENT", 15, 17, &umr_bitfield_default },
	 { "GROUP2_AGE_COEFFICIENT", 18, 20, &umr_bitfield_default },
	 { "GROUP3_AGE_COEFFICIENT", 21, 23, &umr_bitfield_default },
};
static struct umr_bitfield mmMMEA0_DRAM_WR_PRI_AGE[] = {
	 { "GROUP0_AGING_RATE", 0, 2, &umr_bitfield_default },
	 { "GROUP1_AGING_RATE", 3, 5, &umr_bitfield_default },
	 { "GROUP2_AGING_RATE", 6, 8, &umr_bitfield_default },
	 { "GROUP3_AGING_RATE", 9, 11, &umr_bitfield_default },
	 { "GROUP0_AGE_COEFFICIENT", 12, 14, &umr_bitfield_default },
	 { "GROUP1_AGE_COEFFICIENT", 15, 17, &umr_bitfield_default },
	 { "GROUP2_AGE_COEFFICIENT", 18, 20, &umr_bitfield_default },
	 { "GROUP3_AGE_COEFFICIENT", 21, 23, &umr_bitfield_default },
};
static struct umr_bitfield mmMMEA0_DRAM_RD_PRI_QUEUING[] = {
	 { "GROUP0_QUEUING_COEFFICIENT", 0, 2, &umr_bitfield_default },
	 { "GROUP1_QUEUING_COEFFICIENT", 3, 5, &umr_bitfield_default },
	 { "GROUP2_QUEUING_COEFFICIENT", 6, 8, &umr_bitfield_default },
	 { "GROUP3_QUEUING_COEFFICIENT", 9, 11, &umr_bitfield_default },
};
static struct umr_bitfield mmMMEA0_DRAM_WR_PRI_QUEUING[] = {
	 { "GROUP0_QUEUING_COEFFICIENT", 0, 2, &umr_bitfield_default },
	 { "GROUP1_QUEUING_COEFFICIENT", 3, 5, &umr_bitfield_default },
	 { "GROUP2_QUEUING_COEFFICIENT", 6, 8, &umr_bitfield_default },
	 { "GROUP3_QUEUING_COEFFICIENT", 9, 11, &umr_bitfield_default },
};
static struct umr_bitfield mmMMEA0_DRAM_RD_PRI_FIXED[] = {
	 { "GROUP0_FIXED_COEFFICIENT", 0, 2, &umr_bitfield_default },
	 { "GROUP1_FIXED_COEFFICIENT", 3, 5, &umr_bitfield_default },
	 { "GROUP2_FIXED_COEFFICIENT", 6, 8, &umr_bitfield_default },
	 { "GROUP3_FIXED_COEFFICIENT", 9, 11, &umr_bitfield_default },
};
static struct umr_bitfield mmMMEA0_DRAM_WR_PRI_FIXED[] = {
	 { "GROUP0_FIXED_COEFFICIENT", 0, 2, &umr_bitfield_default },
	 { "GROUP1_FIXED_COEFFICIENT", 3, 5, &umr_bitfield_default },
	 { "GROUP2_FIXED_COEFFICIENT", 6, 8, &umr_bitfield_default },
	 { "GROUP3_FIXED_COEFFICIENT", 9, 11, &umr_bitfield_default },
};
static struct umr_bitfield mmMMEA0_DRAM_RD_PRI_URGENCY[] = {
	 { "GROUP0_URGENCY_COEFFICIENT", 0, 2, &umr_bitfield_default },
	 { "GROUP1_URGENCY_COEFFICIENT", 3, 5, &umr_bitfield_default },
	 { "GROUP2_URGENCY_COEFFICIENT", 6, 8, &umr_bitfield_default },
	 { "GROUP3_URGENCY_COEFFICIENT", 9, 11, &umr_bitfield_default },
	 { "GROUP0_URGENCY_MODE", 12, 12, &umr_bitfield_default },
	 { "GROUP1_URGENCY_MODE", 13, 13, &umr_bitfield_default },
	 { "GROUP2_URGENCY_MODE", 14, 14, &umr_bitfield_default },
	 { "GROUP3_URGENCY_MODE", 15, 15, &umr_bitfield_default },
};
static struct umr_bitfield mmMMEA0_DRAM_WR_PRI_URGENCY[] = {
	 { "GROUP0_URGENCY_COEFFICIENT", 0, 2, &umr_bitfield_default },
	 { "GROUP1_URGENCY_COEFFICIENT", 3, 5, &umr_bitfield_default },
	 { "GROUP2_URGENCY_COEFFICIENT", 6, 8, &umr_bitfield_default },
	 { "GROUP3_URGENCY_COEFFICIENT", 9, 11, &umr_bitfield_default },
	 { "GROUP0_URGENCY_MODE", 12, 12, &umr_bitfield_default },
	 { "GROUP1_URGENCY_MODE", 13, 13, &umr_bitfield_default },
	 { "GROUP2_URGENCY_MODE", 14, 14, &umr_bitfield_default },
	 { "GROUP3_URGENCY_MODE", 15, 15, &umr_bitfield_default },
};
static struct umr_bitfield mmMMEA0_DRAM_RD_PRI_QUANT_PRI1[] = {
	 { "GROUP0_THRESHOLD", 0, 7, &umr_bitfield_default },
	 { "GROUP1_THRESHOLD", 8, 15, &umr_bitfield_default },
	 { "GROUP2_THRESHOLD", 16, 23, &umr_bitfield_default },
	 { "GROUP3_THRESHOLD", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMMEA0_DRAM_RD_PRI_QUANT_PRI2[] = {
	 { "GROUP0_THRESHOLD", 0, 7, &umr_bitfield_default },
	 { "GROUP1_THRESHOLD", 8, 15, &umr_bitfield_default },
	 { "GROUP2_THRESHOLD", 16, 23, &umr_bitfield_default },
	 { "GROUP3_THRESHOLD", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMMEA0_DRAM_RD_PRI_QUANT_PRI3[] = {
	 { "GROUP0_THRESHOLD", 0, 7, &umr_bitfield_default },
	 { "GROUP1_THRESHOLD", 8, 15, &umr_bitfield_default },
	 { "GROUP2_THRESHOLD", 16, 23, &umr_bitfield_default },
	 { "GROUP3_THRESHOLD", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMMEA0_DRAM_WR_PRI_QUANT_PRI1[] = {
	 { "GROUP0_THRESHOLD", 0, 7, &umr_bitfield_default },
	 { "GROUP1_THRESHOLD", 8, 15, &umr_bitfield_default },
	 { "GROUP2_THRESHOLD", 16, 23, &umr_bitfield_default },
	 { "GROUP3_THRESHOLD", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMMEA0_DRAM_WR_PRI_QUANT_PRI2[] = {
	 { "GROUP0_THRESHOLD", 0, 7, &umr_bitfield_default },
	 { "GROUP1_THRESHOLD", 8, 15, &umr_bitfield_default },
	 { "GROUP2_THRESHOLD", 16, 23, &umr_bitfield_default },
	 { "GROUP3_THRESHOLD", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMMEA0_DRAM_WR_PRI_QUANT_PRI3[] = {
	 { "GROUP0_THRESHOLD", 0, 7, &umr_bitfield_default },
	 { "GROUP1_THRESHOLD", 8, 15, &umr_bitfield_default },
	 { "GROUP2_THRESHOLD", 16, 23, &umr_bitfield_default },
	 { "GROUP3_THRESHOLD", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMMEA0_ADDRNORM_BASE_ADDR0[] = {
	 { "ADDR_RNG_VAL", 0, 0, &umr_bitfield_default },
	 { "LGCY_MMIO_HOLE_EN", 1, 1, &umr_bitfield_default },
	 { "INTLV_NUM_CHAN", 4, 7, &umr_bitfield_default },
	 { "INTLV_ADDR_SEL", 8, 10, &umr_bitfield_default },
	 { "BASE_ADDR", 12, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMMEA0_ADDRNORM_LIMIT_ADDR0[] = {
	 { "DST_FABRIC_ID", 0, 3, &umr_bitfield_default },
	 { "INTLV_NUM_SOCKETS", 8, 8, &umr_bitfield_default },
	 { "INTLV_NUM_DIES", 10, 11, &umr_bitfield_default },
	 { "LIMIT_ADDR", 12, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMMEA0_ADDRNORM_BASE_ADDR1[] = {
	 { "ADDR_RNG_VAL", 0, 0, &umr_bitfield_default },
	 { "LGCY_MMIO_HOLE_EN", 1, 1, &umr_bitfield_default },
	 { "INTLV_NUM_CHAN", 4, 7, &umr_bitfield_default },
	 { "INTLV_ADDR_SEL", 8, 10, &umr_bitfield_default },
	 { "BASE_ADDR", 12, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMMEA0_ADDRNORM_LIMIT_ADDR1[] = {
	 { "DST_FABRIC_ID", 0, 3, &umr_bitfield_default },
	 { "INTLV_NUM_SOCKETS", 8, 8, &umr_bitfield_default },
	 { "INTLV_NUM_DIES", 10, 11, &umr_bitfield_default },
	 { "LIMIT_ADDR", 12, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMMEA0_ADDRNORM_OFFSET_ADDR1[] = {
	 { "HI_ADDR_OFFSET_EN", 0, 0, &umr_bitfield_default },
	 { "HI_ADDR_OFFSET", 20, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMMEA0_ADDRNORM_HOLE_CNTL[] = {
	 { "DRAM_HOLE_VALID", 0, 0, &umr_bitfield_default },
	 { "DRAM_HOLE_OFFSET", 7, 15, &umr_bitfield_default },
};
static struct umr_bitfield mmMMEA0_ADDRDEC_BANK_CFG[] = {
	 { "BANK_MASK_DRAM", 0, 4, &umr_bitfield_default },
	 { "BANK_MASK_GMI", 5, 9, &umr_bitfield_default },
	 { "BANKGROUP_SEL_DRAM", 10, 12, &umr_bitfield_default },
	 { "BANKGROUP_SEL_GMI", 13, 15, &umr_bitfield_default },
	 { "BANKGROUP_INTERLEAVE_DRAM", 16, 16, &umr_bitfield_default },
	 { "BANKGROUP_INTERLEAVE_GMI", 17, 17, &umr_bitfield_default },
};
static struct umr_bitfield mmMMEA0_ADDRDEC_MISC_CFG[] = {
	 { "VCM_EN0", 0, 0, &umr_bitfield_default },
	 { "VCM_EN1", 1, 1, &umr_bitfield_default },
	 { "VCM_EN2", 2, 2, &umr_bitfield_default },
	 { "VCM_EN3", 3, 3, &umr_bitfield_default },
	 { "VCM_EN4", 4, 4, &umr_bitfield_default },
	 { "PCH_MASK_DRAM", 8, 8, &umr_bitfield_default },
	 { "PCH_MASK_GMI", 9, 9, &umr_bitfield_default },
	 { "CH_MASK_DRAM", 12, 15, &umr_bitfield_default },
	 { "CH_MASK_GMI", 16, 19, &umr_bitfield_default },
	 { "CS_MASK_DRAM", 20, 21, &umr_bitfield_default },
	 { "CS_MASK_GMI", 22, 23, &umr_bitfield_default },
	 { "RM_MASK_DRAM", 24, 26, &umr_bitfield_default },
	 { "RM_MASK_GMI", 27, 29, &umr_bitfield_default },
};
static struct umr_bitfield mmMMEA0_ADDRDECDRAM_ADDR_HASH_BANK0[] = {
	 { "XOR_ENABLE", 0, 0, &umr_bitfield_default },
	 { "COL_XOR", 1, 13, &umr_bitfield_default },
	 { "ROW_XOR", 14, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMMEA0_ADDRDECDRAM_ADDR_HASH_BANK1[] = {
	 { "XOR_ENABLE", 0, 0, &umr_bitfield_default },
	 { "COL_XOR", 1, 13, &umr_bitfield_default },
	 { "ROW_XOR", 14, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMMEA0_ADDRDECDRAM_ADDR_HASH_BANK2[] = {
	 { "XOR_ENABLE", 0, 0, &umr_bitfield_default },
	 { "COL_XOR", 1, 13, &umr_bitfield_default },
	 { "ROW_XOR", 14, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMMEA0_ADDRDECDRAM_ADDR_HASH_BANK3[] = {
	 { "XOR_ENABLE", 0, 0, &umr_bitfield_default },
	 { "COL_XOR", 1, 13, &umr_bitfield_default },
	 { "ROW_XOR", 14, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMMEA0_ADDRDECDRAM_ADDR_HASH_BANK4[] = {
	 { "XOR_ENABLE", 0, 0, &umr_bitfield_default },
	 { "COL_XOR", 1, 13, &umr_bitfield_default },
	 { "ROW_XOR", 14, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMMEA0_ADDRDECDRAM_ADDR_HASH_PC[] = {
	 { "XOR_ENABLE", 0, 0, &umr_bitfield_default },
	 { "COL_XOR", 1, 13, &umr_bitfield_default },
	 { "ROW_XOR", 14, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMMEA0_ADDRDECDRAM_ADDR_HASH_PC2[] = {
	 { "BANK_XOR", 0, 4, &umr_bitfield_default },
};
static struct umr_bitfield mmMMEA0_ADDRDECDRAM_ADDR_HASH_CS0[] = {
	 { "XOR_ENABLE", 0, 0, &umr_bitfield_default },
	 { "NA_XOR", 1, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMMEA0_ADDRDECDRAM_ADDR_HASH_CS1[] = {
	 { "XOR_ENABLE", 0, 0, &umr_bitfield_default },
	 { "NA_XOR", 1, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMMEA0_ADDRDECDRAM_HARVEST_ENABLE[] = {
	 { "FORCE_B3_EN", 0, 0, &umr_bitfield_default },
	 { "FORCE_B3_VAL", 1, 1, &umr_bitfield_default },
	 { "FORCE_B4_EN", 2, 2, &umr_bitfield_default },
	 { "FORCE_B4_VAL", 3, 3, &umr_bitfield_default },
};
static struct umr_bitfield mmMMEA0_ADDRDEC0_BASE_ADDR_CS0[] = {
	 { "CS_ENABLE", 0, 0, &umr_bitfield_default },
	 { "BASE_ADDR", 1, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMMEA0_ADDRDEC0_BASE_ADDR_CS1[] = {
	 { "CS_ENABLE", 0, 0, &umr_bitfield_default },
	 { "BASE_ADDR", 1, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMMEA0_ADDRDEC0_BASE_ADDR_CS2[] = {
	 { "CS_ENABLE", 0, 0, &umr_bitfield_default },
	 { "BASE_ADDR", 1, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMMEA0_ADDRDEC0_BASE_ADDR_CS3[] = {
	 { "CS_ENABLE", 0, 0, &umr_bitfield_default },
	 { "BASE_ADDR", 1, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMMEA0_ADDRDEC0_BASE_ADDR_SECCS0[] = {
	 { "CS_ENABLE", 0, 0, &umr_bitfield_default },
	 { "BASE_ADDR", 1, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMMEA0_ADDRDEC0_BASE_ADDR_SECCS1[] = {
	 { "CS_ENABLE", 0, 0, &umr_bitfield_default },
	 { "BASE_ADDR", 1, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMMEA0_ADDRDEC0_BASE_ADDR_SECCS2[] = {
	 { "CS_ENABLE", 0, 0, &umr_bitfield_default },
	 { "BASE_ADDR", 1, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMMEA0_ADDRDEC0_BASE_ADDR_SECCS3[] = {
	 { "CS_ENABLE", 0, 0, &umr_bitfield_default },
	 { "BASE_ADDR", 1, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMMEA0_ADDRDEC0_ADDR_MASK_CS01[] = {
	 { "ADDR_MASK", 1, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMMEA0_ADDRDEC0_ADDR_MASK_CS23[] = {
	 { "ADDR_MASK", 1, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMMEA0_ADDRDEC0_ADDR_MASK_SECCS01[] = {
	 { "ADDR_MASK", 1, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMMEA0_ADDRDEC0_ADDR_MASK_SECCS23[] = {
	 { "ADDR_MASK", 1, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMMEA0_ADDRDEC0_ADDR_CFG_CS01[] = {
	 { "NUM_BANK_GROUPS", 2, 3, &umr_bitfield_default },
	 { "NUM_RM", 4, 5, &umr_bitfield_default },
	 { "NUM_ROW_LO", 8, 11, &umr_bitfield_default },
	 { "NUM_ROW_HI", 12, 15, &umr_bitfield_default },
	 { "NUM_COL", 16, 19, &umr_bitfield_default },
	 { "NUM_BANKS", 20, 21, &umr_bitfield_default },
};
static struct umr_bitfield mmMMEA0_ADDRDEC0_ADDR_CFG_CS23[] = {
	 { "NUM_BANK_GROUPS", 2, 3, &umr_bitfield_default },
	 { "NUM_RM", 4, 5, &umr_bitfield_default },
	 { "NUM_ROW_LO", 8, 11, &umr_bitfield_default },
	 { "NUM_ROW_HI", 12, 15, &umr_bitfield_default },
	 { "NUM_COL", 16, 19, &umr_bitfield_default },
	 { "NUM_BANKS", 20, 21, &umr_bitfield_default },
};
static struct umr_bitfield mmMMEA0_ADDRDEC0_ADDR_SEL_CS01[] = {
	 { "BANK0", 0, 3, &umr_bitfield_default },
	 { "BANK1", 4, 7, &umr_bitfield_default },
	 { "BANK2", 8, 11, &umr_bitfield_default },
	 { "BANK3", 12, 15, &umr_bitfield_default },
	 { "BANK4", 16, 19, &umr_bitfield_default },
	 { "ROW_LO", 24, 27, &umr_bitfield_default },
	 { "ROW_HI", 28, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMMEA0_ADDRDEC0_ADDR_SEL_CS23[] = {
	 { "BANK0", 0, 3, &umr_bitfield_default },
	 { "BANK1", 4, 7, &umr_bitfield_default },
	 { "BANK2", 8, 11, &umr_bitfield_default },
	 { "BANK3", 12, 15, &umr_bitfield_default },
	 { "BANK4", 16, 19, &umr_bitfield_default },
	 { "ROW_LO", 24, 27, &umr_bitfield_default },
	 { "ROW_HI", 28, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMMEA0_ADDRDEC0_COL_SEL_LO_CS01[] = {
	 { "COL0", 0, 3, &umr_bitfield_default },
	 { "COL1", 4, 7, &umr_bitfield_default },
	 { "COL2", 8, 11, &umr_bitfield_default },
	 { "COL3", 12, 15, &umr_bitfield_default },
	 { "COL4", 16, 19, &umr_bitfield_default },
	 { "COL5", 20, 23, &umr_bitfield_default },
	 { "COL6", 24, 27, &umr_bitfield_default },
	 { "COL7", 28, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMMEA0_ADDRDEC0_COL_SEL_LO_CS23[] = {
	 { "COL0", 0, 3, &umr_bitfield_default },
	 { "COL1", 4, 7, &umr_bitfield_default },
	 { "COL2", 8, 11, &umr_bitfield_default },
	 { "COL3", 12, 15, &umr_bitfield_default },
	 { "COL4", 16, 19, &umr_bitfield_default },
	 { "COL5", 20, 23, &umr_bitfield_default },
	 { "COL6", 24, 27, &umr_bitfield_default },
	 { "COL7", 28, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMMEA0_ADDRDEC0_COL_SEL_HI_CS01[] = {
	 { "COL8", 0, 3, &umr_bitfield_default },
	 { "COL9", 4, 7, &umr_bitfield_default },
	 { "COL10", 8, 11, &umr_bitfield_default },
	 { "COL11", 12, 15, &umr_bitfield_default },
	 { "COL12", 16, 19, &umr_bitfield_default },
	 { "COL13", 20, 23, &umr_bitfield_default },
	 { "COL14", 24, 27, &umr_bitfield_default },
	 { "COL15", 28, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMMEA0_ADDRDEC0_COL_SEL_HI_CS23[] = {
	 { "COL8", 0, 3, &umr_bitfield_default },
	 { "COL9", 4, 7, &umr_bitfield_default },
	 { "COL10", 8, 11, &umr_bitfield_default },
	 { "COL11", 12, 15, &umr_bitfield_default },
	 { "COL12", 16, 19, &umr_bitfield_default },
	 { "COL13", 20, 23, &umr_bitfield_default },
	 { "COL14", 24, 27, &umr_bitfield_default },
	 { "COL15", 28, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMMEA0_ADDRDEC0_RM_SEL_CS01[] = {
	 { "RM0", 0, 3, &umr_bitfield_default },
	 { "RM1", 4, 7, &umr_bitfield_default },
	 { "RM2", 8, 11, &umr_bitfield_default },
	 { "CHAN_BIT", 12, 15, &umr_bitfield_default },
	 { "INVERT_ROW_MSBS_EVEN", 16, 17, &umr_bitfield_default },
	 { "INVERT_ROW_MSBS_ODD", 18, 19, &umr_bitfield_default },
};
static struct umr_bitfield mmMMEA0_ADDRDEC0_RM_SEL_CS23[] = {
	 { "RM0", 0, 3, &umr_bitfield_default },
	 { "RM1", 4, 7, &umr_bitfield_default },
	 { "RM2", 8, 11, &umr_bitfield_default },
	 { "CHAN_BIT", 12, 15, &umr_bitfield_default },
	 { "INVERT_ROW_MSBS_EVEN", 16, 17, &umr_bitfield_default },
	 { "INVERT_ROW_MSBS_ODD", 18, 19, &umr_bitfield_default },
};
static struct umr_bitfield mmMMEA0_ADDRDEC0_RM_SEL_SECCS01[] = {
	 { "RM0", 0, 3, &umr_bitfield_default },
	 { "RM1", 4, 7, &umr_bitfield_default },
	 { "RM2", 8, 11, &umr_bitfield_default },
	 { "CHAN_BIT", 12, 15, &umr_bitfield_default },
	 { "INVERT_ROW_MSBS_EVEN", 16, 17, &umr_bitfield_default },
	 { "INVERT_ROW_MSBS_ODD", 18, 19, &umr_bitfield_default },
};
static struct umr_bitfield mmMMEA0_ADDRDEC0_RM_SEL_SECCS23[] = {
	 { "RM0", 0, 3, &umr_bitfield_default },
	 { "RM1", 4, 7, &umr_bitfield_default },
	 { "RM2", 8, 11, &umr_bitfield_default },
	 { "CHAN_BIT", 12, 15, &umr_bitfield_default },
	 { "INVERT_ROW_MSBS_EVEN", 16, 17, &umr_bitfield_default },
	 { "INVERT_ROW_MSBS_ODD", 18, 19, &umr_bitfield_default },
};
static struct umr_bitfield mmMMEA0_ADDRDEC1_BASE_ADDR_CS0[] = {
	 { "CS_ENABLE", 0, 0, &umr_bitfield_default },
	 { "BASE_ADDR", 1, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMMEA0_ADDRDEC1_BASE_ADDR_CS1[] = {
	 { "CS_ENABLE", 0, 0, &umr_bitfield_default },
	 { "BASE_ADDR", 1, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMMEA0_ADDRDEC1_BASE_ADDR_CS2[] = {
	 { "CS_ENABLE", 0, 0, &umr_bitfield_default },
	 { "BASE_ADDR", 1, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMMEA0_ADDRDEC1_BASE_ADDR_CS3[] = {
	 { "CS_ENABLE", 0, 0, &umr_bitfield_default },
	 { "BASE_ADDR", 1, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMMEA0_ADDRDEC1_BASE_ADDR_SECCS0[] = {
	 { "CS_ENABLE", 0, 0, &umr_bitfield_default },
	 { "BASE_ADDR", 1, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMMEA0_ADDRDEC1_BASE_ADDR_SECCS1[] = {
	 { "CS_ENABLE", 0, 0, &umr_bitfield_default },
	 { "BASE_ADDR", 1, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMMEA0_ADDRDEC1_BASE_ADDR_SECCS2[] = {
	 { "CS_ENABLE", 0, 0, &umr_bitfield_default },
	 { "BASE_ADDR", 1, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMMEA0_ADDRDEC1_BASE_ADDR_SECCS3[] = {
	 { "CS_ENABLE", 0, 0, &umr_bitfield_default },
	 { "BASE_ADDR", 1, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMMEA0_ADDRDEC1_ADDR_MASK_CS01[] = {
	 { "ADDR_MASK", 1, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMMEA0_ADDRDEC1_ADDR_MASK_CS23[] = {
	 { "ADDR_MASK", 1, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMMEA0_ADDRDEC1_ADDR_MASK_SECCS01[] = {
	 { "ADDR_MASK", 1, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMMEA0_ADDRDEC1_ADDR_MASK_SECCS23[] = {
	 { "ADDR_MASK", 1, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMMEA0_ADDRDEC1_ADDR_CFG_CS01[] = {
	 { "NUM_BANK_GROUPS", 2, 3, &umr_bitfield_default },
	 { "NUM_RM", 4, 5, &umr_bitfield_default },
	 { "NUM_ROW_LO", 8, 11, &umr_bitfield_default },
	 { "NUM_ROW_HI", 12, 15, &umr_bitfield_default },
	 { "NUM_COL", 16, 19, &umr_bitfield_default },
	 { "NUM_BANKS", 20, 21, &umr_bitfield_default },
};
static struct umr_bitfield mmMMEA0_ADDRDEC1_ADDR_CFG_CS23[] = {
	 { "NUM_BANK_GROUPS", 2, 3, &umr_bitfield_default },
	 { "NUM_RM", 4, 5, &umr_bitfield_default },
	 { "NUM_ROW_LO", 8, 11, &umr_bitfield_default },
	 { "NUM_ROW_HI", 12, 15, &umr_bitfield_default },
	 { "NUM_COL", 16, 19, &umr_bitfield_default },
	 { "NUM_BANKS", 20, 21, &umr_bitfield_default },
};
static struct umr_bitfield mmMMEA0_ADDRDEC1_ADDR_SEL_CS01[] = {
	 { "BANK0", 0, 3, &umr_bitfield_default },
	 { "BANK1", 4, 7, &umr_bitfield_default },
	 { "BANK2", 8, 11, &umr_bitfield_default },
	 { "BANK3", 12, 15, &umr_bitfield_default },
	 { "BANK4", 16, 19, &umr_bitfield_default },
	 { "ROW_LO", 24, 27, &umr_bitfield_default },
	 { "ROW_HI", 28, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMMEA0_ADDRDEC1_ADDR_SEL_CS23[] = {
	 { "BANK0", 0, 3, &umr_bitfield_default },
	 { "BANK1", 4, 7, &umr_bitfield_default },
	 { "BANK2", 8, 11, &umr_bitfield_default },
	 { "BANK3", 12, 15, &umr_bitfield_default },
	 { "BANK4", 16, 19, &umr_bitfield_default },
	 { "ROW_LO", 24, 27, &umr_bitfield_default },
	 { "ROW_HI", 28, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMMEA0_ADDRDEC1_COL_SEL_LO_CS01[] = {
	 { "COL0", 0, 3, &umr_bitfield_default },
	 { "COL1", 4, 7, &umr_bitfield_default },
	 { "COL2", 8, 11, &umr_bitfield_default },
	 { "COL3", 12, 15, &umr_bitfield_default },
	 { "COL4", 16, 19, &umr_bitfield_default },
	 { "COL5", 20, 23, &umr_bitfield_default },
	 { "COL6", 24, 27, &umr_bitfield_default },
	 { "COL7", 28, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMMEA0_ADDRDEC1_COL_SEL_LO_CS23[] = {
	 { "COL0", 0, 3, &umr_bitfield_default },
	 { "COL1", 4, 7, &umr_bitfield_default },
	 { "COL2", 8, 11, &umr_bitfield_default },
	 { "COL3", 12, 15, &umr_bitfield_default },
	 { "COL4", 16, 19, &umr_bitfield_default },
	 { "COL5", 20, 23, &umr_bitfield_default },
	 { "COL6", 24, 27, &umr_bitfield_default },
	 { "COL7", 28, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMMEA0_ADDRDEC1_COL_SEL_HI_CS01[] = {
	 { "COL8", 0, 3, &umr_bitfield_default },
	 { "COL9", 4, 7, &umr_bitfield_default },
	 { "COL10", 8, 11, &umr_bitfield_default },
	 { "COL11", 12, 15, &umr_bitfield_default },
	 { "COL12", 16, 19, &umr_bitfield_default },
	 { "COL13", 20, 23, &umr_bitfield_default },
	 { "COL14", 24, 27, &umr_bitfield_default },
	 { "COL15", 28, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMMEA0_ADDRDEC1_COL_SEL_HI_CS23[] = {
	 { "COL8", 0, 3, &umr_bitfield_default },
	 { "COL9", 4, 7, &umr_bitfield_default },
	 { "COL10", 8, 11, &umr_bitfield_default },
	 { "COL11", 12, 15, &umr_bitfield_default },
	 { "COL12", 16, 19, &umr_bitfield_default },
	 { "COL13", 20, 23, &umr_bitfield_default },
	 { "COL14", 24, 27, &umr_bitfield_default },
	 { "COL15", 28, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMMEA0_ADDRDEC1_RM_SEL_CS01[] = {
	 { "RM0", 0, 3, &umr_bitfield_default },
	 { "RM1", 4, 7, &umr_bitfield_default },
	 { "RM2", 8, 11, &umr_bitfield_default },
	 { "CHAN_BIT", 12, 15, &umr_bitfield_default },
	 { "INVERT_ROW_MSBS_EVEN", 16, 17, &umr_bitfield_default },
	 { "INVERT_ROW_MSBS_ODD", 18, 19, &umr_bitfield_default },
};
static struct umr_bitfield mmMMEA0_ADDRDEC1_RM_SEL_CS23[] = {
	 { "RM0", 0, 3, &umr_bitfield_default },
	 { "RM1", 4, 7, &umr_bitfield_default },
	 { "RM2", 8, 11, &umr_bitfield_default },
	 { "CHAN_BIT", 12, 15, &umr_bitfield_default },
	 { "INVERT_ROW_MSBS_EVEN", 16, 17, &umr_bitfield_default },
	 { "INVERT_ROW_MSBS_ODD", 18, 19, &umr_bitfield_default },
};
static struct umr_bitfield mmMMEA0_ADDRDEC1_RM_SEL_SECCS01[] = {
	 { "RM0", 0, 3, &umr_bitfield_default },
	 { "RM1", 4, 7, &umr_bitfield_default },
	 { "RM2", 8, 11, &umr_bitfield_default },
	 { "CHAN_BIT", 12, 15, &umr_bitfield_default },
	 { "INVERT_ROW_MSBS_EVEN", 16, 17, &umr_bitfield_default },
	 { "INVERT_ROW_MSBS_ODD", 18, 19, &umr_bitfield_default },
};
static struct umr_bitfield mmMMEA0_ADDRDEC1_RM_SEL_SECCS23[] = {
	 { "RM0", 0, 3, &umr_bitfield_default },
	 { "RM1", 4, 7, &umr_bitfield_default },
	 { "RM2", 8, 11, &umr_bitfield_default },
	 { "CHAN_BIT", 12, 15, &umr_bitfield_default },
	 { "INVERT_ROW_MSBS_EVEN", 16, 17, &umr_bitfield_default },
	 { "INVERT_ROW_MSBS_ODD", 18, 19, &umr_bitfield_default },
};
static struct umr_bitfield mmMMEA0_IO_RD_CLI2GRP_MAP0[] = {
	 { "CID0_GROUP", 0, 1, &umr_bitfield_default },
	 { "CID1_GROUP", 2, 3, &umr_bitfield_default },
	 { "CID2_GROUP", 4, 5, &umr_bitfield_default },
	 { "CID3_GROUP", 6, 7, &umr_bitfield_default },
	 { "CID4_GROUP", 8, 9, &umr_bitfield_default },
	 { "CID5_GROUP", 10, 11, &umr_bitfield_default },
	 { "CID6_GROUP", 12, 13, &umr_bitfield_default },
	 { "CID7_GROUP", 14, 15, &umr_bitfield_default },
	 { "CID8_GROUP", 16, 17, &umr_bitfield_default },
	 { "CID9_GROUP", 18, 19, &umr_bitfield_default },
	 { "CID10_GROUP", 20, 21, &umr_bitfield_default },
	 { "CID11_GROUP", 22, 23, &umr_bitfield_default },
	 { "CID12_GROUP", 24, 25, &umr_bitfield_default },
	 { "CID13_GROUP", 26, 27, &umr_bitfield_default },
	 { "CID14_GROUP", 28, 29, &umr_bitfield_default },
	 { "CID15_GROUP", 30, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMMEA0_IO_RD_CLI2GRP_MAP1[] = {
	 { "CID16_GROUP", 0, 1, &umr_bitfield_default },
	 { "CID17_GROUP", 2, 3, &umr_bitfield_default },
	 { "CID18_GROUP", 4, 5, &umr_bitfield_default },
	 { "CID19_GROUP", 6, 7, &umr_bitfield_default },
	 { "CID20_GROUP", 8, 9, &umr_bitfield_default },
	 { "CID21_GROUP", 10, 11, &umr_bitfield_default },
	 { "CID22_GROUP", 12, 13, &umr_bitfield_default },
	 { "CID23_GROUP", 14, 15, &umr_bitfield_default },
	 { "CID24_GROUP", 16, 17, &umr_bitfield_default },
	 { "CID25_GROUP", 18, 19, &umr_bitfield_default },
	 { "CID26_GROUP", 20, 21, &umr_bitfield_default },
	 { "CID27_GROUP", 22, 23, &umr_bitfield_default },
	 { "CID28_GROUP", 24, 25, &umr_bitfield_default },
	 { "CID29_GROUP", 26, 27, &umr_bitfield_default },
	 { "CID30_GROUP", 28, 29, &umr_bitfield_default },
	 { "CID31_GROUP", 30, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMMEA0_IO_WR_CLI2GRP_MAP0[] = {
	 { "CID0_GROUP", 0, 1, &umr_bitfield_default },
	 { "CID1_GROUP", 2, 3, &umr_bitfield_default },
	 { "CID2_GROUP", 4, 5, &umr_bitfield_default },
	 { "CID3_GROUP", 6, 7, &umr_bitfield_default },
	 { "CID4_GROUP", 8, 9, &umr_bitfield_default },
	 { "CID5_GROUP", 10, 11, &umr_bitfield_default },
	 { "CID6_GROUP", 12, 13, &umr_bitfield_default },
	 { "CID7_GROUP", 14, 15, &umr_bitfield_default },
	 { "CID8_GROUP", 16, 17, &umr_bitfield_default },
	 { "CID9_GROUP", 18, 19, &umr_bitfield_default },
	 { "CID10_GROUP", 20, 21, &umr_bitfield_default },
	 { "CID11_GROUP", 22, 23, &umr_bitfield_default },
	 { "CID12_GROUP", 24, 25, &umr_bitfield_default },
	 { "CID13_GROUP", 26, 27, &umr_bitfield_default },
	 { "CID14_GROUP", 28, 29, &umr_bitfield_default },
	 { "CID15_GROUP", 30, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMMEA0_IO_WR_CLI2GRP_MAP1[] = {
	 { "CID16_GROUP", 0, 1, &umr_bitfield_default },
	 { "CID17_GROUP", 2, 3, &umr_bitfield_default },
	 { "CID18_GROUP", 4, 5, &umr_bitfield_default },
	 { "CID19_GROUP", 6, 7, &umr_bitfield_default },
	 { "CID20_GROUP", 8, 9, &umr_bitfield_default },
	 { "CID21_GROUP", 10, 11, &umr_bitfield_default },
	 { "CID22_GROUP", 12, 13, &umr_bitfield_default },
	 { "CID23_GROUP", 14, 15, &umr_bitfield_default },
	 { "CID24_GROUP", 16, 17, &umr_bitfield_default },
	 { "CID25_GROUP", 18, 19, &umr_bitfield_default },
	 { "CID26_GROUP", 20, 21, &umr_bitfield_default },
	 { "CID27_GROUP", 22, 23, &umr_bitfield_default },
	 { "CID28_GROUP", 24, 25, &umr_bitfield_default },
	 { "CID29_GROUP", 26, 27, &umr_bitfield_default },
	 { "CID30_GROUP", 28, 29, &umr_bitfield_default },
	 { "CID31_GROUP", 30, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMMEA0_IO_RD_COMBINE_FLUSH[] = {
	 { "GROUP0_TIMER", 0, 3, &umr_bitfield_default },
	 { "GROUP1_TIMER", 4, 7, &umr_bitfield_default },
	 { "GROUP2_TIMER", 8, 11, &umr_bitfield_default },
	 { "GROUP3_TIMER", 12, 15, &umr_bitfield_default },
};
static struct umr_bitfield mmMMEA0_IO_WR_COMBINE_FLUSH[] = {
	 { "GROUP0_TIMER", 0, 3, &umr_bitfield_default },
	 { "GROUP1_TIMER", 4, 7, &umr_bitfield_default },
	 { "GROUP2_TIMER", 8, 11, &umr_bitfield_default },
	 { "GROUP3_TIMER", 12, 15, &umr_bitfield_default },
};
static struct umr_bitfield mmMMEA0_IO_GROUP_BURST[] = {
	 { "RD_LIMIT_LO", 0, 7, &umr_bitfield_default },
	 { "RD_LIMIT_HI", 8, 15, &umr_bitfield_default },
	 { "WR_LIMIT_LO", 16, 23, &umr_bitfield_default },
	 { "WR_LIMIT_HI", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMMEA0_IO_RD_PRI_AGE[] = {
	 { "GROUP0_AGING_RATE", 0, 2, &umr_bitfield_default },
	 { "GROUP1_AGING_RATE", 3, 5, &umr_bitfield_default },
	 { "GROUP2_AGING_RATE", 6, 8, &umr_bitfield_default },
	 { "GROUP3_AGING_RATE", 9, 11, &umr_bitfield_default },
	 { "GROUP0_AGE_COEFFICIENT", 12, 14, &umr_bitfield_default },
	 { "GROUP1_AGE_COEFFICIENT", 15, 17, &umr_bitfield_default },
	 { "GROUP2_AGE_COEFFICIENT", 18, 20, &umr_bitfield_default },
	 { "GROUP3_AGE_COEFFICIENT", 21, 23, &umr_bitfield_default },
};
static struct umr_bitfield mmMMEA0_IO_WR_PRI_AGE[] = {
	 { "GROUP0_AGING_RATE", 0, 2, &umr_bitfield_default },
	 { "GROUP1_AGING_RATE", 3, 5, &umr_bitfield_default },
	 { "GROUP2_AGING_RATE", 6, 8, &umr_bitfield_default },
	 { "GROUP3_AGING_RATE", 9, 11, &umr_bitfield_default },
	 { "GROUP0_AGE_COEFFICIENT", 12, 14, &umr_bitfield_default },
	 { "GROUP1_AGE_COEFFICIENT", 15, 17, &umr_bitfield_default },
	 { "GROUP2_AGE_COEFFICIENT", 18, 20, &umr_bitfield_default },
	 { "GROUP3_AGE_COEFFICIENT", 21, 23, &umr_bitfield_default },
};
static struct umr_bitfield mmMMEA0_IO_RD_PRI_QUEUING[] = {
	 { "GROUP0_QUEUING_COEFFICIENT", 0, 2, &umr_bitfield_default },
	 { "GROUP1_QUEUING_COEFFICIENT", 3, 5, &umr_bitfield_default },
	 { "GROUP2_QUEUING_COEFFICIENT", 6, 8, &umr_bitfield_default },
	 { "GROUP3_QUEUING_COEFFICIENT", 9, 11, &umr_bitfield_default },
};
static struct umr_bitfield mmMMEA0_IO_WR_PRI_QUEUING[] = {
	 { "GROUP0_QUEUING_COEFFICIENT", 0, 2, &umr_bitfield_default },
	 { "GROUP1_QUEUING_COEFFICIENT", 3, 5, &umr_bitfield_default },
	 { "GROUP2_QUEUING_COEFFICIENT", 6, 8, &umr_bitfield_default },
	 { "GROUP3_QUEUING_COEFFICIENT", 9, 11, &umr_bitfield_default },
};
static struct umr_bitfield mmMMEA0_IO_RD_PRI_FIXED[] = {
	 { "GROUP0_FIXED_COEFFICIENT", 0, 2, &umr_bitfield_default },
	 { "GROUP1_FIXED_COEFFICIENT", 3, 5, &umr_bitfield_default },
	 { "GROUP2_FIXED_COEFFICIENT", 6, 8, &umr_bitfield_default },
	 { "GROUP3_FIXED_COEFFICIENT", 9, 11, &umr_bitfield_default },
};
static struct umr_bitfield mmMMEA0_IO_WR_PRI_FIXED[] = {
	 { "GROUP0_FIXED_COEFFICIENT", 0, 2, &umr_bitfield_default },
	 { "GROUP1_FIXED_COEFFICIENT", 3, 5, &umr_bitfield_default },
	 { "GROUP2_FIXED_COEFFICIENT", 6, 8, &umr_bitfield_default },
	 { "GROUP3_FIXED_COEFFICIENT", 9, 11, &umr_bitfield_default },
};
static struct umr_bitfield mmMMEA0_IO_RD_PRI_URGENCY[] = {
	 { "GROUP0_URGENCY_COEFFICIENT", 0, 2, &umr_bitfield_default },
	 { "GROUP1_URGENCY_COEFFICIENT", 3, 5, &umr_bitfield_default },
	 { "GROUP2_URGENCY_COEFFICIENT", 6, 8, &umr_bitfield_default },
	 { "GROUP3_URGENCY_COEFFICIENT", 9, 11, &umr_bitfield_default },
	 { "GROUP0_URGENCY_MODE", 12, 12, &umr_bitfield_default },
	 { "GROUP1_URGENCY_MODE", 13, 13, &umr_bitfield_default },
	 { "GROUP2_URGENCY_MODE", 14, 14, &umr_bitfield_default },
	 { "GROUP3_URGENCY_MODE", 15, 15, &umr_bitfield_default },
};
static struct umr_bitfield mmMMEA0_IO_WR_PRI_URGENCY[] = {
	 { "GROUP0_URGENCY_COEFFICIENT", 0, 2, &umr_bitfield_default },
	 { "GROUP1_URGENCY_COEFFICIENT", 3, 5, &umr_bitfield_default },
	 { "GROUP2_URGENCY_COEFFICIENT", 6, 8, &umr_bitfield_default },
	 { "GROUP3_URGENCY_COEFFICIENT", 9, 11, &umr_bitfield_default },
	 { "GROUP0_URGENCY_MODE", 12, 12, &umr_bitfield_default },
	 { "GROUP1_URGENCY_MODE", 13, 13, &umr_bitfield_default },
	 { "GROUP2_URGENCY_MODE", 14, 14, &umr_bitfield_default },
	 { "GROUP3_URGENCY_MODE", 15, 15, &umr_bitfield_default },
};
static struct umr_bitfield mmMMEA0_IO_RD_PRI_URGENCY_MASK[] = {
	 { "CID0_MASK", 0, 0, &umr_bitfield_default },
	 { "CID1_MASK", 1, 1, &umr_bitfield_default },
	 { "CID2_MASK", 2, 2, &umr_bitfield_default },
	 { "CID3_MASK", 3, 3, &umr_bitfield_default },
	 { "CID4_MASK", 4, 4, &umr_bitfield_default },
	 { "CID5_MASK", 5, 5, &umr_bitfield_default },
	 { "CID6_MASK", 6, 6, &umr_bitfield_default },
	 { "CID7_MASK", 7, 7, &umr_bitfield_default },
	 { "CID8_MASK", 8, 8, &umr_bitfield_default },
	 { "CID9_MASK", 9, 9, &umr_bitfield_default },
	 { "CID10_MASK", 10, 10, &umr_bitfield_default },
	 { "CID11_MASK", 11, 11, &umr_bitfield_default },
	 { "CID12_MASK", 12, 12, &umr_bitfield_default },
	 { "CID13_MASK", 13, 13, &umr_bitfield_default },
	 { "CID14_MASK", 14, 14, &umr_bitfield_default },
	 { "CID15_MASK", 15, 15, &umr_bitfield_default },
	 { "CID16_MASK", 16, 16, &umr_bitfield_default },
	 { "CID17_MASK", 17, 17, &umr_bitfield_default },
	 { "CID18_MASK", 18, 18, &umr_bitfield_default },
	 { "CID19_MASK", 19, 19, &umr_bitfield_default },
	 { "CID20_MASK", 20, 20, &umr_bitfield_default },
	 { "CID21_MASK", 21, 21, &umr_bitfield_default },
	 { "CID22_MASK", 22, 22, &umr_bitfield_default },
	 { "CID23_MASK", 23, 23, &umr_bitfield_default },
	 { "CID24_MASK", 24, 24, &umr_bitfield_default },
	 { "CID25_MASK", 25, 25, &umr_bitfield_default },
	 { "CID26_MASK", 26, 26, &umr_bitfield_default },
	 { "CID27_MASK", 27, 27, &umr_bitfield_default },
	 { "CID28_MASK", 28, 28, &umr_bitfield_default },
	 { "CID29_MASK", 29, 29, &umr_bitfield_default },
	 { "CID30_MASK", 30, 30, &umr_bitfield_default },
	 { "CID31_MASK", 31, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMMEA0_IO_WR_PRI_URGENCY_MASK[] = {
	 { "CID0_MASK", 0, 0, &umr_bitfield_default },
	 { "CID1_MASK", 1, 1, &umr_bitfield_default },
	 { "CID2_MASK", 2, 2, &umr_bitfield_default },
	 { "CID3_MASK", 3, 3, &umr_bitfield_default },
	 { "CID4_MASK", 4, 4, &umr_bitfield_default },
	 { "CID5_MASK", 5, 5, &umr_bitfield_default },
	 { "CID6_MASK", 6, 6, &umr_bitfield_default },
	 { "CID7_MASK", 7, 7, &umr_bitfield_default },
	 { "CID8_MASK", 8, 8, &umr_bitfield_default },
	 { "CID9_MASK", 9, 9, &umr_bitfield_default },
	 { "CID10_MASK", 10, 10, &umr_bitfield_default },
	 { "CID11_MASK", 11, 11, &umr_bitfield_default },
	 { "CID12_MASK", 12, 12, &umr_bitfield_default },
	 { "CID13_MASK", 13, 13, &umr_bitfield_default },
	 { "CID14_MASK", 14, 14, &umr_bitfield_default },
	 { "CID15_MASK", 15, 15, &umr_bitfield_default },
	 { "CID16_MASK", 16, 16, &umr_bitfield_default },
	 { "CID17_MASK", 17, 17, &umr_bitfield_default },
	 { "CID18_MASK", 18, 18, &umr_bitfield_default },
	 { "CID19_MASK", 19, 19, &umr_bitfield_default },
	 { "CID20_MASK", 20, 20, &umr_bitfield_default },
	 { "CID21_MASK", 21, 21, &umr_bitfield_default },
	 { "CID22_MASK", 22, 22, &umr_bitfield_default },
	 { "CID23_MASK", 23, 23, &umr_bitfield_default },
	 { "CID24_MASK", 24, 24, &umr_bitfield_default },
	 { "CID25_MASK", 25, 25, &umr_bitfield_default },
	 { "CID26_MASK", 26, 26, &umr_bitfield_default },
	 { "CID27_MASK", 27, 27, &umr_bitfield_default },
	 { "CID28_MASK", 28, 28, &umr_bitfield_default },
	 { "CID29_MASK", 29, 29, &umr_bitfield_default },
	 { "CID30_MASK", 30, 30, &umr_bitfield_default },
	 { "CID31_MASK", 31, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMMEA0_IO_RD_PRI_QUANT_PRI1[] = {
	 { "GROUP0_THRESHOLD", 0, 7, &umr_bitfield_default },
	 { "GROUP1_THRESHOLD", 8, 15, &umr_bitfield_default },
	 { "GROUP2_THRESHOLD", 16, 23, &umr_bitfield_default },
	 { "GROUP3_THRESHOLD", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMMEA0_IO_RD_PRI_QUANT_PRI2[] = {
	 { "GROUP0_THRESHOLD", 0, 7, &umr_bitfield_default },
	 { "GROUP1_THRESHOLD", 8, 15, &umr_bitfield_default },
	 { "GROUP2_THRESHOLD", 16, 23, &umr_bitfield_default },
	 { "GROUP3_THRESHOLD", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMMEA0_IO_RD_PRI_QUANT_PRI3[] = {
	 { "GROUP0_THRESHOLD", 0, 7, &umr_bitfield_default },
	 { "GROUP1_THRESHOLD", 8, 15, &umr_bitfield_default },
	 { "GROUP2_THRESHOLD", 16, 23, &umr_bitfield_default },
	 { "GROUP3_THRESHOLD", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMMEA0_IO_WR_PRI_QUANT_PRI1[] = {
	 { "GROUP0_THRESHOLD", 0, 7, &umr_bitfield_default },
	 { "GROUP1_THRESHOLD", 8, 15, &umr_bitfield_default },
	 { "GROUP2_THRESHOLD", 16, 23, &umr_bitfield_default },
	 { "GROUP3_THRESHOLD", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMMEA0_IO_WR_PRI_QUANT_PRI2[] = {
	 { "GROUP0_THRESHOLD", 0, 7, &umr_bitfield_default },
	 { "GROUP1_THRESHOLD", 8, 15, &umr_bitfield_default },
	 { "GROUP2_THRESHOLD", 16, 23, &umr_bitfield_default },
	 { "GROUP3_THRESHOLD", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMMEA0_IO_WR_PRI_QUANT_PRI3[] = {
	 { "GROUP0_THRESHOLD", 0, 7, &umr_bitfield_default },
	 { "GROUP1_THRESHOLD", 8, 15, &umr_bitfield_default },
	 { "GROUP2_THRESHOLD", 16, 23, &umr_bitfield_default },
	 { "GROUP3_THRESHOLD", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMMEA0_SDP_ARB_DRAM[] = {
	 { "RDWR_BURST_LIMIT_CYCL", 0, 6, &umr_bitfield_default },
	 { "RDWR_BURST_LIMIT_DATA", 8, 14, &umr_bitfield_default },
	 { "EARLY_SW2RD_ON_PRI", 16, 16, &umr_bitfield_default },
	 { "EARLY_SW2WR_ON_PRI", 17, 17, &umr_bitfield_default },
	 { "EARLY_SW2RD_ON_RES", 18, 18, &umr_bitfield_default },
	 { "EARLY_SW2WR_ON_RES", 19, 19, &umr_bitfield_default },
	 { "EOB_ON_EXPIRE", 20, 20, &umr_bitfield_default },
};
static struct umr_bitfield mmMMEA0_SDP_ARB_FINAL[] = {
	 { "DRAM_BURST_LIMIT", 0, 4, &umr_bitfield_default },
	 { "GMI_BURST_LIMIT", 5, 9, &umr_bitfield_default },
	 { "IO_BURST_LIMIT", 10, 14, &umr_bitfield_default },
	 { "BURST_LIMIT_MULTIPLIER", 15, 16, &umr_bitfield_default },
	 { "RDONLY_VC0", 17, 17, &umr_bitfield_default },
	 { "RDONLY_VC1", 18, 18, &umr_bitfield_default },
	 { "RDONLY_VC2", 19, 19, &umr_bitfield_default },
	 { "RDONLY_VC3", 20, 20, &umr_bitfield_default },
	 { "RDONLY_VC4", 21, 21, &umr_bitfield_default },
	 { "RDONLY_VC5", 22, 22, &umr_bitfield_default },
	 { "RDONLY_VC6", 23, 23, &umr_bitfield_default },
	 { "RDONLY_VC7", 24, 24, &umr_bitfield_default },
	 { "ERREVENT_ON_ERROR", 25, 25, &umr_bitfield_default },
	 { "HALTREQ_ON_ERROR", 26, 26, &umr_bitfield_default },
};
static struct umr_bitfield mmMMEA0_SDP_DRAM_PRIORITY[] = {
	 { "RD_GROUP0_PRIORITY", 0, 3, &umr_bitfield_default },
	 { "RD_GROUP1_PRIORITY", 4, 7, &umr_bitfield_default },
	 { "RD_GROUP2_PRIORITY", 8, 11, &umr_bitfield_default },
	 { "RD_GROUP3_PRIORITY", 12, 15, &umr_bitfield_default },
	 { "WR_GROUP0_PRIORITY", 16, 19, &umr_bitfield_default },
	 { "WR_GROUP1_PRIORITY", 20, 23, &umr_bitfield_default },
	 { "WR_GROUP2_PRIORITY", 24, 27, &umr_bitfield_default },
	 { "WR_GROUP3_PRIORITY", 28, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMMEA0_SDP_IO_PRIORITY[] = {
	 { "RD_GROUP0_PRIORITY", 0, 3, &umr_bitfield_default },
	 { "RD_GROUP1_PRIORITY", 4, 7, &umr_bitfield_default },
	 { "RD_GROUP2_PRIORITY", 8, 11, &umr_bitfield_default },
	 { "RD_GROUP3_PRIORITY", 12, 15, &umr_bitfield_default },
	 { "WR_GROUP0_PRIORITY", 16, 19, &umr_bitfield_default },
	 { "WR_GROUP1_PRIORITY", 20, 23, &umr_bitfield_default },
	 { "WR_GROUP2_PRIORITY", 24, 27, &umr_bitfield_default },
	 { "WR_GROUP3_PRIORITY", 28, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMMEA0_SDP_CREDITS[] = {
	 { "TAG_LIMIT", 0, 7, &umr_bitfield_default },
	 { "WR_RESP_CREDITS", 8, 14, &umr_bitfield_default },
	 { "RD_RESP_CREDITS", 16, 22, &umr_bitfield_default },
};
static struct umr_bitfield mmMMEA0_SDP_TAG_RESERVE0[] = {
	 { "VC0", 0, 7, &umr_bitfield_default },
	 { "VC1", 8, 15, &umr_bitfield_default },
	 { "VC2", 16, 23, &umr_bitfield_default },
	 { "VC3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMMEA0_SDP_TAG_RESERVE1[] = {
	 { "VC4", 0, 7, &umr_bitfield_default },
	 { "VC5", 8, 15, &umr_bitfield_default },
	 { "VC6", 16, 23, &umr_bitfield_default },
	 { "VC7", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMMEA0_SDP_VCC_RESERVE0[] = {
	 { "VC0_CREDITS", 0, 5, &umr_bitfield_default },
	 { "VC1_CREDITS", 6, 11, &umr_bitfield_default },
	 { "VC2_CREDITS", 12, 17, &umr_bitfield_default },
	 { "VC3_CREDITS", 18, 23, &umr_bitfield_default },
	 { "VC4_CREDITS", 24, 29, &umr_bitfield_default },
};
static struct umr_bitfield mmMMEA0_SDP_VCC_RESERVE1[] = {
	 { "VC5_CREDITS", 0, 5, &umr_bitfield_default },
	 { "VC6_CREDITS", 6, 11, &umr_bitfield_default },
	 { "VC7_CREDITS", 12, 17, &umr_bitfield_default },
	 { "DISTRIBUTE_POOL", 31, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMMEA0_SDP_VCD_RESERVE0[] = {
	 { "VC0_CREDITS", 0, 5, &umr_bitfield_default },
	 { "VC1_CREDITS", 6, 11, &umr_bitfield_default },
	 { "VC2_CREDITS", 12, 17, &umr_bitfield_default },
	 { "VC3_CREDITS", 18, 23, &umr_bitfield_default },
	 { "VC4_CREDITS", 24, 29, &umr_bitfield_default },
};
static struct umr_bitfield mmMMEA0_SDP_VCD_RESERVE1[] = {
	 { "VC5_CREDITS", 0, 5, &umr_bitfield_default },
	 { "VC6_CREDITS", 6, 11, &umr_bitfield_default },
	 { "VC7_CREDITS", 12, 17, &umr_bitfield_default },
	 { "DISTRIBUTE_POOL", 31, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMMEA0_SDP_REQ_CNTL[] = {
	 { "REQ_PASS_PW_OVERRIDE_READ", 0, 0, &umr_bitfield_default },
	 { "REQ_PASS_PW_OVERRIDE_WRITE", 1, 1, &umr_bitfield_default },
	 { "REQ_PASS_PW_OVERRIDE_ATOMIC", 2, 2, &umr_bitfield_default },
	 { "REQ_CHAIN_OVERRIDE_DRAM", 3, 3, &umr_bitfield_default },
	 { "INNER_DOMAIN_MODE", 4, 4, &umr_bitfield_default },
};
static struct umr_bitfield mmMMEA0_MISC[] = {
	 { "RELATIVE_PRI_IN_DRAM_RD_ARB", 0, 0, &umr_bitfield_default },
	 { "RELATIVE_PRI_IN_DRAM_WR_ARB", 1, 1, &umr_bitfield_default },
	 { "RELATIVE_PRI_IN_GMI_RD_ARB", 2, 2, &umr_bitfield_default },
	 { "RELATIVE_PRI_IN_GMI_WR_ARB", 3, 3, &umr_bitfield_default },
	 { "RELATIVE_PRI_IN_IO_RD_ARB", 4, 4, &umr_bitfield_default },
	 { "RELATIVE_PRI_IN_IO_WR_ARB", 5, 5, &umr_bitfield_default },
	 { "RRET_SWAP_MODE", 6, 6, &umr_bitfield_default },
	 { "EARLY_SDP_ORIGDATA", 7, 7, &umr_bitfield_default },
	 { "LINKMGR_DYNAMIC_MODE", 8, 9, &umr_bitfield_default },
	 { "LINKMGR_HALT_THRESHOLD", 10, 11, &umr_bitfield_default },
	 { "LINKMGR_RECONNECT_DELAY", 12, 13, &umr_bitfield_default },
	 { "LINKMGR_IDLE_THRESHOLD", 14, 18, &umr_bitfield_default },
	 { "FAVOUR_MIDCHAIN_CS_IN_DRAM_ARB", 19, 19, &umr_bitfield_default },
	 { "FAVOUR_MIDCHAIN_CS_IN_GMI_ARB", 20, 20, &umr_bitfield_default },
	 { "FAVOUR_LAST_CS_IN_DRAM_ARB", 21, 21, &umr_bitfield_default },
	 { "FAVOUR_LAST_CS_IN_GMI_ARB", 22, 22, &umr_bitfield_default },
	 { "SWITCH_CS_ON_W2R_IN_DRAM_ARB", 23, 23, &umr_bitfield_default },
	 { "SWITCH_CS_ON_W2R_IN_GMI_ARB", 24, 24, &umr_bitfield_default },
};
static struct umr_bitfield mmMMEA0_LATENCY_SAMPLING[] = {
	 { "SAMPLER0_DRAM", 0, 0, &umr_bitfield_default },
	 { "SAMPLER1_DRAM", 1, 1, &umr_bitfield_default },
	 { "SAMPLER0_GMI", 2, 2, &umr_bitfield_default },
	 { "SAMPLER1_GMI", 3, 3, &umr_bitfield_default },
	 { "SAMPLER0_IO", 4, 4, &umr_bitfield_default },
	 { "SAMPLER1_IO", 5, 5, &umr_bitfield_default },
	 { "SAMPLER0_READ", 6, 6, &umr_bitfield_default },
	 { "SAMPLER1_READ", 7, 7, &umr_bitfield_default },
	 { "SAMPLER0_WRITE", 8, 8, &umr_bitfield_default },
	 { "SAMPLER1_WRITE", 9, 9, &umr_bitfield_default },
	 { "SAMPLER0_ATOMIC_RET", 10, 10, &umr_bitfield_default },
	 { "SAMPLER1_ATOMIC_RET", 11, 11, &umr_bitfield_default },
	 { "SAMPLER0_ATOMIC_NORET", 12, 12, &umr_bitfield_default },
	 { "SAMPLER1_ATOMIC_NORET", 13, 13, &umr_bitfield_default },
	 { "SAMPLER0_VC", 14, 21, &umr_bitfield_default },
	 { "SAMPLER1_VC", 22, 29, &umr_bitfield_default },
};
static struct umr_bitfield mmMMEA0_PERFCOUNTER_LO[] = {
	 { "COUNTER_LO", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMMEA0_PERFCOUNTER_HI[] = {
	 { "COUNTER_HI", 0, 15, &umr_bitfield_default },
	 { "COMPARE_VALUE", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMMEA0_PERFCOUNTER0_CFG[] = {
	 { "PERF_SEL", 0, 7, &umr_bitfield_default },
	 { "PERF_SEL_END", 8, 15, &umr_bitfield_default },
	 { "PERF_MODE", 24, 27, &umr_bitfield_default },
	 { "ENABLE", 28, 28, &umr_bitfield_default },
	 { "CLEAR", 29, 29, &umr_bitfield_default },
};
static struct umr_bitfield mmMMEA0_PERFCOUNTER1_CFG[] = {
	 { "PERF_SEL", 0, 7, &umr_bitfield_default },
	 { "PERF_SEL_END", 8, 15, &umr_bitfield_default },
	 { "PERF_MODE", 24, 27, &umr_bitfield_default },
	 { "ENABLE", 28, 28, &umr_bitfield_default },
	 { "CLEAR", 29, 29, &umr_bitfield_default },
};
static struct umr_bitfield mmMMEA0_PERFCOUNTER_RSLT_CNTL[] = {
	 { "PERF_COUNTER_SELECT", 0, 3, &umr_bitfield_default },
	 { "START_TRIGGER", 8, 15, &umr_bitfield_default },
	 { "STOP_TRIGGER", 16, 23, &umr_bitfield_default },
	 { "ENABLE_ANY", 24, 24, &umr_bitfield_default },
	 { "CLEAR_ALL", 25, 25, &umr_bitfield_default },
	 { "STOP_ALL_ON_SATURATE", 26, 26, &umr_bitfield_default },
};
static struct umr_bitfield mmMMEA0_EDC_CNT[] = {
	 { "DRAMRD_CMDMEM_SEC_COUNT", 0, 1, &umr_bitfield_default },
	 { "DRAMRD_CMDMEM_DED_COUNT", 2, 3, &umr_bitfield_default },
	 { "DRAMWR_CMDMEM_SEC_COUNT", 4, 5, &umr_bitfield_default },
	 { "DRAMWR_CMDMEM_DED_COUNT", 6, 7, &umr_bitfield_default },
	 { "DRAMWR_DATAMEM_SEC_COUNT", 8, 9, &umr_bitfield_default },
	 { "DRAMWR_DATAMEM_DED_COUNT", 10, 11, &umr_bitfield_default },
	 { "RRET_TAGMEM_SEC_COUNT", 12, 13, &umr_bitfield_default },
	 { "RRET_TAGMEM_DED_COUNT", 14, 15, &umr_bitfield_default },
	 { "WRET_TAGMEM_SEC_COUNT", 16, 17, &umr_bitfield_default },
	 { "WRET_TAGMEM_DED_COUNT", 18, 19, &umr_bitfield_default },
	 { "DRAMRD_PAGEMEM_SED_COUNT", 20, 21, &umr_bitfield_default },
	 { "DRAMWR_PAGEMEM_SED_COUNT", 22, 23, &umr_bitfield_default },
	 { "IORD_CMDMEM_SED_COUNT", 24, 25, &umr_bitfield_default },
	 { "IOWR_CMDMEM_SED_COUNT", 26, 27, &umr_bitfield_default },
	 { "IOWR_DATAMEM_SED_COUNT", 28, 29, &umr_bitfield_default },
};
static struct umr_bitfield mmMMEA0_EDC_CNT2[] = {
	 { "GMIRD_CMDMEM_SEC_COUNT", 0, 1, &umr_bitfield_default },
	 { "GMIRD_CMDMEM_DED_COUNT", 2, 3, &umr_bitfield_default },
	 { "GMIWR_CMDMEM_SEC_COUNT", 4, 5, &umr_bitfield_default },
	 { "GMIWR_CMDMEM_DED_COUNT", 6, 7, &umr_bitfield_default },
	 { "GMIWR_DATAMEM_SEC_COUNT", 8, 9, &umr_bitfield_default },
	 { "GMIWR_DATAMEM_DED_COUNT", 10, 11, &umr_bitfield_default },
	 { "GMIRD_PAGEMEM_SED_COUNT", 12, 13, &umr_bitfield_default },
	 { "GMIWR_PAGEMEM_SED_COUNT", 14, 15, &umr_bitfield_default },
};
static struct umr_bitfield mmMMEA0_DSM_CNTL[] = {
	 { "DRAMRD_CMDMEM_DSM_IRRITATOR_DATA", 0, 1, &umr_bitfield_default },
	 { "DRAMRD_CMDMEM_ENABLE_SINGLE_WRITE", 2, 2, &umr_bitfield_default },
	 { "DRAMWR_CMDMEM_DSM_IRRITATOR_DATA", 3, 4, &umr_bitfield_default },
	 { "DRAMWR_CMDMEM_ENABLE_SINGLE_WRITE", 5, 5, &umr_bitfield_default },
	 { "DRAMWR_DATAMEM_DSM_IRRITATOR_DATA", 6, 7, &umr_bitfield_default },
	 { "DRAMWR_DATAMEM_ENABLE_SINGLE_WRITE", 8, 8, &umr_bitfield_default },
	 { "RRET_TAGMEM_DSM_IRRITATOR_DATA", 9, 10, &umr_bitfield_default },
	 { "RRET_TAGMEM_ENABLE_SINGLE_WRITE", 11, 11, &umr_bitfield_default },
	 { "WRET_TAGMEM_DSM_IRRITATOR_DATA", 12, 13, &umr_bitfield_default },
	 { "WRET_TAGMEM_ENABLE_SINGLE_WRITE", 14, 14, &umr_bitfield_default },
	 { "GMIRD_CMDMEM_DSM_IRRITATOR_DATA", 15, 16, &umr_bitfield_default },
	 { "GMIRD_CMDMEM_ENABLE_SINGLE_WRITE", 17, 17, &umr_bitfield_default },
	 { "GMIWR_CMDMEM_DSM_IRRITATOR_DATA", 18, 19, &umr_bitfield_default },
	 { "GMIWR_CMDMEM_ENABLE_SINGLE_WRITE", 20, 20, &umr_bitfield_default },
	 { "GMIWR_DATAMEM_DSM_IRRITATOR_DATA", 21, 22, &umr_bitfield_default },
	 { "GMIWR_DATAMEM_ENABLE_SINGLE_WRITE", 23, 23, &umr_bitfield_default },
};
static struct umr_bitfield mmMMEA0_DSM_CNTLA[] = {
	 { "DRAMRD_PAGEMEM_DSM_IRRITATOR_DATA", 0, 1, &umr_bitfield_default },
	 { "DRAMRD_PAGEMEM_ENABLE_SINGLE_WRITE", 2, 2, &umr_bitfield_default },
	 { "DRAMWR_PAGEMEM_DSM_IRRITATOR_DATA", 3, 4, &umr_bitfield_default },
	 { "DRAMWR_PAGEMEM_ENABLE_SINGLE_WRITE", 5, 5, &umr_bitfield_default },
	 { "IORD_CMDMEM_DSM_IRRITATOR_DATA", 6, 7, &umr_bitfield_default },
	 { "IORD_CMDMEM_ENABLE_SINGLE_WRITE", 8, 8, &umr_bitfield_default },
	 { "IOWR_CMDMEM_DSM_IRRITATOR_DATA", 9, 10, &umr_bitfield_default },
	 { "IOWR_CMDMEM_ENABLE_SINGLE_WRITE", 11, 11, &umr_bitfield_default },
	 { "IOWR_DATAMEM_DSM_IRRITATOR_DATA", 12, 13, &umr_bitfield_default },
	 { "IOWR_DATAMEM_ENABLE_SINGLE_WRITE", 14, 14, &umr_bitfield_default },
	 { "GMIRD_PAGEMEM_DSM_IRRITATOR_DATA", 15, 16, &umr_bitfield_default },
	 { "GMIRD_PAGEMEM_ENABLE_SINGLE_WRITE", 17, 17, &umr_bitfield_default },
	 { "GMIWR_PAGEMEM_DSM_IRRITATOR_DATA", 18, 19, &umr_bitfield_default },
	 { "GMIWR_PAGEMEM_ENABLE_SINGLE_WRITE", 20, 20, &umr_bitfield_default },
};
static struct umr_bitfield mmMMEA0_DSM_CNTL2[] = {
	 { "DRAMRD_CMDMEM_ENABLE_ERROR_INJECT", 0, 1, &umr_bitfield_default },
	 { "DRAMRD_CMDMEM_SELECT_INJECT_DELAY", 2, 2, &umr_bitfield_default },
	 { "DRAMWR_CMDMEM_ENABLE_ERROR_INJECT", 3, 4, &umr_bitfield_default },
	 { "DRAMWR_CMDMEM_SELECT_INJECT_DELAY", 5, 5, &umr_bitfield_default },
	 { "DRAMWR_DATAMEM_ENABLE_ERROR_INJECT", 6, 7, &umr_bitfield_default },
	 { "DRAMWR_DATAMEM_SELECT_INJECT_DELAY", 8, 8, &umr_bitfield_default },
	 { "RRET_TAGMEM_ENABLE_ERROR_INJECT", 9, 10, &umr_bitfield_default },
	 { "RRET_TAGMEM_SELECT_INJECT_DELAY", 11, 11, &umr_bitfield_default },
	 { "WRET_TAGMEM_ENABLE_ERROR_INJECT", 12, 13, &umr_bitfield_default },
	 { "WRET_TAGMEM_SELECT_INJECT_DELAY", 14, 14, &umr_bitfield_default },
	 { "GMIRD_CMDMEM_ENABLE_ERROR_INJECT", 15, 16, &umr_bitfield_default },
	 { "GMIRD_CMDMEM_SELECT_INJECT_DELAY", 17, 17, &umr_bitfield_default },
	 { "GMIWR_CMDMEM_ENABLE_ERROR_INJECT", 18, 19, &umr_bitfield_default },
	 { "GMIWR_CMDMEM_SELECT_INJECT_DELAY", 20, 20, &umr_bitfield_default },
	 { "GMIWR_DATAMEM_ENABLE_ERROR_INJECT", 21, 22, &umr_bitfield_default },
	 { "GMIWR_DATAMEM_SELECT_INJECT_DELAY", 23, 23, &umr_bitfield_default },
	 { "INJECT_DELAY", 26, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMMEA0_DSM_CNTL2A[] = {
	 { "DRAMRD_PAGEMEM_ENABLE_ERROR_INJECT", 0, 1, &umr_bitfield_default },
	 { "DRAMRD_PAGEMEM_SELECT_INJECT_DELAY", 2, 2, &umr_bitfield_default },
	 { "DRAMWR_PAGEMEM_ENABLE_ERROR_INJECT", 3, 4, &umr_bitfield_default },
	 { "DRAMWR_PAGEMEM_SELECT_INJECT_DELAY", 5, 5, &umr_bitfield_default },
	 { "IORD_CMDMEM_ENABLE_ERROR_INJECT", 6, 7, &umr_bitfield_default },
	 { "IORD_CMDMEM_SELECT_INJECT_DELAY", 8, 8, &umr_bitfield_default },
	 { "IOWR_CMDMEM_ENABLE_ERROR_INJECT", 9, 10, &umr_bitfield_default },
	 { "IOWR_CMDMEM_SELECT_INJECT_DELAY", 11, 11, &umr_bitfield_default },
	 { "IOWR_DATAMEM_ENABLE_ERROR_INJECT", 12, 13, &umr_bitfield_default },
	 { "IOWR_DATAMEM_SELECT_INJECT_DELAY", 14, 14, &umr_bitfield_default },
	 { "GMIRD_PAGEMEM_ENABLE_ERROR_INJECT", 15, 16, &umr_bitfield_default },
	 { "GMIRD_PAGEMEM_SELECT_INJECT_DELAY", 17, 17, &umr_bitfield_default },
	 { "GMIWR_PAGEMEM_ENABLE_ERROR_INJECT", 18, 19, &umr_bitfield_default },
	 { "GMIWR_PAGEMEM_SELECT_INJECT_DELAY", 20, 20, &umr_bitfield_default },
};
static struct umr_bitfield mmMMEA0_CGTT_CLK_CTRL[] = {
	 { "ON_DELAY", 0, 3, &umr_bitfield_default },
	 { "OFF_HYSTERESIS", 4, 11, &umr_bitfield_default },
	 { "SOFT_STALL_OVERRIDE", 22, 22, &umr_bitfield_default },
	 { "LS_OVERRIDE", 27, 27, &umr_bitfield_default },
	 { "SOFT_OVERRIDE_WRITE", 28, 28, &umr_bitfield_default },
	 { "SOFT_OVERRIDE_READ", 29, 29, &umr_bitfield_default },
	 { "SOFT_OVERRIDE_RETURN", 30, 30, &umr_bitfield_default },
	 { "SOFT_OVERRIDE_REGISTER", 31, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMMEA0_EDC_MODE[] = {
	 { "COUNT_FED_OUT", 16, 16, &umr_bitfield_default },
	 { "GATE_FUE", 17, 17, &umr_bitfield_default },
	 { "DED_MODE", 20, 21, &umr_bitfield_default },
	 { "PROP_FED", 29, 29, &umr_bitfield_default },
	 { "BYPASS", 31, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMMEA0_ERR_STATUS[] = {
	 { "SDP_RDRSP_STATUS", 0, 3, &umr_bitfield_default },
	 { "SDP_WRRSP_STATUS", 4, 7, &umr_bitfield_default },
	 { "SDP_RDRSP_DATAPARITY_ERROR", 8, 8, &umr_bitfield_default },
	 { "CLEAR_ERROR_STATUS", 9, 9, &umr_bitfield_default },
	 { "BUSY_ON_ERROR", 10, 10, &umr_bitfield_default },
};
static struct umr_bitfield mmMMEA0_MISC2[] = {
	 { "CSGROUP_SWAP_IN_DRAM_ARB", 0, 0, &umr_bitfield_default },
	 { "CSGROUP_SWAP_IN_GMI_ARB", 1, 1, &umr_bitfield_default },
	 { "CSGRP_BURST_LIMIT_DATA_DRAM", 2, 6, &umr_bitfield_default },
	 { "CSGRP_BURST_LIMIT_DATA_GMI", 7, 11, &umr_bitfield_default },
};
static struct umr_bitfield mmMMEA1_DRAM_RD_CLI2GRP_MAP0[] = {
	 { "CID0_GROUP", 0, 1, &umr_bitfield_default },
	 { "CID1_GROUP", 2, 3, &umr_bitfield_default },
	 { "CID2_GROUP", 4, 5, &umr_bitfield_default },
	 { "CID3_GROUP", 6, 7, &umr_bitfield_default },
	 { "CID4_GROUP", 8, 9, &umr_bitfield_default },
	 { "CID5_GROUP", 10, 11, &umr_bitfield_default },
	 { "CID6_GROUP", 12, 13, &umr_bitfield_default },
	 { "CID7_GROUP", 14, 15, &umr_bitfield_default },
	 { "CID8_GROUP", 16, 17, &umr_bitfield_default },
	 { "CID9_GROUP", 18, 19, &umr_bitfield_default },
	 { "CID10_GROUP", 20, 21, &umr_bitfield_default },
	 { "CID11_GROUP", 22, 23, &umr_bitfield_default },
	 { "CID12_GROUP", 24, 25, &umr_bitfield_default },
	 { "CID13_GROUP", 26, 27, &umr_bitfield_default },
	 { "CID14_GROUP", 28, 29, &umr_bitfield_default },
	 { "CID15_GROUP", 30, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMMEA1_DRAM_RD_CLI2GRP_MAP1[] = {
	 { "CID16_GROUP", 0, 1, &umr_bitfield_default },
	 { "CID17_GROUP", 2, 3, &umr_bitfield_default },
	 { "CID18_GROUP", 4, 5, &umr_bitfield_default },
	 { "CID19_GROUP", 6, 7, &umr_bitfield_default },
	 { "CID20_GROUP", 8, 9, &umr_bitfield_default },
	 { "CID21_GROUP", 10, 11, &umr_bitfield_default },
	 { "CID22_GROUP", 12, 13, &umr_bitfield_default },
	 { "CID23_GROUP", 14, 15, &umr_bitfield_default },
	 { "CID24_GROUP", 16, 17, &umr_bitfield_default },
	 { "CID25_GROUP", 18, 19, &umr_bitfield_default },
	 { "CID26_GROUP", 20, 21, &umr_bitfield_default },
	 { "CID27_GROUP", 22, 23, &umr_bitfield_default },
	 { "CID28_GROUP", 24, 25, &umr_bitfield_default },
	 { "CID29_GROUP", 26, 27, &umr_bitfield_default },
	 { "CID30_GROUP", 28, 29, &umr_bitfield_default },
	 { "CID31_GROUP", 30, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMMEA1_DRAM_WR_CLI2GRP_MAP0[] = {
	 { "CID0_GROUP", 0, 1, &umr_bitfield_default },
	 { "CID1_GROUP", 2, 3, &umr_bitfield_default },
	 { "CID2_GROUP", 4, 5, &umr_bitfield_default },
	 { "CID3_GROUP", 6, 7, &umr_bitfield_default },
	 { "CID4_GROUP", 8, 9, &umr_bitfield_default },
	 { "CID5_GROUP", 10, 11, &umr_bitfield_default },
	 { "CID6_GROUP", 12, 13, &umr_bitfield_default },
	 { "CID7_GROUP", 14, 15, &umr_bitfield_default },
	 { "CID8_GROUP", 16, 17, &umr_bitfield_default },
	 { "CID9_GROUP", 18, 19, &umr_bitfield_default },
	 { "CID10_GROUP", 20, 21, &umr_bitfield_default },
	 { "CID11_GROUP", 22, 23, &umr_bitfield_default },
	 { "CID12_GROUP", 24, 25, &umr_bitfield_default },
	 { "CID13_GROUP", 26, 27, &umr_bitfield_default },
	 { "CID14_GROUP", 28, 29, &umr_bitfield_default },
	 { "CID15_GROUP", 30, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMMEA1_DRAM_WR_CLI2GRP_MAP1[] = {
	 { "CID16_GROUP", 0, 1, &umr_bitfield_default },
	 { "CID17_GROUP", 2, 3, &umr_bitfield_default },
	 { "CID18_GROUP", 4, 5, &umr_bitfield_default },
	 { "CID19_GROUP", 6, 7, &umr_bitfield_default },
	 { "CID20_GROUP", 8, 9, &umr_bitfield_default },
	 { "CID21_GROUP", 10, 11, &umr_bitfield_default },
	 { "CID22_GROUP", 12, 13, &umr_bitfield_default },
	 { "CID23_GROUP", 14, 15, &umr_bitfield_default },
	 { "CID24_GROUP", 16, 17, &umr_bitfield_default },
	 { "CID25_GROUP", 18, 19, &umr_bitfield_default },
	 { "CID26_GROUP", 20, 21, &umr_bitfield_default },
	 { "CID27_GROUP", 22, 23, &umr_bitfield_default },
	 { "CID28_GROUP", 24, 25, &umr_bitfield_default },
	 { "CID29_GROUP", 26, 27, &umr_bitfield_default },
	 { "CID30_GROUP", 28, 29, &umr_bitfield_default },
	 { "CID31_GROUP", 30, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMMEA1_DRAM_RD_GRP2VC_MAP[] = {
	 { "GROUP0_VC", 0, 2, &umr_bitfield_default },
	 { "GROUP1_VC", 3, 5, &umr_bitfield_default },
	 { "GROUP2_VC", 6, 8, &umr_bitfield_default },
	 { "GROUP3_VC", 9, 11, &umr_bitfield_default },
};
static struct umr_bitfield mmMMEA1_DRAM_WR_GRP2VC_MAP[] = {
	 { "GROUP0_VC", 0, 2, &umr_bitfield_default },
	 { "GROUP1_VC", 3, 5, &umr_bitfield_default },
	 { "GROUP2_VC", 6, 8, &umr_bitfield_default },
	 { "GROUP3_VC", 9, 11, &umr_bitfield_default },
};
static struct umr_bitfield mmMMEA1_DRAM_RD_LAZY[] = {
	 { "GROUP0_DELAY", 0, 2, &umr_bitfield_default },
	 { "GROUP1_DELAY", 3, 5, &umr_bitfield_default },
	 { "GROUP2_DELAY", 6, 8, &umr_bitfield_default },
	 { "GROUP3_DELAY", 9, 11, &umr_bitfield_default },
};
static struct umr_bitfield mmMMEA1_DRAM_WR_LAZY[] = {
	 { "GROUP0_DELAY", 0, 2, &umr_bitfield_default },
	 { "GROUP1_DELAY", 3, 5, &umr_bitfield_default },
	 { "GROUP2_DELAY", 6, 8, &umr_bitfield_default },
	 { "GROUP3_DELAY", 9, 11, &umr_bitfield_default },
};
static struct umr_bitfield mmMMEA1_DRAM_RD_CAM_CNTL[] = {
	 { "DEPTH_GROUP0", 0, 3, &umr_bitfield_default },
	 { "DEPTH_GROUP1", 4, 7, &umr_bitfield_default },
	 { "DEPTH_GROUP2", 8, 11, &umr_bitfield_default },
	 { "DEPTH_GROUP3", 12, 15, &umr_bitfield_default },
	 { "REORDER_LIMIT_GROUP0", 16, 18, &umr_bitfield_default },
	 { "REORDER_LIMIT_GROUP1", 19, 21, &umr_bitfield_default },
	 { "REORDER_LIMIT_GROUP2", 22, 24, &umr_bitfield_default },
	 { "REORDER_LIMIT_GROUP3", 25, 27, &umr_bitfield_default },
};
static struct umr_bitfield mmMMEA1_DRAM_WR_CAM_CNTL[] = {
	 { "DEPTH_GROUP0", 0, 3, &umr_bitfield_default },
	 { "DEPTH_GROUP1", 4, 7, &umr_bitfield_default },
	 { "DEPTH_GROUP2", 8, 11, &umr_bitfield_default },
	 { "DEPTH_GROUP3", 12, 15, &umr_bitfield_default },
	 { "REORDER_LIMIT_GROUP0", 16, 18, &umr_bitfield_default },
	 { "REORDER_LIMIT_GROUP1", 19, 21, &umr_bitfield_default },
	 { "REORDER_LIMIT_GROUP2", 22, 24, &umr_bitfield_default },
	 { "REORDER_LIMIT_GROUP3", 25, 27, &umr_bitfield_default },
};
static struct umr_bitfield mmMMEA1_DRAM_PAGE_BURST[] = {
	 { "RD_LIMIT_LO", 0, 7, &umr_bitfield_default },
	 { "RD_LIMIT_HI", 8, 15, &umr_bitfield_default },
	 { "WR_LIMIT_LO", 16, 23, &umr_bitfield_default },
	 { "WR_LIMIT_HI", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMMEA1_DRAM_RD_PRI_AGE[] = {
	 { "GROUP0_AGING_RATE", 0, 2, &umr_bitfield_default },
	 { "GROUP1_AGING_RATE", 3, 5, &umr_bitfield_default },
	 { "GROUP2_AGING_RATE", 6, 8, &umr_bitfield_default },
	 { "GROUP3_AGING_RATE", 9, 11, &umr_bitfield_default },
	 { "GROUP0_AGE_COEFFICIENT", 12, 14, &umr_bitfield_default },
	 { "GROUP1_AGE_COEFFICIENT", 15, 17, &umr_bitfield_default },
	 { "GROUP2_AGE_COEFFICIENT", 18, 20, &umr_bitfield_default },
	 { "GROUP3_AGE_COEFFICIENT", 21, 23, &umr_bitfield_default },
};
static struct umr_bitfield mmMMEA1_DRAM_WR_PRI_AGE[] = {
	 { "GROUP0_AGING_RATE", 0, 2, &umr_bitfield_default },
	 { "GROUP1_AGING_RATE", 3, 5, &umr_bitfield_default },
	 { "GROUP2_AGING_RATE", 6, 8, &umr_bitfield_default },
	 { "GROUP3_AGING_RATE", 9, 11, &umr_bitfield_default },
	 { "GROUP0_AGE_COEFFICIENT", 12, 14, &umr_bitfield_default },
	 { "GROUP1_AGE_COEFFICIENT", 15, 17, &umr_bitfield_default },
	 { "GROUP2_AGE_COEFFICIENT", 18, 20, &umr_bitfield_default },
	 { "GROUP3_AGE_COEFFICIENT", 21, 23, &umr_bitfield_default },
};
static struct umr_bitfield mmMMEA1_DRAM_RD_PRI_QUEUING[] = {
	 { "GROUP0_QUEUING_COEFFICIENT", 0, 2, &umr_bitfield_default },
	 { "GROUP1_QUEUING_COEFFICIENT", 3, 5, &umr_bitfield_default },
	 { "GROUP2_QUEUING_COEFFICIENT", 6, 8, &umr_bitfield_default },
	 { "GROUP3_QUEUING_COEFFICIENT", 9, 11, &umr_bitfield_default },
};
static struct umr_bitfield mmMMEA1_DRAM_WR_PRI_QUEUING[] = {
	 { "GROUP0_QUEUING_COEFFICIENT", 0, 2, &umr_bitfield_default },
	 { "GROUP1_QUEUING_COEFFICIENT", 3, 5, &umr_bitfield_default },
	 { "GROUP2_QUEUING_COEFFICIENT", 6, 8, &umr_bitfield_default },
	 { "GROUP3_QUEUING_COEFFICIENT", 9, 11, &umr_bitfield_default },
};
static struct umr_bitfield mmMMEA1_DRAM_RD_PRI_FIXED[] = {
	 { "GROUP0_FIXED_COEFFICIENT", 0, 2, &umr_bitfield_default },
	 { "GROUP1_FIXED_COEFFICIENT", 3, 5, &umr_bitfield_default },
	 { "GROUP2_FIXED_COEFFICIENT", 6, 8, &umr_bitfield_default },
	 { "GROUP3_FIXED_COEFFICIENT", 9, 11, &umr_bitfield_default },
};
static struct umr_bitfield mmMMEA1_DRAM_WR_PRI_FIXED[] = {
	 { "GROUP0_FIXED_COEFFICIENT", 0, 2, &umr_bitfield_default },
	 { "GROUP1_FIXED_COEFFICIENT", 3, 5, &umr_bitfield_default },
	 { "GROUP2_FIXED_COEFFICIENT", 6, 8, &umr_bitfield_default },
	 { "GROUP3_FIXED_COEFFICIENT", 9, 11, &umr_bitfield_default },
};
static struct umr_bitfield mmMMEA1_DRAM_RD_PRI_URGENCY[] = {
	 { "GROUP0_URGENCY_COEFFICIENT", 0, 2, &umr_bitfield_default },
	 { "GROUP1_URGENCY_COEFFICIENT", 3, 5, &umr_bitfield_default },
	 { "GROUP2_URGENCY_COEFFICIENT", 6, 8, &umr_bitfield_default },
	 { "GROUP3_URGENCY_COEFFICIENT", 9, 11, &umr_bitfield_default },
	 { "GROUP0_URGENCY_MODE", 12, 12, &umr_bitfield_default },
	 { "GROUP1_URGENCY_MODE", 13, 13, &umr_bitfield_default },
	 { "GROUP2_URGENCY_MODE", 14, 14, &umr_bitfield_default },
	 { "GROUP3_URGENCY_MODE", 15, 15, &umr_bitfield_default },
};
static struct umr_bitfield mmMMEA1_DRAM_WR_PRI_URGENCY[] = {
	 { "GROUP0_URGENCY_COEFFICIENT", 0, 2, &umr_bitfield_default },
	 { "GROUP1_URGENCY_COEFFICIENT", 3, 5, &umr_bitfield_default },
	 { "GROUP2_URGENCY_COEFFICIENT", 6, 8, &umr_bitfield_default },
	 { "GROUP3_URGENCY_COEFFICIENT", 9, 11, &umr_bitfield_default },
	 { "GROUP0_URGENCY_MODE", 12, 12, &umr_bitfield_default },
	 { "GROUP1_URGENCY_MODE", 13, 13, &umr_bitfield_default },
	 { "GROUP2_URGENCY_MODE", 14, 14, &umr_bitfield_default },
	 { "GROUP3_URGENCY_MODE", 15, 15, &umr_bitfield_default },
};
static struct umr_bitfield mmMMEA1_DRAM_RD_PRI_QUANT_PRI1[] = {
	 { "GROUP0_THRESHOLD", 0, 7, &umr_bitfield_default },
	 { "GROUP1_THRESHOLD", 8, 15, &umr_bitfield_default },
	 { "GROUP2_THRESHOLD", 16, 23, &umr_bitfield_default },
	 { "GROUP3_THRESHOLD", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMMEA1_DRAM_RD_PRI_QUANT_PRI2[] = {
	 { "GROUP0_THRESHOLD", 0, 7, &umr_bitfield_default },
	 { "GROUP1_THRESHOLD", 8, 15, &umr_bitfield_default },
	 { "GROUP2_THRESHOLD", 16, 23, &umr_bitfield_default },
	 { "GROUP3_THRESHOLD", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMMEA1_DRAM_RD_PRI_QUANT_PRI3[] = {
	 { "GROUP0_THRESHOLD", 0, 7, &umr_bitfield_default },
	 { "GROUP1_THRESHOLD", 8, 15, &umr_bitfield_default },
	 { "GROUP2_THRESHOLD", 16, 23, &umr_bitfield_default },
	 { "GROUP3_THRESHOLD", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMMEA1_DRAM_WR_PRI_QUANT_PRI1[] = {
	 { "GROUP0_THRESHOLD", 0, 7, &umr_bitfield_default },
	 { "GROUP1_THRESHOLD", 8, 15, &umr_bitfield_default },
	 { "GROUP2_THRESHOLD", 16, 23, &umr_bitfield_default },
	 { "GROUP3_THRESHOLD", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMMEA1_DRAM_WR_PRI_QUANT_PRI2[] = {
	 { "GROUP0_THRESHOLD", 0, 7, &umr_bitfield_default },
	 { "GROUP1_THRESHOLD", 8, 15, &umr_bitfield_default },
	 { "GROUP2_THRESHOLD", 16, 23, &umr_bitfield_default },
	 { "GROUP3_THRESHOLD", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMMEA1_DRAM_WR_PRI_QUANT_PRI3[] = {
	 { "GROUP0_THRESHOLD", 0, 7, &umr_bitfield_default },
	 { "GROUP1_THRESHOLD", 8, 15, &umr_bitfield_default },
	 { "GROUP2_THRESHOLD", 16, 23, &umr_bitfield_default },
	 { "GROUP3_THRESHOLD", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMMEA1_ADDRNORM_BASE_ADDR0[] = {
	 { "ADDR_RNG_VAL", 0, 0, &umr_bitfield_default },
	 { "LGCY_MMIO_HOLE_EN", 1, 1, &umr_bitfield_default },
	 { "INTLV_NUM_CHAN", 4, 7, &umr_bitfield_default },
	 { "INTLV_ADDR_SEL", 8, 10, &umr_bitfield_default },
	 { "BASE_ADDR", 12, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMMEA1_ADDRNORM_LIMIT_ADDR0[] = {
	 { "DST_FABRIC_ID", 0, 3, &umr_bitfield_default },
	 { "INTLV_NUM_SOCKETS", 8, 8, &umr_bitfield_default },
	 { "INTLV_NUM_DIES", 10, 11, &umr_bitfield_default },
	 { "LIMIT_ADDR", 12, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMMEA1_ADDRNORM_BASE_ADDR1[] = {
	 { "ADDR_RNG_VAL", 0, 0, &umr_bitfield_default },
	 { "LGCY_MMIO_HOLE_EN", 1, 1, &umr_bitfield_default },
	 { "INTLV_NUM_CHAN", 4, 7, &umr_bitfield_default },
	 { "INTLV_ADDR_SEL", 8, 10, &umr_bitfield_default },
	 { "BASE_ADDR", 12, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMMEA1_ADDRNORM_LIMIT_ADDR1[] = {
	 { "DST_FABRIC_ID", 0, 3, &umr_bitfield_default },
	 { "INTLV_NUM_SOCKETS", 8, 8, &umr_bitfield_default },
	 { "INTLV_NUM_DIES", 10, 11, &umr_bitfield_default },
	 { "LIMIT_ADDR", 12, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMMEA1_ADDRNORM_OFFSET_ADDR1[] = {
	 { "HI_ADDR_OFFSET_EN", 0, 0, &umr_bitfield_default },
	 { "HI_ADDR_OFFSET", 20, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMMEA1_ADDRNORM_HOLE_CNTL[] = {
	 { "DRAM_HOLE_VALID", 0, 0, &umr_bitfield_default },
	 { "DRAM_HOLE_OFFSET", 7, 15, &umr_bitfield_default },
};
static struct umr_bitfield mmMMEA1_ADDRDEC_BANK_CFG[] = {
	 { "BANK_MASK_DRAM", 0, 4, &umr_bitfield_default },
	 { "BANK_MASK_GMI", 5, 9, &umr_bitfield_default },
	 { "BANKGROUP_SEL_DRAM", 10, 12, &umr_bitfield_default },
	 { "BANKGROUP_SEL_GMI", 13, 15, &umr_bitfield_default },
	 { "BANKGROUP_INTERLEAVE_DRAM", 16, 16, &umr_bitfield_default },
	 { "BANKGROUP_INTERLEAVE_GMI", 17, 17, &umr_bitfield_default },
};
static struct umr_bitfield mmMMEA1_ADDRDEC_MISC_CFG[] = {
	 { "VCM_EN0", 0, 0, &umr_bitfield_default },
	 { "VCM_EN1", 1, 1, &umr_bitfield_default },
	 { "VCM_EN2", 2, 2, &umr_bitfield_default },
	 { "VCM_EN3", 3, 3, &umr_bitfield_default },
	 { "VCM_EN4", 4, 4, &umr_bitfield_default },
	 { "PCH_MASK_DRAM", 8, 8, &umr_bitfield_default },
	 { "PCH_MASK_GMI", 9, 9, &umr_bitfield_default },
	 { "CH_MASK_DRAM", 12, 15, &umr_bitfield_default },
	 { "CH_MASK_GMI", 16, 19, &umr_bitfield_default },
	 { "CS_MASK_DRAM", 20, 21, &umr_bitfield_default },
	 { "CS_MASK_GMI", 22, 23, &umr_bitfield_default },
	 { "RM_MASK_DRAM", 24, 26, &umr_bitfield_default },
	 { "RM_MASK_GMI", 27, 29, &umr_bitfield_default },
};
static struct umr_bitfield mmMMEA1_ADDRDECDRAM_ADDR_HASH_BANK0[] = {
	 { "XOR_ENABLE", 0, 0, &umr_bitfield_default },
	 { "COL_XOR", 1, 13, &umr_bitfield_default },
	 { "ROW_XOR", 14, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMMEA1_ADDRDECDRAM_ADDR_HASH_BANK1[] = {
	 { "XOR_ENABLE", 0, 0, &umr_bitfield_default },
	 { "COL_XOR", 1, 13, &umr_bitfield_default },
	 { "ROW_XOR", 14, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMMEA1_ADDRDECDRAM_ADDR_HASH_BANK2[] = {
	 { "XOR_ENABLE", 0, 0, &umr_bitfield_default },
	 { "COL_XOR", 1, 13, &umr_bitfield_default },
	 { "ROW_XOR", 14, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMMEA1_ADDRDECDRAM_ADDR_HASH_BANK3[] = {
	 { "XOR_ENABLE", 0, 0, &umr_bitfield_default },
	 { "COL_XOR", 1, 13, &umr_bitfield_default },
	 { "ROW_XOR", 14, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMMEA1_ADDRDECDRAM_ADDR_HASH_BANK4[] = {
	 { "XOR_ENABLE", 0, 0, &umr_bitfield_default },
	 { "COL_XOR", 1, 13, &umr_bitfield_default },
	 { "ROW_XOR", 14, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMMEA1_ADDRDECDRAM_ADDR_HASH_PC[] = {
	 { "XOR_ENABLE", 0, 0, &umr_bitfield_default },
	 { "COL_XOR", 1, 13, &umr_bitfield_default },
	 { "ROW_XOR", 14, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMMEA1_ADDRDECDRAM_ADDR_HASH_PC2[] = {
	 { "BANK_XOR", 0, 4, &umr_bitfield_default },
};
static struct umr_bitfield mmMMEA1_ADDRDECDRAM_ADDR_HASH_CS0[] = {
	 { "XOR_ENABLE", 0, 0, &umr_bitfield_default },
	 { "NA_XOR", 1, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMMEA1_ADDRDECDRAM_ADDR_HASH_CS1[] = {
	 { "XOR_ENABLE", 0, 0, &umr_bitfield_default },
	 { "NA_XOR", 1, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMMEA1_ADDRDECDRAM_HARVEST_ENABLE[] = {
	 { "FORCE_B3_EN", 0, 0, &umr_bitfield_default },
	 { "FORCE_B3_VAL", 1, 1, &umr_bitfield_default },
	 { "FORCE_B4_EN", 2, 2, &umr_bitfield_default },
	 { "FORCE_B4_VAL", 3, 3, &umr_bitfield_default },
};
static struct umr_bitfield mmMMEA1_ADDRDEC0_BASE_ADDR_CS0[] = {
	 { "CS_ENABLE", 0, 0, &umr_bitfield_default },
	 { "BASE_ADDR", 1, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMMEA1_ADDRDEC0_BASE_ADDR_CS1[] = {
	 { "CS_ENABLE", 0, 0, &umr_bitfield_default },
	 { "BASE_ADDR", 1, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMMEA1_ADDRDEC0_BASE_ADDR_CS2[] = {
	 { "CS_ENABLE", 0, 0, &umr_bitfield_default },
	 { "BASE_ADDR", 1, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMMEA1_ADDRDEC0_BASE_ADDR_CS3[] = {
	 { "CS_ENABLE", 0, 0, &umr_bitfield_default },
	 { "BASE_ADDR", 1, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMMEA1_ADDRDEC0_BASE_ADDR_SECCS0[] = {
	 { "CS_ENABLE", 0, 0, &umr_bitfield_default },
	 { "BASE_ADDR", 1, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMMEA1_ADDRDEC0_BASE_ADDR_SECCS1[] = {
	 { "CS_ENABLE", 0, 0, &umr_bitfield_default },
	 { "BASE_ADDR", 1, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMMEA1_ADDRDEC0_BASE_ADDR_SECCS2[] = {
	 { "CS_ENABLE", 0, 0, &umr_bitfield_default },
	 { "BASE_ADDR", 1, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMMEA1_ADDRDEC0_BASE_ADDR_SECCS3[] = {
	 { "CS_ENABLE", 0, 0, &umr_bitfield_default },
	 { "BASE_ADDR", 1, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMMEA1_ADDRDEC0_ADDR_MASK_CS01[] = {
	 { "ADDR_MASK", 1, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMMEA1_ADDRDEC0_ADDR_MASK_CS23[] = {
	 { "ADDR_MASK", 1, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMMEA1_ADDRDEC0_ADDR_MASK_SECCS01[] = {
	 { "ADDR_MASK", 1, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMMEA1_ADDRDEC0_ADDR_MASK_SECCS23[] = {
	 { "ADDR_MASK", 1, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMMEA1_ADDRDEC0_ADDR_CFG_CS01[] = {
	 { "NUM_BANK_GROUPS", 2, 3, &umr_bitfield_default },
	 { "NUM_RM", 4, 5, &umr_bitfield_default },
	 { "NUM_ROW_LO", 8, 11, &umr_bitfield_default },
	 { "NUM_ROW_HI", 12, 15, &umr_bitfield_default },
	 { "NUM_COL", 16, 19, &umr_bitfield_default },
	 { "NUM_BANKS", 20, 21, &umr_bitfield_default },
};
static struct umr_bitfield mmMMEA1_ADDRDEC0_ADDR_CFG_CS23[] = {
	 { "NUM_BANK_GROUPS", 2, 3, &umr_bitfield_default },
	 { "NUM_RM", 4, 5, &umr_bitfield_default },
	 { "NUM_ROW_LO", 8, 11, &umr_bitfield_default },
	 { "NUM_ROW_HI", 12, 15, &umr_bitfield_default },
	 { "NUM_COL", 16, 19, &umr_bitfield_default },
	 { "NUM_BANKS", 20, 21, &umr_bitfield_default },
};
static struct umr_bitfield mmMMEA1_ADDRDEC0_ADDR_SEL_CS01[] = {
	 { "BANK0", 0, 3, &umr_bitfield_default },
	 { "BANK1", 4, 7, &umr_bitfield_default },
	 { "BANK2", 8, 11, &umr_bitfield_default },
	 { "BANK3", 12, 15, &umr_bitfield_default },
	 { "BANK4", 16, 19, &umr_bitfield_default },
	 { "ROW_LO", 24, 27, &umr_bitfield_default },
	 { "ROW_HI", 28, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMMEA1_ADDRDEC0_ADDR_SEL_CS23[] = {
	 { "BANK0", 0, 3, &umr_bitfield_default },
	 { "BANK1", 4, 7, &umr_bitfield_default },
	 { "BANK2", 8, 11, &umr_bitfield_default },
	 { "BANK3", 12, 15, &umr_bitfield_default },
	 { "BANK4", 16, 19, &umr_bitfield_default },
	 { "ROW_LO", 24, 27, &umr_bitfield_default },
	 { "ROW_HI", 28, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMMEA1_ADDRDEC0_COL_SEL_LO_CS01[] = {
	 { "COL0", 0, 3, &umr_bitfield_default },
	 { "COL1", 4, 7, &umr_bitfield_default },
	 { "COL2", 8, 11, &umr_bitfield_default },
	 { "COL3", 12, 15, &umr_bitfield_default },
	 { "COL4", 16, 19, &umr_bitfield_default },
	 { "COL5", 20, 23, &umr_bitfield_default },
	 { "COL6", 24, 27, &umr_bitfield_default },
	 { "COL7", 28, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMMEA1_ADDRDEC0_COL_SEL_LO_CS23[] = {
	 { "COL0", 0, 3, &umr_bitfield_default },
	 { "COL1", 4, 7, &umr_bitfield_default },
	 { "COL2", 8, 11, &umr_bitfield_default },
	 { "COL3", 12, 15, &umr_bitfield_default },
	 { "COL4", 16, 19, &umr_bitfield_default },
	 { "COL5", 20, 23, &umr_bitfield_default },
	 { "COL6", 24, 27, &umr_bitfield_default },
	 { "COL7", 28, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMMEA1_ADDRDEC0_COL_SEL_HI_CS01[] = {
	 { "COL8", 0, 3, &umr_bitfield_default },
	 { "COL9", 4, 7, &umr_bitfield_default },
	 { "COL10", 8, 11, &umr_bitfield_default },
	 { "COL11", 12, 15, &umr_bitfield_default },
	 { "COL12", 16, 19, &umr_bitfield_default },
	 { "COL13", 20, 23, &umr_bitfield_default },
	 { "COL14", 24, 27, &umr_bitfield_default },
	 { "COL15", 28, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMMEA1_ADDRDEC0_COL_SEL_HI_CS23[] = {
	 { "COL8", 0, 3, &umr_bitfield_default },
	 { "COL9", 4, 7, &umr_bitfield_default },
	 { "COL10", 8, 11, &umr_bitfield_default },
	 { "COL11", 12, 15, &umr_bitfield_default },
	 { "COL12", 16, 19, &umr_bitfield_default },
	 { "COL13", 20, 23, &umr_bitfield_default },
	 { "COL14", 24, 27, &umr_bitfield_default },
	 { "COL15", 28, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMMEA1_ADDRDEC0_RM_SEL_CS01[] = {
	 { "RM0", 0, 3, &umr_bitfield_default },
	 { "RM1", 4, 7, &umr_bitfield_default },
	 { "RM2", 8, 11, &umr_bitfield_default },
	 { "CHAN_BIT", 12, 15, &umr_bitfield_default },
	 { "INVERT_ROW_MSBS_EVEN", 16, 17, &umr_bitfield_default },
	 { "INVERT_ROW_MSBS_ODD", 18, 19, &umr_bitfield_default },
};
static struct umr_bitfield mmMMEA1_ADDRDEC0_RM_SEL_CS23[] = {
	 { "RM0", 0, 3, &umr_bitfield_default },
	 { "RM1", 4, 7, &umr_bitfield_default },
	 { "RM2", 8, 11, &umr_bitfield_default },
	 { "CHAN_BIT", 12, 15, &umr_bitfield_default },
	 { "INVERT_ROW_MSBS_EVEN", 16, 17, &umr_bitfield_default },
	 { "INVERT_ROW_MSBS_ODD", 18, 19, &umr_bitfield_default },
};
static struct umr_bitfield mmMMEA1_ADDRDEC0_RM_SEL_SECCS01[] = {
	 { "RM0", 0, 3, &umr_bitfield_default },
	 { "RM1", 4, 7, &umr_bitfield_default },
	 { "RM2", 8, 11, &umr_bitfield_default },
	 { "CHAN_BIT", 12, 15, &umr_bitfield_default },
	 { "INVERT_ROW_MSBS_EVEN", 16, 17, &umr_bitfield_default },
	 { "INVERT_ROW_MSBS_ODD", 18, 19, &umr_bitfield_default },
};
static struct umr_bitfield mmMMEA1_ADDRDEC0_RM_SEL_SECCS23[] = {
	 { "RM0", 0, 3, &umr_bitfield_default },
	 { "RM1", 4, 7, &umr_bitfield_default },
	 { "RM2", 8, 11, &umr_bitfield_default },
	 { "CHAN_BIT", 12, 15, &umr_bitfield_default },
	 { "INVERT_ROW_MSBS_EVEN", 16, 17, &umr_bitfield_default },
	 { "INVERT_ROW_MSBS_ODD", 18, 19, &umr_bitfield_default },
};
static struct umr_bitfield mmMMEA1_ADDRDEC1_BASE_ADDR_CS0[] = {
	 { "CS_ENABLE", 0, 0, &umr_bitfield_default },
	 { "BASE_ADDR", 1, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMMEA1_ADDRDEC1_BASE_ADDR_CS1[] = {
	 { "CS_ENABLE", 0, 0, &umr_bitfield_default },
	 { "BASE_ADDR", 1, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMMEA1_ADDRDEC1_BASE_ADDR_CS2[] = {
	 { "CS_ENABLE", 0, 0, &umr_bitfield_default },
	 { "BASE_ADDR", 1, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMMEA1_ADDRDEC1_BASE_ADDR_CS3[] = {
	 { "CS_ENABLE", 0, 0, &umr_bitfield_default },
	 { "BASE_ADDR", 1, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMMEA1_ADDRDEC1_BASE_ADDR_SECCS0[] = {
	 { "CS_ENABLE", 0, 0, &umr_bitfield_default },
	 { "BASE_ADDR", 1, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMMEA1_ADDRDEC1_BASE_ADDR_SECCS1[] = {
	 { "CS_ENABLE", 0, 0, &umr_bitfield_default },
	 { "BASE_ADDR", 1, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMMEA1_ADDRDEC1_BASE_ADDR_SECCS2[] = {
	 { "CS_ENABLE", 0, 0, &umr_bitfield_default },
	 { "BASE_ADDR", 1, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMMEA1_ADDRDEC1_BASE_ADDR_SECCS3[] = {
	 { "CS_ENABLE", 0, 0, &umr_bitfield_default },
	 { "BASE_ADDR", 1, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMMEA1_ADDRDEC1_ADDR_MASK_CS01[] = {
	 { "ADDR_MASK", 1, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMMEA1_ADDRDEC1_ADDR_MASK_CS23[] = {
	 { "ADDR_MASK", 1, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMMEA1_ADDRDEC1_ADDR_MASK_SECCS01[] = {
	 { "ADDR_MASK", 1, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMMEA1_ADDRDEC1_ADDR_MASK_SECCS23[] = {
	 { "ADDR_MASK", 1, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMMEA1_ADDRDEC1_ADDR_CFG_CS01[] = {
	 { "NUM_BANK_GROUPS", 2, 3, &umr_bitfield_default },
	 { "NUM_RM", 4, 5, &umr_bitfield_default },
	 { "NUM_ROW_LO", 8, 11, &umr_bitfield_default },
	 { "NUM_ROW_HI", 12, 15, &umr_bitfield_default },
	 { "NUM_COL", 16, 19, &umr_bitfield_default },
	 { "NUM_BANKS", 20, 21, &umr_bitfield_default },
};
static struct umr_bitfield mmMMEA1_ADDRDEC1_ADDR_CFG_CS23[] = {
	 { "NUM_BANK_GROUPS", 2, 3, &umr_bitfield_default },
	 { "NUM_RM", 4, 5, &umr_bitfield_default },
	 { "NUM_ROW_LO", 8, 11, &umr_bitfield_default },
	 { "NUM_ROW_HI", 12, 15, &umr_bitfield_default },
	 { "NUM_COL", 16, 19, &umr_bitfield_default },
	 { "NUM_BANKS", 20, 21, &umr_bitfield_default },
};
static struct umr_bitfield mmMMEA1_ADDRDEC1_ADDR_SEL_CS01[] = {
	 { "BANK0", 0, 3, &umr_bitfield_default },
	 { "BANK1", 4, 7, &umr_bitfield_default },
	 { "BANK2", 8, 11, &umr_bitfield_default },
	 { "BANK3", 12, 15, &umr_bitfield_default },
	 { "BANK4", 16, 19, &umr_bitfield_default },
	 { "ROW_LO", 24, 27, &umr_bitfield_default },
	 { "ROW_HI", 28, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMMEA1_ADDRDEC1_ADDR_SEL_CS23[] = {
	 { "BANK0", 0, 3, &umr_bitfield_default },
	 { "BANK1", 4, 7, &umr_bitfield_default },
	 { "BANK2", 8, 11, &umr_bitfield_default },
	 { "BANK3", 12, 15, &umr_bitfield_default },
	 { "BANK4", 16, 19, &umr_bitfield_default },
	 { "ROW_LO", 24, 27, &umr_bitfield_default },
	 { "ROW_HI", 28, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMMEA1_ADDRDEC1_COL_SEL_LO_CS01[] = {
	 { "COL0", 0, 3, &umr_bitfield_default },
	 { "COL1", 4, 7, &umr_bitfield_default },
	 { "COL2", 8, 11, &umr_bitfield_default },
	 { "COL3", 12, 15, &umr_bitfield_default },
	 { "COL4", 16, 19, &umr_bitfield_default },
	 { "COL5", 20, 23, &umr_bitfield_default },
	 { "COL6", 24, 27, &umr_bitfield_default },
	 { "COL7", 28, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMMEA1_ADDRDEC1_COL_SEL_LO_CS23[] = {
	 { "COL0", 0, 3, &umr_bitfield_default },
	 { "COL1", 4, 7, &umr_bitfield_default },
	 { "COL2", 8, 11, &umr_bitfield_default },
	 { "COL3", 12, 15, &umr_bitfield_default },
	 { "COL4", 16, 19, &umr_bitfield_default },
	 { "COL5", 20, 23, &umr_bitfield_default },
	 { "COL6", 24, 27, &umr_bitfield_default },
	 { "COL7", 28, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMMEA1_ADDRDEC1_COL_SEL_HI_CS01[] = {
	 { "COL8", 0, 3, &umr_bitfield_default },
	 { "COL9", 4, 7, &umr_bitfield_default },
	 { "COL10", 8, 11, &umr_bitfield_default },
	 { "COL11", 12, 15, &umr_bitfield_default },
	 { "COL12", 16, 19, &umr_bitfield_default },
	 { "COL13", 20, 23, &umr_bitfield_default },
	 { "COL14", 24, 27, &umr_bitfield_default },
	 { "COL15", 28, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMMEA1_ADDRDEC1_COL_SEL_HI_CS23[] = {
	 { "COL8", 0, 3, &umr_bitfield_default },
	 { "COL9", 4, 7, &umr_bitfield_default },
	 { "COL10", 8, 11, &umr_bitfield_default },
	 { "COL11", 12, 15, &umr_bitfield_default },
	 { "COL12", 16, 19, &umr_bitfield_default },
	 { "COL13", 20, 23, &umr_bitfield_default },
	 { "COL14", 24, 27, &umr_bitfield_default },
	 { "COL15", 28, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMMEA1_ADDRDEC1_RM_SEL_CS01[] = {
	 { "RM0", 0, 3, &umr_bitfield_default },
	 { "RM1", 4, 7, &umr_bitfield_default },
	 { "RM2", 8, 11, &umr_bitfield_default },
	 { "CHAN_BIT", 12, 15, &umr_bitfield_default },
	 { "INVERT_ROW_MSBS_EVEN", 16, 17, &umr_bitfield_default },
	 { "INVERT_ROW_MSBS_ODD", 18, 19, &umr_bitfield_default },
};
static struct umr_bitfield mmMMEA1_ADDRDEC1_RM_SEL_CS23[] = {
	 { "RM0", 0, 3, &umr_bitfield_default },
	 { "RM1", 4, 7, &umr_bitfield_default },
	 { "RM2", 8, 11, &umr_bitfield_default },
	 { "CHAN_BIT", 12, 15, &umr_bitfield_default },
	 { "INVERT_ROW_MSBS_EVEN", 16, 17, &umr_bitfield_default },
	 { "INVERT_ROW_MSBS_ODD", 18, 19, &umr_bitfield_default },
};
static struct umr_bitfield mmMMEA1_ADDRDEC1_RM_SEL_SECCS01[] = {
	 { "RM0", 0, 3, &umr_bitfield_default },
	 { "RM1", 4, 7, &umr_bitfield_default },
	 { "RM2", 8, 11, &umr_bitfield_default },
	 { "CHAN_BIT", 12, 15, &umr_bitfield_default },
	 { "INVERT_ROW_MSBS_EVEN", 16, 17, &umr_bitfield_default },
	 { "INVERT_ROW_MSBS_ODD", 18, 19, &umr_bitfield_default },
};
static struct umr_bitfield mmMMEA1_ADDRDEC1_RM_SEL_SECCS23[] = {
	 { "RM0", 0, 3, &umr_bitfield_default },
	 { "RM1", 4, 7, &umr_bitfield_default },
	 { "RM2", 8, 11, &umr_bitfield_default },
	 { "CHAN_BIT", 12, 15, &umr_bitfield_default },
	 { "INVERT_ROW_MSBS_EVEN", 16, 17, &umr_bitfield_default },
	 { "INVERT_ROW_MSBS_ODD", 18, 19, &umr_bitfield_default },
};
static struct umr_bitfield mmMMEA1_IO_RD_CLI2GRP_MAP0[] = {
	 { "CID0_GROUP", 0, 1, &umr_bitfield_default },
	 { "CID1_GROUP", 2, 3, &umr_bitfield_default },
	 { "CID2_GROUP", 4, 5, &umr_bitfield_default },
	 { "CID3_GROUP", 6, 7, &umr_bitfield_default },
	 { "CID4_GROUP", 8, 9, &umr_bitfield_default },
	 { "CID5_GROUP", 10, 11, &umr_bitfield_default },
	 { "CID6_GROUP", 12, 13, &umr_bitfield_default },
	 { "CID7_GROUP", 14, 15, &umr_bitfield_default },
	 { "CID8_GROUP", 16, 17, &umr_bitfield_default },
	 { "CID9_GROUP", 18, 19, &umr_bitfield_default },
	 { "CID10_GROUP", 20, 21, &umr_bitfield_default },
	 { "CID11_GROUP", 22, 23, &umr_bitfield_default },
	 { "CID12_GROUP", 24, 25, &umr_bitfield_default },
	 { "CID13_GROUP", 26, 27, &umr_bitfield_default },
	 { "CID14_GROUP", 28, 29, &umr_bitfield_default },
	 { "CID15_GROUP", 30, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMMEA1_IO_RD_CLI2GRP_MAP1[] = {
	 { "CID16_GROUP", 0, 1, &umr_bitfield_default },
	 { "CID17_GROUP", 2, 3, &umr_bitfield_default },
	 { "CID18_GROUP", 4, 5, &umr_bitfield_default },
	 { "CID19_GROUP", 6, 7, &umr_bitfield_default },
	 { "CID20_GROUP", 8, 9, &umr_bitfield_default },
	 { "CID21_GROUP", 10, 11, &umr_bitfield_default },
	 { "CID22_GROUP", 12, 13, &umr_bitfield_default },
	 { "CID23_GROUP", 14, 15, &umr_bitfield_default },
	 { "CID24_GROUP", 16, 17, &umr_bitfield_default },
	 { "CID25_GROUP", 18, 19, &umr_bitfield_default },
	 { "CID26_GROUP", 20, 21, &umr_bitfield_default },
	 { "CID27_GROUP", 22, 23, &umr_bitfield_default },
	 { "CID28_GROUP", 24, 25, &umr_bitfield_default },
	 { "CID29_GROUP", 26, 27, &umr_bitfield_default },
	 { "CID30_GROUP", 28, 29, &umr_bitfield_default },
	 { "CID31_GROUP", 30, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMMEA1_IO_WR_CLI2GRP_MAP0[] = {
	 { "CID0_GROUP", 0, 1, &umr_bitfield_default },
	 { "CID1_GROUP", 2, 3, &umr_bitfield_default },
	 { "CID2_GROUP", 4, 5, &umr_bitfield_default },
	 { "CID3_GROUP", 6, 7, &umr_bitfield_default },
	 { "CID4_GROUP", 8, 9, &umr_bitfield_default },
	 { "CID5_GROUP", 10, 11, &umr_bitfield_default },
	 { "CID6_GROUP", 12, 13, &umr_bitfield_default },
	 { "CID7_GROUP", 14, 15, &umr_bitfield_default },
	 { "CID8_GROUP", 16, 17, &umr_bitfield_default },
	 { "CID9_GROUP", 18, 19, &umr_bitfield_default },
	 { "CID10_GROUP", 20, 21, &umr_bitfield_default },
	 { "CID11_GROUP", 22, 23, &umr_bitfield_default },
	 { "CID12_GROUP", 24, 25, &umr_bitfield_default },
	 { "CID13_GROUP", 26, 27, &umr_bitfield_default },
	 { "CID14_GROUP", 28, 29, &umr_bitfield_default },
	 { "CID15_GROUP", 30, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMMEA1_IO_WR_CLI2GRP_MAP1[] = {
	 { "CID16_GROUP", 0, 1, &umr_bitfield_default },
	 { "CID17_GROUP", 2, 3, &umr_bitfield_default },
	 { "CID18_GROUP", 4, 5, &umr_bitfield_default },
	 { "CID19_GROUP", 6, 7, &umr_bitfield_default },
	 { "CID20_GROUP", 8, 9, &umr_bitfield_default },
	 { "CID21_GROUP", 10, 11, &umr_bitfield_default },
	 { "CID22_GROUP", 12, 13, &umr_bitfield_default },
	 { "CID23_GROUP", 14, 15, &umr_bitfield_default },
	 { "CID24_GROUP", 16, 17, &umr_bitfield_default },
	 { "CID25_GROUP", 18, 19, &umr_bitfield_default },
	 { "CID26_GROUP", 20, 21, &umr_bitfield_default },
	 { "CID27_GROUP", 22, 23, &umr_bitfield_default },
	 { "CID28_GROUP", 24, 25, &umr_bitfield_default },
	 { "CID29_GROUP", 26, 27, &umr_bitfield_default },
	 { "CID30_GROUP", 28, 29, &umr_bitfield_default },
	 { "CID31_GROUP", 30, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMMEA1_IO_RD_COMBINE_FLUSH[] = {
	 { "GROUP0_TIMER", 0, 3, &umr_bitfield_default },
	 { "GROUP1_TIMER", 4, 7, &umr_bitfield_default },
	 { "GROUP2_TIMER", 8, 11, &umr_bitfield_default },
	 { "GROUP3_TIMER", 12, 15, &umr_bitfield_default },
};
static struct umr_bitfield mmMMEA1_IO_WR_COMBINE_FLUSH[] = {
	 { "GROUP0_TIMER", 0, 3, &umr_bitfield_default },
	 { "GROUP1_TIMER", 4, 7, &umr_bitfield_default },
	 { "GROUP2_TIMER", 8, 11, &umr_bitfield_default },
	 { "GROUP3_TIMER", 12, 15, &umr_bitfield_default },
};
static struct umr_bitfield mmMMEA1_IO_GROUP_BURST[] = {
	 { "RD_LIMIT_LO", 0, 7, &umr_bitfield_default },
	 { "RD_LIMIT_HI", 8, 15, &umr_bitfield_default },
	 { "WR_LIMIT_LO", 16, 23, &umr_bitfield_default },
	 { "WR_LIMIT_HI", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMMEA1_IO_RD_PRI_AGE[] = {
	 { "GROUP0_AGING_RATE", 0, 2, &umr_bitfield_default },
	 { "GROUP1_AGING_RATE", 3, 5, &umr_bitfield_default },
	 { "GROUP2_AGING_RATE", 6, 8, &umr_bitfield_default },
	 { "GROUP3_AGING_RATE", 9, 11, &umr_bitfield_default },
	 { "GROUP0_AGE_COEFFICIENT", 12, 14, &umr_bitfield_default },
	 { "GROUP1_AGE_COEFFICIENT", 15, 17, &umr_bitfield_default },
	 { "GROUP2_AGE_COEFFICIENT", 18, 20, &umr_bitfield_default },
	 { "GROUP3_AGE_COEFFICIENT", 21, 23, &umr_bitfield_default },
};
static struct umr_bitfield mmMMEA1_IO_WR_PRI_AGE[] = {
	 { "GROUP0_AGING_RATE", 0, 2, &umr_bitfield_default },
	 { "GROUP1_AGING_RATE", 3, 5, &umr_bitfield_default },
	 { "GROUP2_AGING_RATE", 6, 8, &umr_bitfield_default },
	 { "GROUP3_AGING_RATE", 9, 11, &umr_bitfield_default },
	 { "GROUP0_AGE_COEFFICIENT", 12, 14, &umr_bitfield_default },
	 { "GROUP1_AGE_COEFFICIENT", 15, 17, &umr_bitfield_default },
	 { "GROUP2_AGE_COEFFICIENT", 18, 20, &umr_bitfield_default },
	 { "GROUP3_AGE_COEFFICIENT", 21, 23, &umr_bitfield_default },
};
static struct umr_bitfield mmMMEA1_IO_RD_PRI_QUEUING[] = {
	 { "GROUP0_QUEUING_COEFFICIENT", 0, 2, &umr_bitfield_default },
	 { "GROUP1_QUEUING_COEFFICIENT", 3, 5, &umr_bitfield_default },
	 { "GROUP2_QUEUING_COEFFICIENT", 6, 8, &umr_bitfield_default },
	 { "GROUP3_QUEUING_COEFFICIENT", 9, 11, &umr_bitfield_default },
};
static struct umr_bitfield mmMMEA1_IO_WR_PRI_QUEUING[] = {
	 { "GROUP0_QUEUING_COEFFICIENT", 0, 2, &umr_bitfield_default },
	 { "GROUP1_QUEUING_COEFFICIENT", 3, 5, &umr_bitfield_default },
	 { "GROUP2_QUEUING_COEFFICIENT", 6, 8, &umr_bitfield_default },
	 { "GROUP3_QUEUING_COEFFICIENT", 9, 11, &umr_bitfield_default },
};
static struct umr_bitfield mmMMEA1_IO_RD_PRI_FIXED[] = {
	 { "GROUP0_FIXED_COEFFICIENT", 0, 2, &umr_bitfield_default },
	 { "GROUP1_FIXED_COEFFICIENT", 3, 5, &umr_bitfield_default },
	 { "GROUP2_FIXED_COEFFICIENT", 6, 8, &umr_bitfield_default },
	 { "GROUP3_FIXED_COEFFICIENT", 9, 11, &umr_bitfield_default },
};
static struct umr_bitfield mmMMEA1_IO_WR_PRI_FIXED[] = {
	 { "GROUP0_FIXED_COEFFICIENT", 0, 2, &umr_bitfield_default },
	 { "GROUP1_FIXED_COEFFICIENT", 3, 5, &umr_bitfield_default },
	 { "GROUP2_FIXED_COEFFICIENT", 6, 8, &umr_bitfield_default },
	 { "GROUP3_FIXED_COEFFICIENT", 9, 11, &umr_bitfield_default },
};
static struct umr_bitfield mmMMEA1_IO_RD_PRI_URGENCY[] = {
	 { "GROUP0_URGENCY_COEFFICIENT", 0, 2, &umr_bitfield_default },
	 { "GROUP1_URGENCY_COEFFICIENT", 3, 5, &umr_bitfield_default },
	 { "GROUP2_URGENCY_COEFFICIENT", 6, 8, &umr_bitfield_default },
	 { "GROUP3_URGENCY_COEFFICIENT", 9, 11, &umr_bitfield_default },
	 { "GROUP0_URGENCY_MODE", 12, 12, &umr_bitfield_default },
	 { "GROUP1_URGENCY_MODE", 13, 13, &umr_bitfield_default },
	 { "GROUP2_URGENCY_MODE", 14, 14, &umr_bitfield_default },
	 { "GROUP3_URGENCY_MODE", 15, 15, &umr_bitfield_default },
};
static struct umr_bitfield mmMMEA1_IO_WR_PRI_URGENCY[] = {
	 { "GROUP0_URGENCY_COEFFICIENT", 0, 2, &umr_bitfield_default },
	 { "GROUP1_URGENCY_COEFFICIENT", 3, 5, &umr_bitfield_default },
	 { "GROUP2_URGENCY_COEFFICIENT", 6, 8, &umr_bitfield_default },
	 { "GROUP3_URGENCY_COEFFICIENT", 9, 11, &umr_bitfield_default },
	 { "GROUP0_URGENCY_MODE", 12, 12, &umr_bitfield_default },
	 { "GROUP1_URGENCY_MODE", 13, 13, &umr_bitfield_default },
	 { "GROUP2_URGENCY_MODE", 14, 14, &umr_bitfield_default },
	 { "GROUP3_URGENCY_MODE", 15, 15, &umr_bitfield_default },
};
static struct umr_bitfield mmMMEA1_IO_RD_PRI_URGENCY_MASK[] = {
	 { "CID0_MASK", 0, 0, &umr_bitfield_default },
	 { "CID1_MASK", 1, 1, &umr_bitfield_default },
	 { "CID2_MASK", 2, 2, &umr_bitfield_default },
	 { "CID3_MASK", 3, 3, &umr_bitfield_default },
	 { "CID4_MASK", 4, 4, &umr_bitfield_default },
	 { "CID5_MASK", 5, 5, &umr_bitfield_default },
	 { "CID6_MASK", 6, 6, &umr_bitfield_default },
	 { "CID7_MASK", 7, 7, &umr_bitfield_default },
	 { "CID8_MASK", 8, 8, &umr_bitfield_default },
	 { "CID9_MASK", 9, 9, &umr_bitfield_default },
	 { "CID10_MASK", 10, 10, &umr_bitfield_default },
	 { "CID11_MASK", 11, 11, &umr_bitfield_default },
	 { "CID12_MASK", 12, 12, &umr_bitfield_default },
	 { "CID13_MASK", 13, 13, &umr_bitfield_default },
	 { "CID14_MASK", 14, 14, &umr_bitfield_default },
	 { "CID15_MASK", 15, 15, &umr_bitfield_default },
	 { "CID16_MASK", 16, 16, &umr_bitfield_default },
	 { "CID17_MASK", 17, 17, &umr_bitfield_default },
	 { "CID18_MASK", 18, 18, &umr_bitfield_default },
	 { "CID19_MASK", 19, 19, &umr_bitfield_default },
	 { "CID20_MASK", 20, 20, &umr_bitfield_default },
	 { "CID21_MASK", 21, 21, &umr_bitfield_default },
	 { "CID22_MASK", 22, 22, &umr_bitfield_default },
	 { "CID23_MASK", 23, 23, &umr_bitfield_default },
	 { "CID24_MASK", 24, 24, &umr_bitfield_default },
	 { "CID25_MASK", 25, 25, &umr_bitfield_default },
	 { "CID26_MASK", 26, 26, &umr_bitfield_default },
	 { "CID27_MASK", 27, 27, &umr_bitfield_default },
	 { "CID28_MASK", 28, 28, &umr_bitfield_default },
	 { "CID29_MASK", 29, 29, &umr_bitfield_default },
	 { "CID30_MASK", 30, 30, &umr_bitfield_default },
	 { "CID31_MASK", 31, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMMEA1_IO_WR_PRI_URGENCY_MASK[] = {
	 { "CID0_MASK", 0, 0, &umr_bitfield_default },
	 { "CID1_MASK", 1, 1, &umr_bitfield_default },
	 { "CID2_MASK", 2, 2, &umr_bitfield_default },
	 { "CID3_MASK", 3, 3, &umr_bitfield_default },
	 { "CID4_MASK", 4, 4, &umr_bitfield_default },
	 { "CID5_MASK", 5, 5, &umr_bitfield_default },
	 { "CID6_MASK", 6, 6, &umr_bitfield_default },
	 { "CID7_MASK", 7, 7, &umr_bitfield_default },
	 { "CID8_MASK", 8, 8, &umr_bitfield_default },
	 { "CID9_MASK", 9, 9, &umr_bitfield_default },
	 { "CID10_MASK", 10, 10, &umr_bitfield_default },
	 { "CID11_MASK", 11, 11, &umr_bitfield_default },
	 { "CID12_MASK", 12, 12, &umr_bitfield_default },
	 { "CID13_MASK", 13, 13, &umr_bitfield_default },
	 { "CID14_MASK", 14, 14, &umr_bitfield_default },
	 { "CID15_MASK", 15, 15, &umr_bitfield_default },
	 { "CID16_MASK", 16, 16, &umr_bitfield_default },
	 { "CID17_MASK", 17, 17, &umr_bitfield_default },
	 { "CID18_MASK", 18, 18, &umr_bitfield_default },
	 { "CID19_MASK", 19, 19, &umr_bitfield_default },
	 { "CID20_MASK", 20, 20, &umr_bitfield_default },
	 { "CID21_MASK", 21, 21, &umr_bitfield_default },
	 { "CID22_MASK", 22, 22, &umr_bitfield_default },
	 { "CID23_MASK", 23, 23, &umr_bitfield_default },
	 { "CID24_MASK", 24, 24, &umr_bitfield_default },
	 { "CID25_MASK", 25, 25, &umr_bitfield_default },
	 { "CID26_MASK", 26, 26, &umr_bitfield_default },
	 { "CID27_MASK", 27, 27, &umr_bitfield_default },
	 { "CID28_MASK", 28, 28, &umr_bitfield_default },
	 { "CID29_MASK", 29, 29, &umr_bitfield_default },
	 { "CID30_MASK", 30, 30, &umr_bitfield_default },
	 { "CID31_MASK", 31, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMMEA1_IO_RD_PRI_QUANT_PRI1[] = {
	 { "GROUP0_THRESHOLD", 0, 7, &umr_bitfield_default },
	 { "GROUP1_THRESHOLD", 8, 15, &umr_bitfield_default },
	 { "GROUP2_THRESHOLD", 16, 23, &umr_bitfield_default },
	 { "GROUP3_THRESHOLD", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMMEA1_IO_RD_PRI_QUANT_PRI2[] = {
	 { "GROUP0_THRESHOLD", 0, 7, &umr_bitfield_default },
	 { "GROUP1_THRESHOLD", 8, 15, &umr_bitfield_default },
	 { "GROUP2_THRESHOLD", 16, 23, &umr_bitfield_default },
	 { "GROUP3_THRESHOLD", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMMEA1_IO_RD_PRI_QUANT_PRI3[] = {
	 { "GROUP0_THRESHOLD", 0, 7, &umr_bitfield_default },
	 { "GROUP1_THRESHOLD", 8, 15, &umr_bitfield_default },
	 { "GROUP2_THRESHOLD", 16, 23, &umr_bitfield_default },
	 { "GROUP3_THRESHOLD", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMMEA1_IO_WR_PRI_QUANT_PRI1[] = {
	 { "GROUP0_THRESHOLD", 0, 7, &umr_bitfield_default },
	 { "GROUP1_THRESHOLD", 8, 15, &umr_bitfield_default },
	 { "GROUP2_THRESHOLD", 16, 23, &umr_bitfield_default },
	 { "GROUP3_THRESHOLD", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMMEA1_IO_WR_PRI_QUANT_PRI2[] = {
	 { "GROUP0_THRESHOLD", 0, 7, &umr_bitfield_default },
	 { "GROUP1_THRESHOLD", 8, 15, &umr_bitfield_default },
	 { "GROUP2_THRESHOLD", 16, 23, &umr_bitfield_default },
	 { "GROUP3_THRESHOLD", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMMEA1_IO_WR_PRI_QUANT_PRI3[] = {
	 { "GROUP0_THRESHOLD", 0, 7, &umr_bitfield_default },
	 { "GROUP1_THRESHOLD", 8, 15, &umr_bitfield_default },
	 { "GROUP2_THRESHOLD", 16, 23, &umr_bitfield_default },
	 { "GROUP3_THRESHOLD", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMMEA1_SDP_ARB_DRAM[] = {
	 { "RDWR_BURST_LIMIT_CYCL", 0, 6, &umr_bitfield_default },
	 { "RDWR_BURST_LIMIT_DATA", 8, 14, &umr_bitfield_default },
	 { "EARLY_SW2RD_ON_PRI", 16, 16, &umr_bitfield_default },
	 { "EARLY_SW2WR_ON_PRI", 17, 17, &umr_bitfield_default },
	 { "EARLY_SW2RD_ON_RES", 18, 18, &umr_bitfield_default },
	 { "EARLY_SW2WR_ON_RES", 19, 19, &umr_bitfield_default },
	 { "EOB_ON_EXPIRE", 20, 20, &umr_bitfield_default },
};
static struct umr_bitfield mmMMEA1_SDP_ARB_FINAL[] = {
	 { "DRAM_BURST_LIMIT", 0, 4, &umr_bitfield_default },
	 { "GMI_BURST_LIMIT", 5, 9, &umr_bitfield_default },
	 { "IO_BURST_LIMIT", 10, 14, &umr_bitfield_default },
	 { "BURST_LIMIT_MULTIPLIER", 15, 16, &umr_bitfield_default },
	 { "RDONLY_VC0", 17, 17, &umr_bitfield_default },
	 { "RDONLY_VC1", 18, 18, &umr_bitfield_default },
	 { "RDONLY_VC2", 19, 19, &umr_bitfield_default },
	 { "RDONLY_VC3", 20, 20, &umr_bitfield_default },
	 { "RDONLY_VC4", 21, 21, &umr_bitfield_default },
	 { "RDONLY_VC5", 22, 22, &umr_bitfield_default },
	 { "RDONLY_VC6", 23, 23, &umr_bitfield_default },
	 { "RDONLY_VC7", 24, 24, &umr_bitfield_default },
	 { "ERREVENT_ON_ERROR", 25, 25, &umr_bitfield_default },
	 { "HALTREQ_ON_ERROR", 26, 26, &umr_bitfield_default },
};
static struct umr_bitfield mmMMEA1_SDP_DRAM_PRIORITY[] = {
	 { "RD_GROUP0_PRIORITY", 0, 3, &umr_bitfield_default },
	 { "RD_GROUP1_PRIORITY", 4, 7, &umr_bitfield_default },
	 { "RD_GROUP2_PRIORITY", 8, 11, &umr_bitfield_default },
	 { "RD_GROUP3_PRIORITY", 12, 15, &umr_bitfield_default },
	 { "WR_GROUP0_PRIORITY", 16, 19, &umr_bitfield_default },
	 { "WR_GROUP1_PRIORITY", 20, 23, &umr_bitfield_default },
	 { "WR_GROUP2_PRIORITY", 24, 27, &umr_bitfield_default },
	 { "WR_GROUP3_PRIORITY", 28, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMMEA1_SDP_IO_PRIORITY[] = {
	 { "RD_GROUP0_PRIORITY", 0, 3, &umr_bitfield_default },
	 { "RD_GROUP1_PRIORITY", 4, 7, &umr_bitfield_default },
	 { "RD_GROUP2_PRIORITY", 8, 11, &umr_bitfield_default },
	 { "RD_GROUP3_PRIORITY", 12, 15, &umr_bitfield_default },
	 { "WR_GROUP0_PRIORITY", 16, 19, &umr_bitfield_default },
	 { "WR_GROUP1_PRIORITY", 20, 23, &umr_bitfield_default },
	 { "WR_GROUP2_PRIORITY", 24, 27, &umr_bitfield_default },
	 { "WR_GROUP3_PRIORITY", 28, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMMEA1_SDP_CREDITS[] = {
	 { "TAG_LIMIT", 0, 7, &umr_bitfield_default },
	 { "WR_RESP_CREDITS", 8, 14, &umr_bitfield_default },
	 { "RD_RESP_CREDITS", 16, 22, &umr_bitfield_default },
};
static struct umr_bitfield mmMMEA1_SDP_TAG_RESERVE0[] = {
	 { "VC0", 0, 7, &umr_bitfield_default },
	 { "VC1", 8, 15, &umr_bitfield_default },
	 { "VC2", 16, 23, &umr_bitfield_default },
	 { "VC3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMMEA1_SDP_TAG_RESERVE1[] = {
	 { "VC4", 0, 7, &umr_bitfield_default },
	 { "VC5", 8, 15, &umr_bitfield_default },
	 { "VC6", 16, 23, &umr_bitfield_default },
	 { "VC7", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMMEA1_SDP_VCC_RESERVE0[] = {
	 { "VC0_CREDITS", 0, 5, &umr_bitfield_default },
	 { "VC1_CREDITS", 6, 11, &umr_bitfield_default },
	 { "VC2_CREDITS", 12, 17, &umr_bitfield_default },
	 { "VC3_CREDITS", 18, 23, &umr_bitfield_default },
	 { "VC4_CREDITS", 24, 29, &umr_bitfield_default },
};
static struct umr_bitfield mmMMEA1_SDP_VCC_RESERVE1[] = {
	 { "VC5_CREDITS", 0, 5, &umr_bitfield_default },
	 { "VC6_CREDITS", 6, 11, &umr_bitfield_default },
	 { "VC7_CREDITS", 12, 17, &umr_bitfield_default },
	 { "DISTRIBUTE_POOL", 31, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMMEA1_SDP_VCD_RESERVE0[] = {
	 { "VC0_CREDITS", 0, 5, &umr_bitfield_default },
	 { "VC1_CREDITS", 6, 11, &umr_bitfield_default },
	 { "VC2_CREDITS", 12, 17, &umr_bitfield_default },
	 { "VC3_CREDITS", 18, 23, &umr_bitfield_default },
	 { "VC4_CREDITS", 24, 29, &umr_bitfield_default },
};
static struct umr_bitfield mmMMEA1_SDP_VCD_RESERVE1[] = {
	 { "VC5_CREDITS", 0, 5, &umr_bitfield_default },
	 { "VC6_CREDITS", 6, 11, &umr_bitfield_default },
	 { "VC7_CREDITS", 12, 17, &umr_bitfield_default },
	 { "DISTRIBUTE_POOL", 31, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMMEA1_SDP_REQ_CNTL[] = {
	 { "REQ_PASS_PW_OVERRIDE_READ", 0, 0, &umr_bitfield_default },
	 { "REQ_PASS_PW_OVERRIDE_WRITE", 1, 1, &umr_bitfield_default },
	 { "REQ_PASS_PW_OVERRIDE_ATOMIC", 2, 2, &umr_bitfield_default },
	 { "REQ_CHAIN_OVERRIDE_DRAM", 3, 3, &umr_bitfield_default },
	 { "INNER_DOMAIN_MODE", 4, 4, &umr_bitfield_default },
};
static struct umr_bitfield mmMMEA1_MISC[] = {
	 { "RELATIVE_PRI_IN_DRAM_RD_ARB", 0, 0, &umr_bitfield_default },
	 { "RELATIVE_PRI_IN_DRAM_WR_ARB", 1, 1, &umr_bitfield_default },
	 { "RELATIVE_PRI_IN_GMI_RD_ARB", 2, 2, &umr_bitfield_default },
	 { "RELATIVE_PRI_IN_GMI_WR_ARB", 3, 3, &umr_bitfield_default },
	 { "RELATIVE_PRI_IN_IO_RD_ARB", 4, 4, &umr_bitfield_default },
	 { "RELATIVE_PRI_IN_IO_WR_ARB", 5, 5, &umr_bitfield_default },
	 { "RRET_SWAP_MODE", 6, 6, &umr_bitfield_default },
	 { "EARLY_SDP_ORIGDATA", 7, 7, &umr_bitfield_default },
	 { "LINKMGR_DYNAMIC_MODE", 8, 9, &umr_bitfield_default },
	 { "LINKMGR_HALT_THRESHOLD", 10, 11, &umr_bitfield_default },
	 { "LINKMGR_RECONNECT_DELAY", 12, 13, &umr_bitfield_default },
	 { "LINKMGR_IDLE_THRESHOLD", 14, 18, &umr_bitfield_default },
	 { "FAVOUR_MIDCHAIN_CS_IN_DRAM_ARB", 19, 19, &umr_bitfield_default },
	 { "FAVOUR_MIDCHAIN_CS_IN_GMI_ARB", 20, 20, &umr_bitfield_default },
	 { "FAVOUR_LAST_CS_IN_DRAM_ARB", 21, 21, &umr_bitfield_default },
	 { "FAVOUR_LAST_CS_IN_GMI_ARB", 22, 22, &umr_bitfield_default },
	 { "SWITCH_CS_ON_W2R_IN_DRAM_ARB", 23, 23, &umr_bitfield_default },
	 { "SWITCH_CS_ON_W2R_IN_GMI_ARB", 24, 24, &umr_bitfield_default },
};
static struct umr_bitfield mmMMEA1_LATENCY_SAMPLING[] = {
	 { "SAMPLER0_DRAM", 0, 0, &umr_bitfield_default },
	 { "SAMPLER1_DRAM", 1, 1, &umr_bitfield_default },
	 { "SAMPLER0_GMI", 2, 2, &umr_bitfield_default },
	 { "SAMPLER1_GMI", 3, 3, &umr_bitfield_default },
	 { "SAMPLER0_IO", 4, 4, &umr_bitfield_default },
	 { "SAMPLER1_IO", 5, 5, &umr_bitfield_default },
	 { "SAMPLER0_READ", 6, 6, &umr_bitfield_default },
	 { "SAMPLER1_READ", 7, 7, &umr_bitfield_default },
	 { "SAMPLER0_WRITE", 8, 8, &umr_bitfield_default },
	 { "SAMPLER1_WRITE", 9, 9, &umr_bitfield_default },
	 { "SAMPLER0_ATOMIC_RET", 10, 10, &umr_bitfield_default },
	 { "SAMPLER1_ATOMIC_RET", 11, 11, &umr_bitfield_default },
	 { "SAMPLER0_ATOMIC_NORET", 12, 12, &umr_bitfield_default },
	 { "SAMPLER1_ATOMIC_NORET", 13, 13, &umr_bitfield_default },
	 { "SAMPLER0_VC", 14, 21, &umr_bitfield_default },
	 { "SAMPLER1_VC", 22, 29, &umr_bitfield_default },
};
static struct umr_bitfield mmMMEA1_PERFCOUNTER_LO[] = {
	 { "COUNTER_LO", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMMEA1_PERFCOUNTER_HI[] = {
	 { "COUNTER_HI", 0, 15, &umr_bitfield_default },
	 { "COMPARE_VALUE", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMMEA1_PERFCOUNTER0_CFG[] = {
	 { "PERF_SEL", 0, 7, &umr_bitfield_default },
	 { "PERF_SEL_END", 8, 15, &umr_bitfield_default },
	 { "PERF_MODE", 24, 27, &umr_bitfield_default },
	 { "ENABLE", 28, 28, &umr_bitfield_default },
	 { "CLEAR", 29, 29, &umr_bitfield_default },
};
static struct umr_bitfield mmMMEA1_PERFCOUNTER1_CFG[] = {
	 { "PERF_SEL", 0, 7, &umr_bitfield_default },
	 { "PERF_SEL_END", 8, 15, &umr_bitfield_default },
	 { "PERF_MODE", 24, 27, &umr_bitfield_default },
	 { "ENABLE", 28, 28, &umr_bitfield_default },
	 { "CLEAR", 29, 29, &umr_bitfield_default },
};
static struct umr_bitfield mmMMEA1_PERFCOUNTER_RSLT_CNTL[] = {
	 { "PERF_COUNTER_SELECT", 0, 3, &umr_bitfield_default },
	 { "START_TRIGGER", 8, 15, &umr_bitfield_default },
	 { "STOP_TRIGGER", 16, 23, &umr_bitfield_default },
	 { "ENABLE_ANY", 24, 24, &umr_bitfield_default },
	 { "CLEAR_ALL", 25, 25, &umr_bitfield_default },
	 { "STOP_ALL_ON_SATURATE", 26, 26, &umr_bitfield_default },
};
static struct umr_bitfield mmMMEA1_EDC_CNT[] = {
	 { "DRAMRD_CMDMEM_SEC_COUNT", 0, 1, &umr_bitfield_default },
	 { "DRAMRD_CMDMEM_DED_COUNT", 2, 3, &umr_bitfield_default },
	 { "DRAMWR_CMDMEM_SEC_COUNT", 4, 5, &umr_bitfield_default },
	 { "DRAMWR_CMDMEM_DED_COUNT", 6, 7, &umr_bitfield_default },
	 { "DRAMWR_DATAMEM_SEC_COUNT", 8, 9, &umr_bitfield_default },
	 { "DRAMWR_DATAMEM_DED_COUNT", 10, 11, &umr_bitfield_default },
	 { "RRET_TAGMEM_SEC_COUNT", 12, 13, &umr_bitfield_default },
	 { "RRET_TAGMEM_DED_COUNT", 14, 15, &umr_bitfield_default },
	 { "WRET_TAGMEM_SEC_COUNT", 16, 17, &umr_bitfield_default },
	 { "WRET_TAGMEM_DED_COUNT", 18, 19, &umr_bitfield_default },
	 { "DRAMRD_PAGEMEM_SED_COUNT", 20, 21, &umr_bitfield_default },
	 { "DRAMWR_PAGEMEM_SED_COUNT", 22, 23, &umr_bitfield_default },
	 { "IORD_CMDMEM_SED_COUNT", 24, 25, &umr_bitfield_default },
	 { "IOWR_CMDMEM_SED_COUNT", 26, 27, &umr_bitfield_default },
	 { "IOWR_DATAMEM_SED_COUNT", 28, 29, &umr_bitfield_default },
};
static struct umr_bitfield mmMMEA1_EDC_CNT2[] = {
	 { "GMIRD_CMDMEM_SEC_COUNT", 0, 1, &umr_bitfield_default },
	 { "GMIRD_CMDMEM_DED_COUNT", 2, 3, &umr_bitfield_default },
	 { "GMIWR_CMDMEM_SEC_COUNT", 4, 5, &umr_bitfield_default },
	 { "GMIWR_CMDMEM_DED_COUNT", 6, 7, &umr_bitfield_default },
	 { "GMIWR_DATAMEM_SEC_COUNT", 8, 9, &umr_bitfield_default },
	 { "GMIWR_DATAMEM_DED_COUNT", 10, 11, &umr_bitfield_default },
	 { "GMIRD_PAGEMEM_SED_COUNT", 12, 13, &umr_bitfield_default },
	 { "GMIWR_PAGEMEM_SED_COUNT", 14, 15, &umr_bitfield_default },
};
static struct umr_bitfield mmMMEA1_DSM_CNTL[] = {
	 { "DRAMRD_CMDMEM_DSM_IRRITATOR_DATA", 0, 1, &umr_bitfield_default },
	 { "DRAMRD_CMDMEM_ENABLE_SINGLE_WRITE", 2, 2, &umr_bitfield_default },
	 { "DRAMWR_CMDMEM_DSM_IRRITATOR_DATA", 3, 4, &umr_bitfield_default },
	 { "DRAMWR_CMDMEM_ENABLE_SINGLE_WRITE", 5, 5, &umr_bitfield_default },
	 { "DRAMWR_DATAMEM_DSM_IRRITATOR_DATA", 6, 7, &umr_bitfield_default },
	 { "DRAMWR_DATAMEM_ENABLE_SINGLE_WRITE", 8, 8, &umr_bitfield_default },
	 { "RRET_TAGMEM_DSM_IRRITATOR_DATA", 9, 10, &umr_bitfield_default },
	 { "RRET_TAGMEM_ENABLE_SINGLE_WRITE", 11, 11, &umr_bitfield_default },
	 { "WRET_TAGMEM_DSM_IRRITATOR_DATA", 12, 13, &umr_bitfield_default },
	 { "WRET_TAGMEM_ENABLE_SINGLE_WRITE", 14, 14, &umr_bitfield_default },
	 { "GMIRD_CMDMEM_DSM_IRRITATOR_DATA", 15, 16, &umr_bitfield_default },
	 { "GMIRD_CMDMEM_ENABLE_SINGLE_WRITE", 17, 17, &umr_bitfield_default },
	 { "GMIWR_CMDMEM_DSM_IRRITATOR_DATA", 18, 19, &umr_bitfield_default },
	 { "GMIWR_CMDMEM_ENABLE_SINGLE_WRITE", 20, 20, &umr_bitfield_default },
	 { "GMIWR_DATAMEM_DSM_IRRITATOR_DATA", 21, 22, &umr_bitfield_default },
	 { "GMIWR_DATAMEM_ENABLE_SINGLE_WRITE", 23, 23, &umr_bitfield_default },
};
static struct umr_bitfield mmMMEA1_DSM_CNTLA[] = {
	 { "DRAMRD_PAGEMEM_DSM_IRRITATOR_DATA", 0, 1, &umr_bitfield_default },
	 { "DRAMRD_PAGEMEM_ENABLE_SINGLE_WRITE", 2, 2, &umr_bitfield_default },
	 { "DRAMWR_PAGEMEM_DSM_IRRITATOR_DATA", 3, 4, &umr_bitfield_default },
	 { "DRAMWR_PAGEMEM_ENABLE_SINGLE_WRITE", 5, 5, &umr_bitfield_default },
	 { "IORD_CMDMEM_DSM_IRRITATOR_DATA", 6, 7, &umr_bitfield_default },
	 { "IORD_CMDMEM_ENABLE_SINGLE_WRITE", 8, 8, &umr_bitfield_default },
	 { "IOWR_CMDMEM_DSM_IRRITATOR_DATA", 9, 10, &umr_bitfield_default },
	 { "IOWR_CMDMEM_ENABLE_SINGLE_WRITE", 11, 11, &umr_bitfield_default },
	 { "IOWR_DATAMEM_DSM_IRRITATOR_DATA", 12, 13, &umr_bitfield_default },
	 { "IOWR_DATAMEM_ENABLE_SINGLE_WRITE", 14, 14, &umr_bitfield_default },
	 { "GMIRD_PAGEMEM_DSM_IRRITATOR_DATA", 15, 16, &umr_bitfield_default },
	 { "GMIRD_PAGEMEM_ENABLE_SINGLE_WRITE", 17, 17, &umr_bitfield_default },
	 { "GMIWR_PAGEMEM_DSM_IRRITATOR_DATA", 18, 19, &umr_bitfield_default },
	 { "GMIWR_PAGEMEM_ENABLE_SINGLE_WRITE", 20, 20, &umr_bitfield_default },
};
static struct umr_bitfield mmMMEA1_DSM_CNTL2[] = {
	 { "DRAMRD_CMDMEM_ENABLE_ERROR_INJECT", 0, 1, &umr_bitfield_default },
	 { "DRAMRD_CMDMEM_SELECT_INJECT_DELAY", 2, 2, &umr_bitfield_default },
	 { "DRAMWR_CMDMEM_ENABLE_ERROR_INJECT", 3, 4, &umr_bitfield_default },
	 { "DRAMWR_CMDMEM_SELECT_INJECT_DELAY", 5, 5, &umr_bitfield_default },
	 { "DRAMWR_DATAMEM_ENABLE_ERROR_INJECT", 6, 7, &umr_bitfield_default },
	 { "DRAMWR_DATAMEM_SELECT_INJECT_DELAY", 8, 8, &umr_bitfield_default },
	 { "RRET_TAGMEM_ENABLE_ERROR_INJECT", 9, 10, &umr_bitfield_default },
	 { "RRET_TAGMEM_SELECT_INJECT_DELAY", 11, 11, &umr_bitfield_default },
	 { "WRET_TAGMEM_ENABLE_ERROR_INJECT", 12, 13, &umr_bitfield_default },
	 { "WRET_TAGMEM_SELECT_INJECT_DELAY", 14, 14, &umr_bitfield_default },
	 { "GMIRD_CMDMEM_ENABLE_ERROR_INJECT", 15, 16, &umr_bitfield_default },
	 { "GMIRD_CMDMEM_SELECT_INJECT_DELAY", 17, 17, &umr_bitfield_default },
	 { "GMIWR_CMDMEM_ENABLE_ERROR_INJECT", 18, 19, &umr_bitfield_default },
	 { "GMIWR_CMDMEM_SELECT_INJECT_DELAY", 20, 20, &umr_bitfield_default },
	 { "GMIWR_DATAMEM_ENABLE_ERROR_INJECT", 21, 22, &umr_bitfield_default },
	 { "GMIWR_DATAMEM_SELECT_INJECT_DELAY", 23, 23, &umr_bitfield_default },
	 { "INJECT_DELAY", 26, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMMEA1_DSM_CNTL2A[] = {
	 { "DRAMRD_PAGEMEM_ENABLE_ERROR_INJECT", 0, 1, &umr_bitfield_default },
	 { "DRAMRD_PAGEMEM_SELECT_INJECT_DELAY", 2, 2, &umr_bitfield_default },
	 { "DRAMWR_PAGEMEM_ENABLE_ERROR_INJECT", 3, 4, &umr_bitfield_default },
	 { "DRAMWR_PAGEMEM_SELECT_INJECT_DELAY", 5, 5, &umr_bitfield_default },
	 { "IORD_CMDMEM_ENABLE_ERROR_INJECT", 6, 7, &umr_bitfield_default },
	 { "IORD_CMDMEM_SELECT_INJECT_DELAY", 8, 8, &umr_bitfield_default },
	 { "IOWR_CMDMEM_ENABLE_ERROR_INJECT", 9, 10, &umr_bitfield_default },
	 { "IOWR_CMDMEM_SELECT_INJECT_DELAY", 11, 11, &umr_bitfield_default },
	 { "IOWR_DATAMEM_ENABLE_ERROR_INJECT", 12, 13, &umr_bitfield_default },
	 { "IOWR_DATAMEM_SELECT_INJECT_DELAY", 14, 14, &umr_bitfield_default },
	 { "GMIRD_PAGEMEM_ENABLE_ERROR_INJECT", 15, 16, &umr_bitfield_default },
	 { "GMIRD_PAGEMEM_SELECT_INJECT_DELAY", 17, 17, &umr_bitfield_default },
	 { "GMIWR_PAGEMEM_ENABLE_ERROR_INJECT", 18, 19, &umr_bitfield_default },
	 { "GMIWR_PAGEMEM_SELECT_INJECT_DELAY", 20, 20, &umr_bitfield_default },
};
static struct umr_bitfield mmMMEA1_CGTT_CLK_CTRL[] = {
	 { "ON_DELAY", 0, 3, &umr_bitfield_default },
	 { "OFF_HYSTERESIS", 4, 11, &umr_bitfield_default },
	 { "SOFT_STALL_OVERRIDE", 22, 22, &umr_bitfield_default },
	 { "LS_OVERRIDE", 27, 27, &umr_bitfield_default },
	 { "SOFT_OVERRIDE_WRITE", 28, 28, &umr_bitfield_default },
	 { "SOFT_OVERRIDE_READ", 29, 29, &umr_bitfield_default },
	 { "SOFT_OVERRIDE_RETURN", 30, 30, &umr_bitfield_default },
	 { "SOFT_OVERRIDE_REGISTER", 31, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMMEA1_EDC_MODE[] = {
	 { "COUNT_FED_OUT", 16, 16, &umr_bitfield_default },
	 { "GATE_FUE", 17, 17, &umr_bitfield_default },
	 { "DED_MODE", 20, 21, &umr_bitfield_default },
	 { "PROP_FED", 29, 29, &umr_bitfield_default },
	 { "BYPASS", 31, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMMEA1_ERR_STATUS[] = {
	 { "SDP_RDRSP_STATUS", 0, 3, &umr_bitfield_default },
	 { "SDP_WRRSP_STATUS", 4, 7, &umr_bitfield_default },
	 { "SDP_RDRSP_DATAPARITY_ERROR", 8, 8, &umr_bitfield_default },
	 { "CLEAR_ERROR_STATUS", 9, 9, &umr_bitfield_default },
	 { "BUSY_ON_ERROR", 10, 10, &umr_bitfield_default },
};
static struct umr_bitfield mmMMEA1_MISC2[] = {
	 { "CSGROUP_SWAP_IN_DRAM_ARB", 0, 0, &umr_bitfield_default },
	 { "CSGROUP_SWAP_IN_GMI_ARB", 1, 1, &umr_bitfield_default },
	 { "CSGRP_BURST_LIMIT_DATA_DRAM", 2, 6, &umr_bitfield_default },
	 { "CSGRP_BURST_LIMIT_DATA_GMI", 7, 11, &umr_bitfield_default },
};
static struct umr_bitfield mmPCTL_MISC[] = {
	 { "ALLOW_DEEP_SLEEP_MODE", 0, 2, &umr_bitfield_default },
	 { "STCTRL_RSMU_IDLE_THRESHOLD", 3, 5, &umr_bitfield_default },
	 { "STCTRL_DAGB_IDLE_THRESHOLD", 6, 10, &umr_bitfield_default },
	 { "STCTRL_IGNORE_PROTECTION_FAULT", 11, 11, &umr_bitfield_default },
	 { "IGNORE_EA0_SDP_ACK", 12, 12, &umr_bitfield_default },
	 { "IGNORE_EA1_SDP_ACK", 13, 13, &umr_bitfield_default },
	 { "PGFSM_CMD_STATUS", 14, 15, &umr_bitfield_default },
};
static struct umr_bitfield mmPCTL_MMHUB_DEEPSLEEP[] = {
	 { "DS0", 0, 0, &umr_bitfield_default },
	 { "DS1", 1, 1, &umr_bitfield_default },
	 { "DS2", 2, 2, &umr_bitfield_default },
	 { "DS3", 3, 3, &umr_bitfield_default },
	 { "DS4", 4, 4, &umr_bitfield_default },
	 { "DS5", 5, 5, &umr_bitfield_default },
	 { "DS6", 6, 6, &umr_bitfield_default },
	 { "DS7", 7, 7, &umr_bitfield_default },
	 { "DS8", 8, 8, &umr_bitfield_default },
	 { "DS9", 9, 9, &umr_bitfield_default },
	 { "DS10", 10, 10, &umr_bitfield_default },
	 { "DS11", 11, 11, &umr_bitfield_default },
	 { "DS12", 12, 12, &umr_bitfield_default },
	 { "DS13", 13, 13, &umr_bitfield_default },
	 { "DS14", 14, 14, &umr_bitfield_default },
	 { "DS15", 15, 15, &umr_bitfield_default },
	 { "DS16", 16, 16, &umr_bitfield_default },
	 { "SETCLEAR", 31, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmPCTL_MMHUB_DEEPSLEEP_OVERRIDE[] = {
	 { "DS0", 0, 0, &umr_bitfield_default },
	 { "DS1", 1, 1, &umr_bitfield_default },
	 { "DS2", 2, 2, &umr_bitfield_default },
	 { "DS3", 3, 3, &umr_bitfield_default },
	 { "DS4", 4, 4, &umr_bitfield_default },
	 { "DS5", 5, 5, &umr_bitfield_default },
	 { "DS6", 6, 6, &umr_bitfield_default },
	 { "DS7", 7, 7, &umr_bitfield_default },
	 { "DS8", 8, 8, &umr_bitfield_default },
	 { "DS9", 9, 9, &umr_bitfield_default },
	 { "DS10", 10, 10, &umr_bitfield_default },
	 { "DS11", 11, 11, &umr_bitfield_default },
	 { "DS12", 12, 12, &umr_bitfield_default },
	 { "DS13", 13, 13, &umr_bitfield_default },
	 { "DS14", 14, 14, &umr_bitfield_default },
	 { "DS15", 15, 15, &umr_bitfield_default },
	 { "DS16", 16, 16, &umr_bitfield_default },
};
static struct umr_bitfield mmPCTL_PG_IGNORE_DEEPSLEEP[] = {
	 { "ALLIPS", 0, 0, &umr_bitfield_default },
	 { "DS0", 1, 1, &umr_bitfield_default },
	 { "DS1", 2, 2, &umr_bitfield_default },
	 { "DS2", 3, 3, &umr_bitfield_default },
	 { "DS3", 4, 4, &umr_bitfield_default },
	 { "DS4", 5, 5, &umr_bitfield_default },
	 { "DS5", 6, 6, &umr_bitfield_default },
	 { "DS6", 7, 7, &umr_bitfield_default },
	 { "DS7", 8, 8, &umr_bitfield_default },
	 { "DS8", 9, 9, &umr_bitfield_default },
	 { "DS9", 10, 10, &umr_bitfield_default },
	 { "DS10", 11, 11, &umr_bitfield_default },
	 { "DS11", 12, 12, &umr_bitfield_default },
	 { "DS12", 13, 13, &umr_bitfield_default },
	 { "DS13", 14, 14, &umr_bitfield_default },
	 { "DS14", 15, 15, &umr_bitfield_default },
	 { "DS15", 16, 16, &umr_bitfield_default },
	 { "DS16", 17, 17, &umr_bitfield_default },
};
static struct umr_bitfield mmPCTL_PG_DAGB[] = {
	 { "DS0", 0, 0, &umr_bitfield_default },
	 { "DS1", 1, 1, &umr_bitfield_default },
	 { "DS2", 2, 2, &umr_bitfield_default },
	 { "DS3", 3, 3, &umr_bitfield_default },
	 { "DS4", 4, 4, &umr_bitfield_default },
	 { "DS5", 5, 5, &umr_bitfield_default },
	 { "DS6", 6, 6, &umr_bitfield_default },
	 { "DS7", 7, 7, &umr_bitfield_default },
	 { "DS8", 8, 8, &umr_bitfield_default },
	 { "DS9", 9, 9, &umr_bitfield_default },
	 { "DS10", 10, 10, &umr_bitfield_default },
	 { "DS11", 11, 11, &umr_bitfield_default },
	 { "DS12", 12, 12, &umr_bitfield_default },
	 { "DS13", 13, 13, &umr_bitfield_default },
	 { "DS14", 14, 14, &umr_bitfield_default },
	 { "DS15", 15, 15, &umr_bitfield_default },
	 { "DS16", 16, 16, &umr_bitfield_default },
};
static struct umr_bitfield mmPCTL0_RENG_RAM_INDEX[] = {
	 { "RENG_RAM_INDEX", 0, 10, &umr_bitfield_default },
};
static struct umr_bitfield mmPCTL0_RENG_RAM_DATA[] = {
	 { "RENG_RAM_DATA", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmPCTL0_RENG_EXECUTE[] = {
	 { "RENG_EXECUTE_ON_PWR_UP", 0, 0, &umr_bitfield_default },
	 { "RENG_EXECUTE_NOW", 1, 1, &umr_bitfield_default },
	 { "RENG_EXECUTE_NOW_MODE", 2, 2, &umr_bitfield_default },
	 { "RENG_EXECUTE_NOW_START_PTR", 3, 13, &umr_bitfield_default },
	 { "RENG_EXECUTE_END_PTR", 14, 24, &umr_bitfield_default },
	 { "RENG_EXECUTE_ON_REG_UPDATE", 25, 25, &umr_bitfield_default },
};
static struct umr_bitfield mmPCTL0_MISC[] = {
	 { "CRITICAL_REGS_LOCK", 11, 11, &umr_bitfield_default },
	 { "TILE_IDLE_THRESHOLD", 12, 14, &umr_bitfield_default },
	 { "RENG_MEM_LS_ENABLE", 15, 15, &umr_bitfield_default },
	 { "STCTRL_FORCE_PGFSM_CMD_DONE", 16, 16, &umr_bitfield_default },
};
static struct umr_bitfield mmPCTL0_STCTRL_REGISTER_SAVE_RANGE0[] = {
	 { "STCTRL_REGISTER_SAVE_BASE", 0, 15, &umr_bitfield_default },
	 { "STCTRL_REGISTER_SAVE_LIMIT", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmPCTL0_STCTRL_REGISTER_SAVE_RANGE1[] = {
	 { "STCTRL_REGISTER_SAVE_BASE", 0, 15, &umr_bitfield_default },
	 { "STCTRL_REGISTER_SAVE_LIMIT", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmPCTL0_STCTRL_REGISTER_SAVE_RANGE2[] = {
	 { "STCTRL_REGISTER_SAVE_BASE", 0, 15, &umr_bitfield_default },
	 { "STCTRL_REGISTER_SAVE_LIMIT", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmPCTL0_STCTRL_REGISTER_SAVE_EXCL_SET[] = {
	 { "STCTRL_REGISTER_SAVE_EXCL0", 0, 15, &umr_bitfield_default },
	 { "STCTRL_REGISTER_SAVE_EXCL1", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmPCTL0_STCTRL_REGISTER_SAVE_EXCL_SET1[] = {
	 { "STCTRL_REGISTER_SAVE_EXCL2", 0, 15, &umr_bitfield_default },
	 { "STCTRL_REGISTER_SAVE_EXCL3", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmPCTL1_RENG_RAM_INDEX[] = {
	 { "RENG_RAM_INDEX", 0, 9, &umr_bitfield_default },
};
static struct umr_bitfield mmPCTL1_RENG_RAM_DATA[] = {
	 { "RENG_RAM_DATA", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmPCTL1_RENG_EXECUTE[] = {
	 { "RENG_EXECUTE_ON_PWR_UP", 0, 0, &umr_bitfield_default },
	 { "RENG_EXECUTE_NOW", 1, 1, &umr_bitfield_default },
	 { "RENG_EXECUTE_NOW_MODE", 2, 2, &umr_bitfield_default },
	 { "RENG_EXECUTE_NOW_START_PTR", 3, 12, &umr_bitfield_default },
	 { "RENG_EXECUTE_END_PTR", 13, 22, &umr_bitfield_default },
	 { "RENG_EXECUTE_ON_REG_UPDATE", 23, 23, &umr_bitfield_default },
};
static struct umr_bitfield mmPCTL1_MISC[] = {
	 { "CRITICAL_REGS_LOCK", 10, 10, &umr_bitfield_default },
	 { "TILE_IDLE_THRESHOLD", 11, 13, &umr_bitfield_default },
	 { "RENG_MEM_LS_ENABLE", 14, 14, &umr_bitfield_default },
	 { "STCTRL_FORCE_PGFSM_CMD_DONE", 15, 15, &umr_bitfield_default },
	 { "DEEPSLEEP_DISCSDP", 16, 16, &umr_bitfield_default },
};
static struct umr_bitfield mmPCTL1_STCTRL_REGISTER_SAVE_RANGE0[] = {
	 { "STCTRL_REGISTER_SAVE_BASE", 0, 15, &umr_bitfield_default },
	 { "STCTRL_REGISTER_SAVE_LIMIT", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmPCTL1_STCTRL_REGISTER_SAVE_RANGE1[] = {
	 { "STCTRL_REGISTER_SAVE_BASE", 0, 15, &umr_bitfield_default },
	 { "STCTRL_REGISTER_SAVE_LIMIT", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmPCTL1_STCTRL_REGISTER_SAVE_RANGE2[] = {
	 { "STCTRL_REGISTER_SAVE_BASE", 0, 15, &umr_bitfield_default },
	 { "STCTRL_REGISTER_SAVE_LIMIT", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmPCTL1_STCTRL_REGISTER_SAVE_EXCL_SET[] = {
	 { "STCTRL_REGISTER_SAVE_EXCL0", 0, 15, &umr_bitfield_default },
	 { "STCTRL_REGISTER_SAVE_EXCL1", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmPCTL1_STCTRL_REGISTER_SAVE_EXCL_SET1[] = {
	 { "STCTRL_REGISTER_SAVE_EXCL2", 0, 15, &umr_bitfield_default },
	 { "STCTRL_REGISTER_SAVE_EXCL3", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmPCTL2_RENG_RAM_INDEX[] = {
	 { "RENG_RAM_INDEX", 0, 9, &umr_bitfield_default },
};
static struct umr_bitfield mmPCTL2_RENG_RAM_DATA[] = {
	 { "RENG_RAM_DATA", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmPCTL2_RENG_EXECUTE[] = {
	 { "RENG_EXECUTE_ON_PWR_UP", 0, 0, &umr_bitfield_default },
	 { "RENG_EXECUTE_NOW", 1, 1, &umr_bitfield_default },
	 { "RENG_EXECUTE_NOW_MODE", 2, 2, &umr_bitfield_default },
	 { "RENG_EXECUTE_NOW_START_PTR", 3, 12, &umr_bitfield_default },
	 { "RENG_EXECUTE_END_PTR", 13, 22, &umr_bitfield_default },
	 { "RENG_EXECUTE_ON_REG_UPDATE", 23, 23, &umr_bitfield_default },
};
static struct umr_bitfield mmPCTL2_MISC[] = {
	 { "CRITICAL_REGS_LOCK", 10, 10, &umr_bitfield_default },
	 { "TILE_IDLE_THRESHOLD", 11, 13, &umr_bitfield_default },
	 { "RENG_MEM_LS_ENABLE", 14, 14, &umr_bitfield_default },
	 { "STCTRL_FORCE_PGFSM_CMD_DONE", 15, 15, &umr_bitfield_default },
	 { "DEEPSLEEP_DISCSDP", 16, 16, &umr_bitfield_default },
};
static struct umr_bitfield mmPCTL2_STCTRL_REGISTER_SAVE_RANGE0[] = {
	 { "STCTRL_REGISTER_SAVE_BASE", 0, 15, &umr_bitfield_default },
	 { "STCTRL_REGISTER_SAVE_LIMIT", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmPCTL2_STCTRL_REGISTER_SAVE_RANGE1[] = {
	 { "STCTRL_REGISTER_SAVE_BASE", 0, 15, &umr_bitfield_default },
	 { "STCTRL_REGISTER_SAVE_LIMIT", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmPCTL2_STCTRL_REGISTER_SAVE_RANGE2[] = {
	 { "STCTRL_REGISTER_SAVE_BASE", 0, 15, &umr_bitfield_default },
	 { "STCTRL_REGISTER_SAVE_LIMIT", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmPCTL2_STCTRL_REGISTER_SAVE_EXCL_SET[] = {
	 { "STCTRL_REGISTER_SAVE_EXCL0", 0, 15, &umr_bitfield_default },
	 { "STCTRL_REGISTER_SAVE_EXCL1", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmPCTL2_STCTRL_REGISTER_SAVE_EXCL_SET1[] = {
	 { "STCTRL_REGISTER_SAVE_EXCL2", 0, 15, &umr_bitfield_default },
	 { "STCTRL_REGISTER_SAVE_EXCL3", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_VM_MX_L1_TLB0_STATUS[] = {
	 { "BUSY", 0, 0, &umr_bitfield_default },
	 { "FOUND_PARITY_ERRORS", 1, 1, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_VM_MX_L1_TLB1_STATUS[] = {
	 { "BUSY", 0, 0, &umr_bitfield_default },
	 { "FOUND_PARITY_ERRORS", 1, 1, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_VM_MX_L1_TLB2_STATUS[] = {
	 { "BUSY", 0, 0, &umr_bitfield_default },
	 { "FOUND_PARITY_ERRORS", 1, 1, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_VM_MX_L1_TLB3_STATUS[] = {
	 { "BUSY", 0, 0, &umr_bitfield_default },
	 { "FOUND_PARITY_ERRORS", 1, 1, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_VM_MX_L1_TLB4_STATUS[] = {
	 { "BUSY", 0, 0, &umr_bitfield_default },
	 { "FOUND_PARITY_ERRORS", 1, 1, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_VM_MX_L1_TLB5_STATUS[] = {
	 { "BUSY", 0, 0, &umr_bitfield_default },
	 { "FOUND_PARITY_ERRORS", 1, 1, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_VM_MX_L1_TLB6_STATUS[] = {
	 { "BUSY", 0, 0, &umr_bitfield_default },
	 { "FOUND_PARITY_ERRORS", 1, 1, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_VM_MX_L1_TLB7_STATUS[] = {
	 { "BUSY", 0, 0, &umr_bitfield_default },
	 { "FOUND_PARITY_ERRORS", 1, 1, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_VM_MX_L1_PERFCOUNTER0_CFG[] = {
	 { "PERF_SEL", 0, 7, &umr_bitfield_default },
	 { "PERF_SEL_END", 8, 15, &umr_bitfield_default },
	 { "PERF_MODE", 24, 27, &umr_bitfield_default },
	 { "ENABLE", 28, 28, &umr_bitfield_default },
	 { "CLEAR", 29, 29, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_VM_MX_L1_PERFCOUNTER1_CFG[] = {
	 { "PERF_SEL", 0, 7, &umr_bitfield_default },
	 { "PERF_SEL_END", 8, 15, &umr_bitfield_default },
	 { "PERF_MODE", 24, 27, &umr_bitfield_default },
	 { "ENABLE", 28, 28, &umr_bitfield_default },
	 { "CLEAR", 29, 29, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_VM_MX_L1_PERFCOUNTER2_CFG[] = {
	 { "PERF_SEL", 0, 7, &umr_bitfield_default },
	 { "PERF_SEL_END", 8, 15, &umr_bitfield_default },
	 { "PERF_MODE", 24, 27, &umr_bitfield_default },
	 { "ENABLE", 28, 28, &umr_bitfield_default },
	 { "CLEAR", 29, 29, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_VM_MX_L1_PERFCOUNTER3_CFG[] = {
	 { "PERF_SEL", 0, 7, &umr_bitfield_default },
	 { "PERF_SEL_END", 8, 15, &umr_bitfield_default },
	 { "PERF_MODE", 24, 27, &umr_bitfield_default },
	 { "ENABLE", 28, 28, &umr_bitfield_default },
	 { "CLEAR", 29, 29, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL[] = {
	 { "PERF_COUNTER_SELECT", 0, 3, &umr_bitfield_default },
	 { "START_TRIGGER", 8, 15, &umr_bitfield_default },
	 { "STOP_TRIGGER", 16, 23, &umr_bitfield_default },
	 { "ENABLE_ANY", 24, 24, &umr_bitfield_default },
	 { "CLEAR_ALL", 25, 25, &umr_bitfield_default },
	 { "STOP_ALL_ON_SATURATE", 26, 26, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_VM_MX_L1_PERFCOUNTER_LO[] = {
	 { "COUNTER_LO", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_VM_MX_L1_PERFCOUNTER_HI[] = {
	 { "COUNTER_HI", 0, 15, &umr_bitfield_default },
	 { "COMPARE_VALUE", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmATC_L2_CNTL[] = {
	 { "NUMBER_OF_TRANSLATION_READ_REQUESTS", 0, 1, &umr_bitfield_default },
	 { "NUMBER_OF_TRANSLATION_WRITE_REQUESTS", 3, 4, &umr_bitfield_default },
	 { "NUMBER_OF_TRANSLATION_READS_DEPENDS_ON_ADDR_MOD", 6, 6, &umr_bitfield_default },
	 { "NUMBER_OF_TRANSLATION_WRITES_DEPENDS_ON_ADDR_MOD", 7, 7, &umr_bitfield_default },
	 { "CACHE_INVALIDATE_MODE", 8, 10, &umr_bitfield_default },
	 { "ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY", 11, 11, &umr_bitfield_default },
};
static struct umr_bitfield mmATC_L2_CNTL2[] = {
	 { "BANK_SELECT", 0, 5, &umr_bitfield_default },
	 { "L2_CACHE_UPDATE_MODE", 6, 7, &umr_bitfield_default },
	 { "ENABLE_L2_CACHE_LRU_UPDATE_BY_WRITE", 8, 8, &umr_bitfield_default },
	 { "L2_CACHE_SWAP_TAG_INDEX_LSBS", 9, 11, &umr_bitfield_default },
	 { "L2_CACHE_VMID_MODE", 12, 14, &umr_bitfield_default },
	 { "L2_CACHE_UPDATE_WILDCARD_REFERENCE_VALUE", 15, 20, &umr_bitfield_default },
};
static struct umr_bitfield mmATC_L2_CACHE_DATA0[] = {
	 { "DATA_REGISTER_VALID", 0, 0, &umr_bitfield_default },
	 { "CACHE_ENTRY_VALID", 1, 1, &umr_bitfield_default },
	 { "CACHED_ATTRIBUTES", 2, 22, &umr_bitfield_default },
	 { "VIRTUAL_PAGE_ADDRESS_HIGH", 23, 26, &umr_bitfield_default },
};
static struct umr_bitfield mmATC_L2_CACHE_DATA1[] = {
	 { "VIRTUAL_PAGE_ADDRESS_LOW", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmATC_L2_CACHE_DATA2[] = {
	 { "PHYSICAL_PAGE_ADDRESS", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmATC_L2_CNTL3[] = {
	 { "DELAY_SEND_INVALIDATION_REQUEST", 0, 2, &umr_bitfield_default },
	 { "ATS_REQUEST_CREDIT_MINUS1", 3, 8, &umr_bitfield_default },
};
static struct umr_bitfield mmATC_L2_STATUS[] = {
	 { "BUSY", 0, 0, &umr_bitfield_default },
	 { "PARITY_ERROR_INFO", 1, 29, &umr_bitfield_default },
};
static struct umr_bitfield mmATC_L2_STATUS2[] = {
	 { "IFIFO_NON_FATAL_PARITY_ERROR_INFO", 0, 7, &umr_bitfield_default },
	 { "IFIFO_FATAL_PARITY_ERROR_INFO", 8, 15, &umr_bitfield_default },
};
static struct umr_bitfield mmATC_L2_MISC_CG[] = {
	 { "OFFDLY", 6, 11, &umr_bitfield_default },
	 { "ENABLE", 18, 18, &umr_bitfield_default },
	 { "MEM_LS_ENABLE", 19, 19, &umr_bitfield_default },
};
static struct umr_bitfield mmATC_L2_MEM_POWER_LS[] = {
	 { "LS_SETUP", 0, 5, &umr_bitfield_default },
	 { "LS_HOLD", 6, 11, &umr_bitfield_default },
};
static struct umr_bitfield mmATC_L2_CGTT_CLK_CTRL[] = {
	 { "ON_DELAY", 0, 3, &umr_bitfield_default },
	 { "OFF_HYSTERESIS", 4, 11, &umr_bitfield_default },
	 { "MGLS_OVERRIDE", 15, 15, &umr_bitfield_default },
	 { "SOFT_STALL_OVERRIDE", 16, 23, &umr_bitfield_default },
	 { "SOFT_OVERRIDE", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmVM_L2_CNTL[] = {
	 { "ENABLE_L2_CACHE", 0, 0, &umr_bitfield_default },
	 { "ENABLE_L2_FRAGMENT_PROCESSING", 1, 1, &umr_bitfield_default },
	 { "L2_CACHE_PTE_ENDIAN_SWAP_MODE", 2, 3, &umr_bitfield_default },
	 { "L2_CACHE_PDE_ENDIAN_SWAP_MODE", 4, 5, &umr_bitfield_default },
	 { "L2_PDE0_CACHE_TAG_GENERATION_MODE", 8, 8, &umr_bitfield_default },
	 { "ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE", 9, 9, &umr_bitfield_default },
	 { "ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE", 10, 10, &umr_bitfield_default },
	 { "ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY", 11, 11, &umr_bitfield_default },
	 { "L2_PDE0_CACHE_SPLIT_MODE", 12, 14, &umr_bitfield_default },
	 { "EFFECTIVE_L2_QUEUE_SIZE", 15, 17, &umr_bitfield_default },
	 { "PDE_FAULT_CLASSIFICATION", 18, 18, &umr_bitfield_default },
	 { "CONTEXT1_IDENTITY_ACCESS_MODE", 19, 20, &umr_bitfield_default },
	 { "IDENTITY_MODE_FRAGMENT_SIZE", 21, 25, &umr_bitfield_default },
	 { "L2_PTE_CACHE_ADDR_MODE", 26, 27, &umr_bitfield_default },
};
static struct umr_bitfield mmVM_L2_CNTL2[] = {
	 { "INVALIDATE_ALL_L1_TLBS", 0, 0, &umr_bitfield_default },
	 { "INVALIDATE_L2_CACHE", 1, 1, &umr_bitfield_default },
	 { "DISABLE_INVALIDATE_PER_DOMAIN", 21, 21, &umr_bitfield_default },
	 { "DISABLE_BIGK_CACHE_OPTIMIZATION", 22, 22, &umr_bitfield_default },
	 { "L2_PTE_CACHE_VMID_MODE", 23, 25, &umr_bitfield_default },
	 { "INVALIDATE_CACHE_MODE", 26, 27, &umr_bitfield_default },
	 { "PDE_CACHE_EFFECTIVE_SIZE", 28, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmVM_L2_CNTL3[] = {
	 { "BANK_SELECT", 0, 5, &umr_bitfield_default },
	 { "L2_CACHE_UPDATE_MODE", 6, 7, &umr_bitfield_default },
	 { "L2_CACHE_UPDATE_WILDCARD_REFERENCE_VALUE", 8, 12, &umr_bitfield_default },
	 { "L2_CACHE_BIGK_FRAGMENT_SIZE", 15, 19, &umr_bitfield_default },
	 { "L2_CACHE_BIGK_ASSOCIATIVITY", 20, 20, &umr_bitfield_default },
	 { "L2_CACHE_4K_EFFECTIVE_SIZE", 21, 23, &umr_bitfield_default },
	 { "L2_CACHE_BIGK_EFFECTIVE_SIZE", 24, 27, &umr_bitfield_default },
	 { "L2_CACHE_4K_FORCE_MISS", 28, 28, &umr_bitfield_default },
	 { "L2_CACHE_BIGK_FORCE_MISS", 29, 29, &umr_bitfield_default },
	 { "PDE_CACHE_FORCE_MISS", 30, 30, &umr_bitfield_default },
	 { "L2_CACHE_4K_ASSOCIATIVITY", 31, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmVM_L2_STATUS[] = {
	 { "L2_BUSY", 0, 0, &umr_bitfield_default },
	 { "CONTEXT_DOMAIN_BUSY", 1, 16, &umr_bitfield_default },
	 { "FOUND_4K_PTE_CACHE_PARITY_ERRORS", 17, 17, &umr_bitfield_default },
	 { "FOUND_BIGK_PTE_CACHE_PARITY_ERRORS", 18, 18, &umr_bitfield_default },
	 { "FOUND_PDE0_CACHE_PARITY_ERRORS", 19, 19, &umr_bitfield_default },
	 { "FOUND_PDE1_CACHE_PARITY_ERRORS", 20, 20, &umr_bitfield_default },
	 { "FOUND_PDE2_CACHE_PARITY_ERRORS", 21, 21, &umr_bitfield_default },
};
static struct umr_bitfield mmVM_DUMMY_PAGE_FAULT_CNTL[] = {
	 { "DUMMY_PAGE_FAULT_ENABLE", 0, 0, &umr_bitfield_default },
	 { "DUMMY_PAGE_ADDRESS_LOGICAL", 1, 1, &umr_bitfield_default },
	 { "DUMMY_PAGE_COMPARE_MSBS", 2, 7, &umr_bitfield_default },
};
static struct umr_bitfield mmVM_DUMMY_PAGE_FAULT_ADDR_LO32[] = {
	 { "DUMMY_PAGE_ADDR_LO32", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmVM_DUMMY_PAGE_FAULT_ADDR_HI32[] = {
	 { "DUMMY_PAGE_ADDR_HI4", 0, 3, &umr_bitfield_default },
};
static struct umr_bitfield mmVM_L2_PROTECTION_FAULT_CNTL[] = {
	 { "CLEAR_PROTECTION_FAULT_STATUS_ADDR", 0, 0, &umr_bitfield_default },
	 { "ALLOW_SUBSEQUENT_PROTECTION_FAULT_STATUS_ADDR_UPDATES", 1, 1, &umr_bitfield_default },
	 { "RANGE_PROTECTION_FAULT_ENABLE_DEFAULT", 2, 2, &umr_bitfield_default },
	 { "PDE0_PROTECTION_FAULT_ENABLE_DEFAULT", 3, 3, &umr_bitfield_default },
	 { "PDE1_PROTECTION_FAULT_ENABLE_DEFAULT", 4, 4, &umr_bitfield_default },
	 { "PDE2_PROTECTION_FAULT_ENABLE_DEFAULT", 5, 5, &umr_bitfield_default },
	 { "TRANSLATE_FURTHER_PROTECTION_FAULT_ENABLE_DEFAULT", 6, 6, &umr_bitfield_default },
	 { "NACK_PROTECTION_FAULT_ENABLE_DEFAULT", 7, 7, &umr_bitfield_default },
	 { "DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT", 8, 8, &umr_bitfield_default },
	 { "VALID_PROTECTION_FAULT_ENABLE_DEFAULT", 9, 9, &umr_bitfield_default },
	 { "READ_PROTECTION_FAULT_ENABLE_DEFAULT", 10, 10, &umr_bitfield_default },
	 { "WRITE_PROTECTION_FAULT_ENABLE_DEFAULT", 11, 11, &umr_bitfield_default },
	 { "EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT", 12, 12, &umr_bitfield_default },
	 { "CLIENT_ID_NO_RETRY_FAULT_INTERRUPT", 13, 28, &umr_bitfield_default },
	 { "OTHER_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT", 29, 29, &umr_bitfield_default },
	 { "CRASH_ON_NO_RETRY_FAULT", 30, 30, &umr_bitfield_default },
	 { "CRASH_ON_RETRY_FAULT", 31, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmVM_L2_PROTECTION_FAULT_CNTL2[] = {
	 { "CLIENT_ID_PRT_FAULT_INTERRUPT", 0, 15, &umr_bitfield_default },
	 { "OTHER_CLIENT_ID_PRT_FAULT_INTERRUPT", 16, 16, &umr_bitfield_default },
	 { "ACTIVE_PAGE_MIGRATION_PTE", 17, 17, &umr_bitfield_default },
	 { "ACTIVE_PAGE_MIGRATION_PTE_READ_RETRY", 18, 18, &umr_bitfield_default },
	 { "ENABLE_RETRY_FAULT_INTERRUPT", 19, 19, &umr_bitfield_default },
};
static struct umr_bitfield mmVM_L2_PROTECTION_FAULT_MM_CNTL3[] = {
	 { "VML1_READ_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmVM_L2_PROTECTION_FAULT_MM_CNTL4[] = {
	 { "VML1_WRITE_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmVM_L2_PROTECTION_FAULT_STATUS[] = {
	 { "MORE_FAULTS", 0, 0, &umr_bitfield_default },
	 { "WALKER_ERROR", 1, 3, &umr_bitfield_default },
	 { "PERMISSION_FAULTS", 4, 7, &umr_bitfield_default },
	 { "MAPPING_ERROR", 8, 8, &umr_bitfield_default },
	 { "CID", 9, 17, &umr_bitfield_default },
	 { "RW", 18, 18, &umr_bitfield_default },
	 { "ATOMIC", 19, 19, &umr_bitfield_default },
	 { "VMID", 20, 23, &umr_bitfield_default },
	 { "VF", 24, 24, &umr_bitfield_default },
	 { "VFID", 25, 28, &umr_bitfield_default },
};
static struct umr_bitfield mmVM_L2_PROTECTION_FAULT_ADDR_LO32[] = {
	 { "LOGICAL_PAGE_ADDR_LO32", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmVM_L2_PROTECTION_FAULT_ADDR_HI32[] = {
	 { "LOGICAL_PAGE_ADDR_HI4", 0, 3, &umr_bitfield_default },
};
static struct umr_bitfield mmVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32[] = {
	 { "PHYSICAL_PAGE_ADDR_LO32", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32[] = {
	 { "PHYSICAL_PAGE_ADDR_HI4", 0, 3, &umr_bitfield_default },
};
static struct umr_bitfield mmVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32[] = {
	 { "LOGICAL_PAGE_NUMBER_LO32", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32[] = {
	 { "LOGICAL_PAGE_NUMBER_HI4", 0, 3, &umr_bitfield_default },
};
static struct umr_bitfield mmVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32[] = {
	 { "LOGICAL_PAGE_NUMBER_LO32", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32[] = {
	 { "LOGICAL_PAGE_NUMBER_HI4", 0, 3, &umr_bitfield_default },
};
static struct umr_bitfield mmVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32[] = {
	 { "PHYSICAL_PAGE_OFFSET_LO32", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32[] = {
	 { "PHYSICAL_PAGE_OFFSET_HI4", 0, 3, &umr_bitfield_default },
};
static struct umr_bitfield mmVM_L2_CNTL4[] = {
	 { "L2_CACHE_4K_PARTITION_COUNT", 0, 5, &umr_bitfield_default },
	 { "VMC_TAP_PDE_REQUEST_PHYSICAL", 6, 6, &umr_bitfield_default },
	 { "VMC_TAP_PTE_REQUEST_PHYSICAL", 7, 7, &umr_bitfield_default },
	 { "MM_NONRT_IFIFO_ACTIVE_TRANSACTION_LIMIT", 8, 17, &umr_bitfield_default },
	 { "MM_SOFTRT_IFIFO_ACTIVE_TRANSACTION_LIMIT", 18, 27, &umr_bitfield_default },
	 { "BPM_CGCGLS_OVERRIDE", 28, 28, &umr_bitfield_default },
};
static struct umr_bitfield mmVM_L2_MM_GROUP_RT_CLASSES[] = {
	 { "GROUP_0_RT_CLASS", 0, 0, &umr_bitfield_default },
	 { "GROUP_1_RT_CLASS", 1, 1, &umr_bitfield_default },
	 { "GROUP_2_RT_CLASS", 2, 2, &umr_bitfield_default },
	 { "GROUP_3_RT_CLASS", 3, 3, &umr_bitfield_default },
	 { "GROUP_4_RT_CLASS", 4, 4, &umr_bitfield_default },
	 { "GROUP_5_RT_CLASS", 5, 5, &umr_bitfield_default },
	 { "GROUP_6_RT_CLASS", 6, 6, &umr_bitfield_default },
	 { "GROUP_7_RT_CLASS", 7, 7, &umr_bitfield_default },
	 { "GROUP_8_RT_CLASS", 8, 8, &umr_bitfield_default },
	 { "GROUP_9_RT_CLASS", 9, 9, &umr_bitfield_default },
	 { "GROUP_10_RT_CLASS", 10, 10, &umr_bitfield_default },
	 { "GROUP_11_RT_CLASS", 11, 11, &umr_bitfield_default },
	 { "GROUP_12_RT_CLASS", 12, 12, &umr_bitfield_default },
	 { "GROUP_13_RT_CLASS", 13, 13, &umr_bitfield_default },
	 { "GROUP_14_RT_CLASS", 14, 14, &umr_bitfield_default },
	 { "GROUP_15_RT_CLASS", 15, 15, &umr_bitfield_default },
	 { "GROUP_16_RT_CLASS", 16, 16, &umr_bitfield_default },
	 { "GROUP_17_RT_CLASS", 17, 17, &umr_bitfield_default },
	 { "GROUP_18_RT_CLASS", 18, 18, &umr_bitfield_default },
	 { "GROUP_19_RT_CLASS", 19, 19, &umr_bitfield_default },
	 { "GROUP_20_RT_CLASS", 20, 20, &umr_bitfield_default },
	 { "GROUP_21_RT_CLASS", 21, 21, &umr_bitfield_default },
	 { "GROUP_22_RT_CLASS", 22, 22, &umr_bitfield_default },
	 { "GROUP_23_RT_CLASS", 23, 23, &umr_bitfield_default },
	 { "GROUP_24_RT_CLASS", 24, 24, &umr_bitfield_default },
	 { "GROUP_25_RT_CLASS", 25, 25, &umr_bitfield_default },
	 { "GROUP_26_RT_CLASS", 26, 26, &umr_bitfield_default },
	 { "GROUP_27_RT_CLASS", 27, 27, &umr_bitfield_default },
	 { "GROUP_28_RT_CLASS", 28, 28, &umr_bitfield_default },
	 { "GROUP_29_RT_CLASS", 29, 29, &umr_bitfield_default },
	 { "GROUP_30_RT_CLASS", 30, 30, &umr_bitfield_default },
	 { "GROUP_31_RT_CLASS", 31, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmVM_L2_BANK_SELECT_RESERVED_CID[] = {
	 { "RESERVED_READ_CLIENT_ID", 0, 8, &umr_bitfield_default },
	 { "RESERVED_WRITE_CLIENT_ID", 10, 18, &umr_bitfield_default },
	 { "ENABLE", 20, 20, &umr_bitfield_default },
	 { "RESERVED_CACHE_INVALIDATION_MODE", 24, 24, &umr_bitfield_default },
	 { "RESERVED_CACHE_PRIVATE_INVALIDATION", 25, 25, &umr_bitfield_default },
};
static struct umr_bitfield mmVM_L2_BANK_SELECT_RESERVED_CID2[] = {
	 { "RESERVED_READ_CLIENT_ID", 0, 8, &umr_bitfield_default },
	 { "RESERVED_WRITE_CLIENT_ID", 10, 18, &umr_bitfield_default },
	 { "ENABLE", 20, 20, &umr_bitfield_default },
	 { "RESERVED_CACHE_INVALIDATION_MODE", 24, 24, &umr_bitfield_default },
	 { "RESERVED_CACHE_PRIVATE_INVALIDATION", 25, 25, &umr_bitfield_default },
};
static struct umr_bitfield mmVM_L2_CACHE_PARITY_CNTL[] = {
	 { "ENABLE_PARITY_CHECKS_IN_4K_PTE_CACHES", 0, 0, &umr_bitfield_default },
	 { "ENABLE_PARITY_CHECKS_IN_BIGK_PTE_CACHES", 1, 1, &umr_bitfield_default },
	 { "ENABLE_PARITY_CHECKS_IN_PDE_CACHES", 2, 2, &umr_bitfield_default },
	 { "FORCE_PARITY_MISMATCH_IN_4K_PTE_CACHE", 3, 3, &umr_bitfield_default },
	 { "FORCE_PARITY_MISMATCH_IN_BIGK_PTE_CACHE", 4, 4, &umr_bitfield_default },
	 { "FORCE_PARITY_MISMATCH_IN_PDE_CACHE", 5, 5, &umr_bitfield_default },
	 { "FORCE_CACHE_BANK", 6, 8, &umr_bitfield_default },
	 { "FORCE_CACHE_NUMBER", 9, 11, &umr_bitfield_default },
	 { "FORCE_CACHE_ASSOC", 12, 15, &umr_bitfield_default },
};
static struct umr_bitfield mmVM_L2_CGTT_CLK_CTRL[] = {
	 { "ON_DELAY", 0, 3, &umr_bitfield_default },
	 { "OFF_HYSTERESIS", 4, 11, &umr_bitfield_default },
	 { "MGLS_OVERRIDE", 15, 15, &umr_bitfield_default },
	 { "SOFT_STALL_OVERRIDE", 16, 23, &umr_bitfield_default },
	 { "SOFT_OVERRIDE", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmVM_CONTEXT0_CNTL[] = {
	 { "ENABLE_CONTEXT", 0, 0, &umr_bitfield_default },
	 { "PAGE_TABLE_DEPTH", 1, 2, &umr_bitfield_default },
	 { "PAGE_TABLE_BLOCK_SIZE", 3, 6, &umr_bitfield_default },
	 { "RETRY_PERMISSION_OR_INVALID_PAGE_FAULT", 7, 7, &umr_bitfield_default },
	 { "RETRY_OTHER_FAULT", 8, 8, &umr_bitfield_default },
	 { "RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT", 9, 9, &umr_bitfield_default },
	 { "RANGE_PROTECTION_FAULT_ENABLE_DEFAULT", 10, 10, &umr_bitfield_default },
	 { "DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT", 11, 11, &umr_bitfield_default },
	 { "DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT", 12, 12, &umr_bitfield_default },
	 { "PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT", 13, 13, &umr_bitfield_default },
	 { "PDE0_PROTECTION_FAULT_ENABLE_DEFAULT", 14, 14, &umr_bitfield_default },
	 { "VALID_PROTECTION_FAULT_ENABLE_INTERRUPT", 15, 15, &umr_bitfield_default },
	 { "VALID_PROTECTION_FAULT_ENABLE_DEFAULT", 16, 16, &umr_bitfield_default },
	 { "READ_PROTECTION_FAULT_ENABLE_INTERRUPT", 17, 17, &umr_bitfield_default },
	 { "READ_PROTECTION_FAULT_ENABLE_DEFAULT", 18, 18, &umr_bitfield_default },
	 { "WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT", 19, 19, &umr_bitfield_default },
	 { "WRITE_PROTECTION_FAULT_ENABLE_DEFAULT", 20, 20, &umr_bitfield_default },
	 { "EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT", 21, 21, &umr_bitfield_default },
	 { "EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT", 22, 22, &umr_bitfield_default },
};
static struct umr_bitfield mmVM_CONTEXT1_CNTL[] = {
	 { "ENABLE_CONTEXT", 0, 0, &umr_bitfield_default },
	 { "PAGE_TABLE_DEPTH", 1, 2, &umr_bitfield_default },
	 { "PAGE_TABLE_BLOCK_SIZE", 3, 6, &umr_bitfield_default },
	 { "RETRY_PERMISSION_OR_INVALID_PAGE_FAULT", 7, 7, &umr_bitfield_default },
	 { "RETRY_OTHER_FAULT", 8, 8, &umr_bitfield_default },
	 { "RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT", 9, 9, &umr_bitfield_default },
	 { "RANGE_PROTECTION_FAULT_ENABLE_DEFAULT", 10, 10, &umr_bitfield_default },
	 { "DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT", 11, 11, &umr_bitfield_default },
	 { "DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT", 12, 12, &umr_bitfield_default },
	 { "PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT", 13, 13, &umr_bitfield_default },
	 { "PDE0_PROTECTION_FAULT_ENABLE_DEFAULT", 14, 14, &umr_bitfield_default },
	 { "VALID_PROTECTION_FAULT_ENABLE_INTERRUPT", 15, 15, &umr_bitfield_default },
	 { "VALID_PROTECTION_FAULT_ENABLE_DEFAULT", 16, 16, &umr_bitfield_default },
	 { "READ_PROTECTION_FAULT_ENABLE_INTERRUPT", 17, 17, &umr_bitfield_default },
	 { "READ_PROTECTION_FAULT_ENABLE_DEFAULT", 18, 18, &umr_bitfield_default },
	 { "WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT", 19, 19, &umr_bitfield_default },
	 { "WRITE_PROTECTION_FAULT_ENABLE_DEFAULT", 20, 20, &umr_bitfield_default },
	 { "EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT", 21, 21, &umr_bitfield_default },
	 { "EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT", 22, 22, &umr_bitfield_default },
};
static struct umr_bitfield mmVM_CONTEXT2_CNTL[] = {
	 { "ENABLE_CONTEXT", 0, 0, &umr_bitfield_default },
	 { "PAGE_TABLE_DEPTH", 1, 2, &umr_bitfield_default },
	 { "PAGE_TABLE_BLOCK_SIZE", 3, 6, &umr_bitfield_default },
	 { "RETRY_PERMISSION_OR_INVALID_PAGE_FAULT", 7, 7, &umr_bitfield_default },
	 { "RETRY_OTHER_FAULT", 8, 8, &umr_bitfield_default },
	 { "RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT", 9, 9, &umr_bitfield_default },
	 { "RANGE_PROTECTION_FAULT_ENABLE_DEFAULT", 10, 10, &umr_bitfield_default },
	 { "DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT", 11, 11, &umr_bitfield_default },
	 { "DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT", 12, 12, &umr_bitfield_default },
	 { "PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT", 13, 13, &umr_bitfield_default },
	 { "PDE0_PROTECTION_FAULT_ENABLE_DEFAULT", 14, 14, &umr_bitfield_default },
	 { "VALID_PROTECTION_FAULT_ENABLE_INTERRUPT", 15, 15, &umr_bitfield_default },
	 { "VALID_PROTECTION_FAULT_ENABLE_DEFAULT", 16, 16, &umr_bitfield_default },
	 { "READ_PROTECTION_FAULT_ENABLE_INTERRUPT", 17, 17, &umr_bitfield_default },
	 { "READ_PROTECTION_FAULT_ENABLE_DEFAULT", 18, 18, &umr_bitfield_default },
	 { "WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT", 19, 19, &umr_bitfield_default },
	 { "WRITE_PROTECTION_FAULT_ENABLE_DEFAULT", 20, 20, &umr_bitfield_default },
	 { "EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT", 21, 21, &umr_bitfield_default },
	 { "EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT", 22, 22, &umr_bitfield_default },
};
static struct umr_bitfield mmVM_CONTEXT3_CNTL[] = {
	 { "ENABLE_CONTEXT", 0, 0, &umr_bitfield_default },
	 { "PAGE_TABLE_DEPTH", 1, 2, &umr_bitfield_default },
	 { "PAGE_TABLE_BLOCK_SIZE", 3, 6, &umr_bitfield_default },
	 { "RETRY_PERMISSION_OR_INVALID_PAGE_FAULT", 7, 7, &umr_bitfield_default },
	 { "RETRY_OTHER_FAULT", 8, 8, &umr_bitfield_default },
	 { "RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT", 9, 9, &umr_bitfield_default },
	 { "RANGE_PROTECTION_FAULT_ENABLE_DEFAULT", 10, 10, &umr_bitfield_default },
	 { "DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT", 11, 11, &umr_bitfield_default },
	 { "DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT", 12, 12, &umr_bitfield_default },
	 { "PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT", 13, 13, &umr_bitfield_default },
	 { "PDE0_PROTECTION_FAULT_ENABLE_DEFAULT", 14, 14, &umr_bitfield_default },
	 { "VALID_PROTECTION_FAULT_ENABLE_INTERRUPT", 15, 15, &umr_bitfield_default },
	 { "VALID_PROTECTION_FAULT_ENABLE_DEFAULT", 16, 16, &umr_bitfield_default },
	 { "READ_PROTECTION_FAULT_ENABLE_INTERRUPT", 17, 17, &umr_bitfield_default },
	 { "READ_PROTECTION_FAULT_ENABLE_DEFAULT", 18, 18, &umr_bitfield_default },
	 { "WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT", 19, 19, &umr_bitfield_default },
	 { "WRITE_PROTECTION_FAULT_ENABLE_DEFAULT", 20, 20, &umr_bitfield_default },
	 { "EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT", 21, 21, &umr_bitfield_default },
	 { "EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT", 22, 22, &umr_bitfield_default },
};
static struct umr_bitfield mmVM_CONTEXT4_CNTL[] = {
	 { "ENABLE_CONTEXT", 0, 0, &umr_bitfield_default },
	 { "PAGE_TABLE_DEPTH", 1, 2, &umr_bitfield_default },
	 { "PAGE_TABLE_BLOCK_SIZE", 3, 6, &umr_bitfield_default },
	 { "RETRY_PERMISSION_OR_INVALID_PAGE_FAULT", 7, 7, &umr_bitfield_default },
	 { "RETRY_OTHER_FAULT", 8, 8, &umr_bitfield_default },
	 { "RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT", 9, 9, &umr_bitfield_default },
	 { "RANGE_PROTECTION_FAULT_ENABLE_DEFAULT", 10, 10, &umr_bitfield_default },
	 { "DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT", 11, 11, &umr_bitfield_default },
	 { "DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT", 12, 12, &umr_bitfield_default },
	 { "PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT", 13, 13, &umr_bitfield_default },
	 { "PDE0_PROTECTION_FAULT_ENABLE_DEFAULT", 14, 14, &umr_bitfield_default },
	 { "VALID_PROTECTION_FAULT_ENABLE_INTERRUPT", 15, 15, &umr_bitfield_default },
	 { "VALID_PROTECTION_FAULT_ENABLE_DEFAULT", 16, 16, &umr_bitfield_default },
	 { "READ_PROTECTION_FAULT_ENABLE_INTERRUPT", 17, 17, &umr_bitfield_default },
	 { "READ_PROTECTION_FAULT_ENABLE_DEFAULT", 18, 18, &umr_bitfield_default },
	 { "WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT", 19, 19, &umr_bitfield_default },
	 { "WRITE_PROTECTION_FAULT_ENABLE_DEFAULT", 20, 20, &umr_bitfield_default },
	 { "EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT", 21, 21, &umr_bitfield_default },
	 { "EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT", 22, 22, &umr_bitfield_default },
};
static struct umr_bitfield mmVM_CONTEXT5_CNTL[] = {
	 { "ENABLE_CONTEXT", 0, 0, &umr_bitfield_default },
	 { "PAGE_TABLE_DEPTH", 1, 2, &umr_bitfield_default },
	 { "PAGE_TABLE_BLOCK_SIZE", 3, 6, &umr_bitfield_default },
	 { "RETRY_PERMISSION_OR_INVALID_PAGE_FAULT", 7, 7, &umr_bitfield_default },
	 { "RETRY_OTHER_FAULT", 8, 8, &umr_bitfield_default },
	 { "RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT", 9, 9, &umr_bitfield_default },
	 { "RANGE_PROTECTION_FAULT_ENABLE_DEFAULT", 10, 10, &umr_bitfield_default },
	 { "DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT", 11, 11, &umr_bitfield_default },
	 { "DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT", 12, 12, &umr_bitfield_default },
	 { "PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT", 13, 13, &umr_bitfield_default },
	 { "PDE0_PROTECTION_FAULT_ENABLE_DEFAULT", 14, 14, &umr_bitfield_default },
	 { "VALID_PROTECTION_FAULT_ENABLE_INTERRUPT", 15, 15, &umr_bitfield_default },
	 { "VALID_PROTECTION_FAULT_ENABLE_DEFAULT", 16, 16, &umr_bitfield_default },
	 { "READ_PROTECTION_FAULT_ENABLE_INTERRUPT", 17, 17, &umr_bitfield_default },
	 { "READ_PROTECTION_FAULT_ENABLE_DEFAULT", 18, 18, &umr_bitfield_default },
	 { "WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT", 19, 19, &umr_bitfield_default },
	 { "WRITE_PROTECTION_FAULT_ENABLE_DEFAULT", 20, 20, &umr_bitfield_default },
	 { "EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT", 21, 21, &umr_bitfield_default },
	 { "EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT", 22, 22, &umr_bitfield_default },
};
static struct umr_bitfield mmVM_CONTEXT6_CNTL[] = {
	 { "ENABLE_CONTEXT", 0, 0, &umr_bitfield_default },
	 { "PAGE_TABLE_DEPTH", 1, 2, &umr_bitfield_default },
	 { "PAGE_TABLE_BLOCK_SIZE", 3, 6, &umr_bitfield_default },
	 { "RETRY_PERMISSION_OR_INVALID_PAGE_FAULT", 7, 7, &umr_bitfield_default },
	 { "RETRY_OTHER_FAULT", 8, 8, &umr_bitfield_default },
	 { "RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT", 9, 9, &umr_bitfield_default },
	 { "RANGE_PROTECTION_FAULT_ENABLE_DEFAULT", 10, 10, &umr_bitfield_default },
	 { "DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT", 11, 11, &umr_bitfield_default },
	 { "DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT", 12, 12, &umr_bitfield_default },
	 { "PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT", 13, 13, &umr_bitfield_default },
	 { "PDE0_PROTECTION_FAULT_ENABLE_DEFAULT", 14, 14, &umr_bitfield_default },
	 { "VALID_PROTECTION_FAULT_ENABLE_INTERRUPT", 15, 15, &umr_bitfield_default },
	 { "VALID_PROTECTION_FAULT_ENABLE_DEFAULT", 16, 16, &umr_bitfield_default },
	 { "READ_PROTECTION_FAULT_ENABLE_INTERRUPT", 17, 17, &umr_bitfield_default },
	 { "READ_PROTECTION_FAULT_ENABLE_DEFAULT", 18, 18, &umr_bitfield_default },
	 { "WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT", 19, 19, &umr_bitfield_default },
	 { "WRITE_PROTECTION_FAULT_ENABLE_DEFAULT", 20, 20, &umr_bitfield_default },
	 { "EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT", 21, 21, &umr_bitfield_default },
	 { "EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT", 22, 22, &umr_bitfield_default },
};
static struct umr_bitfield mmVM_CONTEXT7_CNTL[] = {
	 { "ENABLE_CONTEXT", 0, 0, &umr_bitfield_default },
	 { "PAGE_TABLE_DEPTH", 1, 2, &umr_bitfield_default },
	 { "PAGE_TABLE_BLOCK_SIZE", 3, 6, &umr_bitfield_default },
	 { "RETRY_PERMISSION_OR_INVALID_PAGE_FAULT", 7, 7, &umr_bitfield_default },
	 { "RETRY_OTHER_FAULT", 8, 8, &umr_bitfield_default },
	 { "RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT", 9, 9, &umr_bitfield_default },
	 { "RANGE_PROTECTION_FAULT_ENABLE_DEFAULT", 10, 10, &umr_bitfield_default },
	 { "DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT", 11, 11, &umr_bitfield_default },
	 { "DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT", 12, 12, &umr_bitfield_default },
	 { "PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT", 13, 13, &umr_bitfield_default },
	 { "PDE0_PROTECTION_FAULT_ENABLE_DEFAULT", 14, 14, &umr_bitfield_default },
	 { "VALID_PROTECTION_FAULT_ENABLE_INTERRUPT", 15, 15, &umr_bitfield_default },
	 { "VALID_PROTECTION_FAULT_ENABLE_DEFAULT", 16, 16, &umr_bitfield_default },
	 { "READ_PROTECTION_FAULT_ENABLE_INTERRUPT", 17, 17, &umr_bitfield_default },
	 { "READ_PROTECTION_FAULT_ENABLE_DEFAULT", 18, 18, &umr_bitfield_default },
	 { "WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT", 19, 19, &umr_bitfield_default },
	 { "WRITE_PROTECTION_FAULT_ENABLE_DEFAULT", 20, 20, &umr_bitfield_default },
	 { "EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT", 21, 21, &umr_bitfield_default },
	 { "EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT", 22, 22, &umr_bitfield_default },
};
static struct umr_bitfield mmVM_CONTEXT8_CNTL[] = {
	 { "ENABLE_CONTEXT", 0, 0, &umr_bitfield_default },
	 { "PAGE_TABLE_DEPTH", 1, 2, &umr_bitfield_default },
	 { "PAGE_TABLE_BLOCK_SIZE", 3, 6, &umr_bitfield_default },
	 { "RETRY_PERMISSION_OR_INVALID_PAGE_FAULT", 7, 7, &umr_bitfield_default },
	 { "RETRY_OTHER_FAULT", 8, 8, &umr_bitfield_default },
	 { "RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT", 9, 9, &umr_bitfield_default },
	 { "RANGE_PROTECTION_FAULT_ENABLE_DEFAULT", 10, 10, &umr_bitfield_default },
	 { "DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT", 11, 11, &umr_bitfield_default },
	 { "DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT", 12, 12, &umr_bitfield_default },
	 { "PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT", 13, 13, &umr_bitfield_default },
	 { "PDE0_PROTECTION_FAULT_ENABLE_DEFAULT", 14, 14, &umr_bitfield_default },
	 { "VALID_PROTECTION_FAULT_ENABLE_INTERRUPT", 15, 15, &umr_bitfield_default },
	 { "VALID_PROTECTION_FAULT_ENABLE_DEFAULT", 16, 16, &umr_bitfield_default },
	 { "READ_PROTECTION_FAULT_ENABLE_INTERRUPT", 17, 17, &umr_bitfield_default },
	 { "READ_PROTECTION_FAULT_ENABLE_DEFAULT", 18, 18, &umr_bitfield_default },
	 { "WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT", 19, 19, &umr_bitfield_default },
	 { "WRITE_PROTECTION_FAULT_ENABLE_DEFAULT", 20, 20, &umr_bitfield_default },
	 { "EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT", 21, 21, &umr_bitfield_default },
	 { "EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT", 22, 22, &umr_bitfield_default },
};
static struct umr_bitfield mmVM_CONTEXT9_CNTL[] = {
	 { "ENABLE_CONTEXT", 0, 0, &umr_bitfield_default },
	 { "PAGE_TABLE_DEPTH", 1, 2, &umr_bitfield_default },
	 { "PAGE_TABLE_BLOCK_SIZE", 3, 6, &umr_bitfield_default },
	 { "RETRY_PERMISSION_OR_INVALID_PAGE_FAULT", 7, 7, &umr_bitfield_default },
	 { "RETRY_OTHER_FAULT", 8, 8, &umr_bitfield_default },
	 { "RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT", 9, 9, &umr_bitfield_default },
	 { "RANGE_PROTECTION_FAULT_ENABLE_DEFAULT", 10, 10, &umr_bitfield_default },
	 { "DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT", 11, 11, &umr_bitfield_default },
	 { "DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT", 12, 12, &umr_bitfield_default },
	 { "PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT", 13, 13, &umr_bitfield_default },
	 { "PDE0_PROTECTION_FAULT_ENABLE_DEFAULT", 14, 14, &umr_bitfield_default },
	 { "VALID_PROTECTION_FAULT_ENABLE_INTERRUPT", 15, 15, &umr_bitfield_default },
	 { "VALID_PROTECTION_FAULT_ENABLE_DEFAULT", 16, 16, &umr_bitfield_default },
	 { "READ_PROTECTION_FAULT_ENABLE_INTERRUPT", 17, 17, &umr_bitfield_default },
	 { "READ_PROTECTION_FAULT_ENABLE_DEFAULT", 18, 18, &umr_bitfield_default },
	 { "WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT", 19, 19, &umr_bitfield_default },
	 { "WRITE_PROTECTION_FAULT_ENABLE_DEFAULT", 20, 20, &umr_bitfield_default },
	 { "EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT", 21, 21, &umr_bitfield_default },
	 { "EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT", 22, 22, &umr_bitfield_default },
};
static struct umr_bitfield mmVM_CONTEXT10_CNTL[] = {
	 { "ENABLE_CONTEXT", 0, 0, &umr_bitfield_default },
	 { "PAGE_TABLE_DEPTH", 1, 2, &umr_bitfield_default },
	 { "PAGE_TABLE_BLOCK_SIZE", 3, 6, &umr_bitfield_default },
	 { "RETRY_PERMISSION_OR_INVALID_PAGE_FAULT", 7, 7, &umr_bitfield_default },
	 { "RETRY_OTHER_FAULT", 8, 8, &umr_bitfield_default },
	 { "RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT", 9, 9, &umr_bitfield_default },
	 { "RANGE_PROTECTION_FAULT_ENABLE_DEFAULT", 10, 10, &umr_bitfield_default },
	 { "DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT", 11, 11, &umr_bitfield_default },
	 { "DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT", 12, 12, &umr_bitfield_default },
	 { "PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT", 13, 13, &umr_bitfield_default },
	 { "PDE0_PROTECTION_FAULT_ENABLE_DEFAULT", 14, 14, &umr_bitfield_default },
	 { "VALID_PROTECTION_FAULT_ENABLE_INTERRUPT", 15, 15, &umr_bitfield_default },
	 { "VALID_PROTECTION_FAULT_ENABLE_DEFAULT", 16, 16, &umr_bitfield_default },
	 { "READ_PROTECTION_FAULT_ENABLE_INTERRUPT", 17, 17, &umr_bitfield_default },
	 { "READ_PROTECTION_FAULT_ENABLE_DEFAULT", 18, 18, &umr_bitfield_default },
	 { "WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT", 19, 19, &umr_bitfield_default },
	 { "WRITE_PROTECTION_FAULT_ENABLE_DEFAULT", 20, 20, &umr_bitfield_default },
	 { "EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT", 21, 21, &umr_bitfield_default },
	 { "EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT", 22, 22, &umr_bitfield_default },
};
static struct umr_bitfield mmVM_CONTEXT11_CNTL[] = {
	 { "ENABLE_CONTEXT", 0, 0, &umr_bitfield_default },
	 { "PAGE_TABLE_DEPTH", 1, 2, &umr_bitfield_default },
	 { "PAGE_TABLE_BLOCK_SIZE", 3, 6, &umr_bitfield_default },
	 { "RETRY_PERMISSION_OR_INVALID_PAGE_FAULT", 7, 7, &umr_bitfield_default },
	 { "RETRY_OTHER_FAULT", 8, 8, &umr_bitfield_default },
	 { "RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT", 9, 9, &umr_bitfield_default },
	 { "RANGE_PROTECTION_FAULT_ENABLE_DEFAULT", 10, 10, &umr_bitfield_default },
	 { "DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT", 11, 11, &umr_bitfield_default },
	 { "DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT", 12, 12, &umr_bitfield_default },
	 { "PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT", 13, 13, &umr_bitfield_default },
	 { "PDE0_PROTECTION_FAULT_ENABLE_DEFAULT", 14, 14, &umr_bitfield_default },
	 { "VALID_PROTECTION_FAULT_ENABLE_INTERRUPT", 15, 15, &umr_bitfield_default },
	 { "VALID_PROTECTION_FAULT_ENABLE_DEFAULT", 16, 16, &umr_bitfield_default },
	 { "READ_PROTECTION_FAULT_ENABLE_INTERRUPT", 17, 17, &umr_bitfield_default },
	 { "READ_PROTECTION_FAULT_ENABLE_DEFAULT", 18, 18, &umr_bitfield_default },
	 { "WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT", 19, 19, &umr_bitfield_default },
	 { "WRITE_PROTECTION_FAULT_ENABLE_DEFAULT", 20, 20, &umr_bitfield_default },
	 { "EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT", 21, 21, &umr_bitfield_default },
	 { "EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT", 22, 22, &umr_bitfield_default },
};
static struct umr_bitfield mmVM_CONTEXT12_CNTL[] = {
	 { "ENABLE_CONTEXT", 0, 0, &umr_bitfield_default },
	 { "PAGE_TABLE_DEPTH", 1, 2, &umr_bitfield_default },
	 { "PAGE_TABLE_BLOCK_SIZE", 3, 6, &umr_bitfield_default },
	 { "RETRY_PERMISSION_OR_INVALID_PAGE_FAULT", 7, 7, &umr_bitfield_default },
	 { "RETRY_OTHER_FAULT", 8, 8, &umr_bitfield_default },
	 { "RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT", 9, 9, &umr_bitfield_default },
	 { "RANGE_PROTECTION_FAULT_ENABLE_DEFAULT", 10, 10, &umr_bitfield_default },
	 { "DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT", 11, 11, &umr_bitfield_default },
	 { "DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT", 12, 12, &umr_bitfield_default },
	 { "PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT", 13, 13, &umr_bitfield_default },
	 { "PDE0_PROTECTION_FAULT_ENABLE_DEFAULT", 14, 14, &umr_bitfield_default },
	 { "VALID_PROTECTION_FAULT_ENABLE_INTERRUPT", 15, 15, &umr_bitfield_default },
	 { "VALID_PROTECTION_FAULT_ENABLE_DEFAULT", 16, 16, &umr_bitfield_default },
	 { "READ_PROTECTION_FAULT_ENABLE_INTERRUPT", 17, 17, &umr_bitfield_default },
	 { "READ_PROTECTION_FAULT_ENABLE_DEFAULT", 18, 18, &umr_bitfield_default },
	 { "WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT", 19, 19, &umr_bitfield_default },
	 { "WRITE_PROTECTION_FAULT_ENABLE_DEFAULT", 20, 20, &umr_bitfield_default },
	 { "EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT", 21, 21, &umr_bitfield_default },
	 { "EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT", 22, 22, &umr_bitfield_default },
};
static struct umr_bitfield mmVM_CONTEXT13_CNTL[] = {
	 { "ENABLE_CONTEXT", 0, 0, &umr_bitfield_default },
	 { "PAGE_TABLE_DEPTH", 1, 2, &umr_bitfield_default },
	 { "PAGE_TABLE_BLOCK_SIZE", 3, 6, &umr_bitfield_default },
	 { "RETRY_PERMISSION_OR_INVALID_PAGE_FAULT", 7, 7, &umr_bitfield_default },
	 { "RETRY_OTHER_FAULT", 8, 8, &umr_bitfield_default },
	 { "RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT", 9, 9, &umr_bitfield_default },
	 { "RANGE_PROTECTION_FAULT_ENABLE_DEFAULT", 10, 10, &umr_bitfield_default },
	 { "DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT", 11, 11, &umr_bitfield_default },
	 { "DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT", 12, 12, &umr_bitfield_default },
	 { "PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT", 13, 13, &umr_bitfield_default },
	 { "PDE0_PROTECTION_FAULT_ENABLE_DEFAULT", 14, 14, &umr_bitfield_default },
	 { "VALID_PROTECTION_FAULT_ENABLE_INTERRUPT", 15, 15, &umr_bitfield_default },
	 { "VALID_PROTECTION_FAULT_ENABLE_DEFAULT", 16, 16, &umr_bitfield_default },
	 { "READ_PROTECTION_FAULT_ENABLE_INTERRUPT", 17, 17, &umr_bitfield_default },
	 { "READ_PROTECTION_FAULT_ENABLE_DEFAULT", 18, 18, &umr_bitfield_default },
	 { "WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT", 19, 19, &umr_bitfield_default },
	 { "WRITE_PROTECTION_FAULT_ENABLE_DEFAULT", 20, 20, &umr_bitfield_default },
	 { "EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT", 21, 21, &umr_bitfield_default },
	 { "EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT", 22, 22, &umr_bitfield_default },
};
static struct umr_bitfield mmVM_CONTEXT14_CNTL[] = {
	 { "ENABLE_CONTEXT", 0, 0, &umr_bitfield_default },
	 { "PAGE_TABLE_DEPTH", 1, 2, &umr_bitfield_default },
	 { "PAGE_TABLE_BLOCK_SIZE", 3, 6, &umr_bitfield_default },
	 { "RETRY_PERMISSION_OR_INVALID_PAGE_FAULT", 7, 7, &umr_bitfield_default },
	 { "RETRY_OTHER_FAULT", 8, 8, &umr_bitfield_default },
	 { "RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT", 9, 9, &umr_bitfield_default },
	 { "RANGE_PROTECTION_FAULT_ENABLE_DEFAULT", 10, 10, &umr_bitfield_default },
	 { "DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT", 11, 11, &umr_bitfield_default },
	 { "DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT", 12, 12, &umr_bitfield_default },
	 { "PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT", 13, 13, &umr_bitfield_default },
	 { "PDE0_PROTECTION_FAULT_ENABLE_DEFAULT", 14, 14, &umr_bitfield_default },
	 { "VALID_PROTECTION_FAULT_ENABLE_INTERRUPT", 15, 15, &umr_bitfield_default },
	 { "VALID_PROTECTION_FAULT_ENABLE_DEFAULT", 16, 16, &umr_bitfield_default },
	 { "READ_PROTECTION_FAULT_ENABLE_INTERRUPT", 17, 17, &umr_bitfield_default },
	 { "READ_PROTECTION_FAULT_ENABLE_DEFAULT", 18, 18, &umr_bitfield_default },
	 { "WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT", 19, 19, &umr_bitfield_default },
	 { "WRITE_PROTECTION_FAULT_ENABLE_DEFAULT", 20, 20, &umr_bitfield_default },
	 { "EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT", 21, 21, &umr_bitfield_default },
	 { "EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT", 22, 22, &umr_bitfield_default },
};
static struct umr_bitfield mmVM_CONTEXT15_CNTL[] = {
	 { "ENABLE_CONTEXT", 0, 0, &umr_bitfield_default },
	 { "PAGE_TABLE_DEPTH", 1, 2, &umr_bitfield_default },
	 { "PAGE_TABLE_BLOCK_SIZE", 3, 6, &umr_bitfield_default },
	 { "RETRY_PERMISSION_OR_INVALID_PAGE_FAULT", 7, 7, &umr_bitfield_default },
	 { "RETRY_OTHER_FAULT", 8, 8, &umr_bitfield_default },
	 { "RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT", 9, 9, &umr_bitfield_default },
	 { "RANGE_PROTECTION_FAULT_ENABLE_DEFAULT", 10, 10, &umr_bitfield_default },
	 { "DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT", 11, 11, &umr_bitfield_default },
	 { "DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT", 12, 12, &umr_bitfield_default },
	 { "PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT", 13, 13, &umr_bitfield_default },
	 { "PDE0_PROTECTION_FAULT_ENABLE_DEFAULT", 14, 14, &umr_bitfield_default },
	 { "VALID_PROTECTION_FAULT_ENABLE_INTERRUPT", 15, 15, &umr_bitfield_default },
	 { "VALID_PROTECTION_FAULT_ENABLE_DEFAULT", 16, 16, &umr_bitfield_default },
	 { "READ_PROTECTION_FAULT_ENABLE_INTERRUPT", 17, 17, &umr_bitfield_default },
	 { "READ_PROTECTION_FAULT_ENABLE_DEFAULT", 18, 18, &umr_bitfield_default },
	 { "WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT", 19, 19, &umr_bitfield_default },
	 { "WRITE_PROTECTION_FAULT_ENABLE_DEFAULT", 20, 20, &umr_bitfield_default },
	 { "EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT", 21, 21, &umr_bitfield_default },
	 { "EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT", 22, 22, &umr_bitfield_default },
};
static struct umr_bitfield mmVM_CONTEXTS_DISABLE[] = {
	 { "DISABLE_CONTEXT_0", 0, 0, &umr_bitfield_default },
	 { "DISABLE_CONTEXT_1", 1, 1, &umr_bitfield_default },
	 { "DISABLE_CONTEXT_2", 2, 2, &umr_bitfield_default },
	 { "DISABLE_CONTEXT_3", 3, 3, &umr_bitfield_default },
	 { "DISABLE_CONTEXT_4", 4, 4, &umr_bitfield_default },
	 { "DISABLE_CONTEXT_5", 5, 5, &umr_bitfield_default },
	 { "DISABLE_CONTEXT_6", 6, 6, &umr_bitfield_default },
	 { "DISABLE_CONTEXT_7", 7, 7, &umr_bitfield_default },
	 { "DISABLE_CONTEXT_8", 8, 8, &umr_bitfield_default },
	 { "DISABLE_CONTEXT_9", 9, 9, &umr_bitfield_default },
	 { "DISABLE_CONTEXT_10", 10, 10, &umr_bitfield_default },
	 { "DISABLE_CONTEXT_11", 11, 11, &umr_bitfield_default },
	 { "DISABLE_CONTEXT_12", 12, 12, &umr_bitfield_default },
	 { "DISABLE_CONTEXT_13", 13, 13, &umr_bitfield_default },
	 { "DISABLE_CONTEXT_14", 14, 14, &umr_bitfield_default },
	 { "DISABLE_CONTEXT_15", 15, 15, &umr_bitfield_default },
};
static struct umr_bitfield mmVM_INVALIDATE_ENG0_SEM[] = {
	 { "SEMAPHORE", 0, 0, &umr_bitfield_default },
};
static struct umr_bitfield mmVM_INVALIDATE_ENG1_SEM[] = {
	 { "SEMAPHORE", 0, 0, &umr_bitfield_default },
};
static struct umr_bitfield mmVM_INVALIDATE_ENG2_SEM[] = {
	 { "SEMAPHORE", 0, 0, &umr_bitfield_default },
};
static struct umr_bitfield mmVM_INVALIDATE_ENG3_SEM[] = {
	 { "SEMAPHORE", 0, 0, &umr_bitfield_default },
};
static struct umr_bitfield mmVM_INVALIDATE_ENG4_SEM[] = {
	 { "SEMAPHORE", 0, 0, &umr_bitfield_default },
};
static struct umr_bitfield mmVM_INVALIDATE_ENG5_SEM[] = {
	 { "SEMAPHORE", 0, 0, &umr_bitfield_default },
};
static struct umr_bitfield mmVM_INVALIDATE_ENG6_SEM[] = {
	 { "SEMAPHORE", 0, 0, &umr_bitfield_default },
};
static struct umr_bitfield mmVM_INVALIDATE_ENG7_SEM[] = {
	 { "SEMAPHORE", 0, 0, &umr_bitfield_default },
};
static struct umr_bitfield mmVM_INVALIDATE_ENG8_SEM[] = {
	 { "SEMAPHORE", 0, 0, &umr_bitfield_default },
};
static struct umr_bitfield mmVM_INVALIDATE_ENG9_SEM[] = {
	 { "SEMAPHORE", 0, 0, &umr_bitfield_default },
};
static struct umr_bitfield mmVM_INVALIDATE_ENG10_SEM[] = {
	 { "SEMAPHORE", 0, 0, &umr_bitfield_default },
};
static struct umr_bitfield mmVM_INVALIDATE_ENG11_SEM[] = {
	 { "SEMAPHORE", 0, 0, &umr_bitfield_default },
};
static struct umr_bitfield mmVM_INVALIDATE_ENG12_SEM[] = {
	 { "SEMAPHORE", 0, 0, &umr_bitfield_default },
};
static struct umr_bitfield mmVM_INVALIDATE_ENG13_SEM[] = {
	 { "SEMAPHORE", 0, 0, &umr_bitfield_default },
};
static struct umr_bitfield mmVM_INVALIDATE_ENG14_SEM[] = {
	 { "SEMAPHORE", 0, 0, &umr_bitfield_default },
};
static struct umr_bitfield mmVM_INVALIDATE_ENG15_SEM[] = {
	 { "SEMAPHORE", 0, 0, &umr_bitfield_default },
};
static struct umr_bitfield mmVM_INVALIDATE_ENG16_SEM[] = {
	 { "SEMAPHORE", 0, 0, &umr_bitfield_default },
};
static struct umr_bitfield mmVM_INVALIDATE_ENG17_SEM[] = {
	 { "SEMAPHORE", 0, 0, &umr_bitfield_default },
};
static struct umr_bitfield mmVM_INVALIDATE_ENG0_REQ[] = {
	 { "PER_VMID_INVALIDATE_REQ", 0, 15, &umr_bitfield_default },
	 { "FLUSH_TYPE", 16, 17, &umr_bitfield_default },
	 { "INVALIDATE_L2_PTES", 18, 18, &umr_bitfield_default },
	 { "INVALIDATE_L2_PDE0", 19, 19, &umr_bitfield_default },
	 { "INVALIDATE_L2_PDE1", 20, 20, &umr_bitfield_default },
	 { "INVALIDATE_L2_PDE2", 21, 21, &umr_bitfield_default },
	 { "INVALIDATE_L1_PTES", 22, 22, &umr_bitfield_default },
	 { "CLEAR_PROTECTION_FAULT_STATUS_ADDR", 23, 23, &umr_bitfield_default },
};
static struct umr_bitfield mmVM_INVALIDATE_ENG1_REQ[] = {
	 { "PER_VMID_INVALIDATE_REQ", 0, 15, &umr_bitfield_default },
	 { "FLUSH_TYPE", 16, 17, &umr_bitfield_default },
	 { "INVALIDATE_L2_PTES", 18, 18, &umr_bitfield_default },
	 { "INVALIDATE_L2_PDE0", 19, 19, &umr_bitfield_default },
	 { "INVALIDATE_L2_PDE1", 20, 20, &umr_bitfield_default },
	 { "INVALIDATE_L2_PDE2", 21, 21, &umr_bitfield_default },
	 { "INVALIDATE_L1_PTES", 22, 22, &umr_bitfield_default },
	 { "CLEAR_PROTECTION_FAULT_STATUS_ADDR", 23, 23, &umr_bitfield_default },
};
static struct umr_bitfield mmVM_INVALIDATE_ENG2_REQ[] = {
	 { "PER_VMID_INVALIDATE_REQ", 0, 15, &umr_bitfield_default },
	 { "FLUSH_TYPE", 16, 17, &umr_bitfield_default },
	 { "INVALIDATE_L2_PTES", 18, 18, &umr_bitfield_default },
	 { "INVALIDATE_L2_PDE0", 19, 19, &umr_bitfield_default },
	 { "INVALIDATE_L2_PDE1", 20, 20, &umr_bitfield_default },
	 { "INVALIDATE_L2_PDE2", 21, 21, &umr_bitfield_default },
	 { "INVALIDATE_L1_PTES", 22, 22, &umr_bitfield_default },
	 { "CLEAR_PROTECTION_FAULT_STATUS_ADDR", 23, 23, &umr_bitfield_default },
};
static struct umr_bitfield mmVM_INVALIDATE_ENG3_REQ[] = {
	 { "PER_VMID_INVALIDATE_REQ", 0, 15, &umr_bitfield_default },
	 { "FLUSH_TYPE", 16, 17, &umr_bitfield_default },
	 { "INVALIDATE_L2_PTES", 18, 18, &umr_bitfield_default },
	 { "INVALIDATE_L2_PDE0", 19, 19, &umr_bitfield_default },
	 { "INVALIDATE_L2_PDE1", 20, 20, &umr_bitfield_default },
	 { "INVALIDATE_L2_PDE2", 21, 21, &umr_bitfield_default },
	 { "INVALIDATE_L1_PTES", 22, 22, &umr_bitfield_default },
	 { "CLEAR_PROTECTION_FAULT_STATUS_ADDR", 23, 23, &umr_bitfield_default },
};
static struct umr_bitfield mmVM_INVALIDATE_ENG4_REQ[] = {
	 { "PER_VMID_INVALIDATE_REQ", 0, 15, &umr_bitfield_default },
	 { "FLUSH_TYPE", 16, 17, &umr_bitfield_default },
	 { "INVALIDATE_L2_PTES", 18, 18, &umr_bitfield_default },
	 { "INVALIDATE_L2_PDE0", 19, 19, &umr_bitfield_default },
	 { "INVALIDATE_L2_PDE1", 20, 20, &umr_bitfield_default },
	 { "INVALIDATE_L2_PDE2", 21, 21, &umr_bitfield_default },
	 { "INVALIDATE_L1_PTES", 22, 22, &umr_bitfield_default },
	 { "CLEAR_PROTECTION_FAULT_STATUS_ADDR", 23, 23, &umr_bitfield_default },
};
static struct umr_bitfield mmVM_INVALIDATE_ENG5_REQ[] = {
	 { "PER_VMID_INVALIDATE_REQ", 0, 15, &umr_bitfield_default },
	 { "FLUSH_TYPE", 16, 17, &umr_bitfield_default },
	 { "INVALIDATE_L2_PTES", 18, 18, &umr_bitfield_default },
	 { "INVALIDATE_L2_PDE0", 19, 19, &umr_bitfield_default },
	 { "INVALIDATE_L2_PDE1", 20, 20, &umr_bitfield_default },
	 { "INVALIDATE_L2_PDE2", 21, 21, &umr_bitfield_default },
	 { "INVALIDATE_L1_PTES", 22, 22, &umr_bitfield_default },
	 { "CLEAR_PROTECTION_FAULT_STATUS_ADDR", 23, 23, &umr_bitfield_default },
};
static struct umr_bitfield mmVM_INVALIDATE_ENG6_REQ[] = {
	 { "PER_VMID_INVALIDATE_REQ", 0, 15, &umr_bitfield_default },
	 { "FLUSH_TYPE", 16, 17, &umr_bitfield_default },
	 { "INVALIDATE_L2_PTES", 18, 18, &umr_bitfield_default },
	 { "INVALIDATE_L2_PDE0", 19, 19, &umr_bitfield_default },
	 { "INVALIDATE_L2_PDE1", 20, 20, &umr_bitfield_default },
	 { "INVALIDATE_L2_PDE2", 21, 21, &umr_bitfield_default },
	 { "INVALIDATE_L1_PTES", 22, 22, &umr_bitfield_default },
	 { "CLEAR_PROTECTION_FAULT_STATUS_ADDR", 23, 23, &umr_bitfield_default },
};
static struct umr_bitfield mmVM_INVALIDATE_ENG7_REQ[] = {
	 { "PER_VMID_INVALIDATE_REQ", 0, 15, &umr_bitfield_default },
	 { "FLUSH_TYPE", 16, 17, &umr_bitfield_default },
	 { "INVALIDATE_L2_PTES", 18, 18, &umr_bitfield_default },
	 { "INVALIDATE_L2_PDE0", 19, 19, &umr_bitfield_default },
	 { "INVALIDATE_L2_PDE1", 20, 20, &umr_bitfield_default },
	 { "INVALIDATE_L2_PDE2", 21, 21, &umr_bitfield_default },
	 { "INVALIDATE_L1_PTES", 22, 22, &umr_bitfield_default },
	 { "CLEAR_PROTECTION_FAULT_STATUS_ADDR", 23, 23, &umr_bitfield_default },
};
static struct umr_bitfield mmVM_INVALIDATE_ENG8_REQ[] = {
	 { "PER_VMID_INVALIDATE_REQ", 0, 15, &umr_bitfield_default },
	 { "FLUSH_TYPE", 16, 17, &umr_bitfield_default },
	 { "INVALIDATE_L2_PTES", 18, 18, &umr_bitfield_default },
	 { "INVALIDATE_L2_PDE0", 19, 19, &umr_bitfield_default },
	 { "INVALIDATE_L2_PDE1", 20, 20, &umr_bitfield_default },
	 { "INVALIDATE_L2_PDE2", 21, 21, &umr_bitfield_default },
	 { "INVALIDATE_L1_PTES", 22, 22, &umr_bitfield_default },
	 { "CLEAR_PROTECTION_FAULT_STATUS_ADDR", 23, 23, &umr_bitfield_default },
};
static struct umr_bitfield mmVM_INVALIDATE_ENG9_REQ[] = {
	 { "PER_VMID_INVALIDATE_REQ", 0, 15, &umr_bitfield_default },
	 { "FLUSH_TYPE", 16, 17, &umr_bitfield_default },
	 { "INVALIDATE_L2_PTES", 18, 18, &umr_bitfield_default },
	 { "INVALIDATE_L2_PDE0", 19, 19, &umr_bitfield_default },
	 { "INVALIDATE_L2_PDE1", 20, 20, &umr_bitfield_default },
	 { "INVALIDATE_L2_PDE2", 21, 21, &umr_bitfield_default },
	 { "INVALIDATE_L1_PTES", 22, 22, &umr_bitfield_default },
	 { "CLEAR_PROTECTION_FAULT_STATUS_ADDR", 23, 23, &umr_bitfield_default },
};
static struct umr_bitfield mmVM_INVALIDATE_ENG10_REQ[] = {
	 { "PER_VMID_INVALIDATE_REQ", 0, 15, &umr_bitfield_default },
	 { "FLUSH_TYPE", 16, 17, &umr_bitfield_default },
	 { "INVALIDATE_L2_PTES", 18, 18, &umr_bitfield_default },
	 { "INVALIDATE_L2_PDE0", 19, 19, &umr_bitfield_default },
	 { "INVALIDATE_L2_PDE1", 20, 20, &umr_bitfield_default },
	 { "INVALIDATE_L2_PDE2", 21, 21, &umr_bitfield_default },
	 { "INVALIDATE_L1_PTES", 22, 22, &umr_bitfield_default },
	 { "CLEAR_PROTECTION_FAULT_STATUS_ADDR", 23, 23, &umr_bitfield_default },
};
static struct umr_bitfield mmVM_INVALIDATE_ENG11_REQ[] = {
	 { "PER_VMID_INVALIDATE_REQ", 0, 15, &umr_bitfield_default },
	 { "FLUSH_TYPE", 16, 17, &umr_bitfield_default },
	 { "INVALIDATE_L2_PTES", 18, 18, &umr_bitfield_default },
	 { "INVALIDATE_L2_PDE0", 19, 19, &umr_bitfield_default },
	 { "INVALIDATE_L2_PDE1", 20, 20, &umr_bitfield_default },
	 { "INVALIDATE_L2_PDE2", 21, 21, &umr_bitfield_default },
	 { "INVALIDATE_L1_PTES", 22, 22, &umr_bitfield_default },
	 { "CLEAR_PROTECTION_FAULT_STATUS_ADDR", 23, 23, &umr_bitfield_default },
};
static struct umr_bitfield mmVM_INVALIDATE_ENG12_REQ[] = {
	 { "PER_VMID_INVALIDATE_REQ", 0, 15, &umr_bitfield_default },
	 { "FLUSH_TYPE", 16, 17, &umr_bitfield_default },
	 { "INVALIDATE_L2_PTES", 18, 18, &umr_bitfield_default },
	 { "INVALIDATE_L2_PDE0", 19, 19, &umr_bitfield_default },
	 { "INVALIDATE_L2_PDE1", 20, 20, &umr_bitfield_default },
	 { "INVALIDATE_L2_PDE2", 21, 21, &umr_bitfield_default },
	 { "INVALIDATE_L1_PTES", 22, 22, &umr_bitfield_default },
	 { "CLEAR_PROTECTION_FAULT_STATUS_ADDR", 23, 23, &umr_bitfield_default },
};
static struct umr_bitfield mmVM_INVALIDATE_ENG13_REQ[] = {
	 { "PER_VMID_INVALIDATE_REQ", 0, 15, &umr_bitfield_default },
	 { "FLUSH_TYPE", 16, 17, &umr_bitfield_default },
	 { "INVALIDATE_L2_PTES", 18, 18, &umr_bitfield_default },
	 { "INVALIDATE_L2_PDE0", 19, 19, &umr_bitfield_default },
	 { "INVALIDATE_L2_PDE1", 20, 20, &umr_bitfield_default },
	 { "INVALIDATE_L2_PDE2", 21, 21, &umr_bitfield_default },
	 { "INVALIDATE_L1_PTES", 22, 22, &umr_bitfield_default },
	 { "CLEAR_PROTECTION_FAULT_STATUS_ADDR", 23, 23, &umr_bitfield_default },
};
static struct umr_bitfield mmVM_INVALIDATE_ENG14_REQ[] = {
	 { "PER_VMID_INVALIDATE_REQ", 0, 15, &umr_bitfield_default },
	 { "FLUSH_TYPE", 16, 17, &umr_bitfield_default },
	 { "INVALIDATE_L2_PTES", 18, 18, &umr_bitfield_default },
	 { "INVALIDATE_L2_PDE0", 19, 19, &umr_bitfield_default },
	 { "INVALIDATE_L2_PDE1", 20, 20, &umr_bitfield_default },
	 { "INVALIDATE_L2_PDE2", 21, 21, &umr_bitfield_default },
	 { "INVALIDATE_L1_PTES", 22, 22, &umr_bitfield_default },
	 { "CLEAR_PROTECTION_FAULT_STATUS_ADDR", 23, 23, &umr_bitfield_default },
};
static struct umr_bitfield mmVM_INVALIDATE_ENG15_REQ[] = {
	 { "PER_VMID_INVALIDATE_REQ", 0, 15, &umr_bitfield_default },
	 { "FLUSH_TYPE", 16, 17, &umr_bitfield_default },
	 { "INVALIDATE_L2_PTES", 18, 18, &umr_bitfield_default },
	 { "INVALIDATE_L2_PDE0", 19, 19, &umr_bitfield_default },
	 { "INVALIDATE_L2_PDE1", 20, 20, &umr_bitfield_default },
	 { "INVALIDATE_L2_PDE2", 21, 21, &umr_bitfield_default },
	 { "INVALIDATE_L1_PTES", 22, 22, &umr_bitfield_default },
	 { "CLEAR_PROTECTION_FAULT_STATUS_ADDR", 23, 23, &umr_bitfield_default },
};
static struct umr_bitfield mmVM_INVALIDATE_ENG16_REQ[] = {
	 { "PER_VMID_INVALIDATE_REQ", 0, 15, &umr_bitfield_default },
	 { "FLUSH_TYPE", 16, 17, &umr_bitfield_default },
	 { "INVALIDATE_L2_PTES", 18, 18, &umr_bitfield_default },
	 { "INVALIDATE_L2_PDE0", 19, 19, &umr_bitfield_default },
	 { "INVALIDATE_L2_PDE1", 20, 20, &umr_bitfield_default },
	 { "INVALIDATE_L2_PDE2", 21, 21, &umr_bitfield_default },
	 { "INVALIDATE_L1_PTES", 22, 22, &umr_bitfield_default },
	 { "CLEAR_PROTECTION_FAULT_STATUS_ADDR", 23, 23, &umr_bitfield_default },
};
static struct umr_bitfield mmVM_INVALIDATE_ENG17_REQ[] = {
	 { "PER_VMID_INVALIDATE_REQ", 0, 15, &umr_bitfield_default },
	 { "FLUSH_TYPE", 16, 17, &umr_bitfield_default },
	 { "INVALIDATE_L2_PTES", 18, 18, &umr_bitfield_default },
	 { "INVALIDATE_L2_PDE0", 19, 19, &umr_bitfield_default },
	 { "INVALIDATE_L2_PDE1", 20, 20, &umr_bitfield_default },
	 { "INVALIDATE_L2_PDE2", 21, 21, &umr_bitfield_default },
	 { "INVALIDATE_L1_PTES", 22, 22, &umr_bitfield_default },
	 { "CLEAR_PROTECTION_FAULT_STATUS_ADDR", 23, 23, &umr_bitfield_default },
};
static struct umr_bitfield mmVM_INVALIDATE_ENG0_ACK[] = {
	 { "PER_VMID_INVALIDATE_ACK", 0, 15, &umr_bitfield_default },
	 { "SEMAPHORE", 16, 16, &umr_bitfield_default },
};
static struct umr_bitfield mmVM_INVALIDATE_ENG1_ACK[] = {
	 { "PER_VMID_INVALIDATE_ACK", 0, 15, &umr_bitfield_default },
	 { "SEMAPHORE", 16, 16, &umr_bitfield_default },
};
static struct umr_bitfield mmVM_INVALIDATE_ENG2_ACK[] = {
	 { "PER_VMID_INVALIDATE_ACK", 0, 15, &umr_bitfield_default },
	 { "SEMAPHORE", 16, 16, &umr_bitfield_default },
};
static struct umr_bitfield mmVM_INVALIDATE_ENG3_ACK[] = {
	 { "PER_VMID_INVALIDATE_ACK", 0, 15, &umr_bitfield_default },
	 { "SEMAPHORE", 16, 16, &umr_bitfield_default },
};
static struct umr_bitfield mmVM_INVALIDATE_ENG4_ACK[] = {
	 { "PER_VMID_INVALIDATE_ACK", 0, 15, &umr_bitfield_default },
	 { "SEMAPHORE", 16, 16, &umr_bitfield_default },
};
static struct umr_bitfield mmVM_INVALIDATE_ENG5_ACK[] = {
	 { "PER_VMID_INVALIDATE_ACK", 0, 15, &umr_bitfield_default },
	 { "SEMAPHORE", 16, 16, &umr_bitfield_default },
};
static struct umr_bitfield mmVM_INVALIDATE_ENG6_ACK[] = {
	 { "PER_VMID_INVALIDATE_ACK", 0, 15, &umr_bitfield_default },
	 { "SEMAPHORE", 16, 16, &umr_bitfield_default },
};
static struct umr_bitfield mmVM_INVALIDATE_ENG7_ACK[] = {
	 { "PER_VMID_INVALIDATE_ACK", 0, 15, &umr_bitfield_default },
	 { "SEMAPHORE", 16, 16, &umr_bitfield_default },
};
static struct umr_bitfield mmVM_INVALIDATE_ENG8_ACK[] = {
	 { "PER_VMID_INVALIDATE_ACK", 0, 15, &umr_bitfield_default },
	 { "SEMAPHORE", 16, 16, &umr_bitfield_default },
};
static struct umr_bitfield mmVM_INVALIDATE_ENG9_ACK[] = {
	 { "PER_VMID_INVALIDATE_ACK", 0, 15, &umr_bitfield_default },
	 { "SEMAPHORE", 16, 16, &umr_bitfield_default },
};
static struct umr_bitfield mmVM_INVALIDATE_ENG10_ACK[] = {
	 { "PER_VMID_INVALIDATE_ACK", 0, 15, &umr_bitfield_default },
	 { "SEMAPHORE", 16, 16, &umr_bitfield_default },
};
static struct umr_bitfield mmVM_INVALIDATE_ENG11_ACK[] = {
	 { "PER_VMID_INVALIDATE_ACK", 0, 15, &umr_bitfield_default },
	 { "SEMAPHORE", 16, 16, &umr_bitfield_default },
};
static struct umr_bitfield mmVM_INVALIDATE_ENG12_ACK[] = {
	 { "PER_VMID_INVALIDATE_ACK", 0, 15, &umr_bitfield_default },
	 { "SEMAPHORE", 16, 16, &umr_bitfield_default },
};
static struct umr_bitfield mmVM_INVALIDATE_ENG13_ACK[] = {
	 { "PER_VMID_INVALIDATE_ACK", 0, 15, &umr_bitfield_default },
	 { "SEMAPHORE", 16, 16, &umr_bitfield_default },
};
static struct umr_bitfield mmVM_INVALIDATE_ENG14_ACK[] = {
	 { "PER_VMID_INVALIDATE_ACK", 0, 15, &umr_bitfield_default },
	 { "SEMAPHORE", 16, 16, &umr_bitfield_default },
};
static struct umr_bitfield mmVM_INVALIDATE_ENG15_ACK[] = {
	 { "PER_VMID_INVALIDATE_ACK", 0, 15, &umr_bitfield_default },
	 { "SEMAPHORE", 16, 16, &umr_bitfield_default },
};
static struct umr_bitfield mmVM_INVALIDATE_ENG16_ACK[] = {
	 { "PER_VMID_INVALIDATE_ACK", 0, 15, &umr_bitfield_default },
	 { "SEMAPHORE", 16, 16, &umr_bitfield_default },
};
static struct umr_bitfield mmVM_INVALIDATE_ENG17_ACK[] = {
	 { "PER_VMID_INVALIDATE_ACK", 0, 15, &umr_bitfield_default },
	 { "SEMAPHORE", 16, 16, &umr_bitfield_default },
};
static struct umr_bitfield mmVM_INVALIDATE_ENG0_ADDR_RANGE_LO32[] = {
	 { "S_BIT", 0, 0, &umr_bitfield_default },
	 { "LOGI_PAGE_ADDR_RANGE_LO31", 1, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmVM_INVALIDATE_ENG0_ADDR_RANGE_HI32[] = {
	 { "LOGI_PAGE_ADDR_RANGE_HI5", 0, 4, &umr_bitfield_default },
};
static struct umr_bitfield mmVM_INVALIDATE_ENG1_ADDR_RANGE_LO32[] = {
	 { "S_BIT", 0, 0, &umr_bitfield_default },
	 { "LOGI_PAGE_ADDR_RANGE_LO31", 1, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmVM_INVALIDATE_ENG1_ADDR_RANGE_HI32[] = {
	 { "LOGI_PAGE_ADDR_RANGE_HI5", 0, 4, &umr_bitfield_default },
};
static struct umr_bitfield mmVM_INVALIDATE_ENG2_ADDR_RANGE_LO32[] = {
	 { "S_BIT", 0, 0, &umr_bitfield_default },
	 { "LOGI_PAGE_ADDR_RANGE_LO31", 1, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmVM_INVALIDATE_ENG2_ADDR_RANGE_HI32[] = {
	 { "LOGI_PAGE_ADDR_RANGE_HI5", 0, 4, &umr_bitfield_default },
};
static struct umr_bitfield mmVM_INVALIDATE_ENG3_ADDR_RANGE_LO32[] = {
	 { "S_BIT", 0, 0, &umr_bitfield_default },
	 { "LOGI_PAGE_ADDR_RANGE_LO31", 1, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmVM_INVALIDATE_ENG3_ADDR_RANGE_HI32[] = {
	 { "LOGI_PAGE_ADDR_RANGE_HI5", 0, 4, &umr_bitfield_default },
};
static struct umr_bitfield mmVM_INVALIDATE_ENG4_ADDR_RANGE_LO32[] = {
	 { "S_BIT", 0, 0, &umr_bitfield_default },
	 { "LOGI_PAGE_ADDR_RANGE_LO31", 1, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmVM_INVALIDATE_ENG4_ADDR_RANGE_HI32[] = {
	 { "LOGI_PAGE_ADDR_RANGE_HI5", 0, 4, &umr_bitfield_default },
};
static struct umr_bitfield mmVM_INVALIDATE_ENG5_ADDR_RANGE_LO32[] = {
	 { "S_BIT", 0, 0, &umr_bitfield_default },
	 { "LOGI_PAGE_ADDR_RANGE_LO31", 1, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmVM_INVALIDATE_ENG5_ADDR_RANGE_HI32[] = {
	 { "LOGI_PAGE_ADDR_RANGE_HI5", 0, 4, &umr_bitfield_default },
};
static struct umr_bitfield mmVM_INVALIDATE_ENG6_ADDR_RANGE_LO32[] = {
	 { "S_BIT", 0, 0, &umr_bitfield_default },
	 { "LOGI_PAGE_ADDR_RANGE_LO31", 1, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmVM_INVALIDATE_ENG6_ADDR_RANGE_HI32[] = {
	 { "LOGI_PAGE_ADDR_RANGE_HI5", 0, 4, &umr_bitfield_default },
};
static struct umr_bitfield mmVM_INVALIDATE_ENG7_ADDR_RANGE_LO32[] = {
	 { "S_BIT", 0, 0, &umr_bitfield_default },
	 { "LOGI_PAGE_ADDR_RANGE_LO31", 1, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmVM_INVALIDATE_ENG7_ADDR_RANGE_HI32[] = {
	 { "LOGI_PAGE_ADDR_RANGE_HI5", 0, 4, &umr_bitfield_default },
};
static struct umr_bitfield mmVM_INVALIDATE_ENG8_ADDR_RANGE_LO32[] = {
	 { "S_BIT", 0, 0, &umr_bitfield_default },
	 { "LOGI_PAGE_ADDR_RANGE_LO31", 1, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmVM_INVALIDATE_ENG8_ADDR_RANGE_HI32[] = {
	 { "LOGI_PAGE_ADDR_RANGE_HI5", 0, 4, &umr_bitfield_default },
};
static struct umr_bitfield mmVM_INVALIDATE_ENG9_ADDR_RANGE_LO32[] = {
	 { "S_BIT", 0, 0, &umr_bitfield_default },
	 { "LOGI_PAGE_ADDR_RANGE_LO31", 1, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmVM_INVALIDATE_ENG9_ADDR_RANGE_HI32[] = {
	 { "LOGI_PAGE_ADDR_RANGE_HI5", 0, 4, &umr_bitfield_default },
};
static struct umr_bitfield mmVM_INVALIDATE_ENG10_ADDR_RANGE_LO32[] = {
	 { "S_BIT", 0, 0, &umr_bitfield_default },
	 { "LOGI_PAGE_ADDR_RANGE_LO31", 1, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmVM_INVALIDATE_ENG10_ADDR_RANGE_HI32[] = {
	 { "LOGI_PAGE_ADDR_RANGE_HI5", 0, 4, &umr_bitfield_default },
};
static struct umr_bitfield mmVM_INVALIDATE_ENG11_ADDR_RANGE_LO32[] = {
	 { "S_BIT", 0, 0, &umr_bitfield_default },
	 { "LOGI_PAGE_ADDR_RANGE_LO31", 1, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmVM_INVALIDATE_ENG11_ADDR_RANGE_HI32[] = {
	 { "LOGI_PAGE_ADDR_RANGE_HI5", 0, 4, &umr_bitfield_default },
};
static struct umr_bitfield mmVM_INVALIDATE_ENG12_ADDR_RANGE_LO32[] = {
	 { "S_BIT", 0, 0, &umr_bitfield_default },
	 { "LOGI_PAGE_ADDR_RANGE_LO31", 1, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmVM_INVALIDATE_ENG12_ADDR_RANGE_HI32[] = {
	 { "LOGI_PAGE_ADDR_RANGE_HI5", 0, 4, &umr_bitfield_default },
};
static struct umr_bitfield mmVM_INVALIDATE_ENG13_ADDR_RANGE_LO32[] = {
	 { "S_BIT", 0, 0, &umr_bitfield_default },
	 { "LOGI_PAGE_ADDR_RANGE_LO31", 1, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmVM_INVALIDATE_ENG13_ADDR_RANGE_HI32[] = {
	 { "LOGI_PAGE_ADDR_RANGE_HI5", 0, 4, &umr_bitfield_default },
};
static struct umr_bitfield mmVM_INVALIDATE_ENG14_ADDR_RANGE_LO32[] = {
	 { "S_BIT", 0, 0, &umr_bitfield_default },
	 { "LOGI_PAGE_ADDR_RANGE_LO31", 1, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmVM_INVALIDATE_ENG14_ADDR_RANGE_HI32[] = {
	 { "LOGI_PAGE_ADDR_RANGE_HI5", 0, 4, &umr_bitfield_default },
};
static struct umr_bitfield mmVM_INVALIDATE_ENG15_ADDR_RANGE_LO32[] = {
	 { "S_BIT", 0, 0, &umr_bitfield_default },
	 { "LOGI_PAGE_ADDR_RANGE_LO31", 1, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmVM_INVALIDATE_ENG15_ADDR_RANGE_HI32[] = {
	 { "LOGI_PAGE_ADDR_RANGE_HI5", 0, 4, &umr_bitfield_default },
};
static struct umr_bitfield mmVM_INVALIDATE_ENG16_ADDR_RANGE_LO32[] = {
	 { "S_BIT", 0, 0, &umr_bitfield_default },
	 { "LOGI_PAGE_ADDR_RANGE_LO31", 1, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmVM_INVALIDATE_ENG16_ADDR_RANGE_HI32[] = {
	 { "LOGI_PAGE_ADDR_RANGE_HI5", 0, 4, &umr_bitfield_default },
};
static struct umr_bitfield mmVM_INVALIDATE_ENG17_ADDR_RANGE_LO32[] = {
	 { "S_BIT", 0, 0, &umr_bitfield_default },
	 { "LOGI_PAGE_ADDR_RANGE_LO31", 1, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmVM_INVALIDATE_ENG17_ADDR_RANGE_HI32[] = {
	 { "LOGI_PAGE_ADDR_RANGE_HI5", 0, 4, &umr_bitfield_default },
};
static struct umr_bitfield mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32[] = {
	 { "PAGE_DIRECTORY_ENTRY_LO32", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32[] = {
	 { "PAGE_DIRECTORY_ENTRY_HI32", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32[] = {
	 { "PAGE_DIRECTORY_ENTRY_LO32", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32[] = {
	 { "PAGE_DIRECTORY_ENTRY_HI32", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32[] = {
	 { "PAGE_DIRECTORY_ENTRY_LO32", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32[] = {
	 { "PAGE_DIRECTORY_ENTRY_HI32", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32[] = {
	 { "PAGE_DIRECTORY_ENTRY_LO32", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32[] = {
	 { "PAGE_DIRECTORY_ENTRY_HI32", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32[] = {
	 { "PAGE_DIRECTORY_ENTRY_LO32", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32[] = {
	 { "PAGE_DIRECTORY_ENTRY_HI32", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32[] = {
	 { "PAGE_DIRECTORY_ENTRY_LO32", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32[] = {
	 { "PAGE_DIRECTORY_ENTRY_HI32", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32[] = {
	 { "PAGE_DIRECTORY_ENTRY_LO32", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32[] = {
	 { "PAGE_DIRECTORY_ENTRY_HI32", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32[] = {
	 { "PAGE_DIRECTORY_ENTRY_LO32", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32[] = {
	 { "PAGE_DIRECTORY_ENTRY_HI32", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32[] = {
	 { "PAGE_DIRECTORY_ENTRY_LO32", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32[] = {
	 { "PAGE_DIRECTORY_ENTRY_HI32", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32[] = {
	 { "PAGE_DIRECTORY_ENTRY_LO32", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32[] = {
	 { "PAGE_DIRECTORY_ENTRY_HI32", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32[] = {
	 { "PAGE_DIRECTORY_ENTRY_LO32", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32[] = {
	 { "PAGE_DIRECTORY_ENTRY_HI32", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32[] = {
	 { "PAGE_DIRECTORY_ENTRY_LO32", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32[] = {
	 { "PAGE_DIRECTORY_ENTRY_HI32", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32[] = {
	 { "PAGE_DIRECTORY_ENTRY_LO32", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32[] = {
	 { "PAGE_DIRECTORY_ENTRY_HI32", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32[] = {
	 { "PAGE_DIRECTORY_ENTRY_LO32", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32[] = {
	 { "PAGE_DIRECTORY_ENTRY_HI32", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32[] = {
	 { "PAGE_DIRECTORY_ENTRY_LO32", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32[] = {
	 { "PAGE_DIRECTORY_ENTRY_HI32", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32[] = {
	 { "PAGE_DIRECTORY_ENTRY_LO32", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32[] = {
	 { "PAGE_DIRECTORY_ENTRY_HI32", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32[] = {
	 { "LOGICAL_PAGE_NUMBER_LO32", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32[] = {
	 { "LOGICAL_PAGE_NUMBER_HI4", 0, 3, &umr_bitfield_default },
};
static struct umr_bitfield mmVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32[] = {
	 { "LOGICAL_PAGE_NUMBER_LO32", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32[] = {
	 { "LOGICAL_PAGE_NUMBER_HI4", 0, 3, &umr_bitfield_default },
};
static struct umr_bitfield mmVM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32[] = {
	 { "LOGICAL_PAGE_NUMBER_LO32", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmVM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32[] = {
	 { "LOGICAL_PAGE_NUMBER_HI4", 0, 3, &umr_bitfield_default },
};
static struct umr_bitfield mmVM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32[] = {
	 { "LOGICAL_PAGE_NUMBER_LO32", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmVM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32[] = {
	 { "LOGICAL_PAGE_NUMBER_HI4", 0, 3, &umr_bitfield_default },
};
static struct umr_bitfield mmVM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32[] = {
	 { "LOGICAL_PAGE_NUMBER_LO32", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmVM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32[] = {
	 { "LOGICAL_PAGE_NUMBER_HI4", 0, 3, &umr_bitfield_default },
};
static struct umr_bitfield mmVM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32[] = {
	 { "LOGICAL_PAGE_NUMBER_LO32", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmVM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32[] = {
	 { "LOGICAL_PAGE_NUMBER_HI4", 0, 3, &umr_bitfield_default },
};
static struct umr_bitfield mmVM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32[] = {
	 { "LOGICAL_PAGE_NUMBER_LO32", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmVM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32[] = {
	 { "LOGICAL_PAGE_NUMBER_HI4", 0, 3, &umr_bitfield_default },
};
static struct umr_bitfield mmVM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32[] = {
	 { "LOGICAL_PAGE_NUMBER_LO32", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmVM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32[] = {
	 { "LOGICAL_PAGE_NUMBER_HI4", 0, 3, &umr_bitfield_default },
};
static struct umr_bitfield mmVM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32[] = {
	 { "LOGICAL_PAGE_NUMBER_LO32", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmVM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32[] = {
	 { "LOGICAL_PAGE_NUMBER_HI4", 0, 3, &umr_bitfield_default },
};
static struct umr_bitfield mmVM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32[] = {
	 { "LOGICAL_PAGE_NUMBER_LO32", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmVM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32[] = {
	 { "LOGICAL_PAGE_NUMBER_HI4", 0, 3, &umr_bitfield_default },
};
static struct umr_bitfield mmVM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32[] = {
	 { "LOGICAL_PAGE_NUMBER_LO32", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmVM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32[] = {
	 { "LOGICAL_PAGE_NUMBER_HI4", 0, 3, &umr_bitfield_default },
};
static struct umr_bitfield mmVM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32[] = {
	 { "LOGICAL_PAGE_NUMBER_LO32", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmVM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32[] = {
	 { "LOGICAL_PAGE_NUMBER_HI4", 0, 3, &umr_bitfield_default },
};
static struct umr_bitfield mmVM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32[] = {
	 { "LOGICAL_PAGE_NUMBER_LO32", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmVM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32[] = {
	 { "LOGICAL_PAGE_NUMBER_HI4", 0, 3, &umr_bitfield_default },
};
static struct umr_bitfield mmVM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32[] = {
	 { "LOGICAL_PAGE_NUMBER_LO32", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmVM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32[] = {
	 { "LOGICAL_PAGE_NUMBER_HI4", 0, 3, &umr_bitfield_default },
};
static struct umr_bitfield mmVM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32[] = {
	 { "LOGICAL_PAGE_NUMBER_LO32", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmVM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32[] = {
	 { "LOGICAL_PAGE_NUMBER_HI4", 0, 3, &umr_bitfield_default },
};
static struct umr_bitfield mmVM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32[] = {
	 { "LOGICAL_PAGE_NUMBER_LO32", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmVM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32[] = {
	 { "LOGICAL_PAGE_NUMBER_HI4", 0, 3, &umr_bitfield_default },
};
static struct umr_bitfield mmVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32[] = {
	 { "LOGICAL_PAGE_NUMBER_LO32", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32[] = {
	 { "LOGICAL_PAGE_NUMBER_HI4", 0, 3, &umr_bitfield_default },
};
static struct umr_bitfield mmVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32[] = {
	 { "LOGICAL_PAGE_NUMBER_LO32", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32[] = {
	 { "LOGICAL_PAGE_NUMBER_HI4", 0, 3, &umr_bitfield_default },
};
static struct umr_bitfield mmVM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32[] = {
	 { "LOGICAL_PAGE_NUMBER_LO32", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmVM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32[] = {
	 { "LOGICAL_PAGE_NUMBER_HI4", 0, 3, &umr_bitfield_default },
};
static struct umr_bitfield mmVM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32[] = {
	 { "LOGICAL_PAGE_NUMBER_LO32", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmVM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32[] = {
	 { "LOGICAL_PAGE_NUMBER_HI4", 0, 3, &umr_bitfield_default },
};
static struct umr_bitfield mmVM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32[] = {
	 { "LOGICAL_PAGE_NUMBER_LO32", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmVM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32[] = {
	 { "LOGICAL_PAGE_NUMBER_HI4", 0, 3, &umr_bitfield_default },
};
static struct umr_bitfield mmVM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32[] = {
	 { "LOGICAL_PAGE_NUMBER_LO32", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmVM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32[] = {
	 { "LOGICAL_PAGE_NUMBER_HI4", 0, 3, &umr_bitfield_default },
};
static struct umr_bitfield mmVM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32[] = {
	 { "LOGICAL_PAGE_NUMBER_LO32", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmVM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32[] = {
	 { "LOGICAL_PAGE_NUMBER_HI4", 0, 3, &umr_bitfield_default },
};
static struct umr_bitfield mmVM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32[] = {
	 { "LOGICAL_PAGE_NUMBER_LO32", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmVM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32[] = {
	 { "LOGICAL_PAGE_NUMBER_HI4", 0, 3, &umr_bitfield_default },
};
static struct umr_bitfield mmVM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32[] = {
	 { "LOGICAL_PAGE_NUMBER_LO32", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmVM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32[] = {
	 { "LOGICAL_PAGE_NUMBER_HI4", 0, 3, &umr_bitfield_default },
};
static struct umr_bitfield mmVM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32[] = {
	 { "LOGICAL_PAGE_NUMBER_LO32", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmVM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32[] = {
	 { "LOGICAL_PAGE_NUMBER_HI4", 0, 3, &umr_bitfield_default },
};
static struct umr_bitfield mmVM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32[] = {
	 { "LOGICAL_PAGE_NUMBER_LO32", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmVM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32[] = {
	 { "LOGICAL_PAGE_NUMBER_HI4", 0, 3, &umr_bitfield_default },
};
static struct umr_bitfield mmVM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32[] = {
	 { "LOGICAL_PAGE_NUMBER_LO32", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmVM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32[] = {
	 { "LOGICAL_PAGE_NUMBER_HI4", 0, 3, &umr_bitfield_default },
};
static struct umr_bitfield mmVM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32[] = {
	 { "LOGICAL_PAGE_NUMBER_LO32", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmVM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32[] = {
	 { "LOGICAL_PAGE_NUMBER_HI4", 0, 3, &umr_bitfield_default },
};
static struct umr_bitfield mmVM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32[] = {
	 { "LOGICAL_PAGE_NUMBER_LO32", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmVM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32[] = {
	 { "LOGICAL_PAGE_NUMBER_HI4", 0, 3, &umr_bitfield_default },
};
static struct umr_bitfield mmVM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32[] = {
	 { "LOGICAL_PAGE_NUMBER_LO32", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmVM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32[] = {
	 { "LOGICAL_PAGE_NUMBER_HI4", 0, 3, &umr_bitfield_default },
};
static struct umr_bitfield mmVM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32[] = {
	 { "LOGICAL_PAGE_NUMBER_LO32", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmVM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32[] = {
	 { "LOGICAL_PAGE_NUMBER_HI4", 0, 3, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_VM_L2_PERFCOUNTER0_CFG[] = {
	 { "PERF_SEL", 0, 7, &umr_bitfield_default },
	 { "PERF_SEL_END", 8, 15, &umr_bitfield_default },
	 { "PERF_MODE", 24, 27, &umr_bitfield_default },
	 { "ENABLE", 28, 28, &umr_bitfield_default },
	 { "CLEAR", 29, 29, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_VM_L2_PERFCOUNTER1_CFG[] = {
	 { "PERF_SEL", 0, 7, &umr_bitfield_default },
	 { "PERF_SEL_END", 8, 15, &umr_bitfield_default },
	 { "PERF_MODE", 24, 27, &umr_bitfield_default },
	 { "ENABLE", 28, 28, &umr_bitfield_default },
	 { "CLEAR", 29, 29, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_VM_L2_PERFCOUNTER2_CFG[] = {
	 { "PERF_SEL", 0, 7, &umr_bitfield_default },
	 { "PERF_SEL_END", 8, 15, &umr_bitfield_default },
	 { "PERF_MODE", 24, 27, &umr_bitfield_default },
	 { "ENABLE", 28, 28, &umr_bitfield_default },
	 { "CLEAR", 29, 29, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_VM_L2_PERFCOUNTER3_CFG[] = {
	 { "PERF_SEL", 0, 7, &umr_bitfield_default },
	 { "PERF_SEL_END", 8, 15, &umr_bitfield_default },
	 { "PERF_MODE", 24, 27, &umr_bitfield_default },
	 { "ENABLE", 28, 28, &umr_bitfield_default },
	 { "CLEAR", 29, 29, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_VM_L2_PERFCOUNTER4_CFG[] = {
	 { "PERF_SEL", 0, 7, &umr_bitfield_default },
	 { "PERF_SEL_END", 8, 15, &umr_bitfield_default },
	 { "PERF_MODE", 24, 27, &umr_bitfield_default },
	 { "ENABLE", 28, 28, &umr_bitfield_default },
	 { "CLEAR", 29, 29, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_VM_L2_PERFCOUNTER5_CFG[] = {
	 { "PERF_SEL", 0, 7, &umr_bitfield_default },
	 { "PERF_SEL_END", 8, 15, &umr_bitfield_default },
	 { "PERF_MODE", 24, 27, &umr_bitfield_default },
	 { "ENABLE", 28, 28, &umr_bitfield_default },
	 { "CLEAR", 29, 29, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_VM_L2_PERFCOUNTER6_CFG[] = {
	 { "PERF_SEL", 0, 7, &umr_bitfield_default },
	 { "PERF_SEL_END", 8, 15, &umr_bitfield_default },
	 { "PERF_MODE", 24, 27, &umr_bitfield_default },
	 { "ENABLE", 28, 28, &umr_bitfield_default },
	 { "CLEAR", 29, 29, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_VM_L2_PERFCOUNTER7_CFG[] = {
	 { "PERF_SEL", 0, 7, &umr_bitfield_default },
	 { "PERF_SEL_END", 8, 15, &umr_bitfield_default },
	 { "PERF_MODE", 24, 27, &umr_bitfield_default },
	 { "ENABLE", 28, 28, &umr_bitfield_default },
	 { "CLEAR", 29, 29, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_VM_L2_PERFCOUNTER_RSLT_CNTL[] = {
	 { "PERF_COUNTER_SELECT", 0, 3, &umr_bitfield_default },
	 { "START_TRIGGER", 8, 15, &umr_bitfield_default },
	 { "STOP_TRIGGER", 16, 23, &umr_bitfield_default },
	 { "ENABLE_ANY", 24, 24, &umr_bitfield_default },
	 { "CLEAR_ALL", 25, 25, &umr_bitfield_default },
	 { "STOP_ALL_ON_SATURATE", 26, 26, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_VM_L2_PERFCOUNTER_LO[] = {
	 { "COUNTER_LO", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_VM_L2_PERFCOUNTER_HI[] = {
	 { "COUNTER_HI", 0, 15, &umr_bitfield_default },
	 { "COMPARE_VALUE", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_VM_FB_SIZE_OFFSET_VF0[] = {
	 { "VF_FB_SIZE", 0, 15, &umr_bitfield_default },
	 { "VF_FB_OFFSET", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_VM_FB_SIZE_OFFSET_VF1[] = {
	 { "VF_FB_SIZE", 0, 15, &umr_bitfield_default },
	 { "VF_FB_OFFSET", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_VM_FB_SIZE_OFFSET_VF2[] = {
	 { "VF_FB_SIZE", 0, 15, &umr_bitfield_default },
	 { "VF_FB_OFFSET", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_VM_FB_SIZE_OFFSET_VF3[] = {
	 { "VF_FB_SIZE", 0, 15, &umr_bitfield_default },
	 { "VF_FB_OFFSET", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_VM_FB_SIZE_OFFSET_VF4[] = {
	 { "VF_FB_SIZE", 0, 15, &umr_bitfield_default },
	 { "VF_FB_OFFSET", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_VM_FB_SIZE_OFFSET_VF5[] = {
	 { "VF_FB_SIZE", 0, 15, &umr_bitfield_default },
	 { "VF_FB_OFFSET", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_VM_FB_SIZE_OFFSET_VF6[] = {
	 { "VF_FB_SIZE", 0, 15, &umr_bitfield_default },
	 { "VF_FB_OFFSET", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_VM_FB_SIZE_OFFSET_VF7[] = {
	 { "VF_FB_SIZE", 0, 15, &umr_bitfield_default },
	 { "VF_FB_OFFSET", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_VM_FB_SIZE_OFFSET_VF8[] = {
	 { "VF_FB_SIZE", 0, 15, &umr_bitfield_default },
	 { "VF_FB_OFFSET", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_VM_FB_SIZE_OFFSET_VF9[] = {
	 { "VF_FB_SIZE", 0, 15, &umr_bitfield_default },
	 { "VF_FB_OFFSET", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_VM_FB_SIZE_OFFSET_VF10[] = {
	 { "VF_FB_SIZE", 0, 15, &umr_bitfield_default },
	 { "VF_FB_OFFSET", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_VM_FB_SIZE_OFFSET_VF11[] = {
	 { "VF_FB_SIZE", 0, 15, &umr_bitfield_default },
	 { "VF_FB_OFFSET", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_VM_FB_SIZE_OFFSET_VF12[] = {
	 { "VF_FB_SIZE", 0, 15, &umr_bitfield_default },
	 { "VF_FB_OFFSET", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_VM_FB_SIZE_OFFSET_VF13[] = {
	 { "VF_FB_SIZE", 0, 15, &umr_bitfield_default },
	 { "VF_FB_OFFSET", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_VM_FB_SIZE_OFFSET_VF14[] = {
	 { "VF_FB_SIZE", 0, 15, &umr_bitfield_default },
	 { "VF_FB_OFFSET", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_VM_FB_SIZE_OFFSET_VF15[] = {
	 { "VF_FB_SIZE", 0, 15, &umr_bitfield_default },
	 { "VF_FB_OFFSET", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmVM_IOMMU_MMIO_CNTRL_1[] = {
	 { "MARC_EN", 8, 8, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_VM_MARC_BASE_LO_0[] = {
	 { "MARC_BASE_LO_0", 12, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_VM_MARC_BASE_LO_1[] = {
	 { "MARC_BASE_LO_1", 12, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_VM_MARC_BASE_LO_2[] = {
	 { "MARC_BASE_LO_2", 12, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_VM_MARC_BASE_LO_3[] = {
	 { "MARC_BASE_LO_3", 12, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_VM_MARC_BASE_HI_0[] = {
	 { "MARC_BASE_HI_0", 0, 19, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_VM_MARC_BASE_HI_1[] = {
	 { "MARC_BASE_HI_1", 0, 19, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_VM_MARC_BASE_HI_2[] = {
	 { "MARC_BASE_HI_2", 0, 19, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_VM_MARC_BASE_HI_3[] = {
	 { "MARC_BASE_HI_3", 0, 19, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_VM_MARC_RELOC_LO_0[] = {
	 { "MARC_ENABLE_0", 0, 0, &umr_bitfield_default },
	 { "MARC_READONLY_0", 1, 1, &umr_bitfield_default },
	 { "MARC_RELOC_LO_0", 12, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_VM_MARC_RELOC_LO_1[] = {
	 { "MARC_ENABLE_1", 0, 0, &umr_bitfield_default },
	 { "MARC_READONLY_1", 1, 1, &umr_bitfield_default },
	 { "MARC_RELOC_LO_1", 12, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_VM_MARC_RELOC_LO_2[] = {
	 { "MARC_ENABLE_2", 0, 0, &umr_bitfield_default },
	 { "MARC_READONLY_2", 1, 1, &umr_bitfield_default },
	 { "MARC_RELOC_LO_2", 12, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_VM_MARC_RELOC_LO_3[] = {
	 { "MARC_ENABLE_3", 0, 0, &umr_bitfield_default },
	 { "MARC_READONLY_3", 1, 1, &umr_bitfield_default },
	 { "MARC_RELOC_LO_3", 12, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_VM_MARC_RELOC_HI_0[] = {
	 { "MARC_RELOC_HI_0", 0, 19, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_VM_MARC_RELOC_HI_1[] = {
	 { "MARC_RELOC_HI_1", 0, 19, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_VM_MARC_RELOC_HI_2[] = {
	 { "MARC_RELOC_HI_2", 0, 19, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_VM_MARC_RELOC_HI_3[] = {
	 { "MARC_RELOC_HI_3", 0, 19, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_VM_MARC_LEN_LO_0[] = {
	 { "MARC_LEN_LO_0", 12, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_VM_MARC_LEN_LO_1[] = {
	 { "MARC_LEN_LO_1", 12, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_VM_MARC_LEN_LO_2[] = {
	 { "MARC_LEN_LO_2", 12, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_VM_MARC_LEN_LO_3[] = {
	 { "MARC_LEN_LO_3", 12, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_VM_MARC_LEN_HI_0[] = {
	 { "MARC_LEN_HI_0", 0, 19, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_VM_MARC_LEN_HI_1[] = {
	 { "MARC_LEN_HI_1", 0, 19, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_VM_MARC_LEN_HI_2[] = {
	 { "MARC_LEN_HI_2", 0, 19, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_VM_MARC_LEN_HI_3[] = {
	 { "MARC_LEN_HI_3", 0, 19, &umr_bitfield_default },
};
static struct umr_bitfield mmVM_IOMMU_CONTROL_REGISTER[] = {
	 { "IOMMUEN", 0, 0, &umr_bitfield_default },
};
static struct umr_bitfield mmVM_IOMMU_PERFORMANCE_OPTIMIZATION_CONTROL_REGISTER[] = {
	 { "PERFOPTEN", 13, 13, &umr_bitfield_default },
};
static struct umr_bitfield mmVM_PCIE_ATS_CNTL[] = {
	 { "STU", 16, 20, &umr_bitfield_default },
	 { "ATC_ENABLE", 31, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmVM_PCIE_ATS_CNTL_VF_0[] = {
	 { "ATC_ENABLE", 31, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmVM_PCIE_ATS_CNTL_VF_1[] = {
	 { "ATC_ENABLE", 31, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmVM_PCIE_ATS_CNTL_VF_2[] = {
	 { "ATC_ENABLE", 31, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmVM_PCIE_ATS_CNTL_VF_3[] = {
	 { "ATC_ENABLE", 31, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmVM_PCIE_ATS_CNTL_VF_4[] = {
	 { "ATC_ENABLE", 31, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmVM_PCIE_ATS_CNTL_VF_5[] = {
	 { "ATC_ENABLE", 31, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmVM_PCIE_ATS_CNTL_VF_6[] = {
	 { "ATC_ENABLE", 31, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmVM_PCIE_ATS_CNTL_VF_7[] = {
	 { "ATC_ENABLE", 31, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmVM_PCIE_ATS_CNTL_VF_8[] = {
	 { "ATC_ENABLE", 31, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmVM_PCIE_ATS_CNTL_VF_9[] = {
	 { "ATC_ENABLE", 31, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmVM_PCIE_ATS_CNTL_VF_10[] = {
	 { "ATC_ENABLE", 31, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmVM_PCIE_ATS_CNTL_VF_11[] = {
	 { "ATC_ENABLE", 31, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmVM_PCIE_ATS_CNTL_VF_12[] = {
	 { "ATC_ENABLE", 31, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmVM_PCIE_ATS_CNTL_VF_13[] = {
	 { "ATC_ENABLE", 31, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmVM_PCIE_ATS_CNTL_VF_14[] = {
	 { "ATC_ENABLE", 31, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmVM_PCIE_ATS_CNTL_VF_15[] = {
	 { "ATC_ENABLE", 31, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmUTCL2_CGTT_CLK_CTRL[] = {
	 { "ON_DELAY", 0, 3, &umr_bitfield_default },
	 { "OFF_HYSTERESIS", 4, 11, &umr_bitfield_default },
	 { "SOFT_OVERRIDE_EXTRA", 12, 14, &umr_bitfield_default },
	 { "MGLS_OVERRIDE", 15, 15, &umr_bitfield_default },
	 { "SOFT_STALL_OVERRIDE", 16, 23, &umr_bitfield_default },
	 { "SOFT_OVERRIDE", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_VM_NB_MMIOBASE[] = {
	 { "MMIOBASE", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_VM_NB_MMIOLIMIT[] = {
	 { "MMIOLIMIT", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_VM_NB_PCI_CTRL[] = {
	 { "MMIOENABLE", 23, 23, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_VM_NB_PCI_ARB[] = {
	 { "VGA_HOLE", 3, 3, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_VM_NB_TOP_OF_DRAM_SLOT1[] = {
	 { "TOP_OF_DRAM", 23, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_VM_NB_LOWER_TOP_OF_DRAM2[] = {
	 { "ENABLE", 0, 0, &umr_bitfield_default },
	 { "LOWER_TOM2", 23, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_VM_NB_UPPER_TOP_OF_DRAM2[] = {
	 { "UPPER_TOM2", 0, 11, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_VM_FB_OFFSET[] = {
	 { "FB_OFFSET", 0, 23, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB[] = {
	 { "PHYSICAL_PAGE_NUMBER_LSB", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB[] = {
	 { "PHYSICAL_PAGE_NUMBER_MSB", 0, 3, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_VM_STEERING[] = {
	 { "DEFAULT_STEERING", 0, 1, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_SHARED_VIRT_RESET_REQ[] = {
	 { "VF", 0, 15, &umr_bitfield_default },
	 { "PF", 31, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_MEM_POWER_LS[] = {
	 { "LS_SETUP", 0, 5, &umr_bitfield_default },
	 { "LS_HOLD", 6, 11, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_VM_CACHEABLE_DRAM_ADDRESS_START[] = {
	 { "ADDRESS", 0, 19, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_VM_CACHEABLE_DRAM_ADDRESS_END[] = {
	 { "ADDRESS", 0, 19, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_VM_APT_CNTL[] = {
	 { "FORCE_MTYPE_UC", 0, 0, &umr_bitfield_default },
	 { "DIRECT_SYSTEM_EN", 1, 1, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_VM_LOCAL_HBM_ADDRESS_START[] = {
	 { "ADDRESS", 0, 19, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_VM_LOCAL_HBM_ADDRESS_END[] = {
	 { "ADDRESS", 0, 19, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL[] = {
	 { "LOCK", 0, 0, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_VM_FB_LOCATION_BASE[] = {
	 { "FB_BASE", 0, 23, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_VM_FB_LOCATION_TOP[] = {
	 { "FB_TOP", 0, 23, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_VM_AGP_TOP[] = {
	 { "AGP_TOP", 0, 23, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_VM_AGP_BOT[] = {
	 { "AGP_BOT", 0, 23, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_VM_AGP_BASE[] = {
	 { "AGP_BASE", 0, 23, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_VM_SYSTEM_APERTURE_LOW_ADDR[] = {
	 { "LOGICAL_ADDR", 0, 29, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR[] = {
	 { "LOGICAL_ADDR", 0, 29, &umr_bitfield_default },
};
static struct umr_bitfield mmMC_VM_MX_L1_TLB_CNTL[] = {
	 { "ENABLE_L1_TLB", 0, 0, &umr_bitfield_default },
	 { "SYSTEM_ACCESS_MODE", 3, 4, &umr_bitfield_default },
	 { "SYSTEM_APERTURE_UNMAPPED_ACCESS", 5, 5, &umr_bitfield_default },
	 { "ENABLE_ADVANCED_DRIVER_MODEL", 6, 6, &umr_bitfield_default },
	 { "ECO_BITS", 7, 10, &umr_bitfield_default },
	 { "MTYPE", 11, 12, &umr_bitfield_default },
	 { "ATC_EN", 13, 13, &umr_bitfield_default },
};
static struct umr_bitfield mmATC_L2_PERFCOUNTER_LO[] = {
	 { "COUNTER_LO", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmATC_L2_PERFCOUNTER_HI[] = {
	 { "COUNTER_HI", 0, 15, &umr_bitfield_default },
	 { "COMPARE_VALUE", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmATC_L2_PERFCOUNTER0_CFG[] = {
	 { "PERF_SEL", 0, 7, &umr_bitfield_default },
	 { "PERF_SEL_END", 8, 15, &umr_bitfield_default },
	 { "PERF_MODE", 24, 27, &umr_bitfield_default },
	 { "ENABLE", 28, 28, &umr_bitfield_default },
	 { "CLEAR", 29, 29, &umr_bitfield_default },
};
static struct umr_bitfield mmATC_L2_PERFCOUNTER1_CFG[] = {
	 { "PERF_SEL", 0, 7, &umr_bitfield_default },
	 { "PERF_SEL_END", 8, 15, &umr_bitfield_default },
	 { "PERF_MODE", 24, 27, &umr_bitfield_default },
	 { "ENABLE", 28, 28, &umr_bitfield_default },
	 { "CLEAR", 29, 29, &umr_bitfield_default },
};
static struct umr_bitfield mmATC_L2_PERFCOUNTER_RSLT_CNTL[] = {
	 { "PERF_COUNTER_SELECT", 0, 3, &umr_bitfield_default },
	 { "START_TRIGGER", 8, 15, &umr_bitfield_default },
	 { "STOP_TRIGGER", 16, 23, &umr_bitfield_default },
	 { "ENABLE_ANY", 24, 24, &umr_bitfield_default },
	 { "CLEAR_ALL", 25, 25, &umr_bitfield_default },
	 { "STOP_ALL_ON_SATURATE", 26, 26, &umr_bitfield_default },
};