static struct umr_bitfield ixDH_TEST[] = {
	 { "DH_TEST", 0, 0, &umr_bitfield_default },
};
static struct umr_bitfield ixKHFS3[] = {
	 { "RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixKSESSION0[] = {
	 { "RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmCC_DRM_ID_STRAPS[] = {
	 { "DEVICE_ID", 4, 19, &umr_bitfield_default },
	 { "MAJOR_REV_ID", 20, 23, &umr_bitfield_default },
	 { "MINOR_REV_ID", 24, 27, &umr_bitfield_default },
	 { "ATI_REV_ID", 28, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_TEST_DEBUG_INDEX[] = {
	 { "DC_TEST_DEBUG_INDEX", 0, 7, &umr_bitfield_default },
	 { "DC_TEST_DEBUG_WRITE_EN", 8, 8, &umr_bitfield_default },
};
static struct umr_bitfield mmDC_TEST_DEBUG_DATA[] = {
	 { "DC_TEST_DEBUG_DATA", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixKSESSION1[] = {
	 { "RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixCLIENT2_K0[] = {
	 { "RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixCLIENT2_K1[] = {
	 { "RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixCLIENT2_K2[] = {
	 { "RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixKSESSION2[] = {
	 { "RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixCLIENT2_K3[] = {
	 { "RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixCLIENT2_CK0[] = {
	 { "RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixCLIENT2_CK1[] = {
	 { "RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixCLIENT2_CK2[] = {
	 { "RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixCLIENT2_CK3[] = {
	 { "RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixCLIENT2_CD0[] = {
	 { "RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixCLIENT2_CD1[] = {
	 { "RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixCLIENT2_CD2[] = {
	 { "RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixCLIENT2_CD3[] = {
	 { "RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixCLIENT2_BM[] = {
	 { "RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixCLIENT2_OFFSET[] = {
	 { "RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixCLIENT2_STATUS[] = {
	 { "RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixCLIENT0_K0[] = {
	 { "RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixCLIENT0_K1[] = {
	 { "RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixCLIENT0_K2[] = {
	 { "RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixCLIENT0_K3[] = {
	 { "RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixKSESSION3[] = {
	 { "RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixCLIENT0_CK0[] = {
	 { "RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixCLIENT0_CK1[] = {
	 { "RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixCLIENT0_CK2[] = {
	 { "RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixCLIENT0_CK3[] = {
	 { "RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixCLIENT0_CD0[] = {
	 { "RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixCLIENT0_CD1[] = {
	 { "RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixCLIENT0_CD2[] = {
	 { "RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixCLIENT0_CD3[] = {
	 { "RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixCLIENT0_BM[] = {
	 { "RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixCLIENT0_OFFSET[] = {
	 { "RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixCLIENT0_STATUS[] = {
	 { "RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixCLIENT1_K0[] = {
	 { "RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixCLIENT1_K1[] = {
	 { "RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixCLIENT1_K2[] = {
	 { "RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixCLIENT1_K3[] = {
	 { "RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixCLIENT1_CK0[] = {
	 { "RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixKSIG0[] = {
	 { "RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixCLIENT1_CK1[] = {
	 { "RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixCLIENT1_CK2[] = {
	 { "RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixCLIENT1_CK3[] = {
	 { "RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixCLIENT1_CD0[] = {
	 { "RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixCLIENT1_CD1[] = {
	 { "RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixCLIENT1_CD2[] = {
	 { "RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixCLIENT1_CD3[] = {
	 { "RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixCLIENT1_BM[] = {
	 { "RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixCLIENT1_OFFSET[] = {
	 { "RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixCLIENT1_PORT_STATUS[] = {
	 { "RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixKEFUSE0[] = {
	 { "RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixKEFUSE1[] = {
	 { "RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixKEFUSE2[] = {
	 { "RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixKEFUSE3[] = {
	 { "RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixHFS_SEED0[] = {
	 { "RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixHFS_SEED1[] = {
	 { "RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixKSIG1[] = {
	 { "RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixHFS_SEED2[] = {
	 { "RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixHFS_SEED3[] = {
	 { "RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixRINGOSC_MASK[] = {
	 { "MASK", 0, 15, &umr_bitfield_default },
};
static struct umr_bitfield ixCLIENT0_OFFSET_HI[] = {
	 { "RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixCLIENT1_OFFSET_HI[] = {
	 { "RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixCLIENT2_OFFSET_HI[] = {
	 { "RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixSPU_PORT_STATUS[] = {
	 { "RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixCLIENT3_OFFSET_HI[] = {
	 { "RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixCLIENT3_K0[] = {
	 { "RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixCLIENT3_K1[] = {
	 { "RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixCLIENT3_K2[] = {
	 { "RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixCLIENT3_K3[] = {
	 { "RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixCLIENT3_CK0[] = {
	 { "RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixCLIENT3_CK1[] = {
	 { "RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixCLIENT3_CK2[] = {
	 { "RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixKSIG2[] = {
	 { "RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixCLIENT3_CK3[] = {
	 { "RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixCLIENT3_CD0[] = {
	 { "RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixCLIENT3_CD1[] = {
	 { "RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixCLIENT3_CD2[] = {
	 { "RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixCLIENT3_CD3[] = {
	 { "RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixCLIENT3_BM[] = {
	 { "RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixCLIENT3_OFFSET[] = {
	 { "RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixCLIENT3_STATUS[] = {
	 { "RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixKSIG3[] = {
	 { "RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixEXP0[] = {
	 { "RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA0_UCODE_ADDR[] = {
	 { "VALUE", 0, 10, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA0_UCODE_DATA[] = {
	 { "VALUE", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA0_POWER_CNTL[] = {
	 { "MEM_POWER_OVERRIDE", 8, 8, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA0_CLK_CTRL[] = {
	 { "ON_DELAY", 0, 3, &umr_bitfield_default },
	 { "OFF_HYSTERESIS", 4, 11, &umr_bitfield_default },
	 { "SOFT_OVERRIDE7", 24, 24, &umr_bitfield_default },
	 { "SOFT_OVERRIDE6", 25, 25, &umr_bitfield_default },
	 { "SOFT_OVERRIDE5", 26, 26, &umr_bitfield_default },
	 { "SOFT_OVERRIDE4", 27, 27, &umr_bitfield_default },
	 { "SOFT_OVERRIDE3", 28, 28, &umr_bitfield_default },
	 { "SOFT_OVERRIDE2", 29, 29, &umr_bitfield_default },
	 { "SOFT_OVERRIDE1", 30, 30, &umr_bitfield_default },
	 { "SOFT_OVERRIDE0", 31, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA0_CNTL[] = {
	 { "TRAP_ENABLE", 0, 0, &umr_bitfield_default },
	 { "SEM_INCOMPLETE_INT_ENABLE", 1, 1, &umr_bitfield_default },
	 { "SEM_WAIT_INT_ENABLE", 2, 2, &umr_bitfield_default },
	 { "DATA_SWAP_ENABLE", 3, 3, &umr_bitfield_default },
	 { "FENCE_SWAP_ENABLE", 4, 4, &umr_bitfield_default },
	 { "MC_WRREQ_CREDIT", 11, 16, &umr_bitfield_default },
	 { "AUTO_CTXSW_ENABLE", 18, 18, &umr_bitfield_default },
	 { "MC_RDREQ_CREDIT", 22, 27, &umr_bitfield_default },
	 { "CTXEMPTY_INT_ENABLE", 28, 28, &umr_bitfield_default },
	 { "FROZEN_INT_ENABLE", 29, 29, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA0_CHICKEN_BITS[] = {
	 { "COPY_EFFICIENCY_ENABLE", 0, 0, &umr_bitfield_default },
	 { "COPY_OVERLAP_ENABLE", 16, 16, &umr_bitfield_default },
	 { "SRBM_POLL_RETRYING", 20, 20, &umr_bitfield_default },
	 { "CG_STATUS_OUTPUT", 23, 23, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA0_TILING_CONFIG[] = {
	 { "PIPE_INTERLEAVE_SIZE", 4, 6, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA0_HASH[] = {
	 { "CHANNEL_BITS", 0, 2, &umr_bitfield_default },
	 { "BANK_BITS", 4, 6, &umr_bitfield_default },
	 { "CHANNEL_XOR_COUNT", 8, 10, &umr_bitfield_default },
	 { "BANK_XOR_COUNT", 12, 14, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA0_SEM_INCOMPLETE_TIMER_CNTL[] = {
	 { "TIMER", 0, 15, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL[] = {
	 { "TIMER", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA0_RB_RPTR_FETCH[] = {
	 { "OFFSET", 2, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA0_IB_OFFSET_FETCH[] = {
	 { "OFFSET", 2, 21, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA0_PROGRAM[] = {
	 { "STREAM", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA0_STATUS_REG[] = {
	 { "IDLE", 0, 0, &umr_bitfield_default },
	 { "REG_IDLE", 1, 1, &umr_bitfield_default },
	 { "RB_EMPTY", 2, 2, &umr_bitfield_default },
	 { "RB_FULL", 3, 3, &umr_bitfield_default },
	 { "RB_CMD_IDLE", 4, 4, &umr_bitfield_default },
	 { "RB_CMD_FULL", 5, 5, &umr_bitfield_default },
	 { "IB_CMD_IDLE", 6, 6, &umr_bitfield_default },
	 { "IB_CMD_FULL", 7, 7, &umr_bitfield_default },
	 { "BLOCK_IDLE", 8, 8, &umr_bitfield_default },
	 { "INSIDE_IB", 9, 9, &umr_bitfield_default },
	 { "EX_IDLE", 10, 10, &umr_bitfield_default },
	 { "EX_IDLE_POLL_TIMER_EXPIRE", 11, 11, &umr_bitfield_default },
	 { "PACKET_READY", 12, 12, &umr_bitfield_default },
	 { "MC_WR_IDLE", 13, 13, &umr_bitfield_default },
	 { "SRBM_IDLE", 14, 14, &umr_bitfield_default },
	 { "CONTEXT_EMPTY", 15, 15, &umr_bitfield_default },
	 { "RB_MC_RREQ_IDLE", 17, 17, &umr_bitfield_default },
	 { "IB_MC_RREQ_IDLE", 18, 18, &umr_bitfield_default },
	 { "MC_RD_IDLE", 19, 19, &umr_bitfield_default },
	 { "MC_RD_RET_STALL", 21, 21, &umr_bitfield_default },
	 { "MC_RD_NO_POLL_IDLE", 22, 22, &umr_bitfield_default },
	 { "PREV_CMD_IDLE", 25, 25, &umr_bitfield_default },
	 { "SEM_IDLE", 26, 26, &umr_bitfield_default },
	 { "SEM_REQ_STALL", 27, 27, &umr_bitfield_default },
	 { "SEM_RESP_STATE", 28, 29, &umr_bitfield_default },
	 { "INT_IDLE", 30, 30, &umr_bitfield_default },
	 { "INT_REQ_STALL", 31, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA0_STATUS1_REG[] = {
	 { "CE_WREQ_IDLE", 0, 0, &umr_bitfield_default },
	 { "CE_WR_IDLE", 1, 1, &umr_bitfield_default },
	 { "CE_SPLIT_IDLE", 2, 2, &umr_bitfield_default },
	 { "CE_RREQ_IDLE", 3, 3, &umr_bitfield_default },
	 { "CE_OUT_IDLE", 4, 4, &umr_bitfield_default },
	 { "CE_IN_IDLE", 5, 5, &umr_bitfield_default },
	 { "CE_DST_IDLE", 6, 6, &umr_bitfield_default },
	 { "CE_AFIFO_FULL", 10, 10, &umr_bitfield_default },
	 { "CE_INFO_FULL", 13, 13, &umr_bitfield_default },
	 { "CE_INFO1_FULL", 14, 14, &umr_bitfield_default },
	 { "CE_RD_STALL", 17, 17, &umr_bitfield_default },
	 { "CE_WR_STALL", 18, 18, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA0_PERFMON_CNTL[] = {
	 { "PERF_ENABLE0", 0, 0, &umr_bitfield_default },
	 { "PERF_CLEAR0", 1, 1, &umr_bitfield_default },
	 { "PERF_SEL0", 2, 7, &umr_bitfield_default },
	 { "PERF_ENABLE1", 8, 8, &umr_bitfield_default },
	 { "PERF_CLEAR1", 9, 9, &umr_bitfield_default },
	 { "PERF_SEL1", 10, 15, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA0_PERFCOUNTER0_RESULT[] = {
	 { "PERF_COUNT", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA0_PERFCOUNTER1_RESULT[] = {
	 { "PERF_COUNT", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA0_F32_CNTL[] = {
	 { "HALT", 0, 0, &umr_bitfield_default },
	 { "STEP", 1, 1, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA0_FREEZE[] = {
	 { "FREEZE", 4, 4, &umr_bitfield_default },
	 { "FROZEN", 5, 5, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA0_PHASE0_QUANTUM[] = {
	 { "UNIT", 0, 3, &umr_bitfield_default },
	 { "VALUE", 8, 23, &umr_bitfield_default },
	 { "PREFER", 30, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA0_PHASE1_QUANTUM[] = {
	 { "UNIT", 0, 3, &umr_bitfield_default },
	 { "VALUE", 8, 23, &umr_bitfield_default },
	 { "PREFER", 30, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA_POWER_GATING[] = {
	 { "PG_CNTL_ENABLE", 0, 0, &umr_bitfield_default },
	 { "AUTOMATIC_STATUS_ENABLE", 1, 1, &umr_bitfield_default },
	 { "PG_STATE_VALID", 2, 2, &umr_bitfield_default },
	 { "PG_CNTL_STATUS", 4, 5, &umr_bitfield_default },
	 { "SDMA0_ON_CONDITION", 6, 6, &umr_bitfield_default },
	 { "SDMA1_ON_CONDITION", 7, 7, &umr_bitfield_default },
	 { "POWER_OFF_DELAY", 8, 19, &umr_bitfield_default },
	 { "POWER_ON_DELAY", 20, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA_PGFSM_CONFIG[] = {
	 { "FSM_ADDR", 0, 7, &umr_bitfield_default },
	 { "POWER_DOWN", 8, 8, &umr_bitfield_default },
	 { "POWER_UP", 9, 9, &umr_bitfield_default },
	 { "P1_SELECT", 10, 10, &umr_bitfield_default },
	 { "P2_SELECT", 11, 11, &umr_bitfield_default },
	 { "WRITE", 12, 12, &umr_bitfield_default },
	 { "READ", 13, 13, &umr_bitfield_default },
	 { "SRBM_OVERRIDE", 27, 27, &umr_bitfield_default },
	 { "REG_ADDR", 28, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA_PGFSM_WRITE[] = {
	 { "VALUE", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA_PGFSM_READ[] = {
	 { "VALUE", 0, 23, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA0_EDC_CONFIG[] = {
	 { "DIS_EDC", 1, 1, &umr_bitfield_default },
	 { "ECC_INT_ENABLE", 2, 2, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA0_GFX_RB_CNTL[] = {
	 { "RB_ENABLE", 0, 0, &umr_bitfield_default },
	 { "RB_SIZE", 1, 5, &umr_bitfield_default },
	 { "RB_SWAP_ENABLE", 9, 9, &umr_bitfield_default },
	 { "RPTR_WRITEBACK_ENABLE", 12, 12, &umr_bitfield_default },
	 { "RPTR_WRITEBACK_SWAP_ENABLE", 13, 13, &umr_bitfield_default },
	 { "RPTR_WRITEBACK_TIMER", 16, 20, &umr_bitfield_default },
	 { "RB_PRIV", 23, 23, &umr_bitfield_default },
	 { "RB_VMID", 24, 27, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA0_GFX_RB_BASE[] = {
	 { "ADDR", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA0_GFX_RB_BASE_HI[] = {
	 { "ADDR", 0, 23, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA0_GFX_RB_RPTR[] = {
	 { "OFFSET", 2, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA0_GFX_RB_WPTR[] = {
	 { "OFFSET", 2, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA0_GFX_RB_WPTR_POLL_CNTL[] = {
	 { "ENABLE", 0, 0, &umr_bitfield_default },
	 { "SWAP_ENABLE", 1, 1, &umr_bitfield_default },
	 { "FREQUENCY", 4, 15, &umr_bitfield_default },
	 { "IDLE_POLL_COUNT", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA0_GFX_RB_WPTR_POLL_ADDR_HI[] = {
	 { "ADDR", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA0_GFX_RB_WPTR_POLL_ADDR_LO[] = {
	 { "ADDR", 2, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA0_GFX_RB_RPTR_ADDR_HI[] = {
	 { "ADDR", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA0_GFX_RB_RPTR_ADDR_LO[] = {
	 { "ADDR", 2, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA0_GFX_IB_CNTL[] = {
	 { "IB_ENABLE", 0, 0, &umr_bitfield_default },
	 { "IB_SWAP_ENABLE", 4, 4, &umr_bitfield_default },
	 { "SWITCH_INSIDE_IB", 8, 8, &umr_bitfield_default },
	 { "CMD_VMID", 16, 19, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA0_GFX_IB_RPTR[] = {
	 { "OFFSET", 2, 21, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA0_GFX_IB_OFFSET[] = {
	 { "OFFSET", 2, 21, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA0_GFX_IB_BASE_LO[] = {
	 { "ADDR", 5, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA0_GFX_IB_BASE_HI[] = {
	 { "ADDR", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA0_GFX_IB_SIZE[] = {
	 { "SIZE", 0, 19, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA0_GFX_SKIP_CNTL[] = {
	 { "SKIP_COUNT", 0, 13, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA0_GFX_CONTEXT_STATUS[] = {
	 { "SELECTED", 0, 0, &umr_bitfield_default },
	 { "IDLE", 2, 2, &umr_bitfield_default },
	 { "EXPIRED", 3, 3, &umr_bitfield_default },
	 { "EXCEPTION", 4, 6, &umr_bitfield_default },
	 { "CTXSW_ABLE", 7, 7, &umr_bitfield_default },
	 { "CTXSW_READY", 8, 8, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA0_GFX_CONTEXT_CNTL[] = {
	 { "RESUME_CTX", 16, 16, &umr_bitfield_default },
	 { "SESSION_SEL", 24, 27, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA0_GFX_VIRTUAL_ADDR[] = {
	 { "ATC", 0, 0, &umr_bitfield_default },
	 { "PTR32", 4, 4, &umr_bitfield_default },
	 { "SHARED_BASE", 8, 10, &umr_bitfield_default },
	 { "VM_HOLE", 30, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA0_GFX_APE1_CNTL[] = {
	 { "BASE", 0, 15, &umr_bitfield_default },
	 { "LIMIT", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA0_GFX_WATERMARK[] = {
	 { "RD_OUTSTANDING", 0, 11, &umr_bitfield_default },
	 { "WR_OUTSTANDING", 16, 24, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA0_RLC0_RB_CNTL[] = {
	 { "RB_ENABLE", 0, 0, &umr_bitfield_default },
	 { "RB_SIZE", 1, 5, &umr_bitfield_default },
	 { "RB_SWAP_ENABLE", 9, 9, &umr_bitfield_default },
	 { "RPTR_WRITEBACK_ENABLE", 12, 12, &umr_bitfield_default },
	 { "RPTR_WRITEBACK_SWAP_ENABLE", 13, 13, &umr_bitfield_default },
	 { "RPTR_WRITEBACK_TIMER", 16, 20, &umr_bitfield_default },
	 { "RB_PRIV", 23, 23, &umr_bitfield_default },
	 { "RB_VMID", 24, 27, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA0_RLC0_RB_BASE[] = {
	 { "ADDR", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA0_RLC0_RB_BASE_HI[] = {
	 { "ADDR", 0, 23, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA0_RLC0_RB_RPTR[] = {
	 { "OFFSET", 2, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA0_RLC0_RB_WPTR[] = {
	 { "OFFSET", 2, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA0_RLC0_RB_WPTR_POLL_CNTL[] = {
	 { "ENABLE", 0, 0, &umr_bitfield_default },
	 { "SWAP_ENABLE", 1, 1, &umr_bitfield_default },
	 { "FREQUENCY", 4, 15, &umr_bitfield_default },
	 { "IDLE_POLL_COUNT", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA0_RLC0_RB_WPTR_POLL_ADDR_HI[] = {
	 { "ADDR", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA0_RLC0_RB_WPTR_POLL_ADDR_LO[] = {
	 { "ADDR", 2, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA0_RLC0_RB_RPTR_ADDR_HI[] = {
	 { "ADDR", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA0_RLC0_RB_RPTR_ADDR_LO[] = {
	 { "ADDR", 2, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA0_RLC0_IB_CNTL[] = {
	 { "IB_ENABLE", 0, 0, &umr_bitfield_default },
	 { "IB_SWAP_ENABLE", 4, 4, &umr_bitfield_default },
	 { "SWITCH_INSIDE_IB", 8, 8, &umr_bitfield_default },
	 { "CMD_VMID", 16, 19, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA0_RLC0_IB_RPTR[] = {
	 { "OFFSET", 2, 21, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA0_RLC0_IB_OFFSET[] = {
	 { "OFFSET", 2, 21, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA0_RLC0_IB_BASE_LO[] = {
	 { "ADDR", 5, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA0_RLC0_IB_BASE_HI[] = {
	 { "ADDR", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA0_RLC0_IB_SIZE[] = {
	 { "SIZE", 0, 19, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA0_RLC0_SKIP_CNTL[] = {
	 { "SKIP_COUNT", 0, 13, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA0_RLC0_CONTEXT_STATUS[] = {
	 { "SELECTED", 0, 0, &umr_bitfield_default },
	 { "IDLE", 2, 2, &umr_bitfield_default },
	 { "EXPIRED", 3, 3, &umr_bitfield_default },
	 { "EXCEPTION", 4, 6, &umr_bitfield_default },
	 { "CTXSW_ABLE", 7, 7, &umr_bitfield_default },
	 { "CTXSW_READY", 8, 8, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA0_RLC0_DOORBELL[] = {
	 { "OFFSET", 0, 20, &umr_bitfield_default },
	 { "ENABLE", 28, 28, &umr_bitfield_default },
	 { "CAPTURED", 30, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA0_RLC0_VIRTUAL_ADDR[] = {
	 { "ATC", 0, 0, &umr_bitfield_default },
	 { "PTR32", 4, 4, &umr_bitfield_default },
	 { "SHARED_BASE", 8, 10, &umr_bitfield_default },
	 { "VM_HOLE", 30, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA0_RLC0_APE1_CNTL[] = {
	 { "BASE", 0, 15, &umr_bitfield_default },
	 { "LIMIT", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA0_RLC0_DOORBELL_LOG[] = {
	 { "BE_ERROR", 0, 0, &umr_bitfield_default },
	 { "DATA", 2, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA0_RLC0_WATERMARK[] = {
	 { "RD_OUTSTANDING", 0, 11, &umr_bitfield_default },
	 { "WR_OUTSTANDING", 16, 24, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA0_RLC1_RB_CNTL[] = {
	 { "RB_ENABLE", 0, 0, &umr_bitfield_default },
	 { "RB_SIZE", 1, 5, &umr_bitfield_default },
	 { "RB_SWAP_ENABLE", 9, 9, &umr_bitfield_default },
	 { "RPTR_WRITEBACK_ENABLE", 12, 12, &umr_bitfield_default },
	 { "RPTR_WRITEBACK_SWAP_ENABLE", 13, 13, &umr_bitfield_default },
	 { "RPTR_WRITEBACK_TIMER", 16, 20, &umr_bitfield_default },
	 { "RB_PRIV", 23, 23, &umr_bitfield_default },
	 { "RB_VMID", 24, 27, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA0_RLC1_RB_BASE[] = {
	 { "ADDR", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA0_RLC1_RB_BASE_HI[] = {
	 { "ADDR", 0, 23, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA0_RLC1_RB_RPTR[] = {
	 { "OFFSET", 2, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA0_RLC1_RB_WPTR[] = {
	 { "OFFSET", 2, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA0_RLC1_RB_WPTR_POLL_CNTL[] = {
	 { "ENABLE", 0, 0, &umr_bitfield_default },
	 { "SWAP_ENABLE", 1, 1, &umr_bitfield_default },
	 { "FREQUENCY", 4, 15, &umr_bitfield_default },
	 { "IDLE_POLL_COUNT", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA0_RLC1_RB_WPTR_POLL_ADDR_HI[] = {
	 { "ADDR", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA0_RLC1_RB_WPTR_POLL_ADDR_LO[] = {
	 { "ADDR", 2, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA0_RLC1_RB_RPTR_ADDR_HI[] = {
	 { "ADDR", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA0_RLC1_RB_RPTR_ADDR_LO[] = {
	 { "ADDR", 2, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA0_RLC1_IB_CNTL[] = {
	 { "IB_ENABLE", 0, 0, &umr_bitfield_default },
	 { "IB_SWAP_ENABLE", 4, 4, &umr_bitfield_default },
	 { "SWITCH_INSIDE_IB", 8, 8, &umr_bitfield_default },
	 { "CMD_VMID", 16, 19, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA0_RLC1_IB_RPTR[] = {
	 { "OFFSET", 2, 21, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA0_RLC1_IB_OFFSET[] = {
	 { "OFFSET", 2, 21, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA0_RLC1_IB_BASE_LO[] = {
	 { "ADDR", 5, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA0_RLC1_IB_BASE_HI[] = {
	 { "ADDR", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA0_RLC1_IB_SIZE[] = {
	 { "SIZE", 0, 19, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA0_RLC1_SKIP_CNTL[] = {
	 { "SKIP_COUNT", 0, 13, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA0_RLC1_CONTEXT_STATUS[] = {
	 { "SELECTED", 0, 0, &umr_bitfield_default },
	 { "IDLE", 2, 2, &umr_bitfield_default },
	 { "EXPIRED", 3, 3, &umr_bitfield_default },
	 { "EXCEPTION", 4, 6, &umr_bitfield_default },
	 { "CTXSW_ABLE", 7, 7, &umr_bitfield_default },
	 { "CTXSW_READY", 8, 8, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA0_RLC1_DOORBELL[] = {
	 { "OFFSET", 0, 20, &umr_bitfield_default },
	 { "ENABLE", 28, 28, &umr_bitfield_default },
	 { "CAPTURED", 30, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA0_RLC1_VIRTUAL_ADDR[] = {
	 { "ATC", 0, 0, &umr_bitfield_default },
	 { "PTR32", 4, 4, &umr_bitfield_default },
	 { "SHARED_BASE", 8, 10, &umr_bitfield_default },
	 { "VM_HOLE", 30, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA0_RLC1_APE1_CNTL[] = {
	 { "BASE", 0, 15, &umr_bitfield_default },
	 { "LIMIT", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA0_RLC1_DOORBELL_LOG[] = {
	 { "BE_ERROR", 0, 0, &umr_bitfield_default },
	 { "DATA", 2, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA0_RLC1_WATERMARK[] = {
	 { "RD_OUTSTANDING", 0, 11, &umr_bitfield_default },
	 { "WR_OUTSTANDING", 16, 24, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA1_UCODE_ADDR[] = {
	 { "VALUE", 0, 10, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA1_UCODE_DATA[] = {
	 { "VALUE", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA1_POWER_CNTL[] = {
	 { "MEM_POWER_OVERRIDE", 8, 8, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA1_CLK_CTRL[] = {
	 { "ON_DELAY", 0, 3, &umr_bitfield_default },
	 { "OFF_HYSTERESIS", 4, 11, &umr_bitfield_default },
	 { "SOFT_OVERRIDE7", 24, 24, &umr_bitfield_default },
	 { "SOFT_OVERRIDE6", 25, 25, &umr_bitfield_default },
	 { "SOFT_OVERRIDE5", 26, 26, &umr_bitfield_default },
	 { "SOFT_OVERRIDE4", 27, 27, &umr_bitfield_default },
	 { "SOFT_OVERRIDE3", 28, 28, &umr_bitfield_default },
	 { "SOFT_OVERRIDE2", 29, 29, &umr_bitfield_default },
	 { "SOFT_OVERRIDE1", 30, 30, &umr_bitfield_default },
	 { "SOFT_OVERRIDE0", 31, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA1_CNTL[] = {
	 { "TRAP_ENABLE", 0, 0, &umr_bitfield_default },
	 { "SEM_INCOMPLETE_INT_ENABLE", 1, 1, &umr_bitfield_default },
	 { "SEM_WAIT_INT_ENABLE", 2, 2, &umr_bitfield_default },
	 { "DATA_SWAP_ENABLE", 3, 3, &umr_bitfield_default },
	 { "FENCE_SWAP_ENABLE", 4, 4, &umr_bitfield_default },
	 { "MC_WRREQ_CREDIT", 11, 16, &umr_bitfield_default },
	 { "AUTO_CTXSW_ENABLE", 18, 18, &umr_bitfield_default },
	 { "MC_RDREQ_CREDIT", 22, 27, &umr_bitfield_default },
	 { "CTXEMPTY_INT_ENABLE", 28, 28, &umr_bitfield_default },
	 { "FROZEN_INT_ENABLE", 29, 29, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA1_CHICKEN_BITS[] = {
	 { "COPY_EFFICIENCY_ENABLE", 0, 0, &umr_bitfield_default },
	 { "COPY_OVERLAP_ENABLE", 16, 16, &umr_bitfield_default },
	 { "SRBM_POLL_RETRYING", 20, 20, &umr_bitfield_default },
	 { "CG_STATUS_OUTPUT", 23, 23, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA1_TILING_CONFIG[] = {
	 { "PIPE_INTERLEAVE_SIZE", 4, 6, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA1_HASH[] = {
	 { "CHANNEL_BITS", 0, 2, &umr_bitfield_default },
	 { "BANK_BITS", 4, 6, &umr_bitfield_default },
	 { "CHANNEL_XOR_COUNT", 8, 10, &umr_bitfield_default },
	 { "BANK_XOR_COUNT", 12, 14, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA1_SEM_INCOMPLETE_TIMER_CNTL[] = {
	 { "TIMER", 0, 15, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA1_SEM_WAIT_FAIL_TIMER_CNTL[] = {
	 { "TIMER", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA1_RB_RPTR_FETCH[] = {
	 { "OFFSET", 2, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA1_IB_OFFSET_FETCH[] = {
	 { "OFFSET", 2, 21, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA1_PROGRAM[] = {
	 { "STREAM", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA1_STATUS_REG[] = {
	 { "IDLE", 0, 0, &umr_bitfield_default },
	 { "REG_IDLE", 1, 1, &umr_bitfield_default },
	 { "RB_EMPTY", 2, 2, &umr_bitfield_default },
	 { "RB_FULL", 3, 3, &umr_bitfield_default },
	 { "RB_CMD_IDLE", 4, 4, &umr_bitfield_default },
	 { "RB_CMD_FULL", 5, 5, &umr_bitfield_default },
	 { "IB_CMD_IDLE", 6, 6, &umr_bitfield_default },
	 { "IB_CMD_FULL", 7, 7, &umr_bitfield_default },
	 { "BLOCK_IDLE", 8, 8, &umr_bitfield_default },
	 { "INSIDE_IB", 9, 9, &umr_bitfield_default },
	 { "EX_IDLE", 10, 10, &umr_bitfield_default },
	 { "EX_IDLE_POLL_TIMER_EXPIRE", 11, 11, &umr_bitfield_default },
	 { "PACKET_READY", 12, 12, &umr_bitfield_default },
	 { "MC_WR_IDLE", 13, 13, &umr_bitfield_default },
	 { "SRBM_IDLE", 14, 14, &umr_bitfield_default },
	 { "CONTEXT_EMPTY", 15, 15, &umr_bitfield_default },
	 { "RB_MC_RREQ_IDLE", 17, 17, &umr_bitfield_default },
	 { "IB_MC_RREQ_IDLE", 18, 18, &umr_bitfield_default },
	 { "MC_RD_IDLE", 19, 19, &umr_bitfield_default },
	 { "MC_RD_RET_STALL", 21, 21, &umr_bitfield_default },
	 { "MC_RD_NO_POLL_IDLE", 22, 22, &umr_bitfield_default },
	 { "PREV_CMD_IDLE", 25, 25, &umr_bitfield_default },
	 { "SEM_IDLE", 26, 26, &umr_bitfield_default },
	 { "SEM_REQ_STALL", 27, 27, &umr_bitfield_default },
	 { "SEM_RESP_STATE", 28, 29, &umr_bitfield_default },
	 { "INT_IDLE", 30, 30, &umr_bitfield_default },
	 { "INT_REQ_STALL", 31, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA1_STATUS1_REG[] = {
	 { "CE_WREQ_IDLE", 0, 0, &umr_bitfield_default },
	 { "CE_WR_IDLE", 1, 1, &umr_bitfield_default },
	 { "CE_SPLIT_IDLE", 2, 2, &umr_bitfield_default },
	 { "CE_RREQ_IDLE", 3, 3, &umr_bitfield_default },
	 { "CE_OUT_IDLE", 4, 4, &umr_bitfield_default },
	 { "CE_IN_IDLE", 5, 5, &umr_bitfield_default },
	 { "CE_DST_IDLE", 6, 6, &umr_bitfield_default },
	 { "CE_AFIFO_FULL", 10, 10, &umr_bitfield_default },
	 { "CE_INFO_FULL", 13, 13, &umr_bitfield_default },
	 { "CE_INFO1_FULL", 14, 14, &umr_bitfield_default },
	 { "CE_RD_STALL", 17, 17, &umr_bitfield_default },
	 { "CE_WR_STALL", 18, 18, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA1_PERFMON_CNTL[] = {
	 { "PERF_ENABLE0", 0, 0, &umr_bitfield_default },
	 { "PERF_CLEAR0", 1, 1, &umr_bitfield_default },
	 { "PERF_SEL0", 2, 7, &umr_bitfield_default },
	 { "PERF_ENABLE1", 8, 8, &umr_bitfield_default },
	 { "PERF_CLEAR1", 9, 9, &umr_bitfield_default },
	 { "PERF_SEL1", 10, 15, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA1_PERFCOUNTER0_RESULT[] = {
	 { "PERF_COUNT", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA1_PERFCOUNTER1_RESULT[] = {
	 { "PERF_COUNT", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA1_F32_CNTL[] = {
	 { "HALT", 0, 0, &umr_bitfield_default },
	 { "STEP", 1, 1, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA1_FREEZE[] = {
	 { "FREEZE", 4, 4, &umr_bitfield_default },
	 { "FROZEN", 5, 5, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA1_PHASE0_QUANTUM[] = {
	 { "UNIT", 0, 3, &umr_bitfield_default },
	 { "VALUE", 8, 23, &umr_bitfield_default },
	 { "PREFER", 30, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA1_PHASE1_QUANTUM[] = {
	 { "UNIT", 0, 3, &umr_bitfield_default },
	 { "VALUE", 8, 23, &umr_bitfield_default },
	 { "PREFER", 30, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA1_EDC_CONFIG[] = {
	 { "DIS_EDC", 1, 1, &umr_bitfield_default },
	 { "ECC_INT_ENABLE", 2, 2, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA1_GFX_RB_CNTL[] = {
	 { "RB_ENABLE", 0, 0, &umr_bitfield_default },
	 { "RB_SIZE", 1, 5, &umr_bitfield_default },
	 { "RB_SWAP_ENABLE", 9, 9, &umr_bitfield_default },
	 { "RPTR_WRITEBACK_ENABLE", 12, 12, &umr_bitfield_default },
	 { "RPTR_WRITEBACK_SWAP_ENABLE", 13, 13, &umr_bitfield_default },
	 { "RPTR_WRITEBACK_TIMER", 16, 20, &umr_bitfield_default },
	 { "RB_PRIV", 23, 23, &umr_bitfield_default },
	 { "RB_VMID", 24, 27, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA1_GFX_RB_BASE[] = {
	 { "ADDR", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA1_GFX_RB_BASE_HI[] = {
	 { "ADDR", 0, 23, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA1_GFX_RB_RPTR[] = {
	 { "OFFSET", 2, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA1_GFX_RB_WPTR[] = {
	 { "OFFSET", 2, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA1_GFX_RB_WPTR_POLL_CNTL[] = {
	 { "ENABLE", 0, 0, &umr_bitfield_default },
	 { "SWAP_ENABLE", 1, 1, &umr_bitfield_default },
	 { "FREQUENCY", 4, 15, &umr_bitfield_default },
	 { "IDLE_POLL_COUNT", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA1_GFX_RB_WPTR_POLL_ADDR_HI[] = {
	 { "ADDR", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA1_GFX_RB_WPTR_POLL_ADDR_LO[] = {
	 { "ADDR", 2, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA1_GFX_RB_RPTR_ADDR_HI[] = {
	 { "ADDR", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA1_GFX_RB_RPTR_ADDR_LO[] = {
	 { "ADDR", 2, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA1_GFX_IB_CNTL[] = {
	 { "IB_ENABLE", 0, 0, &umr_bitfield_default },
	 { "IB_SWAP_ENABLE", 4, 4, &umr_bitfield_default },
	 { "SWITCH_INSIDE_IB", 8, 8, &umr_bitfield_default },
	 { "CMD_VMID", 16, 19, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA1_GFX_IB_RPTR[] = {
	 { "OFFSET", 2, 21, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA1_GFX_IB_OFFSET[] = {
	 { "OFFSET", 2, 21, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA1_GFX_IB_BASE_LO[] = {
	 { "ADDR", 5, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA1_GFX_IB_BASE_HI[] = {
	 { "ADDR", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA1_GFX_IB_SIZE[] = {
	 { "SIZE", 0, 19, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA1_GFX_SKIP_CNTL[] = {
	 { "SKIP_COUNT", 0, 13, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA1_GFX_CONTEXT_STATUS[] = {
	 { "SELECTED", 0, 0, &umr_bitfield_default },
	 { "IDLE", 2, 2, &umr_bitfield_default },
	 { "EXPIRED", 3, 3, &umr_bitfield_default },
	 { "EXCEPTION", 4, 6, &umr_bitfield_default },
	 { "CTXSW_ABLE", 7, 7, &umr_bitfield_default },
	 { "CTXSW_READY", 8, 8, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA1_GFX_CONTEXT_CNTL[] = {
	 { "RESUME_CTX", 16, 16, &umr_bitfield_default },
	 { "SESSION_SEL", 24, 27, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA1_GFX_VIRTUAL_ADDR[] = {
	 { "ATC", 0, 0, &umr_bitfield_default },
	 { "PTR32", 4, 4, &umr_bitfield_default },
	 { "SHARED_BASE", 8, 10, &umr_bitfield_default },
	 { "VM_HOLE", 30, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA1_GFX_APE1_CNTL[] = {
	 { "BASE", 0, 15, &umr_bitfield_default },
	 { "LIMIT", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA1_GFX_WATERMARK[] = {
	 { "RD_OUTSTANDING", 0, 11, &umr_bitfield_default },
	 { "WR_OUTSTANDING", 16, 24, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA1_RLC0_RB_CNTL[] = {
	 { "RB_ENABLE", 0, 0, &umr_bitfield_default },
	 { "RB_SIZE", 1, 5, &umr_bitfield_default },
	 { "RB_SWAP_ENABLE", 9, 9, &umr_bitfield_default },
	 { "RPTR_WRITEBACK_ENABLE", 12, 12, &umr_bitfield_default },
	 { "RPTR_WRITEBACK_SWAP_ENABLE", 13, 13, &umr_bitfield_default },
	 { "RPTR_WRITEBACK_TIMER", 16, 20, &umr_bitfield_default },
	 { "RB_PRIV", 23, 23, &umr_bitfield_default },
	 { "RB_VMID", 24, 27, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA1_RLC0_RB_BASE[] = {
	 { "ADDR", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA1_RLC0_RB_BASE_HI[] = {
	 { "ADDR", 0, 23, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA1_RLC0_RB_RPTR[] = {
	 { "OFFSET", 2, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA1_RLC0_RB_WPTR[] = {
	 { "OFFSET", 2, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA1_RLC0_RB_WPTR_POLL_CNTL[] = {
	 { "ENABLE", 0, 0, &umr_bitfield_default },
	 { "SWAP_ENABLE", 1, 1, &umr_bitfield_default },
	 { "FREQUENCY", 4, 15, &umr_bitfield_default },
	 { "IDLE_POLL_COUNT", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA1_RLC0_RB_WPTR_POLL_ADDR_HI[] = {
	 { "ADDR", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA1_RLC0_RB_WPTR_POLL_ADDR_LO[] = {
	 { "ADDR", 2, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA1_RLC0_RB_RPTR_ADDR_HI[] = {
	 { "ADDR", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA1_RLC0_RB_RPTR_ADDR_LO[] = {
	 { "ADDR", 2, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA1_RLC0_IB_CNTL[] = {
	 { "IB_ENABLE", 0, 0, &umr_bitfield_default },
	 { "IB_SWAP_ENABLE", 4, 4, &umr_bitfield_default },
	 { "SWITCH_INSIDE_IB", 8, 8, &umr_bitfield_default },
	 { "CMD_VMID", 16, 19, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA1_RLC0_IB_RPTR[] = {
	 { "OFFSET", 2, 21, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA1_RLC0_IB_OFFSET[] = {
	 { "OFFSET", 2, 21, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA1_RLC0_IB_BASE_LO[] = {
	 { "ADDR", 5, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA1_RLC0_IB_BASE_HI[] = {
	 { "ADDR", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA1_RLC0_IB_SIZE[] = {
	 { "SIZE", 0, 19, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA1_RLC0_SKIP_CNTL[] = {
	 { "SKIP_COUNT", 0, 13, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA1_RLC0_CONTEXT_STATUS[] = {
	 { "SELECTED", 0, 0, &umr_bitfield_default },
	 { "IDLE", 2, 2, &umr_bitfield_default },
	 { "EXPIRED", 3, 3, &umr_bitfield_default },
	 { "EXCEPTION", 4, 6, &umr_bitfield_default },
	 { "CTXSW_ABLE", 7, 7, &umr_bitfield_default },
	 { "CTXSW_READY", 8, 8, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA1_RLC0_DOORBELL[] = {
	 { "OFFSET", 0, 20, &umr_bitfield_default },
	 { "ENABLE", 28, 28, &umr_bitfield_default },
	 { "CAPTURED", 30, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA1_RLC0_VIRTUAL_ADDR[] = {
	 { "ATC", 0, 0, &umr_bitfield_default },
	 { "PTR32", 4, 4, &umr_bitfield_default },
	 { "SHARED_BASE", 8, 10, &umr_bitfield_default },
	 { "VM_HOLE", 30, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA1_RLC0_APE1_CNTL[] = {
	 { "BASE", 0, 15, &umr_bitfield_default },
	 { "LIMIT", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA1_RLC0_DOORBELL_LOG[] = {
	 { "BE_ERROR", 0, 0, &umr_bitfield_default },
	 { "DATA", 2, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA1_RLC0_WATERMARK[] = {
	 { "RD_OUTSTANDING", 0, 11, &umr_bitfield_default },
	 { "WR_OUTSTANDING", 16, 24, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA1_RLC1_RB_CNTL[] = {
	 { "RB_ENABLE", 0, 0, &umr_bitfield_default },
	 { "RB_SIZE", 1, 5, &umr_bitfield_default },
	 { "RB_SWAP_ENABLE", 9, 9, &umr_bitfield_default },
	 { "RPTR_WRITEBACK_ENABLE", 12, 12, &umr_bitfield_default },
	 { "RPTR_WRITEBACK_SWAP_ENABLE", 13, 13, &umr_bitfield_default },
	 { "RPTR_WRITEBACK_TIMER", 16, 20, &umr_bitfield_default },
	 { "RB_PRIV", 23, 23, &umr_bitfield_default },
	 { "RB_VMID", 24, 27, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA1_RLC1_RB_BASE[] = {
	 { "ADDR", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA1_RLC1_RB_BASE_HI[] = {
	 { "ADDR", 0, 23, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA1_RLC1_RB_RPTR[] = {
	 { "OFFSET", 2, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA1_RLC1_RB_WPTR[] = {
	 { "OFFSET", 2, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA1_RLC1_RB_WPTR_POLL_CNTL[] = {
	 { "ENABLE", 0, 0, &umr_bitfield_default },
	 { "SWAP_ENABLE", 1, 1, &umr_bitfield_default },
	 { "FREQUENCY", 4, 15, &umr_bitfield_default },
	 { "IDLE_POLL_COUNT", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA1_RLC1_RB_WPTR_POLL_ADDR_HI[] = {
	 { "ADDR", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA1_RLC1_RB_WPTR_POLL_ADDR_LO[] = {
	 { "ADDR", 2, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA1_RLC1_RB_RPTR_ADDR_HI[] = {
	 { "ADDR", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA1_RLC1_RB_RPTR_ADDR_LO[] = {
	 { "ADDR", 2, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA1_RLC1_IB_CNTL[] = {
	 { "IB_ENABLE", 0, 0, &umr_bitfield_default },
	 { "IB_SWAP_ENABLE", 4, 4, &umr_bitfield_default },
	 { "SWITCH_INSIDE_IB", 8, 8, &umr_bitfield_default },
	 { "CMD_VMID", 16, 19, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA1_RLC1_IB_RPTR[] = {
	 { "OFFSET", 2, 21, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA1_RLC1_IB_OFFSET[] = {
	 { "OFFSET", 2, 21, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA1_RLC1_IB_BASE_LO[] = {
	 { "ADDR", 5, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA1_RLC1_IB_BASE_HI[] = {
	 { "ADDR", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA1_RLC1_IB_SIZE[] = {
	 { "SIZE", 0, 19, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA1_RLC1_SKIP_CNTL[] = {
	 { "SKIP_COUNT", 0, 13, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA1_RLC1_CONTEXT_STATUS[] = {
	 { "SELECTED", 0, 0, &umr_bitfield_default },
	 { "IDLE", 2, 2, &umr_bitfield_default },
	 { "EXPIRED", 3, 3, &umr_bitfield_default },
	 { "EXCEPTION", 4, 6, &umr_bitfield_default },
	 { "CTXSW_ABLE", 7, 7, &umr_bitfield_default },
	 { "CTXSW_READY", 8, 8, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA1_RLC1_DOORBELL[] = {
	 { "OFFSET", 0, 20, &umr_bitfield_default },
	 { "ENABLE", 28, 28, &umr_bitfield_default },
	 { "CAPTURED", 30, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA1_RLC1_VIRTUAL_ADDR[] = {
	 { "ATC", 0, 0, &umr_bitfield_default },
	 { "PTR32", 4, 4, &umr_bitfield_default },
	 { "SHARED_BASE", 8, 10, &umr_bitfield_default },
	 { "VM_HOLE", 30, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA1_RLC1_APE1_CNTL[] = {
	 { "BASE", 0, 15, &umr_bitfield_default },
	 { "LIMIT", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA1_RLC1_DOORBELL_LOG[] = {
	 { "BE_ERROR", 0, 0, &umr_bitfield_default },
	 { "DATA", 2, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA1_RLC1_WATERMARK[] = {
	 { "RD_OUTSTANDING", 0, 11, &umr_bitfield_default },
	 { "WR_OUTSTANDING", 16, 24, &umr_bitfield_default },
};
static struct umr_bitfield ixEXP1[] = {
	 { "RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSRBM_CNTL[] = {
	 { "READ_TIMEOUT", 0, 12, &umr_bitfield_default },
	 { "PWR_REQUEST_HALT", 16, 16, &umr_bitfield_default },
	 { "COMBINE_SYSTEM_MC", 17, 17, &umr_bitfield_default },
};
static struct umr_bitfield mmSRBM_GFX_CNTL[] = {
	 { "PIPEID", 0, 1, &umr_bitfield_default },
	 { "MEID", 2, 3, &umr_bitfield_default },
	 { "VMID", 4, 7, &umr_bitfield_default },
	 { "QUEUEID", 8, 10, &umr_bitfield_default },
};
static struct umr_bitfield mmSRBM_STATUS2[] = {
	 { "SDMA_RQ_PENDING", 0, 0, &umr_bitfield_default },
	 { "TST_RQ_PENDING", 1, 1, &umr_bitfield_default },
	 { "SDMA1_RQ_PENDING", 2, 2, &umr_bitfield_default },
	 { "VCE_RQ_PENDING", 3, 3, &umr_bitfield_default },
	 { "XSP_BUSY", 4, 4, &umr_bitfield_default },
	 { "SDMA_BUSY", 5, 5, &umr_bitfield_default },
	 { "SDMA1_BUSY", 6, 6, &umr_bitfield_default },
	 { "VCE_BUSY", 7, 7, &umr_bitfield_default },
	 { "XDMA_BUSY", 8, 8, &umr_bitfield_default },
	 { "CHUB_BUSY", 9, 9, &umr_bitfield_default },
};
static struct umr_bitfield mmSRBM_STATUS[] = {
	 { "UVD_RQ_PENDING", 1, 1, &umr_bitfield_default },
	 { "SAM_RQ_PENDING", 2, 2, &umr_bitfield_default },
	 { "ACP_RQ_PENDING", 3, 3, &umr_bitfield_default },
	 { "SMU_RQ_PENDING", 4, 4, &umr_bitfield_default },
	 { "GRBM_RQ_PENDING", 5, 5, &umr_bitfield_default },
	 { "HI_RQ_PENDING", 6, 6, &umr_bitfield_default },
	 { "IO_EXTERN_SIGNAL", 7, 7, &umr_bitfield_default },
	 { "VMC_BUSY", 8, 8, &umr_bitfield_default },
	 { "MCB_BUSY", 9, 9, &umr_bitfield_default },
	 { "MCB_NON_DISPLAY_BUSY", 10, 10, &umr_bitfield_default },
	 { "MCC_BUSY", 11, 11, &umr_bitfield_default },
	 { "MCD_BUSY", 12, 12, &umr_bitfield_default },
	 { "SEM_BUSY", 14, 14, &umr_bitfield_default },
	 { "ACP_BUSY", 16, 16, &umr_bitfield_default },
	 { "IH_BUSY", 17, 17, &umr_bitfield_default },
	 { "UVD_BUSY", 19, 19, &umr_bitfield_default },
	 { "SAM_BUSY", 20, 20, &umr_bitfield_default },
	 { "BIF_BUSY", 29, 29, &umr_bitfield_default },
};
static struct umr_bitfield mmSRBM_CAM_INDEX[] = {
	 { "CAM_INDEX", 0, 2, &umr_bitfield_default },
};
static struct umr_bitfield mmSRBM_CAM_DATA[] = {
	 { "CAM_ADDR", 0, 15, &umr_bitfield_default },
	 { "CAM_REMAPADDR", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSRBM_SOFT_RESET[] = {
	 { "SOFT_RESET_BIF", 1, 1, &umr_bitfield_default },
	 { "SOFT_RESET_ROPLL", 4, 4, &umr_bitfield_default },
	 { "SOFT_RESET_DC", 5, 5, &umr_bitfield_default },
	 { "SOFT_RESET_SDMA1", 6, 6, &umr_bitfield_default },
	 { "SOFT_RESET_GRBM", 8, 8, &umr_bitfield_default },
	 { "SOFT_RESET_HDP", 9, 9, &umr_bitfield_default },
	 { "SOFT_RESET_IH", 10, 10, &umr_bitfield_default },
	 { "SOFT_RESET_MC", 11, 11, &umr_bitfield_default },
	 { "SOFT_RESET_CHUB", 12, 12, &umr_bitfield_default },
	 { "SOFT_RESET_ROM", 14, 14, &umr_bitfield_default },
	 { "SOFT_RESET_SEM", 15, 15, &umr_bitfield_default },
	 { "SOFT_RESET_SMU", 16, 16, &umr_bitfield_default },
	 { "SOFT_RESET_VMC", 17, 17, &umr_bitfield_default },
	 { "SOFT_RESET_UVD", 18, 18, &umr_bitfield_default },
	 { "SOFT_RESET_XSP", 19, 19, &umr_bitfield_default },
	 { "SOFT_RESET_SDMA", 20, 20, &umr_bitfield_default },
	 { "SOFT_RESET_TST", 21, 21, &umr_bitfield_default },
	 { "SOFT_RESET_REGBB", 22, 22, &umr_bitfield_default },
	 { "SOFT_RESET_ORB", 23, 23, &umr_bitfield_default },
	 { "SOFT_RESET_VCE", 24, 24, &umr_bitfield_default },
	 { "SOFT_RESET_XDMA", 25, 25, &umr_bitfield_default },
	 { "SOFT_RESET_ACP", 26, 26, &umr_bitfield_default },
	 { "SOFT_RESET_SAM", 27, 27, &umr_bitfield_default },
};
static struct umr_bitfield mmSRBM_DEBUG_CNTL[] = {
	 { "SRBM_DEBUG_INDEX", 0, 5, &umr_bitfield_default },
};
static struct umr_bitfield mmSRBM_DEBUG_DATA[] = {
	 { "DATA", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSRBM_CHIP_REVISION[] = {
	 { "CHIP_REVISION", 0, 7, &umr_bitfield_default },
};
static struct umr_bitfield mmCC_SYS_RB_REDUNDANCY[] = {
	 { "FAILED_RB0", 8, 11, &umr_bitfield_default },
	 { "EN_REDUNDANCY0", 12, 12, &umr_bitfield_default },
	 { "FAILED_RB1", 16, 19, &umr_bitfield_default },
	 { "EN_REDUNDANCY1", 20, 20, &umr_bitfield_default },
};
static struct umr_bitfield mmCC_SYS_RB_BACKEND_DISABLE[] = {
	 { "BACKEND_DISABLE", 16, 23, &umr_bitfield_default },
};
static struct umr_bitfield mmGC_USER_SYS_RB_BACKEND_DISABLE[] = {
	 { "BACKEND_DISABLE", 16, 23, &umr_bitfield_default },
};
static struct umr_bitfield mmSRBM_DEBUG[] = {
	 { "IGNORE_RDY", 0, 0, &umr_bitfield_default },
	 { "DISABLE_READ_TIMEOUT", 1, 1, &umr_bitfield_default },
	 { "SNAPSHOT_FREE_CNTRS", 2, 2, &umr_bitfield_default },
	 { "SYS_CLOCK_DOMAIN_OVERRIDE", 4, 4, &umr_bitfield_default },
	 { "VCE_CLOCK_DOMAIN_OVERRIDE", 5, 5, &umr_bitfield_default },
	 { "UVD_CLOCK_DOMAIN_OVERRIDE", 6, 6, &umr_bitfield_default },
	 { "SDMA_CLOCK_DOMAIN_OVERRIDE", 7, 7, &umr_bitfield_default },
	 { "MC_CLOCK_DOMAIN_OVERRIDE", 8, 8, &umr_bitfield_default },
	 { "SAM_CLOCK_DOMAIN_OVERRIDE", 9, 9, &umr_bitfield_default },
};
static struct umr_bitfield mmSRBM_DEBUG_SNAPSHOT[] = {
	 { "MCB_RDY", 0, 0, &umr_bitfield_default },
	 { "ROPLL_RDY", 1, 1, &umr_bitfield_default },
	 { "SMU_RDY", 2, 2, &umr_bitfield_default },
	 { "SAM_RDY", 3, 3, &umr_bitfield_default },
	 { "ACP_RDY", 4, 4, &umr_bitfield_default },
	 { "GRBM_RDY", 5, 5, &umr_bitfield_default },
	 { "DC_RDY", 6, 6, &umr_bitfield_default },
	 { "BIF_RDY", 7, 7, &umr_bitfield_default },
	 { "XDMA_RDY", 8, 8, &umr_bitfield_default },
	 { "UVD_RDY", 9, 9, &umr_bitfield_default },
	 { "XSP_RDY", 10, 10, &umr_bitfield_default },
	 { "REGBB_RDY", 11, 11, &umr_bitfield_default },
	 { "ORB_RDY", 12, 12, &umr_bitfield_default },
	 { "MCD7_RDY", 13, 13, &umr_bitfield_default },
	 { "MCD6_RDY", 14, 14, &umr_bitfield_default },
	 { "MCD5_RDY", 15, 15, &umr_bitfield_default },
	 { "MCD4_RDY", 16, 16, &umr_bitfield_default },
	 { "MCD3_RDY", 17, 17, &umr_bitfield_default },
	 { "MCD2_RDY", 18, 18, &umr_bitfield_default },
	 { "MCD1_RDY", 19, 19, &umr_bitfield_default },
	 { "MCD0_RDY", 20, 20, &umr_bitfield_default },
	 { "MCC7_RDY", 21, 21, &umr_bitfield_default },
	 { "MCC6_RDY", 22, 22, &umr_bitfield_default },
	 { "MCC5_RDY", 23, 23, &umr_bitfield_default },
	 { "MCC4_RDY", 24, 24, &umr_bitfield_default },
	 { "MCC3_RDY", 25, 25, &umr_bitfield_default },
	 { "MCC2_RDY", 26, 26, &umr_bitfield_default },
	 { "MCC1_RDY", 27, 27, &umr_bitfield_default },
	 { "MCC0_RDY", 28, 28, &umr_bitfield_default },
	 { "VCE_RDY", 29, 29, &umr_bitfield_default },
};
static struct umr_bitfield mmSRBM_READ_ERROR[] = {
	 { "READ_ADDRESS", 2, 17, &umr_bitfield_default },
	 { "READ_REQUESTER_VCE", 20, 20, &umr_bitfield_default },
	 { "READ_REQUESTER_SDMA1", 21, 21, &umr_bitfield_default },
	 { "READ_REQUESTER_TST", 22, 22, &umr_bitfield_default },
	 { "READ_REQUESTER_SAM", 23, 23, &umr_bitfield_default },
	 { "READ_REQUESTER_HI", 24, 24, &umr_bitfield_default },
	 { "READ_REQUESTER_GRBM", 25, 25, &umr_bitfield_default },
	 { "READ_REQUESTER_SMU", 26, 26, &umr_bitfield_default },
	 { "READ_REQUESTER_ACP", 27, 27, &umr_bitfield_default },
	 { "READ_REQUESTER_SDMA", 28, 28, &umr_bitfield_default },
	 { "READ_REQUESTER_UVD", 29, 29, &umr_bitfield_default },
	 { "READ_ERROR", 31, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSRBM_INT_CNTL[] = {
	 { "RDERR_INT_MASK", 0, 0, &umr_bitfield_default },
};
static struct umr_bitfield mmSRBM_INT_STATUS[] = {
	 { "RDERR_INT_STAT", 0, 0, &umr_bitfield_default },
};
static struct umr_bitfield mmSRBM_INT_ACK[] = {
	 { "RDERR_INT_ACK", 0, 0, &umr_bitfield_default },
};
static struct umr_bitfield mmSRBM_MC_CLKEN_CNTL[] = {
	 { "PREFIX_DELAY_CNT", 0, 3, &umr_bitfield_default },
	 { "POST_DELAY_CNT", 8, 12, &umr_bitfield_default },
};
static struct umr_bitfield mmSRBM_SYS_CLKEN_CNTL[] = {
	 { "PREFIX_DELAY_CNT", 0, 3, &umr_bitfield_default },
	 { "POST_DELAY_CNT", 8, 12, &umr_bitfield_default },
};
static struct umr_bitfield mmSRBM_VCE_CLKEN_CNTL[] = {
	 { "PREFIX_DELAY_CNT", 0, 3, &umr_bitfield_default },
	 { "POST_DELAY_CNT", 8, 12, &umr_bitfield_default },
};
static struct umr_bitfield mmSRBM_UVD_CLKEN_CNTL[] = {
	 { "PREFIX_DELAY_CNT", 0, 3, &umr_bitfield_default },
	 { "POST_DELAY_CNT", 8, 12, &umr_bitfield_default },
};
static struct umr_bitfield mmSRBM_SDMA_CLKEN_CNTL[] = {
	 { "PREFIX_DELAY_CNT", 0, 3, &umr_bitfield_default },
	 { "POST_DELAY_CNT", 8, 12, &umr_bitfield_default },
};
static struct umr_bitfield mmSRBM_SAM_CLKEN_CNTL[] = {
	 { "PREFIX_DELAY_CNT", 0, 3, &umr_bitfield_default },
	 { "POST_DELAY_CNT", 8, 12, &umr_bitfield_default },
};
static struct umr_bitfield ixEXP2[] = {
	 { "RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmXDMA_MSTR_CNTL[] = {
	 { "XDMA_MSTR_ALPHA_POSITION", 12, 13, &umr_bitfield_default },
	 { "XDMA_MSTR_MEM_READY", 14, 14, &umr_bitfield_default },
	 { "XDMA_MSTR_ENABLE", 16, 16, &umr_bitfield_default },
	 { "XDMA_MSTR_DEBUG_MODE", 18, 18, &umr_bitfield_default },
	 { "XDMA_MSTR_LAT_TEST_EN", 19, 19, &umr_bitfield_default },
	 { "XDMA_MSTR_SOFT_RESET", 20, 20, &umr_bitfield_default },
	 { "XDMA_MSTR_BIF_STALL_EN", 21, 21, &umr_bitfield_default },
};
static struct umr_bitfield mmXDMA_MSTR_STATUS[] = {
	 { "XDMA_MSTR_VCOUNT_CURRENT", 0, 13, &umr_bitfield_default },
	 { "XDMA_MSTR_WRITE_LINE_CURRENT", 16, 27, &umr_bitfield_default },
	 { "XDMA_MSTR_STATUS_SELECT", 28, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmXDMA_MSTR_MEM_CLIENT_CONFIG[] = {
	 { "XDMA_MSTR_MEM_CLIENT_SWAP", 8, 9, &umr_bitfield_default },
	 { "XDMA_MSTR_MEM_CLIENT_VMID", 12, 15, &umr_bitfield_default },
	 { "XDMA_MSTR_MEM_CLIENT_PRIV", 16, 16, &umr_bitfield_default },
};
static struct umr_bitfield mmXDMA_MSTR_LOCAL_SURFACE_BASE_ADDR[] = {
	 { "XDMA_MSTR_LOCAL_SURFACE_BASE_ADDR", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmXDMA_MSTR_LOCAL_SURFACE_BASE_ADDR_HIGH[] = {
	 { "XDMA_MSTR_LOCAL_SURFACE_BASE_ADDR_HIGH", 0, 7, &umr_bitfield_default },
};
static struct umr_bitfield mmXDMA_MSTR_LOCAL_SURFACE_PITCH[] = {
	 { "XDMA_MSTR_LOCAL_SURFACE_PITCH", 0, 13, &umr_bitfield_default },
};
static struct umr_bitfield mmXDMA_MSTR_CMD_URGENT_CNTL[] = {
	 { "XDMA_MSTR_CMD_CLIENT_STALL", 0, 0, &umr_bitfield_default },
	 { "XDMA_MSTR_CMD_URGENT_LEVEL", 8, 11, &umr_bitfield_default },
	 { "XDMA_MSTR_CMD_STALL_DELAY", 12, 15, &umr_bitfield_default },
};
static struct umr_bitfield mmXDMA_MSTR_MEM_URGENT_CNTL[] = {
	 { "XDMA_MSTR_MEM_CLIENT_STALL", 0, 0, &umr_bitfield_default },
	 { "XDMA_MSTR_MEM_URGENT_LIMIT", 4, 7, &umr_bitfield_default },
	 { "XDMA_MSTR_MEM_URGENT_LEVEL", 8, 11, &umr_bitfield_default },
	 { "XDMA_MSTR_MEM_STALL_DELAY", 12, 15, &umr_bitfield_default },
	 { "XDMA_MSTR_MEM_URGENT_TIMER", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmXDMA_MSTR_MEM_UNDERFLOW_CONFIG[] = {
	 { "XDMA_MSTR_UNDERFLOW_LIMIT", 0, 15, &umr_bitfield_default },
	 { "XDMA_MSTR_UNDERFLOW_TIMER", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmXDMA_MSTR_PCIE_NACK_STATUS[] = {
	 { "XDMA_MSTR_PCIE_NACK_TAG", 0, 9, &umr_bitfield_default },
	 { "XDMA_MSTR_PCIE_NACK", 12, 13, &umr_bitfield_default },
	 { "XDMA_MSTR_PCIE_NACK_CLR", 16, 16, &umr_bitfield_default },
};
static struct umr_bitfield mmXDMA_MSTR_MEM_NACK_STATUS[] = {
	 { "XDMA_MSTR_MEM_NACK_TAG", 0, 9, &umr_bitfield_default },
	 { "XDMA_MSTR_MEM_NACK", 12, 13, &umr_bitfield_default },
	 { "XDMA_MSTR_MEM_NACK_CLR", 16, 16, &umr_bitfield_default },
};
static struct umr_bitfield mmXDMA_MSTR_VSYNC_GSL_CHECK[] = {
	 { "XDMA_MSTR_VSYNC_GSL_CHECK_SEL", 0, 2, &umr_bitfield_default },
	 { "XDMA_MSTR_VSYNC_GSL_CHECK_V_COUNT", 8, 21, &umr_bitfield_default },
};
static struct umr_bitfield ixKHFS0[] = {
	 { "RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixEXP3[] = {
	 { "RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmXDMA_MSTR_PIPE_CNTL[] = {
	 { "XDMA_MSTR_CACHE_LINES", 0, 7, &umr_bitfield_default },
	 { "XDMA_MSTR_READ_REQUEST", 8, 8, &umr_bitfield_default },
	 { "XDMA_MSTR_PIPE_FRAME_MODE", 9, 9, &umr_bitfield_default },
	 { "XDMA_MSTR_PIPE_SOFT_RESET", 10, 10, &umr_bitfield_default },
	 { "XDMA_MSTR_CACHE_INVALIDATE", 11, 11, &umr_bitfield_default },
	 { "XDMA_MSTR_REQUEST_CHANNEL_ID", 12, 14, &umr_bitfield_default },
	 { "XDMA_MSTR_FLIP_MODE", 15, 15, &umr_bitfield_default },
	 { "XDMA_MSTR_REQUEST_MIN", 16, 23, &umr_bitfield_default },
	 { "XDMA_MSTR_PIPE_ACTIVE", 24, 24, &umr_bitfield_default },
	 { "XDMA_MSTR_PIPE_FLUSHING", 25, 25, &umr_bitfield_default },
	 { "XDMA_MSTR_PIPE_FLIP_PENDING", 26, 26, &umr_bitfield_default },
	 { "XDMA_MSTR_VSYNC_GSL_ENABLE", 27, 27, &umr_bitfield_default },
};
static struct umr_bitfield mmXDMA_MSTR_READ_COMMAND[] = {
	 { "XDMA_MSTR_REQUEST_SIZE", 0, 13, &umr_bitfield_default },
	 { "XDMA_MSTR_REQUEST_PREFETCH", 16, 29, &umr_bitfield_default },
};
static struct umr_bitfield mmXDMA_MSTR_CHANNEL_DIM[] = {
	 { "XDMA_MSTR_CHANNEL_WIDTH", 0, 13, &umr_bitfield_default },
	 { "XDMA_MSTR_CHANNEL_HEIGHT", 16, 29, &umr_bitfield_default },
};
static struct umr_bitfield mmXDMA_MSTR_HEIGHT[] = {
	 { "XDMA_MSTR_ACTIVE_HEIGHT", 0, 13, &umr_bitfield_default },
	 { "XDMA_MSTR_FRAME_HEIGHT", 16, 29, &umr_bitfield_default },
};
static struct umr_bitfield mmXDMA_MSTR_REMOTE_SURFACE_BASE[] = {
	 { "XDMA_MSTR_REMOTE_SURFACE_BASE", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmXDMA_MSTR_REMOTE_SURFACE_BASE_HIGH[] = {
	 { "XDMA_MSTR_REMOTE_SURFACE_BASE_HIGH", 0, 7, &umr_bitfield_default },
};
static struct umr_bitfield mmXDMA_MSTR_REMOTE_GPU_ADDRESS[] = {
	 { "XDMA_MSTR_REMOTE_GPU_ADDRESS", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmXDMA_MSTR_REMOTE_GPU_ADDRESS_HIGH[] = {
	 { "XDMA_MSTR_REMOTE_GPU_ADDRESS_HIGH", 0, 7, &umr_bitfield_default },
};
static struct umr_bitfield mmXDMA_MSTR_CACHE_BASE_ADDR[] = {
	 { "XDMA_MSTR_CACHE_BASE_ADDR", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmXDMA_MSTR_CACHE_BASE_ADDR_HIGH[] = {
	 { "XDMA_MSTR_CACHE_BASE_ADDR_HIGH", 0, 7, &umr_bitfield_default },
};
static struct umr_bitfield mmXDMA_MSTR_CACHE_PITCH[] = {
	 { "XDMA_MSTR_CACHE_PITCH", 0, 13, &umr_bitfield_default },
};
static struct umr_bitfield mmXDMA_MSTR_CHANNEL_START[] = {
	 { "XDMA_MSTR_CHANNEL_START_X", 0, 13, &umr_bitfield_default },
	 { "XDMA_MSTR_CHANNEL_START_Y", 16, 29, &umr_bitfield_default },
};
static struct umr_bitfield mmXDMA_MSTR_MEM_OVERFLOW_CNTL[] = {
	 { "XDMA_MSTR_OVERFLOW_COUNT", 0, 15, &umr_bitfield_default },
	 { "XDMA_MSTR_OVERFLOW_THRESHOLD", 16, 29, &umr_bitfield_default },
	 { "XDMA_MSTR_OVERFLOW_BP_ENABLE", 30, 30, &umr_bitfield_default },
	 { "XDMA_MSTR_OVERFLOW_COUNT_ENABLE", 31, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmXDMA_MSTR_MEM_UNDERFLOW_CNTL[] = {
	 { "XDMA_MSTR_UNDERFLOW_COUNT", 0, 15, &umr_bitfield_default },
	 { "XDMA_MSTR_UNDERFLOW_THRESHOLD", 16, 29, &umr_bitfield_default },
	 { "XDMA_MSTR_UNDERFLOW_DETECT_ENABLE", 31, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmXDMA_MSTR_PERFMEAS_STATUS[] = {
	 { "XDMA_MSTR_PERFMEAS_DATA", 0, 23, &umr_bitfield_default },
	 { "XDMA_MSTR_PERFMEAS_INDEX", 24, 26, &umr_bitfield_default },
	 { "XDMA_MSTR_PERFMEAS_INDEX_MODE", 30, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmXDMA_MSTR_PERFMEAS_CNTL[] = {
	 { "XDMA_MSTR_CACHE_BW_MEAS_ITER", 0, 11, &umr_bitfield_default },
	 { "XDMA_MSTR_CACHE_BW_SEGID_SEL", 12, 16, &umr_bitfield_default },
	 { "XDMA_MSTR_CACHE_BW_COUNTER_RST", 17, 17, &umr_bitfield_default },
	 { "XDMA_MSTR_LT_MEAS_ITER", 19, 30, &umr_bitfield_default },
	 { "XDMA_MSTR_LT_COUNTER_RST", 31, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixEXP4[] = {
	 { "RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmXDMA_SLV_CNTL[] = {
	 { "XDMA_SLV_READ_LINES", 0, 0, &umr_bitfield_default },
	 { "XDMA_SLV_MEM_READY", 9, 9, &umr_bitfield_default },
	 { "XDMA_SLV_ACTIVE", 10, 10, &umr_bitfield_default },
	 { "XDMA_SLV_ALPHA_POSITION", 12, 13, &umr_bitfield_default },
	 { "XDMA_SLV_ENABLE", 16, 16, &umr_bitfield_default },
	 { "XDMA_SLV_READ_LAT_TEST_EN", 19, 19, &umr_bitfield_default },
	 { "XDMA_SLV_SOFT_RESET", 20, 20, &umr_bitfield_default },
	 { "XDMA_SLV_REQ_MAXED_OUT", 24, 24, &umr_bitfield_default },
};
static struct umr_bitfield mmXDMA_SLV_MEM_CLIENT_CONFIG[] = {
	 { "XDMA_SLV_MEM_CLIENT_SWAP", 8, 9, &umr_bitfield_default },
	 { "XDMA_SLV_MEM_CLIENT_VMID", 12, 15, &umr_bitfield_default },
	 { "XDMA_SLV_MEM_CLIENT_PRIV", 16, 16, &umr_bitfield_default },
};
static struct umr_bitfield mmXDMA_SLV_SLS_PITCH[] = {
	 { "XDMA_SLV_SLS_PITCH", 0, 13, &umr_bitfield_default },
	 { "XDMA_SLV_SLS_WIDTH", 16, 29, &umr_bitfield_default },
};
static struct umr_bitfield mmXDMA_SLV_READ_URGENT_CNTL[] = {
	 { "XDMA_SLV_READ_CLIENT_STALL", 0, 0, &umr_bitfield_default },
	 { "XDMA_SLV_READ_URGENT_LIMIT", 4, 7, &umr_bitfield_default },
	 { "XDMA_SLV_READ_URGENT_LEVEL", 8, 11, &umr_bitfield_default },
	 { "XDMA_SLV_READ_STALL_DELAY", 12, 15, &umr_bitfield_default },
	 { "XDMA_SLV_READ_URGENT_TIMER", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmXDMA_SLV_WRITE_URGENT_CNTL[] = {
	 { "XDMA_SLV_WRITE_STALL", 0, 0, &umr_bitfield_default },
	 { "XDMA_SLV_WRITE_URGENT_LEVEL", 8, 11, &umr_bitfield_default },
	 { "XDMA_SLV_WRITE_STALL_DELAY", 12, 15, &umr_bitfield_default },
};
static struct umr_bitfield mmXDMA_SLV_WB_RATE_CNTL[] = {
	 { "XDMA_SLV_WB_BURST_SIZE", 0, 8, &umr_bitfield_default },
	 { "XDMA_SLV_WB_BURST_PERIOD", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmXDMA_SLV_READ_LATENCY_MINMAX[] = {
	 { "XDMA_SLV_READ_LATENCY_MIN", 0, 15, &umr_bitfield_default },
	 { "XDMA_SLV_READ_LATENCY_MAX", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmXDMA_SLV_READ_LATENCY_AVE[] = {
	 { "XDMA_SLV_READ_LATENCY_ACC", 0, 19, &umr_bitfield_default },
	 { "XDMA_SLV_READ_LATENCY_COUNT", 20, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmXDMA_SLV_PCIE_NACK_STATUS[] = {
	 { "XDMA_SLV_PCIE_NACK_TAG", 0, 9, &umr_bitfield_default },
	 { "XDMA_SLV_PCIE_NACK", 12, 13, &umr_bitfield_default },
	 { "XDMA_SLV_PCIE_NACK_CLR", 16, 16, &umr_bitfield_default },
};
static struct umr_bitfield mmXDMA_SLV_MEM_NACK_STATUS[] = {
	 { "XDMA_SLV_MEM_NACK_TAG", 0, 15, &umr_bitfield_default },
	 { "XDMA_SLV_MEM_NACK", 16, 17, &umr_bitfield_default },
	 { "XDMA_SLV_MEM_NACK_CLR", 31, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmXDMA_SLV_RDRET_BUF_STATUS[] = {
	 { "XDMA_SLV_RDRET_FREE_ENTRIES", 0, 9, &umr_bitfield_default },
	 { "XDMA_SLV_RDRET_BUF_SIZE", 12, 21, &umr_bitfield_default },
};
static struct umr_bitfield mmXDMA_SLV_READ_LATENCY_TIMER[] = {
	 { "XDMA_SLV_READ_LATENCY_TIMER", 0, 15, &umr_bitfield_default },
};
static struct umr_bitfield mmXDMA_SLV_FLIP_PENDING[] = {
	 { "XDMA_SLV_FLIP_PENDING", 0, 0, &umr_bitfield_default },
};
static struct umr_bitfield mmXDMA_SLV_CHANNEL_CNTL[] = {
	 { "XDMA_SLV_CHANNEL_WEIGHT", 0, 8, &umr_bitfield_default },
	 { "XDMA_SLV_STOP_TRANSFER", 16, 16, &umr_bitfield_default },
	 { "XDMA_SLV_CHANNEL_SOFT_RESET", 17, 17, &umr_bitfield_default },
	 { "XDMA_SLV_CHANNEL_ACTIVE", 24, 24, &umr_bitfield_default },
};
static struct umr_bitfield mmXDMA_SLV_REMOTE_GPU_ADDRESS[] = {
	 { "XDMA_SLV_REMOTE_GPU_ADDRESS", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmXDMA_SLV_REMOTE_GPU_ADDRESS_HIGH[] = {
	 { "XDMA_SLV_REMOTE_GPU_ADDRESS_HIGH", 0, 7, &umr_bitfield_default },
};
static struct umr_bitfield ixEXP5[] = {
	 { "RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixEXP6[] = {
	 { "RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixEXP7[] = {
	 { "RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixLX0[] = {
	 { "RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixLX1[] = {
	 { "RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixLX2[] = {
	 { "RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixLX3[] = {
	 { "RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSRBM_PERFMON_CNTL[] = {
	 { "PERFMON_STATE", 0, 3, &umr_bitfield_default },
	 { "PERFMON_ENABLE_MODE", 8, 9, &umr_bitfield_default },
	 { "PERFMON_SAMPLE_ENABLE", 10, 10, &umr_bitfield_default },
};
static struct umr_bitfield mmSRBM_PERFCOUNTER0_SELECT[] = {
	 { "PERF_SEL", 0, 5, &umr_bitfield_default },
};
static struct umr_bitfield mmSRBM_PERFCOUNTER1_SELECT[] = {
	 { "PERF_SEL", 0, 5, &umr_bitfield_default },
};
static struct umr_bitfield mmSRBM_PERFCOUNTER0_LO[] = {
	 { "PERF_COUNT0_LO", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSRBM_PERFCOUNTER0_HI[] = {
	 { "PERF_COUNT0_HI", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSRBM_PERFCOUNTER1_LO[] = {
	 { "PERF_COUNT1_LO", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSRBM_PERFCOUNTER1_HI[] = {
	 { "PERF_COUNT1_HI", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixKHFS1[] = {
	 { "RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmHDP_HOST_PATH_CNTL[] = {
	 { "BIF_RDRET_CREDIT", 0, 2, &umr_bitfield_default },
	 { "MC_WRREQ_CREDIT", 3, 8, &umr_bitfield_default },
	 { "WR_STALL_TIMER", 9, 10, &umr_bitfield_default },
	 { "RD_STALL_TIMER", 11, 12, &umr_bitfield_default },
	 { "WRITE_COMBINE_TIMER", 19, 20, &umr_bitfield_default },
	 { "WRITE_COMBINE_EN", 21, 21, &umr_bitfield_default },
	 { "CACHE_INVALIDATE", 22, 22, &umr_bitfield_default },
	 { "CLOCK_GATING_DIS", 23, 23, &umr_bitfield_default },
	 { "REG_CLK_ENABLE_COUNT", 24, 27, &umr_bitfield_default },
	 { "ALL_SURFACES_DIS", 29, 29, &umr_bitfield_default },
	 { "WRITE_THROUGH_CACHE_DIS", 30, 30, &umr_bitfield_default },
	 { "LIN_RD_CACHE_DIS", 31, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmHDP_NONSURFACE_BASE[] = {
	 { "NONSURF_BASE", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmHDP_NONSURFACE_INFO[] = {
	 { "NONSURF_ADDR_TYPE", 0, 0, &umr_bitfield_default },
	 { "NONSURF_ARRAY_MODE", 1, 4, &umr_bitfield_default },
	 { "NONSURF_ENDIAN", 5, 6, &umr_bitfield_default },
	 { "NONSURF_PIXEL_SIZE", 7, 9, &umr_bitfield_default },
	 { "NONSURF_SAMPLE_NUM", 10, 12, &umr_bitfield_default },
	 { "NONSURF_SAMPLE_SIZE", 13, 14, &umr_bitfield_default },
	 { "NONSURF_PRIV", 15, 15, &umr_bitfield_default },
	 { "NONSURF_TILE_COMPACT", 16, 16, &umr_bitfield_default },
	 { "NONSURF_TILE_SPLIT", 17, 19, &umr_bitfield_default },
	 { "NONSURF_NUM_BANKS", 20, 21, &umr_bitfield_default },
	 { "NONSURF_BANK_WIDTH", 22, 23, &umr_bitfield_default },
	 { "NONSURF_BANK_HEIGHT", 24, 25, &umr_bitfield_default },
	 { "NONSURF_MACRO_TILE_ASPECT", 26, 27, &umr_bitfield_default },
	 { "NONSURF_MICRO_TILE_MODE", 28, 30, &umr_bitfield_default },
	 { "NONSURF_SLICE_TILE_MAX_MSB", 31, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmHDP_NONSURFACE_SIZE[] = {
	 { "NONSURF_PITCH_TILE_MAX", 0, 10, &umr_bitfield_default },
	 { "NONSURF_SLICE_TILE_MAX", 11, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmHDP_NONSURF_FLAGS[] = {
	 { "NONSURF_WRITE_FLAG", 0, 0, &umr_bitfield_default },
	 { "NONSURF_READ_FLAG", 1, 1, &umr_bitfield_default },
};
static struct umr_bitfield mmHDP_NONSURF_FLAGS_CLR[] = {
	 { "NONSURF_WRITE_FLAG_CLR", 0, 0, &umr_bitfield_default },
	 { "NONSURF_READ_FLAG_CLR", 1, 1, &umr_bitfield_default },
};
static struct umr_bitfield mmHDP_SW_SEMAPHORE[] = {
	 { "SW_SEMAPHORE", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmHDP_DEBUG0[] = {
};
static struct umr_bitfield mmHDP_DEBUG1[] = {
};
static struct umr_bitfield mmHDP_LAST_SURFACE_HIT[] = {
	 { "LAST_SURFACE_HIT", 0, 5, &umr_bitfield_default },
};
static struct umr_bitfield mmHDP_TILING_CONFIG[] = {
	 { "PIPE_TILING", 1, 3, &umr_bitfield_default },
	 { "BANK_TILING", 4, 5, &umr_bitfield_default },
	 { "GROUP_SIZE", 6, 7, &umr_bitfield_default },
	 { "ROW_TILING", 8, 10, &umr_bitfield_default },
	 { "BANK_SWAPS", 11, 13, &umr_bitfield_default },
	 { "SAMPLE_SPLIT", 14, 15, &umr_bitfield_default },
};
static struct umr_bitfield mmHDP_SC_MULTI_CHIP_CNTL[] = {
	 { "LOG2_NUM_CHIPS", 0, 2, &umr_bitfield_default },
	 { "MULTI_CHIP_TILE_SIZE", 3, 4, &umr_bitfield_default },
};
static struct umr_bitfield mmHDP_OUTSTANDING_REQ[] = {
	 { "WRITE_REQ", 0, 7, &umr_bitfield_default },
	 { "READ_REQ", 8, 15, &umr_bitfield_default },
};
static struct umr_bitfield mmHDP_ADDR_CONFIG[] = {
	 { "NUM_PIPES", 0, 2, &umr_bitfield_default },
	 { "PIPE_INTERLEAVE_SIZE", 4, 6, &umr_bitfield_default },
	 { "BANK_INTERLEAVE_SIZE", 8, 10, &umr_bitfield_default },
	 { "NUM_SHADER_ENGINES", 12, 13, &umr_bitfield_default },
	 { "SHADER_ENGINE_TILE_SIZE", 16, 18, &umr_bitfield_default },
	 { "NUM_GPUS", 20, 22, &umr_bitfield_default },
	 { "MULTI_GPU_TILE_SIZE", 24, 25, &umr_bitfield_default },
	 { "ROW_SIZE", 28, 29, &umr_bitfield_default },
	 { "NUM_LOWER_PIPES", 30, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmHDP_MISC_CNTL[] = {
	 { "FLUSH_INVALIDATE_CACHE", 0, 0, &umr_bitfield_default },
	 { "VM_ID", 1, 4, &umr_bitfield_default },
	 { "OUTSTANDING_WRITE_COUNT_1024", 5, 5, &umr_bitfield_default },
	 { "MULTIPLE_READS", 6, 6, &umr_bitfield_default },
	 { "HDP_BIF_RDRET_CREDIT", 7, 10, &umr_bitfield_default },
	 { "SIMULTANEOUS_READS_WRITES", 11, 11, &umr_bitfield_default },
	 { "NO_SPLIT_ARRAY_LINEAR", 12, 12, &umr_bitfield_default },
	 { "MC_RDREQ_CREDIT", 13, 18, &umr_bitfield_default },
	 { "READ_CACHE_INVALIDATE", 19, 19, &umr_bitfield_default },
	 { "ADDRLIB_LINEAR_BYPASS", 20, 20, &umr_bitfield_default },
	 { "FED_ENABLE", 21, 21, &umr_bitfield_default },
};
static struct umr_bitfield mmHDP_MEM_POWER_LS[] = {
	 { "LS_ENABLE", 0, 0, &umr_bitfield_default },
	 { "LS_SETUP", 1, 6, &umr_bitfield_default },
	 { "LS_HOLD", 7, 12, &umr_bitfield_default },
};
static struct umr_bitfield mmHDP_NONSURFACE_PREFETCH[] = {
	 { "NONSURF_PREFETCH_PRI", 0, 2, &umr_bitfield_default },
	 { "NONSURF_PREFETCH_DIR", 3, 5, &umr_bitfield_default },
	 { "NONSURF_PREFETCH_NUM", 6, 8, &umr_bitfield_default },
	 { "NONSURF_PREFETCH_MAX_Z", 9, 19, &umr_bitfield_default },
	 { "NONSURF_PIPE_CONFIG", 27, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmHDP_MEMIO_CNTL[] = {
	 { "MEMIO_SEND", 0, 0, &umr_bitfield_default },
	 { "MEMIO_OP", 1, 1, &umr_bitfield_default },
	 { "MEMIO_BE", 2, 5, &umr_bitfield_default },
	 { "MEMIO_WR_STROBE", 6, 6, &umr_bitfield_default },
	 { "MEMIO_RD_STROBE", 7, 7, &umr_bitfield_default },
	 { "MEMIO_ADDR_UPPER", 8, 13, &umr_bitfield_default },
	 { "MEMIO_CLR_WR_ERROR", 14, 14, &umr_bitfield_default },
	 { "MEMIO_CLR_RD_ERROR", 15, 15, &umr_bitfield_default },
};
static struct umr_bitfield mmHDP_MEMIO_ADDR[] = {
	 { "MEMIO_ADDR_LOWER", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmHDP_MEMIO_STATUS[] = {
	 { "MEMIO_WR_STATUS", 0, 0, &umr_bitfield_default },
	 { "MEMIO_RD_STATUS", 1, 1, &umr_bitfield_default },
	 { "MEMIO_WR_ERROR", 2, 2, &umr_bitfield_default },
	 { "MEMIO_RD_ERROR", 3, 3, &umr_bitfield_default },
};
static struct umr_bitfield mmHDP_MEMIO_WR_DATA[] = {
	 { "MEMIO_WR_DATA", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmHDP_MEMIO_RD_DATA[] = {
	 { "MEMIO_RD_DATA", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixKHFS2[] = {
	 { "RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmHDP_XDP_DIRECT2HDP_FIRST[] = {
	 { "RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmHDP_XDP_D2H_FLUSH[] = {
	 { "D2H_FLUSH_FLUSH_NUM", 0, 3, &umr_bitfield_default },
	 { "D2H_FLUSH_MBX_ENC_DATA", 4, 7, &umr_bitfield_default },
	 { "D2H_FLUSH_MBX_ADDR_SEL", 8, 10, &umr_bitfield_default },
	 { "D2H_FLUSH_XPB_CLG", 11, 15, &umr_bitfield_default },
	 { "D2H_FLUSH_SEND_HOST", 16, 16, &umr_bitfield_default },
	 { "D2H_FLUSH_SEND_SIDE", 17, 17, &umr_bitfield_default },
	 { "D2H_FLUSH_ALTER_FLUSH_NUM", 18, 18, &umr_bitfield_default },
	 { "D2H_FLUSH_RSVD_0", 19, 19, &umr_bitfield_default },
	 { "D2H_FLUSH_RSVD_1", 20, 20, &umr_bitfield_default },
};
static struct umr_bitfield mmHDP_XDP_D2H_BAR_UPDATE[] = {
	 { "D2H_BAR_UPDATE_ADDR", 0, 15, &umr_bitfield_default },
	 { "D2H_BAR_UPDATE_FLUSH_NUM", 16, 19, &umr_bitfield_default },
	 { "D2H_BAR_UPDATE_BAR_NUM", 20, 22, &umr_bitfield_default },
};
static struct umr_bitfield mmHDP_XDP_D2H_RSVD_3[] = {
	 { "RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmHDP_XDP_D2H_RSVD_4[] = {
	 { "RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmHDP_XDP_D2H_RSVD_5[] = {
	 { "RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmHDP_XDP_D2H_RSVD_6[] = {
	 { "RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmHDP_XDP_D2H_RSVD_7[] = {
	 { "RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmHDP_XDP_D2H_RSVD_8[] = {
	 { "RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmHDP_XDP_D2H_RSVD_9[] = {
	 { "RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmHDP_XDP_D2H_RSVD_10[] = {
	 { "RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmHDP_XDP_D2H_RSVD_11[] = {
	 { "RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmHDP_XDP_D2H_RSVD_12[] = {
	 { "RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmHDP_XDP_D2H_RSVD_13[] = {
	 { "RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmHDP_XDP_D2H_RSVD_14[] = {
	 { "RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmHDP_XDP_D2H_RSVD_15[] = {
	 { "RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmHDP_XDP_D2H_RSVD_16[] = {
	 { "RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmHDP_XDP_D2H_RSVD_17[] = {
	 { "RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmHDP_XDP_D2H_RSVD_18[] = {
	 { "RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmHDP_XDP_D2H_RSVD_19[] = {
	 { "RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmHDP_XDP_D2H_RSVD_20[] = {
	 { "RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmHDP_XDP_D2H_RSVD_21[] = {
	 { "RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmHDP_XDP_D2H_RSVD_22[] = {
	 { "RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmHDP_XDP_D2H_RSVD_23[] = {
	 { "RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmHDP_XDP_D2H_RSVD_24[] = {
	 { "RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmHDP_XDP_D2H_RSVD_25[] = {
	 { "RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmHDP_XDP_D2H_RSVD_26[] = {
	 { "RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmHDP_XDP_D2H_RSVD_27[] = {
	 { "RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmHDP_XDP_D2H_RSVD_28[] = {
	 { "RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmHDP_XDP_D2H_RSVD_29[] = {
	 { "RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmHDP_XDP_D2H_RSVD_30[] = {
	 { "RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmHDP_XDP_D2H_RSVD_31[] = {
	 { "RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmHDP_XDP_D2H_RSVD_32[] = {
	 { "RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmHDP_XDP_D2H_RSVD_33[] = {
	 { "RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmHDP_XDP_D2H_RSVD_34[] = {
	 { "RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmHDP_XDP_DIRECT2HDP_LAST[] = {
	 { "RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmHDP_XDP_P2P_BAR_CFG[] = {
	 { "P2P_BAR_CFG_ADDR_SIZE", 0, 3, &umr_bitfield_default },
	 { "P2P_BAR_CFG_BAR_FROM", 4, 5, &umr_bitfield_default },
};
static struct umr_bitfield mmHDP_XDP_P2P_MBX_OFFSET[] = {
	 { "P2P_MBX_OFFSET", 0, 13, &umr_bitfield_default },
};
static struct umr_bitfield mmHDP_XDP_P2P_MBX_ADDR0[] = {
	 { "VALID", 0, 0, &umr_bitfield_default },
	 { "ADDR", 1, 20, &umr_bitfield_default },
	 { "ADDR_39_36", 21, 24, &umr_bitfield_default },
};
static struct umr_bitfield mmHDP_XDP_P2P_MBX_ADDR1[] = {
	 { "VALID", 0, 0, &umr_bitfield_default },
	 { "ADDR", 1, 20, &umr_bitfield_default },
	 { "ADDR_39_36", 21, 24, &umr_bitfield_default },
};
static struct umr_bitfield mmHDP_XDP_P2P_MBX_ADDR2[] = {
	 { "VALID", 0, 0, &umr_bitfield_default },
	 { "ADDR", 1, 20, &umr_bitfield_default },
	 { "ADDR_39_36", 21, 24, &umr_bitfield_default },
};
static struct umr_bitfield mmHDP_XDP_P2P_MBX_ADDR3[] = {
	 { "VALID", 0, 0, &umr_bitfield_default },
	 { "ADDR", 1, 20, &umr_bitfield_default },
	 { "ADDR_39_36", 21, 24, &umr_bitfield_default },
};
static struct umr_bitfield mmHDP_XDP_P2P_MBX_ADDR4[] = {
	 { "VALID", 0, 0, &umr_bitfield_default },
	 { "ADDR", 1, 20, &umr_bitfield_default },
	 { "ADDR_39_36", 21, 24, &umr_bitfield_default },
};
static struct umr_bitfield mmHDP_XDP_P2P_MBX_ADDR5[] = {
	 { "VALID", 0, 0, &umr_bitfield_default },
	 { "ADDR", 1, 20, &umr_bitfield_default },
	 { "ADDR_39_36", 21, 24, &umr_bitfield_default },
};
static struct umr_bitfield mmHDP_XDP_P2P_MBX_ADDR6[] = {
	 { "VALID", 0, 0, &umr_bitfield_default },
	 { "ADDR", 1, 20, &umr_bitfield_default },
	 { "ADDR_39_36", 21, 24, &umr_bitfield_default },
};
static struct umr_bitfield mmHDP_XDP_HDP_MBX_MC_CFG[] = {
	 { "HDP_MBX_MC_CFG_TAP_WRREQ_PRIV", 0, 0, &umr_bitfield_default },
	 { "HDP_MBX_MC_CFG_TAP_WRREQ_SWAP", 1, 2, &umr_bitfield_default },
	 { "HDP_MBX_MC_CFG_TAP_WRREQ_TRAN", 3, 3, &umr_bitfield_default },
	 { "HDP_MBX_MC_CFG_TAP_WRREQ_VMID", 4, 7, &umr_bitfield_default },
};
static struct umr_bitfield mmHDP_XDP_HDP_MC_CFG[] = {
	 { "HDP_MC_CFG_HST_TAP_WRREQ_PRIV", 0, 0, &umr_bitfield_default },
	 { "HDP_MC_CFG_HST_TAP_WRREQ_SWAP", 1, 2, &umr_bitfield_default },
	 { "HDP_MC_CFG_HST_TAP_WRREQ_TRAN", 3, 3, &umr_bitfield_default },
	 { "HDP_MC_CFG_SID_TAP_WRREQ_PRIV", 4, 4, &umr_bitfield_default },
	 { "HDP_MC_CFG_SID_TAP_WRREQ_SWAP", 5, 6, &umr_bitfield_default },
	 { "HDP_MC_CFG_SID_TAP_WRREQ_TRAN", 7, 7, &umr_bitfield_default },
	 { "HDP_MC_CFG_XL8R_WRREQ_CRD_OVERRIDE", 8, 13, &umr_bitfield_default },
	 { "HDP_MC_CFG_XDP_HIGHER_PRI_THRESH", 14, 19, &umr_bitfield_default },
	 { "HDP_MC_CFG_MC_STALL_ON_BUF_FULL_MASK", 20, 22, &umr_bitfield_default },
	 { "HDP_MC_CFG_HST_TAP_WRREQ_VMID", 23, 26, &umr_bitfield_default },
	 { "HDP_MC_CFG_SID_TAP_WRREQ_VMID", 27, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmHDP_XDP_HST_CFG[] = {
	 { "HST_CFG_WR_COMBINE_EN", 0, 0, &umr_bitfield_default },
	 { "HST_CFG_WR_COMBINE_TIMER", 1, 2, &umr_bitfield_default },
};
static struct umr_bitfield mmHDP_XDP_SID_CFG[] = {
	 { "SID_CFG_WR_COMBINE_EN", 0, 0, &umr_bitfield_default },
	 { "SID_CFG_WR_COMBINE_TIMER", 1, 2, &umr_bitfield_default },
	 { "SID_CFG_FLNUM_MSB_SEL", 3, 4, &umr_bitfield_default },
};
static struct umr_bitfield mmHDP_XDP_HDP_IPH_CFG[] = {
	 { "HDP_IPH_CFG_SYS_FIFO_DEPTH_OVERRIDE", 0, 5, &umr_bitfield_default },
	 { "HDP_IPH_CFG_XDP_FIFO_DEPTH_OVERRIDE", 6, 11, &umr_bitfield_default },
	 { "HDP_IPH_CFG_INVERSE_PEER_TAG_MATCHING", 12, 12, &umr_bitfield_default },
	 { "HDP_IPH_CFG_P2P_RD_EN", 13, 13, &umr_bitfield_default },
};
static struct umr_bitfield mmHDP_XDP_SRBM_CFG[] = {
	 { "SRBM_CFG_REG_CLK_ENABLE_COUNT", 0, 5, &umr_bitfield_default },
	 { "SRBM_CFG_REG_CLK_GATING_DIS", 6, 6, &umr_bitfield_default },
	 { "SRBM_CFG_WAKE_DYN_CLK", 7, 7, &umr_bitfield_default },
};
static struct umr_bitfield mmHDP_XDP_CGTT_BLK_CTRL[] = {
	 { "CGTT_BLK_CTRL_0_ON_DELAY", 0, 3, &umr_bitfield_default },
	 { "CGTT_BLK_CTRL_1_OFF_DELAY", 4, 11, &umr_bitfield_default },
	 { "CGTT_BLK_CTRL_2_RSVD", 12, 29, &umr_bitfield_default },
	 { "CGTT_BLK_CTRL_3_SOFT_CORE_OVERRIDE", 30, 30, &umr_bitfield_default },
	 { "CGTT_BLK_CTRL_4_SOFT_REG_OVERRIDE", 31, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmHDP_XDP_P2P_BAR0[] = {
	 { "ADDR", 0, 15, &umr_bitfield_default },
	 { "FLUSH", 16, 19, &umr_bitfield_default },
	 { "VALID", 20, 20, &umr_bitfield_default },
};
static struct umr_bitfield mmHDP_XDP_P2P_BAR1[] = {
	 { "ADDR", 0, 15, &umr_bitfield_default },
	 { "FLUSH", 16, 19, &umr_bitfield_default },
	 { "VALID", 20, 20, &umr_bitfield_default },
};
static struct umr_bitfield mmHDP_XDP_P2P_BAR2[] = {
	 { "ADDR", 0, 15, &umr_bitfield_default },
	 { "FLUSH", 16, 19, &umr_bitfield_default },
	 { "VALID", 20, 20, &umr_bitfield_default },
};
static struct umr_bitfield mmHDP_XDP_P2P_BAR3[] = {
	 { "ADDR", 0, 15, &umr_bitfield_default },
	 { "FLUSH", 16, 19, &umr_bitfield_default },
	 { "VALID", 20, 20, &umr_bitfield_default },
};
static struct umr_bitfield mmHDP_XDP_P2P_BAR4[] = {
	 { "ADDR", 0, 15, &umr_bitfield_default },
	 { "FLUSH", 16, 19, &umr_bitfield_default },
	 { "VALID", 20, 20, &umr_bitfield_default },
};
static struct umr_bitfield mmHDP_XDP_P2P_BAR5[] = {
	 { "ADDR", 0, 15, &umr_bitfield_default },
	 { "FLUSH", 16, 19, &umr_bitfield_default },
	 { "VALID", 20, 20, &umr_bitfield_default },
};
static struct umr_bitfield mmHDP_XDP_P2P_BAR6[] = {
	 { "ADDR", 0, 15, &umr_bitfield_default },
	 { "FLUSH", 16, 19, &umr_bitfield_default },
	 { "VALID", 20, 20, &umr_bitfield_default },
};
static struct umr_bitfield mmHDP_XDP_P2P_BAR7[] = {
	 { "ADDR", 0, 15, &umr_bitfield_default },
	 { "FLUSH", 16, 19, &umr_bitfield_default },
	 { "VALID", 20, 20, &umr_bitfield_default },
};
static struct umr_bitfield mmHDP_XDP_FLUSH_ARMED_STS[] = {
	 { "FLUSH_ARMED_STS", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmHDP_XDP_FLUSH_CNTR0_STS[] = {
	 { "FLUSH_CNTR0_STS", 0, 25, &umr_bitfield_default },
};
static struct umr_bitfield mmHDP_XDP_BUSY_STS[] = {
	 { "BUSY_BITS", 0, 17, &umr_bitfield_default },
};
static struct umr_bitfield mmHDP_XDP_STICKY[] = {
	 { "STICKY_STS", 0, 15, &umr_bitfield_default },
	 { "STICKY_W1C", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmHDP_XDP_CHKN[] = {
	 { "CHKN_0_RSVD", 0, 7, &umr_bitfield_default },
	 { "CHKN_1_RSVD", 8, 15, &umr_bitfield_default },
	 { "CHKN_2_RSVD", 16, 23, &umr_bitfield_default },
	 { "CHKN_3_RSVD", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmHDP_XDP_DBG_ADDR[] = {
	 { "STS", 0, 15, &umr_bitfield_default },
	 { "CTRL", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmHDP_XDP_DBG_DATA[] = {
	 { "STS", 0, 15, &umr_bitfield_default },
	 { "CTRL", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmHDP_XDP_DBG_MASK[] = {
	 { "STS", 0, 15, &umr_bitfield_default },
	 { "CTRL", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmHDP_XDP_BARS_ADDR_39_36[] = {
	 { "BAR0_ADDR_39_36", 0, 3, &umr_bitfield_default },
	 { "BAR1_ADDR_39_36", 4, 7, &umr_bitfield_default },
	 { "BAR2_ADDR_39_36", 8, 11, &umr_bitfield_default },
	 { "BAR3_ADDR_39_36", 12, 15, &umr_bitfield_default },
	 { "BAR4_ADDR_39_36", 16, 19, &umr_bitfield_default },
	 { "BAR5_ADDR_39_36", 20, 23, &umr_bitfield_default },
	 { "BAR6_ADDR_39_36", 24, 27, &umr_bitfield_default },
	 { "BAR7_ADDR_39_36", 28, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmIH_VMID_0_LUT[] = {
	 { "PASID", 0, 15, &umr_bitfield_default },
};
static struct umr_bitfield mmIH_VMID_1_LUT[] = {
	 { "PASID", 0, 15, &umr_bitfield_default },
};
static struct umr_bitfield mmIH_VMID_2_LUT[] = {
	 { "PASID", 0, 15, &umr_bitfield_default },
};
static struct umr_bitfield mmIH_VMID_3_LUT[] = {
	 { "PASID", 0, 15, &umr_bitfield_default },
};
static struct umr_bitfield mmIH_VMID_4_LUT[] = {
	 { "PASID", 0, 15, &umr_bitfield_default },
};
static struct umr_bitfield mmIH_VMID_5_LUT[] = {
	 { "PASID", 0, 15, &umr_bitfield_default },
};
static struct umr_bitfield mmIH_VMID_6_LUT[] = {
	 { "PASID", 0, 15, &umr_bitfield_default },
};
static struct umr_bitfield mmIH_VMID_7_LUT[] = {
	 { "PASID", 0, 15, &umr_bitfield_default },
};
static struct umr_bitfield mmIH_VMID_8_LUT[] = {
	 { "PASID", 0, 15, &umr_bitfield_default },
};
static struct umr_bitfield mmIH_VMID_9_LUT[] = {
	 { "PASID", 0, 15, &umr_bitfield_default },
};
static struct umr_bitfield mmIH_VMID_10_LUT[] = {
	 { "PASID", 0, 15, &umr_bitfield_default },
};
static struct umr_bitfield mmIH_VMID_11_LUT[] = {
	 { "PASID", 0, 15, &umr_bitfield_default },
};
static struct umr_bitfield mmIH_VMID_12_LUT[] = {
	 { "PASID", 0, 15, &umr_bitfield_default },
};
static struct umr_bitfield mmIH_VMID_13_LUT[] = {
	 { "PASID", 0, 15, &umr_bitfield_default },
};
static struct umr_bitfield mmIH_VMID_14_LUT[] = {
	 { "PASID", 0, 15, &umr_bitfield_default },
};
static struct umr_bitfield mmIH_VMID_15_LUT[] = {
	 { "PASID", 0, 15, &umr_bitfield_default },
};
static struct umr_bitfield mmIH_RB_CNTL[] = {
	 { "RB_ENABLE", 0, 0, &umr_bitfield_default },
	 { "RB_SIZE", 1, 5, &umr_bitfield_default },
	 { "RB_FULL_DRAIN_ENABLE", 6, 6, &umr_bitfield_default },
	 { "RB_GPU_TS_ENABLE", 7, 7, &umr_bitfield_default },
	 { "WPTR_WRITEBACK_ENABLE", 8, 8, &umr_bitfield_default },
	 { "WPTR_WRITEBACK_TIMER", 9, 13, &umr_bitfield_default },
	 { "WPTR_OVERFLOW_ENABLE", 16, 16, &umr_bitfield_default },
	 { "WPTR_OVERFLOW_CLEAR", 31, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmIH_RB_BASE[] = {
	 { "ADDR", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmIH_RB_RPTR[] = {
	 { "OFFSET", 2, 17, &umr_bitfield_default },
};
static struct umr_bitfield mmIH_RB_WPTR[] = {
	 { "RB_OVERFLOW", 0, 0, &umr_bitfield_default },
	 { "OFFSET", 2, 17, &umr_bitfield_default },
};
static struct umr_bitfield mmIH_RB_WPTR_ADDR_HI[] = {
	 { "ADDR", 0, 7, &umr_bitfield_default },
};
static struct umr_bitfield mmIH_RB_WPTR_ADDR_LO[] = {
	 { "ADDR", 2, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmIH_CNTL[] = {
	 { "ENABLE_INTR", 0, 0, &umr_bitfield_default },
	 { "MC_SWAP", 1, 2, &umr_bitfield_default },
	 { "MC_TRAN", 3, 3, &umr_bitfield_default },
	 { "RPTR_REARM", 4, 4, &umr_bitfield_default },
	 { "CLIENT_FIFO_HIGHWATER", 8, 9, &umr_bitfield_default },
	 { "MC_FIFO_HIGHWATER", 10, 14, &umr_bitfield_default },
	 { "MC_WRREQ_CREDIT", 15, 19, &umr_bitfield_default },
	 { "MC_WR_CLEAN_CNT", 20, 24, &umr_bitfield_default },
	 { "MC_VMID", 25, 28, &umr_bitfield_default },
};
static struct umr_bitfield mmIH_LEVEL_STATUS[] = {
	 { "DC_STATUS", 0, 0, &umr_bitfield_default },
	 { "ROM_STATUS", 2, 2, &umr_bitfield_default },
	 { "SRBM_STATUS", 3, 3, &umr_bitfield_default },
	 { "BIF_STATUS", 4, 4, &umr_bitfield_default },
	 { "XDMA_STATUS", 5, 5, &umr_bitfield_default },
};
static struct umr_bitfield mmIH_STATUS[] = {
	 { "IDLE", 0, 0, &umr_bitfield_default },
	 { "INPUT_IDLE", 1, 1, &umr_bitfield_default },
	 { "RB_IDLE", 2, 2, &umr_bitfield_default },
	 { "RB_FULL", 3, 3, &umr_bitfield_default },
	 { "RB_FULL_DRAIN", 4, 4, &umr_bitfield_default },
	 { "RB_OVERFLOW", 5, 5, &umr_bitfield_default },
	 { "MC_WR_IDLE", 6, 6, &umr_bitfield_default },
	 { "MC_WR_STALL", 7, 7, &umr_bitfield_default },
	 { "MC_WR_CLEAN_PENDING", 8, 8, &umr_bitfield_default },
	 { "MC_WR_CLEAN_STALL", 9, 9, &umr_bitfield_default },
	 { "BIF_INTERRUPT_LINE", 10, 10, &umr_bitfield_default },
};
static struct umr_bitfield mmIH_PERFMON_CNTL[] = {
	 { "ENABLE0", 0, 0, &umr_bitfield_default },
	 { "CLEAR0", 1, 1, &umr_bitfield_default },
	 { "PERF_SEL0", 2, 7, &umr_bitfield_default },
	 { "ENABLE1", 8, 8, &umr_bitfield_default },
	 { "CLEAR1", 9, 9, &umr_bitfield_default },
	 { "PERF_SEL1", 10, 15, &umr_bitfield_default },
};
static struct umr_bitfield mmIH_PERFCOUNTER0_RESULT[] = {
	 { "PERF_COUNT", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmIH_PERFCOUNTER1_RESULT[] = {
	 { "PERF_COUNT", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmIH_ADVFAULT_CNTL[] = {
	 { "WATERMARK", 0, 2, &umr_bitfield_default },
	 { "WATERMARK_ENABLE", 3, 3, &umr_bitfield_default },
	 { "WATERMARK_REACHED", 4, 4, &umr_bitfield_default },
	 { "NUM_FAULTS_DROPPED", 8, 15, &umr_bitfield_default },
	 { "WAIT_TIMER", 16, 29, &umr_bitfield_default },
};
static struct umr_bitfield mmSEM_MCIF_CONFIG[] = {
	 { "MC_REQ_SWAP", 0, 1, &umr_bitfield_default },
	 { "MC_WRREQ_CREDIT", 2, 7, &umr_bitfield_default },
	 { "MC_RDREQ_CREDIT", 8, 13, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA_CONFIG[] = {
	 { "SDMA_RDREQ_URG", 8, 11, &umr_bitfield_default },
	 { "SDMA_REQ_TRAN", 16, 16, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA1_CONFIG[] = {
	 { "SDMA_RDREQ_URG", 8, 11, &umr_bitfield_default },
	 { "SDMA_REQ_TRAN", 16, 16, &umr_bitfield_default },
};
static struct umr_bitfield mmUVD_CONFIG[] = {
	 { "UVD_RDREQ_URG", 8, 11, &umr_bitfield_default },
	 { "UVD_REQ_TRAN", 16, 16, &umr_bitfield_default },
};
static struct umr_bitfield mmVCE_CONFIG[] = {
	 { "VCE_RDREQ_URG", 8, 11, &umr_bitfield_default },
	 { "VCE_REQ_TRAN", 16, 16, &umr_bitfield_default },
};
static struct umr_bitfield mmACP_CONFIG[] = {
	 { "ACP_RDREQ_URG", 8, 11, &umr_bitfield_default },
	 { "ACP_REQ_TRAN", 16, 16, &umr_bitfield_default },
};
static struct umr_bitfield mmCPG_CONFIG[] = {
	 { "CPG_RDREQ_URG", 8, 11, &umr_bitfield_default },
	 { "CPG_REQ_TRAN", 16, 16, &umr_bitfield_default },
};
static struct umr_bitfield mmCPC1_CONFIG[] = {
	 { "CPC1_RDREQ_URG", 8, 11, &umr_bitfield_default },
	 { "CPC1_REQ_TRAN", 16, 16, &umr_bitfield_default },
};
static struct umr_bitfield mmCPC2_CONFIG[] = {
	 { "CPC2_RDREQ_URG", 8, 11, &umr_bitfield_default },
	 { "CPC2_REQ_TRAN", 16, 16, &umr_bitfield_default },
};
static struct umr_bitfield mmSEM_STATUS[] = {
	 { "SEM_IDLE", 0, 0, &umr_bitfield_default },
	 { "SEM_INTERNAL_IDLE", 1, 1, &umr_bitfield_default },
	 { "MC_RDREQ_FIFO_FULL", 2, 2, &umr_bitfield_default },
	 { "MC_WRREQ_FIFO_FULL", 3, 3, &umr_bitfield_default },
	 { "WRITE1_FIFO_FULL", 4, 4, &umr_bitfield_default },
	 { "CHECK0_FIFO_FULL", 5, 5, &umr_bitfield_default },
	 { "MC_RDREQ_PENDING", 6, 6, &umr_bitfield_default },
	 { "MC_WRREQ_PENDING", 7, 7, &umr_bitfield_default },
	 { "SDMA0_MAILBOX_PENDING", 8, 8, &umr_bitfield_default },
	 { "SDMA1_MAILBOX_PENDING", 9, 9, &umr_bitfield_default },
	 { "UVD_MAILBOX_PENDING", 10, 10, &umr_bitfield_default },
	 { "VCE_MAILBOX_PENDING", 11, 11, &umr_bitfield_default },
	 { "CPG1_MAILBOX_PENDING", 12, 12, &umr_bitfield_default },
	 { "CPG2_MAILBOX_PENDING", 13, 13, &umr_bitfield_default },
};
static struct umr_bitfield mmSEM_EDC_CONFIG[] = {
	 { "DIS_EDC", 1, 1, &umr_bitfield_default },
};
static struct umr_bitfield mmSEM_MAILBOX_CLIENTCONFIG[] = {
	 { "CP_CLIENT0", 0, 2, &umr_bitfield_default },
	 { "CP_CLIENT1", 3, 5, &umr_bitfield_default },
	 { "CP_CLIENT2", 6, 8, &umr_bitfield_default },
	 { "CP_CLIENT3", 9, 11, &umr_bitfield_default },
	 { "SDMA_CLIENT0", 12, 14, &umr_bitfield_default },
	 { "UVD_CLIENT0", 15, 17, &umr_bitfield_default },
	 { "SDMA1_CLIENT0", 18, 20, &umr_bitfield_default },
	 { "VCE_CLIENT0", 21, 23, &umr_bitfield_default },
};
static struct umr_bitfield mmSEM_MAILBOX[] = {
	 { "SIDEPORT", 0, 7, &umr_bitfield_default },
	 { "HOSTPORT", 8, 15, &umr_bitfield_default },
};
static struct umr_bitfield mmSEM_MAILBOX_CONTROL[] = {
	 { "SIDEPORT_ENABLE", 0, 7, &umr_bitfield_default },
	 { "HOSTPORT_ENABLE", 8, 15, &umr_bitfield_default },
};
static struct umr_bitfield mmSEM_CHICKEN_BITS[] = {
	 { "VMID_PIPELINE_EN", 0, 0, &umr_bitfield_default },
	 { "ENTRY_PIPELINE_EN", 1, 1, &umr_bitfield_default },
};