{ "ixDH_TEST", REG_SMC, 0x0, &ixDH_TEST[0], sizeof(ixDH_TEST)/sizeof(ixDH_TEST[0]), 0, 0 },
	{ "ixKHFS3", REG_SMC, 0x10, &ixKHFS3[0], sizeof(ixKHFS3)/sizeof(ixKHFS3[0]), 0, 0 },
	{ "ixKSESSION0", REG_SMC, 0x14, &ixKSESSION0[0], sizeof(ixKSESSION0)/sizeof(ixKSESSION0[0]), 0, 0 },
	{ "mmCC_DRM_ID_STRAPS", REG_MMIO, 0x1559, &mmCC_DRM_ID_STRAPS[0], sizeof(mmCC_DRM_ID_STRAPS)/sizeof(mmCC_DRM_ID_STRAPS[0]), 0, 0 },
	{ "mmCGTT_DRM_CLK_CTRL0", REG_MMIO, 0x1579, NULL, 0, 0, 0 },
	{ "mmDC_TEST_DEBUG_INDEX", REG_MMIO, 0x157c, &mmDC_TEST_DEBUG_INDEX[0], sizeof(mmDC_TEST_DEBUG_INDEX)/sizeof(mmDC_TEST_DEBUG_INDEX[0]), 0, 0 },
	{ "mmDC_TEST_DEBUG_DATA", REG_MMIO, 0x157d, &mmDC_TEST_DEBUG_DATA[0], sizeof(mmDC_TEST_DEBUG_DATA)/sizeof(mmDC_TEST_DEBUG_DATA[0]), 0, 0 },
	{ "ixKSESSION1", REG_SMC, 0x18, &ixKSESSION1[0], sizeof(ixKSESSION1)/sizeof(ixKSESSION1[0]), 0, 0 },
	{ "ixCLIENT2_K0", REG_SMC, 0x1b4, &ixCLIENT2_K0[0], sizeof(ixCLIENT2_K0)/sizeof(ixCLIENT2_K0[0]), 0, 0 },
	{ "ixCLIENT2_K1", REG_SMC, 0x1b8, &ixCLIENT2_K1[0], sizeof(ixCLIENT2_K1)/sizeof(ixCLIENT2_K1[0]), 0, 0 },
	{ "ixCLIENT2_K2", REG_SMC, 0x1bc, &ixCLIENT2_K2[0], sizeof(ixCLIENT2_K2)/sizeof(ixCLIENT2_K2[0]), 0, 0 },
	{ "ixKSESSION2", REG_SMC, 0x1c, &ixKSESSION2[0], sizeof(ixKSESSION2)/sizeof(ixKSESSION2[0]), 0, 0 },
	{ "ixCLIENT2_K3", REG_SMC, 0x1c0, &ixCLIENT2_K3[0], sizeof(ixCLIENT2_K3)/sizeof(ixCLIENT2_K3[0]), 0, 0 },
	{ "ixCLIENT2_CK0", REG_SMC, 0x1c4, &ixCLIENT2_CK0[0], sizeof(ixCLIENT2_CK0)/sizeof(ixCLIENT2_CK0[0]), 0, 0 },
	{ "ixCLIENT2_CK1", REG_SMC, 0x1c8, &ixCLIENT2_CK1[0], sizeof(ixCLIENT2_CK1)/sizeof(ixCLIENT2_CK1[0]), 0, 0 },
	{ "ixCLIENT2_CK2", REG_SMC, 0x1cc, &ixCLIENT2_CK2[0], sizeof(ixCLIENT2_CK2)/sizeof(ixCLIENT2_CK2[0]), 0, 0 },
	{ "ixCLIENT2_CK3", REG_SMC, 0x1d0, &ixCLIENT2_CK3[0], sizeof(ixCLIENT2_CK3)/sizeof(ixCLIENT2_CK3[0]), 0, 0 },
	{ "ixCLIENT2_CD0", REG_SMC, 0x1d4, &ixCLIENT2_CD0[0], sizeof(ixCLIENT2_CD0)/sizeof(ixCLIENT2_CD0[0]), 0, 0 },
	{ "ixCLIENT2_CD1", REG_SMC, 0x1d8, &ixCLIENT2_CD1[0], sizeof(ixCLIENT2_CD1)/sizeof(ixCLIENT2_CD1[0]), 0, 0 },
	{ "ixCLIENT2_CD2", REG_SMC, 0x1dc, &ixCLIENT2_CD2[0], sizeof(ixCLIENT2_CD2)/sizeof(ixCLIENT2_CD2[0]), 0, 0 },
	{ "ixCLIENT2_CD3", REG_SMC, 0x1e0, &ixCLIENT2_CD3[0], sizeof(ixCLIENT2_CD3)/sizeof(ixCLIENT2_CD3[0]), 0, 0 },
	{ "ixCLIENT2_BM", REG_SMC, 0x1e4, &ixCLIENT2_BM[0], sizeof(ixCLIENT2_BM)/sizeof(ixCLIENT2_BM[0]), 0, 0 },
	{ "ixCLIENT2_OFFSET", REG_SMC, 0x1e8, &ixCLIENT2_OFFSET[0], sizeof(ixCLIENT2_OFFSET)/sizeof(ixCLIENT2_OFFSET[0]), 0, 0 },
	{ "ixCLIENT2_STATUS", REG_SMC, 0x1ec, &ixCLIENT2_STATUS[0], sizeof(ixCLIENT2_STATUS)/sizeof(ixCLIENT2_STATUS[0]), 0, 0 },
	{ "ixCLIENT0_K0", REG_SMC, 0x1f0, &ixCLIENT0_K0[0], sizeof(ixCLIENT0_K0)/sizeof(ixCLIENT0_K0[0]), 0, 0 },
	{ "ixCLIENT0_K1", REG_SMC, 0x1f4, &ixCLIENT0_K1[0], sizeof(ixCLIENT0_K1)/sizeof(ixCLIENT0_K1[0]), 0, 0 },
	{ "ixCLIENT0_K2", REG_SMC, 0x1f8, &ixCLIENT0_K2[0], sizeof(ixCLIENT0_K2)/sizeof(ixCLIENT0_K2[0]), 0, 0 },
	{ "ixCLIENT0_K3", REG_SMC, 0x1fc, &ixCLIENT0_K3[0], sizeof(ixCLIENT0_K3)/sizeof(ixCLIENT0_K3[0]), 0, 0 },
	{ "ixKSESSION3", REG_SMC, 0x20, &ixKSESSION3[0], sizeof(ixKSESSION3)/sizeof(ixKSESSION3[0]), 0, 0 },
	{ "ixCLIENT0_CK0", REG_SMC, 0x200, &ixCLIENT0_CK0[0], sizeof(ixCLIENT0_CK0)/sizeof(ixCLIENT0_CK0[0]), 0, 0 },
	{ "ixCLIENT0_CK1", REG_SMC, 0x204, &ixCLIENT0_CK1[0], sizeof(ixCLIENT0_CK1)/sizeof(ixCLIENT0_CK1[0]), 0, 0 },
	{ "ixCLIENT0_CK2", REG_SMC, 0x208, &ixCLIENT0_CK2[0], sizeof(ixCLIENT0_CK2)/sizeof(ixCLIENT0_CK2[0]), 0, 0 },
	{ "ixCLIENT0_CK3", REG_SMC, 0x20c, &ixCLIENT0_CK3[0], sizeof(ixCLIENT0_CK3)/sizeof(ixCLIENT0_CK3[0]), 0, 0 },
	{ "ixCLIENT0_CD0", REG_SMC, 0x210, &ixCLIENT0_CD0[0], sizeof(ixCLIENT0_CD0)/sizeof(ixCLIENT0_CD0[0]), 0, 0 },
	{ "ixCLIENT0_CD1", REG_SMC, 0x214, &ixCLIENT0_CD1[0], sizeof(ixCLIENT0_CD1)/sizeof(ixCLIENT0_CD1[0]), 0, 0 },
	{ "ixCLIENT0_CD2", REG_SMC, 0x218, &ixCLIENT0_CD2[0], sizeof(ixCLIENT0_CD2)/sizeof(ixCLIENT0_CD2[0]), 0, 0 },
	{ "ixCLIENT0_CD3", REG_SMC, 0x21c, &ixCLIENT0_CD3[0], sizeof(ixCLIENT0_CD3)/sizeof(ixCLIENT0_CD3[0]), 0, 0 },
	{ "ixCLIENT0_BM", REG_SMC, 0x220, &ixCLIENT0_BM[0], sizeof(ixCLIENT0_BM)/sizeof(ixCLIENT0_BM[0]), 0, 0 },
	{ "ixCLIENT0_OFFSET", REG_SMC, 0x224, &ixCLIENT0_OFFSET[0], sizeof(ixCLIENT0_OFFSET)/sizeof(ixCLIENT0_OFFSET[0]), 0, 0 },
	{ "ixCLIENT0_STATUS", REG_SMC, 0x228, &ixCLIENT0_STATUS[0], sizeof(ixCLIENT0_STATUS)/sizeof(ixCLIENT0_STATUS[0]), 0, 0 },
	{ "ixCLIENT1_K0", REG_SMC, 0x22c, &ixCLIENT1_K0[0], sizeof(ixCLIENT1_K0)/sizeof(ixCLIENT1_K0[0]), 0, 0 },
	{ "ixCLIENT1_K1", REG_SMC, 0x230, &ixCLIENT1_K1[0], sizeof(ixCLIENT1_K1)/sizeof(ixCLIENT1_K1[0]), 0, 0 },
	{ "ixCLIENT1_K2", REG_SMC, 0x234, &ixCLIENT1_K2[0], sizeof(ixCLIENT1_K2)/sizeof(ixCLIENT1_K2[0]), 0, 0 },
	{ "ixCLIENT1_K3", REG_SMC, 0x238, &ixCLIENT1_K3[0], sizeof(ixCLIENT1_K3)/sizeof(ixCLIENT1_K3[0]), 0, 0 },
	{ "ixCLIENT1_CK0", REG_SMC, 0x23c, &ixCLIENT1_CK0[0], sizeof(ixCLIENT1_CK0)/sizeof(ixCLIENT1_CK0[0]), 0, 0 },
	{ "ixKSIG0", REG_SMC, 0x24, &ixKSIG0[0], sizeof(ixKSIG0)/sizeof(ixKSIG0[0]), 0, 0 },
	{ "ixCLIENT1_CK1", REG_SMC, 0x240, &ixCLIENT1_CK1[0], sizeof(ixCLIENT1_CK1)/sizeof(ixCLIENT1_CK1[0]), 0, 0 },
	{ "ixCLIENT1_CK2", REG_SMC, 0x244, &ixCLIENT1_CK2[0], sizeof(ixCLIENT1_CK2)/sizeof(ixCLIENT1_CK2[0]), 0, 0 },
	{ "ixCLIENT1_CK3", REG_SMC, 0x248, &ixCLIENT1_CK3[0], sizeof(ixCLIENT1_CK3)/sizeof(ixCLIENT1_CK3[0]), 0, 0 },
	{ "ixCLIENT1_CD0", REG_SMC, 0x24c, &ixCLIENT1_CD0[0], sizeof(ixCLIENT1_CD0)/sizeof(ixCLIENT1_CD0[0]), 0, 0 },
	{ "ixCLIENT1_CD1", REG_SMC, 0x250, &ixCLIENT1_CD1[0], sizeof(ixCLIENT1_CD1)/sizeof(ixCLIENT1_CD1[0]), 0, 0 },
	{ "ixCLIENT1_CD2", REG_SMC, 0x254, &ixCLIENT1_CD2[0], sizeof(ixCLIENT1_CD2)/sizeof(ixCLIENT1_CD2[0]), 0, 0 },
	{ "ixCLIENT1_CD3", REG_SMC, 0x258, &ixCLIENT1_CD3[0], sizeof(ixCLIENT1_CD3)/sizeof(ixCLIENT1_CD3[0]), 0, 0 },
	{ "ixCLIENT1_BM", REG_SMC, 0x25c, &ixCLIENT1_BM[0], sizeof(ixCLIENT1_BM)/sizeof(ixCLIENT1_BM[0]), 0, 0 },
	{ "ixCLIENT1_OFFSET", REG_SMC, 0x260, &ixCLIENT1_OFFSET[0], sizeof(ixCLIENT1_OFFSET)/sizeof(ixCLIENT1_OFFSET[0]), 0, 0 },
	{ "ixCLIENT1_PORT_STATUS", REG_SMC, 0x264, &ixCLIENT1_PORT_STATUS[0], sizeof(ixCLIENT1_PORT_STATUS)/sizeof(ixCLIENT1_PORT_STATUS[0]), 0, 0 },
	{ "ixKEFUSE0", REG_SMC, 0x268, &ixKEFUSE0[0], sizeof(ixKEFUSE0)/sizeof(ixKEFUSE0[0]), 0, 0 },
	{ "ixKEFUSE1", REG_SMC, 0x26c, &ixKEFUSE1[0], sizeof(ixKEFUSE1)/sizeof(ixKEFUSE1[0]), 0, 0 },
	{ "ixKEFUSE2", REG_SMC, 0x270, &ixKEFUSE2[0], sizeof(ixKEFUSE2)/sizeof(ixKEFUSE2[0]), 0, 0 },
	{ "ixKEFUSE3", REG_SMC, 0x274, &ixKEFUSE3[0], sizeof(ixKEFUSE3)/sizeof(ixKEFUSE3[0]), 0, 0 },
	{ "ixHFS_SEED0", REG_SMC, 0x278, &ixHFS_SEED0[0], sizeof(ixHFS_SEED0)/sizeof(ixHFS_SEED0[0]), 0, 0 },
	{ "ixHFS_SEED1", REG_SMC, 0x27c, &ixHFS_SEED1[0], sizeof(ixHFS_SEED1)/sizeof(ixHFS_SEED1[0]), 0, 0 },
	{ "ixKSIG1", REG_SMC, 0x28, &ixKSIG1[0], sizeof(ixKSIG1)/sizeof(ixKSIG1[0]), 0, 0 },
	{ "ixHFS_SEED2", REG_SMC, 0x280, &ixHFS_SEED2[0], sizeof(ixHFS_SEED2)/sizeof(ixHFS_SEED2[0]), 0, 0 },
	{ "ixHFS_SEED3", REG_SMC, 0x284, &ixHFS_SEED3[0], sizeof(ixHFS_SEED3)/sizeof(ixHFS_SEED3[0]), 0, 0 },
	{ "ixRINGOSC_MASK", REG_SMC, 0x288, &ixRINGOSC_MASK[0], sizeof(ixRINGOSC_MASK)/sizeof(ixRINGOSC_MASK[0]), 0, 0 },
	{ "ixCLIENT0_OFFSET_HI", REG_SMC, 0x290, &ixCLIENT0_OFFSET_HI[0], sizeof(ixCLIENT0_OFFSET_HI)/sizeof(ixCLIENT0_OFFSET_HI[0]), 0, 0 },
	{ "ixCLIENT1_OFFSET_HI", REG_SMC, 0x294, &ixCLIENT1_OFFSET_HI[0], sizeof(ixCLIENT1_OFFSET_HI)/sizeof(ixCLIENT1_OFFSET_HI[0]), 0, 0 },
	{ "ixCLIENT2_OFFSET_HI", REG_SMC, 0x298, &ixCLIENT2_OFFSET_HI[0], sizeof(ixCLIENT2_OFFSET_HI)/sizeof(ixCLIENT2_OFFSET_HI[0]), 0, 0 },
	{ "ixSPU_PORT_STATUS", REG_SMC, 0x29c, &ixSPU_PORT_STATUS[0], sizeof(ixSPU_PORT_STATUS)/sizeof(ixSPU_PORT_STATUS[0]), 0, 0 },
	{ "ixCLIENT3_OFFSET_HI", REG_SMC, 0x2a0, &ixCLIENT3_OFFSET_HI[0], sizeof(ixCLIENT3_OFFSET_HI)/sizeof(ixCLIENT3_OFFSET_HI[0]), 0, 0 },
	{ "ixCLIENT3_K0", REG_SMC, 0x2a4, &ixCLIENT3_K0[0], sizeof(ixCLIENT3_K0)/sizeof(ixCLIENT3_K0[0]), 0, 0 },
	{ "ixCLIENT3_K1", REG_SMC, 0x2a8, &ixCLIENT3_K1[0], sizeof(ixCLIENT3_K1)/sizeof(ixCLIENT3_K1[0]), 0, 0 },
	{ "ixCLIENT3_K2", REG_SMC, 0x2ac, &ixCLIENT3_K2[0], sizeof(ixCLIENT3_K2)/sizeof(ixCLIENT3_K2[0]), 0, 0 },
	{ "ixCLIENT3_K3", REG_SMC, 0x2b0, &ixCLIENT3_K3[0], sizeof(ixCLIENT3_K3)/sizeof(ixCLIENT3_K3[0]), 0, 0 },
	{ "ixCLIENT3_CK0", REG_SMC, 0x2b4, &ixCLIENT3_CK0[0], sizeof(ixCLIENT3_CK0)/sizeof(ixCLIENT3_CK0[0]), 0, 0 },
	{ "ixCLIENT3_CK1", REG_SMC, 0x2b8, &ixCLIENT3_CK1[0], sizeof(ixCLIENT3_CK1)/sizeof(ixCLIENT3_CK1[0]), 0, 0 },
	{ "ixCLIENT3_CK2", REG_SMC, 0x2bc, &ixCLIENT3_CK2[0], sizeof(ixCLIENT3_CK2)/sizeof(ixCLIENT3_CK2[0]), 0, 0 },
	{ "ixKSIG2", REG_SMC, 0x2c, &ixKSIG2[0], sizeof(ixKSIG2)/sizeof(ixKSIG2[0]), 0, 0 },
	{ "ixCLIENT3_CK3", REG_SMC, 0x2c0, &ixCLIENT3_CK3[0], sizeof(ixCLIENT3_CK3)/sizeof(ixCLIENT3_CK3[0]), 0, 0 },
	{ "ixCLIENT3_CD0", REG_SMC, 0x2c4, &ixCLIENT3_CD0[0], sizeof(ixCLIENT3_CD0)/sizeof(ixCLIENT3_CD0[0]), 0, 0 },
	{ "ixCLIENT3_CD1", REG_SMC, 0x2c8, &ixCLIENT3_CD1[0], sizeof(ixCLIENT3_CD1)/sizeof(ixCLIENT3_CD1[0]), 0, 0 },
	{ "ixCLIENT3_CD2", REG_SMC, 0x2cc, &ixCLIENT3_CD2[0], sizeof(ixCLIENT3_CD2)/sizeof(ixCLIENT3_CD2[0]), 0, 0 },
	{ "ixCLIENT3_CD3", REG_SMC, 0x2d0, &ixCLIENT3_CD3[0], sizeof(ixCLIENT3_CD3)/sizeof(ixCLIENT3_CD3[0]), 0, 0 },
	{ "ixCLIENT3_BM", REG_SMC, 0x2d4, &ixCLIENT3_BM[0], sizeof(ixCLIENT3_BM)/sizeof(ixCLIENT3_BM[0]), 0, 0 },
	{ "ixCLIENT3_OFFSET", REG_SMC, 0x2d8, &ixCLIENT3_OFFSET[0], sizeof(ixCLIENT3_OFFSET)/sizeof(ixCLIENT3_OFFSET[0]), 0, 0 },
	{ "ixCLIENT3_STATUS", REG_SMC, 0x2dc, &ixCLIENT3_STATUS[0], sizeof(ixCLIENT3_STATUS)/sizeof(ixCLIENT3_STATUS[0]), 0, 0 },
	{ "ixKSIG3", REG_SMC, 0x30, &ixKSIG3[0], sizeof(ixKSIG3)/sizeof(ixKSIG3[0]), 0, 0 },
	{ "ixEXP0", REG_SMC, 0x34, &ixEXP0[0], sizeof(ixEXP0)/sizeof(ixEXP0[0]), 0, 0 },
	{ "mmSDMA0_UCODE_ADDR", REG_MMIO, 0x3400, &mmSDMA0_UCODE_ADDR[0], sizeof(mmSDMA0_UCODE_ADDR)/sizeof(mmSDMA0_UCODE_ADDR[0]), 0, 0 },
	{ "mmSDMA0_UCODE_DATA", REG_MMIO, 0x3401, &mmSDMA0_UCODE_DATA[0], sizeof(mmSDMA0_UCODE_DATA)/sizeof(mmSDMA0_UCODE_DATA[0]), 0, 0 },
	{ "mmSDMA0_POWER_CNTL", REG_MMIO, 0x3402, &mmSDMA0_POWER_CNTL[0], sizeof(mmSDMA0_POWER_CNTL)/sizeof(mmSDMA0_POWER_CNTL[0]), 0, 0 },
	{ "mmSDMA0_CLK_CTRL", REG_MMIO, 0x3403, &mmSDMA0_CLK_CTRL[0], sizeof(mmSDMA0_CLK_CTRL)/sizeof(mmSDMA0_CLK_CTRL[0]), 0, 0 },
	{ "mmSDMA0_CNTL", REG_MMIO, 0x3404, &mmSDMA0_CNTL[0], sizeof(mmSDMA0_CNTL)/sizeof(mmSDMA0_CNTL[0]), 0, 0 },
	{ "mmSDMA0_CHICKEN_BITS", REG_MMIO, 0x3405, &mmSDMA0_CHICKEN_BITS[0], sizeof(mmSDMA0_CHICKEN_BITS)/sizeof(mmSDMA0_CHICKEN_BITS[0]), 0, 0 },
	{ "mmSDMA0_TILING_CONFIG", REG_MMIO, 0x3406, &mmSDMA0_TILING_CONFIG[0], sizeof(mmSDMA0_TILING_CONFIG)/sizeof(mmSDMA0_TILING_CONFIG[0]), 0, 0 },
	{ "mmSDMA0_HASH", REG_MMIO, 0x3407, &mmSDMA0_HASH[0], sizeof(mmSDMA0_HASH)/sizeof(mmSDMA0_HASH[0]), 0, 0 },
	{ "mmSDMA0_SEM_INCOMPLETE_TIMER_CNTL", REG_MMIO, 0x3408, &mmSDMA0_SEM_INCOMPLETE_TIMER_CNTL[0], sizeof(mmSDMA0_SEM_INCOMPLETE_TIMER_CNTL)/sizeof(mmSDMA0_SEM_INCOMPLETE_TIMER_CNTL[0]), 0, 0 },
	{ "mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL", REG_MMIO, 0x3409, &mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL[0], sizeof(mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL)/sizeof(mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL[0]), 0, 0 },
	{ "mmSDMA0_RB_RPTR_FETCH", REG_MMIO, 0x340a, &mmSDMA0_RB_RPTR_FETCH[0], sizeof(mmSDMA0_RB_RPTR_FETCH)/sizeof(mmSDMA0_RB_RPTR_FETCH[0]), 0, 0 },
	{ "mmSDMA0_IB_OFFSET_FETCH", REG_MMIO, 0x340b, &mmSDMA0_IB_OFFSET_FETCH[0], sizeof(mmSDMA0_IB_OFFSET_FETCH)/sizeof(mmSDMA0_IB_OFFSET_FETCH[0]), 0, 0 },
	{ "mmSDMA0_PROGRAM", REG_MMIO, 0x340c, &mmSDMA0_PROGRAM[0], sizeof(mmSDMA0_PROGRAM)/sizeof(mmSDMA0_PROGRAM[0]), 0, 0 },
	{ "mmSDMA0_STATUS_REG", REG_MMIO, 0x340d, &mmSDMA0_STATUS_REG[0], sizeof(mmSDMA0_STATUS_REG)/sizeof(mmSDMA0_STATUS_REG[0]), 0, 0 },
	{ "mmSDMA0_STATUS1_REG", REG_MMIO, 0x340e, &mmSDMA0_STATUS1_REG[0], sizeof(mmSDMA0_STATUS1_REG)/sizeof(mmSDMA0_STATUS1_REG[0]), 0, 0 },
	{ "mmSDMA0_PERFMON_CNTL", REG_MMIO, 0x340f, &mmSDMA0_PERFMON_CNTL[0], sizeof(mmSDMA0_PERFMON_CNTL)/sizeof(mmSDMA0_PERFMON_CNTL[0]), 0, 0 },
	{ "mmSDMA0_PERFCOUNTER0_RESULT", REG_MMIO, 0x3410, &mmSDMA0_PERFCOUNTER0_RESULT[0], sizeof(mmSDMA0_PERFCOUNTER0_RESULT)/sizeof(mmSDMA0_PERFCOUNTER0_RESULT[0]), 0, 0 },
	{ "mmSDMA0_PERFCOUNTER1_RESULT", REG_MMIO, 0x3411, &mmSDMA0_PERFCOUNTER1_RESULT[0], sizeof(mmSDMA0_PERFCOUNTER1_RESULT)/sizeof(mmSDMA0_PERFCOUNTER1_RESULT[0]), 0, 0 },
	{ "mmSDMA0_F32_CNTL", REG_MMIO, 0x3412, &mmSDMA0_F32_CNTL[0], sizeof(mmSDMA0_F32_CNTL)/sizeof(mmSDMA0_F32_CNTL[0]), 0, 0 },
	{ "mmSDMA0_FREEZE", REG_MMIO, 0x3413, &mmSDMA0_FREEZE[0], sizeof(mmSDMA0_FREEZE)/sizeof(mmSDMA0_FREEZE[0]), 0, 0 },
	{ "mmSDMA0_PHASE0_QUANTUM", REG_MMIO, 0x3414, &mmSDMA0_PHASE0_QUANTUM[0], sizeof(mmSDMA0_PHASE0_QUANTUM)/sizeof(mmSDMA0_PHASE0_QUANTUM[0]), 0, 0 },
	{ "mmSDMA0_PHASE1_QUANTUM", REG_MMIO, 0x3415, &mmSDMA0_PHASE1_QUANTUM[0], sizeof(mmSDMA0_PHASE1_QUANTUM)/sizeof(mmSDMA0_PHASE1_QUANTUM[0]), 0, 0 },
	{ "mmSDMA_POWER_GATING", REG_MMIO, 0x3416, &mmSDMA_POWER_GATING[0], sizeof(mmSDMA_POWER_GATING)/sizeof(mmSDMA_POWER_GATING[0]), 0, 0 },
	{ "mmSDMA_PGFSM_CONFIG", REG_MMIO, 0x3417, &mmSDMA_PGFSM_CONFIG[0], sizeof(mmSDMA_PGFSM_CONFIG)/sizeof(mmSDMA_PGFSM_CONFIG[0]), 0, 0 },
	{ "mmSDMA_PGFSM_WRITE", REG_MMIO, 0x3418, &mmSDMA_PGFSM_WRITE[0], sizeof(mmSDMA_PGFSM_WRITE)/sizeof(mmSDMA_PGFSM_WRITE[0]), 0, 0 },
	{ "mmSDMA_PGFSM_READ", REG_MMIO, 0x3419, &mmSDMA_PGFSM_READ[0], sizeof(mmSDMA_PGFSM_READ)/sizeof(mmSDMA_PGFSM_READ[0]), 0, 0 },
	{ "mmSDMA0_EDC_CONFIG", REG_MMIO, 0x341a, &mmSDMA0_EDC_CONFIG[0], sizeof(mmSDMA0_EDC_CONFIG)/sizeof(mmSDMA0_EDC_CONFIG[0]), 0, 0 },
	{ "mmSDMA0_GFX_RB_CNTL", REG_MMIO, 0x3480, &mmSDMA0_GFX_RB_CNTL[0], sizeof(mmSDMA0_GFX_RB_CNTL)/sizeof(mmSDMA0_GFX_RB_CNTL[0]), 0, 0 },
	{ "mmSDMA0_GFX_RB_BASE", REG_MMIO, 0x3481, &mmSDMA0_GFX_RB_BASE[0], sizeof(mmSDMA0_GFX_RB_BASE)/sizeof(mmSDMA0_GFX_RB_BASE[0]), 0, 0 },
	{ "mmSDMA0_GFX_RB_BASE_HI", REG_MMIO, 0x3482, &mmSDMA0_GFX_RB_BASE_HI[0], sizeof(mmSDMA0_GFX_RB_BASE_HI)/sizeof(mmSDMA0_GFX_RB_BASE_HI[0]), 0, 0 },
	{ "mmSDMA0_GFX_RB_RPTR", REG_MMIO, 0x3483, &mmSDMA0_GFX_RB_RPTR[0], sizeof(mmSDMA0_GFX_RB_RPTR)/sizeof(mmSDMA0_GFX_RB_RPTR[0]), 0, 0 },
	{ "mmSDMA0_GFX_RB_WPTR", REG_MMIO, 0x3484, &mmSDMA0_GFX_RB_WPTR[0], sizeof(mmSDMA0_GFX_RB_WPTR)/sizeof(mmSDMA0_GFX_RB_WPTR[0]), 0, 0 },
	{ "mmSDMA0_GFX_RB_WPTR_POLL_CNTL", REG_MMIO, 0x3485, &mmSDMA0_GFX_RB_WPTR_POLL_CNTL[0], sizeof(mmSDMA0_GFX_RB_WPTR_POLL_CNTL)/sizeof(mmSDMA0_GFX_RB_WPTR_POLL_CNTL[0]), 0, 0 },
	{ "mmSDMA0_GFX_RB_WPTR_POLL_ADDR_HI", REG_MMIO, 0x3486, &mmSDMA0_GFX_RB_WPTR_POLL_ADDR_HI[0], sizeof(mmSDMA0_GFX_RB_WPTR_POLL_ADDR_HI)/sizeof(mmSDMA0_GFX_RB_WPTR_POLL_ADDR_HI[0]), 0, 0 },
	{ "mmSDMA0_GFX_RB_WPTR_POLL_ADDR_LO", REG_MMIO, 0x3487, &mmSDMA0_GFX_RB_WPTR_POLL_ADDR_LO[0], sizeof(mmSDMA0_GFX_RB_WPTR_POLL_ADDR_LO)/sizeof(mmSDMA0_GFX_RB_WPTR_POLL_ADDR_LO[0]), 0, 0 },
	{ "mmSDMA0_GFX_RB_RPTR_ADDR_HI", REG_MMIO, 0x3488, &mmSDMA0_GFX_RB_RPTR_ADDR_HI[0], sizeof(mmSDMA0_GFX_RB_RPTR_ADDR_HI)/sizeof(mmSDMA0_GFX_RB_RPTR_ADDR_HI[0]), 0, 0 },
	{ "mmSDMA0_GFX_RB_RPTR_ADDR_LO", REG_MMIO, 0x3489, &mmSDMA0_GFX_RB_RPTR_ADDR_LO[0], sizeof(mmSDMA0_GFX_RB_RPTR_ADDR_LO)/sizeof(mmSDMA0_GFX_RB_RPTR_ADDR_LO[0]), 0, 0 },
	{ "mmSDMA0_GFX_IB_CNTL", REG_MMIO, 0x348a, &mmSDMA0_GFX_IB_CNTL[0], sizeof(mmSDMA0_GFX_IB_CNTL)/sizeof(mmSDMA0_GFX_IB_CNTL[0]), 0, 0 },
	{ "mmSDMA0_GFX_IB_RPTR", REG_MMIO, 0x348b, &mmSDMA0_GFX_IB_RPTR[0], sizeof(mmSDMA0_GFX_IB_RPTR)/sizeof(mmSDMA0_GFX_IB_RPTR[0]), 0, 0 },
	{ "mmSDMA0_GFX_IB_OFFSET", REG_MMIO, 0x348c, &mmSDMA0_GFX_IB_OFFSET[0], sizeof(mmSDMA0_GFX_IB_OFFSET)/sizeof(mmSDMA0_GFX_IB_OFFSET[0]), 0, 0 },
	{ "mmSDMA0_GFX_IB_BASE_LO", REG_MMIO, 0x348d, &mmSDMA0_GFX_IB_BASE_LO[0], sizeof(mmSDMA0_GFX_IB_BASE_LO)/sizeof(mmSDMA0_GFX_IB_BASE_LO[0]), 0, 0 },
	{ "mmSDMA0_GFX_IB_BASE_HI", REG_MMIO, 0x348e, &mmSDMA0_GFX_IB_BASE_HI[0], sizeof(mmSDMA0_GFX_IB_BASE_HI)/sizeof(mmSDMA0_GFX_IB_BASE_HI[0]), 0, 0 },
	{ "mmSDMA0_GFX_IB_SIZE", REG_MMIO, 0x348f, &mmSDMA0_GFX_IB_SIZE[0], sizeof(mmSDMA0_GFX_IB_SIZE)/sizeof(mmSDMA0_GFX_IB_SIZE[0]), 0, 0 },
	{ "mmSDMA0_GFX_SKIP_CNTL", REG_MMIO, 0x3490, &mmSDMA0_GFX_SKIP_CNTL[0], sizeof(mmSDMA0_GFX_SKIP_CNTL)/sizeof(mmSDMA0_GFX_SKIP_CNTL[0]), 0, 0 },
	{ "mmSDMA0_GFX_CONTEXT_STATUS", REG_MMIO, 0x3491, &mmSDMA0_GFX_CONTEXT_STATUS[0], sizeof(mmSDMA0_GFX_CONTEXT_STATUS)/sizeof(mmSDMA0_GFX_CONTEXT_STATUS[0]), 0, 0 },
	{ "mmSDMA0_GFX_CONTEXT_CNTL", REG_MMIO, 0x3493, &mmSDMA0_GFX_CONTEXT_CNTL[0], sizeof(mmSDMA0_GFX_CONTEXT_CNTL)/sizeof(mmSDMA0_GFX_CONTEXT_CNTL[0]), 0, 0 },
	{ "mmSDMA0_GFX_VIRTUAL_ADDR", REG_MMIO, 0x34a7, &mmSDMA0_GFX_VIRTUAL_ADDR[0], sizeof(mmSDMA0_GFX_VIRTUAL_ADDR)/sizeof(mmSDMA0_GFX_VIRTUAL_ADDR[0]), 0, 0 },
	{ "mmSDMA0_GFX_APE1_CNTL", REG_MMIO, 0x34a8, &mmSDMA0_GFX_APE1_CNTL[0], sizeof(mmSDMA0_GFX_APE1_CNTL)/sizeof(mmSDMA0_GFX_APE1_CNTL[0]), 0, 0 },
	{ "mmSDMA0_GFX_WATERMARK", REG_MMIO, 0x34aa, &mmSDMA0_GFX_WATERMARK[0], sizeof(mmSDMA0_GFX_WATERMARK)/sizeof(mmSDMA0_GFX_WATERMARK[0]), 0, 0 },
	{ "mmSDMA0_RLC0_RB_CNTL", REG_MMIO, 0x3500, &mmSDMA0_RLC0_RB_CNTL[0], sizeof(mmSDMA0_RLC0_RB_CNTL)/sizeof(mmSDMA0_RLC0_RB_CNTL[0]), 0, 0 },
	{ "mmSDMA0_RLC0_RB_BASE", REG_MMIO, 0x3501, &mmSDMA0_RLC0_RB_BASE[0], sizeof(mmSDMA0_RLC0_RB_BASE)/sizeof(mmSDMA0_RLC0_RB_BASE[0]), 0, 0 },
	{ "mmSDMA0_RLC0_RB_BASE_HI", REG_MMIO, 0x3502, &mmSDMA0_RLC0_RB_BASE_HI[0], sizeof(mmSDMA0_RLC0_RB_BASE_HI)/sizeof(mmSDMA0_RLC0_RB_BASE_HI[0]), 0, 0 },
	{ "mmSDMA0_RLC0_RB_RPTR", REG_MMIO, 0x3503, &mmSDMA0_RLC0_RB_RPTR[0], sizeof(mmSDMA0_RLC0_RB_RPTR)/sizeof(mmSDMA0_RLC0_RB_RPTR[0]), 0, 0 },
	{ "mmSDMA0_RLC0_RB_WPTR", REG_MMIO, 0x3504, &mmSDMA0_RLC0_RB_WPTR[0], sizeof(mmSDMA0_RLC0_RB_WPTR)/sizeof(mmSDMA0_RLC0_RB_WPTR[0]), 0, 0 },
	{ "mmSDMA0_RLC0_RB_WPTR_POLL_CNTL", REG_MMIO, 0x3505, &mmSDMA0_RLC0_RB_WPTR_POLL_CNTL[0], sizeof(mmSDMA0_RLC0_RB_WPTR_POLL_CNTL)/sizeof(mmSDMA0_RLC0_RB_WPTR_POLL_CNTL[0]), 0, 0 },
	{ "mmSDMA0_RLC0_RB_WPTR_POLL_ADDR_HI", REG_MMIO, 0x3506, &mmSDMA0_RLC0_RB_WPTR_POLL_ADDR_HI[0], sizeof(mmSDMA0_RLC0_RB_WPTR_POLL_ADDR_HI)/sizeof(mmSDMA0_RLC0_RB_WPTR_POLL_ADDR_HI[0]), 0, 0 },
	{ "mmSDMA0_RLC0_RB_WPTR_POLL_ADDR_LO", REG_MMIO, 0x3507, &mmSDMA0_RLC0_RB_WPTR_POLL_ADDR_LO[0], sizeof(mmSDMA0_RLC0_RB_WPTR_POLL_ADDR_LO)/sizeof(mmSDMA0_RLC0_RB_WPTR_POLL_ADDR_LO[0]), 0, 0 },
	{ "mmSDMA0_RLC0_RB_RPTR_ADDR_HI", REG_MMIO, 0x3508, &mmSDMA0_RLC0_RB_RPTR_ADDR_HI[0], sizeof(mmSDMA0_RLC0_RB_RPTR_ADDR_HI)/sizeof(mmSDMA0_RLC0_RB_RPTR_ADDR_HI[0]), 0, 0 },
	{ "mmSDMA0_RLC0_RB_RPTR_ADDR_LO", REG_MMIO, 0x3509, &mmSDMA0_RLC0_RB_RPTR_ADDR_LO[0], sizeof(mmSDMA0_RLC0_RB_RPTR_ADDR_LO)/sizeof(mmSDMA0_RLC0_RB_RPTR_ADDR_LO[0]), 0, 0 },
	{ "mmSDMA0_RLC0_IB_CNTL", REG_MMIO, 0x350a, &mmSDMA0_RLC0_IB_CNTL[0], sizeof(mmSDMA0_RLC0_IB_CNTL)/sizeof(mmSDMA0_RLC0_IB_CNTL[0]), 0, 0 },
	{ "mmSDMA0_RLC0_IB_RPTR", REG_MMIO, 0x350b, &mmSDMA0_RLC0_IB_RPTR[0], sizeof(mmSDMA0_RLC0_IB_RPTR)/sizeof(mmSDMA0_RLC0_IB_RPTR[0]), 0, 0 },
	{ "mmSDMA0_RLC0_IB_OFFSET", REG_MMIO, 0x350c, &mmSDMA0_RLC0_IB_OFFSET[0], sizeof(mmSDMA0_RLC0_IB_OFFSET)/sizeof(mmSDMA0_RLC0_IB_OFFSET[0]), 0, 0 },
	{ "mmSDMA0_RLC0_IB_BASE_LO", REG_MMIO, 0x350d, &mmSDMA0_RLC0_IB_BASE_LO[0], sizeof(mmSDMA0_RLC0_IB_BASE_LO)/sizeof(mmSDMA0_RLC0_IB_BASE_LO[0]), 0, 0 },
	{ "mmSDMA0_RLC0_IB_BASE_HI", REG_MMIO, 0x350e, &mmSDMA0_RLC0_IB_BASE_HI[0], sizeof(mmSDMA0_RLC0_IB_BASE_HI)/sizeof(mmSDMA0_RLC0_IB_BASE_HI[0]), 0, 0 },
	{ "mmSDMA0_RLC0_IB_SIZE", REG_MMIO, 0x350f, &mmSDMA0_RLC0_IB_SIZE[0], sizeof(mmSDMA0_RLC0_IB_SIZE)/sizeof(mmSDMA0_RLC0_IB_SIZE[0]), 0, 0 },
	{ "mmSDMA0_RLC0_SKIP_CNTL", REG_MMIO, 0x3510, &mmSDMA0_RLC0_SKIP_CNTL[0], sizeof(mmSDMA0_RLC0_SKIP_CNTL)/sizeof(mmSDMA0_RLC0_SKIP_CNTL[0]), 0, 0 },
	{ "mmSDMA0_RLC0_CONTEXT_STATUS", REG_MMIO, 0x3511, &mmSDMA0_RLC0_CONTEXT_STATUS[0], sizeof(mmSDMA0_RLC0_CONTEXT_STATUS)/sizeof(mmSDMA0_RLC0_CONTEXT_STATUS[0]), 0, 0 },
	{ "mmSDMA0_RLC0_DOORBELL", REG_MMIO, 0x3512, &mmSDMA0_RLC0_DOORBELL[0], sizeof(mmSDMA0_RLC0_DOORBELL)/sizeof(mmSDMA0_RLC0_DOORBELL[0]), 0, 0 },
	{ "mmSDMA0_RLC0_VIRTUAL_ADDR", REG_MMIO, 0x3527, &mmSDMA0_RLC0_VIRTUAL_ADDR[0], sizeof(mmSDMA0_RLC0_VIRTUAL_ADDR)/sizeof(mmSDMA0_RLC0_VIRTUAL_ADDR[0]), 0, 0 },
	{ "mmSDMA0_RLC0_APE1_CNTL", REG_MMIO, 0x3528, &mmSDMA0_RLC0_APE1_CNTL[0], sizeof(mmSDMA0_RLC0_APE1_CNTL)/sizeof(mmSDMA0_RLC0_APE1_CNTL[0]), 0, 0 },
	{ "mmSDMA0_RLC0_DOORBELL_LOG", REG_MMIO, 0x3529, &mmSDMA0_RLC0_DOORBELL_LOG[0], sizeof(mmSDMA0_RLC0_DOORBELL_LOG)/sizeof(mmSDMA0_RLC0_DOORBELL_LOG[0]), 0, 0 },
	{ "mmSDMA0_RLC0_WATERMARK", REG_MMIO, 0x352a, &mmSDMA0_RLC0_WATERMARK[0], sizeof(mmSDMA0_RLC0_WATERMARK)/sizeof(mmSDMA0_RLC0_WATERMARK[0]), 0, 0 },
	{ "mmSDMA0_RLC1_RB_CNTL", REG_MMIO, 0x3580, &mmSDMA0_RLC1_RB_CNTL[0], sizeof(mmSDMA0_RLC1_RB_CNTL)/sizeof(mmSDMA0_RLC1_RB_CNTL[0]), 0, 0 },
	{ "mmSDMA0_RLC1_RB_BASE", REG_MMIO, 0x3581, &mmSDMA0_RLC1_RB_BASE[0], sizeof(mmSDMA0_RLC1_RB_BASE)/sizeof(mmSDMA0_RLC1_RB_BASE[0]), 0, 0 },
	{ "mmSDMA0_RLC1_RB_BASE_HI", REG_MMIO, 0x3582, &mmSDMA0_RLC1_RB_BASE_HI[0], sizeof(mmSDMA0_RLC1_RB_BASE_HI)/sizeof(mmSDMA0_RLC1_RB_BASE_HI[0]), 0, 0 },
	{ "mmSDMA0_RLC1_RB_RPTR", REG_MMIO, 0x3583, &mmSDMA0_RLC1_RB_RPTR[0], sizeof(mmSDMA0_RLC1_RB_RPTR)/sizeof(mmSDMA0_RLC1_RB_RPTR[0]), 0, 0 },
	{ "mmSDMA0_RLC1_RB_WPTR", REG_MMIO, 0x3584, &mmSDMA0_RLC1_RB_WPTR[0], sizeof(mmSDMA0_RLC1_RB_WPTR)/sizeof(mmSDMA0_RLC1_RB_WPTR[0]), 0, 0 },
	{ "mmSDMA0_RLC1_RB_WPTR_POLL_CNTL", REG_MMIO, 0x3585, &mmSDMA0_RLC1_RB_WPTR_POLL_CNTL[0], sizeof(mmSDMA0_RLC1_RB_WPTR_POLL_CNTL)/sizeof(mmSDMA0_RLC1_RB_WPTR_POLL_CNTL[0]), 0, 0 },
	{ "mmSDMA0_RLC1_RB_WPTR_POLL_ADDR_HI", REG_MMIO, 0x3586, &mmSDMA0_RLC1_RB_WPTR_POLL_ADDR_HI[0], sizeof(mmSDMA0_RLC1_RB_WPTR_POLL_ADDR_HI)/sizeof(mmSDMA0_RLC1_RB_WPTR_POLL_ADDR_HI[0]), 0, 0 },
	{ "mmSDMA0_RLC1_RB_WPTR_POLL_ADDR_LO", REG_MMIO, 0x3587, &mmSDMA0_RLC1_RB_WPTR_POLL_ADDR_LO[0], sizeof(mmSDMA0_RLC1_RB_WPTR_POLL_ADDR_LO)/sizeof(mmSDMA0_RLC1_RB_WPTR_POLL_ADDR_LO[0]), 0, 0 },
	{ "mmSDMA0_RLC1_RB_RPTR_ADDR_HI", REG_MMIO, 0x3588, &mmSDMA0_RLC1_RB_RPTR_ADDR_HI[0], sizeof(mmSDMA0_RLC1_RB_RPTR_ADDR_HI)/sizeof(mmSDMA0_RLC1_RB_RPTR_ADDR_HI[0]), 0, 0 },
	{ "mmSDMA0_RLC1_RB_RPTR_ADDR_LO", REG_MMIO, 0x3589, &mmSDMA0_RLC1_RB_RPTR_ADDR_LO[0], sizeof(mmSDMA0_RLC1_RB_RPTR_ADDR_LO)/sizeof(mmSDMA0_RLC1_RB_RPTR_ADDR_LO[0]), 0, 0 },
	{ "mmSDMA0_RLC1_IB_CNTL", REG_MMIO, 0x358a, &mmSDMA0_RLC1_IB_CNTL[0], sizeof(mmSDMA0_RLC1_IB_CNTL)/sizeof(mmSDMA0_RLC1_IB_CNTL[0]), 0, 0 },
	{ "mmSDMA0_RLC1_IB_RPTR", REG_MMIO, 0x358b, &mmSDMA0_RLC1_IB_RPTR[0], sizeof(mmSDMA0_RLC1_IB_RPTR)/sizeof(mmSDMA0_RLC1_IB_RPTR[0]), 0, 0 },
	{ "mmSDMA0_RLC1_IB_OFFSET", REG_MMIO, 0x358c, &mmSDMA0_RLC1_IB_OFFSET[0], sizeof(mmSDMA0_RLC1_IB_OFFSET)/sizeof(mmSDMA0_RLC1_IB_OFFSET[0]), 0, 0 },
	{ "mmSDMA0_RLC1_IB_BASE_LO", REG_MMIO, 0x358d, &mmSDMA0_RLC1_IB_BASE_LO[0], sizeof(mmSDMA0_RLC1_IB_BASE_LO)/sizeof(mmSDMA0_RLC1_IB_BASE_LO[0]), 0, 0 },
	{ "mmSDMA0_RLC1_IB_BASE_HI", REG_MMIO, 0x358e, &mmSDMA0_RLC1_IB_BASE_HI[0], sizeof(mmSDMA0_RLC1_IB_BASE_HI)/sizeof(mmSDMA0_RLC1_IB_BASE_HI[0]), 0, 0 },
	{ "mmSDMA0_RLC1_IB_SIZE", REG_MMIO, 0x358f, &mmSDMA0_RLC1_IB_SIZE[0], sizeof(mmSDMA0_RLC1_IB_SIZE)/sizeof(mmSDMA0_RLC1_IB_SIZE[0]), 0, 0 },
	{ "mmSDMA0_RLC1_SKIP_CNTL", REG_MMIO, 0x3590, &mmSDMA0_RLC1_SKIP_CNTL[0], sizeof(mmSDMA0_RLC1_SKIP_CNTL)/sizeof(mmSDMA0_RLC1_SKIP_CNTL[0]), 0, 0 },
	{ "mmSDMA0_RLC1_CONTEXT_STATUS", REG_MMIO, 0x3591, &mmSDMA0_RLC1_CONTEXT_STATUS[0], sizeof(mmSDMA0_RLC1_CONTEXT_STATUS)/sizeof(mmSDMA0_RLC1_CONTEXT_STATUS[0]), 0, 0 },
	{ "mmSDMA0_RLC1_DOORBELL", REG_MMIO, 0x3592, &mmSDMA0_RLC1_DOORBELL[0], sizeof(mmSDMA0_RLC1_DOORBELL)/sizeof(mmSDMA0_RLC1_DOORBELL[0]), 0, 0 },
	{ "mmSDMA0_RLC1_VIRTUAL_ADDR", REG_MMIO, 0x35a7, &mmSDMA0_RLC1_VIRTUAL_ADDR[0], sizeof(mmSDMA0_RLC1_VIRTUAL_ADDR)/sizeof(mmSDMA0_RLC1_VIRTUAL_ADDR[0]), 0, 0 },
	{ "mmSDMA0_RLC1_APE1_CNTL", REG_MMIO, 0x35a8, &mmSDMA0_RLC1_APE1_CNTL[0], sizeof(mmSDMA0_RLC1_APE1_CNTL)/sizeof(mmSDMA0_RLC1_APE1_CNTL[0]), 0, 0 },
	{ "mmSDMA0_RLC1_DOORBELL_LOG", REG_MMIO, 0x35a9, &mmSDMA0_RLC1_DOORBELL_LOG[0], sizeof(mmSDMA0_RLC1_DOORBELL_LOG)/sizeof(mmSDMA0_RLC1_DOORBELL_LOG[0]), 0, 0 },
	{ "mmSDMA0_RLC1_WATERMARK", REG_MMIO, 0x35aa, &mmSDMA0_RLC1_WATERMARK[0], sizeof(mmSDMA0_RLC1_WATERMARK)/sizeof(mmSDMA0_RLC1_WATERMARK[0]), 0, 0 },
	{ "mmSDMA1_UCODE_ADDR", REG_MMIO, 0x3600, &mmSDMA1_UCODE_ADDR[0], sizeof(mmSDMA1_UCODE_ADDR)/sizeof(mmSDMA1_UCODE_ADDR[0]), 0, 0 },
	{ "mmSDMA1_UCODE_DATA", REG_MMIO, 0x3601, &mmSDMA1_UCODE_DATA[0], sizeof(mmSDMA1_UCODE_DATA)/sizeof(mmSDMA1_UCODE_DATA[0]), 0, 0 },
	{ "mmSDMA1_POWER_CNTL", REG_MMIO, 0x3602, &mmSDMA1_POWER_CNTL[0], sizeof(mmSDMA1_POWER_CNTL)/sizeof(mmSDMA1_POWER_CNTL[0]), 0, 0 },
	{ "mmSDMA1_CLK_CTRL", REG_MMIO, 0x3603, &mmSDMA1_CLK_CTRL[0], sizeof(mmSDMA1_CLK_CTRL)/sizeof(mmSDMA1_CLK_CTRL[0]), 0, 0 },
	{ "mmSDMA1_CNTL", REG_MMIO, 0x3604, &mmSDMA1_CNTL[0], sizeof(mmSDMA1_CNTL)/sizeof(mmSDMA1_CNTL[0]), 0, 0 },
	{ "mmSDMA1_CHICKEN_BITS", REG_MMIO, 0x3605, &mmSDMA1_CHICKEN_BITS[0], sizeof(mmSDMA1_CHICKEN_BITS)/sizeof(mmSDMA1_CHICKEN_BITS[0]), 0, 0 },
	{ "mmSDMA1_TILING_CONFIG", REG_MMIO, 0x3606, &mmSDMA1_TILING_CONFIG[0], sizeof(mmSDMA1_TILING_CONFIG)/sizeof(mmSDMA1_TILING_CONFIG[0]), 0, 0 },
	{ "mmSDMA1_HASH", REG_MMIO, 0x3607, &mmSDMA1_HASH[0], sizeof(mmSDMA1_HASH)/sizeof(mmSDMA1_HASH[0]), 0, 0 },
	{ "mmSDMA1_SEM_INCOMPLETE_TIMER_CNTL", REG_MMIO, 0x3608, &mmSDMA1_SEM_INCOMPLETE_TIMER_CNTL[0], sizeof(mmSDMA1_SEM_INCOMPLETE_TIMER_CNTL)/sizeof(mmSDMA1_SEM_INCOMPLETE_TIMER_CNTL[0]), 0, 0 },
	{ "mmSDMA1_SEM_WAIT_FAIL_TIMER_CNTL", REG_MMIO, 0x3609, &mmSDMA1_SEM_WAIT_FAIL_TIMER_CNTL[0], sizeof(mmSDMA1_SEM_WAIT_FAIL_TIMER_CNTL)/sizeof(mmSDMA1_SEM_WAIT_FAIL_TIMER_CNTL[0]), 0, 0 },
	{ "mmSDMA1_RB_RPTR_FETCH", REG_MMIO, 0x360a, &mmSDMA1_RB_RPTR_FETCH[0], sizeof(mmSDMA1_RB_RPTR_FETCH)/sizeof(mmSDMA1_RB_RPTR_FETCH[0]), 0, 0 },
	{ "mmSDMA1_IB_OFFSET_FETCH", REG_MMIO, 0x360b, &mmSDMA1_IB_OFFSET_FETCH[0], sizeof(mmSDMA1_IB_OFFSET_FETCH)/sizeof(mmSDMA1_IB_OFFSET_FETCH[0]), 0, 0 },
	{ "mmSDMA1_PROGRAM", REG_MMIO, 0x360c, &mmSDMA1_PROGRAM[0], sizeof(mmSDMA1_PROGRAM)/sizeof(mmSDMA1_PROGRAM[0]), 0, 0 },
	{ "mmSDMA1_STATUS_REG", REG_MMIO, 0x360d, &mmSDMA1_STATUS_REG[0], sizeof(mmSDMA1_STATUS_REG)/sizeof(mmSDMA1_STATUS_REG[0]), 0, 0 },
	{ "mmSDMA1_STATUS1_REG", REG_MMIO, 0x360e, &mmSDMA1_STATUS1_REG[0], sizeof(mmSDMA1_STATUS1_REG)/sizeof(mmSDMA1_STATUS1_REG[0]), 0, 0 },
	{ "mmSDMA1_PERFMON_CNTL", REG_MMIO, 0x360f, &mmSDMA1_PERFMON_CNTL[0], sizeof(mmSDMA1_PERFMON_CNTL)/sizeof(mmSDMA1_PERFMON_CNTL[0]), 0, 0 },
	{ "mmSDMA1_PERFCOUNTER0_RESULT", REG_MMIO, 0x3610, &mmSDMA1_PERFCOUNTER0_RESULT[0], sizeof(mmSDMA1_PERFCOUNTER0_RESULT)/sizeof(mmSDMA1_PERFCOUNTER0_RESULT[0]), 0, 0 },
	{ "mmSDMA1_PERFCOUNTER1_RESULT", REG_MMIO, 0x3611, &mmSDMA1_PERFCOUNTER1_RESULT[0], sizeof(mmSDMA1_PERFCOUNTER1_RESULT)/sizeof(mmSDMA1_PERFCOUNTER1_RESULT[0]), 0, 0 },
	{ "mmSDMA1_F32_CNTL", REG_MMIO, 0x3612, &mmSDMA1_F32_CNTL[0], sizeof(mmSDMA1_F32_CNTL)/sizeof(mmSDMA1_F32_CNTL[0]), 0, 0 },
	{ "mmSDMA1_FREEZE", REG_MMIO, 0x3613, &mmSDMA1_FREEZE[0], sizeof(mmSDMA1_FREEZE)/sizeof(mmSDMA1_FREEZE[0]), 0, 0 },
	{ "mmSDMA1_PHASE0_QUANTUM", REG_MMIO, 0x3614, &mmSDMA1_PHASE0_QUANTUM[0], sizeof(mmSDMA1_PHASE0_QUANTUM)/sizeof(mmSDMA1_PHASE0_QUANTUM[0]), 0, 0 },
	{ "mmSDMA1_PHASE1_QUANTUM", REG_MMIO, 0x3615, &mmSDMA1_PHASE1_QUANTUM[0], sizeof(mmSDMA1_PHASE1_QUANTUM)/sizeof(mmSDMA1_PHASE1_QUANTUM[0]), 0, 0 },
	{ "mmSDMA1_EDC_CONFIG", REG_MMIO, 0x361a, &mmSDMA1_EDC_CONFIG[0], sizeof(mmSDMA1_EDC_CONFIG)/sizeof(mmSDMA1_EDC_CONFIG[0]), 0, 0 },
	{ "mmSDMA1_GFX_RB_CNTL", REG_MMIO, 0x3680, &mmSDMA1_GFX_RB_CNTL[0], sizeof(mmSDMA1_GFX_RB_CNTL)/sizeof(mmSDMA1_GFX_RB_CNTL[0]), 0, 0 },
	{ "mmSDMA1_GFX_RB_BASE", REG_MMIO, 0x3681, &mmSDMA1_GFX_RB_BASE[0], sizeof(mmSDMA1_GFX_RB_BASE)/sizeof(mmSDMA1_GFX_RB_BASE[0]), 0, 0 },
	{ "mmSDMA1_GFX_RB_BASE_HI", REG_MMIO, 0x3682, &mmSDMA1_GFX_RB_BASE_HI[0], sizeof(mmSDMA1_GFX_RB_BASE_HI)/sizeof(mmSDMA1_GFX_RB_BASE_HI[0]), 0, 0 },
	{ "mmSDMA1_GFX_RB_RPTR", REG_MMIO, 0x3683, &mmSDMA1_GFX_RB_RPTR[0], sizeof(mmSDMA1_GFX_RB_RPTR)/sizeof(mmSDMA1_GFX_RB_RPTR[0]), 0, 0 },
	{ "mmSDMA1_GFX_RB_WPTR", REG_MMIO, 0x3684, &mmSDMA1_GFX_RB_WPTR[0], sizeof(mmSDMA1_GFX_RB_WPTR)/sizeof(mmSDMA1_GFX_RB_WPTR[0]), 0, 0 },
	{ "mmSDMA1_GFX_RB_WPTR_POLL_CNTL", REG_MMIO, 0x3685, &mmSDMA1_GFX_RB_WPTR_POLL_CNTL[0], sizeof(mmSDMA1_GFX_RB_WPTR_POLL_CNTL)/sizeof(mmSDMA1_GFX_RB_WPTR_POLL_CNTL[0]), 0, 0 },
	{ "mmSDMA1_GFX_RB_WPTR_POLL_ADDR_HI", REG_MMIO, 0x3686, &mmSDMA1_GFX_RB_WPTR_POLL_ADDR_HI[0], sizeof(mmSDMA1_GFX_RB_WPTR_POLL_ADDR_HI)/sizeof(mmSDMA1_GFX_RB_WPTR_POLL_ADDR_HI[0]), 0, 0 },
	{ "mmSDMA1_GFX_RB_WPTR_POLL_ADDR_LO", REG_MMIO, 0x3687, &mmSDMA1_GFX_RB_WPTR_POLL_ADDR_LO[0], sizeof(mmSDMA1_GFX_RB_WPTR_POLL_ADDR_LO)/sizeof(mmSDMA1_GFX_RB_WPTR_POLL_ADDR_LO[0]), 0, 0 },
	{ "mmSDMA1_GFX_RB_RPTR_ADDR_HI", REG_MMIO, 0x3688, &mmSDMA1_GFX_RB_RPTR_ADDR_HI[0], sizeof(mmSDMA1_GFX_RB_RPTR_ADDR_HI)/sizeof(mmSDMA1_GFX_RB_RPTR_ADDR_HI[0]), 0, 0 },
	{ "mmSDMA1_GFX_RB_RPTR_ADDR_LO", REG_MMIO, 0x3689, &mmSDMA1_GFX_RB_RPTR_ADDR_LO[0], sizeof(mmSDMA1_GFX_RB_RPTR_ADDR_LO)/sizeof(mmSDMA1_GFX_RB_RPTR_ADDR_LO[0]), 0, 0 },
	{ "mmSDMA1_GFX_IB_CNTL", REG_MMIO, 0x368a, &mmSDMA1_GFX_IB_CNTL[0], sizeof(mmSDMA1_GFX_IB_CNTL)/sizeof(mmSDMA1_GFX_IB_CNTL[0]), 0, 0 },
	{ "mmSDMA1_GFX_IB_RPTR", REG_MMIO, 0x368b, &mmSDMA1_GFX_IB_RPTR[0], sizeof(mmSDMA1_GFX_IB_RPTR)/sizeof(mmSDMA1_GFX_IB_RPTR[0]), 0, 0 },
	{ "mmSDMA1_GFX_IB_OFFSET", REG_MMIO, 0x368c, &mmSDMA1_GFX_IB_OFFSET[0], sizeof(mmSDMA1_GFX_IB_OFFSET)/sizeof(mmSDMA1_GFX_IB_OFFSET[0]), 0, 0 },
	{ "mmSDMA1_GFX_IB_BASE_LO", REG_MMIO, 0x368d, &mmSDMA1_GFX_IB_BASE_LO[0], sizeof(mmSDMA1_GFX_IB_BASE_LO)/sizeof(mmSDMA1_GFX_IB_BASE_LO[0]), 0, 0 },
	{ "mmSDMA1_GFX_IB_BASE_HI", REG_MMIO, 0x368e, &mmSDMA1_GFX_IB_BASE_HI[0], sizeof(mmSDMA1_GFX_IB_BASE_HI)/sizeof(mmSDMA1_GFX_IB_BASE_HI[0]), 0, 0 },
	{ "mmSDMA1_GFX_IB_SIZE", REG_MMIO, 0x368f, &mmSDMA1_GFX_IB_SIZE[0], sizeof(mmSDMA1_GFX_IB_SIZE)/sizeof(mmSDMA1_GFX_IB_SIZE[0]), 0, 0 },
	{ "mmSDMA1_GFX_SKIP_CNTL", REG_MMIO, 0x3690, &mmSDMA1_GFX_SKIP_CNTL[0], sizeof(mmSDMA1_GFX_SKIP_CNTL)/sizeof(mmSDMA1_GFX_SKIP_CNTL[0]), 0, 0 },
	{ "mmSDMA1_GFX_CONTEXT_STATUS", REG_MMIO, 0x3691, &mmSDMA1_GFX_CONTEXT_STATUS[0], sizeof(mmSDMA1_GFX_CONTEXT_STATUS)/sizeof(mmSDMA1_GFX_CONTEXT_STATUS[0]), 0, 0 },
	{ "mmSDMA1_GFX_CONTEXT_CNTL", REG_MMIO, 0x3693, &mmSDMA1_GFX_CONTEXT_CNTL[0], sizeof(mmSDMA1_GFX_CONTEXT_CNTL)/sizeof(mmSDMA1_GFX_CONTEXT_CNTL[0]), 0, 0 },
	{ "mmSDMA1_GFX_VIRTUAL_ADDR", REG_MMIO, 0x36a7, &mmSDMA1_GFX_VIRTUAL_ADDR[0], sizeof(mmSDMA1_GFX_VIRTUAL_ADDR)/sizeof(mmSDMA1_GFX_VIRTUAL_ADDR[0]), 0, 0 },
	{ "mmSDMA1_GFX_APE1_CNTL", REG_MMIO, 0x36a8, &mmSDMA1_GFX_APE1_CNTL[0], sizeof(mmSDMA1_GFX_APE1_CNTL)/sizeof(mmSDMA1_GFX_APE1_CNTL[0]), 0, 0 },
	{ "mmSDMA1_GFX_WATERMARK", REG_MMIO, 0x36aa, &mmSDMA1_GFX_WATERMARK[0], sizeof(mmSDMA1_GFX_WATERMARK)/sizeof(mmSDMA1_GFX_WATERMARK[0]), 0, 0 },
	{ "mmSDMA1_RLC0_RB_CNTL", REG_MMIO, 0x3700, &mmSDMA1_RLC0_RB_CNTL[0], sizeof(mmSDMA1_RLC0_RB_CNTL)/sizeof(mmSDMA1_RLC0_RB_CNTL[0]), 0, 0 },
	{ "mmSDMA1_RLC0_RB_BASE", REG_MMIO, 0x3701, &mmSDMA1_RLC0_RB_BASE[0], sizeof(mmSDMA1_RLC0_RB_BASE)/sizeof(mmSDMA1_RLC0_RB_BASE[0]), 0, 0 },
	{ "mmSDMA1_RLC0_RB_BASE_HI", REG_MMIO, 0x3702, &mmSDMA1_RLC0_RB_BASE_HI[0], sizeof(mmSDMA1_RLC0_RB_BASE_HI)/sizeof(mmSDMA1_RLC0_RB_BASE_HI[0]), 0, 0 },
	{ "mmSDMA1_RLC0_RB_RPTR", REG_MMIO, 0x3703, &mmSDMA1_RLC0_RB_RPTR[0], sizeof(mmSDMA1_RLC0_RB_RPTR)/sizeof(mmSDMA1_RLC0_RB_RPTR[0]), 0, 0 },
	{ "mmSDMA1_RLC0_RB_WPTR", REG_MMIO, 0x3704, &mmSDMA1_RLC0_RB_WPTR[0], sizeof(mmSDMA1_RLC0_RB_WPTR)/sizeof(mmSDMA1_RLC0_RB_WPTR[0]), 0, 0 },
	{ "mmSDMA1_RLC0_RB_WPTR_POLL_CNTL", REG_MMIO, 0x3705, &mmSDMA1_RLC0_RB_WPTR_POLL_CNTL[0], sizeof(mmSDMA1_RLC0_RB_WPTR_POLL_CNTL)/sizeof(mmSDMA1_RLC0_RB_WPTR_POLL_CNTL[0]), 0, 0 },
	{ "mmSDMA1_RLC0_RB_WPTR_POLL_ADDR_HI", REG_MMIO, 0x3706, &mmSDMA1_RLC0_RB_WPTR_POLL_ADDR_HI[0], sizeof(mmSDMA1_RLC0_RB_WPTR_POLL_ADDR_HI)/sizeof(mmSDMA1_RLC0_RB_WPTR_POLL_ADDR_HI[0]), 0, 0 },
	{ "mmSDMA1_RLC0_RB_WPTR_POLL_ADDR_LO", REG_MMIO, 0x3707, &mmSDMA1_RLC0_RB_WPTR_POLL_ADDR_LO[0], sizeof(mmSDMA1_RLC0_RB_WPTR_POLL_ADDR_LO)/sizeof(mmSDMA1_RLC0_RB_WPTR_POLL_ADDR_LO[0]), 0, 0 },
	{ "mmSDMA1_RLC0_RB_RPTR_ADDR_HI", REG_MMIO, 0x3708, &mmSDMA1_RLC0_RB_RPTR_ADDR_HI[0], sizeof(mmSDMA1_RLC0_RB_RPTR_ADDR_HI)/sizeof(mmSDMA1_RLC0_RB_RPTR_ADDR_HI[0]), 0, 0 },
	{ "mmSDMA1_RLC0_RB_RPTR_ADDR_LO", REG_MMIO, 0x3709, &mmSDMA1_RLC0_RB_RPTR_ADDR_LO[0], sizeof(mmSDMA1_RLC0_RB_RPTR_ADDR_LO)/sizeof(mmSDMA1_RLC0_RB_RPTR_ADDR_LO[0]), 0, 0 },
	{ "mmSDMA1_RLC0_IB_CNTL", REG_MMIO, 0x370a, &mmSDMA1_RLC0_IB_CNTL[0], sizeof(mmSDMA1_RLC0_IB_CNTL)/sizeof(mmSDMA1_RLC0_IB_CNTL[0]), 0, 0 },
	{ "mmSDMA1_RLC0_IB_RPTR", REG_MMIO, 0x370b, &mmSDMA1_RLC0_IB_RPTR[0], sizeof(mmSDMA1_RLC0_IB_RPTR)/sizeof(mmSDMA1_RLC0_IB_RPTR[0]), 0, 0 },
	{ "mmSDMA1_RLC0_IB_OFFSET", REG_MMIO, 0x370c, &mmSDMA1_RLC0_IB_OFFSET[0], sizeof(mmSDMA1_RLC0_IB_OFFSET)/sizeof(mmSDMA1_RLC0_IB_OFFSET[0]), 0, 0 },
	{ "mmSDMA1_RLC0_IB_BASE_LO", REG_MMIO, 0x370d, &mmSDMA1_RLC0_IB_BASE_LO[0], sizeof(mmSDMA1_RLC0_IB_BASE_LO)/sizeof(mmSDMA1_RLC0_IB_BASE_LO[0]), 0, 0 },
	{ "mmSDMA1_RLC0_IB_BASE_HI", REG_MMIO, 0x370e, &mmSDMA1_RLC0_IB_BASE_HI[0], sizeof(mmSDMA1_RLC0_IB_BASE_HI)/sizeof(mmSDMA1_RLC0_IB_BASE_HI[0]), 0, 0 },
	{ "mmSDMA1_RLC0_IB_SIZE", REG_MMIO, 0x370f, &mmSDMA1_RLC0_IB_SIZE[0], sizeof(mmSDMA1_RLC0_IB_SIZE)/sizeof(mmSDMA1_RLC0_IB_SIZE[0]), 0, 0 },
	{ "mmSDMA1_RLC0_SKIP_CNTL", REG_MMIO, 0x3710, &mmSDMA1_RLC0_SKIP_CNTL[0], sizeof(mmSDMA1_RLC0_SKIP_CNTL)/sizeof(mmSDMA1_RLC0_SKIP_CNTL[0]), 0, 0 },
	{ "mmSDMA1_RLC0_CONTEXT_STATUS", REG_MMIO, 0x3711, &mmSDMA1_RLC0_CONTEXT_STATUS[0], sizeof(mmSDMA1_RLC0_CONTEXT_STATUS)/sizeof(mmSDMA1_RLC0_CONTEXT_STATUS[0]), 0, 0 },
	{ "mmSDMA1_RLC0_DOORBELL", REG_MMIO, 0x3712, &mmSDMA1_RLC0_DOORBELL[0], sizeof(mmSDMA1_RLC0_DOORBELL)/sizeof(mmSDMA1_RLC0_DOORBELL[0]), 0, 0 },
	{ "mmSDMA1_RLC0_VIRTUAL_ADDR", REG_MMIO, 0x3727, &mmSDMA1_RLC0_VIRTUAL_ADDR[0], sizeof(mmSDMA1_RLC0_VIRTUAL_ADDR)/sizeof(mmSDMA1_RLC0_VIRTUAL_ADDR[0]), 0, 0 },
	{ "mmSDMA1_RLC0_APE1_CNTL", REG_MMIO, 0x3728, &mmSDMA1_RLC0_APE1_CNTL[0], sizeof(mmSDMA1_RLC0_APE1_CNTL)/sizeof(mmSDMA1_RLC0_APE1_CNTL[0]), 0, 0 },
	{ "mmSDMA1_RLC0_DOORBELL_LOG", REG_MMIO, 0x3729, &mmSDMA1_RLC0_DOORBELL_LOG[0], sizeof(mmSDMA1_RLC0_DOORBELL_LOG)/sizeof(mmSDMA1_RLC0_DOORBELL_LOG[0]), 0, 0 },
	{ "mmSDMA1_RLC0_WATERMARK", REG_MMIO, 0x372a, &mmSDMA1_RLC0_WATERMARK[0], sizeof(mmSDMA1_RLC0_WATERMARK)/sizeof(mmSDMA1_RLC0_WATERMARK[0]), 0, 0 },
	{ "mmSDMA1_RLC1_RB_CNTL", REG_MMIO, 0x3780, &mmSDMA1_RLC1_RB_CNTL[0], sizeof(mmSDMA1_RLC1_RB_CNTL)/sizeof(mmSDMA1_RLC1_RB_CNTL[0]), 0, 0 },
	{ "mmSDMA1_RLC1_RB_BASE", REG_MMIO, 0x3781, &mmSDMA1_RLC1_RB_BASE[0], sizeof(mmSDMA1_RLC1_RB_BASE)/sizeof(mmSDMA1_RLC1_RB_BASE[0]), 0, 0 },
	{ "mmSDMA1_RLC1_RB_BASE_HI", REG_MMIO, 0x3782, &mmSDMA1_RLC1_RB_BASE_HI[0], sizeof(mmSDMA1_RLC1_RB_BASE_HI)/sizeof(mmSDMA1_RLC1_RB_BASE_HI[0]), 0, 0 },
	{ "mmSDMA1_RLC1_RB_RPTR", REG_MMIO, 0x3783, &mmSDMA1_RLC1_RB_RPTR[0], sizeof(mmSDMA1_RLC1_RB_RPTR)/sizeof(mmSDMA1_RLC1_RB_RPTR[0]), 0, 0 },
	{ "mmSDMA1_RLC1_RB_WPTR", REG_MMIO, 0x3784, &mmSDMA1_RLC1_RB_WPTR[0], sizeof(mmSDMA1_RLC1_RB_WPTR)/sizeof(mmSDMA1_RLC1_RB_WPTR[0]), 0, 0 },
	{ "mmSDMA1_RLC1_RB_WPTR_POLL_CNTL", REG_MMIO, 0x3785, &mmSDMA1_RLC1_RB_WPTR_POLL_CNTL[0], sizeof(mmSDMA1_RLC1_RB_WPTR_POLL_CNTL)/sizeof(mmSDMA1_RLC1_RB_WPTR_POLL_CNTL[0]), 0, 0 },
	{ "mmSDMA1_RLC1_RB_WPTR_POLL_ADDR_HI", REG_MMIO, 0x3786, &mmSDMA1_RLC1_RB_WPTR_POLL_ADDR_HI[0], sizeof(mmSDMA1_RLC1_RB_WPTR_POLL_ADDR_HI)/sizeof(mmSDMA1_RLC1_RB_WPTR_POLL_ADDR_HI[0]), 0, 0 },
	{ "mmSDMA1_RLC1_RB_WPTR_POLL_ADDR_LO", REG_MMIO, 0x3787, &mmSDMA1_RLC1_RB_WPTR_POLL_ADDR_LO[0], sizeof(mmSDMA1_RLC1_RB_WPTR_POLL_ADDR_LO)/sizeof(mmSDMA1_RLC1_RB_WPTR_POLL_ADDR_LO[0]), 0, 0 },
	{ "mmSDMA1_RLC1_RB_RPTR_ADDR_HI", REG_MMIO, 0x3788, &mmSDMA1_RLC1_RB_RPTR_ADDR_HI[0], sizeof(mmSDMA1_RLC1_RB_RPTR_ADDR_HI)/sizeof(mmSDMA1_RLC1_RB_RPTR_ADDR_HI[0]), 0, 0 },
	{ "mmSDMA1_RLC1_RB_RPTR_ADDR_LO", REG_MMIO, 0x3789, &mmSDMA1_RLC1_RB_RPTR_ADDR_LO[0], sizeof(mmSDMA1_RLC1_RB_RPTR_ADDR_LO)/sizeof(mmSDMA1_RLC1_RB_RPTR_ADDR_LO[0]), 0, 0 },
	{ "mmSDMA1_RLC1_IB_CNTL", REG_MMIO, 0x378a, &mmSDMA1_RLC1_IB_CNTL[0], sizeof(mmSDMA1_RLC1_IB_CNTL)/sizeof(mmSDMA1_RLC1_IB_CNTL[0]), 0, 0 },
	{ "mmSDMA1_RLC1_IB_RPTR", REG_MMIO, 0x378b, &mmSDMA1_RLC1_IB_RPTR[0], sizeof(mmSDMA1_RLC1_IB_RPTR)/sizeof(mmSDMA1_RLC1_IB_RPTR[0]), 0, 0 },
	{ "mmSDMA1_RLC1_IB_OFFSET", REG_MMIO, 0x378c, &mmSDMA1_RLC1_IB_OFFSET[0], sizeof(mmSDMA1_RLC1_IB_OFFSET)/sizeof(mmSDMA1_RLC1_IB_OFFSET[0]), 0, 0 },
	{ "mmSDMA1_RLC1_IB_BASE_LO", REG_MMIO, 0x378d, &mmSDMA1_RLC1_IB_BASE_LO[0], sizeof(mmSDMA1_RLC1_IB_BASE_LO)/sizeof(mmSDMA1_RLC1_IB_BASE_LO[0]), 0, 0 },
	{ "mmSDMA1_RLC1_IB_BASE_HI", REG_MMIO, 0x378e, &mmSDMA1_RLC1_IB_BASE_HI[0], sizeof(mmSDMA1_RLC1_IB_BASE_HI)/sizeof(mmSDMA1_RLC1_IB_BASE_HI[0]), 0, 0 },
	{ "mmSDMA1_RLC1_IB_SIZE", REG_MMIO, 0x378f, &mmSDMA1_RLC1_IB_SIZE[0], sizeof(mmSDMA1_RLC1_IB_SIZE)/sizeof(mmSDMA1_RLC1_IB_SIZE[0]), 0, 0 },
	{ "mmSDMA1_RLC1_SKIP_CNTL", REG_MMIO, 0x3790, &mmSDMA1_RLC1_SKIP_CNTL[0], sizeof(mmSDMA1_RLC1_SKIP_CNTL)/sizeof(mmSDMA1_RLC1_SKIP_CNTL[0]), 0, 0 },
	{ "mmSDMA1_RLC1_CONTEXT_STATUS", REG_MMIO, 0x3791, &mmSDMA1_RLC1_CONTEXT_STATUS[0], sizeof(mmSDMA1_RLC1_CONTEXT_STATUS)/sizeof(mmSDMA1_RLC1_CONTEXT_STATUS[0]), 0, 0 },
	{ "mmSDMA1_RLC1_DOORBELL", REG_MMIO, 0x3792, &mmSDMA1_RLC1_DOORBELL[0], sizeof(mmSDMA1_RLC1_DOORBELL)/sizeof(mmSDMA1_RLC1_DOORBELL[0]), 0, 0 },
	{ "mmSDMA1_RLC1_VIRTUAL_ADDR", REG_MMIO, 0x37a7, &mmSDMA1_RLC1_VIRTUAL_ADDR[0], sizeof(mmSDMA1_RLC1_VIRTUAL_ADDR)/sizeof(mmSDMA1_RLC1_VIRTUAL_ADDR[0]), 0, 0 },
	{ "mmSDMA1_RLC1_APE1_CNTL", REG_MMIO, 0x37a8, &mmSDMA1_RLC1_APE1_CNTL[0], sizeof(mmSDMA1_RLC1_APE1_CNTL)/sizeof(mmSDMA1_RLC1_APE1_CNTL[0]), 0, 0 },
	{ "mmSDMA1_RLC1_DOORBELL_LOG", REG_MMIO, 0x37a9, &mmSDMA1_RLC1_DOORBELL_LOG[0], sizeof(mmSDMA1_RLC1_DOORBELL_LOG)/sizeof(mmSDMA1_RLC1_DOORBELL_LOG[0]), 0, 0 },
	{ "mmSDMA1_RLC1_WATERMARK", REG_MMIO, 0x37aa, &mmSDMA1_RLC1_WATERMARK[0], sizeof(mmSDMA1_RLC1_WATERMARK)/sizeof(mmSDMA1_RLC1_WATERMARK[0]), 0, 0 },
	{ "ixEXP1", REG_SMC, 0x38, &ixEXP1[0], sizeof(ixEXP1)/sizeof(ixEXP1[0]), 0, 0 },
	{ "mmSRBM_CNTL", REG_MMIO, 0x390, &mmSRBM_CNTL[0], sizeof(mmSRBM_CNTL)/sizeof(mmSRBM_CNTL[0]), 0, 0 },
	{ "mmSRBM_GFX_CNTL", REG_MMIO, 0x391, &mmSRBM_GFX_CNTL[0], sizeof(mmSRBM_GFX_CNTL)/sizeof(mmSRBM_GFX_CNTL[0]), 0, 0 },
	{ "mmSRBM_STATUS2", REG_MMIO, 0x393, &mmSRBM_STATUS2[0], sizeof(mmSRBM_STATUS2)/sizeof(mmSRBM_STATUS2[0]), 0, 0 },
	{ "mmSRBM_STATUS", REG_MMIO, 0x394, &mmSRBM_STATUS[0], sizeof(mmSRBM_STATUS)/sizeof(mmSRBM_STATUS[0]), 0, 0 },
	{ "mmSRBM_CAM_INDEX", REG_MMIO, 0x396, &mmSRBM_CAM_INDEX[0], sizeof(mmSRBM_CAM_INDEX)/sizeof(mmSRBM_CAM_INDEX[0]), 0, 0 },
	{ "mmSRBM_CAM_DATA", REG_MMIO, 0x397, &mmSRBM_CAM_DATA[0], sizeof(mmSRBM_CAM_DATA)/sizeof(mmSRBM_CAM_DATA[0]), 0, 0 },
	{ "mmSRBM_SOFT_RESET", REG_MMIO, 0x398, &mmSRBM_SOFT_RESET[0], sizeof(mmSRBM_SOFT_RESET)/sizeof(mmSRBM_SOFT_RESET[0]), 0, 0 },
	{ "mmSRBM_DEBUG_CNTL", REG_MMIO, 0x399, &mmSRBM_DEBUG_CNTL[0], sizeof(mmSRBM_DEBUG_CNTL)/sizeof(mmSRBM_DEBUG_CNTL[0]), 0, 0 },
	{ "mmSRBM_DEBUG_DATA", REG_MMIO, 0x39a, &mmSRBM_DEBUG_DATA[0], sizeof(mmSRBM_DEBUG_DATA)/sizeof(mmSRBM_DEBUG_DATA[0]), 0, 0 },
	{ "mmSRBM_CHIP_REVISION", REG_MMIO, 0x39b, &mmSRBM_CHIP_REVISION[0], sizeof(mmSRBM_CHIP_REVISION)/sizeof(mmSRBM_CHIP_REVISION[0]), 0, 0 },
	{ "mmCC_SYS_RB_REDUNDANCY", REG_MMIO, 0x39f, &mmCC_SYS_RB_REDUNDANCY[0], sizeof(mmCC_SYS_RB_REDUNDANCY)/sizeof(mmCC_SYS_RB_REDUNDANCY[0]), 0, 0 },
	{ "mmCC_SYS_RB_BACKEND_DISABLE", REG_MMIO, 0x3a0, &mmCC_SYS_RB_BACKEND_DISABLE[0], sizeof(mmCC_SYS_RB_BACKEND_DISABLE)/sizeof(mmCC_SYS_RB_BACKEND_DISABLE[0]), 0, 0 },
	{ "mmGC_USER_SYS_RB_BACKEND_DISABLE", REG_MMIO, 0x3a1, &mmGC_USER_SYS_RB_BACKEND_DISABLE[0], sizeof(mmGC_USER_SYS_RB_BACKEND_DISABLE)/sizeof(mmGC_USER_SYS_RB_BACKEND_DISABLE[0]), 0, 0 },
	{ "mmSRBM_DEBUG", REG_MMIO, 0x3a4, &mmSRBM_DEBUG[0], sizeof(mmSRBM_DEBUG)/sizeof(mmSRBM_DEBUG[0]), 0, 0 },
	{ "mmSRBM_DEBUG_SNAPSHOT", REG_MMIO, 0x3a5, &mmSRBM_DEBUG_SNAPSHOT[0], sizeof(mmSRBM_DEBUG_SNAPSHOT)/sizeof(mmSRBM_DEBUG_SNAPSHOT[0]), 0, 0 },
	{ "mmSRBM_READ_ERROR", REG_MMIO, 0x3a6, &mmSRBM_READ_ERROR[0], sizeof(mmSRBM_READ_ERROR)/sizeof(mmSRBM_READ_ERROR[0]), 0, 0 },
	{ "mmSRBM_INT_CNTL", REG_MMIO, 0x3a8, &mmSRBM_INT_CNTL[0], sizeof(mmSRBM_INT_CNTL)/sizeof(mmSRBM_INT_CNTL[0]), 0, 0 },
	{ "mmSRBM_INT_STATUS", REG_MMIO, 0x3a9, &mmSRBM_INT_STATUS[0], sizeof(mmSRBM_INT_STATUS)/sizeof(mmSRBM_INT_STATUS[0]), 0, 0 },
	{ "mmSRBM_INT_ACK", REG_MMIO, 0x3aa, &mmSRBM_INT_ACK[0], sizeof(mmSRBM_INT_ACK)/sizeof(mmSRBM_INT_ACK[0]), 0, 0 },
	{ "mmSRBM_MC_CLKEN_CNTL", REG_MMIO, 0x3b3, &mmSRBM_MC_CLKEN_CNTL[0], sizeof(mmSRBM_MC_CLKEN_CNTL)/sizeof(mmSRBM_MC_CLKEN_CNTL[0]), 0, 0 },
	{ "mmSRBM_SYS_CLKEN_CNTL", REG_MMIO, 0x3b4, &mmSRBM_SYS_CLKEN_CNTL[0], sizeof(mmSRBM_SYS_CLKEN_CNTL)/sizeof(mmSRBM_SYS_CLKEN_CNTL[0]), 0, 0 },
	{ "mmSRBM_VCE_CLKEN_CNTL", REG_MMIO, 0x3b5, &mmSRBM_VCE_CLKEN_CNTL[0], sizeof(mmSRBM_VCE_CLKEN_CNTL)/sizeof(mmSRBM_VCE_CLKEN_CNTL[0]), 0, 0 },
	{ "mmSRBM_UVD_CLKEN_CNTL", REG_MMIO, 0x3b6, &mmSRBM_UVD_CLKEN_CNTL[0], sizeof(mmSRBM_UVD_CLKEN_CNTL)/sizeof(mmSRBM_UVD_CLKEN_CNTL[0]), 0, 0 },
	{ "mmSRBM_SDMA_CLKEN_CNTL", REG_MMIO, 0x3b7, &mmSRBM_SDMA_CLKEN_CNTL[0], sizeof(mmSRBM_SDMA_CLKEN_CNTL)/sizeof(mmSRBM_SDMA_CLKEN_CNTL[0]), 0, 0 },
	{ "mmSRBM_SAM_CLKEN_CNTL", REG_MMIO, 0x3b8, &mmSRBM_SAM_CLKEN_CNTL[0], sizeof(mmSRBM_SAM_CLKEN_CNTL)/sizeof(mmSRBM_SAM_CLKEN_CNTL[0]), 0, 0 },
	{ "ixEXP2", REG_SMC, 0x3c, &ixEXP2[0], sizeof(ixEXP2)/sizeof(ixEXP2[0]), 0, 0 },
	{ "mmXDMA_MSTR_CNTL", REG_MMIO, 0x3ec, &mmXDMA_MSTR_CNTL[0], sizeof(mmXDMA_MSTR_CNTL)/sizeof(mmXDMA_MSTR_CNTL[0]), 0, 0 },
	{ "mmXDMA_MSTR_STATUS", REG_MMIO, 0x3ed, &mmXDMA_MSTR_STATUS[0], sizeof(mmXDMA_MSTR_STATUS)/sizeof(mmXDMA_MSTR_STATUS[0]), 0, 0 },
	{ "mmXDMA_MSTR_MEM_CLIENT_CONFIG", REG_MMIO, 0x3ee, &mmXDMA_MSTR_MEM_CLIENT_CONFIG[0], sizeof(mmXDMA_MSTR_MEM_CLIENT_CONFIG)/sizeof(mmXDMA_MSTR_MEM_CLIENT_CONFIG[0]), 0, 0 },
	{ "mmXDMA_MSTR_LOCAL_SURFACE_BASE_ADDR", REG_MMIO, 0x3ef, &mmXDMA_MSTR_LOCAL_SURFACE_BASE_ADDR[0], sizeof(mmXDMA_MSTR_LOCAL_SURFACE_BASE_ADDR)/sizeof(mmXDMA_MSTR_LOCAL_SURFACE_BASE_ADDR[0]), 0, 0 },
	{ "mmXDMA_MSTR_LOCAL_SURFACE_BASE_ADDR_HIGH", REG_MMIO, 0x3f0, &mmXDMA_MSTR_LOCAL_SURFACE_BASE_ADDR_HIGH[0], sizeof(mmXDMA_MSTR_LOCAL_SURFACE_BASE_ADDR_HIGH)/sizeof(mmXDMA_MSTR_LOCAL_SURFACE_BASE_ADDR_HIGH[0]), 0, 0 },
	{ "mmXDMA_MSTR_LOCAL_SURFACE_PITCH", REG_MMIO, 0x3f1, &mmXDMA_MSTR_LOCAL_SURFACE_PITCH[0], sizeof(mmXDMA_MSTR_LOCAL_SURFACE_PITCH)/sizeof(mmXDMA_MSTR_LOCAL_SURFACE_PITCH[0]), 0, 0 },
	{ "mmXDMA_MSTR_CMD_URGENT_CNTL", REG_MMIO, 0x3f2, &mmXDMA_MSTR_CMD_URGENT_CNTL[0], sizeof(mmXDMA_MSTR_CMD_URGENT_CNTL)/sizeof(mmXDMA_MSTR_CMD_URGENT_CNTL[0]), 0, 0 },
	{ "mmXDMA_MSTR_MEM_URGENT_CNTL", REG_MMIO, 0x3f3, &mmXDMA_MSTR_MEM_URGENT_CNTL[0], sizeof(mmXDMA_MSTR_MEM_URGENT_CNTL)/sizeof(mmXDMA_MSTR_MEM_URGENT_CNTL[0]), 0, 0 },
	{ "mmXDMA_MSTR_MEM_UNDERFLOW_CONFIG", REG_MMIO, 0x3f4, &mmXDMA_MSTR_MEM_UNDERFLOW_CONFIG[0], sizeof(mmXDMA_MSTR_MEM_UNDERFLOW_CONFIG)/sizeof(mmXDMA_MSTR_MEM_UNDERFLOW_CONFIG[0]), 0, 0 },
	{ "mmXDMA_MSTR_PCIE_NACK_STATUS", REG_MMIO, 0x3f5, &mmXDMA_MSTR_PCIE_NACK_STATUS[0], sizeof(mmXDMA_MSTR_PCIE_NACK_STATUS)/sizeof(mmXDMA_MSTR_PCIE_NACK_STATUS[0]), 0, 0 },
	{ "mmXDMA_MSTR_MEM_NACK_STATUS", REG_MMIO, 0x3f6, &mmXDMA_MSTR_MEM_NACK_STATUS[0], sizeof(mmXDMA_MSTR_MEM_NACK_STATUS)/sizeof(mmXDMA_MSTR_MEM_NACK_STATUS[0]), 0, 0 },
	{ "mmXDMA_MSTR_VSYNC_GSL_CHECK", REG_MMIO, 0x3f7, &mmXDMA_MSTR_VSYNC_GSL_CHECK[0], sizeof(mmXDMA_MSTR_VSYNC_GSL_CHECK)/sizeof(mmXDMA_MSTR_VSYNC_GSL_CHECK[0]), 0, 0 },
	{ "ixKHFS0", REG_SMC, 0x4, &ixKHFS0[0], sizeof(ixKHFS0)/sizeof(ixKHFS0[0]), 0, 0 },
	{ "ixEXP3", REG_SMC, 0x40, &ixEXP3[0], sizeof(ixEXP3)/sizeof(ixEXP3[0]), 0, 0 },
	{ "mmMDMA_PIPE0_XDMA_MSTR_PIPE_CNTL", REG_MMIO, 0x400, NULL, 0, 0, 0 },
	{ "mmXDMA_MSTR_PIPE_CNTL", REG_MMIO, 0x400, &mmXDMA_MSTR_PIPE_CNTL[0], sizeof(mmXDMA_MSTR_PIPE_CNTL)/sizeof(mmXDMA_MSTR_PIPE_CNTL[0]), 0, 0 },
	{ "mmMDMA_PIPE0_XDMA_MSTR_READ_COMMAND", REG_MMIO, 0x401, NULL, 0, 0, 0 },
	{ "mmXDMA_MSTR_READ_COMMAND", REG_MMIO, 0x401, &mmXDMA_MSTR_READ_COMMAND[0], sizeof(mmXDMA_MSTR_READ_COMMAND)/sizeof(mmXDMA_MSTR_READ_COMMAND[0]), 0, 0 },
	{ "mmMDMA_PIPE0_XDMA_MSTR_CHANNEL_DIM", REG_MMIO, 0x402, NULL, 0, 0, 0 },
	{ "mmXDMA_MSTR_CHANNEL_DIM", REG_MMIO, 0x402, &mmXDMA_MSTR_CHANNEL_DIM[0], sizeof(mmXDMA_MSTR_CHANNEL_DIM)/sizeof(mmXDMA_MSTR_CHANNEL_DIM[0]), 0, 0 },
	{ "mmMDMA_PIPE0_XDMA_MSTR_HEIGHT", REG_MMIO, 0x403, NULL, 0, 0, 0 },
	{ "mmXDMA_MSTR_HEIGHT", REG_MMIO, 0x403, &mmXDMA_MSTR_HEIGHT[0], sizeof(mmXDMA_MSTR_HEIGHT)/sizeof(mmXDMA_MSTR_HEIGHT[0]), 0, 0 },
	{ "mmMDMA_PIPE0_XDMA_MSTR_REMOTE_SURFACE_BASE", REG_MMIO, 0x404, NULL, 0, 0, 0 },
	{ "mmXDMA_MSTR_REMOTE_SURFACE_BASE", REG_MMIO, 0x404, &mmXDMA_MSTR_REMOTE_SURFACE_BASE[0], sizeof(mmXDMA_MSTR_REMOTE_SURFACE_BASE)/sizeof(mmXDMA_MSTR_REMOTE_SURFACE_BASE[0]), 0, 0 },
	{ "mmMDMA_PIPE0_XDMA_MSTR_REMOTE_SURFACE_BASE_HIGH", REG_MMIO, 0x405, NULL, 0, 0, 0 },
	{ "mmXDMA_MSTR_REMOTE_SURFACE_BASE_HIGH", REG_MMIO, 0x405, &mmXDMA_MSTR_REMOTE_SURFACE_BASE_HIGH[0], sizeof(mmXDMA_MSTR_REMOTE_SURFACE_BASE_HIGH)/sizeof(mmXDMA_MSTR_REMOTE_SURFACE_BASE_HIGH[0]), 0, 0 },
	{ "mmMDMA_PIPE0_XDMA_MSTR_REMOTE_GPU_ADDRESS", REG_MMIO, 0x406, NULL, 0, 0, 0 },
	{ "mmXDMA_MSTR_REMOTE_GPU_ADDRESS", REG_MMIO, 0x406, &mmXDMA_MSTR_REMOTE_GPU_ADDRESS[0], sizeof(mmXDMA_MSTR_REMOTE_GPU_ADDRESS)/sizeof(mmXDMA_MSTR_REMOTE_GPU_ADDRESS[0]), 0, 0 },
	{ "mmMDMA_PIPE0_XDMA_MSTR_REMOTE_GPU_ADDRESS_HIGH", REG_MMIO, 0x407, NULL, 0, 0, 0 },
	{ "mmXDMA_MSTR_REMOTE_GPU_ADDRESS_HIGH", REG_MMIO, 0x407, &mmXDMA_MSTR_REMOTE_GPU_ADDRESS_HIGH[0], sizeof(mmXDMA_MSTR_REMOTE_GPU_ADDRESS_HIGH)/sizeof(mmXDMA_MSTR_REMOTE_GPU_ADDRESS_HIGH[0]), 0, 0 },
	{ "mmMDMA_PIPE0_XDMA_MSTR_CACHE_BASE_ADDR", REG_MMIO, 0x408, NULL, 0, 0, 0 },
	{ "mmXDMA_MSTR_CACHE_BASE_ADDR", REG_MMIO, 0x408, &mmXDMA_MSTR_CACHE_BASE_ADDR[0], sizeof(mmXDMA_MSTR_CACHE_BASE_ADDR)/sizeof(mmXDMA_MSTR_CACHE_BASE_ADDR[0]), 0, 0 },
	{ "mmMDMA_PIPE0_XDMA_MSTR_CACHE_BASE_ADDR_HIGH", REG_MMIO, 0x409, NULL, 0, 0, 0 },
	{ "mmXDMA_MSTR_CACHE_BASE_ADDR_HIGH", REG_MMIO, 0x409, &mmXDMA_MSTR_CACHE_BASE_ADDR_HIGH[0], sizeof(mmXDMA_MSTR_CACHE_BASE_ADDR_HIGH)/sizeof(mmXDMA_MSTR_CACHE_BASE_ADDR_HIGH[0]), 0, 0 },
	{ "mmMDMA_PIPE0_XDMA_MSTR_CACHE_PITCH", REG_MMIO, 0x40a, NULL, 0, 0, 0 },
	{ "mmXDMA_MSTR_CACHE_PITCH", REG_MMIO, 0x40a, &mmXDMA_MSTR_CACHE_PITCH[0], sizeof(mmXDMA_MSTR_CACHE_PITCH)/sizeof(mmXDMA_MSTR_CACHE_PITCH[0]), 0, 0 },
	{ "mmMDMA_PIPE0_XDMA_MSTR_CHANNEL_START", REG_MMIO, 0x40b, NULL, 0, 0, 0 },
	{ "mmXDMA_MSTR_CHANNEL_START", REG_MMIO, 0x40b, &mmXDMA_MSTR_CHANNEL_START[0], sizeof(mmXDMA_MSTR_CHANNEL_START)/sizeof(mmXDMA_MSTR_CHANNEL_START[0]), 0, 0 },
	{ "mmMDMA_PIPE0_XDMA_MSTR_MEM_OVERFLOW_CNTL", REG_MMIO, 0x40c, NULL, 0, 0, 0 },
	{ "mmXDMA_MSTR_MEM_OVERFLOW_CNTL", REG_MMIO, 0x40c, &mmXDMA_MSTR_MEM_OVERFLOW_CNTL[0], sizeof(mmXDMA_MSTR_MEM_OVERFLOW_CNTL)/sizeof(mmXDMA_MSTR_MEM_OVERFLOW_CNTL[0]), 0, 0 },
	{ "mmMDMA_PIPE0_XDMA_MSTR_MEM_UNDERFLOW_CNTL", REG_MMIO, 0x40d, NULL, 0, 0, 0 },
	{ "mmXDMA_MSTR_MEM_UNDERFLOW_CNTL", REG_MMIO, 0x40d, &mmXDMA_MSTR_MEM_UNDERFLOW_CNTL[0], sizeof(mmXDMA_MSTR_MEM_UNDERFLOW_CNTL)/sizeof(mmXDMA_MSTR_MEM_UNDERFLOW_CNTL[0]), 0, 0 },
	{ "mmMDMA_PIPE0_XDMA_MSTR_PERFMEAS_STATUS", REG_MMIO, 0x40e, NULL, 0, 0, 0 },
	{ "mmXDMA_MSTR_PERFMEAS_STATUS", REG_MMIO, 0x40e, &mmXDMA_MSTR_PERFMEAS_STATUS[0], sizeof(mmXDMA_MSTR_PERFMEAS_STATUS)/sizeof(mmXDMA_MSTR_PERFMEAS_STATUS[0]), 0, 0 },
	{ "mmMDMA_PIPE0_XDMA_MSTR_PERFMEAS_CNTL", REG_MMIO, 0x40f, NULL, 0, 0, 0 },
	{ "mmXDMA_MSTR_PERFMEAS_CNTL", REG_MMIO, 0x40f, &mmXDMA_MSTR_PERFMEAS_CNTL[0], sizeof(mmXDMA_MSTR_PERFMEAS_CNTL)/sizeof(mmXDMA_MSTR_PERFMEAS_CNTL[0]), 0, 0 },
	{ "mmMDMA_PIPE1_XDMA_MSTR_PIPE_CNTL", REG_MMIO, 0x410, NULL, 0, 0, 0 },
	{ "mmMDMA_PIPE1_XDMA_MSTR_READ_COMMAND", REG_MMIO, 0x411, NULL, 0, 0, 0 },
	{ "mmMDMA_PIPE1_XDMA_MSTR_CHANNEL_DIM", REG_MMIO, 0x412, NULL, 0, 0, 0 },
	{ "mmMDMA_PIPE1_XDMA_MSTR_HEIGHT", REG_MMIO, 0x413, NULL, 0, 0, 0 },
	{ "mmMDMA_PIPE1_XDMA_MSTR_REMOTE_SURFACE_BASE", REG_MMIO, 0x414, NULL, 0, 0, 0 },
	{ "mmMDMA_PIPE1_XDMA_MSTR_REMOTE_SURFACE_BASE_HIGH", REG_MMIO, 0x415, NULL, 0, 0, 0 },
	{ "mmMDMA_PIPE1_XDMA_MSTR_REMOTE_GPU_ADDRESS", REG_MMIO, 0x416, NULL, 0, 0, 0 },
	{ "mmMDMA_PIPE1_XDMA_MSTR_REMOTE_GPU_ADDRESS_HIGH", REG_MMIO, 0x417, NULL, 0, 0, 0 },
	{ "mmMDMA_PIPE1_XDMA_MSTR_CACHE_BASE_ADDR", REG_MMIO, 0x418, NULL, 0, 0, 0 },
	{ "mmMDMA_PIPE1_XDMA_MSTR_CACHE_BASE_ADDR_HIGH", REG_MMIO, 0x419, NULL, 0, 0, 0 },
	{ "mmMDMA_PIPE1_XDMA_MSTR_CACHE_PITCH", REG_MMIO, 0x41a, NULL, 0, 0, 0 },
	{ "mmMDMA_PIPE1_XDMA_MSTR_CHANNEL_START", REG_MMIO, 0x41b, NULL, 0, 0, 0 },
	{ "mmMDMA_PIPE1_XDMA_MSTR_MEM_OVERFLOW_CNTL", REG_MMIO, 0x41c, NULL, 0, 0, 0 },
	{ "mmMDMA_PIPE1_XDMA_MSTR_MEM_UNDERFLOW_CNTL", REG_MMIO, 0x41d, NULL, 0, 0, 0 },
	{ "mmMDMA_PIPE1_XDMA_MSTR_PERFMEAS_STATUS", REG_MMIO, 0x41e, NULL, 0, 0, 0 },
	{ "mmMDMA_PIPE1_XDMA_MSTR_PERFMEAS_CNTL", REG_MMIO, 0x41f, NULL, 0, 0, 0 },
	{ "mmMDMA_PIPE2_XDMA_MSTR_PIPE_CNTL", REG_MMIO, 0x420, NULL, 0, 0, 0 },
	{ "mmMDMA_PIPE2_XDMA_MSTR_READ_COMMAND", REG_MMIO, 0x421, NULL, 0, 0, 0 },
	{ "mmMDMA_PIPE2_XDMA_MSTR_CHANNEL_DIM", REG_MMIO, 0x422, NULL, 0, 0, 0 },
	{ "mmMDMA_PIPE2_XDMA_MSTR_HEIGHT", REG_MMIO, 0x423, NULL, 0, 0, 0 },
	{ "mmMDMA_PIPE2_XDMA_MSTR_REMOTE_SURFACE_BASE", REG_MMIO, 0x424, NULL, 0, 0, 0 },
	{ "mmMDMA_PIPE2_XDMA_MSTR_REMOTE_SURFACE_BASE_HIGH", REG_MMIO, 0x425, NULL, 0, 0, 0 },
	{ "mmMDMA_PIPE2_XDMA_MSTR_REMOTE_GPU_ADDRESS", REG_MMIO, 0x426, NULL, 0, 0, 0 },
	{ "mmMDMA_PIPE2_XDMA_MSTR_REMOTE_GPU_ADDRESS_HIGH", REG_MMIO, 0x427, NULL, 0, 0, 0 },
	{ "mmMDMA_PIPE2_XDMA_MSTR_CACHE_BASE_ADDR", REG_MMIO, 0x428, NULL, 0, 0, 0 },
	{ "mmMDMA_PIPE2_XDMA_MSTR_CACHE_BASE_ADDR_HIGH", REG_MMIO, 0x429, NULL, 0, 0, 0 },
	{ "mmMDMA_PIPE2_XDMA_MSTR_CACHE_PITCH", REG_MMIO, 0x42a, NULL, 0, 0, 0 },
	{ "mmMDMA_PIPE2_XDMA_MSTR_CHANNEL_START", REG_MMIO, 0x42b, NULL, 0, 0, 0 },
	{ "mmMDMA_PIPE2_XDMA_MSTR_MEM_OVERFLOW_CNTL", REG_MMIO, 0x42c, NULL, 0, 0, 0 },
	{ "mmMDMA_PIPE2_XDMA_MSTR_MEM_UNDERFLOW_CNTL", REG_MMIO, 0x42d, NULL, 0, 0, 0 },
	{ "mmMDMA_PIPE2_XDMA_MSTR_PERFMEAS_STATUS", REG_MMIO, 0x42e, NULL, 0, 0, 0 },
	{ "mmMDMA_PIPE2_XDMA_MSTR_PERFMEAS_CNTL", REG_MMIO, 0x42f, NULL, 0, 0, 0 },
	{ "mmMDMA_PIPE3_XDMA_MSTR_PIPE_CNTL", REG_MMIO, 0x430, NULL, 0, 0, 0 },
	{ "mmMDMA_PIPE3_XDMA_MSTR_READ_COMMAND", REG_MMIO, 0x431, NULL, 0, 0, 0 },
	{ "mmMDMA_PIPE3_XDMA_MSTR_CHANNEL_DIM", REG_MMIO, 0x432, NULL, 0, 0, 0 },
	{ "mmMDMA_PIPE3_XDMA_MSTR_HEIGHT", REG_MMIO, 0x433, NULL, 0, 0, 0 },
	{ "mmMDMA_PIPE3_XDMA_MSTR_REMOTE_SURFACE_BASE", REG_MMIO, 0x434, NULL, 0, 0, 0 },
	{ "mmMDMA_PIPE3_XDMA_MSTR_REMOTE_SURFACE_BASE_HIGH", REG_MMIO, 0x435, NULL, 0, 0, 0 },
	{ "mmMDMA_PIPE3_XDMA_MSTR_REMOTE_GPU_ADDRESS", REG_MMIO, 0x436, NULL, 0, 0, 0 },
	{ "mmMDMA_PIPE3_XDMA_MSTR_REMOTE_GPU_ADDRESS_HIGH", REG_MMIO, 0x437, NULL, 0, 0, 0 },
	{ "mmMDMA_PIPE3_XDMA_MSTR_CACHE_BASE_ADDR", REG_MMIO, 0x438, NULL, 0, 0, 0 },
	{ "mmMDMA_PIPE3_XDMA_MSTR_CACHE_BASE_ADDR_HIGH", REG_MMIO, 0x439, NULL, 0, 0, 0 },
	{ "mmMDMA_PIPE3_XDMA_MSTR_CACHE_PITCH", REG_MMIO, 0x43a, NULL, 0, 0, 0 },
	{ "mmMDMA_PIPE3_XDMA_MSTR_CHANNEL_START", REG_MMIO, 0x43b, NULL, 0, 0, 0 },
	{ "mmMDMA_PIPE3_XDMA_MSTR_MEM_OVERFLOW_CNTL", REG_MMIO, 0x43c, NULL, 0, 0, 0 },
	{ "mmMDMA_PIPE3_XDMA_MSTR_MEM_UNDERFLOW_CNTL", REG_MMIO, 0x43d, NULL, 0, 0, 0 },
	{ "mmMDMA_PIPE3_XDMA_MSTR_PERFMEAS_STATUS", REG_MMIO, 0x43e, NULL, 0, 0, 0 },
	{ "mmMDMA_PIPE3_XDMA_MSTR_PERFMEAS_CNTL", REG_MMIO, 0x43f, NULL, 0, 0, 0 },
	{ "ixEXP4", REG_SMC, 0x44, &ixEXP4[0], sizeof(ixEXP4)/sizeof(ixEXP4[0]), 0, 0 },
	{ "mmMDMA_PIPE4_XDMA_MSTR_PIPE_CNTL", REG_MMIO, 0x440, NULL, 0, 0, 0 },
	{ "mmMDMA_PIPE4_XDMA_MSTR_READ_COMMAND", REG_MMIO, 0x441, NULL, 0, 0, 0 },
	{ "mmMDMA_PIPE4_XDMA_MSTR_CHANNEL_DIM", REG_MMIO, 0x442, NULL, 0, 0, 0 },
	{ "mmMDMA_PIPE4_XDMA_MSTR_HEIGHT", REG_MMIO, 0x443, NULL, 0, 0, 0 },
	{ "mmMDMA_PIPE4_XDMA_MSTR_REMOTE_SURFACE_BASE", REG_MMIO, 0x444, NULL, 0, 0, 0 },
	{ "mmMDMA_PIPE4_XDMA_MSTR_REMOTE_SURFACE_BASE_HIGH", REG_MMIO, 0x445, NULL, 0, 0, 0 },
	{ "mmMDMA_PIPE4_XDMA_MSTR_REMOTE_GPU_ADDRESS", REG_MMIO, 0x446, NULL, 0, 0, 0 },
	{ "mmMDMA_PIPE4_XDMA_MSTR_REMOTE_GPU_ADDRESS_HIGH", REG_MMIO, 0x447, NULL, 0, 0, 0 },
	{ "mmMDMA_PIPE4_XDMA_MSTR_CACHE_BASE_ADDR", REG_MMIO, 0x448, NULL, 0, 0, 0 },
	{ "mmMDMA_PIPE4_XDMA_MSTR_CACHE_BASE_ADDR_HIGH", REG_MMIO, 0x449, NULL, 0, 0, 0 },
	{ "mmMDMA_PIPE4_XDMA_MSTR_CACHE_PITCH", REG_MMIO, 0x44a, NULL, 0, 0, 0 },
	{ "mmMDMA_PIPE4_XDMA_MSTR_CHANNEL_START", REG_MMIO, 0x44b, NULL, 0, 0, 0 },
	{ "mmMDMA_PIPE4_XDMA_MSTR_MEM_OVERFLOW_CNTL", REG_MMIO, 0x44c, NULL, 0, 0, 0 },
	{ "mmMDMA_PIPE4_XDMA_MSTR_MEM_UNDERFLOW_CNTL", REG_MMIO, 0x44d, NULL, 0, 0, 0 },
	{ "mmMDMA_PIPE4_XDMA_MSTR_PERFMEAS_STATUS", REG_MMIO, 0x44e, NULL, 0, 0, 0 },
	{ "mmMDMA_PIPE4_XDMA_MSTR_PERFMEAS_CNTL", REG_MMIO, 0x44f, NULL, 0, 0, 0 },
	{ "mmMDMA_PIPE5_XDMA_MSTR_PIPE_CNTL", REG_MMIO, 0x450, NULL, 0, 0, 0 },
	{ "mmMDMA_PIPE5_XDMA_MSTR_READ_COMMAND", REG_MMIO, 0x451, NULL, 0, 0, 0 },
	{ "mmMDMA_PIPE5_XDMA_MSTR_CHANNEL_DIM", REG_MMIO, 0x452, NULL, 0, 0, 0 },
	{ "mmMDMA_PIPE5_XDMA_MSTR_HEIGHT", REG_MMIO, 0x453, NULL, 0, 0, 0 },
	{ "mmMDMA_PIPE5_XDMA_MSTR_REMOTE_SURFACE_BASE", REG_MMIO, 0x454, NULL, 0, 0, 0 },
	{ "mmMDMA_PIPE5_XDMA_MSTR_REMOTE_SURFACE_BASE_HIGH", REG_MMIO, 0x455, NULL, 0, 0, 0 },
	{ "mmMDMA_PIPE5_XDMA_MSTR_REMOTE_GPU_ADDRESS", REG_MMIO, 0x456, NULL, 0, 0, 0 },
	{ "mmMDMA_PIPE5_XDMA_MSTR_REMOTE_GPU_ADDRESS_HIGH", REG_MMIO, 0x457, NULL, 0, 0, 0 },
	{ "mmMDMA_PIPE5_XDMA_MSTR_CACHE_BASE_ADDR", REG_MMIO, 0x458, NULL, 0, 0, 0 },
	{ "mmMDMA_PIPE5_XDMA_MSTR_CACHE_BASE_ADDR_HIGH", REG_MMIO, 0x459, NULL, 0, 0, 0 },
	{ "mmMDMA_PIPE5_XDMA_MSTR_CACHE_PITCH", REG_MMIO, 0x45a, NULL, 0, 0, 0 },
	{ "mmMDMA_PIPE5_XDMA_MSTR_CHANNEL_START", REG_MMIO, 0x45b, NULL, 0, 0, 0 },
	{ "mmMDMA_PIPE5_XDMA_MSTR_MEM_OVERFLOW_CNTL", REG_MMIO, 0x45c, NULL, 0, 0, 0 },
	{ "mmMDMA_PIPE5_XDMA_MSTR_MEM_UNDERFLOW_CNTL", REG_MMIO, 0x45d, NULL, 0, 0, 0 },
	{ "mmMDMA_PIPE5_XDMA_MSTR_PERFMEAS_STATUS", REG_MMIO, 0x45e, NULL, 0, 0, 0 },
	{ "mmMDMA_PIPE5_XDMA_MSTR_PERFMEAS_CNTL", REG_MMIO, 0x45f, NULL, 0, 0, 0 },
	{ "mmXDMA_SLV_CNTL", REG_MMIO, 0x460, &mmXDMA_SLV_CNTL[0], sizeof(mmXDMA_SLV_CNTL)/sizeof(mmXDMA_SLV_CNTL[0]), 0, 0 },
	{ "mmXDMA_SLV_MEM_CLIENT_CONFIG", REG_MMIO, 0x461, &mmXDMA_SLV_MEM_CLIENT_CONFIG[0], sizeof(mmXDMA_SLV_MEM_CLIENT_CONFIG)/sizeof(mmXDMA_SLV_MEM_CLIENT_CONFIG[0]), 0, 0 },
	{ "mmXDMA_SLV_SLS_PITCH", REG_MMIO, 0x462, &mmXDMA_SLV_SLS_PITCH[0], sizeof(mmXDMA_SLV_SLS_PITCH)/sizeof(mmXDMA_SLV_SLS_PITCH[0]), 0, 0 },
	{ "mmXDMA_SLV_READ_URGENT_CNTL", REG_MMIO, 0x463, &mmXDMA_SLV_READ_URGENT_CNTL[0], sizeof(mmXDMA_SLV_READ_URGENT_CNTL)/sizeof(mmXDMA_SLV_READ_URGENT_CNTL[0]), 0, 0 },
	{ "mmXDMA_SLV_WRITE_URGENT_CNTL", REG_MMIO, 0x464, &mmXDMA_SLV_WRITE_URGENT_CNTL[0], sizeof(mmXDMA_SLV_WRITE_URGENT_CNTL)/sizeof(mmXDMA_SLV_WRITE_URGENT_CNTL[0]), 0, 0 },
	{ "mmXDMA_SLV_WB_RATE_CNTL", REG_MMIO, 0x465, &mmXDMA_SLV_WB_RATE_CNTL[0], sizeof(mmXDMA_SLV_WB_RATE_CNTL)/sizeof(mmXDMA_SLV_WB_RATE_CNTL[0]), 0, 0 },
	{ "mmXDMA_SLV_READ_LATENCY_MINMAX", REG_MMIO, 0x466, &mmXDMA_SLV_READ_LATENCY_MINMAX[0], sizeof(mmXDMA_SLV_READ_LATENCY_MINMAX)/sizeof(mmXDMA_SLV_READ_LATENCY_MINMAX[0]), 0, 0 },
	{ "mmXDMA_SLV_READ_LATENCY_AVE", REG_MMIO, 0x467, &mmXDMA_SLV_READ_LATENCY_AVE[0], sizeof(mmXDMA_SLV_READ_LATENCY_AVE)/sizeof(mmXDMA_SLV_READ_LATENCY_AVE[0]), 0, 0 },
	{ "mmXDMA_SLV_PCIE_NACK_STATUS", REG_MMIO, 0x468, &mmXDMA_SLV_PCIE_NACK_STATUS[0], sizeof(mmXDMA_SLV_PCIE_NACK_STATUS)/sizeof(mmXDMA_SLV_PCIE_NACK_STATUS[0]), 0, 0 },
	{ "mmXDMA_SLV_MEM_NACK_STATUS", REG_MMIO, 0x469, &mmXDMA_SLV_MEM_NACK_STATUS[0], sizeof(mmXDMA_SLV_MEM_NACK_STATUS)/sizeof(mmXDMA_SLV_MEM_NACK_STATUS[0]), 0, 0 },
	{ "mmXDMA_SLV_RDRET_BUF_STATUS", REG_MMIO, 0x46a, &mmXDMA_SLV_RDRET_BUF_STATUS[0], sizeof(mmXDMA_SLV_RDRET_BUF_STATUS)/sizeof(mmXDMA_SLV_RDRET_BUF_STATUS[0]), 0, 0 },
	{ "mmXDMA_SLV_READ_LATENCY_TIMER", REG_MMIO, 0x46b, &mmXDMA_SLV_READ_LATENCY_TIMER[0], sizeof(mmXDMA_SLV_READ_LATENCY_TIMER)/sizeof(mmXDMA_SLV_READ_LATENCY_TIMER[0]), 0, 0 },
	{ "mmXDMA_SLV_FLIP_PENDING", REG_MMIO, 0x46c, &mmXDMA_SLV_FLIP_PENDING[0], sizeof(mmXDMA_SLV_FLIP_PENDING)/sizeof(mmXDMA_SLV_FLIP_PENDING[0]), 0, 0 },
	{ "mmSDMA_CHANNEL0_XDMA_SLV_CHANNEL_CNTL", REG_MMIO, 0x470, NULL, 0, 0, 0 },
	{ "mmXDMA_SLV_CHANNEL_CNTL", REG_MMIO, 0x470, &mmXDMA_SLV_CHANNEL_CNTL[0], sizeof(mmXDMA_SLV_CHANNEL_CNTL)/sizeof(mmXDMA_SLV_CHANNEL_CNTL[0]), 0, 0 },
	{ "mmSDMA_CHANNEL0_XDMA_SLV_REMOTE_GPU_ADDRESS", REG_MMIO, 0x471, NULL, 0, 0, 0 },
	{ "mmXDMA_SLV_REMOTE_GPU_ADDRESS", REG_MMIO, 0x471, &mmXDMA_SLV_REMOTE_GPU_ADDRESS[0], sizeof(mmXDMA_SLV_REMOTE_GPU_ADDRESS)/sizeof(mmXDMA_SLV_REMOTE_GPU_ADDRESS[0]), 0, 0 },
	{ "mmSDMA_CHANNEL0_XDMA_SLV_REMOTE_GPU_ADDRESS_HIGH", REG_MMIO, 0x472, NULL, 0, 0, 0 },
	{ "mmXDMA_SLV_REMOTE_GPU_ADDRESS_HIGH", REG_MMIO, 0x472, &mmXDMA_SLV_REMOTE_GPU_ADDRESS_HIGH[0], sizeof(mmXDMA_SLV_REMOTE_GPU_ADDRESS_HIGH)/sizeof(mmXDMA_SLV_REMOTE_GPU_ADDRESS_HIGH[0]), 0, 0 },
	{ "mmSDMA_CHANNEL1_XDMA_SLV_CHANNEL_CNTL", REG_MMIO, 0x478, NULL, 0, 0, 0 },
	{ "mmSDMA_CHANNEL1_XDMA_SLV_REMOTE_GPU_ADDRESS", REG_MMIO, 0x479, NULL, 0, 0, 0 },
	{ "mmSDMA_CHANNEL1_XDMA_SLV_REMOTE_GPU_ADDRESS_HIGH", REG_MMIO, 0x47a, NULL, 0, 0, 0 },
	{ "ixEXP5", REG_SMC, 0x48, &ixEXP5[0], sizeof(ixEXP5)/sizeof(ixEXP5[0]), 0, 0 },
	{ "mmSDMA_CHANNEL2_XDMA_SLV_CHANNEL_CNTL", REG_MMIO, 0x480, NULL, 0, 0, 0 },
	{ "mmSDMA_CHANNEL2_XDMA_SLV_REMOTE_GPU_ADDRESS", REG_MMIO, 0x481, NULL, 0, 0, 0 },
	{ "mmSDMA_CHANNEL2_XDMA_SLV_REMOTE_GPU_ADDRESS_HIGH", REG_MMIO, 0x482, NULL, 0, 0, 0 },
	{ "mmSDMA_CHANNEL3_XDMA_SLV_CHANNEL_CNTL", REG_MMIO, 0x488, NULL, 0, 0, 0 },
	{ "mmSDMA_CHANNEL3_XDMA_SLV_REMOTE_GPU_ADDRESS", REG_MMIO, 0x489, NULL, 0, 0, 0 },
	{ "mmSDMA_CHANNEL3_XDMA_SLV_REMOTE_GPU_ADDRESS_HIGH", REG_MMIO, 0x48a, NULL, 0, 0, 0 },
	{ "mmSDMA_CHANNEL4_XDMA_SLV_CHANNEL_CNTL", REG_MMIO, 0x490, NULL, 0, 0, 0 },
	{ "mmSDMA_CHANNEL4_XDMA_SLV_REMOTE_GPU_ADDRESS", REG_MMIO, 0x491, NULL, 0, 0, 0 },
	{ "mmSDMA_CHANNEL4_XDMA_SLV_REMOTE_GPU_ADDRESS_HIGH", REG_MMIO, 0x492, NULL, 0, 0, 0 },
	{ "mmSDMA_CHANNEL5_XDMA_SLV_CHANNEL_CNTL", REG_MMIO, 0x498, NULL, 0, 0, 0 },
	{ "mmSDMA_CHANNEL5_XDMA_SLV_REMOTE_GPU_ADDRESS", REG_MMIO, 0x499, NULL, 0, 0, 0 },
	{ "mmSDMA_CHANNEL5_XDMA_SLV_REMOTE_GPU_ADDRESS_HIGH", REG_MMIO, 0x49a, NULL, 0, 0, 0 },
	{ "ixEXP6", REG_SMC, 0x4c, &ixEXP6[0], sizeof(ixEXP6)/sizeof(ixEXP6[0]), 0, 0 },
	{ "ixEXP7", REG_SMC, 0x50, &ixEXP7[0], sizeof(ixEXP7)/sizeof(ixEXP7[0]), 0, 0 },
	{ "ixLX0", REG_SMC, 0x54, &ixLX0[0], sizeof(ixLX0)/sizeof(ixLX0[0]), 0, 0 },
	{ "ixLX1", REG_SMC, 0x58, &ixLX1[0], sizeof(ixLX1)/sizeof(ixLX1[0]), 0, 0 },
	{ "ixLX2", REG_SMC, 0x5c, &ixLX2[0], sizeof(ixLX2)/sizeof(ixLX2[0]), 0, 0 },
	{ "ixLX3", REG_SMC, 0x60, &ixLX3[0], sizeof(ixLX3)/sizeof(ixLX3[0]), 0, 0 },
	{ "mmSRBM_PERFMON_CNTL", REG_MMIO, 0x700, &mmSRBM_PERFMON_CNTL[0], sizeof(mmSRBM_PERFMON_CNTL)/sizeof(mmSRBM_PERFMON_CNTL[0]), 0, 0 },
	{ "mmSRBM_PERFCOUNTER0_SELECT", REG_MMIO, 0x701, &mmSRBM_PERFCOUNTER0_SELECT[0], sizeof(mmSRBM_PERFCOUNTER0_SELECT)/sizeof(mmSRBM_PERFCOUNTER0_SELECT[0]), 0, 0 },
	{ "mmSRBM_PERFCOUNTER1_SELECT", REG_MMIO, 0x702, &mmSRBM_PERFCOUNTER1_SELECT[0], sizeof(mmSRBM_PERFCOUNTER1_SELECT)/sizeof(mmSRBM_PERFCOUNTER1_SELECT[0]), 0, 0 },
	{ "mmSRBM_PERFCOUNTER0_LO", REG_MMIO, 0x703, &mmSRBM_PERFCOUNTER0_LO[0], sizeof(mmSRBM_PERFCOUNTER0_LO)/sizeof(mmSRBM_PERFCOUNTER0_LO[0]), 0, 0 },
	{ "mmSRBM_PERFCOUNTER0_HI", REG_MMIO, 0x704, &mmSRBM_PERFCOUNTER0_HI[0], sizeof(mmSRBM_PERFCOUNTER0_HI)/sizeof(mmSRBM_PERFCOUNTER0_HI[0]), 0, 0 },
	{ "mmSRBM_PERFCOUNTER1_LO", REG_MMIO, 0x705, &mmSRBM_PERFCOUNTER1_LO[0], sizeof(mmSRBM_PERFCOUNTER1_LO)/sizeof(mmSRBM_PERFCOUNTER1_LO[0]), 0, 0 },
	{ "mmSRBM_PERFCOUNTER1_HI", REG_MMIO, 0x706, &mmSRBM_PERFCOUNTER1_HI[0], sizeof(mmSRBM_PERFCOUNTER1_HI)/sizeof(mmSRBM_PERFCOUNTER1_HI[0]), 0, 0 },
	{ "ixKHFS1", REG_SMC, 0x8, &ixKHFS1[0], sizeof(ixKHFS1)/sizeof(ixKHFS1[0]), 0, 0 },
	{ "mmHDP_HOST_PATH_CNTL", REG_MMIO, 0xb00, &mmHDP_HOST_PATH_CNTL[0], sizeof(mmHDP_HOST_PATH_CNTL)/sizeof(mmHDP_HOST_PATH_CNTL[0]), 0, 0 },
	{ "mmHDP_NONSURFACE_BASE", REG_MMIO, 0xb01, &mmHDP_NONSURFACE_BASE[0], sizeof(mmHDP_NONSURFACE_BASE)/sizeof(mmHDP_NONSURFACE_BASE[0]), 0, 0 },
	{ "mmHDP_NONSURFACE_INFO", REG_MMIO, 0xb02, &mmHDP_NONSURFACE_INFO[0], sizeof(mmHDP_NONSURFACE_INFO)/sizeof(mmHDP_NONSURFACE_INFO[0]), 0, 0 },
	{ "mmHDP_NONSURFACE_SIZE", REG_MMIO, 0xb03, &mmHDP_NONSURFACE_SIZE[0], sizeof(mmHDP_NONSURFACE_SIZE)/sizeof(mmHDP_NONSURFACE_SIZE[0]), 0, 0 },
	{ "mmHDP_NONSURF_FLAGS", REG_MMIO, 0xbc9, &mmHDP_NONSURF_FLAGS[0], sizeof(mmHDP_NONSURF_FLAGS)/sizeof(mmHDP_NONSURF_FLAGS[0]), 0, 0 },
	{ "mmHDP_NONSURF_FLAGS_CLR", REG_MMIO, 0xbca, &mmHDP_NONSURF_FLAGS_CLR[0], sizeof(mmHDP_NONSURF_FLAGS_CLR)/sizeof(mmHDP_NONSURF_FLAGS_CLR[0]), 0, 0 },
	{ "mmHDP_SW_SEMAPHORE", REG_MMIO, 0xbcb, &mmHDP_SW_SEMAPHORE[0], sizeof(mmHDP_SW_SEMAPHORE)/sizeof(mmHDP_SW_SEMAPHORE[0]), 0, 0 },
	{ "mmHDP_DEBUG0", REG_MMIO, 0xbcc, &mmHDP_DEBUG0[0], sizeof(mmHDP_DEBUG0)/sizeof(mmHDP_DEBUG0[0]), 0, 0 },
	{ "mmHDP_DEBUG1", REG_MMIO, 0xbcd, &mmHDP_DEBUG1[0], sizeof(mmHDP_DEBUG1)/sizeof(mmHDP_DEBUG1[0]), 0, 0 },
	{ "mmHDP_LAST_SURFACE_HIT", REG_MMIO, 0xbce, &mmHDP_LAST_SURFACE_HIT[0], sizeof(mmHDP_LAST_SURFACE_HIT)/sizeof(mmHDP_LAST_SURFACE_HIT[0]), 0, 0 },
	{ "mmHDP_TILING_CONFIG", REG_MMIO, 0xbcf, &mmHDP_TILING_CONFIG[0], sizeof(mmHDP_TILING_CONFIG)/sizeof(mmHDP_TILING_CONFIG[0]), 0, 0 },
	{ "mmHDP_SC_MULTI_CHIP_CNTL", REG_MMIO, 0xbd0, &mmHDP_SC_MULTI_CHIP_CNTL[0], sizeof(mmHDP_SC_MULTI_CHIP_CNTL)/sizeof(mmHDP_SC_MULTI_CHIP_CNTL[0]), 0, 0 },
	{ "mmHDP_OUTSTANDING_REQ", REG_MMIO, 0xbd1, &mmHDP_OUTSTANDING_REQ[0], sizeof(mmHDP_OUTSTANDING_REQ)/sizeof(mmHDP_OUTSTANDING_REQ[0]), 0, 0 },
	{ "mmHDP_ADDR_CONFIG", REG_MMIO, 0xbd2, &mmHDP_ADDR_CONFIG[0], sizeof(mmHDP_ADDR_CONFIG)/sizeof(mmHDP_ADDR_CONFIG[0]), 0, 0 },
	{ "mmHDP_MISC_CNTL", REG_MMIO, 0xbd3, &mmHDP_MISC_CNTL[0], sizeof(mmHDP_MISC_CNTL)/sizeof(mmHDP_MISC_CNTL[0]), 0, 0 },
	{ "mmHDP_MEM_POWER_LS", REG_MMIO, 0xbd4, &mmHDP_MEM_POWER_LS[0], sizeof(mmHDP_MEM_POWER_LS)/sizeof(mmHDP_MEM_POWER_LS[0]), 0, 0 },
	{ "mmHDP_NONSURFACE_PREFETCH", REG_MMIO, 0xbd5, &mmHDP_NONSURFACE_PREFETCH[0], sizeof(mmHDP_NONSURFACE_PREFETCH)/sizeof(mmHDP_NONSURFACE_PREFETCH[0]), 0, 0 },
	{ "mmHDP_MEMIO_CNTL", REG_MMIO, 0xbf6, &mmHDP_MEMIO_CNTL[0], sizeof(mmHDP_MEMIO_CNTL)/sizeof(mmHDP_MEMIO_CNTL[0]), 0, 0 },
	{ "mmHDP_MEMIO_ADDR", REG_MMIO, 0xbf7, &mmHDP_MEMIO_ADDR[0], sizeof(mmHDP_MEMIO_ADDR)/sizeof(mmHDP_MEMIO_ADDR[0]), 0, 0 },
	{ "mmHDP_MEMIO_STATUS", REG_MMIO, 0xbf8, &mmHDP_MEMIO_STATUS[0], sizeof(mmHDP_MEMIO_STATUS)/sizeof(mmHDP_MEMIO_STATUS[0]), 0, 0 },
	{ "mmHDP_MEMIO_WR_DATA", REG_MMIO, 0xbf9, &mmHDP_MEMIO_WR_DATA[0], sizeof(mmHDP_MEMIO_WR_DATA)/sizeof(mmHDP_MEMIO_WR_DATA[0]), 0, 0 },
	{ "mmHDP_MEMIO_RD_DATA", REG_MMIO, 0xbfa, &mmHDP_MEMIO_RD_DATA[0], sizeof(mmHDP_MEMIO_RD_DATA)/sizeof(mmHDP_MEMIO_RD_DATA[0]), 0, 0 },
	{ "ixKHFS2", REG_SMC, 0xc, &ixKHFS2[0], sizeof(ixKHFS2)/sizeof(ixKHFS2[0]), 0, 0 },
	{ "mmHDP_XDP_DIRECT2HDP_FIRST", REG_MMIO, 0xc00, &mmHDP_XDP_DIRECT2HDP_FIRST[0], sizeof(mmHDP_XDP_DIRECT2HDP_FIRST)/sizeof(mmHDP_XDP_DIRECT2HDP_FIRST[0]), 0, 0 },
	{ "mmHDP_XDP_D2H_FLUSH", REG_MMIO, 0xc01, &mmHDP_XDP_D2H_FLUSH[0], sizeof(mmHDP_XDP_D2H_FLUSH)/sizeof(mmHDP_XDP_D2H_FLUSH[0]), 0, 0 },
	{ "mmHDP_XDP_D2H_BAR_UPDATE", REG_MMIO, 0xc02, &mmHDP_XDP_D2H_BAR_UPDATE[0], sizeof(mmHDP_XDP_D2H_BAR_UPDATE)/sizeof(mmHDP_XDP_D2H_BAR_UPDATE[0]), 0, 0 },
	{ "mmHDP_XDP_D2H_RSVD_3", REG_MMIO, 0xc03, &mmHDP_XDP_D2H_RSVD_3[0], sizeof(mmHDP_XDP_D2H_RSVD_3)/sizeof(mmHDP_XDP_D2H_RSVD_3[0]), 0, 0 },
	{ "mmHDP_XDP_D2H_RSVD_4", REG_MMIO, 0xc04, &mmHDP_XDP_D2H_RSVD_4[0], sizeof(mmHDP_XDP_D2H_RSVD_4)/sizeof(mmHDP_XDP_D2H_RSVD_4[0]), 0, 0 },
	{ "mmHDP_XDP_D2H_RSVD_5", REG_MMIO, 0xc05, &mmHDP_XDP_D2H_RSVD_5[0], sizeof(mmHDP_XDP_D2H_RSVD_5)/sizeof(mmHDP_XDP_D2H_RSVD_5[0]), 0, 0 },
	{ "mmHDP_XDP_D2H_RSVD_6", REG_MMIO, 0xc06, &mmHDP_XDP_D2H_RSVD_6[0], sizeof(mmHDP_XDP_D2H_RSVD_6)/sizeof(mmHDP_XDP_D2H_RSVD_6[0]), 0, 0 },
	{ "mmHDP_XDP_D2H_RSVD_7", REG_MMIO, 0xc07, &mmHDP_XDP_D2H_RSVD_7[0], sizeof(mmHDP_XDP_D2H_RSVD_7)/sizeof(mmHDP_XDP_D2H_RSVD_7[0]), 0, 0 },
	{ "mmHDP_XDP_D2H_RSVD_8", REG_MMIO, 0xc08, &mmHDP_XDP_D2H_RSVD_8[0], sizeof(mmHDP_XDP_D2H_RSVD_8)/sizeof(mmHDP_XDP_D2H_RSVD_8[0]), 0, 0 },
	{ "mmHDP_XDP_D2H_RSVD_9", REG_MMIO, 0xc09, &mmHDP_XDP_D2H_RSVD_9[0], sizeof(mmHDP_XDP_D2H_RSVD_9)/sizeof(mmHDP_XDP_D2H_RSVD_9[0]), 0, 0 },
	{ "mmHDP_XDP_D2H_RSVD_10", REG_MMIO, 0xc0a, &mmHDP_XDP_D2H_RSVD_10[0], sizeof(mmHDP_XDP_D2H_RSVD_10)/sizeof(mmHDP_XDP_D2H_RSVD_10[0]), 0, 0 },
	{ "mmHDP_XDP_D2H_RSVD_11", REG_MMIO, 0xc0b, &mmHDP_XDP_D2H_RSVD_11[0], sizeof(mmHDP_XDP_D2H_RSVD_11)/sizeof(mmHDP_XDP_D2H_RSVD_11[0]), 0, 0 },
	{ "mmHDP_XDP_D2H_RSVD_12", REG_MMIO, 0xc0c, &mmHDP_XDP_D2H_RSVD_12[0], sizeof(mmHDP_XDP_D2H_RSVD_12)/sizeof(mmHDP_XDP_D2H_RSVD_12[0]), 0, 0 },
	{ "mmHDP_XDP_D2H_RSVD_13", REG_MMIO, 0xc0d, &mmHDP_XDP_D2H_RSVD_13[0], sizeof(mmHDP_XDP_D2H_RSVD_13)/sizeof(mmHDP_XDP_D2H_RSVD_13[0]), 0, 0 },
	{ "mmHDP_XDP_D2H_RSVD_14", REG_MMIO, 0xc0e, &mmHDP_XDP_D2H_RSVD_14[0], sizeof(mmHDP_XDP_D2H_RSVD_14)/sizeof(mmHDP_XDP_D2H_RSVD_14[0]), 0, 0 },
	{ "mmHDP_XDP_D2H_RSVD_15", REG_MMIO, 0xc0f, &mmHDP_XDP_D2H_RSVD_15[0], sizeof(mmHDP_XDP_D2H_RSVD_15)/sizeof(mmHDP_XDP_D2H_RSVD_15[0]), 0, 0 },
	{ "mmHDP_XDP_D2H_RSVD_16", REG_MMIO, 0xc10, &mmHDP_XDP_D2H_RSVD_16[0], sizeof(mmHDP_XDP_D2H_RSVD_16)/sizeof(mmHDP_XDP_D2H_RSVD_16[0]), 0, 0 },
	{ "mmHDP_XDP_D2H_RSVD_17", REG_MMIO, 0xc11, &mmHDP_XDP_D2H_RSVD_17[0], sizeof(mmHDP_XDP_D2H_RSVD_17)/sizeof(mmHDP_XDP_D2H_RSVD_17[0]), 0, 0 },
	{ "mmHDP_XDP_D2H_RSVD_18", REG_MMIO, 0xc12, &mmHDP_XDP_D2H_RSVD_18[0], sizeof(mmHDP_XDP_D2H_RSVD_18)/sizeof(mmHDP_XDP_D2H_RSVD_18[0]), 0, 0 },
	{ "mmHDP_XDP_D2H_RSVD_19", REG_MMIO, 0xc13, &mmHDP_XDP_D2H_RSVD_19[0], sizeof(mmHDP_XDP_D2H_RSVD_19)/sizeof(mmHDP_XDP_D2H_RSVD_19[0]), 0, 0 },
	{ "mmHDP_XDP_D2H_RSVD_20", REG_MMIO, 0xc14, &mmHDP_XDP_D2H_RSVD_20[0], sizeof(mmHDP_XDP_D2H_RSVD_20)/sizeof(mmHDP_XDP_D2H_RSVD_20[0]), 0, 0 },
	{ "mmHDP_XDP_D2H_RSVD_21", REG_MMIO, 0xc15, &mmHDP_XDP_D2H_RSVD_21[0], sizeof(mmHDP_XDP_D2H_RSVD_21)/sizeof(mmHDP_XDP_D2H_RSVD_21[0]), 0, 0 },
	{ "mmHDP_XDP_D2H_RSVD_22", REG_MMIO, 0xc16, &mmHDP_XDP_D2H_RSVD_22[0], sizeof(mmHDP_XDP_D2H_RSVD_22)/sizeof(mmHDP_XDP_D2H_RSVD_22[0]), 0, 0 },
	{ "mmHDP_XDP_D2H_RSVD_23", REG_MMIO, 0xc17, &mmHDP_XDP_D2H_RSVD_23[0], sizeof(mmHDP_XDP_D2H_RSVD_23)/sizeof(mmHDP_XDP_D2H_RSVD_23[0]), 0, 0 },
	{ "mmHDP_XDP_D2H_RSVD_24", REG_MMIO, 0xc18, &mmHDP_XDP_D2H_RSVD_24[0], sizeof(mmHDP_XDP_D2H_RSVD_24)/sizeof(mmHDP_XDP_D2H_RSVD_24[0]), 0, 0 },
	{ "mmHDP_XDP_D2H_RSVD_25", REG_MMIO, 0xc19, &mmHDP_XDP_D2H_RSVD_25[0], sizeof(mmHDP_XDP_D2H_RSVD_25)/sizeof(mmHDP_XDP_D2H_RSVD_25[0]), 0, 0 },
	{ "mmHDP_XDP_D2H_RSVD_26", REG_MMIO, 0xc1a, &mmHDP_XDP_D2H_RSVD_26[0], sizeof(mmHDP_XDP_D2H_RSVD_26)/sizeof(mmHDP_XDP_D2H_RSVD_26[0]), 0, 0 },
	{ "mmHDP_XDP_D2H_RSVD_27", REG_MMIO, 0xc1b, &mmHDP_XDP_D2H_RSVD_27[0], sizeof(mmHDP_XDP_D2H_RSVD_27)/sizeof(mmHDP_XDP_D2H_RSVD_27[0]), 0, 0 },
	{ "mmHDP_XDP_D2H_RSVD_28", REG_MMIO, 0xc1c, &mmHDP_XDP_D2H_RSVD_28[0], sizeof(mmHDP_XDP_D2H_RSVD_28)/sizeof(mmHDP_XDP_D2H_RSVD_28[0]), 0, 0 },
	{ "mmHDP_XDP_D2H_RSVD_29", REG_MMIO, 0xc1d, &mmHDP_XDP_D2H_RSVD_29[0], sizeof(mmHDP_XDP_D2H_RSVD_29)/sizeof(mmHDP_XDP_D2H_RSVD_29[0]), 0, 0 },
	{ "mmHDP_XDP_D2H_RSVD_30", REG_MMIO, 0xc1e, &mmHDP_XDP_D2H_RSVD_30[0], sizeof(mmHDP_XDP_D2H_RSVD_30)/sizeof(mmHDP_XDP_D2H_RSVD_30[0]), 0, 0 },
	{ "mmHDP_XDP_D2H_RSVD_31", REG_MMIO, 0xc1f, &mmHDP_XDP_D2H_RSVD_31[0], sizeof(mmHDP_XDP_D2H_RSVD_31)/sizeof(mmHDP_XDP_D2H_RSVD_31[0]), 0, 0 },
	{ "mmHDP_XDP_D2H_RSVD_32", REG_MMIO, 0xc20, &mmHDP_XDP_D2H_RSVD_32[0], sizeof(mmHDP_XDP_D2H_RSVD_32)/sizeof(mmHDP_XDP_D2H_RSVD_32[0]), 0, 0 },
	{ "mmHDP_XDP_D2H_RSVD_33", REG_MMIO, 0xc21, &mmHDP_XDP_D2H_RSVD_33[0], sizeof(mmHDP_XDP_D2H_RSVD_33)/sizeof(mmHDP_XDP_D2H_RSVD_33[0]), 0, 0 },
	{ "mmHDP_XDP_D2H_RSVD_34", REG_MMIO, 0xc22, &mmHDP_XDP_D2H_RSVD_34[0], sizeof(mmHDP_XDP_D2H_RSVD_34)/sizeof(mmHDP_XDP_D2H_RSVD_34[0]), 0, 0 },
	{ "mmHDP_XDP_DIRECT2HDP_LAST", REG_MMIO, 0xc23, &mmHDP_XDP_DIRECT2HDP_LAST[0], sizeof(mmHDP_XDP_DIRECT2HDP_LAST)/sizeof(mmHDP_XDP_DIRECT2HDP_LAST[0]), 0, 0 },
	{ "mmHDP_XDP_P2P_BAR_CFG", REG_MMIO, 0xc24, &mmHDP_XDP_P2P_BAR_CFG[0], sizeof(mmHDP_XDP_P2P_BAR_CFG)/sizeof(mmHDP_XDP_P2P_BAR_CFG[0]), 0, 0 },
	{ "mmHDP_XDP_P2P_MBX_OFFSET", REG_MMIO, 0xc25, &mmHDP_XDP_P2P_MBX_OFFSET[0], sizeof(mmHDP_XDP_P2P_MBX_OFFSET)/sizeof(mmHDP_XDP_P2P_MBX_OFFSET[0]), 0, 0 },
	{ "mmHDP_XDP_P2P_MBX_ADDR0", REG_MMIO, 0xc26, &mmHDP_XDP_P2P_MBX_ADDR0[0], sizeof(mmHDP_XDP_P2P_MBX_ADDR0)/sizeof(mmHDP_XDP_P2P_MBX_ADDR0[0]), 0, 0 },
	{ "mmHDP_XDP_P2P_MBX_ADDR1", REG_MMIO, 0xc27, &mmHDP_XDP_P2P_MBX_ADDR1[0], sizeof(mmHDP_XDP_P2P_MBX_ADDR1)/sizeof(mmHDP_XDP_P2P_MBX_ADDR1[0]), 0, 0 },
	{ "mmHDP_XDP_P2P_MBX_ADDR2", REG_MMIO, 0xc28, &mmHDP_XDP_P2P_MBX_ADDR2[0], sizeof(mmHDP_XDP_P2P_MBX_ADDR2)/sizeof(mmHDP_XDP_P2P_MBX_ADDR2[0]), 0, 0 },
	{ "mmHDP_XDP_P2P_MBX_ADDR3", REG_MMIO, 0xc29, &mmHDP_XDP_P2P_MBX_ADDR3[0], sizeof(mmHDP_XDP_P2P_MBX_ADDR3)/sizeof(mmHDP_XDP_P2P_MBX_ADDR3[0]), 0, 0 },
	{ "mmHDP_XDP_P2P_MBX_ADDR4", REG_MMIO, 0xc2a, &mmHDP_XDP_P2P_MBX_ADDR4[0], sizeof(mmHDP_XDP_P2P_MBX_ADDR4)/sizeof(mmHDP_XDP_P2P_MBX_ADDR4[0]), 0, 0 },
	{ "mmHDP_XDP_P2P_MBX_ADDR5", REG_MMIO, 0xc2b, &mmHDP_XDP_P2P_MBX_ADDR5[0], sizeof(mmHDP_XDP_P2P_MBX_ADDR5)/sizeof(mmHDP_XDP_P2P_MBX_ADDR5[0]), 0, 0 },
	{ "mmHDP_XDP_P2P_MBX_ADDR6", REG_MMIO, 0xc2c, &mmHDP_XDP_P2P_MBX_ADDR6[0], sizeof(mmHDP_XDP_P2P_MBX_ADDR6)/sizeof(mmHDP_XDP_P2P_MBX_ADDR6[0]), 0, 0 },
	{ "mmHDP_XDP_HDP_MBX_MC_CFG", REG_MMIO, 0xc2d, &mmHDP_XDP_HDP_MBX_MC_CFG[0], sizeof(mmHDP_XDP_HDP_MBX_MC_CFG)/sizeof(mmHDP_XDP_HDP_MBX_MC_CFG[0]), 0, 0 },
	{ "mmHDP_XDP_HDP_MC_CFG", REG_MMIO, 0xc2e, &mmHDP_XDP_HDP_MC_CFG[0], sizeof(mmHDP_XDP_HDP_MC_CFG)/sizeof(mmHDP_XDP_HDP_MC_CFG[0]), 0, 0 },
	{ "mmHDP_XDP_HST_CFG", REG_MMIO, 0xc2f, &mmHDP_XDP_HST_CFG[0], sizeof(mmHDP_XDP_HST_CFG)/sizeof(mmHDP_XDP_HST_CFG[0]), 0, 0 },
	{ "mmHDP_XDP_SID_CFG", REG_MMIO, 0xc30, &mmHDP_XDP_SID_CFG[0], sizeof(mmHDP_XDP_SID_CFG)/sizeof(mmHDP_XDP_SID_CFG[0]), 0, 0 },
	{ "mmHDP_XDP_HDP_IPH_CFG", REG_MMIO, 0xc31, &mmHDP_XDP_HDP_IPH_CFG[0], sizeof(mmHDP_XDP_HDP_IPH_CFG)/sizeof(mmHDP_XDP_HDP_IPH_CFG[0]), 0, 0 },
	{ "mmHDP_XDP_SRBM_CFG", REG_MMIO, 0xc32, &mmHDP_XDP_SRBM_CFG[0], sizeof(mmHDP_XDP_SRBM_CFG)/sizeof(mmHDP_XDP_SRBM_CFG[0]), 0, 0 },
	{ "mmHDP_XDP_CGTT_BLK_CTRL", REG_MMIO, 0xc33, &mmHDP_XDP_CGTT_BLK_CTRL[0], sizeof(mmHDP_XDP_CGTT_BLK_CTRL)/sizeof(mmHDP_XDP_CGTT_BLK_CTRL[0]), 0, 0 },
	{ "mmHDP_XDP_P2P_BAR0", REG_MMIO, 0xc34, &mmHDP_XDP_P2P_BAR0[0], sizeof(mmHDP_XDP_P2P_BAR0)/sizeof(mmHDP_XDP_P2P_BAR0[0]), 0, 0 },
	{ "mmHDP_XDP_P2P_BAR1", REG_MMIO, 0xc35, &mmHDP_XDP_P2P_BAR1[0], sizeof(mmHDP_XDP_P2P_BAR1)/sizeof(mmHDP_XDP_P2P_BAR1[0]), 0, 0 },
	{ "mmHDP_XDP_P2P_BAR2", REG_MMIO, 0xc36, &mmHDP_XDP_P2P_BAR2[0], sizeof(mmHDP_XDP_P2P_BAR2)/sizeof(mmHDP_XDP_P2P_BAR2[0]), 0, 0 },
	{ "mmHDP_XDP_P2P_BAR3", REG_MMIO, 0xc37, &mmHDP_XDP_P2P_BAR3[0], sizeof(mmHDP_XDP_P2P_BAR3)/sizeof(mmHDP_XDP_P2P_BAR3[0]), 0, 0 },
	{ "mmHDP_XDP_P2P_BAR4", REG_MMIO, 0xc38, &mmHDP_XDP_P2P_BAR4[0], sizeof(mmHDP_XDP_P2P_BAR4)/sizeof(mmHDP_XDP_P2P_BAR4[0]), 0, 0 },
	{ "mmHDP_XDP_P2P_BAR5", REG_MMIO, 0xc39, &mmHDP_XDP_P2P_BAR5[0], sizeof(mmHDP_XDP_P2P_BAR5)/sizeof(mmHDP_XDP_P2P_BAR5[0]), 0, 0 },
	{ "mmHDP_XDP_P2P_BAR6", REG_MMIO, 0xc3a, &mmHDP_XDP_P2P_BAR6[0], sizeof(mmHDP_XDP_P2P_BAR6)/sizeof(mmHDP_XDP_P2P_BAR6[0]), 0, 0 },
	{ "mmHDP_XDP_P2P_BAR7", REG_MMIO, 0xc3b, &mmHDP_XDP_P2P_BAR7[0], sizeof(mmHDP_XDP_P2P_BAR7)/sizeof(mmHDP_XDP_P2P_BAR7[0]), 0, 0 },
	{ "mmHDP_XDP_FLUSH_ARMED_STS", REG_MMIO, 0xc3c, &mmHDP_XDP_FLUSH_ARMED_STS[0], sizeof(mmHDP_XDP_FLUSH_ARMED_STS)/sizeof(mmHDP_XDP_FLUSH_ARMED_STS[0]), 0, 0 },
	{ "mmHDP_XDP_FLUSH_CNTR0_STS", REG_MMIO, 0xc3d, &mmHDP_XDP_FLUSH_CNTR0_STS[0], sizeof(mmHDP_XDP_FLUSH_CNTR0_STS)/sizeof(mmHDP_XDP_FLUSH_CNTR0_STS[0]), 0, 0 },
	{ "mmHDP_XDP_BUSY_STS", REG_MMIO, 0xc3e, &mmHDP_XDP_BUSY_STS[0], sizeof(mmHDP_XDP_BUSY_STS)/sizeof(mmHDP_XDP_BUSY_STS[0]), 0, 0 },
	{ "mmHDP_XDP_STICKY", REG_MMIO, 0xc3f, &mmHDP_XDP_STICKY[0], sizeof(mmHDP_XDP_STICKY)/sizeof(mmHDP_XDP_STICKY[0]), 0, 0 },
	{ "mmHDP_XDP_CHKN", REG_MMIO, 0xc40, &mmHDP_XDP_CHKN[0], sizeof(mmHDP_XDP_CHKN)/sizeof(mmHDP_XDP_CHKN[0]), 0, 0 },
	{ "mmHDP_XDP_DBG_ADDR", REG_MMIO, 0xc41, &mmHDP_XDP_DBG_ADDR[0], sizeof(mmHDP_XDP_DBG_ADDR)/sizeof(mmHDP_XDP_DBG_ADDR[0]), 0, 0 },
	{ "mmHDP_XDP_DBG_DATA", REG_MMIO, 0xc42, &mmHDP_XDP_DBG_DATA[0], sizeof(mmHDP_XDP_DBG_DATA)/sizeof(mmHDP_XDP_DBG_DATA[0]), 0, 0 },
	{ "mmHDP_XDP_DBG_MASK", REG_MMIO, 0xc43, &mmHDP_XDP_DBG_MASK[0], sizeof(mmHDP_XDP_DBG_MASK)/sizeof(mmHDP_XDP_DBG_MASK[0]), 0, 0 },
	{ "mmHDP_XDP_BARS_ADDR_39_36", REG_MMIO, 0xc44, &mmHDP_XDP_BARS_ADDR_39_36[0], sizeof(mmHDP_XDP_BARS_ADDR_39_36)/sizeof(mmHDP_XDP_BARS_ADDR_39_36[0]), 0, 0 },
	{ "mmIH_VMID_0_LUT", REG_MMIO, 0xf50, &mmIH_VMID_0_LUT[0], sizeof(mmIH_VMID_0_LUT)/sizeof(mmIH_VMID_0_LUT[0]), 0, 0 },
	{ "mmIH_VMID_1_LUT", REG_MMIO, 0xf51, &mmIH_VMID_1_LUT[0], sizeof(mmIH_VMID_1_LUT)/sizeof(mmIH_VMID_1_LUT[0]), 0, 0 },
	{ "mmIH_VMID_2_LUT", REG_MMIO, 0xf52, &mmIH_VMID_2_LUT[0], sizeof(mmIH_VMID_2_LUT)/sizeof(mmIH_VMID_2_LUT[0]), 0, 0 },
	{ "mmIH_VMID_3_LUT", REG_MMIO, 0xf53, &mmIH_VMID_3_LUT[0], sizeof(mmIH_VMID_3_LUT)/sizeof(mmIH_VMID_3_LUT[0]), 0, 0 },
	{ "mmIH_VMID_4_LUT", REG_MMIO, 0xf54, &mmIH_VMID_4_LUT[0], sizeof(mmIH_VMID_4_LUT)/sizeof(mmIH_VMID_4_LUT[0]), 0, 0 },
	{ "mmIH_VMID_5_LUT", REG_MMIO, 0xf55, &mmIH_VMID_5_LUT[0], sizeof(mmIH_VMID_5_LUT)/sizeof(mmIH_VMID_5_LUT[0]), 0, 0 },
	{ "mmIH_VMID_6_LUT", REG_MMIO, 0xf56, &mmIH_VMID_6_LUT[0], sizeof(mmIH_VMID_6_LUT)/sizeof(mmIH_VMID_6_LUT[0]), 0, 0 },
	{ "mmIH_VMID_7_LUT", REG_MMIO, 0xf57, &mmIH_VMID_7_LUT[0], sizeof(mmIH_VMID_7_LUT)/sizeof(mmIH_VMID_7_LUT[0]), 0, 0 },
	{ "mmIH_VMID_8_LUT", REG_MMIO, 0xf58, &mmIH_VMID_8_LUT[0], sizeof(mmIH_VMID_8_LUT)/sizeof(mmIH_VMID_8_LUT[0]), 0, 0 },
	{ "mmIH_VMID_9_LUT", REG_MMIO, 0xf59, &mmIH_VMID_9_LUT[0], sizeof(mmIH_VMID_9_LUT)/sizeof(mmIH_VMID_9_LUT[0]), 0, 0 },
	{ "mmIH_VMID_10_LUT", REG_MMIO, 0xf5a, &mmIH_VMID_10_LUT[0], sizeof(mmIH_VMID_10_LUT)/sizeof(mmIH_VMID_10_LUT[0]), 0, 0 },
	{ "mmIH_VMID_11_LUT", REG_MMIO, 0xf5b, &mmIH_VMID_11_LUT[0], sizeof(mmIH_VMID_11_LUT)/sizeof(mmIH_VMID_11_LUT[0]), 0, 0 },
	{ "mmIH_VMID_12_LUT", REG_MMIO, 0xf5c, &mmIH_VMID_12_LUT[0], sizeof(mmIH_VMID_12_LUT)/sizeof(mmIH_VMID_12_LUT[0]), 0, 0 },
	{ "mmIH_VMID_13_LUT", REG_MMIO, 0xf5d, &mmIH_VMID_13_LUT[0], sizeof(mmIH_VMID_13_LUT)/sizeof(mmIH_VMID_13_LUT[0]), 0, 0 },
	{ "mmIH_VMID_14_LUT", REG_MMIO, 0xf5e, &mmIH_VMID_14_LUT[0], sizeof(mmIH_VMID_14_LUT)/sizeof(mmIH_VMID_14_LUT[0]), 0, 0 },
	{ "mmIH_VMID_15_LUT", REG_MMIO, 0xf5f, &mmIH_VMID_15_LUT[0], sizeof(mmIH_VMID_15_LUT)/sizeof(mmIH_VMID_15_LUT[0]), 0, 0 },
	{ "mmIH_RB_CNTL", REG_MMIO, 0xf80, &mmIH_RB_CNTL[0], sizeof(mmIH_RB_CNTL)/sizeof(mmIH_RB_CNTL[0]), 0, 0 },
	{ "mmIH_RB_BASE", REG_MMIO, 0xf81, &mmIH_RB_BASE[0], sizeof(mmIH_RB_BASE)/sizeof(mmIH_RB_BASE[0]), 0, 0 },
	{ "mmIH_RB_RPTR", REG_MMIO, 0xf82, &mmIH_RB_RPTR[0], sizeof(mmIH_RB_RPTR)/sizeof(mmIH_RB_RPTR[0]), 0, 0 },
	{ "mmIH_RB_WPTR", REG_MMIO, 0xf83, &mmIH_RB_WPTR[0], sizeof(mmIH_RB_WPTR)/sizeof(mmIH_RB_WPTR[0]), 0, 0 },
	{ "mmIH_RB_WPTR_ADDR_HI", REG_MMIO, 0xf84, &mmIH_RB_WPTR_ADDR_HI[0], sizeof(mmIH_RB_WPTR_ADDR_HI)/sizeof(mmIH_RB_WPTR_ADDR_HI[0]), 0, 0 },
	{ "mmIH_RB_WPTR_ADDR_LO", REG_MMIO, 0xf85, &mmIH_RB_WPTR_ADDR_LO[0], sizeof(mmIH_RB_WPTR_ADDR_LO)/sizeof(mmIH_RB_WPTR_ADDR_LO[0]), 0, 0 },
	{ "mmIH_CNTL", REG_MMIO, 0xf86, &mmIH_CNTL[0], sizeof(mmIH_CNTL)/sizeof(mmIH_CNTL[0]), 0, 0 },
	{ "mmIH_LEVEL_STATUS", REG_MMIO, 0xf87, &mmIH_LEVEL_STATUS[0], sizeof(mmIH_LEVEL_STATUS)/sizeof(mmIH_LEVEL_STATUS[0]), 0, 0 },
	{ "mmIH_STATUS", REG_MMIO, 0xf88, &mmIH_STATUS[0], sizeof(mmIH_STATUS)/sizeof(mmIH_STATUS[0]), 0, 0 },
	{ "mmIH_PERFMON_CNTL", REG_MMIO, 0xf89, &mmIH_PERFMON_CNTL[0], sizeof(mmIH_PERFMON_CNTL)/sizeof(mmIH_PERFMON_CNTL[0]), 0, 0 },
	{ "mmIH_PERFCOUNTER0_RESULT", REG_MMIO, 0xf8a, &mmIH_PERFCOUNTER0_RESULT[0], sizeof(mmIH_PERFCOUNTER0_RESULT)/sizeof(mmIH_PERFCOUNTER0_RESULT[0]), 0, 0 },
	{ "mmIH_PERFCOUNTER1_RESULT", REG_MMIO, 0xf8b, &mmIH_PERFCOUNTER1_RESULT[0], sizeof(mmIH_PERFCOUNTER1_RESULT)/sizeof(mmIH_PERFCOUNTER1_RESULT[0]), 0, 0 },
	{ "mmIH_ADVFAULT_CNTL", REG_MMIO, 0xf8c, &mmIH_ADVFAULT_CNTL[0], sizeof(mmIH_ADVFAULT_CNTL)/sizeof(mmIH_ADVFAULT_CNTL[0]), 0, 0 },
	{ "mmSEM_MCIF_CONFIG", REG_MMIO, 0xf90, &mmSEM_MCIF_CONFIG[0], sizeof(mmSEM_MCIF_CONFIG)/sizeof(mmSEM_MCIF_CONFIG[0]), 0, 0 },
	{ "mmSDMA_CONFIG", REG_MMIO, 0xf91, &mmSDMA_CONFIG[0], sizeof(mmSDMA_CONFIG)/sizeof(mmSDMA_CONFIG[0]), 0, 0 },
	{ "mmSDMA1_CONFIG", REG_MMIO, 0xf92, &mmSDMA1_CONFIG[0], sizeof(mmSDMA1_CONFIG)/sizeof(mmSDMA1_CONFIG[0]), 0, 0 },
	{ "mmUVD_CONFIG", REG_MMIO, 0xf93, &mmUVD_CONFIG[0], sizeof(mmUVD_CONFIG)/sizeof(mmUVD_CONFIG[0]), 0, 0 },
	{ "mmVCE_CONFIG", REG_MMIO, 0xf94, &mmVCE_CONFIG[0], sizeof(mmVCE_CONFIG)/sizeof(mmVCE_CONFIG[0]), 0, 0 },
	{ "mmACP_CONFIG", REG_MMIO, 0xf95, &mmACP_CONFIG[0], sizeof(mmACP_CONFIG)/sizeof(mmACP_CONFIG[0]), 0, 0 },
	{ "mmCPG_CONFIG", REG_MMIO, 0xf96, &mmCPG_CONFIG[0], sizeof(mmCPG_CONFIG)/sizeof(mmCPG_CONFIG[0]), 0, 0 },
	{ "mmCPC1_CONFIG", REG_MMIO, 0xf97, &mmCPC1_CONFIG[0], sizeof(mmCPC1_CONFIG)/sizeof(mmCPC1_CONFIG[0]), 0, 0 },
	{ "mmCPC2_CONFIG", REG_MMIO, 0xf98, &mmCPC2_CONFIG[0], sizeof(mmCPC2_CONFIG)/sizeof(mmCPC2_CONFIG[0]), 0, 0 },
	{ "mmSEM_STATUS", REG_MMIO, 0xf99, &mmSEM_STATUS[0], sizeof(mmSEM_STATUS)/sizeof(mmSEM_STATUS[0]), 0, 0 },
	{ "mmSEM_EDC_CONFIG", REG_MMIO, 0xf9a, &mmSEM_EDC_CONFIG[0], sizeof(mmSEM_EDC_CONFIG)/sizeof(mmSEM_EDC_CONFIG[0]), 0, 0 },
	{ "mmSEM_MAILBOX_CLIENTCONFIG", REG_MMIO, 0xf9b, &mmSEM_MAILBOX_CLIENTCONFIG[0], sizeof(mmSEM_MAILBOX_CLIENTCONFIG)/sizeof(mmSEM_MAILBOX_CLIENTCONFIG[0]), 0, 0 },
	{ "mmSEM_MAILBOX", REG_MMIO, 0xf9c, &mmSEM_MAILBOX[0], sizeof(mmSEM_MAILBOX)/sizeof(mmSEM_MAILBOX[0]), 0, 0 },
	{ "mmSEM_MAILBOX_CONTROL", REG_MMIO, 0xf9d, &mmSEM_MAILBOX_CONTROL[0], sizeof(mmSEM_MAILBOX_CONTROL)/sizeof(mmSEM_MAILBOX_CONTROL[0]), 0, 0 },
	{ "mmSEM_CHICKEN_BITS", REG_MMIO, 0xf9e, &mmSEM_CHICKEN_BITS[0], sizeof(mmSEM_CHICKEN_BITS)/sizeof(mmSEM_CHICKEN_BITS[0]), 0, 0 },