static struct umr_bitfield mmIH_VMID_0_LUT[] = {
	 { "PASID", 0, 15, &umr_bitfield_default },
};
static struct umr_bitfield mmIH_VMID_1_LUT[] = {
	 { "PASID", 0, 15, &umr_bitfield_default },
};
static struct umr_bitfield mmIH_VMID_2_LUT[] = {
	 { "PASID", 0, 15, &umr_bitfield_default },
};
static struct umr_bitfield mmIH_VMID_3_LUT[] = {
	 { "PASID", 0, 15, &umr_bitfield_default },
};
static struct umr_bitfield mmIH_VMID_4_LUT[] = {
	 { "PASID", 0, 15, &umr_bitfield_default },
};
static struct umr_bitfield mmIH_VMID_5_LUT[] = {
	 { "PASID", 0, 15, &umr_bitfield_default },
};
static struct umr_bitfield mmIH_VMID_6_LUT[] = {
	 { "PASID", 0, 15, &umr_bitfield_default },
};
static struct umr_bitfield mmIH_VMID_7_LUT[] = {
	 { "PASID", 0, 15, &umr_bitfield_default },
};
static struct umr_bitfield mmIH_VMID_8_LUT[] = {
	 { "PASID", 0, 15, &umr_bitfield_default },
};
static struct umr_bitfield mmIH_VMID_9_LUT[] = {
	 { "PASID", 0, 15, &umr_bitfield_default },
};
static struct umr_bitfield mmIH_VMID_10_LUT[] = {
	 { "PASID", 0, 15, &umr_bitfield_default },
};
static struct umr_bitfield mmIH_VMID_11_LUT[] = {
	 { "PASID", 0, 15, &umr_bitfield_default },
};
static struct umr_bitfield mmIH_VMID_12_LUT[] = {
	 { "PASID", 0, 15, &umr_bitfield_default },
};
static struct umr_bitfield mmIH_VMID_13_LUT[] = {
	 { "PASID", 0, 15, &umr_bitfield_default },
};
static struct umr_bitfield mmIH_VMID_14_LUT[] = {
	 { "PASID", 0, 15, &umr_bitfield_default },
};
static struct umr_bitfield mmIH_VMID_15_LUT[] = {
	 { "PASID", 0, 15, &umr_bitfield_default },
};
static struct umr_bitfield mmIH_VMID_0_LUT_MM[] = {
	 { "PASID", 0, 15, &umr_bitfield_default },
};
static struct umr_bitfield mmIH_VMID_1_LUT_MM[] = {
	 { "PASID", 0, 15, &umr_bitfield_default },
};
static struct umr_bitfield mmIH_VMID_2_LUT_MM[] = {
	 { "PASID", 0, 15, &umr_bitfield_default },
};
static struct umr_bitfield mmIH_VMID_3_LUT_MM[] = {
	 { "PASID", 0, 15, &umr_bitfield_default },
};
static struct umr_bitfield mmIH_VMID_4_LUT_MM[] = {
	 { "PASID", 0, 15, &umr_bitfield_default },
};
static struct umr_bitfield mmIH_VMID_5_LUT_MM[] = {
	 { "PASID", 0, 15, &umr_bitfield_default },
};
static struct umr_bitfield mmIH_VMID_6_LUT_MM[] = {
	 { "PASID", 0, 15, &umr_bitfield_default },
};
static struct umr_bitfield mmIH_VMID_7_LUT_MM[] = {
	 { "PASID", 0, 15, &umr_bitfield_default },
};
static struct umr_bitfield mmIH_VMID_8_LUT_MM[] = {
	 { "PASID", 0, 15, &umr_bitfield_default },
};
static struct umr_bitfield mmIH_VMID_9_LUT_MM[] = {
	 { "PASID", 0, 15, &umr_bitfield_default },
};
static struct umr_bitfield mmIH_VMID_10_LUT_MM[] = {
	 { "PASID", 0, 15, &umr_bitfield_default },
};
static struct umr_bitfield mmIH_VMID_11_LUT_MM[] = {
	 { "PASID", 0, 15, &umr_bitfield_default },
};
static struct umr_bitfield mmIH_VMID_12_LUT_MM[] = {
	 { "PASID", 0, 15, &umr_bitfield_default },
};
static struct umr_bitfield mmIH_VMID_13_LUT_MM[] = {
	 { "PASID", 0, 15, &umr_bitfield_default },
};
static struct umr_bitfield mmIH_VMID_14_LUT_MM[] = {
	 { "PASID", 0, 15, &umr_bitfield_default },
};
static struct umr_bitfield mmIH_VMID_15_LUT_MM[] = {
	 { "PASID", 0, 15, &umr_bitfield_default },
};
static struct umr_bitfield mmIH_COOKIE_0[] = {
	 { "CLIENT_ID", 0, 7, &umr_bitfield_default },
	 { "SOURCE_ID", 8, 15, &umr_bitfield_default },
	 { "RING_ID", 16, 23, &umr_bitfield_default },
	 { "VM_ID", 24, 27, &umr_bitfield_default },
	 { "RESERVED", 28, 30, &umr_bitfield_default },
	 { "VMID_TYPE", 31, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmIH_COOKIE_1[] = {
	 { "TIMESTAMP_31_0", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmIH_COOKIE_2[] = {
	 { "TIMESTAMP_47_32", 0, 15, &umr_bitfield_default },
	 { "RESERVED", 16, 30, &umr_bitfield_default },
	 { "TIMESTAMP_SRC", 31, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmIH_COOKIE_3[] = {
	 { "PAS_ID", 0, 15, &umr_bitfield_default },
	 { "RESERVED", 16, 30, &umr_bitfield_default },
	 { "PASID_SRC", 31, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmIH_COOKIE_4[] = {
	 { "CONTEXT_ID_31_0", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmIH_COOKIE_5[] = {
	 { "CONTEXT_ID_63_32", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmIH_COOKIE_6[] = {
	 { "CONTEXT_ID_95_64", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmIH_COOKIE_7[] = {
	 { "CONTEXT_ID_128_96", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmIH_REGISTER_LAST_PART0[] = {
	 { "RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSEM_REQ_INPUT_0[] = {
	 { "DATA", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSEM_REQ_INPUT_1[] = {
	 { "DATA", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSEM_REQ_INPUT_2[] = {
	 { "DATA", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSEM_REQ_INPUT_3[] = {
	 { "DATA", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSEM_REGISTER_LAST_PART0[] = {
	 { "RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmIH_RB_CNTL[] = {
	 { "RB_ENABLE", 0, 0, &umr_bitfield_default },
	 { "RB_SIZE", 1, 5, &umr_bitfield_default },
	 { "RB_GPU_TS_ENABLE", 7, 7, &umr_bitfield_default },
	 { "WPTR_WRITEBACK_ENABLE", 8, 8, &umr_bitfield_default },
	 { "RB_FULL_DRAIN_ENABLE", 9, 9, &umr_bitfield_default },
	 { "FULL_DRAIN_CLEAR", 10, 10, &umr_bitfield_default },
	 { "RB_USED_INT_THRESHOLD", 12, 15, &umr_bitfield_default },
	 { "WPTR_OVERFLOW_ENABLE", 16, 16, &umr_bitfield_default },
	 { "ENABLE_INTR", 17, 17, &umr_bitfield_default },
	 { "MC_SWAP", 18, 19, &umr_bitfield_default },
	 { "MC_SNOOP", 20, 20, &umr_bitfield_default },
	 { "RPTR_REARM", 21, 21, &umr_bitfield_default },
	 { "MC_RO", 22, 22, &umr_bitfield_default },
	 { "MC_VMID", 24, 27, &umr_bitfield_default },
	 { "MC_SPACE", 28, 30, &umr_bitfield_default },
	 { "WPTR_OVERFLOW_CLEAR", 31, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmIH_RB_BASE[] = {
	 { "ADDR", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmIH_RB_BASE_HI[] = {
	 { "ADDR", 0, 7, &umr_bitfield_default },
};
static struct umr_bitfield mmIH_RB_RPTR[] = {
	 { "OFFSET", 2, 17, &umr_bitfield_default },
};
static struct umr_bitfield mmIH_RB_WPTR[] = {
	 { "RB_OVERFLOW", 0, 0, &umr_bitfield_default },
	 { "OFFSET", 2, 17, &umr_bitfield_default },
	 { "RB_LEFT_NONE", 18, 18, &umr_bitfield_default },
	 { "RB_MAY_OVERFLOW", 19, 19, &umr_bitfield_default },
};
static struct umr_bitfield mmIH_RB_WPTR_ADDR_HI[] = {
	 { "ADDR", 0, 15, &umr_bitfield_default },
};
static struct umr_bitfield mmIH_RB_WPTR_ADDR_LO[] = {
	 { "ADDR", 2, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmIH_DOORBELL_RPTR[] = {
	 { "OFFSET", 0, 25, &umr_bitfield_default },
	 { "ENABLE", 28, 28, &umr_bitfield_default },
};
static struct umr_bitfield mmIH_RB_CNTL_RING1[] = {
	 { "RB_ENABLE", 0, 0, &umr_bitfield_default },
	 { "RB_SIZE", 1, 5, &umr_bitfield_default },
	 { "RB_GPU_TS_ENABLE", 7, 7, &umr_bitfield_default },
	 { "RB_FULL_DRAIN_ENABLE", 9, 9, &umr_bitfield_default },
	 { "FULL_DRAIN_CLEAR", 10, 10, &umr_bitfield_default },
	 { "RB_USED_INT_THRESHOLD", 12, 15, &umr_bitfield_default },
	 { "WPTR_OVERFLOW_ENABLE", 16, 16, &umr_bitfield_default },
	 { "MC_SWAP", 18, 19, &umr_bitfield_default },
	 { "MC_SNOOP", 20, 20, &umr_bitfield_default },
	 { "MC_RO", 22, 22, &umr_bitfield_default },
	 { "MC_VMID", 24, 27, &umr_bitfield_default },
	 { "MC_SPACE", 28, 30, &umr_bitfield_default },
	 { "WPTR_OVERFLOW_CLEAR", 31, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmIH_RB_BASE_RING1[] = {
	 { "ADDR", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmIH_RB_BASE_HI_RING1[] = {
	 { "ADDR", 0, 7, &umr_bitfield_default },
};
static struct umr_bitfield mmIH_RB_RPTR_RING1[] = {
	 { "OFFSET", 2, 17, &umr_bitfield_default },
};
static struct umr_bitfield mmIH_RB_WPTR_RING1[] = {
	 { "RB_OVERFLOW", 0, 0, &umr_bitfield_default },
	 { "OFFSET", 2, 17, &umr_bitfield_default },
	 { "RB_LEFT_NONE", 18, 18, &umr_bitfield_default },
	 { "RB_MAY_OVERFLOW", 19, 19, &umr_bitfield_default },
};
static struct umr_bitfield mmIH_DOORBELL_RPTR_RING1[] = {
	 { "OFFSET", 0, 25, &umr_bitfield_default },
	 { "ENABLE", 28, 28, &umr_bitfield_default },
};
static struct umr_bitfield mmIH_RB_CNTL_RING2[] = {
	 { "RB_ENABLE", 0, 0, &umr_bitfield_default },
	 { "RB_SIZE", 1, 5, &umr_bitfield_default },
	 { "RB_GPU_TS_ENABLE", 7, 7, &umr_bitfield_default },
	 { "RB_FULL_DRAIN_ENABLE", 9, 9, &umr_bitfield_default },
	 { "FULL_DRAIN_CLEAR", 10, 10, &umr_bitfield_default },
	 { "RB_USED_INT_THRESHOLD", 12, 15, &umr_bitfield_default },
	 { "WPTR_OVERFLOW_ENABLE", 16, 16, &umr_bitfield_default },
	 { "MC_SWAP", 18, 19, &umr_bitfield_default },
	 { "MC_SNOOP", 20, 20, &umr_bitfield_default },
	 { "MC_RO", 22, 22, &umr_bitfield_default },
	 { "MC_VMID", 24, 27, &umr_bitfield_default },
	 { "MC_SPACE", 28, 30, &umr_bitfield_default },
	 { "WPTR_OVERFLOW_CLEAR", 31, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmIH_RB_BASE_RING2[] = {
	 { "ADDR", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmIH_RB_BASE_HI_RING2[] = {
	 { "ADDR", 0, 7, &umr_bitfield_default },
};
static struct umr_bitfield mmIH_RB_RPTR_RING2[] = {
	 { "OFFSET", 2, 17, &umr_bitfield_default },
};
static struct umr_bitfield mmIH_RB_WPTR_RING2[] = {
	 { "RB_OVERFLOW", 0, 0, &umr_bitfield_default },
	 { "OFFSET", 2, 17, &umr_bitfield_default },
	 { "RB_LEFT_NONE", 18, 18, &umr_bitfield_default },
	 { "RB_MAY_OVERFLOW", 19, 19, &umr_bitfield_default },
};
static struct umr_bitfield mmIH_DOORBELL_RPTR_RING2[] = {
	 { "OFFSET", 0, 25, &umr_bitfield_default },
	 { "ENABLE", 28, 28, &umr_bitfield_default },
};
static struct umr_bitfield mmIH_VERSION[] = {
	 { "MINVER", 0, 6, &umr_bitfield_default },
	 { "MAJVER", 8, 14, &umr_bitfield_default },
	 { "REV", 16, 21, &umr_bitfield_default },
};
static struct umr_bitfield mmIH_CNTL[] = {
	 { "WPTR_WRITEBACK_TIMER", 0, 4, &umr_bitfield_default },
	 { "IH_IDLE_HYSTERESIS_CNTL", 6, 7, &umr_bitfield_default },
	 { "IH_FIFO_HIGHWATER", 8, 14, &umr_bitfield_default },
	 { "MC_WR_CLEAN_CNT", 20, 24, &umr_bitfield_default },
};
static struct umr_bitfield mmIH_CNTL2[] = {
	 { "SELF_IV_FORCE_WPTR_UPDATE_TIMEOUT", 0, 7, &umr_bitfield_default },
	 { "SELF_IV_FORCE_WPTR_UPDATE_ENABLE", 8, 8, &umr_bitfield_default },
};
static struct umr_bitfield mmIH_STATUS[] = {
	 { "IDLE", 0, 0, &umr_bitfield_default },
	 { "INPUT_IDLE", 1, 1, &umr_bitfield_default },
	 { "BUFFER_IDLE", 2, 2, &umr_bitfield_default },
	 { "RB_FULL", 3, 3, &umr_bitfield_default },
	 { "RB_FULL_DRAIN", 4, 4, &umr_bitfield_default },
	 { "RB_OVERFLOW", 5, 5, &umr_bitfield_default },
	 { "MC_WR_IDLE", 6, 6, &umr_bitfield_default },
	 { "MC_WR_STALL", 7, 7, &umr_bitfield_default },
	 { "MC_WR_CLEAN_PENDING", 8, 8, &umr_bitfield_default },
	 { "MC_WR_CLEAN_STALL", 9, 9, &umr_bitfield_default },
	 { "BIF_INTERRUPT_LINE", 10, 10, &umr_bitfield_default },
	 { "SWITCH_READY", 11, 11, &umr_bitfield_default },
	 { "RB1_FULL", 12, 12, &umr_bitfield_default },
	 { "RB1_FULL_DRAIN", 13, 13, &umr_bitfield_default },
	 { "RB1_OVERFLOW", 14, 14, &umr_bitfield_default },
	 { "RB2_FULL", 15, 15, &umr_bitfield_default },
	 { "RB2_FULL_DRAIN", 16, 16, &umr_bitfield_default },
	 { "RB2_OVERFLOW", 17, 17, &umr_bitfield_default },
	 { "SELF_INT_GEN_IDLE", 18, 18, &umr_bitfield_default },
};
static struct umr_bitfield mmIH_PERFMON_CNTL[] = {
	 { "ENABLE0", 0, 0, &umr_bitfield_default },
	 { "CLEAR0", 1, 1, &umr_bitfield_default },
	 { "PERF_SEL0", 2, 10, &umr_bitfield_default },
	 { "ENABLE1", 16, 16, &umr_bitfield_default },
	 { "CLEAR1", 17, 17, &umr_bitfield_default },
	 { "PERF_SEL1", 18, 26, &umr_bitfield_default },
};
static struct umr_bitfield mmIH_PERFCOUNTER0_RESULT[] = {
	 { "PERF_COUNT", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmIH_PERFCOUNTER1_RESULT[] = {
	 { "PERF_COUNT", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmIH_DSM_MATCH_VALUE_BIT_31_0[] = {
	 { "VALUE", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmIH_DSM_MATCH_VALUE_BIT_63_32[] = {
	 { "VALUE", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmIH_DSM_MATCH_VALUE_BIT_95_64[] = {
	 { "VALUE", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmIH_DSM_MATCH_FIELD_CONTROL[] = {
	 { "SRC_EN", 0, 0, &umr_bitfield_default },
	 { "FCNID_EN", 1, 1, &umr_bitfield_default },
	 { "TIMESTAMP_EN", 2, 2, &umr_bitfield_default },
	 { "RINGID_EN", 3, 3, &umr_bitfield_default },
	 { "VMID_EN", 4, 4, &umr_bitfield_default },
	 { "PASID_EN", 5, 5, &umr_bitfield_default },
	 { "CLIENT_ID_EN", 6, 6, &umr_bitfield_default },
};
static struct umr_bitfield mmIH_DSM_MATCH_DATA_CONTROL[] = {
	 { "VALUE", 0, 27, &umr_bitfield_default },
};
static struct umr_bitfield mmIH_DSM_MATCH_FCN_ID[] = {
	 { "PF_VF", 0, 0, &umr_bitfield_default },
	 { "VF_ID", 1, 4, &umr_bitfield_default },
};
static struct umr_bitfield mmIH_LIMIT_INT_RATE_CNTL[] = {
	 { "LIMIT_ENABLE", 0, 0, &umr_bitfield_default },
	 { "PERF_INTERVAL", 1, 4, &umr_bitfield_default },
	 { "PERF_THRESHOLD", 5, 15, &umr_bitfield_default },
	 { "RETURN_DELAY", 17, 20, &umr_bitfield_default },
	 { "PERF_RESULT", 21, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmIH_VF_RB_STATUS[] = {
	 { "RB_FULL_DRAIN_VF", 0, 15, &umr_bitfield_default },
	 { "RB_OVERFLOW_VF", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmIH_VF_RB_STATUS2[] = {
	 { "RB_FULL_VF", 0, 15, &umr_bitfield_default },
	 { "BIF_INTERRUPT_LINE_VF", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmIH_VF_RB1_STATUS[] = {
	 { "RB_FULL_DRAIN_VF", 0, 15, &umr_bitfield_default },
	 { "RB_OVERFLOW_VF", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmIH_VF_RB1_STATUS2[] = {
	 { "RB_FULL_VF", 0, 15, &umr_bitfield_default },
};
static struct umr_bitfield mmIH_VF_RB2_STATUS[] = {
	 { "RB_FULL_DRAIN_VF", 0, 15, &umr_bitfield_default },
	 { "RB_OVERFLOW_VF", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmIH_VF_RB2_STATUS2[] = {
	 { "RB_FULL_VF", 0, 15, &umr_bitfield_default },
};
static struct umr_bitfield mmIH_INT_FLOOD_CNTL[] = {
	 { "HIGHWATER", 0, 2, &umr_bitfield_default },
	 { "FLOOD_CNTL_ENABLE", 3, 3, &umr_bitfield_default },
	 { "CLEAR_INT_FLOOD_STATUS", 4, 4, &umr_bitfield_default },
};
static struct umr_bitfield mmIH_RB0_INT_FLOOD_STATUS[] = {
	 { "RB_INT_DROPPED_VF", 0, 15, &umr_bitfield_default },
	 { "RB_INT_DROPPED", 31, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmIH_RB1_INT_FLOOD_STATUS[] = {
	 { "RB_INT_DROPPED_VF", 0, 15, &umr_bitfield_default },
	 { "RB_INT_DROPPED", 31, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmIH_RB2_INT_FLOOD_STATUS[] = {
	 { "RB_INT_DROPPED_VF", 0, 15, &umr_bitfield_default },
	 { "RB_INT_DROPPED", 31, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmIH_INT_FLOOD_STATUS[] = {
	 { "INT_DROP_CNT", 0, 7, &umr_bitfield_default },
	 { "FIRST_DROP_INT_CLIENT_ID", 8, 15, &umr_bitfield_default },
	 { "FIRST_DROP_INT_SOURCE_ID", 16, 23, &umr_bitfield_default },
	 { "FIRST_DROP_INT_VF_ID", 24, 27, &umr_bitfield_default },
	 { "FIRST_DROP_INT_VF", 28, 28, &umr_bitfield_default },
	 { "INT_DROPPED", 30, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmIH_STORM_CLIENT_LIST_CNTL[] = {
	 { "CLIENT1_IS_STORM_CLIENT", 1, 1, &umr_bitfield_default },
	 { "CLIENT2_IS_STORM_CLIENT", 2, 2, &umr_bitfield_default },
	 { "CLIENT3_IS_STORM_CLIENT", 3, 3, &umr_bitfield_default },
	 { "CLIENT4_IS_STORM_CLIENT", 4, 4, &umr_bitfield_default },
	 { "CLIENT5_IS_STORM_CLIENT", 5, 5, &umr_bitfield_default },
	 { "CLIENT6_IS_STORM_CLIENT", 6, 6, &umr_bitfield_default },
	 { "CLIENT7_IS_STORM_CLIENT", 7, 7, &umr_bitfield_default },
	 { "CLIENT8_IS_STORM_CLIENT", 8, 8, &umr_bitfield_default },
	 { "CLIENT9_IS_STORM_CLIENT", 9, 9, &umr_bitfield_default },
	 { "CLIENT10_IS_STORM_CLIENT", 10, 10, &umr_bitfield_default },
	 { "CLIENT11_IS_STORM_CLIENT", 11, 11, &umr_bitfield_default },
	 { "CLIENT12_IS_STORM_CLIENT", 12, 12, &umr_bitfield_default },
	 { "CLIENT13_IS_STORM_CLIENT", 13, 13, &umr_bitfield_default },
	 { "CLIENT14_IS_STORM_CLIENT", 14, 14, &umr_bitfield_default },
	 { "CLIENT15_IS_STORM_CLIENT", 15, 15, &umr_bitfield_default },
	 { "CLIENT16_IS_STORM_CLIENT", 16, 16, &umr_bitfield_default },
	 { "CLIENT17_IS_STORM_CLIENT", 17, 17, &umr_bitfield_default },
	 { "CLIENT18_IS_STORM_CLIENT", 18, 18, &umr_bitfield_default },
	 { "CLIENT19_IS_STORM_CLIENT", 19, 19, &umr_bitfield_default },
	 { "CLIENT20_IS_STORM_CLIENT", 20, 20, &umr_bitfield_default },
	 { "CLIENT21_IS_STORM_CLIENT", 21, 21, &umr_bitfield_default },
	 { "CLIENT22_IS_STORM_CLIENT", 22, 22, &umr_bitfield_default },
	 { "CLIENT23_IS_STORM_CLIENT", 23, 23, &umr_bitfield_default },
	 { "CLIENT24_IS_STORM_CLIENT", 24, 24, &umr_bitfield_default },
	 { "CLIENT25_IS_STORM_CLIENT", 25, 25, &umr_bitfield_default },
	 { "CLIENT26_IS_STORM_CLIENT", 26, 26, &umr_bitfield_default },
	 { "CLIENT27_IS_STORM_CLIENT", 27, 27, &umr_bitfield_default },
	 { "CLIENT28_IS_STORM_CLIENT", 28, 28, &umr_bitfield_default },
	 { "CLIENT29_IS_STORM_CLIENT", 29, 29, &umr_bitfield_default },
	 { "CLIENT30_IS_STORM_CLIENT", 30, 30, &umr_bitfield_default },
	 { "CLIENT31_IS_STORM_CLIENT", 31, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmIH_CLK_CTRL[] = {
	 { "DBUS_MUX_CLK_SOFT_OVERRIDE", 27, 27, &umr_bitfield_default },
	 { "OSSSYS_SHARE_CLK_SOFT_OVERRIDE", 28, 28, &umr_bitfield_default },
	 { "LIMIT_SMN_CLK_SOFT_OVERRIDE", 29, 29, &umr_bitfield_default },
	 { "DYN_CLK_SOFT_OVERRIDE", 30, 30, &umr_bitfield_default },
	 { "REG_CLK_SOFT_OVERRIDE", 31, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmIH_INT_FLAGS[] = {
	 { "CLIENT_0_FLAG", 0, 0, &umr_bitfield_default },
	 { "CLIENT_1_FLAG", 1, 1, &umr_bitfield_default },
	 { "CLIENT_2_FLAG", 2, 2, &umr_bitfield_default },
	 { "CLIENT_3_FLAG", 3, 3, &umr_bitfield_default },
	 { "CLIENT_4_FLAG", 4, 4, &umr_bitfield_default },
	 { "CLIENT_5_FLAG", 5, 5, &umr_bitfield_default },
	 { "CLIENT_6_FLAG", 6, 6, &umr_bitfield_default },
	 { "CLIENT_7_FLAG", 7, 7, &umr_bitfield_default },
	 { "CLIENT_8_FLAG", 8, 8, &umr_bitfield_default },
	 { "CLIENT_9_FLAG", 9, 9, &umr_bitfield_default },
	 { "CLIENT_10_FLAG", 10, 10, &umr_bitfield_default },
	 { "CLIENT_11_FLAG", 11, 11, &umr_bitfield_default },
	 { "CLIENT_12_FLAG", 12, 12, &umr_bitfield_default },
	 { "CLIENT_13_FLAG", 13, 13, &umr_bitfield_default },
	 { "CLIENT_14_FLAG", 14, 14, &umr_bitfield_default },
	 { "CLIENT_15_FLAG", 15, 15, &umr_bitfield_default },
	 { "CLIENT_16_FLAG", 16, 16, &umr_bitfield_default },
	 { "CLIENT_17_FLAG", 17, 17, &umr_bitfield_default },
	 { "CLIENT_18_FLAG", 18, 18, &umr_bitfield_default },
	 { "CLIENT_19_FLAG", 19, 19, &umr_bitfield_default },
	 { "CLIENT_20_FLAG", 20, 20, &umr_bitfield_default },
	 { "CLIENT_21_FLAG", 21, 21, &umr_bitfield_default },
	 { "CLIENT_22_FLAG", 22, 22, &umr_bitfield_default },
	 { "CLIENT_23_FLAG", 23, 23, &umr_bitfield_default },
	 { "CLIENT_24_FLAG", 24, 24, &umr_bitfield_default },
	 { "CLIENT_25_FLAG", 25, 25, &umr_bitfield_default },
	 { "CLIENT_26_FLAG", 26, 26, &umr_bitfield_default },
	 { "CLIENT_27_FLAG", 27, 27, &umr_bitfield_default },
	 { "CLIENT_28_FLAG", 28, 28, &umr_bitfield_default },
	 { "CLIENT_29_FLAG", 29, 29, &umr_bitfield_default },
	 { "CLIENT_30_FLAG", 30, 30, &umr_bitfield_default },
	 { "CLIENT_31_FLAG", 31, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmIH_LAST_INT_INFO0[] = {
	 { "CLIENT_ID", 0, 7, &umr_bitfield_default },
	 { "SOURCE_ID", 8, 15, &umr_bitfield_default },
	 { "RING_ID", 16, 23, &umr_bitfield_default },
	 { "VM_ID", 24, 27, &umr_bitfield_default },
	 { "VMID_TYPE", 31, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmIH_LAST_INT_INFO1[] = {
	 { "CONTEXT_ID", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmIH_LAST_INT_INFO2[] = {
	 { "PAS_ID", 0, 15, &umr_bitfield_default },
	 { "VF_ID", 16, 19, &umr_bitfield_default },
	 { "VF", 20, 20, &umr_bitfield_default },
};
static struct umr_bitfield mmIH_SCRATCH[] = {
	 { "DATA", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmIH_CLIENT_CREDIT_ERROR[] = {
	 { "CLEAR", 0, 0, &umr_bitfield_default },
	 { "CLIENT_1_ERROR", 1, 1, &umr_bitfield_default },
	 { "CLIENT_2_ERROR", 2, 2, &umr_bitfield_default },
	 { "CLIENT_3_ERROR", 3, 3, &umr_bitfield_default },
	 { "CLIENT_4_ERROR", 4, 4, &umr_bitfield_default },
	 { "CLIENT_5_ERROR", 5, 5, &umr_bitfield_default },
	 { "CLIENT_6_ERROR", 6, 6, &umr_bitfield_default },
	 { "CLIENT_7_ERROR", 7, 7, &umr_bitfield_default },
	 { "CLIENT_8_ERROR", 8, 8, &umr_bitfield_default },
	 { "CLIENT_9_ERROR", 9, 9, &umr_bitfield_default },
	 { "CLIENT_10_ERROR", 10, 10, &umr_bitfield_default },
	 { "CLIENT_11_ERROR", 11, 11, &umr_bitfield_default },
	 { "CLIENT_12_ERROR", 12, 12, &umr_bitfield_default },
	 { "CLIENT_13_ERROR", 13, 13, &umr_bitfield_default },
	 { "CLIENT_14_ERROR", 14, 14, &umr_bitfield_default },
	 { "CLIENT_15_ERROR", 15, 15, &umr_bitfield_default },
	 { "CLIENT_16_ERROR", 16, 16, &umr_bitfield_default },
	 { "CLIENT_17_ERROR", 17, 17, &umr_bitfield_default },
	 { "CLIENT_18_ERROR", 18, 18, &umr_bitfield_default },
	 { "CLIENT_19_ERROR", 19, 19, &umr_bitfield_default },
	 { "CLIENT_20_ERROR", 20, 20, &umr_bitfield_default },
	 { "CLIENT_21_ERROR", 21, 21, &umr_bitfield_default },
	 { "CLIENT_22_ERROR", 22, 22, &umr_bitfield_default },
	 { "CLIENT_23_ERROR", 23, 23, &umr_bitfield_default },
	 { "CLIENT_24_ERROR", 24, 24, &umr_bitfield_default },
	 { "CLIENT_25_ERROR", 25, 25, &umr_bitfield_default },
	 { "CLIENT_26_ERROR", 26, 26, &umr_bitfield_default },
	 { "CLIENT_27_ERROR", 27, 27, &umr_bitfield_default },
	 { "CLIENT_28_ERROR", 28, 28, &umr_bitfield_default },
	 { "CLIENT_29_ERROR", 29, 29, &umr_bitfield_default },
	 { "CLIENT_30_ERROR", 30, 30, &umr_bitfield_default },
	 { "CLIENT_31_ERROR", 31, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmIH_GPU_IOV_VIOLATION_LOG[] = {
	 { "VIOLATION_STATUS", 0, 0, &umr_bitfield_default },
	 { "MULTIPLE_VIOLATION_STATUS", 1, 1, &umr_bitfield_default },
	 { "ADDRESS", 2, 17, &umr_bitfield_default },
	 { "OPCODE", 18, 18, &umr_bitfield_default },
	 { "VF", 19, 19, &umr_bitfield_default },
	 { "VF_ID", 20, 23, &umr_bitfield_default },
	 { "INITIATOR_ID", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmIH_COOKIE_REC_VIOLATION_LOG[] = {
	 { "VIOLATION_STATUS", 0, 0, &umr_bitfield_default },
	 { "CLIENT_ID", 16, 23, &umr_bitfield_default },
	 { "INITIATOR_ID", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmIH_CREDIT_STATUS[] = {
	 { "CLIENT_1_CREDIT_RETURNED", 1, 1, &umr_bitfield_default },
	 { "CLIENT_2_CREDIT_RETURNED", 2, 2, &umr_bitfield_default },
	 { "CLIENT_3_CREDIT_RETURNED", 3, 3, &umr_bitfield_default },
	 { "CLIENT_4_CREDIT_RETURNED", 4, 4, &umr_bitfield_default },
	 { "CLIENT_5_CREDIT_RETURNED", 5, 5, &umr_bitfield_default },
	 { "CLIENT_6_CREDIT_RETURNED", 6, 6, &umr_bitfield_default },
	 { "CLIENT_7_CREDIT_RETURNED", 7, 7, &umr_bitfield_default },
	 { "CLIENT_8_CREDIT_RETURNED", 8, 8, &umr_bitfield_default },
	 { "CLIENT_9_CREDIT_RETURNED", 9, 9, &umr_bitfield_default },
	 { "CLIENT_10_CREDIT_RETURNED", 10, 10, &umr_bitfield_default },
	 { "CLIENT_11_CREDIT_RETURNED", 11, 11, &umr_bitfield_default },
	 { "CLIENT_12_CREDIT_RETURNED", 12, 12, &umr_bitfield_default },
	 { "CLIENT_13_CREDIT_RETURNED", 13, 13, &umr_bitfield_default },
	 { "CLIENT_14_CREDIT_RETURNED", 14, 14, &umr_bitfield_default },
	 { "CLIENT_15_CREDIT_RETURNED", 15, 15, &umr_bitfield_default },
	 { "CLIENT_16_CREDIT_RETURNED", 16, 16, &umr_bitfield_default },
	 { "CLIENT_17_CREDIT_RETURNED", 17, 17, &umr_bitfield_default },
	 { "CLIENT_18_CREDIT_RETURNED", 18, 18, &umr_bitfield_default },
	 { "CLIENT_19_CREDIT_RETURNED", 19, 19, &umr_bitfield_default },
	 { "CLIENT_20_CREDIT_RETURNED", 20, 20, &umr_bitfield_default },
	 { "CLIENT_21_CREDIT_RETURNED", 21, 21, &umr_bitfield_default },
	 { "CLIENT_22_CREDIT_RETURNED", 22, 22, &umr_bitfield_default },
	 { "CLIENT_23_CREDIT_RETURNED", 23, 23, &umr_bitfield_default },
	 { "CLIENT_24_CREDIT_RETURNED", 24, 24, &umr_bitfield_default },
	 { "CLIENT_25_CREDIT_RETURNED", 25, 25, &umr_bitfield_default },
	 { "CLIENT_26_CREDIT_RETURNED", 26, 26, &umr_bitfield_default },
	 { "CLIENT_27_CREDIT_RETURNED", 27, 27, &umr_bitfield_default },
	 { "CLIENT_28_CREDIT_RETURNED", 28, 28, &umr_bitfield_default },
	 { "CLIENT_29_CREDIT_RETURNED", 29, 29, &umr_bitfield_default },
	 { "CLIENT_30_CREDIT_RETURNED", 30, 30, &umr_bitfield_default },
	 { "CLIENT_31_CREDIT_RETURNED", 31, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmIH_MMHUB_ERROR[] = {
	 { "IH_BRESP_01", 1, 1, &umr_bitfield_default },
	 { "IH_BRESP_10", 2, 2, &umr_bitfield_default },
	 { "IH_BRESP_11", 3, 3, &umr_bitfield_default },
	 { "IH_BUSER_NACK_01", 5, 5, &umr_bitfield_default },
	 { "IH_BUSER_NACK_10", 6, 6, &umr_bitfield_default },
	 { "IH_BUSER_NACK_11", 7, 7, &umr_bitfield_default },
};
static struct umr_bitfield mmIH_REGISTER_LAST_PART2[] = {
	 { "RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSEM_CLK_CTRL[] = {
	 { "ON_DELAY", 0, 3, &umr_bitfield_default },
	 { "OFF_HYSTERESIS", 4, 11, &umr_bitfield_default },
	 { "RESERVED", 12, 23, &umr_bitfield_default },
	 { "SOFT_OVERRIDE7", 24, 24, &umr_bitfield_default },
	 { "SOFT_OVERRIDE6", 25, 25, &umr_bitfield_default },
	 { "SOFT_OVERRIDE5", 26, 26, &umr_bitfield_default },
	 { "SOFT_OVERRIDE4", 27, 27, &umr_bitfield_default },
	 { "SOFT_OVERRIDE3", 28, 28, &umr_bitfield_default },
	 { "SOFT_OVERRIDE2", 29, 29, &umr_bitfield_default },
	 { "SOFT_OVERRIDE1", 30, 30, &umr_bitfield_default },
	 { "SOFT_OVERRIDE0", 31, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSEM_UTC_CREDIT[] = {
	 { "UTCL2_CREDIT", 0, 4, &umr_bitfield_default },
	 { "WATERMARK", 8, 11, &umr_bitfield_default },
};
static struct umr_bitfield mmSEM_UTC_CONFIG[] = {
	 { "USE_MTYPE", 0, 2, &umr_bitfield_default },
	 { "FORCE_SNOOP", 3, 3, &umr_bitfield_default },
	 { "FORCE_GCC", 4, 4, &umr_bitfield_default },
	 { "USE_PT_SNOOP", 5, 5, &umr_bitfield_default },
};
static struct umr_bitfield mmSEM_UTCL2_TRAN_EN_LUT[] = {
	 { "SDMA0_UTCL2_EN", 0, 0, &umr_bitfield_default },
	 { "SDMA1_UTCL2_EN", 1, 1, &umr_bitfield_default },
	 { "UVD_UTCL2_EN", 2, 2, &umr_bitfield_default },
	 { "VCE0_UTCL2_EN", 3, 3, &umr_bitfield_default },
	 { "ACP_UTCL2_EN", 4, 4, &umr_bitfield_default },
	 { "ISP_UTCL2_EN", 5, 5, &umr_bitfield_default },
	 { "VCE1_UTCL2_EN", 6, 6, &umr_bitfield_default },
	 { "VP8_UTCL2_EN", 7, 7, &umr_bitfield_default },
	 { "RESERVED", 8, 30, &umr_bitfield_default },
	 { "CP_UTCL2_EN", 31, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSEM_MCIF_CONFIG[] = {
	 { "MC_REQ_SWAP", 0, 1, &umr_bitfield_default },
	 { "MC_WRREQ_CREDIT", 2, 7, &umr_bitfield_default },
	 { "MC_RDREQ_CREDIT", 8, 13, &umr_bitfield_default },
};
static struct umr_bitfield mmSEM_PERFMON_CNTL[] = {
	 { "PERF_ENABLE0", 0, 0, &umr_bitfield_default },
	 { "PERF_CLEAR0", 1, 1, &umr_bitfield_default },
	 { "PERF_SEL0", 2, 9, &umr_bitfield_default },
	 { "PERF_ENABLE1", 10, 10, &umr_bitfield_default },
	 { "PERF_CLEAR1", 11, 11, &umr_bitfield_default },
	 { "PERF_SEL1", 12, 19, &umr_bitfield_default },
};
static struct umr_bitfield mmSEM_PERFCOUNTER0_RESULT[] = {
	 { "PERF_COUNT", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSEM_PERFCOUNTER1_RESULT[] = {
	 { "PERF_COUNT", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSEM_STATUS[] = {
	 { "SEM_IDLE", 0, 0, &umr_bitfield_default },
	 { "SEM_INTERNAL_IDLE", 1, 1, &umr_bitfield_default },
	 { "MC_RDREQ_FIFO_FULL", 2, 2, &umr_bitfield_default },
	 { "MC_WRREQ_FIFO_FULL", 3, 3, &umr_bitfield_default },
	 { "WRITE1_FIFO_FULL", 4, 4, &umr_bitfield_default },
	 { "CHECK0_FIFO_FULL", 5, 5, &umr_bitfield_default },
	 { "MC_RDREQ_PENDING", 6, 6, &umr_bitfield_default },
	 { "MC_WRREQ_PENDING", 7, 7, &umr_bitfield_default },
	 { "SDMA0_MAILBOX_PENDING", 8, 8, &umr_bitfield_default },
	 { "SDMA1_MAILBOX_PENDING", 9, 9, &umr_bitfield_default },
	 { "UVD_MAILBOX_PENDING", 10, 10, &umr_bitfield_default },
	 { "VCE_MAILBOX_PENDING", 11, 11, &umr_bitfield_default },
	 { "CPG1_MAILBOX_PENDING", 12, 12, &umr_bitfield_default },
	 { "CPG2_MAILBOX_PENDING", 13, 13, &umr_bitfield_default },
	 { "VCE1_MAILBOX_PENDING", 14, 14, &umr_bitfield_default },
	 { "ATC_REQ_PENDING", 15, 15, &umr_bitfield_default },
	 { "OUTSTANDING_CLEAN", 16, 16, &umr_bitfield_default },
	 { "INVREQ_FLUSH_VF_MISMATCH", 17, 17, &umr_bitfield_default },
	 { "INVREQ_NONFLUSH_VF_MISMATCH", 18, 18, &umr_bitfield_default },
	 { "INVREQ_CNT_IDLE", 19, 19, &umr_bitfield_default },
	 { "ENTRYLIST_IDLE", 20, 20, &umr_bitfield_default },
	 { "MIF_IDLE", 21, 21, &umr_bitfield_default },
	 { "REGISTER_IDLE", 22, 22, &umr_bitfield_default },
	 { "ATCL2_INVREQ_IDLE", 23, 23, &umr_bitfield_default },
	 { "SWITCH_READY", 31, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSEM_MAILBOX_CLIENTCONFIG[] = {
	 { "CP_CLIENT0", 0, 2, &umr_bitfield_default },
	 { "CP_CLIENT1", 3, 5, &umr_bitfield_default },
	 { "CP_CLIENT2", 6, 8, &umr_bitfield_default },
	 { "CP_CLIENT3", 9, 11, &umr_bitfield_default },
	 { "SDMA_CLIENT0", 12, 14, &umr_bitfield_default },
	 { "UVD_CLIENT0", 15, 17, &umr_bitfield_default },
	 { "SDMA1_CLIENT0", 18, 20, &umr_bitfield_default },
	 { "VCE_CLIENT0", 21, 23, &umr_bitfield_default },
};
static struct umr_bitfield mmSEM_MAILBOX[] = {
	 { "HOSTPORT", 0, 15, &umr_bitfield_default },
	 { "RESERVED", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSEM_MAILBOX_CONTROL[] = {
	 { "HOSTPORT_ENABLE", 0, 15, &umr_bitfield_default },
	 { "RESERVED", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSEM_CHICKEN_BITS[] = {
	 { "VMID_PIPELINE_EN", 0, 0, &umr_bitfield_default },
	 { "ENTRY_PIPELINE_EN", 1, 1, &umr_bitfield_default },
	 { "CHECK_COUNTER_EN", 2, 2, &umr_bitfield_default },
	 { "ECC_BEHAVIOR", 3, 4, &umr_bitfield_default },
	 { "PHY_TRAN_EN", 6, 6, &umr_bitfield_default },
	 { "ADDR_CMP_UNTRAN_EN", 7, 7, &umr_bitfield_default },
	 { "IDLE_COUNTER_INDEX", 8, 9, &umr_bitfield_default },
	 { "OUTSTANDING_CLEAN_COUNTER_INDEX", 10, 11, &umr_bitfield_default },
	 { "ATCL2_BUS_ID", 12, 13, &umr_bitfield_default },
	 { "ATOMIC_EN", 14, 14, &umr_bitfield_default },
	 { "EXTERNAL_ATOMIC_CHECK", 15, 15, &umr_bitfield_default },
	 { "CLEAR_MAILBOX", 16, 17, &umr_bitfield_default },
	 { "INVACK_AFTER_OUTSTANDING_CLEAN", 18, 18, &umr_bitfield_default },
	 { "UTC_TAG_CONFLICT_CHECK", 19, 19, &umr_bitfield_default },
};
static struct umr_bitfield mmSEM_MAILBOX_CLIENTCONFIG_EXTRA[] = {
	 { "VCE1_CLIENT0", 0, 3, &umr_bitfield_default },
};
static struct umr_bitfield mmSEM_GPU_IOV_VIOLATION_LOG[] = {
	 { "VIOLATION_STATUS", 0, 0, &umr_bitfield_default },
	 { "MULTIPLE_VIOLATION_STATUS", 1, 1, &umr_bitfield_default },
	 { "ADDRESS", 2, 17, &umr_bitfield_default },
	 { "OPCODE", 18, 18, &umr_bitfield_default },
	 { "VF", 19, 19, &umr_bitfield_default },
	 { "VF_ID", 20, 23, &umr_bitfield_default },
	 { "INITIATOR_ID", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSEM_OUTSTANDING_THRESHOLD[] = {
	 { "VALUE", 0, 7, &umr_bitfield_default },
};
static struct umr_bitfield mmSEM_REGISTER_LAST_PART2[] = {
	 { "RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmIH_ACTIVE_FCN_ID[] = {
	 { "VF_ID", 0, 3, &umr_bitfield_default },
	 { "RESERVED", 4, 30, &umr_bitfield_default },
	 { "PF_VF", 31, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmIH_VIRT_RESET_REQ[] = {
	 { "VF", 0, 15, &umr_bitfield_default },
	 { "PF", 31, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmIH_CLIENT_CFG[] = {
	 { "TOTAL_CLIENT_NUM", 0, 4, &umr_bitfield_default },
};
static struct umr_bitfield mmIH_CLIENT_CFG_INDEX[] = {
	 { "INDEX", 0, 4, &umr_bitfield_default },
};
static struct umr_bitfield mmIH_CLIENT_CFG_DATA[] = {
	 { "CREDIT_RETURN_ADDR", 0, 16, &umr_bitfield_default },
	 { "CLIENT_TYPE", 18, 19, &umr_bitfield_default },
	 { "RING_ID", 20, 21, &umr_bitfield_default },
	 { "VF_RB_SELECT", 22, 23, &umr_bitfield_default },
	 { "OVERWRITE_RING_ID_WITH_ACTIVE_FCN_ID", 24, 24, &umr_bitfield_default },
};
static struct umr_bitfield mmIH_CID_REMAP_INDEX[] = {
	 { "INDEX", 0, 1, &umr_bitfield_default },
};
static struct umr_bitfield mmIH_CID_REMAP_DATA[] = {
	 { "CLIENT_ID", 0, 7, &umr_bitfield_default },
	 { "INITIATOR_ID", 8, 15, &umr_bitfield_default },
	 { "CLIENT_ID_REMAP", 16, 23, &umr_bitfield_default },
};
static struct umr_bitfield mmIH_CHICKEN[] = {
	 { "ACTIVE_FCN_ID_PROT_ENABLE", 0, 0, &umr_bitfield_default },
};
static struct umr_bitfield mmIH_MMHUB_CNTL[] = {
	 { "UNITID", 0, 5, &umr_bitfield_default },
	 { "IV_TLVL", 8, 10, &umr_bitfield_default },
	 { "WPTR_WB_TLVL", 12, 14, &umr_bitfield_default },
};
static struct umr_bitfield mmIH_REGISTER_LAST_PART1[] = {
	 { "RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSEM_ACTIVE_FCN_ID[] = {
	 { "VFID", 0, 3, &umr_bitfield_default },
	 { "VF", 31, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSEM_VIRT_RESET_REQ[] = {
	 { "VF", 0, 15, &umr_bitfield_default },
	 { "PF", 31, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSEM_RESP_SDMA0[] = {
	 { "ADDR", 2, 19, &umr_bitfield_default },
};
static struct umr_bitfield mmSEM_RESP_SDMA1[] = {
	 { "ADDR", 2, 19, &umr_bitfield_default },
};
static struct umr_bitfield mmSEM_RESP_UVD[] = {
	 { "ADDR", 2, 19, &umr_bitfield_default },
};
static struct umr_bitfield mmSEM_RESP_VCE_0[] = {
	 { "ADDR", 2, 19, &umr_bitfield_default },
};
static struct umr_bitfield mmSEM_RESP_ACP[] = {
	 { "ADDR", 2, 19, &umr_bitfield_default },
};
static struct umr_bitfield mmSEM_RESP_ISP[] = {
	 { "ADDR", 2, 19, &umr_bitfield_default },
};
static struct umr_bitfield mmSEM_RESP_VCE_1[] = {
	 { "ADDR", 2, 19, &umr_bitfield_default },
};
static struct umr_bitfield mmSEM_RESP_VP8[] = {
	 { "ADDR", 2, 19, &umr_bitfield_default },
};
static struct umr_bitfield mmSEM_RESP_GC[] = {
	 { "ADDR", 2, 19, &umr_bitfield_default },
};
static struct umr_bitfield mmSEM_CID_REMAP_INDEX[] = {
	 { "INDEX", 0, 1, &umr_bitfield_default },
};
static struct umr_bitfield mmSEM_CID_REMAP_DATA[] = {
	 { "CLIENT_ID", 0, 7, &umr_bitfield_default },
	 { "INITIATOR_ID", 8, 15, &umr_bitfield_default },
	 { "CLIENT_ID_REMAP", 16, 23, &umr_bitfield_default },
};
static struct umr_bitfield mmSEM_ATOMIC_OP_LUT[] = {
	 { "SIGNAL_NORMAL", 0, 6, &umr_bitfield_default },
	 { "SIGNAL_WRITE1", 7, 13, &umr_bitfield_default },
	 { "WAIT_NORMAL", 14, 20, &umr_bitfield_default },
	 { "WAIT_CHECK0", 21, 27, &umr_bitfield_default },
};
static struct umr_bitfield mmSEM_EDC_CONFIG[] = {
	 { "DIS_EDC", 1, 1, &umr_bitfield_default },
};
static struct umr_bitfield mmSEM_CHICKEN_BITS2[] = {
	 { "ACTIVE_FCN_ID_PROT_ENABLE", 0, 0, &umr_bitfield_default },
	 { "MM_CLIENT_USE_CONFIG_VFID", 1, 1, &umr_bitfield_default },
};
static struct umr_bitfield mmSEM_MMHUB_CNTL[] = {
	 { "UNIT_ID", 0, 5, &umr_bitfield_default },
	 { "TLVL_VALUE", 8, 10, &umr_bitfield_default },
};
static struct umr_bitfield mmSEM_REGISTER_LAST_PART1[] = {
	 { "RESERVED", 0, 31, &umr_bitfield_default },
};