static struct umr_bitfield mmPWRHW_SMC_IND_INDEX[] = {
	 { "SMC_IND_ADDR", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMP0PUB_IND_INDEX_0[] = {
	 { "MP0PUB_IND_ADDR", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMP0PUB_IND_INDEX[] = {
	 { "MP0PUB_IND_ADDR", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmPWRHW_SMC_IND_DATA[] = {
	 { "SMC_IND_DATA", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMP0PUB_IND_DATA_0[] = {
	 { "MP0PUB_IND_DATA", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMP0PUB_IND_DATA[] = {
	 { "MP0PUB_IND_DATA", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMP0PUB_IND_INDEX_1[] = {
	 { "MP0PUB_IND_ADDR", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMP0PUB_IND_DATA_1[] = {
	 { "MP0PUB_IND_DATA", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMP0PUB_IND_INDEX_2[] = {
	 { "MP0PUB_IND_ADDR", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMP0PUB_IND_DATA_2[] = {
	 { "MP0PUB_IND_DATA", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMP0PUB_IND_INDEX_3[] = {
	 { "MP0PUB_IND_ADDR", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMP0PUB_IND_DATA_3[] = {
	 { "MP0PUB_IND_DATA", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMP0PUB_IND_INDEX_4[] = {
	 { "MP0PUB_IND_ADDR", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMP0PUB_IND_DATA_4[] = {
	 { "MP0PUB_IND_DATA", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMP0PUB_IND_INDEX_5[] = {
	 { "MP0PUB_IND_ADDR", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMP0PUB_IND_DATA_5[] = {
	 { "MP0PUB_IND_DATA", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMP0PUB_IND_INDEX_6[] = {
	 { "MP0PUB_IND_ADDR", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMP0PUB_IND_DATA_6[] = {
	 { "MP0PUB_IND_DATA", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMP0PUB_IND_INDEX_7[] = {
	 { "MP0PUB_IND_ADDR", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMP0PUB_IND_DATA_7[] = {
	 { "MP0PUB_IND_DATA", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMP0PUB_IND_INDEX_8[] = {
	 { "MP0PUB_IND_ADDR", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMP0PUB_IND_DATA_8[] = {
	 { "MP0PUB_IND_DATA", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMP0PUB_IND_INDEX_9[] = {
	 { "MP0PUB_IND_ADDR", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMP0PUB_IND_DATA_9[] = {
	 { "MP0PUB_IND_DATA", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMP0PUB_IND_INDEX_10[] = {
	 { "MP0PUB_IND_ADDR", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMP0PUB_IND_DATA_10[] = {
	 { "MP0PUB_IND_DATA", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMP0PUB_IND_INDEX_11[] = {
	 { "MP0PUB_IND_ADDR", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMP0PUB_IND_DATA_11[] = {
	 { "MP0PUB_IND_DATA", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMP0PUB_IND_INDEX_12[] = {
	 { "MP0PUB_IND_ADDR", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMP0PUB_IND_DATA_12[] = {
	 { "MP0PUB_IND_DATA", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMP0PUB_IND_INDEX_13[] = {
	 { "MP0PUB_IND_ADDR", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMP0PUB_IND_DATA_13[] = {
	 { "MP0PUB_IND_DATA", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMP0PUB_IND_INDEX_14[] = {
	 { "MP0PUB_IND_ADDR", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMP0PUB_IND_DATA_14[] = {
	 { "MP0PUB_IND_DATA", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMP0PUB_IND_INDEX_15[] = {
	 { "MP0PUB_IND_ADDR", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMP0PUB_IND_DATA_15[] = {
	 { "MP0PUB_IND_DATA", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMP0_IND_ACCESS_CNTL[] = {
	 { "AUTO_INCREMENT_IND_0", 0, 0, &umr_bitfield_default },
	 { "AUTO_INCREMENT_IND_1", 1, 1, &umr_bitfield_default },
	 { "AUTO_INCREMENT_IND_2", 2, 2, &umr_bitfield_default },
	 { "AUTO_INCREMENT_IND_3", 3, 3, &umr_bitfield_default },
	 { "AUTO_INCREMENT_IND_4", 4, 4, &umr_bitfield_default },
	 { "AUTO_INCREMENT_IND_5", 5, 5, &umr_bitfield_default },
	 { "AUTO_INCREMENT_IND_6", 6, 6, &umr_bitfield_default },
	 { "AUTO_INCREMENT_IND_7", 7, 7, &umr_bitfield_default },
	 { "AUTO_INCREMENT_IND_8", 8, 8, &umr_bitfield_default },
	 { "AUTO_INCREMENT_IND_9", 9, 9, &umr_bitfield_default },
	 { "AUTO_INCREMENT_IND_10", 10, 10, &umr_bitfield_default },
	 { "AUTO_INCREMENT_IND_11", 11, 11, &umr_bitfield_default },
	 { "AUTO_INCREMENT_IND_12", 12, 12, &umr_bitfield_default },
	 { "AUTO_INCREMENT_IND_13", 13, 13, &umr_bitfield_default },
	 { "AUTO_INCREMENT_IND_14", 14, 14, &umr_bitfield_default },
	 { "AUTO_INCREMENT_IND_15", 15, 15, &umr_bitfield_default },
};
static struct umr_bitfield mmMP0_MSP_MESSAGE_0[] = {
	 { "MP0_MSP_MSG", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMP0_MSP_MESSAGE_1[] = {
	 { "MP0_MSP_MSG", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMP0_MSP_MESSAGE_2[] = {
	 { "MP0_MSP_MSG", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMP0_MSP_MESSAGE_3[] = {
	 { "MP0_MSP_MSG", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMP0_MSP_MESSAGE_4[] = {
	 { "MP0_MSP_MSG", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMP0_MSP_MESSAGE_5[] = {
	 { "MP0_MSP_MSG", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMP0_MSP_MESSAGE_6[] = {
	 { "MP0_MSP_MSG", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMP0_MSP_MESSAGE_7[] = {
	 { "MP0_MSP_MSG", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSAM_IH_EXT_ERR_INTR[] = {
	 { "UVD", 0, 0, &umr_bitfield_default },
	 { "VCE", 1, 1, &umr_bitfield_default },
	 { "ISP", 2, 2, &umr_bitfield_default },
	 { "RESERVED", 3, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSAM_IH_EXT_ERR_INTR_STATUS[] = {
	 { "UVD", 0, 0, &umr_bitfield_default },
	 { "VCE", 1, 1, &umr_bitfield_default },
	 { "ISP", 2, 2, &umr_bitfield_default },
	 { "RESERVED", 3, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMP0_DISP_TIMER0_CTRL0[] = {
	 { "START", 0, 0, &umr_bitfield_default },
	 { "CLEAR", 8, 8, &umr_bitfield_default },
	 { "DEC", 16, 16, &umr_bitfield_default },
	 { "PULSE_COUNT_MODE", 24, 24, &umr_bitfield_default },
};
static struct umr_bitfield mmMP0_DISP_TIMER0_CTRL1[] = {
	 { "PWM_OUTPUT_EN", 0, 0, &umr_bitfield_default },
	 { "TIME_SLICE_MODE_EN", 8, 8, &umr_bitfield_default },
	 { "TIMER_SATURATION_EN", 16, 16, &umr_bitfield_default },
	 { "RESERVED", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMP0_DISP_TIMER0_CMP_AUTOINC[] = {
	 { "AUTOINC", 0, 3, &umr_bitfield_default },
	 { "RESERVED", 4, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMP0_DISP_TIMER0_INTEN[] = {
	 { "INTEN", 0, 3, &umr_bitfield_default },
	 { "RESERVED", 4, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMP0_DISP_TIMER0_OCMP_0_0[] = {
	 { "OCMP", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMP0_DISP_TIMER0_OCMP_0_1[] = {
	 { "OCMP", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMP0_DISP_TIMER0_CNT[] = {
	 { "COUNT", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMP0_DISP_TIMER1_CTRL0[] = {
	 { "START", 0, 0, &umr_bitfield_default },
	 { "CLEAR", 8, 8, &umr_bitfield_default },
	 { "DEC", 16, 16, &umr_bitfield_default },
	 { "PULSE_COUNT_MODE", 24, 24, &umr_bitfield_default },
};
static struct umr_bitfield mmMP0_DISP_TIMER1_CTRL1[] = {
	 { "PWM_OUTPUT_EN", 0, 0, &umr_bitfield_default },
	 { "TIME_SLICE_MODE_EN", 8, 8, &umr_bitfield_default },
	 { "TIMER_SATURATION_EN", 16, 16, &umr_bitfield_default },
	 { "RESERVED", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMP0_DISP_TIMER1_CMP_AUTOINC[] = {
	 { "AUTOINC", 0, 3, &umr_bitfield_default },
	 { "RESERVED", 4, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMP0_DISP_TIMER1_INTEN[] = {
	 { "INTEN", 0, 3, &umr_bitfield_default },
	 { "RESERVED", 4, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMP0_DISP_TIMER1_OCMP_0_0[] = {
	 { "OCMP", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMP0_DISP_TIMER1_OCMP_0_1[] = {
	 { "OCMP", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMP0_DISP_TIMER1_CNT[] = {
	 { "COUNT", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSMU_MP1_SRBM2P_MSG_0[] = {
	 { "CONTENT", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSMU_MP1_SRBM2P_MSG_1[] = {
	 { "CONTENT", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSMU_MP1_SRBM2P_MSG_2[] = {
	 { "CONTENT", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSMU_MP1_SRBM2P_MSG_3[] = {
	 { "CONTENT", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSMU_MP1_SRBM2P_MSG_4[] = {
	 { "CONTENT", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSMU_MP1_SRBM2P_MSG_5[] = {
	 { "CONTENT", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSMU_MP1_SRBM2P_MSG_6[] = {
	 { "CONTENT", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSMU_MP1_SRBM2P_MSG_7[] = {
	 { "CONTENT", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSMU_MP1_SRBM2P_MSG_8[] = {
	 { "CONTENT", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSMU_MP1_SRBM2P_MSG_9[] = {
	 { "CONTENT", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSMU_MP1_SRBM2P_MSG_10[] = {
	 { "CONTENT", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSMU_MP1_SRBM2P_MSG_11[] = {
	 { "CONTENT", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSMU_MP1_SRBM2P_MSG_12[] = {
	 { "CONTENT", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSMU_MP1_SRBM2P_MSG_13[] = {
	 { "CONTENT", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSMU_MP1_SRBM2P_MSG_14[] = {
	 { "CONTENT", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSMU_MP1_SRBM2P_MSG_15[] = {
	 { "CONTENT", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSMU_MP1_SRBM2P_RESP_0[] = {
	 { "CONTENT", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSMU_MP1_SRBM2P_RESP_1[] = {
	 { "CONTENT", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSMU_MP1_SRBM2P_RESP_2[] = {
	 { "CONTENT", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSMU_MP1_SRBM2P_RESP_3[] = {
	 { "CONTENT", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSMU_MP1_SRBM2P_RESP_4[] = {
	 { "CONTENT", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSMU_MP1_SRBM2P_RESP_5[] = {
	 { "CONTENT", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSMU_MP1_SRBM2P_RESP_6[] = {
	 { "CONTENT", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSMU_MP1_SRBM2P_RESP_7[] = {
	 { "CONTENT", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSMU_MP1_SRBM2P_RESP_8[] = {
	 { "CONTENT", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSMU_MP1_SRBM2P_RESP_9[] = {
	 { "CONTENT", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSMU_MP1_SRBM2P_RESP_10[] = {
	 { "CONTENT", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSMU_MP1_SRBM2P_RESP_11[] = {
	 { "CONTENT", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSMU_MP1_SRBM2P_RESP_12[] = {
	 { "CONTENT", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSMU_MP1_SRBM2P_RESP_13[] = {
	 { "CONTENT", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSMU_MP1_SRBM2P_RESP_14[] = {
	 { "CONTENT", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSMU_MP1_SRBM2P_RESP_15[] = {
	 { "CONTENT", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSMU_MP1_SRBM2P_ARG_0[] = {
	 { "CONTENT", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSMU_MP1_SRBM2P_ARG_1[] = {
	 { "CONTENT", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSMU_MP1_SRBM2P_ARG_2[] = {
	 { "CONTENT", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSMU_MP1_SRBM2P_ARG_3[] = {
	 { "CONTENT", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSMU_MP1_SRBM2P_ARG_4[] = {
	 { "CONTENT", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSMU_MP1_SRBM2P_ARG_5[] = {
	 { "CONTENT", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSMU_MP1_SRBM2P_ARG_6[] = {
	 { "CONTENT", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSMU_MP1_SRBM2P_ARG_7[] = {
	 { "CONTENT", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSMU_MP1_SRBM2P_ARG_8[] = {
	 { "CONTENT", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSMU_MP1_SRBM2P_ARG_9[] = {
	 { "CONTENT", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSMU_MP1_SRBM2P_ARG_10[] = {
	 { "CONTENT", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSMU_MP1_SRBM2P_ARG_11[] = {
	 { "CONTENT", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSMU_MP1_SRBM2P_ARG_12[] = {
	 { "CONTENT", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSMU_MP1_SRBM2P_ARG_13[] = {
	 { "CONTENT", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSMU_MP1_SRBM2P_ARG_14[] = {
	 { "CONTENT", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSMU_MP1_SRBM2P_ARG_15[] = {
	 { "CONTENT", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSMU_MP1_ACP2MP_RESP[] = {
	 { "CONTENT", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSMU_MP1_DC2MP_RESP[] = {
	 { "CONTENT", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSMU_MP1_UVD2MP_RESP[] = {
	 { "CONTENT", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSMU_MP1_VCE2MP_RESP[] = {
	 { "CONTENT", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSMU_MP1_RLC2MP_RESP[] = {
	 { "CONTENT", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMP_FPS_CNT[] = {
	 { "FPS_CNT", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSMU_DISP0_TIMER_INT_CONTROL[] = {
	 { "INT_STAT", 0, 0, &umr_bitfield_default },
	 { "INT_UNMASK", 1, 1, &umr_bitfield_default },
	 { "INT_TYPE", 2, 2, &umr_bitfield_default },
	 { "INT_ACK", 3, 3, &umr_bitfield_default },
	 { "MASK", 4, 4, &umr_bitfield_default },
};
static struct umr_bitfield mmSMU_DISP1_TIMER_INT_CONTROL[] = {
	 { "INT_STAT", 0, 0, &umr_bitfield_default },
	 { "INT_UNMASK", 1, 1, &umr_bitfield_default },
	 { "INT_TYPE", 2, 2, &umr_bitfield_default },
	 { "INT_ACK", 3, 3, &umr_bitfield_default },
	 { "MASK", 4, 4, &umr_bitfield_default },
};
static struct umr_bitfield mmSMU_SRBM_CONFIG[] = {
	 { "MSTR_CREDITS", 0, 4, &umr_bitfield_default },
};
static struct umr_bitfield ixGC_CAC_WEIGHT_CU_0[] = {
	 { "WEIGHT_CU_SIG0", 0, 15, &umr_bitfield_default },
	 { "WEIGHT_CU_SIG1", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmGC_CAC_LKG_AGGR_LOWER[] = {
	 { "LKG_AGGR_31_0", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmGC_CAC_LKG_AGGR_UPPER[] = {
	 { "LKG_AGGR_63_32", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixGC_CAC_WEIGHT_CU_1[] = {
	 { "WEIGHT_CU_SIG2", 0, 15, &umr_bitfield_default },
	 { "WEIGHT_CU_SIG3", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixGC_CAC_WEIGHT_CU_2[] = {
	 { "WEIGHT_CU_SIG4", 0, 15, &umr_bitfield_default },
	 { "WEIGHT_CU_SIG5", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixGC_CAC_WEIGHT_CU_3[] = {
	 { "WEIGHT_CU_SIG6", 0, 15, &umr_bitfield_default },
	 { "WEIGHT_CU_SIG7", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixGC_CAC_ACC_CU0[] = {
	 { "ACCUMULATOR_31_0", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixGC_CAC_ACC_CU1[] = {
	 { "ACCUMULATOR_31_0", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixGC_CAC_ACC_CU2[] = {
	 { "ACCUMULATOR_31_0", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixGC_CAC_ACC_CU3[] = {
	 { "ACCUMULATOR_31_0", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixGC_CAC_ACC_CU4[] = {
	 { "ACCUMULATOR_31_0", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixGC_CAC_ACC_CU5[] = {
	 { "ACCUMULATOR_31_0", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixGC_CAC_ACC_CU6[] = {
	 { "ACCUMULATOR_31_0", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixGC_CAC_ACC_CU7[] = {
	 { "ACCUMULATOR_31_0", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMP_IOC_CTRL[] = {
	 { "IOC_mst_send", 0, 0, &umr_bitfield_default },
	 { "IOC_mst_stop", 1, 1, &umr_bitfield_default },
	 { "IOC_mst_force_active", 2, 2, &umr_bitfield_default },
	 { "IOC_mst_rdValid", 3, 3, &umr_bitfield_default },
	 { "IOC_mst_busy", 4, 4, &umr_bitfield_default },
	 { "IOC_mst_disabled", 5, 5, &umr_bitfield_default },
	 { "IOC_mst_debug_rst", 6, 6, &umr_bitfield_default },
	 { "IOC_mst_stop_ack", 7, 7, &umr_bitfield_default },
	 { "IOC_mst_rderr", 8, 9, &umr_bitfield_default },
};
static struct umr_bitfield ixMP_IOC_RDDATA[] = {
	 { "IOC_mst_rdData", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMP_IOC_PHASE1[] = {
	 { "BiuCqfC_AwqReqCommit", 1, 1, &umr_bitfield_default },
	 { "BiuCqfC_AltReqRdCmd", 2, 2, &umr_bitfield_default },
	 { "BiuCqfC_AltReqAddrLo", 3, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMP_IOC_PHASE2[] = {
	 { "BiuCqfC_AltReqAddrMid", 0, 7, &umr_bitfield_default },
	 { "BiuCqfC_AltReqMask", 8, 15, &umr_bitfield_default },
	 { "BiuCqfC_AltReqSize", 16, 17, &umr_bitfield_default },
	 { "BiuCqfC_AltReqAddrHi", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMP_IOC_PHASE3[] = {
	 { "BiuDbfC_C2aDataOut", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMP_IOC_READ_0[] = {
	 { "data", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMP_IOC_READ_1[] = {
	 { "data", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMP_IOC_READ_2[] = {
	 { "data", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMP_IOC_READ_3[] = {
	 { "data", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMP_IOC_READ_4[] = {
	 { "data", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMP_IOC_READ_5[] = {
	 { "data", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMP_IOC_READ_6[] = {
	 { "data", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMP_IOC_READ_7[] = {
	 { "data", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMP_IOC_READ_8[] = {
	 { "data", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMP_IOC_READ_9[] = {
	 { "data", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMP_IOC_READ_10[] = {
	 { "data", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMP_IOC_READ_11[] = {
	 { "data", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMP_IOC_READ_12[] = {
	 { "data", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMP_IOC_READ_13[] = {
	 { "data", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMP_IOC_READ_14[] = {
	 { "data", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMP_IOC_READ_15[] = {
	 { "data", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMP_IOC_WRITE_0[] = {
	 { "data", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMP_IOC_WRITE_1[] = {
	 { "data", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMP_IOC_WRITE_2[] = {
	 { "data", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMP_IOC_WRITE_3[] = {
	 { "data", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMP_IOC_WRITE_4[] = {
	 { "data", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMP_IOC_WRITE_5[] = {
	 { "data", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMP_IOC_WRITE_6[] = {
	 { "data", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMP_IOC_WRITE_7[] = {
	 { "data", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMP_IOC_WRITE_8[] = {
	 { "data", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMP_IOC_WRITE_9[] = {
	 { "data", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMP_IOC_WRITE_10[] = {
	 { "data", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMP_IOC_WRITE_11[] = {
	 { "data", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMP_IOC_WRITE_12[] = {
	 { "data", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMP_IOC_WRITE_13[] = {
	 { "data", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMP_IOC_WRITE_14[] = {
	 { "data", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMP_IOC_WRITE_15[] = {
	 { "data", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMP_DRAM_CNTL_WRREQ_CNTL[] = {
	 { "tag", 0, 16, &umr_bitfield_default },
	 { "urg", 17, 20, &umr_bitfield_default },
	 { "stall", 21, 21, &umr_bitfield_default },
	 { "priv", 22, 22, &umr_bitfield_default },
	 { "cid", 23, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMP_DRAM_CNTL_WRREQ_CNTL_1[] = {
	 { "vf", 0, 0, &umr_bitfield_default },
	 { "vfid", 1, 7, &umr_bitfield_default },
	 { "physical", 8, 8, &umr_bitfield_default },
	 { "snoop", 9, 9, &umr_bitfield_default },
	 { "inval", 10, 10, &umr_bitfield_default },
	 { "op", 11, 17, &umr_bitfield_default },
	 { "swap", 20, 21, &umr_bitfield_default },
	 { "vmid", 22, 25, &umr_bitfield_default },
	 { "atc", 26, 26, &umr_bitfield_default },
	 { "fed", 27, 27, &umr_bitfield_default },
};
static struct umr_bitfield ixMP_DRAM_CNTL_WRREQ_LOW_ADDR[] = {
	 { "addr", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMP_DRAM_CNTL_WRREQ_HIGH_ADDR[] = {
	 { "addr_47_37", 0, 10, &umr_bitfield_default },
	 { "reserved", 11, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMP_DRAM_CNTL_WRREQ_MASK[] = {
	 { "mask", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMP_DRAM_CNTL_WRREQ_DATA_0[] = {
	 { "data", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMP_DRAM_CNTL_WRREQ_DATA_1[] = {
	 { "data", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMP_DRAM_CNTL_WRREQ_DATA_2[] = {
	 { "data", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMP_DRAM_CNTL_WRREQ_DATA_3[] = {
	 { "data", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMP_DRAM_CNTL_WRREQ_DATA_4[] = {
	 { "data", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMP_DRAM_CNTL_WRREQ_DATA_5[] = {
	 { "data", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMP_DRAM_CNTL_WRREQ_DATA_6[] = {
	 { "data", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMP_DRAM_CNTL_WRREQ_DATA_7[] = {
	 { "data", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMP_DRAM_CNTL_WRREQ_STATUS[] = {
	 { "credit_counter", 0, 4, &umr_bitfield_default },
	 { "reserved0", 5, 7, &umr_bitfield_default },
	 { "fifo_not_empty", 8, 8, &umr_bitfield_default },
	 { "reserved1", 9, 15, &umr_bitfield_default },
	 { "tag_pointer", 16, 19, &umr_bitfield_default },
	 { "reserved2", 20, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMP_DRAM_CNTL_WRRET_STATUS_0[] = {
	 { "valid", 0, 0, &umr_bitfield_default },
	 { "nack", 1, 2, &umr_bitfield_default },
	 { "reserved", 3, 15, &umr_bitfield_default },
	 { "tag", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMP_DRAM_CNTL_RDREQ_ADDR[] = {
	 { "addr", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMP_DRAM_CNTL_RDREQ_CNTL[] = {
	 { "tag", 0, 15, &umr_bitfield_default },
	 { "mask", 16, 23, &umr_bitfield_default },
	 { "addr_47_40", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMP_DRAM_CNTL_RDREQ_CNTL_1[] = {
	 { "urg", 0, 3, &umr_bitfield_default },
	 { "stall", 4, 4, &umr_bitfield_default },
	 { "priv", 5, 5, &umr_bitfield_default },
	 { "swap", 6, 7, &umr_bitfield_default },
	 { "cid", 8, 16, &umr_bitfield_default },
	 { "vmid", 17, 20, &umr_bitfield_default },
	 { "atc", 21, 21, &umr_bitfield_default },
	 { "physical", 22, 22, &umr_bitfield_default },
	 { "exe", 23, 23, &umr_bitfield_default },
	 { "snoop", 24, 24, &umr_bitfield_default },
	 { "shared", 25, 25, &umr_bitfield_default },
	 { "vf", 26, 26, &umr_bitfield_default },
	 { "vfid", 27, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMP_DRAM_CNTL_RDRET_VALID[] = {
	 { "vld_0", 0, 0, &umr_bitfield_default },
	 { "vld_1", 1, 1, &umr_bitfield_default },
	 { "vld_2", 2, 2, &umr_bitfield_default },
	 { "vld_3", 3, 3, &umr_bitfield_default },
	 { "vld_4", 4, 4, &umr_bitfield_default },
	 { "vld_5", 5, 5, &umr_bitfield_default },
	 { "vld_6", 6, 6, &umr_bitfield_default },
	 { "vld_7", 7, 7, &umr_bitfield_default },
	 { "reserved", 8, 23, &umr_bitfield_default },
	 { "atomic", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMP_DRAM_CNTL_RDRET_NACK[] = {
	 { "nack_0", 0, 1, &umr_bitfield_default },
	 { "nack_1", 2, 3, &umr_bitfield_default },
	 { "nack_2", 4, 5, &umr_bitfield_default },
	 { "nack_3", 6, 7, &umr_bitfield_default },
	 { "nack_4", 8, 9, &umr_bitfield_default },
	 { "nack_5", 10, 11, &umr_bitfield_default },
	 { "nack_6", 12, 13, &umr_bitfield_default },
	 { "nack_7", 14, 15, &umr_bitfield_default },
	 { "reserved", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMP_DRAM_CNTL_RDRET_DATA_0[] = {
	 { "DATA", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMP_DRAM_CNTL_RDRET_DATA_1[] = {
	 { "DATA", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMP_DRAM_CNTL_RDRET_DATA_2[] = {
	 { "DATA", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMP_DRAM_CNTL_RDRET_DATA_3[] = {
	 { "DATA", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMP_DRAM_CNTL_RDRET_DATA_4[] = {
	 { "DATA", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMP_DRAM_CNTL_RDRET_DATA_5[] = {
	 { "DATA", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMP_DRAM_CNTL_RDRET_DATA_6[] = {
	 { "DATA", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMP_DRAM_CNTL_RDRET_DATA_7[] = {
	 { "DATA", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMP_DRAM_CNTL_RDRET_DATA_8[] = {
	 { "DATA", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMP_DRAM_CNTL_RDRET_DATA_9[] = {
	 { "DATA", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMP_DRAM_CNTL_RDRET_DATA_10[] = {
	 { "DATA", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMP_DRAM_CNTL_RDRET_DATA_11[] = {
	 { "DATA", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMP_DRAM_CNTL_RDRET_DATA_12[] = {
	 { "DATA", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMP_DRAM_CNTL_RDRET_DATA_13[] = {
	 { "DATA", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMP_DRAM_CNTL_RDRET_DATA_14[] = {
	 { "DATA", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMP_DRAM_CNTL_RDRET_DATA_15[] = {
	 { "DATA", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMP_DRAM_CNTL_RDRET_DATA_16[] = {
	 { "DATA", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMP_DRAM_CNTL_RDRET_DATA_17[] = {
	 { "DATA", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMP_DRAM_CNTL_RDRET_DATA_18[] = {
	 { "DATA", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMP_DRAM_CNTL_RDRET_DATA_19[] = {
	 { "DATA", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMP_DRAM_CNTL_RDRET_DATA_20[] = {
	 { "DATA", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMP_DRAM_CNTL_RDRET_DATA_21[] = {
	 { "DATA", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMP_DRAM_CNTL_RDRET_DATA_22[] = {
	 { "DATA", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMP_DRAM_CNTL_RDRET_DATA_23[] = {
	 { "DATA", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMP_DRAM_CNTL_RDRET_DATA_24[] = {
	 { "DATA", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMP_DRAM_CNTL_RDRET_DATA_25[] = {
	 { "DATA", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMP_DRAM_CNTL_RDRET_DATA_26[] = {
	 { "DATA", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMP_DRAM_CNTL_RDRET_DATA_27[] = {
	 { "DATA", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMP_DRAM_CNTL_RDRET_DATA_28[] = {
	 { "DATA", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMP_DRAM_CNTL_RDRET_DATA_29[] = {
	 { "DATA", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMP_DRAM_CNTL_RDRET_DATA_30[] = {
	 { "DATA", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMP_DRAM_CNTL_RDRET_DATA_31[] = {
	 { "DATA", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMP_DRAM_CNTL_RDRET_DATA_32[] = {
	 { "DATA", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMP_DRAM_CNTL_RDRET_DATA_33[] = {
	 { "DATA", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMP_DRAM_CNTL_RDRET_DATA_34[] = {
	 { "DATA", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMP_DRAM_CNTL_RDRET_DATA_35[] = {
	 { "DATA", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMP_DRAM_CNTL_RDRET_DATA_36[] = {
	 { "DATA", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMP_DRAM_CNTL_RDRET_DATA_37[] = {
	 { "DATA", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMP_DRAM_CNTL_RDRET_DATA_38[] = {
	 { "DATA", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMP_DRAM_CNTL_RDRET_DATA_39[] = {
	 { "DATA", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMP_DRAM_CNTL_RDRET_DATA_40[] = {
	 { "DATA", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMP_DRAM_CNTL_RDRET_DATA_41[] = {
	 { "DATA", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMP_DRAM_CNTL_RDRET_DATA_42[] = {
	 { "DATA", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMP_DRAM_CNTL_RDRET_DATA_43[] = {
	 { "DATA", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMP_DRAM_CNTL_RDRET_DATA_44[] = {
	 { "DATA", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMP_DRAM_CNTL_RDRET_DATA_45[] = {
	 { "DATA", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMP_DRAM_CNTL_RDRET_DATA_46[] = {
	 { "DATA", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMP_DRAM_CNTL_RDRET_DATA_47[] = {
	 { "DATA", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMP_DRAM_CNTL_RDRET_DATA_48[] = {
	 { "DATA", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMP_DRAM_CNTL_RDRET_DATA_49[] = {
	 { "DATA", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMP_DRAM_CNTL_RDRET_DATA_50[] = {
	 { "DATA", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMP_DRAM_CNTL_RDRET_DATA_51[] = {
	 { "DATA", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMP_DRAM_CNTL_RDRET_DATA_52[] = {
	 { "DATA", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMP_DRAM_CNTL_RDRET_DATA_53[] = {
	 { "DATA", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMP_DRAM_CNTL_RDRET_DATA_54[] = {
	 { "DATA", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMP_DRAM_CNTL_RDRET_DATA_55[] = {
	 { "DATA", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMP_DRAM_CNTL_RDRET_DATA_56[] = {
	 { "DATA", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMP_DRAM_CNTL_RDRET_DATA_57[] = {
	 { "DATA", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMP_DRAM_CNTL_RDRET_DATA_58[] = {
	 { "DATA", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMP_DRAM_CNTL_RDRET_DATA_59[] = {
	 { "DATA", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMP_DRAM_CNTL_RDRET_DATA_60[] = {
	 { "DATA", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMP_DRAM_CNTL_RDRET_DATA_61[] = {
	 { "DATA", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMP_DRAM_CNTL_RDRET_DATA_62[] = {
	 { "DATA", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMP_DRAM_CNTL_RDRET_DATA_63[] = {
	 { "DATA", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMP_INTERRUPT_CONTROL[] = {
	 { "MAX_CREDIT_VALUE", 0, 4, &umr_bitfield_default },
	 { "MP0_SW_TRIG_MASK", 5, 5, &umr_bitfield_default },
	 { "MP0_SW_INT_ACK", 6, 6, &umr_bitfield_default },
	 { "MP1_SW_TRIG_MASK", 7, 7, &umr_bitfield_default },
	 { "MP1_SW_INT_ACK", 8, 8, &umr_bitfield_default },
};
static struct umr_bitfield ixMP0_SW_INT[] = {
	 { "VALID", 0, 0, &umr_bitfield_default },
	 { "INT_ID", 1, 8, &umr_bitfield_default },
};
static struct umr_bitfield ixMP0_SW_INT_CTXID[] = {
	 { "CTXID", 0, 27, &umr_bitfield_default },
};
static struct umr_bitfield ixMP1_SW_INT[] = {
	 { "VALID", 0, 0, &umr_bitfield_default },
	 { "INT_ID", 1, 8, &umr_bitfield_default },
};
static struct umr_bitfield ixMP1_SW_INT_CTXID[] = {
	 { "CTXID", 0, 27, &umr_bitfield_default },
};
static struct umr_bitfield ixDISP_TIMER_ID[] = {
	 { "DISP_T0_INT_ID", 0, 7, &umr_bitfield_default },
	 { "DISP_T1_INT_ID", 8, 15, &umr_bitfield_default },
};
static struct umr_bitfield ixMP_FPS_CNT_XBAR[] = {
	 { "FPS_CNT", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMP_SRBM_CONFIG_XBAR[] = {
	 { "MSTR_CREDITS", 0, 4, &umr_bitfield_default },
};
static struct umr_bitfield ixMP_SRBM_CONTROL[] = {
	 { "ACC_VIO_EN", 0, 0, &umr_bitfield_default },
	 { "ALLOW_NS_ACC", 1, 1, &umr_bitfield_default },
	 { "SOFT_RST_MASK", 2, 2, &umr_bitfield_default },
	 { "SOFT_RST_STS", 3, 3, &umr_bitfield_default },
};
static struct umr_bitfield ixMP_SRBM_ACCVIO_LOG[] = {
	 { "ACC_VIO_OP", 0, 0, &umr_bitfield_default },
	 { "ACC_VIO_SRCID", 1, 3, &umr_bitfield_default },
	 { "ACC_VIO_VALID", 31, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMP_SRBM_ACCVIO_ADDR[] = {
	 { "ACC_VIO_ADDR", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMP_CRBBM_CONTROL[] = {
	 { "ACC_VIO_EN", 0, 0, &umr_bitfield_default },
	 { "MP0_ACCESS", 1, 1, &umr_bitfield_default },
	 { "ALLOW_NS_ACC", 2, 2, &umr_bitfield_default },
};
static struct umr_bitfield ixMP_CRBBM_ACCVIO_LOG[] = {
	 { "ACC_VIO_OP", 0, 0, &umr_bitfield_default },
	 { "ACC_VIO_INTF", 1, 1, &umr_bitfield_default },
	 { "ACC_VIO_VALID", 31, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMP_CRBBM_ACCVIO_ADDR[] = {
	 { "ACC_VIO_ADDR", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixGENERAL_PWRMGT[] = {
	 { "GLOBAL_PWRMGT_EN", 0, 0, &umr_bitfield_default },
	 { "STATIC_PM_EN", 1, 1, &umr_bitfield_default },
	 { "THERMAL_PROTECTION_DIS", 2, 2, &umr_bitfield_default },
	 { "THERMAL_PROTECTION_TYPE", 3, 3, &umr_bitfield_default },
	 { "SW_SMIO_INDEX", 6, 6, &umr_bitfield_default },
	 { "LOW_VOLT_D2_ACPI", 8, 8, &umr_bitfield_default },
	 { "LOW_VOLT_D3_ACPI", 9, 9, &umr_bitfield_default },
	 { "VOLT_PWRMGT_EN", 10, 10, &umr_bitfield_default },
	 { "SPARE11", 11, 11, &umr_bitfield_default },
	 { "GPU_COUNTER_ACPI", 14, 14, &umr_bitfield_default },
	 { "GPU_COUNTER_CLK", 15, 15, &umr_bitfield_default },
	 { "GPU_COUNTER_OFF", 16, 16, &umr_bitfield_default },
	 { "GPU_COUNTER_INTF_OFF", 17, 17, &umr_bitfield_default },
	 { "SPARE18", 18, 18, &umr_bitfield_default },
	 { "ACPI_D3_VID", 19, 20, &umr_bitfield_default },
	 { "DYN_SPREAD_SPECTRUM_EN", 23, 23, &umr_bitfield_default },
	 { "SPARE27", 27, 27, &umr_bitfield_default },
	 { "SPARE", 28, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixCNB_PWRMGT_CNTL[] = {
	 { "GNB_SLOW_MODE", 0, 1, &umr_bitfield_default },
	 { "GNB_SLOW", 2, 2, &umr_bitfield_default },
	 { "FORCE_NB_PS1", 3, 3, &umr_bitfield_default },
	 { "DPM_ENABLED", 4, 4, &umr_bitfield_default },
	 { "SPARE", 5, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixSCLK_PWRMGT_CNTL[] = {
	 { "RESET_BUSY_CNT", 4, 4, &umr_bitfield_default },
	 { "RESET_SCLK_CNT", 5, 5, &umr_bitfield_default },
	 { "RESERVED_0", 6, 6, &umr_bitfield_default },
	 { "RESERVED_3", 24, 24, &umr_bitfield_default },
};
static struct umr_bitfield ixTARGET_AND_CURRENT_PROFILE_INDEX[] = {
	 { "TARG_ACPI_INDEX", 0, 3, &umr_bitfield_default },
	 { "CURR_ACPI_INDEX", 4, 7, &umr_bitfield_default },
	 { "CURR_MCLK_INDEX", 8, 11, &umr_bitfield_default },
	 { "TARG_MCLK_INDEX", 12, 15, &umr_bitfield_default },
	 { "CURR_SCLK_INDEX", 16, 20, &umr_bitfield_default },
	 { "TARG_SCLK_INDEX", 21, 25, &umr_bitfield_default },
	 { "CURR_LCLK_INDEX", 26, 28, &umr_bitfield_default },
	 { "TARG_LCLK_INDEX", 29, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixCG_STATIC_SCREEN_PARAMETER[] = {
	 { "STATIC_SCREEN_THRESHOLD", 0, 15, &umr_bitfield_default },
	 { "STATIC_SCREEN_THRESHOLD_UNIT", 16, 19, &umr_bitfield_default },
};
static struct umr_bitfield ixCG_ACPI_CNTL[] = {
	 { "SCLK_ACPI_DIV", 0, 6, &umr_bitfield_default },
	 { "SCLK_CHANGE_SKIP", 7, 7, &umr_bitfield_default },
};
static struct umr_bitfield ixSCLK_DEEP_SLEEP_CNTL[] = {
	 { "DIV_ID", 0, 2, &umr_bitfield_default },
	 { "RAMP_DIS", 3, 3, &umr_bitfield_default },
	 { "HYSTERESIS", 4, 15, &umr_bitfield_default },
	 { "SCLK_RUNNING_MASK", 16, 16, &umr_bitfield_default },
	 { "SELF_REFRESH_MASK", 17, 17, &umr_bitfield_default },
	 { "ALLOW_NBPSTATE_MASK", 18, 18, &umr_bitfield_default },
	 { "BIF_BUSY_MASK", 19, 19, &umr_bitfield_default },
	 { "UVD_BUSY_MASK", 20, 20, &umr_bitfield_default },
	 { "MC0SRBM_BUSY_MASK", 21, 21, &umr_bitfield_default },
	 { "MC1SRBM_BUSY_MASK", 22, 22, &umr_bitfield_default },
	 { "MC_ALLOW_MASK", 23, 23, &umr_bitfield_default },
	 { "SMU_BUSY_MASK", 24, 24, &umr_bitfield_default },
	 { "SELF_REFRESH_NLC_MASK", 25, 25, &umr_bitfield_default },
	 { "FAST_EXIT_REQ_NBPSTATE", 26, 26, &umr_bitfield_default },
	 { "DEEP_SLEEP_ENTRY_MODE", 27, 27, &umr_bitfield_default },
	 { "MBUS2_ACTIVE_MASK", 28, 28, &umr_bitfield_default },
	 { "VCE_0_BUSY_MASK", 29, 29, &umr_bitfield_default },
	 { "AZ_BUSY_MASK", 30, 30, &umr_bitfield_default },
	 { "ENABLE_DS", 31, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixSCLK_DEEP_SLEEP_CNTL2[] = {
	 { "RLC_BUSY_MASK", 0, 0, &umr_bitfield_default },
	 { "HDP_BUSY_MASK", 1, 1, &umr_bitfield_default },
	 { "ROM_BUSY_MASK", 2, 2, &umr_bitfield_default },
	 { "IH_SEM_BUSY_MASK", 3, 3, &umr_bitfield_default },
	 { "PDMA_BUSY_MASK", 4, 4, &umr_bitfield_default },
	 { "IDCT_BUSY_MASK", 6, 6, &umr_bitfield_default },
	 { "SDMA_BUSY_MASK", 7, 7, &umr_bitfield_default },
	 { "DC_AZ_BUSY_MASK", 8, 8, &umr_bitfield_default },
	 { "ACP_SMU_ALLOW_DSLEEP_STUTTER_MASK", 9, 9, &umr_bitfield_default },
	 { "UVD_CG_MC_STAT_BUSY_MASK", 10, 10, &umr_bitfield_default },
	 { "VCE_0_CG_MC_STAT_BUSY_MASK", 11, 11, &umr_bitfield_default },
	 { "VCE_1_BUSY_MASK", 21, 21, &umr_bitfield_default },
	 { "VCE_1_CG_MC_STAT_BUSY_MASK", 22, 22, &umr_bitfield_default },
	 { "REG_SCLK_DEEP_SLEEP_MASK", 23, 23, &umr_bitfield_default },
	 { "INOUT_CUSHION", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixSCLK_DEEP_SLEEP_MISC_CNTL[] = {
	 { "DPM_DS_DIV_ID", 0, 2, &umr_bitfield_default },
	 { "DPM_SS_DIV_ID", 3, 5, &umr_bitfield_default },
	 { "OCP_ENABLE", 16, 16, &umr_bitfield_default },
	 { "OCP_DS_DIV_ID", 17, 19, &umr_bitfield_default },
	 { "OCP_SS_DIV_ID", 20, 22, &umr_bitfield_default },
};
static struct umr_bitfield ixLCLK_DEEP_SLEEP_CNTL[] = {
	 { "DIV_ID", 0, 2, &umr_bitfield_default },
	 { "RAMP_DIS", 3, 3, &umr_bitfield_default },
	 { "HYSTERESIS", 4, 15, &umr_bitfield_default },
	 { "RESERVED", 16, 30, &umr_bitfield_default },
	 { "ENABLE_DS", 31, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixSMU_VOLTAGE_STATUS[] = {
	 { "SMU_VOLTAGE_STATUS", 0, 0, &umr_bitfield_default },
	 { "SMU_VOLTAGE_CURRENT_LEVEL", 1, 8, &umr_bitfield_default },
};
static struct umr_bitfield ixSCLK_DEEP_SLEEP_CNTL3[] = {
	 { "GRBM_0_SMU_BUSY_MASK", 0, 0, &umr_bitfield_default },
	 { "GRBM_1_SMU_BUSY_MASK", 1, 1, &umr_bitfield_default },
	 { "GRBM_2_SMU_BUSY_MASK", 2, 2, &umr_bitfield_default },
	 { "GRBM_3_SMU_BUSY_MASK", 3, 3, &umr_bitfield_default },
	 { "GRBM_4_SMU_BUSY_MASK", 4, 4, &umr_bitfield_default },
	 { "GRBM_5_SMU_BUSY_MASK", 5, 5, &umr_bitfield_default },
	 { "GRBM_6_SMU_BUSY_MASK", 6, 6, &umr_bitfield_default },
	 { "GRBM_7_SMU_BUSY_MASK", 7, 7, &umr_bitfield_default },
	 { "GRBM_8_SMU_BUSY_MASK", 8, 8, &umr_bitfield_default },
	 { "GRBM_9_SMU_BUSY_MASK", 9, 9, &umr_bitfield_default },
	 { "GRBM_10_SMU_BUSY_MASK", 10, 10, &umr_bitfield_default },
	 { "GRBM_11_SMU_BUSY_MASK", 11, 11, &umr_bitfield_default },
	 { "GRBM_12_SMU_BUSY_MASK", 12, 12, &umr_bitfield_default },
	 { "GRBM_13_SMU_BUSY_MASK", 13, 13, &umr_bitfield_default },
	 { "GRBM_14_SMU_BUSY_MASK", 14, 14, &umr_bitfield_default },
	 { "GRBM_15_SMU_BUSY_MASK", 15, 15, &umr_bitfield_default },
	 { "SMUIF_SLAVE_SCLK_BUSY_MASK", 16, 16, &umr_bitfield_default },
	 { "SMUIF_MASTER_SCLK_BUSY_MASK", 17, 17, &umr_bitfield_default },
};
static struct umr_bitfield ixTARGET_AND_CURRENT_PROFILE_INDEX_1[] = {
	 { "CURR_VDDCI_INDEX", 0, 3, &umr_bitfield_default },
	 { "TARG_VDDCI_INDEX", 4, 7, &umr_bitfield_default },
	 { "CURR_MVDD_INDEX", 8, 11, &umr_bitfield_default },
	 { "TARG_MVDD_INDEX", 12, 15, &umr_bitfield_default },
	 { "CURR_VDDC_INDEX", 16, 19, &umr_bitfield_default },
	 { "TARG_VDDC_INDEX", 20, 23, &umr_bitfield_default },
	 { "CURR_PCIE_INDEX", 24, 27, &umr_bitfield_default },
	 { "TARG_PCIE_INDEX", 28, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixTARGET_AND_CURRENT_PROFILE_INDEX_2[] = {
	 { "CURR_UVD_INDEX", 0, 3, &umr_bitfield_default },
	 { "TARG_UVD_INDEX", 4, 7, &umr_bitfield_default },
	 { "CURR_VCE_INDEX", 8, 11, &umr_bitfield_default },
	 { "TARG_VCE_INDEX", 12, 15, &umr_bitfield_default },
	 { "CURR_ACP_INDEX", 16, 19, &umr_bitfield_default },
	 { "TARG_ACP_INDEX", 20, 23, &umr_bitfield_default },
	 { "CURR_SAMU_INDEX", 24, 27, &umr_bitfield_default },
	 { "TARG_SAMU_INDEX", 28, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixCG_ULV_PARAMETER[] = {
	 { "ULV_THRESHOLD", 0, 15, &umr_bitfield_default },
	 { "ULV_THRESHOLD_UNIT", 16, 19, &umr_bitfield_default },
};
static struct umr_bitfield ixCG_FREQ_TRAN_VOTING_0[] = {
	 { "BIF_FREQ_THROTTLING_VOTE_EN", 0, 0, &umr_bitfield_default },
	 { "HDP_FREQ_THROTTLING_VOTE_EN", 1, 1, &umr_bitfield_default },
	 { "ROM_FREQ_THROTTLING_VOTE_EN", 2, 2, &umr_bitfield_default },
	 { "IH_SEM_FREQ_THROTTLING_VOTE_EN", 3, 3, &umr_bitfield_default },
	 { "PDMA_FREQ_THROTTLING_VOTE_EN", 4, 4, &umr_bitfield_default },
	 { "DRM_FREQ_THROTTLING_VOTE_EN", 5, 5, &umr_bitfield_default },
	 { "IDCT_FREQ_THROTTLING_VOTE_EN", 6, 6, &umr_bitfield_default },
	 { "ACP_FREQ_THROTTLING_VOTE_EN", 7, 7, &umr_bitfield_default },
	 { "SDMA_FREQ_THROTTLING_VOTE_EN", 8, 8, &umr_bitfield_default },
	 { "UVD_FREQ_THROTTLING_VOTE_EN", 9, 9, &umr_bitfield_default },
	 { "VCE_0_FREQ_THROTTLING_VOTE_EN", 10, 10, &umr_bitfield_default },
	 { "DC_AZ_FREQ_THROTTLING_VOTE_EN", 11, 11, &umr_bitfield_default },
	 { "AVP_FREQ_THROTTLING_VOTE_EN", 13, 13, &umr_bitfield_default },
	 { "GRBM_0_FREQ_THROTTLING_VOTE_EN", 14, 14, &umr_bitfield_default },
	 { "GRBM_1_FREQ_THROTTLING_VOTE_EN", 15, 15, &umr_bitfield_default },
	 { "GRBM_2_FREQ_THROTTLING_VOTE_EN", 16, 16, &umr_bitfield_default },
	 { "GRBM_3_FREQ_THROTTLING_VOTE_EN", 17, 17, &umr_bitfield_default },
	 { "GRBM_4_FREQ_THROTTLING_VOTE_EN", 18, 18, &umr_bitfield_default },
	 { "GRBM_5_FREQ_THROTTLING_VOTE_EN", 19, 19, &umr_bitfield_default },
	 { "GRBM_6_FREQ_THROTTLING_VOTE_EN", 20, 20, &umr_bitfield_default },
	 { "GRBM_7_FREQ_THROTTLING_VOTE_EN", 21, 21, &umr_bitfield_default },
	 { "GRBM_8_FREQ_THROTTLING_VOTE_EN", 22, 22, &umr_bitfield_default },
	 { "GRBM_9_FREQ_THROTTLING_VOTE_EN", 23, 23, &umr_bitfield_default },
	 { "GRBM_10_FREQ_THROTTLING_VOTE_EN", 24, 24, &umr_bitfield_default },
	 { "GRBM_11_FREQ_THROTTLING_VOTE_EN", 25, 25, &umr_bitfield_default },
	 { "GRBM_12_FREQ_THROTTLING_VOTE_EN", 26, 26, &umr_bitfield_default },
	 { "GRBM_13_FREQ_THROTTLING_VOTE_EN", 27, 27, &umr_bitfield_default },
	 { "GRBM_14_FREQ_THROTTLING_VOTE_EN", 28, 28, &umr_bitfield_default },
	 { "GRBM_15_FREQ_THROTTLING_VOTE_EN", 29, 29, &umr_bitfield_default },
	 { "RLC_FREQ_THROTTLING_VOTE_EN", 30, 30, &umr_bitfield_default },
	 { "VCE_1_FREQ_THROTTLING_VOTE_EN", 31, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixCG_FREQ_TRAN_VOTING_1[] = {
	 { "BIF_FREQ_THROTTLING_VOTE_EN", 0, 0, &umr_bitfield_default },
	 { "HDP_FREQ_THROTTLING_VOTE_EN", 1, 1, &umr_bitfield_default },
	 { "ROM_FREQ_THROTTLING_VOTE_EN", 2, 2, &umr_bitfield_default },
	 { "IH_SEM_FREQ_THROTTLING_VOTE_EN", 3, 3, &umr_bitfield_default },
	 { "PDMA_FREQ_THROTTLING_VOTE_EN", 4, 4, &umr_bitfield_default },
	 { "DRM_FREQ_THROTTLING_VOTE_EN", 5, 5, &umr_bitfield_default },
	 { "IDCT_FREQ_THROTTLING_VOTE_EN", 6, 6, &umr_bitfield_default },
	 { "ACP_FREQ_THROTTLING_VOTE_EN", 7, 7, &umr_bitfield_default },
	 { "SDMA_FREQ_THROTTLING_VOTE_EN", 8, 8, &umr_bitfield_default },
	 { "UVD_FREQ_THROTTLING_VOTE_EN", 9, 9, &umr_bitfield_default },
	 { "VCE_0_FREQ_THROTTLING_VOTE_EN", 10, 10, &umr_bitfield_default },
	 { "DC_AZ_FREQ_THROTTLING_VOTE_EN", 11, 11, &umr_bitfield_default },
	 { "AVP_FREQ_THROTTLING_VOTE_EN", 13, 13, &umr_bitfield_default },
	 { "GRBM_0_FREQ_THROTTLING_VOTE_EN", 14, 14, &umr_bitfield_default },
	 { "GRBM_1_FREQ_THROTTLING_VOTE_EN", 15, 15, &umr_bitfield_default },
	 { "GRBM_2_FREQ_THROTTLING_VOTE_EN", 16, 16, &umr_bitfield_default },
	 { "GRBM_3_FREQ_THROTTLING_VOTE_EN", 17, 17, &umr_bitfield_default },
	 { "GRBM_4_FREQ_THROTTLING_VOTE_EN", 18, 18, &umr_bitfield_default },
	 { "GRBM_5_FREQ_THROTTLING_VOTE_EN", 19, 19, &umr_bitfield_default },
	 { "GRBM_6_FREQ_THROTTLING_VOTE_EN", 20, 20, &umr_bitfield_default },
	 { "GRBM_7_FREQ_THROTTLING_VOTE_EN", 21, 21, &umr_bitfield_default },
	 { "GRBM_8_FREQ_THROTTLING_VOTE_EN", 22, 22, &umr_bitfield_default },
	 { "GRBM_9_FREQ_THROTTLING_VOTE_EN", 23, 23, &umr_bitfield_default },
	 { "GRBM_10_FREQ_THROTTLING_VOTE_EN", 24, 24, &umr_bitfield_default },
	 { "GRBM_11_FREQ_THROTTLING_VOTE_EN", 25, 25, &umr_bitfield_default },
	 { "GRBM_12_FREQ_THROTTLING_VOTE_EN", 26, 26, &umr_bitfield_default },
	 { "GRBM_13_FREQ_THROTTLING_VOTE_EN", 27, 27, &umr_bitfield_default },
	 { "GRBM_14_FREQ_THROTTLING_VOTE_EN", 28, 28, &umr_bitfield_default },
	 { "GRBM_15_FREQ_THROTTLING_VOTE_EN", 29, 29, &umr_bitfield_default },
	 { "RLC_FREQ_THROTTLING_VOTE_EN", 30, 30, &umr_bitfield_default },
	 { "VCE_1_FREQ_THROTTLING_VOTE_EN", 31, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixCG_FREQ_TRAN_VOTING_2[] = {
	 { "BIF_FREQ_THROTTLING_VOTE_EN", 0, 0, &umr_bitfield_default },
	 { "HDP_FREQ_THROTTLING_VOTE_EN", 1, 1, &umr_bitfield_default },
	 { "ROM_FREQ_THROTTLING_VOTE_EN", 2, 2, &umr_bitfield_default },
	 { "IH_SEM_FREQ_THROTTLING_VOTE_EN", 3, 3, &umr_bitfield_default },
	 { "PDMA_FREQ_THROTTLING_VOTE_EN", 4, 4, &umr_bitfield_default },
	 { "DRM_FREQ_THROTTLING_VOTE_EN", 5, 5, &umr_bitfield_default },
	 { "IDCT_FREQ_THROTTLING_VOTE_EN", 6, 6, &umr_bitfield_default },
	 { "ACP_FREQ_THROTTLING_VOTE_EN", 7, 7, &umr_bitfield_default },
	 { "SDMA_FREQ_THROTTLING_VOTE_EN", 8, 8, &umr_bitfield_default },
	 { "UVD_FREQ_THROTTLING_VOTE_EN", 9, 9, &umr_bitfield_default },
	 { "VCE_0_FREQ_THROTTLING_VOTE_EN", 10, 10, &umr_bitfield_default },
	 { "DC_AZ_FREQ_THROTTLING_VOTE_EN", 11, 11, &umr_bitfield_default },
	 { "AVP_FREQ_THROTTLING_VOTE_EN", 13, 13, &umr_bitfield_default },
	 { "GRBM_0_FREQ_THROTTLING_VOTE_EN", 14, 14, &umr_bitfield_default },
	 { "GRBM_1_FREQ_THROTTLING_VOTE_EN", 15, 15, &umr_bitfield_default },
	 { "GRBM_2_FREQ_THROTTLING_VOTE_EN", 16, 16, &umr_bitfield_default },
	 { "GRBM_3_FREQ_THROTTLING_VOTE_EN", 17, 17, &umr_bitfield_default },
	 { "GRBM_4_FREQ_THROTTLING_VOTE_EN", 18, 18, &umr_bitfield_default },
	 { "GRBM_5_FREQ_THROTTLING_VOTE_EN", 19, 19, &umr_bitfield_default },
	 { "GRBM_6_FREQ_THROTTLING_VOTE_EN", 20, 20, &umr_bitfield_default },
	 { "GRBM_7_FREQ_THROTTLING_VOTE_EN", 21, 21, &umr_bitfield_default },
	 { "GRBM_8_FREQ_THROTTLING_VOTE_EN", 22, 22, &umr_bitfield_default },
	 { "GRBM_9_FREQ_THROTTLING_VOTE_EN", 23, 23, &umr_bitfield_default },
	 { "GRBM_10_FREQ_THROTTLING_VOTE_EN", 24, 24, &umr_bitfield_default },
	 { "GRBM_11_FREQ_THROTTLING_VOTE_EN", 25, 25, &umr_bitfield_default },
	 { "GRBM_12_FREQ_THROTTLING_VOTE_EN", 26, 26, &umr_bitfield_default },
	 { "GRBM_13_FREQ_THROTTLING_VOTE_EN", 27, 27, &umr_bitfield_default },
	 { "GRBM_14_FREQ_THROTTLING_VOTE_EN", 28, 28, &umr_bitfield_default },
	 { "GRBM_15_FREQ_THROTTLING_VOTE_EN", 29, 29, &umr_bitfield_default },
	 { "RLC_FREQ_THROTTLING_VOTE_EN", 30, 30, &umr_bitfield_default },
	 { "VCE_1_FREQ_THROTTLING_VOTE_EN", 31, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixCG_FREQ_TRAN_VOTING_3[] = {
	 { "BIF_FREQ_THROTTLING_VOTE_EN", 0, 0, &umr_bitfield_default },
	 { "HDP_FREQ_THROTTLING_VOTE_EN", 1, 1, &umr_bitfield_default },
	 { "ROM_FREQ_THROTTLING_VOTE_EN", 2, 2, &umr_bitfield_default },
	 { "IH_SEM_FREQ_THROTTLING_VOTE_EN", 3, 3, &umr_bitfield_default },
	 { "PDMA_FREQ_THROTTLING_VOTE_EN", 4, 4, &umr_bitfield_default },
	 { "DRM_FREQ_THROTTLING_VOTE_EN", 5, 5, &umr_bitfield_default },
	 { "IDCT_FREQ_THROTTLING_VOTE_EN", 6, 6, &umr_bitfield_default },
	 { "ACP_FREQ_THROTTLING_VOTE_EN", 7, 7, &umr_bitfield_default },
	 { "SDMA_FREQ_THROTTLING_VOTE_EN", 8, 8, &umr_bitfield_default },
	 { "UVD_FREQ_THROTTLING_VOTE_EN", 9, 9, &umr_bitfield_default },
	 { "VCE_0_FREQ_THROTTLING_VOTE_EN", 10, 10, &umr_bitfield_default },
	 { "DC_AZ_FREQ_THROTTLING_VOTE_EN", 11, 11, &umr_bitfield_default },
	 { "AVP_FREQ_THROTTLING_VOTE_EN", 13, 13, &umr_bitfield_default },
	 { "GRBM_0_FREQ_THROTTLING_VOTE_EN", 14, 14, &umr_bitfield_default },
	 { "GRBM_1_FREQ_THROTTLING_VOTE_EN", 15, 15, &umr_bitfield_default },
	 { "GRBM_2_FREQ_THROTTLING_VOTE_EN", 16, 16, &umr_bitfield_default },
	 { "GRBM_3_FREQ_THROTTLING_VOTE_EN", 17, 17, &umr_bitfield_default },
	 { "GRBM_4_FREQ_THROTTLING_VOTE_EN", 18, 18, &umr_bitfield_default },
	 { "GRBM_5_FREQ_THROTTLING_VOTE_EN", 19, 19, &umr_bitfield_default },
	 { "GRBM_6_FREQ_THROTTLING_VOTE_EN", 20, 20, &umr_bitfield_default },
	 { "GRBM_7_FREQ_THROTTLING_VOTE_EN", 21, 21, &umr_bitfield_default },
	 { "GRBM_8_FREQ_THROTTLING_VOTE_EN", 22, 22, &umr_bitfield_default },
	 { "GRBM_9_FREQ_THROTTLING_VOTE_EN", 23, 23, &umr_bitfield_default },
	 { "GRBM_10_FREQ_THROTTLING_VOTE_EN", 24, 24, &umr_bitfield_default },
	 { "GRBM_11_FREQ_THROTTLING_VOTE_EN", 25, 25, &umr_bitfield_default },
	 { "GRBM_12_FREQ_THROTTLING_VOTE_EN", 26, 26, &umr_bitfield_default },
	 { "GRBM_13_FREQ_THROTTLING_VOTE_EN", 27, 27, &umr_bitfield_default },
	 { "GRBM_14_FREQ_THROTTLING_VOTE_EN", 28, 28, &umr_bitfield_default },
	 { "GRBM_15_FREQ_THROTTLING_VOTE_EN", 29, 29, &umr_bitfield_default },
	 { "RLC_FREQ_THROTTLING_VOTE_EN", 30, 30, &umr_bitfield_default },
	 { "VCE_1_FREQ_THROTTLING_VOTE_EN", 31, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixCG_FREQ_TRAN_VOTING_4[] = {
	 { "BIF_FREQ_THROTTLING_VOTE_EN", 0, 0, &umr_bitfield_default },
	 { "HDP_FREQ_THROTTLING_VOTE_EN", 1, 1, &umr_bitfield_default },
	 { "ROM_FREQ_THROTTLING_VOTE_EN", 2, 2, &umr_bitfield_default },
	 { "IH_SEM_FREQ_THROTTLING_VOTE_EN", 3, 3, &umr_bitfield_default },
	 { "PDMA_FREQ_THROTTLING_VOTE_EN", 4, 4, &umr_bitfield_default },
	 { "DRM_FREQ_THROTTLING_VOTE_EN", 5, 5, &umr_bitfield_default },
	 { "IDCT_FREQ_THROTTLING_VOTE_EN", 6, 6, &umr_bitfield_default },
	 { "ACP_FREQ_THROTTLING_VOTE_EN", 7, 7, &umr_bitfield_default },
	 { "SDMA_FREQ_THROTTLING_VOTE_EN", 8, 8, &umr_bitfield_default },
	 { "UVD_FREQ_THROTTLING_VOTE_EN", 9, 9, &umr_bitfield_default },
	 { "VCE_0_FREQ_THROTTLING_VOTE_EN", 10, 10, &umr_bitfield_default },
	 { "DC_AZ_FREQ_THROTTLING_VOTE_EN", 11, 11, &umr_bitfield_default },
	 { "AVP_FREQ_THROTTLING_VOTE_EN", 13, 13, &umr_bitfield_default },
	 { "GRBM_0_FREQ_THROTTLING_VOTE_EN", 14, 14, &umr_bitfield_default },
	 { "GRBM_1_FREQ_THROTTLING_VOTE_EN", 15, 15, &umr_bitfield_default },
	 { "GRBM_2_FREQ_THROTTLING_VOTE_EN", 16, 16, &umr_bitfield_default },
	 { "GRBM_3_FREQ_THROTTLING_VOTE_EN", 17, 17, &umr_bitfield_default },
	 { "GRBM_4_FREQ_THROTTLING_VOTE_EN", 18, 18, &umr_bitfield_default },
	 { "GRBM_5_FREQ_THROTTLING_VOTE_EN", 19, 19, &umr_bitfield_default },
	 { "GRBM_6_FREQ_THROTTLING_VOTE_EN", 20, 20, &umr_bitfield_default },
	 { "GRBM_7_FREQ_THROTTLING_VOTE_EN", 21, 21, &umr_bitfield_default },
	 { "GRBM_8_FREQ_THROTTLING_VOTE_EN", 22, 22, &umr_bitfield_default },
	 { "GRBM_9_FREQ_THROTTLING_VOTE_EN", 23, 23, &umr_bitfield_default },
	 { "GRBM_10_FREQ_THROTTLING_VOTE_EN", 24, 24, &umr_bitfield_default },
	 { "GRBM_11_FREQ_THROTTLING_VOTE_EN", 25, 25, &umr_bitfield_default },
	 { "GRBM_12_FREQ_THROTTLING_VOTE_EN", 26, 26, &umr_bitfield_default },
	 { "GRBM_13_FREQ_THROTTLING_VOTE_EN", 27, 27, &umr_bitfield_default },
	 { "GRBM_14_FREQ_THROTTLING_VOTE_EN", 28, 28, &umr_bitfield_default },
	 { "GRBM_15_FREQ_THROTTLING_VOTE_EN", 29, 29, &umr_bitfield_default },
	 { "RLC_FREQ_THROTTLING_VOTE_EN", 30, 30, &umr_bitfield_default },
	 { "VCE_1_FREQ_THROTTLING_VOTE_EN", 31, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixCG_FREQ_TRAN_VOTING_5[] = {
	 { "BIF_FREQ_THROTTLING_VOTE_EN", 0, 0, &umr_bitfield_default },
	 { "HDP_FREQ_THROTTLING_VOTE_EN", 1, 1, &umr_bitfield_default },
	 { "ROM_FREQ_THROTTLING_VOTE_EN", 2, 2, &umr_bitfield_default },
	 { "IH_SEM_FREQ_THROTTLING_VOTE_EN", 3, 3, &umr_bitfield_default },
	 { "PDMA_FREQ_THROTTLING_VOTE_EN", 4, 4, &umr_bitfield_default },
	 { "DRM_FREQ_THROTTLING_VOTE_EN", 5, 5, &umr_bitfield_default },
	 { "IDCT_FREQ_THROTTLING_VOTE_EN", 6, 6, &umr_bitfield_default },
	 { "ACP_FREQ_THROTTLING_VOTE_EN", 7, 7, &umr_bitfield_default },
	 { "SDMA_FREQ_THROTTLING_VOTE_EN", 8, 8, &umr_bitfield_default },
	 { "UVD_FREQ_THROTTLING_VOTE_EN", 9, 9, &umr_bitfield_default },
	 { "VCE_0_FREQ_THROTTLING_VOTE_EN", 10, 10, &umr_bitfield_default },
	 { "DC_AZ_FREQ_THROTTLING_VOTE_EN", 11, 11, &umr_bitfield_default },
	 { "AVP_FREQ_THROTTLING_VOTE_EN", 13, 13, &umr_bitfield_default },
	 { "GRBM_0_FREQ_THROTTLING_VOTE_EN", 14, 14, &umr_bitfield_default },
	 { "GRBM_1_FREQ_THROTTLING_VOTE_EN", 15, 15, &umr_bitfield_default },
	 { "GRBM_2_FREQ_THROTTLING_VOTE_EN", 16, 16, &umr_bitfield_default },
	 { "GRBM_3_FREQ_THROTTLING_VOTE_EN", 17, 17, &umr_bitfield_default },
	 { "GRBM_4_FREQ_THROTTLING_VOTE_EN", 18, 18, &umr_bitfield_default },
	 { "GRBM_5_FREQ_THROTTLING_VOTE_EN", 19, 19, &umr_bitfield_default },
	 { "GRBM_6_FREQ_THROTTLING_VOTE_EN", 20, 20, &umr_bitfield_default },
	 { "GRBM_7_FREQ_THROTTLING_VOTE_EN", 21, 21, &umr_bitfield_default },
	 { "GRBM_8_FREQ_THROTTLING_VOTE_EN", 22, 22, &umr_bitfield_default },
	 { "GRBM_9_FREQ_THROTTLING_VOTE_EN", 23, 23, &umr_bitfield_default },
	 { "GRBM_10_FREQ_THROTTLING_VOTE_EN", 24, 24, &umr_bitfield_default },
	 { "GRBM_11_FREQ_THROTTLING_VOTE_EN", 25, 25, &umr_bitfield_default },
	 { "GRBM_12_FREQ_THROTTLING_VOTE_EN", 26, 26, &umr_bitfield_default },
	 { "GRBM_13_FREQ_THROTTLING_VOTE_EN", 27, 27, &umr_bitfield_default },
	 { "GRBM_14_FREQ_THROTTLING_VOTE_EN", 28, 28, &umr_bitfield_default },
	 { "GRBM_15_FREQ_THROTTLING_VOTE_EN", 29, 29, &umr_bitfield_default },
	 { "RLC_FREQ_THROTTLING_VOTE_EN", 30, 30, &umr_bitfield_default },
	 { "VCE_1_FREQ_THROTTLING_VOTE_EN", 31, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixCG_FREQ_TRAN_VOTING_6[] = {
	 { "BIF_FREQ_THROTTLING_VOTE_EN", 0, 0, &umr_bitfield_default },
	 { "HDP_FREQ_THROTTLING_VOTE_EN", 1, 1, &umr_bitfield_default },
	 { "ROM_FREQ_THROTTLING_VOTE_EN", 2, 2, &umr_bitfield_default },
	 { "IH_SEM_FREQ_THROTTLING_VOTE_EN", 3, 3, &umr_bitfield_default },
	 { "PDMA_FREQ_THROTTLING_VOTE_EN", 4, 4, &umr_bitfield_default },
	 { "DRM_FREQ_THROTTLING_VOTE_EN", 5, 5, &umr_bitfield_default },
	 { "IDCT_FREQ_THROTTLING_VOTE_EN", 6, 6, &umr_bitfield_default },
	 { "ACP_FREQ_THROTTLING_VOTE_EN", 7, 7, &umr_bitfield_default },
	 { "SDMA_FREQ_THROTTLING_VOTE_EN", 8, 8, &umr_bitfield_default },
	 { "UVD_FREQ_THROTTLING_VOTE_EN", 9, 9, &umr_bitfield_default },
	 { "VCE_0_FREQ_THROTTLING_VOTE_EN", 10, 10, &umr_bitfield_default },
	 { "DC_AZ_FREQ_THROTTLING_VOTE_EN", 11, 11, &umr_bitfield_default },
	 { "AVP_FREQ_THROTTLING_VOTE_EN", 13, 13, &umr_bitfield_default },
	 { "GRBM_0_FREQ_THROTTLING_VOTE_EN", 14, 14, &umr_bitfield_default },
	 { "GRBM_1_FREQ_THROTTLING_VOTE_EN", 15, 15, &umr_bitfield_default },
	 { "GRBM_2_FREQ_THROTTLING_VOTE_EN", 16, 16, &umr_bitfield_default },
	 { "GRBM_3_FREQ_THROTTLING_VOTE_EN", 17, 17, &umr_bitfield_default },
	 { "GRBM_4_FREQ_THROTTLING_VOTE_EN", 18, 18, &umr_bitfield_default },
	 { "GRBM_5_FREQ_THROTTLING_VOTE_EN", 19, 19, &umr_bitfield_default },
	 { "GRBM_6_FREQ_THROTTLING_VOTE_EN", 20, 20, &umr_bitfield_default },
	 { "GRBM_7_FREQ_THROTTLING_VOTE_EN", 21, 21, &umr_bitfield_default },
	 { "GRBM_8_FREQ_THROTTLING_VOTE_EN", 22, 22, &umr_bitfield_default },
	 { "GRBM_9_FREQ_THROTTLING_VOTE_EN", 23, 23, &umr_bitfield_default },
	 { "GRBM_10_FREQ_THROTTLING_VOTE_EN", 24, 24, &umr_bitfield_default },
	 { "GRBM_11_FREQ_THROTTLING_VOTE_EN", 25, 25, &umr_bitfield_default },
	 { "GRBM_12_FREQ_THROTTLING_VOTE_EN", 26, 26, &umr_bitfield_default },
	 { "GRBM_13_FREQ_THROTTLING_VOTE_EN", 27, 27, &umr_bitfield_default },
	 { "GRBM_14_FREQ_THROTTLING_VOTE_EN", 28, 28, &umr_bitfield_default },
	 { "GRBM_15_FREQ_THROTTLING_VOTE_EN", 29, 29, &umr_bitfield_default },
	 { "RLC_FREQ_THROTTLING_VOTE_EN", 30, 30, &umr_bitfield_default },
	 { "VCE_1_FREQ_THROTTLING_VOTE_EN", 31, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixCG_FREQ_TRAN_VOTING_7[] = {
	 { "BIF_FREQ_THROTTLING_VOTE_EN", 0, 0, &umr_bitfield_default },
	 { "HDP_FREQ_THROTTLING_VOTE_EN", 1, 1, &umr_bitfield_default },
	 { "ROM_FREQ_THROTTLING_VOTE_EN", 2, 2, &umr_bitfield_default },
	 { "IH_SEM_FREQ_THROTTLING_VOTE_EN", 3, 3, &umr_bitfield_default },
	 { "PDMA_FREQ_THROTTLING_VOTE_EN", 4, 4, &umr_bitfield_default },
	 { "DRM_FREQ_THROTTLING_VOTE_EN", 5, 5, &umr_bitfield_default },
	 { "IDCT_FREQ_THROTTLING_VOTE_EN", 6, 6, &umr_bitfield_default },
	 { "ACP_FREQ_THROTTLING_VOTE_EN", 7, 7, &umr_bitfield_default },
	 { "SDMA_FREQ_THROTTLING_VOTE_EN", 8, 8, &umr_bitfield_default },
	 { "UVD_FREQ_THROTTLING_VOTE_EN", 9, 9, &umr_bitfield_default },
	 { "VCE_0_FREQ_THROTTLING_VOTE_EN", 10, 10, &umr_bitfield_default },
	 { "DC_AZ_FREQ_THROTTLING_VOTE_EN", 11, 11, &umr_bitfield_default },
	 { "AVP_FREQ_THROTTLING_VOTE_EN", 13, 13, &umr_bitfield_default },
	 { "GRBM_0_FREQ_THROTTLING_VOTE_EN", 14, 14, &umr_bitfield_default },
	 { "GRBM_1_FREQ_THROTTLING_VOTE_EN", 15, 15, &umr_bitfield_default },
	 { "GRBM_2_FREQ_THROTTLING_VOTE_EN", 16, 16, &umr_bitfield_default },
	 { "GRBM_3_FREQ_THROTTLING_VOTE_EN", 17, 17, &umr_bitfield_default },
	 { "GRBM_4_FREQ_THROTTLING_VOTE_EN", 18, 18, &umr_bitfield_default },
	 { "GRBM_5_FREQ_THROTTLING_VOTE_EN", 19, 19, &umr_bitfield_default },
	 { "GRBM_6_FREQ_THROTTLING_VOTE_EN", 20, 20, &umr_bitfield_default },
	 { "GRBM_7_FREQ_THROTTLING_VOTE_EN", 21, 21, &umr_bitfield_default },
	 { "GRBM_8_FREQ_THROTTLING_VOTE_EN", 22, 22, &umr_bitfield_default },
	 { "GRBM_9_FREQ_THROTTLING_VOTE_EN", 23, 23, &umr_bitfield_default },
	 { "GRBM_10_FREQ_THROTTLING_VOTE_EN", 24, 24, &umr_bitfield_default },
	 { "GRBM_11_FREQ_THROTTLING_VOTE_EN", 25, 25, &umr_bitfield_default },
	 { "GRBM_12_FREQ_THROTTLING_VOTE_EN", 26, 26, &umr_bitfield_default },
	 { "GRBM_13_FREQ_THROTTLING_VOTE_EN", 27, 27, &umr_bitfield_default },
	 { "GRBM_14_FREQ_THROTTLING_VOTE_EN", 28, 28, &umr_bitfield_default },
	 { "GRBM_15_FREQ_THROTTLING_VOTE_EN", 29, 29, &umr_bitfield_default },
	 { "RLC_FREQ_THROTTLING_VOTE_EN", 30, 30, &umr_bitfield_default },
	 { "VCE_1_FREQ_THROTTLING_VOTE_EN", 31, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixPCIE_PGFSM_CONFIG[] = {
	 { "FSM_ADDR", 0, 7, &umr_bitfield_default },
	 { "Power_Down", 8, 8, &umr_bitfield_default },
	 { "Power_Up", 9, 9, &umr_bitfield_default },
	 { "P1_Select", 10, 10, &umr_bitfield_default },
	 { "P2_Select", 11, 11, &umr_bitfield_default },
	 { "Write_Op", 12, 12, &umr_bitfield_default },
	 { "Read_Op", 13, 13, &umr_bitfield_default },
	 { "Reserved", 14, 27, &umr_bitfield_default },
	 { "REG_ADDR", 28, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixPCIE_PGFSM_WRITE[] = {
	 { "Write_value", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixSERDES_BUSY[] = {
	 { "PCIE_SERDES_BUSY", 0, 0, &umr_bitfield_default },
};
static struct umr_bitfield ixPCIE_PGFSM2_CONFIG[] = {
	 { "FSM_ADDR", 0, 7, &umr_bitfield_default },
	 { "Power_Down", 8, 8, &umr_bitfield_default },
	 { "Power_Up", 9, 9, &umr_bitfield_default },
	 { "P1_Select", 10, 10, &umr_bitfield_default },
	 { "P2_Select", 11, 11, &umr_bitfield_default },
	 { "Write_Op", 12, 12, &umr_bitfield_default },
	 { "Read_Op", 13, 13, &umr_bitfield_default },
	 { "Reserved", 14, 27, &umr_bitfield_default },
	 { "REG_ADDR", 28, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixPCIE_PGFSM2_WRITE[] = {
	 { "Write_value", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixSERDES2_BUSY[] = {
	 { "PCIE_SERDES_BUSY", 0, 0, &umr_bitfield_default },
};
static struct umr_bitfield ixPCIE_PGFSM_0_READ[] = {
	 { "Read_value", 0, 23, &umr_bitfield_default },
	 { "Read_valid", 24, 24, &umr_bitfield_default },
};
static struct umr_bitfield ixPCIE_PGFSM_1_READ[] = {
	 { "Read_value", 0, 23, &umr_bitfield_default },
	 { "Read_valid", 24, 24, &umr_bitfield_default },
};
static struct umr_bitfield ixPWR_DC_RESP[] = {
	 { "RESPONSE", 0, 0, &umr_bitfield_default },
};
static struct umr_bitfield ixPWR_VCE_RESP[] = {
	 { "RESPONSE", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixPWR_UVD_RESP[] = {
	 { "RESPONSE", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixPWR_ACP_RESP[] = {
	 { "RESPONSE", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixLCLK_DEEP_SLEEP_CNTL2[] = {
	 { "RFE_BUSY_MASK", 0, 0, &umr_bitfield_default },
	 { "BIF_CG_LCLK_BUSY_MASK", 1, 1, &umr_bitfield_default },
	 { "L1IMU_SMU_IDLE_MASK", 2, 2, &umr_bitfield_default },
	 { "RESERVED_BIT3", 3, 3, &umr_bitfield_default },
	 { "SCLK_RUNNING_MASK", 4, 4, &umr_bitfield_default },
	 { "SMU_BUSY_MASK", 5, 5, &umr_bitfield_default },
	 { "PCIE_LCLK_IDLE1_MASK", 6, 6, &umr_bitfield_default },
	 { "PCIE_LCLK_IDLE2_MASK", 7, 7, &umr_bitfield_default },
	 { "PCIE_LCLK_IDLE3_MASK", 8, 8, &umr_bitfield_default },
	 { "PCIE_LCLK_IDLE4_MASK", 9, 9, &umr_bitfield_default },
	 { "L1IMUGPP_IDLE_MASK", 10, 10, &umr_bitfield_default },
	 { "L1IMUGPPSB_IDLE_MASK", 11, 11, &umr_bitfield_default },
	 { "L1IMUBIF_IDLE_MASK", 12, 12, &umr_bitfield_default },
	 { "L1IMUINTGEN_IDLE_MASK", 13, 13, &umr_bitfield_default },
	 { "L2IMU_IDLE_MASK", 14, 14, &umr_bitfield_default },
	 { "ORB_IDLE_MASK", 15, 15, &umr_bitfield_default },
	 { "ON_INB_WAKE_MASK", 16, 16, &umr_bitfield_default },
	 { "ON_INB_WAKE_ACK_MASK", 17, 17, &umr_bitfield_default },
	 { "ON_OUTB_WAKE_MASK", 18, 18, &umr_bitfield_default },
	 { "ON_OUTB_WAKE_ACK_MASK", 19, 19, &umr_bitfield_default },
	 { "DMAACTIVE_MASK", 20, 20, &umr_bitfield_default },
	 { "L1IMUPCIE0_IDLE_MASK", 21, 21, &umr_bitfield_default },
	 { "L1IMUPCIE1_IDLE_MASK", 22, 22, &umr_bitfield_default },
	 { "L1IMUIOAGR_IDLE_MASK", 23, 23, &umr_bitfield_default },
	 { "SPG_SMU_IDLE_MASK", 24, 24, &umr_bitfield_default },
	 { "APG_SMU_IDLE_MASK", 25, 25, &umr_bitfield_default },
	 { "IP_SMU_IDLE0_MASK", 26, 26, &umr_bitfield_default },
	 { "IP_SMU_IDLE1_MASK", 27, 27, &umr_bitfield_default },
	 { "IP_SMU_IDLE2_MASK", 28, 28, &umr_bitfield_default },
	 { "IP_SMU_IDLE3_MASK", 29, 29, &umr_bitfield_default },
	 { "RESERVED", 30, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixPWR_ACPI_INTERRUPT[] = {
	 { "BIF_CG_req", 0, 0, &umr_bitfield_default },
	 { "AZ_CG_req", 1, 1, &umr_bitfield_default },
	 { "AZ_CG_resp", 2, 2, &umr_bitfield_default },
};
static struct umr_bitfield ixPWR_DC_REQ[] = {
	 { "REQUEST", 0, 0, &umr_bitfield_default },
};
static struct umr_bitfield ixVDDGFX_IDLE_PARAMETER[] = {
	 { "VDDGFX_IDLE_THRESHOLD", 0, 15, &umr_bitfield_default },
	 { "VDDGFX_IDLE_THRESHOLD_UNIT", 16, 19, &umr_bitfield_default },
};
static struct umr_bitfield ixVDDGFX_IDLE_CONTROL[] = {
	 { "VDDGFX_IDLE_EN", 0, 0, &umr_bitfield_default },
	 { "VDDGFX_IDLE_DETECT", 1, 1, &umr_bitfield_default },
	 { "FORCE_VDDGFX_IDLE_EXIT", 2, 2, &umr_bitfield_default },
	 { "SMC_VDDGFX_IDLE_STATE", 3, 3, &umr_bitfield_default },
};
static struct umr_bitfield ixVDDGFX_IDLE_EXIT[] = {
	 { "BIF_EXIT_REQ", 0, 0, &umr_bitfield_default },
};
static struct umr_bitfield ixREG_SCLK_DEEP_SLEEP_EXIT[] = {
	 { "REG_sclk_deep_sleep_exit", 0, 0, &umr_bitfield_default },
};
static struct umr_bitfield ixSCLK_MIN_DIV[] = {
	 { "FRACV", 0, 11, &umr_bitfield_default },
	 { "INTV", 12, 18, &umr_bitfield_default },
};
static struct umr_bitfield ixCAC_WEIGHT_LKG_DC_3[] = {
	 { "WEIGHT_LKG_DC_SIG4", 0, 15, &umr_bitfield_default },
	 { "WEIGHT_LKG_DC_SIG5", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixLCAC_MC0_CNTL[] = {
	 { "MC0_ENABLE", 0, 0, &umr_bitfield_default },
	 { "MC0_THRESHOLD", 1, 16, &umr_bitfield_default },
	 { "MC0_BLOCK_ID", 17, 21, &umr_bitfield_default },
	 { "MC0_SIGNAL_ID", 22, 29, &umr_bitfield_default },
};
static struct umr_bitfield ixLCAC_MC0_OVR_SEL[] = {
	 { "MC0_OVR_SEL", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixLCAC_MC0_OVR_VAL[] = {
	 { "MC0_OVR_VAL", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixLCAC_MC1_CNTL[] = {
	 { "MC1_ENABLE", 0, 0, &umr_bitfield_default },
	 { "MC1_THRESHOLD", 1, 16, &umr_bitfield_default },
	 { "MC1_BLOCK_ID", 17, 21, &umr_bitfield_default },
	 { "MC1_SIGNAL_ID", 22, 29, &umr_bitfield_default },
};
static struct umr_bitfield ixLCAC_MC1_OVR_SEL[] = {
	 { "MC1_OVR_SEL", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixLCAC_MC1_OVR_VAL[] = {
	 { "MC1_OVR_VAL", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixLCAC_MC2_CNTL[] = {
	 { "MC2_ENABLE", 0, 0, &umr_bitfield_default },
	 { "MC2_THRESHOLD", 1, 16, &umr_bitfield_default },
	 { "MC2_BLOCK_ID", 17, 21, &umr_bitfield_default },
	 { "MC2_SIGNAL_ID", 22, 29, &umr_bitfield_default },
};
static struct umr_bitfield ixLCAC_MC2_OVR_SEL[] = {
	 { "MC2_OVR_SEL", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixLCAC_MC2_OVR_VAL[] = {
	 { "MC2_OVR_VAL", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixLCAC_MC3_CNTL[] = {
	 { "MC3_ENABLE", 0, 0, &umr_bitfield_default },
	 { "MC3_THRESHOLD", 1, 16, &umr_bitfield_default },
	 { "MC3_BLOCK_ID", 17, 21, &umr_bitfield_default },
	 { "MC3_SIGNAL_ID", 22, 29, &umr_bitfield_default },
};
static struct umr_bitfield ixLCAC_MC3_OVR_SEL[] = {
	 { "MC3_OVR_SEL", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixLCAC_MC3_OVR_VAL[] = {
	 { "MC3_OVR_VAL", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixLCAC_CPL_CNTL[] = {
	 { "CPL_ENABLE", 0, 0, &umr_bitfield_default },
	 { "CPL_THRESHOLD", 1, 16, &umr_bitfield_default },
	 { "CPL_BLOCK_ID", 17, 21, &umr_bitfield_default },
	 { "CPL_SIGNAL_ID", 22, 29, &umr_bitfield_default },
};
static struct umr_bitfield ixLCAC_CPL_OVR_SEL[] = {
	 { "CPL_OVR_SEL", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixLCAC_CPL_OVR_VAL[] = {
	 { "CPL_OVR_VAL", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMISC_UNB_PWRMGT_CFG0[] = {
	 { "TARGET_ADDR", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMISC_UNB_PWRMGT_CFG1[] = {
	 { "TIMER_EN", 0, 0, &umr_bitfield_default },
	 { "TIMER_INTERVAL", 1, 16, &umr_bitfield_default },
	 { "INT_GEN_EN", 17, 17, &umr_bitfield_default },
};
static struct umr_bitfield ixMISC_UNB_PWRMGT_DATA[] = {
	 { "NB_CROSS_TRIGGER", 0, 3, &umr_bitfield_default },
	 { "NB_PRE_SELF_REFRESH", 4, 4, &umr_bitfield_default },
	 { "NB_REQ_NB_PSTATE", 5, 5, &umr_bitfield_default },
	 { "NB_FLUSH_ACK_TOGGLE", 6, 6, &umr_bitfield_default },
	 { "NB_ON_INB_WAKE_ACK", 7, 7, &umr_bitfield_default },
	 { "NB_ON3_CH0LINK_WAKE_ACK", 8, 8, &umr_bitfield_default },
	 { "NB_ON3_CH1LINK_WAKE_ACK", 9, 9, &umr_bitfield_default },
};
static struct umr_bitfield ixGNBPM_SMU_PWRMGT_DATA[] = {
	 { "UNBPM_AllCpusInCC6", 0, 0, &umr_bitfield_default },
	 { "UNBPM_HtcActive", 1, 1, &umr_bitfield_default },
	 { "UNBPM_SmuInt", 2, 2, &umr_bitfield_default },
	 { "UNBPM_SPARE", 3, 7, &umr_bitfield_default },
};
static struct umr_bitfield ixDMA_ACTIVE_SAMPLER_CFG[] = {
	 { "SAMPLING_TIMER_EN", 0, 0, &umr_bitfield_default },
	 { "SAMPLING_TIMER_PERIOD", 1, 16, &umr_bitfield_default },
	 { "DMA_ACTIVE_TRANS_CNT", 17, 18, &umr_bitfield_default },
};
static struct umr_bitfield ixSOUTHBRIDGE_TYPE[] = {
	 { "DISCRETE_SB", 0, 0, &umr_bitfield_default },
};
static struct umr_bitfield ixGNBPM_SMU_PWRMGT_STATUS[] = {
	 { "PM_AllCpusInCC6", 0, 0, &umr_bitfield_default },
	 { "PM_HtcActive", 1, 1, &umr_bitfield_default },
	 { "PM_SmuInt", 2, 2, &umr_bitfield_default },
	 { "PM_SmuIntSuperVminExit", 3, 3, &umr_bitfield_default },
	 { "PM_PreSelfRefresh", 4, 4, &umr_bitfield_default },
	 { "PM_ReqNbPstate", 5, 5, &umr_bitfield_default },
	 { "PM_AllowNbPstate", 6, 6, &umr_bitfield_default },
	 { "PM_AllowSelfRefresh", 7, 7, &umr_bitfield_default },
	 { "PM_IntrWake", 8, 8, &umr_bitfield_default },
	 { "SPARE", 9, 15, &umr_bitfield_default },
};
static struct umr_bitfield ixALLOW_SR_INTR_CTRL[] = {
	 { "ALLOW_SR_INTR_CTRL", 0, 1, &umr_bitfield_default },
};
static struct umr_bitfield ixCURRENT_STATE_CPU0[] = {
	 { "CURRENT_PSTATE_ID", 0, 2, &umr_bitfield_default },
	 { "CURRENT_DID", 3, 5, &umr_bitfield_default },
	 { "CURRENT_FID", 6, 11, &umr_bitfield_default },
	 { "CPU_COF", 12, 23, &umr_bitfield_default },
	 { "CPU_COF_IND_PROG", 24, 30, &umr_bitfield_default },
};
static struct umr_bitfield ixCPU_REDUN_DONE0[] = {
	 { "CPU_REDUN_DONE", 0, 0, &umr_bitfield_default },
};
static struct umr_bitfield ixCURRENT_VID_CPU0[] = {
	 { "CURRENT_VID", 0, 7, &umr_bitfield_default },
};
static struct umr_bitfield ixCURRENT_STATE_CPU1[] = {
	 { "CURRENT_PSTATE_ID", 0, 2, &umr_bitfield_default },
	 { "CURRENT_DID", 3, 5, &umr_bitfield_default },
	 { "CURRENT_FID", 6, 11, &umr_bitfield_default },
	 { "CPU_COF", 12, 23, &umr_bitfield_default },
	 { "CPU_COF_IND_PROG", 24, 30, &umr_bitfield_default },
};
static struct umr_bitfield ixCPU_REDUN_DONE1[] = {
	 { "CPU_REDUN_DONE", 0, 0, &umr_bitfield_default },
};
static struct umr_bitfield ixCURRENT_VID_CPU1[] = {
	 { "CURRENT_VID", 0, 7, &umr_bitfield_default },
};
static struct umr_bitfield ixUNBPM_PWRMGT_ACK[] = {
	 { "REQUESTOR_CODE", 0, 4, &umr_bitfield_default },
	 { "REQUEST_ACK", 8, 8, &umr_bitfield_default },
	 { "REQUEST_NACK", 16, 16, &umr_bitfield_default },
	 { "ERROR_CODE", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixCURRENT_FREQ_STATE_NB[] = {
	 { "CURRENT_FID", 0, 7, &umr_bitfield_default },
	 { "CURRENT_DID", 8, 15, &umr_bitfield_default },
	 { "NB_LOW_POWER", 16, 23, &umr_bitfield_default },
	 { "NB_STUTTER_MODE", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixCURRENT_PSTATE_NB[] = {
	 { "CURRENT_PSTATE_ID", 0, 7, &umr_bitfield_default },
	 { "CURRENT_PSTATE_LO", 8, 8, &umr_bitfield_default },
	 { "CURRENT_MEM_PSTATE_ID", 9, 9, &umr_bitfield_default },
};
static struct umr_bitfield ixUNBPM_MSG_INT_CONFIG[] = {
	 { "MSG_REG_TARGET_ADDR", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixUNBPM_NBPWRMGT_CMD[] = {
	 { "TARGET_BLOCK", 0, 1, &umr_bitfield_default },
	 { "TARGET_CMD", 8, 8, &umr_bitfield_default },
	 { "DCT_SR_MAP", 16, 23, &umr_bitfield_default },
	 { "RETURN_NB_ACK", 24, 24, &umr_bitfield_default },
	 { "OVERRIDE_PARAMS", 25, 25, &umr_bitfield_default },
	 { "SET_NB_LOW_POWER", 26, 26, &umr_bitfield_default },
	 { "SET_NB_STUTTER_MODE", 27, 27, &umr_bitfield_default },
};
static struct umr_bitfield ixUNBPM_NBPWRMGT_FSM_CFG[] = {
	 { "DIS_AUTO_PWRGATE_ON_EXIT", 1, 1, &umr_bitfield_default },
};
static struct umr_bitfield ixDDR0_FUSE_SSB_XFER[] = {
	 { "START_STATUS_XFER", 0, 0, &umr_bitfield_default },
};
static struct umr_bitfield ixDDR0_FUSE_SSB_XFER_CFG[] = {
	 { "FUSE_DDR0_LAST_ADDR", 0, 10, &umr_bitfield_default },
};
static struct umr_bitfield ixDDR1_FUSE_SSB_XFER[] = {
	 { "START_STATUS_XFER", 0, 0, &umr_bitfield_default },
};
static struct umr_bitfield ixDDR1_FUSE_SSB_XFER_CFG[] = {
	 { "FUSE_DDR1_LAST_ADDR", 0, 10, &umr_bitfield_default },
};
static struct umr_bitfield ixUNBPM_FUSES_VAL_PWROK[] = {
	 { "CK_FUSES_VAL_PWROK", 0, 0, &umr_bitfield_default },
};
static struct umr_bitfield ixSYNFIFO_CLK_RATIO[] = {
	 { "CK_CCLK_IS_FASTER0", 0, 0, &umr_bitfield_default },
	 { "CK_CCLK_IS_FASTER1", 1, 1, &umr_bitfield_default },
	 { "CK_NCLK_IS_FASTER0", 2, 2, &umr_bitfield_default },
	 { "CK_NCLK_IS_FASTER1", 3, 3, &umr_bitfield_default },
	 { "CK_SYNFIFO_ASYNC_EN0", 4, 4, &umr_bitfield_default },
	 { "CK_SYNFIFO_ASYNC_EN1", 5, 5, &umr_bitfield_default },
};
static struct umr_bitfield ixMISC_SMU_PWRMGT_CFG0[] = {
	 { "TARGET_ADDR", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMISC_GNB_PWRMGT_CFG1[] = {
	 { "TIMER_EN", 0, 0, &umr_bitfield_default },
	 { "TIMER_INTERVAL", 1, 16, &umr_bitfield_default },
	 { "INT_GEN_EN", 17, 17, &umr_bitfield_default },
};
static struct umr_bitfield ixMISC_SMU_PWRMGT_CFG1[] = {
	 { "TIMER_EN", 0, 0, &umr_bitfield_default },
	 { "TIMER_INTERVAL", 1, 16, &umr_bitfield_default },
	 { "INT_GEN_EN", 17, 17, &umr_bitfield_default },
};
static struct umr_bitfield ixMISC_GNB_PWRMGT_DATA[] = {
	 { "GN_ON_INB_WAKE", 0, 0, &umr_bitfield_default },
	 { "GN_ALLOW_NB_PSTATES", 1, 1, &umr_bitfield_default },
	 { "GN_FLUSH_REQ_TOGGLE", 2, 2, &umr_bitfield_default },
	 { "GN_CROSS_TRIGGER", 3, 6, &umr_bitfield_default },
	 { "GN_STOP_CLOCKS", 7, 7, &umr_bitfield_default },
	 { "GN_ON3_CH0LINK_WAKE", 8, 8, &umr_bitfield_default },
	 { "GN_ON3_CH1LINK_WAKE", 9, 9, &umr_bitfield_default },
};
static struct umr_bitfield ixGN_GNB_SLOW[] = {
	 { "GN_GNB_SLOW_DATA", 0, 0, &umr_bitfield_default },
};
static struct umr_bitfield ixGN_FORCE_NBPS1[] = {
	 { "GN_FORCE_NBPS1_DATA", 0, 0, &umr_bitfield_default },
};
static struct umr_bitfield ixMISC_SMU_PWRMGT_DATA[] = {
	 { "NB_NBPS", 0, 0, &umr_bitfield_default },
	 { "NB_MEMPS", 1, 1, &umr_bitfield_default },
};
static struct umr_bitfield ixNB_COF[] = {
	 { "NB_COF", 0, 15, &umr_bitfield_default },
};
static struct umr_bitfield ixUNBPM_CK_IRESET[] = {
	 { "CK_IRESET_LOCAL", 0, 0, &umr_bitfield_default },
};
static struct umr_bitfield ixCURRENT_VID_NB[] = {
	 { "CURRENT_VID", 0, 7, &umr_bitfield_default },
};
static struct umr_bitfield ixSPR_FUSE_PSTATEPWR1[] = {
	 { "PwrValue0", 0, 7, &umr_bitfield_default },
	 { "PwrValue1", 8, 15, &umr_bitfield_default },
	 { "PwrValue2", 16, 23, &umr_bitfield_default },
	 { "PwrValue3", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixSPR_FUSE_PSTATEPWR2[] = {
	 { "PwrValue4", 0, 7, &umr_bitfield_default },
	 { "PwrDiv0", 8, 9, &umr_bitfield_default },
	 { "PwrDiv1", 10, 11, &umr_bitfield_default },
	 { "PwrDiv2", 12, 13, &umr_bitfield_default },
	 { "PwrDiv3", 14, 15, &umr_bitfield_default },
	 { "PwrDiv4", 16, 17, &umr_bitfield_default },
	 { "PwrDiv5", 18, 19, &umr_bitfield_default },
	 { "PwrDiv6", 20, 21, &umr_bitfield_default },
	 { "PwrDiv7", 22, 23, &umr_bitfield_default },
	 { "Reserved", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixSPR_FUSE_PSTATEPWR3[] = {
	 { "PwrValue5", 0, 7, &umr_bitfield_default },
	 { "PwrValue6", 8, 15, &umr_bitfield_default },
	 { "PwrValue7", 16, 23, &umr_bitfield_default },
	 { "Reserved", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixSPR_FUSE_THERMAL_SCRATCH[] = {
	 { "ThermalScratch", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixSPR_PRODUCT_INFO0[] = {
	 { "BrandId", 0, 15, &umr_bitfield_default },
	 { "Reserved0", 16, 18, &umr_bitfield_default },
	 { "SerialNumRdDis", 19, 19, &umr_bitfield_default },
	 { "Reserved1", 20, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixSPR_SERIALNUM_REG1[] = {
	 { "SPR_SERIALNUM_REG1", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixSPR_SERIALNUM_REG2[] = {
	 { "SPR_SERIALNUM_REG2", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixSPR_PRODUCT_INFO1[] = {
	 { "DiDtMode", 0, 0, &umr_bitfield_default },
	 { "DiDtCfg0", 1, 5, &umr_bitfield_default },
	 { "DiDtCfg1", 6, 13, &umr_bitfield_default },
	 { "DiDtCfg2", 14, 15, &umr_bitfield_default },
	 { "DiDtCfg3", 16, 16, &umr_bitfield_default },
	 { "DiDtCfg4", 17, 20, &umr_bitfield_default },
	 { "Reserved", 21, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixSPR_EXT_PRODUCT_INFO[] = {
	 { "Reserved", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixSPR_MSIDFUSE[] = {
	 { "MSID", 0, 23, &umr_bitfield_default },
	 { "Reserved", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixSPR_LINK_PRODUCT_INFO[] = {
	 { "Reserved", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixSPR_BRAND_NAME_ADDR[] = {
	 { "Index", 0, 3, &umr_bitfield_default },
	 { "Reserved", 4, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixSPR_BRAND_NAME_DATA[] = {
	 { "DATA", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixSPR_COMBO_PHY_PRODUCT_INFO[] = {
	 { "SPR_COMBO_PHY_PRODUCT_INFO", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixMISC_GNB_PWRMGT_CFG0[] = {
	 { "TARGET_ADDR", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixUNBPM_EXIT_TO_PSTATE[] = {
	 { "EXIT_TO_PSTATE", 0, 0, &umr_bitfield_default },
};
static struct umr_bitfield ixUNBPM_WARM_RESET_HS_STATUS[] = {
	 { "NB_CSTATE_ACTIVE", 0, 0, &umr_bitfield_default },
	 { "WARM_RESET_HS_DONE", 1, 1, &umr_bitfield_default },
};
static struct umr_bitfield ixUNBPM_VOLTAGE_CNTL[] = {
	 { "VOLTAGE_EN", 0, 0, &umr_bitfield_default },
	 { "VOLTAGE_LEVEL", 1, 8, &umr_bitfield_default },
};
static struct umr_bitfield ixUNBPM_VOLTAGE_STATUS[] = {
	 { "VOLTAGE_STATUS", 0, 0, &umr_bitfield_default },
	 { "VOLTAGE_CURRENT_LEVEL", 1, 8, &umr_bitfield_default },
};
static struct umr_bitfield ixNUM_BOOST_STATES[] = {
	 { "NUM_BOOST_STATES", 0, 2, &umr_bitfield_default },
};
static struct umr_bitfield ixWARM_RESET_NB_CONTROL[] = {
	 { "WARM_RESET_CPU_VID", 0, 7, &umr_bitfield_default },
	 { "NB_DISABLE_CORE", 8, 15, &umr_bitfield_default },
};
static struct umr_bitfield ixONION_NO_STREAMS_PEND[] = {
	 { "ONION_NO_STREAMS_PEND", 0, 0, &umr_bitfield_default },
	 { "ONION3_NO_STREAMS_PEND_0", 1, 1, &umr_bitfield_default },
	 { "ONION3_NO_STREAMS_PEND_1", 2, 2, &umr_bitfield_default },
};
static struct umr_bitfield ixSPR_PROGRAMMABLE_CTRL[] = {
	 { "PllRegUpTime", 0, 1, &umr_bitfield_default },
	 { "PllVddOutUpTime", 2, 3, &umr_bitfield_default },
	 { "ResonanceTime", 4, 5, &umr_bitfield_default },
	 { "C6PLLPwrDnReg", 6, 6, &umr_bitfield_default },
	 { "CC6PLLPwrDnVCO", 7, 7, &umr_bitfield_default },
	 { "CC6PLLPwrDnReg", 8, 8, &umr_bitfield_default },
	 { "NbPLLPwrDnReg", 9, 9, &umr_bitfield_default },
	 { "SOIWait", 10, 13, &umr_bitfield_default },
};
static struct umr_bitfield ixPHN_FUSERX_MISC_FUSES[] = {
	 { "Spare", 0, 7, &umr_bitfield_default },
	 { "OverClockRefClkDis", 8, 8, &umr_bitfield_default },
	 { "MemPstate", 9, 12, &umr_bitfield_default },
	 { "NbPstateHi", 13, 14, &umr_bitfield_default },
	 { "NbPstateLo", 15, 16, &umr_bitfield_default },
	 { "ScanCLK400MHz", 17, 17, &umr_bitfield_default },
	 { "CoreDis", 18, 21, &umr_bitfield_default },
	 { "PHN_FusesValid", 31, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixUNBPM_PWRCTRL_MISC[] = {
	 { "PWRGATEMASTERDIS", 0, 0, &umr_bitfield_default },
};
static struct umr_bitfield ixCSTATE_ACTIVE_SAMPLER[] = {
	 { "SAMPLE_TIME", 0, 4, &umr_bitfield_default },
};
static struct umr_bitfield ixUNBPM_DEBUG_CONFIG_STATUS[] = {
	 { "AXI_MASTER_QOS", 0, 3, &umr_bitfield_default },
	 { "FIFO_BUFF_FLUSH", 4, 4, &umr_bitfield_default },
	 { "MASTER_DEBUG_EN", 5, 5, &umr_bitfield_default },
	 { "AXI_MASTER_ACTIVE", 8, 8, &umr_bitfield_default },
	 { "AXI_MASTER_BUSY", 9, 9, &umr_bitfield_default },
	 { "FIFO_DATA_COUNT", 10, 13, &umr_bitfield_default },
	 { "MST_OUTSTANDING_TRANS", 16, 23, &umr_bitfield_default },
};
static struct umr_bitfield ixUNBPM_AXIMST_LAST_CMD[] = {
	 { "AXI_MASTER_LAST_CMD", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixUNB_IF_INTRGEN_LAST_SENT[] = {
	 { "GNBPM_LAST_DATA_SENT", 0, 15, &umr_bitfield_default },
	 { "SMUPM_LAST_DATA_SENT", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixUNBPM_DEBUG_BUS_CNTL[] = {
	 { "DEBUG_BUS_LOGGING_EN", 0, 0, &umr_bitfield_default },
	 { "DEBUG_BUS_CYCLE_NUM", 1, 8, &umr_bitfield_default },
};
static struct umr_bitfield ixUNBPM_PWRMGT_REQ_DBG_STATUS[] = {
	 { "NB_PwrMgtReqNb", 0, 0, &umr_bitfield_default },
	 { "NB_PwrMgtReqDct", 1, 2, &umr_bitfield_default },
	 { "NB_PwrMgtReqCpu", 3, 5, &umr_bitfield_default },
	 { "NB_PwrMgtReqCpuPwrTog", 6, 6, &umr_bitfield_default },
	 { "NB_PwrMgtReqNbPstateLo", 7, 7, &umr_bitfield_default },
	 { "NB_PwrMgtReqNbMemPstate", 8, 8, &umr_bitfield_default },
	 { "NB_PwrMgtReqCpuNbFid", 9, 14, &umr_bitfield_default },
	 { "NB_PwrMgtReqDid", 15, 17, &umr_bitfield_default },
	 { "NB_PwrMgtReqPstate", 18, 18, &umr_bitfield_default },
	 { "NB_PwrMgtReqPstateId", 19, 21, &umr_bitfield_default },
	 { "NB_PwrMgtReqGateEn", 22, 22, &umr_bitfield_default },
	 { "NB_PwrMgtReqCpuPrbEn", 23, 23, &umr_bitfield_default },
	 { "NbPwrMgtReqOutstanding", 24, 26, &umr_bitfield_default },
};
static struct umr_bitfield ixUNBPM_VIDCHG_REQ_DBG_STATUS[] = {
	 { "NB_VidChgZeroVid", 0, 0, &umr_bitfield_default },
	 { "NB_VidPlane", 1, 2, &umr_bitfield_default },
	 { "NB_VidChgRamp", 3, 3, &umr_bitfield_default },
	 { "NB_Vid", 4, 11, &umr_bitfield_default },
	 { "NB_VSTime", 12, 14, &umr_bitfield_default },
	 { "CK_VidChgBusy", 16, 16, &umr_bitfield_default },
};
static struct umr_bitfield ixUNBPM_SCRATCH_0[] = {
	 { "DATA", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixUNBPM_SCRATCH_1[] = {
	 { "DATA", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixPOWERON_CPU_0[] = {
	 { "POWERON", 0, 0, &umr_bitfield_default },
};
static struct umr_bitfield ixPOWERREADY_CPU_0[] = {
	 { "POWERREADY", 0, 0, &umr_bitfield_default },
};
static struct umr_bitfield ixPGRUNFEEDBACK_CPU_0[] = {
	 { "PG_RUNFEEDBACK", 0, 0, &umr_bitfield_default },
};
static struct umr_bitfield ixRCC3ON_CPU_0[] = {
	 { "CK_RCC3ON", 0, 0, &umr_bitfield_default },
	 { "RCC3_PSM_EN", 1, 1, &umr_bitfield_default },
	 { "RCC3_PSM_CLK_DIV", 2, 3, &umr_bitfield_default },
	 { "RCC3_AVG_EN", 4, 4, &umr_bitfield_default },
	 { "RCC3_AVG_DIV", 5, 10, &umr_bitfield_default },
	 { "RCC3_DIDT_TIMER", 11, 16, &umr_bitfield_default },
	 { "RCC3_WAKE_MIN_14_0", 17, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixRCC3EXITDONE_CPU_0[] = {
	 { "RCC3EXITDONE", 0, 0, &umr_bitfield_default },
};
static struct umr_bitfield ixCORE_FUNC_LATE_SSB_XFER_0[] = {
	 { "START_STATUS_XFER", 0, 0, &umr_bitfield_default },
};
static struct umr_bitfield ixCORE_FUNC_LATE_SSB_XFER_CFG_0[] = {
	 { "FUSE_FUNC_LAST_ADDR", 0, 10, &umr_bitfield_default },
	 { "FUSE_LATE_LAST_ADDR", 16, 26, &umr_bitfield_default },
};
static struct umr_bitfield ixCORE_REDUN_SSB_XFER_0[] = {
	 { "START_STATUS_XFER", 0, 0, &umr_bitfield_default },
};
static struct umr_bitfield ixCORE_REDUN_SSB_XFER_CFG_0[] = {
	 { "FUSE_REDUN_LAST_ADDR", 0, 10, &umr_bitfield_default },
};
static struct umr_bitfield ixCORE_APM_SSB_XFER_0[] = {
	 { "START_STATUS_XFER", 0, 0, &umr_bitfield_default },
};
static struct umr_bitfield ixCORE_APM_SSB_XFER_CFG_0[] = {
	 { "FUSE_APM_LAST_ADDR", 0, 10, &umr_bitfield_default },
};
static struct umr_bitfield ixCOREPM_PWRCTRL_MISC_0[] = {
	 { "PWRGATEMASTERDIS", 0, 0, &umr_bitfield_default },
};
static struct umr_bitfield ixLDOIVRON_CPU_0[] = {
	 { "CK_LDOIVRON", 0, 0, &umr_bitfield_default },
};
static struct umr_bitfield ixLDOIVREXITDONE_CPU_0[] = {
	 { "LDOIVREXITDONE", 0, 0, &umr_bitfield_default },
};
static struct umr_bitfield ixRCC3_TARGETPSMREF_CPU_0[] = {
	 { "RCC3_TARGETPSMREF", 0, 13, &umr_bitfield_default },
};
static struct umr_bitfield ixIVR_TARGETPSMREF_CPU_0[] = {
	 { "IVR_TARGETPSMREF", 0, 13, &umr_bitfield_default },
};
static struct umr_bitfield ixCK_JTCOOLRESET_LATCHED_CPU_0[] = {
	 { "CK_JTCOOLRESET_LATCHED", 0, 0, &umr_bitfield_default },
};
static struct umr_bitfield ixCK_DISABLECORE_CPU_0[] = {
	 { "CK_DISABLECORE", 0, 0, &umr_bitfield_default },
};
static struct umr_bitfield ixCOREPM_ID_0[] = {
	 { "COREPM_INDEX", 0, 0, &umr_bitfield_default },
};
static struct umr_bitfield ixCOREPM_SCRATCH_0[] = {
	 { "SCRATCH_DATA", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixRCC3_WAKEMIN_CPU_0[] = {
	 { "RCC3_WAKE_MIN_46_15", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixSPMI_CONFIG0_0[] = {
	 { "SPMI_ENABLE", 0, 0, &umr_bitfield_default },
	 { "SPMI_PATH_NUM_TIMING_FLOPS", 2, 6, &umr_bitfield_default },
	 { "SPMI_SIGNALING_DELAY_CYCLES", 7, 11, &umr_bitfield_default },
	 { "SPMI_SIGNALING_HOLD_CYCLES", 12, 16, &umr_bitfield_default },
	 { "SPMI_PATH_ENABLE_DELAY_CYCLES", 17, 21, &umr_bitfield_default },
	 { "SPMI_PATH_DISABLE_DELAY_CYCLES", 22, 26, &umr_bitfield_default },
};
static struct umr_bitfield ixSPMI_CONFIG1_0[] = {
	 { "SPMI_SIGNALING_RESET_HOLD_CYCLES", 0, 4, &umr_bitfield_default },
	 { "SPMI_CHAIN_SIZE", 5, 15, &umr_bitfield_default },
};
static struct umr_bitfield ixSPMI_FSM_READ_TRIGGER_0[] = {
	 { "FSM_READ_TRIGGER", 0, 0, &umr_bitfield_default },
};
static struct umr_bitfield ixSPMI_FSM_WRITE_TRIGGER_0[] = {
	 { "FSM_WRITE_TRIGGER", 0, 0, &umr_bitfield_default },
};
static struct umr_bitfield ixSPMI_FSM_RESET_TRIGGER_0[] = {
	 { "FSM_RESET_TRIGGER", 0, 0, &umr_bitfield_default },
};
static struct umr_bitfield ixSPMI_FSM_BUSY_0[] = {
	 { "FSM_BUSY", 0, 0, &umr_bitfield_default },
};
static struct umr_bitfield ixSPMI_PATH_0[] = {
	 { "PATH_ENABLE_REQ", 0, 0, &umr_bitfield_default },
	 { "PATH_ENABLE_ACK", 1, 1, &umr_bitfield_default },
	 { "PATH_ENABLE_REQ_auto_clear", 4, 4, &umr_bitfield_default },
};
static struct umr_bitfield ixSPMI_C6_STATE_0[] = {
	 { "SPMI_IF_C6_STATE_ENTERED", 0, 0, &umr_bitfield_default },
	 { "SPMI_IF_C6_STATE_ENTERED_WHEN_FSM_BUSY", 1, 1, &umr_bitfield_default },
	 { "SPMI_IF_COUNTER_ADDRESS_C6", 2, 15, &umr_bitfield_default },
};
static struct umr_bitfield ixSPMI_JTAG_OVER_0[] = {
	 { "SPMI_IF_JTAG_OVER_HAPPENED", 0, 0, &umr_bitfield_default },
};
static struct umr_bitfield ixSPMI_SRAM_ADDRESS_0[] = {
	 { "SRAM_ADDRESS", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixSPMI_SRAM_DATA_0[] = {
	 { "SRAM_DATA", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixSPMI_RESET_0[] = {
	 { "ASYNC_RESET_0", 0, 0, &umr_bitfield_default },
	 { "SYNC_RESET", 31, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixSPMI_FORCE_CLOCK_GATERS_0[] = {
	 { "CLOCK_GATER_0_FORCE", 0, 0, &umr_bitfield_default },
	 { "SRAM_CLOCK_GATER_FORCE", 8, 8, &umr_bitfield_default },
};
static struct umr_bitfield ixSPMI_SPARE_0[] = {
	 { "SPARE_DATA", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixSPMI_SPARE_EX_0[] = {
	 { "SPARE_DATA_EX", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixSPMI_SRAM_CLK_GATER_0[] = {
	 { "SRAM_CLK_GATER_EN", 0, 0, &umr_bitfield_default },
	 { "SRAM_CLK_GATER_TIMER", 1, 10, &umr_bitfield_default },
};
static struct umr_bitfield ixPOWERON_CPU_1[] = {
	 { "POWERON", 0, 0, &umr_bitfield_default },
};
static struct umr_bitfield ixPOWERREADY_CPU_1[] = {
	 { "POWERREADY", 0, 0, &umr_bitfield_default },
};
static struct umr_bitfield ixPGRUNFEEDBACK_CPU_1[] = {
	 { "PG_RUNFEEDBACK", 0, 0, &umr_bitfield_default },
};
static struct umr_bitfield ixRCC3ON_CPU_1[] = {
	 { "CK_RCC3ON", 0, 0, &umr_bitfield_default },
	 { "RCC3_PSM_EN", 1, 1, &umr_bitfield_default },
	 { "RCC3_PSM_CLK_DIV", 2, 3, &umr_bitfield_default },
	 { "RCC3_AVG_EN", 4, 4, &umr_bitfield_default },
	 { "RCC3_AVG_DIV", 5, 10, &umr_bitfield_default },
	 { "RCC3_DIDT_TIMER", 11, 16, &umr_bitfield_default },
	 { "RCC3_WAKE_MIN_14_0", 17, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixRCC3EXITDONE_CPU_1[] = {
	 { "RCC3EXITDONE", 0, 0, &umr_bitfield_default },
};
static struct umr_bitfield ixCORE_FUNC_LATE_SSB_XFER_1[] = {
	 { "START_STATUS_XFER", 0, 0, &umr_bitfield_default },
};
static struct umr_bitfield ixCORE_FUNC_LATE_SSB_XFER_CFG_1[] = {
	 { "FUSE_FUNC_LAST_ADDR", 0, 10, &umr_bitfield_default },
	 { "FUSE_LATE_LAST_ADDR", 16, 26, &umr_bitfield_default },
};
static struct umr_bitfield ixCORE_REDUN_SSB_XFER_1[] = {
	 { "START_STATUS_XFER", 0, 0, &umr_bitfield_default },
};
static struct umr_bitfield ixCORE_REDUN_SSB_XFER_CFG_1[] = {
	 { "FUSE_REDUN_LAST_ADDR", 0, 10, &umr_bitfield_default },
};
static struct umr_bitfield ixCORE_APM_SSB_XFER_1[] = {
	 { "START_STATUS_XFER", 0, 0, &umr_bitfield_default },
};
static struct umr_bitfield ixCORE_APM_SSB_XFER_CFG_1[] = {
	 { "FUSE_APM_LAST_ADDR", 0, 10, &umr_bitfield_default },
};
static struct umr_bitfield ixCOREPM_PWRCTRL_MISC_1[] = {
	 { "PWRGATEMASTERDIS", 0, 0, &umr_bitfield_default },
};
static struct umr_bitfield ixLDOIVRON_CPU_1[] = {
	 { "CK_LDOIVRON", 0, 0, &umr_bitfield_default },
};
static struct umr_bitfield ixLDOIVREXITDONE_CPU_1[] = {
	 { "LDOIVREXITDONE", 0, 0, &umr_bitfield_default },
};
static struct umr_bitfield ixRCC3_TARGETPSMREF_CPU_1[] = {
	 { "RCC3_TARGETPSMREF", 0, 13, &umr_bitfield_default },
};
static struct umr_bitfield ixIVR_TARGETPSMREF_CPU_1[] = {
	 { "IVR_TARGETPSMREF", 0, 13, &umr_bitfield_default },
};
static struct umr_bitfield ixCK_JTCOOLRESET_LATCHED_CPU_1[] = {
	 { "CK_JTCOOLRESET_LATCHED", 0, 0, &umr_bitfield_default },
};
static struct umr_bitfield ixCK_DISABLECORE_CPU_1[] = {
	 { "CK_DISABLECORE", 0, 0, &umr_bitfield_default },
};
static struct umr_bitfield ixCOREPM_ID_1[] = {
	 { "COREPM_INDEX", 0, 0, &umr_bitfield_default },
};
static struct umr_bitfield ixCOREPM_SCRATCH_1[] = {
	 { "SCRATCH_DATA", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixRCC3_WAKEMIN_CPU_1[] = {
	 { "RCC3_WAKE_MIN_46_15", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixSPMI_CONFIG0_1[] = {
	 { "SPMI_ENABLE", 0, 0, &umr_bitfield_default },
	 { "SPMI_PATH_NUM_TIMING_FLOPS", 2, 6, &umr_bitfield_default },
	 { "SPMI_SIGNALING_DELAY_CYCLES", 7, 11, &umr_bitfield_default },
	 { "SPMI_SIGNALING_HOLD_CYCLES", 12, 16, &umr_bitfield_default },
	 { "SPMI_PATH_ENABLE_DELAY_CYCLES", 17, 21, &umr_bitfield_default },
	 { "SPMI_PATH_DISABLE_DELAY_CYCLES", 22, 26, &umr_bitfield_default },
};
static struct umr_bitfield ixSPMI_CONFIG1_1[] = {
	 { "SPMI_SIGNALING_RESET_HOLD_CYCLES", 0, 4, &umr_bitfield_default },
	 { "SPMI_CHAIN_SIZE", 5, 15, &umr_bitfield_default },
};
static struct umr_bitfield ixSPMI_FSM_READ_TRIGGER_1[] = {
	 { "FSM_READ_TRIGGER", 0, 0, &umr_bitfield_default },
};
static struct umr_bitfield ixSPMI_FSM_WRITE_TRIGGER_1[] = {
	 { "FSM_WRITE_TRIGGER", 0, 0, &umr_bitfield_default },
};
static struct umr_bitfield ixSPMI_FSM_RESET_TRIGGER_1[] = {
	 { "FSM_RESET_TRIGGER", 0, 0, &umr_bitfield_default },
};
static struct umr_bitfield ixSPMI_FSM_BUSY_1[] = {
	 { "FSM_BUSY", 0, 0, &umr_bitfield_default },
};
static struct umr_bitfield ixSPMI_PATH_1[] = {
	 { "PATH_ENABLE_REQ", 0, 0, &umr_bitfield_default },
	 { "PATH_ENABLE_ACK", 1, 1, &umr_bitfield_default },
	 { "PATH_ENABLE_REQ_auto_clear", 4, 4, &umr_bitfield_default },
};
static struct umr_bitfield ixSPMI_C6_STATE_1[] = {
	 { "SPMI_IF_C6_STATE_ENTERED", 0, 0, &umr_bitfield_default },
	 { "SPMI_IF_C6_STATE_ENTERED_WHEN_FSM_BUSY", 1, 1, &umr_bitfield_default },
	 { "SPMI_IF_COUNTER_ADDRESS_C6", 2, 15, &umr_bitfield_default },
};
static struct umr_bitfield ixSPMI_JTAG_OVER_1[] = {
	 { "SPMI_IF_JTAG_OVER_HAPPENED", 0, 0, &umr_bitfield_default },
};
static struct umr_bitfield ixSPMI_SRAM_ADDRESS_1[] = {
	 { "SRAM_ADDRESS", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixSPMI_SRAM_DATA_1[] = {
	 { "SRAM_DATA", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixSPMI_RESET_1[] = {
	 { "ASYNC_RESET_0", 0, 0, &umr_bitfield_default },
	 { "SYNC_RESET", 31, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixSPMI_FORCE_CLOCK_GATERS_1[] = {
	 { "CLOCK_GATER_0_FORCE", 0, 0, &umr_bitfield_default },
	 { "SRAM_CLOCK_GATER_FORCE", 8, 8, &umr_bitfield_default },
};
static struct umr_bitfield ixSPMI_SPARE_1[] = {
	 { "SPARE_DATA", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixSPMI_SPARE_EX_1[] = {
	 { "SPARE_DATA_EX", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixSPMI_SRAM_CLK_GATER_1[] = {
	 { "SRAM_CLK_GATER_EN", 0, 0, &umr_bitfield_default },
	 { "SRAM_CLK_GATER_TIMER", 1, 10, &umr_bitfield_default },
};
static struct umr_bitfield ixTHM_TCON_HTC[] = {
	 { "HTC_EN", 0, 0, &umr_bitfield_default },
	 { "RSVD0", 1, 1, &umr_bitfield_default },
	 { "HTC_P_STATE_EN", 2, 2, &umr_bitfield_default },
	 { "RSVD1", 3, 3, &umr_bitfield_default },
	 { "HTC_ACTIVE", 4, 4, &umr_bitfield_default },
	 { "HTC_ACTIVE_LOG", 5, 5, &umr_bitfield_default },
	 { "HTC_APIC_HI_EN", 6, 6, &umr_bitfield_default },
	 { "HTC_APIC_LO_EN", 7, 7, &umr_bitfield_default },
	 { "HTC_DIAG", 8, 8, &umr_bitfield_default },
	 { "DIS_PROCHOT_PIN", 9, 9, &umr_bitfield_default },
	 { "HTC_TO_GNB_EN", 10, 10, &umr_bitfield_default },
	 { "PROCHOT_TO_GNB_EN", 11, 11, &umr_bitfield_default },
	 { "RSVD2", 12, 15, &umr_bitfield_default },
	 { "HTC_TMP_LMT", 16, 22, &umr_bitfield_default },
	 { "HTC_SLEW_SEL", 23, 23, &umr_bitfield_default },
	 { "HTC_HYST_LMT", 24, 27, &umr_bitfield_default },
	 { "HTC_PSTATE_LIMIT", 28, 30, &umr_bitfield_default },
};
static struct umr_bitfield ixTHM_TCON_CUR_TMP[] = {
	 { "PER_STEP_TIME_UP", 0, 4, &umr_bitfield_default },
	 { "TMP_MAX_DIFF_UP", 5, 6, &umr_bitfield_default },
	 { "TMP_SLEW_DN_EN", 7, 7, &umr_bitfield_default },
	 { "PER_STEP_TIME_DN", 8, 12, &umr_bitfield_default },
	 { "CUR_TEMP_TJ_SEL", 16, 17, &umr_bitfield_default },
	 { "CUR_TEMP_TJ_SLEW_SEL", 18, 18, &umr_bitfield_default },
	 { "CUR_TEMP_RANGE_SEL", 19, 19, &umr_bitfield_default },
	 { "CUR_TEMP", 21, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixTHM_TCON_THERM_TRIP[] = {
	 { "RSVD0", 0, 0, &umr_bitfield_default },
	 { "THERM_TP", 1, 1, &umr_bitfield_default },
	 { "RSVD1", 2, 2, &umr_bitfield_default },
	 { "THERM_TP_SENSE", 3, 3, &umr_bitfield_default },
	 { "RSVD2", 4, 4, &umr_bitfield_default },
	 { "THERM_TP_EN", 5, 5, &umr_bitfield_default },
	 { "RSVD3", 6, 30, &umr_bitfield_default },
	 { "SW_THERM_TP", 31, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixTHM_GPIO_PROCHOT_CTRL[] = {
	 { "TX12_EN", 0, 0, &umr_bitfield_default },
	 { "PD", 1, 1, &umr_bitfield_default },
	 { "PU", 2, 2, &umr_bitfield_default },
	 { "SCHMEN", 3, 3, &umr_bitfield_default },
	 { "SN", 4, 4, &umr_bitfield_default },
	 { "OE_OVERRIDE", 8, 8, &umr_bitfield_default },
	 { "OE", 9, 9, &umr_bitfield_default },
	 { "A_OVERRIDE", 10, 10, &umr_bitfield_default },
	 { "A", 11, 11, &umr_bitfield_default },
	 { "Y", 12, 12, &umr_bitfield_default },
};
static struct umr_bitfield ixTHM_GPIO_THERMTRIP_CTRL[] = {
	 { "TX12_EN", 0, 0, &umr_bitfield_default },
	 { "PD", 1, 1, &umr_bitfield_default },
	 { "PU", 2, 2, &umr_bitfield_default },
	 { "SCHMEN", 3, 3, &umr_bitfield_default },
	 { "SN", 4, 4, &umr_bitfield_default },
	 { "OE_OVERRIDE", 8, 8, &umr_bitfield_default },
	 { "OE", 9, 9, &umr_bitfield_default },
	 { "A_OVERRIDE", 10, 10, &umr_bitfield_default },
	 { "A", 11, 11, &umr_bitfield_default },
	 { "Y", 12, 12, &umr_bitfield_default },
};
static struct umr_bitfield ixTHM_THERMAL_INT_ENA[] = {
	 { "THERM_INTH_SET", 0, 0, &umr_bitfield_default },
	 { "THERM_INTL_SET", 1, 1, &umr_bitfield_default },
	 { "THERM_TRIGGER_SET", 2, 2, &umr_bitfield_default },
	 { "THERM_INTH_CLR", 3, 3, &umr_bitfield_default },
	 { "THERM_INTL_CLR", 4, 4, &umr_bitfield_default },
	 { "THERM_TRIGGER_CLR", 5, 5, &umr_bitfield_default },
};
static struct umr_bitfield ixTHM_THERMAL_INT_CTRL[] = {
	 { "DIG_THERM_INTH", 0, 7, &umr_bitfield_default },
	 { "DIG_THERM_INTL", 8, 15, &umr_bitfield_default },
	 { "GNB_TEMP_THRESHOLD", 16, 23, &umr_bitfield_default },
	 { "THERM_INTH_MASK", 24, 24, &umr_bitfield_default },
	 { "THERM_INTL_MASK", 25, 25, &umr_bitfield_default },
	 { "THERM_TRIGGER_MASK", 26, 26, &umr_bitfield_default },
	 { "THERM_TRIGGER_CNB_MASK", 27, 27, &umr_bitfield_default },
	 { "THERM_GNB_HW_ENA", 28, 28, &umr_bitfield_default },
};
static struct umr_bitfield ixTHM_THERMAL_INT_STATUS[] = {
	 { "THERM_INTH_DETECT", 0, 0, &umr_bitfield_default },
	 { "THERM_INTL_DETECT", 1, 1, &umr_bitfield_default },
	 { "THERM_TRIGGER_DETECT", 2, 2, &umr_bitfield_default },
	 { "THERM_TRIGGER_CNB_DETECT", 3, 3, &umr_bitfield_default },
};
static struct umr_bitfield ixTHM_TCON_CSR_CONFIG[] = {
	 { "TCC_ADDR", 0, 9, &umr_bitfield_default },
	 { "TCC_READ_OP", 10, 10, &umr_bitfield_default },
};
static struct umr_bitfield ixTHM_TCON_CSR_DATA[] = {
	 { "TCC_DATA", 0, 11, &umr_bitfield_default },
	 { "TCC_REQ_DONE", 12, 12, &umr_bitfield_default },
};
static struct umr_bitfield ixTMON0_RDIL0_DATA[] = {
	 { "TEMP_Z_DATA", 0, 11, &umr_bitfield_default },
};
static struct umr_bitfield ixTMON0_RDIL1_DATA[] = {
	 { "TEMP_Z_DATA", 0, 11, &umr_bitfield_default },
};
static struct umr_bitfield ixTMON0_RDIL2_DATA[] = {
	 { "TEMP_Z_DATA", 0, 11, &umr_bitfield_default },
};
static struct umr_bitfield ixTMON0_RDIL3_DATA[] = {
	 { "TEMP_Z_DATA", 0, 11, &umr_bitfield_default },
};
static struct umr_bitfield ixTMON0_RDIL4_DATA[] = {
	 { "TEMP_Z_DATA", 0, 11, &umr_bitfield_default },
};
static struct umr_bitfield ixTMON0_RDIL5_DATA[] = {
	 { "TEMP_Z_DATA", 0, 11, &umr_bitfield_default },
};
static struct umr_bitfield ixTMON0_RDIL6_DATA[] = {
	 { "TEMP_Z_DATA", 0, 11, &umr_bitfield_default },
};
static struct umr_bitfield ixTMON0_RDIL7_DATA[] = {
	 { "TEMP_Z_DATA", 0, 11, &umr_bitfield_default },
};
static struct umr_bitfield ixTMON0_RDIL8_DATA[] = {
	 { "TEMP_Z_DATA", 0, 11, &umr_bitfield_default },
};
static struct umr_bitfield ixTMON0_RDIL9_DATA[] = {
	 { "TEMP_Z_DATA", 0, 11, &umr_bitfield_default },
};
static struct umr_bitfield ixTMON0_RDIL10_DATA[] = {
	 { "TEMP_Z_DATA", 0, 11, &umr_bitfield_default },
};
static struct umr_bitfield ixTMON0_RDIL11_DATA[] = {
	 { "TEMP_Z_DATA", 0, 11, &umr_bitfield_default },
};
static struct umr_bitfield ixTMON0_RDIL12_DATA[] = {
	 { "TEMP_Z_DATA", 0, 11, &umr_bitfield_default },
};
static struct umr_bitfield ixTMON0_RDIL13_DATA[] = {
	 { "TEMP_Z_DATA", 0, 11, &umr_bitfield_default },
};
static struct umr_bitfield ixTMON0_RDIL14_DATA[] = {
	 { "TEMP_Z_DATA", 0, 11, &umr_bitfield_default },
};
static struct umr_bitfield ixTMON0_RDIL15_DATA[] = {
	 { "TEMP_Z_DATA", 0, 11, &umr_bitfield_default },
};
static struct umr_bitfield ixTMON0_RDIR0_DATA[] = {
	 { "TEMP_Z_DATA", 0, 11, &umr_bitfield_default },
};
static struct umr_bitfield ixTMON0_RDIR1_DATA[] = {
	 { "TEMP_Z_DATA", 0, 11, &umr_bitfield_default },
};
static struct umr_bitfield ixTMON0_RDIR2_DATA[] = {
	 { "TEMP_Z_DATA", 0, 11, &umr_bitfield_default },
};
static struct umr_bitfield ixTMON0_RDIR3_DATA[] = {
	 { "TEMP_Z_DATA", 0, 11, &umr_bitfield_default },
};
static struct umr_bitfield ixTMON0_RDIR4_DATA[] = {
	 { "TEMP_Z_DATA", 0, 11, &umr_bitfield_default },
};
static struct umr_bitfield ixTMON0_RDIR5_DATA[] = {
	 { "TEMP_Z_DATA", 0, 11, &umr_bitfield_default },
};
static struct umr_bitfield ixTMON0_RDIR6_DATA[] = {
	 { "TEMP_Z_DATA", 0, 11, &umr_bitfield_default },
};
static struct umr_bitfield ixTMON0_RDIR7_DATA[] = {
	 { "TEMP_Z_DATA", 0, 11, &umr_bitfield_default },
};
static struct umr_bitfield ixTMON0_RDIR8_DATA[] = {
	 { "TEMP_Z_DATA", 0, 11, &umr_bitfield_default },
};
static struct umr_bitfield ixTMON0_RDIR9_DATA[] = {
	 { "TEMP_Z_DATA", 0, 11, &umr_bitfield_default },
};
static struct umr_bitfield ixTMON0_RDIR10_DATA[] = {
	 { "TEMP_Z_DATA", 0, 11, &umr_bitfield_default },
};
static struct umr_bitfield ixTMON0_RDIR11_DATA[] = {
	 { "TEMP_Z_DATA", 0, 11, &umr_bitfield_default },
};
static struct umr_bitfield ixTMON0_RDIR12_DATA[] = {
	 { "TEMP_Z_DATA", 0, 11, &umr_bitfield_default },
};
static struct umr_bitfield ixTMON0_RDIR13_DATA[] = {
	 { "TEMP_Z_DATA", 0, 11, &umr_bitfield_default },
};
static struct umr_bitfield ixTMON0_RDIR14_DATA[] = {
	 { "TEMP_Z_DATA", 0, 11, &umr_bitfield_default },
};
static struct umr_bitfield ixTMON0_RDIR15_DATA[] = {
	 { "TEMP_Z_DATA", 0, 11, &umr_bitfield_default },
};
static struct umr_bitfield ixTMON0_INT_DATA[] = {
	 { "TEMP_Z_DATA", 0, 11, &umr_bitfield_default },
};
static struct umr_bitfield ixTMON0_RDIL_PRESENT0[] = {
	 { "RDIL_PRESENT_7_0", 0, 7, &umr_bitfield_default },
};
static struct umr_bitfield ixTMON0_RDIL_PRESENT1[] = {
	 { "RDIL_PRESENT_15_8", 0, 7, &umr_bitfield_default },
};
static struct umr_bitfield ixTMON0_RDIR_PRESENT0[] = {
	 { "RDIR_PRESENT_7_0", 0, 7, &umr_bitfield_default },
};
static struct umr_bitfield ixTMON0_RDIR_PRESENT1[] = {
	 { "RDIR_PRESENT_15_8", 0, 7, &umr_bitfield_default },
};
static struct umr_bitfield ixTMON0_CONFIG[] = {
	 { "NUM_ACQ", 0, 2, &umr_bitfield_default },
	 { "FORCE_MAX_ACQ", 3, 3, &umr_bitfield_default },
	 { "RDI_INTERLEAVE", 4, 4, &umr_bitfield_default },
	 { "RE_CALIB_EN", 6, 6, &umr_bitfield_default },
};
static struct umr_bitfield ixTMON0_TEMP_CALC_COEFF0[] = {
	 { "Z", 0, 10, &umr_bitfield_default },
};
static struct umr_bitfield ixTMON0_TEMP_CALC_COEFF1[] = {
	 { "A", 0, 11, &umr_bitfield_default },
};
static struct umr_bitfield ixTMON0_TEMP_CALC_COEFF2[] = {
	 { "B", 0, 5, &umr_bitfield_default },
};
static struct umr_bitfield ixTMON0_TEMP_CALC_COEFF3[] = {
	 { "C", 0, 10, &umr_bitfield_default },
};
static struct umr_bitfield ixTMON0_TEMP_CALC_COEFF4[] = {
	 { "K", 0, 0, &umr_bitfield_default },
};
static struct umr_bitfield ixTMON0_DEBUG0[] = {
	 { "DEBUG_Z", 0, 10, &umr_bitfield_default },
	 { "DEBUG_Z_EN", 11, 11, &umr_bitfield_default },
};
static struct umr_bitfield ixTMON0_DEBUG1[] = {
	 { "DEBUG_RDI", 0, 4, &umr_bitfield_default },
};
static struct umr_bitfield ixTMON1_RDIL0_DATA[] = {
	 { "TEMP_Z_DATA", 0, 11, &umr_bitfield_default },
};
static struct umr_bitfield ixTMON1_RDIL1_DATA[] = {
	 { "TEMP_Z_DATA", 0, 11, &umr_bitfield_default },
};
static struct umr_bitfield ixTMON1_RDIL2_DATA[] = {
	 { "TEMP_Z_DATA", 0, 11, &umr_bitfield_default },
};
static struct umr_bitfield ixTMON1_RDIL3_DATA[] = {
	 { "TEMP_Z_DATA", 0, 11, &umr_bitfield_default },
};
static struct umr_bitfield ixTMON1_RDIL4_DATA[] = {
	 { "TEMP_Z_DATA", 0, 11, &umr_bitfield_default },
};
static struct umr_bitfield ixTMON1_RDIL5_DATA[] = {
	 { "TEMP_Z_DATA", 0, 11, &umr_bitfield_default },
};
static struct umr_bitfield ixTMON1_RDIL6_DATA[] = {
	 { "TEMP_Z_DATA", 0, 11, &umr_bitfield_default },
};
static struct umr_bitfield ixTMON1_RDIL7_DATA[] = {
	 { "TEMP_Z_DATA", 0, 11, &umr_bitfield_default },
};
static struct umr_bitfield ixTMON1_RDIL8_DATA[] = {
	 { "TEMP_Z_DATA", 0, 11, &umr_bitfield_default },
};
static struct umr_bitfield ixTMON1_RDIL9_DATA[] = {
	 { "TEMP_Z_DATA", 0, 11, &umr_bitfield_default },
};
static struct umr_bitfield ixTMON1_RDIL10_DATA[] = {
	 { "TEMP_Z_DATA", 0, 11, &umr_bitfield_default },
};
static struct umr_bitfield ixTMON1_RDIL11_DATA[] = {
	 { "TEMP_Z_DATA", 0, 11, &umr_bitfield_default },
};
static struct umr_bitfield ixTMON1_RDIL12_DATA[] = {
	 { "TEMP_Z_DATA", 0, 11, &umr_bitfield_default },
};
static struct umr_bitfield ixTMON1_RDIL13_DATA[] = {
	 { "TEMP_Z_DATA", 0, 11, &umr_bitfield_default },
};
static struct umr_bitfield ixTMON1_RDIL14_DATA[] = {
	 { "TEMP_Z_DATA", 0, 11, &umr_bitfield_default },
};
static struct umr_bitfield ixTMON1_RDIL15_DATA[] = {
	 { "TEMP_Z_DATA", 0, 11, &umr_bitfield_default },
};
static struct umr_bitfield ixTMON1_RDIR0_DATA[] = {
	 { "TEMP_Z_DATA", 0, 11, &umr_bitfield_default },
};
static struct umr_bitfield ixTMON1_RDIR1_DATA[] = {
	 { "TEMP_Z_DATA", 0, 11, &umr_bitfield_default },
};
static struct umr_bitfield ixTMON1_RDIR2_DATA[] = {
	 { "TEMP_Z_DATA", 0, 11, &umr_bitfield_default },
};
static struct umr_bitfield ixTMON1_RDIR3_DATA[] = {
	 { "TEMP_Z_DATA", 0, 11, &umr_bitfield_default },
};
static struct umr_bitfield ixTMON1_RDIR4_DATA[] = {
	 { "TEMP_Z_DATA", 0, 11, &umr_bitfield_default },
};
static struct umr_bitfield ixTMON1_RDIR5_DATA[] = {
	 { "TEMP_Z_DATA", 0, 11, &umr_bitfield_default },
};
static struct umr_bitfield ixTMON1_RDIR6_DATA[] = {
	 { "TEMP_Z_DATA", 0, 11, &umr_bitfield_default },
};
static struct umr_bitfield ixTMON1_RDIR7_DATA[] = {
	 { "TEMP_Z_DATA", 0, 11, &umr_bitfield_default },
};
static struct umr_bitfield ixTMON1_RDIR8_DATA[] = {
	 { "TEMP_Z_DATA", 0, 11, &umr_bitfield_default },
};
static struct umr_bitfield ixTMON1_RDIR9_DATA[] = {
	 { "TEMP_Z_DATA", 0, 11, &umr_bitfield_default },
};
static struct umr_bitfield ixTMON1_RDIR10_DATA[] = {
	 { "TEMP_Z_DATA", 0, 11, &umr_bitfield_default },
};
static struct umr_bitfield ixTMON1_RDIR11_DATA[] = {
	 { "TEMP_Z_DATA", 0, 11, &umr_bitfield_default },
};
static struct umr_bitfield ixTMON1_RDIR12_DATA[] = {
	 { "TEMP_Z_DATA", 0, 11, &umr_bitfield_default },
};
static struct umr_bitfield ixTMON1_RDIR13_DATA[] = {
	 { "TEMP_Z_DATA", 0, 11, &umr_bitfield_default },
};
static struct umr_bitfield ixTMON1_RDIR14_DATA[] = {
	 { "TEMP_Z_DATA", 0, 11, &umr_bitfield_default },
};
static struct umr_bitfield ixTMON1_RDIR15_DATA[] = {
	 { "TEMP_Z_DATA", 0, 11, &umr_bitfield_default },
};
static struct umr_bitfield ixTMON1_INT_DATA[] = {
	 { "TEMP_Z_DATA", 0, 11, &umr_bitfield_default },
};
static struct umr_bitfield ixTMON1_RDIL_PRESENT0[] = {
	 { "RDIL_PRESENT_7_0", 0, 7, &umr_bitfield_default },
};
static struct umr_bitfield ixTMON1_RDIL_PRESENT1[] = {
	 { "RDIL_PRESENT_15_8", 0, 7, &umr_bitfield_default },
};
static struct umr_bitfield ixTMON1_RDIR_PRESENT0[] = {
	 { "RDIR_PRESENT_7_0", 0, 7, &umr_bitfield_default },
};
static struct umr_bitfield ixTMON1_RDIR_PRESENT1[] = {
	 { "RDIR_PRESENT_15_8", 0, 7, &umr_bitfield_default },
};
static struct umr_bitfield ixTMON1_CONFIG[] = {
	 { "NUM_ACQ", 0, 2, &umr_bitfield_default },
	 { "FORCE_MAX_ACQ", 3, 3, &umr_bitfield_default },
	 { "RDI_INTERLEAVE", 4, 4, &umr_bitfield_default },
	 { "RE_CALIB_EN", 6, 6, &umr_bitfield_default },
};
static struct umr_bitfield ixTMON1_TEMP_CALC_COEFF0[] = {
	 { "Z", 0, 10, &umr_bitfield_default },
};
static struct umr_bitfield ixTMON1_TEMP_CALC_COEFF1[] = {
	 { "A", 0, 11, &umr_bitfield_default },
};
static struct umr_bitfield ixTMON1_TEMP_CALC_COEFF2[] = {
	 { "B", 0, 5, &umr_bitfield_default },
};
static struct umr_bitfield ixTMON1_TEMP_CALC_COEFF3[] = {
	 { "C", 0, 10, &umr_bitfield_default },
};
static struct umr_bitfield ixTMON1_TEMP_CALC_COEFF4[] = {
	 { "K", 0, 0, &umr_bitfield_default },
};
static struct umr_bitfield ixTMON1_DEBUG0[] = {
	 { "DEBUG_Z", 0, 10, &umr_bitfield_default },
	 { "DEBUG_Z_EN", 11, 11, &umr_bitfield_default },
};
static struct umr_bitfield ixTMON1_DEBUG1[] = {
	 { "DEBUG_RDI", 0, 4, &umr_bitfield_default },
};
static struct umr_bitfield ixTHM_TMON0_REMOTE_START[] = {
	 { "DATA", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixTHM_TMON0_REMOTE_END[] = {
	 { "DATA", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixTHM_TMON1_REMOTE_START[] = {
	 { "DATA", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixTHM_TMON1_REMOTE_END[] = {
	 { "DATA", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixTHM_TCON_LOCAL0[] = {
	 { "HaltPolling", 0, 0, &umr_bitfield_default },
	 { "TMON0_PwrDn_Dis", 1, 1, &umr_bitfield_default },
	 { "TMON1_PwrDn_Dis", 2, 2, &umr_bitfield_default },
};
static struct umr_bitfield ixTHM_TCON_LOCAL1[] = {
	 { "PwrDn_Limit_Temp", 0, 2, &umr_bitfield_default },
	 { "PwrDn_DelaySlope", 3, 5, &umr_bitfield_default },
	 { "PwrDn_MinDelay", 6, 8, &umr_bitfield_default },
};
static struct umr_bitfield ixTHM_TCON_LOCAL2[] = {
	 { "PwrDn_MaxDlyMult", 0, 1, &umr_bitfield_default },
	 { "PwrDn_NumSensors", 2, 3, &umr_bitfield_default },
	 { "start_mission_polling", 4, 4, &umr_bitfield_default },
	 { "short_stagger_count", 5, 5, &umr_bitfield_default },
	 { "sbtsi_use_corrected", 6, 6, &umr_bitfield_default },
	 { "csrslave_use_corrected", 7, 7, &umr_bitfield_default },
	 { "smu_use_corrected", 8, 8, &umr_bitfield_default },
	 { "skip_scale_correction", 11, 11, &umr_bitfield_default },
};
static struct umr_bitfield ixTHM_TCON_LOCAL3[] = {
	 { "Global_TMAX", 0, 10, &umr_bitfield_default },
};
static struct umr_bitfield ixTHM_TCON_LOCAL4[] = {
	 { "Global_TMAX_ID", 0, 7, &umr_bitfield_default },
};
static struct umr_bitfield ixTHM_TCON_LOCAL5[] = {
	 { "Global_TMIN", 0, 10, &umr_bitfield_default },
};
static struct umr_bitfield ixTHM_TCON_LOCAL6[] = {
	 { "Global_TMIN_ID", 0, 7, &umr_bitfield_default },
};
static struct umr_bitfield ixTHM_TCON_LOCAL7[] = {
	 { "THERMID", 0, 7, &umr_bitfield_default },
};
static struct umr_bitfield ixTHM_TCON_LOCAL8[] = {
	 { "THERMMAX", 0, 10, &umr_bitfield_default },
};
static struct umr_bitfield ixTHM_TCON_LOCAL9[] = {
	 { "Tj_Max_TMON0", 0, 10, &umr_bitfield_default },
};
static struct umr_bitfield ixTHM_TCON_LOCAL10[] = {
	 { "TMON0_Tj_Max_RS_ID", 0, 3, &umr_bitfield_default },
};
static struct umr_bitfield ixTHM_TCON_LOCAL11[] = {
	 { "Tj_Max_TMON1", 0, 10, &umr_bitfield_default },
};
static struct umr_bitfield ixTHM_TCON_LOCAL12[] = {
	 { "TMON1_Tj_Max_RS_ID", 0, 3, &umr_bitfield_default },
};
static struct umr_bitfield ixTHM_TCON_LOCAL13[] = {
	 { "PowerDownTmon0", 0, 0, &umr_bitfield_default },
	 { "PowerDownTmon1", 1, 1, &umr_bitfield_default },
};
static struct umr_bitfield ixTHM_TCON_LOCAL14[] = {
	 { "boot_done", 0, 0, &umr_bitfield_default },
};
static struct umr_bitfield ixTHM_FUSE0[] = {
	 { "FUSE_TmonRsInterleave", 0, 0, &umr_bitfield_default },
	 { "FUSE_TmonNumAcq", 1, 3, &umr_bitfield_default },
	 { "FUSE_TmonForceMaxAcq", 4, 4, &umr_bitfield_default },
	 { "FUSE_TmonClkDiv", 5, 6, &umr_bitfield_default },
	 { "FUSE_TmonBGAdj1", 7, 14, &umr_bitfield_default },
	 { "FUSE_TmonBGAdj0", 15, 22, &umr_bitfield_default },
	 { "FUSE_TconZtValue", 23, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixTHM_FUSE1[] = {
	 { "FUSE_TconZtValue", 0, 1, &umr_bitfield_default },
	 { "FUSE_TconUseSecondary", 2, 3, &umr_bitfield_default },
	 { "FUSE_TconTmpAdjLoRes", 4, 4, &umr_bitfield_default },
	 { "FUSE_TconPwrUpStaggerTime", 5, 6, &umr_bitfield_default },
	 { "FUSE_TconPwrDnTmpLmt", 7, 9, &umr_bitfield_default },
	 { "FUSE_TconPwrDnNumSensors", 10, 11, &umr_bitfield_default },
	 { "FUSE_TconPwrDnMinDelay", 12, 14, &umr_bitfield_default },
	 { "FUSE_TconPwrDnMaxDelayMult", 15, 16, &umr_bitfield_default },
	 { "FUSE_TconPwrDnDelaySlope", 17, 19, &umr_bitfield_default },
	 { "FUSE_TconKValue", 20, 20, &umr_bitfield_default },
	 { "FUSE_TconDtValue31", 21, 26, &umr_bitfield_default },
	 { "FUSE_TconDtValue30", 27, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixTHM_FUSE2[] = {
	 { "FUSE_TconDtValue30", 0, 0, &umr_bitfield_default },
	 { "FUSE_TconDtValue29", 1, 6, &umr_bitfield_default },
	 { "FUSE_TconDtValue28", 7, 12, &umr_bitfield_default },
	 { "FUSE_TconDtValue27", 13, 18, &umr_bitfield_default },
	 { "FUSE_TconDtValue26", 19, 24, &umr_bitfield_default },
	 { "FUSE_TconDtValue25", 25, 30, &umr_bitfield_default },
	 { "FUSE_TconDtValue24", 31, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixTHM_FUSE3[] = {
	 { "FUSE_TconDtValue24", 0, 4, &umr_bitfield_default },
	 { "FUSE_TconDtValue23", 5, 10, &umr_bitfield_default },
	 { "FUSE_TconDtValue22", 11, 16, &umr_bitfield_default },
	 { "FUSE_TconDtValue21", 17, 22, &umr_bitfield_default },
	 { "FUSE_TconDtValue20", 23, 28, &umr_bitfield_default },
	 { "FUSE_TconDtValue19", 29, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixTHM_FUSE4[] = {
	 { "FUSE_TconDtValue19", 0, 2, &umr_bitfield_default },
	 { "FUSE_TconDtValue18", 3, 8, &umr_bitfield_default },
	 { "FUSE_TconDtValue17", 9, 14, &umr_bitfield_default },
	 { "FUSE_TconDtValue16", 15, 20, &umr_bitfield_default },
	 { "FUSE_TconDtValue15", 21, 26, &umr_bitfield_default },
	 { "FUSE_TconDtValue14", 27, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixTHM_FUSE5[] = {
	 { "FUSE_TconDtValue14", 0, 0, &umr_bitfield_default },
	 { "FUSE_TconDtValue13", 1, 6, &umr_bitfield_default },
	 { "FUSE_TconDtValue12", 7, 12, &umr_bitfield_default },
	 { "FUSE_TconDtValue11", 13, 18, &umr_bitfield_default },
	 { "FUSE_TconDtValue10", 19, 24, &umr_bitfield_default },
	 { "FUSE_TconDtValue9", 25, 30, &umr_bitfield_default },
	 { "FUSE_TconDtValue8", 31, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixTHM_FUSE6[] = {
	 { "FUSE_TconDtValue8", 0, 4, &umr_bitfield_default },
	 { "FUSE_TconDtValue7", 5, 10, &umr_bitfield_default },
	 { "FUSE_TconDtValue6", 11, 16, &umr_bitfield_default },
	 { "FUSE_TconDtValue5", 17, 22, &umr_bitfield_default },
	 { "FUSE_TconDtValue4", 23, 28, &umr_bitfield_default },
	 { "FUSE_TconDtValue3", 29, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixTHM_FUSE7[] = {
	 { "FUSE_TconDtValue3", 0, 2, &umr_bitfield_default },
	 { "FUSE_TconDtValue2", 3, 8, &umr_bitfield_default },
	 { "FUSE_TconDtValue1", 9, 14, &umr_bitfield_default },
	 { "FUSE_TconDtValue0", 15, 20, &umr_bitfield_default },
	 { "FUSE_TconCtValue1", 21, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixTHM_FUSE8[] = {
	 { "FUSE_TconCtValue0", 0, 10, &umr_bitfield_default },
	 { "FUSE_TconBtValue", 11, 16, &umr_bitfield_default },
	 { "FUSE_TconBootDelay", 17, 18, &umr_bitfield_default },
	 { "FUSE_TconAtValue1", 19, 30, &umr_bitfield_default },
	 { "FUSE_TconAtValue0", 31, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixTHM_FUSE9[] = {
	 { "FUSE_TconAtValue0", 0, 10, &umr_bitfield_default },
	 { "FUSE_ThermTripLimit", 11, 18, &umr_bitfield_default },
	 { "FUSE_ThermTripEn", 19, 19, &umr_bitfield_default },
	 { "FUSE_HtcTmpLmt", 20, 26, &umr_bitfield_default },
	 { "FUSE_HtcMsrLock", 27, 27, &umr_bitfield_default },
	 { "FUSE_HtcHystLmt", 28, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixTHM_FUSE10[] = {
	 { "FUSE_HtcDis", 0, 0, &umr_bitfield_default },
	 { "FUSE_HtcClkInact", 1, 3, &umr_bitfield_default },
	 { "FUSE_HtcClkAct", 4, 6, &umr_bitfield_default },
	 { "FUSE_UnusedBits", 7, 31, &umr_bitfield_default },
};
static struct umr_bitfield ixTHM_FUSE11[] = {
	 { "PA_SPARE", 0, 7, &umr_bitfield_default },
};
static struct umr_bitfield ixTHM_FUSE12[] = {
	 { "FusesValid", 0, 0, &umr_bitfield_default },
};
static struct umr_bitfield ixGC_CAC_OVRD_CU[] = {
	 { "OVRRD_SELECT", 0, 15, &umr_bitfield_default },
	 { "OVRRD_VALUE", 16, 31, &umr_bitfield_default },
};