{ "mmMP_SMUIF0_MP0PUB_IND_INDEX", REG_MMIO, 0x180, NULL, 0, 0, 0 },
	{ "mmPWRHW_SMC_IND_INDEX", REG_MMIO, 0x180, &mmPWRHW_SMC_IND_INDEX[0], sizeof(mmPWRHW_SMC_IND_INDEX)/sizeof(mmPWRHW_SMC_IND_INDEX[0]), 0, 0 },
	{ "mmMP0PUB_IND_INDEX_0", REG_MMIO, 0x180, &mmMP0PUB_IND_INDEX_0[0], sizeof(mmMP0PUB_IND_INDEX_0)/sizeof(mmMP0PUB_IND_INDEX_0[0]), 0, 0 },
	{ "mmMP0PUB_IND_INDEX", REG_MMIO, 0x180, &mmMP0PUB_IND_INDEX[0], sizeof(mmMP0PUB_IND_INDEX)/sizeof(mmMP0PUB_IND_INDEX[0]), 0, 0 },
	{ "mmMP_SMUIF0_MP0PUB_IND_DATA", REG_MMIO, 0x181, NULL, 0, 0, 0 },
	{ "mmPWRHW_SMC_IND_DATA", REG_MMIO, 0x181, &mmPWRHW_SMC_IND_DATA[0], sizeof(mmPWRHW_SMC_IND_DATA)/sizeof(mmPWRHW_SMC_IND_DATA[0]), 0, 0 },
	{ "mmMP0PUB_IND_DATA_0", REG_MMIO, 0x181, &mmMP0PUB_IND_DATA_0[0], sizeof(mmMP0PUB_IND_DATA_0)/sizeof(mmMP0PUB_IND_DATA_0[0]), 0, 0 },
	{ "mmMP0PUB_IND_DATA", REG_MMIO, 0x181, &mmMP0PUB_IND_DATA[0], sizeof(mmMP0PUB_IND_DATA)/sizeof(mmMP0PUB_IND_DATA[0]), 0, 0 },
	{ "mmMP_SMUIF1_MP0PUB_IND_INDEX", REG_MMIO, 0x182, NULL, 0, 0, 0 },
	{ "mmMP0PUB_IND_INDEX_1", REG_MMIO, 0x182, &mmMP0PUB_IND_INDEX_1[0], sizeof(mmMP0PUB_IND_INDEX_1)/sizeof(mmMP0PUB_IND_INDEX_1[0]), 0, 0 },
	{ "mmMP_SMUIF1_MP0PUB_IND_DATA", REG_MMIO, 0x183, NULL, 0, 0, 0 },
	{ "mmMP0PUB_IND_DATA_1", REG_MMIO, 0x183, &mmMP0PUB_IND_DATA_1[0], sizeof(mmMP0PUB_IND_DATA_1)/sizeof(mmMP0PUB_IND_DATA_1[0]), 0, 0 },
	{ "mmMP_SMUIF2_MP0PUB_IND_INDEX", REG_MMIO, 0x184, NULL, 0, 0, 0 },
	{ "mmMP0PUB_IND_INDEX_2", REG_MMIO, 0x184, &mmMP0PUB_IND_INDEX_2[0], sizeof(mmMP0PUB_IND_INDEX_2)/sizeof(mmMP0PUB_IND_INDEX_2[0]), 0, 0 },
	{ "mmMP_SMUIF2_MP0PUB_IND_DATA", REG_MMIO, 0x185, NULL, 0, 0, 0 },
	{ "mmMP0PUB_IND_DATA_2", REG_MMIO, 0x185, &mmMP0PUB_IND_DATA_2[0], sizeof(mmMP0PUB_IND_DATA_2)/sizeof(mmMP0PUB_IND_DATA_2[0]), 0, 0 },
	{ "mmMP_SMUIF3_MP0PUB_IND_INDEX", REG_MMIO, 0x186, NULL, 0, 0, 0 },
	{ "mmMP0PUB_IND_INDEX_3", REG_MMIO, 0x186, &mmMP0PUB_IND_INDEX_3[0], sizeof(mmMP0PUB_IND_INDEX_3)/sizeof(mmMP0PUB_IND_INDEX_3[0]), 0, 0 },
	{ "mmMP_SMUIF3_MP0PUB_IND_DATA", REG_MMIO, 0x187, NULL, 0, 0, 0 },
	{ "mmMP0PUB_IND_DATA_3", REG_MMIO, 0x187, &mmMP0PUB_IND_DATA_3[0], sizeof(mmMP0PUB_IND_DATA_3)/sizeof(mmMP0PUB_IND_DATA_3[0]), 0, 0 },
	{ "mmMP_SMUIF4_MP0PUB_IND_INDEX", REG_MMIO, 0x188, NULL, 0, 0, 0 },
	{ "mmMP0PUB_IND_INDEX_4", REG_MMIO, 0x188, &mmMP0PUB_IND_INDEX_4[0], sizeof(mmMP0PUB_IND_INDEX_4)/sizeof(mmMP0PUB_IND_INDEX_4[0]), 0, 0 },
	{ "mmMP_SMUIF4_MP0PUB_IND_DATA", REG_MMIO, 0x189, NULL, 0, 0, 0 },
	{ "mmMP0PUB_IND_DATA_4", REG_MMIO, 0x189, &mmMP0PUB_IND_DATA_4[0], sizeof(mmMP0PUB_IND_DATA_4)/sizeof(mmMP0PUB_IND_DATA_4[0]), 0, 0 },
	{ "mmMP_SMUIF5_MP0PUB_IND_INDEX", REG_MMIO, 0x18a, NULL, 0, 0, 0 },
	{ "mmMP0PUB_IND_INDEX_5", REG_MMIO, 0x18a, &mmMP0PUB_IND_INDEX_5[0], sizeof(mmMP0PUB_IND_INDEX_5)/sizeof(mmMP0PUB_IND_INDEX_5[0]), 0, 0 },
	{ "mmMP_SMUIF5_MP0PUB_IND_DATA", REG_MMIO, 0x18b, NULL, 0, 0, 0 },
	{ "mmMP0PUB_IND_DATA_5", REG_MMIO, 0x18b, &mmMP0PUB_IND_DATA_5[0], sizeof(mmMP0PUB_IND_DATA_5)/sizeof(mmMP0PUB_IND_DATA_5[0]), 0, 0 },
	{ "mmMP_SMUIF6_MP0PUB_IND_INDEX", REG_MMIO, 0x18c, NULL, 0, 0, 0 },
	{ "mmMP0PUB_IND_INDEX_6", REG_MMIO, 0x18c, &mmMP0PUB_IND_INDEX_6[0], sizeof(mmMP0PUB_IND_INDEX_6)/sizeof(mmMP0PUB_IND_INDEX_6[0]), 0, 0 },
	{ "mmMP_SMUIF6_MP0PUB_IND_DATA", REG_MMIO, 0x18d, NULL, 0, 0, 0 },
	{ "mmMP0PUB_IND_DATA_6", REG_MMIO, 0x18d, &mmMP0PUB_IND_DATA_6[0], sizeof(mmMP0PUB_IND_DATA_6)/sizeof(mmMP0PUB_IND_DATA_6[0]), 0, 0 },
	{ "mmMP_SMUIF7_MP0PUB_IND_INDEX", REG_MMIO, 0x18e, NULL, 0, 0, 0 },
	{ "mmMP0PUB_IND_INDEX_7", REG_MMIO, 0x18e, &mmMP0PUB_IND_INDEX_7[0], sizeof(mmMP0PUB_IND_INDEX_7)/sizeof(mmMP0PUB_IND_INDEX_7[0]), 0, 0 },
	{ "mmMP_SMUIF7_MP0PUB_IND_DATA", REG_MMIO, 0x18f, NULL, 0, 0, 0 },
	{ "mmMP0PUB_IND_DATA_7", REG_MMIO, 0x18f, &mmMP0PUB_IND_DATA_7[0], sizeof(mmMP0PUB_IND_DATA_7)/sizeof(mmMP0PUB_IND_DATA_7[0]), 0, 0 },
	{ "mmMP_SMUIF8_MP0PUB_IND_INDEX", REG_MMIO, 0x190, NULL, 0, 0, 0 },
	{ "mmMP0PUB_IND_INDEX_8", REG_MMIO, 0x190, &mmMP0PUB_IND_INDEX_8[0], sizeof(mmMP0PUB_IND_INDEX_8)/sizeof(mmMP0PUB_IND_INDEX_8[0]), 0, 0 },
	{ "mmMP_SMUIF8_MP0PUB_IND_DATA", REG_MMIO, 0x191, NULL, 0, 0, 0 },
	{ "mmMP0PUB_IND_DATA_8", REG_MMIO, 0x191, &mmMP0PUB_IND_DATA_8[0], sizeof(mmMP0PUB_IND_DATA_8)/sizeof(mmMP0PUB_IND_DATA_8[0]), 0, 0 },
	{ "mmMP_SMUIF9_MP0PUB_IND_INDEX", REG_MMIO, 0x192, NULL, 0, 0, 0 },
	{ "mmMP0PUB_IND_INDEX_9", REG_MMIO, 0x192, &mmMP0PUB_IND_INDEX_9[0], sizeof(mmMP0PUB_IND_INDEX_9)/sizeof(mmMP0PUB_IND_INDEX_9[0]), 0, 0 },
	{ "mmMP_SMUIF9_MP0PUB_IND_DATA", REG_MMIO, 0x193, NULL, 0, 0, 0 },
	{ "mmMP0PUB_IND_DATA_9", REG_MMIO, 0x193, &mmMP0PUB_IND_DATA_9[0], sizeof(mmMP0PUB_IND_DATA_9)/sizeof(mmMP0PUB_IND_DATA_9[0]), 0, 0 },
	{ "mmMP_SMUIF10_MP0PUB_IND_INDEX", REG_MMIO, 0x194, NULL, 0, 0, 0 },
	{ "mmMP0PUB_IND_INDEX_10", REG_MMIO, 0x194, &mmMP0PUB_IND_INDEX_10[0], sizeof(mmMP0PUB_IND_INDEX_10)/sizeof(mmMP0PUB_IND_INDEX_10[0]), 0, 0 },
	{ "mmMP_SMUIF10_MP0PUB_IND_DATA", REG_MMIO, 0x195, NULL, 0, 0, 0 },
	{ "mmMP0PUB_IND_DATA_10", REG_MMIO, 0x195, &mmMP0PUB_IND_DATA_10[0], sizeof(mmMP0PUB_IND_DATA_10)/sizeof(mmMP0PUB_IND_DATA_10[0]), 0, 0 },
	{ "mmMP_SMUIF11_MP0PUB_IND_INDEX", REG_MMIO, 0x196, NULL, 0, 0, 0 },
	{ "mmMP0PUB_IND_INDEX_11", REG_MMIO, 0x196, &mmMP0PUB_IND_INDEX_11[0], sizeof(mmMP0PUB_IND_INDEX_11)/sizeof(mmMP0PUB_IND_INDEX_11[0]), 0, 0 },
	{ "mmMP_SMUIF11_MP0PUB_IND_DATA", REG_MMIO, 0x197, NULL, 0, 0, 0 },
	{ "mmMP0PUB_IND_DATA_11", REG_MMIO, 0x197, &mmMP0PUB_IND_DATA_11[0], sizeof(mmMP0PUB_IND_DATA_11)/sizeof(mmMP0PUB_IND_DATA_11[0]), 0, 0 },
	{ "mmMP_SMUIF12_MP0PUB_IND_INDEX", REG_MMIO, 0x198, NULL, 0, 0, 0 },
	{ "mmMP0PUB_IND_INDEX_12", REG_MMIO, 0x198, &mmMP0PUB_IND_INDEX_12[0], sizeof(mmMP0PUB_IND_INDEX_12)/sizeof(mmMP0PUB_IND_INDEX_12[0]), 0, 0 },
	{ "mmMP_SMUIF12_MP0PUB_IND_DATA", REG_MMIO, 0x199, NULL, 0, 0, 0 },
	{ "mmMP0PUB_IND_DATA_12", REG_MMIO, 0x199, &mmMP0PUB_IND_DATA_12[0], sizeof(mmMP0PUB_IND_DATA_12)/sizeof(mmMP0PUB_IND_DATA_12[0]), 0, 0 },
	{ "mmMP_SMUIF13_MP0PUB_IND_INDEX", REG_MMIO, 0x19a, NULL, 0, 0, 0 },
	{ "mmMP0PUB_IND_INDEX_13", REG_MMIO, 0x19a, &mmMP0PUB_IND_INDEX_13[0], sizeof(mmMP0PUB_IND_INDEX_13)/sizeof(mmMP0PUB_IND_INDEX_13[0]), 0, 0 },
	{ "mmMP_SMUIF13_MP0PUB_IND_DATA", REG_MMIO, 0x19b, NULL, 0, 0, 0 },
	{ "mmMP0PUB_IND_DATA_13", REG_MMIO, 0x19b, &mmMP0PUB_IND_DATA_13[0], sizeof(mmMP0PUB_IND_DATA_13)/sizeof(mmMP0PUB_IND_DATA_13[0]), 0, 0 },
	{ "mmMP_SMUIF14_MP0PUB_IND_INDEX", REG_MMIO, 0x19c, NULL, 0, 0, 0 },
	{ "mmMP0PUB_IND_INDEX_14", REG_MMIO, 0x19c, &mmMP0PUB_IND_INDEX_14[0], sizeof(mmMP0PUB_IND_INDEX_14)/sizeof(mmMP0PUB_IND_INDEX_14[0]), 0, 0 },
	{ "mmMP_SMUIF14_MP0PUB_IND_DATA", REG_MMIO, 0x19d, NULL, 0, 0, 0 },
	{ "mmMP0PUB_IND_DATA_14", REG_MMIO, 0x19d, &mmMP0PUB_IND_DATA_14[0], sizeof(mmMP0PUB_IND_DATA_14)/sizeof(mmMP0PUB_IND_DATA_14[0]), 0, 0 },
	{ "mmMP_SMUIF15_MP0PUB_IND_INDEX", REG_MMIO, 0x19e, NULL, 0, 0, 0 },
	{ "mmMP0PUB_IND_INDEX_15", REG_MMIO, 0x19e, &mmMP0PUB_IND_INDEX_15[0], sizeof(mmMP0PUB_IND_INDEX_15)/sizeof(mmMP0PUB_IND_INDEX_15[0]), 0, 0 },
	{ "mmMP_SMUIF15_MP0PUB_IND_DATA", REG_MMIO, 0x19f, NULL, 0, 0, 0 },
	{ "mmMP0PUB_IND_DATA_15", REG_MMIO, 0x19f, &mmMP0PUB_IND_DATA_15[0], sizeof(mmMP0PUB_IND_DATA_15)/sizeof(mmMP0PUB_IND_DATA_15[0]), 0, 0 },
	{ "mmMP0_IND_ACCESS_CNTL", REG_MMIO, 0x1a0, &mmMP0_IND_ACCESS_CNTL[0], sizeof(mmMP0_IND_ACCESS_CNTL)/sizeof(mmMP0_IND_ACCESS_CNTL[0]), 0, 0 },
	{ "mmMP0_MSP_MESSAGE_0", REG_MMIO, 0x1a1, &mmMP0_MSP_MESSAGE_0[0], sizeof(mmMP0_MSP_MESSAGE_0)/sizeof(mmMP0_MSP_MESSAGE_0[0]), 0, 0 },
	{ "mmMP0_MSP_MESSAGE_1", REG_MMIO, 0x1a2, &mmMP0_MSP_MESSAGE_1[0], sizeof(mmMP0_MSP_MESSAGE_1)/sizeof(mmMP0_MSP_MESSAGE_1[0]), 0, 0 },
	{ "mmMP0_MSP_MESSAGE_2", REG_MMIO, 0x1a3, &mmMP0_MSP_MESSAGE_2[0], sizeof(mmMP0_MSP_MESSAGE_2)/sizeof(mmMP0_MSP_MESSAGE_2[0]), 0, 0 },
	{ "mmMP0_MSP_MESSAGE_3", REG_MMIO, 0x1a4, &mmMP0_MSP_MESSAGE_3[0], sizeof(mmMP0_MSP_MESSAGE_3)/sizeof(mmMP0_MSP_MESSAGE_3[0]), 0, 0 },
	{ "mmMP0_MSP_MESSAGE_4", REG_MMIO, 0x1a5, &mmMP0_MSP_MESSAGE_4[0], sizeof(mmMP0_MSP_MESSAGE_4)/sizeof(mmMP0_MSP_MESSAGE_4[0]), 0, 0 },
	{ "mmMP0_MSP_MESSAGE_5", REG_MMIO, 0x1a6, &mmMP0_MSP_MESSAGE_5[0], sizeof(mmMP0_MSP_MESSAGE_5)/sizeof(mmMP0_MSP_MESSAGE_5[0]), 0, 0 },
	{ "mmMP0_MSP_MESSAGE_6", REG_MMIO, 0x1a7, &mmMP0_MSP_MESSAGE_6[0], sizeof(mmMP0_MSP_MESSAGE_6)/sizeof(mmMP0_MSP_MESSAGE_6[0]), 0, 0 },
	{ "mmMP0_MSP_MESSAGE_7", REG_MMIO, 0x1a8, &mmMP0_MSP_MESSAGE_7[0], sizeof(mmMP0_MSP_MESSAGE_7)/sizeof(mmMP0_MSP_MESSAGE_7[0]), 0, 0 },
	{ "mmSAM_IH_EXT_ERR_INTR", REG_MMIO, 0x1a9, &mmSAM_IH_EXT_ERR_INTR[0], sizeof(mmSAM_IH_EXT_ERR_INTR)/sizeof(mmSAM_IH_EXT_ERR_INTR[0]), 0, 0 },
	{ "mmSAM_IH_EXT_ERR_INTR_STATUS", REG_MMIO, 0x1aa, &mmSAM_IH_EXT_ERR_INTR_STATUS[0], sizeof(mmSAM_IH_EXT_ERR_INTR_STATUS)/sizeof(mmSAM_IH_EXT_ERR_INTR_STATUS[0]), 0, 0 },
	{ "mmMP0_DISP_TIMER0_CTRL0", REG_MMIO, 0x1ab, &mmMP0_DISP_TIMER0_CTRL0[0], sizeof(mmMP0_DISP_TIMER0_CTRL0)/sizeof(mmMP0_DISP_TIMER0_CTRL0[0]), 0, 0 },
	{ "mmMP0_DISP_TIMER0_CTRL1", REG_MMIO, 0x1ac, &mmMP0_DISP_TIMER0_CTRL1[0], sizeof(mmMP0_DISP_TIMER0_CTRL1)/sizeof(mmMP0_DISP_TIMER0_CTRL1[0]), 0, 0 },
	{ "mmMP0_DISP_TIMER0_CMP_AUTOINC", REG_MMIO, 0x1ad, &mmMP0_DISP_TIMER0_CMP_AUTOINC[0], sizeof(mmMP0_DISP_TIMER0_CMP_AUTOINC)/sizeof(mmMP0_DISP_TIMER0_CMP_AUTOINC[0]), 0, 0 },
	{ "mmMP0_DISP_TIMER0_INTEN", REG_MMIO, 0x1ae, &mmMP0_DISP_TIMER0_INTEN[0], sizeof(mmMP0_DISP_TIMER0_INTEN)/sizeof(mmMP0_DISP_TIMER0_INTEN[0]), 0, 0 },
	{ "mmMP0_DISP_TIMER0_OCMP_0_0", REG_MMIO, 0x1af, &mmMP0_DISP_TIMER0_OCMP_0_0[0], sizeof(mmMP0_DISP_TIMER0_OCMP_0_0)/sizeof(mmMP0_DISP_TIMER0_OCMP_0_0[0]), 0, 0 },
	{ "mmMP0_DISP_TIMER0_OCMP_0_1", REG_MMIO, 0x1b0, &mmMP0_DISP_TIMER0_OCMP_0_1[0], sizeof(mmMP0_DISP_TIMER0_OCMP_0_1)/sizeof(mmMP0_DISP_TIMER0_OCMP_0_1[0]), 0, 0 },
	{ "mmMP0_DISP_TIMER0_CNT", REG_MMIO, 0x1b1, &mmMP0_DISP_TIMER0_CNT[0], sizeof(mmMP0_DISP_TIMER0_CNT)/sizeof(mmMP0_DISP_TIMER0_CNT[0]), 0, 0 },
	{ "mmMP0_DISP_TIMER1_CTRL0", REG_MMIO, 0x1b2, &mmMP0_DISP_TIMER1_CTRL0[0], sizeof(mmMP0_DISP_TIMER1_CTRL0)/sizeof(mmMP0_DISP_TIMER1_CTRL0[0]), 0, 0 },
	{ "mmMP0_DISP_TIMER1_CTRL1", REG_MMIO, 0x1b3, &mmMP0_DISP_TIMER1_CTRL1[0], sizeof(mmMP0_DISP_TIMER1_CTRL1)/sizeof(mmMP0_DISP_TIMER1_CTRL1[0]), 0, 0 },
	{ "mmMP0_DISP_TIMER1_CMP_AUTOINC", REG_MMIO, 0x1b4, &mmMP0_DISP_TIMER1_CMP_AUTOINC[0], sizeof(mmMP0_DISP_TIMER1_CMP_AUTOINC)/sizeof(mmMP0_DISP_TIMER1_CMP_AUTOINC[0]), 0, 0 },
	{ "mmMP0_DISP_TIMER1_INTEN", REG_MMIO, 0x1b5, &mmMP0_DISP_TIMER1_INTEN[0], sizeof(mmMP0_DISP_TIMER1_INTEN)/sizeof(mmMP0_DISP_TIMER1_INTEN[0]), 0, 0 },
	{ "mmMP0_DISP_TIMER1_OCMP_0_0", REG_MMIO, 0x1b6, &mmMP0_DISP_TIMER1_OCMP_0_0[0], sizeof(mmMP0_DISP_TIMER1_OCMP_0_0)/sizeof(mmMP0_DISP_TIMER1_OCMP_0_0[0]), 0, 0 },
	{ "mmMP0_DISP_TIMER1_OCMP_0_1", REG_MMIO, 0x1b7, &mmMP0_DISP_TIMER1_OCMP_0_1[0], sizeof(mmMP0_DISP_TIMER1_OCMP_0_1)/sizeof(mmMP0_DISP_TIMER1_OCMP_0_1[0]), 0, 0 },
	{ "mmMP0_DISP_TIMER1_CNT", REG_MMIO, 0x1b8, &mmMP0_DISP_TIMER1_CNT[0], sizeof(mmMP0_DISP_TIMER1_CNT)/sizeof(mmMP0_DISP_TIMER1_CNT[0]), 0, 0 },
	{ "mmSMU_MP1_SRBM2P_MSG_0", REG_MMIO, 0x1c0, &mmSMU_MP1_SRBM2P_MSG_0[0], sizeof(mmSMU_MP1_SRBM2P_MSG_0)/sizeof(mmSMU_MP1_SRBM2P_MSG_0[0]), 0, 0 },
	{ "mmSMU_MP1_SRBM2P_MSG_1", REG_MMIO, 0x1c1, &mmSMU_MP1_SRBM2P_MSG_1[0], sizeof(mmSMU_MP1_SRBM2P_MSG_1)/sizeof(mmSMU_MP1_SRBM2P_MSG_1[0]), 0, 0 },
	{ "mmSMU_MP1_SRBM2P_MSG_2", REG_MMIO, 0x1c2, &mmSMU_MP1_SRBM2P_MSG_2[0], sizeof(mmSMU_MP1_SRBM2P_MSG_2)/sizeof(mmSMU_MP1_SRBM2P_MSG_2[0]), 0, 0 },
	{ "mmSMU_MP1_SRBM2P_MSG_3", REG_MMIO, 0x1c3, &mmSMU_MP1_SRBM2P_MSG_3[0], sizeof(mmSMU_MP1_SRBM2P_MSG_3)/sizeof(mmSMU_MP1_SRBM2P_MSG_3[0]), 0, 0 },
	{ "mmSMU_MP1_SRBM2P_MSG_4", REG_MMIO, 0x1c4, &mmSMU_MP1_SRBM2P_MSG_4[0], sizeof(mmSMU_MP1_SRBM2P_MSG_4)/sizeof(mmSMU_MP1_SRBM2P_MSG_4[0]), 0, 0 },
	{ "mmSMU_MP1_SRBM2P_MSG_5", REG_MMIO, 0x1c5, &mmSMU_MP1_SRBM2P_MSG_5[0], sizeof(mmSMU_MP1_SRBM2P_MSG_5)/sizeof(mmSMU_MP1_SRBM2P_MSG_5[0]), 0, 0 },
	{ "mmSMU_MP1_SRBM2P_MSG_6", REG_MMIO, 0x1c6, &mmSMU_MP1_SRBM2P_MSG_6[0], sizeof(mmSMU_MP1_SRBM2P_MSG_6)/sizeof(mmSMU_MP1_SRBM2P_MSG_6[0]), 0, 0 },
	{ "mmSMU_MP1_SRBM2P_MSG_7", REG_MMIO, 0x1c7, &mmSMU_MP1_SRBM2P_MSG_7[0], sizeof(mmSMU_MP1_SRBM2P_MSG_7)/sizeof(mmSMU_MP1_SRBM2P_MSG_7[0]), 0, 0 },
	{ "mmSMU_MP1_SRBM2P_MSG_8", REG_MMIO, 0x1c8, &mmSMU_MP1_SRBM2P_MSG_8[0], sizeof(mmSMU_MP1_SRBM2P_MSG_8)/sizeof(mmSMU_MP1_SRBM2P_MSG_8[0]), 0, 0 },
	{ "mmSMU_MP1_SRBM2P_MSG_9", REG_MMIO, 0x1c9, &mmSMU_MP1_SRBM2P_MSG_9[0], sizeof(mmSMU_MP1_SRBM2P_MSG_9)/sizeof(mmSMU_MP1_SRBM2P_MSG_9[0]), 0, 0 },
	{ "mmSMU_MP1_SRBM2P_MSG_10", REG_MMIO, 0x1ca, &mmSMU_MP1_SRBM2P_MSG_10[0], sizeof(mmSMU_MP1_SRBM2P_MSG_10)/sizeof(mmSMU_MP1_SRBM2P_MSG_10[0]), 0, 0 },
	{ "mmSMU_MP1_SRBM2P_MSG_11", REG_MMIO, 0x1cb, &mmSMU_MP1_SRBM2P_MSG_11[0], sizeof(mmSMU_MP1_SRBM2P_MSG_11)/sizeof(mmSMU_MP1_SRBM2P_MSG_11[0]), 0, 0 },
	{ "mmSMU_MP1_SRBM2P_MSG_12", REG_MMIO, 0x1cc, &mmSMU_MP1_SRBM2P_MSG_12[0], sizeof(mmSMU_MP1_SRBM2P_MSG_12)/sizeof(mmSMU_MP1_SRBM2P_MSG_12[0]), 0, 0 },
	{ "mmSMU_MP1_SRBM2P_MSG_13", REG_MMIO, 0x1cd, &mmSMU_MP1_SRBM2P_MSG_13[0], sizeof(mmSMU_MP1_SRBM2P_MSG_13)/sizeof(mmSMU_MP1_SRBM2P_MSG_13[0]), 0, 0 },
	{ "mmSMU_MP1_SRBM2P_MSG_14", REG_MMIO, 0x1ce, &mmSMU_MP1_SRBM2P_MSG_14[0], sizeof(mmSMU_MP1_SRBM2P_MSG_14)/sizeof(mmSMU_MP1_SRBM2P_MSG_14[0]), 0, 0 },
	{ "mmSMU_MP1_SRBM2P_MSG_15", REG_MMIO, 0x1cf, &mmSMU_MP1_SRBM2P_MSG_15[0], sizeof(mmSMU_MP1_SRBM2P_MSG_15)/sizeof(mmSMU_MP1_SRBM2P_MSG_15[0]), 0, 0 },
	{ "mmSMU_MP1_SRBM2P_RESP_0", REG_MMIO, 0x1d0, &mmSMU_MP1_SRBM2P_RESP_0[0], sizeof(mmSMU_MP1_SRBM2P_RESP_0)/sizeof(mmSMU_MP1_SRBM2P_RESP_0[0]), 0, 0 },
	{ "mmSMU_MP1_SRBM2P_RESP_1", REG_MMIO, 0x1d1, &mmSMU_MP1_SRBM2P_RESP_1[0], sizeof(mmSMU_MP1_SRBM2P_RESP_1)/sizeof(mmSMU_MP1_SRBM2P_RESP_1[0]), 0, 0 },
	{ "mmSMU_MP1_SRBM2P_RESP_2", REG_MMIO, 0x1d2, &mmSMU_MP1_SRBM2P_RESP_2[0], sizeof(mmSMU_MP1_SRBM2P_RESP_2)/sizeof(mmSMU_MP1_SRBM2P_RESP_2[0]), 0, 0 },
	{ "mmSMU_MP1_SRBM2P_RESP_3", REG_MMIO, 0x1d3, &mmSMU_MP1_SRBM2P_RESP_3[0], sizeof(mmSMU_MP1_SRBM2P_RESP_3)/sizeof(mmSMU_MP1_SRBM2P_RESP_3[0]), 0, 0 },
	{ "mmSMU_MP1_SRBM2P_RESP_4", REG_MMIO, 0x1d4, &mmSMU_MP1_SRBM2P_RESP_4[0], sizeof(mmSMU_MP1_SRBM2P_RESP_4)/sizeof(mmSMU_MP1_SRBM2P_RESP_4[0]), 0, 0 },
	{ "mmSMU_MP1_SRBM2P_RESP_5", REG_MMIO, 0x1d5, &mmSMU_MP1_SRBM2P_RESP_5[0], sizeof(mmSMU_MP1_SRBM2P_RESP_5)/sizeof(mmSMU_MP1_SRBM2P_RESP_5[0]), 0, 0 },
	{ "mmSMU_MP1_SRBM2P_RESP_6", REG_MMIO, 0x1d6, &mmSMU_MP1_SRBM2P_RESP_6[0], sizeof(mmSMU_MP1_SRBM2P_RESP_6)/sizeof(mmSMU_MP1_SRBM2P_RESP_6[0]), 0, 0 },
	{ "mmSMU_MP1_SRBM2P_RESP_7", REG_MMIO, 0x1d7, &mmSMU_MP1_SRBM2P_RESP_7[0], sizeof(mmSMU_MP1_SRBM2P_RESP_7)/sizeof(mmSMU_MP1_SRBM2P_RESP_7[0]), 0, 0 },
	{ "mmSMU_MP1_SRBM2P_RESP_8", REG_MMIO, 0x1d8, &mmSMU_MP1_SRBM2P_RESP_8[0], sizeof(mmSMU_MP1_SRBM2P_RESP_8)/sizeof(mmSMU_MP1_SRBM2P_RESP_8[0]), 0, 0 },
	{ "mmSMU_MP1_SRBM2P_RESP_9", REG_MMIO, 0x1d9, &mmSMU_MP1_SRBM2P_RESP_9[0], sizeof(mmSMU_MP1_SRBM2P_RESP_9)/sizeof(mmSMU_MP1_SRBM2P_RESP_9[0]), 0, 0 },
	{ "mmSMU_MP1_SRBM2P_RESP_10", REG_MMIO, 0x1da, &mmSMU_MP1_SRBM2P_RESP_10[0], sizeof(mmSMU_MP1_SRBM2P_RESP_10)/sizeof(mmSMU_MP1_SRBM2P_RESP_10[0]), 0, 0 },
	{ "mmSMU_MP1_SRBM2P_RESP_11", REG_MMIO, 0x1db, &mmSMU_MP1_SRBM2P_RESP_11[0], sizeof(mmSMU_MP1_SRBM2P_RESP_11)/sizeof(mmSMU_MP1_SRBM2P_RESP_11[0]), 0, 0 },
	{ "mmSMU_MP1_SRBM2P_RESP_12", REG_MMIO, 0x1dc, &mmSMU_MP1_SRBM2P_RESP_12[0], sizeof(mmSMU_MP1_SRBM2P_RESP_12)/sizeof(mmSMU_MP1_SRBM2P_RESP_12[0]), 0, 0 },
	{ "mmSMU_MP1_SRBM2P_RESP_13", REG_MMIO, 0x1dd, &mmSMU_MP1_SRBM2P_RESP_13[0], sizeof(mmSMU_MP1_SRBM2P_RESP_13)/sizeof(mmSMU_MP1_SRBM2P_RESP_13[0]), 0, 0 },
	{ "mmSMU_MP1_SRBM2P_RESP_14", REG_MMIO, 0x1de, &mmSMU_MP1_SRBM2P_RESP_14[0], sizeof(mmSMU_MP1_SRBM2P_RESP_14)/sizeof(mmSMU_MP1_SRBM2P_RESP_14[0]), 0, 0 },
	{ "mmSMU_MP1_SRBM2P_RESP_15", REG_MMIO, 0x1df, &mmSMU_MP1_SRBM2P_RESP_15[0], sizeof(mmSMU_MP1_SRBM2P_RESP_15)/sizeof(mmSMU_MP1_SRBM2P_RESP_15[0]), 0, 0 },
	{ "mmSMU_MP1_SRBM2P_ARG_0", REG_MMIO, 0x1e0, &mmSMU_MP1_SRBM2P_ARG_0[0], sizeof(mmSMU_MP1_SRBM2P_ARG_0)/sizeof(mmSMU_MP1_SRBM2P_ARG_0[0]), 0, 0 },
	{ "mmSMU_MP1_SRBM2P_ARG_1", REG_MMIO, 0x1e1, &mmSMU_MP1_SRBM2P_ARG_1[0], sizeof(mmSMU_MP1_SRBM2P_ARG_1)/sizeof(mmSMU_MP1_SRBM2P_ARG_1[0]), 0, 0 },
	{ "mmSMU_MP1_SRBM2P_ARG_2", REG_MMIO, 0x1e2, &mmSMU_MP1_SRBM2P_ARG_2[0], sizeof(mmSMU_MP1_SRBM2P_ARG_2)/sizeof(mmSMU_MP1_SRBM2P_ARG_2[0]), 0, 0 },
	{ "mmSMU_MP1_SRBM2P_ARG_3", REG_MMIO, 0x1e3, &mmSMU_MP1_SRBM2P_ARG_3[0], sizeof(mmSMU_MP1_SRBM2P_ARG_3)/sizeof(mmSMU_MP1_SRBM2P_ARG_3[0]), 0, 0 },
	{ "mmSMU_MP1_SRBM2P_ARG_4", REG_MMIO, 0x1e4, &mmSMU_MP1_SRBM2P_ARG_4[0], sizeof(mmSMU_MP1_SRBM2P_ARG_4)/sizeof(mmSMU_MP1_SRBM2P_ARG_4[0]), 0, 0 },
	{ "mmSMU_MP1_SRBM2P_ARG_5", REG_MMIO, 0x1e5, &mmSMU_MP1_SRBM2P_ARG_5[0], sizeof(mmSMU_MP1_SRBM2P_ARG_5)/sizeof(mmSMU_MP1_SRBM2P_ARG_5[0]), 0, 0 },
	{ "mmSMU_MP1_SRBM2P_ARG_6", REG_MMIO, 0x1e6, &mmSMU_MP1_SRBM2P_ARG_6[0], sizeof(mmSMU_MP1_SRBM2P_ARG_6)/sizeof(mmSMU_MP1_SRBM2P_ARG_6[0]), 0, 0 },
	{ "mmSMU_MP1_SRBM2P_ARG_7", REG_MMIO, 0x1e7, &mmSMU_MP1_SRBM2P_ARG_7[0], sizeof(mmSMU_MP1_SRBM2P_ARG_7)/sizeof(mmSMU_MP1_SRBM2P_ARG_7[0]), 0, 0 },
	{ "mmSMU_MP1_SRBM2P_ARG_8", REG_MMIO, 0x1e8, &mmSMU_MP1_SRBM2P_ARG_8[0], sizeof(mmSMU_MP1_SRBM2P_ARG_8)/sizeof(mmSMU_MP1_SRBM2P_ARG_8[0]), 0, 0 },
	{ "mmSMU_MP1_SRBM2P_ARG_9", REG_MMIO, 0x1e9, &mmSMU_MP1_SRBM2P_ARG_9[0], sizeof(mmSMU_MP1_SRBM2P_ARG_9)/sizeof(mmSMU_MP1_SRBM2P_ARG_9[0]), 0, 0 },
	{ "mmSMU_MP1_SRBM2P_ARG_10", REG_MMIO, 0x1ea, &mmSMU_MP1_SRBM2P_ARG_10[0], sizeof(mmSMU_MP1_SRBM2P_ARG_10)/sizeof(mmSMU_MP1_SRBM2P_ARG_10[0]), 0, 0 },
	{ "mmSMU_MP1_SRBM2P_ARG_11", REG_MMIO, 0x1eb, &mmSMU_MP1_SRBM2P_ARG_11[0], sizeof(mmSMU_MP1_SRBM2P_ARG_11)/sizeof(mmSMU_MP1_SRBM2P_ARG_11[0]), 0, 0 },
	{ "mmSMU_MP1_SRBM2P_ARG_12", REG_MMIO, 0x1ec, &mmSMU_MP1_SRBM2P_ARG_12[0], sizeof(mmSMU_MP1_SRBM2P_ARG_12)/sizeof(mmSMU_MP1_SRBM2P_ARG_12[0]), 0, 0 },
	{ "mmSMU_MP1_SRBM2P_ARG_13", REG_MMIO, 0x1ed, &mmSMU_MP1_SRBM2P_ARG_13[0], sizeof(mmSMU_MP1_SRBM2P_ARG_13)/sizeof(mmSMU_MP1_SRBM2P_ARG_13[0]), 0, 0 },
	{ "mmSMU_MP1_SRBM2P_ARG_14", REG_MMIO, 0x1ee, &mmSMU_MP1_SRBM2P_ARG_14[0], sizeof(mmSMU_MP1_SRBM2P_ARG_14)/sizeof(mmSMU_MP1_SRBM2P_ARG_14[0]), 0, 0 },
	{ "mmSMU_MP1_SRBM2P_ARG_15", REG_MMIO, 0x1ef, &mmSMU_MP1_SRBM2P_ARG_15[0], sizeof(mmSMU_MP1_SRBM2P_ARG_15)/sizeof(mmSMU_MP1_SRBM2P_ARG_15[0]), 0, 0 },
	{ "mmSMU_MP1_ACP2MP_RESP", REG_MMIO, 0x1f0, &mmSMU_MP1_ACP2MP_RESP[0], sizeof(mmSMU_MP1_ACP2MP_RESP)/sizeof(mmSMU_MP1_ACP2MP_RESP[0]), 0, 0 },
	{ "mmSMU_MP1_DC2MP_RESP", REG_MMIO, 0x1f1, &mmSMU_MP1_DC2MP_RESP[0], sizeof(mmSMU_MP1_DC2MP_RESP)/sizeof(mmSMU_MP1_DC2MP_RESP[0]), 0, 0 },
	{ "mmSMU_MP1_UVD2MP_RESP", REG_MMIO, 0x1f2, &mmSMU_MP1_UVD2MP_RESP[0], sizeof(mmSMU_MP1_UVD2MP_RESP)/sizeof(mmSMU_MP1_UVD2MP_RESP[0]), 0, 0 },
	{ "mmSMU_MP1_VCE2MP_RESP", REG_MMIO, 0x1f3, &mmSMU_MP1_VCE2MP_RESP[0], sizeof(mmSMU_MP1_VCE2MP_RESP)/sizeof(mmSMU_MP1_VCE2MP_RESP[0]), 0, 0 },
	{ "mmSMU_MP1_RLC2MP_RESP", REG_MMIO, 0x1f4, &mmSMU_MP1_RLC2MP_RESP[0], sizeof(mmSMU_MP1_RLC2MP_RESP)/sizeof(mmSMU_MP1_RLC2MP_RESP[0]), 0, 0 },
	{ "mmMP_FPS_CNT", REG_MMIO, 0x1f5, &mmMP_FPS_CNT[0], sizeof(mmMP_FPS_CNT)/sizeof(mmMP_FPS_CNT[0]), 0, 0 },
	{ "mmSMU_DISP0_TIMER_INT_CONTROL", REG_MMIO, 0x1f6, &mmSMU_DISP0_TIMER_INT_CONTROL[0], sizeof(mmSMU_DISP0_TIMER_INT_CONTROL)/sizeof(mmSMU_DISP0_TIMER_INT_CONTROL[0]), 0, 0 },
	{ "mmSMU_DISP1_TIMER_INT_CONTROL", REG_MMIO, 0x1f7, &mmSMU_DISP1_TIMER_INT_CONTROL[0], sizeof(mmSMU_DISP1_TIMER_INT_CONTROL)/sizeof(mmSMU_DISP1_TIMER_INT_CONTROL[0]), 0, 0 },
	{ "mmSMU_SRBM_CONFIG", REG_MMIO, 0x1f8, &mmSMU_SRBM_CONFIG[0], sizeof(mmSMU_SRBM_CONFIG)/sizeof(mmSMU_SRBM_CONFIG[0]), 0, 0 },
	{ "ixGC_CAC_WEIGHT_CU_0", REG_SMC, 0x32, &ixGC_CAC_WEIGHT_CU_0[0], sizeof(ixGC_CAC_WEIGHT_CU_0)/sizeof(ixGC_CAC_WEIGHT_CU_0[0]), 0, 0 },
	{ "mmGC_CAC_LKG_AGGR_LOWER", REG_MMIO, 0x3294, &mmGC_CAC_LKG_AGGR_LOWER[0], sizeof(mmGC_CAC_LKG_AGGR_LOWER)/sizeof(mmGC_CAC_LKG_AGGR_LOWER[0]), 0, 0 },
	{ "mmGC_CAC_LKG_AGGR_UPPER", REG_MMIO, 0x3295, &mmGC_CAC_LKG_AGGR_UPPER[0], sizeof(mmGC_CAC_LKG_AGGR_UPPER)/sizeof(mmGC_CAC_LKG_AGGR_UPPER[0]), 0, 0 },
	{ "ixGC_CAC_WEIGHT_CU_1", REG_SMC, 0x33, &ixGC_CAC_WEIGHT_CU_1[0], sizeof(ixGC_CAC_WEIGHT_CU_1)/sizeof(ixGC_CAC_WEIGHT_CU_1[0]), 0, 0 },
	{ "ixGC_CAC_WEIGHT_CU_2", REG_SMC, 0x34, &ixGC_CAC_WEIGHT_CU_2[0], sizeof(ixGC_CAC_WEIGHT_CU_2)/sizeof(ixGC_CAC_WEIGHT_CU_2[0]), 0, 0 },
	{ "ixGC_CAC_WEIGHT_CU_3", REG_SMC, 0x35, &ixGC_CAC_WEIGHT_CU_3[0], sizeof(ixGC_CAC_WEIGHT_CU_3)/sizeof(ixGC_CAC_WEIGHT_CU_3[0]), 0, 0 },
	{ "ixGC_CAC_ACC_CU0", REG_SMC, 0xba, &ixGC_CAC_ACC_CU0[0], sizeof(ixGC_CAC_ACC_CU0)/sizeof(ixGC_CAC_ACC_CU0[0]), 0, 0 },
	{ "ixGC_CAC_ACC_CU1", REG_SMC, 0xbb, &ixGC_CAC_ACC_CU1[0], sizeof(ixGC_CAC_ACC_CU1)/sizeof(ixGC_CAC_ACC_CU1[0]), 0, 0 },
	{ "ixGC_CAC_ACC_CU2", REG_SMC, 0xbc, &ixGC_CAC_ACC_CU2[0], sizeof(ixGC_CAC_ACC_CU2)/sizeof(ixGC_CAC_ACC_CU2[0]), 0, 0 },
	{ "ixGC_CAC_ACC_CU3", REG_SMC, 0xbd, &ixGC_CAC_ACC_CU3[0], sizeof(ixGC_CAC_ACC_CU3)/sizeof(ixGC_CAC_ACC_CU3[0]), 0, 0 },
	{ "ixGC_CAC_ACC_CU4", REG_SMC, 0xbe, &ixGC_CAC_ACC_CU4[0], sizeof(ixGC_CAC_ACC_CU4)/sizeof(ixGC_CAC_ACC_CU4[0]), 0, 0 },
	{ "ixGC_CAC_ACC_CU5", REG_SMC, 0xbf, &ixGC_CAC_ACC_CU5[0], sizeof(ixGC_CAC_ACC_CU5)/sizeof(ixGC_CAC_ACC_CU5[0]), 0, 0 },
	{ "ixGC_CAC_ACC_CU6", REG_SMC, 0xc0, &ixGC_CAC_ACC_CU6[0], sizeof(ixGC_CAC_ACC_CU6)/sizeof(ixGC_CAC_ACC_CU6[0]), 0, 0 },
	{ "ixGC_CAC_ACC_CU7", REG_SMC, 0xc1, &ixGC_CAC_ACC_CU7[0], sizeof(ixGC_CAC_ACC_CU7)/sizeof(ixGC_CAC_ACC_CU7[0]), 0, 0 },
	{ "ixMP_IOC_CTRL", REG_SMC, 0xcf100000, &ixMP_IOC_CTRL[0], sizeof(ixMP_IOC_CTRL)/sizeof(ixMP_IOC_CTRL[0]), 0, 0 },
	{ "ixMP_IOC_RDDATA", REG_SMC, 0xcf100004, &ixMP_IOC_RDDATA[0], sizeof(ixMP_IOC_RDDATA)/sizeof(ixMP_IOC_RDDATA[0]), 0, 0 },
	{ "ixMP_IOC_PHASE1", REG_SMC, 0xcf100008, &ixMP_IOC_PHASE1[0], sizeof(ixMP_IOC_PHASE1)/sizeof(ixMP_IOC_PHASE1[0]), 0, 0 },
	{ "ixMP_IOC_PHASE2", REG_SMC, 0xcf10000c, &ixMP_IOC_PHASE2[0], sizeof(ixMP_IOC_PHASE2)/sizeof(ixMP_IOC_PHASE2[0]), 0, 0 },
	{ "ixMP_IOC_PHASE3", REG_SMC, 0xcf100010, &ixMP_IOC_PHASE3[0], sizeof(ixMP_IOC_PHASE3)/sizeof(ixMP_IOC_PHASE3[0]), 0, 0 },
	{ "ixMP_IOC_READ_0", REG_SMC, 0xcf100024, &ixMP_IOC_READ_0[0], sizeof(ixMP_IOC_READ_0)/sizeof(ixMP_IOC_READ_0[0]), 0, 0 },
	{ "ixMP_IOC_READ_1", REG_SMC, 0xcf100028, &ixMP_IOC_READ_1[0], sizeof(ixMP_IOC_READ_1)/sizeof(ixMP_IOC_READ_1[0]), 0, 0 },
	{ "ixMP_IOC_READ_2", REG_SMC, 0xcf10002c, &ixMP_IOC_READ_2[0], sizeof(ixMP_IOC_READ_2)/sizeof(ixMP_IOC_READ_2[0]), 0, 0 },
	{ "ixMP_IOC_READ_3", REG_SMC, 0xcf100030, &ixMP_IOC_READ_3[0], sizeof(ixMP_IOC_READ_3)/sizeof(ixMP_IOC_READ_3[0]), 0, 0 },
	{ "ixMP_IOC_READ_4", REG_SMC, 0xcf100034, &ixMP_IOC_READ_4[0], sizeof(ixMP_IOC_READ_4)/sizeof(ixMP_IOC_READ_4[0]), 0, 0 },
	{ "ixMP_IOC_READ_5", REG_SMC, 0xcf100038, &ixMP_IOC_READ_5[0], sizeof(ixMP_IOC_READ_5)/sizeof(ixMP_IOC_READ_5[0]), 0, 0 },
	{ "ixMP_IOC_READ_6", REG_SMC, 0xcf10003c, &ixMP_IOC_READ_6[0], sizeof(ixMP_IOC_READ_6)/sizeof(ixMP_IOC_READ_6[0]), 0, 0 },
	{ "ixMP_IOC_READ_7", REG_SMC, 0xcf100040, &ixMP_IOC_READ_7[0], sizeof(ixMP_IOC_READ_7)/sizeof(ixMP_IOC_READ_7[0]), 0, 0 },
	{ "ixMP_IOC_READ_8", REG_SMC, 0xcf100044, &ixMP_IOC_READ_8[0], sizeof(ixMP_IOC_READ_8)/sizeof(ixMP_IOC_READ_8[0]), 0, 0 },
	{ "ixMP_IOC_READ_9", REG_SMC, 0xcf100048, &ixMP_IOC_READ_9[0], sizeof(ixMP_IOC_READ_9)/sizeof(ixMP_IOC_READ_9[0]), 0, 0 },
	{ "ixMP_IOC_READ_10", REG_SMC, 0xcf10004c, &ixMP_IOC_READ_10[0], sizeof(ixMP_IOC_READ_10)/sizeof(ixMP_IOC_READ_10[0]), 0, 0 },
	{ "ixMP_IOC_READ_11", REG_SMC, 0xcf100050, &ixMP_IOC_READ_11[0], sizeof(ixMP_IOC_READ_11)/sizeof(ixMP_IOC_READ_11[0]), 0, 0 },
	{ "ixMP_IOC_READ_12", REG_SMC, 0xcf100054, &ixMP_IOC_READ_12[0], sizeof(ixMP_IOC_READ_12)/sizeof(ixMP_IOC_READ_12[0]), 0, 0 },
	{ "ixMP_IOC_READ_13", REG_SMC, 0xcf100058, &ixMP_IOC_READ_13[0], sizeof(ixMP_IOC_READ_13)/sizeof(ixMP_IOC_READ_13[0]), 0, 0 },
	{ "ixMP_IOC_READ_14", REG_SMC, 0xcf10005c, &ixMP_IOC_READ_14[0], sizeof(ixMP_IOC_READ_14)/sizeof(ixMP_IOC_READ_14[0]), 0, 0 },
	{ "ixMP_IOC_READ_15", REG_SMC, 0xcf100060, &ixMP_IOC_READ_15[0], sizeof(ixMP_IOC_READ_15)/sizeof(ixMP_IOC_READ_15[0]), 0, 0 },
	{ "ixMP_IOC_WRITE_0", REG_SMC, 0xcf100064, &ixMP_IOC_WRITE_0[0], sizeof(ixMP_IOC_WRITE_0)/sizeof(ixMP_IOC_WRITE_0[0]), 0, 0 },
	{ "ixMP_IOC_WRITE_1", REG_SMC, 0xcf100068, &ixMP_IOC_WRITE_1[0], sizeof(ixMP_IOC_WRITE_1)/sizeof(ixMP_IOC_WRITE_1[0]), 0, 0 },
	{ "ixMP_IOC_WRITE_2", REG_SMC, 0xcf10006c, &ixMP_IOC_WRITE_2[0], sizeof(ixMP_IOC_WRITE_2)/sizeof(ixMP_IOC_WRITE_2[0]), 0, 0 },
	{ "ixMP_IOC_WRITE_3", REG_SMC, 0xcf100070, &ixMP_IOC_WRITE_3[0], sizeof(ixMP_IOC_WRITE_3)/sizeof(ixMP_IOC_WRITE_3[0]), 0, 0 },
	{ "ixMP_IOC_WRITE_4", REG_SMC, 0xcf100074, &ixMP_IOC_WRITE_4[0], sizeof(ixMP_IOC_WRITE_4)/sizeof(ixMP_IOC_WRITE_4[0]), 0, 0 },
	{ "ixMP_IOC_WRITE_5", REG_SMC, 0xcf100078, &ixMP_IOC_WRITE_5[0], sizeof(ixMP_IOC_WRITE_5)/sizeof(ixMP_IOC_WRITE_5[0]), 0, 0 },
	{ "ixMP_IOC_WRITE_6", REG_SMC, 0xcf10007c, &ixMP_IOC_WRITE_6[0], sizeof(ixMP_IOC_WRITE_6)/sizeof(ixMP_IOC_WRITE_6[0]), 0, 0 },
	{ "ixMP_IOC_WRITE_7", REG_SMC, 0xcf100080, &ixMP_IOC_WRITE_7[0], sizeof(ixMP_IOC_WRITE_7)/sizeof(ixMP_IOC_WRITE_7[0]), 0, 0 },
	{ "ixMP_IOC_WRITE_8", REG_SMC, 0xcf100084, &ixMP_IOC_WRITE_8[0], sizeof(ixMP_IOC_WRITE_8)/sizeof(ixMP_IOC_WRITE_8[0]), 0, 0 },
	{ "ixMP_IOC_WRITE_9", REG_SMC, 0xcf100088, &ixMP_IOC_WRITE_9[0], sizeof(ixMP_IOC_WRITE_9)/sizeof(ixMP_IOC_WRITE_9[0]), 0, 0 },
	{ "ixMP_IOC_WRITE_10", REG_SMC, 0xcf10008c, &ixMP_IOC_WRITE_10[0], sizeof(ixMP_IOC_WRITE_10)/sizeof(ixMP_IOC_WRITE_10[0]), 0, 0 },
	{ "ixMP_IOC_WRITE_11", REG_SMC, 0xcf100090, &ixMP_IOC_WRITE_11[0], sizeof(ixMP_IOC_WRITE_11)/sizeof(ixMP_IOC_WRITE_11[0]), 0, 0 },
	{ "ixMP_IOC_WRITE_12", REG_SMC, 0xcf100094, &ixMP_IOC_WRITE_12[0], sizeof(ixMP_IOC_WRITE_12)/sizeof(ixMP_IOC_WRITE_12[0]), 0, 0 },
	{ "ixMP_IOC_WRITE_13", REG_SMC, 0xcf100098, &ixMP_IOC_WRITE_13[0], sizeof(ixMP_IOC_WRITE_13)/sizeof(ixMP_IOC_WRITE_13[0]), 0, 0 },
	{ "ixMP_IOC_WRITE_14", REG_SMC, 0xcf10009c, &ixMP_IOC_WRITE_14[0], sizeof(ixMP_IOC_WRITE_14)/sizeof(ixMP_IOC_WRITE_14[0]), 0, 0 },
	{ "ixMP_IOC_WRITE_15", REG_SMC, 0xcf1000a0, &ixMP_IOC_WRITE_15[0], sizeof(ixMP_IOC_WRITE_15)/sizeof(ixMP_IOC_WRITE_15[0]), 0, 0 },
	{ "ixMP_DRAM_CNTL_WRREQ_CNTL", REG_SMC, 0xcf200000, &ixMP_DRAM_CNTL_WRREQ_CNTL[0], sizeof(ixMP_DRAM_CNTL_WRREQ_CNTL)/sizeof(ixMP_DRAM_CNTL_WRREQ_CNTL[0]), 0, 0 },
	{ "ixMP_DRAM_CNTL_WRREQ_CNTL_1", REG_SMC, 0xcf200004, &ixMP_DRAM_CNTL_WRREQ_CNTL_1[0], sizeof(ixMP_DRAM_CNTL_WRREQ_CNTL_1)/sizeof(ixMP_DRAM_CNTL_WRREQ_CNTL_1[0]), 0, 0 },
	{ "ixMP_DRAM_CNTL_WRREQ_LOW_ADDR", REG_SMC, 0xcf200008, &ixMP_DRAM_CNTL_WRREQ_LOW_ADDR[0], sizeof(ixMP_DRAM_CNTL_WRREQ_LOW_ADDR)/sizeof(ixMP_DRAM_CNTL_WRREQ_LOW_ADDR[0]), 0, 0 },
	{ "ixMP_DRAM_CNTL_WRREQ_HIGH_ADDR", REG_SMC, 0xcf20000c, &ixMP_DRAM_CNTL_WRREQ_HIGH_ADDR[0], sizeof(ixMP_DRAM_CNTL_WRREQ_HIGH_ADDR)/sizeof(ixMP_DRAM_CNTL_WRREQ_HIGH_ADDR[0]), 0, 0 },
	{ "ixMP_DRAM_CNTL_WRREQ_MASK", REG_SMC, 0xcf200010, &ixMP_DRAM_CNTL_WRREQ_MASK[0], sizeof(ixMP_DRAM_CNTL_WRREQ_MASK)/sizeof(ixMP_DRAM_CNTL_WRREQ_MASK[0]), 0, 0 },
	{ "ixMP_DRAM_CNTL_WRREQ_DATA_0", REG_SMC, 0xcf200014, &ixMP_DRAM_CNTL_WRREQ_DATA_0[0], sizeof(ixMP_DRAM_CNTL_WRREQ_DATA_0)/sizeof(ixMP_DRAM_CNTL_WRREQ_DATA_0[0]), 0, 0 },
	{ "ixMP_DRAM_CNTL_WRREQ_DATA_1", REG_SMC, 0xcf200018, &ixMP_DRAM_CNTL_WRREQ_DATA_1[0], sizeof(ixMP_DRAM_CNTL_WRREQ_DATA_1)/sizeof(ixMP_DRAM_CNTL_WRREQ_DATA_1[0]), 0, 0 },
	{ "ixMP_DRAM_CNTL_WRREQ_DATA_2", REG_SMC, 0xcf20001c, &ixMP_DRAM_CNTL_WRREQ_DATA_2[0], sizeof(ixMP_DRAM_CNTL_WRREQ_DATA_2)/sizeof(ixMP_DRAM_CNTL_WRREQ_DATA_2[0]), 0, 0 },
	{ "ixMP_DRAM_CNTL_WRREQ_DATA_3", REG_SMC, 0xcf200020, &ixMP_DRAM_CNTL_WRREQ_DATA_3[0], sizeof(ixMP_DRAM_CNTL_WRREQ_DATA_3)/sizeof(ixMP_DRAM_CNTL_WRREQ_DATA_3[0]), 0, 0 },
	{ "ixMP_DRAM_CNTL_WRREQ_DATA_4", REG_SMC, 0xcf200024, &ixMP_DRAM_CNTL_WRREQ_DATA_4[0], sizeof(ixMP_DRAM_CNTL_WRREQ_DATA_4)/sizeof(ixMP_DRAM_CNTL_WRREQ_DATA_4[0]), 0, 0 },
	{ "ixMP_DRAM_CNTL_WRREQ_DATA_5", REG_SMC, 0xcf200028, &ixMP_DRAM_CNTL_WRREQ_DATA_5[0], sizeof(ixMP_DRAM_CNTL_WRREQ_DATA_5)/sizeof(ixMP_DRAM_CNTL_WRREQ_DATA_5[0]), 0, 0 },
	{ "ixMP_DRAM_CNTL_WRREQ_DATA_6", REG_SMC, 0xcf20002c, &ixMP_DRAM_CNTL_WRREQ_DATA_6[0], sizeof(ixMP_DRAM_CNTL_WRREQ_DATA_6)/sizeof(ixMP_DRAM_CNTL_WRREQ_DATA_6[0]), 0, 0 },
	{ "ixMP_DRAM_CNTL_WRREQ_DATA_7", REG_SMC, 0xcf200030, &ixMP_DRAM_CNTL_WRREQ_DATA_7[0], sizeof(ixMP_DRAM_CNTL_WRREQ_DATA_7)/sizeof(ixMP_DRAM_CNTL_WRREQ_DATA_7[0]), 0, 0 },
	{ "ixMP_DRAM_CNTL_WRREQ_STATUS", REG_SMC, 0xcf200038, &ixMP_DRAM_CNTL_WRREQ_STATUS[0], sizeof(ixMP_DRAM_CNTL_WRREQ_STATUS)/sizeof(ixMP_DRAM_CNTL_WRREQ_STATUS[0]), 0, 0 },
	{ "ixMP_DRAM_CNTL_WRRET_STATUS_0", REG_SMC, 0xcf20003c, &ixMP_DRAM_CNTL_WRRET_STATUS_0[0], sizeof(ixMP_DRAM_CNTL_WRRET_STATUS_0)/sizeof(ixMP_DRAM_CNTL_WRRET_STATUS_0[0]), 0, 0 },
	{ "ixMP_DRAM_CNTL_RDREQ_ADDR", REG_SMC, 0xcf200040, &ixMP_DRAM_CNTL_RDREQ_ADDR[0], sizeof(ixMP_DRAM_CNTL_RDREQ_ADDR)/sizeof(ixMP_DRAM_CNTL_RDREQ_ADDR[0]), 0, 0 },
	{ "ixMP_DRAM_CNTL_RDREQ_CNTL", REG_SMC, 0xcf200044, &ixMP_DRAM_CNTL_RDREQ_CNTL[0], sizeof(ixMP_DRAM_CNTL_RDREQ_CNTL)/sizeof(ixMP_DRAM_CNTL_RDREQ_CNTL[0]), 0, 0 },
	{ "ixMP_DRAM_CNTL_RDREQ_CNTL_1", REG_SMC, 0xcf200048, &ixMP_DRAM_CNTL_RDREQ_CNTL_1[0], sizeof(ixMP_DRAM_CNTL_RDREQ_CNTL_1)/sizeof(ixMP_DRAM_CNTL_RDREQ_CNTL_1[0]), 0, 0 },
	{ "ixMP_DRAM_CNTL_RDRET_VALID", REG_SMC, 0xcf20004c, &ixMP_DRAM_CNTL_RDRET_VALID[0], sizeof(ixMP_DRAM_CNTL_RDRET_VALID)/sizeof(ixMP_DRAM_CNTL_RDRET_VALID[0]), 0, 0 },
	{ "ixMP_DRAM_CNTL_RDRET_NACK", REG_SMC, 0xcf200050, &ixMP_DRAM_CNTL_RDRET_NACK[0], sizeof(ixMP_DRAM_CNTL_RDRET_NACK)/sizeof(ixMP_DRAM_CNTL_RDRET_NACK[0]), 0, 0 },
	{ "ixMP_DRAM_CNTL_RDRET_DATA_0", REG_SMC, 0xcf200054, &ixMP_DRAM_CNTL_RDRET_DATA_0[0], sizeof(ixMP_DRAM_CNTL_RDRET_DATA_0)/sizeof(ixMP_DRAM_CNTL_RDRET_DATA_0[0]), 0, 0 },
	{ "ixMP_DRAM_CNTL_RDRET_DATA_1", REG_SMC, 0xcf200058, &ixMP_DRAM_CNTL_RDRET_DATA_1[0], sizeof(ixMP_DRAM_CNTL_RDRET_DATA_1)/sizeof(ixMP_DRAM_CNTL_RDRET_DATA_1[0]), 0, 0 },
	{ "ixMP_DRAM_CNTL_RDRET_DATA_2", REG_SMC, 0xcf20005c, &ixMP_DRAM_CNTL_RDRET_DATA_2[0], sizeof(ixMP_DRAM_CNTL_RDRET_DATA_2)/sizeof(ixMP_DRAM_CNTL_RDRET_DATA_2[0]), 0, 0 },
	{ "ixMP_DRAM_CNTL_RDRET_DATA_3", REG_SMC, 0xcf200060, &ixMP_DRAM_CNTL_RDRET_DATA_3[0], sizeof(ixMP_DRAM_CNTL_RDRET_DATA_3)/sizeof(ixMP_DRAM_CNTL_RDRET_DATA_3[0]), 0, 0 },
	{ "ixMP_DRAM_CNTL_RDRET_DATA_4", REG_SMC, 0xcf200064, &ixMP_DRAM_CNTL_RDRET_DATA_4[0], sizeof(ixMP_DRAM_CNTL_RDRET_DATA_4)/sizeof(ixMP_DRAM_CNTL_RDRET_DATA_4[0]), 0, 0 },
	{ "ixMP_DRAM_CNTL_RDRET_DATA_5", REG_SMC, 0xcf200068, &ixMP_DRAM_CNTL_RDRET_DATA_5[0], sizeof(ixMP_DRAM_CNTL_RDRET_DATA_5)/sizeof(ixMP_DRAM_CNTL_RDRET_DATA_5[0]), 0, 0 },
	{ "ixMP_DRAM_CNTL_RDRET_DATA_6", REG_SMC, 0xcf20006c, &ixMP_DRAM_CNTL_RDRET_DATA_6[0], sizeof(ixMP_DRAM_CNTL_RDRET_DATA_6)/sizeof(ixMP_DRAM_CNTL_RDRET_DATA_6[0]), 0, 0 },
	{ "ixMP_DRAM_CNTL_RDRET_DATA_7", REG_SMC, 0xcf200070, &ixMP_DRAM_CNTL_RDRET_DATA_7[0], sizeof(ixMP_DRAM_CNTL_RDRET_DATA_7)/sizeof(ixMP_DRAM_CNTL_RDRET_DATA_7[0]), 0, 0 },
	{ "ixMP_DRAM_CNTL_RDRET_DATA_8", REG_SMC, 0xcf200074, &ixMP_DRAM_CNTL_RDRET_DATA_8[0], sizeof(ixMP_DRAM_CNTL_RDRET_DATA_8)/sizeof(ixMP_DRAM_CNTL_RDRET_DATA_8[0]), 0, 0 },
	{ "ixMP_DRAM_CNTL_RDRET_DATA_9", REG_SMC, 0xcf200078, &ixMP_DRAM_CNTL_RDRET_DATA_9[0], sizeof(ixMP_DRAM_CNTL_RDRET_DATA_9)/sizeof(ixMP_DRAM_CNTL_RDRET_DATA_9[0]), 0, 0 },
	{ "ixMP_DRAM_CNTL_RDRET_DATA_10", REG_SMC, 0xcf20007c, &ixMP_DRAM_CNTL_RDRET_DATA_10[0], sizeof(ixMP_DRAM_CNTL_RDRET_DATA_10)/sizeof(ixMP_DRAM_CNTL_RDRET_DATA_10[0]), 0, 0 },
	{ "ixMP_DRAM_CNTL_RDRET_DATA_11", REG_SMC, 0xcf200080, &ixMP_DRAM_CNTL_RDRET_DATA_11[0], sizeof(ixMP_DRAM_CNTL_RDRET_DATA_11)/sizeof(ixMP_DRAM_CNTL_RDRET_DATA_11[0]), 0, 0 },
	{ "ixMP_DRAM_CNTL_RDRET_DATA_12", REG_SMC, 0xcf200084, &ixMP_DRAM_CNTL_RDRET_DATA_12[0], sizeof(ixMP_DRAM_CNTL_RDRET_DATA_12)/sizeof(ixMP_DRAM_CNTL_RDRET_DATA_12[0]), 0, 0 },
	{ "ixMP_DRAM_CNTL_RDRET_DATA_13", REG_SMC, 0xcf200088, &ixMP_DRAM_CNTL_RDRET_DATA_13[0], sizeof(ixMP_DRAM_CNTL_RDRET_DATA_13)/sizeof(ixMP_DRAM_CNTL_RDRET_DATA_13[0]), 0, 0 },
	{ "ixMP_DRAM_CNTL_RDRET_DATA_14", REG_SMC, 0xcf20008c, &ixMP_DRAM_CNTL_RDRET_DATA_14[0], sizeof(ixMP_DRAM_CNTL_RDRET_DATA_14)/sizeof(ixMP_DRAM_CNTL_RDRET_DATA_14[0]), 0, 0 },
	{ "ixMP_DRAM_CNTL_RDRET_DATA_15", REG_SMC, 0xcf200090, &ixMP_DRAM_CNTL_RDRET_DATA_15[0], sizeof(ixMP_DRAM_CNTL_RDRET_DATA_15)/sizeof(ixMP_DRAM_CNTL_RDRET_DATA_15[0]), 0, 0 },
	{ "ixMP_DRAM_CNTL_RDRET_DATA_16", REG_SMC, 0xcf200094, &ixMP_DRAM_CNTL_RDRET_DATA_16[0], sizeof(ixMP_DRAM_CNTL_RDRET_DATA_16)/sizeof(ixMP_DRAM_CNTL_RDRET_DATA_16[0]), 0, 0 },
	{ "ixMP_DRAM_CNTL_RDRET_DATA_17", REG_SMC, 0xcf200098, &ixMP_DRAM_CNTL_RDRET_DATA_17[0], sizeof(ixMP_DRAM_CNTL_RDRET_DATA_17)/sizeof(ixMP_DRAM_CNTL_RDRET_DATA_17[0]), 0, 0 },
	{ "ixMP_DRAM_CNTL_RDRET_DATA_18", REG_SMC, 0xcf20009c, &ixMP_DRAM_CNTL_RDRET_DATA_18[0], sizeof(ixMP_DRAM_CNTL_RDRET_DATA_18)/sizeof(ixMP_DRAM_CNTL_RDRET_DATA_18[0]), 0, 0 },
	{ "ixMP_DRAM_CNTL_RDRET_DATA_19", REG_SMC, 0xcf2000a0, &ixMP_DRAM_CNTL_RDRET_DATA_19[0], sizeof(ixMP_DRAM_CNTL_RDRET_DATA_19)/sizeof(ixMP_DRAM_CNTL_RDRET_DATA_19[0]), 0, 0 },
	{ "ixMP_DRAM_CNTL_RDRET_DATA_20", REG_SMC, 0xcf2000a4, &ixMP_DRAM_CNTL_RDRET_DATA_20[0], sizeof(ixMP_DRAM_CNTL_RDRET_DATA_20)/sizeof(ixMP_DRAM_CNTL_RDRET_DATA_20[0]), 0, 0 },
	{ "ixMP_DRAM_CNTL_RDRET_DATA_21", REG_SMC, 0xcf2000a8, &ixMP_DRAM_CNTL_RDRET_DATA_21[0], sizeof(ixMP_DRAM_CNTL_RDRET_DATA_21)/sizeof(ixMP_DRAM_CNTL_RDRET_DATA_21[0]), 0, 0 },
	{ "ixMP_DRAM_CNTL_RDRET_DATA_22", REG_SMC, 0xcf2000ac, &ixMP_DRAM_CNTL_RDRET_DATA_22[0], sizeof(ixMP_DRAM_CNTL_RDRET_DATA_22)/sizeof(ixMP_DRAM_CNTL_RDRET_DATA_22[0]), 0, 0 },
	{ "ixMP_DRAM_CNTL_RDRET_DATA_23", REG_SMC, 0xcf2000b0, &ixMP_DRAM_CNTL_RDRET_DATA_23[0], sizeof(ixMP_DRAM_CNTL_RDRET_DATA_23)/sizeof(ixMP_DRAM_CNTL_RDRET_DATA_23[0]), 0, 0 },
	{ "ixMP_DRAM_CNTL_RDRET_DATA_24", REG_SMC, 0xcf2000b4, &ixMP_DRAM_CNTL_RDRET_DATA_24[0], sizeof(ixMP_DRAM_CNTL_RDRET_DATA_24)/sizeof(ixMP_DRAM_CNTL_RDRET_DATA_24[0]), 0, 0 },
	{ "ixMP_DRAM_CNTL_RDRET_DATA_25", REG_SMC, 0xcf2000b8, &ixMP_DRAM_CNTL_RDRET_DATA_25[0], sizeof(ixMP_DRAM_CNTL_RDRET_DATA_25)/sizeof(ixMP_DRAM_CNTL_RDRET_DATA_25[0]), 0, 0 },
	{ "ixMP_DRAM_CNTL_RDRET_DATA_26", REG_SMC, 0xcf2000bc, &ixMP_DRAM_CNTL_RDRET_DATA_26[0], sizeof(ixMP_DRAM_CNTL_RDRET_DATA_26)/sizeof(ixMP_DRAM_CNTL_RDRET_DATA_26[0]), 0, 0 },
	{ "ixMP_DRAM_CNTL_RDRET_DATA_27", REG_SMC, 0xcf2000c0, &ixMP_DRAM_CNTL_RDRET_DATA_27[0], sizeof(ixMP_DRAM_CNTL_RDRET_DATA_27)/sizeof(ixMP_DRAM_CNTL_RDRET_DATA_27[0]), 0, 0 },
	{ "ixMP_DRAM_CNTL_RDRET_DATA_28", REG_SMC, 0xcf2000c4, &ixMP_DRAM_CNTL_RDRET_DATA_28[0], sizeof(ixMP_DRAM_CNTL_RDRET_DATA_28)/sizeof(ixMP_DRAM_CNTL_RDRET_DATA_28[0]), 0, 0 },
	{ "ixMP_DRAM_CNTL_RDRET_DATA_29", REG_SMC, 0xcf2000c8, &ixMP_DRAM_CNTL_RDRET_DATA_29[0], sizeof(ixMP_DRAM_CNTL_RDRET_DATA_29)/sizeof(ixMP_DRAM_CNTL_RDRET_DATA_29[0]), 0, 0 },
	{ "ixMP_DRAM_CNTL_RDRET_DATA_30", REG_SMC, 0xcf2000cc, &ixMP_DRAM_CNTL_RDRET_DATA_30[0], sizeof(ixMP_DRAM_CNTL_RDRET_DATA_30)/sizeof(ixMP_DRAM_CNTL_RDRET_DATA_30[0]), 0, 0 },
	{ "ixMP_DRAM_CNTL_RDRET_DATA_31", REG_SMC, 0xcf2000d0, &ixMP_DRAM_CNTL_RDRET_DATA_31[0], sizeof(ixMP_DRAM_CNTL_RDRET_DATA_31)/sizeof(ixMP_DRAM_CNTL_RDRET_DATA_31[0]), 0, 0 },
	{ "ixMP_DRAM_CNTL_RDRET_DATA_32", REG_SMC, 0xcf2000d4, &ixMP_DRAM_CNTL_RDRET_DATA_32[0], sizeof(ixMP_DRAM_CNTL_RDRET_DATA_32)/sizeof(ixMP_DRAM_CNTL_RDRET_DATA_32[0]), 0, 0 },
	{ "ixMP_DRAM_CNTL_RDRET_DATA_33", REG_SMC, 0xcf2000d8, &ixMP_DRAM_CNTL_RDRET_DATA_33[0], sizeof(ixMP_DRAM_CNTL_RDRET_DATA_33)/sizeof(ixMP_DRAM_CNTL_RDRET_DATA_33[0]), 0, 0 },
	{ "ixMP_DRAM_CNTL_RDRET_DATA_34", REG_SMC, 0xcf2000dc, &ixMP_DRAM_CNTL_RDRET_DATA_34[0], sizeof(ixMP_DRAM_CNTL_RDRET_DATA_34)/sizeof(ixMP_DRAM_CNTL_RDRET_DATA_34[0]), 0, 0 },
	{ "ixMP_DRAM_CNTL_RDRET_DATA_35", REG_SMC, 0xcf2000e0, &ixMP_DRAM_CNTL_RDRET_DATA_35[0], sizeof(ixMP_DRAM_CNTL_RDRET_DATA_35)/sizeof(ixMP_DRAM_CNTL_RDRET_DATA_35[0]), 0, 0 },
	{ "ixMP_DRAM_CNTL_RDRET_DATA_36", REG_SMC, 0xcf2000e4, &ixMP_DRAM_CNTL_RDRET_DATA_36[0], sizeof(ixMP_DRAM_CNTL_RDRET_DATA_36)/sizeof(ixMP_DRAM_CNTL_RDRET_DATA_36[0]), 0, 0 },
	{ "ixMP_DRAM_CNTL_RDRET_DATA_37", REG_SMC, 0xcf2000e8, &ixMP_DRAM_CNTL_RDRET_DATA_37[0], sizeof(ixMP_DRAM_CNTL_RDRET_DATA_37)/sizeof(ixMP_DRAM_CNTL_RDRET_DATA_37[0]), 0, 0 },
	{ "ixMP_DRAM_CNTL_RDRET_DATA_38", REG_SMC, 0xcf2000ec, &ixMP_DRAM_CNTL_RDRET_DATA_38[0], sizeof(ixMP_DRAM_CNTL_RDRET_DATA_38)/sizeof(ixMP_DRAM_CNTL_RDRET_DATA_38[0]), 0, 0 },
	{ "ixMP_DRAM_CNTL_RDRET_DATA_39", REG_SMC, 0xcf2000f0, &ixMP_DRAM_CNTL_RDRET_DATA_39[0], sizeof(ixMP_DRAM_CNTL_RDRET_DATA_39)/sizeof(ixMP_DRAM_CNTL_RDRET_DATA_39[0]), 0, 0 },
	{ "ixMP_DRAM_CNTL_RDRET_DATA_40", REG_SMC, 0xcf2000f4, &ixMP_DRAM_CNTL_RDRET_DATA_40[0], sizeof(ixMP_DRAM_CNTL_RDRET_DATA_40)/sizeof(ixMP_DRAM_CNTL_RDRET_DATA_40[0]), 0, 0 },
	{ "ixMP_DRAM_CNTL_RDRET_DATA_41", REG_SMC, 0xcf2000f8, &ixMP_DRAM_CNTL_RDRET_DATA_41[0], sizeof(ixMP_DRAM_CNTL_RDRET_DATA_41)/sizeof(ixMP_DRAM_CNTL_RDRET_DATA_41[0]), 0, 0 },
	{ "ixMP_DRAM_CNTL_RDRET_DATA_42", REG_SMC, 0xcf2000fc, &ixMP_DRAM_CNTL_RDRET_DATA_42[0], sizeof(ixMP_DRAM_CNTL_RDRET_DATA_42)/sizeof(ixMP_DRAM_CNTL_RDRET_DATA_42[0]), 0, 0 },
	{ "ixMP_DRAM_CNTL_RDRET_DATA_43", REG_SMC, 0xcf200100, &ixMP_DRAM_CNTL_RDRET_DATA_43[0], sizeof(ixMP_DRAM_CNTL_RDRET_DATA_43)/sizeof(ixMP_DRAM_CNTL_RDRET_DATA_43[0]), 0, 0 },
	{ "ixMP_DRAM_CNTL_RDRET_DATA_44", REG_SMC, 0xcf200104, &ixMP_DRAM_CNTL_RDRET_DATA_44[0], sizeof(ixMP_DRAM_CNTL_RDRET_DATA_44)/sizeof(ixMP_DRAM_CNTL_RDRET_DATA_44[0]), 0, 0 },
	{ "ixMP_DRAM_CNTL_RDRET_DATA_45", REG_SMC, 0xcf200108, &ixMP_DRAM_CNTL_RDRET_DATA_45[0], sizeof(ixMP_DRAM_CNTL_RDRET_DATA_45)/sizeof(ixMP_DRAM_CNTL_RDRET_DATA_45[0]), 0, 0 },
	{ "ixMP_DRAM_CNTL_RDRET_DATA_46", REG_SMC, 0xcf20010c, &ixMP_DRAM_CNTL_RDRET_DATA_46[0], sizeof(ixMP_DRAM_CNTL_RDRET_DATA_46)/sizeof(ixMP_DRAM_CNTL_RDRET_DATA_46[0]), 0, 0 },
	{ "ixMP_DRAM_CNTL_RDRET_DATA_47", REG_SMC, 0xcf200110, &ixMP_DRAM_CNTL_RDRET_DATA_47[0], sizeof(ixMP_DRAM_CNTL_RDRET_DATA_47)/sizeof(ixMP_DRAM_CNTL_RDRET_DATA_47[0]), 0, 0 },
	{ "ixMP_DRAM_CNTL_RDRET_DATA_48", REG_SMC, 0xcf200114, &ixMP_DRAM_CNTL_RDRET_DATA_48[0], sizeof(ixMP_DRAM_CNTL_RDRET_DATA_48)/sizeof(ixMP_DRAM_CNTL_RDRET_DATA_48[0]), 0, 0 },
	{ "ixMP_DRAM_CNTL_RDRET_DATA_49", REG_SMC, 0xcf200118, &ixMP_DRAM_CNTL_RDRET_DATA_49[0], sizeof(ixMP_DRAM_CNTL_RDRET_DATA_49)/sizeof(ixMP_DRAM_CNTL_RDRET_DATA_49[0]), 0, 0 },
	{ "ixMP_DRAM_CNTL_RDRET_DATA_50", REG_SMC, 0xcf20011c, &ixMP_DRAM_CNTL_RDRET_DATA_50[0], sizeof(ixMP_DRAM_CNTL_RDRET_DATA_50)/sizeof(ixMP_DRAM_CNTL_RDRET_DATA_50[0]), 0, 0 },
	{ "ixMP_DRAM_CNTL_RDRET_DATA_51", REG_SMC, 0xcf200120, &ixMP_DRAM_CNTL_RDRET_DATA_51[0], sizeof(ixMP_DRAM_CNTL_RDRET_DATA_51)/sizeof(ixMP_DRAM_CNTL_RDRET_DATA_51[0]), 0, 0 },
	{ "ixMP_DRAM_CNTL_RDRET_DATA_52", REG_SMC, 0xcf200124, &ixMP_DRAM_CNTL_RDRET_DATA_52[0], sizeof(ixMP_DRAM_CNTL_RDRET_DATA_52)/sizeof(ixMP_DRAM_CNTL_RDRET_DATA_52[0]), 0, 0 },
	{ "ixMP_DRAM_CNTL_RDRET_DATA_53", REG_SMC, 0xcf200128, &ixMP_DRAM_CNTL_RDRET_DATA_53[0], sizeof(ixMP_DRAM_CNTL_RDRET_DATA_53)/sizeof(ixMP_DRAM_CNTL_RDRET_DATA_53[0]), 0, 0 },
	{ "ixMP_DRAM_CNTL_RDRET_DATA_54", REG_SMC, 0xcf20012c, &ixMP_DRAM_CNTL_RDRET_DATA_54[0], sizeof(ixMP_DRAM_CNTL_RDRET_DATA_54)/sizeof(ixMP_DRAM_CNTL_RDRET_DATA_54[0]), 0, 0 },
	{ "ixMP_DRAM_CNTL_RDRET_DATA_55", REG_SMC, 0xcf200130, &ixMP_DRAM_CNTL_RDRET_DATA_55[0], sizeof(ixMP_DRAM_CNTL_RDRET_DATA_55)/sizeof(ixMP_DRAM_CNTL_RDRET_DATA_55[0]), 0, 0 },
	{ "ixMP_DRAM_CNTL_RDRET_DATA_56", REG_SMC, 0xcf200134, &ixMP_DRAM_CNTL_RDRET_DATA_56[0], sizeof(ixMP_DRAM_CNTL_RDRET_DATA_56)/sizeof(ixMP_DRAM_CNTL_RDRET_DATA_56[0]), 0, 0 },
	{ "ixMP_DRAM_CNTL_RDRET_DATA_57", REG_SMC, 0xcf200138, &ixMP_DRAM_CNTL_RDRET_DATA_57[0], sizeof(ixMP_DRAM_CNTL_RDRET_DATA_57)/sizeof(ixMP_DRAM_CNTL_RDRET_DATA_57[0]), 0, 0 },
	{ "ixMP_DRAM_CNTL_RDRET_DATA_58", REG_SMC, 0xcf20013c, &ixMP_DRAM_CNTL_RDRET_DATA_58[0], sizeof(ixMP_DRAM_CNTL_RDRET_DATA_58)/sizeof(ixMP_DRAM_CNTL_RDRET_DATA_58[0]), 0, 0 },
	{ "ixMP_DRAM_CNTL_RDRET_DATA_59", REG_SMC, 0xcf200140, &ixMP_DRAM_CNTL_RDRET_DATA_59[0], sizeof(ixMP_DRAM_CNTL_RDRET_DATA_59)/sizeof(ixMP_DRAM_CNTL_RDRET_DATA_59[0]), 0, 0 },
	{ "ixMP_DRAM_CNTL_RDRET_DATA_60", REG_SMC, 0xcf200144, &ixMP_DRAM_CNTL_RDRET_DATA_60[0], sizeof(ixMP_DRAM_CNTL_RDRET_DATA_60)/sizeof(ixMP_DRAM_CNTL_RDRET_DATA_60[0]), 0, 0 },
	{ "ixMP_DRAM_CNTL_RDRET_DATA_61", REG_SMC, 0xcf200148, &ixMP_DRAM_CNTL_RDRET_DATA_61[0], sizeof(ixMP_DRAM_CNTL_RDRET_DATA_61)/sizeof(ixMP_DRAM_CNTL_RDRET_DATA_61[0]), 0, 0 },
	{ "ixMP_DRAM_CNTL_RDRET_DATA_62", REG_SMC, 0xcf20014c, &ixMP_DRAM_CNTL_RDRET_DATA_62[0], sizeof(ixMP_DRAM_CNTL_RDRET_DATA_62)/sizeof(ixMP_DRAM_CNTL_RDRET_DATA_62[0]), 0, 0 },
	{ "ixMP_DRAM_CNTL_RDRET_DATA_63", REG_SMC, 0xcf200150, &ixMP_DRAM_CNTL_RDRET_DATA_63[0], sizeof(ixMP_DRAM_CNTL_RDRET_DATA_63)/sizeof(ixMP_DRAM_CNTL_RDRET_DATA_63[0]), 0, 0 },
	{ "ixMP_INTERRUPT_CONTROL", REG_SMC, 0xcf200400, &ixMP_INTERRUPT_CONTROL[0], sizeof(ixMP_INTERRUPT_CONTROL)/sizeof(ixMP_INTERRUPT_CONTROL[0]), 0, 0 },
	{ "ixMP0_SW_INT", REG_SMC, 0xcf200404, &ixMP0_SW_INT[0], sizeof(ixMP0_SW_INT)/sizeof(ixMP0_SW_INT[0]), 0, 0 },
	{ "ixMP0_SW_INT_CTXID", REG_SMC, 0xcf200408, &ixMP0_SW_INT_CTXID[0], sizeof(ixMP0_SW_INT_CTXID)/sizeof(ixMP0_SW_INT_CTXID[0]), 0, 0 },
	{ "ixMP1_SW_INT", REG_SMC, 0xcf20040c, &ixMP1_SW_INT[0], sizeof(ixMP1_SW_INT)/sizeof(ixMP1_SW_INT[0]), 0, 0 },
	{ "ixMP1_SW_INT_CTXID", REG_SMC, 0xcf200410, &ixMP1_SW_INT_CTXID[0], sizeof(ixMP1_SW_INT_CTXID)/sizeof(ixMP1_SW_INT_CTXID[0]), 0, 0 },
	{ "ixDISP_TIMER_ID", REG_SMC, 0xcf200414, &ixDISP_TIMER_ID[0], sizeof(ixDISP_TIMER_ID)/sizeof(ixDISP_TIMER_ID[0]), 0, 0 },
	{ "ixMP_FPS_CNT_XBAR", REG_SMC, 0xcf200800, &ixMP_FPS_CNT_XBAR[0], sizeof(ixMP_FPS_CNT_XBAR)/sizeof(ixMP_FPS_CNT_XBAR[0]), 0, 0 },
	{ "ixMP_SRBM_CONFIG_XBAR", REG_SMC, 0xcf200804, &ixMP_SRBM_CONFIG_XBAR[0], sizeof(ixMP_SRBM_CONFIG_XBAR)/sizeof(ixMP_SRBM_CONFIG_XBAR[0]), 0, 0 },
	{ "ixMP_SRBM_CONTROL", REG_SMC, 0xcf200c00, &ixMP_SRBM_CONTROL[0], sizeof(ixMP_SRBM_CONTROL)/sizeof(ixMP_SRBM_CONTROL[0]), 0, 0 },
	{ "ixMP_SRBM_ACCVIO_LOG", REG_SMC, 0xcf200c04, &ixMP_SRBM_ACCVIO_LOG[0], sizeof(ixMP_SRBM_ACCVIO_LOG)/sizeof(ixMP_SRBM_ACCVIO_LOG[0]), 0, 0 },
	{ "ixMP_SRBM_ACCVIO_ADDR", REG_SMC, 0xcf200c08, &ixMP_SRBM_ACCVIO_ADDR[0], sizeof(ixMP_SRBM_ACCVIO_ADDR)/sizeof(ixMP_SRBM_ACCVIO_ADDR[0]), 0, 0 },
	{ "ixMP_CRBBM_CONTROL", REG_SMC, 0xcf200c0c, &ixMP_CRBBM_CONTROL[0], sizeof(ixMP_CRBBM_CONTROL)/sizeof(ixMP_CRBBM_CONTROL[0]), 0, 0 },
	{ "ixMP_CRBBM_ACCVIO_LOG", REG_SMC, 0xcf200c10, &ixMP_CRBBM_ACCVIO_LOG[0], sizeof(ixMP_CRBBM_ACCVIO_LOG)/sizeof(ixMP_CRBBM_ACCVIO_LOG[0]), 0, 0 },
	{ "ixMP_CRBBM_ACCVIO_ADDR", REG_SMC, 0xcf200c14, &ixMP_CRBBM_ACCVIO_ADDR[0], sizeof(ixMP_CRBBM_ACCVIO_ADDR)/sizeof(ixMP_CRBBM_ACCVIO_ADDR[0]), 0, 0 },
	{ "ixGENERAL_PWRMGT", REG_SMC, 0xd0200000, &ixGENERAL_PWRMGT[0], sizeof(ixGENERAL_PWRMGT)/sizeof(ixGENERAL_PWRMGT[0]), 0, 0 },
	{ "ixCNB_PWRMGT_CNTL", REG_SMC, 0xd0200004, &ixCNB_PWRMGT_CNTL[0], sizeof(ixCNB_PWRMGT_CNTL)/sizeof(ixCNB_PWRMGT_CNTL[0]), 0, 0 },
	{ "ixSCLK_PWRMGT_CNTL", REG_SMC, 0xd0200008, &ixSCLK_PWRMGT_CNTL[0], sizeof(ixSCLK_PWRMGT_CNTL)/sizeof(ixSCLK_PWRMGT_CNTL[0]), 0, 0 },
	{ "ixTARGET_AND_CURRENT_PROFILE_INDEX", REG_SMC, 0xd0200014, &ixTARGET_AND_CURRENT_PROFILE_INDEX[0], sizeof(ixTARGET_AND_CURRENT_PROFILE_INDEX)/sizeof(ixTARGET_AND_CURRENT_PROFILE_INDEX[0]), 0, 0 },
	{ "ixCG_STATIC_SCREEN_PARAMETER", REG_SMC, 0xd0200044, &ixCG_STATIC_SCREEN_PARAMETER[0], sizeof(ixCG_STATIC_SCREEN_PARAMETER)/sizeof(ixCG_STATIC_SCREEN_PARAMETER[0]), 0, 0 },
	{ "ixCG_ACPI_CNTL", REG_SMC, 0xd0200064, &ixCG_ACPI_CNTL[0], sizeof(ixCG_ACPI_CNTL)/sizeof(ixCG_ACPI_CNTL[0]), 0, 0 },
	{ "ixSCLK_DEEP_SLEEP_CNTL", REG_SMC, 0xd0200080, &ixSCLK_DEEP_SLEEP_CNTL[0], sizeof(ixSCLK_DEEP_SLEEP_CNTL)/sizeof(ixSCLK_DEEP_SLEEP_CNTL[0]), 0, 0 },
	{ "ixSCLK_DEEP_SLEEP_CNTL2", REG_SMC, 0xd0200084, &ixSCLK_DEEP_SLEEP_CNTL2[0], sizeof(ixSCLK_DEEP_SLEEP_CNTL2)/sizeof(ixSCLK_DEEP_SLEEP_CNTL2[0]), 0, 0 },
	{ "ixSCLK_DEEP_SLEEP_MISC_CNTL", REG_SMC, 0xd0200088, &ixSCLK_DEEP_SLEEP_MISC_CNTL[0], sizeof(ixSCLK_DEEP_SLEEP_MISC_CNTL)/sizeof(ixSCLK_DEEP_SLEEP_MISC_CNTL[0]), 0, 0 },
	{ "ixLCLK_DEEP_SLEEP_CNTL", REG_SMC, 0xd020008c, &ixLCLK_DEEP_SLEEP_CNTL[0], sizeof(ixLCLK_DEEP_SLEEP_CNTL)/sizeof(ixLCLK_DEEP_SLEEP_CNTL[0]), 0, 0 },
	{ "ixSMU_VOLTAGE_STATUS", REG_SMC, 0xd0200094, &ixSMU_VOLTAGE_STATUS[0], sizeof(ixSMU_VOLTAGE_STATUS)/sizeof(ixSMU_VOLTAGE_STATUS[0]), 0, 0 },
	{ "ixSCLK_DEEP_SLEEP_CNTL3", REG_SMC, 0xd020009c, &ixSCLK_DEEP_SLEEP_CNTL3[0], sizeof(ixSCLK_DEEP_SLEEP_CNTL3)/sizeof(ixSCLK_DEEP_SLEEP_CNTL3[0]), 0, 0 },
	{ "ixTARGET_AND_CURRENT_PROFILE_INDEX_1", REG_SMC, 0xd02000f0, &ixTARGET_AND_CURRENT_PROFILE_INDEX_1[0], sizeof(ixTARGET_AND_CURRENT_PROFILE_INDEX_1)/sizeof(ixTARGET_AND_CURRENT_PROFILE_INDEX_1[0]), 0, 0 },
	{ "ixTARGET_AND_CURRENT_PROFILE_INDEX_2", REG_SMC, 0xd02000f4, &ixTARGET_AND_CURRENT_PROFILE_INDEX_2[0], sizeof(ixTARGET_AND_CURRENT_PROFILE_INDEX_2)/sizeof(ixTARGET_AND_CURRENT_PROFILE_INDEX_2[0]), 0, 0 },
	{ "ixCG_ULV_PARAMETER", REG_SMC, 0xd020015c, &ixCG_ULV_PARAMETER[0], sizeof(ixCG_ULV_PARAMETER)/sizeof(ixCG_ULV_PARAMETER[0]), 0, 0 },
	{ "ixCG_FREQ_TRAN_VOTING_0", REG_SMC, 0xd02001a8, &ixCG_FREQ_TRAN_VOTING_0[0], sizeof(ixCG_FREQ_TRAN_VOTING_0)/sizeof(ixCG_FREQ_TRAN_VOTING_0[0]), 0, 0 },
	{ "ixCG_FREQ_TRAN_VOTING_1", REG_SMC, 0xd02001ac, &ixCG_FREQ_TRAN_VOTING_1[0], sizeof(ixCG_FREQ_TRAN_VOTING_1)/sizeof(ixCG_FREQ_TRAN_VOTING_1[0]), 0, 0 },
	{ "ixCG_FREQ_TRAN_VOTING_2", REG_SMC, 0xd02001b0, &ixCG_FREQ_TRAN_VOTING_2[0], sizeof(ixCG_FREQ_TRAN_VOTING_2)/sizeof(ixCG_FREQ_TRAN_VOTING_2[0]), 0, 0 },
	{ "ixCG_FREQ_TRAN_VOTING_3", REG_SMC, 0xd02001b4, &ixCG_FREQ_TRAN_VOTING_3[0], sizeof(ixCG_FREQ_TRAN_VOTING_3)/sizeof(ixCG_FREQ_TRAN_VOTING_3[0]), 0, 0 },
	{ "ixCG_FREQ_TRAN_VOTING_4", REG_SMC, 0xd02001b8, &ixCG_FREQ_TRAN_VOTING_4[0], sizeof(ixCG_FREQ_TRAN_VOTING_4)/sizeof(ixCG_FREQ_TRAN_VOTING_4[0]), 0, 0 },
	{ "ixCG_FREQ_TRAN_VOTING_5", REG_SMC, 0xd02001bc, &ixCG_FREQ_TRAN_VOTING_5[0], sizeof(ixCG_FREQ_TRAN_VOTING_5)/sizeof(ixCG_FREQ_TRAN_VOTING_5[0]), 0, 0 },
	{ "ixCG_FREQ_TRAN_VOTING_6", REG_SMC, 0xd02001c0, &ixCG_FREQ_TRAN_VOTING_6[0], sizeof(ixCG_FREQ_TRAN_VOTING_6)/sizeof(ixCG_FREQ_TRAN_VOTING_6[0]), 0, 0 },
	{ "ixCG_FREQ_TRAN_VOTING_7", REG_SMC, 0xd02001c4, &ixCG_FREQ_TRAN_VOTING_7[0], sizeof(ixCG_FREQ_TRAN_VOTING_7)/sizeof(ixCG_FREQ_TRAN_VOTING_7[0]), 0, 0 },
	{ "ixPCIE_PGFSM_CONFIG", REG_SMC, 0xd02002d0, &ixPCIE_PGFSM_CONFIG[0], sizeof(ixPCIE_PGFSM_CONFIG)/sizeof(ixPCIE_PGFSM_CONFIG[0]), 0, 0 },
	{ "ixPCIE_PGFSM_WRITE", REG_SMC, 0xd02002d4, &ixPCIE_PGFSM_WRITE[0], sizeof(ixPCIE_PGFSM_WRITE)/sizeof(ixPCIE_PGFSM_WRITE[0]), 0, 0 },
	{ "ixSERDES_BUSY", REG_SMC, 0xd02002d8, &ixSERDES_BUSY[0], sizeof(ixSERDES_BUSY)/sizeof(ixSERDES_BUSY[0]), 0, 0 },
	{ "ixPCIE_PGFSM2_CONFIG", REG_SMC, 0xd02002dc, &ixPCIE_PGFSM2_CONFIG[0], sizeof(ixPCIE_PGFSM2_CONFIG)/sizeof(ixPCIE_PGFSM2_CONFIG[0]), 0, 0 },
	{ "ixPCIE_PGFSM2_WRITE", REG_SMC, 0xd02002e0, &ixPCIE_PGFSM2_WRITE[0], sizeof(ixPCIE_PGFSM2_WRITE)/sizeof(ixPCIE_PGFSM2_WRITE[0]), 0, 0 },
	{ "ixSERDES2_BUSY", REG_SMC, 0xd02002e4, &ixSERDES2_BUSY[0], sizeof(ixSERDES2_BUSY)/sizeof(ixSERDES2_BUSY[0]), 0, 0 },
	{ "ixPCIE_PGFSM_0_READ", REG_SMC, 0xd02002e8, &ixPCIE_PGFSM_0_READ[0], sizeof(ixPCIE_PGFSM_0_READ)/sizeof(ixPCIE_PGFSM_0_READ[0]), 0, 0 },
	{ "ixPCIE_PGFSM_1_READ", REG_SMC, 0xd02002ec, &ixPCIE_PGFSM_1_READ[0], sizeof(ixPCIE_PGFSM_1_READ)/sizeof(ixPCIE_PGFSM_1_READ[0]), 0, 0 },
	{ "ixPWR_DC_RESP", REG_SMC, 0xd0200300, &ixPWR_DC_RESP[0], sizeof(ixPWR_DC_RESP)/sizeof(ixPWR_DC_RESP[0]), 0, 0 },
	{ "ixPWR_VCE_RESP", REG_SMC, 0xd0200304, &ixPWR_VCE_RESP[0], sizeof(ixPWR_VCE_RESP)/sizeof(ixPWR_VCE_RESP[0]), 0, 0 },
	{ "ixPWR_UVD_RESP", REG_SMC, 0xd0200308, &ixPWR_UVD_RESP[0], sizeof(ixPWR_UVD_RESP)/sizeof(ixPWR_UVD_RESP[0]), 0, 0 },
	{ "ixPWR_ACP_RESP", REG_SMC, 0xd020030c, &ixPWR_ACP_RESP[0], sizeof(ixPWR_ACP_RESP)/sizeof(ixPWR_ACP_RESP[0]), 0, 0 },
	{ "ixLCLK_DEEP_SLEEP_CNTL2", REG_SMC, 0xd0200310, &ixLCLK_DEEP_SLEEP_CNTL2[0], sizeof(ixLCLK_DEEP_SLEEP_CNTL2)/sizeof(ixLCLK_DEEP_SLEEP_CNTL2[0]), 0, 0 },
	{ "ixPWR_ACPI_INTERRUPT", REG_SMC, 0xd0200318, &ixPWR_ACPI_INTERRUPT[0], sizeof(ixPWR_ACPI_INTERRUPT)/sizeof(ixPWR_ACPI_INTERRUPT[0]), 0, 0 },
	{ "ixPWR_DC_REQ", REG_SMC, 0xd020031c, &ixPWR_DC_REQ[0], sizeof(ixPWR_DC_REQ)/sizeof(ixPWR_DC_REQ[0]), 0, 0 },
	{ "ixVDDGFX_IDLE_PARAMETER", REG_SMC, 0xd020036c, &ixVDDGFX_IDLE_PARAMETER[0], sizeof(ixVDDGFX_IDLE_PARAMETER)/sizeof(ixVDDGFX_IDLE_PARAMETER[0]), 0, 0 },
	{ "ixVDDGFX_IDLE_CONTROL", REG_SMC, 0xd0200370, &ixVDDGFX_IDLE_CONTROL[0], sizeof(ixVDDGFX_IDLE_CONTROL)/sizeof(ixVDDGFX_IDLE_CONTROL[0]), 0, 0 },
	{ "ixVDDGFX_IDLE_EXIT", REG_SMC, 0xd0200374, &ixVDDGFX_IDLE_EXIT[0], sizeof(ixVDDGFX_IDLE_EXIT)/sizeof(ixVDDGFX_IDLE_EXIT[0]), 0, 0 },
	{ "ixREG_SCLK_DEEP_SLEEP_EXIT", REG_SMC, 0xd0200378, &ixREG_SCLK_DEEP_SLEEP_EXIT[0], sizeof(ixREG_SCLK_DEEP_SLEEP_EXIT)/sizeof(ixREG_SCLK_DEEP_SLEEP_EXIT[0]), 0, 0 },
	{ "ixSCLK_MIN_DIV", REG_SMC, 0xd02003ac, &ixSCLK_MIN_DIV[0], sizeof(ixSCLK_MIN_DIV)/sizeof(ixSCLK_MIN_DIV[0]), 0, 0 },
	{ "ixCAC_WEIGHT_LKG_DC_3", REG_SMC, 0xd020803c, &ixCAC_WEIGHT_LKG_DC_3[0], sizeof(ixCAC_WEIGHT_LKG_DC_3)/sizeof(ixCAC_WEIGHT_LKG_DC_3[0]), 0, 0 },
	{ "ixLCAC_MC0_CNTL", REG_SMC, 0xd0208130, &ixLCAC_MC0_CNTL[0], sizeof(ixLCAC_MC0_CNTL)/sizeof(ixLCAC_MC0_CNTL[0]), 0, 0 },
	{ "ixLCAC_MC0_OVR_SEL", REG_SMC, 0xd0208134, &ixLCAC_MC0_OVR_SEL[0], sizeof(ixLCAC_MC0_OVR_SEL)/sizeof(ixLCAC_MC0_OVR_SEL[0]), 0, 0 },
	{ "ixLCAC_MC0_OVR_VAL", REG_SMC, 0xd0208138, &ixLCAC_MC0_OVR_VAL[0], sizeof(ixLCAC_MC0_OVR_VAL)/sizeof(ixLCAC_MC0_OVR_VAL[0]), 0, 0 },
	{ "ixLCAC_MC1_CNTL", REG_SMC, 0xd020813c, &ixLCAC_MC1_CNTL[0], sizeof(ixLCAC_MC1_CNTL)/sizeof(ixLCAC_MC1_CNTL[0]), 0, 0 },
	{ "ixLCAC_MC1_OVR_SEL", REG_SMC, 0xd0208140, &ixLCAC_MC1_OVR_SEL[0], sizeof(ixLCAC_MC1_OVR_SEL)/sizeof(ixLCAC_MC1_OVR_SEL[0]), 0, 0 },
	{ "ixLCAC_MC1_OVR_VAL", REG_SMC, 0xd0208144, &ixLCAC_MC1_OVR_VAL[0], sizeof(ixLCAC_MC1_OVR_VAL)/sizeof(ixLCAC_MC1_OVR_VAL[0]), 0, 0 },
	{ "ixLCAC_MC2_CNTL", REG_SMC, 0xd0208148, &ixLCAC_MC2_CNTL[0], sizeof(ixLCAC_MC2_CNTL)/sizeof(ixLCAC_MC2_CNTL[0]), 0, 0 },
	{ "ixLCAC_MC2_OVR_SEL", REG_SMC, 0xd020814c, &ixLCAC_MC2_OVR_SEL[0], sizeof(ixLCAC_MC2_OVR_SEL)/sizeof(ixLCAC_MC2_OVR_SEL[0]), 0, 0 },
	{ "ixLCAC_MC2_OVR_VAL", REG_SMC, 0xd0208150, &ixLCAC_MC2_OVR_VAL[0], sizeof(ixLCAC_MC2_OVR_VAL)/sizeof(ixLCAC_MC2_OVR_VAL[0]), 0, 0 },
	{ "ixLCAC_MC3_CNTL", REG_SMC, 0xd0208154, &ixLCAC_MC3_CNTL[0], sizeof(ixLCAC_MC3_CNTL)/sizeof(ixLCAC_MC3_CNTL[0]), 0, 0 },
	{ "ixLCAC_MC3_OVR_SEL", REG_SMC, 0xd0208158, &ixLCAC_MC3_OVR_SEL[0], sizeof(ixLCAC_MC3_OVR_SEL)/sizeof(ixLCAC_MC3_OVR_SEL[0]), 0, 0 },
	{ "ixLCAC_MC3_OVR_VAL", REG_SMC, 0xd020815c, &ixLCAC_MC3_OVR_VAL[0], sizeof(ixLCAC_MC3_OVR_VAL)/sizeof(ixLCAC_MC3_OVR_VAL[0]), 0, 0 },
	{ "ixLCAC_CPL_CNTL", REG_SMC, 0xd0208160, &ixLCAC_CPL_CNTL[0], sizeof(ixLCAC_CPL_CNTL)/sizeof(ixLCAC_CPL_CNTL[0]), 0, 0 },
	{ "ixLCAC_CPL_OVR_SEL", REG_SMC, 0xd0208164, &ixLCAC_CPL_OVR_SEL[0], sizeof(ixLCAC_CPL_OVR_SEL)/sizeof(ixLCAC_CPL_OVR_SEL[0]), 0, 0 },
	{ "ixLCAC_CPL_OVR_VAL", REG_SMC, 0xd0208168, &ixLCAC_CPL_OVR_VAL[0], sizeof(ixLCAC_CPL_OVR_VAL)/sizeof(ixLCAC_CPL_OVR_VAL[0]), 0, 0 },
	{ "ixMISC_UNB_PWRMGT_CFG0", REG_SMC, 0xd020c000, &ixMISC_UNB_PWRMGT_CFG0[0], sizeof(ixMISC_UNB_PWRMGT_CFG0)/sizeof(ixMISC_UNB_PWRMGT_CFG0[0]), 0, 0 },
	{ "ixMISC_UNB_PWRMGT_CFG1", REG_SMC, 0xd020c004, &ixMISC_UNB_PWRMGT_CFG1[0], sizeof(ixMISC_UNB_PWRMGT_CFG1)/sizeof(ixMISC_UNB_PWRMGT_CFG1[0]), 0, 0 },
	{ "ixMISC_UNB_PWRMGT_DATA", REG_SMC, 0xd020c00c, &ixMISC_UNB_PWRMGT_DATA[0], sizeof(ixMISC_UNB_PWRMGT_DATA)/sizeof(ixMISC_UNB_PWRMGT_DATA[0]), 0, 0 },
	{ "ixGNBPM_SMU_PWRMGT_DATA", REG_SMC, 0xd020c010, &ixGNBPM_SMU_PWRMGT_DATA[0], sizeof(ixGNBPM_SMU_PWRMGT_DATA)/sizeof(ixGNBPM_SMU_PWRMGT_DATA[0]), 0, 0 },
	{ "ixDMA_ACTIVE_SAMPLER_CFG", REG_SMC, 0xd020c014, &ixDMA_ACTIVE_SAMPLER_CFG[0], sizeof(ixDMA_ACTIVE_SAMPLER_CFG)/sizeof(ixDMA_ACTIVE_SAMPLER_CFG[0]), 0, 0 },
	{ "ixSOUTHBRIDGE_TYPE", REG_SMC, 0xd020c01c, &ixSOUTHBRIDGE_TYPE[0], sizeof(ixSOUTHBRIDGE_TYPE)/sizeof(ixSOUTHBRIDGE_TYPE[0]), 0, 0 },
	{ "ixGNBPM_SMU_PWRMGT_STATUS", REG_SMC, 0xd020c020, &ixGNBPM_SMU_PWRMGT_STATUS[0], sizeof(ixGNBPM_SMU_PWRMGT_STATUS)/sizeof(ixGNBPM_SMU_PWRMGT_STATUS[0]), 0, 0 },
	{ "ixALLOW_SR_INTR_CTRL", REG_SMC, 0xd020c024, &ixALLOW_SR_INTR_CTRL[0], sizeof(ixALLOW_SR_INTR_CTRL)/sizeof(ixALLOW_SR_INTR_CTRL[0]), 0, 0 },
	{ "ixCURRENT_STATE_CPU0", REG_SMC, 0xd0210000, &ixCURRENT_STATE_CPU0[0], sizeof(ixCURRENT_STATE_CPU0)/sizeof(ixCURRENT_STATE_CPU0[0]), 0, 0 },
	{ "ixCPU_REDUN_DONE0", REG_SMC, 0xd0210004, &ixCPU_REDUN_DONE0[0], sizeof(ixCPU_REDUN_DONE0)/sizeof(ixCPU_REDUN_DONE0[0]), 0, 0 },
	{ "ixCURRENT_VID_CPU0", REG_SMC, 0xd0210008, &ixCURRENT_VID_CPU0[0], sizeof(ixCURRENT_VID_CPU0)/sizeof(ixCURRENT_VID_CPU0[0]), 0, 0 },
	{ "ixCURRENT_STATE_CPU1", REG_SMC, 0xd0210010, &ixCURRENT_STATE_CPU1[0], sizeof(ixCURRENT_STATE_CPU1)/sizeof(ixCURRENT_STATE_CPU1[0]), 0, 0 },
	{ "ixCPU_REDUN_DONE1", REG_SMC, 0xd0210014, &ixCPU_REDUN_DONE1[0], sizeof(ixCPU_REDUN_DONE1)/sizeof(ixCPU_REDUN_DONE1[0]), 0, 0 },
	{ "ixCURRENT_VID_CPU1", REG_SMC, 0xd0210018, &ixCURRENT_VID_CPU1[0], sizeof(ixCURRENT_VID_CPU1)/sizeof(ixCURRENT_VID_CPU1[0]), 0, 0 },
	{ "ixUNBPM_PWRMGT_ACK", REG_SMC, 0xd0211000, &ixUNBPM_PWRMGT_ACK[0], sizeof(ixUNBPM_PWRMGT_ACK)/sizeof(ixUNBPM_PWRMGT_ACK[0]), 0, 0 },
	{ "ixCURRENT_FREQ_STATE_NB", REG_SMC, 0xd0211004, &ixCURRENT_FREQ_STATE_NB[0], sizeof(ixCURRENT_FREQ_STATE_NB)/sizeof(ixCURRENT_FREQ_STATE_NB[0]), 0, 0 },
	{ "ixCURRENT_PSTATE_NB", REG_SMC, 0xd0211008, &ixCURRENT_PSTATE_NB[0], sizeof(ixCURRENT_PSTATE_NB)/sizeof(ixCURRENT_PSTATE_NB[0]), 0, 0 },
	{ "ixUNBPM_MSG_INT_CONFIG", REG_SMC, 0xd021100c, &ixUNBPM_MSG_INT_CONFIG[0], sizeof(ixUNBPM_MSG_INT_CONFIG)/sizeof(ixUNBPM_MSG_INT_CONFIG[0]), 0, 0 },
	{ "ixUNBPM_NBPWRMGT_CMD", REG_SMC, 0xd0211010, &ixUNBPM_NBPWRMGT_CMD[0], sizeof(ixUNBPM_NBPWRMGT_CMD)/sizeof(ixUNBPM_NBPWRMGT_CMD[0]), 0, 0 },
	{ "ixUNBPM_NBPWRMGT_FSM_CFG", REG_SMC, 0xd0211014, &ixUNBPM_NBPWRMGT_FSM_CFG[0], sizeof(ixUNBPM_NBPWRMGT_FSM_CFG)/sizeof(ixUNBPM_NBPWRMGT_FSM_CFG[0]), 0, 0 },
	{ "ixDDR0_FUSE_SSB_XFER", REG_SMC, 0xd0211018, &ixDDR0_FUSE_SSB_XFER[0], sizeof(ixDDR0_FUSE_SSB_XFER)/sizeof(ixDDR0_FUSE_SSB_XFER[0]), 0, 0 },
	{ "ixDDR0_FUSE_SSB_XFER_CFG", REG_SMC, 0xd021101c, &ixDDR0_FUSE_SSB_XFER_CFG[0], sizeof(ixDDR0_FUSE_SSB_XFER_CFG)/sizeof(ixDDR0_FUSE_SSB_XFER_CFG[0]), 0, 0 },
	{ "ixDDR1_FUSE_SSB_XFER", REG_SMC, 0xd0211020, &ixDDR1_FUSE_SSB_XFER[0], sizeof(ixDDR1_FUSE_SSB_XFER)/sizeof(ixDDR1_FUSE_SSB_XFER[0]), 0, 0 },
	{ "ixDDR1_FUSE_SSB_XFER_CFG", REG_SMC, 0xd0211024, &ixDDR1_FUSE_SSB_XFER_CFG[0], sizeof(ixDDR1_FUSE_SSB_XFER_CFG)/sizeof(ixDDR1_FUSE_SSB_XFER_CFG[0]), 0, 0 },
	{ "ixUNBPM_FUSES_VAL_PWROK", REG_SMC, 0xd0211028, &ixUNBPM_FUSES_VAL_PWROK[0], sizeof(ixUNBPM_FUSES_VAL_PWROK)/sizeof(ixUNBPM_FUSES_VAL_PWROK[0]), 0, 0 },
	{ "ixSYNFIFO_CLK_RATIO", REG_SMC, 0xd021102c, &ixSYNFIFO_CLK_RATIO[0], sizeof(ixSYNFIFO_CLK_RATIO)/sizeof(ixSYNFIFO_CLK_RATIO[0]), 0, 0 },
	{ "ixMISC_SMU_PWRMGT_CFG0", REG_SMC, 0xd0211030, &ixMISC_SMU_PWRMGT_CFG0[0], sizeof(ixMISC_SMU_PWRMGT_CFG0)/sizeof(ixMISC_SMU_PWRMGT_CFG0[0]), 0, 0 },
	{ "ixMISC_GNB_PWRMGT_CFG1", REG_SMC, 0xd0211034, &ixMISC_GNB_PWRMGT_CFG1[0], sizeof(ixMISC_GNB_PWRMGT_CFG1)/sizeof(ixMISC_GNB_PWRMGT_CFG1[0]), 0, 0 },
	{ "ixMISC_SMU_PWRMGT_CFG1", REG_SMC, 0xd0211038, &ixMISC_SMU_PWRMGT_CFG1[0], sizeof(ixMISC_SMU_PWRMGT_CFG1)/sizeof(ixMISC_SMU_PWRMGT_CFG1[0]), 0, 0 },
	{ "ixMISC_GNB_PWRMGT_DATA", REG_SMC, 0xd021103c, &ixMISC_GNB_PWRMGT_DATA[0], sizeof(ixMISC_GNB_PWRMGT_DATA)/sizeof(ixMISC_GNB_PWRMGT_DATA[0]), 0, 0 },
	{ "ixGN_GNB_SLOW", REG_SMC, 0xd0211040, &ixGN_GNB_SLOW[0], sizeof(ixGN_GNB_SLOW)/sizeof(ixGN_GNB_SLOW[0]), 0, 0 },
	{ "ixGN_FORCE_NBPS1", REG_SMC, 0xd0211044, &ixGN_FORCE_NBPS1[0], sizeof(ixGN_FORCE_NBPS1)/sizeof(ixGN_FORCE_NBPS1[0]), 0, 0 },
	{ "ixMISC_SMU_PWRMGT_DATA", REG_SMC, 0xd0211048, &ixMISC_SMU_PWRMGT_DATA[0], sizeof(ixMISC_SMU_PWRMGT_DATA)/sizeof(ixMISC_SMU_PWRMGT_DATA[0]), 0, 0 },
	{ "ixNB_COF", REG_SMC, 0xd021104c, &ixNB_COF[0], sizeof(ixNB_COF)/sizeof(ixNB_COF[0]), 0, 0 },
	{ "ixUNBPM_CK_IRESET", REG_SMC, 0xd0211050, &ixUNBPM_CK_IRESET[0], sizeof(ixUNBPM_CK_IRESET)/sizeof(ixUNBPM_CK_IRESET[0]), 0, 0 },
	{ "ixCURRENT_VID_NB", REG_SMC, 0xd0211054, &ixCURRENT_VID_NB[0], sizeof(ixCURRENT_VID_NB)/sizeof(ixCURRENT_VID_NB[0]), 0, 0 },
	{ "ixSPR_FUSE_PSTATEPWR1", REG_SMC, 0xd0211058, &ixSPR_FUSE_PSTATEPWR1[0], sizeof(ixSPR_FUSE_PSTATEPWR1)/sizeof(ixSPR_FUSE_PSTATEPWR1[0]), 0, 0 },
	{ "ixSPR_FUSE_PSTATEPWR2", REG_SMC, 0xd021105c, &ixSPR_FUSE_PSTATEPWR2[0], sizeof(ixSPR_FUSE_PSTATEPWR2)/sizeof(ixSPR_FUSE_PSTATEPWR2[0]), 0, 0 },
	{ "ixSPR_FUSE_PSTATEPWR3", REG_SMC, 0xd0211060, &ixSPR_FUSE_PSTATEPWR3[0], sizeof(ixSPR_FUSE_PSTATEPWR3)/sizeof(ixSPR_FUSE_PSTATEPWR3[0]), 0, 0 },
	{ "ixSPR_FUSE_THERMAL_SCRATCH", REG_SMC, 0xd0211064, &ixSPR_FUSE_THERMAL_SCRATCH[0], sizeof(ixSPR_FUSE_THERMAL_SCRATCH)/sizeof(ixSPR_FUSE_THERMAL_SCRATCH[0]), 0, 0 },
	{ "ixSPR_PRODUCT_INFO0", REG_SMC, 0xd0211068, &ixSPR_PRODUCT_INFO0[0], sizeof(ixSPR_PRODUCT_INFO0)/sizeof(ixSPR_PRODUCT_INFO0[0]), 0, 0 },
	{ "ixSPR_SERIALNUM_REG1", REG_SMC, 0xd021106c, &ixSPR_SERIALNUM_REG1[0], sizeof(ixSPR_SERIALNUM_REG1)/sizeof(ixSPR_SERIALNUM_REG1[0]), 0, 0 },
	{ "ixSPR_SERIALNUM_REG2", REG_SMC, 0xd0211070, &ixSPR_SERIALNUM_REG2[0], sizeof(ixSPR_SERIALNUM_REG2)/sizeof(ixSPR_SERIALNUM_REG2[0]), 0, 0 },
	{ "ixSPR_PRODUCT_INFO1", REG_SMC, 0xd0211074, &ixSPR_PRODUCT_INFO1[0], sizeof(ixSPR_PRODUCT_INFO1)/sizeof(ixSPR_PRODUCT_INFO1[0]), 0, 0 },
	{ "ixSPR_EXT_PRODUCT_INFO", REG_SMC, 0xd021107c, &ixSPR_EXT_PRODUCT_INFO[0], sizeof(ixSPR_EXT_PRODUCT_INFO)/sizeof(ixSPR_EXT_PRODUCT_INFO[0]), 0, 0 },
	{ "ixSPR_MSIDFUSE", REG_SMC, 0xd0211080, &ixSPR_MSIDFUSE[0], sizeof(ixSPR_MSIDFUSE)/sizeof(ixSPR_MSIDFUSE[0]), 0, 0 },
	{ "ixSPR_LINK_PRODUCT_INFO", REG_SMC, 0xd0211084, &ixSPR_LINK_PRODUCT_INFO[0], sizeof(ixSPR_LINK_PRODUCT_INFO)/sizeof(ixSPR_LINK_PRODUCT_INFO[0]), 0, 0 },
	{ "ixSPR_BRAND_NAME_ADDR", REG_SMC, 0xd0211088, &ixSPR_BRAND_NAME_ADDR[0], sizeof(ixSPR_BRAND_NAME_ADDR)/sizeof(ixSPR_BRAND_NAME_ADDR[0]), 0, 0 },
	{ "ixSPR_BRAND_NAME_DATA", REG_SMC, 0xd021108c, &ixSPR_BRAND_NAME_DATA[0], sizeof(ixSPR_BRAND_NAME_DATA)/sizeof(ixSPR_BRAND_NAME_DATA[0]), 0, 0 },
	{ "ixSPR_COMBO_PHY_PRODUCT_INFO", REG_SMC, 0xd0211090, &ixSPR_COMBO_PHY_PRODUCT_INFO[0], sizeof(ixSPR_COMBO_PHY_PRODUCT_INFO)/sizeof(ixSPR_COMBO_PHY_PRODUCT_INFO[0]), 0, 0 },
	{ "ixMISC_GNB_PWRMGT_CFG0", REG_SMC, 0xd0211094, &ixMISC_GNB_PWRMGT_CFG0[0], sizeof(ixMISC_GNB_PWRMGT_CFG0)/sizeof(ixMISC_GNB_PWRMGT_CFG0[0]), 0, 0 },
	{ "ixUNBPM_EXIT_TO_PSTATE", REG_SMC, 0xd0211098, &ixUNBPM_EXIT_TO_PSTATE[0], sizeof(ixUNBPM_EXIT_TO_PSTATE)/sizeof(ixUNBPM_EXIT_TO_PSTATE[0]), 0, 0 },
	{ "ixUNBPM_WARM_RESET_HS_STATUS", REG_SMC, 0xd021109c, &ixUNBPM_WARM_RESET_HS_STATUS[0], sizeof(ixUNBPM_WARM_RESET_HS_STATUS)/sizeof(ixUNBPM_WARM_RESET_HS_STATUS[0]), 0, 0 },
	{ "ixUNBPM_VOLTAGE_CNTL", REG_SMC, 0xd02110a0, &ixUNBPM_VOLTAGE_CNTL[0], sizeof(ixUNBPM_VOLTAGE_CNTL)/sizeof(ixUNBPM_VOLTAGE_CNTL[0]), 0, 0 },
	{ "ixUNBPM_VOLTAGE_STATUS", REG_SMC, 0xd02110a4, &ixUNBPM_VOLTAGE_STATUS[0], sizeof(ixUNBPM_VOLTAGE_STATUS)/sizeof(ixUNBPM_VOLTAGE_STATUS[0]), 0, 0 },
	{ "ixNUM_BOOST_STATES", REG_SMC, 0xd02110a8, &ixNUM_BOOST_STATES[0], sizeof(ixNUM_BOOST_STATES)/sizeof(ixNUM_BOOST_STATES[0]), 0, 0 },
	{ "ixWARM_RESET_NB_CONTROL", REG_SMC, 0xd02110ac, &ixWARM_RESET_NB_CONTROL[0], sizeof(ixWARM_RESET_NB_CONTROL)/sizeof(ixWARM_RESET_NB_CONTROL[0]), 0, 0 },
	{ "ixONION_NO_STREAMS_PEND", REG_SMC, 0xd02110b0, &ixONION_NO_STREAMS_PEND[0], sizeof(ixONION_NO_STREAMS_PEND)/sizeof(ixONION_NO_STREAMS_PEND[0]), 0, 0 },
	{ "ixSPR_PROGRAMMABLE_CTRL", REG_SMC, 0xd02110b4, &ixSPR_PROGRAMMABLE_CTRL[0], sizeof(ixSPR_PROGRAMMABLE_CTRL)/sizeof(ixSPR_PROGRAMMABLE_CTRL[0]), 0, 0 },
	{ "ixPHN_FUSERX_MISC_FUSES", REG_SMC, 0xd02110b8, &ixPHN_FUSERX_MISC_FUSES[0], sizeof(ixPHN_FUSERX_MISC_FUSES)/sizeof(ixPHN_FUSERX_MISC_FUSES[0]), 0, 0 },
	{ "ixUNBPM_PWRCTRL_MISC", REG_SMC, 0xd02110bc, &ixUNBPM_PWRCTRL_MISC[0], sizeof(ixUNBPM_PWRCTRL_MISC)/sizeof(ixUNBPM_PWRCTRL_MISC[0]), 0, 0 },
	{ "ixCSTATE_ACTIVE_SAMPLER", REG_SMC, 0xd02110c0, &ixCSTATE_ACTIVE_SAMPLER[0], sizeof(ixCSTATE_ACTIVE_SAMPLER)/sizeof(ixCSTATE_ACTIVE_SAMPLER[0]), 0, 0 },
	{ "ixUNBPM_DEBUG_CONFIG_STATUS", REG_SMC, 0xd02110c4, &ixUNBPM_DEBUG_CONFIG_STATUS[0], sizeof(ixUNBPM_DEBUG_CONFIG_STATUS)/sizeof(ixUNBPM_DEBUG_CONFIG_STATUS[0]), 0, 0 },
	{ "ixUNBPM_AXIMST_LAST_CMD", REG_SMC, 0xd02110c8, &ixUNBPM_AXIMST_LAST_CMD[0], sizeof(ixUNBPM_AXIMST_LAST_CMD)/sizeof(ixUNBPM_AXIMST_LAST_CMD[0]), 0, 0 },
	{ "ixUNB_IF_INTRGEN_LAST_SENT", REG_SMC, 0xd02110cc, &ixUNB_IF_INTRGEN_LAST_SENT[0], sizeof(ixUNB_IF_INTRGEN_LAST_SENT)/sizeof(ixUNB_IF_INTRGEN_LAST_SENT[0]), 0, 0 },
	{ "ixUNBPM_DEBUG_BUS_CNTL", REG_SMC, 0xd02110d0, &ixUNBPM_DEBUG_BUS_CNTL[0], sizeof(ixUNBPM_DEBUG_BUS_CNTL)/sizeof(ixUNBPM_DEBUG_BUS_CNTL[0]), 0, 0 },
	{ "ixUNBPM_PWRMGT_REQ_DBG_STATUS", REG_SMC, 0xd02110d4, &ixUNBPM_PWRMGT_REQ_DBG_STATUS[0], sizeof(ixUNBPM_PWRMGT_REQ_DBG_STATUS)/sizeof(ixUNBPM_PWRMGT_REQ_DBG_STATUS[0]), 0, 0 },
	{ "ixUNBPM_VIDCHG_REQ_DBG_STATUS", REG_SMC, 0xd02110d8, &ixUNBPM_VIDCHG_REQ_DBG_STATUS[0], sizeof(ixUNBPM_VIDCHG_REQ_DBG_STATUS)/sizeof(ixUNBPM_VIDCHG_REQ_DBG_STATUS[0]), 0, 0 },
	{ "ixUNBPM_SCRATCH_0", REG_SMC, 0xd021e000, &ixUNBPM_SCRATCH_0[0], sizeof(ixUNBPM_SCRATCH_0)/sizeof(ixUNBPM_SCRATCH_0[0]), 0, 0 },
	{ "ixUNBPM_SCRATCH_1", REG_SMC, 0xd021e004, &ixUNBPM_SCRATCH_1[0], sizeof(ixUNBPM_SCRATCH_1)/sizeof(ixUNBPM_SCRATCH_1[0]), 0, 0 },
	{ "ixPOWERON_CPU_0", REG_SMC, 0xd0220000, &ixPOWERON_CPU_0[0], sizeof(ixPOWERON_CPU_0)/sizeof(ixPOWERON_CPU_0[0]), 0, 0 },
	{ "ixPOWERREADY_CPU_0", REG_SMC, 0xd0220004, &ixPOWERREADY_CPU_0[0], sizeof(ixPOWERREADY_CPU_0)/sizeof(ixPOWERREADY_CPU_0[0]), 0, 0 },
	{ "ixPGRUNFEEDBACK_CPU_0", REG_SMC, 0xd0220008, &ixPGRUNFEEDBACK_CPU_0[0], sizeof(ixPGRUNFEEDBACK_CPU_0)/sizeof(ixPGRUNFEEDBACK_CPU_0[0]), 0, 0 },
	{ "ixRCC3ON_CPU_0", REG_SMC, 0xd022000c, &ixRCC3ON_CPU_0[0], sizeof(ixRCC3ON_CPU_0)/sizeof(ixRCC3ON_CPU_0[0]), 0, 0 },
	{ "ixRCC3EXITDONE_CPU_0", REG_SMC, 0xd0220010, &ixRCC3EXITDONE_CPU_0[0], sizeof(ixRCC3EXITDONE_CPU_0)/sizeof(ixRCC3EXITDONE_CPU_0[0]), 0, 0 },
	{ "ixCORE_FUNC_LATE_SSB_XFER_0", REG_SMC, 0xd0220014, &ixCORE_FUNC_LATE_SSB_XFER_0[0], sizeof(ixCORE_FUNC_LATE_SSB_XFER_0)/sizeof(ixCORE_FUNC_LATE_SSB_XFER_0[0]), 0, 0 },
	{ "ixCORE_FUNC_LATE_SSB_XFER_CFG_0", REG_SMC, 0xd0220018, &ixCORE_FUNC_LATE_SSB_XFER_CFG_0[0], sizeof(ixCORE_FUNC_LATE_SSB_XFER_CFG_0)/sizeof(ixCORE_FUNC_LATE_SSB_XFER_CFG_0[0]), 0, 0 },
	{ "ixCORE_REDUN_SSB_XFER_0", REG_SMC, 0xd022001c, &ixCORE_REDUN_SSB_XFER_0[0], sizeof(ixCORE_REDUN_SSB_XFER_0)/sizeof(ixCORE_REDUN_SSB_XFER_0[0]), 0, 0 },
	{ "ixCORE_REDUN_SSB_XFER_CFG_0", REG_SMC, 0xd0220020, &ixCORE_REDUN_SSB_XFER_CFG_0[0], sizeof(ixCORE_REDUN_SSB_XFER_CFG_0)/sizeof(ixCORE_REDUN_SSB_XFER_CFG_0[0]), 0, 0 },
	{ "ixCORE_APM_SSB_XFER_0", REG_SMC, 0xd0220024, &ixCORE_APM_SSB_XFER_0[0], sizeof(ixCORE_APM_SSB_XFER_0)/sizeof(ixCORE_APM_SSB_XFER_0[0]), 0, 0 },
	{ "ixCORE_APM_SSB_XFER_CFG_0", REG_SMC, 0xd0220028, &ixCORE_APM_SSB_XFER_CFG_0[0], sizeof(ixCORE_APM_SSB_XFER_CFG_0)/sizeof(ixCORE_APM_SSB_XFER_CFG_0[0]), 0, 0 },
	{ "ixCOREPM_PWRCTRL_MISC_0", REG_SMC, 0xd022002c, &ixCOREPM_PWRCTRL_MISC_0[0], sizeof(ixCOREPM_PWRCTRL_MISC_0)/sizeof(ixCOREPM_PWRCTRL_MISC_0[0]), 0, 0 },
	{ "ixLDOIVRON_CPU_0", REG_SMC, 0xd0220030, &ixLDOIVRON_CPU_0[0], sizeof(ixLDOIVRON_CPU_0)/sizeof(ixLDOIVRON_CPU_0[0]), 0, 0 },
	{ "ixLDOIVREXITDONE_CPU_0", REG_SMC, 0xd0220034, &ixLDOIVREXITDONE_CPU_0[0], sizeof(ixLDOIVREXITDONE_CPU_0)/sizeof(ixLDOIVREXITDONE_CPU_0[0]), 0, 0 },
	{ "ixRCC3_TARGETPSMREF_CPU_0", REG_SMC, 0xd0220038, &ixRCC3_TARGETPSMREF_CPU_0[0], sizeof(ixRCC3_TARGETPSMREF_CPU_0)/sizeof(ixRCC3_TARGETPSMREF_CPU_0[0]), 0, 0 },
	{ "ixIVR_TARGETPSMREF_CPU_0", REG_SMC, 0xd022003c, &ixIVR_TARGETPSMREF_CPU_0[0], sizeof(ixIVR_TARGETPSMREF_CPU_0)/sizeof(ixIVR_TARGETPSMREF_CPU_0[0]), 0, 0 },
	{ "ixCK_JTCOOLRESET_LATCHED_CPU_0", REG_SMC, 0xd0220044, &ixCK_JTCOOLRESET_LATCHED_CPU_0[0], sizeof(ixCK_JTCOOLRESET_LATCHED_CPU_0)/sizeof(ixCK_JTCOOLRESET_LATCHED_CPU_0[0]), 0, 0 },
	{ "ixCK_DISABLECORE_CPU_0", REG_SMC, 0xd0220048, &ixCK_DISABLECORE_CPU_0[0], sizeof(ixCK_DISABLECORE_CPU_0)/sizeof(ixCK_DISABLECORE_CPU_0[0]), 0, 0 },
	{ "ixCOREPM_ID_0", REG_SMC, 0xd022004c, &ixCOREPM_ID_0[0], sizeof(ixCOREPM_ID_0)/sizeof(ixCOREPM_ID_0[0]), 0, 0 },
	{ "ixCOREPM_SCRATCH_0", REG_SMC, 0xd0220050, &ixCOREPM_SCRATCH_0[0], sizeof(ixCOREPM_SCRATCH_0)/sizeof(ixCOREPM_SCRATCH_0[0]), 0, 0 },
	{ "ixRCC3_WAKEMIN_CPU_0", REG_SMC, 0xd0220054, &ixRCC3_WAKEMIN_CPU_0[0], sizeof(ixRCC3_WAKEMIN_CPU_0)/sizeof(ixRCC3_WAKEMIN_CPU_0[0]), 0, 0 },
	{ "ixSPMI_CONFIG0_0", REG_SMC, 0xd0221000, &ixSPMI_CONFIG0_0[0], sizeof(ixSPMI_CONFIG0_0)/sizeof(ixSPMI_CONFIG0_0[0]), 0, 0 },
	{ "ixSPMI_CONFIG1_0", REG_SMC, 0xd0221004, &ixSPMI_CONFIG1_0[0], sizeof(ixSPMI_CONFIG1_0)/sizeof(ixSPMI_CONFIG1_0[0]), 0, 0 },
	{ "ixSPMI_FSM_READ_TRIGGER_0", REG_SMC, 0xd0221008, &ixSPMI_FSM_READ_TRIGGER_0[0], sizeof(ixSPMI_FSM_READ_TRIGGER_0)/sizeof(ixSPMI_FSM_READ_TRIGGER_0[0]), 0, 0 },
	{ "ixSPMI_FSM_WRITE_TRIGGER_0", REG_SMC, 0xd022100c, &ixSPMI_FSM_WRITE_TRIGGER_0[0], sizeof(ixSPMI_FSM_WRITE_TRIGGER_0)/sizeof(ixSPMI_FSM_WRITE_TRIGGER_0[0]), 0, 0 },
	{ "ixSPMI_FSM_RESET_TRIGGER_0", REG_SMC, 0xd0221010, &ixSPMI_FSM_RESET_TRIGGER_0[0], sizeof(ixSPMI_FSM_RESET_TRIGGER_0)/sizeof(ixSPMI_FSM_RESET_TRIGGER_0[0]), 0, 0 },
	{ "ixSPMI_FSM_BUSY_0", REG_SMC, 0xd0221014, &ixSPMI_FSM_BUSY_0[0], sizeof(ixSPMI_FSM_BUSY_0)/sizeof(ixSPMI_FSM_BUSY_0[0]), 0, 0 },
	{ "ixSPMI_PATH_0", REG_SMC, 0xd0221018, &ixSPMI_PATH_0[0], sizeof(ixSPMI_PATH_0)/sizeof(ixSPMI_PATH_0[0]), 0, 0 },
	{ "ixSPMI_C6_STATE_0", REG_SMC, 0xd022101c, &ixSPMI_C6_STATE_0[0], sizeof(ixSPMI_C6_STATE_0)/sizeof(ixSPMI_C6_STATE_0[0]), 0, 0 },
	{ "ixSPMI_JTAG_OVER_0", REG_SMC, 0xd0221020, &ixSPMI_JTAG_OVER_0[0], sizeof(ixSPMI_JTAG_OVER_0)/sizeof(ixSPMI_JTAG_OVER_0[0]), 0, 0 },
	{ "ixSPMI_SRAM_ADDRESS_0", REG_SMC, 0xd0221024, &ixSPMI_SRAM_ADDRESS_0[0], sizeof(ixSPMI_SRAM_ADDRESS_0)/sizeof(ixSPMI_SRAM_ADDRESS_0[0]), 0, 0 },
	{ "ixSPMI_SRAM_DATA_0", REG_SMC, 0xd0221028, &ixSPMI_SRAM_DATA_0[0], sizeof(ixSPMI_SRAM_DATA_0)/sizeof(ixSPMI_SRAM_DATA_0[0]), 0, 0 },
	{ "ixSPMI_RESET_0", REG_SMC, 0xd022102c, &ixSPMI_RESET_0[0], sizeof(ixSPMI_RESET_0)/sizeof(ixSPMI_RESET_0[0]), 0, 0 },
	{ "ixSPMI_FORCE_CLOCK_GATERS_0", REG_SMC, 0xd0221030, &ixSPMI_FORCE_CLOCK_GATERS_0[0], sizeof(ixSPMI_FORCE_CLOCK_GATERS_0)/sizeof(ixSPMI_FORCE_CLOCK_GATERS_0[0]), 0, 0 },
	{ "ixSPMI_SPARE_0", REG_SMC, 0xd0221034, &ixSPMI_SPARE_0[0], sizeof(ixSPMI_SPARE_0)/sizeof(ixSPMI_SPARE_0[0]), 0, 0 },
	{ "ixSPMI_SPARE_EX_0", REG_SMC, 0xd0221038, &ixSPMI_SPARE_EX_0[0], sizeof(ixSPMI_SPARE_EX_0)/sizeof(ixSPMI_SPARE_EX_0[0]), 0, 0 },
	{ "ixSPMI_SRAM_CLK_GATER_0", REG_SMC, 0xd022103c, &ixSPMI_SRAM_CLK_GATER_0[0], sizeof(ixSPMI_SRAM_CLK_GATER_0)/sizeof(ixSPMI_SRAM_CLK_GATER_0[0]), 0, 0 },
	{ "ixPOWERON_CPU_1", REG_SMC, 0xd0230000, &ixPOWERON_CPU_1[0], sizeof(ixPOWERON_CPU_1)/sizeof(ixPOWERON_CPU_1[0]), 0, 0 },
	{ "ixPOWERREADY_CPU_1", REG_SMC, 0xd0230004, &ixPOWERREADY_CPU_1[0], sizeof(ixPOWERREADY_CPU_1)/sizeof(ixPOWERREADY_CPU_1[0]), 0, 0 },
	{ "ixPGRUNFEEDBACK_CPU_1", REG_SMC, 0xd0230008, &ixPGRUNFEEDBACK_CPU_1[0], sizeof(ixPGRUNFEEDBACK_CPU_1)/sizeof(ixPGRUNFEEDBACK_CPU_1[0]), 0, 0 },
	{ "ixRCC3ON_CPU_1", REG_SMC, 0xd023000c, &ixRCC3ON_CPU_1[0], sizeof(ixRCC3ON_CPU_1)/sizeof(ixRCC3ON_CPU_1[0]), 0, 0 },
	{ "ixRCC3EXITDONE_CPU_1", REG_SMC, 0xd0230010, &ixRCC3EXITDONE_CPU_1[0], sizeof(ixRCC3EXITDONE_CPU_1)/sizeof(ixRCC3EXITDONE_CPU_1[0]), 0, 0 },
	{ "ixCORE_FUNC_LATE_SSB_XFER_1", REG_SMC, 0xd0230014, &ixCORE_FUNC_LATE_SSB_XFER_1[0], sizeof(ixCORE_FUNC_LATE_SSB_XFER_1)/sizeof(ixCORE_FUNC_LATE_SSB_XFER_1[0]), 0, 0 },
	{ "ixCORE_FUNC_LATE_SSB_XFER_CFG_1", REG_SMC, 0xd0230018, &ixCORE_FUNC_LATE_SSB_XFER_CFG_1[0], sizeof(ixCORE_FUNC_LATE_SSB_XFER_CFG_1)/sizeof(ixCORE_FUNC_LATE_SSB_XFER_CFG_1[0]), 0, 0 },
	{ "ixCORE_REDUN_SSB_XFER_1", REG_SMC, 0xd023001c, &ixCORE_REDUN_SSB_XFER_1[0], sizeof(ixCORE_REDUN_SSB_XFER_1)/sizeof(ixCORE_REDUN_SSB_XFER_1[0]), 0, 0 },
	{ "ixCORE_REDUN_SSB_XFER_CFG_1", REG_SMC, 0xd0230020, &ixCORE_REDUN_SSB_XFER_CFG_1[0], sizeof(ixCORE_REDUN_SSB_XFER_CFG_1)/sizeof(ixCORE_REDUN_SSB_XFER_CFG_1[0]), 0, 0 },
	{ "ixCORE_APM_SSB_XFER_1", REG_SMC, 0xd0230024, &ixCORE_APM_SSB_XFER_1[0], sizeof(ixCORE_APM_SSB_XFER_1)/sizeof(ixCORE_APM_SSB_XFER_1[0]), 0, 0 },
	{ "ixCORE_APM_SSB_XFER_CFG_1", REG_SMC, 0xd0230028, &ixCORE_APM_SSB_XFER_CFG_1[0], sizeof(ixCORE_APM_SSB_XFER_CFG_1)/sizeof(ixCORE_APM_SSB_XFER_CFG_1[0]), 0, 0 },
	{ "ixCOREPM_PWRCTRL_MISC_1", REG_SMC, 0xd023002c, &ixCOREPM_PWRCTRL_MISC_1[0], sizeof(ixCOREPM_PWRCTRL_MISC_1)/sizeof(ixCOREPM_PWRCTRL_MISC_1[0]), 0, 0 },
	{ "ixLDOIVRON_CPU_1", REG_SMC, 0xd0230030, &ixLDOIVRON_CPU_1[0], sizeof(ixLDOIVRON_CPU_1)/sizeof(ixLDOIVRON_CPU_1[0]), 0, 0 },
	{ "ixLDOIVREXITDONE_CPU_1", REG_SMC, 0xd0230034, &ixLDOIVREXITDONE_CPU_1[0], sizeof(ixLDOIVREXITDONE_CPU_1)/sizeof(ixLDOIVREXITDONE_CPU_1[0]), 0, 0 },
	{ "ixRCC3_TARGETPSMREF_CPU_1", REG_SMC, 0xd0230038, &ixRCC3_TARGETPSMREF_CPU_1[0], sizeof(ixRCC3_TARGETPSMREF_CPU_1)/sizeof(ixRCC3_TARGETPSMREF_CPU_1[0]), 0, 0 },
	{ "ixIVR_TARGETPSMREF_CPU_1", REG_SMC, 0xd023003c, &ixIVR_TARGETPSMREF_CPU_1[0], sizeof(ixIVR_TARGETPSMREF_CPU_1)/sizeof(ixIVR_TARGETPSMREF_CPU_1[0]), 0, 0 },
	{ "ixCK_JTCOOLRESET_LATCHED_CPU_1", REG_SMC, 0xd0230044, &ixCK_JTCOOLRESET_LATCHED_CPU_1[0], sizeof(ixCK_JTCOOLRESET_LATCHED_CPU_1)/sizeof(ixCK_JTCOOLRESET_LATCHED_CPU_1[0]), 0, 0 },
	{ "ixCK_DISABLECORE_CPU_1", REG_SMC, 0xd0230048, &ixCK_DISABLECORE_CPU_1[0], sizeof(ixCK_DISABLECORE_CPU_1)/sizeof(ixCK_DISABLECORE_CPU_1[0]), 0, 0 },
	{ "ixCOREPM_ID_1", REG_SMC, 0xd023004c, &ixCOREPM_ID_1[0], sizeof(ixCOREPM_ID_1)/sizeof(ixCOREPM_ID_1[0]), 0, 0 },
	{ "ixCOREPM_SCRATCH_1", REG_SMC, 0xd0230050, &ixCOREPM_SCRATCH_1[0], sizeof(ixCOREPM_SCRATCH_1)/sizeof(ixCOREPM_SCRATCH_1[0]), 0, 0 },
	{ "ixRCC3_WAKEMIN_CPU_1", REG_SMC, 0xd0230054, &ixRCC3_WAKEMIN_CPU_1[0], sizeof(ixRCC3_WAKEMIN_CPU_1)/sizeof(ixRCC3_WAKEMIN_CPU_1[0]), 0, 0 },
	{ "ixSPMI_CONFIG0_1", REG_SMC, 0xd0231000, &ixSPMI_CONFIG0_1[0], sizeof(ixSPMI_CONFIG0_1)/sizeof(ixSPMI_CONFIG0_1[0]), 0, 0 },
	{ "ixSPMI_CONFIG1_1", REG_SMC, 0xd0231004, &ixSPMI_CONFIG1_1[0], sizeof(ixSPMI_CONFIG1_1)/sizeof(ixSPMI_CONFIG1_1[0]), 0, 0 },
	{ "ixSPMI_FSM_READ_TRIGGER_1", REG_SMC, 0xd0231008, &ixSPMI_FSM_READ_TRIGGER_1[0], sizeof(ixSPMI_FSM_READ_TRIGGER_1)/sizeof(ixSPMI_FSM_READ_TRIGGER_1[0]), 0, 0 },
	{ "ixSPMI_FSM_WRITE_TRIGGER_1", REG_SMC, 0xd023100c, &ixSPMI_FSM_WRITE_TRIGGER_1[0], sizeof(ixSPMI_FSM_WRITE_TRIGGER_1)/sizeof(ixSPMI_FSM_WRITE_TRIGGER_1[0]), 0, 0 },
	{ "ixSPMI_FSM_RESET_TRIGGER_1", REG_SMC, 0xd0231010, &ixSPMI_FSM_RESET_TRIGGER_1[0], sizeof(ixSPMI_FSM_RESET_TRIGGER_1)/sizeof(ixSPMI_FSM_RESET_TRIGGER_1[0]), 0, 0 },
	{ "ixSPMI_FSM_BUSY_1", REG_SMC, 0xd0231014, &ixSPMI_FSM_BUSY_1[0], sizeof(ixSPMI_FSM_BUSY_1)/sizeof(ixSPMI_FSM_BUSY_1[0]), 0, 0 },
	{ "ixSPMI_PATH_1", REG_SMC, 0xd0231018, &ixSPMI_PATH_1[0], sizeof(ixSPMI_PATH_1)/sizeof(ixSPMI_PATH_1[0]), 0, 0 },
	{ "ixSPMI_C6_STATE_1", REG_SMC, 0xd023101c, &ixSPMI_C6_STATE_1[0], sizeof(ixSPMI_C6_STATE_1)/sizeof(ixSPMI_C6_STATE_1[0]), 0, 0 },
	{ "ixSPMI_JTAG_OVER_1", REG_SMC, 0xd0231020, &ixSPMI_JTAG_OVER_1[0], sizeof(ixSPMI_JTAG_OVER_1)/sizeof(ixSPMI_JTAG_OVER_1[0]), 0, 0 },
	{ "ixSPMI_SRAM_ADDRESS_1", REG_SMC, 0xd0231024, &ixSPMI_SRAM_ADDRESS_1[0], sizeof(ixSPMI_SRAM_ADDRESS_1)/sizeof(ixSPMI_SRAM_ADDRESS_1[0]), 0, 0 },
	{ "ixSPMI_SRAM_DATA_1", REG_SMC, 0xd0231028, &ixSPMI_SRAM_DATA_1[0], sizeof(ixSPMI_SRAM_DATA_1)/sizeof(ixSPMI_SRAM_DATA_1[0]), 0, 0 },
	{ "ixSPMI_RESET_1", REG_SMC, 0xd023102c, &ixSPMI_RESET_1[0], sizeof(ixSPMI_RESET_1)/sizeof(ixSPMI_RESET_1[0]), 0, 0 },
	{ "ixSPMI_FORCE_CLOCK_GATERS_1", REG_SMC, 0xd0231030, &ixSPMI_FORCE_CLOCK_GATERS_1[0], sizeof(ixSPMI_FORCE_CLOCK_GATERS_1)/sizeof(ixSPMI_FORCE_CLOCK_GATERS_1[0]), 0, 0 },
	{ "ixSPMI_SPARE_1", REG_SMC, 0xd0231034, &ixSPMI_SPARE_1[0], sizeof(ixSPMI_SPARE_1)/sizeof(ixSPMI_SPARE_1[0]), 0, 0 },
	{ "ixSPMI_SPARE_EX_1", REG_SMC, 0xd0231038, &ixSPMI_SPARE_EX_1[0], sizeof(ixSPMI_SPARE_EX_1)/sizeof(ixSPMI_SPARE_EX_1[0]), 0, 0 },
	{ "ixSPMI_SRAM_CLK_GATER_1", REG_SMC, 0xd023103c, &ixSPMI_SRAM_CLK_GATER_1[0], sizeof(ixSPMI_SRAM_CLK_GATER_1)/sizeof(ixSPMI_SRAM_CLK_GATER_1[0]), 0, 0 },
	{ "ixTHM_TCON_HTC", REG_SMC, 0xd8200c64, &ixTHM_TCON_HTC[0], sizeof(ixTHM_TCON_HTC)/sizeof(ixTHM_TCON_HTC[0]), 0, 0 },
	{ "ixTHM_TCON_CUR_TMP", REG_SMC, 0xd8200ca4, &ixTHM_TCON_CUR_TMP[0], sizeof(ixTHM_TCON_CUR_TMP)/sizeof(ixTHM_TCON_CUR_TMP[0]), 0, 0 },
	{ "ixTHM_TCON_THERM_TRIP", REG_SMC, 0xd8200ce4, &ixTHM_TCON_THERM_TRIP[0], sizeof(ixTHM_TCON_THERM_TRIP)/sizeof(ixTHM_TCON_THERM_TRIP[0]), 0, 0 },
	{ "ixTHM_GPIO_PROCHOT_CTRL", REG_SMC, 0xd8200d00, &ixTHM_GPIO_PROCHOT_CTRL[0], sizeof(ixTHM_GPIO_PROCHOT_CTRL)/sizeof(ixTHM_GPIO_PROCHOT_CTRL[0]), 0, 0 },
	{ "ixTHM_GPIO_THERMTRIP_CTRL", REG_SMC, 0xd8200d04, &ixTHM_GPIO_THERMTRIP_CTRL[0], sizeof(ixTHM_GPIO_THERMTRIP_CTRL)/sizeof(ixTHM_GPIO_THERMTRIP_CTRL[0]), 0, 0 },
	{ "ixTHM_THERMAL_INT_ENA", REG_SMC, 0xd8200d10, &ixTHM_THERMAL_INT_ENA[0], sizeof(ixTHM_THERMAL_INT_ENA)/sizeof(ixTHM_THERMAL_INT_ENA[0]), 0, 0 },
	{ "ixTHM_THERMAL_INT_CTRL", REG_SMC, 0xd8200d14, &ixTHM_THERMAL_INT_CTRL[0], sizeof(ixTHM_THERMAL_INT_CTRL)/sizeof(ixTHM_THERMAL_INT_CTRL[0]), 0, 0 },
	{ "ixTHM_THERMAL_INT_STATUS", REG_SMC, 0xd8200d18, &ixTHM_THERMAL_INT_STATUS[0], sizeof(ixTHM_THERMAL_INT_STATUS)/sizeof(ixTHM_THERMAL_INT_STATUS[0]), 0, 0 },
	{ "ixTHM_TCON_CSR_CONFIG", REG_SMC, 0xd82014a4, &ixTHM_TCON_CSR_CONFIG[0], sizeof(ixTHM_TCON_CSR_CONFIG)/sizeof(ixTHM_TCON_CSR_CONFIG[0]), 0, 0 },
	{ "ixTHM_TCON_CSR_DATA", REG_SMC, 0xd82014a8, &ixTHM_TCON_CSR_DATA[0], sizeof(ixTHM_TCON_CSR_DATA)/sizeof(ixTHM_TCON_CSR_DATA[0]), 0, 0 },
	{ "ixTMON0_RDIL0_DATA", REG_SMC, 0xd8202000, &ixTMON0_RDIL0_DATA[0], sizeof(ixTMON0_RDIL0_DATA)/sizeof(ixTMON0_RDIL0_DATA[0]), 0, 0 },
	{ "ixTMON0_RDIL1_DATA", REG_SMC, 0xd8202004, &ixTMON0_RDIL1_DATA[0], sizeof(ixTMON0_RDIL1_DATA)/sizeof(ixTMON0_RDIL1_DATA[0]), 0, 0 },
	{ "ixTMON0_RDIL2_DATA", REG_SMC, 0xd8202008, &ixTMON0_RDIL2_DATA[0], sizeof(ixTMON0_RDIL2_DATA)/sizeof(ixTMON0_RDIL2_DATA[0]), 0, 0 },
	{ "ixTMON0_RDIL3_DATA", REG_SMC, 0xd820200c, &ixTMON0_RDIL3_DATA[0], sizeof(ixTMON0_RDIL3_DATA)/sizeof(ixTMON0_RDIL3_DATA[0]), 0, 0 },
	{ "ixTMON0_RDIL4_DATA", REG_SMC, 0xd8202010, &ixTMON0_RDIL4_DATA[0], sizeof(ixTMON0_RDIL4_DATA)/sizeof(ixTMON0_RDIL4_DATA[0]), 0, 0 },
	{ "ixTMON0_RDIL5_DATA", REG_SMC, 0xd8202014, &ixTMON0_RDIL5_DATA[0], sizeof(ixTMON0_RDIL5_DATA)/sizeof(ixTMON0_RDIL5_DATA[0]), 0, 0 },
	{ "ixTMON0_RDIL6_DATA", REG_SMC, 0xd8202018, &ixTMON0_RDIL6_DATA[0], sizeof(ixTMON0_RDIL6_DATA)/sizeof(ixTMON0_RDIL6_DATA[0]), 0, 0 },
	{ "ixTMON0_RDIL7_DATA", REG_SMC, 0xd820201c, &ixTMON0_RDIL7_DATA[0], sizeof(ixTMON0_RDIL7_DATA)/sizeof(ixTMON0_RDIL7_DATA[0]), 0, 0 },
	{ "ixTMON0_RDIL8_DATA", REG_SMC, 0xd8202020, &ixTMON0_RDIL8_DATA[0], sizeof(ixTMON0_RDIL8_DATA)/sizeof(ixTMON0_RDIL8_DATA[0]), 0, 0 },
	{ "ixTMON0_RDIL9_DATA", REG_SMC, 0xd8202024, &ixTMON0_RDIL9_DATA[0], sizeof(ixTMON0_RDIL9_DATA)/sizeof(ixTMON0_RDIL9_DATA[0]), 0, 0 },
	{ "ixTMON0_RDIL10_DATA", REG_SMC, 0xd8202028, &ixTMON0_RDIL10_DATA[0], sizeof(ixTMON0_RDIL10_DATA)/sizeof(ixTMON0_RDIL10_DATA[0]), 0, 0 },
	{ "ixTMON0_RDIL11_DATA", REG_SMC, 0xd820202c, &ixTMON0_RDIL11_DATA[0], sizeof(ixTMON0_RDIL11_DATA)/sizeof(ixTMON0_RDIL11_DATA[0]), 0, 0 },
	{ "ixTMON0_RDIL12_DATA", REG_SMC, 0xd8202030, &ixTMON0_RDIL12_DATA[0], sizeof(ixTMON0_RDIL12_DATA)/sizeof(ixTMON0_RDIL12_DATA[0]), 0, 0 },
	{ "ixTMON0_RDIL13_DATA", REG_SMC, 0xd8202034, &ixTMON0_RDIL13_DATA[0], sizeof(ixTMON0_RDIL13_DATA)/sizeof(ixTMON0_RDIL13_DATA[0]), 0, 0 },
	{ "ixTMON0_RDIL14_DATA", REG_SMC, 0xd8202038, &ixTMON0_RDIL14_DATA[0], sizeof(ixTMON0_RDIL14_DATA)/sizeof(ixTMON0_RDIL14_DATA[0]), 0, 0 },
	{ "ixTMON0_RDIL15_DATA", REG_SMC, 0xd820203c, &ixTMON0_RDIL15_DATA[0], sizeof(ixTMON0_RDIL15_DATA)/sizeof(ixTMON0_RDIL15_DATA[0]), 0, 0 },
	{ "ixTMON0_RDIR0_DATA", REG_SMC, 0xd8202040, &ixTMON0_RDIR0_DATA[0], sizeof(ixTMON0_RDIR0_DATA)/sizeof(ixTMON0_RDIR0_DATA[0]), 0, 0 },
	{ "ixTMON0_RDIR1_DATA", REG_SMC, 0xd8202044, &ixTMON0_RDIR1_DATA[0], sizeof(ixTMON0_RDIR1_DATA)/sizeof(ixTMON0_RDIR1_DATA[0]), 0, 0 },
	{ "ixTMON0_RDIR2_DATA", REG_SMC, 0xd8202048, &ixTMON0_RDIR2_DATA[0], sizeof(ixTMON0_RDIR2_DATA)/sizeof(ixTMON0_RDIR2_DATA[0]), 0, 0 },
	{ "ixTMON0_RDIR3_DATA", REG_SMC, 0xd820204c, &ixTMON0_RDIR3_DATA[0], sizeof(ixTMON0_RDIR3_DATA)/sizeof(ixTMON0_RDIR3_DATA[0]), 0, 0 },
	{ "ixTMON0_RDIR4_DATA", REG_SMC, 0xd8202050, &ixTMON0_RDIR4_DATA[0], sizeof(ixTMON0_RDIR4_DATA)/sizeof(ixTMON0_RDIR4_DATA[0]), 0, 0 },
	{ "ixTMON0_RDIR5_DATA", REG_SMC, 0xd8202054, &ixTMON0_RDIR5_DATA[0], sizeof(ixTMON0_RDIR5_DATA)/sizeof(ixTMON0_RDIR5_DATA[0]), 0, 0 },
	{ "ixTMON0_RDIR6_DATA", REG_SMC, 0xd8202058, &ixTMON0_RDIR6_DATA[0], sizeof(ixTMON0_RDIR6_DATA)/sizeof(ixTMON0_RDIR6_DATA[0]), 0, 0 },
	{ "ixTMON0_RDIR7_DATA", REG_SMC, 0xd820205c, &ixTMON0_RDIR7_DATA[0], sizeof(ixTMON0_RDIR7_DATA)/sizeof(ixTMON0_RDIR7_DATA[0]), 0, 0 },
	{ "ixTMON0_RDIR8_DATA", REG_SMC, 0xd8202060, &ixTMON0_RDIR8_DATA[0], sizeof(ixTMON0_RDIR8_DATA)/sizeof(ixTMON0_RDIR8_DATA[0]), 0, 0 },
	{ "ixTMON0_RDIR9_DATA", REG_SMC, 0xd8202064, &ixTMON0_RDIR9_DATA[0], sizeof(ixTMON0_RDIR9_DATA)/sizeof(ixTMON0_RDIR9_DATA[0]), 0, 0 },
	{ "ixTMON0_RDIR10_DATA", REG_SMC, 0xd8202068, &ixTMON0_RDIR10_DATA[0], sizeof(ixTMON0_RDIR10_DATA)/sizeof(ixTMON0_RDIR10_DATA[0]), 0, 0 },
	{ "ixTMON0_RDIR11_DATA", REG_SMC, 0xd820206c, &ixTMON0_RDIR11_DATA[0], sizeof(ixTMON0_RDIR11_DATA)/sizeof(ixTMON0_RDIR11_DATA[0]), 0, 0 },
	{ "ixTMON0_RDIR12_DATA", REG_SMC, 0xd8202070, &ixTMON0_RDIR12_DATA[0], sizeof(ixTMON0_RDIR12_DATA)/sizeof(ixTMON0_RDIR12_DATA[0]), 0, 0 },
	{ "ixTMON0_RDIR13_DATA", REG_SMC, 0xd8202074, &ixTMON0_RDIR13_DATA[0], sizeof(ixTMON0_RDIR13_DATA)/sizeof(ixTMON0_RDIR13_DATA[0]), 0, 0 },
	{ "ixTMON0_RDIR14_DATA", REG_SMC, 0xd8202078, &ixTMON0_RDIR14_DATA[0], sizeof(ixTMON0_RDIR14_DATA)/sizeof(ixTMON0_RDIR14_DATA[0]), 0, 0 },
	{ "ixTMON0_RDIR15_DATA", REG_SMC, 0xd820207c, &ixTMON0_RDIR15_DATA[0], sizeof(ixTMON0_RDIR15_DATA)/sizeof(ixTMON0_RDIR15_DATA[0]), 0, 0 },
	{ "ixTMON0_INT_DATA", REG_SMC, 0xd8202080, &ixTMON0_INT_DATA[0], sizeof(ixTMON0_INT_DATA)/sizeof(ixTMON0_INT_DATA[0]), 0, 0 },
	{ "ixTMON0_RDIL_PRESENT0", REG_SMC, 0xd8202084, &ixTMON0_RDIL_PRESENT0[0], sizeof(ixTMON0_RDIL_PRESENT0)/sizeof(ixTMON0_RDIL_PRESENT0[0]), 0, 0 },
	{ "ixTMON0_RDIL_PRESENT1", REG_SMC, 0xd8202088, &ixTMON0_RDIL_PRESENT1[0], sizeof(ixTMON0_RDIL_PRESENT1)/sizeof(ixTMON0_RDIL_PRESENT1[0]), 0, 0 },
	{ "ixTMON0_RDIR_PRESENT0", REG_SMC, 0xd820208c, &ixTMON0_RDIR_PRESENT0[0], sizeof(ixTMON0_RDIR_PRESENT0)/sizeof(ixTMON0_RDIR_PRESENT0[0]), 0, 0 },
	{ "ixTMON0_RDIR_PRESENT1", REG_SMC, 0xd8202090, &ixTMON0_RDIR_PRESENT1[0], sizeof(ixTMON0_RDIR_PRESENT1)/sizeof(ixTMON0_RDIR_PRESENT1[0]), 0, 0 },
	{ "ixTMON0_CONFIG", REG_SMC, 0xd8202098, &ixTMON0_CONFIG[0], sizeof(ixTMON0_CONFIG)/sizeof(ixTMON0_CONFIG[0]), 0, 0 },
	{ "ixTMON0_TEMP_CALC_COEFF0", REG_SMC, 0xd82020a0, &ixTMON0_TEMP_CALC_COEFF0[0], sizeof(ixTMON0_TEMP_CALC_COEFF0)/sizeof(ixTMON0_TEMP_CALC_COEFF0[0]), 0, 0 },
	{ "ixTMON0_TEMP_CALC_COEFF1", REG_SMC, 0xd82020a4, &ixTMON0_TEMP_CALC_COEFF1[0], sizeof(ixTMON0_TEMP_CALC_COEFF1)/sizeof(ixTMON0_TEMP_CALC_COEFF1[0]), 0, 0 },
	{ "ixTMON0_TEMP_CALC_COEFF2", REG_SMC, 0xd82020a8, &ixTMON0_TEMP_CALC_COEFF2[0], sizeof(ixTMON0_TEMP_CALC_COEFF2)/sizeof(ixTMON0_TEMP_CALC_COEFF2[0]), 0, 0 },
	{ "ixTMON0_TEMP_CALC_COEFF3", REG_SMC, 0xd82020ac, &ixTMON0_TEMP_CALC_COEFF3[0], sizeof(ixTMON0_TEMP_CALC_COEFF3)/sizeof(ixTMON0_TEMP_CALC_COEFF3[0]), 0, 0 },
	{ "ixTMON0_TEMP_CALC_COEFF4", REG_SMC, 0xd82020b0, &ixTMON0_TEMP_CALC_COEFF4[0], sizeof(ixTMON0_TEMP_CALC_COEFF4)/sizeof(ixTMON0_TEMP_CALC_COEFF4[0]), 0, 0 },
	{ "ixTMON0_DEBUG0", REG_SMC, 0xd82020b4, &ixTMON0_DEBUG0[0], sizeof(ixTMON0_DEBUG0)/sizeof(ixTMON0_DEBUG0[0]), 0, 0 },
	{ "ixTMON0_DEBUG1", REG_SMC, 0xd82020b8, &ixTMON0_DEBUG1[0], sizeof(ixTMON0_DEBUG1)/sizeof(ixTMON0_DEBUG1[0]), 0, 0 },
	{ "ixTMON1_RDIL0_DATA", REG_SMC, 0xd8202100, &ixTMON1_RDIL0_DATA[0], sizeof(ixTMON1_RDIL0_DATA)/sizeof(ixTMON1_RDIL0_DATA[0]), 0, 0 },
	{ "ixTMON1_RDIL1_DATA", REG_SMC, 0xd8202104, &ixTMON1_RDIL1_DATA[0], sizeof(ixTMON1_RDIL1_DATA)/sizeof(ixTMON1_RDIL1_DATA[0]), 0, 0 },
	{ "ixTMON1_RDIL2_DATA", REG_SMC, 0xd8202108, &ixTMON1_RDIL2_DATA[0], sizeof(ixTMON1_RDIL2_DATA)/sizeof(ixTMON1_RDIL2_DATA[0]), 0, 0 },
	{ "ixTMON1_RDIL3_DATA", REG_SMC, 0xd820210c, &ixTMON1_RDIL3_DATA[0], sizeof(ixTMON1_RDIL3_DATA)/sizeof(ixTMON1_RDIL3_DATA[0]), 0, 0 },
	{ "ixTMON1_RDIL4_DATA", REG_SMC, 0xd8202110, &ixTMON1_RDIL4_DATA[0], sizeof(ixTMON1_RDIL4_DATA)/sizeof(ixTMON1_RDIL4_DATA[0]), 0, 0 },
	{ "ixTMON1_RDIL5_DATA", REG_SMC, 0xd8202114, &ixTMON1_RDIL5_DATA[0], sizeof(ixTMON1_RDIL5_DATA)/sizeof(ixTMON1_RDIL5_DATA[0]), 0, 0 },
	{ "ixTMON1_RDIL6_DATA", REG_SMC, 0xd8202118, &ixTMON1_RDIL6_DATA[0], sizeof(ixTMON1_RDIL6_DATA)/sizeof(ixTMON1_RDIL6_DATA[0]), 0, 0 },
	{ "ixTMON1_RDIL7_DATA", REG_SMC, 0xd820211c, &ixTMON1_RDIL7_DATA[0], sizeof(ixTMON1_RDIL7_DATA)/sizeof(ixTMON1_RDIL7_DATA[0]), 0, 0 },
	{ "ixTMON1_RDIL8_DATA", REG_SMC, 0xd8202120, &ixTMON1_RDIL8_DATA[0], sizeof(ixTMON1_RDIL8_DATA)/sizeof(ixTMON1_RDIL8_DATA[0]), 0, 0 },
	{ "ixTMON1_RDIL9_DATA", REG_SMC, 0xd8202124, &ixTMON1_RDIL9_DATA[0], sizeof(ixTMON1_RDIL9_DATA)/sizeof(ixTMON1_RDIL9_DATA[0]), 0, 0 },
	{ "ixTMON1_RDIL10_DATA", REG_SMC, 0xd8202128, &ixTMON1_RDIL10_DATA[0], sizeof(ixTMON1_RDIL10_DATA)/sizeof(ixTMON1_RDIL10_DATA[0]), 0, 0 },
	{ "ixTMON1_RDIL11_DATA", REG_SMC, 0xd820212c, &ixTMON1_RDIL11_DATA[0], sizeof(ixTMON1_RDIL11_DATA)/sizeof(ixTMON1_RDIL11_DATA[0]), 0, 0 },
	{ "ixTMON1_RDIL12_DATA", REG_SMC, 0xd8202130, &ixTMON1_RDIL12_DATA[0], sizeof(ixTMON1_RDIL12_DATA)/sizeof(ixTMON1_RDIL12_DATA[0]), 0, 0 },
	{ "ixTMON1_RDIL13_DATA", REG_SMC, 0xd8202134, &ixTMON1_RDIL13_DATA[0], sizeof(ixTMON1_RDIL13_DATA)/sizeof(ixTMON1_RDIL13_DATA[0]), 0, 0 },
	{ "ixTMON1_RDIL14_DATA", REG_SMC, 0xd8202138, &ixTMON1_RDIL14_DATA[0], sizeof(ixTMON1_RDIL14_DATA)/sizeof(ixTMON1_RDIL14_DATA[0]), 0, 0 },
	{ "ixTMON1_RDIL15_DATA", REG_SMC, 0xd820213c, &ixTMON1_RDIL15_DATA[0], sizeof(ixTMON1_RDIL15_DATA)/sizeof(ixTMON1_RDIL15_DATA[0]), 0, 0 },
	{ "ixTMON1_RDIR0_DATA", REG_SMC, 0xd8202140, &ixTMON1_RDIR0_DATA[0], sizeof(ixTMON1_RDIR0_DATA)/sizeof(ixTMON1_RDIR0_DATA[0]), 0, 0 },
	{ "ixTMON1_RDIR1_DATA", REG_SMC, 0xd8202144, &ixTMON1_RDIR1_DATA[0], sizeof(ixTMON1_RDIR1_DATA)/sizeof(ixTMON1_RDIR1_DATA[0]), 0, 0 },
	{ "ixTMON1_RDIR2_DATA", REG_SMC, 0xd8202148, &ixTMON1_RDIR2_DATA[0], sizeof(ixTMON1_RDIR2_DATA)/sizeof(ixTMON1_RDIR2_DATA[0]), 0, 0 },
	{ "ixTMON1_RDIR3_DATA", REG_SMC, 0xd820214c, &ixTMON1_RDIR3_DATA[0], sizeof(ixTMON1_RDIR3_DATA)/sizeof(ixTMON1_RDIR3_DATA[0]), 0, 0 },
	{ "ixTMON1_RDIR4_DATA", REG_SMC, 0xd8202150, &ixTMON1_RDIR4_DATA[0], sizeof(ixTMON1_RDIR4_DATA)/sizeof(ixTMON1_RDIR4_DATA[0]), 0, 0 },
	{ "ixTMON1_RDIR5_DATA", REG_SMC, 0xd8202154, &ixTMON1_RDIR5_DATA[0], sizeof(ixTMON1_RDIR5_DATA)/sizeof(ixTMON1_RDIR5_DATA[0]), 0, 0 },
	{ "ixTMON1_RDIR6_DATA", REG_SMC, 0xd8202158, &ixTMON1_RDIR6_DATA[0], sizeof(ixTMON1_RDIR6_DATA)/sizeof(ixTMON1_RDIR6_DATA[0]), 0, 0 },
	{ "ixTMON1_RDIR7_DATA", REG_SMC, 0xd820215c, &ixTMON1_RDIR7_DATA[0], sizeof(ixTMON1_RDIR7_DATA)/sizeof(ixTMON1_RDIR7_DATA[0]), 0, 0 },
	{ "ixTMON1_RDIR8_DATA", REG_SMC, 0xd8202160, &ixTMON1_RDIR8_DATA[0], sizeof(ixTMON1_RDIR8_DATA)/sizeof(ixTMON1_RDIR8_DATA[0]), 0, 0 },
	{ "ixTMON1_RDIR9_DATA", REG_SMC, 0xd8202164, &ixTMON1_RDIR9_DATA[0], sizeof(ixTMON1_RDIR9_DATA)/sizeof(ixTMON1_RDIR9_DATA[0]), 0, 0 },
	{ "ixTMON1_RDIR10_DATA", REG_SMC, 0xd8202168, &ixTMON1_RDIR10_DATA[0], sizeof(ixTMON1_RDIR10_DATA)/sizeof(ixTMON1_RDIR10_DATA[0]), 0, 0 },
	{ "ixTMON1_RDIR11_DATA", REG_SMC, 0xd820216c, &ixTMON1_RDIR11_DATA[0], sizeof(ixTMON1_RDIR11_DATA)/sizeof(ixTMON1_RDIR11_DATA[0]), 0, 0 },
	{ "ixTMON1_RDIR12_DATA", REG_SMC, 0xd8202170, &ixTMON1_RDIR12_DATA[0], sizeof(ixTMON1_RDIR12_DATA)/sizeof(ixTMON1_RDIR12_DATA[0]), 0, 0 },
	{ "ixTMON1_RDIR13_DATA", REG_SMC, 0xd8202174, &ixTMON1_RDIR13_DATA[0], sizeof(ixTMON1_RDIR13_DATA)/sizeof(ixTMON1_RDIR13_DATA[0]), 0, 0 },
	{ "ixTMON1_RDIR14_DATA", REG_SMC, 0xd8202178, &ixTMON1_RDIR14_DATA[0], sizeof(ixTMON1_RDIR14_DATA)/sizeof(ixTMON1_RDIR14_DATA[0]), 0, 0 },
	{ "ixTMON1_RDIR15_DATA", REG_SMC, 0xd820217c, &ixTMON1_RDIR15_DATA[0], sizeof(ixTMON1_RDIR15_DATA)/sizeof(ixTMON1_RDIR15_DATA[0]), 0, 0 },
	{ "ixTMON1_INT_DATA", REG_SMC, 0xd8202180, &ixTMON1_INT_DATA[0], sizeof(ixTMON1_INT_DATA)/sizeof(ixTMON1_INT_DATA[0]), 0, 0 },
	{ "ixTMON1_RDIL_PRESENT0", REG_SMC, 0xd8202184, &ixTMON1_RDIL_PRESENT0[0], sizeof(ixTMON1_RDIL_PRESENT0)/sizeof(ixTMON1_RDIL_PRESENT0[0]), 0, 0 },
	{ "ixTMON1_RDIL_PRESENT1", REG_SMC, 0xd8202188, &ixTMON1_RDIL_PRESENT1[0], sizeof(ixTMON1_RDIL_PRESENT1)/sizeof(ixTMON1_RDIL_PRESENT1[0]), 0, 0 },
	{ "ixTMON1_RDIR_PRESENT0", REG_SMC, 0xd820218c, &ixTMON1_RDIR_PRESENT0[0], sizeof(ixTMON1_RDIR_PRESENT0)/sizeof(ixTMON1_RDIR_PRESENT0[0]), 0, 0 },
	{ "ixTMON1_RDIR_PRESENT1", REG_SMC, 0xd8202190, &ixTMON1_RDIR_PRESENT1[0], sizeof(ixTMON1_RDIR_PRESENT1)/sizeof(ixTMON1_RDIR_PRESENT1[0]), 0, 0 },
	{ "ixTMON1_CONFIG", REG_SMC, 0xd8202198, &ixTMON1_CONFIG[0], sizeof(ixTMON1_CONFIG)/sizeof(ixTMON1_CONFIG[0]), 0, 0 },
	{ "ixTMON1_TEMP_CALC_COEFF0", REG_SMC, 0xd82021a0, &ixTMON1_TEMP_CALC_COEFF0[0], sizeof(ixTMON1_TEMP_CALC_COEFF0)/sizeof(ixTMON1_TEMP_CALC_COEFF0[0]), 0, 0 },
	{ "ixTMON1_TEMP_CALC_COEFF1", REG_SMC, 0xd82021a4, &ixTMON1_TEMP_CALC_COEFF1[0], sizeof(ixTMON1_TEMP_CALC_COEFF1)/sizeof(ixTMON1_TEMP_CALC_COEFF1[0]), 0, 0 },
	{ "ixTMON1_TEMP_CALC_COEFF2", REG_SMC, 0xd82021a8, &ixTMON1_TEMP_CALC_COEFF2[0], sizeof(ixTMON1_TEMP_CALC_COEFF2)/sizeof(ixTMON1_TEMP_CALC_COEFF2[0]), 0, 0 },
	{ "ixTMON1_TEMP_CALC_COEFF3", REG_SMC, 0xd82021ac, &ixTMON1_TEMP_CALC_COEFF3[0], sizeof(ixTMON1_TEMP_CALC_COEFF3)/sizeof(ixTMON1_TEMP_CALC_COEFF3[0]), 0, 0 },
	{ "ixTMON1_TEMP_CALC_COEFF4", REG_SMC, 0xd82021b0, &ixTMON1_TEMP_CALC_COEFF4[0], sizeof(ixTMON1_TEMP_CALC_COEFF4)/sizeof(ixTMON1_TEMP_CALC_COEFF4[0]), 0, 0 },
	{ "ixTMON1_DEBUG0", REG_SMC, 0xd82021b4, &ixTMON1_DEBUG0[0], sizeof(ixTMON1_DEBUG0)/sizeof(ixTMON1_DEBUG0[0]), 0, 0 },
	{ "ixTMON1_DEBUG1", REG_SMC, 0xd82021b8, &ixTMON1_DEBUG1[0], sizeof(ixTMON1_DEBUG1)/sizeof(ixTMON1_DEBUG1[0]), 0, 0 },
	{ "ixTHM_TMON0_REMOTE_START", REG_SMC, 0xd8202800, &ixTHM_TMON0_REMOTE_START[0], sizeof(ixTHM_TMON0_REMOTE_START)/sizeof(ixTHM_TMON0_REMOTE_START[0]), 0, 0 },
	{ "ixTHM_TMON0_REMOTE_END", REG_SMC, 0xd82028fc, &ixTHM_TMON0_REMOTE_END[0], sizeof(ixTHM_TMON0_REMOTE_END)/sizeof(ixTHM_TMON0_REMOTE_END[0]), 0, 0 },
	{ "ixTHM_TMON1_REMOTE_START", REG_SMC, 0xd8202900, &ixTHM_TMON1_REMOTE_START[0], sizeof(ixTHM_TMON1_REMOTE_START)/sizeof(ixTHM_TMON1_REMOTE_START[0]), 0, 0 },
	{ "ixTHM_TMON1_REMOTE_END", REG_SMC, 0xd82029fc, &ixTHM_TMON1_REMOTE_END[0], sizeof(ixTHM_TMON1_REMOTE_END)/sizeof(ixTHM_TMON1_REMOTE_END[0]), 0, 0 },
	{ "ixTHM_TCON_LOCAL0", REG_SMC, 0xd8202e00, &ixTHM_TCON_LOCAL0[0], sizeof(ixTHM_TCON_LOCAL0)/sizeof(ixTHM_TCON_LOCAL0[0]), 0, 0 },
	{ "ixTHM_TCON_LOCAL1", REG_SMC, 0xd8202e04, &ixTHM_TCON_LOCAL1[0], sizeof(ixTHM_TCON_LOCAL1)/sizeof(ixTHM_TCON_LOCAL1[0]), 0, 0 },
	{ "ixTHM_TCON_LOCAL2", REG_SMC, 0xd8202e08, &ixTHM_TCON_LOCAL2[0], sizeof(ixTHM_TCON_LOCAL2)/sizeof(ixTHM_TCON_LOCAL2[0]), 0, 0 },
	{ "ixTHM_TCON_LOCAL3", REG_SMC, 0xd8202e0c, &ixTHM_TCON_LOCAL3[0], sizeof(ixTHM_TCON_LOCAL3)/sizeof(ixTHM_TCON_LOCAL3[0]), 0, 0 },
	{ "ixTHM_TCON_LOCAL4", REG_SMC, 0xd8202e10, &ixTHM_TCON_LOCAL4[0], sizeof(ixTHM_TCON_LOCAL4)/sizeof(ixTHM_TCON_LOCAL4[0]), 0, 0 },
	{ "ixTHM_TCON_LOCAL5", REG_SMC, 0xd8202e14, &ixTHM_TCON_LOCAL5[0], sizeof(ixTHM_TCON_LOCAL5)/sizeof(ixTHM_TCON_LOCAL5[0]), 0, 0 },
	{ "ixTHM_TCON_LOCAL6", REG_SMC, 0xd8202e18, &ixTHM_TCON_LOCAL6[0], sizeof(ixTHM_TCON_LOCAL6)/sizeof(ixTHM_TCON_LOCAL6[0]), 0, 0 },
	{ "ixTHM_TCON_LOCAL7", REG_SMC, 0xd8202e1c, &ixTHM_TCON_LOCAL7[0], sizeof(ixTHM_TCON_LOCAL7)/sizeof(ixTHM_TCON_LOCAL7[0]), 0, 0 },
	{ "ixTHM_TCON_LOCAL8", REG_SMC, 0xd8202e20, &ixTHM_TCON_LOCAL8[0], sizeof(ixTHM_TCON_LOCAL8)/sizeof(ixTHM_TCON_LOCAL8[0]), 0, 0 },
	{ "ixTHM_TCON_LOCAL9", REG_SMC, 0xd8202e24, &ixTHM_TCON_LOCAL9[0], sizeof(ixTHM_TCON_LOCAL9)/sizeof(ixTHM_TCON_LOCAL9[0]), 0, 0 },
	{ "ixTHM_TCON_LOCAL10", REG_SMC, 0xd8202e28, &ixTHM_TCON_LOCAL10[0], sizeof(ixTHM_TCON_LOCAL10)/sizeof(ixTHM_TCON_LOCAL10[0]), 0, 0 },
	{ "ixTHM_TCON_LOCAL11", REG_SMC, 0xd8202e2c, &ixTHM_TCON_LOCAL11[0], sizeof(ixTHM_TCON_LOCAL11)/sizeof(ixTHM_TCON_LOCAL11[0]), 0, 0 },
	{ "ixTHM_TCON_LOCAL12", REG_SMC, 0xd8202e30, &ixTHM_TCON_LOCAL12[0], sizeof(ixTHM_TCON_LOCAL12)/sizeof(ixTHM_TCON_LOCAL12[0]), 0, 0 },
	{ "ixTHM_TCON_LOCAL13", REG_SMC, 0xd8202ef8, &ixTHM_TCON_LOCAL13[0], sizeof(ixTHM_TCON_LOCAL13)/sizeof(ixTHM_TCON_LOCAL13[0]), 0, 0 },
	{ "ixTHM_TCON_LOCAL14", REG_SMC, 0xd8202efc, &ixTHM_TCON_LOCAL14[0], sizeof(ixTHM_TCON_LOCAL14)/sizeof(ixTHM_TCON_LOCAL14[0]), 0, 0 },
	{ "ixTHM_FUSE0", REG_SMC, 0xd8210000, &ixTHM_FUSE0[0], sizeof(ixTHM_FUSE0)/sizeof(ixTHM_FUSE0[0]), 0, 0 },
	{ "ixTHM_FUSE1", REG_SMC, 0xd8210004, &ixTHM_FUSE1[0], sizeof(ixTHM_FUSE1)/sizeof(ixTHM_FUSE1[0]), 0, 0 },
	{ "ixTHM_FUSE2", REG_SMC, 0xd8210008, &ixTHM_FUSE2[0], sizeof(ixTHM_FUSE2)/sizeof(ixTHM_FUSE2[0]), 0, 0 },
	{ "ixTHM_FUSE3", REG_SMC, 0xd821000c, &ixTHM_FUSE3[0], sizeof(ixTHM_FUSE3)/sizeof(ixTHM_FUSE3[0]), 0, 0 },
	{ "ixTHM_FUSE4", REG_SMC, 0xd8210010, &ixTHM_FUSE4[0], sizeof(ixTHM_FUSE4)/sizeof(ixTHM_FUSE4[0]), 0, 0 },
	{ "ixTHM_FUSE5", REG_SMC, 0xd8210014, &ixTHM_FUSE5[0], sizeof(ixTHM_FUSE5)/sizeof(ixTHM_FUSE5[0]), 0, 0 },
	{ "ixTHM_FUSE6", REG_SMC, 0xd8210018, &ixTHM_FUSE6[0], sizeof(ixTHM_FUSE6)/sizeof(ixTHM_FUSE6[0]), 0, 0 },
	{ "ixTHM_FUSE7", REG_SMC, 0xd821001c, &ixTHM_FUSE7[0], sizeof(ixTHM_FUSE7)/sizeof(ixTHM_FUSE7[0]), 0, 0 },
	{ "ixTHM_FUSE8", REG_SMC, 0xd8210020, &ixTHM_FUSE8[0], sizeof(ixTHM_FUSE8)/sizeof(ixTHM_FUSE8[0]), 0, 0 },
	{ "ixTHM_FUSE9", REG_SMC, 0xd8210024, &ixTHM_FUSE9[0], sizeof(ixTHM_FUSE9)/sizeof(ixTHM_FUSE9[0]), 0, 0 },
	{ "ixTHM_FUSE10", REG_SMC, 0xd8210028, &ixTHM_FUSE10[0], sizeof(ixTHM_FUSE10)/sizeof(ixTHM_FUSE10[0]), 0, 0 },
	{ "ixTHM_FUSE11", REG_SMC, 0xd821002c, &ixTHM_FUSE11[0], sizeof(ixTHM_FUSE11)/sizeof(ixTHM_FUSE11[0]), 0, 0 },
	{ "ixTHM_FUSE12", REG_SMC, 0xd8210030, &ixTHM_FUSE12[0], sizeof(ixTHM_FUSE12)/sizeof(ixTHM_FUSE12[0]), 0, 0 },
	{ "ixGC_CAC_OVRD_CU", REG_SMC, 0xe7, &ixGC_CAC_OVRD_CU[0], sizeof(ixGC_CAC_OVRD_CU)/sizeof(ixGC_CAC_OVRD_CU[0]), 0, 0 },