634 ixPB0_DFT_DEBUG_CTRL_REG0 2 0x1300c 2 0 4294967295 DFT_PHY_DEBUG_EN 0 0 DFT_PHY_DEBUG_MODE 1 5 ixPB0_DFT_JIT_INJ_REG0 2 0x13000 5 0 4294967295 DFT_CLK_PER_STEP 8 11 DFT_DECR_SWP_EN 23 23 DFT_INCR_SWP_EN 22 22 DFT_NUM_STEPS 0 4 DFT_RECOVERY_TIME 24 31 ixPB0_DFT_JIT_INJ_REG1 2 0x13004 3 0 4294967295 DFT_BLOCK_EN 16 16 DFT_BYPASS_EN 8 8 DFT_BYPASS_VALUE 0 7 ixPB0_DFT_JIT_INJ_REG2 2 0x13008 1 0 4294967295 DFT_LANE_EN 0 15 ixPB0_GLB_CTRL_REG0 2 0x10004 8 0 4294967295 BACKUP 0 15 CFG_IDLEDET_TH 16 17 DBG_RX2TXBYP_SEL 20 22 DBG_RXFEBYP_EN 23 23 DBG_RXPRBS_CLR 24 24 DBG_RXTOGGLE_EN 25 25 DBG_TX2RXLBACK_EN 26 26 TXCFG_CMGOOD_RANGE 30 31 ixPB0_GLB_CTRL_REG1 2 0x10008 10 0 4294967295 PLL_CFG_DISPCLK_DIV 31 31 RXDBG_CDR_FR_BYP_EN 0 0 RXDBG_CDR_FR_BYP_VAL 1 6 RXDBG_CDR_PH_BYP_EN 7 7 RXDBG_CDR_PH_BYP_VAL 8 13 RXDBG_D0TH_BYP_EN 14 14 RXDBG_D0TH_BYP_VAL 15 21 RXDBG_D1TH_BYP_EN 22 22 RXDBG_D1TH_BYP_VAL 23 29 TST_LOSPDTST_EN 30 30 ixPB0_GLB_CTRL_REG2 2 0x1000c 8 0 4294967295 RXDBG_D2TH_BYP_EN 0 0 RXDBG_D2TH_BYP_VAL 1 7 RXDBG_D3TH_BYP_EN 8 8 RXDBG_D3TH_BYP_VAL 9 15 RXDBG_DXTH_BYP_EN 16 16 RXDBG_DXTH_BYP_VAL 17 23 RXDBG_ETH_BYP_EN 24 24 RXDBG_ETH_BYP_VAL 25 31 ixPB0_GLB_CTRL_REG3 2 0x10010 14 0 4294967295 BG_CFG_LC_REG_VREF0_SEL 5 6 BG_CFG_LC_REG_VREF1_SEL 7 8 BG_CFG_RO_REG_VREF_SEL 9 10 BG_DBG_ANALOG_SEL 14 16 BG_DBG_IREFBYP_EN 12 12 BG_DBG_VREFBYP_EN 11 11 DBG_DLL_CLK_SEL 18 20 DBG_RXLEQ_DCATTN_BYP_OVR_DISABLE 31 31 DBG_RXPI_OFFSET_BYP_EN 22 22 DBG_RXPI_OFFSET_BYP_VAL 23 26 DBG_RXSWAPDX_BYP_EN 27 27 DBG_RXSWAPDX_BYP_VAL 28 30 PLL_DISPCLK_CMOS_SEL 21 21 RXDBG_SEL 0 4 ixPB0_GLB_CTRL_REG4 2 0x10014 7 0 4294967295 DBG_RXAPU_EXEC 22 25 DBG_RXAPU_INST 0 15 DBG_RXDFEMUX_BYP_EN 18 18 DBG_RXDFEMUX_BYP_VAL 16 17 DBG_RXDLL_VREG_REF_SEL 26 26 DBG_RXRDATA_GATING_DISABLE 28 28 PWRGOOD_OVRD 27 27 ixPB0_GLB_CTRL_REG5 2 0x10018 1 0 4294967295 DBG_RXAPU_MODE 0 7 ixPB0_GLB_OVRD_REG0 2 0x10030 2 0 4294967295 TXPDTERM_VAL_OVRD_VAL 0 15 TXPUTERM_VAL_OVRD_VAL 16 31 ixPB0_GLB_OVRD_REG1 2 0x10034 6 0 4294967295 RXTERM_VAL_OVRD_EN 15 15 RXTERM_VAL_OVRD_VAL 16 31 TST_LOSPDTST_RST_OVRD_EN 2 2 TST_LOSPDTST_RST_OVRD_VAL 3 3 TXPDTERM_VAL_OVRD_EN 0 0 TXPUTERM_VAL_OVRD_EN 1 1 ixPB0_GLB_OVRD_REG2 2 0x10038 2 0 4294967295 BG_PWRON_OVRD_EN 0 0 BG_PWRON_OVRD_VAL 1 1 ixPB0_GLB_SCI_STAT_OVRD_REG0 2 0x1001c 9 0 4294967295 IGNR_ALL_SCI_UPDT_L0T3 0 0 IGNR_ALL_SCI_UPDT_L12T15 3 3 IGNR_ALL_SCI_UPDT_L4T7 1 1 IGNR_ALL_SCI_UPDT_L8T11 2 2 IGNR_IMPCAL_ACTIVE_SCI_UPDT 4 4 IMPCAL_ACTIVE 20 20 RXIMP 16 19 TXNIMP 8 11 TXPIMP 12 15 ixPB0_GLB_SCI_STAT_OVRD_REG1 2 0x10020 15 0 4294967295 DLL_LOCK_0 12 12 DLL_LOCK_1 13 13 DLL_LOCK_2 14 14 DLL_LOCK_3 15 15 FREQDIV_0 18 19 FREQDIV_1 22 23 FREQDIV_2 26 27 FREQDIV_3 30 31 IGNR_DLL_LOCK_SCI_UPDT_L0T3 2 2 IGNR_FREQDIV_SCI_UPDT_L0T3 1 1 IGNR_MODE_SCI_UPDT_L0T3 0 0 MODE_0 16 17 MODE_1 20 21 MODE_2 24 25 MODE_3 28 29 ixPB0_GLB_SCI_STAT_OVRD_REG2 2 0x10024 15 0 4294967295 DLL_LOCK_4 12 12 DLL_LOCK_5 13 13 DLL_LOCK_6 14 14 DLL_LOCK_7 15 15 FREQDIV_4 18 19 FREQDIV_5 22 23 FREQDIV_6 26 27 FREQDIV_7 30 31 IGNR_DLL_LOCK_SCI_UPDT_L4T7 2 2 IGNR_FREQDIV_SCI_UPDT_L4T7 1 1 IGNR_MODE_SCI_UPDT_L4T7 0 0 MODE_4 16 17 MODE_5 20 21 MODE_6 24 25 MODE_7 28 29 ixPB0_GLB_SCI_STAT_OVRD_REG3 2 0x10028 15 0 4294967295 DLL_LOCK_10 14 14 DLL_LOCK_11 15 15 DLL_LOCK_8 12 12 DLL_LOCK_9 13 13 FREQDIV_10 26 27 FREQDIV_11 30 31 FREQDIV_8 18 19 FREQDIV_9 22 23 IGNR_DLL_LOCK_SCI_UPDT_L8T11 2 2 IGNR_FREQDIV_SCI_UPDT_L8T11 1 1 IGNR_MODE_SCI_UPDT_L8T11 0 0 MODE_10 24 25 MODE_11 28 29 MODE_8 16 17 MODE_9 20 21 ixPB0_GLB_SCI_STAT_OVRD_REG4 2 0x1002c 15 0 4294967295 DLL_LOCK_12 12 12 DLL_LOCK_13 13 13 DLL_LOCK_14 14 14 DLL_LOCK_15 15 15 FREQDIV_12 18 19 FREQDIV_13 22 23 FREQDIV_14 26 27 FREQDIV_15 30 31 IGNR_DLL_LOCK_SCI_UPDT_L12T15 2 2 IGNR_FREQDIV_SCI_UPDT_L12T15 1 1 IGNR_MODE_SCI_UPDT_L12T15 0 0 MODE_12 16 17 MODE_13 20 21 MODE_14 24 25 MODE_15 28 29 ixPB0_HW_DEBUG 2 0x12004 32 0 4294967295 PB0_HW_00_DEBUG 0 0 PB0_HW_01_DEBUG 1 1 PB0_HW_02_DEBUG 2 2 PB0_HW_03_DEBUG 3 3 PB0_HW_04_DEBUG 4 4 PB0_HW_05_DEBUG 5 5 PB0_HW_06_DEBUG 6 6 PB0_HW_07_DEBUG 7 7 PB0_HW_08_DEBUG 8 8 PB0_HW_09_DEBUG 9 9 PB0_HW_10_DEBUG 10 10 PB0_HW_11_DEBUG 11 11 PB0_HW_12_DEBUG 12 12 PB0_HW_13_DEBUG 13 13 PB0_HW_14_DEBUG 14 14 PB0_HW_15_DEBUG 15 15 PB0_HW_16_DEBUG 16 16 PB0_HW_17_DEBUG 17 17 PB0_HW_18_DEBUG 18 18 PB0_HW_19_DEBUG 19 19 PB0_HW_20_DEBUG 20 20 PB0_HW_21_DEBUG 21 21 PB0_HW_22_DEBUG 22 22 PB0_HW_23_DEBUG 23 23 PB0_HW_24_DEBUG 24 24 PB0_HW_25_DEBUG 25 25 PB0_HW_26_DEBUG 26 26 PB0_HW_27_DEBUG 27 27 PB0_HW_28_DEBUG 28 28 PB0_HW_29_DEBUG 29 29 PB0_HW_30_DEBUG 30 30 PB0_HW_31_DEBUG 31 31 ixPB0_PIF_CNTL 2 0x10 20 0 4294967295 DA_FIFO_RESET_0 1 1 DA_FIFO_RESET_1 5 5 DA_FIFO_RESET_2 9 9 DA_FIFO_RESET_3 13 13 DIVINIT_MODE 8 8 EI_CYCLE_OFF_TIME 20 22 EI_DET_CYCLE_MODE 4 4 EXIT_L0S_INIT_DIS 23 23 EXTEND_WAIT_FOR_RAMPUP 28 28 IGNORE_TxDataValid_EP_DIS 29 29 LS2_EXIT_TIME 17 19 PHYCMD_CR_EN_MODE 3 3 PHY_CR_EN_MODE 2 2 PLL_BINDING_ENABLE 10 10 RXDETECT_FIFO_RESET_MODE 6 6 RXDETECT_TX_PWR_MODE 7 7 RXEN_GATER 24 27 SC_CALIB_DONE_CNTL 11 11 SERIAL_CFG_ENABLE 0 0 TXGND_TIME 16 16 ixPB0_PIF_CNTL2 2 0x14 19 0 4294967295 RXDETECT_OVERRIDE_EN 7 7 RXDETECT_OVERRIDE_VAL_0 8 8 RXDETECT_OVERRIDE_VAL_10 18 18 RXDETECT_OVERRIDE_VAL_11 19 19 RXDETECT_OVERRIDE_VAL_12 20 20 RXDETECT_OVERRIDE_VAL_13 21 21 RXDETECT_OVERRIDE_VAL_14 22 22 RXDETECT_OVERRIDE_VAL_15 23 23 RXDETECT_OVERRIDE_VAL_1 9 9 RXDETECT_OVERRIDE_VAL_2 10 10 RXDETECT_OVERRIDE_VAL_3 11 11 RXDETECT_OVERRIDE_VAL_4 12 12 RXDETECT_OVERRIDE_VAL_5 13 13 RXDETECT_OVERRIDE_VAL_6 14 14 RXDETECT_OVERRIDE_VAL_7 15 15 RXDETECT_OVERRIDE_VAL_8 16 16 RXDETECT_OVERRIDE_VAL_9 17 17 RXDETECT_SAMPL_TIME 1 2 RXPHYSTATUS_DELAY 24 26 ixPB0_PIF_HW_DEBUG 2 0x2 16 0 4294967295 PB0_PIF_HW_00_DEBUG 0 0 PB0_PIF_HW_01_DEBUG 1 1 PB0_PIF_HW_02_DEBUG 2 2 PB0_PIF_HW_03_DEBUG 3 3 PB0_PIF_HW_04_DEBUG 4 4 PB0_PIF_HW_05_DEBUG 5 5 PB0_PIF_HW_06_DEBUG 6 6 PB0_PIF_HW_07_DEBUG 7 7 PB0_PIF_HW_08_DEBUG 8 8 PB0_PIF_HW_09_DEBUG 9 9 PB0_PIF_HW_10_DEBUG 10 10 PB0_PIF_HW_11_DEBUG 11 11 PB0_PIF_HW_12_DEBUG 12 12 PB0_PIF_HW_13_DEBUG 13 13 PB0_PIF_HW_14_DEBUG 14 14 PB0_PIF_HW_15_DEBUG 15 15 ixPB0_PIF_PAIRING 2 0x11 16 0 4294967295 MULTI_PIF 25 25 X16_LANE_15_0 20 20 X2_LANE_1_0 0 0 X2_LANE_11_10 5 5 X2_LANE_13_12 6 6 X2_LANE_15_14 7 7 X2_LANE_3_2 1 1 X2_LANE_5_4 2 2 X2_LANE_7_6 3 3 X2_LANE_9_8 4 4 X4_LANE_11_8 10 10 X4_LANE_15_12 11 11 X4_LANE_3_0 8 8 X4_LANE_7_4 9 9 X8_LANE_15_8 17 17 X8_LANE_7_0 16 16 ixPB0_PIF_PDNB_OVERRIDE_0 2 0x20 10 0 4294967295 RXEN_OVERRIDE_EN_0 8 8 RXEN_OVERRIDE_VAL_0 9 9 RX_PDNB_OVERRIDE_EN_0 4 4 RX_PDNB_OVERRIDE_VAL_0 5 7 RXPWR_OVERRIDE_EN_0 14 14 RXPWR_OVERRIDE_VAL_0 15 17 TX_PDNB_OVERRIDE_EN_0 0 0 TX_PDNB_OVERRIDE_VAL_0 1 3 TXPWR_OVERRIDE_EN_0 10 10 TXPWR_OVERRIDE_VAL_0 11 13 ixPB0_PIF_PDNB_OVERRIDE_10 2 0x32 10 0 4294967295 RXEN_OVERRIDE_EN_10 8 8 RXEN_OVERRIDE_VAL_10 9 9 RX_PDNB_OVERRIDE_EN_10 4 4 RX_PDNB_OVERRIDE_VAL_10 5 7 RXPWR_OVERRIDE_EN_10 14 14 RXPWR_OVERRIDE_VAL_10 15 17 TX_PDNB_OVERRIDE_EN_10 0 0 TX_PDNB_OVERRIDE_VAL_10 1 3 TXPWR_OVERRIDE_EN_10 10 10 TXPWR_OVERRIDE_VAL_10 11 13 ixPB0_PIF_PDNB_OVERRIDE_1 2 0x21 10 0 4294967295 RXEN_OVERRIDE_EN_1 8 8 RXEN_OVERRIDE_VAL_1 9 9 RX_PDNB_OVERRIDE_EN_1 4 4 RX_PDNB_OVERRIDE_VAL_1 5 7 RXPWR_OVERRIDE_EN_1 14 14 RXPWR_OVERRIDE_VAL_1 15 17 TX_PDNB_OVERRIDE_EN_1 0 0 TX_PDNB_OVERRIDE_VAL_1 1 3 TXPWR_OVERRIDE_EN_1 10 10 TXPWR_OVERRIDE_VAL_1 11 13 ixPB0_PIF_PDNB_OVERRIDE_11 2 0x33 10 0 4294967295 RXEN_OVERRIDE_EN_11 8 8 RXEN_OVERRIDE_VAL_11 9 9 RX_PDNB_OVERRIDE_EN_11 4 4 RX_PDNB_OVERRIDE_VAL_11 5 7 RXPWR_OVERRIDE_EN_11 14 14 RXPWR_OVERRIDE_VAL_11 15 17 TX_PDNB_OVERRIDE_EN_11 0 0 TX_PDNB_OVERRIDE_VAL_11 1 3 TXPWR_OVERRIDE_EN_11 10 10 TXPWR_OVERRIDE_VAL_11 11 13 ixPB0_PIF_PDNB_OVERRIDE_12 2 0x34 10 0 4294967295 RXEN_OVERRIDE_EN_12 8 8 RXEN_OVERRIDE_VAL_12 9 9 RX_PDNB_OVERRIDE_EN_12 4 4 RX_PDNB_OVERRIDE_VAL_12 5 7 RXPWR_OVERRIDE_EN_12 14 14 RXPWR_OVERRIDE_VAL_12 15 17 TX_PDNB_OVERRIDE_EN_12 0 0 TX_PDNB_OVERRIDE_VAL_12 1 3 TXPWR_OVERRIDE_EN_12 10 10 TXPWR_OVERRIDE_VAL_12 11 13 ixPB0_PIF_PDNB_OVERRIDE_13 2 0x35 10 0 4294967295 RXEN_OVERRIDE_EN_13 8 8 RXEN_OVERRIDE_VAL_13 9 9 RX_PDNB_OVERRIDE_EN_13 4 4 RX_PDNB_OVERRIDE_VAL_13 5 7 RXPWR_OVERRIDE_EN_13 14 14 RXPWR_OVERRIDE_VAL_13 15 17 TX_PDNB_OVERRIDE_EN_13 0 0 TX_PDNB_OVERRIDE_VAL_13 1 3 TXPWR_OVERRIDE_EN_13 10 10 TXPWR_OVERRIDE_VAL_13 11 13 ixPB0_PIF_PDNB_OVERRIDE_14 2 0x36 10 0 4294967295 RXEN_OVERRIDE_EN_14 8 8 RXEN_OVERRIDE_VAL_14 9 9 RX_PDNB_OVERRIDE_EN_14 4 4 RX_PDNB_OVERRIDE_VAL_14 5 7 RXPWR_OVERRIDE_EN_14 14 14 RXPWR_OVERRIDE_VAL_14 15 17 TX_PDNB_OVERRIDE_EN_14 0 0 TX_PDNB_OVERRIDE_VAL_14 1 3 TXPWR_OVERRIDE_EN_14 10 10 TXPWR_OVERRIDE_VAL_14 11 13 ixPB0_PIF_PDNB_OVERRIDE_15 2 0x37 10 0 4294967295 RXEN_OVERRIDE_EN_15 8 8 RXEN_OVERRIDE_VAL_15 9 9 RX_PDNB_OVERRIDE_EN_15 4 4 RX_PDNB_OVERRIDE_VAL_15 5 7 RXPWR_OVERRIDE_EN_15 14 14 RXPWR_OVERRIDE_VAL_15 15 17 TX_PDNB_OVERRIDE_EN_15 0 0 TX_PDNB_OVERRIDE_VAL_15 1 3 TXPWR_OVERRIDE_EN_15 10 10 TXPWR_OVERRIDE_VAL_15 11 13 ixPB0_PIF_PDNB_OVERRIDE_2 2 0x22 10 0 4294967295 RXEN_OVERRIDE_EN_2 8 8 RXEN_OVERRIDE_VAL_2 9 9 RX_PDNB_OVERRIDE_EN_2 4 4 RX_PDNB_OVERRIDE_VAL_2 5 7 RXPWR_OVERRIDE_EN_2 14 14 RXPWR_OVERRIDE_VAL_2 15 17 TX_PDNB_OVERRIDE_EN_2 0 0 TX_PDNB_OVERRIDE_VAL_2 1 3 TXPWR_OVERRIDE_EN_2 10 10 TXPWR_OVERRIDE_VAL_2 11 13 ixPB0_PIF_PDNB_OVERRIDE_3 2 0x23 10 0 4294967295 RXEN_OVERRIDE_EN_3 8 8 RXEN_OVERRIDE_VAL_3 9 9 RX_PDNB_OVERRIDE_EN_3 4 4 RX_PDNB_OVERRIDE_VAL_3 5 7 RXPWR_OVERRIDE_EN_3 14 14 RXPWR_OVERRIDE_VAL_3 15 17 TX_PDNB_OVERRIDE_EN_3 0 0 TX_PDNB_OVERRIDE_VAL_3 1 3 TXPWR_OVERRIDE_EN_3 10 10 TXPWR_OVERRIDE_VAL_3 11 13 ixPB0_PIF_PDNB_OVERRIDE_4 2 0x24 10 0 4294967295 RXEN_OVERRIDE_EN_4 8 8 RXEN_OVERRIDE_VAL_4 9 9 RX_PDNB_OVERRIDE_EN_4 4 4 RX_PDNB_OVERRIDE_VAL_4 5 7 RXPWR_OVERRIDE_EN_4 14 14 RXPWR_OVERRIDE_VAL_4 15 17 TX_PDNB_OVERRIDE_EN_4 0 0 TX_PDNB_OVERRIDE_VAL_4 1 3 TXPWR_OVERRIDE_EN_4 10 10 TXPWR_OVERRIDE_VAL_4 11 13 ixPB0_PIF_PDNB_OVERRIDE_5 2 0x25 10 0 4294967295 RXEN_OVERRIDE_EN_5 8 8 RXEN_OVERRIDE_VAL_5 9 9 RX_PDNB_OVERRIDE_EN_5 4 4 RX_PDNB_OVERRIDE_VAL_5 5 7 RXPWR_OVERRIDE_EN_5 14 14 RXPWR_OVERRIDE_VAL_5 15 17 TX_PDNB_OVERRIDE_EN_5 0 0 TX_PDNB_OVERRIDE_VAL_5 1 3 TXPWR_OVERRIDE_EN_5 10 10 TXPWR_OVERRIDE_VAL_5 11 13 ixPB0_PIF_PDNB_OVERRIDE_6 2 0x26 10 0 4294967295 RXEN_OVERRIDE_EN_6 8 8 RXEN_OVERRIDE_VAL_6 9 9 RX_PDNB_OVERRIDE_EN_6 4 4 RX_PDNB_OVERRIDE_VAL_6 5 7 RXPWR_OVERRIDE_EN_6 14 14 RXPWR_OVERRIDE_VAL_6 15 17 TX_PDNB_OVERRIDE_EN_6 0 0 TX_PDNB_OVERRIDE_VAL_6 1 3 TXPWR_OVERRIDE_EN_6 10 10 TXPWR_OVERRIDE_VAL_6 11 13 ixPB0_PIF_PDNB_OVERRIDE_7 2 0x27 10 0 4294967295 RXEN_OVERRIDE_EN_7 8 8 RXEN_OVERRIDE_VAL_7 9 9 RX_PDNB_OVERRIDE_EN_7 4 4 RX_PDNB_OVERRIDE_VAL_7 5 7 RXPWR_OVERRIDE_EN_7 14 14 RXPWR_OVERRIDE_VAL_7 15 17 TX_PDNB_OVERRIDE_EN_7 0 0 TX_PDNB_OVERRIDE_VAL_7 1 3 TXPWR_OVERRIDE_EN_7 10 10 TXPWR_OVERRIDE_VAL_7 11 13 ixPB0_PIF_PDNB_OVERRIDE_8 2 0x30 10 0 4294967295 RXEN_OVERRIDE_EN_8 8 8 RXEN_OVERRIDE_VAL_8 9 9 RX_PDNB_OVERRIDE_EN_8 4 4 RX_PDNB_OVERRIDE_VAL_8 5 7 RXPWR_OVERRIDE_EN_8 14 14 RXPWR_OVERRIDE_VAL_8 15 17 TX_PDNB_OVERRIDE_EN_8 0 0 TX_PDNB_OVERRIDE_VAL_8 1 3 TXPWR_OVERRIDE_EN_8 10 10 TXPWR_OVERRIDE_VAL_8 11 13 ixPB0_PIF_PDNB_OVERRIDE_9 2 0x31 10 0 4294967295 RXEN_OVERRIDE_EN_9 8 8 RXEN_OVERRIDE_VAL_9 9 9 RX_PDNB_OVERRIDE_EN_9 4 4 RX_PDNB_OVERRIDE_VAL_9 5 7 RXPWR_OVERRIDE_EN_9 14 14 RXPWR_OVERRIDE_VAL_9 15 17 TX_PDNB_OVERRIDE_EN_9 0 0 TX_PDNB_OVERRIDE_VAL_9 1 3 TXPWR_OVERRIDE_EN_9 10 10 TXPWR_OVERRIDE_VAL_9 11 13 ixPB0_PIF_PWRDOWN_0 2 0x12 9 0 4294967295 FORCE_RXEN_IN_L0s_0 3 3 PLL_POWER_STATE_IN_OFF_0 10 12 PLL_POWER_STATE_IN_TXS2_0 7 9 PLLPWR_OVERRIDE_EN_0 28 28 PLLPWR_OVERRIDE_VAL_0 29 31 PLL_RAMP_UP_TIME_0 24 26 RX_POWER_STATE_IN_RXS2_0 4 6 TX2P5CLK_CLOCK_GATING_EN_0 16 16 TX_POWER_STATE_IN_TXS2_0 0 2 ixPB0_PIF_PWRDOWN_1 2 0x13 9 0 4294967295 FORCE_RXEN_IN_L0s_1 3 3 PLL_POWER_STATE_IN_OFF_1 10 12 PLL_POWER_STATE_IN_TXS2_1 7 9 PLLPWR_OVERRIDE_EN_1 28 28 PLLPWR_OVERRIDE_VAL_1 29 31 PLL_RAMP_UP_TIME_1 24 26 RX_POWER_STATE_IN_RXS2_1 4 6 TX2P5CLK_CLOCK_GATING_EN_1 16 16 TX_POWER_STATE_IN_TXS2_1 0 2 ixPB0_PIF_PWRDOWN_2 2 0x17 9 0 4294967295 FORCE_RXEN_IN_L0s_2 3 3 PLL_POWER_STATE_IN_OFF_2 10 12 PLL_POWER_STATE_IN_TXS2_2 7 9 PLLPWR_OVERRIDE_EN_2 28 28 PLLPWR_OVERRIDE_VAL_2 29 31 PLL_RAMP_UP_TIME_2 24 26 RX_POWER_STATE_IN_RXS2_2 4 6 TX2P5CLK_CLOCK_GATING_EN_2 16 16 TX_POWER_STATE_IN_TXS2_2 0 2 ixPB0_PIF_PWRDOWN_3 2 0x18 9 0 4294967295 FORCE_RXEN_IN_L0s_3 3 3 PLL_POWER_STATE_IN_OFF_3 10 12 PLL_POWER_STATE_IN_TXS2_3 7 9 PLLPWR_OVERRIDE_EN_3 28 28 PLLPWR_OVERRIDE_VAL_3 29 31 PLL_RAMP_UP_TIME_3 24 26 RX_POWER_STATE_IN_RXS2_3 4 6 TX2P5CLK_CLOCK_GATING_EN_3 16 16 TX_POWER_STATE_IN_TXS2_3 0 2 ixPB0_PIF_SC_CTL 2 0x16 31 0 4294967295 SC_CALIBRATION 0 0 SC_ENTER_L1_FROM_L0 5 5 SC_ENTER_L1_FROM_L0S 4 4 SC_EXIT_L1_TO_L0 3 3 SC_EXIT_L1_TO_L0S 2 2 SC_LANE_0_RESUME 16 16 SC_LANE_10_RESUME 26 26 SC_LANE_11_RESUME 27 27 SC_LANE_12_RESUME 28 28 SC_LANE_13_RESUME 29 29 SC_LANE_14_RESUME 30 30 SC_LANE_15_RESUME 31 31 SC_LANE_1_RESUME 17 17 SC_LANE_2_RESUME 18 18 SC_LANE_3_RESUME 19 19 SC_LANE_4_RESUME 20 20 SC_LANE_5_RESUME 21 21 SC_LANE_6_RESUME 22 22 SC_LANE_7_RESUME 23 23 SC_LANE_8_RESUME 24 24 SC_LANE_9_RESUME 25 25 SC_PHASE_1 8 8 SC_PHASE_2 9 9 SC_PHASE_3 10 10 SC_PHASE_4 11 11 SC_PHASE_5 12 12 SC_PHASE_6 13 13 SC_PHASE_7 14 14 SC_PHASE_8 15 15 SC_RXDETECT 1 1 SC_SPEED_CHANGE 6 6 ixPB0_PIF_SCRATCH 2 0x1 1 0 4294967295 PIF_SCRATCH 0 31 ixPB0_PIF_SEQ_STATUS_0 2 0x28 8 0 4294967295 SEQ_CALIBRATION_0 0 0 SEQ_ENTER_L1_FROM_L0_0 5 5 SEQ_ENTER_L1_FROM_L0S_0 4 4 SEQ_EXIT_L1_TO_L0_0 3 3 SEQ_EXIT_L1_TO_L0S_0 2 2 SEQ_PHASE_0 8 10 SEQ_RXDETECT_0 1 1 SEQ_SPEED_CHANGE_0 6 6 ixPB0_PIF_SEQ_STATUS_10 2 0x3a 8 0 4294967295 SEQ_CALIBRATION_10 0 0 SEQ_ENTER_L1_FROM_L0_10 5 5 SEQ_ENTER_L1_FROM_L0S_10 4 4 SEQ_EXIT_L1_TO_L0_10 3 3 SEQ_EXIT_L1_TO_L0S_10 2 2 SEQ_PHASE_10 8 10 SEQ_RXDETECT_10 1 1 SEQ_SPEED_CHANGE_10 6 6 ixPB0_PIF_SEQ_STATUS_1 2 0x29 8 0 4294967295 SEQ_CALIBRATION_1 0 0 SEQ_ENTER_L1_FROM_L0_1 5 5 SEQ_ENTER_L1_FROM_L0S_1 4 4 SEQ_EXIT_L1_TO_L0_1 3 3 SEQ_EXIT_L1_TO_L0S_1 2 2 SEQ_PHASE_1 8 10 SEQ_RXDETECT_1 1 1 SEQ_SPEED_CHANGE_1 6 6 ixPB0_PIF_SEQ_STATUS_11 2 0x3b 8 0 4294967295 SEQ_CALIBRATION_11 0 0 SEQ_ENTER_L1_FROM_L0_11 5 5 SEQ_ENTER_L1_FROM_L0S_11 4 4 SEQ_EXIT_L1_TO_L0_11 3 3 SEQ_EXIT_L1_TO_L0S_11 2 2 SEQ_PHASE_11 8 10 SEQ_RXDETECT_11 1 1 SEQ_SPEED_CHANGE_11 6 6 ixPB0_PIF_SEQ_STATUS_12 2 0x3c 8 0 4294967295 SEQ_CALIBRATION_12 0 0 SEQ_ENTER_L1_FROM_L0_12 5 5 SEQ_ENTER_L1_FROM_L0S_12 4 4 SEQ_EXIT_L1_TO_L0_12 3 3 SEQ_EXIT_L1_TO_L0S_12 2 2 SEQ_PHASE_12 8 10 SEQ_RXDETECT_12 1 1 SEQ_SPEED_CHANGE_12 6 6 ixPB0_PIF_SEQ_STATUS_13 2 0x3d 8 0 4294967295 SEQ_CALIBRATION_13 0 0 SEQ_ENTER_L1_FROM_L0_13 5 5 SEQ_ENTER_L1_FROM_L0S_13 4 4 SEQ_EXIT_L1_TO_L0_13 3 3 SEQ_EXIT_L1_TO_L0S_13 2 2 SEQ_PHASE_13 8 10 SEQ_RXDETECT_13 1 1 SEQ_SPEED_CHANGE_13 6 6 ixPB0_PIF_SEQ_STATUS_14 2 0x3e 8 0 4294967295 SEQ_CALIBRATION_14 0 0 SEQ_ENTER_L1_FROM_L0_14 5 5 SEQ_ENTER_L1_FROM_L0S_14 4 4 SEQ_EXIT_L1_TO_L0_14 3 3 SEQ_EXIT_L1_TO_L0S_14 2 2 SEQ_PHASE_14 8 10 SEQ_RXDETECT_14 1 1 SEQ_SPEED_CHANGE_14 6 6 ixPB0_PIF_SEQ_STATUS_15 2 0x3f 8 0 4294967295 SEQ_CALIBRATION_15 0 0 SEQ_ENTER_L1_FROM_L0_15 5 5 SEQ_ENTER_L1_FROM_L0S_15 4 4 SEQ_EXIT_L1_TO_L0_15 3 3 SEQ_EXIT_L1_TO_L0S_15 2 2 SEQ_PHASE_15 8 10 SEQ_RXDETECT_15 1 1 SEQ_SPEED_CHANGE_15 6 6 ixPB0_PIF_SEQ_STATUS_2 2 0x2a 8 0 4294967295 SEQ_CALIBRATION_2 0 0 SEQ_ENTER_L1_FROM_L0_2 5 5 SEQ_ENTER_L1_FROM_L0S_2 4 4 SEQ_EXIT_L1_TO_L0_2 3 3 SEQ_EXIT_L1_TO_L0S_2 2 2 SEQ_PHASE_2 8 10 SEQ_RXDETECT_2 1 1 SEQ_SPEED_CHANGE_2 6 6 ixPB0_PIF_SEQ_STATUS_3 2 0x2b 8 0 4294967295 SEQ_CALIBRATION_3 0 0 SEQ_ENTER_L1_FROM_L0_3 5 5 SEQ_ENTER_L1_FROM_L0S_3 4 4 SEQ_EXIT_L1_TO_L0_3 3 3 SEQ_EXIT_L1_TO_L0S_3 2 2 SEQ_PHASE_3 8 10 SEQ_RXDETECT_3 1 1 SEQ_SPEED_CHANGE_3 6 6 ixPB0_PIF_SEQ_STATUS_4 2 0x2c 8 0 4294967295 SEQ_CALIBRATION_4 0 0 SEQ_ENTER_L1_FROM_L0_4 5 5 SEQ_ENTER_L1_FROM_L0S_4 4 4 SEQ_EXIT_L1_TO_L0_4 3 3 SEQ_EXIT_L1_TO_L0S_4 2 2 SEQ_PHASE_4 8 10 SEQ_RXDETECT_4 1 1 SEQ_SPEED_CHANGE_4 6 6 ixPB0_PIF_SEQ_STATUS_5 2 0x2d 8 0 4294967295 SEQ_CALIBRATION_5 0 0 SEQ_ENTER_L1_FROM_L0_5 5 5 SEQ_ENTER_L1_FROM_L0S_5 4 4 SEQ_EXIT_L1_TO_L0_5 3 3 SEQ_EXIT_L1_TO_L0S_5 2 2 SEQ_PHASE_5 8 10 SEQ_RXDETECT_5 1 1 SEQ_SPEED_CHANGE_5 6 6 ixPB0_PIF_SEQ_STATUS_6 2 0x2e 8 0 4294967295 SEQ_CALIBRATION_6 0 0 SEQ_ENTER_L1_FROM_L0_6 5 5 SEQ_ENTER_L1_FROM_L0S_6 4 4 SEQ_EXIT_L1_TO_L0_6 3 3 SEQ_EXIT_L1_TO_L0S_6 2 2 SEQ_PHASE_6 8 10 SEQ_RXDETECT_6 1 1 SEQ_SPEED_CHANGE_6 6 6 ixPB0_PIF_SEQ_STATUS_7 2 0x2f 8 0 4294967295 SEQ_CALIBRATION_7 0 0 SEQ_ENTER_L1_FROM_L0_7 5 5 SEQ_ENTER_L1_FROM_L0S_7 4 4 SEQ_EXIT_L1_TO_L0_7 3 3 SEQ_EXIT_L1_TO_L0S_7 2 2 SEQ_PHASE_7 8 10 SEQ_RXDETECT_7 1 1 SEQ_SPEED_CHANGE_7 6 6 ixPB0_PIF_SEQ_STATUS_8 2 0x38 8 0 4294967295 SEQ_CALIBRATION_8 0 0 SEQ_ENTER_L1_FROM_L0_8 5 5 SEQ_ENTER_L1_FROM_L0S_8 4 4 SEQ_EXIT_L1_TO_L0_8 3 3 SEQ_EXIT_L1_TO_L0S_8 2 2 SEQ_PHASE_8 8 10 SEQ_RXDETECT_8 1 1 SEQ_SPEED_CHANGE_8 6 6 ixPB0_PIF_SEQ_STATUS_9 2 0x39 8 0 4294967295 SEQ_CALIBRATION_9 0 0 SEQ_ENTER_L1_FROM_L0_9 5 5 SEQ_ENTER_L1_FROM_L0S_9 4 4 SEQ_EXIT_L1_TO_L0_9 3 3 SEQ_EXIT_L1_TO_L0S_9 2 2 SEQ_PHASE_9 8 10 SEQ_RXDETECT_9 1 1 SEQ_SPEED_CHANGE_9 6 6 ixPB0_PIF_TXPHYSTATUS 2 0x15 16 0 4294967295 TXPHYSTATUS_0 0 0 TXPHYSTATUS_10 10 10 TXPHYSTATUS_11 11 11 TXPHYSTATUS_12 12 12 TXPHYSTATUS_13 13 13 TXPHYSTATUS_14 14 14 TXPHYSTATUS_15 15 15 TXPHYSTATUS_1 1 1 TXPHYSTATUS_2 2 2 TXPHYSTATUS_3 3 3 TXPHYSTATUS_4 4 4 TXPHYSTATUS_5 5 5 TXPHYSTATUS_6 6 6 TXPHYSTATUS_7 7 7 TXPHYSTATUS_8 8 8 TXPHYSTATUS_9 9 9 ixPB0_PLL_LC0_CTRL_REG0 2 0x14480 4 0 4294967295 PLL_DBG_LC_ANALOG_SEL_0 0 1 PLL_DBG_LC_EXT_RESET_EN_0 2 2 PLL_DBG_LC_VCTL_ADC_EN_0 3 3 PLL_TST_LC_USAMPLE_EN_0 4 4 ixPB0_PLL_LC0_OVRD_REG0 2 0x14490 12 0 4294967295 PLL_CFG_LC_BW_CNTRL_OVRD_EN_0 3 3 PLL_CFG_LC_BW_CNTRL_OVRD_VAL_0 0 2 PLL_CFG_LC_CORECLK_DIV_OVRD_EN_0 7 7 PLL_CFG_LC_CORECLK_DIV_OVRD_VAL_0 4 6 PLL_CFG_LC_CORECLK_EN_OVRD_EN_0 9 9 PLL_CFG_LC_CORECLK_EN_OVRD_VAL_0 8 8 PLL_CFG_LC_FBDIV_OVRD_EN_0 18 18 PLL_CFG_LC_FBDIV_OVRD_VAL_0 10 17 PLL_CFG_LC_LF_CNTRL_OVRD_EN_0 28 28 PLL_CFG_LC_LF_CNTRL_OVRD_VAL_0 19 27 PLL_CFG_LC_REFDIV_OVRD_EN_0 31 31 PLL_CFG_LC_REFDIV_OVRD_VAL_0 29 30 ixPB0_PLL_LC0_OVRD_REG1 2 0x14494 10 0 4294967295 PLL_CFG_LC_REFCLK_SRC_OVRD_EN_0 3 3 PLL_CFG_LC_REFCLK_SRC_OVRD_VAL_0 0 2 PLL_CFG_LC_VCO_TUNE_OVRD_EN_0 18 18 PLL_CFG_LC_VCO_TUNE_OVRD_VAL_0 14 17 PLL_LC_HSCLK_LEFT_EN_OVRD_EN_0 5 5 PLL_LC_HSCLK_LEFT_EN_OVRD_VAL_0 4 4 PLL_LC_HSCLK_RIGHT_EN_OVRD_EN_0 7 7 PLL_LC_HSCLK_RIGHT_EN_OVRD_VAL_0 6 6 PLL_LC_PWRON_OVRD_EN_0 9 9 PLL_LC_PWRON_OVRD_VAL_0 8 8 ixPB0_PLL_LC0_SCI_STAT_OVRD_REG0 2 0x14500 4 0 4294967295 PLL_LC0_FREQMODE 8 9 PLL_LC0_IGNR_FREQMODE_SCI_UPDT 1 1 PLL_LC0_IGNR_PLLPWR_SCI_UPDT 0 0 PLL_LC0_PLLPWR 4 6 ixPB0_PLL_LC1_SCI_STAT_OVRD_REG0 2 0x14504 4 0 4294967295 PLL_LC1_FREQMODE 8 9 PLL_LC1_IGNR_FREQMODE_SCI_UPDT 1 1 PLL_LC1_IGNR_PLLPWR_SCI_UPDT 0 0 PLL_LC1_PLLPWR 4 6 ixPB0_PLL_LC2_SCI_STAT_OVRD_REG0 2 0x14508 4 0 4294967295 PLL_LC2_FREQMODE 8 9 PLL_LC2_IGNR_FREQMODE_SCI_UPDT 1 1 PLL_LC2_IGNR_PLLPWR_SCI_UPDT 0 0 PLL_LC2_PLLPWR 4 6 ixPB0_PLL_LC3_SCI_STAT_OVRD_REG0 2 0x1450c 4 0 4294967295 PLL_LC3_FREQMODE 8 9 PLL_LC3_IGNR_FREQMODE_SCI_UPDT 1 1 PLL_LC3_IGNR_PLLPWR_SCI_UPDT 0 0 PLL_LC3_PLLPWR 4 6 ixPB0_PLL_RO0_CTRL_REG0 2 0x14440 5 0 4294967295 PLL_DBG_RO_ANALOG_SEL_0 0 1 PLL_DBG_RO_EXT_RESET_EN_0 2 2 PLL_DBG_RO_LF_CNTRL_0 4 10 PLL_DBG_RO_VCTL_ADC_EN_0 3 3 PLL_TST_RO_USAMPLE_EN_0 11 11 ixPB0_PLL_RO0_OVRD_REG0 2 0x14450 10 0 4294967295 PLL_CFG_RO_BW_CNTRL_OVRD_EN_0 8 8 PLL_CFG_RO_BW_CNTRL_OVRD_VAL_0 0 7 PLL_CFG_RO_CORECLK_DIV_OVRD_EN_0 12 12 PLL_CFG_RO_CORECLK_DIV_OVRD_VAL_0 9 11 PLL_CFG_RO_CORECLK_EN_OVRD_EN_0 14 14 PLL_CFG_RO_CORECLK_EN_OVRD_VAL_0 13 13 PLL_CFG_RO_FBDIV_OVRD_EN_0 28 28 PLL_CFG_RO_FBDIV_OVRD_VAL_0 15 27 PLL_CFG_RO_VTOI_BIAS_CNTRL_OVRD_EN_0 31 31 PLL_CFG_RO_VTOI_BIAS_CNTRL_OVRD_VAL_0 30 30 ixPB0_PLL_RO0_OVRD_REG1 2 0x14454 12 0 4294967295 PLL_CFG_RO_REFCLK_SRC_OVRD_EN_0 22 22 PLL_CFG_RO_REFCLK_SRC_OVRD_VAL_0 19 21 PLL_CFG_RO_REFDIV_OVRD_EN_0 5 5 PLL_CFG_RO_REFDIV_OVRD_VAL_0 0 4 PLL_CFG_RO_VCO_MODE_OVRD_EN_0 8 8 PLL_CFG_RO_VCO_MODE_OVRD_VAL_0 6 7 PLL_RO_HSCLK_LEFT_EN_OVRD_EN_0 10 10 PLL_RO_HSCLK_LEFT_EN_OVRD_VAL_0 9 9 PLL_RO_HSCLK_RIGHT_EN_OVRD_EN_0 12 12 PLL_RO_HSCLK_RIGHT_EN_OVRD_VAL_0 11 11 PLL_RO_PWRON_OVRD_EN_0 14 14 PLL_RO_PWRON_OVRD_VAL_0 13 13 ixPB0_PLL_RO0_SCI_STAT_OVRD_REG0 2 0x14460 4 0 4294967295 PLL_RO0_FREQMODE 8 9 PLL_RO0_IGNR_FREQMODE_SCI_UPDT 1 1 PLL_RO0_IGNR_PLLPWR_SCI_UPDT 0 0 PLL_RO0_PLLPWR 4 6 ixPB0_PLL_RO1_SCI_STAT_OVRD_REG0 2 0x14464 4 0 4294967295 PLL_RO1_FREQMODE 8 9 PLL_RO1_IGNR_FREQMODE_SCI_UPDT 1 1 PLL_RO1_IGNR_PLLPWR_SCI_UPDT 0 0 PLL_RO1_PLLPWR 4 6 ixPB0_PLL_RO2_SCI_STAT_OVRD_REG0 2 0x14468 4 0 4294967295 PLL_RO2_FREQMODE 8 9 PLL_RO2_IGNR_FREQMODE_SCI_UPDT 1 1 PLL_RO2_IGNR_PLLPWR_SCI_UPDT 0 0 PLL_RO2_PLLPWR 4 6 ixPB0_PLL_RO3_SCI_STAT_OVRD_REG0 2 0x1446c 4 0 4294967295 PLL_RO3_FREQMODE 8 9 PLL_RO3_IGNR_FREQMODE_SCI_UPDT 1 1 PLL_RO3_IGNR_PLLPWR_SCI_UPDT 0 0 PLL_RO3_PLLPWR 4 6 ixPB0_PLL_RO_GLB_CTRL_REG0 2 0x14000 23 0 4294967295 PLL_LC_HSCLK_LEFT_EN_LUT_ENTRY_LS0 9 9 PLL_LC_HSCLK_LEFT_EN_LUT_ENTRY_LS1 10 10 PLL_LC_HSCLK_LEFT_EN_LUT_ENTRY_LS2 11 11 PLL_LC_HSCLK_LEFT_LEFT_EN_GATING_EN 20 20 PLL_LC_HSCLK_LEFT_RIGHT_EN_GATING_EN 21 21 PLL_LC_HSCLK_RIGHT_EN_LUT_ENTRY_LS0 12 12 PLL_LC_HSCLK_RIGHT_EN_LUT_ENTRY_LS1 13 13 PLL_LC_HSCLK_RIGHT_EN_LUT_ENTRY_LS2 14 14 PLL_LC_HSCLK_RIGHT_LEFT_EN_GATING_EN 22 22 PLL_LC_HSCLK_RIGHT_RIGHT_EN_GATING_EN 23 23 PLL_LC_PWRON_LUT_ENTRY_LS2 8 8 PLL_RO_HSCLK_LEFT_EN_LUT_ENTRY_LS0 1 1 PLL_RO_HSCLK_LEFT_EN_LUT_ENTRY_LS1 2 2 PLL_RO_HSCLK_LEFT_EN_LUT_ENTRY_LS2 3 3 PLL_RO_HSCLK_LEFT_LEFT_EN_GATING_EN 16 16 PLL_RO_HSCLK_LEFT_RIGHT_EN_GATING_EN 17 17 PLL_RO_HSCLK_RIGHT_EN_LUT_ENTRY_LS0 4 4 PLL_RO_HSCLK_RIGHT_EN_LUT_ENTRY_LS1 5 5 PLL_RO_HSCLK_RIGHT_EN_LUT_ENTRY_LS2 6 6 PLL_RO_HSCLK_RIGHT_LEFT_EN_GATING_EN 18 18 PLL_RO_HSCLK_RIGHT_RIGHT_EN_GATING_EN 19 19 PLL_RO_PWRON_LUT_ENTRY_LS2 7 7 PLL_TST_LOSPDTST_SRC 0 0 ixPB0_PLL_RO_GLB_OVRD_REG0 2 0x14010 0 0 4294967295 ixPB0_RX_GLB_CTRL_REG0 2 0x16000 4 0 4294967295 RX_CFG_ADAPT_MODE_GEN1 0 9 RX_CFG_ADAPT_MODE_GEN2 10 19 RX_CFG_ADAPT_MODE_GEN3 20 29 RX_CFG_ADAPT_RST_MODE 30 31 ixPB0_RX_GLB_CTRL_REG1 2 0x16004 13 0 4294967295 RX_ADAPT_HLD_ASRT_TO_DCLK_EN 30 31 RX_CFG_CDR_FR_GAIN_GEN1 0 3 RX_CFG_CDR_FR_GAIN_GEN2 4 7 RX_CFG_CDR_FR_GAIN_GEN3 8 11 RX_CFG_CDR_PH_GAIN_GEN1 12 15 RX_CFG_CDR_PH_GAIN_GEN2 16 19 RX_CFG_CDR_PH_GAIN_GEN3 20 23 RX_CFG_CDR_PI_STPSZ_GEN1 24 24 RX_CFG_CDR_PI_STPSZ_GEN2 25 25 RX_CFG_CDR_PI_STPSZ_GEN3 26 26 RX_CFG_LEQ_DCATTN_BYP_EN_GEN1 27 27 RX_CFG_LEQ_DCATTN_BYP_EN_GEN2 28 28 RX_CFG_LEQ_DCATTN_BYP_EN_GEN3 29 29 ixPB0_RX_GLB_CTRL_REG2 2 0x16008 7 0 4294967295 RX_CFG_CDR_TIME_GEN1 12 15 RX_CFG_CDR_TIME_GEN2 16 19 RX_CFG_CDR_TIME_GEN3 20 23 RX_CFG_LEQ_LOOP_GAIN_GEN1 24 25 RX_CFG_LEQ_LOOP_GAIN_GEN2 26 27 RX_CFG_LEQ_LOOP_GAIN_GEN3 28 29 RX_DCLK_EN_ASRT_TO_ADAPT_HLD 30 31 ixPB0_RX_GLB_CTRL_REG3 2 0x1600c 6 0 4294967295 RX_CFG_CDR_FR_EN_GEN1 0 0 RX_CFG_CDR_FR_EN_GEN2 1 1 RX_CFG_CDR_FR_EN_GEN3 2 2 RX_CFG_DFE_TIME_GEN1 20 23 RX_CFG_DFE_TIME_GEN2 24 27 RX_CFG_DFE_TIME_GEN3 28 31 ixPB0_RX_GLB_CTRL_REG4 2 0x16010 9 0 4294967295 RX_CFG_FOM_BER_GEN1 0 2 RX_CFG_FOM_BER_GEN2 3 5 RX_CFG_FOM_BER_GEN3 6 8 RX_CFG_FOM_TIME_GEN1 20 23 RX_CFG_FOM_TIME_GEN2 24 27 RX_CFG_FOM_TIME_GEN3 28 31 RX_CFG_LEQ_POLE_BYP_VAL_GEN1 9 11 RX_CFG_LEQ_POLE_BYP_VAL_GEN2 12 14 RX_CFG_LEQ_POLE_BYP_VAL_GEN3 15 17 ixPB0_RX_GLB_CTRL_REG5 2 0x16014 13 0 4294967295 RX_CFG_LEQ_DCATTN_BYP_VAL_GEN1 0 4 RX_CFG_LEQ_DCATTN_BYP_VAL_GEN2 5 9 RX_CFG_LEQ_DCATTN_BYP_VAL_GEN3 10 14 RX_CFG_LEQ_POLE_BYP_EN_GEN1 15 15 RX_CFG_LEQ_POLE_BYP_EN_GEN2 16 16 RX_CFG_LEQ_POLE_BYP_EN_GEN3 17 17 RX_CFG_LEQ_SHUNT_EN_GEN1 18 18 RX_CFG_LEQ_SHUNT_EN_GEN2 19 19 RX_CFG_LEQ_SHUNT_EN_GEN3 20 20 RX_CFG_TERM_MODE_GEN1 27 27 RX_CFG_TERM_MODE_GEN2 28 28 RX_CFG_TERM_MODE_GEN3 29 29 RX_FORCE_DLL_RST_RXPWR_LS2OFF_TO_LS0 30 30 ixPB0_RX_GLB_CTRL_REG6 2 0x16018 9 0 4294967295 RX_AUX_PWRON_LUT_ENTRY_LS2 27 27 RX_CFG_LEQ_TIME_GEN1 0 3 RX_CFG_LEQ_TIME_GEN2 4 7 RX_CFG_LEQ_TIME_GEN3 8 11 RX_CFG_OC_TIME_GEN1 12 15 RX_CFG_OC_TIME_GEN2 16 19 RX_CFG_OC_TIME_GEN3 20 23 RX_FRONTEND_PWRON_LUT_ENTRY_LS0_CDR_EN_0 24 24 RX_FRONTEND_PWRON_LUT_ENTRY_LS2 26 26 ixPB0_RX_GLB_CTRL_REG7 2 0x1601c 12 0 4294967295 RX_CFG_DLL_CPI_SEL_GEN1 18 20 RX_CFG_DLL_CPI_SEL_GEN2 21 23 RX_CFG_DLL_CPI_SEL_GEN3 24 26 RX_CFG_DLL_FLOCK_DISABLE_GEN1 27 27 RX_CFG_DLL_FLOCK_DISABLE_GEN2 28 28 RX_CFG_DLL_FLOCK_DISABLE_GEN3 29 29 RX_CFG_TH_LOOP_GAIN_GEN1 0 3 RX_CFG_TH_LOOP_GAIN_GEN2 4 7 RX_CFG_TH_LOOP_GAIN_GEN3 8 11 RX_DCLK_EN_LUT_ENTRY_LS0_CDR_EN_0 12 12 RX_DCLK_EN_LUT_ENTRY_LS2 13 13 RX_DLL_PWRON_LUT_ENTRY_LS2 17 17 ixPB0_RX_GLB_CTRL_REG8 2 0x16020 0 0 4294967295 ixPB0_RX_GLB_OVRD_REG0 2 0x16030 26 0 4294967295 RX_ADAPT_FOM_OVRD_EN 31 31 RX_ADAPT_FOM_OVRD_VAL 30 30 RX_ADAPT_HLD_OVRD_EN 1 1 RX_ADAPT_HLD_OVRD_VAL 0 0 RX_ADAPT_RST_OVRD_EN 3 3 RX_ADAPT_RST_OVRD_VAL 2 2 RX_AUX_PWRON_OVRD_EN 29 29 RX_AUX_PWRON_OVRD_VAL 28 28 RX_CFG_DCLK_DIV_OVRD_EN 8 8 RX_CFG_DCLK_DIV_OVRD_VAL 6 7 RX_CFG_DLL_FREQ_MODE_OVRD_EN 10 10 RX_CFG_DLL_FREQ_MODE_OVRD_VAL 9 9 RX_CFG_PLLCLK_SEL_OVRD_EN 12 12 RX_CFG_PLLCLK_SEL_OVRD_VAL 11 11 RX_CFG_RCLK_DIV_OVRD_EN 14 14 RX_CFG_RCLK_DIV_OVRD_VAL 13 13 RX_DCLK_EN_OVRD_EN 16 16 RX_DCLK_EN_OVRD_VAL 15 15 RX_DLL_PWRON_OVRD_EN 18 18 RX_DLL_PWRON_OVRD_VAL 17 17 RX_FRONTEND_PWRON_OVRD_EN 20 20 RX_FRONTEND_PWRON_OVRD_VAL 19 19 RX_IDLEDET_PWRON_OVRD_EN 22 22 RX_IDLEDET_PWRON_OVRD_VAL 21 21 RX_TERM_EN_OVRD_EN 24 24 RX_TERM_EN_OVRD_VAL 23 23 ixPB0_RX_GLB_OVRD_REG1 2 0x16034 2 0 4294967295 RX_ADAPT_TRK_OVRD_EN 1 1 RX_ADAPT_TRK_OVRD_VAL 0 0 ixPB0_RX_GLB_SCI_STAT_OVRD_REG0 2 0x16028 24 0 4294967295 IGNR_ELECIDLEDETEN_SCI_UPDT_L0T3 4 4 IGNR_ELECIDLEDETEN_SCI_UPDT_L12T15 7 7 IGNR_ELECIDLEDETEN_SCI_UPDT_L4T7 5 5 IGNR_ELECIDLEDETEN_SCI_UPDT_L8T11 6 6 IGNR_ENABLEFOM_SCI_UPDT_L0T3 12 12 IGNR_ENABLEFOM_SCI_UPDT_L12T15 15 15 IGNR_ENABLEFOM_SCI_UPDT_L4T7 13 13 IGNR_ENABLEFOM_SCI_UPDT_L8T11 14 14 IGNR_REQUESTFOM_SCI_UPDT_L0T3 16 16 IGNR_REQUESTFOM_SCI_UPDT_L12T15 19 19 IGNR_REQUESTFOM_SCI_UPDT_L4T7 17 17 IGNR_REQUESTFOM_SCI_UPDT_L8T11 18 18 IGNR_RESPONSEMODE_SCI_UPDT_L0T3 20 20 IGNR_RESPONSEMODE_SCI_UPDT_L12T15 23 23 IGNR_RESPONSEMODE_SCI_UPDT_L4T7 21 21 IGNR_RESPONSEMODE_SCI_UPDT_L8T11 22 22 IGNR_RXPRESETHINT_SCI_UPDT_L0T3 8 8 IGNR_RXPRESETHINT_SCI_UPDT_L12T15 11 11 IGNR_RXPRESETHINT_SCI_UPDT_L4T7 9 9 IGNR_RXPRESETHINT_SCI_UPDT_L8T11 10 10 IGNR_RXPWR_SCI_UPDT_L0T3 0 0 IGNR_RXPWR_SCI_UPDT_L12T15 3 3 IGNR_RXPWR_SCI_UPDT_L4T7 1 1 IGNR_RXPWR_SCI_UPDT_L8T11 2 2 ixPB0_RX_LANE0_CTRL_REG0 2 0x16440 4 0 4294967295 RX_BACKUP_0 0 7 RX_CFG_OVR_PWRSF_0 13 13 RX_DBG_ANALOG_SEL_0 10 11 RX_TST_BSCAN_EN_0 12 12 ixPB0_RX_LANE0_SCI_STAT_OVRD_REG0 2 0x16448 6 0 4294967295 ELECIDLEDETEN_0 3 3 ENABLEFOM_0 7 7 REQUESTFOM_0 8 8 RESPONSEMODE_0 9 9 RXPRESETHINT_0 4 6 RXPWR_0 0 2 ixPB0_RX_LANE10_CTRL_REG0 2 0x17500 4 0 4294967295 RX_BACKUP_10 0 7 RX_CFG_OVR_PWRSF_10 13 13 RX_DBG_ANALOG_SEL_10 10 11 RX_TST_BSCAN_EN_10 12 12 ixPB0_RX_LANE10_SCI_STAT_OVRD_REG0 2 0x17508 6 0 4294967295 ELECIDLEDETEN_10 3 3 ENABLEFOM_10 7 7 REQUESTFOM_10 8 8 RESPONSEMODE_10 9 9 RXPRESETHINT_10 4 6 RXPWR_10 0 2 ixPB0_RX_LANE11_CTRL_REG0 2 0x17600 4 0 4294967295 RX_BACKUP_11 0 7 RX_CFG_OVR_PWRSF_11 13 13 RX_DBG_ANALOG_SEL_11 10 11 RX_TST_BSCAN_EN_11 12 12 ixPB0_RX_LANE11_SCI_STAT_OVRD_REG0 2 0x17608 6 0 4294967295 ELECIDLEDETEN_11 3 3 ENABLEFOM_11 7 7 REQUESTFOM_11 8 8 RESPONSEMODE_11 9 9 RXPRESETHINT_11 4 6 RXPWR_11 0 2 ixPB0_RX_LANE12_CTRL_REG0 2 0x17840 4 0 4294967295 RX_BACKUP_12 0 7 RX_CFG_OVR_PWRSF_12 13 13 RX_DBG_ANALOG_SEL_12 10 11 RX_TST_BSCAN_EN_12 12 12 ixPB0_RX_LANE12_SCI_STAT_OVRD_REG0 2 0x17848 6 0 4294967295 ELECIDLEDETEN_12 3 3 ENABLEFOM_12 7 7 REQUESTFOM_12 8 8 RESPONSEMODE_12 9 9 RXPRESETHINT_12 4 6 RXPWR_12 0 2 ixPB0_RX_LANE13_CTRL_REG0 2 0x17880 4 0 4294967295 RX_BACKUP_13 0 7 RX_CFG_OVR_PWRSF_13 13 13 RX_DBG_ANALOG_SEL_13 10 11 RX_TST_BSCAN_EN_13 12 12 ixPB0_RX_LANE13_SCI_STAT_OVRD_REG0 2 0x17888 6 0 4294967295 ELECIDLEDETEN_13 3 3 ENABLEFOM_13 7 7 REQUESTFOM_13 8 8 RESPONSEMODE_13 9 9 RXPRESETHINT_13 4 6 RXPWR_13 0 2 ixPB0_RX_LANE14_CTRL_REG0 2 0x17900 4 0 4294967295 RX_BACKUP_14 0 7 RX_CFG_OVR_PWRSF_14 13 13 RX_DBG_ANALOG_SEL_14 10 11 RX_TST_BSCAN_EN_14 12 12 ixPB0_RX_LANE14_SCI_STAT_OVRD_REG0 2 0x17908 6 0 4294967295 ELECIDLEDETEN_14 3 3 ENABLEFOM_14 7 7 REQUESTFOM_14 8 8 RESPONSEMODE_14 9 9 RXPRESETHINT_14 4 6 RXPWR_14 0 2 ixPB0_RX_LANE15_CTRL_REG0 2 0x17a00 4 0 4294967295 RX_BACKUP_15 0 7 RX_CFG_OVR_PWRSF_15 13 13 RX_DBG_ANALOG_SEL_15 10 11 RX_TST_BSCAN_EN_15 12 12 ixPB0_RX_LANE15_SCI_STAT_OVRD_REG0 2 0x17a08 6 0 4294967295 ELECIDLEDETEN_15 3 3 ENABLEFOM_15 7 7 REQUESTFOM_15 8 8 RESPONSEMODE_15 9 9 RXPRESETHINT_15 4 6 RXPWR_15 0 2 ixPB0_RX_LANE1_CTRL_REG0 2 0x16480 4 0 4294967295 RX_BACKUP_1 0 7 RX_CFG_OVR_PWRSF_1 13 13 RX_DBG_ANALOG_SEL_1 10 11 RX_TST_BSCAN_EN_1 12 12 ixPB0_RX_LANE1_SCI_STAT_OVRD_REG0 2 0x16488 6 0 4294967295 ELECIDLEDETEN_1 3 3 ENABLEFOM_1 7 7 REQUESTFOM_1 8 8 RESPONSEMODE_1 9 9 RXPRESETHINT_1 4 6 RXPWR_1 0 2 ixPB0_RX_LANE2_CTRL_REG0 2 0x16500 4 0 4294967295 RX_BACKUP_2 0 7 RX_CFG_OVR_PWRSF_2 13 13 RX_DBG_ANALOG_SEL_2 10 11 RX_TST_BSCAN_EN_2 12 12 ixPB0_RX_LANE2_SCI_STAT_OVRD_REG0 2 0x16508 6 0 4294967295 ELECIDLEDETEN_2 3 3 ENABLEFOM_2 7 7 REQUESTFOM_2 8 8 RESPONSEMODE_2 9 9 RXPRESETHINT_2 4 6 RXPWR_2 0 2 ixPB0_RX_LANE3_CTRL_REG0 2 0x16600 4 0 4294967295 RX_BACKUP_3 0 7 RX_CFG_OVR_PWRSF_3 13 13 RX_DBG_ANALOG_SEL_3 10 11 RX_TST_BSCAN_EN_3 12 12 ixPB0_RX_LANE3_SCI_STAT_OVRD_REG0 2 0x16608 6 0 4294967295 ELECIDLEDETEN_3 3 3 ENABLEFOM_3 7 7 REQUESTFOM_3 8 8 RESPONSEMODE_3 9 9 RXPRESETHINT_3 4 6 RXPWR_3 0 2 ixPB0_RX_LANE4_CTRL_REG0 2 0x16800 4 0 4294967295 RX_BACKUP_4 0 7 RX_CFG_OVR_PWRSF_4 13 13 RX_DBG_ANALOG_SEL_4 10 11 RX_TST_BSCAN_EN_4 12 12 ixPB0_RX_LANE4_SCI_STAT_OVRD_REG0 2 0x16848 6 0 4294967295 ELECIDLEDETEN_4 3 3 ENABLEFOM_4 7 7 REQUESTFOM_4 8 8 RESPONSEMODE_4 9 9 RXPRESETHINT_4 4 6 RXPWR_4 0 2 ixPB0_RX_LANE5_CTRL_REG0 2 0x16880 4 0 4294967295 RX_BACKUP_5 0 7 RX_CFG_OVR_PWRSF_5 13 13 RX_DBG_ANALOG_SEL_5 10 11 RX_TST_BSCAN_EN_5 12 12 ixPB0_RX_LANE5_SCI_STAT_OVRD_REG0 2 0x16888 6 0 4294967295 ELECIDLEDETEN_5 3 3 ENABLEFOM_5 7 7 REQUESTFOM_5 8 8 RESPONSEMODE_5 9 9 RXPRESETHINT_5 4 6 RXPWR_5 0 2 ixPB0_RX_LANE6_CTRL_REG0 2 0x16900 4 0 4294967295 RX_BACKUP_6 0 7 RX_CFG_OVR_PWRSF_6 13 13 RX_DBG_ANALOG_SEL_6 10 11 RX_TST_BSCAN_EN_6 12 12 ixPB0_RX_LANE6_SCI_STAT_OVRD_REG0 2 0x16908 6 0 4294967295 ELECIDLEDETEN_6 3 3 ENABLEFOM_6 7 7 REQUESTFOM_6 8 8 RESPONSEMODE_6 9 9 RXPRESETHINT_6 4 6 RXPWR_6 0 2 ixPB0_RX_LANE7_CTRL_REG0 2 0x16a00 4 0 4294967295 RX_BACKUP_7 0 7 RX_CFG_OVR_PWRSF_7 13 13 RX_DBG_ANALOG_SEL_7 10 11 RX_TST_BSCAN_EN_7 12 12 ixPB0_RX_LANE7_SCI_STAT_OVRD_REG0 2 0x16a08 6 0 4294967295 ELECIDLEDETEN_7 3 3 ENABLEFOM_7 7 7 REQUESTFOM_7 8 8 RESPONSEMODE_7 9 9 RXPRESETHINT_7 4 6 RXPWR_7 0 2 ixPB0_RX_LANE8_CTRL_REG0 2 0x17440 4 0 4294967295 RX_BACKUP_8 0 7 RX_CFG_OVR_PWRSF_8 13 13 RX_DBG_ANALOG_SEL_8 10 11 RX_TST_BSCAN_EN_8 12 12 ixPB0_RX_LANE8_SCI_STAT_OVRD_REG0 2 0x17448 6 0 4294967295 ELECIDLEDETEN_8 3 3 ENABLEFOM_8 7 7 REQUESTFOM_8 8 8 RESPONSEMODE_8 9 9 RXPRESETHINT_8 4 6 RXPWR_8 0 2 ixPB0_RX_LANE9_CTRL_REG0 2 0x17480 4 0 4294967295 RX_BACKUP_9 0 7 RX_CFG_OVR_PWRSF_9 13 13 RX_DBG_ANALOG_SEL_9 10 11 RX_TST_BSCAN_EN_9 12 12 ixPB0_RX_LANE9_SCI_STAT_OVRD_REG0 2 0x17488 6 0 4294967295 ELECIDLEDETEN_9 3 3 ENABLEFOM_9 7 7 REQUESTFOM_9 8 8 RESPONSEMODE_9 9 9 RXPRESETHINT_9 4 6 RXPWR_9 0 2 ixPB0_STRAP_GLB_REG0 2 0x12020 1 0 4294967295 STRAP_DBG_RXDLL_VREG_REF_SEL 15 15 ixPB0_STRAP_PLL_REG0 2 0x12030 0 0 4294967295 ixPB0_STRAP_RX_REG0 2 0x12028 0 0 4294967295 ixPB0_STRAP_RX_REG1 2 0x1202c 0 0 4294967295 ixPB0_STRAP_TX_REG0 2 0x12024 0 0 4294967295 ixPB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0 2 0x18014 32 0 4294967295 ACCEPT_ENTRY_0 0 0 ACCEPT_ENTRY_10 10 10 ACCEPT_ENTRY_11 11 11 ACCEPT_ENTRY_12 12 12 ACCEPT_ENTRY_13 13 13 ACCEPT_ENTRY_14 14 14 ACCEPT_ENTRY_15 15 15 ACCEPT_ENTRY_16 16 16 ACCEPT_ENTRY_17 17 17 ACCEPT_ENTRY_18 18 18 ACCEPT_ENTRY_19 19 19 ACCEPT_ENTRY_1 1 1 ACCEPT_ENTRY_20 20 20 ACCEPT_ENTRY_21 21 21 ACCEPT_ENTRY_22 22 22 ACCEPT_ENTRY_23 23 23 ACCEPT_ENTRY_24 24 24 ACCEPT_ENTRY_25 25 25 ACCEPT_ENTRY_26 26 26 ACCEPT_ENTRY_27 27 27 ACCEPT_ENTRY_28 28 28 ACCEPT_ENTRY_29 29 29 ACCEPT_ENTRY_2 2 2 ACCEPT_ENTRY_30 30 30 ACCEPT_ENTRY_31 31 31 ACCEPT_ENTRY_3 3 3 ACCEPT_ENTRY_4 4 4 ACCEPT_ENTRY_5 5 5 ACCEPT_ENTRY_6 6 6 ACCEPT_ENTRY_7 7 7 ACCEPT_ENTRY_8 8 8 ACCEPT_ENTRY_9 9 9 ixPB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1 2 0x18018 32 0 4294967295 ACCEPT_ENTRY_32 0 0 ACCEPT_ENTRY_33 1 1 ACCEPT_ENTRY_34 2 2 ACCEPT_ENTRY_35 3 3 ACCEPT_ENTRY_36 4 4 ACCEPT_ENTRY_37 5 5 ACCEPT_ENTRY_38 6 6 ACCEPT_ENTRY_39 7 7 ACCEPT_ENTRY_40 8 8 ACCEPT_ENTRY_41 9 9 ACCEPT_ENTRY_42 10 10 ACCEPT_ENTRY_43 11 11 ACCEPT_ENTRY_44 12 12 ACCEPT_ENTRY_45 13 13 ACCEPT_ENTRY_46 14 14 ACCEPT_ENTRY_47 15 15 ACCEPT_ENTRY_48 16 16 ACCEPT_ENTRY_49 17 17 ACCEPT_ENTRY_50 18 18 ACCEPT_ENTRY_51 19 19 ACCEPT_ENTRY_52 20 20 ACCEPT_ENTRY_53 21 21 ACCEPT_ENTRY_54 22 22 ACCEPT_ENTRY_55 23 23 ACCEPT_ENTRY_56 24 24 ACCEPT_ENTRY_57 25 25 ACCEPT_ENTRY_58 26 26 ACCEPT_ENTRY_59 27 27 ACCEPT_ENTRY_60 28 28 ACCEPT_ENTRY_61 29 29 ACCEPT_ENTRY_62 30 30 ACCEPT_ENTRY_63 31 31 ixPB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2 2 0x1801c 32 0 4294967295 ACCEPT_ENTRY_64 0 0 ACCEPT_ENTRY_65 1 1 ACCEPT_ENTRY_66 2 2 ACCEPT_ENTRY_67 3 3 ACCEPT_ENTRY_68 4 4 ACCEPT_ENTRY_69 5 5 ACCEPT_ENTRY_70 6 6 ACCEPT_ENTRY_71 7 7 ACCEPT_ENTRY_72 8 8 ACCEPT_ENTRY_73 9 9 ACCEPT_ENTRY_74 10 10 ACCEPT_ENTRY_75 11 11 ACCEPT_ENTRY_76 12 12 ACCEPT_ENTRY_77 13 13 ACCEPT_ENTRY_78 14 14 ACCEPT_ENTRY_79 15 15 ACCEPT_ENTRY_80 16 16 ACCEPT_ENTRY_81 17 17 ACCEPT_ENTRY_82 18 18 ACCEPT_ENTRY_83 19 19 ACCEPT_ENTRY_84 20 20 ACCEPT_ENTRY_85 21 21 ACCEPT_ENTRY_86 22 22 ACCEPT_ENTRY_87 23 23 ACCEPT_ENTRY_88 24 24 ACCEPT_ENTRY_89 25 25 ACCEPT_ENTRY_90 26 26 ACCEPT_ENTRY_91 27 27 ACCEPT_ENTRY_92 28 28 ACCEPT_ENTRY_93 29 29 ACCEPT_ENTRY_94 30 30 ACCEPT_ENTRY_95 31 31 ixPB0_TX_GLB_COEFF_ACCEPT_TABLE_REG3 2 0x18020 14 0 4294967295 ACCEPT_ENTRY_100 4 4 ACCEPT_ENTRY_101 5 5 ACCEPT_ENTRY_102 6 6 ACCEPT_ENTRY_103 7 7 ACCEPT_ENTRY_104 8 8 ACCEPT_ENTRY_105 9 9 ACCEPT_ENTRY_106 10 10 ACCEPT_ENTRY_107 11 11 ACCEPT_ENTRY_108 12 12 ACCEPT_ENTRY_109 13 13 ACCEPT_ENTRY_96 0 0 ACCEPT_ENTRY_97 1 1 ACCEPT_ENTRY_98 2 2 ACCEPT_ENTRY_99 3 3 ixPB0_TX_GLB_CTRL_REG0 2 0x18000 12 0 4294967295 TX_CFG_RPTR_RST_VAL_GEN1 8 10 TX_CFG_RPTR_RST_VAL_GEN2 11 13 TX_CFG_RPTR_RST_VAL_GEN3 14 16 TX_COEFF_ROUND_DIR_VER 22 22 TX_COEFF_ROUND_EN 21 21 TX_DATA_CLK_GATING 19 19 TX_DCLK_EN_LSX_ALWAYS_ON 23 23 TX_DRV_DATA_ASRT_DLY_VAL 0 2 TX_DRV_DATA_DSRT_DLY_VAL 3 5 TX_FRONTEND_PWRON_IN_OFF 24 24 TX_PRESET_TABLE_BYPASS 20 20 TX_STAGGER_CTRL 17 18 ixPB0_TX_GLB_LANE_SKEW_CTRL 2 0x18004 31 0 4294967295 TX_CFG_GROUPX16_EN_L0T15 30 30 TX_CFG_GROUPX1_EN_0 0 0 TX_CFG_GROUPX1_EN_10 10 10 TX_CFG_GROUPX1_EN_11 11 11 TX_CFG_GROUPX1_EN_12 12 12 TX_CFG_GROUPX1_EN_13 13 13 TX_CFG_GROUPX1_EN_14 14 14 TX_CFG_GROUPX1_EN_15 15 15 TX_CFG_GROUPX1_EN_1 1 1 TX_CFG_GROUPX1_EN_2 2 2 TX_CFG_GROUPX1_EN_3 3 3 TX_CFG_GROUPX1_EN_4 4 4 TX_CFG_GROUPX1_EN_5 5 5 TX_CFG_GROUPX1_EN_6 6 6 TX_CFG_GROUPX1_EN_7 7 7 TX_CFG_GROUPX1_EN_8 8 8 TX_CFG_GROUPX1_EN_9 9 9 TX_CFG_GROUPX2_EN_L0T1 16 16 TX_CFG_GROUPX2_EN_L10T11 21 21 TX_CFG_GROUPX2_EN_L12T13 22 22 TX_CFG_GROUPX2_EN_L14T15 23 23 TX_CFG_GROUPX2_EN_L2T3 17 17 TX_CFG_GROUPX2_EN_L4T5 18 18 TX_CFG_GROUPX2_EN_L6T7 19 19 TX_CFG_GROUPX2_EN_L8T9 20 20 TX_CFG_GROUPX4_EN_L0T3 24 24 TX_CFG_GROUPX4_EN_L12T15 27 27 TX_CFG_GROUPX4_EN_L4T7 25 25 TX_CFG_GROUPX4_EN_L8T11 26 26 TX_CFG_GROUPX8_EN_L0T7 28 28 TX_CFG_GROUPX8_EN_L8T15 29 29 ixPB0_TX_GLB_OVRD_REG0 2 0x18030 12 0 4294967295 TX_CFG_DCLK_DIV_OVRD_EN 3 3 TX_CFG_DCLK_DIV_OVRD_VAL 0 2 TX_CFG_DRV0_EN_GEN1_OVRD_VAL 4 7 TX_CFG_DRV0_EN_OVRD_EN 8 8 TX_CFG_DRV0_TAP_SEL_GEN1_OVRD_VAL 9 12 TX_CFG_DRV0_TAP_SEL_OVRD_EN 13 13 TX_CFG_DRV1_EN_GEN1_OVRD_VAL 14 18 TX_CFG_DRV1_EN_OVRD_EN 19 19 TX_CFG_DRV1_TAP_SEL_GEN1_OVRD_VAL 20 24 TX_CFG_DRV1_TAP_SEL_OVRD_EN 25 25 TX_CFG_DRV2_EN_GEN1_OVRD_VAL 26 29 TX_CFG_DRV2_EN_OVRD_EN 30 30 ixPB0_TX_GLB_OVRD_REG1 2 0x18034 20 0 4294967295 TX_CFG_DRV2_TAP_SEL_GEN1_OVRD_VAL 0 3 TX_CFG_DRV2_TAP_SEL_OVRD_EN 4 4 TX_CFG_DRVX_EN_GEN1_OVRD_VAL 5 5 TX_CFG_DRVX_EN_OVRD_EN 6 6 TX_CFG_DRVX_TAP_SEL_GEN1_OVRD_VAL 7 7 TX_CFG_DRVX_TAP_SEL_OVRD_EN 8 8 TX_CFG_PLLCLK_SEL_OVRD_EN 10 10 TX_CFG_PLLCLK_SEL_OVRD_VAL 9 9 TX_CFG_TCLK_DIV_OVRD_EN 12 12 TX_CFG_TCLK_DIV_OVRD_VAL 11 11 TX_CMDET_EN_OVRD_EN 14 14 TX_CMDET_EN_OVRD_VAL 13 13 TX_DATA_IN_OVRD_EN 25 25 TX_DATA_IN_OVRD_VAL 15 24 TX_RPTR_RSTN_OVRD_EN 27 27 TX_RPTR_RSTN_OVRD_VAL 26 26 TX_RXDET_EN_OVRD_EN 29 29 TX_RXDET_EN_OVRD_VAL 28 28 TX_WPTR_RSTN_OVRD_EN 31 31 TX_WPTR_RSTN_OVRD_VAL 30 30 ixPB0_TX_GLB_OVRD_REG2 2 0x18038 16 0 4294967295 TX_CFG_DRV0_EN_GEN2_OVRD_VAL 12 15 TX_CFG_DRV0_TAP_SEL_GEN2_OVRD_VAL 16 19 TX_CFG_DRV1_EN_GEN2_OVRD_VAL 20 24 TX_CFG_DRV1_TAP_SEL_GEN2_OVRD_VAL 25 29 TX_CFG_GROUPX16_EN_OVRD_EN 11 11 TX_CFG_GROUPX16_EN_OVRD_VAL 10 10 TX_CFG_GROUPX1_EN_OVRD_EN 3 3 TX_CFG_GROUPX1_EN_OVRD_VAL 2 2 TX_CFG_GROUPX2_EN_OVRD_EN 5 5 TX_CFG_GROUPX2_EN_OVRD_VAL 4 4 TX_CFG_GROUPX4_EN_OVRD_EN 7 7 TX_CFG_GROUPX4_EN_OVRD_VAL 6 6 TX_CFG_GROUPX8_EN_OVRD_EN 9 9 TX_CFG_GROUPX8_EN_OVRD_VAL 8 8 TX_WRITE_EN_OVRD_EN 1 1 TX_WRITE_EN_OVRD_VAL 0 0 ixPB0_TX_GLB_OVRD_REG3 2 0x1803c 9 0 4294967295 TX_CFG_DRV0_EN_GEN3_OVRD_VAL 10 13 TX_CFG_DRV0_TAP_SEL_GEN3_OVRD_VAL 14 17 TX_CFG_DRV1_EN_GEN3_OVRD_VAL 18 22 TX_CFG_DRV1_TAP_SEL_GEN3_OVRD_VAL 23 27 TX_CFG_DRV2_EN_GEN2_OVRD_VAL 0 3 TX_CFG_DRV2_EN_GEN3_OVRD_VAL 28 31 TX_CFG_DRV2_TAP_SEL_GEN2_OVRD_VAL 4 7 TX_CFG_DRVX_EN_GEN2_OVRD_VAL 8 8 TX_CFG_DRVX_TAP_SEL_GEN2_OVRD_VAL 9 9 ixPB0_TX_GLB_OVRD_REG4 2 0x18040 3 0 4294967295 TX_CFG_DRV2_TAP_SEL_GEN3_OVRD_VAL 0 3 TX_CFG_DRVX_EN_GEN3_OVRD_VAL 4 4 TX_CFG_DRVX_TAP_SEL_GEN3_OVRD_VAL 5 5 ixPB0_TX_GLB_SCI_STAT_OVRD_REG0 2 0x18010 16 0 4294967295 IGNR_COEFFICIENTID_SCI_UPDT_L0T3 8 8 IGNR_COEFFICIENTID_SCI_UPDT_L12T15 11 11 IGNR_COEFFICIENTID_SCI_UPDT_L4T7 9 9 IGNR_COEFFICIENTID_SCI_UPDT_L8T11 10 10 IGNR_COEFFICIENT_SCI_UPDT_L0T3 12 12 IGNR_COEFFICIENT_SCI_UPDT_L12T15 15 15 IGNR_COEFFICIENT_SCI_UPDT_L4T7 13 13 IGNR_COEFFICIENT_SCI_UPDT_L8T11 14 14 IGNR_INCOHERENTCK_SCI_UPDT_L0T3 4 4 IGNR_INCOHERENTCK_SCI_UPDT_L12T15 7 7 IGNR_INCOHERENTCK_SCI_UPDT_L4T7 5 5 IGNR_INCOHERENTCK_SCI_UPDT_L8T11 6 6 IGNR_TXPWR_SCI_UPDT_L0T3 0 0 IGNR_TXPWR_SCI_UPDT_L12T15 3 3 IGNR_TXPWR_SCI_UPDT_L4T7 1 1 IGNR_TXPWR_SCI_UPDT_L8T11 2 2 ixPB0_TX_LANE0_CTRL_REG0 2 0x18440 4 0 4294967295 TX_CFG_DISPCLK_MODE_0 0 0 TX_CFG_INV_DATA_0 1 1 TX_CFG_SWING_BOOST_EN_0 2 2 TX_DBG_PRBS_EN_0 3 3 ixPB0_TX_LANE0_OVRD_REG0 2 0x18444 8 0 4294967295 TX_DCLK_EN_OVRD_EN_0 1 1 TX_DCLK_EN_OVRD_VAL_0 0 0 TX_DRV_DATA_EN_OVRD_EN_0 3 3 TX_DRV_DATA_EN_OVRD_VAL_0 2 2 TX_DRV_PWRON_OVRD_EN_0 5 5 TX_DRV_PWRON_OVRD_VAL_0 4 4 TX_FRONTEND_PWRON_OVRD_EN_0 7 7 TX_FRONTEND_PWRON_OVRD_VAL_0 6 6 ixPB0_TX_LANE0_SCI_STAT_OVRD_REG0 2 0x18448 6 0 4294967295 COEFFICIENT_0 10 15 COEFFICIENTID_0 8 9 DEEMPH_0 7 7 INCOHERENTCK_0 3 3 TXMARG_0 4 6 TXPWR_0 0 2 ixPB0_TX_LANE10_CTRL_REG0 2 0x19500 4 0 4294967295 TX_CFG_DISPCLK_MODE_10 0 0 TX_CFG_INV_DATA_10 1 1 TX_CFG_SWING_BOOST_EN_10 2 2 TX_DBG_PRBS_EN_10 3 3 ixPB0_TX_LANE10_OVRD_REG0 2 0x19504 8 0 4294967295 TX_DCLK_EN_OVRD_EN_10 1 1 TX_DCLK_EN_OVRD_VAL_10 0 0 TX_DRV_DATA_EN_OVRD_EN_10 3 3 TX_DRV_DATA_EN_OVRD_VAL_10 2 2 TX_DRV_PWRON_OVRD_EN_10 5 5 TX_DRV_PWRON_OVRD_VAL_10 4 4 TX_FRONTEND_PWRON_OVRD_EN_10 7 7 TX_FRONTEND_PWRON_OVRD_VAL_10 6 6 ixPB0_TX_LANE10_SCI_STAT_OVRD_REG0 2 0x19508 6 0 4294967295 COEFFICIENT_10 10 15 COEFFICIENTID_10 8 9 DEEMPH_10 7 7 INCOHERENTCK_10 3 3 TXMARG_10 4 6 TXPWR_10 0 2 ixPB0_TX_LANE11_CTRL_REG0 2 0x19600 4 0 4294967295 TX_CFG_DISPCLK_MODE_11 0 0 TX_CFG_INV_DATA_11 1 1 TX_CFG_SWING_BOOST_EN_11 2 2 TX_DBG_PRBS_EN_11 3 3 ixPB0_TX_LANE11_OVRD_REG0 2 0x19604 8 0 4294967295 TX_DCLK_EN_OVRD_EN_11 1 1 TX_DCLK_EN_OVRD_VAL_11 0 0 TX_DRV_DATA_EN_OVRD_EN_11 3 3 TX_DRV_DATA_EN_OVRD_VAL_11 2 2 TX_DRV_PWRON_OVRD_EN_11 5 5 TX_DRV_PWRON_OVRD_VAL_11 4 4 TX_FRONTEND_PWRON_OVRD_EN_11 7 7 TX_FRONTEND_PWRON_OVRD_VAL_11 6 6 ixPB0_TX_LANE11_SCI_STAT_OVRD_REG0 2 0x19608 6 0 4294967295 COEFFICIENT_11 10 15 COEFFICIENTID_11 8 9 DEEMPH_11 7 7 INCOHERENTCK_11 3 3 TXMARG_11 4 6 TXPWR_11 0 2 ixPB0_TX_LANE12_CTRL_REG0 2 0x19840 4 0 4294967295 TX_CFG_DISPCLK_MODE_12 0 0 TX_CFG_INV_DATA_12 1 1 TX_CFG_SWING_BOOST_EN_12 2 2 TX_DBG_PRBS_EN_12 3 3 ixPB0_TX_LANE12_OVRD_REG0 2 0x19844 8 0 4294967295 TX_DCLK_EN_OVRD_EN_12 1 1 TX_DCLK_EN_OVRD_VAL_12 0 0 TX_DRV_DATA_EN_OVRD_EN_12 3 3 TX_DRV_DATA_EN_OVRD_VAL_12 2 2 TX_DRV_PWRON_OVRD_EN_12 5 5 TX_DRV_PWRON_OVRD_VAL_12 4 4 TX_FRONTEND_PWRON_OVRD_EN_12 7 7 TX_FRONTEND_PWRON_OVRD_VAL_12 6 6 ixPB0_TX_LANE12_SCI_STAT_OVRD_REG0 2 0x19848 6 0 4294967295 COEFFICIENT_12 10 15 COEFFICIENTID_12 8 9 DEEMPH_12 7 7 INCOHERENTCK_12 3 3 TXMARG_12 4 6 TXPWR_12 0 2 ixPB0_TX_LANE13_CTRL_REG0 2 0x19880 4 0 4294967295 TX_CFG_DISPCLK_MODE_13 0 0 TX_CFG_INV_DATA_13 1 1 TX_CFG_SWING_BOOST_EN_13 2 2 TX_DBG_PRBS_EN_13 3 3 ixPB0_TX_LANE13_OVRD_REG0 2 0x19884 8 0 4294967295 TX_DCLK_EN_OVRD_EN_13 1 1 TX_DCLK_EN_OVRD_VAL_13 0 0 TX_DRV_DATA_EN_OVRD_EN_13 3 3 TX_DRV_DATA_EN_OVRD_VAL_13 2 2 TX_DRV_PWRON_OVRD_EN_13 5 5 TX_DRV_PWRON_OVRD_VAL_13 4 4 TX_FRONTEND_PWRON_OVRD_EN_13 7 7 TX_FRONTEND_PWRON_OVRD_VAL_13 6 6 ixPB0_TX_LANE13_SCI_STAT_OVRD_REG0 2 0x19888 6 0 4294967295 COEFFICIENT_13 10 15 COEFFICIENTID_13 8 9 DEEMPH_13 7 7 INCOHERENTCK_13 3 3 TXMARG_13 4 6 TXPWR_13 0 2 ixPB0_TX_LANE14_CTRL_REG0 2 0x19900 4 0 4294967295 TX_CFG_DISPCLK_MODE_14 0 0 TX_CFG_INV_DATA_14 1 1 TX_CFG_SWING_BOOST_EN_14 2 2 TX_DBG_PRBS_EN_14 3 3 ixPB0_TX_LANE14_OVRD_REG0 2 0x19904 8 0 4294967295 TX_DCLK_EN_OVRD_EN_14 1 1 TX_DCLK_EN_OVRD_VAL_14 0 0 TX_DRV_DATA_EN_OVRD_EN_14 3 3 TX_DRV_DATA_EN_OVRD_VAL_14 2 2 TX_DRV_PWRON_OVRD_EN_14 5 5 TX_DRV_PWRON_OVRD_VAL_14 4 4 TX_FRONTEND_PWRON_OVRD_EN_14 7 7 TX_FRONTEND_PWRON_OVRD_VAL_14 6 6 ixPB0_TX_LANE14_SCI_STAT_OVRD_REG0 2 0x19908 6 0 4294967295 COEFFICIENT_14 10 15 COEFFICIENTID_14 8 9 DEEMPH_14 7 7 INCOHERENTCK_14 3 3 TXMARG_14 4 6 TXPWR_14 0 2 ixPB0_TX_LANE15_CTRL_REG0 2 0x19a00 4 0 4294967295 TX_CFG_DISPCLK_MODE_15 0 0 TX_CFG_INV_DATA_15 1 1 TX_CFG_SWING_BOOST_EN_15 2 2 TX_DBG_PRBS_EN_15 3 3 ixPB0_TX_LANE15_OVRD_REG0 2 0x19a04 8 0 4294967295 TX_DCLK_EN_OVRD_EN_15 1 1 TX_DCLK_EN_OVRD_VAL_15 0 0 TX_DRV_DATA_EN_OVRD_EN_15 3 3 TX_DRV_DATA_EN_OVRD_VAL_15 2 2 TX_DRV_PWRON_OVRD_EN_15 5 5 TX_DRV_PWRON_OVRD_VAL_15 4 4 TX_FRONTEND_PWRON_OVRD_EN_15 7 7 TX_FRONTEND_PWRON_OVRD_VAL_15 6 6 ixPB0_TX_LANE15_SCI_STAT_OVRD_REG0 2 0x19a08 6 0 4294967295 COEFFICIENT_15 10 15 COEFFICIENTID_15 8 9 DEEMPH_15 7 7 INCOHERENTCK_15 3 3 TXMARG_15 4 6 TXPWR_15 0 2 ixPB0_TX_LANE1_CTRL_REG0 2 0x18480 4 0 4294967295 TX_CFG_DISPCLK_MODE_1 0 0 TX_CFG_INV_DATA_1 1 1 TX_CFG_SWING_BOOST_EN_1 2 2 TX_DBG_PRBS_EN_1 3 3 ixPB0_TX_LANE1_OVRD_REG0 2 0x18484 8 0 4294967295 TX_DCLK_EN_OVRD_EN_1 1 1 TX_DCLK_EN_OVRD_VAL_1 0 0 TX_DRV_DATA_EN_OVRD_EN_1 3 3 TX_DRV_DATA_EN_OVRD_VAL_1 2 2 TX_DRV_PWRON_OVRD_EN_1 5 5 TX_DRV_PWRON_OVRD_VAL_1 4 4 TX_FRONTEND_PWRON_OVRD_EN_1 7 7 TX_FRONTEND_PWRON_OVRD_VAL_1 6 6 ixPB0_TX_LANE1_SCI_STAT_OVRD_REG0 2 0x18488 6 0 4294967295 COEFFICIENT_1 10 15 COEFFICIENTID_1 8 9 DEEMPH_1 7 7 INCOHERENTCK_1 3 3 TXMARG_1 4 6 TXPWR_1 0 2 ixPB0_TX_LANE2_CTRL_REG0 2 0x18500 4 0 4294967295 TX_CFG_DISPCLK_MODE_2 0 0 TX_CFG_INV_DATA_2 1 1 TX_CFG_SWING_BOOST_EN_2 2 2 TX_DBG_PRBS_EN_2 3 3 ixPB0_TX_LANE2_OVRD_REG0 2 0x18504 8 0 4294967295 TX_DCLK_EN_OVRD_EN_2 1 1 TX_DCLK_EN_OVRD_VAL_2 0 0 TX_DRV_DATA_EN_OVRD_EN_2 3 3 TX_DRV_DATA_EN_OVRD_VAL_2 2 2 TX_DRV_PWRON_OVRD_EN_2 5 5 TX_DRV_PWRON_OVRD_VAL_2 4 4 TX_FRONTEND_PWRON_OVRD_EN_2 7 7 TX_FRONTEND_PWRON_OVRD_VAL_2 6 6 ixPB0_TX_LANE2_SCI_STAT_OVRD_REG0 2 0x18508 6 0 4294967295 COEFFICIENT_2 10 15 COEFFICIENTID_2 8 9 DEEMPH_2 7 7 INCOHERENTCK_2 3 3 TXMARG_2 4 6 TXPWR_2 0 2 ixPB0_TX_LANE3_CTRL_REG0 2 0x18600 4 0 4294967295 TX_CFG_DISPCLK_MODE_3 0 0 TX_CFG_INV_DATA_3 1 1 TX_CFG_SWING_BOOST_EN_3 2 2 TX_DBG_PRBS_EN_3 3 3 ixPB0_TX_LANE3_OVRD_REG0 2 0x18604 8 0 4294967295 TX_DCLK_EN_OVRD_EN_3 1 1 TX_DCLK_EN_OVRD_VAL_3 0 0 TX_DRV_DATA_EN_OVRD_EN_3 3 3 TX_DRV_DATA_EN_OVRD_VAL_3 2 2 TX_DRV_PWRON_OVRD_EN_3 5 5 TX_DRV_PWRON_OVRD_VAL_3 4 4 TX_FRONTEND_PWRON_OVRD_EN_3 7 7 TX_FRONTEND_PWRON_OVRD_VAL_3 6 6 ixPB0_TX_LANE3_SCI_STAT_OVRD_REG0 2 0x18608 6 0 4294967295 COEFFICIENT_3 10 15 COEFFICIENTID_3 8 9 DEEMPH_3 7 7 INCOHERENTCK_3 3 3 TXMARG_3 4 6 TXPWR_3 0 2 ixPB0_TX_LANE4_CTRL_REG0 2 0x18840 4 0 4294967295 TX_CFG_DISPCLK_MODE_4 0 0 TX_CFG_INV_DATA_4 1 1 TX_CFG_SWING_BOOST_EN_4 2 2 TX_DBG_PRBS_EN_4 3 3 ixPB0_TX_LANE4_OVRD_REG0 2 0x18844 8 0 4294967295 TX_DCLK_EN_OVRD_EN_4 1 1 TX_DCLK_EN_OVRD_VAL_4 0 0 TX_DRV_DATA_EN_OVRD_EN_4 3 3 TX_DRV_DATA_EN_OVRD_VAL_4 2 2 TX_DRV_PWRON_OVRD_EN_4 5 5 TX_DRV_PWRON_OVRD_VAL_4 4 4 TX_FRONTEND_PWRON_OVRD_EN_4 7 7 TX_FRONTEND_PWRON_OVRD_VAL_4 6 6 ixPB0_TX_LANE4_SCI_STAT_OVRD_REG0 2 0x18848 6 0 4294967295 COEFFICIENT_4 10 15 COEFFICIENTID_4 8 9 DEEMPH_4 7 7 INCOHERENTCK_4 3 3 TXMARG_4 4 6 TXPWR_4 0 2 ixPB0_TX_LANE5_CTRL_REG0 2 0x18880 4 0 4294967295 TX_CFG_DISPCLK_MODE_5 0 0 TX_CFG_INV_DATA_5 1 1 TX_CFG_SWING_BOOST_EN_5 2 2 TX_DBG_PRBS_EN_5 3 3 ixPB0_TX_LANE5_OVRD_REG0 2 0x18884 8 0 4294967295 TX_DCLK_EN_OVRD_EN_5 1 1 TX_DCLK_EN_OVRD_VAL_5 0 0 TX_DRV_DATA_EN_OVRD_EN_5 3 3 TX_DRV_DATA_EN_OVRD_VAL_5 2 2 TX_DRV_PWRON_OVRD_EN_5 5 5 TX_DRV_PWRON_OVRD_VAL_5 4 4 TX_FRONTEND_PWRON_OVRD_EN_5 7 7 TX_FRONTEND_PWRON_OVRD_VAL_5 6 6 ixPB0_TX_LANE5_SCI_STAT_OVRD_REG0 2 0x18888 6 0 4294967295 COEFFICIENT_5 10 15 COEFFICIENTID_5 8 9 DEEMPH_5 7 7 INCOHERENTCK_5 3 3 TXMARG_5 4 6 TXPWR_5 0 2 ixPB0_TX_LANE6_CTRL_REG0 2 0x18900 4 0 4294967295 TX_CFG_DISPCLK_MODE_6 0 0 TX_CFG_INV_DATA_6 1 1 TX_CFG_SWING_BOOST_EN_6 2 2 TX_DBG_PRBS_EN_6 3 3 ixPB0_TX_LANE6_OVRD_REG0 2 0x18904 8 0 4294967295 TX_DCLK_EN_OVRD_EN_6 1 1 TX_DCLK_EN_OVRD_VAL_6 0 0 TX_DRV_DATA_EN_OVRD_EN_6 3 3 TX_DRV_DATA_EN_OVRD_VAL_6 2 2 TX_DRV_PWRON_OVRD_EN_6 5 5 TX_DRV_PWRON_OVRD_VAL_6 4 4 TX_FRONTEND_PWRON_OVRD_EN_6 7 7 TX_FRONTEND_PWRON_OVRD_VAL_6 6 6 ixPB0_TX_LANE6_SCI_STAT_OVRD_REG0 2 0x18908 6 0 4294967295 COEFFICIENT_6 10 15 COEFFICIENTID_6 8 9 DEEMPH_6 7 7 INCOHERENTCK_6 3 3 TXMARG_6 4 6 TXPWR_6 0 2 ixPB0_TX_LANE7_CTRL_REG0 2 0x18a00 4 0 4294967295 TX_CFG_DISPCLK_MODE_7 0 0 TX_CFG_INV_DATA_7 1 1 TX_CFG_SWING_BOOST_EN_7 2 2 TX_DBG_PRBS_EN_7 3 3 ixPB0_TX_LANE7_OVRD_REG0 2 0x18a04 8 0 4294967295 TX_DCLK_EN_OVRD_EN_7 1 1 TX_DCLK_EN_OVRD_VAL_7 0 0 TX_DRV_DATA_EN_OVRD_EN_7 3 3 TX_DRV_DATA_EN_OVRD_VAL_7 2 2 TX_DRV_PWRON_OVRD_EN_7 5 5 TX_DRV_PWRON_OVRD_VAL_7 4 4 TX_FRONTEND_PWRON_OVRD_EN_7 7 7 TX_FRONTEND_PWRON_OVRD_VAL_7 6 6 ixPB0_TX_LANE7_SCI_STAT_OVRD_REG0 2 0x18a08 6 0 4294967295 COEFFICIENT_7 10 15 COEFFICIENTID_7 8 9 DEEMPH_7 7 7 INCOHERENTCK_7 3 3 TXMARG_7 4 6 TXPWR_7 0 2 ixPB0_TX_LANE8_CTRL_REG0 2 0x19440 4 0 4294967295 TX_CFG_DISPCLK_MODE_8 0 0 TX_CFG_INV_DATA_8 1 1 TX_CFG_SWING_BOOST_EN_8 2 2 TX_DBG_PRBS_EN_8 3 3 ixPB0_TX_LANE8_OVRD_REG0 2 0x19444 8 0 4294967295 TX_DCLK_EN_OVRD_EN_8 1 1 TX_DCLK_EN_OVRD_VAL_8 0 0 TX_DRV_DATA_EN_OVRD_EN_8 3 3 TX_DRV_DATA_EN_OVRD_VAL_8 2 2 TX_DRV_PWRON_OVRD_EN_8 5 5 TX_DRV_PWRON_OVRD_VAL_8 4 4 TX_FRONTEND_PWRON_OVRD_EN_8 7 7 TX_FRONTEND_PWRON_OVRD_VAL_8 6 6 ixPB0_TX_LANE8_SCI_STAT_OVRD_REG0 2 0x19448 6 0 4294967295 COEFFICIENT_8 10 15 COEFFICIENTID_8 8 9 DEEMPH_8 7 7 INCOHERENTCK_8 3 3 TXMARG_8 4 6 TXPWR_8 0 2 ixPB0_TX_LANE9_CTRL_REG0 2 0x19480 4 0 4294967295 TX_CFG_DISPCLK_MODE_9 0 0 TX_CFG_INV_DATA_9 1 1 TX_CFG_SWING_BOOST_EN_9 2 2 TX_DBG_PRBS_EN_9 3 3 ixPB0_TX_LANE9_OVRD_REG0 2 0x19484 8 0 4294967295 TX_DCLK_EN_OVRD_EN_9 1 1 TX_DCLK_EN_OVRD_VAL_9 0 0 TX_DRV_DATA_EN_OVRD_EN_9 3 3 TX_DRV_DATA_EN_OVRD_VAL_9 2 2 TX_DRV_PWRON_OVRD_EN_9 5 5 TX_DRV_PWRON_OVRD_VAL_9 4 4 TX_FRONTEND_PWRON_OVRD_EN_9 7 7 TX_FRONTEND_PWRON_OVRD_VAL_9 6 6 ixPB0_TX_LANE9_SCI_STAT_OVRD_REG0 2 0x19488 6 0 4294967295 COEFFICIENT_9 10 15 COEFFICIENTID_9 8 9 DEEMPH_9 7 7 INCOHERENTCK_9 3 3 TXMARG_9 4 6 TXPWR_9 0 2 ixPB1_DFT_DEBUG_CTRL_REG0 2 0x1300c 2 0 4294967295 DFT_PHY_DEBUG_EN 0 0 DFT_PHY_DEBUG_MODE 1 5 ixPB1_DFT_JIT_INJ_REG0 2 0x13000 5 0 4294967295 DFT_CLK_PER_STEP 8 11 DFT_DECR_SWP_EN 23 23 DFT_INCR_SWP_EN 22 22 DFT_NUM_STEPS 0 4 DFT_RECOVERY_TIME 24 31 ixPB1_DFT_JIT_INJ_REG1 2 0x13004 3 0 4294967295 DFT_BLOCK_EN 16 16 DFT_BYPASS_EN 8 8 DFT_BYPASS_VALUE 0 7 ixPB1_DFT_JIT_INJ_REG2 2 0x13008 1 0 4294967295 DFT_LANE_EN 0 15 ixPB1_GLB_CTRL_REG0 2 0x10004 8 0 4294967295 BACKUP 0 15 CFG_IDLEDET_TH 16 17 DBG_RX2TXBYP_SEL 20 22 DBG_RXFEBYP_EN 23 23 DBG_RXPRBS_CLR 24 24 DBG_RXTOGGLE_EN 25 25 DBG_TX2RXLBACK_EN 26 26 TXCFG_CMGOOD_RANGE 30 31 ixPB1_GLB_CTRL_REG1 2 0x10008 10 0 4294967295 PLL_CFG_DISPCLK_DIV 31 31 RXDBG_CDR_FR_BYP_EN 0 0 RXDBG_CDR_FR_BYP_VAL 1 6 RXDBG_CDR_PH_BYP_EN 7 7 RXDBG_CDR_PH_BYP_VAL 8 13 RXDBG_D0TH_BYP_EN 14 14 RXDBG_D0TH_BYP_VAL 15 21 RXDBG_D1TH_BYP_EN 22 22 RXDBG_D1TH_BYP_VAL 23 29 TST_LOSPDTST_EN 30 30 ixPB1_GLB_CTRL_REG2 2 0x1000c 8 0 4294967295 RXDBG_D2TH_BYP_EN 0 0 RXDBG_D2TH_BYP_VAL 1 7 RXDBG_D3TH_BYP_EN 8 8 RXDBG_D3TH_BYP_VAL 9 15 RXDBG_DXTH_BYP_EN 16 16 RXDBG_DXTH_BYP_VAL 17 23 RXDBG_ETH_BYP_EN 24 24 RXDBG_ETH_BYP_VAL 25 31 ixPB1_GLB_CTRL_REG3 2 0x10010 14 0 4294967295 BG_CFG_LC_REG_VREF0_SEL 5 6 BG_CFG_LC_REG_VREF1_SEL 7 8 BG_CFG_RO_REG_VREF_SEL 9 10 BG_DBG_ANALOG_SEL 14 16 BG_DBG_IREFBYP_EN 12 12 BG_DBG_VREFBYP_EN 11 11 DBG_DLL_CLK_SEL 18 20 DBG_RXLEQ_DCATTN_BYP_OVR_DISABLE 31 31 DBG_RXPI_OFFSET_BYP_EN 22 22 DBG_RXPI_OFFSET_BYP_VAL 23 26 DBG_RXSWAPDX_BYP_EN 27 27 DBG_RXSWAPDX_BYP_VAL 28 30 PLL_DISPCLK_CMOS_SEL 21 21 RXDBG_SEL 0 4 ixPB1_GLB_CTRL_REG4 2 0x10014 7 0 4294967295 DBG_RXAPU_EXEC 22 25 DBG_RXAPU_INST 0 15 DBG_RXDFEMUX_BYP_EN 18 18 DBG_RXDFEMUX_BYP_VAL 16 17 DBG_RXDLL_VREG_REF_SEL 26 26 DBG_RXRDATA_GATING_DISABLE 28 28 PWRGOOD_OVRD 27 27 ixPB1_GLB_CTRL_REG5 2 0x10018 1 0 4294967295 DBG_RXAPU_MODE 0 7 ixPB1_GLB_OVRD_REG0 2 0x10030 2 0 4294967295 TXPDTERM_VAL_OVRD_VAL 0 15 TXPUTERM_VAL_OVRD_VAL 16 31 ixPB1_GLB_OVRD_REG1 2 0x10034 6 0 4294967295 RXTERM_VAL_OVRD_EN 15 15 RXTERM_VAL_OVRD_VAL 16 31 TST_LOSPDTST_RST_OVRD_EN 2 2 TST_LOSPDTST_RST_OVRD_VAL 3 3 TXPDTERM_VAL_OVRD_EN 0 0 TXPUTERM_VAL_OVRD_EN 1 1 ixPB1_GLB_OVRD_REG2 2 0x10038 2 0 4294967295 BG_PWRON_OVRD_EN 0 0 BG_PWRON_OVRD_VAL 1 1 ixPB1_GLB_SCI_STAT_OVRD_REG0 2 0x1001c 9 0 4294967295 IGNR_ALL_SCI_UPDT_L0T3 0 0 IGNR_ALL_SCI_UPDT_L12T15 3 3 IGNR_ALL_SCI_UPDT_L4T7 1 1 IGNR_ALL_SCI_UPDT_L8T11 2 2 IGNR_IMPCAL_ACTIVE_SCI_UPDT 4 4 IMPCAL_ACTIVE 20 20 RXIMP 16 19 TXNIMP 8 11 TXPIMP 12 15 ixPB1_GLB_SCI_STAT_OVRD_REG1 2 0x10020 15 0 4294967295 DLL_LOCK_0 12 12 DLL_LOCK_1 13 13 DLL_LOCK_2 14 14 DLL_LOCK_3 15 15 FREQDIV_0 18 19 FREQDIV_1 22 23 FREQDIV_2 26 27 FREQDIV_3 30 31 IGNR_DLL_LOCK_SCI_UPDT_L0T3 2 2 IGNR_FREQDIV_SCI_UPDT_L0T3 1 1 IGNR_MODE_SCI_UPDT_L0T3 0 0 MODE_0 16 17 MODE_1 20 21 MODE_2 24 25 MODE_3 28 29 ixPB1_GLB_SCI_STAT_OVRD_REG2 2 0x10024 15 0 4294967295 DLL_LOCK_4 12 12 DLL_LOCK_5 13 13 DLL_LOCK_6 14 14 DLL_LOCK_7 15 15 FREQDIV_4 18 19 FREQDIV_5 22 23 FREQDIV_6 26 27 FREQDIV_7 30 31 IGNR_DLL_LOCK_SCI_UPDT_L4T7 2 2 IGNR_FREQDIV_SCI_UPDT_L4T7 1 1 IGNR_MODE_SCI_UPDT_L4T7 0 0 MODE_4 16 17 MODE_5 20 21 MODE_6 24 25 MODE_7 28 29 ixPB1_GLB_SCI_STAT_OVRD_REG3 2 0x10028 15 0 4294967295 DLL_LOCK_10 14 14 DLL_LOCK_11 15 15 DLL_LOCK_8 12 12 DLL_LOCK_9 13 13 FREQDIV_10 26 27 FREQDIV_11 30 31 FREQDIV_8 18 19 FREQDIV_9 22 23 IGNR_DLL_LOCK_SCI_UPDT_L8T11 2 2 IGNR_FREQDIV_SCI_UPDT_L8T11 1 1 IGNR_MODE_SCI_UPDT_L8T11 0 0 MODE_10 24 25 MODE_11 28 29 MODE_8 16 17 MODE_9 20 21 ixPB1_GLB_SCI_STAT_OVRD_REG4 2 0x1002c 15 0 4294967295 DLL_LOCK_12 12 12 DLL_LOCK_13 13 13 DLL_LOCK_14 14 14 DLL_LOCK_15 15 15 FREQDIV_12 18 19 FREQDIV_13 22 23 FREQDIV_14 26 27 FREQDIV_15 30 31 IGNR_DLL_LOCK_SCI_UPDT_L12T15 2 2 IGNR_FREQDIV_SCI_UPDT_L12T15 1 1 IGNR_MODE_SCI_UPDT_L12T15 0 0 MODE_12 16 17 MODE_13 20 21 MODE_14 24 25 MODE_15 28 29 ixPB1_HW_DEBUG 2 0x12004 32 0 4294967295 PB1_HW_00_DEBUG 0 0 PB1_HW_01_DEBUG 1 1 PB1_HW_02_DEBUG 2 2 PB1_HW_03_DEBUG 3 3 PB1_HW_04_DEBUG 4 4 PB1_HW_05_DEBUG 5 5 PB1_HW_06_DEBUG 6 6 PB1_HW_07_DEBUG 7 7 PB1_HW_08_DEBUG 8 8 PB1_HW_09_DEBUG 9 9 PB1_HW_10_DEBUG 10 10 PB1_HW_11_DEBUG 11 11 PB1_HW_12_DEBUG 12 12 PB1_HW_13_DEBUG 13 13 PB1_HW_14_DEBUG 14 14 PB1_HW_15_DEBUG 15 15 PB1_HW_16_DEBUG 16 16 PB1_HW_17_DEBUG 17 17 PB1_HW_18_DEBUG 18 18 PB1_HW_19_DEBUG 19 19 PB1_HW_20_DEBUG 20 20 PB1_HW_21_DEBUG 21 21 PB1_HW_22_DEBUG 22 22 PB1_HW_23_DEBUG 23 23 PB1_HW_24_DEBUG 24 24 PB1_HW_25_DEBUG 25 25 PB1_HW_26_DEBUG 26 26 PB1_HW_27_DEBUG 27 27 PB1_HW_28_DEBUG 28 28 PB1_HW_29_DEBUG 29 29 PB1_HW_30_DEBUG 30 30 PB1_HW_31_DEBUG 31 31 ixPB1_PIF_CNTL 2 0x10 20 0 4294967295 DA_FIFO_RESET_0 1 1 DA_FIFO_RESET_1 5 5 DA_FIFO_RESET_2 9 9 DA_FIFO_RESET_3 13 13 DIVINIT_MODE 8 8 EI_CYCLE_OFF_TIME 20 22 EI_DET_CYCLE_MODE 4 4 EXIT_L0S_INIT_DIS 23 23 EXTEND_WAIT_FOR_RAMPUP 28 28 IGNORE_TxDataValid_EP_DIS 29 29 LS2_EXIT_TIME 17 19 PHYCMD_CR_EN_MODE 3 3 PHY_CR_EN_MODE 2 2 PLL_BINDING_ENABLE 10 10 RXDETECT_FIFO_RESET_MODE 6 6 RXDETECT_TX_PWR_MODE 7 7 RXEN_GATER 24 27 SC_CALIB_DONE_CNTL 11 11 SERIAL_CFG_ENABLE 0 0 TXGND_TIME 16 16 ixPB1_PIF_CNTL2 2 0x14 19 0 4294967295 RXDETECT_OVERRIDE_EN 7 7 RXDETECT_OVERRIDE_VAL_0 8 8 RXDETECT_OVERRIDE_VAL_10 18 18 RXDETECT_OVERRIDE_VAL_11 19 19 RXDETECT_OVERRIDE_VAL_12 20 20 RXDETECT_OVERRIDE_VAL_13 21 21 RXDETECT_OVERRIDE_VAL_14 22 22 RXDETECT_OVERRIDE_VAL_15 23 23 RXDETECT_OVERRIDE_VAL_1 9 9 RXDETECT_OVERRIDE_VAL_2 10 10 RXDETECT_OVERRIDE_VAL_3 11 11 RXDETECT_OVERRIDE_VAL_4 12 12 RXDETECT_OVERRIDE_VAL_5 13 13 RXDETECT_OVERRIDE_VAL_6 14 14 RXDETECT_OVERRIDE_VAL_7 15 15 RXDETECT_OVERRIDE_VAL_8 16 16 RXDETECT_OVERRIDE_VAL_9 17 17 RXDETECT_SAMPL_TIME 1 2 RXPHYSTATUS_DELAY 24 26 ixPB1_PIF_HW_DEBUG 2 0x2 16 0 4294967295 PB1_PIF_HW_00_DEBUG 0 0 PB1_PIF_HW_01_DEBUG 1 1 PB1_PIF_HW_02_DEBUG 2 2 PB1_PIF_HW_03_DEBUG 3 3 PB1_PIF_HW_04_DEBUG 4 4 PB1_PIF_HW_05_DEBUG 5 5 PB1_PIF_HW_06_DEBUG 6 6 PB1_PIF_HW_07_DEBUG 7 7 PB1_PIF_HW_08_DEBUG 8 8 PB1_PIF_HW_09_DEBUG 9 9 PB1_PIF_HW_10_DEBUG 10 10 PB1_PIF_HW_11_DEBUG 11 11 PB1_PIF_HW_12_DEBUG 12 12 PB1_PIF_HW_13_DEBUG 13 13 PB1_PIF_HW_14_DEBUG 14 14 PB1_PIF_HW_15_DEBUG 15 15 ixPB1_PIF_PAIRING 2 0x11 16 0 4294967295 MULTI_PIF 25 25 X16_LANE_15_0 20 20 X2_LANE_1_0 0 0 X2_LANE_11_10 5 5 X2_LANE_13_12 6 6 X2_LANE_15_14 7 7 X2_LANE_3_2 1 1 X2_LANE_5_4 2 2 X2_LANE_7_6 3 3 X2_LANE_9_8 4 4 X4_LANE_11_8 10 10 X4_LANE_15_12 11 11 X4_LANE_3_0 8 8 X4_LANE_7_4 9 9 X8_LANE_15_8 17 17 X8_LANE_7_0 16 16 ixPB1_PIF_PDNB_OVERRIDE_0 2 0x20 10 0 4294967295 RXEN_OVERRIDE_EN_0 8 8 RXEN_OVERRIDE_VAL_0 9 9 RX_PDNB_OVERRIDE_EN_0 4 4 RX_PDNB_OVERRIDE_VAL_0 5 7 RXPWR_OVERRIDE_EN_0 14 14 RXPWR_OVERRIDE_VAL_0 15 17 TX_PDNB_OVERRIDE_EN_0 0 0 TX_PDNB_OVERRIDE_VAL_0 1 3 TXPWR_OVERRIDE_EN_0 10 10 TXPWR_OVERRIDE_VAL_0 11 13 ixPB1_PIF_PDNB_OVERRIDE_10 2 0x32 10 0 4294967295 RXEN_OVERRIDE_EN_10 8 8 RXEN_OVERRIDE_VAL_10 9 9 RX_PDNB_OVERRIDE_EN_10 4 4 RX_PDNB_OVERRIDE_VAL_10 5 7 RXPWR_OVERRIDE_EN_10 14 14 RXPWR_OVERRIDE_VAL_10 15 17 TX_PDNB_OVERRIDE_EN_10 0 0 TX_PDNB_OVERRIDE_VAL_10 1 3 TXPWR_OVERRIDE_EN_10 10 10 TXPWR_OVERRIDE_VAL_10 11 13 ixPB1_PIF_PDNB_OVERRIDE_1 2 0x21 10 0 4294967295 RXEN_OVERRIDE_EN_1 8 8 RXEN_OVERRIDE_VAL_1 9 9 RX_PDNB_OVERRIDE_EN_1 4 4 RX_PDNB_OVERRIDE_VAL_1 5 7 RXPWR_OVERRIDE_EN_1 14 14 RXPWR_OVERRIDE_VAL_1 15 17 TX_PDNB_OVERRIDE_EN_1 0 0 TX_PDNB_OVERRIDE_VAL_1 1 3 TXPWR_OVERRIDE_EN_1 10 10 TXPWR_OVERRIDE_VAL_1 11 13 ixPB1_PIF_PDNB_OVERRIDE_11 2 0x33 10 0 4294967295 RXEN_OVERRIDE_EN_11 8 8 RXEN_OVERRIDE_VAL_11 9 9 RX_PDNB_OVERRIDE_EN_11 4 4 RX_PDNB_OVERRIDE_VAL_11 5 7 RXPWR_OVERRIDE_EN_11 14 14 RXPWR_OVERRIDE_VAL_11 15 17 TX_PDNB_OVERRIDE_EN_11 0 0 TX_PDNB_OVERRIDE_VAL_11 1 3 TXPWR_OVERRIDE_EN_11 10 10 TXPWR_OVERRIDE_VAL_11 11 13 ixPB1_PIF_PDNB_OVERRIDE_12 2 0x34 10 0 4294967295 RXEN_OVERRIDE_EN_12 8 8 RXEN_OVERRIDE_VAL_12 9 9 RX_PDNB_OVERRIDE_EN_12 4 4 RX_PDNB_OVERRIDE_VAL_12 5 7 RXPWR_OVERRIDE_EN_12 14 14 RXPWR_OVERRIDE_VAL_12 15 17 TX_PDNB_OVERRIDE_EN_12 0 0 TX_PDNB_OVERRIDE_VAL_12 1 3 TXPWR_OVERRIDE_EN_12 10 10 TXPWR_OVERRIDE_VAL_12 11 13 ixPB1_PIF_PDNB_OVERRIDE_13 2 0x35 10 0 4294967295 RXEN_OVERRIDE_EN_13 8 8 RXEN_OVERRIDE_VAL_13 9 9 RX_PDNB_OVERRIDE_EN_13 4 4 RX_PDNB_OVERRIDE_VAL_13 5 7 RXPWR_OVERRIDE_EN_13 14 14 RXPWR_OVERRIDE_VAL_13 15 17 TX_PDNB_OVERRIDE_EN_13 0 0 TX_PDNB_OVERRIDE_VAL_13 1 3 TXPWR_OVERRIDE_EN_13 10 10 TXPWR_OVERRIDE_VAL_13 11 13 ixPB1_PIF_PDNB_OVERRIDE_14 2 0x36 10 0 4294967295 RXEN_OVERRIDE_EN_14 8 8 RXEN_OVERRIDE_VAL_14 9 9 RX_PDNB_OVERRIDE_EN_14 4 4 RX_PDNB_OVERRIDE_VAL_14 5 7 RXPWR_OVERRIDE_EN_14 14 14 RXPWR_OVERRIDE_VAL_14 15 17 TX_PDNB_OVERRIDE_EN_14 0 0 TX_PDNB_OVERRIDE_VAL_14 1 3 TXPWR_OVERRIDE_EN_14 10 10 TXPWR_OVERRIDE_VAL_14 11 13 ixPB1_PIF_PDNB_OVERRIDE_15 2 0x37 10 0 4294967295 RXEN_OVERRIDE_EN_15 8 8 RXEN_OVERRIDE_VAL_15 9 9 RX_PDNB_OVERRIDE_EN_15 4 4 RX_PDNB_OVERRIDE_VAL_15 5 7 RXPWR_OVERRIDE_EN_15 14 14 RXPWR_OVERRIDE_VAL_15 15 17 TX_PDNB_OVERRIDE_EN_15 0 0 TX_PDNB_OVERRIDE_VAL_15 1 3 TXPWR_OVERRIDE_EN_15 10 10 TXPWR_OVERRIDE_VAL_15 11 13 ixPB1_PIF_PDNB_OVERRIDE_2 2 0x22 10 0 4294967295 RXEN_OVERRIDE_EN_2 8 8 RXEN_OVERRIDE_VAL_2 9 9 RX_PDNB_OVERRIDE_EN_2 4 4 RX_PDNB_OVERRIDE_VAL_2 5 7 RXPWR_OVERRIDE_EN_2 14 14 RXPWR_OVERRIDE_VAL_2 15 17 TX_PDNB_OVERRIDE_EN_2 0 0 TX_PDNB_OVERRIDE_VAL_2 1 3 TXPWR_OVERRIDE_EN_2 10 10 TXPWR_OVERRIDE_VAL_2 11 13 ixPB1_PIF_PDNB_OVERRIDE_3 2 0x23 10 0 4294967295 RXEN_OVERRIDE_EN_3 8 8 RXEN_OVERRIDE_VAL_3 9 9 RX_PDNB_OVERRIDE_EN_3 4 4 RX_PDNB_OVERRIDE_VAL_3 5 7 RXPWR_OVERRIDE_EN_3 14 14 RXPWR_OVERRIDE_VAL_3 15 17 TX_PDNB_OVERRIDE_EN_3 0 0 TX_PDNB_OVERRIDE_VAL_3 1 3 TXPWR_OVERRIDE_EN_3 10 10 TXPWR_OVERRIDE_VAL_3 11 13 ixPB1_PIF_PDNB_OVERRIDE_4 2 0x24 10 0 4294967295 RXEN_OVERRIDE_EN_4 8 8 RXEN_OVERRIDE_VAL_4 9 9 RX_PDNB_OVERRIDE_EN_4 4 4 RX_PDNB_OVERRIDE_VAL_4 5 7 RXPWR_OVERRIDE_EN_4 14 14 RXPWR_OVERRIDE_VAL_4 15 17 TX_PDNB_OVERRIDE_EN_4 0 0 TX_PDNB_OVERRIDE_VAL_4 1 3 TXPWR_OVERRIDE_EN_4 10 10 TXPWR_OVERRIDE_VAL_4 11 13 ixPB1_PIF_PDNB_OVERRIDE_5 2 0x25 10 0 4294967295 RXEN_OVERRIDE_EN_5 8 8 RXEN_OVERRIDE_VAL_5 9 9 RX_PDNB_OVERRIDE_EN_5 4 4 RX_PDNB_OVERRIDE_VAL_5 5 7 RXPWR_OVERRIDE_EN_5 14 14 RXPWR_OVERRIDE_VAL_5 15 17 TX_PDNB_OVERRIDE_EN_5 0 0 TX_PDNB_OVERRIDE_VAL_5 1 3 TXPWR_OVERRIDE_EN_5 10 10 TXPWR_OVERRIDE_VAL_5 11 13 ixPB1_PIF_PDNB_OVERRIDE_6 2 0x26 10 0 4294967295 RXEN_OVERRIDE_EN_6 8 8 RXEN_OVERRIDE_VAL_6 9 9 RX_PDNB_OVERRIDE_EN_6 4 4 RX_PDNB_OVERRIDE_VAL_6 5 7 RXPWR_OVERRIDE_EN_6 14 14 RXPWR_OVERRIDE_VAL_6 15 17 TX_PDNB_OVERRIDE_EN_6 0 0 TX_PDNB_OVERRIDE_VAL_6 1 3 TXPWR_OVERRIDE_EN_6 10 10 TXPWR_OVERRIDE_VAL_6 11 13 ixPB1_PIF_PDNB_OVERRIDE_7 2 0x27 10 0 4294967295 RXEN_OVERRIDE_EN_7 8 8 RXEN_OVERRIDE_VAL_7 9 9 RX_PDNB_OVERRIDE_EN_7 4 4 RX_PDNB_OVERRIDE_VAL_7 5 7 RXPWR_OVERRIDE_EN_7 14 14 RXPWR_OVERRIDE_VAL_7 15 17 TX_PDNB_OVERRIDE_EN_7 0 0 TX_PDNB_OVERRIDE_VAL_7 1 3 TXPWR_OVERRIDE_EN_7 10 10 TXPWR_OVERRIDE_VAL_7 11 13 ixPB1_PIF_PDNB_OVERRIDE_8 2 0x30 10 0 4294967295 RXEN_OVERRIDE_EN_8 8 8 RXEN_OVERRIDE_VAL_8 9 9 RX_PDNB_OVERRIDE_EN_8 4 4 RX_PDNB_OVERRIDE_VAL_8 5 7 RXPWR_OVERRIDE_EN_8 14 14 RXPWR_OVERRIDE_VAL_8 15 17 TX_PDNB_OVERRIDE_EN_8 0 0 TX_PDNB_OVERRIDE_VAL_8 1 3 TXPWR_OVERRIDE_EN_8 10 10 TXPWR_OVERRIDE_VAL_8 11 13 ixPB1_PIF_PDNB_OVERRIDE_9 2 0x31 10 0 4294967295 RXEN_OVERRIDE_EN_9 8 8 RXEN_OVERRIDE_VAL_9 9 9 RX_PDNB_OVERRIDE_EN_9 4 4 RX_PDNB_OVERRIDE_VAL_9 5 7 RXPWR_OVERRIDE_EN_9 14 14 RXPWR_OVERRIDE_VAL_9 15 17 TX_PDNB_OVERRIDE_EN_9 0 0 TX_PDNB_OVERRIDE_VAL_9 1 3 TXPWR_OVERRIDE_EN_9 10 10 TXPWR_OVERRIDE_VAL_9 11 13 ixPB1_PIF_PWRDOWN_0 2 0x12 9 0 4294967295 FORCE_RXEN_IN_L0s_0 3 3 PLL_POWER_STATE_IN_OFF_0 10 12 PLL_POWER_STATE_IN_TXS2_0 7 9 PLLPWR_OVERRIDE_EN_0 28 28 PLLPWR_OVERRIDE_VAL_0 29 31 PLL_RAMP_UP_TIME_0 24 26 RX_POWER_STATE_IN_RXS2_0 4 6 TX2P5CLK_CLOCK_GATING_EN_0 16 16 TX_POWER_STATE_IN_TXS2_0 0 2 ixPB1_PIF_PWRDOWN_1 2 0x13 9 0 4294967295 FORCE_RXEN_IN_L0s_1 3 3 PLL_POWER_STATE_IN_OFF_1 10 12 PLL_POWER_STATE_IN_TXS2_1 7 9 PLLPWR_OVERRIDE_EN_1 28 28 PLLPWR_OVERRIDE_VAL_1 29 31 PLL_RAMP_UP_TIME_1 24 26 RX_POWER_STATE_IN_RXS2_1 4 6 TX2P5CLK_CLOCK_GATING_EN_1 16 16 TX_POWER_STATE_IN_TXS2_1 0 2 ixPB1_PIF_PWRDOWN_2 2 0x17 9 0 4294967295 FORCE_RXEN_IN_L0s_2 3 3 PLL_POWER_STATE_IN_OFF_2 10 12 PLL_POWER_STATE_IN_TXS2_2 7 9 PLLPWR_OVERRIDE_EN_2 28 28 PLLPWR_OVERRIDE_VAL_2 29 31 PLL_RAMP_UP_TIME_2 24 26 RX_POWER_STATE_IN_RXS2_2 4 6 TX2P5CLK_CLOCK_GATING_EN_2 16 16 TX_POWER_STATE_IN_TXS2_2 0 2 ixPB1_PIF_PWRDOWN_3 2 0x18 9 0 4294967295 FORCE_RXEN_IN_L0s_3 3 3 PLL_POWER_STATE_IN_OFF_3 10 12 PLL_POWER_STATE_IN_TXS2_3 7 9 PLLPWR_OVERRIDE_EN_3 28 28 PLLPWR_OVERRIDE_VAL_3 29 31 PLL_RAMP_UP_TIME_3 24 26 RX_POWER_STATE_IN_RXS2_3 4 6 TX2P5CLK_CLOCK_GATING_EN_3 16 16 TX_POWER_STATE_IN_TXS2_3 0 2 ixPB1_PIF_SC_CTL 2 0x16 31 0 4294967295 SC_CALIBRATION 0 0 SC_ENTER_L1_FROM_L0 5 5 SC_ENTER_L1_FROM_L0S 4 4 SC_EXIT_L1_TO_L0 3 3 SC_EXIT_L1_TO_L0S 2 2 SC_LANE_0_RESUME 16 16 SC_LANE_10_RESUME 26 26 SC_LANE_11_RESUME 27 27 SC_LANE_12_RESUME 28 28 SC_LANE_13_RESUME 29 29 SC_LANE_14_RESUME 30 30 SC_LANE_15_RESUME 31 31 SC_LANE_1_RESUME 17 17 SC_LANE_2_RESUME 18 18 SC_LANE_3_RESUME 19 19 SC_LANE_4_RESUME 20 20 SC_LANE_5_RESUME 21 21 SC_LANE_6_RESUME 22 22 SC_LANE_7_RESUME 23 23 SC_LANE_8_RESUME 24 24 SC_LANE_9_RESUME 25 25 SC_PHASE_1 8 8 SC_PHASE_2 9 9 SC_PHASE_3 10 10 SC_PHASE_4 11 11 SC_PHASE_5 12 12 SC_PHASE_6 13 13 SC_PHASE_7 14 14 SC_PHASE_8 15 15 SC_RXDETECT 1 1 SC_SPEED_CHANGE 6 6 ixPB1_PIF_SCRATCH 2 0x1 1 0 4294967295 PIF_SCRATCH 0 31 ixPB1_PIF_SEQ_STATUS_0 2 0x28 8 0 4294967295 SEQ_CALIBRATION_0 0 0 SEQ_ENTER_L1_FROM_L0_0 5 5 SEQ_ENTER_L1_FROM_L0S_0 4 4 SEQ_EXIT_L1_TO_L0_0 3 3 SEQ_EXIT_L1_TO_L0S_0 2 2 SEQ_PHASE_0 8 10 SEQ_RXDETECT_0 1 1 SEQ_SPEED_CHANGE_0 6 6 ixPB1_PIF_SEQ_STATUS_10 2 0x3a 8 0 4294967295 SEQ_CALIBRATION_10 0 0 SEQ_ENTER_L1_FROM_L0_10 5 5 SEQ_ENTER_L1_FROM_L0S_10 4 4 SEQ_EXIT_L1_TO_L0_10 3 3 SEQ_EXIT_L1_TO_L0S_10 2 2 SEQ_PHASE_10 8 10 SEQ_RXDETECT_10 1 1 SEQ_SPEED_CHANGE_10 6 6 ixPB1_PIF_SEQ_STATUS_1 2 0x29 8 0 4294967295 SEQ_CALIBRATION_1 0 0 SEQ_ENTER_L1_FROM_L0_1 5 5 SEQ_ENTER_L1_FROM_L0S_1 4 4 SEQ_EXIT_L1_TO_L0_1 3 3 SEQ_EXIT_L1_TO_L0S_1 2 2 SEQ_PHASE_1 8 10 SEQ_RXDETECT_1 1 1 SEQ_SPEED_CHANGE_1 6 6 ixPB1_PIF_SEQ_STATUS_11 2 0x3b 8 0 4294967295 SEQ_CALIBRATION_11 0 0 SEQ_ENTER_L1_FROM_L0_11 5 5 SEQ_ENTER_L1_FROM_L0S_11 4 4 SEQ_EXIT_L1_TO_L0_11 3 3 SEQ_EXIT_L1_TO_L0S_11 2 2 SEQ_PHASE_11 8 10 SEQ_RXDETECT_11 1 1 SEQ_SPEED_CHANGE_11 6 6 ixPB1_PIF_SEQ_STATUS_12 2 0x3c 8 0 4294967295 SEQ_CALIBRATION_12 0 0 SEQ_ENTER_L1_FROM_L0_12 5 5 SEQ_ENTER_L1_FROM_L0S_12 4 4 SEQ_EXIT_L1_TO_L0_12 3 3 SEQ_EXIT_L1_TO_L0S_12 2 2 SEQ_PHASE_12 8 10 SEQ_RXDETECT_12 1 1 SEQ_SPEED_CHANGE_12 6 6 ixPB1_PIF_SEQ_STATUS_13 2 0x3d 8 0 4294967295 SEQ_CALIBRATION_13 0 0 SEQ_ENTER_L1_FROM_L0_13 5 5 SEQ_ENTER_L1_FROM_L0S_13 4 4 SEQ_EXIT_L1_TO_L0_13 3 3 SEQ_EXIT_L1_TO_L0S_13 2 2 SEQ_PHASE_13 8 10 SEQ_RXDETECT_13 1 1 SEQ_SPEED_CHANGE_13 6 6 ixPB1_PIF_SEQ_STATUS_14 2 0x3e 8 0 4294967295 SEQ_CALIBRATION_14 0 0 SEQ_ENTER_L1_FROM_L0_14 5 5 SEQ_ENTER_L1_FROM_L0S_14 4 4 SEQ_EXIT_L1_TO_L0_14 3 3 SEQ_EXIT_L1_TO_L0S_14 2 2 SEQ_PHASE_14 8 10 SEQ_RXDETECT_14 1 1 SEQ_SPEED_CHANGE_14 6 6 ixPB1_PIF_SEQ_STATUS_15 2 0x3f 8 0 4294967295 SEQ_CALIBRATION_15 0 0 SEQ_ENTER_L1_FROM_L0_15 5 5 SEQ_ENTER_L1_FROM_L0S_15 4 4 SEQ_EXIT_L1_TO_L0_15 3 3 SEQ_EXIT_L1_TO_L0S_15 2 2 SEQ_PHASE_15 8 10 SEQ_RXDETECT_15 1 1 SEQ_SPEED_CHANGE_15 6 6 ixPB1_PIF_SEQ_STATUS_2 2 0x2a 8 0 4294967295 SEQ_CALIBRATION_2 0 0 SEQ_ENTER_L1_FROM_L0_2 5 5 SEQ_ENTER_L1_FROM_L0S_2 4 4 SEQ_EXIT_L1_TO_L0_2 3 3 SEQ_EXIT_L1_TO_L0S_2 2 2 SEQ_PHASE_2 8 10 SEQ_RXDETECT_2 1 1 SEQ_SPEED_CHANGE_2 6 6 ixPB1_PIF_SEQ_STATUS_3 2 0x2b 8 0 4294967295 SEQ_CALIBRATION_3 0 0 SEQ_ENTER_L1_FROM_L0_3 5 5 SEQ_ENTER_L1_FROM_L0S_3 4 4 SEQ_EXIT_L1_TO_L0_3 3 3 SEQ_EXIT_L1_TO_L0S_3 2 2 SEQ_PHASE_3 8 10 SEQ_RXDETECT_3 1 1 SEQ_SPEED_CHANGE_3 6 6 ixPB1_PIF_SEQ_STATUS_4 2 0x2c 8 0 4294967295 SEQ_CALIBRATION_4 0 0 SEQ_ENTER_L1_FROM_L0_4 5 5 SEQ_ENTER_L1_FROM_L0S_4 4 4 SEQ_EXIT_L1_TO_L0_4 3 3 SEQ_EXIT_L1_TO_L0S_4 2 2 SEQ_PHASE_4 8 10 SEQ_RXDETECT_4 1 1 SEQ_SPEED_CHANGE_4 6 6 ixPB1_PIF_SEQ_STATUS_5 2 0x2d 8 0 4294967295 SEQ_CALIBRATION_5 0 0 SEQ_ENTER_L1_FROM_L0_5 5 5 SEQ_ENTER_L1_FROM_L0S_5 4 4 SEQ_EXIT_L1_TO_L0_5 3 3 SEQ_EXIT_L1_TO_L0S_5 2 2 SEQ_PHASE_5 8 10 SEQ_RXDETECT_5 1 1 SEQ_SPEED_CHANGE_5 6 6 ixPB1_PIF_SEQ_STATUS_6 2 0x2e 8 0 4294967295 SEQ_CALIBRATION_6 0 0 SEQ_ENTER_L1_FROM_L0_6 5 5 SEQ_ENTER_L1_FROM_L0S_6 4 4 SEQ_EXIT_L1_TO_L0_6 3 3 SEQ_EXIT_L1_TO_L0S_6 2 2 SEQ_PHASE_6 8 10 SEQ_RXDETECT_6 1 1 SEQ_SPEED_CHANGE_6 6 6 ixPB1_PIF_SEQ_STATUS_7 2 0x2f 8 0 4294967295 SEQ_CALIBRATION_7 0 0 SEQ_ENTER_L1_FROM_L0_7 5 5 SEQ_ENTER_L1_FROM_L0S_7 4 4 SEQ_EXIT_L1_TO_L0_7 3 3 SEQ_EXIT_L1_TO_L0S_7 2 2 SEQ_PHASE_7 8 10 SEQ_RXDETECT_7 1 1 SEQ_SPEED_CHANGE_7 6 6 ixPB1_PIF_SEQ_STATUS_8 2 0x38 8 0 4294967295 SEQ_CALIBRATION_8 0 0 SEQ_ENTER_L1_FROM_L0_8 5 5 SEQ_ENTER_L1_FROM_L0S_8 4 4 SEQ_EXIT_L1_TO_L0_8 3 3 SEQ_EXIT_L1_TO_L0S_8 2 2 SEQ_PHASE_8 8 10 SEQ_RXDETECT_8 1 1 SEQ_SPEED_CHANGE_8 6 6 ixPB1_PIF_SEQ_STATUS_9 2 0x39 8 0 4294967295 SEQ_CALIBRATION_9 0 0 SEQ_ENTER_L1_FROM_L0_9 5 5 SEQ_ENTER_L1_FROM_L0S_9 4 4 SEQ_EXIT_L1_TO_L0_9 3 3 SEQ_EXIT_L1_TO_L0S_9 2 2 SEQ_PHASE_9 8 10 SEQ_RXDETECT_9 1 1 SEQ_SPEED_CHANGE_9 6 6 ixPB1_PIF_TXPHYSTATUS 2 0x15 16 0 4294967295 TXPHYSTATUS_0 0 0 TXPHYSTATUS_10 10 10 TXPHYSTATUS_11 11 11 TXPHYSTATUS_12 12 12 TXPHYSTATUS_13 13 13 TXPHYSTATUS_14 14 14 TXPHYSTATUS_15 15 15 TXPHYSTATUS_1 1 1 TXPHYSTATUS_2 2 2 TXPHYSTATUS_3 3 3 TXPHYSTATUS_4 4 4 TXPHYSTATUS_5 5 5 TXPHYSTATUS_6 6 6 TXPHYSTATUS_7 7 7 TXPHYSTATUS_8 8 8 TXPHYSTATUS_9 9 9 ixPB1_PLL_LC0_CTRL_REG0 2 0x14480 4 0 4294967295 PLL_DBG_LC_ANALOG_SEL_0 0 1 PLL_DBG_LC_EXT_RESET_EN_0 2 2 PLL_DBG_LC_VCTL_ADC_EN_0 3 3 PLL_TST_LC_USAMPLE_EN_0 4 4 ixPB1_PLL_LC0_OVRD_REG0 2 0x14490 12 0 4294967295 PLL_CFG_LC_BW_CNTRL_OVRD_EN_0 3 3 PLL_CFG_LC_BW_CNTRL_OVRD_VAL_0 0 2 PLL_CFG_LC_CORECLK_DIV_OVRD_EN_0 7 7 PLL_CFG_LC_CORECLK_DIV_OVRD_VAL_0 4 6 PLL_CFG_LC_CORECLK_EN_OVRD_EN_0 9 9 PLL_CFG_LC_CORECLK_EN_OVRD_VAL_0 8 8 PLL_CFG_LC_FBDIV_OVRD_EN_0 18 18 PLL_CFG_LC_FBDIV_OVRD_VAL_0 10 17 PLL_CFG_LC_LF_CNTRL_OVRD_EN_0 28 28 PLL_CFG_LC_LF_CNTRL_OVRD_VAL_0 19 27 PLL_CFG_LC_REFDIV_OVRD_EN_0 31 31 PLL_CFG_LC_REFDIV_OVRD_VAL_0 29 30 ixPB1_PLL_LC0_OVRD_REG1 2 0x14494 10 0 4294967295 PLL_CFG_LC_REFCLK_SRC_OVRD_EN_0 3 3 PLL_CFG_LC_REFCLK_SRC_OVRD_VAL_0 0 2 PLL_CFG_LC_VCO_TUNE_OVRD_EN_0 18 18 PLL_CFG_LC_VCO_TUNE_OVRD_VAL_0 14 17 PLL_LC_HSCLK_LEFT_EN_OVRD_EN_0 5 5 PLL_LC_HSCLK_LEFT_EN_OVRD_VAL_0 4 4 PLL_LC_HSCLK_RIGHT_EN_OVRD_EN_0 7 7 PLL_LC_HSCLK_RIGHT_EN_OVRD_VAL_0 6 6 PLL_LC_PWRON_OVRD_EN_0 9 9 PLL_LC_PWRON_OVRD_VAL_0 8 8 ixPB1_PLL_LC0_SCI_STAT_OVRD_REG0 2 0x14500 4 0 4294967295 PLL_LC0_FREQMODE 8 9 PLL_LC0_IGNR_FREQMODE_SCI_UPDT 1 1 PLL_LC0_IGNR_PLLPWR_SCI_UPDT 0 0 PLL_LC0_PLLPWR 4 6 ixPB1_PLL_LC1_SCI_STAT_OVRD_REG0 2 0x14504 4 0 4294967295 PLL_LC1_FREQMODE 8 9 PLL_LC1_IGNR_FREQMODE_SCI_UPDT 1 1 PLL_LC1_IGNR_PLLPWR_SCI_UPDT 0 0 PLL_LC1_PLLPWR 4 6 ixPB1_PLL_LC2_SCI_STAT_OVRD_REG0 2 0x14508 4 0 4294967295 PLL_LC2_FREQMODE 8 9 PLL_LC2_IGNR_FREQMODE_SCI_UPDT 1 1 PLL_LC2_IGNR_PLLPWR_SCI_UPDT 0 0 PLL_LC2_PLLPWR 4 6 ixPB1_PLL_LC3_SCI_STAT_OVRD_REG0 2 0x1450c 4 0 4294967295 PLL_LC3_FREQMODE 8 9 PLL_LC3_IGNR_FREQMODE_SCI_UPDT 1 1 PLL_LC3_IGNR_PLLPWR_SCI_UPDT 0 0 PLL_LC3_PLLPWR 4 6 ixPB1_PLL_RO0_CTRL_REG0 2 0x14440 5 0 4294967295 PLL_DBG_RO_ANALOG_SEL_0 0 1 PLL_DBG_RO_EXT_RESET_EN_0 2 2 PLL_DBG_RO_LF_CNTRL_0 4 10 PLL_DBG_RO_VCTL_ADC_EN_0 3 3 PLL_TST_RO_USAMPLE_EN_0 11 11 ixPB1_PLL_RO0_OVRD_REG0 2 0x14450 10 0 4294967295 PLL_CFG_RO_BW_CNTRL_OVRD_EN_0 8 8 PLL_CFG_RO_BW_CNTRL_OVRD_VAL_0 0 7 PLL_CFG_RO_CORECLK_DIV_OVRD_EN_0 12 12 PLL_CFG_RO_CORECLK_DIV_OVRD_VAL_0 9 11 PLL_CFG_RO_CORECLK_EN_OVRD_EN_0 14 14 PLL_CFG_RO_CORECLK_EN_OVRD_VAL_0 13 13 PLL_CFG_RO_FBDIV_OVRD_EN_0 28 28 PLL_CFG_RO_FBDIV_OVRD_VAL_0 15 27 PLL_CFG_RO_VTOI_BIAS_CNTRL_OVRD_EN_0 31 31 PLL_CFG_RO_VTOI_BIAS_CNTRL_OVRD_VAL_0 30 30 ixPB1_PLL_RO0_OVRD_REG1 2 0x14454 12 0 4294967295 PLL_CFG_RO_REFCLK_SRC_OVRD_EN_0 22 22 PLL_CFG_RO_REFCLK_SRC_OVRD_VAL_0 19 21 PLL_CFG_RO_REFDIV_OVRD_EN_0 5 5 PLL_CFG_RO_REFDIV_OVRD_VAL_0 0 4 PLL_CFG_RO_VCO_MODE_OVRD_EN_0 8 8 PLL_CFG_RO_VCO_MODE_OVRD_VAL_0 6 7 PLL_RO_HSCLK_LEFT_EN_OVRD_EN_0 10 10 PLL_RO_HSCLK_LEFT_EN_OVRD_VAL_0 9 9 PLL_RO_HSCLK_RIGHT_EN_OVRD_EN_0 12 12 PLL_RO_HSCLK_RIGHT_EN_OVRD_VAL_0 11 11 PLL_RO_PWRON_OVRD_EN_0 14 14 PLL_RO_PWRON_OVRD_VAL_0 13 13 ixPB1_PLL_RO0_SCI_STAT_OVRD_REG0 2 0x14460 4 0 4294967295 PLL_RO0_FREQMODE 8 9 PLL_RO0_IGNR_FREQMODE_SCI_UPDT 1 1 PLL_RO0_IGNR_PLLPWR_SCI_UPDT 0 0 PLL_RO0_PLLPWR 4 6 ixPB1_PLL_RO1_SCI_STAT_OVRD_REG0 2 0x14464 4 0 4294967295 PLL_RO1_FREQMODE 8 9 PLL_RO1_IGNR_FREQMODE_SCI_UPDT 1 1 PLL_RO1_IGNR_PLLPWR_SCI_UPDT 0 0 PLL_RO1_PLLPWR 4 6 ixPB1_PLL_RO2_SCI_STAT_OVRD_REG0 2 0x14468 4 0 4294967295 PLL_RO2_FREQMODE 8 9 PLL_RO2_IGNR_FREQMODE_SCI_UPDT 1 1 PLL_RO2_IGNR_PLLPWR_SCI_UPDT 0 0 PLL_RO2_PLLPWR 4 6 ixPB1_PLL_RO3_SCI_STAT_OVRD_REG0 2 0x1446c 4 0 4294967295 PLL_RO3_FREQMODE 8 9 PLL_RO3_IGNR_FREQMODE_SCI_UPDT 1 1 PLL_RO3_IGNR_PLLPWR_SCI_UPDT 0 0 PLL_RO3_PLLPWR 4 6 ixPB1_PLL_RO_GLB_CTRL_REG0 2 0x14000 23 0 4294967295 PLL_LC_HSCLK_LEFT_EN_LUT_ENTRY_LS0 9 9 PLL_LC_HSCLK_LEFT_EN_LUT_ENTRY_LS1 10 10 PLL_LC_HSCLK_LEFT_EN_LUT_ENTRY_LS2 11 11 PLL_LC_HSCLK_LEFT_LEFT_EN_GATING_EN 20 20 PLL_LC_HSCLK_LEFT_RIGHT_EN_GATING_EN 21 21 PLL_LC_HSCLK_RIGHT_EN_LUT_ENTRY_LS0 12 12 PLL_LC_HSCLK_RIGHT_EN_LUT_ENTRY_LS1 13 13 PLL_LC_HSCLK_RIGHT_EN_LUT_ENTRY_LS2 14 14 PLL_LC_HSCLK_RIGHT_LEFT_EN_GATING_EN 22 22 PLL_LC_HSCLK_RIGHT_RIGHT_EN_GATING_EN 23 23 PLL_LC_PWRON_LUT_ENTRY_LS2 8 8 PLL_RO_HSCLK_LEFT_EN_LUT_ENTRY_LS0 1 1 PLL_RO_HSCLK_LEFT_EN_LUT_ENTRY_LS1 2 2 PLL_RO_HSCLK_LEFT_EN_LUT_ENTRY_LS2 3 3 PLL_RO_HSCLK_LEFT_LEFT_EN_GATING_EN 16 16 PLL_RO_HSCLK_LEFT_RIGHT_EN_GATING_EN 17 17 PLL_RO_HSCLK_RIGHT_EN_LUT_ENTRY_LS0 4 4 PLL_RO_HSCLK_RIGHT_EN_LUT_ENTRY_LS1 5 5 PLL_RO_HSCLK_RIGHT_EN_LUT_ENTRY_LS2 6 6 PLL_RO_HSCLK_RIGHT_LEFT_EN_GATING_EN 18 18 PLL_RO_HSCLK_RIGHT_RIGHT_EN_GATING_EN 19 19 PLL_RO_PWRON_LUT_ENTRY_LS2 7 7 PLL_TST_LOSPDTST_SRC 0 0 ixPB1_PLL_RO_GLB_OVRD_REG0 2 0x14010 0 0 4294967295 ixPB1_RX_GLB_CTRL_REG0 2 0x16000 4 0 4294967295 RX_CFG_ADAPT_MODE_GEN1 0 9 RX_CFG_ADAPT_MODE_GEN2 10 19 RX_CFG_ADAPT_MODE_GEN3 20 29 RX_CFG_ADAPT_RST_MODE 30 31 ixPB1_RX_GLB_CTRL_REG1 2 0x16004 13 0 4294967295 RX_ADAPT_HLD_ASRT_TO_DCLK_EN 30 31 RX_CFG_CDR_FR_GAIN_GEN1 0 3 RX_CFG_CDR_FR_GAIN_GEN2 4 7 RX_CFG_CDR_FR_GAIN_GEN3 8 11 RX_CFG_CDR_PH_GAIN_GEN1 12 15 RX_CFG_CDR_PH_GAIN_GEN2 16 19 RX_CFG_CDR_PH_GAIN_GEN3 20 23 RX_CFG_CDR_PI_STPSZ_GEN1 24 24 RX_CFG_CDR_PI_STPSZ_GEN2 25 25 RX_CFG_CDR_PI_STPSZ_GEN3 26 26 RX_CFG_LEQ_DCATTN_BYP_EN_GEN1 27 27 RX_CFG_LEQ_DCATTN_BYP_EN_GEN2 28 28 RX_CFG_LEQ_DCATTN_BYP_EN_GEN3 29 29 ixPB1_RX_GLB_CTRL_REG2 2 0x16008 7 0 4294967295 RX_CFG_CDR_TIME_GEN1 12 15 RX_CFG_CDR_TIME_GEN2 16 19 RX_CFG_CDR_TIME_GEN3 20 23 RX_CFG_LEQ_LOOP_GAIN_GEN1 24 25 RX_CFG_LEQ_LOOP_GAIN_GEN2 26 27 RX_CFG_LEQ_LOOP_GAIN_GEN3 28 29 RX_DCLK_EN_ASRT_TO_ADAPT_HLD 30 31 ixPB1_RX_GLB_CTRL_REG3 2 0x1600c 6 0 4294967295 RX_CFG_CDR_FR_EN_GEN1 0 0 RX_CFG_CDR_FR_EN_GEN2 1 1 RX_CFG_CDR_FR_EN_GEN3 2 2 RX_CFG_DFE_TIME_GEN1 20 23 RX_CFG_DFE_TIME_GEN2 24 27 RX_CFG_DFE_TIME_GEN3 28 31 ixPB1_RX_GLB_CTRL_REG4 2 0x16010 9 0 4294967295 RX_CFG_FOM_BER_GEN1 0 2 RX_CFG_FOM_BER_GEN2 3 5 RX_CFG_FOM_BER_GEN3 6 8 RX_CFG_FOM_TIME_GEN1 20 23 RX_CFG_FOM_TIME_GEN2 24 27 RX_CFG_FOM_TIME_GEN3 28 31 RX_CFG_LEQ_POLE_BYP_VAL_GEN1 9 11 RX_CFG_LEQ_POLE_BYP_VAL_GEN2 12 14 RX_CFG_LEQ_POLE_BYP_VAL_GEN3 15 17 ixPB1_RX_GLB_CTRL_REG5 2 0x16014 13 0 4294967295 RX_CFG_LEQ_DCATTN_BYP_VAL_GEN1 0 4 RX_CFG_LEQ_DCATTN_BYP_VAL_GEN2 5 9 RX_CFG_LEQ_DCATTN_BYP_VAL_GEN3 10 14 RX_CFG_LEQ_POLE_BYP_EN_GEN1 15 15 RX_CFG_LEQ_POLE_BYP_EN_GEN2 16 16 RX_CFG_LEQ_POLE_BYP_EN_GEN3 17 17 RX_CFG_LEQ_SHUNT_EN_GEN1 18 18 RX_CFG_LEQ_SHUNT_EN_GEN2 19 19 RX_CFG_LEQ_SHUNT_EN_GEN3 20 20 RX_CFG_TERM_MODE_GEN1 27 27 RX_CFG_TERM_MODE_GEN2 28 28 RX_CFG_TERM_MODE_GEN3 29 29 RX_FORCE_DLL_RST_RXPWR_LS2OFF_TO_LS0 30 30 ixPB1_RX_GLB_CTRL_REG6 2 0x16018 9 0 4294967295 RX_AUX_PWRON_LUT_ENTRY_LS2 27 27 RX_CFG_LEQ_TIME_GEN1 0 3 RX_CFG_LEQ_TIME_GEN2 4 7 RX_CFG_LEQ_TIME_GEN3 8 11 RX_CFG_OC_TIME_GEN1 12 15 RX_CFG_OC_TIME_GEN2 16 19 RX_CFG_OC_TIME_GEN3 20 23 RX_FRONTEND_PWRON_LUT_ENTRY_LS0_CDR_EN_0 24 24 RX_FRONTEND_PWRON_LUT_ENTRY_LS2 26 26 ixPB1_RX_GLB_CTRL_REG7 2 0x1601c 12 0 4294967295 RX_CFG_DLL_CPI_SEL_GEN1 18 20 RX_CFG_DLL_CPI_SEL_GEN2 21 23 RX_CFG_DLL_CPI_SEL_GEN3 24 26 RX_CFG_DLL_FLOCK_DISABLE_GEN1 27 27 RX_CFG_DLL_FLOCK_DISABLE_GEN2 28 28 RX_CFG_DLL_FLOCK_DISABLE_GEN3 29 29 RX_CFG_TH_LOOP_GAIN_GEN1 0 3 RX_CFG_TH_LOOP_GAIN_GEN2 4 7 RX_CFG_TH_LOOP_GAIN_GEN3 8 11 RX_DCLK_EN_LUT_ENTRY_LS0_CDR_EN_0 12 12 RX_DCLK_EN_LUT_ENTRY_LS2 13 13 RX_DLL_PWRON_LUT_ENTRY_LS2 17 17 ixPB1_RX_GLB_CTRL_REG8 2 0x16020 0 0 4294967295 ixPB1_RX_GLB_OVRD_REG0 2 0x16030 26 0 4294967295 RX_ADAPT_FOM_OVRD_EN 31 31 RX_ADAPT_FOM_OVRD_VAL 30 30 RX_ADAPT_HLD_OVRD_EN 1 1 RX_ADAPT_HLD_OVRD_VAL 0 0 RX_ADAPT_RST_OVRD_EN 3 3 RX_ADAPT_RST_OVRD_VAL 2 2 RX_AUX_PWRON_OVRD_EN 29 29 RX_AUX_PWRON_OVRD_VAL 28 28 RX_CFG_DCLK_DIV_OVRD_EN 8 8 RX_CFG_DCLK_DIV_OVRD_VAL 6 7 RX_CFG_DLL_FREQ_MODE_OVRD_EN 10 10 RX_CFG_DLL_FREQ_MODE_OVRD_VAL 9 9 RX_CFG_PLLCLK_SEL_OVRD_EN 12 12 RX_CFG_PLLCLK_SEL_OVRD_VAL 11 11 RX_CFG_RCLK_DIV_OVRD_EN 14 14 RX_CFG_RCLK_DIV_OVRD_VAL 13 13 RX_DCLK_EN_OVRD_EN 16 16 RX_DCLK_EN_OVRD_VAL 15 15 RX_DLL_PWRON_OVRD_EN 18 18 RX_DLL_PWRON_OVRD_VAL 17 17 RX_FRONTEND_PWRON_OVRD_EN 20 20 RX_FRONTEND_PWRON_OVRD_VAL 19 19 RX_IDLEDET_PWRON_OVRD_EN 22 22 RX_IDLEDET_PWRON_OVRD_VAL 21 21 RX_TERM_EN_OVRD_EN 24 24 RX_TERM_EN_OVRD_VAL 23 23 ixPB1_RX_GLB_OVRD_REG1 2 0x16034 2 0 4294967295 RX_ADAPT_TRK_OVRD_EN 1 1 RX_ADAPT_TRK_OVRD_VAL 0 0 ixPB1_RX_GLB_SCI_STAT_OVRD_REG0 2 0x16028 24 0 4294967295 IGNR_ELECIDLEDETEN_SCI_UPDT_L0T3 4 4 IGNR_ELECIDLEDETEN_SCI_UPDT_L12T15 7 7 IGNR_ELECIDLEDETEN_SCI_UPDT_L4T7 5 5 IGNR_ELECIDLEDETEN_SCI_UPDT_L8T11 6 6 IGNR_ENABLEFOM_SCI_UPDT_L0T3 12 12 IGNR_ENABLEFOM_SCI_UPDT_L12T15 15 15 IGNR_ENABLEFOM_SCI_UPDT_L4T7 13 13 IGNR_ENABLEFOM_SCI_UPDT_L8T11 14 14 IGNR_REQUESTFOM_SCI_UPDT_L0T3 16 16 IGNR_REQUESTFOM_SCI_UPDT_L12T15 19 19 IGNR_REQUESTFOM_SCI_UPDT_L4T7 17 17 IGNR_REQUESTFOM_SCI_UPDT_L8T11 18 18 IGNR_RESPONSEMODE_SCI_UPDT_L0T3 20 20 IGNR_RESPONSEMODE_SCI_UPDT_L12T15 23 23 IGNR_RESPONSEMODE_SCI_UPDT_L4T7 21 21 IGNR_RESPONSEMODE_SCI_UPDT_L8T11 22 22 IGNR_RXPRESETHINT_SCI_UPDT_L0T3 8 8 IGNR_RXPRESETHINT_SCI_UPDT_L12T15 11 11 IGNR_RXPRESETHINT_SCI_UPDT_L4T7 9 9 IGNR_RXPRESETHINT_SCI_UPDT_L8T11 10 10 IGNR_RXPWR_SCI_UPDT_L0T3 0 0 IGNR_RXPWR_SCI_UPDT_L12T15 3 3 IGNR_RXPWR_SCI_UPDT_L4T7 1 1 IGNR_RXPWR_SCI_UPDT_L8T11 2 2 ixPB1_RX_LANE0_CTRL_REG0 2 0x16440 4 0 4294967295 RX_BACKUP_0 0 7 RX_CFG_OVR_PWRSF_0 13 13 RX_DBG_ANALOG_SEL_0 10 11 RX_TST_BSCAN_EN_0 12 12 ixPB1_RX_LANE0_SCI_STAT_OVRD_REG0 2 0x16448 6 0 4294967295 ELECIDLEDETEN_0 3 3 ENABLEFOM_0 7 7 REQUESTFOM_0 8 8 RESPONSEMODE_0 9 9 RXPRESETHINT_0 4 6 RXPWR_0 0 2 ixPB1_RX_LANE10_CTRL_REG0 2 0x17500 4 0 4294967295 RX_BACKUP_10 0 7 RX_CFG_OVR_PWRSF_10 13 13 RX_DBG_ANALOG_SEL_10 10 11 RX_TST_BSCAN_EN_10 12 12 ixPB1_RX_LANE10_SCI_STAT_OVRD_REG0 2 0x17508 6 0 4294967295 ELECIDLEDETEN_10 3 3 ENABLEFOM_10 7 7 REQUESTFOM_10 8 8 RESPONSEMODE_10 9 9 RXPRESETHINT_10 4 6 RXPWR_10 0 2 ixPB1_RX_LANE11_CTRL_REG0 2 0x17600 4 0 4294967295 RX_BACKUP_11 0 7 RX_CFG_OVR_PWRSF_11 13 13 RX_DBG_ANALOG_SEL_11 10 11 RX_TST_BSCAN_EN_11 12 12 ixPB1_RX_LANE11_SCI_STAT_OVRD_REG0 2 0x17608 6 0 4294967295 ELECIDLEDETEN_11 3 3 ENABLEFOM_11 7 7 REQUESTFOM_11 8 8 RESPONSEMODE_11 9 9 RXPRESETHINT_11 4 6 RXPWR_11 0 2 ixPB1_RX_LANE12_CTRL_REG0 2 0x17840 4 0 4294967295 RX_BACKUP_12 0 7 RX_CFG_OVR_PWRSF_12 13 13 RX_DBG_ANALOG_SEL_12 10 11 RX_TST_BSCAN_EN_12 12 12 ixPB1_RX_LANE12_SCI_STAT_OVRD_REG0 2 0x17848 6 0 4294967295 ELECIDLEDETEN_12 3 3 ENABLEFOM_12 7 7 REQUESTFOM_12 8 8 RESPONSEMODE_12 9 9 RXPRESETHINT_12 4 6 RXPWR_12 0 2 ixPB1_RX_LANE13_CTRL_REG0 2 0x17880 4 0 4294967295 RX_BACKUP_13 0 7 RX_CFG_OVR_PWRSF_13 13 13 RX_DBG_ANALOG_SEL_13 10 11 RX_TST_BSCAN_EN_13 12 12 ixPB1_RX_LANE13_SCI_STAT_OVRD_REG0 2 0x17888 6 0 4294967295 ELECIDLEDETEN_13 3 3 ENABLEFOM_13 7 7 REQUESTFOM_13 8 8 RESPONSEMODE_13 9 9 RXPRESETHINT_13 4 6 RXPWR_13 0 2 ixPB1_RX_LANE14_CTRL_REG0 2 0x17900 4 0 4294967295 RX_BACKUP_14 0 7 RX_CFG_OVR_PWRSF_14 13 13 RX_DBG_ANALOG_SEL_14 10 11 RX_TST_BSCAN_EN_14 12 12 ixPB1_RX_LANE14_SCI_STAT_OVRD_REG0 2 0x17908 6 0 4294967295 ELECIDLEDETEN_14 3 3 ENABLEFOM_14 7 7 REQUESTFOM_14 8 8 RESPONSEMODE_14 9 9 RXPRESETHINT_14 4 6 RXPWR_14 0 2 ixPB1_RX_LANE15_CTRL_REG0 2 0x17a00 4 0 4294967295 RX_BACKUP_15 0 7 RX_CFG_OVR_PWRSF_15 13 13 RX_DBG_ANALOG_SEL_15 10 11 RX_TST_BSCAN_EN_15 12 12 ixPB1_RX_LANE15_SCI_STAT_OVRD_REG0 2 0x17a08 6 0 4294967295 ELECIDLEDETEN_15 3 3 ENABLEFOM_15 7 7 REQUESTFOM_15 8 8 RESPONSEMODE_15 9 9 RXPRESETHINT_15 4 6 RXPWR_15 0 2 ixPB1_RX_LANE1_CTRL_REG0 2 0x16480 4 0 4294967295 RX_BACKUP_1 0 7 RX_CFG_OVR_PWRSF_1 13 13 RX_DBG_ANALOG_SEL_1 10 11 RX_TST_BSCAN_EN_1 12 12 ixPB1_RX_LANE1_SCI_STAT_OVRD_REG0 2 0x16488 6 0 4294967295 ELECIDLEDETEN_1 3 3 ENABLEFOM_1 7 7 REQUESTFOM_1 8 8 RESPONSEMODE_1 9 9 RXPRESETHINT_1 4 6 RXPWR_1 0 2 ixPB1_RX_LANE2_CTRL_REG0 2 0x16500 4 0 4294967295 RX_BACKUP_2 0 7 RX_CFG_OVR_PWRSF_2 13 13 RX_DBG_ANALOG_SEL_2 10 11 RX_TST_BSCAN_EN_2 12 12 ixPB1_RX_LANE2_SCI_STAT_OVRD_REG0 2 0x16508 6 0 4294967295 ELECIDLEDETEN_2 3 3 ENABLEFOM_2 7 7 REQUESTFOM_2 8 8 RESPONSEMODE_2 9 9 RXPRESETHINT_2 4 6 RXPWR_2 0 2 ixPB1_RX_LANE3_CTRL_REG0 2 0x16600 4 0 4294967295 RX_BACKUP_3 0 7 RX_CFG_OVR_PWRSF_3 13 13 RX_DBG_ANALOG_SEL_3 10 11 RX_TST_BSCAN_EN_3 12 12 ixPB1_RX_LANE3_SCI_STAT_OVRD_REG0 2 0x16608 6 0 4294967295 ELECIDLEDETEN_3 3 3 ENABLEFOM_3 7 7 REQUESTFOM_3 8 8 RESPONSEMODE_3 9 9 RXPRESETHINT_3 4 6 RXPWR_3 0 2 ixPB1_RX_LANE4_CTRL_REG0 2 0x16800 4 0 4294967295 RX_BACKUP_4 0 7 RX_CFG_OVR_PWRSF_4 13 13 RX_DBG_ANALOG_SEL_4 10 11 RX_TST_BSCAN_EN_4 12 12 ixPB1_RX_LANE4_SCI_STAT_OVRD_REG0 2 0x16848 6 0 4294967295 ELECIDLEDETEN_4 3 3 ENABLEFOM_4 7 7 REQUESTFOM_4 8 8 RESPONSEMODE_4 9 9 RXPRESETHINT_4 4 6 RXPWR_4 0 2 ixPB1_RX_LANE5_CTRL_REG0 2 0x16880 4 0 4294967295 RX_BACKUP_5 0 7 RX_CFG_OVR_PWRSF_5 13 13 RX_DBG_ANALOG_SEL_5 10 11 RX_TST_BSCAN_EN_5 12 12 ixPB1_RX_LANE5_SCI_STAT_OVRD_REG0 2 0x16888 6 0 4294967295 ELECIDLEDETEN_5 3 3 ENABLEFOM_5 7 7 REQUESTFOM_5 8 8 RESPONSEMODE_5 9 9 RXPRESETHINT_5 4 6 RXPWR_5 0 2 ixPB1_RX_LANE6_CTRL_REG0 2 0x16900 4 0 4294967295 RX_BACKUP_6 0 7 RX_CFG_OVR_PWRSF_6 13 13 RX_DBG_ANALOG_SEL_6 10 11 RX_TST_BSCAN_EN_6 12 12 ixPB1_RX_LANE6_SCI_STAT_OVRD_REG0 2 0x16908 6 0 4294967295 ELECIDLEDETEN_6 3 3 ENABLEFOM_6 7 7 REQUESTFOM_6 8 8 RESPONSEMODE_6 9 9 RXPRESETHINT_6 4 6 RXPWR_6 0 2 ixPB1_RX_LANE7_CTRL_REG0 2 0x16a00 4 0 4294967295 RX_BACKUP_7 0 7 RX_CFG_OVR_PWRSF_7 13 13 RX_DBG_ANALOG_SEL_7 10 11 RX_TST_BSCAN_EN_7 12 12 ixPB1_RX_LANE7_SCI_STAT_OVRD_REG0 2 0x16a08 6 0 4294967295 ELECIDLEDETEN_7 3 3 ENABLEFOM_7 7 7 REQUESTFOM_7 8 8 RESPONSEMODE_7 9 9 RXPRESETHINT_7 4 6 RXPWR_7 0 2 ixPB1_RX_LANE8_CTRL_REG0 2 0x17440 4 0 4294967295 RX_BACKUP_8 0 7 RX_CFG_OVR_PWRSF_8 13 13 RX_DBG_ANALOG_SEL_8 10 11 RX_TST_BSCAN_EN_8 12 12 ixPB1_RX_LANE8_SCI_STAT_OVRD_REG0 2 0x17448 6 0 4294967295 ELECIDLEDETEN_8 3 3 ENABLEFOM_8 7 7 REQUESTFOM_8 8 8 RESPONSEMODE_8 9 9 RXPRESETHINT_8 4 6 RXPWR_8 0 2 ixPB1_RX_LANE9_CTRL_REG0 2 0x17480 4 0 4294967295 RX_BACKUP_9 0 7 RX_CFG_OVR_PWRSF_9 13 13 RX_DBG_ANALOG_SEL_9 10 11 RX_TST_BSCAN_EN_9 12 12 ixPB1_RX_LANE9_SCI_STAT_OVRD_REG0 2 0x17488 6 0 4294967295 ELECIDLEDETEN_9 3 3 ENABLEFOM_9 7 7 REQUESTFOM_9 8 8 RESPONSEMODE_9 9 9 RXPRESETHINT_9 4 6 RXPWR_9 0 2 ixPB1_STRAP_GLB_REG0 2 0x12020 1 0 4294967295 STRAP_DBG_RXDLL_VREG_REF_SEL 15 15 ixPB1_STRAP_PLL_REG0 2 0x12030 0 0 4294967295 ixPB1_STRAP_RX_REG0 2 0x12028 0 0 4294967295 ixPB1_STRAP_RX_REG1 2 0x1202c 0 0 4294967295 ixPB1_STRAP_TX_REG0 2 0x12024 0 0 4294967295 ixPB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0 2 0x18014 32 0 4294967295 ACCEPT_ENTRY_0 0 0 ACCEPT_ENTRY_10 10 10 ACCEPT_ENTRY_11 11 11 ACCEPT_ENTRY_12 12 12 ACCEPT_ENTRY_13 13 13 ACCEPT_ENTRY_14 14 14 ACCEPT_ENTRY_15 15 15 ACCEPT_ENTRY_16 16 16 ACCEPT_ENTRY_17 17 17 ACCEPT_ENTRY_18 18 18 ACCEPT_ENTRY_19 19 19 ACCEPT_ENTRY_1 1 1 ACCEPT_ENTRY_20 20 20 ACCEPT_ENTRY_21 21 21 ACCEPT_ENTRY_22 22 22 ACCEPT_ENTRY_23 23 23 ACCEPT_ENTRY_24 24 24 ACCEPT_ENTRY_25 25 25 ACCEPT_ENTRY_26 26 26 ACCEPT_ENTRY_27 27 27 ACCEPT_ENTRY_28 28 28 ACCEPT_ENTRY_29 29 29 ACCEPT_ENTRY_2 2 2 ACCEPT_ENTRY_30 30 30 ACCEPT_ENTRY_31 31 31 ACCEPT_ENTRY_3 3 3 ACCEPT_ENTRY_4 4 4 ACCEPT_ENTRY_5 5 5 ACCEPT_ENTRY_6 6 6 ACCEPT_ENTRY_7 7 7 ACCEPT_ENTRY_8 8 8 ACCEPT_ENTRY_9 9 9 ixPB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1 2 0x18018 32 0 4294967295 ACCEPT_ENTRY_32 0 0 ACCEPT_ENTRY_33 1 1 ACCEPT_ENTRY_34 2 2 ACCEPT_ENTRY_35 3 3 ACCEPT_ENTRY_36 4 4 ACCEPT_ENTRY_37 5 5 ACCEPT_ENTRY_38 6 6 ACCEPT_ENTRY_39 7 7 ACCEPT_ENTRY_40 8 8 ACCEPT_ENTRY_41 9 9 ACCEPT_ENTRY_42 10 10 ACCEPT_ENTRY_43 11 11 ACCEPT_ENTRY_44 12 12 ACCEPT_ENTRY_45 13 13 ACCEPT_ENTRY_46 14 14 ACCEPT_ENTRY_47 15 15 ACCEPT_ENTRY_48 16 16 ACCEPT_ENTRY_49 17 17 ACCEPT_ENTRY_50 18 18 ACCEPT_ENTRY_51 19 19 ACCEPT_ENTRY_52 20 20 ACCEPT_ENTRY_53 21 21 ACCEPT_ENTRY_54 22 22 ACCEPT_ENTRY_55 23 23 ACCEPT_ENTRY_56 24 24 ACCEPT_ENTRY_57 25 25 ACCEPT_ENTRY_58 26 26 ACCEPT_ENTRY_59 27 27 ACCEPT_ENTRY_60 28 28 ACCEPT_ENTRY_61 29 29 ACCEPT_ENTRY_62 30 30 ACCEPT_ENTRY_63 31 31 ixPB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2 2 0x1801c 32 0 4294967295 ACCEPT_ENTRY_64 0 0 ACCEPT_ENTRY_65 1 1 ACCEPT_ENTRY_66 2 2 ACCEPT_ENTRY_67 3 3 ACCEPT_ENTRY_68 4 4 ACCEPT_ENTRY_69 5 5 ACCEPT_ENTRY_70 6 6 ACCEPT_ENTRY_71 7 7 ACCEPT_ENTRY_72 8 8 ACCEPT_ENTRY_73 9 9 ACCEPT_ENTRY_74 10 10 ACCEPT_ENTRY_75 11 11 ACCEPT_ENTRY_76 12 12 ACCEPT_ENTRY_77 13 13 ACCEPT_ENTRY_78 14 14 ACCEPT_ENTRY_79 15 15 ACCEPT_ENTRY_80 16 16 ACCEPT_ENTRY_81 17 17 ACCEPT_ENTRY_82 18 18 ACCEPT_ENTRY_83 19 19 ACCEPT_ENTRY_84 20 20 ACCEPT_ENTRY_85 21 21 ACCEPT_ENTRY_86 22 22 ACCEPT_ENTRY_87 23 23 ACCEPT_ENTRY_88 24 24 ACCEPT_ENTRY_89 25 25 ACCEPT_ENTRY_90 26 26 ACCEPT_ENTRY_91 27 27 ACCEPT_ENTRY_92 28 28 ACCEPT_ENTRY_93 29 29 ACCEPT_ENTRY_94 30 30 ACCEPT_ENTRY_95 31 31 ixPB1_TX_GLB_COEFF_ACCEPT_TABLE_REG3 2 0x18020 14 0 4294967295 ACCEPT_ENTRY_100 4 4 ACCEPT_ENTRY_101 5 5 ACCEPT_ENTRY_102 6 6 ACCEPT_ENTRY_103 7 7 ACCEPT_ENTRY_104 8 8 ACCEPT_ENTRY_105 9 9 ACCEPT_ENTRY_106 10 10 ACCEPT_ENTRY_107 11 11 ACCEPT_ENTRY_108 12 12 ACCEPT_ENTRY_109 13 13 ACCEPT_ENTRY_96 0 0 ACCEPT_ENTRY_97 1 1 ACCEPT_ENTRY_98 2 2 ACCEPT_ENTRY_99 3 3 ixPB1_TX_GLB_CTRL_REG0 2 0x18000 12 0 4294967295 TX_CFG_RPTR_RST_VAL_GEN1 8 10 TX_CFG_RPTR_RST_VAL_GEN2 11 13 TX_CFG_RPTR_RST_VAL_GEN3 14 16 TX_COEFF_ROUND_DIR_VER 22 22 TX_COEFF_ROUND_EN 21 21 TX_DATA_CLK_GATING 19 19 TX_DCLK_EN_LSX_ALWAYS_ON 23 23 TX_DRV_DATA_ASRT_DLY_VAL 0 2 TX_DRV_DATA_DSRT_DLY_VAL 3 5 TX_FRONTEND_PWRON_IN_OFF 24 24 TX_PRESET_TABLE_BYPASS 20 20 TX_STAGGER_CTRL 17 18 ixPB1_TX_GLB_LANE_SKEW_CTRL 2 0x18004 31 0 4294967295 TX_CFG_GROUPX16_EN_L0T15 30 30 TX_CFG_GROUPX1_EN_0 0 0 TX_CFG_GROUPX1_EN_10 10 10 TX_CFG_GROUPX1_EN_11 11 11 TX_CFG_GROUPX1_EN_12 12 12 TX_CFG_GROUPX1_EN_13 13 13 TX_CFG_GROUPX1_EN_14 14 14 TX_CFG_GROUPX1_EN_15 15 15 TX_CFG_GROUPX1_EN_1 1 1 TX_CFG_GROUPX1_EN_2 2 2 TX_CFG_GROUPX1_EN_3 3 3 TX_CFG_GROUPX1_EN_4 4 4 TX_CFG_GROUPX1_EN_5 5 5 TX_CFG_GROUPX1_EN_6 6 6 TX_CFG_GROUPX1_EN_7 7 7 TX_CFG_GROUPX1_EN_8 8 8 TX_CFG_GROUPX1_EN_9 9 9 TX_CFG_GROUPX2_EN_L0T1 16 16 TX_CFG_GROUPX2_EN_L10T11 21 21 TX_CFG_GROUPX2_EN_L12T13 22 22 TX_CFG_GROUPX2_EN_L14T15 23 23 TX_CFG_GROUPX2_EN_L2T3 17 17 TX_CFG_GROUPX2_EN_L4T5 18 18 TX_CFG_GROUPX2_EN_L6T7 19 19 TX_CFG_GROUPX2_EN_L8T9 20 20 TX_CFG_GROUPX4_EN_L0T3 24 24 TX_CFG_GROUPX4_EN_L12T15 27 27 TX_CFG_GROUPX4_EN_L4T7 25 25 TX_CFG_GROUPX4_EN_L8T11 26 26 TX_CFG_GROUPX8_EN_L0T7 28 28 TX_CFG_GROUPX8_EN_L8T15 29 29 ixPB1_TX_GLB_OVRD_REG0 2 0x18030 12 0 4294967295 TX_CFG_DCLK_DIV_OVRD_EN 3 3 TX_CFG_DCLK_DIV_OVRD_VAL 0 2 TX_CFG_DRV0_EN_GEN1_OVRD_VAL 4 7 TX_CFG_DRV0_EN_OVRD_EN 8 8 TX_CFG_DRV0_TAP_SEL_GEN1_OVRD_VAL 9 12 TX_CFG_DRV0_TAP_SEL_OVRD_EN 13 13 TX_CFG_DRV1_EN_GEN1_OVRD_VAL 14 18 TX_CFG_DRV1_EN_OVRD_EN 19 19 TX_CFG_DRV1_TAP_SEL_GEN1_OVRD_VAL 20 24 TX_CFG_DRV1_TAP_SEL_OVRD_EN 25 25 TX_CFG_DRV2_EN_GEN1_OVRD_VAL 26 29 TX_CFG_DRV2_EN_OVRD_EN 30 30 ixPB1_TX_GLB_OVRD_REG1 2 0x18034 20 0 4294967295 TX_CFG_DRV2_TAP_SEL_GEN1_OVRD_VAL 0 3 TX_CFG_DRV2_TAP_SEL_OVRD_EN 4 4 TX_CFG_DRVX_EN_GEN1_OVRD_VAL 5 5 TX_CFG_DRVX_EN_OVRD_EN 6 6 TX_CFG_DRVX_TAP_SEL_GEN1_OVRD_VAL 7 7 TX_CFG_DRVX_TAP_SEL_OVRD_EN 8 8 TX_CFG_PLLCLK_SEL_OVRD_EN 10 10 TX_CFG_PLLCLK_SEL_OVRD_VAL 9 9 TX_CFG_TCLK_DIV_OVRD_EN 12 12 TX_CFG_TCLK_DIV_OVRD_VAL 11 11 TX_CMDET_EN_OVRD_EN 14 14 TX_CMDET_EN_OVRD_VAL 13 13 TX_DATA_IN_OVRD_EN 25 25 TX_DATA_IN_OVRD_VAL 15 24 TX_RPTR_RSTN_OVRD_EN 27 27 TX_RPTR_RSTN_OVRD_VAL 26 26 TX_RXDET_EN_OVRD_EN 29 29 TX_RXDET_EN_OVRD_VAL 28 28 TX_WPTR_RSTN_OVRD_EN 31 31 TX_WPTR_RSTN_OVRD_VAL 30 30 ixPB1_TX_GLB_OVRD_REG2 2 0x18038 16 0 4294967295 TX_CFG_DRV0_EN_GEN2_OVRD_VAL 12 15 TX_CFG_DRV0_TAP_SEL_GEN2_OVRD_VAL 16 19 TX_CFG_DRV1_EN_GEN2_OVRD_VAL 20 24 TX_CFG_DRV1_TAP_SEL_GEN2_OVRD_VAL 25 29 TX_CFG_GROUPX16_EN_OVRD_EN 11 11 TX_CFG_GROUPX16_EN_OVRD_VAL 10 10 TX_CFG_GROUPX1_EN_OVRD_EN 3 3 TX_CFG_GROUPX1_EN_OVRD_VAL 2 2 TX_CFG_GROUPX2_EN_OVRD_EN 5 5 TX_CFG_GROUPX2_EN_OVRD_VAL 4 4 TX_CFG_GROUPX4_EN_OVRD_EN 7 7 TX_CFG_GROUPX4_EN_OVRD_VAL 6 6 TX_CFG_GROUPX8_EN_OVRD_EN 9 9 TX_CFG_GROUPX8_EN_OVRD_VAL 8 8 TX_WRITE_EN_OVRD_EN 1 1 TX_WRITE_EN_OVRD_VAL 0 0 ixPB1_TX_GLB_OVRD_REG3 2 0x1803c 9 0 4294967295 TX_CFG_DRV0_EN_GEN3_OVRD_VAL 10 13 TX_CFG_DRV0_TAP_SEL_GEN3_OVRD_VAL 14 17 TX_CFG_DRV1_EN_GEN3_OVRD_VAL 18 22 TX_CFG_DRV1_TAP_SEL_GEN3_OVRD_VAL 23 27 TX_CFG_DRV2_EN_GEN2_OVRD_VAL 0 3 TX_CFG_DRV2_EN_GEN3_OVRD_VAL 28 31 TX_CFG_DRV2_TAP_SEL_GEN2_OVRD_VAL 4 7 TX_CFG_DRVX_EN_GEN2_OVRD_VAL 8 8 TX_CFG_DRVX_TAP_SEL_GEN2_OVRD_VAL 9 9 ixPB1_TX_GLB_OVRD_REG4 2 0x18040 3 0 4294967295 TX_CFG_DRV2_TAP_SEL_GEN3_OVRD_VAL 0 3 TX_CFG_DRVX_EN_GEN3_OVRD_VAL 4 4 TX_CFG_DRVX_TAP_SEL_GEN3_OVRD_VAL 5 5 ixPB1_TX_GLB_SCI_STAT_OVRD_REG0 2 0x18010 16 0 4294967295 IGNR_COEFFICIENTID_SCI_UPDT_L0T3 8 8 IGNR_COEFFICIENTID_SCI_UPDT_L12T15 11 11 IGNR_COEFFICIENTID_SCI_UPDT_L4T7 9 9 IGNR_COEFFICIENTID_SCI_UPDT_L8T11 10 10 IGNR_COEFFICIENT_SCI_UPDT_L0T3 12 12 IGNR_COEFFICIENT_SCI_UPDT_L12T15 15 15 IGNR_COEFFICIENT_SCI_UPDT_L4T7 13 13 IGNR_COEFFICIENT_SCI_UPDT_L8T11 14 14 IGNR_INCOHERENTCK_SCI_UPDT_L0T3 4 4 IGNR_INCOHERENTCK_SCI_UPDT_L12T15 7 7 IGNR_INCOHERENTCK_SCI_UPDT_L4T7 5 5 IGNR_INCOHERENTCK_SCI_UPDT_L8T11 6 6 IGNR_TXPWR_SCI_UPDT_L0T3 0 0 IGNR_TXPWR_SCI_UPDT_L12T15 3 3 IGNR_TXPWR_SCI_UPDT_L4T7 1 1 IGNR_TXPWR_SCI_UPDT_L8T11 2 2 ixPB1_TX_LANE0_CTRL_REG0 2 0x18440 4 0 4294967295 TX_CFG_DISPCLK_MODE_0 0 0 TX_CFG_INV_DATA_0 1 1 TX_CFG_SWING_BOOST_EN_0 2 2 TX_DBG_PRBS_EN_0 3 3 ixPB1_TX_LANE0_OVRD_REG0 2 0x18444 8 0 4294967295 TX_DCLK_EN_OVRD_EN_0 1 1 TX_DCLK_EN_OVRD_VAL_0 0 0 TX_DRV_DATA_EN_OVRD_EN_0 3 3 TX_DRV_DATA_EN_OVRD_VAL_0 2 2 TX_DRV_PWRON_OVRD_EN_0 5 5 TX_DRV_PWRON_OVRD_VAL_0 4 4 TX_FRONTEND_PWRON_OVRD_EN_0 7 7 TX_FRONTEND_PWRON_OVRD_VAL_0 6 6 ixPB1_TX_LANE0_SCI_STAT_OVRD_REG0 2 0x18448 6 0 4294967295 COEFFICIENT_0 10 15 COEFFICIENTID_0 8 9 DEEMPH_0 7 7 INCOHERENTCK_0 3 3 TXMARG_0 4 6 TXPWR_0 0 2 ixPB1_TX_LANE10_CTRL_REG0 2 0x19500 4 0 4294967295 TX_CFG_DISPCLK_MODE_10 0 0 TX_CFG_INV_DATA_10 1 1 TX_CFG_SWING_BOOST_EN_10 2 2 TX_DBG_PRBS_EN_10 3 3 ixPB1_TX_LANE10_OVRD_REG0 2 0x19504 8 0 4294967295 TX_DCLK_EN_OVRD_EN_10 1 1 TX_DCLK_EN_OVRD_VAL_10 0 0 TX_DRV_DATA_EN_OVRD_EN_10 3 3 TX_DRV_DATA_EN_OVRD_VAL_10 2 2 TX_DRV_PWRON_OVRD_EN_10 5 5 TX_DRV_PWRON_OVRD_VAL_10 4 4 TX_FRONTEND_PWRON_OVRD_EN_10 7 7 TX_FRONTEND_PWRON_OVRD_VAL_10 6 6 ixPB1_TX_LANE10_SCI_STAT_OVRD_REG0 2 0x19508 6 0 4294967295 COEFFICIENT_10 10 15 COEFFICIENTID_10 8 9 DEEMPH_10 7 7 INCOHERENTCK_10 3 3 TXMARG_10 4 6 TXPWR_10 0 2 ixPB1_TX_LANE11_CTRL_REG0 2 0x19600 4 0 4294967295 TX_CFG_DISPCLK_MODE_11 0 0 TX_CFG_INV_DATA_11 1 1 TX_CFG_SWING_BOOST_EN_11 2 2 TX_DBG_PRBS_EN_11 3 3 ixPB1_TX_LANE11_OVRD_REG0 2 0x19604 8 0 4294967295 TX_DCLK_EN_OVRD_EN_11 1 1 TX_DCLK_EN_OVRD_VAL_11 0 0 TX_DRV_DATA_EN_OVRD_EN_11 3 3 TX_DRV_DATA_EN_OVRD_VAL_11 2 2 TX_DRV_PWRON_OVRD_EN_11 5 5 TX_DRV_PWRON_OVRD_VAL_11 4 4 TX_FRONTEND_PWRON_OVRD_EN_11 7 7 TX_FRONTEND_PWRON_OVRD_VAL_11 6 6 ixPB1_TX_LANE11_SCI_STAT_OVRD_REG0 2 0x19608 6 0 4294967295 COEFFICIENT_11 10 15 COEFFICIENTID_11 8 9 DEEMPH_11 7 7 INCOHERENTCK_11 3 3 TXMARG_11 4 6 TXPWR_11 0 2 ixPB1_TX_LANE12_CTRL_REG0 2 0x19840 4 0 4294967295 TX_CFG_DISPCLK_MODE_12 0 0 TX_CFG_INV_DATA_12 1 1 TX_CFG_SWING_BOOST_EN_12 2 2 TX_DBG_PRBS_EN_12 3 3 ixPB1_TX_LANE12_OVRD_REG0 2 0x19844 8 0 4294967295 TX_DCLK_EN_OVRD_EN_12 1 1 TX_DCLK_EN_OVRD_VAL_12 0 0 TX_DRV_DATA_EN_OVRD_EN_12 3 3 TX_DRV_DATA_EN_OVRD_VAL_12 2 2 TX_DRV_PWRON_OVRD_EN_12 5 5 TX_DRV_PWRON_OVRD_VAL_12 4 4 TX_FRONTEND_PWRON_OVRD_EN_12 7 7 TX_FRONTEND_PWRON_OVRD_VAL_12 6 6 ixPB1_TX_LANE12_SCI_STAT_OVRD_REG0 2 0x19848 6 0 4294967295 COEFFICIENT_12 10 15 COEFFICIENTID_12 8 9 DEEMPH_12 7 7 INCOHERENTCK_12 3 3 TXMARG_12 4 6 TXPWR_12 0 2 ixPB1_TX_LANE13_CTRL_REG0 2 0x19880 4 0 4294967295 TX_CFG_DISPCLK_MODE_13 0 0 TX_CFG_INV_DATA_13 1 1 TX_CFG_SWING_BOOST_EN_13 2 2 TX_DBG_PRBS_EN_13 3 3 ixPB1_TX_LANE13_OVRD_REG0 2 0x19884 8 0 4294967295 TX_DCLK_EN_OVRD_EN_13 1 1 TX_DCLK_EN_OVRD_VAL_13 0 0 TX_DRV_DATA_EN_OVRD_EN_13 3 3 TX_DRV_DATA_EN_OVRD_VAL_13 2 2 TX_DRV_PWRON_OVRD_EN_13 5 5 TX_DRV_PWRON_OVRD_VAL_13 4 4 TX_FRONTEND_PWRON_OVRD_EN_13 7 7 TX_FRONTEND_PWRON_OVRD_VAL_13 6 6 ixPB1_TX_LANE13_SCI_STAT_OVRD_REG0 2 0x19888 6 0 4294967295 COEFFICIENT_13 10 15 COEFFICIENTID_13 8 9 DEEMPH_13 7 7 INCOHERENTCK_13 3 3 TXMARG_13 4 6 TXPWR_13 0 2 ixPB1_TX_LANE14_CTRL_REG0 2 0x19900 4 0 4294967295 TX_CFG_DISPCLK_MODE_14 0 0 TX_CFG_INV_DATA_14 1 1 TX_CFG_SWING_BOOST_EN_14 2 2 TX_DBG_PRBS_EN_14 3 3 ixPB1_TX_LANE14_OVRD_REG0 2 0x19904 8 0 4294967295 TX_DCLK_EN_OVRD_EN_14 1 1 TX_DCLK_EN_OVRD_VAL_14 0 0 TX_DRV_DATA_EN_OVRD_EN_14 3 3 TX_DRV_DATA_EN_OVRD_VAL_14 2 2 TX_DRV_PWRON_OVRD_EN_14 5 5 TX_DRV_PWRON_OVRD_VAL_14 4 4 TX_FRONTEND_PWRON_OVRD_EN_14 7 7 TX_FRONTEND_PWRON_OVRD_VAL_14 6 6 ixPB1_TX_LANE14_SCI_STAT_OVRD_REG0 2 0x19908 6 0 4294967295 COEFFICIENT_14 10 15 COEFFICIENTID_14 8 9 DEEMPH_14 7 7 INCOHERENTCK_14 3 3 TXMARG_14 4 6 TXPWR_14 0 2 ixPB1_TX_LANE15_CTRL_REG0 2 0x19a00 4 0 4294967295 TX_CFG_DISPCLK_MODE_15 0 0 TX_CFG_INV_DATA_15 1 1 TX_CFG_SWING_BOOST_EN_15 2 2 TX_DBG_PRBS_EN_15 3 3 ixPB1_TX_LANE15_OVRD_REG0 2 0x19a04 8 0 4294967295 TX_DCLK_EN_OVRD_EN_15 1 1 TX_DCLK_EN_OVRD_VAL_15 0 0 TX_DRV_DATA_EN_OVRD_EN_15 3 3 TX_DRV_DATA_EN_OVRD_VAL_15 2 2 TX_DRV_PWRON_OVRD_EN_15 5 5 TX_DRV_PWRON_OVRD_VAL_15 4 4 TX_FRONTEND_PWRON_OVRD_EN_15 7 7 TX_FRONTEND_PWRON_OVRD_VAL_15 6 6 ixPB1_TX_LANE15_SCI_STAT_OVRD_REG0 2 0x19a08 6 0 4294967295 COEFFICIENT_15 10 15 COEFFICIENTID_15 8 9 DEEMPH_15 7 7 INCOHERENTCK_15 3 3 TXMARG_15 4 6 TXPWR_15 0 2 ixPB1_TX_LANE1_CTRL_REG0 2 0x18480 4 0 4294967295 TX_CFG_DISPCLK_MODE_1 0 0 TX_CFG_INV_DATA_1 1 1 TX_CFG_SWING_BOOST_EN_1 2 2 TX_DBG_PRBS_EN_1 3 3 ixPB1_TX_LANE1_OVRD_REG0 2 0x18484 8 0 4294967295 TX_DCLK_EN_OVRD_EN_1 1 1 TX_DCLK_EN_OVRD_VAL_1 0 0 TX_DRV_DATA_EN_OVRD_EN_1 3 3 TX_DRV_DATA_EN_OVRD_VAL_1 2 2 TX_DRV_PWRON_OVRD_EN_1 5 5 TX_DRV_PWRON_OVRD_VAL_1 4 4 TX_FRONTEND_PWRON_OVRD_EN_1 7 7 TX_FRONTEND_PWRON_OVRD_VAL_1 6 6 ixPB1_TX_LANE1_SCI_STAT_OVRD_REG0 2 0x18488 6 0 4294967295 COEFFICIENT_1 10 15 COEFFICIENTID_1 8 9 DEEMPH_1 7 7 INCOHERENTCK_1 3 3 TXMARG_1 4 6 TXPWR_1 0 2 ixPB1_TX_LANE2_CTRL_REG0 2 0x18500 4 0 4294967295 TX_CFG_DISPCLK_MODE_2 0 0 TX_CFG_INV_DATA_2 1 1 TX_CFG_SWING_BOOST_EN_2 2 2 TX_DBG_PRBS_EN_2 3 3 ixPB1_TX_LANE2_OVRD_REG0 2 0x18504 8 0 4294967295 TX_DCLK_EN_OVRD_EN_2 1 1 TX_DCLK_EN_OVRD_VAL_2 0 0 TX_DRV_DATA_EN_OVRD_EN_2 3 3 TX_DRV_DATA_EN_OVRD_VAL_2 2 2 TX_DRV_PWRON_OVRD_EN_2 5 5 TX_DRV_PWRON_OVRD_VAL_2 4 4 TX_FRONTEND_PWRON_OVRD_EN_2 7 7 TX_FRONTEND_PWRON_OVRD_VAL_2 6 6 ixPB1_TX_LANE2_SCI_STAT_OVRD_REG0 2 0x18508 6 0 4294967295 COEFFICIENT_2 10 15 COEFFICIENTID_2 8 9 DEEMPH_2 7 7 INCOHERENTCK_2 3 3 TXMARG_2 4 6 TXPWR_2 0 2 ixPB1_TX_LANE3_CTRL_REG0 2 0x18600 4 0 4294967295 TX_CFG_DISPCLK_MODE_3 0 0 TX_CFG_INV_DATA_3 1 1 TX_CFG_SWING_BOOST_EN_3 2 2 TX_DBG_PRBS_EN_3 3 3 ixPB1_TX_LANE3_OVRD_REG0 2 0x18604 8 0 4294967295 TX_DCLK_EN_OVRD_EN_3 1 1 TX_DCLK_EN_OVRD_VAL_3 0 0 TX_DRV_DATA_EN_OVRD_EN_3 3 3 TX_DRV_DATA_EN_OVRD_VAL_3 2 2 TX_DRV_PWRON_OVRD_EN_3 5 5 TX_DRV_PWRON_OVRD_VAL_3 4 4 TX_FRONTEND_PWRON_OVRD_EN_3 7 7 TX_FRONTEND_PWRON_OVRD_VAL_3 6 6 ixPB1_TX_LANE3_SCI_STAT_OVRD_REG0 2 0x18608 6 0 4294967295 COEFFICIENT_3 10 15 COEFFICIENTID_3 8 9 DEEMPH_3 7 7 INCOHERENTCK_3 3 3 TXMARG_3 4 6 TXPWR_3 0 2 ixPB1_TX_LANE4_CTRL_REG0 2 0x18840 4 0 4294967295 TX_CFG_DISPCLK_MODE_4 0 0 TX_CFG_INV_DATA_4 1 1 TX_CFG_SWING_BOOST_EN_4 2 2 TX_DBG_PRBS_EN_4 3 3 ixPB1_TX_LANE4_OVRD_REG0 2 0x18844 8 0 4294967295 TX_DCLK_EN_OVRD_EN_4 1 1 TX_DCLK_EN_OVRD_VAL_4 0 0 TX_DRV_DATA_EN_OVRD_EN_4 3 3 TX_DRV_DATA_EN_OVRD_VAL_4 2 2 TX_DRV_PWRON_OVRD_EN_4 5 5 TX_DRV_PWRON_OVRD_VAL_4 4 4 TX_FRONTEND_PWRON_OVRD_EN_4 7 7 TX_FRONTEND_PWRON_OVRD_VAL_4 6 6 ixPB1_TX_LANE4_SCI_STAT_OVRD_REG0 2 0x18848 6 0 4294967295 COEFFICIENT_4 10 15 COEFFICIENTID_4 8 9 DEEMPH_4 7 7 INCOHERENTCK_4 3 3 TXMARG_4 4 6 TXPWR_4 0 2 ixPB1_TX_LANE5_CTRL_REG0 2 0x18880 4 0 4294967295 TX_CFG_DISPCLK_MODE_5 0 0 TX_CFG_INV_DATA_5 1 1 TX_CFG_SWING_BOOST_EN_5 2 2 TX_DBG_PRBS_EN_5 3 3 ixPB1_TX_LANE5_OVRD_REG0 2 0x18884 8 0 4294967295 TX_DCLK_EN_OVRD_EN_5 1 1 TX_DCLK_EN_OVRD_VAL_5 0 0 TX_DRV_DATA_EN_OVRD_EN_5 3 3 TX_DRV_DATA_EN_OVRD_VAL_5 2 2 TX_DRV_PWRON_OVRD_EN_5 5 5 TX_DRV_PWRON_OVRD_VAL_5 4 4 TX_FRONTEND_PWRON_OVRD_EN_5 7 7 TX_FRONTEND_PWRON_OVRD_VAL_5 6 6 ixPB1_TX_LANE5_SCI_STAT_OVRD_REG0 2 0x18888 6 0 4294967295 COEFFICIENT_5 10 15 COEFFICIENTID_5 8 9 DEEMPH_5 7 7 INCOHERENTCK_5 3 3 TXMARG_5 4 6 TXPWR_5 0 2 ixPB1_TX_LANE6_CTRL_REG0 2 0x18900 4 0 4294967295 TX_CFG_DISPCLK_MODE_6 0 0 TX_CFG_INV_DATA_6 1 1 TX_CFG_SWING_BOOST_EN_6 2 2 TX_DBG_PRBS_EN_6 3 3 ixPB1_TX_LANE6_OVRD_REG0 2 0x18904 8 0 4294967295 TX_DCLK_EN_OVRD_EN_6 1 1 TX_DCLK_EN_OVRD_VAL_6 0 0 TX_DRV_DATA_EN_OVRD_EN_6 3 3 TX_DRV_DATA_EN_OVRD_VAL_6 2 2 TX_DRV_PWRON_OVRD_EN_6 5 5 TX_DRV_PWRON_OVRD_VAL_6 4 4 TX_FRONTEND_PWRON_OVRD_EN_6 7 7 TX_FRONTEND_PWRON_OVRD_VAL_6 6 6 ixPB1_TX_LANE6_SCI_STAT_OVRD_REG0 2 0x18908 6 0 4294967295 COEFFICIENT_6 10 15 COEFFICIENTID_6 8 9 DEEMPH_6 7 7 INCOHERENTCK_6 3 3 TXMARG_6 4 6 TXPWR_6 0 2 ixPB1_TX_LANE7_CTRL_REG0 2 0x18a00 4 0 4294967295 TX_CFG_DISPCLK_MODE_7 0 0 TX_CFG_INV_DATA_7 1 1 TX_CFG_SWING_BOOST_EN_7 2 2 TX_DBG_PRBS_EN_7 3 3 ixPB1_TX_LANE7_OVRD_REG0 2 0x18a04 8 0 4294967295 TX_DCLK_EN_OVRD_EN_7 1 1 TX_DCLK_EN_OVRD_VAL_7 0 0 TX_DRV_DATA_EN_OVRD_EN_7 3 3 TX_DRV_DATA_EN_OVRD_VAL_7 2 2 TX_DRV_PWRON_OVRD_EN_7 5 5 TX_DRV_PWRON_OVRD_VAL_7 4 4 TX_FRONTEND_PWRON_OVRD_EN_7 7 7 TX_FRONTEND_PWRON_OVRD_VAL_7 6 6 ixPB1_TX_LANE7_SCI_STAT_OVRD_REG0 2 0x18a08 6 0 4294967295 COEFFICIENT_7 10 15 COEFFICIENTID_7 8 9 DEEMPH_7 7 7 INCOHERENTCK_7 3 3 TXMARG_7 4 6 TXPWR_7 0 2 ixPB1_TX_LANE8_CTRL_REG0 2 0x19440 4 0 4294967295 TX_CFG_DISPCLK_MODE_8 0 0 TX_CFG_INV_DATA_8 1 1 TX_CFG_SWING_BOOST_EN_8 2 2 TX_DBG_PRBS_EN_8 3 3 ixPB1_TX_LANE8_OVRD_REG0 2 0x19444 8 0 4294967295 TX_DCLK_EN_OVRD_EN_8 1 1 TX_DCLK_EN_OVRD_VAL_8 0 0 TX_DRV_DATA_EN_OVRD_EN_8 3 3 TX_DRV_DATA_EN_OVRD_VAL_8 2 2 TX_DRV_PWRON_OVRD_EN_8 5 5 TX_DRV_PWRON_OVRD_VAL_8 4 4 TX_FRONTEND_PWRON_OVRD_EN_8 7 7 TX_FRONTEND_PWRON_OVRD_VAL_8 6 6 ixPB1_TX_LANE8_SCI_STAT_OVRD_REG0 2 0x19448 6 0 4294967295 COEFFICIENT_8 10 15 COEFFICIENTID_8 8 9 DEEMPH_8 7 7 INCOHERENTCK_8 3 3 TXMARG_8 4 6 TXPWR_8 0 2 ixPB1_TX_LANE9_CTRL_REG0 2 0x19480 4 0 4294967295 TX_CFG_DISPCLK_MODE_9 0 0 TX_CFG_INV_DATA_9 1 1 TX_CFG_SWING_BOOST_EN_9 2 2 TX_DBG_PRBS_EN_9 3 3 ixPB1_TX_LANE9_OVRD_REG0 2 0x19484 8 0 4294967295 TX_DCLK_EN_OVRD_EN_9 1 1 TX_DCLK_EN_OVRD_VAL_9 0 0 TX_DRV_DATA_EN_OVRD_EN_9 3 3 TX_DRV_DATA_EN_OVRD_VAL_9 2 2 TX_DRV_PWRON_OVRD_EN_9 5 5 TX_DRV_PWRON_OVRD_VAL_9 4 4 TX_FRONTEND_PWRON_OVRD_EN_9 7 7 TX_FRONTEND_PWRON_OVRD_VAL_9 6 6 ixPB1_TX_LANE9_SCI_STAT_OVRD_REG0 2 0x19488 6 0 4294967295 COEFFICIENT_9 10 15 COEFFICIENTID_9 8 9 DEEMPH_9 7 7 INCOHERENTCK_9 3 3 TXMARG_9 4 6 TXPWR_9 0 2 ixPCIE_BUS_CNTL 2 0x21 2 0 4294967295 IMMEDIATE_PMI_DIS 7 7 PMI_INT_DIS 6 6 ixPCIE_CFG_CNTL 2 0x3c 3 0 4294967295 CFG_EN_DEC_TO_GEN2_HIDDEN_REG 0 0 CFG_EN_DEC_TO_GEN3_HIDDEN_REG 2 2 CFG_EN_DEC_TO_HIDDEN_REG 1 1 ixPCIE_CI_CNTL 2 0x20 10 0 4294967295 CI_MST_CMPL_DUMMY_DATA 4 4 CI_MST_IGNORE_PAGE_ALIGNED_REQUEST 13 13 CI_RC_ORDERING_DIS 9 9 CI_SLAVE_GEN_USR_DIS 3 3 CI_SLAVE_SPLIT_MODE 2 2 CI_SLV_CPL_ALLOC_DIS 10 10 CI_SLV_CPL_ALLOC_MODE 11 11 CI_SLV_CPL_ALLOC_SOR 12 12 CI_SLV_ORDERING_DIS 8 8 CI_SLV_RC_RD_REQ_SIZE 6 7 ixPCIE_CNTL 2 0x10 17 0 4294967295 HWINIT_WR_LOCK 0 0 LC_HOT_PLUG_DELAY_SEL 1 3 PCIE_HT_NP_MEM_WRITE 9 9 PCIE_MALFORM_ATOMIC_OPS 8 8 RX_ATS_TRAN_CPL_SPLIT_DIS 23 23 RX_CPL_POSTED_REQ_ORD_EN 31 31 RX_RCB_ATS_UC_DIS 15 15 RX_RCB_CHANNEL_ORDERING 20 20 RX_RCB_CPL_TIMEOUT_TEST_MODE 19 19 RX_RCB_INVALID_SIZE_DIS 17 17 RX_RCB_REORDER_EN 16 16 RX_RCB_UNEXP_CPL_DIS 18 18 RX_RCB_WRONG_ATTR_DIS 21 21 RX_RCB_WRONG_FUNCNUM_DIS 22 22 RX_SB_ADJ_PAYLOAD_SIZE 10 12 TX_CPL_DEBUG 24 29 UR_ERR_REPORT_DIS 7 7 ixPCIE_CNTL2 2 0x1c 12 0 4294967295 MST_MEM_LS_EN 18 18 MST_MEM_SD_EN 22 22 REPLAY_MEM_LS_EN 19 19 REPLAY_MEM_SD_EN 23 23 RX_NP_MEM_WRITE_ENCODING 24 28 SLV_MEM_AGGRESSIVE_LS_EN 17 17 SLV_MEM_AGGRESSIVE_SD_EN 21 21 SLV_MEM_LS_EN 16 16 SLV_MEM_SD_EN 20 20 TX_ARB_MST_LIMIT 6 10 TX_ARB_ROUND_ROBIN_EN 0 0 TX_ARB_SLV_LIMIT 1 5 ixPCIE_CONFIG_CNTL 2 0x11 7 0 4294967295 CI_EXTENDED_TAG_EN_OVERRIDE 25 25 CI_MAX_PAYLOAD_SIZE_MODE 16 16 CI_MAX_READ_REQUEST_SIZE_MODE 20 20 CI_MAX_READ_SAFE_MODE 24 24 CI_PRIV_MAX_PAYLOAD_SIZE 17 19 CI_PRIV_MAX_READ_REQUEST_SIZE 21 23 DYN_CLK_LATENCY 0 3 ixPCIE_DEBUG_CNTL 2 0x12 3 0 4294967295 DEBUG_LANE_EN 16 31 DEBUG_PORT_EN 0 7 DEBUG_SELECT 8 8 ixPCIE_ERR_CNTL 2 0x6a 13 0 4294967295 AER_HDR_LOG_F0_TIMER_EXPIRED 11 11 AER_HDR_LOG_F1_TIMER_EXPIRED 12 12 AER_HDR_LOG_F2_TIMER_EXPIRED 13 13 AER_HDR_LOG_TIMEOUT 8 10 CI_NP_SLV_BUF_RD_HALT_STATUS 15 15 CI_P_SLV_BUF_RD_HALT_STATUS 14 14 CI_SLV_BUF_HALT_RESET 16 16 ERR_REPORTING_DIS 0 0 RX_GENERATE_ECRC_ERR 7 7 RX_GENERATE_LCRC_ERR 5 5 STRAP_FIRST_RCVD_ERR_LOG 1 1 TX_GENERATE_ECRC_ERR 6 6 TX_GENERATE_LCRC_ERR 4 4 ixPCIE_F0_DPA_CAP 2 0xe0 4 0 4294967295 PWR_ALLOC_SCALE 12 13 TRANS_LAT_UNIT 8 9 TRANS_LAT_VAL_0 16 23 TRANS_LAT_VAL_1 24 31 ixPCIE_F0_DPA_CNTL 2 0xe5 1 0 4294967295 SUBSTATE_STATUS 0 4 ixPCIE_F0_DPA_LATENCY_INDICATOR 2 0xe4 1 0 4294967295 TRANS_LAT_INDICATOR_BITS 0 7 ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0 2 0xe7 1 0 4294967295 SUBSTATE_PWR_ALLOC 0 7 ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1 2 0xe8 1 0 4294967295 SUBSTATE_PWR_ALLOC 0 7 ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2 2 0xe9 1 0 4294967295 SUBSTATE_PWR_ALLOC 0 7 ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3 2 0xea 1 0 4294967295 SUBSTATE_PWR_ALLOC 0 7 ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4 2 0xeb 1 0 4294967295 SUBSTATE_PWR_ALLOC 0 7 ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5 2 0xec 1 0 4294967295 SUBSTATE_PWR_ALLOC 0 7 ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6 2 0xed 1 0 4294967295 SUBSTATE_PWR_ALLOC 0 7 ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7 2 0xee 1 0 4294967295 SUBSTATE_PWR_ALLOC 0 7 ixPCIE_FC_CPL 2 0x62 2 0 4294967295 CPLD_CREDITS 0 7 CPLH_CREDITS 8 15 ixPCIE_FC_NP 2 0x61 2 0 4294967295 NPD_CREDITS 0 7 NPH_CREDITS 8 15 ixPCIE_FC_P 2 0x60 2 0 4294967295 PD_CREDITS 0 7 PH_CREDITS 8 15 ixPCIE_HW_DEBUG 2 0x2 16 0 4294967295 HW_00_DEBUG 0 0 HW_01_DEBUG 1 1 HW_02_DEBUG 2 2 HW_03_DEBUG 3 3 HW_04_DEBUG 4 4 HW_05_DEBUG 5 5 HW_06_DEBUG 6 6 HW_07_DEBUG 7 7 HW_08_DEBUG 8 8 HW_09_DEBUG 9 9 HW_10_DEBUG 10 10 HW_11_DEBUG 11 11 HW_12_DEBUG 12 12 HW_13_DEBUG 13 13 HW_14_DEBUG 14 14 HW_15_DEBUG 15 15 ixPCIE_I2C_REG_ADDR_EXPAND 2 0x3a 1 0 4294967295 I2C_REG_ADDR 0 16 ixPCIE_I2C_REG_DATA 2 0x3b 1 0 4294967295 I2C_REG_DATA 0 31 ixPCIE_INT_CNTL 2 0x1a 8 0 4294967295 CORR_ERR_INT_EN 0 0 FATAL_ERR_INT_EN 2 2 LINK_BW_INT_EN 7 7 MISC_ERR_INT_EN 4 4 NON_FATAL_ERR_INT_EN 1 1 POWER_STATE_CHG_INT_EN 6 6 QUIESCE_RCVD_INT_EN 8 8 USR_DETECTED_INT_EN 3 3 ixPCIE_INT_STATUS 2 0x1b 8 0 4294967295 CORR_ERR_INT_STATUS 0 0 FATAL_ERR_INT_STATUS 2 2 LINK_BW_INT_STATUS 7 7 MISC_ERR_INT_STATUS 4 4 NON_FATAL_ERR_INT_STATUS 1 1 POWER_STATE_CHG_INT_STATUS 6 6 QUIESCE_RCVD_INT_STATUS 8 8 USR_DETECTED_INT_STATUS 3 3 ixPCIE_LC_BEST_EQ_SETTINGS 2 0xb9 5 0 4294967295 LC_BEST_CURSOR 10 15 LC_BEST_FOM 22 29 LC_BEST_POSTCURSOR 16 21 LC_BEST_PRECURSOR 4 9 LC_BEST_PRESET 0 3 ixPCIE_LC_BW_CHANGE_CNTL 2 0xb2 11 0 4294967295 LC_BW_CHANGE_INT_EN 0 0 LC_FAILED_SPEED_NEG 5 5 LC_HW_INIT_SPEED_CHANGE 1 1 LC_LINK_BW_NOTIFICATION_DETECT_MODE 10 10 LC_LONG_LW_CHANGE 6 6 LC_LW_CHANGE_FAILED 9 9 LC_LW_CHANGE_OTHER 8 8 LC_OTHER_INIT_SPEED_CHANGE 3 3 LC_RELIABILITY_SPEED_CHANGE 4 4 LC_SHORT_LW_CHANGE 7 7 LC_SW_INIT_SPEED_CHANGE 2 2 ixPCIE_LC_CDR_CNTL 2 0xb3 3 0 4294967295 LC_CDR_SET_TYPE 24 25 LC_CDR_TEST_OFF 0 11 LC_CDR_TEST_SETS 12 23 ixPCIE_LC_CNTL 2 0xa0 20 0 4294967295 LC_16X_CLEAR_TX_PIPE 4 7 LC_ASPM_TO_L1_DIS 24 24 LC_DELAY_COUNT 25 26 LC_DELAY_L0S_EXIT 27 27 LC_DELAY_L1_EXIT 28 28 LC_DONT_ENTER_L23_IN_D0 1 1 LC_ESCAPE_L1L23_EN 30 30 LC_EXTEND_WAIT_FOR_EL_IDLE 29 29 LC_FACTOR_IN_EXT_SYNC 20 20 LC_GATE_RCVR_IDLE 31 31 LC_INC_N_FTS_EN 17 17 LC_L0S_INACTIVITY 8 11 LC_L1_IMMEDIATE_ACK 23 23 LC_L1_INACTIVITY 12 15 LC_LOOK_FOR_IDLE_IN_L1L23 18 19 LC_PMI_TO_L1_DIS 16 16 LC_RESET_L_IDLE_COUNT_EN 2 2 LC_RESET_LINK 3 3 LC_WAIT_FOR_PM_ACK_DIS 21 21 LC_WAKE_FROM_L23 22 22 ixPCIE_LC_CNTL2 2 0xb1 24 0 4294967295 LC_ALLOW_PDWN_IN_L1 17 17 LC_ALLOW_PDWN_IN_L23 18 18 LC_ASSERT_INACTIVE_DURING_HOLD 22 22 LC_BLOCK_EL_IDLE_IN_L0 20 20 LC_DEASSERT_RX_EN_IN_L0S 19 19 LC_DISABLE_INFERRED_ELEC_IDLE_DET 16 16 LC_DISABLE_LOST_SYM_LOCK_ARCS 26 26 LC_ELEC_IDLE_MODE 14 15 LC_ENABLE_INFERRED_ELEC_IDLE_FOR_PI 31 31 LC_ILLEGAL_STATE 11 11 LC_ILLEGAL_STATE_RESTART_EN 12 12 LC_LINK_BW_NOTIFICATION_DIS 27 27 LC_LINK_UP_REVERSAL_EN 10 10 LC_LOOK_FOR_BW_REDUCTION 7 7 LC_MORE_TS2_EN 8 8 LC_PMI_L1_WAIT_FOR_SLV_IDLE 28 28 LC_PWR_DOWN_NEG_OFF_LANES 25 25 LC_RCV_L0_TO_RCV_L0S_DIS 21 21 LC_STATE_TIMED_OUT 6 6 LC_TEST_TIMER_SEL 29 30 LC_TIMED_OUT_STATE 0 5 LC_WAIT_FOR_LANES_IN_LW_NEG 23 24 LC_WAIT_FOR_OTHER_LANES_MODE 13 13 LC_X12_NEGOTIATION_DIS 9 9 ixPCIE_LC_CNTL3 2 0xb5 23 0 4294967295 LC_AUTO_DISABLE_SPEED_SUPPORT_EN 18 18 LC_AUTO_DISABLE_SPEED_SUPPORT_MAX_FAIL_SEL 19 20 LC_AUTO_SPEED_CHANGE_ATTEMPT_FAILED 8 8 LC_AUTO_SPEED_CHANGE_ATTEMPTS_ALLOWED 6 7 LC_CHIP_BIF_USB_IDLE_EN 16 16 LC_CLR_FAILED_AUTO_SPD_CHANGE_CNT 9 9 LC_COMP_TO_DETECT 4 4 LC_DSC_DONT_ENTER_L23_AFTER_PME_ACK 23 23 LC_EHP_RX_PHY_CMD 12 13 LC_EHP_TX_PHY_CMD 14 15 LC_ENHANCED_HOT_PLUG_EN 10 10 LC_FAST_L1_ENTRY_EXIT_EN 21 21 LC_GO_TO_RECOVERY 30 30 LC_HW_VOLTAGE_IF_CONTROL 24 25 LC_L1_BLOCK_RECONFIG_EN 17 17 LC_N_EIE_SEL 31 31 LC_RCVD_DEEMPHASIS 3 3 LC_RCVR_DET_EN_OVERRIDE 11 11 LC_RESET_TSX_CNT_IN_RLOCK_EN 5 5 LC_RXPHYCMD_INACTIVE_EN_MODE 22 22 LC_SELECT_DEEMPHASIS_CNTL 1 2 LC_SELECT_DEEMPHASIS 0 0 LC_VOLTAGE_TIMER_SEL 26 29 ixPCIE_LC_CNTL4 2 0xb6 20 0 4294967295 LC_8GT_SKIP_ORDER_EN 25 25 LC_BYPASS_EQ 4 4 LC_BYPASS_EQ_REQ_PHASE 16 16 LC_DSC_CHECK_COEFFS_IN_RLOCK 10 10 LC_EQ_SEARCH_MODE 8 9 LC_EQ_WAIT_FOR_EVAL_DONE 24 24 LC_EXTEND_EIEOS 6 6 LC_FORCE_PRESET_IN_EQ_REQ_PHASE 17 17 LC_FORCE_PRESET_VALUE 18 21 LC_IGNORE_PARITY 7 7 LC_PCIE_TX_FULL_SWING 23 23 LC_QUIESCE_RCVD 14 14 LC_REDO_EQ 5 5 LC_SET_QUIESCE 13 13 LC_TX_ENABLE_BEHAVIOUR 0 1 LC_UNEXPECTED_COEFFS_RCVD 15 15 LC_USC_DELAY_DLLPS 22 22 LC_USC_EQ_NOT_REQD 11 11 LC_USC_GO_TO_EQ 12 12 LC_WAIT_FOR_MORE_TS_IN_RLOCK 26 31 ixPCIE_LC_CNTL5 2 0xb7 4 0 4294967295 LC_EQ_FS_0 0 5 LC_EQ_FS_8 6 11 LC_EQ_LF_0 12 17 LC_EQ_LF_8 18 23 ixPCIE_LC_FORCE_COEFF 2 0xb8 5 0 4294967295 LC_3X3_COEFF_SEARCH_EN 19 19 LC_FORCE_COEFF 0 0 LC_FORCE_CURSOR 7 12 LC_FORCE_POST_CURSOR 13 18 LC_FORCE_PRE_CURSOR 1 6 ixPCIE_LC_FORCE_EQ_REQ_COEFF 2 0xba 6 0 4294967295 LC_FORCE_COEFF_IN_EQ_REQ_PHASE 0 0 LC_FORCE_CURSOR_REQ 7 12 LC_FORCE_POST_CURSOR_REQ 13 18 LC_FORCE_PRE_CURSOR_REQ 1 6 LC_FS_OTHER_END 19 24 LC_LF_OTHER_END 25 30 ixPCIE_LC_LANE_CNTL 2 0xb4 2 0 4294967295 LC_CORRUPTED_LANES 0 15 LC_LANE_DIS 16 31 ixPCIE_LC_LINK_WIDTH_CNTL 2 0xa2 18 0 4294967295 LC_DEASSERT_TX_PDNB 16 16 LC_DUAL_END_RECONFIG_EN 19 19 LC_DYN_LANES_PWR_STATE 21 22 LC_DYNLINK_MST_EN 18 18 LC_EQ_REVERSAL_LOGIC_EN 23 23 LC_L1_RECONFIG_EN 17 17 LC_LINK_WIDTH 0 2 LC_LINK_WIDTH_RD 4 6 LC_RECONFIG_ARC_MISSING_ESCAPE 7 7 LC_RECONFIG_NOW 8 8 LC_RENEGOTIATE_EN 10 10 LC_RENEGOTIATION_SUPPORT 9 9 LC_SHORT_RECONFIG_EN 11 11 LC_UPCFG_TIMER_SEL 15 15 LC_UPCFG_WAIT_FOR_RCVR_DIS 14 14 LC_UPCONFIGURE_CAPABLE 20 20 LC_UPCONFIGURE_DIS 13 13 LC_UPCONFIGURE_SUPPORT 12 12 ixPCIE_LC_N_FTS_CNTL 2 0xa3 5 0 4294967295 LC_N_FTS 24 31 LC_XMIT_FTS_BEFORE_RECOVERY 9 9 LC_XMIT_N_FTS_LIMIT 16 23 LC_XMIT_N_FTS 0 7 LC_XMIT_N_FTS_OVERRIDE_EN 8 8 ixPCIE_LC_SPEED_CNTL 2 0xa4 28 0 4294967295 LC_1_OR_MORE_TS2_SPEED_ARC_EN 17 17 LC_AUTO_RECOVERY_DIS 22 22 LC_CHECK_DATA_RATE 26 26 LC_CLR_FAILED_SPD_CHANGE_CNT 16 16 LC_CURRENT_DATA_RATE 13 14 LC_DATA_RATE_ADVERTISED 24 25 LC_DELAY_COEFF_UPDATE_DIS 31 31 LC_DONT_CHECK_EQTS_IN_RCFG 30 30 LC_DONT_CLR_TARGET_SPD_CHANGE_STATUS 15 15 LC_FORCE_DIS_HW_SPEED_CHANGE 8 8 LC_FORCE_DIS_SW_SPEED_CHANGE 6 6 LC_FORCE_EN_HW_SPEED_CHANGE 7 7 LC_FORCE_EN_SW_SPEED_CHANGE 5 5 LC_GEN2_EN_STRAP 0 0 LC_GEN3_EN_STRAP 1 1 LC_INITIATE_LINK_SPEED_CHANGE 9 9 LC_INIT_SPEED_NEG_IN_L0s_EN 28 28 LC_INIT_SPEED_NEG_IN_L1_EN 29 29 LC_MULT_UPSTREAM_AUTO_SPD_CHNG_EN 27 27 LC_OTHER_SIDE_EVER_SENT_GEN2 18 18 LC_OTHER_SIDE_EVER_SENT_GEN3 20 20 LC_OTHER_SIDE_SUPPORTS_GEN2 19 19 LC_OTHER_SIDE_SUPPORTS_GEN3 21 21 LC_SPEED_CHANGE_ATTEMPT_FAILED 12 12 LC_SPEED_CHANGE_ATTEMPTS_ALLOWED 10 11 LC_SPEED_CHANGE_STATUS 23 23 LC_TARGET_LINK_SPEED_OVERRIDE_EN 2 2 LC_TARGET_LINK_SPEED_OVERRIDE 3 4 ixPCIE_LC_STATE0 2 0xa5 4 0 4294967295 LC_CURRENT_STATE 0 5 LC_PREV_STATE1 8 13 LC_PREV_STATE2 16 21 LC_PREV_STATE3 24 29 ixPCIE_LC_STATE10 2 0x26 4 0 4294967295 LC_PREV_STATE40 0 5 LC_PREV_STATE41 8 13 LC_PREV_STATE42 16 21 LC_PREV_STATE43 24 29 ixPCIE_LC_STATE1 2 0xa6 4 0 4294967295 LC_PREV_STATE4 0 5 LC_PREV_STATE5 8 13 LC_PREV_STATE6 16 21 LC_PREV_STATE7 24 29 ixPCIE_LC_STATE11 2 0x27 4 0 4294967295 LC_PREV_STATE44 0 5 LC_PREV_STATE45 8 13 LC_PREV_STATE46 16 21 LC_PREV_STATE47 24 29 ixPCIE_LC_STATE2 2 0xa7 4 0 4294967295 LC_PREV_STATE10 16 21 LC_PREV_STATE11 24 29 LC_PREV_STATE8 0 5 LC_PREV_STATE9 8 13 ixPCIE_LC_STATE3 2 0xa8 4 0 4294967295 LC_PREV_STATE12 0 5 LC_PREV_STATE13 8 13 LC_PREV_STATE14 16 21 LC_PREV_STATE15 24 29 ixPCIE_LC_STATE4 2 0xa9 4 0 4294967295 LC_PREV_STATE16 0 5 LC_PREV_STATE17 8 13 LC_PREV_STATE18 16 21 LC_PREV_STATE19 24 29 ixPCIE_LC_STATE5 2 0xaa 4 0 4294967295 LC_PREV_STATE20 0 5 LC_PREV_STATE21 8 13 LC_PREV_STATE22 16 21 LC_PREV_STATE23 24 29 ixPCIE_LC_STATE6 2 0x22 4 0 4294967295 LC_PREV_STATE24 0 5 LC_PREV_STATE25 8 13 LC_PREV_STATE26 16 21 LC_PREV_STATE27 24 29 ixPCIE_LC_STATE7 2 0x23 4 0 4294967295 LC_PREV_STATE28 0 5 LC_PREV_STATE29 8 13 LC_PREV_STATE30 16 21 LC_PREV_STATE31 24 29 ixPCIE_LC_STATE8 2 0x24 4 0 4294967295 LC_PREV_STATE32 0 5 LC_PREV_STATE33 8 13 LC_PREV_STATE34 16 21 LC_PREV_STATE35 24 29 ixPCIE_LC_STATE9 2 0x25 4 0 4294967295 LC_PREV_STATE36 0 5 LC_PREV_STATE37 8 13 LC_PREV_STATE38 16 21 LC_PREV_STATE39 24 29 ixPCIE_LC_STATUS1 2 0x28 4 0 4294967295 LC_DETECTED_LINK_WIDTH 5 7 LC_OPERATING_LINK_WIDTH 2 4 LC_REVERSE_RCVR 0 0 LC_REVERSE_XMIT 1 1 ixPCIE_LC_STATUS2 2 0x29 2 0 4294967295 LC_TOTAL_INACTIVE_LANES 0 15 LC_TURN_ON_LANE 16 31 ixPCIE_LC_TRAINING_CNTL 2 0xa1 23 0 4294967295 LC_ALLOW_TX_L1_CONTROL 28 28 LC_ASPM_L1_NAK_TIMER_SEL 22 23 LC_AUTONOMOUS_CHANGE_OFF 17 17 LC_COMPLIANCE_RECEIVE 4 4 LC_DISABLE_TRAINING_BIT_ARCH 13 13 LC_DONT_DEASSERT_RX_EN_IN_R_SPEED 24 24 LC_DONT_DEASSERT_RX_EN_IN_TEST 25 25 LC_DONT_GO_TO_L0S_IF_L1_ARMED 11 11 LC_EXTEND_EQ_REQ_TIME 30 31 LC_EXTEND_WAIT_FOR_SKP 16 16 LC_HW_LINK_DIS_EN 19 19 LC_INIT_SPD_CHG_WITH_CSR_EN 12 12 LC_L0S_L1_TRAINING_CNTL_EN 6 6 LC_L1_LONG_WAKE_FIX_EN 7 7 LC_LINK_DIS_BY_HW 20 20 LC_LOOK_FOR_MORE_NON_MATCHING_TS1 5 5 LC_POWER_STATE 8 10 LC_RESET_ASPM_L1_NAK_TIMER 26 26 LC_SHORT_RCFG_TIMEOUT 27 27 LC_STATIC_TX_PIPE_COUNT_EN 21 21 LC_TRAINING_CNTL 0 3 LC_UPCONFIGURE_CAP_OFF 18 18 LC_WAIT_FOR_FOM_VALID_AFTER_TRACK 29 29 ixPCIE_P_BUF_STATUS 2 0x41 2 0 4294967295 P_OVERFLOW_ERR 0 15 P_UNDERFLOW_ERR 16 31 ixPCIE_P_CNTL 2 0x40 12 0 4294967295 P_ALWAYS_USE_FAST_TXCLK 13 13 P_BLK_LOCK_MODE 12 12 P_ELASTDESKEW_HW_DEBUG 3 3 P_ELEC_IDLE_MODE 14 15 P_IGNORE_CRC_ERR 4 4 P_IGNORE_EDB_ERR 6 6 P_IGNORE_IDL_ERR 7 7 P_IGNORE_LEN_ERR 5 5 P_IGNORE_TOK_ERR 8 8 P_PWRDN_EN 0 0 P_SYMALIGN_HW_DEBUG 2 2 P_SYMALIGN_MODE 1 1 ixPCIE_P_DECODER_STATUS 2 0x42 1 0 4294967295 P_DECODE_ERR 0 15 ixPCIE_PERF_CNTL_EVENT0_PORT_SEL 2 0x93 7 0 4294967295 PERF0_PORT_SEL_MST_C_CLK 8 11 PERF0_PORT_SEL_MST_R_CLK 4 7 PERF0_PORT_SEL_SLV_NS_C_CLK 20 23 PERF0_PORT_SEL_SLV_R_CLK 12 15 PERF0_PORT_SEL_SLV_S_C_CLK 16 19 PERF0_PORT_SEL_TXCLK2 24 27 PERF0_PORT_SEL_TXCLK 0 3 ixPCIE_PERF_CNTL_EVENT1_PORT_SEL 2 0x94 7 0 4294967295 PERF1_PORT_SEL_MST_C_CLK 8 11 PERF1_PORT_SEL_MST_R_CLK 4 7 PERF1_PORT_SEL_SLV_NS_C_CLK 20 23 PERF1_PORT_SEL_SLV_R_CLK 12 15 PERF1_PORT_SEL_SLV_S_C_CLK 16 19 PERF1_PORT_SEL_TXCLK2 24 27 PERF1_PORT_SEL_TXCLK 0 3 ixPCIE_PERF_CNTL_MST_C_CLK 2 0x87 4 0 4294967295 COUNTER0_UPPER 16 23 COUNTER1_UPPER 24 31 EVENT0_SEL 0 7 EVENT1_SEL 8 15 ixPCIE_PERF_CNTL_MST_R_CLK 2 0x84 4 0 4294967295 COUNTER0_UPPER 16 23 COUNTER1_UPPER 24 31 EVENT0_SEL 0 7 EVENT1_SEL 8 15 ixPCIE_PERF_CNTL_SLV_NS_C_CLK 2 0x90 4 0 4294967295 COUNTER0_UPPER 16 23 COUNTER1_UPPER 24 31 EVENT0_SEL 0 7 EVENT1_SEL 8 15 ixPCIE_PERF_CNTL_SLV_R_CLK 2 0x8a 4 0 4294967295 COUNTER0_UPPER 16 23 COUNTER1_UPPER 24 31 EVENT0_SEL 0 7 EVENT1_SEL 8 15 ixPCIE_PERF_CNTL_SLV_S_C_CLK 2 0x8d 4 0 4294967295 COUNTER0_UPPER 16 23 COUNTER1_UPPER 24 31 EVENT0_SEL 0 7 EVENT1_SEL 8 15 ixPCIE_PERF_CNTL_TXCLK 2 0x81 4 0 4294967295 COUNTER0_UPPER 16 23 COUNTER1_UPPER 24 31 EVENT0_SEL 0 7 EVENT1_SEL 8 15 ixPCIE_PERF_CNTL_TXCLK2 2 0x95 4 0 4294967295 COUNTER0_UPPER 16 23 COUNTER1_UPPER 24 31 EVENT0_SEL 0 7 EVENT1_SEL 8 15 ixPCIE_PERF_COUNT0_MST_C_CLK 2 0x88 1 0 4294967295 COUNTER0 0 31 ixPCIE_PERF_COUNT0_MST_R_CLK 2 0x85 1 0 4294967295 COUNTER0 0 31 ixPCIE_PERF_COUNT0_SLV_NS_C_CLK 2 0x91 1 0 4294967295 COUNTER0 0 31 ixPCIE_PERF_COUNT0_SLV_R_CLK 2 0x8b 1 0 4294967295 COUNTER0 0 31 ixPCIE_PERF_COUNT0_SLV_S_C_CLK 2 0x8e 1 0 4294967295 COUNTER0 0 31 ixPCIE_PERF_COUNT0_TXCLK 2 0x82 1 0 4294967295 COUNTER0 0 31 ixPCIE_PERF_COUNT0_TXCLK2 2 0x96 1 0 4294967295 COUNTER0 0 31 ixPCIE_PERF_COUNT1_MST_C_CLK 2 0x89 1 0 4294967295 COUNTER1 0 31 ixPCIE_PERF_COUNT1_MST_R_CLK 2 0x86 1 0 4294967295 COUNTER1 0 31 ixPCIE_PERF_COUNT1_SLV_NS_C_CLK 2 0x92 1 0 4294967295 COUNTER1 0 31 ixPCIE_PERF_COUNT1_SLV_R_CLK 2 0x8c 1 0 4294967295 COUNTER1 0 31 ixPCIE_PERF_COUNT1_SLV_S_C_CLK 2 0x8f 1 0 4294967295 COUNTER1 0 31 ixPCIE_PERF_COUNT1_TXCLK 2 0x83 1 0 4294967295 COUNTER1 0 31 ixPCIE_PERF_COUNT1_TXCLK2 2 0x97 1 0 4294967295 COUNTER1 0 31 ixPCIE_PERF_COUNT_CNTL 2 0x80 3 0 4294967295 GLOBAL_COUNT_EN 0 0 GLOBAL_COUNT_RESET 2 2 GLOBAL_SHADOW_WR 1 1 ixPCIEP_HW_DEBUG 2 0x2 16 0 4294967295 HW_00_DEBUG 0 0 HW_01_DEBUG 1 1 HW_02_DEBUG 2 2 HW_03_DEBUG 3 3 HW_04_DEBUG 4 4 HW_05_DEBUG 5 5 HW_06_DEBUG 6 6 HW_07_DEBUG 7 7 HW_08_DEBUG 8 8 HW_09_DEBUG 9 9 HW_10_DEBUG 10 10 HW_11_DEBUG 11 11 HW_12_DEBUG 12 12 HW_13_DEBUG 13 13 HW_14_DEBUG 14 14 HW_15_DEBUG 15 15 ixPCIE_P_MISC_STATUS 2 0x43 2 0 4294967295 P_DESKEW_ERR 0 7 P_SYMUNLOCK_ERR 16 31 ixPCIEP_PORT_CNTL 2 0x10 8 0 4294967295 CI_SLV_CPL_STATIC_ALLOC_LIMIT_S 8 14 CI_SNOOP_OVERRIDE 1 1 HOTPLUG_MSG_EN 2 2 NATIVE_PME_EN 3 3 PMI_BM_DIS 5 5 PWR_FAULT_EN 4 4 SEQNUM_DEBUG_MODE 6 6 SLV_PORT_REQ_EN 0 0 ixPCIE_P_PORT_LANE_STATUS 2 0x50 2 0 4294967295 PHY_LINK_WIDTH 1 6 PORT_LANE_REVERSAL 0 0 ixPCIE_PRBS_CLR 2 0xc8 2 0 4294967295 PRBS_CHECKER_DEBUG_BUS_SELECT 16 19 PRBS_CLR 0 15 ixPCIE_PRBS_ERRCNT_0 2 0xd0 1 0 4294967295 PRBS_ERRCNT_0 0 31 ixPCIE_PRBS_ERRCNT_10 2 0xda 1 0 4294967295 PRBS_ERRCNT_10 0 31 ixPCIE_PRBS_ERRCNT_1 2 0xd1 1 0 4294967295 PRBS_ERRCNT_1 0 31 ixPCIE_PRBS_ERRCNT_11 2 0xdb 1 0 4294967295 PRBS_ERRCNT_11 0 31 ixPCIE_PRBS_ERRCNT_12 2 0xdc 1 0 4294967295 PRBS_ERRCNT_12 0 31 ixPCIE_PRBS_ERRCNT_13 2 0xdd 1 0 4294967295 PRBS_ERRCNT_13 0 31 ixPCIE_PRBS_ERRCNT_14 2 0xde 1 0 4294967295 PRBS_ERRCNT_14 0 31 ixPCIE_PRBS_ERRCNT_15 2 0xdf 1 0 4294967295 PRBS_ERRCNT_15 0 31 ixPCIE_PRBS_ERRCNT_2 2 0xd2 1 0 4294967295 PRBS_ERRCNT_2 0 31 ixPCIE_PRBS_ERRCNT_3 2 0xd3 1 0 4294967295 PRBS_ERRCNT_3 0 31 ixPCIE_PRBS_ERRCNT_4 2 0xd4 1 0 4294967295 PRBS_ERRCNT_4 0 31 ixPCIE_PRBS_ERRCNT_5 2 0xd5 1 0 4294967295 PRBS_ERRCNT_5 0 31 ixPCIE_PRBS_ERRCNT_6 2 0xd6 1 0 4294967295 PRBS_ERRCNT_6 0 31 ixPCIE_PRBS_ERRCNT_7 2 0xd7 1 0 4294967295 PRBS_ERRCNT_7 0 31 ixPCIE_PRBS_ERRCNT_8 2 0xd8 1 0 4294967295 PRBS_ERRCNT_8 0 31 ixPCIE_PRBS_ERRCNT_9 2 0xd9 1 0 4294967295 PRBS_ERRCNT_9 0 31 ixPCIE_PRBS_FREERUN 2 0xcb 1 0 4294967295 PRBS_FREERUN 0 15 ixPCIE_PRBS_HI_BITCNT 2 0xcf 1 0 4294967295 PRBS_HI_BITCNT 0 7 ixPCIE_PRBS_LO_BITCNT 2 0xce 1 0 4294967295 PRBS_LO_BITCNT 0 31 ixPCIE_PRBS_MISC 2 0xcc 8 0 4294967295 PRBS_8BIT_SEL 4 4 PRBS_CHK_ERR_MASK 16 31 PRBS_COMMA_NUM 5 6 PRBS_DATA_RATE 14 15 PRBS_EN 0 0 PRBS_LOCK_CNT 7 11 PRBS_TEST_MODE 1 2 PRBS_USER_PATTERN_TOGGLE 3 3 ixPCIE_PRBS_STATUS1 2 0xc9 2 0 4294967295 PRBS_ERRSTAT 0 15 PRBS_LOCKED 16 31 ixPCIE_PRBS_STATUS2 2 0xca 1 0 4294967295 PRBS_BITCNT_DONE 0 15 ixPCIE_PRBS_USER_PATTERN 2 0xcd 1 0 4294967295 PRBS_USER_PATTERN 0 29 ixPCIE_P_RCV_L0S_FTS_DET 2 0x50 2 0 4294967295 P_RCV_L0S_FTS_DET_MAX 8 15 P_RCV_L0S_FTS_DET_MIN 0 7 ixPCIEP_RESERVED 2 0x0 1 0 4294967295 PCIEP_RESERVED 0 31 ixPCIEP_SCRATCH 2 0x1 1 0 4294967295 PCIEP_SCRATCH 0 31 ixPCIEP_STRAP_LC 2 0xc0 11 0 4294967295 STRAP_AUTO_RC_SPEED_NEGOTIATION_DIS 15 15 STRAP_BYPASS_RCVR_DET 11 11 STRAP_COMPLIANCE_DIS 12 12 STRAP_FORCE_COMPLIANCE 13 13 STRAP_FTS_yTSx_COUNT 0 1 STRAP_LANE_NEGOTIATION 16 18 STRAP_LONG_yTSx_COUNT 2 3 STRAP_MED_yTSx_COUNT 4 5 STRAP_REVERSE_LC_LANES 14 14 STRAP_SHORT_yTSx_COUNT 6 7 STRAP_SKIP_INTERVAL 8 10 ixPCIEP_STRAP_MISC 2 0xc1 4 0 4294967295 STRAP_E2E_PREFIX_EN 1 1 STRAP_EXTENDED_FMT_SUPPORTED 2 2 STRAP_OBFF_SUPPORTED 3 4 STRAP_REVERSE_LANES 0 0 ixPCIE_RESERVED 2 0x0 1 0 4294967295 PCIE_RESERVED 0 31 ixPCIE_RX_CNTL 2 0x70 24 0 4294967295 RX_FC_INIT_FROM_REG 15 15 RX_GEN_ONE_NAK 14 14 RX_IGNORE_AT_ERR 12 12 RX_IGNORE_BE_ERR 1 1 RX_IGNORE_CFG_ERR 4 4 RX_IGNORE_CFG_UR 10 10 RX_IGNORE_CPL_ERR 5 5 RX_IGNORE_CPLPREFIX_ERR 23 23 RX_IGNORE_CRC_ERR 3 3 RX_IGNORE_EP_ERR 6 6 RX_IGNORE_INVALIDPASID_ERR 24 24 RX_IGNORE_IO_ERR 0 0 RX_IGNORE_IO_UR 11 11 RX_IGNORE_LEN_MISMATCH_ERR 7 7 RX_IGNORE_MAX_PAYLOAD_ERR 8 8 RX_IGNORE_MAXPREFIX_ERR 22 22 RX_IGNORE_MSG_ERR 2 2 RX_IGNORE_NOT_PASID_UR 25 25 RX_IGNORE_SHORTPREFIX_ERR 21 21 RX_IGNORE_TC_ERR 9 9 RX_NAK_IF_FIFO_FULL 13 13 RX_PCIE_CPL_TIMEOUT_DIS 20 20 RX_RCB_CPL_TIMEOUT 16 18 RX_RCB_CPL_TIMEOUT_MODE 19 19 ixPCIE_RX_CNTL2 2 0x1d 6 0 4294967295 RX_IGNORE_EP_ATSTRANSREQ_UR 3 3 RX_IGNORE_EP_INVALIDPASID_UR 0 0 RX_IGNORE_EP_INVCPL_UR 5 5 RX_IGNORE_EP_PAGEREQMSG_UR 4 4 RX_IGNORE_EP_TRANSMRD_UR 1 1 RX_IGNORE_EP_TRANSMWR_UR 2 2 ixPCIE_RX_CNTL3 2 0x74 5 0 4294967295 RX_IGNORE_RC_INVCPLPASID_UR 4 4 RX_IGNORE_RC_INVREQ_UR 3 3 RX_IGNORE_RC_PRGRESPMSG_UR 2 2 RX_IGNORE_RC_TRANSMRDPASID_UR 0 0 RX_IGNORE_RC_TRANSMWRPASID_UR 1 1 ixPCIE_RX_CREDITS_ALLOCATED_CPL 2 0x82 2 0 4294967295 RX_CREDITS_ALLOCATED_CPLD 0 11 RX_CREDITS_ALLOCATED_CPLH 16 23 ixPCIE_RX_CREDITS_ALLOCATED_NP 2 0x81 2 0 4294967295 RX_CREDITS_ALLOCATED_NPD 0 11 RX_CREDITS_ALLOCATED_NPH 16 23 ixPCIE_RX_CREDITS_ALLOCATED_P 2 0x80 2 0 4294967295 RX_CREDITS_ALLOCATED_PD 0 11 RX_CREDITS_ALLOCATED_PH 16 23 ixPCIE_RX_EXPECTED_SEQNUM 2 0x71 1 0 4294967295 RX_EXPECTED_SEQNUM 0 11 ixPCIE_RX_LAST_TLP0 2 0x31 1 0 4294967295 RX_LAST_TLP0 0 31 ixPCIE_RX_LAST_TLP1 2 0x32 1 0 4294967295 RX_LAST_TLP1 0 31 ixPCIE_RX_LAST_TLP2 2 0x33 1 0 4294967295 RX_LAST_TLP2 0 31 ixPCIE_RX_LAST_TLP3 2 0x34 1 0 4294967295 RX_LAST_TLP3 0 31 ixPCIE_RX_NUM_NAK 2 0xe 1 0 4294967295 RX_NUM_NAK 0 31 ixPCIE_RX_NUM_NAK_GENERATED 2 0xf 1 0 4294967295 RX_NUM_NAK_GENERATED 0 31 ixPCIE_RX_VENDOR_SPECIFIC 2 0x72 2 0 4294967295 RX_VENDOR_DATA 0 23 RX_VENDOR_STATUS 24 24 ixPCIE_SCRATCH 2 0x1 1 0 4294967295 PCIE_SCRATCH 0 31 ixPCIE_STRAP_F0 2 0xb0 13 0 4294967295 STRAP_F0_ACS_EN 6 6 STRAP_F0_AER_EN 5 5 STRAP_F0_ATS_EN 10 10 STRAP_F0_BAR_EN 7 7 STRAP_F0_DPA_EN 9 9 STRAP_F0_DSN_EN 4 4 STRAP_F0_EN 0 0 STRAP_F0_LEGACY_DEVICE_TYPE_EN 1 1 STRAP_F0_MSI_EN 2 2 STRAP_F0_PAGE_REQ_EN 11 11 STRAP_F0_PASID_EN 12 12 STRAP_F0_PWR_EN 8 8 STRAP_F0_VC_EN 3 3 ixPCIE_STRAP_F1 2 0xb1 13 0 4294967295 STRAP_F1_ACS_EN 6 6 STRAP_F1_AER_EN 5 5 STRAP_F1_ATS_EN 10 10 STRAP_F1_BAR_EN 7 7 STRAP_F1_DPA_EN 9 9 STRAP_F1_DSN_EN 4 4 STRAP_F1_EN 0 0 STRAP_F1_LEGACY_DEVICE_TYPE_EN 1 1 STRAP_F1_MSI_EN 2 2 STRAP_F1_PAGE_REQ_EN 11 11 STRAP_F1_PASID_EN 12 12 STRAP_F1_PWR_EN 8 8 STRAP_F1_VC_EN 3 3 ixPCIE_STRAP_F2 2 0xb2 13 0 4294967295 STRAP_F2_ACS_EN 6 6 STRAP_F2_AER_EN 5 5 STRAP_F2_ATS_EN 10 10 STRAP_F2_BAR_EN 7 7 STRAP_F2_DPA_EN 9 9 STRAP_F2_DSN_EN 4 4 STRAP_F2_EN 0 0 STRAP_F2_LEGACY_DEVICE_TYPE_EN 1 1 STRAP_F2_MSI_EN 2 2 STRAP_F2_PAGE_REQ_EN 11 11 STRAP_F2_PASID_EN 12 12 STRAP_F2_PWR_EN 8 8 STRAP_F2_VC_EN 3 3 ixPCIE_STRAP_F3 2 0xb3 1 0 4294967295 RESERVED 0 31 ixPCIE_STRAP_F4 2 0xb4 1 0 4294967295 RESERVED 0 31 ixPCIE_STRAP_F5 2 0xb5 1 0 4294967295 RESERVED 0 31 ixPCIE_STRAP_F6 2 0xb6 1 0 4294967295 RESERVED 0 31 ixPCIE_STRAP_F7 2 0xb7 1 0 4294967295 RESERVED 0 31 ixPCIE_STRAP_I2C_BD 2 0xc4 2 0 4294967295 STRAP_BIF_DBG_I2C_EN 7 7 STRAP_BIF_I2C_SLV_ADR 0 6 ixPCIE_STRAP_MISC 2 0xc0 11 0 4294967295 STRAP_CLK_PM_EN 24 24 STRAP_ECN1P1_EN 25 25 STRAP_EXT_VC_COUNT 26 26 STRAP_FLR_EN 30 30 STRAP_LINK_CONFIG 0 3 STRAP_MAX_PASID_WIDTH 8 12 STRAP_MST_ADR64_EN 29 29 STRAP_PASID_EXE_PERMISSION_SUPPORTED 13 13 STRAP_PASID_GLOBAL_INVALIDATE_SUPPORTED 15 15 STRAP_PASID_PRIV_MODE_SUPPORTED 14 14 STRAP_REVERSE_ALL 28 28 ixPCIE_STRAP_MISC2 2 0xc1 3 0 4294967295 STRAP_GEN2_COMPLIANCE 1 1 STRAP_GEN3_COMPLIANCE 3 3 STRAP_MSTCPL_TIMEOUT_EN 2 2 ixPCIE_STRAP_PI 2 0xc2 3 0 4294967295 STRAP_QUICKSIM_START 0 0 STRAP_TEST_TOGGLE_MODE 29 29 STRAP_TEST_TOGGLE_PATTERN 28 28 ixPCIE_TX_ACK_LATENCY_LIMIT 2 0x26 2 0 4294967295 TX_ACK_LATENCY_LIMIT 0 11 TX_ACK_LATENCY_LIMIT_OVERWRITE 12 12 ixPCIE_TX_CNTL 2 0x20 8 0 4294967295 TX_CLEAR_EXTRA_PM_REQS 22 22 TX_CPL_PASS_P 20 20 TX_FC_UPDATE_TIMEOUT_DIS 23 23 TX_FLUSH_TLP_DIS 15 15 TX_NP_PASS_P 21 21 TX_PACK_PACKET_DIS 14 14 TX_RO_OVERRIDE 12 13 TX_SNR_OVERRIDE 10 11 ixPCIE_TX_CREDITS_ADVT_CPL 2 0x32 2 0 4294967295 TX_CREDITS_ADVT_CPLD 0 11 TX_CREDITS_ADVT_CPLH 16 23 ixPCIE_TX_CREDITS_ADVT_NP 2 0x31 2 0 4294967295 TX_CREDITS_ADVT_NPD 0 11 TX_CREDITS_ADVT_NPH 16 23 ixPCIE_TX_CREDITS_ADVT_P 2 0x30 2 0 4294967295 TX_CREDITS_ADVT_PD 0 11 TX_CREDITS_ADVT_PH 16 23 ixPCIE_TX_CREDITS_FCU_THRESHOLD 2 0x37 6 0 4294967295 TX_FCU_THRESHOLD_CPL_VC0 8 10 TX_FCU_THRESHOLD_CPL_VC1 24 26 TX_FCU_THRESHOLD_NP_VC0 4 6 TX_FCU_THRESHOLD_NP_VC1 20 22 TX_FCU_THRESHOLD_P_VC0 0 2 TX_FCU_THRESHOLD_P_VC1 16 18 ixPCIE_TX_CREDITS_INIT_CPL 2 0x35 2 0 4294967295 TX_CREDITS_INIT_CPLD 0 11 TX_CREDITS_INIT_CPLH 16 23 ixPCIE_TX_CREDITS_INIT_NP 2 0x34 2 0 4294967295 TX_CREDITS_INIT_NPD 0 11 TX_CREDITS_INIT_NPH 16 23 ixPCIE_TX_CREDITS_INIT_P 2 0x33 2 0 4294967295 TX_CREDITS_INIT_PD 0 11 TX_CREDITS_INIT_PH 16 23 ixPCIE_TX_CREDITS_STATUS 2 0x36 12 0 4294967295 TX_CREDITS_CUR_STATUS_CPLD 20 20 TX_CREDITS_CUR_STATUS_CPLH 21 21 TX_CREDITS_CUR_STATUS_NPD 18 18 TX_CREDITS_CUR_STATUS_NPH 19 19 TX_CREDITS_CUR_STATUS_PD 16 16 TX_CREDITS_CUR_STATUS_PH 17 17 TX_CREDITS_ERR_CPLD 4 4 TX_CREDITS_ERR_CPLH 5 5 TX_CREDITS_ERR_NPD 2 2 TX_CREDITS_ERR_NPH 3 3 TX_CREDITS_ERR_PD 0 0 TX_CREDITS_ERR_PH 1 1 ixPCIE_TX_LAST_TLP0 2 0x35 1 0 4294967295 TX_LAST_TLP0 0 31 ixPCIE_TX_LAST_TLP1 2 0x36 1 0 4294967295 TX_LAST_TLP1 0 31 ixPCIE_TX_LAST_TLP2 2 0x37 1 0 4294967295 TX_LAST_TLP2 0 31 ixPCIE_TX_LAST_TLP3 2 0x38 1 0 4294967295 TX_LAST_TLP3 0 31 ixPCIE_TX_REPLAY 2 0x25 3 0 4294967295 TX_REPLAY_NUM 0 2 TX_REPLAY_TIMER 16 31 TX_REPLAY_TIMER_OVERWRITE 15 15 ixPCIE_TX_REQUESTER_ID 2 0x21 3 0 4294967295 TX_REQUESTER_ID_BUS 8 15 TX_REQUESTER_ID_DEVICE 3 7 TX_REQUESTER_ID_FUNCTION 0 2 ixPCIE_TX_REQUEST_NUM_CNTL 2 0x23 3 0 4294967295 TX_NUM_OUTSTANDING_NP_EN 31 31 TX_NUM_OUTSTANDING_NP 24 29 TX_NUM_OUTSTANDING_NP_VC1_EN 30 30 ixPCIE_TX_SEQ 2 0x24 2 0 4294967295 TX_ACKD_SEQ 16 27 TX_NEXT_TRANSMIT_SEQ 0 11 ixPCIE_TX_VENDOR_SPECIFIC 2 0x22 1 0 4294967295 TX_VENDOR_DATA 0 23 ixPCIE_WPR_CNTL 2 0x30 7 0 4294967295 WPR_RESET_COR_EN 3 3 WPR_RESET_HOT_RST_EN 0 0 WPR_RESET_LNK_DIS_EN 2 2 WPR_RESET_LNK_DWN_EN 1 1 WPR_RESET_PHY_EN 6 6 WPR_RESET_REG_EN 4 4 WPR_RESET_STY_EN 5 5 mmBACO_CNTL 0 0x14e5 13 0 4294967295 BACO_ANA_ISO_DIS 7 7 BACO_BCLK_OFF 1 1 BACO_EN 0 0 BACO_HANG_PROTECTION_EN 5 5 BACO_ISO_DIS 2 2 BACO_MODE 6 6 BACO_POWER_OFF 3 3 BACO_RESET_EN 4 4 PWRGOOD_BF 9 9 PWRGOOD_DVO 12 12 PWRGOOD_GPIO 10 10 PWRGOOD_MEM 11 11 RCU_BIF_CONFIG_DONE 8 8 mmBF_ANA_ISO_CNTL 0 0x14c7 2 0 4294967295 BF_ANA_ISO_DIS_MASK 0 0 BF_VDDC_ISO_DIS_MASK 1 1 mmBIF_BACO_DEBUG 0 0x14df 1 0 4294967295 BIF_BACO_SCANDUMP_FLG 0 0 mmBIF_BACO_DEBUG_LATCH 0 0x14dc 1 0 4294967295 BIF_BACO_LATCH_FLG 0 0 mmBIF_BACO_MSIC 0 0x14de 1 0 4294967295 BIF_XTALIN_SEL 0 0 mmBIF_BUSNUM_CNTL1 0 0x1525 1 0 4294967295 ID_MASK 0 7 mmBIF_BUSNUM_CNTL2 0 0x152b 4 0 4294967295 AUTOUPDATE_EN 8 8 AUTOUPDATE_SEL 0 7 ERROR_MULTIPLE_ID_MATCH 17 17 HDPREG_CNTL 16 16 mmBIF_BUSNUM_LIST0 0 0x1526 4 0 4294967295 ID0 0 7 ID1 8 15 ID2 16 23 ID3 24 31 mmBIF_BUSNUM_LIST1 0 0x1527 4 0 4294967295 ID4 0 7 ID5 8 15 ID6 16 23 ID7 24 31 mmBIF_BUSY_DELAY_CNTR 0 0x1529 1 0 4294967295 DELAY_CNT 0 5 mmBIF_CLK_PDWN_DELAY_TIMER 0 0x151f 1 0 4294967295 TIMER 0 9 mmBIF_DEBUG_CNTL 0 0x151c 12 0 4294967295 DEBUG_BYTESEL_BLK1 4 4 DEBUG_BYTESEL_BLK2 5 5 DEBUG_EN 0 0 DEBUG_IDSEL_BLK1 8 12 DEBUG_IDSEL_BLK2 16 20 DEBUG_IDSEL_XSP 24 24 DEBUG_MULTIBLOCKEN 1 1 DEBUG_OUT_EN 2 2 DEBUG_PAD_SEL 3 3 DEBUG_SWAP 7 7 DEBUG_SYNC_CLKSEL 30 31 DEBUG_SYNC_EN 6 6 mmBIF_DEBUG_MUX 0 0x151d 2 0 4294967295 DEBUG_MUX_BLK1 0 5 DEBUG_MUX_BLK2 8 13 mmBIF_DEBUG_OUT 0 0x151e 1 0 4294967295 DEBUG_OUTPUT 0 16 mmBIF_DEVFUNCNUM_LIST0 0 0x14e8 4 0 4294967295 DEVFUNC_ID0 0 7 DEVFUNC_ID1 8 15 DEVFUNC_ID2 16 23 DEVFUNC_ID3 24 31 mmBIF_DEVFUNCNUM_LIST1 0 0x14e7 4 0 4294967295 DEVFUNC_ID4 0 7 DEVFUNC_ID5 8 15 DEVFUNC_ID6 16 23 DEVFUNC_ID7 24 31 mmBIF_FB_EN 0 0x1524 2 0 4294967295 FB_READ_EN 0 0 FB_WRITE_EN 1 1 mmBIF_FEATURES_CONTROL_MISC 0 0x14c2 9 0 4294967295 BIF_MST_CPL_EP_DIS 3 3 BIF_SLV_REQ_EP_DIS 2 2 IGNORE_BE_CHECK_GASKET_COMB_DIS 8 8 MST_BIF_REQ_EP_DIS 0 0 PLL_SWITCH_IMPCTL_CAL_DONE_DIS 7 7 POST_PSN_ONLY_PKT_REPORT_UR_ALL_DIS 5 5 POST_PSN_ONLY_PKT_REPORT_UR_PART_DIS 6 6 SLV_BIF_CPL_EP_DIS 1 1 UR_PSN_PKT_REPORT_POISON_DIS 4 4 mmBIF_PERFCOUNTER0_RESULT 0 0x152d 1 0 4294967295 PERFCOUNTER_RESULT 0 31 mmBIF_PERFCOUNTER1_RESULT 0 0x152e 1 0 4294967295 PERFCOUNTER_RESULT 0 31 mmBIF_PERFMON_CNTL 0 0x152c 5 0 4294967295 PERFCOUNTER_EN 0 0 PERFCOUNTER_RESET0 1 1 PERFCOUNTER_RESET1 2 2 PERF_SEL0 8 12 PERF_SEL1 13 17 mmBIF_PIF_TXCLK_SWITCH_TIMER 0 0x152f 3 0 4294967295 PLL0_ACK_TIMER 0 2 PLL1_ACK_TIMER 3 5 PLL_SWITCH_TIMER 6 9 mmBIF_RESET_EN 0 0x1511 22 0 4294967295 BIF_COR_RESET_EN 22 22 CFG_RESET_EN 6 6 CFG_RESET_PULSE_WIDTH 12 17 COR_RESET_EN 3 3 DRV_RESET_DELAY_SEL 18 19 DRV_RESET_EN 7 7 FUNC0_FLR_EN 23 23 FUNC0_RESET_DELAY_SEL 26 27 FUNC1_FLR_EN 24 24 FUNC1_RESET_DELAY_SEL 28 29 FUNC2_FLR_EN 25 25 FUNC2_RESET_DELAY_SEL 30 31 HOT_RESET_EN 9 9 LINK_DISABLE_RESET_EN 10 10 LINK_DOWN_RESET_EN 11 11 PHY_RESET_EN 2 2 PIF_RSTB_EN 20 20 PIF_STRAP_ALLVALID_EN 21 21 REG_RESET_EN 4 4 RESET_CFGREG_ONLY_EN 8 8 SOFT_RST_MODE 1 1 STY_RESET_EN 5 5 mmBIF_SCRATCH0 0 0x150e 1 0 4294967295 BIF_SCRATCH0 0 31 mmBIF_SCRATCH1 0 0x150f 1 0 4294967295 BIF_SCRATCH1 0 31 mmBIF_SSA_DISP_LOWER 0 0x14d2 3 0 4294967295 SSA_DISP_LOWER 2 17 SSA_DISP_REG_CMP_EN 30 30 SSA_DISP_REG_STALL_EN 31 31 mmBIF_SSA_DISP_UPPER 0 0x14d3 1 0 4294967295 SSA_DISP_UPPER 2 17 mmBIF_SSA_GFX0_LOWER 0 0x14ca 3 0 4294967295 SSA_GFX0_LOWER 2 17 SSA_GFX0_REG_CMP_EN 30 30 SSA_GFX0_REG_STALL_EN 31 31 mmBIF_SSA_GFX0_UPPER 0 0x14cb 1 0 4294967295 SSA_GFX0_UPPER 2 17 mmBIF_SSA_GFX1_LOWER 0 0x14cc 3 0 4294967295 SSA_GFX1_LOWER 2 17 SSA_GFX1_REG_CMP_EN 30 30 SSA_GFX1_REG_STALL_EN 31 31 mmBIF_SSA_GFX1_UPPER 0 0x14cd 1 0 4294967295 SSA_GFX1_UPPER 2 17 mmBIF_SSA_GFX2_LOWER 0 0x14ce 3 0 4294967295 SSA_GFX2_LOWER 2 17 SSA_GFX2_REG_CMP_EN 30 30 SSA_GFX2_REG_STALL_EN 31 31 mmBIF_SSA_GFX2_UPPER 0 0x14cf 1 0 4294967295 SSA_GFX2_UPPER 2 17 mmBIF_SSA_GFX3_LOWER 0 0x14d0 3 0 4294967295 SSA_GFX3_LOWER 2 17 SSA_GFX3_REG_CMP_EN 30 30 SSA_GFX3_REG_STALL_EN 31 31 mmBIF_SSA_GFX3_UPPER 0 0x14d1 1 0 4294967295 SSA_GFX3_UPPER 2 17 mmBIF_SSA_MC_LOWER 0 0x14d4 4 0 4294967295 SSA_MC_FB_STALL_EN 29 29 SSA_MC_LOWER 2 17 SSA_MC_REG_CMP_EN 30 30 SSA_MC_REG_STALL_EN 31 31 mmBIF_SSA_MC_UPPER 0 0x14d5 1 0 4294967295 SSA_MC_UPPER 2 17 mmBIF_SSA_PWR_STATUS 0 0x14c8 3 0 4294967295 SSA_DISP_PWR_STATUS 1 1 SSA_GFX_PWR_STATUS 0 0 SSA_MC_PWR_STATUS 2 2 mmBIF_XDMA_HI 0 0x14c1 1 0 4294967295 BIF_XDMA_UPPER_BOUND 0 28 mmBIF_XDMA_LO 0 0x14c0 2 0 4294967295 BIF_XDMA_APER_EN 31 31 BIF_XDMA_LOWER_BOUND 0 28 mmBIOS_SCRATCH_0 0 0x5c9 1 0 4294967295 BIOS_SCRATCH_0 0 31 mmBIOS_SCRATCH_10 0 0x5d3 1 0 4294967295 BIOS_SCRATCH_10 0 31 mmBIOS_SCRATCH_1 0 0x5ca 1 0 4294967295 BIOS_SCRATCH_1 0 31 mmBIOS_SCRATCH_11 0 0x5d4 1 0 4294967295 BIOS_SCRATCH_11 0 31 mmBIOS_SCRATCH_12 0 0x5d5 1 0 4294967295 BIOS_SCRATCH_12 0 31 mmBIOS_SCRATCH_13 0 0x5d6 1 0 4294967295 BIOS_SCRATCH_13 0 31 mmBIOS_SCRATCH_14 0 0x5d7 1 0 4294967295 BIOS_SCRATCH_14 0 31 mmBIOS_SCRATCH_15 0 0x5d8 1 0 4294967295 BIOS_SCRATCH_15 0 31 mmBIOS_SCRATCH_2 0 0x5cb 1 0 4294967295 BIOS_SCRATCH_2 0 31 mmBIOS_SCRATCH_3 0 0x5cc 1 0 4294967295 BIOS_SCRATCH_3 0 31 mmBIOS_SCRATCH_4 0 0x5cd 1 0 4294967295 BIOS_SCRATCH_4 0 31 mmBIOS_SCRATCH_5 0 0x5ce 1 0 4294967295 BIOS_SCRATCH_5 0 31 mmBIOS_SCRATCH_6 0 0x5cf 1 0 4294967295 BIOS_SCRATCH_6 0 31 mmBIOS_SCRATCH_7 0 0x5d0 1 0 4294967295 BIOS_SCRATCH_7 0 31 mmBIOS_SCRATCH_8 0 0x5d1 1 0 4294967295 BIOS_SCRATCH_8 0 31 mmBIOS_SCRATCH_9 0 0x5d2 1 0 4294967295 BIOS_SCRATCH_9 0 31 mmBUS_CNTL 0 0x1508 14 0 4294967295 BIF_ERR_RTR_BKPRESSURE_EN 8 8 BIOS_ROM_DIS 1 1 BIOS_ROM_WRT_EN 0 0 PMI_BM_DIS 4 4 PMI_INT_DIS 5 5 PMI_IO_DIS 2 2 PMI_MEM_DIS 3 3 RD_STALL_IO_WR 18 18 SET_AZ_TC 10 12 SET_MC_TC 13 15 VGA_MEM_COHERENCY_DIS 7 7 VGA_REG_COHERENCY_DIS 6 6 ZERO_BE_RD_EN 17 17 ZERO_BE_WR_EN 16 16 mmCAPTURE_HOST_BUSNUM 0 0x153c 1 0 4294967295 CHECK_EN 0 0 mmCLKREQB_PAD_CNTL 0 0x1521 12 0 4294967295 CLKREQB_PAD_A 0 0 CLKREQB_PAD_CNTL_EN 12 12 CLKREQB_PAD_MODE 2 2 CLKREQB_PAD_SCHMEN 11 11 CLKREQB_PAD_SEL 1 1 CLKREQB_PAD_SLEWN 9 9 CLKREQB_PAD_SN0 5 5 CLKREQB_PAD_SN1 6 6 CLKREQB_PAD_SN2 7 7 CLKREQB_PAD_SN3 8 8 CLKREQB_PAD_SPARE 3 4 CLKREQB_PAD_WAKE 10 10 mmCONFIG_APER_SIZE 0 0x150c 1 0 4294967295 APER_SIZE 0 31 mmCONFIG_CNTL 0 0x1509 4 0 4294967295 CFG_VGA_RAM_EN 0 0 GENMO_MONO_ADDRESS_B 2 2 GRPH_ADRSEL 3 4 VGA_DIS 1 1 mmCONFIG_F0_BASE 0 0x150b 1 0 4294967295 F0_BASE 0 31 mmCONFIG_MEMSIZE 0 0x150a 1 0 4294967295 CONFIG_MEMSIZE 0 31 mmCONFIG_REG_APER_SIZE 0 0x150d 1 0 4294967295 REG_APER_SIZE 0 19 mmHDP_MEM_COHERENCY_FLUSH_CNTL 0 0x1520 1 0 4294967295 HDP_MEM_FLUSH_ADDR 0 0 mmHDP_REG_COHERENCY_FLUSH_CNTL 0 0x1528 1 0 4294967295 HDP_REG_FLUSH_ADDR 0 0 mmHOST_BUSNUM 0 0x153d 1 0 4294967295 HOST_ID 0 15 mmHW_DEBUG 0 0x1515 32 0 4294967295 HW_00_DEBUG 0 0 HW_01_DEBUG 1 1 HW_02_DEBUG 2 2 HW_03_DEBUG 3 3 HW_04_DEBUG 4 4 HW_05_DEBUG 5 5 HW_06_DEBUG 6 6 HW_07_DEBUG 7 7 HW_08_DEBUG 8 8 HW_09_DEBUG 9 9 HW_10_DEBUG 10 10 HW_11_DEBUG 11 11 HW_12_DEBUG 12 12 HW_13_DEBUG 13 13 HW_14_DEBUG 14 14 HW_15_DEBUG 15 15 HW_16_DEBUG 16 16 HW_17_DEBUG 17 17 HW_18_DEBUG 18 18 HW_19_DEBUG 19 19 HW_20_DEBUG 20 20 HW_21_DEBUG 21 21 HW_22_DEBUG 22 22 HW_23_DEBUG 23 23 HW_24_DEBUG 24 24 HW_25_DEBUG 25 25 HW_26_DEBUG 26 26 HW_27_DEBUG 27 27 HW_28_DEBUG 28 28 HW_29_DEBUG 29 29 HW_30_DEBUG 30 30 HW_31_DEBUG 31 31 mmIMPCTL_RESET 0 0x14f5 1 0 4294967295 IMP_SW_RESET 0 0 mmINTERRUPT_CNTL 0 0x151a 7 0 4294967295 GEN_GPIO_INT_EN 9 12 GEN_IH_INT_EN 8 8 IH_DUMMY_RD_EN 1 1 IH_DUMMY_RD_OVERRIDE 0 0 IH_INTR_DLY_CNTR 4 7 IH_REQ_NONSNOOP_EN 3 3 SELECT_INT_GPIO_OUTPUT 13 14 mmINTERRUPT_CNTL2 0 0x151b 1 0 4294967295 IH_DUMMY_RD_ADDR 0 31 mmMASTER_CREDIT_CNTL 0 0x1516 2 0 4294967295 BIF_AZ_RDRET_CREDIT 16 21 BIF_MC_RDRET_CREDIT 0 5 mmMM_CFGREGS_CNTL 0 0x1513 2 0 4294967295 MM_CFG_FUNC_SEL 0 2 MM_WR_TO_CFG_EN 3 3 mmMM_DATA 0 0x1 1 0 4294967295 MM_DATA 0 31 mmMM_INDEX 0 0x0 2 0 4294967295 MM_APER 31 31 MM_OFFSET 0 30 mmMM_INDEX_HI 0 0x6 1 0 4294967295 MM_OFFSET_HI 0 31 mmNEW_REFCLKB_TIMER 0 0x14ea 3 0 4294967295 REFCLK_ON 21 21 REG_STOP_REFCLK_EN 0 0 STOP_REFCLK_TIMER 1 20 mmNEW_REFCLKB_TIMER_1 0 0x14e9 2 0 4294967295 PHY_PLL_PDWN_TIMER 0 9 PLL0_PDNB_EN 10 10 mmPCIE_DATA 0 0xd 1 0 4294967295 PCIE_DATA 0 31 mmPCIE_INDEX 0 0xc 1 0 4294967295 PCIE_INDEX 0 7 mmPEER0_FB_OFFSET_HI 0 0x14f3 1 0 4294967295 PEER0_FB_OFFSET_HI 0 19 mmPEER0_FB_OFFSET_LO 0 0x14f2 2 0 4294967295 PEER0_FB_EN 31 31 PEER0_FB_OFFSET_LO 0 19 mmPEER1_FB_OFFSET_HI 0 0x14f1 1 0 4294967295 PEER1_FB_OFFSET_HI 0 19 mmPEER1_FB_OFFSET_LO 0 0x14f0 2 0 4294967295 PEER1_FB_EN 31 31 PEER1_FB_OFFSET_LO 0 19 mmPEER2_FB_OFFSET_HI 0 0x14ef 1 0 4294967295 PEER2_FB_OFFSET_HI 0 19 mmPEER2_FB_OFFSET_LO 0 0x14ee 2 0 4294967295 PEER2_FB_EN 31 31 PEER2_FB_OFFSET_LO 0 19 mmPEER3_FB_OFFSET_HI 0 0x14ed 1 0 4294967295 PEER3_FB_OFFSET_HI 0 19 mmPEER3_FB_OFFSET_LO 0 0x14ec 2 0 4294967295 PEER3_FB_EN 31 31 PEER3_FB_OFFSET_LO 0 19 mmPEER_REG_RANGE0 0 0x153e 2 0 4294967295 END_ADDR 16 31 START_ADDR 0 15 mmPEER_REG_RANGE1 0 0x153f 2 0 4294967295 END_ADDR 16 31 START_ADDR 0 15 mmSLAVE_HANG_ERROR 0 0x153b 6 0 4294967295 AUDIO_HANG_ERROR 4 4 CEC_HANG_ERROR 5 5 HDP_HANG_ERROR 1 1 ROM_HANG_ERROR 3 3 SRBM_HANG_ERROR 0 0 VGA_HANG_ERROR 2 2 mmSLAVE_HANG_PROTECTION_CNTL 0 0x1536 1 0 4294967295 HANG_PROTECTION_TIMER_SEL 1 3 mmSLAVE_REQ_CREDIT_CNTL 0 0x1517 6 0 4294967295 BIF_AZ_REQ_CREDIT 20 20 BIF_HDP_REQ_CREDIT 10 14 BIF_ROM_REQ_CREDIT 15 15 BIF_SRBM_REQ_CREDIT 0 4 BIF_VGA_REQ_CREDIT 5 8 BIF_XDMA_REQ_CREDIT 25 30 mmSMBCLK_PAD_CNTL 0 0x1523 12 0 4294967295 SMBCLK_PAD_A 0 0 SMBCLK_PAD_CNTL_EN 12 12 SMBCLK_PAD_MODE 2 2 SMBCLK_PAD_SCHMEN 11 11 SMBCLK_PAD_SEL 1 1 SMBCLK_PAD_SLEWN 9 9 SMBCLK_PAD_SN0 5 5 SMBCLK_PAD_SN1 6 6 SMBCLK_PAD_SN2 7 7 SMBCLK_PAD_SN3 8 8 SMBCLK_PAD_SPARE 3 4 SMBCLK_PAD_WAKE 10 10 mmSMBDAT_PAD_CNTL 0 0x1522 12 0 4294967295 SMBDAT_PAD_A 0 0 SMBDAT_PAD_CNTL_EN 12 12 SMBDAT_PAD_MODE 2 2 SMBDAT_PAD_SCHMEN 11 11 SMBDAT_PAD_SEL 1 1 SMBDAT_PAD_SLEWN 9 9 SMBDAT_PAD_SN0 5 5 SMBDAT_PAD_SN1 6 6 SMBDAT_PAD_SN2 7 7 SMBDAT_PAD_SN3 8 8 SMBDAT_PAD_SPARE 3 4 SMBDAT_PAD_WAKE 10 10 mmSMBUS_BACO_DUMMY 0 0x14c6 1 0 4294967295 SMBUS_BACO_DUMMY_DATA 0 31