894 mmMM_INDEX 0 0x0 2 0 4294967295 MM_OFFSET 0 30 MM_APER 31 31 mmMM_INDEX_HI 0 0x6 1 0 4294967295 MM_OFFSET_HI 0 31 mmMM_DATA 0 0x1 1 0 4294967295 MM_DATA 0 31 mmCC_BIF_BX_FUSESTRAP0 0 0x14d7 1 0 4294967295 STRAP_BIF_PX_CAPABLE 1 1 mmBUS_CNTL 0 0x1508 14 0 4294967295 BIOS_ROM_WRT_EN 0 0 BIOS_ROM_DIS 1 1 PMI_IO_DIS 2 2 PMI_MEM_DIS 3 3 PMI_BM_DIS 4 4 PMI_INT_DIS 5 5 VGA_REG_COHERENCY_DIS 6 6 VGA_MEM_COHERENCY_DIS 7 7 BIF_ERR_RTR_BKPRESSURE_EN 8 8 SET_AZ_TC 10 12 SET_MC_TC 13 15 ZERO_BE_WR_EN 16 16 ZERO_BE_RD_EN 17 17 RD_STALL_IO_WR 18 18 mmCONFIG_CNTL 0 0x1509 4 0 4294967295 CFG_VGA_RAM_EN 0 0 VGA_DIS 1 1 GENMO_MONO_ADDRESS_B 2 2 GRPH_ADRSEL 3 4 mmCONFIG_MEMSIZE 0 0x150a 1 0 4294967295 CONFIG_MEMSIZE 0 31 mmCONFIG_F0_BASE 0 0x150b 1 0 4294967295 F0_BASE 0 31 mmCONFIG_APER_SIZE 0 0x150c 1 0 4294967295 APER_SIZE 0 31 mmCONFIG_REG_APER_SIZE 0 0x150d 1 0 4294967295 REG_APER_SIZE 0 19 mmBIF_SCRATCH0 0 0x150e 1 0 4294967295 BIF_SCRATCH0 0 31 mmBIF_SCRATCH1 0 0x150f 1 0 4294967295 BIF_SCRATCH1 0 31 mmBX_RESET_EN 0 0x1514 3 0 4294967295 COR_RESET_EN 0 0 REG_RESET_EN 1 1 STY_RESET_EN 2 2 mmMM_CFGREGS_CNTL 0 0x1513 2 0 4294967295 MM_CFG_FUNC_SEL 0 2 MM_WR_TO_CFG_EN 3 3 mmHW_DEBUG 0 0x1515 32 0 4294967295 HW_00_DEBUG 0 0 HW_01_DEBUG 1 1 HW_02_DEBUG 2 2 HW_03_DEBUG 3 3 HW_04_DEBUG 4 4 HW_05_DEBUG 5 5 HW_06_DEBUG 6 6 HW_07_DEBUG 7 7 HW_08_DEBUG 8 8 HW_09_DEBUG 9 9 HW_10_DEBUG 10 10 HW_11_DEBUG 11 11 HW_12_DEBUG 12 12 HW_13_DEBUG 13 13 HW_14_DEBUG 14 14 HW_15_DEBUG 15 15 HW_16_DEBUG 16 16 HW_17_DEBUG 17 17 HW_18_DEBUG 18 18 HW_19_DEBUG 19 19 HW_20_DEBUG 20 20 HW_21_DEBUG 21 21 HW_22_DEBUG 22 22 HW_23_DEBUG 23 23 HW_24_DEBUG 24 24 HW_25_DEBUG 25 25 HW_26_DEBUG 26 26 HW_27_DEBUG 27 27 HW_28_DEBUG 28 28 HW_29_DEBUG 29 29 HW_30_DEBUG 30 30 HW_31_DEBUG 31 31 mmMASTER_CREDIT_CNTL 0 0x1516 2 0 4294967295 BIF_MC_RDRET_CREDIT 0 6 BIF_AZ_RDRET_CREDIT 16 21 mmSLAVE_REQ_CREDIT_CNTL 0 0x1517 6 0 4294967295 BIF_SRBM_REQ_CREDIT 0 4 BIF_VGA_REQ_CREDIT 5 8 BIF_HDP_REQ_CREDIT 10 14 BIF_ROM_REQ_CREDIT 15 15 BIF_AZ_REQ_CREDIT 20 20 BIF_XDMA_REQ_CREDIT 25 30 mmBX_RESET_CNTL 0 0x1518 1 0 4294967295 LINK_TRAIN_EN 0 0 mmINTERRUPT_CNTL 0 0x151a 7 0 4294967295 IH_DUMMY_RD_OVERRIDE 0 0 IH_DUMMY_RD_EN 1 1 IH_REQ_NONSNOOP_EN 3 3 IH_INTR_DLY_CNTR 4 7 GEN_IH_INT_EN 8 8 GEN_GPIO_INT_EN 9 12 SELECT_INT_GPIO_OUTPUT 13 14 mmINTERRUPT_CNTL2 0 0x151b 1 0 4294967295 IH_DUMMY_RD_ADDR 0 31 mmBIF_DEBUG_CNTL 0 0x151c 12 0 4294967295 DEBUG_EN 0 0 DEBUG_MULTIBLOCKEN 1 1 DEBUG_OUT_EN 2 2 DEBUG_PAD_SEL 3 3 DEBUG_BYTESEL_BLK1 4 4 DEBUG_BYTESEL_BLK2 5 5 DEBUG_SYNC_EN 6 6 DEBUG_SWAP 7 7 DEBUG_IDSEL_BLK1 8 12 DEBUG_IDSEL_BLK2 16 20 DEBUG_IDSEL_XSP 24 24 DEBUG_SYNC_CLKSEL 30 31 mmBIF_DEBUG_MUX 0 0x151d 2 0 4294967295 DEBUG_MUX_BLK1 0 5 DEBUG_MUX_BLK2 8 13 mmBIF_DEBUG_OUT 0 0x151e 1 0 4294967295 DEBUG_OUTPUT 0 16 mmHDP_REG_COHERENCY_FLUSH_CNTL 0 0x1528 1 0 4294967295 HDP_REG_FLUSH_ADDR 0 0 mmHDP_MEM_COHERENCY_FLUSH_CNTL 0 0x1520 1 0 4294967295 HDP_MEM_FLUSH_ADDR 0 0 mmCLKREQB_PAD_CNTL 0 0x1521 12 0 4294967295 CLKREQB_PAD_A 0 0 CLKREQB_PAD_SEL 1 1 CLKREQB_PAD_MODE 2 2 CLKREQB_PAD_SPARE 3 4 CLKREQB_PAD_SN0 5 5 CLKREQB_PAD_SN1 6 6 CLKREQB_PAD_SN2 7 7 CLKREQB_PAD_SN3 8 8 CLKREQB_PAD_SLEWN 9 9 CLKREQB_PAD_WAKE 10 10 CLKREQB_PAD_SCHMEN 11 11 CLKREQB_PAD_CNTL_EN 12 12 mmSMBUS_SLV_CNTL 0 0x14fd 2 0 4294967295 SMB_SOFT_RESET 0 0 SMB_SLV_ADR 1 7 mmSMBUS_SLV_CNTL1 0 0x14fe 4 0 4294967295 SMB_TIMEOUT_THRESHOLD 0 21 SMB_XTALIN_FREQUENCY_SEL 24 24 SMB_TIMEOUT_DIS 25 25 SMB_DAT_HOLD_TIME_MARGIN 26 31 mmSMBDAT_PAD_CNTL 0 0x1522 12 0 4294967295 SMBDAT_PAD_A 0 0 SMBDAT_PAD_SEL 1 1 SMBDAT_PAD_MODE 2 2 SMBDAT_PAD_SPARE 3 4 SMBDAT_PAD_SN0 5 5 SMBDAT_PAD_SN1 6 6 SMBDAT_PAD_SN2 7 7 SMBDAT_PAD_SN3 8 8 SMBDAT_PAD_SLEWN 9 9 SMBDAT_PAD_WAKE 10 10 SMBDAT_PAD_SCHMEN 11 11 SMBDAT_PAD_CNTL_EN 12 12 mmSMBCLK_PAD_CNTL 0 0x1523 12 0 4294967295 SMBCLK_PAD_A 0 0 SMBCLK_PAD_SEL 1 1 SMBCLK_PAD_MODE 2 2 SMBCLK_PAD_SPARE 3 4 SMBCLK_PAD_SN0 5 5 SMBCLK_PAD_SN1 6 6 SMBCLK_PAD_SN2 7 7 SMBCLK_PAD_SN3 8 8 SMBCLK_PAD_SLEWN 9 9 SMBCLK_PAD_WAKE 10 10 SMBCLK_PAD_SCHMEN 11 11 SMBCLK_PAD_CNTL_EN 12 12 mmBIF_XDMA_LO 0 0x14c0 2 0 4294967295 BIF_XDMA_LOWER_BOUND 0 28 BIF_XDMA_APER_EN 31 31 mmBIF_XDMA_HI 0 0x14c1 1 0 4294967295 BIF_XDMA_UPPER_BOUND 0 28 mmBIF_FEATURES_CONTROL_MISC 0 0x14c2 12 0 4294967295 MST_BIF_REQ_EP_DIS 0 0 SLV_BIF_CPL_EP_DIS 1 1 BIF_SLV_REQ_EP_DIS 2 2 BIF_MST_CPL_EP_DIS 3 3 UR_PSN_PKT_REPORT_POISON_DIS 4 4 POST_PSN_ONLY_PKT_REPORT_UR_ALL_DIS 5 5 POST_PSN_ONLY_PKT_REPORT_UR_PART_DIS 6 6 PLL_SWITCH_IMPCTL_CAL_DONE_DIS 7 7 IGNORE_BE_CHECK_GASKET_COMB_DIS 8 8 MC_BIF_REQ_ID_ROUTING_DIS 9 9 AZ_BIF_REQ_ID_ROUTING_DIS 10 10 ATC_PRG_RESP_PASID_UR_EN 11 11 mmBIF_DOORBELL_CNTL 0 0x14c3 4 0 4294967295 SELF_RING_DIS 0 0 TRANS_CHECK_DIS 1 1 UNTRANS_LBACK_EN 2 2 NON_CONSECUTIVE_BE_ZERO_DIS 3 3 mmBIF_SLVARB_MODE 0 0x14c4 1 0 4294967295 SLVARB_MODE 0 1 mmBIF_FB_EN 0 0x1524 2 0 4294967295 FB_READ_EN 0 0 FB_WRITE_EN 1 1 mmBIF_BUSNUM_CNTL1 0 0x1525 1 0 4294967295 ID_MASK 0 7 mmBIF_BUSNUM_LIST0 0 0x1526 4 0 4294967295 ID0 0 7 ID1 8 15 ID2 16 23 ID3 24 31 mmBIF_BUSNUM_LIST1 0 0x1527 4 0 4294967295 ID4 0 7 ID5 8 15 ID6 16 23 ID7 24 31 mmBIF_BUSNUM_CNTL2 0 0x152b 4 0 4294967295 AUTOUPDATE_SEL 0 7 AUTOUPDATE_EN 8 8 HDPREG_CNTL 16 16 ERROR_MULTIPLE_ID_MATCH 17 17 mmBIF_BUSY_DELAY_CNTR 0 0x1529 1 0 4294967295 DELAY_CNT 0 5 mmBIF_PERFMON_CNTL 0 0x152c 5 0 4294967295 PERFCOUNTER_EN 0 0 PERFCOUNTER_RESET0 1 1 PERFCOUNTER_RESET1 2 2 PERF_SEL0 8 12 PERF_SEL1 13 17 mmBIF_PERFCOUNTER0_RESULT 0 0x152d 1 0 4294967295 PERFCOUNTER_RESULT 0 31 mmBIF_PERFCOUNTER1_RESULT 0 0x152e 1 0 4294967295 PERFCOUNTER_RESULT 0 31 mmSLAVE_HANG_PROTECTION_CNTL 0 0x1536 1 0 4294967295 HANG_PROTECTION_TIMER_SEL 1 3 mmGPU_HDP_FLUSH_REQ 0 0x1537 12 0 4294967295 CP0 0 0 CP1 1 1 CP2 2 2 CP3 3 3 CP4 4 4 CP5 5 5 CP6 6 6 CP7 7 7 CP8 8 8 CP9 9 9 SDMA0 10 10 SDMA1 11 11 mmGPU_HDP_FLUSH_DONE 0 0x1538 12 0 4294967295 CP0 0 0 CP1 1 1 CP2 2 2 CP3 3 3 CP4 4 4 CP5 5 5 CP6 6 6 CP7 7 7 CP8 8 8 CP9 9 9 SDMA0 10 10 SDMA1 11 11 mmSLAVE_HANG_ERROR 0 0x153b 9 0 4294967295 SRBM_HANG_ERROR 0 0 HDP_HANG_ERROR 1 1 VGA_HANG_ERROR 2 2 ROM_HANG_ERROR 3 3 AUDIO_HANG_ERROR 4 4 CEC_HANG_ERROR 5 5 XDMA_HANG_ERROR 7 7 DOORBELL_HANG_ERROR 8 8 GARLIC_HANG_ERROR 9 9 mmCAPTURE_HOST_BUSNUM 0 0x153c 1 0 4294967295 CHECK_EN 0 0 mmHOST_BUSNUM 0 0x153d 1 0 4294967295 HOST_ID 0 15 mmPEER_REG_RANGE0 0 0x153e 2 0 4294967295 START_ADDR 0 15 END_ADDR 16 31 mmPEER_REG_RANGE1 0 0x153f 2 0 4294967295 START_ADDR 0 15 END_ADDR 16 31 mmPEER0_FB_OFFSET_HI 0 0x14f3 1 0 4294967295 PEER0_FB_OFFSET_HI 0 19 mmPEER0_FB_OFFSET_LO 0 0x14f2 2 0 4294967295 PEER0_FB_OFFSET_LO 0 19 PEER0_FB_EN 31 31 mmPEER1_FB_OFFSET_HI 0 0x14f1 1 0 4294967295 PEER1_FB_OFFSET_HI 0 19 mmPEER1_FB_OFFSET_LO 0 0x14f0 2 0 4294967295 PEER1_FB_OFFSET_LO 0 19 PEER1_FB_EN 31 31 mmPEER2_FB_OFFSET_HI 0 0x14ef 1 0 4294967295 PEER2_FB_OFFSET_HI 0 19 mmPEER2_FB_OFFSET_LO 0 0x14ee 2 0 4294967295 PEER2_FB_OFFSET_LO 0 19 PEER2_FB_EN 31 31 mmPEER3_FB_OFFSET_HI 0 0x14ed 1 0 4294967295 PEER3_FB_OFFSET_HI 0 19 mmPEER3_FB_OFFSET_LO 0 0x14ec 2 0 4294967295 PEER3_FB_OFFSET_LO 0 19 PEER3_FB_EN 31 31 mmDBG_BYPASS_SRBM_ACCESS 0 0x14eb 2 0 4294967295 DBG_BYPASS_SRBM_ACCESS_EN 0 0 DBG_APER_AD 1 4 mmSMBUS_BACO_DUMMY 0 0x14c6 1 0 4294967295 SMBUS_BACO_DUMMY_DATA 0 31 mmBIF_DEVFUNCNUM_LIST0 0 0x14e8 4 0 4294967295 DEVFUNC_ID0 0 7 DEVFUNC_ID1 8 15 DEVFUNC_ID2 16 23 DEVFUNC_ID3 24 31 mmBIF_DEVFUNCNUM_LIST1 0 0x14e7 4 0 4294967295 DEVFUNC_ID4 0 7 DEVFUNC_ID5 8 15 DEVFUNC_ID6 16 23 DEVFUNC_ID7 24 31 mmBACO_CNTL 0 0x14e5 16 0 4294967295 BACO_EN 0 0 BACO_BCLK_OFF 1 1 BACO_ISO_DIS 2 2 BACO_POWER_OFF 3 3 BACO_RESET_EN 4 4 BACO_HANG_PROTECTION_EN 5 5 BACO_MODE 6 6 BACO_ANA_ISO_DIS 7 7 RCU_BIF_CONFIG_DONE 8 8 PWRGOOD_BF 9 9 PWRGOOD_GPIO 10 10 PWRGOOD_MEM 11 11 PWRGOOD_DVO 12 12 PWRGOOD_IDSC 13 13 BACO_POWER_OFF_DRAM 16 16 BACO_BF_MEM_PHY_ISO_CNTRL 17 17 mmBF_ANA_ISO_CNTL 0 0x14c7 2 0 4294967295 BF_ANA_ISO_DIS_MASK 0 0 BF_VDDC_ISO_DIS_MASK 1 1 mmMEM_TYPE_CNTL 0 0x14e4 1 0 4294967295 BF_MEM_PHY_G5_G3 0 0 mmBIF_BACO_DEBUG 0 0x14df 1 0 4294967295 BIF_BACO_SCANDUMP_FLG 0 0 mmBIF_BACO_DEBUG_LATCH 0 0x14dc 1 0 4294967295 BIF_BACO_LATCH_FLG 0 0 mmBACO_CNTL_MISC 0 0x14db 3 0 4294967295 BIF_ROM_REQ_DIS 0 0 BIF_AZ_REQ_DIS 1 1 BACO_LINK_RST_WIDTH_SEL 2 3 mmBIF_SSA_PWR_STATUS 0 0x14c8 3 0 4294967295 SSA_GFX_PWR_STATUS 0 0 SSA_DISP_PWR_STATUS 1 1 SSA_MC_PWR_STATUS 2 2 mmBIF_SSA_GFX0_LOWER 0 0x14ca 3 0 4294967295 SSA_GFX0_LOWER 2 17 SSA_GFX0_REG_CMP_EN 30 30 SSA_GFX0_REG_STALL_EN 31 31 mmBIF_SSA_GFX0_UPPER 0 0x14cb 1 0 4294967295 SSA_GFX0_UPPER 2 17 mmBIF_SSA_GFX1_LOWER 0 0x14cc 3 0 4294967295 SSA_GFX1_LOWER 2 17 SSA_GFX1_REG_CMP_EN 30 30 SSA_GFX1_REG_STALL_EN 31 31 mmBIF_SSA_GFX1_UPPER 0 0x14cd 1 0 4294967295 SSA_GFX1_UPPER 2 17 mmBIF_SSA_GFX2_LOWER 0 0x14ce 3 0 4294967295 SSA_GFX2_LOWER 2 17 SSA_GFX2_REG_CMP_EN 30 30 SSA_GFX2_REG_STALL_EN 31 31 mmBIF_SSA_GFX2_UPPER 0 0x14cf 1 0 4294967295 SSA_GFX2_UPPER 2 17 mmBIF_SSA_GFX3_LOWER 0 0x14d0 3 0 4294967295 SSA_GFX3_LOWER 2 17 SSA_GFX3_REG_CMP_EN 30 30 SSA_GFX3_REG_STALL_EN 31 31 mmBIF_SSA_GFX3_UPPER 0 0x14d1 1 0 4294967295 SSA_GFX3_UPPER 2 17 mmBIF_SSA_DISP_LOWER 0 0x14d2 3 0 4294967295 SSA_DISP_LOWER 2 17 SSA_DISP_REG_CMP_EN 30 30 SSA_DISP_REG_STALL_EN 31 31 mmBIF_SSA_DISP_UPPER 0 0x14d3 1 0 4294967295 SSA_DISP_UPPER 2 17 mmBIF_SSA_MC_LOWER 0 0x14d4 4 0 4294967295 SSA_MC_LOWER 2 17 SSA_MC_FB_STALL_EN 29 29 SSA_MC_REG_CMP_EN 30 30 SSA_MC_REG_STALL_EN 31 31 mmBIF_SSA_MC_UPPER 0 0x14d5 1 0 4294967295 SSA_MC_UPPER 2 17 mmIMPCTL_RESET 0 0x14f5 1 0 4294967295 IMP_SW_RESET 0 0 mmGARLIC_FLUSH_CNTL 0 0x1401 18 0 4294967295 CP_RB0_WPTR 0 0 CP_RB1_WPTR 1 1 CP_RB2_WPTR 2 2 UVD_RBC_RB_WPTR 3 3 SDMA0_GFX_RB_WPTR 4 4 SDMA1_GFX_RB_WPTR 5 5 CP_DMA_ME_COMMAND 6 6 CP_DMA_PFP_COMMAND 7 7 SAM_SAB_RBI_WPTR 8 8 SAM_SAB_RBO_WPTR 9 9 VCE_OUT_RB_WPTR 10 10 VCE_RB_WPTR2 11 11 VCE_RB_WPTR 12 12 HOST_DOORBELL 13 13 SELFRING_DOORBELL 14 14 DISPLAY 16 16 IGNORE_MC_DISABLE 30 30 DISABLE_ALL 31 31 mmGARLIC_FLUSH_ADDR_START_0 0 0x1402 3 0 4294967295 ENABLE 0 0 MODE 1 1 ADDR_START 2 31 mmGARLIC_FLUSH_ADDR_START_1 0 0x1404 3 0 4294967295 ENABLE 0 0 MODE 1 1 ADDR_START 2 31 mmGARLIC_FLUSH_ADDR_START_2 0 0x1406 3 0 4294967295 ENABLE 0 0 MODE 1 1 ADDR_START 2 31 mmGARLIC_FLUSH_ADDR_START_3 0 0x1408 3 0 4294967295 ENABLE 0 0 MODE 1 1 ADDR_START 2 31 mmGARLIC_FLUSH_ADDR_START_4 0 0x140a 3 0 4294967295 ENABLE 0 0 MODE 1 1 ADDR_START 2 31 mmGARLIC_FLUSH_ADDR_START_5 0 0x140c 3 0 4294967295 ENABLE 0 0 MODE 1 1 ADDR_START 2 31 mmGARLIC_FLUSH_ADDR_START_6 0 0x140e 3 0 4294967295 ENABLE 0 0 MODE 1 1 ADDR_START 2 31 mmGARLIC_FLUSH_ADDR_START_7 0 0x1410 3 0 4294967295 ENABLE 0 0 MODE 1 1 ADDR_START 2 31 mmGARLIC_FLUSH_ADDR_END_0 0 0x1403 1 0 4294967295 ADDR_END 2 31 mmGARLIC_FLUSH_ADDR_END_1 0 0x1405 1 0 4294967295 ADDR_END 2 31 mmGARLIC_FLUSH_ADDR_END_2 0 0x1407 1 0 4294967295 ADDR_END 2 31 mmGARLIC_FLUSH_ADDR_END_3 0 0x1409 1 0 4294967295 ADDR_END 2 31 mmGARLIC_FLUSH_ADDR_END_4 0 0x140b 1 0 4294967295 ADDR_END 2 31 mmGARLIC_FLUSH_ADDR_END_5 0 0x140d 1 0 4294967295 ADDR_END 2 31 mmGARLIC_FLUSH_ADDR_END_6 0 0x140f 1 0 4294967295 ADDR_END 2 31 mmGARLIC_FLUSH_ADDR_END_7 0 0x1411 1 0 4294967295 ADDR_END 2 31 mmGARLIC_FLUSH_REQ 0 0x1412 1 0 4294967295 FLUSH_REQ 0 0 mmGPU_GARLIC_FLUSH_REQ 0 0x1413 12 0 4294967295 CP0 0 0 CP1 1 1 CP2 2 2 CP3 3 3 CP4 4 4 CP5 5 5 CP6 6 6 CP7 7 7 CP8 8 8 CP9 9 9 SDMA0 10 10 SDMA1 11 11 mmGPU_GARLIC_FLUSH_DONE 0 0x1414 12 0 4294967295 CP0 0 0 CP1 1 1 CP2 2 2 CP3 3 3 CP4 4 4 CP5 5 5 CP6 6 6 CP7 7 7 CP8 8 8 CP9 9 9 SDMA0 10 10 SDMA1 11 11 mmGARLIC_COHE_CP_RB0_WPTR 0 0x1415 1 0 4294967295 ADDRESS 2 18 mmGARLIC_COHE_CP_RB1_WPTR 0 0x1416 1 0 4294967295 ADDRESS 2 18 mmGARLIC_COHE_CP_RB2_WPTR 0 0x1417 1 0 4294967295 ADDRESS 2 18 mmGARLIC_COHE_UVD_RBC_RB_WPTR 0 0x1418 1 0 4294967295 ADDRESS 2 18 mmGARLIC_COHE_SDMA0_GFX_RB_WPTR 0 0x1419 1 0 4294967295 ADDRESS 2 18 mmGARLIC_COHE_SDMA1_GFX_RB_WPTR 0 0x141a 1 0 4294967295 ADDRESS 2 18 mmGARLIC_COHE_CP_DMA_ME_COMMAND 0 0x141b 1 0 4294967295 ADDRESS 2 18 mmGARLIC_COHE_CP_DMA_PFP_COMMAND 0 0x141c 1 0 4294967295 ADDRESS 2 18 mmGARLIC_COHE_SAM_SAB_RBI_WPTR 0 0x141d 1 0 4294967295 ADDRESS 2 18 mmGARLIC_COHE_SAM_SAB_RBO_WPTR 0 0x141e 1 0 4294967295 ADDRESS 2 18 mmGARLIC_COHE_VCE_OUT_RB_WPTR 0 0x141f 1 0 4294967295 ADDRESS 2 18 mmGARLIC_COHE_VCE_RB_WPTR2 0 0x1420 1 0 4294967295 ADDRESS 2 18 mmGARLIC_COHE_VCE_RB_WPTR 0 0x1421 1 0 4294967295 ADDRESS 2 18 mmBIOS_SCRATCH_0 0 0x5c9 1 0 4294967295 BIOS_SCRATCH_0 0 31 mmBIOS_SCRATCH_1 0 0x5ca 1 0 4294967295 BIOS_SCRATCH_1 0 31 mmBIOS_SCRATCH_2 0 0x5cb 1 0 4294967295 BIOS_SCRATCH_2 0 31 mmBIOS_SCRATCH_3 0 0x5cc 1 0 4294967295 BIOS_SCRATCH_3 0 31 mmBIOS_SCRATCH_4 0 0x5cd 1 0 4294967295 BIOS_SCRATCH_4 0 31 mmBIOS_SCRATCH_5 0 0x5ce 1 0 4294967295 BIOS_SCRATCH_5 0 31 mmBIOS_SCRATCH_6 0 0x5cf 1 0 4294967295 BIOS_SCRATCH_6 0 31 mmBIOS_SCRATCH_7 0 0x5d0 1 0 4294967295 BIOS_SCRATCH_7 0 31 mmBIOS_SCRATCH_8 0 0x5d1 1 0 4294967295 BIOS_SCRATCH_8 0 31 mmBIOS_SCRATCH_9 0 0x5d2 1 0 4294967295 BIOS_SCRATCH_9 0 31 mmBIOS_SCRATCH_10 0 0x5d3 1 0 4294967295 BIOS_SCRATCH_10 0 31 mmBIOS_SCRATCH_11 0 0x5d4 1 0 4294967295 BIOS_SCRATCH_11 0 31 mmBIOS_SCRATCH_12 0 0x5d5 1 0 4294967295 BIOS_SCRATCH_12 0 31 mmBIOS_SCRATCH_13 0 0x5d6 1 0 4294967295 BIOS_SCRATCH_13 0 31 mmBIOS_SCRATCH_14 0 0x5d7 1 0 4294967295 BIOS_SCRATCH_14 0 31 mmBIOS_SCRATCH_15 0 0x5d8 1 0 4294967295 BIOS_SCRATCH_15 0 31 mmVENDOR_ID 0 0x0 1 0 4294967295 VENDOR_ID 0 15 mmDEVICE_ID 0 0x0 1 0 4294967295 DEVICE_ID 0 15 mmCOMMAND 0 0x1 11 0 4294967295 IO_ACCESS_EN 0 0 MEM_ACCESS_EN 1 1 BUS_MASTER_EN 2 2 SPECIAL_CYCLE_EN 3 3 MEM_WRITE_INVALIDATE_EN 4 4 PAL_SNOOP_EN 5 5 PARITY_ERROR_RESPONSE 6 6 AD_STEPPING 7 7 SERR_EN 8 8 FAST_B2B_EN 9 9 INT_DIS 10 10 mmSTATUS 0 0x1 11 0 4294967295 INT_STATUS 3 3 CAP_LIST 4 4 PCI_66_EN 5 5 FAST_BACK_CAPABLE 7 7 MASTER_DATA_PARITY_ERROR 8 8 DEVSEL_TIMING 9 10 SIGNAL_TARGET_ABORT 11 11 RECEIVED_TARGET_ABORT 12 12 RECEIVED_MASTER_ABORT 13 13 SIGNALED_SYSTEM_ERROR 14 14 PARITY_ERROR_DETECTED 15 15 mmREVISION_ID 0 0x2 2 0 4294967295 MINOR_REV_ID 0 3 MAJOR_REV_ID 4 7 mmPROG_INTERFACE 0 0x2 1 0 4294967295 PROG_INTERFACE 0 7 mmSUB_CLASS 0 0x2 1 0 4294967295 SUB_CLASS 0 7 mmBASE_CLASS 0 0x2 1 0 4294967295 BASE_CLASS 0 7 mmCACHE_LINE 0 0x3 1 0 4294967295 CACHE_LINE_SIZE 0 7 mmLATENCY 0 0x3 1 0 4294967295 LATENCY_TIMER 0 7 mmHEADER 0 0x3 2 0 4294967295 HEADER_TYPE 0 6 DEVICE_TYPE 7 7 mmBIST 0 0x3 3 0 4294967295 BIST_COMP 0 3 BIST_STRT 6 6 BIST_CAP 7 7 mmBASE_ADDR_1 0 0x4 1 0 4294967295 BASE_ADDR 0 31 mmBASE_ADDR_2 0 0x5 1 0 4294967295 BASE_ADDR 0 31 mmBASE_ADDR_3 0 0x6 1 0 4294967295 BASE_ADDR 0 31 mmBASE_ADDR_4 0 0x7 1 0 4294967295 BASE_ADDR 0 31 mmBASE_ADDR_5 0 0x8 1 0 4294967295 BASE_ADDR 0 31 mmBASE_ADDR_6 0 0x9 1 0 4294967295 BASE_ADDR 0 31 mmROM_BASE_ADDR 0 0xc 1 0 4294967295 BASE_ADDR 0 31 mmCAP_PTR 0 0xd 1 0 4294967295 CAP_PTR 0 7 mmINTERRUPT_LINE 0 0xf 1 0 4294967295 INTERRUPT_LINE 0 7 mmINTERRUPT_PIN 0 0xf 1 0 4294967295 INTERRUPT_PIN 0 7 mmADAPTER_ID 0 0xb 2 0 4294967295 SUBSYSTEM_VENDOR_ID 0 15 SUBSYSTEM_ID 16 31 mmMIN_GRANT 0 0xf 1 0 4294967295 MIN_GNT 0 7 mmMAX_LATENCY 0 0xf 1 0 4294967295 MAX_LAT 0 7 mmVENDOR_CAP_LIST 0 0x12 3 0 4294967295 CAP_ID 0 7 NEXT_PTR 8 15 LENGTH 16 23 mmADAPTER_ID_W 0 0x13 2 0 4294967295 SUBSYSTEM_VENDOR_ID 0 15 SUBSYSTEM_ID 16 31 mmPMI_CAP_LIST 0 0x14 2 0 4294967295 CAP_ID 0 7 NEXT_PTR 8 15 mmPMI_CAP 0 0x14 7 0 4294967295 VERSION 0 2 PME_CLOCK 3 3 DEV_SPECIFIC_INIT 5 5 AUX_CURRENT 6 8 D1_SUPPORT 9 9 D2_SUPPORT 10 10 PME_SUPPORT 11 15 mmPMI_STATUS_CNTL 0 0x15 9 0 4294967295 POWER_STATE 0 1 NO_SOFT_RESET 3 3 PME_EN 8 8 DATA_SELECT 9 12 DATA_SCALE 13 14 PME_STATUS 15 15 B2_B3_SUPPORT 22 22 BUS_PWR_EN 23 23 PMI_DATA 24 31 mmPCIE_CAP_LIST 0 0x16 2 0 4294967295 CAP_ID 0 7 NEXT_PTR 8 15 mmPCIE_CAP 0 0x16 4 0 4294967295 VERSION 0 3 DEVICE_TYPE 4 7 SLOT_IMPLEMENTED 8 8 INT_MESSAGE_NUM 9 13 mmDEVICE_CAP 0 0x17 9 0 4294967295 MAX_PAYLOAD_SUPPORT 0 2 PHANTOM_FUNC 3 4 EXTENDED_TAG 5 5 L0S_ACCEPTABLE_LATENCY 6 8 L1_ACCEPTABLE_LATENCY 9 11 ROLE_BASED_ERR_REPORTING 15 15 CAPTURED_SLOT_POWER_LIMIT 18 25 CAPTURED_SLOT_POWER_SCALE 26 27 FLR_CAPABLE 28 28 mmDEVICE_CNTL 0 0x18 12 0 4294967295 CORR_ERR_EN 0 0 NON_FATAL_ERR_EN 1 1 FATAL_ERR_EN 2 2 USR_REPORT_EN 3 3 RELAXED_ORD_EN 4 4 MAX_PAYLOAD_SIZE 5 7 EXTENDED_TAG_EN 8 8 PHANTOM_FUNC_EN 9 9 AUX_POWER_PM_EN 10 10 NO_SNOOP_EN 11 11 MAX_READ_REQUEST_SIZE 12 14 INITIATE_FLR 15 15 mmDEVICE_STATUS 0 0x18 6 0 4294967295 CORR_ERR 0 0 NON_FATAL_ERR 1 1 FATAL_ERR 2 2 USR_DETECTED 3 3 AUX_PWR 4 4 TRANSACTIONS_PEND 5 5 mmLINK_CAP 0 0x19 11 0 4294967295 LINK_SPEED 0 3 LINK_WIDTH 4 9 PM_SUPPORT 10 11 L0S_EXIT_LATENCY 12 14 L1_EXIT_LATENCY 15 17 CLOCK_POWER_MANAGEMENT 18 18 SURPRISE_DOWN_ERR_REPORTING 19 19 DL_ACTIVE_REPORTING_CAPABLE 20 20 LINK_BW_NOTIFICATION_CAP 21 21 ASPM_OPTIONALITY_COMPLIANCE 22 22 PORT_NUMBER 24 31 mmLINK_CNTL 0 0x1a 10 0 4294967295 PM_CONTROL 0 1 READ_CPL_BOUNDARY 3 3 LINK_DIS 4 4 RETRAIN_LINK 5 5 COMMON_CLOCK_CFG 6 6 EXTENDED_SYNC 7 7 CLOCK_POWER_MANAGEMENT_EN 8 8 HW_AUTONOMOUS_WIDTH_DISABLE 9 9 LINK_BW_MANAGEMENT_INT_EN 10 10 LINK_AUTONOMOUS_BW_INT_EN 11 11 mmLINK_STATUS 0 0x1a 7 0 4294967295 CURRENT_LINK_SPEED 0 3 NEGOTIATED_LINK_WIDTH 4 9 LINK_TRAINING 11 11 SLOT_CLOCK_CFG 12 12 DL_ACTIVE 13 13 LINK_BW_MANAGEMENT_STATUS 14 14 LINK_AUTONOMOUS_BW_STATUS 15 15 mmDEVICE_CAP2 0 0x1f 10 0 4294967295 CPL_TIMEOUT_RANGE_SUPPORTED 0 3 CPL_TIMEOUT_DIS_SUPPORTED 4 4 ARI_FORWARDING_SUPPORTED 5 5 NO_RO_ENABLED_P2P_PASSING 10 10 LTR_SUPPORTED 11 11 TPH_CPLR_SUPPORTED 12 13 OBFF_SUPPORTED 18 19 EXTENDED_FMT_FIELD_SUPPORTED 20 20 END_END_TLP_PREFIX_SUPPORTED 21 21 MAX_END_END_TLP_PREFIXES 22 23 mmDEVICE_CNTL2 0 0x20 8 0 4294967295 CPL_TIMEOUT_VALUE 0 3 CPL_TIMEOUT_DIS 4 4 ARI_FORWARDING_EN 5 5 IDO_REQUEST_ENABLE 8 8 IDO_COMPLETION_ENABLE 9 9 LTR_EN 10 10 OBFF_EN 13 14 END_END_TLP_PREFIX_BLOCKING 15 15 mmDEVICE_STATUS2 0 0x20 1 0 4294967295 RESERVED 0 15 mmLINK_CAP2 0 0x21 3 0 4294967295 SUPPORTED_LINK_SPEED 1 7 CROSSLINK_SUPPORTED 8 8 RESERVED 9 31 mmLINK_CNTL2 0 0x22 8 0 4294967295 TARGET_LINK_SPEED 0 3 ENTER_COMPLIANCE 4 4 HW_AUTONOMOUS_SPEED_DISABLE 5 5 SELECTABLE_DEEMPHASIS 6 6 XMIT_MARGIN 7 9 ENTER_MOD_COMPLIANCE 10 10 COMPLIANCE_SOS 11 11 COMPLIANCE_DEEMPHASIS 12 15 mmLINK_STATUS2 0 0x22 6 0 4294967295 CUR_DEEMPHASIS_LEVEL 0 0 EQUALIZATION_COMPLETE 1 1 EQUALIZATION_PHASE1_SUCCESS 2 2 EQUALIZATION_PHASE2_SUCCESS 3 3 EQUALIZATION_PHASE3_SUCCESS 4 4 LINK_EQUALIZATION_REQUEST 5 5 mmMSI_CAP_LIST 0 0x28 2 0 4294967295 CAP_ID 0 7 NEXT_PTR 8 15 mmMSI_MSG_CNTL 0 0x28 4 0 4294967295 MSI_EN 0 0 MSI_MULTI_CAP 1 3 MSI_MULTI_EN 4 6 MSI_64BIT 7 7 mmMSI_MSG_ADDR_LO 0 0x29 1 0 4294967295 MSI_MSG_ADDR_LO 2 31 mmMSI_MSG_ADDR_HI 0 0x2a 1 0 4294967295 MSI_MSG_ADDR_HI 0 31 mmMSI_MSG_DATA_64 0 0x2b 1 0 4294967295 MSI_DATA_64 0 15 mmMSI_MSG_DATA 0 0x2a 1 0 4294967295 MSI_DATA 0 15 mmPCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0 0x40 3 0 4294967295 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 mmPCIE_VENDOR_SPECIFIC_HDR 0 0x41 3 0 4294967295 VSEC_ID 0 15 VSEC_REV 16 19 VSEC_LENGTH 20 31 mmPCIE_VENDOR_SPECIFIC1 0 0x42 1 0 4294967295 SCRATCH 0 31 mmPCIE_VENDOR_SPECIFIC2 0 0x43 1 0 4294967295 SCRATCH 0 31 mmPCIE_VC_ENH_CAP_LIST 0 0x44 3 0 4294967295 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 mmPCIE_PORT_VC_CAP_REG1 0 0x45 4 0 4294967295 EXT_VC_COUNT 0 2 LOW_PRIORITY_EXT_VC_COUNT 4 6 REF_CLK 8 9 PORT_ARB_TABLE_ENTRY_SIZE 10 11 mmPCIE_PORT_VC_CAP_REG2 0 0x46 2 0 4294967295 VC_ARB_CAP 0 7 VC_ARB_TABLE_OFFSET 24 31 mmPCIE_PORT_VC_CNTL 0 0x47 2 0 4294967295 LOAD_VC_ARB_TABLE 0 0 VC_ARB_SELECT 1 3 mmPCIE_PORT_VC_STATUS 0 0x47 1 0 4294967295 VC_ARB_TABLE_STATUS 0 0 mmPCIE_VC0_RESOURCE_CAP 0 0x48 4 0 4294967295 PORT_ARB_CAP 0 7 REJECT_SNOOP_TRANS 15 15 MAX_TIME_SLOTS 16 21 PORT_ARB_TABLE_OFFSET 24 31 mmPCIE_VC0_RESOURCE_CNTL 0 0x49 6 0 4294967295 TC_VC_MAP_TC0 0 0 TC_VC_MAP_TC1_7 1 7 LOAD_PORT_ARB_TABLE 16 16 PORT_ARB_SELECT 17 19 VC_ID 24 26 VC_ENABLE 31 31 mmPCIE_VC0_RESOURCE_STATUS 0 0x4a 2 0 4294967295 PORT_ARB_TABLE_STATUS 0 0 VC_NEGOTIATION_PENDING 1 1 mmPCIE_VC1_RESOURCE_CAP 0 0x4b 4 0 4294967295 PORT_ARB_CAP 0 7 REJECT_SNOOP_TRANS 15 15 MAX_TIME_SLOTS 16 21 PORT_ARB_TABLE_OFFSET 24 31 mmPCIE_VC1_RESOURCE_CNTL 0 0x4c 6 0 4294967295 TC_VC_MAP_TC0 0 0 TC_VC_MAP_TC1_7 1 7 LOAD_PORT_ARB_TABLE 16 16 PORT_ARB_SELECT 17 19 VC_ID 24 26 VC_ENABLE 31 31 mmPCIE_VC1_RESOURCE_STATUS 0 0x4d 2 0 4294967295 PORT_ARB_TABLE_STATUS 0 0 VC_NEGOTIATION_PENDING 1 1 mmPCIE_DEV_SERIAL_NUM_ENH_CAP_LIST 0 0x50 3 0 4294967295 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 mmPCIE_DEV_SERIAL_NUM_DW1 0 0x51 1 0 4294967295 SERIAL_NUMBER_LO 0 31 mmPCIE_DEV_SERIAL_NUM_DW2 0 0x52 1 0 4294967295 SERIAL_NUMBER_HI 0 31 mmPCIE_ADV_ERR_RPT_ENH_CAP_LIST 0 0x54 3 0 4294967295 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 mmPCIE_UNCORR_ERR_STATUS 0 0x55 16 0 4294967295 DLP_ERR_STATUS 4 4 SURPDN_ERR_STATUS 5 5 PSN_ERR_STATUS 12 12 FC_ERR_STATUS 13 13 CPL_TIMEOUT_STATUS 14 14 CPL_ABORT_ERR_STATUS 15 15 UNEXP_CPL_STATUS 16 16 RCV_OVFL_STATUS 17 17 MAL_TLP_STATUS 18 18 ECRC_ERR_STATUS 19 19 UNSUPP_REQ_ERR_STATUS 20 20 ACS_VIOLATION_STATUS 21 21 UNCORR_INT_ERR_STATUS 22 22 MC_BLOCKED_TLP_STATUS 23 23 ATOMICOP_EGRESS_BLOCKED_STATUS 24 24 TLP_PREFIX_BLOCKED_ERR_STATUS 25 25 mmPCIE_UNCORR_ERR_MASK 0 0x56 16 0 4294967295 DLP_ERR_MASK 4 4 SURPDN_ERR_MASK 5 5 PSN_ERR_MASK 12 12 FC_ERR_MASK 13 13 CPL_TIMEOUT_MASK 14 14 CPL_ABORT_ERR_MASK 15 15 UNEXP_CPL_MASK 16 16 RCV_OVFL_MASK 17 17 MAL_TLP_MASK 18 18 ECRC_ERR_MASK 19 19 UNSUPP_REQ_ERR_MASK 20 20 ACS_VIOLATION_MASK 21 21 UNCORR_INT_ERR_MASK 22 22 MC_BLOCKED_TLP_MASK 23 23 ATOMICOP_EGRESS_BLOCKED_MASK 24 24 TLP_PREFIX_BLOCKED_ERR_MASK 25 25 mmPCIE_UNCORR_ERR_SEVERITY 0 0x57 16 0 4294967295 DLP_ERR_SEVERITY 4 4 SURPDN_ERR_SEVERITY 5 5 PSN_ERR_SEVERITY 12 12 FC_ERR_SEVERITY 13 13 CPL_TIMEOUT_SEVERITY 14 14 CPL_ABORT_ERR_SEVERITY 15 15 UNEXP_CPL_SEVERITY 16 16 RCV_OVFL_SEVERITY 17 17 MAL_TLP_SEVERITY 18 18 ECRC_ERR_SEVERITY 19 19 UNSUPP_REQ_ERR_SEVERITY 20 20 ACS_VIOLATION_SEVERITY 21 21 UNCORR_INT_ERR_SEVERITY 22 22 MC_BLOCKED_TLP_SEVERITY 23 23 ATOMICOP_EGRESS_BLOCKED_SEVERITY 24 24 TLP_PREFIX_BLOCKED_ERR_SEVERITY 25 25 mmPCIE_CORR_ERR_STATUS 0 0x58 8 0 4294967295 RCV_ERR_STATUS 0 0 BAD_TLP_STATUS 6 6 BAD_DLLP_STATUS 7 7 REPLAY_NUM_ROLLOVER_STATUS 8 8 REPLAY_TIMER_TIMEOUT_STATUS 12 12 ADVISORY_NONFATAL_ERR_STATUS 13 13 CORR_INT_ERR_STATUS 14 14 HDR_LOG_OVFL_STATUS 15 15 mmPCIE_CORR_ERR_MASK 0 0x59 8 0 4294967295 RCV_ERR_MASK 0 0 BAD_TLP_MASK 6 6 BAD_DLLP_MASK 7 7 REPLAY_NUM_ROLLOVER_MASK 8 8 REPLAY_TIMER_TIMEOUT_MASK 12 12 ADVISORY_NONFATAL_ERR_MASK 13 13 CORR_INT_ERR_MASK 14 14 HDR_LOG_OVFL_MASK 15 15 mmPCIE_ADV_ERR_CAP_CNTL 0 0x5a 8 0 4294967295 FIRST_ERR_PTR 0 4 ECRC_GEN_CAP 5 5 ECRC_GEN_EN 6 6 ECRC_CHECK_CAP 7 7 ECRC_CHECK_EN 8 8 MULTI_HDR_RECD_CAP 9 9 MULTI_HDR_RECD_EN 10 10 TLP_PREFIX_LOG_PRESENT 11 11 mmPCIE_HDR_LOG0 0 0x5b 1 0 4294967295 TLP_HDR 0 31 mmPCIE_HDR_LOG1 0 0x5c 1 0 4294967295 TLP_HDR 0 31 mmPCIE_HDR_LOG2 0 0x5d 1 0 4294967295 TLP_HDR 0 31 mmPCIE_HDR_LOG3 0 0x5e 1 0 4294967295 TLP_HDR 0 31 mmPCIE_TLP_PREFIX_LOG0 0 0x62 1 0 4294967295 TLP_PREFIX 0 31 mmPCIE_TLP_PREFIX_LOG1 0 0x63 1 0 4294967295 TLP_PREFIX 0 31 mmPCIE_TLP_PREFIX_LOG2 0 0x64 1 0 4294967295 TLP_PREFIX 0 31 mmPCIE_TLP_PREFIX_LOG3 0 0x65 1 0 4294967295 TLP_PREFIX 0 31 mmPCIE_BAR_ENH_CAP_LIST 0 0x80 3 0 4294967295 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 mmPCIE_BAR1_CAP 0 0x81 1 0 4294967295 BAR_SIZE_SUPPORTED 4 23 mmPCIE_BAR1_CNTL 0 0x82 3 0 4294967295 BAR_INDEX 0 2 BAR_TOTAL_NUM 5 7 BAR_SIZE 8 12 mmPCIE_BAR2_CAP 0 0x83 1 0 4294967295 BAR_SIZE_SUPPORTED 4 23 mmPCIE_BAR2_CNTL 0 0x84 3 0 4294967295 BAR_INDEX 0 2 BAR_TOTAL_NUM 5 7 BAR_SIZE 8 12 mmPCIE_BAR3_CAP 0 0x85 1 0 4294967295 BAR_SIZE_SUPPORTED 4 23 mmPCIE_BAR3_CNTL 0 0x86 3 0 4294967295 BAR_INDEX 0 2 BAR_TOTAL_NUM 5 7 BAR_SIZE 8 12 mmPCIE_BAR4_CAP 0 0x87 1 0 4294967295 BAR_SIZE_SUPPORTED 4 23 mmPCIE_BAR4_CNTL 0 0x88 3 0 4294967295 BAR_INDEX 0 2 BAR_TOTAL_NUM 5 7 BAR_SIZE 8 12 mmPCIE_BAR5_CAP 0 0x89 1 0 4294967295 BAR_SIZE_SUPPORTED 4 23 mmPCIE_BAR5_CNTL 0 0x8a 3 0 4294967295 BAR_INDEX 0 2 BAR_TOTAL_NUM 5 7 BAR_SIZE 8 12 mmPCIE_BAR6_CAP 0 0x8b 1 0 4294967295 BAR_SIZE_SUPPORTED 4 23 mmPCIE_BAR6_CNTL 0 0x8c 3 0 4294967295 BAR_INDEX 0 2 BAR_TOTAL_NUM 5 7 BAR_SIZE 8 12 mmPCIE_PWR_BUDGET_ENH_CAP_LIST 0 0x90 3 0 4294967295 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 mmPCIE_PWR_BUDGET_DATA_SELECT 0 0x91 1 0 4294967295 DATA_SELECT 0 7 mmPCIE_PWR_BUDGET_DATA 0 0x92 6 0 4294967295 BASE_POWER 0 7 DATA_SCALE 8 9 PM_SUB_STATE 10 12 PM_STATE 13 14 TYPE 15 17 POWER_RAIL 18 20 mmPCIE_PWR_BUDGET_CAP 0 0x93 1 0 4294967295 SYSTEM_ALLOCATED 0 0 mmPCIE_DPA_ENH_CAP_LIST 0 0x94 3 0 4294967295 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 mmPCIE_DPA_CAP 0 0x95 5 0 4294967295 SUBSTATE_MAX 0 4 TRANS_LAT_UNIT 8 9 PWR_ALLOC_SCALE 12 13 TRANS_LAT_VAL_0 16 23 TRANS_LAT_VAL_1 24 31 mmPCIE_DPA_LATENCY_INDICATOR 0 0x96 1 0 4294967295 TRANS_LAT_INDICATOR_BITS 0 7 mmPCIE_DPA_STATUS 0 0x97 2 0 4294967295 SUBSTATE_STATUS 0 4 SUBSTATE_CNTL_ENABLED 8 8 mmPCIE_DPA_CNTL 0 0x97 1 0 4294967295 SUBSTATE_CNTL 0 4 mmPCIE_DPA_SUBSTATE_PWR_ALLOC_0 0 0x98 1 0 4294967295 SUBSTATE_PWR_ALLOC 0 7 mmPCIE_DPA_SUBSTATE_PWR_ALLOC_1 0 0x98 1 0 4294967295 SUBSTATE_PWR_ALLOC 0 7 mmPCIE_DPA_SUBSTATE_PWR_ALLOC_2 0 0x98 1 0 4294967295 SUBSTATE_PWR_ALLOC 0 7 mmPCIE_DPA_SUBSTATE_PWR_ALLOC_3 0 0x98 1 0 4294967295 SUBSTATE_PWR_ALLOC 0 7 mmPCIE_DPA_SUBSTATE_PWR_ALLOC_4 0 0x99 1 0 4294967295 SUBSTATE_PWR_ALLOC 0 7 mmPCIE_DPA_SUBSTATE_PWR_ALLOC_5 0 0x99 1 0 4294967295 SUBSTATE_PWR_ALLOC 0 7 mmPCIE_DPA_SUBSTATE_PWR_ALLOC_6 0 0x99 1 0 4294967295 SUBSTATE_PWR_ALLOC 0 7 mmPCIE_DPA_SUBSTATE_PWR_ALLOC_7 0 0x99 1 0 4294967295 SUBSTATE_PWR_ALLOC 0 7 mmPCIE_SECONDARY_ENH_CAP_LIST 0 0x9c 3 0 4294967295 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 mmPCIE_LINK_CNTL3 0 0x9d 3 0 4294967295 PERFORM_EQUALIZATION 0 0 LINK_EQUALIZATION_REQ_INT_EN 1 1 RESERVED 2 31 mmPCIE_LANE_ERROR_STATUS 0 0x9e 2 0 4294967295 LANE_ERROR_STATUS_BITS 0 15 RESERVED 16 31 mmPCIE_LANE_0_EQUALIZATION_CNTL 0 0x9f 5 0 4294967295 DOWNSTREAM_PORT_TX_PRESET 0 3 DOWNSTREAM_PORT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_TX_PRESET 8 11 UPSTREAM_PORT_RX_PRESET_HINT 12 14 RESERVED 15 15 mmPCIE_LANE_1_EQUALIZATION_CNTL 0 0x9f 5 0 4294967295 DOWNSTREAM_PORT_TX_PRESET 0 3 DOWNSTREAM_PORT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_TX_PRESET 8 11 UPSTREAM_PORT_RX_PRESET_HINT 12 14 RESERVED 15 15 mmPCIE_LANE_2_EQUALIZATION_CNTL 0 0xa0 5 0 4294967295 DOWNSTREAM_PORT_TX_PRESET 0 3 DOWNSTREAM_PORT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_TX_PRESET 8 11 UPSTREAM_PORT_RX_PRESET_HINT 12 14 RESERVED 15 15 mmPCIE_LANE_3_EQUALIZATION_CNTL 0 0xa0 5 0 4294967295 DOWNSTREAM_PORT_TX_PRESET 0 3 DOWNSTREAM_PORT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_TX_PRESET 8 11 UPSTREAM_PORT_RX_PRESET_HINT 12 14 RESERVED 15 15 mmPCIE_LANE_4_EQUALIZATION_CNTL 0 0xa1 5 0 4294967295 DOWNSTREAM_PORT_TX_PRESET 0 3 DOWNSTREAM_PORT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_TX_PRESET 8 11 UPSTREAM_PORT_RX_PRESET_HINT 12 14 RESERVED 15 15 mmPCIE_LANE_5_EQUALIZATION_CNTL 0 0xa1 5 0 4294967295 DOWNSTREAM_PORT_TX_PRESET 0 3 DOWNSTREAM_PORT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_TX_PRESET 8 11 UPSTREAM_PORT_RX_PRESET_HINT 12 14 RESERVED 15 15 mmPCIE_LANE_6_EQUALIZATION_CNTL 0 0xa2 5 0 4294967295 DOWNSTREAM_PORT_TX_PRESET 0 3 DOWNSTREAM_PORT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_TX_PRESET 8 11 UPSTREAM_PORT_RX_PRESET_HINT 12 14 RESERVED 15 15 mmPCIE_LANE_7_EQUALIZATION_CNTL 0 0xa2 5 0 4294967295 DOWNSTREAM_PORT_TX_PRESET 0 3 DOWNSTREAM_PORT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_TX_PRESET 8 11 UPSTREAM_PORT_RX_PRESET_HINT 12 14 RESERVED 15 15 mmPCIE_LANE_8_EQUALIZATION_CNTL 0 0xa3 5 0 4294967295 DOWNSTREAM_PORT_TX_PRESET 0 3 DOWNSTREAM_PORT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_TX_PRESET 8 11 UPSTREAM_PORT_RX_PRESET_HINT 12 14 RESERVED 15 15 mmPCIE_LANE_9_EQUALIZATION_CNTL 0 0xa3 5 0 4294967295 DOWNSTREAM_PORT_TX_PRESET 0 3 DOWNSTREAM_PORT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_TX_PRESET 8 11 UPSTREAM_PORT_RX_PRESET_HINT 12 14 RESERVED 15 15 mmPCIE_LANE_10_EQUALIZATION_CNTL 0 0xa4 5 0 4294967295 DOWNSTREAM_PORT_TX_PRESET 0 3 DOWNSTREAM_PORT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_TX_PRESET 8 11 UPSTREAM_PORT_RX_PRESET_HINT 12 14 RESERVED 15 15 mmPCIE_LANE_11_EQUALIZATION_CNTL 0 0xa4 5 0 4294967295 DOWNSTREAM_PORT_TX_PRESET 0 3 DOWNSTREAM_PORT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_TX_PRESET 8 11 UPSTREAM_PORT_RX_PRESET_HINT 12 14 RESERVED 15 15 mmPCIE_LANE_12_EQUALIZATION_CNTL 0 0xa5 5 0 4294967295 DOWNSTREAM_PORT_TX_PRESET 0 3 DOWNSTREAM_PORT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_TX_PRESET 8 11 UPSTREAM_PORT_RX_PRESET_HINT 12 14 RESERVED 15 15 mmPCIE_LANE_13_EQUALIZATION_CNTL 0 0xa5 5 0 4294967295 DOWNSTREAM_PORT_TX_PRESET 0 3 DOWNSTREAM_PORT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_TX_PRESET 8 11 UPSTREAM_PORT_RX_PRESET_HINT 12 14 RESERVED 15 15 mmPCIE_LANE_14_EQUALIZATION_CNTL 0 0xa6 5 0 4294967295 DOWNSTREAM_PORT_TX_PRESET 0 3 DOWNSTREAM_PORT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_TX_PRESET 8 11 UPSTREAM_PORT_RX_PRESET_HINT 12 14 RESERVED 15 15 mmPCIE_LANE_15_EQUALIZATION_CNTL 0 0xa6 5 0 4294967295 DOWNSTREAM_PORT_TX_PRESET 0 3 DOWNSTREAM_PORT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_TX_PRESET 8 11 UPSTREAM_PORT_RX_PRESET_HINT 12 14 RESERVED 15 15 mmPCIE_ACS_ENH_CAP_LIST 0 0xa8 3 0 4294967295 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 mmPCIE_ACS_CAP 0 0xa9 8 0 4294967295 SOURCE_VALIDATION 0 0 TRANSLATION_BLOCKING 1 1 P2P_REQUEST_REDIRECT 2 2 P2P_COMPLETION_REDIRECT 3 3 UPSTREAM_FORWARDING 4 4 P2P_EGRESS_CONTROL 5 5 DIRECT_TRANSLATED_P2P 6 6 EGRESS_CONTROL_VECTOR_SIZE 8 15 mmPCIE_ACS_CNTL 0 0xa9 7 0 4294967295 SOURCE_VALIDATION_EN 0 0 TRANSLATION_BLOCKING_EN 1 1 P2P_REQUEST_REDIRECT_EN 2 2 P2P_COMPLETION_REDIRECT_EN 3 3 UPSTREAM_FORWARDING_EN 4 4 P2P_EGRESS_CONTROL_EN 5 5 DIRECT_TRANSLATED_P2P_EN 6 6 mmPCIE_ATS_ENH_CAP_LIST 0 0xac 3 0 4294967295 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 mmPCIE_ATS_CAP 0 0xad 3 0 4294967295 INVALIDATE_Q_DEPTH 0 4 PAGE_ALIGNED_REQUEST 5 5 GLOBAL_INVALIDATE_SUPPORTED 6 6 mmPCIE_ATS_CNTL 0 0xad 2 0 4294967295 STU 0 4 ATC_ENABLE 15 15 mmPCIE_PAGE_REQ_ENH_CAP_LIST 0 0xb0 3 0 4294967295 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 mmPCIE_PAGE_REQ_CNTL 0 0xb1 2 0 4294967295 PRI_ENABLE 0 0 PRI_RESET 1 1 mmPCIE_PAGE_REQ_STATUS 0 0xb1 4 0 4294967295 RESPONSE_FAILURE 0 0 UNEXPECTED_PAGE_REQ_GRP_INDEX 1 1 STOPPED 8 8 PRG_RESPONSE_PASID_REQUIRED 15 15 mmPCIE_OUTSTAND_PAGE_REQ_CAPACITY 0 0xb2 1 0 4294967295 OUTSTAND_PAGE_REQ_CAPACITY 0 31 mmPCIE_OUTSTAND_PAGE_REQ_ALLOC 0 0xb3 1 0 4294967295 OUTSTAND_PAGE_REQ_ALLOC 0 31 mmPCIE_PASID_ENH_CAP_LIST 0 0xb4 3 0 4294967295 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 mmPCIE_PASID_CAP 0 0xb5 3 0 4294967295 PASID_EXE_PERMISSION_SUPPORTED 1 1 PASID_PRIV_MODE_SUPPORTED 2 2 MAX_PASID_WIDTH 8 12 mmPCIE_PASID_CNTL 0 0xb5 3 0 4294967295 PASID_ENABLE 0 0 PASID_EXE_PERMISSION_ENABLE 1 1 PASID_PRIV_MODE_SUPPORTED_ENABLE 2 2 mmPCIE_TPH_REQR_ENH_CAP_LIST 0 0xb8 3 0 4294967295 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 mmPCIE_TPH_REQR_CAP 0 0xb9 6 0 4294967295 TPH_REQR_NO_ST_MODE_SUPPORTED 0 0 TPH_REQR_INT_VEC_MODE_SUPPORTED 1 1 TPH_REQR_DEV_SPC_MODE_SUPPORTED 2 2 TPH_REQR_EXTND_TPH_REQR_SUPPORED 8 8 TPH_REQR_ST_TABLE_LOCATION 9 10 TPH_REQR_ST_TABLE_SIZE 16 26 mmPCIE_TPH_REQR_CNTL 0 0xba 2 0 4294967295 TPH_REQR_ST_MODE_SEL 0 2 TPH_REQR_EN 8 9 mmPCIE_MC_ENH_CAP_LIST 0 0xbc 3 0 4294967295 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 mmPCIE_MC_CAP 0 0xbd 3 0 4294967295 MC_MAX_GROUP 0 5 MC_WIN_SIZE_REQ 8 13 MC_ECRC_REGEN_SUPP 15 15 mmPCIE_MC_CNTL 0 0xbd 2 0 4294967295 MC_NUM_GROUP 0 5 MC_ENABLE 15 15 mmPCIE_MC_ADDR0 0 0xbe 2 0 4294967295 MC_INDEX_POS 0 5 MC_BASE_ADDR_0 12 31 mmPCIE_MC_ADDR1 0 0xbf 1 0 4294967295 MC_BASE_ADDR_1 0 31 mmPCIE_MC_RCV0 0 0xc0 1 0 4294967295 MC_RECEIVE_0 0 31 mmPCIE_MC_RCV1 0 0xc1 1 0 4294967295 MC_RECEIVE_1 0 31 mmPCIE_MC_BLOCK_ALL0 0 0xc2 1 0 4294967295 MC_BLOCK_ALL_0 0 31 mmPCIE_MC_BLOCK_ALL1 0 0xc3 1 0 4294967295 MC_BLOCK_ALL_1 0 31 mmPCIE_MC_BLOCK_UNTRANSLATED_0 0 0xc4 1 0 4294967295 MC_BLOCK_UNTRANSLATED_0 0 31 mmPCIE_MC_BLOCK_UNTRANSLATED_1 0 0xc5 1 0 4294967295 MC_BLOCK_UNTRANSLATED_1 0 31 mmPCIE_LTR_ENH_CAP_LIST 0 0xc8 3 0 4294967295 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 mmPCIE_LTR_CAP 0 0xc9 4 0 4294967295 LTR_MAX_S_LATENCY_VALUE 0 9 LTR_MAX_S_LATENCY_SCALE 10 12 LTR_MAX_NS_LATENCY_VALUE 16 25 LTR_MAX_NS_LATENCY_SCALE 26 28 mmPCIE_INDEX 0 0xe 1 0 4294967295 PCIE_INDEX 0 31 mmPCIE_DATA 0 0xf 1 0 4294967295 PCIE_DATA 0 31 mmPCIE_INDEX_2 0 0xc 1 0 4294967295 PCIE_INDEX 0 31 mmPCIE_DATA_2 0 0xd 1 0 4294967295 PCIE_DATA 0 31 ixPCIE_RESERVED 2 0x1400000 1 0 4294967295 PCIE_RESERVED 0 31 ixPCIE_SCRATCH 2 0x1400001 1 0 4294967295 PCIE_SCRATCH 0 31 ixPCIE_HW_DEBUG 2 0x1400002 16 0 4294967295 HW_00_DEBUG 0 0 HW_01_DEBUG 1 1 HW_02_DEBUG 2 2 HW_03_DEBUG 3 3 HW_04_DEBUG 4 4 HW_05_DEBUG 5 5 HW_06_DEBUG 6 6 HW_07_DEBUG 7 7 HW_08_DEBUG 8 8 HW_09_DEBUG 9 9 HW_10_DEBUG 10 10 HW_11_DEBUG 11 11 HW_12_DEBUG 12 12 HW_13_DEBUG 13 13 HW_14_DEBUG 14 14 HW_15_DEBUG 15 15 ixPCIE_RX_NUM_NAK 2 0x140000e 1 0 4294967295 RX_NUM_NAK 0 31 ixPCIE_RX_NUM_NAK_GENERATED 2 0x140000f 1 0 4294967295 RX_NUM_NAK_GENERATED 0 31 ixPCIE_CNTL 2 0x1400010 18 0 4294967295 HWINIT_WR_LOCK 0 0 LC_HOT_PLUG_DELAY_SEL 1 3 UR_ERR_REPORT_DIS 7 7 PCIE_MALFORM_ATOMIC_OPS 8 8 PCIE_HT_NP_MEM_WRITE 9 9 RX_SB_ADJ_PAYLOAD_SIZE 10 12 RX_RCB_ATS_UC_DIS 15 15 RX_RCB_REORDER_EN 16 16 RX_RCB_INVALID_SIZE_DIS 17 17 RX_RCB_UNEXP_CPL_DIS 18 18 RX_RCB_CPL_TIMEOUT_TEST_MODE 19 19 RX_RCB_CHANNEL_ORDERING 20 20 RX_RCB_WRONG_ATTR_DIS 21 21 RX_RCB_WRONG_FUNCNUM_DIS 22 22 RX_ATS_TRAN_CPL_SPLIT_DIS 23 23 TX_CPL_DEBUG 24 29 RX_IGNORE_LTR_MSG_UR 30 30 RX_CPL_POSTED_REQ_ORD_EN 31 31 ixPCIE_CONFIG_CNTL 2 0x1400011 7 0 4294967295 DYN_CLK_LATENCY 0 3 CI_MAX_PAYLOAD_SIZE_MODE 16 16 CI_PRIV_MAX_PAYLOAD_SIZE 17 19 CI_MAX_READ_REQUEST_SIZE_MODE 20 20 CI_PRIV_MAX_READ_REQUEST_SIZE 21 23 CI_MAX_READ_SAFE_MODE 24 24 CI_EXTENDED_TAG_EN_OVERRIDE 25 26 ixPCIE_DEBUG_CNTL 2 0x1400012 3 0 4294967295 DEBUG_PORT_EN 0 7 DEBUG_SELECT 8 8 DEBUG_LANE_EN 16 31 ixPCIE_INT_CNTL 2 0x140001a 8 0 4294967295 CORR_ERR_INT_EN 0 0 NON_FATAL_ERR_INT_EN 1 1 FATAL_ERR_INT_EN 2 2 USR_DETECTED_INT_EN 3 3 MISC_ERR_INT_EN 4 4 POWER_STATE_CHG_INT_EN 6 6 LINK_BW_INT_EN 7 7 QUIESCE_RCVD_INT_EN 8 8 ixPCIE_INT_STATUS 2 0x140001b 8 0 4294967295 CORR_ERR_INT_STATUS 0 0 NON_FATAL_ERR_INT_STATUS 1 1 FATAL_ERR_INT_STATUS 2 2 USR_DETECTED_INT_STATUS 3 3 MISC_ERR_INT_STATUS 4 4 POWER_STATE_CHG_INT_STATUS 6 6 LINK_BW_INT_STATUS 7 7 QUIESCE_RCVD_INT_STATUS 8 8 ixPCIE_CNTL2 2 0x140001c 13 0 4294967295 TX_ARB_ROUND_ROBIN_EN 0 0 TX_ARB_SLV_LIMIT 1 5 TX_ARB_MST_LIMIT 6 10 TX_BLOCK_TLP_ON_PM_DIS 11 11 SLV_MEM_LS_EN 16 16 SLV_MEM_AGGRESSIVE_LS_EN 17 17 MST_MEM_LS_EN 18 18 REPLAY_MEM_LS_EN 19 19 SLV_MEM_SD_EN 20 20 SLV_MEM_AGGRESSIVE_SD_EN 21 21 MST_MEM_SD_EN 22 22 REPLAY_MEM_SD_EN 23 23 RX_NP_MEM_WRITE_ENCODING 24 28 ixPCIE_RX_CNTL2 2 0x140001d 9 0 4294967295 RX_IGNORE_EP_INVALIDPASID_UR 0 0 RX_IGNORE_EP_TRANSMRD_UR 1 1 RX_IGNORE_EP_TRANSMWR_UR 2 2 RX_IGNORE_EP_ATSTRANSREQ_UR 3 3 RX_IGNORE_EP_PAGEREQMSG_UR 4 4 RX_IGNORE_EP_INVCPL_UR 5 5 RX_RCB_LATENCY_EN 8 8 RX_RCB_LATENCY_SCALE 9 11 RX_RCB_LATENCY_MAX_COUNT 16 25 ixPCIE_TX_F0_ATTR_CNTL 2 0x140001e 7 0 4294967295 TX_F0_IDO_OVERRIDE_P 0 1 TX_F0_IDO_OVERRIDE_NP 2 3 TX_F0_IDO_OVERRIDE_CPL 4 5 TX_F0_RO_OVERRIDE_P 6 7 TX_F0_RO_OVERRIDE_NP 8 9 TX_F0_SNR_OVERRIDE_P 10 11 TX_F0_SNR_OVERRIDE_NP 12 13 ixPCIE_TX_F1_F2_ATTR_CNTL 2 0x140001f 14 0 4294967295 TX_F1_IDO_OVERRIDE_P 0 1 TX_F1_IDO_OVERRIDE_NP 2 3 TX_F1_IDO_OVERRIDE_CPL 4 5 TX_F1_RO_OVERRIDE_P 6 7 TX_F1_RO_OVERRIDE_NP 8 9 TX_F1_SNR_OVERRIDE_P 10 11 TX_F1_SNR_OVERRIDE_NP 12 13 TX_F2_IDO_OVERRIDE_P 16 17 TX_F2_IDO_OVERRIDE_NP 18 19 TX_F2_IDO_OVERRIDE_CPL 20 21 TX_F2_RO_OVERRIDE_P 22 23 TX_F2_RO_OVERRIDE_NP 24 25 TX_F2_SNR_OVERRIDE_P 26 27 TX_F2_SNR_OVERRIDE_NP 28 29 ixPCIE_CI_CNTL 2 0x1400020 10 0 4294967295 CI_SLAVE_SPLIT_MODE 2 2 CI_SLAVE_GEN_USR_DIS 3 3 CI_MST_CMPL_DUMMY_DATA 4 4 CI_SLV_RC_RD_REQ_SIZE 6 7 CI_SLV_ORDERING_DIS 8 8 CI_RC_ORDERING_DIS 9 9 CI_SLV_CPL_ALLOC_DIS 10 10 CI_SLV_CPL_ALLOC_MODE 11 11 CI_SLV_CPL_ALLOC_SOR 12 12 CI_MST_IGNORE_PAGE_ALIGNED_REQUEST 13 13 ixPCIE_BUS_CNTL 2 0x1400021 3 0 4294967295 PMI_INT_DIS 6 6 IMMEDIATE_PMI_DIS 7 7 TRUE_PM_STATUS_EN 12 12 ixPCIE_LC_STATE6 2 0x1400022 4 0 4294967295 LC_PREV_STATE24 0 5 LC_PREV_STATE25 8 13 LC_PREV_STATE26 16 21 LC_PREV_STATE27 24 29 ixPCIE_LC_STATE7 2 0x1400023 4 0 4294967295 LC_PREV_STATE28 0 5 LC_PREV_STATE29 8 13 LC_PREV_STATE30 16 21 LC_PREV_STATE31 24 29 ixPCIE_LC_STATE8 2 0x1400024 4 0 4294967295 LC_PREV_STATE32 0 5 LC_PREV_STATE33 8 13 LC_PREV_STATE34 16 21 LC_PREV_STATE35 24 29 ixPCIE_LC_STATE9 2 0x1400025 4 0 4294967295 LC_PREV_STATE36 0 5 LC_PREV_STATE37 8 13 LC_PREV_STATE38 16 21 LC_PREV_STATE39 24 29 ixPCIE_LC_STATE10 2 0x1400026 4 0 4294967295 LC_PREV_STATE40 0 5 LC_PREV_STATE41 8 13 LC_PREV_STATE42 16 21 LC_PREV_STATE43 24 29 ixPCIE_LC_STATE11 2 0x1400027 4 0 4294967295 LC_PREV_STATE44 0 5 LC_PREV_STATE45 8 13 LC_PREV_STATE46 16 21 LC_PREV_STATE47 24 29 ixPCIE_LC_STATUS1 2 0x1400028 4 0 4294967295 LC_REVERSE_RCVR 0 0 LC_REVERSE_XMIT 1 1 LC_OPERATING_LINK_WIDTH 2 4 LC_DETECTED_LINK_WIDTH 5 7 ixPCIE_LC_STATUS2 2 0x1400029 2 0 4294967295 LC_TOTAL_INACTIVE_LANES 0 15 LC_TURN_ON_LANE 16 31 ixPCIE_WPR_CNTL 2 0x1400030 7 0 4294967295 WPR_RESET_HOT_RST_EN 0 0 WPR_RESET_LNK_DWN_EN 1 1 WPR_RESET_LNK_DIS_EN 2 2 WPR_RESET_COR_EN 3 3 WPR_RESET_REG_EN 4 4 WPR_RESET_STY_EN 5 5 WPR_RESET_PHY_EN 6 6 ixPCIE_RX_LAST_TLP0 2 0x1400031 1 0 4294967295 RX_LAST_TLP0 0 31 ixPCIE_RX_LAST_TLP1 2 0x1400032 1 0 4294967295 RX_LAST_TLP1 0 31 ixPCIE_RX_LAST_TLP2 2 0x1400033 1 0 4294967295 RX_LAST_TLP2 0 31 ixPCIE_RX_LAST_TLP3 2 0x1400034 1 0 4294967295 RX_LAST_TLP3 0 31 ixPCIE_TX_LAST_TLP0 2 0x1400035 1 0 4294967295 TX_LAST_TLP0 0 31 ixPCIE_TX_LAST_TLP1 2 0x1400036 1 0 4294967295 TX_LAST_TLP1 0 31 ixPCIE_TX_LAST_TLP2 2 0x1400037 1 0 4294967295 TX_LAST_TLP2 0 31 ixPCIE_TX_LAST_TLP3 2 0x1400038 1 0 4294967295 TX_LAST_TLP3 0 31 ixPCIE_I2C_REG_ADDR_EXPAND 2 0x140003a 1 0 4294967295 I2C_REG_ADDR 0 16 ixPCIE_I2C_REG_DATA 2 0x140003b 1 0 4294967295 I2C_REG_DATA 0 31 ixPCIE_CFG_CNTL 2 0x140003c 3 0 4294967295 CFG_EN_DEC_TO_HIDDEN_REG 0 0 CFG_EN_DEC_TO_GEN2_HIDDEN_REG 1 1 CFG_EN_DEC_TO_GEN3_HIDDEN_REG 2 2 ixPCIE_P_CNTL 2 0x1400040 13 0 4294967295 P_PWRDN_EN 0 0 P_SYMALIGN_MODE 1 1 P_SYMALIGN_HW_DEBUG 2 2 P_ELASTDESKEW_HW_DEBUG 3 3 P_IGNORE_CRC_ERR 4 4 P_IGNORE_LEN_ERR 5 5 P_IGNORE_EDB_ERR 6 6 P_IGNORE_IDL_ERR 7 7 P_IGNORE_TOK_ERR 8 8 P_BLK_LOCK_MODE 12 12 P_ALWAYS_USE_FAST_TXCLK 13 13 P_ELEC_IDLE_MODE 14 15 DLP_IGNORE_IN_L1_EN 16 16 ixPCIE_P_BUF_STATUS 2 0x1400041 2 0 4294967295 P_OVERFLOW_ERR 0 15 P_UNDERFLOW_ERR 16 31 ixPCIE_P_DECODER_STATUS 2 0x1400042 1 0 4294967295 P_DECODE_ERR 0 15 ixPCIE_P_MISC_STATUS 2 0x1400043 2 0 4294967295 P_DESKEW_ERR 0 7 P_SYMUNLOCK_ERR 16 31 ixPCIE_P_RCV_L0S_FTS_DET 2 0x1400050 2 0 4294967295 P_RCV_L0S_FTS_DET_MIN 0 7 P_RCV_L0S_FTS_DET_MAX 8 15 ixPCIE_OBFF_CNTL 2 0x1400061 11 0 4294967295 TX_OBFF_PRIV_DISABLE 0 0 TX_OBFF_WAKE_SIMPLE_MODE_EN 1 1 TX_OBFF_HOSTMEM_TO_ACTIVE 2 2 TX_OBFF_SLVCPL_TO_ACTIVE 3 3 TX_OBFF_WAKE_MAX_PULSE_WIDTH 4 7 TX_OBFF_WAKE_MAX_TWO_FALLING_WIDTH 8 11 TX_OBFF_WAKE_SAMPLING_PERIOD 12 15 TX_OBFF_INTR_TO_ACTIVE 16 16 TX_OBFF_ERR_TO_ACTIVE 17 17 TX_OBFF_ANY_MSG_TO_ACTIVE 18 18 TX_OBFF_PENDING_REQ_TO_ACTIVE 20 23 ixPCIE_TX_LTR_CNTL 2 0x1400060 8 0 4294967295 LTR_PRIV_S_SHORT_VALUE 0 2 LTR_PRIV_S_LONG_VALUE 3 5 LTR_PRIV_S_REQUIREMENT 6 6 LTR_PRIV_NS_SHORT_VALUE 7 9 LTR_PRIV_NS_LONG_VALUE 10 12 LTR_PRIV_NS_REQUIREMENT 13 13 LTR_PRIV_MSG_DIS_IN_PM_NON_D0 14 14 LTR_PRIV_RST_LTR_IN_DL_DOWN 15 15 ixPCIE_PERF_COUNT_CNTL 2 0x1400080 3 0 4294967295 GLOBAL_COUNT_EN 0 0 GLOBAL_SHADOW_WR 1 1 GLOBAL_COUNT_RESET 2 2 ixPCIE_PERF_CNTL_TXCLK 2 0x1400081 4 0 4294967295 EVENT0_SEL 0 7 EVENT1_SEL 8 15 COUNTER0_UPPER 16 23 COUNTER1_UPPER 24 31 ixPCIE_PERF_COUNT0_TXCLK 2 0x1400082 1 0 4294967295 COUNTER0 0 31 ixPCIE_PERF_COUNT1_TXCLK 2 0x1400083 1 0 4294967295 COUNTER1 0 31 ixPCIE_PERF_CNTL_MST_R_CLK 2 0x1400084 4 0 4294967295 EVENT0_SEL 0 7 EVENT1_SEL 8 15 COUNTER0_UPPER 16 23 COUNTER1_UPPER 24 31 ixPCIE_PERF_COUNT0_MST_R_CLK 2 0x1400085 1 0 4294967295 COUNTER0 0 31 ixPCIE_PERF_COUNT1_MST_R_CLK 2 0x1400086 1 0 4294967295 COUNTER1 0 31 ixPCIE_PERF_CNTL_MST_C_CLK 2 0x1400087 4 0 4294967295 EVENT0_SEL 0 7 EVENT1_SEL 8 15 COUNTER0_UPPER 16 23 COUNTER1_UPPER 24 31 ixPCIE_PERF_COUNT0_MST_C_CLK 2 0x1400088 1 0 4294967295 COUNTER0 0 31 ixPCIE_PERF_COUNT1_MST_C_CLK 2 0x1400089 1 0 4294967295 COUNTER1 0 31 ixPCIE_PERF_CNTL_SLV_R_CLK 2 0x140008a 4 0 4294967295 EVENT0_SEL 0 7 EVENT1_SEL 8 15 COUNTER0_UPPER 16 23 COUNTER1_UPPER 24 31 ixPCIE_PERF_COUNT0_SLV_R_CLK 2 0x140008b 1 0 4294967295 COUNTER0 0 31 ixPCIE_PERF_COUNT1_SLV_R_CLK 2 0x140008c 1 0 4294967295 COUNTER1 0 31 ixPCIE_PERF_CNTL_SLV_S_C_CLK 2 0x140008d 4 0 4294967295 EVENT0_SEL 0 7 EVENT1_SEL 8 15 COUNTER0_UPPER 16 23 COUNTER1_UPPER 24 31 ixPCIE_PERF_COUNT0_SLV_S_C_CLK 2 0x140008e 1 0 4294967295 COUNTER0 0 31 ixPCIE_PERF_COUNT1_SLV_S_C_CLK 2 0x140008f 1 0 4294967295 COUNTER1 0 31 ixPCIE_PERF_CNTL_SLV_NS_C_CLK 2 0x1400090 4 0 4294967295 EVENT0_SEL 0 7 EVENT1_SEL 8 15 COUNTER0_UPPER 16 23 COUNTER1_UPPER 24 31 ixPCIE_PERF_COUNT0_SLV_NS_C_CLK 2 0x1400091 1 0 4294967295 COUNTER0 0 31 ixPCIE_PERF_COUNT1_SLV_NS_C_CLK 2 0x1400092 1 0 4294967295 COUNTER1 0 31 ixPCIE_PERF_CNTL_EVENT0_PORT_SEL 2 0x1400093 7 0 4294967295 PERF0_PORT_SEL_TXCLK 0 3 PERF0_PORT_SEL_MST_R_CLK 4 7 PERF0_PORT_SEL_MST_C_CLK 8 11 PERF0_PORT_SEL_SLV_R_CLK 12 15 PERF0_PORT_SEL_SLV_S_C_CLK 16 19 PERF0_PORT_SEL_SLV_NS_C_CLK 20 23 PERF0_PORT_SEL_TXCLK2 24 27 ixPCIE_PERF_CNTL_EVENT1_PORT_SEL 2 0x1400094 7 0 4294967295 PERF1_PORT_SEL_TXCLK 0 3 PERF1_PORT_SEL_MST_R_CLK 4 7 PERF1_PORT_SEL_MST_C_CLK 8 11 PERF1_PORT_SEL_SLV_R_CLK 12 15 PERF1_PORT_SEL_SLV_S_C_CLK 16 19 PERF1_PORT_SEL_SLV_NS_C_CLK 20 23 PERF1_PORT_SEL_TXCLK2 24 27 ixPCIE_PERF_CNTL_TXCLK2 2 0x1400095 4 0 4294967295 EVENT0_SEL 0 7 EVENT1_SEL 8 15 COUNTER0_UPPER 16 23 COUNTER1_UPPER 24 31 ixPCIE_PERF_COUNT0_TXCLK2 2 0x1400096 1 0 4294967295 COUNTER0 0 31 ixPCIE_PERF_COUNT1_TXCLK2 2 0x1400097 1 0 4294967295 COUNTER1 0 31 ixPCIE_STRAP_F0 2 0x14000b0 18 0 4294967295 STRAP_F0_EN 0 0 STRAP_F0_LEGACY_DEVICE_TYPE_EN 1 1 STRAP_F0_MSI_EN 2 2 STRAP_F0_VC_EN 3 3 STRAP_F0_DSN_EN 4 4 STRAP_F0_AER_EN 5 5 STRAP_F0_ACS_EN 6 6 STRAP_F0_BAR_EN 7 7 STRAP_F0_PWR_EN 8 8 STRAP_F0_DPA_EN 9 9 STRAP_F0_ATS_EN 10 10 STRAP_F0_PAGE_REQ_EN 11 11 STRAP_F0_PASID_EN 12 12 STRAP_F0_ECRC_CHECK_EN 13 13 STRAP_F0_ECRC_GEN_EN 14 14 STRAP_F0_CPL_ABORT_ERR_EN 15 15 STRAP_F0_POISONED_ADVISORY_NONFATAL 16 16 STRAP_F0_MC_EN 17 17 ixPCIE_STRAP_F1 2 0x14000b1 17 0 4294967295 STRAP_F1_EN 0 0 STRAP_F1_LEGACY_DEVICE_TYPE_EN 1 1 STRAP_F1_MSI_EN 2 2 STRAP_F1_VC_EN 3 3 STRAP_F1_DSN_EN 4 4 STRAP_F1_AER_EN 5 5 STRAP_F1_ACS_EN 6 6 STRAP_F1_BAR_EN 7 7 STRAP_F1_PWR_EN 8 8 STRAP_F1_DPA_EN 9 9 STRAP_F1_ATS_EN 10 10 STRAP_F1_PAGE_REQ_EN 11 11 STRAP_F1_PASID_EN 12 12 STRAP_F1_ECRC_CHECK_EN 13 13 STRAP_F1_ECRC_GEN_EN 14 14 STRAP_F1_CPL_ABORT_ERR_EN 15 15 STRAP_F1_POISONED_ADVISORY_NONFATAL 16 16 ixPCIE_STRAP_F2 2 0x14000b2 17 0 4294967295 STRAP_F2_EN 0 0 STRAP_F2_LEGACY_DEVICE_TYPE_EN 1 1 STRAP_F2_MSI_EN 2 2 STRAP_F2_VC_EN 3 3 STRAP_F2_DSN_EN 4 4 STRAP_F2_AER_EN 5 5 STRAP_F2_ACS_EN 6 6 STRAP_F2_BAR_EN 7 7 STRAP_F2_PWR_EN 8 8 STRAP_F2_DPA_EN 9 9 STRAP_F2_ATS_EN 10 10 STRAP_F2_PAGE_REQ_EN 11 11 STRAP_F2_PASID_EN 12 12 STRAP_F2_ECRC_CHECK_EN 13 13 STRAP_F2_ECRC_GEN_EN 14 14 STRAP_F2_CPL_ABORT_ERR_EN 15 15 STRAP_F2_POISONED_ADVISORY_NONFATAL 16 16 ixPCIE_STRAP_F3 2 0x14000b3 1 0 4294967295 RESERVED 0 31 ixPCIE_STRAP_F4 2 0x14000b4 1 0 4294967295 RESERVED 0 31 ixPCIE_STRAP_F5 2 0x14000b5 1 0 4294967295 RESERVED 0 31 ixPCIE_STRAP_F6 2 0x14000b6 1 0 4294967295 RESERVED 0 31 ixPCIE_STRAP_F7 2 0x14000b7 1 0 4294967295 RESERVED 0 31 ixPCIE_STRAP_MISC 2 0x14000c0 13 0 4294967295 STRAP_LINK_CONFIG 0 3 STRAP_TL_ALT_BUF_EN 4 4 STRAP_MAX_PASID_WIDTH 8 12 STRAP_PASID_EXE_PERMISSION_SUPPORTED 13 13 STRAP_PASID_PRIV_MODE_SUPPORTED 14 14 STRAP_PASID_GLOBAL_INVALIDATE_SUPPORTED 15 15 STRAP_CLK_PM_EN 24 24 STRAP_ECN1P1_EN 25 25 STRAP_EXT_VC_COUNT 26 26 STRAP_REVERSE_ALL 28 28 STRAP_MST_ADR64_EN 29 29 STRAP_FLR_EN 30 30 STRAP_INTERNAL_ERR_EN 31 31 ixPCIE_STRAP_MISC2 2 0x14000c1 4 0 4294967295 STRAP_GEN2_COMPLIANCE 1 1 STRAP_MSTCPL_TIMEOUT_EN 2 2 STRAP_GEN3_COMPLIANCE 3 3 STRAP_TPH_SUPPORTED 4 4 ixPCIE_STRAP_PI 2 0x14000c2 3 0 4294967295 STRAP_QUICKSIM_START 0 0 STRAP_TEST_TOGGLE_PATTERN 28 28 STRAP_TEST_TOGGLE_MODE 29 29 ixPCIE_STRAP_I2C_BD 2 0x14000c4 2 0 4294967295 STRAP_BIF_I2C_SLV_ADR 0 6 STRAP_BIF_DBG_I2C_EN 7 7 ixPCIE_PRBS_CLR 2 0x14000c8 2 0 4294967295 PRBS_CLR 0 15 PRBS_CHECKER_DEBUG_BUS_SELECT 16 19 ixPCIE_PRBS_STATUS1 2 0x14000c9 2 0 4294967295 PRBS_ERRSTAT 0 15 PRBS_LOCKED 16 31 ixPCIE_PRBS_STATUS2 2 0x14000ca 1 0 4294967295 PRBS_BITCNT_DONE 0 15 ixPCIE_PRBS_FREERUN 2 0x14000cb 1 0 4294967295 PRBS_FREERUN 0 15 ixPCIE_PRBS_MISC 2 0x14000cc 8 0 4294967295 PRBS_EN 0 0 PRBS_TEST_MODE 1 2 PRBS_USER_PATTERN_TOGGLE 3 3 PRBS_8BIT_SEL 4 4 PRBS_COMMA_NUM 5 6 PRBS_LOCK_CNT 7 11 PRBS_DATA_RATE 14 15 PRBS_CHK_ERR_MASK 16 31 ixPCIE_PRBS_USER_PATTERN 2 0x14000cd 1 0 4294967295 PRBS_USER_PATTERN 0 29 ixPCIE_PRBS_LO_BITCNT 2 0x14000ce 1 0 4294967295 PRBS_LO_BITCNT 0 31 ixPCIE_PRBS_HI_BITCNT 2 0x14000cf 1 0 4294967295 PRBS_HI_BITCNT 0 7 ixPCIE_PRBS_ERRCNT_0 2 0x14000d0 1 0 4294967295 PRBS_ERRCNT_0 0 31 ixPCIE_PRBS_ERRCNT_1 2 0x14000d1 1 0 4294967295 PRBS_ERRCNT_1 0 31 ixPCIE_PRBS_ERRCNT_2 2 0x14000d2 1 0 4294967295 PRBS_ERRCNT_2 0 31 ixPCIE_PRBS_ERRCNT_3 2 0x14000d3 1 0 4294967295 PRBS_ERRCNT_3 0 31 ixPCIE_PRBS_ERRCNT_4 2 0x14000d4 1 0 4294967295 PRBS_ERRCNT_4 0 31 ixPCIE_PRBS_ERRCNT_5 2 0x14000d5 1 0 4294967295 PRBS_ERRCNT_5 0 31 ixPCIE_PRBS_ERRCNT_6 2 0x14000d6 1 0 4294967295 PRBS_ERRCNT_6 0 31 ixPCIE_PRBS_ERRCNT_7 2 0x14000d7 1 0 4294967295 PRBS_ERRCNT_7 0 31 ixPCIE_PRBS_ERRCNT_8 2 0x14000d8 1 0 4294967295 PRBS_ERRCNT_8 0 31 ixPCIE_PRBS_ERRCNT_9 2 0x14000d9 1 0 4294967295 PRBS_ERRCNT_9 0 31 ixPCIE_PRBS_ERRCNT_10 2 0x14000da 1 0 4294967295 PRBS_ERRCNT_10 0 31 ixPCIE_PRBS_ERRCNT_11 2 0x14000db 1 0 4294967295 PRBS_ERRCNT_11 0 31 ixPCIE_PRBS_ERRCNT_12 2 0x14000dc 1 0 4294967295 PRBS_ERRCNT_12 0 31 ixPCIE_PRBS_ERRCNT_13 2 0x14000dd 1 0 4294967295 PRBS_ERRCNT_13 0 31 ixPCIE_PRBS_ERRCNT_14 2 0x14000de 1 0 4294967295 PRBS_ERRCNT_14 0 31 ixPCIE_PRBS_ERRCNT_15 2 0x14000df 1 0 4294967295 PRBS_ERRCNT_15 0 31 ixPCIE_F0_DPA_CAP 2 0x14000e0 4 0 4294967295 TRANS_LAT_UNIT 8 9 PWR_ALLOC_SCALE 12 13 TRANS_LAT_VAL_0 16 23 TRANS_LAT_VAL_1 24 31 ixPCIE_F0_DPA_LATENCY_INDICATOR 2 0x14000e4 1 0 4294967295 TRANS_LAT_INDICATOR_BITS 0 7 ixPCIE_F0_DPA_CNTL 2 0x14000e5 1 0 4294967295 SUBSTATE_STATUS 0 4 ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0 2 0x14000e7 1 0 4294967295 SUBSTATE_PWR_ALLOC 0 7 ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1 2 0x14000e8 1 0 4294967295 SUBSTATE_PWR_ALLOC 0 7 ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2 2 0x14000e9 1 0 4294967295 SUBSTATE_PWR_ALLOC 0 7 ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3 2 0x14000ea 1 0 4294967295 SUBSTATE_PWR_ALLOC 0 7 ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4 2 0x14000eb 1 0 4294967295 SUBSTATE_PWR_ALLOC 0 7 ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5 2 0x14000ec 1 0 4294967295 SUBSTATE_PWR_ALLOC 0 7 ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6 2 0x14000ed 1 0 4294967295 SUBSTATE_PWR_ALLOC 0 7 ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7 2 0x14000ee 1 0 4294967295 SUBSTATE_PWR_ALLOC 0 7 ixPCIEP_RESERVED 2 0x10010000 1 0 4294967295 PCIEP_RESERVED 0 31 ixPCIEP_SCRATCH 2 0x10010001 1 0 4294967295 PCIEP_SCRATCH 0 31 ixPCIEP_HW_DEBUG 2 0x10010002 16 0 4294967295 HW_00_DEBUG 0 0 HW_01_DEBUG 1 1 HW_02_DEBUG 2 2 HW_03_DEBUG 3 3 HW_04_DEBUG 4 4 HW_05_DEBUG 5 5 HW_06_DEBUG 6 6 HW_07_DEBUG 7 7 HW_08_DEBUG 8 8 HW_09_DEBUG 9 9 HW_10_DEBUG 10 10 HW_11_DEBUG 11 11 HW_12_DEBUG 12 12 HW_13_DEBUG 13 13 HW_14_DEBUG 14 14 HW_15_DEBUG 15 15 ixPCIEP_PORT_CNTL 2 0x10010010 10 0 4294967295 SLV_PORT_REQ_EN 0 0 CI_SNOOP_OVERRIDE 1 1 HOTPLUG_MSG_EN 2 2 NATIVE_PME_EN 3 3 PWR_FAULT_EN 4 4 PMI_BM_DIS 5 5 SEQNUM_DEBUG_MODE 6 6 CI_SLV_CPL_STATIC_ALLOC_LIMIT_S 8 14 CI_MAX_CPL_PAYLOAD_SIZE_MODE 16 17 CI_PRIV_MAX_CPL_PAYLOAD_SIZE 18 20 ixPCIE_TX_CNTL 2 0x10010020 11 0 4294967295 TX_SNR_OVERRIDE 10 11 TX_RO_OVERRIDE 12 13 TX_PACK_PACKET_DIS 14 14 TX_FLUSH_TLP_DIS 15 15 TX_CPL_PASS_P 20 20 TX_NP_PASS_P 21 21 TX_CLEAR_EXTRA_PM_REQS 22 22 TX_FC_UPDATE_TIMEOUT_DIS 23 23 TX_F0_TPH_DIS 24 24 TX_F1_TPH_DIS 25 25 TX_F2_TPH_DIS 26 26 ixPCIE_TX_REQUESTER_ID 2 0x10010021 3 0 4294967295 TX_REQUESTER_ID_FUNCTION 0 2 TX_REQUESTER_ID_DEVICE 3 7 TX_REQUESTER_ID_BUS 8 15 ixPCIE_TX_VENDOR_SPECIFIC 2 0x10010022 1 0 4294967295 TX_VENDOR_DATA 0 23 ixPCIE_TX_REQUEST_NUM_CNTL 2 0x10010023 3 0 4294967295 TX_NUM_OUTSTANDING_NP 24 29 TX_NUM_OUTSTANDING_NP_VC1_EN 30 30 TX_NUM_OUTSTANDING_NP_EN 31 31 ixPCIE_TX_SEQ 2 0x10010024 2 0 4294967295 TX_NEXT_TRANSMIT_SEQ 0 11 TX_ACKD_SEQ 16 27 ixPCIE_TX_REPLAY 2 0x10010025 3 0 4294967295 TX_REPLAY_NUM 0 2 TX_REPLAY_TIMER_OVERWRITE 15 15 TX_REPLAY_TIMER 16 31 ixPCIE_TX_ACK_LATENCY_LIMIT 2 0x10010026 2 0 4294967295 TX_ACK_LATENCY_LIMIT 0 11 TX_ACK_LATENCY_LIMIT_OVERWRITE 12 12 ixPCIE_TX_CREDITS_ADVT_P 2 0x10010030 2 0 4294967295 TX_CREDITS_ADVT_PD 0 11 TX_CREDITS_ADVT_PH 16 23 ixPCIE_TX_CREDITS_ADVT_NP 2 0x10010031 2 0 4294967295 TX_CREDITS_ADVT_NPD 0 11 TX_CREDITS_ADVT_NPH 16 23 ixPCIE_TX_CREDITS_ADVT_CPL 2 0x10010032 2 0 4294967295 TX_CREDITS_ADVT_CPLD 0 11 TX_CREDITS_ADVT_CPLH 16 23 ixPCIE_TX_CREDITS_INIT_P 2 0x10010033 2 0 4294967295 TX_CREDITS_INIT_PD 0 11 TX_CREDITS_INIT_PH 16 23 ixPCIE_TX_CREDITS_INIT_NP 2 0x10010034 2 0 4294967295 TX_CREDITS_INIT_NPD 0 11 TX_CREDITS_INIT_NPH 16 23 ixPCIE_TX_CREDITS_INIT_CPL 2 0x10010035 2 0 4294967295 TX_CREDITS_INIT_CPLD 0 11 TX_CREDITS_INIT_CPLH 16 23 ixPCIE_TX_CREDITS_STATUS 2 0x10010036 12 0 4294967295 TX_CREDITS_ERR_PD 0 0 TX_CREDITS_ERR_PH 1 1 TX_CREDITS_ERR_NPD 2 2 TX_CREDITS_ERR_NPH 3 3 TX_CREDITS_ERR_CPLD 4 4 TX_CREDITS_ERR_CPLH 5 5 TX_CREDITS_CUR_STATUS_PD 16 16 TX_CREDITS_CUR_STATUS_PH 17 17 TX_CREDITS_CUR_STATUS_NPD 18 18 TX_CREDITS_CUR_STATUS_NPH 19 19 TX_CREDITS_CUR_STATUS_CPLD 20 20 TX_CREDITS_CUR_STATUS_CPLH 21 21 ixPCIE_TX_CREDITS_FCU_THRESHOLD 2 0x10010037 6 0 4294967295 TX_FCU_THRESHOLD_P_VC0 0 2 TX_FCU_THRESHOLD_NP_VC0 4 6 TX_FCU_THRESHOLD_CPL_VC0 8 10 TX_FCU_THRESHOLD_P_VC1 16 18 TX_FCU_THRESHOLD_NP_VC1 20 22 TX_FCU_THRESHOLD_CPL_VC1 24 26 ixPCIE_P_PORT_LANE_STATUS 2 0x10010050 2 0 4294967295 PORT_LANE_REVERSAL 0 0 PHY_LINK_WIDTH 1 6 ixPCIE_FC_P 2 0x10010060 2 0 4294967295 PD_CREDITS 0 7 PH_CREDITS 8 15 ixPCIE_FC_NP 2 0x10010061 2 0 4294967295 NPD_CREDITS 0 7 NPH_CREDITS 8 15 ixPCIE_FC_CPL 2 0x10010062 2 0 4294967295 CPLD_CREDITS 0 7 CPLH_CREDITS 8 15 ixPCIE_ERR_CNTL 2 0x1001006a 16 0 4294967295 ERR_REPORTING_DIS 0 0 STRAP_FIRST_RCVD_ERR_LOG 1 1 RX_DROP_ECRC_FAILURES 2 2 TX_GENERATE_LCRC_ERR 4 4 RX_GENERATE_LCRC_ERR 5 5 TX_GENERATE_ECRC_ERR 6 6 RX_GENERATE_ECRC_ERR 7 7 AER_HDR_LOG_TIMEOUT 8 10 AER_HDR_LOG_F0_TIMER_EXPIRED 11 11 AER_HDR_LOG_F1_TIMER_EXPIRED 12 12 AER_HDR_LOG_F2_TIMER_EXPIRED 13 13 CI_P_SLV_BUF_RD_HALT_STATUS 14 14 CI_NP_SLV_BUF_RD_HALT_STATUS 15 15 CI_SLV_BUF_HALT_RESET 16 16 SEND_ERR_MSG_IMMEDIATELY 17 17 STRAP_POISONED_ADVISORY_NONFATAL 18 18 ixPCIE_RX_CNTL 2 0x10010070 24 0 4294967295 RX_IGNORE_IO_ERR 0 0 RX_IGNORE_BE_ERR 1 1 RX_IGNORE_MSG_ERR 2 2 RX_IGNORE_CRC_ERR 3 3 RX_IGNORE_CFG_ERR 4 4 RX_IGNORE_CPL_ERR 5 5 RX_IGNORE_EP_ERR 6 6 RX_IGNORE_LEN_MISMATCH_ERR 7 7 RX_IGNORE_MAX_PAYLOAD_ERR 8 8 RX_IGNORE_TC_ERR 9 9 RX_IGNORE_CFG_UR 10 10 RX_IGNORE_IO_UR 11 11 RX_IGNORE_AT_ERR 12 12 RX_NAK_IF_FIFO_FULL 13 13 RX_GEN_ONE_NAK 14 14 RX_FC_INIT_FROM_REG 15 15 RX_RCB_CPL_TIMEOUT 16 18 RX_RCB_CPL_TIMEOUT_MODE 19 19 RX_PCIE_CPL_TIMEOUT_DIS 20 20 RX_IGNORE_SHORTPREFIX_ERR 21 21 RX_IGNORE_MAXPREFIX_ERR 22 22 RX_IGNORE_CPLPREFIX_ERR 23 23 RX_IGNORE_INVALIDPASID_ERR 24 24 RX_IGNORE_NOT_PASID_UR 25 25 ixPCIE_RX_EXPECTED_SEQNUM 2 0x10010071 1 0 4294967295 RX_EXPECTED_SEQNUM 0 11 ixPCIE_RX_VENDOR_SPECIFIC 2 0x10010072 2 0 4294967295 RX_VENDOR_DATA 0 23 RX_VENDOR_STATUS 24 24 ixPCIE_RX_CNTL3 2 0x10010074 5 0 4294967295 RX_IGNORE_RC_TRANSMRDPASID_UR 0 0 RX_IGNORE_RC_TRANSMWRPASID_UR 1 1 RX_IGNORE_RC_PRGRESPMSG_UR 2 2 RX_IGNORE_RC_INVREQ_UR 3 3 RX_IGNORE_RC_INVCPLPASID_UR 4 4 ixPCIE_RX_CREDITS_ALLOCATED_P 2 0x10010080 2 0 4294967295 RX_CREDITS_ALLOCATED_PD 0 11 RX_CREDITS_ALLOCATED_PH 16 23 ixPCIE_RX_CREDITS_ALLOCATED_NP 2 0x10010081 2 0 4294967295 RX_CREDITS_ALLOCATED_NPD 0 11 RX_CREDITS_ALLOCATED_NPH 16 23 ixPCIE_RX_CREDITS_ALLOCATED_CPL 2 0x10010082 2 0 4294967295 RX_CREDITS_ALLOCATED_CPLD 0 11 RX_CREDITS_ALLOCATED_CPLH 16 23 ixPCIE_LC_CNTL 2 0x100100a0 20 0 4294967295 LC_DONT_ENTER_L23_IN_D0 1 1 LC_RESET_L_IDLE_COUNT_EN 2 2 LC_RESET_LINK 3 3 LC_16X_CLEAR_TX_PIPE 4 7 LC_L0S_INACTIVITY 8 11 LC_L1_INACTIVITY 12 15 LC_PMI_TO_L1_DIS 16 16 LC_INC_N_FTS_EN 17 17 LC_LOOK_FOR_IDLE_IN_L1L23 18 19 LC_FACTOR_IN_EXT_SYNC 20 20 LC_WAIT_FOR_PM_ACK_DIS 21 21 LC_WAKE_FROM_L23 22 22 LC_L1_IMMEDIATE_ACK 23 23 LC_ASPM_TO_L1_DIS 24 24 LC_DELAY_COUNT 25 26 LC_DELAY_L0S_EXIT 27 27 LC_DELAY_L1_EXIT 28 28 LC_EXTEND_WAIT_FOR_EL_IDLE 29 29 LC_ESCAPE_L1L23_EN 30 30 LC_GATE_RCVR_IDLE 31 31 ixPCIE_LC_CNTL2 2 0x100100b1 24 0 4294967295 LC_TIMED_OUT_STATE 0 5 LC_STATE_TIMED_OUT 6 6 LC_LOOK_FOR_BW_REDUCTION 7 7 LC_MORE_TS2_EN 8 8 LC_X12_NEGOTIATION_DIS 9 9 LC_LINK_UP_REVERSAL_EN 10 10 LC_ILLEGAL_STATE 11 11 LC_ILLEGAL_STATE_RESTART_EN 12 12 LC_WAIT_FOR_OTHER_LANES_MODE 13 13 LC_ELEC_IDLE_MODE 14 15 LC_DISABLE_INFERRED_ELEC_IDLE_DET 16 16 LC_ALLOW_PDWN_IN_L1 17 17 LC_ALLOW_PDWN_IN_L23 18 18 LC_DEASSERT_RX_EN_IN_L0S 19 19 LC_BLOCK_EL_IDLE_IN_L0 20 20 LC_RCV_L0_TO_RCV_L0S_DIS 21 21 LC_ASSERT_INACTIVE_DURING_HOLD 22 22 LC_WAIT_FOR_LANES_IN_LW_NEG 23 24 LC_PWR_DOWN_NEG_OFF_LANES 25 25 LC_DISABLE_LOST_SYM_LOCK_ARCS 26 26 LC_LINK_BW_NOTIFICATION_DIS 27 27 LC_PMI_L1_WAIT_FOR_SLV_IDLE 28 28 LC_TEST_TIMER_SEL 29 30 LC_ENABLE_INFERRED_ELEC_IDLE_FOR_PI 31 31 ixPCIE_LC_CNTL3 2 0x100100b5 23 0 4294967295 LC_SELECT_DEEMPHASIS 0 0 LC_SELECT_DEEMPHASIS_CNTL 1 2 LC_RCVD_DEEMPHASIS 3 3 LC_COMP_TO_DETECT 4 4 LC_RESET_TSX_CNT_IN_RLOCK_EN 5 5 LC_AUTO_SPEED_CHANGE_ATTEMPTS_ALLOWED 6 7 LC_AUTO_SPEED_CHANGE_ATTEMPT_FAILED 8 8 LC_CLR_FAILED_AUTO_SPD_CHANGE_CNT 9 9 LC_ENHANCED_HOT_PLUG_EN 10 10 LC_RCVR_DET_EN_OVERRIDE 11 11 LC_EHP_RX_PHY_CMD 12 13 LC_EHP_TX_PHY_CMD 14 15 LC_CHIP_BIF_USB_IDLE_EN 16 16 LC_L1_BLOCK_RECONFIG_EN 17 17 LC_AUTO_DISABLE_SPEED_SUPPORT_EN 18 18 LC_AUTO_DISABLE_SPEED_SUPPORT_MAX_FAIL_SEL 19 20 LC_FAST_L1_ENTRY_EXIT_EN 21 21 LC_RXPHYCMD_INACTIVE_EN_MODE 22 22 LC_DSC_DONT_ENTER_L23_AFTER_PME_ACK 23 23 LC_HW_VOLTAGE_IF_CONTROL 24 25 LC_VOLTAGE_TIMER_SEL 26 29 LC_GO_TO_RECOVERY 30 30 LC_N_EIE_SEL 31 31 ixPCIE_LC_CNTL4 2 0x100100b6 20 0 4294967295 LC_TX_ENABLE_BEHAVIOUR 0 1 LC_BYPASS_EQ 4 4 LC_REDO_EQ 5 5 LC_EXTEND_EIEOS 6 6 LC_IGNORE_PARITY 7 7 LC_EQ_SEARCH_MODE 8 9 LC_DSC_CHECK_COEFFS_IN_RLOCK 10 10 LC_USC_EQ_NOT_REQD 11 11 LC_USC_GO_TO_EQ 12 12 LC_SET_QUIESCE 13 13 LC_QUIESCE_RCVD 14 14 LC_UNEXPECTED_COEFFS_RCVD 15 15 LC_BYPASS_EQ_REQ_PHASE 16 16 LC_FORCE_PRESET_IN_EQ_REQ_PHASE 17 17 LC_FORCE_PRESET_VALUE 18 21 LC_USC_DELAY_DLLPS 22 22 LC_PCIE_TX_FULL_SWING 23 23 LC_EQ_WAIT_FOR_EVAL_DONE 24 24 LC_8GT_SKIP_ORDER_EN 25 25 LC_WAIT_FOR_MORE_TS_IN_RLOCK 26 31 ixPCIE_LC_CNTL5 2 0x100100b7 4 0 4294967295 LC_EQ_FS_0 0 5 LC_EQ_FS_8 6 11 LC_EQ_LF_0 12 17 LC_EQ_LF_8 18 23 ixPCIE_LC_BW_CHANGE_CNTL 2 0x100100b2 11 0 4294967295 LC_BW_CHANGE_INT_EN 0 0 LC_HW_INIT_SPEED_CHANGE 1 1 LC_SW_INIT_SPEED_CHANGE 2 2 LC_OTHER_INIT_SPEED_CHANGE 3 3 LC_RELIABILITY_SPEED_CHANGE 4 4 LC_FAILED_SPEED_NEG 5 5 LC_LONG_LW_CHANGE 6 6 LC_SHORT_LW_CHANGE 7 7 LC_LW_CHANGE_OTHER 8 8 LC_LW_CHANGE_FAILED 9 9 LC_LINK_BW_NOTIFICATION_DETECT_MODE 10 10 ixPCIE_LC_TRAINING_CNTL 2 0x100100a1 23 0 4294967295 LC_TRAINING_CNTL 0 3 LC_COMPLIANCE_RECEIVE 4 4 LC_LOOK_FOR_MORE_NON_MATCHING_TS1 5 5 LC_L0S_L1_TRAINING_CNTL_EN 6 6 LC_L1_LONG_WAKE_FIX_EN 7 7 LC_POWER_STATE 8 10 LC_DONT_GO_TO_L0S_IF_L1_ARMED 11 11 LC_INIT_SPD_CHG_WITH_CSR_EN 12 12 LC_DISABLE_TRAINING_BIT_ARCH 13 13 LC_EXTEND_WAIT_FOR_SKP 16 16 LC_AUTONOMOUS_CHANGE_OFF 17 17 LC_UPCONFIGURE_CAP_OFF 18 18 LC_HW_LINK_DIS_EN 19 19 LC_LINK_DIS_BY_HW 20 20 LC_STATIC_TX_PIPE_COUNT_EN 21 21 LC_ASPM_L1_NAK_TIMER_SEL 22 23 LC_DONT_DEASSERT_RX_EN_IN_R_SPEED 24 24 LC_DONT_DEASSERT_RX_EN_IN_TEST 25 25 LC_RESET_ASPM_L1_NAK_TIMER 26 26 LC_SHORT_RCFG_TIMEOUT 27 27 LC_ALLOW_TX_L1_CONTROL 28 28 LC_WAIT_FOR_FOM_VALID_AFTER_TRACK 29 29 LC_EXTEND_EQ_REQ_TIME 30 31 ixPCIE_LC_LINK_WIDTH_CNTL 2 0x100100a2 18 0 4294967295 LC_LINK_WIDTH 0 2 LC_LINK_WIDTH_RD 4 6 LC_RECONFIG_ARC_MISSING_ESCAPE 7 7 LC_RECONFIG_NOW 8 8 LC_RENEGOTIATION_SUPPORT 9 9 LC_RENEGOTIATE_EN 10 10 LC_SHORT_RECONFIG_EN 11 11 LC_UPCONFIGURE_SUPPORT 12 12 LC_UPCONFIGURE_DIS 13 13 LC_UPCFG_WAIT_FOR_RCVR_DIS 14 14 LC_UPCFG_TIMER_SEL 15 15 LC_DEASSERT_TX_PDNB 16 16 LC_L1_RECONFIG_EN 17 17 LC_DYNLINK_MST_EN 18 18 LC_DUAL_END_RECONFIG_EN 19 19 LC_UPCONFIGURE_CAPABLE 20 20 LC_DYN_LANES_PWR_STATE 21 22 LC_EQ_REVERSAL_LOGIC_EN 23 23 ixPCIE_LC_N_FTS_CNTL 2 0x100100a3 5 0 4294967295 LC_XMIT_N_FTS 0 7 LC_XMIT_N_FTS_OVERRIDE_EN 8 8 LC_XMIT_FTS_BEFORE_RECOVERY 9 9 LC_XMIT_N_FTS_LIMIT 16 23 LC_N_FTS 24 31 ixPCIE_LC_SPEED_CNTL 2 0x100100a4 28 0 4294967295 LC_GEN2_EN_STRAP 0 0 LC_GEN3_EN_STRAP 1 1 LC_TARGET_LINK_SPEED_OVERRIDE_EN 2 2 LC_TARGET_LINK_SPEED_OVERRIDE 3 4 LC_FORCE_EN_SW_SPEED_CHANGE 5 5 LC_FORCE_DIS_SW_SPEED_CHANGE 6 6 LC_FORCE_EN_HW_SPEED_CHANGE 7 7 LC_FORCE_DIS_HW_SPEED_CHANGE 8 8 LC_INITIATE_LINK_SPEED_CHANGE 9 9 LC_SPEED_CHANGE_ATTEMPTS_ALLOWED 10 11 LC_SPEED_CHANGE_ATTEMPT_FAILED 12 12 LC_CURRENT_DATA_RATE 13 14 LC_DONT_CLR_TARGET_SPD_CHANGE_STATUS 15 15 LC_CLR_FAILED_SPD_CHANGE_CNT 16 16 LC_1_OR_MORE_TS2_SPEED_ARC_EN 17 17 LC_OTHER_SIDE_EVER_SENT_GEN2 18 18 LC_OTHER_SIDE_SUPPORTS_GEN2 19 19 LC_OTHER_SIDE_EVER_SENT_GEN3 20 20 LC_OTHER_SIDE_SUPPORTS_GEN3 21 21 LC_AUTO_RECOVERY_DIS 22 22 LC_SPEED_CHANGE_STATUS 23 23 LC_DATA_RATE_ADVERTISED 24 25 LC_CHECK_DATA_RATE 26 26 LC_MULT_UPSTREAM_AUTO_SPD_CHNG_EN 27 27 LC_INIT_SPEED_NEG_IN_L0s_EN 28 28 LC_INIT_SPEED_NEG_IN_L1_EN 29 29 LC_DONT_CHECK_EQTS_IN_RCFG 30 30 LC_DELAY_COEFF_UPDATE_DIS 31 31 ixPCIE_LC_CDR_CNTL 2 0x100100b3 3 0 4294967295 LC_CDR_TEST_OFF 0 11 LC_CDR_TEST_SETS 12 23 LC_CDR_SET_TYPE 24 25 ixPCIE_LC_LANE_CNTL 2 0x100100b4 2 0 4294967295 LC_CORRUPTED_LANES 0 15 LC_LANE_DIS 16 31 ixPCIE_LC_FORCE_COEFF 2 0x100100b8 5 0 4294967295 LC_FORCE_COEFF 0 0 LC_FORCE_PRE_CURSOR 1 6 LC_FORCE_CURSOR 7 12 LC_FORCE_POST_CURSOR 13 18 LC_3X3_COEFF_SEARCH_EN 19 19 ixPCIE_LC_BEST_EQ_SETTINGS 2 0x100100b9 5 0 4294967295 LC_BEST_PRESET 0 3 LC_BEST_PRECURSOR 4 9 LC_BEST_CURSOR 10 15 LC_BEST_POSTCURSOR 16 21 LC_BEST_FOM 22 29 ixPCIE_LC_FORCE_EQ_REQ_COEFF 2 0x100100ba 6 0 4294967295 LC_FORCE_COEFF_IN_EQ_REQ_PHASE 0 0 LC_FORCE_PRE_CURSOR_REQ 1 6 LC_FORCE_CURSOR_REQ 7 12 LC_FORCE_POST_CURSOR_REQ 13 18 LC_FS_OTHER_END 19 24 LC_LF_OTHER_END 25 30 ixPCIE_LC_STATE0 2 0x100100a5 4 0 4294967295 LC_CURRENT_STATE 0 5 LC_PREV_STATE1 8 13 LC_PREV_STATE2 16 21 LC_PREV_STATE3 24 29 ixPCIE_LC_STATE1 2 0x100100a6 4 0 4294967295 LC_PREV_STATE4 0 5 LC_PREV_STATE5 8 13 LC_PREV_STATE6 16 21 LC_PREV_STATE7 24 29 ixPCIE_LC_STATE2 2 0x100100a7 4 0 4294967295 LC_PREV_STATE8 0 5 LC_PREV_STATE9 8 13 LC_PREV_STATE10 16 21 LC_PREV_STATE11 24 29 ixPCIE_LC_STATE3 2 0x100100a8 4 0 4294967295 LC_PREV_STATE12 0 5 LC_PREV_STATE13 8 13 LC_PREV_STATE14 16 21 LC_PREV_STATE15 24 29 ixPCIE_LC_STATE4 2 0x100100a9 4 0 4294967295 LC_PREV_STATE16 0 5 LC_PREV_STATE17 8 13 LC_PREV_STATE18 16 21 LC_PREV_STATE19 24 29 ixPCIE_LC_STATE5 2 0x100100aa 4 0 4294967295 LC_PREV_STATE20 0 5 LC_PREV_STATE21 8 13 LC_PREV_STATE22 16 21 LC_PREV_STATE23 24 29 ixPCIEP_STRAP_LC 2 0x100100c0 11 0 4294967295 STRAP_FTS_yTSx_COUNT 0 1 STRAP_LONG_yTSx_COUNT 2 3 STRAP_MED_yTSx_COUNT 4 5 STRAP_SHORT_yTSx_COUNT 6 7 STRAP_SKIP_INTERVAL 8 10 STRAP_BYPASS_RCVR_DET 11 11 STRAP_COMPLIANCE_DIS 12 12 STRAP_FORCE_COMPLIANCE 13 13 STRAP_REVERSE_LC_LANES 14 14 STRAP_AUTO_RC_SPEED_NEGOTIATION_DIS 15 15 STRAP_LANE_NEGOTIATION 16 18 ixPCIEP_STRAP_MISC 2 0x100100c1 5 0 4294967295 STRAP_REVERSE_LANES 0 0 STRAP_E2E_PREFIX_EN 1 1 STRAP_EXTENDED_FMT_SUPPORTED 2 2 STRAP_OBFF_SUPPORTED 3 4 STRAP_LTR_SUPPORTED 5 5 ixPCIEP_BCH_ECC_CNTL 2 0x100100d0 3 0 4294967295 STRAP_BCH_ECC_EN 0 0 BCH_ECC_ERROR_THRESHOLD 8 15 BCH_ECC_ERROR_STATUS 16 31 ixPB0_GLB_CTRL_REG0 2 0x1200004 8 0 4294967295 BACKUP 0 15 CFG_IDLEDET_TH 16 17 DBG_RX2TXBYP_SEL 20 22 DBG_RXFEBYP_EN 23 23 DBG_RXPRBS_CLR 24 24 DBG_RXTOGGLE_EN 25 25 DBG_TX2RXLBACK_EN 26 26 TXCFG_CMGOOD_RANGE 30 31 ixPB0_GLB_CTRL_REG1 2 0x1200008 10 0 4294967295 RXDBG_CDR_FR_BYP_EN 0 0 RXDBG_CDR_FR_BYP_VAL 1 6 RXDBG_CDR_PH_BYP_EN 7 7 RXDBG_CDR_PH_BYP_VAL 8 13 RXDBG_D0TH_BYP_EN 14 14 RXDBG_D0TH_BYP_VAL 15 21 RXDBG_D1TH_BYP_EN 22 22 RXDBG_D1TH_BYP_VAL 23 29 TST_LOSPDTST_EN 30 30 PLL_CFG_DISPCLK_DIV 31 31 ixPB0_GLB_CTRL_REG2 2 0x120000c 8 0 4294967295 RXDBG_D2TH_BYP_EN 0 0 RXDBG_D2TH_BYP_VAL 1 7 RXDBG_D3TH_BYP_EN 8 8 RXDBG_D3TH_BYP_VAL 9 15 RXDBG_DXTH_BYP_EN 16 16 RXDBG_DXTH_BYP_VAL 17 23 RXDBG_ETH_BYP_EN 24 24 RXDBG_ETH_BYP_VAL 25 31 ixPB0_GLB_CTRL_REG3 2 0x1200010 14 0 4294967295 RXDBG_SEL 0 4 BG_CFG_LC_REG_VREF0_SEL 5 6 BG_CFG_LC_REG_VREF1_SEL 7 8 BG_CFG_RO_REG_VREF_SEL 9 10 BG_DBG_VREFBYP_EN 11 11 BG_DBG_IREFBYP_EN 12 12 BG_DBG_ANALOG_SEL 14 16 DBG_DLL_CLK_SEL 18 20 PLL_DISPCLK_CMOS_SEL 21 21 DBG_RXPI_OFFSET_BYP_EN 22 22 DBG_RXPI_OFFSET_BYP_VAL 23 26 DBG_RXSWAPDX_BYP_EN 27 27 DBG_RXSWAPDX_BYP_VAL 28 30 DBG_RXLEQ_DCATTN_BYP_OVR_DISABLE 31 31 ixPB0_GLB_CTRL_REG4 2 0x1200014 7 0 4294967295 DBG_RXAPU_INST 0 15 DBG_RXDFEMUX_BYP_VAL 16 17 DBG_RXDFEMUX_BYP_EN 18 18 DBG_RXAPU_EXEC 22 25 DBG_RXDLL_VREG_REF_SEL 26 26 PWRGOOD_OVRD 27 27 DBG_RXRDATA_GATING_DISABLE 28 28 ixPB0_GLB_CTRL_REG5 2 0x1200018 1 0 4294967295 DBG_RXAPU_MODE 0 7 ixPB0_GLB_SCI_STAT_OVRD_REG0 2 0x120001c 9 0 4294967295 IGNR_ALL_SCI_UPDT_L0T3 0 0 IGNR_ALL_SCI_UPDT_L4T7 1 1 IGNR_ALL_SCI_UPDT_L8T11 2 2 IGNR_ALL_SCI_UPDT_L12T15 3 3 IGNR_IMPCAL_ACTIVE_SCI_UPDT 4 4 TXNIMP 8 11 TXPIMP 12 15 RXIMP 16 19 IMPCAL_ACTIVE 20 20 ixPB0_GLB_SCI_STAT_OVRD_REG1 2 0x1200020 15 0 4294967295 IGNR_MODE_SCI_UPDT_L0T3 0 0 IGNR_FREQDIV_SCI_UPDT_L0T3 1 1 IGNR_DLL_LOCK_SCI_UPDT_L0T3 2 2 DLL_LOCK_0 12 12 DLL_LOCK_1 13 13 DLL_LOCK_2 14 14 DLL_LOCK_3 15 15 MODE_0 16 17 FREQDIV_0 18 19 MODE_1 20 21 FREQDIV_1 22 23 MODE_2 24 25 FREQDIV_2 26 27 MODE_3 28 29 FREQDIV_3 30 31 ixPB0_GLB_SCI_STAT_OVRD_REG2 2 0x1200024 15 0 4294967295 IGNR_MODE_SCI_UPDT_L4T7 0 0 IGNR_FREQDIV_SCI_UPDT_L4T7 1 1 IGNR_DLL_LOCK_SCI_UPDT_L4T7 2 2 DLL_LOCK_4 12 12 DLL_LOCK_5 13 13 DLL_LOCK_6 14 14 DLL_LOCK_7 15 15 MODE_4 16 17 FREQDIV_4 18 19 MODE_5 20 21 FREQDIV_5 22 23 MODE_6 24 25 FREQDIV_6 26 27 MODE_7 28 29 FREQDIV_7 30 31 ixPB0_GLB_SCI_STAT_OVRD_REG3 2 0x1200028 15 0 4294967295 IGNR_MODE_SCI_UPDT_L8T11 0 0 IGNR_FREQDIV_SCI_UPDT_L8T11 1 1 IGNR_DLL_LOCK_SCI_UPDT_L8T11 2 2 DLL_LOCK_8 12 12 DLL_LOCK_9 13 13 DLL_LOCK_10 14 14 DLL_LOCK_11 15 15 MODE_8 16 17 FREQDIV_8 18 19 MODE_9 20 21 FREQDIV_9 22 23 MODE_10 24 25 FREQDIV_10 26 27 MODE_11 28 29 FREQDIV_11 30 31 ixPB0_GLB_SCI_STAT_OVRD_REG4 2 0x120002c 15 0 4294967295 IGNR_MODE_SCI_UPDT_L12T15 0 0 IGNR_FREQDIV_SCI_UPDT_L12T15 1 1 IGNR_DLL_LOCK_SCI_UPDT_L12T15 2 2 DLL_LOCK_12 12 12 DLL_LOCK_13 13 13 DLL_LOCK_14 14 14 DLL_LOCK_15 15 15 MODE_12 16 17 FREQDIV_12 18 19 MODE_13 20 21 FREQDIV_13 22 23 MODE_14 24 25 FREQDIV_14 26 27 MODE_15 28 29 FREQDIV_15 30 31 ixPB0_GLB_OVRD_REG0 2 0x1200030 2 0 4294967295 TXPDTERM_VAL_OVRD_VAL 0 15 TXPUTERM_VAL_OVRD_VAL 16 31 ixPB0_GLB_OVRD_REG1 2 0x1200034 6 0 4294967295 TXPDTERM_VAL_OVRD_EN 0 0 TXPUTERM_VAL_OVRD_EN 1 1 TST_LOSPDTST_RST_OVRD_EN 2 2 TST_LOSPDTST_RST_OVRD_VAL 3 3 RXTERM_VAL_OVRD_EN 15 15 RXTERM_VAL_OVRD_VAL 16 31 ixPB0_GLB_OVRD_REG2 2 0x1200038 2 0 4294967295 BG_PWRON_OVRD_EN 0 0 BG_PWRON_OVRD_VAL 1 1 ixPB0_HW_DEBUG 2 0x1202004 32 0 4294967295 PB0_HW_00_DEBUG 0 0 PB0_HW_01_DEBUG 1 1 PB0_HW_02_DEBUG 2 2 PB0_HW_03_DEBUG 3 3 PB0_HW_04_DEBUG 4 4 PB0_HW_05_DEBUG 5 5 PB0_HW_06_DEBUG 6 6 PB0_HW_07_DEBUG 7 7 PB0_HW_08_DEBUG 8 8 PB0_HW_09_DEBUG 9 9 PB0_HW_10_DEBUG 10 10 PB0_HW_11_DEBUG 11 11 PB0_HW_12_DEBUG 12 12 PB0_HW_13_DEBUG 13 13 PB0_HW_14_DEBUG 14 14 PB0_HW_15_DEBUG 15 15 PB0_HW_16_DEBUG 16 16 PB0_HW_17_DEBUG 17 17 PB0_HW_18_DEBUG 18 18 PB0_HW_19_DEBUG 19 19 PB0_HW_20_DEBUG 20 20 PB0_HW_21_DEBUG 21 21 PB0_HW_22_DEBUG 22 22 PB0_HW_23_DEBUG 23 23 PB0_HW_24_DEBUG 24 24 PB0_HW_25_DEBUG 25 25 PB0_HW_26_DEBUG 26 26 PB0_HW_27_DEBUG 27 27 PB0_HW_28_DEBUG 28 28 PB0_HW_29_DEBUG 29 29 PB0_HW_30_DEBUG 30 30 PB0_HW_31_DEBUG 31 31 ixPB0_STRAP_GLB_REG0 2 0x1202020 12 0 4294967295 STRAP_QUICK_SIM_START 1 1 STRAP_DFT_RXBSCAN_EN_VAL 2 2 STRAP_DFT_CALIB_BYPASS 3 3 STRAP_CFG_IDLEDET_TH 5 6 STRAP_RX_CFG_LEQ_DCATTN_BYP_VAL 7 11 STRAP_RX_CFG_OVR_PWRSF 12 12 STRAP_RX_TRK_MODE_0_ 13 13 STRAP_PWRGOOD_OVRD 14 14 STRAP_DBG_RXDLL_VREG_REF_SEL 15 15 STRAP_PLL_CFG_LC_VCO_TUNE 16 19 STRAP_DBG_RXRDATA_GATING_DISABLE 20 20 STRAP_DBG_RXPI_OFFSET_BYP_VAL 21 24 ixPB0_STRAP_TX_REG0 2 0x1202024 10 0 4294967295 STRAP_TX_CFG_DRV0_EN 1 4 STRAP_TX_CFG_DRV0_TAP_SEL 5 8 STRAP_TX_CFG_DRV1_EN 9 13 STRAP_TX_CFG_DRV1_TAP_SEL 14 18 STRAP_TX_CFG_DRV2_EN 19 22 STRAP_TX_CFG_DRV2_TAP_SEL 23 26 STRAP_TX_CFG_DRVX_EN 27 27 STRAP_TX_CFG_DRVX_TAP_SEL 28 28 STRAP_RX_TRK_MODE_1_ 29 29 STRAP_TX_CFG_SWING_BOOST_EN 30 30 ixPB0_STRAP_RX_REG0 2 0x1202028 12 0 4294967295 STRAP_RX_CFG_TH_LOOP_GAIN 1 4 STRAP_RX_CFG_DLL_FLOCK_DISABLE 5 5 STRAP_DBG_RXPI_OFFSET_BYP_EN 6 6 STRAP_RX_CFG_LEQ_DCATTN_BYP_DIS 7 7 STRAP_BG_CFG_LC_REG_VREF0_SEL 8 9 STRAP_BG_CFG_LC_REG_VREF1_SEL 10 11 STRAP_RX_CFG_CDR_TIME 12 15 STRAP_RX_CFG_FOM_TIME 16 19 STRAP_RX_CFG_LEQ_TIME 20 23 STRAP_RX_CFG_OC_TIME 24 27 STRAP_TX_CFG_RPTR_RST_VAL 28 30 STRAP_RX_CFG_TERM_MODE 31 31 ixPB0_STRAP_RX_REG1 2 0x120202c 10 0 4294967295 STRAP_RX_CFG_CDR_PI_STPSZ 1 1 STRAP_TX_DEEMPH_PRSHT_STNG 2 4 STRAP_BG_CFG_RO_REG_VREF_SEL 5 6 STRAP_RX_CFG_LEQ_POLE_BYP_DIS 7 7 STRAP_RX_CFG_LEQ_POLE_BYP_VAL 8 10 STRAP_RX_CFG_CDR_PH_GAIN 11 14 STRAP_RX_CFG_ADAPT_MODE 15 24 STRAP_RX_CFG_DFE_TIME 25 28 STRAP_RX_CFG_LEQ_LOOP_GAIN 29 30 STRAP_RX_CFG_LEQ_SHUNT_DIS 31 31 ixPB0_STRAP_PLL_REG0 2 0x1202030 6 0 4294967295 STRAP_PLL_CFG_LC_BW_CNTRL 1 3 STRAP_PLL_CFG_LC_LF_CNTRL 4 12 STRAP_TX_RXDET_X1_SSF 13 13 STRAP_PLL_CFG_RO_VTOI_BIAS_CNTRL_DIS 15 15 STRAP_PLL_CFG_RO_BW_CNTRL 16 23 STRAP_PLL_STRAP_SEL 24 24 ixPB0_STRAP_PIN_REG0 2 0x1202034 2 0 4294967295 STRAP_TX_DEEMPH_EN 1 1 STRAP_TX_FULL_SWING 2 2 ixPB0_DFT_JIT_INJ_REG0 2 0x1203000 8 0 4294967295 DFT_NUM_STEPS 0 5 DFT_DISABLE_ERR 7 7 DFT_CLK_PER_STEP 8 11 DFT_MODE_CDR_EN 20 20 DFT_EN_RECOVERY 21 21 DFT_INCR_SWP_EN 22 22 DFT_DECR_SWP_EN 23 23 DFT_RECOVERY_TIME 24 31 ixPB0_DFT_JIT_INJ_REG1 2 0x1203004 5 0 4294967295 DFT_BYPASS_VALUE 0 7 DFT_BYPASS_EN 8 8 DFT_BLOCK_EN 16 16 DFT_NUM_OF_TESTS 17 19 DFT_CHECK_TIME 20 23 ixPB0_DFT_JIT_INJ_REG2 2 0x1203008 1 0 4294967295 DFT_LANE_EN 0 15 ixPB0_DFT_DEBUG_CTRL_REG0 2 0x120300c 2 0 4294967295 DFT_PHY_DEBUG_EN 0 0 DFT_PHY_DEBUG_MODE 1 5 ixPB0_DFT_JIT_INJ_STAT_REG0 2 0x1203010 3 0 4294967295 DFT_STAT_DECR 0 7 DFT_STAT_INCR 8 15 DFT_STAT_FINISHED 16 16 ixPB0_PLL_RO_GLB_CTRL_REG0 2 0x1204000 23 0 4294967295 PLL_TST_LOSPDTST_SRC 0 0 PLL_RO_HSCLK_LEFT_EN_LUT_ENTRY_LS0 1 1 PLL_RO_HSCLK_LEFT_EN_LUT_ENTRY_LS1 2 2 PLL_RO_HSCLK_LEFT_EN_LUT_ENTRY_LS2 3 3 PLL_RO_HSCLK_RIGHT_EN_LUT_ENTRY_LS0 4 4 PLL_RO_HSCLK_RIGHT_EN_LUT_ENTRY_LS1 5 5 PLL_RO_HSCLK_RIGHT_EN_LUT_ENTRY_LS2 6 6 PLL_RO_PWRON_LUT_ENTRY_LS2 7 7 PLL_LC_PWRON_LUT_ENTRY_LS2 8 8 PLL_LC_HSCLK_LEFT_EN_LUT_ENTRY_LS0 9 9 PLL_LC_HSCLK_LEFT_EN_LUT_ENTRY_LS1 10 10 PLL_LC_HSCLK_LEFT_EN_LUT_ENTRY_LS2 11 11 PLL_LC_HSCLK_RIGHT_EN_LUT_ENTRY_LS0 12 12 PLL_LC_HSCLK_RIGHT_EN_LUT_ENTRY_LS1 13 13 PLL_LC_HSCLK_RIGHT_EN_LUT_ENTRY_LS2 14 14 PLL_RO_HSCLK_LEFT_LEFT_EN_GATING_EN 16 16 PLL_RO_HSCLK_LEFT_RIGHT_EN_GATING_EN 17 17 PLL_RO_HSCLK_RIGHT_LEFT_EN_GATING_EN 18 18 PLL_RO_HSCLK_RIGHT_RIGHT_EN_GATING_EN 19 19 PLL_LC_HSCLK_LEFT_LEFT_EN_GATING_EN 20 20 PLL_LC_HSCLK_LEFT_RIGHT_EN_GATING_EN 21 21 PLL_LC_HSCLK_RIGHT_LEFT_EN_GATING_EN 22 22 PLL_LC_HSCLK_RIGHT_RIGHT_EN_GATING_EN 23 23 ixPB0_PLL_RO_GLB_OVRD_REG0 2 0x1204010 0 0 4294967295 ixPB0_PLL_RO0_CTRL_REG0 2 0x1204440 5 0 4294967295 PLL_DBG_RO_ANALOG_SEL_0 0 1 PLL_DBG_RO_EXT_RESET_EN_0 2 2 PLL_DBG_RO_VCTL_ADC_EN_0 3 3 PLL_DBG_RO_LF_CNTRL_0 4 10 PLL_TST_RO_USAMPLE_EN_0 11 11 ixPB0_PLL_RO0_OVRD_REG0 2 0x1204450 10 0 4294967295 PLL_CFG_RO_BW_CNTRL_OVRD_VAL_0 0 7 PLL_CFG_RO_BW_CNTRL_OVRD_EN_0 8 8 PLL_CFG_RO_CORECLK_DIV_OVRD_VAL_0 9 11 PLL_CFG_RO_CORECLK_DIV_OVRD_EN_0 12 12 PLL_CFG_RO_CORECLK_EN_OVRD_VAL_0 13 13 PLL_CFG_RO_CORECLK_EN_OVRD_EN_0 14 14 PLL_CFG_RO_FBDIV_OVRD_VAL_0 15 27 PLL_CFG_RO_FBDIV_OVRD_EN_0 28 28 PLL_CFG_RO_VTOI_BIAS_CNTRL_OVRD_VAL_0 30 30 PLL_CFG_RO_VTOI_BIAS_CNTRL_OVRD_EN_0 31 31 ixPB0_PLL_RO0_OVRD_REG1 2 0x1204454 12 0 4294967295 PLL_CFG_RO_REFDIV_OVRD_VAL_0 0 4 PLL_CFG_RO_REFDIV_OVRD_EN_0 5 5 PLL_CFG_RO_VCO_MODE_OVRD_VAL_0 6 7 PLL_CFG_RO_VCO_MODE_OVRD_EN_0 8 8 PLL_RO_HSCLK_LEFT_EN_OVRD_VAL_0 9 9 PLL_RO_HSCLK_LEFT_EN_OVRD_EN_0 10 10 PLL_RO_HSCLK_RIGHT_EN_OVRD_VAL_0 11 11 PLL_RO_HSCLK_RIGHT_EN_OVRD_EN_0 12 12 PLL_RO_PWRON_OVRD_VAL_0 13 13 PLL_RO_PWRON_OVRD_EN_0 14 14 PLL_CFG_RO_REFCLK_SRC_OVRD_VAL_0 19 21 PLL_CFG_RO_REFCLK_SRC_OVRD_EN_0 22 22 ixPB0_PLL_RO0_SCI_STAT_OVRD_REG0 2 0x1204460 4 0 4294967295 PLL_RO0_IGNR_PLLPWR_SCI_UPDT 0 0 PLL_RO0_IGNR_FREQMODE_SCI_UPDT 1 1 PLL_RO0_PLLPWR 4 6 PLL_RO0_FREQMODE 8 9 ixPB0_PLL_RO1_SCI_STAT_OVRD_REG0 2 0x1204464 4 0 4294967295 PLL_RO1_IGNR_PLLPWR_SCI_UPDT 0 0 PLL_RO1_IGNR_FREQMODE_SCI_UPDT 1 1 PLL_RO1_PLLPWR 4 6 PLL_RO1_FREQMODE 8 9 ixPB0_PLL_RO2_SCI_STAT_OVRD_REG0 2 0x1204468 4 0 4294967295 PLL_RO2_IGNR_PLLPWR_SCI_UPDT 0 0 PLL_RO2_IGNR_FREQMODE_SCI_UPDT 1 1 PLL_RO2_PLLPWR 4 6 PLL_RO2_FREQMODE 8 9 ixPB0_PLL_RO3_SCI_STAT_OVRD_REG0 2 0x120446c 4 0 4294967295 PLL_RO3_IGNR_PLLPWR_SCI_UPDT 0 0 PLL_RO3_IGNR_FREQMODE_SCI_UPDT 1 1 PLL_RO3_PLLPWR 4 6 PLL_RO3_FREQMODE 8 9 ixPB0_PLL_LC0_CTRL_REG0 2 0x1204480 4 0 4294967295 PLL_DBG_LC_ANALOG_SEL_0 0 1 PLL_DBG_LC_EXT_RESET_EN_0 2 2 PLL_DBG_LC_VCTL_ADC_EN_0 3 3 PLL_TST_LC_USAMPLE_EN_0 4 4 ixPB0_PLL_LC0_OVRD_REG0 2 0x1204490 12 0 4294967295 PLL_CFG_LC_BW_CNTRL_OVRD_VAL_0 0 2 PLL_CFG_LC_BW_CNTRL_OVRD_EN_0 3 3 PLL_CFG_LC_CORECLK_DIV_OVRD_VAL_0 4 6 PLL_CFG_LC_CORECLK_DIV_OVRD_EN_0 7 7 PLL_CFG_LC_CORECLK_EN_OVRD_VAL_0 8 8 PLL_CFG_LC_CORECLK_EN_OVRD_EN_0 9 9 PLL_CFG_LC_FBDIV_OVRD_VAL_0 10 17 PLL_CFG_LC_FBDIV_OVRD_EN_0 18 18 PLL_CFG_LC_LF_CNTRL_OVRD_VAL_0 19 27 PLL_CFG_LC_LF_CNTRL_OVRD_EN_0 28 28 PLL_CFG_LC_REFDIV_OVRD_VAL_0 29 30 PLL_CFG_LC_REFDIV_OVRD_EN_0 31 31 ixPB0_PLL_LC0_OVRD_REG1 2 0x1204494 10 0 4294967295 PLL_CFG_LC_REFCLK_SRC_OVRD_VAL_0 0 2 PLL_CFG_LC_REFCLK_SRC_OVRD_EN_0 3 3 PLL_LC_HSCLK_LEFT_EN_OVRD_VAL_0 4 4 PLL_LC_HSCLK_LEFT_EN_OVRD_EN_0 5 5 PLL_LC_HSCLK_RIGHT_EN_OVRD_VAL_0 6 6 PLL_LC_HSCLK_RIGHT_EN_OVRD_EN_0 7 7 PLL_LC_PWRON_OVRD_VAL_0 8 8 PLL_LC_PWRON_OVRD_EN_0 9 9 PLL_CFG_LC_VCO_TUNE_OVRD_VAL_0 14 17 PLL_CFG_LC_VCO_TUNE_OVRD_EN_0 18 18 ixPB0_PLL_LC0_SCI_STAT_OVRD_REG0 2 0x1204500 4 0 4294967295 PLL_LC0_IGNR_PLLPWR_SCI_UPDT 0 0 PLL_LC0_IGNR_FREQMODE_SCI_UPDT 1 1 PLL_LC0_PLLPWR 4 6 PLL_LC0_FREQMODE 8 9 ixPB0_PLL_LC1_SCI_STAT_OVRD_REG0 2 0x1204504 4 0 4294967295 PLL_LC1_IGNR_PLLPWR_SCI_UPDT 0 0 PLL_LC1_IGNR_FREQMODE_SCI_UPDT 1 1 PLL_LC1_PLLPWR 4 6 PLL_LC1_FREQMODE 8 9 ixPB0_PLL_LC2_SCI_STAT_OVRD_REG0 2 0x1204508 4 0 4294967295 PLL_LC2_IGNR_PLLPWR_SCI_UPDT 0 0 PLL_LC2_IGNR_FREQMODE_SCI_UPDT 1 1 PLL_LC2_PLLPWR 4 6 PLL_LC2_FREQMODE 8 9 ixPB0_PLL_LC3_SCI_STAT_OVRD_REG0 2 0x120450c 4 0 4294967295 PLL_LC3_IGNR_PLLPWR_SCI_UPDT 0 0 PLL_LC3_IGNR_FREQMODE_SCI_UPDT 1 1 PLL_LC3_PLLPWR 4 6 PLL_LC3_FREQMODE 8 9 ixPB0_RX_GLB_CTRL_REG0 2 0x1206000 4 0 4294967295 RX_CFG_ADAPT_MODE_GEN1 0 9 RX_CFG_ADAPT_MODE_GEN2 10 19 RX_CFG_ADAPT_MODE_GEN3 20 29 RX_CFG_ADAPT_RST_MODE 30 31 ixPB0_RX_GLB_CTRL_REG1 2 0x1206004 13 0 4294967295 RX_CFG_CDR_FR_GAIN_GEN1 0 3 RX_CFG_CDR_FR_GAIN_GEN2 4 7 RX_CFG_CDR_FR_GAIN_GEN3 8 11 RX_CFG_CDR_PH_GAIN_GEN1 12 15 RX_CFG_CDR_PH_GAIN_GEN2 16 19 RX_CFG_CDR_PH_GAIN_GEN3 20 23 RX_CFG_CDR_PI_STPSZ_GEN1 24 24 RX_CFG_CDR_PI_STPSZ_GEN2 25 25 RX_CFG_CDR_PI_STPSZ_GEN3 26 26 RX_CFG_LEQ_DCATTN_BYP_EN_GEN1 27 27 RX_CFG_LEQ_DCATTN_BYP_EN_GEN2 28 28 RX_CFG_LEQ_DCATTN_BYP_EN_GEN3 29 29 RX_ADAPT_HLD_ASRT_TO_DCLK_EN 30 31 ixPB0_RX_GLB_CTRL_REG2 2 0x1206008 7 0 4294967295 RX_CFG_CDR_TIME_GEN1 12 15 RX_CFG_CDR_TIME_GEN2 16 19 RX_CFG_CDR_TIME_GEN3 20 23 RX_CFG_LEQ_LOOP_GAIN_GEN1 24 25 RX_CFG_LEQ_LOOP_GAIN_GEN2 26 27 RX_CFG_LEQ_LOOP_GAIN_GEN3 28 29 RX_DCLK_EN_ASRT_TO_ADAPT_HLD 30 31 ixPB0_RX_GLB_CTRL_REG3 2 0x120600c 6 0 4294967295 RX_CFG_CDR_FR_EN_GEN1 0 0 RX_CFG_CDR_FR_EN_GEN2 1 1 RX_CFG_CDR_FR_EN_GEN3 2 2 RX_CFG_DFE_TIME_GEN1 20 23 RX_CFG_DFE_TIME_GEN2 24 27 RX_CFG_DFE_TIME_GEN3 28 31 ixPB0_RX_GLB_CTRL_REG4 2 0x1206010 9 0 4294967295 RX_CFG_FOM_BER_GEN1 0 2 RX_CFG_FOM_BER_GEN2 3 5 RX_CFG_FOM_BER_GEN3 6 8 RX_CFG_LEQ_POLE_BYP_VAL_GEN1 9 11 RX_CFG_LEQ_POLE_BYP_VAL_GEN2 12 14 RX_CFG_LEQ_POLE_BYP_VAL_GEN3 15 17 RX_CFG_FOM_TIME_GEN1 20 23 RX_CFG_FOM_TIME_GEN2 24 27 RX_CFG_FOM_TIME_GEN3 28 31 ixPB0_RX_GLB_CTRL_REG5 2 0x1206014 14 0 4294967295 RX_CFG_LEQ_DCATTN_BYP_VAL_GEN1 0 4 RX_CFG_LEQ_DCATTN_BYP_VAL_GEN2 5 9 RX_CFG_LEQ_DCATTN_BYP_VAL_GEN3 10 14 RX_CFG_LEQ_POLE_BYP_EN_GEN1 15 15 RX_CFG_LEQ_POLE_BYP_EN_GEN2 16 16 RX_CFG_LEQ_POLE_BYP_EN_GEN3 17 17 RX_CFG_LEQ_SHUNT_EN_GEN1 18 18 RX_CFG_LEQ_SHUNT_EN_GEN2 19 19 RX_CFG_LEQ_SHUNT_EN_GEN3 20 20 RX_CFG_TERM_MODE_GEN1 27 27 RX_CFG_TERM_MODE_GEN2 28 28 RX_CFG_TERM_MODE_GEN3 29 29 RX_FORCE_DLL_RST_RXPWR_LS2OFF_TO_LS0 30 30 RX_ADAPT_AUX_PWRON_MODE 31 31 ixPB0_RX_GLB_CTRL_REG6 2 0x1206018 10 0 4294967295 RX_CFG_LEQ_TIME_GEN1 0 3 RX_CFG_LEQ_TIME_GEN2 4 7 RX_CFG_LEQ_TIME_GEN3 8 11 RX_CFG_OC_TIME_GEN1 12 15 RX_CFG_OC_TIME_GEN2 16 19 RX_CFG_OC_TIME_GEN3 20 23 RX_FRONTEND_PWRON_LUT_ENTRY_LS0_CDR_EN_0 24 24 RX_FRONTEND_PWRON_LUT_ENTRY_LS2 26 26 RX_AUX_PWRON_LUT_ENTRY_LS2 27 27 RX_ADAPT_HLD_L0S_EARLY_EXIT_DIS 28 28 ixPB0_RX_GLB_CTRL_REG7 2 0x120601c 12 0 4294967295 RX_CFG_TH_LOOP_GAIN_GEN1 0 3 RX_CFG_TH_LOOP_GAIN_GEN2 4 7 RX_CFG_TH_LOOP_GAIN_GEN3 8 11 RX_DCLK_EN_LUT_ENTRY_LS0_CDR_EN_0 12 12 RX_DCLK_EN_LUT_ENTRY_LS2 13 13 RX_DLL_PWRON_LUT_ENTRY_LS2 17 17 RX_CFG_DLL_CPI_SEL_GEN1 18 20 RX_CFG_DLL_CPI_SEL_GEN2 21 23 RX_CFG_DLL_CPI_SEL_GEN3 24 26 RX_CFG_DLL_FLOCK_DISABLE_GEN1 27 27 RX_CFG_DLL_FLOCK_DISABLE_GEN2 28 28 RX_CFG_DLL_FLOCK_DISABLE_GEN3 29 29 ixPB0_RX_GLB_CTRL_REG8 2 0x1206020 2 0 4294967295 RX_DLL_LOCK_TIME 0 1 RX_DLL_SPEEDCHANGE_RESET_TIME 2 3 ixPB0_RX_GLB_SCI_STAT_OVRD_REG0 2 0x1206028 24 0 4294967295 IGNR_RXPWR_SCI_UPDT_L0T3 0 0 IGNR_RXPWR_SCI_UPDT_L4T7 1 1 IGNR_RXPWR_SCI_UPDT_L8T11 2 2 IGNR_RXPWR_SCI_UPDT_L12T15 3 3 IGNR_ELECIDLEDETEN_SCI_UPDT_L0T3 4 4 IGNR_ELECIDLEDETEN_SCI_UPDT_L4T7 5 5 IGNR_ELECIDLEDETEN_SCI_UPDT_L8T11 6 6 IGNR_ELECIDLEDETEN_SCI_UPDT_L12T15 7 7 IGNR_RXPRESETHINT_SCI_UPDT_L0T3 8 8 IGNR_RXPRESETHINT_SCI_UPDT_L4T7 9 9 IGNR_RXPRESETHINT_SCI_UPDT_L8T11 10 10 IGNR_RXPRESETHINT_SCI_UPDT_L12T15 11 11 IGNR_ENABLEFOM_SCI_UPDT_L0T3 12 12 IGNR_ENABLEFOM_SCI_UPDT_L4T7 13 13 IGNR_ENABLEFOM_SCI_UPDT_L8T11 14 14 IGNR_ENABLEFOM_SCI_UPDT_L12T15 15 15 IGNR_REQUESTFOM_SCI_UPDT_L0T3 16 16 IGNR_REQUESTFOM_SCI_UPDT_L4T7 17 17 IGNR_REQUESTFOM_SCI_UPDT_L8T11 18 18 IGNR_REQUESTFOM_SCI_UPDT_L12T15 19 19 IGNR_RESPONSEMODE_SCI_UPDT_L0T3 20 20 IGNR_RESPONSEMODE_SCI_UPDT_L4T7 21 21 IGNR_RESPONSEMODE_SCI_UPDT_L8T11 22 22 IGNR_RESPONSEMODE_SCI_UPDT_L12T15 23 23 ixPB0_RX_GLB_OVRD_REG0 2 0x1206030 26 0 4294967295 RX_ADAPT_HLD_OVRD_VAL 0 0 RX_ADAPT_HLD_OVRD_EN 1 1 RX_ADAPT_RST_OVRD_VAL 2 2 RX_ADAPT_RST_OVRD_EN 3 3 RX_CFG_DCLK_DIV_OVRD_VAL 6 7 RX_CFG_DCLK_DIV_OVRD_EN 8 8 RX_CFG_DLL_FREQ_MODE_OVRD_VAL 9 9 RX_CFG_DLL_FREQ_MODE_OVRD_EN 10 10 RX_CFG_PLLCLK_SEL_OVRD_VAL 11 11 RX_CFG_PLLCLK_SEL_OVRD_EN 12 12 RX_CFG_RCLK_DIV_OVRD_VAL 13 13 RX_CFG_RCLK_DIV_OVRD_EN 14 14 RX_DCLK_EN_OVRD_VAL 15 15 RX_DCLK_EN_OVRD_EN 16 16 RX_DLL_PWRON_OVRD_VAL 17 17 RX_DLL_PWRON_OVRD_EN 18 18 RX_FRONTEND_PWRON_OVRD_VAL 19 19 RX_FRONTEND_PWRON_OVRD_EN 20 20 RX_IDLEDET_PWRON_OVRD_VAL 21 21 RX_IDLEDET_PWRON_OVRD_EN 22 22 RX_TERM_EN_OVRD_VAL 23 23 RX_TERM_EN_OVRD_EN 24 24 RX_AUX_PWRON_OVRD_VAL 28 28 RX_AUX_PWRON_OVRD_EN 29 29 RX_ADAPT_FOM_OVRD_VAL 30 30 RX_ADAPT_FOM_OVRD_EN 31 31 ixPB0_RX_GLB_OVRD_REG1 2 0x1206034 2 0 4294967295 RX_ADAPT_TRK_OVRD_VAL 0 0 RX_ADAPT_TRK_OVRD_EN 1 1 ixPB0_RX_LANE0_CTRL_REG0 2 0x1206440 4 0 4294967295 RX_BACKUP_0 0 7 RX_DBG_ANALOG_SEL_0 10 11 RX_TST_BSCAN_EN_0 12 12 RX_CFG_OVR_PWRSF_0 13 13 ixPB0_RX_LANE0_SCI_STAT_OVRD_REG0 2 0x1206448 6 0 4294967295 RXPWR_0 0 2 ELECIDLEDETEN_0 3 3 RXPRESETHINT_0 4 6 ENABLEFOM_0 7 7 REQUESTFOM_0 8 8 RESPONSEMODE_0 9 9 ixPB0_RX_LANE1_CTRL_REG0 2 0x1206480 4 0 4294967295 RX_BACKUP_1 0 7 RX_DBG_ANALOG_SEL_1 10 11 RX_TST_BSCAN_EN_1 12 12 RX_CFG_OVR_PWRSF_1 13 13 ixPB0_RX_LANE1_SCI_STAT_OVRD_REG0 2 0x1206488 6 0 4294967295 RXPWR_1 0 2 ELECIDLEDETEN_1 3 3 RXPRESETHINT_1 4 6 ENABLEFOM_1 7 7 REQUESTFOM_1 8 8 RESPONSEMODE_1 9 9 ixPB0_RX_LANE2_CTRL_REG0 2 0x1206500 4 0 4294967295 RX_BACKUP_2 0 7 RX_DBG_ANALOG_SEL_2 10 11 RX_TST_BSCAN_EN_2 12 12 RX_CFG_OVR_PWRSF_2 13 13 ixPB0_RX_LANE2_SCI_STAT_OVRD_REG0 2 0x1206508 6 0 4294967295 RXPWR_2 0 2 ELECIDLEDETEN_2 3 3 RXPRESETHINT_2 4 6 ENABLEFOM_2 7 7 REQUESTFOM_2 8 8 RESPONSEMODE_2 9 9 ixPB0_RX_LANE3_CTRL_REG0 2 0x1206600 4 0 4294967295 RX_BACKUP_3 0 7 RX_DBG_ANALOG_SEL_3 10 11 RX_TST_BSCAN_EN_3 12 12 RX_CFG_OVR_PWRSF_3 13 13 ixPB0_RX_LANE3_SCI_STAT_OVRD_REG0 2 0x1206608 6 0 4294967295 RXPWR_3 0 2 ELECIDLEDETEN_3 3 3 RXPRESETHINT_3 4 6 ENABLEFOM_3 7 7 REQUESTFOM_3 8 8 RESPONSEMODE_3 9 9 ixPB0_RX_LANE4_CTRL_REG0 2 0x1206800 4 0 4294967295 RX_BACKUP_4 0 7 RX_DBG_ANALOG_SEL_4 10 11 RX_TST_BSCAN_EN_4 12 12 RX_CFG_OVR_PWRSF_4 13 13 ixPB0_RX_LANE4_SCI_STAT_OVRD_REG0 2 0x1206848 6 0 4294967295 RXPWR_4 0 2 ELECIDLEDETEN_4 3 3 RXPRESETHINT_4 4 6 ENABLEFOM_4 7 7 REQUESTFOM_4 8 8 RESPONSEMODE_4 9 9 ixPB0_RX_LANE5_CTRL_REG0 2 0x1206880 4 0 4294967295 RX_BACKUP_5 0 7 RX_DBG_ANALOG_SEL_5 10 11 RX_TST_BSCAN_EN_5 12 12 RX_CFG_OVR_PWRSF_5 13 13 ixPB0_RX_LANE5_SCI_STAT_OVRD_REG0 2 0x1206888 6 0 4294967295 RXPWR_5 0 2 ELECIDLEDETEN_5 3 3 RXPRESETHINT_5 4 6 ENABLEFOM_5 7 7 REQUESTFOM_5 8 8 RESPONSEMODE_5 9 9 ixPB0_RX_LANE6_CTRL_REG0 2 0x1206900 4 0 4294967295 RX_BACKUP_6 0 7 RX_DBG_ANALOG_SEL_6 10 11 RX_TST_BSCAN_EN_6 12 12 RX_CFG_OVR_PWRSF_6 13 13 ixPB0_RX_LANE6_SCI_STAT_OVRD_REG0 2 0x1206908 6 0 4294967295 RXPWR_6 0 2 ELECIDLEDETEN_6 3 3 RXPRESETHINT_6 4 6 ENABLEFOM_6 7 7 REQUESTFOM_6 8 8 RESPONSEMODE_6 9 9 ixPB0_RX_LANE7_CTRL_REG0 2 0x1206a00 4 0 4294967295 RX_BACKUP_7 0 7 RX_DBG_ANALOG_SEL_7 10 11 RX_TST_BSCAN_EN_7 12 12 RX_CFG_OVR_PWRSF_7 13 13 ixPB0_RX_LANE7_SCI_STAT_OVRD_REG0 2 0x1206a08 6 0 4294967295 RXPWR_7 0 2 ELECIDLEDETEN_7 3 3 RXPRESETHINT_7 4 6 ENABLEFOM_7 7 7 REQUESTFOM_7 8 8 RESPONSEMODE_7 9 9 ixPB0_RX_LANE8_CTRL_REG0 2 0x1207440 4 0 4294967295 RX_BACKUP_8 0 7 RX_DBG_ANALOG_SEL_8 10 11 RX_TST_BSCAN_EN_8 12 12 RX_CFG_OVR_PWRSF_8 13 13 ixPB0_RX_LANE8_SCI_STAT_OVRD_REG0 2 0x1207448 6 0 4294967295 RXPWR_8 0 2 ELECIDLEDETEN_8 3 3 RXPRESETHINT_8 4 6 ENABLEFOM_8 7 7 REQUESTFOM_8 8 8 RESPONSEMODE_8 9 9 ixPB0_RX_LANE9_CTRL_REG0 2 0x1207480 4 0 4294967295 RX_BACKUP_9 0 7 RX_DBG_ANALOG_SEL_9 10 11 RX_TST_BSCAN_EN_9 12 12 RX_CFG_OVR_PWRSF_9 13 13 ixPB0_RX_LANE9_SCI_STAT_OVRD_REG0 2 0x1207488 6 0 4294967295 RXPWR_9 0 2 ELECIDLEDETEN_9 3 3 RXPRESETHINT_9 4 6 ENABLEFOM_9 7 7 REQUESTFOM_9 8 8 RESPONSEMODE_9 9 9 ixPB0_RX_LANE10_CTRL_REG0 2 0x1207500 4 0 4294967295 RX_BACKUP_10 0 7 RX_DBG_ANALOG_SEL_10 10 11 RX_TST_BSCAN_EN_10 12 12 RX_CFG_OVR_PWRSF_10 13 13 ixPB0_RX_LANE10_SCI_STAT_OVRD_REG0 2 0x1207508 6 0 4294967295 RXPWR_10 0 2 ELECIDLEDETEN_10 3 3 RXPRESETHINT_10 4 6 ENABLEFOM_10 7 7 REQUESTFOM_10 8 8 RESPONSEMODE_10 9 9 ixPB0_RX_LANE11_CTRL_REG0 2 0x1207600 4 0 4294967295 RX_BACKUP_11 0 7 RX_DBG_ANALOG_SEL_11 10 11 RX_TST_BSCAN_EN_11 12 12 RX_CFG_OVR_PWRSF_11 13 13 ixPB0_RX_LANE11_SCI_STAT_OVRD_REG0 2 0x1207608 6 0 4294967295 RXPWR_11 0 2 ELECIDLEDETEN_11 3 3 RXPRESETHINT_11 4 6 ENABLEFOM_11 7 7 REQUESTFOM_11 8 8 RESPONSEMODE_11 9 9 ixPB0_RX_LANE12_CTRL_REG0 2 0x1207840 4 0 4294967295 RX_BACKUP_12 0 7 RX_DBG_ANALOG_SEL_12 10 11 RX_TST_BSCAN_EN_12 12 12 RX_CFG_OVR_PWRSF_12 13 13 ixPB0_RX_LANE12_SCI_STAT_OVRD_REG0 2 0x1207848 6 0 4294967295 RXPWR_12 0 2 ELECIDLEDETEN_12 3 3 RXPRESETHINT_12 4 6 ENABLEFOM_12 7 7 REQUESTFOM_12 8 8 RESPONSEMODE_12 9 9 ixPB0_RX_LANE13_CTRL_REG0 2 0x1207880 4 0 4294967295 RX_BACKUP_13 0 7 RX_DBG_ANALOG_SEL_13 10 11 RX_TST_BSCAN_EN_13 12 12 RX_CFG_OVR_PWRSF_13 13 13 ixPB0_RX_LANE13_SCI_STAT_OVRD_REG0 2 0x1207888 6 0 4294967295 RXPWR_13 0 2 ELECIDLEDETEN_13 3 3 RXPRESETHINT_13 4 6 ENABLEFOM_13 7 7 REQUESTFOM_13 8 8 RESPONSEMODE_13 9 9 ixPB0_RX_LANE14_CTRL_REG0 2 0x1207900 4 0 4294967295 RX_BACKUP_14 0 7 RX_DBG_ANALOG_SEL_14 10 11 RX_TST_BSCAN_EN_14 12 12 RX_CFG_OVR_PWRSF_14 13 13 ixPB0_RX_LANE14_SCI_STAT_OVRD_REG0 2 0x1207908 6 0 4294967295 RXPWR_14 0 2 ELECIDLEDETEN_14 3 3 RXPRESETHINT_14 4 6 ENABLEFOM_14 7 7 REQUESTFOM_14 8 8 RESPONSEMODE_14 9 9 ixPB0_RX_LANE15_CTRL_REG0 2 0x1207a00 4 0 4294967295 RX_BACKUP_15 0 7 RX_DBG_ANALOG_SEL_15 10 11 RX_TST_BSCAN_EN_15 12 12 RX_CFG_OVR_PWRSF_15 13 13 ixPB0_RX_LANE15_SCI_STAT_OVRD_REG0 2 0x1207a08 6 0 4294967295 RXPWR_15 0 2 ELECIDLEDETEN_15 3 3 RXPRESETHINT_15 4 6 ENABLEFOM_15 7 7 REQUESTFOM_15 8 8 RESPONSEMODE_15 9 9 ixPB0_TX_GLB_CTRL_REG0 2 0x1208000 12 0 4294967295 TX_DRV_DATA_ASRT_DLY_VAL 0 2 TX_DRV_DATA_DSRT_DLY_VAL 3 5 TX_CFG_RPTR_RST_VAL_GEN1 8 10 TX_CFG_RPTR_RST_VAL_GEN2 11 13 TX_CFG_RPTR_RST_VAL_GEN3 14 16 TX_STAGGER_CTRL 17 18 TX_DATA_CLK_GATING 19 19 TX_PRESET_TABLE_BYPASS 20 20 TX_COEFF_ROUND_EN 21 21 TX_COEFF_ROUND_DIR_VER 22 22 TX_DCLK_EN_LSX_ALWAYS_ON 23 23 TX_FRONTEND_PWRON_IN_OFF 24 24 ixPB0_TX_GLB_LANE_SKEW_CTRL 2 0x1208004 31 0 4294967295 TX_CFG_GROUPX1_EN_0 0 0 TX_CFG_GROUPX1_EN_1 1 1 TX_CFG_GROUPX1_EN_2 2 2 TX_CFG_GROUPX1_EN_3 3 3 TX_CFG_GROUPX1_EN_4 4 4 TX_CFG_GROUPX1_EN_5 5 5 TX_CFG_GROUPX1_EN_6 6 6 TX_CFG_GROUPX1_EN_7 7 7 TX_CFG_GROUPX1_EN_8 8 8 TX_CFG_GROUPX1_EN_9 9 9 TX_CFG_GROUPX1_EN_10 10 10 TX_CFG_GROUPX1_EN_11 11 11 TX_CFG_GROUPX1_EN_12 12 12 TX_CFG_GROUPX1_EN_13 13 13 TX_CFG_GROUPX1_EN_14 14 14 TX_CFG_GROUPX1_EN_15 15 15 TX_CFG_GROUPX2_EN_L0T1 16 16 TX_CFG_GROUPX2_EN_L2T3 17 17 TX_CFG_GROUPX2_EN_L4T5 18 18 TX_CFG_GROUPX2_EN_L6T7 19 19 TX_CFG_GROUPX2_EN_L8T9 20 20 TX_CFG_GROUPX2_EN_L10T11 21 21 TX_CFG_GROUPX2_EN_L12T13 22 22 TX_CFG_GROUPX2_EN_L14T15 23 23 TX_CFG_GROUPX4_EN_L0T3 24 24 TX_CFG_GROUPX4_EN_L4T7 25 25 TX_CFG_GROUPX4_EN_L8T11 26 26 TX_CFG_GROUPX4_EN_L12T15 27 27 TX_CFG_GROUPX8_EN_L0T7 28 28 TX_CFG_GROUPX8_EN_L8T15 29 29 TX_CFG_GROUPX16_EN_L0T15 30 30 ixPB0_TX_GLB_SCI_STAT_OVRD_REG0 2 0x1208010 16 0 4294967295 IGNR_TXPWR_SCI_UPDT_L0T3 0 0 IGNR_TXPWR_SCI_UPDT_L4T7 1 1 IGNR_TXPWR_SCI_UPDT_L8T11 2 2 IGNR_TXPWR_SCI_UPDT_L12T15 3 3 IGNR_INCOHERENTCK_SCI_UPDT_L0T3 4 4 IGNR_INCOHERENTCK_SCI_UPDT_L4T7 5 5 IGNR_INCOHERENTCK_SCI_UPDT_L8T11 6 6 IGNR_INCOHERENTCK_SCI_UPDT_L12T15 7 7 IGNR_COEFFICIENTID_SCI_UPDT_L0T3 8 8 IGNR_COEFFICIENTID_SCI_UPDT_L4T7 9 9 IGNR_COEFFICIENTID_SCI_UPDT_L8T11 10 10 IGNR_COEFFICIENTID_SCI_UPDT_L12T15 11 11 IGNR_COEFFICIENT_SCI_UPDT_L0T3 12 12 IGNR_COEFFICIENT_SCI_UPDT_L4T7 13 13 IGNR_COEFFICIENT_SCI_UPDT_L8T11 14 14 IGNR_COEFFICIENT_SCI_UPDT_L12T15 15 15 ixPB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0 2 0x1208014 32 0 4294967295 ACCEPT_ENTRY_0 0 0 ACCEPT_ENTRY_1 1 1 ACCEPT_ENTRY_2 2 2 ACCEPT_ENTRY_3 3 3 ACCEPT_ENTRY_4 4 4 ACCEPT_ENTRY_5 5 5 ACCEPT_ENTRY_6 6 6 ACCEPT_ENTRY_7 7 7 ACCEPT_ENTRY_8 8 8 ACCEPT_ENTRY_9 9 9 ACCEPT_ENTRY_10 10 10 ACCEPT_ENTRY_11 11 11 ACCEPT_ENTRY_12 12 12 ACCEPT_ENTRY_13 13 13 ACCEPT_ENTRY_14 14 14 ACCEPT_ENTRY_15 15 15 ACCEPT_ENTRY_16 16 16 ACCEPT_ENTRY_17 17 17 ACCEPT_ENTRY_18 18 18 ACCEPT_ENTRY_19 19 19 ACCEPT_ENTRY_20 20 20 ACCEPT_ENTRY_21 21 21 ACCEPT_ENTRY_22 22 22 ACCEPT_ENTRY_23 23 23 ACCEPT_ENTRY_24 24 24 ACCEPT_ENTRY_25 25 25 ACCEPT_ENTRY_26 26 26 ACCEPT_ENTRY_27 27 27 ACCEPT_ENTRY_28 28 28 ACCEPT_ENTRY_29 29 29 ACCEPT_ENTRY_30 30 30 ACCEPT_ENTRY_31 31 31 ixPB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1 2 0x1208018 32 0 4294967295 ACCEPT_ENTRY_32 0 0 ACCEPT_ENTRY_33 1 1 ACCEPT_ENTRY_34 2 2 ACCEPT_ENTRY_35 3 3 ACCEPT_ENTRY_36 4 4 ACCEPT_ENTRY_37 5 5 ACCEPT_ENTRY_38 6 6 ACCEPT_ENTRY_39 7 7 ACCEPT_ENTRY_40 8 8 ACCEPT_ENTRY_41 9 9 ACCEPT_ENTRY_42 10 10 ACCEPT_ENTRY_43 11 11 ACCEPT_ENTRY_44 12 12 ACCEPT_ENTRY_45 13 13 ACCEPT_ENTRY_46 14 14 ACCEPT_ENTRY_47 15 15 ACCEPT_ENTRY_48 16 16 ACCEPT_ENTRY_49 17 17 ACCEPT_ENTRY_50 18 18 ACCEPT_ENTRY_51 19 19 ACCEPT_ENTRY_52 20 20 ACCEPT_ENTRY_53 21 21 ACCEPT_ENTRY_54 22 22 ACCEPT_ENTRY_55 23 23 ACCEPT_ENTRY_56 24 24 ACCEPT_ENTRY_57 25 25 ACCEPT_ENTRY_58 26 26 ACCEPT_ENTRY_59 27 27 ACCEPT_ENTRY_60 28 28 ACCEPT_ENTRY_61 29 29 ACCEPT_ENTRY_62 30 30 ACCEPT_ENTRY_63 31 31 ixPB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2 2 0x120801c 32 0 4294967295 ACCEPT_ENTRY_64 0 0 ACCEPT_ENTRY_65 1 1 ACCEPT_ENTRY_66 2 2 ACCEPT_ENTRY_67 3 3 ACCEPT_ENTRY_68 4 4 ACCEPT_ENTRY_69 5 5 ACCEPT_ENTRY_70 6 6 ACCEPT_ENTRY_71 7 7 ACCEPT_ENTRY_72 8 8 ACCEPT_ENTRY_73 9 9 ACCEPT_ENTRY_74 10 10 ACCEPT_ENTRY_75 11 11 ACCEPT_ENTRY_76 12 12 ACCEPT_ENTRY_77 13 13 ACCEPT_ENTRY_78 14 14 ACCEPT_ENTRY_79 15 15 ACCEPT_ENTRY_80 16 16 ACCEPT_ENTRY_81 17 17 ACCEPT_ENTRY_82 18 18 ACCEPT_ENTRY_83 19 19 ACCEPT_ENTRY_84 20 20 ACCEPT_ENTRY_85 21 21 ACCEPT_ENTRY_86 22 22 ACCEPT_ENTRY_87 23 23 ACCEPT_ENTRY_88 24 24 ACCEPT_ENTRY_89 25 25 ACCEPT_ENTRY_90 26 26 ACCEPT_ENTRY_91 27 27 ACCEPT_ENTRY_92 28 28 ACCEPT_ENTRY_93 29 29 ACCEPT_ENTRY_94 30 30 ACCEPT_ENTRY_95 31 31 ixPB0_TX_GLB_COEFF_ACCEPT_TABLE_REG3 2 0x1208020 14 0 4294967295 ACCEPT_ENTRY_96 0 0 ACCEPT_ENTRY_97 1 1 ACCEPT_ENTRY_98 2 2 ACCEPT_ENTRY_99 3 3 ACCEPT_ENTRY_100 4 4 ACCEPT_ENTRY_101 5 5 ACCEPT_ENTRY_102 6 6 ACCEPT_ENTRY_103 7 7 ACCEPT_ENTRY_104 8 8 ACCEPT_ENTRY_105 9 9 ACCEPT_ENTRY_106 10 10 ACCEPT_ENTRY_107 11 11 ACCEPT_ENTRY_108 12 12 ACCEPT_ENTRY_109 13 13 ixPB0_TX_GLB_OVRD_REG0 2 0x1208030 12 0 4294967295 TX_CFG_DCLK_DIV_OVRD_VAL 0 2 TX_CFG_DCLK_DIV_OVRD_EN 3 3 TX_CFG_DRV0_EN_GEN1_OVRD_VAL 4 7 TX_CFG_DRV0_EN_OVRD_EN 8 8 TX_CFG_DRV0_TAP_SEL_GEN1_OVRD_VAL 9 12 TX_CFG_DRV0_TAP_SEL_OVRD_EN 13 13 TX_CFG_DRV1_EN_GEN1_OVRD_VAL 14 18 TX_CFG_DRV1_EN_OVRD_EN 19 19 TX_CFG_DRV1_TAP_SEL_GEN1_OVRD_VAL 20 24 TX_CFG_DRV1_TAP_SEL_OVRD_EN 25 25 TX_CFG_DRV2_EN_GEN1_OVRD_VAL 26 29 TX_CFG_DRV2_EN_OVRD_EN 30 30 ixPB0_TX_GLB_OVRD_REG1 2 0x1208034 20 0 4294967295 TX_CFG_DRV2_TAP_SEL_GEN1_OVRD_VAL 0 3 TX_CFG_DRV2_TAP_SEL_OVRD_EN 4 4 TX_CFG_DRVX_EN_GEN1_OVRD_VAL 5 5 TX_CFG_DRVX_EN_OVRD_EN 6 6 TX_CFG_DRVX_TAP_SEL_GEN1_OVRD_VAL 7 7 TX_CFG_DRVX_TAP_SEL_OVRD_EN 8 8 TX_CFG_PLLCLK_SEL_OVRD_VAL 9 9 TX_CFG_PLLCLK_SEL_OVRD_EN 10 10 TX_CFG_TCLK_DIV_OVRD_VAL 11 11 TX_CFG_TCLK_DIV_OVRD_EN 12 12 TX_CMDET_EN_OVRD_VAL 13 13 TX_CMDET_EN_OVRD_EN 14 14 TX_DATA_IN_OVRD_VAL 15 24 TX_DATA_IN_OVRD_EN 25 25 TX_RPTR_RSTN_OVRD_VAL 26 26 TX_RPTR_RSTN_OVRD_EN 27 27 TX_RXDET_EN_OVRD_VAL 28 28 TX_RXDET_EN_OVRD_EN 29 29 TX_WPTR_RSTN_OVRD_VAL 30 30 TX_WPTR_RSTN_OVRD_EN 31 31 ixPB0_TX_GLB_OVRD_REG2 2 0x1208038 16 0 4294967295 TX_WRITE_EN_OVRD_VAL 0 0 TX_WRITE_EN_OVRD_EN 1 1 TX_CFG_GROUPX1_EN_OVRD_VAL 2 2 TX_CFG_GROUPX1_EN_OVRD_EN 3 3 TX_CFG_GROUPX2_EN_OVRD_VAL 4 4 TX_CFG_GROUPX2_EN_OVRD_EN 5 5 TX_CFG_GROUPX4_EN_OVRD_VAL 6 6 TX_CFG_GROUPX4_EN_OVRD_EN 7 7 TX_CFG_GROUPX8_EN_OVRD_VAL 8 8 TX_CFG_GROUPX8_EN_OVRD_EN 9 9 TX_CFG_GROUPX16_EN_OVRD_VAL 10 10 TX_CFG_GROUPX16_EN_OVRD_EN 11 11 TX_CFG_DRV0_EN_GEN2_OVRD_VAL 12 15 TX_CFG_DRV0_TAP_SEL_GEN2_OVRD_VAL 16 19 TX_CFG_DRV1_EN_GEN2_OVRD_VAL 20 24 TX_CFG_DRV1_TAP_SEL_GEN2_OVRD_VAL 25 29 ixPB0_TX_GLB_OVRD_REG3 2 0x120803c 9 0 4294967295 TX_CFG_DRV2_EN_GEN2_OVRD_VAL 0 3 TX_CFG_DRV2_TAP_SEL_GEN2_OVRD_VAL 4 7 TX_CFG_DRVX_EN_GEN2_OVRD_VAL 8 8 TX_CFG_DRVX_TAP_SEL_GEN2_OVRD_VAL 9 9 TX_CFG_DRV0_EN_GEN3_OVRD_VAL 10 13 TX_CFG_DRV0_TAP_SEL_GEN3_OVRD_VAL 14 17 TX_CFG_DRV1_EN_GEN3_OVRD_VAL 18 22 TX_CFG_DRV1_TAP_SEL_GEN3_OVRD_VAL 23 27 TX_CFG_DRV2_EN_GEN3_OVRD_VAL 28 31 ixPB0_TX_GLB_OVRD_REG4 2 0x1208040 3 0 4294967295 TX_CFG_DRV2_TAP_SEL_GEN3_OVRD_VAL 0 3 TX_CFG_DRVX_EN_GEN3_OVRD_VAL 4 4 TX_CFG_DRVX_TAP_SEL_GEN3_OVRD_VAL 5 5 ixPB0_TX_LANE0_CTRL_REG0 2 0x1208440 4 0 4294967295 TX_CFG_DISPCLK_MODE_0 0 0 TX_CFG_INV_DATA_0 1 1 TX_CFG_SWING_BOOST_EN_0 2 2 TX_DBG_PRBS_EN_0 3 3 ixPB0_TX_LANE0_OVRD_REG0 2 0x1208444 8 0 4294967295 TX_DCLK_EN_OVRD_VAL_0 0 0 TX_DCLK_EN_OVRD_EN_0 1 1 TX_DRV_DATA_EN_OVRD_VAL_0 2 2 TX_DRV_DATA_EN_OVRD_EN_0 3 3 TX_DRV_PWRON_OVRD_VAL_0 4 4 TX_DRV_PWRON_OVRD_EN_0 5 5 TX_FRONTEND_PWRON_OVRD_VAL_0 6 6 TX_FRONTEND_PWRON_OVRD_EN_0 7 7 ixPB0_TX_LANE0_SCI_STAT_OVRD_REG0 2 0x1208448 6 0 4294967295 TXPWR_0 0 2 INCOHERENTCK_0 3 3 TXMARG_0 4 6 DEEMPH_0 7 7 COEFFICIENTID_0 8 9 COEFFICIENT_0 10 15 ixPB0_TX_LANE1_CTRL_REG0 2 0x1208480 4 0 4294967295 TX_CFG_DISPCLK_MODE_1 0 0 TX_CFG_INV_DATA_1 1 1 TX_CFG_SWING_BOOST_EN_1 2 2 TX_DBG_PRBS_EN_1 3 3 ixPB0_TX_LANE1_OVRD_REG0 2 0x1208484 8 0 4294967295 TX_DCLK_EN_OVRD_VAL_1 0 0 TX_DCLK_EN_OVRD_EN_1 1 1 TX_DRV_DATA_EN_OVRD_VAL_1 2 2 TX_DRV_DATA_EN_OVRD_EN_1 3 3 TX_DRV_PWRON_OVRD_VAL_1 4 4 TX_DRV_PWRON_OVRD_EN_1 5 5 TX_FRONTEND_PWRON_OVRD_VAL_1 6 6 TX_FRONTEND_PWRON_OVRD_EN_1 7 7 ixPB0_TX_LANE1_SCI_STAT_OVRD_REG0 2 0x1208488 6 0 4294967295 TXPWR_1 0 2 INCOHERENTCK_1 3 3 TXMARG_1 4 6 DEEMPH_1 7 7 COEFFICIENTID_1 8 9 COEFFICIENT_1 10 15 ixPB0_TX_LANE2_CTRL_REG0 2 0x1208500 4 0 4294967295 TX_CFG_DISPCLK_MODE_2 0 0 TX_CFG_INV_DATA_2 1 1 TX_CFG_SWING_BOOST_EN_2 2 2 TX_DBG_PRBS_EN_2 3 3 ixPB0_TX_LANE2_OVRD_REG0 2 0x1208504 8 0 4294967295 TX_DCLK_EN_OVRD_VAL_2 0 0 TX_DCLK_EN_OVRD_EN_2 1 1 TX_DRV_DATA_EN_OVRD_VAL_2 2 2 TX_DRV_DATA_EN_OVRD_EN_2 3 3 TX_DRV_PWRON_OVRD_VAL_2 4 4 TX_DRV_PWRON_OVRD_EN_2 5 5 TX_FRONTEND_PWRON_OVRD_VAL_2 6 6 TX_FRONTEND_PWRON_OVRD_EN_2 7 7 ixPB0_TX_LANE2_SCI_STAT_OVRD_REG0 2 0x1208508 6 0 4294967295 TXPWR_2 0 2 INCOHERENTCK_2 3 3 TXMARG_2 4 6 DEEMPH_2 7 7 COEFFICIENTID_2 8 9 COEFFICIENT_2 10 15 ixPB0_TX_LANE3_CTRL_REG0 2 0x1208600 4 0 4294967295 TX_CFG_DISPCLK_MODE_3 0 0 TX_CFG_INV_DATA_3 1 1 TX_CFG_SWING_BOOST_EN_3 2 2 TX_DBG_PRBS_EN_3 3 3 ixPB0_TX_LANE3_OVRD_REG0 2 0x1208604 8 0 4294967295 TX_DCLK_EN_OVRD_VAL_3 0 0 TX_DCLK_EN_OVRD_EN_3 1 1 TX_DRV_DATA_EN_OVRD_VAL_3 2 2 TX_DRV_DATA_EN_OVRD_EN_3 3 3 TX_DRV_PWRON_OVRD_VAL_3 4 4 TX_DRV_PWRON_OVRD_EN_3 5 5 TX_FRONTEND_PWRON_OVRD_VAL_3 6 6 TX_FRONTEND_PWRON_OVRD_EN_3 7 7 ixPB0_TX_LANE3_SCI_STAT_OVRD_REG0 2 0x1208608 6 0 4294967295 TXPWR_3 0 2 INCOHERENTCK_3 3 3 TXMARG_3 4 6 DEEMPH_3 7 7 COEFFICIENTID_3 8 9 COEFFICIENT_3 10 15 ixPB0_TX_LANE4_CTRL_REG0 2 0x1208840 4 0 4294967295 TX_CFG_DISPCLK_MODE_4 0 0 TX_CFG_INV_DATA_4 1 1 TX_CFG_SWING_BOOST_EN_4 2 2 TX_DBG_PRBS_EN_4 3 3 ixPB0_TX_LANE4_OVRD_REG0 2 0x1208844 8 0 4294967295 TX_DCLK_EN_OVRD_VAL_4 0 0 TX_DCLK_EN_OVRD_EN_4 1 1 TX_DRV_DATA_EN_OVRD_VAL_4 2 2 TX_DRV_DATA_EN_OVRD_EN_4 3 3 TX_DRV_PWRON_OVRD_VAL_4 4 4 TX_DRV_PWRON_OVRD_EN_4 5 5 TX_FRONTEND_PWRON_OVRD_VAL_4 6 6 TX_FRONTEND_PWRON_OVRD_EN_4 7 7 ixPB0_TX_LANE4_SCI_STAT_OVRD_REG0 2 0x1208848 6 0 4294967295 TXPWR_4 0 2 INCOHERENTCK_4 3 3 TXMARG_4 4 6 DEEMPH_4 7 7 COEFFICIENTID_4 8 9 COEFFICIENT_4 10 15 ixPB0_TX_LANE5_CTRL_REG0 2 0x1208880 4 0 4294967295 TX_CFG_DISPCLK_MODE_5 0 0 TX_CFG_INV_DATA_5 1 1 TX_CFG_SWING_BOOST_EN_5 2 2 TX_DBG_PRBS_EN_5 3 3 ixPB0_TX_LANE5_OVRD_REG0 2 0x1208884 8 0 4294967295 TX_DCLK_EN_OVRD_VAL_5 0 0 TX_DCLK_EN_OVRD_EN_5 1 1 TX_DRV_DATA_EN_OVRD_VAL_5 2 2 TX_DRV_DATA_EN_OVRD_EN_5 3 3 TX_DRV_PWRON_OVRD_VAL_5 4 4 TX_DRV_PWRON_OVRD_EN_5 5 5 TX_FRONTEND_PWRON_OVRD_VAL_5 6 6 TX_FRONTEND_PWRON_OVRD_EN_5 7 7 ixPB0_TX_LANE5_SCI_STAT_OVRD_REG0 2 0x1208888 6 0 4294967295 TXPWR_5 0 2 INCOHERENTCK_5 3 3 TXMARG_5 4 6 DEEMPH_5 7 7 COEFFICIENTID_5 8 9 COEFFICIENT_5 10 15 ixPB0_TX_LANE6_CTRL_REG0 2 0x1208900 4 0 4294967295 TX_CFG_DISPCLK_MODE_6 0 0 TX_CFG_INV_DATA_6 1 1 TX_CFG_SWING_BOOST_EN_6 2 2 TX_DBG_PRBS_EN_6 3 3 ixPB0_TX_LANE6_OVRD_REG0 2 0x1208904 8 0 4294967295 TX_DCLK_EN_OVRD_VAL_6 0 0 TX_DCLK_EN_OVRD_EN_6 1 1 TX_DRV_DATA_EN_OVRD_VAL_6 2 2 TX_DRV_DATA_EN_OVRD_EN_6 3 3 TX_DRV_PWRON_OVRD_VAL_6 4 4 TX_DRV_PWRON_OVRD_EN_6 5 5 TX_FRONTEND_PWRON_OVRD_VAL_6 6 6 TX_FRONTEND_PWRON_OVRD_EN_6 7 7 ixPB0_TX_LANE6_SCI_STAT_OVRD_REG0 2 0x1208908 6 0 4294967295 TXPWR_6 0 2 INCOHERENTCK_6 3 3 TXMARG_6 4 6 DEEMPH_6 7 7 COEFFICIENTID_6 8 9 COEFFICIENT_6 10 15 ixPB0_TX_LANE7_CTRL_REG0 2 0x1208a00 4 0 4294967295 TX_CFG_DISPCLK_MODE_7 0 0 TX_CFG_INV_DATA_7 1 1 TX_CFG_SWING_BOOST_EN_7 2 2 TX_DBG_PRBS_EN_7 3 3 ixPB0_TX_LANE7_OVRD_REG0 2 0x1208a04 8 0 4294967295 TX_DCLK_EN_OVRD_VAL_7 0 0 TX_DCLK_EN_OVRD_EN_7 1 1 TX_DRV_DATA_EN_OVRD_VAL_7 2 2 TX_DRV_DATA_EN_OVRD_EN_7 3 3 TX_DRV_PWRON_OVRD_VAL_7 4 4 TX_DRV_PWRON_OVRD_EN_7 5 5 TX_FRONTEND_PWRON_OVRD_VAL_7 6 6 TX_FRONTEND_PWRON_OVRD_EN_7 7 7 ixPB0_TX_LANE7_SCI_STAT_OVRD_REG0 2 0x1208a08 6 0 4294967295 TXPWR_7 0 2 INCOHERENTCK_7 3 3 TXMARG_7 4 6 DEEMPH_7 7 7 COEFFICIENTID_7 8 9 COEFFICIENT_7 10 15 ixPB0_TX_LANE8_CTRL_REG0 2 0x1209440 4 0 4294967295 TX_CFG_DISPCLK_MODE_8 0 0 TX_CFG_INV_DATA_8 1 1 TX_CFG_SWING_BOOST_EN_8 2 2 TX_DBG_PRBS_EN_8 3 3 ixPB0_TX_LANE8_OVRD_REG0 2 0x1209444 8 0 4294967295 TX_DCLK_EN_OVRD_VAL_8 0 0 TX_DCLK_EN_OVRD_EN_8 1 1 TX_DRV_DATA_EN_OVRD_VAL_8 2 2 TX_DRV_DATA_EN_OVRD_EN_8 3 3 TX_DRV_PWRON_OVRD_VAL_8 4 4 TX_DRV_PWRON_OVRD_EN_8 5 5 TX_FRONTEND_PWRON_OVRD_VAL_8 6 6 TX_FRONTEND_PWRON_OVRD_EN_8 7 7 ixPB0_TX_LANE8_SCI_STAT_OVRD_REG0 2 0x1209448 6 0 4294967295 TXPWR_8 0 2 INCOHERENTCK_8 3 3 TXMARG_8 4 6 DEEMPH_8 7 7 COEFFICIENTID_8 8 9 COEFFICIENT_8 10 15 ixPB0_TX_LANE9_CTRL_REG0 2 0x1209480 4 0 4294967295 TX_CFG_DISPCLK_MODE_9 0 0 TX_CFG_INV_DATA_9 1 1 TX_CFG_SWING_BOOST_EN_9 2 2 TX_DBG_PRBS_EN_9 3 3 ixPB0_TX_LANE9_OVRD_REG0 2 0x1209484 8 0 4294967295 TX_DCLK_EN_OVRD_VAL_9 0 0 TX_DCLK_EN_OVRD_EN_9 1 1 TX_DRV_DATA_EN_OVRD_VAL_9 2 2 TX_DRV_DATA_EN_OVRD_EN_9 3 3 TX_DRV_PWRON_OVRD_VAL_9 4 4 TX_DRV_PWRON_OVRD_EN_9 5 5 TX_FRONTEND_PWRON_OVRD_VAL_9 6 6 TX_FRONTEND_PWRON_OVRD_EN_9 7 7 ixPB0_TX_LANE9_SCI_STAT_OVRD_REG0 2 0x1209488 6 0 4294967295 TXPWR_9 0 2 INCOHERENTCK_9 3 3 TXMARG_9 4 6 DEEMPH_9 7 7 COEFFICIENTID_9 8 9 COEFFICIENT_9 10 15 ixPB0_TX_LANE10_CTRL_REG0 2 0x1209500 4 0 4294967295 TX_CFG_DISPCLK_MODE_10 0 0 TX_CFG_INV_DATA_10 1 1 TX_CFG_SWING_BOOST_EN_10 2 2 TX_DBG_PRBS_EN_10 3 3 ixPB0_TX_LANE10_OVRD_REG0 2 0x1209504 8 0 4294967295 TX_DCLK_EN_OVRD_VAL_10 0 0 TX_DCLK_EN_OVRD_EN_10 1 1 TX_DRV_DATA_EN_OVRD_VAL_10 2 2 TX_DRV_DATA_EN_OVRD_EN_10 3 3 TX_DRV_PWRON_OVRD_VAL_10 4 4 TX_DRV_PWRON_OVRD_EN_10 5 5 TX_FRONTEND_PWRON_OVRD_VAL_10 6 6 TX_FRONTEND_PWRON_OVRD_EN_10 7 7 ixPB0_TX_LANE10_SCI_STAT_OVRD_REG0 2 0x1209508 6 0 4294967295 TXPWR_10 0 2 INCOHERENTCK_10 3 3 TXMARG_10 4 6 DEEMPH_10 7 7 COEFFICIENTID_10 8 9 COEFFICIENT_10 10 15 ixPB0_TX_LANE11_CTRL_REG0 2 0x1209600 4 0 4294967295 TX_CFG_DISPCLK_MODE_11 0 0 TX_CFG_INV_DATA_11 1 1 TX_CFG_SWING_BOOST_EN_11 2 2 TX_DBG_PRBS_EN_11 3 3 ixPB0_TX_LANE11_OVRD_REG0 2 0x1209604 8 0 4294967295 TX_DCLK_EN_OVRD_VAL_11 0 0 TX_DCLK_EN_OVRD_EN_11 1 1 TX_DRV_DATA_EN_OVRD_VAL_11 2 2 TX_DRV_DATA_EN_OVRD_EN_11 3 3 TX_DRV_PWRON_OVRD_VAL_11 4 4 TX_DRV_PWRON_OVRD_EN_11 5 5 TX_FRONTEND_PWRON_OVRD_VAL_11 6 6 TX_FRONTEND_PWRON_OVRD_EN_11 7 7 ixPB0_TX_LANE11_SCI_STAT_OVRD_REG0 2 0x1209608 6 0 4294967295 TXPWR_11 0 2 INCOHERENTCK_11 3 3 TXMARG_11 4 6 DEEMPH_11 7 7 COEFFICIENTID_11 8 9 COEFFICIENT_11 10 15 ixPB0_TX_LANE12_CTRL_REG0 2 0x1209840 4 0 4294967295 TX_CFG_DISPCLK_MODE_12 0 0 TX_CFG_INV_DATA_12 1 1 TX_CFG_SWING_BOOST_EN_12 2 2 TX_DBG_PRBS_EN_12 3 3 ixPB0_TX_LANE12_OVRD_REG0 2 0x1209844 8 0 4294967295 TX_DCLK_EN_OVRD_VAL_12 0 0 TX_DCLK_EN_OVRD_EN_12 1 1 TX_DRV_DATA_EN_OVRD_VAL_12 2 2 TX_DRV_DATA_EN_OVRD_EN_12 3 3 TX_DRV_PWRON_OVRD_VAL_12 4 4 TX_DRV_PWRON_OVRD_EN_12 5 5 TX_FRONTEND_PWRON_OVRD_VAL_12 6 6 TX_FRONTEND_PWRON_OVRD_EN_12 7 7 ixPB0_TX_LANE12_SCI_STAT_OVRD_REG0 2 0x1209848 6 0 4294967295 TXPWR_12 0 2 INCOHERENTCK_12 3 3 TXMARG_12 4 6 DEEMPH_12 7 7 COEFFICIENTID_12 8 9 COEFFICIENT_12 10 15 ixPB0_TX_LANE13_CTRL_REG0 2 0x1209880 4 0 4294967295 TX_CFG_DISPCLK_MODE_13 0 0 TX_CFG_INV_DATA_13 1 1 TX_CFG_SWING_BOOST_EN_13 2 2 TX_DBG_PRBS_EN_13 3 3 ixPB0_TX_LANE13_OVRD_REG0 2 0x1209884 8 0 4294967295 TX_DCLK_EN_OVRD_VAL_13 0 0 TX_DCLK_EN_OVRD_EN_13 1 1 TX_DRV_DATA_EN_OVRD_VAL_13 2 2 TX_DRV_DATA_EN_OVRD_EN_13 3 3 TX_DRV_PWRON_OVRD_VAL_13 4 4 TX_DRV_PWRON_OVRD_EN_13 5 5 TX_FRONTEND_PWRON_OVRD_VAL_13 6 6 TX_FRONTEND_PWRON_OVRD_EN_13 7 7 ixPB0_TX_LANE13_SCI_STAT_OVRD_REG0 2 0x1209888 6 0 4294967295 TXPWR_13 0 2 INCOHERENTCK_13 3 3 TXMARG_13 4 6 DEEMPH_13 7 7 COEFFICIENTID_13 8 9 COEFFICIENT_13 10 15 ixPB0_TX_LANE14_CTRL_REG0 2 0x1209900 4 0 4294967295 TX_CFG_DISPCLK_MODE_14 0 0 TX_CFG_INV_DATA_14 1 1 TX_CFG_SWING_BOOST_EN_14 2 2 TX_DBG_PRBS_EN_14 3 3 ixPB0_TX_LANE14_OVRD_REG0 2 0x1209904 8 0 4294967295 TX_DCLK_EN_OVRD_VAL_14 0 0 TX_DCLK_EN_OVRD_EN_14 1 1 TX_DRV_DATA_EN_OVRD_VAL_14 2 2 TX_DRV_DATA_EN_OVRD_EN_14 3 3 TX_DRV_PWRON_OVRD_VAL_14 4 4 TX_DRV_PWRON_OVRD_EN_14 5 5 TX_FRONTEND_PWRON_OVRD_VAL_14 6 6 TX_FRONTEND_PWRON_OVRD_EN_14 7 7 ixPB0_TX_LANE14_SCI_STAT_OVRD_REG0 2 0x1209908 6 0 4294967295 TXPWR_14 0 2 INCOHERENTCK_14 3 3 TXMARG_14 4 6 DEEMPH_14 7 7 COEFFICIENTID_14 8 9 COEFFICIENT_14 10 15 ixPB0_TX_LANE15_CTRL_REG0 2 0x1209a00 4 0 4294967295 TX_CFG_DISPCLK_MODE_15 0 0 TX_CFG_INV_DATA_15 1 1 TX_CFG_SWING_BOOST_EN_15 2 2 TX_DBG_PRBS_EN_15 3 3 ixPB0_TX_LANE15_OVRD_REG0 2 0x1209a04 8 0 4294967295 TX_DCLK_EN_OVRD_VAL_15 0 0 TX_DCLK_EN_OVRD_EN_15 1 1 TX_DRV_DATA_EN_OVRD_VAL_15 2 2 TX_DRV_DATA_EN_OVRD_EN_15 3 3 TX_DRV_PWRON_OVRD_VAL_15 4 4 TX_DRV_PWRON_OVRD_EN_15 5 5 TX_FRONTEND_PWRON_OVRD_VAL_15 6 6 TX_FRONTEND_PWRON_OVRD_EN_15 7 7 ixPB0_TX_LANE15_SCI_STAT_OVRD_REG0 2 0x1209a08 6 0 4294967295 TXPWR_15 0 2 INCOHERENTCK_15 3 3 TXMARG_15 4 6 DEEMPH_15 7 7 COEFFICIENTID_15 8 9 COEFFICIENT_15 10 15 ixPB1_GLB_CTRL_REG0 2 0x2200004 8 0 4294967295 BACKUP 0 15 CFG_IDLEDET_TH 16 17 DBG_RX2TXBYP_SEL 20 22 DBG_RXFEBYP_EN 23 23 DBG_RXPRBS_CLR 24 24 DBG_RXTOGGLE_EN 25 25 DBG_TX2RXLBACK_EN 26 26 TXCFG_CMGOOD_RANGE 30 31 ixPB1_GLB_CTRL_REG1 2 0x2200008 10 0 4294967295 RXDBG_CDR_FR_BYP_EN 0 0 RXDBG_CDR_FR_BYP_VAL 1 6 RXDBG_CDR_PH_BYP_EN 7 7 RXDBG_CDR_PH_BYP_VAL 8 13 RXDBG_D0TH_BYP_EN 14 14 RXDBG_D0TH_BYP_VAL 15 21 RXDBG_D1TH_BYP_EN 22 22 RXDBG_D1TH_BYP_VAL 23 29 TST_LOSPDTST_EN 30 30 PLL_CFG_DISPCLK_DIV 31 31 ixPB1_GLB_CTRL_REG2 2 0x220000c 8 0 4294967295 RXDBG_D2TH_BYP_EN 0 0 RXDBG_D2TH_BYP_VAL 1 7 RXDBG_D3TH_BYP_EN 8 8 RXDBG_D3TH_BYP_VAL 9 15 RXDBG_DXTH_BYP_EN 16 16 RXDBG_DXTH_BYP_VAL 17 23 RXDBG_ETH_BYP_EN 24 24 RXDBG_ETH_BYP_VAL 25 31 ixPB1_GLB_CTRL_REG3 2 0x2200010 14 0 4294967295 RXDBG_SEL 0 4 BG_CFG_LC_REG_VREF0_SEL 5 6 BG_CFG_LC_REG_VREF1_SEL 7 8 BG_CFG_RO_REG_VREF_SEL 9 10 BG_DBG_VREFBYP_EN 11 11 BG_DBG_IREFBYP_EN 12 12 BG_DBG_ANALOG_SEL 14 16 DBG_DLL_CLK_SEL 18 20 PLL_DISPCLK_CMOS_SEL 21 21 DBG_RXPI_OFFSET_BYP_EN 22 22 DBG_RXPI_OFFSET_BYP_VAL 23 26 DBG_RXSWAPDX_BYP_EN 27 27 DBG_RXSWAPDX_BYP_VAL 28 30 DBG_RXLEQ_DCATTN_BYP_OVR_DISABLE 31 31 ixPB1_GLB_CTRL_REG4 2 0x2200014 7 0 4294967295 DBG_RXAPU_INST 0 15 DBG_RXDFEMUX_BYP_VAL 16 17 DBG_RXDFEMUX_BYP_EN 18 18 DBG_RXAPU_EXEC 22 25 DBG_RXDLL_VREG_REF_SEL 26 26 PWRGOOD_OVRD 27 27 DBG_RXRDATA_GATING_DISABLE 28 28 ixPB1_GLB_CTRL_REG5 2 0x2200018 1 0 4294967295 DBG_RXAPU_MODE 0 7 ixPB1_GLB_SCI_STAT_OVRD_REG0 2 0x220001c 9 0 4294967295 IGNR_ALL_SCI_UPDT_L0T3 0 0 IGNR_ALL_SCI_UPDT_L4T7 1 1 IGNR_ALL_SCI_UPDT_L8T11 2 2 IGNR_ALL_SCI_UPDT_L12T15 3 3 IGNR_IMPCAL_ACTIVE_SCI_UPDT 4 4 TXNIMP 8 11 TXPIMP 12 15 RXIMP 16 19 IMPCAL_ACTIVE 20 20 ixPB1_GLB_SCI_STAT_OVRD_REG1 2 0x2200020 15 0 4294967295 IGNR_MODE_SCI_UPDT_L0T3 0 0 IGNR_FREQDIV_SCI_UPDT_L0T3 1 1 IGNR_DLL_LOCK_SCI_UPDT_L0T3 2 2 DLL_LOCK_0 12 12 DLL_LOCK_1 13 13 DLL_LOCK_2 14 14 DLL_LOCK_3 15 15 MODE_0 16 17 FREQDIV_0 18 19 MODE_1 20 21 FREQDIV_1 22 23 MODE_2 24 25 FREQDIV_2 26 27 MODE_3 28 29 FREQDIV_3 30 31 ixPB1_GLB_SCI_STAT_OVRD_REG2 2 0x2200024 15 0 4294967295 IGNR_MODE_SCI_UPDT_L4T7 0 0 IGNR_FREQDIV_SCI_UPDT_L4T7 1 1 IGNR_DLL_LOCK_SCI_UPDT_L4T7 2 2 DLL_LOCK_4 12 12 DLL_LOCK_5 13 13 DLL_LOCK_6 14 14 DLL_LOCK_7 15 15 MODE_4 16 17 FREQDIV_4 18 19 MODE_5 20 21 FREQDIV_5 22 23 MODE_6 24 25 FREQDIV_6 26 27 MODE_7 28 29 FREQDIV_7 30 31 ixPB1_GLB_SCI_STAT_OVRD_REG3 2 0x2200028 15 0 4294967295 IGNR_MODE_SCI_UPDT_L8T11 0 0 IGNR_FREQDIV_SCI_UPDT_L8T11 1 1 IGNR_DLL_LOCK_SCI_UPDT_L8T11 2 2 DLL_LOCK_8 12 12 DLL_LOCK_9 13 13 DLL_LOCK_10 14 14 DLL_LOCK_11 15 15 MODE_8 16 17 FREQDIV_8 18 19 MODE_9 20 21 FREQDIV_9 22 23 MODE_10 24 25 FREQDIV_10 26 27 MODE_11 28 29 FREQDIV_11 30 31 ixPB1_GLB_SCI_STAT_OVRD_REG4 2 0x220002c 15 0 4294967295 IGNR_MODE_SCI_UPDT_L12T15 0 0 IGNR_FREQDIV_SCI_UPDT_L12T15 1 1 IGNR_DLL_LOCK_SCI_UPDT_L12T15 2 2 DLL_LOCK_12 12 12 DLL_LOCK_13 13 13 DLL_LOCK_14 14 14 DLL_LOCK_15 15 15 MODE_12 16 17 FREQDIV_12 18 19 MODE_13 20 21 FREQDIV_13 22 23 MODE_14 24 25 FREQDIV_14 26 27 MODE_15 28 29 FREQDIV_15 30 31 ixPB1_GLB_OVRD_REG0 2 0x2200030 2 0 4294967295 TXPDTERM_VAL_OVRD_VAL 0 15 TXPUTERM_VAL_OVRD_VAL 16 31 ixPB1_GLB_OVRD_REG1 2 0x2200034 6 0 4294967295 TXPDTERM_VAL_OVRD_EN 0 0 TXPUTERM_VAL_OVRD_EN 1 1 TST_LOSPDTST_RST_OVRD_EN 2 2 TST_LOSPDTST_RST_OVRD_VAL 3 3 RXTERM_VAL_OVRD_EN 15 15 RXTERM_VAL_OVRD_VAL 16 31 ixPB1_GLB_OVRD_REG2 2 0x2200038 2 0 4294967295 BG_PWRON_OVRD_EN 0 0 BG_PWRON_OVRD_VAL 1 1 ixPB1_HW_DEBUG 2 0x2202004 32 0 4294967295 PB1_HW_00_DEBUG 0 0 PB1_HW_01_DEBUG 1 1 PB1_HW_02_DEBUG 2 2 PB1_HW_03_DEBUG 3 3 PB1_HW_04_DEBUG 4 4 PB1_HW_05_DEBUG 5 5 PB1_HW_06_DEBUG 6 6 PB1_HW_07_DEBUG 7 7 PB1_HW_08_DEBUG 8 8 PB1_HW_09_DEBUG 9 9 PB1_HW_10_DEBUG 10 10 PB1_HW_11_DEBUG 11 11 PB1_HW_12_DEBUG 12 12 PB1_HW_13_DEBUG 13 13 PB1_HW_14_DEBUG 14 14 PB1_HW_15_DEBUG 15 15 PB1_HW_16_DEBUG 16 16 PB1_HW_17_DEBUG 17 17 PB1_HW_18_DEBUG 18 18 PB1_HW_19_DEBUG 19 19 PB1_HW_20_DEBUG 20 20 PB1_HW_21_DEBUG 21 21 PB1_HW_22_DEBUG 22 22 PB1_HW_23_DEBUG 23 23 PB1_HW_24_DEBUG 24 24 PB1_HW_25_DEBUG 25 25 PB1_HW_26_DEBUG 26 26 PB1_HW_27_DEBUG 27 27 PB1_HW_28_DEBUG 28 28 PB1_HW_29_DEBUG 29 29 PB1_HW_30_DEBUG 30 30 PB1_HW_31_DEBUG 31 31 ixPB1_STRAP_GLB_REG0 2 0x2202020 12 0 4294967295 STRAP_QUICK_SIM_START 1 1 STRAP_DFT_RXBSCAN_EN_VAL 2 2 STRAP_DFT_CALIB_BYPASS 3 3 STRAP_CFG_IDLEDET_TH 5 6 STRAP_RX_CFG_LEQ_DCATTN_BYP_VAL 7 11 STRAP_RX_CFG_OVR_PWRSF 12 12 STRAP_RX_TRK_MODE_0_ 13 13 STRAP_PWRGOOD_OVRD 14 14 STRAP_DBG_RXDLL_VREG_REF_SEL 15 15 STRAP_PLL_CFG_LC_VCO_TUNE 16 19 STRAP_DBG_RXRDATA_GATING_DISABLE 20 20 STRAP_DBG_RXPI_OFFSET_BYP_VAL 21 24 ixPB1_STRAP_TX_REG0 2 0x2202024 10 0 4294967295 STRAP_TX_CFG_DRV0_EN 1 4 STRAP_TX_CFG_DRV0_TAP_SEL 5 8 STRAP_TX_CFG_DRV1_EN 9 13 STRAP_TX_CFG_DRV1_TAP_SEL 14 18 STRAP_TX_CFG_DRV2_EN 19 22 STRAP_TX_CFG_DRV2_TAP_SEL 23 26 STRAP_TX_CFG_DRVX_EN 27 27 STRAP_TX_CFG_DRVX_TAP_SEL 28 28 STRAP_RX_TRK_MODE_1_ 29 29 STRAP_TX_CFG_SWING_BOOST_EN 30 30 ixPB1_STRAP_RX_REG0 2 0x2202028 12 0 4294967295 STRAP_RX_CFG_TH_LOOP_GAIN 1 4 STRAP_RX_CFG_DLL_FLOCK_DISABLE 5 5 STRAP_DBG_RXPI_OFFSET_BYP_EN 6 6 STRAP_RX_CFG_LEQ_DCATTN_BYP_DIS 7 7 STRAP_BG_CFG_LC_REG_VREF0_SEL 8 9 STRAP_BG_CFG_LC_REG_VREF1_SEL 10 11 STRAP_RX_CFG_CDR_TIME 12 15 STRAP_RX_CFG_FOM_TIME 16 19 STRAP_RX_CFG_LEQ_TIME 20 23 STRAP_RX_CFG_OC_TIME 24 27 STRAP_TX_CFG_RPTR_RST_VAL 28 30 STRAP_RX_CFG_TERM_MODE 31 31 ixPB1_STRAP_RX_REG1 2 0x220202c 10 0 4294967295 STRAP_RX_CFG_CDR_PI_STPSZ 1 1 STRAP_TX_DEEMPH_PRSHT_STNG 2 4 STRAP_BG_CFG_RO_REG_VREF_SEL 5 6 STRAP_RX_CFG_LEQ_POLE_BYP_DIS 7 7 STRAP_RX_CFG_LEQ_POLE_BYP_VAL 8 10 STRAP_RX_CFG_CDR_PH_GAIN 11 14 STRAP_RX_CFG_ADAPT_MODE 15 24 STRAP_RX_CFG_DFE_TIME 25 28 STRAP_RX_CFG_LEQ_LOOP_GAIN 29 30 STRAP_RX_CFG_LEQ_SHUNT_DIS 31 31 ixPB1_STRAP_PLL_REG0 2 0x2202030 6 0 4294967295 STRAP_PLL_CFG_LC_BW_CNTRL 1 3 STRAP_PLL_CFG_LC_LF_CNTRL 4 12 STRAP_TX_RXDET_X1_SSF 13 13 STRAP_PLL_CFG_RO_VTOI_BIAS_CNTRL_DIS 15 15 STRAP_PLL_CFG_RO_BW_CNTRL 16 23 STRAP_PLL_STRAP_SEL 24 24 ixPB1_STRAP_PIN_REG0 2 0x2202034 2 0 4294967295 STRAP_TX_DEEMPH_EN 1 1 STRAP_TX_FULL_SWING 2 2 ixPB1_DFT_JIT_INJ_REG0 2 0x2203000 8 0 4294967295 DFT_NUM_STEPS 0 5 DFT_DISABLE_ERR 7 7 DFT_CLK_PER_STEP 8 11 DFT_MODE_CDR_EN 20 20 DFT_EN_RECOVERY 21 21 DFT_INCR_SWP_EN 22 22 DFT_DECR_SWP_EN 23 23 DFT_RECOVERY_TIME 24 31 ixPB1_DFT_JIT_INJ_REG1 2 0x2203004 5 0 4294967295 DFT_BYPASS_VALUE 0 7 DFT_BYPASS_EN 8 8 DFT_BLOCK_EN 16 16 DFT_NUM_OF_TESTS 17 19 DFT_CHECK_TIME 20 23 ixPB1_DFT_JIT_INJ_REG2 2 0x2203008 1 0 4294967295 DFT_LANE_EN 0 15 ixPB1_DFT_DEBUG_CTRL_REG0 2 0x220300c 2 0 4294967295 DFT_PHY_DEBUG_EN 0 0 DFT_PHY_DEBUG_MODE 1 5 ixPB1_DFT_JIT_INJ_STAT_REG0 2 0x2203010 3 0 4294967295 DFT_STAT_DECR 0 7 DFT_STAT_INCR 8 15 DFT_STAT_FINISHED 16 16 ixPB1_PLL_RO_GLB_CTRL_REG0 2 0x2204000 23 0 4294967295 PLL_TST_LOSPDTST_SRC 0 0 PLL_RO_HSCLK_LEFT_EN_LUT_ENTRY_LS0 1 1 PLL_RO_HSCLK_LEFT_EN_LUT_ENTRY_LS1 2 2 PLL_RO_HSCLK_LEFT_EN_LUT_ENTRY_LS2 3 3 PLL_RO_HSCLK_RIGHT_EN_LUT_ENTRY_LS0 4 4 PLL_RO_HSCLK_RIGHT_EN_LUT_ENTRY_LS1 5 5 PLL_RO_HSCLK_RIGHT_EN_LUT_ENTRY_LS2 6 6 PLL_RO_PWRON_LUT_ENTRY_LS2 7 7 PLL_LC_PWRON_LUT_ENTRY_LS2 8 8 PLL_LC_HSCLK_LEFT_EN_LUT_ENTRY_LS0 9 9 PLL_LC_HSCLK_LEFT_EN_LUT_ENTRY_LS1 10 10 PLL_LC_HSCLK_LEFT_EN_LUT_ENTRY_LS2 11 11 PLL_LC_HSCLK_RIGHT_EN_LUT_ENTRY_LS0 12 12 PLL_LC_HSCLK_RIGHT_EN_LUT_ENTRY_LS1 13 13 PLL_LC_HSCLK_RIGHT_EN_LUT_ENTRY_LS2 14 14 PLL_RO_HSCLK_LEFT_LEFT_EN_GATING_EN 16 16 PLL_RO_HSCLK_LEFT_RIGHT_EN_GATING_EN 17 17 PLL_RO_HSCLK_RIGHT_LEFT_EN_GATING_EN 18 18 PLL_RO_HSCLK_RIGHT_RIGHT_EN_GATING_EN 19 19 PLL_LC_HSCLK_LEFT_LEFT_EN_GATING_EN 20 20 PLL_LC_HSCLK_LEFT_RIGHT_EN_GATING_EN 21 21 PLL_LC_HSCLK_RIGHT_LEFT_EN_GATING_EN 22 22 PLL_LC_HSCLK_RIGHT_RIGHT_EN_GATING_EN 23 23 ixPB1_PLL_RO_GLB_OVRD_REG0 2 0x2204010 0 0 4294967295 ixPB1_PLL_RO0_CTRL_REG0 2 0x2204440 5 0 4294967295 PLL_DBG_RO_ANALOG_SEL_0 0 1 PLL_DBG_RO_EXT_RESET_EN_0 2 2 PLL_DBG_RO_VCTL_ADC_EN_0 3 3 PLL_DBG_RO_LF_CNTRL_0 4 10 PLL_TST_RO_USAMPLE_EN_0 11 11 ixPB1_PLL_RO0_OVRD_REG0 2 0x2204450 10 0 4294967295 PLL_CFG_RO_BW_CNTRL_OVRD_VAL_0 0 7 PLL_CFG_RO_BW_CNTRL_OVRD_EN_0 8 8 PLL_CFG_RO_CORECLK_DIV_OVRD_VAL_0 9 11 PLL_CFG_RO_CORECLK_DIV_OVRD_EN_0 12 12 PLL_CFG_RO_CORECLK_EN_OVRD_VAL_0 13 13 PLL_CFG_RO_CORECLK_EN_OVRD_EN_0 14 14 PLL_CFG_RO_FBDIV_OVRD_VAL_0 15 27 PLL_CFG_RO_FBDIV_OVRD_EN_0 28 28 PLL_CFG_RO_VTOI_BIAS_CNTRL_OVRD_VAL_0 30 30 PLL_CFG_RO_VTOI_BIAS_CNTRL_OVRD_EN_0 31 31 ixPB1_PLL_RO0_OVRD_REG1 2 0x2204454 12 0 4294967295 PLL_CFG_RO_REFDIV_OVRD_VAL_0 0 4 PLL_CFG_RO_REFDIV_OVRD_EN_0 5 5 PLL_CFG_RO_VCO_MODE_OVRD_VAL_0 6 7 PLL_CFG_RO_VCO_MODE_OVRD_EN_0 8 8 PLL_RO_HSCLK_LEFT_EN_OVRD_VAL_0 9 9 PLL_RO_HSCLK_LEFT_EN_OVRD_EN_0 10 10 PLL_RO_HSCLK_RIGHT_EN_OVRD_VAL_0 11 11 PLL_RO_HSCLK_RIGHT_EN_OVRD_EN_0 12 12 PLL_RO_PWRON_OVRD_VAL_0 13 13 PLL_RO_PWRON_OVRD_EN_0 14 14 PLL_CFG_RO_REFCLK_SRC_OVRD_VAL_0 19 21 PLL_CFG_RO_REFCLK_SRC_OVRD_EN_0 22 22 ixPB1_PLL_RO0_SCI_STAT_OVRD_REG0 2 0x2204460 4 0 4294967295 PLL_RO0_IGNR_PLLPWR_SCI_UPDT 0 0 PLL_RO0_IGNR_FREQMODE_SCI_UPDT 1 1 PLL_RO0_PLLPWR 4 6 PLL_RO0_FREQMODE 8 9 ixPB1_PLL_RO1_SCI_STAT_OVRD_REG0 2 0x2204464 4 0 4294967295 PLL_RO1_IGNR_PLLPWR_SCI_UPDT 0 0 PLL_RO1_IGNR_FREQMODE_SCI_UPDT 1 1 PLL_RO1_PLLPWR 4 6 PLL_RO1_FREQMODE 8 9 ixPB1_PLL_RO2_SCI_STAT_OVRD_REG0 2 0x2204468 4 0 4294967295 PLL_RO2_IGNR_PLLPWR_SCI_UPDT 0 0 PLL_RO2_IGNR_FREQMODE_SCI_UPDT 1 1 PLL_RO2_PLLPWR 4 6 PLL_RO2_FREQMODE 8 9 ixPB1_PLL_RO3_SCI_STAT_OVRD_REG0 2 0x220446c 4 0 4294967295 PLL_RO3_IGNR_PLLPWR_SCI_UPDT 0 0 PLL_RO3_IGNR_FREQMODE_SCI_UPDT 1 1 PLL_RO3_PLLPWR 4 6 PLL_RO3_FREQMODE 8 9 ixPB1_PLL_LC0_CTRL_REG0 2 0x2204480 4 0 4294967295 PLL_DBG_LC_ANALOG_SEL_0 0 1 PLL_DBG_LC_EXT_RESET_EN_0 2 2 PLL_DBG_LC_VCTL_ADC_EN_0 3 3 PLL_TST_LC_USAMPLE_EN_0 4 4 ixPB1_PLL_LC0_OVRD_REG0 2 0x2204490 12 0 4294967295 PLL_CFG_LC_BW_CNTRL_OVRD_VAL_0 0 2 PLL_CFG_LC_BW_CNTRL_OVRD_EN_0 3 3 PLL_CFG_LC_CORECLK_DIV_OVRD_VAL_0 4 6 PLL_CFG_LC_CORECLK_DIV_OVRD_EN_0 7 7 PLL_CFG_LC_CORECLK_EN_OVRD_VAL_0 8 8 PLL_CFG_LC_CORECLK_EN_OVRD_EN_0 9 9 PLL_CFG_LC_FBDIV_OVRD_VAL_0 10 17 PLL_CFG_LC_FBDIV_OVRD_EN_0 18 18 PLL_CFG_LC_LF_CNTRL_OVRD_VAL_0 19 27 PLL_CFG_LC_LF_CNTRL_OVRD_EN_0 28 28 PLL_CFG_LC_REFDIV_OVRD_VAL_0 29 30 PLL_CFG_LC_REFDIV_OVRD_EN_0 31 31 ixPB1_PLL_LC0_OVRD_REG1 2 0x2204494 10 0 4294967295 PLL_CFG_LC_REFCLK_SRC_OVRD_VAL_0 0 2 PLL_CFG_LC_REFCLK_SRC_OVRD_EN_0 3 3 PLL_LC_HSCLK_LEFT_EN_OVRD_VAL_0 4 4 PLL_LC_HSCLK_LEFT_EN_OVRD_EN_0 5 5 PLL_LC_HSCLK_RIGHT_EN_OVRD_VAL_0 6 6 PLL_LC_HSCLK_RIGHT_EN_OVRD_EN_0 7 7 PLL_LC_PWRON_OVRD_VAL_0 8 8 PLL_LC_PWRON_OVRD_EN_0 9 9 PLL_CFG_LC_VCO_TUNE_OVRD_VAL_0 14 17 PLL_CFG_LC_VCO_TUNE_OVRD_EN_0 18 18 ixPB1_PLL_LC0_SCI_STAT_OVRD_REG0 2 0x2204500 4 0 4294967295 PLL_LC0_IGNR_PLLPWR_SCI_UPDT 0 0 PLL_LC0_IGNR_FREQMODE_SCI_UPDT 1 1 PLL_LC0_PLLPWR 4 6 PLL_LC0_FREQMODE 8 9 ixPB1_PLL_LC1_SCI_STAT_OVRD_REG0 2 0x2204504 4 0 4294967295 PLL_LC1_IGNR_PLLPWR_SCI_UPDT 0 0 PLL_LC1_IGNR_FREQMODE_SCI_UPDT 1 1 PLL_LC1_PLLPWR 4 6 PLL_LC1_FREQMODE 8 9 ixPB1_PLL_LC2_SCI_STAT_OVRD_REG0 2 0x2204508 4 0 4294967295 PLL_LC2_IGNR_PLLPWR_SCI_UPDT 0 0 PLL_LC2_IGNR_FREQMODE_SCI_UPDT 1 1 PLL_LC2_PLLPWR 4 6 PLL_LC2_FREQMODE 8 9 ixPB1_PLL_LC3_SCI_STAT_OVRD_REG0 2 0x220450c 4 0 4294967295 PLL_LC3_IGNR_PLLPWR_SCI_UPDT 0 0 PLL_LC3_IGNR_FREQMODE_SCI_UPDT 1 1 PLL_LC3_PLLPWR 4 6 PLL_LC3_FREQMODE 8 9 ixPB1_RX_GLB_CTRL_REG0 2 0x2206000 4 0 4294967295 RX_CFG_ADAPT_MODE_GEN1 0 9 RX_CFG_ADAPT_MODE_GEN2 10 19 RX_CFG_ADAPT_MODE_GEN3 20 29 RX_CFG_ADAPT_RST_MODE 30 31 ixPB1_RX_GLB_CTRL_REG1 2 0x2206004 13 0 4294967295 RX_CFG_CDR_FR_GAIN_GEN1 0 3 RX_CFG_CDR_FR_GAIN_GEN2 4 7 RX_CFG_CDR_FR_GAIN_GEN3 8 11 RX_CFG_CDR_PH_GAIN_GEN1 12 15 RX_CFG_CDR_PH_GAIN_GEN2 16 19 RX_CFG_CDR_PH_GAIN_GEN3 20 23 RX_CFG_CDR_PI_STPSZ_GEN1 24 24 RX_CFG_CDR_PI_STPSZ_GEN2 25 25 RX_CFG_CDR_PI_STPSZ_GEN3 26 26 RX_CFG_LEQ_DCATTN_BYP_EN_GEN1 27 27 RX_CFG_LEQ_DCATTN_BYP_EN_GEN2 28 28 RX_CFG_LEQ_DCATTN_BYP_EN_GEN3 29 29 RX_ADAPT_HLD_ASRT_TO_DCLK_EN 30 31 ixPB1_RX_GLB_CTRL_REG2 2 0x2206008 7 0 4294967295 RX_CFG_CDR_TIME_GEN1 12 15 RX_CFG_CDR_TIME_GEN2 16 19 RX_CFG_CDR_TIME_GEN3 20 23 RX_CFG_LEQ_LOOP_GAIN_GEN1 24 25 RX_CFG_LEQ_LOOP_GAIN_GEN2 26 27 RX_CFG_LEQ_LOOP_GAIN_GEN3 28 29 RX_DCLK_EN_ASRT_TO_ADAPT_HLD 30 31 ixPB1_RX_GLB_CTRL_REG3 2 0x220600c 6 0 4294967295 RX_CFG_CDR_FR_EN_GEN1 0 0 RX_CFG_CDR_FR_EN_GEN2 1 1 RX_CFG_CDR_FR_EN_GEN3 2 2 RX_CFG_DFE_TIME_GEN1 20 23 RX_CFG_DFE_TIME_GEN2 24 27 RX_CFG_DFE_TIME_GEN3 28 31 ixPB1_RX_GLB_CTRL_REG4 2 0x2206010 9 0 4294967295 RX_CFG_FOM_BER_GEN1 0 2 RX_CFG_FOM_BER_GEN2 3 5 RX_CFG_FOM_BER_GEN3 6 8 RX_CFG_LEQ_POLE_BYP_VAL_GEN1 9 11 RX_CFG_LEQ_POLE_BYP_VAL_GEN2 12 14 RX_CFG_LEQ_POLE_BYP_VAL_GEN3 15 17 RX_CFG_FOM_TIME_GEN1 20 23 RX_CFG_FOM_TIME_GEN2 24 27 RX_CFG_FOM_TIME_GEN3 28 31 ixPB1_RX_GLB_CTRL_REG5 2 0x2206014 14 0 4294967295 RX_CFG_LEQ_DCATTN_BYP_VAL_GEN1 0 4 RX_CFG_LEQ_DCATTN_BYP_VAL_GEN2 5 9 RX_CFG_LEQ_DCATTN_BYP_VAL_GEN3 10 14 RX_CFG_LEQ_POLE_BYP_EN_GEN1 15 15 RX_CFG_LEQ_POLE_BYP_EN_GEN2 16 16 RX_CFG_LEQ_POLE_BYP_EN_GEN3 17 17 RX_CFG_LEQ_SHUNT_EN_GEN1 18 18 RX_CFG_LEQ_SHUNT_EN_GEN2 19 19 RX_CFG_LEQ_SHUNT_EN_GEN3 20 20 RX_CFG_TERM_MODE_GEN1 27 27 RX_CFG_TERM_MODE_GEN2 28 28 RX_CFG_TERM_MODE_GEN3 29 29 RX_FORCE_DLL_RST_RXPWR_LS2OFF_TO_LS0 30 30 RX_ADAPT_AUX_PWRON_MODE 31 31 ixPB1_RX_GLB_CTRL_REG6 2 0x2206018 10 0 4294967295 RX_CFG_LEQ_TIME_GEN1 0 3 RX_CFG_LEQ_TIME_GEN2 4 7 RX_CFG_LEQ_TIME_GEN3 8 11 RX_CFG_OC_TIME_GEN1 12 15 RX_CFG_OC_TIME_GEN2 16 19 RX_CFG_OC_TIME_GEN3 20 23 RX_FRONTEND_PWRON_LUT_ENTRY_LS0_CDR_EN_0 24 24 RX_FRONTEND_PWRON_LUT_ENTRY_LS2 26 26 RX_AUX_PWRON_LUT_ENTRY_LS2 27 27 RX_ADAPT_HLD_L0S_EARLY_EXIT_DIS 28 28 ixPB1_RX_GLB_CTRL_REG7 2 0x220601c 12 0 4294967295 RX_CFG_TH_LOOP_GAIN_GEN1 0 3 RX_CFG_TH_LOOP_GAIN_GEN2 4 7 RX_CFG_TH_LOOP_GAIN_GEN3 8 11 RX_DCLK_EN_LUT_ENTRY_LS0_CDR_EN_0 12 12 RX_DCLK_EN_LUT_ENTRY_LS2 13 13 RX_DLL_PWRON_LUT_ENTRY_LS2 17 17 RX_CFG_DLL_CPI_SEL_GEN1 18 20 RX_CFG_DLL_CPI_SEL_GEN2 21 23 RX_CFG_DLL_CPI_SEL_GEN3 24 26 RX_CFG_DLL_FLOCK_DISABLE_GEN1 27 27 RX_CFG_DLL_FLOCK_DISABLE_GEN2 28 28 RX_CFG_DLL_FLOCK_DISABLE_GEN3 29 29 ixPB1_RX_GLB_CTRL_REG8 2 0x2206020 2 0 4294967295 RX_DLL_LOCK_TIME 0 1 RX_DLL_SPEEDCHANGE_RESET_TIME 2 3 ixPB1_RX_GLB_SCI_STAT_OVRD_REG0 2 0x2206028 24 0 4294967295 IGNR_RXPWR_SCI_UPDT_L0T3 0 0 IGNR_RXPWR_SCI_UPDT_L4T7 1 1 IGNR_RXPWR_SCI_UPDT_L8T11 2 2 IGNR_RXPWR_SCI_UPDT_L12T15 3 3 IGNR_ELECIDLEDETEN_SCI_UPDT_L0T3 4 4 IGNR_ELECIDLEDETEN_SCI_UPDT_L4T7 5 5 IGNR_ELECIDLEDETEN_SCI_UPDT_L8T11 6 6 IGNR_ELECIDLEDETEN_SCI_UPDT_L12T15 7 7 IGNR_RXPRESETHINT_SCI_UPDT_L0T3 8 8 IGNR_RXPRESETHINT_SCI_UPDT_L4T7 9 9 IGNR_RXPRESETHINT_SCI_UPDT_L8T11 10 10 IGNR_RXPRESETHINT_SCI_UPDT_L12T15 11 11 IGNR_ENABLEFOM_SCI_UPDT_L0T3 12 12 IGNR_ENABLEFOM_SCI_UPDT_L4T7 13 13 IGNR_ENABLEFOM_SCI_UPDT_L8T11 14 14 IGNR_ENABLEFOM_SCI_UPDT_L12T15 15 15 IGNR_REQUESTFOM_SCI_UPDT_L0T3 16 16 IGNR_REQUESTFOM_SCI_UPDT_L4T7 17 17 IGNR_REQUESTFOM_SCI_UPDT_L8T11 18 18 IGNR_REQUESTFOM_SCI_UPDT_L12T15 19 19 IGNR_RESPONSEMODE_SCI_UPDT_L0T3 20 20 IGNR_RESPONSEMODE_SCI_UPDT_L4T7 21 21 IGNR_RESPONSEMODE_SCI_UPDT_L8T11 22 22 IGNR_RESPONSEMODE_SCI_UPDT_L12T15 23 23 ixPB1_RX_GLB_OVRD_REG0 2 0x2206030 26 0 4294967295 RX_ADAPT_HLD_OVRD_VAL 0 0 RX_ADAPT_HLD_OVRD_EN 1 1 RX_ADAPT_RST_OVRD_VAL 2 2 RX_ADAPT_RST_OVRD_EN 3 3 RX_CFG_DCLK_DIV_OVRD_VAL 6 7 RX_CFG_DCLK_DIV_OVRD_EN 8 8 RX_CFG_DLL_FREQ_MODE_OVRD_VAL 9 9 RX_CFG_DLL_FREQ_MODE_OVRD_EN 10 10 RX_CFG_PLLCLK_SEL_OVRD_VAL 11 11 RX_CFG_PLLCLK_SEL_OVRD_EN 12 12 RX_CFG_RCLK_DIV_OVRD_VAL 13 13 RX_CFG_RCLK_DIV_OVRD_EN 14 14 RX_DCLK_EN_OVRD_VAL 15 15 RX_DCLK_EN_OVRD_EN 16 16 RX_DLL_PWRON_OVRD_VAL 17 17 RX_DLL_PWRON_OVRD_EN 18 18 RX_FRONTEND_PWRON_OVRD_VAL 19 19 RX_FRONTEND_PWRON_OVRD_EN 20 20 RX_IDLEDET_PWRON_OVRD_VAL 21 21 RX_IDLEDET_PWRON_OVRD_EN 22 22 RX_TERM_EN_OVRD_VAL 23 23 RX_TERM_EN_OVRD_EN 24 24 RX_AUX_PWRON_OVRD_VAL 28 28 RX_AUX_PWRON_OVRD_EN 29 29 RX_ADAPT_FOM_OVRD_VAL 30 30 RX_ADAPT_FOM_OVRD_EN 31 31 ixPB1_RX_GLB_OVRD_REG1 2 0x2206034 2 0 4294967295 RX_ADAPT_TRK_OVRD_VAL 0 0 RX_ADAPT_TRK_OVRD_EN 1 1 ixPB1_RX_LANE0_CTRL_REG0 2 0x2206440 4 0 4294967295 RX_BACKUP_0 0 7 RX_DBG_ANALOG_SEL_0 10 11 RX_TST_BSCAN_EN_0 12 12 RX_CFG_OVR_PWRSF_0 13 13 ixPB1_RX_LANE0_SCI_STAT_OVRD_REG0 2 0x2206448 6 0 4294967295 RXPWR_0 0 2 ELECIDLEDETEN_0 3 3 RXPRESETHINT_0 4 6 ENABLEFOM_0 7 7 REQUESTFOM_0 8 8 RESPONSEMODE_0 9 9 ixPB1_RX_LANE1_CTRL_REG0 2 0x2206480 4 0 4294967295 RX_BACKUP_1 0 7 RX_DBG_ANALOG_SEL_1 10 11 RX_TST_BSCAN_EN_1 12 12 RX_CFG_OVR_PWRSF_1 13 13 ixPB1_RX_LANE1_SCI_STAT_OVRD_REG0 2 0x2206488 6 0 4294967295 RXPWR_1 0 2 ELECIDLEDETEN_1 3 3 RXPRESETHINT_1 4 6 ENABLEFOM_1 7 7 REQUESTFOM_1 8 8 RESPONSEMODE_1 9 9 ixPB1_RX_LANE2_CTRL_REG0 2 0x2206500 4 0 4294967295 RX_BACKUP_2 0 7 RX_DBG_ANALOG_SEL_2 10 11 RX_TST_BSCAN_EN_2 12 12 RX_CFG_OVR_PWRSF_2 13 13 ixPB1_RX_LANE2_SCI_STAT_OVRD_REG0 2 0x2206508 6 0 4294967295 RXPWR_2 0 2 ELECIDLEDETEN_2 3 3 RXPRESETHINT_2 4 6 ENABLEFOM_2 7 7 REQUESTFOM_2 8 8 RESPONSEMODE_2 9 9 ixPB1_RX_LANE3_CTRL_REG0 2 0x2206600 4 0 4294967295 RX_BACKUP_3 0 7 RX_DBG_ANALOG_SEL_3 10 11 RX_TST_BSCAN_EN_3 12 12 RX_CFG_OVR_PWRSF_3 13 13 ixPB1_RX_LANE3_SCI_STAT_OVRD_REG0 2 0x2206608 6 0 4294967295 RXPWR_3 0 2 ELECIDLEDETEN_3 3 3 RXPRESETHINT_3 4 6 ENABLEFOM_3 7 7 REQUESTFOM_3 8 8 RESPONSEMODE_3 9 9 ixPB1_RX_LANE4_CTRL_REG0 2 0x2206800 4 0 4294967295 RX_BACKUP_4 0 7 RX_DBG_ANALOG_SEL_4 10 11 RX_TST_BSCAN_EN_4 12 12 RX_CFG_OVR_PWRSF_4 13 13 ixPB1_RX_LANE4_SCI_STAT_OVRD_REG0 2 0x2206848 6 0 4294967295 RXPWR_4 0 2 ELECIDLEDETEN_4 3 3 RXPRESETHINT_4 4 6 ENABLEFOM_4 7 7 REQUESTFOM_4 8 8 RESPONSEMODE_4 9 9 ixPB1_RX_LANE5_CTRL_REG0 2 0x2206880 4 0 4294967295 RX_BACKUP_5 0 7 RX_DBG_ANALOG_SEL_5 10 11 RX_TST_BSCAN_EN_5 12 12 RX_CFG_OVR_PWRSF_5 13 13 ixPB1_RX_LANE5_SCI_STAT_OVRD_REG0 2 0x2206888 6 0 4294967295 RXPWR_5 0 2 ELECIDLEDETEN_5 3 3 RXPRESETHINT_5 4 6 ENABLEFOM_5 7 7 REQUESTFOM_5 8 8 RESPONSEMODE_5 9 9 ixPB1_RX_LANE6_CTRL_REG0 2 0x2206900 4 0 4294967295 RX_BACKUP_6 0 7 RX_DBG_ANALOG_SEL_6 10 11 RX_TST_BSCAN_EN_6 12 12 RX_CFG_OVR_PWRSF_6 13 13 ixPB1_RX_LANE6_SCI_STAT_OVRD_REG0 2 0x2206908 6 0 4294967295 RXPWR_6 0 2 ELECIDLEDETEN_6 3 3 RXPRESETHINT_6 4 6 ENABLEFOM_6 7 7 REQUESTFOM_6 8 8 RESPONSEMODE_6 9 9 ixPB1_RX_LANE7_CTRL_REG0 2 0x2206a00 4 0 4294967295 RX_BACKUP_7 0 7 RX_DBG_ANALOG_SEL_7 10 11 RX_TST_BSCAN_EN_7 12 12 RX_CFG_OVR_PWRSF_7 13 13 ixPB1_RX_LANE7_SCI_STAT_OVRD_REG0 2 0x2206a08 6 0 4294967295 RXPWR_7 0 2 ELECIDLEDETEN_7 3 3 RXPRESETHINT_7 4 6 ENABLEFOM_7 7 7 REQUESTFOM_7 8 8 RESPONSEMODE_7 9 9 ixPB1_RX_LANE8_CTRL_REG0 2 0x2207440 4 0 4294967295 RX_BACKUP_8 0 7 RX_DBG_ANALOG_SEL_8 10 11 RX_TST_BSCAN_EN_8 12 12 RX_CFG_OVR_PWRSF_8 13 13 ixPB1_RX_LANE8_SCI_STAT_OVRD_REG0 2 0x2207448 6 0 4294967295 RXPWR_8 0 2 ELECIDLEDETEN_8 3 3 RXPRESETHINT_8 4 6 ENABLEFOM_8 7 7 REQUESTFOM_8 8 8 RESPONSEMODE_8 9 9 ixPB1_RX_LANE9_CTRL_REG0 2 0x2207480 4 0 4294967295 RX_BACKUP_9 0 7 RX_DBG_ANALOG_SEL_9 10 11 RX_TST_BSCAN_EN_9 12 12 RX_CFG_OVR_PWRSF_9 13 13 ixPB1_RX_LANE9_SCI_STAT_OVRD_REG0 2 0x2207488 6 0 4294967295 RXPWR_9 0 2 ELECIDLEDETEN_9 3 3 RXPRESETHINT_9 4 6 ENABLEFOM_9 7 7 REQUESTFOM_9 8 8 RESPONSEMODE_9 9 9 ixPB1_RX_LANE10_CTRL_REG0 2 0x2207500 4 0 4294967295 RX_BACKUP_10 0 7 RX_DBG_ANALOG_SEL_10 10 11 RX_TST_BSCAN_EN_10 12 12 RX_CFG_OVR_PWRSF_10 13 13 ixPB1_RX_LANE10_SCI_STAT_OVRD_REG0 2 0x2207508 6 0 4294967295 RXPWR_10 0 2 ELECIDLEDETEN_10 3 3 RXPRESETHINT_10 4 6 ENABLEFOM_10 7 7 REQUESTFOM_10 8 8 RESPONSEMODE_10 9 9 ixPB1_RX_LANE11_CTRL_REG0 2 0x2207600 4 0 4294967295 RX_BACKUP_11 0 7 RX_DBG_ANALOG_SEL_11 10 11 RX_TST_BSCAN_EN_11 12 12 RX_CFG_OVR_PWRSF_11 13 13 ixPB1_RX_LANE11_SCI_STAT_OVRD_REG0 2 0x2207608 6 0 4294967295 RXPWR_11 0 2 ELECIDLEDETEN_11 3 3 RXPRESETHINT_11 4 6 ENABLEFOM_11 7 7 REQUESTFOM_11 8 8 RESPONSEMODE_11 9 9 ixPB1_RX_LANE12_CTRL_REG0 2 0x2207840 4 0 4294967295 RX_BACKUP_12 0 7 RX_DBG_ANALOG_SEL_12 10 11 RX_TST_BSCAN_EN_12 12 12 RX_CFG_OVR_PWRSF_12 13 13 ixPB1_RX_LANE12_SCI_STAT_OVRD_REG0 2 0x2207848 6 0 4294967295 RXPWR_12 0 2 ELECIDLEDETEN_12 3 3 RXPRESETHINT_12 4 6 ENABLEFOM_12 7 7 REQUESTFOM_12 8 8 RESPONSEMODE_12 9 9 ixPB1_RX_LANE13_CTRL_REG0 2 0x2207880 4 0 4294967295 RX_BACKUP_13 0 7 RX_DBG_ANALOG_SEL_13 10 11 RX_TST_BSCAN_EN_13 12 12 RX_CFG_OVR_PWRSF_13 13 13 ixPB1_RX_LANE13_SCI_STAT_OVRD_REG0 2 0x2207888 6 0 4294967295 RXPWR_13 0 2 ELECIDLEDETEN_13 3 3 RXPRESETHINT_13 4 6 ENABLEFOM_13 7 7 REQUESTFOM_13 8 8 RESPONSEMODE_13 9 9 ixPB1_RX_LANE14_CTRL_REG0 2 0x2207900 4 0 4294967295 RX_BACKUP_14 0 7 RX_DBG_ANALOG_SEL_14 10 11 RX_TST_BSCAN_EN_14 12 12 RX_CFG_OVR_PWRSF_14 13 13 ixPB1_RX_LANE14_SCI_STAT_OVRD_REG0 2 0x2207908 6 0 4294967295 RXPWR_14 0 2 ELECIDLEDETEN_14 3 3 RXPRESETHINT_14 4 6 ENABLEFOM_14 7 7 REQUESTFOM_14 8 8 RESPONSEMODE_14 9 9 ixPB1_RX_LANE15_CTRL_REG0 2 0x2207a00 4 0 4294967295 RX_BACKUP_15 0 7 RX_DBG_ANALOG_SEL_15 10 11 RX_TST_BSCAN_EN_15 12 12 RX_CFG_OVR_PWRSF_15 13 13 ixPB1_RX_LANE15_SCI_STAT_OVRD_REG0 2 0x2207a08 6 0 4294967295 RXPWR_15 0 2 ELECIDLEDETEN_15 3 3 RXPRESETHINT_15 4 6 ENABLEFOM_15 7 7 REQUESTFOM_15 8 8 RESPONSEMODE_15 9 9 ixPB1_TX_GLB_CTRL_REG0 2 0x2208000 12 0 4294967295 TX_DRV_DATA_ASRT_DLY_VAL 0 2 TX_DRV_DATA_DSRT_DLY_VAL 3 5 TX_CFG_RPTR_RST_VAL_GEN1 8 10 TX_CFG_RPTR_RST_VAL_GEN2 11 13 TX_CFG_RPTR_RST_VAL_GEN3 14 16 TX_STAGGER_CTRL 17 18 TX_DATA_CLK_GATING 19 19 TX_PRESET_TABLE_BYPASS 20 20 TX_COEFF_ROUND_EN 21 21 TX_COEFF_ROUND_DIR_VER 22 22 TX_DCLK_EN_LSX_ALWAYS_ON 23 23 TX_FRONTEND_PWRON_IN_OFF 24 24 ixPB1_TX_GLB_LANE_SKEW_CTRL 2 0x2208004 31 0 4294967295 TX_CFG_GROUPX1_EN_0 0 0 TX_CFG_GROUPX1_EN_1 1 1 TX_CFG_GROUPX1_EN_2 2 2 TX_CFG_GROUPX1_EN_3 3 3 TX_CFG_GROUPX1_EN_4 4 4 TX_CFG_GROUPX1_EN_5 5 5 TX_CFG_GROUPX1_EN_6 6 6 TX_CFG_GROUPX1_EN_7 7 7 TX_CFG_GROUPX1_EN_8 8 8 TX_CFG_GROUPX1_EN_9 9 9 TX_CFG_GROUPX1_EN_10 10 10 TX_CFG_GROUPX1_EN_11 11 11 TX_CFG_GROUPX1_EN_12 12 12 TX_CFG_GROUPX1_EN_13 13 13 TX_CFG_GROUPX1_EN_14 14 14 TX_CFG_GROUPX1_EN_15 15 15 TX_CFG_GROUPX2_EN_L0T1 16 16 TX_CFG_GROUPX2_EN_L2T3 17 17 TX_CFG_GROUPX2_EN_L4T5 18 18 TX_CFG_GROUPX2_EN_L6T7 19 19 TX_CFG_GROUPX2_EN_L8T9 20 20 TX_CFG_GROUPX2_EN_L10T11 21 21 TX_CFG_GROUPX2_EN_L12T13 22 22 TX_CFG_GROUPX2_EN_L14T15 23 23 TX_CFG_GROUPX4_EN_L0T3 24 24 TX_CFG_GROUPX4_EN_L4T7 25 25 TX_CFG_GROUPX4_EN_L8T11 26 26 TX_CFG_GROUPX4_EN_L12T15 27 27 TX_CFG_GROUPX8_EN_L0T7 28 28 TX_CFG_GROUPX8_EN_L8T15 29 29 TX_CFG_GROUPX16_EN_L0T15 30 30 ixPB1_TX_GLB_SCI_STAT_OVRD_REG0 2 0x2208010 16 0 4294967295 IGNR_TXPWR_SCI_UPDT_L0T3 0 0 IGNR_TXPWR_SCI_UPDT_L4T7 1 1 IGNR_TXPWR_SCI_UPDT_L8T11 2 2 IGNR_TXPWR_SCI_UPDT_L12T15 3 3 IGNR_INCOHERENTCK_SCI_UPDT_L0T3 4 4 IGNR_INCOHERENTCK_SCI_UPDT_L4T7 5 5 IGNR_INCOHERENTCK_SCI_UPDT_L8T11 6 6 IGNR_INCOHERENTCK_SCI_UPDT_L12T15 7 7 IGNR_COEFFICIENTID_SCI_UPDT_L0T3 8 8 IGNR_COEFFICIENTID_SCI_UPDT_L4T7 9 9 IGNR_COEFFICIENTID_SCI_UPDT_L8T11 10 10 IGNR_COEFFICIENTID_SCI_UPDT_L12T15 11 11 IGNR_COEFFICIENT_SCI_UPDT_L0T3 12 12 IGNR_COEFFICIENT_SCI_UPDT_L4T7 13 13 IGNR_COEFFICIENT_SCI_UPDT_L8T11 14 14 IGNR_COEFFICIENT_SCI_UPDT_L12T15 15 15 ixPB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0 2 0x2208014 32 0 4294967295 ACCEPT_ENTRY_0 0 0 ACCEPT_ENTRY_1 1 1 ACCEPT_ENTRY_2 2 2 ACCEPT_ENTRY_3 3 3 ACCEPT_ENTRY_4 4 4 ACCEPT_ENTRY_5 5 5 ACCEPT_ENTRY_6 6 6 ACCEPT_ENTRY_7 7 7 ACCEPT_ENTRY_8 8 8 ACCEPT_ENTRY_9 9 9 ACCEPT_ENTRY_10 10 10 ACCEPT_ENTRY_11 11 11 ACCEPT_ENTRY_12 12 12 ACCEPT_ENTRY_13 13 13 ACCEPT_ENTRY_14 14 14 ACCEPT_ENTRY_15 15 15 ACCEPT_ENTRY_16 16 16 ACCEPT_ENTRY_17 17 17 ACCEPT_ENTRY_18 18 18 ACCEPT_ENTRY_19 19 19 ACCEPT_ENTRY_20 20 20 ACCEPT_ENTRY_21 21 21 ACCEPT_ENTRY_22 22 22 ACCEPT_ENTRY_23 23 23 ACCEPT_ENTRY_24 24 24 ACCEPT_ENTRY_25 25 25 ACCEPT_ENTRY_26 26 26 ACCEPT_ENTRY_27 27 27 ACCEPT_ENTRY_28 28 28 ACCEPT_ENTRY_29 29 29 ACCEPT_ENTRY_30 30 30 ACCEPT_ENTRY_31 31 31 ixPB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1 2 0x2208018 32 0 4294967295 ACCEPT_ENTRY_32 0 0 ACCEPT_ENTRY_33 1 1 ACCEPT_ENTRY_34 2 2 ACCEPT_ENTRY_35 3 3 ACCEPT_ENTRY_36 4 4 ACCEPT_ENTRY_37 5 5 ACCEPT_ENTRY_38 6 6 ACCEPT_ENTRY_39 7 7 ACCEPT_ENTRY_40 8 8 ACCEPT_ENTRY_41 9 9 ACCEPT_ENTRY_42 10 10 ACCEPT_ENTRY_43 11 11 ACCEPT_ENTRY_44 12 12 ACCEPT_ENTRY_45 13 13 ACCEPT_ENTRY_46 14 14 ACCEPT_ENTRY_47 15 15 ACCEPT_ENTRY_48 16 16 ACCEPT_ENTRY_49 17 17 ACCEPT_ENTRY_50 18 18 ACCEPT_ENTRY_51 19 19 ACCEPT_ENTRY_52 20 20 ACCEPT_ENTRY_53 21 21 ACCEPT_ENTRY_54 22 22 ACCEPT_ENTRY_55 23 23 ACCEPT_ENTRY_56 24 24 ACCEPT_ENTRY_57 25 25 ACCEPT_ENTRY_58 26 26 ACCEPT_ENTRY_59 27 27 ACCEPT_ENTRY_60 28 28 ACCEPT_ENTRY_61 29 29 ACCEPT_ENTRY_62 30 30 ACCEPT_ENTRY_63 31 31 ixPB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2 2 0x220801c 32 0 4294967295 ACCEPT_ENTRY_64 0 0 ACCEPT_ENTRY_65 1 1 ACCEPT_ENTRY_66 2 2 ACCEPT_ENTRY_67 3 3 ACCEPT_ENTRY_68 4 4 ACCEPT_ENTRY_69 5 5 ACCEPT_ENTRY_70 6 6 ACCEPT_ENTRY_71 7 7 ACCEPT_ENTRY_72 8 8 ACCEPT_ENTRY_73 9 9 ACCEPT_ENTRY_74 10 10 ACCEPT_ENTRY_75 11 11 ACCEPT_ENTRY_76 12 12 ACCEPT_ENTRY_77 13 13 ACCEPT_ENTRY_78 14 14 ACCEPT_ENTRY_79 15 15 ACCEPT_ENTRY_80 16 16 ACCEPT_ENTRY_81 17 17 ACCEPT_ENTRY_82 18 18 ACCEPT_ENTRY_83 19 19 ACCEPT_ENTRY_84 20 20 ACCEPT_ENTRY_85 21 21 ACCEPT_ENTRY_86 22 22 ACCEPT_ENTRY_87 23 23 ACCEPT_ENTRY_88 24 24 ACCEPT_ENTRY_89 25 25 ACCEPT_ENTRY_90 26 26 ACCEPT_ENTRY_91 27 27 ACCEPT_ENTRY_92 28 28 ACCEPT_ENTRY_93 29 29 ACCEPT_ENTRY_94 30 30 ACCEPT_ENTRY_95 31 31 ixPB1_TX_GLB_COEFF_ACCEPT_TABLE_REG3 2 0x2208020 14 0 4294967295 ACCEPT_ENTRY_96 0 0 ACCEPT_ENTRY_97 1 1 ACCEPT_ENTRY_98 2 2 ACCEPT_ENTRY_99 3 3 ACCEPT_ENTRY_100 4 4 ACCEPT_ENTRY_101 5 5 ACCEPT_ENTRY_102 6 6 ACCEPT_ENTRY_103 7 7 ACCEPT_ENTRY_104 8 8 ACCEPT_ENTRY_105 9 9 ACCEPT_ENTRY_106 10 10 ACCEPT_ENTRY_107 11 11 ACCEPT_ENTRY_108 12 12 ACCEPT_ENTRY_109 13 13 ixPB1_TX_GLB_OVRD_REG0 2 0x2208030 12 0 4294967295 TX_CFG_DCLK_DIV_OVRD_VAL 0 2 TX_CFG_DCLK_DIV_OVRD_EN 3 3 TX_CFG_DRV0_EN_GEN1_OVRD_VAL 4 7 TX_CFG_DRV0_EN_OVRD_EN 8 8 TX_CFG_DRV0_TAP_SEL_GEN1_OVRD_VAL 9 12 TX_CFG_DRV0_TAP_SEL_OVRD_EN 13 13 TX_CFG_DRV1_EN_GEN1_OVRD_VAL 14 18 TX_CFG_DRV1_EN_OVRD_EN 19 19 TX_CFG_DRV1_TAP_SEL_GEN1_OVRD_VAL 20 24 TX_CFG_DRV1_TAP_SEL_OVRD_EN 25 25 TX_CFG_DRV2_EN_GEN1_OVRD_VAL 26 29 TX_CFG_DRV2_EN_OVRD_EN 30 30 ixPB1_TX_GLB_OVRD_REG1 2 0x2208034 20 0 4294967295 TX_CFG_DRV2_TAP_SEL_GEN1_OVRD_VAL 0 3 TX_CFG_DRV2_TAP_SEL_OVRD_EN 4 4 TX_CFG_DRVX_EN_GEN1_OVRD_VAL 5 5 TX_CFG_DRVX_EN_OVRD_EN 6 6 TX_CFG_DRVX_TAP_SEL_GEN1_OVRD_VAL 7 7 TX_CFG_DRVX_TAP_SEL_OVRD_EN 8 8 TX_CFG_PLLCLK_SEL_OVRD_VAL 9 9 TX_CFG_PLLCLK_SEL_OVRD_EN 10 10 TX_CFG_TCLK_DIV_OVRD_VAL 11 11 TX_CFG_TCLK_DIV_OVRD_EN 12 12 TX_CMDET_EN_OVRD_VAL 13 13 TX_CMDET_EN_OVRD_EN 14 14 TX_DATA_IN_OVRD_VAL 15 24 TX_DATA_IN_OVRD_EN 25 25 TX_RPTR_RSTN_OVRD_VAL 26 26 TX_RPTR_RSTN_OVRD_EN 27 27 TX_RXDET_EN_OVRD_VAL 28 28 TX_RXDET_EN_OVRD_EN 29 29 TX_WPTR_RSTN_OVRD_VAL 30 30 TX_WPTR_RSTN_OVRD_EN 31 31 ixPB1_TX_GLB_OVRD_REG2 2 0x2208038 16 0 4294967295 TX_WRITE_EN_OVRD_VAL 0 0 TX_WRITE_EN_OVRD_EN 1 1 TX_CFG_GROUPX1_EN_OVRD_VAL 2 2 TX_CFG_GROUPX1_EN_OVRD_EN 3 3 TX_CFG_GROUPX2_EN_OVRD_VAL 4 4 TX_CFG_GROUPX2_EN_OVRD_EN 5 5 TX_CFG_GROUPX4_EN_OVRD_VAL 6 6 TX_CFG_GROUPX4_EN_OVRD_EN 7 7 TX_CFG_GROUPX8_EN_OVRD_VAL 8 8 TX_CFG_GROUPX8_EN_OVRD_EN 9 9 TX_CFG_GROUPX16_EN_OVRD_VAL 10 10 TX_CFG_GROUPX16_EN_OVRD_EN 11 11 TX_CFG_DRV0_EN_GEN2_OVRD_VAL 12 15 TX_CFG_DRV0_TAP_SEL_GEN2_OVRD_VAL 16 19 TX_CFG_DRV1_EN_GEN2_OVRD_VAL 20 24 TX_CFG_DRV1_TAP_SEL_GEN2_OVRD_VAL 25 29 ixPB1_TX_GLB_OVRD_REG3 2 0x220803c 9 0 4294967295 TX_CFG_DRV2_EN_GEN2_OVRD_VAL 0 3 TX_CFG_DRV2_TAP_SEL_GEN2_OVRD_VAL 4 7 TX_CFG_DRVX_EN_GEN2_OVRD_VAL 8 8 TX_CFG_DRVX_TAP_SEL_GEN2_OVRD_VAL 9 9 TX_CFG_DRV0_EN_GEN3_OVRD_VAL 10 13 TX_CFG_DRV0_TAP_SEL_GEN3_OVRD_VAL 14 17 TX_CFG_DRV1_EN_GEN3_OVRD_VAL 18 22 TX_CFG_DRV1_TAP_SEL_GEN3_OVRD_VAL 23 27 TX_CFG_DRV2_EN_GEN3_OVRD_VAL 28 31 ixPB1_TX_GLB_OVRD_REG4 2 0x2208040 3 0 4294967295 TX_CFG_DRV2_TAP_SEL_GEN3_OVRD_VAL 0 3 TX_CFG_DRVX_EN_GEN3_OVRD_VAL 4 4 TX_CFG_DRVX_TAP_SEL_GEN3_OVRD_VAL 5 5 ixPB1_TX_LANE0_CTRL_REG0 2 0x2208440 4 0 4294967295 TX_CFG_DISPCLK_MODE_0 0 0 TX_CFG_INV_DATA_0 1 1 TX_CFG_SWING_BOOST_EN_0 2 2 TX_DBG_PRBS_EN_0 3 3 ixPB1_TX_LANE0_OVRD_REG0 2 0x2208444 8 0 4294967295 TX_DCLK_EN_OVRD_VAL_0 0 0 TX_DCLK_EN_OVRD_EN_0 1 1 TX_DRV_DATA_EN_OVRD_VAL_0 2 2 TX_DRV_DATA_EN_OVRD_EN_0 3 3 TX_DRV_PWRON_OVRD_VAL_0 4 4 TX_DRV_PWRON_OVRD_EN_0 5 5 TX_FRONTEND_PWRON_OVRD_VAL_0 6 6 TX_FRONTEND_PWRON_OVRD_EN_0 7 7 ixPB1_TX_LANE0_SCI_STAT_OVRD_REG0 2 0x2208448 6 0 4294967295 TXPWR_0 0 2 INCOHERENTCK_0 3 3 TXMARG_0 4 6 DEEMPH_0 7 7 COEFFICIENTID_0 8 9 COEFFICIENT_0 10 15 ixPB1_TX_LANE1_CTRL_REG0 2 0x2208480 4 0 4294967295 TX_CFG_DISPCLK_MODE_1 0 0 TX_CFG_INV_DATA_1 1 1 TX_CFG_SWING_BOOST_EN_1 2 2 TX_DBG_PRBS_EN_1 3 3 ixPB1_TX_LANE1_OVRD_REG0 2 0x2208484 8 0 4294967295 TX_DCLK_EN_OVRD_VAL_1 0 0 TX_DCLK_EN_OVRD_EN_1 1 1 TX_DRV_DATA_EN_OVRD_VAL_1 2 2 TX_DRV_DATA_EN_OVRD_EN_1 3 3 TX_DRV_PWRON_OVRD_VAL_1 4 4 TX_DRV_PWRON_OVRD_EN_1 5 5 TX_FRONTEND_PWRON_OVRD_VAL_1 6 6 TX_FRONTEND_PWRON_OVRD_EN_1 7 7 ixPB1_TX_LANE1_SCI_STAT_OVRD_REG0 2 0x2208488 6 0 4294967295 TXPWR_1 0 2 INCOHERENTCK_1 3 3 TXMARG_1 4 6 DEEMPH_1 7 7 COEFFICIENTID_1 8 9 COEFFICIENT_1 10 15 ixPB1_TX_LANE2_CTRL_REG0 2 0x2208500 4 0 4294967295 TX_CFG_DISPCLK_MODE_2 0 0 TX_CFG_INV_DATA_2 1 1 TX_CFG_SWING_BOOST_EN_2 2 2 TX_DBG_PRBS_EN_2 3 3 ixPB1_TX_LANE2_OVRD_REG0 2 0x2208504 8 0 4294967295 TX_DCLK_EN_OVRD_VAL_2 0 0 TX_DCLK_EN_OVRD_EN_2 1 1 TX_DRV_DATA_EN_OVRD_VAL_2 2 2 TX_DRV_DATA_EN_OVRD_EN_2 3 3 TX_DRV_PWRON_OVRD_VAL_2 4 4 TX_DRV_PWRON_OVRD_EN_2 5 5 TX_FRONTEND_PWRON_OVRD_VAL_2 6 6 TX_FRONTEND_PWRON_OVRD_EN_2 7 7 ixPB1_TX_LANE2_SCI_STAT_OVRD_REG0 2 0x2208508 6 0 4294967295 TXPWR_2 0 2 INCOHERENTCK_2 3 3 TXMARG_2 4 6 DEEMPH_2 7 7 COEFFICIENTID_2 8 9 COEFFICIENT_2 10 15 ixPB1_TX_LANE3_CTRL_REG0 2 0x2208600 4 0 4294967295 TX_CFG_DISPCLK_MODE_3 0 0 TX_CFG_INV_DATA_3 1 1 TX_CFG_SWING_BOOST_EN_3 2 2 TX_DBG_PRBS_EN_3 3 3 ixPB1_TX_LANE3_OVRD_REG0 2 0x2208604 8 0 4294967295 TX_DCLK_EN_OVRD_VAL_3 0 0 TX_DCLK_EN_OVRD_EN_3 1 1 TX_DRV_DATA_EN_OVRD_VAL_3 2 2 TX_DRV_DATA_EN_OVRD_EN_3 3 3 TX_DRV_PWRON_OVRD_VAL_3 4 4 TX_DRV_PWRON_OVRD_EN_3 5 5 TX_FRONTEND_PWRON_OVRD_VAL_3 6 6 TX_FRONTEND_PWRON_OVRD_EN_3 7 7 ixPB1_TX_LANE3_SCI_STAT_OVRD_REG0 2 0x2208608 6 0 4294967295 TXPWR_3 0 2 INCOHERENTCK_3 3 3 TXMARG_3 4 6 DEEMPH_3 7 7 COEFFICIENTID_3 8 9 COEFFICIENT_3 10 15 ixPB1_TX_LANE4_CTRL_REG0 2 0x2208840 4 0 4294967295 TX_CFG_DISPCLK_MODE_4 0 0 TX_CFG_INV_DATA_4 1 1 TX_CFG_SWING_BOOST_EN_4 2 2 TX_DBG_PRBS_EN_4 3 3 ixPB1_TX_LANE4_OVRD_REG0 2 0x2208844 8 0 4294967295 TX_DCLK_EN_OVRD_VAL_4 0 0 TX_DCLK_EN_OVRD_EN_4 1 1 TX_DRV_DATA_EN_OVRD_VAL_4 2 2 TX_DRV_DATA_EN_OVRD_EN_4 3 3 TX_DRV_PWRON_OVRD_VAL_4 4 4 TX_DRV_PWRON_OVRD_EN_4 5 5 TX_FRONTEND_PWRON_OVRD_VAL_4 6 6 TX_FRONTEND_PWRON_OVRD_EN_4 7 7 ixPB1_TX_LANE4_SCI_STAT_OVRD_REG0 2 0x2208848 6 0 4294967295 TXPWR_4 0 2 INCOHERENTCK_4 3 3 TXMARG_4 4 6 DEEMPH_4 7 7 COEFFICIENTID_4 8 9 COEFFICIENT_4 10 15 ixPB1_TX_LANE5_CTRL_REG0 2 0x2208880 4 0 4294967295 TX_CFG_DISPCLK_MODE_5 0 0 TX_CFG_INV_DATA_5 1 1 TX_CFG_SWING_BOOST_EN_5 2 2 TX_DBG_PRBS_EN_5 3 3 ixPB1_TX_LANE5_OVRD_REG0 2 0x2208884 8 0 4294967295 TX_DCLK_EN_OVRD_VAL_5 0 0 TX_DCLK_EN_OVRD_EN_5 1 1 TX_DRV_DATA_EN_OVRD_VAL_5 2 2 TX_DRV_DATA_EN_OVRD_EN_5 3 3 TX_DRV_PWRON_OVRD_VAL_5 4 4 TX_DRV_PWRON_OVRD_EN_5 5 5 TX_FRONTEND_PWRON_OVRD_VAL_5 6 6 TX_FRONTEND_PWRON_OVRD_EN_5 7 7 ixPB1_TX_LANE5_SCI_STAT_OVRD_REG0 2 0x2208888 6 0 4294967295 TXPWR_5 0 2 INCOHERENTCK_5 3 3 TXMARG_5 4 6 DEEMPH_5 7 7 COEFFICIENTID_5 8 9 COEFFICIENT_5 10 15 ixPB1_TX_LANE6_CTRL_REG0 2 0x2208900 4 0 4294967295 TX_CFG_DISPCLK_MODE_6 0 0 TX_CFG_INV_DATA_6 1 1 TX_CFG_SWING_BOOST_EN_6 2 2 TX_DBG_PRBS_EN_6 3 3 ixPB1_TX_LANE6_OVRD_REG0 2 0x2208904 8 0 4294967295 TX_DCLK_EN_OVRD_VAL_6 0 0 TX_DCLK_EN_OVRD_EN_6 1 1 TX_DRV_DATA_EN_OVRD_VAL_6 2 2 TX_DRV_DATA_EN_OVRD_EN_6 3 3 TX_DRV_PWRON_OVRD_VAL_6 4 4 TX_DRV_PWRON_OVRD_EN_6 5 5 TX_FRONTEND_PWRON_OVRD_VAL_6 6 6 TX_FRONTEND_PWRON_OVRD_EN_6 7 7 ixPB1_TX_LANE6_SCI_STAT_OVRD_REG0 2 0x2208908 6 0 4294967295 TXPWR_6 0 2 INCOHERENTCK_6 3 3 TXMARG_6 4 6 DEEMPH_6 7 7 COEFFICIENTID_6 8 9 COEFFICIENT_6 10 15 ixPB1_TX_LANE7_CTRL_REG0 2 0x2208a00 4 0 4294967295 TX_CFG_DISPCLK_MODE_7 0 0 TX_CFG_INV_DATA_7 1 1 TX_CFG_SWING_BOOST_EN_7 2 2 TX_DBG_PRBS_EN_7 3 3 ixPB1_TX_LANE7_OVRD_REG0 2 0x2208a04 8 0 4294967295 TX_DCLK_EN_OVRD_VAL_7 0 0 TX_DCLK_EN_OVRD_EN_7 1 1 TX_DRV_DATA_EN_OVRD_VAL_7 2 2 TX_DRV_DATA_EN_OVRD_EN_7 3 3 TX_DRV_PWRON_OVRD_VAL_7 4 4 TX_DRV_PWRON_OVRD_EN_7 5 5 TX_FRONTEND_PWRON_OVRD_VAL_7 6 6 TX_FRONTEND_PWRON_OVRD_EN_7 7 7 ixPB1_TX_LANE7_SCI_STAT_OVRD_REG0 2 0x2208a08 6 0 4294967295 TXPWR_7 0 2 INCOHERENTCK_7 3 3 TXMARG_7 4 6 DEEMPH_7 7 7 COEFFICIENTID_7 8 9 COEFFICIENT_7 10 15 ixPB1_TX_LANE8_CTRL_REG0 2 0x2209440 4 0 4294967295 TX_CFG_DISPCLK_MODE_8 0 0 TX_CFG_INV_DATA_8 1 1 TX_CFG_SWING_BOOST_EN_8 2 2 TX_DBG_PRBS_EN_8 3 3 ixPB1_TX_LANE8_OVRD_REG0 2 0x2209444 8 0 4294967295 TX_DCLK_EN_OVRD_VAL_8 0 0 TX_DCLK_EN_OVRD_EN_8 1 1 TX_DRV_DATA_EN_OVRD_VAL_8 2 2 TX_DRV_DATA_EN_OVRD_EN_8 3 3 TX_DRV_PWRON_OVRD_VAL_8 4 4 TX_DRV_PWRON_OVRD_EN_8 5 5 TX_FRONTEND_PWRON_OVRD_VAL_8 6 6 TX_FRONTEND_PWRON_OVRD_EN_8 7 7 ixPB1_TX_LANE8_SCI_STAT_OVRD_REG0 2 0x2209448 6 0 4294967295 TXPWR_8 0 2 INCOHERENTCK_8 3 3 TXMARG_8 4 6 DEEMPH_8 7 7 COEFFICIENTID_8 8 9 COEFFICIENT_8 10 15 ixPB1_TX_LANE9_CTRL_REG0 2 0x2209480 4 0 4294967295 TX_CFG_DISPCLK_MODE_9 0 0 TX_CFG_INV_DATA_9 1 1 TX_CFG_SWING_BOOST_EN_9 2 2 TX_DBG_PRBS_EN_9 3 3 ixPB1_TX_LANE9_OVRD_REG0 2 0x2209484 8 0 4294967295 TX_DCLK_EN_OVRD_VAL_9 0 0 TX_DCLK_EN_OVRD_EN_9 1 1 TX_DRV_DATA_EN_OVRD_VAL_9 2 2 TX_DRV_DATA_EN_OVRD_EN_9 3 3 TX_DRV_PWRON_OVRD_VAL_9 4 4 TX_DRV_PWRON_OVRD_EN_9 5 5 TX_FRONTEND_PWRON_OVRD_VAL_9 6 6 TX_FRONTEND_PWRON_OVRD_EN_9 7 7 ixPB1_TX_LANE9_SCI_STAT_OVRD_REG0 2 0x2209488 6 0 4294967295 TXPWR_9 0 2 INCOHERENTCK_9 3 3 TXMARG_9 4 6 DEEMPH_9 7 7 COEFFICIENTID_9 8 9 COEFFICIENT_9 10 15 ixPB1_TX_LANE10_CTRL_REG0 2 0x2209500 4 0 4294967295 TX_CFG_DISPCLK_MODE_10 0 0 TX_CFG_INV_DATA_10 1 1 TX_CFG_SWING_BOOST_EN_10 2 2 TX_DBG_PRBS_EN_10 3 3 ixPB1_TX_LANE10_OVRD_REG0 2 0x2209504 8 0 4294967295 TX_DCLK_EN_OVRD_VAL_10 0 0 TX_DCLK_EN_OVRD_EN_10 1 1 TX_DRV_DATA_EN_OVRD_VAL_10 2 2 TX_DRV_DATA_EN_OVRD_EN_10 3 3 TX_DRV_PWRON_OVRD_VAL_10 4 4 TX_DRV_PWRON_OVRD_EN_10 5 5 TX_FRONTEND_PWRON_OVRD_VAL_10 6 6 TX_FRONTEND_PWRON_OVRD_EN_10 7 7 ixPB1_TX_LANE10_SCI_STAT_OVRD_REG0 2 0x2209508 6 0 4294967295 TXPWR_10 0 2 INCOHERENTCK_10 3 3 TXMARG_10 4 6 DEEMPH_10 7 7 COEFFICIENTID_10 8 9 COEFFICIENT_10 10 15 ixPB1_TX_LANE11_CTRL_REG0 2 0x2209600 4 0 4294967295 TX_CFG_DISPCLK_MODE_11 0 0 TX_CFG_INV_DATA_11 1 1 TX_CFG_SWING_BOOST_EN_11 2 2 TX_DBG_PRBS_EN_11 3 3 ixPB1_TX_LANE11_OVRD_REG0 2 0x2209604 8 0 4294967295 TX_DCLK_EN_OVRD_VAL_11 0 0 TX_DCLK_EN_OVRD_EN_11 1 1 TX_DRV_DATA_EN_OVRD_VAL_11 2 2 TX_DRV_DATA_EN_OVRD_EN_11 3 3 TX_DRV_PWRON_OVRD_VAL_11 4 4 TX_DRV_PWRON_OVRD_EN_11 5 5 TX_FRONTEND_PWRON_OVRD_VAL_11 6 6 TX_FRONTEND_PWRON_OVRD_EN_11 7 7 ixPB1_TX_LANE11_SCI_STAT_OVRD_REG0 2 0x2209608 6 0 4294967295 TXPWR_11 0 2 INCOHERENTCK_11 3 3 TXMARG_11 4 6 DEEMPH_11 7 7 COEFFICIENTID_11 8 9 COEFFICIENT_11 10 15 ixPB1_TX_LANE12_CTRL_REG0 2 0x2209840 4 0 4294967295 TX_CFG_DISPCLK_MODE_12 0 0 TX_CFG_INV_DATA_12 1 1 TX_CFG_SWING_BOOST_EN_12 2 2 TX_DBG_PRBS_EN_12 3 3 ixPB1_TX_LANE12_OVRD_REG0 2 0x2209844 8 0 4294967295 TX_DCLK_EN_OVRD_VAL_12 0 0 TX_DCLK_EN_OVRD_EN_12 1 1 TX_DRV_DATA_EN_OVRD_VAL_12 2 2 TX_DRV_DATA_EN_OVRD_EN_12 3 3 TX_DRV_PWRON_OVRD_VAL_12 4 4 TX_DRV_PWRON_OVRD_EN_12 5 5 TX_FRONTEND_PWRON_OVRD_VAL_12 6 6 TX_FRONTEND_PWRON_OVRD_EN_12 7 7 ixPB1_TX_LANE12_SCI_STAT_OVRD_REG0 2 0x2209848 6 0 4294967295 TXPWR_12 0 2 INCOHERENTCK_12 3 3 TXMARG_12 4 6 DEEMPH_12 7 7 COEFFICIENTID_12 8 9 COEFFICIENT_12 10 15 ixPB1_TX_LANE13_CTRL_REG0 2 0x2209880 4 0 4294967295 TX_CFG_DISPCLK_MODE_13 0 0 TX_CFG_INV_DATA_13 1 1 TX_CFG_SWING_BOOST_EN_13 2 2 TX_DBG_PRBS_EN_13 3 3 ixPB1_TX_LANE13_OVRD_REG0 2 0x2209884 8 0 4294967295 TX_DCLK_EN_OVRD_VAL_13 0 0 TX_DCLK_EN_OVRD_EN_13 1 1 TX_DRV_DATA_EN_OVRD_VAL_13 2 2 TX_DRV_DATA_EN_OVRD_EN_13 3 3 TX_DRV_PWRON_OVRD_VAL_13 4 4 TX_DRV_PWRON_OVRD_EN_13 5 5 TX_FRONTEND_PWRON_OVRD_VAL_13 6 6 TX_FRONTEND_PWRON_OVRD_EN_13 7 7 ixPB1_TX_LANE13_SCI_STAT_OVRD_REG0 2 0x2209888 6 0 4294967295 TXPWR_13 0 2 INCOHERENTCK_13 3 3 TXMARG_13 4 6 DEEMPH_13 7 7 COEFFICIENTID_13 8 9 COEFFICIENT_13 10 15 ixPB1_TX_LANE14_CTRL_REG0 2 0x2209900 4 0 4294967295 TX_CFG_DISPCLK_MODE_14 0 0 TX_CFG_INV_DATA_14 1 1 TX_CFG_SWING_BOOST_EN_14 2 2 TX_DBG_PRBS_EN_14 3 3 ixPB1_TX_LANE14_OVRD_REG0 2 0x2209904 8 0 4294967295 TX_DCLK_EN_OVRD_VAL_14 0 0 TX_DCLK_EN_OVRD_EN_14 1 1 TX_DRV_DATA_EN_OVRD_VAL_14 2 2 TX_DRV_DATA_EN_OVRD_EN_14 3 3 TX_DRV_PWRON_OVRD_VAL_14 4 4 TX_DRV_PWRON_OVRD_EN_14 5 5 TX_FRONTEND_PWRON_OVRD_VAL_14 6 6 TX_FRONTEND_PWRON_OVRD_EN_14 7 7 ixPB1_TX_LANE14_SCI_STAT_OVRD_REG0 2 0x2209908 6 0 4294967295 TXPWR_14 0 2 INCOHERENTCK_14 3 3 TXMARG_14 4 6 DEEMPH_14 7 7 COEFFICIENTID_14 8 9 COEFFICIENT_14 10 15 ixPB1_TX_LANE15_CTRL_REG0 2 0x2209a00 4 0 4294967295 TX_CFG_DISPCLK_MODE_15 0 0 TX_CFG_INV_DATA_15 1 1 TX_CFG_SWING_BOOST_EN_15 2 2 TX_DBG_PRBS_EN_15 3 3 ixPB1_TX_LANE15_OVRD_REG0 2 0x2209a04 8 0 4294967295 TX_DCLK_EN_OVRD_VAL_15 0 0 TX_DCLK_EN_OVRD_EN_15 1 1 TX_DRV_DATA_EN_OVRD_VAL_15 2 2 TX_DRV_DATA_EN_OVRD_EN_15 3 3 TX_DRV_PWRON_OVRD_VAL_15 4 4 TX_DRV_PWRON_OVRD_EN_15 5 5 TX_FRONTEND_PWRON_OVRD_VAL_15 6 6 TX_FRONTEND_PWRON_OVRD_EN_15 7 7 ixPB1_TX_LANE15_SCI_STAT_OVRD_REG0 2 0x2209a08 6 0 4294967295 TXPWR_15 0 2 INCOHERENTCK_15 3 3 TXMARG_15 4 6 DEEMPH_15 7 7 COEFFICIENTID_15 8 9 COEFFICIENT_15 10 15 ixPB0_PIF_SCRATCH 2 0x1100001 1 0 4294967295 PIF_SCRATCH 0 31 ixPB0_PIF_HW_DEBUG 2 0x1100002 16 0 4294967295 PB0_PIF_HW_00_DEBUG 0 0 PB0_PIF_HW_01_DEBUG 1 1 PB0_PIF_HW_02_DEBUG 2 2 PB0_PIF_HW_03_DEBUG 3 3 PB0_PIF_HW_04_DEBUG 4 4 PB0_PIF_HW_05_DEBUG 5 5 PB0_PIF_HW_06_DEBUG 6 6 PB0_PIF_HW_07_DEBUG 7 7 PB0_PIF_HW_08_DEBUG 8 8 PB0_PIF_HW_09_DEBUG 9 9 PB0_PIF_HW_10_DEBUG 10 10 PB0_PIF_HW_11_DEBUG 11 11 PB0_PIF_HW_12_DEBUG 12 12 PB0_PIF_HW_13_DEBUG 13 13 PB0_PIF_HW_14_DEBUG 14 14 PB0_PIF_HW_15_DEBUG 15 15 ixPB0_PIF_PRG6 2 0x1100003 1 0 4294967295 PRG_SPEEDCHANGE_STEP4_DELAY 0 17 ixPB0_PIF_PRG7 2 0x1100004 1 0 4294967295 PRG_SPEEDCHANGE_STEP4_FIRSTGEN3_DELAY 0 17 ixPB0_PIF_CNTL 2 0x1100010 24 0 4294967295 SERIAL_CFG_ENABLE 0 0 DA_FIFO_RESET_0 1 1 PHY_CR_EN_MODE 2 2 PHYCMD_CR_EN_MODE 3 3 EI_DET_CYCLE_MODE 4 4 DA_FIFO_RESET_1 5 5 RXDETECT_FIFO_RESET_MODE 6 6 RXDETECT_TX_PWR_MODE 7 7 DIVINIT_MODE 8 8 DA_FIFO_RESET_2 9 9 PLL_BINDING_ENABLE 10 10 SC_CALIB_DONE_CNTL 11 11 DIVINIT_ENABLE 12 12 DA_FIFO_RESET_3 13 13 PLL0_IN_GEN3_MODE 14 14 FORCE_TxFreqEquZeroinDTM_EN 15 15 TXGND_TIME 16 16 LS2_EXIT_TIME 17 19 EI_CYCLE_OFF_TIME 20 22 EXIT_L0S_INIT_DIS 23 23 RXEN_GATER 24 27 EXTEND_WAIT_FOR_RAMPUP 28 28 IGNORE_TxDataValid_EP_DIS 29 29 PHYRESPONSEMODE_ON_RXDET_EN 30 30 ixPB0_PIF_PAIRING 2 0x1100011 16 0 4294967295 X2_LANE_1_0 0 0 X2_LANE_3_2 1 1 X2_LANE_5_4 2 2 X2_LANE_7_6 3 3 X2_LANE_9_8 4 4 X2_LANE_11_10 5 5 X2_LANE_13_12 6 6 X2_LANE_15_14 7 7 X4_LANE_3_0 8 8 X4_LANE_7_4 9 9 X4_LANE_11_8 10 10 X4_LANE_15_12 11 11 X8_LANE_7_0 16 16 X8_LANE_15_8 17 17 X16_LANE_15_0 20 20 MULTI_PIF 25 25 ixPB0_PIF_PWRDOWN_0 2 0x1100012 9 0 4294967295 TX_POWER_STATE_IN_TXS2_0 0 2 FORCE_RXEN_IN_L0s_0 3 3 RX_POWER_STATE_IN_RXS2_0 4 6 PLL_POWER_STATE_IN_TXS2_0 7 9 PLL_POWER_STATE_IN_OFF_0 10 12 TX2P5CLK_CLOCK_GATING_EN_0 16 16 PLL_RAMP_UP_TIME_0 24 26 PLLPWR_OVERRIDE_EN_0 28 28 PLLPWR_OVERRIDE_VAL_0 29 31 ixPB0_PIF_PWRDOWN_1 2 0x1100013 9 0 4294967295 TX_POWER_STATE_IN_TXS2_1 0 2 FORCE_RXEN_IN_L0s_1 3 3 RX_POWER_STATE_IN_RXS2_1 4 6 PLL_POWER_STATE_IN_TXS2_1 7 9 PLL_POWER_STATE_IN_OFF_1 10 12 TX2P5CLK_CLOCK_GATING_EN_1 16 16 PLL_RAMP_UP_TIME_1 24 26 PLLPWR_OVERRIDE_EN_1 28 28 PLLPWR_OVERRIDE_VAL_1 29 31 ixPB0_PIF_CNTL2 2 0x1100014 29 0 4294967295 RXDETECT_PRG_EN 0 0 RXDETECT_SAMPL_TIME 1 2 PLL_RAMP_UP_TIME_PRG_EN 3 3 LS2_EXIT_TIME_PRG_EN 4 4 SERVICE2_STEP4_DELAY_PRG_EN 5 5 SERVICE3_STEP4_DELAY_PRG_EN 6 6 RXDETECT_OVERRIDE_EN 7 7 RXDETECT_OVERRIDE_VAL_0 8 8 RXDETECT_OVERRIDE_VAL_1 9 9 RXDETECT_OVERRIDE_VAL_2 10 10 RXDETECT_OVERRIDE_VAL_3 11 11 RXDETECT_OVERRIDE_VAL_4 12 12 RXDETECT_OVERRIDE_VAL_5 13 13 RXDETECT_OVERRIDE_VAL_6 14 14 RXDETECT_OVERRIDE_VAL_7 15 15 RXDETECT_OVERRIDE_VAL_8 16 16 RXDETECT_OVERRIDE_VAL_9 17 17 RXDETECT_OVERRIDE_VAL_10 18 18 RXDETECT_OVERRIDE_VAL_11 19 19 RXDETECT_OVERRIDE_VAL_12 20 20 RXDETECT_OVERRIDE_VAL_13 21 21 RXDETECT_OVERRIDE_VAL_14 22 22 RXDETECT_OVERRIDE_VAL_15 23 23 RXPHYSTATUS_DELAY 24 26 RX_STAGGERING_MODE 27 27 SPEEDCHANGE_STEP2_DELAY_PRG_EN 28 28 RX_STAGGERING_DISABLE 29 29 PLL1_ALWAYS_ON_EN 30 30 SPEEDCHANGE_STEP4_DELAY_FORCE_LONG_EN 31 31 ixPB0_PIF_TXPHYSTATUS 2 0x1100015 16 0 4294967295 TXPHYSTATUS_0 0 0 TXPHYSTATUS_1 1 1 TXPHYSTATUS_2 2 2 TXPHYSTATUS_3 3 3 TXPHYSTATUS_4 4 4 TXPHYSTATUS_5 5 5 TXPHYSTATUS_6 6 6 TXPHYSTATUS_7 7 7 TXPHYSTATUS_8 8 8 TXPHYSTATUS_9 9 9 TXPHYSTATUS_10 10 10 TXPHYSTATUS_11 11 11 TXPHYSTATUS_12 12 12 TXPHYSTATUS_13 13 13 TXPHYSTATUS_14 14 14 TXPHYSTATUS_15 15 15 ixPB0_PIF_SC_CTL 2 0x1100016 31 0 4294967295 SC_CALIBRATION 0 0 SC_RXDETECT 1 1 SC_EXIT_L1_TO_L0S 2 2 SC_EXIT_L1_TO_L0 3 3 SC_ENTER_L1_FROM_L0S 4 4 SC_ENTER_L1_FROM_L0 5 5 SC_SPEED_CHANGE 6 6 SC_PHASE_1 8 8 SC_PHASE_2 9 9 SC_PHASE_3 10 10 SC_PHASE_4 11 11 SC_PHASE_5 12 12 SC_PHASE_6 13 13 SC_PHASE_7 14 14 SC_PHASE_8 15 15 SC_LANE_0_RESUME 16 16 SC_LANE_1_RESUME 17 17 SC_LANE_2_RESUME 18 18 SC_LANE_3_RESUME 19 19 SC_LANE_4_RESUME 20 20 SC_LANE_5_RESUME 21 21 SC_LANE_6_RESUME 22 22 SC_LANE_7_RESUME 23 23 SC_LANE_8_RESUME 24 24 SC_LANE_9_RESUME 25 25 SC_LANE_10_RESUME 26 26 SC_LANE_11_RESUME 27 27 SC_LANE_12_RESUME 28 28 SC_LANE_13_RESUME 29 29 SC_LANE_14_RESUME 30 30 SC_LANE_15_RESUME 31 31 ixPB0_PIF_PWRDOWN_2 2 0x1100017 9 0 4294967295 TX_POWER_STATE_IN_TXS2_2 0 2 FORCE_RXEN_IN_L0s_2 3 3 RX_POWER_STATE_IN_RXS2_2 4 6 PLL_POWER_STATE_IN_TXS2_2 7 9 PLL_POWER_STATE_IN_OFF_2 10 12 TX2P5CLK_CLOCK_GATING_EN_2 16 16 PLL_RAMP_UP_TIME_2 24 26 PLLPWR_OVERRIDE_EN_2 28 28 PLLPWR_OVERRIDE_VAL_2 29 31 ixPB0_PIF_PWRDOWN_3 2 0x1100018 9 0 4294967295 TX_POWER_STATE_IN_TXS2_3 0 2 FORCE_RXEN_IN_L0s_3 3 3 RX_POWER_STATE_IN_RXS2_3 4 6 PLL_POWER_STATE_IN_TXS2_3 7 9 PLL_POWER_STATE_IN_OFF_3 10 12 TX2P5CLK_CLOCK_GATING_EN_3 16 16 PLL_RAMP_UP_TIME_3 24 26 PLLPWR_OVERRIDE_EN_3 28 28 PLLPWR_OVERRIDE_VAL_3 29 31 ixPB0_PIF_SC_CTL2 2 0x1100019 16 0 4294967295 SERIAL_CFG_PERLANE_DISABLE_0 0 0 SERIAL_CFG_PERLANE_DISABLE_1 1 1 SERIAL_CFG_PERLANE_DISABLE_2 2 2 SERIAL_CFG_PERLANE_DISABLE_3 3 3 SERIAL_CFG_PERLANE_DISABLE_4 4 4 SERIAL_CFG_PERLANE_DISABLE_5 5 5 SERIAL_CFG_PERLANE_DISABLE_6 6 6 SERIAL_CFG_PERLANE_DISABLE_7 7 7 SERIAL_CFG_PERLANE_DISABLE_8 8 8 SERIAL_CFG_PERLANE_DISABLE_9 9 9 SERIAL_CFG_PERLANE_DISABLE_10 10 10 SERIAL_CFG_PERLANE_DISABLE_11 11 11 SERIAL_CFG_PERLANE_DISABLE_12 12 12 SERIAL_CFG_PERLANE_DISABLE_13 13 13 SERIAL_CFG_PERLANE_DISABLE_14 14 14 SERIAL_CFG_PERLANE_DISABLE_15 15 15 ixPB0_PIF_PRG0 2 0x110001a 1 0 4294967295 PRG_RXDETECT_SAMPL_TIME 0 17 ixPB0_PIF_PRG1 2 0x110001b 1 0 4294967295 PRG_PLL_RAMP_UP_TIME 0 17 ixPB0_PIF_PRG2 2 0x110001c 1 0 4294967295 PRG_SERVICE2_STEP4_DELAY 0 17 ixPB0_PIF_PRG3 2 0x110001d 1 0 4294967295 PRG_SERVICE3_STEP4_DELAY 0 17 ixPB0_PIF_PRG4 2 0x110001e 1 0 4294967295 PRG_SPEEDCHANGE_STEP2_DELAY 0 17 ixPB0_PIF_PRG5 2 0x110001f 1 0 4294967295 PRG_LS2_EXIT_TIME 0 17 ixPB0_PIF_PDNB_OVERRIDE_0 2 0x1100020 10 0 4294967295 TX_PDNB_OVERRIDE_EN_0 0 0 TX_PDNB_OVERRIDE_VAL_0 1 3 RX_PDNB_OVERRIDE_EN_0 4 4 RX_PDNB_OVERRIDE_VAL_0 5 7 RXEN_OVERRIDE_EN_0 8 8 RXEN_OVERRIDE_VAL_0 9 9 TXPWR_OVERRIDE_EN_0 10 10 TXPWR_OVERRIDE_VAL_0 11 13 RXPWR_OVERRIDE_EN_0 14 14 RXPWR_OVERRIDE_VAL_0 15 17 ixPB0_PIF_PDNB_OVERRIDE_1 2 0x1100021 10 0 4294967295 TX_PDNB_OVERRIDE_EN_1 0 0 TX_PDNB_OVERRIDE_VAL_1 1 3 RX_PDNB_OVERRIDE_EN_1 4 4 RX_PDNB_OVERRIDE_VAL_1 5 7 RXEN_OVERRIDE_EN_1 8 8 RXEN_OVERRIDE_VAL_1 9 9 TXPWR_OVERRIDE_EN_1 10 10 TXPWR_OVERRIDE_VAL_1 11 13 RXPWR_OVERRIDE_EN_1 14 14 RXPWR_OVERRIDE_VAL_1 15 17 ixPB0_PIF_PDNB_OVERRIDE_2 2 0x1100022 10 0 4294967295 TX_PDNB_OVERRIDE_EN_2 0 0 TX_PDNB_OVERRIDE_VAL_2 1 3 RX_PDNB_OVERRIDE_EN_2 4 4 RX_PDNB_OVERRIDE_VAL_2 5 7 RXEN_OVERRIDE_EN_2 8 8 RXEN_OVERRIDE_VAL_2 9 9 TXPWR_OVERRIDE_EN_2 10 10 TXPWR_OVERRIDE_VAL_2 11 13 RXPWR_OVERRIDE_EN_2 14 14 RXPWR_OVERRIDE_VAL_2 15 17 ixPB0_PIF_PDNB_OVERRIDE_3 2 0x1100023 10 0 4294967295 TX_PDNB_OVERRIDE_EN_3 0 0 TX_PDNB_OVERRIDE_VAL_3 1 3 RX_PDNB_OVERRIDE_EN_3 4 4 RX_PDNB_OVERRIDE_VAL_3 5 7 RXEN_OVERRIDE_EN_3 8 8 RXEN_OVERRIDE_VAL_3 9 9 TXPWR_OVERRIDE_EN_3 10 10 TXPWR_OVERRIDE_VAL_3 11 13 RXPWR_OVERRIDE_EN_3 14 14 RXPWR_OVERRIDE_VAL_3 15 17 ixPB0_PIF_PDNB_OVERRIDE_4 2 0x1100024 10 0 4294967295 TX_PDNB_OVERRIDE_EN_4 0 0 TX_PDNB_OVERRIDE_VAL_4 1 3 RX_PDNB_OVERRIDE_EN_4 4 4 RX_PDNB_OVERRIDE_VAL_4 5 7 RXEN_OVERRIDE_EN_4 8 8 RXEN_OVERRIDE_VAL_4 9 9 TXPWR_OVERRIDE_EN_4 10 10 TXPWR_OVERRIDE_VAL_4 11 13 RXPWR_OVERRIDE_EN_4 14 14 RXPWR_OVERRIDE_VAL_4 15 17 ixPB0_PIF_PDNB_OVERRIDE_5 2 0x1100025 10 0 4294967295 TX_PDNB_OVERRIDE_EN_5 0 0 TX_PDNB_OVERRIDE_VAL_5 1 3 RX_PDNB_OVERRIDE_EN_5 4 4 RX_PDNB_OVERRIDE_VAL_5 5 7 RXEN_OVERRIDE_EN_5 8 8 RXEN_OVERRIDE_VAL_5 9 9 TXPWR_OVERRIDE_EN_5 10 10 TXPWR_OVERRIDE_VAL_5 11 13 RXPWR_OVERRIDE_EN_5 14 14 RXPWR_OVERRIDE_VAL_5 15 17 ixPB0_PIF_PDNB_OVERRIDE_6 2 0x1100026 10 0 4294967295 TX_PDNB_OVERRIDE_EN_6 0 0 TX_PDNB_OVERRIDE_VAL_6 1 3 RX_PDNB_OVERRIDE_EN_6 4 4 RX_PDNB_OVERRIDE_VAL_6 5 7 RXEN_OVERRIDE_EN_6 8 8 RXEN_OVERRIDE_VAL_6 9 9 TXPWR_OVERRIDE_EN_6 10 10 TXPWR_OVERRIDE_VAL_6 11 13 RXPWR_OVERRIDE_EN_6 14 14 RXPWR_OVERRIDE_VAL_6 15 17 ixPB0_PIF_PDNB_OVERRIDE_7 2 0x1100027 10 0 4294967295 TX_PDNB_OVERRIDE_EN_7 0 0 TX_PDNB_OVERRIDE_VAL_7 1 3 RX_PDNB_OVERRIDE_EN_7 4 4 RX_PDNB_OVERRIDE_VAL_7 5 7 RXEN_OVERRIDE_EN_7 8 8 RXEN_OVERRIDE_VAL_7 9 9 TXPWR_OVERRIDE_EN_7 10 10 TXPWR_OVERRIDE_VAL_7 11 13 RXPWR_OVERRIDE_EN_7 14 14 RXPWR_OVERRIDE_VAL_7 15 17 ixPB0_PIF_SEQ_STATUS_0 2 0x1100028 8 0 4294967295 SEQ_CALIBRATION_0 0 0 SEQ_RXDETECT_0 1 1 SEQ_EXIT_L1_TO_L0S_0 2 2 SEQ_EXIT_L1_TO_L0_0 3 3 SEQ_ENTER_L1_FROM_L0S_0 4 4 SEQ_ENTER_L1_FROM_L0_0 5 5 SEQ_SPEED_CHANGE_0 6 6 SEQ_PHASE_0 8 10 ixPB0_PIF_SEQ_STATUS_1 2 0x1100029 8 0 4294967295 SEQ_CALIBRATION_1 0 0 SEQ_RXDETECT_1 1 1 SEQ_EXIT_L1_TO_L0S_1 2 2 SEQ_EXIT_L1_TO_L0_1 3 3 SEQ_ENTER_L1_FROM_L0S_1 4 4 SEQ_ENTER_L1_FROM_L0_1 5 5 SEQ_SPEED_CHANGE_1 6 6 SEQ_PHASE_1 8 10 ixPB0_PIF_SEQ_STATUS_2 2 0x110002a 8 0 4294967295 SEQ_CALIBRATION_2 0 0 SEQ_RXDETECT_2 1 1 SEQ_EXIT_L1_TO_L0S_2 2 2 SEQ_EXIT_L1_TO_L0_2 3 3 SEQ_ENTER_L1_FROM_L0S_2 4 4 SEQ_ENTER_L1_FROM_L0_2 5 5 SEQ_SPEED_CHANGE_2 6 6 SEQ_PHASE_2 8 10 ixPB0_PIF_SEQ_STATUS_3 2 0x110002b 8 0 4294967295 SEQ_CALIBRATION_3 0 0 SEQ_RXDETECT_3 1 1 SEQ_EXIT_L1_TO_L0S_3 2 2 SEQ_EXIT_L1_TO_L0_3 3 3 SEQ_ENTER_L1_FROM_L0S_3 4 4 SEQ_ENTER_L1_FROM_L0_3 5 5 SEQ_SPEED_CHANGE_3 6 6 SEQ_PHASE_3 8 10 ixPB0_PIF_SEQ_STATUS_4 2 0x110002c 8 0 4294967295 SEQ_CALIBRATION_4 0 0 SEQ_RXDETECT_4 1 1 SEQ_EXIT_L1_TO_L0S_4 2 2 SEQ_EXIT_L1_TO_L0_4 3 3 SEQ_ENTER_L1_FROM_L0S_4 4 4 SEQ_ENTER_L1_FROM_L0_4 5 5 SEQ_SPEED_CHANGE_4 6 6 SEQ_PHASE_4 8 10 ixPB0_PIF_SEQ_STATUS_5 2 0x110002d 8 0 4294967295 SEQ_CALIBRATION_5 0 0 SEQ_RXDETECT_5 1 1 SEQ_EXIT_L1_TO_L0S_5 2 2 SEQ_EXIT_L1_TO_L0_5 3 3 SEQ_ENTER_L1_FROM_L0S_5 4 4 SEQ_ENTER_L1_FROM_L0_5 5 5 SEQ_SPEED_CHANGE_5 6 6 SEQ_PHASE_5 8 10 ixPB0_PIF_SEQ_STATUS_6 2 0x110002e 8 0 4294967295 SEQ_CALIBRATION_6 0 0 SEQ_RXDETECT_6 1 1 SEQ_EXIT_L1_TO_L0S_6 2 2 SEQ_EXIT_L1_TO_L0_6 3 3 SEQ_ENTER_L1_FROM_L0S_6 4 4 SEQ_ENTER_L1_FROM_L0_6 5 5 SEQ_SPEED_CHANGE_6 6 6 SEQ_PHASE_6 8 10 ixPB0_PIF_SEQ_STATUS_7 2 0x110002f 8 0 4294967295 SEQ_CALIBRATION_7 0 0 SEQ_RXDETECT_7 1 1 SEQ_EXIT_L1_TO_L0S_7 2 2 SEQ_EXIT_L1_TO_L0_7 3 3 SEQ_ENTER_L1_FROM_L0S_7 4 4 SEQ_ENTER_L1_FROM_L0_7 5 5 SEQ_SPEED_CHANGE_7 6 6 SEQ_PHASE_7 8 10 ixPB0_PIF_PDNB_OVERRIDE_8 2 0x1100030 10 0 4294967295 TX_PDNB_OVERRIDE_EN_8 0 0 TX_PDNB_OVERRIDE_VAL_8 1 3 RX_PDNB_OVERRIDE_EN_8 4 4 RX_PDNB_OVERRIDE_VAL_8 5 7 RXEN_OVERRIDE_EN_8 8 8 RXEN_OVERRIDE_VAL_8 9 9 TXPWR_OVERRIDE_EN_8 10 10 TXPWR_OVERRIDE_VAL_8 11 13 RXPWR_OVERRIDE_EN_8 14 14 RXPWR_OVERRIDE_VAL_8 15 17 ixPB0_PIF_PDNB_OVERRIDE_9 2 0x1100031 10 0 4294967295 TX_PDNB_OVERRIDE_EN_9 0 0 TX_PDNB_OVERRIDE_VAL_9 1 3 RX_PDNB_OVERRIDE_EN_9 4 4 RX_PDNB_OVERRIDE_VAL_9 5 7 RXEN_OVERRIDE_EN_9 8 8 RXEN_OVERRIDE_VAL_9 9 9 TXPWR_OVERRIDE_EN_9 10 10 TXPWR_OVERRIDE_VAL_9 11 13 RXPWR_OVERRIDE_EN_9 14 14 RXPWR_OVERRIDE_VAL_9 15 17 ixPB0_PIF_PDNB_OVERRIDE_10 2 0x1100032 10 0 4294967295 TX_PDNB_OVERRIDE_EN_10 0 0 TX_PDNB_OVERRIDE_VAL_10 1 3 RX_PDNB_OVERRIDE_EN_10 4 4 RX_PDNB_OVERRIDE_VAL_10 5 7 RXEN_OVERRIDE_EN_10 8 8 RXEN_OVERRIDE_VAL_10 9 9 TXPWR_OVERRIDE_EN_10 10 10 TXPWR_OVERRIDE_VAL_10 11 13 RXPWR_OVERRIDE_EN_10 14 14 RXPWR_OVERRIDE_VAL_10 15 17 ixPB0_PIF_PDNB_OVERRIDE_11 2 0x1100033 10 0 4294967295 TX_PDNB_OVERRIDE_EN_11 0 0 TX_PDNB_OVERRIDE_VAL_11 1 3 RX_PDNB_OVERRIDE_EN_11 4 4 RX_PDNB_OVERRIDE_VAL_11 5 7 RXEN_OVERRIDE_EN_11 8 8 RXEN_OVERRIDE_VAL_11 9 9 TXPWR_OVERRIDE_EN_11 10 10 TXPWR_OVERRIDE_VAL_11 11 13 RXPWR_OVERRIDE_EN_11 14 14 RXPWR_OVERRIDE_VAL_11 15 17 ixPB0_PIF_PDNB_OVERRIDE_12 2 0x1100034 10 0 4294967295 TX_PDNB_OVERRIDE_EN_12 0 0 TX_PDNB_OVERRIDE_VAL_12 1 3 RX_PDNB_OVERRIDE_EN_12 4 4 RX_PDNB_OVERRIDE_VAL_12 5 7 RXEN_OVERRIDE_EN_12 8 8 RXEN_OVERRIDE_VAL_12 9 9 TXPWR_OVERRIDE_EN_12 10 10 TXPWR_OVERRIDE_VAL_12 11 13 RXPWR_OVERRIDE_EN_12 14 14 RXPWR_OVERRIDE_VAL_12 15 17 ixPB0_PIF_PDNB_OVERRIDE_13 2 0x1100035 10 0 4294967295 TX_PDNB_OVERRIDE_EN_13 0 0 TX_PDNB_OVERRIDE_VAL_13 1 3 RX_PDNB_OVERRIDE_EN_13 4 4 RX_PDNB_OVERRIDE_VAL_13 5 7 RXEN_OVERRIDE_EN_13 8 8 RXEN_OVERRIDE_VAL_13 9 9 TXPWR_OVERRIDE_EN_13 10 10 TXPWR_OVERRIDE_VAL_13 11 13 RXPWR_OVERRIDE_EN_13 14 14 RXPWR_OVERRIDE_VAL_13 15 17 ixPB0_PIF_PDNB_OVERRIDE_14 2 0x1100036 10 0 4294967295 TX_PDNB_OVERRIDE_EN_14 0 0 TX_PDNB_OVERRIDE_VAL_14 1 3 RX_PDNB_OVERRIDE_EN_14 4 4 RX_PDNB_OVERRIDE_VAL_14 5 7 RXEN_OVERRIDE_EN_14 8 8 RXEN_OVERRIDE_VAL_14 9 9 TXPWR_OVERRIDE_EN_14 10 10 TXPWR_OVERRIDE_VAL_14 11 13 RXPWR_OVERRIDE_EN_14 14 14 RXPWR_OVERRIDE_VAL_14 15 17 ixPB0_PIF_PDNB_OVERRIDE_15 2 0x1100037 10 0 4294967295 TX_PDNB_OVERRIDE_EN_15 0 0 TX_PDNB_OVERRIDE_VAL_15 1 3 RX_PDNB_OVERRIDE_EN_15 4 4 RX_PDNB_OVERRIDE_VAL_15 5 7 RXEN_OVERRIDE_EN_15 8 8 RXEN_OVERRIDE_VAL_15 9 9 TXPWR_OVERRIDE_EN_15 10 10 TXPWR_OVERRIDE_VAL_15 11 13 RXPWR_OVERRIDE_EN_15 14 14 RXPWR_OVERRIDE_VAL_15 15 17 ixPB0_PIF_SEQ_STATUS_8 2 0x1100038 8 0 4294967295 SEQ_CALIBRATION_8 0 0 SEQ_RXDETECT_8 1 1 SEQ_EXIT_L1_TO_L0S_8 2 2 SEQ_EXIT_L1_TO_L0_8 3 3 SEQ_ENTER_L1_FROM_L0S_8 4 4 SEQ_ENTER_L1_FROM_L0_8 5 5 SEQ_SPEED_CHANGE_8 6 6 SEQ_PHASE_8 8 10 ixPB0_PIF_SEQ_STATUS_9 2 0x1100039 8 0 4294967295 SEQ_CALIBRATION_9 0 0 SEQ_RXDETECT_9 1 1 SEQ_EXIT_L1_TO_L0S_9 2 2 SEQ_EXIT_L1_TO_L0_9 3 3 SEQ_ENTER_L1_FROM_L0S_9 4 4 SEQ_ENTER_L1_FROM_L0_9 5 5 SEQ_SPEED_CHANGE_9 6 6 SEQ_PHASE_9 8 10 ixPB0_PIF_SEQ_STATUS_10 2 0x110003a 8 0 4294967295 SEQ_CALIBRATION_10 0 0 SEQ_RXDETECT_10 1 1 SEQ_EXIT_L1_TO_L0S_10 2 2 SEQ_EXIT_L1_TO_L0_10 3 3 SEQ_ENTER_L1_FROM_L0S_10 4 4 SEQ_ENTER_L1_FROM_L0_10 5 5 SEQ_SPEED_CHANGE_10 6 6 SEQ_PHASE_10 8 10 ixPB0_PIF_SEQ_STATUS_11 2 0x110003b 8 0 4294967295 SEQ_CALIBRATION_11 0 0 SEQ_RXDETECT_11 1 1 SEQ_EXIT_L1_TO_L0S_11 2 2 SEQ_EXIT_L1_TO_L0_11 3 3 SEQ_ENTER_L1_FROM_L0S_11 4 4 SEQ_ENTER_L1_FROM_L0_11 5 5 SEQ_SPEED_CHANGE_11 6 6 SEQ_PHASE_11 8 10 ixPB0_PIF_SEQ_STATUS_12 2 0x110003c 8 0 4294967295 SEQ_CALIBRATION_12 0 0 SEQ_RXDETECT_12 1 1 SEQ_EXIT_L1_TO_L0S_12 2 2 SEQ_EXIT_L1_TO_L0_12 3 3 SEQ_ENTER_L1_FROM_L0S_12 4 4 SEQ_ENTER_L1_FROM_L0_12 5 5 SEQ_SPEED_CHANGE_12 6 6 SEQ_PHASE_12 8 10 ixPB0_PIF_SEQ_STATUS_13 2 0x110003d 8 0 4294967295 SEQ_CALIBRATION_13 0 0 SEQ_RXDETECT_13 1 1 SEQ_EXIT_L1_TO_L0S_13 2 2 SEQ_EXIT_L1_TO_L0_13 3 3 SEQ_ENTER_L1_FROM_L0S_13 4 4 SEQ_ENTER_L1_FROM_L0_13 5 5 SEQ_SPEED_CHANGE_13 6 6 SEQ_PHASE_13 8 10 ixPB0_PIF_SEQ_STATUS_14 2 0x110003e 8 0 4294967295 SEQ_CALIBRATION_14 0 0 SEQ_RXDETECT_14 1 1 SEQ_EXIT_L1_TO_L0S_14 2 2 SEQ_EXIT_L1_TO_L0_14 3 3 SEQ_ENTER_L1_FROM_L0S_14 4 4 SEQ_ENTER_L1_FROM_L0_14 5 5 SEQ_SPEED_CHANGE_14 6 6 SEQ_PHASE_14 8 10 ixPB0_PIF_SEQ_STATUS_15 2 0x110003f 8 0 4294967295 SEQ_CALIBRATION_15 0 0 SEQ_RXDETECT_15 1 1 SEQ_EXIT_L1_TO_L0S_15 2 2 SEQ_EXIT_L1_TO_L0_15 3 3 SEQ_ENTER_L1_FROM_L0S_15 4 4 SEQ_ENTER_L1_FROM_L0_15 5 5 SEQ_SPEED_CHANGE_15 6 6 SEQ_PHASE_15 8 10 ixPB1_PIF_SCRATCH 2 0x2100001 1 0 4294967295 PIF_SCRATCH 0 31 ixPB1_PIF_HW_DEBUG 2 0x2100002 16 0 4294967295 PB1_PIF_HW_00_DEBUG 0 0 PB1_PIF_HW_01_DEBUG 1 1 PB1_PIF_HW_02_DEBUG 2 2 PB1_PIF_HW_03_DEBUG 3 3 PB1_PIF_HW_04_DEBUG 4 4 PB1_PIF_HW_05_DEBUG 5 5 PB1_PIF_HW_06_DEBUG 6 6 PB1_PIF_HW_07_DEBUG 7 7 PB1_PIF_HW_08_DEBUG 8 8 PB1_PIF_HW_09_DEBUG 9 9 PB1_PIF_HW_10_DEBUG 10 10 PB1_PIF_HW_11_DEBUG 11 11 PB1_PIF_HW_12_DEBUG 12 12 PB1_PIF_HW_13_DEBUG 13 13 PB1_PIF_HW_14_DEBUG 14 14 PB1_PIF_HW_15_DEBUG 15 15 ixPB1_PIF_PRG6 2 0x2100003 1 0 4294967295 PRG_SPEEDCHANGE_STEP4_DELAY 0 17 ixPB1_PIF_PRG7 2 0x2100004 1 0 4294967295 PRG_SPEEDCHANGE_STEP4_FIRSTGEN3_DELAY 0 17 ixPB1_PIF_CNTL 2 0x2100010 24 0 4294967295 SERIAL_CFG_ENABLE 0 0 DA_FIFO_RESET_0 1 1 PHY_CR_EN_MODE 2 2 PHYCMD_CR_EN_MODE 3 3 EI_DET_CYCLE_MODE 4 4 DA_FIFO_RESET_1 5 5 RXDETECT_FIFO_RESET_MODE 6 6 RXDETECT_TX_PWR_MODE 7 7 DIVINIT_MODE 8 8 DA_FIFO_RESET_2 9 9 PLL_BINDING_ENABLE 10 10 SC_CALIB_DONE_CNTL 11 11 DIVINIT_ENABLE 12 12 DA_FIFO_RESET_3 13 13 PLL0_IN_GEN3_MODE 14 14 FORCE_TxFreqEquZeroinDTM_EN 15 15 TXGND_TIME 16 16 LS2_EXIT_TIME 17 19 EI_CYCLE_OFF_TIME 20 22 EXIT_L0S_INIT_DIS 23 23 RXEN_GATER 24 27 EXTEND_WAIT_FOR_RAMPUP 28 28 IGNORE_TxDataValid_EP_DIS 29 29 PHYRESPONSEMODE_ON_RXDET_EN 30 30 ixPB1_PIF_PAIRING 2 0x2100011 16 0 4294967295 X2_LANE_1_0 0 0 X2_LANE_3_2 1 1 X2_LANE_5_4 2 2 X2_LANE_7_6 3 3 X2_LANE_9_8 4 4 X2_LANE_11_10 5 5 X2_LANE_13_12 6 6 X2_LANE_15_14 7 7 X4_LANE_3_0 8 8 X4_LANE_7_4 9 9 X4_LANE_11_8 10 10 X4_LANE_15_12 11 11 X8_LANE_7_0 16 16 X8_LANE_15_8 17 17 X16_LANE_15_0 20 20 MULTI_PIF 25 25 ixPB1_PIF_PWRDOWN_0 2 0x2100012 9 0 4294967295 TX_POWER_STATE_IN_TXS2_0 0 2 FORCE_RXEN_IN_L0s_0 3 3 RX_POWER_STATE_IN_RXS2_0 4 6 PLL_POWER_STATE_IN_TXS2_0 7 9 PLL_POWER_STATE_IN_OFF_0 10 12 TX2P5CLK_CLOCK_GATING_EN_0 16 16 PLL_RAMP_UP_TIME_0 24 26 PLLPWR_OVERRIDE_EN_0 28 28 PLLPWR_OVERRIDE_VAL_0 29 31 ixPB1_PIF_PWRDOWN_1 2 0x2100013 9 0 4294967295 TX_POWER_STATE_IN_TXS2_1 0 2 FORCE_RXEN_IN_L0s_1 3 3 RX_POWER_STATE_IN_RXS2_1 4 6 PLL_POWER_STATE_IN_TXS2_1 7 9 PLL_POWER_STATE_IN_OFF_1 10 12 TX2P5CLK_CLOCK_GATING_EN_1 16 16 PLL_RAMP_UP_TIME_1 24 26 PLLPWR_OVERRIDE_EN_1 28 28 PLLPWR_OVERRIDE_VAL_1 29 31 ixPB1_PIF_CNTL2 2 0x2100014 29 0 4294967295 RXDETECT_PRG_EN 0 0 RXDETECT_SAMPL_TIME 1 2 PLL_RAMP_UP_TIME_PRG_EN 3 3 LS2_EXIT_TIME_PRG_EN 4 4 SERVICE2_STEP4_DELAY_PRG_EN 5 5 SERVICE3_STEP4_DELAY_PRG_EN 6 6 RXDETECT_OVERRIDE_EN 7 7 RXDETECT_OVERRIDE_VAL_0 8 8 RXDETECT_OVERRIDE_VAL_1 9 9 RXDETECT_OVERRIDE_VAL_2 10 10 RXDETECT_OVERRIDE_VAL_3 11 11 RXDETECT_OVERRIDE_VAL_4 12 12 RXDETECT_OVERRIDE_VAL_5 13 13 RXDETECT_OVERRIDE_VAL_6 14 14 RXDETECT_OVERRIDE_VAL_7 15 15 RXDETECT_OVERRIDE_VAL_8 16 16 RXDETECT_OVERRIDE_VAL_9 17 17 RXDETECT_OVERRIDE_VAL_10 18 18 RXDETECT_OVERRIDE_VAL_11 19 19 RXDETECT_OVERRIDE_VAL_12 20 20 RXDETECT_OVERRIDE_VAL_13 21 21 RXDETECT_OVERRIDE_VAL_14 22 22 RXDETECT_OVERRIDE_VAL_15 23 23 RXPHYSTATUS_DELAY 24 26 RX_STAGGERING_MODE 27 27 SPEEDCHANGE_STEP2_DELAY_PRG_EN 28 28 RX_STAGGERING_DISABLE 29 29 PLL1_ALWAYS_ON_EN 30 30 SPEEDCHANGE_STEP4_DELAY_FORCE_LONG_EN 31 31 ixPB1_PIF_TXPHYSTATUS 2 0x2100015 16 0 4294967295 TXPHYSTATUS_0 0 0 TXPHYSTATUS_1 1 1 TXPHYSTATUS_2 2 2 TXPHYSTATUS_3 3 3 TXPHYSTATUS_4 4 4 TXPHYSTATUS_5 5 5 TXPHYSTATUS_6 6 6 TXPHYSTATUS_7 7 7 TXPHYSTATUS_8 8 8 TXPHYSTATUS_9 9 9 TXPHYSTATUS_10 10 10 TXPHYSTATUS_11 11 11 TXPHYSTATUS_12 12 12 TXPHYSTATUS_13 13 13 TXPHYSTATUS_14 14 14 TXPHYSTATUS_15 15 15 ixPB1_PIF_SC_CTL 2 0x2100016 31 0 4294967295 SC_CALIBRATION 0 0 SC_RXDETECT 1 1 SC_EXIT_L1_TO_L0S 2 2 SC_EXIT_L1_TO_L0 3 3 SC_ENTER_L1_FROM_L0S 4 4 SC_ENTER_L1_FROM_L0 5 5 SC_SPEED_CHANGE 6 6 SC_PHASE_1 8 8 SC_PHASE_2 9 9 SC_PHASE_3 10 10 SC_PHASE_4 11 11 SC_PHASE_5 12 12 SC_PHASE_6 13 13 SC_PHASE_7 14 14 SC_PHASE_8 15 15 SC_LANE_0_RESUME 16 16 SC_LANE_1_RESUME 17 17 SC_LANE_2_RESUME 18 18 SC_LANE_3_RESUME 19 19 SC_LANE_4_RESUME 20 20 SC_LANE_5_RESUME 21 21 SC_LANE_6_RESUME 22 22 SC_LANE_7_RESUME 23 23 SC_LANE_8_RESUME 24 24 SC_LANE_9_RESUME 25 25 SC_LANE_10_RESUME 26 26 SC_LANE_11_RESUME 27 27 SC_LANE_12_RESUME 28 28 SC_LANE_13_RESUME 29 29 SC_LANE_14_RESUME 30 30 SC_LANE_15_RESUME 31 31 ixPB1_PIF_PWRDOWN_2 2 0x2100017 9 0 4294967295 TX_POWER_STATE_IN_TXS2_2 0 2 FORCE_RXEN_IN_L0s_2 3 3 RX_POWER_STATE_IN_RXS2_2 4 6 PLL_POWER_STATE_IN_TXS2_2 7 9 PLL_POWER_STATE_IN_OFF_2 10 12 TX2P5CLK_CLOCK_GATING_EN_2 16 16 PLL_RAMP_UP_TIME_2 24 26 PLLPWR_OVERRIDE_EN_2 28 28 PLLPWR_OVERRIDE_VAL_2 29 31 ixPB1_PIF_PWRDOWN_3 2 0x2100018 9 0 4294967295 TX_POWER_STATE_IN_TXS2_3 0 2 FORCE_RXEN_IN_L0s_3 3 3 RX_POWER_STATE_IN_RXS2_3 4 6 PLL_POWER_STATE_IN_TXS2_3 7 9 PLL_POWER_STATE_IN_OFF_3 10 12 TX2P5CLK_CLOCK_GATING_EN_3 16 16 PLL_RAMP_UP_TIME_3 24 26 PLLPWR_OVERRIDE_EN_3 28 28 PLLPWR_OVERRIDE_VAL_3 29 31 ixPB1_PIF_SC_CTL2 2 0x2100019 16 0 4294967295 SERIAL_CFG_PERLANE_DISABLE_0 0 0 SERIAL_CFG_PERLANE_DISABLE_1 1 1 SERIAL_CFG_PERLANE_DISABLE_2 2 2 SERIAL_CFG_PERLANE_DISABLE_3 3 3 SERIAL_CFG_PERLANE_DISABLE_4 4 4 SERIAL_CFG_PERLANE_DISABLE_5 5 5 SERIAL_CFG_PERLANE_DISABLE_6 6 6 SERIAL_CFG_PERLANE_DISABLE_7 7 7 SERIAL_CFG_PERLANE_DISABLE_8 8 8 SERIAL_CFG_PERLANE_DISABLE_9 9 9 SERIAL_CFG_PERLANE_DISABLE_10 10 10 SERIAL_CFG_PERLANE_DISABLE_11 11 11 SERIAL_CFG_PERLANE_DISABLE_12 12 12 SERIAL_CFG_PERLANE_DISABLE_13 13 13 SERIAL_CFG_PERLANE_DISABLE_14 14 14 SERIAL_CFG_PERLANE_DISABLE_15 15 15 ixPB1_PIF_PRG0 2 0x210001a 1 0 4294967295 PRG_RXDETECT_SAMPL_TIME 0 17 ixPB1_PIF_PRG1 2 0x210001b 1 0 4294967295 PRG_PLL_RAMP_UP_TIME 0 17 ixPB1_PIF_PRG2 2 0x210001c 1 0 4294967295 PRG_SERVICE2_STEP4_DELAY 0 17 ixPB1_PIF_PRG3 2 0x210001d 1 0 4294967295 PRG_SERVICE3_STEP4_DELAY 0 17 ixPB1_PIF_PRG4 2 0x210001e 1 0 4294967295 PRG_SPEEDCHANGE_STEP2_DELAY 0 17 ixPB1_PIF_PRG5 2 0x210001f 1 0 4294967295 PRG_LS2_EXIT_TIME 0 17 ixPB1_PIF_PDNB_OVERRIDE_0 2 0x2100020 10 0 4294967295 TX_PDNB_OVERRIDE_EN_0 0 0 TX_PDNB_OVERRIDE_VAL_0 1 3 RX_PDNB_OVERRIDE_EN_0 4 4 RX_PDNB_OVERRIDE_VAL_0 5 7 RXEN_OVERRIDE_EN_0 8 8 RXEN_OVERRIDE_VAL_0 9 9 TXPWR_OVERRIDE_EN_0 10 10 TXPWR_OVERRIDE_VAL_0 11 13 RXPWR_OVERRIDE_EN_0 14 14 RXPWR_OVERRIDE_VAL_0 15 17 ixPB1_PIF_PDNB_OVERRIDE_1 2 0x2100021 10 0 4294967295 TX_PDNB_OVERRIDE_EN_1 0 0 TX_PDNB_OVERRIDE_VAL_1 1 3 RX_PDNB_OVERRIDE_EN_1 4 4 RX_PDNB_OVERRIDE_VAL_1 5 7 RXEN_OVERRIDE_EN_1 8 8 RXEN_OVERRIDE_VAL_1 9 9 TXPWR_OVERRIDE_EN_1 10 10 TXPWR_OVERRIDE_VAL_1 11 13 RXPWR_OVERRIDE_EN_1 14 14 RXPWR_OVERRIDE_VAL_1 15 17 ixPB1_PIF_PDNB_OVERRIDE_2 2 0x2100022 10 0 4294967295 TX_PDNB_OVERRIDE_EN_2 0 0 TX_PDNB_OVERRIDE_VAL_2 1 3 RX_PDNB_OVERRIDE_EN_2 4 4 RX_PDNB_OVERRIDE_VAL_2 5 7 RXEN_OVERRIDE_EN_2 8 8 RXEN_OVERRIDE_VAL_2 9 9 TXPWR_OVERRIDE_EN_2 10 10 TXPWR_OVERRIDE_VAL_2 11 13 RXPWR_OVERRIDE_EN_2 14 14 RXPWR_OVERRIDE_VAL_2 15 17 ixPB1_PIF_PDNB_OVERRIDE_3 2 0x2100023 10 0 4294967295 TX_PDNB_OVERRIDE_EN_3 0 0 TX_PDNB_OVERRIDE_VAL_3 1 3 RX_PDNB_OVERRIDE_EN_3 4 4 RX_PDNB_OVERRIDE_VAL_3 5 7 RXEN_OVERRIDE_EN_3 8 8 RXEN_OVERRIDE_VAL_3 9 9 TXPWR_OVERRIDE_EN_3 10 10 TXPWR_OVERRIDE_VAL_3 11 13 RXPWR_OVERRIDE_EN_3 14 14 RXPWR_OVERRIDE_VAL_3 15 17 ixPB1_PIF_PDNB_OVERRIDE_4 2 0x2100024 10 0 4294967295 TX_PDNB_OVERRIDE_EN_4 0 0 TX_PDNB_OVERRIDE_VAL_4 1 3 RX_PDNB_OVERRIDE_EN_4 4 4 RX_PDNB_OVERRIDE_VAL_4 5 7 RXEN_OVERRIDE_EN_4 8 8 RXEN_OVERRIDE_VAL_4 9 9 TXPWR_OVERRIDE_EN_4 10 10 TXPWR_OVERRIDE_VAL_4 11 13 RXPWR_OVERRIDE_EN_4 14 14 RXPWR_OVERRIDE_VAL_4 15 17 ixPB1_PIF_PDNB_OVERRIDE_5 2 0x2100025 10 0 4294967295 TX_PDNB_OVERRIDE_EN_5 0 0 TX_PDNB_OVERRIDE_VAL_5 1 3 RX_PDNB_OVERRIDE_EN_5 4 4 RX_PDNB_OVERRIDE_VAL_5 5 7 RXEN_OVERRIDE_EN_5 8 8 RXEN_OVERRIDE_VAL_5 9 9 TXPWR_OVERRIDE_EN_5 10 10 TXPWR_OVERRIDE_VAL_5 11 13 RXPWR_OVERRIDE_EN_5 14 14 RXPWR_OVERRIDE_VAL_5 15 17 ixPB1_PIF_PDNB_OVERRIDE_6 2 0x2100026 10 0 4294967295 TX_PDNB_OVERRIDE_EN_6 0 0 TX_PDNB_OVERRIDE_VAL_6 1 3 RX_PDNB_OVERRIDE_EN_6 4 4 RX_PDNB_OVERRIDE_VAL_6 5 7 RXEN_OVERRIDE_EN_6 8 8 RXEN_OVERRIDE_VAL_6 9 9 TXPWR_OVERRIDE_EN_6 10 10 TXPWR_OVERRIDE_VAL_6 11 13 RXPWR_OVERRIDE_EN_6 14 14 RXPWR_OVERRIDE_VAL_6 15 17 ixPB1_PIF_PDNB_OVERRIDE_7 2 0x2100027 10 0 4294967295 TX_PDNB_OVERRIDE_EN_7 0 0 TX_PDNB_OVERRIDE_VAL_7 1 3 RX_PDNB_OVERRIDE_EN_7 4 4 RX_PDNB_OVERRIDE_VAL_7 5 7 RXEN_OVERRIDE_EN_7 8 8 RXEN_OVERRIDE_VAL_7 9 9 TXPWR_OVERRIDE_EN_7 10 10 TXPWR_OVERRIDE_VAL_7 11 13 RXPWR_OVERRIDE_EN_7 14 14 RXPWR_OVERRIDE_VAL_7 15 17 ixPB1_PIF_SEQ_STATUS_0 2 0x2100028 8 0 4294967295 SEQ_CALIBRATION_0 0 0 SEQ_RXDETECT_0 1 1 SEQ_EXIT_L1_TO_L0S_0 2 2 SEQ_EXIT_L1_TO_L0_0 3 3 SEQ_ENTER_L1_FROM_L0S_0 4 4 SEQ_ENTER_L1_FROM_L0_0 5 5 SEQ_SPEED_CHANGE_0 6 6 SEQ_PHASE_0 8 10 ixPB1_PIF_SEQ_STATUS_1 2 0x2100029 8 0 4294967295 SEQ_CALIBRATION_1 0 0 SEQ_RXDETECT_1 1 1 SEQ_EXIT_L1_TO_L0S_1 2 2 SEQ_EXIT_L1_TO_L0_1 3 3 SEQ_ENTER_L1_FROM_L0S_1 4 4 SEQ_ENTER_L1_FROM_L0_1 5 5 SEQ_SPEED_CHANGE_1 6 6 SEQ_PHASE_1 8 10 ixPB1_PIF_SEQ_STATUS_2 2 0x210002a 8 0 4294967295 SEQ_CALIBRATION_2 0 0 SEQ_RXDETECT_2 1 1 SEQ_EXIT_L1_TO_L0S_2 2 2 SEQ_EXIT_L1_TO_L0_2 3 3 SEQ_ENTER_L1_FROM_L0S_2 4 4 SEQ_ENTER_L1_FROM_L0_2 5 5 SEQ_SPEED_CHANGE_2 6 6 SEQ_PHASE_2 8 10 ixPB1_PIF_SEQ_STATUS_3 2 0x210002b 8 0 4294967295 SEQ_CALIBRATION_3 0 0 SEQ_RXDETECT_3 1 1 SEQ_EXIT_L1_TO_L0S_3 2 2 SEQ_EXIT_L1_TO_L0_3 3 3 SEQ_ENTER_L1_FROM_L0S_3 4 4 SEQ_ENTER_L1_FROM_L0_3 5 5 SEQ_SPEED_CHANGE_3 6 6 SEQ_PHASE_3 8 10 ixPB1_PIF_SEQ_STATUS_4 2 0x210002c 8 0 4294967295 SEQ_CALIBRATION_4 0 0 SEQ_RXDETECT_4 1 1 SEQ_EXIT_L1_TO_L0S_4 2 2 SEQ_EXIT_L1_TO_L0_4 3 3 SEQ_ENTER_L1_FROM_L0S_4 4 4 SEQ_ENTER_L1_FROM_L0_4 5 5 SEQ_SPEED_CHANGE_4 6 6 SEQ_PHASE_4 8 10 ixPB1_PIF_SEQ_STATUS_5 2 0x210002d 8 0 4294967295 SEQ_CALIBRATION_5 0 0 SEQ_RXDETECT_5 1 1 SEQ_EXIT_L1_TO_L0S_5 2 2 SEQ_EXIT_L1_TO_L0_5 3 3 SEQ_ENTER_L1_FROM_L0S_5 4 4 SEQ_ENTER_L1_FROM_L0_5 5 5 SEQ_SPEED_CHANGE_5 6 6 SEQ_PHASE_5 8 10 ixPB1_PIF_SEQ_STATUS_6 2 0x210002e 8 0 4294967295 SEQ_CALIBRATION_6 0 0 SEQ_RXDETECT_6 1 1 SEQ_EXIT_L1_TO_L0S_6 2 2 SEQ_EXIT_L1_TO_L0_6 3 3 SEQ_ENTER_L1_FROM_L0S_6 4 4 SEQ_ENTER_L1_FROM_L0_6 5 5 SEQ_SPEED_CHANGE_6 6 6 SEQ_PHASE_6 8 10 ixPB1_PIF_SEQ_STATUS_7 2 0x210002f 8 0 4294967295 SEQ_CALIBRATION_7 0 0 SEQ_RXDETECT_7 1 1 SEQ_EXIT_L1_TO_L0S_7 2 2 SEQ_EXIT_L1_TO_L0_7 3 3 SEQ_ENTER_L1_FROM_L0S_7 4 4 SEQ_ENTER_L1_FROM_L0_7 5 5 SEQ_SPEED_CHANGE_7 6 6 SEQ_PHASE_7 8 10 ixPB1_PIF_PDNB_OVERRIDE_8 2 0x2100030 10 0 4294967295 TX_PDNB_OVERRIDE_EN_8 0 0 TX_PDNB_OVERRIDE_VAL_8 1 3 RX_PDNB_OVERRIDE_EN_8 4 4 RX_PDNB_OVERRIDE_VAL_8 5 7 RXEN_OVERRIDE_EN_8 8 8 RXEN_OVERRIDE_VAL_8 9 9 TXPWR_OVERRIDE_EN_8 10 10 TXPWR_OVERRIDE_VAL_8 11 13 RXPWR_OVERRIDE_EN_8 14 14 RXPWR_OVERRIDE_VAL_8 15 17 ixPB1_PIF_PDNB_OVERRIDE_9 2 0x2100031 10 0 4294967295 TX_PDNB_OVERRIDE_EN_9 0 0 TX_PDNB_OVERRIDE_VAL_9 1 3 RX_PDNB_OVERRIDE_EN_9 4 4 RX_PDNB_OVERRIDE_VAL_9 5 7 RXEN_OVERRIDE_EN_9 8 8 RXEN_OVERRIDE_VAL_9 9 9 TXPWR_OVERRIDE_EN_9 10 10 TXPWR_OVERRIDE_VAL_9 11 13 RXPWR_OVERRIDE_EN_9 14 14 RXPWR_OVERRIDE_VAL_9 15 17 ixPB1_PIF_PDNB_OVERRIDE_10 2 0x2100032 10 0 4294967295 TX_PDNB_OVERRIDE_EN_10 0 0 TX_PDNB_OVERRIDE_VAL_10 1 3 RX_PDNB_OVERRIDE_EN_10 4 4 RX_PDNB_OVERRIDE_VAL_10 5 7 RXEN_OVERRIDE_EN_10 8 8 RXEN_OVERRIDE_VAL_10 9 9 TXPWR_OVERRIDE_EN_10 10 10 TXPWR_OVERRIDE_VAL_10 11 13 RXPWR_OVERRIDE_EN_10 14 14 RXPWR_OVERRIDE_VAL_10 15 17 ixPB1_PIF_PDNB_OVERRIDE_11 2 0x2100033 10 0 4294967295 TX_PDNB_OVERRIDE_EN_11 0 0 TX_PDNB_OVERRIDE_VAL_11 1 3 RX_PDNB_OVERRIDE_EN_11 4 4 RX_PDNB_OVERRIDE_VAL_11 5 7 RXEN_OVERRIDE_EN_11 8 8 RXEN_OVERRIDE_VAL_11 9 9 TXPWR_OVERRIDE_EN_11 10 10 TXPWR_OVERRIDE_VAL_11 11 13 RXPWR_OVERRIDE_EN_11 14 14 RXPWR_OVERRIDE_VAL_11 15 17 ixPB1_PIF_PDNB_OVERRIDE_12 2 0x2100034 10 0 4294967295 TX_PDNB_OVERRIDE_EN_12 0 0 TX_PDNB_OVERRIDE_VAL_12 1 3 RX_PDNB_OVERRIDE_EN_12 4 4 RX_PDNB_OVERRIDE_VAL_12 5 7 RXEN_OVERRIDE_EN_12 8 8 RXEN_OVERRIDE_VAL_12 9 9 TXPWR_OVERRIDE_EN_12 10 10 TXPWR_OVERRIDE_VAL_12 11 13 RXPWR_OVERRIDE_EN_12 14 14 RXPWR_OVERRIDE_VAL_12 15 17 ixPB1_PIF_PDNB_OVERRIDE_13 2 0x2100035 10 0 4294967295 TX_PDNB_OVERRIDE_EN_13 0 0 TX_PDNB_OVERRIDE_VAL_13 1 3 RX_PDNB_OVERRIDE_EN_13 4 4 RX_PDNB_OVERRIDE_VAL_13 5 7 RXEN_OVERRIDE_EN_13 8 8 RXEN_OVERRIDE_VAL_13 9 9 TXPWR_OVERRIDE_EN_13 10 10 TXPWR_OVERRIDE_VAL_13 11 13 RXPWR_OVERRIDE_EN_13 14 14 RXPWR_OVERRIDE_VAL_13 15 17 ixPB1_PIF_PDNB_OVERRIDE_14 2 0x2100036 10 0 4294967295 TX_PDNB_OVERRIDE_EN_14 0 0 TX_PDNB_OVERRIDE_VAL_14 1 3 RX_PDNB_OVERRIDE_EN_14 4 4 RX_PDNB_OVERRIDE_VAL_14 5 7 RXEN_OVERRIDE_EN_14 8 8 RXEN_OVERRIDE_VAL_14 9 9 TXPWR_OVERRIDE_EN_14 10 10 TXPWR_OVERRIDE_VAL_14 11 13 RXPWR_OVERRIDE_EN_14 14 14 RXPWR_OVERRIDE_VAL_14 15 17 ixPB1_PIF_PDNB_OVERRIDE_15 2 0x2100037 10 0 4294967295 TX_PDNB_OVERRIDE_EN_15 0 0 TX_PDNB_OVERRIDE_VAL_15 1 3 RX_PDNB_OVERRIDE_EN_15 4 4 RX_PDNB_OVERRIDE_VAL_15 5 7 RXEN_OVERRIDE_EN_15 8 8 RXEN_OVERRIDE_VAL_15 9 9 TXPWR_OVERRIDE_EN_15 10 10 TXPWR_OVERRIDE_VAL_15 11 13 RXPWR_OVERRIDE_EN_15 14 14 RXPWR_OVERRIDE_VAL_15 15 17 ixPB1_PIF_SEQ_STATUS_8 2 0x2100038 8 0 4294967295 SEQ_CALIBRATION_8 0 0 SEQ_RXDETECT_8 1 1 SEQ_EXIT_L1_TO_L0S_8 2 2 SEQ_EXIT_L1_TO_L0_8 3 3 SEQ_ENTER_L1_FROM_L0S_8 4 4 SEQ_ENTER_L1_FROM_L0_8 5 5 SEQ_SPEED_CHANGE_8 6 6 SEQ_PHASE_8 8 10 ixPB1_PIF_SEQ_STATUS_9 2 0x2100039 8 0 4294967295 SEQ_CALIBRATION_9 0 0 SEQ_RXDETECT_9 1 1 SEQ_EXIT_L1_TO_L0S_9 2 2 SEQ_EXIT_L1_TO_L0_9 3 3 SEQ_ENTER_L1_FROM_L0S_9 4 4 SEQ_ENTER_L1_FROM_L0_9 5 5 SEQ_SPEED_CHANGE_9 6 6 SEQ_PHASE_9 8 10 ixPB1_PIF_SEQ_STATUS_10 2 0x210003a 8 0 4294967295 SEQ_CALIBRATION_10 0 0 SEQ_RXDETECT_10 1 1 SEQ_EXIT_L1_TO_L0S_10 2 2 SEQ_EXIT_L1_TO_L0_10 3 3 SEQ_ENTER_L1_FROM_L0S_10 4 4 SEQ_ENTER_L1_FROM_L0_10 5 5 SEQ_SPEED_CHANGE_10 6 6 SEQ_PHASE_10 8 10 ixPB1_PIF_SEQ_STATUS_11 2 0x210003b 8 0 4294967295 SEQ_CALIBRATION_11 0 0 SEQ_RXDETECT_11 1 1 SEQ_EXIT_L1_TO_L0S_11 2 2 SEQ_EXIT_L1_TO_L0_11 3 3 SEQ_ENTER_L1_FROM_L0S_11 4 4 SEQ_ENTER_L1_FROM_L0_11 5 5 SEQ_SPEED_CHANGE_11 6 6 SEQ_PHASE_11 8 10 ixPB1_PIF_SEQ_STATUS_12 2 0x210003c 8 0 4294967295 SEQ_CALIBRATION_12 0 0 SEQ_RXDETECT_12 1 1 SEQ_EXIT_L1_TO_L0S_12 2 2 SEQ_EXIT_L1_TO_L0_12 3 3 SEQ_ENTER_L1_FROM_L0S_12 4 4 SEQ_ENTER_L1_FROM_L0_12 5 5 SEQ_SPEED_CHANGE_12 6 6 SEQ_PHASE_12 8 10 ixPB1_PIF_SEQ_STATUS_13 2 0x210003d 8 0 4294967295 SEQ_CALIBRATION_13 0 0 SEQ_RXDETECT_13 1 1 SEQ_EXIT_L1_TO_L0S_13 2 2 SEQ_EXIT_L1_TO_L0_13 3 3 SEQ_ENTER_L1_FROM_L0S_13 4 4 SEQ_ENTER_L1_FROM_L0_13 5 5 SEQ_SPEED_CHANGE_13 6 6 SEQ_PHASE_13 8 10 ixPB1_PIF_SEQ_STATUS_14 2 0x210003e 8 0 4294967295 SEQ_CALIBRATION_14 0 0 SEQ_RXDETECT_14 1 1 SEQ_EXIT_L1_TO_L0S_14 2 2 SEQ_EXIT_L1_TO_L0_14 3 3 SEQ_ENTER_L1_FROM_L0S_14 4 4 SEQ_ENTER_L1_FROM_L0_14 5 5 SEQ_SPEED_CHANGE_14 6 6 SEQ_PHASE_14 8 10 ixPB1_PIF_SEQ_STATUS_15 2 0x210003f 8 0 4294967295 SEQ_CALIBRATION_15 0 0 SEQ_RXDETECT_15 1 1 SEQ_EXIT_L1_TO_L0S_15 2 2 SEQ_EXIT_L1_TO_L0_15 3 3 SEQ_ENTER_L1_FROM_L0S_15 4 4 SEQ_ENTER_L1_FROM_L0_15 5 5 SEQ_SPEED_CHANGE_15 6 6 SEQ_PHASE_15 8 10 mmBIF_RFE_SNOOP_REG 0 0x27 2 0 4294967295 REG_SNOOP_ARBITER 0 0 REG_SNOOP_ALLMASTER 1 1 mmBIF_RFE_WARMRST_CNTL 0 0x1459 2 0 4294967295 REG_RST_warmRstRfeEn 0 0 REG_RST_warmRstImpEn 1 1 mmBIF_RFE_SOFTRST_CNTL 0 0x1441 3 0 4294967295 REG_RST_rstTimer 0 15 REG_RST_softRstPropEn 30 30 SoftRstReg 31 31 mmBIF_RFE_IMPRST_CNTL 0 0x1458 1 0 4294967295 REG_RST_impEn 0 0 mmBIF_RFE_CLIENT_SOFTRST_TRIGGER 0 0x1442 2 0 4294967295 CLIENT0_RFE_RFEWDBIF_rst 0 0 CLIENT1_RFE_RFEWDBIF_rst 1 1 mmBIF_RFE_MASTER_SOFTRST_TRIGGER 0 0x1443 3 0 4294967295 BU_rst 0 0 RWREG_RFEWDBIF_rst 1 1 BX_rst 2 2 mmBIF_PWDN_COMMAND 0 0x1444 3 0 4294967295 REG_BU_pw_cmd 0 0 REG_RWREG_RFEWDBIF_pw_cmd 1 1 REG_BX_pw_cmd 2 2 mmBIF_PWDN_STATUS 0 0x1445 3 0 4294967295 BU_REG_pw_status 0 0 RWREG_RFEWDBIF_REG_pw_status 1 1 BX_REG_pw_status 2 2 mmBIF_RFE_MST_BU_CMDSTATUS 0 0x1446 4 0 4294967295 REG_BU_clkGate_timer 0 7 REG_BU_clkSetup_timer 8 11 REG_BU_timeout_timer 16 23 BU_RFE_mstTimeout 24 24 mmBIF_RFE_MST_RWREG_RFEWDBIF_CMDSTATUS 0 0x1447 4 0 4294967295 REG_RWREG_RFEWDBIF_clkGate_timer 0 7 REG_RWREG_RFEWDBIF_clkSetup_timer 8 11 REG_RWREG_RFEWDBIF_timeout_timer 16 23 RWREG_RFEWDBIF_RFE_mstTimeout 24 24 mmBIF_RFE_MST_BX_CMDSTATUS 0 0x1448 4 0 4294967295 REG_BX_clkGate_timer 0 7 REG_BX_clkSetup_timer 8 11 REG_BX_timeout_timer 16 23 BX_RFE_mstTimeout 24 24 mmBIF_RFE_MST_TMOUT_STATUS 0 0x144b 1 0 4294967295 MstTmoutStatus 0 0 mmBIF_RFE_MMCFG_CNTL 0 0x144c 4 0 4294967295 CLIENT0_RFE_RFEWDBIF_MM_WR_TO_CFG_EN 0 0 CLIENT0_RFE_RFEWDBIF_MM_CFG_FUNC_SEL 1 3 CLIENT1_RFE_RFEWDBIF_MM_WR_TO_CFG_EN 4 4 CLIENT1_RFE_RFEWDBIF_MM_CFG_FUNC_SEL 5 7 mmBIF_CC_RFE_IMP_OVERRIDECNTL 0 0x1455 7 0 4294967295 STRAP_PLL_RX_IMPVAL 1 4 STRAP_PLL_RX_IMPVAL_EN 5 5 STRAP_PLL_TX_IMPVAL_PD 6 9 STRAP_PLL_TX_IMPVAL_EN_PD 10 10 STRAP_PLL_TX_IMPVAL_PU 11 14 STRAP_PLL_TX_IMPVAL_EN_PU 15 15 STRAP_PLL_IMP_DBG_ANALOG_EN 16 16 mmBIF_IMPCTL_SMPLCNTL 0 0x1450 10 0 4294967295 FORCE_DONE 0 0 RxPDNB 1 1 TxPDNB_pd 2 2 TxPDNB_pu 3 3 SAMPLE_PERIOD 8 12 EXTEND_SAMPLES 13 13 FORCE_ENABLE 14 14 SETUP_TIME 15 19 LOWER_SAMPLE_THRESH 20 25 UPPER_SAMPLE_THRESH 26 31 mmBIF_IMPCTL_RXCNTL 0 0x1451 14 0 4294967295 RX_ADJUST 0 2 RX_BIAS_HIGH 3 3 CONT_AFTER_RX_DECT 4 4 SUSPEND 6 6 FORCE_RST 7 7 LOWER_RX_ADJ_THRESH 8 11 LOWER_RX_ADJ 12 12 UPPER_RX_ADJ_THRESH 13 16 UPPER_RX_ADJ 17 17 RX_IMP_LOCKED 18 18 RX_IMP_READBACK_SEL 19 19 RX_IMP_READBACK 20 23 RX_CMP_AMBIG 28 28 CAL_DONE 29 29 mmBIF_IMPCTL_TXCNTL_pd 0 0x1452 10 0 4294967295 TX_ADJUST_pd 0 2 TX_BIAS_HIGH_pd 3 3 LOWER_TX_ADJ_THRESH_pd 8 11 LOWER_TX_ADJ_pd 12 12 UPPER_TX_ADJ_THRESH_pd 13 16 UPPER_TX_ADJ_pd 17 17 TX_IMP_LOCKED_pd 18 18 TX_IMP_READBACK_SEL_pd 19 19 TX_IMP_READBACK_pd 20 23 TX_CMP_AMBIG_pd 28 28 mmBIF_IMPCTL_TXCNTL_pu 0 0x1453 10 0 4294967295 TX_ADJUST_pu 0 2 TX_BIAS_HIGH_pu 3 3 LOWER_TX_ADJ_THRESH_pu 8 11 LOWER_TX_ADJ_pu 12 12 UPPER_TX_ADJ_THRESH_pu 13 16 UPPER_TX_ADJ_pu 17 17 TX_IMP_LOCKED_pu 18 18 TX_IMP_READBACK_SEL_pu 19 19 TX_IMP_READBACK_pu 20 23 TX_CMP_AMBIG_pu 28 28 mmBIF_IMPCTL_CONTINUOUS_CALIBRATION_PERIOD 0 0x1454 1 0 4294967295 UPDATE_PERIOD 0 31 mmBIF_CLOCKS_BITS 0 0x1489 1 0 4294967295 OBFF_XSL_FORCE_REFCLK 0 0 mmBIF_LNCNT_RESET 0 0x1488 1 0 4294967295 RESET_LNCNT_EN 0 0 mmLNCNT_CONTROL 0 0x1487 2 0 4294967295 LNCNT_ACC_MODE 0 0 LNCNT_REF_TIMEBASE 1 2 mmNEW_REFCLKB_TIMER 0 0x1485 3 0 4294967295 REG_STOP_REFCLK_EN 0 0 STOP_REFCLK_TIMER 1 20 REFCLK_ON 21 21 mmNEW_REFCLKB_TIMER_1 0 0x1484 2 0 4294967295 PHY_PLL_PDWN_TIMER 0 9 PLL0_PDNB_EN 10 10 mmBIF_CLK_PDWN_DELAY_TIMER 0 0x1483 1 0 4294967295 TIMER 0 9 mmBIF_RESET_EN 0 0x1482 22 0 4294967295 SOFT_RST_MODE 1 1 PHY_RESET_EN 2 2 COR_RESET_EN 3 3 REG_RESET_EN 4 4 STY_RESET_EN 5 5 CFG_RESET_EN 6 6 DRV_RESET_EN 7 7 RESET_CFGREG_ONLY_EN 8 8 HOT_RESET_EN 9 9 LINK_DISABLE_RESET_EN 10 10 LINK_DOWN_RESET_EN 11 11 CFG_RESET_PULSE_WIDTH 12 17 DRV_RESET_DELAY_SEL 18 19 PIF_RSTB_EN 20 20 PIF_STRAP_ALLVALID_EN 21 21 BIF_COR_RESET_EN 22 22 FUNC0_FLR_EN 23 23 FUNC1_FLR_EN 24 24 FUNC2_FLR_EN 25 25 FUNC0_RESET_DELAY_SEL 26 27 FUNC1_RESET_DELAY_SEL 28 29 FUNC2_RESET_DELAY_SEL 30 31 mmBIF_PIF_TXCLK_SWITCH_TIMER 0 0x1481 3 0 4294967295 PLL0_ACK_TIMER 0 2 PLL1_ACK_TIMER 3 5 PLL_SWITCH_TIMER 6 9 mmBIF_BACO_MSIC 0 0x1480 2 0 4294967295 BIF_XTALIN_SEL 0 0 BACO_LINK_RST_SEL 1 2 mmBIF_RESET_CNTL 0 0x1486 6 0 4294967295 STRAP_EN 0 0 RST_DONE 1 1 LINK_TRAIN_EN 2 2 STRAP_ALL_VALID 3 3 RECAP_STRAP_WARMRST 8 8 HOLD_LKTRN_WARMRST_DIS 9 9 mmBIF_RFE_CNTL_MISC 0 0x148c 4 0 4294967295 ADAPT_pif0_bu_reg_accessMode 0 0 ADAPT_pif1_bu_reg_accessMode 1 1 ADAPT_pwreg_bu_reg_accessMode 2 2 ADAPT_pciecore0_bu_reg_accessMode 3 3