1043 mmMM_INDEX 0 0x0 2 0 4294967295 MM_OFFSET 0 30 MM_APER 31 31 mmMM_INDEX_HI 0 0x6 1 0 4294967295 MM_OFFSET_HI 0 31 mmMM_DATA 0 0x1 1 0 4294967295 MM_DATA 0 31 mmCC_BIF_BX_FUSESTRAP0 0 0x14d7 1 0 4294967295 STRAP_BIF_PX_CAPABLE 1 1 mmCC_BIF_BX_STRAP2 0 0x152a 0 0 4294967295 mmBIF_MM_INDACCESS_CNTL 0 0x1500 1 0 4294967295 MM_INDACCESS_DIS 1 1 mmBIF_DOORBELL_APER_EN 0 0x1501 1 0 4294967295 BIF_DOORBELL_APER_EN 0 0 mmBUS_CNTL 0 0x1508 14 0 4294967295 BIOS_ROM_WRT_EN 0 0 BIOS_ROM_DIS 1 1 PMI_IO_DIS 2 2 PMI_MEM_DIS 3 3 PMI_BM_DIS 4 4 PMI_INT_DIS 5 5 VGA_REG_COHERENCY_DIS 6 6 VGA_MEM_COHERENCY_DIS 7 7 BIF_ERR_RTR_BKPRESSURE_EN 8 8 SET_AZ_TC 10 12 SET_MC_TC 13 15 ZERO_BE_WR_EN 16 16 ZERO_BE_RD_EN 17 17 RD_STALL_IO_WR 18 18 mmCONFIG_CNTL 0 0x1509 4 0 4294967295 CFG_VGA_RAM_EN 0 0 VGA_DIS 1 1 GENMO_MONO_ADDRESS_B 2 2 GRPH_ADRSEL 3 4 mmCONFIG_MEMSIZE 0 0x150a 1 0 4294967295 CONFIG_MEMSIZE 0 31 mmCONFIG_RESERVED 0 0x1502 1 0 4294967295 CONFIG_RESERVED 0 31 mmBIF_IOV_FUNC_IDENTIFIER 0 0x1503 2 0 4294967295 FUNC_IDENTIFIER 0 0 IOV_ENABLE 31 31 mmCONFIG_F0_BASE 0 0x150b 1 0 4294967295 F0_BASE 0 31 mmCONFIG_APER_SIZE 0 0x150c 1 0 4294967295 APER_SIZE 0 31 mmCONFIG_REG_APER_SIZE 0 0x150d 1 0 4294967295 REG_APER_SIZE 0 19 mmBIF_SCRATCH0 0 0x150e 1 0 4294967295 BIF_SCRATCH0 0 31 mmBIF_SCRATCH1 0 0x150f 1 0 4294967295 BIF_SCRATCH1 0 31 mmBIF_RLC_INTR_CNTL 0 0x1510 2 0 4294967295 RLC_HVCMD_INTERRUPT 0 0 RLC_VM_IDLE_INTERRUPT 8 8 mmBIF_BME_STATUS 0 0x1511 2 0 4294967295 DMA_ON_BME_LOW 0 0 CLEAR_DMA_ON_BME_LOW 16 16 mmBIF_ATOMIC_ERR_LOG 0 0x1512 4 0 4294967295 UR_ATOMIC_OPCODE 0 0 UR_ATOMIC_REQEN_LOW 1 1 CLEAR_UR_ATOMIC_OPCODE 16 16 CLEAR_UR_ATOMIC_REQEN_LOW 17 17 mmBX_RESET_EN 0 0x1514 8 0 4294967295 COR_RESET_EN 0 0 REG_RESET_EN 1 1 STY_RESET_EN 2 2 FLR_TWICE_EN 8 8 FLR_TIMER_SEL 9 10 DB_APER_RESET_EN 15 15 RESET_ON_VFENABLE_LOW_EN 16 16 PF_FLR_NEWHDL_EN 17 17 mmMM_CFGREGS_CNTL 0 0x1513 2 0 4294967295 MM_CFG_FUNC_SEL 0 2 MM_WR_TO_CFG_EN 3 3 mmHW_DEBUG 0 0x1515 32 0 4294967295 HW_00_DEBUG 0 0 HW_01_DEBUG 1 1 HW_02_DEBUG 2 2 HW_03_DEBUG 3 3 HW_04_DEBUG 4 4 HW_05_DEBUG 5 5 HW_06_DEBUG 6 6 HW_07_DEBUG 7 7 HW_08_DEBUG 8 8 HW_09_DEBUG 9 9 HW_10_DEBUG 10 10 HW_11_DEBUG 11 11 HW_12_DEBUG 12 12 HW_13_DEBUG 13 13 HW_14_DEBUG 14 14 HW_15_DEBUG 15 15 HW_16_DEBUG 16 16 HW_17_DEBUG 17 17 HW_18_DEBUG 18 18 HW_19_DEBUG 19 19 HW_20_DEBUG 20 20 HW_21_DEBUG 21 21 HW_22_DEBUG 22 22 HW_23_DEBUG 23 23 HW_24_DEBUG 24 24 HW_25_DEBUG 25 25 HW_26_DEBUG 26 26 HW_27_DEBUG 27 27 HW_28_DEBUG 28 28 HW_29_DEBUG 29 29 HW_30_DEBUG 30 30 HW_31_DEBUG 31 31 mmMASTER_CREDIT_CNTL 0 0x1516 2 0 4294967295 BIF_MC_RDRET_CREDIT 0 6 BIF_AZ_RDRET_CREDIT 16 21 mmSLAVE_REQ_CREDIT_CNTL 0 0x1517 6 0 4294967295 BIF_SRBM_REQ_CREDIT 0 4 BIF_VGA_REQ_CREDIT 5 8 BIF_HDP_REQ_CREDIT 10 14 BIF_ROM_REQ_CREDIT 15 15 BIF_AZ_REQ_CREDIT 20 20 BIF_XDMA_REQ_CREDIT 25 30 mmBX_RESET_CNTL 0 0x1518 1 0 4294967295 LINK_TRAIN_EN 0 0 mmINTERRUPT_CNTL 0 0x151a 8 0 4294967295 IH_DUMMY_RD_OVERRIDE 0 0 IH_DUMMY_RD_EN 1 1 IH_REQ_NONSNOOP_EN 3 3 IH_INTR_DLY_CNTR 4 7 GEN_IH_INT_EN 8 8 GEN_GPIO_INT_EN 9 12 SELECT_INT_GPIO_OUTPUT 13 14 BIF_RB_REQ_NONSNOOP_EN 15 15 mmINTERRUPT_CNTL2 0 0x151b 1 0 4294967295 IH_DUMMY_RD_ADDR 0 31 mmBIF_DEBUG_CNTL 0 0x151c 12 0 4294967295 DEBUG_EN 0 0 DEBUG_MULTIBLOCKEN 1 1 DEBUG_OUT_EN 2 2 DEBUG_PAD_SEL 3 3 DEBUG_BYTESEL_BLK1 4 4 DEBUG_BYTESEL_BLK2 5 5 DEBUG_SYNC_EN 6 6 DEBUG_SWAP 7 7 DEBUG_IDSEL_BLK1 8 12 DEBUG_IDSEL_BLK2 16 20 DEBUG_IDSEL_XSP 24 24 DEBUG_SYNC_CLKSEL 30 31 mmBIF_DEBUG_MUX 0 0x151d 2 0 4294967295 DEBUG_MUX_BLK1 0 5 DEBUG_MUX_BLK2 8 13 mmBIF_DEBUG_OUT 0 0x151e 1 0 4294967295 DEBUG_OUTPUT 0 16 mmHDP_REG_COHERENCY_FLUSH_CNTL 0 0x1528 1 0 4294967295 HDP_REG_FLUSH_ADDR 0 0 mmHDP_MEM_COHERENCY_FLUSH_CNTL 0 0x1520 1 0 4294967295 HDP_MEM_FLUSH_ADDR 0 0 mmCLKREQB_PAD_CNTL 0 0x1521 14 0 4294967295 CLKREQB_PAD_A 0 0 CLKREQB_PAD_SEL 1 1 CLKREQB_PAD_MODE 2 2 CLKREQB_PAD_SPARE 3 4 CLKREQB_PAD_SN0 5 5 CLKREQB_PAD_SN1 6 6 CLKREQB_PAD_SN2 7 7 CLKREQB_PAD_SN3 8 8 CLKREQB_PAD_SLEWN 9 9 CLKREQB_PAD_WAKE 10 10 CLKREQB_PAD_SCHMEN 11 11 CLKREQB_PAD_CNTL_EN 12 12 CLKREQB_PAD_Y 13 13 CLKREQB_PERF_COUNTER_UPPER 24 31 mmCLKREQB_PERF_COUNTER 0 0x1522 1 0 4294967295 CLKREQB_PERF_COUNTER_LOWER 0 31 mmBIF_XDMA_LO 0 0x14c0 2 0 4294967295 BIF_XDMA_LOWER_BOUND 0 28 BIF_XDMA_APER_EN 31 31 mmBIF_XDMA_HI 0 0x14c1 1 0 4294967295 BIF_XDMA_UPPER_BOUND 0 28 mmBIF_FEATURES_CONTROL_MISC 0 0x14c2 24 0 4294967295 MST_BIF_REQ_EP_DIS 0 0 SLV_BIF_CPL_EP_DIS 1 1 BIF_SLV_REQ_EP_DIS 2 2 BIF_MST_CPL_EP_DIS 3 3 UR_PSN_PKT_REPORT_POISON_DIS 4 4 POST_PSN_ONLY_PKT_REPORT_UR_ALL_DIS 5 5 POST_PSN_ONLY_PKT_REPORT_UR_PART_DIS 6 6 PLL_SWITCH_IMPCTL_CAL_DONE_DIS 7 7 IGNORE_BE_CHECK_GASKET_COMB_DIS 8 8 MC_BIF_REQ_ID_ROUTING_DIS 9 9 AZ_BIF_REQ_ID_ROUTING_DIS 10 10 ATC_PRG_RESP_PASID_UR_EN 11 11 BIF_RB_SET_OVERFLOW_EN 12 12 ATOMIC_ERR_INT_DIS 13 13 BME_HDL_NONVIR_EN 15 15 INIT_PFFLR_CRS_RET_DIS 16 16 FLR_MST_PEND_CHK_DIS 17 17 FLR_SLV_PEND_CHK_DIS 18 18 SOFT_PF_FLR_UR_CFG_EN 19 19 FLR_OSTD_UR_DIS 20 20 FLR_OSTD_HDL_DIS 21 21 FLR_NEWREQ_HDL_DIS 22 22 FLR_CRS_CFG_DIS 23 23 DUMMY_TRANS_CPL_RET_DIS 24 24 mmBIF_DOORBELL_CNTL 0 0x14c3 11 0 4294967295 SELF_RING_DIS 0 0 TRANS_CHECK_DIS 1 1 UNTRANS_LBACK_EN 2 2 NON_CONSECUTIVE_BE_ZERO_DIS 3 3 DOORBELL_MONITOR_EN 4 4 DOORBELL_INTERRUPT_STATUS 5 5 DOORBELL_INTERRUPT_CLEAR 16 16 DB_MNTR_INTGEN_DIS 24 24 DB_MNTR_INTGEN_MODE_0 25 25 DB_MNTR_INTGEN_MODE_1 26 26 DB_MNTR_INTGEN_MODE_2 27 27 mmBIF_SLVARB_MODE 0 0x14c4 1 0 4294967295 SLVARB_MODE 0 1 mmBIF_CLK_CTRL 0 0x14c5 2 0 4294967295 BIF_XSTCLK_READY 0 0 BACO_XSTCLK_SWITCH_BYPASS 1 1 mmBIF_FB_EN 0 0x1524 2 0 4294967295 FB_READ_EN 0 0 FB_WRITE_EN 1 1 mmBIF_BUSNUM_CNTL1 0 0x1525 1 0 4294967295 ID_MASK 0 7 mmBIF_BUSNUM_LIST0 0 0x1526 4 0 4294967295 ID0 0 7 ID1 8 15 ID2 16 23 ID3 24 31 mmBIF_BUSNUM_LIST1 0 0x1527 4 0 4294967295 ID4 0 7 ID5 8 15 ID6 16 23 ID7 24 31 mmBIF_BUSNUM_CNTL2 0 0x152b 4 0 4294967295 AUTOUPDATE_SEL 0 7 AUTOUPDATE_EN 8 8 HDPREG_CNTL 16 16 ERROR_MULTIPLE_ID_MATCH 17 17 mmBIF_BUSY_DELAY_CNTR 0 0x1529 1 0 4294967295 DELAY_CNT 0 5 mmBIF_PERFMON_CNTL 0 0x152c 5 0 4294967295 PERFCOUNTER_EN 0 0 PERFCOUNTER_RESET0 1 1 PERFCOUNTER_RESET1 2 2 PERF_SEL0 8 12 PERF_SEL1 13 17 mmBIF_PERFCOUNTER0_RESULT 0 0x152d 1 0 4294967295 PERFCOUNTER_RESULT 0 31 mmBIF_PERFCOUNTER1_RESULT 0 0x152e 1 0 4294967295 PERFCOUNTER_RESULT 0 31 mmSLAVE_HANG_PROTECTION_CNTL 0 0x1536 1 0 4294967295 HANG_PROTECTION_TIMER_SEL 1 3 mmGPU_HDP_FLUSH_REQ 0 0x1537 12 0 4294967295 CP0 0 0 CP1 1 1 CP2 2 2 CP3 3 3 CP4 4 4 CP5 5 5 CP6 6 6 CP7 7 7 CP8 8 8 CP9 9 9 SDMA0 10 10 SDMA1 11 11 mmGPU_HDP_FLUSH_DONE 0 0x1538 12 0 4294967295 CP0 0 0 CP1 1 1 CP2 2 2 CP3 3 3 CP4 4 4 CP5 5 5 CP6 6 6 CP7 7 7 CP8 8 8 CP9 9 9 SDMA0 10 10 SDMA1 11 11 mmSLAVE_HANG_ERROR 0 0x153b 9 0 4294967295 SRBM_HANG_ERROR 0 0 HDP_HANG_ERROR 1 1 VGA_HANG_ERROR 2 2 ROM_HANG_ERROR 3 3 AUDIO_HANG_ERROR 4 4 CEC_HANG_ERROR 5 5 XDMA_HANG_ERROR 7 7 DOORBELL_HANG_ERROR 8 8 GARLIC_HANG_ERROR 9 9 mmCAPTURE_HOST_BUSNUM 0 0x153c 1 0 4294967295 CHECK_EN 0 0 mmHOST_BUSNUM 0 0x153d 1 0 4294967295 HOST_ID 0 15 mmPEER_REG_RANGE0 0 0x153e 2 0 4294967295 START_ADDR 0 15 END_ADDR 16 31 mmPEER_REG_RANGE1 0 0x153f 2 0 4294967295 START_ADDR 0 15 END_ADDR 16 31 mmPEER0_FB_OFFSET_HI 0 0x14f3 1 0 4294967295 PEER0_FB_OFFSET_HI 0 19 mmPEER0_FB_OFFSET_LO 0 0x14f2 2 0 4294967295 PEER0_FB_OFFSET_LO 0 19 PEER0_FB_EN 31 31 mmPEER1_FB_OFFSET_HI 0 0x14f1 1 0 4294967295 PEER1_FB_OFFSET_HI 0 19 mmPEER1_FB_OFFSET_LO 0 0x14f0 2 0 4294967295 PEER1_FB_OFFSET_LO 0 19 PEER1_FB_EN 31 31 mmPEER2_FB_OFFSET_HI 0 0x14ef 1 0 4294967295 PEER2_FB_OFFSET_HI 0 19 mmPEER2_FB_OFFSET_LO 0 0x14ee 2 0 4294967295 PEER2_FB_OFFSET_LO 0 19 PEER2_FB_EN 31 31 mmPEER3_FB_OFFSET_HI 0 0x14ed 1 0 4294967295 PEER3_FB_OFFSET_HI 0 19 mmPEER3_FB_OFFSET_LO 0 0x14ec 2 0 4294967295 PEER3_FB_OFFSET_LO 0 19 PEER3_FB_EN 31 31 mmDBG_SMB_BYPASS_SRBM_ACCESS 0 0x14eb 1 0 4294967295 DBG_SMB_BYPASS_SRBM_EN 0 0 mmBIF_MST_TRANS_PENDING 0 0x14ea 1 0 4294967295 BIF_MST_TRANS_PENDING 0 31 mmBIF_SLV_TRANS_PENDING 0 0x14e9 1 0 4294967295 BIF_SLV_TRANS_PENDING 0 31 mmBIF_DEVFUNCNUM_LIST0 0 0x14e8 4 0 4294967295 DEVFUNC_ID0 0 7 DEVFUNC_ID1 8 15 DEVFUNC_ID2 16 23 DEVFUNC_ID3 24 31 mmBIF_DEVFUNCNUM_LIST1 0 0x14e7 4 0 4294967295 DEVFUNC_ID4 0 7 DEVFUNC_ID5 8 15 DEVFUNC_ID6 16 23 DEVFUNC_ID7 24 31 mmBACO_CNTL 0 0x14e5 17 0 4294967295 BACO_EN 0 0 BACO_BCLK_OFF 1 1 BACO_ISO_DIS 2 2 BACO_POWER_OFF 3 3 BACO_RESET_EN 4 4 BACO_HANG_PROTECTION_EN 5 5 BACO_MODE 6 6 BACO_ANA_ISO_DIS 7 7 RCU_BIF_CONFIG_DONE 8 8 PWRGOOD_BF 9 9 PWRGOOD_GPIO 10 10 PWRGOOD_MEM 11 11 PWRGOOD_DVO 12 12 PWRGOOD_IDSC 13 13 BACO_POWER_OFF_DRAM 16 16 BACO_BF_MEM_PHY_ISO_CNTRL 17 17 BACO_BIF_SCLK_SWITCH 18 18 mmBF_ANA_ISO_CNTL 0 0x14c7 2 0 4294967295 BF_ANA_ISO_DIS_MASK 0 0 BF_VDDC_ISO_DIS_MASK 1 1 mmMEM_TYPE_CNTL 0 0x14e4 1 0 4294967295 BF_MEM_PHY_G5_G3 0 0 mmBIF_BACO_DEBUG 0 0x14df 1 0 4294967295 BIF_BACO_SCANDUMP_FLG 0 0 mmBIF_BACO_DEBUG_LATCH 0 0x14dc 1 0 4294967295 BIF_BACO_LATCH_FLG 0 0 mmBACO_CNTL_MISC 0 0x14db 4 0 4294967295 BIF_ROM_REQ_DIS 0 0 BIF_AZ_REQ_DIS 1 1 BACO_LINK_RST_WIDTH_SEL 2 3 BACO_REFCLK_SEL 4 4 mmSMU_BIF_VDDGFX_PWR_STATUS 0 0x14f8 1 0 4294967295 VDDGFX_GFX_PWR_OFF 0 0 mmBIF_VDDGFX_GFX0_LOWER 0 0x1428 3 0 4294967295 VDDGFX_GFX0_REG_LOWER 2 17 VDDGFX_GFX0_REG_CMP_EN 30 30 VDDGFX_GFX0_REG_STALL_EN 31 31 mmBIF_VDDGFX_GFX0_UPPER 0 0x1429 1 0 4294967295 VDDGFX_GFX0_REG_UPPER 2 17 mmBIF_VDDGFX_GFX1_LOWER 0 0x142a 3 0 4294967295 VDDGFX_GFX1_REG_LOWER 2 17 VDDGFX_GFX1_REG_CMP_EN 30 30 VDDGFX_GFX1_REG_STALL_EN 31 31 mmBIF_VDDGFX_GFX1_UPPER 0 0x142b 1 0 4294967295 VDDGFX_GFX1_REG_UPPER 2 17 mmBIF_VDDGFX_GFX2_LOWER 0 0x142c 3 0 4294967295 VDDGFX_GFX2_REG_LOWER 2 17 VDDGFX_GFX2_REG_CMP_EN 30 30 VDDGFX_GFX2_REG_STALL_EN 31 31 mmBIF_VDDGFX_GFX2_UPPER 0 0x142d 1 0 4294967295 VDDGFX_GFX2_REG_UPPER 2 17 mmBIF_VDDGFX_GFX3_LOWER 0 0x142e 3 0 4294967295 VDDGFX_GFX3_REG_LOWER 2 17 VDDGFX_GFX3_REG_CMP_EN 30 30 VDDGFX_GFX3_REG_STALL_EN 31 31 mmBIF_VDDGFX_GFX3_UPPER 0 0x142f 1 0 4294967295 VDDGFX_GFX3_REG_UPPER 2 17 mmBIF_VDDGFX_GFX4_LOWER 0 0x1430 3 0 4294967295 VDDGFX_GFX4_REG_LOWER 2 17 VDDGFX_GFX4_REG_CMP_EN 30 30 VDDGFX_GFX4_REG_STALL_EN 31 31 mmBIF_VDDGFX_GFX4_UPPER 0 0x1431 1 0 4294967295 VDDGFX_GFX4_REG_UPPER 2 17 mmBIF_VDDGFX_GFX5_LOWER 0 0x1432 3 0 4294967295 VDDGFX_GFX5_REG_LOWER 2 17 VDDGFX_GFX5_REG_CMP_EN 30 30 VDDGFX_GFX5_REG_STALL_EN 31 31 mmBIF_VDDGFX_GFX5_UPPER 0 0x1433 1 0 4294967295 VDDGFX_GFX5_REG_UPPER 2 17 mmBIF_VDDGFX_RSV1_LOWER 0 0x1434 3 0 4294967295 VDDGFX_RSV1_REG_LOWER 2 17 VDDGFX_RSV1_REG_CMP_EN 30 30 VDDGFX_RSV1_REG_STALL_EN 31 31 mmBIF_VDDGFX_RSV1_UPPER 0 0x1435 1 0 4294967295 VDDGFX_RSV1_REG_UPPER 2 17 mmBIF_VDDGFX_RSV2_LOWER 0 0x1436 3 0 4294967295 VDDGFX_RSV2_REG_LOWER 2 17 VDDGFX_RSV2_REG_CMP_EN 30 30 VDDGFX_RSV2_REG_STALL_EN 31 31 mmBIF_VDDGFX_RSV2_UPPER 0 0x1437 1 0 4294967295 VDDGFX_RSV2_REG_UPPER 2 17 mmBIF_VDDGFX_RSV3_LOWER 0 0x1438 3 0 4294967295 VDDGFX_RSV3_REG_LOWER 2 17 VDDGFX_RSV3_REG_CMP_EN 30 30 VDDGFX_RSV3_REG_STALL_EN 31 31 mmBIF_VDDGFX_RSV3_UPPER 0 0x1439 1 0 4294967295 VDDGFX_RSV3_REG_UPPER 2 17 mmBIF_VDDGFX_RSV4_LOWER 0 0x143a 3 0 4294967295 VDDGFX_RSV4_REG_LOWER 2 17 VDDGFX_RSV4_REG_CMP_EN 30 30 VDDGFX_RSV4_REG_STALL_EN 31 31 mmBIF_VDDGFX_RSV4_UPPER 0 0x143b 1 0 4294967295 VDDGFX_RSV4_REG_UPPER 2 17 mmBIF_VDDGFX_FB_CMP 0 0x143c 6 0 4294967295 VDDGFX_FB_HDP_CMP_EN 0 0 VDDGFX_FB_HDP_STALL_EN 1 1 VDDGFX_FB_XDMA_CMP_EN 2 2 VDDGFX_FB_XDMA_STALL_EN 3 3 VDDGFX_FB_VGA_CMP_EN 4 4 VDDGFX_FB_VGA_STALL_EN 5 5 mmBIF_SMU_INDEX 0 0x143d 1 0 4294967295 BIF_SMU_INDEX 2 18 mmBIF_SMU_DATA 0 0x143e 1 0 4294967295 BIF_SMU_DATA 2 18 mmBIF_DOORBELL_GBLAPER1_LOWER 0 0x14fc 2 0 4294967295 DOORBELL_GBLAPER1_LOWER 2 11 DOORBELL_GBLAPER1_EN 31 31 mmBIF_DOORBELL_GBLAPER1_UPPER 0 0x14fd 1 0 4294967295 DOORBELL_GBLAPER1_UPPER 2 11 mmBIF_DOORBELL_GBLAPER2_LOWER 0 0x14fe 2 0 4294967295 DOORBELL_GBLAPER2_LOWER 2 11 DOORBELL_GBLAPER2_EN 31 31 mmBIF_DOORBELL_GBLAPER2_UPPER 0 0x14ff 1 0 4294967295 DOORBELL_GBLAPER2_UPPER 2 11 mmIMPCTL_RESET 0 0x14f5 1 0 4294967295 IMP_SW_RESET 0 0 mmGARLIC_FLUSH_CNTL 0 0x1401 21 0 4294967295 CP_RB0_WPTR 0 0 CP_RB1_WPTR 1 1 CP_RB2_WPTR 2 2 UVD_RBC_RB_WPTR 3 3 SDMA0_GFX_RB_WPTR 4 4 SDMA1_GFX_RB_WPTR 5 5 CP_DMA_ME_COMMAND 6 6 CP_DMA_PFP_COMMAND 7 7 SAM_SAB_RBI_WPTR 8 8 SAM_SAB_RBO_WPTR 9 9 VCE_OUT_RB_WPTR 10 10 VCE_RB_WPTR2 11 11 VCE_RB_WPTR 12 12 HOST_DOORBELL 13 13 SELFRING_DOORBELL 14 14 CP_DMA_PIO_COMMAND 15 15 DISPLAY 16 16 SDMA2_GFX_RB_WPTR 17 17 SDMA3_GFX_RB_WPTR 18 18 IGNORE_MC_DISABLE 30 30 DISABLE_ALL 31 31 mmGARLIC_FLUSH_ADDR_START_0 0 0x1402 3 0 4294967295 ENABLE 0 0 MODE 1 1 ADDR_START 2 31 mmGARLIC_FLUSH_ADDR_START_1 0 0x1404 3 0 4294967295 ENABLE 0 0 MODE 1 1 ADDR_START 2 31 mmGARLIC_FLUSH_ADDR_START_2 0 0x1406 3 0 4294967295 ENABLE 0 0 MODE 1 1 ADDR_START 2 31 mmGARLIC_FLUSH_ADDR_START_3 0 0x1408 3 0 4294967295 ENABLE 0 0 MODE 1 1 ADDR_START 2 31 mmGARLIC_FLUSH_ADDR_START_4 0 0x140a 3 0 4294967295 ENABLE 0 0 MODE 1 1 ADDR_START 2 31 mmGARLIC_FLUSH_ADDR_START_5 0 0x140c 3 0 4294967295 ENABLE 0 0 MODE 1 1 ADDR_START 2 31 mmGARLIC_FLUSH_ADDR_START_6 0 0x140e 3 0 4294967295 ENABLE 0 0 MODE 1 1 ADDR_START 2 31 mmGARLIC_FLUSH_ADDR_START_7 0 0x1410 3 0 4294967295 ENABLE 0 0 MODE 1 1 ADDR_START 2 31 mmGARLIC_FLUSH_ADDR_END_0 0 0x1403 1 0 4294967295 ADDR_END 2 31 mmGARLIC_FLUSH_ADDR_END_1 0 0x1405 1 0 4294967295 ADDR_END 2 31 mmGARLIC_FLUSH_ADDR_END_2 0 0x1407 1 0 4294967295 ADDR_END 2 31 mmGARLIC_FLUSH_ADDR_END_3 0 0x1409 1 0 4294967295 ADDR_END 2 31 mmGARLIC_FLUSH_ADDR_END_4 0 0x140b 1 0 4294967295 ADDR_END 2 31 mmGARLIC_FLUSH_ADDR_END_5 0 0x140d 1 0 4294967295 ADDR_END 2 31 mmGARLIC_FLUSH_ADDR_END_6 0 0x140f 1 0 4294967295 ADDR_END 2 31 mmGARLIC_FLUSH_ADDR_END_7 0 0x1411 1 0 4294967295 ADDR_END 2 31 mmGARLIC_FLUSH_REQ 0 0x1412 1 0 4294967295 FLUSH_REQ 0 0 mmGPU_GARLIC_FLUSH_REQ 0 0x1413 14 0 4294967295 CP0 0 0 CP1 1 1 CP2 2 2 CP3 3 3 CP4 4 4 CP5 5 5 CP6 6 6 CP7 7 7 CP8 8 8 CP9 9 9 SDMA0 10 10 SDMA1 11 11 SDMA2 12 12 SDMA3 13 13 mmGPU_GARLIC_FLUSH_DONE 0 0x1414 14 0 4294967295 CP0 0 0 CP1 1 1 CP2 2 2 CP3 3 3 CP4 4 4 CP5 5 5 CP6 6 6 CP7 7 7 CP8 8 8 CP9 9 9 SDMA0 10 10 SDMA1 11 11 SDMA2 12 12 SDMA3 13 13 mmREMAP_HDP_MEM_FLUSH_CNTL 0 0x1426 1 0 4294967295 ADDRESS 2 18 mmREMAP_HDP_REG_FLUSH_CNTL 0 0x1427 1 0 4294967295 ADDRESS 2 18 mmBIOS_SCRATCH_0 0 0x5c9 1 0 4294967295 BIOS_SCRATCH_0 0 31 mmBIOS_SCRATCH_1 0 0x5ca 1 0 4294967295 BIOS_SCRATCH_1 0 31 mmBIOS_SCRATCH_2 0 0x5cb 1 0 4294967295 BIOS_SCRATCH_2 0 31 mmBIOS_SCRATCH_3 0 0x5cc 1 0 4294967295 BIOS_SCRATCH_3 0 31 mmBIOS_SCRATCH_4 0 0x5cd 1 0 4294967295 BIOS_SCRATCH_4 0 31 mmBIOS_SCRATCH_5 0 0x5ce 1 0 4294967295 BIOS_SCRATCH_5 0 31 mmBIOS_SCRATCH_6 0 0x5cf 1 0 4294967295 BIOS_SCRATCH_6 0 31 mmBIOS_SCRATCH_7 0 0x5d0 1 0 4294967295 BIOS_SCRATCH_7 0 31 mmBIOS_SCRATCH_8 0 0x5d1 1 0 4294967295 BIOS_SCRATCH_8 0 31 mmBIOS_SCRATCH_9 0 0x5d2 1 0 4294967295 BIOS_SCRATCH_9 0 31 mmBIOS_SCRATCH_10 0 0x5d3 1 0 4294967295 BIOS_SCRATCH_10 0 31 mmBIOS_SCRATCH_11 0 0x5d4 1 0 4294967295 BIOS_SCRATCH_11 0 31 mmBIOS_SCRATCH_12 0 0x5d5 1 0 4294967295 BIOS_SCRATCH_12 0 31 mmBIOS_SCRATCH_13 0 0x5d6 1 0 4294967295 BIOS_SCRATCH_13 0 31 mmBIOS_SCRATCH_14 0 0x5d7 1 0 4294967295 BIOS_SCRATCH_14 0 31 mmBIOS_SCRATCH_15 0 0x5d8 1 0 4294967295 BIOS_SCRATCH_15 0 31 mmBIF_RB_CNTL 0 0x1530 6 0 4294967295 RB_ENABLE 0 0 RB_SIZE 1 5 WPTR_WRITEBACK_ENABLE 8 8 WPTR_WRITEBACK_TIMER 9 13 BIF_RB_TRAN 17 17 WPTR_OVERFLOW_CLEAR 31 31 mmBIF_RB_BASE 0 0x1531 1 0 4294967295 ADDR 0 31 mmBIF_RB_RPTR 0 0x1532 1 0 4294967295 OFFSET 2 17 mmBIF_RB_WPTR 0 0x1533 2 0 4294967295 BIF_RB_OVERFLOW 0 0 OFFSET 2 17 mmBIF_RB_WPTR_ADDR_HI 0 0x1534 1 0 4294967295 ADDR 0 7 mmBIF_RB_WPTR_ADDR_LO 0 0x1535 1 0 4294967295 ADDR 2 31 mmMAILBOX_INDEX 0 0x14c6 1 0 4294967295 MAILBOX_INDEX 0 3 mmMAILBOX_MSGBUF_TRN_DW0 0 0x14c8 1 0 4294967295 MSGBUF_DATA 0 31 mmMAILBOX_MSGBUF_TRN_DW1 0 0x14c9 1 0 4294967295 MSGBUF_DATA 0 31 mmMAILBOX_MSGBUF_TRN_DW2 0 0x14ca 1 0 4294967295 MSGBUF_DATA 0 31 mmMAILBOX_MSGBUF_TRN_DW3 0 0x14cb 1 0 4294967295 MSGBUF_DATA 0 31 mmMAILBOX_MSGBUF_RCV_DW0 0 0x14cc 1 0 4294967295 MSGBUF_DATA 0 31 mmMAILBOX_MSGBUF_RCV_DW1 0 0x14cd 1 0 4294967295 MSGBUF_DATA 0 31 mmMAILBOX_MSGBUF_RCV_DW2 0 0x14ce 1 0 4294967295 MSGBUF_DATA 0 31 mmMAILBOX_MSGBUF_RCV_DW3 0 0x14cf 1 0 4294967295 MSGBUF_DATA 0 31 mmMAILBOX_CONTROL 0 0x14d0 4 0 4294967295 TRN_MSG_VALID 0 0 TRN_MSG_ACK 1 1 RCV_MSG_VALID 8 8 RCV_MSG_ACK 9 9 mmMAILBOX_INT_CNTL 0 0x14d1 2 0 4294967295 VALID_INT_EN 0 0 ACK_INT_EN 1 1 mmBIF_VIRT_RESET_REQ 0 0x14d2 2 0 4294967295 VIRT_RESET_REQ_VF 0 15 VIRT_RESET_REQ_SOFTPF 31 31 mmVM_INIT_STATUS 0 0x14d3 1 0 4294967295 VM_INIT_STATUS 0 0 mmBIF_GPUIOV_RESET_NOTIFICATION 0 0x14d5 1 0 4294967295 RESET_NOTIFICATION 0 31 mmBIF_GPUIOV_VM_INIT_STATUS 0 0x14d6 1 0 4294967295 VM_INIT_STATUS 0 31 mmBIF_GPUIOV_FB_TOTAL_FB_INFO 0 0x14d8 2 0 4294967295 TOTAL_FB_AVAILABLE 0 15 TOTAL_FB_CONSUMED 16 31 mmBIF_GPUIOV_GPU_IDLE_LATENCY 0 0x141c 1 0 4294967295 GPU_IDLE_LATENCY 0 31 mmBIF_GPUIOV_MMIO_MAP_RANGE0 0 0x141d 2 0 4294967295 MMIO_MAP_RANGE0_LOWER 0 15 MMIO_MAP_RANGE0_UPPER 16 31 mmBIF_GPUIOV_MMIO_MAP_RANGE1 0 0x141e 2 0 4294967295 MMIO_MAP_RANGE1_LOWER 0 15 MMIO_MAP_RANGE1_UPPER 16 31 mmBIF_GPUIOV_MMIO_MAP_RANGE2 0 0x141f 2 0 4294967295 MMIO_MAP_RANGE2_LOWER 0 15 MMIO_MAP_RANGE2_UPPER 16 31 mmBIF_GPUIOV_MMIO_MAP_RANGE3 0 0x1420 2 0 4294967295 MMIO_MAP_RANGE3_LOWER 0 15 MMIO_MAP_RANGE3_UPPER 16 31 mmBIF_GPUIOV_MMIO_MAP_RANGE4 0 0x1421 2 0 4294967295 MMIO_MAP_RANGE4_LOWER 0 15 MMIO_MAP_RANGE4_UPPER 16 31 mmBIF_GPUIOV_MMIO_MAP_RANGE5 0 0x1422 2 0 4294967295 MMIO_MAP_RANGE5_LOWER 0 15 MMIO_MAP_RANGE5_UPPER 16 31 mmBIF_GPU_IDLE_LATENCY 0 0x1415 1 0 4294967295 GPU_IDLE_LATENCY 0 31 mmBIF_MMIO_MAP_RANGE0 0 0x1416 2 0 4294967295 MMIO_MAP_RANGE0_LOWER 0 15 MMIO_MAP_RANGE0_UPPER 16 31 mmBIF_MMIO_MAP_RANGE1 0 0x1417 2 0 4294967295 MMIO_MAP_RANGE1_LOWER 0 15 MMIO_MAP_RANGE1_UPPER 16 31 mmBIF_MMIO_MAP_RANGE2 0 0x1418 2 0 4294967295 MMIO_MAP_RANGE2_LOWER 0 15 MMIO_MAP_RANGE2_UPPER 16 31 mmBIF_MMIO_MAP_RANGE3 0 0x1419 2 0 4294967295 MMIO_MAP_RANGE3_LOWER 0 15 MMIO_MAP_RANGE3_UPPER 16 31 mmBIF_MMIO_MAP_RANGE4 0 0x141a 2 0 4294967295 MMIO_MAP_RANGE4_LOWER 0 15 MMIO_MAP_RANGE4_UPPER 16 31 mmBIF_MMIO_MAP_RANGE5 0 0x141b 2 0 4294967295 MMIO_MAP_RANGE5_LOWER 0 15 MMIO_MAP_RANGE5_UPPER 16 31 mmVENDOR_ID 0 0x0 1 0 4294967295 VENDOR_ID 0 15 mmDEVICE_ID 0 0x0 1 0 4294967295 DEVICE_ID 0 15 mmCOMMAND 0 0x1 11 0 4294967295 IO_ACCESS_EN 0 0 MEM_ACCESS_EN 1 1 BUS_MASTER_EN 2 2 SPECIAL_CYCLE_EN 3 3 MEM_WRITE_INVALIDATE_EN 4 4 PAL_SNOOP_EN 5 5 PARITY_ERROR_RESPONSE 6 6 AD_STEPPING 7 7 SERR_EN 8 8 FAST_B2B_EN 9 9 INT_DIS 10 10 mmSTATUS 0 0x1 11 0 4294967295 INT_STATUS 3 3 CAP_LIST 4 4 PCI_66_EN 5 5 FAST_BACK_CAPABLE 7 7 MASTER_DATA_PARITY_ERROR 8 8 DEVSEL_TIMING 9 10 SIGNAL_TARGET_ABORT 11 11 RECEIVED_TARGET_ABORT 12 12 RECEIVED_MASTER_ABORT 13 13 SIGNALED_SYSTEM_ERROR 14 14 PARITY_ERROR_DETECTED 15 15 mmREVISION_ID 0 0x2 2 0 4294967295 MINOR_REV_ID 0 3 MAJOR_REV_ID 4 7 mmPROG_INTERFACE 0 0x2 1 0 4294967295 PROG_INTERFACE 0 7 mmSUB_CLASS 0 0x2 1 0 4294967295 SUB_CLASS 0 7 mmBASE_CLASS 0 0x2 1 0 4294967295 BASE_CLASS 0 7 mmCACHE_LINE 0 0x3 1 0 4294967295 CACHE_LINE_SIZE 0 7 mmLATENCY 0 0x3 1 0 4294967295 LATENCY_TIMER 0 7 mmHEADER 0 0x3 2 0 4294967295 HEADER_TYPE 0 6 DEVICE_TYPE 7 7 mmBIST 0 0x3 3 0 4294967295 BIST_COMP 0 3 BIST_STRT 6 6 BIST_CAP 7 7 mmBASE_ADDR_1 0 0x4 1 0 4294967295 BASE_ADDR 0 31 mmBASE_ADDR_2 0 0x5 1 0 4294967295 BASE_ADDR 0 31 mmBASE_ADDR_3 0 0x6 1 0 4294967295 BASE_ADDR 0 31 mmBASE_ADDR_4 0 0x7 1 0 4294967295 BASE_ADDR 0 31 mmBASE_ADDR_5 0 0x8 1 0 4294967295 BASE_ADDR 0 31 mmBASE_ADDR_6 0 0x9 1 0 4294967295 BASE_ADDR 0 31 mmROM_BASE_ADDR 0 0xc 1 0 4294967295 BASE_ADDR 0 31 mmCAP_PTR 0 0xd 1 0 4294967295 CAP_PTR 0 7 mmINTERRUPT_LINE 0 0xf 1 0 4294967295 INTERRUPT_LINE 0 7 mmINTERRUPT_PIN 0 0xf 1 0 4294967295 INTERRUPT_PIN 0 7 mmADAPTER_ID 0 0xb 2 0 4294967295 SUBSYSTEM_VENDOR_ID 0 15 SUBSYSTEM_ID 16 31 mmMIN_GRANT 0 0xf 1 0 4294967295 MIN_GNT 0 7 mmMAX_LATENCY 0 0xf 1 0 4294967295 MAX_LAT 0 7 mmVENDOR_CAP_LIST 0 0x12 3 0 4294967295 CAP_ID 0 7 NEXT_PTR 8 15 LENGTH 16 23 mmADAPTER_ID_W 0 0x13 2 0 4294967295 SUBSYSTEM_VENDOR_ID 0 15 SUBSYSTEM_ID 16 31 mmPMI_CAP_LIST 0 0x14 2 0 4294967295 CAP_ID 0 7 NEXT_PTR 8 15 mmPMI_CAP 0 0x14 7 0 4294967295 VERSION 0 2 PME_CLOCK 3 3 DEV_SPECIFIC_INIT 5 5 AUX_CURRENT 6 8 D1_SUPPORT 9 9 D2_SUPPORT 10 10 PME_SUPPORT 11 15 mmPMI_STATUS_CNTL 0 0x15 9 0 4294967295 POWER_STATE 0 1 NO_SOFT_RESET 3 3 PME_EN 8 8 DATA_SELECT 9 12 DATA_SCALE 13 14 PME_STATUS 15 15 B2_B3_SUPPORT 22 22 BUS_PWR_EN 23 23 PMI_DATA 24 31 mmPCIE_CAP_LIST 0 0x16 2 0 4294967295 CAP_ID 0 7 NEXT_PTR 8 15 mmPCIE_CAP 0 0x16 4 0 4294967295 VERSION 0 3 DEVICE_TYPE 4 7 SLOT_IMPLEMENTED 8 8 INT_MESSAGE_NUM 9 13 mmDEVICE_CAP 0 0x17 9 0 4294967295 MAX_PAYLOAD_SUPPORT 0 2 PHANTOM_FUNC 3 4 EXTENDED_TAG 5 5 L0S_ACCEPTABLE_LATENCY 6 8 L1_ACCEPTABLE_LATENCY 9 11 ROLE_BASED_ERR_REPORTING 15 15 CAPTURED_SLOT_POWER_LIMIT 18 25 CAPTURED_SLOT_POWER_SCALE 26 27 FLR_CAPABLE 28 28 mmDEVICE_CNTL 0 0x18 12 0 4294967295 CORR_ERR_EN 0 0 NON_FATAL_ERR_EN 1 1 FATAL_ERR_EN 2 2 USR_REPORT_EN 3 3 RELAXED_ORD_EN 4 4 MAX_PAYLOAD_SIZE 5 7 EXTENDED_TAG_EN 8 8 PHANTOM_FUNC_EN 9 9 AUX_POWER_PM_EN 10 10 NO_SNOOP_EN 11 11 MAX_READ_REQUEST_SIZE 12 14 INITIATE_FLR 15 15 mmDEVICE_STATUS 0 0x18 6 0 4294967295 CORR_ERR 0 0 NON_FATAL_ERR 1 1 FATAL_ERR 2 2 USR_DETECTED 3 3 AUX_PWR 4 4 TRANSACTIONS_PEND 5 5 mmLINK_CAP 0 0x19 11 0 4294967295 LINK_SPEED 0 3 LINK_WIDTH 4 9 PM_SUPPORT 10 11 L0S_EXIT_LATENCY 12 14 L1_EXIT_LATENCY 15 17 CLOCK_POWER_MANAGEMENT 18 18 SURPRISE_DOWN_ERR_REPORTING 19 19 DL_ACTIVE_REPORTING_CAPABLE 20 20 LINK_BW_NOTIFICATION_CAP 21 21 ASPM_OPTIONALITY_COMPLIANCE 22 22 PORT_NUMBER 24 31 mmLINK_CNTL 0 0x1a 10 0 4294967295 PM_CONTROL 0 1 READ_CPL_BOUNDARY 3 3 LINK_DIS 4 4 RETRAIN_LINK 5 5 COMMON_CLOCK_CFG 6 6 EXTENDED_SYNC 7 7 CLOCK_POWER_MANAGEMENT_EN 8 8 HW_AUTONOMOUS_WIDTH_DISABLE 9 9 LINK_BW_MANAGEMENT_INT_EN 10 10 LINK_AUTONOMOUS_BW_INT_EN 11 11 mmLINK_STATUS 0 0x1a 7 0 4294967295 CURRENT_LINK_SPEED 0 3 NEGOTIATED_LINK_WIDTH 4 9 LINK_TRAINING 11 11 SLOT_CLOCK_CFG 12 12 DL_ACTIVE 13 13 LINK_BW_MANAGEMENT_STATUS 14 14 LINK_AUTONOMOUS_BW_STATUS 15 15 mmDEVICE_CAP2 0 0x1f 14 0 4294967295 CPL_TIMEOUT_RANGE_SUPPORTED 0 3 CPL_TIMEOUT_DIS_SUPPORTED 4 4 ARI_FORWARDING_SUPPORTED 5 5 ATOMICOP_ROUTING_SUPPORTED 6 6 ATOMICOP_32CMPLT_SUPPORTED 7 7 ATOMICOP_64CMPLT_SUPPORTED 8 8 CAS128_CMPLT_SUPPORTED 9 9 NO_RO_ENABLED_P2P_PASSING 10 10 LTR_SUPPORTED 11 11 TPH_CPLR_SUPPORTED 12 13 OBFF_SUPPORTED 18 19 EXTENDED_FMT_FIELD_SUPPORTED 20 20 END_END_TLP_PREFIX_SUPPORTED 21 21 MAX_END_END_TLP_PREFIXES 22 23 mmDEVICE_CNTL2 0 0x20 10 0 4294967295 CPL_TIMEOUT_VALUE 0 3 CPL_TIMEOUT_DIS 4 4 ARI_FORWARDING_EN 5 5 ATOMICOP_REQUEST_EN 6 6 ATOMICOP_EGRESS_BLOCKING 7 7 IDO_REQUEST_ENABLE 8 8 IDO_COMPLETION_ENABLE 9 9 LTR_EN 10 10 OBFF_EN 13 14 END_END_TLP_PREFIX_BLOCKING 15 15 mmDEVICE_STATUS2 0 0x20 1 0 4294967295 RESERVED 0 15 mmLINK_CAP2 0 0x21 3 0 4294967295 SUPPORTED_LINK_SPEED 1 7 CROSSLINK_SUPPORTED 8 8 RESERVED 9 31 mmLINK_CNTL2 0 0x22 8 0 4294967295 TARGET_LINK_SPEED 0 3 ENTER_COMPLIANCE 4 4 HW_AUTONOMOUS_SPEED_DISABLE 5 5 SELECTABLE_DEEMPHASIS 6 6 XMIT_MARGIN 7 9 ENTER_MOD_COMPLIANCE 10 10 COMPLIANCE_SOS 11 11 COMPLIANCE_DEEMPHASIS 12 15 mmLINK_STATUS2 0 0x22 6 0 4294967295 CUR_DEEMPHASIS_LEVEL 0 0 EQUALIZATION_COMPLETE 1 1 EQUALIZATION_PHASE1_SUCCESS 2 2 EQUALIZATION_PHASE2_SUCCESS 3 3 EQUALIZATION_PHASE3_SUCCESS 4 4 LINK_EQUALIZATION_REQUEST 5 5 mmMSI_CAP_LIST 0 0x28 2 0 4294967295 CAP_ID 0 7 NEXT_PTR 8 15 mmMSI_MSG_CNTL 0 0x28 5 0 4294967295 MSI_EN 0 0 MSI_MULTI_CAP 1 3 MSI_MULTI_EN 4 6 MSI_64BIT 7 7 MSI_PERVECTOR_MASKING_CAP 8 8 mmMSI_MSG_ADDR_LO 0 0x29 1 0 4294967295 MSI_MSG_ADDR_LO 2 31 mmMSI_MSG_ADDR_HI 0 0x2a 1 0 4294967295 MSI_MSG_ADDR_HI 0 31 mmMSI_MSG_DATA_64 0 0x2b 1 0 4294967295 MSI_DATA_64 0 15 mmMSI_MSG_DATA 0 0x2a 1 0 4294967295 MSI_DATA 0 15 mmMSI_MASK 0 0x2b 1 0 4294967295 MSI_MASK 0 31 mmMSI_PENDING 0 0x2c 1 0 4294967295 MSI_PENDING 0 31 mmMSI_MASK_64 0 0x2c 1 0 4294967295 MSI_MASK_64 0 31 mmMSI_PENDING_64 0 0x2d 1 0 4294967295 MSI_PENDING_64 0 31 mmMSIX_CAP_LIST 0 0x30 2 0 4294967295 CAP_ID 0 7 NEXT_PTR 8 15 mmMSIX_MSG_CNTL 0 0x30 3 0 4294967295 MSIX_TABLE_SIZE 0 10 MSIX_FUNC_MASK 14 14 MSIX_EN 15 15 mmMSIX_TABLE 0 0x31 2 0 4294967295 MSIX_TABLE_BIR 0 2 MSIX_TABLE_OFFSET 3 31 mmMSIX_PBA 0 0x32 2 0 4294967295 MSIX_PBA_BIR 0 2 MSIX_PBA_OFFSET 3 31 mmPCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0 0x40 3 0 4294967295 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 mmPCIE_VENDOR_SPECIFIC_HDR 0 0x41 3 0 4294967295 VSEC_ID 0 15 VSEC_REV 16 19 VSEC_LENGTH 20 31 mmPCIE_VENDOR_SPECIFIC1 0 0x42 1 0 4294967295 SCRATCH 0 31 mmPCIE_VENDOR_SPECIFIC2 0 0x43 1 0 4294967295 SCRATCH 0 31 mmPCIE_VC_ENH_CAP_LIST 0 0x44 3 0 4294967295 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 mmPCIE_PORT_VC_CAP_REG1 0 0x45 4 0 4294967295 EXT_VC_COUNT 0 2 LOW_PRIORITY_EXT_VC_COUNT 4 6 REF_CLK 8 9 PORT_ARB_TABLE_ENTRY_SIZE 10 11 mmPCIE_PORT_VC_CAP_REG2 0 0x46 2 0 4294967295 VC_ARB_CAP 0 7 VC_ARB_TABLE_OFFSET 24 31 mmPCIE_PORT_VC_CNTL 0 0x47 2 0 4294967295 LOAD_VC_ARB_TABLE 0 0 VC_ARB_SELECT 1 3 mmPCIE_PORT_VC_STATUS 0 0x47 1 0 4294967295 VC_ARB_TABLE_STATUS 0 0 mmPCIE_VC0_RESOURCE_CAP 0 0x48 4 0 4294967295 PORT_ARB_CAP 0 7 REJECT_SNOOP_TRANS 15 15 MAX_TIME_SLOTS 16 21 PORT_ARB_TABLE_OFFSET 24 31 mmPCIE_VC0_RESOURCE_CNTL 0 0x49 6 0 4294967295 TC_VC_MAP_TC0 0 0 TC_VC_MAP_TC1_7 1 7 LOAD_PORT_ARB_TABLE 16 16 PORT_ARB_SELECT 17 19 VC_ID 24 26 VC_ENABLE 31 31 mmPCIE_VC0_RESOURCE_STATUS 0 0x4a 2 0 4294967295 PORT_ARB_TABLE_STATUS 0 0 VC_NEGOTIATION_PENDING 1 1 mmPCIE_VC1_RESOURCE_CAP 0 0x4b 4 0 4294967295 PORT_ARB_CAP 0 7 REJECT_SNOOP_TRANS 15 15 MAX_TIME_SLOTS 16 21 PORT_ARB_TABLE_OFFSET 24 31 mmPCIE_VC1_RESOURCE_CNTL 0 0x4c 6 0 4294967295 TC_VC_MAP_TC0 0 0 TC_VC_MAP_TC1_7 1 7 LOAD_PORT_ARB_TABLE 16 16 PORT_ARB_SELECT 17 19 VC_ID 24 26 VC_ENABLE 31 31 mmPCIE_VC1_RESOURCE_STATUS 0 0x4d 2 0 4294967295 PORT_ARB_TABLE_STATUS 0 0 VC_NEGOTIATION_PENDING 1 1 mmPCIE_DEV_SERIAL_NUM_ENH_CAP_LIST 0 0x50 3 0 4294967295 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 mmPCIE_DEV_SERIAL_NUM_DW1 0 0x51 1 0 4294967295 SERIAL_NUMBER_LO 0 31 mmPCIE_DEV_SERIAL_NUM_DW2 0 0x52 1 0 4294967295 SERIAL_NUMBER_HI 0 31 mmPCIE_ADV_ERR_RPT_ENH_CAP_LIST 0 0x54 3 0 4294967295 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 mmPCIE_UNCORR_ERR_STATUS 0 0x55 16 0 4294967295 DLP_ERR_STATUS 4 4 SURPDN_ERR_STATUS 5 5 PSN_ERR_STATUS 12 12 FC_ERR_STATUS 13 13 CPL_TIMEOUT_STATUS 14 14 CPL_ABORT_ERR_STATUS 15 15 UNEXP_CPL_STATUS 16 16 RCV_OVFL_STATUS 17 17 MAL_TLP_STATUS 18 18 ECRC_ERR_STATUS 19 19 UNSUPP_REQ_ERR_STATUS 20 20 ACS_VIOLATION_STATUS 21 21 UNCORR_INT_ERR_STATUS 22 22 MC_BLOCKED_TLP_STATUS 23 23 ATOMICOP_EGRESS_BLOCKED_STATUS 24 24 TLP_PREFIX_BLOCKED_ERR_STATUS 25 25 mmPCIE_UNCORR_ERR_MASK 0 0x56 16 0 4294967295 DLP_ERR_MASK 4 4 SURPDN_ERR_MASK 5 5 PSN_ERR_MASK 12 12 FC_ERR_MASK 13 13 CPL_TIMEOUT_MASK 14 14 CPL_ABORT_ERR_MASK 15 15 UNEXP_CPL_MASK 16 16 RCV_OVFL_MASK 17 17 MAL_TLP_MASK 18 18 ECRC_ERR_MASK 19 19 UNSUPP_REQ_ERR_MASK 20 20 ACS_VIOLATION_MASK 21 21 UNCORR_INT_ERR_MASK 22 22 MC_BLOCKED_TLP_MASK 23 23 ATOMICOP_EGRESS_BLOCKED_MASK 24 24 TLP_PREFIX_BLOCKED_ERR_MASK 25 25 mmPCIE_UNCORR_ERR_SEVERITY 0 0x57 16 0 4294967295 DLP_ERR_SEVERITY 4 4 SURPDN_ERR_SEVERITY 5 5 PSN_ERR_SEVERITY 12 12 FC_ERR_SEVERITY 13 13 CPL_TIMEOUT_SEVERITY 14 14 CPL_ABORT_ERR_SEVERITY 15 15 UNEXP_CPL_SEVERITY 16 16 RCV_OVFL_SEVERITY 17 17 MAL_TLP_SEVERITY 18 18 ECRC_ERR_SEVERITY 19 19 UNSUPP_REQ_ERR_SEVERITY 20 20 ACS_VIOLATION_SEVERITY 21 21 UNCORR_INT_ERR_SEVERITY 22 22 MC_BLOCKED_TLP_SEVERITY 23 23 ATOMICOP_EGRESS_BLOCKED_SEVERITY 24 24 TLP_PREFIX_BLOCKED_ERR_SEVERITY 25 25 mmPCIE_CORR_ERR_STATUS 0 0x58 8 0 4294967295 RCV_ERR_STATUS 0 0 BAD_TLP_STATUS 6 6 BAD_DLLP_STATUS 7 7 REPLAY_NUM_ROLLOVER_STATUS 8 8 REPLAY_TIMER_TIMEOUT_STATUS 12 12 ADVISORY_NONFATAL_ERR_STATUS 13 13 CORR_INT_ERR_STATUS 14 14 HDR_LOG_OVFL_STATUS 15 15 mmPCIE_CORR_ERR_MASK 0 0x59 8 0 4294967295 RCV_ERR_MASK 0 0 BAD_TLP_MASK 6 6 BAD_DLLP_MASK 7 7 REPLAY_NUM_ROLLOVER_MASK 8 8 REPLAY_TIMER_TIMEOUT_MASK 12 12 ADVISORY_NONFATAL_ERR_MASK 13 13 CORR_INT_ERR_MASK 14 14 HDR_LOG_OVFL_MASK 15 15 mmPCIE_ADV_ERR_CAP_CNTL 0 0x5a 8 0 4294967295 FIRST_ERR_PTR 0 4 ECRC_GEN_CAP 5 5 ECRC_GEN_EN 6 6 ECRC_CHECK_CAP 7 7 ECRC_CHECK_EN 8 8 MULTI_HDR_RECD_CAP 9 9 MULTI_HDR_RECD_EN 10 10 TLP_PREFIX_LOG_PRESENT 11 11 mmPCIE_HDR_LOG0 0 0x5b 1 0 4294967295 TLP_HDR 0 31 mmPCIE_HDR_LOG1 0 0x5c 1 0 4294967295 TLP_HDR 0 31 mmPCIE_HDR_LOG2 0 0x5d 1 0 4294967295 TLP_HDR 0 31 mmPCIE_HDR_LOG3 0 0x5e 1 0 4294967295 TLP_HDR 0 31 mmPCIE_TLP_PREFIX_LOG0 0 0x62 1 0 4294967295 TLP_PREFIX 0 31 mmPCIE_TLP_PREFIX_LOG1 0 0x63 1 0 4294967295 TLP_PREFIX 0 31 mmPCIE_TLP_PREFIX_LOG2 0 0x64 1 0 4294967295 TLP_PREFIX 0 31 mmPCIE_TLP_PREFIX_LOG3 0 0x65 1 0 4294967295 TLP_PREFIX 0 31 mmPCIE_BAR_ENH_CAP_LIST 0 0x80 3 0 4294967295 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 mmPCIE_BAR1_CAP 0 0x81 1 0 4294967295 BAR_SIZE_SUPPORTED 4 23 mmPCIE_BAR1_CNTL 0 0x82 3 0 4294967295 BAR_INDEX 0 2 BAR_TOTAL_NUM 5 7 BAR_SIZE 8 12 mmPCIE_BAR2_CAP 0 0x83 1 0 4294967295 BAR_SIZE_SUPPORTED 4 23 mmPCIE_BAR2_CNTL 0 0x84 3 0 4294967295 BAR_INDEX 0 2 BAR_TOTAL_NUM 5 7 BAR_SIZE 8 12 mmPCIE_BAR3_CAP 0 0x85 1 0 4294967295 BAR_SIZE_SUPPORTED 4 23 mmPCIE_BAR3_CNTL 0 0x86 3 0 4294967295 BAR_INDEX 0 2 BAR_TOTAL_NUM 5 7 BAR_SIZE 8 12 mmPCIE_BAR4_CAP 0 0x87 1 0 4294967295 BAR_SIZE_SUPPORTED 4 23 mmPCIE_BAR4_CNTL 0 0x88 3 0 4294967295 BAR_INDEX 0 2 BAR_TOTAL_NUM 5 7 BAR_SIZE 8 12 mmPCIE_BAR5_CAP 0 0x89 1 0 4294967295 BAR_SIZE_SUPPORTED 4 23 mmPCIE_BAR5_CNTL 0 0x8a 3 0 4294967295 BAR_INDEX 0 2 BAR_TOTAL_NUM 5 7 BAR_SIZE 8 12 mmPCIE_BAR6_CAP 0 0x8b 1 0 4294967295 BAR_SIZE_SUPPORTED 4 23 mmPCIE_BAR6_CNTL 0 0x8c 3 0 4294967295 BAR_INDEX 0 2 BAR_TOTAL_NUM 5 7 BAR_SIZE 8 12 mmPCIE_PWR_BUDGET_ENH_CAP_LIST 0 0x90 3 0 4294967295 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 mmPCIE_PWR_BUDGET_DATA_SELECT 0 0x91 1 0 4294967295 DATA_SELECT 0 7 mmPCIE_PWR_BUDGET_DATA 0 0x92 6 0 4294967295 BASE_POWER 0 7 DATA_SCALE 8 9 PM_SUB_STATE 10 12 PM_STATE 13 14 TYPE 15 17 POWER_RAIL 18 20 mmPCIE_PWR_BUDGET_CAP 0 0x93 1 0 4294967295 SYSTEM_ALLOCATED 0 0 mmPCIE_DPA_ENH_CAP_LIST 0 0x94 3 0 4294967295 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 mmPCIE_DPA_CAP 0 0x95 5 0 4294967295 SUBSTATE_MAX 0 4 TRANS_LAT_UNIT 8 9 PWR_ALLOC_SCALE 12 13 TRANS_LAT_VAL_0 16 23 TRANS_LAT_VAL_1 24 31 mmPCIE_DPA_LATENCY_INDICATOR 0 0x96 1 0 4294967295 TRANS_LAT_INDICATOR_BITS 0 7 mmPCIE_DPA_STATUS 0 0x97 2 0 4294967295 SUBSTATE_STATUS 0 4 SUBSTATE_CNTL_ENABLED 8 8 mmPCIE_DPA_CNTL 0 0x97 1 0 4294967295 SUBSTATE_CNTL 0 4 mmPCIE_DPA_SUBSTATE_PWR_ALLOC_0 0 0x98 1 0 4294967295 SUBSTATE_PWR_ALLOC 0 7 mmPCIE_DPA_SUBSTATE_PWR_ALLOC_1 0 0x98 1 0 4294967295 SUBSTATE_PWR_ALLOC 0 7 mmPCIE_DPA_SUBSTATE_PWR_ALLOC_2 0 0x98 1 0 4294967295 SUBSTATE_PWR_ALLOC 0 7 mmPCIE_DPA_SUBSTATE_PWR_ALLOC_3 0 0x98 1 0 4294967295 SUBSTATE_PWR_ALLOC 0 7 mmPCIE_DPA_SUBSTATE_PWR_ALLOC_4 0 0x99 1 0 4294967295 SUBSTATE_PWR_ALLOC 0 7 mmPCIE_DPA_SUBSTATE_PWR_ALLOC_5 0 0x99 1 0 4294967295 SUBSTATE_PWR_ALLOC 0 7 mmPCIE_DPA_SUBSTATE_PWR_ALLOC_6 0 0x99 1 0 4294967295 SUBSTATE_PWR_ALLOC 0 7 mmPCIE_DPA_SUBSTATE_PWR_ALLOC_7 0 0x99 1 0 4294967295 SUBSTATE_PWR_ALLOC 0 7 mmPCIE_SECONDARY_ENH_CAP_LIST 0 0x9c 3 0 4294967295 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 mmPCIE_LINK_CNTL3 0 0x9d 3 0 4294967295 PERFORM_EQUALIZATION 0 0 LINK_EQUALIZATION_REQ_INT_EN 1 1 RESERVED 2 31 mmPCIE_LANE_ERROR_STATUS 0 0x9e 2 0 4294967295 LANE_ERROR_STATUS_BITS 0 15 RESERVED 16 31 mmPCIE_LANE_0_EQUALIZATION_CNTL 0 0x9f 5 0 4294967295 DOWNSTREAM_PORT_TX_PRESET 0 3 DOWNSTREAM_PORT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_TX_PRESET 8 11 UPSTREAM_PORT_RX_PRESET_HINT 12 14 RESERVED 15 15 mmPCIE_LANE_1_EQUALIZATION_CNTL 0 0x9f 5 0 4294967295 DOWNSTREAM_PORT_TX_PRESET 0 3 DOWNSTREAM_PORT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_TX_PRESET 8 11 UPSTREAM_PORT_RX_PRESET_HINT 12 14 RESERVED 15 15 mmPCIE_LANE_2_EQUALIZATION_CNTL 0 0xa0 5 0 4294967295 DOWNSTREAM_PORT_TX_PRESET 0 3 DOWNSTREAM_PORT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_TX_PRESET 8 11 UPSTREAM_PORT_RX_PRESET_HINT 12 14 RESERVED 15 15 mmPCIE_LANE_3_EQUALIZATION_CNTL 0 0xa0 5 0 4294967295 DOWNSTREAM_PORT_TX_PRESET 0 3 DOWNSTREAM_PORT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_TX_PRESET 8 11 UPSTREAM_PORT_RX_PRESET_HINT 12 14 RESERVED 15 15 mmPCIE_LANE_4_EQUALIZATION_CNTL 0 0xa1 5 0 4294967295 DOWNSTREAM_PORT_TX_PRESET 0 3 DOWNSTREAM_PORT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_TX_PRESET 8 11 UPSTREAM_PORT_RX_PRESET_HINT 12 14 RESERVED 15 15 mmPCIE_LANE_5_EQUALIZATION_CNTL 0 0xa1 5 0 4294967295 DOWNSTREAM_PORT_TX_PRESET 0 3 DOWNSTREAM_PORT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_TX_PRESET 8 11 UPSTREAM_PORT_RX_PRESET_HINT 12 14 RESERVED 15 15 mmPCIE_LANE_6_EQUALIZATION_CNTL 0 0xa2 5 0 4294967295 DOWNSTREAM_PORT_TX_PRESET 0 3 DOWNSTREAM_PORT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_TX_PRESET 8 11 UPSTREAM_PORT_RX_PRESET_HINT 12 14 RESERVED 15 15 mmPCIE_LANE_7_EQUALIZATION_CNTL 0 0xa2 5 0 4294967295 DOWNSTREAM_PORT_TX_PRESET 0 3 DOWNSTREAM_PORT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_TX_PRESET 8 11 UPSTREAM_PORT_RX_PRESET_HINT 12 14 RESERVED 15 15 mmPCIE_LANE_8_EQUALIZATION_CNTL 0 0xa3 5 0 4294967295 DOWNSTREAM_PORT_TX_PRESET 0 3 DOWNSTREAM_PORT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_TX_PRESET 8 11 UPSTREAM_PORT_RX_PRESET_HINT 12 14 RESERVED 15 15 mmPCIE_LANE_9_EQUALIZATION_CNTL 0 0xa3 5 0 4294967295 DOWNSTREAM_PORT_TX_PRESET 0 3 DOWNSTREAM_PORT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_TX_PRESET 8 11 UPSTREAM_PORT_RX_PRESET_HINT 12 14 RESERVED 15 15 mmPCIE_LANE_10_EQUALIZATION_CNTL 0 0xa4 5 0 4294967295 DOWNSTREAM_PORT_TX_PRESET 0 3 DOWNSTREAM_PORT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_TX_PRESET 8 11 UPSTREAM_PORT_RX_PRESET_HINT 12 14 RESERVED 15 15 mmPCIE_LANE_11_EQUALIZATION_CNTL 0 0xa4 5 0 4294967295 DOWNSTREAM_PORT_TX_PRESET 0 3 DOWNSTREAM_PORT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_TX_PRESET 8 11 UPSTREAM_PORT_RX_PRESET_HINT 12 14 RESERVED 15 15 mmPCIE_LANE_12_EQUALIZATION_CNTL 0 0xa5 5 0 4294967295 DOWNSTREAM_PORT_TX_PRESET 0 3 DOWNSTREAM_PORT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_TX_PRESET 8 11 UPSTREAM_PORT_RX_PRESET_HINT 12 14 RESERVED 15 15 mmPCIE_LANE_13_EQUALIZATION_CNTL 0 0xa5 5 0 4294967295 DOWNSTREAM_PORT_TX_PRESET 0 3 DOWNSTREAM_PORT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_TX_PRESET 8 11 UPSTREAM_PORT_RX_PRESET_HINT 12 14 RESERVED 15 15 mmPCIE_LANE_14_EQUALIZATION_CNTL 0 0xa6 5 0 4294967295 DOWNSTREAM_PORT_TX_PRESET 0 3 DOWNSTREAM_PORT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_TX_PRESET 8 11 UPSTREAM_PORT_RX_PRESET_HINT 12 14 RESERVED 15 15 mmPCIE_LANE_15_EQUALIZATION_CNTL 0 0xa6 5 0 4294967295 DOWNSTREAM_PORT_TX_PRESET 0 3 DOWNSTREAM_PORT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_TX_PRESET 8 11 UPSTREAM_PORT_RX_PRESET_HINT 12 14 RESERVED 15 15 mmPCIE_ACS_ENH_CAP_LIST 0 0xa8 3 0 4294967295 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 mmPCIE_ACS_CAP 0 0xa9 8 0 4294967295 SOURCE_VALIDATION 0 0 TRANSLATION_BLOCKING 1 1 P2P_REQUEST_REDIRECT 2 2 P2P_COMPLETION_REDIRECT 3 3 UPSTREAM_FORWARDING 4 4 P2P_EGRESS_CONTROL 5 5 DIRECT_TRANSLATED_P2P 6 6 EGRESS_CONTROL_VECTOR_SIZE 8 15 mmPCIE_ACS_CNTL 0 0xa9 7 0 4294967295 SOURCE_VALIDATION_EN 0 0 TRANSLATION_BLOCKING_EN 1 1 P2P_REQUEST_REDIRECT_EN 2 2 P2P_COMPLETION_REDIRECT_EN 3 3 UPSTREAM_FORWARDING_EN 4 4 P2P_EGRESS_CONTROL_EN 5 5 DIRECT_TRANSLATED_P2P_EN 6 6 mmPCIE_ATS_ENH_CAP_LIST 0 0xac 3 0 4294967295 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 mmPCIE_ATS_CAP 0 0xad 3 0 4294967295 INVALIDATE_Q_DEPTH 0 4 PAGE_ALIGNED_REQUEST 5 5 GLOBAL_INVALIDATE_SUPPORTED 6 6 mmPCIE_ATS_CNTL 0 0xad 2 0 4294967295 STU 0 4 ATC_ENABLE 15 15 mmPCIE_PAGE_REQ_ENH_CAP_LIST 0 0xb0 3 0 4294967295 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 mmPCIE_PAGE_REQ_CNTL 0 0xb1 2 0 4294967295 PRI_ENABLE 0 0 PRI_RESET 1 1 mmPCIE_PAGE_REQ_STATUS 0 0xb1 4 0 4294967295 RESPONSE_FAILURE 0 0 UNEXPECTED_PAGE_REQ_GRP_INDEX 1 1 STOPPED 8 8 PRG_RESPONSE_PASID_REQUIRED 15 15 mmPCIE_OUTSTAND_PAGE_REQ_CAPACITY 0 0xb2 1 0 4294967295 OUTSTAND_PAGE_REQ_CAPACITY 0 31 mmPCIE_OUTSTAND_PAGE_REQ_ALLOC 0 0xb3 1 0 4294967295 OUTSTAND_PAGE_REQ_ALLOC 0 31 mmPCIE_PASID_ENH_CAP_LIST 0 0xb4 3 0 4294967295 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 mmPCIE_PASID_CAP 0 0xb5 3 0 4294967295 PASID_EXE_PERMISSION_SUPPORTED 1 1 PASID_PRIV_MODE_SUPPORTED 2 2 MAX_PASID_WIDTH 8 12 mmPCIE_PASID_CNTL 0 0xb5 3 0 4294967295 PASID_ENABLE 0 0 PASID_EXE_PERMISSION_ENABLE 1 1 PASID_PRIV_MODE_SUPPORTED_ENABLE 2 2 mmPCIE_TPH_REQR_ENH_CAP_LIST 0 0xb8 3 0 4294967295 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 mmPCIE_TPH_REQR_CAP 0 0xb9 6 0 4294967295 TPH_REQR_NO_ST_MODE_SUPPORTED 0 0 TPH_REQR_INT_VEC_MODE_SUPPORTED 1 1 TPH_REQR_DEV_SPC_MODE_SUPPORTED 2 2 TPH_REQR_EXTND_TPH_REQR_SUPPORED 8 8 TPH_REQR_ST_TABLE_LOCATION 9 10 TPH_REQR_ST_TABLE_SIZE 16 26 mmPCIE_TPH_REQR_CNTL 0 0xba 2 0 4294967295 TPH_REQR_ST_MODE_SEL 0 2 TPH_REQR_EN 8 9 mmPCIE_MC_ENH_CAP_LIST 0 0xbc 3 0 4294967295 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 mmPCIE_MC_CAP 0 0xbd 3 0 4294967295 MC_MAX_GROUP 0 5 MC_WIN_SIZE_REQ 8 13 MC_ECRC_REGEN_SUPP 15 15 mmPCIE_MC_CNTL 0 0xbd 2 0 4294967295 MC_NUM_GROUP 0 5 MC_ENABLE 15 15 mmPCIE_MC_ADDR0 0 0xbe 2 0 4294967295 MC_INDEX_POS 0 5 MC_BASE_ADDR_0 12 31 mmPCIE_MC_ADDR1 0 0xbf 1 0 4294967295 MC_BASE_ADDR_1 0 31 mmPCIE_MC_RCV0 0 0xc0 1 0 4294967295 MC_RECEIVE_0 0 31 mmPCIE_MC_RCV1 0 0xc1 1 0 4294967295 MC_RECEIVE_1 0 31 mmPCIE_MC_BLOCK_ALL0 0 0xc2 1 0 4294967295 MC_BLOCK_ALL_0 0 31 mmPCIE_MC_BLOCK_ALL1 0 0xc3 1 0 4294967295 MC_BLOCK_ALL_1 0 31 mmPCIE_MC_BLOCK_UNTRANSLATED_0 0 0xc4 1 0 4294967295 MC_BLOCK_UNTRANSLATED_0 0 31 mmPCIE_MC_BLOCK_UNTRANSLATED_1 0 0xc5 1 0 4294967295 MC_BLOCK_UNTRANSLATED_1 0 31 mmPCIE_LTR_ENH_CAP_LIST 0 0xc8 3 0 4294967295 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 mmPCIE_LTR_CAP 0 0xc9 4 0 4294967295 LTR_MAX_S_LATENCY_VALUE 0 9 LTR_MAX_S_LATENCY_SCALE 10 12 LTR_MAX_NS_LATENCY_VALUE 16 25 LTR_MAX_NS_LATENCY_SCALE 26 28 mmPCIE_ARI_ENH_CAP_LIST 0 0xca 3 0 4294967295 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 mmPCIE_ARI_CAP 0 0xcb 3 0 4294967295 ARI_MFVC_FUNC_GROUPS_CAP 0 0 ARI_ACS_FUNC_GROUPS_CAP 1 1 ARI_NEXT_FUNC_NUM 8 15 mmPCIE_ARI_CNTL 0 0xcb 3 0 4294967295 ARI_MFVC_FUNC_GROUPS_EN 0 0 ARI_ACS_FUNC_GROUPS_EN 1 1 ARI_FUNCTION_GROUP 4 6 mmPCIE_SRIOV_ENH_CAP_LIST 0 0xcc 3 0 4294967295 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 mmPCIE_SRIOV_CAP 0 0xcd 3 0 4294967295 SRIOV_VF_MIGRATION_CAP 0 0 SRIOV_ARI_CAP_HIERARCHY_PRESERVED 1 1 SRIOV_VF_MIGRATION_INTR_MSG_NUM 21 31 mmPCIE_SRIOV_CONTROL 0 0xce 5 0 4294967295 SRIOV_VF_ENABLE 0 0 SRIOV_VF_MIGRATION_ENABLE 1 1 SRIOV_VF_MIGRATION_INTR_ENABLE 2 2 SRIOV_VF_MSE 3 3 SRIOV_ARI_CAP_HIERARCHY 4 4 mmPCIE_SRIOV_STATUS 0 0xce 1 0 4294967295 SRIOV_VF_MIGRATION_STATUS 0 0 mmPCIE_SRIOV_INITIAL_VFS 0 0xcf 1 0 4294967295 SRIOV_INITIAL_VFS 0 15 mmPCIE_SRIOV_TOTAL_VFS 0 0xcf 1 0 4294967295 SRIOV_TOTAL_VFS 0 15 mmPCIE_SRIOV_NUM_VFS 0 0xd0 1 0 4294967295 SRIOV_NUM_VFS 0 15 mmPCIE_SRIOV_FUNC_DEP_LINK 0 0xd0 1 0 4294967295 SRIOV_FUNC_DEP_LINK 0 7 mmPCIE_SRIOV_FIRST_VF_OFFSET 0 0xd1 1 0 4294967295 SRIOV_FIRST_VF_OFFSET 0 15 mmPCIE_SRIOV_VF_STRIDE 0 0xd1 1 0 4294967295 SRIOV_VF_STRIDE 0 15 mmPCIE_SRIOV_VF_DEVICE_ID 0 0xd2 1 0 4294967295 SRIOV_VF_DEVICE_ID 0 15 mmPCIE_SRIOV_SUPPORTED_PAGE_SIZE 0 0xd3 1 0 4294967295 SRIOV_SUPPORTED_PAGE_SIZE 0 31 mmPCIE_SRIOV_SYSTEM_PAGE_SIZE 0 0xd4 1 0 4294967295 SRIOV_SYSTEM_PAGE_SIZE 0 31 mmPCIE_SRIOV_VF_BASE_ADDR_0 0 0xd5 1 0 4294967295 VF_BASE_ADDR 0 31 mmPCIE_SRIOV_VF_BASE_ADDR_1 0 0xd6 1 0 4294967295 VF_BASE_ADDR 0 31 mmPCIE_SRIOV_VF_BASE_ADDR_2 0 0xd7 1 0 4294967295 VF_BASE_ADDR 0 31 mmPCIE_SRIOV_VF_BASE_ADDR_3 0 0xd8 1 0 4294967295 VF_BASE_ADDR 0 31 mmPCIE_SRIOV_VF_BASE_ADDR_4 0 0xd9 1 0 4294967295 VF_BASE_ADDR 0 31 mmPCIE_SRIOV_VF_BASE_ADDR_5 0 0xda 1 0 4294967295 VF_BASE_ADDR 0 31 mmPCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET 0 0xdb 1 0 4294967295 SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET 0 31 mmPCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV 0 0x100 3 0 4294967295 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV 0 0x101 3 0 4294967295 VSEC_ID 0 15 VSEC_REV 16 19 VSEC_LENGTH 20 31 mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW 0 0x102 2 0 4294967295 VF_EN 0 0 VF_NUM 16 31 mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CMD_CTRL_N_FUNC 0 0x103 3 0 4294967295 CMD_CONTROL 0 7 FCN_ID 8 15 NXT_FCN_ID 16 23 mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CMD_STATUS 0 0x104 1 0 4294967295 CMD_STATUS 0 7 mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL 0 0x105 1 0 4294967295 SOFT_PF_FLR 0 0 mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_NOTIFICATION 0 0x106 1 0 4294967295 RESET_NOTIFICATION 0 31 mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VM_INIT_STATUS 0 0x107 1 0 4294967295 VM_INIT_STATUS 0 31 mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT 0 0x108 3 0 4294967295 CNTXT_SIZE 0 6 LOC 7 7 CNTXT_OFFSET 18 31 mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB 0 0x109 2 0 4294967295 TOTAL_FB_CONSUMED 0 15 TOTAL_FB_AVAILABLE 16 31 mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VM_BUSY_STATUS 0 0x10a 1 0 4294967295 VM_BUSY_STATUS 0 31 mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS 0 0x10b 3 0 4294967295 GPU_INFO_OFFSET 8 15 AUTO_SCH_OFFSET 16 23 DISP_OFFSET 24 31 mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB 0 0x10c 2 0 4294967295 FB_OFFSET 0 15 FB_SIZE 16 31 mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB 0 0x10d 2 0 4294967295 FB_OFFSET 0 15 FB_SIZE 16 31 mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB 0 0x10e 2 0 4294967295 FB_OFFSET 0 15 FB_SIZE 16 31 mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB 0 0x10f 2 0 4294967295 FB_OFFSET 0 15 FB_SIZE 16 31 mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB 0 0x110 2 0 4294967295 FB_OFFSET 0 15 FB_SIZE 16 31 mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB 0 0x111 2 0 4294967295 FB_OFFSET 0 15 FB_SIZE 16 31 mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB 0 0x112 2 0 4294967295 FB_OFFSET 0 15 FB_SIZE 16 31 mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB 0 0x113 2 0 4294967295 FB_OFFSET 0 15 FB_SIZE 16 31 mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB 0 0x114 2 0 4294967295 FB_OFFSET 0 15 FB_SIZE 16 31 mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB 0 0x115 2 0 4294967295 FB_OFFSET 0 15 FB_SIZE 16 31 mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB 0 0x116 2 0 4294967295 FB_OFFSET 0 15 FB_SIZE 16 31 mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB 0 0x117 2 0 4294967295 FB_OFFSET 0 15 FB_SIZE 16 31 mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB 0 0x118 2 0 4294967295 FB_OFFSET 0 15 FB_SIZE 16 31 mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB 0 0x119 2 0 4294967295 FB_OFFSET 0 15 FB_SIZE 16 31 mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB 0 0x11a 2 0 4294967295 FB_OFFSET 0 15 FB_SIZE 16 31 mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB 0 0x11b 2 0 4294967295 FB_OFFSET 0 15 FB_SIZE 16 31 mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GPU_IDLE_LAT 0 0x11c 1 0 4294967295 GPU_IDLE_LATENCY 0 31 mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_MMIO_MAP_RANGE0 0 0x11d 2 0 4294967295 LOWER 0 15 UPPER 16 31 mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_MMIO_MAP_RANGE1 0 0x11e 2 0 4294967295 LOWER 0 15 UPPER 16 31 mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_MMIO_MAP_RANGE2 0 0x11f 2 0 4294967295 LOWER 0 15 UPPER 16 31 mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_MMIO_MAP_RANGE3 0 0x120 2 0 4294967295 LOWER 0 15 UPPER 16 31 mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_MMIO_MAP_RANGE4 0 0x121 2 0 4294967295 LOWER 0 15 UPPER 16 31 mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_MMIO_MAP_RANGE5 0 0x122 2 0 4294967295 LOWER 0 15 UPPER 16 31 mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH_0 0 0x124 1 0 4294967295 DATA 0 31 mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH_1 0 0x125 1 0 4294967295 DATA 0 31 mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH_2 0 0x126 1 0 4294967295 DATA 0 31 mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH_3 0 0x127 1 0 4294967295 DATA 0 31 mmPCIE_INDEX 0 0xe 1 0 4294967295 PCIE_INDEX 0 31 mmPCIE_DATA 0 0xf 1 0 4294967295 PCIE_DATA 0 31 mmPCIE_INDEX_2 0 0xc 1 0 4294967295 PCIE_INDEX 0 31 mmPCIE_DATA_2 0 0xd 1 0 4294967295 PCIE_DATA 0 31 ixPCIE_HOLD_TRAINING_A 2 0x1500820 1 0 4294967295 HOLD_TRAINING_A 0 0 ixLNCNT_CONTROL 2 0x1508030 5 0 4294967295 CFG_LNC_WINDOW_EN0 0 0 CFG_LNC_BW_CNT_EN1 1 1 CFG_LNC_CMN_CNT_EN2 2 2 CFG_LNC_OVRD_EN3 3 3 CFG_LNC_OVRD_VAL4 4 4 ixCFG_LNC_WINDOW 2 0x1508031 1 0 4294967295 CFG_LNC_WINDOW0 0 23 ixLNCNT_QUAN_THRD 2 0x1508032 2 0 4294967295 CFG_LNC_BW_QUAN_THRD0 0 2 CFG_LNC_CMN_QUAN_THRD4 4 6 ixLNCNT_WEIGHT 2 0x1508033 2 0 4294967295 CFG_LNC_BW_WEIGHT0 0 15 CFG_LNC_CMN_WEIGHT16 16 31 ixLNC_TOTAL_WACC 2 0x1508034 1 0 4294967295 LNC_TOTAL_WACC 0 31 ixLNC_BW_WACC 2 0x1508035 1 0 4294967295 LNC_BW_WACC 0 31 ixLNC_CMN_WACC 2 0x1508036 1 0 4294967295 LNC_CMN_WACC 0 31 mmPCIE_EFUSE 0 0xfc0 7 0 4294967295 PCIE_EFUSE_VALID 1 1 PPHY_EFUSE_VALID 2 2 SPARE_5_3_EFUSE0 3 5 ISTRAP_ARBEN0 6 6 SPARE_26_7_EFUSE0 7 26 CHIP_BIF_MODE 27 27 SPARE_31_28_EFUSE0 28 31 mmPCIE_EFUSE2 0 0xfc1 1 0 4294967295 SPARE_31_1_EFUSE2 1 31 mmPCIE_EFUSE3 0 0xfc2 3 0 4294967295 STRAP_CEC_ID 1 16 STRAP_BIF_KILL_GEN3 17 17 SPARE_14_PCIEFUSE3 18 31 mmPCIE_EFUSE4 0 0xfc3 6 0 4294967295 CC_WRITE_DISABLE 0 0 SPARE_3_PCIEFUSE4 1 3 STRAP_BIF_F0_DEVICE_ID 4 19 STRAP_BIF_F0_MAJOR_REV_ID 20 23 STRAP_BIF_F0_MINOR_REV_ID 24 27 STRAP_BIF_ATI_REV_ID 28 31 mmPCIE_EFUSE5 0 0xfc4 2 0 4294967295 STRAP_AZALIA_DID 1 16 SPARE_16_PCIEFUSE5 17 31 mmPCIE_EFUSE6 0 0xfc5 2 0 4294967295 STRAP_BIF_F0_SUPPORTED_PAGE_SIZES 1 16 SPARE_15_PCIEFUSE6 17 31 mmPCIE_EFUSE7 0 0xfc6 2 0 4294967295 STRAP_BIF_F0_SRIOV_VF_DEVICE_ID 1 16 SPARE_15_PCIEFUSE7 17 31 ixPCIE_WRAP_SCRATCH1 2 0x1308001 1 0 4294967295 PCIE_WRAP_SCRATCH1 0 31 ixPCIE_WRAP_SCRATCH2 2 0x1308002 1 0 4294967295 PCIE_WRAP_SCRATCH2 0 31 ixPCIE_WRAP_REG_TARG_MISC 2 0x1308005 1 0 4294967295 CLKEN_MASK 0 0 ixPCIE_WRAP_DTM_MISC 2 0x1308006 1 0 4294967295 DTM_BULKPHY_FREQDIV_OVERRIDE 0 0 ixPCIE_WRAP_TURNAROUND_DAISYCHAIN 2 0x1308007 2 0 4294967295 END_BIFCORE_REGISTER_DAISYCHAIN 0 0 END_WRAPPER_REGISTER_DAISYCHAIN 1 1 ixPCIE_WRAP_MISC 2 0x1308008 2 0 4294967295 STRAP_BIF_HOLD_TRAINING_STICKY 1 1 STRAP_BIF_QUICKSIM_START 2 2 ixPCIE_WRAP_PIF_MISC 2 0x1308009 4 0 4294967295 DTM_PIF_DELAY_FI 0 2 DTM_PIF_DELAY_DI 4 6 DTM_PIF_ATSEL_FI 7 7 DTM_PIF_ATSEL_DI 8 8 ixPCIE_RXDET_OVERRIDE 2 0x130800a 2 0 4294967295 RxDetOvrVal 0 15 RxDetOvrEn 16 16 ixREG_ADAPT_pciecore0_CONTROL 2 0x1308090 1 0 4294967295 ACCESS_MODE_pciecore0 0 0 ixREG_ADAPT_pwregt_CONTROL 2 0x1308096 1 0 4294967295 ACCESS_MODE_pwregt 0 0 ixREG_ADAPT_pwregr_CONTROL 2 0x1308097 1 0 4294967295 ACCESS_MODE_pwregr 0 0 ixREG_ADAPT_pif0_CONTROL 2 0x1308098 1 0 4294967295 ACCESS_MODE_pif0 0 0 ixPCIE_RESERVED 2 0x1400000 1 0 4294967295 PCIE_RESERVED 0 31 ixPCIE_SCRATCH 2 0x1400001 1 0 4294967295 PCIE_SCRATCH 0 31 ixPCIE_HW_DEBUG 2 0x1400002 16 0 4294967295 HW_00_DEBUG 0 0 HW_01_DEBUG 1 1 HW_02_DEBUG 2 2 HW_03_DEBUG 3 3 HW_04_DEBUG 4 4 HW_05_DEBUG 5 5 HW_06_DEBUG 6 6 HW_07_DEBUG 7 7 HW_08_DEBUG 8 8 HW_09_DEBUG 9 9 HW_10_DEBUG 10 10 HW_11_DEBUG 11 11 HW_12_DEBUG 12 12 HW_13_DEBUG 13 13 HW_14_DEBUG 14 14 HW_15_DEBUG 15 15 ixPCIE_RX_NUM_NAK 2 0x140000e 1 0 4294967295 RX_NUM_NAK 0 31 ixPCIE_RX_NUM_NAK_GENERATED 2 0x140000f 1 0 4294967295 RX_NUM_NAK_GENERATED 0 31 ixPCIE_CNTL 2 0x1400010 18 0 4294967295 HWINIT_WR_LOCK 0 0 LC_HOT_PLUG_DELAY_SEL 1 3 UR_ERR_REPORT_DIS 7 7 PCIE_MALFORM_ATOMIC_OPS 8 8 PCIE_HT_NP_MEM_WRITE 9 9 RX_SB_ADJ_PAYLOAD_SIZE 10 12 RX_RCB_ATS_UC_DIS 15 15 RX_RCB_REORDER_EN 16 16 RX_RCB_INVALID_SIZE_DIS 17 17 RX_RCB_UNEXP_CPL_DIS 18 18 RX_RCB_CPL_TIMEOUT_TEST_MODE 19 19 RX_RCB_WRONG_PREFIX_DIS 20 20 RX_RCB_WRONG_ATTR_DIS 21 21 RX_RCB_WRONG_FUNCNUM_DIS 22 22 RX_ATS_TRAN_CPL_SPLIT_DIS 23 23 TX_CPL_DEBUG 24 29 RX_IGNORE_LTR_MSG_UR 30 30 RX_CPL_POSTED_REQ_ORD_EN 31 31 ixPCIE_CONFIG_CNTL 2 0x1400011 7 0 4294967295 DYN_CLK_LATENCY 0 3 CI_MAX_PAYLOAD_SIZE_MODE 16 16 CI_PRIV_MAX_PAYLOAD_SIZE 17 19 CI_MAX_READ_REQUEST_SIZE_MODE 20 20 CI_PRIV_MAX_READ_REQUEST_SIZE 21 23 CI_MAX_READ_SAFE_MODE 24 24 CI_EXTENDED_TAG_EN_OVERRIDE 25 26 ixPCIE_DEBUG_CNTL 2 0x1400012 3 0 4294967295 DEBUG_PORT_EN 0 7 DEBUG_SELECT 8 8 DEBUG_LANE_EN 16 31 ixPCIE_INT_CNTL 2 0x140001a 8 0 4294967295 CORR_ERR_INT_EN 0 0 NON_FATAL_ERR_INT_EN 1 1 FATAL_ERR_INT_EN 2 2 USR_DETECTED_INT_EN 3 3 MISC_ERR_INT_EN 4 4 POWER_STATE_CHG_INT_EN 6 6 LINK_BW_INT_EN 7 7 QUIESCE_RCVD_INT_EN 8 8 ixPCIE_INT_STATUS 2 0x140001b 8 0 4294967295 CORR_ERR_INT_STATUS 0 0 NON_FATAL_ERR_INT_STATUS 1 1 FATAL_ERR_INT_STATUS 2 2 USR_DETECTED_INT_STATUS 3 3 MISC_ERR_INT_STATUS 4 4 POWER_STATE_CHG_INT_STATUS 6 6 LINK_BW_INT_STATUS 7 7 QUIESCE_RCVD_INT_STATUS 8 8 ixPCIE_CNTL2 2 0x140001c 19 0 4294967295 TX_ARB_ROUND_ROBIN_EN 0 0 TX_ARB_SLV_LIMIT 1 5 TX_ARB_MST_LIMIT 6 10 TX_BLOCK_TLP_ON_PM_DIS 11 11 TX_NP_MEM_WRITE_SWP_ENCODING 12 12 TX_ATOMIC_OPS_DISABLE 13 13 TX_ATOMIC_ORDERING_DIS 14 14 SLV_MEM_LS_EN 16 16 SLV_MEM_AGGRESSIVE_LS_EN 17 17 MST_MEM_LS_EN 18 18 REPLAY_MEM_LS_EN 19 19 SLV_MEM_SD_EN 20 20 SLV_MEM_AGGRESSIVE_SD_EN 21 21 MST_MEM_SD_EN 22 22 REPLAY_MEM_SD_EN 23 23 RX_NP_MEM_WRITE_ENCODING 24 28 SLV_MEM_DS_EN 29 29 MST_MEM_DS_EN 30 30 REPLAY_MEM_DS_EN 31 31 ixPCIE_RX_CNTL2 2 0x140001d 13 0 4294967295 RX_IGNORE_EP_INVALIDPASID_UR 0 0 RX_IGNORE_EP_TRANSMRD_UR 1 1 RX_IGNORE_EP_TRANSMWR_UR 2 2 RX_IGNORE_EP_ATSTRANSREQ_UR 3 3 RX_IGNORE_EP_PAGEREQMSG_UR 4 4 RX_IGNORE_EP_INVCPL_UR 5 5 RX_RCB_LATENCY_EN 8 8 RX_RCB_LATENCY_SCALE 9 11 SLVCPL_MEM_LS_EN 12 12 SLVCPL_MEM_SD_EN 13 13 SLVCPL_MEM_DS_EN 14 14 RX_RCB_LATENCY_MAX_COUNT 16 25 FLR_EXTEND_MODE 28 30 ixPCIE_TX_F0_ATTR_CNTL 2 0x140001e 7 0 4294967295 TX_F0_IDO_OVERRIDE_P 0 1 TX_F0_IDO_OVERRIDE_NP 2 3 TX_F0_IDO_OVERRIDE_CPL 4 5 TX_F0_RO_OVERRIDE_P 6 7 TX_F0_RO_OVERRIDE_NP 8 9 TX_F0_SNR_OVERRIDE_P 10 11 TX_F0_SNR_OVERRIDE_NP 12 13 ixPCIE_TX_F1_F2_ATTR_CNTL 2 0x140001f 14 0 4294967295 TX_F1_IDO_OVERRIDE_P 0 1 TX_F1_IDO_OVERRIDE_NP 2 3 TX_F1_IDO_OVERRIDE_CPL 4 5 TX_F1_RO_OVERRIDE_P 6 7 TX_F1_RO_OVERRIDE_NP 8 9 TX_F1_SNR_OVERRIDE_P 10 11 TX_F1_SNR_OVERRIDE_NP 12 13 TX_F2_IDO_OVERRIDE_P 16 17 TX_F2_IDO_OVERRIDE_NP 18 19 TX_F2_IDO_OVERRIDE_CPL 20 21 TX_F2_RO_OVERRIDE_P 22 23 TX_F2_RO_OVERRIDE_NP 24 25 TX_F2_SNR_OVERRIDE_P 26 27 TX_F2_SNR_OVERRIDE_NP 28 29 ixPCIE_CI_CNTL 2 0x1400020 11 0 4294967295 CI_SLAVE_SPLIT_MODE 2 2 CI_SLAVE_GEN_USR_DIS 3 3 CI_MST_CMPL_DUMMY_DATA 4 4 CI_SLV_RC_RD_REQ_SIZE 6 7 CI_SLV_ORDERING_DIS 8 8 CI_RC_ORDERING_DIS 9 9 CI_SLV_CPL_ALLOC_DIS 10 10 CI_SLV_CPL_ALLOC_MODE 11 11 CI_SLV_CPL_ALLOC_SOR 12 12 CI_MST_IGNORE_PAGE_ALIGNED_REQUEST 13 13 CI_MST_ATOMIC_ADDR_HASH 16 18 ixPCIE_BUS_CNTL 2 0x1400021 3 0 4294967295 PMI_INT_DIS 6 6 IMMEDIATE_PMI_DIS 7 7 TRUE_PM_STATUS_EN 12 12 ixPCIE_LC_STATE6 2 0x1400022 4 0 4294967295 LC_PREV_STATE24 0 5 LC_PREV_STATE25 8 13 LC_PREV_STATE26 16 21 LC_PREV_STATE27 24 29 ixPCIE_LC_STATE7 2 0x1400023 4 0 4294967295 LC_PREV_STATE28 0 5 LC_PREV_STATE29 8 13 LC_PREV_STATE30 16 21 LC_PREV_STATE31 24 29 ixPCIE_LC_STATE8 2 0x1400024 4 0 4294967295 LC_PREV_STATE32 0 5 LC_PREV_STATE33 8 13 LC_PREV_STATE34 16 21 LC_PREV_STATE35 24 29 ixPCIE_LC_STATE9 2 0x1400025 4 0 4294967295 LC_PREV_STATE36 0 5 LC_PREV_STATE37 8 13 LC_PREV_STATE38 16 21 LC_PREV_STATE39 24 29 ixPCIE_LC_STATE10 2 0x1400026 4 0 4294967295 LC_PREV_STATE40 0 5 LC_PREV_STATE41 8 13 LC_PREV_STATE42 16 21 LC_PREV_STATE43 24 29 ixPCIE_LC_STATE11 2 0x1400027 4 0 4294967295 LC_PREV_STATE44 0 5 LC_PREV_STATE45 8 13 LC_PREV_STATE46 16 21 LC_PREV_STATE47 24 29 ixPCIE_LC_STATUS1 2 0x1400028 4 0 4294967295 LC_REVERSE_RCVR 0 0 LC_REVERSE_XMIT 1 1 LC_OPERATING_LINK_WIDTH 2 4 LC_DETECTED_LINK_WIDTH 5 7 ixPCIE_LC_STATUS2 2 0x1400029 2 0 4294967295 LC_TOTAL_INACTIVE_LANES 0 15 LC_TURN_ON_LANE 16 31 ixPCIE_WPR_CNTL 2 0x1400030 7 0 4294967295 WPR_RESET_HOT_RST_EN 0 0 WPR_RESET_LNK_DWN_EN 1 1 WPR_RESET_LNK_DIS_EN 2 2 WPR_RESET_COR_EN 3 3 WPR_RESET_REG_EN 4 4 WPR_RESET_STY_EN 5 5 WPR_RESET_PHY_EN 6 6 ixPCIE_RX_LAST_TLP0 2 0x1400031 1 0 4294967295 RX_LAST_TLP0 0 31 ixPCIE_RX_LAST_TLP1 2 0x1400032 1 0 4294967295 RX_LAST_TLP1 0 31 ixPCIE_RX_LAST_TLP2 2 0x1400033 1 0 4294967295 RX_LAST_TLP2 0 31 ixPCIE_RX_LAST_TLP3 2 0x1400034 1 0 4294967295 RX_LAST_TLP3 0 31 ixPCIE_TX_LAST_TLP0 2 0x1400035 1 0 4294967295 TX_LAST_TLP0 0 31 ixPCIE_TX_LAST_TLP1 2 0x1400036 1 0 4294967295 TX_LAST_TLP1 0 31 ixPCIE_TX_LAST_TLP2 2 0x1400037 1 0 4294967295 TX_LAST_TLP2 0 31 ixPCIE_TX_LAST_TLP3 2 0x1400038 1 0 4294967295 TX_LAST_TLP3 0 31 ixPCIE_I2C_REG_ADDR_EXPAND 2 0x140003a 1 0 4294967295 I2C_REG_ADDR 0 16 ixPCIE_I2C_REG_DATA 2 0x140003b 1 0 4294967295 I2C_REG_DATA 0 31 ixPCIE_CFG_CNTL 2 0x140003c 3 0 4294967295 CFG_EN_DEC_TO_HIDDEN_REG 0 0 CFG_EN_DEC_TO_GEN2_HIDDEN_REG 1 1 CFG_EN_DEC_TO_GEN3_HIDDEN_REG 2 2 ixPCIE_LC_PM_CNTL 2 0x140003d 1 0 4294967295 LC_L1_POWER_GATING_EN 0 0 ixPCIE_P_CNTL 2 0x1400040 13 0 4294967295 P_PWRDN_EN 0 0 P_SYMALIGN_MODE 1 1 P_SYMALIGN_HW_DEBUG 2 2 P_ELASTDESKEW_HW_DEBUG 3 3 P_IGNORE_CRC_ERR 4 4 P_IGNORE_LEN_ERR 5 5 P_IGNORE_EDB_ERR 6 6 P_IGNORE_IDL_ERR 7 7 P_IGNORE_TOK_ERR 8 8 P_BLK_LOCK_MODE 12 12 P_ALWAYS_USE_FAST_TXCLK 13 13 P_ELEC_IDLE_MODE 14 15 DLP_IGNORE_IN_L1_EN 16 16 ixPCIE_P_BUF_STATUS 2 0x1400041 2 0 4294967295 P_OVERFLOW_ERR 0 15 P_UNDERFLOW_ERR 16 31 ixPCIE_P_DECODER_STATUS 2 0x1400042 1 0 4294967295 P_DECODE_ERR 0 15 ixPCIE_P_MISC_STATUS 2 0x1400043 2 0 4294967295 P_DESKEW_ERR 0 7 P_SYMUNLOCK_ERR 16 31 ixPCIE_P_RCV_L0S_FTS_DET 2 0x1400050 2 0 4294967295 P_RCV_L0S_FTS_DET_MIN 0 7 P_RCV_L0S_FTS_DET_MAX 8 15 ixPCIE_OBFF_CNTL 2 0x1400061 12 0 4294967295 TX_OBFF_PRIV_DISABLE 0 0 TX_OBFF_WAKE_SIMPLE_MODE_EN 1 1 TX_OBFF_HOSTMEM_TO_ACTIVE 2 2 TX_OBFF_SLVCPL_TO_ACTIVE 3 3 TX_OBFF_WAKE_MAX_PULSE_WIDTH 4 7 TX_OBFF_WAKE_MAX_TWO_FALLING_WIDTH 8 11 TX_OBFF_WAKE_SAMPLING_PERIOD 12 15 TX_OBFF_INTR_TO_ACTIVE 16 16 TX_OBFF_ERR_TO_ACTIVE 17 17 TX_OBFF_ANY_MSG_TO_ACTIVE 18 18 TX_OBFF_ACCEPT_IN_NOND0 19 19 TX_OBFF_PENDING_REQ_TO_ACTIVE 20 23 ixPCIE_TX_LTR_CNTL 2 0x1400060 9 0 4294967295 LTR_PRIV_S_SHORT_VALUE 0 2 LTR_PRIV_S_LONG_VALUE 3 5 LTR_PRIV_S_REQUIREMENT 6 6 LTR_PRIV_NS_SHORT_VALUE 7 9 LTR_PRIV_NS_LONG_VALUE 10 12 LTR_PRIV_NS_REQUIREMENT 13 13 LTR_PRIV_MSG_DIS_IN_PM_NON_D0 14 14 LTR_PRIV_RST_LTR_IN_DL_DOWN 15 15 TX_CHK_FC_FOR_L1 16 16 ixPCIE_IDLE_STATUS 2 0x1400062 9 0 4294967295 PCIE_ALL_IDLE_STATUS 0 0 TX_TXDL_IDLE_STATUS 1 1 TX_RBUF_IDLE_STATUS 2 2 TX_RCVD_FC_CREDITS_IDLE 3 3 TX_RPL_CREDITS_IDLE 4 4 TX_PBUF_IDLE 5 5 TX_NPBUF_IDLE 6 6 TX_CPLBUF_IDLE 7 7 TX_MSGBUF_IDLE 8 8 ixPCIE_PERF_COUNT_CNTL 2 0x1400080 3 0 4294967295 GLOBAL_COUNT_EN 0 0 GLOBAL_SHADOW_WR 1 1 GLOBAL_COUNT_RESET 2 2 ixPCIE_PERF_CNTL_TXCLK 2 0x1400081 4 0 4294967295 EVENT0_SEL 0 7 EVENT1_SEL 8 15 COUNTER0_UPPER 16 23 COUNTER1_UPPER 24 31 ixPCIE_PERF_COUNT0_TXCLK 2 0x1400082 1 0 4294967295 COUNTER0 0 31 ixPCIE_PERF_COUNT1_TXCLK 2 0x1400083 1 0 4294967295 COUNTER1 0 31 ixPCIE_PERF_CNTL_MST_R_CLK 2 0x1400084 4 0 4294967295 EVENT0_SEL 0 7 EVENT1_SEL 8 15 COUNTER0_UPPER 16 23 COUNTER1_UPPER 24 31 ixPCIE_PERF_COUNT0_MST_R_CLK 2 0x1400085 1 0 4294967295 COUNTER0 0 31 ixPCIE_PERF_COUNT1_MST_R_CLK 2 0x1400086 1 0 4294967295 COUNTER1 0 31 ixPCIE_PERF_CNTL_MST_C_CLK 2 0x1400087 4 0 4294967295 EVENT0_SEL 0 7 EVENT1_SEL 8 15 COUNTER0_UPPER 16 23 COUNTER1_UPPER 24 31 ixPCIE_PERF_COUNT0_MST_C_CLK 2 0x1400088 1 0 4294967295 COUNTER0 0 31 ixPCIE_PERF_COUNT1_MST_C_CLK 2 0x1400089 1 0 4294967295 COUNTER1 0 31 ixPCIE_PERF_CNTL_SLV_R_CLK 2 0x140008a 4 0 4294967295 EVENT0_SEL 0 7 EVENT1_SEL 8 15 COUNTER0_UPPER 16 23 COUNTER1_UPPER 24 31 ixPCIE_PERF_COUNT0_SLV_R_CLK 2 0x140008b 1 0 4294967295 COUNTER0 0 31 ixPCIE_PERF_COUNT1_SLV_R_CLK 2 0x140008c 1 0 4294967295 COUNTER1 0 31 ixPCIE_PERF_CNTL_SLV_S_C_CLK 2 0x140008d 4 0 4294967295 EVENT0_SEL 0 7 EVENT1_SEL 8 15 COUNTER0_UPPER 16 23 COUNTER1_UPPER 24 31 ixPCIE_PERF_COUNT0_SLV_S_C_CLK 2 0x140008e 1 0 4294967295 COUNTER0 0 31 ixPCIE_PERF_COUNT1_SLV_S_C_CLK 2 0x140008f 1 0 4294967295 COUNTER1 0 31 ixPCIE_PERF_CNTL_SLV_NS_C_CLK 2 0x1400090 4 0 4294967295 EVENT0_SEL 0 7 EVENT1_SEL 8 15 COUNTER0_UPPER 16 23 COUNTER1_UPPER 24 31 ixPCIE_PERF_COUNT0_SLV_NS_C_CLK 2 0x1400091 1 0 4294967295 COUNTER0 0 31 ixPCIE_PERF_COUNT1_SLV_NS_C_CLK 2 0x1400092 1 0 4294967295 COUNTER1 0 31 ixPCIE_PERF_CNTL_EVENT0_PORT_SEL 2 0x1400093 7 0 4294967295 PERF0_PORT_SEL_TXCLK 0 3 PERF0_PORT_SEL_MST_R_CLK 4 7 PERF0_PORT_SEL_MST_C_CLK 8 11 PERF0_PORT_SEL_SLV_R_CLK 12 15 PERF0_PORT_SEL_SLV_S_C_CLK 16 19 PERF0_PORT_SEL_SLV_NS_C_CLK 20 23 PERF0_PORT_SEL_TXCLK2 24 27 ixPCIE_PERF_CNTL_EVENT1_PORT_SEL 2 0x1400094 7 0 4294967295 PERF1_PORT_SEL_TXCLK 0 3 PERF1_PORT_SEL_MST_R_CLK 4 7 PERF1_PORT_SEL_MST_C_CLK 8 11 PERF1_PORT_SEL_SLV_R_CLK 12 15 PERF1_PORT_SEL_SLV_S_C_CLK 16 19 PERF1_PORT_SEL_SLV_NS_C_CLK 20 23 PERF1_PORT_SEL_TXCLK2 24 27 ixPCIE_PERF_CNTL_TXCLK2 2 0x1400095 4 0 4294967295 EVENT0_SEL 0 7 EVENT1_SEL 8 15 COUNTER0_UPPER 16 23 COUNTER1_UPPER 24 31 ixPCIE_PERF_COUNT0_TXCLK2 2 0x1400096 1 0 4294967295 COUNTER0 0 31 ixPCIE_PERF_COUNT1_TXCLK2 2 0x1400097 1 0 4294967295 COUNTER1 0 31 ixPCIE_STRAP_F0 2 0x14000b0 27 0 4294967295 STRAP_F0_EN 0 0 STRAP_F0_LEGACY_DEVICE_TYPE_EN 1 1 STRAP_F0_MSI_EN 2 2 STRAP_F0_VC_EN 3 3 STRAP_F0_DSN_EN 4 4 STRAP_F0_AER_EN 5 5 STRAP_F0_ACS_EN 6 6 STRAP_F0_BAR_EN 7 7 STRAP_F0_PWR_EN 8 8 STRAP_F0_DPA_EN 9 9 STRAP_F0_ATS_EN 10 10 STRAP_F0_PAGE_REQ_EN 11 11 STRAP_F0_PASID_EN 12 12 STRAP_F0_ECRC_CHECK_EN 13 13 STRAP_F0_ECRC_GEN_EN 14 14 STRAP_F0_CPL_ABORT_ERR_EN 15 15 STRAP_F0_POISONED_ADVISORY_NONFATAL 16 16 STRAP_F0_MC_EN 17 17 STRAP_F0_ATOMIC_EN 18 18 STRAP_F0_ATOMIC_64BIT_EN 19 19 STRAP_F0_ATOMIC_ROUTING_EN 20 20 STRAP_F0_MSI_MULTI_CAP 21 23 STRAP_F0_VFn_MSI_MULTI_CAP 24 26 STRAP_F0_MSI_PERVECTOR_MASK_CAP 27 27 STRAP_F0_NO_RO_ENABLED_P2P_PASSING 28 28 STRAP_F0_ARI_EN 29 29 STRAP_F0_SRIOV_EN 30 30 ixPCIE_STRAP_F1 2 0x14000b1 21 0 4294967295 STRAP_F1_LEGACY_DEVICE_TYPE_EN 1 1 STRAP_F1_MSI_EN 2 2 STRAP_F1_VC_EN 3 3 STRAP_F1_DSN_EN 4 4 STRAP_F1_AER_EN 5 5 STRAP_F1_ACS_EN 6 6 STRAP_F1_BAR_EN 7 7 STRAP_F1_PWR_EN 8 8 STRAP_F1_DPA_EN 9 9 STRAP_F1_ATS_EN 10 10 STRAP_F1_PAGE_REQ_EN 11 11 STRAP_F1_PASID_EN 12 12 STRAP_F1_ECRC_CHECK_EN 13 13 STRAP_F1_ECRC_GEN_EN 14 14 STRAP_F1_CPL_ABORT_ERR_EN 15 15 STRAP_F1_POISONED_ADVISORY_NONFATAL 16 16 STRAP_F1_ATOMIC_EN 18 18 STRAP_F1_ATOMIC_64BIT_EN 19 19 STRAP_F1_ATOMIC_ROUTING_EN 20 20 STRAP_F1_MSI_MULTI_CAP 21 23 STRAP_F1_MSI_PERVECTOR_MASK_CAP 27 27 ixPCIE_STRAP_F2 2 0x14000b2 21 0 4294967295 STRAP_F2_LEGACY_DEVICE_TYPE_EN 1 1 STRAP_F2_MSI_EN 2 2 STRAP_F2_VC_EN 3 3 STRAP_F2_DSN_EN 4 4 STRAP_F2_AER_EN 5 5 STRAP_F2_ACS_EN 6 6 STRAP_F2_BAR_EN 7 7 STRAP_F2_PWR_EN 8 8 STRAP_F2_DPA_EN 9 9 STRAP_F2_ATS_EN 10 10 STRAP_F2_PAGE_REQ_EN 11 11 STRAP_F2_PASID_EN 12 12 STRAP_F2_ECRC_CHECK_EN 13 13 STRAP_F2_ECRC_GEN_EN 14 14 STRAP_F2_CPL_ABORT_ERR_EN 15 15 STRAP_F2_POISONED_ADVISORY_NONFATAL 16 16 STRAP_F2_ATOMIC_EN 18 18 STRAP_F2_ATOMIC_64BIT_EN 19 19 STRAP_F2_ATOMIC_ROUTING_EN 20 20 STRAP_F2_MSI_MULTI_CAP 21 23 STRAP_F2_MSI_PERVECTOR_MASK_CAP 27 27 ixPCIE_STRAP_F3 2 0x14000b3 1 0 4294967295 RESERVED 0 31 ixPCIE_STRAP_F4 2 0x14000b4 1 0 4294967295 RESERVED 0 31 ixPCIE_STRAP_F5 2 0x14000b5 1 0 4294967295 RESERVED 0 31 ixPCIE_STRAP_F6 2 0x14000b6 1 0 4294967295 RESERVED 0 31 ixPCIE_STRAP_MSIX 2 0x14000b7 3 0 4294967295 STRAP_F0_MSIX_EN 0 0 STRAP_F0_MSIX_TABLE_BIR 1 3 STRAP_F0_MSIX_TABLE_OFFSET 12 31 ixPCIE_STRAP_MISC 2 0x14000c0 12 0 4294967295 STRAP_TL_ALT_BUF_EN 4 4 STRAP_MAX_PASID_WIDTH 8 12 STRAP_PASID_EXE_PERMISSION_SUPPORTED 13 13 STRAP_PASID_PRIV_MODE_SUPPORTED 14 14 STRAP_PASID_GLOBAL_INVALIDATE_SUPPORTED 15 15 STRAP_CLK_PM_EN 24 24 STRAP_ECN1P1_EN 25 25 STRAP_EXT_VC_COUNT 26 26 STRAP_REVERSE_ALL 28 28 STRAP_MST_ADR64_EN 29 29 STRAP_FLR_EN 30 30 STRAP_INTERNAL_ERR_EN 31 31 ixPCIE_STRAP_MISC2 2 0x14000c1 4 0 4294967295 STRAP_GEN2_COMPLIANCE 1 1 STRAP_MSTCPL_TIMEOUT_EN 2 2 STRAP_GEN3_COMPLIANCE 3 3 STRAP_TPH_SUPPORTED 4 4 ixPCIE_STRAP_PI 2 0x14000c2 3 0 4294967295 STRAP_QUICKSIM_START 0 0 STRAP_TEST_TOGGLE_PATTERN 28 28 STRAP_TEST_TOGGLE_MODE 29 29 ixPCIE_STRAP_I2C_BD 2 0x14000c4 2 0 4294967295 STRAP_BIF_I2C_SLV_ADR 0 6 STRAP_BIF_DBG_I2C_EN 7 7 ixPCIE_PRBS_CLR 2 0x14000c8 3 0 4294967295 PRBS_CLR 0 15 PRBS_CHECKER_DEBUG_BUS_SELECT 16 19 PRBS_POLARITY_EN 24 24 ixPCIE_PRBS_STATUS1 2 0x14000c9 2 0 4294967295 PRBS_ERRSTAT 0 15 PRBS_LOCKED 16 31 ixPCIE_PRBS_STATUS2 2 0x14000ca 1 0 4294967295 PRBS_BITCNT_DONE 0 15 ixPCIE_PRBS_FREERUN 2 0x14000cb 1 0 4294967295 PRBS_FREERUN 0 15 ixPCIE_PRBS_MISC 2 0x14000cc 8 0 4294967295 PRBS_EN 0 0 PRBS_TEST_MODE 1 3 PRBS_USER_PATTERN_TOGGLE 4 4 PRBS_8BIT_SEL 5 5 PRBS_COMMA_NUM 6 7 PRBS_LOCK_CNT 8 12 PRBS_DATA_RATE 14 15 PRBS_CHK_ERR_MASK 16 31 ixPCIE_PRBS_USER_PATTERN 2 0x14000cd 1 0 4294967295 PRBS_USER_PATTERN 0 29 ixPCIE_PRBS_LO_BITCNT 2 0x14000ce 1 0 4294967295 PRBS_LO_BITCNT 0 31 ixPCIE_PRBS_HI_BITCNT 2 0x14000cf 1 0 4294967295 PRBS_HI_BITCNT 0 7 ixPCIE_PRBS_ERRCNT_0 2 0x14000d0 1 0 4294967295 PRBS_ERRCNT_0 0 31 ixPCIE_PRBS_ERRCNT_1 2 0x14000d1 1 0 4294967295 PRBS_ERRCNT_1 0 31 ixPCIE_PRBS_ERRCNT_2 2 0x14000d2 1 0 4294967295 PRBS_ERRCNT_2 0 31 ixPCIE_PRBS_ERRCNT_3 2 0x14000d3 1 0 4294967295 PRBS_ERRCNT_3 0 31 ixPCIE_PRBS_ERRCNT_4 2 0x14000d4 1 0 4294967295 PRBS_ERRCNT_4 0 31 ixPCIE_PRBS_ERRCNT_5 2 0x14000d5 1 0 4294967295 PRBS_ERRCNT_5 0 31 ixPCIE_PRBS_ERRCNT_6 2 0x14000d6 1 0 4294967295 PRBS_ERRCNT_6 0 31 ixPCIE_PRBS_ERRCNT_7 2 0x14000d7 1 0 4294967295 PRBS_ERRCNT_7 0 31 ixPCIE_PRBS_ERRCNT_8 2 0x14000d8 1 0 4294967295 PRBS_ERRCNT_8 0 31 ixPCIE_PRBS_ERRCNT_9 2 0x14000d9 1 0 4294967295 PRBS_ERRCNT_9 0 31 ixPCIE_PRBS_ERRCNT_10 2 0x14000da 1 0 4294967295 PRBS_ERRCNT_10 0 31 ixPCIE_PRBS_ERRCNT_11 2 0x14000db 1 0 4294967295 PRBS_ERRCNT_11 0 31 ixPCIE_PRBS_ERRCNT_12 2 0x14000dc 1 0 4294967295 PRBS_ERRCNT_12 0 31 ixPCIE_PRBS_ERRCNT_13 2 0x14000dd 1 0 4294967295 PRBS_ERRCNT_13 0 31 ixPCIE_PRBS_ERRCNT_14 2 0x14000de 1 0 4294967295 PRBS_ERRCNT_14 0 31 ixPCIE_PRBS_ERRCNT_15 2 0x14000df 1 0 4294967295 PRBS_ERRCNT_15 0 31 ixPCIE_F0_DPA_CAP 2 0x14000e0 4 0 4294967295 TRANS_LAT_UNIT 8 9 PWR_ALLOC_SCALE 12 13 TRANS_LAT_VAL_0 16 23 TRANS_LAT_VAL_1 24 31 ixPCIE_F0_DPA_LATENCY_INDICATOR 2 0x14000e4 1 0 4294967295 TRANS_LAT_INDICATOR_BITS 0 7 ixPCIE_F0_DPA_CNTL 2 0x14000e5 2 0 4294967295 SUBSTATE_STATUS 0 4 DPA_COMPLIANCE_MODE 8 8 ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0 2 0x14000e7 1 0 4294967295 SUBSTATE_PWR_ALLOC 0 7 ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1 2 0x14000e8 1 0 4294967295 SUBSTATE_PWR_ALLOC 0 7 ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2 2 0x14000e9 1 0 4294967295 SUBSTATE_PWR_ALLOC 0 7 ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3 2 0x14000ea 1 0 4294967295 SUBSTATE_PWR_ALLOC 0 7 ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4 2 0x14000eb 1 0 4294967295 SUBSTATE_PWR_ALLOC 0 7 ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5 2 0x14000ec 1 0 4294967295 SUBSTATE_PWR_ALLOC 0 7 ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6 2 0x14000ed 1 0 4294967295 SUBSTATE_PWR_ALLOC 0 7 ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7 2 0x14000ee 1 0 4294967295 SUBSTATE_PWR_ALLOC 0 7 mmSWRST_COMMAND_STATUS 0 0x14a0 4 0 4294967295 RECONFIGURE 0 0 ATOMIC_RESET 1 1 RESET_COMPLETE 16 16 WAIT_STATE 17 17 mmSWRST_GENERAL_CONTROL 0 0x14a1 13 0 4294967295 RECONFIGURE_EN 0 0 ATOMIC_RESET_EN 1 1 RESET_PERIOD 2 4 WAIT_LINKUP 8 8 FORCE_REGIDLE 9 9 BLOCK_ON_IDLE 10 10 CONFIG_XFER_MODE 12 12 MUXSEL_XFER_MODE 13 13 HLDTRAIN_XFER_MODE 14 14 BYPASS_HOLD 16 16 BYPASS_PIF_HOLD 17 17 EP_COMPLT_CHK_EN 28 28 EP_COMPLT_WAIT_TMR 29 30 mmSWRST_COMMAND_0 0 0x14a2 8 0 4294967295 BIF_STRAPREG_RESET 15 15 BIF0_GLOBAL_RESET 16 16 BIF0_CALIB_RESET 17 17 BIF0_CORE_RESET 18 18 BIF0_REGISTER_RESET 19 19 BIF0_PHY_RESET 20 20 BIF0_STICKY_RESET 21 21 BIF0_CONFIG_RESET 22 22 mmSWRST_COMMAND_1 0 0x14a3 20 0 4294967295 SWITCHCLK 0 0 RESETPCFG 1 1 RESETLANEMUX 2 2 RESETWRAPREGS 3 3 RESETSRBM0 4 4 RESETSRBM1 5 5 RESETLC 6 6 SYNCIDLEPIF0 8 8 SYNCIDLEPIF1 9 9 RESETMNTR 13 13 RESETHLTR 14 14 RESETCPM 15 15 RESETPIF0 16 16 RESETPIF1 17 17 RESETIMPARB0 20 20 RESETIMPARB1 21 21 RESETPHY0 24 24 RESETPHY1 25 25 TOGGLESTRAP 28 28 CMDCFGEN 29 29 mmSWRST_CONTROL_0 0 0x14a4 8 0 4294967295 BIF_STRAPREG_RESETRCEN 15 15 BIF0_GLOBAL_RESETRCEN 16 16 BIF0_CALIB_RESETRCEN 17 17 BIF0_CORE_RESETRCEN 18 18 BIF0_REGISTER_RESETRCEN 19 19 BIF0_PHY_RESETRCEN 20 20 BIF0_STICKY_RESETRCEN 21 21 BIF0_CONFIG_RESETRCEN 22 22 mmSWRST_CONTROL_1 0 0x14a5 20 0 4294967295 SWITCHCLK_RCEN 0 0 RESETPCFG_RCEN 1 1 RESETLANEMUX_RCEN 2 2 RESETWRAPREGS_RCEN 3 3 RESETSRBM0_RCEN 4 4 RESETSRBM1_RCEN 5 5 RESETLC_RCEN 6 6 SYNCIDLEPIF0_RCEN 8 8 SYNCIDLEPIF1_RCEN 9 9 RESETMNTR_RCEN 13 13 RESETHLTR_RCEN 14 14 RESETCPM_RCEN 15 15 RESETPIF0_RCEN 16 16 RESETPIF1_RCEN 17 17 RESETIMPARB0_RCEN 20 20 RESETIMPARB1_RCEN 21 21 RESETPHY0_RCEN 24 24 RESETPHY1_RCEN 25 25 STRAPVLD_RCEN 28 28 CMDCFG_RCEN 29 29 mmSWRST_CONTROL_2 0 0x14a6 8 0 4294967295 BIF_STRAPREG_RESETATEN 15 15 BIF0_GLOBAL_RESETATEN 16 16 BIF0_CALIB_RESETATEN 17 17 BIF0_CORE_RESETATEN 18 18 BIF0_REGISTER_RESETATEN 19 19 BIF0_PHY_RESETATEN 20 20 BIF0_STICKY_RESETATEN 21 21 BIF0_CONFIG_RESETATEN 22 22 mmSWRST_CONTROL_3 0 0x14a7 20 0 4294967295 SWITCHCLK_ATEN 0 0 RESETPCFG_ATEN 1 1 RESETLANEMUX_ATEN 2 2 RESETWRAPREGS_ATEN 3 3 RESETSRBM0_ATEN 4 4 RESETSRBM1_ATEN 5 5 RESETLC_ATEN 6 6 SYNCIDLEPIF0_ATEN 8 8 SYNCIDLEPIF1_ATEN 9 9 RESETMNTR_ATEN 13 13 RESETHLTR_ATEN 14 14 RESETCPM_ATEN 15 15 RESETPIF0_ATEN 16 16 RESETPIF1_ATEN 17 17 RESETIMPARB0_ATEN 20 20 RESETIMPARB1_ATEN 21 21 RESETPHY0_ATEN 24 24 RESETPHY1_ATEN 25 25 STRAPVLD_ATEN 28 28 CMDCFG_ATEN 29 29 mmSWRST_CONTROL_4 0 0x14a8 8 0 4294967295 BIF_STRAPREG_WRRESETEN 14 14 BIF0_GLOBAL_WRRESETEN 16 16 BIF0_CALIB_WRRESETEN 17 17 BIF0_CORE_WRRESETEN 18 18 BIF0_REGISTER_WRRESETEN 19 19 BIF0_PHY_WRRESETEN 20 20 BIF0_STICKY_WRRESETEN 21 21 BIF0_CONFIG_WRRESETEN 22 22 mmSWRST_CONTROL_5 0 0x14a9 20 0 4294967295 WRSWITCHCLK_EN 0 0 WRRESETPCFG_EN 1 1 WRRESETLANEMUX_EN 2 2 WRRESETWRAPREGS_EN 3 3 WRRESETSRBM0_EN 4 4 WRRESETSRBM1_EN 5 5 WRRESETLC_EN 6 6 WRSYNCIDLEPIF0_EN 8 8 WRSYNCIDLEPIF1_EN 9 9 WRRESETMNTR_EN 13 13 WRRESETHLTR_EN 14 14 WRRESETCPM_EN 15 15 WRRESETPIF0_EN 16 16 WRRESETPIF1_EN 17 17 WRRESETIMPARB0_EN 20 20 WRRESETIMPARB1_EN 21 21 WRRESETPHY0_EN 24 24 WRRESETPHY1_EN 25 25 WRSTRAPVLD_EN 28 28 WRCMDCFG_EN 29 29 mmSWRST_CONTROL_6 0 0x14aa 2 0 4294967295 WARMRESET_EN 0 0 CONNECTWITHWRAPREGS_EN 8 8 mmSWRST_EP_COMMAND_0 0 0x14ab 9 0 4294967295 EP_CFG_RESET_ONLY 0 0 EP_SOFT_RESET 1 1 EP_DRV_RESET 2 2 EP_HOT_RESET 8 8 EP_LNKDWN_RESET 9 9 EP_LNKDIS_RESET 10 10 EP_FLR0_RESET 16 16 EP_FLR1_RESET 17 17 EP_FLR2_RESET 18 18 mmSWRST_EP_CONTROL_0 0 0x14ac 11 0 4294967295 EP_CFG_RESET_ONLY_EN 0 0 EP_SOFT_RESET_EN 1 1 EP_DRV_RESET_EN 2 2 EP_HOT_RESET_EN 8 8 EP_LNKDWN_RESET_EN 9 9 EP_LNKDIS_RESET_EN 10 10 EP_FLR0_RESET_EN 16 16 EP_FLR1_RESET_EN 17 17 EP_FLR2_RESET_EN 18 18 EP_CFG_WR_RESET_EN 19 19 EP_FLR_DISABLE_CFG_RST 20 23 mmCPM_CONTROL 0 0x14b8 23 0 4294967295 LCLK_DYN_GATE_ENABLE 0 0 TXCLK_DYN_GATE_ENABLE 1 1 TXCLK_PERM_GATE_ENABLE 2 2 TXCLK_PIF_GATE_ENABLE 3 3 TXCLK_GSKT_GATE_ENABLE 4 4 TXCLK_LCNT_GATE_ENABLE 5 5 TXCLK_REGS_GATE_ENABLE 6 6 TXCLK_PRBS_GATE_ENABLE 7 7 REFCLK_REGS_GATE_ENABLE 8 8 LCLK_DYN_GATE_LATENCY 9 9 TXCLK_DYN_GATE_LATENCY 10 10 TXCLK_PERM_GATE_LATENCY 11 11 TXCLK_REGS_GATE_LATENCY 12 12 REFCLK_REGS_GATE_LATENCY 13 13 LCLK_GATE_TXCLK_FREE 14 14 RCVR_DET_CLK_ENABLE 15 15 TXCLK_PERM_GATE_PLL_PDN 16 16 FAST_TXCLK_LATENCY 17 19 MASTER_PCIE_PLL_SELECT 20 20 MASTER_PCIE_PLL_AUTO 21 21 REFCLK_XSTCLK_ENABLE 22 22 REFCLK_XSTCLK_LATENCY 23 23 SPARE_REGS 24 31 mmGSKT_CONTROL 0 0x14bf 4 0 4294967295 GSKT_TxFifoBypass 0 0 GSKT_TxFifoDelay 1 1 GSKT_TxFifoDelay2 2 2 GSKT_SpareRegs 3 7 ixSWRST_COMMAND_1 2 0x1400103 0 0 4294967295 ixLM_CONTROL 2 0x1400120 4 0 4294967295 LoopbackSelect 1 4 PRBSPCIeLbSelect 5 5 LoopbackHalfRate 6 7 LoopbackFifoPtr 8 10 ixLM_PCIETXMUX0 2 0x1400121 4 0 4294967295 TXLANE0 0 7 TXLANE1 8 15 TXLANE2 16 23 TXLANE3 24 31 ixLM_PCIETXMUX1 2 0x1400122 4 0 4294967295 TXLANE4 0 7 TXLANE5 8 15 TXLANE6 16 23 TXLANE7 24 31 ixLM_PCIETXMUX2 2 0x1400123 4 0 4294967295 TXLANE8 0 7 TXLANE9 8 15 TXLANE10 16 23 TXLANE11 24 31 ixLM_PCIETXMUX3 2 0x1400124 4 0 4294967295 TXLANE12 0 7 TXLANE13 8 15 TXLANE14 16 23 TXLANE15 24 31 ixLM_PCIERXMUX0 2 0x1400125 4 0 4294967295 RXLANE0 0 7 RXLANE1 8 15 RXLANE2 16 23 RXLANE3 24 31 ixLM_PCIERXMUX1 2 0x1400126 4 0 4294967295 RXLANE4 0 7 RXLANE5 8 15 RXLANE6 16 23 RXLANE7 24 31 ixLM_PCIERXMUX2 2 0x1400127 4 0 4294967295 RXLANE8 0 7 RXLANE9 8 15 RXLANE10 16 23 RXLANE11 24 31 ixLM_PCIERXMUX3 2 0x1400128 4 0 4294967295 RXLANE12 0 7 RXLANE13 8 15 RXLANE14 16 23 RXLANE15 24 31 ixLM_LANEENABLE 2 0x1400129 1 0 4294967295 LANE_enable 0 15 ixLM_PRBSCONTROL 2 0x140012a 5 0 4294967295 PRBSPCIeSelect 0 15 LMLaneDegrade0 28 28 LMLaneDegrade1 29 29 LMLaneDegrade2 30 30 LMLaneDegrade3 31 31 ixLM_POWERCONTROL 2 0x140012b 12 0 4294967295 LMTxPhyCmd0 0 2 LMRxPhyCmd0 3 5 LMLinkSpeed0 6 7 LMTxPhyCmd1 8 10 LMRxPhyCmd1 11 13 LMLinkSpeed1 14 15 LMTxPhyCmd2 16 18 LMRxPhyCmd2 19 21 LMLinkSpeed2 22 23 LMTxPhyCmd3 24 26 LMRxPhyCmd3 27 29 LMLinkSpeed3 30 31 ixLM_POWERCONTROL1 2 0x140012c 23 0 4294967295 LMTxEn0 0 0 LMTxClkEn0 1 1 LMTxMargin0 2 4 LMSkipBit0 5 5 LMLaneUnused0 6 6 LMTxMarginEn0 7 7 LMDeemph0 8 8 LMTxEn1 9 9 LMTxClkEn1 10 10 LMTxMargin1 11 13 LMSkipBit1 14 14 LMLaneUnused1 15 15 LMTxMarginEn1 16 16 LMDeemph1 17 17 LMTxEn2 18 18 LMTxClkEn2 19 19 LMTxMargin2 20 22 LMSkipBit2 23 23 LMLaneUnused2 24 24 LMTxMarginEn2 25 25 LMDeemph2 26 26 TxCoeffID0 27 28 TxCoeffID1 29 30 ixLM_POWERCONTROL2 2 0x140012d 12 0 4294967295 LMTxEn3 0 0 LMTxClkEn3 1 1 LMTxMargin3 2 4 LMSkipBit3 5 5 LMLaneUnused3 6 6 LMTxMarginEn3 7 7 LMDeemph3 8 8 TxCoeffID2 9 10 TxCoeffID3 11 12 TxCoeff0 13 18 TxCoeff1 19 24 TxCoeff2 25 30 ixLM_POWERCONTROL3 2 0x140012e 5 0 4294967295 TxCoeff3 0 5 RxEqCtl0 6 11 RxEqCtl1 12 17 RxEqCtl2 18 23 RxEqCtl3 24 29 ixLM_POWERCONTROL4 2 0x140012f 12 0 4294967295 LinkNum0 0 2 LinkNum1 3 5 LinkNum2 6 8 LinkNum3 9 11 LaneNum0 12 15 LaneNum1 16 19 LaneNum2 20 23 LaneNum3 24 27 SpcMode0 28 28 SpcMode1 29 29 SpcMode2 30 30 SpcMode3 31 31 ixPB0_GLB_CTRL_REG0 2 0x1200004 8 0 4294967295 BACKUP 0 15 CFG_IDLEDET_TH 16 17 DBG_RX2TXBYP_SEL 20 22 DBG_RXFEBYP_EN 23 23 DBG_RXPRBS_CLR 24 24 DBG_RXTOGGLE_EN 25 25 DBG_TX2RXLBACK_EN 26 26 TXCFG_CMGOOD_RANGE 30 31 ixPB0_GLB_CTRL_REG1 2 0x1200008 10 0 4294967295 RXDBG_CDR_FR_BYP_EN 0 0 RXDBG_CDR_FR_BYP_VAL 1 6 RXDBG_CDR_PH_BYP_EN 7 7 RXDBG_CDR_PH_BYP_VAL 8 13 RXDBG_D0TH_BYP_EN 14 14 RXDBG_D0TH_BYP_VAL 15 21 RXDBG_D1TH_BYP_EN 22 22 RXDBG_D1TH_BYP_VAL 23 29 TST_LOSPDTST_EN 30 30 PLL_CFG_DISPCLK_DIV 31 31 ixPB0_GLB_CTRL_REG2 2 0x120000c 8 0 4294967295 RXDBG_D2TH_BYP_EN 0 0 RXDBG_D2TH_BYP_VAL 1 7 RXDBG_D3TH_BYP_EN 8 8 RXDBG_D3TH_BYP_VAL 9 15 RXDBG_DXTH_BYP_EN 16 16 RXDBG_DXTH_BYP_VAL 17 23 RXDBG_ETH_BYP_EN 24 24 RXDBG_ETH_BYP_VAL 25 31 ixPB0_GLB_CTRL_REG3 2 0x1200010 14 0 4294967295 RXDBG_SEL 0 4 BG_CFG_LC_REG_VREF0_SEL 5 6 BG_CFG_LC_REG_VREF1_SEL 7 8 BG_CFG_RO_REG_VREF_SEL 9 10 BG_DBG_VREFBYP_EN 11 11 BG_DBG_IREFBYP_EN 12 12 BG_DBG_ANALOG_SEL 14 16 DBG_DLL_CLK_SEL 18 20 PLL_DISPCLK_CMOS_SEL 21 21 DBG_RXPI_OFFSET_BYP_EN 22 22 DBG_RXPI_OFFSET_BYP_VAL 23 26 DBG_RXSWAPDX_BYP_EN 27 27 DBG_RXSWAPDX_BYP_VAL 28 30 DBG_RXLEQ_DCATTN_BYP_OVR_DISABLE 31 31 ixPB0_GLB_CTRL_REG4 2 0x1200014 7 0 4294967295 DBG_RXAPU_INST 0 15 DBG_RXDFEMUX_BYP_VAL 16 17 DBG_RXDFEMUX_BYP_EN 18 18 DBG_RXAPU_EXEC 22 25 DBG_RXDLL_VREG_REF_SEL 26 26 PWRGOOD_OVRD 27 27 DBG_RXRDATA_GATING_DISABLE 28 28 ixPB0_GLB_CTRL_REG5 2 0x1200018 1 0 4294967295 DBG_RXAPU_MODE 0 7 ixPB0_GLB_SCI_STAT_OVRD_REG0 2 0x120001c 9 0 4294967295 IGNR_ALL_CBI_UPDT_L0T3 0 0 IGNR_ALL_CBI_UPDT_L4T7 1 1 IGNR_ALL_CBI_UPDT_L8T11 2 2 IGNR_ALL_CBI_UPDT_L12T15 3 3 IGNR_IMPCAL_ACTIVE_CBI_UPDT 4 4 TXNIMP 8 11 TXPIMP 12 15 RXIMP 16 19 IMPCAL_ACTIVE 20 20 ixPB0_GLB_SCI_STAT_OVRD_REG1 2 0x1200020 15 0 4294967295 IGNR_LINKSPEED_CBI_UPDT_L0T3 0 0 IGNR_FREQDIV_CBI_UPDT_L0T3 1 1 IGNR_DLL_LOCK_CBI_UPDT_L0T3 2 2 DLL_LOCK_0 12 12 DLL_LOCK_1 13 13 DLL_LOCK_2 14 14 DLL_LOCK_3 15 15 LINKSPEED_0 16 17 FREQDIV_0 18 19 LINKSPEED_1 20 21 FREQDIV_1 22 23 LINKSPEED_2 24 25 FREQDIV_2 26 27 LINKSPEED_3 28 29 FREQDIV_3 30 31 ixPB0_GLB_SCI_STAT_OVRD_REG2 2 0x1200024 15 0 4294967295 IGNR_LINKSPEED_CBI_UPDT_L4T7 0 0 IGNR_FREQDIV_CBI_UPDT_L4T7 1 1 IGNR_DLL_LOCK_CBI_UPDT_L4T7 2 2 DLL_LOCK_4 12 12 DLL_LOCK_5 13 13 DLL_LOCK_6 14 14 DLL_LOCK_7 15 15 LINKSPEED_4 16 17 FREQDIV_4 18 19 LINKSPEED_5 20 21 FREQDIV_5 22 23 LINKSPEED_6 24 25 FREQDIV_6 26 27 LINKSPEED_7 28 29 FREQDIV_7 30 31 ixPB0_GLB_SCI_STAT_OVRD_REG3 2 0x1200028 15 0 4294967295 IGNR_LINKSPEED_CBI_UPDT_L8T11 0 0 IGNR_FREQDIV_CBI_UPDT_L8T11 1 1 IGNR_DLL_LOCK_CBI_UPDT_L8T11 2 2 DLL_LOCK_8 12 12 DLL_LOCK_9 13 13 DLL_LOCK_10 14 14 DLL_LOCK_11 15 15 LINKSPEED_8 16 17 FREQDIV_8 18 19 LINKSPEED_9 20 21 FREQDIV_9 22 23 LINKSPEED_10 24 25 FREQDIV_10 26 27 LINKSPEED_11 28 29 FREQDIV_11 30 31 ixPB0_GLB_SCI_STAT_OVRD_REG4 2 0x120002c 15 0 4294967295 IGNR_LINKSPEED_CBI_UPDT_L12T15 0 0 IGNR_FREQDIV_CBI_UPDT_L12T15 1 1 IGNR_DLL_LOCK_CBI_UPDT_L12T15 2 2 DLL_LOCK_12 12 12 DLL_LOCK_13 13 13 DLL_LOCK_14 14 14 DLL_LOCK_15 15 15 LINKSPEED_12 16 17 FREQDIV_12 18 19 LINKSPEED_13 20 21 FREQDIV_13 22 23 LINKSPEED_14 24 25 FREQDIV_14 26 27 LINKSPEED_15 28 29 FREQDIV_15 30 31 ixPB0_GLB_OVRD_REG0 2 0x1200030 2 0 4294967295 TXPDTERM_VAL_OVRD_VAL 0 15 TXPUTERM_VAL_OVRD_VAL 16 31 ixPB0_GLB_OVRD_REG1 2 0x1200034 6 0 4294967295 TXPDTERM_VAL_OVRD_EN 0 0 TXPUTERM_VAL_OVRD_EN 1 1 TST_LOSPDTST_RST_OVRD_EN 2 2 TST_LOSPDTST_RST_OVRD_VAL 3 3 RXTERM_VAL_OVRD_EN 15 15 RXTERM_VAL_OVRD_VAL 16 31 ixPB0_GLB_OVRD_REG2 2 0x1200038 6 0 4294967295 BG_PWRON_OVRD_EN 0 0 BG_PWRON_OVRD_VAL 1 1 PLL_DBG_LC_EXT_RESET_OVRD_EN 2 2 PLL_DBG_LC_EXT_RESET_OVRD_VAL 3 3 PLL_DBG_RO_EXT_RESET_OVRD_EN 4 4 PLL_DBG_RO_EXT_RESET_OVRD_VAL 5 5 ixPB0_HW_DEBUG 2 0x1202004 32 0 4294967295 HW_00_DEBUG 0 0 HW_01_DEBUG 1 1 HW_02_DEBUG 2 2 HW_03_DEBUG 3 3 HW_04_DEBUG 4 4 HW_05_DEBUG 5 5 HW_06_DEBUG 6 6 HW_07_DEBUG 7 7 HW_08_DEBUG 8 8 HW_09_DEBUG 9 9 HW_10_DEBUG 10 10 HW_11_DEBUG 11 11 HW_12_DEBUG 12 12 HW_13_DEBUG 13 13 HW_14_DEBUG 14 14 HW_15_DEBUG 15 15 HW_16_DEBUG 16 16 HW_17_DEBUG 17 17 HW_18_DEBUG 18 18 HW_19_DEBUG 19 19 HW_20_DEBUG 20 20 HW_21_DEBUG 21 21 HW_22_DEBUG 22 22 HW_23_DEBUG 23 23 HW_24_DEBUG 24 24 HW_25_DEBUG 25 25 HW_26_DEBUG 26 26 HW_27_DEBUG 27 27 HW_28_DEBUG 28 28 HW_29_DEBUG 29 29 HW_30_DEBUG 30 30 HW_31_DEBUG 31 31 ixPB0_STRAP_GLB_REG0 2 0x1202020 13 0 4294967295 STRAP_QUICK_SIM_START 1 1 STRAP_DFT_RXBSCAN_EN_VAL 2 2 STRAP_DFT_CALIB_BYPASS 3 3 STRAP_FORCE_LC_PLL_ON 4 4 STRAP_CFG_IDLEDET_TH 5 6 STRAP_RX_CFG_LEQ_DCATTN_BYP_VAL 7 11 STRAP_RX_CFG_OVR_PWRSF 12 12 STRAP_RX_TRK_MODE_0_ 13 13 STRAP_PWRGOOD_OVRD 14 14 STRAP_DBG_RXDLL_VREG_REF_SEL 15 15 STRAP_PLL_CFG_LC_VCO_TUNE 16 19 STRAP_DBG_RXRDATA_GATING_DISABLE 20 20 STRAP_DBG_RXPI_OFFSET_BYP_VAL 21 24 ixPB0_STRAP_TX_REG0 2 0x1202024 10 0 4294967295 STRAP_TX_CFG_DRV0_EN 1 4 STRAP_TX_CFG_DRV0_TAP_SEL 5 8 STRAP_TX_CFG_DRV1_EN 9 13 STRAP_TX_CFG_DRV1_TAP_SEL 14 18 STRAP_TX_CFG_DRV2_EN 19 22 STRAP_TX_CFG_DRV2_TAP_SEL 23 26 STRAP_TX_CFG_DRVX_EN 27 27 STRAP_TX_CFG_DRVX_TAP_SEL 28 28 STRAP_RX_TRK_MODE_1_ 29 29 STRAP_TX_CFG_SWING_BOOST_EN 30 30 ixPB0_STRAP_RX_REG0 2 0x1202028 12 0 4294967295 STRAP_RX_CFG_TH_LOOP_GAIN 1 4 STRAP_RX_CFG_DLL_FLOCK_DISABLE 5 5 STRAP_DBG_RXPI_OFFSET_BYP_EN 6 6 STRAP_RX_CFG_LEQ_DCATTN_BYP_DIS 7 7 STRAP_BG_CFG_LC_REG_VREF0_SEL 8 9 STRAP_BG_CFG_LC_REG_VREF1_SEL 10 11 STRAP_RX_CFG_CDR_TIME 12 15 STRAP_RX_CFG_FOM_TIME 16 19 STRAP_RX_CFG_LEQ_TIME 20 23 STRAP_RX_CFG_OC_TIME 24 27 STRAP_TX_CFG_RPTR_RST_VAL 28 30 STRAP_RX_CFG_TERM_MODE 31 31 ixPB0_STRAP_RX_REG1 2 0x120202c 10 0 4294967295 STRAP_RX_CFG_CDR_PI_STPSZ 1 1 STRAP_TX_DEEMPH_PRSHT_STNG 2 4 STRAP_BG_CFG_RO_REG_VREF_SEL 5 6 STRAP_RX_CFG_LEQ_POLE_BYP_DIS 7 7 STRAP_RX_CFG_LEQ_POLE_BYP_VAL 8 10 STRAP_RX_CFG_CDR_PH_GAIN 11 14 STRAP_RX_CFG_ADAPT_MODE 15 24 STRAP_RX_CFG_DFE_TIME 25 28 STRAP_RX_CFG_LEQ_LOOP_GAIN 29 30 STRAP_RX_CFG_LEQ_SHUNT_DIS 31 31 ixPB0_STRAP_PLL_REG0 2 0x1202030 6 0 4294967295 STRAP_PLL_CFG_LC_BW_CNTRL 1 3 STRAP_PLL_CFG_LC_LF_CNTRL 4 12 STRAP_TX_RXDET_X1_SSF 13 13 STRAP_PLL_CFG_RO_VTOI_BIAS_CNTRL_DIS 15 15 STRAP_PLL_CFG_RO_BW_CNTRL 16 23 STRAP_PLL_STRAP_SEL 24 24 ixPB0_STRAP_PIN_REG0 2 0x1202034 2 0 4294967295 STRAP_TX_DEEMPH_EN 1 1 STRAP_TX_FULL_SWING 2 2 ixPB0_STRAP_GLB_REG1 2 0x1202038 7 0 4294967295 STRAP_RX_ADAPT_RST_MODE 1 2 STRAP_RX_L0_ENTRY_MODE 3 4 STRAP_RX_EI_FILTER 5 6 STRAP_RX_ADAPT_RST_SUB_ENTRY 7 7 STRAP_RX_PS0_RDY_GEN_MODE 8 9 STRAP_RX_DLL_RESET_IN_SPDCHG 10 10 STRAP_RX_ADAPT_TIME_OUT 11 12 ixPB0_STRAP_GLB_REG2 2 0x120203c 8 0 4294967295 STRAP_BPHYC_PLL_RAMP_UP_TIME 2 4 STRAP_IMPCAL_SETTLE_TIME 5 6 STRAP_BG_SETTLE_TIME 7 8 STRAP_TX_CMDET_TIME 9 10 STRAP_TX_STARTUP_TIME 11 12 STRAP_B_PCB_DIS0 28 28 STRAP_B_PCB_DIS1 29 29 STRAP_B_PCB_DRV_STR 30 31 ixPB0_DFT_JIT_INJ_REG0 2 0x1203000 8 0 4294967295 DFT_NUM_STEPS 0 5 DFT_DISABLE_ERR 7 7 DFT_CLK_PER_STEP 8 11 DFT_MODE_CDR_EN 20 20 DFT_EN_RECOVERY 21 21 DFT_INCR_SWP_EN 22 22 DFT_DECR_SWP_EN 23 23 DFT_RECOVERY_TIME 24 31 ixPB0_DFT_JIT_INJ_REG1 2 0x1203004 5 0 4294967295 DFT_BYPASS_VALUE 0 7 DFT_BYPASS_EN 8 8 DFT_BLOCK_EN 16 16 DFT_NUM_OF_TESTS 17 19 DFT_CHECK_TIME 20 23 ixPB0_DFT_JIT_INJ_REG2 2 0x1203008 1 0 4294967295 DFT_LANE_EN 0 15 ixPB0_DFT_DEBUG_CTRL_REG0 2 0x120300c 2 0 4294967295 DFT_PHY_DEBUG_EN 0 0 DFT_PHY_DEBUG_MODE 1 5 ixPB0_DFT_JIT_INJ_STAT_REG0 2 0x1203010 3 0 4294967295 DFT_STAT_DECR 0 7 DFT_STAT_INCR 8 15 DFT_STAT_FINISHED 16 16 ixPB0_PLL_RO_GLB_CTRL_REG0 2 0x1204000 19 0 4294967295 PLL_TST_LOSPDTST_SRC 0 0 PLL_RO_HSCLK_LEFT_EN_LUT_ENTRY_LS0 1 1 PLL_RO_HSCLK_LEFT_EN_LUT_ENTRY_LS1 2 2 PLL_RO_HSCLK_LEFT_EN_LUT_ENTRY_LS2 3 3 PLL_RO_HSCLK_RIGHT_EN_LUT_ENTRY_LS0 4 4 PLL_RO_HSCLK_RIGHT_EN_LUT_ENTRY_LS1 5 5 PLL_RO_HSCLK_RIGHT_EN_LUT_ENTRY_LS2 6 6 PLL_RO_PWRON_LUT_ENTRY_LS2 7 7 PLL_LC_PWRON_LUT_ENTRY_LS2 8 8 PLL_LC_HSCLK_LEFT_EN_LUT_ENTRY_LS0 9 9 PLL_LC_HSCLK_LEFT_EN_LUT_ENTRY_LS1 10 10 PLL_LC_HSCLK_LEFT_EN_LUT_ENTRY_LS2 11 11 PLL_LC_HSCLK_RIGHT_EN_LUT_ENTRY_LS0 12 12 PLL_LC_HSCLK_RIGHT_EN_LUT_ENTRY_LS1 13 13 PLL_LC_HSCLK_RIGHT_EN_LUT_ENTRY_LS2 14 14 PLL_RO_HSCLK_LEFT_EN_GATING_EN 15 15 PLL_RO_HSCLK_RIGHT_EN_GATING_EN 16 16 PLL_LC_HSCLK_LEFT_EN_GATING_EN 17 17 PLL_LC_HSCLK_RIGHT_EN_GATING_EN 18 18 ixPB0_PLL_RO_GLB_OVRD_REG0 2 0x1204010 0 0 4294967295 ixPB0_PLL_RO0_CTRL_REG0 2 0x1204440 5 0 4294967295 PLL_DBG_RO_ANALOG_SEL_0 0 1 PLL_DBG_RO_EXT_RESET_EN_0 2 2 PLL_DBG_RO_VCTL_ADC_EN_0 3 3 PLL_DBG_RO_LF_CNTRL_0 4 10 PLL_TST_RO_USAMPLE_EN_0 11 11 ixPB0_PLL_RO0_OVRD_REG0 2 0x1204450 10 0 4294967295 PLL_CFG_RO_BW_CNTRL_OVRD_VAL_0 0 7 PLL_CFG_RO_BW_CNTRL_OVRD_EN_0 8 8 PLL_CFG_RO_CORECLK_DIV_OVRD_VAL_0 9 11 PLL_CFG_RO_CORECLK_DIV_OVRD_EN_0 12 12 PLL_CFG_RO_CORECLK_EN_OVRD_VAL_0 13 13 PLL_CFG_RO_CORECLK_EN_OVRD_EN_0 14 14 PLL_CFG_RO_FBDIV_OVRD_VAL_0 15 27 PLL_CFG_RO_FBDIV_OVRD_EN_0 28 28 PLL_CFG_RO_VTOI_BIAS_CNTRL_OVRD_VAL_0 30 30 PLL_CFG_RO_VTOI_BIAS_CNTRL_OVRD_EN_0 31 31 ixPB0_PLL_RO0_OVRD_REG1 2 0x1204454 12 0 4294967295 PLL_CFG_RO_REFDIV_OVRD_VAL_0 0 4 PLL_CFG_RO_REFDIV_OVRD_EN_0 5 5 PLL_CFG_RO_VCO_MODE_OVRD_VAL_0 6 7 PLL_CFG_RO_VCO_MODE_OVRD_EN_0 8 8 PLL_RO_HSCLK_LEFT_EN_OVRD_VAL_0 9 9 PLL_RO_HSCLK_LEFT_EN_OVRD_EN_0 10 10 PLL_RO_HSCLK_RIGHT_EN_OVRD_VAL_0 11 11 PLL_RO_HSCLK_RIGHT_EN_OVRD_EN_0 12 12 PLL_RO_PWRON_OVRD_VAL_0 13 13 PLL_RO_PWRON_OVRD_EN_0 14 14 PLL_CFG_RO_REFCLK_SRC_OVRD_VAL_0 19 21 PLL_CFG_RO_REFCLK_SRC_OVRD_EN_0 22 22 ixPB0_PLL_RO0_SCI_STAT_OVRD_REG0 2 0x1204460 4 0 4294967295 PLL_RO0_IGNR_PLLPWR_CBI_UPDT 0 0 PLL_RO0_IGNR_PLLFREQ_CBI_UPDT 1 1 PLL_RO0_PLLPWR 4 6 PLL_RO0_PLLFREQ 8 9 ixPB0_PLL_RO1_SCI_STAT_OVRD_REG0 2 0x1204464 4 0 4294967295 PLL_RO1_IGNR_PLLPWR_CBI_UPDT 0 0 PLL_RO1_IGNR_PLLFREQ_CBI_UPDT 1 1 PLL_RO1_PLLPWR 4 6 PLL_RO1_PLLFREQ 8 9 ixPB0_PLL_RO2_SCI_STAT_OVRD_REG0 2 0x1204468 4 0 4294967295 PLL_RO2_IGNR_PLLPWR_CBI_UPDT 0 0 PLL_RO2_IGNR_PLLFREQ_CBI_UPDT 1 1 PLL_RO2_PLLPWR 4 6 PLL_RO2_PLLFREQ 8 9 ixPB0_PLL_RO3_SCI_STAT_OVRD_REG0 2 0x120446c 4 0 4294967295 PLL_RO3_IGNR_PLLPWR_CBI_UPDT 0 0 PLL_RO3_IGNR_PLLFREQ_CBI_UPDT 1 1 PLL_RO3_PLLPWR 4 6 PLL_RO3_PLLFREQ 8 9 ixPB0_PLL_LC0_CTRL_REG0 2 0x1204480 4 0 4294967295 PLL_DBG_LC_ANALOG_SEL_0 0 1 PLL_DBG_LC_EXT_RESET_EN_0 2 2 PLL_DBG_LC_VCTL_ADC_EN_0 3 3 PLL_TST_LC_USAMPLE_EN_0 4 4 ixPB0_PLL_LC0_OVRD_REG0 2 0x1204490 12 0 4294967295 PLL_CFG_LC_BW_CNTRL_OVRD_VAL_0 0 2 PLL_CFG_LC_BW_CNTRL_OVRD_EN_0 3 3 PLL_CFG_LC_CORECLK_DIV_OVRD_VAL_0 4 6 PLL_CFG_LC_CORECLK_DIV_OVRD_EN_0 7 7 PLL_CFG_LC_CORECLK_EN_OVRD_VAL_0 8 8 PLL_CFG_LC_CORECLK_EN_OVRD_EN_0 9 9 PLL_CFG_LC_FBDIV_OVRD_VAL_0 10 17 PLL_CFG_LC_FBDIV_OVRD_EN_0 18 18 PLL_CFG_LC_LF_CNTRL_OVRD_VAL_0 19 27 PLL_CFG_LC_LF_CNTRL_OVRD_EN_0 28 28 PLL_CFG_LC_REFDIV_OVRD_VAL_0 29 30 PLL_CFG_LC_REFDIV_OVRD_EN_0 31 31 ixPB0_PLL_LC0_OVRD_REG1 2 0x1204494 10 0 4294967295 PLL_CFG_LC_REFCLK_SRC_OVRD_VAL_0 0 2 PLL_CFG_LC_REFCLK_SRC_OVRD_EN_0 3 3 PLL_LC_HSCLK_LEFT_EN_OVRD_VAL_0 4 4 PLL_LC_HSCLK_LEFT_EN_OVRD_EN_0 5 5 PLL_LC_HSCLK_RIGHT_EN_OVRD_VAL_0 6 6 PLL_LC_HSCLK_RIGHT_EN_OVRD_EN_0 7 7 PLL_LC_PWRON_OVRD_VAL_0 8 8 PLL_LC_PWRON_OVRD_EN_0 9 9 PLL_CFG_LC_VCO_TUNE_OVRD_VAL_0 14 17 PLL_CFG_LC_VCO_TUNE_OVRD_EN_0 18 18 ixPB0_PLL_LC0_SCI_STAT_OVRD_REG0 2 0x1204500 2 0 4294967295 PLL_LC0_IGNR_PLLPWR_CBI_UPDT 0 0 PLL_LC0_PLLPWR 4 6 ixPB0_PLL_LC1_SCI_STAT_OVRD_REG0 2 0x1204504 2 0 4294967295 PLL_LC1_IGNR_PLLPWR_CBI_UPDT 0 0 PLL_LC1_PLLPWR 4 6 ixPB0_PLL_LC2_SCI_STAT_OVRD_REG0 2 0x1204508 2 0 4294967295 PLL_LC2_IGNR_PLLPWR_CBI_UPDT 0 0 PLL_LC2_PLLPWR 4 6 ixPB0_PLL_LC3_SCI_STAT_OVRD_REG0 2 0x120450c 2 0 4294967295 PLL_LC3_IGNR_PLLPWR_CBI_UPDT 0 0 PLL_LC3_PLLPWR 4 6 ixPB0_RX_GLB_CTRL_REG0 2 0x1206000 3 0 4294967295 RX_CFG_ADAPT_MODE_GEN1 0 9 RX_CFG_ADAPT_MODE_GEN2 10 19 RX_CFG_ADAPT_MODE_GEN3 20 29 ixPB0_RX_GLB_CTRL_REG1 2 0x1206004 13 0 4294967295 RX_CFG_CDR_FR_GAIN_GEN1 0 3 RX_CFG_CDR_FR_GAIN_GEN2 4 7 RX_CFG_CDR_FR_GAIN_GEN3 8 11 RX_CFG_CDR_PH_GAIN_GEN1 12 15 RX_CFG_CDR_PH_GAIN_GEN2 16 19 RX_CFG_CDR_PH_GAIN_GEN3 20 23 RX_CFG_CDR_PI_STPSZ_GEN1 24 24 RX_CFG_CDR_PI_STPSZ_GEN2 25 25 RX_CFG_CDR_PI_STPSZ_GEN3 26 26 RX_CFG_LEQ_DCATTN_BYP_EN_GEN1 27 27 RX_CFG_LEQ_DCATTN_BYP_EN_GEN2 28 28 RX_CFG_LEQ_DCATTN_BYP_EN_GEN3 29 29 RX_ADAPT_HLD_ASRT_TO_DCLK_EN 30 31 ixPB0_RX_GLB_CTRL_REG2 2 0x1206008 7 0 4294967295 RX_CFG_CDR_TIME_GEN1 12 15 RX_CFG_CDR_TIME_GEN2 16 19 RX_CFG_CDR_TIME_GEN3 20 23 RX_CFG_LEQ_LOOP_GAIN_GEN1 24 25 RX_CFG_LEQ_LOOP_GAIN_GEN2 26 27 RX_CFG_LEQ_LOOP_GAIN_GEN3 28 29 RX_DCLK_EN_ASRT_TO_ADAPT_HLD 30 31 ixPB0_RX_GLB_CTRL_REG3 2 0x120600c 13 0 4294967295 RX_CFG_CDR_FR_EN_GEN1 0 0 RX_CFG_CDR_FR_EN_GEN2 1 1 RX_CFG_CDR_FR_EN_GEN3 2 2 RX_ADAPT_RST_MODE_GEN1 3 4 RX_ADAPT_RST_MODE_GEN2 5 6 RX_ADAPT_RST_MODE_GEN3 7 8 RX_ADAPT_RST_SUB_MODE 9 11 RX_L0_ENTRY_MODE_GEN1 12 13 RX_L0_ENTRY_MODE_GEN2 14 15 RX_L0_ENTRY_MODE_GEN3 16 17 RX_CFG_DFE_TIME_GEN1 20 23 RX_CFG_DFE_TIME_GEN2 24 27 RX_CFG_DFE_TIME_GEN3 28 31 ixPB0_RX_GLB_CTRL_REG4 2 0x1206010 9 0 4294967295 RX_CFG_FOM_BER_GEN1 0 2 RX_CFG_FOM_BER_GEN2 3 5 RX_CFG_FOM_BER_GEN3 6 8 RX_CFG_LEQ_POLE_BYP_VAL_GEN1 9 11 RX_CFG_LEQ_POLE_BYP_VAL_GEN2 12 14 RX_CFG_LEQ_POLE_BYP_VAL_GEN3 15 17 RX_CFG_FOM_TIME_GEN1 20 23 RX_CFG_FOM_TIME_GEN2 24 27 RX_CFG_FOM_TIME_GEN3 28 31 ixPB0_RX_GLB_CTRL_REG5 2 0x1206014 13 0 4294967295 RX_CFG_LEQ_DCATTN_BYP_VAL_GEN1 0 4 RX_CFG_LEQ_DCATTN_BYP_VAL_GEN2 5 9 RX_CFG_LEQ_DCATTN_BYP_VAL_GEN3 10 14 RX_CFG_LEQ_POLE_BYP_EN_GEN1 15 15 RX_CFG_LEQ_POLE_BYP_EN_GEN2 16 16 RX_CFG_LEQ_POLE_BYP_EN_GEN3 17 17 RX_CFG_LEQ_SHUNT_EN_GEN1 18 18 RX_CFG_LEQ_SHUNT_EN_GEN2 19 19 RX_CFG_LEQ_SHUNT_EN_GEN3 20 20 RX_CFG_TERM_MODE_GEN1 27 27 RX_CFG_TERM_MODE_GEN2 28 28 RX_CFG_TERM_MODE_GEN3 29 29 RX_ADAPT_AUX_PWRON_MODE 31 31 ixPB0_RX_GLB_CTRL_REG6 2 0x1206018 11 0 4294967295 RX_CFG_LEQ_TIME_GEN1 0 3 RX_CFG_LEQ_TIME_GEN2 4 7 RX_CFG_LEQ_TIME_GEN3 8 11 RX_CFG_OC_TIME_GEN1 12 15 RX_CFG_OC_TIME_GEN2 16 19 RX_CFG_OC_TIME_GEN3 20 23 RX_FRONTEND_PWRON_LUT_ENTRY_LS0_CDR_EN_0 24 24 RX_FRONTEND_PWRON_LUT_ENTRY_LS2 26 26 RX_AUX_PWRON_LUT_ENTRY_LS2 27 27 RX_ADAPT_HLD_L0S_EARLY_EXIT_DIS 28 28 RX_ADAPT_HLD_L1_DLL_OFF 29 29 ixPB0_RX_GLB_CTRL_REG7 2 0x120601c 14 0 4294967295 RX_CFG_TH_LOOP_GAIN_GEN1 0 3 RX_CFG_TH_LOOP_GAIN_GEN2 4 7 RX_CFG_TH_LOOP_GAIN_GEN3 8 11 RX_DCLK_EN_LUT_ENTRY_LS0_CDR_EN_0 12 12 RX_DCLK_EN_LUT_ENTRY_LS2 13 13 RX_DCLK_EN_AFTER_DLL_LOCK 14 14 RX_DLL_PWRON_LUT_ENTRY_PS3 16 16 RX_DLL_PWRON_LUT_ENTRY_PS2 17 17 RX_CFG_DLL_CPI_SEL_GEN1 18 20 RX_CFG_DLL_CPI_SEL_GEN2 21 23 RX_CFG_DLL_CPI_SEL_GEN3 24 26 RX_CFG_DLL_FLOCK_DISABLE_GEN1 27 27 RX_CFG_DLL_FLOCK_DISABLE_GEN2 28 28 RX_CFG_DLL_FLOCK_DISABLE_GEN3 29 29 ixPB0_RX_GLB_CTRL_REG8 2 0x1206020 4 0 4294967295 RX_DLL_LOCK_TIME 0 1 RX_DLL_SPEEDCHANGE_RESET_TIME 2 3 RX_DLL_PWRON_IN_RAMPDOWN 4 4 RX_FSM_L0S_IF_RX_RDY 5 5 ixPB0_RX_GLB_SCI_STAT_OVRD_REG0 2 0x1206028 24 0 4294967295 IGNR_RXPWR_CBI_UPDT_L0T3 0 0 IGNR_RXPWR_CBI_UPDT_L4T7 1 1 IGNR_RXPWR_CBI_UPDT_L8T11 2 2 IGNR_RXPWR_CBI_UPDT_L12T15 3 3 IGNR_ELECIDLEDETEN_CBI_UPDT_L0T3 4 4 IGNR_ELECIDLEDETEN_CBI_UPDT_L4T7 5 5 IGNR_ELECIDLEDETEN_CBI_UPDT_L8T11 6 6 IGNR_ELECIDLEDETEN_CBI_UPDT_L12T15 7 7 IGNR_REQUESTTRK_CBI_UPDT_L0T3 8 8 IGNR_REQUESTTRK_CBI_UPDT_L4T7 9 9 IGNR_REQUESTTRK_CBI_UPDT_L8T11 10 10 IGNR_REQUESTTRK_CBI_UPDT_L12T15 11 11 IGNR_ENABLEFOM_CBI_UPDT_L0T3 12 12 IGNR_ENABLEFOM_CBI_UPDT_L4T7 13 13 IGNR_ENABLEFOM_CBI_UPDT_L8T11 14 14 IGNR_ENABLEFOM_CBI_UPDT_L12T15 15 15 IGNR_REQUESTFOM_CBI_UPDT_L0T3 16 16 IGNR_REQUESTFOM_CBI_UPDT_L4T7 17 17 IGNR_REQUESTFOM_CBI_UPDT_L8T11 18 18 IGNR_REQUESTFOM_CBI_UPDT_L12T15 19 19 IGNR_RESPONSEMODE_CBI_UPDT_L0T3 20 20 IGNR_RESPONSEMODE_CBI_UPDT_L4T7 21 21 IGNR_RESPONSEMODE_CBI_UPDT_L8T11 22 22 IGNR_RESPONSEMODE_CBI_UPDT_L12T15 23 23 ixPB0_RX_GLB_OVRD_REG0 2 0x1206030 24 0 4294967295 RX_ADAPT_HLD_OVRD_VAL 0 0 RX_ADAPT_HLD_OVRD_EN 1 1 RX_ADAPT_RST_OVRD_VAL 2 2 RX_ADAPT_RST_OVRD_EN 3 3 RX_CFG_DCLK_DIV_OVRD_VAL 6 7 RX_CFG_DCLK_DIV_OVRD_EN 8 8 RX_CFG_DLL_FREQ_MODE_OVRD_VAL 9 9 RX_CFG_DLL_FREQ_MODE_OVRD_EN 10 10 RX_CFG_PLLCLK_SEL_OVRD_VAL 11 11 RX_CFG_PLLCLK_SEL_OVRD_EN 12 12 RX_CFG_RCLK_DIV_OVRD_VAL 13 13 RX_CFG_RCLK_DIV_OVRD_EN 14 14 RX_DCLK_EN_OVRD_VAL 15 15 RX_DCLK_EN_OVRD_EN 16 16 RX_DLL_PWRON_OVRD_VAL 17 17 RX_DLL_PWRON_OVRD_EN 18 18 RX_FRONTEND_PWRON_OVRD_VAL 19 19 RX_FRONTEND_PWRON_OVRD_EN 20 20 RX_IDLEDET_PWRON_OVRD_VAL 21 21 RX_IDLEDET_PWRON_OVRD_EN 22 22 RX_AUX_PWRON_OVRD_VAL 28 28 RX_AUX_PWRON_OVRD_EN 29 29 RX_ADAPT_FOM_OVRD_VAL 30 30 RX_ADAPT_FOM_OVRD_EN 31 31 ixPB0_RX_GLB_OVRD_REG1 2 0x1206034 2 0 4294967295 RX_ADAPT_TRK_OVRD_VAL 0 0 RX_ADAPT_TRK_OVRD_EN 1 1 ixPB0_RX_LANE0_CTRL_REG0 2 0x1206440 5 0 4294967295 RX_BACKUP_0 0 7 RX_DBG_ANALOG_SEL_0 10 11 RX_TST_BSCAN_EN_0 12 12 RX_CFG_OVR_PWRSF_0 13 13 RX_TERM_EN_0 14 14 ixPB0_RX_LANE0_SCI_STAT_OVRD_REG0 2 0x1206448 7 0 4294967295 RXPWR_0 0 2 ELECIDLEDETEN_0 3 3 REQUESTTRK_0 6 6 ENABLEFOM_0 7 7 REQUESTFOM_0 8 8 RESPONSEMODE_0 9 9 RXEYEFOM_0 10 17 ixPB0_RX_LANE1_CTRL_REG0 2 0x1206480 5 0 4294967295 RX_BACKUP_1 0 7 RX_DBG_ANALOG_SEL_1 10 11 RX_TST_BSCAN_EN_1 12 12 RX_CFG_OVR_PWRSF_1 13 13 RX_TERM_EN_1 14 14 ixPB0_RX_LANE1_SCI_STAT_OVRD_REG0 2 0x1206488 7 0 4294967295 RXPWR_1 0 2 ELECIDLEDETEN_1 3 3 REQUESTTRK_1 6 6 ENABLEFOM_1 7 7 REQUESTFOM_1 8 8 RESPONSEMODE_1 9 9 RXEYEFOM_1 10 17 ixPB0_RX_LANE2_CTRL_REG0 2 0x1206500 5 0 4294967295 RX_BACKUP_2 0 7 RX_DBG_ANALOG_SEL_2 10 11 RX_TST_BSCAN_EN_2 12 12 RX_CFG_OVR_PWRSF_2 13 13 RX_TERM_EN_2 14 14 ixPB0_RX_LANE2_SCI_STAT_OVRD_REG0 2 0x1206508 7 0 4294967295 RXPWR_2 0 2 ELECIDLEDETEN_2 3 3 REQUESTTRK_2 6 6 ENABLEFOM_2 7 7 REQUESTFOM_2 8 8 RESPONSEMODE_2 9 9 RXEYEFOM_2 10 17 ixPB0_RX_LANE3_CTRL_REG0 2 0x1206600 5 0 4294967295 RX_BACKUP_3 0 7 RX_DBG_ANALOG_SEL_3 10 11 RX_TST_BSCAN_EN_3 12 12 RX_CFG_OVR_PWRSF_3 13 13 RX_TERM_EN_3 14 14 ixPB0_RX_LANE3_SCI_STAT_OVRD_REG0 2 0x1206608 7 0 4294967295 RXPWR_3 0 2 ELECIDLEDETEN_3 3 3 REQUESTTRK_3 6 6 ENABLEFOM_3 7 7 REQUESTFOM_3 8 8 RESPONSEMODE_3 9 9 RXEYEFOM_3 10 17 ixPB0_RX_LANE4_CTRL_REG0 2 0x1206800 5 0 4294967295 RX_BACKUP_4 0 7 RX_DBG_ANALOG_SEL_4 10 11 RX_TST_BSCAN_EN_4 12 12 RX_CFG_OVR_PWRSF_4 13 13 RX_TERM_EN_4 14 14 ixPB0_RX_LANE4_SCI_STAT_OVRD_REG0 2 0x1206848 7 0 4294967295 RXPWR_4 0 2 ELECIDLEDETEN_4 3 3 REQUESTTRK_4 6 6 ENABLEFOM_4 7 7 REQUESTFOM_4 8 8 RESPONSEMODE_4 9 9 RXEYEFOM_4 10 17 ixPB0_RX_LANE5_CTRL_REG0 2 0x1206880 5 0 4294967295 RX_BACKUP_5 0 7 RX_DBG_ANALOG_SEL_5 10 11 RX_TST_BSCAN_EN_5 12 12 RX_CFG_OVR_PWRSF_5 13 13 RX_TERM_EN_5 14 14 ixPB0_RX_LANE5_SCI_STAT_OVRD_REG0 2 0x1206888 7 0 4294967295 RXPWR_5 0 2 ELECIDLEDETEN_5 3 3 REQUESTTRK_5 6 6 ENABLEFOM_5 7 7 REQUESTFOM_5 8 8 RESPONSEMODE_5 9 9 RXEYEFOM_5 10 17 ixPB0_RX_LANE6_CTRL_REG0 2 0x1206900 5 0 4294967295 RX_BACKUP_6 0 7 RX_DBG_ANALOG_SEL_6 10 11 RX_TST_BSCAN_EN_6 12 12 RX_CFG_OVR_PWRSF_6 13 13 RX_TERM_EN_6 14 14 ixPB0_RX_LANE6_SCI_STAT_OVRD_REG0 2 0x1206908 7 0 4294967295 RXPWR_6 0 2 ELECIDLEDETEN_6 3 3 REQUESTTRK_6 6 6 ENABLEFOM_6 7 7 REQUESTFOM_6 8 8 RESPONSEMODE_6 9 9 RXEYEFOM_6 10 17 ixPB0_RX_LANE7_CTRL_REG0 2 0x1206a00 5 0 4294967295 RX_BACKUP_7 0 7 RX_DBG_ANALOG_SEL_7 10 11 RX_TST_BSCAN_EN_7 12 12 RX_CFG_OVR_PWRSF_7 13 13 RX_TERM_EN_7 14 14 ixPB0_RX_LANE7_SCI_STAT_OVRD_REG0 2 0x1206a08 7 0 4294967295 RXPWR_7 0 2 ELECIDLEDETEN_7 3 3 REQUESTTRK_7 6 6 ENABLEFOM_7 7 7 REQUESTFOM_7 8 8 RESPONSEMODE_7 9 9 RXEYEFOM_7 10 17 ixPB0_RX_LANE8_CTRL_REG0 2 0x1207440 5 0 4294967295 RX_BACKUP_8 0 7 RX_DBG_ANALOG_SEL_8 10 11 RX_TST_BSCAN_EN_8 12 12 RX_CFG_OVR_PWRSF_8 13 13 RX_TERM_EN_8 14 14 ixPB0_RX_LANE8_SCI_STAT_OVRD_REG0 2 0x1207448 7 0 4294967295 RXPWR_8 0 2 ELECIDLEDETEN_8 3 3 REQUESTTRK_8 6 6 ENABLEFOM_8 7 7 REQUESTFOM_8 8 8 RESPONSEMODE_8 9 9 RXEYEFOM_8 10 17 ixPB0_RX_LANE9_CTRL_REG0 2 0x1207480 5 0 4294967295 RX_BACKUP_9 0 7 RX_DBG_ANALOG_SEL_9 10 11 RX_TST_BSCAN_EN_9 12 12 RX_CFG_OVR_PWRSF_9 13 13 RX_TERM_EN_9 14 14 ixPB0_RX_LANE9_SCI_STAT_OVRD_REG0 2 0x1207488 7 0 4294967295 RXPWR_9 0 2 ELECIDLEDETEN_9 3 3 REQUESTTRK_9 6 6 ENABLEFOM_9 7 7 REQUESTFOM_9 8 8 RESPONSEMODE_9 9 9 RXEYEFOM_9 10 17 ixPB0_RX_LANE10_CTRL_REG0 2 0x1207500 5 0 4294967295 RX_BACKUP_10 0 7 RX_DBG_ANALOG_SEL_10 10 11 RX_TST_BSCAN_EN_10 12 12 RX_CFG_OVR_PWRSF_10 13 13 RX_TERM_EN_10 14 14 ixPB0_RX_LANE10_SCI_STAT_OVRD_REG0 2 0x1207508 7 0 4294967295 RXPWR_10 0 2 ELECIDLEDETEN_10 3 3 REQUESTTRK_10 6 6 ENABLEFOM_10 7 7 REQUESTFOM_10 8 8 RESPONSEMODE_10 9 9 RXEYEFOM_10 10 17 ixPB0_RX_LANE11_CTRL_REG0 2 0x1207600 5 0 4294967295 RX_BACKUP_11 0 7 RX_DBG_ANALOG_SEL_11 10 11 RX_TST_BSCAN_EN_11 12 12 RX_CFG_OVR_PWRSF_11 13 13 RX_TERM_EN_11 14 14 ixPB0_RX_LANE11_SCI_STAT_OVRD_REG0 2 0x1207608 7 0 4294967295 RXPWR_11 0 2 ELECIDLEDETEN_11 3 3 REQUESTTRK_11 6 6 ENABLEFOM_11 7 7 REQUESTFOM_11 8 8 RESPONSEMODE_11 9 9 RXEYEFOM_11 10 17 ixPB0_RX_LANE12_CTRL_REG0 2 0x1207840 5 0 4294967295 RX_BACKUP_12 0 7 RX_DBG_ANALOG_SEL_12 10 11 RX_TST_BSCAN_EN_12 12 12 RX_CFG_OVR_PWRSF_12 13 13 RX_TERM_EN_12 14 14 ixPB0_RX_LANE12_SCI_STAT_OVRD_REG0 2 0x1207848 7 0 4294967295 RXPWR_12 0 2 ELECIDLEDETEN_12 3 3 REQUESTTRK_12 6 6 ENABLEFOM_12 7 7 REQUESTFOM_12 8 8 RESPONSEMODE_12 9 9 RXEYEFOM_12 10 17 ixPB0_RX_LANE13_CTRL_REG0 2 0x1207880 5 0 4294967295 RX_BACKUP_13 0 7 RX_DBG_ANALOG_SEL_13 10 11 RX_TST_BSCAN_EN_13 12 12 RX_CFG_OVR_PWRSF_13 13 13 RX_TERM_EN_13 14 14 ixPB0_RX_LANE13_SCI_STAT_OVRD_REG0 2 0x1207888 7 0 4294967295 RXPWR_13 0 2 ELECIDLEDETEN_13 3 3 REQUESTTRK_13 6 6 ENABLEFOM_13 7 7 REQUESTFOM_13 8 8 RESPONSEMODE_13 9 9 RXEYEFOM_13 10 17 ixPB0_RX_LANE14_CTRL_REG0 2 0x1207900 5 0 4294967295 RX_BACKUP_14 0 7 RX_DBG_ANALOG_SEL_14 10 11 RX_TST_BSCAN_EN_14 12 12 RX_CFG_OVR_PWRSF_14 13 13 RX_TERM_EN_14 14 14 ixPB0_RX_LANE14_SCI_STAT_OVRD_REG0 2 0x1207908 7 0 4294967295 RXPWR_14 0 2 ELECIDLEDETEN_14 3 3 REQUESTTRK_14 6 6 ENABLEFOM_14 7 7 REQUESTFOM_14 8 8 RESPONSEMODE_14 9 9 RXEYEFOM_14 10 17 ixPB0_RX_LANE15_CTRL_REG0 2 0x1207a00 5 0 4294967295 RX_BACKUP_15 0 7 RX_DBG_ANALOG_SEL_15 10 11 RX_TST_BSCAN_EN_15 12 12 RX_CFG_OVR_PWRSF_15 13 13 RX_TERM_EN_15 14 14 ixPB0_RX_LANE15_SCI_STAT_OVRD_REG0 2 0x1207a08 7 0 4294967295 RXPWR_15 0 2 ELECIDLEDETEN_15 3 3 REQUESTTRK_15 6 6 ENABLEFOM_15 7 7 REQUESTFOM_15 8 8 RESPONSEMODE_15 9 9 RXEYEFOM_15 10 17 ixPB0_TX_GLB_CTRL_REG0 2 0x1208000 12 0 4294967295 TX_DRV_DATA_ASRT_DLY_VAL 0 2 TX_DRV_DATA_DSRT_DLY_VAL 3 5 TX_CFG_RPTR_RST_VAL_GEN1 8 10 TX_CFG_RPTR_RST_VAL_GEN2 11 13 TX_CFG_RPTR_RST_VAL_GEN3 14 16 TX_STAGGER_CTRL 17 18 TX_DATA_CLK_GATING 19 19 TX_PRESET_TABLE_BYPASS 20 20 TX_COEFF_ROUND_EN 21 21 TX_COEFF_ROUND_DIR_VER 22 22 TX_DCLK_EN_LSX_ALWAYS_ON 23 23 TX_FRONTEND_PWRON_IN_PS4 24 24 ixPB0_TX_GLB_LANE_SKEW_CTRL 2 0x1208004 31 0 4294967295 TX_CFG_GROUPX1_EN_0 0 0 TX_CFG_GROUPX1_EN_1 1 1 TX_CFG_GROUPX1_EN_2 2 2 TX_CFG_GROUPX1_EN_3 3 3 TX_CFG_GROUPX1_EN_4 4 4 TX_CFG_GROUPX1_EN_5 5 5 TX_CFG_GROUPX1_EN_6 6 6 TX_CFG_GROUPX1_EN_7 7 7 TX_CFG_GROUPX1_EN_8 8 8 TX_CFG_GROUPX1_EN_9 9 9 TX_CFG_GROUPX1_EN_10 10 10 TX_CFG_GROUPX1_EN_11 11 11 TX_CFG_GROUPX1_EN_12 12 12 TX_CFG_GROUPX1_EN_13 13 13 TX_CFG_GROUPX1_EN_14 14 14 TX_CFG_GROUPX1_EN_15 15 15 TX_CFG_GROUPX2_EN_L0T1 16 16 TX_CFG_GROUPX2_EN_L2T3 17 17 TX_CFG_GROUPX2_EN_L4T5 18 18 TX_CFG_GROUPX2_EN_L6T7 19 19 TX_CFG_GROUPX2_EN_L8T9 20 20 TX_CFG_GROUPX2_EN_L10T11 21 21 TX_CFG_GROUPX2_EN_L12T13 22 22 TX_CFG_GROUPX2_EN_L14T15 23 23 TX_CFG_GROUPX4_EN_L0T3 24 24 TX_CFG_GROUPX4_EN_L4T7 25 25 TX_CFG_GROUPX4_EN_L8T11 26 26 TX_CFG_GROUPX4_EN_L12T15 27 27 TX_CFG_GROUPX8_EN_L0T7 28 28 TX_CFG_GROUPX8_EN_L8T15 29 29 TX_CFG_GROUPX16_EN_L0T15 30 30 ixPB0_TX_GLB_SCI_STAT_OVRD_REG0 2 0x1208010 12 0 4294967295 IGNR_TXPWR_CBI_UPDT_L0T3 0 0 IGNR_TXPWR_CBI_UPDT_L4T7 1 1 IGNR_TXPWR_CBI_UPDT_L8T11 2 2 IGNR_TXPWR_CBI_UPDT_L12T15 3 3 IGNR_COEFFICIENTID_CBI_UPDT_L0T3 8 8 IGNR_COEFFICIENTID_CBI_UPDT_L4T7 9 9 IGNR_COEFFICIENTID_CBI_UPDT_L8T11 10 10 IGNR_COEFFICIENTID_CBI_UPDT_L12T15 11 11 IGNR_COEFFICIENT_CBI_UPDT_L0T3 12 12 IGNR_COEFFICIENT_CBI_UPDT_L4T7 13 13 IGNR_COEFFICIENT_CBI_UPDT_L8T11 14 14 IGNR_COEFFICIENT_CBI_UPDT_L12T15 15 15 ixPB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0 2 0x1208014 32 0 4294967295 ACCEPT_ENTRY_0 0 0 ACCEPT_ENTRY_1 1 1 ACCEPT_ENTRY_2 2 2 ACCEPT_ENTRY_3 3 3 ACCEPT_ENTRY_4 4 4 ACCEPT_ENTRY_5 5 5 ACCEPT_ENTRY_6 6 6 ACCEPT_ENTRY_7 7 7 ACCEPT_ENTRY_8 8 8 ACCEPT_ENTRY_9 9 9 ACCEPT_ENTRY_10 10 10 ACCEPT_ENTRY_11 11 11 ACCEPT_ENTRY_12 12 12 ACCEPT_ENTRY_13 13 13 ACCEPT_ENTRY_14 14 14 ACCEPT_ENTRY_15 15 15 ACCEPT_ENTRY_16 16 16 ACCEPT_ENTRY_17 17 17 ACCEPT_ENTRY_18 18 18 ACCEPT_ENTRY_19 19 19 ACCEPT_ENTRY_20 20 20 ACCEPT_ENTRY_21 21 21 ACCEPT_ENTRY_22 22 22 ACCEPT_ENTRY_23 23 23 ACCEPT_ENTRY_24 24 24 ACCEPT_ENTRY_25 25 25 ACCEPT_ENTRY_26 26 26 ACCEPT_ENTRY_27 27 27 ACCEPT_ENTRY_28 28 28 ACCEPT_ENTRY_29 29 29 ACCEPT_ENTRY_30 30 30 ACCEPT_ENTRY_31 31 31 ixPB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1 2 0x1208018 32 0 4294967295 ACCEPT_ENTRY_32 0 0 ACCEPT_ENTRY_33 1 1 ACCEPT_ENTRY_34 2 2 ACCEPT_ENTRY_35 3 3 ACCEPT_ENTRY_36 4 4 ACCEPT_ENTRY_37 5 5 ACCEPT_ENTRY_38 6 6 ACCEPT_ENTRY_39 7 7 ACCEPT_ENTRY_40 8 8 ACCEPT_ENTRY_41 9 9 ACCEPT_ENTRY_42 10 10 ACCEPT_ENTRY_43 11 11 ACCEPT_ENTRY_44 12 12 ACCEPT_ENTRY_45 13 13 ACCEPT_ENTRY_46 14 14 ACCEPT_ENTRY_47 15 15 ACCEPT_ENTRY_48 16 16 ACCEPT_ENTRY_49 17 17 ACCEPT_ENTRY_50 18 18 ACCEPT_ENTRY_51 19 19 ACCEPT_ENTRY_52 20 20 ACCEPT_ENTRY_53 21 21 ACCEPT_ENTRY_54 22 22 ACCEPT_ENTRY_55 23 23 ACCEPT_ENTRY_56 24 24 ACCEPT_ENTRY_57 25 25 ACCEPT_ENTRY_58 26 26 ACCEPT_ENTRY_59 27 27 ACCEPT_ENTRY_60 28 28 ACCEPT_ENTRY_61 29 29 ACCEPT_ENTRY_62 30 30 ACCEPT_ENTRY_63 31 31 ixPB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2 2 0x120801c 32 0 4294967295 ACCEPT_ENTRY_64 0 0 ACCEPT_ENTRY_65 1 1 ACCEPT_ENTRY_66 2 2 ACCEPT_ENTRY_67 3 3 ACCEPT_ENTRY_68 4 4 ACCEPT_ENTRY_69 5 5 ACCEPT_ENTRY_70 6 6 ACCEPT_ENTRY_71 7 7 ACCEPT_ENTRY_72 8 8 ACCEPT_ENTRY_73 9 9 ACCEPT_ENTRY_74 10 10 ACCEPT_ENTRY_75 11 11 ACCEPT_ENTRY_76 12 12 ACCEPT_ENTRY_77 13 13 ACCEPT_ENTRY_78 14 14 ACCEPT_ENTRY_79 15 15 ACCEPT_ENTRY_80 16 16 ACCEPT_ENTRY_81 17 17 ACCEPT_ENTRY_82 18 18 ACCEPT_ENTRY_83 19 19 ACCEPT_ENTRY_84 20 20 ACCEPT_ENTRY_85 21 21 ACCEPT_ENTRY_86 22 22 ACCEPT_ENTRY_87 23 23 ACCEPT_ENTRY_88 24 24 ACCEPT_ENTRY_89 25 25 ACCEPT_ENTRY_90 26 26 ACCEPT_ENTRY_91 27 27 ACCEPT_ENTRY_92 28 28 ACCEPT_ENTRY_93 29 29 ACCEPT_ENTRY_94 30 30 ACCEPT_ENTRY_95 31 31 ixPB0_TX_GLB_COEFF_ACCEPT_TABLE_REG3 2 0x1208020 14 0 4294967295 ACCEPT_ENTRY_96 0 0 ACCEPT_ENTRY_97 1 1 ACCEPT_ENTRY_98 2 2 ACCEPT_ENTRY_99 3 3 ACCEPT_ENTRY_100 4 4 ACCEPT_ENTRY_101 5 5 ACCEPT_ENTRY_102 6 6 ACCEPT_ENTRY_103 7 7 ACCEPT_ENTRY_104 8 8 ACCEPT_ENTRY_105 9 9 ACCEPT_ENTRY_106 10 10 ACCEPT_ENTRY_107 11 11 ACCEPT_ENTRY_108 12 12 ACCEPT_ENTRY_109 13 13 ixPB0_TX_GLB_OVRD_REG0 2 0x1208030 12 0 4294967295 TX_CFG_DCLK_DIV_OVRD_VAL 0 2 TX_CFG_DCLK_DIV_OVRD_EN 3 3 TX_CFG_DRV0_EN_GEN1_OVRD_VAL 4 7 TX_CFG_DRV0_EN_OVRD_EN 8 8 TX_CFG_DRV0_TAP_SEL_GEN1_OVRD_VAL 9 12 TX_CFG_DRV0_TAP_SEL_OVRD_EN 13 13 TX_CFG_DRV1_EN_GEN1_OVRD_VAL 14 18 TX_CFG_DRV1_EN_OVRD_EN 19 19 TX_CFG_DRV1_TAP_SEL_GEN1_OVRD_VAL 20 24 TX_CFG_DRV1_TAP_SEL_OVRD_EN 25 25 TX_CFG_DRV2_EN_GEN1_OVRD_VAL 26 29 TX_CFG_DRV2_EN_OVRD_EN 30 30 ixPB0_TX_GLB_OVRD_REG1 2 0x1208034 20 0 4294967295 TX_CFG_DRV2_TAP_SEL_GEN1_OVRD_VAL 0 3 TX_CFG_DRV2_TAP_SEL_OVRD_EN 4 4 TX_CFG_DRVX_EN_GEN1_OVRD_VAL 5 5 TX_CFG_DRVX_EN_OVRD_EN 6 6 TX_CFG_DRVX_TAP_SEL_GEN1_OVRD_VAL 7 7 TX_CFG_DRVX_TAP_SEL_OVRD_EN 8 8 TX_CFG_PLLCLK_SEL_OVRD_VAL 9 9 TX_CFG_PLLCLK_SEL_OVRD_EN 10 10 TX_CFG_TCLK_DIV_OVRD_VAL 11 11 TX_CFG_TCLK_DIV_OVRD_EN 12 12 TX_CMDET_EN_OVRD_VAL 13 13 TX_CMDET_EN_OVRD_EN 14 14 TX_DATA_IN_OVRD_VAL 15 24 TX_DATA_IN_OVRD_EN 25 25 TX_RPTR_RSTN_OVRD_VAL 26 26 TX_RPTR_RSTN_OVRD_EN 27 27 TX_RXDET_EN_OVRD_VAL 28 28 TX_RXDET_EN_OVRD_EN 29 29 TX_WPTR_RSTN_OVRD_VAL 30 30 TX_WPTR_RSTN_OVRD_EN 31 31 ixPB0_TX_GLB_OVRD_REG2 2 0x1208038 16 0 4294967295 TX_WRITE_EN_OVRD_VAL 0 0 TX_WRITE_EN_OVRD_EN 1 1 TX_CFG_GROUPX1_EN_OVRD_VAL 2 2 TX_CFG_GROUPX1_EN_OVRD_EN 3 3 TX_CFG_GROUPX2_EN_OVRD_VAL 4 4 TX_CFG_GROUPX2_EN_OVRD_EN 5 5 TX_CFG_GROUPX4_EN_OVRD_VAL 6 6 TX_CFG_GROUPX4_EN_OVRD_EN 7 7 TX_CFG_GROUPX8_EN_OVRD_VAL 8 8 TX_CFG_GROUPX8_EN_OVRD_EN 9 9 TX_CFG_GROUPX16_EN_OVRD_VAL 10 10 TX_CFG_GROUPX16_EN_OVRD_EN 11 11 TX_CFG_DRV0_EN_GEN2_OVRD_VAL 12 15 TX_CFG_DRV0_TAP_SEL_GEN2_OVRD_VAL 16 19 TX_CFG_DRV1_EN_GEN2_OVRD_VAL 20 24 TX_CFG_DRV1_TAP_SEL_GEN2_OVRD_VAL 25 29 ixPB0_TX_GLB_OVRD_REG3 2 0x120803c 9 0 4294967295 TX_CFG_DRV2_EN_GEN2_OVRD_VAL 0 3 TX_CFG_DRV2_TAP_SEL_GEN2_OVRD_VAL 4 7 TX_CFG_DRVX_EN_GEN2_OVRD_VAL 8 8 TX_CFG_DRVX_TAP_SEL_GEN2_OVRD_VAL 9 9 TX_CFG_DRV0_EN_GEN3_OVRD_VAL 10 13 TX_CFG_DRV0_TAP_SEL_GEN3_OVRD_VAL 14 17 TX_CFG_DRV1_EN_GEN3_OVRD_VAL 18 22 TX_CFG_DRV1_TAP_SEL_GEN3_OVRD_VAL 23 27 TX_CFG_DRV2_EN_GEN3_OVRD_VAL 28 31 ixPB0_TX_GLB_OVRD_REG4 2 0x1208040 3 0 4294967295 TX_CFG_DRV2_TAP_SEL_GEN3_OVRD_VAL 0 3 TX_CFG_DRVX_EN_GEN3_OVRD_VAL 4 4 TX_CFG_DRVX_TAP_SEL_GEN3_OVRD_VAL 5 5 ixPB0_TX_LANE0_CTRL_REG0 2 0x1208440 4 0 4294967295 TX_CFG_DISPCLK_MODE_0 0 0 TX_CFG_INV_DATA_0 1 1 TX_CFG_SWING_BOOST_EN_0 2 2 TX_DBG_PRBS_EN_0 3 3 ixPB0_TX_LANE0_OVRD_REG0 2 0x1208444 8 0 4294967295 TX_DCLK_EN_OVRD_VAL_0 0 0 TX_DCLK_EN_OVRD_EN_0 1 1 TX_DRV_DATA_EN_OVRD_VAL_0 2 2 TX_DRV_DATA_EN_OVRD_EN_0 3 3 TX_DRV_PWRON_OVRD_VAL_0 4 4 TX_DRV_PWRON_OVRD_EN_0 5 5 TX_FRONTEND_PWRON_OVRD_VAL_0 6 6 TX_FRONTEND_PWRON_OVRD_EN_0 7 7 ixPB0_TX_LANE0_SCI_STAT_OVRD_REG0 2 0x1208448 5 0 4294967295 TXPWR_0 0 2 TXMARG_0 4 6 DEEMPH_0 7 7 COEFFICIENTID_0 8 9 COEFFICIENT_0 10 15 ixPB0_TX_LANE1_CTRL_REG0 2 0x1208480 4 0 4294967295 TX_CFG_DISPCLK_MODE_1 0 0 TX_CFG_INV_DATA_1 1 1 TX_CFG_SWING_BOOST_EN_1 2 2 TX_DBG_PRBS_EN_1 3 3 ixPB0_TX_LANE1_OVRD_REG0 2 0x1208484 8 0 4294967295 TX_DCLK_EN_OVRD_VAL_1 0 0 TX_DCLK_EN_OVRD_EN_1 1 1 TX_DRV_DATA_EN_OVRD_VAL_1 2 2 TX_DRV_DATA_EN_OVRD_EN_1 3 3 TX_DRV_PWRON_OVRD_VAL_1 4 4 TX_DRV_PWRON_OVRD_EN_1 5 5 TX_FRONTEND_PWRON_OVRD_VAL_1 6 6 TX_FRONTEND_PWRON_OVRD_EN_1 7 7 ixPB0_TX_LANE1_SCI_STAT_OVRD_REG0 2 0x1208488 5 0 4294967295 TXPWR_1 0 2 TXMARG_1 4 6 DEEMPH_1 7 7 COEFFICIENTID_1 8 9 COEFFICIENT_1 10 15 ixPB0_TX_LANE2_CTRL_REG0 2 0x1208500 4 0 4294967295 TX_CFG_DISPCLK_MODE_2 0 0 TX_CFG_INV_DATA_2 1 1 TX_CFG_SWING_BOOST_EN_2 2 2 TX_DBG_PRBS_EN_2 3 3 ixPB0_TX_LANE2_OVRD_REG0 2 0x1208504 8 0 4294967295 TX_DCLK_EN_OVRD_VAL_2 0 0 TX_DCLK_EN_OVRD_EN_2 1 1 TX_DRV_DATA_EN_OVRD_VAL_2 2 2 TX_DRV_DATA_EN_OVRD_EN_2 3 3 TX_DRV_PWRON_OVRD_VAL_2 4 4 TX_DRV_PWRON_OVRD_EN_2 5 5 TX_FRONTEND_PWRON_OVRD_VAL_2 6 6 TX_FRONTEND_PWRON_OVRD_EN_2 7 7 ixPB0_TX_LANE2_SCI_STAT_OVRD_REG0 2 0x1208508 5 0 4294967295 TXPWR_2 0 2 TXMARG_2 4 6 DEEMPH_2 7 7 COEFFICIENTID_2 8 9 COEFFICIENT_2 10 15 ixPB0_TX_LANE3_CTRL_REG0 2 0x1208600 4 0 4294967295 TX_CFG_DISPCLK_MODE_3 0 0 TX_CFG_INV_DATA_3 1 1 TX_CFG_SWING_BOOST_EN_3 2 2 TX_DBG_PRBS_EN_3 3 3 ixPB0_TX_LANE3_OVRD_REG0 2 0x1208604 8 0 4294967295 TX_DCLK_EN_OVRD_VAL_3 0 0 TX_DCLK_EN_OVRD_EN_3 1 1 TX_DRV_DATA_EN_OVRD_VAL_3 2 2 TX_DRV_DATA_EN_OVRD_EN_3 3 3 TX_DRV_PWRON_OVRD_VAL_3 4 4 TX_DRV_PWRON_OVRD_EN_3 5 5 TX_FRONTEND_PWRON_OVRD_VAL_3 6 6 TX_FRONTEND_PWRON_OVRD_EN_3 7 7 ixPB0_TX_LANE3_SCI_STAT_OVRD_REG0 2 0x1208608 5 0 4294967295 TXPWR_3 0 2 TXMARG_3 4 6 DEEMPH_3 7 7 COEFFICIENTID_3 8 9 COEFFICIENT_3 10 15 ixPB0_TX_LANE4_CTRL_REG0 2 0x1208840 4 0 4294967295 TX_CFG_DISPCLK_MODE_4 0 0 TX_CFG_INV_DATA_4 1 1 TX_CFG_SWING_BOOST_EN_4 2 2 TX_DBG_PRBS_EN_4 3 3 ixPB0_TX_LANE4_OVRD_REG0 2 0x1208844 8 0 4294967295 TX_DCLK_EN_OVRD_VAL_4 0 0 TX_DCLK_EN_OVRD_EN_4 1 1 TX_DRV_DATA_EN_OVRD_VAL_4 2 2 TX_DRV_DATA_EN_OVRD_EN_4 3 3 TX_DRV_PWRON_OVRD_VAL_4 4 4 TX_DRV_PWRON_OVRD_EN_4 5 5 TX_FRONTEND_PWRON_OVRD_VAL_4 6 6 TX_FRONTEND_PWRON_OVRD_EN_4 7 7 ixPB0_TX_LANE4_SCI_STAT_OVRD_REG0 2 0x1208848 5 0 4294967295 TXPWR_4 0 2 TXMARG_4 4 6 DEEMPH_4 7 7 COEFFICIENTID_4 8 9 COEFFICIENT_4 10 15 ixPB0_TX_LANE5_CTRL_REG0 2 0x1208880 4 0 4294967295 TX_CFG_DISPCLK_MODE_5 0 0 TX_CFG_INV_DATA_5 1 1 TX_CFG_SWING_BOOST_EN_5 2 2 TX_DBG_PRBS_EN_5 3 3 ixPB0_TX_LANE5_OVRD_REG0 2 0x1208884 8 0 4294967295 TX_DCLK_EN_OVRD_VAL_5 0 0 TX_DCLK_EN_OVRD_EN_5 1 1 TX_DRV_DATA_EN_OVRD_VAL_5 2 2 TX_DRV_DATA_EN_OVRD_EN_5 3 3 TX_DRV_PWRON_OVRD_VAL_5 4 4 TX_DRV_PWRON_OVRD_EN_5 5 5 TX_FRONTEND_PWRON_OVRD_VAL_5 6 6 TX_FRONTEND_PWRON_OVRD_EN_5 7 7 ixPB0_TX_LANE5_SCI_STAT_OVRD_REG0 2 0x1208888 5 0 4294967295 TXPWR_5 0 2 TXMARG_5 4 6 DEEMPH_5 7 7 COEFFICIENTID_5 8 9 COEFFICIENT_5 10 15 ixPB0_TX_LANE6_CTRL_REG0 2 0x1208900 4 0 4294967295 TX_CFG_DISPCLK_MODE_6 0 0 TX_CFG_INV_DATA_6 1 1 TX_CFG_SWING_BOOST_EN_6 2 2 TX_DBG_PRBS_EN_6 3 3 ixPB0_TX_LANE6_OVRD_REG0 2 0x1208904 8 0 4294967295 TX_DCLK_EN_OVRD_VAL_6 0 0 TX_DCLK_EN_OVRD_EN_6 1 1 TX_DRV_DATA_EN_OVRD_VAL_6 2 2 TX_DRV_DATA_EN_OVRD_EN_6 3 3 TX_DRV_PWRON_OVRD_VAL_6 4 4 TX_DRV_PWRON_OVRD_EN_6 5 5 TX_FRONTEND_PWRON_OVRD_VAL_6 6 6 TX_FRONTEND_PWRON_OVRD_EN_6 7 7 ixPB0_TX_LANE6_SCI_STAT_OVRD_REG0 2 0x1208908 5 0 4294967295 TXPWR_6 0 2 TXMARG_6 4 6 DEEMPH_6 7 7 COEFFICIENTID_6 8 9 COEFFICIENT_6 10 15 ixPB0_TX_LANE7_CTRL_REG0 2 0x1208a00 4 0 4294967295 TX_CFG_DISPCLK_MODE_7 0 0 TX_CFG_INV_DATA_7 1 1 TX_CFG_SWING_BOOST_EN_7 2 2 TX_DBG_PRBS_EN_7 3 3 ixPB0_TX_LANE7_OVRD_REG0 2 0x1208a04 8 0 4294967295 TX_DCLK_EN_OVRD_VAL_7 0 0 TX_DCLK_EN_OVRD_EN_7 1 1 TX_DRV_DATA_EN_OVRD_VAL_7 2 2 TX_DRV_DATA_EN_OVRD_EN_7 3 3 TX_DRV_PWRON_OVRD_VAL_7 4 4 TX_DRV_PWRON_OVRD_EN_7 5 5 TX_FRONTEND_PWRON_OVRD_VAL_7 6 6 TX_FRONTEND_PWRON_OVRD_EN_7 7 7 ixPB0_TX_LANE7_SCI_STAT_OVRD_REG0 2 0x1208a08 5 0 4294967295 TXPWR_7 0 2 TXMARG_7 4 6 DEEMPH_7 7 7 COEFFICIENTID_7 8 9 COEFFICIENT_7 10 15 ixPB0_TX_LANE8_CTRL_REG0 2 0x1209440 4 0 4294967295 TX_CFG_DISPCLK_MODE_8 0 0 TX_CFG_INV_DATA_8 1 1 TX_CFG_SWING_BOOST_EN_8 2 2 TX_DBG_PRBS_EN_8 3 3 ixPB0_TX_LANE8_OVRD_REG0 2 0x1209444 8 0 4294967295 TX_DCLK_EN_OVRD_VAL_8 0 0 TX_DCLK_EN_OVRD_EN_8 1 1 TX_DRV_DATA_EN_OVRD_VAL_8 2 2 TX_DRV_DATA_EN_OVRD_EN_8 3 3 TX_DRV_PWRON_OVRD_VAL_8 4 4 TX_DRV_PWRON_OVRD_EN_8 5 5 TX_FRONTEND_PWRON_OVRD_VAL_8 6 6 TX_FRONTEND_PWRON_OVRD_EN_8 7 7 ixPB0_TX_LANE8_SCI_STAT_OVRD_REG0 2 0x1209448 5 0 4294967295 TXPWR_8 0 2 TXMARG_8 4 6 DEEMPH_8 7 7 COEFFICIENTID_8 8 9 COEFFICIENT_8 10 15 ixPB0_TX_LANE9_CTRL_REG0 2 0x1209480 4 0 4294967295 TX_CFG_DISPCLK_MODE_9 0 0 TX_CFG_INV_DATA_9 1 1 TX_CFG_SWING_BOOST_EN_9 2 2 TX_DBG_PRBS_EN_9 3 3 ixPB0_TX_LANE9_OVRD_REG0 2 0x1209484 8 0 4294967295 TX_DCLK_EN_OVRD_VAL_9 0 0 TX_DCLK_EN_OVRD_EN_9 1 1 TX_DRV_DATA_EN_OVRD_VAL_9 2 2 TX_DRV_DATA_EN_OVRD_EN_9 3 3 TX_DRV_PWRON_OVRD_VAL_9 4 4 TX_DRV_PWRON_OVRD_EN_9 5 5 TX_FRONTEND_PWRON_OVRD_VAL_9 6 6 TX_FRONTEND_PWRON_OVRD_EN_9 7 7 ixPB0_TX_LANE9_SCI_STAT_OVRD_REG0 2 0x1209488 5 0 4294967295 TXPWR_9 0 2 TXMARG_9 4 6 DEEMPH_9 7 7 COEFFICIENTID_9 8 9 COEFFICIENT_9 10 15 ixPB0_TX_LANE10_CTRL_REG0 2 0x1209500 4 0 4294967295 TX_CFG_DISPCLK_MODE_10 0 0 TX_CFG_INV_DATA_10 1 1 TX_CFG_SWING_BOOST_EN_10 2 2 TX_DBG_PRBS_EN_10 3 3 ixPB0_TX_LANE10_OVRD_REG0 2 0x1209504 8 0 4294967295 TX_DCLK_EN_OVRD_VAL_10 0 0 TX_DCLK_EN_OVRD_EN_10 1 1 TX_DRV_DATA_EN_OVRD_VAL_10 2 2 TX_DRV_DATA_EN_OVRD_EN_10 3 3 TX_DRV_PWRON_OVRD_VAL_10 4 4 TX_DRV_PWRON_OVRD_EN_10 5 5 TX_FRONTEND_PWRON_OVRD_VAL_10 6 6 TX_FRONTEND_PWRON_OVRD_EN_10 7 7 ixPB0_TX_LANE10_SCI_STAT_OVRD_REG0 2 0x1209508 5 0 4294967295 TXPWR_10 0 2 TXMARG_10 4 6 DEEMPH_10 7 7 COEFFICIENTID_10 8 9 COEFFICIENT_10 10 15 ixPB0_TX_LANE11_CTRL_REG0 2 0x1209600 4 0 4294967295 TX_CFG_DISPCLK_MODE_11 0 0 TX_CFG_INV_DATA_11 1 1 TX_CFG_SWING_BOOST_EN_11 2 2 TX_DBG_PRBS_EN_11 3 3 ixPB0_TX_LANE11_OVRD_REG0 2 0x1209604 8 0 4294967295 TX_DCLK_EN_OVRD_VAL_11 0 0 TX_DCLK_EN_OVRD_EN_11 1 1 TX_DRV_DATA_EN_OVRD_VAL_11 2 2 TX_DRV_DATA_EN_OVRD_EN_11 3 3 TX_DRV_PWRON_OVRD_VAL_11 4 4 TX_DRV_PWRON_OVRD_EN_11 5 5 TX_FRONTEND_PWRON_OVRD_VAL_11 6 6 TX_FRONTEND_PWRON_OVRD_EN_11 7 7 ixPB0_TX_LANE11_SCI_STAT_OVRD_REG0 2 0x1209608 5 0 4294967295 TXPWR_11 0 2 TXMARG_11 4 6 DEEMPH_11 7 7 COEFFICIENTID_11 8 9 COEFFICIENT_11 10 15 ixPB0_TX_LANE12_CTRL_REG0 2 0x1209840 4 0 4294967295 TX_CFG_DISPCLK_MODE_12 0 0 TX_CFG_INV_DATA_12 1 1 TX_CFG_SWING_BOOST_EN_12 2 2 TX_DBG_PRBS_EN_12 3 3 ixPB0_TX_LANE12_OVRD_REG0 2 0x1209844 8 0 4294967295 TX_DCLK_EN_OVRD_VAL_12 0 0 TX_DCLK_EN_OVRD_EN_12 1 1 TX_DRV_DATA_EN_OVRD_VAL_12 2 2 TX_DRV_DATA_EN_OVRD_EN_12 3 3 TX_DRV_PWRON_OVRD_VAL_12 4 4 TX_DRV_PWRON_OVRD_EN_12 5 5 TX_FRONTEND_PWRON_OVRD_VAL_12 6 6 TX_FRONTEND_PWRON_OVRD_EN_12 7 7 ixPB0_TX_LANE12_SCI_STAT_OVRD_REG0 2 0x1209848 5 0 4294967295 TXPWR_12 0 2 TXMARG_12 4 6 DEEMPH_12 7 7 COEFFICIENTID_12 8 9 COEFFICIENT_12 10 15 ixPB0_TX_LANE13_CTRL_REG0 2 0x1209880 4 0 4294967295 TX_CFG_DISPCLK_MODE_13 0 0 TX_CFG_INV_DATA_13 1 1 TX_CFG_SWING_BOOST_EN_13 2 2 TX_DBG_PRBS_EN_13 3 3 ixPB0_TX_LANE13_OVRD_REG0 2 0x1209884 8 0 4294967295 TX_DCLK_EN_OVRD_VAL_13 0 0 TX_DCLK_EN_OVRD_EN_13 1 1 TX_DRV_DATA_EN_OVRD_VAL_13 2 2 TX_DRV_DATA_EN_OVRD_EN_13 3 3 TX_DRV_PWRON_OVRD_VAL_13 4 4 TX_DRV_PWRON_OVRD_EN_13 5 5 TX_FRONTEND_PWRON_OVRD_VAL_13 6 6 TX_FRONTEND_PWRON_OVRD_EN_13 7 7 ixPB0_TX_LANE13_SCI_STAT_OVRD_REG0 2 0x1209888 5 0 4294967295 TXPWR_13 0 2 TXMARG_13 4 6 DEEMPH_13 7 7 COEFFICIENTID_13 8 9 COEFFICIENT_13 10 15 ixPB0_TX_LANE14_CTRL_REG0 2 0x1209900 4 0 4294967295 TX_CFG_DISPCLK_MODE_14 0 0 TX_CFG_INV_DATA_14 1 1 TX_CFG_SWING_BOOST_EN_14 2 2 TX_DBG_PRBS_EN_14 3 3 ixPB0_TX_LANE14_OVRD_REG0 2 0x1209904 8 0 4294967295 TX_DCLK_EN_OVRD_VAL_14 0 0 TX_DCLK_EN_OVRD_EN_14 1 1 TX_DRV_DATA_EN_OVRD_VAL_14 2 2 TX_DRV_DATA_EN_OVRD_EN_14 3 3 TX_DRV_PWRON_OVRD_VAL_14 4 4 TX_DRV_PWRON_OVRD_EN_14 5 5 TX_FRONTEND_PWRON_OVRD_VAL_14 6 6 TX_FRONTEND_PWRON_OVRD_EN_14 7 7 ixPB0_TX_LANE14_SCI_STAT_OVRD_REG0 2 0x1209908 5 0 4294967295 TXPWR_14 0 2 TXMARG_14 4 6 DEEMPH_14 7 7 COEFFICIENTID_14 8 9 COEFFICIENT_14 10 15 ixPB0_TX_LANE15_CTRL_REG0 2 0x1209a00 4 0 4294967295 TX_CFG_DISPCLK_MODE_15 0 0 TX_CFG_INV_DATA_15 1 1 TX_CFG_SWING_BOOST_EN_15 2 2 TX_DBG_PRBS_EN_15 3 3 ixPB0_TX_LANE15_OVRD_REG0 2 0x1209a04 8 0 4294967295 TX_DCLK_EN_OVRD_VAL_15 0 0 TX_DCLK_EN_OVRD_EN_15 1 1 TX_DRV_DATA_EN_OVRD_VAL_15 2 2 TX_DRV_DATA_EN_OVRD_EN_15 3 3 TX_DRV_PWRON_OVRD_VAL_15 4 4 TX_DRV_PWRON_OVRD_EN_15 5 5 TX_FRONTEND_PWRON_OVRD_VAL_15 6 6 TX_FRONTEND_PWRON_OVRD_EN_15 7 7 ixPB0_TX_LANE15_SCI_STAT_OVRD_REG0 2 0x1209a08 5 0 4294967295 TXPWR_15 0 2 TXMARG_15 4 6 DEEMPH_15 7 7 COEFFICIENTID_15 8 9 COEFFICIENT_15 10 15 ixPB1_GLB_CTRL_REG0 2 0x2200004 8 0 4294967295 BACKUP 0 15 CFG_IDLEDET_TH 16 17 DBG_RX2TXBYP_SEL 20 22 DBG_RXFEBYP_EN 23 23 DBG_RXPRBS_CLR 24 24 DBG_RXTOGGLE_EN 25 25 DBG_TX2RXLBACK_EN 26 26 TXCFG_CMGOOD_RANGE 30 31 ixPB1_GLB_CTRL_REG1 2 0x2200008 10 0 4294967295 RXDBG_CDR_FR_BYP_EN 0 0 RXDBG_CDR_FR_BYP_VAL 1 6 RXDBG_CDR_PH_BYP_EN 7 7 RXDBG_CDR_PH_BYP_VAL 8 13 RXDBG_D0TH_BYP_EN 14 14 RXDBG_D0TH_BYP_VAL 15 21 RXDBG_D1TH_BYP_EN 22 22 RXDBG_D1TH_BYP_VAL 23 29 TST_LOSPDTST_EN 30 30 PLL_CFG_DISPCLK_DIV 31 31 ixPB1_GLB_CTRL_REG2 2 0x220000c 8 0 4294967295 RXDBG_D2TH_BYP_EN 0 0 RXDBG_D2TH_BYP_VAL 1 7 RXDBG_D3TH_BYP_EN 8 8 RXDBG_D3TH_BYP_VAL 9 15 RXDBG_DXTH_BYP_EN 16 16 RXDBG_DXTH_BYP_VAL 17 23 RXDBG_ETH_BYP_EN 24 24 RXDBG_ETH_BYP_VAL 25 31 ixPB1_GLB_CTRL_REG3 2 0x2200010 14 0 4294967295 RXDBG_SEL 0 4 BG_CFG_LC_REG_VREF0_SEL 5 6 BG_CFG_LC_REG_VREF1_SEL 7 8 BG_CFG_RO_REG_VREF_SEL 9 10 BG_DBG_VREFBYP_EN 11 11 BG_DBG_IREFBYP_EN 12 12 BG_DBG_ANALOG_SEL 14 16 DBG_DLL_CLK_SEL 18 20 PLL_DISPCLK_CMOS_SEL 21 21 DBG_RXPI_OFFSET_BYP_EN 22 22 DBG_RXPI_OFFSET_BYP_VAL 23 26 DBG_RXSWAPDX_BYP_EN 27 27 DBG_RXSWAPDX_BYP_VAL 28 30 DBG_RXLEQ_DCATTN_BYP_OVR_DISABLE 31 31 ixPB1_GLB_CTRL_REG4 2 0x2200014 7 0 4294967295 DBG_RXAPU_INST 0 15 DBG_RXDFEMUX_BYP_VAL 16 17 DBG_RXDFEMUX_BYP_EN 18 18 DBG_RXAPU_EXEC 22 25 DBG_RXDLL_VREG_REF_SEL 26 26 PWRGOOD_OVRD 27 27 DBG_RXRDATA_GATING_DISABLE 28 28 ixPB1_GLB_CTRL_REG5 2 0x2200018 1 0 4294967295 DBG_RXAPU_MODE 0 7 ixPB1_GLB_SCI_STAT_OVRD_REG0 2 0x220001c 9 0 4294967295 IGNR_ALL_CBI_UPDT_L0T3 0 0 IGNR_ALL_CBI_UPDT_L4T7 1 1 IGNR_ALL_CBI_UPDT_L8T11 2 2 IGNR_ALL_CBI_UPDT_L12T15 3 3 IGNR_IMPCAL_ACTIVE_CBI_UPDT 4 4 TXNIMP 8 11 TXPIMP 12 15 RXIMP 16 19 IMPCAL_ACTIVE 20 20 ixPB1_GLB_SCI_STAT_OVRD_REG1 2 0x2200020 15 0 4294967295 IGNR_LINKSPEED_CBI_UPDT_L0T3 0 0 IGNR_FREQDIV_CBI_UPDT_L0T3 1 1 IGNR_DLL_LOCK_CBI_UPDT_L0T3 2 2 DLL_LOCK_0 12 12 DLL_LOCK_1 13 13 DLL_LOCK_2 14 14 DLL_LOCK_3 15 15 LINKSPEED_0 16 17 FREQDIV_0 18 19 LINKSPEED_1 20 21 FREQDIV_1 22 23 LINKSPEED_2 24 25 FREQDIV_2 26 27 LINKSPEED_3 28 29 FREQDIV_3 30 31 ixPB1_GLB_SCI_STAT_OVRD_REG2 2 0x2200024 15 0 4294967295 IGNR_LINKSPEED_CBI_UPDT_L4T7 0 0 IGNR_FREQDIV_CBI_UPDT_L4T7 1 1 IGNR_DLL_LOCK_CBI_UPDT_L4T7 2 2 DLL_LOCK_4 12 12 DLL_LOCK_5 13 13 DLL_LOCK_6 14 14 DLL_LOCK_7 15 15 LINKSPEED_4 16 17 FREQDIV_4 18 19 LINKSPEED_5 20 21 FREQDIV_5 22 23 LINKSPEED_6 24 25 FREQDIV_6 26 27 LINKSPEED_7 28 29 FREQDIV_7 30 31 ixPB1_GLB_SCI_STAT_OVRD_REG3 2 0x2200028 15 0 4294967295 IGNR_LINKSPEED_CBI_UPDT_L8T11 0 0 IGNR_FREQDIV_CBI_UPDT_L8T11 1 1 IGNR_DLL_LOCK_CBI_UPDT_L8T11 2 2 DLL_LOCK_8 12 12 DLL_LOCK_9 13 13 DLL_LOCK_10 14 14 DLL_LOCK_11 15 15 LINKSPEED_8 16 17 FREQDIV_8 18 19 LINKSPEED_9 20 21 FREQDIV_9 22 23 LINKSPEED_10 24 25 FREQDIV_10 26 27 LINKSPEED_11 28 29 FREQDIV_11 30 31 ixPB1_GLB_SCI_STAT_OVRD_REG4 2 0x220002c 15 0 4294967295 IGNR_LINKSPEED_CBI_UPDT_L12T15 0 0 IGNR_FREQDIV_CBI_UPDT_L12T15 1 1 IGNR_DLL_LOCK_CBI_UPDT_L12T15 2 2 DLL_LOCK_12 12 12 DLL_LOCK_13 13 13 DLL_LOCK_14 14 14 DLL_LOCK_15 15 15 LINKSPEED_12 16 17 FREQDIV_12 18 19 LINKSPEED_13 20 21 FREQDIV_13 22 23 LINKSPEED_14 24 25 FREQDIV_14 26 27 LINKSPEED_15 28 29 FREQDIV_15 30 31 ixPB1_GLB_OVRD_REG0 2 0x2200030 2 0 4294967295 TXPDTERM_VAL_OVRD_VAL 0 15 TXPUTERM_VAL_OVRD_VAL 16 31 ixPB1_GLB_OVRD_REG1 2 0x2200034 6 0 4294967295 TXPDTERM_VAL_OVRD_EN 0 0 TXPUTERM_VAL_OVRD_EN 1 1 TST_LOSPDTST_RST_OVRD_EN 2 2 TST_LOSPDTST_RST_OVRD_VAL 3 3 RXTERM_VAL_OVRD_EN 15 15 RXTERM_VAL_OVRD_VAL 16 31 ixPB1_GLB_OVRD_REG2 2 0x2200038 6 0 4294967295 BG_PWRON_OVRD_EN 0 0 BG_PWRON_OVRD_VAL 1 1 PLL_DBG_LC_EXT_RESET_OVRD_EN 2 2 PLL_DBG_LC_EXT_RESET_OVRD_VAL 3 3 PLL_DBG_RO_EXT_RESET_OVRD_EN 4 4 PLL_DBG_RO_EXT_RESET_OVRD_VAL 5 5 ixPB1_HW_DEBUG 2 0x2202004 32 0 4294967295 HW_00_DEBUG 0 0 HW_01_DEBUG 1 1 HW_02_DEBUG 2 2 HW_03_DEBUG 3 3 HW_04_DEBUG 4 4 HW_05_DEBUG 5 5 HW_06_DEBUG 6 6 HW_07_DEBUG 7 7 HW_08_DEBUG 8 8 HW_09_DEBUG 9 9 HW_10_DEBUG 10 10 HW_11_DEBUG 11 11 HW_12_DEBUG 12 12 HW_13_DEBUG 13 13 HW_14_DEBUG 14 14 HW_15_DEBUG 15 15 HW_16_DEBUG 16 16 HW_17_DEBUG 17 17 HW_18_DEBUG 18 18 HW_19_DEBUG 19 19 HW_20_DEBUG 20 20 HW_21_DEBUG 21 21 HW_22_DEBUG 22 22 HW_23_DEBUG 23 23 HW_24_DEBUG 24 24 HW_25_DEBUG 25 25 HW_26_DEBUG 26 26 HW_27_DEBUG 27 27 HW_28_DEBUG 28 28 HW_29_DEBUG 29 29 HW_30_DEBUG 30 30 HW_31_DEBUG 31 31 ixPB1_STRAP_GLB_REG0 2 0x2202020 13 0 4294967295 STRAP_QUICK_SIM_START 1 1 STRAP_DFT_RXBSCAN_EN_VAL 2 2 STRAP_DFT_CALIB_BYPASS 3 3 STRAP_FORCE_LC_PLL_ON 4 4 STRAP_CFG_IDLEDET_TH 5 6 STRAP_RX_CFG_LEQ_DCATTN_BYP_VAL 7 11 STRAP_RX_CFG_OVR_PWRSF 12 12 STRAP_RX_TRK_MODE_0_ 13 13 STRAP_PWRGOOD_OVRD 14 14 STRAP_DBG_RXDLL_VREG_REF_SEL 15 15 STRAP_PLL_CFG_LC_VCO_TUNE 16 19 STRAP_DBG_RXRDATA_GATING_DISABLE 20 20 STRAP_DBG_RXPI_OFFSET_BYP_VAL 21 24 ixPB1_STRAP_TX_REG0 2 0x2202024 10 0 4294967295 STRAP_TX_CFG_DRV0_EN 1 4 STRAP_TX_CFG_DRV0_TAP_SEL 5 8 STRAP_TX_CFG_DRV1_EN 9 13 STRAP_TX_CFG_DRV1_TAP_SEL 14 18 STRAP_TX_CFG_DRV2_EN 19 22 STRAP_TX_CFG_DRV2_TAP_SEL 23 26 STRAP_TX_CFG_DRVX_EN 27 27 STRAP_TX_CFG_DRVX_TAP_SEL 28 28 STRAP_RX_TRK_MODE_1_ 29 29 STRAP_TX_CFG_SWING_BOOST_EN 30 30 ixPB1_STRAP_RX_REG0 2 0x2202028 12 0 4294967295 STRAP_RX_CFG_TH_LOOP_GAIN 1 4 STRAP_RX_CFG_DLL_FLOCK_DISABLE 5 5 STRAP_DBG_RXPI_OFFSET_BYP_EN 6 6 STRAP_RX_CFG_LEQ_DCATTN_BYP_DIS 7 7 STRAP_BG_CFG_LC_REG_VREF0_SEL 8 9 STRAP_BG_CFG_LC_REG_VREF1_SEL 10 11 STRAP_RX_CFG_CDR_TIME 12 15 STRAP_RX_CFG_FOM_TIME 16 19 STRAP_RX_CFG_LEQ_TIME 20 23 STRAP_RX_CFG_OC_TIME 24 27 STRAP_TX_CFG_RPTR_RST_VAL 28 30 STRAP_RX_CFG_TERM_MODE 31 31 ixPB1_STRAP_RX_REG1 2 0x220202c 10 0 4294967295 STRAP_RX_CFG_CDR_PI_STPSZ 1 1 STRAP_TX_DEEMPH_PRSHT_STNG 2 4 STRAP_BG_CFG_RO_REG_VREF_SEL 5 6 STRAP_RX_CFG_LEQ_POLE_BYP_DIS 7 7 STRAP_RX_CFG_LEQ_POLE_BYP_VAL 8 10 STRAP_RX_CFG_CDR_PH_GAIN 11 14 STRAP_RX_CFG_ADAPT_MODE 15 24 STRAP_RX_CFG_DFE_TIME 25 28 STRAP_RX_CFG_LEQ_LOOP_GAIN 29 30 STRAP_RX_CFG_LEQ_SHUNT_DIS 31 31 ixPB1_STRAP_PLL_REG0 2 0x2202030 6 0 4294967295 STRAP_PLL_CFG_LC_BW_CNTRL 1 3 STRAP_PLL_CFG_LC_LF_CNTRL 4 12 STRAP_TX_RXDET_X1_SSF 13 13 STRAP_PLL_CFG_RO_VTOI_BIAS_CNTRL_DIS 15 15 STRAP_PLL_CFG_RO_BW_CNTRL 16 23 STRAP_PLL_STRAP_SEL 24 24 ixPB1_STRAP_PIN_REG0 2 0x2202034 2 0 4294967295 STRAP_TX_DEEMPH_EN 1 1 STRAP_TX_FULL_SWING 2 2 ixPB1_STRAP_GLB_REG1 2 0x2202038 7 0 4294967295 STRAP_RX_ADAPT_RST_MODE 1 2 STRAP_RX_L0_ENTRY_MODE 3 4 STRAP_RX_EI_FILTER 5 6 STRAP_RX_ADAPT_RST_SUB_ENTRY 7 7 STRAP_RX_PS0_RDY_GEN_MODE 8 9 STRAP_RX_DLL_RESET_IN_SPDCHG 10 10 STRAP_RX_ADAPT_TIME_OUT 11 12 ixPB1_STRAP_GLB_REG2 2 0x220203c 8 0 4294967295 STRAP_BPHYC_PLL_RAMP_UP_TIME 2 4 STRAP_IMPCAL_SETTLE_TIME 5 6 STRAP_BG_SETTLE_TIME 7 8 STRAP_TX_CMDET_TIME 9 10 STRAP_TX_STARTUP_TIME 11 12 STRAP_B_PCB_DIS0 28 28 STRAP_B_PCB_DIS1 29 29 STRAP_B_PCB_DRV_STR 30 31 ixPB1_DFT_JIT_INJ_REG0 2 0x2203000 8 0 4294967295 DFT_NUM_STEPS 0 5 DFT_DISABLE_ERR 7 7 DFT_CLK_PER_STEP 8 11 DFT_MODE_CDR_EN 20 20 DFT_EN_RECOVERY 21 21 DFT_INCR_SWP_EN 22 22 DFT_DECR_SWP_EN 23 23 DFT_RECOVERY_TIME 24 31 ixPB1_DFT_JIT_INJ_REG1 2 0x2203004 5 0 4294967295 DFT_BYPASS_VALUE 0 7 DFT_BYPASS_EN 8 8 DFT_BLOCK_EN 16 16 DFT_NUM_OF_TESTS 17 19 DFT_CHECK_TIME 20 23 ixPB1_DFT_JIT_INJ_REG2 2 0x2203008 1 0 4294967295 DFT_LANE_EN 0 15 ixPB1_DFT_DEBUG_CTRL_REG0 2 0x220300c 2 0 4294967295 DFT_PHY_DEBUG_EN 0 0 DFT_PHY_DEBUG_MODE 1 5 ixPB1_DFT_JIT_INJ_STAT_REG0 2 0x2203010 3 0 4294967295 DFT_STAT_DECR 0 7 DFT_STAT_INCR 8 15 DFT_STAT_FINISHED 16 16 ixPB1_PLL_RO_GLB_CTRL_REG0 2 0x2204000 19 0 4294967295 PLL_TST_LOSPDTST_SRC 0 0 PLL_RO_HSCLK_LEFT_EN_LUT_ENTRY_LS0 1 1 PLL_RO_HSCLK_LEFT_EN_LUT_ENTRY_LS1 2 2 PLL_RO_HSCLK_LEFT_EN_LUT_ENTRY_LS2 3 3 PLL_RO_HSCLK_RIGHT_EN_LUT_ENTRY_LS0 4 4 PLL_RO_HSCLK_RIGHT_EN_LUT_ENTRY_LS1 5 5 PLL_RO_HSCLK_RIGHT_EN_LUT_ENTRY_LS2 6 6 PLL_RO_PWRON_LUT_ENTRY_LS2 7 7 PLL_LC_PWRON_LUT_ENTRY_LS2 8 8 PLL_LC_HSCLK_LEFT_EN_LUT_ENTRY_LS0 9 9 PLL_LC_HSCLK_LEFT_EN_LUT_ENTRY_LS1 10 10 PLL_LC_HSCLK_LEFT_EN_LUT_ENTRY_LS2 11 11 PLL_LC_HSCLK_RIGHT_EN_LUT_ENTRY_LS0 12 12 PLL_LC_HSCLK_RIGHT_EN_LUT_ENTRY_LS1 13 13 PLL_LC_HSCLK_RIGHT_EN_LUT_ENTRY_LS2 14 14 PLL_RO_HSCLK_LEFT_EN_GATING_EN 15 15 PLL_RO_HSCLK_RIGHT_EN_GATING_EN 16 16 PLL_LC_HSCLK_LEFT_EN_GATING_EN 17 17 PLL_LC_HSCLK_RIGHT_EN_GATING_EN 18 18 ixPB1_PLL_RO_GLB_OVRD_REG0 2 0x2204010 0 0 4294967295 ixPB1_PLL_RO0_CTRL_REG0 2 0x2204440 5 0 4294967295 PLL_DBG_RO_ANALOG_SEL_0 0 1 PLL_DBG_RO_EXT_RESET_EN_0 2 2 PLL_DBG_RO_VCTL_ADC_EN_0 3 3 PLL_DBG_RO_LF_CNTRL_0 4 10 PLL_TST_RO_USAMPLE_EN_0 11 11 ixPB1_PLL_RO0_OVRD_REG0 2 0x2204450 10 0 4294967295 PLL_CFG_RO_BW_CNTRL_OVRD_VAL_0 0 7 PLL_CFG_RO_BW_CNTRL_OVRD_EN_0 8 8 PLL_CFG_RO_CORECLK_DIV_OVRD_VAL_0 9 11 PLL_CFG_RO_CORECLK_DIV_OVRD_EN_0 12 12 PLL_CFG_RO_CORECLK_EN_OVRD_VAL_0 13 13 PLL_CFG_RO_CORECLK_EN_OVRD_EN_0 14 14 PLL_CFG_RO_FBDIV_OVRD_VAL_0 15 27 PLL_CFG_RO_FBDIV_OVRD_EN_0 28 28 PLL_CFG_RO_VTOI_BIAS_CNTRL_OVRD_VAL_0 30 30 PLL_CFG_RO_VTOI_BIAS_CNTRL_OVRD_EN_0 31 31 ixPB1_PLL_RO0_OVRD_REG1 2 0x2204454 12 0 4294967295 PLL_CFG_RO_REFDIV_OVRD_VAL_0 0 4 PLL_CFG_RO_REFDIV_OVRD_EN_0 5 5 PLL_CFG_RO_VCO_MODE_OVRD_VAL_0 6 7 PLL_CFG_RO_VCO_MODE_OVRD_EN_0 8 8 PLL_RO_HSCLK_LEFT_EN_OVRD_VAL_0 9 9 PLL_RO_HSCLK_LEFT_EN_OVRD_EN_0 10 10 PLL_RO_HSCLK_RIGHT_EN_OVRD_VAL_0 11 11 PLL_RO_HSCLK_RIGHT_EN_OVRD_EN_0 12 12 PLL_RO_PWRON_OVRD_VAL_0 13 13 PLL_RO_PWRON_OVRD_EN_0 14 14 PLL_CFG_RO_REFCLK_SRC_OVRD_VAL_0 19 21 PLL_CFG_RO_REFCLK_SRC_OVRD_EN_0 22 22 ixPB1_PLL_RO0_SCI_STAT_OVRD_REG0 2 0x2204460 4 0 4294967295 PLL_RO0_IGNR_PLLPWR_CBI_UPDT 0 0 PLL_RO0_IGNR_PLLFREQ_CBI_UPDT 1 1 PLL_RO0_PLLPWR 4 6 PLL_RO0_PLLFREQ 8 9 ixPB1_PLL_RO1_SCI_STAT_OVRD_REG0 2 0x2204464 4 0 4294967295 PLL_RO1_IGNR_PLLPWR_CBI_UPDT 0 0 PLL_RO1_IGNR_PLLFREQ_CBI_UPDT 1 1 PLL_RO1_PLLPWR 4 6 PLL_RO1_PLLFREQ 8 9 ixPB1_PLL_RO2_SCI_STAT_OVRD_REG0 2 0x2204468 4 0 4294967295 PLL_RO2_IGNR_PLLPWR_CBI_UPDT 0 0 PLL_RO2_IGNR_PLLFREQ_CBI_UPDT 1 1 PLL_RO2_PLLPWR 4 6 PLL_RO2_PLLFREQ 8 9 ixPB1_PLL_RO3_SCI_STAT_OVRD_REG0 2 0x220446c 4 0 4294967295 PLL_RO3_IGNR_PLLPWR_CBI_UPDT 0 0 PLL_RO3_IGNR_PLLFREQ_CBI_UPDT 1 1 PLL_RO3_PLLPWR 4 6 PLL_RO3_PLLFREQ 8 9 ixPB1_PLL_LC0_CTRL_REG0 2 0x2204480 4 0 4294967295 PLL_DBG_LC_ANALOG_SEL_0 0 1 PLL_DBG_LC_EXT_RESET_EN_0 2 2 PLL_DBG_LC_VCTL_ADC_EN_0 3 3 PLL_TST_LC_USAMPLE_EN_0 4 4 ixPB1_PLL_LC0_OVRD_REG0 2 0x2204490 12 0 4294967295 PLL_CFG_LC_BW_CNTRL_OVRD_VAL_0 0 2 PLL_CFG_LC_BW_CNTRL_OVRD_EN_0 3 3 PLL_CFG_LC_CORECLK_DIV_OVRD_VAL_0 4 6 PLL_CFG_LC_CORECLK_DIV_OVRD_EN_0 7 7 PLL_CFG_LC_CORECLK_EN_OVRD_VAL_0 8 8 PLL_CFG_LC_CORECLK_EN_OVRD_EN_0 9 9 PLL_CFG_LC_FBDIV_OVRD_VAL_0 10 17 PLL_CFG_LC_FBDIV_OVRD_EN_0 18 18 PLL_CFG_LC_LF_CNTRL_OVRD_VAL_0 19 27 PLL_CFG_LC_LF_CNTRL_OVRD_EN_0 28 28 PLL_CFG_LC_REFDIV_OVRD_VAL_0 29 30 PLL_CFG_LC_REFDIV_OVRD_EN_0 31 31 ixPB1_PLL_LC0_OVRD_REG1 2 0x2204494 10 0 4294967295 PLL_CFG_LC_REFCLK_SRC_OVRD_VAL_0 0 2 PLL_CFG_LC_REFCLK_SRC_OVRD_EN_0 3 3 PLL_LC_HSCLK_LEFT_EN_OVRD_VAL_0 4 4 PLL_LC_HSCLK_LEFT_EN_OVRD_EN_0 5 5 PLL_LC_HSCLK_RIGHT_EN_OVRD_VAL_0 6 6 PLL_LC_HSCLK_RIGHT_EN_OVRD_EN_0 7 7 PLL_LC_PWRON_OVRD_VAL_0 8 8 PLL_LC_PWRON_OVRD_EN_0 9 9 PLL_CFG_LC_VCO_TUNE_OVRD_VAL_0 14 17 PLL_CFG_LC_VCO_TUNE_OVRD_EN_0 18 18 ixPB1_PLL_LC0_SCI_STAT_OVRD_REG0 2 0x2204500 2 0 4294967295 PLL_LC0_IGNR_PLLPWR_CBI_UPDT 0 0 PLL_LC0_PLLPWR 4 6 ixPB1_PLL_LC1_SCI_STAT_OVRD_REG0 2 0x2204504 2 0 4294967295 PLL_LC1_IGNR_PLLPWR_CBI_UPDT 0 0 PLL_LC1_PLLPWR 4 6 ixPB1_PLL_LC2_SCI_STAT_OVRD_REG0 2 0x2204508 2 0 4294967295 PLL_LC2_IGNR_PLLPWR_CBI_UPDT 0 0 PLL_LC2_PLLPWR 4 6 ixPB1_PLL_LC3_SCI_STAT_OVRD_REG0 2 0x220450c 2 0 4294967295 PLL_LC3_IGNR_PLLPWR_CBI_UPDT 0 0 PLL_LC3_PLLPWR 4 6 ixPB1_RX_GLB_CTRL_REG0 2 0x2206000 3 0 4294967295 RX_CFG_ADAPT_MODE_GEN1 0 9 RX_CFG_ADAPT_MODE_GEN2 10 19 RX_CFG_ADAPT_MODE_GEN3 20 29 ixPB1_RX_GLB_CTRL_REG1 2 0x2206004 13 0 4294967295 RX_CFG_CDR_FR_GAIN_GEN1 0 3 RX_CFG_CDR_FR_GAIN_GEN2 4 7 RX_CFG_CDR_FR_GAIN_GEN3 8 11 RX_CFG_CDR_PH_GAIN_GEN1 12 15 RX_CFG_CDR_PH_GAIN_GEN2 16 19 RX_CFG_CDR_PH_GAIN_GEN3 20 23 RX_CFG_CDR_PI_STPSZ_GEN1 24 24 RX_CFG_CDR_PI_STPSZ_GEN2 25 25 RX_CFG_CDR_PI_STPSZ_GEN3 26 26 RX_CFG_LEQ_DCATTN_BYP_EN_GEN1 27 27 RX_CFG_LEQ_DCATTN_BYP_EN_GEN2 28 28 RX_CFG_LEQ_DCATTN_BYP_EN_GEN3 29 29 RX_ADAPT_HLD_ASRT_TO_DCLK_EN 30 31 ixPB1_RX_GLB_CTRL_REG2 2 0x2206008 7 0 4294967295 RX_CFG_CDR_TIME_GEN1 12 15 RX_CFG_CDR_TIME_GEN2 16 19 RX_CFG_CDR_TIME_GEN3 20 23 RX_CFG_LEQ_LOOP_GAIN_GEN1 24 25 RX_CFG_LEQ_LOOP_GAIN_GEN2 26 27 RX_CFG_LEQ_LOOP_GAIN_GEN3 28 29 RX_DCLK_EN_ASRT_TO_ADAPT_HLD 30 31 ixPB1_RX_GLB_CTRL_REG3 2 0x220600c 13 0 4294967295 RX_CFG_CDR_FR_EN_GEN1 0 0 RX_CFG_CDR_FR_EN_GEN2 1 1 RX_CFG_CDR_FR_EN_GEN3 2 2 RX_ADAPT_RST_MODE_GEN1 3 4 RX_ADAPT_RST_MODE_GEN2 5 6 RX_ADAPT_RST_MODE_GEN3 7 8 RX_ADAPT_RST_SUB_MODE 9 11 RX_L0_ENTRY_MODE_GEN1 12 13 RX_L0_ENTRY_MODE_GEN2 14 15 RX_L0_ENTRY_MODE_GEN3 16 17 RX_CFG_DFE_TIME_GEN1 20 23 RX_CFG_DFE_TIME_GEN2 24 27 RX_CFG_DFE_TIME_GEN3 28 31 ixPB1_RX_GLB_CTRL_REG4 2 0x2206010 9 0 4294967295 RX_CFG_FOM_BER_GEN1 0 2 RX_CFG_FOM_BER_GEN2 3 5 RX_CFG_FOM_BER_GEN3 6 8 RX_CFG_LEQ_POLE_BYP_VAL_GEN1 9 11 RX_CFG_LEQ_POLE_BYP_VAL_GEN2 12 14 RX_CFG_LEQ_POLE_BYP_VAL_GEN3 15 17 RX_CFG_FOM_TIME_GEN1 20 23 RX_CFG_FOM_TIME_GEN2 24 27 RX_CFG_FOM_TIME_GEN3 28 31 ixPB1_RX_GLB_CTRL_REG5 2 0x2206014 13 0 4294967295 RX_CFG_LEQ_DCATTN_BYP_VAL_GEN1 0 4 RX_CFG_LEQ_DCATTN_BYP_VAL_GEN2 5 9 RX_CFG_LEQ_DCATTN_BYP_VAL_GEN3 10 14 RX_CFG_LEQ_POLE_BYP_EN_GEN1 15 15 RX_CFG_LEQ_POLE_BYP_EN_GEN2 16 16 RX_CFG_LEQ_POLE_BYP_EN_GEN3 17 17 RX_CFG_LEQ_SHUNT_EN_GEN1 18 18 RX_CFG_LEQ_SHUNT_EN_GEN2 19 19 RX_CFG_LEQ_SHUNT_EN_GEN3 20 20 RX_CFG_TERM_MODE_GEN1 27 27 RX_CFG_TERM_MODE_GEN2 28 28 RX_CFG_TERM_MODE_GEN3 29 29 RX_ADAPT_AUX_PWRON_MODE 31 31 ixPB1_RX_GLB_CTRL_REG6 2 0x2206018 11 0 4294967295 RX_CFG_LEQ_TIME_GEN1 0 3 RX_CFG_LEQ_TIME_GEN2 4 7 RX_CFG_LEQ_TIME_GEN3 8 11 RX_CFG_OC_TIME_GEN1 12 15 RX_CFG_OC_TIME_GEN2 16 19 RX_CFG_OC_TIME_GEN3 20 23 RX_FRONTEND_PWRON_LUT_ENTRY_LS0_CDR_EN_0 24 24 RX_FRONTEND_PWRON_LUT_ENTRY_LS2 26 26 RX_AUX_PWRON_LUT_ENTRY_LS2 27 27 RX_ADAPT_HLD_L0S_EARLY_EXIT_DIS 28 28 RX_ADAPT_HLD_L1_DLL_OFF 29 29 ixPB1_RX_GLB_CTRL_REG7 2 0x220601c 14 0 4294967295 RX_CFG_TH_LOOP_GAIN_GEN1 0 3 RX_CFG_TH_LOOP_GAIN_GEN2 4 7 RX_CFG_TH_LOOP_GAIN_GEN3 8 11 RX_DCLK_EN_LUT_ENTRY_LS0_CDR_EN_0 12 12 RX_DCLK_EN_LUT_ENTRY_LS2 13 13 RX_DCLK_EN_AFTER_DLL_LOCK 14 14 RX_DLL_PWRON_LUT_ENTRY_PS3 16 16 RX_DLL_PWRON_LUT_ENTRY_PS2 17 17 RX_CFG_DLL_CPI_SEL_GEN1 18 20 RX_CFG_DLL_CPI_SEL_GEN2 21 23 RX_CFG_DLL_CPI_SEL_GEN3 24 26 RX_CFG_DLL_FLOCK_DISABLE_GEN1 27 27 RX_CFG_DLL_FLOCK_DISABLE_GEN2 28 28 RX_CFG_DLL_FLOCK_DISABLE_GEN3 29 29 ixPB1_RX_GLB_CTRL_REG8 2 0x2206020 4 0 4294967295 RX_DLL_LOCK_TIME 0 1 RX_DLL_SPEEDCHANGE_RESET_TIME 2 3 RX_DLL_PWRON_IN_RAMPDOWN 4 4 RX_FSM_L0S_IF_RX_RDY 5 5 ixPB1_RX_GLB_SCI_STAT_OVRD_REG0 2 0x2206028 24 0 4294967295 IGNR_RXPWR_CBI_UPDT_L0T3 0 0 IGNR_RXPWR_CBI_UPDT_L4T7 1 1 IGNR_RXPWR_CBI_UPDT_L8T11 2 2 IGNR_RXPWR_CBI_UPDT_L12T15 3 3 IGNR_ELECIDLEDETEN_CBI_UPDT_L0T3 4 4 IGNR_ELECIDLEDETEN_CBI_UPDT_L4T7 5 5 IGNR_ELECIDLEDETEN_CBI_UPDT_L8T11 6 6 IGNR_ELECIDLEDETEN_CBI_UPDT_L12T15 7 7 IGNR_REQUESTTRK_CBI_UPDT_L0T3 8 8 IGNR_REQUESTTRK_CBI_UPDT_L4T7 9 9 IGNR_REQUESTTRK_CBI_UPDT_L8T11 10 10 IGNR_REQUESTTRK_CBI_UPDT_L12T15 11 11 IGNR_ENABLEFOM_CBI_UPDT_L0T3 12 12 IGNR_ENABLEFOM_CBI_UPDT_L4T7 13 13 IGNR_ENABLEFOM_CBI_UPDT_L8T11 14 14 IGNR_ENABLEFOM_CBI_UPDT_L12T15 15 15 IGNR_REQUESTFOM_CBI_UPDT_L0T3 16 16 IGNR_REQUESTFOM_CBI_UPDT_L4T7 17 17 IGNR_REQUESTFOM_CBI_UPDT_L8T11 18 18 IGNR_REQUESTFOM_CBI_UPDT_L12T15 19 19 IGNR_RESPONSEMODE_CBI_UPDT_L0T3 20 20 IGNR_RESPONSEMODE_CBI_UPDT_L4T7 21 21 IGNR_RESPONSEMODE_CBI_UPDT_L8T11 22 22 IGNR_RESPONSEMODE_CBI_UPDT_L12T15 23 23 ixPB1_RX_GLB_OVRD_REG0 2 0x2206030 24 0 4294967295 RX_ADAPT_HLD_OVRD_VAL 0 0 RX_ADAPT_HLD_OVRD_EN 1 1 RX_ADAPT_RST_OVRD_VAL 2 2 RX_ADAPT_RST_OVRD_EN 3 3 RX_CFG_DCLK_DIV_OVRD_VAL 6 7 RX_CFG_DCLK_DIV_OVRD_EN 8 8 RX_CFG_DLL_FREQ_MODE_OVRD_VAL 9 9 RX_CFG_DLL_FREQ_MODE_OVRD_EN 10 10 RX_CFG_PLLCLK_SEL_OVRD_VAL 11 11 RX_CFG_PLLCLK_SEL_OVRD_EN 12 12 RX_CFG_RCLK_DIV_OVRD_VAL 13 13 RX_CFG_RCLK_DIV_OVRD_EN 14 14 RX_DCLK_EN_OVRD_VAL 15 15 RX_DCLK_EN_OVRD_EN 16 16 RX_DLL_PWRON_OVRD_VAL 17 17 RX_DLL_PWRON_OVRD_EN 18 18 RX_FRONTEND_PWRON_OVRD_VAL 19 19 RX_FRONTEND_PWRON_OVRD_EN 20 20 RX_IDLEDET_PWRON_OVRD_VAL 21 21 RX_IDLEDET_PWRON_OVRD_EN 22 22 RX_AUX_PWRON_OVRD_VAL 28 28 RX_AUX_PWRON_OVRD_EN 29 29 RX_ADAPT_FOM_OVRD_VAL 30 30 RX_ADAPT_FOM_OVRD_EN 31 31 ixPB1_RX_GLB_OVRD_REG1 2 0x2206034 2 0 4294967295 RX_ADAPT_TRK_OVRD_VAL 0 0 RX_ADAPT_TRK_OVRD_EN 1 1 ixPB1_RX_LANE0_CTRL_REG0 2 0x2206440 5 0 4294967295 RX_BACKUP_0 0 7 RX_DBG_ANALOG_SEL_0 10 11 RX_TST_BSCAN_EN_0 12 12 RX_CFG_OVR_PWRSF_0 13 13 RX_TERM_EN_0 14 14 ixPB1_RX_LANE0_SCI_STAT_OVRD_REG0 2 0x2206448 7 0 4294967295 RXPWR_0 0 2 ELECIDLEDETEN_0 3 3 REQUESTTRK_0 6 6 ENABLEFOM_0 7 7 REQUESTFOM_0 8 8 RESPONSEMODE_0 9 9 RXEYEFOM_0 10 17 ixPB1_RX_LANE1_CTRL_REG0 2 0x2206480 5 0 4294967295 RX_BACKUP_1 0 7 RX_DBG_ANALOG_SEL_1 10 11 RX_TST_BSCAN_EN_1 12 12 RX_CFG_OVR_PWRSF_1 13 13 RX_TERM_EN_1 14 14 ixPB1_RX_LANE1_SCI_STAT_OVRD_REG0 2 0x2206488 7 0 4294967295 RXPWR_1 0 2 ELECIDLEDETEN_1 3 3 REQUESTTRK_1 6 6 ENABLEFOM_1 7 7 REQUESTFOM_1 8 8 RESPONSEMODE_1 9 9 RXEYEFOM_1 10 17 ixPB1_RX_LANE2_CTRL_REG0 2 0x2206500 5 0 4294967295 RX_BACKUP_2 0 7 RX_DBG_ANALOG_SEL_2 10 11 RX_TST_BSCAN_EN_2 12 12 RX_CFG_OVR_PWRSF_2 13 13 RX_TERM_EN_2 14 14 ixPB1_RX_LANE2_SCI_STAT_OVRD_REG0 2 0x2206508 7 0 4294967295 RXPWR_2 0 2 ELECIDLEDETEN_2 3 3 REQUESTTRK_2 6 6 ENABLEFOM_2 7 7 REQUESTFOM_2 8 8 RESPONSEMODE_2 9 9 RXEYEFOM_2 10 17 ixPB1_RX_LANE3_CTRL_REG0 2 0x2206600 5 0 4294967295 RX_BACKUP_3 0 7 RX_DBG_ANALOG_SEL_3 10 11 RX_TST_BSCAN_EN_3 12 12 RX_CFG_OVR_PWRSF_3 13 13 RX_TERM_EN_3 14 14 ixPB1_RX_LANE3_SCI_STAT_OVRD_REG0 2 0x2206608 7 0 4294967295 RXPWR_3 0 2 ELECIDLEDETEN_3 3 3 REQUESTTRK_3 6 6 ENABLEFOM_3 7 7 REQUESTFOM_3 8 8 RESPONSEMODE_3 9 9 RXEYEFOM_3 10 17 ixPB1_RX_LANE4_CTRL_REG0 2 0x2206800 5 0 4294967295 RX_BACKUP_4 0 7 RX_DBG_ANALOG_SEL_4 10 11 RX_TST_BSCAN_EN_4 12 12 RX_CFG_OVR_PWRSF_4 13 13 RX_TERM_EN_4 14 14 ixPB1_RX_LANE4_SCI_STAT_OVRD_REG0 2 0x2206848 7 0 4294967295 RXPWR_4 0 2 ELECIDLEDETEN_4 3 3 REQUESTTRK_4 6 6 ENABLEFOM_4 7 7 REQUESTFOM_4 8 8 RESPONSEMODE_4 9 9 RXEYEFOM_4 10 17 ixPB1_RX_LANE5_CTRL_REG0 2 0x2206880 5 0 4294967295 RX_BACKUP_5 0 7 RX_DBG_ANALOG_SEL_5 10 11 RX_TST_BSCAN_EN_5 12 12 RX_CFG_OVR_PWRSF_5 13 13 RX_TERM_EN_5 14 14 ixPB1_RX_LANE5_SCI_STAT_OVRD_REG0 2 0x2206888 7 0 4294967295 RXPWR_5 0 2 ELECIDLEDETEN_5 3 3 REQUESTTRK_5 6 6 ENABLEFOM_5 7 7 REQUESTFOM_5 8 8 RESPONSEMODE_5 9 9 RXEYEFOM_5 10 17 ixPB1_RX_LANE6_CTRL_REG0 2 0x2206900 5 0 4294967295 RX_BACKUP_6 0 7 RX_DBG_ANALOG_SEL_6 10 11 RX_TST_BSCAN_EN_6 12 12 RX_CFG_OVR_PWRSF_6 13 13 RX_TERM_EN_6 14 14 ixPB1_RX_LANE6_SCI_STAT_OVRD_REG0 2 0x2206908 7 0 4294967295 RXPWR_6 0 2 ELECIDLEDETEN_6 3 3 REQUESTTRK_6 6 6 ENABLEFOM_6 7 7 REQUESTFOM_6 8 8 RESPONSEMODE_6 9 9 RXEYEFOM_6 10 17 ixPB1_RX_LANE7_CTRL_REG0 2 0x2206a00 5 0 4294967295 RX_BACKUP_7 0 7 RX_DBG_ANALOG_SEL_7 10 11 RX_TST_BSCAN_EN_7 12 12 RX_CFG_OVR_PWRSF_7 13 13 RX_TERM_EN_7 14 14 ixPB1_RX_LANE7_SCI_STAT_OVRD_REG0 2 0x2206a08 7 0 4294967295 RXPWR_7 0 2 ELECIDLEDETEN_7 3 3 REQUESTTRK_7 6 6 ENABLEFOM_7 7 7 REQUESTFOM_7 8 8 RESPONSEMODE_7 9 9 RXEYEFOM_7 10 17 ixPB1_RX_LANE8_CTRL_REG0 2 0x2207440 5 0 4294967295 RX_BACKUP_8 0 7 RX_DBG_ANALOG_SEL_8 10 11 RX_TST_BSCAN_EN_8 12 12 RX_CFG_OVR_PWRSF_8 13 13 RX_TERM_EN_8 14 14 ixPB1_RX_LANE8_SCI_STAT_OVRD_REG0 2 0x2207448 7 0 4294967295 RXPWR_8 0 2 ELECIDLEDETEN_8 3 3 REQUESTTRK_8 6 6 ENABLEFOM_8 7 7 REQUESTFOM_8 8 8 RESPONSEMODE_8 9 9 RXEYEFOM_8 10 17 ixPB1_RX_LANE9_CTRL_REG0 2 0x2207480 5 0 4294967295 RX_BACKUP_9 0 7 RX_DBG_ANALOG_SEL_9 10 11 RX_TST_BSCAN_EN_9 12 12 RX_CFG_OVR_PWRSF_9 13 13 RX_TERM_EN_9 14 14 ixPB1_RX_LANE9_SCI_STAT_OVRD_REG0 2 0x2207488 7 0 4294967295 RXPWR_9 0 2 ELECIDLEDETEN_9 3 3 REQUESTTRK_9 6 6 ENABLEFOM_9 7 7 REQUESTFOM_9 8 8 RESPONSEMODE_9 9 9 RXEYEFOM_9 10 17 ixPB1_RX_LANE10_CTRL_REG0 2 0x2207500 5 0 4294967295 RX_BACKUP_10 0 7 RX_DBG_ANALOG_SEL_10 10 11 RX_TST_BSCAN_EN_10 12 12 RX_CFG_OVR_PWRSF_10 13 13 RX_TERM_EN_10 14 14 ixPB1_RX_LANE10_SCI_STAT_OVRD_REG0 2 0x2207508 7 0 4294967295 RXPWR_10 0 2 ELECIDLEDETEN_10 3 3 REQUESTTRK_10 6 6 ENABLEFOM_10 7 7 REQUESTFOM_10 8 8 RESPONSEMODE_10 9 9 RXEYEFOM_10 10 17 ixPB1_RX_LANE11_CTRL_REG0 2 0x2207600 5 0 4294967295 RX_BACKUP_11 0 7 RX_DBG_ANALOG_SEL_11 10 11 RX_TST_BSCAN_EN_11 12 12 RX_CFG_OVR_PWRSF_11 13 13 RX_TERM_EN_11 14 14 ixPB1_RX_LANE11_SCI_STAT_OVRD_REG0 2 0x2207608 7 0 4294967295 RXPWR_11 0 2 ELECIDLEDETEN_11 3 3 REQUESTTRK_11 6 6 ENABLEFOM_11 7 7 REQUESTFOM_11 8 8 RESPONSEMODE_11 9 9 RXEYEFOM_11 10 17 ixPB1_RX_LANE12_CTRL_REG0 2 0x2207840 5 0 4294967295 RX_BACKUP_12 0 7 RX_DBG_ANALOG_SEL_12 10 11 RX_TST_BSCAN_EN_12 12 12 RX_CFG_OVR_PWRSF_12 13 13 RX_TERM_EN_12 14 14 ixPB1_RX_LANE12_SCI_STAT_OVRD_REG0 2 0x2207848 7 0 4294967295 RXPWR_12 0 2 ELECIDLEDETEN_12 3 3 REQUESTTRK_12 6 6 ENABLEFOM_12 7 7 REQUESTFOM_12 8 8 RESPONSEMODE_12 9 9 RXEYEFOM_12 10 17 ixPB1_RX_LANE13_CTRL_REG0 2 0x2207880 5 0 4294967295 RX_BACKUP_13 0 7 RX_DBG_ANALOG_SEL_13 10 11 RX_TST_BSCAN_EN_13 12 12 RX_CFG_OVR_PWRSF_13 13 13 RX_TERM_EN_13 14 14 ixPB1_RX_LANE13_SCI_STAT_OVRD_REG0 2 0x2207888 7 0 4294967295 RXPWR_13 0 2 ELECIDLEDETEN_13 3 3 REQUESTTRK_13 6 6 ENABLEFOM_13 7 7 REQUESTFOM_13 8 8 RESPONSEMODE_13 9 9 RXEYEFOM_13 10 17 ixPB1_RX_LANE14_CTRL_REG0 2 0x2207900 5 0 4294967295 RX_BACKUP_14 0 7 RX_DBG_ANALOG_SEL_14 10 11 RX_TST_BSCAN_EN_14 12 12 RX_CFG_OVR_PWRSF_14 13 13 RX_TERM_EN_14 14 14 ixPB1_RX_LANE14_SCI_STAT_OVRD_REG0 2 0x2207908 7 0 4294967295 RXPWR_14 0 2 ELECIDLEDETEN_14 3 3 REQUESTTRK_14 6 6 ENABLEFOM_14 7 7 REQUESTFOM_14 8 8 RESPONSEMODE_14 9 9 RXEYEFOM_14 10 17 ixPB1_RX_LANE15_CTRL_REG0 2 0x2207a00 5 0 4294967295 RX_BACKUP_15 0 7 RX_DBG_ANALOG_SEL_15 10 11 RX_TST_BSCAN_EN_15 12 12 RX_CFG_OVR_PWRSF_15 13 13 RX_TERM_EN_15 14 14 ixPB1_RX_LANE15_SCI_STAT_OVRD_REG0 2 0x2207a08 7 0 4294967295 RXPWR_15 0 2 ELECIDLEDETEN_15 3 3 REQUESTTRK_15 6 6 ENABLEFOM_15 7 7 REQUESTFOM_15 8 8 RESPONSEMODE_15 9 9 RXEYEFOM_15 10 17 ixPB1_TX_GLB_CTRL_REG0 2 0x2208000 12 0 4294967295 TX_DRV_DATA_ASRT_DLY_VAL 0 2 TX_DRV_DATA_DSRT_DLY_VAL 3 5 TX_CFG_RPTR_RST_VAL_GEN1 8 10 TX_CFG_RPTR_RST_VAL_GEN2 11 13 TX_CFG_RPTR_RST_VAL_GEN3 14 16 TX_STAGGER_CTRL 17 18 TX_DATA_CLK_GATING 19 19 TX_PRESET_TABLE_BYPASS 20 20 TX_COEFF_ROUND_EN 21 21 TX_COEFF_ROUND_DIR_VER 22 22 TX_DCLK_EN_LSX_ALWAYS_ON 23 23 TX_FRONTEND_PWRON_IN_PS4 24 24 ixPB1_TX_GLB_LANE_SKEW_CTRL 2 0x2208004 31 0 4294967295 TX_CFG_GROUPX1_EN_0 0 0 TX_CFG_GROUPX1_EN_1 1 1 TX_CFG_GROUPX1_EN_2 2 2 TX_CFG_GROUPX1_EN_3 3 3 TX_CFG_GROUPX1_EN_4 4 4 TX_CFG_GROUPX1_EN_5 5 5 TX_CFG_GROUPX1_EN_6 6 6 TX_CFG_GROUPX1_EN_7 7 7 TX_CFG_GROUPX1_EN_8 8 8 TX_CFG_GROUPX1_EN_9 9 9 TX_CFG_GROUPX1_EN_10 10 10 TX_CFG_GROUPX1_EN_11 11 11 TX_CFG_GROUPX1_EN_12 12 12 TX_CFG_GROUPX1_EN_13 13 13 TX_CFG_GROUPX1_EN_14 14 14 TX_CFG_GROUPX1_EN_15 15 15 TX_CFG_GROUPX2_EN_L0T1 16 16 TX_CFG_GROUPX2_EN_L2T3 17 17 TX_CFG_GROUPX2_EN_L4T5 18 18 TX_CFG_GROUPX2_EN_L6T7 19 19 TX_CFG_GROUPX2_EN_L8T9 20 20 TX_CFG_GROUPX2_EN_L10T11 21 21 TX_CFG_GROUPX2_EN_L12T13 22 22 TX_CFG_GROUPX2_EN_L14T15 23 23 TX_CFG_GROUPX4_EN_L0T3 24 24 TX_CFG_GROUPX4_EN_L4T7 25 25 TX_CFG_GROUPX4_EN_L8T11 26 26 TX_CFG_GROUPX4_EN_L12T15 27 27 TX_CFG_GROUPX8_EN_L0T7 28 28 TX_CFG_GROUPX8_EN_L8T15 29 29 TX_CFG_GROUPX16_EN_L0T15 30 30 ixPB1_TX_GLB_SCI_STAT_OVRD_REG0 2 0x2208010 12 0 4294967295 IGNR_TXPWR_CBI_UPDT_L0T3 0 0 IGNR_TXPWR_CBI_UPDT_L4T7 1 1 IGNR_TXPWR_CBI_UPDT_L8T11 2 2 IGNR_TXPWR_CBI_UPDT_L12T15 3 3 IGNR_COEFFICIENTID_CBI_UPDT_L0T3 8 8 IGNR_COEFFICIENTID_CBI_UPDT_L4T7 9 9 IGNR_COEFFICIENTID_CBI_UPDT_L8T11 10 10 IGNR_COEFFICIENTID_CBI_UPDT_L12T15 11 11 IGNR_COEFFICIENT_CBI_UPDT_L0T3 12 12 IGNR_COEFFICIENT_CBI_UPDT_L4T7 13 13 IGNR_COEFFICIENT_CBI_UPDT_L8T11 14 14 IGNR_COEFFICIENT_CBI_UPDT_L12T15 15 15 ixPB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0 2 0x2208014 32 0 4294967295 ACCEPT_ENTRY_0 0 0 ACCEPT_ENTRY_1 1 1 ACCEPT_ENTRY_2 2 2 ACCEPT_ENTRY_3 3 3 ACCEPT_ENTRY_4 4 4 ACCEPT_ENTRY_5 5 5 ACCEPT_ENTRY_6 6 6 ACCEPT_ENTRY_7 7 7 ACCEPT_ENTRY_8 8 8 ACCEPT_ENTRY_9 9 9 ACCEPT_ENTRY_10 10 10 ACCEPT_ENTRY_11 11 11 ACCEPT_ENTRY_12 12 12 ACCEPT_ENTRY_13 13 13 ACCEPT_ENTRY_14 14 14 ACCEPT_ENTRY_15 15 15 ACCEPT_ENTRY_16 16 16 ACCEPT_ENTRY_17 17 17 ACCEPT_ENTRY_18 18 18 ACCEPT_ENTRY_19 19 19 ACCEPT_ENTRY_20 20 20 ACCEPT_ENTRY_21 21 21 ACCEPT_ENTRY_22 22 22 ACCEPT_ENTRY_23 23 23 ACCEPT_ENTRY_24 24 24 ACCEPT_ENTRY_25 25 25 ACCEPT_ENTRY_26 26 26 ACCEPT_ENTRY_27 27 27 ACCEPT_ENTRY_28 28 28 ACCEPT_ENTRY_29 29 29 ACCEPT_ENTRY_30 30 30 ACCEPT_ENTRY_31 31 31 ixPB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1 2 0x2208018 32 0 4294967295 ACCEPT_ENTRY_32 0 0 ACCEPT_ENTRY_33 1 1 ACCEPT_ENTRY_34 2 2 ACCEPT_ENTRY_35 3 3 ACCEPT_ENTRY_36 4 4 ACCEPT_ENTRY_37 5 5 ACCEPT_ENTRY_38 6 6 ACCEPT_ENTRY_39 7 7 ACCEPT_ENTRY_40 8 8 ACCEPT_ENTRY_41 9 9 ACCEPT_ENTRY_42 10 10 ACCEPT_ENTRY_43 11 11 ACCEPT_ENTRY_44 12 12 ACCEPT_ENTRY_45 13 13 ACCEPT_ENTRY_46 14 14 ACCEPT_ENTRY_47 15 15 ACCEPT_ENTRY_48 16 16 ACCEPT_ENTRY_49 17 17 ACCEPT_ENTRY_50 18 18 ACCEPT_ENTRY_51 19 19 ACCEPT_ENTRY_52 20 20 ACCEPT_ENTRY_53 21 21 ACCEPT_ENTRY_54 22 22 ACCEPT_ENTRY_55 23 23 ACCEPT_ENTRY_56 24 24 ACCEPT_ENTRY_57 25 25 ACCEPT_ENTRY_58 26 26 ACCEPT_ENTRY_59 27 27 ACCEPT_ENTRY_60 28 28 ACCEPT_ENTRY_61 29 29 ACCEPT_ENTRY_62 30 30 ACCEPT_ENTRY_63 31 31 ixPB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2 2 0x220801c 32 0 4294967295 ACCEPT_ENTRY_64 0 0 ACCEPT_ENTRY_65 1 1 ACCEPT_ENTRY_66 2 2 ACCEPT_ENTRY_67 3 3 ACCEPT_ENTRY_68 4 4 ACCEPT_ENTRY_69 5 5 ACCEPT_ENTRY_70 6 6 ACCEPT_ENTRY_71 7 7 ACCEPT_ENTRY_72 8 8 ACCEPT_ENTRY_73 9 9 ACCEPT_ENTRY_74 10 10 ACCEPT_ENTRY_75 11 11 ACCEPT_ENTRY_76 12 12 ACCEPT_ENTRY_77 13 13 ACCEPT_ENTRY_78 14 14 ACCEPT_ENTRY_79 15 15 ACCEPT_ENTRY_80 16 16 ACCEPT_ENTRY_81 17 17 ACCEPT_ENTRY_82 18 18 ACCEPT_ENTRY_83 19 19 ACCEPT_ENTRY_84 20 20 ACCEPT_ENTRY_85 21 21 ACCEPT_ENTRY_86 22 22 ACCEPT_ENTRY_87 23 23 ACCEPT_ENTRY_88 24 24 ACCEPT_ENTRY_89 25 25 ACCEPT_ENTRY_90 26 26 ACCEPT_ENTRY_91 27 27 ACCEPT_ENTRY_92 28 28 ACCEPT_ENTRY_93 29 29 ACCEPT_ENTRY_94 30 30 ACCEPT_ENTRY_95 31 31 ixPB1_TX_GLB_COEFF_ACCEPT_TABLE_REG3 2 0x2208020 14 0 4294967295 ACCEPT_ENTRY_96 0 0 ACCEPT_ENTRY_97 1 1 ACCEPT_ENTRY_98 2 2 ACCEPT_ENTRY_99 3 3 ACCEPT_ENTRY_100 4 4 ACCEPT_ENTRY_101 5 5 ACCEPT_ENTRY_102 6 6 ACCEPT_ENTRY_103 7 7 ACCEPT_ENTRY_104 8 8 ACCEPT_ENTRY_105 9 9 ACCEPT_ENTRY_106 10 10 ACCEPT_ENTRY_107 11 11 ACCEPT_ENTRY_108 12 12 ACCEPT_ENTRY_109 13 13 ixPB1_TX_GLB_OVRD_REG0 2 0x2208030 12 0 4294967295 TX_CFG_DCLK_DIV_OVRD_VAL 0 2 TX_CFG_DCLK_DIV_OVRD_EN 3 3 TX_CFG_DRV0_EN_GEN1_OVRD_VAL 4 7 TX_CFG_DRV0_EN_OVRD_EN 8 8 TX_CFG_DRV0_TAP_SEL_GEN1_OVRD_VAL 9 12 TX_CFG_DRV0_TAP_SEL_OVRD_EN 13 13 TX_CFG_DRV1_EN_GEN1_OVRD_VAL 14 18 TX_CFG_DRV1_EN_OVRD_EN 19 19 TX_CFG_DRV1_TAP_SEL_GEN1_OVRD_VAL 20 24 TX_CFG_DRV1_TAP_SEL_OVRD_EN 25 25 TX_CFG_DRV2_EN_GEN1_OVRD_VAL 26 29 TX_CFG_DRV2_EN_OVRD_EN 30 30 ixPB1_TX_GLB_OVRD_REG1 2 0x2208034 20 0 4294967295 TX_CFG_DRV2_TAP_SEL_GEN1_OVRD_VAL 0 3 TX_CFG_DRV2_TAP_SEL_OVRD_EN 4 4 TX_CFG_DRVX_EN_GEN1_OVRD_VAL 5 5 TX_CFG_DRVX_EN_OVRD_EN 6 6 TX_CFG_DRVX_TAP_SEL_GEN1_OVRD_VAL 7 7 TX_CFG_DRVX_TAP_SEL_OVRD_EN 8 8 TX_CFG_PLLCLK_SEL_OVRD_VAL 9 9 TX_CFG_PLLCLK_SEL_OVRD_EN 10 10 TX_CFG_TCLK_DIV_OVRD_VAL 11 11 TX_CFG_TCLK_DIV_OVRD_EN 12 12 TX_CMDET_EN_OVRD_VAL 13 13 TX_CMDET_EN_OVRD_EN 14 14 TX_DATA_IN_OVRD_VAL 15 24 TX_DATA_IN_OVRD_EN 25 25 TX_RPTR_RSTN_OVRD_VAL 26 26 TX_RPTR_RSTN_OVRD_EN 27 27 TX_RXDET_EN_OVRD_VAL 28 28 TX_RXDET_EN_OVRD_EN 29 29 TX_WPTR_RSTN_OVRD_VAL 30 30 TX_WPTR_RSTN_OVRD_EN 31 31 ixPB1_TX_GLB_OVRD_REG2 2 0x2208038 16 0 4294967295 TX_WRITE_EN_OVRD_VAL 0 0 TX_WRITE_EN_OVRD_EN 1 1 TX_CFG_GROUPX1_EN_OVRD_VAL 2 2 TX_CFG_GROUPX1_EN_OVRD_EN 3 3 TX_CFG_GROUPX2_EN_OVRD_VAL 4 4 TX_CFG_GROUPX2_EN_OVRD_EN 5 5 TX_CFG_GROUPX4_EN_OVRD_VAL 6 6 TX_CFG_GROUPX4_EN_OVRD_EN 7 7 TX_CFG_GROUPX8_EN_OVRD_VAL 8 8 TX_CFG_GROUPX8_EN_OVRD_EN 9 9 TX_CFG_GROUPX16_EN_OVRD_VAL 10 10 TX_CFG_GROUPX16_EN_OVRD_EN 11 11 TX_CFG_DRV0_EN_GEN2_OVRD_VAL 12 15 TX_CFG_DRV0_TAP_SEL_GEN2_OVRD_VAL 16 19 TX_CFG_DRV1_EN_GEN2_OVRD_VAL 20 24 TX_CFG_DRV1_TAP_SEL_GEN2_OVRD_VAL 25 29 ixPB1_TX_GLB_OVRD_REG3 2 0x220803c 9 0 4294967295 TX_CFG_DRV2_EN_GEN2_OVRD_VAL 0 3 TX_CFG_DRV2_TAP_SEL_GEN2_OVRD_VAL 4 7 TX_CFG_DRVX_EN_GEN2_OVRD_VAL 8 8 TX_CFG_DRVX_TAP_SEL_GEN2_OVRD_VAL 9 9 TX_CFG_DRV0_EN_GEN3_OVRD_VAL 10 13 TX_CFG_DRV0_TAP_SEL_GEN3_OVRD_VAL 14 17 TX_CFG_DRV1_EN_GEN3_OVRD_VAL 18 22 TX_CFG_DRV1_TAP_SEL_GEN3_OVRD_VAL 23 27 TX_CFG_DRV2_EN_GEN3_OVRD_VAL 28 31 ixPB1_TX_GLB_OVRD_REG4 2 0x2208040 3 0 4294967295 TX_CFG_DRV2_TAP_SEL_GEN3_OVRD_VAL 0 3 TX_CFG_DRVX_EN_GEN3_OVRD_VAL 4 4 TX_CFG_DRVX_TAP_SEL_GEN3_OVRD_VAL 5 5 ixPB1_TX_LANE0_CTRL_REG0 2 0x2208440 4 0 4294967295 TX_CFG_DISPCLK_MODE_0 0 0 TX_CFG_INV_DATA_0 1 1 TX_CFG_SWING_BOOST_EN_0 2 2 TX_DBG_PRBS_EN_0 3 3 ixPB1_TX_LANE0_OVRD_REG0 2 0x2208444 8 0 4294967295 TX_DCLK_EN_OVRD_VAL_0 0 0 TX_DCLK_EN_OVRD_EN_0 1 1 TX_DRV_DATA_EN_OVRD_VAL_0 2 2 TX_DRV_DATA_EN_OVRD_EN_0 3 3 TX_DRV_PWRON_OVRD_VAL_0 4 4 TX_DRV_PWRON_OVRD_EN_0 5 5 TX_FRONTEND_PWRON_OVRD_VAL_0 6 6 TX_FRONTEND_PWRON_OVRD_EN_0 7 7 ixPB1_TX_LANE0_SCI_STAT_OVRD_REG0 2 0x2208448 5 0 4294967295 TXPWR_0 0 2 TXMARG_0 4 6 DEEMPH_0 7 7 COEFFICIENTID_0 8 9 COEFFICIENT_0 10 15 ixPB1_TX_LANE1_CTRL_REG0 2 0x2208480 4 0 4294967295 TX_CFG_DISPCLK_MODE_1 0 0 TX_CFG_INV_DATA_1 1 1 TX_CFG_SWING_BOOST_EN_1 2 2 TX_DBG_PRBS_EN_1 3 3 ixPB1_TX_LANE1_OVRD_REG0 2 0x2208484 8 0 4294967295 TX_DCLK_EN_OVRD_VAL_1 0 0 TX_DCLK_EN_OVRD_EN_1 1 1 TX_DRV_DATA_EN_OVRD_VAL_1 2 2 TX_DRV_DATA_EN_OVRD_EN_1 3 3 TX_DRV_PWRON_OVRD_VAL_1 4 4 TX_DRV_PWRON_OVRD_EN_1 5 5 TX_FRONTEND_PWRON_OVRD_VAL_1 6 6 TX_FRONTEND_PWRON_OVRD_EN_1 7 7 ixPB1_TX_LANE1_SCI_STAT_OVRD_REG0 2 0x2208488 5 0 4294967295 TXPWR_1 0 2 TXMARG_1 4 6 DEEMPH_1 7 7 COEFFICIENTID_1 8 9 COEFFICIENT_1 10 15 ixPB1_TX_LANE2_CTRL_REG0 2 0x2208500 4 0 4294967295 TX_CFG_DISPCLK_MODE_2 0 0 TX_CFG_INV_DATA_2 1 1 TX_CFG_SWING_BOOST_EN_2 2 2 TX_DBG_PRBS_EN_2 3 3 ixPB1_TX_LANE2_OVRD_REG0 2 0x2208504 8 0 4294967295 TX_DCLK_EN_OVRD_VAL_2 0 0 TX_DCLK_EN_OVRD_EN_2 1 1 TX_DRV_DATA_EN_OVRD_VAL_2 2 2 TX_DRV_DATA_EN_OVRD_EN_2 3 3 TX_DRV_PWRON_OVRD_VAL_2 4 4 TX_DRV_PWRON_OVRD_EN_2 5 5 TX_FRONTEND_PWRON_OVRD_VAL_2 6 6 TX_FRONTEND_PWRON_OVRD_EN_2 7 7 ixPB1_TX_LANE2_SCI_STAT_OVRD_REG0 2 0x2208508 5 0 4294967295 TXPWR_2 0 2 TXMARG_2 4 6 DEEMPH_2 7 7 COEFFICIENTID_2 8 9 COEFFICIENT_2 10 15 ixPB1_TX_LANE3_CTRL_REG0 2 0x2208600 4 0 4294967295 TX_CFG_DISPCLK_MODE_3 0 0 TX_CFG_INV_DATA_3 1 1 TX_CFG_SWING_BOOST_EN_3 2 2 TX_DBG_PRBS_EN_3 3 3 ixPB1_TX_LANE3_OVRD_REG0 2 0x2208604 8 0 4294967295 TX_DCLK_EN_OVRD_VAL_3 0 0 TX_DCLK_EN_OVRD_EN_3 1 1 TX_DRV_DATA_EN_OVRD_VAL_3 2 2 TX_DRV_DATA_EN_OVRD_EN_3 3 3 TX_DRV_PWRON_OVRD_VAL_3 4 4 TX_DRV_PWRON_OVRD_EN_3 5 5 TX_FRONTEND_PWRON_OVRD_VAL_3 6 6 TX_FRONTEND_PWRON_OVRD_EN_3 7 7 ixPB1_TX_LANE3_SCI_STAT_OVRD_REG0 2 0x2208608 5 0 4294967295 TXPWR_3 0 2 TXMARG_3 4 6 DEEMPH_3 7 7 COEFFICIENTID_3 8 9 COEFFICIENT_3 10 15 ixPB1_TX_LANE4_CTRL_REG0 2 0x2208840 4 0 4294967295 TX_CFG_DISPCLK_MODE_4 0 0 TX_CFG_INV_DATA_4 1 1 TX_CFG_SWING_BOOST_EN_4 2 2 TX_DBG_PRBS_EN_4 3 3 ixPB1_TX_LANE4_OVRD_REG0 2 0x2208844 8 0 4294967295 TX_DCLK_EN_OVRD_VAL_4 0 0 TX_DCLK_EN_OVRD_EN_4 1 1 TX_DRV_DATA_EN_OVRD_VAL_4 2 2 TX_DRV_DATA_EN_OVRD_EN_4 3 3 TX_DRV_PWRON_OVRD_VAL_4 4 4 TX_DRV_PWRON_OVRD_EN_4 5 5 TX_FRONTEND_PWRON_OVRD_VAL_4 6 6 TX_FRONTEND_PWRON_OVRD_EN_4 7 7 ixPB1_TX_LANE4_SCI_STAT_OVRD_REG0 2 0x2208848 5 0 4294967295 TXPWR_4 0 2 TXMARG_4 4 6 DEEMPH_4 7 7 COEFFICIENTID_4 8 9 COEFFICIENT_4 10 15 ixPB1_TX_LANE5_CTRL_REG0 2 0x2208880 4 0 4294967295 TX_CFG_DISPCLK_MODE_5 0 0 TX_CFG_INV_DATA_5 1 1 TX_CFG_SWING_BOOST_EN_5 2 2 TX_DBG_PRBS_EN_5 3 3 ixPB1_TX_LANE5_OVRD_REG0 2 0x2208884 8 0 4294967295 TX_DCLK_EN_OVRD_VAL_5 0 0 TX_DCLK_EN_OVRD_EN_5 1 1 TX_DRV_DATA_EN_OVRD_VAL_5 2 2 TX_DRV_DATA_EN_OVRD_EN_5 3 3 TX_DRV_PWRON_OVRD_VAL_5 4 4 TX_DRV_PWRON_OVRD_EN_5 5 5 TX_FRONTEND_PWRON_OVRD_VAL_5 6 6 TX_FRONTEND_PWRON_OVRD_EN_5 7 7 ixPB1_TX_LANE5_SCI_STAT_OVRD_REG0 2 0x2208888 5 0 4294967295 TXPWR_5 0 2 TXMARG_5 4 6 DEEMPH_5 7 7 COEFFICIENTID_5 8 9 COEFFICIENT_5 10 15 ixPB1_TX_LANE6_CTRL_REG0 2 0x2208900 4 0 4294967295 TX_CFG_DISPCLK_MODE_6 0 0 TX_CFG_INV_DATA_6 1 1 TX_CFG_SWING_BOOST_EN_6 2 2 TX_DBG_PRBS_EN_6 3 3 ixPB1_TX_LANE6_OVRD_REG0 2 0x2208904 8 0 4294967295 TX_DCLK_EN_OVRD_VAL_6 0 0 TX_DCLK_EN_OVRD_EN_6 1 1 TX_DRV_DATA_EN_OVRD_VAL_6 2 2 TX_DRV_DATA_EN_OVRD_EN_6 3 3 TX_DRV_PWRON_OVRD_VAL_6 4 4 TX_DRV_PWRON_OVRD_EN_6 5 5 TX_FRONTEND_PWRON_OVRD_VAL_6 6 6 TX_FRONTEND_PWRON_OVRD_EN_6 7 7 ixPB1_TX_LANE6_SCI_STAT_OVRD_REG0 2 0x2208908 5 0 4294967295 TXPWR_6 0 2 TXMARG_6 4 6 DEEMPH_6 7 7 COEFFICIENTID_6 8 9 COEFFICIENT_6 10 15 ixPB1_TX_LANE7_CTRL_REG0 2 0x2208a00 4 0 4294967295 TX_CFG_DISPCLK_MODE_7 0 0 TX_CFG_INV_DATA_7 1 1 TX_CFG_SWING_BOOST_EN_7 2 2 TX_DBG_PRBS_EN_7 3 3 ixPB1_TX_LANE7_OVRD_REG0 2 0x2208a04 8 0 4294967295 TX_DCLK_EN_OVRD_VAL_7 0 0 TX_DCLK_EN_OVRD_EN_7 1 1 TX_DRV_DATA_EN_OVRD_VAL_7 2 2 TX_DRV_DATA_EN_OVRD_EN_7 3 3 TX_DRV_PWRON_OVRD_VAL_7 4 4 TX_DRV_PWRON_OVRD_EN_7 5 5 TX_FRONTEND_PWRON_OVRD_VAL_7 6 6 TX_FRONTEND_PWRON_OVRD_EN_7 7 7 ixPB1_TX_LANE7_SCI_STAT_OVRD_REG0 2 0x2208a08 5 0 4294967295 TXPWR_7 0 2 TXMARG_7 4 6 DEEMPH_7 7 7 COEFFICIENTID_7 8 9 COEFFICIENT_7 10 15 ixPB1_TX_LANE8_CTRL_REG0 2 0x2209440 4 0 4294967295 TX_CFG_DISPCLK_MODE_8 0 0 TX_CFG_INV_DATA_8 1 1 TX_CFG_SWING_BOOST_EN_8 2 2 TX_DBG_PRBS_EN_8 3 3 ixPB1_TX_LANE8_OVRD_REG0 2 0x2209444 8 0 4294967295 TX_DCLK_EN_OVRD_VAL_8 0 0 TX_DCLK_EN_OVRD_EN_8 1 1 TX_DRV_DATA_EN_OVRD_VAL_8 2 2 TX_DRV_DATA_EN_OVRD_EN_8 3 3 TX_DRV_PWRON_OVRD_VAL_8 4 4 TX_DRV_PWRON_OVRD_EN_8 5 5 TX_FRONTEND_PWRON_OVRD_VAL_8 6 6 TX_FRONTEND_PWRON_OVRD_EN_8 7 7 ixPB1_TX_LANE8_SCI_STAT_OVRD_REG0 2 0x2209448 5 0 4294967295 TXPWR_8 0 2 TXMARG_8 4 6 DEEMPH_8 7 7 COEFFICIENTID_8 8 9 COEFFICIENT_8 10 15 ixPB1_TX_LANE9_CTRL_REG0 2 0x2209480 4 0 4294967295 TX_CFG_DISPCLK_MODE_9 0 0 TX_CFG_INV_DATA_9 1 1 TX_CFG_SWING_BOOST_EN_9 2 2 TX_DBG_PRBS_EN_9 3 3 ixPB1_TX_LANE9_OVRD_REG0 2 0x2209484 8 0 4294967295 TX_DCLK_EN_OVRD_VAL_9 0 0 TX_DCLK_EN_OVRD_EN_9 1 1 TX_DRV_DATA_EN_OVRD_VAL_9 2 2 TX_DRV_DATA_EN_OVRD_EN_9 3 3 TX_DRV_PWRON_OVRD_VAL_9 4 4 TX_DRV_PWRON_OVRD_EN_9 5 5 TX_FRONTEND_PWRON_OVRD_VAL_9 6 6 TX_FRONTEND_PWRON_OVRD_EN_9 7 7 ixPB1_TX_LANE9_SCI_STAT_OVRD_REG0 2 0x2209488 5 0 4294967295 TXPWR_9 0 2 TXMARG_9 4 6 DEEMPH_9 7 7 COEFFICIENTID_9 8 9 COEFFICIENT_9 10 15 ixPB1_TX_LANE10_CTRL_REG0 2 0x2209500 4 0 4294967295 TX_CFG_DISPCLK_MODE_10 0 0 TX_CFG_INV_DATA_10 1 1 TX_CFG_SWING_BOOST_EN_10 2 2 TX_DBG_PRBS_EN_10 3 3 ixPB1_TX_LANE10_OVRD_REG0 2 0x2209504 8 0 4294967295 TX_DCLK_EN_OVRD_VAL_10 0 0 TX_DCLK_EN_OVRD_EN_10 1 1 TX_DRV_DATA_EN_OVRD_VAL_10 2 2 TX_DRV_DATA_EN_OVRD_EN_10 3 3 TX_DRV_PWRON_OVRD_VAL_10 4 4 TX_DRV_PWRON_OVRD_EN_10 5 5 TX_FRONTEND_PWRON_OVRD_VAL_10 6 6 TX_FRONTEND_PWRON_OVRD_EN_10 7 7 ixPB1_TX_LANE10_SCI_STAT_OVRD_REG0 2 0x2209508 5 0 4294967295 TXPWR_10 0 2 TXMARG_10 4 6 DEEMPH_10 7 7 COEFFICIENTID_10 8 9 COEFFICIENT_10 10 15 ixPB1_TX_LANE11_CTRL_REG0 2 0x2209600 4 0 4294967295 TX_CFG_DISPCLK_MODE_11 0 0 TX_CFG_INV_DATA_11 1 1 TX_CFG_SWING_BOOST_EN_11 2 2 TX_DBG_PRBS_EN_11 3 3 ixPB1_TX_LANE11_OVRD_REG0 2 0x2209604 8 0 4294967295 TX_DCLK_EN_OVRD_VAL_11 0 0 TX_DCLK_EN_OVRD_EN_11 1 1 TX_DRV_DATA_EN_OVRD_VAL_11 2 2 TX_DRV_DATA_EN_OVRD_EN_11 3 3 TX_DRV_PWRON_OVRD_VAL_11 4 4 TX_DRV_PWRON_OVRD_EN_11 5 5 TX_FRONTEND_PWRON_OVRD_VAL_11 6 6 TX_FRONTEND_PWRON_OVRD_EN_11 7 7 ixPB1_TX_LANE11_SCI_STAT_OVRD_REG0 2 0x2209608 5 0 4294967295 TXPWR_11 0 2 TXMARG_11 4 6 DEEMPH_11 7 7 COEFFICIENTID_11 8 9 COEFFICIENT_11 10 15 ixPB1_TX_LANE12_CTRL_REG0 2 0x2209840 4 0 4294967295 TX_CFG_DISPCLK_MODE_12 0 0 TX_CFG_INV_DATA_12 1 1 TX_CFG_SWING_BOOST_EN_12 2 2 TX_DBG_PRBS_EN_12 3 3 ixPB1_TX_LANE12_OVRD_REG0 2 0x2209844 8 0 4294967295 TX_DCLK_EN_OVRD_VAL_12 0 0 TX_DCLK_EN_OVRD_EN_12 1 1 TX_DRV_DATA_EN_OVRD_VAL_12 2 2 TX_DRV_DATA_EN_OVRD_EN_12 3 3 TX_DRV_PWRON_OVRD_VAL_12 4 4 TX_DRV_PWRON_OVRD_EN_12 5 5 TX_FRONTEND_PWRON_OVRD_VAL_12 6 6 TX_FRONTEND_PWRON_OVRD_EN_12 7 7 ixPB1_TX_LANE12_SCI_STAT_OVRD_REG0 2 0x2209848 5 0 4294967295 TXPWR_12 0 2 TXMARG_12 4 6 DEEMPH_12 7 7 COEFFICIENTID_12 8 9 COEFFICIENT_12 10 15 ixPB1_TX_LANE13_CTRL_REG0 2 0x2209880 4 0 4294967295 TX_CFG_DISPCLK_MODE_13 0 0 TX_CFG_INV_DATA_13 1 1 TX_CFG_SWING_BOOST_EN_13 2 2 TX_DBG_PRBS_EN_13 3 3 ixPB1_TX_LANE13_OVRD_REG0 2 0x2209884 8 0 4294967295 TX_DCLK_EN_OVRD_VAL_13 0 0 TX_DCLK_EN_OVRD_EN_13 1 1 TX_DRV_DATA_EN_OVRD_VAL_13 2 2 TX_DRV_DATA_EN_OVRD_EN_13 3 3 TX_DRV_PWRON_OVRD_VAL_13 4 4 TX_DRV_PWRON_OVRD_EN_13 5 5 TX_FRONTEND_PWRON_OVRD_VAL_13 6 6 TX_FRONTEND_PWRON_OVRD_EN_13 7 7 ixPB1_TX_LANE13_SCI_STAT_OVRD_REG0 2 0x2209888 5 0 4294967295 TXPWR_13 0 2 TXMARG_13 4 6 DEEMPH_13 7 7 COEFFICIENTID_13 8 9 COEFFICIENT_13 10 15 ixPB1_TX_LANE14_CTRL_REG0 2 0x2209900 4 0 4294967295 TX_CFG_DISPCLK_MODE_14 0 0 TX_CFG_INV_DATA_14 1 1 TX_CFG_SWING_BOOST_EN_14 2 2 TX_DBG_PRBS_EN_14 3 3 ixPB1_TX_LANE14_OVRD_REG0 2 0x2209904 8 0 4294967295 TX_DCLK_EN_OVRD_VAL_14 0 0 TX_DCLK_EN_OVRD_EN_14 1 1 TX_DRV_DATA_EN_OVRD_VAL_14 2 2 TX_DRV_DATA_EN_OVRD_EN_14 3 3 TX_DRV_PWRON_OVRD_VAL_14 4 4 TX_DRV_PWRON_OVRD_EN_14 5 5 TX_FRONTEND_PWRON_OVRD_VAL_14 6 6 TX_FRONTEND_PWRON_OVRD_EN_14 7 7 ixPB1_TX_LANE14_SCI_STAT_OVRD_REG0 2 0x2209908 5 0 4294967295 TXPWR_14 0 2 TXMARG_14 4 6 DEEMPH_14 7 7 COEFFICIENTID_14 8 9 COEFFICIENT_14 10 15 ixPB1_TX_LANE15_CTRL_REG0 2 0x2209a00 4 0 4294967295 TX_CFG_DISPCLK_MODE_15 0 0 TX_CFG_INV_DATA_15 1 1 TX_CFG_SWING_BOOST_EN_15 2 2 TX_DBG_PRBS_EN_15 3 3 ixPB1_TX_LANE15_OVRD_REG0 2 0x2209a04 8 0 4294967295 TX_DCLK_EN_OVRD_VAL_15 0 0 TX_DCLK_EN_OVRD_EN_15 1 1 TX_DRV_DATA_EN_OVRD_VAL_15 2 2 TX_DRV_DATA_EN_OVRD_EN_15 3 3 TX_DRV_PWRON_OVRD_VAL_15 4 4 TX_DRV_PWRON_OVRD_EN_15 5 5 TX_FRONTEND_PWRON_OVRD_VAL_15 6 6 TX_FRONTEND_PWRON_OVRD_EN_15 7 7 ixPB1_TX_LANE15_SCI_STAT_OVRD_REG0 2 0x2209a08 5 0 4294967295 TXPWR_15 0 2 TXMARG_15 4 6 DEEMPH_15 7 7 COEFFICIENTID_15 8 9 COEFFICIENT_15 10 15 ixPB0_PIF_SCRATCH 2 0x1100001 1 0 4294967295 PIF_SCRATCH 0 31 ixPB0_PIF_HW_DEBUG 2 0x1100002 16 0 4294967295 HW_00_DEBUG 0 0 HW_01_DEBUG 1 1 HW_02_DEBUG 2 2 HW_03_DEBUG 3 3 HW_04_DEBUG 4 4 HW_05_DEBUG 5 5 HW_06_DEBUG 6 6 HW_07_DEBUG 7 7 HW_08_DEBUG 8 8 HW_09_DEBUG 9 9 HW_10_DEBUG 10 10 HW_11_DEBUG 11 11 HW_12_DEBUG 12 12 HW_13_DEBUG 13 13 HW_14_DEBUG 14 14 HW_15_DEBUG 15 15 ixPB0_PIF_STRAP_0 2 0x1100003 14 0 4294967295 STRAP_TX_RDY_XTND_DIS 1 1 STRAP_RX_RDY_XTND_DIS 2 2 STRAP_TX_STATUS_XTND_DIS 3 3 STRAP_RX_STATUS_XTND_DIS 4 4 STRAP_FORCE_OWN_MSTR 5 5 STRAP_PIF_CDR_EN_MODE 6 7 STRAP_RX_EI_FILTER 8 9 STRAP_RX_DIS_HLD_EIE_IN_PS1 10 10 STRAP_RX_DIS_HLD_EIE_IN_PS2 11 11 STRAP_PIF_BIT_12 12 12 STRAP_PIF_BIT_13 13 13 STRAP_PIF_BIT_14 14 14 STRAP_PIF_BIT_15 15 15 STRAP_PIF_BIT_16 16 16 ixPB0_PIF_CTRL 2 0x1100004 13 0 4294967295 PIF_PLL_PWRDN_EN 0 0 DTM_FORCE_FREQDIV_X1 1 1 PIF_PLL_HNDSHK_EARLY_ABORT 2 2 PIF_PLL_PWRDN_EARLY_EXIT 3 3 PHY_RST_PWROK_VDD 4 4 PIF_PLL_STATUS 6 7 PIF_PLL_DEGRADE_OFF_VOTE 8 8 PIF_PLL_UNUSED_OFF_VOTE 9 9 PIF_PLL_DEGRADE_S2_VOTE 10 10 PIF_PG_EXIT_MODE 11 11 PIF_DEGRADE_PWR_PLL_MODE 12 12 PIF_LANEUNUSED_AFFECT_GANG 13 13 PIF_PG_ABORT_DISABLE 14 14 ixPB0_PIF_TX_CTRL 2 0x1100008 11 0 4294967295 TXPWR_IN_S2 0 2 TXPWR_IN_SPDCHNG 3 5 TXPWR_IN_OFF 6 8 TXPWR_IN_DEGRADE 9 11 TXPWR_IN_UNUSED 12 14 TXPWR_IN_INIT 15 17 TXPWR_IN_PLL_OFF 18 20 TXPWR_IN_DEGRADE_MODE 21 21 TXPWR_IN_UNUSED_MODE 22 22 TXPWR_GATING_IN_L1 23 23 TXPWR_GATING_IN_UNUSED 24 24 ixPB0_PIF_TX_CTRL2 2 0x1100009 13 0 4294967295 TX_RDY_DASRT_COUNT 0 2 TX_STATUS_DASRT_COUNT 3 5 TXPHYSTATUS_DELAY 6 8 TX_L1_PG_PHY_STATUS_MODE 9 9 TX_OFF_PG_PHY_STATUS_MODE 10 10 TX_HIGH_IMP_STAG_MP 16 16 TX_HIGH_IMP_STAG_MODE 17 18 TX_FORCE_DATA_VALID 21 21 TX_L0_TO_HIZ_DLY 22 24 TX_FIFO_INIT_UPCONFIG 25 25 TX_HIZ_TO_L0_DLY 26 28 TX_LINKSPEED_ACK_IN_S2 29 29 TX_DELAY_FIFO_INIT_IN_S1 30 30 ixPB0_PIF_RX_CTRL 2 0x110000a 13 0 4294967295 RXPWR_IN_S2 0 2 RXPWR_IN_SPDCHNG 3 5 RXPWR_IN_OFF 6 8 RXPWR_IN_DEGRADE 9 11 RXPWR_IN_UNUSED 12 14 RXPWR_IN_INIT 15 17 RXPWR_IN_PLL_OFF 18 20 RXPWR_IN_DEGRADE_MODE 21 21 RXPWR_IN_UNUSED_MODE 22 22 RXPWR_GATING_IN_L1 23 23 RXPWR_GATING_IN_UNUSED 24 24 RX_HLD_EIE_COUNT 25 25 RX_EI_DET_IN_PS2_DEGRADE 26 26 ixPB0_PIF_RX_CTRL2 2 0x110000b 12 0 4294967295 RX_RDY_DASRT_COUNT 0 2 RX_STATUS_DASRT_COUNT 3 5 RXPHYSTATUS_DELAY 6 8 RX_L1_PG_PHY_STATUS_MODE 9 9 RX_OFF_PG_PHY_STATUS_MODE 10 10 FORCE_CDREN_IN_L0S 16 16 EI_DET_CYCLE_MODE 17 18 EI_DET_ON_TIME 19 20 EI_DET_OFF_TIME 21 23 EI_DET_CYCLE_DIS_IN_PS1 24 24 RX_CDR_XTND_MODE 25 26 RX_L0S_TO_L0_DETECT_EI 27 27 ixPB0_PIF_GLB_OVRD 2 0x110000c 9 0 4294967295 RXDETECT_OVERRIDE_VAL_0 0 0 RXDETECT_OVERRIDE_VAL_1 1 1 RXDETECT_OVERRIDE_VAL_2 2 2 RXDETECT_OVERRIDE_VAL_3 3 3 RXDETECT_OVERRIDE_VAL_4 4 4 RXDETECT_OVERRIDE_VAL_5 5 5 RXDETECT_OVERRIDE_VAL_6 6 6 RXDETECT_OVERRIDE_VAL_7 7 7 RXDETECT_OVERRIDE_EN 16 16 ixPB0_PIF_GLB_OVRD2 2 0x110000d 15 0 4294967295 X2_LANE_1_0_OVRD 0 0 X2_LANE_3_2_OVRD 1 1 X2_LANE_5_4_OVRD 2 2 X2_LANE_7_6_OVRD 3 3 X2_LANE_9_8_OVRD 4 4 X2_LANE_11_10_OVRD 5 5 X2_LANE_13_12_OVRD 6 6 X2_LANE_15_14_OVRD 7 7 X4_LANE_3_0_OVRD 8 8 X4_LANE_7_4_OVRD 9 9 X4_LANE_11_8_OVRD 10 10 X4_LANE_15_12_OVRD 11 11 X8_LANE_7_0_OVRD 16 16 X8_LANE_15_8_OVRD 17 17 X16_LANE_15_0_OVRD 20 20 ixPB0_PIF_BIF_CMD_STATUS 2 0x1100010 32 0 4294967295 TXPHYSTATUS_0 0 0 TXPHYSTATUS_1 1 1 TXPHYSTATUS_2 2 2 TXPHYSTATUS_3 3 3 TXPHYSTATUS_4 4 4 TXPHYSTATUS_5 5 5 TXPHYSTATUS_6 6 6 TXPHYSTATUS_7 7 7 RXPHYSTATUS_0 8 8 RXPHYSTATUS_1 9 9 RXPHYSTATUS_2 10 10 RXPHYSTATUS_3 11 11 RXPHYSTATUS_4 12 12 RXPHYSTATUS_5 13 13 RXPHYSTATUS_6 14 14 RXPHYSTATUS_7 15 15 BPHY_CORE_TX_RDY_0 16 16 BPHY_CORE_TX_RDY_1 17 17 BPHY_CORE_TX_RDY_2 18 18 BPHY_CORE_TX_RDY_3 19 19 BPHY_CORE_TX_RDY_4 20 20 BPHY_CORE_TX_RDY_5 21 21 BPHY_CORE_TX_RDY_6 22 22 BPHY_CORE_TX_RDY_7 23 23 BPHY_CORE_RX_RDY_0 24 24 BPHY_CORE_RX_RDY_1 25 25 BPHY_CORE_RX_RDY_2 26 26 BPHY_CORE_RX_RDY_3 27 27 BPHY_CORE_RX_RDY_4 28 28 BPHY_CORE_RX_RDY_5 29 29 BPHY_CORE_RX_RDY_6 30 30 BPHY_CORE_RX_RDY_7 31 31 ixPB0_PIF_CMD_BUS_CTRL 2 0x1100011 7 0 4294967295 CMD_BUS_SCHL_MODE 0 1 CMD_BUS_STAG_MODE 2 3 CMD_BUS_STAG_DIS 4 4 CMD_BUS_SCH_REQ_MODE 5 6 CMD_BUS_IGNR_PEND_PWR 7 7 SEND_GANGED_MODE_UPDATE_FOR_OFFPG_LANES 8 8 CMD_BUS_IGNR_PWR_NOT_ON 9 9 ixPB0_PIF_CMD_BUS_GLB_OVRD 2 0x1100013 15 0 4294967295 TXMARG_OVRD_EN 0 0 DEEMPH_OVRD_EN 1 1 PLLFREQ_OVRD_EN 2 2 TXMARG 3 5 DEEMPH 6 6 PLLFREQ 7 8 RESPONSEMODE_PIF_OVRD 9 9 CMD_BUS_LANE_DIS_0 16 16 CMD_BUS_LANE_DIS_1 17 17 CMD_BUS_LANE_DIS_2 18 18 CMD_BUS_LANE_DIS_3 19 19 CMD_BUS_LANE_DIS_4 20 20 CMD_BUS_LANE_DIS_5 21 21 CMD_BUS_LANE_DIS_6 22 22 CMD_BUS_LANE_DIS_7 23 23 ixPB0_PIF_LANE0_OVRD 2 0x1100014 18 0 4294967295 GANGMODE_OVRD_EN_0 0 0 FREQDIV_OVRD_EN_0 1 1 LINKSPEED_OVRD_EN_0 2 2 TWOSYMENABLE_OVRD_EN_0 3 3 TXPWR_OVRD_EN_0 4 4 TXPGENABLE_OVRD_EN_0 5 5 RXPWR_OVRD_EN_0 6 6 RXPGENABLE_OVRD_EN_0 7 7 ELECIDLEDETEN_OVRD_EN_0 8 8 ENABLEFOM_OVRD_EN_0 9 9 REQUESTFOM_OVRD_EN_0 10 10 RESPONSEMODE_OVRD_EN_0 11 11 REQUESTTRK_OVRD_EN_0 12 12 REQUESTTRN_OVRD_EN_0 13 13 COEFFICIENTID_OVRD_EN_0 14 14 COEFFICIENT_OVRD_EN_0 15 15 CDREN_OVRD_EN_0 16 16 CDREN_OVRD_VAL_0 17 17 ixPB0_PIF_LANE0_OVRD2 2 0x1100015 16 0 4294967295 GANGMODE_0 0 2 FREQDIV_0 3 4 LINKSPEED_0 5 6 TWOSYMENABLE_0 7 7 TXPWR_0 8 10 TXPGENABLE_0 11 12 RXPWR_0 13 15 RXPGENABLE_0 16 17 ELECIDLEDETEN_0 18 18 ENABLEFOM_0 19 19 REQUESTFOM_0 20 20 RESPONSEMODE_0 21 21 REQUESTTRK_0 22 22 REQUESTTRN_0 23 23 COEFFICIENTID_0 24 25 COEFFICIENT_0 26 31 ixPB0_PIF_LANE1_OVRD 2 0x1100016 18 0 4294967295 GANGMODE_OVRD_EN_1 0 0 FREQDIV_OVRD_EN_1 1 1 LINKSPEED_OVRD_EN_1 2 2 TWOSYMENABLE_OVRD_EN_1 3 3 TXPWR_OVRD_EN_1 4 4 TXPGENABLE_OVRD_EN_1 5 5 RXPWR_OVRD_EN_1 6 6 RXPGENABLE_OVRD_EN_1 7 7 ELECIDLEDETEN_OVRD_EN_1 8 8 ENABLEFOM_OVRD_EN_1 9 9 REQUESTFOM_OVRD_EN_1 10 10 RESPONSEMODE_OVRD_EN_1 11 11 REQUESTTRK_OVRD_EN_1 12 12 REQUESTTRN_OVRD_EN_1 13 13 COEFFICIENTID_OVRD_EN_1 14 14 COEFFICIENT_OVRD_EN_1 15 15 CDREN_OVRD_EN_1 16 16 CDREN_OVRD_VAL_1 17 17 ixPB0_PIF_LANE1_OVRD2 2 0x1100017 16 0 4294967295 GANGMODE_1 0 2 FREQDIV_1 3 4 LINKSPEED_1 5 6 TWOSYMENABLE_1 7 7 TXPWR_1 8 10 TXPGENABLE_1 11 12 RXPWR_1 13 15 RXPGENABLE_1 16 17 ELECIDLEDETEN_1 18 18 ENABLEFOM_1 19 19 REQUESTFOM_1 20 20 RESPONSEMODE_1 21 21 REQUESTTRK_1 22 22 REQUESTTRN_1 23 23 COEFFICIENTID_1 24 25 COEFFICIENT_1 26 31 ixPB0_PIF_LANE2_OVRD 2 0x1100018 18 0 4294967295 GANGMODE_OVRD_EN_2 0 0 FREQDIV_OVRD_EN_2 1 1 LINKSPEED_OVRD_EN_2 2 2 TWOSYMENABLE_OVRD_EN_2 3 3 TXPWR_OVRD_EN_2 4 4 TXPGENABLE_OVRD_EN_2 5 5 RXPWR_OVRD_EN_2 6 6 RXPGENABLE_OVRD_EN_2 7 7 ELECIDLEDETEN_OVRD_EN_2 8 8 ENABLEFOM_OVRD_EN_2 9 9 REQUESTFOM_OVRD_EN_2 10 10 RESPONSEMODE_OVRD_EN_2 11 11 REQUESTTRK_OVRD_EN_2 12 12 REQUESTTRN_OVRD_EN_2 13 13 COEFFICIENTID_OVRD_EN_2 14 14 COEFFICIENT_OVRD_EN_2 15 15 CDREN_OVRD_EN_2 16 16 CDREN_OVRD_VAL_2 17 17 ixPB0_PIF_LANE2_OVRD2 2 0x1100019 16 0 4294967295 GANGMODE_2 0 2 FREQDIV_2 3 4 LINKSPEED_2 5 6 TWOSYMENABLE_2 7 7 TXPWR_2 8 10 TXPGENABLE_2 11 12 RXPWR_2 13 15 RXPGENABLE_2 16 17 ELECIDLEDETEN_2 18 18 ENABLEFOM_2 19 19 REQUESTFOM_2 20 20 RESPONSEMODE_2 21 21 REQUESTTRK_2 22 22 REQUESTTRN_2 23 23 COEFFICIENTID_2 24 25 COEFFICIENT_2 26 31 ixPB0_PIF_LANE3_OVRD 2 0x110001a 18 0 4294967295 GANGMODE_OVRD_EN_3 0 0 FREQDIV_OVRD_EN_3 1 1 LINKSPEED_OVRD_EN_3 2 2 TWOSYMENABLE_OVRD_EN_3 3 3 TXPWR_OVRD_EN_3 4 4 TXPGENABLE_OVRD_EN_3 5 5 RXPWR_OVRD_EN_3 6 6 RXPGENABLE_OVRD_EN_3 7 7 ELECIDLEDETEN_OVRD_EN_3 8 8 ENABLEFOM_OVRD_EN_3 9 9 REQUESTFOM_OVRD_EN_3 10 10 RESPONSEMODE_OVRD_EN_3 11 11 REQUESTTRK_OVRD_EN_3 12 12 REQUESTTRN_OVRD_EN_3 13 13 COEFFICIENTID_OVRD_EN_3 14 14 COEFFICIENT_OVRD_EN_3 15 15 CDREN_OVRD_EN_3 16 16 CDREN_OVRD_VAL_3 17 17 ixPB0_PIF_LANE3_OVRD2 2 0x110001b 16 0 4294967295 GANGMODE_3 0 2 FREQDIV_3 3 4 LINKSPEED_3 5 6 TWOSYMENABLE_3 7 7 TXPWR_3 8 10 TXPGENABLE_3 11 12 RXPWR_3 13 15 RXPGENABLE_3 16 17 ELECIDLEDETEN_3 18 18 ENABLEFOM_3 19 19 REQUESTFOM_3 20 20 RESPONSEMODE_3 21 21 REQUESTTRK_3 22 22 REQUESTTRN_3 23 23 COEFFICIENTID_3 24 25 COEFFICIENT_3 26 31 ixPB0_PIF_LANE4_OVRD 2 0x110001c 18 0 4294967295 GANGMODE_OVRD_EN_4 0 0 FREQDIV_OVRD_EN_4 1 1 LINKSPEED_OVRD_EN_4 2 2 TWOSYMENABLE_OVRD_EN_4 3 3 TXPWR_OVRD_EN_4 4 4 TXPGENABLE_OVRD_EN_4 5 5 RXPWR_OVRD_EN_4 6 6 RXPGENABLE_OVRD_EN_4 7 7 ELECIDLEDETEN_OVRD_EN_4 8 8 ENABLEFOM_OVRD_EN_4 9 9 REQUESTFOM_OVRD_EN_4 10 10 RESPONSEMODE_OVRD_EN_4 11 11 REQUESTTRK_OVRD_EN_4 12 12 REQUESTTRN_OVRD_EN_4 13 13 COEFFICIENTID_OVRD_EN_4 14 14 COEFFICIENT_OVRD_EN_4 15 15 CDREN_OVRD_EN_4 16 16 CDREN_OVRD_VAL_4 17 17 ixPB0_PIF_LANE4_OVRD2 2 0x110001d 16 0 4294967295 GANGMODE_4 0 2 FREQDIV_4 3 4 LINKSPEED_4 5 6 TWOSYMENABLE_4 7 7 TXPWR_4 8 10 TXPGENABLE_4 11 12 RXPWR_4 13 15 RXPGENABLE_4 16 17 ELECIDLEDETEN_4 18 18 ENABLEFOM_4 19 19 REQUESTFOM_4 20 20 RESPONSEMODE_4 21 21 REQUESTTRK_4 22 22 REQUESTTRN_4 23 23 COEFFICIENTID_4 24 25 COEFFICIENT_4 26 31 ixPB0_PIF_LANE5_OVRD 2 0x110001e 18 0 4294967295 GANGMODE_OVRD_EN_5 0 0 FREQDIV_OVRD_EN_5 1 1 LINKSPEED_OVRD_EN_5 2 2 TWOSYMENABLE_OVRD_EN_5 3 3 TXPWR_OVRD_EN_5 4 4 TXPGENABLE_OVRD_EN_5 5 5 RXPWR_OVRD_EN_5 6 6 RXPGENABLE_OVRD_EN_5 7 7 ELECIDLEDETEN_OVRD_EN_5 8 8 ENABLEFOM_OVRD_EN_5 9 9 REQUESTFOM_OVRD_EN_5 10 10 RESPONSEMODE_OVRD_EN_5 11 11 REQUESTTRK_OVRD_EN_5 12 12 REQUESTTRN_OVRD_EN_5 13 13 COEFFICIENTID_OVRD_EN_5 14 14 COEFFICIENT_OVRD_EN_5 15 15 CDREN_OVRD_EN_5 16 16 CDREN_OVRD_VAL_5 17 17 ixPB0_PIF_LANE5_OVRD2 2 0x110001f 16 0 4294967295 GANGMODE_5 0 2 FREQDIV_5 3 4 LINKSPEED_5 5 6 TWOSYMENABLE_5 7 7 TXPWR_5 8 10 TXPGENABLE_5 11 12 RXPWR_5 13 15 RXPGENABLE_5 16 17 ELECIDLEDETEN_5 18 18 ENABLEFOM_5 19 19 REQUESTFOM_5 20 20 RESPONSEMODE_5 21 21 REQUESTTRK_5 22 22 REQUESTTRN_5 23 23 COEFFICIENTID_5 24 25 COEFFICIENT_5 26 31 ixPB0_PIF_LANE6_OVRD 2 0x1100020 18 0 4294967295 GANGMODE_OVRD_EN_6 0 0 FREQDIV_OVRD_EN_6 1 1 LINKSPEED_OVRD_EN_6 2 2 TWOSYMENABLE_OVRD_EN_6 3 3 TXPWR_OVRD_EN_6 4 4 TXPGENABLE_OVRD_EN_6 5 5 RXPWR_OVRD_EN_6 6 6 RXPGENABLE_OVRD_EN_6 7 7 ELECIDLEDETEN_OVRD_EN_6 8 8 ENABLEFOM_OVRD_EN_6 9 9 REQUESTFOM_OVRD_EN_6 10 10 RESPONSEMODE_OVRD_EN_6 11 11 REQUESTTRK_OVRD_EN_6 12 12 REQUESTTRN_OVRD_EN_6 13 13 COEFFICIENTID_OVRD_EN_6 14 14 COEFFICIENT_OVRD_EN_6 15 15 CDREN_OVRD_EN_6 16 16 CDREN_OVRD_VAL_6 17 17 ixPB0_PIF_LANE6_OVRD2 2 0x1100021 16 0 4294967295 GANGMODE_6 0 2 FREQDIV_6 3 4 LINKSPEED_6 5 6 TWOSYMENABLE_6 7 7 TXPWR_6 8 10 TXPGENABLE_6 11 12 RXPWR_6 13 15 RXPGENABLE_6 16 17 ELECIDLEDETEN_6 18 18 ENABLEFOM_6 19 19 REQUESTFOM_6 20 20 RESPONSEMODE_6 21 21 REQUESTTRK_6 22 22 REQUESTTRN_6 23 23 COEFFICIENTID_6 24 25 COEFFICIENT_6 26 31 ixPB0_PIF_LANE7_OVRD 2 0x1100022 18 0 4294967295 GANGMODE_OVRD_EN_7 0 0 FREQDIV_OVRD_EN_7 1 1 LINKSPEED_OVRD_EN_7 2 2 TWOSYMENABLE_OVRD_EN_7 3 3 TXPWR_OVRD_EN_7 4 4 TXPGENABLE_OVRD_EN_7 5 5 RXPWR_OVRD_EN_7 6 6 RXPGENABLE_OVRD_EN_7 7 7 ELECIDLEDETEN_OVRD_EN_7 8 8 ENABLEFOM_OVRD_EN_7 9 9 REQUESTFOM_OVRD_EN_7 10 10 RESPONSEMODE_OVRD_EN_7 11 11 REQUESTTRK_OVRD_EN_7 12 12 REQUESTTRN_OVRD_EN_7 13 13 COEFFICIENTID_OVRD_EN_7 14 14 COEFFICIENT_OVRD_EN_7 15 15 CDREN_OVRD_EN_7 16 16 CDREN_OVRD_VAL_7 17 17 ixPB0_PIF_LANE7_OVRD2 2 0x1100023 16 0 4294967295 GANGMODE_7 0 2 FREQDIV_7 3 4 LINKSPEED_7 5 6 TWOSYMENABLE_7 7 7 TXPWR_7 8 10 TXPGENABLE_7 11 12 RXPWR_7 13 15 RXPGENABLE_7 16 17 ELECIDLEDETEN_7 18 18 ENABLEFOM_7 19 19 REQUESTFOM_7 20 20 RESPONSEMODE_7 21 21 REQUESTTRK_7 22 22 REQUESTTRN_7 23 23 COEFFICIENTID_7 24 25 COEFFICIENT_7 26 31 ixPB1_PIF_SCRATCH 2 0x2100001 1 0 4294967295 PIF_SCRATCH 0 31 ixPB1_PIF_HW_DEBUG 2 0x2100002 16 0 4294967295 HW_00_DEBUG 0 0 HW_01_DEBUG 1 1 HW_02_DEBUG 2 2 HW_03_DEBUG 3 3 HW_04_DEBUG 4 4 HW_05_DEBUG 5 5 HW_06_DEBUG 6 6 HW_07_DEBUG 7 7 HW_08_DEBUG 8 8 HW_09_DEBUG 9 9 HW_10_DEBUG 10 10 HW_11_DEBUG 11 11 HW_12_DEBUG 12 12 HW_13_DEBUG 13 13 HW_14_DEBUG 14 14 HW_15_DEBUG 15 15 ixPB1_PIF_STRAP_0 2 0x2100003 14 0 4294967295 STRAP_TX_RDY_XTND_DIS 1 1 STRAP_RX_RDY_XTND_DIS 2 2 STRAP_TX_STATUS_XTND_DIS 3 3 STRAP_RX_STATUS_XTND_DIS 4 4 STRAP_FORCE_OWN_MSTR 5 5 STRAP_PIF_CDR_EN_MODE 6 7 STRAP_RX_EI_FILTER 8 9 STRAP_RX_DIS_HLD_EIE_IN_PS1 10 10 STRAP_RX_DIS_HLD_EIE_IN_PS2 11 11 STRAP_PIF_BIT_12 12 12 STRAP_PIF_BIT_13 13 13 STRAP_PIF_BIT_14 14 14 STRAP_PIF_BIT_15 15 15 STRAP_PIF_BIT_16 16 16 ixPB1_PIF_CTRL 2 0x2100004 13 0 4294967295 PIF_PLL_PWRDN_EN 0 0 DTM_FORCE_FREQDIV_X1 1 1 PIF_PLL_HNDSHK_EARLY_ABORT 2 2 PIF_PLL_PWRDN_EARLY_EXIT 3 3 PHY_RST_PWROK_VDD 4 4 PIF_PLL_STATUS 6 7 PIF_PLL_DEGRADE_OFF_VOTE 8 8 PIF_PLL_UNUSED_OFF_VOTE 9 9 PIF_PLL_DEGRADE_S2_VOTE 10 10 PIF_PG_EXIT_MODE 11 11 PIF_DEGRADE_PWR_PLL_MODE 12 12 PIF_LANEUNUSED_AFFECT_GANG 13 13 PIF_PG_ABORT_DISABLE 14 14 ixPB1_PIF_TX_CTRL 2 0x2100008 11 0 4294967295 TXPWR_IN_S2 0 2 TXPWR_IN_SPDCHNG 3 5 TXPWR_IN_OFF 6 8 TXPWR_IN_DEGRADE 9 11 TXPWR_IN_UNUSED 12 14 TXPWR_IN_INIT 15 17 TXPWR_IN_PLL_OFF 18 20 TXPWR_IN_DEGRADE_MODE 21 21 TXPWR_IN_UNUSED_MODE 22 22 TXPWR_GATING_IN_L1 23 23 TXPWR_GATING_IN_UNUSED 24 24 ixPB1_PIF_TX_CTRL2 2 0x2100009 13 0 4294967295 TX_RDY_DASRT_COUNT 0 2 TX_STATUS_DASRT_COUNT 3 5 TXPHYSTATUS_DELAY 6 8 TX_L1_PG_PHY_STATUS_MODE 9 9 TX_OFF_PG_PHY_STATUS_MODE 10 10 TX_HIGH_IMP_STAG_MP 16 16 TX_HIGH_IMP_STAG_MODE 17 18 TX_FORCE_DATA_VALID 21 21 TX_L0_TO_HIZ_DLY 22 24 TX_FIFO_INIT_UPCONFIG 25 25 TX_HIZ_TO_L0_DLY 26 28 TX_LINKSPEED_ACK_IN_S2 29 29 TX_DELAY_FIFO_INIT_IN_S1 30 30 ixPB1_PIF_RX_CTRL 2 0x210000a 13 0 4294967295 RXPWR_IN_S2 0 2 RXPWR_IN_SPDCHNG 3 5 RXPWR_IN_OFF 6 8 RXPWR_IN_DEGRADE 9 11 RXPWR_IN_UNUSED 12 14 RXPWR_IN_INIT 15 17 RXPWR_IN_PLL_OFF 18 20 RXPWR_IN_DEGRADE_MODE 21 21 RXPWR_IN_UNUSED_MODE 22 22 RXPWR_GATING_IN_L1 23 23 RXPWR_GATING_IN_UNUSED 24 24 RX_HLD_EIE_COUNT 25 25 RX_EI_DET_IN_PS2_DEGRADE 26 26 ixPB1_PIF_RX_CTRL2 2 0x210000b 12 0 4294967295 RX_RDY_DASRT_COUNT 0 2 RX_STATUS_DASRT_COUNT 3 5 RXPHYSTATUS_DELAY 6 8 RX_L1_PG_PHY_STATUS_MODE 9 9 RX_OFF_PG_PHY_STATUS_MODE 10 10 FORCE_CDREN_IN_L0S 16 16 EI_DET_CYCLE_MODE 17 18 EI_DET_ON_TIME 19 20 EI_DET_OFF_TIME 21 23 EI_DET_CYCLE_DIS_IN_PS1 24 24 RX_CDR_XTND_MODE 25 26 RX_L0S_TO_L0_DETECT_EI 27 27 ixPB1_PIF_GLB_OVRD 2 0x210000c 9 0 4294967295 RXDETECT_OVERRIDE_VAL_0 0 0 RXDETECT_OVERRIDE_VAL_1 1 1 RXDETECT_OVERRIDE_VAL_2 2 2 RXDETECT_OVERRIDE_VAL_3 3 3 RXDETECT_OVERRIDE_VAL_4 4 4 RXDETECT_OVERRIDE_VAL_5 5 5 RXDETECT_OVERRIDE_VAL_6 6 6 RXDETECT_OVERRIDE_VAL_7 7 7 RXDETECT_OVERRIDE_EN 16 16 ixPB1_PIF_GLB_OVRD2 2 0x210000d 15 0 4294967295 X2_LANE_1_0_OVRD 0 0 X2_LANE_3_2_OVRD 1 1 X2_LANE_5_4_OVRD 2 2 X2_LANE_7_6_OVRD 3 3 X2_LANE_9_8_OVRD 4 4 X2_LANE_11_10_OVRD 5 5 X2_LANE_13_12_OVRD 6 6 X2_LANE_15_14_OVRD 7 7 X4_LANE_3_0_OVRD 8 8 X4_LANE_7_4_OVRD 9 9 X4_LANE_11_8_OVRD 10 10 X4_LANE_15_12_OVRD 11 11 X8_LANE_7_0_OVRD 16 16 X8_LANE_15_8_OVRD 17 17 X16_LANE_15_0_OVRD 20 20 ixPB1_PIF_BIF_CMD_STATUS 2 0x2100010 32 0 4294967295 TXPHYSTATUS_0 0 0 TXPHYSTATUS_1 1 1 TXPHYSTATUS_2 2 2 TXPHYSTATUS_3 3 3 TXPHYSTATUS_4 4 4 TXPHYSTATUS_5 5 5 TXPHYSTATUS_6 6 6 TXPHYSTATUS_7 7 7 RXPHYSTATUS_0 8 8 RXPHYSTATUS_1 9 9 RXPHYSTATUS_2 10 10 RXPHYSTATUS_3 11 11 RXPHYSTATUS_4 12 12 RXPHYSTATUS_5 13 13 RXPHYSTATUS_6 14 14 RXPHYSTATUS_7 15 15 BPHY_CORE_TX_RDY_0 16 16 BPHY_CORE_TX_RDY_1 17 17 BPHY_CORE_TX_RDY_2 18 18 BPHY_CORE_TX_RDY_3 19 19 BPHY_CORE_TX_RDY_4 20 20 BPHY_CORE_TX_RDY_5 21 21 BPHY_CORE_TX_RDY_6 22 22 BPHY_CORE_TX_RDY_7 23 23 BPHY_CORE_RX_RDY_0 24 24 BPHY_CORE_RX_RDY_1 25 25 BPHY_CORE_RX_RDY_2 26 26 BPHY_CORE_RX_RDY_3 27 27 BPHY_CORE_RX_RDY_4 28 28 BPHY_CORE_RX_RDY_5 29 29 BPHY_CORE_RX_RDY_6 30 30 BPHY_CORE_RX_RDY_7 31 31 ixPB1_PIF_CMD_BUS_CTRL 2 0x2100011 7 0 4294967295 CMD_BUS_SCHL_MODE 0 1 CMD_BUS_STAG_MODE 2 3 CMD_BUS_STAG_DIS 4 4 CMD_BUS_SCH_REQ_MODE 5 6 CMD_BUS_IGNR_PEND_PWR 7 7 SEND_GANGED_MODE_UPDATE_FOR_OFFPG_LANES 8 8 CMD_BUS_IGNR_PWR_NOT_ON 9 9 ixPB1_PIF_CMD_BUS_GLB_OVRD 2 0x2100013 15 0 4294967295 TXMARG_OVRD_EN 0 0 DEEMPH_OVRD_EN 1 1 PLLFREQ_OVRD_EN 2 2 TXMARG 3 5 DEEMPH 6 6 PLLFREQ 7 8 RESPONSEMODE_PIF_OVRD 9 9 CMD_BUS_LANE_DIS_0 16 16 CMD_BUS_LANE_DIS_1 17 17 CMD_BUS_LANE_DIS_2 18 18 CMD_BUS_LANE_DIS_3 19 19 CMD_BUS_LANE_DIS_4 20 20 CMD_BUS_LANE_DIS_5 21 21 CMD_BUS_LANE_DIS_6 22 22 CMD_BUS_LANE_DIS_7 23 23 ixPB1_PIF_LANE0_OVRD 2 0x2100014 18 0 4294967295 GANGMODE_OVRD_EN_0 0 0 FREQDIV_OVRD_EN_0 1 1 LINKSPEED_OVRD_EN_0 2 2 TWOSYMENABLE_OVRD_EN_0 3 3 TXPWR_OVRD_EN_0 4 4 TXPGENABLE_OVRD_EN_0 5 5 RXPWR_OVRD_EN_0 6 6 RXPGENABLE_OVRD_EN_0 7 7 ELECIDLEDETEN_OVRD_EN_0 8 8 ENABLEFOM_OVRD_EN_0 9 9 REQUESTFOM_OVRD_EN_0 10 10 RESPONSEMODE_OVRD_EN_0 11 11 REQUESTTRK_OVRD_EN_0 12 12 REQUESTTRN_OVRD_EN_0 13 13 COEFFICIENTID_OVRD_EN_0 14 14 COEFFICIENT_OVRD_EN_0 15 15 CDREN_OVRD_EN_0 16 16 CDREN_OVRD_VAL_0 17 17 ixPB1_PIF_LANE0_OVRD2 2 0x2100015 16 0 4294967295 GANGMODE_0 0 2 FREQDIV_0 3 4 LINKSPEED_0 5 6 TWOSYMENABLE_0 7 7 TXPWR_0 8 10 TXPGENABLE_0 11 12 RXPWR_0 13 15 RXPGENABLE_0 16 17 ELECIDLEDETEN_0 18 18 ENABLEFOM_0 19 19 REQUESTFOM_0 20 20 RESPONSEMODE_0 21 21 REQUESTTRK_0 22 22 REQUESTTRN_0 23 23 COEFFICIENTID_0 24 25 COEFFICIENT_0 26 31 ixPB1_PIF_LANE1_OVRD 2 0x2100016 18 0 4294967295 GANGMODE_OVRD_EN_1 0 0 FREQDIV_OVRD_EN_1 1 1 LINKSPEED_OVRD_EN_1 2 2 TWOSYMENABLE_OVRD_EN_1 3 3 TXPWR_OVRD_EN_1 4 4 TXPGENABLE_OVRD_EN_1 5 5 RXPWR_OVRD_EN_1 6 6 RXPGENABLE_OVRD_EN_1 7 7 ELECIDLEDETEN_OVRD_EN_1 8 8 ENABLEFOM_OVRD_EN_1 9 9 REQUESTFOM_OVRD_EN_1 10 10 RESPONSEMODE_OVRD_EN_1 11 11 REQUESTTRK_OVRD_EN_1 12 12 REQUESTTRN_OVRD_EN_1 13 13 COEFFICIENTID_OVRD_EN_1 14 14 COEFFICIENT_OVRD_EN_1 15 15 CDREN_OVRD_EN_1 16 16 CDREN_OVRD_VAL_1 17 17 ixPB1_PIF_LANE1_OVRD2 2 0x2100017 16 0 4294967295 GANGMODE_1 0 2 FREQDIV_1 3 4 LINKSPEED_1 5 6 TWOSYMENABLE_1 7 7 TXPWR_1 8 10 TXPGENABLE_1 11 12 RXPWR_1 13 15 RXPGENABLE_1 16 17 ELECIDLEDETEN_1 18 18 ENABLEFOM_1 19 19 REQUESTFOM_1 20 20 RESPONSEMODE_1 21 21 REQUESTTRK_1 22 22 REQUESTTRN_1 23 23 COEFFICIENTID_1 24 25 COEFFICIENT_1 26 31 ixPB1_PIF_LANE2_OVRD 2 0x2100018 18 0 4294967295 GANGMODE_OVRD_EN_2 0 0 FREQDIV_OVRD_EN_2 1 1 LINKSPEED_OVRD_EN_2 2 2 TWOSYMENABLE_OVRD_EN_2 3 3 TXPWR_OVRD_EN_2 4 4 TXPGENABLE_OVRD_EN_2 5 5 RXPWR_OVRD_EN_2 6 6 RXPGENABLE_OVRD_EN_2 7 7 ELECIDLEDETEN_OVRD_EN_2 8 8 ENABLEFOM_OVRD_EN_2 9 9 REQUESTFOM_OVRD_EN_2 10 10 RESPONSEMODE_OVRD_EN_2 11 11 REQUESTTRK_OVRD_EN_2 12 12 REQUESTTRN_OVRD_EN_2 13 13 COEFFICIENTID_OVRD_EN_2 14 14 COEFFICIENT_OVRD_EN_2 15 15 CDREN_OVRD_EN_2 16 16 CDREN_OVRD_VAL_2 17 17 ixPB1_PIF_LANE2_OVRD2 2 0x2100019 16 0 4294967295 GANGMODE_2 0 2 FREQDIV_2 3 4 LINKSPEED_2 5 6 TWOSYMENABLE_2 7 7 TXPWR_2 8 10 TXPGENABLE_2 11 12 RXPWR_2 13 15 RXPGENABLE_2 16 17 ELECIDLEDETEN_2 18 18 ENABLEFOM_2 19 19 REQUESTFOM_2 20 20 RESPONSEMODE_2 21 21 REQUESTTRK_2 22 22 REQUESTTRN_2 23 23 COEFFICIENTID_2 24 25 COEFFICIENT_2 26 31 ixPB1_PIF_LANE3_OVRD 2 0x210001a 18 0 4294967295 GANGMODE_OVRD_EN_3 0 0 FREQDIV_OVRD_EN_3 1 1 LINKSPEED_OVRD_EN_3 2 2 TWOSYMENABLE_OVRD_EN_3 3 3 TXPWR_OVRD_EN_3 4 4 TXPGENABLE_OVRD_EN_3 5 5 RXPWR_OVRD_EN_3 6 6 RXPGENABLE_OVRD_EN_3 7 7 ELECIDLEDETEN_OVRD_EN_3 8 8 ENABLEFOM_OVRD_EN_3 9 9 REQUESTFOM_OVRD_EN_3 10 10 RESPONSEMODE_OVRD_EN_3 11 11 REQUESTTRK_OVRD_EN_3 12 12 REQUESTTRN_OVRD_EN_3 13 13 COEFFICIENTID_OVRD_EN_3 14 14 COEFFICIENT_OVRD_EN_3 15 15 CDREN_OVRD_EN_3 16 16 CDREN_OVRD_VAL_3 17 17 ixPB1_PIF_LANE3_OVRD2 2 0x210001b 16 0 4294967295 GANGMODE_3 0 2 FREQDIV_3 3 4 LINKSPEED_3 5 6 TWOSYMENABLE_3 7 7 TXPWR_3 8 10 TXPGENABLE_3 11 12 RXPWR_3 13 15 RXPGENABLE_3 16 17 ELECIDLEDETEN_3 18 18 ENABLEFOM_3 19 19 REQUESTFOM_3 20 20 RESPONSEMODE_3 21 21 REQUESTTRK_3 22 22 REQUESTTRN_3 23 23 COEFFICIENTID_3 24 25 COEFFICIENT_3 26 31 ixPB1_PIF_LANE4_OVRD 2 0x210001c 18 0 4294967295 GANGMODE_OVRD_EN_4 0 0 FREQDIV_OVRD_EN_4 1 1 LINKSPEED_OVRD_EN_4 2 2 TWOSYMENABLE_OVRD_EN_4 3 3 TXPWR_OVRD_EN_4 4 4 TXPGENABLE_OVRD_EN_4 5 5 RXPWR_OVRD_EN_4 6 6 RXPGENABLE_OVRD_EN_4 7 7 ELECIDLEDETEN_OVRD_EN_4 8 8 ENABLEFOM_OVRD_EN_4 9 9 REQUESTFOM_OVRD_EN_4 10 10 RESPONSEMODE_OVRD_EN_4 11 11 REQUESTTRK_OVRD_EN_4 12 12 REQUESTTRN_OVRD_EN_4 13 13 COEFFICIENTID_OVRD_EN_4 14 14 COEFFICIENT_OVRD_EN_4 15 15 CDREN_OVRD_EN_4 16 16 CDREN_OVRD_VAL_4 17 17 ixPB1_PIF_LANE4_OVRD2 2 0x210001d 16 0 4294967295 GANGMODE_4 0 2 FREQDIV_4 3 4 LINKSPEED_4 5 6 TWOSYMENABLE_4 7 7 TXPWR_4 8 10 TXPGENABLE_4 11 12 RXPWR_4 13 15 RXPGENABLE_4 16 17 ELECIDLEDETEN_4 18 18 ENABLEFOM_4 19 19 REQUESTFOM_4 20 20 RESPONSEMODE_4 21 21 REQUESTTRK_4 22 22 REQUESTTRN_4 23 23 COEFFICIENTID_4 24 25 COEFFICIENT_4 26 31 ixPB1_PIF_LANE5_OVRD 2 0x210001e 18 0 4294967295 GANGMODE_OVRD_EN_5 0 0 FREQDIV_OVRD_EN_5 1 1 LINKSPEED_OVRD_EN_5 2 2 TWOSYMENABLE_OVRD_EN_5 3 3 TXPWR_OVRD_EN_5 4 4 TXPGENABLE_OVRD_EN_5 5 5 RXPWR_OVRD_EN_5 6 6 RXPGENABLE_OVRD_EN_5 7 7 ELECIDLEDETEN_OVRD_EN_5 8 8 ENABLEFOM_OVRD_EN_5 9 9 REQUESTFOM_OVRD_EN_5 10 10 RESPONSEMODE_OVRD_EN_5 11 11 REQUESTTRK_OVRD_EN_5 12 12 REQUESTTRN_OVRD_EN_5 13 13 COEFFICIENTID_OVRD_EN_5 14 14 COEFFICIENT_OVRD_EN_5 15 15 CDREN_OVRD_EN_5 16 16 CDREN_OVRD_VAL_5 17 17 ixPB1_PIF_LANE5_OVRD2 2 0x210001f 16 0 4294967295 GANGMODE_5 0 2 FREQDIV_5 3 4 LINKSPEED_5 5 6 TWOSYMENABLE_5 7 7 TXPWR_5 8 10 TXPGENABLE_5 11 12 RXPWR_5 13 15 RXPGENABLE_5 16 17 ELECIDLEDETEN_5 18 18 ENABLEFOM_5 19 19 REQUESTFOM_5 20 20 RESPONSEMODE_5 21 21 REQUESTTRK_5 22 22 REQUESTTRN_5 23 23 COEFFICIENTID_5 24 25 COEFFICIENT_5 26 31 ixPB1_PIF_LANE6_OVRD 2 0x2100020 18 0 4294967295 GANGMODE_OVRD_EN_6 0 0 FREQDIV_OVRD_EN_6 1 1 LINKSPEED_OVRD_EN_6 2 2 TWOSYMENABLE_OVRD_EN_6 3 3 TXPWR_OVRD_EN_6 4 4 TXPGENABLE_OVRD_EN_6 5 5 RXPWR_OVRD_EN_6 6 6 RXPGENABLE_OVRD_EN_6 7 7 ELECIDLEDETEN_OVRD_EN_6 8 8 ENABLEFOM_OVRD_EN_6 9 9 REQUESTFOM_OVRD_EN_6 10 10 RESPONSEMODE_OVRD_EN_6 11 11 REQUESTTRK_OVRD_EN_6 12 12 REQUESTTRN_OVRD_EN_6 13 13 COEFFICIENTID_OVRD_EN_6 14 14 COEFFICIENT_OVRD_EN_6 15 15 CDREN_OVRD_EN_6 16 16 CDREN_OVRD_VAL_6 17 17 ixPB1_PIF_LANE6_OVRD2 2 0x2100021 16 0 4294967295 GANGMODE_6 0 2 FREQDIV_6 3 4 LINKSPEED_6 5 6 TWOSYMENABLE_6 7 7 TXPWR_6 8 10 TXPGENABLE_6 11 12 RXPWR_6 13 15 RXPGENABLE_6 16 17 ELECIDLEDETEN_6 18 18 ENABLEFOM_6 19 19 REQUESTFOM_6 20 20 RESPONSEMODE_6 21 21 REQUESTTRK_6 22 22 REQUESTTRN_6 23 23 COEFFICIENTID_6 24 25 COEFFICIENT_6 26 31 ixPB1_PIF_LANE7_OVRD 2 0x2100022 18 0 4294967295 GANGMODE_OVRD_EN_7 0 0 FREQDIV_OVRD_EN_7 1 1 LINKSPEED_OVRD_EN_7 2 2 TWOSYMENABLE_OVRD_EN_7 3 3 TXPWR_OVRD_EN_7 4 4 TXPGENABLE_OVRD_EN_7 5 5 RXPWR_OVRD_EN_7 6 6 RXPGENABLE_OVRD_EN_7 7 7 ELECIDLEDETEN_OVRD_EN_7 8 8 ENABLEFOM_OVRD_EN_7 9 9 REQUESTFOM_OVRD_EN_7 10 10 RESPONSEMODE_OVRD_EN_7 11 11 REQUESTTRK_OVRD_EN_7 12 12 REQUESTTRN_OVRD_EN_7 13 13 COEFFICIENTID_OVRD_EN_7 14 14 COEFFICIENT_OVRD_EN_7 15 15 CDREN_OVRD_EN_7 16 16 CDREN_OVRD_VAL_7 17 17 ixPB1_PIF_LANE7_OVRD2 2 0x2100023 16 0 4294967295 GANGMODE_7 0 2 FREQDIV_7 3 4 LINKSPEED_7 5 6 TWOSYMENABLE_7 7 7 TXPWR_7 8 10 TXPGENABLE_7 11 12 RXPWR_7 13 15 RXPGENABLE_7 16 17 ELECIDLEDETEN_7 18 18 ENABLEFOM_7 19 19 REQUESTFOM_7 20 20 RESPONSEMODE_7 21 21 REQUESTTRK_7 22 22 REQUESTTRN_7 23 23 COEFFICIENTID_7 24 25 COEFFICIENT_7 26 31 ixPCIEP_RESERVED 2 0x10010000 1 0 4294967295 PCIEP_RESERVED 0 31 ixPCIEP_SCRATCH 2 0x10010001 1 0 4294967295 PCIEP_SCRATCH 0 31 ixPCIEP_HW_DEBUG 2 0x10010002 16 0 4294967295 HW_00_DEBUG 0 0 HW_01_DEBUG 1 1 HW_02_DEBUG 2 2 HW_03_DEBUG 3 3 HW_04_DEBUG 4 4 HW_05_DEBUG 5 5 HW_06_DEBUG 6 6 HW_07_DEBUG 7 7 HW_08_DEBUG 8 8 HW_09_DEBUG 9 9 HW_10_DEBUG 10 10 HW_11_DEBUG 11 11 HW_12_DEBUG 12 12 HW_13_DEBUG 13 13 HW_14_DEBUG 14 14 HW_15_DEBUG 15 15 ixPCIEP_PORT_CNTL 2 0x10010010 10 0 4294967295 SLV_PORT_REQ_EN 0 0 CI_SNOOP_OVERRIDE 1 1 HOTPLUG_MSG_EN 2 2 NATIVE_PME_EN 3 3 PWR_FAULT_EN 4 4 PMI_BM_DIS 5 5 SEQNUM_DEBUG_MODE 6 6 CI_SLV_CPL_STATIC_ALLOC_LIMIT_S 8 14 CI_MAX_CPL_PAYLOAD_SIZE_MODE 16 17 CI_PRIV_MAX_CPL_PAYLOAD_SIZE 18 20 ixPCIE_TX_CNTL 2 0x10010020 11 0 4294967295 TX_SNR_OVERRIDE 10 11 TX_RO_OVERRIDE 12 13 TX_PACK_PACKET_DIS 14 14 TX_FLUSH_TLP_DIS 15 15 TX_CPL_PASS_P 20 20 TX_NP_PASS_P 21 21 TX_CLEAR_EXTRA_PM_REQS 22 22 TX_FC_UPDATE_TIMEOUT_DIS 23 23 TX_F0_TPH_DIS 24 24 TX_F1_TPH_DIS 25 25 TX_F2_TPH_DIS 26 26 ixPCIE_TX_REQUESTER_ID 2 0x10010021 3 0 4294967295 TX_REQUESTER_ID_FUNCTION 0 2 TX_REQUESTER_ID_DEVICE 3 7 TX_REQUESTER_ID_BUS 8 15 ixPCIE_TX_VENDOR_SPECIFIC 2 0x10010022 1 0 4294967295 TX_VENDOR_DATA 0 23 ixPCIE_TX_REQUEST_NUM_CNTL 2 0x10010023 3 0 4294967295 TX_NUM_OUTSTANDING_NP 24 29 TX_NUM_OUTSTANDING_NP_VC1_EN 30 30 TX_NUM_OUTSTANDING_NP_EN 31 31 ixPCIE_TX_SEQ 2 0x10010024 2 0 4294967295 TX_NEXT_TRANSMIT_SEQ 0 11 TX_ACKD_SEQ 16 27 ixPCIE_TX_REPLAY 2 0x10010025 3 0 4294967295 TX_REPLAY_NUM 0 2 TX_REPLAY_TIMER_OVERWRITE 15 15 TX_REPLAY_TIMER 16 31 ixPCIE_TX_ACK_LATENCY_LIMIT 2 0x10010026 2 0 4294967295 TX_ACK_LATENCY_LIMIT 0 11 TX_ACK_LATENCY_LIMIT_OVERWRITE 12 12 ixPCIE_TX_CREDITS_ADVT_P 2 0x10010030 2 0 4294967295 TX_CREDITS_ADVT_PD 0 11 TX_CREDITS_ADVT_PH 16 23 ixPCIE_TX_CREDITS_ADVT_NP 2 0x10010031 2 0 4294967295 TX_CREDITS_ADVT_NPD 0 11 TX_CREDITS_ADVT_NPH 16 23 ixPCIE_TX_CREDITS_ADVT_CPL 2 0x10010032 2 0 4294967295 TX_CREDITS_ADVT_CPLD 0 11 TX_CREDITS_ADVT_CPLH 16 23 ixPCIE_TX_CREDITS_INIT_P 2 0x10010033 2 0 4294967295 TX_CREDITS_INIT_PD 0 11 TX_CREDITS_INIT_PH 16 23 ixPCIE_TX_CREDITS_INIT_NP 2 0x10010034 2 0 4294967295 TX_CREDITS_INIT_NPD 0 11 TX_CREDITS_INIT_NPH 16 23 ixPCIE_TX_CREDITS_INIT_CPL 2 0x10010035 2 0 4294967295 TX_CREDITS_INIT_CPLD 0 11 TX_CREDITS_INIT_CPLH 16 23 ixPCIE_TX_CREDITS_STATUS 2 0x10010036 12 0 4294967295 TX_CREDITS_ERR_PD 0 0 TX_CREDITS_ERR_PH 1 1 TX_CREDITS_ERR_NPD 2 2 TX_CREDITS_ERR_NPH 3 3 TX_CREDITS_ERR_CPLD 4 4 TX_CREDITS_ERR_CPLH 5 5 TX_CREDITS_CUR_STATUS_PD 16 16 TX_CREDITS_CUR_STATUS_PH 17 17 TX_CREDITS_CUR_STATUS_NPD 18 18 TX_CREDITS_CUR_STATUS_NPH 19 19 TX_CREDITS_CUR_STATUS_CPLD 20 20 TX_CREDITS_CUR_STATUS_CPLH 21 21 ixPCIE_TX_CREDITS_FCU_THRESHOLD 2 0x10010037 6 0 4294967295 TX_FCU_THRESHOLD_P_VC0 0 2 TX_FCU_THRESHOLD_NP_VC0 4 6 TX_FCU_THRESHOLD_CPL_VC0 8 10 TX_FCU_THRESHOLD_P_VC1 16 18 TX_FCU_THRESHOLD_NP_VC1 20 22 TX_FCU_THRESHOLD_CPL_VC1 24 26 ixPCIE_P_PORT_LANE_STATUS 2 0x10010050 2 0 4294967295 PORT_LANE_REVERSAL 0 0 PHY_LINK_WIDTH 1 6 ixPCIE_FC_P 2 0x10010060 2 0 4294967295 PD_CREDITS 0 7 PH_CREDITS 8 15 ixPCIE_FC_NP 2 0x10010061 2 0 4294967295 NPD_CREDITS 0 7 NPH_CREDITS 8 15 ixPCIE_FC_CPL 2 0x10010062 2 0 4294967295 CPLD_CREDITS 0 7 CPLH_CREDITS 8 15 ixPCIE_ERR_CNTL 2 0x1001006a 16 0 4294967295 ERR_REPORTING_DIS 0 0 STRAP_FIRST_RCVD_ERR_LOG 1 1 RX_DROP_ECRC_FAILURES 2 2 TX_GENERATE_LCRC_ERR 4 4 RX_GENERATE_LCRC_ERR 5 5 TX_GENERATE_ECRC_ERR 6 6 RX_GENERATE_ECRC_ERR 7 7 AER_HDR_LOG_TIMEOUT 8 10 AER_HDR_LOG_F0_TIMER_EXPIRED 11 11 AER_HDR_LOG_F1_TIMER_EXPIRED 12 12 AER_HDR_LOG_F2_TIMER_EXPIRED 13 13 CI_P_SLV_BUF_RD_HALT_STATUS 14 14 CI_NP_SLV_BUF_RD_HALT_STATUS 15 15 CI_SLV_BUF_HALT_RESET 16 16 SEND_ERR_MSG_IMMEDIATELY 17 17 STRAP_POISONED_ADVISORY_NONFATAL 18 18 ixPCIE_RX_CNTL 2 0x10010070 26 0 4294967295 RX_IGNORE_IO_ERR 0 0 RX_IGNORE_BE_ERR 1 1 RX_IGNORE_MSG_ERR 2 2 RX_IGNORE_CRC_ERR 3 3 RX_IGNORE_CFG_ERR 4 4 RX_IGNORE_CPL_ERR 5 5 RX_IGNORE_EP_ERR 6 6 RX_IGNORE_LEN_MISMATCH_ERR 7 7 RX_IGNORE_MAX_PAYLOAD_ERR 8 8 RX_IGNORE_TC_ERR 9 9 RX_IGNORE_CFG_UR 10 10 RX_IGNORE_IO_UR 11 11 RX_IGNORE_AT_ERR 12 12 RX_NAK_IF_FIFO_FULL 13 13 RX_GEN_ONE_NAK 14 14 RX_FC_INIT_FROM_REG 15 15 RX_RCB_CPL_TIMEOUT 16 18 RX_RCB_CPL_TIMEOUT_MODE 19 19 RX_PCIE_CPL_TIMEOUT_DIS 20 20 RX_IGNORE_SHORTPREFIX_ERR 21 21 RX_IGNORE_MAXPREFIX_ERR 22 22 RX_IGNORE_CPLPREFIX_ERR 23 23 RX_IGNORE_INVALIDPASID_ERR 24 24 RX_IGNORE_NOT_PASID_UR 25 25 RX_TPH_DIS 26 26 RX_RCB_FLR_TIMEOUT_DIS 27 27 ixPCIE_RX_EXPECTED_SEQNUM 2 0x10010071 1 0 4294967295 RX_EXPECTED_SEQNUM 0 11 ixPCIE_RX_VENDOR_SPECIFIC 2 0x10010072 2 0 4294967295 RX_VENDOR_DATA 0 23 RX_VENDOR_STATUS 24 24 ixPCIE_RX_CNTL3 2 0x10010074 5 0 4294967295 RX_IGNORE_RC_TRANSMRDPASID_UR 0 0 RX_IGNORE_RC_TRANSMWRPASID_UR 1 1 RX_IGNORE_RC_PRGRESPMSG_UR 2 2 RX_IGNORE_RC_INVREQ_UR 3 3 RX_IGNORE_RC_INVCPLPASID_UR 4 4 ixPCIE_RX_CREDITS_ALLOCATED_P 2 0x10010080 2 0 4294967295 RX_CREDITS_ALLOCATED_PD 0 11 RX_CREDITS_ALLOCATED_PH 16 23 ixPCIE_RX_CREDITS_ALLOCATED_NP 2 0x10010081 2 0 4294967295 RX_CREDITS_ALLOCATED_NPD 0 11 RX_CREDITS_ALLOCATED_NPH 16 23 ixPCIE_RX_CREDITS_ALLOCATED_CPL 2 0x10010082 2 0 4294967295 RX_CREDITS_ALLOCATED_CPLD 0 11 RX_CREDITS_ALLOCATED_CPLH 16 23 ixPCIEP_ERROR_INJECT_PHYSICAL 2 0x10010083 12 0 4294967295 ERROR_INJECT_PL_LANE_ERR 0 1 ERROR_INJECT_PL_FRAMING_ERR 2 3 ERROR_INJECT_PL_BAD_PARITY_IN_SKP 4 5 ERROR_INJECT_PL_BAD_LFSR_IN_SKP 6 7 ERROR_INJECT_PL_LOOPBACK_UFLOW 8 9 ERROR_INJECT_PL_LOOPBACK_OFLOW 10 11 ERROR_INJECT_PL_DESKEW_ERR 12 13 ERROR_INJECT_PL_8B10B_DISPARITY_ERR 14 15 ERROR_INJECT_PL_8B10B_DECODE_ERR 16 17 ERROR_INJECT_PL_SKP_OS_ERROR 18 19 ERROR_INJECT_PL_INV_OS_IDENTIFIER 20 21 ERROR_INJECT_PL_BAD_SYNC_HEADER 22 23 ixPCIEP_ERROR_INJECT_TRANSACTION 2 0x10010084 10 0 4294967295 ERROR_INJECT_TL_FLOW_CTL_ERR 0 1 ERROR_INJECT_TL_REPLAY_NUM_ROLLOVER 2 3 ERROR_INJECT_TL_BAD_DLLP 4 5 ERROR_INJECT_TL_BAD_TLP 6 7 ERROR_INJECT_TL_UNSUPPORTED_REQ 8 9 ERROR_INJECT_TL_ECRC_ERROR 10 11 ERROR_INJECT_TL_MALFORMED_TLP 12 13 ERROR_INJECT_TL_UNEXPECTED_CMPLT 14 15 ERROR_INJECT_TL_COMPLETER_ABORT 16 17 ERROR_INJECT_TL_COMPLETION_TIMEOUT 18 19 ixPCIEP_SRIOV_PRIV_CTRL 2 0x10010085 2 0 4294967295 RX_SRIOV_VF_MAPPING_MODE 0 1 SRIOV_SAVE_VFS_ON_VFENABLE_CLR 2 3 ixPCIE_LC_CNTL 2 0x100100a0 20 0 4294967295 LC_DONT_ENTER_L23_IN_D0 1 1 LC_RESET_L_IDLE_COUNT_EN 2 2 LC_RESET_LINK 3 3 LC_16X_CLEAR_TX_PIPE 4 7 LC_L0S_INACTIVITY 8 11 LC_L1_INACTIVITY 12 15 LC_PMI_TO_L1_DIS 16 16 LC_INC_N_FTS_EN 17 17 LC_LOOK_FOR_IDLE_IN_L1L23 18 19 LC_FACTOR_IN_EXT_SYNC 20 20 LC_WAIT_FOR_PM_ACK_DIS 21 21 LC_WAKE_FROM_L23 22 22 LC_L1_IMMEDIATE_ACK 23 23 LC_ASPM_TO_L1_DIS 24 24 LC_DELAY_COUNT 25 26 LC_DELAY_L0S_EXIT 27 27 LC_DELAY_L1_EXIT 28 28 LC_EXTEND_WAIT_FOR_EL_IDLE 29 29 LC_ESCAPE_L1L23_EN 30 30 LC_GATE_RCVR_IDLE 31 31 ixPCIE_LC_CNTL2 2 0x100100b1 24 0 4294967295 LC_TIMED_OUT_STATE 0 5 LC_STATE_TIMED_OUT 6 6 LC_LOOK_FOR_BW_REDUCTION 7 7 LC_MORE_TS2_EN 8 8 LC_X12_NEGOTIATION_DIS 9 9 LC_LINK_UP_REVERSAL_EN 10 10 LC_ILLEGAL_STATE 11 11 LC_ILLEGAL_STATE_RESTART_EN 12 12 LC_WAIT_FOR_OTHER_LANES_MODE 13 13 LC_ELEC_IDLE_MODE 14 15 LC_DISABLE_INFERRED_ELEC_IDLE_DET 16 16 LC_ALLOW_PDWN_IN_L1 17 17 LC_ALLOW_PDWN_IN_L23 18 18 LC_DEASSERT_RX_EN_IN_L0S 19 19 LC_BLOCK_EL_IDLE_IN_L0 20 20 LC_RCV_L0_TO_RCV_L0S_DIS 21 21 LC_ASSERT_INACTIVE_DURING_HOLD 22 22 LC_WAIT_FOR_LANES_IN_LW_NEG 23 24 LC_PWR_DOWN_NEG_OFF_LANES 25 25 LC_DISABLE_LOST_SYM_LOCK_ARCS 26 26 LC_LINK_BW_NOTIFICATION_DIS 27 27 LC_PMI_L1_WAIT_FOR_SLV_IDLE 28 28 LC_TEST_TIMER_SEL 29 30 LC_ENABLE_INFERRED_ELEC_IDLE_FOR_PI 31 31 ixPCIE_LC_CNTL3 2 0x100100b5 23 0 4294967295 LC_SELECT_DEEMPHASIS 0 0 LC_SELECT_DEEMPHASIS_CNTL 1 2 LC_RCVD_DEEMPHASIS 3 3 LC_COMP_TO_DETECT 4 4 LC_RESET_TSX_CNT_IN_RLOCK_EN 5 5 LC_AUTO_SPEED_CHANGE_ATTEMPTS_ALLOWED 6 7 LC_AUTO_SPEED_CHANGE_ATTEMPT_FAILED 8 8 LC_CLR_FAILED_AUTO_SPD_CHANGE_CNT 9 9 LC_ENHANCED_HOT_PLUG_EN 10 10 LC_RCVR_DET_EN_OVERRIDE 11 11 LC_EHP_RX_PHY_CMD 12 13 LC_EHP_TX_PHY_CMD 14 15 LC_CHIP_BIF_USB_IDLE_EN 16 16 LC_L1_BLOCK_RECONFIG_EN 17 17 LC_AUTO_DISABLE_SPEED_SUPPORT_EN 18 18 LC_AUTO_DISABLE_SPEED_SUPPORT_MAX_FAIL_SEL 19 20 LC_FAST_L1_ENTRY_EXIT_EN 21 21 LC_RXPHYCMD_INACTIVE_EN_MODE 22 22 LC_DSC_DONT_ENTER_L23_AFTER_PME_ACK 23 23 LC_HW_VOLTAGE_IF_CONTROL 24 25 LC_VOLTAGE_TIMER_SEL 26 29 LC_GO_TO_RECOVERY 30 30 LC_N_EIE_SEL 31 31 ixPCIE_LC_CNTL4 2 0x100100b6 22 0 4294967295 LC_TX_ENABLE_BEHAVIOUR 0 1 LC_DIS_CONTIG_END_SET_CHECK 2 2 LC_DIS_ASPM_L1_IN_SPEED_CHANGE 3 3 LC_BYPASS_EQ 4 4 LC_REDO_EQ 5 5 LC_EXTEND_EIEOS 6 6 LC_IGNORE_PARITY 7 7 LC_EQ_SEARCH_MODE 8 9 LC_DSC_CHECK_COEFFS_IN_RLOCK 10 10 LC_USC_EQ_NOT_REQD 11 11 LC_USC_GO_TO_EQ 12 12 LC_SET_QUIESCE 13 13 LC_QUIESCE_RCVD 14 14 LC_UNEXPECTED_COEFFS_RCVD 15 15 LC_BYPASS_EQ_REQ_PHASE 16 16 LC_FORCE_PRESET_IN_EQ_REQ_PHASE 17 17 LC_FORCE_PRESET_VALUE 18 21 LC_USC_DELAY_DLLPS 22 22 LC_PCIE_TX_FULL_SWING 23 23 LC_EQ_WAIT_FOR_EVAL_DONE 24 24 LC_8GT_SKIP_ORDER_EN 25 25 LC_WAIT_FOR_MORE_TS_IN_RLOCK 26 31 ixPCIE_LC_CNTL5 2 0x100100b7 5 0 4294967295 LC_EQ_FS_0 0 5 LC_EQ_FS_8 6 11 LC_EQ_LF_0 12 17 LC_EQ_LF_8 18 23 LC_DSC_EQ_FS_LF_INVALID_TO_PRESETS 24 24 ixPCIE_LC_CNTL6 2 0x100100bb 3 0 4294967295 LC_SPC_MODE_2P5GT 0 0 LC_SPC_MODE_5GT 2 2 LC_SPC_MODE_8GT 4 4 ixPCIE_LC_BW_CHANGE_CNTL 2 0x100100b2 11 0 4294967295 LC_BW_CHANGE_INT_EN 0 0 LC_HW_INIT_SPEED_CHANGE 1 1 LC_SW_INIT_SPEED_CHANGE 2 2 LC_OTHER_INIT_SPEED_CHANGE 3 3 LC_RELIABILITY_SPEED_CHANGE 4 4 LC_FAILED_SPEED_NEG 5 5 LC_LONG_LW_CHANGE 6 6 LC_SHORT_LW_CHANGE 7 7 LC_LW_CHANGE_OTHER 8 8 LC_LW_CHANGE_FAILED 9 9 LC_LINK_BW_NOTIFICATION_DETECT_MODE 10 10 ixPCIE_LC_TRAINING_CNTL 2 0x100100a1 25 0 4294967295 LC_TRAINING_CNTL 0 3 LC_COMPLIANCE_RECEIVE 4 4 LC_LOOK_FOR_MORE_NON_MATCHING_TS1 5 5 LC_L0S_L1_TRAINING_CNTL_EN 6 6 LC_L1_LONG_WAKE_FIX_EN 7 7 LC_POWER_STATE 8 10 LC_DONT_GO_TO_L0S_IF_L1_ARMED 11 11 LC_INIT_SPD_CHG_WITH_CSR_EN 12 12 LC_DISABLE_TRAINING_BIT_ARCH 13 13 LC_WAIT_FOR_SETS_IN_RCFG 14 14 LC_HOT_RESET_QUICK_EXIT_EN 15 15 LC_EXTEND_WAIT_FOR_SKP 16 16 LC_AUTONOMOUS_CHANGE_OFF 17 17 LC_UPCONFIGURE_CAP_OFF 18 18 LC_HW_LINK_DIS_EN 19 19 LC_LINK_DIS_BY_HW 20 20 LC_STATIC_TX_PIPE_COUNT_EN 21 21 LC_ASPM_L1_NAK_TIMER_SEL 22 23 LC_DONT_DEASSERT_RX_EN_IN_R_SPEED 24 24 LC_DONT_DEASSERT_RX_EN_IN_TEST 25 25 LC_RESET_ASPM_L1_NAK_TIMER 26 26 LC_SHORT_RCFG_TIMEOUT 27 27 LC_ALLOW_TX_L1_CONTROL 28 28 LC_WAIT_FOR_FOM_VALID_AFTER_TRACK 29 29 LC_EXTEND_EQ_REQ_TIME 30 31 ixPCIE_LC_LINK_WIDTH_CNTL 2 0x100100a2 24 0 4294967295 LC_LINK_WIDTH 0 2 LC_LINK_WIDTH_RD 4 6 LC_RECONFIG_ARC_MISSING_ESCAPE 7 7 LC_RECONFIG_NOW 8 8 LC_RENEGOTIATION_SUPPORT 9 9 LC_RENEGOTIATE_EN 10 10 LC_SHORT_RECONFIG_EN 11 11 LC_UPCONFIGURE_SUPPORT 12 12 LC_UPCONFIGURE_DIS 13 13 LC_UPCFG_WAIT_FOR_RCVR_DIS 14 14 LC_UPCFG_TIMER_SEL 15 15 LC_DEASSERT_TX_PDNB 16 16 LC_L1_RECONFIG_EN 17 17 LC_DYNLINK_MST_EN 18 18 LC_DUAL_END_RECONFIG_EN 19 19 LC_UPCONFIGURE_CAPABLE 20 20 LC_DYN_LANES_PWR_STATE 21 22 LC_EQ_REVERSAL_LOGIC_EN 23 23 LC_MULT_REVERSE_ATTEMP_EN 24 24 LC_RESET_TSX_CNT_IN_RCONFIG_EN 25 25 LC_WAIT_FOR_L_IDLE_IN_R_IDLE 26 26 LC_WAIT_FOR_NON_EI_ON_RXL0S_EXIT 27 27 LC_HOLD_EI_FOR_RSPEED_CMD_CHANGE 28 28 LC_BYPASS_RXL0S_ON_SHORT_EI 29 29 ixPCIE_LC_N_FTS_CNTL 2 0x100100a3 5 0 4294967295 LC_XMIT_N_FTS 0 7 LC_XMIT_N_FTS_OVERRIDE_EN 8 8 LC_XMIT_FTS_BEFORE_RECOVERY 9 9 LC_XMIT_N_FTS_LIMIT 16 23 LC_N_FTS 24 31 ixPCIE_LC_SPEED_CNTL 2 0x100100a4 28 0 4294967295 LC_GEN2_EN_STRAP 0 0 LC_GEN3_EN_STRAP 1 1 LC_TARGET_LINK_SPEED_OVERRIDE_EN 2 2 LC_TARGET_LINK_SPEED_OVERRIDE 3 4 LC_FORCE_EN_SW_SPEED_CHANGE 5 5 LC_FORCE_DIS_SW_SPEED_CHANGE 6 6 LC_FORCE_EN_HW_SPEED_CHANGE 7 7 LC_FORCE_DIS_HW_SPEED_CHANGE 8 8 LC_INITIATE_LINK_SPEED_CHANGE 9 9 LC_SPEED_CHANGE_ATTEMPTS_ALLOWED 10 11 LC_SPEED_CHANGE_ATTEMPT_FAILED 12 12 LC_CURRENT_DATA_RATE 13 14 LC_DONT_CLR_TARGET_SPD_CHANGE_STATUS 15 15 LC_CLR_FAILED_SPD_CHANGE_CNT 16 16 LC_1_OR_MORE_TS2_SPEED_ARC_EN 17 17 LC_OTHER_SIDE_EVER_SENT_GEN2 18 18 LC_OTHER_SIDE_SUPPORTS_GEN2 19 19 LC_OTHER_SIDE_EVER_SENT_GEN3 20 20 LC_OTHER_SIDE_SUPPORTS_GEN3 21 21 LC_AUTO_RECOVERY_DIS 22 22 LC_SPEED_CHANGE_STATUS 23 23 LC_DATA_RATE_ADVERTISED 24 25 LC_CHECK_DATA_RATE 26 26 LC_MULT_UPSTREAM_AUTO_SPD_CHNG_EN 27 27 LC_INIT_SPEED_NEG_IN_L0s_EN 28 28 LC_INIT_SPEED_NEG_IN_L1_EN 29 29 LC_DONT_CHECK_EQTS_IN_RCFG 30 30 LC_DELAY_COEFF_UPDATE_DIS 31 31 ixPCIE_LC_CDR_CNTL 2 0x100100b3 3 0 4294967295 LC_CDR_TEST_OFF 0 11 LC_CDR_TEST_SETS 12 23 LC_CDR_SET_TYPE 24 25 ixPCIE_LC_LANE_CNTL 2 0x100100b4 2 0 4294967295 LC_CORRUPTED_LANES 0 15 LC_LANE_DIS 16 31 ixPCIE_LC_FORCE_COEFF 2 0x100100b8 6 0 4294967295 LC_FORCE_COEFF 0 0 LC_FORCE_PRE_CURSOR 1 6 LC_FORCE_CURSOR 7 12 LC_FORCE_POST_CURSOR 13 18 LC_3X3_COEFF_SEARCH_EN 19 19 LC_PRESET_10_EN 20 20 ixPCIE_LC_BEST_EQ_SETTINGS 2 0x100100b9 5 0 4294967295 LC_BEST_PRESET 0 3 LC_BEST_PRECURSOR 4 9 LC_BEST_CURSOR 10 15 LC_BEST_POSTCURSOR 16 21 LC_BEST_FOM 22 29 ixPCIE_LC_FORCE_EQ_REQ_COEFF 2 0x100100ba 6 0 4294967295 LC_FORCE_COEFF_IN_EQ_REQ_PHASE 0 0 LC_FORCE_PRE_CURSOR_REQ 1 6 LC_FORCE_CURSOR_REQ 7 12 LC_FORCE_POST_CURSOR_REQ 13 18 LC_FS_OTHER_END 19 24 LC_LF_OTHER_END 25 30 ixPCIE_LC_STATE0 2 0x100100a5 4 0 4294967295 LC_CURRENT_STATE 0 5 LC_PREV_STATE1 8 13 LC_PREV_STATE2 16 21 LC_PREV_STATE3 24 29 ixPCIE_LC_STATE1 2 0x100100a6 4 0 4294967295 LC_PREV_STATE4 0 5 LC_PREV_STATE5 8 13 LC_PREV_STATE6 16 21 LC_PREV_STATE7 24 29 ixPCIE_LC_STATE2 2 0x100100a7 4 0 4294967295 LC_PREV_STATE8 0 5 LC_PREV_STATE9 8 13 LC_PREV_STATE10 16 21 LC_PREV_STATE11 24 29 ixPCIE_LC_STATE3 2 0x100100a8 4 0 4294967295 LC_PREV_STATE12 0 5 LC_PREV_STATE13 8 13 LC_PREV_STATE14 16 21 LC_PREV_STATE15 24 29 ixPCIE_LC_STATE4 2 0x100100a9 4 0 4294967295 LC_PREV_STATE16 0 5 LC_PREV_STATE17 8 13 LC_PREV_STATE18 16 21 LC_PREV_STATE19 24 29 ixPCIE_LC_STATE5 2 0x100100aa 4 0 4294967295 LC_PREV_STATE20 0 5 LC_PREV_STATE21 8 13 LC_PREV_STATE22 16 21 LC_PREV_STATE23 24 29 ixPCIEP_STRAP_LC 2 0x100100c0 11 0 4294967295 STRAP_FTS_yTSx_COUNT 0 1 STRAP_LONG_yTSx_COUNT 2 3 STRAP_MED_yTSx_COUNT 4 5 STRAP_SHORT_yTSx_COUNT 6 7 STRAP_SKIP_INTERVAL 8 10 STRAP_BYPASS_RCVR_DET 11 11 STRAP_COMPLIANCE_DIS 12 12 STRAP_FORCE_COMPLIANCE 13 13 STRAP_REVERSE_LC_LANES 14 14 STRAP_AUTO_RC_SPEED_NEGOTIATION_DIS 15 15 STRAP_LANE_NEGOTIATION 16 18 ixPCIEP_STRAP_MISC 2 0x100100c1 5 0 4294967295 STRAP_REVERSE_LANES 0 0 STRAP_E2E_PREFIX_EN 1 1 STRAP_EXTENDED_FMT_SUPPORTED 2 2 STRAP_OBFF_SUPPORTED 3 4 STRAP_LTR_SUPPORTED 5 5 ixPCIEP_BCH_ECC_CNTL 2 0x100100d0 3 0 4294967295 STRAP_BCH_ECC_EN 0 0 BCH_ECC_ERROR_THRESHOLD 8 15 BCH_ECC_ERROR_STATUS 16 31 ixPCIEP_HPGI_PRIVATE 2 0x100100d2 2 0 4294967295 PRESENCE_DETECT_CHANGED_PRIVATE 3 3 PRESENCE_DETECT_STATE_PRIVATE 6 6 ixPCIEP_HPGI 2 0x100100da 11 0 4294967295 REG_HPGI_ASSERT_TO_SMI_EN 0 0 REG_HPGI_ASSERT_TO_SCI_EN 1 1 REG_HPGI_DEASSERT_TO_SMI_EN 2 2 REG_HPGI_DEASSERT_TO_SCI_EN 3 3 REG_HPGI_HOOK 7 7 HPGI_REG_ASSERT_TO_SMI_STATUS 8 8 HPGI_REG_ASSERT_TO_SCI_STATUS 9 9 HPGI_REG_DEASSERT_TO_SMI_STATUS 10 10 HPGI_REG_DEASSERT_TO_SCI_STATUS 11 11 HPGI_REG_PRESENCE_DETECT_STATE_CHANGE_STATUS 15 15 REG_HPGI_PRESENCE_DETECT_STATE_CHANGE_EN 16 16 mmPCIEMSIX_VECT0_ADDR_LO 0 0x6000 1 0 4294967295 MSG_ADDR_LO 2 31 mmPCIEMSIX_VECT0_ADDR_HI 0 0x6001 1 0 4294967295 MSG_ADDR_HI 0 31 mmPCIEMSIX_VECT0_MSG_DATA 0 0x6002 1 0 4294967295 MSG_DATA 0 31 mmPCIEMSIX_VECT0_CONTROL 0 0x6003 1 0 4294967295 MASK_BIT 0 0 mmPCIEMSIX_VECT1_ADDR_LO 0 0x6004 1 0 4294967295 MSG_ADDR_LO 2 31 mmPCIEMSIX_VECT1_ADDR_HI 0 0x6005 1 0 4294967295 MSG_ADDR_HI 0 31 mmPCIEMSIX_VECT1_MSG_DATA 0 0x6006 1 0 4294967295 MSG_DATA 0 31 mmPCIEMSIX_VECT1_CONTROL 0 0x6007 1 0 4294967295 MASK_BIT 0 0 mmPCIEMSIX_VECT2_ADDR_LO 0 0x6008 1 0 4294967295 MSG_ADDR_LO 2 31 mmPCIEMSIX_VECT2_ADDR_HI 0 0x6009 1 0 4294967295 MSG_ADDR_HI 0 31 mmPCIEMSIX_VECT2_MSG_DATA 0 0x600a 1 0 4294967295 MSG_DATA 0 31 mmPCIEMSIX_VECT2_CONTROL 0 0x600b 1 0 4294967295 MASK_BIT 0 0 mmPCIEMSIX_VECT3_ADDR_LO 0 0x600c 1 0 4294967295 MSG_ADDR_LO 2 31 mmPCIEMSIX_VECT3_ADDR_HI 0 0x600d 1 0 4294967295 MSG_ADDR_HI 0 31 mmPCIEMSIX_VECT3_MSG_DATA 0 0x600e 1 0 4294967295 MSG_DATA 0 31 mmPCIEMSIX_VECT3_CONTROL 0 0x600f 1 0 4294967295 MASK_BIT 0 0 mmPCIEMSIX_PBA 0 0x6200 1 0 4294967295 MSIX_PENDING_BITS 0 3 mmBIF_RFE_SNOOP_REG 0 0x27 2 0 4294967295 REG_SNOOP_ARBITER 0 0 REG_SNOOP_ALLMASTER 1 1 mmBIF_RFE_WARMRST_CNTL 0 0x1459 2 0 4294967295 REG_RST_warmRstRfeEn 0 0 REG_RST_warmRstImpEn 1 1 mmBIF_RFE_SOFTRST_CNTL 0 0x1441 3 0 4294967295 REG_RST_rstTimer 0 15 REG_RST_softRstPropEn 30 30 SoftRstReg 31 31 mmBIF_RFE_IMPRST_CNTL 0 0x1458 1 0 4294967295 REG_RST_impEn 0 0 mmBIF_RFE_CLIENT_SOFTRST_TRIGGER 0 0x1442 2 0 4294967295 CLIENT0_RFE_RFEWDBIF_rst 0 0 CLIENT1_RFE_RFEWDBIF_rst 1 1 mmBIF_RFE_MASTER_SOFTRST_TRIGGER 0 0x1443 4 0 4294967295 BU_rst 0 0 RWREG_RFEWDBIF_rst 1 1 SMBUS_rst 2 2 BX_rst 3 3 mmBIF_PWDN_COMMAND 0 0x1444 4 0 4294967295 REG_BU_pw_cmd 0 0 REG_RWREG_RFEWDBIF_pw_cmd 1 1 REG_SMBUS_pw_cmd 2 2 REG_BX_pw_cmd 3 3 mmBIF_PWDN_STATUS 0 0x1445 4 0 4294967295 BU_REG_pw_status 0 0 RWREG_RFEWDBIF_REG_pw_status 1 1 SMBUS_REG_pw_status 2 2 BX_REG_pw_status 3 3 mmBIF_RFE_MST_BU_CMDSTATUS 0 0x1446 4 0 4294967295 REG_BU_clkGate_timer 0 7 REG_BU_clkSetup_timer 8 11 REG_BU_timeout_timer 16 23 BU_RFE_mstTimeout 24 24 mmBIF_RFE_MST_RWREG_RFEWDBIF_CMDSTATUS 0 0x1447 4 0 4294967295 REG_RWREG_RFEWDBIF_clkGate_timer 0 7 REG_RWREG_RFEWDBIF_clkSetup_timer 8 11 REG_RWREG_RFEWDBIF_timeout_timer 16 23 RWREG_RFEWDBIF_RFE_mstTimeout 24 24 mmBIF_RFE_MST_SMBUS_CMDSTATUS 0 0x1448 4 0 4294967295 REG_SMBUS_clkGate_timer 0 7 REG_SMBUS_clkSetup_timer 8 11 REG_SMBUS_timeout_timer 16 23 SMBUS_RFE_mstTimeout 24 24 mmBIF_RFE_MST_BX_CMDSTATUS 0 0x1449 4 0 4294967295 REG_BX_clkGate_timer 0 7 REG_BX_clkSetup_timer 8 11 REG_BX_timeout_timer 16 23 BX_RFE_mstTimeout 24 24 mmBIF_RFE_MST_TMOUT_STATUS 0 0x144b 1 0 4294967295 MstTmoutStatus 0 0 mmBIF_RFE_MMCFG_CNTL 0 0x144c 4 0 4294967295 CLIENT0_RFE_RFEWDBIF_MM_WR_TO_CFG_EN 0 0 CLIENT0_RFE_RFEWDBIF_MM_CFG_FUNC_SEL 1 3 CLIENT1_RFE_RFEWDBIF_MM_WR_TO_CFG_EN 4 4 CLIENT1_RFE_RFEWDBIF_MM_CFG_FUNC_SEL 5 7 mmBIF_CC_RFE_IMP_OVERRIDECNTL 0 0x1455 8 0 4294967295 STRAP_PLL_RX_IMPVAL 1 4 STRAP_PLL_RX_IMPVAL_EN 5 5 STRAP_PLL_TX_IMPVAL_PD 6 9 STRAP_PLL_TX_IMPVAL_EN_PD 10 10 STRAP_PLL_TX_IMPVAL_PU 11 14 STRAP_PLL_TX_IMPVAL_EN_PU 15 15 STRAP_PLL_IMP_DBG_ANALOG_EN 16 16 STRAP_PLL_IMP_IGNORE_QUICKSIM 17 17 mmBIF_IMPCTL_SMPLCNTL 0 0x1450 10 0 4294967295 FORCE_DONE 0 0 RxPDNB 1 1 TxPDNB_pd 2 2 TxPDNB_pu 3 3 SAMPLE_PERIOD 8 12 EXTEND_SAMPLES 13 13 FORCE_ENABLE 14 14 SETUP_TIME 15 19 LOWER_SAMPLE_THRESH 20 25 UPPER_SAMPLE_THRESH 26 31 mmBIF_IMPCTL_RXCNTL 0 0x1451 14 0 4294967295 RX_ADJUST 0 2 RX_BIAS_HIGH 3 3 CONT_AFTER_RX_DECT 4 4 SUSPEND 6 6 FORCE_RST 7 7 LOWER_RX_ADJ_THRESH 8 11 LOWER_RX_ADJ 12 12 UPPER_RX_ADJ_THRESH 13 16 UPPER_RX_ADJ 17 17 RX_IMP_LOCKED 18 18 RX_IMP_READBACK_SEL 19 19 RX_IMP_READBACK 20 23 RX_CMP_AMBIG 28 28 CAL_DONE 29 29 mmBIF_IMPCTL_TXCNTL_pd 0 0x1452 10 0 4294967295 TX_ADJUST_pd 0 2 TX_BIAS_HIGH_pd 3 3 LOWER_TX_ADJ_THRESH_pd 8 11 LOWER_TX_ADJ_pd 12 12 UPPER_TX_ADJ_THRESH_pd 13 16 UPPER_TX_ADJ_pd 17 17 TX_IMP_LOCKED_pd 18 18 TX_IMP_READBACK_SEL_pd 19 19 TX_IMP_READBACK_pd 20 23 TX_CMP_AMBIG_pd 28 28 mmBIF_IMPCTL_TXCNTL_pu 0 0x1453 10 0 4294967295 TX_ADJUST_pu 0 2 TX_BIAS_HIGH_pu 3 3 LOWER_TX_ADJ_THRESH_pu 8 11 LOWER_TX_ADJ_pu 12 12 UPPER_TX_ADJ_THRESH_pu 13 16 UPPER_TX_ADJ_pu 17 17 TX_IMP_LOCKED_pu 18 18 TX_IMP_READBACK_SEL_pu 19 19 TX_IMP_READBACK_pu 20 23 TX_CMP_AMBIG_pu 28 28 mmBIF_IMPCTL_CONTINUOUS_CALIBRATION_PERIOD 0 0x1454 1 0 4294967295 UPDATE_PERIOD 0 31