11
mmCLK1_0_CLK1_CLK_PLL_REQ 0 0x410 2 0 0
	FbMult_int 0 8
	FbMult_frac 16 31
mmCLK1_0_CLK1_CLK0_BYPASS_CNTL 0 0x44a 2 0 0
	CLK0_BYPASS_SEL 0 2
	CLK0_BYPASS_DIV 16 19
mmCLK1_0_CLK1_CLK1_BYPASS_CNTL 0 0x454 2 0 0
	CLK1_BYPASS_SEL 0 2
	CLK1_BYPASS_DIV 16 19
mmCLK1_0_CLK1_CLK2_BYPASS_CNTL 0 0x45e 2 0 0
	CLK2_BYPASS_SEL 0 2
	CLK2_BYPASS_DIV 16 19
mmCLK1_0_CLK1_CLK3_DS_CNTL 0 0x461 1 0 0
	CLK3_DS_DIV_ID 0 2
mmCLK1_0_CLK1_CLK3_ALLOW_DS 0 0x462 1 0 0
	CLK3_ALLOW_DS 0 0
mmCLK1_0_CLK1_CLK3_BYPASS_CNTL 0 0x468 2 0 0
	CLK3_BYPASS_SEL 0 2
	CLK3_BYPASS_DIV 16 19
mmCLK1_0_CLK1_CLK0_CURRENT_CNT 0 0x4a7 1 0 0
	CURRENT_COUNT 0 31
mmCLK1_0_CLK1_CLK1_CURRENT_CNT 0 0x4a8 1 0 0
	CURRENT_COUNT 0 31
mmCLK1_0_CLK1_CLK2_CURRENT_CNT 0 0x4a9 1 0 0
	CURRENT_COUNT 0 31
mmCLK1_0_CLK1_CLK3_CURRENT_CNT 0 0x4aa 1 0 0
	CURRENT_COUNT 0 31