9137 mmdispdec_VGA_MEM_WRITE_PAGE_ADDR 0 0x12 2 0 0 VGA_MEM_WRITE_PAGE0_ADDR 0 9 VGA_MEM_WRITE_PAGE1_ADDR 16 25 mmdispdec_VGA_MEM_READ_PAGE_ADDR 0 0x14 2 0 0 VGA_MEM_READ_PAGE0_ADDR 0 9 VGA_MEM_READ_PAGE1_ADDR 16 25 mmDC_PERFMON0_PERFCOUNTER_CNTL 0 0x20 13 0 2 PERFCOUNTER_EVENT_SEL 0 8 PERFCOUNTER_CVALUE_SEL 9 11 PERFCOUNTER_INC_MODE 12 14 PERFCOUNTER_HW_CNTL_SEL 15 15 PERFCOUNTER_RUNEN_MODE 16 16 PERFCOUNTER_CNTOFF_SEL 17 21 PERFCOUNTER_CNTOFF_START_DIS 22 22 PERFCOUNTER_RESTART_EN 23 23 PERFCOUNTER_INT_EN 24 24 PERFCOUNTER_OFF_MASK 25 25 PERFCOUNTER_ACTIVE 26 26 PERFCOUNTER_INT_TYPE 27 27 PERFCOUNTER_CNTL_SEL 29 31 mmDC_PERFMON0_PERFCOUNTER_CNTL2 0 0x21 4 0 2 PERFCOUNTER_COUNTED_VALUE_TYPE 0 1 PERFCOUNTER_HW_STOP1_SEL 2 2 PERFCOUNTER_HW_STOP2_SEL 3 3 PERFCOUNTER_CNTL2_SEL 29 31 mmDC_PERFMON0_PERFCOUNTER_STATE 0 0x22 16 0 2 PERFCOUNTER_CNT0_STATE 0 1 PERFCOUNTER_STATE_SEL0 2 2 PERFCOUNTER_CNT1_STATE 4 5 PERFCOUNTER_STATE_SEL1 6 6 PERFCOUNTER_CNT2_STATE 8 9 PERFCOUNTER_STATE_SEL2 10 10 PERFCOUNTER_CNT3_STATE 12 13 PERFCOUNTER_STATE_SEL3 14 14 PERFCOUNTER_CNT4_STATE 16 17 PERFCOUNTER_STATE_SEL4 18 18 PERFCOUNTER_CNT5_STATE 20 21 PERFCOUNTER_STATE_SEL5 22 22 PERFCOUNTER_CNT6_STATE 24 25 PERFCOUNTER_STATE_SEL6 26 26 PERFCOUNTER_CNT7_STATE 28 29 PERFCOUNTER_STATE_SEL7 30 30 mmDC_PERFMON0_PERFMON_CNTL 0 0x23 6 0 2 PERFMON_STATE 0 1 PERFMON_RPT_COUNT 8 27 PERFMON_CNTOFF_AND_OR 28 28 PERFMON_CNTOFF_INT_EN 29 29 PERFMON_CNTOFF_INT_STATUS 30 30 PERFMON_CNTOFF_INT_ACK 31 31 mmDC_PERFMON0_PERFMON_CNTL2 0 0x24 4 0 2 PERFMON_CNTOFF_INT_TYPE 0 0 PERFMON_CLK_ENABLE 1 1 PERFMON_RUN_ENABLE_START_SEL 2 9 PERFMON_RUN_ENABLE_STOP_SEL 10 17 mmDC_PERFMON0_PERFMON_CVALUE_INT_MISC 0 0x25 17 0 2 PERFCOUNTER_INT0_STATUS 0 0 PERFCOUNTER_INT1_STATUS 1 1 PERFCOUNTER_INT2_STATUS 2 2 PERFCOUNTER_INT3_STATUS 3 3 PERFCOUNTER_INT4_STATUS 4 4 PERFCOUNTER_INT5_STATUS 5 5 PERFCOUNTER_INT6_STATUS 6 6 PERFCOUNTER_INT7_STATUS 7 7 PERFCOUNTER_INT0_ACK 8 8 PERFCOUNTER_INT1_ACK 9 9 PERFCOUNTER_INT2_ACK 10 10 PERFCOUNTER_INT3_ACK 11 11 PERFCOUNTER_INT4_ACK 12 12 PERFCOUNTER_INT5_ACK 13 13 PERFCOUNTER_INT6_ACK 14 14 PERFCOUNTER_INT7_ACK 15 15 PERFMON_CVALUE_HI 16 31 mmDC_PERFMON0_PERFMON_CVALUE_LOW 0 0x26 1 0 2 PERFMON_CVALUE_LOW 0 31 mmDC_PERFMON0_PERFMON_HI 0 0x27 2 0 2 PERFMON_HI 0 15 PERFMON_READ_SEL 29 31 mmDC_PERFMON0_PERFMON_LOW 0 0x28 1 0 2 PERFMON_LOW 0 31 mmDC_PERFMON13_PERFCOUNTER_CNTL 0 0x2c 13 0 2 PERFCOUNTER_EVENT_SEL 0 8 PERFCOUNTER_CVALUE_SEL 9 11 PERFCOUNTER_INC_MODE 12 14 PERFCOUNTER_HW_CNTL_SEL 15 15 PERFCOUNTER_RUNEN_MODE 16 16 PERFCOUNTER_CNTOFF_SEL 17 21 PERFCOUNTER_CNTOFF_START_DIS 22 22 PERFCOUNTER_RESTART_EN 23 23 PERFCOUNTER_INT_EN 24 24 PERFCOUNTER_OFF_MASK 25 25 PERFCOUNTER_ACTIVE 26 26 PERFCOUNTER_INT_TYPE 27 27 PERFCOUNTER_CNTL_SEL 29 31 mmDC_PERFMON13_PERFCOUNTER_CNTL2 0 0x2d 4 0 2 PERFCOUNTER_COUNTED_VALUE_TYPE 0 1 PERFCOUNTER_HW_STOP1_SEL 2 2 PERFCOUNTER_HW_STOP2_SEL 3 3 PERFCOUNTER_CNTL2_SEL 29 31 mmDC_PERFMON13_PERFCOUNTER_STATE 0 0x2e 16 0 2 PERFCOUNTER_CNT0_STATE 0 1 PERFCOUNTER_STATE_SEL0 2 2 PERFCOUNTER_CNT1_STATE 4 5 PERFCOUNTER_STATE_SEL1 6 6 PERFCOUNTER_CNT2_STATE 8 9 PERFCOUNTER_STATE_SEL2 10 10 PERFCOUNTER_CNT3_STATE 12 13 PERFCOUNTER_STATE_SEL3 14 14 PERFCOUNTER_CNT4_STATE 16 17 PERFCOUNTER_STATE_SEL4 18 18 PERFCOUNTER_CNT5_STATE 20 21 PERFCOUNTER_STATE_SEL5 22 22 PERFCOUNTER_CNT6_STATE 24 25 PERFCOUNTER_STATE_SEL6 26 26 PERFCOUNTER_CNT7_STATE 28 29 PERFCOUNTER_STATE_SEL7 30 30 mmDC_PERFMON13_PERFMON_CNTL 0 0x2f 6 0 2 PERFMON_STATE 0 1 PERFMON_RPT_COUNT 8 27 PERFMON_CNTOFF_AND_OR 28 28 PERFMON_CNTOFF_INT_EN 29 29 PERFMON_CNTOFF_INT_STATUS 30 30 PERFMON_CNTOFF_INT_ACK 31 31 mmDC_PERFMON13_PERFMON_CNTL2 0 0x30 4 0 2 PERFMON_CNTOFF_INT_TYPE 0 0 PERFMON_CLK_ENABLE 1 1 PERFMON_RUN_ENABLE_START_SEL 2 9 PERFMON_RUN_ENABLE_STOP_SEL 10 17 mmDC_PERFMON13_PERFMON_CVALUE_INT_MISC 0 0x31 17 0 2 PERFCOUNTER_INT0_STATUS 0 0 PERFCOUNTER_INT1_STATUS 1 1 PERFCOUNTER_INT2_STATUS 2 2 PERFCOUNTER_INT3_STATUS 3 3 PERFCOUNTER_INT4_STATUS 4 4 PERFCOUNTER_INT5_STATUS 5 5 PERFCOUNTER_INT6_STATUS 6 6 PERFCOUNTER_INT7_STATUS 7 7 PERFCOUNTER_INT0_ACK 8 8 PERFCOUNTER_INT1_ACK 9 9 PERFCOUNTER_INT2_ACK 10 10 PERFCOUNTER_INT3_ACK 11 11 PERFCOUNTER_INT4_ACK 12 12 PERFCOUNTER_INT5_ACK 13 13 PERFCOUNTER_INT6_ACK 14 14 PERFCOUNTER_INT7_ACK 15 15 PERFMON_CVALUE_HI 16 31 mmDC_PERFMON13_PERFMON_CVALUE_LOW 0 0x32 1 0 2 PERFMON_CVALUE_LOW 0 31 mmDC_PERFMON13_PERFMON_HI 0 0x33 2 0 2 PERFMON_HI 0 15 PERFMON_READ_SEL 29 31 mmDC_PERFMON13_PERFMON_LOW 0 0x34 1 0 2 PERFMON_LOW 0 31 mmPPLL_VREG_CFG 0 0x38 14 0 2 pw_pc_bleeder_ac 0 0 pw_pc_bleeder_en 1 1 pw_pc_is_1p2 2 2 pw_pc_reg_obs_sel 3 4 pw_pc_reg_on_mode 5 6 pw_pc_rlad_tap_sel 7 10 pw_pc_reg_off_hi 11 11 pw_pc_reg_off_lo 12 12 pw_pc_scale_driver 13 14 pw_pc_sel_bump 15 15 pw_pc_sel_rladder_x 16 16 pw_pc_short_rc_filt_x 17 17 pw_pc_vref_pwr_on 18 18 pw_pc_dpll_cfg_2 20 27 mmPPLL_MODE_CNTL 0 0x39 3 0 2 pw_pc_refclk_gate_dis 0 0 pw_pc_multi_phase_en 8 11 reg_tmg_pwr_state 16 17 mmPPLL_FREQ_CTRL0 0 0x3a 2 0 2 reg_tmg_fcw0_frac 0 15 reg_tmg_fcw0_int 16 24 mmPPLL_FREQ_CTRL1 0 0x3b 2 0 2 reg_tmg_fcw1_frac 0 15 reg_tmg_fcw1_int 16 24 mmPPLL_FREQ_CTRL2 0 0x3c 2 0 2 reg_tmg_fcw_denom 0 15 reg_tmg_fcw_slew_frac 16 31 mmPPLL_FREQ_CTRL3 0 0x3d 8 0 2 reg_tmg_refclk_div 0 1 reg_tmg_vco_pre_div 3 4 reg_tmg_fracn_en 6 6 reg_tmg_ssc_en 8 8 reg_tmg_fcw_sel 10 10 reg_tmg_freq_jump_en 12 12 reg_tmg_tdc_resol 16 23 pw_pc_dpll_cfg_1 24 31 mmPPLL_BW_CTRL_COARSE 0 0x3e 6 0 2 reg_tmg_gi_crse_mant 0 1 reg_tmg_gi_crse_exp 2 5 reg_tmg_gp_crse_mant 7 10 reg_tmg_gp_crse_exp 12 15 reg_tmg_nctl_crse_res 17 22 reg_tmg_nctl_crse_frac_res 24 25 mmPPLL_BW_CTRL_FINE 0 0x40 1 0 2 pw_pc_dpll_cfg_3 0 9 mmPPLL_CAL_CTRL 0 0x41 9 0 2 pw_pc_bypass_freq_lock 0 0 pw_pc_tdc_cal_en 1 1 pw_pc_tdc_cal_ctrl 3 8 pw_pc_meas_win_sel 9 10 pw_pc_kdco_cal_dis 11 11 pw_pc_kdco_ratio 13 20 pw_pc_kdco_incr_cal_dis 22 22 pw_pc_nctl_adj_dis 23 23 pw_pc_refclk_rate 24 31 mmPPLL_LOOP_CTRL 0 0x42 10 0 2 pw_pc_fbdiv_mask_en 0 0 pw_pc_fb_slip_dis 2 2 pw_pc_clk_tdc_sel 4 5 pw_pc_clk_nctl_sel 7 8 pw_pc_sig_del_patt_sel 10 10 pw_pc_nctl_sig_del_dis 12 12 pw_pc_fbclk_track_refclk 14 14 pw_pc_prbs_en 16 16 pw_pc_tdc_clk_gate_en 18 18 pw_pc_phase_offset 20 26 mmPPLL_REFCLK_CNTL 0 0x50 10 0 2 regs_pw_refclk0_recv_en 0 0 regs_pw_refclk1_recv_en 1 1 regs_pw_refclk2_recv_en 2 2 regs_pw_refclk3_recv_en 3 3 regs_pw_refclk0_recv_sel 8 8 regs_pw_refclk1_recv_sel 9 9 regs_pw_refclk2_recv_sel 10 10 regs_pw_refclk3_recv_sel 11 11 regs_pw_refdivsrc 14 15 regs_pw_ref2core_sel 16 16 mmPPLL_CLKOUT_CNTL 0 0x51 10 0 2 regs_pw_pixclk_pre_pdivsel 8 8 regs_pw_pixclk_pdivsel 9 9 regs_pw_dvoclk_pre_pdivsel 10 10 regs_pw_dvoclk_pdivsel 11 11 regs_pw_idclk_en 12 12 regs_pw_idclk_pre_pdivsel 13 13 regs_pw_idclk_pdivsel 14 14 regs_pw_idclk_obs_sel 15 15 regs_pw_refclk_sel 16 17 regs_cc_resetb 20 20 mmPPLL_DFT_CNTL 0 0x52 5 0 2 regs_pw_obs_en 0 0 regs_pw_obs_div_sel_1 1 2 regs_pw_obs_clk_sel_1 4 7 regs_pw_obs_clk_sel_2 8 11 regs_pw_obs_sel 12 13 mmPPLL_ANALOG_CNTL 0 0x53 1 0 2 regs_pw_spare 0 7 mmPPLL_POSTDIV 0 0x54 2 0 2 reg_tmg_postdiv 8 11 reg_tmg_pixclk_pdiv2 12 12 mmPPLL_OBSERVE0 0 0x59 5 0 2 pw_pc_lock_det_tdc_steps 0 4 pw_pc_clear_sticky_lock 6 6 pw_pc_lock_det_dis 8 8 pw_pc_dco_cfg 10 17 pw_pc_anaobs_sel 21 23 mmPPLL_OBSERVE1 0 0x5a 5 0 2 pw_pc_digobs_sel 0 3 pw_pc_digobs_trig_sel 5 8 pw_pc_digobs_div 10 11 pw_pc_digobs_trig_div 12 13 reg_tmg_lock_timer 16 29 mmPPLL_UPDATE_CNTL 0 0x5c 5 0 2 reg_tmg_PLL_UPDATE_LOCK 2 2 reg_tmg_PLL_UPDATE_POINT 3 3 tmg_reg_UPDATE_PENDING 8 8 pc_pw_pll_rdy 9 9 TieLow1 16 16 mmPPLL_OBSERVE0_OUT 0 0x5d 1 0 2 disppll_core_obsout 0 31 mmPLL_MACRO_CNTL_RESERVED0 0 0x38 1 0 2 PLL_MACRO_CNTL_RESERVED 0 31 mmPLL_MACRO_CNTL_RESERVED1 0 0x39 1 0 2 PLL_MACRO_CNTL_RESERVED 0 31 mmPLL_MACRO_CNTL_RESERVED2 0 0x3a 1 0 2 PLL_MACRO_CNTL_RESERVED 0 31 mmPLL_MACRO_CNTL_RESERVED3 0 0x3b 1 0 2 PLL_MACRO_CNTL_RESERVED 0 31 mmPLL_MACRO_CNTL_RESERVED4 0 0x3c 1 0 2 PLL_MACRO_CNTL_RESERVED 0 31 mmPLL_MACRO_CNTL_RESERVED5 0 0x3d 1 0 2 PLL_MACRO_CNTL_RESERVED 0 31 mmPLL_MACRO_CNTL_RESERVED6 0 0x3e 1 0 2 PLL_MACRO_CNTL_RESERVED 0 31 mmPLL_MACRO_CNTL_RESERVED7 0 0x3f 1 0 2 PLL_MACRO_CNTL_RESERVED 0 31 mmPLL_MACRO_CNTL_RESERVED8 0 0x40 1 0 2 PLL_MACRO_CNTL_RESERVED 0 31 mmPLL_MACRO_CNTL_RESERVED9 0 0x41 1 0 2 PLL_MACRO_CNTL_RESERVED 0 31 mmPLL_MACRO_CNTL_RESERVED10 0 0x42 1 0 2 PLL_MACRO_CNTL_RESERVED 0 31 mmPLL_MACRO_CNTL_RESERVED11 0 0x43 1 0 2 PLL_MACRO_CNTL_RESERVED 0 31 mmPLL_MACRO_CNTL_RESERVED12 0 0x44 1 0 2 PLL_MACRO_CNTL_RESERVED 0 31 mmPLL_MACRO_CNTL_RESERVED13 0 0x45 1 0 2 PLL_MACRO_CNTL_RESERVED 0 31 mmPLL_MACRO_CNTL_RESERVED14 0 0x46 1 0 2 PLL_MACRO_CNTL_RESERVED 0 31 mmPLL_MACRO_CNTL_RESERVED15 0 0x47 1 0 2 PLL_MACRO_CNTL_RESERVED 0 31 mmPLL_MACRO_CNTL_RESERVED16 0 0x48 1 0 2 PLL_MACRO_CNTL_RESERVED 0 31 mmPLL_MACRO_CNTL_RESERVED17 0 0x49 1 0 2 PLL_MACRO_CNTL_RESERVED 0 31 mmPLL_MACRO_CNTL_RESERVED18 0 0x4a 1 0 2 PLL_MACRO_CNTL_RESERVED 0 31 mmPLL_MACRO_CNTL_RESERVED19 0 0x4b 1 0 2 PLL_MACRO_CNTL_RESERVED 0 31 mmPLL_MACRO_CNTL_RESERVED20 0 0x4c 1 0 2 PLL_MACRO_CNTL_RESERVED 0 31 mmPLL_MACRO_CNTL_RESERVED21 0 0x4d 1 0 2 PLL_MACRO_CNTL_RESERVED 0 31 mmPLL_MACRO_CNTL_RESERVED22 0 0x4e 1 0 2 PLL_MACRO_CNTL_RESERVED 0 31 mmPLL_MACRO_CNTL_RESERVED23 0 0x4f 1 0 2 PLL_MACRO_CNTL_RESERVED 0 31 mmPLL_MACRO_CNTL_RESERVED24 0 0x50 1 0 2 PLL_MACRO_CNTL_RESERVED 0 31 mmPLL_MACRO_CNTL_RESERVED25 0 0x51 1 0 2 PLL_MACRO_CNTL_RESERVED 0 31 mmPLL_MACRO_CNTL_RESERVED26 0 0x52 1 0 2 PLL_MACRO_CNTL_RESERVED 0 31 mmPLL_MACRO_CNTL_RESERVED27 0 0x53 1 0 2 PLL_MACRO_CNTL_RESERVED 0 31 mmPLL_MACRO_CNTL_RESERVED28 0 0x54 1 0 2 PLL_MACRO_CNTL_RESERVED 0 31 mmPLL_MACRO_CNTL_RESERVED29 0 0x55 1 0 2 PLL_MACRO_CNTL_RESERVED 0 31 mmPLL_MACRO_CNTL_RESERVED30 0 0x56 1 0 2 PLL_MACRO_CNTL_RESERVED 0 31 mmPLL_MACRO_CNTL_RESERVED31 0 0x57 1 0 2 PLL_MACRO_CNTL_RESERVED 0 31 mmPLL_MACRO_CNTL_RESERVED32 0 0x58 1 0 2 PLL_MACRO_CNTL_RESERVED 0 31 mmPLL_MACRO_CNTL_RESERVED33 0 0x59 1 0 2 PLL_MACRO_CNTL_RESERVED 0 31 mmPLL_MACRO_CNTL_RESERVED34 0 0x5a 1 0 2 PLL_MACRO_CNTL_RESERVED 0 31 mmPLL_MACRO_CNTL_RESERVED35 0 0x5b 1 0 2 PLL_MACRO_CNTL_RESERVED 0 31 mmPLL_MACRO_CNTL_RESERVED36 0 0x5c 1 0 2 PLL_MACRO_CNTL_RESERVED 0 31 mmPLL_MACRO_CNTL_RESERVED37 0 0x5d 1 0 2 PLL_MACRO_CNTL_RESERVED 0 31 mmPLL_MACRO_CNTL_RESERVED38 0 0x5e 1 0 2 PLL_MACRO_CNTL_RESERVED 0 31 mmPLL_MACRO_CNTL_RESERVED39 0 0x5f 1 0 2 PLL_MACRO_CNTL_RESERVED 0 31 mmPLL_MACRO_CNTL_RESERVED40 0 0x60 1 0 2 PLL_MACRO_CNTL_RESERVED 0 31 mmPLL_MACRO_CNTL_RESERVED41 0 0x61 1 0 2 PLL_MACRO_CNTL_RESERVED 0 31 mmDC_PERFMON1_PERFCOUNTER_CNTL 0 0x186 13 0 2 PERFCOUNTER_EVENT_SEL 0 8 PERFCOUNTER_CVALUE_SEL 9 11 PERFCOUNTER_INC_MODE 12 14 PERFCOUNTER_HW_CNTL_SEL 15 15 PERFCOUNTER_RUNEN_MODE 16 16 PERFCOUNTER_CNTOFF_SEL 17 21 PERFCOUNTER_CNTOFF_START_DIS 22 22 PERFCOUNTER_RESTART_EN 23 23 PERFCOUNTER_INT_EN 24 24 PERFCOUNTER_OFF_MASK 25 25 PERFCOUNTER_ACTIVE 26 26 PERFCOUNTER_INT_TYPE 27 27 PERFCOUNTER_CNTL_SEL 29 31 mmDC_PERFMON1_PERFCOUNTER_CNTL2 0 0x187 4 0 2 PERFCOUNTER_COUNTED_VALUE_TYPE 0 1 PERFCOUNTER_HW_STOP1_SEL 2 2 PERFCOUNTER_HW_STOP2_SEL 3 3 PERFCOUNTER_CNTL2_SEL 29 31 mmDC_PERFMON1_PERFCOUNTER_STATE 0 0x188 16 0 2 PERFCOUNTER_CNT0_STATE 0 1 PERFCOUNTER_STATE_SEL0 2 2 PERFCOUNTER_CNT1_STATE 4 5 PERFCOUNTER_STATE_SEL1 6 6 PERFCOUNTER_CNT2_STATE 8 9 PERFCOUNTER_STATE_SEL2 10 10 PERFCOUNTER_CNT3_STATE 12 13 PERFCOUNTER_STATE_SEL3 14 14 PERFCOUNTER_CNT4_STATE 16 17 PERFCOUNTER_STATE_SEL4 18 18 PERFCOUNTER_CNT5_STATE 20 21 PERFCOUNTER_STATE_SEL5 22 22 PERFCOUNTER_CNT6_STATE 24 25 PERFCOUNTER_STATE_SEL6 26 26 PERFCOUNTER_CNT7_STATE 28 29 PERFCOUNTER_STATE_SEL7 30 30 mmDC_PERFMON1_PERFMON_CNTL 0 0x189 6 0 2 PERFMON_STATE 0 1 PERFMON_RPT_COUNT 8 27 PERFMON_CNTOFF_AND_OR 28 28 PERFMON_CNTOFF_INT_EN 29 29 PERFMON_CNTOFF_INT_STATUS 30 30 PERFMON_CNTOFF_INT_ACK 31 31 mmDC_PERFMON1_PERFMON_CNTL2 0 0x18a 4 0 2 PERFMON_CNTOFF_INT_TYPE 0 0 PERFMON_CLK_ENABLE 1 1 PERFMON_RUN_ENABLE_START_SEL 2 9 PERFMON_RUN_ENABLE_STOP_SEL 10 17 mmDC_PERFMON1_PERFMON_CVALUE_INT_MISC 0 0x18b 17 0 2 PERFCOUNTER_INT0_STATUS 0 0 PERFCOUNTER_INT1_STATUS 1 1 PERFCOUNTER_INT2_STATUS 2 2 PERFCOUNTER_INT3_STATUS 3 3 PERFCOUNTER_INT4_STATUS 4 4 PERFCOUNTER_INT5_STATUS 5 5 PERFCOUNTER_INT6_STATUS 6 6 PERFCOUNTER_INT7_STATUS 7 7 PERFCOUNTER_INT0_ACK 8 8 PERFCOUNTER_INT1_ACK 9 9 PERFCOUNTER_INT2_ACK 10 10 PERFCOUNTER_INT3_ACK 11 11 PERFCOUNTER_INT4_ACK 12 12 PERFCOUNTER_INT5_ACK 13 13 PERFCOUNTER_INT6_ACK 14 14 PERFCOUNTER_INT7_ACK 15 15 PERFMON_CVALUE_HI 16 31 mmDC_PERFMON1_PERFMON_CVALUE_LOW 0 0x18c 1 0 2 PERFMON_CVALUE_LOW 0 31 mmDC_PERFMON1_PERFMON_HI 0 0x18d 2 0 2 PERFMON_HI 0 15 PERFMON_READ_SEL 29 31 mmDC_PERFMON1_PERFMON_LOW 0 0x18e 1 0 2 PERFMON_LOW 0 31 mmMCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL 0 0x272 9 0 2 MCIF_WB_BUFMGR_ENABLE 0 0 MCIF_WB_BUF_DUALSIZE_REQ 1 1 MCIF_WB_BUFMGR_SW_INT_EN 4 4 MCIF_WB_BUFMGR_SW_INT_ACK 5 5 MCIF_WB_BUFMGR_SW_SLICE_INT_EN 6 6 MCIF_WB_BUFMGR_SW_OVERRUN_INT_EN 7 7 MCIF_WB_BUFMGR_SW_LOCK 8 11 MCIF_WB_P_VMID 16 19 MCIF_WB_BUF_ADDR_FENCE_EN 24 24 mmMCIF_WB0_MCIF_WB_BUFMGR_CUR_LINE_R 0 0x273 1 0 2 MCIF_WB_BUFMGR_CUR_LINE_R 0 12 mmMCIF_WB0_MCIF_WB_BUFMGR_STATUS 0 0x274 8 0 2 MCIF_WB_BUFMGR_VCE_INT_STATUS 0 0 MCIF_WB_BUFMGR_SW_INT_STATUS 1 1 MCIF_WB_BUFMGR_SW_OVERRUN_INT_STATUS 2 2 MCIF_WB_BUFMGR_CUR_BUF 4 6 MCIF_WB_BUF_DUALSIZE_STATUS 7 7 MCIF_WB_BUFMGR_BUFTAG 8 11 MCIF_WB_BUFMGR_CUR_LINE_L 12 24 MCIF_WB_BUFMGR_NEXT_BUF 28 30 mmMCIF_WB0_MCIF_WB_BUF_PITCH 0 0x275 2 0 2 MCIF_WB_BUF_LUMA_PITCH 8 15 MCIF_WB_BUF_CHROMA_PITCH 24 31 mmMCIF_WB0_MCIF_WB_BUF_1_STATUS 0 0x276 13 0 2 MCIF_WB_BUF_1_ACTIVE 0 0 MCIF_WB_BUF_1_SW_LOCKED 1 1 MCIF_WB_BUF_1_VCE_LOCKED 2 2 MCIF_WB_BUF_1_OVERFLOW 3 3 MCIF_WB_BUF_1_DISABLE 4 4 MCIF_WB_BUF_1_MODE 5 7 MCIF_WB_BUF_1_BUFTAG 8 11 MCIF_WB_BUF_1_NXT_BUF 12 14 MCIF_WB_BUF_1_FIELD 15 15 MCIF_WB_BUF_1_CUR_LINE_L 16 28 MCIF_WB_BUF_1_LONG_LINE_ERROR 29 29 MCIF_WB_BUF_1_SHORT_LINE_ERROR 30 30 MCIF_WB_BUF_1_FRAME_LENGTH_ERROR 31 31 mmMCIF_WB0_MCIF_WB_BUF_1_STATUS2 0 0x277 5 0 2 MCIF_WB_BUF_1_CUR_LINE_R 0 12 MCIF_WB_BUF_1_NEW_CONTENT 13 13 MCIF_WB_BUF_1_COLOR_DEPTH 14 14 MCIF_WB_BUF_1_Y_OVERRUN 17 17 MCIF_WB_BUF_1_C_OVERRUN 18 18 mmMCIF_WB0_MCIF_WB_BUF_2_STATUS 0 0x278 13 0 2 MCIF_WB_BUF_2_ACTIVE 0 0 MCIF_WB_BUF_2_SW_LOCKED 1 1 MCIF_WB_BUF_2_VCE_LOCKED 2 2 MCIF_WB_BUF_2_OVERFLOW 3 3 MCIF_WB_BUF_2_DISABLE 4 4 MCIF_WB_BUF_2_MODE 5 7 MCIF_WB_BUF_2_BUFTAG 8 11 MCIF_WB_BUF_2_NXT_BUF 12 14 MCIF_WB_BUF_2_FIELD 15 15 MCIF_WB_BUF_2_CUR_LINE_L 16 28 MCIF_WB_BUF_2_LONG_LINE_ERROR 29 29 MCIF_WB_BUF_2_SHORT_LINE_ERROR 30 30 MCIF_WB_BUF_2_FRAME_LENGTH_ERROR 31 31 mmMCIF_WB0_MCIF_WB_BUF_2_STATUS2 0 0x279 5 0 2 MCIF_WB_BUF_2_CUR_LINE_R 0 12 MCIF_WB_BUF_2_NEW_CONTENT 13 13 MCIF_WB_BUF_2_COLOR_DEPTH 14 14 MCIF_WB_BUF_2_Y_OVERRUN 17 17 MCIF_WB_BUF_2_C_OVERRUN 18 18 mmMCIF_WB0_MCIF_WB_BUF_3_STATUS 0 0x27a 13 0 2 MCIF_WB_BUF_3_ACTIVE 0 0 MCIF_WB_BUF_3_SW_LOCKED 1 1 MCIF_WB_BUF_3_VCE_LOCKED 2 2 MCIF_WB_BUF_3_OVERFLOW 3 3 MCIF_WB_BUF_3_DISABLE 4 4 MCIF_WB_BUF_3_MODE 5 7 MCIF_WB_BUF_3_BUFTAG 8 11 MCIF_WB_BUF_3_NXT_BUF 12 14 MCIF_WB_BUF_3_FIELD 15 15 MCIF_WB_BUF_3_CUR_LINE_L 16 28 MCIF_WB_BUF_3_LONG_LINE_ERROR 29 29 MCIF_WB_BUF_3_SHORT_LINE_ERROR 30 30 MCIF_WB_BUF_3_FRAME_LENGTH_ERROR 31 31 mmMCIF_WB0_MCIF_WB_BUF_3_STATUS2 0 0x27b 5 0 2 MCIF_WB_BUF_3_CUR_LINE_R 0 12 MCIF_WB_BUF_3_NEW_CONTENT 13 13 MCIF_WB_BUF_3_COLOR_DEPTH 14 14 MCIF_WB_BUF_3_Y_OVERRUN 17 17 MCIF_WB_BUF_3_C_OVERRUN 18 18 mmMCIF_WB0_MCIF_WB_BUF_4_STATUS 0 0x27c 13 0 2 MCIF_WB_BUF_4_ACTIVE 0 0 MCIF_WB_BUF_4_SW_LOCKED 1 1 MCIF_WB_BUF_4_VCE_LOCKED 2 2 MCIF_WB_BUF_4_OVERFLOW 3 3 MCIF_WB_BUF_4_DISABLE 4 4 MCIF_WB_BUF_4_MODE 5 7 MCIF_WB_BUF_4_BUFTAG 8 11 MCIF_WB_BUF_4_NXT_BUF 12 14 MCIF_WB_BUF_4_FIELD 15 15 MCIF_WB_BUF_4_CUR_LINE_L 16 28 MCIF_WB_BUF_4_LONG_LINE_ERROR 29 29 MCIF_WB_BUF_4_SHORT_LINE_ERROR 30 30 MCIF_WB_BUF_4_FRAME_LENGTH_ERROR 31 31 mmMCIF_WB0_MCIF_WB_BUF_4_STATUS2 0 0x27d 5 0 2 MCIF_WB_BUF_4_CUR_LINE_R 0 12 MCIF_WB_BUF_4_NEW_CONTENT 13 13 MCIF_WB_BUF_4_COLOR_DEPTH 14 14 MCIF_WB_BUF_4_Y_OVERRUN 17 17 MCIF_WB_BUF_4_C_OVERRUN 18 18 mmMCIF_WB0_MCIF_WB_ARBITRATION_CONTROL 0 0x27e 2 0 2 MCIF_WB_CLIENT_ARBITRATION_SLICE 0 1 MCIF_WB_TIME_PER_PIXEL 22 31 mmMCIF_WB0_MCIF_WB_SCLK_CHANGE 0 0x27f 2 0 2 WM_CHANGE_ACK_FORCE_ON 0 0 MCIF_WB_CLI_WATERMARK_MASK 1 3 mmMCIF_WB0_MCIF_WB_BUF_1_ADDR_Y 0 0x282 1 0 2 MCIF_WB_BUF_1_ADDR_Y 0 31 mmMCIF_WB0_MCIF_WB_BUF_1_ADDR_Y_OFFSET 0 0x283 1 0 2 MCIF_WB_BUF_1_ADDR_Y_OFFSET 0 17 mmMCIF_WB0_MCIF_WB_BUF_1_ADDR_C 0 0x284 1 0 2 MCIF_WB_BUF_1_ADDR_C 0 31 mmMCIF_WB0_MCIF_WB_BUF_1_ADDR_C_OFFSET 0 0x285 1 0 2 MCIF_WB_BUF_1_ADDR_C_OFFSET 0 17 mmMCIF_WB0_MCIF_WB_BUF_2_ADDR_Y 0 0x286 1 0 2 MCIF_WB_BUF_2_ADDR_Y 0 31 mmMCIF_WB0_MCIF_WB_BUF_2_ADDR_Y_OFFSET 0 0x287 1 0 2 MCIF_WB_BUF_2_ADDR_Y_OFFSET 0 17 mmMCIF_WB0_MCIF_WB_BUF_2_ADDR_C 0 0x288 1 0 2 MCIF_WB_BUF_2_ADDR_C 0 31 mmMCIF_WB0_MCIF_WB_BUF_2_ADDR_C_OFFSET 0 0x289 1 0 2 MCIF_WB_BUF_2_ADDR_C_OFFSET 0 17 mmMCIF_WB0_MCIF_WB_BUF_3_ADDR_Y 0 0x28a 1 0 2 MCIF_WB_BUF_3_ADDR_Y 0 31 mmMCIF_WB0_MCIF_WB_BUF_3_ADDR_Y_OFFSET 0 0x28b 1 0 2 MCIF_WB_BUF_3_ADDR_Y_OFFSET 0 17 mmMCIF_WB0_MCIF_WB_BUF_3_ADDR_C 0 0x28c 1 0 2 MCIF_WB_BUF_3_ADDR_C 0 31 mmMCIF_WB0_MCIF_WB_BUF_3_ADDR_C_OFFSET 0 0x28d 1 0 2 MCIF_WB_BUF_3_ADDR_C_OFFSET 0 17 mmMCIF_WB0_MCIF_WB_BUF_4_ADDR_Y 0 0x28e 1 0 2 MCIF_WB_BUF_4_ADDR_Y 0 31 mmMCIF_WB0_MCIF_WB_BUF_4_ADDR_Y_OFFSET 0 0x28f 1 0 2 MCIF_WB_BUF_4_ADDR_Y_OFFSET 0 17 mmMCIF_WB0_MCIF_WB_BUF_4_ADDR_C 0 0x290 1 0 2 MCIF_WB_BUF_4_ADDR_C 0 31 mmMCIF_WB0_MCIF_WB_BUF_4_ADDR_C_OFFSET 0 0x291 1 0 2 MCIF_WB_BUF_4_ADDR_C_OFFSET 0 17 mmMCIF_WB0_MCIF_WB_BUFMGR_VCE_CONTROL 0 0x292 6 0 2 MCIF_WB_BUFMGR_VCE_LOCK_IGNORE 0 0 MCIF_WB_BUFMGR_VCE_INT_EN 4 4 MCIF_WB_BUFMGR_VCE_INT_ACK 5 5 MCIF_WB_BUFMGR_VCE_SLICE_INT_EN 6 6 MCIF_WB_BUFMGR_VCE_LOCK 8 11 MCIF_WB_BUFMGR_SLICE_SIZE 16 28 mmMCIF_WB0_MCIF_WB_NB_PSTATE_LATENCY_WATERMARK 0 0x293 1 0 2 NB_PSTATE_CHANGE_REFRESH_WATERMARK 0 16 mmMCIF_WB0_MCIF_WB_NB_PSTATE_CONTROL 0 0x294 4 0 2 NB_PSTATE_CHANGE_URGENT_DURING_REQUEST 0 0 NB_PSTATE_CHANGE_FORCE_ON 1 1 NB_PSTATE_ALLOW_FOR_URGENT 2 2 NB_PSTATE_CHANGE_WATERMARK_MASK 4 6 mmMCIF_WB0_MCIF_WB_WATERMARK 0 0x295 1 0 2 MCIF_WB_CLI_WATERMARK 0 15 mmMCIF_WB0_MCIF_WB_CLOCK_GATER_CONTROL 0 0x296 1 0 2 MCIF_WB_CLI_CLOCK_GATER_OVERRIDE 0 0 mmMCIF_WB0_MCIF_WB_WARM_UP_CNTL 0 0x297 1 0 2 MCIF_WB_PITCH_SIZE_WARMUP 8 15 mmMCIF_WB0_MCIF_WB_SELF_REFRESH_CONTROL 0 0x298 2 0 2 DIS_REFRESH_UNDER_NBPREQ 0 0 PERFRAME_SELF_REFRESH 1 1 mmMCIF_WB0_MULTI_LEVEL_QOS_CTRL 0 0x299 1 0 2 MAX_SCALED_TIME_TO_URGENT 0 21 mmMCIF_WB0_MCIF_WB_BUF_LUMA_SIZE 0 0x29b 1 0 2 MCIF_WB_BUF_LUMA_SIZE 0 19 mmMCIF_WB0_MCIF_WB_BUF_CHROMA_SIZE 0 0x29c 1 0 2 MCIF_WB_BUF_CHROMA_SIZE 0 19 mmMCIF_WB1_MCIF_WB_BUFMGR_SW_CONTROL 0 0x2b2 9 0 2 MCIF_WB_BUFMGR_ENABLE 0 0 MCIF_WB_BUF_DUALSIZE_REQ 1 1 MCIF_WB_BUFMGR_SW_INT_EN 4 4 MCIF_WB_BUFMGR_SW_INT_ACK 5 5 MCIF_WB_BUFMGR_SW_SLICE_INT_EN 6 6 MCIF_WB_BUFMGR_SW_OVERRUN_INT_EN 7 7 MCIF_WB_BUFMGR_SW_LOCK 8 11 MCIF_WB_P_VMID 16 19 MCIF_WB_BUF_ADDR_FENCE_EN 24 24 mmMCIF_WB1_MCIF_WB_BUFMGR_CUR_LINE_R 0 0x2b3 1 0 2 MCIF_WB_BUFMGR_CUR_LINE_R 0 12 mmMCIF_WB1_MCIF_WB_BUFMGR_STATUS 0 0x2b4 8 0 2 MCIF_WB_BUFMGR_VCE_INT_STATUS 0 0 MCIF_WB_BUFMGR_SW_INT_STATUS 1 1 MCIF_WB_BUFMGR_SW_OVERRUN_INT_STATUS 2 2 MCIF_WB_BUFMGR_CUR_BUF 4 6 MCIF_WB_BUF_DUALSIZE_STATUS 7 7 MCIF_WB_BUFMGR_BUFTAG 8 11 MCIF_WB_BUFMGR_CUR_LINE_L 12 24 MCIF_WB_BUFMGR_NEXT_BUF 28 30 mmMCIF_WB1_MCIF_WB_BUF_PITCH 0 0x2b5 2 0 2 MCIF_WB_BUF_LUMA_PITCH 8 15 MCIF_WB_BUF_CHROMA_PITCH 24 31 mmMCIF_WB1_MCIF_WB_BUF_1_STATUS 0 0x2b6 13 0 2 MCIF_WB_BUF_1_ACTIVE 0 0 MCIF_WB_BUF_1_SW_LOCKED 1 1 MCIF_WB_BUF_1_VCE_LOCKED 2 2 MCIF_WB_BUF_1_OVERFLOW 3 3 MCIF_WB_BUF_1_DISABLE 4 4 MCIF_WB_BUF_1_MODE 5 7 MCIF_WB_BUF_1_BUFTAG 8 11 MCIF_WB_BUF_1_NXT_BUF 12 14 MCIF_WB_BUF_1_FIELD 15 15 MCIF_WB_BUF_1_CUR_LINE_L 16 28 MCIF_WB_BUF_1_LONG_LINE_ERROR 29 29 MCIF_WB_BUF_1_SHORT_LINE_ERROR 30 30 MCIF_WB_BUF_1_FRAME_LENGTH_ERROR 31 31 mmMCIF_WB1_MCIF_WB_BUF_1_STATUS2 0 0x2b7 5 0 2 MCIF_WB_BUF_1_CUR_LINE_R 0 12 MCIF_WB_BUF_1_NEW_CONTENT 13 13 MCIF_WB_BUF_1_COLOR_DEPTH 14 14 MCIF_WB_BUF_1_Y_OVERRUN 17 17 MCIF_WB_BUF_1_C_OVERRUN 18 18 mmMCIF_WB1_MCIF_WB_BUF_2_STATUS 0 0x2b8 13 0 2 MCIF_WB_BUF_2_ACTIVE 0 0 MCIF_WB_BUF_2_SW_LOCKED 1 1 MCIF_WB_BUF_2_VCE_LOCKED 2 2 MCIF_WB_BUF_2_OVERFLOW 3 3 MCIF_WB_BUF_2_DISABLE 4 4 MCIF_WB_BUF_2_MODE 5 7 MCIF_WB_BUF_2_BUFTAG 8 11 MCIF_WB_BUF_2_NXT_BUF 12 14 MCIF_WB_BUF_2_FIELD 15 15 MCIF_WB_BUF_2_CUR_LINE_L 16 28 MCIF_WB_BUF_2_LONG_LINE_ERROR 29 29 MCIF_WB_BUF_2_SHORT_LINE_ERROR 30 30 MCIF_WB_BUF_2_FRAME_LENGTH_ERROR 31 31 mmMCIF_WB1_MCIF_WB_BUF_2_STATUS2 0 0x2b9 5 0 2 MCIF_WB_BUF_2_CUR_LINE_R 0 12 MCIF_WB_BUF_2_NEW_CONTENT 13 13 MCIF_WB_BUF_2_COLOR_DEPTH 14 14 MCIF_WB_BUF_2_Y_OVERRUN 17 17 MCIF_WB_BUF_2_C_OVERRUN 18 18 mmMCIF_WB1_MCIF_WB_BUF_3_STATUS 0 0x2ba 13 0 2 MCIF_WB_BUF_3_ACTIVE 0 0 MCIF_WB_BUF_3_SW_LOCKED 1 1 MCIF_WB_BUF_3_VCE_LOCKED 2 2 MCIF_WB_BUF_3_OVERFLOW 3 3 MCIF_WB_BUF_3_DISABLE 4 4 MCIF_WB_BUF_3_MODE 5 7 MCIF_WB_BUF_3_BUFTAG 8 11 MCIF_WB_BUF_3_NXT_BUF 12 14 MCIF_WB_BUF_3_FIELD 15 15 MCIF_WB_BUF_3_CUR_LINE_L 16 28 MCIF_WB_BUF_3_LONG_LINE_ERROR 29 29 MCIF_WB_BUF_3_SHORT_LINE_ERROR 30 30 MCIF_WB_BUF_3_FRAME_LENGTH_ERROR 31 31 mmMCIF_WB1_MCIF_WB_BUF_3_STATUS2 0 0x2bb 5 0 2 MCIF_WB_BUF_3_CUR_LINE_R 0 12 MCIF_WB_BUF_3_NEW_CONTENT 13 13 MCIF_WB_BUF_3_COLOR_DEPTH 14 14 MCIF_WB_BUF_3_Y_OVERRUN 17 17 MCIF_WB_BUF_3_C_OVERRUN 18 18 mmMCIF_WB1_MCIF_WB_BUF_4_STATUS 0 0x2bc 13 0 2 MCIF_WB_BUF_4_ACTIVE 0 0 MCIF_WB_BUF_4_SW_LOCKED 1 1 MCIF_WB_BUF_4_VCE_LOCKED 2 2 MCIF_WB_BUF_4_OVERFLOW 3 3 MCIF_WB_BUF_4_DISABLE 4 4 MCIF_WB_BUF_4_MODE 5 7 MCIF_WB_BUF_4_BUFTAG 8 11 MCIF_WB_BUF_4_NXT_BUF 12 14 MCIF_WB_BUF_4_FIELD 15 15 MCIF_WB_BUF_4_CUR_LINE_L 16 28 MCIF_WB_BUF_4_LONG_LINE_ERROR 29 29 MCIF_WB_BUF_4_SHORT_LINE_ERROR 30 30 MCIF_WB_BUF_4_FRAME_LENGTH_ERROR 31 31 mmMCIF_WB1_MCIF_WB_BUF_4_STATUS2 0 0x2bd 5 0 2 MCIF_WB_BUF_4_CUR_LINE_R 0 12 MCIF_WB_BUF_4_NEW_CONTENT 13 13 MCIF_WB_BUF_4_COLOR_DEPTH 14 14 MCIF_WB_BUF_4_Y_OVERRUN 17 17 MCIF_WB_BUF_4_C_OVERRUN 18 18 mmMCIF_WB1_MCIF_WB_ARBITRATION_CONTROL 0 0x2be 2 0 2 MCIF_WB_CLIENT_ARBITRATION_SLICE 0 1 MCIF_WB_TIME_PER_PIXEL 22 31 mmMCIF_WB1_MCIF_WB_SCLK_CHANGE 0 0x2bf 2 0 2 WM_CHANGE_ACK_FORCE_ON 0 0 MCIF_WB_CLI_WATERMARK_MASK 1 3 mmMCIF_WB1_MCIF_WB_BUF_1_ADDR_Y 0 0x2c2 1 0 2 MCIF_WB_BUF_1_ADDR_Y 0 31 mmMCIF_WB1_MCIF_WB_BUF_1_ADDR_Y_OFFSET 0 0x2c3 1 0 2 MCIF_WB_BUF_1_ADDR_Y_OFFSET 0 17 mmMCIF_WB1_MCIF_WB_BUF_1_ADDR_C 0 0x2c4 1 0 2 MCIF_WB_BUF_1_ADDR_C 0 31 mmMCIF_WB1_MCIF_WB_BUF_1_ADDR_C_OFFSET 0 0x2c5 1 0 2 MCIF_WB_BUF_1_ADDR_C_OFFSET 0 17 mmMCIF_WB1_MCIF_WB_BUF_2_ADDR_Y 0 0x2c6 1 0 2 MCIF_WB_BUF_2_ADDR_Y 0 31 mmMCIF_WB1_MCIF_WB_BUF_2_ADDR_Y_OFFSET 0 0x2c7 1 0 2 MCIF_WB_BUF_2_ADDR_Y_OFFSET 0 17 mmMCIF_WB1_MCIF_WB_BUF_2_ADDR_C 0 0x2c8 1 0 2 MCIF_WB_BUF_2_ADDR_C 0 31 mmMCIF_WB1_MCIF_WB_BUF_2_ADDR_C_OFFSET 0 0x2c9 1 0 2 MCIF_WB_BUF_2_ADDR_C_OFFSET 0 17 mmMCIF_WB1_MCIF_WB_BUF_3_ADDR_Y 0 0x2ca 1 0 2 MCIF_WB_BUF_3_ADDR_Y 0 31 mmMCIF_WB1_MCIF_WB_BUF_3_ADDR_Y_OFFSET 0 0x2cb 1 0 2 MCIF_WB_BUF_3_ADDR_Y_OFFSET 0 17 mmMCIF_WB1_MCIF_WB_BUF_3_ADDR_C 0 0x2cc 1 0 2 MCIF_WB_BUF_3_ADDR_C 0 31 mmMCIF_WB1_MCIF_WB_BUF_3_ADDR_C_OFFSET 0 0x2cd 1 0 2 MCIF_WB_BUF_3_ADDR_C_OFFSET 0 17 mmMCIF_WB1_MCIF_WB_BUF_4_ADDR_Y 0 0x2ce 1 0 2 MCIF_WB_BUF_4_ADDR_Y 0 31 mmMCIF_WB1_MCIF_WB_BUF_4_ADDR_Y_OFFSET 0 0x2cf 1 0 2 MCIF_WB_BUF_4_ADDR_Y_OFFSET 0 17 mmMCIF_WB1_MCIF_WB_BUF_4_ADDR_C 0 0x2d0 1 0 2 MCIF_WB_BUF_4_ADDR_C 0 31 mmMCIF_WB1_MCIF_WB_BUF_4_ADDR_C_OFFSET 0 0x2d1 1 0 2 MCIF_WB_BUF_4_ADDR_C_OFFSET 0 17 mmMCIF_WB1_MCIF_WB_BUFMGR_VCE_CONTROL 0 0x2d2 6 0 2 MCIF_WB_BUFMGR_VCE_LOCK_IGNORE 0 0 MCIF_WB_BUFMGR_VCE_INT_EN 4 4 MCIF_WB_BUFMGR_VCE_INT_ACK 5 5 MCIF_WB_BUFMGR_VCE_SLICE_INT_EN 6 6 MCIF_WB_BUFMGR_VCE_LOCK 8 11 MCIF_WB_BUFMGR_SLICE_SIZE 16 28 mmMCIF_WB1_MCIF_WB_NB_PSTATE_LATENCY_WATERMARK 0 0x2d3 1 0 2 NB_PSTATE_CHANGE_REFRESH_WATERMARK 0 16 mmMCIF_WB1_MCIF_WB_NB_PSTATE_CONTROL 0 0x2d4 4 0 2 NB_PSTATE_CHANGE_URGENT_DURING_REQUEST 0 0 NB_PSTATE_CHANGE_FORCE_ON 1 1 NB_PSTATE_ALLOW_FOR_URGENT 2 2 NB_PSTATE_CHANGE_WATERMARK_MASK 4 6 mmMCIF_WB1_MCIF_WB_WATERMARK 0 0x2d5 1 0 2 MCIF_WB_CLI_WATERMARK 0 15 mmMCIF_WB1_MCIF_WB_CLOCK_GATER_CONTROL 0 0x2d6 1 0 2 MCIF_WB_CLI_CLOCK_GATER_OVERRIDE 0 0 mmMCIF_WB1_MCIF_WB_WARM_UP_CNTL 0 0x2d7 1 0 2 MCIF_WB_PITCH_SIZE_WARMUP 8 15 mmMCIF_WB1_MCIF_WB_SELF_REFRESH_CONTROL 0 0x2d8 2 0 2 DIS_REFRESH_UNDER_NBPREQ 0 0 PERFRAME_SELF_REFRESH 1 1 mmMCIF_WB1_MULTI_LEVEL_QOS_CTRL 0 0x2d9 1 0 2 MAX_SCALED_TIME_TO_URGENT 0 21 mmMCIF_WB1_MCIF_WB_BUF_LUMA_SIZE 0 0x2db 1 0 2 MCIF_WB_BUF_LUMA_SIZE 0 19 mmMCIF_WB1_MCIF_WB_BUF_CHROMA_SIZE 0 0x2dc 1 0 2 MCIF_WB_BUF_CHROMA_SIZE 0 19 mmMCIF_WB2_MCIF_WB_BUFMGR_SW_CONTROL 0 0x2f2 9 0 2 MCIF_WB_BUFMGR_ENABLE 0 0 MCIF_WB_BUF_DUALSIZE_REQ 1 1 MCIF_WB_BUFMGR_SW_INT_EN 4 4 MCIF_WB_BUFMGR_SW_INT_ACK 5 5 MCIF_WB_BUFMGR_SW_SLICE_INT_EN 6 6 MCIF_WB_BUFMGR_SW_OVERRUN_INT_EN 7 7 MCIF_WB_BUFMGR_SW_LOCK 8 11 MCIF_WB_P_VMID 16 19 MCIF_WB_BUF_ADDR_FENCE_EN 24 24 mmMCIF_WB2_MCIF_WB_BUFMGR_CUR_LINE_R 0 0x2f3 1 0 2 MCIF_WB_BUFMGR_CUR_LINE_R 0 12 mmMCIF_WB2_MCIF_WB_BUFMGR_STATUS 0 0x2f4 8 0 2 MCIF_WB_BUFMGR_VCE_INT_STATUS 0 0 MCIF_WB_BUFMGR_SW_INT_STATUS 1 1 MCIF_WB_BUFMGR_SW_OVERRUN_INT_STATUS 2 2 MCIF_WB_BUFMGR_CUR_BUF 4 6 MCIF_WB_BUF_DUALSIZE_STATUS 7 7 MCIF_WB_BUFMGR_BUFTAG 8 11 MCIF_WB_BUFMGR_CUR_LINE_L 12 24 MCIF_WB_BUFMGR_NEXT_BUF 28 30 mmMCIF_WB2_MCIF_WB_BUF_PITCH 0 0x2f5 2 0 2 MCIF_WB_BUF_LUMA_PITCH 8 15 MCIF_WB_BUF_CHROMA_PITCH 24 31 mmMCIF_WB2_MCIF_WB_BUF_1_STATUS 0 0x2f6 13 0 2 MCIF_WB_BUF_1_ACTIVE 0 0 MCIF_WB_BUF_1_SW_LOCKED 1 1 MCIF_WB_BUF_1_VCE_LOCKED 2 2 MCIF_WB_BUF_1_OVERFLOW 3 3 MCIF_WB_BUF_1_DISABLE 4 4 MCIF_WB_BUF_1_MODE 5 7 MCIF_WB_BUF_1_BUFTAG 8 11 MCIF_WB_BUF_1_NXT_BUF 12 14 MCIF_WB_BUF_1_FIELD 15 15 MCIF_WB_BUF_1_CUR_LINE_L 16 28 MCIF_WB_BUF_1_LONG_LINE_ERROR 29 29 MCIF_WB_BUF_1_SHORT_LINE_ERROR 30 30 MCIF_WB_BUF_1_FRAME_LENGTH_ERROR 31 31 mmMCIF_WB2_MCIF_WB_BUF_1_STATUS2 0 0x2f7 5 0 2 MCIF_WB_BUF_1_CUR_LINE_R 0 12 MCIF_WB_BUF_1_NEW_CONTENT 13 13 MCIF_WB_BUF_1_COLOR_DEPTH 14 14 MCIF_WB_BUF_1_Y_OVERRUN 17 17 MCIF_WB_BUF_1_C_OVERRUN 18 18 mmMCIF_WB2_MCIF_WB_BUF_2_STATUS 0 0x2f8 13 0 2 MCIF_WB_BUF_2_ACTIVE 0 0 MCIF_WB_BUF_2_SW_LOCKED 1 1 MCIF_WB_BUF_2_VCE_LOCKED 2 2 MCIF_WB_BUF_2_OVERFLOW 3 3 MCIF_WB_BUF_2_DISABLE 4 4 MCIF_WB_BUF_2_MODE 5 7 MCIF_WB_BUF_2_BUFTAG 8 11 MCIF_WB_BUF_2_NXT_BUF 12 14 MCIF_WB_BUF_2_FIELD 15 15 MCIF_WB_BUF_2_CUR_LINE_L 16 28 MCIF_WB_BUF_2_LONG_LINE_ERROR 29 29 MCIF_WB_BUF_2_SHORT_LINE_ERROR 30 30 MCIF_WB_BUF_2_FRAME_LENGTH_ERROR 31 31 mmMCIF_WB2_MCIF_WB_BUF_2_STATUS2 0 0x2f9 5 0 2 MCIF_WB_BUF_2_CUR_LINE_R 0 12 MCIF_WB_BUF_2_NEW_CONTENT 13 13 MCIF_WB_BUF_2_COLOR_DEPTH 14 14 MCIF_WB_BUF_2_Y_OVERRUN 17 17 MCIF_WB_BUF_2_C_OVERRUN 18 18 mmMCIF_WB2_MCIF_WB_BUF_3_STATUS 0 0x2fa 13 0 2 MCIF_WB_BUF_3_ACTIVE 0 0 MCIF_WB_BUF_3_SW_LOCKED 1 1 MCIF_WB_BUF_3_VCE_LOCKED 2 2 MCIF_WB_BUF_3_OVERFLOW 3 3 MCIF_WB_BUF_3_DISABLE 4 4 MCIF_WB_BUF_3_MODE 5 7 MCIF_WB_BUF_3_BUFTAG 8 11 MCIF_WB_BUF_3_NXT_BUF 12 14 MCIF_WB_BUF_3_FIELD 15 15 MCIF_WB_BUF_3_CUR_LINE_L 16 28 MCIF_WB_BUF_3_LONG_LINE_ERROR 29 29 MCIF_WB_BUF_3_SHORT_LINE_ERROR 30 30 MCIF_WB_BUF_3_FRAME_LENGTH_ERROR 31 31 mmMCIF_WB2_MCIF_WB_BUF_3_STATUS2 0 0x2fb 5 0 2 MCIF_WB_BUF_3_CUR_LINE_R 0 12 MCIF_WB_BUF_3_NEW_CONTENT 13 13 MCIF_WB_BUF_3_COLOR_DEPTH 14 14 MCIF_WB_BUF_3_Y_OVERRUN 17 17 MCIF_WB_BUF_3_C_OVERRUN 18 18 mmMCIF_WB2_MCIF_WB_BUF_4_STATUS 0 0x2fc 13 0 2 MCIF_WB_BUF_4_ACTIVE 0 0 MCIF_WB_BUF_4_SW_LOCKED 1 1 MCIF_WB_BUF_4_VCE_LOCKED 2 2 MCIF_WB_BUF_4_OVERFLOW 3 3 MCIF_WB_BUF_4_DISABLE 4 4 MCIF_WB_BUF_4_MODE 5 7 MCIF_WB_BUF_4_BUFTAG 8 11 MCIF_WB_BUF_4_NXT_BUF 12 14 MCIF_WB_BUF_4_FIELD 15 15 MCIF_WB_BUF_4_CUR_LINE_L 16 28 MCIF_WB_BUF_4_LONG_LINE_ERROR 29 29 MCIF_WB_BUF_4_SHORT_LINE_ERROR 30 30 MCIF_WB_BUF_4_FRAME_LENGTH_ERROR 31 31 mmMCIF_WB2_MCIF_WB_BUF_4_STATUS2 0 0x2fd 5 0 2 MCIF_WB_BUF_4_CUR_LINE_R 0 12 MCIF_WB_BUF_4_NEW_CONTENT 13 13 MCIF_WB_BUF_4_COLOR_DEPTH 14 14 MCIF_WB_BUF_4_Y_OVERRUN 17 17 MCIF_WB_BUF_4_C_OVERRUN 18 18 mmMCIF_WB2_MCIF_WB_ARBITRATION_CONTROL 0 0x2fe 2 0 2 MCIF_WB_CLIENT_ARBITRATION_SLICE 0 1 MCIF_WB_TIME_PER_PIXEL 22 31 mmMCIF_WB2_MCIF_WB_SCLK_CHANGE 0 0x2ff 2 0 2 WM_CHANGE_ACK_FORCE_ON 0 0 MCIF_WB_CLI_WATERMARK_MASK 1 3 mmMCIF_WB2_MCIF_WB_BUF_1_ADDR_Y 0 0x302 1 0 2 MCIF_WB_BUF_1_ADDR_Y 0 31 mmMCIF_WB2_MCIF_WB_BUF_1_ADDR_Y_OFFSET 0 0x303 1 0 2 MCIF_WB_BUF_1_ADDR_Y_OFFSET 0 17 mmMCIF_WB2_MCIF_WB_BUF_1_ADDR_C 0 0x304 1 0 2 MCIF_WB_BUF_1_ADDR_C 0 31 mmMCIF_WB2_MCIF_WB_BUF_1_ADDR_C_OFFSET 0 0x305 1 0 2 MCIF_WB_BUF_1_ADDR_C_OFFSET 0 17 mmMCIF_WB2_MCIF_WB_BUF_2_ADDR_Y 0 0x306 1 0 2 MCIF_WB_BUF_2_ADDR_Y 0 31 mmMCIF_WB2_MCIF_WB_BUF_2_ADDR_Y_OFFSET 0 0x307 1 0 2 MCIF_WB_BUF_2_ADDR_Y_OFFSET 0 17 mmMCIF_WB2_MCIF_WB_BUF_2_ADDR_C 0 0x308 1 0 2 MCIF_WB_BUF_2_ADDR_C 0 31 mmMCIF_WB2_MCIF_WB_BUF_2_ADDR_C_OFFSET 0 0x309 1 0 2 MCIF_WB_BUF_2_ADDR_C_OFFSET 0 17 mmMCIF_WB2_MCIF_WB_BUF_3_ADDR_Y 0 0x30a 1 0 2 MCIF_WB_BUF_3_ADDR_Y 0 31 mmMCIF_WB2_MCIF_WB_BUF_3_ADDR_Y_OFFSET 0 0x30b 1 0 2 MCIF_WB_BUF_3_ADDR_Y_OFFSET 0 17 mmMCIF_WB2_MCIF_WB_BUF_3_ADDR_C 0 0x30c 1 0 2 MCIF_WB_BUF_3_ADDR_C 0 31 mmMCIF_WB2_MCIF_WB_BUF_3_ADDR_C_OFFSET 0 0x30d 1 0 2 MCIF_WB_BUF_3_ADDR_C_OFFSET 0 17 mmMCIF_WB2_MCIF_WB_BUF_4_ADDR_Y 0 0x30e 1 0 2 MCIF_WB_BUF_4_ADDR_Y 0 31 mmMCIF_WB2_MCIF_WB_BUF_4_ADDR_Y_OFFSET 0 0x30f 1 0 2 MCIF_WB_BUF_4_ADDR_Y_OFFSET 0 17 mmMCIF_WB2_MCIF_WB_BUF_4_ADDR_C 0 0x310 1 0 2 MCIF_WB_BUF_4_ADDR_C 0 31 mmMCIF_WB2_MCIF_WB_BUF_4_ADDR_C_OFFSET 0 0x311 1 0 2 MCIF_WB_BUF_4_ADDR_C_OFFSET 0 17 mmMCIF_WB2_MCIF_WB_BUFMGR_VCE_CONTROL 0 0x312 6 0 2 MCIF_WB_BUFMGR_VCE_LOCK_IGNORE 0 0 MCIF_WB_BUFMGR_VCE_INT_EN 4 4 MCIF_WB_BUFMGR_VCE_INT_ACK 5 5 MCIF_WB_BUFMGR_VCE_SLICE_INT_EN 6 6 MCIF_WB_BUFMGR_VCE_LOCK 8 11 MCIF_WB_BUFMGR_SLICE_SIZE 16 28 mmMCIF_WB2_MCIF_WB_NB_PSTATE_LATENCY_WATERMARK 0 0x313 1 0 2 NB_PSTATE_CHANGE_REFRESH_WATERMARK 0 16 mmMCIF_WB2_MCIF_WB_NB_PSTATE_CONTROL 0 0x314 4 0 2 NB_PSTATE_CHANGE_URGENT_DURING_REQUEST 0 0 NB_PSTATE_CHANGE_FORCE_ON 1 1 NB_PSTATE_ALLOW_FOR_URGENT 2 2 NB_PSTATE_CHANGE_WATERMARK_MASK 4 6 mmMCIF_WB2_MCIF_WB_WATERMARK 0 0x315 1 0 2 MCIF_WB_CLI_WATERMARK 0 15 mmMCIF_WB2_MCIF_WB_CLOCK_GATER_CONTROL 0 0x316 1 0 2 MCIF_WB_CLI_CLOCK_GATER_OVERRIDE 0 0 mmMCIF_WB2_MCIF_WB_WARM_UP_CNTL 0 0x317 1 0 2 MCIF_WB_PITCH_SIZE_WARMUP 8 15 mmMCIF_WB2_MCIF_WB_SELF_REFRESH_CONTROL 0 0x318 2 0 2 DIS_REFRESH_UNDER_NBPREQ 0 0 PERFRAME_SELF_REFRESH 1 1 mmMCIF_WB2_MULTI_LEVEL_QOS_CTRL 0 0x319 1 0 2 MAX_SCALED_TIME_TO_URGENT 0 21 mmMCIF_WB2_MCIF_WB_BUF_LUMA_SIZE 0 0x31b 1 0 2 MCIF_WB_BUF_LUMA_SIZE 0 19 mmMCIF_WB2_MCIF_WB_BUF_CHROMA_SIZE 0 0x31c 1 0 2 MCIF_WB_BUF_CHROMA_SIZE 0 19 mmCWB0_CWB_CTRL 0 0x332 7 0 2 CWB_EN 0 0 CWB_OUTPUT_COLOR_DEPTH 2 3 CWB_ZERO_PADDING_MODE 4 4 CWB_CB_CR_SWAP 6 6 CWB_422MODE_LUMA_CHROMA_SWAP 7 7 CWB_444MODE_ROUNDING_EN 8 8 CWB_PACK_FMT_SEL 10 10 mmCWB0_CWB_FENCE_PAR0 0 0x334 2 0 2 CWB_OUTPUT_LINE_WIDTH 0 12 CWB_ERROR_LINE_WIDTH 16 28 mmCWB0_CWB_FENCE_PAR1 0 0x335 2 0 2 CWB_OUTPUT_LINES_PER_FRAME 0 12 CWB_EOF_TO_SOF_SPACING 16 21 mmCWB0_CWB_CRC_CTRL 0 0x339 3 0 2 CWB_CRC_EN 0 0 CWB_CRC_CONT_EN 2 2 CWB_CRC_SRC_SEL 6 6 mmCWB0_CWB_CRC_RED_GREEN_MASK 0 0x33a 2 0 2 CWB_CRC_RED_MASK 0 15 CWB_CRC_GREEN_MASK 16 31 mmCWB0_CWB_CRC_BLUE_MASK 0 0x33b 1 0 2 CWB_CRC_BLUE_MASK 0 15 mmCWB0_CWB_CRC_RED_GREEN_RESULT 0 0x33c 2 0 2 CWB_CRC_RED_RESULT 0 15 CWB_CRC_GREEN_RESULT 16 31 mmCWB0_CWB_CRC_BLUE_RESULT 0 0x33d 2 0 2 CWB_CRC_BLUE_RESULT 0 15 CWB_CRC_COUNT 16 19 mmCWB1_CWB_CTRL 0 0x34a 7 0 2 CWB_EN 0 0 CWB_OUTPUT_COLOR_DEPTH 2 3 CWB_ZERO_PADDING_MODE 4 4 CWB_CB_CR_SWAP 6 6 CWB_422MODE_LUMA_CHROMA_SWAP 7 7 CWB_444MODE_ROUNDING_EN 8 8 CWB_PACK_FMT_SEL 10 10 mmCWB1_CWB_FENCE_PAR0 0 0x34c 2 0 2 CWB_OUTPUT_LINE_WIDTH 0 12 CWB_ERROR_LINE_WIDTH 16 28 mmCWB1_CWB_FENCE_PAR1 0 0x34d 2 0 2 CWB_OUTPUT_LINES_PER_FRAME 0 12 CWB_EOF_TO_SOF_SPACING 16 21 mmCWB1_CWB_CRC_CTRL 0 0x351 3 0 2 CWB_CRC_EN 0 0 CWB_CRC_CONT_EN 2 2 CWB_CRC_SRC_SEL 6 6 mmCWB1_CWB_CRC_RED_GREEN_MASK 0 0x352 2 0 2 CWB_CRC_RED_MASK 0 15 CWB_CRC_GREEN_MASK 16 31 mmCWB1_CWB_CRC_BLUE_MASK 0 0x353 1 0 2 CWB_CRC_BLUE_MASK 0 15 mmCWB1_CWB_CRC_RED_GREEN_RESULT 0 0x354 2 0 2 CWB_CRC_RED_RESULT 0 15 CWB_CRC_GREEN_RESULT 16 31 mmCWB1_CWB_CRC_BLUE_RESULT 0 0x355 2 0 2 CWB_CRC_BLUE_RESULT 0 15 CWB_CRC_COUNT 16 19 mmDC_PERFMON9_PERFCOUNTER_CNTL 0 0x362 13 0 2 PERFCOUNTER_EVENT_SEL 0 8 PERFCOUNTER_CVALUE_SEL 9 11 PERFCOUNTER_INC_MODE 12 14 PERFCOUNTER_HW_CNTL_SEL 15 15 PERFCOUNTER_RUNEN_MODE 16 16 PERFCOUNTER_CNTOFF_SEL 17 21 PERFCOUNTER_CNTOFF_START_DIS 22 22 PERFCOUNTER_RESTART_EN 23 23 PERFCOUNTER_INT_EN 24 24 PERFCOUNTER_OFF_MASK 25 25 PERFCOUNTER_ACTIVE 26 26 PERFCOUNTER_INT_TYPE 27 27 PERFCOUNTER_CNTL_SEL 29 31 mmDC_PERFMON9_PERFCOUNTER_CNTL2 0 0x363 4 0 2 PERFCOUNTER_COUNTED_VALUE_TYPE 0 1 PERFCOUNTER_HW_STOP1_SEL 2 2 PERFCOUNTER_HW_STOP2_SEL 3 3 PERFCOUNTER_CNTL2_SEL 29 31 mmDC_PERFMON9_PERFCOUNTER_STATE 0 0x364 16 0 2 PERFCOUNTER_CNT0_STATE 0 1 PERFCOUNTER_STATE_SEL0 2 2 PERFCOUNTER_CNT1_STATE 4 5 PERFCOUNTER_STATE_SEL1 6 6 PERFCOUNTER_CNT2_STATE 8 9 PERFCOUNTER_STATE_SEL2 10 10 PERFCOUNTER_CNT3_STATE 12 13 PERFCOUNTER_STATE_SEL3 14 14 PERFCOUNTER_CNT4_STATE 16 17 PERFCOUNTER_STATE_SEL4 18 18 PERFCOUNTER_CNT5_STATE 20 21 PERFCOUNTER_STATE_SEL5 22 22 PERFCOUNTER_CNT6_STATE 24 25 PERFCOUNTER_STATE_SEL6 26 26 PERFCOUNTER_CNT7_STATE 28 29 PERFCOUNTER_STATE_SEL7 30 30 mmDC_PERFMON9_PERFMON_CNTL 0 0x365 6 0 2 PERFMON_STATE 0 1 PERFMON_RPT_COUNT 8 27 PERFMON_CNTOFF_AND_OR 28 28 PERFMON_CNTOFF_INT_EN 29 29 PERFMON_CNTOFF_INT_STATUS 30 30 PERFMON_CNTOFF_INT_ACK 31 31 mmDC_PERFMON9_PERFMON_CNTL2 0 0x366 4 0 2 PERFMON_CNTOFF_INT_TYPE 0 0 PERFMON_CLK_ENABLE 1 1 PERFMON_RUN_ENABLE_START_SEL 2 9 PERFMON_RUN_ENABLE_STOP_SEL 10 17 mmDC_PERFMON9_PERFMON_CVALUE_INT_MISC 0 0x367 17 0 2 PERFCOUNTER_INT0_STATUS 0 0 PERFCOUNTER_INT1_STATUS 1 1 PERFCOUNTER_INT2_STATUS 2 2 PERFCOUNTER_INT3_STATUS 3 3 PERFCOUNTER_INT4_STATUS 4 4 PERFCOUNTER_INT5_STATUS 5 5 PERFCOUNTER_INT6_STATUS 6 6 PERFCOUNTER_INT7_STATUS 7 7 PERFCOUNTER_INT0_ACK 8 8 PERFCOUNTER_INT1_ACK 9 9 PERFCOUNTER_INT2_ACK 10 10 PERFCOUNTER_INT3_ACK 11 11 PERFCOUNTER_INT4_ACK 12 12 PERFCOUNTER_INT5_ACK 13 13 PERFCOUNTER_INT6_ACK 14 14 PERFCOUNTER_INT7_ACK 15 15 PERFMON_CVALUE_HI 16 31 mmDC_PERFMON9_PERFMON_CVALUE_LOW 0 0x368 1 0 2 PERFMON_CVALUE_LOW 0 31 mmDC_PERFMON9_PERFMON_HI 0 0x369 2 0 2 PERFMON_HI 0 15 PERFMON_READ_SEL 29 31 mmDC_PERFMON9_PERFMON_LOW 0 0x36a 1 0 2 PERFMON_LOW 0 31 mmVGA_MEM_WRITE_PAGE_ADDR 0 0x0 2 0 0 VGA_MEM_WRITE_PAGE0_ADDR 0 9 VGA_MEM_WRITE_PAGE1_ADDR 16 25 mmVGA_MEM_READ_PAGE_ADDR 0 0x1 2 0 0 VGA_MEM_READ_PAGE0_ADDR 0 9 VGA_MEM_READ_PAGE1_ADDR 16 25 mmVGA_RENDER_CONTROL 0 0x0 7 0 1 VGA_BLINK_RATE 0 4 VGA_BLINK_MODE 5 6 VGA_CURSOR_BLINK_INVERT 7 7 VGA_EXTD_ADDR_COUNT_ENABLE 8 8 VGA_VSTATUS_CNTL 16 17 VGA_LOCK_8DOT 24 24 VGAREG_LINECMP_COMPATIBILITY_SEL 25 25 mmVGA_SEQUENCER_RESET_CONTROL 0 0x1 15 0 1 D1_BLANK_DISPLAY_WHEN_SEQUENCER_RESET 0 0 D2_BLANK_DISPLAY_WHEN_SEQUENCER_RESET 1 1 D3_BLANK_DISPLAY_WHEN_SEQUENCER_RESET 2 2 D4_BLANK_DISPLAY_WHEN_SEQUENCER_RESET 3 3 D5_BLANK_DISPLAY_WHEN_SEQUENCER_RESET 4 4 D6_BLANK_DISPLAY_WHEN_SEQUENCER_RESET 5 5 D1_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET 8 8 D2_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET 9 9 D3_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET 10 10 D4_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET 11 11 D5_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET 12 12 D6_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET 13 13 VGA_MODE_AUTO_TRIGGER_ENABLE 16 16 VGA_MODE_AUTO_TRIGGER_REGISTER_SELECT 17 17 VGA_MODE_AUTO_TRIGGER_INDEX_SELECT 18 23 mmVGA_MODE_CONTROL 0 0x2 5 0 1 VGA_ATI_LINEAR 0 0 VGA_LUT_PALETTE_UPDATE_MODE 4 5 VGA_128K_APERTURE_PAGING 8 8 VGA_TEXT_132_COLUMNS_EN 16 16 VGA_DEEP_SLEEP_FORCE_EXIT 24 24 mmVGA_SURFACE_PITCH_SELECT 0 0x3 2 0 1 VGA_SURFACE_PITCH_SELECT 0 1 VGA_SURFACE_HEIGHT_SELECT 8 9 mmVGA_MEMORY_BASE_ADDRESS 0 0x4 1 0 1 VGA_MEMORY_BASE_ADDRESS 0 31 mmVGA_DISPBUF1_SURFACE_ADDR 0 0x6 1 0 1 VGA_DISPBUF1_SURFACE_ADDR 0 24 mmVGA_DISPBUF2_SURFACE_ADDR 0 0x8 1 0 1 VGA_DISPBUF2_SURFACE_ADDR 0 24 mmVGA_MEMORY_BASE_ADDRESS_HIGH 0 0x9 1 0 1 VGA_MEMORY_BASE_ADDRESS_HIGH 0 7 mmVGA_HDP_CONTROL 0 0xa 5 0 1 VGA_MEM_PAGE_SELECT_EN 0 0 VGA_MEMORY_DISABLE 4 4 VGA_RBBM_LOCK_DISABLE 8 8 VGA_SOFT_RESET 16 16 VGA_TEST_RESET_CONTROL 24 24 mmVGA_CACHE_CONTROL 0 0xb 5 0 1 VGA_WRITE_THROUGH_CACHE_DIS 0 0 VGA_READ_CACHE_DISABLE 8 8 VGA_READ_BUFFER_INVALIDATE 16 16 VGA_DCCIF_W256ONLY 20 20 VGA_DCCIF_WC_TIMEOUT 24 29 mmD1VGA_CONTROL 0 0xc 5 0 1 D1VGA_MODE_ENABLE 0 0 D1VGA_TIMING_SELECT 8 8 D1VGA_SYNC_POLARITY_SELECT 9 9 D1VGA_OVERSCAN_COLOR_EN 16 16 D1VGA_ROTATE 24 25 mmD2VGA_CONTROL 0 0xe 5 0 1 D2VGA_MODE_ENABLE 0 0 D2VGA_TIMING_SELECT 8 8 D2VGA_SYNC_POLARITY_SELECT 9 9 D2VGA_OVERSCAN_COLOR_EN 16 16 D2VGA_ROTATE 24 25 mmVGA_STATUS 0 0x10 4 0 1 VGA_MEM_ACCESS_STATUS 0 0 VGA_REG_ACCESS_STATUS 1 1 VGA_DISPLAY_SWITCH_STATUS 2 2 VGA_MODE_AUTO_TRIGGER_STATUS 3 3 mmVGA_INTERRUPT_CONTROL 0 0x11 4 0 1 VGA_MEM_ACCESS_INT_MASK 0 0 VGA_REG_ACCESS_INT_MASK 8 8 VGA_DISPLAY_SWITCH_INT_MASK 16 16 VGA_MODE_AUTO_TRIGGER_INT_MASK 24 24 mmVGA_STATUS_CLEAR 0 0x12 4 0 1 VGA_MEM_ACCESS_INT_CLEAR 0 0 VGA_REG_ACCESS_INT_CLEAR 8 8 VGA_DISPLAY_SWITCH_INT_CLEAR 16 16 VGA_MODE_AUTO_TRIGGER_INT_CLEAR 24 24 mmVGA_INTERRUPT_STATUS 0 0x13 4 0 1 VGA_MEM_ACCESS_INT_STATUS 0 0 VGA_REG_ACCESS_INT_STATUS 1 1 VGA_DISPLAY_SWITCH_INT_STATUS 2 2 VGA_MODE_AUTO_TRIGGER_INT_STATUS 3 3 mmVGA_MAIN_CONTROL 0 0x14 10 0 1 VGA_CRTC_TIMEOUT 0 1 VGA_RENDER_TIMEOUT_COUNT 3 4 VGA_VIRTUAL_VERTICAL_RETRACE_DURATION 5 7 VGA_READBACK_VGA_VSTATUS_SOURCE_SELECT 8 9 VGA_MC_WRITE_CLEAN_WAIT_DELAY 12 15 VGA_READBACK_NO_DISPLAY_SOURCE_SELECT 16 17 VGA_READBACK_CRT_INTR_SOURCE_SELECT 24 25 VGA_READBACK_SENSE_SWITCH_SELECT 26 26 VGA_EXTERNAL_DAC_SENSE 29 29 VGA_MAIN_TEST_VSTATUS_NO_DISPLAY_CRTC_TIMEOUT 31 31 mmVGA_TEST_CONTROL 0 0x15 4 0 1 VGA_TEST_ENABLE 0 0 VGA_TEST_RENDER_START 8 8 VGA_TEST_RENDER_DONE 16 16 VGA_TEST_RENDER_DISPBUF_SELECT 24 24 mmVGA_QOS_CTRL 0 0x18 2 0 1 VGA_READ_QOS 0 3 VGA_WRITE_QOS 4 7 mmCRTC8_IDX 0 0x2d 1 0 1 VCRTC_IDX 0 5 mmCRTC8_DATA 0 0x2d 1 0 1 VCRTC_DATA 0 7 mmGENFC_WT 0 0x2e 1 0 1 VSYNC_SEL_W 3 3 mmGENS1 0 0x2e 3 0 1 NO_DISPLAY 0 0 VGA_VSTATUS 3 3 PIXEL_READ_BACK 4 5 mmATTRDW 0 0x30 1 0 1 ATTR_DATA 0 7 mmATTRX 0 0x30 2 0 1 ATTR_IDX 0 4 ATTR_PAL_RW_ENB 5 5 mmATTRDR 0 0x30 1 0 1 ATTR_DATA 0 7 mmGENMO_WT 0 0x30 6 0 1 GENMO_MONO_ADDRESS_B 0 0 VGA_RAM_EN 1 1 VGA_CKSEL 2 3 ODD_EVEN_MD_PGSEL 5 5 VGA_HSYNC_POL 6 6 VGA_VSYNC_POL 7 7 mmGENS0 0 0x30 2 0 1 SENSE_SWITCH 4 4 CRT_INTR 7 7 mmGENENB 0 0x30 1 0 1 BLK_IO_BASE 0 7 mmSEQ8_IDX 0 0x31 1 0 1 SEQ_IDX 0 2 mmSEQ8_DATA 0 0x31 1 0 1 SEQ_DATA 0 7 mmDAC_MASK 0 0x31 1 0 1 DAC_MASK 0 7 mmDAC_R_INDEX 0 0x31 1 0 1 DAC_R_INDEX 0 7 mmDAC_W_INDEX 0 0x32 1 0 1 DAC_W_INDEX 0 7 mmDAC_DATA 0 0x32 1 0 1 DAC_DATA 0 5 mmGENFC_RD 0 0x32 1 0 1 VSYNC_SEL_R 3 3 mmGENMO_RD 0 0x33 6 0 1 GENMO_MONO_ADDRESS_B 0 0 VGA_RAM_EN 1 1 VGA_CKSEL 2 3 ODD_EVEN_MD_PGSEL 5 5 VGA_HSYNC_POL 6 6 VGA_VSYNC_POL 7 7 mmGRPH8_IDX 0 0x33 1 0 1 GRPH_IDX 0 3 mmGRPH8_DATA 0 0x33 1 0 1 GRPH_DATA 0 7 mmCRTC8_IDX_1 0 0x35 1 0 1 VCRTC_IDX 0 5 mmCRTC8_DATA_1 0 0x35 1 0 1 VCRTC_DATA 0 7 mmGENFC_WT_1 0 0x36 1 0 1 VSYNC_SEL_W 3 3 mmGENS1_1 0 0x36 3 0 1 NO_DISPLAY 0 0 VGA_VSTATUS 3 3 PIXEL_READ_BACK 4 5 mmD3VGA_CONTROL 0 0x38 5 0 1 D3VGA_MODE_ENABLE 0 0 D3VGA_TIMING_SELECT 8 8 D3VGA_SYNC_POLARITY_SELECT 9 9 D3VGA_OVERSCAN_COLOR_EN 16 16 D3VGA_ROTATE 24 25 mmD4VGA_CONTROL 0 0x39 5 0 1 D4VGA_MODE_ENABLE 0 0 D4VGA_TIMING_SELECT 8 8 D4VGA_SYNC_POLARITY_SELECT 9 9 D4VGA_OVERSCAN_COLOR_EN 16 16 D4VGA_ROTATE 24 25 mmD5VGA_CONTROL 0 0x3a 5 0 1 D5VGA_MODE_ENABLE 0 0 D5VGA_TIMING_SELECT 8 8 D5VGA_SYNC_POLARITY_SELECT 9 9 D5VGA_OVERSCAN_COLOR_EN 16 16 D5VGA_ROTATE 24 25 mmD6VGA_CONTROL 0 0x3b 5 0 1 D6VGA_MODE_ENABLE 0 0 D6VGA_TIMING_SELECT 8 8 D6VGA_SYNC_POLARITY_SELECT 9 9 D6VGA_OVERSCAN_COLOR_EN 16 16 D6VGA_ROTATE 24 25 mmVGA_SOURCE_SELECT 0 0x3c 2 0 1 VGA_SOURCE_SEL_A 0 2 VGA_SOURCE_SEL_B 8 10 mmPHYPLLA_PIXCLK_RESYNC_CNTL 0 0x40 4 0 1 PHYPLLA_PIXCLK_RESYNC_ENABLE 0 0 PHYPLLA_DCCG_DEEP_COLOR_CNTL 4 5 PHYPLLA_PIXCLK_ENABLE 8 8 PHYPLLA_PIXCLK_DOUBLE_RATE_ENABLE 9 9 mmPHYPLLB_PIXCLK_RESYNC_CNTL 0 0x41 4 0 1 PHYPLLB_PIXCLK_RESYNC_ENABLE 0 0 PHYPLLB_DCCG_DEEP_COLOR_CNTL 4 5 PHYPLLB_PIXCLK_ENABLE 8 8 PHYPLLB_PIXCLK_DOUBLE_RATE_ENABLE 9 9 mmPHYPLLC_PIXCLK_RESYNC_CNTL 0 0x42 4 0 1 PHYPLLC_PIXCLK_RESYNC_ENABLE 0 0 PHYPLLC_DCCG_DEEP_COLOR_CNTL 4 5 PHYPLLC_PIXCLK_ENABLE 8 8 PHYPLLC_PIXCLK_DOUBLE_RATE_ENABLE 9 9 mmPHYPLLD_PIXCLK_RESYNC_CNTL 0 0x43 4 0 1 PHYPLLD_PIXCLK_RESYNC_ENABLE 0 0 PHYPLLD_DCCG_DEEP_COLOR_CNTL 4 5 PHYPLLD_PIXCLK_ENABLE 8 8 PHYPLLD_PIXCLK_DOUBLE_RATE_ENABLE 9 9 mmDCFEV0_CRTC_PIXEL_RATE_CNTL 0 0x44 3 0 1 DCFEV0_CRTC_PIXEL_RATE_SOURCE 0 1 DCFEV0_CRTC_PHYPLL_PIXEL_RATE_SOURCE 8 10 DCFEV0_CRTC_PIXEL_RATE_PLL_SOURCE 15 15 mmDCFEV1_CRTC_PIXEL_RATE_CNTL 0 0x45 3 0 1 DCFEV1_CRTC_PIXEL_RATE_SOURCE 0 1 DCFEV1_CRTC_PHYPLL_PIXEL_RATE_SOURCE 8 10 DCFEV1_CRTC_PIXEL_RATE_PLL_SOURCE 15 15 mmSYMCLKLPA_CLOCK_ENABLE 0 0x46 3 0 1 SYMCLKLPA_CLOCK_ENABLE 0 0 SYMCLKLPA_FE_FORCE_EN 4 4 SYMCLKLPA_FE_FORCE_SRC 8 10 mmSYMCLKLPB_CLOCK_ENABLE 0 0x47 3 0 1 SYMCLKLPB_CLOCK_ENABLE 0 0 SYMCLKLPB_FE_FORCE_EN 4 4 SYMCLKLPB_FE_FORCE_SRC 8 10 mmDPREFCLK_CGTT_BLK_CTRL_REG 0 0x48 2 0 1 DPREFCLK_TURN_ON_DELAY 0 3 DPREFCLK_TURN_OFF_DELAY 4 11 mmREFCLK_CNTL 0 0x49 2 0 1 REFCLK_CLOCK_EN 0 0 REFCLK_SRC_SEL 1 1 mmMIPI_CLK_CNTL 0 0x4a 3 0 1 DSICLK_CLOCK_ENABLE 0 0 BYTECLK_CLOCK_ENABLE 1 1 ESCCLK_CLOCK_ENABLE 2 2 mmREFCLK_CGTT_BLK_CTRL_REG 0 0x4b 2 0 1 REFCLK_TURN_ON_DELAY 0 3 REFCLK_TURN_OFF_DELAY 4 11 mmPHYPLLE_PIXCLK_RESYNC_CNTL 0 0x4c 4 0 1 PHYPLLE_PIXCLK_RESYNC_ENABLE 0 0 PHYPLLE_DCCG_DEEP_COLOR_CNTL 4 5 PHYPLLE_PIXCLK_ENABLE 8 8 PHYPLLE_PIXCLK_DOUBLE_RATE_ENABLE 9 9 mmDCCG_PERFMON_CNTL2 0 0x4e 9 0 1 DCCG_PERF_DSICLK_ENABLE 0 0 DCCG_PERF_REFCLK_ENABLE 1 1 DCCG_PERF_PIXCLK1_ENABLE 2 2 DCCG_PERF_PIXCLK2_ENABLE 3 3 DCCG_PERF_UNIPHYC_PIXCLK_ENABLE 4 4 DCCG_PERF_UNIPHYD_PIXCLK_ENABLE 5 5 DCCG_PERF_UNIPHYE_PIXCLK_ENABLE 6 6 DCCG_PERF_UNIPHYF_PIXCLK_ENABLE 7 7 DCCG_PERF_UNIPHYG_PIXCLK_ENABLE 8 8 mmDSICLK_CGTT_BLK_CTRL_REG 0 0x4f 2 0 1 DSICLK_TURN_ON_DELAY 0 3 DSICLK_TURN_OFF_DELAY 4 11 mmDCCG_CBUS_WRCMD_DELAY 0 0x50 1 0 1 CBUS_PLL_WRCMD_DELAY 0 3 mmDCCG_DS_DTO_INCR 0 0x53 1 0 1 DCCG_DS_DTO_INCR 0 31 mmDCCG_DS_DTO_MODULO 0 0x54 1 0 1 DCCG_DS_DTO_MODULO 0 31 mmDCCG_DS_CNTL 0 0x55 7 0 1 DCCG_DS_ENABLE 0 0 DCCG_DS_REF_SRC 4 5 DCCG_DS_HW_CAL_ENABLE 8 8 DCCG_DS_ENABLED_STATUS 9 9 DCCG_DS_XTALIN_RATE_DIV 16 17 DCCG_DS_JITTER_REMOVE_DIS 24 24 DCCG_DS_DELAY_XTAL_SEL 25 25 mmDCCG_DS_HW_CAL_INTERVAL 0 0x56 1 0 1 DCCG_DS_HW_CAL_INTERVAL 0 31 mmSYMCLKG_CLOCK_ENABLE 0 0x57 3 0 1 SYMCLKG_CLOCK_ENABLE 0 0 SYMCLKG_FE_FORCE_EN 4 4 SYMCLKG_FE_FORCE_SRC 8 10 mmDPREFCLK_CNTL 0 0x58 2 0 1 DPREFCLK_SRC_SEL 0 2 UNB_DB_CLK_ENABLE 8 8 mmAOMCLK0_CNTL 0 0x59 1 0 1 AOMCLK0_CLOCK_EN 0 0 mmAOMCLK1_CNTL 0 0x5a 1 0 1 AOMCLK1_CLOCK_EN 0 0 mmAOMCLK2_CNTL 0 0x5b 1 0 1 AOMCLK2_CLOCK_EN 0 0 mmDCCG_AUDIO_DTO2_PHASE 0 0x5c 1 0 1 DCCG_AUDIO_DTO2_PHASE 0 31 mmDCCG_AUDIO_DTO2_MODULO 0 0x5d 1 0 1 DCCG_AUDIO_DTO2_MODULO 0 31 mmDCE_VERSION 0 0x5e 2 0 1 MAJOR_VERSION 0 7 MINOR_VERSION 8 15 mmPHYPLLG_PIXCLK_RESYNC_CNTL 0 0x5f 4 0 1 PHYPLLG_PIXCLK_RESYNC_ENABLE 0 0 PHYPLLG_DCCG_DEEP_COLOR_CNTL 4 5 PHYPLLG_PIXCLK_ENABLE 8 8 PHYPLLG_PIXCLK_DOUBLE_RATE_ENABLE 9 9 mmDCCG_GTC_CNTL 0 0x60 1 0 1 DCCG_GTC_ENABLE 0 0 mmDCCG_GTC_DTO_INCR 0 0x61 1 0 1 DCCG_GTC_DTO_INCR 0 31 mmDCCG_GTC_DTO_MODULO 0 0x62 1 0 1 DCCG_GTC_DTO_MODULO 0 31 mmDCCG_GTC_CURRENT 0 0x63 1 0 1 DCCG_GTC_CURRENT 0 31 mmDENTIST_DISPCLK_CNTL 0 0x64 10 0 1 DENTIST_DISPCLK_WDIVIDER 0 6 DENTIST_DISPCLK_RDIVIDER 8 14 DENTIST_DISPCLK_CHG_MODE 15 16 DENTIST_DISPCLK_CHGTOG 17 17 DENTIST_DISPCLK_DONETOG 18 18 DENTIST_DISPCLK_CHG_DONE 19 19 DENTIST_DPREFCLK_CHG_DONE 20 20 DENTIST_DPREFCLK_CHGTOG 21 21 DENTIST_DPREFCLK_DONETOG 22 22 DENTIST_DPREFCLK_WDIVIDER 24 30 mmMIPI_DTO_CNTL 0 0x65 1 0 1 MIPI_DTO_ENABLE 0 0 mmMIPI_DTO_PHASE 0 0x66 1 0 1 MIPI_DTO_PHASE 0 31 mmMIPI_DTO_MODULO 0 0x67 1 0 1 MIPI_DTO_MODULO 0 31 mmDAC_CLK_ENABLE 0 0x68 2 0 1 DACA_CLK_ENABLE 0 0 DACB_CLK_ENABLE 4 4 mmDVO_CLK_ENABLE 0 0x69 1 0 1 DVO_CLK_ENABLE 0 0 mmAVSYNC_COUNTER_WRITE 0 0x6a 1 0 1 AVSYNC_COUNTER_WRVALUE 0 31 mmAVSYNC_COUNTER_CONTROL 0 0x6b 1 0 1 AVSYNC_COUNTER_ENABLE 0 0 mmDMCU_SMU_INTERRUPT_CNTL 0 0x6c 2 0 1 DMCU_SMU_STATIC_SCREEN_INT 0 0 DMCU_SMU_STATIC_SCREEN_STATUS 16 31 mmSMU_CONTROL 0 0x6d 9 0 1 DISPLAY0_FORCE_VBI 0 0 DISPLAY1_FORCE_VBI 1 1 DISPLAY2_FORCE_VBI 2 2 DISPLAY3_FORCE_VBI 3 3 DISPLAY4_FORCE_VBI 4 4 DISPLAY5_FORCE_VBI 5 5 DISPLAY_V0_FORCE_VBI 6 6 DISPLAY_V1_FORCE_VBI 7 7 MCIF_WB_FORCE_VBI 8 8 mmSMU_INTERRUPT_CONTROL 0 0x6e 3 0 1 DC_SMU_INT_ENABLE 0 0 DC_SMU_INT_STATUS 4 4 DC_SMU_INT_EVENT 16 31 mmAVSYNC_COUNTER_READ 0 0x6f 1 0 1 AVSYNC_COUNTER_RDVALUE 0 31 mmMILLISECOND_TIME_BASE_DIV 0 0x70 2 0 1 MILLISECOND_TIME_BASE_DIV 0 16 MILLISECOND_TIME_BASE_CLOCK_SOURCE_SEL 20 20 mmDISPCLK_FREQ_CHANGE_CNTL 0 0x71 8 0 1 DISPCLK_STEP_DELAY 0 13 DISPCLK_STEP_SIZE 16 19 DISPCLK_FREQ_RAMP_DONE 20 20 DISPCLK_MAX_ERRDET_CYCLES 25 27 DCCG_FIFO_ERRDET_RESET 28 28 DCCG_FIFO_ERRDET_STATE 29 29 DCCG_FIFO_ERRDET_OVR_EN 30 30 DISPCLK_CHG_FWD_CORR_DISABLE 31 31 mmDC_MEM_GLOBAL_PWR_REQ_CNTL 0 0x72 1 0 1 DC_MEM_GLOBAL_PWR_REQ_DIS 0 0 mmDCCG_PERFMON_CNTL 0 0x73 10 0 1 DCCG_PERF_DISPCLK_ENABLE 0 0 DCCG_PERF_DPREFCLK_ENABLE 1 1 DCCG_PERF_UNIPHYA_PIXCLK_ENABLE 2 2 DCCG_PERF_UNIPHYB_PIXCLK_ENABLE 3 3 DCCG_PERF_PIXCLK0_ENABLE 4 4 DCCG_PERF_RUN 5 5 DCCG_PERF_MODE_VSYNC 6 6 DCCG_PERF_MODE_HSYNC 7 7 DCCG_PERF_CRTC_SEL 8 10 DCCG_PERF_XTALIN_PULSE_DIV 11 31 mmDCCG_GATE_DISABLE_CNTL 0 0x74 19 0 1 DISPCLK_DCCG_GATE_DISABLE 0 0 DISPCLK_R_DCCG_GATE_DISABLE 1 1 SCLK_GATE_DISABLE 2 2 DPREFCLK_GATE_DISABLE 3 3 DACACLK_GATE_DISABLE 4 4 DACBCLK_GATE_DISABLE 5 5 DVOACLK_GATE_DISABLE 6 6 DPREFCLK_R_DCCG_GATE_DISABLE 8 8 AOMCLK0_GATE_DISABLE 17 17 AOMCLK1_GATE_DISABLE 18 18 AOMCLK2_GATE_DISABLE 19 19 AUDIO_DTO2_CLK_GATE_DISABLE 21 21 DPREFCLK_GTC_GATE_DISABLE 22 22 UNB_DB_CLK_GATE_DISABLE 23 23 REFCLK_GATE_DISABLE 26 26 REFCLK_R_DIG_GATE_DISABLE 27 27 DSICLK_GATE_DISABLE 28 28 BYTECLK_GATE_DISABLE 29 29 ESCCLK_GATE_DISABLE 30 30 mmDISPCLK_CGTT_BLK_CTRL_REG 0 0x75 2 0 1 DISPCLK_TURN_ON_DELAY 0 3 DISPCLK_TURN_OFF_DELAY 4 11 mmSCLK_CGTT_BLK_CTRL_REG 0 0x76 3 0 1 SCLK_TURN_ON_DELAY 0 3 SCLK_TURN_OFF_DELAY 4 11 CGTT_SCLK_OVERRIDE 12 12 mmDCCG_CAC_STATUS 0 0x77 1 0 1 CAC_STATUS_RDDATA 0 31 mmPIXCLK1_RESYNC_CNTL 0 0x78 2 0 1 PIXCLK1_RESYNC_ENABLE 0 0 DCCG_DEEP_COLOR_CNTL1 4 5 mmPIXCLK2_RESYNC_CNTL 0 0x79 2 0 1 PIXCLK2_RESYNC_ENABLE 0 0 DCCG_DEEP_COLOR_CNTL2 4 5 mmPIXCLK0_RESYNC_CNTL 0 0x7a 2 0 1 PIXCLK0_RESYNC_ENABLE 0 0 DCCG_DEEP_COLOR_CNTL0 4 5 mmMICROSECOND_TIME_BASE_DIV 0 0x7b 5 0 1 MICROSECOND_TIME_BASE_DIV 0 6 XTAL_REF_DIV 8 14 XTAL_REF_SEL 16 16 XTAL_REF_CLOCK_SOURCE_SEL 17 17 MICROSECOND_TIME_BASE_CLOCK_SOURCE_SEL 20 20 mmDCCG_GATE_DISABLE_CNTL2 0 0x7c 18 0 1 SYMCLKA_FE_GATE_DISABLE 0 0 SYMCLKB_FE_GATE_DISABLE 1 1 SYMCLKC_FE_GATE_DISABLE 2 2 SYMCLKD_FE_GATE_DISABLE 3 3 SYMCLKE_FE_GATE_DISABLE 4 4 SYMCLKF_FE_GATE_DISABLE 5 5 SYMCLKG_FE_GATE_DISABLE 6 6 SYMCLKLPA_FE_GATE_DISABLE 8 8 SYMCLKLPB_FE_GATE_DISABLE 9 9 SYMCLKA_GATE_DISABLE 16 16 SYMCLKB_GATE_DISABLE 17 17 SYMCLKC_GATE_DISABLE 18 18 SYMCLKD_GATE_DISABLE 19 19 SYMCLKE_GATE_DISABLE 20 20 SYMCLKF_GATE_DISABLE 21 21 SYMCLKG_GATE_DISABLE 22 22 SYMCLKLPA_GATE_DISABLE 24 24 SYMCLKLPB_GATE_DISABLE 25 25 mmSYMCLK_CGTT_BLK_CTRL_REG 0 0x7d 2 0 1 SYMCLK_TURN_ON_DELAY 0 3 SYMCLK_TURN_OFF_DELAY 4 11 mmPHYPLLF_PIXCLK_RESYNC_CNTL 0 0x7e 4 0 1 PHYPLLF_PIXCLK_RESYNC_ENABLE 0 0 PHYPLLF_DCCG_DEEP_COLOR_CNTL 4 5 PHYPLLF_PIXCLK_ENABLE 8 8 PHYPLLF_PIXCLK_DOUBLE_RATE_ENABLE 9 9 mmDCCG_DISP_CNTL_REG 0 0x7f 1 0 1 ALLOW_SR_ON_TRANS_REQ 8 8 mmCRTC0_PIXEL_RATE_CNTL 0 0x80 8 0 1 CRTC0_PIXEL_RATE_SOURCE 0 1 DP_DTO0_ENABLE 4 4 DP_DTO0_DS_DISABLE 5 5 CRTC0_ADD_PIXEL 8 8 CRTC0_DROP_PIXEL 9 9 CRTC0_DISPOUT_HALF_RATE_EN 11 11 CRTC0_DISPOUT_FIFO_ERROR 14 15 CRTC0_DISPOUT_ERROR_COUNT 16 27 mmDP_DTO0_PHASE 0 0x81 1 0 1 DP_DTO0_PHASE 0 31 mmDP_DTO0_MODULO 0 0x82 1 0 1 DP_DTO0_MODULO 0 31 mmCRTC0_PHYPLL_PIXEL_RATE_CNTL 0 0x83 2 0 1 CRTC0_PHYPLL_PIXEL_RATE_SOURCE 0 2 CRTC0_PIXEL_RATE_PLL_SOURCE 4 4 mmCRTC1_PIXEL_RATE_CNTL 0 0x84 8 0 1 CRTC1_PIXEL_RATE_SOURCE 0 1 DP_DTO1_ENABLE 4 4 DP_DTO1_DS_DISABLE 5 5 CRTC1_ADD_PIXEL 8 8 CRTC1_DROP_PIXEL 9 9 CRTC1_DISPOUT_HALF_RATE_EN 11 11 CRTC1_DISPOUT_FIFO_ERROR 14 15 CRTC1_DISPOUT_ERROR_COUNT 16 27 mmDP_DTO1_PHASE 0 0x85 1 0 1 DP_DTO1_PHASE 0 31 mmDP_DTO1_MODULO 0 0x86 1 0 1 DP_DTO1_MODULO 0 31 mmCRTC1_PHYPLL_PIXEL_RATE_CNTL 0 0x87 2 0 1 CRTC1_PHYPLL_PIXEL_RATE_SOURCE 0 2 CRTC1_PIXEL_RATE_PLL_SOURCE 4 4 mmCRTC2_PIXEL_RATE_CNTL 0 0x88 8 0 1 CRTC2_PIXEL_RATE_SOURCE 0 1 DP_DTO2_ENABLE 4 4 DP_DTO2_DS_DISABLE 5 5 CRTC2_ADD_PIXEL 8 8 CRTC2_DROP_PIXEL 9 9 CRTC2_DISPOUT_HALF_RATE_EN 11 11 CRTC2_DISPOUT_FIFO_ERROR 14 15 CRTC2_DISPOUT_ERROR_COUNT 16 27 mmDP_DTO2_PHASE 0 0x89 1 0 1 DP_DTO2_PHASE 0 31 mmDP_DTO2_MODULO 0 0x8a 1 0 1 DP_DTO2_MODULO 0 31 mmCRTC2_PHYPLL_PIXEL_RATE_CNTL 0 0x8b 2 0 1 CRTC2_PHYPLL_PIXEL_RATE_SOURCE 0 2 CRTC2_PIXEL_RATE_PLL_SOURCE 4 4 mmCRTC3_PIXEL_RATE_CNTL 0 0x8c 8 0 1 CRTC3_PIXEL_RATE_SOURCE 0 1 DP_DTO3_ENABLE 4 4 DP_DTO3_DS_DISABLE 5 5 CRTC3_ADD_PIXEL 8 8 CRTC3_DROP_PIXEL 9 9 CRTC3_DISPOUT_HALF_RATE_EN 11 11 CRTC3_DISPOUT_FIFO_ERROR 14 15 CRTC3_DISPOUT_ERROR_COUNT 16 27 mmDP_DTO3_PHASE 0 0x8d 1 0 1 DP_DTO3_PHASE 0 31 mmDP_DTO3_MODULO 0 0x8e 1 0 1 DP_DTO3_MODULO 0 31 mmCRTC3_PHYPLL_PIXEL_RATE_CNTL 0 0x8f 2 0 1 CRTC3_PHYPLL_PIXEL_RATE_SOURCE 0 2 CRTC3_PIXEL_RATE_PLL_SOURCE 4 4 mmCRTC4_PIXEL_RATE_CNTL 0 0x90 8 0 1 CRTC4_PIXEL_RATE_SOURCE 0 1 DP_DTO4_ENABLE 4 4 DP_DTO4_DS_DISABLE 5 5 CRTC4_ADD_PIXEL 8 8 CRTC4_DROP_PIXEL 9 9 CRTC4_DISPOUT_HALF_RATE_EN 11 11 CRTC4_DISPOUT_FIFO_ERROR 14 15 CRTC4_DISPOUT_ERROR_COUNT 16 27 mmDP_DTO4_PHASE 0 0x91 1 0 1 DP_DTO4_PHASE 0 31 mmDP_DTO4_MODULO 0 0x92 1 0 1 DP_DTO4_MODULO 0 31 mmCRTC4_PHYPLL_PIXEL_RATE_CNTL 0 0x93 2 0 1 CRTC4_PHYPLL_PIXEL_RATE_SOURCE 0 2 CRTC4_PIXEL_RATE_PLL_SOURCE 4 4 mmCRTC5_PIXEL_RATE_CNTL 0 0x94 8 0 1 CRTC5_PIXEL_RATE_SOURCE 0 1 DP_DTO5_ENABLE 4 4 DP_DTO5_DS_DISABLE 5 5 CRTC5_ADD_PIXEL 8 8 CRTC5_DROP_PIXEL 9 9 CRTC5_DISPOUT_HALF_RATE_EN 11 11 CRTC5_DISPOUT_FIFO_ERROR 14 15 CRTC5_DISPOUT_ERROR_COUNT 16 27 mmDP_DTO5_PHASE 0 0x95 1 0 1 DP_DTO5_PHASE 0 31 mmDP_DTO5_MODULO 0 0x96 1 0 1 DP_DTO5_MODULO 0 31 mmCRTC5_PHYPLL_PIXEL_RATE_CNTL 0 0x97 2 0 1 CRTC5_PHYPLL_PIXEL_RATE_SOURCE 0 2 CRTC5_PIXEL_RATE_PLL_SOURCE 4 4 mmDCCG_SOFT_RESET 0 0x9f 16 0 1 REFCLK_SOFT_RESET 0 0 PCIE_REFCLK_SOFT_RESET 1 1 SOFT_RESET_DVO 2 2 DVO_ENABLE_RST 3 3 AUDIO_DTO2_CLK_SOFT_RESET 4 4 DPREFCLK_SOFT_RESET 8 8 AMCLK0_SOFT_RESET 12 12 AMCLK1_SOFT_RESET 13 13 P0PLL_CFG_IF_SOFT_RESET 14 14 P1PLL_CFG_IF_SOFT_RESET 15 15 P2PLL_CFG_IF_SOFT_RESET 16 16 A0PLL_CFG_IF_SOFT_RESET 17 17 A1PLL_CFG_IF_SOFT_RESET 18 18 C0PLL_CFG_IF_SOFT_RESET 19 19 C1PLL_CFG_IF_SOFT_RESET 20 20 C2PLL_CFG_IF_SOFT_RESET 21 21 mmSYMCLKA_CLOCK_ENABLE 0 0xa0 3 0 1 SYMCLKA_CLOCK_ENABLE 0 0 SYMCLKA_FE_FORCE_EN 4 4 SYMCLKA_FE_FORCE_SRC 8 10 mmSYMCLKB_CLOCK_ENABLE 0 0xa1 3 0 1 SYMCLKB_CLOCK_ENABLE 0 0 SYMCLKB_FE_FORCE_EN 4 4 SYMCLKB_FE_FORCE_SRC 8 10 mmSYMCLKC_CLOCK_ENABLE 0 0xa2 3 0 1 SYMCLKC_CLOCK_ENABLE 0 0 SYMCLKC_FE_FORCE_EN 4 4 SYMCLKC_FE_FORCE_SRC 8 10 mmSYMCLKD_CLOCK_ENABLE 0 0xa3 3 0 1 SYMCLKD_CLOCK_ENABLE 0 0 SYMCLKD_FE_FORCE_EN 4 4 SYMCLKD_FE_FORCE_SRC 8 10 mmSYMCLKE_CLOCK_ENABLE 0 0xa4 3 0 1 SYMCLKE_CLOCK_ENABLE 0 0 SYMCLKE_FE_FORCE_EN 4 4 SYMCLKE_FE_FORCE_SRC 8 10 mmSYMCLKF_CLOCK_ENABLE 0 0xa5 3 0 1 SYMCLKF_CLOCK_ENABLE 0 0 SYMCLKF_FE_FORCE_EN 4 4 SYMCLKF_FE_FORCE_SRC 8 10 mmDVOACLKD_CNTL 0 0xa8 5 0 1 DVOACLKD_FINE_SKEW_CNTL 0 2 DVOACLKD_COARSE_SKEW_CNTL 8 12 DVOACLKD_FINE_ADJUST_EN 16 16 DVOACLKD_COARSE_ADJUST_EN 17 17 DVOACLKD_IN_PHASE 18 18 mmDVOACLKC_MVP_CNTL 0 0xa9 8 0 1 DVOACLKC_MVP_FINE_SKEW_CNTL 0 2 DVOACLKC_MVP_COARSE_SKEW_CNTL 8 12 DVOACLKC_MVP_FINE_ADJUST_EN 16 16 DVOACLKC_MVP_COARSE_ADJUST_EN 17 17 DVOACLKC_MVP_IN_PHASE 18 18 DVOACLKC_MVP_SKEW_PHASE_OVERRIDE 20 20 MVP_CLK_A_SRC_SEL 24 25 MVP_CLK_B_SRC_SEL 28 29 mmDVOACLKC_CNTL 0 0xaa 5 0 1 DVOACLKC_FINE_SKEW_CNTL 0 2 DVOACLKC_COARSE_SKEW_CNTL 8 12 DVOACLKC_FINE_ADJUST_EN 16 16 DVOACLKC_COARSE_ADJUST_EN 17 17 DVOACLKC_IN_PHASE 18 18 mmDCCG_AUDIO_DTO_SOURCE 0 0xab 7 0 1 DCCG_AUDIO_DTO0_SOURCE_SEL 0 2 DCCG_AUDIO_DTO_SEL 4 5 DCCG_AUDIO_DTO2_SOURCE_SEL 12 13 DCCG_AUDIO_DTO2_CLOCK_EN 16 16 DCCG_AUDIO_DTO2_USE_512FBR_DTO 20 20 DCCG_AUDIO_DTO0_USE_512FBR_DTO 24 24 DCCG_AUDIO_DTO1_USE_512FBR_DTO 28 28 mmDCCG_AUDIO_DTO0_PHASE 0 0xac 1 0 1 DCCG_AUDIO_DTO0_PHASE 0 31 mmDCCG_AUDIO_DTO0_MODULE 0 0xad 1 0 1 DCCG_AUDIO_DTO0_MODULE 0 31 mmDCCG_AUDIO_DTO1_PHASE 0 0xae 1 0 1 DCCG_AUDIO_DTO1_PHASE 0 31 mmDCCG_AUDIO_DTO1_MODULE 0 0xaf 1 0 1 DCCG_AUDIO_DTO1_MODULE 0 31 mmDCCG_TEST_CLK_SEL 0 0xbe 4 0 1 DCCG_TEST_CLK_GENERICA_SEL 0 8 DCCG_TEST_CLK_GENERICA_INV 12 12 DCCG_TEST_CLK_GENERICB_SEL 16 24 DCCG_TEST_CLK_GENERICB_INV 28 28 mmFBC_CNTL 0 0x62 9 0 2 FBC_GRPH_COMP_EN 0 0 FBC_SRC_SEL 1 3 FBC_COMP_CLK_GATE_EN 8 8 FBC_DECOMP_CLK_GATE_EN 10 10 FBC_COHERENCY_MODE 16 17 FBC_DS_ALLOW_DIS 24 24 FBC_SOFT_COMPRESS_EN 25 25 FBC_QOS_LEVEL 26 29 FBC_EN 31 31 mmFBC_IDLE_FORCE_CLEAR_MASK 0 0x64 1 0 2 FBC_IDLE_FORCE_CLEAR_MASK 0 31 mmFBC_START_STOP_DELAY 0 0x65 3 0 2 FBC_DECOMP_START_DELAY 0 4 FBC_DECOMP_STOP_DELAY 7 7 FBC_COMP_START_DELAY 8 12 mmFBC_COMP_CNTL 0 0x66 6 0 2 FBC_MIN_COMPRESSION 0 3 FBC_DEPTH_MONO08_EN 16 16 FBC_DEPTH_MONO16_EN 17 17 FBC_DEPTH_RGB04_EN 18 18 FBC_DEPTH_RGB08_EN 19 19 FBC_DEPTH_RGB16_EN 20 20 mmFBC_COMP_MODE 0 0x67 6 0 2 FBC_RLE_EN 0 0 FBC_DPCM4_RGB_EN 8 8 FBC_DPCM8_RGB_EN 9 9 FBC_DPCM4_YUV_EN 10 10 FBC_DPCM8_YUV_EN 11 11 FBC_IND_EN 16 16 mmFBC_IND_LUT0 0 0x6b 1 0 2 FBC_IND_LUT0 0 31 mmFBC_IND_LUT1 0 0x6c 1 0 2 FBC_IND_LUT1 0 31 mmFBC_IND_LUT2 0 0x6d 1 0 2 FBC_IND_LUT2 0 31 mmFBC_IND_LUT3 0 0x6e 1 0 2 FBC_IND_LUT3 0 31 mmFBC_IND_LUT4 0 0x6f 1 0 2 FBC_IND_LUT4 0 31 mmFBC_IND_LUT5 0 0x70 1 0 2 FBC_IND_LUT5 0 31 mmFBC_IND_LUT6 0 0x71 1 0 2 FBC_IND_LUT6 0 31 mmFBC_IND_LUT7 0 0x72 1 0 2 FBC_IND_LUT7 0 31 mmFBC_IND_LUT8 0 0x73 1 0 2 FBC_IND_LUT8 0 31 mmFBC_IND_LUT9 0 0x74 1 0 2 FBC_IND_LUT9 0 31 mmFBC_IND_LUT10 0 0x75 1 0 2 FBC_IND_LUT10 0 31 mmFBC_IND_LUT11 0 0x76 1 0 2 FBC_IND_LUT11 0 31 mmFBC_IND_LUT12 0 0x77 1 0 2 FBC_IND_LUT12 0 31 mmFBC_IND_LUT13 0 0x78 1 0 2 FBC_IND_LUT13 0 31 mmFBC_IND_LUT14 0 0x79 1 0 2 FBC_IND_LUT14 0 31 mmFBC_IND_LUT15 0 0x7a 1 0 2 FBC_IND_LUT15 0 31 mmFBC_CSM_REGION_OFFSET_01 0 0x7b 2 0 2 FBC_CSM_REGION_OFFSET_0 0 11 FBC_CSM_REGION_OFFSET_1 16 27 mmFBC_CSM_REGION_OFFSET_23 0 0x7c 2 0 2 FBC_CSM_REGION_OFFSET_2 0 11 FBC_CSM_REGION_OFFSET_3 16 27 mmFBC_CLIENT_REGION_MASK 0 0x7d 1 0 2 FBC_MEMORY_REGION_MASK 16 19 mmFBC_DEBUG_COMP 0 0x7e 6 0 2 FBC_COMP_SWAP 0 1 FBC_COMP_RSIZE 3 3 FBC_COMP_BUSY_HYSTERESIS 4 7 FBC_COMP_CLK_CNTL 8 9 FBC_COMP_PRIVILEGED_ACCESS_ENABLE 10 10 FBC_COMP_ADDRESS_TRANSLATION_ENABLE 11 11 mmFBC_MISC 0 0x84 15 0 2 FBC_DECOMPRESS_ERROR 0 1 FBC_STOP_ON_ERROR 2 2 FBC_INVALIDATE_ON_ERROR 3 3 FBC_ERROR_PIXEL 4 7 FBC_DIVIDE_X 8 9 FBC_DIVIDE_Y 10 10 FBC_RSM_WRITE_VALUE 11 11 FBC_RSM_UNCOMP_DATA_IMMEDIATELY 12 12 FBC_STOP_ON_HFLIP_EVENT 13 13 FBC_STOP_COMP_ON_INVALIDATE 14 14 FBC_DECOMPRESS_ERROR_CLEAR 16 16 FBC_RESET_AT_ENABLE 20 20 FBC_RESET_AT_DISABLE 21 21 FBC_SLOW_REQ_INTERVAL 24 28 FBC_FORCE_DECOMPRESSOR_EN 31 31 mmFBC_STATUS 0 0x85 4 0 2 FBC_ENABLE_STATUS 0 0 FBC_ENABLE_STATUS_SW 4 4 FBC_COMPRESSION_ENABLE_STATUS 8 8 FBC_DECOMPRESSION_ENABLE_STATUS 12 12 mmFBC_ALPHA_CNTL 0 0x88 3 0 2 FBC_ALPHA_COMP_EN 0 0 FBC_FORCE_COPY_TO_COMP_BUF 4 4 FBC_ZERO_ALPHA_CHUNK_SKIP_EN 8 8 mmFBC_ALPHA_RGB_OVERRIDE 0 0x89 3 0 2 FBC_ZERO_ALPHA_R_VAL 0 7 FBC_ZERO_ALPHA_G_VAL 12 19 FBC_ZERO_ALPHA_B_VAL 24 31 mmPIPE0_PG_CONFIG 0 0x8e 1 0 2 PIPE0_POWER_FORCEON 0 0 mmPIPE0_PG_ENABLE 0 0x8f 1 0 2 PIPE0_POWER_GATE 0 0 mmPIPE0_PG_STATUS 0 0x90 2 0 2 PIPE0_DESIRED_PWR_STATE 28 28 PIPE0_PGFSM_PWR_STATUS 30 31 mmPIPE1_PG_CONFIG 0 0x91 1 0 2 PIPE1_POWER_FORCEON 0 0 mmPIPE1_PG_ENABLE 0 0x92 1 0 2 PIPE1_POWER_GATE 0 0 mmPIPE1_PG_STATUS 0 0x93 2 0 2 PIPE1_DESIRED_PWR_STATE 28 28 PIPE1_PGFSM_PWR_STATUS 30 31 mmPIPE2_PG_CONFIG 0 0x94 1 0 2 PIPE2_POWER_FORCEON 0 0 mmPIPE2_PG_ENABLE 0 0x95 1 0 2 PIPE2_POWER_GATE 0 0 mmPIPE2_PG_STATUS 0 0x96 2 0 2 PIPE2_DESIRED_PWR_STATE 28 28 PIPE2_PGFSM_PWR_STATUS 30 31 mmPIPE3_PG_CONFIG 0 0x97 1 0 2 PIPE3_POWER_FORCEON 0 0 mmPIPE3_PG_ENABLE 0 0x98 1 0 2 PIPE3_POWER_GATE 0 0 mmPIPE3_PG_STATUS 0 0x99 2 0 2 PIPE3_DESIRED_PWR_STATE 28 28 PIPE3_PGFSM_PWR_STATUS 30 31 mmPIPE4_PG_CONFIG 0 0x9a 1 0 2 PIPE4_POWER_FORCEON 0 0 mmPIPE4_PG_ENABLE 0 0x9b 1 0 2 PIPE4_POWER_GATE 0 0 mmPIPE4_PG_STATUS 0 0x9c 2 0 2 PIPE4_DESIRED_PWR_STATE 28 28 PIPE4_PGFSM_PWR_STATUS 30 31 mmPIPE5_PG_CONFIG 0 0x9d 1 0 2 PIPE5_POWER_FORCEON 0 0 mmPIPE5_PG_ENABLE 0 0x9e 1 0 2 PIPE5_POWER_GATE 0 0 mmPIPE5_PG_STATUS 0 0x9f 2 0 2 PIPE5_DESIRED_PWR_STATE 28 28 PIPE5_PGFSM_PWR_STATUS 30 31 mmDSI_PG_CONFIG 0 0xa0 1 0 2 DSI_POWER_FORCEON 0 0 mmDSI_PG_ENABLE 0 0xa1 1 0 2 DSI_POWER_GATE 0 0 mmDSI_PG_STATUS 0 0xa2 2 0 2 DSI_DESIRED_PWR_STATE 28 28 DSI_PGFSM_PWR_STATUS 30 31 mmDCFEV0_PG_CONFIG 0 0xa3 1 0 2 DCFEV0_POWER_FORCEON 0 0 mmDCFEV0_PG_ENABLE 0 0xa4 1 0 2 DCFEV0_POWER_GATE 0 0 mmDCFEV0_PG_STATUS 0 0xa5 2 0 2 DCFEV0_DESIRED_PWR_STATE 28 28 DCFEV0_PGFSM_PWR_STATUS 30 31 mmDCPG_INTERRUPT_STATUS 0 0xa6 18 0 2 DCFE0_POWER_UP_INT_OCCURRED 0 0 DCFE0_POWER_DOWN_INT_OCCURRED 1 1 DCFE1_POWER_UP_INT_OCCURRED 2 2 DCFE1_POWER_DOWN_INT_OCCURRED 3 3 DCFE2_POWER_UP_INT_OCCURRED 4 4 DCFE2_POWER_DOWN_INT_OCCURRED 5 5 DCFE3_POWER_UP_INT_OCCURRED 6 6 DCFE3_POWER_DOWN_INT_OCCURRED 7 7 DCFE4_POWER_UP_INT_OCCURRED 8 8 DCFE4_POWER_DOWN_INT_OCCURRED 9 9 DCFE5_POWER_UP_INT_OCCURRED 10 10 DCFE5_POWER_DOWN_INT_OCCURRED 11 11 DCFEV0_POWER_UP_INT_OCCURRED 12 12 DCFEV0_POWER_DOWN_INT_OCCURRED 13 13 DSI_POWER_UP_INT_OCCURRED 14 14 DSI_POWER_DOWN_INT_OCCURRED 15 15 DCFEV1_POWER_UP_INT_OCCURRED 16 16 DCFEV1_POWER_DOWN_INT_OCCURRED 17 17 mmDCPG_INTERRUPT_CONTROL 0 0xa7 32 0 2 DCFE0_POWER_UP_INT_MASK 0 0 DCFE0_POWER_UP_INT_CLEAR 1 1 DCFE0_POWER_DOWN_INT_MASK 2 2 DCFE0_POWER_DOWN_INT_CLEAR 3 3 DCFE1_POWER_UP_INT_MASK 4 4 DCFE1_POWER_UP_INT_CLEAR 5 5 DCFE1_POWER_DOWN_INT_MASK 6 6 DCFE1_POWER_DOWN_INT_CLEAR 7 7 DCFE2_POWER_UP_INT_MASK 8 8 DCFE2_POWER_UP_INT_CLEAR 9 9 DCFE2_POWER_DOWN_INT_MASK 10 10 DCFE2_POWER_DOWN_INT_CLEAR 11 11 DCFE3_POWER_UP_INT_MASK 12 12 DCFE3_POWER_UP_INT_CLEAR 13 13 DCFE3_POWER_DOWN_INT_MASK 14 14 DCFE3_POWER_DOWN_INT_CLEAR 15 15 DCFE4_POWER_UP_INT_MASK 16 16 DCFE4_POWER_UP_INT_CLEAR 17 17 DCFE4_POWER_DOWN_INT_MASK 18 18 DCFE4_POWER_DOWN_INT_CLEAR 19 19 DCFE5_POWER_UP_INT_MASK 20 20 DCFE5_POWER_UP_INT_CLEAR 21 21 DCFE5_POWER_DOWN_INT_MASK 22 22 DCFE5_POWER_DOWN_INT_CLEAR 23 23 DCFEV0_POWER_UP_INT_MASK 24 24 DCFEV0_POWER_UP_INT_CLEAR 25 25 DCFEV0_POWER_DOWN_INT_MASK 26 26 DCFEV0_POWER_DOWN_INT_CLEAR 27 27 DSI_POWER_UP_INT_MASK 28 28 DSI_POWER_UP_INT_CLEAR 29 29 DSI_POWER_DOWN_INT_MASK 30 30 DSI_POWER_DOWN_INT_CLEAR 31 31 mmDCPG_INTERRUPT_CONTROL2 0 0xa8 4 0 2 DCFEV1_POWER_UP_INT_MASK 24 24 DCFEV1_POWER_UP_INT_CLEAR 25 25 DCFEV1_POWER_DOWN_INT_MASK 26 26 DCFEV1_POWER_DOWN_INT_CLEAR 27 27 mmDCFEV1_PG_CONFIG 0 0xa9 1 0 2 DCFEV1_POWER_FORCEON 0 0 mmDCFEV1_PG_ENABLE 0 0xaa 1 0 2 DCFEV1_POWER_GATE 0 0 mmDCFEV1_PG_STATUS 0 0xab 2 0 2 DCFEV1_DESIRED_PWR_STATE 28 28 DCFEV1_PGFSM_PWR_STATUS 30 31 mmDC_IP_REQUEST_CNTL 0 0xac 1 0 2 IP_REQUEST_EN 0 0 mmDC_PGCNTL_STATUS_REG 0 0xad 0 0 2 mmDMIFV_STATUS 0 0xc3 2 0 2 DMIFV_MC_SEND_ON_IDLE 0 3 DMIFV_CLEAR_MC_SEND_ON_IDLE 8 11 mmDMIF_CONTROL 0 0xc4 10 0 2 DMIF_BUFF_SIZE 0 1 DMIF_GROUP_REQUESTS_IN_CHUNK 2 2 DMIF_DISABLE_EARLY_RECEIVED_LEVEL_COUNT 4 4 DMIF_REQ_BURST_SIZE 8 10 DMIF_UNDERFLOW_RECOVERY_EN 11 11 DMIF_FORCE_TOTAL_REQ_BURST_SIZE 12 16 DMIF_MAX_TOTAL_OUTSTANDING_CHUNK_REQUESTS 17 22 DMIF_DELAY_ARBITRATION 24 28 DMIF_CHUNK_BUFF_MARGIN 29 30 DMIF_PSTATE_URGENT_DISABLE 31 31 mmDMIF_STATUS 0 0xc5 10 0 2 DMIF_MC_SEND_ON_IDLE 0 5 DMIF_CLEAR_MC_SEND_ON_IDLE 8 13 DMIF_MC_LATENCY_COUNTER_ENABLE 15 15 DMIF_MC_LATENCY_COUNTER_URGENT_ONLY 16 16 DMIF_PIPE_EN_FBC_CHUNK_TRACKER 17 19 DMIF_MC_LATENCY_COUNTER_SOURCE_SELECT 20 23 DMIF_PERFORMANCE_COUNTER_SOURCE_SELECT 24 27 DMIF_UNDERFLOW 28 28 DMIF_MC_LATENCY_TAP_POINT 29 30 DMIF_MC_LATENCY_REQ_TYPE 31 31 mmDMIF_ARBITRATION_CONTROL 0 0xc7 2 0 2 DMIF_ARBITRATION_REFERENCE_CLOCK_PERIOD 0 15 PIPE_SWITCH_EFFICIENCY_WEIGHT 16 31 mmPIPE0_ARBITRATION_CONTROL3 0 0xc8 1 0 2 EFFICIENCY_WEIGHT 0 15 mmPIPE1_ARBITRATION_CONTROL3 0 0xc9 1 0 2 EFFICIENCY_WEIGHT 0 15 mmPIPE2_ARBITRATION_CONTROL3 0 0xca 1 0 2 EFFICIENCY_WEIGHT 0 15 mmPIPE3_ARBITRATION_CONTROL3 0 0xcb 1 0 2 EFFICIENCY_WEIGHT 0 15 mmPIPE4_ARBITRATION_CONTROL3 0 0xcc 1 0 2 EFFICIENCY_WEIGHT 0 15 mmPIPE5_ARBITRATION_CONTROL3 0 0xcd 1 0 2 EFFICIENCY_WEIGHT 0 15 mmDMIF_P_VMID 0 0xce 8 0 2 P_VMID_PIPE0 0 3 P_VMID_PIPE1 4 7 P_VMID_PIPE2 8 11 P_VMID_PIPE3 12 15 P_VMID_PIPE4 16 19 P_VMID_PIPE5 20 23 P_VMID_PIPE6 24 27 P_VMID_PIPE7 28 31 mmDMIF_ADDR_CALC 0 0xd1 2 0 2 ADDR_CONFIG_PIPE_INTERLEAVE_SIZE 3 5 ADDR_CONFIG_ROW_SIZE 28 29 mmDMIF_STATUS2 0 0xd2 8 0 2 DMIF_PIPE0_DISPCLK_STATUS 0 0 DMIF_PIPE1_DISPCLK_STATUS 1 1 DMIF_PIPE2_DISPCLK_STATUS 2 2 DMIF_PIPE3_DISPCLK_STATUS 3 3 DMIF_PIPE4_DISPCLK_STATUS 4 4 DMIF_PIPE5_DISPCLK_STATUS 5 5 DMIF_CHUNK_TRACKER_SCLK_STATUS 8 8 DMIF_FBC_TRACKER_SCLK_STATUS 9 9 mmPIPE0_MAX_REQUESTS 0 0xd3 1 0 2 MAX_REQUESTS 0 9 mmPIPE1_MAX_REQUESTS 0 0xd4 1 0 2 MAX_REQUESTS 0 9 mmPIPE2_MAX_REQUESTS 0 0xd5 1 0 2 MAX_REQUESTS 0 9 mmPIPE3_MAX_REQUESTS 0 0xd6 1 0 2 MAX_REQUESTS 0 9 mmPIPE4_MAX_REQUESTS 0 0xd7 1 0 2 MAX_REQUESTS 0 9 mmPIPE5_MAX_REQUESTS 0 0xd8 1 0 2 MAX_REQUESTS 0 9 mmLOW_POWER_TILING_CONTROL 0 0xd9 7 0 2 LOW_POWER_TILING_ENABLE 0 0 LOW_POWER_TILING_MODE 3 4 LOW_POWER_TILING_NUM_PIPES 5 7 LOW_POWER_TILING_NUM_BANKS 8 10 LOW_POWER_TILING_PIPE_INTERLEAVE_SIZE 11 11 LOW_POWER_TILING_ROW_SIZE 12 14 LOW_POWER_TILING_ROWS_PER_CHAN 16 27 mmMCIF_CONTROL 0 0xda 2 0 2 MCIF_MC_LATENCY_COUNTER_ENABLE 30 30 MCIF_MC_LATENCY_COUNTER_URGENT_ONLY 31 31 mmMCIF_WRITE_COMBINE_CONTROL 0 0xdb 1 0 2 MCIF_WRITE_COMBINE_TIMEOUT 0 9 mmMCIF_PHASE0_OUTSTANDING_COUNTER 0 0xde 1 0 2 MCIF_PHASE0_OUTSTANDING_COUNTER 0 26 mmCC_DC_PIPE_DIS 0 0xe0 2 0 2 DC_PIPE_DIS 1 6 DC_UNDERLAY_PIPE_DIS 16 21 mmSMU_WM_CONTROL 0 0xe1 8 0 2 DMIF_WM_CHG_SEL 0 1 DMIF_WM_CHG_REQ 2 2 DMIF_WM_CHG_ACK_INT_DIS 16 16 DMIF_WM_CHG_ACK_INT_STATUS 17 17 MCIF_WB_WM_CHG_SEL 20 21 MCIF_WB_WM_CHG_REQ 22 22 MCIF_WB_WM_CHG_ACK_INT_DIS 24 24 MCIF_WB_WM_CHG_ACK_INT_STATUS 25 25 mmRBBMIF_TIMEOUT 0 0xe2 2 0 2 RBBMIF_TIMEOUT_DELAY 0 19 RBBMIF_TIMEOUT_TO_REQ_HOLD 20 31 mmRBBMIF_STATUS 0 0xe3 5 0 2 RBBMIF_TIMEOUT_CLIENTS_DEC 0 15 RBBMIF_TIMEOUT_OP 28 28 RBBMIF_TIMEOUT_RDWR_STATUS 29 29 RBBMIF_TIMEOUT_ACK 30 30 RBBMIF_TIMEOUT_MASK 31 31 mmRBBMIF_TIMEOUT_DIS 0 0xe4 16 0 2 CLIENT0_TIMEOUT_DIS 0 0 CLIENT1_TIMEOUT_DIS 1 1 CLIENT2_TIMEOUT_DIS 2 2 CLIENT3_TIMEOUT_DIS 3 3 CLIENT4_TIMEOUT_DIS 4 4 CLIENT5_TIMEOUT_DIS 5 5 CLIENT6_TIMEOUT_DIS 6 6 CLIENT7_TIMEOUT_DIS 7 7 CLIENT8_TIMEOUT_DIS 8 8 CLIENT9_TIMEOUT_DIS 9 9 CLIENT10_TIMEOUT_DIS 10 10 CLIENT11_TIMEOUT_DIS 11 11 CLIENT12_TIMEOUT_DIS 12 12 CLIENT13_TIMEOUT_DIS 13 13 CLIENT14_TIMEOUT_DIS 14 14 CLIENT15_TIMEOUT_DIS 15 15 mmDCI_MEM_PWR_STATUS 0 0xe5 11 0 2 DMIF_RDREQ_MEM1_PWR_STATE 0 1 VGA_MEM_PWR_STATE 8 8 DMCU_ERAM_MEM_PWR_STATE 9 10 DMCU_IRAM_MEM_PWR_STATE 11 11 FBC_MEM_PWR_STATE 12 13 DMIF_CURSOR_MEM_PWR_STATE 16 17 DMIF_CURSOR_RD_REQ_MEM_PWR_STATE 18 19 VIP_MEM_PWR_STATE 22 22 DMIF0_ASYNC_MEM_PWR_STATE 24 25 DMIF0_DATA_MEM_PWR_STATE 26 27 DMIF0_CHUNK_MEM_PWR_STATE 28 28 mmDCI_MEM_PWR_STATUS2 0 0xe6 15 0 2 DMIF1_ASYNC_MEM_PWR_STATE 0 1 DMIF1_DATA_MEM_PWR_STATE 2 3 DMIF1_CHUNK_MEM_PWR_STATE 4 4 DMIF2_ASYNC_MEM_PWR_STATE 5 6 DMIF2_DATA_MEM_PWR_STATE 7 8 DMIF2_CHUNK_MEM_PWR_STATE 9 9 DMIF3_ASYNC_MEM_PWR_STATE 10 11 DMIF3_DATA_MEM_PWR_STATE 12 13 DMIF3_CHUNK_MEM_PWR_STATE 14 14 DMIF4_ASYNC_MEM_PWR_STATE 15 16 DMIF4_DATA_MEM_PWR_STATE 17 18 DMIF4_CHUNK_MEM_PWR_STATE 19 19 DMIF5_ASYNC_MEM_PWR_STATE 20 21 DMIF5_DATA_MEM_PWR_STATE 22 23 DMIF5_CHUNK_MEM_PWR_STATE 24 24 mmDCI_CLK_CNTL 0 0xe7 24 0 2 DCI_TEST_CLK_SEL 0 4 DISPCLK_R_DCI_GATE_DIS 5 5 DISPCLK_M_GATE_DIS 6 6 SCLK_G_STREAM_AZ_GATE_DIS 7 7 SCLK_R_AZ_GATE_DIS 8 8 DISPCLK_G_FBC_GATE_DIS 9 9 DISPCLK_G_DMIFV1_L_GATE_DIS 10 10 DISPCLK_G_VGA_GATE_DIS 11 11 DISPCLK_G_DMIFV1_C_GATE_DIS 12 12 DISPCLK_G_VIP_GATE_DIS 13 13 VPCLK_POL 14 14 DISPCLK_G_DMCU_GATE_DIS 15 15 DISPCLK_G_DMIF0_GATE_DIS 16 16 DISPCLK_G_DMIF1_GATE_DIS 17 17 DISPCLK_G_DMIF2_GATE_DIS 18 18 DISPCLK_G_DMIF3_GATE_DIS 19 19 DISPCLK_G_DMIF4_GATE_DIS 20 20 DISPCLK_G_DMIF5_GATE_DIS 21 21 DCEFCLK_G_DMIF_FBCTRK_GATE_DIS 22 22 DCEFCLK_G_DMIFTRK_GATE_DIS 23 23 SCLK_G_CNTL_AZ_GATE_DIS 24 24 DISPCLK_G_DMIFV0_L_GATE_DIS 25 25 DISPCLK_G_DMIFV0_C_GATE_DIS 26 26 DCI_PG_TEST_CLK_SEL 27 31 mmDCI_CLK_CNTL2 0 0xe8 10 0 2 DISPCLK_G_MCIF_DWB_GATE_DIS 0 0 SCLK_G_MCIF_DWB_GATE_DIS 1 1 DISPCLK_G_MCIF_CWB0_GATE_DIS 2 2 SCLK_G_MCIF_CWB0_GATE_DIS 3 3 DISPCLK_G_MCIF_CWB1_GATE_DIS 4 4 DCEFCLK_GATE_DIS 5 5 DCEFCLK_TURN_ON_DELAY 8 11 DCEFCLK_TURN_OFF_DELAY 12 19 CGTT_DCEFCLK_OVERRIDE 20 20 SCLK_G_MCIF_CWB1_GATE_DIS 31 31 mmDCI_MEM_PWR_CNTL 0 0xe9 18 0 2 DMIF_RDREQ_MEM_PWR_FORCE 0 1 DMIF_RDREQ_MEM_PWR_DIS 2 2 VGA_MEM_PWR_FORCE 7 7 VGA_MEM_PWR_DIS 8 8 DMCU_ERAM_MEM_PWR_FORCE 9 10 DMCU_ERAM_MEM_PWR_DIS 11 11 DMCU_IRAM_MEM_PWR_FORCE 12 12 DMCU_IRAM_MEM_PWR_DIS 13 13 FBC_MEM_PWR_FORCE 14 15 FBC_MEM_PWR_DIS 16 16 MCIF_DWB_MEM_PWR_FORCE 20 21 MCIF_DWB_MEM_PWR_DIS 22 22 MCIF_CWB0_MEM_PWR_FORCE 23 24 MCIF_CWB0_MEM_PWR_DIS 25 25 MCIF_CWB1_MEM_PWR_FORCE 26 27 MCIF_CWB1_MEM_PWR_DIS 28 28 VIP_MEM_PWR_FORCE 29 29 VIP_MEM_PWR_DIS 30 30 mmDCI_MEM_PWR_CNTL2 0 0xea 24 0 2 DMIF0_ASYNC_MEM_PWR_FORCE 0 1 DMIF0_ASYNC_MEM_PWR_DIS 2 2 DMIF0_DATA_MEM_PWR_FORCE 3 4 DMIF0_DATA_MEM_PWR_DIS 5 5 DMIF0_CHUNK_MEM_PWR_FORCE 6 6 DMIF0_CHUNK_MEM_PWR_DIS 7 7 DMIF1_ASYNC_MEM_PWR_FORCE 8 9 DMIF1_ASYNC_MEM_PWR_DIS 10 10 DMIF1_DATA_MEM_PWR_FORCE 11 12 DMIF1_DATA_MEM_PWR_DIS 13 13 DMIF1_CHUNK_MEM_PWR_FORCE 14 14 DMIF1_CHUNK_MEM_PWR_DIS 15 15 DMIF2_ASYNC_MEM_PWR_FORCE 16 17 DMIF2_ASYNC_MEM_PWR_DIS 18 18 DMIF2_DATA_MEM_PWR_FORCE 19 20 DMIF2_DATA_MEM_PWR_DIS 21 21 DMIF2_CHUNK_MEM_PWR_FORCE 22 22 DMIF2_CHUNK_MEM_PWR_DIS 23 23 DMIF3_ASYNC_MEM_PWR_FORCE 24 25 DMIF3_ASYNC_MEM_PWR_DIS 26 26 DMIF3_DATA_MEM_PWR_FORCE 27 28 DMIF3_DATA_MEM_PWR_DIS 29 29 DMIF3_CHUNK_MEM_PWR_FORCE 30 30 DMIF3_CHUNK_MEM_PWR_DIS 31 31 mmDCI_MEM_PWR_CNTL3 0 0xeb 20 0 2 DMIF4_ASYNC_MEM_PWR_FORCE 0 1 DMIF4_ASYNC_MEM_PWR_DIS 2 2 DMIF4_DATA_MEM_PWR_FORCE 3 4 DMIF4_DATA_MEM_PWR_DIS 5 5 DMIF4_CHUNK_MEM_PWR_FORCE 6 6 DMIF4_CHUNK_MEM_PWR_DIS 7 7 DMIF5_ASYNC_MEM_PWR_FORCE 8 9 DMIF5_ASYNC_MEM_PWR_DIS 10 10 DMIF5_DATA_MEM_PWR_FORCE 11 12 DMIF5_DATA_MEM_PWR_DIS 13 13 DMIF5_CHUNK_MEM_PWR_FORCE 14 14 DMIF5_CHUNK_MEM_PWR_DIS 15 15 DMIF_RDREQ_MEM_PWR_MODE_SEL 16 17 DMIF_ASYNC_MEM_PWR_MODE_SEL 18 19 DMIF_DATA_MEM_PWR_MODE_SEL 20 21 DMCU_ERAM_MEM_PWR_MODE_SEL 22 22 FBC_MEM_PWR_MODE_SEL 23 24 MCIF_CWB0_MEM_PWR_MODE_SEL 25 26 MCIF_CWB1_MEM_PWR_MODE_SEL 27 28 MCIF_DWB_MEM_PWR_MODE_SEL 29 30 mmPIPE0_DMIF_BUFFER_CONTROL 0 0xef 2 0 2 DMIF_BUFFERS_ALLOCATED 0 2 DMIF_BUFFERS_ALLOCATION_COMPLETED 4 4 mmPIPE1_DMIF_BUFFER_CONTROL 0 0xf0 2 0 2 DMIF_BUFFERS_ALLOCATED 0 2 DMIF_BUFFERS_ALLOCATION_COMPLETED 4 4 mmPIPE2_DMIF_BUFFER_CONTROL 0 0xf1 2 0 2 DMIF_BUFFERS_ALLOCATED 0 2 DMIF_BUFFERS_ALLOCATION_COMPLETED 4 4 mmPIPE3_DMIF_BUFFER_CONTROL 0 0xf2 2 0 2 DMIF_BUFFERS_ALLOCATED 0 2 DMIF_BUFFERS_ALLOCATION_COMPLETED 4 4 mmPIPE4_DMIF_BUFFER_CONTROL 0 0xf3 2 0 2 DMIF_BUFFERS_ALLOCATED 0 2 DMIF_BUFFERS_ALLOCATION_COMPLETED 4 4 mmPIPE5_DMIF_BUFFER_CONTROL 0 0xf4 2 0 2 DMIF_BUFFERS_ALLOCATED 0 2 DMIF_BUFFERS_ALLOCATION_COMPLETED 4 4 mmRBBMIF_STATUS_FLAG 0 0xf5 7 0 2 RBBMIF_STATE 0 1 RBBMIF_READ_TIMEOUT 4 4 RBBMIF_FIFO_EMPTY 5 5 RBBMIF_FIFO_FULL 6 6 RBBMIF_INVALID_ACCESS_FLAG 8 8 RBBMIF_INVALID_ACCESS_TYPE 9 11 RBBMIF_INVALID_ACCESS_ADDR 16 31 mmDCI_SOFT_RESET 0 0xf6 20 0 2 VGA_SOFT_RESET 0 0 VIP_SOFT_RESET 1 1 MCIF_SOFT_RESET 2 2 FBC_SOFT_RESET 3 3 DMIF0_SOFT_RESET 4 4 DMIF1_SOFT_RESET 5 5 DMIF2_SOFT_RESET 6 6 DMIF3_SOFT_RESET 7 7 DMIF4_SOFT_RESET 8 8 DMIF5_SOFT_RESET 9 9 DCFEV0_L_SOFT_RESET 10 10 DCFEV0_C_SOFT_RESET 11 11 DCFEV1_L_SOFT_RESET 12 12 DCFEV1_C_SOFT_RESET 13 13 DMIFARB_SOFT_RESET 14 14 DCHUB_SOFT_RESET 15 15 MCIF_DWB_SOFT_RESET 16 16 MCIF_CWB0_SOFT_RESET 17 17 MCIF_CWB1_SOFT_RESET 18 18 MCIF_WB_SOFT_RESET 19 19 mmDMIF_URG_OVERRIDE 0 0xf7 2 0 2 DMIF_URG_OVERRIDE_EN 0 0 DMIF_URG_OVERRIDE_LEVEL 4 7 mmPIPE6_ARBITRATION_CONTROL3 0 0xf8 1 0 2 EFFICIENCY_WEIGHT 0 15 mmPIPE7_ARBITRATION_CONTROL3 0 0xf9 1 0 2 EFFICIENCY_WEIGHT 0 15 mmPIPE6_MAX_REQUESTS 0 0xfa 1 0 2 MAX_REQUESTS 0 9 mmPIPE7_MAX_REQUESTS 0 0xfb 1 0 2 MAX_REQUESTS 0 9 mmDVMM_REG_RD_STATUS 0 0xfc 1 0 2 DVMM_REG_RD_STATUS 0 0 mmDVMM_REG_RD_DATA 0 0xfd 1 0 2 DVMM_REG_RD_DATA 0 31 mmDVMM_PTE_REQ 0 0xfe 3 0 2 MAX_PTEREQ_TO_ISSUE 0 7 HFLIP_PTEREQ_PER_CHUNK_INT 8 15 HFLIP_PTEREQ_PER_CHUNK_MULTIPLIER 16 21 mmDVMM_CNTL 0 0xff 4 0 2 PDE_CACHE_INVALIDATE_CNTL 0 1 FORCE_SYSTEM_ACCESS_MODE 7 7 OVERRIDE_SNOOP 17 17 ENABLE_PDE_INVALIDATE 18 18 mmDVMM_FAULT_STATUS 0 0x100 1 0 2 DVMM_FAULT_STATUS 0 31 mmDVMM_FAULT_ADDR 0 0x101 1 0 2 DVMM_FAULT_ADDR 0 31 mmFMON_CTRL 0 0x102 10 0 2 FMON_START 0 0 FMON_MODE 1 2 FMON_PSTATE_IGNORE 4 4 FMON_STATUS_IGNORE 5 5 FMON_URG_MODE_GREATER 6 6 FMON_FILTER_UID_EN 7 7 FMON_STATE 8 9 FMON_URG_THRESHOLD 12 15 FMON_FILTER_UID 16 20 FMON_SOF_SEL 24 26 mmDVMM_PTE_PGMEM_CONTROL 0 0x103 17 0 2 DVMM_PTE0_MEM_PWR_FORCE 0 1 DVMM_PTE0_MEM_PWR_DIS 2 2 DVMM_PTE1_MEM_PWR_FORCE 3 4 DVMM_PTE1_MEM_PWR_DIS 5 5 DVMM_PTE2_MEM_PWR_FORCE 6 7 DVMM_PTE2_MEM_PWR_DIS 8 8 DVMM_PTE3_MEM_PWR_FORCE 9 10 DVMM_PTE3_MEM_PWR_DIS 11 11 DVMM_PTE4_MEM_PWR_FORCE 12 13 DVMM_PTE4_MEM_PWR_DIS 14 14 DVMM_PTE5_MEM_PWR_FORCE 15 16 DVMM_PTE5_MEM_PWR_DIS 17 17 DVMM_PTE6_MEM_PWR_FORCE 18 19 DVMM_PTE6_MEM_PWR_DIS 20 20 DVMM_PTE7_MEM_PWR_FORCE 21 22 DVMM_PTE7_MEM_PWR_DIS 23 23 DVMM_PTE_MEM_PWR_MODE_SEL 24 25 mmDVMM_PTE_PGMEM_STATE 0 0x104 8 0 2 DVMM_PIPE0_PTE_PGMEM_STATE 0 1 DVMM_PIPE1_PTE_PGMEM_STATE 2 3 DVMM_PIPE2_PTE_PGMEM_STATE 4 5 DVMM_PIPE3_PTE_PGMEM_STATE 6 7 DVMM_PIPE4_PTE_PGMEM_STATE 8 9 DVMM_PIPE5_PTE_PGMEM_STATE 10 11 DVMM_PIPE6_PTE_PGMEM_STATE 12 13 DVMM_PIPE7_PTE_PGMEM_STATE 14 15 mmMCIF_PHASE1_OUTSTANDING_COUNTER 0 0x105 1 0 2 MCIF_PHASE1_OUTSTANDING_COUNTER 0 26 mmMCIF_PHASE2_OUTSTANDING_COUNTER 0 0x106 1 0 2 MCIF_PHASE2_OUTSTANDING_COUNTER 0 26 mmMCIF_WB_PHASE0_OUTSTANDING_COUNTER 0 0x107 1 0 2 MCIF_WB_PHASE0_OUTSTANDING_COUNTER 0 26 mmMCIF_WB_PHASE1_OUTSTANDING_COUNTER 0 0x108 1 0 2 MCIF_WB_PHASE1_OUTSTANDING_COUNTER 0 26 mmDCI_MEM_PWR_CNTL4 0 0x109 11 0 2 MCIF_DWB_LUMA_MEM_EN_NUM 0 0 MCIF_DWB_CHROMA_MEM_EN_NUM 1 1 MCIF_CWB0_LUMA_MEM_EN_NUM 2 2 MCIF_CWB0_CHROMA_MEM_EN_NUM 3 3 MCIF_CWB1_LUMA_MEM_EN_NUM 4 4 MCIF_CWB1_CHROMA_MEM_EN_NUM 5 5 DMIF_CURSOR_MEM_PWR_FORCE 6 7 DMIF_CURSOR_MEM_PWR_DIS 8 8 DMIF_CURSOR_RD_REQ_MEM_PWR_FORCE 9 10 DMIF_CURSOR_RD_REQ_MEM_PWR_DIS 11 11 DMIF_CURSOR_RD_REQ_MEM_PWR_MODE_SEL 12 13 mmMCIF_WB_MISC_CTRL 0 0x10a 2 0 2 MCIFWB_WR_COMBINE_TIMEOUT_THRESH 0 9 MCIF_WB_SOCCLK_DS_ENABLE 16 16 mmDCI_MEM_PWR_STATUS3 0 0x10b 12 0 2 MCIF_DWB_LUMA_MEM0_PWR_STATE 0 1 MCIF_DWB_LUMA_MEM1_PWR_STATE 2 3 MCIF_DWB_CHROMA_MEM0_PWR_STATE 4 5 MCIF_DWB_CHROMA_MEM1_PWR_STATE 6 7 MCIF_CWB0_LUMA_MEM0_PWR_STATE 8 9 MCIF_CWB0_LUMA_MEM1_PWR_STATE 10 11 MCIF_CWB0_CHROMA_MEM0_PWR_STATE 12 13 MCIF_CWB0_CHROMA_MEM1_PWR_STATE 14 15 MCIF_CWB1_LUMA_MEM0_PWR_STATE 16 17 MCIF_CWB1_LUMA_MEM1_PWR_STATE 18 19 MCIF_CWB1_CHROMA_MEM0_PWR_STATE 20 21 MCIF_CWB1_CHROMA_MEM1_PWR_STATE 22 23 mmDMIF_CURSOR_CONTROL 0 0x10c 5 0 2 ADDRESS_TRANSLATION_ENABLE 4 4 PRIVILEGED_ACCESS_ENABLE 8 8 LOW_READ_URG_LEVEL 16 23 DMIF_CURSOR_MC_LATENCY_COUNTER_ENABLE 30 30 DMIF_CURSOR_MC_LATENCY_COUNTER_URGENT_ONLY 31 31 mmDMIF_CURSOR_MEM_CONTROL 0 0x10d 5 0 2 DMIF_CURSOR_MEM_CACHE_MODE_DIS 0 0 DMIF_CURSOR_MEM_CACHE_MODE 4 5 DMIF_CURSOR_MEM_CACHE_SIZE 8 15 DMIF_CURSOR_MEM_CACHE_PIPE 16 18 DMIF_CURSOR_MEM_CACHE_TYPE 19 20 mmDCHUB_FB_LOCATION 0 0x126 2 0 2 FB_BASE 0 15 FB_TOP 16 31 mmDCHUB_FB_OFFSET 0 0x127 1 0 2 FB_OFFSET 0 21 mmDCHUB_AGP_BASE 0 0x128 1 0 2 AGP_BASE 0 21 mmDCHUB_AGP_BOT 0 0x129 1 0 2 AGP_BOT 0 17 mmDCHUB_AGP_TOP 0 0x12a 1 0 2 AGP_TOP 0 17 mmDCHUB_DRAM_APER_BASE 0 0x12b 2 0 2 BASE 0 23 LOCK_DCHUB_DRAM_REGS 28 28 mmDCHUB_DRAM_APER_DEF 0 0x12c 1 0 2 DEF 0 31 mmDCHUB_DRAM_APER_TOP 0 0x12d 1 0 2 TOP 0 23 mmDCHUB_CONTROL_STATUS 0 0x12e 10 0 2 NO_OUTSTANDING_REQ 0 0 SDP_PORT_STATUS 4 5 SDP_DATA_RESPONSE_STATUS 6 8 SDP_REQ_CREDIT_ERROR 9 9 SDP_DATA_RESPONSE_STATUS_CLEAR 12 12 SDP_REQ_CREDIT_ERROR_CLEAR 13 13 FLUSH_REQ_CREDIT_EN 16 16 REQ_CREDIT_EN 17 17 DCE_PORT_CONTROL 18 18 SDP_CREDIT_DISCONNECT_DELAY 20 25 mmWB_ENABLE 0 0x212 1 0 2 WB_ENABLE 0 0 mmWB_EC_CONFIG 0 0x213 18 0 2 DISPCLK_R_WB_GATE_DIS 0 0 DISPCLK_G_WB_GATE_DIS 1 1 DISPCLK_G_WBSCL_GATE_DIS 2 2 WB_TEST_CLK_SEL 3 6 WB_LB_LS_DIS 7 7 WB_LB_SD_DIS 8 8 WB_LUT_LS_DIS 9 9 WBSCL_LB_MEM_PWR_MODE_SEL 12 13 WBSCL_LB_MEM_PWR_DIS 14 14 WBSCL_LB_MEM_PWR_FORCE 15 16 WBSCL_LB_MEM_PWR_STATE_SM 17 18 WBSCL_LB_MEM_PWR_STATE_BG 19 20 WBSCL_LB_MEM_PWR_STATE 21 22 WB_RAM_PW_SAVE_MODE 23 23 LB_MEM_PWR_STATE_SM 24 25 LB_MEM_PWR_STATE_BG 26 27 LB_MEM_PWR_STATE 28 29 LUT_MEM_PWR_STATE 30 31 mmCNV_MODE 0 0x214 10 0 2 CNV_FRAME_CAPTURE_RATE 8 9 CNV_WINDOW_CROP_EN 12 12 CNV_STEREO_TYPE 13 14 CNV_INTERLACED_MODE 15 15 CNV_EYE_SELECTION 16 17 CNV_STEREO_POLARITY 18 18 CNV_INTERLACED_FIELD_ORDER 19 19 CNV_STEREO_SPLIT 20 20 CNV_NEW_CONTENT 24 24 CNV_FRAME_CAPTURE_EN 31 31 mmCNV_WINDOW_START 0 0x215 2 0 2 CNV_WINDOW_START_X 0 11 CNV_WINDOW_START_Y 16 27 mmCNV_WINDOW_SIZE 0 0x216 2 0 2 CNV_WINDOW_WIDTH 0 11 CNV_WINDOW_HEIGHT 16 27 mmCNV_UPDATE 0 0x217 3 0 2 CNV_UPDATE_PENDING 0 0 CNV_UPDATE_TAKEN 8 8 CNV_UPDATE_LOCK 16 16 mmCNV_SOURCE_SIZE 0 0x218 2 0 2 CNV_SOURCE_WIDTH 0 14 CNV_SOURCE_HEIGHT 16 30 mmCNV_CSC_CONTROL 0 0x219 1 0 2 CNV_CSC_BYPASS 0 0 mmCNV_CSC_C11_C12 0 0x21a 2 0 2 CNV_CSC_C11 0 12 CNV_CSC_C12 16 28 mmCNV_CSC_C13_C14 0 0x21b 2 0 2 CNV_CSC_C13 0 12 CNV_CSC_C14 16 30 mmCNV_CSC_C21_C22 0 0x21c 2 0 2 CNV_CSC_C21 0 12 CNV_CSC_C22 16 28 mmCNV_CSC_C23_C24 0 0x21d 2 0 2 CNV_CSC_C23 0 12 CNV_CSC_C24 16 30 mmCNV_CSC_C31_C32 0 0x21e 2 0 2 CNV_CSC_C31 0 12 CNV_CSC_C32 16 28 mmCNV_CSC_C33_C34 0 0x21f 2 0 2 CNV_CSC_C33 0 12 CNV_CSC_C34 16 30 mmCNV_CSC_ROUND_OFFSET_R 0 0x220 1 0 2 CNV_CSC_ROUND_OFFSET_R 0 15 mmCNV_CSC_ROUND_OFFSET_G 0 0x221 1 0 2 CNV_CSC_ROUND_OFFSET_G 0 15 mmCNV_CSC_ROUND_OFFSET_B 0 0x222 1 0 2 CNV_CSC_ROUND_OFFSET_B 0 15 mmCNV_CSC_CLAMP_R 0 0x223 2 0 2 CNV_CSC_CLAMP_UPPER_R 0 15 CNV_CSC_CLAMP_LOWER_R 16 31 mmCNV_CSC_CLAMP_G 0 0x224 2 0 2 CNV_CSC_CLAMP_UPPER_G 0 15 CNV_CSC_CLAMP_LOWER_G 16 31 mmCNV_CSC_CLAMP_B 0 0x225 2 0 2 CNV_CSC_CLAMP_UPPER_B 0 15 CNV_CSC_CLAMP_LOWER_B 16 31 mmCNV_TEST_CNTL 0 0x226 3 0 2 CNV_TEST_CRC_EN 4 4 CNV_TEST_CRC_CONT_EN 8 8 CNV_TEST_CRC_DE_ONLY 16 16 mmCNV_TEST_CRC_RED 0 0x227 2 0 2 CNV_TEST_CRC_RED_MASK 4 15 CNV_TEST_CRC_SIG_RED 16 31 mmCNV_TEST_CRC_GREEN 0 0x228 2 0 2 CNV_TEST_CRC_GREEN_MASK 4 15 CNV_TEST_CRC_SIG_GREEN 16 31 mmCNV_TEST_CRC_BLUE 0 0x229 2 0 2 CNV_TEST_CRC_BLUE_MASK 4 15 CNV_TEST_CRC_SIG_BLUE 16 31 mmCNV_INPUT_SELECT 0 0x22d 2 0 2 CNV_INPUT_SRC_SELECT 0 1 CNV_INPUT_PIPE_SELECT 2 4 mmWB_SOFT_RESET 0 0x230 1 0 2 WB_SOFT_RESET 0 0 mmWB_WARM_UP_MODE_CTL1 0 0x231 3 0 2 WIDTH_WARMUP 0 14 HEIGHT_WARMUP 16 30 GMC_WARM_UP_ENABLE 31 31 mmWB_WARM_UP_MODE_CTL2 0 0x232 2 0 2 DATA_VALUE_WARMUP 0 7 MODE_WARMUP 8 8 mmWBSCL_COEF_RAM_SELECT 0 0x242 3 0 2 WBSCL_COEF_RAM_TAP_PAIR_IDX 0 2 WBSCL_COEF_RAM_PHASE 8 11 WBSCL_COEF_RAM_FILTER_TYPE 16 17 mmWBSCL_COEF_RAM_TAP_DATA 0 0x243 4 0 2 WBSCL_COEF_RAM_EVEN_TAP_COEF 0 13 WBSCL_COEF_RAM_EVEN_TAP_COEF_EN 15 15 WBSCL_COEF_RAM_ODD_TAP_COEF 16 29 WBSCL_COEF_RAM_ODD_TAP_COEF_EN 31 31 mmWBSCL_MODE 0 0x244 1 0 2 WBSCL_MODE 0 1 mmWBSCL_TAP_CONTROL 0 0x245 4 0 2 WBSCL_V_NUM_OF_TAPS_Y_RGB 0 3 WBSCL_V_NUM_OF_TAPS_CBCR 4 7 WBSCL_H_NUM_OF_TAPS_Y_RGB 8 11 WBSCL_H_NUM_OF_TAPS_CBCR 12 15 mmWBSCL_DEST_SIZE 0 0x246 2 0 2 WBSCL_DEST_HEIGHT 0 14 WBSCL_DEST_WIDTH 16 30 mmWBSCL_HORZ_FILTER_SCALE_RATIO 0 0x247 1 0 2 WBSCL_H_SCALE_RATIO 0 26 mmWBSCL_HORZ_FILTER_INIT_Y_RGB 0 0x248 2 0 2 WBSCL_H_INIT_FRAC_Y_RGB 0 23 WBSCL_H_INIT_INT_Y_RGB 24 28 mmWBSCL_HORZ_FILTER_INIT_CBCR 0 0x249 2 0 2 WBSCL_H_INIT_FRAC_CBCR 0 23 WBSCL_H_INIT_INT_CBCR 24 28 mmWBSCL_VERT_FILTER_SCALE_RATIO 0 0x24a 1 0 2 WBSCL_V_SCALE_RATIO 0 26 mmWBSCL_VERT_FILTER_INIT_Y_RGB 0 0x24b 2 0 2 WBSCL_V_INIT_FRAC_Y_RGB 0 23 WBSCL_V_INIT_INT_Y_RGB 24 28 mmWBSCL_VERT_FILTER_INIT_CBCR 0 0x24c 2 0 2 WBSCL_V_INIT_FRAC_CBCR 0 23 WBSCL_V_INIT_INT_CBCR 24 28 mmWBSCL_ROUND_OFFSET 0 0x24d 2 0 2 WBSCL_ROUND_OFFSET_Y_RGB 0 15 WBSCL_ROUND_OFFSET_CBCR 16 31 mmWBSCL_CLAMP 0 0x24e 4 0 2 WBSCL_CLAMP_UPPER_Y_RGB 0 7 WBSCL_CLAMP_LOWER_Y_RGB 8 15 WBSCL_CLAMP_UPPER_CBCR 16 23 WBSCL_CLAMP_LOWER_CBCR 24 31 mmWBSCL_OVERFLOW_STATUS 0 0x24f 5 0 2 WBSCL_DATA_OVERFLOW_FLAG 0 0 WBSCL_DATA_OVERFLOW_ACK 8 8 WBSCL_DATA_OVERFLOW_MASK 12 12 WBSCL_DATA_OVERFLOW_INT_STATUS 16 16 WBSCL_DATA_OVERFLOW_INT_TYPE 20 20 mmWBSCL_COEF_RAM_CONFLICT_STATUS 0 0x250 5 0 2 WBSCL_HOST_CONFLICT_FLAG 0 0 WBSCL_HOST_CONFLICT_ACK 8 8 WBSCL_HOST_CONFLICT_MASK 12 12 WBSCL_HOST_CONFLICT_INT_STATUS 16 16 WBSCL_HOST_CONFLICT_INT_TYPE 20 20 mmWBSCL_OUTSIDE_PIX_STRATEGY 0 0x251 4 0 2 WBSCL_OUTSIDE_PIX_STRATEGY 0 0 WBSCL_BLACK_COLOR_B_CB 8 15 WBSCL_BLACK_COLOR_G_Y 16 23 WBSCL_BLACK_COLOR_R_CR 24 31 mmWBSCL_TEST_CNTL 0 0x252 3 0 2 WBSCL_TEST_CRC_EN 4 4 WBSCL_TEST_CRC_CONT_EN 8 8 WBSCL_TEST_CRC_DE_ONLY 16 16 mmWBSCL_TEST_CRC_RED 0 0x253 2 0 2 WBSCL_TEST_CRC_RED_MASK 8 15 WBSCL_TEST_CRC_SIG_RED 16 31 mmWBSCL_TEST_CRC_GREEN 0 0x254 2 0 2 WBSCL_TEST_CRC_GREEN_MASK 0 15 WBSCL_TEST_CRC_SIG_GREEN 16 31 mmWBSCL_TEST_CRC_BLUE 0 0x255 2 0 2 WBSCL_TEST_CRC_BLUE_MASK 8 15 WBSCL_TEST_CRC_SIG_BLUE 16 31 mmWBSCL_BACKPRESSURE_CNT_EN 0 0x256 1 0 2 WBSCL_BACKPRESSURE_CNT_EN 0 0 mmWB_MCIF_BACKPRESSURE_CNT 0 0x257 2 0 2 WB_MCIF_Y_MAX_BACKPRESSURE 0 15 WB_MCIF_C_MAX_BACKPRESSURE 16 31 mmWBSCL_RAM_SHUTDOWN 0 0x25a 1 0 2 WBSCL_RAM_SHUTDOWN_SEL 0 1 mmDMCU_CTRL 0 0x3b6 7 0 2 RESET_UC 0 0 IGNORE_PWRMGT 1 1 DISABLE_IRQ_TO_UC 2 2 DISABLE_XIRQ_TO_UC 3 3 DMCU_ENABLE 4 4 DMCU_DYN_CLK_GATING_EN 8 8 UC_REG_RD_TIMEOUT 16 31 mmDMCU_STATUS 0 0x3b7 3 0 2 UC_IN_RESET 0 0 UC_IN_WAIT_MODE 1 1 UC_IN_STOP_MODE 2 2 mmDMCU_PC_START_ADDR 0 0x3b8 2 0 2 PC_START_ADDR_LSB 0 7 PC_START_ADDR_MSB 8 15 mmDMCU_FW_START_ADDR 0 0x3b9 2 0 2 FW_START_ADDR_LSB 0 7 FW_START_ADDR_MSB 8 15 mmDMCU_FW_END_ADDR 0 0x3ba 2 0 2 FW_END_ADDR_LSB 0 7 FW_END_ADDR_MSB 8 15 mmDMCU_FW_ISR_START_ADDR 0 0x3bb 2 0 2 FW_ISR_START_ADDR_LSB 0 7 FW_ISR_START_ADDR_MSB 8 15 mmDMCU_FW_CS_HI 0 0x3bc 1 0 2 FW_CHECKSUM_HI 0 31 mmDMCU_FW_CS_LO 0 0x3bd 1 0 2 FW_CHECKSUM_LO 0 31 mmDMCU_RAM_ACCESS_CTRL 0 0x3be 6 0 2 ERAM_WR_ADDR_AUTO_INC 0 0 ERAM_RD_ADDR_AUTO_INC 1 1 IRAM_WR_ADDR_AUTO_INC 2 2 IRAM_RD_ADDR_AUTO_INC 3 3 ERAM_HOST_ACCESS_EN 4 4 IRAM_HOST_ACCESS_EN 5 5 mmDMCU_ERAM_WR_CTRL 0 0x3bf 3 0 2 ERAM_WR_ADDR 0 15 ERAM_WR_BE 16 19 ERAM_WR_BYTE_MODE 20 20 mmDMCU_ERAM_WR_DATA 0 0x3c0 1 0 2 ERAM_WR_DATA 0 31 mmDMCU_ERAM_RD_CTRL 0 0x3c1 3 0 2 ERAM_RD_ADDR 0 15 ERAM_RD_BE 16 19 ERAM_RD_BYTE_MODE 20 20 mmDMCU_ERAM_RD_DATA 0 0x3c2 1 0 2 ERAM_RD_DATA 0 31 mmDMCU_IRAM_WR_CTRL 0 0x3c3 1 0 2 IRAM_WR_ADDR 0 9 mmDMCU_IRAM_WR_DATA 0 0x3c4 1 0 2 IRAM_WR_DATA 0 7 mmDMCU_IRAM_RD_CTRL 0 0x3c5 1 0 2 IRAM_RD_ADDR 0 9 mmDMCU_IRAM_RD_DATA 0 0x3c6 1 0 2 IRAM_RD_DATA 0 7 mmDMCU_EVENT_TRIGGER 0 0x3c7 3 0 2 GEN_SW_INT_TO_UC 0 0 UC_INTERNAL_INT_CODE 16 22 GEN_UC_INTERNAL_INT_TO_HOST 23 23 mmDMCU_UC_INTERNAL_INT_STATUS 0 0x3c8 16 0 2 UC_INT_IRQ_N_PIN 0 0 UC_INT_XIRQ_N_PIN 1 1 UC_INT_SOFTWARE_INTERRUPT 2 2 UC_INT_ILLEGAL_OPCODE_TRAP 3 3 UC_INT_TIMER_OUTPUT_COMPARE_4 4 4 UC_INT_TIMER_OUTPUT_COMPARE_3 5 5 UC_INT_TIMER_OUTPUT_COMPARE_2 6 6 UC_INT_TIMER_OUTPUT_COMPARE_1 7 7 UC_INT_TIMER_OVERFLOW 8 8 UC_INT_REAL_TIME_INTERRUPT 9 9 UC_INT_TIMER_INPUT_CAPTURE_4_OUTPUT_COMPARE_5 10 10 UC_INT_TIMER_INPUT_CAPTURE_3 11 11 UC_INT_TIMER_INPUT_CAPTURE_2 12 12 UC_INT_TIMER_INPUT_CAPTURE_1 13 13 UC_INT_PULSE_ACCUMULATOR_INPUT_EDGE 14 14 UC_INT_PULSE_ACCUMULATOR_OVERFLOW 15 15 mmDMCU_SS_INTERRUPT_CNTL_STATUS 0 0x3c9 18 0 2 STATIC_SCREEN1_INT_STATUS 13 13 STATIC_SCREEN1_INT_OCCURRED 14 14 STATIC_SCREEN1_INT_CLEAR 14 14 STATIC_SCREEN2_INT_STATUS 15 15 STATIC_SCREEN2_INT_OCCURRED 16 16 STATIC_SCREEN2_INT_CLEAR 16 16 STATIC_SCREEN3_INT_STATUS 17 17 STATIC_SCREEN3_INT_OCCURRED 18 18 STATIC_SCREEN3_INT_CLEAR 18 18 STATIC_SCREEN4_INT_STATUS 19 19 STATIC_SCREEN4_INT_OCCURRED 20 20 STATIC_SCREEN4_INT_CLEAR 20 20 STATIC_SCREEN5_INT_STATUS 21 21 STATIC_SCREEN5_INT_OCCURRED 22 22 STATIC_SCREEN5_INT_CLEAR 22 22 STATIC_SCREEN6_INT_STATUS 23 23 STATIC_SCREEN6_INT_OCCURRED 24 24 STATIC_SCREEN6_INT_CLEAR 24 24 mmDMCU_INTERRUPT_STATUS 0 0x3ca 54 0 2 ABM1_HG_READY_INT_OCCURRED 0 0 ABM1_HG_READY_INT_CLEAR 0 0 ABM1_LS_READY_INT_OCCURRED 1 1 ABM1_LS_READY_INT_CLEAR 1 1 ABM1_BL_UPDATE_INT_OCCURRED 2 2 ABM1_BL_UPDATE_INT_CLEAR 2 2 MCP_INT_OCCURRED 3 3 DCPG_IHC_DSI_POWER_UP_INT_OCCURRED 4 4 DCPG_IHC_DSI_POWER_UP_INT_CLEAR 4 4 DCPG_IHC_DSI_POWER_DOWN_INT_OCCURRED 5 5 DCPG_IHC_DSI_POWER_DOWN_INT_CLEAR 5 5 EXTERNAL_SW_INT_OCCURRED 8 8 EXTERNAL_SW_INT_CLEAR 8 8 SCP_INT_OCCURRED 9 9 UC_INTERNAL_INT_OCCURRED 10 10 UC_INTERNAL_INT_CLEAR 10 10 UC_REG_RD_TIMEOUT_INT_OCCURRED 11 11 UC_REG_RD_TIMEOUT_INT_CLEAR 11 11 DCPG_IHC_DCFE0_POWER_UP_INT_OCCURRED 12 12 DCPG_IHC_DCFE0_POWER_UP_INT_CLEAR 12 12 DCPG_IHC_DCFE1_POWER_UP_INT_OCCURRED 13 13 DCPG_IHC_DCFE1_POWER_UP_INT_CLEAR 13 13 DCPG_IHC_DCFE2_POWER_UP_INT_OCCURRED 14 14 DCPG_IHC_DCFE2_POWER_UP_INT_CLEAR 14 14 DCPG_IHC_DCFE3_POWER_UP_INT_OCCURRED 15 15 DCPG_IHC_DCFE3_POWER_UP_INT_CLEAR 15 15 DCPG_IHC_DCFE4_POWER_UP_INT_OCCURRED 16 16 DCPG_IHC_DCFE4_POWER_UP_INT_CLEAR 16 16 DCPG_IHC_DCFE5_POWER_UP_INT_OCCURRED 17 17 DCPG_IHC_DCFE5_POWER_UP_INT_CLEAR 17 17 DCPG_IHC_DCFE0_POWER_DOWN_INT_OCCURRED 18 18 DCPG_IHC_DCFE0_POWER_DOWN_INT_CLEAR 18 18 DCPG_IHC_DCFE1_POWER_DOWN_INT_OCCURRED 19 19 DCPG_IHC_DCFE1_POWER_DOWN_INT_CLEAR 19 19 DCPG_IHC_DCFE2_POWER_DOWN_INT_OCCURRED 20 20 DCPG_IHC_DCFE2_POWER_DOWN_INT_CLEAR 20 20 DCPG_IHC_DCFE3_POWER_DOWN_INT_OCCURRED 21 21 DCPG_IHC_DCFE3_POWER_DOWN_INT_CLEAR 21 21 DCPG_IHC_DCFE4_POWER_DOWN_INT_OCCURRED 22 22 DCPG_IHC_DCFE4_POWER_DOWN_INT_CLEAR 22 22 DCPG_IHC_DCFE5_POWER_DOWN_INT_OCCURRED 23 23 DCPG_IHC_DCFE5_POWER_DOWN_INT_CLEAR 23 23 VBLANK1_INT_OCCURRED 24 24 VBLANK1_INT_CLEAR 24 24 VBLANK2_INT_OCCURRED 25 25 VBLANK2_INT_CLEAR 25 25 VBLANK3_INT_OCCURRED 26 26 VBLANK3_INT_CLEAR 26 26 VBLANK4_INT_OCCURRED 27 27 VBLANK4_INT_CLEAR 27 27 VBLANK5_INT_OCCURRED 28 28 VBLANK5_INT_CLEAR 28 28 VBLANK6_INT_OCCURRED 29 29 VBLANK6_INT_CLEAR 29 29 mmDMCU_INTERRUPT_TO_HOST_EN_MASK 0 0x3cb 6 0 2 ABM1_HG_READY_INT_MASK 0 0 ABM1_LS_READY_INT_MASK 1 1 ABM1_BL_UPDATE_INT_MASK 2 2 SCP_INT_MASK 9 9 UC_INTERNAL_INT_MASK 10 10 UC_REG_RD_TIMEOUT_INT_MASK 11 11 mmDMCU_INTERRUPT_TO_UC_EN_MASK 0 0x3cc 31 0 2 ABM1_HG_READY_INT_TO_UC_EN 0 0 ABM1_LS_READY_INT_TO_UC_EN 1 1 ABM1_BL_UPDATE_INT_TO_UC_EN 2 2 MCP_INT_TO_UC_EN 3 3 DCPG_IHC_DSI_POWER_UP_INT_TO_UC_EN 4 4 DCPG_IHC_DSI_POWER_DOWN_INT_TO_UC_EN 5 5 STATIC_SCREEN1_INT_TO_UC_EN 6 6 STATIC_SCREEN2_INT_TO_UC_EN 7 7 EXTERNAL_SW_INT_TO_UC_EN 8 8 STATIC_SCREEN3_INT_TO_UC_EN 9 9 STATIC_SCREEN4_INT_TO_UC_EN 10 10 STATIC_SCREEN5_INT_TO_UC_EN 11 11 DCPG_IHC_DCFE0_POWER_UP_INT_TO_UC_EN 12 12 DCPG_IHC_DCFE1_POWER_UP_INT_TO_UC_EN 13 13 DCPG_IHC_DCFE2_POWER_UP_INT_TO_UC_EN 14 14 DCPG_IHC_DCFE3_POWER_UP_INT_TO_UC_EN 15 15 DCPG_IHC_DCFE4_POWER_UP_INT_TO_UC_EN 16 16 DCPG_IHC_DCFE5_POWER_UP_INT_TO_UC_EN 17 17 DCPG_IHC_DCFE0_POWER_DOWN_INT_TO_UC_EN 18 18 DCPG_IHC_DCFE1_POWER_DOWN_INT_TO_UC_EN 19 19 DCPG_IHC_DCFE2_POWER_DOWN_INT_TO_UC_EN 20 20 DCPG_IHC_DCFE3_POWER_DOWN_INT_TO_UC_EN 21 21 DCPG_IHC_DCFE4_POWER_DOWN_INT_TO_UC_EN 22 22 DCPG_IHC_DCFE5_POWER_DOWN_INT_TO_UC_EN 23 23 VBLANK1_INT_TO_UC_EN 24 24 VBLANK2_INT_TO_UC_EN 25 25 VBLANK3_INT_TO_UC_EN 26 26 VBLANK4_INT_TO_UC_EN 27 27 VBLANK5_INT_TO_UC_EN 28 28 VBLANK6_INT_TO_UC_EN 29 29 STATIC_SCREEN6_INT_TO_UC_EN 30 30 mmDMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL 0 0x3cd 31 0 2 ABM1_HG_READY_INT_XIRQ_IRQ_SEL 0 0 ABM1_LS_READY_INT_XIRQ_IRQ_SEL 1 1 ABM1_BL_UPDATE_INT_XIRQ_IRQ_SEL 2 2 MCP_INT_XIRQ_IRQ_SEL 3 3 DCPG_IHC_DSI_POWER_UP_INT_XIRQ_IRQ_SEL 4 4 DCPG_IHC_DSI_POWER_DOWN_INT_XIRQ_IRQ_SEL 5 5 STATIC_SCREEN1_INT_XIRQ_IRQ_SEL 6 6 STATIC_SCREEN2_INT_XIRQ_IRQ_SEL 7 7 EXTERNAL_SW_INT_XIRQ_IRQ_SEL 8 8 STATIC_SCREEN3_INT_XIRQ_IRQ_SEL 9 9 STATIC_SCREEN4_INT_XIRQ_IRQ_SEL 10 10 STATIC_SCREEN5_INT_XIRQ_IRQ_SEL 11 11 DCPG_IHC_DCFE0_POWER_UP_INT_XIRQ_IRQ_SEL 12 12 DCPG_IHC_DCFE1_POWER_UP_INT_XIRQ_IRQ_SEL 13 13 DCPG_IHC_DCFE2_POWER_UP_INT_XIRQ_IRQ_SEL 14 14 DCPG_IHC_DCFE3_POWER_UP_INT_XIRQ_IRQ_SEL 15 15 DCPG_IHC_DCFE4_POWER_UP_INT_XIRQ_IRQ_SEL 16 16 DCPG_IHC_DCFE5_POWER_UP_INT_XIRQ_IRQ_SEL 17 17 DCPG_IHC_DCFE0_POWER_DOWN_INT_XIRQ_IRQ_SEL 18 18 DCPG_IHC_DCFE1_POWER_DOWN_INT_XIRQ_IRQ_SEL 19 19 DCPG_IHC_DCFE2_POWER_DOWN_INT_XIRQ_IRQ_SEL 20 20 DCPG_IHC_DCFE3_POWER_DOWN_INT_XIRQ_IRQ_SEL 21 21 DCPG_IHC_DCFE4_POWER_DOWN_INT_XIRQ_IRQ_SEL 22 22 DCPG_IHC_DCFE5_POWER_DOWN_INT_XIRQ_IRQ_SEL 23 23 VBLANK1_INT_XIRQ_IRQ_SEL 24 24 VBLANK2_INT_XIRQ_IRQ_SEL 25 25 VBLANK3_INT_XIRQ_IRQ_SEL 26 26 VBLANK4_INT_XIRQ_IRQ_SEL 27 27 VBLANK5_INT_XIRQ_IRQ_SEL 28 28 VBLANK6_INT_XIRQ_IRQ_SEL 29 29 STATIC_SCREEN6_INT_XIRQ_IRQ_SEL 30 30 mmDC_DMCU_SCRATCH 0 0x3ce 1 0 2 DMCU_SCRATCH 0 31 mmDMCU_INT_CNT 0 0x3cf 3 0 2 DMCU_ABM1_HG_READY_INT_CNT 0 7 DMCU_ABM1_LS_READY_INT_CNT 8 15 DMCU_ABM1_BL_UPDATE_INT_CNT 16 23 mmDMCU_FW_CHECKSUM_SMPL_BYTE_POS 0 0x3d0 2 0 2 DMCU_FW_CHECKSUM_LO_SMPL_BYTE_POS 0 1 DMCU_FW_CHECKSUM_HI_SMPL_BYTE_POS 2 3 mmDMCU_UC_CLK_GATING_CNTL 0 0x3d1 3 0 2 UC_IRAM_RD_DELAY 0 2 UC_ERAM_RD_DELAY 8 10 UC_RBBM_RD_CLK_GATING_EN 16 16 mmMASTER_COMM_DATA_REG1 0 0x3d2 4 0 2 MASTER_COMM_DATA_REG1_BYTE0 0 7 MASTER_COMM_DATA_REG1_BYTE1 8 15 MASTER_COMM_DATA_REG1_BYTE2 16 23 MASTER_COMM_DATA_REG1_BYTE3 24 31 mmMASTER_COMM_DATA_REG2 0 0x3d3 4 0 2 MASTER_COMM_DATA_REG2_BYTE0 0 7 MASTER_COMM_DATA_REG2_BYTE1 8 15 MASTER_COMM_DATA_REG2_BYTE2 16 23 MASTER_COMM_DATA_REG2_BYTE3 24 31 mmMASTER_COMM_DATA_REG3 0 0x3d4 4 0 2 MASTER_COMM_DATA_REG3_BYTE0 0 7 MASTER_COMM_DATA_REG3_BYTE1 8 15 MASTER_COMM_DATA_REG3_BYTE2 16 23 MASTER_COMM_DATA_REG3_BYTE3 24 31 mmMASTER_COMM_CMD_REG 0 0x3d5 4 0 2 MASTER_COMM_CMD_REG_BYTE0 0 7 MASTER_COMM_CMD_REG_BYTE1 8 15 MASTER_COMM_CMD_REG_BYTE2 16 23 MASTER_COMM_CMD_REG_BYTE3 24 31 mmMASTER_COMM_CNTL_REG 0 0x3d6 1 0 2 MASTER_COMM_INTERRUPT 0 0 mmSLAVE_COMM_DATA_REG1 0 0x3d7 4 0 2 SLAVE_COMM_DATA_REG1_BYTE0 0 7 SLAVE_COMM_DATA_REG1_BYTE1 8 15 SLAVE_COMM_DATA_REG1_BYTE2 16 23 SLAVE_COMM_DATA_REG1_BYTE3 24 31 mmSLAVE_COMM_DATA_REG2 0 0x3d8 4 0 2 SLAVE_COMM_DATA_REG2_BYTE0 0 7 SLAVE_COMM_DATA_REG2_BYTE1 8 15 SLAVE_COMM_DATA_REG2_BYTE2 16 23 SLAVE_COMM_DATA_REG2_BYTE3 24 31 mmSLAVE_COMM_DATA_REG3 0 0x3d9 4 0 2 SLAVE_COMM_DATA_REG3_BYTE0 0 7 SLAVE_COMM_DATA_REG3_BYTE1 8 15 SLAVE_COMM_DATA_REG3_BYTE2 16 23 SLAVE_COMM_DATA_REG3_BYTE3 24 31 mmSLAVE_COMM_CMD_REG 0 0x3da 4 0 2 SLAVE_COMM_CMD_REG_BYTE0 0 7 SLAVE_COMM_CMD_REG_BYTE1 8 15 SLAVE_COMM_CMD_REG_BYTE2 16 23 SLAVE_COMM_CMD_REG_BYTE3 24 31 mmSLAVE_COMM_CNTL_REG 0 0x3db 2 0 2 SLAVE_COMM_INTERRUPT 0 0 COMM_PORT_MSG_TO_HOST_IN_PROGRESS 8 8 mmBL1_PWM_AMBIENT_LIGHT_LEVEL 0 0x3de 1 0 2 BL1_PWM_AMBIENT_LIGHT_LEVEL 0 16 mmBL1_PWM_USER_LEVEL 0 0x3df 1 0 2 BL1_PWM_USER_LEVEL 0 16 mmBL1_PWM_TARGET_ABM_LEVEL 0 0x3e0 1 0 2 BL1_PWM_TARGET_ABM_LEVEL 0 16 mmBL1_PWM_CURRENT_ABM_LEVEL 0 0x3e1 1 0 2 BL1_PWM_CURRENT_ABM_LEVEL 0 16 mmBL1_PWM_FINAL_DUTY_CYCLE 0 0x3e2 1 0 2 BL1_PWM_FINAL_DUTY_CYCLE 0 16 mmBL1_PWM_MINIMUM_DUTY_CYCLE 0 0x3e3 1 0 2 BL1_PWM_MINIMUM_DUTY_CYCLE 0 16 mmBL1_PWM_ABM_CNTL 0 0x3e4 5 0 2 BL1_PWM_USE_ABM_EN 0 0 BL1_PWM_USE_AMBIENT_LEVEL_EN 1 1 BL1_PWM_AUTO_UPDATE_CURRENT_ABM_LEVEL_EN 2 2 BL1_PWM_AUTO_CALC_FINAL_DUTY_CYCLE_EN 3 3 BL1_PWM_AUTO_UPDATE_CURRENT_ABM_STEP_SIZE 16 31 mmBL1_PWM_BL_UPDATE_SAMPLE_RATE 0 0x3e5 5 0 2 BL1_PWM_BL_UPDATE_SAMPLE_RATE_COUNT_EN 0 0 BL1_PWM_BL_UPDATE_RESET_SAMPLE_RATE_FRAME_COUNTER 1 1 BL1_PWM_BL_UPDATE_SAMPLE_RATE_FRAME_COUNT 8 15 BL1_PWM_BL_UPDATE_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET 16 23 ABM1_HGLS_REG_LOCK 31 31 mmBL1_PWM_GRP2_REG_LOCK 0 0x3e6 6 0 2 BL1_PWM_GRP2_REG_LOCK 0 0 BL1_PWM_GRP2_REG_UPDATE_PENDING 8 8 BL1_PWM_GRP2_UPDATE_AT_FRAME_START 16 16 BL1_PWM_GRP2_FRAME_START_DISP_SEL 17 19 BL1_PWM_GRP2_READBACK_DB_REG_VALUE_EN 24 24 BL1_PWM_GRP2_IGNORE_MASTER_LOCK_EN 31 31 mmDMCU_INTERRUPT_TO_UC_EN_MASK_1 0 0x3e7 13 0 2 DCPG_IHC_DCFEV0_POWER_UP_INT_TO_UC_EN 0 0 DCPG_IHC_DCFEV0_POWER_DOWN_INT_TO_UC_EN 1 1 DCFEV0_VBLANK_INT_TO_UC_EN 2 2 DCPG_IHC_DCFEV1_POWER_UP_INT_TO_UC_EN 3 3 DCPG_IHC_DCFEV1_POWER_DOWN_INT_TO_UC_EN 4 4 DCFEV1_VBLANK_INT_TO_UC_EN 5 5 CRTC0_RANGE_TIMING_UPDATE_INT_TO_UC_EN 6 6 CRTC1_RANGE_TIMING_UPDATE_INT_TO_UC_EN 7 7 CRTC2_RANGE_TIMING_UPDATE_INT_TO_UC_EN 8 8 CRTC3_RANGE_TIMING_UPDATE_INT_TO_UC_EN 9 9 CRTC4_RANGE_TIMING_UPDATE_INT_TO_UC_EN 10 10 CRTC5_RANGE_TIMING_UPDATE_INT_TO_UC_EN 11 11 DMCU_GENERIC_INT_TO_UC_EN 13 13 mmDMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1 0 0x3e8 13 0 2 DCPG_IHC_DCFEV0_POWER_UP_INT_XIRQ_IRQ_SEL 0 0 DCPG_IHC_DCFEV0_POWER_DOWN_INT_XIRQ_IRQ_SEL 1 1 DCFEV0_VBLANK_INT_XIRQ_IRQ_SEL 2 2 DCPG_IHC_DCFEV1_POWER_UP_INT_XIRQ_IRQ_SEL 3 3 DCPG_IHC_DCFEV1_POWER_DOWN_INT_XIRQ_IRQ_SEL 4 4 DCFEV1_VBLANK_INT_XIRQ_IRQ_SEL 5 5 CRTC0_RANGE_TIMING_UPDATE_INT_XIRQ_IRQ_SEL 6 6 CRTC1_RANGE_TIMING_UPDATE_INT_XIRQ_IRQ_SEL 7 7 CRTC2_RANGE_TIMING_UPDATE_INT_XIRQ_IRQ_SEL 8 8 CRTC3_RANGE_TIMING_UPDATE_INT_XIRQ_IRQ_SEL 9 9 CRTC4_RANGE_TIMING_UPDATE_INT_XIRQ_IRQ_SEL 10 10 CRTC5_RANGE_TIMING_UPDATE_INT_XIRQ_IRQ_SEL 11 11 DMCU_GENERIC_INT_XIRQ_IRQ_SEL 13 13 mmDMCU_INTERRUPT_STATUS_1 0 0x3e9 26 0 2 DCPG_IHC_DCFEV0_POWER_UP_INT_OCCURRED 0 0 DCPG_IHC_DCFEV0_POWER_UP_INT_CLEAR 0 0 DCPG_IHC_DCFEV1_POWER_UP_INT_OCCURRED 1 1 DCPG_IHC_DCFEV1_POWER_UP_INT_CLEAR 1 1 DCPG_IHC_DCFEV0_POWER_DOWN_INT_OCCURRED 2 2 DCPG_IHC_DCFEV0_POWER_DOWN_INT_CLEAR 2 2 DCPG_IHC_DCFEV1_POWER_DOWN_INT_OCCURRED 3 3 DCPG_IHC_DCFEV1_POWER_DOWN_INT_CLEAR 3 3 DCFEV0_VBLANK_INT_OCCURRED 4 4 DCFEV0_VBLANK_INT_CLEAR 4 4 DCFEV1_VBLANK_INT_OCCURRED 5 5 DCFEV1_VBLANK_INT_CLEAR 5 5 CRTC0_RANGE_TIMING_UPDATE_OCCURRED 6 6 CRTC0_RANGE_TIMING_UPDATE_CLEAR 6 6 CRTC1_RANGE_TIMING_UPDATE_OCCURRED 7 7 CRTC1_RANGE_TIMING_UPDATE_CLEAR 7 7 CRTC2_RANGE_TIMING_UPDATE_OCCURRED 8 8 CRTC2_RANGE_TIMING_UPDATE_CLEAR 8 8 CRTC3_RANGE_TIMING_UPDATE_OCCURRED 9 9 CRTC3_RANGE_TIMING_UPDATE_CLEAR 9 9 CRTC4_RANGE_TIMING_UPDATE_OCCURRED 10 10 CRTC4_RANGE_TIMING_UPDATE_CLEAR 10 10 CRTC5_RANGE_TIMING_UPDATE_OCCURRED 11 11 CRTC5_RANGE_TIMING_UPDATE_CLEAR 11 11 DMCU_GENERIC_INTERRUPT_OCCURRED 13 13 DMCU_GENERIC_INTERRUPT_CLEAR 13 13 mmDMCU_DPRX_INTERRUPT_STATUS1 0 0x3ea 58 0 2 DPRX_SD0P0_MSA_RECEIVED_INT_OCCURRED 0 0 DPRX_SD0P0_MSA_RECEIVED_INT_CLEAR 0 0 DPRX_SD0P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_OCCURRED 1 1 DPRX_SD0P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_CLEAR 1 1 DPRX_SD0P0_VERTICAL_INT0_OCCURRED 2 2 DPRX_SD0P0_VERTICAL_INT0_CLEAR 2 2 DPRX_SD0P0_VERTICAL_INT1_OCCURRED 3 3 DPRX_SD0P0_VERTICAL_INT1_CLEAR 3 3 DPRX_SD0P0_SDP_RECEIVED_INT_OCCURRED 4 4 DPRX_SD0P0_SDP_RECEIVED_INT_CLEAR 4 4 DPRX_SD1P0_MSA_RECEIVED_INT_OCCURRED 5 5 DPRX_SD1P0_MSA_RECEIVED_INT_CLEAR 5 5 DPRX_SD1P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_OCCURRED 6 6 DPRX_SD1P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_CLEAR 6 6 DPRX_SD1P0_VERTICAL_INT0_OCCURRED 7 7 DPRX_SD1P0_VERTICAL_INT0_CLEAR 7 7 DPRX_SD1P0_VERTICAL_INT1_OCCURRED 8 8 DPRX_SD1P0_VERTICAL_INT1_CLEAR 8 8 DPRX_SD1P0_SDP_RECEIVED_INT_OCCURRED 9 9 DPRX_SD1P0_SDP_RECEIVED_INT_CLEAR 9 9 DPRX_DPHY_P0_BS_INTERVAL_ERROR_THRESH_EXCEEDED_INT_OCCURRED 10 10 DPRX_DPHY_P0_BS_INTERVAL_ERROR_THRESH_EXCEEDED_INT_CLEAR 10 10 DPRX_DPHY_P0_SR_INTERVAL_ERROR_THRESH_EXCEEDED_INT_OCCURRED 11 11 DPRX_DPHY_P0_SR_INTERVAL_ERROR_THRESH_EXCEEDED_INT_CLEAR 11 11 DPRX_DPHY_P0_SYMBOL_ERROR_THRESH_EXCEEDED_INT_OCCURRED 12 12 DPRX_DPHY_P0_SYMBOL_ERROR_THRESH_EXCEEDED_INT_CLEAR 12 12 DPRX_DPHY_P0_DISPARITY_ERROR_THRESH_EXCEEDED_INT_OCCURRED 13 13 DPRX_DPHY_P0_DISPARITY_ERROR_THRESH_EXCEEDED_INT_CLEAR 13 13 DPRX_DPHY_P0_TRAINING_ERROR_THRESH_EXCEEDED_INT_OCCURRED 14 14 DPRX_DPHY_P0_TRAINING_ERROR_THRESH_EXCEEDED_INT_CLEAR 14 14 DPRX_DPHY_P0_TEST_PATTERN_ERROR_THRESH_EXCEEDED_INT_OCCURRED 15 15 DPRX_DPHY_P0_TEST_PATTERN_ERROR_THRESH_EXCEEDED_INT_CLEAR 15 15 DPRX_DPHY_P0_ECF_ERROR_THRESH_EXCEEDED_INT_OCCURRED 16 16 DPRX_DPHY_P0_ECF_ERROR_THRESH_EXCEEDED_INT_CLEAR 16 16 DPRX_DPHY_P0_DETECT_SR_LOCK_INT_OCCURRED 17 17 DPRX_DPHY_P0_DETECT_SR_LOCK_INT_CLEAR 17 17 DPRX_DPHY_P0_LOSS_OF_ALIGN_INT_OCCURRED 18 18 DPRX_DPHY_P0_LOSS_OF_ALIGN_INT_CLEAR 18 18 DPRX_DPHY_P0_LOSS_OF_DESKEW_INT_OCCURRED 19 19 DPRX_DPHY_P0_LOSS_OF_DESKEW_INT_CLEAR 19 19 DPRX_DPHY_P0_EXCESSIVE_ERROR_INT_OCCURRED 20 20 DPRX_DPHY_P0_EXCESSIVE_ERROR_INT_CLEAR 20 20 DPRX_DPHY_P0_DESKEW_FIFO_OVERFLOW_INT_OCCURRED 21 21 DPRX_DPHY_P0_DESKEW_FIFO_OVERFLOW_INT_CLEAR 21 21 DPRX_AUX_P0_AUX_INT_OCCURRED 22 22 DPRX_AUX_P0_AUX_INT_CLEAR 22 22 DPRX_AUX_P0_I2C_INT_OCCURRED 23 23 DPRX_AUX_P0_I2C_INT_CLEAR 23 23 DPRX_AUX_P0_CPU_INT_OCCURRED 24 24 DPRX_AUX_P0_CPU_INT_CLEAR 24 24 DPRX_AUX_P0_MSG1_TIMEOUT_INT_OCCURRED 25 25 DPRX_AUX_P0_MSG1_TIMEOUT_INT_CLEAR 25 25 DPRX_AUX_P0_MSG2_TIMEOUT_INT_OCCURRED 26 26 DPRX_AUX_P0_MSG2_TIMEOUT_INT_CLEAR 26 26 DPRX_AUX_P0_MSG3_TIMEOUT_INT_OCCURRED 27 27 DPRX_AUX_P0_MSG3_TIMEOUT_INT_CLEAR 27 27 DPRX_AUX_P0_MSG4_TIMEOUT_INT_OCCURRED 28 28 DPRX_AUX_P0_MSG4_TIMEOUT_INT_CLEAR 28 28 mmDMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1 0 0x3eb 29 0 2 DPRX_SD0P0_MSA_RECEIVED_INT_TO_UC_EN 0 0 DPRX_SD0P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_TO_UC_EN 1 1 DPRX_SD0P0_VERTICAL_INT0_TO_UC_EN 2 2 DPRX_SD0P0_VERTICAL_INT1_TO_UC_EN 3 3 DPRX_SD0P0_SDP_RECEIVED_INT_TO_UC_EN 4 4 DPRX_SD1P0_MSA_RECEIVED_INT_TO_UC_EN 5 5 DPRX_SD1P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_TO_UC_EN 6 6 DPRX_SD1P0_VERTICAL_INT0_TO_UC_EN 7 7 DPRX_SD1P0_VERTICAL_INT1_TO_UC_EN 8 8 DPRX_SD1P0_SDP_RECEIVED_INT_TO_UC_EN 9 9 DPRX_DPHY_P0_BS_INTERVAL_ERROR_THRESH_EXCEEDED_INT_TO_UC_EN 10 10 DPRX_DPHY_P0_SR_INTERVAL_ERROR_THRESH_EXCEEDED_INT_TO_UC_EN 11 11 DPRX_DPHY_P0_SYMBOL_ERROR_THRESH_EXCEEDED_INT_TO_UC_EN 12 12 DPRX_DPHY_P0_DISPARITY_ERROR_THRESH_EXCEEDED_INT_TO_UC_EN 13 13 DPRX_DPHY_P0_TRAINING_ERROR_THRESH_EXCEEDED_INT_TO_UC_EN 14 14 DPRX_DPHY_P0_TEST_PATTERN_ERROR_THRESH_EXCEEDED_INT_TO_UC_EN 15 15 DPRX_DPHY_P0_ECF_ERROR_THRESH_EXCEEDED_INT_TO_UC_EN 16 16 DPRX_DPHY_P0_DETECT_SR_LOCK_INT_TO_UC_EN 17 17 DPRX_DPHY_P0_LOSS_OF_ALIGN_INT_TO_UC_EN 18 18 DPRX_DPHY_P0_LOSS_OF_DESKEW_INT_TO_UC_EN 19 19 DPRX_DPHY_P0_EXCESSIVE_ERROR_INT_TO_UC_EN 20 20 DPRX_DPHY_P0_DESKEW_FIFO_OVERFLOW_INT_TO_UC_EN 21 21 DPRX_AUX_P0_AUX_INT_TO_UC_EN 22 22 DPRX_AUX_P0_I2C_INT_TO_UC_EN 23 23 DPRX_AUX_P0_CPU_INT_TO_UC_EN 24 24 DPRX_AUX_P0_MSG1_TIMEOUT_INT_TO_UC_EN 25 25 DPRX_AUX_P0_MSG2_TIMEOUT_INT_TO_UC_EN 26 26 DPRX_AUX_P0_MSG3_TIMEOUT_INT_TO_UC_EN 27 27 DPRX_AUX_P0_MSG4_TIMEOUT_INT_TO_UC_EN 28 28 mmDMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1 0 0x3ec 29 0 2 DPRX_SD0P0_MSA_RECEIVED_INT_XIRQ_IRQ_SEL 0 0 DPRX_SD0P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_XIRQ_IRQ_SEL 1 1 DPRX_SD0P0_VERTICAL_INT0_XIRQ_IRQ_SEL 2 2 DPRX_SD0P0_VERTICAL_INT1_XIRQ_IRQ_SEL 3 3 DPRX_SD0P0_SDP_RECEIVED_INT_XIRQ_IRQ_SEL 4 4 DPRX_SD1P0_MSA_RECEIVED_INT_XIRQ_IRQ_SEL 5 5 DPRX_SD1P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_XIRQ_IRQ_SEL 6 6 DPRX_SD1P0_VERTICAL_INT0_XIRQ_IRQ_SEL 7 7 DPRX_SD1P0_VERTICAL_INT1_XIRQ_IRQ_SEL 8 8 DPRX_SD1P0_SDP_RECEIVED_INT_XIRQ_IRQ_SEL 9 9 DPRX_DPHY_P0_BS_INTERVAL_ERROR_THRESH_EXCEEDED_INT_XIRQ_IRQ_SEL 10 10 DPRX_DPHY_P0_SR_INTERVAL_ERROR_THRESH_EXCEEDED_INT_XIRQ_IRQ_SEL 11 11 DPRX_DPHY_P0_SYMBOL_ERROR_THRESH_EXCEEDED_INT_XIRQ_IRQ_SEL 12 12 DPRX_DPHY_P0_DISPARITY_ERROR_THRESH_EXCEEDED_INT_XIRQ_IRQ_SEL 13 13 DPRX_DPHY_P0_TRAINING_ERROR_THRESH_EXCEEDED_INT_XIRQ_IRQ_SEL 14 14 DPRX_DPHY_P0_TEST_PATTERN_ERROR_THRESH_EXCEEDED_INT_XIRQ_IRQ_SEL 15 15 DPRX_DPHY_P0_ECF_ERROR_THRESH_EXCEEDED_INT_XIRQ_IRQ_SEL 16 16 DPRX_DPHY_P0_DETECT_SR_LOCK_INT_XIRQ_IRQ_SEL 17 17 DPRX_DPHY_P0_LOSS_OF_ALIGN_INT_XIRQ_IRQ_SEL 18 18 DPRX_DPHY_P0_LOSS_OF_DESKEW_INT_XIRQ_IRQ_SEL 19 19 DPRX_DPHY_P0_EXCESSIVE_ERROR_INT_XIRQ_IRQ_SEL 20 20 DPRX_DPHY_P0_DESKEW_FIFO_OVERFLOW_INT_XIRQ_IRQ_SEL 21 21 DPRX_AUX_P0_AUX_INT_XIRQ_IRQ_SEL 22 22 DPRX_AUX_P0_I2C_INT_XIRQ_IRQ_SEL 23 23 DPRX_AUX_P0_CPU_INT_XIRQ_IRQ_SEL 24 24 DPRX_AUX_P0_MSG1_TIMEOUT_INT_XIRQ_IRQ_SEL 25 25 DPRX_AUX_P0_MSG2_TIMEOUT_INT_XIRQ_IRQ_SEL 26 26 DPRX_AUX_P0_MSG3_TIMEOUT_INT_XIRQ_IRQ_SEL 27 27 DPRX_AUX_P0_MSG4_TIMEOUT_INT_XIRQ_IRQ_SEL 28 28 mmDC_ABM1_CNTL 0 0x3ee 3 0 2 ABM1_EN 0 0 ABM1_SOURCE_SELECT 8 10 ABM1_BLANK_MODE_SUPPORT_ENABLE 31 31 mmDC_ABM1_IPCSC_COEFF_SEL 0 0x3ef 4 0 2 ABM1_IPCSC_COEFF_SEL_B 0 3 ABM1_IPCSC_COEFF_SEL_G 8 11 ABM1_IPCSC_COEFF_SEL_R 16 19 ABM1_HGLS_REG_LOCK 31 31 mmDC_ABM1_ACE_OFFSET_SLOPE_0 0 0x3f0 3 0 2 ABM1_ACE_SLOPE_0 0 14 ABM1_ACE_OFFSET_0 16 26 ABM1_ACE_LOCK 31 31 mmDC_ABM1_ACE_OFFSET_SLOPE_1 0 0x3f1 3 0 2 ABM1_ACE_SLOPE_1 0 14 ABM1_ACE_OFFSET_1 16 26 ABM1_ACE_LOCK 31 31 mmDC_ABM1_ACE_OFFSET_SLOPE_2 0 0x3f2 3 0 2 ABM1_ACE_SLOPE_2 0 14 ABM1_ACE_OFFSET_2 16 26 ABM1_ACE_LOCK 31 31 mmDC_ABM1_ACE_OFFSET_SLOPE_3 0 0x3f3 3 0 2 ABM1_ACE_SLOPE_3 0 14 ABM1_ACE_OFFSET_3 16 26 ABM1_ACE_LOCK 31 31 mmDC_ABM1_ACE_OFFSET_SLOPE_4 0 0x3f4 3 0 2 ABM1_ACE_SLOPE_4 0 14 ABM1_ACE_OFFSET_4 16 26 ABM1_ACE_LOCK 31 31 mmDC_ABM1_ACE_THRES_12 0 0x3f5 3 0 2 ABM1_ACE_THRES_1 0 9 ABM1_ACE_THRES_2 16 25 ABM1_ACE_LOCK 31 31 mmDC_ABM1_ACE_THRES_34 0 0x3f6 6 0 2 ABM1_ACE_THRES_3 0 9 ABM1_ACE_THRES_4 16 25 ABM1_ACE_IGNORE_MASTER_LOCK_EN 28 28 ABM1_ACE_READBACK_DB_REG_VALUE_EN 29 29 ABM1_ACE_DBUF_REG_UPDATE_PENDING 30 30 ABM1_ACE_LOCK 31 31 mmDC_ABM1_ACE_CNTL_MISC 0 0x3f7 2 0 2 ABM1_ACE_REG_WR_MISSED_FRAME 0 0 ABM1_ACE_REG_WR_MISSED_FRAME_CLEAR 8 8 mmDMCU_PERFMON_INTERRUPT_STATUS5 0 0x3f8 36 0 2 DCFEV0_PERFMON_COUNTER0_INT_OCCURRED 0 0 DCFEV0_PERFMON_COUNTER0_INT_CLEAR 0 0 DCFEV0_PERFMON_COUNTER1_INT_OCCURRED 1 1 DCFEV0_PERFMON_COUNTER1_INT_CLEAR 1 1 DCFEV0_PERFMON_COUNTER2_INT_OCCURRED 2 2 DCFEV0_PERFMON_COUNTER2_INT_CLEAR 2 2 DCFEV0_PERFMON_COUNTER3_INT_OCCURRED 3 3 DCFEV0_PERFMON_COUNTER3_INT_CLEAR 3 3 DCFEV0_PERFMON_COUNTER4_INT_OCCURRED 4 4 DCFEV0_PERFMON_COUNTER4_INT_CLEAR 4 4 DCFEV0_PERFMON_COUNTER5_INT_OCCURRED 5 5 DCFEV0_PERFMON_COUNTER5_INT_CLEAR 5 5 DCFEV0_PERFMON_COUNTER6_INT_OCCURRED 6 6 DCFEV0_PERFMON_COUNTER6_INT_CLEAR 6 6 DCFEV0_PERFMON_COUNTER7_INT_OCCURRED 7 7 DCFEV0_PERFMON_COUNTER7_INT_CLEAR 7 7 DCFEV1_PERFMON_COUNTER0_INT_OCCURRED 8 8 DCFEV1_PERFMON_COUNTER0_INT_CLEAR 8 8 DCFEV1_PERFMON_COUNTER1_INT_OCCURRED 9 9 DCFEV1_PERFMON_COUNTER1_INT_CLEAR 9 9 DCFEV1_PERFMON_COUNTER2_INT_OCCURRED 10 10 DCFEV1_PERFMON_COUNTER2_INT_CLEAR 10 10 DCFEV1_PERFMON_COUNTER3_INT_OCCURRED 11 11 DCFEV1_PERFMON_COUNTER3_INT_CLEAR 11 11 DCFEV1_PERFMON_COUNTER4_INT_OCCURRED 12 12 DCFEV1_PERFMON_COUNTER4_INT_CLEAR 12 12 DCFEV1_PERFMON_COUNTER5_INT_OCCURRED 13 13 DCFEV1_PERFMON_COUNTER5_INT_CLEAR 13 13 DCFEV1_PERFMON_COUNTER6_INT_OCCURRED 14 14 DCFEV1_PERFMON_COUNTER6_INT_CLEAR 14 14 DCFEV1_PERFMON_COUNTER7_INT_OCCURRED 15 15 DCFEV1_PERFMON_COUNTER7_INT_CLEAR 15 15 DCFEV0_PERFMON_COUNTER_OFF_INT_OCCURRED 16 16 DCFEV0_PERFMON_COUNTER_OFF_INT_CLEAR 16 16 DCFEV1_PERFMON_COUNTER_OFF_INT_OCCURRED 17 17 DCFEV1_PERFMON_COUNTER_OFF_INT_CLEAR 17 17 mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5 0 0x3f9 18 0 2 DCFEV0_PERFMON_COUNTER0_INT_TO_UC_EN 0 0 DCFEV0_PERFMON_COUNTER1_INT_TO_UC_EN 1 1 DCFEV0_PERFMON_COUNTER2_INT_TO_UC_EN 2 2 DCFEV0_PERFMON_COUNTER3_INT_TO_UC_EN 3 3 DCFEV0_PERFMON_COUNTER4_INT_TO_UC_EN 4 4 DCFEV0_PERFMON_COUNTER5_INT_TO_UC_EN 5 5 DCFEV0_PERFMON_COUNTER6_INT_TO_UC_EN 6 6 DCFEV0_PERFMON_COUNTER7_INT_TO_UC_EN 7 7 DCFEV0_PERFMON_COUNTER_OFF_INT_TO_UC_EN 8 8 DCFEV1_PERFMON_COUNTER0_INT_TO_UC_EN 9 9 DCFEV1_PERFMON_COUNTER1_INT_TO_UC_EN 10 10 DCFEV1_PERFMON_COUNTER2_INT_TO_UC_EN 11 11 DCFEV1_PERFMON_COUNTER3_INT_TO_UC_EN 12 12 DCFEV1_PERFMON_COUNTER4_INT_TO_UC_EN 13 13 DCFEV1_PERFMON_COUNTER5_INT_TO_UC_EN 14 14 DCFEV1_PERFMON_COUNTER6_INT_TO_UC_EN 15 15 DCFEV1_PERFMON_COUNTER7_INT_TO_UC_EN 16 16 DCFEV1_PERFMON_COUNTER_OFF_INT_TO_UC_EN 17 17 mmDMCU_PERFMON_INTERRUPT_STATUS1 0 0x3fa 54 0 2 DCI_PERFMON_COUNTER0_INT_OCCURRED 0 0 DCI_PERFMON_COUNTER0_INT_CLEAR 0 0 DCI_PERFMON_COUNTER1_INT_OCCURRED 1 1 DCI_PERFMON_COUNTER1_INT_CLEAR 1 1 DCI_PERFMON_COUNTER2_INT_OCCURRED 2 2 DCI_PERFMON_COUNTER2_INT_CLEAR 2 2 DCI_PERFMON_COUNTER3_INT_OCCURRED 3 3 DCI_PERFMON_COUNTER3_INT_CLEAR 3 3 DCI_PERFMON_COUNTER4_INT_OCCURRED 4 4 DCI_PERFMON_COUNTER4_INT_CLEAR 4 4 DCI_PERFMON_COUNTER5_INT_OCCURRED 5 5 DCI_PERFMON_COUNTER5_INT_CLEAR 5 5 DCI_PERFMON_COUNTER6_INT_OCCURRED 6 6 DCI_PERFMON_COUNTER6_INT_CLEAR 6 6 DCI_PERFMON_COUNTER7_INT_OCCURRED 7 7 DCI_PERFMON_COUNTER7_INT_CLEAR 7 7 DCO_PERFMON_COUNTER0_INT_OCCURRED 8 8 DCO_PERFMON_COUNTER0_INT_CLEAR 8 8 DCO_PERFMON_COUNTER1_INT_OCCURRED 9 9 DCO_PERFMON_COUNTER1_INT_CLEAR 9 9 DCO_PERFMON_COUNTER2_INT_OCCURRED 10 10 DCO_PERFMON_COUNTER2_INT_CLEAR 10 10 DCO_PERFMON_COUNTER3_INT_OCCURRED 11 11 DCO_PERFMON_COUNTER3_INT_CLEAR 11 11 DCO_PERFMON_COUNTER4_INT_OCCURRED 12 12 DCO_PERFMON_COUNTER4_INT_CLEAR 12 12 DCO_PERFMON_COUNTER5_INT_OCCURRED 13 13 DCO_PERFMON_COUNTER5_INT_CLEAR 13 13 DCO_PERFMON_COUNTER6_INT_OCCURRED 14 14 DCO_PERFMON_COUNTER6_INT_CLEAR 14 14 DCO_PERFMON_COUNTER7_INT_OCCURRED 15 15 DCO_PERFMON_COUNTER7_INT_CLEAR 15 15 DCCG_PERFMON_COUNTER0_INT_OCCURRED 16 16 DCCG_PERFMON_COUNTER0_INT_CLEAR 16 16 DCCG_PERFMON_COUNTER1_INT_OCCURRED 17 17 DCCG_PERFMON_COUNTER1_INT_CLEAR 17 17 DCCG_PERFMON_COUNTER2_INT_OCCURRED 18 18 DCCG_PERFMON_COUNTER2_INT_CLEAR 18 18 DCCG_PERFMON_COUNTER3_INT_OCCURRED 19 19 DCCG_PERFMON_COUNTER3_INT_CLEAR 19 19 DCCG_PERFMON_COUNTER4_INT_OCCURRED 20 20 DCCG_PERFMON_COUNTER4_INT_CLEAR 20 20 DCCG_PERFMON_COUNTER5_INT_OCCURRED 21 21 DCCG_PERFMON_COUNTER5_INT_CLEAR 21 21 DCCG_PERFMON_COUNTER6_INT_OCCURRED 22 22 DCCG_PERFMON_COUNTER6_INT_CLEAR 22 22 DCCG_PERFMON_COUNTER7_INT_OCCURRED 23 23 DCCG_PERFMON_COUNTER7_INT_CLEAR 23 23 DCI_PERFMON_COUNTER_OFF_INT_OCCURRED 24 24 DCI_PERFMON_COUNTER_OFF_INT_CLEAR 24 24 DCO_PERFMON_COUNTER_OFF_INT_OCCURRED 25 25 DCO_PERFMON_COUNTER_OFF_INT_CLEAR 25 25 DCCG_PERFMON_COUNTER_OFF_INT_OCCURRED 26 26 DCCG_PERFMON_COUNTER_OFF_INT_CLEAR 26 26 mmDMCU_PERFMON_INTERRUPT_STATUS2 0 0x3fb 54 0 2 DCFE0_PERFMON_COUNTER0_INT_OCCURRED 0 0 DCFE0_PERFMON_COUNTER0_INT_CLEAR 0 0 DCFE0_PERFMON_COUNTER1_INT_OCCURRED 1 1 DCFE0_PERFMON_COUNTER1_INT_CLEAR 1 1 DCFE0_PERFMON_COUNTER2_INT_OCCURRED 2 2 DCFE0_PERFMON_COUNTER2_INT_CLEAR 2 2 DCFE0_PERFMON_COUNTER3_INT_OCCURRED 3 3 DCFE0_PERFMON_COUNTER3_INT_CLEAR 3 3 DCFE0_PERFMON_COUNTER4_INT_OCCURRED 4 4 DCFE0_PERFMON_COUNTER4_INT_CLEAR 4 4 DCFE0_PERFMON_COUNTER5_INT_OCCURRED 5 5 DCFE0_PERFMON_COUNTER5_INT_CLEAR 5 5 DCFE0_PERFMON_COUNTER6_INT_OCCURRED 6 6 DCFE0_PERFMON_COUNTER6_INT_CLEAR 6 6 DCFE0_PERFMON_COUNTER7_INT_OCCURRED 7 7 DCFE0_PERFMON_COUNTER7_INT_CLEAR 7 7 DCFE1_PERFMON_COUNTER0_INT_OCCURRED 8 8 DCFE1_PERFMON_COUNTER0_INT_CLEAR 8 8 DCFE1_PERFMON_COUNTER1_INT_OCCURRED 9 9 DCFE1_PERFMON_COUNTER1_INT_CLEAR 9 9 DCFE1_PERFMON_COUNTER2_INT_OCCURRED 10 10 DCFE1_PERFMON_COUNTER2_INT_CLEAR 10 10 DCFE1_PERFMON_COUNTER3_INT_OCCURRED 11 11 DCFE1_PERFMON_COUNTER3_INT_CLEAR 11 11 DCFE1_PERFMON_COUNTER4_INT_OCCURRED 12 12 DCFE1_PERFMON_COUNTER4_INT_CLEAR 12 12 DCFE1_PERFMON_COUNTER5_INT_OCCURRED 13 13 DCFE1_PERFMON_COUNTER5_INT_CLEAR 13 13 DCFE1_PERFMON_COUNTER6_INT_OCCURRED 14 14 DCFE1_PERFMON_COUNTER6_INT_CLEAR 14 14 DCFE1_PERFMON_COUNTER7_INT_OCCURRED 15 15 DCFE1_PERFMON_COUNTER7_INT_CLEAR 15 15 DCFE2_PERFMON_COUNTER0_INT_OCCURRED 16 16 DCFE2_PERFMON_COUNTER0_INT_CLEAR 16 16 DCFE2_PERFMON_COUNTER1_INT_OCCURRED 17 17 DCFE2_PERFMON_COUNTER1_INT_CLEAR 17 17 DCFE2_PERFMON_COUNTER2_INT_OCCURRED 18 18 DCFE2_PERFMON_COUNTER2_INT_CLEAR 18 18 DCFE2_PERFMON_COUNTER3_INT_OCCURRED 19 19 DCFE2_PERFMON_COUNTER3_INT_CLEAR 19 19 DCFE2_PERFMON_COUNTER4_INT_OCCURRED 20 20 DCFE2_PERFMON_COUNTER4_INT_CLEAR 20 20 DCFE2_PERFMON_COUNTER5_INT_OCCURRED 21 21 DCFE2_PERFMON_COUNTER5_INT_CLEAR 21 21 DCFE2_PERFMON_COUNTER6_INT_OCCURRED 22 22 DCFE2_PERFMON_COUNTER6_INT_CLEAR 22 22 DCFE2_PERFMON_COUNTER7_INT_OCCURRED 23 23 DCFE2_PERFMON_COUNTER7_INT_CLEAR 23 23 DCFE0_PERFMON_COUNTER_OFF_INT_OCCURRED 24 24 DCFE0_PERFMON_COUNTER_OFF_INT_CLEAR 24 24 DCFE1_PERFMON_COUNTER_OFF_INT_OCCURRED 25 25 DCFE1_PERFMON_COUNTER_OFF_INT_CLEAR 25 25 DCFE2_PERFMON_COUNTER_OFF_INT_OCCURRED 26 26 DCFE2_PERFMON_COUNTER_OFF_INT_CLEAR 26 26 mmDMCU_PERFMON_INTERRUPT_STATUS3 0 0x3fc 54 0 2 DCFE3_PERFMON_COUNTER0_INT_OCCURRED 0 0 DCFE3_PERFMON_COUNTER0_INT_CLEAR 0 0 DCFE3_PERFMON_COUNTER1_INT_OCCURRED 1 1 DCFE3_PERFMON_COUNTER1_INT_CLEAR 1 1 DCFE3_PERFMON_COUNTER2_INT_OCCURRED 2 2 DCFE3_PERFMON_COUNTER2_INT_CLEAR 2 2 DCFE3_PERFMON_COUNTER3_INT_OCCURRED 3 3 DCFE3_PERFMON_COUNTER3_INT_CLEAR 3 3 DCFE3_PERFMON_COUNTER4_INT_OCCURRED 4 4 DCFE3_PERFMON_COUNTER4_INT_CLEAR 4 4 DCFE3_PERFMON_COUNTER5_INT_OCCURRED 5 5 DCFE3_PERFMON_COUNTER5_INT_CLEAR 5 5 DCFE3_PERFMON_COUNTER6_INT_OCCURRED 6 6 DCFE3_PERFMON_COUNTER6_INT_CLEAR 6 6 DCFE3_PERFMON_COUNTER7_INT_OCCURRED 7 7 DCFE3_PERFMON_COUNTER7_INT_CLEAR 7 7 DCFE4_PERFMON_COUNTER0_INT_OCCURRED 8 8 DCFE4_PERFMON_COUNTER0_INT_CLEAR 8 8 DCFE4_PERFMON_COUNTER1_INT_OCCURRED 9 9 DCFE4_PERFMON_COUNTER1_INT_CLEAR 9 9 DCFE4_PERFMON_COUNTER2_INT_OCCURRED 10 10 DCFE4_PERFMON_COUNTER2_INT_CLEAR 10 10 DCFE4_PERFMON_COUNTER3_INT_OCCURRED 11 11 DCFE4_PERFMON_COUNTER3_INT_CLEAR 11 11 DCFE4_PERFMON_COUNTER4_INT_OCCURRED 12 12 DCFE4_PERFMON_COUNTER4_INT_CLEAR 12 12 DCFE4_PERFMON_COUNTER5_INT_OCCURRED 13 13 DCFE4_PERFMON_COUNTER5_INT_CLEAR 13 13 DCFE4_PERFMON_COUNTER6_INT_OCCURRED 14 14 DCFE4_PERFMON_COUNTER6_INT_CLEAR 14 14 DCFE4_PERFMON_COUNTER7_INT_OCCURRED 15 15 DCFE4_PERFMON_COUNTER7_INT_CLEAR 15 15 DCFE5_PERFMON_COUNTER0_INT_OCCURRED 16 16 DCFE5_PERFMON_COUNTER0_INT_CLEAR 16 16 DCFE5_PERFMON_COUNTER1_INT_OCCURRED 17 17 DCFE5_PERFMON_COUNTER1_INT_CLEAR 17 17 DCFE5_PERFMON_COUNTER2_INT_OCCURRED 18 18 DCFE5_PERFMON_COUNTER2_INT_CLEAR 18 18 DCFE5_PERFMON_COUNTER3_INT_OCCURRED 19 19 DCFE5_PERFMON_COUNTER3_INT_CLEAR 19 19 DCFE5_PERFMON_COUNTER4_INT_OCCURRED 20 20 DCFE5_PERFMON_COUNTER4_INT_CLEAR 20 20 DCFE5_PERFMON_COUNTER5_INT_OCCURRED 21 21 DCFE5_PERFMON_COUNTER5_INT_CLEAR 21 21 DCFE5_PERFMON_COUNTER6_INT_OCCURRED 22 22 DCFE5_PERFMON_COUNTER6_INT_CLEAR 22 22 DCFE5_PERFMON_COUNTER7_INT_OCCURRED 23 23 DCFE5_PERFMON_COUNTER7_INT_CLEAR 23 23 DCFE3_PERFMON_COUNTER_OFF_INT_OCCURRED 24 24 DCFE3_PERFMON_COUNTER_OFF_INT_CLEAR 24 24 DCFE4_PERFMON_COUNTER_OFF_INT_OCCURRED 25 25 DCFE4_PERFMON_COUNTER_OFF_INT_CLEAR 25 25 DCFE5_PERFMON_COUNTER_OFF_INT_OCCURRED 26 26 DCFE5_PERFMON_COUNTER_OFF_INT_CLEAR 26 26 mmDMCU_PERFMON_INTERRUPT_STATUS4 0 0x3fd 54 0 2 WB_PERFMON_COUNTER0_INT_OCCURRED 0 0 WB_PERFMON_COUNTER0_INT_CLEAR 0 0 WB_PERFMON_COUNTER1_INT_OCCURRED 1 1 WB_PERFMON_COUNTER1_INT_CLEAR 1 1 WB_PERFMON_COUNTER2_INT_OCCURRED 2 2 WB_PERFMON_COUNTER2_INT_CLEAR 2 2 WB_PERFMON_COUNTER3_INT_OCCURRED 3 3 WB_PERFMON_COUNTER3_INT_CLEAR 3 3 WB_PERFMON_COUNTER4_INT_OCCURRED 4 4 WB_PERFMON_COUNTER4_INT_CLEAR 4 4 WB_PERFMON_COUNTER5_INT_OCCURRED 5 5 WB_PERFMON_COUNTER5_INT_CLEAR 5 5 WB_PERFMON_COUNTER6_INT_OCCURRED 6 6 WB_PERFMON_COUNTER6_INT_CLEAR 6 6 WB_PERFMON_COUNTER7_INT_OCCURRED 7 7 WB_PERFMON_COUNTER7_INT_CLEAR 7 7 DCRX_PERFMON_COUNTER0_INT_OCCURRED 8 8 DCRX_PERFMON_COUNTER0_INT_CLEAR 8 8 DCRX_PERFMON_COUNTER1_INT_OCCURRED 9 9 DCRX_PERFMON_COUNTER1_INT_CLEAR 9 9 DCRX_PERFMON_COUNTER2_INT_OCCURRED 10 10 DCRX_PERFMON_COUNTER2_INT_CLEAR 10 10 DCRX_PERFMON_COUNTER3_INT_OCCURRED 11 11 DCRX_PERFMON_COUNTER3_INT_CLEAR 11 11 DCRX_PERFMON_COUNTER4_INT_OCCURRED 12 12 DCRX_PERFMON_COUNTER4_INT_CLEAR 12 12 DCRX_PERFMON_COUNTER5_INT_OCCURRED 13 13 DCRX_PERFMON_COUNTER5_INT_CLEAR 13 13 DCRX_PERFMON_COUNTER6_INT_OCCURRED 14 14 DCRX_PERFMON_COUNTER6_INT_CLEAR 14 14 DCRX_PERFMON_COUNTER7_INT_OCCURRED 15 15 DCRX_PERFMON_COUNTER7_INT_CLEAR 15 15 DCCG_PERFMON2_COUNTER0_INT_OCCURRED 16 16 DCCG_PERFMON2_COUNTER0_INT_CLEAR 16 16 DCCG_PERFMON2_COUNTER1_INT_OCCURRED 17 17 DCCG_PERFMON2_COUNTER1_INT_CLEAR 17 17 DCCG_PERFMON2_COUNTER2_INT_OCCURRED 18 18 DCCG_PERFMON2_COUNTER2_INT_CLEAR 18 18 DCCG_PERFMON2_COUNTER3_INT_OCCURRED 19 19 DCCG_PERFMON2_COUNTER3_INT_CLEAR 19 19 DCCG_PERFMON2_COUNTER4_INT_OCCURRED 20 20 DCCG_PERFMON2_COUNTER4_INT_CLEAR 20 20 DCCG_PERFMON2_COUNTER5_INT_OCCURRED 21 21 DCCG_PERFMON2_COUNTER5_INT_CLEAR 21 21 DCCG_PERFMON2_COUNTER6_INT_OCCURRED 22 22 DCCG_PERFMON2_COUNTER6_INT_CLEAR 22 22 DCCG_PERFMON2_COUNTER7_INT_OCCURRED 23 23 DCCG_PERFMON2_COUNTER7_INT_CLEAR 23 23 WB_PERFMON_COUNTER_OFF_INT_OCCURRED 24 24 WB_PERFMON_COUNTER_OFF_INT_CLEAR 24 24 DCRX_PERFMON_COUNTER_OFF_INT_OCCURRED 25 25 DCRX_PERFMON_COUNTER_OFF_INT_CLEAR 25 25 DCCG_PERFMON2_COUNTER_OFF_INT_OCCURRED 26 26 DCCG_PERFMON2_COUNTER_OFF_INT_CLEAR 26 26 mmDC_ABM1_HGLS_REG_READ_PROGRESS 0 0x400 9 0 2 ABM1_HG_REG_READ_IN_PROGRESS 0 0 ABM1_LS_REG_READ_IN_PROGRESS 1 1 ABM1_BL_REG_READ_IN_PROGRESS 2 2 ABM1_HG_REG_READ_MISSED_FRAME 8 8 ABM1_LS_REG_READ_MISSED_FRAME 9 9 ABM1_BL_REG_READ_MISSED_FRAME 10 10 ABM1_HG_REG_READ_MISSED_FRAME_CLEAR 16 16 ABM1_LS_REG_READ_MISSED_FRAME_CLEAR 24 24 ABM1_BL_REG_READ_MISSED_FRAME_CLEAR 31 31 mmDC_ABM1_HG_MISC_CTRL 0 0x401 11 0 2 ABM1_HG_NUM_OF_BINS_SEL 0 1 ABM1_HG_VMAX_SEL 8 8 ABM1_HG_FINE_MODE_BIN_SEL 12 12 ABM1_HG_BIN_BITWIDTH_SIZE_SEL 16 17 ABM1_OVR_SCAN_PIXEL_PROCESS_EN 20 20 ABM1_DBUF_HGLS_READBACK_DB_REG_VALUE_EN 23 23 ABM1_DBUF_HGLS_REG_FRAME_START_DISP_SEL 24 26 ABM1_DBUF_HGLS_REG_UPDATE_AT_FRAME_START 28 28 ABM1_HGLS_IGNORE_MASTER_LOCK_EN 29 29 ABM1_DBUF_HGLS_REG_UPDATE_PENDING 30 30 ABM1_HGLS_REG_LOCK 31 31 mmDC_ABM1_LS_SUM_OF_LUMA 0 0x402 1 0 2 ABM1_LS_SUM_OF_LUMA 0 31 mmDC_ABM1_LS_MIN_MAX_LUMA 0 0x403 2 0 2 ABM1_LS_MIN_LUMA 0 9 ABM1_LS_MAX_LUMA 16 25 mmDC_ABM1_LS_FILTERED_MIN_MAX_LUMA 0 0x404 2 0 2 ABM1_LS_FILTERED_MIN_LUMA 0 9 ABM1_LS_FILTERED_MAX_LUMA 16 25 mmDC_ABM1_LS_PIXEL_COUNT 0 0x405 1 0 2 ABM1_LS_PIXEL_COUNT 0 23 mmDC_ABM1_LS_OVR_SCAN_BIN 0 0x406 1 0 2 ABM1_LS_OVR_SCAN_BIN 0 23 mmDC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES 0 0x407 3 0 2 ABM1_LS_MIN_PIXEL_VALUE_THRES 0 9 ABM1_LS_MAX_PIXEL_VALUE_THRES 16 25 ABM1_HGLS_REG_LOCK 31 31 mmDC_ABM1_LS_MIN_PIXEL_VALUE_COUNT 0 0x408 1 0 2 ABM1_LS_MIN_PIXEL_VALUE_COUNT 0 23 mmDC_ABM1_LS_MAX_PIXEL_VALUE_COUNT 0 0x409 1 0 2 ABM1_LS_MAX_PIXEL_VALUE_COUNT 0 23 mmDC_ABM1_HG_SAMPLE_RATE 0 0x40a 5 0 2 ABM1_HG_SAMPLE_RATE_COUNT_EN 0 0 ABM1_HG_RESET_SAMPLE_RATE_FRAME_COUNTER 1 1 ABM1_HG_SAMPLE_RATE_FRAME_COUNT 8 15 ABM1_HG_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET 16 23 ABM1_HGLS_REG_LOCK 31 31 mmDC_ABM1_LS_SAMPLE_RATE 0 0x40b 5 0 2 ABM1_LS_SAMPLE_RATE_COUNT_EN 0 0 ABM1_LS_RESET_SAMPLE_RATE_FRAME_COUNTER 1 1 ABM1_LS_SAMPLE_RATE_FRAME_COUNT 8 15 ABM1_LS_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET 16 23 ABM1_HGLS_REG_LOCK 31 31 mmDC_ABM1_HG_BIN_1_32_SHIFT_FLAG 0 0x40c 1 0 2 ABM1_HG_BIN_1_32_SHIFT_FLAG 0 31 mmDC_ABM1_HG_BIN_1_8_SHIFT_INDEX 0 0x40d 1 0 2 ABM1_HG_BIN_1_8_SHIFT_INDEX 0 31 mmDC_ABM1_HG_BIN_9_16_SHIFT_INDEX 0 0x40e 1 0 2 ABM1_HG_BIN_9_16_SHIFT_INDEX 0 31 mmDC_ABM1_HG_BIN_17_24_SHIFT_INDEX 0 0x40f 1 0 2 ABM1_HG_BIN_17_24_SHIFT_INDEX 0 31 mmDC_ABM1_HG_BIN_25_32_SHIFT_INDEX 0 0x410 1 0 2 ABM1_HG_BIN_25_32_SHIFT_INDEX 0 31 mmDC_ABM1_HG_RESULT_1 0 0x411 1 0 2 ABM1_HG_RESULT_1 0 31 mmDC_ABM1_HG_RESULT_2 0 0x412 1 0 2 ABM1_HG_RESULT_2 0 31 mmDC_ABM1_HG_RESULT_3 0 0x413 1 0 2 ABM1_HG_RESULT_3 0 31 mmDC_ABM1_HG_RESULT_4 0 0x414 1 0 2 ABM1_HG_RESULT_4 0 31 mmDC_ABM1_HG_RESULT_5 0 0x415 1 0 2 ABM1_HG_RESULT_5 0 31 mmDC_ABM1_HG_RESULT_6 0 0x416 1 0 2 ABM1_HG_RESULT_6 0 31 mmDC_ABM1_HG_RESULT_7 0 0x417 1 0 2 ABM1_HG_RESULT_7 0 31 mmDC_ABM1_HG_RESULT_8 0 0x418 1 0 2 ABM1_HG_RESULT_8 0 31 mmDC_ABM1_HG_RESULT_9 0 0x419 1 0 2 ABM1_HG_RESULT_9 0 31 mmDC_ABM1_HG_RESULT_10 0 0x41a 1 0 2 ABM1_HG_RESULT_10 0 31 mmDC_ABM1_HG_RESULT_11 0 0x41b 1 0 2 ABM1_HG_RESULT_11 0 31 mmDC_ABM1_HG_RESULT_12 0 0x41c 1 0 2 ABM1_HG_RESULT_12 0 31 mmDC_ABM1_HG_RESULT_13 0 0x41d 1 0 2 ABM1_HG_RESULT_13 0 31 mmDC_ABM1_HG_RESULT_14 0 0x41e 1 0 2 ABM1_HG_RESULT_14 0 31 mmDC_ABM1_HG_RESULT_15 0 0x41f 1 0 2 ABM1_HG_RESULT_15 0 31 mmDC_ABM1_HG_RESULT_16 0 0x420 1 0 2 ABM1_HG_RESULT_16 0 31 mmDC_ABM1_HG_RESULT_17 0 0x421 1 0 2 ABM1_HG_RESULT_17 0 31 mmDC_ABM1_HG_RESULT_18 0 0x422 1 0 2 ABM1_HG_RESULT_18 0 31 mmDC_ABM1_HG_RESULT_19 0 0x423 1 0 2 ABM1_HG_RESULT_19 0 31 mmDC_ABM1_HG_RESULT_20 0 0x424 1 0 2 ABM1_HG_RESULT_20 0 31 mmDC_ABM1_HG_RESULT_21 0 0x425 1 0 2 ABM1_HG_RESULT_21 0 31 mmDC_ABM1_HG_RESULT_22 0 0x426 1 0 2 ABM1_HG_RESULT_22 0 31 mmDC_ABM1_HG_RESULT_23 0 0x427 1 0 2 ABM1_HG_RESULT_23 0 31 mmDC_ABM1_HG_RESULT_24 0 0x428 1 0 2 ABM1_HG_RESULT_24 0 31 mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5 0 0x429 18 0 2 DCFEV0_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL 0 0 DCFEV0_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL 1 1 DCFEV0_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL 2 2 DCFEV0_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL 3 3 DCFEV0_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL 4 4 DCFEV0_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL 5 5 DCFEV0_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL 6 6 DCFEV0_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL 7 7 DCFEV0_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL 8 8 DCFEV1_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL 9 9 DCFEV1_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL 10 10 DCFEV1_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL 11 11 DCFEV1_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL 12 12 DCFEV1_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL 13 13 DCFEV1_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL 14 14 DCFEV1_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL 15 15 DCFEV1_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL 16 16 DCFEV1_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL 17 17 mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1 0 0x42a 27 0 2 DCI_PERFMON_COUNTER0_INT_TO_UC_EN 0 0 DCI_PERFMON_COUNTER1_INT_TO_UC_EN 1 1 DCI_PERFMON_COUNTER2_INT_TO_UC_EN 2 2 DCI_PERFMON_COUNTER3_INT_TO_UC_EN 3 3 DCI_PERFMON_COUNTER4_INT_TO_UC_EN 4 4 DCI_PERFMON_COUNTER5_INT_TO_UC_EN 5 5 DCI_PERFMON_COUNTER6_INT_TO_UC_EN 6 6 DCI_PERFMON_COUNTER7_INT_TO_UC_EN 7 7 DCO_PERFMON_COUNTER0_INT_TO_UC_EN 8 8 DCO_PERFMON_COUNTER1_INT_TO_UC_EN 9 9 DCO_PERFMON_COUNTER2_INT_TO_UC_EN 10 10 DCO_PERFMON_COUNTER3_INT_TO_UC_EN 11 11 DCO_PERFMON_COUNTER4_INT_TO_UC_EN 12 12 DCO_PERFMON_COUNTER5_INT_TO_UC_EN 13 13 DCO_PERFMON_COUNTER6_INT_TO_UC_EN 14 14 DCO_PERFMON_COUNTER7_INT_TO_UC_EN 15 15 DCCG_PERFMON_COUNTER0_INT_TO_UC_EN 16 16 DCCG_PERFMON_COUNTER1_INT_TO_UC_EN 17 17 DCCG_PERFMON_COUNTER2_INT_TO_UC_EN 18 18 DCCG_PERFMON_COUNTER3_INT_TO_UC_EN 19 19 DCCG_PERFMON_COUNTER4_INT_TO_UC_EN 20 20 DCCG_PERFMON_COUNTER5_INT_TO_UC_EN 21 21 DCCG_PERFMON_COUNTER6_INT_TO_UC_EN 22 22 DCCG_PERFMON_COUNTER7_INT_TO_UC_EN 23 23 DCI_PERFMON_COUNTER_OFF_INT_TO_UC_EN 24 24 DCO_PERFMON_COUNTER_OFF_INT_TO_UC_EN 25 25 DCCG_PERFMON_COUNTER_OFF_INT_TO_UC_EN 26 26 mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2 0 0x42b 27 0 2 DCFE0_PERFMON_COUNTER0_INT_TO_UC_EN 0 0 DCFE0_PERFMON_COUNTER1_INT_TO_UC_EN 1 1 DCFE0_PERFMON_COUNTER2_INT_TO_UC_EN 2 2 DCFE0_PERFMON_COUNTER3_INT_TO_UC_EN 3 3 DCFE0_PERFMON_COUNTER4_INT_TO_UC_EN 4 4 DCFE0_PERFMON_COUNTER5_INT_TO_UC_EN 5 5 DCFE0_PERFMON_COUNTER6_INT_TO_UC_EN 6 6 DCFE0_PERFMON_COUNTER7_INT_TO_UC_EN 7 7 DCFE1_PERFMON_COUNTER0_INT_TO_UC_EN 8 8 DCFE1_PERFMON_COUNTER1_INT_TO_UC_EN 9 9 DCFE1_PERFMON_COUNTER2_INT_TO_UC_EN 10 10 DCFE1_PERFMON_COUNTER3_INT_TO_UC_EN 11 11 DCFE1_PERFMON_COUNTER4_INT_TO_UC_EN 12 12 DCFE1_PERFMON_COUNTER5_INT_TO_UC_EN 13 13 DCFE1_PERFMON_COUNTER6_INT_TO_UC_EN 14 14 DCFE1_PERFMON_COUNTER7_INT_TO_UC_EN 15 15 DCFE2_PERFMON_COUNTER0_INT_TO_UC_EN 16 16 DCFE2_PERFMON_COUNTER1_INT_TO_UC_EN 17 17 DCFE2_PERFMON_COUNTER2_INT_TO_UC_EN 18 18 DCFE2_PERFMON_COUNTER3_INT_TO_UC_EN 19 19 DCFE2_PERFMON_COUNTER4_INT_TO_UC_EN 20 20 DCFE2_PERFMON_COUNTER5_INT_TO_UC_EN 21 21 DCFE2_PERFMON_COUNTER6_INT_TO_UC_EN 22 22 DCFE2_PERFMON_COUNTER7_INT_TO_UC_EN 23 23 DCFE0_PERFMON_COUNTER_OFF_INT_TO_UC_EN 24 24 DCFE1_PERFMON_COUNTER_OFF_INT_TO_UC_EN 25 25 DCFE2_PERFMON_COUNTER_OFF_INT_TO_UC_EN 26 26 mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3 0 0x42c 27 0 2 DCFE3_PERFMON_COUNTER0_INT_TO_UC_EN 0 0 DCFE3_PERFMON_COUNTER1_INT_TO_UC_EN 1 1 DCFE3_PERFMON_COUNTER2_INT_TO_UC_EN 2 2 DCFE3_PERFMON_COUNTER3_INT_TO_UC_EN 3 3 DCFE3_PERFMON_COUNTER4_INT_TO_UC_EN 4 4 DCFE3_PERFMON_COUNTER5_INT_TO_UC_EN 5 5 DCFE3_PERFMON_COUNTER6_INT_TO_UC_EN 6 6 DCFE3_PERFMON_COUNTER7_INT_TO_UC_EN 7 7 DCFE4_PERFMON_COUNTER0_INT_TO_UC_EN 8 8 DCFE4_PERFMON_COUNTER1_INT_TO_UC_EN 9 9 DCFE4_PERFMON_COUNTER2_INT_TO_UC_EN 10 10 DCFE4_PERFMON_COUNTER3_INT_TO_UC_EN 11 11 DCFE4_PERFMON_COUNTER4_INT_TO_UC_EN 12 12 DCFE4_PERFMON_COUNTER5_INT_TO_UC_EN 13 13 DCFE4_PERFMON_COUNTER6_INT_TO_UC_EN 14 14 DCFE4_PERFMON_COUNTER7_INT_TO_UC_EN 15 15 DCFE5_PERFMON_COUNTER0_INT_TO_UC_EN 16 16 DCFE5_PERFMON_COUNTER1_INT_TO_UC_EN 17 17 DCFE5_PERFMON_COUNTER2_INT_TO_UC_EN 18 18 DCFE5_PERFMON_COUNTER3_INT_TO_UC_EN 19 19 DCFE5_PERFMON_COUNTER4_INT_TO_UC_EN 20 20 DCFE5_PERFMON_COUNTER5_INT_TO_UC_EN 21 21 DCFE5_PERFMON_COUNTER6_INT_TO_UC_EN 22 22 DCFE5_PERFMON_COUNTER7_INT_TO_UC_EN 23 23 DCFE3_PERFMON_COUNTER_OFF_INT_TO_UC_EN 24 24 DCFE4_PERFMON_COUNTER_OFF_INT_TO_UC_EN 25 25 DCFE5_PERFMON_COUNTER_OFF_INT_TO_UC_EN 26 26 mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4 0 0x42d 27 0 2 WB_PERFMON_COUNTER0_INT_TO_UC_EN 0 0 WB_PERFMON_COUNTER1_INT_TO_UC_EN 1 1 WB_PERFMON_COUNTER2_INT_TO_UC_EN 2 2 WB_PERFMON_COUNTER3_INT_TO_UC_EN 3 3 WB_PERFMON_COUNTER4_INT_TO_UC_EN 4 4 WB_PERFMON_COUNTER5_INT_TO_UC_EN 5 5 WB_PERFMON_COUNTER6_INT_TO_UC_EN 6 6 WB_PERFMON_COUNTER7_INT_TO_UC_EN 7 7 DCRX_PERFMON_COUNTER0_INT_TO_UC_EN 8 8 DCRX_PERFMON_COUNTER1_INT_TO_UC_EN 9 9 DCRX_PERFMON_COUNTER2_INT_TO_UC_EN 10 10 DCRX_PERFMON_COUNTER3_INT_TO_UC_EN 11 11 DCRX_PERFMON_COUNTER4_INT_TO_UC_EN 12 12 DCRX_PERFMON_COUNTER5_INT_TO_UC_EN 13 13 DCRX_PERFMON_COUNTER6_INT_TO_UC_EN 14 14 DCRX_PERFMON_COUNTER7_INT_TO_UC_EN 15 15 DCCG_PERFMON2_COUNTER0_INT_TO_UC_EN 16 16 DCCG_PERFMON2_COUNTER1_INT_TO_UC_EN 17 17 DCCG_PERFMON2_COUNTER2_INT_TO_UC_EN 18 18 DCCG_PERFMON2_COUNTER3_INT_TO_UC_EN 19 19 DCCG_PERFMON2_COUNTER4_INT_TO_UC_EN 20 20 DCCG_PERFMON2_COUNTER5_INT_TO_UC_EN 21 21 DCCG_PERFMON2_COUNTER6_INT_TO_UC_EN 22 22 DCCG_PERFMON2_COUNTER7_INT_TO_UC_EN 23 23 WB_PERFMON_COUNTER_OFF_INT_TO_UC_EN 24 24 DCRX_PERFMON_COUNTER_OFF_INT_TO_UC_EN 25 25 DCCG_PERFMON2_COUNTER_OFF_INT_TO_UC_EN 26 26 mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1 0 0x42e 27 0 2 DCI_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL 0 0 DCI_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL 1 1 DCI_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL 2 2 DCI_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL 3 3 DCI_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL 4 4 DCI_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL 5 5 DCI_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL 6 6 DCI_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL 7 7 DCO_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL 8 8 DCO_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL 9 9 DCO_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL 10 10 DCO_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL 11 11 DCO_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL 12 12 DCO_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL 13 13 DCO_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL 14 14 DCO_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL 15 15 DCCG_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL 16 16 DCCG_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL 17 17 DCCG_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL 18 18 DCCG_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL 19 19 DCCG_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL 20 20 DCCG_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL 21 21 DCCG_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL 22 22 DCCG_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL 23 23 DCI_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL 24 24 DCO_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL 25 25 DCCG_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL 26 26 mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2 0 0x42f 27 0 2 DCFE0_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL 0 0 DCFE0_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL 1 1 DCFE0_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL 2 2 DCFE0_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL 3 3 DCFE0_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL 4 4 DCFE0_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL 5 5 DCFE0_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL 6 6 DCFE0_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL 7 7 DCFE1_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL 8 8 DCFE1_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL 9 9 DCFE1_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL 10 10 DCFE1_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL 11 11 DCFE1_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL 12 12 DCFE1_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL 13 13 DCFE1_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL 14 14 DCFE1_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL 15 15 DCFE2_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL 16 16 DCFE2_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL 17 17 DCFE2_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL 18 18 DCFE2_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL 19 19 DCFE2_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL 20 20 DCFE2_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL 21 21 DCFE2_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL 22 22 DCFE2_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL 23 23 DCFE0_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL 24 24 DCFE1_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL 25 25 DCFE2_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL 26 26 mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3 0 0x430 27 0 2 DCFE3_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL 0 0 DCFE3_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL 1 1 DCFE3_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL 2 2 DCFE3_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL 3 3 DCFE3_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL 4 4 DCFE3_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL 5 5 DCFE3_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL 6 6 DCFE3_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL 7 7 DCFE4_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL 8 8 DCFE4_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL 9 9 DCFE4_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL 10 10 DCFE4_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL 11 11 DCFE4_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL 12 12 DCFE4_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL 13 13 DCFE4_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL 14 14 DCFE4_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL 15 15 DCFE5_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL 16 16 DCFE5_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL 17 17 DCFE5_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL 18 18 DCFE5_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL 19 19 DCFE5_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL 20 20 DCFE5_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL 21 21 DCFE5_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL 22 22 DCFE5_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL 23 23 DCFE3_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL 24 24 DCFE4_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL 25 25 DCFE5_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL 26 26 mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4 0 0x431 27 0 2 WB_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL 0 0 WB_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL 1 1 WB_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL 2 2 WB_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL 3 3 WB_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL 4 4 WB_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL 5 5 WB_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL 6 6 WB_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL 7 7 DCRX_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL 8 8 DCRX_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL 9 9 DCRX_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL 10 10 DCRX_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL 11 11 DCRX_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL 12 12 DCRX_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL 13 13 DCRX_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL 14 14 DCRX_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL 15 15 DCCG_PERFMON2_COUNTER0_INT_XIRQ_IRQ_SEL 16 16 DCCG_PERFMON2_COUNTER1_INT_XIRQ_IRQ_SEL 17 17 DCCG_PERFMON2_COUNTER2_INT_XIRQ_IRQ_SEL 18 18 DCCG_PERFMON2_COUNTER3_INT_XIRQ_IRQ_SEL 19 19 DCCG_PERFMON2_COUNTER4_INT_XIRQ_IRQ_SEL 20 20 DCCG_PERFMON2_COUNTER5_INT_XIRQ_IRQ_SEL 21 21 DCCG_PERFMON2_COUNTER6_INT_XIRQ_IRQ_SEL 22 22 DCCG_PERFMON2_COUNTER7_INT_XIRQ_IRQ_SEL 23 23 WB_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL 24 24 DCRX_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL 25 25 DCCG_PERFMON2_COUNTER_OFF_INT_XIRQ_IRQ_SEL 26 26 mmDC_ABM1_OVERSCAN_PIXEL_VALUE 0 0x451 3 0 2 ABM1_OVERSCAN_R_PIXEL_VALUE 0 9 ABM1_OVERSCAN_G_PIXEL_VALUE 10 19 ABM1_OVERSCAN_B_PIXEL_VALUE 20 29 mmDC_ABM1_BL_MASTER_LOCK 0 0x452 1 0 2 ABM1_BL_MASTER_LOCK 31 31 mmAZALIA_CONTROLLER_CLOCK_GATING 0 0x4bc 2 0 2 ENABLE_CLOCK_GATING 0 0 CLOCK_ON_STATE 4 4 mmAZALIA_AUDIO_DTO 0 0x4bd 2 0 2 AZALIA_AUDIO_DTO_PHASE 0 15 AZALIA_AUDIO_DTO_MODULE 16 31 mmAZALIA_AUDIO_DTO_CONTROL 0 0x4be 1 0 2 AZALIA_AUDIO_FORCE_DTO 8 9 mmAZALIA_SOCCLK_CONTROL 0 0x4bf 1 0 2 AUDIO_STREAM_SOCCLK_DEEP_SLEEP_EXIT_EN 1 1 mmAZALIA_UNDERFLOW_FILLER_SAMPLE 0 0x4c0 1 0 2 AZALIA_UNDERFLOW_FILLER_SAMPLE 0 31 mmAZALIA_DATA_DMA_CONTROL 0 0x4c1 6 0 2 DATA_DMA_NON_SNOOP 0 1 INPUT_DATA_DMA_NON_SNOOP 2 3 DATA_DMA_ISOCHRONOUS 4 5 INPUT_DATA_DMA_ISOCHRONOUS 6 7 AZALIA_IOC_GENERATION_METHOD 16 16 AZALIA_UNDERFLOW_CONTROL 17 17 mmAZALIA_BDL_DMA_CONTROL 0 0x4c2 4 0 2 BDL_DMA_NON_SNOOP 0 1 INPUT_BDL_DMA_NON_SNOOP 2 3 BDL_DMA_ISOCHRONOUS 4 5 INPUT_BDL_DMA_ISOCHRONOUS 6 7 mmAZALIA_RIRB_AND_DP_CONTROL 0 0x4c3 3 0 2 RIRB_NON_SNOOP 0 0 DP_DMA_NON_SNOOP 4 4 DP_UPDATE_FREQ_DIVIDER 5 8 mmAZALIA_CORB_DMA_CONTROL 0 0x4c4 2 0 2 CORB_DMA_NON_SNOOP 0 0 CORB_DMA_ISOCHRONOUS 4 4 mmAZALIA_APPLICATION_POSITION_IN_CYCLIC_BUFFER 0 0x4cb 1 0 2 APPLICATION_POSITION_IN_CYCLIC_BUFFER 0 31 mmAZALIA_CYCLIC_BUFFER_SYNC 0 0x4cc 1 0 2 CYCLIC_BUFFER_SYNC_ENABLE 0 0 mmAZALIA_GLOBAL_CAPABILITIES 0 0x4cd 1 0 2 NUMBER_OF_SERIAL_DATA_OUTPUT_SIGNALS 1 2 mmAZALIA_OUTPUT_PAYLOAD_CAPABILITY 0 0x4ce 2 0 2 OUTPUT_PAYLOAD_CAPABILITY 0 15 OUTSTRMPAY 16 31 mmAZALIA_OUTPUT_STREAM_ARBITER_CONTROL 0 0x4cf 3 0 2 LATENCY_HIDING_LEVEL 0 7 SYS_MEM_ACTIVE_ENABLE 8 8 INPUT_LATENCY_HIDING_LEVEL 16 23 mmAZALIA_INPUT_PAYLOAD_CAPABILITY 0 0x4d0 2 0 2 INPUT_PAYLOAD_CAPABILITY 0 15 INSTRMPAY 16 31 mmAZALIA_INPUT_CRC0_CONTROL0 0 0x4d3 3 0 2 INPUT_CRC_EN 0 0 INPUT_CRC_BLOCK_MODE 4 4 INPUT_CRC_INSTANCE_SEL 8 10 mmAZALIA_INPUT_CRC0_CONTROL1 0 0x4d4 1 0 2 INPUT_CRC_BLOCK_SIZE 0 31 mmAZALIA_INPUT_CRC0_CONTROL2 0 0x4d5 1 0 2 INPUT_CRC_BLOCK_ITERATION 0 15 mmAZALIA_INPUT_CRC0_CONTROL3 0 0x4d6 3 0 2 INPUT_CRC_COMPLETE 0 0 INPUT_CRC_BLOCK_COMPLETE_PHASE 4 4 INPUT_CRC_CHANNEL_RESULT_SEL 8 10 mmAZALIA_INPUT_CRC0_RESULT 0 0x4d7 1 0 2 INPUT_CRC_RESULT 0 31 mmAZALIA_INPUT_CRC1_CONTROL0 0 0x4d8 3 0 2 INPUT_CRC_EN 0 0 INPUT_CRC_BLOCK_MODE 4 4 INPUT_CRC_INSTANCE_SEL 8 10 mmAZALIA_INPUT_CRC1_CONTROL1 0 0x4d9 1 0 2 INPUT_CRC_BLOCK_SIZE 0 31 mmAZALIA_INPUT_CRC1_CONTROL2 0 0x4da 1 0 2 INPUT_CRC_BLOCK_ITERATION 0 15 mmAZALIA_INPUT_CRC1_CONTROL3 0 0x4db 3 0 2 INPUT_CRC_COMPLETE 0 0 INPUT_CRC_BLOCK_COMPLETE_PHASE 4 4 INPUT_CRC_CHANNEL_RESULT_SEL 8 10 mmAZALIA_INPUT_CRC1_RESULT 0 0x4dc 1 0 2 INPUT_CRC_RESULT 0 31 mmAZALIA_CRC0_CONTROL0 0 0x4dd 4 0 2 CRC_EN 0 0 CRC_BLOCK_MODE 4 4 CRC_INSTANCE_SEL 8 10 CRC_SOURCE_SEL 12 12 mmAZALIA_CRC0_CONTROL1 0 0x4de 1 0 2 CRC_BLOCK_SIZE 0 31 mmAZALIA_CRC0_CONTROL2 0 0x4df 1 0 2 CRC_BLOCK_ITERATION 0 15 mmAZALIA_CRC0_CONTROL3 0 0x4e0 3 0 2 CRC_COMPLETE 0 0 CRC_BLOCK_COMPLETE_PHASE 4 4 CRC_CHANNEL_RESULT_SEL 8 10 mmAZALIA_CRC0_RESULT 0 0x4e1 1 0 2 CRC_RESULT 0 31 mmAZALIA_CRC1_CONTROL0 0 0x4e2 4 0 2 CRC_EN 0 0 CRC_BLOCK_MODE 4 4 CRC_INSTANCE_SEL 8 10 CRC_SOURCE_SEL 12 12 mmAZALIA_CRC1_CONTROL1 0 0x4e3 1 0 2 CRC_BLOCK_SIZE 0 31 mmAZALIA_CRC1_CONTROL2 0 0x4e4 1 0 2 CRC_BLOCK_ITERATION 0 15 mmAZALIA_CRC1_CONTROL3 0 0x4e5 3 0 2 CRC_COMPLETE 0 0 CRC_BLOCK_COMPLETE_PHASE 4 4 CRC_CHANNEL_RESULT_SEL 8 10 mmAZALIA_CRC1_RESULT 0 0x4e6 1 0 2 CRC_RESULT 0 31 mmAZALIA_MEM_PWR_CTRL 0 0x4e8 15 0 2 AZ_MEM_PWR_FORCE 0 1 AZ_MEM_PWR_DIS 2 2 AZ_INPUT_STREAM0_MEM_PWR_FORCE 3 4 AZ_INPUT_STREAM0_MEM_PWR_DIS 5 5 AZ_INPUT_STREAM1_MEM_PWR_FORCE 6 7 AZ_INPUT_STREAM1_MEM_PWR_DIS 8 8 AZ_INPUT_STREAM2_MEM_PWR_FORCE 9 10 AZ_INPUT_STREAM2_MEM_PWR_DIS 11 11 AZ_INPUT_STREAM3_MEM_PWR_FORCE 12 13 AZ_INPUT_STREAM3_MEM_PWR_DIS 14 14 AZ_INPUT_STREAM4_MEM_PWR_FORCE 15 16 AZ_INPUT_STREAM4_MEM_PWR_DIS 17 17 AZ_INPUT_STREAM5_MEM_PWR_FORCE 18 19 AZ_INPUT_STREAM5_MEM_PWR_DIS 20 20 AZ_MEM_PWR_MODE_SEL 28 29 mmAZALIA_MEM_PWR_STATUS 0 0x4e9 7 0 2 AZ_MEM_PWR_STATE 0 1 AZ_INPUT_STREAM0_MEM_PWR_STATE 2 3 AZ_INPUT_STREAM1_MEM_PWR_STATE 4 5 AZ_INPUT_STREAM2_MEM_PWR_STATE 6 7 AZ_INPUT_STREAM3_MEM_PWR_STATE 8 9 AZ_INPUT_STREAM4_MEM_PWR_STATE 10 11 AZ_INPUT_STREAM5_MEM_PWR_STATE 12 13 mmAZALIA_F0_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID 0 0x500 1 0 2 AZALIA_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID 0 31 mmAZALIA_F0_CODEC_ROOT_PARAMETER_REVISION_ID 0 0x501 1 0 2 AZALIA_CODEC_ROOT_PARAMETER_REVISION_ID 0 31 mmAZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL 0 0x502 2 0 2 HBR_CHANNEL_COUNT 0 2 COMPRESSED_CHANNEL_COUNT 4 6 mmAZALIA_F0_CODEC_RESYNC_FIFO_CONTROL 0 0x503 1 0 2 RESYNC_FIFO_STARTUP_KEEPOUT_WINDOW 0 5 mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_GROUP_TYPE 0 0x504 1 0 2 AZALIA_CODEC_FUNCTION_PARAMETER_GROUP_TYPE 0 31 mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES 0 0x505 2 0 2 AUDIO_RATE_CAPABILITIES 0 11 AUDIO_BIT_CAPABILITIES 16 20 mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS 0 0x506 1 0 2 AZALIA_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS 0 31 mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES 0 0x507 3 0 2 AZALIA_CODEC_FUNCTION_PARAMETER_POWER_STATES 0 29 CLKSTOP 30 30 EPSS 31 31 mmAZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE 0 0x508 4 0 2 POWER_STATE_SET 0 3 POWER_STATE_ACT 4 7 CLKSTOPOK 9 9 POWER_STATE_SETTINGS_RESET 10 10 mmAZALIA_F0_CODEC_FUNCTION_CONTROL_RESET 0 0x509 1 0 2 CODEC_RESET 0 0 mmAZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID 0 0x50a 4 0 2 SUBSYSTEM_ID_BYTE0 0 7 SUBSYSTEM_ID_BYTE1 8 15 SUBSYSTEM_ID_BYTE2 16 23 SUBSYSTEM_ID_BYTE3 24 31 mmAZALIA_F0_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION 0 0x50b 1 0 2 CONVERTER_SYNCHRONIZATION 0 7 mmCC_RCU_DC_AUDIO_PORT_CONNECTIVITY 0 0x50c 2 0 2 PORT_CONNECTIVITY 0 2 PORT_CONNECTIVITY_OVERRIDE_ENABLE 4 4 mmCC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY 0 0x50d 2 0 2 INPUT_PORT_CONNECTIVITY 0 2 INPUT_PORT_CONNECTIVITY_OVERRIDE_ENABLE 4 4 mmAZALIA_F0_GTC_GROUP_OFFSET0 0 0x50f 1 0 2 GTC_GROUP_OFFSET0 0 31 mmAZALIA_F0_GTC_GROUP_OFFSET1 0 0x510 1 0 2 GTC_GROUP_OFFSET1 0 31 mmAZALIA_F0_GTC_GROUP_OFFSET2 0 0x511 1 0 2 GTC_GROUP_OFFSET2 0 31 mmAZALIA_F0_GTC_GROUP_OFFSET3 0 0x512 1 0 2 GTC_GROUP_OFFSET3 0 31 mmAZALIA_F0_GTC_GROUP_OFFSET4 0 0x513 1 0 2 GTC_GROUP_OFFSET4 0 31 mmAZALIA_F0_GTC_GROUP_OFFSET5 0 0x514 1 0 2 GTC_GROUP_OFFSET5 0 31 mmAZALIA_F0_GTC_GROUP_OFFSET6 0 0x515 1 0 2 GTC_GROUP_OFFSET6 0 31 mmREG_DC_AUDIO_PORT_CONNECTIVITY 0 0x516 2 0 2 REG_PORT_CONNECTIVITY 0 2 REG_PORT_CONNECTIVITY_OVERRIDE_ENABLE 4 4 mmREG_DC_AUDIO_INPUT_PORT_CONNECTIVITY 0 0x517 2 0 2 REG_INPUT_PORT_CONNECTIVITY 0 2 REG_INPUT_PORT_CONNECTIVITY_OVERRIDE_ENABLE 4 4 mmDAC_ENABLE 0 0x155a 6 0 2 DAC_ENABLE 0 0 DAC_RESYNC_FIFO_ENABLE 1 1 DAC_RESYNC_FIFO_POINTER_SKEW 2 3 DAC_RESYNC_FIFO_ERROR 4 4 DAC_RESYNC_FIFO_ERROR_ACK 5 5 DAC_RESYNC_FIFO_TVOUT_SIM 8 8 mmDAC_SOURCE_SELECT 0 0x155b 2 0 2 DAC_SOURCE_SELECT 0 2 DAC_TV_SELECT 3 3 mmDAC_CRC_EN 0 0x155c 2 0 2 DAC_CRC_EN 0 0 DAC_CRC_CONT_EN 16 16 mmDAC_CRC_CONTROL 0 0x155d 2 0 2 DAC_CRC_FIELD 0 0 DAC_CRC_ONLY_BLANKB 8 8 mmDAC_CRC_SIG_RGB_MASK 0 0x155e 3 0 2 DAC_CRC_SIG_BLUE_MASK 0 9 DAC_CRC_SIG_GREEN_MASK 10 19 DAC_CRC_SIG_RED_MASK 20 29 mmDAC_CRC_SIG_CONTROL_MASK 0 0x155f 1 0 2 DAC_CRC_SIG_CONTROL_MASK 0 5 mmDAC_CRC_SIG_RGB 0 0x1560 3 0 2 DAC_CRC_SIG_BLUE 0 9 DAC_CRC_SIG_GREEN 10 19 DAC_CRC_SIG_RED 20 29 mmDAC_CRC_SIG_CONTROL 0 0x1561 1 0 2 DAC_CRC_SIG_CONTROL 0 5 mmDAC_SYNC_TRISTATE_CONTROL 0 0x1562 3 0 2 DAC_HSYNCA_TRISTATE 0 0 DAC_VSYNCA_TRISTATE 8 8 DAC_SYNCA_TRISTATE 16 16 mmDAC_STEREOSYNC_SELECT 0 0x1563 1 0 2 DAC_STEREOSYNC_SELECT 0 2 mmDAC_AUTODETECT_CONTROL 0 0x1564 3 0 2 DAC_AUTODETECT_MODE 0 1 DAC_AUTODETECT_FRAME_TIME_COUNTER 8 15 DAC_AUTODETECT_CHECK_MASK 16 18 mmDAC_AUTODETECT_CONTROL2 0 0x1565 2 0 2 DAC_AUTODETECT_POWERUP_COUNTER 0 7 DAC_AUTODETECT_TESTMODE 8 8 mmDAC_AUTODETECT_CONTROL3 0 0x1566 2 0 2 DAC_AUTODET_COMPARATOR_IN_DELAY 0 7 DAC_AUTODET_COMPARATOR_OUT_DELAY 8 15 mmDAC_AUTODETECT_STATUS 0 0x1567 5 0 2 DAC_AUTODETECT_STATUS 0 0 DAC_AUTODETECT_CONNECT 4 4 DAC_AUTODETECT_RED_SENSE 8 9 DAC_AUTODETECT_GREEN_SENSE 16 17 DAC_AUTODETECT_BLUE_SENSE 24 25 mmDAC_AUTODETECT_INT_CONTROL 0 0x1568 2 0 2 DAC_AUTODETECT_ACK 0 0 DAC_AUTODETECT_INT_ENABLE 16 16 mmDAC_FORCE_OUTPUT_CNTL 0 0x1569 3 0 2 DAC_FORCE_DATA_EN 0 0 DAC_FORCE_DATA_SEL 8 10 DAC_FORCE_DATA_ON_BLANKB_ONLY 24 24 mmDAC_FORCE_DATA 0 0x156a 1 0 2 DAC_FORCE_DATA 0 9 mmDAC_POWERDOWN 0 0x156b 4 0 2 DAC_POWERDOWN 0 0 DAC_POWERDOWN_BLUE 8 8 DAC_POWERDOWN_GREEN 16 16 DAC_POWERDOWN_RED 24 24 mmDAC_CONTROL 0 0x156c 3 0 2 DAC_DFORCE_EN 0 0 DAC_TV_ENABLE 8 8 DAC_ZSCALE_SHIFT 16 16 mmDAC_COMPARATOR_ENABLE 0 0x156d 5 0 2 DAC_COMP_DDET_REF_EN 0 0 DAC_COMP_SDET_REF_EN 8 8 DAC_R_ASYNC_ENABLE 16 16 DAC_G_ASYNC_ENABLE 17 17 DAC_B_ASYNC_ENABLE 18 18 mmDAC_COMPARATOR_OUTPUT 0 0x156e 4 0 2 DAC_COMPARATOR_OUTPUT 0 0 DAC_COMPARATOR_OUTPUT_BLUE 1 1 DAC_COMPARATOR_OUTPUT_GREEN 2 2 DAC_COMPARATOR_OUTPUT_RED 3 3 mmDAC_PWR_CNTL 0 0x156f 2 0 2 DAC_BG_MODE 0 1 DAC_PWRCNTL 16 17 mmDAC_DFT_CONFIG 0 0x1570 1 0 2 DAC_DFT_CONFIG 0 31 mmDAC_FIFO_STATUS 0 0x1571 8 0 2 DAC_FIFO_USE_OVERWRITE_LEVEL 1 1 DAC_FIFO_OVERWRITE_LEVEL 2 7 DAC_FIFO_CAL_AVERAGE_LEVEL 10 15 DAC_FIFO_MAXIMUM_LEVEL 16 19 DAC_FIFO_MINIMUM_LEVEL 22 25 DAC_FIFO_CALIBRATED 29 29 DAC_FIFO_FORCE_RECAL_AVERAGE 30 30 DAC_FIFO_FORCE_RECOMP_MINMAX 31 31 mmDC_I2C_CONTROL 0 0x1584 6 0 2 DC_I2C_GO 0 0 DC_I2C_SOFT_RESET 1 1 DC_I2C_SEND_RESET 2 2 DC_I2C_SW_STATUS_RESET 3 3 DC_I2C_DDC_SELECT 8 10 DC_I2C_TRANSACTION_COUNT 20 21 mmDC_I2C_ARBITRATION 0 0x1585 9 0 2 DC_I2C_SW_PRIORITY 0 1 DC_I2C_REG_RW_CNTL_STATUS 2 3 DC_I2C_NO_QUEUED_SW_GO 4 4 DC_I2C_ABORT_HW_XFER 8 8 DC_I2C_ABORT_SW_XFER 12 12 DC_I2C_SW_USE_I2C_REG_REQ 20 20 DC_I2C_SW_DONE_USING_I2C_REG 21 21 DC_I2C_DMCU_USE_I2C_REG_REQ 24 24 DC_I2C_DMCU_DONE_USING_I2C_REG 25 25 mmDC_I2C_INTERRUPT_CONTROL 0 0x1586 24 0 2 DC_I2C_SW_DONE_INT 0 0 DC_I2C_SW_DONE_ACK 1 1 DC_I2C_SW_DONE_MASK 2 2 DC_I2C_DDC1_HW_DONE_INT 4 4 DC_I2C_DDC1_HW_DONE_ACK 5 5 DC_I2C_DDC1_HW_DONE_MASK 6 6 DC_I2C_DDC2_HW_DONE_INT 8 8 DC_I2C_DDC2_HW_DONE_ACK 9 9 DC_I2C_DDC2_HW_DONE_MASK 10 10 DC_I2C_DDC3_HW_DONE_INT 12 12 DC_I2C_DDC3_HW_DONE_ACK 13 13 DC_I2C_DDC3_HW_DONE_MASK 14 14 DC_I2C_DDC4_HW_DONE_INT 16 16 DC_I2C_DDC4_HW_DONE_ACK 17 17 DC_I2C_DDC4_HW_DONE_MASK 18 18 DC_I2C_DDC5_HW_DONE_INT 20 20 DC_I2C_DDC5_HW_DONE_ACK 21 21 DC_I2C_DDC5_HW_DONE_MASK 22 22 DC_I2C_DDC6_HW_DONE_INT 24 24 DC_I2C_DDC6_HW_DONE_ACK 25 25 DC_I2C_DDC6_HW_DONE_MASK 26 26 DC_I2C_DDCVGA_HW_DONE_INT 27 27 DC_I2C_DDCVGA_HW_DONE_ACK 28 28 DC_I2C_DDCVGA_HW_DONE_MASK 29 29 mmDC_I2C_SW_STATUS 0 0x1587 12 0 2 DC_I2C_SW_STATUS 0 1 DC_I2C_SW_DONE 2 2 DC_I2C_SW_ABORTED 4 4 DC_I2C_SW_TIMEOUT 5 5 DC_I2C_SW_INTERRUPTED 6 6 DC_I2C_SW_BUFFER_OVERFLOW 7 7 DC_I2C_SW_STOPPED_ON_NACK 8 8 DC_I2C_SW_NACK0 12 12 DC_I2C_SW_NACK1 13 13 DC_I2C_SW_NACK2 14 14 DC_I2C_SW_NACK3 15 15 DC_I2C_SW_REQ 18 18 mmDC_I2C_DDC1_HW_STATUS 0 0x1588 7 0 2 DC_I2C_DDC1_HW_STATUS 0 1 DC_I2C_DDC1_HW_DONE 3 3 DC_I2C_DDC1_HW_REQ 16 16 DC_I2C_DDC1_HW_URG 17 17 DC_I2C_DDC1_EDID_DETECT_STATUS 20 20 DC_I2C_DDC1_EDID_DETECT_NUM_VALID_TRIES 24 27 DC_I2C_DDC1_EDID_DETECT_STATE 28 30 mmDC_I2C_DDC2_HW_STATUS 0 0x1589 7 0 2 DC_I2C_DDC2_HW_STATUS 0 1 DC_I2C_DDC2_HW_DONE 3 3 DC_I2C_DDC2_HW_REQ 16 16 DC_I2C_DDC2_HW_URG 17 17 DC_I2C_DDC2_EDID_DETECT_STATUS 20 20 DC_I2C_DDC2_EDID_DETECT_NUM_VALID_TRIES 24 27 DC_I2C_DDC2_EDID_DETECT_STATE 28 30 mmDC_I2C_DDC3_HW_STATUS 0 0x158a 7 0 2 DC_I2C_DDC3_HW_STATUS 0 1 DC_I2C_DDC3_HW_DONE 3 3 DC_I2C_DDC3_HW_REQ 16 16 DC_I2C_DDC3_HW_URG 17 17 DC_I2C_DDC3_EDID_DETECT_STATUS 20 20 DC_I2C_DDC3_EDID_DETECT_NUM_VALID_TRIES 24 27 DC_I2C_DDC3_EDID_DETECT_STATE 28 30 mmDC_I2C_DDC4_HW_STATUS 0 0x158b 7 0 2 DC_I2C_DDC4_HW_STATUS 0 1 DC_I2C_DDC4_HW_DONE 3 3 DC_I2C_DDC4_HW_REQ 16 16 DC_I2C_DDC4_HW_URG 17 17 DC_I2C_DDC4_EDID_DETECT_STATUS 20 20 DC_I2C_DDC4_EDID_DETECT_NUM_VALID_TRIES 24 27 DC_I2C_DDC4_EDID_DETECT_STATE 28 30 mmDC_I2C_DDC5_HW_STATUS 0 0x158c 7 0 2 DC_I2C_DDC5_HW_STATUS 0 1 DC_I2C_DDC5_HW_DONE 3 3 DC_I2C_DDC5_HW_REQ 16 16 DC_I2C_DDC5_HW_URG 17 17 DC_I2C_DDC5_EDID_DETECT_STATUS 20 20 DC_I2C_DDC5_EDID_DETECT_NUM_VALID_TRIES 24 27 DC_I2C_DDC5_EDID_DETECT_STATE 28 30 mmDC_I2C_DDC6_HW_STATUS 0 0x158d 7 0 2 DC_I2C_DDC6_HW_STATUS 0 1 DC_I2C_DDC6_HW_DONE 3 3 DC_I2C_DDC6_HW_REQ 16 16 DC_I2C_DDC6_HW_URG 17 17 DC_I2C_DDC6_EDID_DETECT_STATUS 20 20 DC_I2C_DDC6_EDID_DETECT_NUM_VALID_TRIES 24 27 DC_I2C_DDC6_EDID_DETECT_STATE 28 30 mmDC_I2C_DDC1_SPEED 0 0x158e 4 0 2 DC_I2C_DDC1_THRESHOLD 0 1 DC_I2C_DDC1_DISABLE_FILTER_DURING_STALL 4 4 DC_I2C_DDC1_START_STOP_TIMING_CNTL 8 9 DC_I2C_DDC1_PRESCALE 16 31 mmDC_I2C_DDC1_SETUP 0 0x158f 9 0 2 DC_I2C_DDC1_DATA_DRIVE_EN 0 0 DC_I2C_DDC1_DATA_DRIVE_SEL 1 1 DC_I2C_DDC1_EDID_DETECT_ENABLE 4 4 DC_I2C_DDC1_EDID_DETECT_MODE 5 5 DC_I2C_DDC1_ENABLE 6 6 DC_I2C_DDC1_CLK_DRIVE_EN 7 7 DC_I2C_DDC1_INTRA_BYTE_DELAY 8 15 DC_I2C_DDC1_INTRA_TRANSACTION_DELAY 16 23 DC_I2C_DDC1_TIME_LIMIT 24 31 mmDC_I2C_DDC2_SPEED 0 0x1590 4 0 2 DC_I2C_DDC2_THRESHOLD 0 1 DC_I2C_DDC2_DISABLE_FILTER_DURING_STALL 4 4 DC_I2C_DDC2_START_STOP_TIMING_CNTL 8 9 DC_I2C_DDC2_PRESCALE 16 31 mmDC_I2C_DDC2_SETUP 0 0x1591 9 0 2 DC_I2C_DDC2_DATA_DRIVE_EN 0 0 DC_I2C_DDC2_DATA_DRIVE_SEL 1 1 DC_I2C_DDC2_EDID_DETECT_ENABLE 4 4 DC_I2C_DDC2_EDID_DETECT_MODE 5 5 DC_I2C_DDC2_ENABLE 6 6 DC_I2C_DDC2_CLK_DRIVE_EN 7 7 DC_I2C_DDC2_INTRA_BYTE_DELAY 8 15 DC_I2C_DDC2_INTRA_TRANSACTION_DELAY 16 23 DC_I2C_DDC2_TIME_LIMIT 24 31 mmDC_I2C_DDC3_SPEED 0 0x1592 4 0 2 DC_I2C_DDC3_THRESHOLD 0 1 DC_I2C_DDC3_DISABLE_FILTER_DURING_STALL 4 4 DC_I2C_DDC3_START_STOP_TIMING_CNTL 8 9 DC_I2C_DDC3_PRESCALE 16 31 mmDC_I2C_DDC3_SETUP 0 0x1593 9 0 2 DC_I2C_DDC3_DATA_DRIVE_EN 0 0 DC_I2C_DDC3_DATA_DRIVE_SEL 1 1 DC_I2C_DDC3_EDID_DETECT_ENABLE 4 4 DC_I2C_DDC3_EDID_DETECT_MODE 5 5 DC_I2C_DDC3_ENABLE 6 6 DC_I2C_DDC3_CLK_DRIVE_EN 7 7 DC_I2C_DDC3_INTRA_BYTE_DELAY 8 15 DC_I2C_DDC3_INTRA_TRANSACTION_DELAY 16 23 DC_I2C_DDC3_TIME_LIMIT 24 31 mmDC_I2C_DDC4_SPEED 0 0x1594 4 0 2 DC_I2C_DDC4_THRESHOLD 0 1 DC_I2C_DDC4_DISABLE_FILTER_DURING_STALL 4 4 DC_I2C_DDC4_START_STOP_TIMING_CNTL 8 9 DC_I2C_DDC4_PRESCALE 16 31 mmDC_I2C_DDC4_SETUP 0 0x1595 9 0 2 DC_I2C_DDC4_DATA_DRIVE_EN 0 0 DC_I2C_DDC4_DATA_DRIVE_SEL 1 1 DC_I2C_DDC4_EDID_DETECT_ENABLE 4 4 DC_I2C_DDC4_EDID_DETECT_MODE 5 5 DC_I2C_DDC4_ENABLE 6 6 DC_I2C_DDC4_CLK_DRIVE_EN 7 7 DC_I2C_DDC4_INTRA_BYTE_DELAY 8 15 DC_I2C_DDC4_INTRA_TRANSACTION_DELAY 16 23 DC_I2C_DDC4_TIME_LIMIT 24 31 mmDC_I2C_DDC5_SPEED 0 0x1596 4 0 2 DC_I2C_DDC5_THRESHOLD 0 1 DC_I2C_DDC5_DISABLE_FILTER_DURING_STALL 4 4 DC_I2C_DDC5_START_STOP_TIMING_CNTL 8 9 DC_I2C_DDC5_PRESCALE 16 31 mmDC_I2C_DDC5_SETUP 0 0x1597 9 0 2 DC_I2C_DDC5_DATA_DRIVE_EN 0 0 DC_I2C_DDC5_DATA_DRIVE_SEL 1 1 DC_I2C_DDC5_EDID_DETECT_ENABLE 4 4 DC_I2C_DDC5_EDID_DETECT_MODE 5 5 DC_I2C_DDC5_ENABLE 6 6 DC_I2C_DDC5_CLK_DRIVE_EN 7 7 DC_I2C_DDC5_INTRA_BYTE_DELAY 8 15 DC_I2C_DDC5_INTRA_TRANSACTION_DELAY 16 23 DC_I2C_DDC5_TIME_LIMIT 24 31 mmDC_I2C_DDC6_SPEED 0 0x1598 4 0 2 DC_I2C_DDC6_THRESHOLD 0 1 DC_I2C_DDC6_DISABLE_FILTER_DURING_STALL 4 4 DC_I2C_DDC6_START_STOP_TIMING_CNTL 8 9 DC_I2C_DDC6_PRESCALE 16 31 mmDC_I2C_DDC6_SETUP 0 0x1599 9 0 2 DC_I2C_DDC6_DATA_DRIVE_EN 0 0 DC_I2C_DDC6_DATA_DRIVE_SEL 1 1 DC_I2C_DDC6_EDID_DETECT_ENABLE 4 4 DC_I2C_DDC6_EDID_DETECT_MODE 5 5 DC_I2C_DDC6_ENABLE 6 6 DC_I2C_DDC6_CLK_DRIVE_EN 7 7 DC_I2C_DDC6_INTRA_BYTE_DELAY 8 15 DC_I2C_DDC6_INTRA_TRANSACTION_DELAY 16 23 DC_I2C_DDC6_TIME_LIMIT 24 31 mmDC_I2C_TRANSACTION0 0 0x159a 5 0 2 DC_I2C_RW0 0 0 DC_I2C_STOP_ON_NACK0 8 8 DC_I2C_START0 12 12 DC_I2C_STOP0 13 13 DC_I2C_COUNT0 16 25 mmDC_I2C_TRANSACTION1 0 0x159b 5 0 2 DC_I2C_RW1 0 0 DC_I2C_STOP_ON_NACK1 8 8 DC_I2C_START1 12 12 DC_I2C_STOP1 13 13 DC_I2C_COUNT1 16 25 mmDC_I2C_TRANSACTION2 0 0x159c 5 0 2 DC_I2C_RW2 0 0 DC_I2C_STOP_ON_NACK2 8 8 DC_I2C_START2 12 12 DC_I2C_STOP2 13 13 DC_I2C_COUNT2 16 25 mmDC_I2C_TRANSACTION3 0 0x159d 5 0 2 DC_I2C_RW3 0 0 DC_I2C_STOP_ON_NACK3 8 8 DC_I2C_START3 12 12 DC_I2C_STOP3 13 13 DC_I2C_COUNT3 16 25 mmDC_I2C_DATA 0 0x159e 4 0 2 DC_I2C_DATA_RW 0 0 DC_I2C_DATA 8 15 DC_I2C_INDEX 16 25 DC_I2C_INDEX_WRITE 31 31 mmDC_I2C_DDCVGA_HW_STATUS 0 0x159f 7 0 2 DC_I2C_DDCVGA_HW_STATUS 0 1 DC_I2C_DDCVGA_HW_DONE 3 3 DC_I2C_DDCVGA_HW_REQ 16 16 DC_I2C_DDCVGA_HW_URG 17 17 DC_I2C_DDCVGA_EDID_DETECT_STATUS 20 20 DC_I2C_DDCVGA_EDID_DETECT_NUM_VALID_TRIES 24 27 DC_I2C_DDCVGA_EDID_DETECT_STATE 28 30 mmDC_I2C_DDCVGA_SPEED 0 0x15a0 4 0 2 DC_I2C_DDCVGA_THRESHOLD 0 1 DC_I2C_DDCVGA_DISABLE_FILTER_DURING_STALL 4 4 DC_I2C_DDCVGA_START_STOP_TIMING_CNTL 8 9 DC_I2C_DDCVGA_PRESCALE 16 31 mmDC_I2C_DDCVGA_SETUP 0 0x15a1 9 0 2 DC_I2C_DDCVGA_DATA_DRIVE_EN 0 0 DC_I2C_DDCVGA_DATA_DRIVE_SEL 1 1 DC_I2C_DDCVGA_EDID_DETECT_ENABLE 4 4 DC_I2C_DDCVGA_EDID_DETECT_MODE 5 5 DC_I2C_DDCVGA_ENABLE 6 6 DC_I2C_DDCVGA_CLK_DRIVE_EN 7 7 DC_I2C_DDCVGA_INTRA_BYTE_DELAY 8 15 DC_I2C_DDCVGA_INTRA_TRANSACTION_DELAY 16 23 DC_I2C_DDCVGA_TIME_LIMIT 24 31 mmDC_I2C_EDID_DETECT_CTRL 0 0x15a2 3 0 2 DC_I2C_EDID_DETECT_WAIT_TIME 0 15 DC_I2C_EDID_DETECT_NUM_TRIES_UNTIL_VALID 20 23 DC_I2C_EDID_DETECT_SEND_RESET 28 28 mmDC_I2C_READ_REQUEST_INTERRUPT 0 0x15a3 30 0 2 DC_I2C_DDC1_READ_REQUEST_OCCURRED 0 0 DC_I2C_DDC1_READ_REQUEST_INT 1 1 DC_I2C_DDC1_READ_REQUEST_ACK 2 2 DC_I2C_DDC1_READ_REQUEST_MASK 3 3 DC_I2C_DDC2_READ_REQUEST_OCCURRED 4 4 DC_I2C_DDC2_READ_REQUEST_INT 5 5 DC_I2C_DDC2_READ_REQUEST_ACK 6 6 DC_I2C_DDC2_READ_REQUEST_MASK 7 7 DC_I2C_DDC3_READ_REQUEST_OCCURRED 8 8 DC_I2C_DDC3_READ_REQUEST_INT 9 9 DC_I2C_DDC3_READ_REQUEST_ACK 10 10 DC_I2C_DDC3_READ_REQUEST_MASK 11 11 DC_I2C_DDC4_READ_REQUEST_OCCURRED 12 12 DC_I2C_DDC4_READ_REQUEST_INT 13 13 DC_I2C_DDC4_READ_REQUEST_ACK 14 14 DC_I2C_DDC4_READ_REQUEST_MASK 15 15 DC_I2C_DDC5_READ_REQUEST_OCCURRED 16 16 DC_I2C_DDC5_READ_REQUEST_INT 17 17 DC_I2C_DDC5_READ_REQUEST_ACK 18 18 DC_I2C_DDC5_READ_REQUEST_MASK 19 19 DC_I2C_DDC6_READ_REQUEST_OCCURRED 20 20 DC_I2C_DDC6_READ_REQUEST_INT 21 21 DC_I2C_DDC6_READ_REQUEST_ACK 22 22 DC_I2C_DDC6_READ_REQUEST_MASK 23 23 DC_I2C_DDCVGA_READ_REQUEST_OCCURRED 24 24 DC_I2C_DDCVGA_READ_REQUEST_INT 25 25 DC_I2C_DDCVGA_READ_REQUEST_ACK 26 26 DC_I2C_DDCVGA_READ_REQUEST_MASK 27 27 DC_I2C_DDC_READ_REQUEST_ACK_ENABLE 30 30 DC_I2C_DDC_READ_REQUEST_INT_TYPE 31 31 mmGENERIC_I2C_CONTROL 0 0x15a4 4 0 2 GENERIC_I2C_GO 0 0 GENERIC_I2C_SOFT_RESET 1 1 GENERIC_I2C_SEND_RESET 2 2 GENERIC_I2C_ENABLE 3 3 mmGENERIC_I2C_INTERRUPT_CONTROL 0 0x15a5 3 0 2 GENERIC_I2C_DONE_INT 0 0 GENERIC_I2C_DONE_ACK 1 1 GENERIC_I2C_DONE_MASK 2 2 mmGENERIC_I2C_STATUS 0 0x15a6 6 0 2 GENERIC_I2C_STATUS 0 3 GENERIC_I2C_DONE 4 4 GENERIC_I2C_ABORTED 5 5 GENERIC_I2C_TIMEOUT 6 6 GENERIC_I2C_STOPPED_ON_NACK 9 9 GENERIC_I2C_NACK 10 10 mmGENERIC_I2C_SPEED 0 0x15a7 4 0 2 GENERIC_I2C_THRESHOLD 0 1 GENERIC_I2C_DISABLE_FILTER_DURING_STALL 4 4 GENERIC_I2C_START_STOP_TIMING_CNTL 8 9 GENERIC_I2C_PRESCALE 16 31 mmGENERIC_I2C_SETUP 0 0x15a8 5 0 2 GENERIC_I2C_DATA_DRIVE_EN 0 0 GENERIC_I2C_DATA_DRIVE_SEL 1 1 GENERIC_I2C_CLK_DRIVE_EN 7 7 GENERIC_I2C_INTRA_BYTE_DELAY 8 15 GENERIC_I2C_TIME_LIMIT 24 31 mmGENERIC_I2C_TRANSACTION 0 0x15a9 6 0 2 GENERIC_I2C_RW 0 0 GENERIC_I2C_STOP_ON_NACK 8 8 GENERIC_I2C_ACK_ON_READ 9 9 GENERIC_I2C_START 12 12 GENERIC_I2C_STOP 13 13 GENERIC_I2C_COUNT 16 19 mmGENERIC_I2C_DATA 0 0x15aa 4 0 2 GENERIC_I2C_DATA_RW 0 0 GENERIC_I2C_DATA 8 15 GENERIC_I2C_INDEX 16 19 GENERIC_I2C_INDEX_WRITE 31 31 mmGENERIC_I2C_PIN_SELECTION 0 0x15ab 2 0 2 GENERIC_I2C_SCL_PIN_SEL 0 6 GENERIC_I2C_SDA_PIN_SEL 8 14 mmDCO_SCRATCH0 0 0x15b6 1 0 2 DCO_SCRATCH0 0 31 mmDCO_SCRATCH1 0 0x15b7 1 0 2 DCO_SCRATCH1 0 31 mmDCO_SCRATCH2 0 0x15b8 1 0 2 DCO_SCRATCH2 0 31 mmDCO_SCRATCH3 0 0x15b9 1 0 2 DCO_SCRATCH3 0 31 mmDCO_SCRATCH4 0 0x15ba 1 0 2 DCO_SCRATCH4 0 31 mmDCO_SCRATCH5 0 0x15bb 1 0 2 DCO_SCRATCH5 0 31 mmDCO_SCRATCH6 0 0x15bc 1 0 2 DCO_SCRATCH6 0 31 mmDCO_SCRATCH7 0 0x15bd 1 0 2 DCO_SCRATCH7 0 31 mmDCE_VCE_CONTROL 0 0x15be 2 0 2 DC_VCE_VIDEO_PIPE_SELECT 0 2 DC_VCE_AUDIO_STREAM_SELECT 4 6 mmDISP_INTERRUPT_STATUS 0 0x15bf 26 0 2 SCL_DISP1_MODE_CHANGE_INTERRUPT 0 0 D1BLND_DATA_UNDERFLOW_INTERRUPT 1 1 LB_D1_VLINE_INTERRUPT 2 2 LB_D1_VBLANK_INTERRUPT 3 3 CRTC1_SNAPSHOT_INTERRUPT 4 4 CRTC1_FORCE_VSYNC_NEXT_LINE_INTERRUPT 5 5 CRTC1_FORCE_COUNT_NOW_INTERRUPT 6 6 CRTC1_TRIGA_INTERRUPT 7 7 CRTC1_TRIGB_INTERRUPT 8 8 CRTC1_VSYNC_NOM_INTERRUPT 9 9 CRTC1_SET_V_TOTAL_MIN_EVENT_OCCURED_INT 10 10 DIGA_DP_FAST_TRAINING_COMPLETE_INTERRUPT 15 15 DIGA_DP_VID_STREAM_DISABLE_INTERRUPT 16 16 DC_HPD1_INTERRUPT 17 17 DC_HPD1_RX_INTERRUPT 18 18 AUX1_SW_DONE_INTERRUPT 19 19 AUX1_LS_DONE_INTERRUPT 20 20 DACA_AUTODETECT_INTERRUPT 22 22 DACB_AUTODETECT_INTERRUPT 23 23 DC_I2C_SW_DONE_INTERRUPT 24 24 DC_I2C_HW_DONE_INTERRUPT 25 25 DMCU_UC_INTERNAL_INT 26 26 ABM1_HG_READY_INT 28 28 ABM1_LS_READY_INT 29 29 ABM1_BL_UPDATE_INT 30 30 DISP_INTERRUPT_STATUS_CONTINUE 31 31 mmDISP_INTERRUPT_STATUS_CONTINUE 0 0x15c0 27 0 2 SCL_DISP2_MODE_CHANGE_INTERRUPT 0 0 D2BLND_DATA_UNDERFLOW_INTERRUPT 1 1 LB_D2_VLINE_INTERRUPT 2 2 LB_D2_VBLANK_INTERRUPT 3 3 CRTC2_SNAPSHOT_INTERRUPT 4 4 CRTC2_FORCE_VSYNC_NEXT_LINE_INTERRUPT 5 5 CRTC2_FORCE_COUNT_NOW_INTERRUPT 6 6 CRTC2_TRIGA_INTERRUPT 7 7 CRTC2_TRIGB_INTERRUPT 8 8 CRTC2_VSYNC_NOM_INTERRUPT 9 9 CRTC2_SET_V_TOTAL_MIN_EVENT_OCCURED_INT 10 10 DIGB_DP_FAST_TRAINING_COMPLETE_INTERRUPT 15 15 DIGB_DP_VID_STREAM_DISABLE_INTERRUPT 16 16 DC_HPD2_INTERRUPT 17 17 DC_HPD2_RX_INTERRUPT 18 18 AUX2_SW_DONE_INTERRUPT 19 19 AUX2_LS_DONE_INTERRUPT 20 20 LB_D1_VLINE2_INTERRUPT 21 21 LB_D2_VLINE2_INTERRUPT 22 22 LB_D3_VLINE2_INTERRUPT 23 23 CRTC1_EXT_TIMING_SYNC_LOSS_INTERRUPT 25 25 CRTC1_EXT_TIMING_SYNC_INTERRUPT 26 26 CRTC1_EXT_TIMING_SYNC_SIGNAL_INTERRUPT 27 27 CRTC1_VERTICAL_INTERRUPT0 28 28 CRTC1_VERTICAL_INTERRUPT1 29 29 CRTC1_VERTICAL_INTERRUPT2 30 30 DISP_INTERRUPT_STATUS_CONTINUE2 31 31 mmDISP_INTERRUPT_STATUS_CONTINUE2 0 0x15c1 27 0 2 SCL_DISP3_MODE_CHANGE_INTERRUPT 0 0 D3BLND_DATA_UNDERFLOW_INTERRUPT 1 1 LB_D3_VLINE_INTERRUPT 2 2 LB_D3_VBLANK_INTERRUPT 3 3 CRTC3_SNAPSHOT_INTERRUPT 4 4 CRTC3_FORCE_VSYNC_NEXT_LINE_INTERRUPT 5 5 CRTC3_FORCE_COUNT_NOW_INTERRUPT 6 6 CRTC3_TRIGA_INTERRUPT 7 7 CRTC3_TRIGB_INTERRUPT 8 8 CRTC3_VSYNC_NOM_INTERRUPT 9 9 CRTC3_SET_V_TOTAL_MIN_EVENT_OCCURED_INT 10 10 DIGC_DP_FAST_TRAINING_COMPLETE_INTERRUPT 15 15 DIGC_DP_VID_STREAM_DISABLE_INTERRUPT 16 16 DC_HPD3_INTERRUPT 17 17 DC_HPD3_RX_INTERRUPT 18 18 AUX3_SW_DONE_INTERRUPT 19 19 AUX3_LS_DONE_INTERRUPT 20 20 LB_D4_VLINE2_INTERRUPT 21 21 LB_D5_VLINE2_INTERRUPT 22 22 LB_D6_VLINE2_INTERRUPT 23 23 CRTC2_EXT_TIMING_SYNC_LOSS_INTERRUPT 25 25 CRTC2_EXT_TIMING_SYNC_INTERRUPT 26 26 CRTC2_EXT_TIMING_SYNC_SIGNAL_INTERRUPT 27 27 CRTC2_VERTICAL_INTERRUPT0 28 28 CRTC2_VERTICAL_INTERRUPT1 29 29 CRTC2_VERTICAL_INTERRUPT2 30 30 DISP_INTERRUPT_STATUS_CONTINUE3 31 31 mmDISP_INTERRUPT_STATUS_CONTINUE3 0 0x15c2 27 0 2 SCL_DISP4_MODE_CHANGE_INTERRUPT 0 0 D4BLND_DATA_UNDERFLOW_INTERRUPT 1 1 LB_D4_VLINE_INTERRUPT 2 2 LB_D4_VBLANK_INTERRUPT 3 3 CRTC4_SNAPSHOT_INTERRUPT 4 4 CRTC4_FORCE_VSYNC_NEXT_LINE_INTERRUPT 5 5 CRTC4_FORCE_COUNT_NOW_INTERRUPT 6 6 CRTC4_TRIGA_INTERRUPT 7 7 CRTC4_TRIGB_INTERRUPT 8 8 CRTC4_VSYNC_NOM_INTERRUPT 9 9 CRTC4_SET_V_TOTAL_MIN_EVENT_OCCURED_INT 10 10 DIGD_DP_FAST_TRAINING_COMPLETE_INTERRUPT 15 15 DIGD_DP_VID_STREAM_DISABLE_INTERRUPT 16 16 DC_HPD4_INTERRUPT 17 17 DC_HPD4_RX_INTERRUPT 18 18 AUX4_SW_DONE_INTERRUPT 19 19 AUX4_LS_DONE_INTERRUPT 20 20 BUFMGR_IHIF_INTERRUPT 21 21 WBSCL_HOST_CONFLICT_INTERRUPT 22 22 WBSCL_DATA_OVERFLOW_INTERRUPT 23 23 CRTC3_EXT_TIMING_SYNC_LOSS_INTERRUPT 25 25 CRTC3_EXT_TIMING_SYNC_INTERRUPT 26 26 CRTC3_EXT_TIMING_SYNC_SIGNAL_INTERRUPT 27 27 CRTC3_VERTICAL_INTERRUPT0 28 28 CRTC3_VERTICAL_INTERRUPT1 29 29 CRTC3_VERTICAL_INTERRUPT2 30 30 DISP_INTERRUPT_STATUS_CONTINUE4 31 31 mmDISP_INTERRUPT_STATUS_CONTINUE4 0 0x15c3 27 0 2 SCL_DISP5_MODE_CHANGE_INTERRUPT 0 0 D5BLND_DATA_UNDERFLOW_INTERRUPT 1 1 LB_D5_VLINE_INTERRUPT 2 2 LB_D5_VBLANK_INTERRUPT 3 3 CRTC5_SNAPSHOT_INTERRUPT 4 4 CRTC5_FORCE_VSYNC_NEXT_LINE_INTERRUPT 5 5 CRTC5_FORCE_COUNT_NOW_INTERRUPT 6 6 CRTC5_TRIGA_INTERRUPT 7 7 CRTC5_TRIGB_INTERRUPT 8 8 CRTC5_VSYNC_NOM_INTERRUPT 9 9 CRTC5_SET_V_TOTAL_MIN_EVENT_OCCURED_INT 10 10 DIGE_DP_FAST_TRAINING_COMPLETE_INTERRUPT 15 15 DIGE_DP_VID_STREAM_DISABLE_INTERRUPT 16 16 DC_HPD5_INTERRUPT 17 17 DC_HPD5_RX_INTERRUPT 18 18 AUX5_SW_DONE_INTERRUPT 19 19 AUX5_LS_DONE_INTERRUPT 20 20 CRTC4_EXT_TIMING_SYNC_LOSS_INTERRUPT 22 22 CRTC4_EXT_TIMING_SYNC_INTERRUPT 23 23 CRTC4_EXT_TIMING_SYNC_SIGNAL_INTERRUPT 24 24 CRTC5_EXT_TIMING_SYNC_LOSS_INTERRUPT 25 25 CRTC5_EXT_TIMING_SYNC_INTERRUPT 26 26 CRTC5_EXT_TIMING_SYNC_SIGNAL_INTERRUPT 27 27 CRTC4_VERTICAL_INTERRUPT0 28 28 CRTC4_VERTICAL_INTERRUPT1 29 29 CRTC4_VERTICAL_INTERRUPT2 30 30 DISP_INTERRUPT_STATUS_CONTINUE5 31 31 mmDISP_INTERRUPT_STATUS_CONTINUE5 0 0x15c4 27 0 2 SCL_DISP6_MODE_CHANGE_INTERRUPT 0 0 D6BLND_DATA_UNDERFLOW_INTERRUPT 1 1 LB_D6_VLINE_INTERRUPT 2 2 LB_D6_VBLANK_INTERRUPT 3 3 CRTC6_SNAPSHOT_INTERRUPT 4 4 CRTC6_FORCE_VSYNC_NEXT_LINE_INTERRUPT 5 5 CRTC6_FORCE_COUNT_NOW_INTERRUPT 6 6 CRTC6_TRIGA_INTERRUPT 7 7 CRTC6_TRIGB_INTERRUPT 8 8 CRTC6_VSYNC_NOM_INTERRUPT 9 9 CRTC6_SET_V_TOTAL_MIN_EVENT_OCCURED_INT 10 10 DIGF_DP_FAST_TRAINING_COMPLETE_INTERRUPT 15 15 DIGF_DP_VID_STREAM_DISABLE_INTERRUPT 16 16 DC_HPD6_INTERRUPT 17 17 DC_HPD6_RX_INTERRUPT 18 18 AUX6_SW_DONE_INTERRUPT 19 19 AUX6_LS_DONE_INTERRUPT 20 20 CRTC6_EXT_TIMING_SYNC_LOSS_INTERRUPT 22 22 CRTC6_EXT_TIMING_SYNC_INTERRUPT 23 23 CRTC6_EXT_TIMING_SYNC_SIGNAL_INTERRUPT 24 24 CRTC5_VERTICAL_INTERRUPT0 25 25 CRTC5_VERTICAL_INTERRUPT1 26 26 CRTC5_VERTICAL_INTERRUPT2 27 27 CRTC6_VERTICAL_INTERRUPT0 28 28 CRTC6_VERTICAL_INTERRUPT1 29 29 CRTC6_VERTICAL_INTERRUPT2 30 30 DISP_INTERRUPT_STATUS_CONTINUE6 31 31 mmDISP_INTERRUPT_STATUS_CONTINUE6 0 0x15c5 26 0 2 DCRX_PERFMON_COUNTER0_INTERRUPT 0 0 DCRX_PERFMON_COUNTER1_INTERRUPT 1 1 DCRX_PERFMON_COUNTER2_INTERRUPT 2 2 DCRX_PERFMON_COUNTER3_INTERRUPT 3 3 DCRX_PERFMON_COUNTER4_INTERRUPT 4 4 DCRX_PERFMON_COUNTER5_INTERRUPT 5 5 DCRX_PERFMON_COUNTER6_INTERRUPT 6 6 DCRX_PERFMON_COUNTER7_INTERRUPT 7 7 DCRX_PERFMON_COUNTER_OFF_INTERRUPT 8 8 BUFMGR_CWB0_IHIF_INTERRUPT 9 9 BUFMGR_CWB1_IHIF_INTERRUPT 10 10 DIGG_DP_FAST_TRAINING_COMPLETE_INTERRUPT 15 15 DIGG_DP_VID_STREAM_DISABLE_INTERRUPT 16 16 AUX1_GTC_SYNC_LOCK_DONE_INTERRUPT 17 17 AUX1_GTC_SYNC_ERROR_INTERRUPT 18 18 AUX2_GTC_SYNC_LOCK_DONE_INTERRUPT 19 19 AUX2_GTC_SYNC_ERROR_INTERRUPT 20 20 AUX3_GTC_SYNC_LOCK_DONE_INTERRUPT 21 21 AUX3_GTC_SYNC_ERROR_INTERRUPT 22 22 AUX4_GTC_SYNC_LOCK_DONE_INTERRUPT 23 23 AUX4_GTC_SYNC_ERROR_INTERRUPT 24 24 AUX5_GTC_SYNC_LOCK_DONE_INTERRUPT 25 25 AUX5_GTC_SYNC_ERROR_INTERRUPT 26 26 AUX6_GTC_SYNC_LOCK_DONE_INTERRUPT 27 27 AUX6_GTC_SYNC_ERROR_INTERRUPT 28 28 DISP_INTERRUPT_STATUS_CONTINUE7 31 31 mmDISP_INTERRUPT_STATUS_CONTINUE7 0 0x15c6 32 0 2 DCCG_PERFMON_COUNTER0_INTERRUPT 0 0 DCCG_PERFMON_COUNTER1_INTERRUPT 1 1 DCCG_PERFMON_COUNTER2_INTERRUPT 2 2 DCCG_PERFMON_COUNTER3_INTERRUPT 3 3 DCCG_PERFMON_COUNTER4_INTERRUPT 4 4 DCCG_PERFMON_COUNTER5_INTERRUPT 5 5 DCCG_PERFMON_COUNTER6_INTERRUPT 6 6 DCCG_PERFMON_COUNTER7_INTERRUPT 7 7 DCCG_PERFMON_COUNTER_OFF_INTERRUPT 8 8 DCI_PERFMON_COUNTER0_INTERRUPT 9 9 DCI_PERFMON_COUNTER1_INTERRUPT 10 10 DCI_PERFMON_COUNTER2_INTERRUPT 11 11 DCI_PERFMON_COUNTER3_INTERRUPT 12 12 DCI_PERFMON_COUNTER4_INTERRUPT 13 13 DCI_PERFMON_COUNTER5_INTERRUPT 14 14 DCI_PERFMON_COUNTER6_INTERRUPT 15 15 DCI_PERFMON_COUNTER7_INTERRUPT 16 16 DCI_PERFMON_COUNTER_OFF_INTERRUPT 17 17 DCO_PERFMON_COUNTER0_INTERRUPT 18 18 DCO_PERFMON_COUNTER1_INTERRUPT 19 19 DCO_PERFMON_COUNTER2_INTERRUPT 20 20 DCO_PERFMON_COUNTER3_INTERRUPT 21 21 DCO_PERFMON_COUNTER4_INTERRUPT 22 22 DCO_PERFMON_COUNTER5_INTERRUPT 23 23 DCO_PERFMON_COUNTER6_INTERRUPT 24 24 DCO_PERFMON_COUNTER7_INTERRUPT 25 25 DCO_PERFMON_COUNTER_OFF_INTERRUPT 26 26 WB_PERFMON_COUNTER0_INTERRUPT 27 27 WB_PERFMON_COUNTER1_INTERRUPT 28 28 WB_PERFMON_COUNTER2_INTERRUPT 29 29 WB_PERFMON_COUNTER3_INTERRUPT 30 30 DISP_INTERRUPT_STATUS_CONTINUE8 31 31 mmDISP_INTERRUPT_STATUS_CONTINUE8 0 0x15c7 32 0 2 DCFE0_PERFMON_COUNTER0_INTERRUPT 0 0 DCFE0_PERFMON_COUNTER1_INTERRUPT 1 1 DCFE0_PERFMON_COUNTER2_INTERRUPT 2 2 DCFE0_PERFMON_COUNTER3_INTERRUPT 3 3 DCFE0_PERFMON_COUNTER4_INTERRUPT 4 4 DCFE0_PERFMON_COUNTER5_INTERRUPT 5 5 DCFE0_PERFMON_COUNTER6_INTERRUPT 6 6 DCFE0_PERFMON_COUNTER7_INTERRUPT 7 7 DCFE0_PERFMON_COUNTER_OFF_INTERRUPT 8 8 DCFE1_PERFMON_COUNTER0_INTERRUPT 9 9 DCFE1_PERFMON_COUNTER1_INTERRUPT 10 10 DCFE1_PERFMON_COUNTER2_INTERRUPT 11 11 DCFE1_PERFMON_COUNTER3_INTERRUPT 12 12 DCFE1_PERFMON_COUNTER4_INTERRUPT 13 13 DCFE1_PERFMON_COUNTER5_INTERRUPT 14 14 DCFE1_PERFMON_COUNTER6_INTERRUPT 15 15 DCFE1_PERFMON_COUNTER7_INTERRUPT 16 16 DCFE1_PERFMON_COUNTER_OFF_INTERRUPT 17 17 DCFE2_PERFMON_COUNTER0_INTERRUPT 18 18 DCFE2_PERFMON_COUNTER1_INTERRUPT 19 19 DCFE2_PERFMON_COUNTER2_INTERRUPT 20 20 DCFE2_PERFMON_COUNTER3_INTERRUPT 21 21 DCFE2_PERFMON_COUNTER4_INTERRUPT 22 22 DCFE2_PERFMON_COUNTER5_INTERRUPT 23 23 DCFE2_PERFMON_COUNTER6_INTERRUPT 24 24 DCFE2_PERFMON_COUNTER7_INTERRUPT 25 25 DCFE2_PERFMON_COUNTER_OFF_INTERRUPT 26 26 WB_PERFMON_COUNTER4_INTERRUPT 27 27 WB_PERFMON_COUNTER5_INTERRUPT 28 28 WB_PERFMON_COUNTER6_INTERRUPT 29 29 WB_PERFMON_COUNTER7_INTERRUPT 30 30 DISP_INTERRUPT_STATUS_CONTINUE9 31 31 mmDISP_INTERRUPT_STATUS_CONTINUE9 0 0x15c8 29 0 2 DCFE3_PERFMON_COUNTER0_INTERRUPT 0 0 DCFE3_PERFMON_COUNTER1_INTERRUPT 1 1 DCFE3_PERFMON_COUNTER2_INTERRUPT 2 2 DCFE3_PERFMON_COUNTER3_INTERRUPT 3 3 DCFE3_PERFMON_COUNTER4_INTERRUPT 4 4 DCFE3_PERFMON_COUNTER5_INTERRUPT 5 5 DCFE3_PERFMON_COUNTER6_INTERRUPT 6 6 DCFE3_PERFMON_COUNTER7_INTERRUPT 7 7 DCFE3_PERFMON_COUNTER_OFF_INTERRUPT 8 8 DCFE4_PERFMON_COUNTER0_INTERRUPT 9 9 DCFE4_PERFMON_COUNTER1_INTERRUPT 10 10 DCFE4_PERFMON_COUNTER2_INTERRUPT 11 11 DCFE4_PERFMON_COUNTER3_INTERRUPT 12 12 DCFE4_PERFMON_COUNTER4_INTERRUPT 13 13 DCFE4_PERFMON_COUNTER5_INTERRUPT 14 14 DCFE4_PERFMON_COUNTER6_INTERRUPT 15 15 DCFE4_PERFMON_COUNTER7_INTERRUPT 16 16 DCFE4_PERFMON_COUNTER_OFF_INTERRUPT 17 17 DCFE5_PERFMON_COUNTER0_INTERRUPT 18 18 DCFE5_PERFMON_COUNTER1_INTERRUPT 19 19 DCFE5_PERFMON_COUNTER2_INTERRUPT 20 20 DCFE5_PERFMON_COUNTER3_INTERRUPT 21 21 DCFE5_PERFMON_COUNTER4_INTERRUPT 22 22 DCFE5_PERFMON_COUNTER5_INTERRUPT 23 23 DCFE5_PERFMON_COUNTER6_INTERRUPT 24 24 DCFE5_PERFMON_COUNTER7_INTERRUPT 25 25 DCFE5_PERFMON_COUNTER_OFF_INTERRUPT 26 26 WB_PERFMON_COUNTER_OFF_INTERRUPT 27 27 DISP_INTERRUPT_STATUS_CONTINUE10 31 31 mmDCO_MEM_PWR_STATUS 0 0x15c9 16 0 2 I2C_MEM_PWR_STATE 0 0 MVP_MEM_PWR_STATE 2 2 DPA_MEM_PWR_STATE 3 3 DPB_MEM_PWR_STATE 4 4 DPC_MEM_PWR_STATE 5 5 DPD_MEM_PWR_STATE 6 6 DPE_MEM_PWR_STATE 7 7 DPF_MEM_PWR_STATE 8 8 DPG_MEM_PWR_STATE 9 9 HDMI0_MEM_PWR_STATE 10 11 HDMI1_MEM_PWR_STATE 12 13 HDMI2_MEM_PWR_STATE 14 15 HDMI3_MEM_PWR_STATE 16 17 HDMI4_MEM_PWR_STATE 18 19 HDMI5_MEM_PWR_STATE 20 21 HDMI6_MEM_PWR_STATE 22 23 mmDCO_MEM_PWR_CTRL 0 0x15ca 24 0 2 I2C_LIGHT_SLEEP_FORCE 0 0 I2C_LIGHT_SLEEP_DIS 1 1 MVP_LIGHT_SLEEP_DIS 3 3 DPA_LIGHT_SLEEP_DIS 4 4 DPB_LIGHT_SLEEP_DIS 5 5 DPC_LIGHT_SLEEP_DIS 6 6 DPD_LIGHT_SLEEP_DIS 7 7 DPE_LIGHT_SLEEP_DIS 8 8 DPF_LIGHT_SLEEP_DIS 9 9 DPG_LIGHT_SLEEP_DIS 10 10 HDMI0_MEM_PWR_FORCE 11 12 HDMI0_MEM_PWR_DIS 13 13 HDMI1_MEM_PWR_FORCE 14 15 HDMI1_MEM_PWR_DIS 16 16 HDMI2_MEM_PWR_FORCE 17 18 HDMI2_MEM_PWR_DIS 19 19 HDMI3_MEM_PWR_FORCE 20 21 HDMI3_MEM_PWR_DIS 22 22 HDMI4_MEM_PWR_FORCE 23 24 HDMI4_MEM_PWR_DIS 25 25 HDMI5_MEM_PWR_FORCE 26 27 HDMI5_MEM_PWR_DIS 28 28 HDMI6_MEM_PWR_FORCE 29 30 HDMI6_MEM_PWR_DIS 31 31 mmDCO_MEM_PWR_CTRL2 0 0x15cb 7 0 2 HDMI_MEM_PWR_MODE_SEL 0 1 DPLPA_LIGHT_SLEEP_DIS 2 2 DPLPB_LIGHT_SLEEP_DIS 3 3 HDMILP0_MEM_PWR_FORCE 16 17 HDMILP0_MEM_PWR_DIS 18 18 HDMILP1_MEM_PWR_FORCE 19 20 HDMILP1_MEM_PWR_DIS 21 21 mmDCO_CLK_CNTL 0 0x15cc 21 0 2 DISPCLK_R_DCO_GATE_DIS 5 5 DISPCLK_G_ABM_GATE_DIS 6 6 DISPCLK_G_DVO_GATE_DIS 7 7 DISPCLK_G_DACA_GATE_DIS 8 8 DISPCLK_G_DACB_GATE_DIS 9 9 REFCLK_R_DCO_GATE_DIS 10 10 DISPCLK_G_FMT0_GATE_DIS 16 16 DISPCLK_G_FMT1_GATE_DIS 17 17 DISPCLK_G_FMT2_GATE_DIS 18 18 DISPCLK_G_FMT3_GATE_DIS 19 19 DISPCLK_G_FMT4_GATE_DIS 20 20 DISPCLK_G_FMT5_GATE_DIS 21 21 DISPCLK_G_DIGLPA_GATE_DIS 22 22 DISPCLK_G_DIGLPB_GATE_DIS 23 23 DISPCLK_G_DIGA_GATE_DIS 24 24 DISPCLK_G_DIGB_GATE_DIS 25 25 DISPCLK_G_DIGC_GATE_DIS 26 26 DISPCLK_G_DIGD_GATE_DIS 27 27 DISPCLK_G_DIGE_GATE_DIS 28 28 DISPCLK_G_DIGF_GATE_DIS 29 29 DISPCLK_G_DIGG_GATE_DIS 30 30 mmDCO_POWER_MANAGEMENT_CNTL 0 0x15d0 2 0 2 PM_ASSERT_RESET 0 0 PM_ALL_BUSY_OFF 8 8 mmDIG_SOFT_RESET_2 0 0x15d2 4 0 2 DIGLPA_FE_SOFT_RESET 0 0 DIGLPA_BE_SOFT_RESET 1 1 DIGLPB_FE_SOFT_RESET 4 4 DIGLPB_BE_SOFT_RESET 5 5 mmDCO_STEREOSYNC_SEL 0 0x15d6 2 0 2 GENERICA_STEREOSYNC_SEL 0 2 GENERICB_STEREOSYNC_SEL 16 18 mmDCO_SOFT_RESET 0 0x15d9 14 0 2 DACA_SOFT_RESET 0 0 I2S0_SPDIF0_SOFT_RESET 4 4 I2S1_SOFT_RESET 5 5 SPDIF1_SOFT_RESET 6 6 DB_CLK_SOFT_RESET 12 12 FMT0_SOFT_RESET 16 16 FMT1_SOFT_RESET 17 17 FMT2_SOFT_RESET 18 18 FMT3_SOFT_RESET 19 19 FMT4_SOFT_RESET 20 20 FMT5_SOFT_RESET 21 21 MVP_SOFT_RESET 24 24 ABM_SOFT_RESET 25 25 DVO_SOFT_RESET 27 27 mmDIG_SOFT_RESET 0 0x15da 14 0 2 DIGA_FE_SOFT_RESET 0 0 DIGA_BE_SOFT_RESET 1 1 DIGB_FE_SOFT_RESET 4 4 DIGB_BE_SOFT_RESET 5 5 DIGC_FE_SOFT_RESET 8 8 DIGC_BE_SOFT_RESET 9 9 DIGD_FE_SOFT_RESET 12 12 DIGD_BE_SOFT_RESET 13 13 DIGE_FE_SOFT_RESET 16 16 DIGE_BE_SOFT_RESET 17 17 DIGF_FE_SOFT_RESET 20 20 DIGF_BE_SOFT_RESET 21 21 DIGG_FE_SOFT_RESET 24 24 DIGG_BE_SOFT_RESET 25 25 mmDCO_MEM_PWR_STATUS1 0 0x15dc 4 0 2 DPLPA_MEM_PWR_STATE 0 0 DPLPB_MEM_PWR_STATE 1 1 HDMILP0_MEM_PWR_STATE 10 11 HDMILP1_MEM_PWR_STATE 12 13 mmDISP_INTERRUPT_STATUS_CONTINUE10 0 0x15dd 20 0 2 DIGLPA_DP_FAST_TRAINING_COMPLETE_INTERRUPT 4 4 DIGLPA_DP_VID_STREAM_DISABLE_INTERRUPT 5 5 DIGLPB_DP_FAST_TRAINING_COMPLETE_INTERRUPT 10 10 DIGLPB_DP_VID_STREAM_DISABLE_INTERRUPT 11 11 DCCG_PERFMON2_COUNTER0_INTERRUPT 12 12 DCCG_PERFMON2_COUNTER1_INTERRUPT 13 13 DCCG_PERFMON2_COUNTER2_INTERRUPT 14 14 DCCG_PERFMON2_COUNTER3_INTERRUPT 15 15 DCCG_PERFMON2_COUNTER4_INTERRUPT 16 16 DCCG_PERFMON2_COUNTER5_INTERRUPT 17 17 DCCG_PERFMON2_COUNTER6_INTERRUPT 18 18 DCCG_PERFMON2_COUNTER7_INTERRUPT 19 19 DCCG_PERFMON2_COUNTER_OFF_INTERRUPT 20 20 CRTC1_RANGE_TIMING_UPDATE 22 22 CRTC2_RANGE_TIMING_UPDATE 23 23 CRTC3_RANGE_TIMING_UPDATE 24 24 CRTC4_RANGE_TIMING_UPDATE 25 25 CRTC5_RANGE_TIMING_UPDATE 26 26 CRTC6_RANGE_TIMING_UPDATE 27 27 DISP_INTERRUPT_STATUS_CONTINUE11 31 31 mmDCO_CLK_CNTL2 0 0x15de 19 0 2 DCO_TEST_CLK_SEL 0 6 SCLK_G_AFMTA_GATE_DIS 7 7 SCLK_G_AFMTB_GATE_DIS 8 8 SCLK_G_AFMTC_GATE_DIS 9 9 SCLK_G_AFMTD_GATE_DIS 10 10 SCLK_G_AFMTE_GATE_DIS 11 11 SCLK_G_AFMTF_GATE_DIS 12 12 SCLK_G_AFMTG_GATE_DIS 13 13 SCLK_G_AFMTLPA_GATE_DIS 15 15 SCLK_G_AFMTLPB_GATE_DIS 16 16 SYMCLKA_FE_G_AFMT_GATE_DIS 17 17 SYMCLKB_FE_G_AFMT_GATE_DIS 18 18 SYMCLKC_FE_G_AFMT_GATE_DIS 19 19 SYMCLKD_FE_G_AFMT_GATE_DIS 20 20 SYMCLKE_FE_G_AFMT_GATE_DIS 21 21 SYMCLKF_FE_G_AFMT_GATE_DIS 22 22 SYMCLKG_FE_G_AFMT_GATE_DIS 23 23 SYMCLKLPA_FE_G_AFMT_GATE_DIS 25 25 SYMCLKLPB_FE_G_AFMT_GATE_DIS 26 26 mmDCO_CLK_CNTL3 0 0x15df 18 0 2 SYMCLKA_FE_G_TMDS_GATE_DIS 0 0 SYMCLKB_FE_G_TMDS_GATE_DIS 1 1 SYMCLKC_FE_G_TMDS_GATE_DIS 2 2 SYMCLKD_FE_G_TMDS_GATE_DIS 3 3 SYMCLKE_FE_G_TMDS_GATE_DIS 4 4 SYMCLKF_FE_G_TMDS_GATE_DIS 5 5 SYMCLKG_FE_G_TMDS_GATE_DIS 6 6 SYMCLKLPA_FE_G_TMDS_GATE_DIS 8 8 SYMCLKLPB_FE_G_TMDS_GATE_DIS 9 9 SYMCLKA_G_TMDS_GATE_DIS 10 10 SYMCLKB_G_TMDS_GATE_DIS 11 11 SYMCLKC_G_TMDS_GATE_DIS 12 12 SYMCLKD_G_TMDS_GATE_DIS 13 13 SYMCLKE_G_TMDS_GATE_DIS 14 14 SYMCLKF_G_TMDS_GATE_DIS 15 15 SYMCLKG_G_TMDS_GATE_DIS 16 16 SYMCLKLPA_G_TMDS_GATE_DIS 18 18 SYMCLKLPB_G_TMDS_GATE_DIS 19 19 mmDCO_HDMI_RXSTATUS_TIMER_CONTROL 0 0x15eb 5 0 2 DCO_HDMI_RXSTATUS_TIMER_ENABLE 0 0 DCO_HDMI_RXSTATUS_TIMER_TYPE 4 4 DCO_HDMI_RXSTATUS_TIMER_STATUS 8 8 DCO_HDMI_RXSTATUS_TIMER_MASK 12 12 DCO_HDMI_RXSTATUS_TIMER_INTERVAL 16 27 mmDCO_PSP_INTERRUPT_STATUS 0 0x15ec 2 0 2 DCO_PSP_INTERRUPT_STATUS 0 0 DCO_PSP_INTERRUPT_MESSAGE 1 31 mmDCO_PSP_INTERRUPT_CLEAR 0 0x15ed 1 0 2 DCO_PSP_INTERRUPT_CLEAR 0 0 mmDCO_GENERIC_INTERRUPT_MESSAGE 0 0x15ee 2 0 2 DCO_GENERIC_INTERRUPT_STATUS 0 0 DCO_GENERIC_INTERRUPT_MESSAGE 1 31 mmDCO_GENERIC_INTERRUPT_CLEAR 0 0x15ef 1 0 2 DCO_GENERIC_INTERRUPT_CLEAR 0 0 mmFMT_MEMORY0_CONTROL 0 0x15f0 4 0 2 FMT420_MEM0_SOURCE_SEL 0 2 FMT420_MEM0_PWR_FORCE 4 5 FMT420_MEM0_PWR_DIS 8 8 FMT420_MEM0_PWR_STATE 12 13 mmFMT_MEMORY1_CONTROL 0 0x15f1 4 0 2 FMT420_MEM1_SOURCE_SEL 0 2 FMT420_MEM1_PWR_FORCE 4 5 FMT420_MEM1_PWR_DIS 8 8 FMT420_MEM1_PWR_STATE 12 13 mmFMT_MEMORY2_CONTROL 0 0x15f2 4 0 2 FMT420_MEM2_SOURCE_SEL 0 2 FMT420_MEM2_PWR_FORCE 4 5 FMT420_MEM2_PWR_DIS 8 8 FMT420_MEM2_PWR_STATE 12 13 mmFMT_MEMORY3_CONTROL 0 0x15f3 4 0 2 FMT420_MEM3_SOURCE_SEL 0 2 FMT420_MEM3_PWR_FORCE 4 5 FMT420_MEM3_PWR_DIS 8 8 FMT420_MEM3_PWR_STATE 12 13 mmFMT_MEMORY4_CONTROL 0 0x15f4 4 0 2 FMT420_MEM4_SOURCE_SEL 0 2 FMT420_MEM4_PWR_FORCE 4 5 FMT420_MEM4_PWR_DIS 8 8 FMT420_MEM4_PWR_STATE 12 13 mmFMT_MEMORY5_CONTROL 0 0x15f5 4 0 2 FMT420_MEM5_SOURCE_SEL 0 2 FMT420_MEM5_PWR_FORCE 4 5 FMT420_MEM5_PWR_DIS 8 8 FMT420_MEM5_PWR_STATE 12 13 mmDISP_INTERRUPT_STATUS_CONTINUE11 0 0x15f6 6 0 2 DCP0_xdma_vsync_flip_timeout_interrupt 0 0 DCP1_xdma_vsync_flip_timeout_interrupt 1 1 DCP2_xdma_vsync_flip_timeout_interrupt 2 2 DCP3_xdma_vsync_flip_timeout_interrupt 3 3 DCP4_xdma_vsync_flip_timeout_interrupt 4 4 DCP5_xdma_vsync_flip_timeout_interrupt 5 5 mmDC_GENERICA 0 0x207e 6 0 2 GENERICA_EN 0 0 GENERICA_SEL 7 11 GENERICA_UNIPHY_REFDIV_CLK_SEL 12 15 GENERICA_UNIPHY_FBDIV_CLK_SEL 16 19 GENERICA_UNIPHY_FBDIV_SSC_CLK_SEL 20 23 GENERICA_UNIPHY_FBDIV_CLK_DIV2_SEL 24 27 mmDC_GENERICB 0 0x207f 6 0 2 GENERICB_EN 0 0 GENERICB_SEL 8 11 GENERICB_UNIPHY_REFDIV_CLK_SEL 12 15 GENERICB_UNIPHY_FBDIV_CLK_SEL 16 19 GENERICB_UNIPHY_FBDIV_SSC_CLK_SEL 20 23 GENERICB_UNIPHY_FBDIV_CLK_DIV2_SEL 24 27 mmDC_PAD_EXTERN_SIG 0 0x2080 2 0 2 DC_PAD_EXTERN_SIG_SEL 0 3 MVP_PIXEL_SRC_STATUS 4 5 mmDC_REF_CLK_CNTL 0 0x2081 2 0 2 HSYNCA_OUTPUT_SEL 0 1 GENLK_CLK_OUTPUT_SEL 8 9 mmDC_GPIO_DEBUG 0 0x2082 5 0 2 DC_GPIO_VIP_DEBUG 0 0 DC_GPIO_MACRO_DEBUG 8 9 DC_GPIO_CHIP_DEBUG_OUT_PIN_SEL 16 16 DC_GPIO_DEBUG_BUS_FLOP_EN 17 17 DPRX_LOOPBACK_ENABLE 31 31 mmUNIPHYA_LINK_CNTL 0 0x2083 9 0 2 UNIPHY_PFREQCHG 0 0 UNIPHY_PIXVLD_RESET 4 4 UNIPHY_MINIMUM_PIXVLD_LOW_DURATION 8 10 UNIPHY_CHANNEL0_INVERT 12 12 UNIPHY_CHANNEL1_INVERT 13 13 UNIPHY_CHANNEL2_INVERT 14 14 UNIPHY_CHANNEL3_INVERT 15 15 UNIPHY_LANE_STAGGER_DELAY 20 22 UNIPHY_LINK_ENABLE_HPD_MASK 24 25 mmUNIPHYA_CHANNEL_XBAR_CNTL 0 0x2084 5 0 2 UNIPHY_CHANNEL0_XBAR_SOURCE 0 1 UNIPHY_CHANNEL1_XBAR_SOURCE 8 9 UNIPHY_CHANNEL2_XBAR_SOURCE 16 17 UNIPHY_CHANNEL3_XBAR_SOURCE 24 25 UNIPHY_LINK_ENABLE 28 28 mmUNIPHYB_LINK_CNTL 0 0x2085 9 0 2 UNIPHY_PFREQCHG 0 0 UNIPHY_PIXVLD_RESET 4 4 UNIPHY_MINIMUM_PIXVLD_LOW_DURATION 8 10 UNIPHY_CHANNEL0_INVERT 12 12 UNIPHY_CHANNEL1_INVERT 13 13 UNIPHY_CHANNEL2_INVERT 14 14 UNIPHY_CHANNEL3_INVERT 15 15 UNIPHY_LANE_STAGGER_DELAY 20 22 UNIPHY_LINK_ENABLE_HPD_MASK 24 25 mmUNIPHYB_CHANNEL_XBAR_CNTL 0 0x2086 5 0 2 UNIPHY_CHANNEL0_XBAR_SOURCE 0 1 UNIPHY_CHANNEL1_XBAR_SOURCE 8 9 UNIPHY_CHANNEL2_XBAR_SOURCE 16 17 UNIPHY_CHANNEL3_XBAR_SOURCE 24 25 UNIPHY_LINK_ENABLE 28 28 mmUNIPHYC_LINK_CNTL 0 0x2087 9 0 2 UNIPHY_PFREQCHG 0 0 UNIPHY_PIXVLD_RESET 4 4 UNIPHY_MINIMUM_PIXVLD_LOW_DURATION 8 10 UNIPHY_CHANNEL0_INVERT 12 12 UNIPHY_CHANNEL1_INVERT 13 13 UNIPHY_CHANNEL2_INVERT 14 14 UNIPHY_CHANNEL3_INVERT 15 15 UNIPHY_LANE_STAGGER_DELAY 20 22 UNIPHY_LINK_ENABLE_HPD_MASK 24 25 mmUNIPHYC_CHANNEL_XBAR_CNTL 0 0x2088 5 0 2 UNIPHY_CHANNEL0_XBAR_SOURCE 0 1 UNIPHY_CHANNEL1_XBAR_SOURCE 8 9 UNIPHY_CHANNEL2_XBAR_SOURCE 16 17 UNIPHY_CHANNEL3_XBAR_SOURCE 24 25 UNIPHY_LINK_ENABLE 28 28 mmUNIPHYD_LINK_CNTL 0 0x2089 9 0 2 UNIPHY_PFREQCHG 0 0 UNIPHY_PIXVLD_RESET 4 4 UNIPHY_MINIMUM_PIXVLD_LOW_DURATION 8 10 UNIPHY_CHANNEL0_INVERT 12 12 UNIPHY_CHANNEL1_INVERT 13 13 UNIPHY_CHANNEL2_INVERT 14 14 UNIPHY_CHANNEL3_INVERT 15 15 UNIPHY_LANE_STAGGER_DELAY 20 22 UNIPHY_LINK_ENABLE_HPD_MASK 24 25 mmUNIPHYD_CHANNEL_XBAR_CNTL 0 0x208a 5 0 2 UNIPHY_CHANNEL0_XBAR_SOURCE 0 1 UNIPHY_CHANNEL1_XBAR_SOURCE 8 9 UNIPHY_CHANNEL2_XBAR_SOURCE 16 17 UNIPHY_CHANNEL3_XBAR_SOURCE 24 25 UNIPHY_LINK_ENABLE 28 28 mmUNIPHYE_LINK_CNTL 0 0x208b 9 0 2 UNIPHY_PFREQCHG 0 0 UNIPHY_PIXVLD_RESET 4 4 UNIPHY_MINIMUM_PIXVLD_LOW_DURATION 8 10 UNIPHY_CHANNEL0_INVERT 12 12 UNIPHY_CHANNEL1_INVERT 13 13 UNIPHY_CHANNEL2_INVERT 14 14 UNIPHY_CHANNEL3_INVERT 15 15 UNIPHY_LANE_STAGGER_DELAY 20 22 UNIPHY_LINK_ENABLE_HPD_MASK 24 25 mmUNIPHYE_CHANNEL_XBAR_CNTL 0 0x208c 5 0 2 UNIPHY_CHANNEL0_XBAR_SOURCE 0 1 UNIPHY_CHANNEL1_XBAR_SOURCE 8 9 UNIPHY_CHANNEL2_XBAR_SOURCE 16 17 UNIPHY_CHANNEL3_XBAR_SOURCE 24 25 UNIPHY_LINK_ENABLE 28 28 mmUNIPHYF_LINK_CNTL 0 0x208d 9 0 2 UNIPHY_PFREQCHG 0 0 UNIPHY_PIXVLD_RESET 4 4 UNIPHY_MINIMUM_PIXVLD_LOW_DURATION 8 10 UNIPHY_CHANNEL0_INVERT 12 12 UNIPHY_CHANNEL1_INVERT 13 13 UNIPHY_CHANNEL2_INVERT 14 14 UNIPHY_CHANNEL3_INVERT 15 15 UNIPHY_LANE_STAGGER_DELAY 20 22 UNIPHY_LINK_ENABLE_HPD_MASK 24 25 mmUNIPHYF_CHANNEL_XBAR_CNTL 0 0x208e 5 0 2 UNIPHY_CHANNEL0_XBAR_SOURCE 0 1 UNIPHY_CHANNEL1_XBAR_SOURCE 8 9 UNIPHY_CHANNEL2_XBAR_SOURCE 16 17 UNIPHY_CHANNEL3_XBAR_SOURCE 24 25 UNIPHY_LINK_ENABLE 28 28 mmUNIPHYG_LINK_CNTL 0 0x208f 9 0 2 UNIPHY_PFREQCHG 0 0 UNIPHY_PIXVLD_RESET 4 4 UNIPHY_MINIMUM_PIXVLD_LOW_DURATION 8 10 UNIPHY_CHANNEL0_INVERT 12 12 UNIPHY_CHANNEL1_INVERT 13 13 UNIPHY_CHANNEL2_INVERT 14 14 UNIPHY_CHANNEL3_INVERT 15 15 UNIPHY_LANE_STAGGER_DELAY 20 22 UNIPHY_LINK_ENABLE_HPD_MASK 24 25 mmUNIPHYG_CHANNEL_XBAR_CNTL 0 0x2090 5 0 2 UNIPHY_CHANNEL0_XBAR_SOURCE 0 1 UNIPHY_CHANNEL1_XBAR_SOURCE 8 9 UNIPHY_CHANNEL2_XBAR_SOURCE 16 17 UNIPHY_CHANNEL3_XBAR_SOURCE 24 25 UNIPHY_LINK_ENABLE 28 28 mmDCIO_WRCMD_DELAY 0 0x2094 5 0 2 UNIPHY_DELAY 0 3 DAC_DELAY 4 7 DPHY_DELAY 8 11 DCRXPHY_DELAY 12 15 ZCAL_DELAY 16 19 mmDC_PINSTRAPS 0 0x2096 1 0 2 DC_PINSTRAPS_AUDIO 14 15 mmCC_DC_MISC_STRAPS 0 0x2097 2 0 2 HDMI_DISABLE 6 6 AUDIO_STREAM_NUMBER 8 10 mmDC_DVODATA_CONFIG 0 0x2098 3 0 2 VIP_MUX_EN 19 19 VIP_ALTER_MAPPING_EN 20 20 DVO_ALTER_MAPPING_EN 21 21 mmLVTMA_PWRSEQ_CNTL 0 0x2099 12 0 2 LVTMA_PWRSEQ_EN 0 0 LVTMA_PWRSEQ_DISABLE_SYNCEN_CONTROL_OF_TX_EN 1 1 LVTMA_PWRSEQ_TARGET_STATE 4 4 LVTMA_SYNCEN 8 8 LVTMA_SYNCEN_OVRD 9 9 LVTMA_SYNCEN_POL 10 10 LVTMA_DIGON 16 16 LVTMA_DIGON_OVRD 17 17 LVTMA_DIGON_POL 18 18 LVTMA_BLON 24 24 LVTMA_BLON_OVRD 25 25 LVTMA_BLON_POL 26 26 mmLVTMA_PWRSEQ_STATE 0 0x209a 6 0 2 LVTMA_PWRSEQ_TARGET_STATE_R 0 0 LVTMA_PWRSEQ_DIGON 1 1 LVTMA_PWRSEQ_SYNCEN 2 2 LVTMA_PWRSEQ_BLON 3 3 LVTMA_PWRSEQ_DONE 4 4 LVTMA_PWRSEQ_STATE 8 11 mmLVTMA_PWRSEQ_REF_DIV 0 0x209b 2 0 2 LVTMA_PWRSEQ_REF_DIV 0 11 BL_PWM_REF_DIV 16 31 mmLVTMA_PWRSEQ_DELAY1 0 0x209c 4 0 2 LVTMA_PWRUP_DELAY1 0 7 LVTMA_PWRUP_DELAY2 8 15 LVTMA_PWRDN_DELAY1 16 23 LVTMA_PWRDN_DELAY2 24 31 mmLVTMA_PWRSEQ_DELAY2 0 0x209d 4 0 2 LVTMA_PWRDN_MIN_LENGTH 0 7 LVTMA_PWRUP_DELAY3 8 15 LVTMA_PWRDN_DELAY3 16 23 LVTMA_VARY_BL_OVERRIDE_EN 24 24 mmBL_PWM_CNTL 0 0x209e 3 0 2 BL_ACTIVE_INT_FRAC_CNT 0 15 BL_PWM_FRACTIONAL_EN 30 30 BL_PWM_EN 31 31 mmBL_PWM_CNTL2 0 0x209f 3 0 2 BL_PWM_POST_FRAME_START_DELAY_BEFORE_UPDATE 0 15 BL_PWM_OVERRIDE_BL_OUT_ENABLE 30 30 BL_PWM_OVERRIDE_LVTMA_PWRSEQ_EN 31 31 mmBL_PWM_PERIOD_CNTL 0 0x20a0 2 0 2 BL_PWM_PERIOD 0 15 BL_PWM_PERIOD_BITCNT 16 19 mmBL_PWM_GRP1_REG_LOCK 0 0x20a1 6 0 2 BL_PWM_GRP1_REG_LOCK 0 0 BL_PWM_GRP1_REG_UPDATE_PENDING 8 8 BL_PWM_GRP1_UPDATE_AT_FRAME_START 16 16 BL_PWM_GRP1_FRAME_START_DISP_SEL 17 19 BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN 24 24 BL_PWM_GRP1_IGNORE_MASTER_LOCK_EN 31 31 mmDCIO_GSL_GENLK_PAD_CNTL 0 0x20a2 6 0 2 DCIO_GENLK_CLK_GSL_TIMING_SYNC_SEL 0 1 DCIO_GENLK_CLK_GSL_FLIP_LOCK_SEL 4 5 DCIO_GENLK_CLK_GSL_MASK 8 9 DCIO_GENLK_VSYNC_GSL_TIMING_SYNC_SEL 16 17 DCIO_GENLK_VSYNC_GSL_FLIP_LOCK_SEL 20 21 DCIO_GENLK_VSYNC_GSL_MASK 24 25 mmDCIO_GSL_SWAPLOCK_PAD_CNTL 0 0x20a3 6 0 2 DCIO_SWAPLOCK_A_GSL_TIMING_SYNC_SEL 0 1 DCIO_SWAPLOCK_A_GSL_FLIP_LOCK_SEL 4 5 DCIO_SWAPLOCK_A_GSL_MASK 8 9 DCIO_SWAPLOCK_B_GSL_TIMING_SYNC_SEL 16 17 DCIO_SWAPLOCK_B_GSL_FLIP_LOCK_SEL 20 21 DCIO_SWAPLOCK_B_GSL_MASK 24 25 mmDCIO_GSL0_CNTL 0 0x20a4 3 0 2 DCIO_GSL0_VSYNC_SEL 0 2 DCIO_GSL0_TIMING_SYNC_SEL 8 10 DCIO_GSL0_GLOBAL_UNLOCK_SEL 16 18 mmDCIO_GSL1_CNTL 0 0x20a5 3 0 2 DCIO_GSL1_VSYNC_SEL 0 2 DCIO_GSL1_TIMING_SYNC_SEL 8 10 DCIO_GSL1_GLOBAL_UNLOCK_SEL 16 18 mmDCIO_GSL2_CNTL 0 0x20a6 3 0 2 DCIO_GSL2_VSYNC_SEL 0 2 DCIO_GSL2_TIMING_SYNC_SEL 8 10 DCIO_GSL2_GLOBAL_UNLOCK_SEL 16 18 mmDC_GPU_TIMER_START_POSITION_V_UPDATE 0 0x20a7 6 0 2 DC_GPU_TIMER_START_POSITION_D1_V_UPDATE 0 2 DC_GPU_TIMER_START_POSITION_D2_V_UPDATE 4 6 DC_GPU_TIMER_START_POSITION_D3_V_UPDATE 8 10 DC_GPU_TIMER_START_POSITION_D4_V_UPDATE 12 14 DC_GPU_TIMER_START_POSITION_D5_V_UPDATE 16 18 DC_GPU_TIMER_START_POSITION_D6_V_UPDATE 20 22 mmDC_GPU_TIMER_START_POSITION_P_FLIP 0 0x20a8 8 0 2 DC_GPU_TIMER_START_POSITION_D1_P_FLIP 0 2 DC_GPU_TIMER_START_POSITION_D2_P_FLIP 4 6 DC_GPU_TIMER_START_POSITION_D3_P_FLIP 8 10 DC_GPU_TIMER_START_POSITION_D4_P_FLIP 12 14 DC_GPU_TIMER_START_POSITION_D5_P_FLIP 16 18 DC_GPU_TIMER_START_POSITION_D6_P_FLIP 20 22 DC_GPU_TIMER_START_POSITION_DCFEV0_P_FLIP 23 25 DC_GPU_TIMER_START_POSITION_DCFEV1_P_FLIP 26 28 mmDC_GPU_TIMER_READ 0 0x20a9 1 0 2 DC_GPU_TIMER_READ 0 31 mmDC_GPU_TIMER_READ_CNTL 0 0x20aa 7 0 2 DC_GPU_TIMER_READ_SELECT 0 5 DC_GPU_TIMER_START_POSITION_D1_VSYNC_NOM 8 10 DC_GPU_TIMER_START_POSITION_D2_VSYNC_NOM 11 13 DC_GPU_TIMER_START_POSITION_D3_VSYNC_NOM 14 16 DC_GPU_TIMER_START_POSITION_D4_VSYNC_NOM 17 19 DC_GPU_TIMER_START_POSITION_D5_VSYNC_NOM 20 22 DC_GPU_TIMER_START_POSITION_D6_VSYNC_NOM 23 25 mmDCIO_CLOCK_CNTL 0 0x20ab 2 0 2 DCIO_TEST_CLK_SEL 0 4 DISPCLK_R_DCIO_GATE_DIS 5 5 mmDCO_DCFE_EXT_VSYNC_CNTL 0 0x20ae 9 0 2 DCO_DCFE0_EXT_VSYNC_MUX 0 2 DCO_DCFE1_EXT_VSYNC_MUX 4 6 DCO_DCFE2_EXT_VSYNC_MUX 8 10 DCO_DCFE3_EXT_VSYNC_MUX 12 14 DCO_DCFE4_EXT_VSYNC_MUX 16 18 DCO_DCFE5_EXT_VSYNC_MUX 20 22 DCO_SWAPLOCKB_EXT_VSYNC_MASK 24 26 DCO_GENERICB_EXT_VSYNC_MASK 28 30 DCO_CRTC_MANUAL_FLOW_CONTROL 31 31 mmDCIO_SOFT_RESET 0 0x20b4 22 0 2 UNIPHYA_SOFT_RESET 0 0 DSYNCA_SOFT_RESET 1 1 UNIPHYB_SOFT_RESET 2 2 DSYNCB_SOFT_RESET 3 3 UNIPHYC_SOFT_RESET 4 4 DSYNCC_SOFT_RESET 5 5 UNIPHYD_SOFT_RESET 6 6 DSYNCD_SOFT_RESET 7 7 UNIPHYE_SOFT_RESET 8 8 DSYNCE_SOFT_RESET 9 9 UNIPHYF_SOFT_RESET 10 10 DSYNCF_SOFT_RESET 11 11 UNIPHYG_SOFT_RESET 12 12 DSYNCG_SOFT_RESET 13 13 DACA_SOFT_RESET 16 16 DCRXPHY_SOFT_RESET 20 20 DPHY_SOFT_RESET 24 24 ZCAL_SOFT_RESET 26 26 UNIPHYLPA_SOFT_RESET 28 28 DSYNCLPA_SOFT_RESET 29 29 UNIPHYLPB_SOFT_RESET 30 30 DSYNCLPB_SOFT_RESET 31 31 mmDCIO_DPHY_SEL 0 0x20b5 4 0 2 DPHY_LANE0_SEL 0 1 DPHY_LANE1_SEL 2 3 DPHY_LANE2_SEL 4 5 DPHY_LANE3_SEL 6 7 mmUNIPHY_IMPCAL_LINKA 0 0x20b6 9 0 2 UNIPHY_IMPCAL_ENABLE_LINKA 0 0 UNIPHY_IMPCAL_CALOUT_LINKA 8 8 UNIPHY_CALOUT_ERROR_LINKA 9 9 UNIPHY_CALOUT_ERROR_LINKA_AK 10 10 UNIPHY_IMPCAL_VALUE_LINKA 16 19 UNIPHY_IMPCAL_STEP_DELAY_LINKA 20 23 UNIPHY_IMPCAL_OVERRIDE_LINKA 24 27 UNIPHY_IMPCAL_OVERRIDE_ENABLE_LINKA 28 28 UNIPHY_IMPCAL_SEL_LINKA 30 30 mmUNIPHY_IMPCAL_LINKB 0 0x20b7 9 0 2 UNIPHY_IMPCAL_ENABLE_LINKB 0 0 UNIPHY_IMPCAL_CALOUT_LINKB 8 8 UNIPHY_CALOUT_ERROR_LINKB 9 9 UNIPHY_CALOUT_ERROR_LINKB_AK 10 10 UNIPHY_IMPCAL_VALUE_LINKB 16 19 UNIPHY_IMPCAL_STEP_DELAY_LINKB 20 23 UNIPHY_IMPCAL_OVERRIDE_LINKB 24 27 UNIPHY_IMPCAL_OVERRIDE_ENABLE_LINKB 28 28 UNIPHY_IMPCAL_SEL_LINKB 30 30 mmUNIPHY_IMPCAL_PERIOD 0 0x20b8 1 0 2 UNIPHY_IMPCAL_PERIOD 0 31 mmAUXP_IMPCAL 0 0x20b9 8 0 2 AUXP_IMPCAL_ENABLE 0 0 AUXP_IMPCAL_CALOUT 8 8 AUXP_CALOUT_ERROR 9 9 AUXP_CALOUT_ERROR_AK 10 10 AUXP_IMPCAL_VALUE 16 19 AUXP_IMPCAL_STEP_DELAY 20 23 AUXP_IMPCAL_OVERRIDE 24 27 AUXP_IMPCAL_OVERRIDE_ENABLE 28 28 mmAUXN_IMPCAL 0 0x20ba 8 0 2 AUXN_IMPCAL_ENABLE 0 0 AUXN_IMPCAL_CALOUT 8 8 AUXN_CALOUT_ERROR 9 9 AUXN_CALOUT_ERROR_AK 10 10 AUXN_IMPCAL_VALUE 16 19 AUXN_IMPCAL_STEP_DELAY 20 23 AUXN_IMPCAL_OVERRIDE 24 27 AUXN_IMPCAL_OVERRIDE_ENABLE 28 28 mmDCIO_IMPCAL_CNTL 0 0x20bb 5 0 2 CALR_CNTL_OVERRIDE 0 3 IMPCAL_SOFT_RESET 5 5 IMPCAL_STATUS 8 9 IMPCAL_ARB_STATE 12 14 AUX_IMPCAL_INTERVAL 15 18 mmUNIPHY_IMPCAL_PSW_AB 0 0x20bc 2 0 2 UNIPHY_IMPCAL_PSW_LINKA 0 14 UNIPHY_IMPCAL_PSW_LINKB 16 30 mmUNIPHY_IMPCAL_LINKC 0 0x20bd 9 0 2 UNIPHY_IMPCAL_ENABLE_LINKC 0 0 UNIPHY_IMPCAL_CALOUT_LINKC 8 8 UNIPHY_CALOUT_ERROR_LINKC 9 9 UNIPHY_CALOUT_ERROR_LINKC_AK 10 10 UNIPHY_IMPCAL_VALUE_LINKC 16 19 UNIPHY_IMPCAL_STEP_DELAY_LINKC 20 23 UNIPHY_IMPCAL_OVERRIDE_LINKC 24 27 UNIPHY_IMPCAL_OVERRIDE_ENABLE_LINKC 28 28 UNIPHY_IMPCAL_SEL_LINKC 30 30 mmUNIPHY_IMPCAL_LINKD 0 0x20be 9 0 2 UNIPHY_IMPCAL_ENABLE_LINKD 0 0 UNIPHY_IMPCAL_CALOUT_LINKD 8 8 UNIPHY_CALOUT_ERROR_LINKD 9 9 UNIPHY_CALOUT_ERROR_LINKD_AK 10 10 UNIPHY_IMPCAL_VALUE_LINKD 16 19 UNIPHY_IMPCAL_STEP_DELAY_LINKD 20 23 UNIPHY_IMPCAL_OVERRIDE_LINKD 24 27 UNIPHY_IMPCAL_OVERRIDE_ENABLE_LINKD 28 28 UNIPHY_IMPCAL_SEL_LINKD 30 30 mmDCIO_IMPCAL_CNTL_CD 0 0x20bf 4 0 2 CALR_CNTL_OVERRIDE 0 3 IMPCAL_SOFT_RESET 5 5 IMPCAL_STATUS 8 9 IMPCAL_ARB_STATE 12 14 mmUNIPHY_IMPCAL_PSW_CD 0 0x20c0 2 0 2 UNIPHY_IMPCAL_PSW_LINKC 0 14 UNIPHY_IMPCAL_PSW_LINKD 16 30 mmUNIPHY_IMPCAL_LINKE 0 0x20c1 9 0 2 UNIPHY_IMPCAL_ENABLE_LINKE 0 0 UNIPHY_IMPCAL_CALOUT_LINKE 8 8 UNIPHY_CALOUT_ERROR_LINKE 9 9 UNIPHY_CALOUT_ERROR_LINKE_AK 10 10 UNIPHY_IMPCAL_VALUE_LINKE 16 19 UNIPHY_IMPCAL_STEP_DELAY_LINKE 20 23 UNIPHY_IMPCAL_OVERRIDE_LINKE 24 27 UNIPHY_IMPCAL_OVERRIDE_ENABLE_LINKE 28 28 UNIPHY_IMPCAL_SEL_LINKE 30 30 mmUNIPHY_IMPCAL_LINKF 0 0x20c2 9 0 2 UNIPHY_IMPCAL_ENABLE_LINKF 0 0 UNIPHY_IMPCAL_CALOUT_LINKF 8 8 UNIPHY_CALOUT_ERROR_LINKF 9 9 UNIPHY_CALOUT_ERROR_LINKF_AK 10 10 UNIPHY_IMPCAL_VALUE_LINKF 16 19 UNIPHY_IMPCAL_STEP_DELAY_LINKF 20 23 UNIPHY_IMPCAL_OVERRIDE_LINKF 24 27 UNIPHY_IMPCAL_OVERRIDE_ENABLE_LINKF 28 28 UNIPHY_IMPCAL_SEL_LINKF 30 30 mmDCIO_IMPCAL_CNTL_EF 0 0x20c3 4 0 2 CALR_CNTL_OVERRIDE 0 3 IMPCAL_SOFT_RESET 5 5 IMPCAL_STATUS 8 9 IMPCAL_ARB_STATE 12 14 mmUNIPHY_IMPCAL_PSW_EF 0 0x20c4 2 0 2 UNIPHY_IMPCAL_PSW_LINKE 0 14 UNIPHY_IMPCAL_PSW_LINKF 16 30 mmUNIPHYLPA_LINK_CNTL 0 0x20c5 9 0 2 UNIPHYLP_PFREQCHG 0 0 UNIPHYLP_PIXVLD_RESET 4 4 UNIPHYLP_MINIMUM_PIXVLD_LOW_DURATION 8 10 UNIPHYLP_CHANNEL0_INVERT 12 12 UNIPHYLP_CHANNEL1_INVERT 13 13 UNIPHYLP_CHANNEL2_INVERT 14 14 UNIPHYLP_CHANNEL3_INVERT 15 15 UNIPHYLP_LANE_STAGGER_DELAY 20 22 UNIPHYLP_LINK_ENABLE_HPD_MASK 24 25 mmUNIPHYLPB_LINK_CNTL 0 0x20c6 9 0 2 UNIPHYLP_PFREQCHG 0 0 UNIPHYLP_PIXVLD_RESET 4 4 UNIPHYLP_MINIMUM_PIXVLD_LOW_DURATION 8 10 UNIPHYLP_CHANNEL0_INVERT 12 12 UNIPHYLP_CHANNEL1_INVERT 13 13 UNIPHYLP_CHANNEL2_INVERT 14 14 UNIPHYLP_CHANNEL3_INVERT 15 15 UNIPHYLP_LANE_STAGGER_DELAY 20 22 UNIPHYLP_LINK_ENABLE_HPD_MASK 24 25 mmUNIPHYLPA_CHANNEL_XBAR_CNTL 0 0x20c7 5 0 2 UNIPHYLP_CHANNEL0_XBAR_SOURCE 0 1 UNIPHYLP_CHANNEL1_XBAR_SOURCE 8 9 UNIPHYLP_CHANNEL2_XBAR_SOURCE 16 17 UNIPHYLP_CHANNEL3_XBAR_SOURCE 24 25 UNIPHYLP_LINK_ENABLE 28 28 mmUNIPHYLPB_CHANNEL_XBAR_CNTL 0 0x20c8 5 0 2 UNIPHYLP_CHANNEL0_XBAR_SOURCE 0 1 UNIPHYLP_CHANNEL1_XBAR_SOURCE 8 9 UNIPHYLP_CHANNEL2_XBAR_SOURCE 16 17 UNIPHYLP_CHANNEL3_XBAR_SOURCE 24 25 UNIPHYLP_LINK_ENABLE 28 28 mmDCIO_DPCS_TX_INTERRUPT 0 0x20c9 27 0 2 DCIO_DPCS_TXA_INT_TYPE 0 0 DCIO_DPCS_TXA_INT_MASK 1 1 DCIO_DPCS_TXA_INT_OCCUR 2 2 DCIO_DPCS_TXB_INT_TYPE 3 3 DCIO_DPCS_TXB_INT_MASK 4 4 DCIO_DPCS_TXB_INT_OCCUR 5 5 DCIO_DPCS_TXC_INT_TYPE 6 6 DCIO_DPCS_TXC_INT_MASK 7 7 DCIO_DPCS_TXC_INT_OCCUR 8 8 DCIO_DPCS_TXD_INT_TYPE 9 9 DCIO_DPCS_TXD_INT_MASK 10 10 DCIO_DPCS_TXD_INT_OCCUR 11 11 DCIO_DPCS_TXE_INT_TYPE 12 12 DCIO_DPCS_TXE_INT_MASK 13 13 DCIO_DPCS_TXE_INT_OCCUR 14 14 DCIO_DPCS_TXF_INT_TYPE 15 15 DCIO_DPCS_TXF_INT_MASK 16 16 DCIO_DPCS_TXF_INT_OCCUR 17 17 DCIO_DPCS_TXG_INT_TYPE 18 18 DCIO_DPCS_TXG_INT_MASK 19 19 DCIO_DPCS_TXG_INT_OCCUR 20 20 DCIO_DPCS_TXLPA_INT_TYPE 24 24 DCIO_DPCS_TXLPA_INT_MASK 25 25 DCIO_DPCS_TXLPA_INT_OCCUR 26 26 DCIO_DPCS_TXLPB_INT_TYPE 27 27 DCIO_DPCS_TXLPB_INT_MASK 28 28 DCIO_DPCS_TXLPB_INT_OCCUR 29 29 mmDCIO_DPCS_RX_INTERRUPT 0 0x20ca 3 0 2 DCIO_DPCS_RXA_INT_TYPE 0 0 DCIO_DPCS_RXA_INT_MASK 1 1 DCIO_DPCS_RXA_INT_OCCUR 2 2 mmDCIO_SEMAPHORE0 0 0x20cb 2 0 2 DCIO_SEMAPHORE0_REQ 0 15 DCIO_SEMAPHORE0_GNT 16 31 mmDCIO_SEMAPHORE1 0 0x20cc 2 0 2 DCIO_SEMAPHORE1_REQ 0 15 DCIO_SEMAPHORE1_GNT 16 31 mmDCIO_SEMAPHORE2 0 0x20cd 2 0 2 DCIO_SEMAPHORE2_REQ 0 15 DCIO_SEMAPHORE2_GNT 16 31 mmDCIO_SEMAPHORE3 0 0x20ce 2 0 2 DCIO_SEMAPHORE3_REQ 0 15 DCIO_SEMAPHORE3_GNT 16 31 mmDCIO_SEMAPHORE4 0 0x20cf 2 0 2 DCIO_SEMAPHORE4_REQ 0 15 DCIO_SEMAPHORE4_GNT 16 31 mmDCIO_SEMAPHORE5 0 0x20d0 2 0 2 DCIO_SEMAPHORE5_REQ 0 15 DCIO_SEMAPHORE5_GNT 16 31 mmDCIO_SEMAPHORE6 0 0x20d1 2 0 2 DCIO_SEMAPHORE6_REQ 0 15 DCIO_SEMAPHORE6_GNT 16 31 mmDCIO_SEMAPHORE7 0 0x20d2 2 0 2 DCIO_SEMAPHORE7_REQ 0 15 DCIO_SEMAPHORE7_GNT 16 31 mmDC_GPIO_GENERIC_MASK 0 0x20de 21 0 2 DC_GPIO_GENERICA_MASK 0 0 DC_GPIO_GENERICA_PD_DIS 1 1 DC_GPIO_GENERICA_RECV 2 3 DC_GPIO_GENERICB_MASK 4 4 DC_GPIO_GENERICB_PD_DIS 5 5 DC_GPIO_GENERICB_RECV 6 7 DC_GPIO_GENERICC_MASK 8 8 DC_GPIO_GENERICC_PD_DIS 9 9 DC_GPIO_GENERICC_RECV 10 11 DC_GPIO_GENERICD_MASK 12 12 DC_GPIO_GENERICD_PD_DIS 13 13 DC_GPIO_GENERICD_RECV 14 15 DC_GPIO_GENERICE_MASK 16 16 DC_GPIO_GENERICE_PD_DIS 17 17 DC_GPIO_GENERICE_RECV 18 19 DC_GPIO_GENERICF_MASK 20 20 DC_GPIO_GENERICF_PD_DIS 21 21 DC_GPIO_GENERICF_RECV 22 23 DC_GPIO_GENERICG_MASK 24 24 DC_GPIO_GENERICG_PD_DIS 25 25 DC_GPIO_GENERICG_RECV 26 27 mmDC_GPIO_GENERIC_A 0 0x20df 7 0 2 DC_GPIO_GENERICA_A 0 0 DC_GPIO_GENERICB_A 8 8 DC_GPIO_GENERICC_A 16 16 DC_GPIO_GENERICD_A 20 20 DC_GPIO_GENERICE_A 21 21 DC_GPIO_GENERICF_A 22 22 DC_GPIO_GENERICG_A 23 23 mmDC_GPIO_GENERIC_EN 0 0x20e0 7 0 2 DC_GPIO_GENERICA_EN 0 0 DC_GPIO_GENERICB_EN 8 8 DC_GPIO_GENERICC_EN 16 16 DC_GPIO_GENERICD_EN 20 20 DC_GPIO_GENERICE_EN 21 21 DC_GPIO_GENERICF_EN 22 22 DC_GPIO_GENERICG_EN 23 23 mmDC_GPIO_GENERIC_Y 0 0x20e1 7 0 2 DC_GPIO_GENERICA_Y 0 0 DC_GPIO_GENERICB_Y 8 8 DC_GPIO_GENERICC_Y 16 16 DC_GPIO_GENERICD_Y 20 20 DC_GPIO_GENERICE_Y 21 21 DC_GPIO_GENERICF_Y 22 22 DC_GPIO_GENERICG_Y 23 23 mmDC_GPIO_DVODATA_MASK 0 0x20e2 4 0 2 DC_GPIO_DVODATA_MASK 0 23 DC_GPIO_DVOCNTL_MASK 24 28 DC_GPIO_DVOCLK_MASK 29 29 DC_GPIO_MVP_DVOCNTL_MASK 30 31 mmDC_GPIO_DVODATA_A 0 0x20e3 4 0 2 DC_GPIO_DVODATA_A 0 23 DC_GPIO_DVOCNTL_A 24 28 DC_GPIO_DVOCLK_A 29 29 DC_GPIO_MVP_DVOCNTL_A 30 31 mmDC_GPIO_DVODATA_EN 0 0x20e4 4 0 2 DC_GPIO_DVODATA_EN 0 23 DC_GPIO_DVOCNTL_EN 24 28 DC_GPIO_DVOCLK_EN 29 29 DC_GPIO_MVP_DVOCNTL_EN 30 31 mmDC_GPIO_DVODATA_Y 0 0x20e5 4 0 2 DC_GPIO_DVODATA_Y 0 23 DC_GPIO_DVOCNTL_Y 24 28 DC_GPIO_DVOCLK_Y 29 29 DC_GPIO_MVP_DVOCNTL_Y 30 31 mmDC_GPIO_DDC1_MASK 0 0x20e6 11 0 2 DC_GPIO_DDC1CLK_MASK 0 0 DC_GPIO_DDC1CLK_PD_EN 4 4 DC_GPIO_DDC1CLK_RECV 6 6 DC_GPIO_DDC1DATA_MASK 8 8 DC_GPIO_DDC1DATA_PD_EN 12 12 DC_GPIO_DDC1DATA_RECV 14 14 AUX_PAD1_MODE 16 16 AUX1_POL 20 20 ALLOW_HW_DDC1_PD_EN 22 22 DC_GPIO_DDC1CLK_STR 24 27 DC_GPIO_DDC1DATA_STR 28 31 mmDC_GPIO_DDC1_A 0 0x20e7 2 0 2 DC_GPIO_DDC1CLK_A 0 0 DC_GPIO_DDC1DATA_A 8 8 mmDC_GPIO_DDC1_EN 0 0x20e8 2 0 2 DC_GPIO_DDC1CLK_EN 0 0 DC_GPIO_DDC1DATA_EN 8 8 mmDC_GPIO_DDC1_Y 0 0x20e9 2 0 2 DC_GPIO_DDC1CLK_Y 0 0 DC_GPIO_DDC1DATA_Y 8 8 mmDC_GPIO_DDC2_MASK 0 0x20ea 11 0 2 DC_GPIO_DDC2CLK_MASK 0 0 DC_GPIO_DDC2CLK_PD_EN 4 4 DC_GPIO_DDC2CLK_RECV 6 6 DC_GPIO_DDC2DATA_MASK 8 8 DC_GPIO_DDC2DATA_PD_EN 12 12 DC_GPIO_DDC2DATA_RECV 14 14 AUX_PAD2_MODE 16 16 AUX2_POL 20 20 ALLOW_HW_DDC2_PD_EN 22 22 DC_GPIO_DDC2CLK_STR 24 27 DC_GPIO_DDC2DATA_STR 28 31 mmDC_GPIO_DDC2_A 0 0x20eb 2 0 2 DC_GPIO_DDC2CLK_A 0 0 DC_GPIO_DDC2DATA_A 8 8 mmDC_GPIO_DDC2_EN 0 0x20ec 2 0 2 DC_GPIO_DDC2CLK_EN 0 0 DC_GPIO_DDC2DATA_EN 8 8 mmDC_GPIO_DDC2_Y 0 0x20ed 2 0 2 DC_GPIO_DDC2CLK_Y 0 0 DC_GPIO_DDC2DATA_Y 8 8 mmDC_GPIO_DDC3_MASK 0 0x20ee 11 0 2 DC_GPIO_DDC3CLK_MASK 0 0 DC_GPIO_DDC3CLK_PD_EN 4 4 DC_GPIO_DDC3CLK_RECV 6 6 DC_GPIO_DDC3DATA_MASK 8 8 DC_GPIO_DDC3DATA_PD_EN 12 12 DC_GPIO_DDC3DATA_RECV 14 14 AUX_PAD3_MODE 16 16 AUX3_POL 20 20 ALLOW_HW_DDC3_PD_EN 22 22 DC_GPIO_DDC3CLK_STR 24 27 DC_GPIO_DDC3DATA_STR 28 31 mmDC_GPIO_DDC3_A 0 0x20ef 2 0 2 DC_GPIO_DDC3CLK_A 0 0 DC_GPIO_DDC3DATA_A 8 8 mmDC_GPIO_DDC3_EN 0 0x20f0 2 0 2 DC_GPIO_DDC3CLK_EN 0 0 DC_GPIO_DDC3DATA_EN 8 8 mmDC_GPIO_DDC3_Y 0 0x20f1 2 0 2 DC_GPIO_DDC3CLK_Y 0 0 DC_GPIO_DDC3DATA_Y 8 8 mmDC_GPIO_DDC4_MASK 0 0x20f2 11 0 2 DC_GPIO_DDC4CLK_MASK 0 0 DC_GPIO_DDC4CLK_PD_EN 4 4 DC_GPIO_DDC4CLK_RECV 6 6 DC_GPIO_DDC4DATA_MASK 8 8 DC_GPIO_DDC4DATA_PD_EN 12 12 DC_GPIO_DDC4DATA_RECV 14 14 AUX_PAD4_MODE 16 16 AUX4_POL 20 20 ALLOW_HW_DDC4_PD_EN 22 22 DC_GPIO_DDC4CLK_STR 24 27 DC_GPIO_DDC4DATA_STR 28 31 mmDC_GPIO_DDC4_A 0 0x20f3 2 0 2 DC_GPIO_DDC4CLK_A 0 0 DC_GPIO_DDC4DATA_A 8 8 mmDC_GPIO_DDC4_EN 0 0x20f4 2 0 2 DC_GPIO_DDC4CLK_EN 0 0 DC_GPIO_DDC4DATA_EN 8 8 mmDC_GPIO_DDC4_Y 0 0x20f5 2 0 2 DC_GPIO_DDC4CLK_Y 0 0 DC_GPIO_DDC4DATA_Y 8 8 mmDC_GPIO_DDC5_MASK 0 0x20f6 11 0 2 DC_GPIO_DDC5CLK_MASK 0 0 DC_GPIO_DDC5CLK_PD_EN 4 4 DC_GPIO_DDC5CLK_RECV 6 6 DC_GPIO_DDC5DATA_MASK 8 8 DC_GPIO_DDC5DATA_PD_EN 12 12 DC_GPIO_DDC5DATA_RECV 14 14 AUX_PAD5_MODE 16 16 AUX5_POL 20 20 ALLOW_HW_DDC5_PD_EN 22 22 DC_GPIO_DDC5CLK_STR 24 27 DC_GPIO_DDC5DATA_STR 28 31 mmDC_GPIO_DDC5_A 0 0x20f7 2 0 2 DC_GPIO_DDC5CLK_A 0 0 DC_GPIO_DDC5DATA_A 8 8 mmDC_GPIO_DDC5_EN 0 0x20f8 2 0 2 DC_GPIO_DDC5CLK_EN 0 0 DC_GPIO_DDC5DATA_EN 8 8 mmDC_GPIO_DDC5_Y 0 0x20f9 2 0 2 DC_GPIO_DDC5CLK_Y 0 0 DC_GPIO_DDC5DATA_Y 8 8 mmDC_GPIO_DDC6_MASK 0 0x20fa 11 0 2 DC_GPIO_DDC6CLK_MASK 0 0 DC_GPIO_DDC6CLK_PD_EN 4 4 DC_GPIO_DDC6CLK_RECV 6 6 DC_GPIO_DDC6DATA_MASK 8 8 DC_GPIO_DDC6DATA_PD_EN 12 12 DC_GPIO_DDC6DATA_RECV 14 14 AUX_PAD6_MODE 16 16 AUX6_POL 20 20 ALLOW_HW_DDC6_PD_EN 22 22 DC_GPIO_DDC6CLK_STR 24 27 DC_GPIO_DDC6DATA_STR 28 31 mmDC_GPIO_DDC6_A 0 0x20fb 2 0 2 DC_GPIO_DDC6CLK_A 0 0 DC_GPIO_DDC6DATA_A 8 8 mmDC_GPIO_DDC6_EN 0 0x20fc 2 0 2 DC_GPIO_DDC6CLK_EN 0 0 DC_GPIO_DDC6DATA_EN 8 8 mmDC_GPIO_DDC6_Y 0 0x20fd 2 0 2 DC_GPIO_DDC6CLK_Y 0 0 DC_GPIO_DDC6DATA_Y 8 8 mmDC_GPIO_DDCVGA_MASK 0 0x20fe 10 0 2 DC_GPIO_DDCVGACLK_MASK 0 0 DC_GPIO_DDCVGACLK_RECV 6 6 DC_GPIO_DDCVGADATA_MASK 8 8 DC_GPIO_DDCVGADATA_PD_EN 12 12 DC_GPIO_DDCVGADATA_RECV 14 14 AUX_PADVGA_MODE 16 16 AUXVGA_POL 20 20 ALLOW_HW_DDCVGA_PD_EN 22 22 DC_GPIO_DDCVGACLK_STR 24 27 DC_GPIO_DDCVGADATA_STR 28 31 mmDC_GPIO_DDCVGA_A 0 0x20ff 2 0 2 DC_GPIO_DDCVGACLK_A 0 0 DC_GPIO_DDCVGADATA_A 8 8 mmDC_GPIO_DDCVGA_EN 0 0x2100 2 0 2 DC_GPIO_DDCVGACLK_EN 0 0 DC_GPIO_DDCVGADATA_EN 8 8 mmDC_GPIO_DDCVGA_Y 0 0x2101 2 0 2 DC_GPIO_DDCVGACLK_Y 0 0 DC_GPIO_DDCVGADATA_Y 8 8 mmDC_GPIO_SYNCA_MASK 0 0x2102 8 0 2 DC_GPIO_HSYNCA_MASK 0 0 DC_GPIO_HSYNCA_PD_DIS 4 4 DC_GPIO_HSYNCA_RECV 6 7 DC_GPIO_VSYNCA_MASK 8 8 DC_GPIO_VSYNCA_PD_DIS 12 12 DC_GPIO_VSYNCA_RECV 14 15 DC_GPIO_HSYNCA_CRTC_HSYNC_MASK 24 26 DC_GPIO_VSYNCA_CRTC_VSYNC_MASK 28 30 mmDC_GPIO_SYNCA_A 0 0x2103 2 0 2 DC_GPIO_HSYNCA_A 0 0 DC_GPIO_VSYNCA_A 8 8 mmDC_GPIO_SYNCA_EN 0 0x2104 2 0 2 DC_GPIO_HSYNCA_EN 0 0 DC_GPIO_VSYNCA_EN 8 8 mmDC_GPIO_SYNCA_Y 0 0x2105 2 0 2 DC_GPIO_HSYNCA_Y 0 0 DC_GPIO_VSYNCA_Y 8 8 mmDC_GPIO_GENLK_MASK 0 0x2106 16 0 2 DC_GPIO_GENLK_CLK_MASK 0 0 DC_GPIO_GENLK_CLK_PD_DIS 1 1 DC_GPIO_GENLK_CLK_PU_EN 3 3 DC_GPIO_GENLK_CLK_RECV 4 5 DC_GPIO_GENLK_VSYNC_MASK 8 8 DC_GPIO_GENLK_VSYNC_PD_DIS 9 9 DC_GPIO_GENLK_VSYNC_PU_EN 11 11 DC_GPIO_GENLK_VSYNC_RECV 12 13 DC_GPIO_SWAPLOCK_A_MASK 16 16 DC_GPIO_SWAPLOCK_A_PD_DIS 17 17 DC_GPIO_SWAPLOCK_A_PU_EN 19 19 DC_GPIO_SWAPLOCK_A_RECV 20 21 DC_GPIO_SWAPLOCK_B_MASK 24 24 DC_GPIO_SWAPLOCK_B_PD_DIS 25 25 DC_GPIO_SWAPLOCK_B_PU_EN 27 27 DC_GPIO_SWAPLOCK_B_RECV 28 29 mmDC_GPIO_GENLK_A 0 0x2107 4 0 2 DC_GPIO_GENLK_CLK_A 0 0 DC_GPIO_GENLK_VSYNC_A 8 8 DC_GPIO_SWAPLOCK_A_A 16 16 DC_GPIO_SWAPLOCK_B_A 24 24 mmDC_GPIO_GENLK_EN 0 0x2108 4 0 2 DC_GPIO_GENLK_CLK_EN 0 0 DC_GPIO_GENLK_VSYNC_EN 8 8 DC_GPIO_SWAPLOCK_A_EN 16 16 DC_GPIO_SWAPLOCK_B_EN 24 24 mmDC_GPIO_GENLK_Y 0 0x2109 4 0 2 DC_GPIO_GENLK_CLK_Y 0 0 DC_GPIO_GENLK_VSYNC_Y 8 8 DC_GPIO_SWAPLOCK_A_Y 16 16 DC_GPIO_SWAPLOCK_B_Y 24 24 mmDC_GPIO_HPD_MASK 0 0x210a 21 0 2 DC_GPIO_HPD1_MASK 0 0 DC_GPIO_RX_HPD_MASK 1 1 DC_GPIO_RX_HPD_PD_DIS 2 2 DC_GPIO_RX_HPD_RX_SEL 3 3 DC_GPIO_HPD1_PD_DIS 4 4 DC_GPIO_HPD1_RECV 6 7 DC_GPIO_HPD2_MASK 8 8 DC_GPIO_HPD2_PD_DIS 9 9 DC_GPIO_HPD2_RECV 10 11 DC_GPIO_HPD3_MASK 16 16 DC_GPIO_HPD3_PD_DIS 17 17 DC_GPIO_HPD3_RECV 18 19 DC_GPIO_HPD4_MASK 20 20 DC_GPIO_HPD4_PD_DIS 21 21 DC_GPIO_HPD4_RECV 22 23 DC_GPIO_HPD5_MASK 24 24 DC_GPIO_HPD5_PD_DIS 25 25 DC_GPIO_HPD5_RECV 26 27 DC_GPIO_HPD6_MASK 28 28 DC_GPIO_HPD6_PD_DIS 29 29 DC_GPIO_HPD6_RECV 30 31 mmDC_GPIO_HPD_A 0 0x210b 6 0 2 DC_GPIO_HPD1_A 0 0 DC_GPIO_HPD2_A 8 8 DC_GPIO_HPD3_A 16 16 DC_GPIO_HPD4_A 24 24 DC_GPIO_HPD5_A 26 26 DC_GPIO_HPD6_A 28 28 mmDC_GPIO_HPD_EN 0 0x210c 23 0 2 DC_GPIO_HPD1_EN 0 0 HPD1_SCHMEN_PI 1 1 HPD1_SLEWNCORE 2 2 RX_HPD_SCHMEN_PI 3 3 RX_HPD_SLEWNCORE 4 4 HPD12_SPARE0 5 5 HPD1_SEL0 6 6 RX_HPD_SEL0 7 7 DC_GPIO_HPD2_EN 8 8 HPD2_SCHMEN_PI 9 9 HPD12_SPARE1 10 10 DC_GPIO_HPD3_EN 16 16 HPD3_SCHMEN_PI 17 17 HPD34_SPARE0 18 18 DC_GPIO_HPD4_EN 20 20 HPD4_SCHMEN_PI 21 21 HPD34_SPARE1 22 22 DC_GPIO_HPD5_EN 24 24 HPD5_SCHMEN_PI 25 25 HPD56_SPARE0 26 26 DC_GPIO_HPD6_EN 28 28 HPD6_SCHMEN_PI 29 29 HPD56_SPARE1 30 30 mmDC_GPIO_HPD_Y 0 0x210d 6 0 2 DC_GPIO_HPD1_Y 0 0 DC_GPIO_HPD2_Y 8 8 DC_GPIO_HPD3_Y 16 16 DC_GPIO_HPD4_Y 24 24 DC_GPIO_HPD5_Y 26 26 DC_GPIO_HPD6_Y 28 28 mmDC_GPIO_PWRSEQ_MASK 0 0x210e 15 0 2 DC_GPIO_BLON_MASK 0 0 DC_GPIO_BLON_PD_DIS 4 4 DC_GPIO_BLON_RECV 6 7 DC_GPIO_DIGON_MASK 8 8 DC_GPIO_DIGON_PD_DIS 12 12 DC_GPIO_DIGON_RECV 14 15 DC_GPIO_ENA_BL_MASK 16 16 DC_GPIO_ENA_BL_PD_DIS 20 20 DC_GPIO_ENA_BL_RECV 22 23 DC_GPIO_VSYNC_IN_MASK 24 24 DC_GPIO_VSYNC_IN_PD_DIS 25 25 DC_GPIO_VSYNC_IN_RECV 26 26 DC_GPIO_HSYNC_IN_MASK 28 28 DC_GPIO_HSYNC_IN_PD_DIS 29 29 DC_GPIO_HSYNC_IN_RECV 30 30 mmDC_GPIO_PWRSEQ_A 0 0x210f 5 0 2 DC_GPIO_BLON_A 0 0 DC_GPIO_DIGON_A 8 8 DC_GPIO_ENA_BL_A 16 16 DC_GPIO_VSYNC_IN_A 24 24 DC_GPIO_HSYNC_IN_A 31 31 mmDC_GPIO_PWRSEQ_EN 0 0x2110 6 0 2 DC_GPIO_BLON_EN 0 0 DC_GPIO_VARY_BL_GENERICA_EN 1 1 DC_GPIO_DIGON_EN 8 8 DC_GPIO_ENA_BL_EN 16 16 DC_GPIO_VSYNC_IN_EN 24 24 DC_GPIO_HSYNC_IN_EN 31 31 mmDC_GPIO_PWRSEQ_Y 0 0x2111 5 0 2 DC_GPIO_BLON_Y 0 0 DC_GPIO_DIGON_Y 8 8 DC_GPIO_ENA_BL_Y 16 16 DC_GPIO_VSYNC_IN 24 24 DC_GPIO_HSYNC_IN 31 31 mmDC_GPIO_PAD_STRENGTH_1 0 0x2112 8 0 2 GENLK_STRENGTH_SN 0 3 GENLK_STRENGTH_SP 4 7 RX_HPD_STRENGTH_SN 8 11 RX_HPD_STRENGTH_SP 12 15 TX_HPD_STRENGTH_SN 16 19 TX_HPD_STRENGTH_SP 20 23 SYNC_STRENGTH_SN 24 27 SYNC_STRENGTH_SP 28 31 mmDC_GPIO_PAD_STRENGTH_2 0 0x2113 7 0 2 STRENGTH_SN 0 3 STRENGTH_SP 4 7 EXT_RESET_DRVSTRENGTH 8 10 REF_27_DRVSTRENGTH 12 14 PWRSEQ_STRENGTH_SN 16 19 PWRSEQ_STRENGTH_SP 20 23 REF_27_SRC_SEL 30 31 mmPHY_AUX_CNTL 0 0x2115 15 0 2 AUXSLAVE_PAD_SLEWN 0 0 AUXSLAVE_PAD_WAKE 1 1 AUXSLAVE_PAD_RXSEL 2 2 AUXSLAVE_PAD_MODE 3 3 DDCSLAVE_DATA_PD_EN 4 4 DDCSLAVE_DATA_EN 5 5 DDCSLAVE_CLK_PD_EN 6 6 DDCSLAVE_CLK_EN 7 7 AUX_PAD_SLEWN 12 12 AUXSLAVE_CLK_PD_EN 13 13 AUX_PAD_WAKE 14 14 AUX_PAD_RXSEL 16 17 AUX_CAL_BIASENTST 20 22 AUX_CAL_RESBIASEN 23 23 AUX_CAL_SPARE 24 25 mmDC_GPIO_I2CPAD_MASK 0 0x2116 6 0 2 DC_GPIO_SCL_MASK 0 0 DC_GPIO_SCL_PD_DIS 1 1 DC_GPIO_SCL_RECV 2 2 DC_GPIO_SDA_MASK 4 4 DC_GPIO_SDA_PD_DIS 5 5 DC_GPIO_SDA_RECV 6 6 mmDC_GPIO_I2CPAD_A 0 0x2117 2 0 2 DC_GPIO_SCL_A 0 0 DC_GPIO_SDA_A 1 1 mmDC_GPIO_I2CPAD_EN 0 0x2118 2 0 2 DC_GPIO_SCL_EN 0 0 DC_GPIO_SDA_EN 1 1 mmDC_GPIO_I2CPAD_Y 0 0x2119 2 0 2 DC_GPIO_SCL_Y 0 0 DC_GPIO_SDA_Y 1 1 mmDC_GPIO_I2CPAD_STRENGTH 0 0x211a 2 0 2 I2C_STRENGTH_SN 0 3 I2C_STRENGTH_SP 4 7 mmDVO_STRENGTH_CONTROL 0 0x211b 9 0 2 DVO_SP 0 3 DVO_SN 4 7 DVOCLK_SP 8 11 DVOCLK_SN 12 15 DVO_DRVSTRENGTH 16 18 DVOCLK_DRVSTRENGTH 20 22 FLDO_VITNE_DRVSTRENGTH 24 26 DVO_LSB_VMODE 28 28 DVO_MSB_VMODE 29 29 mmDVO_VREF_CONTROL 0 0x211c 3 0 2 DVO_VREFPON 0 0 DVO_VREFSEL 1 1 DVO_VREFCAL 4 7 mmDVO_SKEW_ADJUST 0 0x211d 1 0 2 DVO_SKEW_ADJUST 0 31 mmDC_GPIO_I2S_SPDIF_MASK 0 0x2126 10 0 2 DC_GPIO_I2SDATA0_MASK 0 3 DC_GPIO_MCLK0_MASK 4 4 DC_GPIO_BCLK0_MASK 5 5 DC_GPIO_LRCK0_MASK 6 6 DC_GPIO_SPDIF0_MASK 7 7 DC_GPIO_I2SDATA1_MASK 8 8 DC_GPIO_MCLK1_MASK 9 9 DC_GPIO_BCLK1_MASK 10 10 DC_GPIO_LRCK1_MASK 11 11 DC_GPIO_SPDIF1_MASK 12 12 mmDC_GPIO_I2S_SPDIF_A 0 0x2127 10 0 2 DC_GPIO_I2SDATA0_A 0 3 DC_GPIO_MCLK0_A 4 4 DC_GPIO_BCLK0_A 5 5 DC_GPIO_LRCK0_A 6 6 DC_GPIO_SPDIF0_A 7 7 DC_GPIO_I2SDATA1_A 8 8 DC_GPIO_MCLK1_A 9 9 DC_GPIO_BCLK1_A 10 10 DC_GPIO_LRCK1_A 11 11 DC_GPIO_SPDIF1_A 12 12 mmDC_GPIO_I2S_SPDIF_EN 0 0x2128 16 0 2 DC_GPIO_I2SDATA0_EN 0 3 DC_GPIO_MCLK0_EN 4 4 DC_GPIO_BCLK0_EN 5 5 DC_GPIO_LRCK0_EN 6 6 DC_GPIO_SPDIF0_EN 7 7 DC_GPIO_I2SDATA1_EN 8 8 DC_GPIO_MCLK1_EN 9 9 DC_GPIO_BCLK1_EN 10 10 DC_GPIO_LRCK1_EN 11 11 DC_GPIO_SPDIF1_EN 12 12 SPDIF1_APORT 13 13 SPDIF1_PU 14 14 SPDIF1_RXSEL 15 15 SPDIF1_SCHMEN 16 16 SPDIF1_SMODE_EN 17 17 SPDIF1_IMODE 18 18 mmDC_GPIO_I2S_SPDIF_Y 0 0x2129 10 0 2 DC_GPIO_I2SDATA0_Y 0 3 DC_GPIO_MCLK0_Y 4 4 DC_GPIO_BCLK0_Y 5 5 DC_GPIO_LRCK0_Y 6 6 DC_GPIO_SPDIF0_Y 7 7 DC_GPIO_I2SDATA1_Y 8 8 DC_GPIO_MCLK1_Y 9 9 DC_GPIO_BCLK1_Y 10 10 DC_GPIO_LRCK1_Y 11 11 DC_GPIO_SPDIF1_Y 12 12 mmDC_GPIO_I2S_SPDIF_STRENGTH 0 0x212a 6 0 2 I2S0_DRVSTRENGTH 0 2 SPDIF0_DRVSTRENGTH_SN 8 10 SPDIF0_DRVSTRENGTH_SP 11 13 I2S1_DRVSTRENGTH 16 18 SPDIF1_DRVSTRENGTH_SN 24 26 SPDIF1_DRVSTRENGTH_SP 27 29 mmDC_GPIO_TX12_EN 0 0x212b 19 0 2 DC_GPIO_BLON_TX12_EN 0 0 DC_GPIO_DIGON_TX12_EN 1 1 DC_GPIO_ENA_BL_TX12_EN 2 2 DC_GPIO_GENERICA_TX12_EN 3 3 DC_GPIO_GENERICB_TX12_EN 4 4 DC_GPIO_GENERICC_TX12_EN 5 5 DC_GPIO_GENERICD_TX12_EN 6 6 DC_GPIO_GENERICE_TX12_EN 7 7 DC_GPIO_GENERICF_TX12_EN 8 8 DC_GPIO_GENERICG_TX12_EN 9 9 DC_GPIO_HSYNC_TX12_EN 10 10 DC_GPIO_VSYNC_TX12_EN 11 11 DC_GPIO_GENLK_CLK_TX12_EN 12 12 DC_GPIO_GENLK_VSYNC_TX12_EN 13 13 DC_GPIO_SWAPLOCKA_TX12_EN 14 14 DC_GPIO_SWAPLOCKB_TX12_EN 15 15 DC_GPIO_SCL_TX12_EN 16 16 DC_GPIO_SDA_TX12_EN 17 17 DC_GPIO_HPD1_TX12_EN 18 18 mmDC_GPIO_AUX_CTRL_0 0 0x212c 24 0 2 DC_GPIO_AUX1_FALLSLEWSEL 0 1 DC_GPIO_AUX2_FALLSLEWSEL 2 3 DC_GPIO_AUX3_FALLSLEWSEL 4 5 DC_GPIO_AUX4_FALLSLEWSEL 6 7 DC_GPIO_AUX5_FALLSLEWSEL 8 9 DC_GPIO_AUX6_FALLSLEWSEL 10 11 DC_GPIO_DDCVGA_FALLSLEWSEL 12 13 DC_GPIO_GENI2C_FALLSLEWSEL 14 15 DC_GPIO_AUX1_SPIKERCEN 16 16 DC_GPIO_AUX2_SPIKERCEN 17 17 DC_GPIO_AUX3_SPIKERCEN 18 18 DC_GPIO_AUX4_SPIKERCEN 19 19 DC_GPIO_AUX5_SPIKERCEN 20 20 DC_GPIO_AUX6_SPIKERCEN 21 21 DC_GPIO_DDCVGA_SPIKERCEN 22 22 DC_GPIO_GENI2C_SPIKERCEN 23 23 DC_GPIO_AUX1_SPIKERCSEL 24 24 DC_GPIO_AUX2_SPIKERCSEL 25 25 DC_GPIO_AUX3_SPIKERCSEL 26 26 DC_GPIO_AUX4_SPIKERCSEL 27 27 DC_GPIO_AUX5_SPIKERCSEL 28 28 DC_GPIO_AUX6_SPIKERCSEL 29 29 DC_GPIO_DDCVGA_SPIKERCSEL 30 30 DC_GPIO_GENI2C_SPIKERCSEL 31 31 mmDC_GPIO_AUX_CTRL_1 0 0x212d 21 0 2 DC_GPIO_AUX_CSEL_0P9 0 0 DC_GPIO_AUX_CSEL_1P1 1 1 DC_GPIO_AUX_RSEL_0P9 2 2 DC_GPIO_AUX_RSEL_1P1 3 3 DC_GPIO_I2C_CSEL_0P9 4 4 DC_GPIO_I2C_CSEL_1P1 5 5 DC_GPIO_I2C_RSEL_0P9 6 6 DC_GPIO_I2C_RSEL_1P1 7 7 DC_GPIO_AUX_BIASCRTEN 8 8 DC_GPIO_I2C_BIASCRTEN 9 9 DC_GPIO_AUX_RESBIASEN 10 10 DC_GPIO_I2C_RESBIASEN 11 11 DC_GPIO_AUX_COMPSEL 12 12 DC_GPIO_I2C_COMPSEL 13 13 DC_GPIO_DDCVGA_SPARE 14 15 DC_GPIO_GENI2C_SPARE 16 17 DC_GPIO_DDCVGA_SLEWN 18 18 DC_GPIO_GENI2C_SLEWN 19 19 DC_GPIO_DDCVGA_RXSEL 20 21 DC_GPIO_GENI2C_RXSEL 22 23 DC_GPIO_GENI2C_PDEN 24 24 mmDC_GPIO_AUX_CTRL_2 0 0x212e 17 0 2 DC_GPIO_HPD12_FALLSLEWSEL 0 1 DC_GPIO_HPD34_FALLSLEWSEL 2 3 DC_GPIO_HPD56_FALLSLEWSEL 4 5 DC_GPIO_HPD12_SPIKERCEN 8 8 DC_GPIO_HPD34_SPIKERCEN 9 9 DC_GPIO_HPD56_SPIKERCEN 10 10 DC_GPIO_HPD12_SPIKERCSEL 12 12 DC_GPIO_HPD34_SPIKERCSEL 13 13 DC_GPIO_HPD56_SPIKERCSEL 14 14 DC_GPIO_HPD_CSEL_0P9 16 16 DC_GPIO_HPD_CSEL_1P1 17 17 DC_GPIO_HPD_RSEL_0P9 18 18 DC_GPIO_HPD_RSEL_1P1 19 19 DC_GPIO_HPD_BIASCRTEN 20 20 DC_GPIO_HPD12_SLEWN 24 24 DC_GPIO_HPD34_SLEWN 25 25 DC_GPIO_HPD56_SLEWN 26 26 mmDC_GPIO_RXEN 0 0x212f 22 0 2 DC_GPIO_GENERICA_RXEN 0 0 DC_GPIO_GENERICB_RXEN 1 1 DC_GPIO_GENERICC_RXEN 2 2 DC_GPIO_GENERICD_RXEN 3 3 DC_GPIO_GENERICE_RXEN 4 4 DC_GPIO_GENERICF_RXEN 5 5 DC_GPIO_GENERICG_RXEN 6 6 DC_GPIO_HSYNCA_RXEN 8 8 DC_GPIO_VSYNCA_RXEN 9 9 DC_GPIO_GENLK_CLK_RXEN 10 10 DC_GPIO_GENLK_VSYNC_RXEN 11 11 DC_GPIO_SWAPLOCK_A_RXEN 12 12 DC_GPIO_SWAPLOCK_B_RXEN 13 13 DC_GPIO_HPD1_RXEN 14 14 DC_GPIO_HPD2_RXEN 15 15 DC_GPIO_HPD3_RXEN 16 16 DC_GPIO_HPD4_RXEN 17 17 DC_GPIO_HPD5_RXEN 18 18 DC_GPIO_HPD6_RXEN 19 19 DC_GPIO_BLON_RXEN 20 20 DC_GPIO_DIGON_RXEN 21 21 DC_GPIO_ENA_BL_RXEN 22 22 mmDC_GPIO_AUX_CTRL_3 0 0x2130 18 0 2 AUX1_NEN_RTERM 0 0 AUX2_NEN_RTERM 1 1 AUX3_NEN_RTERM 2 2 AUX4_NEN_RTERM 3 3 AUX5_NEN_RTERM 4 4 AUX6_NEN_RTERM 5 5 AUX1_DP_DN_SWAP 8 8 AUX2_DP_DN_SWAP 9 9 AUX3_DP_DN_SWAP 10 10 AUX4_DP_DN_SWAP 11 11 AUX5_DP_DN_SWAP 12 12 AUX6_DP_DN_SWAP 13 13 AUX1_HYS_TUNE 16 17 AUX2_HYS_TUNE 18 19 AUX3_HYS_TUNE 20 21 AUX4_HYS_TUNE 22 23 AUX5_HYS_TUNE 24 25 AUX6_HYS_TUNE 26 27 mmDC_GPIO_AUX_CTRL_4 0 0x2131 6 0 2 AUX1_AUX_CTRL 0 3 AUX2_AUX_CTRL 4 7 AUX3_AUX_CTRL 8 11 AUX4_AUX_CTRL 12 15 AUX5_AUX_CTRL 16 19 AUX6_AUX_CTRL 20 23 mmDC_GPIO_AUX_CTRL_5 0 0x2132 24 0 2 AUX1_VOD_TUNE 0 1 AUX2_VOD_TUNE 2 3 AUX3_VOD_TUNE 4 5 AUX4_VOD_TUNE 6 7 AUX5_VOD_TUNE 8 9 AUX6_VOD_TUNE 10 11 DDC_PAD1_I2CMODE 12 12 DDC_PAD2_I2CMODE 13 13 DDC_PAD3_I2CMODE 14 14 DDC_PAD4_I2CMODE 15 15 DDC_PAD5_I2CMODE 16 16 DDC_PAD6_I2CMODE 17 17 DDC1_I2C_VPH_1V2_EN 18 18 DDC2_I2C_VPH_1V2_EN 19 19 DDC3_I2C_VPH_1V2_EN 20 20 DDC4_I2C_VPH_1V2_EN 21 21 DDC5_I2C_VPH_1V2_EN 22 22 DDC6_I2C_VPH_1V2_EN 23 23 DDC1_PAD_I2C_CTRL 24 24 DDC2_PAD_I2C_CTRL 25 25 DDC3_PAD_I2C_CTRL 26 26 DDC4_PAD_I2C_CTRL 27 27 DDC5_PAD_I2C_CTRL 28 28 DDC6_PAD_I2C_CTRL 29 29 mmAUXI2C_PAD_ALL_PWR_OK 0 0x2133 6 0 2 AUXI2C_PHY1_ALL_PWR_OK 0 0 AUXI2C_PHY2_ALL_PWR_OK 1 1 AUXI2C_PHY3_ALL_PWR_OK 2 2 AUXI2C_PHY4_ALL_PWR_OK 3 3 AUXI2C_PHY5_ALL_PWR_OK 4 4 AUXI2C_PHY6_ALL_PWR_OK 5 5 mmDC_GPIO_PULLUPEN 0 0x2134 13 0 2 DC_GPIO_GENERICA_PU_EN 0 0 DC_GPIO_GENERICB_PU_EN 1 1 DC_GPIO_GENERICC_PU_EN 2 2 DC_GPIO_GENERICD_PU_EN 3 3 DC_GPIO_GENERICE_PU_EN 4 4 DC_GPIO_GENERICF_PU_EN 5 5 DC_GPIO_GENERICG_PU_EN 6 6 DC_GPIO_HSYNCA_PU_EN 8 8 DC_GPIO_VSYNCA_PU_EN 9 9 DC_GPIO_HPD1_PU_EN 14 14 DC_GPIO_BLON_PU_EN 20 20 DC_GPIO_DIGON_PU_EN 21 21 DC_GPIO_ENA_BL_PU_EN 22 22 mmDC_GPIO_AUX_CTRL_6 0 0x2135 6 0 2 AUX1_PAD_RXSEL 0 1 AUX2_PAD_RXSEL 2 3 AUX3_PAD_RXSEL 4 5 AUX4_PAD_RXSEL 6 7 AUX5_PAD_RXSEL 8 9 AUX6_PAD_RXSEL 10 11 mmBPHYC_DAC_MACRO_CNTL 0 0x2136 5 0 2 BPHYC_DAC_WHITE_LEVEL 0 1 BPHYC_DAC_WHITE_FINE_CONTROL 8 13 BPHYC_DAC_BANDGAP_ADJUSTMENT 16 21 BPHYC_DAC_ANALOG_MONITOR 24 27 BPHYC_DAC_COREMON 28 28 mmDAC_MACRO_CNTL_RESERVED0 0 0x2136 1 0 2 DAC_MACRO_CNTL_RESERVED 0 31 mmBPHYC_DAC_AUTO_CALIB_CONTROL 0 0x2137 6 0 2 BPHYC_DAC_CAL_INITB 0 0 BPHYC_DAC_CAL_EN 1 1 BPHYC_DAC_CAL_DACADJ_EN 2 2 BPHYC_DAC_CAL_WAIT_ADJUST 4 13 BPHYC_DAC_CAL_MASK 20 22 BPHYC_DAC_CAL_COMPLETE 28 28 mmDAC_MACRO_CNTL_RESERVED1 0 0x2137 1 0 2 DAC_MACRO_CNTL_RESERVED 0 31 mmDAC_MACRO_CNTL_RESERVED2 0 0x2138 1 0 2 DAC_MACRO_CNTL_RESERVED 0 31 mmDAC_MACRO_CNTL_RESERVED3 0 0x2139 1 0 2 DAC_MACRO_CNTL_RESERVED 0 31 mmDISP_DSI_DUAL_CTRL 0 0x277e 1 0 2 DUAL_PIPE_MODE 0 0 mmDPHY_MACRO_CNTL_RESERVED0 0 0x283e 1 0 2 DPHY_MACRO_CNTL_RESERVED 0 31 mmDPHY_MACRO_CNTL_RESERVED1 0 0x283f 1 0 2 DPHY_MACRO_CNTL_RESERVED 0 31 mmDPHY_MACRO_CNTL_RESERVED2 0 0x2840 1 0 2 DPHY_MACRO_CNTL_RESERVED 0 31 mmDPHY_MACRO_CNTL_RESERVED3 0 0x2841 1 0 2 DPHY_MACRO_CNTL_RESERVED 0 31 mmDPHY_MACRO_CNTL_RESERVED4 0 0x2842 1 0 2 DPHY_MACRO_CNTL_RESERVED 0 31 mmDPHY_MACRO_CNTL_RESERVED5 0 0x2843 1 0 2 DPHY_MACRO_CNTL_RESERVED 0 31 mmDPHY_MACRO_CNTL_RESERVED6 0 0x2844 1 0 2 DPHY_MACRO_CNTL_RESERVED 0 31 mmDPHY_MACRO_CNTL_RESERVED7 0 0x2845 1 0 2 DPHY_MACRO_CNTL_RESERVED 0 31 mmDPHY_MACRO_CNTL_RESERVED8 0 0x2846 1 0 2 DPHY_MACRO_CNTL_RESERVED 0 31 mmDPHY_MACRO_CNTL_RESERVED9 0 0x2847 1 0 2 DPHY_MACRO_CNTL_RESERVED 0 31 mmDPHY_MACRO_CNTL_RESERVED10 0 0x2848 1 0 2 DPHY_MACRO_CNTL_RESERVED 0 31 mmDPHY_MACRO_CNTL_RESERVED11 0 0x2849 1 0 2 DPHY_MACRO_CNTL_RESERVED 0 31 mmDPHY_MACRO_CNTL_RESERVED12 0 0x284a 1 0 2 DPHY_MACRO_CNTL_RESERVED 0 31 mmDPHY_MACRO_CNTL_RESERVED13 0 0x284b 1 0 2 DPHY_MACRO_CNTL_RESERVED 0 31 mmDPHY_MACRO_CNTL_RESERVED14 0 0x284c 1 0 2 DPHY_MACRO_CNTL_RESERVED 0 31 mmDPHY_MACRO_CNTL_RESERVED15 0 0x284d 1 0 2 DPHY_MACRO_CNTL_RESERVED 0 31 mmDPHY_MACRO_CNTL_RESERVED16 0 0x284e 1 0 2 DPHY_MACRO_CNTL_RESERVED 0 31 mmDPHY_MACRO_CNTL_RESERVED17 0 0x284f 1 0 2 DPHY_MACRO_CNTL_RESERVED 0 31 mmDPHY_MACRO_CNTL_RESERVED18 0 0x2850 1 0 2 DPHY_MACRO_CNTL_RESERVED 0 31 mmDPHY_MACRO_CNTL_RESERVED19 0 0x2851 1 0 2 DPHY_MACRO_CNTL_RESERVED 0 31 mmDPHY_MACRO_CNTL_RESERVED20 0 0x2852 1 0 2 DPHY_MACRO_CNTL_RESERVED 0 31 mmDPHY_MACRO_CNTL_RESERVED21 0 0x2853 1 0 2 DPHY_MACRO_CNTL_RESERVED 0 31 mmDPHY_MACRO_CNTL_RESERVED22 0 0x2854 1 0 2 DPHY_MACRO_CNTL_RESERVED 0 31 mmDPHY_MACRO_CNTL_RESERVED23 0 0x2855 1 0 2 DPHY_MACRO_CNTL_RESERVED 0 31 mmDPHY_MACRO_CNTL_RESERVED24 0 0x2856 1 0 2 DPHY_MACRO_CNTL_RESERVED 0 31 mmDPHY_MACRO_CNTL_RESERVED25 0 0x2857 1 0 2 DPHY_MACRO_CNTL_RESERVED 0 31 mmDPHY_MACRO_CNTL_RESERVED26 0 0x2858 1 0 2 DPHY_MACRO_CNTL_RESERVED 0 31 mmDPHY_MACRO_CNTL_RESERVED27 0 0x2859 1 0 2 DPHY_MACRO_CNTL_RESERVED 0 31 mmDPHY_MACRO_CNTL_RESERVED28 0 0x285a 1 0 2 DPHY_MACRO_CNTL_RESERVED 0 31 mmDPHY_MACRO_CNTL_RESERVED29 0 0x285b 1 0 2 DPHY_MACRO_CNTL_RESERVED 0 31 mmDPHY_MACRO_CNTL_RESERVED30 0 0x285c 1 0 2 DPHY_MACRO_CNTL_RESERVED 0 31 mmDPHY_MACRO_CNTL_RESERVED31 0 0x285d 1 0 2 DPHY_MACRO_CNTL_RESERVED 0 31 mmDPHY_MACRO_CNTL_RESERVED32 0 0x285e 1 0 2 DPHY_MACRO_CNTL_RESERVED 0 31 mmDPHY_MACRO_CNTL_RESERVED33 0 0x285f 1 0 2 DPHY_MACRO_CNTL_RESERVED 0 31 mmDPHY_MACRO_CNTL_RESERVED34 0 0x2860 1 0 2 DPHY_MACRO_CNTL_RESERVED 0 31 mmDPHY_MACRO_CNTL_RESERVED35 0 0x2861 1 0 2 DPHY_MACRO_CNTL_RESERVED 0 31 mmDPHY_MACRO_CNTL_RESERVED36 0 0x2862 1 0 2 DPHY_MACRO_CNTL_RESERVED 0 31 mmDPHY_MACRO_CNTL_RESERVED37 0 0x2863 1 0 2 DPHY_MACRO_CNTL_RESERVED 0 31 mmDPHY_MACRO_CNTL_RESERVED38 0 0x2864 1 0 2 DPHY_MACRO_CNTL_RESERVED 0 31 mmDPHY_MACRO_CNTL_RESERVED39 0 0x2865 1 0 2 DPHY_MACRO_CNTL_RESERVED 0 31 mmDPHY_MACRO_CNTL_RESERVED40 0 0x2866 1 0 2 DPHY_MACRO_CNTL_RESERVED 0 31 mmDPHY_MACRO_CNTL_RESERVED41 0 0x2867 1 0 2 DPHY_MACRO_CNTL_RESERVED 0 31 mmDPHY_MACRO_CNTL_RESERVED42 0 0x2868 1 0 2 DPHY_MACRO_CNTL_RESERVED 0 31 mmDPHY_MACRO_CNTL_RESERVED43 0 0x2869 1 0 2 DPHY_MACRO_CNTL_RESERVED 0 31 mmDPHY_MACRO_CNTL_RESERVED44 0 0x286a 1 0 2 DPHY_MACRO_CNTL_RESERVED 0 31 mmDPHY_MACRO_CNTL_RESERVED45 0 0x286b 1 0 2 DPHY_MACRO_CNTL_RESERVED 0 31 mmDPHY_MACRO_CNTL_RESERVED46 0 0x286c 1 0 2 DPHY_MACRO_CNTL_RESERVED 0 31 mmDPHY_MACRO_CNTL_RESERVED47 0 0x286d 1 0 2 DPHY_MACRO_CNTL_RESERVED 0 31 mmDPHY_MACRO_CNTL_RESERVED48 0 0x286e 1 0 2 DPHY_MACRO_CNTL_RESERVED 0 31 mmDPHY_MACRO_CNTL_RESERVED49 0 0x286f 1 0 2 DPHY_MACRO_CNTL_RESERVED 0 31 mmDPHY_MACRO_CNTL_RESERVED50 0 0x2870 1 0 2 DPHY_MACRO_CNTL_RESERVED 0 31 mmDPHY_MACRO_CNTL_RESERVED51 0 0x2871 1 0 2 DPHY_MACRO_CNTL_RESERVED 0 31 mmDPHY_MACRO_CNTL_RESERVED52 0 0x2872 1 0 2 DPHY_MACRO_CNTL_RESERVED 0 31 mmDPHY_MACRO_CNTL_RESERVED53 0 0x2873 1 0 2 DPHY_MACRO_CNTL_RESERVED 0 31 mmDPHY_MACRO_CNTL_RESERVED54 0 0x2874 1 0 2 DPHY_MACRO_CNTL_RESERVED 0 31 mmDPHY_MACRO_CNTL_RESERVED55 0 0x2875 1 0 2 DPHY_MACRO_CNTL_RESERVED 0 31 mmDPHY_MACRO_CNTL_RESERVED56 0 0x2876 1 0 2 DPHY_MACRO_CNTL_RESERVED 0 31 mmDPHY_MACRO_CNTL_RESERVED57 0 0x2877 1 0 2 DPHY_MACRO_CNTL_RESERVED 0 31 mmDPHY_MACRO_CNTL_RESERVED58 0 0x2878 1 0 2 DPHY_MACRO_CNTL_RESERVED 0 31 mmDPHY_MACRO_CNTL_RESERVED59 0 0x2879 1 0 2 DPHY_MACRO_CNTL_RESERVED 0 31 mmDPHY_MACRO_CNTL_RESERVED60 0 0x287a 1 0 2 DPHY_MACRO_CNTL_RESERVED 0 31 mmDPHY_MACRO_CNTL_RESERVED61 0 0x287b 1 0 2 DPHY_MACRO_CNTL_RESERVED 0 31 mmDPHY_MACRO_CNTL_RESERVED62 0 0x287c 1 0 2 DPHY_MACRO_CNTL_RESERVED 0 31 mmDPHY_MACRO_CNTL_RESERVED63 0 0x287d 1 0 2 DPHY_MACRO_CNTL_RESERVED 0 31 mmDPRX_AUX_REFERENCE_PULSE_DIV 0 0x2a7e 4 0 2 DPRX_AUX_1_MICROSECOND_DIV 0 9 DPRX_AUX_1_MICROSECOND_SOURCE_SEL 15 15 DPRX_AUX_100_MICROSECOND_DIV 16 23 DPRX_AUX_1_MILLISECOND_DIV 24 29 mmDPRX_AUX_CONTROL 0 0x2a7f 7 0 2 DPRX_AUX_EN 0 0 DPRX_AUX_REQUEST_TIMEOUT_LEN 8 16 DPRX_AUX_IMPCAL_REQ_EN 24 24 DPRX_AUX_TEST_MODE 28 28 DPRX_AUX_DEGLITCH_EN 29 29 DPRX_AUX_SPARE_0 30 30 DPRX_AUX_SPARE_1 31 31 mmDPRX_AUX_HPD_CONTROL1 0 0x2a80 4 0 2 DPRX_AUX_HPD_IRQ_PULSE_WIDTH 0 3 DPRX_AUX_HPD_IRQ_GAP 8 13 DPRX_AUX_HPD_A 16 16 DPRX_AUX_HPD_EN 17 17 mmDPRX_AUX_HPD_CONTROL2 0 0x2a81 2 0 2 DPRX_AUX_HPD_IRQ_TRIGGER 0 0 DPRX_AUX_NEW_HPD_IRQ_READY 1 1 mmDPRX_AUX_RX_STATUS 0 0x2a82 14 0 2 DPRX_AUX_RX_STATUS_CLEAR 0 0 DPRX_AUX_RX_DONE 7 7 DPRX_AUX_RX_OVERFLOW 8 8 DPRX_AUX_RX_TIMEOUT 9 9 DPRX_AUX_RX_PARTIAL_BYTE 10 10 DPRX_AUX_RX_MIN_COUNT_VIOL 12 12 DPRX_AUX_RX_INVALID_STOP 14 14 DPRX_AUX_RX_SYNC_INVALID_L 17 17 DPRX_AUX_RX_SYNC_INVALID_H 18 18 DPRX_AUX_RX_INVALID_START 19 19 DPRX_AUX_RX_RECV_NO_DET 20 20 DPRX_AUX_RX_RECV_INVALID_H 22 22 DPRX_AUX_RX_RECV_INVALID_L 23 23 DPRX_AUX_RX_BYTE_COUNT 24 28 mmDPRX_AUX_RX_ERROR_MASK 0 0x2a83 11 0 2 DPRX_AUX_RX_OVERFLOW_MASK 8 8 DPRX_AUX_RX_TIMEOUT_MASK 9 9 DPRX_AUX_RX_PARTIAL_BYTE_MASK 10 10 DPRX_AUX_RX_MIN_COUNT_VIOL_MASK 12 12 DPRX_AUX_RX_INVALID_STOP_MASK 14 14 DPRX_AUX_RX_SYNC_INVALID_L_MASK 17 17 DPRX_AUX_RX_SYNC_INVALID_H_MASK 18 18 DPRX_AUX_RX_INVALID_START_MASK 19 19 DPRX_AUX_RX_RECV_NO_DET_MASK 20 20 DPRX_AUX_RX_RECV_INVALID_H_MASK 22 22 DPRX_AUX_RX_RECV_INVALID_L_MASK 23 23 mmDPRX_AUX_DPHY_TX_REF_CONTROL 0 0x2a84 3 0 2 DPRX_AUX_TX_REF_SEL 0 0 DPRX_AUX_TX_RATE 4 5 DPRX_AUX_TX_REF_DIV 16 24 mmDPRX_AUX_DPHY_TX_CONTROL 0 0x2a85 2 0 2 DPRX_AUX_TX_PRECHARGE_LEN 0 2 DPRX_AUX_TX_PRECHARGE_SYMBOLS 8 13 mmDPRX_AUX_DPHY_RX_CONTROL0 0 0x2a86 9 0 2 DPRX_AUX_RX_START_WINDOW 4 6 DPRX_AUX_RX_RECEIVE_WINDOW 8 10 DPRX_AUX_RX_HALF_SYM_DETECT_LEN 12 13 DPRX_AUX_RX_TRANSITION_FILTER_EN 16 16 DPRX_AUX_RX_ALLOW_BELOW_THRESHOLD_PHASE_DETECT 17 17 DPRX_AUX_RX_ALLOW_BELOW_THRESHOLD_START 18 18 DPRX_AUX_RX_ALLOW_BELOW_THRESHOLD_STOP 19 19 DPRX_AUX_RX_PHASE_DETECT_LEN 20 21 DPRX_AUX_RX_DETECTION_THRESHOLD 28 30 mmDPRX_AUX_DPHY_RX_CONTROL1 0 0x2a87 3 0 2 DPRX_AUX_RX_PRECHARGE_SKIP 0 7 DPRX_AUX_RX_TIMEOUT_LEN 8 16 DPRX_AUX_RX_TIMEOUT_COUNTER_START 24 28 mmDPRX_AUX_DPHY_TX_STATUS 0 0x2a88 3 0 2 DPRX_AUX_TX_ACTIVE 0 0 DPRX_AUX_TX_STATE 4 7 DPRX_AUX_TX_HALF_SYM_PERIOD 16 24 mmDPRX_AUX_DPHY_RX_STATUS 0 0x2a89 4 0 2 DPRX_AUX_RX_STATE 0 2 DPRX_AUX_RX_SYNC_VALID_COUNT 8 12 DPRX_AUX_RX_HALF_SYM_PERIOD_FRACT 16 20 DPRX_AUX_RX_HALF_SYM_PERIOD 21 29 mmDPRX_AUX_DMCU_HW_INT_STATUS 0 0x2a8a 18 0 2 DPRX_AUX_DMCU_AUX_INT_STATUS 0 0 DPRX_AUX_DMCU_I2C_INT_STATUS 1 1 DPRX_AUX_DMCU_MSG1_TIMEOUT_INT_STATUS 2 2 DPRX_AUX_DMCU_MSG2_TIMEOUT_INT_STATUS 3 3 DPRX_AUX_DMCU_MSG3_TIMEOUT_INT_STATUS 4 4 DPRX_AUX_DMCU_MSG4_TIMEOUT_INT_STATUS 5 5 DPRX_AUX_DMCU_AUX_INT_MASK 8 8 DPRX_AUX_DMCU_I2C_INT_MASK 9 9 DPRX_AUX_DMCU_MSG1_TIMEOUT_INT_MASK 10 10 DPRX_AUX_DMCU_MSG2_TIMEOUT_INT_MASK 11 11 DPRX_AUX_DMCU_MSG3_TIMEOUT_INT_MASK 12 12 DPRX_AUX_DMCU_MSG4_TIMEOUT_INT_MASK 13 13 DPRX_AUX_DMCU_AUX_EVENT_OCCURRED 16 16 DPRX_AUX_DMCU_I2C_EVENT_OCCURRED 17 17 DPRX_AUX_DMCU_MSG1_TIMEOUT_EVENT_OCCURRED 18 18 DPRX_AUX_DMCU_MSG2_TIMEOUT_EVENT_OCCURRED 19 19 DPRX_AUX_DMCU_MSG3_TIMEOUT_EVENT_OCCURRED 20 20 DPRX_AUX_DMCU_MSG4_TIMEOUT_EVENT_OCCURRED 21 21 mmDPRX_AUX_DMCU_HW_INT_ACK 0 0x2a8b 6 0 2 DPRX_AUX_DMCU_AUX_INT_ACK 0 0 DPRX_AUX_DMCU_I2C_INT_ACK 1 1 DPRX_AUX_DMCU_MSG1_TIMEOUT_INT_ACK 2 2 DPRX_AUX_DMCU_MSG2_TIMEOUT_INT_ACK 3 3 DPRX_AUX_DMCU_MSG3_TIMEOUT_INT_ACK 4 4 DPRX_AUX_DMCU_MSG4_TIMEOUT_INT_ACK 5 5 mmDPRX_AUX_CPU_TO_DMCU_INTERRUPT1 0 0x2a8c 1 0 2 DPRX_AUX_CPU_TO_DMCU_INT_TRIGGER 0 0 mmDPRX_AUX_CPU_TO_DMCU_INTERRUPT2 0 0x2a8d 3 0 2 DPRX_AUX_CPU_TO_DMCU_INT_MASK 0 0 DPRX_AUX_CPU_TO_DMCU_INT_ACK 8 8 DPRX_AUX_CPU_TO_DMCU_INT_STATUS 16 16 mmDPRX_AUX_DMCU_TO_CPU_INTERRUPT1 0 0x2a8e 1 0 2 DPRX_AUX_DMCU_TO_CPU_INT_TRIGGER 0 0 mmDPRX_AUX_DMCU_TO_CPU_INTERRUPT2 0 0x2a8f 4 0 2 DPRX_AUX_DMCU_TO_CPU_INT_MASK 0 0 DPRX_AUX_DMCU_TO_CPU_INT_TYPE 1 1 DPRX_AUX_DMCU_TO_CPU_INT_ACK 8 8 DPRX_AUX_DMCU_TO_CPU_INT_OCCURRED 16 16 mmDPRX_AUX_AUX_BUF_INDEX 0 0x2a90 1 0 2 DPRX_AUX_AUX_BUF_INDEX 0 6 mmDPRX_AUX_AUX_BUF_DATA 0 0x2a91 1 0 2 DPRX_AUX_AUX_BUF_DATA 0 31 mmDPRX_AUX_EDID_INDEX 0 0x2a92 2 0 2 DPRX_AUX_EDID_INDEX 0 9 DPRX_AUX_EDID_MODE 16 16 mmDPRX_AUX_EDID_DATA 0 0x2a93 1 0 2 DPRX_AUX_EDID_DATA 0 31 mmDPRX_AUX_DPCD_INDEX1 0 0x2a94 2 0 2 DPRX_AUX_DPCD_INDEX1 0 10 DPRX_AUX_DPCD_MODE1 16 16 mmDPRX_AUX_DPCD_DATA1 0 0x2a95 1 0 2 DPRX_AUX_DPCD_DATA1 0 31 mmDPRX_AUX_DPCD_INDEX2 0 0x2a96 2 0 2 DPRX_AUX_DPCD_INDEX2 0 10 DPRX_AUX_DPCD_MODE2 16 16 mmDPRX_AUX_DPCD_DATA2 0 0x2a97 1 0 2 DPRX_AUX_DPCD_DATA2 0 31 mmDPRX_AUX_MSG_INDEX1 0 0x2a98 2 0 2 DPRX_AUX_MSG_INDEX1 0 9 DPRX_AUX_MSG_MODE1 16 16 mmDPRX_AUX_MSG_DATA1 0 0x2a99 1 0 2 DPRX_AUX_MSG_DATA1 0 31 mmDPRX_AUX_MSG_INDEX2 0 0x2a9a 2 0 2 DPRX_AUX_MSG_INDEX2 0 9 DPRX_AUX_MSG_MODE2 16 16 mmDPRX_AUX_MSG_DATA2 0 0x2a9b 1 0 2 DPRX_AUX_MSG_DATA2 0 31 mmDPRX_AUX_KSV_INDEX1 0 0x2a9c 2 0 2 DPRX_AUX_KSV_INDEX1 0 9 DPRX_AUX_KSV_MODE1 16 16 mmDPRX_AUX_KSV_DATA1 0 0x2a9d 1 0 2 DPRX_AUX_KSV_DATA1 0 31 mmDPRX_AUX_KSV_INDEX2 0 0x2a9e 2 0 2 DPRX_AUX_KSV_INDEX2 0 9 DPRX_AUX_KSV_MODE2 16 16 mmDPRX_AUX_KSV_DATA2 0 0x2a9f 1 0 2 DPRX_AUX_KSV_DATA2 0 31 mmDPRX_AUX_MSG_TIMEOUT_CONTROL 0 0x2aa0 1 0 2 DPRX_AUX_MSG_TIMEOUT_LEN 0 7 mmDPRX_AUX_MSG_BUF_CONTROL1 0 0x2aa1 2 0 2 DPRX_AUX_MSG_REP_WRITE_REQ1 0 0 DPRX_AUX_MSG_REP_WRITE_GNT1 1 1 mmDPRX_AUX_MSG_BUF_CONTROL2 0 0x2aa2 2 0 2 DPRX_AUX_MSG_REP_WRITE_REQ2 0 0 DPRX_AUX_MSG_REP_WRITE_GNT2 1 1 mmDPRX_AUX_SCRATCH1 0 0x2aa3 1 0 2 DPRX_AUX_SCRATCH1 0 31 mmDPRX_AUX_SCRATCH2 0 0x2aa4 1 0 2 DPRX_AUX_SCRATCH2 0 31 mmDPRX_AUX_MSG1_PENDING 0 0x2aa5 1 0 2 DPRX_AUX_MSG1_PENDING 0 0 mmDPRX_AUX_MSG2_PENDING 0 0x2aa6 1 0 2 DPRX_AUX_MSG2_PENDING 0 0 mmDPRX_AUX_MSG3_PENDING 0 0x2aa7 1 0 2 DPRX_AUX_MSG3_PENDING 0 0 mmDPRX_AUX_MSG4_PENDING 0 0x2aa8 1 0 2 DPRX_AUX_MSG4_PENDING 0 0 mmDPRX_DPHY_DPCD_LANE_COUNT_SET 0 0x2afe 1 0 2 LANE_COUNT_SET 0 4 mmDPRX_DPHY_DPCD_TRAINING_PATTERN_SET 0 0x2aff 1 0 2 TRAINING_PATTERN_SET 0 1 mmDPRX_DPHY_DPCD_MSTM_CTRL 0 0x2b00 1 0 2 MST_EN 0 0 mmDPRX_DPHY_DPCD_LINK_QUAL_LANE0_SET 0 0x2b01 1 0 2 LANE0_LINK_QUAL_PATTERN_SET 0 2 mmDPRX_DPHY_DPCD_LINK_QUAL_LANE0_STATUS 0 0x2b02 2 0 2 LANE0_LINK_QUAL_PATTERN_DETECT 0 2 LANE0_HBR2_COMPL_EYE_PATTERN_DETECT 3 4 mmDPRX_DPHY_DPCD_LINK_QUAL_LANE1_SET 0 0x2b03 1 0 2 LANE1_LINK_QUAL_PATTERN_SET 0 2 mmDPRX_DPHY_DPCD_LINK_QUAL_LANE1_STATUS 0 0x2b04 2 0 2 LANE1_LINK_QUAL_PATTERN_DETECT 0 2 LANE1_HBR2_COMPL_EYE_PATTERN_DETECT 3 4 mmDPRX_DPHY_DPCD_LINK_QUAL_LANE2_SET 0 0x2b05 1 0 2 LANE2_LINK_QUAL_PATTERN_SET 0 2 mmDPRX_DPHY_DPCD_LINK_QUAL_LANE2_STATUS 0 0x2b06 2 0 2 LANE2_LINK_QUAL_PATTERN_DETECT 0 2 LANE2_HBR2_COMPL_EYE_PATTERN_DETECT 3 4 mmDPRX_DPHY_DPCD_LINK_QUAL_LANE3_SET 0 0x2b07 1 0 2 LANE3_LINK_QUAL_PATTERN_SET 0 2 mmDPRX_DPHY_DPCD_LINK_QUAL_LANE3_STATUS 0 0x2b08 2 0 2 LANE3_LINK_QUAL_PATTERN_DETECT 0 2 LANE3_HBR2_COMPL_EYE_PATTERN_DETECT 3 4 mmDPRX_DPHY_READY 0 0x2b09 8 0 2 CP_READY 0 0 ACT_READY 1 1 SDOUT_READY 2 2 ACT_READY_CLR 3 3 MVOTE_DATA_ERROR 4 4 MVOTE_DATA_ERROR_CLR 5 5 MVOTE_KCODE_ERROR 6 6 MVOTE_KCODE_ERROR_CLR 7 7 mmDPRX_DPHY_COMMA_STATUS 0 0x2b0b 8 0 2 LANE0_COMMA_LOCKED 0 0 LANE1_COMMA_LOCKED 1 1 LANE2_COMMA_LOCKED 2 2 LANE3_COMMA_LOCKED 3 3 LANE0_SR_LOCKED 4 4 LANE1_SR_LOCKED 5 5 LANE2_SR_LOCKED 6 6 LANE3_SR_LOCKED 7 7 mmDPRX_DPHY_LANE_ALIGN_ERROR_STATUS_UPDATED 0 0x2b0c 1 0 2 LANE0_INTERLANE_ALIGN_ERROR_COUNT 0 3 mmDPRX_DPHY_LANE_ALIGN_STATUS_UPDATED 0 0x2b0d 5 0 2 INTERLANE_ALIGN_DONE 0 0 INTERLANE_ALIGN_CHECK_DONE 1 1 INTERLANE_ALIGN_FIFO_LEVEL 2 17 INTERLANE_ALIGN_STATE 25 26 INTERLANE_ALIGN_WAIT_COUNT 27 31 mmDPRX_DPHY_ERROR_THRESH_A_LANE0 0 0x2b0f 3 0 2 LANE0_SYMBOL_ERROR_COUNT_THRESH 0 7 LANE0_DISPARITY_ERROR_COUNT_THRESH 8 15 LANE0_TEST_PATTERN_ERROR_THRESH 24 31 mmDPRX_DPHY_ERROR_COUNT_A_LANE0 0 0x2b11 4 0 2 LANE0_SYMBOL_ERROR_COUNT 0 14 LANE0_SYMBOL_ERROR_COUNT_VALID 15 15 LANE0_DISPARITY_ERROR_COUNT 16 30 LANE0_DISPARITY_ERROR_COUNT_VALID 31 31 mmDPRX_DPHY_ERROR_COUNT_B_LANE0 0 0x2b12 2 0 2 LANE0_TEST_PATTERN_ERROR_COUNT 16 30 LANE0_TEST_PATTERN_ERROR_COUNT_VALID 31 31 mmDPRX_DPHY_ERROR_COUNT_C_LANE0 0 0x2b13 3 0 2 LANE0_SYMBOL_ERROR_COUNT_CLR 27 27 LANE0_DISPARITY_ERROR_COUNT_CLR 28 28 LANE0_TEST_PATTERN_ERROR_COUNT_CLR 30 30 mmDPRX_DPHY_ERROR_THRESH_A_LANE1 0 0x2b14 3 0 2 LANE1_SYMBOL_ERROR_COUNT_THRESH 0 7 LANE1_DISPARITY_ERROR_COUNT_THRESH 8 15 LANE1_TEST_PATTERN_ERROR_THRESH 24 31 mmDPRX_DPHY_ERROR_COUNT_A_LANE1 0 0x2b16 4 0 2 LANE1_SYMBOL_ERROR_COUNT 0 14 LANE1_SYMBOL_ERROR_COUNT_VALID 15 15 LANE1_DISPARITY_ERROR_COUNT 16 30 LANE1_DISPARITY_ERROR_COUNT_VALID 31 31 mmDPRX_DPHY_ERROR_COUNT_B_LANE1 0 0x2b17 2 0 2 LANE1_TEST_PATTERN_ERROR_COUNT 16 30 LANE1_TEST_PATTERN_ERROR_COUNT_VALID 31 31 mmDPRX_DPHY_ERROR_COUNT_C_LANE1 0 0x2b18 3 0 2 LANE1_SYMBOL_ERROR_COUNT_CLR 27 27 LANE1_DISPARITY_ERROR_COUNT_CLR 28 28 LANE1_TEST_PATTERN_ERROR_COUNT_CLR 30 30 mmDPRX_DPHY_ERROR_THRESH_A_LANE2 0 0x2b19 3 0 2 LANE2_SYMBOL_ERROR_COUNT_THRESH 0 7 LANE2_DISPARITY_ERROR_COUNT_THRESH 8 15 LANE2_TEST_PATTERN_ERROR_THRESH 24 31 mmDPRX_DPHY_ERROR_COUNT_A_LANE2 0 0x2b1b 4 0 2 LANE2_SYMBOL_ERROR_COUNT 0 14 LANE2_SYMBOL_ERROR_COUNT_VALID 15 15 LANE2_DISPARITY_ERROR_COUNT 16 30 LANE2_DISPARITY_ERROR_COUNT_VALID 31 31 mmDPRX_DPHY_ERROR_COUNT_B_LANE2 0 0x2b1c 2 0 2 LANE2_TEST_PATTERN_ERROR_COUNT 16 30 LANE2_TEST_PATTERN_ERROR_COUNT_VALID 31 31 mmDPRX_DPHY_ERROR_COUNT_C_LANE2 0 0x2b1d 3 0 2 LANE2_SYMBOL_ERROR_COUNT_CLR 27 27 LANE2_DISPARITY_ERROR_COUNT_CLR 28 28 LANE2_TEST_PATTERN_ERROR_COUNT_CLR 30 30 mmDPRX_DPHY_ERROR_THRESH_A_LANE3 0 0x2b1e 3 0 2 LANE3_SYMBOL_ERROR_COUNT_THRESH 0 7 LANE3_DISPARITY_ERROR_COUNT_THRESH 8 15 LANE3_TEST_PATTERN_ERROR_THRESH 24 31 mmDPRX_DPHY_ERROR_COUNT_A_LANE3 0 0x2b20 4 0 2 LANE3_SYMBOL_ERROR_COUNT 0 14 LANE3_SYMBOL_ERROR_COUNT_VALID 15 15 LANE3_DISPARITY_ERROR_COUNT 16 30 LANE3_DISPARITY_ERROR_COUNT_VALID 31 31 mmDPRX_DPHY_ERROR_COUNT_B_LANE3 0 0x2b21 2 0 2 LANE3_TEST_PATTERN_ERROR_COUNT 16 30 LANE3_TEST_PATTERN_ERROR_COUNT_VALID 31 31 mmDPRX_DPHY_ERROR_COUNT_C_LANE3 0 0x2b22 3 0 2 LANE3_SYMBOL_ERROR_COUNT_CLR 27 27 LANE3_DISPARITY_ERROR_COUNT_CLR 28 28 LANE3_TEST_PATTERN_ERROR_COUNT_CLR 30 30 mmDPRX_DPHY_BS_ERROR_THRESH_GLOBAL 0 0x2b24 2 0 2 BS_INTERVAL_ERROR_THRESH 0 4 BS_INTERVAL_UNCERTAINTY_THRESH 8 15 mmDPRX_DPHY_SR_ERROR_COUNT_A 0 0x2b25 3 0 2 SR_ERROR_COUNT 0 7 SR_INTERVAL_COUNT 8 24 SR_ERROR_COUNT_CLR 25 25 mmDPRX_DPHY_BS_ERROR_COUNT_A 0 0x2b27 3 0 2 BS_ERROR_COUNT 0 7 BS_INTERVAL_COUNT 8 24 BS_ERROR_COUNT_CLR 25 25 mmDPRX_DPHY_BS_ERROR_COUNT_B 0 0x2b28 11 0 2 BS_INTERVAL_UNCERTAINTY_COUNT 0 7 BS_INTERVAL_ERROR_COUNT 8 12 BS_INTERVAL_ERROR_COUNT_CLR 17 17 LANE0_CPBS_ERROR_CLR 20 20 LANE1_CPBS_ERROR_CLR 21 21 LANE2_CPBS_ERROR_CLR 22 22 LANE3_CPBS_ERROR_CLR 23 23 LANE0_CPBS_ERROR 24 25 LANE1_CPBS_ERROR 26 27 LANE2_CPBS_ERROR 28 29 LANE3_CPBS_ERROR 30 31 mmDPRX_DPHY_LANESETUP0 0 0x2b2d 1 0 2 LANE_MAP 0 7 mmDPRX_DPHY_LANESETUP1 0 0x2b2e 1 0 2 LANEINV 0 3 mmDPRX_DPHY_LFSRADV 0 0x2b31 5 0 2 TWOSYMCORRECTMIDDLE_ENABLE 1 1 TWOSYMCORRECTLR_ENABLE 2 2 SEVENSYMBOLWINDOW_ENABLE 3 3 SUPPRESS_SINGLE_BS_BF_CP_SR_EN 4 4 IGNORE_ERROR_FLAG_FOR_BS_INTERVAL 5 5 mmDPRX_DPHY_SEVENSYMBOLWINDOW_ERROR_DETECT 0 0x2b32 5 0 2 SEVENSYMBOLWINDOW_ERROR_DETECT_LANE0 0 6 SEVENSYMBOLWINDOW_ERROR_DETECT_LANE1 8 14 SEVENSYMBOLWINDOW_ERROR_DETECT_LANE2 16 22 SEVENSYMBOLWINDOW_ERROR_DETECT_LANE3 24 30 SEVENSYMBOLWINDOW_ERROR_DETECT_CLEAR 31 31 mmDPRX_DPHY_SET_ENABLE 0 0x2b33 3 0 2 SET_ENABLE 0 1 CLOCK_ENABLE 8 8 CLOCK_ON 12 12 mmDPRX_DPHY_ECF_LSB 0 0x2b34 1 0 2 ECF_LSB 0 31 mmDPRX_DPHY_ECF_MSB 0 0x2b35 1 0 2 ECF_MSB 0 31 mmDPRX_DPHY_ENHANCED_FRAME_EN 0 0x2b36 1 0 2 ENHANCED_FRAME_EN 0 0 mmDPRX_DPHY_MTP_HEADER_COUNT_FORCE 0 0x2b3c 4 0 2 MTP_HEADER_COUNT_FORCE 0 9 USE_TRAILING_BF 17 17 LINK_LINE_COUNT_FORCE 18 19 BS_COUNT_FORCE 20 29 mmDPRX_DPHY_DYNAMIC_DESKEW_DATA 0 0x2b3d 4 0 2 MATCH0_DATA 0 7 MATCH1_DATA 8 15 MATCH2_DATA 16 23 MATCH3_DATA 24 31 mmDPRX_DPHY_DYNAMIC_DESKEW_CONTROL 0 0x2b3e 15 0 2 DESKEW_WAIT_COUNT 0 4 MATCH0_KCODE 5 5 MATCH0_DATA_DONTCARE 6 6 MATCH0_KCODE_DONTCARE 7 7 MATCH1_KCODE 8 8 MATCH1_DATA_DONTCARE 9 9 MATCH1_KCODE_DONTCARE 10 10 MATCH2_KCODE 11 11 MATCH2_DATA_DONTCARE 12 12 MATCH2_KCODE_DONTCARE 13 13 MATCH3_KCODE 14 14 MATCH3_DATA_DONTCARE 15 15 MATCH3_KCODE_DONTCARE 16 16 INTERLANE_ALIGN_CHECK_COUNT 17 22 FIFO_LEN_IGNORE_DURING_DS_RST 31 31 mmDPRX_DPHY_BYPASS 0 0x2b3f 4 0 2 LANE0_SDESKEW_BYPASS 4 4 LANE1_SDESKEW_BYPASS 5 5 LANE2_SDESKEW_BYPASS 6 6 LANE3_SDESKEW_BYPASS 7 7 mmDPRX_DPHY_INT_RESET 0 0x2b40 28 0 2 LANE0_ALIGN_RESET 0 0 LANE1_ALIGN_RESET 1 1 LANE2_ALIGN_RESET 2 2 LANE3_ALIGN_RESET 3 3 LANE0_SDESKEW_RESET 4 4 LANE1_SDESKEW_RESET 5 5 LANE2_SDESKEW_RESET 6 6 LANE3_SDESKEW_RESET 7 7 LANE0_8B10BDEC_RESET 8 8 LANE1_8B10BDEC_RESET 9 9 LANE2_8B10BDEC_RESET 10 10 LANE3_8B10BDEC_RESET 11 11 LANE0_LCOUNT_RESET 16 16 LANE1_LCOUNT_RESET 17 17 LANE2_LCOUNT_RESET 18 18 LANE3_LCOUNT_RESET 19 19 LANE0_DDESKEW_RESET 20 20 LANE1_DDESKEW_RESET 21 21 LANE2_DDESKEW_RESET 22 22 LANE3_DDESKEW_RESET 23 23 INV_RESET 24 24 LANEREV_RESET 25 25 ENABLE_RESET 26 26 CTL_RESET 27 27 CTL_DS_RESET 28 28 CTL_TRN_RESET 29 29 HEADERPARSE_RESET 30 30 SDOUT_RESET 31 31 mmDPRX_DPHY_BS_INTERVAL_ERROR_THRESH_EXCEEDED_STATUS 0 0x2b41 3 0 2 BS_INTERVAL_ERROR_THRESH_EXCEEDED_FLAG 0 0 BS_INTERVAL_ERROR_THRESH_EXCEEDED_ACK 4 4 BS_INTERVAL_ERROR_THRESH_EXCEEDED_MASK 8 8 mmDPRX_DPHY_SYMBOL_ERROR_THRESH_EXCEEDED_STATUS 0 0x2b43 3 0 2 SYMBOL_ERROR_THRESH_EXCEEDED_FLAG 0 0 SYMBOL_ERROR_THRESH_EXCEEDED_ACK 4 4 SYMBOL_ERROR_THRESH_EXCEEDED_MASK 8 8 mmDPRX_DPHY_DISPARITY_ERROR_THRESH_EXCEEDED_STATUS 0 0x2b44 3 0 2 DISPARITY_ERROR_THRESH_EXCEEDED_FLAG 0 0 DISPARITY_ERROR_THRESH_EXCEEDED_ACK 4 4 DISPARITY_ERROR_THRESH_EXCEEDED_MASK 8 8 mmDPRX_DPHY_TEST_PATTERN_ERROR_THRESH_EXCEEDED_STATUS 0 0x2b46 3 0 2 TEST_PATTERN_ERROR_THRESH_EXCEEDED_FLAG 0 0 TEST_PATTERN_ERROR_THRESH_EXCEEDED_ACK 4 4 TEST_PATTERN_ERROR_THRESH_EXCEEDED_MASK 8 8 mmDPRX_DPHY_DETECT_SR_LOCK_STATUS 0 0x2b48 4 0 2 DETECT_SR_LOCK_STATUS_FLAG 0 0 DETECT_SR_LOCK_STATUS_ACK 4 4 DETECT_SR_LOCK_STATUS_MASK 8 8 DETECT_SR_LOCK_STATUS_TYPE 12 12 mmDPRX_DPHY_LOSS_OF_ALIGN_STATUS 0 0x2b49 3 0 2 LOSS_OF_ALIGN_FLAG 0 0 LOSS_OF_ALIGN_ACK 4 4 LOSS_OF_ALIGN_MASK 8 8 mmDPRX_DPHY_LOSS_OF_DESKEW_STATUS 0 0x2b4a 3 0 2 LOSS_OF_DESKEW_FLAG 0 0 LOSS_OF_DESKEW_ACK 4 4 LOSS_OF_DESKEW_MASK 8 8 mmDPRX_DPHY_EXCESSIVE_ERROR_STATUS 0 0x2b4b 3 0 2 EXCESSIVE_ERROR_FLAG 0 0 EXCESSIVE_ERROR_ACK 4 4 EXCESSIVE_ERROR_MASK 8 8 mmDPRX_DPHY_DESKEW_FIFO_OVERFLOW_STATUS 0 0x2b4c 3 0 2 DESKEW_FIFO_OVERFLOW_FLAG 0 0 DESKEW_FIFO_OVERFLOW_ACK 4 4 DESKEW_FIFO_OVERFLOW_MASK 8 8 mmDPRX_DPHY_SPARE 0 0x2b4d 1 0 2 DPHY_SPARE 0 31 mmDCRX_GATE_DISABLE_CNTL 0 0x2b6e 8 0 2 DCRX_DISPCLK_CWB0_SD0_GATE_DISABLE 0 0 DCRX_DISPCLK_CWB1_SD1_GATE_DISABLE 1 1 DCRX_DISPCLK_AUX_GATE_DISABLE 2 2 DCRX_DISPCLK_R_GATE_DISABLE 3 3 DCRX_SYMCLK_RX_SD0_GATE_DISABLE 8 8 DCRX_SYMCLK_RX_SD1_GATE_DISABLE 9 9 DCRX_SYMCLK_RX_DPHY_GATE_DISABLE 10 10 DCRX_SYMCLK_RX_P_GATE_DISABLE 12 12 mmDCRX_SOFT_RESET 0 0x2b6f 10 0 2 DCRX_DISPCLK_CWB0_SD0_SOFT_RESET 0 0 DCRX_DISPCLK_CWB1_SD1_SOFT_RESET 1 1 DCRX_DISPCLK_AUX_SOFT_RESET 2 2 DCRX_DISPCLK_P_SOFT_RESET 4 4 DCRX_SYMCLK_RX_SD0_SOFT_RESET 8 8 DCRX_SYMCLK_RX_SD1_SOFT_RESET 9 9 DCRX_SYMCLK_RX_DPHY_SOFT_RESET 10 10 DCRX_SYMCLK_RX_P_SOFT_RESET 12 12 DCRX_REFCLK_SOFT_RESET 16 16 DCRX_SCLK_SOFT_RESET 17 17 mmDCRX_LIGHT_SLEEP_CNTL 0 0x2b70 2 0 2 DCRX_AUX_LIGHT_SLEEP_DIS 0 0 DCRX_DPRX_LIGHT_SLEEP_DIS 8 8 mmDCRX_DISPCLK_GATE_CNTL 0 0x2b73 2 0 2 DCRX_DISPCLK_TURN_ON_DELAY 0 3 DCRX_DISPCLK_TURN_OFF_DELAY 4 11 mmDCRX_CLK_CNTL 0 0x2b74 1 0 2 DCRX_SYMCLK_RX_P_ENABLE 2 2 mmDCRX_TEST_CLK_CNTL 0 0x2b75 4 0 2 DCRX_TEST_CLK_GENERICA_SEL 0 4 DCRX_TEST_CLK_GENERICA_INV 7 7 DCRX_TEST_CLK_GENERICB_SEL 8 12 DCRX_TEST_CLK_GENERICB_INV 15 15 mmDCRX_PHY_MACRO_CNTL_RESERVED0 0 0x2c06 1 0 2 DCRX_PHY_MACRO_CNTL_RESERVED 0 31 mmDCRX_PHY_MACRO_CNTL_RESERVED1 0 0x2c07 1 0 2 DCRX_PHY_MACRO_CNTL_RESERVED 0 31 mmDCRX_PHY_MACRO_CNTL_RESERVED2 0 0x2c08 1 0 2 DCRX_PHY_MACRO_CNTL_RESERVED 0 31 mmDCRX_PHY_MACRO_CNTL_RESERVED3 0 0x2c09 1 0 2 DCRX_PHY_MACRO_CNTL_RESERVED 0 31 mmDCRX_PHY_MACRO_CNTL_RESERVED4 0 0x2c0a 1 0 2 DCRX_PHY_MACRO_CNTL_RESERVED 0 31 mmDCRX_PHY_MACRO_CNTL_RESERVED5 0 0x2c0b 1 0 2 DCRX_PHY_MACRO_CNTL_RESERVED 0 31 mmDCRX_PHY_MACRO_CNTL_RESERVED6 0 0x2c0c 1 0 2 DCRX_PHY_MACRO_CNTL_RESERVED 0 31 mmDCRX_PHY_MACRO_CNTL_RESERVED7 0 0x2c0d 1 0 2 DCRX_PHY_MACRO_CNTL_RESERVED 0 31 mmDCRX_PHY_MACRO_CNTL_RESERVED8 0 0x2c0e 1 0 2 DCRX_PHY_MACRO_CNTL_RESERVED 0 31 mmDCRX_PHY_MACRO_CNTL_RESERVED9 0 0x2c0f 1 0 2 DCRX_PHY_MACRO_CNTL_RESERVED 0 31 mmDCRX_PHY_MACRO_CNTL_RESERVED10 0 0x2c10 1 0 2 DCRX_PHY_MACRO_CNTL_RESERVED 0 31 mmDCRX_PHY_MACRO_CNTL_RESERVED11 0 0x2c11 1 0 2 DCRX_PHY_MACRO_CNTL_RESERVED 0 31 mmDCRX_PHY_MACRO_CNTL_RESERVED12 0 0x2c12 1 0 2 DCRX_PHY_MACRO_CNTL_RESERVED 0 31 mmDCRX_PHY_MACRO_CNTL_RESERVED13 0 0x2c13 1 0 2 DCRX_PHY_MACRO_CNTL_RESERVED 0 31 mmDCRX_PHY_MACRO_CNTL_RESERVED14 0 0x2c14 1 0 2 DCRX_PHY_MACRO_CNTL_RESERVED 0 31 mmDCRX_PHY_MACRO_CNTL_RESERVED15 0 0x2c15 1 0 2 DCRX_PHY_MACRO_CNTL_RESERVED 0 31 mmDCRX_PHY_MACRO_CNTL_RESERVED16 0 0x2c16 1 0 2 DCRX_PHY_MACRO_CNTL_RESERVED 0 31 mmDCRX_PHY_MACRO_CNTL_RESERVED17 0 0x2c17 1 0 2 DCRX_PHY_MACRO_CNTL_RESERVED 0 31 mmDCRX_PHY_MACRO_CNTL_RESERVED18 0 0x2c18 1 0 2 DCRX_PHY_MACRO_CNTL_RESERVED 0 31 mmDCRX_PHY_MACRO_CNTL_RESERVED19 0 0x2c19 1 0 2 DCRX_PHY_MACRO_CNTL_RESERVED 0 31 mmDCRX_PHY_MACRO_CNTL_RESERVED20 0 0x2c1a 1 0 2 DCRX_PHY_MACRO_CNTL_RESERVED 0 31 mmDCRX_PHY_MACRO_CNTL_RESERVED21 0 0x2c1b 1 0 2 DCRX_PHY_MACRO_CNTL_RESERVED 0 31 mmDCRX_PHY_MACRO_CNTL_RESERVED22 0 0x2c1c 1 0 2 DCRX_PHY_MACRO_CNTL_RESERVED 0 31 mmDCRX_PHY_MACRO_CNTL_RESERVED23 0 0x2c1d 1 0 2 DCRX_PHY_MACRO_CNTL_RESERVED 0 31 mmDCRX_PHY_MACRO_CNTL_RESERVED24 0 0x2c1e 1 0 2 DCRX_PHY_MACRO_CNTL_RESERVED 0 31 mmDCRX_PHY_MACRO_CNTL_RESERVED25 0 0x2c1f 1 0 2 DCRX_PHY_MACRO_CNTL_RESERVED 0 31 mmDCRX_PHY_MACRO_CNTL_RESERVED26 0 0x2c20 1 0 2 DCRX_PHY_MACRO_CNTL_RESERVED 0 31 mmDCRX_PHY_MACRO_CNTL_RESERVED27 0 0x2c21 1 0 2 DCRX_PHY_MACRO_CNTL_RESERVED 0 31 mmDCRX_PHY_MACRO_CNTL_RESERVED28 0 0x2c22 1 0 2 DCRX_PHY_MACRO_CNTL_RESERVED 0 31 mmDCRX_PHY_MACRO_CNTL_RESERVED29 0 0x2c23 1 0 2 DCRX_PHY_MACRO_CNTL_RESERVED 0 31 mmDCRX_PHY_MACRO_CNTL_RESERVED30 0 0x2c24 1 0 2 DCRX_PHY_MACRO_CNTL_RESERVED 0 31 mmDCRX_PHY_MACRO_CNTL_RESERVED31 0 0x2c25 1 0 2 DCRX_PHY_MACRO_CNTL_RESERVED 0 31 mmDCRX_PHY_MACRO_CNTL_RESERVED32 0 0x2c26 1 0 2 DCRX_PHY_MACRO_CNTL_RESERVED 0 31 mmDCRX_PHY_MACRO_CNTL_RESERVED33 0 0x2c27 1 0 2 DCRX_PHY_MACRO_CNTL_RESERVED 0 31 mmDCRX_PHY_MACRO_CNTL_RESERVED34 0 0x2c28 1 0 2 DCRX_PHY_MACRO_CNTL_RESERVED 0 31 mmDCRX_PHY_MACRO_CNTL_RESERVED35 0 0x2c29 1 0 2 DCRX_PHY_MACRO_CNTL_RESERVED 0 31 mmDCRX_PHY_MACRO_CNTL_RESERVED36 0 0x2c2a 1 0 2 DCRX_PHY_MACRO_CNTL_RESERVED 0 31 mmDCRX_PHY_MACRO_CNTL_RESERVED37 0 0x2c2b 1 0 2 DCRX_PHY_MACRO_CNTL_RESERVED 0 31 mmDCRX_PHY_MACRO_CNTL_RESERVED38 0 0x2c2c 1 0 2 DCRX_PHY_MACRO_CNTL_RESERVED 0 31 mmDCRX_PHY_MACRO_CNTL_RESERVED39 0 0x2c2d 1 0 2 DCRX_PHY_MACRO_CNTL_RESERVED 0 31 mmDCRX_PHY_MACRO_CNTL_RESERVED40 0 0x2c2e 1 0 2 DCRX_PHY_MACRO_CNTL_RESERVED 0 31 mmDCRX_PHY_MACRO_CNTL_RESERVED41 0 0x2c2f 1 0 2 DCRX_PHY_MACRO_CNTL_RESERVED 0 31 mmDCRX_PHY_MACRO_CNTL_RESERVED42 0 0x2c30 1 0 2 DCRX_PHY_MACRO_CNTL_RESERVED 0 31 mmDCRX_PHY_MACRO_CNTL_RESERVED43 0 0x2c31 1 0 2 DCRX_PHY_MACRO_CNTL_RESERVED 0 31 mmDCRX_PHY_MACRO_CNTL_RESERVED44 0 0x2c32 1 0 2 DCRX_PHY_MACRO_CNTL_RESERVED 0 31 mmDCRX_PHY_MACRO_CNTL_RESERVED45 0 0x2c33 1 0 2 DCRX_PHY_MACRO_CNTL_RESERVED 0 31 mmDCRX_PHY_MACRO_CNTL_RESERVED46 0 0x2c34 1 0 2 DCRX_PHY_MACRO_CNTL_RESERVED 0 31 mmDCRX_PHY_MACRO_CNTL_RESERVED47 0 0x2c35 1 0 2 DCRX_PHY_MACRO_CNTL_RESERVED 0 31 mmDCRX_PHY_MACRO_CNTL_RESERVED48 0 0x2c36 1 0 2 DCRX_PHY_MACRO_CNTL_RESERVED 0 31 mmDCRX_PHY_MACRO_CNTL_RESERVED49 0 0x2c37 1 0 2 DCRX_PHY_MACRO_CNTL_RESERVED 0 31 mmDCRX_PHY_MACRO_CNTL_RESERVED50 0 0x2c38 1 0 2 DCRX_PHY_MACRO_CNTL_RESERVED 0 31 mmDCRX_PHY_MACRO_CNTL_RESERVED51 0 0x2c39 1 0 2 DCRX_PHY_MACRO_CNTL_RESERVED 0 31 mmDCRX_PHY_MACRO_CNTL_RESERVED52 0 0x2c3a 1 0 2 DCRX_PHY_MACRO_CNTL_RESERVED 0 31 mmDCRX_PHY_MACRO_CNTL_RESERVED53 0 0x2c3b 1 0 2 DCRX_PHY_MACRO_CNTL_RESERVED 0 31 mmDCRX_PHY_MACRO_CNTL_RESERVED54 0 0x2c3c 1 0 2 DCRX_PHY_MACRO_CNTL_RESERVED 0 31 mmDCRX_PHY_MACRO_CNTL_RESERVED55 0 0x2c3d 1 0 2 DCRX_PHY_MACRO_CNTL_RESERVED 0 31 mmDCRX_PHY_MACRO_CNTL_RESERVED56 0 0x2c3e 1 0 2 DCRX_PHY_MACRO_CNTL_RESERVED 0 31 mmDCRX_PHY_MACRO_CNTL_RESERVED57 0 0x2c3f 1 0 2 DCRX_PHY_MACRO_CNTL_RESERVED 0 31 mmDCRX_PHY_MACRO_CNTL_RESERVED58 0 0x2c40 1 0 2 DCRX_PHY_MACRO_CNTL_RESERVED 0 31 mmDCRX_PHY_MACRO_CNTL_RESERVED59 0 0x2c41 1 0 2 DCRX_PHY_MACRO_CNTL_RESERVED 0 31 mmDCRX_PHY_MACRO_CNTL_RESERVED60 0 0x2c42 1 0 2 DCRX_PHY_MACRO_CNTL_RESERVED 0 31 mmDCRX_PHY_MACRO_CNTL_RESERVED61 0 0x2c43 1 0 2 DCRX_PHY_MACRO_CNTL_RESERVED 0 31 mmDCRX_PHY_MACRO_CNTL_RESERVED62 0 0x2c44 1 0 2 DCRX_PHY_MACRO_CNTL_RESERVED 0 31 mmDCRX_PHY_MACRO_CNTL_RESERVED63 0 0x2c45 1 0 2 DCRX_PHY_MACRO_CNTL_RESERVED 0 31 mmDCRX_PHY_MACRO_CNTL_RESERVED64 0 0x2c46 1 0 2 DCRX_PHY_MACRO_CNTL_RESERVED 0 31 mmDCRX_PHY_MACRO_CNTL_RESERVED65 0 0x2c47 1 0 2 DCRX_PHY_MACRO_CNTL_RESERVED 0 31 mmDCRX_PHY_MACRO_CNTL_RESERVED66 0 0x2c48 1 0 2 DCRX_PHY_MACRO_CNTL_RESERVED 0 31 mmDCRX_PHY_MACRO_CNTL_RESERVED67 0 0x2c49 1 0 2 DCRX_PHY_MACRO_CNTL_RESERVED 0 31 mmDCRX_PHY_MACRO_CNTL_RESERVED68 0 0x2c4a 1 0 2 DCRX_PHY_MACRO_CNTL_RESERVED 0 31 mmDCRX_PHY_MACRO_CNTL_RESERVED69 0 0x2c4b 1 0 2 DCRX_PHY_MACRO_CNTL_RESERVED 0 31 mmDCRX_PHY_MACRO_CNTL_RESERVED70 0 0x2c4c 1 0 2 DCRX_PHY_MACRO_CNTL_RESERVED 0 31 mmDCRX_PHY_MACRO_CNTL_RESERVED71 0 0x2c4d 1 0 2 DCRX_PHY_MACRO_CNTL_RESERVED 0 31 mmDCRX_PHY_MACRO_CNTL_RESERVED72 0 0x2c4e 1 0 2 DCRX_PHY_MACRO_CNTL_RESERVED 0 31 mmDCRX_PHY_MACRO_CNTL_RESERVED73 0 0x2c4f 1 0 2 DCRX_PHY_MACRO_CNTL_RESERVED 0 31 mmDCRX_PHY_MACRO_CNTL_RESERVED74 0 0x2c50 1 0 2 DCRX_PHY_MACRO_CNTL_RESERVED 0 31 mmDCRX_PHY_MACRO_CNTL_RESERVED75 0 0x2c51 1 0 2 DCRX_PHY_MACRO_CNTL_RESERVED 0 31 mmDCRX_PHY_MACRO_CNTL_RESERVED76 0 0x2c52 1 0 2 DCRX_PHY_MACRO_CNTL_RESERVED 0 31 mmDCRX_PHY_MACRO_CNTL_RESERVED77 0 0x2c53 1 0 2 DCRX_PHY_MACRO_CNTL_RESERVED 0 31 mmDCRX_PHY_MACRO_CNTL_RESERVED78 0 0x2c54 1 0 2 DCRX_PHY_MACRO_CNTL_RESERVED 0 31 mmDCRX_PHY_MACRO_CNTL_RESERVED79 0 0x2c55 1 0 2 DCRX_PHY_MACRO_CNTL_RESERVED 0 31 mmDCRX_PHY_MACRO_CNTL_RESERVED80 0 0x2c56 1 0 2 DCRX_PHY_MACRO_CNTL_RESERVED 0 31 mmDCRX_PHY_MACRO_CNTL_RESERVED81 0 0x2c57 1 0 2 DCRX_PHY_MACRO_CNTL_RESERVED 0 31 mmDCRX_PHY_MACRO_CNTL_RESERVED82 0 0x2c58 1 0 2 DCRX_PHY_MACRO_CNTL_RESERVED 0 31 mmDCRX_PHY_MACRO_CNTL_RESERVED83 0 0x2c59 1 0 2 DCRX_PHY_MACRO_CNTL_RESERVED 0 31 mmDCRX_PHY_MACRO_CNTL_RESERVED84 0 0x2c5a 1 0 2 DCRX_PHY_MACRO_CNTL_RESERVED 0 31 mmDCRX_PHY_MACRO_CNTL_RESERVED85 0 0x2c5b 1 0 2 DCRX_PHY_MACRO_CNTL_RESERVED 0 31 mmDCRX_PHY_MACRO_CNTL_RESERVED86 0 0x2c5c 1 0 2 DCRX_PHY_MACRO_CNTL_RESERVED 0 31 mmDCRX_PHY_MACRO_CNTL_RESERVED87 0 0x2c5d 1 0 2 DCRX_PHY_MACRO_CNTL_RESERVED 0 31 mmDCRX_PHY_MACRO_CNTL_RESERVED88 0 0x2c5e 1 0 2 DCRX_PHY_MACRO_CNTL_RESERVED 0 31 mmDCRX_PHY_MACRO_CNTL_RESERVED89 0 0x2c5f 1 0 2 DCRX_PHY_MACRO_CNTL_RESERVED 0 31 mmDCRX_PHY_MACRO_CNTL_RESERVED90 0 0x2c60 1 0 2 DCRX_PHY_MACRO_CNTL_RESERVED 0 31 mmDCRX_PHY_MACRO_CNTL_RESERVED91 0 0x2c61 1 0 2 DCRX_PHY_MACRO_CNTL_RESERVED 0 31 mmDCRX_PHY_MACRO_CNTL_RESERVED92 0 0x2c62 1 0 2 DCRX_PHY_MACRO_CNTL_RESERVED 0 31 mmDCRX_PHY_MACRO_CNTL_RESERVED93 0 0x2c63 1 0 2 DCRX_PHY_MACRO_CNTL_RESERVED 0 31 mmDCRX_PHY_MACRO_CNTL_RESERVED94 0 0x2c64 1 0 2 DCRX_PHY_MACRO_CNTL_RESERVED 0 31 mmDCRX_PHY_MACRO_CNTL_RESERVED95 0 0x2c65 1 0 2 DCRX_PHY_MACRO_CNTL_RESERVED 0 31 mmDCRX_PHY_MACRO_CNTL_RESERVED96 0 0x2c66 1 0 2 DCRX_PHY_MACRO_CNTL_RESERVED 0 31 mmDCRX_PHY_MACRO_CNTL_RESERVED97 0 0x2c67 1 0 2 DCRX_PHY_MACRO_CNTL_RESERVED 0 31 mmDCRX_PHY_MACRO_CNTL_RESERVED98 0 0x2c68 1 0 2 DCRX_PHY_MACRO_CNTL_RESERVED 0 31 mmDCRX_PHY_MACRO_CNTL_RESERVED99 0 0x2c69 1 0 2 DCRX_PHY_MACRO_CNTL_RESERVED 0 31 mmDCRX_PHY_MACRO_CNTL_RESERVED100 0 0x2c6a 1 0 2 DCRX_PHY_MACRO_CNTL_RESERVED 0 31 mmDCRX_PHY_MACRO_CNTL_RESERVED101 0 0x2c6b 1 0 2 DCRX_PHY_MACRO_CNTL_RESERVED 0 31 mmDCRX_PHY_MACRO_CNTL_RESERVED102 0 0x2c6c 1 0 2 DCRX_PHY_MACRO_CNTL_RESERVED 0 31 mmDCRX_PHY_MACRO_CNTL_RESERVED103 0 0x2c6d 1 0 2 DCRX_PHY_MACRO_CNTL_RESERVED 0 31 mmDCRX_PHY_MACRO_CNTL_RESERVED104 0 0x2c6e 1 0 2 DCRX_PHY_MACRO_CNTL_RESERVED 0 31 mmDCRX_PHY_MACRO_CNTL_RESERVED105 0 0x2c6f 1 0 2 DCRX_PHY_MACRO_CNTL_RESERVED 0 31 mmDCRX_PHY_MACRO_CNTL_RESERVED106 0 0x2c70 1 0 2 DCRX_PHY_MACRO_CNTL_RESERVED 0 31 mmDCRX_PHY_MACRO_CNTL_RESERVED107 0 0x2c71 1 0 2 DCRX_PHY_MACRO_CNTL_RESERVED 0 31 mmDCRX_PHY_MACRO_CNTL_RESERVED108 0 0x2c72 1 0 2 DCRX_PHY_MACRO_CNTL_RESERVED 0 31 mmDCRX_PHY_MACRO_CNTL_RESERVED109 0 0x2c73 1 0 2 DCRX_PHY_MACRO_CNTL_RESERVED 0 31 mmDCRX_PHY_MACRO_CNTL_RESERVED110 0 0x2c74 1 0 2 DCRX_PHY_MACRO_CNTL_RESERVED 0 31 mmDCRX_PHY_MACRO_CNTL_RESERVED111 0 0x2c75 1 0 2 DCRX_PHY_MACRO_CNTL_RESERVED 0 31 mmDCRX_PHY_MACRO_CNTL_RESERVED112 0 0x2c76 1 0 2 DCRX_PHY_MACRO_CNTL_RESERVED 0 31 mmDCRX_PHY_MACRO_CNTL_RESERVED113 0 0x2c77 1 0 2 DCRX_PHY_MACRO_CNTL_RESERVED 0 31 mmDCRX_PHY_MACRO_CNTL_RESERVED114 0 0x2c78 1 0 2 DCRX_PHY_MACRO_CNTL_RESERVED 0 31 mmDCRX_PHY_MACRO_CNTL_RESERVED115 0 0x2c79 1 0 2 DCRX_PHY_MACRO_CNTL_RESERVED 0 31 mmDCRX_PHY_MACRO_CNTL_RESERVED116 0 0x2c7a 1 0 2 DCRX_PHY_MACRO_CNTL_RESERVED 0 31 mmDCRX_PHY_MACRO_CNTL_RESERVED117 0 0x2c7b 1 0 2 DCRX_PHY_MACRO_CNTL_RESERVED 0 31 mmDCRX_PHY_MACRO_CNTL_RESERVED118 0 0x2c7c 1 0 2 DCRX_PHY_MACRO_CNTL_RESERVED 0 31 mmDCRX_PHY_MACRO_CNTL_RESERVED119 0 0x2c7d 1 0 2 DCRX_PHY_MACRO_CNTL_RESERVED 0 31 mmDCRX_PHY_MACRO_CNTL_RESERVED120 0 0x2c7e 1 0 2 DCRX_PHY_MACRO_CNTL_RESERVED 0 31 mmDCRX_PHY_MACRO_CNTL_RESERVED121 0 0x2c7f 1 0 2 DCRX_PHY_MACRO_CNTL_RESERVED 0 31 mmDCRX_PHY_MACRO_CNTL_RESERVED122 0 0x2c80 1 0 2 DCRX_PHY_MACRO_CNTL_RESERVED 0 31 mmDCRX_PHY_MACRO_CNTL_RESERVED123 0 0x2c81 1 0 2 DCRX_PHY_MACRO_CNTL_RESERVED 0 31 mmDCRX_PHY_MACRO_CNTL_RESERVED124 0 0x2c82 1 0 2 DCRX_PHY_MACRO_CNTL_RESERVED 0 31 mmDCRX_PHY_MACRO_CNTL_RESERVED125 0 0x2c83 1 0 2 DCRX_PHY_MACRO_CNTL_RESERVED 0 31 mmDCRX_PHY_MACRO_CNTL_RESERVED126 0 0x2c84 1 0 2 DCRX_PHY_MACRO_CNTL_RESERVED 0 31 mmDCRX_PHY_MACRO_CNTL_RESERVED127 0 0x2c85 1 0 2 DCRX_PHY_MACRO_CNTL_RESERVED 0 31 mmDCRX_PHY_MACRO_CNTL_RESERVED128 0 0x2c86 1 0 2 DCRX_PHY_MACRO_CNTL_RESERVED 0 31 mmDCRX_PHY_MACRO_CNTL_RESERVED129 0 0x2c87 1 0 2 DCRX_PHY_MACRO_CNTL_RESERVED 0 31 mmDCRX_PHY_MACRO_CNTL_RESERVED130 0 0x2c88 1 0 2 DCRX_PHY_MACRO_CNTL_RESERVED 0 31 mmDCRX_PHY_MACRO_CNTL_RESERVED131 0 0x2c89 1 0 2 DCRX_PHY_MACRO_CNTL_RESERVED 0 31 mmDCRX_PHY_MACRO_CNTL_RESERVED132 0 0x2c8a 1 0 2 DCRX_PHY_MACRO_CNTL_RESERVED 0 31 mmDCRX_PHY_MACRO_CNTL_RESERVED133 0 0x2c8b 1 0 2 DCRX_PHY_MACRO_CNTL_RESERVED 0 31 mmDCRX_PHY_MACRO_CNTL_RESERVED134 0 0x2c8c 1 0 2 DCRX_PHY_MACRO_CNTL_RESERVED 0 31 mmDCRX_PHY_MACRO_CNTL_RESERVED135 0 0x2c8d 1 0 2 DCRX_PHY_MACRO_CNTL_RESERVED 0 31 mmDCRX_PHY_MACRO_CNTL_RESERVED136 0 0x2c8e 1 0 2 DCRX_PHY_MACRO_CNTL_RESERVED 0 31 mmDCRX_PHY_MACRO_CNTL_RESERVED137 0 0x2c8f 1 0 2 DCRX_PHY_MACRO_CNTL_RESERVED 0 31 mmDCRX_PHY_MACRO_CNTL_RESERVED138 0 0x2c90 1 0 2 DCRX_PHY_MACRO_CNTL_RESERVED 0 31 mmDCRX_PHY_MACRO_CNTL_RESERVED139 0 0x2c91 1 0 2 DCRX_PHY_MACRO_CNTL_RESERVED 0 31 mmDCRX_PHY_MACRO_CNTL_RESERVED140 0 0x2c92 1 0 2 DCRX_PHY_MACRO_CNTL_RESERVED 0 31 mmDCRX_PHY_MACRO_CNTL_RESERVED141 0 0x2c93 1 0 2 DCRX_PHY_MACRO_CNTL_RESERVED 0 31 mmDCRX_PHY_MACRO_CNTL_RESERVED142 0 0x2c94 1 0 2 DCRX_PHY_MACRO_CNTL_RESERVED 0 31 mmDCRX_PHY_MACRO_CNTL_RESERVED143 0 0x2c95 1 0 2 DCRX_PHY_MACRO_CNTL_RESERVED 0 31 mmDCRX_PHY_MACRO_CNTL_RESERVED144 0 0x2c96 1 0 2 DCRX_PHY_MACRO_CNTL_RESERVED 0 31 mmDCRX_PHY_MACRO_CNTL_RESERVED145 0 0x2c97 1 0 2 DCRX_PHY_MACRO_CNTL_RESERVED 0 31 mmDCRX_PHY_MACRO_CNTL_RESERVED146 0 0x2c98 1 0 2 DCRX_PHY_MACRO_CNTL_RESERVED 0 31 mmDCRX_PHY_MACRO_CNTL_RESERVED147 0 0x2c99 1 0 2 DCRX_PHY_MACRO_CNTL_RESERVED 0 31 mmDCRX_PHY_MACRO_CNTL_RESERVED148 0 0x2c9a 1 0 2 DCRX_PHY_MACRO_CNTL_RESERVED 0 31 mmDCRX_PHY_MACRO_CNTL_RESERVED149 0 0x2c9b 1 0 2 DCRX_PHY_MACRO_CNTL_RESERVED 0 31 mmDCRX_PHY_MACRO_CNTL_RESERVED150 0 0x2c9c 1 0 2 DCRX_PHY_MACRO_CNTL_RESERVED 0 31 mmDCRX_PHY_MACRO_CNTL_RESERVED151 0 0x2c9d 1 0 2 DCRX_PHY_MACRO_CNTL_RESERVED 0 31 mmDCRX_PHY_MACRO_CNTL_RESERVED152 0 0x2c9e 1 0 2 DCRX_PHY_MACRO_CNTL_RESERVED 0 31 mmDCRX_PHY_MACRO_CNTL_RESERVED153 0 0x2c9f 1 0 2 DCRX_PHY_MACRO_CNTL_RESERVED 0 31 mmDCRX_PHY_MACRO_CNTL_RESERVED154 0 0x2ca0 1 0 2 DCRX_PHY_MACRO_CNTL_RESERVED 0 31 mmDCRX_PHY_MACRO_CNTL_RESERVED155 0 0x2ca1 1 0 2 DCRX_PHY_MACRO_CNTL_RESERVED 0 31 mmDCRX_PHY_MACRO_CNTL_RESERVED156 0 0x2ca2 1 0 2 DCRX_PHY_MACRO_CNTL_RESERVED 0 31 mmDCRX_PHY_MACRO_CNTL_RESERVED157 0 0x2ca3 1 0 2 DCRX_PHY_MACRO_CNTL_RESERVED 0 31 mmDCRX_PHY_MACRO_CNTL_RESERVED158 0 0x2ca4 1 0 2 DCRX_PHY_MACRO_CNTL_RESERVED 0 31 mmDCRX_PHY_MACRO_CNTL_RESERVED159 0 0x2ca5 1 0 2 DCRX_PHY_MACRO_CNTL_RESERVED 0 31 mmDCRX_PHY_MACRO_CNTL_RESERVED160 0 0x2ca6 1 0 2 DCRX_PHY_MACRO_CNTL_RESERVED 0 31 mmDCRX_PHY_MACRO_CNTL_RESERVED161 0 0x2ca7 1 0 2 DCRX_PHY_MACRO_CNTL_RESERVED 0 31 mmDCRX_PHY_MACRO_CNTL_RESERVED162 0 0x2ca8 1 0 2 DCRX_PHY_MACRO_CNTL_RESERVED 0 31 mmDCRX_PHY_MACRO_CNTL_RESERVED163 0 0x2ca9 1 0 2 DCRX_PHY_MACRO_CNTL_RESERVED 0 31 mmDCRX_PHY_MACRO_CNTL_RESERVED164 0 0x2caa 1 0 2 DCRX_PHY_MACRO_CNTL_RESERVED 0 31 mmDCRX_PHY_MACRO_CNTL_RESERVED165 0 0x2cab 1 0 2 DCRX_PHY_MACRO_CNTL_RESERVED 0 31 mmDCRX_PHY_MACRO_CNTL_RESERVED166 0 0x2cac 1 0 2 DCRX_PHY_MACRO_CNTL_RESERVED 0 31 mmDCRX_PHY_MACRO_CNTL_RESERVED167 0 0x2cad 1 0 2 DCRX_PHY_MACRO_CNTL_RESERVED 0 31 mmDCRX_PHY_MACRO_CNTL_RESERVED168 0 0x2cae 1 0 2 DCRX_PHY_MACRO_CNTL_RESERVED 0 31 mmDCRX_PHY_MACRO_CNTL_RESERVED169 0 0x2caf 1 0 2 DCRX_PHY_MACRO_CNTL_RESERVED 0 31 mmDCRX_PHY_MACRO_CNTL_RESERVED170 0 0x2cb0 1 0 2 DCRX_PHY_MACRO_CNTL_RESERVED 0 31 mmDCRX_PHY_MACRO_CNTL_RESERVED171 0 0x2cb1 1 0 2 DCRX_PHY_MACRO_CNTL_RESERVED 0 31 mmDCRX_PHY_MACRO_CNTL_RESERVED172 0 0x2cb2 1 0 2 DCRX_PHY_MACRO_CNTL_RESERVED 0 31 mmDCRX_PHY_MACRO_CNTL_RESERVED173 0 0x2cb3 1 0 2 DCRX_PHY_MACRO_CNTL_RESERVED 0 31 mmDCRX_PHY_MACRO_CNTL_RESERVED174 0 0x2cb4 1 0 2 DCRX_PHY_MACRO_CNTL_RESERVED 0 31 mmDCRX_PHY_MACRO_CNTL_RESERVED175 0 0x2cb5 1 0 2 DCRX_PHY_MACRO_CNTL_RESERVED 0 31 mmDCRX_PHY_MACRO_CNTL_RESERVED176 0 0x2cb6 1 0 2 DCRX_PHY_MACRO_CNTL_RESERVED 0 31 mmDCRX_PHY_MACRO_CNTL_RESERVED177 0 0x2cb7 1 0 2 DCRX_PHY_MACRO_CNTL_RESERVED 0 31 mmDCRX_PHY_MACRO_CNTL_RESERVED178 0 0x2cb8 1 0 2 DCRX_PHY_MACRO_CNTL_RESERVED 0 31 mmDCRX_PHY_MACRO_CNTL_RESERVED179 0 0x2cb9 1 0 2 DCRX_PHY_MACRO_CNTL_RESERVED 0 31 mmDCRX_PHY_MACRO_CNTL_RESERVED180 0 0x2cba 1 0 2 DCRX_PHY_MACRO_CNTL_RESERVED 0 31 mmDCRX_PHY_MACRO_CNTL_RESERVED181 0 0x2cbb 1 0 2 DCRX_PHY_MACRO_CNTL_RESERVED 0 31 mmDCRX_PHY_MACRO_CNTL_RESERVED182 0 0x2cbc 1 0 2 DCRX_PHY_MACRO_CNTL_RESERVED 0 31 mmDCRX_PHY_MACRO_CNTL_RESERVED183 0 0x2cbd 1 0 2 DCRX_PHY_MACRO_CNTL_RESERVED 0 31 mmDCRX_PHY_MACRO_CNTL_RESERVED184 0 0x2cbe 1 0 2 DCRX_PHY_MACRO_CNTL_RESERVED 0 31 mmDCRX_PHY_MACRO_CNTL_RESERVED185 0 0x2cbf 1 0 2 DCRX_PHY_MACRO_CNTL_RESERVED 0 31 mmDCRX_PHY_MACRO_CNTL_RESERVED186 0 0x2cc0 1 0 2 DCRX_PHY_MACRO_CNTL_RESERVED 0 31 mmDCRX_PHY_MACRO_CNTL_RESERVED187 0 0x2cc1 1 0 2 DCRX_PHY_MACRO_CNTL_RESERVED 0 31 mmDCRX_PHY_MACRO_CNTL_RESERVED188 0 0x2cc2 1 0 2 DCRX_PHY_MACRO_CNTL_RESERVED 0 31 mmDCRX_PHY_MACRO_CNTL_RESERVED189 0 0x2cc3 1 0 2 DCRX_PHY_MACRO_CNTL_RESERVED 0 31 mmDCRX_PHY_MACRO_CNTL_RESERVED190 0 0x2cc4 1 0 2 DCRX_PHY_MACRO_CNTL_RESERVED 0 31 mmDCRX_PHY_MACRO_CNTL_RESERVED191 0 0x2cc5 1 0 2 DCRX_PHY_MACRO_CNTL_RESERVED 0 31 mmDCRX_PHY_MACRO_CNTL_RESERVED192 0 0x2cc6 1 0 2 DCRX_PHY_MACRO_CNTL_RESERVED 0 31 mmDCRX_PHY_MACRO_CNTL_RESERVED193 0 0x2cc7 1 0 2 DCRX_PHY_MACRO_CNTL_RESERVED 0 31 mmDCRX_PHY_MACRO_CNTL_RESERVED194 0 0x2cc8 1 0 2 DCRX_PHY_MACRO_CNTL_RESERVED 0 31 mmDCRX_PHY_MACRO_CNTL_RESERVED195 0 0x2cc9 1 0 2 DCRX_PHY_MACRO_CNTL_RESERVED 0 31 mmDCRX_PHY_MACRO_CNTL_RESERVED196 0 0x2cca 1 0 2 DCRX_PHY_MACRO_CNTL_RESERVED 0 31 mmDCRX_PHY_MACRO_CNTL_RESERVED197 0 0x2ccb 1 0 2 DCRX_PHY_MACRO_CNTL_RESERVED 0 31 mmDCRX_PHY_MACRO_CNTL_RESERVED198 0 0x2ccc 1 0 2 DCRX_PHY_MACRO_CNTL_RESERVED 0 31 mmDCRX_PHY_MACRO_CNTL_RESERVED199 0 0x2ccd 1 0 2 DCRX_PHY_MACRO_CNTL_RESERVED 0 31 mmDCRX_PHY_MACRO_CNTL_RESERVED200 0 0x2cce 1 0 2 DCRX_PHY_MACRO_CNTL_RESERVED 0 31 mmDCRX_PHY_MACRO_CNTL_RESERVED201 0 0x2ccf 1 0 2 DCRX_PHY_MACRO_CNTL_RESERVED 0 31 mmDCRX_PHY_MACRO_CNTL_RESERVED202 0 0x2cd0 1 0 2 DCRX_PHY_MACRO_CNTL_RESERVED 0 31 mmDCRX_PHY_MACRO_CNTL_RESERVED203 0 0x2cd1 1 0 2 DCRX_PHY_MACRO_CNTL_RESERVED 0 31 mmDCRX_PHY_MACRO_CNTL_RESERVED204 0 0x2cd2 1 0 2 DCRX_PHY_MACRO_CNTL_RESERVED 0 31 mmDCRX_PHY_MACRO_CNTL_RESERVED205 0 0x2cd3 1 0 2 DCRX_PHY_MACRO_CNTL_RESERVED 0 31 mmDCRX_PHY_MACRO_CNTL_RESERVED206 0 0x2cd4 1 0 2 DCRX_PHY_MACRO_CNTL_RESERVED 0 31 mmDCRX_PHY_MACRO_CNTL_RESERVED207 0 0x2cd5 1 0 2 DCRX_PHY_MACRO_CNTL_RESERVED 0 31 mmDCRX_PHY_MACRO_CNTL_RESERVED208 0 0x2cd6 1 0 2 DCRX_PHY_MACRO_CNTL_RESERVED 0 31 mmDCRX_PHY_MACRO_CNTL_RESERVED209 0 0x2cd7 1 0 2 DCRX_PHY_MACRO_CNTL_RESERVED 0 31 mmDCRX_PHY_MACRO_CNTL_RESERVED210 0 0x2cd8 1 0 2 DCRX_PHY_MACRO_CNTL_RESERVED 0 31 mmDCRX_PHY_MACRO_CNTL_RESERVED211 0 0x2cd9 1 0 2 DCRX_PHY_MACRO_CNTL_RESERVED 0 31 mmDCRX_PHY_MACRO_CNTL_RESERVED212 0 0x2cda 1 0 2 DCRX_PHY_MACRO_CNTL_RESERVED 0 31 mmDCRX_PHY_MACRO_CNTL_RESERVED213 0 0x2cdb 1 0 2 DCRX_PHY_MACRO_CNTL_RESERVED 0 31 mmDCRX_PHY_MACRO_CNTL_RESERVED214 0 0x2cdc 1 0 2 DCRX_PHY_MACRO_CNTL_RESERVED 0 31 mmDCRX_PHY_MACRO_CNTL_RESERVED215 0 0x2cdd 1 0 2 DCRX_PHY_MACRO_CNTL_RESERVED 0 31 mmDCRX_PHY_MACRO_CNTL_RESERVED216 0 0x2cde 1 0 2 DCRX_PHY_MACRO_CNTL_RESERVED 0 31 mmDCRX_PHY_MACRO_CNTL_RESERVED217 0 0x2cdf 1 0 2 DCRX_PHY_MACRO_CNTL_RESERVED 0 31 mmDCRX_PHY_MACRO_CNTL_RESERVED218 0 0x2ce0 1 0 2 DCRX_PHY_MACRO_CNTL_RESERVED 0 31 mmDCRX_PHY_MACRO_CNTL_RESERVED219 0 0x2ce1 1 0 2 DCRX_PHY_MACRO_CNTL_RESERVED 0 31 mmDCRX_PHY_MACRO_CNTL_RESERVED220 0 0x2ce2 1 0 2 DCRX_PHY_MACRO_CNTL_RESERVED 0 31 mmDCRX_PHY_MACRO_CNTL_RESERVED221 0 0x2ce3 1 0 2 DCRX_PHY_MACRO_CNTL_RESERVED 0 31 mmDCRX_PHY_MACRO_CNTL_RESERVED222 0 0x2ce4 1 0 2 DCRX_PHY_MACRO_CNTL_RESERVED 0 31 mmDCRX_PHY_MACRO_CNTL_RESERVED223 0 0x2ce5 1 0 2 DCRX_PHY_MACRO_CNTL_RESERVED 0 31 mmDCRX_PHY_MACRO_CNTL_RESERVED224 0 0x2ce6 1 0 2 DCRX_PHY_MACRO_CNTL_RESERVED 0 31 mmDCRX_PHY_MACRO_CNTL_RESERVED225 0 0x2ce7 1 0 2 DCRX_PHY_MACRO_CNTL_RESERVED 0 31 mmDCRX_PHY_MACRO_CNTL_RESERVED226 0 0x2ce8 1 0 2 DCRX_PHY_MACRO_CNTL_RESERVED 0 31 mmDCRX_PHY_MACRO_CNTL_RESERVED227 0 0x2ce9 1 0 2 DCRX_PHY_MACRO_CNTL_RESERVED 0 31 mmDCRX_PHY_MACRO_CNTL_RESERVED228 0 0x2cea 1 0 2 DCRX_PHY_MACRO_CNTL_RESERVED 0 31 mmDCRX_PHY_MACRO_CNTL_RESERVED229 0 0x2ceb 1 0 2 DCRX_PHY_MACRO_CNTL_RESERVED 0 31 mmDCRX_PHY_MACRO_CNTL_RESERVED230 0 0x2cec 1 0 2 DCRX_PHY_MACRO_CNTL_RESERVED 0 31 mmDCRX_PHY_MACRO_CNTL_RESERVED231 0 0x2ced 1 0 2 DCRX_PHY_MACRO_CNTL_RESERVED 0 31 mmDCRX_PHY_MACRO_CNTL_RESERVED232 0 0x2cee 1 0 2 DCRX_PHY_MACRO_CNTL_RESERVED 0 31 mmDCRX_PHY_MACRO_CNTL_RESERVED233 0 0x2cef 1 0 2 DCRX_PHY_MACRO_CNTL_RESERVED 0 31 mmDCRX_PHY_MACRO_CNTL_RESERVED234 0 0x2cf0 1 0 2 DCRX_PHY_MACRO_CNTL_RESERVED 0 31 mmDCRX_PHY_MACRO_CNTL_RESERVED235 0 0x2cf1 1 0 2 DCRX_PHY_MACRO_CNTL_RESERVED 0 31 mmDCRX_PHY_MACRO_CNTL_RESERVED236 0 0x2cf2 1 0 2 DCRX_PHY_MACRO_CNTL_RESERVED 0 31 mmDCRX_PHY_MACRO_CNTL_RESERVED237 0 0x2cf3 1 0 2 DCRX_PHY_MACRO_CNTL_RESERVED 0 31 mmDCRX_PHY_MACRO_CNTL_RESERVED238 0 0x2cf4 1 0 2 DCRX_PHY_MACRO_CNTL_RESERVED 0 31 mmDCRX_PHY_MACRO_CNTL_RESERVED239 0 0x2cf5 1 0 2 DCRX_PHY_MACRO_CNTL_RESERVED 0 31 mmDCRX_PHY_MACRO_CNTL_RESERVED240 0 0x2cf6 1 0 2 DCRX_PHY_MACRO_CNTL_RESERVED 0 31 mmDCRX_PHY_MACRO_CNTL_RESERVED241 0 0x2cf7 1 0 2 DCRX_PHY_MACRO_CNTL_RESERVED 0 31 mmDCRX_PHY_MACRO_CNTL_RESERVED242 0 0x2cf8 1 0 2 DCRX_PHY_MACRO_CNTL_RESERVED 0 31 mmDCRX_PHY_MACRO_CNTL_RESERVED243 0 0x2cf9 1 0 2 DCRX_PHY_MACRO_CNTL_RESERVED 0 31 mmDCRX_PHY_MACRO_CNTL_RESERVED244 0 0x2cfa 1 0 2 DCRX_PHY_MACRO_CNTL_RESERVED 0 31 mmDCRX_PHY_MACRO_CNTL_RESERVED245 0 0x2cfb 1 0 2 DCRX_PHY_MACRO_CNTL_RESERVED 0 31 mmDCRX_PHY_MACRO_CNTL_RESERVED246 0 0x2cfc 1 0 2 DCRX_PHY_MACRO_CNTL_RESERVED 0 31 mmDCRX_PHY_MACRO_CNTL_RESERVED247 0 0x2cfd 1 0 2 DCRX_PHY_MACRO_CNTL_RESERVED 0 31 mmDCRX_PHY_MACRO_CNTL_RESERVED248 0 0x2cfe 1 0 2 DCRX_PHY_MACRO_CNTL_RESERVED 0 31 mmDCRX_PHY_MACRO_CNTL_RESERVED249 0 0x2cff 1 0 2 DCRX_PHY_MACRO_CNTL_RESERVED 0 31 mmDCRX_PHY_MACRO_CNTL_RESERVED250 0 0x2d00 1 0 2 DCRX_PHY_MACRO_CNTL_RESERVED 0 31 mmDCRX_PHY_MACRO_CNTL_RESERVED251 0 0x2d01 1 0 2 DCRX_PHY_MACRO_CNTL_RESERVED 0 31 mmDCRX_PHY_MACRO_CNTL_RESERVED252 0 0x2d02 1 0 2 DCRX_PHY_MACRO_CNTL_RESERVED 0 31 mmDCRX_PHY_MACRO_CNTL_RESERVED253 0 0x2d03 1 0 2 DCRX_PHY_MACRO_CNTL_RESERVED 0 31 mmDCRX_PHY_MACRO_CNTL_RESERVED254 0 0x2d04 1 0 2 DCRX_PHY_MACRO_CNTL_RESERVED 0 31 mmDCRX_PHY_MACRO_CNTL_RESERVED255 0 0x2d05 1 0 2 DCRX_PHY_MACRO_CNTL_RESERVED 0 31 mmDCRX_PHY_MACRO_CNTL_RESERVED256 0 0x2d06 1 0 2 DCRX_PHY_MACRO_CNTL_RESERVED 0 31 mmDCRX_PHY_MACRO_CNTL_RESERVED257 0 0x2d07 1 0 2 DCRX_PHY_MACRO_CNTL_RESERVED 0 31 mmDCRX_PHY_MACRO_CNTL_RESERVED258 0 0x2d08 1 0 2 DCRX_PHY_MACRO_CNTL_RESERVED 0 31 mmDCRX_PHY_MACRO_CNTL_RESERVED259 0 0x2d09 1 0 2 DCRX_PHY_MACRO_CNTL_RESERVED 0 31 mmDCRX_PHY_MACRO_CNTL_RESERVED260 0 0x2d0a 1 0 2 DCRX_PHY_MACRO_CNTL_RESERVED 0 31 mmDCRX_PHY_MACRO_CNTL_RESERVED261 0 0x2d0b 1 0 2 DCRX_PHY_MACRO_CNTL_RESERVED 0 31 mmDCRX_PHY_MACRO_CNTL_RESERVED262 0 0x2d0c 1 0 2 DCRX_PHY_MACRO_CNTL_RESERVED 0 31 mmDCRX_PHY_MACRO_CNTL_RESERVED263 0 0x2d0d 1 0 2 DCRX_PHY_MACRO_CNTL_RESERVED 0 31 mmDCRX_PHY_MACRO_CNTL_RESERVED264 0 0x2d0e 1 0 2 DCRX_PHY_MACRO_CNTL_RESERVED 0 31 mmDCRX_PHY_MACRO_CNTL_RESERVED265 0 0x2d0f 1 0 2 DCRX_PHY_MACRO_CNTL_RESERVED 0 31 mmDCRX_PHY_MACRO_CNTL_RESERVED266 0 0x2d10 1 0 2 DCRX_PHY_MACRO_CNTL_RESERVED 0 31 mmDCRX_PHY_MACRO_CNTL_RESERVED267 0 0x2d11 1 0 2 DCRX_PHY_MACRO_CNTL_RESERVED 0 31 mmDCRX_PHY_MACRO_CNTL_RESERVED268 0 0x2d12 1 0 2 DCRX_PHY_MACRO_CNTL_RESERVED 0 31 mmDCRX_PHY_MACRO_CNTL_RESERVED269 0 0x2d13 1 0 2 DCRX_PHY_MACRO_CNTL_RESERVED 0 31 mmDCRX_PHY_MACRO_CNTL_RESERVED270 0 0x2d14 1 0 2 DCRX_PHY_MACRO_CNTL_RESERVED 0 31 mmDCRX_PHY_MACRO_CNTL_RESERVED271 0 0x2d15 1 0 2 DCRX_PHY_MACRO_CNTL_RESERVED 0 31 mmDCRX_PHY_MACRO_CNTL_RESERVED272 0 0x2d16 1 0 2 DCRX_PHY_MACRO_CNTL_RESERVED 0 31 mmDCRX_PHY_MACRO_CNTL_RESERVED273 0 0x2d17 1 0 2 DCRX_PHY_MACRO_CNTL_RESERVED 0 31 mmDCRX_PHY_MACRO_CNTL_RESERVED274 0 0x2d18 1 0 2 DCRX_PHY_MACRO_CNTL_RESERVED 0 31 mmDCRX_PHY_MACRO_CNTL_RESERVED275 0 0x2d19 1 0 2 DCRX_PHY_MACRO_CNTL_RESERVED 0 31 mmDCRX_PHY_MACRO_CNTL_RESERVED276 0 0x2d1a 1 0 2 DCRX_PHY_MACRO_CNTL_RESERVED 0 31 mmDCRX_PHY_MACRO_CNTL_RESERVED277 0 0x2d1b 1 0 2 DCRX_PHY_MACRO_CNTL_RESERVED 0 31 mmDCRX_PHY_MACRO_CNTL_RESERVED278 0 0x2d1c 1 0 2 DCRX_PHY_MACRO_CNTL_RESERVED 0 31 mmDCRX_PHY_MACRO_CNTL_RESERVED279 0 0x2d1d 1 0 2 DCRX_PHY_MACRO_CNTL_RESERVED 0 31 mmDCRX_PHY_MACRO_CNTL_RESERVED280 0 0x2d1e 1 0 2 DCRX_PHY_MACRO_CNTL_RESERVED 0 31 mmDCRX_PHY_MACRO_CNTL_RESERVED281 0 0x2d1f 1 0 2 DCRX_PHY_MACRO_CNTL_RESERVED 0 31 mmDCRX_PHY_MACRO_CNTL_RESERVED282 0 0x2d20 1 0 2 DCRX_PHY_MACRO_CNTL_RESERVED 0 31 mmDCRX_PHY_MACRO_CNTL_RESERVED283 0 0x2d21 1 0 2 DCRX_PHY_MACRO_CNTL_RESERVED 0 31 mmDCRX_PHY_MACRO_CNTL_RESERVED284 0 0x2d22 1 0 2 DCRX_PHY_MACRO_CNTL_RESERVED 0 31 mmDCRX_PHY_MACRO_CNTL_RESERVED285 0 0x2d23 1 0 2 DCRX_PHY_MACRO_CNTL_RESERVED 0 31 mmDCRX_PHY_MACRO_CNTL_RESERVED286 0 0x2d24 1 0 2 DCRX_PHY_MACRO_CNTL_RESERVED 0 31 mmDCRX_PHY_MACRO_CNTL_RESERVED287 0 0x2d25 1 0 2 DCRX_PHY_MACRO_CNTL_RESERVED 0 31 mmDCRX_PHY_MACRO_CNTL_RESERVED288 0 0x2d26 1 0 2 DCRX_PHY_MACRO_CNTL_RESERVED 0 31 mmDCRX_PHY_MACRO_CNTL_RESERVED289 0 0x2d27 1 0 2 DCRX_PHY_MACRO_CNTL_RESERVED 0 31 mmDCRX_PHY_MACRO_CNTL_RESERVED290 0 0x2d28 1 0 2 DCRX_PHY_MACRO_CNTL_RESERVED 0 31 mmDCRX_PHY_MACRO_CNTL_RESERVED291 0 0x2d29 1 0 2 DCRX_PHY_MACRO_CNTL_RESERVED 0 31 mmDCRX_PHY_MACRO_CNTL_RESERVED292 0 0x2d2a 1 0 2 DCRX_PHY_MACRO_CNTL_RESERVED 0 31 mmDCRX_PHY_MACRO_CNTL_RESERVED293 0 0x2d2b 1 0 2 DCRX_PHY_MACRO_CNTL_RESERVED 0 31 mmDCRX_PHY_MACRO_CNTL_RESERVED294 0 0x2d2c 1 0 2 DCRX_PHY_MACRO_CNTL_RESERVED 0 31 mmDCRX_PHY_MACRO_CNTL_RESERVED295 0 0x2d2d 1 0 2 DCRX_PHY_MACRO_CNTL_RESERVED 0 31 mmDCRX_PHY_MACRO_CNTL_RESERVED296 0 0x2d2e 1 0 2 DCRX_PHY_MACRO_CNTL_RESERVED 0 31 mmDCRX_PHY_MACRO_CNTL_RESERVED297 0 0x2d2f 1 0 2 DCRX_PHY_MACRO_CNTL_RESERVED 0 31 mmDCRX_PHY_MACRO_CNTL_RESERVED298 0 0x2d30 1 0 2 DCRX_PHY_MACRO_CNTL_RESERVED 0 31 mmDCRX_PHY_MACRO_CNTL_RESERVED299 0 0x2d31 1 0 2 DCRX_PHY_MACRO_CNTL_RESERVED 0 31 mmDCRX_PHY_MACRO_CNTL_RESERVED300 0 0x2d32 1 0 2 DCRX_PHY_MACRO_CNTL_RESERVED 0 31 mmDCRX_PHY_MACRO_CNTL_RESERVED301 0 0x2d33 1 0 2 DCRX_PHY_MACRO_CNTL_RESERVED 0 31 mmDCRX_PHY_MACRO_CNTL_RESERVED302 0 0x2d34 1 0 2 DCRX_PHY_MACRO_CNTL_RESERVED 0 31 mmDCRX_PHY_MACRO_CNTL_RESERVED303 0 0x2d35 1 0 2 DCRX_PHY_MACRO_CNTL_RESERVED 0 31 mmDCRX_PHY_MACRO_CNTL_RESERVED304 0 0x2d36 1 0 2 DCRX_PHY_MACRO_CNTL_RESERVED 0 31 mmDCRX_PHY_MACRO_CNTL_RESERVED305 0 0x2d37 1 0 2 DCRX_PHY_MACRO_CNTL_RESERVED 0 31 mmDCRX_PHY_MACRO_CNTL_RESERVED306 0 0x2d38 1 0 2 DCRX_PHY_MACRO_CNTL_RESERVED 0 31 mmDCRX_PHY_MACRO_CNTL_RESERVED307 0 0x2d39 1 0 2 DCRX_PHY_MACRO_CNTL_RESERVED 0 31 mmDCRX_PHY_MACRO_CNTL_RESERVED308 0 0x2d3a 1 0 2 DCRX_PHY_MACRO_CNTL_RESERVED 0 31 mmDCRX_PHY_MACRO_CNTL_RESERVED309 0 0x2d3b 1 0 2 DCRX_PHY_MACRO_CNTL_RESERVED 0 31 mmDCRX_PHY_MACRO_CNTL_RESERVED310 0 0x2d3c 1 0 2 DCRX_PHY_MACRO_CNTL_RESERVED 0 31 mmDCRX_PHY_MACRO_CNTL_RESERVED311 0 0x2d3d 1 0 2 DCRX_PHY_MACRO_CNTL_RESERVED 0 31 mmDCRX_PHY_MACRO_CNTL_RESERVED312 0 0x2d3e 1 0 2 DCRX_PHY_MACRO_CNTL_RESERVED 0 31 mmDCRX_PHY_MACRO_CNTL_RESERVED313 0 0x2d3f 1 0 2 DCRX_PHY_MACRO_CNTL_RESERVED 0 31 mmDCRX_PHY_MACRO_CNTL_RESERVED314 0 0x2d40 1 0 2 DCRX_PHY_MACRO_CNTL_RESERVED 0 31 mmDCRX_PHY_MACRO_CNTL_RESERVED315 0 0x2d41 1 0 2 DCRX_PHY_MACRO_CNTL_RESERVED 0 31 mmDCRX_PHY_MACRO_CNTL_RESERVED316 0 0x2d42 1 0 2 DCRX_PHY_MACRO_CNTL_RESERVED 0 31 mmDCRX_PHY_MACRO_CNTL_RESERVED317 0 0x2d43 1 0 2 DCRX_PHY_MACRO_CNTL_RESERVED 0 31 mmDCRX_PHY_MACRO_CNTL_RESERVED318 0 0x2d44 1 0 2 DCRX_PHY_MACRO_CNTL_RESERVED 0 31 mmDCRX_PHY_MACRO_CNTL_RESERVED319 0 0x2d45 1 0 2 DCRX_PHY_MACRO_CNTL_RESERVED 0 31 mmDCRX_PHY_MACRO_CNTL_RESERVED320 0 0x2d46 1 0 2 DCRX_PHY_MACRO_CNTL_RESERVED 0 31 mmDCRX_PHY_MACRO_CNTL_RESERVED321 0 0x2d47 1 0 2 DCRX_PHY_MACRO_CNTL_RESERVED 0 31 mmDCRX_PHY_MACRO_CNTL_RESERVED322 0 0x2d48 1 0 2 DCRX_PHY_MACRO_CNTL_RESERVED 0 31 mmDCRX_PHY_MACRO_CNTL_RESERVED323 0 0x2d49 1 0 2 DCRX_PHY_MACRO_CNTL_RESERVED 0 31 mmDCRX_PHY_MACRO_CNTL_RESERVED324 0 0x2d4a 1 0 2 DCRX_PHY_MACRO_CNTL_RESERVED 0 31 mmDCRX_PHY_MACRO_CNTL_RESERVED325 0 0x2d4b 1 0 2 DCRX_PHY_MACRO_CNTL_RESERVED 0 31 mmDCRX_PHY_MACRO_CNTL_RESERVED326 0 0x2d4c 1 0 2 DCRX_PHY_MACRO_CNTL_RESERVED 0 31 mmDCRX_PHY_MACRO_CNTL_RESERVED327 0 0x2d4d 1 0 2 DCRX_PHY_MACRO_CNTL_RESERVED 0 31 mmDCRX_PHY_MACRO_CNTL_RESERVED328 0 0x2d4e 1 0 2 DCRX_PHY_MACRO_CNTL_RESERVED 0 31 mmDCRX_PHY_MACRO_CNTL_RESERVED329 0 0x2d4f 1 0 2 DCRX_PHY_MACRO_CNTL_RESERVED 0 31 mmDCRX_PHY_MACRO_CNTL_RESERVED330 0 0x2d50 1 0 2 DCRX_PHY_MACRO_CNTL_RESERVED 0 31 mmDCRX_PHY_MACRO_CNTL_RESERVED331 0 0x2d51 1 0 2 DCRX_PHY_MACRO_CNTL_RESERVED 0 31 mmDCRX_PHY_MACRO_CNTL_RESERVED332 0 0x2d52 1 0 2 DCRX_PHY_MACRO_CNTL_RESERVED 0 31 mmDCRX_PHY_MACRO_CNTL_RESERVED333 0 0x2d53 1 0 2 DCRX_PHY_MACRO_CNTL_RESERVED 0 31 mmDCRX_PHY_MACRO_CNTL_RESERVED334 0 0x2d54 1 0 2 DCRX_PHY_MACRO_CNTL_RESERVED 0 31 mmDCRX_PHY_MACRO_CNTL_RESERVED335 0 0x2d55 1 0 2 DCRX_PHY_MACRO_CNTL_RESERVED 0 31 mmDCRX_PHY_MACRO_CNTL_RESERVED336 0 0x2d56 1 0 2 DCRX_PHY_MACRO_CNTL_RESERVED 0 31 mmDCRX_PHY_MACRO_CNTL_RESERVED337 0 0x2d57 1 0 2 DCRX_PHY_MACRO_CNTL_RESERVED 0 31 mmDCRX_PHY_MACRO_CNTL_RESERVED338 0 0x2d58 1 0 2 DCRX_PHY_MACRO_CNTL_RESERVED 0 31 mmDCRX_PHY_MACRO_CNTL_RESERVED339 0 0x2d59 1 0 2 DCRX_PHY_MACRO_CNTL_RESERVED 0 31 mmDCRX_PHY_MACRO_CNTL_RESERVED340 0 0x2d5a 1 0 2 DCRX_PHY_MACRO_CNTL_RESERVED 0 31 mmDCRX_PHY_MACRO_CNTL_RESERVED341 0 0x2d5b 1 0 2 DCRX_PHY_MACRO_CNTL_RESERVED 0 31 mmDCRX_PHY_MACRO_CNTL_RESERVED342 0 0x2d5c 1 0 2 DCRX_PHY_MACRO_CNTL_RESERVED 0 31 mmDCRX_PHY_MACRO_CNTL_RESERVED343 0 0x2d5d 1 0 2 DCRX_PHY_MACRO_CNTL_RESERVED 0 31 mmDCRX_PHY_MACRO_CNTL_RESERVED344 0 0x2d5e 1 0 2 DCRX_PHY_MACRO_CNTL_RESERVED 0 31 mmDCRX_PHY_MACRO_CNTL_RESERVED345 0 0x2d5f 1 0 2 DCRX_PHY_MACRO_CNTL_RESERVED 0 31 mmDCRX_PHY_MACRO_CNTL_RESERVED346 0 0x2d60 1 0 2 DCRX_PHY_MACRO_CNTL_RESERVED 0 31 mmDCRX_PHY_MACRO_CNTL_RESERVED347 0 0x2d61 1 0 2 DCRX_PHY_MACRO_CNTL_RESERVED 0 31 mmDCRX_PHY_MACRO_CNTL_RESERVED348 0 0x2d62 1 0 2 DCRX_PHY_MACRO_CNTL_RESERVED 0 31 mmDCRX_PHY_MACRO_CNTL_RESERVED349 0 0x2d63 1 0 2 DCRX_PHY_MACRO_CNTL_RESERVED 0 31 mmDCRX_PHY_MACRO_CNTL_RESERVED350 0 0x2d64 1 0 2 DCRX_PHY_MACRO_CNTL_RESERVED 0 31 mmDCRX_PHY_MACRO_CNTL_RESERVED351 0 0x2d65 1 0 2 DCRX_PHY_MACRO_CNTL_RESERVED 0 31 mmDCRX_PHY_MACRO_CNTL_RESERVED352 0 0x2d66 1 0 2 DCRX_PHY_MACRO_CNTL_RESERVED 0 31 mmDCRX_PHY_MACRO_CNTL_RESERVED353 0 0x2d67 1 0 2 DCRX_PHY_MACRO_CNTL_RESERVED 0 31 mmDCRX_PHY_MACRO_CNTL_RESERVED354 0 0x2d68 1 0 2 DCRX_PHY_MACRO_CNTL_RESERVED 0 31 mmDCRX_PHY_MACRO_CNTL_RESERVED355 0 0x2d69 1 0 2 DCRX_PHY_MACRO_CNTL_RESERVED 0 31 mmDCRX_PHY_MACRO_CNTL_RESERVED356 0 0x2d6a 1 0 2 DCRX_PHY_MACRO_CNTL_RESERVED 0 31 mmDCRX_PHY_MACRO_CNTL_RESERVED357 0 0x2d6b 1 0 2 DCRX_PHY_MACRO_CNTL_RESERVED 0 31 mmDCRX_PHY_MACRO_CNTL_RESERVED358 0 0x2d6c 1 0 2 DCRX_PHY_MACRO_CNTL_RESERVED 0 31 mmDCRX_PHY_MACRO_CNTL_RESERVED359 0 0x2d6d 1 0 2 DCRX_PHY_MACRO_CNTL_RESERVED 0 31 mmDCRX_PHY_MACRO_CNTL_RESERVED360 0 0x2d6e 1 0 2 DCRX_PHY_MACRO_CNTL_RESERVED 0 31 mmDCRX_PHY_MACRO_CNTL_RESERVED361 0 0x2d6f 1 0 2 DCRX_PHY_MACRO_CNTL_RESERVED 0 31 mmDCRX_PHY_MACRO_CNTL_RESERVED362 0 0x2d70 1 0 2 DCRX_PHY_MACRO_CNTL_RESERVED 0 31 mmDCRX_PHY_MACRO_CNTL_RESERVED363 0 0x2d71 1 0 2 DCRX_PHY_MACRO_CNTL_RESERVED 0 31 mmDCRX_PHY_MACRO_CNTL_RESERVED364 0 0x2d72 1 0 2 DCRX_PHY_MACRO_CNTL_RESERVED 0 31 mmDCRX_PHY_MACRO_CNTL_RESERVED365 0 0x2d73 1 0 2 DCRX_PHY_MACRO_CNTL_RESERVED 0 31 mmDCRX_PHY_MACRO_CNTL_RESERVED366 0 0x2d74 1 0 2 DCRX_PHY_MACRO_CNTL_RESERVED 0 31 mmDCRX_PHY_MACRO_CNTL_RESERVED367 0 0x2d75 1 0 2 DCRX_PHY_MACRO_CNTL_RESERVED 0 31 mmDCRX_PHY_MACRO_CNTL_RESERVED368 0 0x2d76 1 0 2 DCRX_PHY_MACRO_CNTL_RESERVED 0 31 mmDCRX_PHY_MACRO_CNTL_RESERVED369 0 0x2d77 1 0 2 DCRX_PHY_MACRO_CNTL_RESERVED 0 31 mmDCRX_PHY_MACRO_CNTL_RESERVED370 0 0x2d78 1 0 2 DCRX_PHY_MACRO_CNTL_RESERVED 0 31 mmDCRX_PHY_MACRO_CNTL_RESERVED371 0 0x2d79 1 0 2 DCRX_PHY_MACRO_CNTL_RESERVED 0 31 mmDCRX_PHY_MACRO_CNTL_RESERVED372 0 0x2d7a 1 0 2 DCRX_PHY_MACRO_CNTL_RESERVED 0 31 mmDCRX_PHY_MACRO_CNTL_RESERVED373 0 0x2d7b 1 0 2 DCRX_PHY_MACRO_CNTL_RESERVED 0 31 mmDCRX_PHY_MACRO_CNTL_RESERVED374 0 0x2d7c 1 0 2 DCRX_PHY_MACRO_CNTL_RESERVED 0 31 mmDCRX_PHY_MACRO_CNTL_RESERVED375 0 0x2d7d 1 0 2 DCRX_PHY_MACRO_CNTL_RESERVED 0 31 mmDCRX_PHY_MACRO_CNTL_RESERVED376 0 0x2d7e 1 0 2 DCRX_PHY_MACRO_CNTL_RESERVED 0 31 mmDCRX_PHY_MACRO_CNTL_RESERVED377 0 0x2d7f 1 0 2 DCRX_PHY_MACRO_CNTL_RESERVED 0 31 mmDCRX_PHY_MACRO_CNTL_RESERVED378 0 0x2d80 1 0 2 DCRX_PHY_MACRO_CNTL_RESERVED 0 31 mmDCRX_PHY_MACRO_CNTL_RESERVED379 0 0x2d81 1 0 2 DCRX_PHY_MACRO_CNTL_RESERVED 0 31 mmI2S0_CNTL 0 0x2d82 7 0 2 I2S0_WORD_SIZE 0 0 I2S0_SAMPLE_ALIGNMENT 4 4 I2S0_SAMPLE_BIT_ORDER 8 8 I2S0_LRCLK_POLARITY 12 12 I2S0_WORD_ALIGNMENT 16 16 I2S0_ENABLE 26 26 I2S0_FIFO_START_ADDR 30 30 mmSPDIF0_CNTL 0 0x2d83 2 0 2 SPDIF0_EN 0 0 SPDIF0_FIFO_START_ADDR 4 4 mmI2S1_CNTL 0 0x2d84 7 0 2 I2S1_WORD_SIZE 0 0 I2S1_SAMPLE_ALIGNMENT 4 4 I2S1_SAMPLE_BIT_ORDER 8 8 I2S1_LRCLK_POLARITY 12 12 I2S1_WORD_ALIGNMENT 16 16 I2S1_ENABLE 26 26 I2S1_FIFO_START_ADDR 30 30 mmSPDIF1_CNTL 0 0x2d85 3 0 2 SPDIF1_EN 0 0 SPDIF1_FIFO_START_ADDR 4 4 SPDIF1_INVERT_EN 8 8 mmI2S0_STATUS 0 0x2d86 4 0 2 STREAM0_AUDIO_ENABLE 0 0 STREAM0_IDLE 1 1 I2S0_DATA_RDY 2 2 I2S0_SAMPLE_RATE 3 5 mmI2S1_STATUS 0 0x2d87 4 0 2 STREAM1_AUDIO_ENABLE 0 0 STREAM1_IDLE 1 1 I2S1_DATA_RDY 2 2 I2S1_SAMPLE_RATE 3 5 mmI2S0_CRC_TEST_CNTL 0 0x2d8a 4 0 2 I2S0_CRC_TEST_EN 0 0 I2S0_CRC_SOFT_RESET 1 1 I2S0_CRC_TEST_CONT_EN 4 4 I2S0_CRC_TEST_NUMBER_OF_SAMPLES 8 31 mmI2S0_CRC_TEST_DATA_01 0 0x2d8b 2 0 2 I2S0_CRC_TEST_DATA0 0 15 I2S0_CRC_TEST_DATA1 16 31 mmI2S0_CRC_TEST_DATA_23 0 0x2d8c 2 0 2 I2S0_CRC_TEST_DATA2 0 15 I2S0_CRC_TEST_DATA3 16 31 mmI2S1_CRC_TEST_CNTL 0 0x2d8d 4 0 2 I2S1_CRC_TEST_EN 0 0 I2S1_CRC_SOFT_RESET 1 1 I2S1_CRC_TEST_CONT_EN 4 4 I2S1_CRC_TEST_NUMBER_OF_SAMPLES 8 31 mmI2S1_CRC_TEST_DATA_0 0 0x2d8e 1 0 2 I2S1_CRC_TEST_DATA0 0 15 mmSPDIF0_CRC_TEST_CNTL 0 0x2d8f 4 0 2 SPDIF0_CRC_TEST_EN 0 0 SPDIF0_CRC_SOFT_RESET 1 1 SPDIF0_CRC_TEST_CONT_EN 4 4 SPDIF0_CRC_TEST_NUMBER_OF_SAMPLES 8 31 mmSPDIF0_CRC_TEST_DATA_0 0 0x2d90 1 0 2 SPDIF0_CRC_TEST_DATA0 0 15 mmSPDIF1_CRC_TEST_CNTL 0 0x2d91 4 0 2 SPDIF1_CRC_TEST_EN 0 0 SPDIF1_CRC_SOFT_RESET 1 1 SPDIF1_CRC_TEST_CONT_EN 4 4 SPDIF1_CRC_TEST_NUMBER_OF_SAMPLES 8 31 mmSPDIF1_CRC_TEST_DATA 0 0x2d92 1 0 2 SPDIF1_CRC_TEST_DATA 0 15 mmCRC_I2S_CONT_REPEAT_NUM 0 0x2d93 2 0 2 I2S0_CRC_CONT_REPEAT_NUM 0 15 I2S1_CRC_CONT_REPEAT_NUM 16 31 mmCRC_SPDIF_CONT_REPEAT_NUM 0 0x2d94 2 0 2 SPDIF0_CRC_CONT_REPEAT_NUM 0 15 SPDIF1_CRC_CONT_REPEAT_NUM 16 31 mmZCAL_MACRO_CNTL_RESERVED0 0 0x2d96 1 0 2 ZCAL_MACRO_CNTL_RESERVED 0 31 mmZCAL_MACRO_CNTL_RESERVED1 0 0x2d97 1 0 2 ZCAL_MACRO_CNTL_RESERVED 0 31 mmZCAL_MACRO_CNTL_RESERVED2 0 0x2d98 1 0 2 ZCAL_MACRO_CNTL_RESERVED 0 31 mmZCAL_MACRO_CNTL_RESERVED3 0 0x2d99 1 0 2 ZCAL_MACRO_CNTL_RESERVED 0 31 mmZCAL_MACRO_CNTL_RESERVED4 0 0x2d9a 1 0 2 ZCAL_MACRO_CNTL_RESERVED 0 31 mmAZF0STREAM0_AZALIA_STREAM_INDEX 0 0x458 2 0 2 AZALIA_STREAM_REG_INDEX 0 7 AZALIA_STREAM_REG_WRITE_EN 8 8 mmAZF0STREAM0_AZALIA_STREAM_DATA 0 0x459 1 0 2 AZALIA_STREAM_REG_DATA 0 31 mmAZF0STREAM1_AZALIA_STREAM_INDEX 0 0x45a 2 0 2 AZALIA_STREAM_REG_INDEX 0 7 AZALIA_STREAM_REG_WRITE_EN 8 8 mmAZF0STREAM1_AZALIA_STREAM_DATA 0 0x45b 1 0 2 AZALIA_STREAM_REG_DATA 0 31 mmAZF0STREAM2_AZALIA_STREAM_INDEX 0 0x45c 2 0 2 AZALIA_STREAM_REG_INDEX 0 7 AZALIA_STREAM_REG_WRITE_EN 8 8 mmAZF0STREAM2_AZALIA_STREAM_DATA 0 0x45d 1 0 2 AZALIA_STREAM_REG_DATA 0 31 mmAZF0STREAM3_AZALIA_STREAM_INDEX 0 0x45e 2 0 2 AZALIA_STREAM_REG_INDEX 0 7 AZALIA_STREAM_REG_WRITE_EN 8 8 mmAZF0STREAM3_AZALIA_STREAM_DATA 0 0x45f 1 0 2 AZALIA_STREAM_REG_DATA 0 31 mmAZF0STREAM4_AZALIA_STREAM_INDEX 0 0x460 2 0 2 AZALIA_STREAM_REG_INDEX 0 7 AZALIA_STREAM_REG_WRITE_EN 8 8 mmAZF0STREAM4_AZALIA_STREAM_DATA 0 0x461 1 0 2 AZALIA_STREAM_REG_DATA 0 31 mmAZF0STREAM5_AZALIA_STREAM_INDEX 0 0x462 2 0 2 AZALIA_STREAM_REG_INDEX 0 7 AZALIA_STREAM_REG_WRITE_EN 8 8 mmAZF0STREAM5_AZALIA_STREAM_DATA 0 0x463 1 0 2 AZALIA_STREAM_REG_DATA 0 31 mmAZF0STREAM6_AZALIA_STREAM_INDEX 0 0x464 2 0 2 AZALIA_STREAM_REG_INDEX 0 7 AZALIA_STREAM_REG_WRITE_EN 8 8 mmAZF0STREAM6_AZALIA_STREAM_DATA 0 0x465 1 0 2 AZALIA_STREAM_REG_DATA 0 31 mmAZF0STREAM7_AZALIA_STREAM_INDEX 0 0x466 2 0 2 AZALIA_STREAM_REG_INDEX 0 7 AZALIA_STREAM_REG_WRITE_EN 8 8 mmAZF0STREAM7_AZALIA_STREAM_DATA 0 0x467 1 0 2 AZALIA_STREAM_REG_DATA 0 31 mmAZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX 0 0x480 1 0 2 AZALIA_ENDPOINT_REG_INDEX 0 13 mmAZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA 0 0x481 1 0 2 AZALIA_ENDPOINT_REG_DATA 0 31 mmAZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_INDEX 0 0x486 1 0 2 AZALIA_ENDPOINT_REG_INDEX 0 13 mmAZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_DATA 0 0x487 1 0 2 AZALIA_ENDPOINT_REG_DATA 0 31 mmAZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_INDEX 0 0x48c 1 0 2 AZALIA_ENDPOINT_REG_INDEX 0 13 mmAZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_DATA 0 0x48d 1 0 2 AZALIA_ENDPOINT_REG_DATA 0 31 mmAZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_INDEX 0 0x492 1 0 2 AZALIA_ENDPOINT_REG_INDEX 0 13 mmAZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_DATA 0 0x493 1 0 2 AZALIA_ENDPOINT_REG_DATA 0 31 mmAZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_INDEX 0 0x498 1 0 2 AZALIA_ENDPOINT_REG_INDEX 0 13 mmAZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_DATA 0 0x499 1 0 2 AZALIA_ENDPOINT_REG_DATA 0 31 mmAZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_INDEX 0 0x49e 1 0 2 AZALIA_ENDPOINT_REG_INDEX 0 13 mmAZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_DATA 0 0x49f 1 0 2 AZALIA_ENDPOINT_REG_DATA 0 31 mmAZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_INDEX 0 0x4a4 1 0 2 AZALIA_ENDPOINT_REG_INDEX 0 13 mmAZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_DATA 0 0x4a5 1 0 2 AZALIA_ENDPOINT_REG_DATA 0 31 mmAZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_INDEX 0 0x4aa 1 0 2 AZALIA_ENDPOINT_REG_INDEX 0 13 mmAZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_DATA 0 0x4ab 1 0 2 AZALIA_ENDPOINT_REG_DATA 0 31 mmAZF0STREAM8_AZALIA_STREAM_INDEX 0 0x520 2 0 2 AZALIA_STREAM_REG_INDEX 0 7 AZALIA_STREAM_REG_WRITE_EN 8 8 mmAZF0STREAM8_AZALIA_STREAM_DATA 0 0x521 1 0 2 AZALIA_STREAM_REG_DATA 0 31 mmAZF0STREAM9_AZALIA_STREAM_INDEX 0 0x522 2 0 2 AZALIA_STREAM_REG_INDEX 0 7 AZALIA_STREAM_REG_WRITE_EN 8 8 mmAZF0STREAM9_AZALIA_STREAM_DATA 0 0x523 1 0 2 AZALIA_STREAM_REG_DATA 0 31 mmAZF0STREAM10_AZALIA_STREAM_INDEX 0 0x524 2 0 2 AZALIA_STREAM_REG_INDEX 0 7 AZALIA_STREAM_REG_WRITE_EN 8 8 mmAZF0STREAM10_AZALIA_STREAM_DATA 0 0x525 1 0 2 AZALIA_STREAM_REG_DATA 0 31 mmAZF0STREAM11_AZALIA_STREAM_INDEX 0 0x526 2 0 2 AZALIA_STREAM_REG_INDEX 0 7 AZALIA_STREAM_REG_WRITE_EN 8 8 mmAZF0STREAM11_AZALIA_STREAM_DATA 0 0x527 1 0 2 AZALIA_STREAM_REG_DATA 0 31 mmAZF0STREAM12_AZALIA_STREAM_INDEX 0 0x528 2 0 2 AZALIA_STREAM_REG_INDEX 0 7 AZALIA_STREAM_REG_WRITE_EN 8 8 mmAZF0STREAM12_AZALIA_STREAM_DATA 0 0x529 1 0 2 AZALIA_STREAM_REG_DATA 0 31 mmAZF0STREAM13_AZALIA_STREAM_INDEX 0 0x52a 2 0 2 AZALIA_STREAM_REG_INDEX 0 7 AZALIA_STREAM_REG_WRITE_EN 8 8 mmAZF0STREAM13_AZALIA_STREAM_DATA 0 0x52b 1 0 2 AZALIA_STREAM_REG_DATA 0 31 mmAZF0STREAM14_AZALIA_STREAM_INDEX 0 0x52c 2 0 2 AZALIA_STREAM_REG_INDEX 0 7 AZALIA_STREAM_REG_WRITE_EN 8 8 mmAZF0STREAM14_AZALIA_STREAM_DATA 0 0x52d 1 0 2 AZALIA_STREAM_REG_DATA 0 31 mmAZF0STREAM15_AZALIA_STREAM_INDEX 0 0x52e 2 0 2 AZALIA_STREAM_REG_INDEX 0 7 AZALIA_STREAM_REG_WRITE_EN 8 8 mmAZF0STREAM15_AZALIA_STREAM_DATA 0 0x52f 1 0 2 AZALIA_STREAM_REG_DATA 0 31 mmAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0 0x534 1 0 2 AZALIA_INPUT_ENDPOINT_REG_INDEX 0 13 mmAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0 0x535 1 0 2 AZALIA_INPUT_ENDPOINT_REG_DATA 0 31 mmAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0 0x538 1 0 2 AZALIA_INPUT_ENDPOINT_REG_INDEX 0 13 mmAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0 0x539 1 0 2 AZALIA_INPUT_ENDPOINT_REG_DATA 0 31 mmAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0 0x53c 1 0 2 AZALIA_INPUT_ENDPOINT_REG_INDEX 0 13 mmAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0 0x53d 1 0 2 AZALIA_INPUT_ENDPOINT_REG_DATA 0 31 mmAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0 0x540 1 0 2 AZALIA_INPUT_ENDPOINT_REG_INDEX 0 13 mmAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0 0x541 1 0 2 AZALIA_INPUT_ENDPOINT_REG_DATA 0 31 mmAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0 0x544 1 0 2 AZALIA_INPUT_ENDPOINT_REG_INDEX 0 13 mmAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0 0x545 1 0 2 AZALIA_INPUT_ENDPOINT_REG_DATA 0 31 mmAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0 0x548 1 0 2 AZALIA_INPUT_ENDPOINT_REG_INDEX 0 13 mmAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0 0x549 1 0 2 AZALIA_INPUT_ENDPOINT_REG_DATA 0 31 mmAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0 0x54c 1 0 2 AZALIA_INPUT_ENDPOINT_REG_INDEX 0 13 mmAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0 0x54d 1 0 2 AZALIA_INPUT_ENDPOINT_REG_DATA 0 31 mmAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0 0x550 1 0 2 AZALIA_INPUT_ENDPOINT_REG_INDEX 0 13 mmAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0 0x551 1 0 2 AZALIA_INPUT_ENDPOINT_REG_DATA 0 31 mmDCP0_GRPH_ENABLE 0 0x55a 2 0 2 GRPH_ENABLE 0 0 GRPH_KEYER_ALPHA_SEL 1 1 mmDCP0_GRPH_CONTROL 0 0x55b 12 0 2 GRPH_DEPTH 0 1 GRPH_SE_ENABLE 2 2 GRPH_Z 4 5 GRPH_DIM_TYPE 6 7 GRPH_FORMAT 8 10 GRPH_NUM_BANKS 12 14 GRPH_ADDRESS_TRANSLATION_ENABLE 16 16 GRPH_PRIVILEGED_ACCESS_ENABLE 17 17 GRPH_NUM_SHADER_ENGINES 18 19 GRPH_SW_MODE 20 24 GRPH_NUM_PIPES 28 30 GRPH_COLOR_EXPANSION_MODE 31 31 mmDCP0_GRPH_LUT_10BIT_BYPASS 0 0x55c 2 0 2 GRPH_LUT_10BIT_BYPASS_EN 8 8 GRPH_LUT_10BIT_BYPASS_DBL_BUF_EN 16 16 mmDCP0_GRPH_SWAP_CNTL 0 0x55d 5 0 2 GRPH_ENDIAN_SWAP 0 1 GRPH_RED_CROSSBAR 4 5 GRPH_GREEN_CROSSBAR 6 7 GRPH_BLUE_CROSSBAR 8 9 GRPH_ALPHA_CROSSBAR 10 11 mmDCP0_GRPH_PRIMARY_SURFACE_ADDRESS 0 0x55e 2 0 2 GRPH_PRIMARY_DFQ_ENABLE 0 0 GRPH_PRIMARY_SURFACE_ADDRESS 8 31 mmDCP0_GRPH_SECONDARY_SURFACE_ADDRESS 0 0x55f 2 0 2 GRPH_SECONDARY_DFQ_ENABLE 0 0 GRPH_SECONDARY_SURFACE_ADDRESS 8 31 mmDCP0_GRPH_PITCH 0 0x560 1 0 2 GRPH_PITCH 0 14 mmDCP0_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH 0 0x561 1 0 2 GRPH_PRIMARY_SURFACE_ADDRESS_HIGH 0 7 mmDCP0_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH 0 0x562 1 0 2 GRPH_SECONDARY_SURFACE_ADDRESS_HIGH 0 7 mmDCP0_GRPH_SURFACE_OFFSET_X 0 0x563 1 0 2 GRPH_SURFACE_OFFSET_X 0 13 mmDCP0_GRPH_SURFACE_OFFSET_Y 0 0x564 1 0 2 GRPH_SURFACE_OFFSET_Y 0 13 mmDCP0_GRPH_X_START 0 0x565 1 0 2 GRPH_X_START 0 13 mmDCP0_GRPH_Y_START 0 0x566 1 0 2 GRPH_Y_START 0 13 mmDCP0_GRPH_X_END 0 0x567 1 0 2 GRPH_X_END 0 14 mmDCP0_GRPH_Y_END 0 0x568 1 0 2 GRPH_Y_END 0 14 mmDCP0_INPUT_GAMMA_CONTROL 0 0x569 1 0 2 GRPH_INPUT_GAMMA_MODE 0 0 mmDCP0_GRPH_UPDATE 0 0x56a 11 0 2 GRPH_MODE_UPDATE_PENDING 0 0 GRPH_MODE_UPDATE_TAKEN 1 1 GRPH_SURFACE_UPDATE_PENDING 2 2 GRPH_SURFACE_UPDATE_TAKEN 3 3 GRPH_XDMA_FLIP_TYPE_CLEAR 8 8 GRPH_XDMA_DRR_MODE_ENABLE 9 9 GRPH_XDMA_MULTIFLIP_ENABLE 10 10 GRPH_UPDATE_LOCK 16 16 GRPH_SURFACE_IGNORE_UPDATE_LOCK 20 20 GRPH_MODE_DISABLE_MULTIPLE_UPDATE 24 24 GRPH_SURFACE_DISABLE_MULTIPLE_UPDATE 28 28 mmDCP0_GRPH_FLIP_CONTROL 0 0x56b 4 0 2 GRPH_SURFACE_UPDATE_H_RETRACE_EN 0 0 GRPH_XDMA_SUPER_AA_EN 1 1 GRPH_SURFACE_UPDATE_IMMEDIATE_EN 4 4 GRPH_SURFACE_UPDATE_PENDING_MODE 5 5 mmDCP0_GRPH_SURFACE_ADDRESS_INUSE 0 0x56c 1 0 2 GRPH_SURFACE_ADDRESS_INUSE 8 31 mmDCP0_GRPH_DFQ_CONTROL 0 0x56d 3 0 2 GRPH_DFQ_RESET 0 0 GRPH_DFQ_SIZE 4 6 GRPH_DFQ_MIN_FREE_ENTRIES 8 10 mmDCP0_GRPH_DFQ_STATUS 0 0x56e 4 0 2 GRPH_PRIMARY_DFQ_NUM_ENTRIES 0 3 GRPH_SECONDARY_DFQ_NUM_ENTRIES 4 7 GRPH_DFQ_RESET_FLAG 8 8 GRPH_DFQ_RESET_ACK 9 9 mmDCP0_GRPH_INTERRUPT_STATUS 0 0x56f 2 0 2 GRPH_PFLIP_INT_OCCURRED 0 0 GRPH_PFLIP_INT_CLEAR 8 8 mmDCP0_GRPH_INTERRUPT_CONTROL 0 0x570 2 0 2 GRPH_PFLIP_INT_MASK 0 0 GRPH_PFLIP_INT_TYPE 8 8 mmDCP0_GRPH_SURFACE_ADDRESS_HIGH_INUSE 0 0x571 1 0 2 GRPH_SURFACE_ADDRESS_HIGH_INUSE 0 7 mmDCP0_GRPH_COMPRESS_SURFACE_ADDRESS 0 0x572 1 0 2 GRPH_COMPRESS_SURFACE_ADDRESS 8 31 mmDCP0_GRPH_COMPRESS_PITCH 0 0x573 1 0 2 GRPH_COMPRESS_PITCH 6 16 mmDCP0_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH 0 0x574 1 0 2 GRPH_COMPRESS_SURFACE_ADDRESS_HIGH 0 7 mmDCP0_GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT 0 0x575 1 0 2 GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT 0 7 mmDCP0_PRESCALE_GRPH_CONTROL 0 0x576 5 0 2 GRPH_PRESCALE_SELECT 0 0 GRPH_PRESCALE_R_SIGN 1 1 GRPH_PRESCALE_G_SIGN 2 2 GRPH_PRESCALE_B_SIGN 3 3 GRPH_PRESCALE_BYPASS 4 4 mmDCP0_PRESCALE_VALUES_GRPH_R 0 0x577 2 0 2 GRPH_PRESCALE_BIAS_R 0 15 GRPH_PRESCALE_SCALE_R 16 31 mmDCP0_PRESCALE_VALUES_GRPH_G 0 0x578 2 0 2 GRPH_PRESCALE_BIAS_G 0 15 GRPH_PRESCALE_SCALE_G 16 31 mmDCP0_PRESCALE_VALUES_GRPH_B 0 0x579 2 0 2 GRPH_PRESCALE_BIAS_B 0 15 GRPH_PRESCALE_SCALE_B 16 31 mmDCP0_INPUT_CSC_CONTROL 0 0x57a 1 0 2 INPUT_CSC_GRPH_MODE 0 1 mmDCP0_INPUT_CSC_C11_C12 0 0x57b 2 0 2 INPUT_CSC_C11 0 15 INPUT_CSC_C12 16 31 mmDCP0_INPUT_CSC_C13_C14 0 0x57c 2 0 2 INPUT_CSC_C13 0 15 INPUT_CSC_C14 16 31 mmDCP0_INPUT_CSC_C21_C22 0 0x57d 2 0 2 INPUT_CSC_C21 0 15 INPUT_CSC_C22 16 31 mmDCP0_INPUT_CSC_C23_C24 0 0x57e 2 0 2 INPUT_CSC_C23 0 15 INPUT_CSC_C24 16 31 mmDCP0_INPUT_CSC_C31_C32 0 0x57f 2 0 2 INPUT_CSC_C31 0 15 INPUT_CSC_C32 16 31 mmDCP0_INPUT_CSC_C33_C34 0 0x580 2 0 2 INPUT_CSC_C33 0 15 INPUT_CSC_C34 16 31 mmDCP0_OUTPUT_CSC_CONTROL 0 0x581 1 0 2 OUTPUT_CSC_GRPH_MODE 0 2 mmDCP0_OUTPUT_CSC_C11_C12 0 0x582 2 0 2 OUTPUT_CSC_C11 0 15 OUTPUT_CSC_C12 16 31 mmDCP0_OUTPUT_CSC_C13_C14 0 0x583 2 0 2 OUTPUT_CSC_C13 0 15 OUTPUT_CSC_C14 16 31 mmDCP0_OUTPUT_CSC_C21_C22 0 0x584 2 0 2 OUTPUT_CSC_C21 0 15 OUTPUT_CSC_C22 16 31 mmDCP0_OUTPUT_CSC_C23_C24 0 0x585 2 0 2 OUTPUT_CSC_C23 0 15 OUTPUT_CSC_C24 16 31 mmDCP0_OUTPUT_CSC_C31_C32 0 0x586 2 0 2 OUTPUT_CSC_C31 0 15 OUTPUT_CSC_C32 16 31 mmDCP0_OUTPUT_CSC_C33_C34 0 0x587 2 0 2 OUTPUT_CSC_C33 0 15 OUTPUT_CSC_C34 16 31 mmDCP0_COMM_MATRIXA_TRANS_C11_C12 0 0x588 2 0 2 COMM_MATRIXA_TRANS_C11 0 15 COMM_MATRIXA_TRANS_C12 16 31 mmDCP0_COMM_MATRIXA_TRANS_C13_C14 0 0x589 2 0 2 COMM_MATRIXA_TRANS_C13 0 15 COMM_MATRIXA_TRANS_C14 16 31 mmDCP0_COMM_MATRIXA_TRANS_C21_C22 0 0x58a 2 0 2 COMM_MATRIXA_TRANS_C21 0 15 COMM_MATRIXA_TRANS_C22 16 31 mmDCP0_COMM_MATRIXA_TRANS_C23_C24 0 0x58b 2 0 2 COMM_MATRIXA_TRANS_C23 0 15 COMM_MATRIXA_TRANS_C24 16 31 mmDCP0_COMM_MATRIXA_TRANS_C31_C32 0 0x58c 2 0 2 COMM_MATRIXA_TRANS_C31 0 15 COMM_MATRIXA_TRANS_C32 16 31 mmDCP0_COMM_MATRIXA_TRANS_C33_C34 0 0x58d 2 0 2 COMM_MATRIXA_TRANS_C33 0 15 COMM_MATRIXA_TRANS_C34 16 31 mmDCP0_COMM_MATRIXB_TRANS_C11_C12 0 0x58e 2 0 2 COMM_MATRIXB_TRANS_C11 0 15 COMM_MATRIXB_TRANS_C12 16 31 mmDCP0_COMM_MATRIXB_TRANS_C13_C14 0 0x58f 2 0 2 COMM_MATRIXB_TRANS_C13 0 15 COMM_MATRIXB_TRANS_C14 16 31 mmDCP0_COMM_MATRIXB_TRANS_C21_C22 0 0x590 2 0 2 COMM_MATRIXB_TRANS_C21 0 15 COMM_MATRIXB_TRANS_C22 16 31 mmDCP0_COMM_MATRIXB_TRANS_C23_C24 0 0x591 2 0 2 COMM_MATRIXB_TRANS_C23 0 15 COMM_MATRIXB_TRANS_C24 16 31 mmDCP0_COMM_MATRIXB_TRANS_C31_C32 0 0x592 2 0 2 COMM_MATRIXB_TRANS_C31 0 15 COMM_MATRIXB_TRANS_C32 16 31 mmDCP0_COMM_MATRIXB_TRANS_C33_C34 0 0x593 2 0 2 COMM_MATRIXB_TRANS_C33 0 15 COMM_MATRIXB_TRANS_C34 16 31 mmDCP0_DENORM_CONTROL 0 0x594 2 0 2 DENORM_MODE 0 2 DENORM_14BIT_OUT 4 4 mmDCP0_OUT_ROUND_CONTROL 0 0x595 1 0 2 OUT_ROUND_TRUNC_MODE 0 3 mmDCP0_OUT_CLAMP_CONTROL_R_CR 0 0x596 2 0 2 OUT_CLAMP_MAX_R_CR 0 13 OUT_CLAMP_MIN_R_CR 16 29 mmDCP0_OUT_CLAMP_CONTROL_G_Y 0 0x597 2 0 2 OUT_CLAMP_MAX_G_Y 0 13 OUT_CLAMP_MIN_G_Y 16 29 mmDCP0_OUT_CLAMP_CONTROL_B_CB 0 0x598 2 0 2 OUT_CLAMP_MAX_B_CB 0 13 OUT_CLAMP_MIN_B_CB 16 29 mmDCP0_KEY_CONTROL 0 0x599 1 0 2 KEY_MODE 1 2 mmDCP0_KEY_RANGE_ALPHA 0 0x59a 2 0 2 KEY_ALPHA_LOW 0 15 KEY_ALPHA_HIGH 16 31 mmDCP0_KEY_RANGE_RED 0 0x59b 2 0 2 KEY_RED_LOW 0 15 KEY_RED_HIGH 16 31 mmDCP0_KEY_RANGE_GREEN 0 0x59c 2 0 2 KEY_GREEN_LOW 0 15 KEY_GREEN_HIGH 16 31 mmDCP0_KEY_RANGE_BLUE 0 0x59d 2 0 2 KEY_BLUE_LOW 0 15 KEY_BLUE_HIGH 16 31 mmDCP0_DEGAMMA_CONTROL 0 0x59e 3 0 2 GRPH_DEGAMMA_MODE 0 1 CURSOR2_DEGAMMA_MODE 8 9 CURSOR_DEGAMMA_MODE 12 13 mmDCP0_GAMUT_REMAP_CONTROL 0 0x59f 1 0 2 GRPH_GAMUT_REMAP_MODE 0 1 mmDCP0_GAMUT_REMAP_C11_C12 0 0x5a0 2 0 2 GAMUT_REMAP_C11 0 15 GAMUT_REMAP_C12 16 31 mmDCP0_GAMUT_REMAP_C13_C14 0 0x5a1 2 0 2 GAMUT_REMAP_C13 0 15 GAMUT_REMAP_C14 16 31 mmDCP0_GAMUT_REMAP_C21_C22 0 0x5a2 2 0 2 GAMUT_REMAP_C21 0 15 GAMUT_REMAP_C22 16 31 mmDCP0_GAMUT_REMAP_C23_C24 0 0x5a3 2 0 2 GAMUT_REMAP_C23 0 15 GAMUT_REMAP_C24 16 31 mmDCP0_GAMUT_REMAP_C31_C32 0 0x5a4 2 0 2 GAMUT_REMAP_C31 0 15 GAMUT_REMAP_C32 16 31 mmDCP0_GAMUT_REMAP_C33_C34 0 0x5a5 2 0 2 GAMUT_REMAP_C33 0 15 GAMUT_REMAP_C34 16 31 mmDCP0_DCP_SPATIAL_DITHER_CNTL 0 0x5a6 6 0 2 DCP_SPATIAL_DITHER_EN 0 0 DCP_SPATIAL_DITHER_MODE 4 5 DCP_SPATIAL_DITHER_DEPTH 6 7 DCP_FRAME_RANDOM_ENABLE 8 8 DCP_RGB_RANDOM_ENABLE 9 9 DCP_HIGHPASS_RANDOM_ENABLE 10 10 mmDCP0_DCP_RANDOM_SEEDS 0 0x5a7 3 0 2 DCP_RAND_R_SEED 0 7 DCP_RAND_G_SEED 8 15 DCP_RAND_B_SEED 16 23 mmDCP0_DCP_FP_CONVERTED_FIELD 0 0x5a8 2 0 2 DCP_FP_CONVERTED_FIELD_DATA 0 17 DCP_FP_CONVERTED_FIELD_INDEX 20 26 mmDCP0_CUR_CONTROL 0 0x5a9 8 0 2 CURSOR_EN 0 0 CUR_INV_TRANS_CLAMP 4 4 CURSOR_MODE 8 9 CURSOR_MAX_OUTSTANDING_GROUP_NUM 11 11 CURSOR_BUSY_START_LINE_POSITION 12 15 CURSOR_2X_MAGNIFY 16 16 CURSOR_FORCE_MC_ON 20 20 CURSOR_URGENT_CONTROL 24 26 mmDCP0_CUR_SURFACE_ADDRESS 0 0x5aa 1 0 2 CURSOR_SURFACE_ADDRESS 0 31 mmDCP0_CUR_SIZE 0 0x5ab 2 0 2 CURSOR_HEIGHT 0 6 CURSOR_WIDTH 16 22 mmDCP0_CUR_SURFACE_ADDRESS_HIGH 0 0x5ac 1 0 2 CURSOR_SURFACE_ADDRESS_HIGH 0 7 mmDCP0_CUR_POSITION 0 0x5ad 2 0 2 CURSOR_Y_POSITION 0 13 CURSOR_X_POSITION 16 29 mmDCP0_CUR_HOT_SPOT 0 0x5ae 2 0 2 CURSOR_HOT_SPOT_Y 0 6 CURSOR_HOT_SPOT_X 16 22 mmDCP0_CUR_COLOR1 0 0x5af 3 0 2 CUR_COLOR1_BLUE 0 7 CUR_COLOR1_GREEN 8 15 CUR_COLOR1_RED 16 23 mmDCP0_CUR_COLOR2 0 0x5b0 3 0 2 CUR_COLOR2_BLUE 0 7 CUR_COLOR2_GREEN 8 15 CUR_COLOR2_RED 16 23 mmDCP0_CUR_UPDATE 0 0x5b1 5 0 2 CURSOR_UPDATE_PENDING 0 0 CURSOR_UPDATE_TAKEN 1 1 CURSOR_UPDATE_LOCK 16 16 CURSOR_DISABLE_MULTIPLE_UPDATE 24 24 CURSOR_UPDATE_STEREO_MODE 25 26 mmDCP0_CUR_REQUEST_FILTER_CNTL 0 0x5bb 1 0 2 CUR_REQUEST_FILTER_DIS 0 0 mmDCP0_CUR_STEREO_CONTROL 0 0x5bc 3 0 2 CURSOR_STEREO_EN 0 0 CURSOR_PRIMARY_OFFSET 4 13 CURSOR_SECONDARY_OFFSET 16 25 mmDCP0_DC_LUT_RW_MODE 0 0x5be 3 0 2 DC_LUT_RW_MODE 0 0 DC_LUT_ERROR 16 16 DC_LUT_ERROR_RST 17 17 mmDCP0_DC_LUT_RW_INDEX 0 0x5bf 1 0 2 DC_LUT_RW_INDEX 0 7 mmDCP0_DC_LUT_SEQ_COLOR 0 0x5c0 1 0 2 DC_LUT_SEQ_COLOR 0 15 mmDCP0_DC_LUT_PWL_DATA 0 0x5c1 2 0 2 DC_LUT_BASE 0 15 DC_LUT_DELTA 16 31 mmDCP0_DC_LUT_30_COLOR 0 0x5c2 3 0 2 DC_LUT_COLOR_10_BLUE 0 9 DC_LUT_COLOR_10_GREEN 10 19 DC_LUT_COLOR_10_RED 20 29 mmDCP0_DC_LUT_VGA_ACCESS_ENABLE 0 0x5c3 1 0 2 DC_LUT_VGA_ACCESS_ENABLE 0 0 mmDCP0_DC_LUT_WRITE_EN_MASK 0 0x5c4 1 0 2 DC_LUT_WRITE_EN_MASK 0 2 mmDCP0_DC_LUT_AUTOFILL 0 0x5c5 2 0 2 DC_LUT_AUTOFILL 0 0 DC_LUT_AUTOFILL_DONE 1 1 mmDCP0_DC_LUT_CONTROL 0 0x5c6 12 0 2 DC_LUT_INC_B 0 3 DC_LUT_DATA_B_SIGNED_EN 4 4 DC_LUT_DATA_B_FLOAT_POINT_EN 5 5 DC_LUT_DATA_B_FORMAT 6 7 DC_LUT_INC_G 8 11 DC_LUT_DATA_G_SIGNED_EN 12 12 DC_LUT_DATA_G_FLOAT_POINT_EN 13 13 DC_LUT_DATA_G_FORMAT 14 15 DC_LUT_INC_R 16 19 DC_LUT_DATA_R_SIGNED_EN 20 20 DC_LUT_DATA_R_FLOAT_POINT_EN 21 21 DC_LUT_DATA_R_FORMAT 22 23 mmDCP0_DC_LUT_BLACK_OFFSET_BLUE 0 0x5c7 1 0 2 DC_LUT_BLACK_OFFSET_BLUE 0 15 mmDCP0_DC_LUT_BLACK_OFFSET_GREEN 0 0x5c8 1 0 2 DC_LUT_BLACK_OFFSET_GREEN 0 15 mmDCP0_DC_LUT_BLACK_OFFSET_RED 0 0x5c9 1 0 2 DC_LUT_BLACK_OFFSET_RED 0 15 mmDCP0_DC_LUT_WHITE_OFFSET_BLUE 0 0x5ca 1 0 2 DC_LUT_WHITE_OFFSET_BLUE 0 15 mmDCP0_DC_LUT_WHITE_OFFSET_GREEN 0 0x5cb 1 0 2 DC_LUT_WHITE_OFFSET_GREEN 0 15 mmDCP0_DC_LUT_WHITE_OFFSET_RED 0 0x5cc 1 0 2 DC_LUT_WHITE_OFFSET_RED 0 15 mmDCP0_DCP_CRC_CONTROL 0 0x5cd 3 0 2 DCP_CRC_ENABLE 0 0 DCP_CRC_SOURCE_SEL 2 4 DCP_CRC_LINE_SEL 8 9 mmDCP0_DCP_CRC_MASK 0 0x5ce 1 0 2 DCP_CRC_MASK 0 31 mmDCP0_DCP_CRC_CURRENT 0 0x5cf 1 0 2 DCP_CRC_CURRENT 0 31 mmDCP0_DVMM_PTE_CONTROL 0 0x5d0 6 0 2 DVMM_USE_SINGLE_PTE 0 0 DVMM_PAGE_WIDTH 1 4 DVMM_PAGE_HEIGHT 5 8 DVMM_MIN_PTE_BEFORE_FLIP 9 18 DVMM_PTE_BUFFER_MODE0 20 20 DVMM_PTE_BUFFER_MODE1 21 21 mmDCP0_DCP_CRC_LAST 0 0x5d1 1 0 2 DCP_CRC_LAST 0 31 mmDCP0_DVMM_PTE_ARB_CONTROL 0 0x5d2 2 0 2 DVMM_PTE_REQ_PER_CHUNK 0 5 DVMM_MAX_PTE_REQ_OUTSTANDING 8 15 mmDCP0_GRPH_FLIP_RATE_CNTL 0 0x5d4 2 0 2 GRPH_FLIP_RATE 0 2 GRPH_FLIP_RATE_ENABLE 3 3 mmDCP0_DCP_GSL_CONTROL 0 0x5d5 11 0 2 DCP_GSL0_EN 0 0 DCP_GSL1_EN 1 1 DCP_GSL2_EN 2 2 DCP_GSL_HSYNC_FLIP_FORCE_DELAY 4 19 DCP_GSL_MASTER_EN 20 20 DCP_GSL_XDMA_GROUP 21 22 DCP_GSL_XDMA_GROUP_UNDERFLOW_EN 23 23 DCP_GSL_SYNC_SOURCE 24 25 DCP_GSL_USE_CHECKPOINT_WINDOW_IN_VSYNC 26 26 DCP_GSL_DELAY_SURFACE_UPDATE_PENDING 27 27 DCP_GSL_HSYNC_FLIP_CHECK_DELAY 28 31 mmDCP0_DCP_LB_DATA_GAP_BETWEEN_CHUNK 0 0x5d6 2 0 2 DCP_LB_GAP_BETWEEN_CHUNK_20BPP 0 3 DCP_LB_GAP_BETWEEN_CHUNK_30BPP 4 8 mmDCP0_GRPH_STEREOSYNC_FLIP 0 0x5dc 5 0 2 GRPH_STEREOSYNC_FLIP_EN 0 0 GRPH_STEREOSYNC_FLIP_MODE 8 9 GRPH_PRIMARY_SURFACE_PENDING 16 16 GRPH_SECONDARY_SURFACE_PENDING 17 17 GRPH_STEREOSYNC_SELECT_DISABLE 28 28 mmDCP0_HW_ROTATION 0 0x5de 1 0 2 GRPH_ROTATION_ANGLE 0 2 mmDCP0_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL 0 0x5df 3 0 2 GRPH_XDMA_CACHE_UNDERFLOW_CNT_EN 0 0 GRPH_XDMA_CACHE_UNDERFLOW_CNT_MODE 1 1 GRPH_XDMA_CACHE_UNDERFLOW_FRAME_CNT 4 16 mmDCP0_REGAMMA_CONTROL 0 0x5e0 1 0 2 GRPH_REGAMMA_MODE 0 2 mmDCP0_REGAMMA_LUT_INDEX 0 0x5e1 1 0 2 REGAMMA_LUT_INDEX 0 8 mmDCP0_REGAMMA_LUT_DATA 0 0x5e2 1 0 2 REGAMMA_LUT_DATA 0 18 mmDCP0_REGAMMA_LUT_WRITE_EN_MASK 0 0x5e3 1 0 2 REGAMMA_LUT_WRITE_EN_MASK 0 2 mmDCP0_REGAMMA_CNTLA_START_CNTL 0 0x5e4 2 0 2 REGAMMA_CNTLA_EXP_REGION_START 0 17 REGAMMA_CNTLA_EXP_REGION_START_SEGMENT 20 26 mmDCP0_REGAMMA_CNTLA_SLOPE_CNTL 0 0x5e5 1 0 2 REGAMMA_CNTLA_EXP_REGION_LINEAR_SLOPE 0 17 mmDCP0_REGAMMA_CNTLA_END_CNTL1 0 0x5e6 1 0 2 REGAMMA_CNTLA_EXP_REGION_END 0 15 mmDCP0_REGAMMA_CNTLA_END_CNTL2 0 0x5e7 2 0 2 REGAMMA_CNTLA_EXP_REGION_END_SLOPE 0 15 REGAMMA_CNTLA_EXP_REGION_END_BASE 16 31 mmDCP0_REGAMMA_CNTLA_REGION_0_1 0 0x5e8 4 0 2 REGAMMA_CNTLA_EXP_REGION0_LUT_OFFSET 0 8 REGAMMA_CNTLA_EXP_REGION0_NUM_SEGMENTS 12 14 REGAMMA_CNTLA_EXP_REGION1_LUT_OFFSET 16 24 REGAMMA_CNTLA_EXP_REGION1_NUM_SEGMENTS 28 30 mmDCP0_REGAMMA_CNTLA_REGION_2_3 0 0x5e9 4 0 2 REGAMMA_CNTLA_EXP_REGION2_LUT_OFFSET 0 8 REGAMMA_CNTLA_EXP_REGION2_NUM_SEGMENTS 12 14 REGAMMA_CNTLA_EXP_REGION3_LUT_OFFSET 16 24 REGAMMA_CNTLA_EXP_REGION3_NUM_SEGMENTS 28 30 mmDCP0_REGAMMA_CNTLA_REGION_4_5 0 0x5ea 4 0 2 REGAMMA_CNTLA_EXP_REGION4_LUT_OFFSET 0 8 REGAMMA_CNTLA_EXP_REGION4_NUM_SEGMENTS 12 14 REGAMMA_CNTLA_EXP_REGION5_LUT_OFFSET 16 24 REGAMMA_CNTLA_EXP_REGION5_NUM_SEGMENTS 28 30 mmDCP0_REGAMMA_CNTLA_REGION_6_7 0 0x5eb 4 0 2 REGAMMA_CNTLA_EXP_REGION6_LUT_OFFSET 0 8 REGAMMA_CNTLA_EXP_REGION6_NUM_SEGMENTS 12 14 REGAMMA_CNTLA_EXP_REGION7_LUT_OFFSET 16 24 REGAMMA_CNTLA_EXP_REGION7_NUM_SEGMENTS 28 30 mmDCP0_REGAMMA_CNTLA_REGION_8_9 0 0x5ec 4 0 2 REGAMMA_CNTLA_EXP_REGION8_LUT_OFFSET 0 8 REGAMMA_CNTLA_EXP_REGION8_NUM_SEGMENTS 12 14 REGAMMA_CNTLA_EXP_REGION9_LUT_OFFSET 16 24 REGAMMA_CNTLA_EXP_REGION9_NUM_SEGMENTS 28 30 mmDCP0_REGAMMA_CNTLA_REGION_10_11 0 0x5ed 4 0 2 REGAMMA_CNTLA_EXP_REGION10_LUT_OFFSET 0 8 REGAMMA_CNTLA_EXP_REGION10_NUM_SEGMENTS 12 14 REGAMMA_CNTLA_EXP_REGION11_LUT_OFFSET 16 24 REGAMMA_CNTLA_EXP_REGION11_NUM_SEGMENTS 28 30 mmDCP0_REGAMMA_CNTLA_REGION_12_13 0 0x5ee 4 0 2 REGAMMA_CNTLA_EXP_REGION12_LUT_OFFSET 0 8 REGAMMA_CNTLA_EXP_REGION12_NUM_SEGMENTS 12 14 REGAMMA_CNTLA_EXP_REGION13_LUT_OFFSET 16 24 REGAMMA_CNTLA_EXP_REGION13_NUM_SEGMENTS 28 30 mmDCP0_REGAMMA_CNTLA_REGION_14_15 0 0x5ef 4 0 2 REGAMMA_CNTLA_EXP_REGION14_LUT_OFFSET 0 8 REGAMMA_CNTLA_EXP_REGION14_NUM_SEGMENTS 12 14 REGAMMA_CNTLA_EXP_REGION15_LUT_OFFSET 16 24 REGAMMA_CNTLA_EXP_REGION15_NUM_SEGMENTS 28 30 mmDCP0_REGAMMA_CNTLB_START_CNTL 0 0x5f0 2 0 2 REGAMMA_CNTLB_EXP_REGION_START 0 17 REGAMMA_CNTLB_EXP_REGION_START_SEGMENT 20 26 mmDCP0_REGAMMA_CNTLB_SLOPE_CNTL 0 0x5f1 1 0 2 REGAMMA_CNTLB_EXP_REGION_LINEAR_SLOPE 0 17 mmDCP0_REGAMMA_CNTLB_END_CNTL1 0 0x5f2 1 0 2 REGAMMA_CNTLB_EXP_REGION_END 0 15 mmDCP0_REGAMMA_CNTLB_END_CNTL2 0 0x5f3 2 0 2 REGAMMA_CNTLB_EXP_REGION_END_SLOPE 0 15 REGAMMA_CNTLB_EXP_REGION_END_BASE 16 31 mmDCP0_REGAMMA_CNTLB_REGION_0_1 0 0x5f4 4 0 2 REGAMMA_CNTLB_EXP_REGION0_LUT_OFFSET 0 8 REGAMMA_CNTLB_EXP_REGION0_NUM_SEGMENTS 12 14 REGAMMA_CNTLB_EXP_REGION1_LUT_OFFSET 16 24 REGAMMA_CNTLB_EXP_REGION1_NUM_SEGMENTS 28 30 mmDCP0_REGAMMA_CNTLB_REGION_2_3 0 0x5f5 4 0 2 REGAMMA_CNTLB_EXP_REGION2_LUT_OFFSET 0 8 REGAMMA_CNTLB_EXP_REGION2_NUM_SEGMENTS 12 14 REGAMMA_CNTLB_EXP_REGION3_LUT_OFFSET 16 24 REGAMMA_CNTLB_EXP_REGION3_NUM_SEGMENTS 28 30 mmDCP0_REGAMMA_CNTLB_REGION_4_5 0 0x5f6 4 0 2 REGAMMA_CNTLB_EXP_REGION4_LUT_OFFSET 0 8 REGAMMA_CNTLB_EXP_REGION4_NUM_SEGMENTS 12 14 REGAMMA_CNTLB_EXP_REGION5_LUT_OFFSET 16 24 REGAMMA_CNTLB_EXP_REGION5_NUM_SEGMENTS 28 30 mmDCP0_REGAMMA_CNTLB_REGION_6_7 0 0x5f7 4 0 2 REGAMMA_CNTLB_EXP_REGION6_LUT_OFFSET 0 8 REGAMMA_CNTLB_EXP_REGION6_NUM_SEGMENTS 12 14 REGAMMA_CNTLB_EXP_REGION7_LUT_OFFSET 16 24 REGAMMA_CNTLB_EXP_REGION7_NUM_SEGMENTS 28 30 mmDCP0_REGAMMA_CNTLB_REGION_8_9 0 0x5f8 4 0 2 REGAMMA_CNTLB_EXP_REGION8_LUT_OFFSET 0 8 REGAMMA_CNTLB_EXP_REGION8_NUM_SEGMENTS 12 14 REGAMMA_CNTLB_EXP_REGION9_LUT_OFFSET 16 24 REGAMMA_CNTLB_EXP_REGION9_NUM_SEGMENTS 28 30 mmDCP0_REGAMMA_CNTLB_REGION_10_11 0 0x5f9 4 0 2 REGAMMA_CNTLB_EXP_REGION10_LUT_OFFSET 0 8 REGAMMA_CNTLB_EXP_REGION10_NUM_SEGMENTS 12 14 REGAMMA_CNTLB_EXP_REGION11_LUT_OFFSET 16 24 REGAMMA_CNTLB_EXP_REGION11_NUM_SEGMENTS 28 30 mmDCP0_REGAMMA_CNTLB_REGION_12_13 0 0x5fa 4 0 2 REGAMMA_CNTLB_EXP_REGION12_LUT_OFFSET 0 8 REGAMMA_CNTLB_EXP_REGION12_NUM_SEGMENTS 12 14 REGAMMA_CNTLB_EXP_REGION13_LUT_OFFSET 16 24 REGAMMA_CNTLB_EXP_REGION13_NUM_SEGMENTS 28 30 mmDCP0_REGAMMA_CNTLB_REGION_14_15 0 0x5fb 4 0 2 REGAMMA_CNTLB_EXP_REGION14_LUT_OFFSET 0 8 REGAMMA_CNTLB_EXP_REGION14_NUM_SEGMENTS 12 14 REGAMMA_CNTLB_EXP_REGION15_LUT_OFFSET 16 24 REGAMMA_CNTLB_EXP_REGION15_NUM_SEGMENTS 28 30 mmDCP0_ALPHA_CONTROL 0 0x5fc 2 0 2 ALPHA_ROUND_TRUNC_MODE 0 0 CURSOR_ALPHA_BLND_ENA 1 1 mmDCP0_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS 0 0x5fd 1 0 2 GRPH_XDMA_RECOVERY_SURFACE_ADDRESS 8 31 mmDCP0_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH 0 0x5fe 1 0 2 GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH 0 7 mmDCP0_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS 0 0x5ff 7 0 2 GRPH_XDMA_CACHE_UNDERFLOW_CNT 0 19 GRPH_XDMA_CACHE_UNDERFLOW_CNT_STATUS 24 24 GRPH_XDMA_CACHE_UNDERFLOW_FRAME_MASK 25 25 GRPH_XDMA_CACHE_UNDERFLOW_FRAME_ACK 26 26 GRPH_XDMA_CACHE_UNDERFLOW_INT 28 28 GRPH_XDMA_CACHE_UNDERFLOW_INT_MASK 29 29 GRPH_XDMA_CACHE_UNDERFLOW_INT_ACK 30 30 mmDCP0_GRPH_XDMA_FLIP_TIMEOUT 0 0x600 3 0 2 GRPH_XDMA_FLIP_TIMEOUT_STATUS 0 0 GRPH_XDMA_FLIP_TIMEOUT_MASK 1 1 GRPH_XDMA_FLIP_TIMEOUT_ACK 2 2 mmDCP0_GRPH_XDMA_FLIP_AVG_DELAY 0 0x601 2 0 2 GRPH_XDMA_FLIP_AVG_DELAY 0 15 GRPH_XDMA_FLIP_AVG_PERIOD 16 23 mmDCP0_GRPH_SURFACE_COUNTER_CONTROL 0 0x602 3 0 2 GRPH_SURFACE_COUNTER_EN 0 0 GRPH_SURFACE_COUNTER_EVENT_SELECT 1 4 GRPH_SURFACE_COUNTER_ERR_WRAP_OCCURED 9 9 mmDCP0_GRPH_SURFACE_COUNTER_OUTPUT 0 0x603 2 0 2 GRPH_SURFACE_COUNTER_MIN 0 15 GRPH_SURFACE_COUNTER_MAX 16 31 mmLB0_LB_DATA_FORMAT 0 0x61a 9 0 2 PIXEL_DEPTH 0 1 PIXEL_EXPAN_MODE 2 2 INTERLEAVE_EN 3 3 PIXEL_REDUCE_MODE 4 4 DYNAMIC_PIXEL_DEPTH 5 5 PREFILL_EN 8 8 PREFETCH 12 12 REQUEST_MODE 24 24 ALPHA_EN 31 31 mmLB0_LB_MEMORY_CTRL 0 0x61b 3 0 2 LB_MEMORY_SIZE 0 12 LB_NUM_PARTITIONS 16 19 LB_MEMORY_CONFIG 20 21 mmLB0_LB_MEMORY_SIZE_STATUS 0 0x61c 1 0 2 LB_MEMORY_SIZE_STATUS 0 12 mmLB0_LB_DESKTOP_HEIGHT 0 0x61d 1 0 2 DESKTOP_HEIGHT 0 14 mmLB0_LB_VLINE_START_END 0 0x61e 3 0 2 VLINE_START 0 13 VLINE_END 16 30 VLINE_INV 31 31 mmLB0_LB_VLINE2_START_END 0 0x61f 3 0 2 VLINE2_START 0 13 VLINE2_END 16 30 VLINE2_INV 31 31 mmLB0_LB_V_COUNTER 0 0x620 1 0 2 V_COUNTER 0 14 mmLB0_LB_SNAPSHOT_V_COUNTER 0 0x621 1 0 2 SNAPSHOT_V_COUNTER 0 14 mmLB0_LB_INTERRUPT_MASK 0 0x622 3 0 2 VBLANK_INTERRUPT_MASK 0 0 VLINE_INTERRUPT_MASK 4 4 VLINE2_INTERRUPT_MASK 8 8 mmLB0_LB_VLINE_STATUS 0 0x623 5 0 2 VLINE_OCCURRED 0 0 VLINE_ACK 4 4 VLINE_STAT 12 12 VLINE_INTERRUPT 16 16 VLINE_INTERRUPT_TYPE 17 17 mmLB0_LB_VLINE2_STATUS 0 0x624 5 0 2 VLINE2_OCCURRED 0 0 VLINE2_ACK 4 4 VLINE2_STAT 12 12 VLINE2_INTERRUPT 16 16 VLINE2_INTERRUPT_TYPE 17 17 mmLB0_LB_VBLANK_STATUS 0 0x625 5 0 2 VBLANK_OCCURRED 0 0 VBLANK_ACK 4 4 VBLANK_STAT 12 12 VBLANK_INTERRUPT 16 16 VBLANK_INTERRUPT_TYPE 17 17 mmLB0_LB_SYNC_RESET_SEL 0 0x626 4 0 2 LB_SYNC_RESET_SEL 0 1 LB_SYNC_RESET_SEL2 4 4 LB_SYNC_RESET_DELAY 8 15 LB_SYNC_DURATION 22 23 mmLB0_LB_BLACK_KEYER_R_CR 0 0x627 1 0 2 LB_BLACK_KEYER_R_CR 4 15 mmLB0_LB_BLACK_KEYER_G_Y 0 0x628 1 0 2 LB_BLACK_KEYER_G_Y 4 15 mmLB0_LB_BLACK_KEYER_B_CB 0 0x629 1 0 2 LB_BLACK_KEYER_B_CB 4 15 mmLB0_LB_KEYER_COLOR_CTRL 0 0x62a 2 0 2 LB_KEYER_COLOR_EN 0 0 LB_KEYER_COLOR_REP_EN 8 8 mmLB0_LB_KEYER_COLOR_R_CR 0 0x62b 1 0 2 LB_KEYER_COLOR_R_CR 4 15 mmLB0_LB_KEYER_COLOR_G_Y 0 0x62c 1 0 2 LB_KEYER_COLOR_G_Y 4 15 mmLB0_LB_KEYER_COLOR_B_CB 0 0x62d 1 0 2 LB_KEYER_COLOR_B_CB 4 15 mmLB0_LB_KEYER_COLOR_REP_R_CR 0 0x62e 1 0 2 LB_KEYER_COLOR_REP_R_CR 4 15 mmLB0_LB_KEYER_COLOR_REP_G_Y 0 0x62f 1 0 2 LB_KEYER_COLOR_REP_G_Y 4 15 mmLB0_LB_KEYER_COLOR_REP_B_CB 0 0x630 1 0 2 LB_KEYER_COLOR_REP_B_CB 4 15 mmLB0_LB_BUFFER_LEVEL_STATUS 0 0x631 4 0 2 REQ_FIFO_LEVEL 0 5 REQ_FIFO_FULL_CNTL 10 15 DATA_BUFFER_LEVEL 16 27 DATA_FIFO_FULL_CNTL 28 31 mmLB0_LB_BUFFER_URGENCY_CTRL 0 0x632 2 0 2 LB_BUFFER_URGENCY_MARK_ON 0 11 LB_BUFFER_URGENCY_MARK_OFF 16 27 mmLB0_LB_BUFFER_URGENCY_STATUS 0 0x633 2 0 2 LB_BUFFER_URGENCY_LEVEL 0 11 LB_BUFFER_URGENCY_STAT 16 16 mmLB0_LB_BUFFER_STATUS 0 0x634 7 0 2 LB_BUFFER_EMPTY_MARGIN 0 3 LB_BUFFER_EMPTY_STAT 4 4 LB_BUFFER_EMPTY_OCCURRED 8 8 LB_BUFFER_EMPTY_ACK 12 12 LB_BUFFER_FULL_STAT 16 16 LB_BUFFER_FULL_OCCURRED 20 20 LB_BUFFER_FULL_ACK 24 24 mmLB0_LB_NO_OUTSTANDING_REQ_STATUS 0 0x635 1 0 2 LB_NO_OUTSTANDING_REQ_STAT 0 0 mmLB0_MVP_AFR_FLIP_MODE 0 0x636 1 0 2 MVP_AFR_FLIP_MODE 0 1 mmLB0_MVP_AFR_FLIP_FIFO_CNTL 0 0x637 4 0 2 MVP_AFR_FLIP_FIFO_NUM_ENTRIES 0 3 MVP_AFR_FLIP_FIFO_RESET 4 4 MVP_AFR_FLIP_FIFO_RESET_FLAG 8 8 MVP_AFR_FLIP_FIFO_RESET_ACK 12 12 mmLB0_MVP_FLIP_LINE_NUM_INSERT 0 0x638 4 0 2 MVP_FLIP_LINE_NUM_INSERT_MODE 0 1 MVP_FLIP_LINE_NUM_INSERT 8 22 MVP_FLIP_LINE_NUM_OFFSET 24 29 MVP_FLIP_AUTO_ENABLE 30 30 mmLB0_DC_MVP_LB_CONTROL 0 0x639 7 0 2 MVP_SWAP_LOCK_IN_MODE 0 1 DC_MVP_SWAP_LOCK_OUT_SEL 8 8 DC_MVP_SWAP_LOCK_OUT_FORCE_ONE 12 12 DC_MVP_SWAP_LOCK_OUT_FORCE_ZERO 16 16 DC_MVP_SWAP_LOCK_STATUS 20 20 DC_MVP_SWAP_LOCK_IN_CAP 28 28 DC_MVP_SPARE_FLOPS 31 31 mmDCFE0_DCFE_CLOCK_CONTROL 0 0x65a 7 0 2 DISPCLK_R_DCFE_GATE_DISABLE 4 4 DISPCLK_G_DCP_GATE_DISABLE 8 8 DISPCLK_G_SCL_GATE_DISABLE 12 12 DISPCLK_G_PSCL_GATE_DISABLE 15 15 DISPCLK_G_PIPE_REQUEST_DIS_GATE_DISABLE 17 17 DCFE_TEST_CLK_SEL 24 28 DCFE_CLOCK_ENABLE 31 31 mmDCFE0_DCFE_SOFT_RESET 0 0x65b 6 0 2 DCP_PIXPIPE_SOFT_RESET 0 0 DCP_REQ_SOFT_RESET 1 1 SCL_ALU_SOFT_RESET 2 2 SCL_SOFT_RESET 3 3 CRTC_SOFT_RESET 4 4 PSCL_SOFT_RESET 5 5 mmDCFE0_DCFE_MEM_PWR_CTRL 0 0x65d 20 0 2 DCP_LUT_MEM_PWR_FORCE 0 1 DCP_LUT_MEM_PWR_DIS 2 2 DCP_REGAMMA_MEM_PWR_FORCE 3 4 DCP_REGAMMA_MEM_PWR_DIS 5 5 SCL_COEFF_MEM_PWR_FORCE 6 7 SCL_COEFF_MEM_PWR_DIS 8 8 DCP_CURSOR_MEM_PWR_FORCE 9 10 DCP_CURSOR_MEM_PWR_DIS 11 11 LB0_ALPHA_MEM_PWR_FORCE 12 13 LB0_ALPHA_MEM_PWR_DIS 14 14 LB1_ALPHA_MEM_PWR_FORCE 15 16 LB1_ALPHA_MEM_PWR_DIS 17 17 LB2_ALPHA_MEM_PWR_FORCE 18 19 LB2_ALPHA_MEM_PWR_DIS 20 20 LB0_MEM_PWR_FORCE 21 22 LB0_MEM_PWR_DIS 23 23 LB1_MEM_PWR_FORCE 24 25 LB1_MEM_PWR_DIS 26 26 LB2_MEM_PWR_FORCE 27 28 LB2_MEM_PWR_DIS 29 29 mmDCFE0_DCFE_MEM_PWR_CTRL2 0 0x65e 12 0 2 DCP_LUT_MEM_PWR_MODE_SEL 0 1 DCP_REGAMMA_MEM_PWR_MODE_SEL 2 3 SCL_COEFF_MEM_PWR_MODE_SEL 4 5 DCP_CURSOR_MEM_PWR_MODE_SEL 6 7 LB_ALPHA_MEM_PWR_MODE_SEL 8 9 LB_MEM_PWR_MODE_SEL 10 11 DCP_CURSOR2_MEM_PWR_MODE_SEL 12 13 BLND_MEM_PWR_MODE_SEL 14 15 BLND_MEM_PWR_FORCE 16 17 BLND_MEM_PWR_DIS 18 18 DCP_CURSOR2_MEM_PWR_FORCE 21 22 DCP_CURSOR2_MEM_PWR_DIS 23 23 mmDCFE0_DCFE_MEM_PWR_STATUS 0 0x65f 12 0 2 DCP_LUT_MEM_PWR_STATE 0 1 DCP_REGAMMA_MEM_PWR_STATE 2 3 SCL_COEFF_MEM_PWR_STATE 4 5 DCP_CURSOR_MEM_PWR_STATE 6 7 DCP_CURSOR2_MEM_PWR_STATE 8 9 LB0_ALPHA_MEM_PWR_STATE 10 11 LB1_ALPHA_MEM_PWR_STATE 12 13 LB2_ALPHA_MEM_PWR_STATE 14 15 LB0_MEM_PWR_STATE 16 17 LB1_MEM_PWR_STATE 18 19 LB2_MEM_PWR_STATE 20 21 BLND_MEM_PWR_STATE 22 23 mmDCFE0_DCFE_MISC 0 0x660 1 0 2 DCFE_DPG_ALLOW_SR_ECO_EN 0 0 mmDCFE0_DCFE_FLUSH 0 0x661 5 0 2 FLUSH_OCCURED 0 0 CLEAR_FLUSH_OCCURED 1 1 FLUSH_DEEP 2 2 CLEAR_FLUSH_DEEP 3 3 ALL_MC_REQ_RET 4 4 mmDC_PERFMON3_PERFCOUNTER_CNTL 0 0x66e 13 0 2 PERFCOUNTER_EVENT_SEL 0 8 PERFCOUNTER_CVALUE_SEL 9 11 PERFCOUNTER_INC_MODE 12 14 PERFCOUNTER_HW_CNTL_SEL 15 15 PERFCOUNTER_RUNEN_MODE 16 16 PERFCOUNTER_CNTOFF_SEL 17 21 PERFCOUNTER_CNTOFF_START_DIS 22 22 PERFCOUNTER_RESTART_EN 23 23 PERFCOUNTER_INT_EN 24 24 PERFCOUNTER_OFF_MASK 25 25 PERFCOUNTER_ACTIVE 26 26 PERFCOUNTER_INT_TYPE 27 27 PERFCOUNTER_CNTL_SEL 29 31 mmDC_PERFMON3_PERFCOUNTER_CNTL2 0 0x66f 4 0 2 PERFCOUNTER_COUNTED_VALUE_TYPE 0 1 PERFCOUNTER_HW_STOP1_SEL 2 2 PERFCOUNTER_HW_STOP2_SEL 3 3 PERFCOUNTER_CNTL2_SEL 29 31 mmDC_PERFMON3_PERFCOUNTER_STATE 0 0x670 16 0 2 PERFCOUNTER_CNT0_STATE 0 1 PERFCOUNTER_STATE_SEL0 2 2 PERFCOUNTER_CNT1_STATE 4 5 PERFCOUNTER_STATE_SEL1 6 6 PERFCOUNTER_CNT2_STATE 8 9 PERFCOUNTER_STATE_SEL2 10 10 PERFCOUNTER_CNT3_STATE 12 13 PERFCOUNTER_STATE_SEL3 14 14 PERFCOUNTER_CNT4_STATE 16 17 PERFCOUNTER_STATE_SEL4 18 18 PERFCOUNTER_CNT5_STATE 20 21 PERFCOUNTER_STATE_SEL5 22 22 PERFCOUNTER_CNT6_STATE 24 25 PERFCOUNTER_STATE_SEL6 26 26 PERFCOUNTER_CNT7_STATE 28 29 PERFCOUNTER_STATE_SEL7 30 30 mmDC_PERFMON3_PERFMON_CNTL 0 0x671 6 0 2 PERFMON_STATE 0 1 PERFMON_RPT_COUNT 8 27 PERFMON_CNTOFF_AND_OR 28 28 PERFMON_CNTOFF_INT_EN 29 29 PERFMON_CNTOFF_INT_STATUS 30 30 PERFMON_CNTOFF_INT_ACK 31 31 mmDC_PERFMON3_PERFMON_CNTL2 0 0x672 4 0 2 PERFMON_CNTOFF_INT_TYPE 0 0 PERFMON_CLK_ENABLE 1 1 PERFMON_RUN_ENABLE_START_SEL 2 9 PERFMON_RUN_ENABLE_STOP_SEL 10 17 mmDC_PERFMON3_PERFMON_CVALUE_INT_MISC 0 0x673 17 0 2 PERFCOUNTER_INT0_STATUS 0 0 PERFCOUNTER_INT1_STATUS 1 1 PERFCOUNTER_INT2_STATUS 2 2 PERFCOUNTER_INT3_STATUS 3 3 PERFCOUNTER_INT4_STATUS 4 4 PERFCOUNTER_INT5_STATUS 5 5 PERFCOUNTER_INT6_STATUS 6 6 PERFCOUNTER_INT7_STATUS 7 7 PERFCOUNTER_INT0_ACK 8 8 PERFCOUNTER_INT1_ACK 9 9 PERFCOUNTER_INT2_ACK 10 10 PERFCOUNTER_INT3_ACK 11 11 PERFCOUNTER_INT4_ACK 12 12 PERFCOUNTER_INT5_ACK 13 13 PERFCOUNTER_INT6_ACK 14 14 PERFCOUNTER_INT7_ACK 15 15 PERFMON_CVALUE_HI 16 31 mmDC_PERFMON3_PERFMON_CVALUE_LOW 0 0x674 1 0 2 PERFMON_CVALUE_LOW 0 31 mmDC_PERFMON3_PERFMON_HI 0 0x675 2 0 2 PERFMON_HI 0 15 PERFMON_READ_SEL 29 31 mmDC_PERFMON3_PERFMON_LOW 0 0x676 1 0 2 PERFMON_LOW 0 31 mmDMIF_PG0_DPG_PIPE_ARBITRATION_CONTROL1 0 0x67a 2 0 2 PIXEL_DURATION 0 15 BASE_WEIGHT 16 31 mmDMIF_PG0_DPG_PIPE_ARBITRATION_CONTROL2 0 0x67b 2 0 2 TIME_WEIGHT 0 15 URGENCY_WEIGHT 16 31 mmDMIF_PG0_DPG_WATERMARK_MASK_CONTROL 0 0x67c 8 0 2 STUTTER_EXIT_SELF_REFRESH_WATERMARK_MASK 0 2 STUTTER_ENTER_SELF_REFRESH_WATERMARK_MASK 4 6 URGENCY_WATERMARK_MASK 8 10 URGENT_LEVEL_WATERMARK_MASK 12 14 PSTATE_CHANGE_WATERMARK_MASK 15 17 DISABLE_FLIP_URGENT 18 18 URGENT_LEVEL_RAMP_CONTROL 19 19 STATIC_URGENT_LEVEL 20 29 mmDMIF_PG0_DPG_PIPE_URGENCY_CONTROL 0 0x67d 2 0 2 URGENCY_LOW_WATERMARK 0 15 URGENCY_HIGH_WATERMARK 16 31 mmDMIF_PG0_DPG_PIPE_URGENT_LEVEL_CONTROL 0 0x67e 2 0 2 URGENT_LEVEL_LOW_WATERMARK 0 15 URGENT_LEVEL_HIGH_WATERMARK 16 31 mmDMIF_PG0_DPG_PIPE_STUTTER_CONTROL 0 0x67f 14 0 2 STUTTER_ENABLE 0 0 STUTTER_IGNORE_CURSOR 4 4 STUTTER_IGNORE_ICON 5 5 STUTTER_IGNORE_VGA 6 6 STUTTER_IGNORE_FBC 7 7 STUTTER_URGENT_IN_NOT_SELF_REFRESH 10 10 STUTTER_SELF_REFRESH_FORCE_ON 11 11 STUTTER_ENABLE_NONLPTCH 16 16 STUTTER_IGNORE_CURSOR_NONLPTCH 20 20 STUTTER_IGNORE_ICON_NONLPTCH 21 21 STUTTER_IGNORE_VGA_NONLPTCH 22 22 STUTTER_IGNORE_FBC_NONLPTCH 23 23 STUTTER_URGENT_IN_NOT_SELF_REFRESH_NONLPTCH 26 26 STUTTER_SELF_REFRESH_FORCE_ON_NONLPTCH 27 27 mmDMIF_PG0_DPG_PIPE_STUTTER_CONTROL2 0 0x680 2 0 2 STUTTER_EXIT_SELF_REFRESH_WATERMARK 0 15 STUTTER_ENTER_SELF_REFRESH_WATERMARK 16 31 mmDMIF_PG0_DPG_PIPE_LOW_POWER_CONTROL 0 0x681 7 0 2 PSTATE_CHANGE_ENABLE 0 0 DPM_ENABLE 1 1 PSTATE_CHANGE_URGENT_DURING_REQUEST 4 4 PSTATE_CHANGE_NOT_SELF_REFRESH_DURING_REQUEST 8 8 PSTATE_CHANGE_FORCE_ON 9 9 PSTATE_ALLOW_FOR_URGENT 10 10 PSTATE_CHANGE_WATERMARK 15 31 mmDMIF_PG0_DPG_REPEATER_PROGRAM 0 0x682 2 0 2 REG_DPG_DMIFRC_REPEATER 0 2 REG_DMIFRC_DPG_REPEATER 4 6 mmDMIF_PG0_DPG_CHK_PRE_PROC_CNTL 0 0x686 1 0 2 DPG_DISABLE_DMIF_BUF_CHK 0 0 mmDMIF_PG0_DPG_DVMM_STATUS 0 0x687 4 0 2 DPG_DVMM_FORCED_FLIP_TO_UNMAPPED 0 0 DPG_DVMM_FORCED_FLIP_TO_MAPPED 1 1 DPG_DVMM_FORCED_FLIP_TO_UNMAPPED_CLR 4 4 DPG_DVMM_FORCED_FLIP_TO_MAPPED_CLR 5 5 mmSCL0_SCL_COEF_RAM_SELECT 0 0x69a 3 0 2 SCL_C_RAM_TAP_PAIR_IDX 0 3 SCL_C_RAM_PHASE 8 11 SCL_C_RAM_FILTER_TYPE 16 18 mmSCL0_SCL_COEF_RAM_TAP_DATA 0 0x69b 4 0 2 SCL_C_RAM_EVEN_TAP_COEF 0 13 SCL_C_RAM_EVEN_TAP_COEF_EN 15 15 SCL_C_RAM_ODD_TAP_COEF 16 29 SCL_C_RAM_ODD_TAP_COEF_EN 31 31 mmSCL0_SCL_MODE 0 0x69c 2 0 2 SCL_MODE 0 1 SCL_PSCL_EN 4 4 mmSCL0_SCL_TAP_CONTROL 0 0x69d 2 0 2 SCL_V_NUM_OF_TAPS 0 2 SCL_H_NUM_OF_TAPS 8 11 mmSCL0_SCL_CONTROL 0 0x69e 2 0 2 SCL_BOUNDARY_MODE 0 0 SCL_EARLY_EOL_MODE 4 4 mmSCL0_SCL_BYPASS_CONTROL 0 0x69f 1 0 2 SCL_BYPASS_MODE 0 1 mmSCL0_SCL_MANUAL_REPLICATE_CONTROL 0 0x6a0 2 0 2 SCL_V_MANUAL_REPLICATE_FACTOR 0 3 SCL_H_MANUAL_REPLICATE_FACTOR 8 11 mmSCL0_SCL_AUTOMATIC_MODE_CONTROL 0 0x6a1 2 0 2 SCL_V_CALC_AUTO_RATIO_EN 0 0 SCL_H_CALC_AUTO_RATIO_EN 16 16 mmSCL0_SCL_HORZ_FILTER_CONTROL 0 0x6a2 2 0 2 SCL_H_FILTER_PICK_NEAREST 0 0 SCL_H_2TAP_HARDCODE_COEF_EN 8 8 mmSCL0_SCL_HORZ_FILTER_SCALE_RATIO 0 0x6a3 1 0 2 SCL_H_SCALE_RATIO 0 25 mmSCL0_SCL_HORZ_FILTER_INIT 0 0x6a4 2 0 2 SCL_H_INIT_FRAC 0 23 SCL_H_INIT_INT 24 27 mmSCL0_SCL_VERT_FILTER_CONTROL 0 0x6a5 2 0 2 SCL_V_FILTER_PICK_NEAREST 0 0 SCL_V_2TAP_HARDCODE_COEF_EN 8 8 mmSCL0_SCL_VERT_FILTER_SCALE_RATIO 0 0x6a6 1 0 2 SCL_V_SCALE_RATIO 0 25 mmSCL0_SCL_VERT_FILTER_INIT 0 0x6a7 2 0 2 SCL_V_INIT_FRAC 0 23 SCL_V_INIT_INT 24 26 mmSCL0_SCL_VERT_FILTER_INIT_BOT 0 0x6a8 2 0 2 SCL_V_INIT_FRAC_BOT 0 23 SCL_V_INIT_INT_BOT 24 26 mmSCL0_SCL_ROUND_OFFSET 0 0x6a9 2 0 2 SCL_ROUND_OFFSET_RGB_Y 0 15 SCL_ROUND_OFFSET_CBCR 16 31 mmSCL0_SCL_UPDATE 0 0x6aa 4 0 2 SCL_UPDATE_PENDING 0 0 SCL_UPDATE_TAKEN 8 8 SCL_UPDATE_LOCK 16 16 SCL_COEF_UPDATE_COMPLETE 24 24 mmSCL0_SCL_F_SHARP_CONTROL 0 0x6ab 4 0 2 SCL_HF_SHARP_SCALE_FACTOR 0 2 SCL_HF_SHARP_EN 4 4 SCL_VF_SHARP_SCALE_FACTOR 8 10 SCL_VF_SHARP_EN 12 12 mmSCL0_SCL_ALU_CONTROL 0 0x6ac 1 0 2 SCL_ALU_DISABLE 0 0 mmSCL0_SCL_COEF_RAM_CONFLICT_STATUS 0 0x6ad 4 0 2 SCL_HOST_CONFLICT_FLAG 0 0 SCL_HOST_CONFLICT_ACK 8 8 SCL_HOST_CONFLICT_MASK 12 12 SCL_HOST_CONFLICT_INT_STATUS 16 16 mmSCL0_VIEWPORT_START_SECONDARY 0 0x6ae 2 0 2 VIEWPORT_Y_START_SECONDARY 0 13 VIEWPORT_X_START_SECONDARY 16 29 mmSCL0_VIEWPORT_START 0 0x6af 2 0 2 VIEWPORT_Y_START 0 13 VIEWPORT_X_START 16 29 mmSCL0_VIEWPORT_SIZE 0 0x6b0 2 0 2 VIEWPORT_HEIGHT 0 13 VIEWPORT_WIDTH 16 29 mmSCL0_EXT_OVERSCAN_LEFT_RIGHT 0 0x6b1 2 0 2 EXT_OVERSCAN_RIGHT 0 12 EXT_OVERSCAN_LEFT 16 28 mmSCL0_EXT_OVERSCAN_TOP_BOTTOM 0 0x6b2 2 0 2 EXT_OVERSCAN_BOTTOM 0 12 EXT_OVERSCAN_TOP 16 28 mmSCL0_SCL_MODE_CHANGE_DET1 0 0x6b3 3 0 2 SCL_MODE_CHANGE 0 0 SCL_MODE_CHANGE_ACK 4 4 SCL_ALU_H_SCALE_RATIO 7 27 mmSCL0_SCL_MODE_CHANGE_DET2 0 0x6b4 1 0 2 SCL_ALU_V_SCALE_RATIO 0 20 mmSCL0_SCL_MODE_CHANGE_DET3 0 0x6b5 2 0 2 SCL_ALU_SOURCE_HEIGHT 0 13 SCL_ALU_SOURCE_WIDTH 16 29 mmSCL0_SCL_MODE_CHANGE_MASK 0 0x6b6 1 0 2 SCL_MODE_CHANGE_MASK 0 0 mmBLND0_BLND_CONTROL 0 0x6c7 9 0 2 BLND_GLOBAL_GAIN 0 7 BLND_MODE 8 9 BLND_STEREO_TYPE 10 11 BLND_STEREO_POLARITY 12 12 BLND_FEEDTHROUGH_EN 13 13 BLND_ALPHA_MODE 16 17 BLND_ACTIVE_OVERLAP_ONLY 18 18 BLND_MULTIPLIED_MODE 20 20 BLND_GLOBAL_ALPHA 24 31 mmBLND0_BLND_SM_CONTROL2 0 0x6c8 6 0 2 SM_MODE 0 2 SM_FRAME_ALTERNATE 4 4 SM_FIELD_ALTERNATE 5 5 SM_FORCE_NEXT_FRAME_POL 8 9 SM_FORCE_NEXT_TOP_POL 16 17 SM_CURRENT_FRAME_POL 24 24 mmBLND0_BLND_CONTROL2 0 0x6c9 5 0 2 PTI_ENABLE 0 0 PTI_NEW_PIXEL_GAP 4 5 BLND_NEW_PIXEL_MODE 6 6 BLND_SUPERAA_DEGAMMA_EN 7 7 BLND_SUPERAA_REGAMMA_EN 8 8 mmBLND0_BLND_UPDATE 0 0x6ca 3 0 2 BLND_UPDATE_PENDING 0 0 BLND_UPDATE_TAKEN 8 8 BLND_UPDATE_LOCK 16 16 mmBLND0_BLND_UNDERFLOW_INTERRUPT 0 0x6cb 4 0 2 BLND_UNDERFLOW_INT_OCCURED 0 0 BLND_UNDERFLOW_INT_ACK 8 8 BLND_UNDERFLOW_INT_MASK 12 12 BLND_UNDERFLOW_INT_PIPE_INDEX 16 17 mmBLND0_BLND_V_UPDATE_LOCK 0 0x6cc 6 0 2 BLND_DCP_GRPH_V_UPDATE_LOCK 0 0 BLND_DCP_GRPH_SURF_V_UPDATE_LOCK 1 1 BLND_DCP_CUR_V_UPDATE_LOCK 16 16 BLND_SCL_V_UPDATE_LOCK 28 28 BLND_BLND_V_UPDATE_LOCK 29 29 BLND_V_UPDATE_LOCK_MODE 31 31 mmBLND0_BLND_REG_UPDATE_STATUS 0 0x6cd 10 0 2 DCP_BLNDC_GRPH_UPDATE_PENDING 0 0 DCP_BLNDO_GRPH_UPDATE_PENDING 1 1 DCP_BLNDC_GRPH_SURF_UPDATE_PENDING 2 2 DCP_BLNDO_GRPH_SURF_UPDATE_PENDING 3 3 DCP_BLNDC_CUR_UPDATE_PENDING 6 6 DCP_BLNDO_CUR_UPDATE_PENDING 7 7 SCL_BLNDC_UPDATE_PENDING 8 8 SCL_BLNDO_UPDATE_PENDING 9 9 BLND_BLNDC_UPDATE_PENDING 10 10 BLND_BLNDO_UPDATE_PENDING 11 11 mmCRTC0_CRTC_H_BLANK_EARLY_NUM 0 0x6d2 2 0 2 CRTC_H_BLANK_EARLY_NUM 0 9 CRTC_H_BLANK_EARLY_NUM_DIS 16 16 mmCRTC0_CRTC_H_TOTAL 0 0x6d3 1 0 2 CRTC_H_TOTAL 0 13 mmCRTC0_CRTC_H_BLANK_START_END 0 0x6d4 2 0 2 CRTC_H_BLANK_START 0 13 CRTC_H_BLANK_END 16 29 mmCRTC0_CRTC_H_SYNC_A 0 0x6d5 2 0 2 CRTC_H_SYNC_A_START 0 13 CRTC_H_SYNC_A_END 16 29 mmCRTC0_CRTC_H_SYNC_A_CNTL 0 0x6d6 3 0 2 CRTC_H_SYNC_A_POL 0 0 CRTC_COMP_SYNC_A_EN 16 16 CRTC_H_SYNC_A_CUTOFF 17 17 mmCRTC0_CRTC_H_SYNC_B 0 0x6d7 2 0 2 CRTC_H_SYNC_B_START 0 13 CRTC_H_SYNC_B_END 16 29 mmCRTC0_CRTC_H_SYNC_B_CNTL 0 0x6d8 3 0 2 CRTC_H_SYNC_B_POL 0 0 CRTC_COMP_SYNC_B_EN 16 16 CRTC_H_SYNC_B_CUTOFF 17 17 mmCRTC0_CRTC_VBI_END 0 0x6d9 2 0 2 CRTC_VBI_V_END 0 13 CRTC_VBI_H_END 16 29 mmCRTC0_CRTC_V_TOTAL 0 0x6da 1 0 2 CRTC_V_TOTAL 0 13 mmCRTC0_CRTC_V_TOTAL_MIN 0 0x6db 1 0 2 CRTC_V_TOTAL_MIN 0 13 mmCRTC0_CRTC_V_TOTAL_MAX 0 0x6dc 2 0 2 CRTC_V_TOTAL_MAX 0 13 CRTC_ALLOW_VBLANK_EXTENSION_FOR_MC_TRAINING 16 16 mmCRTC0_CRTC_V_TOTAL_CONTROL 0 0x6dd 6 0 2 CRTC_V_TOTAL_MIN_SEL 0 0 CRTC_V_TOTAL_MAX_SEL 4 4 CRTC_FORCE_LOCK_ON_EVENT 8 8 CRTC_FORCE_LOCK_TO_MASTER_VSYNC 12 12 CRTC_SET_V_TOTAL_MIN_MASK_EN 15 15 CRTC_SET_V_TOTAL_MIN_MASK 16 31 mmCRTC0_CRTC_V_TOTAL_INT_STATUS 0 0x6de 4 0 2 CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED 0 0 CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT 4 4 CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_ACK 8 8 CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_MSK 12 12 mmCRTC0_CRTC_VSYNC_NOM_INT_STATUS 0 0x6df 2 0 2 CRTC_VSYNC_NOM 0 0 CRTC_VSYNC_NOM_INT_CLEAR 4 4 mmCRTC0_CRTC_V_BLANK_START_END 0 0x6e0 2 0 2 CRTC_V_BLANK_START 0 13 CRTC_V_BLANK_END 16 29 mmCRTC0_CRTC_V_SYNC_A 0 0x6e1 2 0 2 CRTC_V_SYNC_A_START 0 13 CRTC_V_SYNC_A_END 16 29 mmCRTC0_CRTC_V_SYNC_A_CNTL 0 0x6e2 1 0 2 CRTC_V_SYNC_A_POL 0 0 mmCRTC0_CRTC_V_SYNC_B 0 0x6e3 2 0 2 CRTC_V_SYNC_B_START 0 13 CRTC_V_SYNC_B_END 16 29 mmCRTC0_CRTC_V_SYNC_B_CNTL 0 0x6e4 1 0 2 CRTC_V_SYNC_B_POL 0 0 mmCRTC0_CRTC_DTMTEST_CNTL 0 0x6e5 2 0 2 CRTC_DTMTEST_CRTC_EN 0 0 CRTC_DTMTEST_CLK_DIV 1 4 mmCRTC0_CRTC_DTMTEST_STATUS_POSITION 0 0x6e6 2 0 2 CRTC_DTMTEST_VERT_COUNT 0 13 CRTC_DTMTEST_HORZ_COUNT 16 29 mmCRTC0_CRTC_TRIGA_CNTL 0 0x6e7 11 0 2 CRTC_TRIGA_SOURCE_SELECT 0 4 CRTC_TRIGA_POLARITY_SELECT 5 7 CRTC_TRIGA_RESYNC_BYPASS_EN 8 8 CRTC_TRIGA_INPUT_STATUS 9 9 CRTC_TRIGA_POLARITY_STATUS 10 10 CRTC_TRIGA_OCCURRED 11 11 CRTC_TRIGA_RISING_EDGE_DETECT_CNTL 12 13 CRTC_TRIGA_FALLING_EDGE_DETECT_CNTL 16 17 CRTC_TRIGA_FREQUENCY_SELECT 20 21 CRTC_TRIGA_DELAY 24 28 CRTC_TRIGA_CLEAR 31 31 mmCRTC0_CRTC_TRIGA_MANUAL_TRIG 0 0x6e8 1 0 2 CRTC_TRIGA_MANUAL_TRIG 0 0 mmCRTC0_CRTC_TRIGB_CNTL 0 0x6e9 11 0 2 CRTC_TRIGB_SOURCE_SELECT 0 4 CRTC_TRIGB_POLARITY_SELECT 5 7 CRTC_TRIGB_RESYNC_BYPASS_EN 8 8 CRTC_TRIGB_INPUT_STATUS 9 9 CRTC_TRIGB_POLARITY_STATUS 10 10 CRTC_TRIGB_OCCURRED 11 11 CRTC_TRIGB_RISING_EDGE_DETECT_CNTL 12 13 CRTC_TRIGB_FALLING_EDGE_DETECT_CNTL 16 17 CRTC_TRIGB_FREQUENCY_SELECT 20 21 CRTC_TRIGB_DELAY 24 28 CRTC_TRIGB_CLEAR 31 31 mmCRTC0_CRTC_TRIGB_MANUAL_TRIG 0 0x6ea 1 0 2 CRTC_TRIGB_MANUAL_TRIG 0 0 mmCRTC0_CRTC_FORCE_COUNT_NOW_CNTL 0 0x6eb 5 0 2 CRTC_FORCE_COUNT_NOW_MODE 0 1 CRTC_FORCE_COUNT_NOW_CHECK 4 4 CRTC_FORCE_COUNT_NOW_TRIG_SEL 8 8 CRTC_FORCE_COUNT_NOW_OCCURRED 16 16 CRTC_FORCE_COUNT_NOW_CLEAR 24 24 mmCRTC0_CRTC_FLOW_CONTROL 0 0x6ec 4 0 2 CRTC_FLOW_CONTROL_SOURCE_SELECT 0 4 CRTC_FLOW_CONTROL_POLARITY 8 8 CRTC_FLOW_CONTROL_GRANULARITY 16 16 CRTC_FLOW_CONTROL_INPUT_STATUS 24 24 mmCRTC0_CRTC_STEREO_FORCE_NEXT_EYE 0 0x6ed 3 0 2 CRTC_STEREO_FORCE_NEXT_EYE 0 1 CRTC_AVSYNC_FRAME_COUNTER 8 15 CRTC_AVSYNC_LINE_COUNTER 16 28 mmCRTC0_CRTC_AVSYNC_COUNTER 0 0x6ee 1 0 2 CRTC_AVSYNC_COUNTER 0 31 mmCRTC0_CRTC_CONTROL 0 0x6ef 11 0 2 CRTC_MASTER_EN 0 0 CRTC_SYNC_RESET_SEL 4 4 CRTC_DISABLE_POINT_CNTL 8 9 CRTC_START_POINT_CNTL 12 12 CRTC_FIELD_NUMBER_CNTL 13 13 CRTC_FIELD_NUMBER_POLARITY 14 14 CRTC_CURRENT_MASTER_EN_STATE 16 16 CRTC_HBLANK_EARLY_CONTROL 20 22 CRTC_SOF_PULL_EN 29 29 CRTC_AVSYNC_LOCK_SNAPSHOT 30 30 CRTC_AVSYNC_VSYNC_N_HSYNC_MODE 31 31 mmCRTC0_CRTC_BLANK_CONTROL 0 0x6f0 3 0 2 CRTC_CURRENT_BLANK_STATE 0 0 CRTC_BLANK_DATA_EN 8 8 CRTC_BLANK_DE_MODE 16 16 mmCRTC0_CRTC_INTERLACE_CONTROL 0 0x6f1 2 0 2 CRTC_INTERLACE_ENABLE 0 0 CRTC_INTERLACE_FORCE_NEXT_FIELD 16 17 mmCRTC0_CRTC_INTERLACE_STATUS 0 0x6f2 2 0 2 CRTC_INTERLACE_CURRENT_FIELD 0 0 CRTC_INTERLACE_NEXT_FIELD 1 1 mmCRTC0_CRTC_FIELD_INDICATION_CONTROL 0 0x6f3 2 0 2 CRTC_FIELD_INDICATION_OUTPUT_POLARITY 0 0 CRTC_FIELD_ALIGNMENT 1 1 mmCRTC0_CRTC_PIXEL_DATA_READBACK0 0 0x6f4 2 0 2 CRTC_PIXEL_DATA_BLUE_CB 0 11 CRTC_PIXEL_DATA_GREEN_Y 16 27 mmCRTC0_CRTC_PIXEL_DATA_READBACK1 0 0x6f5 1 0 2 CRTC_PIXEL_DATA_RED_CR 0 11 mmCRTC0_CRTC_STATUS 0 0x6f6 9 0 2 CRTC_V_BLANK 0 0 CRTC_V_ACTIVE_DISP 1 1 CRTC_V_SYNC_A 2 2 CRTC_V_UPDATE 3 3 CRTC_V_START_LINE 4 4 CRTC_V_BLANK_3D_STRUCTURE 5 5 CRTC_H_BLANK 16 16 CRTC_H_ACTIVE_DISP 17 17 CRTC_H_SYNC_A 18 18 mmCRTC0_CRTC_STATUS_POSITION 0 0x6f7 2 0 2 CRTC_VERT_COUNT 0 13 CRTC_HORZ_COUNT 16 29 mmCRTC0_CRTC_NOM_VERT_POSITION 0 0x6f8 1 0 2 CRTC_VERT_COUNT_NOM 0 13 mmCRTC0_CRTC_STATUS_FRAME_COUNT 0 0x6f9 1 0 2 CRTC_FRAME_COUNT 0 23 mmCRTC0_CRTC_STATUS_VF_COUNT 0 0x6fa 1 0 2 CRTC_VF_COUNT 0 29 mmCRTC0_CRTC_STATUS_HV_COUNT 0 0x6fb 1 0 2 CRTC_HV_COUNT 0 29 mmCRTC0_CRTC_COUNT_CONTROL 0 0x6fc 2 0 2 CRTC_HORZ_COUNT_BY2_EN 0 0 CRTC_HORZ_REPETITION_COUNT 1 4 mmCRTC0_CRTC_COUNT_RESET 0 0x6fd 1 0 2 CRTC_RESET_FRAME_COUNT 0 0 mmCRTC0_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE 0 0x6fe 1 0 2 CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE 0 0 mmCRTC0_CRTC_VERT_SYNC_CONTROL 0 0x6ff 3 0 2 CRTC_FORCE_VSYNC_NEXT_LINE_OCCURRED 0 0 CRTC_FORCE_VSYNC_NEXT_LINE_CLEAR 8 8 CRTC_AUTO_FORCE_VSYNC_MODE 16 17 mmCRTC0_CRTC_STEREO_STATUS 0 0x700 5 0 2 CRTC_STEREO_CURRENT_EYE 0 0 CRTC_STEREO_SYNC_OUTPUT 8 8 CRTC_STEREO_SYNC_SELECT 16 16 CRTC_STEREO_EYE_FLAG 20 20 CRTC_STEREO_FORCE_NEXT_EYE_PENDING 24 25 mmCRTC0_CRTC_STEREO_CONTROL 0 0x701 8 0 2 CRTC_STEREO_SYNC_OUTPUT_LINE_NUM 0 13 CRTC_STEREO_SYNC_OUTPUT_POLARITY 15 15 CRTC_STEREO_SYNC_SELECT_POLARITY 16 16 CRTC_STEREO_EYE_FLAG_POLARITY 17 17 CRTC_DISABLE_STEREOSYNC_OUTPUT_FOR_DP 18 18 CRTC_DISABLE_FIELD_NUM 19 19 CRTC_DISABLE_V_BLANK_FOR_DP_FIX 20 20 CRTC_STEREO_EN 24 24 mmCRTC0_CRTC_SNAPSHOT_STATUS 0 0x702 3 0 2 CRTC_SNAPSHOT_OCCURRED 0 0 CRTC_SNAPSHOT_CLEAR 1 1 CRTC_SNAPSHOT_MANUAL_TRIGGER 2 2 mmCRTC0_CRTC_SNAPSHOT_CONTROL 0 0x703 1 0 2 CRTC_AUTO_SNAPSHOT_TRIG_SEL 0 1 mmCRTC0_CRTC_SNAPSHOT_POSITION 0 0x704 2 0 2 CRTC_SNAPSHOT_VERT_COUNT 0 13 CRTC_SNAPSHOT_HORZ_COUNT 16 29 mmCRTC0_CRTC_SNAPSHOT_FRAME 0 0x705 1 0 2 CRTC_SNAPSHOT_FRAME_COUNT 0 23 mmCRTC0_CRTC_START_LINE_CONTROL 0 0x706 5 0 2 CRTC_PROGRESSIVE_START_LINE_EARLY 0 0 CRTC_INTERLACE_START_LINE_EARLY 1 1 CRTC_PREFETCH_EN 2 2 CRTC_LEGACY_REQUESTOR_EN 8 8 CRTC_ADVANCED_START_LINE_POSITION 12 19 mmCRTC0_CRTC_INTERRUPT_CONTROL 0 0x707 16 0 2 CRTC_SNAPSHOT_INT_MSK 0 0 CRTC_SNAPSHOT_INT_TYPE 1 1 CRTC_V_UPDATE_INT_MSK 4 4 CRTC_V_UPDATE_INT_TYPE 5 5 CRTC_FORCE_COUNT_NOW_INT_MSK 8 8 CRTC_FORCE_COUNT_NOW_INT_TYPE 9 9 CRTC_FORCE_VSYNC_NEXT_LINE_INT_MSK 16 16 CRTC_FORCE_VSYNC_NEXT_LINE_INT_TYPE 17 17 CRTC_TRIGA_INT_MSK 24 24 CRTC_TRIGB_INT_MSK 25 25 CRTC_TRIGA_INT_TYPE 26 26 CRTC_TRIGB_INT_TYPE 27 27 CRTC_VSYNC_NOM_INT_MSK 28 28 CRTC_VSYNC_NOM_INT_TYPE 29 29 CRTC_GSL_VSYNC_GAP_INT_MSK 30 30 CRTC_GSL_VSYNC_GAP_INT_TYPE 31 31 mmCRTC0_CRTC_UPDATE_LOCK 0 0x708 1 0 2 CRTC_UPDATE_LOCK 0 0 mmCRTC0_CRTC_DOUBLE_BUFFER_CONTROL 0 0x709 5 0 2 CRTC_UPDATE_PENDING 0 0 CRTC_UPDATE_INSTANTLY 8 8 CRTC_BLANK_DATA_DOUBLE_BUFFER_EN 16 16 CRTC_RANGE_TIMING_DBUF_UPDATE_MODE 24 24 CRTC_RANGE_TIMING_DBUF_UPDATE_PENDING 25 25 mmCRTC0_CRTC_VGA_PARAMETER_CAPTURE_MODE 0 0x70a 1 0 2 CRTC_VGA_PARAMETER_CAPTURE_MODE 0 0 mmCRTC0_CRTC_TEST_PATTERN_CONTROL 0 0x70b 4 0 2 CRTC_TEST_PATTERN_EN 0 0 CRTC_TEST_PATTERN_MODE 8 10 CRTC_TEST_PATTERN_DYNAMIC_RANGE 16 16 CRTC_TEST_PATTERN_COLOR_FORMAT 24 31 mmCRTC0_CRTC_TEST_PATTERN_PARAMETERS 0 0x70c 5 0 2 CRTC_TEST_PATTERN_INC0 0 3 CRTC_TEST_PATTERN_INC1 4 7 CRTC_TEST_PATTERN_VRES 8 11 CRTC_TEST_PATTERN_HRES 12 15 CRTC_TEST_PATTERN_RAMP0_OFFSET 16 31 mmCRTC0_CRTC_TEST_PATTERN_COLOR 0 0x70d 2 0 2 CRTC_TEST_PATTERN_DATA 0 15 CRTC_TEST_PATTERN_MASK 16 21 mmCRTC0_CRTC_MASTER_UPDATE_LOCK 0 0x70e 3 0 2 MASTER_UPDATE_LOCK 0 0 GSL_CONTROL_MASTER_UPDATE_LOCK 8 8 UNDERFLOW_UPDATE_LOCK 16 16 mmCRTC0_CRTC_MASTER_UPDATE_MODE 0 0x70f 2 0 2 MASTER_UPDATE_MODE 0 2 MASTER_UPDATE_INTERLACED_MODE 16 17 mmCRTC0_CRTC_MVP_INBAND_CNTL_INSERT 0 0x710 2 0 2 CRTC_MVP_INBAND_OUT_MODE 0 1 CRTC_MVP_INBAND_CNTL_CHAR_INSERT 8 31 mmCRTC0_CRTC_MVP_INBAND_CNTL_INSERT_TIMER 0 0x711 1 0 2 CRTC_MVP_INBAND_CNTL_CHAR_INSERT_TIMER 0 7 mmCRTC0_CRTC_MVP_STATUS 0 0x712 4 0 2 CRTC_FLIP_NOW_OCCURRED 0 0 CRTC_AFR_HSYNC_SWITCH_DONE_OCCURRED 4 4 CRTC_FLIP_NOW_CLEAR 16 16 CRTC_AFR_HSYNC_SWITCH_DONE_CLEAR 20 20 mmCRTC0_CRTC_MASTER_EN 0 0x713 1 0 2 CRTC_MASTER_EN 0 0 mmCRTC0_CRTC_ALLOW_STOP_OFF_V_CNT 0 0x714 2 0 2 CRTC_ALLOW_STOP_OFF_V_CNT 0 7 CRTC_DISABLE_ALLOW_STOP_OFF_V_CNT 16 16 mmCRTC0_CRTC_V_UPDATE_INT_STATUS 0 0x715 2 0 2 CRTC_V_UPDATE_INT_OCCURRED 0 0 CRTC_V_UPDATE_INT_CLEAR 8 8 mmCRTC0_CRTC_OVERSCAN_COLOR 0 0x717 3 0 2 CRTC_OVERSCAN_COLOR_BLUE 0 9 CRTC_OVERSCAN_COLOR_GREEN 10 19 CRTC_OVERSCAN_COLOR_RED 20 29 mmCRTC0_CRTC_OVERSCAN_COLOR_EXT 0 0x718 3 0 2 CRTC_OVERSCAN_COLOR_BLUE_EXT 0 1 CRTC_OVERSCAN_COLOR_GREEN_EXT 8 9 CRTC_OVERSCAN_COLOR_RED_EXT 16 17 mmCRTC0_CRTC_BLANK_DATA_COLOR 0 0x719 3 0 2 CRTC_BLANK_DATA_COLOR_BLUE_CB 0 9 CRTC_BLANK_DATA_COLOR_GREEN_Y 10 19 CRTC_BLANK_DATA_COLOR_RED_CR 20 29 mmCRTC0_CRTC_BLANK_DATA_COLOR_EXT 0 0x71a 3 0 2 CRTC_BLANK_DATA_COLOR_BLUE_CB_EXT 0 1 CRTC_BLANK_DATA_COLOR_GREEN_Y_EXT 8 9 CRTC_BLANK_DATA_COLOR_RED_CR_EXT 16 17 mmCRTC0_CRTC_BLACK_COLOR 0 0x71b 3 0 2 CRTC_BLACK_COLOR_B_CB 0 9 CRTC_BLACK_COLOR_G_Y 10 19 CRTC_BLACK_COLOR_R_CR 20 29 mmCRTC0_CRTC_BLACK_COLOR_EXT 0 0x71c 3 0 2 CRTC_BLACK_COLOR_B_CB_EXT 0 1 CRTC_BLACK_COLOR_G_Y_EXT 8 9 CRTC_BLACK_COLOR_R_CR_EXT 16 17 mmCRTC0_CRTC_VERTICAL_INTERRUPT0_POSITION 0 0x71d 2 0 2 CRTC_VERTICAL_INTERRUPT0_LINE_START 0 13 CRTC_VERTICAL_INTERRUPT0_LINE_END 16 29 mmCRTC0_CRTC_VERTICAL_INTERRUPT0_CONTROL 0 0x71e 6 0 2 CRTC_VERTICAL_INTERRUPT0_OUTPUT_POLARITY 4 4 CRTC_VERTICAL_INTERRUPT0_INT_ENABLE 8 8 CRTC_VERTICAL_INTERRUPT0_STATUS 12 12 CRTC_VERTICAL_INTERRUPT0_INT_STATUS 16 16 CRTC_VERTICAL_INTERRUPT0_CLEAR 20 20 CRTC_VERTICAL_INTERRUPT0_INT_TYPE 24 24 mmCRTC0_CRTC_VERTICAL_INTERRUPT1_POSITION 0 0x71f 1 0 2 CRTC_VERTICAL_INTERRUPT1_LINE_START 0 13 mmCRTC0_CRTC_VERTICAL_INTERRUPT1_CONTROL 0 0x720 5 0 2 CRTC_VERTICAL_INTERRUPT1_INT_ENABLE 8 8 CRTC_VERTICAL_INTERRUPT1_STATUS 12 12 CRTC_VERTICAL_INTERRUPT1_INT_STATUS 16 16 CRTC_VERTICAL_INTERRUPT1_CLEAR 20 20 CRTC_VERTICAL_INTERRUPT1_INT_TYPE 24 24 mmCRTC0_CRTC_VERTICAL_INTERRUPT2_POSITION 0 0x721 1 0 2 CRTC_VERTICAL_INTERRUPT2_LINE_START 0 13 mmCRTC0_CRTC_VERTICAL_INTERRUPT2_CONTROL 0 0x722 5 0 2 CRTC_VERTICAL_INTERRUPT2_INT_ENABLE 8 8 CRTC_VERTICAL_INTERRUPT2_STATUS 12 12 CRTC_VERTICAL_INTERRUPT2_INT_STATUS 16 16 CRTC_VERTICAL_INTERRUPT2_CLEAR 20 20 CRTC_VERTICAL_INTERRUPT2_INT_TYPE 24 24 mmCRTC0_CRTC_CRC_CNTL 0 0x723 7 0 2 CRTC_CRC_EN 0 0 CRTC_CRC_CONT_EN 4 4 CRTC_CRC_STEREO_MODE 8 9 CRTC_CRC_INTERLACE_MODE 12 13 CRTC_CRC_USE_NEW_AND_REPEATED_PIXELS 16 16 CRTC_CRC0_SELECT 20 22 CRTC_CRC1_SELECT 24 26 mmCRTC0_CRTC_CRC0_WINDOWA_X_CONTROL 0 0x724 2 0 2 CRTC_CRC0_WINDOWA_X_START 0 13 CRTC_CRC0_WINDOWA_X_END 16 29 mmCRTC0_CRTC_CRC0_WINDOWA_Y_CONTROL 0 0x725 2 0 2 CRTC_CRC0_WINDOWA_Y_START 0 13 CRTC_CRC0_WINDOWA_Y_END 16 29 mmCRTC0_CRTC_CRC0_WINDOWB_X_CONTROL 0 0x726 2 0 2 CRTC_CRC0_WINDOWB_X_START 0 13 CRTC_CRC0_WINDOWB_X_END 16 29 mmCRTC0_CRTC_CRC0_WINDOWB_Y_CONTROL 0 0x727 2 0 2 CRTC_CRC0_WINDOWB_Y_START 0 13 CRTC_CRC0_WINDOWB_Y_END 16 29 mmCRTC0_CRTC_CRC0_DATA_RG 0 0x728 2 0 2 CRC0_R_CR 0 15 CRC0_G_Y 16 31 mmCRTC0_CRTC_CRC0_DATA_B 0 0x729 1 0 2 CRC0_B_CB 0 15 mmCRTC0_CRTC_CRC1_WINDOWA_X_CONTROL 0 0x72a 2 0 2 CRTC_CRC1_WINDOWA_X_START 0 13 CRTC_CRC1_WINDOWA_X_END 16 29 mmCRTC0_CRTC_CRC1_WINDOWA_Y_CONTROL 0 0x72b 2 0 2 CRTC_CRC1_WINDOWA_Y_START 0 13 CRTC_CRC1_WINDOWA_Y_END 16 29 mmCRTC0_CRTC_CRC1_WINDOWB_X_CONTROL 0 0x72c 2 0 2 CRTC_CRC1_WINDOWB_X_START 0 13 CRTC_CRC1_WINDOWB_X_END 16 29 mmCRTC0_CRTC_CRC1_WINDOWB_Y_CONTROL 0 0x72d 2 0 2 CRTC_CRC1_WINDOWB_Y_START 0 13 CRTC_CRC1_WINDOWB_Y_END 16 29 mmCRTC0_CRTC_CRC1_DATA_RG 0 0x72e 2 0 2 CRC1_R_CR 0 15 CRC1_G_Y 16 31 mmCRTC0_CRTC_CRC1_DATA_B 0 0x72f 1 0 2 CRC1_B_CB 0 15 mmCRTC0_CRTC_EXT_TIMING_SYNC_CONTROL 0 0x730 11 0 2 CRTC_EXT_TIMING_SYNC_ENABLE 0 1 CRTC_EXT_TIMING_SYNC_HCOUNT_MODE_ENABLE 3 3 CRTC_EXT_TIMING_SYNC_JITTER_FILTERING_ENABLE 4 4 CRTC_EXT_TIMING_SYNC_JITTER_FILTERING_WINDOW 5 6 CRTC_EXT_TIMING_SYNC_WINDOW_ENABLE 8 8 CRTC_EXT_TIMING_SYNC_WINDOW_UPDATE 9 9 CRTC_EXT_TIMING_SYNC_VSYNC_POLARITY 12 12 CRTC_EXT_TIMING_SYNC_HSYNC_POLARITY 13 13 CRTC_EXT_TIMING_SYNC_INTERLACE_MODE 14 14 CRTC_EXT_TIMING_SYNC_MASTER_FRAME_RATE 24 26 CRTC_EXT_TIMING_SYNC_SLAVE_FRAME_RATE 28 30 mmCRTC0_CRTC_EXT_TIMING_SYNC_WINDOW_START 0 0x731 2 0 2 CRTC_EXT_TIMING_SYNC_WINDOW_START_X 0 13 CRTC_EXT_TIMING_SYNC_WINDOW_START_Y 16 29 mmCRTC0_CRTC_EXT_TIMING_SYNC_WINDOW_END 0 0x732 2 0 2 CRTC_EXT_TIMING_SYNC_WINDOW_END_X 0 13 CRTC_EXT_TIMING_SYNC_WINDOW_END_Y 16 29 mmCRTC0_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL 0 0x733 6 0 2 CRTC_EXT_TIMING_SYNC_LOSS_INT_ENABLE 0 0 CRTC_EXT_TIMING_SYNC_LOSS_STATUS 4 4 CRTC_EXT_TIMING_SYNC_LOSS_INT_STATUS 8 8 CRTC_EXT_TIMING_SYNC_LOSS_CLEAR 16 16 CRTC_EXT_TIMING_SYNC_LOSS_INT_TYPE 20 20 CRTC_EXT_TIMING_SYNC_LOSS_FRAME_COUNT 29 31 mmCRTC0_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL 0 0x734 5 0 2 CRTC_EXT_TIMING_SYNC_INT_ENABLE 0 0 CRTC_EXT_TIMING_SYNC_STATUS 4 4 CRTC_EXT_TIMING_SYNC_INT_STATUS 8 8 CRTC_EXT_TIMING_SYNC_CLEAR 16 16 CRTC_EXT_TIMING_SYNC_INT_TYPE 20 20 mmCRTC0_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL 0 0x735 5 0 2 CRTC_EXT_TIMING_SYNC_SIGNAL_INT_ENABLE 0 0 CRTC_EXT_TIMING_SYNC_SIGNAL_STATUS 4 4 CRTC_EXT_TIMING_SYNC_SIGNAL_INT_STATUS 8 8 CRTC_EXT_TIMING_SYNC_SIGNAL_CLEAR 16 16 CRTC_EXT_TIMING_SYNC_SIGNAL_INT_TYPE 20 20 mmCRTC0_CRTC_STATIC_SCREEN_CONTROL 0 0x736 9 0 2 CRTC_STATIC_SCREEN_EVENT_MASK 0 15 CRTC_STATIC_SCREEN_FRAME_COUNT 16 23 CRTC_CPU_SS_INT_ENABLE 24 24 CRTC_SS_STATUS 25 25 CRTC_CPU_SS_INT_STATUS 26 26 CRTC_CPU_SS_INT_CLEAR 27 27 CRTC_CPU_SS_INT_TYPE 28 28 CRTC_STATIC_SCREEN_OVERRIDE 30 30 CRTC_STATIC_SCREEN_OVERRIDE_VALUE 31 31 mmCRTC0_CRTC_3D_STRUCTURE_CONTROL 0 0x737 7 0 2 CRTC_3D_STRUCTURE_EN 0 0 CRTC_3D_STRUCTURE_EN_DB 4 4 CRTC_3D_STRUCTURE_V_UPDATE_MODE 8 9 CRTC_3D_STRUCTURE_STEREO_SEL_OVR 12 12 CRTC_3D_STRUCTURE_F_COUNT_RESET 16 16 CRTC_3D_STRUCTURE_F_COUNT_RESET_PENDING 17 17 CRTC_3D_STRUCTURE_F_COUNT 18 19 mmCRTC0_CRTC_GSL_VSYNC_GAP 0 0x738 8 0 2 CRTC_GSL_VSYNC_GAP_LIMIT 0 7 CRTC_GSL_VSYNC_GAP_DELAY 8 15 CRTC_GSL_VSYNC_GAP_SOURCE_SEL 16 16 CRTC_GSL_VSYNC_GAP_MODE 17 18 CRTC_GSL_VSYNC_GAP_CLEAR 19 19 CRTC_GSL_VSYNC_GAP_OCCURRED 20 20 CRTC_GSL_VSYNC_GAP_MASTER_FASTER 23 23 CRTC_GSL_VSYNC_GAP 24 31 mmCRTC0_CRTC_GSL_WINDOW 0 0x739 2 0 2 CRTC_GSL_WINDOW_START 0 13 CRTC_GSL_WINDOW_END 16 29 mmCRTC0_CRTC_GSL_CONTROL 0 0x73a 3 0 2 CRTC_GSL_CHECK_LINE_NUM 0 13 CRTC_GSL_FORCE_DELAY 16 20 CRTC_GSL_CHECK_ALL_FIELDS 28 28 mmCRTC0_CRTC_RANGE_TIMING_INT_STATUS 0 0x73d 5 0 2 CRTC_RANGE_TIMING_UPDATE_OCCURRED 0 0 CRTC_RANGE_TIMING_UPDATE_OCCURRED_INT 4 4 CRTC_RANGE_TIMING_UPDATE_OCCURRED_CLEAR 8 8 CRTC_RANGE_TIMING_UPDATE_OCCURRED_INT_MSK 12 12 CRTC_RANGE_TIMING_UPDATE_OCCURRED_INT_TYPE 16 16 mmCRTC0_CRTC_DRR_CONTROL 0 0x73e 4 0 2 CRTC_XDMA_PREFETCH_DELAY 0 13 CRTC_V_TOTAL_LAST_USED_BY_DRR 14 27 CRTC_SET_V_TOTAL_MIN_AUTO_DIS 28 28 CRTC_DRR_MODE_DBUF_UPDATE_MODE 29 30 mmFMT0_FMT_CLAMP_COMPONENT_R 0 0x742 2 0 2 FMT_CLAMP_LOWER_R 0 15 FMT_CLAMP_UPPER_R 16 31 mmFMT0_FMT_CLAMP_COMPONENT_G 0 0x743 2 0 2 FMT_CLAMP_LOWER_G 0 15 FMT_CLAMP_UPPER_G 16 31 mmFMT0_FMT_CLAMP_COMPONENT_B 0 0x744 2 0 2 FMT_CLAMP_LOWER_B 0 15 FMT_CLAMP_UPPER_B 16 31 mmFMT0_FMT_DYNAMIC_EXP_CNTL 0 0x745 2 0 2 FMT_DYNAMIC_EXP_EN 0 0 FMT_DYNAMIC_EXP_MODE 4 4 mmFMT0_FMT_CONTROL 0 0x746 11 0 2 FMT_STEREOSYNC_OVERRIDE 0 0 FMT_STEREOSYNC_OVR_POL 4 4 FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX 8 11 FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP 12 13 FMT_PIXEL_ENCODING 16 17 FMT_SUBSAMPLING_MODE 18 19 FMT_SUBSAMPLING_ORDER 20 20 FMT_CBCR_BIT_REDUCTION_BYPASS 21 21 FMT_SRC_SELECT 24 26 FMT_420_PIXEL_PHASE_LOCKED 30 30 FMT_420_PIXEL_PHASE_LOCKED_CLEAR 31 31 mmFMT0_FMT_BIT_DEPTH_CONTROL 0 0x747 17 0 2 FMT_TRUNCATE_EN 0 0 FMT_TRUNCATE_MODE 1 1 FMT_TRUNCATE_DEPTH 4 5 FMT_SPATIAL_DITHER_EN 8 8 FMT_SPATIAL_DITHER_MODE 9 10 FMT_SPATIAL_DITHER_DEPTH 11 12 FMT_FRAME_RANDOM_ENABLE 13 13 FMT_RGB_RANDOM_ENABLE 14 14 FMT_HIGHPASS_RANDOM_ENABLE 15 15 FMT_TEMPORAL_DITHER_EN 16 16 FMT_TEMPORAL_DITHER_DEPTH 17 18 FMT_TEMPORAL_DITHER_OFFSET 21 22 FMT_TEMPORAL_LEVEL 24 24 FMT_TEMPORAL_DITHER_RESET 25 25 FMT_25FRC_SEL 26 27 FMT_50FRC_SEL 28 29 FMT_75FRC_SEL 30 31 mmFMT0_FMT_DITHER_RAND_R_SEED 0 0x748 2 0 2 FMT_RAND_R_SEED 0 7 FMT_OFFSET_R_CR 16 31 mmFMT0_FMT_DITHER_RAND_G_SEED 0 0x749 2 0 2 FMT_RAND_G_SEED 0 7 FMT_OFFSET_G_Y 16 31 mmFMT0_FMT_DITHER_RAND_B_SEED 0 0x74a 2 0 2 FMT_RAND_B_SEED 0 7 FMT_OFFSET_B_CB 16 31 mmFMT0_FMT_CLAMP_CNTL 0 0x74e 2 0 2 FMT_CLAMP_DATA_EN 0 0 FMT_CLAMP_COLOR_FORMAT 16 18 mmFMT0_FMT_CRC_CNTL 0 0x74f 11 0 2 FMT_CRC_EN 0 0 FMT_DTMTEST_CRC_EN 1 1 FMT_CRC_CONT_EN 4 4 FMT_ONE_SHOT_CRC_PENDING 5 5 FMT_CRC_INCLUDE_OVERSCAN 6 6 FMT_CRC_ONLY_BLANKB 8 8 FMT_CRC_PSR_MODE_ENABLE 9 9 FMT_CRC_INTERLACE_MODE 12 13 FMT_CRC_USE_NEW_AND_REPEATED_PIXELS 16 16 FMT_CRC_EVEN_ODD_PIX_ENABLE 20 20 FMT_CRC_EVEN_ODD_PIX_SELECT 24 24 mmFMT0_FMT_CRC_SIG_RED_GREEN_MASK 0 0x750 2 0 2 FMT_CRC_SIG_RED_MASK 0 15 FMT_CRC_SIG_GREEN_MASK 16 31 mmFMT0_FMT_CRC_SIG_BLUE_CONTROL_MASK 0 0x751 2 0 2 FMT_CRC_SIG_BLUE_MASK 0 15 FMT_CRC_SIG_CONTROL_MASK 16 31 mmFMT0_FMT_CRC_SIG_RED_GREEN 0 0x752 2 0 2 FMT_CRC_SIG_RED 0 15 FMT_CRC_SIG_GREEN 16 31 mmFMT0_FMT_CRC_SIG_BLUE_CONTROL 0 0x753 2 0 2 FMT_CRC_SIG_BLUE 0 15 FMT_CRC_SIG_CONTROL 16 31 mmFMT0_FMT_SIDE_BY_SIDE_STEREO_CONTROL 0 0x754 1 0 2 FMT_SIDE_BY_SIDE_STEREO_ACTIVE_WIDTH 0 12 mmFMT0_FMT_420_HBLANK_EARLY_START 0 0x755 1 0 2 FMT_420_HBLANK_EARLY_START 0 11 mmDCP1_GRPH_ENABLE 0 0x75a 2 0 2 GRPH_ENABLE 0 0 GRPH_KEYER_ALPHA_SEL 1 1 mmDCP1_GRPH_CONTROL 0 0x75b 12 0 2 GRPH_DEPTH 0 1 GRPH_SE_ENABLE 2 2 GRPH_Z 4 5 GRPH_DIM_TYPE 6 7 GRPH_FORMAT 8 10 GRPH_NUM_BANKS 12 14 GRPH_ADDRESS_TRANSLATION_ENABLE 16 16 GRPH_PRIVILEGED_ACCESS_ENABLE 17 17 GRPH_NUM_SHADER_ENGINES 18 19 GRPH_SW_MODE 20 24 GRPH_NUM_PIPES 28 30 GRPH_COLOR_EXPANSION_MODE 31 31 mmDCP1_GRPH_LUT_10BIT_BYPASS 0 0x75c 2 0 2 GRPH_LUT_10BIT_BYPASS_EN 8 8 GRPH_LUT_10BIT_BYPASS_DBL_BUF_EN 16 16 mmDCP1_GRPH_SWAP_CNTL 0 0x75d 5 0 2 GRPH_ENDIAN_SWAP 0 1 GRPH_RED_CROSSBAR 4 5 GRPH_GREEN_CROSSBAR 6 7 GRPH_BLUE_CROSSBAR 8 9 GRPH_ALPHA_CROSSBAR 10 11 mmDCP1_GRPH_PRIMARY_SURFACE_ADDRESS 0 0x75e 2 0 2 GRPH_PRIMARY_DFQ_ENABLE 0 0 GRPH_PRIMARY_SURFACE_ADDRESS 8 31 mmDCP1_GRPH_SECONDARY_SURFACE_ADDRESS 0 0x75f 2 0 2 GRPH_SECONDARY_DFQ_ENABLE 0 0 GRPH_SECONDARY_SURFACE_ADDRESS 8 31 mmDCP1_GRPH_PITCH 0 0x760 1 0 2 GRPH_PITCH 0 14 mmDCP1_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH 0 0x761 1 0 2 GRPH_PRIMARY_SURFACE_ADDRESS_HIGH 0 7 mmDCP1_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH 0 0x762 1 0 2 GRPH_SECONDARY_SURFACE_ADDRESS_HIGH 0 7 mmDCP1_GRPH_SURFACE_OFFSET_X 0 0x763 1 0 2 GRPH_SURFACE_OFFSET_X 0 13 mmDCP1_GRPH_SURFACE_OFFSET_Y 0 0x764 1 0 2 GRPH_SURFACE_OFFSET_Y 0 13 mmDCP1_GRPH_X_START 0 0x765 1 0 2 GRPH_X_START 0 13 mmDCP1_GRPH_Y_START 0 0x766 1 0 2 GRPH_Y_START 0 13 mmDCP1_GRPH_X_END 0 0x767 1 0 2 GRPH_X_END 0 14 mmDCP1_GRPH_Y_END 0 0x768 1 0 2 GRPH_Y_END 0 14 mmDCP1_INPUT_GAMMA_CONTROL 0 0x769 1 0 2 GRPH_INPUT_GAMMA_MODE 0 0 mmDCP1_GRPH_UPDATE 0 0x76a 11 0 2 GRPH_MODE_UPDATE_PENDING 0 0 GRPH_MODE_UPDATE_TAKEN 1 1 GRPH_SURFACE_UPDATE_PENDING 2 2 GRPH_SURFACE_UPDATE_TAKEN 3 3 GRPH_XDMA_FLIP_TYPE_CLEAR 8 8 GRPH_XDMA_DRR_MODE_ENABLE 9 9 GRPH_XDMA_MULTIFLIP_ENABLE 10 10 GRPH_UPDATE_LOCK 16 16 GRPH_SURFACE_IGNORE_UPDATE_LOCK 20 20 GRPH_MODE_DISABLE_MULTIPLE_UPDATE 24 24 GRPH_SURFACE_DISABLE_MULTIPLE_UPDATE 28 28 mmDCP1_GRPH_FLIP_CONTROL 0 0x76b 4 0 2 GRPH_SURFACE_UPDATE_H_RETRACE_EN 0 0 GRPH_XDMA_SUPER_AA_EN 1 1 GRPH_SURFACE_UPDATE_IMMEDIATE_EN 4 4 GRPH_SURFACE_UPDATE_PENDING_MODE 5 5 mmDCP1_GRPH_SURFACE_ADDRESS_INUSE 0 0x76c 1 0 2 GRPH_SURFACE_ADDRESS_INUSE 8 31 mmDCP1_GRPH_DFQ_CONTROL 0 0x76d 3 0 2 GRPH_DFQ_RESET 0 0 GRPH_DFQ_SIZE 4 6 GRPH_DFQ_MIN_FREE_ENTRIES 8 10 mmDCP1_GRPH_DFQ_STATUS 0 0x76e 4 0 2 GRPH_PRIMARY_DFQ_NUM_ENTRIES 0 3 GRPH_SECONDARY_DFQ_NUM_ENTRIES 4 7 GRPH_DFQ_RESET_FLAG 8 8 GRPH_DFQ_RESET_ACK 9 9 mmDCP1_GRPH_INTERRUPT_STATUS 0 0x76f 2 0 2 GRPH_PFLIP_INT_OCCURRED 0 0 GRPH_PFLIP_INT_CLEAR 8 8 mmDCP1_GRPH_INTERRUPT_CONTROL 0 0x770 2 0 2 GRPH_PFLIP_INT_MASK 0 0 GRPH_PFLIP_INT_TYPE 8 8 mmDCP1_GRPH_SURFACE_ADDRESS_HIGH_INUSE 0 0x771 1 0 2 GRPH_SURFACE_ADDRESS_HIGH_INUSE 0 7 mmDCP1_GRPH_COMPRESS_SURFACE_ADDRESS 0 0x772 1 0 2 GRPH_COMPRESS_SURFACE_ADDRESS 8 31 mmDCP1_GRPH_COMPRESS_PITCH 0 0x773 1 0 2 GRPH_COMPRESS_PITCH 6 16 mmDCP1_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH 0 0x774 1 0 2 GRPH_COMPRESS_SURFACE_ADDRESS_HIGH 0 7 mmDCP1_GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT 0 0x775 1 0 2 GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT 0 7 mmDCP1_PRESCALE_GRPH_CONTROL 0 0x776 5 0 2 GRPH_PRESCALE_SELECT 0 0 GRPH_PRESCALE_R_SIGN 1 1 GRPH_PRESCALE_G_SIGN 2 2 GRPH_PRESCALE_B_SIGN 3 3 GRPH_PRESCALE_BYPASS 4 4 mmDCP1_PRESCALE_VALUES_GRPH_R 0 0x777 2 0 2 GRPH_PRESCALE_BIAS_R 0 15 GRPH_PRESCALE_SCALE_R 16 31 mmDCP1_PRESCALE_VALUES_GRPH_G 0 0x778 2 0 2 GRPH_PRESCALE_BIAS_G 0 15 GRPH_PRESCALE_SCALE_G 16 31 mmDCP1_PRESCALE_VALUES_GRPH_B 0 0x779 2 0 2 GRPH_PRESCALE_BIAS_B 0 15 GRPH_PRESCALE_SCALE_B 16 31 mmDCP1_INPUT_CSC_CONTROL 0 0x77a 1 0 2 INPUT_CSC_GRPH_MODE 0 1 mmDCP1_INPUT_CSC_C11_C12 0 0x77b 2 0 2 INPUT_CSC_C11 0 15 INPUT_CSC_C12 16 31 mmDCP1_INPUT_CSC_C13_C14 0 0x77c 2 0 2 INPUT_CSC_C13 0 15 INPUT_CSC_C14 16 31 mmDCP1_INPUT_CSC_C21_C22 0 0x77d 2 0 2 INPUT_CSC_C21 0 15 INPUT_CSC_C22 16 31 mmDCP1_INPUT_CSC_C23_C24 0 0x77e 2 0 2 INPUT_CSC_C23 0 15 INPUT_CSC_C24 16 31 mmDCP1_INPUT_CSC_C31_C32 0 0x77f 2 0 2 INPUT_CSC_C31 0 15 INPUT_CSC_C32 16 31 mmDCP1_INPUT_CSC_C33_C34 0 0x780 2 0 2 INPUT_CSC_C33 0 15 INPUT_CSC_C34 16 31 mmDCP1_OUTPUT_CSC_CONTROL 0 0x781 1 0 2 OUTPUT_CSC_GRPH_MODE 0 2 mmDCP1_OUTPUT_CSC_C11_C12 0 0x782 2 0 2 OUTPUT_CSC_C11 0 15 OUTPUT_CSC_C12 16 31 mmDCP1_OUTPUT_CSC_C13_C14 0 0x783 2 0 2 OUTPUT_CSC_C13 0 15 OUTPUT_CSC_C14 16 31 mmDCP1_OUTPUT_CSC_C21_C22 0 0x784 2 0 2 OUTPUT_CSC_C21 0 15 OUTPUT_CSC_C22 16 31 mmDCP1_OUTPUT_CSC_C23_C24 0 0x785 2 0 2 OUTPUT_CSC_C23 0 15 OUTPUT_CSC_C24 16 31 mmDCP1_OUTPUT_CSC_C31_C32 0 0x786 2 0 2 OUTPUT_CSC_C31 0 15 OUTPUT_CSC_C32 16 31 mmDCP1_OUTPUT_CSC_C33_C34 0 0x787 2 0 2 OUTPUT_CSC_C33 0 15 OUTPUT_CSC_C34 16 31 mmDCP1_COMM_MATRIXA_TRANS_C11_C12 0 0x788 2 0 2 COMM_MATRIXA_TRANS_C11 0 15 COMM_MATRIXA_TRANS_C12 16 31 mmDCP1_COMM_MATRIXA_TRANS_C13_C14 0 0x789 2 0 2 COMM_MATRIXA_TRANS_C13 0 15 COMM_MATRIXA_TRANS_C14 16 31 mmDCP1_COMM_MATRIXA_TRANS_C21_C22 0 0x78a 2 0 2 COMM_MATRIXA_TRANS_C21 0 15 COMM_MATRIXA_TRANS_C22 16 31 mmDCP1_COMM_MATRIXA_TRANS_C23_C24 0 0x78b 2 0 2 COMM_MATRIXA_TRANS_C23 0 15 COMM_MATRIXA_TRANS_C24 16 31 mmDCP1_COMM_MATRIXA_TRANS_C31_C32 0 0x78c 2 0 2 COMM_MATRIXA_TRANS_C31 0 15 COMM_MATRIXA_TRANS_C32 16 31 mmDCP1_COMM_MATRIXA_TRANS_C33_C34 0 0x78d 2 0 2 COMM_MATRIXA_TRANS_C33 0 15 COMM_MATRIXA_TRANS_C34 16 31 mmDCP1_COMM_MATRIXB_TRANS_C11_C12 0 0x78e 2 0 2 COMM_MATRIXB_TRANS_C11 0 15 COMM_MATRIXB_TRANS_C12 16 31 mmDCP1_COMM_MATRIXB_TRANS_C13_C14 0 0x78f 2 0 2 COMM_MATRIXB_TRANS_C13 0 15 COMM_MATRIXB_TRANS_C14 16 31 mmDCP1_COMM_MATRIXB_TRANS_C21_C22 0 0x790 2 0 2 COMM_MATRIXB_TRANS_C21 0 15 COMM_MATRIXB_TRANS_C22 16 31 mmDCP1_COMM_MATRIXB_TRANS_C23_C24 0 0x791 2 0 2 COMM_MATRIXB_TRANS_C23 0 15 COMM_MATRIXB_TRANS_C24 16 31 mmDCP1_COMM_MATRIXB_TRANS_C31_C32 0 0x792 2 0 2 COMM_MATRIXB_TRANS_C31 0 15 COMM_MATRIXB_TRANS_C32 16 31 mmDCP1_COMM_MATRIXB_TRANS_C33_C34 0 0x793 2 0 2 COMM_MATRIXB_TRANS_C33 0 15 COMM_MATRIXB_TRANS_C34 16 31 mmDCP1_DENORM_CONTROL 0 0x794 2 0 2 DENORM_MODE 0 2 DENORM_14BIT_OUT 4 4 mmDCP1_OUT_ROUND_CONTROL 0 0x795 1 0 2 OUT_ROUND_TRUNC_MODE 0 3 mmDCP1_OUT_CLAMP_CONTROL_R_CR 0 0x796 2 0 2 OUT_CLAMP_MAX_R_CR 0 13 OUT_CLAMP_MIN_R_CR 16 29 mmDCP1_OUT_CLAMP_CONTROL_G_Y 0 0x797 2 0 2 OUT_CLAMP_MAX_G_Y 0 13 OUT_CLAMP_MIN_G_Y 16 29 mmDCP1_OUT_CLAMP_CONTROL_B_CB 0 0x798 2 0 2 OUT_CLAMP_MAX_B_CB 0 13 OUT_CLAMP_MIN_B_CB 16 29 mmDCP1_KEY_CONTROL 0 0x799 1 0 2 KEY_MODE 1 2 mmDCP1_KEY_RANGE_ALPHA 0 0x79a 2 0 2 KEY_ALPHA_LOW 0 15 KEY_ALPHA_HIGH 16 31 mmDCP1_KEY_RANGE_RED 0 0x79b 2 0 2 KEY_RED_LOW 0 15 KEY_RED_HIGH 16 31 mmDCP1_KEY_RANGE_GREEN 0 0x79c 2 0 2 KEY_GREEN_LOW 0 15 KEY_GREEN_HIGH 16 31 mmDCP1_KEY_RANGE_BLUE 0 0x79d 2 0 2 KEY_BLUE_LOW 0 15 KEY_BLUE_HIGH 16 31 mmDCP1_DEGAMMA_CONTROL 0 0x79e 3 0 2 GRPH_DEGAMMA_MODE 0 1 CURSOR2_DEGAMMA_MODE 8 9 CURSOR_DEGAMMA_MODE 12 13 mmDCP1_GAMUT_REMAP_CONTROL 0 0x79f 1 0 2 GRPH_GAMUT_REMAP_MODE 0 1 mmDCP1_GAMUT_REMAP_C11_C12 0 0x7a0 2 0 2 GAMUT_REMAP_C11 0 15 GAMUT_REMAP_C12 16 31 mmDCP1_GAMUT_REMAP_C13_C14 0 0x7a1 2 0 2 GAMUT_REMAP_C13 0 15 GAMUT_REMAP_C14 16 31 mmDCP1_GAMUT_REMAP_C21_C22 0 0x7a2 2 0 2 GAMUT_REMAP_C21 0 15 GAMUT_REMAP_C22 16 31 mmDCP1_GAMUT_REMAP_C23_C24 0 0x7a3 2 0 2 GAMUT_REMAP_C23 0 15 GAMUT_REMAP_C24 16 31 mmDCP1_GAMUT_REMAP_C31_C32 0 0x7a4 2 0 2 GAMUT_REMAP_C31 0 15 GAMUT_REMAP_C32 16 31 mmDCP1_GAMUT_REMAP_C33_C34 0 0x7a5 2 0 2 GAMUT_REMAP_C33 0 15 GAMUT_REMAP_C34 16 31 mmDCP1_DCP_SPATIAL_DITHER_CNTL 0 0x7a6 6 0 2 DCP_SPATIAL_DITHER_EN 0 0 DCP_SPATIAL_DITHER_MODE 4 5 DCP_SPATIAL_DITHER_DEPTH 6 7 DCP_FRAME_RANDOM_ENABLE 8 8 DCP_RGB_RANDOM_ENABLE 9 9 DCP_HIGHPASS_RANDOM_ENABLE 10 10 mmDCP1_DCP_RANDOM_SEEDS 0 0x7a7 3 0 2 DCP_RAND_R_SEED 0 7 DCP_RAND_G_SEED 8 15 DCP_RAND_B_SEED 16 23 mmDCP1_DCP_FP_CONVERTED_FIELD 0 0x7a8 2 0 2 DCP_FP_CONVERTED_FIELD_DATA 0 17 DCP_FP_CONVERTED_FIELD_INDEX 20 26 mmDCP1_CUR_CONTROL 0 0x7a9 8 0 2 CURSOR_EN 0 0 CUR_INV_TRANS_CLAMP 4 4 CURSOR_MODE 8 9 CURSOR_MAX_OUTSTANDING_GROUP_NUM 11 11 CURSOR_BUSY_START_LINE_POSITION 12 15 CURSOR_2X_MAGNIFY 16 16 CURSOR_FORCE_MC_ON 20 20 CURSOR_URGENT_CONTROL 24 26 mmDCP1_CUR_SURFACE_ADDRESS 0 0x7aa 1 0 2 CURSOR_SURFACE_ADDRESS 0 31 mmDCP1_CUR_SIZE 0 0x7ab 2 0 2 CURSOR_HEIGHT 0 6 CURSOR_WIDTH 16 22 mmDCP1_CUR_SURFACE_ADDRESS_HIGH 0 0x7ac 1 0 2 CURSOR_SURFACE_ADDRESS_HIGH 0 7 mmDCP1_CUR_POSITION 0 0x7ad 2 0 2 CURSOR_Y_POSITION 0 13 CURSOR_X_POSITION 16 29 mmDCP1_CUR_HOT_SPOT 0 0x7ae 2 0 2 CURSOR_HOT_SPOT_Y 0 6 CURSOR_HOT_SPOT_X 16 22 mmDCP1_CUR_COLOR1 0 0x7af 3 0 2 CUR_COLOR1_BLUE 0 7 CUR_COLOR1_GREEN 8 15 CUR_COLOR1_RED 16 23 mmDCP1_CUR_COLOR2 0 0x7b0 3 0 2 CUR_COLOR2_BLUE 0 7 CUR_COLOR2_GREEN 8 15 CUR_COLOR2_RED 16 23 mmDCP1_CUR_UPDATE 0 0x7b1 5 0 2 CURSOR_UPDATE_PENDING 0 0 CURSOR_UPDATE_TAKEN 1 1 CURSOR_UPDATE_LOCK 16 16 CURSOR_DISABLE_MULTIPLE_UPDATE 24 24 CURSOR_UPDATE_STEREO_MODE 25 26 mmDCP1_CUR_REQUEST_FILTER_CNTL 0 0x7bb 1 0 2 CUR_REQUEST_FILTER_DIS 0 0 mmDCP1_CUR_STEREO_CONTROL 0 0x7bc 3 0 2 CURSOR_STEREO_EN 0 0 CURSOR_PRIMARY_OFFSET 4 13 CURSOR_SECONDARY_OFFSET 16 25 mmDCP1_DC_LUT_RW_MODE 0 0x7be 3 0 2 DC_LUT_RW_MODE 0 0 DC_LUT_ERROR 16 16 DC_LUT_ERROR_RST 17 17 mmDCP1_DC_LUT_RW_INDEX 0 0x7bf 1 0 2 DC_LUT_RW_INDEX 0 7 mmDCP1_DC_LUT_SEQ_COLOR 0 0x7c0 1 0 2 DC_LUT_SEQ_COLOR 0 15 mmDCP1_DC_LUT_PWL_DATA 0 0x7c1 2 0 2 DC_LUT_BASE 0 15 DC_LUT_DELTA 16 31 mmDCP1_DC_LUT_30_COLOR 0 0x7c2 3 0 2 DC_LUT_COLOR_10_BLUE 0 9 DC_LUT_COLOR_10_GREEN 10 19 DC_LUT_COLOR_10_RED 20 29 mmDCP1_DC_LUT_VGA_ACCESS_ENABLE 0 0x7c3 1 0 2 DC_LUT_VGA_ACCESS_ENABLE 0 0 mmDCP1_DC_LUT_WRITE_EN_MASK 0 0x7c4 1 0 2 DC_LUT_WRITE_EN_MASK 0 2 mmDCP1_DC_LUT_AUTOFILL 0 0x7c5 2 0 2 DC_LUT_AUTOFILL 0 0 DC_LUT_AUTOFILL_DONE 1 1 mmDCP1_DC_LUT_CONTROL 0 0x7c6 12 0 2 DC_LUT_INC_B 0 3 DC_LUT_DATA_B_SIGNED_EN 4 4 DC_LUT_DATA_B_FLOAT_POINT_EN 5 5 DC_LUT_DATA_B_FORMAT 6 7 DC_LUT_INC_G 8 11 DC_LUT_DATA_G_SIGNED_EN 12 12 DC_LUT_DATA_G_FLOAT_POINT_EN 13 13 DC_LUT_DATA_G_FORMAT 14 15 DC_LUT_INC_R 16 19 DC_LUT_DATA_R_SIGNED_EN 20 20 DC_LUT_DATA_R_FLOAT_POINT_EN 21 21 DC_LUT_DATA_R_FORMAT 22 23 mmDCP1_DC_LUT_BLACK_OFFSET_BLUE 0 0x7c7 1 0 2 DC_LUT_BLACK_OFFSET_BLUE 0 15 mmDCP1_DC_LUT_BLACK_OFFSET_GREEN 0 0x7c8 1 0 2 DC_LUT_BLACK_OFFSET_GREEN 0 15 mmDCP1_DC_LUT_BLACK_OFFSET_RED 0 0x7c9 1 0 2 DC_LUT_BLACK_OFFSET_RED 0 15 mmDCP1_DC_LUT_WHITE_OFFSET_BLUE 0 0x7ca 1 0 2 DC_LUT_WHITE_OFFSET_BLUE 0 15 mmDCP1_DC_LUT_WHITE_OFFSET_GREEN 0 0x7cb 1 0 2 DC_LUT_WHITE_OFFSET_GREEN 0 15 mmDCP1_DC_LUT_WHITE_OFFSET_RED 0 0x7cc 1 0 2 DC_LUT_WHITE_OFFSET_RED 0 15 mmDCP1_DCP_CRC_CONTROL 0 0x7cd 3 0 2 DCP_CRC_ENABLE 0 0 DCP_CRC_SOURCE_SEL 2 4 DCP_CRC_LINE_SEL 8 9 mmDCP1_DCP_CRC_MASK 0 0x7ce 1 0 2 DCP_CRC_MASK 0 31 mmDCP1_DCP_CRC_CURRENT 0 0x7cf 1 0 2 DCP_CRC_CURRENT 0 31 mmDCP1_DVMM_PTE_CONTROL 0 0x7d0 6 0 2 DVMM_USE_SINGLE_PTE 0 0 DVMM_PAGE_WIDTH 1 4 DVMM_PAGE_HEIGHT 5 8 DVMM_MIN_PTE_BEFORE_FLIP 9 18 DVMM_PTE_BUFFER_MODE0 20 20 DVMM_PTE_BUFFER_MODE1 21 21 mmDCP1_DCP_CRC_LAST 0 0x7d1 1 0 2 DCP_CRC_LAST 0 31 mmDCP1_DVMM_PTE_ARB_CONTROL 0 0x7d2 2 0 2 DVMM_PTE_REQ_PER_CHUNK 0 5 DVMM_MAX_PTE_REQ_OUTSTANDING 8 15 mmDCP1_GRPH_FLIP_RATE_CNTL 0 0x7d4 2 0 2 GRPH_FLIP_RATE 0 2 GRPH_FLIP_RATE_ENABLE 3 3 mmDCP1_DCP_GSL_CONTROL 0 0x7d5 11 0 2 DCP_GSL0_EN 0 0 DCP_GSL1_EN 1 1 DCP_GSL2_EN 2 2 DCP_GSL_HSYNC_FLIP_FORCE_DELAY 4 19 DCP_GSL_MASTER_EN 20 20 DCP_GSL_XDMA_GROUP 21 22 DCP_GSL_XDMA_GROUP_UNDERFLOW_EN 23 23 DCP_GSL_SYNC_SOURCE 24 25 DCP_GSL_USE_CHECKPOINT_WINDOW_IN_VSYNC 26 26 DCP_GSL_DELAY_SURFACE_UPDATE_PENDING 27 27 DCP_GSL_HSYNC_FLIP_CHECK_DELAY 28 31 mmDCP1_DCP_LB_DATA_GAP_BETWEEN_CHUNK 0 0x7d6 2 0 2 DCP_LB_GAP_BETWEEN_CHUNK_20BPP 0 3 DCP_LB_GAP_BETWEEN_CHUNK_30BPP 4 8 mmDCP1_GRPH_STEREOSYNC_FLIP 0 0x7dc 5 0 2 GRPH_STEREOSYNC_FLIP_EN 0 0 GRPH_STEREOSYNC_FLIP_MODE 8 9 GRPH_PRIMARY_SURFACE_PENDING 16 16 GRPH_SECONDARY_SURFACE_PENDING 17 17 GRPH_STEREOSYNC_SELECT_DISABLE 28 28 mmDCP1_HW_ROTATION 0 0x7de 1 0 2 GRPH_ROTATION_ANGLE 0 2 mmDCP1_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL 0 0x7df 3 0 2 GRPH_XDMA_CACHE_UNDERFLOW_CNT_EN 0 0 GRPH_XDMA_CACHE_UNDERFLOW_CNT_MODE 1 1 GRPH_XDMA_CACHE_UNDERFLOW_FRAME_CNT 4 16 mmDCP1_REGAMMA_CONTROL 0 0x7e0 1 0 2 GRPH_REGAMMA_MODE 0 2 mmDCP1_REGAMMA_LUT_INDEX 0 0x7e1 1 0 2 REGAMMA_LUT_INDEX 0 8 mmDCP1_REGAMMA_LUT_DATA 0 0x7e2 1 0 2 REGAMMA_LUT_DATA 0 18 mmDCP1_REGAMMA_LUT_WRITE_EN_MASK 0 0x7e3 1 0 2 REGAMMA_LUT_WRITE_EN_MASK 0 2 mmDCP1_REGAMMA_CNTLA_START_CNTL 0 0x7e4 2 0 2 REGAMMA_CNTLA_EXP_REGION_START 0 17 REGAMMA_CNTLA_EXP_REGION_START_SEGMENT 20 26 mmDCP1_REGAMMA_CNTLA_SLOPE_CNTL 0 0x7e5 1 0 2 REGAMMA_CNTLA_EXP_REGION_LINEAR_SLOPE 0 17 mmDCP1_REGAMMA_CNTLA_END_CNTL1 0 0x7e6 1 0 2 REGAMMA_CNTLA_EXP_REGION_END 0 15 mmDCP1_REGAMMA_CNTLA_END_CNTL2 0 0x7e7 2 0 2 REGAMMA_CNTLA_EXP_REGION_END_SLOPE 0 15 REGAMMA_CNTLA_EXP_REGION_END_BASE 16 31 mmDCP1_REGAMMA_CNTLA_REGION_0_1 0 0x7e8 4 0 2 REGAMMA_CNTLA_EXP_REGION0_LUT_OFFSET 0 8 REGAMMA_CNTLA_EXP_REGION0_NUM_SEGMENTS 12 14 REGAMMA_CNTLA_EXP_REGION1_LUT_OFFSET 16 24 REGAMMA_CNTLA_EXP_REGION1_NUM_SEGMENTS 28 30 mmDCP1_REGAMMA_CNTLA_REGION_2_3 0 0x7e9 4 0 2 REGAMMA_CNTLA_EXP_REGION2_LUT_OFFSET 0 8 REGAMMA_CNTLA_EXP_REGION2_NUM_SEGMENTS 12 14 REGAMMA_CNTLA_EXP_REGION3_LUT_OFFSET 16 24 REGAMMA_CNTLA_EXP_REGION3_NUM_SEGMENTS 28 30 mmDCP1_REGAMMA_CNTLA_REGION_4_5 0 0x7ea 4 0 2 REGAMMA_CNTLA_EXP_REGION4_LUT_OFFSET 0 8 REGAMMA_CNTLA_EXP_REGION4_NUM_SEGMENTS 12 14 REGAMMA_CNTLA_EXP_REGION5_LUT_OFFSET 16 24 REGAMMA_CNTLA_EXP_REGION5_NUM_SEGMENTS 28 30 mmDCP1_REGAMMA_CNTLA_REGION_6_7 0 0x7eb 4 0 2 REGAMMA_CNTLA_EXP_REGION6_LUT_OFFSET 0 8 REGAMMA_CNTLA_EXP_REGION6_NUM_SEGMENTS 12 14 REGAMMA_CNTLA_EXP_REGION7_LUT_OFFSET 16 24 REGAMMA_CNTLA_EXP_REGION7_NUM_SEGMENTS 28 30 mmDCP1_REGAMMA_CNTLA_REGION_8_9 0 0x7ec 4 0 2 REGAMMA_CNTLA_EXP_REGION8_LUT_OFFSET 0 8 REGAMMA_CNTLA_EXP_REGION8_NUM_SEGMENTS 12 14 REGAMMA_CNTLA_EXP_REGION9_LUT_OFFSET 16 24 REGAMMA_CNTLA_EXP_REGION9_NUM_SEGMENTS 28 30 mmDCP1_REGAMMA_CNTLA_REGION_10_11 0 0x7ed 4 0 2 REGAMMA_CNTLA_EXP_REGION10_LUT_OFFSET 0 8 REGAMMA_CNTLA_EXP_REGION10_NUM_SEGMENTS 12 14 REGAMMA_CNTLA_EXP_REGION11_LUT_OFFSET 16 24 REGAMMA_CNTLA_EXP_REGION11_NUM_SEGMENTS 28 30 mmDCP1_REGAMMA_CNTLA_REGION_12_13 0 0x7ee 4 0 2 REGAMMA_CNTLA_EXP_REGION12_LUT_OFFSET 0 8 REGAMMA_CNTLA_EXP_REGION12_NUM_SEGMENTS 12 14 REGAMMA_CNTLA_EXP_REGION13_LUT_OFFSET 16 24 REGAMMA_CNTLA_EXP_REGION13_NUM_SEGMENTS 28 30 mmDCP1_REGAMMA_CNTLA_REGION_14_15 0 0x7ef 4 0 2 REGAMMA_CNTLA_EXP_REGION14_LUT_OFFSET 0 8 REGAMMA_CNTLA_EXP_REGION14_NUM_SEGMENTS 12 14 REGAMMA_CNTLA_EXP_REGION15_LUT_OFFSET 16 24 REGAMMA_CNTLA_EXP_REGION15_NUM_SEGMENTS 28 30 mmDCP1_REGAMMA_CNTLB_START_CNTL 0 0x7f0 2 0 2 REGAMMA_CNTLB_EXP_REGION_START 0 17 REGAMMA_CNTLB_EXP_REGION_START_SEGMENT 20 26 mmDCP1_REGAMMA_CNTLB_SLOPE_CNTL 0 0x7f1 1 0 2 REGAMMA_CNTLB_EXP_REGION_LINEAR_SLOPE 0 17 mmDCP1_REGAMMA_CNTLB_END_CNTL1 0 0x7f2 1 0 2 REGAMMA_CNTLB_EXP_REGION_END 0 15 mmDCP1_REGAMMA_CNTLB_END_CNTL2 0 0x7f3 2 0 2 REGAMMA_CNTLB_EXP_REGION_END_SLOPE 0 15 REGAMMA_CNTLB_EXP_REGION_END_BASE 16 31 mmDCP1_REGAMMA_CNTLB_REGION_0_1 0 0x7f4 4 0 2 REGAMMA_CNTLB_EXP_REGION0_LUT_OFFSET 0 8 REGAMMA_CNTLB_EXP_REGION0_NUM_SEGMENTS 12 14 REGAMMA_CNTLB_EXP_REGION1_LUT_OFFSET 16 24 REGAMMA_CNTLB_EXP_REGION1_NUM_SEGMENTS 28 30 mmDCP1_REGAMMA_CNTLB_REGION_2_3 0 0x7f5 4 0 2 REGAMMA_CNTLB_EXP_REGION2_LUT_OFFSET 0 8 REGAMMA_CNTLB_EXP_REGION2_NUM_SEGMENTS 12 14 REGAMMA_CNTLB_EXP_REGION3_LUT_OFFSET 16 24 REGAMMA_CNTLB_EXP_REGION3_NUM_SEGMENTS 28 30 mmDCP1_REGAMMA_CNTLB_REGION_4_5 0 0x7f6 4 0 2 REGAMMA_CNTLB_EXP_REGION4_LUT_OFFSET 0 8 REGAMMA_CNTLB_EXP_REGION4_NUM_SEGMENTS 12 14 REGAMMA_CNTLB_EXP_REGION5_LUT_OFFSET 16 24 REGAMMA_CNTLB_EXP_REGION5_NUM_SEGMENTS 28 30 mmDCP1_REGAMMA_CNTLB_REGION_6_7 0 0x7f7 4 0 2 REGAMMA_CNTLB_EXP_REGION6_LUT_OFFSET 0 8 REGAMMA_CNTLB_EXP_REGION6_NUM_SEGMENTS 12 14 REGAMMA_CNTLB_EXP_REGION7_LUT_OFFSET 16 24 REGAMMA_CNTLB_EXP_REGION7_NUM_SEGMENTS 28 30 mmDCP1_REGAMMA_CNTLB_REGION_8_9 0 0x7f8 4 0 2 REGAMMA_CNTLB_EXP_REGION8_LUT_OFFSET 0 8 REGAMMA_CNTLB_EXP_REGION8_NUM_SEGMENTS 12 14 REGAMMA_CNTLB_EXP_REGION9_LUT_OFFSET 16 24 REGAMMA_CNTLB_EXP_REGION9_NUM_SEGMENTS 28 30 mmDCP1_REGAMMA_CNTLB_REGION_10_11 0 0x7f9 4 0 2 REGAMMA_CNTLB_EXP_REGION10_LUT_OFFSET 0 8 REGAMMA_CNTLB_EXP_REGION10_NUM_SEGMENTS 12 14 REGAMMA_CNTLB_EXP_REGION11_LUT_OFFSET 16 24 REGAMMA_CNTLB_EXP_REGION11_NUM_SEGMENTS 28 30 mmDCP1_REGAMMA_CNTLB_REGION_12_13 0 0x7fa 4 0 2 REGAMMA_CNTLB_EXP_REGION12_LUT_OFFSET 0 8 REGAMMA_CNTLB_EXP_REGION12_NUM_SEGMENTS 12 14 REGAMMA_CNTLB_EXP_REGION13_LUT_OFFSET 16 24 REGAMMA_CNTLB_EXP_REGION13_NUM_SEGMENTS 28 30 mmDCP1_REGAMMA_CNTLB_REGION_14_15 0 0x7fb 4 0 2 REGAMMA_CNTLB_EXP_REGION14_LUT_OFFSET 0 8 REGAMMA_CNTLB_EXP_REGION14_NUM_SEGMENTS 12 14 REGAMMA_CNTLB_EXP_REGION15_LUT_OFFSET 16 24 REGAMMA_CNTLB_EXP_REGION15_NUM_SEGMENTS 28 30 mmDCP1_ALPHA_CONTROL 0 0x7fc 2 0 2 ALPHA_ROUND_TRUNC_MODE 0 0 CURSOR_ALPHA_BLND_ENA 1 1 mmDCP1_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS 0 0x7fd 1 0 2 GRPH_XDMA_RECOVERY_SURFACE_ADDRESS 8 31 mmDCP1_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH 0 0x7fe 1 0 2 GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH 0 7 mmDCP1_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS 0 0x7ff 7 0 2 GRPH_XDMA_CACHE_UNDERFLOW_CNT 0 19 GRPH_XDMA_CACHE_UNDERFLOW_CNT_STATUS 24 24 GRPH_XDMA_CACHE_UNDERFLOW_FRAME_MASK 25 25 GRPH_XDMA_CACHE_UNDERFLOW_FRAME_ACK 26 26 GRPH_XDMA_CACHE_UNDERFLOW_INT 28 28 GRPH_XDMA_CACHE_UNDERFLOW_INT_MASK 29 29 GRPH_XDMA_CACHE_UNDERFLOW_INT_ACK 30 30 mmDCP1_GRPH_XDMA_FLIP_TIMEOUT 0 0x800 3 0 2 GRPH_XDMA_FLIP_TIMEOUT_STATUS 0 0 GRPH_XDMA_FLIP_TIMEOUT_MASK 1 1 GRPH_XDMA_FLIP_TIMEOUT_ACK 2 2 mmDCP1_GRPH_XDMA_FLIP_AVG_DELAY 0 0x801 2 0 2 GRPH_XDMA_FLIP_AVG_DELAY 0 15 GRPH_XDMA_FLIP_AVG_PERIOD 16 23 mmDCP1_GRPH_SURFACE_COUNTER_CONTROL 0 0x802 3 0 2 GRPH_SURFACE_COUNTER_EN 0 0 GRPH_SURFACE_COUNTER_EVENT_SELECT 1 4 GRPH_SURFACE_COUNTER_ERR_WRAP_OCCURED 9 9 mmDCP1_GRPH_SURFACE_COUNTER_OUTPUT 0 0x803 2 0 2 GRPH_SURFACE_COUNTER_MIN 0 15 GRPH_SURFACE_COUNTER_MAX 16 31 mmLB1_LB_DATA_FORMAT 0 0x81a 9 0 2 PIXEL_DEPTH 0 1 PIXEL_EXPAN_MODE 2 2 INTERLEAVE_EN 3 3 PIXEL_REDUCE_MODE 4 4 DYNAMIC_PIXEL_DEPTH 5 5 PREFILL_EN 8 8 PREFETCH 12 12 REQUEST_MODE 24 24 ALPHA_EN 31 31 mmLB1_LB_MEMORY_CTRL 0 0x81b 3 0 2 LB_MEMORY_SIZE 0 12 LB_NUM_PARTITIONS 16 19 LB_MEMORY_CONFIG 20 21 mmLB1_LB_MEMORY_SIZE_STATUS 0 0x81c 1 0 2 LB_MEMORY_SIZE_STATUS 0 12 mmLB1_LB_DESKTOP_HEIGHT 0 0x81d 1 0 2 DESKTOP_HEIGHT 0 14 mmLB1_LB_VLINE_START_END 0 0x81e 3 0 2 VLINE_START 0 13 VLINE_END 16 30 VLINE_INV 31 31 mmLB1_LB_VLINE2_START_END 0 0x81f 3 0 2 VLINE2_START 0 13 VLINE2_END 16 30 VLINE2_INV 31 31 mmLB1_LB_V_COUNTER 0 0x820 1 0 2 V_COUNTER 0 14 mmLB1_LB_SNAPSHOT_V_COUNTER 0 0x821 1 0 2 SNAPSHOT_V_COUNTER 0 14 mmLB1_LB_INTERRUPT_MASK 0 0x822 3 0 2 VBLANK_INTERRUPT_MASK 0 0 VLINE_INTERRUPT_MASK 4 4 VLINE2_INTERRUPT_MASK 8 8 mmLB1_LB_VLINE_STATUS 0 0x823 5 0 2 VLINE_OCCURRED 0 0 VLINE_ACK 4 4 VLINE_STAT 12 12 VLINE_INTERRUPT 16 16 VLINE_INTERRUPT_TYPE 17 17 mmLB1_LB_VLINE2_STATUS 0 0x824 5 0 2 VLINE2_OCCURRED 0 0 VLINE2_ACK 4 4 VLINE2_STAT 12 12 VLINE2_INTERRUPT 16 16 VLINE2_INTERRUPT_TYPE 17 17 mmLB1_LB_VBLANK_STATUS 0 0x825 5 0 2 VBLANK_OCCURRED 0 0 VBLANK_ACK 4 4 VBLANK_STAT 12 12 VBLANK_INTERRUPT 16 16 VBLANK_INTERRUPT_TYPE 17 17 mmLB1_LB_SYNC_RESET_SEL 0 0x826 4 0 2 LB_SYNC_RESET_SEL 0 1 LB_SYNC_RESET_SEL2 4 4 LB_SYNC_RESET_DELAY 8 15 LB_SYNC_DURATION 22 23 mmLB1_LB_BLACK_KEYER_R_CR 0 0x827 1 0 2 LB_BLACK_KEYER_R_CR 4 15 mmLB1_LB_BLACK_KEYER_G_Y 0 0x828 1 0 2 LB_BLACK_KEYER_G_Y 4 15 mmLB1_LB_BLACK_KEYER_B_CB 0 0x829 1 0 2 LB_BLACK_KEYER_B_CB 4 15 mmLB1_LB_KEYER_COLOR_CTRL 0 0x82a 2 0 2 LB_KEYER_COLOR_EN 0 0 LB_KEYER_COLOR_REP_EN 8 8 mmLB1_LB_KEYER_COLOR_R_CR 0 0x82b 1 0 2 LB_KEYER_COLOR_R_CR 4 15 mmLB1_LB_KEYER_COLOR_G_Y 0 0x82c 1 0 2 LB_KEYER_COLOR_G_Y 4 15 mmLB1_LB_KEYER_COLOR_B_CB 0 0x82d 1 0 2 LB_KEYER_COLOR_B_CB 4 15 mmLB1_LB_KEYER_COLOR_REP_R_CR 0 0x82e 1 0 2 LB_KEYER_COLOR_REP_R_CR 4 15 mmLB1_LB_KEYER_COLOR_REP_G_Y 0 0x82f 1 0 2 LB_KEYER_COLOR_REP_G_Y 4 15 mmLB1_LB_KEYER_COLOR_REP_B_CB 0 0x830 1 0 2 LB_KEYER_COLOR_REP_B_CB 4 15 mmLB1_LB_BUFFER_LEVEL_STATUS 0 0x831 4 0 2 REQ_FIFO_LEVEL 0 5 REQ_FIFO_FULL_CNTL 10 15 DATA_BUFFER_LEVEL 16 27 DATA_FIFO_FULL_CNTL 28 31 mmLB1_LB_BUFFER_URGENCY_CTRL 0 0x832 2 0 2 LB_BUFFER_URGENCY_MARK_ON 0 11 LB_BUFFER_URGENCY_MARK_OFF 16 27 mmLB1_LB_BUFFER_URGENCY_STATUS 0 0x833 2 0 2 LB_BUFFER_URGENCY_LEVEL 0 11 LB_BUFFER_URGENCY_STAT 16 16 mmLB1_LB_BUFFER_STATUS 0 0x834 7 0 2 LB_BUFFER_EMPTY_MARGIN 0 3 LB_BUFFER_EMPTY_STAT 4 4 LB_BUFFER_EMPTY_OCCURRED 8 8 LB_BUFFER_EMPTY_ACK 12 12 LB_BUFFER_FULL_STAT 16 16 LB_BUFFER_FULL_OCCURRED 20 20 LB_BUFFER_FULL_ACK 24 24 mmLB1_LB_NO_OUTSTANDING_REQ_STATUS 0 0x835 1 0 2 LB_NO_OUTSTANDING_REQ_STAT 0 0 mmLB1_MVP_AFR_FLIP_MODE 0 0x836 1 0 2 MVP_AFR_FLIP_MODE 0 1 mmLB1_MVP_AFR_FLIP_FIFO_CNTL 0 0x837 4 0 2 MVP_AFR_FLIP_FIFO_NUM_ENTRIES 0 3 MVP_AFR_FLIP_FIFO_RESET 4 4 MVP_AFR_FLIP_FIFO_RESET_FLAG 8 8 MVP_AFR_FLIP_FIFO_RESET_ACK 12 12 mmLB1_MVP_FLIP_LINE_NUM_INSERT 0 0x838 4 0 2 MVP_FLIP_LINE_NUM_INSERT_MODE 0 1 MVP_FLIP_LINE_NUM_INSERT 8 22 MVP_FLIP_LINE_NUM_OFFSET 24 29 MVP_FLIP_AUTO_ENABLE 30 30 mmLB1_DC_MVP_LB_CONTROL 0 0x839 7 0 2 MVP_SWAP_LOCK_IN_MODE 0 1 DC_MVP_SWAP_LOCK_OUT_SEL 8 8 DC_MVP_SWAP_LOCK_OUT_FORCE_ONE 12 12 DC_MVP_SWAP_LOCK_OUT_FORCE_ZERO 16 16 DC_MVP_SWAP_LOCK_STATUS 20 20 DC_MVP_SWAP_LOCK_IN_CAP 28 28 DC_MVP_SPARE_FLOPS 31 31 mmDCFE1_DCFE_CLOCK_CONTROL 0 0x85a 7 0 2 DISPCLK_R_DCFE_GATE_DISABLE 4 4 DISPCLK_G_DCP_GATE_DISABLE 8 8 DISPCLK_G_SCL_GATE_DISABLE 12 12 DISPCLK_G_PSCL_GATE_DISABLE 15 15 DISPCLK_G_PIPE_REQUEST_DIS_GATE_DISABLE 17 17 DCFE_TEST_CLK_SEL 24 28 DCFE_CLOCK_ENABLE 31 31 mmDCFE1_DCFE_SOFT_RESET 0 0x85b 6 0 2 DCP_PIXPIPE_SOFT_RESET 0 0 DCP_REQ_SOFT_RESET 1 1 SCL_ALU_SOFT_RESET 2 2 SCL_SOFT_RESET 3 3 CRTC_SOFT_RESET 4 4 PSCL_SOFT_RESET 5 5 mmDCFE1_DCFE_MEM_PWR_CTRL 0 0x85d 20 0 2 DCP_LUT_MEM_PWR_FORCE 0 1 DCP_LUT_MEM_PWR_DIS 2 2 DCP_REGAMMA_MEM_PWR_FORCE 3 4 DCP_REGAMMA_MEM_PWR_DIS 5 5 SCL_COEFF_MEM_PWR_FORCE 6 7 SCL_COEFF_MEM_PWR_DIS 8 8 DCP_CURSOR_MEM_PWR_FORCE 9 10 DCP_CURSOR_MEM_PWR_DIS 11 11 LB0_ALPHA_MEM_PWR_FORCE 12 13 LB0_ALPHA_MEM_PWR_DIS 14 14 LB1_ALPHA_MEM_PWR_FORCE 15 16 LB1_ALPHA_MEM_PWR_DIS 17 17 LB2_ALPHA_MEM_PWR_FORCE 18 19 LB2_ALPHA_MEM_PWR_DIS 20 20 LB0_MEM_PWR_FORCE 21 22 LB0_MEM_PWR_DIS 23 23 LB1_MEM_PWR_FORCE 24 25 LB1_MEM_PWR_DIS 26 26 LB2_MEM_PWR_FORCE 27 28 LB2_MEM_PWR_DIS 29 29 mmDCFE1_DCFE_MEM_PWR_CTRL2 0 0x85e 12 0 2 DCP_LUT_MEM_PWR_MODE_SEL 0 1 DCP_REGAMMA_MEM_PWR_MODE_SEL 2 3 SCL_COEFF_MEM_PWR_MODE_SEL 4 5 DCP_CURSOR_MEM_PWR_MODE_SEL 6 7 LB_ALPHA_MEM_PWR_MODE_SEL 8 9 LB_MEM_PWR_MODE_SEL 10 11 DCP_CURSOR2_MEM_PWR_MODE_SEL 12 13 BLND_MEM_PWR_MODE_SEL 14 15 BLND_MEM_PWR_FORCE 16 17 BLND_MEM_PWR_DIS 18 18 DCP_CURSOR2_MEM_PWR_FORCE 21 22 DCP_CURSOR2_MEM_PWR_DIS 23 23 mmDCFE1_DCFE_MEM_PWR_STATUS 0 0x85f 12 0 2 DCP_LUT_MEM_PWR_STATE 0 1 DCP_REGAMMA_MEM_PWR_STATE 2 3 SCL_COEFF_MEM_PWR_STATE 4 5 DCP_CURSOR_MEM_PWR_STATE 6 7 DCP_CURSOR2_MEM_PWR_STATE 8 9 LB0_ALPHA_MEM_PWR_STATE 10 11 LB1_ALPHA_MEM_PWR_STATE 12 13 LB2_ALPHA_MEM_PWR_STATE 14 15 LB0_MEM_PWR_STATE 16 17 LB1_MEM_PWR_STATE 18 19 LB2_MEM_PWR_STATE 20 21 BLND_MEM_PWR_STATE 22 23 mmDCFE1_DCFE_MISC 0 0x860 1 0 2 DCFE_DPG_ALLOW_SR_ECO_EN 0 0 mmDCFE1_DCFE_FLUSH 0 0x861 5 0 2 FLUSH_OCCURED 0 0 CLEAR_FLUSH_OCCURED 1 1 FLUSH_DEEP 2 2 CLEAR_FLUSH_DEEP 3 3 ALL_MC_REQ_RET 4 4 mmDC_PERFMON4_PERFCOUNTER_CNTL 0 0x86e 13 0 2 PERFCOUNTER_EVENT_SEL 0 8 PERFCOUNTER_CVALUE_SEL 9 11 PERFCOUNTER_INC_MODE 12 14 PERFCOUNTER_HW_CNTL_SEL 15 15 PERFCOUNTER_RUNEN_MODE 16 16 PERFCOUNTER_CNTOFF_SEL 17 21 PERFCOUNTER_CNTOFF_START_DIS 22 22 PERFCOUNTER_RESTART_EN 23 23 PERFCOUNTER_INT_EN 24 24 PERFCOUNTER_OFF_MASK 25 25 PERFCOUNTER_ACTIVE 26 26 PERFCOUNTER_INT_TYPE 27 27 PERFCOUNTER_CNTL_SEL 29 31 mmDC_PERFMON4_PERFCOUNTER_CNTL2 0 0x86f 4 0 2 PERFCOUNTER_COUNTED_VALUE_TYPE 0 1 PERFCOUNTER_HW_STOP1_SEL 2 2 PERFCOUNTER_HW_STOP2_SEL 3 3 PERFCOUNTER_CNTL2_SEL 29 31 mmDC_PERFMON4_PERFCOUNTER_STATE 0 0x870 16 0 2 PERFCOUNTER_CNT0_STATE 0 1 PERFCOUNTER_STATE_SEL0 2 2 PERFCOUNTER_CNT1_STATE 4 5 PERFCOUNTER_STATE_SEL1 6 6 PERFCOUNTER_CNT2_STATE 8 9 PERFCOUNTER_STATE_SEL2 10 10 PERFCOUNTER_CNT3_STATE 12 13 PERFCOUNTER_STATE_SEL3 14 14 PERFCOUNTER_CNT4_STATE 16 17 PERFCOUNTER_STATE_SEL4 18 18 PERFCOUNTER_CNT5_STATE 20 21 PERFCOUNTER_STATE_SEL5 22 22 PERFCOUNTER_CNT6_STATE 24 25 PERFCOUNTER_STATE_SEL6 26 26 PERFCOUNTER_CNT7_STATE 28 29 PERFCOUNTER_STATE_SEL7 30 30 mmDC_PERFMON4_PERFMON_CNTL 0 0x871 6 0 2 PERFMON_STATE 0 1 PERFMON_RPT_COUNT 8 27 PERFMON_CNTOFF_AND_OR 28 28 PERFMON_CNTOFF_INT_EN 29 29 PERFMON_CNTOFF_INT_STATUS 30 30 PERFMON_CNTOFF_INT_ACK 31 31 mmDC_PERFMON4_PERFMON_CNTL2 0 0x872 4 0 2 PERFMON_CNTOFF_INT_TYPE 0 0 PERFMON_CLK_ENABLE 1 1 PERFMON_RUN_ENABLE_START_SEL 2 9 PERFMON_RUN_ENABLE_STOP_SEL 10 17 mmDC_PERFMON4_PERFMON_CVALUE_INT_MISC 0 0x873 17 0 2 PERFCOUNTER_INT0_STATUS 0 0 PERFCOUNTER_INT1_STATUS 1 1 PERFCOUNTER_INT2_STATUS 2 2 PERFCOUNTER_INT3_STATUS 3 3 PERFCOUNTER_INT4_STATUS 4 4 PERFCOUNTER_INT5_STATUS 5 5 PERFCOUNTER_INT6_STATUS 6 6 PERFCOUNTER_INT7_STATUS 7 7 PERFCOUNTER_INT0_ACK 8 8 PERFCOUNTER_INT1_ACK 9 9 PERFCOUNTER_INT2_ACK 10 10 PERFCOUNTER_INT3_ACK 11 11 PERFCOUNTER_INT4_ACK 12 12 PERFCOUNTER_INT5_ACK 13 13 PERFCOUNTER_INT6_ACK 14 14 PERFCOUNTER_INT7_ACK 15 15 PERFMON_CVALUE_HI 16 31 mmDC_PERFMON4_PERFMON_CVALUE_LOW 0 0x874 1 0 2 PERFMON_CVALUE_LOW 0 31 mmDC_PERFMON4_PERFMON_HI 0 0x875 2 0 2 PERFMON_HI 0 15 PERFMON_READ_SEL 29 31 mmDC_PERFMON4_PERFMON_LOW 0 0x876 1 0 2 PERFMON_LOW 0 31 mmDMIF_PG1_DPG_PIPE_ARBITRATION_CONTROL1 0 0x87a 2 0 2 PIXEL_DURATION 0 15 BASE_WEIGHT 16 31 mmDMIF_PG1_DPG_PIPE_ARBITRATION_CONTROL2 0 0x87b 2 0 2 TIME_WEIGHT 0 15 URGENCY_WEIGHT 16 31 mmDMIF_PG1_DPG_WATERMARK_MASK_CONTROL 0 0x87c 8 0 2 STUTTER_EXIT_SELF_REFRESH_WATERMARK_MASK 0 2 STUTTER_ENTER_SELF_REFRESH_WATERMARK_MASK 4 6 URGENCY_WATERMARK_MASK 8 10 URGENT_LEVEL_WATERMARK_MASK 12 14 PSTATE_CHANGE_WATERMARK_MASK 15 17 DISABLE_FLIP_URGENT 18 18 URGENT_LEVEL_RAMP_CONTROL 19 19 STATIC_URGENT_LEVEL 20 29 mmDMIF_PG1_DPG_PIPE_URGENCY_CONTROL 0 0x87d 2 0 2 URGENCY_LOW_WATERMARK 0 15 URGENCY_HIGH_WATERMARK 16 31 mmDMIF_PG1_DPG_PIPE_URGENT_LEVEL_CONTROL 0 0x87e 2 0 2 URGENT_LEVEL_LOW_WATERMARK 0 15 URGENT_LEVEL_HIGH_WATERMARK 16 31 mmDMIF_PG1_DPG_PIPE_STUTTER_CONTROL 0 0x87f 14 0 2 STUTTER_ENABLE 0 0 STUTTER_IGNORE_CURSOR 4 4 STUTTER_IGNORE_ICON 5 5 STUTTER_IGNORE_VGA 6 6 STUTTER_IGNORE_FBC 7 7 STUTTER_URGENT_IN_NOT_SELF_REFRESH 10 10 STUTTER_SELF_REFRESH_FORCE_ON 11 11 STUTTER_ENABLE_NONLPTCH 16 16 STUTTER_IGNORE_CURSOR_NONLPTCH 20 20 STUTTER_IGNORE_ICON_NONLPTCH 21 21 STUTTER_IGNORE_VGA_NONLPTCH 22 22 STUTTER_IGNORE_FBC_NONLPTCH 23 23 STUTTER_URGENT_IN_NOT_SELF_REFRESH_NONLPTCH 26 26 STUTTER_SELF_REFRESH_FORCE_ON_NONLPTCH 27 27 mmDMIF_PG1_DPG_PIPE_STUTTER_CONTROL2 0 0x880 2 0 2 STUTTER_EXIT_SELF_REFRESH_WATERMARK 0 15 STUTTER_ENTER_SELF_REFRESH_WATERMARK 16 31 mmDMIF_PG1_DPG_PIPE_LOW_POWER_CONTROL 0 0x881 7 0 2 PSTATE_CHANGE_ENABLE 0 0 DPM_ENABLE 1 1 PSTATE_CHANGE_URGENT_DURING_REQUEST 4 4 PSTATE_CHANGE_NOT_SELF_REFRESH_DURING_REQUEST 8 8 PSTATE_CHANGE_FORCE_ON 9 9 PSTATE_ALLOW_FOR_URGENT 10 10 PSTATE_CHANGE_WATERMARK 15 31 mmDMIF_PG1_DPG_REPEATER_PROGRAM 0 0x882 2 0 2 REG_DPG_DMIFRC_REPEATER 0 2 REG_DMIFRC_DPG_REPEATER 4 6 mmDMIF_PG1_DPG_CHK_PRE_PROC_CNTL 0 0x886 1 0 2 DPG_DISABLE_DMIF_BUF_CHK 0 0 mmDMIF_PG1_DPG_DVMM_STATUS 0 0x887 4 0 2 DPG_DVMM_FORCED_FLIP_TO_UNMAPPED 0 0 DPG_DVMM_FORCED_FLIP_TO_MAPPED 1 1 DPG_DVMM_FORCED_FLIP_TO_UNMAPPED_CLR 4 4 DPG_DVMM_FORCED_FLIP_TO_MAPPED_CLR 5 5 mmSCL1_SCL_COEF_RAM_SELECT 0 0x89a 3 0 2 SCL_C_RAM_TAP_PAIR_IDX 0 3 SCL_C_RAM_PHASE 8 11 SCL_C_RAM_FILTER_TYPE 16 18 mmSCL1_SCL_COEF_RAM_TAP_DATA 0 0x89b 4 0 2 SCL_C_RAM_EVEN_TAP_COEF 0 13 SCL_C_RAM_EVEN_TAP_COEF_EN 15 15 SCL_C_RAM_ODD_TAP_COEF 16 29 SCL_C_RAM_ODD_TAP_COEF_EN 31 31 mmSCL1_SCL_MODE 0 0x89c 2 0 2 SCL_MODE 0 1 SCL_PSCL_EN 4 4 mmSCL1_SCL_TAP_CONTROL 0 0x89d 2 0 2 SCL_V_NUM_OF_TAPS 0 2 SCL_H_NUM_OF_TAPS 8 11 mmSCL1_SCL_CONTROL 0 0x89e 2 0 2 SCL_BOUNDARY_MODE 0 0 SCL_EARLY_EOL_MODE 4 4 mmSCL1_SCL_BYPASS_CONTROL 0 0x89f 1 0 2 SCL_BYPASS_MODE 0 1 mmSCL1_SCL_MANUAL_REPLICATE_CONTROL 0 0x8a0 2 0 2 SCL_V_MANUAL_REPLICATE_FACTOR 0 3 SCL_H_MANUAL_REPLICATE_FACTOR 8 11 mmSCL1_SCL_AUTOMATIC_MODE_CONTROL 0 0x8a1 2 0 2 SCL_V_CALC_AUTO_RATIO_EN 0 0 SCL_H_CALC_AUTO_RATIO_EN 16 16 mmSCL1_SCL_HORZ_FILTER_CONTROL 0 0x8a2 2 0 2 SCL_H_FILTER_PICK_NEAREST 0 0 SCL_H_2TAP_HARDCODE_COEF_EN 8 8 mmSCL1_SCL_HORZ_FILTER_SCALE_RATIO 0 0x8a3 1 0 2 SCL_H_SCALE_RATIO 0 25 mmSCL1_SCL_HORZ_FILTER_INIT 0 0x8a4 2 0 2 SCL_H_INIT_FRAC 0 23 SCL_H_INIT_INT 24 27 mmSCL1_SCL_VERT_FILTER_CONTROL 0 0x8a5 2 0 2 SCL_V_FILTER_PICK_NEAREST 0 0 SCL_V_2TAP_HARDCODE_COEF_EN 8 8 mmSCL1_SCL_VERT_FILTER_SCALE_RATIO 0 0x8a6 1 0 2 SCL_V_SCALE_RATIO 0 25 mmSCL1_SCL_VERT_FILTER_INIT 0 0x8a7 2 0 2 SCL_V_INIT_FRAC 0 23 SCL_V_INIT_INT 24 26 mmSCL1_SCL_VERT_FILTER_INIT_BOT 0 0x8a8 2 0 2 SCL_V_INIT_FRAC_BOT 0 23 SCL_V_INIT_INT_BOT 24 26 mmSCL1_SCL_ROUND_OFFSET 0 0x8a9 2 0 2 SCL_ROUND_OFFSET_RGB_Y 0 15 SCL_ROUND_OFFSET_CBCR 16 31 mmSCL1_SCL_UPDATE 0 0x8aa 4 0 2 SCL_UPDATE_PENDING 0 0 SCL_UPDATE_TAKEN 8 8 SCL_UPDATE_LOCK 16 16 SCL_COEF_UPDATE_COMPLETE 24 24 mmSCL1_SCL_F_SHARP_CONTROL 0 0x8ab 4 0 2 SCL_HF_SHARP_SCALE_FACTOR 0 2 SCL_HF_SHARP_EN 4 4 SCL_VF_SHARP_SCALE_FACTOR 8 10 SCL_VF_SHARP_EN 12 12 mmSCL1_SCL_ALU_CONTROL 0 0x8ac 1 0 2 SCL_ALU_DISABLE 0 0 mmSCL1_SCL_COEF_RAM_CONFLICT_STATUS 0 0x8ad 4 0 2 SCL_HOST_CONFLICT_FLAG 0 0 SCL_HOST_CONFLICT_ACK 8 8 SCL_HOST_CONFLICT_MASK 12 12 SCL_HOST_CONFLICT_INT_STATUS 16 16 mmSCL1_VIEWPORT_START_SECONDARY 0 0x8ae 2 0 2 VIEWPORT_Y_START_SECONDARY 0 13 VIEWPORT_X_START_SECONDARY 16 29 mmSCL1_VIEWPORT_START 0 0x8af 2 0 2 VIEWPORT_Y_START 0 13 VIEWPORT_X_START 16 29 mmSCL1_VIEWPORT_SIZE 0 0x8b0 2 0 2 VIEWPORT_HEIGHT 0 13 VIEWPORT_WIDTH 16 29 mmSCL1_EXT_OVERSCAN_LEFT_RIGHT 0 0x8b1 2 0 2 EXT_OVERSCAN_RIGHT 0 12 EXT_OVERSCAN_LEFT 16 28 mmSCL1_EXT_OVERSCAN_TOP_BOTTOM 0 0x8b2 2 0 2 EXT_OVERSCAN_BOTTOM 0 12 EXT_OVERSCAN_TOP 16 28 mmSCL1_SCL_MODE_CHANGE_DET1 0 0x8b3 3 0 2 SCL_MODE_CHANGE 0 0 SCL_MODE_CHANGE_ACK 4 4 SCL_ALU_H_SCALE_RATIO 7 27 mmSCL1_SCL_MODE_CHANGE_DET2 0 0x8b4 1 0 2 SCL_ALU_V_SCALE_RATIO 0 20 mmSCL1_SCL_MODE_CHANGE_DET3 0 0x8b5 2 0 2 SCL_ALU_SOURCE_HEIGHT 0 13 SCL_ALU_SOURCE_WIDTH 16 29 mmSCL1_SCL_MODE_CHANGE_MASK 0 0x8b6 1 0 2 SCL_MODE_CHANGE_MASK 0 0 mmBLND1_BLND_CONTROL 0 0x8c7 9 0 2 BLND_GLOBAL_GAIN 0 7 BLND_MODE 8 9 BLND_STEREO_TYPE 10 11 BLND_STEREO_POLARITY 12 12 BLND_FEEDTHROUGH_EN 13 13 BLND_ALPHA_MODE 16 17 BLND_ACTIVE_OVERLAP_ONLY 18 18 BLND_MULTIPLIED_MODE 20 20 BLND_GLOBAL_ALPHA 24 31 mmBLND1_BLND_SM_CONTROL2 0 0x8c8 6 0 2 SM_MODE 0 2 SM_FRAME_ALTERNATE 4 4 SM_FIELD_ALTERNATE 5 5 SM_FORCE_NEXT_FRAME_POL 8 9 SM_FORCE_NEXT_TOP_POL 16 17 SM_CURRENT_FRAME_POL 24 24 mmBLND1_BLND_CONTROL2 0 0x8c9 5 0 2 PTI_ENABLE 0 0 PTI_NEW_PIXEL_GAP 4 5 BLND_NEW_PIXEL_MODE 6 6 BLND_SUPERAA_DEGAMMA_EN 7 7 BLND_SUPERAA_REGAMMA_EN 8 8 mmBLND1_BLND_UPDATE 0 0x8ca 3 0 2 BLND_UPDATE_PENDING 0 0 BLND_UPDATE_TAKEN 8 8 BLND_UPDATE_LOCK 16 16 mmBLND1_BLND_UNDERFLOW_INTERRUPT 0 0x8cb 4 0 2 BLND_UNDERFLOW_INT_OCCURED 0 0 BLND_UNDERFLOW_INT_ACK 8 8 BLND_UNDERFLOW_INT_MASK 12 12 BLND_UNDERFLOW_INT_PIPE_INDEX 16 17 mmBLND1_BLND_V_UPDATE_LOCK 0 0x8cc 6 0 2 BLND_DCP_GRPH_V_UPDATE_LOCK 0 0 BLND_DCP_GRPH_SURF_V_UPDATE_LOCK 1 1 BLND_DCP_CUR_V_UPDATE_LOCK 16 16 BLND_SCL_V_UPDATE_LOCK 28 28 BLND_BLND_V_UPDATE_LOCK 29 29 BLND_V_UPDATE_LOCK_MODE 31 31 mmBLND1_BLND_REG_UPDATE_STATUS 0 0x8cd 10 0 2 DCP_BLNDC_GRPH_UPDATE_PENDING 0 0 DCP_BLNDO_GRPH_UPDATE_PENDING 1 1 DCP_BLNDC_GRPH_SURF_UPDATE_PENDING 2 2 DCP_BLNDO_GRPH_SURF_UPDATE_PENDING 3 3 DCP_BLNDC_CUR_UPDATE_PENDING 6 6 DCP_BLNDO_CUR_UPDATE_PENDING 7 7 SCL_BLNDC_UPDATE_PENDING 8 8 SCL_BLNDO_UPDATE_PENDING 9 9 BLND_BLNDC_UPDATE_PENDING 10 10 BLND_BLNDO_UPDATE_PENDING 11 11 mmCRTC1_CRTC_H_BLANK_EARLY_NUM 0 0x8d2 2 0 2 CRTC_H_BLANK_EARLY_NUM 0 9 CRTC_H_BLANK_EARLY_NUM_DIS 16 16 mmCRTC1_CRTC_H_TOTAL 0 0x8d3 1 0 2 CRTC_H_TOTAL 0 13 mmCRTC1_CRTC_H_BLANK_START_END 0 0x8d4 2 0 2 CRTC_H_BLANK_START 0 13 CRTC_H_BLANK_END 16 29 mmCRTC1_CRTC_H_SYNC_A 0 0x8d5 2 0 2 CRTC_H_SYNC_A_START 0 13 CRTC_H_SYNC_A_END 16 29 mmCRTC1_CRTC_H_SYNC_A_CNTL 0 0x8d6 3 0 2 CRTC_H_SYNC_A_POL 0 0 CRTC_COMP_SYNC_A_EN 16 16 CRTC_H_SYNC_A_CUTOFF 17 17 mmCRTC1_CRTC_H_SYNC_B 0 0x8d7 2 0 2 CRTC_H_SYNC_B_START 0 13 CRTC_H_SYNC_B_END 16 29 mmCRTC1_CRTC_H_SYNC_B_CNTL 0 0x8d8 3 0 2 CRTC_H_SYNC_B_POL 0 0 CRTC_COMP_SYNC_B_EN 16 16 CRTC_H_SYNC_B_CUTOFF 17 17 mmCRTC1_CRTC_VBI_END 0 0x8d9 2 0 2 CRTC_VBI_V_END 0 13 CRTC_VBI_H_END 16 29 mmCRTC1_CRTC_V_TOTAL 0 0x8da 1 0 2 CRTC_V_TOTAL 0 13 mmCRTC1_CRTC_V_TOTAL_MIN 0 0x8db 1 0 2 CRTC_V_TOTAL_MIN 0 13 mmCRTC1_CRTC_V_TOTAL_MAX 0 0x8dc 2 0 2 CRTC_V_TOTAL_MAX 0 13 CRTC_ALLOW_VBLANK_EXTENSION_FOR_MC_TRAINING 16 16 mmCRTC1_CRTC_V_TOTAL_CONTROL 0 0x8dd 6 0 2 CRTC_V_TOTAL_MIN_SEL 0 0 CRTC_V_TOTAL_MAX_SEL 4 4 CRTC_FORCE_LOCK_ON_EVENT 8 8 CRTC_FORCE_LOCK_TO_MASTER_VSYNC 12 12 CRTC_SET_V_TOTAL_MIN_MASK_EN 15 15 CRTC_SET_V_TOTAL_MIN_MASK 16 31 mmCRTC1_CRTC_V_TOTAL_INT_STATUS 0 0x8de 4 0 2 CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED 0 0 CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT 4 4 CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_ACK 8 8 CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_MSK 12 12 mmCRTC1_CRTC_VSYNC_NOM_INT_STATUS 0 0x8df 2 0 2 CRTC_VSYNC_NOM 0 0 CRTC_VSYNC_NOM_INT_CLEAR 4 4 mmCRTC1_CRTC_V_BLANK_START_END 0 0x8e0 2 0 2 CRTC_V_BLANK_START 0 13 CRTC_V_BLANK_END 16 29 mmCRTC1_CRTC_V_SYNC_A 0 0x8e1 2 0 2 CRTC_V_SYNC_A_START 0 13 CRTC_V_SYNC_A_END 16 29 mmCRTC1_CRTC_V_SYNC_A_CNTL 0 0x8e2 1 0 2 CRTC_V_SYNC_A_POL 0 0 mmCRTC1_CRTC_V_SYNC_B 0 0x8e3 2 0 2 CRTC_V_SYNC_B_START 0 13 CRTC_V_SYNC_B_END 16 29 mmCRTC1_CRTC_V_SYNC_B_CNTL 0 0x8e4 1 0 2 CRTC_V_SYNC_B_POL 0 0 mmCRTC1_CRTC_DTMTEST_CNTL 0 0x8e5 2 0 2 CRTC_DTMTEST_CRTC_EN 0 0 CRTC_DTMTEST_CLK_DIV 1 4 mmCRTC1_CRTC_DTMTEST_STATUS_POSITION 0 0x8e6 2 0 2 CRTC_DTMTEST_VERT_COUNT 0 13 CRTC_DTMTEST_HORZ_COUNT 16 29 mmCRTC1_CRTC_TRIGA_CNTL 0 0x8e7 11 0 2 CRTC_TRIGA_SOURCE_SELECT 0 4 CRTC_TRIGA_POLARITY_SELECT 5 7 CRTC_TRIGA_RESYNC_BYPASS_EN 8 8 CRTC_TRIGA_INPUT_STATUS 9 9 CRTC_TRIGA_POLARITY_STATUS 10 10 CRTC_TRIGA_OCCURRED 11 11 CRTC_TRIGA_RISING_EDGE_DETECT_CNTL 12 13 CRTC_TRIGA_FALLING_EDGE_DETECT_CNTL 16 17 CRTC_TRIGA_FREQUENCY_SELECT 20 21 CRTC_TRIGA_DELAY 24 28 CRTC_TRIGA_CLEAR 31 31 mmCRTC1_CRTC_TRIGA_MANUAL_TRIG 0 0x8e8 1 0 2 CRTC_TRIGA_MANUAL_TRIG 0 0 mmCRTC1_CRTC_TRIGB_CNTL 0 0x8e9 11 0 2 CRTC_TRIGB_SOURCE_SELECT 0 4 CRTC_TRIGB_POLARITY_SELECT 5 7 CRTC_TRIGB_RESYNC_BYPASS_EN 8 8 CRTC_TRIGB_INPUT_STATUS 9 9 CRTC_TRIGB_POLARITY_STATUS 10 10 CRTC_TRIGB_OCCURRED 11 11 CRTC_TRIGB_RISING_EDGE_DETECT_CNTL 12 13 CRTC_TRIGB_FALLING_EDGE_DETECT_CNTL 16 17 CRTC_TRIGB_FREQUENCY_SELECT 20 21 CRTC_TRIGB_DELAY 24 28 CRTC_TRIGB_CLEAR 31 31 mmCRTC1_CRTC_TRIGB_MANUAL_TRIG 0 0x8ea 1 0 2 CRTC_TRIGB_MANUAL_TRIG 0 0 mmCRTC1_CRTC_FORCE_COUNT_NOW_CNTL 0 0x8eb 5 0 2 CRTC_FORCE_COUNT_NOW_MODE 0 1 CRTC_FORCE_COUNT_NOW_CHECK 4 4 CRTC_FORCE_COUNT_NOW_TRIG_SEL 8 8 CRTC_FORCE_COUNT_NOW_OCCURRED 16 16 CRTC_FORCE_COUNT_NOW_CLEAR 24 24 mmCRTC1_CRTC_FLOW_CONTROL 0 0x8ec 4 0 2 CRTC_FLOW_CONTROL_SOURCE_SELECT 0 4 CRTC_FLOW_CONTROL_POLARITY 8 8 CRTC_FLOW_CONTROL_GRANULARITY 16 16 CRTC_FLOW_CONTROL_INPUT_STATUS 24 24 mmCRTC1_CRTC_STEREO_FORCE_NEXT_EYE 0 0x8ed 3 0 2 CRTC_STEREO_FORCE_NEXT_EYE 0 1 CRTC_AVSYNC_FRAME_COUNTER 8 15 CRTC_AVSYNC_LINE_COUNTER 16 28 mmCRTC1_CRTC_AVSYNC_COUNTER 0 0x8ee 1 0 2 CRTC_AVSYNC_COUNTER 0 31 mmCRTC1_CRTC_CONTROL 0 0x8ef 11 0 2 CRTC_MASTER_EN 0 0 CRTC_SYNC_RESET_SEL 4 4 CRTC_DISABLE_POINT_CNTL 8 9 CRTC_START_POINT_CNTL 12 12 CRTC_FIELD_NUMBER_CNTL 13 13 CRTC_FIELD_NUMBER_POLARITY 14 14 CRTC_CURRENT_MASTER_EN_STATE 16 16 CRTC_HBLANK_EARLY_CONTROL 20 22 CRTC_SOF_PULL_EN 29 29 CRTC_AVSYNC_LOCK_SNAPSHOT 30 30 CRTC_AVSYNC_VSYNC_N_HSYNC_MODE 31 31 mmCRTC1_CRTC_BLANK_CONTROL 0 0x8f0 3 0 2 CRTC_CURRENT_BLANK_STATE 0 0 CRTC_BLANK_DATA_EN 8 8 CRTC_BLANK_DE_MODE 16 16 mmCRTC1_CRTC_INTERLACE_CONTROL 0 0x8f1 2 0 2 CRTC_INTERLACE_ENABLE 0 0 CRTC_INTERLACE_FORCE_NEXT_FIELD 16 17 mmCRTC1_CRTC_INTERLACE_STATUS 0 0x8f2 2 0 2 CRTC_INTERLACE_CURRENT_FIELD 0 0 CRTC_INTERLACE_NEXT_FIELD 1 1 mmCRTC1_CRTC_FIELD_INDICATION_CONTROL 0 0x8f3 2 0 2 CRTC_FIELD_INDICATION_OUTPUT_POLARITY 0 0 CRTC_FIELD_ALIGNMENT 1 1 mmCRTC1_CRTC_PIXEL_DATA_READBACK0 0 0x8f4 2 0 2 CRTC_PIXEL_DATA_BLUE_CB 0 11 CRTC_PIXEL_DATA_GREEN_Y 16 27 mmCRTC1_CRTC_PIXEL_DATA_READBACK1 0 0x8f5 1 0 2 CRTC_PIXEL_DATA_RED_CR 0 11 mmCRTC1_CRTC_STATUS 0 0x8f6 9 0 2 CRTC_V_BLANK 0 0 CRTC_V_ACTIVE_DISP 1 1 CRTC_V_SYNC_A 2 2 CRTC_V_UPDATE 3 3 CRTC_V_START_LINE 4 4 CRTC_V_BLANK_3D_STRUCTURE 5 5 CRTC_H_BLANK 16 16 CRTC_H_ACTIVE_DISP 17 17 CRTC_H_SYNC_A 18 18 mmCRTC1_CRTC_STATUS_POSITION 0 0x8f7 2 0 2 CRTC_VERT_COUNT 0 13 CRTC_HORZ_COUNT 16 29 mmCRTC1_CRTC_NOM_VERT_POSITION 0 0x8f8 1 0 2 CRTC_VERT_COUNT_NOM 0 13 mmCRTC1_CRTC_STATUS_FRAME_COUNT 0 0x8f9 1 0 2 CRTC_FRAME_COUNT 0 23 mmCRTC1_CRTC_STATUS_VF_COUNT 0 0x8fa 1 0 2 CRTC_VF_COUNT 0 29 mmCRTC1_CRTC_STATUS_HV_COUNT 0 0x8fb 1 0 2 CRTC_HV_COUNT 0 29 mmCRTC1_CRTC_COUNT_CONTROL 0 0x8fc 2 0 2 CRTC_HORZ_COUNT_BY2_EN 0 0 CRTC_HORZ_REPETITION_COUNT 1 4 mmCRTC1_CRTC_COUNT_RESET 0 0x8fd 1 0 2 CRTC_RESET_FRAME_COUNT 0 0 mmCRTC1_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE 0 0x8fe 1 0 2 CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE 0 0 mmCRTC1_CRTC_VERT_SYNC_CONTROL 0 0x8ff 3 0 2 CRTC_FORCE_VSYNC_NEXT_LINE_OCCURRED 0 0 CRTC_FORCE_VSYNC_NEXT_LINE_CLEAR 8 8 CRTC_AUTO_FORCE_VSYNC_MODE 16 17 mmCRTC1_CRTC_STEREO_STATUS 0 0x900 5 0 2 CRTC_STEREO_CURRENT_EYE 0 0 CRTC_STEREO_SYNC_OUTPUT 8 8 CRTC_STEREO_SYNC_SELECT 16 16 CRTC_STEREO_EYE_FLAG 20 20 CRTC_STEREO_FORCE_NEXT_EYE_PENDING 24 25 mmCRTC1_CRTC_STEREO_CONTROL 0 0x901 8 0 2 CRTC_STEREO_SYNC_OUTPUT_LINE_NUM 0 13 CRTC_STEREO_SYNC_OUTPUT_POLARITY 15 15 CRTC_STEREO_SYNC_SELECT_POLARITY 16 16 CRTC_STEREO_EYE_FLAG_POLARITY 17 17 CRTC_DISABLE_STEREOSYNC_OUTPUT_FOR_DP 18 18 CRTC_DISABLE_FIELD_NUM 19 19 CRTC_DISABLE_V_BLANK_FOR_DP_FIX 20 20 CRTC_STEREO_EN 24 24 mmCRTC1_CRTC_SNAPSHOT_STATUS 0 0x902 3 0 2 CRTC_SNAPSHOT_OCCURRED 0 0 CRTC_SNAPSHOT_CLEAR 1 1 CRTC_SNAPSHOT_MANUAL_TRIGGER 2 2 mmCRTC1_CRTC_SNAPSHOT_CONTROL 0 0x903 1 0 2 CRTC_AUTO_SNAPSHOT_TRIG_SEL 0 1 mmCRTC1_CRTC_SNAPSHOT_POSITION 0 0x904 2 0 2 CRTC_SNAPSHOT_VERT_COUNT 0 13 CRTC_SNAPSHOT_HORZ_COUNT 16 29 mmCRTC1_CRTC_SNAPSHOT_FRAME 0 0x905 1 0 2 CRTC_SNAPSHOT_FRAME_COUNT 0 23 mmCRTC1_CRTC_START_LINE_CONTROL 0 0x906 5 0 2 CRTC_PROGRESSIVE_START_LINE_EARLY 0 0 CRTC_INTERLACE_START_LINE_EARLY 1 1 CRTC_PREFETCH_EN 2 2 CRTC_LEGACY_REQUESTOR_EN 8 8 CRTC_ADVANCED_START_LINE_POSITION 12 19 mmCRTC1_CRTC_INTERRUPT_CONTROL 0 0x907 16 0 2 CRTC_SNAPSHOT_INT_MSK 0 0 CRTC_SNAPSHOT_INT_TYPE 1 1 CRTC_V_UPDATE_INT_MSK 4 4 CRTC_V_UPDATE_INT_TYPE 5 5 CRTC_FORCE_COUNT_NOW_INT_MSK 8 8 CRTC_FORCE_COUNT_NOW_INT_TYPE 9 9 CRTC_FORCE_VSYNC_NEXT_LINE_INT_MSK 16 16 CRTC_FORCE_VSYNC_NEXT_LINE_INT_TYPE 17 17 CRTC_TRIGA_INT_MSK 24 24 CRTC_TRIGB_INT_MSK 25 25 CRTC_TRIGA_INT_TYPE 26 26 CRTC_TRIGB_INT_TYPE 27 27 CRTC_VSYNC_NOM_INT_MSK 28 28 CRTC_VSYNC_NOM_INT_TYPE 29 29 CRTC_GSL_VSYNC_GAP_INT_MSK 30 30 CRTC_GSL_VSYNC_GAP_INT_TYPE 31 31 mmCRTC1_CRTC_UPDATE_LOCK 0 0x908 1 0 2 CRTC_UPDATE_LOCK 0 0 mmCRTC1_CRTC_DOUBLE_BUFFER_CONTROL 0 0x909 5 0 2 CRTC_UPDATE_PENDING 0 0 CRTC_UPDATE_INSTANTLY 8 8 CRTC_BLANK_DATA_DOUBLE_BUFFER_EN 16 16 CRTC_RANGE_TIMING_DBUF_UPDATE_MODE 24 24 CRTC_RANGE_TIMING_DBUF_UPDATE_PENDING 25 25 mmCRTC1_CRTC_VGA_PARAMETER_CAPTURE_MODE 0 0x90a 1 0 2 CRTC_VGA_PARAMETER_CAPTURE_MODE 0 0 mmCRTC1_CRTC_TEST_PATTERN_CONTROL 0 0x90b 4 0 2 CRTC_TEST_PATTERN_EN 0 0 CRTC_TEST_PATTERN_MODE 8 10 CRTC_TEST_PATTERN_DYNAMIC_RANGE 16 16 CRTC_TEST_PATTERN_COLOR_FORMAT 24 31 mmCRTC1_CRTC_TEST_PATTERN_PARAMETERS 0 0x90c 5 0 2 CRTC_TEST_PATTERN_INC0 0 3 CRTC_TEST_PATTERN_INC1 4 7 CRTC_TEST_PATTERN_VRES 8 11 CRTC_TEST_PATTERN_HRES 12 15 CRTC_TEST_PATTERN_RAMP0_OFFSET 16 31 mmCRTC1_CRTC_TEST_PATTERN_COLOR 0 0x90d 2 0 2 CRTC_TEST_PATTERN_DATA 0 15 CRTC_TEST_PATTERN_MASK 16 21 mmCRTC1_CRTC_MASTER_UPDATE_LOCK 0 0x90e 3 0 2 MASTER_UPDATE_LOCK 0 0 GSL_CONTROL_MASTER_UPDATE_LOCK 8 8 UNDERFLOW_UPDATE_LOCK 16 16 mmCRTC1_CRTC_MASTER_UPDATE_MODE 0 0x90f 2 0 2 MASTER_UPDATE_MODE 0 2 MASTER_UPDATE_INTERLACED_MODE 16 17 mmCRTC1_CRTC_MVP_INBAND_CNTL_INSERT 0 0x910 2 0 2 CRTC_MVP_INBAND_OUT_MODE 0 1 CRTC_MVP_INBAND_CNTL_CHAR_INSERT 8 31 mmCRTC1_CRTC_MVP_INBAND_CNTL_INSERT_TIMER 0 0x911 1 0 2 CRTC_MVP_INBAND_CNTL_CHAR_INSERT_TIMER 0 7 mmCRTC1_CRTC_MVP_STATUS 0 0x912 4 0 2 CRTC_FLIP_NOW_OCCURRED 0 0 CRTC_AFR_HSYNC_SWITCH_DONE_OCCURRED 4 4 CRTC_FLIP_NOW_CLEAR 16 16 CRTC_AFR_HSYNC_SWITCH_DONE_CLEAR 20 20 mmCRTC1_CRTC_MASTER_EN 0 0x913 1 0 2 CRTC_MASTER_EN 0 0 mmCRTC1_CRTC_ALLOW_STOP_OFF_V_CNT 0 0x914 2 0 2 CRTC_ALLOW_STOP_OFF_V_CNT 0 7 CRTC_DISABLE_ALLOW_STOP_OFF_V_CNT 16 16 mmCRTC1_CRTC_V_UPDATE_INT_STATUS 0 0x915 2 0 2 CRTC_V_UPDATE_INT_OCCURRED 0 0 CRTC_V_UPDATE_INT_CLEAR 8 8 mmCRTC1_CRTC_OVERSCAN_COLOR 0 0x917 3 0 2 CRTC_OVERSCAN_COLOR_BLUE 0 9 CRTC_OVERSCAN_COLOR_GREEN 10 19 CRTC_OVERSCAN_COLOR_RED 20 29 mmCRTC1_CRTC_OVERSCAN_COLOR_EXT 0 0x918 3 0 2 CRTC_OVERSCAN_COLOR_BLUE_EXT 0 1 CRTC_OVERSCAN_COLOR_GREEN_EXT 8 9 CRTC_OVERSCAN_COLOR_RED_EXT 16 17 mmCRTC1_CRTC_BLANK_DATA_COLOR 0 0x919 3 0 2 CRTC_BLANK_DATA_COLOR_BLUE_CB 0 9 CRTC_BLANK_DATA_COLOR_GREEN_Y 10 19 CRTC_BLANK_DATA_COLOR_RED_CR 20 29 mmCRTC1_CRTC_BLANK_DATA_COLOR_EXT 0 0x91a 3 0 2 CRTC_BLANK_DATA_COLOR_BLUE_CB_EXT 0 1 CRTC_BLANK_DATA_COLOR_GREEN_Y_EXT 8 9 CRTC_BLANK_DATA_COLOR_RED_CR_EXT 16 17 mmCRTC1_CRTC_BLACK_COLOR 0 0x91b 3 0 2 CRTC_BLACK_COLOR_B_CB 0 9 CRTC_BLACK_COLOR_G_Y 10 19 CRTC_BLACK_COLOR_R_CR 20 29 mmCRTC1_CRTC_BLACK_COLOR_EXT 0 0x91c 3 0 2 CRTC_BLACK_COLOR_B_CB_EXT 0 1 CRTC_BLACK_COLOR_G_Y_EXT 8 9 CRTC_BLACK_COLOR_R_CR_EXT 16 17 mmCRTC1_CRTC_VERTICAL_INTERRUPT0_POSITION 0 0x91d 2 0 2 CRTC_VERTICAL_INTERRUPT0_LINE_START 0 13 CRTC_VERTICAL_INTERRUPT0_LINE_END 16 29 mmCRTC1_CRTC_VERTICAL_INTERRUPT0_CONTROL 0 0x91e 6 0 2 CRTC_VERTICAL_INTERRUPT0_OUTPUT_POLARITY 4 4 CRTC_VERTICAL_INTERRUPT0_INT_ENABLE 8 8 CRTC_VERTICAL_INTERRUPT0_STATUS 12 12 CRTC_VERTICAL_INTERRUPT0_INT_STATUS 16 16 CRTC_VERTICAL_INTERRUPT0_CLEAR 20 20 CRTC_VERTICAL_INTERRUPT0_INT_TYPE 24 24 mmCRTC1_CRTC_VERTICAL_INTERRUPT1_POSITION 0 0x91f 1 0 2 CRTC_VERTICAL_INTERRUPT1_LINE_START 0 13 mmCRTC1_CRTC_VERTICAL_INTERRUPT1_CONTROL 0 0x920 5 0 2 CRTC_VERTICAL_INTERRUPT1_INT_ENABLE 8 8 CRTC_VERTICAL_INTERRUPT1_STATUS 12 12 CRTC_VERTICAL_INTERRUPT1_INT_STATUS 16 16 CRTC_VERTICAL_INTERRUPT1_CLEAR 20 20 CRTC_VERTICAL_INTERRUPT1_INT_TYPE 24 24 mmCRTC1_CRTC_VERTICAL_INTERRUPT2_POSITION 0 0x921 1 0 2 CRTC_VERTICAL_INTERRUPT2_LINE_START 0 13 mmCRTC1_CRTC_VERTICAL_INTERRUPT2_CONTROL 0 0x922 5 0 2 CRTC_VERTICAL_INTERRUPT2_INT_ENABLE 8 8 CRTC_VERTICAL_INTERRUPT2_STATUS 12 12 CRTC_VERTICAL_INTERRUPT2_INT_STATUS 16 16 CRTC_VERTICAL_INTERRUPT2_CLEAR 20 20 CRTC_VERTICAL_INTERRUPT2_INT_TYPE 24 24 mmCRTC1_CRTC_CRC_CNTL 0 0x923 7 0 2 CRTC_CRC_EN 0 0 CRTC_CRC_CONT_EN 4 4 CRTC_CRC_STEREO_MODE 8 9 CRTC_CRC_INTERLACE_MODE 12 13 CRTC_CRC_USE_NEW_AND_REPEATED_PIXELS 16 16 CRTC_CRC0_SELECT 20 22 CRTC_CRC1_SELECT 24 26 mmCRTC1_CRTC_CRC0_WINDOWA_X_CONTROL 0 0x924 2 0 2 CRTC_CRC0_WINDOWA_X_START 0 13 CRTC_CRC0_WINDOWA_X_END 16 29 mmCRTC1_CRTC_CRC0_WINDOWA_Y_CONTROL 0 0x925 2 0 2 CRTC_CRC0_WINDOWA_Y_START 0 13 CRTC_CRC0_WINDOWA_Y_END 16 29 mmCRTC1_CRTC_CRC0_WINDOWB_X_CONTROL 0 0x926 2 0 2 CRTC_CRC0_WINDOWB_X_START 0 13 CRTC_CRC0_WINDOWB_X_END 16 29 mmCRTC1_CRTC_CRC0_WINDOWB_Y_CONTROL 0 0x927 2 0 2 CRTC_CRC0_WINDOWB_Y_START 0 13 CRTC_CRC0_WINDOWB_Y_END 16 29 mmCRTC1_CRTC_CRC0_DATA_RG 0 0x928 2 0 2 CRC0_R_CR 0 15 CRC0_G_Y 16 31 mmCRTC1_CRTC_CRC0_DATA_B 0 0x929 1 0 2 CRC0_B_CB 0 15 mmCRTC1_CRTC_CRC1_WINDOWA_X_CONTROL 0 0x92a 2 0 2 CRTC_CRC1_WINDOWA_X_START 0 13 CRTC_CRC1_WINDOWA_X_END 16 29 mmCRTC1_CRTC_CRC1_WINDOWA_Y_CONTROL 0 0x92b 2 0 2 CRTC_CRC1_WINDOWA_Y_START 0 13 CRTC_CRC1_WINDOWA_Y_END 16 29 mmCRTC1_CRTC_CRC1_WINDOWB_X_CONTROL 0 0x92c 2 0 2 CRTC_CRC1_WINDOWB_X_START 0 13 CRTC_CRC1_WINDOWB_X_END 16 29 mmCRTC1_CRTC_CRC1_WINDOWB_Y_CONTROL 0 0x92d 2 0 2 CRTC_CRC1_WINDOWB_Y_START 0 13 CRTC_CRC1_WINDOWB_Y_END 16 29 mmCRTC1_CRTC_CRC1_DATA_RG 0 0x92e 2 0 2 CRC1_R_CR 0 15 CRC1_G_Y 16 31 mmCRTC1_CRTC_CRC1_DATA_B 0 0x92f 1 0 2 CRC1_B_CB 0 15 mmCRTC1_CRTC_EXT_TIMING_SYNC_CONTROL 0 0x930 11 0 2 CRTC_EXT_TIMING_SYNC_ENABLE 0 1 CRTC_EXT_TIMING_SYNC_HCOUNT_MODE_ENABLE 3 3 CRTC_EXT_TIMING_SYNC_JITTER_FILTERING_ENABLE 4 4 CRTC_EXT_TIMING_SYNC_JITTER_FILTERING_WINDOW 5 6 CRTC_EXT_TIMING_SYNC_WINDOW_ENABLE 8 8 CRTC_EXT_TIMING_SYNC_WINDOW_UPDATE 9 9 CRTC_EXT_TIMING_SYNC_VSYNC_POLARITY 12 12 CRTC_EXT_TIMING_SYNC_HSYNC_POLARITY 13 13 CRTC_EXT_TIMING_SYNC_INTERLACE_MODE 14 14 CRTC_EXT_TIMING_SYNC_MASTER_FRAME_RATE 24 26 CRTC_EXT_TIMING_SYNC_SLAVE_FRAME_RATE 28 30 mmCRTC1_CRTC_EXT_TIMING_SYNC_WINDOW_START 0 0x931 2 0 2 CRTC_EXT_TIMING_SYNC_WINDOW_START_X 0 13 CRTC_EXT_TIMING_SYNC_WINDOW_START_Y 16 29 mmCRTC1_CRTC_EXT_TIMING_SYNC_WINDOW_END 0 0x932 2 0 2 CRTC_EXT_TIMING_SYNC_WINDOW_END_X 0 13 CRTC_EXT_TIMING_SYNC_WINDOW_END_Y 16 29 mmCRTC1_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL 0 0x933 6 0 2 CRTC_EXT_TIMING_SYNC_LOSS_INT_ENABLE 0 0 CRTC_EXT_TIMING_SYNC_LOSS_STATUS 4 4 CRTC_EXT_TIMING_SYNC_LOSS_INT_STATUS 8 8 CRTC_EXT_TIMING_SYNC_LOSS_CLEAR 16 16 CRTC_EXT_TIMING_SYNC_LOSS_INT_TYPE 20 20 CRTC_EXT_TIMING_SYNC_LOSS_FRAME_COUNT 29 31 mmCRTC1_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL 0 0x934 5 0 2 CRTC_EXT_TIMING_SYNC_INT_ENABLE 0 0 CRTC_EXT_TIMING_SYNC_STATUS 4 4 CRTC_EXT_TIMING_SYNC_INT_STATUS 8 8 CRTC_EXT_TIMING_SYNC_CLEAR 16 16 CRTC_EXT_TIMING_SYNC_INT_TYPE 20 20 mmCRTC1_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL 0 0x935 5 0 2 CRTC_EXT_TIMING_SYNC_SIGNAL_INT_ENABLE 0 0 CRTC_EXT_TIMING_SYNC_SIGNAL_STATUS 4 4 CRTC_EXT_TIMING_SYNC_SIGNAL_INT_STATUS 8 8 CRTC_EXT_TIMING_SYNC_SIGNAL_CLEAR 16 16 CRTC_EXT_TIMING_SYNC_SIGNAL_INT_TYPE 20 20 mmCRTC1_CRTC_STATIC_SCREEN_CONTROL 0 0x936 9 0 2 CRTC_STATIC_SCREEN_EVENT_MASK 0 15 CRTC_STATIC_SCREEN_FRAME_COUNT 16 23 CRTC_CPU_SS_INT_ENABLE 24 24 CRTC_SS_STATUS 25 25 CRTC_CPU_SS_INT_STATUS 26 26 CRTC_CPU_SS_INT_CLEAR 27 27 CRTC_CPU_SS_INT_TYPE 28 28 CRTC_STATIC_SCREEN_OVERRIDE 30 30 CRTC_STATIC_SCREEN_OVERRIDE_VALUE 31 31 mmCRTC1_CRTC_3D_STRUCTURE_CONTROL 0 0x937 7 0 2 CRTC_3D_STRUCTURE_EN 0 0 CRTC_3D_STRUCTURE_EN_DB 4 4 CRTC_3D_STRUCTURE_V_UPDATE_MODE 8 9 CRTC_3D_STRUCTURE_STEREO_SEL_OVR 12 12 CRTC_3D_STRUCTURE_F_COUNT_RESET 16 16 CRTC_3D_STRUCTURE_F_COUNT_RESET_PENDING 17 17 CRTC_3D_STRUCTURE_F_COUNT 18 19 mmCRTC1_CRTC_GSL_VSYNC_GAP 0 0x938 8 0 2 CRTC_GSL_VSYNC_GAP_LIMIT 0 7 CRTC_GSL_VSYNC_GAP_DELAY 8 15 CRTC_GSL_VSYNC_GAP_SOURCE_SEL 16 16 CRTC_GSL_VSYNC_GAP_MODE 17 18 CRTC_GSL_VSYNC_GAP_CLEAR 19 19 CRTC_GSL_VSYNC_GAP_OCCURRED 20 20 CRTC_GSL_VSYNC_GAP_MASTER_FASTER 23 23 CRTC_GSL_VSYNC_GAP 24 31 mmCRTC1_CRTC_GSL_WINDOW 0 0x939 2 0 2 CRTC_GSL_WINDOW_START 0 13 CRTC_GSL_WINDOW_END 16 29 mmCRTC1_CRTC_GSL_CONTROL 0 0x93a 3 0 2 CRTC_GSL_CHECK_LINE_NUM 0 13 CRTC_GSL_FORCE_DELAY 16 20 CRTC_GSL_CHECK_ALL_FIELDS 28 28 mmCRTC1_CRTC_RANGE_TIMING_INT_STATUS 0 0x93d 5 0 2 CRTC_RANGE_TIMING_UPDATE_OCCURRED 0 0 CRTC_RANGE_TIMING_UPDATE_OCCURRED_INT 4 4 CRTC_RANGE_TIMING_UPDATE_OCCURRED_CLEAR 8 8 CRTC_RANGE_TIMING_UPDATE_OCCURRED_INT_MSK 12 12 CRTC_RANGE_TIMING_UPDATE_OCCURRED_INT_TYPE 16 16 mmCRTC1_CRTC_DRR_CONTROL 0 0x93e 4 0 2 CRTC_XDMA_PREFETCH_DELAY 0 13 CRTC_V_TOTAL_LAST_USED_BY_DRR 14 27 CRTC_SET_V_TOTAL_MIN_AUTO_DIS 28 28 CRTC_DRR_MODE_DBUF_UPDATE_MODE 29 30 mmFMT1_FMT_CLAMP_COMPONENT_R 0 0x942 2 0 2 FMT_CLAMP_LOWER_R 0 15 FMT_CLAMP_UPPER_R 16 31 mmFMT1_FMT_CLAMP_COMPONENT_G 0 0x943 2 0 2 FMT_CLAMP_LOWER_G 0 15 FMT_CLAMP_UPPER_G 16 31 mmFMT1_FMT_CLAMP_COMPONENT_B 0 0x944 2 0 2 FMT_CLAMP_LOWER_B 0 15 FMT_CLAMP_UPPER_B 16 31 mmFMT1_FMT_DYNAMIC_EXP_CNTL 0 0x945 2 0 2 FMT_DYNAMIC_EXP_EN 0 0 FMT_DYNAMIC_EXP_MODE 4 4 mmFMT1_FMT_CONTROL 0 0x946 11 0 2 FMT_STEREOSYNC_OVERRIDE 0 0 FMT_STEREOSYNC_OVR_POL 4 4 FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX 8 11 FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP 12 13 FMT_PIXEL_ENCODING 16 17 FMT_SUBSAMPLING_MODE 18 19 FMT_SUBSAMPLING_ORDER 20 20 FMT_CBCR_BIT_REDUCTION_BYPASS 21 21 FMT_SRC_SELECT 24 26 FMT_420_PIXEL_PHASE_LOCKED 30 30 FMT_420_PIXEL_PHASE_LOCKED_CLEAR 31 31 mmFMT1_FMT_BIT_DEPTH_CONTROL 0 0x947 17 0 2 FMT_TRUNCATE_EN 0 0 FMT_TRUNCATE_MODE 1 1 FMT_TRUNCATE_DEPTH 4 5 FMT_SPATIAL_DITHER_EN 8 8 FMT_SPATIAL_DITHER_MODE 9 10 FMT_SPATIAL_DITHER_DEPTH 11 12 FMT_FRAME_RANDOM_ENABLE 13 13 FMT_RGB_RANDOM_ENABLE 14 14 FMT_HIGHPASS_RANDOM_ENABLE 15 15 FMT_TEMPORAL_DITHER_EN 16 16 FMT_TEMPORAL_DITHER_DEPTH 17 18 FMT_TEMPORAL_DITHER_OFFSET 21 22 FMT_TEMPORAL_LEVEL 24 24 FMT_TEMPORAL_DITHER_RESET 25 25 FMT_25FRC_SEL 26 27 FMT_50FRC_SEL 28 29 FMT_75FRC_SEL 30 31 mmFMT1_FMT_DITHER_RAND_R_SEED 0 0x948 2 0 2 FMT_RAND_R_SEED 0 7 FMT_OFFSET_R_CR 16 31 mmFMT1_FMT_DITHER_RAND_G_SEED 0 0x949 2 0 2 FMT_RAND_G_SEED 0 7 FMT_OFFSET_G_Y 16 31 mmFMT1_FMT_DITHER_RAND_B_SEED 0 0x94a 2 0 2 FMT_RAND_B_SEED 0 7 FMT_OFFSET_B_CB 16 31 mmFMT1_FMT_CLAMP_CNTL 0 0x94e 2 0 2 FMT_CLAMP_DATA_EN 0 0 FMT_CLAMP_COLOR_FORMAT 16 18 mmFMT1_FMT_CRC_CNTL 0 0x94f 11 0 2 FMT_CRC_EN 0 0 FMT_DTMTEST_CRC_EN 1 1 FMT_CRC_CONT_EN 4 4 FMT_ONE_SHOT_CRC_PENDING 5 5 FMT_CRC_INCLUDE_OVERSCAN 6 6 FMT_CRC_ONLY_BLANKB 8 8 FMT_CRC_PSR_MODE_ENABLE 9 9 FMT_CRC_INTERLACE_MODE 12 13 FMT_CRC_USE_NEW_AND_REPEATED_PIXELS 16 16 FMT_CRC_EVEN_ODD_PIX_ENABLE 20 20 FMT_CRC_EVEN_ODD_PIX_SELECT 24 24 mmFMT1_FMT_CRC_SIG_RED_GREEN_MASK 0 0x950 2 0 2 FMT_CRC_SIG_RED_MASK 0 15 FMT_CRC_SIG_GREEN_MASK 16 31 mmFMT1_FMT_CRC_SIG_BLUE_CONTROL_MASK 0 0x951 2 0 2 FMT_CRC_SIG_BLUE_MASK 0 15 FMT_CRC_SIG_CONTROL_MASK 16 31 mmFMT1_FMT_CRC_SIG_RED_GREEN 0 0x952 2 0 2 FMT_CRC_SIG_RED 0 15 FMT_CRC_SIG_GREEN 16 31 mmFMT1_FMT_CRC_SIG_BLUE_CONTROL 0 0x953 2 0 2 FMT_CRC_SIG_BLUE 0 15 FMT_CRC_SIG_CONTROL 16 31 mmFMT1_FMT_SIDE_BY_SIDE_STEREO_CONTROL 0 0x954 1 0 2 FMT_SIDE_BY_SIDE_STEREO_ACTIVE_WIDTH 0 12 mmFMT1_FMT_420_HBLANK_EARLY_START 0 0x955 1 0 2 FMT_420_HBLANK_EARLY_START 0 11 mmDCP2_GRPH_ENABLE 0 0x95a 2 0 2 GRPH_ENABLE 0 0 GRPH_KEYER_ALPHA_SEL 1 1 mmDCP2_GRPH_CONTROL 0 0x95b 12 0 2 GRPH_DEPTH 0 1 GRPH_SE_ENABLE 2 2 GRPH_Z 4 5 GRPH_DIM_TYPE 6 7 GRPH_FORMAT 8 10 GRPH_NUM_BANKS 12 14 GRPH_ADDRESS_TRANSLATION_ENABLE 16 16 GRPH_PRIVILEGED_ACCESS_ENABLE 17 17 GRPH_NUM_SHADER_ENGINES 18 19 GRPH_SW_MODE 20 24 GRPH_NUM_PIPES 28 30 GRPH_COLOR_EXPANSION_MODE 31 31 mmDCP2_GRPH_LUT_10BIT_BYPASS 0 0x95c 2 0 2 GRPH_LUT_10BIT_BYPASS_EN 8 8 GRPH_LUT_10BIT_BYPASS_DBL_BUF_EN 16 16 mmDCP2_GRPH_SWAP_CNTL 0 0x95d 5 0 2 GRPH_ENDIAN_SWAP 0 1 GRPH_RED_CROSSBAR 4 5 GRPH_GREEN_CROSSBAR 6 7 GRPH_BLUE_CROSSBAR 8 9 GRPH_ALPHA_CROSSBAR 10 11 mmDCP2_GRPH_PRIMARY_SURFACE_ADDRESS 0 0x95e 2 0 2 GRPH_PRIMARY_DFQ_ENABLE 0 0 GRPH_PRIMARY_SURFACE_ADDRESS 8 31 mmDCP2_GRPH_SECONDARY_SURFACE_ADDRESS 0 0x95f 2 0 2 GRPH_SECONDARY_DFQ_ENABLE 0 0 GRPH_SECONDARY_SURFACE_ADDRESS 8 31 mmDCP2_GRPH_PITCH 0 0x960 1 0 2 GRPH_PITCH 0 14 mmDCP2_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH 0 0x961 1 0 2 GRPH_PRIMARY_SURFACE_ADDRESS_HIGH 0 7 mmDCP2_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH 0 0x962 1 0 2 GRPH_SECONDARY_SURFACE_ADDRESS_HIGH 0 7 mmDCP2_GRPH_SURFACE_OFFSET_X 0 0x963 1 0 2 GRPH_SURFACE_OFFSET_X 0 13 mmDCP2_GRPH_SURFACE_OFFSET_Y 0 0x964 1 0 2 GRPH_SURFACE_OFFSET_Y 0 13 mmDCP2_GRPH_X_START 0 0x965 1 0 2 GRPH_X_START 0 13 mmDCP2_GRPH_Y_START 0 0x966 1 0 2 GRPH_Y_START 0 13 mmDCP2_GRPH_X_END 0 0x967 1 0 2 GRPH_X_END 0 14 mmDCP2_GRPH_Y_END 0 0x968 1 0 2 GRPH_Y_END 0 14 mmDCP2_INPUT_GAMMA_CONTROL 0 0x969 1 0 2 GRPH_INPUT_GAMMA_MODE 0 0 mmDCP2_GRPH_UPDATE 0 0x96a 11 0 2 GRPH_MODE_UPDATE_PENDING 0 0 GRPH_MODE_UPDATE_TAKEN 1 1 GRPH_SURFACE_UPDATE_PENDING 2 2 GRPH_SURFACE_UPDATE_TAKEN 3 3 GRPH_XDMA_FLIP_TYPE_CLEAR 8 8 GRPH_XDMA_DRR_MODE_ENABLE 9 9 GRPH_XDMA_MULTIFLIP_ENABLE 10 10 GRPH_UPDATE_LOCK 16 16 GRPH_SURFACE_IGNORE_UPDATE_LOCK 20 20 GRPH_MODE_DISABLE_MULTIPLE_UPDATE 24 24 GRPH_SURFACE_DISABLE_MULTIPLE_UPDATE 28 28 mmDCP2_GRPH_FLIP_CONTROL 0 0x96b 4 0 2 GRPH_SURFACE_UPDATE_H_RETRACE_EN 0 0 GRPH_XDMA_SUPER_AA_EN 1 1 GRPH_SURFACE_UPDATE_IMMEDIATE_EN 4 4 GRPH_SURFACE_UPDATE_PENDING_MODE 5 5 mmDCP2_GRPH_SURFACE_ADDRESS_INUSE 0 0x96c 1 0 2 GRPH_SURFACE_ADDRESS_INUSE 8 31 mmDCP2_GRPH_DFQ_CONTROL 0 0x96d 3 0 2 GRPH_DFQ_RESET 0 0 GRPH_DFQ_SIZE 4 6 GRPH_DFQ_MIN_FREE_ENTRIES 8 10 mmDCP2_GRPH_DFQ_STATUS 0 0x96e 4 0 2 GRPH_PRIMARY_DFQ_NUM_ENTRIES 0 3 GRPH_SECONDARY_DFQ_NUM_ENTRIES 4 7 GRPH_DFQ_RESET_FLAG 8 8 GRPH_DFQ_RESET_ACK 9 9 mmDCP2_GRPH_INTERRUPT_STATUS 0 0x96f 2 0 2 GRPH_PFLIP_INT_OCCURRED 0 0 GRPH_PFLIP_INT_CLEAR 8 8 mmDCP2_GRPH_INTERRUPT_CONTROL 0 0x970 2 0 2 GRPH_PFLIP_INT_MASK 0 0 GRPH_PFLIP_INT_TYPE 8 8 mmDCP2_GRPH_SURFACE_ADDRESS_HIGH_INUSE 0 0x971 1 0 2 GRPH_SURFACE_ADDRESS_HIGH_INUSE 0 7 mmDCP2_GRPH_COMPRESS_SURFACE_ADDRESS 0 0x972 1 0 2 GRPH_COMPRESS_SURFACE_ADDRESS 8 31 mmDCP2_GRPH_COMPRESS_PITCH 0 0x973 1 0 2 GRPH_COMPRESS_PITCH 6 16 mmDCP2_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH 0 0x974 1 0 2 GRPH_COMPRESS_SURFACE_ADDRESS_HIGH 0 7 mmDCP2_GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT 0 0x975 1 0 2 GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT 0 7 mmDCP2_PRESCALE_GRPH_CONTROL 0 0x976 5 0 2 GRPH_PRESCALE_SELECT 0 0 GRPH_PRESCALE_R_SIGN 1 1 GRPH_PRESCALE_G_SIGN 2 2 GRPH_PRESCALE_B_SIGN 3 3 GRPH_PRESCALE_BYPASS 4 4 mmDCP2_PRESCALE_VALUES_GRPH_R 0 0x977 2 0 2 GRPH_PRESCALE_BIAS_R 0 15 GRPH_PRESCALE_SCALE_R 16 31 mmDCP2_PRESCALE_VALUES_GRPH_G 0 0x978 2 0 2 GRPH_PRESCALE_BIAS_G 0 15 GRPH_PRESCALE_SCALE_G 16 31 mmDCP2_PRESCALE_VALUES_GRPH_B 0 0x979 2 0 2 GRPH_PRESCALE_BIAS_B 0 15 GRPH_PRESCALE_SCALE_B 16 31 mmDCP2_INPUT_CSC_CONTROL 0 0x97a 1 0 2 INPUT_CSC_GRPH_MODE 0 1 mmDCP2_INPUT_CSC_C11_C12 0 0x97b 2 0 2 INPUT_CSC_C11 0 15 INPUT_CSC_C12 16 31 mmDCP2_INPUT_CSC_C13_C14 0 0x97c 2 0 2 INPUT_CSC_C13 0 15 INPUT_CSC_C14 16 31 mmDCP2_INPUT_CSC_C21_C22 0 0x97d 2 0 2 INPUT_CSC_C21 0 15 INPUT_CSC_C22 16 31 mmDCP2_INPUT_CSC_C23_C24 0 0x97e 2 0 2 INPUT_CSC_C23 0 15 INPUT_CSC_C24 16 31 mmDCP2_INPUT_CSC_C31_C32 0 0x97f 2 0 2 INPUT_CSC_C31 0 15 INPUT_CSC_C32 16 31 mmDCP2_INPUT_CSC_C33_C34 0 0x980 2 0 2 INPUT_CSC_C33 0 15 INPUT_CSC_C34 16 31 mmDCP2_OUTPUT_CSC_CONTROL 0 0x981 1 0 2 OUTPUT_CSC_GRPH_MODE 0 2 mmDCP2_OUTPUT_CSC_C11_C12 0 0x982 2 0 2 OUTPUT_CSC_C11 0 15 OUTPUT_CSC_C12 16 31 mmDCP2_OUTPUT_CSC_C13_C14 0 0x983 2 0 2 OUTPUT_CSC_C13 0 15 OUTPUT_CSC_C14 16 31 mmDCP2_OUTPUT_CSC_C21_C22 0 0x984 2 0 2 OUTPUT_CSC_C21 0 15 OUTPUT_CSC_C22 16 31 mmDCP2_OUTPUT_CSC_C23_C24 0 0x985 2 0 2 OUTPUT_CSC_C23 0 15 OUTPUT_CSC_C24 16 31 mmDCP2_OUTPUT_CSC_C31_C32 0 0x986 2 0 2 OUTPUT_CSC_C31 0 15 OUTPUT_CSC_C32 16 31 mmDCP2_OUTPUT_CSC_C33_C34 0 0x987 2 0 2 OUTPUT_CSC_C33 0 15 OUTPUT_CSC_C34 16 31 mmDCP2_COMM_MATRIXA_TRANS_C11_C12 0 0x988 2 0 2 COMM_MATRIXA_TRANS_C11 0 15 COMM_MATRIXA_TRANS_C12 16 31 mmDCP2_COMM_MATRIXA_TRANS_C13_C14 0 0x989 2 0 2 COMM_MATRIXA_TRANS_C13 0 15 COMM_MATRIXA_TRANS_C14 16 31 mmDCP2_COMM_MATRIXA_TRANS_C21_C22 0 0x98a 2 0 2 COMM_MATRIXA_TRANS_C21 0 15 COMM_MATRIXA_TRANS_C22 16 31 mmDCP2_COMM_MATRIXA_TRANS_C23_C24 0 0x98b 2 0 2 COMM_MATRIXA_TRANS_C23 0 15 COMM_MATRIXA_TRANS_C24 16 31 mmDCP2_COMM_MATRIXA_TRANS_C31_C32 0 0x98c 2 0 2 COMM_MATRIXA_TRANS_C31 0 15 COMM_MATRIXA_TRANS_C32 16 31 mmDCP2_COMM_MATRIXA_TRANS_C33_C34 0 0x98d 2 0 2 COMM_MATRIXA_TRANS_C33 0 15 COMM_MATRIXA_TRANS_C34 16 31 mmDCP2_COMM_MATRIXB_TRANS_C11_C12 0 0x98e 2 0 2 COMM_MATRIXB_TRANS_C11 0 15 COMM_MATRIXB_TRANS_C12 16 31 mmDCP2_COMM_MATRIXB_TRANS_C13_C14 0 0x98f 2 0 2 COMM_MATRIXB_TRANS_C13 0 15 COMM_MATRIXB_TRANS_C14 16 31 mmDCP2_COMM_MATRIXB_TRANS_C21_C22 0 0x990 2 0 2 COMM_MATRIXB_TRANS_C21 0 15 COMM_MATRIXB_TRANS_C22 16 31 mmDCP2_COMM_MATRIXB_TRANS_C23_C24 0 0x991 2 0 2 COMM_MATRIXB_TRANS_C23 0 15 COMM_MATRIXB_TRANS_C24 16 31 mmDCP2_COMM_MATRIXB_TRANS_C31_C32 0 0x992 2 0 2 COMM_MATRIXB_TRANS_C31 0 15 COMM_MATRIXB_TRANS_C32 16 31 mmDCP2_COMM_MATRIXB_TRANS_C33_C34 0 0x993 2 0 2 COMM_MATRIXB_TRANS_C33 0 15 COMM_MATRIXB_TRANS_C34 16 31 mmDCP2_DENORM_CONTROL 0 0x994 2 0 2 DENORM_MODE 0 2 DENORM_14BIT_OUT 4 4 mmDCP2_OUT_ROUND_CONTROL 0 0x995 1 0 2 OUT_ROUND_TRUNC_MODE 0 3 mmDCP2_OUT_CLAMP_CONTROL_R_CR 0 0x996 2 0 2 OUT_CLAMP_MAX_R_CR 0 13 OUT_CLAMP_MIN_R_CR 16 29 mmDCP2_OUT_CLAMP_CONTROL_G_Y 0 0x997 2 0 2 OUT_CLAMP_MAX_G_Y 0 13 OUT_CLAMP_MIN_G_Y 16 29 mmDCP2_OUT_CLAMP_CONTROL_B_CB 0 0x998 2 0 2 OUT_CLAMP_MAX_B_CB 0 13 OUT_CLAMP_MIN_B_CB 16 29 mmDCP2_KEY_CONTROL 0 0x999 1 0 2 KEY_MODE 1 2 mmDCP2_KEY_RANGE_ALPHA 0 0x99a 2 0 2 KEY_ALPHA_LOW 0 15 KEY_ALPHA_HIGH 16 31 mmDCP2_KEY_RANGE_RED 0 0x99b 2 0 2 KEY_RED_LOW 0 15 KEY_RED_HIGH 16 31 mmDCP2_KEY_RANGE_GREEN 0 0x99c 2 0 2 KEY_GREEN_LOW 0 15 KEY_GREEN_HIGH 16 31 mmDCP2_KEY_RANGE_BLUE 0 0x99d 2 0 2 KEY_BLUE_LOW 0 15 KEY_BLUE_HIGH 16 31 mmDCP2_DEGAMMA_CONTROL 0 0x99e 3 0 2 GRPH_DEGAMMA_MODE 0 1 CURSOR2_DEGAMMA_MODE 8 9 CURSOR_DEGAMMA_MODE 12 13 mmDCP2_GAMUT_REMAP_CONTROL 0 0x99f 1 0 2 GRPH_GAMUT_REMAP_MODE 0 1 mmDCP2_GAMUT_REMAP_C11_C12 0 0x9a0 2 0 2 GAMUT_REMAP_C11 0 15 GAMUT_REMAP_C12 16 31 mmDCP2_GAMUT_REMAP_C13_C14 0 0x9a1 2 0 2 GAMUT_REMAP_C13 0 15 GAMUT_REMAP_C14 16 31 mmDCP2_GAMUT_REMAP_C21_C22 0 0x9a2 2 0 2 GAMUT_REMAP_C21 0 15 GAMUT_REMAP_C22 16 31 mmDCP2_GAMUT_REMAP_C23_C24 0 0x9a3 2 0 2 GAMUT_REMAP_C23 0 15 GAMUT_REMAP_C24 16 31 mmDCP2_GAMUT_REMAP_C31_C32 0 0x9a4 2 0 2 GAMUT_REMAP_C31 0 15 GAMUT_REMAP_C32 16 31 mmDCP2_GAMUT_REMAP_C33_C34 0 0x9a5 2 0 2 GAMUT_REMAP_C33 0 15 GAMUT_REMAP_C34 16 31 mmDCP2_DCP_SPATIAL_DITHER_CNTL 0 0x9a6 6 0 2 DCP_SPATIAL_DITHER_EN 0 0 DCP_SPATIAL_DITHER_MODE 4 5 DCP_SPATIAL_DITHER_DEPTH 6 7 DCP_FRAME_RANDOM_ENABLE 8 8 DCP_RGB_RANDOM_ENABLE 9 9 DCP_HIGHPASS_RANDOM_ENABLE 10 10 mmDCP2_DCP_RANDOM_SEEDS 0 0x9a7 3 0 2 DCP_RAND_R_SEED 0 7 DCP_RAND_G_SEED 8 15 DCP_RAND_B_SEED 16 23 mmDCP2_DCP_FP_CONVERTED_FIELD 0 0x9a8 2 0 2 DCP_FP_CONVERTED_FIELD_DATA 0 17 DCP_FP_CONVERTED_FIELD_INDEX 20 26 mmDCP2_CUR_CONTROL 0 0x9a9 8 0 2 CURSOR_EN 0 0 CUR_INV_TRANS_CLAMP 4 4 CURSOR_MODE 8 9 CURSOR_MAX_OUTSTANDING_GROUP_NUM 11 11 CURSOR_BUSY_START_LINE_POSITION 12 15 CURSOR_2X_MAGNIFY 16 16 CURSOR_FORCE_MC_ON 20 20 CURSOR_URGENT_CONTROL 24 26 mmDCP2_CUR_SURFACE_ADDRESS 0 0x9aa 1 0 2 CURSOR_SURFACE_ADDRESS 0 31 mmDCP2_CUR_SIZE 0 0x9ab 2 0 2 CURSOR_HEIGHT 0 6 CURSOR_WIDTH 16 22 mmDCP2_CUR_SURFACE_ADDRESS_HIGH 0 0x9ac 1 0 2 CURSOR_SURFACE_ADDRESS_HIGH 0 7 mmDCP2_CUR_POSITION 0 0x9ad 2 0 2 CURSOR_Y_POSITION 0 13 CURSOR_X_POSITION 16 29 mmDCP2_CUR_HOT_SPOT 0 0x9ae 2 0 2 CURSOR_HOT_SPOT_Y 0 6 CURSOR_HOT_SPOT_X 16 22 mmDCP2_CUR_COLOR1 0 0x9af 3 0 2 CUR_COLOR1_BLUE 0 7 CUR_COLOR1_GREEN 8 15 CUR_COLOR1_RED 16 23 mmDCP2_CUR_COLOR2 0 0x9b0 3 0 2 CUR_COLOR2_BLUE 0 7 CUR_COLOR2_GREEN 8 15 CUR_COLOR2_RED 16 23 mmDCP2_CUR_UPDATE 0 0x9b1 5 0 2 CURSOR_UPDATE_PENDING 0 0 CURSOR_UPDATE_TAKEN 1 1 CURSOR_UPDATE_LOCK 16 16 CURSOR_DISABLE_MULTIPLE_UPDATE 24 24 CURSOR_UPDATE_STEREO_MODE 25 26 mmDCP2_CUR_REQUEST_FILTER_CNTL 0 0x9bb 1 0 2 CUR_REQUEST_FILTER_DIS 0 0 mmDCP2_CUR_STEREO_CONTROL 0 0x9bc 3 0 2 CURSOR_STEREO_EN 0 0 CURSOR_PRIMARY_OFFSET 4 13 CURSOR_SECONDARY_OFFSET 16 25 mmDCP2_DC_LUT_RW_MODE 0 0x9be 3 0 2 DC_LUT_RW_MODE 0 0 DC_LUT_ERROR 16 16 DC_LUT_ERROR_RST 17 17 mmDCP2_DC_LUT_RW_INDEX 0 0x9bf 1 0 2 DC_LUT_RW_INDEX 0 7 mmDCP2_DC_LUT_SEQ_COLOR 0 0x9c0 1 0 2 DC_LUT_SEQ_COLOR 0 15 mmDCP2_DC_LUT_PWL_DATA 0 0x9c1 2 0 2 DC_LUT_BASE 0 15 DC_LUT_DELTA 16 31 mmDCP2_DC_LUT_30_COLOR 0 0x9c2 3 0 2 DC_LUT_COLOR_10_BLUE 0 9 DC_LUT_COLOR_10_GREEN 10 19 DC_LUT_COLOR_10_RED 20 29 mmDCP2_DC_LUT_VGA_ACCESS_ENABLE 0 0x9c3 1 0 2 DC_LUT_VGA_ACCESS_ENABLE 0 0 mmDCP2_DC_LUT_WRITE_EN_MASK 0 0x9c4 1 0 2 DC_LUT_WRITE_EN_MASK 0 2 mmDCP2_DC_LUT_AUTOFILL 0 0x9c5 2 0 2 DC_LUT_AUTOFILL 0 0 DC_LUT_AUTOFILL_DONE 1 1 mmDCP2_DC_LUT_CONTROL 0 0x9c6 12 0 2 DC_LUT_INC_B 0 3 DC_LUT_DATA_B_SIGNED_EN 4 4 DC_LUT_DATA_B_FLOAT_POINT_EN 5 5 DC_LUT_DATA_B_FORMAT 6 7 DC_LUT_INC_G 8 11 DC_LUT_DATA_G_SIGNED_EN 12 12 DC_LUT_DATA_G_FLOAT_POINT_EN 13 13 DC_LUT_DATA_G_FORMAT 14 15 DC_LUT_INC_R 16 19 DC_LUT_DATA_R_SIGNED_EN 20 20 DC_LUT_DATA_R_FLOAT_POINT_EN 21 21 DC_LUT_DATA_R_FORMAT 22 23 mmDCP2_DC_LUT_BLACK_OFFSET_BLUE 0 0x9c7 1 0 2 DC_LUT_BLACK_OFFSET_BLUE 0 15 mmDCP2_DC_LUT_BLACK_OFFSET_GREEN 0 0x9c8 1 0 2 DC_LUT_BLACK_OFFSET_GREEN 0 15 mmDCP2_DC_LUT_BLACK_OFFSET_RED 0 0x9c9 1 0 2 DC_LUT_BLACK_OFFSET_RED 0 15 mmDCP2_DC_LUT_WHITE_OFFSET_BLUE 0 0x9ca 1 0 2 DC_LUT_WHITE_OFFSET_BLUE 0 15 mmDCP2_DC_LUT_WHITE_OFFSET_GREEN 0 0x9cb 1 0 2 DC_LUT_WHITE_OFFSET_GREEN 0 15 mmDCP2_DC_LUT_WHITE_OFFSET_RED 0 0x9cc 1 0 2 DC_LUT_WHITE_OFFSET_RED 0 15 mmDCP2_DCP_CRC_CONTROL 0 0x9cd 3 0 2 DCP_CRC_ENABLE 0 0 DCP_CRC_SOURCE_SEL 2 4 DCP_CRC_LINE_SEL 8 9 mmDCP2_DCP_CRC_MASK 0 0x9ce 1 0 2 DCP_CRC_MASK 0 31 mmDCP2_DCP_CRC_CURRENT 0 0x9cf 1 0 2 DCP_CRC_CURRENT 0 31 mmDCP2_DVMM_PTE_CONTROL 0 0x9d0 6 0 2 DVMM_USE_SINGLE_PTE 0 0 DVMM_PAGE_WIDTH 1 4 DVMM_PAGE_HEIGHT 5 8 DVMM_MIN_PTE_BEFORE_FLIP 9 18 DVMM_PTE_BUFFER_MODE0 20 20 DVMM_PTE_BUFFER_MODE1 21 21 mmDCP2_DCP_CRC_LAST 0 0x9d1 1 0 2 DCP_CRC_LAST 0 31 mmDCP2_DVMM_PTE_ARB_CONTROL 0 0x9d2 2 0 2 DVMM_PTE_REQ_PER_CHUNK 0 5 DVMM_MAX_PTE_REQ_OUTSTANDING 8 15 mmDCP2_GRPH_FLIP_RATE_CNTL 0 0x9d4 2 0 2 GRPH_FLIP_RATE 0 2 GRPH_FLIP_RATE_ENABLE 3 3 mmDCP2_DCP_GSL_CONTROL 0 0x9d5 11 0 2 DCP_GSL0_EN 0 0 DCP_GSL1_EN 1 1 DCP_GSL2_EN 2 2 DCP_GSL_HSYNC_FLIP_FORCE_DELAY 4 19 DCP_GSL_MASTER_EN 20 20 DCP_GSL_XDMA_GROUP 21 22 DCP_GSL_XDMA_GROUP_UNDERFLOW_EN 23 23 DCP_GSL_SYNC_SOURCE 24 25 DCP_GSL_USE_CHECKPOINT_WINDOW_IN_VSYNC 26 26 DCP_GSL_DELAY_SURFACE_UPDATE_PENDING 27 27 DCP_GSL_HSYNC_FLIP_CHECK_DELAY 28 31 mmDCP2_DCP_LB_DATA_GAP_BETWEEN_CHUNK 0 0x9d6 2 0 2 DCP_LB_GAP_BETWEEN_CHUNK_20BPP 0 3 DCP_LB_GAP_BETWEEN_CHUNK_30BPP 4 8 mmDCP2_GRPH_STEREOSYNC_FLIP 0 0x9dc 5 0 2 GRPH_STEREOSYNC_FLIP_EN 0 0 GRPH_STEREOSYNC_FLIP_MODE 8 9 GRPH_PRIMARY_SURFACE_PENDING 16 16 GRPH_SECONDARY_SURFACE_PENDING 17 17 GRPH_STEREOSYNC_SELECT_DISABLE 28 28 mmDCP2_HW_ROTATION 0 0x9de 1 0 2 GRPH_ROTATION_ANGLE 0 2 mmDCP2_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL 0 0x9df 3 0 2 GRPH_XDMA_CACHE_UNDERFLOW_CNT_EN 0 0 GRPH_XDMA_CACHE_UNDERFLOW_CNT_MODE 1 1 GRPH_XDMA_CACHE_UNDERFLOW_FRAME_CNT 4 16 mmDCP2_REGAMMA_CONTROL 0 0x9e0 1 0 2 GRPH_REGAMMA_MODE 0 2 mmDCP2_REGAMMA_LUT_INDEX 0 0x9e1 1 0 2 REGAMMA_LUT_INDEX 0 8 mmDCP2_REGAMMA_LUT_DATA 0 0x9e2 1 0 2 REGAMMA_LUT_DATA 0 18 mmDCP2_REGAMMA_LUT_WRITE_EN_MASK 0 0x9e3 1 0 2 REGAMMA_LUT_WRITE_EN_MASK 0 2 mmDCP2_REGAMMA_CNTLA_START_CNTL 0 0x9e4 2 0 2 REGAMMA_CNTLA_EXP_REGION_START 0 17 REGAMMA_CNTLA_EXP_REGION_START_SEGMENT 20 26 mmDCP2_REGAMMA_CNTLA_SLOPE_CNTL 0 0x9e5 1 0 2 REGAMMA_CNTLA_EXP_REGION_LINEAR_SLOPE 0 17 mmDCP2_REGAMMA_CNTLA_END_CNTL1 0 0x9e6 1 0 2 REGAMMA_CNTLA_EXP_REGION_END 0 15 mmDCP2_REGAMMA_CNTLA_END_CNTL2 0 0x9e7 2 0 2 REGAMMA_CNTLA_EXP_REGION_END_SLOPE 0 15 REGAMMA_CNTLA_EXP_REGION_END_BASE 16 31 mmDCP2_REGAMMA_CNTLA_REGION_0_1 0 0x9e8 4 0 2 REGAMMA_CNTLA_EXP_REGION0_LUT_OFFSET 0 8 REGAMMA_CNTLA_EXP_REGION0_NUM_SEGMENTS 12 14 REGAMMA_CNTLA_EXP_REGION1_LUT_OFFSET 16 24 REGAMMA_CNTLA_EXP_REGION1_NUM_SEGMENTS 28 30 mmDCP2_REGAMMA_CNTLA_REGION_2_3 0 0x9e9 4 0 2 REGAMMA_CNTLA_EXP_REGION2_LUT_OFFSET 0 8 REGAMMA_CNTLA_EXP_REGION2_NUM_SEGMENTS 12 14 REGAMMA_CNTLA_EXP_REGION3_LUT_OFFSET 16 24 REGAMMA_CNTLA_EXP_REGION3_NUM_SEGMENTS 28 30 mmDCP2_REGAMMA_CNTLA_REGION_4_5 0 0x9ea 4 0 2 REGAMMA_CNTLA_EXP_REGION4_LUT_OFFSET 0 8 REGAMMA_CNTLA_EXP_REGION4_NUM_SEGMENTS 12 14 REGAMMA_CNTLA_EXP_REGION5_LUT_OFFSET 16 24 REGAMMA_CNTLA_EXP_REGION5_NUM_SEGMENTS 28 30 mmDCP2_REGAMMA_CNTLA_REGION_6_7 0 0x9eb 4 0 2 REGAMMA_CNTLA_EXP_REGION6_LUT_OFFSET 0 8 REGAMMA_CNTLA_EXP_REGION6_NUM_SEGMENTS 12 14 REGAMMA_CNTLA_EXP_REGION7_LUT_OFFSET 16 24 REGAMMA_CNTLA_EXP_REGION7_NUM_SEGMENTS 28 30 mmDCP2_REGAMMA_CNTLA_REGION_8_9 0 0x9ec 4 0 2 REGAMMA_CNTLA_EXP_REGION8_LUT_OFFSET 0 8 REGAMMA_CNTLA_EXP_REGION8_NUM_SEGMENTS 12 14 REGAMMA_CNTLA_EXP_REGION9_LUT_OFFSET 16 24 REGAMMA_CNTLA_EXP_REGION9_NUM_SEGMENTS 28 30 mmDCP2_REGAMMA_CNTLA_REGION_10_11 0 0x9ed 4 0 2 REGAMMA_CNTLA_EXP_REGION10_LUT_OFFSET 0 8 REGAMMA_CNTLA_EXP_REGION10_NUM_SEGMENTS 12 14 REGAMMA_CNTLA_EXP_REGION11_LUT_OFFSET 16 24 REGAMMA_CNTLA_EXP_REGION11_NUM_SEGMENTS 28 30 mmDCP2_REGAMMA_CNTLA_REGION_12_13 0 0x9ee 4 0 2 REGAMMA_CNTLA_EXP_REGION12_LUT_OFFSET 0 8 REGAMMA_CNTLA_EXP_REGION12_NUM_SEGMENTS 12 14 REGAMMA_CNTLA_EXP_REGION13_LUT_OFFSET 16 24 REGAMMA_CNTLA_EXP_REGION13_NUM_SEGMENTS 28 30 mmDCP2_REGAMMA_CNTLA_REGION_14_15 0 0x9ef 4 0 2 REGAMMA_CNTLA_EXP_REGION14_LUT_OFFSET 0 8 REGAMMA_CNTLA_EXP_REGION14_NUM_SEGMENTS 12 14 REGAMMA_CNTLA_EXP_REGION15_LUT_OFFSET 16 24 REGAMMA_CNTLA_EXP_REGION15_NUM_SEGMENTS 28 30 mmDCP2_REGAMMA_CNTLB_START_CNTL 0 0x9f0 2 0 2 REGAMMA_CNTLB_EXP_REGION_START 0 17 REGAMMA_CNTLB_EXP_REGION_START_SEGMENT 20 26 mmDCP2_REGAMMA_CNTLB_SLOPE_CNTL 0 0x9f1 1 0 2 REGAMMA_CNTLB_EXP_REGION_LINEAR_SLOPE 0 17 mmDCP2_REGAMMA_CNTLB_END_CNTL1 0 0x9f2 1 0 2 REGAMMA_CNTLB_EXP_REGION_END 0 15 mmDCP2_REGAMMA_CNTLB_END_CNTL2 0 0x9f3 2 0 2 REGAMMA_CNTLB_EXP_REGION_END_SLOPE 0 15 REGAMMA_CNTLB_EXP_REGION_END_BASE 16 31 mmDCP2_REGAMMA_CNTLB_REGION_0_1 0 0x9f4 4 0 2 REGAMMA_CNTLB_EXP_REGION0_LUT_OFFSET 0 8 REGAMMA_CNTLB_EXP_REGION0_NUM_SEGMENTS 12 14 REGAMMA_CNTLB_EXP_REGION1_LUT_OFFSET 16 24 REGAMMA_CNTLB_EXP_REGION1_NUM_SEGMENTS 28 30 mmDCP2_REGAMMA_CNTLB_REGION_2_3 0 0x9f5 4 0 2 REGAMMA_CNTLB_EXP_REGION2_LUT_OFFSET 0 8 REGAMMA_CNTLB_EXP_REGION2_NUM_SEGMENTS 12 14 REGAMMA_CNTLB_EXP_REGION3_LUT_OFFSET 16 24 REGAMMA_CNTLB_EXP_REGION3_NUM_SEGMENTS 28 30 mmDCP2_REGAMMA_CNTLB_REGION_4_5 0 0x9f6 4 0 2 REGAMMA_CNTLB_EXP_REGION4_LUT_OFFSET 0 8 REGAMMA_CNTLB_EXP_REGION4_NUM_SEGMENTS 12 14 REGAMMA_CNTLB_EXP_REGION5_LUT_OFFSET 16 24 REGAMMA_CNTLB_EXP_REGION5_NUM_SEGMENTS 28 30 mmDCP2_REGAMMA_CNTLB_REGION_6_7 0 0x9f7 4 0 2 REGAMMA_CNTLB_EXP_REGION6_LUT_OFFSET 0 8 REGAMMA_CNTLB_EXP_REGION6_NUM_SEGMENTS 12 14 REGAMMA_CNTLB_EXP_REGION7_LUT_OFFSET 16 24 REGAMMA_CNTLB_EXP_REGION7_NUM_SEGMENTS 28 30 mmDCP2_REGAMMA_CNTLB_REGION_8_9 0 0x9f8 4 0 2 REGAMMA_CNTLB_EXP_REGION8_LUT_OFFSET 0 8 REGAMMA_CNTLB_EXP_REGION8_NUM_SEGMENTS 12 14 REGAMMA_CNTLB_EXP_REGION9_LUT_OFFSET 16 24 REGAMMA_CNTLB_EXP_REGION9_NUM_SEGMENTS 28 30 mmDCP2_REGAMMA_CNTLB_REGION_10_11 0 0x9f9 4 0 2 REGAMMA_CNTLB_EXP_REGION10_LUT_OFFSET 0 8 REGAMMA_CNTLB_EXP_REGION10_NUM_SEGMENTS 12 14 REGAMMA_CNTLB_EXP_REGION11_LUT_OFFSET 16 24 REGAMMA_CNTLB_EXP_REGION11_NUM_SEGMENTS 28 30 mmDCP2_REGAMMA_CNTLB_REGION_12_13 0 0x9fa 4 0 2 REGAMMA_CNTLB_EXP_REGION12_LUT_OFFSET 0 8 REGAMMA_CNTLB_EXP_REGION12_NUM_SEGMENTS 12 14 REGAMMA_CNTLB_EXP_REGION13_LUT_OFFSET 16 24 REGAMMA_CNTLB_EXP_REGION13_NUM_SEGMENTS 28 30 mmDCP2_REGAMMA_CNTLB_REGION_14_15 0 0x9fb 4 0 2 REGAMMA_CNTLB_EXP_REGION14_LUT_OFFSET 0 8 REGAMMA_CNTLB_EXP_REGION14_NUM_SEGMENTS 12 14 REGAMMA_CNTLB_EXP_REGION15_LUT_OFFSET 16 24 REGAMMA_CNTLB_EXP_REGION15_NUM_SEGMENTS 28 30 mmDCP2_ALPHA_CONTROL 0 0x9fc 2 0 2 ALPHA_ROUND_TRUNC_MODE 0 0 CURSOR_ALPHA_BLND_ENA 1 1 mmDCP2_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS 0 0x9fd 1 0 2 GRPH_XDMA_RECOVERY_SURFACE_ADDRESS 8 31 mmDCP2_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH 0 0x9fe 1 0 2 GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH 0 7 mmDCP2_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS 0 0x9ff 7 0 2 GRPH_XDMA_CACHE_UNDERFLOW_CNT 0 19 GRPH_XDMA_CACHE_UNDERFLOW_CNT_STATUS 24 24 GRPH_XDMA_CACHE_UNDERFLOW_FRAME_MASK 25 25 GRPH_XDMA_CACHE_UNDERFLOW_FRAME_ACK 26 26 GRPH_XDMA_CACHE_UNDERFLOW_INT 28 28 GRPH_XDMA_CACHE_UNDERFLOW_INT_MASK 29 29 GRPH_XDMA_CACHE_UNDERFLOW_INT_ACK 30 30 mmDCP2_GRPH_XDMA_FLIP_TIMEOUT 0 0xa00 3 0 2 GRPH_XDMA_FLIP_TIMEOUT_STATUS 0 0 GRPH_XDMA_FLIP_TIMEOUT_MASK 1 1 GRPH_XDMA_FLIP_TIMEOUT_ACK 2 2 mmDCP2_GRPH_XDMA_FLIP_AVG_DELAY 0 0xa01 2 0 2 GRPH_XDMA_FLIP_AVG_DELAY 0 15 GRPH_XDMA_FLIP_AVG_PERIOD 16 23 mmDCP2_GRPH_SURFACE_COUNTER_CONTROL 0 0xa02 3 0 2 GRPH_SURFACE_COUNTER_EN 0 0 GRPH_SURFACE_COUNTER_EVENT_SELECT 1 4 GRPH_SURFACE_COUNTER_ERR_WRAP_OCCURED 9 9 mmDCP2_GRPH_SURFACE_COUNTER_OUTPUT 0 0xa03 2 0 2 GRPH_SURFACE_COUNTER_MIN 0 15 GRPH_SURFACE_COUNTER_MAX 16 31 mmLB2_LB_DATA_FORMAT 0 0xa1a 9 0 2 PIXEL_DEPTH 0 1 PIXEL_EXPAN_MODE 2 2 INTERLEAVE_EN 3 3 PIXEL_REDUCE_MODE 4 4 DYNAMIC_PIXEL_DEPTH 5 5 PREFILL_EN 8 8 PREFETCH 12 12 REQUEST_MODE 24 24 ALPHA_EN 31 31 mmLB2_LB_MEMORY_CTRL 0 0xa1b 3 0 2 LB_MEMORY_SIZE 0 12 LB_NUM_PARTITIONS 16 19 LB_MEMORY_CONFIG 20 21 mmLB2_LB_MEMORY_SIZE_STATUS 0 0xa1c 1 0 2 LB_MEMORY_SIZE_STATUS 0 12 mmLB2_LB_DESKTOP_HEIGHT 0 0xa1d 1 0 2 DESKTOP_HEIGHT 0 14 mmLB2_LB_VLINE_START_END 0 0xa1e 3 0 2 VLINE_START 0 13 VLINE_END 16 30 VLINE_INV 31 31 mmLB2_LB_VLINE2_START_END 0 0xa1f 3 0 2 VLINE2_START 0 13 VLINE2_END 16 30 VLINE2_INV 31 31 mmLB2_LB_V_COUNTER 0 0xa20 1 0 2 V_COUNTER 0 14 mmLB2_LB_SNAPSHOT_V_COUNTER 0 0xa21 1 0 2 SNAPSHOT_V_COUNTER 0 14 mmLB2_LB_INTERRUPT_MASK 0 0xa22 3 0 2 VBLANK_INTERRUPT_MASK 0 0 VLINE_INTERRUPT_MASK 4 4 VLINE2_INTERRUPT_MASK 8 8 mmLB2_LB_VLINE_STATUS 0 0xa23 5 0 2 VLINE_OCCURRED 0 0 VLINE_ACK 4 4 VLINE_STAT 12 12 VLINE_INTERRUPT 16 16 VLINE_INTERRUPT_TYPE 17 17 mmLB2_LB_VLINE2_STATUS 0 0xa24 5 0 2 VLINE2_OCCURRED 0 0 VLINE2_ACK 4 4 VLINE2_STAT 12 12 VLINE2_INTERRUPT 16 16 VLINE2_INTERRUPT_TYPE 17 17 mmLB2_LB_VBLANK_STATUS 0 0xa25 5 0 2 VBLANK_OCCURRED 0 0 VBLANK_ACK 4 4 VBLANK_STAT 12 12 VBLANK_INTERRUPT 16 16 VBLANK_INTERRUPT_TYPE 17 17 mmLB2_LB_SYNC_RESET_SEL 0 0xa26 4 0 2 LB_SYNC_RESET_SEL 0 1 LB_SYNC_RESET_SEL2 4 4 LB_SYNC_RESET_DELAY 8 15 LB_SYNC_DURATION 22 23 mmLB2_LB_BLACK_KEYER_R_CR 0 0xa27 1 0 2 LB_BLACK_KEYER_R_CR 4 15 mmLB2_LB_BLACK_KEYER_G_Y 0 0xa28 1 0 2 LB_BLACK_KEYER_G_Y 4 15 mmLB2_LB_BLACK_KEYER_B_CB 0 0xa29 1 0 2 LB_BLACK_KEYER_B_CB 4 15 mmLB2_LB_KEYER_COLOR_CTRL 0 0xa2a 2 0 2 LB_KEYER_COLOR_EN 0 0 LB_KEYER_COLOR_REP_EN 8 8 mmLB2_LB_KEYER_COLOR_R_CR 0 0xa2b 1 0 2 LB_KEYER_COLOR_R_CR 4 15 mmLB2_LB_KEYER_COLOR_G_Y 0 0xa2c 1 0 2 LB_KEYER_COLOR_G_Y 4 15 mmLB2_LB_KEYER_COLOR_B_CB 0 0xa2d 1 0 2 LB_KEYER_COLOR_B_CB 4 15 mmLB2_LB_KEYER_COLOR_REP_R_CR 0 0xa2e 1 0 2 LB_KEYER_COLOR_REP_R_CR 4 15 mmLB2_LB_KEYER_COLOR_REP_G_Y 0 0xa2f 1 0 2 LB_KEYER_COLOR_REP_G_Y 4 15 mmLB2_LB_KEYER_COLOR_REP_B_CB 0 0xa30 1 0 2 LB_KEYER_COLOR_REP_B_CB 4 15 mmLB2_LB_BUFFER_LEVEL_STATUS 0 0xa31 4 0 2 REQ_FIFO_LEVEL 0 5 REQ_FIFO_FULL_CNTL 10 15 DATA_BUFFER_LEVEL 16 27 DATA_FIFO_FULL_CNTL 28 31 mmLB2_LB_BUFFER_URGENCY_CTRL 0 0xa32 2 0 2 LB_BUFFER_URGENCY_MARK_ON 0 11 LB_BUFFER_URGENCY_MARK_OFF 16 27 mmLB2_LB_BUFFER_URGENCY_STATUS 0 0xa33 2 0 2 LB_BUFFER_URGENCY_LEVEL 0 11 LB_BUFFER_URGENCY_STAT 16 16 mmLB2_LB_BUFFER_STATUS 0 0xa34 7 0 2 LB_BUFFER_EMPTY_MARGIN 0 3 LB_BUFFER_EMPTY_STAT 4 4 LB_BUFFER_EMPTY_OCCURRED 8 8 LB_BUFFER_EMPTY_ACK 12 12 LB_BUFFER_FULL_STAT 16 16 LB_BUFFER_FULL_OCCURRED 20 20 LB_BUFFER_FULL_ACK 24 24 mmLB2_LB_NO_OUTSTANDING_REQ_STATUS 0 0xa35 1 0 2 LB_NO_OUTSTANDING_REQ_STAT 0 0 mmLB2_MVP_AFR_FLIP_MODE 0 0xa36 1 0 2 MVP_AFR_FLIP_MODE 0 1 mmLB2_MVP_AFR_FLIP_FIFO_CNTL 0 0xa37 4 0 2 MVP_AFR_FLIP_FIFO_NUM_ENTRIES 0 3 MVP_AFR_FLIP_FIFO_RESET 4 4 MVP_AFR_FLIP_FIFO_RESET_FLAG 8 8 MVP_AFR_FLIP_FIFO_RESET_ACK 12 12 mmLB2_MVP_FLIP_LINE_NUM_INSERT 0 0xa38 4 0 2 MVP_FLIP_LINE_NUM_INSERT_MODE 0 1 MVP_FLIP_LINE_NUM_INSERT 8 22 MVP_FLIP_LINE_NUM_OFFSET 24 29 MVP_FLIP_AUTO_ENABLE 30 30 mmLB2_DC_MVP_LB_CONTROL 0 0xa39 7 0 2 MVP_SWAP_LOCK_IN_MODE 0 1 DC_MVP_SWAP_LOCK_OUT_SEL 8 8 DC_MVP_SWAP_LOCK_OUT_FORCE_ONE 12 12 DC_MVP_SWAP_LOCK_OUT_FORCE_ZERO 16 16 DC_MVP_SWAP_LOCK_STATUS 20 20 DC_MVP_SWAP_LOCK_IN_CAP 28 28 DC_MVP_SPARE_FLOPS 31 31 mmDCFE2_DCFE_CLOCK_CONTROL 0 0xa5a 7 0 2 DISPCLK_R_DCFE_GATE_DISABLE 4 4 DISPCLK_G_DCP_GATE_DISABLE 8 8 DISPCLK_G_SCL_GATE_DISABLE 12 12 DISPCLK_G_PSCL_GATE_DISABLE 15 15 DISPCLK_G_PIPE_REQUEST_DIS_GATE_DISABLE 17 17 DCFE_TEST_CLK_SEL 24 28 DCFE_CLOCK_ENABLE 31 31 mmDCFE2_DCFE_SOFT_RESET 0 0xa5b 6 0 2 DCP_PIXPIPE_SOFT_RESET 0 0 DCP_REQ_SOFT_RESET 1 1 SCL_ALU_SOFT_RESET 2 2 SCL_SOFT_RESET 3 3 CRTC_SOFT_RESET 4 4 PSCL_SOFT_RESET 5 5 mmDCFE2_DCFE_MEM_PWR_CTRL 0 0xa5d 20 0 2 DCP_LUT_MEM_PWR_FORCE 0 1 DCP_LUT_MEM_PWR_DIS 2 2 DCP_REGAMMA_MEM_PWR_FORCE 3 4 DCP_REGAMMA_MEM_PWR_DIS 5 5 SCL_COEFF_MEM_PWR_FORCE 6 7 SCL_COEFF_MEM_PWR_DIS 8 8 DCP_CURSOR_MEM_PWR_FORCE 9 10 DCP_CURSOR_MEM_PWR_DIS 11 11 LB0_ALPHA_MEM_PWR_FORCE 12 13 LB0_ALPHA_MEM_PWR_DIS 14 14 LB1_ALPHA_MEM_PWR_FORCE 15 16 LB1_ALPHA_MEM_PWR_DIS 17 17 LB2_ALPHA_MEM_PWR_FORCE 18 19 LB2_ALPHA_MEM_PWR_DIS 20 20 LB0_MEM_PWR_FORCE 21 22 LB0_MEM_PWR_DIS 23 23 LB1_MEM_PWR_FORCE 24 25 LB1_MEM_PWR_DIS 26 26 LB2_MEM_PWR_FORCE 27 28 LB2_MEM_PWR_DIS 29 29 mmDCFE2_DCFE_MEM_PWR_CTRL2 0 0xa5e 12 0 2 DCP_LUT_MEM_PWR_MODE_SEL 0 1 DCP_REGAMMA_MEM_PWR_MODE_SEL 2 3 SCL_COEFF_MEM_PWR_MODE_SEL 4 5 DCP_CURSOR_MEM_PWR_MODE_SEL 6 7 LB_ALPHA_MEM_PWR_MODE_SEL 8 9 LB_MEM_PWR_MODE_SEL 10 11 DCP_CURSOR2_MEM_PWR_MODE_SEL 12 13 BLND_MEM_PWR_MODE_SEL 14 15 BLND_MEM_PWR_FORCE 16 17 BLND_MEM_PWR_DIS 18 18 DCP_CURSOR2_MEM_PWR_FORCE 21 22 DCP_CURSOR2_MEM_PWR_DIS 23 23 mmDCFE2_DCFE_MEM_PWR_STATUS 0 0xa5f 12 0 2 DCP_LUT_MEM_PWR_STATE 0 1 DCP_REGAMMA_MEM_PWR_STATE 2 3 SCL_COEFF_MEM_PWR_STATE 4 5 DCP_CURSOR_MEM_PWR_STATE 6 7 DCP_CURSOR2_MEM_PWR_STATE 8 9 LB0_ALPHA_MEM_PWR_STATE 10 11 LB1_ALPHA_MEM_PWR_STATE 12 13 LB2_ALPHA_MEM_PWR_STATE 14 15 LB0_MEM_PWR_STATE 16 17 LB1_MEM_PWR_STATE 18 19 LB2_MEM_PWR_STATE 20 21 BLND_MEM_PWR_STATE 22 23 mmDCFE2_DCFE_MISC 0 0xa60 1 0 2 DCFE_DPG_ALLOW_SR_ECO_EN 0 0 mmDCFE2_DCFE_FLUSH 0 0xa61 5 0 2 FLUSH_OCCURED 0 0 CLEAR_FLUSH_OCCURED 1 1 FLUSH_DEEP 2 2 CLEAR_FLUSH_DEEP 3 3 ALL_MC_REQ_RET 4 4 mmDC_PERFMON5_PERFCOUNTER_CNTL 0 0xa6e 13 0 2 PERFCOUNTER_EVENT_SEL 0 8 PERFCOUNTER_CVALUE_SEL 9 11 PERFCOUNTER_INC_MODE 12 14 PERFCOUNTER_HW_CNTL_SEL 15 15 PERFCOUNTER_RUNEN_MODE 16 16 PERFCOUNTER_CNTOFF_SEL 17 21 PERFCOUNTER_CNTOFF_START_DIS 22 22 PERFCOUNTER_RESTART_EN 23 23 PERFCOUNTER_INT_EN 24 24 PERFCOUNTER_OFF_MASK 25 25 PERFCOUNTER_ACTIVE 26 26 PERFCOUNTER_INT_TYPE 27 27 PERFCOUNTER_CNTL_SEL 29 31 mmDC_PERFMON5_PERFCOUNTER_CNTL2 0 0xa6f 4 0 2 PERFCOUNTER_COUNTED_VALUE_TYPE 0 1 PERFCOUNTER_HW_STOP1_SEL 2 2 PERFCOUNTER_HW_STOP2_SEL 3 3 PERFCOUNTER_CNTL2_SEL 29 31 mmDC_PERFMON5_PERFCOUNTER_STATE 0 0xa70 16 0 2 PERFCOUNTER_CNT0_STATE 0 1 PERFCOUNTER_STATE_SEL0 2 2 PERFCOUNTER_CNT1_STATE 4 5 PERFCOUNTER_STATE_SEL1 6 6 PERFCOUNTER_CNT2_STATE 8 9 PERFCOUNTER_STATE_SEL2 10 10 PERFCOUNTER_CNT3_STATE 12 13 PERFCOUNTER_STATE_SEL3 14 14 PERFCOUNTER_CNT4_STATE 16 17 PERFCOUNTER_STATE_SEL4 18 18 PERFCOUNTER_CNT5_STATE 20 21 PERFCOUNTER_STATE_SEL5 22 22 PERFCOUNTER_CNT6_STATE 24 25 PERFCOUNTER_STATE_SEL6 26 26 PERFCOUNTER_CNT7_STATE 28 29 PERFCOUNTER_STATE_SEL7 30 30 mmDC_PERFMON5_PERFMON_CNTL 0 0xa71 6 0 2 PERFMON_STATE 0 1 PERFMON_RPT_COUNT 8 27 PERFMON_CNTOFF_AND_OR 28 28 PERFMON_CNTOFF_INT_EN 29 29 PERFMON_CNTOFF_INT_STATUS 30 30 PERFMON_CNTOFF_INT_ACK 31 31 mmDC_PERFMON5_PERFMON_CNTL2 0 0xa72 4 0 2 PERFMON_CNTOFF_INT_TYPE 0 0 PERFMON_CLK_ENABLE 1 1 PERFMON_RUN_ENABLE_START_SEL 2 9 PERFMON_RUN_ENABLE_STOP_SEL 10 17 mmDC_PERFMON5_PERFMON_CVALUE_INT_MISC 0 0xa73 17 0 2 PERFCOUNTER_INT0_STATUS 0 0 PERFCOUNTER_INT1_STATUS 1 1 PERFCOUNTER_INT2_STATUS 2 2 PERFCOUNTER_INT3_STATUS 3 3 PERFCOUNTER_INT4_STATUS 4 4 PERFCOUNTER_INT5_STATUS 5 5 PERFCOUNTER_INT6_STATUS 6 6 PERFCOUNTER_INT7_STATUS 7 7 PERFCOUNTER_INT0_ACK 8 8 PERFCOUNTER_INT1_ACK 9 9 PERFCOUNTER_INT2_ACK 10 10 PERFCOUNTER_INT3_ACK 11 11 PERFCOUNTER_INT4_ACK 12 12 PERFCOUNTER_INT5_ACK 13 13 PERFCOUNTER_INT6_ACK 14 14 PERFCOUNTER_INT7_ACK 15 15 PERFMON_CVALUE_HI 16 31 mmDC_PERFMON5_PERFMON_CVALUE_LOW 0 0xa74 1 0 2 PERFMON_CVALUE_LOW 0 31 mmDC_PERFMON5_PERFMON_HI 0 0xa75 2 0 2 PERFMON_HI 0 15 PERFMON_READ_SEL 29 31 mmDC_PERFMON5_PERFMON_LOW 0 0xa76 1 0 2 PERFMON_LOW 0 31 mmDMIF_PG2_DPG_PIPE_ARBITRATION_CONTROL1 0 0xa7a 2 0 2 PIXEL_DURATION 0 15 BASE_WEIGHT 16 31 mmDMIF_PG2_DPG_PIPE_ARBITRATION_CONTROL2 0 0xa7b 2 0 2 TIME_WEIGHT 0 15 URGENCY_WEIGHT 16 31 mmDMIF_PG2_DPG_WATERMARK_MASK_CONTROL 0 0xa7c 8 0 2 STUTTER_EXIT_SELF_REFRESH_WATERMARK_MASK 0 2 STUTTER_ENTER_SELF_REFRESH_WATERMARK_MASK 4 6 URGENCY_WATERMARK_MASK 8 10 URGENT_LEVEL_WATERMARK_MASK 12 14 PSTATE_CHANGE_WATERMARK_MASK 15 17 DISABLE_FLIP_URGENT 18 18 URGENT_LEVEL_RAMP_CONTROL 19 19 STATIC_URGENT_LEVEL 20 29 mmDMIF_PG2_DPG_PIPE_URGENCY_CONTROL 0 0xa7d 2 0 2 URGENCY_LOW_WATERMARK 0 15 URGENCY_HIGH_WATERMARK 16 31 mmDMIF_PG2_DPG_PIPE_URGENT_LEVEL_CONTROL 0 0xa7e 2 0 2 URGENT_LEVEL_LOW_WATERMARK 0 15 URGENT_LEVEL_HIGH_WATERMARK 16 31 mmDMIF_PG2_DPG_PIPE_STUTTER_CONTROL 0 0xa7f 14 0 2 STUTTER_ENABLE 0 0 STUTTER_IGNORE_CURSOR 4 4 STUTTER_IGNORE_ICON 5 5 STUTTER_IGNORE_VGA 6 6 STUTTER_IGNORE_FBC 7 7 STUTTER_URGENT_IN_NOT_SELF_REFRESH 10 10 STUTTER_SELF_REFRESH_FORCE_ON 11 11 STUTTER_ENABLE_NONLPTCH 16 16 STUTTER_IGNORE_CURSOR_NONLPTCH 20 20 STUTTER_IGNORE_ICON_NONLPTCH 21 21 STUTTER_IGNORE_VGA_NONLPTCH 22 22 STUTTER_IGNORE_FBC_NONLPTCH 23 23 STUTTER_URGENT_IN_NOT_SELF_REFRESH_NONLPTCH 26 26 STUTTER_SELF_REFRESH_FORCE_ON_NONLPTCH 27 27 mmDMIF_PG2_DPG_PIPE_STUTTER_CONTROL2 0 0xa80 2 0 2 STUTTER_EXIT_SELF_REFRESH_WATERMARK 0 15 STUTTER_ENTER_SELF_REFRESH_WATERMARK 16 31 mmDMIF_PG2_DPG_PIPE_LOW_POWER_CONTROL 0 0xa81 7 0 2 PSTATE_CHANGE_ENABLE 0 0 DPM_ENABLE 1 1 PSTATE_CHANGE_URGENT_DURING_REQUEST 4 4 PSTATE_CHANGE_NOT_SELF_REFRESH_DURING_REQUEST 8 8 PSTATE_CHANGE_FORCE_ON 9 9 PSTATE_ALLOW_FOR_URGENT 10 10 PSTATE_CHANGE_WATERMARK 15 31 mmDMIF_PG2_DPG_REPEATER_PROGRAM 0 0xa82 2 0 2 REG_DPG_DMIFRC_REPEATER 0 2 REG_DMIFRC_DPG_REPEATER 4 6 mmDMIF_PG2_DPG_CHK_PRE_PROC_CNTL 0 0xa86 1 0 2 DPG_DISABLE_DMIF_BUF_CHK 0 0 mmDMIF_PG2_DPG_DVMM_STATUS 0 0xa87 4 0 2 DPG_DVMM_FORCED_FLIP_TO_UNMAPPED 0 0 DPG_DVMM_FORCED_FLIP_TO_MAPPED 1 1 DPG_DVMM_FORCED_FLIP_TO_UNMAPPED_CLR 4 4 DPG_DVMM_FORCED_FLIP_TO_MAPPED_CLR 5 5 mmSCL2_SCL_COEF_RAM_SELECT 0 0xa9a 3 0 2 SCL_C_RAM_TAP_PAIR_IDX 0 3 SCL_C_RAM_PHASE 8 11 SCL_C_RAM_FILTER_TYPE 16 18 mmSCL2_SCL_COEF_RAM_TAP_DATA 0 0xa9b 4 0 2 SCL_C_RAM_EVEN_TAP_COEF 0 13 SCL_C_RAM_EVEN_TAP_COEF_EN 15 15 SCL_C_RAM_ODD_TAP_COEF 16 29 SCL_C_RAM_ODD_TAP_COEF_EN 31 31 mmSCL2_SCL_MODE 0 0xa9c 2 0 2 SCL_MODE 0 1 SCL_PSCL_EN 4 4 mmSCL2_SCL_TAP_CONTROL 0 0xa9d 2 0 2 SCL_V_NUM_OF_TAPS 0 2 SCL_H_NUM_OF_TAPS 8 11 mmSCL2_SCL_CONTROL 0 0xa9e 2 0 2 SCL_BOUNDARY_MODE 0 0 SCL_EARLY_EOL_MODE 4 4 mmSCL2_SCL_BYPASS_CONTROL 0 0xa9f 1 0 2 SCL_BYPASS_MODE 0 1 mmSCL2_SCL_MANUAL_REPLICATE_CONTROL 0 0xaa0 2 0 2 SCL_V_MANUAL_REPLICATE_FACTOR 0 3 SCL_H_MANUAL_REPLICATE_FACTOR 8 11 mmSCL2_SCL_AUTOMATIC_MODE_CONTROL 0 0xaa1 2 0 2 SCL_V_CALC_AUTO_RATIO_EN 0 0 SCL_H_CALC_AUTO_RATIO_EN 16 16 mmSCL2_SCL_HORZ_FILTER_CONTROL 0 0xaa2 2 0 2 SCL_H_FILTER_PICK_NEAREST 0 0 SCL_H_2TAP_HARDCODE_COEF_EN 8 8 mmSCL2_SCL_HORZ_FILTER_SCALE_RATIO 0 0xaa3 1 0 2 SCL_H_SCALE_RATIO 0 25 mmSCL2_SCL_HORZ_FILTER_INIT 0 0xaa4 2 0 2 SCL_H_INIT_FRAC 0 23 SCL_H_INIT_INT 24 27 mmSCL2_SCL_VERT_FILTER_CONTROL 0 0xaa5 2 0 2 SCL_V_FILTER_PICK_NEAREST 0 0 SCL_V_2TAP_HARDCODE_COEF_EN 8 8 mmSCL2_SCL_VERT_FILTER_SCALE_RATIO 0 0xaa6 1 0 2 SCL_V_SCALE_RATIO 0 25 mmSCL2_SCL_VERT_FILTER_INIT 0 0xaa7 2 0 2 SCL_V_INIT_FRAC 0 23 SCL_V_INIT_INT 24 26 mmSCL2_SCL_VERT_FILTER_INIT_BOT 0 0xaa8 2 0 2 SCL_V_INIT_FRAC_BOT 0 23 SCL_V_INIT_INT_BOT 24 26 mmSCL2_SCL_ROUND_OFFSET 0 0xaa9 2 0 2 SCL_ROUND_OFFSET_RGB_Y 0 15 SCL_ROUND_OFFSET_CBCR 16 31 mmSCL2_SCL_UPDATE 0 0xaaa 4 0 2 SCL_UPDATE_PENDING 0 0 SCL_UPDATE_TAKEN 8 8 SCL_UPDATE_LOCK 16 16 SCL_COEF_UPDATE_COMPLETE 24 24 mmSCL2_SCL_F_SHARP_CONTROL 0 0xaab 4 0 2 SCL_HF_SHARP_SCALE_FACTOR 0 2 SCL_HF_SHARP_EN 4 4 SCL_VF_SHARP_SCALE_FACTOR 8 10 SCL_VF_SHARP_EN 12 12 mmSCL2_SCL_ALU_CONTROL 0 0xaac 1 0 2 SCL_ALU_DISABLE 0 0 mmSCL2_SCL_COEF_RAM_CONFLICT_STATUS 0 0xaad 4 0 2 SCL_HOST_CONFLICT_FLAG 0 0 SCL_HOST_CONFLICT_ACK 8 8 SCL_HOST_CONFLICT_MASK 12 12 SCL_HOST_CONFLICT_INT_STATUS 16 16 mmSCL2_VIEWPORT_START_SECONDARY 0 0xaae 2 0 2 VIEWPORT_Y_START_SECONDARY 0 13 VIEWPORT_X_START_SECONDARY 16 29 mmSCL2_VIEWPORT_START 0 0xaaf 2 0 2 VIEWPORT_Y_START 0 13 VIEWPORT_X_START 16 29 mmSCL2_VIEWPORT_SIZE 0 0xab0 2 0 2 VIEWPORT_HEIGHT 0 13 VIEWPORT_WIDTH 16 29 mmSCL2_EXT_OVERSCAN_LEFT_RIGHT 0 0xab1 2 0 2 EXT_OVERSCAN_RIGHT 0 12 EXT_OVERSCAN_LEFT 16 28 mmSCL2_EXT_OVERSCAN_TOP_BOTTOM 0 0xab2 2 0 2 EXT_OVERSCAN_BOTTOM 0 12 EXT_OVERSCAN_TOP 16 28 mmSCL2_SCL_MODE_CHANGE_DET1 0 0xab3 3 0 2 SCL_MODE_CHANGE 0 0 SCL_MODE_CHANGE_ACK 4 4 SCL_ALU_H_SCALE_RATIO 7 27 mmSCL2_SCL_MODE_CHANGE_DET2 0 0xab4 1 0 2 SCL_ALU_V_SCALE_RATIO 0 20 mmSCL2_SCL_MODE_CHANGE_DET3 0 0xab5 2 0 2 SCL_ALU_SOURCE_HEIGHT 0 13 SCL_ALU_SOURCE_WIDTH 16 29 mmSCL2_SCL_MODE_CHANGE_MASK 0 0xab6 1 0 2 SCL_MODE_CHANGE_MASK 0 0 mmBLND2_BLND_CONTROL 0 0xac7 9 0 2 BLND_GLOBAL_GAIN 0 7 BLND_MODE 8 9 BLND_STEREO_TYPE 10 11 BLND_STEREO_POLARITY 12 12 BLND_FEEDTHROUGH_EN 13 13 BLND_ALPHA_MODE 16 17 BLND_ACTIVE_OVERLAP_ONLY 18 18 BLND_MULTIPLIED_MODE 20 20 BLND_GLOBAL_ALPHA 24 31 mmBLND2_BLND_SM_CONTROL2 0 0xac8 6 0 2 SM_MODE 0 2 SM_FRAME_ALTERNATE 4 4 SM_FIELD_ALTERNATE 5 5 SM_FORCE_NEXT_FRAME_POL 8 9 SM_FORCE_NEXT_TOP_POL 16 17 SM_CURRENT_FRAME_POL 24 24 mmBLND2_BLND_CONTROL2 0 0xac9 5 0 2 PTI_ENABLE 0 0 PTI_NEW_PIXEL_GAP 4 5 BLND_NEW_PIXEL_MODE 6 6 BLND_SUPERAA_DEGAMMA_EN 7 7 BLND_SUPERAA_REGAMMA_EN 8 8 mmBLND2_BLND_UPDATE 0 0xaca 3 0 2 BLND_UPDATE_PENDING 0 0 BLND_UPDATE_TAKEN 8 8 BLND_UPDATE_LOCK 16 16 mmBLND2_BLND_UNDERFLOW_INTERRUPT 0 0xacb 4 0 2 BLND_UNDERFLOW_INT_OCCURED 0 0 BLND_UNDERFLOW_INT_ACK 8 8 BLND_UNDERFLOW_INT_MASK 12 12 BLND_UNDERFLOW_INT_PIPE_INDEX 16 17 mmBLND2_BLND_V_UPDATE_LOCK 0 0xacc 6 0 2 BLND_DCP_GRPH_V_UPDATE_LOCK 0 0 BLND_DCP_GRPH_SURF_V_UPDATE_LOCK 1 1 BLND_DCP_CUR_V_UPDATE_LOCK 16 16 BLND_SCL_V_UPDATE_LOCK 28 28 BLND_BLND_V_UPDATE_LOCK 29 29 BLND_V_UPDATE_LOCK_MODE 31 31 mmBLND2_BLND_REG_UPDATE_STATUS 0 0xacd 10 0 2 DCP_BLNDC_GRPH_UPDATE_PENDING 0 0 DCP_BLNDO_GRPH_UPDATE_PENDING 1 1 DCP_BLNDC_GRPH_SURF_UPDATE_PENDING 2 2 DCP_BLNDO_GRPH_SURF_UPDATE_PENDING 3 3 DCP_BLNDC_CUR_UPDATE_PENDING 6 6 DCP_BLNDO_CUR_UPDATE_PENDING 7 7 SCL_BLNDC_UPDATE_PENDING 8 8 SCL_BLNDO_UPDATE_PENDING 9 9 BLND_BLNDC_UPDATE_PENDING 10 10 BLND_BLNDO_UPDATE_PENDING 11 11 mmCRTC2_CRTC_H_BLANK_EARLY_NUM 0 0xad2 2 0 2 CRTC_H_BLANK_EARLY_NUM 0 9 CRTC_H_BLANK_EARLY_NUM_DIS 16 16 mmCRTC2_CRTC_H_TOTAL 0 0xad3 1 0 2 CRTC_H_TOTAL 0 13 mmCRTC2_CRTC_H_BLANK_START_END 0 0xad4 2 0 2 CRTC_H_BLANK_START 0 13 CRTC_H_BLANK_END 16 29 mmCRTC2_CRTC_H_SYNC_A 0 0xad5 2 0 2 CRTC_H_SYNC_A_START 0 13 CRTC_H_SYNC_A_END 16 29 mmCRTC2_CRTC_H_SYNC_A_CNTL 0 0xad6 3 0 2 CRTC_H_SYNC_A_POL 0 0 CRTC_COMP_SYNC_A_EN 16 16 CRTC_H_SYNC_A_CUTOFF 17 17 mmCRTC2_CRTC_H_SYNC_B 0 0xad7 2 0 2 CRTC_H_SYNC_B_START 0 13 CRTC_H_SYNC_B_END 16 29 mmCRTC2_CRTC_H_SYNC_B_CNTL 0 0xad8 3 0 2 CRTC_H_SYNC_B_POL 0 0 CRTC_COMP_SYNC_B_EN 16 16 CRTC_H_SYNC_B_CUTOFF 17 17 mmCRTC2_CRTC_VBI_END 0 0xad9 2 0 2 CRTC_VBI_V_END 0 13 CRTC_VBI_H_END 16 29 mmCRTC2_CRTC_V_TOTAL 0 0xada 1 0 2 CRTC_V_TOTAL 0 13 mmCRTC2_CRTC_V_TOTAL_MIN 0 0xadb 1 0 2 CRTC_V_TOTAL_MIN 0 13 mmCRTC2_CRTC_V_TOTAL_MAX 0 0xadc 2 0 2 CRTC_V_TOTAL_MAX 0 13 CRTC_ALLOW_VBLANK_EXTENSION_FOR_MC_TRAINING 16 16 mmCRTC2_CRTC_V_TOTAL_CONTROL 0 0xadd 6 0 2 CRTC_V_TOTAL_MIN_SEL 0 0 CRTC_V_TOTAL_MAX_SEL 4 4 CRTC_FORCE_LOCK_ON_EVENT 8 8 CRTC_FORCE_LOCK_TO_MASTER_VSYNC 12 12 CRTC_SET_V_TOTAL_MIN_MASK_EN 15 15 CRTC_SET_V_TOTAL_MIN_MASK 16 31 mmCRTC2_CRTC_V_TOTAL_INT_STATUS 0 0xade 4 0 2 CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED 0 0 CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT 4 4 CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_ACK 8 8 CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_MSK 12 12 mmCRTC2_CRTC_VSYNC_NOM_INT_STATUS 0 0xadf 2 0 2 CRTC_VSYNC_NOM 0 0 CRTC_VSYNC_NOM_INT_CLEAR 4 4 mmCRTC2_CRTC_V_BLANK_START_END 0 0xae0 2 0 2 CRTC_V_BLANK_START 0 13 CRTC_V_BLANK_END 16 29 mmCRTC2_CRTC_V_SYNC_A 0 0xae1 2 0 2 CRTC_V_SYNC_A_START 0 13 CRTC_V_SYNC_A_END 16 29 mmCRTC2_CRTC_V_SYNC_A_CNTL 0 0xae2 1 0 2 CRTC_V_SYNC_A_POL 0 0 mmCRTC2_CRTC_V_SYNC_B 0 0xae3 2 0 2 CRTC_V_SYNC_B_START 0 13 CRTC_V_SYNC_B_END 16 29 mmCRTC2_CRTC_V_SYNC_B_CNTL 0 0xae4 1 0 2 CRTC_V_SYNC_B_POL 0 0 mmCRTC2_CRTC_DTMTEST_CNTL 0 0xae5 2 0 2 CRTC_DTMTEST_CRTC_EN 0 0 CRTC_DTMTEST_CLK_DIV 1 4 mmCRTC2_CRTC_DTMTEST_STATUS_POSITION 0 0xae6 2 0 2 CRTC_DTMTEST_VERT_COUNT 0 13 CRTC_DTMTEST_HORZ_COUNT 16 29 mmCRTC2_CRTC_TRIGA_CNTL 0 0xae7 11 0 2 CRTC_TRIGA_SOURCE_SELECT 0 4 CRTC_TRIGA_POLARITY_SELECT 5 7 CRTC_TRIGA_RESYNC_BYPASS_EN 8 8 CRTC_TRIGA_INPUT_STATUS 9 9 CRTC_TRIGA_POLARITY_STATUS 10 10 CRTC_TRIGA_OCCURRED 11 11 CRTC_TRIGA_RISING_EDGE_DETECT_CNTL 12 13 CRTC_TRIGA_FALLING_EDGE_DETECT_CNTL 16 17 CRTC_TRIGA_FREQUENCY_SELECT 20 21 CRTC_TRIGA_DELAY 24 28 CRTC_TRIGA_CLEAR 31 31 mmCRTC2_CRTC_TRIGA_MANUAL_TRIG 0 0xae8 1 0 2 CRTC_TRIGA_MANUAL_TRIG 0 0 mmCRTC2_CRTC_TRIGB_CNTL 0 0xae9 11 0 2 CRTC_TRIGB_SOURCE_SELECT 0 4 CRTC_TRIGB_POLARITY_SELECT 5 7 CRTC_TRIGB_RESYNC_BYPASS_EN 8 8 CRTC_TRIGB_INPUT_STATUS 9 9 CRTC_TRIGB_POLARITY_STATUS 10 10 CRTC_TRIGB_OCCURRED 11 11 CRTC_TRIGB_RISING_EDGE_DETECT_CNTL 12 13 CRTC_TRIGB_FALLING_EDGE_DETECT_CNTL 16 17 CRTC_TRIGB_FREQUENCY_SELECT 20 21 CRTC_TRIGB_DELAY 24 28 CRTC_TRIGB_CLEAR 31 31 mmCRTC2_CRTC_TRIGB_MANUAL_TRIG 0 0xaea 1 0 2 CRTC_TRIGB_MANUAL_TRIG 0 0 mmCRTC2_CRTC_FORCE_COUNT_NOW_CNTL 0 0xaeb 5 0 2 CRTC_FORCE_COUNT_NOW_MODE 0 1 CRTC_FORCE_COUNT_NOW_CHECK 4 4 CRTC_FORCE_COUNT_NOW_TRIG_SEL 8 8 CRTC_FORCE_COUNT_NOW_OCCURRED 16 16 CRTC_FORCE_COUNT_NOW_CLEAR 24 24 mmCRTC2_CRTC_FLOW_CONTROL 0 0xaec 4 0 2 CRTC_FLOW_CONTROL_SOURCE_SELECT 0 4 CRTC_FLOW_CONTROL_POLARITY 8 8 CRTC_FLOW_CONTROL_GRANULARITY 16 16 CRTC_FLOW_CONTROL_INPUT_STATUS 24 24 mmCRTC2_CRTC_STEREO_FORCE_NEXT_EYE 0 0xaed 3 0 2 CRTC_STEREO_FORCE_NEXT_EYE 0 1 CRTC_AVSYNC_FRAME_COUNTER 8 15 CRTC_AVSYNC_LINE_COUNTER 16 28 mmCRTC2_CRTC_AVSYNC_COUNTER 0 0xaee 1 0 2 CRTC_AVSYNC_COUNTER 0 31 mmCRTC2_CRTC_CONTROL 0 0xaef 11 0 2 CRTC_MASTER_EN 0 0 CRTC_SYNC_RESET_SEL 4 4 CRTC_DISABLE_POINT_CNTL 8 9 CRTC_START_POINT_CNTL 12 12 CRTC_FIELD_NUMBER_CNTL 13 13 CRTC_FIELD_NUMBER_POLARITY 14 14 CRTC_CURRENT_MASTER_EN_STATE 16 16 CRTC_HBLANK_EARLY_CONTROL 20 22 CRTC_SOF_PULL_EN 29 29 CRTC_AVSYNC_LOCK_SNAPSHOT 30 30 CRTC_AVSYNC_VSYNC_N_HSYNC_MODE 31 31 mmCRTC2_CRTC_BLANK_CONTROL 0 0xaf0 3 0 2 CRTC_CURRENT_BLANK_STATE 0 0 CRTC_BLANK_DATA_EN 8 8 CRTC_BLANK_DE_MODE 16 16 mmCRTC2_CRTC_INTERLACE_CONTROL 0 0xaf1 2 0 2 CRTC_INTERLACE_ENABLE 0 0 CRTC_INTERLACE_FORCE_NEXT_FIELD 16 17 mmCRTC2_CRTC_INTERLACE_STATUS 0 0xaf2 2 0 2 CRTC_INTERLACE_CURRENT_FIELD 0 0 CRTC_INTERLACE_NEXT_FIELD 1 1 mmCRTC2_CRTC_FIELD_INDICATION_CONTROL 0 0xaf3 2 0 2 CRTC_FIELD_INDICATION_OUTPUT_POLARITY 0 0 CRTC_FIELD_ALIGNMENT 1 1 mmCRTC2_CRTC_PIXEL_DATA_READBACK0 0 0xaf4 2 0 2 CRTC_PIXEL_DATA_BLUE_CB 0 11 CRTC_PIXEL_DATA_GREEN_Y 16 27 mmCRTC2_CRTC_PIXEL_DATA_READBACK1 0 0xaf5 1 0 2 CRTC_PIXEL_DATA_RED_CR 0 11 mmCRTC2_CRTC_STATUS 0 0xaf6 9 0 2 CRTC_V_BLANK 0 0 CRTC_V_ACTIVE_DISP 1 1 CRTC_V_SYNC_A 2 2 CRTC_V_UPDATE 3 3 CRTC_V_START_LINE 4 4 CRTC_V_BLANK_3D_STRUCTURE 5 5 CRTC_H_BLANK 16 16 CRTC_H_ACTIVE_DISP 17 17 CRTC_H_SYNC_A 18 18 mmCRTC2_CRTC_STATUS_POSITION 0 0xaf7 2 0 2 CRTC_VERT_COUNT 0 13 CRTC_HORZ_COUNT 16 29 mmCRTC2_CRTC_NOM_VERT_POSITION 0 0xaf8 1 0 2 CRTC_VERT_COUNT_NOM 0 13 mmCRTC2_CRTC_STATUS_FRAME_COUNT 0 0xaf9 1 0 2 CRTC_FRAME_COUNT 0 23 mmCRTC2_CRTC_STATUS_VF_COUNT 0 0xafa 1 0 2 CRTC_VF_COUNT 0 29 mmCRTC2_CRTC_STATUS_HV_COUNT 0 0xafb 1 0 2 CRTC_HV_COUNT 0 29 mmCRTC2_CRTC_COUNT_CONTROL 0 0xafc 2 0 2 CRTC_HORZ_COUNT_BY2_EN 0 0 CRTC_HORZ_REPETITION_COUNT 1 4 mmCRTC2_CRTC_COUNT_RESET 0 0xafd 1 0 2 CRTC_RESET_FRAME_COUNT 0 0 mmCRTC2_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE 0 0xafe 1 0 2 CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE 0 0 mmCRTC2_CRTC_VERT_SYNC_CONTROL 0 0xaff 3 0 2 CRTC_FORCE_VSYNC_NEXT_LINE_OCCURRED 0 0 CRTC_FORCE_VSYNC_NEXT_LINE_CLEAR 8 8 CRTC_AUTO_FORCE_VSYNC_MODE 16 17 mmCRTC2_CRTC_STEREO_STATUS 0 0xb00 5 0 2 CRTC_STEREO_CURRENT_EYE 0 0 CRTC_STEREO_SYNC_OUTPUT 8 8 CRTC_STEREO_SYNC_SELECT 16 16 CRTC_STEREO_EYE_FLAG 20 20 CRTC_STEREO_FORCE_NEXT_EYE_PENDING 24 25 mmCRTC2_CRTC_STEREO_CONTROL 0 0xb01 8 0 2 CRTC_STEREO_SYNC_OUTPUT_LINE_NUM 0 13 CRTC_STEREO_SYNC_OUTPUT_POLARITY 15 15 CRTC_STEREO_SYNC_SELECT_POLARITY 16 16 CRTC_STEREO_EYE_FLAG_POLARITY 17 17 CRTC_DISABLE_STEREOSYNC_OUTPUT_FOR_DP 18 18 CRTC_DISABLE_FIELD_NUM 19 19 CRTC_DISABLE_V_BLANK_FOR_DP_FIX 20 20 CRTC_STEREO_EN 24 24 mmCRTC2_CRTC_SNAPSHOT_STATUS 0 0xb02 3 0 2 CRTC_SNAPSHOT_OCCURRED 0 0 CRTC_SNAPSHOT_CLEAR 1 1 CRTC_SNAPSHOT_MANUAL_TRIGGER 2 2 mmCRTC2_CRTC_SNAPSHOT_CONTROL 0 0xb03 1 0 2 CRTC_AUTO_SNAPSHOT_TRIG_SEL 0 1 mmCRTC2_CRTC_SNAPSHOT_POSITION 0 0xb04 2 0 2 CRTC_SNAPSHOT_VERT_COUNT 0 13 CRTC_SNAPSHOT_HORZ_COUNT 16 29 mmCRTC2_CRTC_SNAPSHOT_FRAME 0 0xb05 1 0 2 CRTC_SNAPSHOT_FRAME_COUNT 0 23 mmCRTC2_CRTC_START_LINE_CONTROL 0 0xb06 5 0 2 CRTC_PROGRESSIVE_START_LINE_EARLY 0 0 CRTC_INTERLACE_START_LINE_EARLY 1 1 CRTC_PREFETCH_EN 2 2 CRTC_LEGACY_REQUESTOR_EN 8 8 CRTC_ADVANCED_START_LINE_POSITION 12 19 mmCRTC2_CRTC_INTERRUPT_CONTROL 0 0xb07 16 0 2 CRTC_SNAPSHOT_INT_MSK 0 0 CRTC_SNAPSHOT_INT_TYPE 1 1 CRTC_V_UPDATE_INT_MSK 4 4 CRTC_V_UPDATE_INT_TYPE 5 5 CRTC_FORCE_COUNT_NOW_INT_MSK 8 8 CRTC_FORCE_COUNT_NOW_INT_TYPE 9 9 CRTC_FORCE_VSYNC_NEXT_LINE_INT_MSK 16 16 CRTC_FORCE_VSYNC_NEXT_LINE_INT_TYPE 17 17 CRTC_TRIGA_INT_MSK 24 24 CRTC_TRIGB_INT_MSK 25 25 CRTC_TRIGA_INT_TYPE 26 26 CRTC_TRIGB_INT_TYPE 27 27 CRTC_VSYNC_NOM_INT_MSK 28 28 CRTC_VSYNC_NOM_INT_TYPE 29 29 CRTC_GSL_VSYNC_GAP_INT_MSK 30 30 CRTC_GSL_VSYNC_GAP_INT_TYPE 31 31 mmCRTC2_CRTC_UPDATE_LOCK 0 0xb08 1 0 2 CRTC_UPDATE_LOCK 0 0 mmCRTC2_CRTC_DOUBLE_BUFFER_CONTROL 0 0xb09 5 0 2 CRTC_UPDATE_PENDING 0 0 CRTC_UPDATE_INSTANTLY 8 8 CRTC_BLANK_DATA_DOUBLE_BUFFER_EN 16 16 CRTC_RANGE_TIMING_DBUF_UPDATE_MODE 24 24 CRTC_RANGE_TIMING_DBUF_UPDATE_PENDING 25 25 mmCRTC2_CRTC_VGA_PARAMETER_CAPTURE_MODE 0 0xb0a 1 0 2 CRTC_VGA_PARAMETER_CAPTURE_MODE 0 0 mmCRTC2_CRTC_TEST_PATTERN_CONTROL 0 0xb0b 4 0 2 CRTC_TEST_PATTERN_EN 0 0 CRTC_TEST_PATTERN_MODE 8 10 CRTC_TEST_PATTERN_DYNAMIC_RANGE 16 16 CRTC_TEST_PATTERN_COLOR_FORMAT 24 31 mmCRTC2_CRTC_TEST_PATTERN_PARAMETERS 0 0xb0c 5 0 2 CRTC_TEST_PATTERN_INC0 0 3 CRTC_TEST_PATTERN_INC1 4 7 CRTC_TEST_PATTERN_VRES 8 11 CRTC_TEST_PATTERN_HRES 12 15 CRTC_TEST_PATTERN_RAMP0_OFFSET 16 31 mmCRTC2_CRTC_TEST_PATTERN_COLOR 0 0xb0d 2 0 2 CRTC_TEST_PATTERN_DATA 0 15 CRTC_TEST_PATTERN_MASK 16 21 mmCRTC2_CRTC_MASTER_UPDATE_LOCK 0 0xb0e 3 0 2 MASTER_UPDATE_LOCK 0 0 GSL_CONTROL_MASTER_UPDATE_LOCK 8 8 UNDERFLOW_UPDATE_LOCK 16 16 mmCRTC2_CRTC_MASTER_UPDATE_MODE 0 0xb0f 2 0 2 MASTER_UPDATE_MODE 0 2 MASTER_UPDATE_INTERLACED_MODE 16 17 mmCRTC2_CRTC_MVP_INBAND_CNTL_INSERT 0 0xb10 2 0 2 CRTC_MVP_INBAND_OUT_MODE 0 1 CRTC_MVP_INBAND_CNTL_CHAR_INSERT 8 31 mmCRTC2_CRTC_MVP_INBAND_CNTL_INSERT_TIMER 0 0xb11 1 0 2 CRTC_MVP_INBAND_CNTL_CHAR_INSERT_TIMER 0 7 mmCRTC2_CRTC_MVP_STATUS 0 0xb12 4 0 2 CRTC_FLIP_NOW_OCCURRED 0 0 CRTC_AFR_HSYNC_SWITCH_DONE_OCCURRED 4 4 CRTC_FLIP_NOW_CLEAR 16 16 CRTC_AFR_HSYNC_SWITCH_DONE_CLEAR 20 20 mmCRTC2_CRTC_MASTER_EN 0 0xb13 1 0 2 CRTC_MASTER_EN 0 0 mmCRTC2_CRTC_ALLOW_STOP_OFF_V_CNT 0 0xb14 2 0 2 CRTC_ALLOW_STOP_OFF_V_CNT 0 7 CRTC_DISABLE_ALLOW_STOP_OFF_V_CNT 16 16 mmCRTC2_CRTC_V_UPDATE_INT_STATUS 0 0xb15 2 0 2 CRTC_V_UPDATE_INT_OCCURRED 0 0 CRTC_V_UPDATE_INT_CLEAR 8 8 mmCRTC2_CRTC_OVERSCAN_COLOR 0 0xb17 3 0 2 CRTC_OVERSCAN_COLOR_BLUE 0 9 CRTC_OVERSCAN_COLOR_GREEN 10 19 CRTC_OVERSCAN_COLOR_RED 20 29 mmCRTC2_CRTC_OVERSCAN_COLOR_EXT 0 0xb18 3 0 2 CRTC_OVERSCAN_COLOR_BLUE_EXT 0 1 CRTC_OVERSCAN_COLOR_GREEN_EXT 8 9 CRTC_OVERSCAN_COLOR_RED_EXT 16 17 mmCRTC2_CRTC_BLANK_DATA_COLOR 0 0xb19 3 0 2 CRTC_BLANK_DATA_COLOR_BLUE_CB 0 9 CRTC_BLANK_DATA_COLOR_GREEN_Y 10 19 CRTC_BLANK_DATA_COLOR_RED_CR 20 29 mmCRTC2_CRTC_BLANK_DATA_COLOR_EXT 0 0xb1a 3 0 2 CRTC_BLANK_DATA_COLOR_BLUE_CB_EXT 0 1 CRTC_BLANK_DATA_COLOR_GREEN_Y_EXT 8 9 CRTC_BLANK_DATA_COLOR_RED_CR_EXT 16 17 mmCRTC2_CRTC_BLACK_COLOR 0 0xb1b 3 0 2 CRTC_BLACK_COLOR_B_CB 0 9 CRTC_BLACK_COLOR_G_Y 10 19 CRTC_BLACK_COLOR_R_CR 20 29 mmCRTC2_CRTC_BLACK_COLOR_EXT 0 0xb1c 3 0 2 CRTC_BLACK_COLOR_B_CB_EXT 0 1 CRTC_BLACK_COLOR_G_Y_EXT 8 9 CRTC_BLACK_COLOR_R_CR_EXT 16 17 mmCRTC2_CRTC_VERTICAL_INTERRUPT0_POSITION 0 0xb1d 2 0 2 CRTC_VERTICAL_INTERRUPT0_LINE_START 0 13 CRTC_VERTICAL_INTERRUPT0_LINE_END 16 29 mmCRTC2_CRTC_VERTICAL_INTERRUPT0_CONTROL 0 0xb1e 6 0 2 CRTC_VERTICAL_INTERRUPT0_OUTPUT_POLARITY 4 4 CRTC_VERTICAL_INTERRUPT0_INT_ENABLE 8 8 CRTC_VERTICAL_INTERRUPT0_STATUS 12 12 CRTC_VERTICAL_INTERRUPT0_INT_STATUS 16 16 CRTC_VERTICAL_INTERRUPT0_CLEAR 20 20 CRTC_VERTICAL_INTERRUPT0_INT_TYPE 24 24 mmCRTC2_CRTC_VERTICAL_INTERRUPT1_POSITION 0 0xb1f 1 0 2 CRTC_VERTICAL_INTERRUPT1_LINE_START 0 13 mmCRTC2_CRTC_VERTICAL_INTERRUPT1_CONTROL 0 0xb20 5 0 2 CRTC_VERTICAL_INTERRUPT1_INT_ENABLE 8 8 CRTC_VERTICAL_INTERRUPT1_STATUS 12 12 CRTC_VERTICAL_INTERRUPT1_INT_STATUS 16 16 CRTC_VERTICAL_INTERRUPT1_CLEAR 20 20 CRTC_VERTICAL_INTERRUPT1_INT_TYPE 24 24 mmCRTC2_CRTC_VERTICAL_INTERRUPT2_POSITION 0 0xb21 1 0 2 CRTC_VERTICAL_INTERRUPT2_LINE_START 0 13 mmCRTC2_CRTC_VERTICAL_INTERRUPT2_CONTROL 0 0xb22 5 0 2 CRTC_VERTICAL_INTERRUPT2_INT_ENABLE 8 8 CRTC_VERTICAL_INTERRUPT2_STATUS 12 12 CRTC_VERTICAL_INTERRUPT2_INT_STATUS 16 16 CRTC_VERTICAL_INTERRUPT2_CLEAR 20 20 CRTC_VERTICAL_INTERRUPT2_INT_TYPE 24 24 mmCRTC2_CRTC_CRC_CNTL 0 0xb23 7 0 2 CRTC_CRC_EN 0 0 CRTC_CRC_CONT_EN 4 4 CRTC_CRC_STEREO_MODE 8 9 CRTC_CRC_INTERLACE_MODE 12 13 CRTC_CRC_USE_NEW_AND_REPEATED_PIXELS 16 16 CRTC_CRC0_SELECT 20 22 CRTC_CRC1_SELECT 24 26 mmCRTC2_CRTC_CRC0_WINDOWA_X_CONTROL 0 0xb24 2 0 2 CRTC_CRC0_WINDOWA_X_START 0 13 CRTC_CRC0_WINDOWA_X_END 16 29 mmCRTC2_CRTC_CRC0_WINDOWA_Y_CONTROL 0 0xb25 2 0 2 CRTC_CRC0_WINDOWA_Y_START 0 13 CRTC_CRC0_WINDOWA_Y_END 16 29 mmCRTC2_CRTC_CRC0_WINDOWB_X_CONTROL 0 0xb26 2 0 2 CRTC_CRC0_WINDOWB_X_START 0 13 CRTC_CRC0_WINDOWB_X_END 16 29 mmCRTC2_CRTC_CRC0_WINDOWB_Y_CONTROL 0 0xb27 2 0 2 CRTC_CRC0_WINDOWB_Y_START 0 13 CRTC_CRC0_WINDOWB_Y_END 16 29 mmCRTC2_CRTC_CRC0_DATA_RG 0 0xb28 2 0 2 CRC0_R_CR 0 15 CRC0_G_Y 16 31 mmCRTC2_CRTC_CRC0_DATA_B 0 0xb29 1 0 2 CRC0_B_CB 0 15 mmCRTC2_CRTC_CRC1_WINDOWA_X_CONTROL 0 0xb2a 2 0 2 CRTC_CRC1_WINDOWA_X_START 0 13 CRTC_CRC1_WINDOWA_X_END 16 29 mmCRTC2_CRTC_CRC1_WINDOWA_Y_CONTROL 0 0xb2b 2 0 2 CRTC_CRC1_WINDOWA_Y_START 0 13 CRTC_CRC1_WINDOWA_Y_END 16 29 mmCRTC2_CRTC_CRC1_WINDOWB_X_CONTROL 0 0xb2c 2 0 2 CRTC_CRC1_WINDOWB_X_START 0 13 CRTC_CRC1_WINDOWB_X_END 16 29 mmCRTC2_CRTC_CRC1_WINDOWB_Y_CONTROL 0 0xb2d 2 0 2 CRTC_CRC1_WINDOWB_Y_START 0 13 CRTC_CRC1_WINDOWB_Y_END 16 29 mmCRTC2_CRTC_CRC1_DATA_RG 0 0xb2e 2 0 2 CRC1_R_CR 0 15 CRC1_G_Y 16 31 mmCRTC2_CRTC_CRC1_DATA_B 0 0xb2f 1 0 2 CRC1_B_CB 0 15 mmCRTC2_CRTC_EXT_TIMING_SYNC_CONTROL 0 0xb30 11 0 2 CRTC_EXT_TIMING_SYNC_ENABLE 0 1 CRTC_EXT_TIMING_SYNC_HCOUNT_MODE_ENABLE 3 3 CRTC_EXT_TIMING_SYNC_JITTER_FILTERING_ENABLE 4 4 CRTC_EXT_TIMING_SYNC_JITTER_FILTERING_WINDOW 5 6 CRTC_EXT_TIMING_SYNC_WINDOW_ENABLE 8 8 CRTC_EXT_TIMING_SYNC_WINDOW_UPDATE 9 9 CRTC_EXT_TIMING_SYNC_VSYNC_POLARITY 12 12 CRTC_EXT_TIMING_SYNC_HSYNC_POLARITY 13 13 CRTC_EXT_TIMING_SYNC_INTERLACE_MODE 14 14 CRTC_EXT_TIMING_SYNC_MASTER_FRAME_RATE 24 26 CRTC_EXT_TIMING_SYNC_SLAVE_FRAME_RATE 28 30 mmCRTC2_CRTC_EXT_TIMING_SYNC_WINDOW_START 0 0xb31 2 0 2 CRTC_EXT_TIMING_SYNC_WINDOW_START_X 0 13 CRTC_EXT_TIMING_SYNC_WINDOW_START_Y 16 29 mmCRTC2_CRTC_EXT_TIMING_SYNC_WINDOW_END 0 0xb32 2 0 2 CRTC_EXT_TIMING_SYNC_WINDOW_END_X 0 13 CRTC_EXT_TIMING_SYNC_WINDOW_END_Y 16 29 mmCRTC2_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL 0 0xb33 6 0 2 CRTC_EXT_TIMING_SYNC_LOSS_INT_ENABLE 0 0 CRTC_EXT_TIMING_SYNC_LOSS_STATUS 4 4 CRTC_EXT_TIMING_SYNC_LOSS_INT_STATUS 8 8 CRTC_EXT_TIMING_SYNC_LOSS_CLEAR 16 16 CRTC_EXT_TIMING_SYNC_LOSS_INT_TYPE 20 20 CRTC_EXT_TIMING_SYNC_LOSS_FRAME_COUNT 29 31 mmCRTC2_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL 0 0xb34 5 0 2 CRTC_EXT_TIMING_SYNC_INT_ENABLE 0 0 CRTC_EXT_TIMING_SYNC_STATUS 4 4 CRTC_EXT_TIMING_SYNC_INT_STATUS 8 8 CRTC_EXT_TIMING_SYNC_CLEAR 16 16 CRTC_EXT_TIMING_SYNC_INT_TYPE 20 20 mmCRTC2_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL 0 0xb35 5 0 2 CRTC_EXT_TIMING_SYNC_SIGNAL_INT_ENABLE 0 0 CRTC_EXT_TIMING_SYNC_SIGNAL_STATUS 4 4 CRTC_EXT_TIMING_SYNC_SIGNAL_INT_STATUS 8 8 CRTC_EXT_TIMING_SYNC_SIGNAL_CLEAR 16 16 CRTC_EXT_TIMING_SYNC_SIGNAL_INT_TYPE 20 20 mmCRTC2_CRTC_STATIC_SCREEN_CONTROL 0 0xb36 9 0 2 CRTC_STATIC_SCREEN_EVENT_MASK 0 15 CRTC_STATIC_SCREEN_FRAME_COUNT 16 23 CRTC_CPU_SS_INT_ENABLE 24 24 CRTC_SS_STATUS 25 25 CRTC_CPU_SS_INT_STATUS 26 26 CRTC_CPU_SS_INT_CLEAR 27 27 CRTC_CPU_SS_INT_TYPE 28 28 CRTC_STATIC_SCREEN_OVERRIDE 30 30 CRTC_STATIC_SCREEN_OVERRIDE_VALUE 31 31 mmCRTC2_CRTC_3D_STRUCTURE_CONTROL 0 0xb37 7 0 2 CRTC_3D_STRUCTURE_EN 0 0 CRTC_3D_STRUCTURE_EN_DB 4 4 CRTC_3D_STRUCTURE_V_UPDATE_MODE 8 9 CRTC_3D_STRUCTURE_STEREO_SEL_OVR 12 12 CRTC_3D_STRUCTURE_F_COUNT_RESET 16 16 CRTC_3D_STRUCTURE_F_COUNT_RESET_PENDING 17 17 CRTC_3D_STRUCTURE_F_COUNT 18 19 mmCRTC2_CRTC_GSL_VSYNC_GAP 0 0xb38 8 0 2 CRTC_GSL_VSYNC_GAP_LIMIT 0 7 CRTC_GSL_VSYNC_GAP_DELAY 8 15 CRTC_GSL_VSYNC_GAP_SOURCE_SEL 16 16 CRTC_GSL_VSYNC_GAP_MODE 17 18 CRTC_GSL_VSYNC_GAP_CLEAR 19 19 CRTC_GSL_VSYNC_GAP_OCCURRED 20 20 CRTC_GSL_VSYNC_GAP_MASTER_FASTER 23 23 CRTC_GSL_VSYNC_GAP 24 31 mmCRTC2_CRTC_GSL_WINDOW 0 0xb39 2 0 2 CRTC_GSL_WINDOW_START 0 13 CRTC_GSL_WINDOW_END 16 29 mmCRTC2_CRTC_GSL_CONTROL 0 0xb3a 3 0 2 CRTC_GSL_CHECK_LINE_NUM 0 13 CRTC_GSL_FORCE_DELAY 16 20 CRTC_GSL_CHECK_ALL_FIELDS 28 28 mmCRTC2_CRTC_RANGE_TIMING_INT_STATUS 0 0xb3d 5 0 2 CRTC_RANGE_TIMING_UPDATE_OCCURRED 0 0 CRTC_RANGE_TIMING_UPDATE_OCCURRED_INT 4 4 CRTC_RANGE_TIMING_UPDATE_OCCURRED_CLEAR 8 8 CRTC_RANGE_TIMING_UPDATE_OCCURRED_INT_MSK 12 12 CRTC_RANGE_TIMING_UPDATE_OCCURRED_INT_TYPE 16 16 mmCRTC2_CRTC_DRR_CONTROL 0 0xb3e 4 0 2 CRTC_XDMA_PREFETCH_DELAY 0 13 CRTC_V_TOTAL_LAST_USED_BY_DRR 14 27 CRTC_SET_V_TOTAL_MIN_AUTO_DIS 28 28 CRTC_DRR_MODE_DBUF_UPDATE_MODE 29 30 mmFMT2_FMT_CLAMP_COMPONENT_R 0 0xb42 2 0 2 FMT_CLAMP_LOWER_R 0 15 FMT_CLAMP_UPPER_R 16 31 mmFMT2_FMT_CLAMP_COMPONENT_G 0 0xb43 2 0 2 FMT_CLAMP_LOWER_G 0 15 FMT_CLAMP_UPPER_G 16 31 mmFMT2_FMT_CLAMP_COMPONENT_B 0 0xb44 2 0 2 FMT_CLAMP_LOWER_B 0 15 FMT_CLAMP_UPPER_B 16 31 mmFMT2_FMT_DYNAMIC_EXP_CNTL 0 0xb45 2 0 2 FMT_DYNAMIC_EXP_EN 0 0 FMT_DYNAMIC_EXP_MODE 4 4 mmFMT2_FMT_CONTROL 0 0xb46 11 0 2 FMT_STEREOSYNC_OVERRIDE 0 0 FMT_STEREOSYNC_OVR_POL 4 4 FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX 8 11 FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP 12 13 FMT_PIXEL_ENCODING 16 17 FMT_SUBSAMPLING_MODE 18 19 FMT_SUBSAMPLING_ORDER 20 20 FMT_CBCR_BIT_REDUCTION_BYPASS 21 21 FMT_SRC_SELECT 24 26 FMT_420_PIXEL_PHASE_LOCKED 30 30 FMT_420_PIXEL_PHASE_LOCKED_CLEAR 31 31 mmFMT2_FMT_BIT_DEPTH_CONTROL 0 0xb47 17 0 2 FMT_TRUNCATE_EN 0 0 FMT_TRUNCATE_MODE 1 1 FMT_TRUNCATE_DEPTH 4 5 FMT_SPATIAL_DITHER_EN 8 8 FMT_SPATIAL_DITHER_MODE 9 10 FMT_SPATIAL_DITHER_DEPTH 11 12 FMT_FRAME_RANDOM_ENABLE 13 13 FMT_RGB_RANDOM_ENABLE 14 14 FMT_HIGHPASS_RANDOM_ENABLE 15 15 FMT_TEMPORAL_DITHER_EN 16 16 FMT_TEMPORAL_DITHER_DEPTH 17 18 FMT_TEMPORAL_DITHER_OFFSET 21 22 FMT_TEMPORAL_LEVEL 24 24 FMT_TEMPORAL_DITHER_RESET 25 25 FMT_25FRC_SEL 26 27 FMT_50FRC_SEL 28 29 FMT_75FRC_SEL 30 31 mmFMT2_FMT_DITHER_RAND_R_SEED 0 0xb48 2 0 2 FMT_RAND_R_SEED 0 7 FMT_OFFSET_R_CR 16 31 mmFMT2_FMT_DITHER_RAND_G_SEED 0 0xb49 2 0 2 FMT_RAND_G_SEED 0 7 FMT_OFFSET_G_Y 16 31 mmFMT2_FMT_DITHER_RAND_B_SEED 0 0xb4a 2 0 2 FMT_RAND_B_SEED 0 7 FMT_OFFSET_B_CB 16 31 mmFMT2_FMT_CLAMP_CNTL 0 0xb4e 2 0 2 FMT_CLAMP_DATA_EN 0 0 FMT_CLAMP_COLOR_FORMAT 16 18 mmFMT2_FMT_CRC_CNTL 0 0xb4f 11 0 2 FMT_CRC_EN 0 0 FMT_DTMTEST_CRC_EN 1 1 FMT_CRC_CONT_EN 4 4 FMT_ONE_SHOT_CRC_PENDING 5 5 FMT_CRC_INCLUDE_OVERSCAN 6 6 FMT_CRC_ONLY_BLANKB 8 8 FMT_CRC_PSR_MODE_ENABLE 9 9 FMT_CRC_INTERLACE_MODE 12 13 FMT_CRC_USE_NEW_AND_REPEATED_PIXELS 16 16 FMT_CRC_EVEN_ODD_PIX_ENABLE 20 20 FMT_CRC_EVEN_ODD_PIX_SELECT 24 24 mmFMT2_FMT_CRC_SIG_RED_GREEN_MASK 0 0xb50 2 0 2 FMT_CRC_SIG_RED_MASK 0 15 FMT_CRC_SIG_GREEN_MASK 16 31 mmFMT2_FMT_CRC_SIG_BLUE_CONTROL_MASK 0 0xb51 2 0 2 FMT_CRC_SIG_BLUE_MASK 0 15 FMT_CRC_SIG_CONTROL_MASK 16 31 mmFMT2_FMT_CRC_SIG_RED_GREEN 0 0xb52 2 0 2 FMT_CRC_SIG_RED 0 15 FMT_CRC_SIG_GREEN 16 31 mmFMT2_FMT_CRC_SIG_BLUE_CONTROL 0 0xb53 2 0 2 FMT_CRC_SIG_BLUE 0 15 FMT_CRC_SIG_CONTROL 16 31 mmFMT2_FMT_SIDE_BY_SIDE_STEREO_CONTROL 0 0xb54 1 0 2 FMT_SIDE_BY_SIDE_STEREO_ACTIVE_WIDTH 0 12 mmFMT2_FMT_420_HBLANK_EARLY_START 0 0xb55 1 0 2 FMT_420_HBLANK_EARLY_START 0 11 mmDCP3_GRPH_ENABLE 0 0xb5a 2 0 2 GRPH_ENABLE 0 0 GRPH_KEYER_ALPHA_SEL 1 1 mmDCP3_GRPH_CONTROL 0 0xb5b 12 0 2 GRPH_DEPTH 0 1 GRPH_SE_ENABLE 2 2 GRPH_Z 4 5 GRPH_DIM_TYPE 6 7 GRPH_FORMAT 8 10 GRPH_NUM_BANKS 12 14 GRPH_ADDRESS_TRANSLATION_ENABLE 16 16 GRPH_PRIVILEGED_ACCESS_ENABLE 17 17 GRPH_NUM_SHADER_ENGINES 18 19 GRPH_SW_MODE 20 24 GRPH_NUM_PIPES 28 30 GRPH_COLOR_EXPANSION_MODE 31 31 mmDCP3_GRPH_LUT_10BIT_BYPASS 0 0xb5c 2 0 2 GRPH_LUT_10BIT_BYPASS_EN 8 8 GRPH_LUT_10BIT_BYPASS_DBL_BUF_EN 16 16 mmDCP3_GRPH_SWAP_CNTL 0 0xb5d 5 0 2 GRPH_ENDIAN_SWAP 0 1 GRPH_RED_CROSSBAR 4 5 GRPH_GREEN_CROSSBAR 6 7 GRPH_BLUE_CROSSBAR 8 9 GRPH_ALPHA_CROSSBAR 10 11 mmDCP3_GRPH_PRIMARY_SURFACE_ADDRESS 0 0xb5e 2 0 2 GRPH_PRIMARY_DFQ_ENABLE 0 0 GRPH_PRIMARY_SURFACE_ADDRESS 8 31 mmDCP3_GRPH_SECONDARY_SURFACE_ADDRESS 0 0xb5f 2 0 2 GRPH_SECONDARY_DFQ_ENABLE 0 0 GRPH_SECONDARY_SURFACE_ADDRESS 8 31 mmDCP3_GRPH_PITCH 0 0xb60 1 0 2 GRPH_PITCH 0 14 mmDCP3_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH 0 0xb61 1 0 2 GRPH_PRIMARY_SURFACE_ADDRESS_HIGH 0 7 mmDCP3_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH 0 0xb62 1 0 2 GRPH_SECONDARY_SURFACE_ADDRESS_HIGH 0 7 mmDCP3_GRPH_SURFACE_OFFSET_X 0 0xb63 1 0 2 GRPH_SURFACE_OFFSET_X 0 13 mmDCP3_GRPH_SURFACE_OFFSET_Y 0 0xb64 1 0 2 GRPH_SURFACE_OFFSET_Y 0 13 mmDCP3_GRPH_X_START 0 0xb65 1 0 2 GRPH_X_START 0 13 mmDCP3_GRPH_Y_START 0 0xb66 1 0 2 GRPH_Y_START 0 13 mmDCP3_GRPH_X_END 0 0xb67 1 0 2 GRPH_X_END 0 14 mmDCP3_GRPH_Y_END 0 0xb68 1 0 2 GRPH_Y_END 0 14 mmDCP3_INPUT_GAMMA_CONTROL 0 0xb69 1 0 2 GRPH_INPUT_GAMMA_MODE 0 0 mmDCP3_GRPH_UPDATE 0 0xb6a 11 0 2 GRPH_MODE_UPDATE_PENDING 0 0 GRPH_MODE_UPDATE_TAKEN 1 1 GRPH_SURFACE_UPDATE_PENDING 2 2 GRPH_SURFACE_UPDATE_TAKEN 3 3 GRPH_XDMA_FLIP_TYPE_CLEAR 8 8 GRPH_XDMA_DRR_MODE_ENABLE 9 9 GRPH_XDMA_MULTIFLIP_ENABLE 10 10 GRPH_UPDATE_LOCK 16 16 GRPH_SURFACE_IGNORE_UPDATE_LOCK 20 20 GRPH_MODE_DISABLE_MULTIPLE_UPDATE 24 24 GRPH_SURFACE_DISABLE_MULTIPLE_UPDATE 28 28 mmDCP3_GRPH_FLIP_CONTROL 0 0xb6b 4 0 2 GRPH_SURFACE_UPDATE_H_RETRACE_EN 0 0 GRPH_XDMA_SUPER_AA_EN 1 1 GRPH_SURFACE_UPDATE_IMMEDIATE_EN 4 4 GRPH_SURFACE_UPDATE_PENDING_MODE 5 5 mmDCP3_GRPH_SURFACE_ADDRESS_INUSE 0 0xb6c 1 0 2 GRPH_SURFACE_ADDRESS_INUSE 8 31 mmDCP3_GRPH_DFQ_CONTROL 0 0xb6d 3 0 2 GRPH_DFQ_RESET 0 0 GRPH_DFQ_SIZE 4 6 GRPH_DFQ_MIN_FREE_ENTRIES 8 10 mmDCP3_GRPH_DFQ_STATUS 0 0xb6e 4 0 2 GRPH_PRIMARY_DFQ_NUM_ENTRIES 0 3 GRPH_SECONDARY_DFQ_NUM_ENTRIES 4 7 GRPH_DFQ_RESET_FLAG 8 8 GRPH_DFQ_RESET_ACK 9 9 mmDCP3_GRPH_INTERRUPT_STATUS 0 0xb6f 2 0 2 GRPH_PFLIP_INT_OCCURRED 0 0 GRPH_PFLIP_INT_CLEAR 8 8 mmDCP3_GRPH_INTERRUPT_CONTROL 0 0xb70 2 0 2 GRPH_PFLIP_INT_MASK 0 0 GRPH_PFLIP_INT_TYPE 8 8 mmDCP3_GRPH_SURFACE_ADDRESS_HIGH_INUSE 0 0xb71 1 0 2 GRPH_SURFACE_ADDRESS_HIGH_INUSE 0 7 mmDCP3_GRPH_COMPRESS_SURFACE_ADDRESS 0 0xb72 1 0 2 GRPH_COMPRESS_SURFACE_ADDRESS 8 31 mmDCP3_GRPH_COMPRESS_PITCH 0 0xb73 1 0 2 GRPH_COMPRESS_PITCH 6 16 mmDCP3_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH 0 0xb74 1 0 2 GRPH_COMPRESS_SURFACE_ADDRESS_HIGH 0 7 mmDCP3_GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT 0 0xb75 1 0 2 GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT 0 7 mmDCP3_PRESCALE_GRPH_CONTROL 0 0xb76 5 0 2 GRPH_PRESCALE_SELECT 0 0 GRPH_PRESCALE_R_SIGN 1 1 GRPH_PRESCALE_G_SIGN 2 2 GRPH_PRESCALE_B_SIGN 3 3 GRPH_PRESCALE_BYPASS 4 4 mmDCP3_PRESCALE_VALUES_GRPH_R 0 0xb77 2 0 2 GRPH_PRESCALE_BIAS_R 0 15 GRPH_PRESCALE_SCALE_R 16 31 mmDCP3_PRESCALE_VALUES_GRPH_G 0 0xb78 2 0 2 GRPH_PRESCALE_BIAS_G 0 15 GRPH_PRESCALE_SCALE_G 16 31 mmDCP3_PRESCALE_VALUES_GRPH_B 0 0xb79 2 0 2 GRPH_PRESCALE_BIAS_B 0 15 GRPH_PRESCALE_SCALE_B 16 31 mmDCP3_INPUT_CSC_CONTROL 0 0xb7a 1 0 2 INPUT_CSC_GRPH_MODE 0 1 mmDCP3_INPUT_CSC_C11_C12 0 0xb7b 2 0 2 INPUT_CSC_C11 0 15 INPUT_CSC_C12 16 31 mmDCP3_INPUT_CSC_C13_C14 0 0xb7c 2 0 2 INPUT_CSC_C13 0 15 INPUT_CSC_C14 16 31 mmDCP3_INPUT_CSC_C21_C22 0 0xb7d 2 0 2 INPUT_CSC_C21 0 15 INPUT_CSC_C22 16 31 mmDCP3_INPUT_CSC_C23_C24 0 0xb7e 2 0 2 INPUT_CSC_C23 0 15 INPUT_CSC_C24 16 31 mmDCP3_INPUT_CSC_C31_C32 0 0xb7f 2 0 2 INPUT_CSC_C31 0 15 INPUT_CSC_C32 16 31 mmDCP3_INPUT_CSC_C33_C34 0 0xb80 2 0 2 INPUT_CSC_C33 0 15 INPUT_CSC_C34 16 31 mmDCP3_OUTPUT_CSC_CONTROL 0 0xb81 1 0 2 OUTPUT_CSC_GRPH_MODE 0 2 mmDCP3_OUTPUT_CSC_C11_C12 0 0xb82 2 0 2 OUTPUT_CSC_C11 0 15 OUTPUT_CSC_C12 16 31 mmDCP3_OUTPUT_CSC_C13_C14 0 0xb83 2 0 2 OUTPUT_CSC_C13 0 15 OUTPUT_CSC_C14 16 31 mmDCP3_OUTPUT_CSC_C21_C22 0 0xb84 2 0 2 OUTPUT_CSC_C21 0 15 OUTPUT_CSC_C22 16 31 mmDCP3_OUTPUT_CSC_C23_C24 0 0xb85 2 0 2 OUTPUT_CSC_C23 0 15 OUTPUT_CSC_C24 16 31 mmDCP3_OUTPUT_CSC_C31_C32 0 0xb86 2 0 2 OUTPUT_CSC_C31 0 15 OUTPUT_CSC_C32 16 31 mmDCP3_OUTPUT_CSC_C33_C34 0 0xb87 2 0 2 OUTPUT_CSC_C33 0 15 OUTPUT_CSC_C34 16 31 mmDCP3_COMM_MATRIXA_TRANS_C11_C12 0 0xb88 2 0 2 COMM_MATRIXA_TRANS_C11 0 15 COMM_MATRIXA_TRANS_C12 16 31 mmDCP3_COMM_MATRIXA_TRANS_C13_C14 0 0xb89 2 0 2 COMM_MATRIXA_TRANS_C13 0 15 COMM_MATRIXA_TRANS_C14 16 31 mmDCP3_COMM_MATRIXA_TRANS_C21_C22 0 0xb8a 2 0 2 COMM_MATRIXA_TRANS_C21 0 15 COMM_MATRIXA_TRANS_C22 16 31 mmDCP3_COMM_MATRIXA_TRANS_C23_C24 0 0xb8b 2 0 2 COMM_MATRIXA_TRANS_C23 0 15 COMM_MATRIXA_TRANS_C24 16 31 mmDCP3_COMM_MATRIXA_TRANS_C31_C32 0 0xb8c 2 0 2 COMM_MATRIXA_TRANS_C31 0 15 COMM_MATRIXA_TRANS_C32 16 31 mmDCP3_COMM_MATRIXA_TRANS_C33_C34 0 0xb8d 2 0 2 COMM_MATRIXA_TRANS_C33 0 15 COMM_MATRIXA_TRANS_C34 16 31 mmDCP3_COMM_MATRIXB_TRANS_C11_C12 0 0xb8e 2 0 2 COMM_MATRIXB_TRANS_C11 0 15 COMM_MATRIXB_TRANS_C12 16 31 mmDCP3_COMM_MATRIXB_TRANS_C13_C14 0 0xb8f 2 0 2 COMM_MATRIXB_TRANS_C13 0 15 COMM_MATRIXB_TRANS_C14 16 31 mmDCP3_COMM_MATRIXB_TRANS_C21_C22 0 0xb90 2 0 2 COMM_MATRIXB_TRANS_C21 0 15 COMM_MATRIXB_TRANS_C22 16 31 mmDCP3_COMM_MATRIXB_TRANS_C23_C24 0 0xb91 2 0 2 COMM_MATRIXB_TRANS_C23 0 15 COMM_MATRIXB_TRANS_C24 16 31 mmDCP3_COMM_MATRIXB_TRANS_C31_C32 0 0xb92 2 0 2 COMM_MATRIXB_TRANS_C31 0 15 COMM_MATRIXB_TRANS_C32 16 31 mmDCP3_COMM_MATRIXB_TRANS_C33_C34 0 0xb93 2 0 2 COMM_MATRIXB_TRANS_C33 0 15 COMM_MATRIXB_TRANS_C34 16 31 mmDCP3_DENORM_CONTROL 0 0xb94 2 0 2 DENORM_MODE 0 2 DENORM_14BIT_OUT 4 4 mmDCP3_OUT_ROUND_CONTROL 0 0xb95 1 0 2 OUT_ROUND_TRUNC_MODE 0 3 mmDCP3_OUT_CLAMP_CONTROL_R_CR 0 0xb96 2 0 2 OUT_CLAMP_MAX_R_CR 0 13 OUT_CLAMP_MIN_R_CR 16 29 mmDCP3_OUT_CLAMP_CONTROL_G_Y 0 0xb97 2 0 2 OUT_CLAMP_MAX_G_Y 0 13 OUT_CLAMP_MIN_G_Y 16 29 mmDCP3_OUT_CLAMP_CONTROL_B_CB 0 0xb98 2 0 2 OUT_CLAMP_MAX_B_CB 0 13 OUT_CLAMP_MIN_B_CB 16 29 mmDCP3_KEY_CONTROL 0 0xb99 1 0 2 KEY_MODE 1 2 mmDCP3_KEY_RANGE_ALPHA 0 0xb9a 2 0 2 KEY_ALPHA_LOW 0 15 KEY_ALPHA_HIGH 16 31 mmDCP3_KEY_RANGE_RED 0 0xb9b 2 0 2 KEY_RED_LOW 0 15 KEY_RED_HIGH 16 31 mmDCP3_KEY_RANGE_GREEN 0 0xb9c 2 0 2 KEY_GREEN_LOW 0 15 KEY_GREEN_HIGH 16 31 mmDCP3_KEY_RANGE_BLUE 0 0xb9d 2 0 2 KEY_BLUE_LOW 0 15 KEY_BLUE_HIGH 16 31 mmDCP3_DEGAMMA_CONTROL 0 0xb9e 3 0 2 GRPH_DEGAMMA_MODE 0 1 CURSOR2_DEGAMMA_MODE 8 9 CURSOR_DEGAMMA_MODE 12 13 mmDCP3_GAMUT_REMAP_CONTROL 0 0xb9f 1 0 2 GRPH_GAMUT_REMAP_MODE 0 1 mmDCP3_GAMUT_REMAP_C11_C12 0 0xba0 2 0 2 GAMUT_REMAP_C11 0 15 GAMUT_REMAP_C12 16 31 mmDCP3_GAMUT_REMAP_C13_C14 0 0xba1 2 0 2 GAMUT_REMAP_C13 0 15 GAMUT_REMAP_C14 16 31 mmDCP3_GAMUT_REMAP_C21_C22 0 0xba2 2 0 2 GAMUT_REMAP_C21 0 15 GAMUT_REMAP_C22 16 31 mmDCP3_GAMUT_REMAP_C23_C24 0 0xba3 2 0 2 GAMUT_REMAP_C23 0 15 GAMUT_REMAP_C24 16 31 mmDCP3_GAMUT_REMAP_C31_C32 0 0xba4 2 0 2 GAMUT_REMAP_C31 0 15 GAMUT_REMAP_C32 16 31 mmDCP3_GAMUT_REMAP_C33_C34 0 0xba5 2 0 2 GAMUT_REMAP_C33 0 15 GAMUT_REMAP_C34 16 31 mmDCP3_DCP_SPATIAL_DITHER_CNTL 0 0xba6 6 0 2 DCP_SPATIAL_DITHER_EN 0 0 DCP_SPATIAL_DITHER_MODE 4 5 DCP_SPATIAL_DITHER_DEPTH 6 7 DCP_FRAME_RANDOM_ENABLE 8 8 DCP_RGB_RANDOM_ENABLE 9 9 DCP_HIGHPASS_RANDOM_ENABLE 10 10 mmDCP3_DCP_RANDOM_SEEDS 0 0xba7 3 0 2 DCP_RAND_R_SEED 0 7 DCP_RAND_G_SEED 8 15 DCP_RAND_B_SEED 16 23 mmDCP3_DCP_FP_CONVERTED_FIELD 0 0xba8 2 0 2 DCP_FP_CONVERTED_FIELD_DATA 0 17 DCP_FP_CONVERTED_FIELD_INDEX 20 26 mmDCP3_CUR_CONTROL 0 0xba9 8 0 2 CURSOR_EN 0 0 CUR_INV_TRANS_CLAMP 4 4 CURSOR_MODE 8 9 CURSOR_MAX_OUTSTANDING_GROUP_NUM 11 11 CURSOR_BUSY_START_LINE_POSITION 12 15 CURSOR_2X_MAGNIFY 16 16 CURSOR_FORCE_MC_ON 20 20 CURSOR_URGENT_CONTROL 24 26 mmDCP3_CUR_SURFACE_ADDRESS 0 0xbaa 1 0 2 CURSOR_SURFACE_ADDRESS 0 31 mmDCP3_CUR_SIZE 0 0xbab 2 0 2 CURSOR_HEIGHT 0 6 CURSOR_WIDTH 16 22 mmDCP3_CUR_SURFACE_ADDRESS_HIGH 0 0xbac 1 0 2 CURSOR_SURFACE_ADDRESS_HIGH 0 7 mmDCP3_CUR_POSITION 0 0xbad 2 0 2 CURSOR_Y_POSITION 0 13 CURSOR_X_POSITION 16 29 mmDCP3_CUR_HOT_SPOT 0 0xbae 2 0 2 CURSOR_HOT_SPOT_Y 0 6 CURSOR_HOT_SPOT_X 16 22 mmDCP3_CUR_COLOR1 0 0xbaf 3 0 2 CUR_COLOR1_BLUE 0 7 CUR_COLOR1_GREEN 8 15 CUR_COLOR1_RED 16 23 mmDCP3_CUR_COLOR2 0 0xbb0 3 0 2 CUR_COLOR2_BLUE 0 7 CUR_COLOR2_GREEN 8 15 CUR_COLOR2_RED 16 23 mmDCP3_CUR_UPDATE 0 0xbb1 5 0 2 CURSOR_UPDATE_PENDING 0 0 CURSOR_UPDATE_TAKEN 1 1 CURSOR_UPDATE_LOCK 16 16 CURSOR_DISABLE_MULTIPLE_UPDATE 24 24 CURSOR_UPDATE_STEREO_MODE 25 26 mmDCP3_CUR_REQUEST_FILTER_CNTL 0 0xbbb 1 0 2 CUR_REQUEST_FILTER_DIS 0 0 mmDCP3_CUR_STEREO_CONTROL 0 0xbbc 3 0 2 CURSOR_STEREO_EN 0 0 CURSOR_PRIMARY_OFFSET 4 13 CURSOR_SECONDARY_OFFSET 16 25 mmDCP3_DC_LUT_RW_MODE 0 0xbbe 3 0 2 DC_LUT_RW_MODE 0 0 DC_LUT_ERROR 16 16 DC_LUT_ERROR_RST 17 17 mmDCP3_DC_LUT_RW_INDEX 0 0xbbf 1 0 2 DC_LUT_RW_INDEX 0 7 mmDCP3_DC_LUT_SEQ_COLOR 0 0xbc0 1 0 2 DC_LUT_SEQ_COLOR 0 15 mmDCP3_DC_LUT_PWL_DATA 0 0xbc1 2 0 2 DC_LUT_BASE 0 15 DC_LUT_DELTA 16 31 mmDCP3_DC_LUT_30_COLOR 0 0xbc2 3 0 2 DC_LUT_COLOR_10_BLUE 0 9 DC_LUT_COLOR_10_GREEN 10 19 DC_LUT_COLOR_10_RED 20 29 mmDCP3_DC_LUT_VGA_ACCESS_ENABLE 0 0xbc3 1 0 2 DC_LUT_VGA_ACCESS_ENABLE 0 0 mmDCP3_DC_LUT_WRITE_EN_MASK 0 0xbc4 1 0 2 DC_LUT_WRITE_EN_MASK 0 2 mmDCP3_DC_LUT_AUTOFILL 0 0xbc5 2 0 2 DC_LUT_AUTOFILL 0 0 DC_LUT_AUTOFILL_DONE 1 1 mmDCP3_DC_LUT_CONTROL 0 0xbc6 12 0 2 DC_LUT_INC_B 0 3 DC_LUT_DATA_B_SIGNED_EN 4 4 DC_LUT_DATA_B_FLOAT_POINT_EN 5 5 DC_LUT_DATA_B_FORMAT 6 7 DC_LUT_INC_G 8 11 DC_LUT_DATA_G_SIGNED_EN 12 12 DC_LUT_DATA_G_FLOAT_POINT_EN 13 13 DC_LUT_DATA_G_FORMAT 14 15 DC_LUT_INC_R 16 19 DC_LUT_DATA_R_SIGNED_EN 20 20 DC_LUT_DATA_R_FLOAT_POINT_EN 21 21 DC_LUT_DATA_R_FORMAT 22 23 mmDCP3_DC_LUT_BLACK_OFFSET_BLUE 0 0xbc7 1 0 2 DC_LUT_BLACK_OFFSET_BLUE 0 15 mmDCP3_DC_LUT_BLACK_OFFSET_GREEN 0 0xbc8 1 0 2 DC_LUT_BLACK_OFFSET_GREEN 0 15 mmDCP3_DC_LUT_BLACK_OFFSET_RED 0 0xbc9 1 0 2 DC_LUT_BLACK_OFFSET_RED 0 15 mmDCP3_DC_LUT_WHITE_OFFSET_BLUE 0 0xbca 1 0 2 DC_LUT_WHITE_OFFSET_BLUE 0 15 mmDCP3_DC_LUT_WHITE_OFFSET_GREEN 0 0xbcb 1 0 2 DC_LUT_WHITE_OFFSET_GREEN 0 15 mmDCP3_DC_LUT_WHITE_OFFSET_RED 0 0xbcc 1 0 2 DC_LUT_WHITE_OFFSET_RED 0 15 mmDCP3_DCP_CRC_CONTROL 0 0xbcd 3 0 2 DCP_CRC_ENABLE 0 0 DCP_CRC_SOURCE_SEL 2 4 DCP_CRC_LINE_SEL 8 9 mmDCP3_DCP_CRC_MASK 0 0xbce 1 0 2 DCP_CRC_MASK 0 31 mmDCP3_DCP_CRC_CURRENT 0 0xbcf 1 0 2 DCP_CRC_CURRENT 0 31 mmDCP3_DVMM_PTE_CONTROL 0 0xbd0 6 0 2 DVMM_USE_SINGLE_PTE 0 0 DVMM_PAGE_WIDTH 1 4 DVMM_PAGE_HEIGHT 5 8 DVMM_MIN_PTE_BEFORE_FLIP 9 18 DVMM_PTE_BUFFER_MODE0 20 20 DVMM_PTE_BUFFER_MODE1 21 21 mmDCP3_DCP_CRC_LAST 0 0xbd1 1 0 2 DCP_CRC_LAST 0 31 mmDCP3_DVMM_PTE_ARB_CONTROL 0 0xbd2 2 0 2 DVMM_PTE_REQ_PER_CHUNK 0 5 DVMM_MAX_PTE_REQ_OUTSTANDING 8 15 mmDCP3_GRPH_FLIP_RATE_CNTL 0 0xbd4 2 0 2 GRPH_FLIP_RATE 0 2 GRPH_FLIP_RATE_ENABLE 3 3 mmDCP3_DCP_GSL_CONTROL 0 0xbd5 11 0 2 DCP_GSL0_EN 0 0 DCP_GSL1_EN 1 1 DCP_GSL2_EN 2 2 DCP_GSL_HSYNC_FLIP_FORCE_DELAY 4 19 DCP_GSL_MASTER_EN 20 20 DCP_GSL_XDMA_GROUP 21 22 DCP_GSL_XDMA_GROUP_UNDERFLOW_EN 23 23 DCP_GSL_SYNC_SOURCE 24 25 DCP_GSL_USE_CHECKPOINT_WINDOW_IN_VSYNC 26 26 DCP_GSL_DELAY_SURFACE_UPDATE_PENDING 27 27 DCP_GSL_HSYNC_FLIP_CHECK_DELAY 28 31 mmDCP3_DCP_LB_DATA_GAP_BETWEEN_CHUNK 0 0xbd6 2 0 2 DCP_LB_GAP_BETWEEN_CHUNK_20BPP 0 3 DCP_LB_GAP_BETWEEN_CHUNK_30BPP 4 8 mmDCP3_GRPH_STEREOSYNC_FLIP 0 0xbdc 5 0 2 GRPH_STEREOSYNC_FLIP_EN 0 0 GRPH_STEREOSYNC_FLIP_MODE 8 9 GRPH_PRIMARY_SURFACE_PENDING 16 16 GRPH_SECONDARY_SURFACE_PENDING 17 17 GRPH_STEREOSYNC_SELECT_DISABLE 28 28 mmDCP3_HW_ROTATION 0 0xbde 1 0 2 GRPH_ROTATION_ANGLE 0 2 mmDCP3_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL 0 0xbdf 3 0 2 GRPH_XDMA_CACHE_UNDERFLOW_CNT_EN 0 0 GRPH_XDMA_CACHE_UNDERFLOW_CNT_MODE 1 1 GRPH_XDMA_CACHE_UNDERFLOW_FRAME_CNT 4 16 mmDCP3_REGAMMA_CONTROL 0 0xbe0 1 0 2 GRPH_REGAMMA_MODE 0 2 mmDCP3_REGAMMA_LUT_INDEX 0 0xbe1 1 0 2 REGAMMA_LUT_INDEX 0 8 mmDCP3_REGAMMA_LUT_DATA 0 0xbe2 1 0 2 REGAMMA_LUT_DATA 0 18 mmDCP3_REGAMMA_LUT_WRITE_EN_MASK 0 0xbe3 1 0 2 REGAMMA_LUT_WRITE_EN_MASK 0 2 mmDCP3_REGAMMA_CNTLA_START_CNTL 0 0xbe4 2 0 2 REGAMMA_CNTLA_EXP_REGION_START 0 17 REGAMMA_CNTLA_EXP_REGION_START_SEGMENT 20 26 mmDCP3_REGAMMA_CNTLA_SLOPE_CNTL 0 0xbe5 1 0 2 REGAMMA_CNTLA_EXP_REGION_LINEAR_SLOPE 0 17 mmDCP3_REGAMMA_CNTLA_END_CNTL1 0 0xbe6 1 0 2 REGAMMA_CNTLA_EXP_REGION_END 0 15 mmDCP3_REGAMMA_CNTLA_END_CNTL2 0 0xbe7 2 0 2 REGAMMA_CNTLA_EXP_REGION_END_SLOPE 0 15 REGAMMA_CNTLA_EXP_REGION_END_BASE 16 31 mmDCP3_REGAMMA_CNTLA_REGION_0_1 0 0xbe8 4 0 2 REGAMMA_CNTLA_EXP_REGION0_LUT_OFFSET 0 8 REGAMMA_CNTLA_EXP_REGION0_NUM_SEGMENTS 12 14 REGAMMA_CNTLA_EXP_REGION1_LUT_OFFSET 16 24 REGAMMA_CNTLA_EXP_REGION1_NUM_SEGMENTS 28 30 mmDCP3_REGAMMA_CNTLA_REGION_2_3 0 0xbe9 4 0 2 REGAMMA_CNTLA_EXP_REGION2_LUT_OFFSET 0 8 REGAMMA_CNTLA_EXP_REGION2_NUM_SEGMENTS 12 14 REGAMMA_CNTLA_EXP_REGION3_LUT_OFFSET 16 24 REGAMMA_CNTLA_EXP_REGION3_NUM_SEGMENTS 28 30 mmDCP3_REGAMMA_CNTLA_REGION_4_5 0 0xbea 4 0 2 REGAMMA_CNTLA_EXP_REGION4_LUT_OFFSET 0 8 REGAMMA_CNTLA_EXP_REGION4_NUM_SEGMENTS 12 14 REGAMMA_CNTLA_EXP_REGION5_LUT_OFFSET 16 24 REGAMMA_CNTLA_EXP_REGION5_NUM_SEGMENTS 28 30 mmDCP3_REGAMMA_CNTLA_REGION_6_7 0 0xbeb 4 0 2 REGAMMA_CNTLA_EXP_REGION6_LUT_OFFSET 0 8 REGAMMA_CNTLA_EXP_REGION6_NUM_SEGMENTS 12 14 REGAMMA_CNTLA_EXP_REGION7_LUT_OFFSET 16 24 REGAMMA_CNTLA_EXP_REGION7_NUM_SEGMENTS 28 30 mmDCP3_REGAMMA_CNTLA_REGION_8_9 0 0xbec 4 0 2 REGAMMA_CNTLA_EXP_REGION8_LUT_OFFSET 0 8 REGAMMA_CNTLA_EXP_REGION8_NUM_SEGMENTS 12 14 REGAMMA_CNTLA_EXP_REGION9_LUT_OFFSET 16 24 REGAMMA_CNTLA_EXP_REGION9_NUM_SEGMENTS 28 30 mmDCP3_REGAMMA_CNTLA_REGION_10_11 0 0xbed 4 0 2 REGAMMA_CNTLA_EXP_REGION10_LUT_OFFSET 0 8 REGAMMA_CNTLA_EXP_REGION10_NUM_SEGMENTS 12 14 REGAMMA_CNTLA_EXP_REGION11_LUT_OFFSET 16 24 REGAMMA_CNTLA_EXP_REGION11_NUM_SEGMENTS 28 30 mmDCP3_REGAMMA_CNTLA_REGION_12_13 0 0xbee 4 0 2 REGAMMA_CNTLA_EXP_REGION12_LUT_OFFSET 0 8 REGAMMA_CNTLA_EXP_REGION12_NUM_SEGMENTS 12 14 REGAMMA_CNTLA_EXP_REGION13_LUT_OFFSET 16 24 REGAMMA_CNTLA_EXP_REGION13_NUM_SEGMENTS 28 30 mmDCP3_REGAMMA_CNTLA_REGION_14_15 0 0xbef 4 0 2 REGAMMA_CNTLA_EXP_REGION14_LUT_OFFSET 0 8 REGAMMA_CNTLA_EXP_REGION14_NUM_SEGMENTS 12 14 REGAMMA_CNTLA_EXP_REGION15_LUT_OFFSET 16 24 REGAMMA_CNTLA_EXP_REGION15_NUM_SEGMENTS 28 30 mmDCP3_REGAMMA_CNTLB_START_CNTL 0 0xbf0 2 0 2 REGAMMA_CNTLB_EXP_REGION_START 0 17 REGAMMA_CNTLB_EXP_REGION_START_SEGMENT 20 26 mmDCP3_REGAMMA_CNTLB_SLOPE_CNTL 0 0xbf1 1 0 2 REGAMMA_CNTLB_EXP_REGION_LINEAR_SLOPE 0 17 mmDCP3_REGAMMA_CNTLB_END_CNTL1 0 0xbf2 1 0 2 REGAMMA_CNTLB_EXP_REGION_END 0 15 mmDCP3_REGAMMA_CNTLB_END_CNTL2 0 0xbf3 2 0 2 REGAMMA_CNTLB_EXP_REGION_END_SLOPE 0 15 REGAMMA_CNTLB_EXP_REGION_END_BASE 16 31 mmDCP3_REGAMMA_CNTLB_REGION_0_1 0 0xbf4 4 0 2 REGAMMA_CNTLB_EXP_REGION0_LUT_OFFSET 0 8 REGAMMA_CNTLB_EXP_REGION0_NUM_SEGMENTS 12 14 REGAMMA_CNTLB_EXP_REGION1_LUT_OFFSET 16 24 REGAMMA_CNTLB_EXP_REGION1_NUM_SEGMENTS 28 30 mmDCP3_REGAMMA_CNTLB_REGION_2_3 0 0xbf5 4 0 2 REGAMMA_CNTLB_EXP_REGION2_LUT_OFFSET 0 8 REGAMMA_CNTLB_EXP_REGION2_NUM_SEGMENTS 12 14 REGAMMA_CNTLB_EXP_REGION3_LUT_OFFSET 16 24 REGAMMA_CNTLB_EXP_REGION3_NUM_SEGMENTS 28 30 mmDCP3_REGAMMA_CNTLB_REGION_4_5 0 0xbf6 4 0 2 REGAMMA_CNTLB_EXP_REGION4_LUT_OFFSET 0 8 REGAMMA_CNTLB_EXP_REGION4_NUM_SEGMENTS 12 14 REGAMMA_CNTLB_EXP_REGION5_LUT_OFFSET 16 24 REGAMMA_CNTLB_EXP_REGION5_NUM_SEGMENTS 28 30 mmDCP3_REGAMMA_CNTLB_REGION_6_7 0 0xbf7 4 0 2 REGAMMA_CNTLB_EXP_REGION6_LUT_OFFSET 0 8 REGAMMA_CNTLB_EXP_REGION6_NUM_SEGMENTS 12 14 REGAMMA_CNTLB_EXP_REGION7_LUT_OFFSET 16 24 REGAMMA_CNTLB_EXP_REGION7_NUM_SEGMENTS 28 30 mmDCP3_REGAMMA_CNTLB_REGION_8_9 0 0xbf8 4 0 2 REGAMMA_CNTLB_EXP_REGION8_LUT_OFFSET 0 8 REGAMMA_CNTLB_EXP_REGION8_NUM_SEGMENTS 12 14 REGAMMA_CNTLB_EXP_REGION9_LUT_OFFSET 16 24 REGAMMA_CNTLB_EXP_REGION9_NUM_SEGMENTS 28 30 mmDCP3_REGAMMA_CNTLB_REGION_10_11 0 0xbf9 4 0 2 REGAMMA_CNTLB_EXP_REGION10_LUT_OFFSET 0 8 REGAMMA_CNTLB_EXP_REGION10_NUM_SEGMENTS 12 14 REGAMMA_CNTLB_EXP_REGION11_LUT_OFFSET 16 24 REGAMMA_CNTLB_EXP_REGION11_NUM_SEGMENTS 28 30 mmDCP3_REGAMMA_CNTLB_REGION_12_13 0 0xbfa 4 0 2 REGAMMA_CNTLB_EXP_REGION12_LUT_OFFSET 0 8 REGAMMA_CNTLB_EXP_REGION12_NUM_SEGMENTS 12 14 REGAMMA_CNTLB_EXP_REGION13_LUT_OFFSET 16 24 REGAMMA_CNTLB_EXP_REGION13_NUM_SEGMENTS 28 30 mmDCP3_REGAMMA_CNTLB_REGION_14_15 0 0xbfb 4 0 2 REGAMMA_CNTLB_EXP_REGION14_LUT_OFFSET 0 8 REGAMMA_CNTLB_EXP_REGION14_NUM_SEGMENTS 12 14 REGAMMA_CNTLB_EXP_REGION15_LUT_OFFSET 16 24 REGAMMA_CNTLB_EXP_REGION15_NUM_SEGMENTS 28 30 mmDCP3_ALPHA_CONTROL 0 0xbfc 2 0 2 ALPHA_ROUND_TRUNC_MODE 0 0 CURSOR_ALPHA_BLND_ENA 1 1 mmDCP3_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS 0 0xbfd 1 0 2 GRPH_XDMA_RECOVERY_SURFACE_ADDRESS 8 31 mmDCP3_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH 0 0xbfe 1 0 2 GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH 0 7 mmDCP3_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS 0 0xbff 7 0 2 GRPH_XDMA_CACHE_UNDERFLOW_CNT 0 19 GRPH_XDMA_CACHE_UNDERFLOW_CNT_STATUS 24 24 GRPH_XDMA_CACHE_UNDERFLOW_FRAME_MASK 25 25 GRPH_XDMA_CACHE_UNDERFLOW_FRAME_ACK 26 26 GRPH_XDMA_CACHE_UNDERFLOW_INT 28 28 GRPH_XDMA_CACHE_UNDERFLOW_INT_MASK 29 29 GRPH_XDMA_CACHE_UNDERFLOW_INT_ACK 30 30 mmDCP3_GRPH_XDMA_FLIP_TIMEOUT 0 0xc00 3 0 2 GRPH_XDMA_FLIP_TIMEOUT_STATUS 0 0 GRPH_XDMA_FLIP_TIMEOUT_MASK 1 1 GRPH_XDMA_FLIP_TIMEOUT_ACK 2 2 mmDCP3_GRPH_XDMA_FLIP_AVG_DELAY 0 0xc01 2 0 2 GRPH_XDMA_FLIP_AVG_DELAY 0 15 GRPH_XDMA_FLIP_AVG_PERIOD 16 23 mmDCP3_GRPH_SURFACE_COUNTER_CONTROL 0 0xc02 3 0 2 GRPH_SURFACE_COUNTER_EN 0 0 GRPH_SURFACE_COUNTER_EVENT_SELECT 1 4 GRPH_SURFACE_COUNTER_ERR_WRAP_OCCURED 9 9 mmDCP3_GRPH_SURFACE_COUNTER_OUTPUT 0 0xc03 2 0 2 GRPH_SURFACE_COUNTER_MIN 0 15 GRPH_SURFACE_COUNTER_MAX 16 31 mmLB3_LB_DATA_FORMAT 0 0xc1a 9 0 2 PIXEL_DEPTH 0 1 PIXEL_EXPAN_MODE 2 2 INTERLEAVE_EN 3 3 PIXEL_REDUCE_MODE 4 4 DYNAMIC_PIXEL_DEPTH 5 5 PREFILL_EN 8 8 PREFETCH 12 12 REQUEST_MODE 24 24 ALPHA_EN 31 31 mmLB3_LB_MEMORY_CTRL 0 0xc1b 3 0 2 LB_MEMORY_SIZE 0 12 LB_NUM_PARTITIONS 16 19 LB_MEMORY_CONFIG 20 21 mmLB3_LB_MEMORY_SIZE_STATUS 0 0xc1c 1 0 2 LB_MEMORY_SIZE_STATUS 0 12 mmLB3_LB_DESKTOP_HEIGHT 0 0xc1d 1 0 2 DESKTOP_HEIGHT 0 14 mmLB3_LB_VLINE_START_END 0 0xc1e 3 0 2 VLINE_START 0 13 VLINE_END 16 30 VLINE_INV 31 31 mmLB3_LB_VLINE2_START_END 0 0xc1f 3 0 2 VLINE2_START 0 13 VLINE2_END 16 30 VLINE2_INV 31 31 mmLB3_LB_V_COUNTER 0 0xc20 1 0 2 V_COUNTER 0 14 mmLB3_LB_SNAPSHOT_V_COUNTER 0 0xc21 1 0 2 SNAPSHOT_V_COUNTER 0 14 mmLB3_LB_INTERRUPT_MASK 0 0xc22 3 0 2 VBLANK_INTERRUPT_MASK 0 0 VLINE_INTERRUPT_MASK 4 4 VLINE2_INTERRUPT_MASK 8 8 mmLB3_LB_VLINE_STATUS 0 0xc23 5 0 2 VLINE_OCCURRED 0 0 VLINE_ACK 4 4 VLINE_STAT 12 12 VLINE_INTERRUPT 16 16 VLINE_INTERRUPT_TYPE 17 17 mmLB3_LB_VLINE2_STATUS 0 0xc24 5 0 2 VLINE2_OCCURRED 0 0 VLINE2_ACK 4 4 VLINE2_STAT 12 12 VLINE2_INTERRUPT 16 16 VLINE2_INTERRUPT_TYPE 17 17 mmLB3_LB_VBLANK_STATUS 0 0xc25 5 0 2 VBLANK_OCCURRED 0 0 VBLANK_ACK 4 4 VBLANK_STAT 12 12 VBLANK_INTERRUPT 16 16 VBLANK_INTERRUPT_TYPE 17 17 mmLB3_LB_SYNC_RESET_SEL 0 0xc26 4 0 2 LB_SYNC_RESET_SEL 0 1 LB_SYNC_RESET_SEL2 4 4 LB_SYNC_RESET_DELAY 8 15 LB_SYNC_DURATION 22 23 mmLB3_LB_BLACK_KEYER_R_CR 0 0xc27 1 0 2 LB_BLACK_KEYER_R_CR 4 15 mmLB3_LB_BLACK_KEYER_G_Y 0 0xc28 1 0 2 LB_BLACK_KEYER_G_Y 4 15 mmLB3_LB_BLACK_KEYER_B_CB 0 0xc29 1 0 2 LB_BLACK_KEYER_B_CB 4 15 mmLB3_LB_KEYER_COLOR_CTRL 0 0xc2a 2 0 2 LB_KEYER_COLOR_EN 0 0 LB_KEYER_COLOR_REP_EN 8 8 mmLB3_LB_KEYER_COLOR_R_CR 0 0xc2b 1 0 2 LB_KEYER_COLOR_R_CR 4 15 mmLB3_LB_KEYER_COLOR_G_Y 0 0xc2c 1 0 2 LB_KEYER_COLOR_G_Y 4 15 mmLB3_LB_KEYER_COLOR_B_CB 0 0xc2d 1 0 2 LB_KEYER_COLOR_B_CB 4 15 mmLB3_LB_KEYER_COLOR_REP_R_CR 0 0xc2e 1 0 2 LB_KEYER_COLOR_REP_R_CR 4 15 mmLB3_LB_KEYER_COLOR_REP_G_Y 0 0xc2f 1 0 2 LB_KEYER_COLOR_REP_G_Y 4 15 mmLB3_LB_KEYER_COLOR_REP_B_CB 0 0xc30 1 0 2 LB_KEYER_COLOR_REP_B_CB 4 15 mmLB3_LB_BUFFER_LEVEL_STATUS 0 0xc31 4 0 2 REQ_FIFO_LEVEL 0 5 REQ_FIFO_FULL_CNTL 10 15 DATA_BUFFER_LEVEL 16 27 DATA_FIFO_FULL_CNTL 28 31 mmLB3_LB_BUFFER_URGENCY_CTRL 0 0xc32 2 0 2 LB_BUFFER_URGENCY_MARK_ON 0 11 LB_BUFFER_URGENCY_MARK_OFF 16 27 mmLB3_LB_BUFFER_URGENCY_STATUS 0 0xc33 2 0 2 LB_BUFFER_URGENCY_LEVEL 0 11 LB_BUFFER_URGENCY_STAT 16 16 mmLB3_LB_BUFFER_STATUS 0 0xc34 7 0 2 LB_BUFFER_EMPTY_MARGIN 0 3 LB_BUFFER_EMPTY_STAT 4 4 LB_BUFFER_EMPTY_OCCURRED 8 8 LB_BUFFER_EMPTY_ACK 12 12 LB_BUFFER_FULL_STAT 16 16 LB_BUFFER_FULL_OCCURRED 20 20 LB_BUFFER_FULL_ACK 24 24 mmLB3_LB_NO_OUTSTANDING_REQ_STATUS 0 0xc35 1 0 2 LB_NO_OUTSTANDING_REQ_STAT 0 0 mmLB3_MVP_AFR_FLIP_MODE 0 0xc36 1 0 2 MVP_AFR_FLIP_MODE 0 1 mmLB3_MVP_AFR_FLIP_FIFO_CNTL 0 0xc37 4 0 2 MVP_AFR_FLIP_FIFO_NUM_ENTRIES 0 3 MVP_AFR_FLIP_FIFO_RESET 4 4 MVP_AFR_FLIP_FIFO_RESET_FLAG 8 8 MVP_AFR_FLIP_FIFO_RESET_ACK 12 12 mmLB3_MVP_FLIP_LINE_NUM_INSERT 0 0xc38 4 0 2 MVP_FLIP_LINE_NUM_INSERT_MODE 0 1 MVP_FLIP_LINE_NUM_INSERT 8 22 MVP_FLIP_LINE_NUM_OFFSET 24 29 MVP_FLIP_AUTO_ENABLE 30 30 mmLB3_DC_MVP_LB_CONTROL 0 0xc39 7 0 2 MVP_SWAP_LOCK_IN_MODE 0 1 DC_MVP_SWAP_LOCK_OUT_SEL 8 8 DC_MVP_SWAP_LOCK_OUT_FORCE_ONE 12 12 DC_MVP_SWAP_LOCK_OUT_FORCE_ZERO 16 16 DC_MVP_SWAP_LOCK_STATUS 20 20 DC_MVP_SWAP_LOCK_IN_CAP 28 28 DC_MVP_SPARE_FLOPS 31 31 mmDCFE3_DCFE_CLOCK_CONTROL 0 0xc5a 7 0 2 DISPCLK_R_DCFE_GATE_DISABLE 4 4 DISPCLK_G_DCP_GATE_DISABLE 8 8 DISPCLK_G_SCL_GATE_DISABLE 12 12 DISPCLK_G_PSCL_GATE_DISABLE 15 15 DISPCLK_G_PIPE_REQUEST_DIS_GATE_DISABLE 17 17 DCFE_TEST_CLK_SEL 24 28 DCFE_CLOCK_ENABLE 31 31 mmDCFE3_DCFE_SOFT_RESET 0 0xc5b 6 0 2 DCP_PIXPIPE_SOFT_RESET 0 0 DCP_REQ_SOFT_RESET 1 1 SCL_ALU_SOFT_RESET 2 2 SCL_SOFT_RESET 3 3 CRTC_SOFT_RESET 4 4 PSCL_SOFT_RESET 5 5 mmDCFE3_DCFE_MEM_PWR_CTRL 0 0xc5d 20 0 2 DCP_LUT_MEM_PWR_FORCE 0 1 DCP_LUT_MEM_PWR_DIS 2 2 DCP_REGAMMA_MEM_PWR_FORCE 3 4 DCP_REGAMMA_MEM_PWR_DIS 5 5 SCL_COEFF_MEM_PWR_FORCE 6 7 SCL_COEFF_MEM_PWR_DIS 8 8 DCP_CURSOR_MEM_PWR_FORCE 9 10 DCP_CURSOR_MEM_PWR_DIS 11 11 LB0_ALPHA_MEM_PWR_FORCE 12 13 LB0_ALPHA_MEM_PWR_DIS 14 14 LB1_ALPHA_MEM_PWR_FORCE 15 16 LB1_ALPHA_MEM_PWR_DIS 17 17 LB2_ALPHA_MEM_PWR_FORCE 18 19 LB2_ALPHA_MEM_PWR_DIS 20 20 LB0_MEM_PWR_FORCE 21 22 LB0_MEM_PWR_DIS 23 23 LB1_MEM_PWR_FORCE 24 25 LB1_MEM_PWR_DIS 26 26 LB2_MEM_PWR_FORCE 27 28 LB2_MEM_PWR_DIS 29 29 mmDCFE3_DCFE_MEM_PWR_CTRL2 0 0xc5e 12 0 2 DCP_LUT_MEM_PWR_MODE_SEL 0 1 DCP_REGAMMA_MEM_PWR_MODE_SEL 2 3 SCL_COEFF_MEM_PWR_MODE_SEL 4 5 DCP_CURSOR_MEM_PWR_MODE_SEL 6 7 LB_ALPHA_MEM_PWR_MODE_SEL 8 9 LB_MEM_PWR_MODE_SEL 10 11 DCP_CURSOR2_MEM_PWR_MODE_SEL 12 13 BLND_MEM_PWR_MODE_SEL 14 15 BLND_MEM_PWR_FORCE 16 17 BLND_MEM_PWR_DIS 18 18 DCP_CURSOR2_MEM_PWR_FORCE 21 22 DCP_CURSOR2_MEM_PWR_DIS 23 23 mmDCFE3_DCFE_MEM_PWR_STATUS 0 0xc5f 12 0 2 DCP_LUT_MEM_PWR_STATE 0 1 DCP_REGAMMA_MEM_PWR_STATE 2 3 SCL_COEFF_MEM_PWR_STATE 4 5 DCP_CURSOR_MEM_PWR_STATE 6 7 DCP_CURSOR2_MEM_PWR_STATE 8 9 LB0_ALPHA_MEM_PWR_STATE 10 11 LB1_ALPHA_MEM_PWR_STATE 12 13 LB2_ALPHA_MEM_PWR_STATE 14 15 LB0_MEM_PWR_STATE 16 17 LB1_MEM_PWR_STATE 18 19 LB2_MEM_PWR_STATE 20 21 BLND_MEM_PWR_STATE 22 23 mmDCFE3_DCFE_MISC 0 0xc60 1 0 2 DCFE_DPG_ALLOW_SR_ECO_EN 0 0 mmDCFE3_DCFE_FLUSH 0 0xc61 5 0 2 FLUSH_OCCURED 0 0 CLEAR_FLUSH_OCCURED 1 1 FLUSH_DEEP 2 2 CLEAR_FLUSH_DEEP 3 3 ALL_MC_REQ_RET 4 4 mmDC_PERFMON6_PERFCOUNTER_CNTL 0 0xc6e 13 0 2 PERFCOUNTER_EVENT_SEL 0 8 PERFCOUNTER_CVALUE_SEL 9 11 PERFCOUNTER_INC_MODE 12 14 PERFCOUNTER_HW_CNTL_SEL 15 15 PERFCOUNTER_RUNEN_MODE 16 16 PERFCOUNTER_CNTOFF_SEL 17 21 PERFCOUNTER_CNTOFF_START_DIS 22 22 PERFCOUNTER_RESTART_EN 23 23 PERFCOUNTER_INT_EN 24 24 PERFCOUNTER_OFF_MASK 25 25 PERFCOUNTER_ACTIVE 26 26 PERFCOUNTER_INT_TYPE 27 27 PERFCOUNTER_CNTL_SEL 29 31 mmDC_PERFMON6_PERFCOUNTER_CNTL2 0 0xc6f 4 0 2 PERFCOUNTER_COUNTED_VALUE_TYPE 0 1 PERFCOUNTER_HW_STOP1_SEL 2 2 PERFCOUNTER_HW_STOP2_SEL 3 3 PERFCOUNTER_CNTL2_SEL 29 31 mmDC_PERFMON6_PERFCOUNTER_STATE 0 0xc70 16 0 2 PERFCOUNTER_CNT0_STATE 0 1 PERFCOUNTER_STATE_SEL0 2 2 PERFCOUNTER_CNT1_STATE 4 5 PERFCOUNTER_STATE_SEL1 6 6 PERFCOUNTER_CNT2_STATE 8 9 PERFCOUNTER_STATE_SEL2 10 10 PERFCOUNTER_CNT3_STATE 12 13 PERFCOUNTER_STATE_SEL3 14 14 PERFCOUNTER_CNT4_STATE 16 17 PERFCOUNTER_STATE_SEL4 18 18 PERFCOUNTER_CNT5_STATE 20 21 PERFCOUNTER_STATE_SEL5 22 22 PERFCOUNTER_CNT6_STATE 24 25 PERFCOUNTER_STATE_SEL6 26 26 PERFCOUNTER_CNT7_STATE 28 29 PERFCOUNTER_STATE_SEL7 30 30 mmDC_PERFMON6_PERFMON_CNTL 0 0xc71 6 0 2 PERFMON_STATE 0 1 PERFMON_RPT_COUNT 8 27 PERFMON_CNTOFF_AND_OR 28 28 PERFMON_CNTOFF_INT_EN 29 29 PERFMON_CNTOFF_INT_STATUS 30 30 PERFMON_CNTOFF_INT_ACK 31 31 mmDC_PERFMON6_PERFMON_CNTL2 0 0xc72 4 0 2 PERFMON_CNTOFF_INT_TYPE 0 0 PERFMON_CLK_ENABLE 1 1 PERFMON_RUN_ENABLE_START_SEL 2 9 PERFMON_RUN_ENABLE_STOP_SEL 10 17 mmDC_PERFMON6_PERFMON_CVALUE_INT_MISC 0 0xc73 17 0 2 PERFCOUNTER_INT0_STATUS 0 0 PERFCOUNTER_INT1_STATUS 1 1 PERFCOUNTER_INT2_STATUS 2 2 PERFCOUNTER_INT3_STATUS 3 3 PERFCOUNTER_INT4_STATUS 4 4 PERFCOUNTER_INT5_STATUS 5 5 PERFCOUNTER_INT6_STATUS 6 6 PERFCOUNTER_INT7_STATUS 7 7 PERFCOUNTER_INT0_ACK 8 8 PERFCOUNTER_INT1_ACK 9 9 PERFCOUNTER_INT2_ACK 10 10 PERFCOUNTER_INT3_ACK 11 11 PERFCOUNTER_INT4_ACK 12 12 PERFCOUNTER_INT5_ACK 13 13 PERFCOUNTER_INT6_ACK 14 14 PERFCOUNTER_INT7_ACK 15 15 PERFMON_CVALUE_HI 16 31 mmDC_PERFMON6_PERFMON_CVALUE_LOW 0 0xc74 1 0 2 PERFMON_CVALUE_LOW 0 31 mmDC_PERFMON6_PERFMON_HI 0 0xc75 2 0 2 PERFMON_HI 0 15 PERFMON_READ_SEL 29 31 mmDC_PERFMON6_PERFMON_LOW 0 0xc76 1 0 2 PERFMON_LOW 0 31 mmDMIF_PG3_DPG_PIPE_ARBITRATION_CONTROL1 0 0xc7a 2 0 2 PIXEL_DURATION 0 15 BASE_WEIGHT 16 31 mmDMIF_PG3_DPG_PIPE_ARBITRATION_CONTROL2 0 0xc7b 2 0 2 TIME_WEIGHT 0 15 URGENCY_WEIGHT 16 31 mmDMIF_PG3_DPG_WATERMARK_MASK_CONTROL 0 0xc7c 8 0 2 STUTTER_EXIT_SELF_REFRESH_WATERMARK_MASK 0 2 STUTTER_ENTER_SELF_REFRESH_WATERMARK_MASK 4 6 URGENCY_WATERMARK_MASK 8 10 URGENT_LEVEL_WATERMARK_MASK 12 14 PSTATE_CHANGE_WATERMARK_MASK 15 17 DISABLE_FLIP_URGENT 18 18 URGENT_LEVEL_RAMP_CONTROL 19 19 STATIC_URGENT_LEVEL 20 29 mmDMIF_PG3_DPG_PIPE_URGENCY_CONTROL 0 0xc7d 2 0 2 URGENCY_LOW_WATERMARK 0 15 URGENCY_HIGH_WATERMARK 16 31 mmDMIF_PG3_DPG_PIPE_URGENT_LEVEL_CONTROL 0 0xc7e 2 0 2 URGENT_LEVEL_LOW_WATERMARK 0 15 URGENT_LEVEL_HIGH_WATERMARK 16 31 mmDMIF_PG3_DPG_PIPE_STUTTER_CONTROL 0 0xc7f 14 0 2 STUTTER_ENABLE 0 0 STUTTER_IGNORE_CURSOR 4 4 STUTTER_IGNORE_ICON 5 5 STUTTER_IGNORE_VGA 6 6 STUTTER_IGNORE_FBC 7 7 STUTTER_URGENT_IN_NOT_SELF_REFRESH 10 10 STUTTER_SELF_REFRESH_FORCE_ON 11 11 STUTTER_ENABLE_NONLPTCH 16 16 STUTTER_IGNORE_CURSOR_NONLPTCH 20 20 STUTTER_IGNORE_ICON_NONLPTCH 21 21 STUTTER_IGNORE_VGA_NONLPTCH 22 22 STUTTER_IGNORE_FBC_NONLPTCH 23 23 STUTTER_URGENT_IN_NOT_SELF_REFRESH_NONLPTCH 26 26 STUTTER_SELF_REFRESH_FORCE_ON_NONLPTCH 27 27 mmDMIF_PG3_DPG_PIPE_STUTTER_CONTROL2 0 0xc80 2 0 2 STUTTER_EXIT_SELF_REFRESH_WATERMARK 0 15 STUTTER_ENTER_SELF_REFRESH_WATERMARK 16 31 mmDMIF_PG3_DPG_PIPE_LOW_POWER_CONTROL 0 0xc81 7 0 2 PSTATE_CHANGE_ENABLE 0 0 DPM_ENABLE 1 1 PSTATE_CHANGE_URGENT_DURING_REQUEST 4 4 PSTATE_CHANGE_NOT_SELF_REFRESH_DURING_REQUEST 8 8 PSTATE_CHANGE_FORCE_ON 9 9 PSTATE_ALLOW_FOR_URGENT 10 10 PSTATE_CHANGE_WATERMARK 15 31 mmDMIF_PG3_DPG_REPEATER_PROGRAM 0 0xc82 2 0 2 REG_DPG_DMIFRC_REPEATER 0 2 REG_DMIFRC_DPG_REPEATER 4 6 mmDMIF_PG3_DPG_CHK_PRE_PROC_CNTL 0 0xc86 1 0 2 DPG_DISABLE_DMIF_BUF_CHK 0 0 mmDMIF_PG3_DPG_DVMM_STATUS 0 0xc87 4 0 2 DPG_DVMM_FORCED_FLIP_TO_UNMAPPED 0 0 DPG_DVMM_FORCED_FLIP_TO_MAPPED 1 1 DPG_DVMM_FORCED_FLIP_TO_UNMAPPED_CLR 4 4 DPG_DVMM_FORCED_FLIP_TO_MAPPED_CLR 5 5 mmSCL3_SCL_COEF_RAM_SELECT 0 0xc9a 3 0 2 SCL_C_RAM_TAP_PAIR_IDX 0 3 SCL_C_RAM_PHASE 8 11 SCL_C_RAM_FILTER_TYPE 16 18 mmSCL3_SCL_COEF_RAM_TAP_DATA 0 0xc9b 4 0 2 SCL_C_RAM_EVEN_TAP_COEF 0 13 SCL_C_RAM_EVEN_TAP_COEF_EN 15 15 SCL_C_RAM_ODD_TAP_COEF 16 29 SCL_C_RAM_ODD_TAP_COEF_EN 31 31 mmSCL3_SCL_MODE 0 0xc9c 2 0 2 SCL_MODE 0 1 SCL_PSCL_EN 4 4 mmSCL3_SCL_TAP_CONTROL 0 0xc9d 2 0 2 SCL_V_NUM_OF_TAPS 0 2 SCL_H_NUM_OF_TAPS 8 11 mmSCL3_SCL_CONTROL 0 0xc9e 2 0 2 SCL_BOUNDARY_MODE 0 0 SCL_EARLY_EOL_MODE 4 4 mmSCL3_SCL_BYPASS_CONTROL 0 0xc9f 1 0 2 SCL_BYPASS_MODE 0 1 mmSCL3_SCL_MANUAL_REPLICATE_CONTROL 0 0xca0 2 0 2 SCL_V_MANUAL_REPLICATE_FACTOR 0 3 SCL_H_MANUAL_REPLICATE_FACTOR 8 11 mmSCL3_SCL_AUTOMATIC_MODE_CONTROL 0 0xca1 2 0 2 SCL_V_CALC_AUTO_RATIO_EN 0 0 SCL_H_CALC_AUTO_RATIO_EN 16 16 mmSCL3_SCL_HORZ_FILTER_CONTROL 0 0xca2 2 0 2 SCL_H_FILTER_PICK_NEAREST 0 0 SCL_H_2TAP_HARDCODE_COEF_EN 8 8 mmSCL3_SCL_HORZ_FILTER_SCALE_RATIO 0 0xca3 1 0 2 SCL_H_SCALE_RATIO 0 25 mmSCL3_SCL_HORZ_FILTER_INIT 0 0xca4 2 0 2 SCL_H_INIT_FRAC 0 23 SCL_H_INIT_INT 24 27 mmSCL3_SCL_VERT_FILTER_CONTROL 0 0xca5 2 0 2 SCL_V_FILTER_PICK_NEAREST 0 0 SCL_V_2TAP_HARDCODE_COEF_EN 8 8 mmSCL3_SCL_VERT_FILTER_SCALE_RATIO 0 0xca6 1 0 2 SCL_V_SCALE_RATIO 0 25 mmSCL3_SCL_VERT_FILTER_INIT 0 0xca7 2 0 2 SCL_V_INIT_FRAC 0 23 SCL_V_INIT_INT 24 26 mmSCL3_SCL_VERT_FILTER_INIT_BOT 0 0xca8 2 0 2 SCL_V_INIT_FRAC_BOT 0 23 SCL_V_INIT_INT_BOT 24 26 mmSCL3_SCL_ROUND_OFFSET 0 0xca9 2 0 2 SCL_ROUND_OFFSET_RGB_Y 0 15 SCL_ROUND_OFFSET_CBCR 16 31 mmSCL3_SCL_UPDATE 0 0xcaa 4 0 2 SCL_UPDATE_PENDING 0 0 SCL_UPDATE_TAKEN 8 8 SCL_UPDATE_LOCK 16 16 SCL_COEF_UPDATE_COMPLETE 24 24 mmSCL3_SCL_F_SHARP_CONTROL 0 0xcab 4 0 2 SCL_HF_SHARP_SCALE_FACTOR 0 2 SCL_HF_SHARP_EN 4 4 SCL_VF_SHARP_SCALE_FACTOR 8 10 SCL_VF_SHARP_EN 12 12 mmSCL3_SCL_ALU_CONTROL 0 0xcac 1 0 2 SCL_ALU_DISABLE 0 0 mmSCL3_SCL_COEF_RAM_CONFLICT_STATUS 0 0xcad 4 0 2 SCL_HOST_CONFLICT_FLAG 0 0 SCL_HOST_CONFLICT_ACK 8 8 SCL_HOST_CONFLICT_MASK 12 12 SCL_HOST_CONFLICT_INT_STATUS 16 16 mmSCL3_VIEWPORT_START_SECONDARY 0 0xcae 2 0 2 VIEWPORT_Y_START_SECONDARY 0 13 VIEWPORT_X_START_SECONDARY 16 29 mmSCL3_VIEWPORT_START 0 0xcaf 2 0 2 VIEWPORT_Y_START 0 13 VIEWPORT_X_START 16 29 mmSCL3_VIEWPORT_SIZE 0 0xcb0 2 0 2 VIEWPORT_HEIGHT 0 13 VIEWPORT_WIDTH 16 29 mmSCL3_EXT_OVERSCAN_LEFT_RIGHT 0 0xcb1 2 0 2 EXT_OVERSCAN_RIGHT 0 12 EXT_OVERSCAN_LEFT 16 28 mmSCL3_EXT_OVERSCAN_TOP_BOTTOM 0 0xcb2 2 0 2 EXT_OVERSCAN_BOTTOM 0 12 EXT_OVERSCAN_TOP 16 28 mmSCL3_SCL_MODE_CHANGE_DET1 0 0xcb3 3 0 2 SCL_MODE_CHANGE 0 0 SCL_MODE_CHANGE_ACK 4 4 SCL_ALU_H_SCALE_RATIO 7 27 mmSCL3_SCL_MODE_CHANGE_DET2 0 0xcb4 1 0 2 SCL_ALU_V_SCALE_RATIO 0 20 mmSCL3_SCL_MODE_CHANGE_DET3 0 0xcb5 2 0 2 SCL_ALU_SOURCE_HEIGHT 0 13 SCL_ALU_SOURCE_WIDTH 16 29 mmSCL3_SCL_MODE_CHANGE_MASK 0 0xcb6 1 0 2 SCL_MODE_CHANGE_MASK 0 0 mmBLND3_BLND_CONTROL 0 0xcc7 9 0 2 BLND_GLOBAL_GAIN 0 7 BLND_MODE 8 9 BLND_STEREO_TYPE 10 11 BLND_STEREO_POLARITY 12 12 BLND_FEEDTHROUGH_EN 13 13 BLND_ALPHA_MODE 16 17 BLND_ACTIVE_OVERLAP_ONLY 18 18 BLND_MULTIPLIED_MODE 20 20 BLND_GLOBAL_ALPHA 24 31 mmBLND3_BLND_SM_CONTROL2 0 0xcc8 6 0 2 SM_MODE 0 2 SM_FRAME_ALTERNATE 4 4 SM_FIELD_ALTERNATE 5 5 SM_FORCE_NEXT_FRAME_POL 8 9 SM_FORCE_NEXT_TOP_POL 16 17 SM_CURRENT_FRAME_POL 24 24 mmBLND3_BLND_CONTROL2 0 0xcc9 5 0 2 PTI_ENABLE 0 0 PTI_NEW_PIXEL_GAP 4 5 BLND_NEW_PIXEL_MODE 6 6 BLND_SUPERAA_DEGAMMA_EN 7 7 BLND_SUPERAA_REGAMMA_EN 8 8 mmBLND3_BLND_UPDATE 0 0xcca 3 0 2 BLND_UPDATE_PENDING 0 0 BLND_UPDATE_TAKEN 8 8 BLND_UPDATE_LOCK 16 16 mmBLND3_BLND_UNDERFLOW_INTERRUPT 0 0xccb 4 0 2 BLND_UNDERFLOW_INT_OCCURED 0 0 BLND_UNDERFLOW_INT_ACK 8 8 BLND_UNDERFLOW_INT_MASK 12 12 BLND_UNDERFLOW_INT_PIPE_INDEX 16 17 mmBLND3_BLND_V_UPDATE_LOCK 0 0xccc 6 0 2 BLND_DCP_GRPH_V_UPDATE_LOCK 0 0 BLND_DCP_GRPH_SURF_V_UPDATE_LOCK 1 1 BLND_DCP_CUR_V_UPDATE_LOCK 16 16 BLND_SCL_V_UPDATE_LOCK 28 28 BLND_BLND_V_UPDATE_LOCK 29 29 BLND_V_UPDATE_LOCK_MODE 31 31 mmBLND3_BLND_REG_UPDATE_STATUS 0 0xccd 10 0 2 DCP_BLNDC_GRPH_UPDATE_PENDING 0 0 DCP_BLNDO_GRPH_UPDATE_PENDING 1 1 DCP_BLNDC_GRPH_SURF_UPDATE_PENDING 2 2 DCP_BLNDO_GRPH_SURF_UPDATE_PENDING 3 3 DCP_BLNDC_CUR_UPDATE_PENDING 6 6 DCP_BLNDO_CUR_UPDATE_PENDING 7 7 SCL_BLNDC_UPDATE_PENDING 8 8 SCL_BLNDO_UPDATE_PENDING 9 9 BLND_BLNDC_UPDATE_PENDING 10 10 BLND_BLNDO_UPDATE_PENDING 11 11 mmCRTC3_CRTC_H_BLANK_EARLY_NUM 0 0xcd2 2 0 2 CRTC_H_BLANK_EARLY_NUM 0 9 CRTC_H_BLANK_EARLY_NUM_DIS 16 16 mmCRTC3_CRTC_H_TOTAL 0 0xcd3 1 0 2 CRTC_H_TOTAL 0 13 mmCRTC3_CRTC_H_BLANK_START_END 0 0xcd4 2 0 2 CRTC_H_BLANK_START 0 13 CRTC_H_BLANK_END 16 29 mmCRTC3_CRTC_H_SYNC_A 0 0xcd5 2 0 2 CRTC_H_SYNC_A_START 0 13 CRTC_H_SYNC_A_END 16 29 mmCRTC3_CRTC_H_SYNC_A_CNTL 0 0xcd6 3 0 2 CRTC_H_SYNC_A_POL 0 0 CRTC_COMP_SYNC_A_EN 16 16 CRTC_H_SYNC_A_CUTOFF 17 17 mmCRTC3_CRTC_H_SYNC_B 0 0xcd7 2 0 2 CRTC_H_SYNC_B_START 0 13 CRTC_H_SYNC_B_END 16 29 mmCRTC3_CRTC_H_SYNC_B_CNTL 0 0xcd8 3 0 2 CRTC_H_SYNC_B_POL 0 0 CRTC_COMP_SYNC_B_EN 16 16 CRTC_H_SYNC_B_CUTOFF 17 17 mmCRTC3_CRTC_VBI_END 0 0xcd9 2 0 2 CRTC_VBI_V_END 0 13 CRTC_VBI_H_END 16 29 mmCRTC3_CRTC_V_TOTAL 0 0xcda 1 0 2 CRTC_V_TOTAL 0 13 mmCRTC3_CRTC_V_TOTAL_MIN 0 0xcdb 1 0 2 CRTC_V_TOTAL_MIN 0 13 mmCRTC3_CRTC_V_TOTAL_MAX 0 0xcdc 2 0 2 CRTC_V_TOTAL_MAX 0 13 CRTC_ALLOW_VBLANK_EXTENSION_FOR_MC_TRAINING 16 16 mmCRTC3_CRTC_V_TOTAL_CONTROL 0 0xcdd 6 0 2 CRTC_V_TOTAL_MIN_SEL 0 0 CRTC_V_TOTAL_MAX_SEL 4 4 CRTC_FORCE_LOCK_ON_EVENT 8 8 CRTC_FORCE_LOCK_TO_MASTER_VSYNC 12 12 CRTC_SET_V_TOTAL_MIN_MASK_EN 15 15 CRTC_SET_V_TOTAL_MIN_MASK 16 31 mmCRTC3_CRTC_V_TOTAL_INT_STATUS 0 0xcde 4 0 2 CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED 0 0 CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT 4 4 CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_ACK 8 8 CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_MSK 12 12 mmCRTC3_CRTC_VSYNC_NOM_INT_STATUS 0 0xcdf 2 0 2 CRTC_VSYNC_NOM 0 0 CRTC_VSYNC_NOM_INT_CLEAR 4 4 mmCRTC3_CRTC_V_BLANK_START_END 0 0xce0 2 0 2 CRTC_V_BLANK_START 0 13 CRTC_V_BLANK_END 16 29 mmCRTC3_CRTC_V_SYNC_A 0 0xce1 2 0 2 CRTC_V_SYNC_A_START 0 13 CRTC_V_SYNC_A_END 16 29 mmCRTC3_CRTC_V_SYNC_A_CNTL 0 0xce2 1 0 2 CRTC_V_SYNC_A_POL 0 0 mmCRTC3_CRTC_V_SYNC_B 0 0xce3 2 0 2 CRTC_V_SYNC_B_START 0 13 CRTC_V_SYNC_B_END 16 29 mmCRTC3_CRTC_V_SYNC_B_CNTL 0 0xce4 1 0 2 CRTC_V_SYNC_B_POL 0 0 mmCRTC3_CRTC_DTMTEST_CNTL 0 0xce5 2 0 2 CRTC_DTMTEST_CRTC_EN 0 0 CRTC_DTMTEST_CLK_DIV 1 4 mmCRTC3_CRTC_DTMTEST_STATUS_POSITION 0 0xce6 2 0 2 CRTC_DTMTEST_VERT_COUNT 0 13 CRTC_DTMTEST_HORZ_COUNT 16 29 mmCRTC3_CRTC_TRIGA_CNTL 0 0xce7 11 0 2 CRTC_TRIGA_SOURCE_SELECT 0 4 CRTC_TRIGA_POLARITY_SELECT 5 7 CRTC_TRIGA_RESYNC_BYPASS_EN 8 8 CRTC_TRIGA_INPUT_STATUS 9 9 CRTC_TRIGA_POLARITY_STATUS 10 10 CRTC_TRIGA_OCCURRED 11 11 CRTC_TRIGA_RISING_EDGE_DETECT_CNTL 12 13 CRTC_TRIGA_FALLING_EDGE_DETECT_CNTL 16 17 CRTC_TRIGA_FREQUENCY_SELECT 20 21 CRTC_TRIGA_DELAY 24 28 CRTC_TRIGA_CLEAR 31 31 mmCRTC3_CRTC_TRIGA_MANUAL_TRIG 0 0xce8 1 0 2 CRTC_TRIGA_MANUAL_TRIG 0 0 mmCRTC3_CRTC_TRIGB_CNTL 0 0xce9 11 0 2 CRTC_TRIGB_SOURCE_SELECT 0 4 CRTC_TRIGB_POLARITY_SELECT 5 7 CRTC_TRIGB_RESYNC_BYPASS_EN 8 8 CRTC_TRIGB_INPUT_STATUS 9 9 CRTC_TRIGB_POLARITY_STATUS 10 10 CRTC_TRIGB_OCCURRED 11 11 CRTC_TRIGB_RISING_EDGE_DETECT_CNTL 12 13 CRTC_TRIGB_FALLING_EDGE_DETECT_CNTL 16 17 CRTC_TRIGB_FREQUENCY_SELECT 20 21 CRTC_TRIGB_DELAY 24 28 CRTC_TRIGB_CLEAR 31 31 mmCRTC3_CRTC_TRIGB_MANUAL_TRIG 0 0xcea 1 0 2 CRTC_TRIGB_MANUAL_TRIG 0 0 mmCRTC3_CRTC_FORCE_COUNT_NOW_CNTL 0 0xceb 5 0 2 CRTC_FORCE_COUNT_NOW_MODE 0 1 CRTC_FORCE_COUNT_NOW_CHECK 4 4 CRTC_FORCE_COUNT_NOW_TRIG_SEL 8 8 CRTC_FORCE_COUNT_NOW_OCCURRED 16 16 CRTC_FORCE_COUNT_NOW_CLEAR 24 24 mmCRTC3_CRTC_FLOW_CONTROL 0 0xcec 4 0 2 CRTC_FLOW_CONTROL_SOURCE_SELECT 0 4 CRTC_FLOW_CONTROL_POLARITY 8 8 CRTC_FLOW_CONTROL_GRANULARITY 16 16 CRTC_FLOW_CONTROL_INPUT_STATUS 24 24 mmCRTC3_CRTC_STEREO_FORCE_NEXT_EYE 0 0xced 3 0 2 CRTC_STEREO_FORCE_NEXT_EYE 0 1 CRTC_AVSYNC_FRAME_COUNTER 8 15 CRTC_AVSYNC_LINE_COUNTER 16 28 mmCRTC3_CRTC_AVSYNC_COUNTER 0 0xcee 1 0 2 CRTC_AVSYNC_COUNTER 0 31 mmCRTC3_CRTC_CONTROL 0 0xcef 11 0 2 CRTC_MASTER_EN 0 0 CRTC_SYNC_RESET_SEL 4 4 CRTC_DISABLE_POINT_CNTL 8 9 CRTC_START_POINT_CNTL 12 12 CRTC_FIELD_NUMBER_CNTL 13 13 CRTC_FIELD_NUMBER_POLARITY 14 14 CRTC_CURRENT_MASTER_EN_STATE 16 16 CRTC_HBLANK_EARLY_CONTROL 20 22 CRTC_SOF_PULL_EN 29 29 CRTC_AVSYNC_LOCK_SNAPSHOT 30 30 CRTC_AVSYNC_VSYNC_N_HSYNC_MODE 31 31 mmCRTC3_CRTC_BLANK_CONTROL 0 0xcf0 3 0 2 CRTC_CURRENT_BLANK_STATE 0 0 CRTC_BLANK_DATA_EN 8 8 CRTC_BLANK_DE_MODE 16 16 mmCRTC3_CRTC_INTERLACE_CONTROL 0 0xcf1 2 0 2 CRTC_INTERLACE_ENABLE 0 0 CRTC_INTERLACE_FORCE_NEXT_FIELD 16 17 mmCRTC3_CRTC_INTERLACE_STATUS 0 0xcf2 2 0 2 CRTC_INTERLACE_CURRENT_FIELD 0 0 CRTC_INTERLACE_NEXT_FIELD 1 1 mmCRTC3_CRTC_FIELD_INDICATION_CONTROL 0 0xcf3 2 0 2 CRTC_FIELD_INDICATION_OUTPUT_POLARITY 0 0 CRTC_FIELD_ALIGNMENT 1 1 mmCRTC3_CRTC_PIXEL_DATA_READBACK0 0 0xcf4 2 0 2 CRTC_PIXEL_DATA_BLUE_CB 0 11 CRTC_PIXEL_DATA_GREEN_Y 16 27 mmCRTC3_CRTC_PIXEL_DATA_READBACK1 0 0xcf5 1 0 2 CRTC_PIXEL_DATA_RED_CR 0 11 mmCRTC3_CRTC_STATUS 0 0xcf6 9 0 2 CRTC_V_BLANK 0 0 CRTC_V_ACTIVE_DISP 1 1 CRTC_V_SYNC_A 2 2 CRTC_V_UPDATE 3 3 CRTC_V_START_LINE 4 4 CRTC_V_BLANK_3D_STRUCTURE 5 5 CRTC_H_BLANK 16 16 CRTC_H_ACTIVE_DISP 17 17 CRTC_H_SYNC_A 18 18 mmCRTC3_CRTC_STATUS_POSITION 0 0xcf7 2 0 2 CRTC_VERT_COUNT 0 13 CRTC_HORZ_COUNT 16 29 mmCRTC3_CRTC_NOM_VERT_POSITION 0 0xcf8 1 0 2 CRTC_VERT_COUNT_NOM 0 13 mmCRTC3_CRTC_STATUS_FRAME_COUNT 0 0xcf9 1 0 2 CRTC_FRAME_COUNT 0 23 mmCRTC3_CRTC_STATUS_VF_COUNT 0 0xcfa 1 0 2 CRTC_VF_COUNT 0 29 mmCRTC3_CRTC_STATUS_HV_COUNT 0 0xcfb 1 0 2 CRTC_HV_COUNT 0 29 mmCRTC3_CRTC_COUNT_CONTROL 0 0xcfc 2 0 2 CRTC_HORZ_COUNT_BY2_EN 0 0 CRTC_HORZ_REPETITION_COUNT 1 4 mmCRTC3_CRTC_COUNT_RESET 0 0xcfd 1 0 2 CRTC_RESET_FRAME_COUNT 0 0 mmCRTC3_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE 0 0xcfe 1 0 2 CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE 0 0 mmCRTC3_CRTC_VERT_SYNC_CONTROL 0 0xcff 3 0 2 CRTC_FORCE_VSYNC_NEXT_LINE_OCCURRED 0 0 CRTC_FORCE_VSYNC_NEXT_LINE_CLEAR 8 8 CRTC_AUTO_FORCE_VSYNC_MODE 16 17 mmCRTC3_CRTC_STEREO_STATUS 0 0xd00 5 0 2 CRTC_STEREO_CURRENT_EYE 0 0 CRTC_STEREO_SYNC_OUTPUT 8 8 CRTC_STEREO_SYNC_SELECT 16 16 CRTC_STEREO_EYE_FLAG 20 20 CRTC_STEREO_FORCE_NEXT_EYE_PENDING 24 25 mmCRTC3_CRTC_STEREO_CONTROL 0 0xd01 8 0 2 CRTC_STEREO_SYNC_OUTPUT_LINE_NUM 0 13 CRTC_STEREO_SYNC_OUTPUT_POLARITY 15 15 CRTC_STEREO_SYNC_SELECT_POLARITY 16 16 CRTC_STEREO_EYE_FLAG_POLARITY 17 17 CRTC_DISABLE_STEREOSYNC_OUTPUT_FOR_DP 18 18 CRTC_DISABLE_FIELD_NUM 19 19 CRTC_DISABLE_V_BLANK_FOR_DP_FIX 20 20 CRTC_STEREO_EN 24 24 mmCRTC3_CRTC_SNAPSHOT_STATUS 0 0xd02 3 0 2 CRTC_SNAPSHOT_OCCURRED 0 0 CRTC_SNAPSHOT_CLEAR 1 1 CRTC_SNAPSHOT_MANUAL_TRIGGER 2 2 mmCRTC3_CRTC_SNAPSHOT_CONTROL 0 0xd03 1 0 2 CRTC_AUTO_SNAPSHOT_TRIG_SEL 0 1 mmCRTC3_CRTC_SNAPSHOT_POSITION 0 0xd04 2 0 2 CRTC_SNAPSHOT_VERT_COUNT 0 13 CRTC_SNAPSHOT_HORZ_COUNT 16 29 mmCRTC3_CRTC_SNAPSHOT_FRAME 0 0xd05 1 0 2 CRTC_SNAPSHOT_FRAME_COUNT 0 23 mmCRTC3_CRTC_START_LINE_CONTROL 0 0xd06 5 0 2 CRTC_PROGRESSIVE_START_LINE_EARLY 0 0 CRTC_INTERLACE_START_LINE_EARLY 1 1 CRTC_PREFETCH_EN 2 2 CRTC_LEGACY_REQUESTOR_EN 8 8 CRTC_ADVANCED_START_LINE_POSITION 12 19 mmCRTC3_CRTC_INTERRUPT_CONTROL 0 0xd07 16 0 2 CRTC_SNAPSHOT_INT_MSK 0 0 CRTC_SNAPSHOT_INT_TYPE 1 1 CRTC_V_UPDATE_INT_MSK 4 4 CRTC_V_UPDATE_INT_TYPE 5 5 CRTC_FORCE_COUNT_NOW_INT_MSK 8 8 CRTC_FORCE_COUNT_NOW_INT_TYPE 9 9 CRTC_FORCE_VSYNC_NEXT_LINE_INT_MSK 16 16 CRTC_FORCE_VSYNC_NEXT_LINE_INT_TYPE 17 17 CRTC_TRIGA_INT_MSK 24 24 CRTC_TRIGB_INT_MSK 25 25 CRTC_TRIGA_INT_TYPE 26 26 CRTC_TRIGB_INT_TYPE 27 27 CRTC_VSYNC_NOM_INT_MSK 28 28 CRTC_VSYNC_NOM_INT_TYPE 29 29 CRTC_GSL_VSYNC_GAP_INT_MSK 30 30 CRTC_GSL_VSYNC_GAP_INT_TYPE 31 31 mmCRTC3_CRTC_UPDATE_LOCK 0 0xd08 1 0 2 CRTC_UPDATE_LOCK 0 0 mmCRTC3_CRTC_DOUBLE_BUFFER_CONTROL 0 0xd09 5 0 2 CRTC_UPDATE_PENDING 0 0 CRTC_UPDATE_INSTANTLY 8 8 CRTC_BLANK_DATA_DOUBLE_BUFFER_EN 16 16 CRTC_RANGE_TIMING_DBUF_UPDATE_MODE 24 24 CRTC_RANGE_TIMING_DBUF_UPDATE_PENDING 25 25 mmCRTC3_CRTC_VGA_PARAMETER_CAPTURE_MODE 0 0xd0a 1 0 2 CRTC_VGA_PARAMETER_CAPTURE_MODE 0 0 mmCRTC3_CRTC_TEST_PATTERN_CONTROL 0 0xd0b 4 0 2 CRTC_TEST_PATTERN_EN 0 0 CRTC_TEST_PATTERN_MODE 8 10 CRTC_TEST_PATTERN_DYNAMIC_RANGE 16 16 CRTC_TEST_PATTERN_COLOR_FORMAT 24 31 mmCRTC3_CRTC_TEST_PATTERN_PARAMETERS 0 0xd0c 5 0 2 CRTC_TEST_PATTERN_INC0 0 3 CRTC_TEST_PATTERN_INC1 4 7 CRTC_TEST_PATTERN_VRES 8 11 CRTC_TEST_PATTERN_HRES 12 15 CRTC_TEST_PATTERN_RAMP0_OFFSET 16 31 mmCRTC3_CRTC_TEST_PATTERN_COLOR 0 0xd0d 2 0 2 CRTC_TEST_PATTERN_DATA 0 15 CRTC_TEST_PATTERN_MASK 16 21 mmCRTC3_CRTC_MASTER_UPDATE_LOCK 0 0xd0e 3 0 2 MASTER_UPDATE_LOCK 0 0 GSL_CONTROL_MASTER_UPDATE_LOCK 8 8 UNDERFLOW_UPDATE_LOCK 16 16 mmCRTC3_CRTC_MASTER_UPDATE_MODE 0 0xd0f 2 0 2 MASTER_UPDATE_MODE 0 2 MASTER_UPDATE_INTERLACED_MODE 16 17 mmCRTC3_CRTC_MVP_INBAND_CNTL_INSERT 0 0xd10 2 0 2 CRTC_MVP_INBAND_OUT_MODE 0 1 CRTC_MVP_INBAND_CNTL_CHAR_INSERT 8 31 mmCRTC3_CRTC_MVP_INBAND_CNTL_INSERT_TIMER 0 0xd11 1 0 2 CRTC_MVP_INBAND_CNTL_CHAR_INSERT_TIMER 0 7 mmCRTC3_CRTC_MVP_STATUS 0 0xd12 4 0 2 CRTC_FLIP_NOW_OCCURRED 0 0 CRTC_AFR_HSYNC_SWITCH_DONE_OCCURRED 4 4 CRTC_FLIP_NOW_CLEAR 16 16 CRTC_AFR_HSYNC_SWITCH_DONE_CLEAR 20 20 mmCRTC3_CRTC_MASTER_EN 0 0xd13 1 0 2 CRTC_MASTER_EN 0 0 mmCRTC3_CRTC_ALLOW_STOP_OFF_V_CNT 0 0xd14 2 0 2 CRTC_ALLOW_STOP_OFF_V_CNT 0 7 CRTC_DISABLE_ALLOW_STOP_OFF_V_CNT 16 16 mmCRTC3_CRTC_V_UPDATE_INT_STATUS 0 0xd15 2 0 2 CRTC_V_UPDATE_INT_OCCURRED 0 0 CRTC_V_UPDATE_INT_CLEAR 8 8 mmCRTC3_CRTC_OVERSCAN_COLOR 0 0xd17 3 0 2 CRTC_OVERSCAN_COLOR_BLUE 0 9 CRTC_OVERSCAN_COLOR_GREEN 10 19 CRTC_OVERSCAN_COLOR_RED 20 29 mmCRTC3_CRTC_OVERSCAN_COLOR_EXT 0 0xd18 3 0 2 CRTC_OVERSCAN_COLOR_BLUE_EXT 0 1 CRTC_OVERSCAN_COLOR_GREEN_EXT 8 9 CRTC_OVERSCAN_COLOR_RED_EXT 16 17 mmCRTC3_CRTC_BLANK_DATA_COLOR 0 0xd19 3 0 2 CRTC_BLANK_DATA_COLOR_BLUE_CB 0 9 CRTC_BLANK_DATA_COLOR_GREEN_Y 10 19 CRTC_BLANK_DATA_COLOR_RED_CR 20 29 mmCRTC3_CRTC_BLANK_DATA_COLOR_EXT 0 0xd1a 3 0 2 CRTC_BLANK_DATA_COLOR_BLUE_CB_EXT 0 1 CRTC_BLANK_DATA_COLOR_GREEN_Y_EXT 8 9 CRTC_BLANK_DATA_COLOR_RED_CR_EXT 16 17 mmCRTC3_CRTC_BLACK_COLOR 0 0xd1b 3 0 2 CRTC_BLACK_COLOR_B_CB 0 9 CRTC_BLACK_COLOR_G_Y 10 19 CRTC_BLACK_COLOR_R_CR 20 29 mmCRTC3_CRTC_BLACK_COLOR_EXT 0 0xd1c 3 0 2 CRTC_BLACK_COLOR_B_CB_EXT 0 1 CRTC_BLACK_COLOR_G_Y_EXT 8 9 CRTC_BLACK_COLOR_R_CR_EXT 16 17 mmCRTC3_CRTC_VERTICAL_INTERRUPT0_POSITION 0 0xd1d 2 0 2 CRTC_VERTICAL_INTERRUPT0_LINE_START 0 13 CRTC_VERTICAL_INTERRUPT0_LINE_END 16 29 mmCRTC3_CRTC_VERTICAL_INTERRUPT0_CONTROL 0 0xd1e 6 0 2 CRTC_VERTICAL_INTERRUPT0_OUTPUT_POLARITY 4 4 CRTC_VERTICAL_INTERRUPT0_INT_ENABLE 8 8 CRTC_VERTICAL_INTERRUPT0_STATUS 12 12 CRTC_VERTICAL_INTERRUPT0_INT_STATUS 16 16 CRTC_VERTICAL_INTERRUPT0_CLEAR 20 20 CRTC_VERTICAL_INTERRUPT0_INT_TYPE 24 24 mmCRTC3_CRTC_VERTICAL_INTERRUPT1_POSITION 0 0xd1f 1 0 2 CRTC_VERTICAL_INTERRUPT1_LINE_START 0 13 mmCRTC3_CRTC_VERTICAL_INTERRUPT1_CONTROL 0 0xd20 5 0 2 CRTC_VERTICAL_INTERRUPT1_INT_ENABLE 8 8 CRTC_VERTICAL_INTERRUPT1_STATUS 12 12 CRTC_VERTICAL_INTERRUPT1_INT_STATUS 16 16 CRTC_VERTICAL_INTERRUPT1_CLEAR 20 20 CRTC_VERTICAL_INTERRUPT1_INT_TYPE 24 24 mmCRTC3_CRTC_VERTICAL_INTERRUPT2_POSITION 0 0xd21 1 0 2 CRTC_VERTICAL_INTERRUPT2_LINE_START 0 13 mmCRTC3_CRTC_VERTICAL_INTERRUPT2_CONTROL 0 0xd22 5 0 2 CRTC_VERTICAL_INTERRUPT2_INT_ENABLE 8 8 CRTC_VERTICAL_INTERRUPT2_STATUS 12 12 CRTC_VERTICAL_INTERRUPT2_INT_STATUS 16 16 CRTC_VERTICAL_INTERRUPT2_CLEAR 20 20 CRTC_VERTICAL_INTERRUPT2_INT_TYPE 24 24 mmCRTC3_CRTC_CRC_CNTL 0 0xd23 7 0 2 CRTC_CRC_EN 0 0 CRTC_CRC_CONT_EN 4 4 CRTC_CRC_STEREO_MODE 8 9 CRTC_CRC_INTERLACE_MODE 12 13 CRTC_CRC_USE_NEW_AND_REPEATED_PIXELS 16 16 CRTC_CRC0_SELECT 20 22 CRTC_CRC1_SELECT 24 26 mmCRTC3_CRTC_CRC0_WINDOWA_X_CONTROL 0 0xd24 2 0 2 CRTC_CRC0_WINDOWA_X_START 0 13 CRTC_CRC0_WINDOWA_X_END 16 29 mmCRTC3_CRTC_CRC0_WINDOWA_Y_CONTROL 0 0xd25 2 0 2 CRTC_CRC0_WINDOWA_Y_START 0 13 CRTC_CRC0_WINDOWA_Y_END 16 29 mmCRTC3_CRTC_CRC0_WINDOWB_X_CONTROL 0 0xd26 2 0 2 CRTC_CRC0_WINDOWB_X_START 0 13 CRTC_CRC0_WINDOWB_X_END 16 29 mmCRTC3_CRTC_CRC0_WINDOWB_Y_CONTROL 0 0xd27 2 0 2 CRTC_CRC0_WINDOWB_Y_START 0 13 CRTC_CRC0_WINDOWB_Y_END 16 29 mmCRTC3_CRTC_CRC0_DATA_RG 0 0xd28 2 0 2 CRC0_R_CR 0 15 CRC0_G_Y 16 31 mmCRTC3_CRTC_CRC0_DATA_B 0 0xd29 1 0 2 CRC0_B_CB 0 15 mmCRTC3_CRTC_CRC1_WINDOWA_X_CONTROL 0 0xd2a 2 0 2 CRTC_CRC1_WINDOWA_X_START 0 13 CRTC_CRC1_WINDOWA_X_END 16 29 mmCRTC3_CRTC_CRC1_WINDOWA_Y_CONTROL 0 0xd2b 2 0 2 CRTC_CRC1_WINDOWA_Y_START 0 13 CRTC_CRC1_WINDOWA_Y_END 16 29 mmCRTC3_CRTC_CRC1_WINDOWB_X_CONTROL 0 0xd2c 2 0 2 CRTC_CRC1_WINDOWB_X_START 0 13 CRTC_CRC1_WINDOWB_X_END 16 29 mmCRTC3_CRTC_CRC1_WINDOWB_Y_CONTROL 0 0xd2d 2 0 2 CRTC_CRC1_WINDOWB_Y_START 0 13 CRTC_CRC1_WINDOWB_Y_END 16 29 mmCRTC3_CRTC_CRC1_DATA_RG 0 0xd2e 2 0 2 CRC1_R_CR 0 15 CRC1_G_Y 16 31 mmCRTC3_CRTC_CRC1_DATA_B 0 0xd2f 1 0 2 CRC1_B_CB 0 15 mmCRTC3_CRTC_EXT_TIMING_SYNC_CONTROL 0 0xd30 11 0 2 CRTC_EXT_TIMING_SYNC_ENABLE 0 1 CRTC_EXT_TIMING_SYNC_HCOUNT_MODE_ENABLE 3 3 CRTC_EXT_TIMING_SYNC_JITTER_FILTERING_ENABLE 4 4 CRTC_EXT_TIMING_SYNC_JITTER_FILTERING_WINDOW 5 6 CRTC_EXT_TIMING_SYNC_WINDOW_ENABLE 8 8 CRTC_EXT_TIMING_SYNC_WINDOW_UPDATE 9 9 CRTC_EXT_TIMING_SYNC_VSYNC_POLARITY 12 12 CRTC_EXT_TIMING_SYNC_HSYNC_POLARITY 13 13 CRTC_EXT_TIMING_SYNC_INTERLACE_MODE 14 14 CRTC_EXT_TIMING_SYNC_MASTER_FRAME_RATE 24 26 CRTC_EXT_TIMING_SYNC_SLAVE_FRAME_RATE 28 30 mmCRTC3_CRTC_EXT_TIMING_SYNC_WINDOW_START 0 0xd31 2 0 2 CRTC_EXT_TIMING_SYNC_WINDOW_START_X 0 13 CRTC_EXT_TIMING_SYNC_WINDOW_START_Y 16 29 mmCRTC3_CRTC_EXT_TIMING_SYNC_WINDOW_END 0 0xd32 2 0 2 CRTC_EXT_TIMING_SYNC_WINDOW_END_X 0 13 CRTC_EXT_TIMING_SYNC_WINDOW_END_Y 16 29 mmCRTC3_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL 0 0xd33 6 0 2 CRTC_EXT_TIMING_SYNC_LOSS_INT_ENABLE 0 0 CRTC_EXT_TIMING_SYNC_LOSS_STATUS 4 4 CRTC_EXT_TIMING_SYNC_LOSS_INT_STATUS 8 8 CRTC_EXT_TIMING_SYNC_LOSS_CLEAR 16 16 CRTC_EXT_TIMING_SYNC_LOSS_INT_TYPE 20 20 CRTC_EXT_TIMING_SYNC_LOSS_FRAME_COUNT 29 31 mmCRTC3_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL 0 0xd34 5 0 2 CRTC_EXT_TIMING_SYNC_INT_ENABLE 0 0 CRTC_EXT_TIMING_SYNC_STATUS 4 4 CRTC_EXT_TIMING_SYNC_INT_STATUS 8 8 CRTC_EXT_TIMING_SYNC_CLEAR 16 16 CRTC_EXT_TIMING_SYNC_INT_TYPE 20 20 mmCRTC3_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL 0 0xd35 5 0 2 CRTC_EXT_TIMING_SYNC_SIGNAL_INT_ENABLE 0 0 CRTC_EXT_TIMING_SYNC_SIGNAL_STATUS 4 4 CRTC_EXT_TIMING_SYNC_SIGNAL_INT_STATUS 8 8 CRTC_EXT_TIMING_SYNC_SIGNAL_CLEAR 16 16 CRTC_EXT_TIMING_SYNC_SIGNAL_INT_TYPE 20 20 mmCRTC3_CRTC_STATIC_SCREEN_CONTROL 0 0xd36 9 0 2 CRTC_STATIC_SCREEN_EVENT_MASK 0 15 CRTC_STATIC_SCREEN_FRAME_COUNT 16 23 CRTC_CPU_SS_INT_ENABLE 24 24 CRTC_SS_STATUS 25 25 CRTC_CPU_SS_INT_STATUS 26 26 CRTC_CPU_SS_INT_CLEAR 27 27 CRTC_CPU_SS_INT_TYPE 28 28 CRTC_STATIC_SCREEN_OVERRIDE 30 30 CRTC_STATIC_SCREEN_OVERRIDE_VALUE 31 31 mmCRTC3_CRTC_3D_STRUCTURE_CONTROL 0 0xd37 7 0 2 CRTC_3D_STRUCTURE_EN 0 0 CRTC_3D_STRUCTURE_EN_DB 4 4 CRTC_3D_STRUCTURE_V_UPDATE_MODE 8 9 CRTC_3D_STRUCTURE_STEREO_SEL_OVR 12 12 CRTC_3D_STRUCTURE_F_COUNT_RESET 16 16 CRTC_3D_STRUCTURE_F_COUNT_RESET_PENDING 17 17 CRTC_3D_STRUCTURE_F_COUNT 18 19 mmCRTC3_CRTC_GSL_VSYNC_GAP 0 0xd38 8 0 2 CRTC_GSL_VSYNC_GAP_LIMIT 0 7 CRTC_GSL_VSYNC_GAP_DELAY 8 15 CRTC_GSL_VSYNC_GAP_SOURCE_SEL 16 16 CRTC_GSL_VSYNC_GAP_MODE 17 18 CRTC_GSL_VSYNC_GAP_CLEAR 19 19 CRTC_GSL_VSYNC_GAP_OCCURRED 20 20 CRTC_GSL_VSYNC_GAP_MASTER_FASTER 23 23 CRTC_GSL_VSYNC_GAP 24 31 mmCRTC3_CRTC_GSL_WINDOW 0 0xd39 2 0 2 CRTC_GSL_WINDOW_START 0 13 CRTC_GSL_WINDOW_END 16 29 mmCRTC3_CRTC_GSL_CONTROL 0 0xd3a 3 0 2 CRTC_GSL_CHECK_LINE_NUM 0 13 CRTC_GSL_FORCE_DELAY 16 20 CRTC_GSL_CHECK_ALL_FIELDS 28 28 mmCRTC3_CRTC_RANGE_TIMING_INT_STATUS 0 0xd3d 5 0 2 CRTC_RANGE_TIMING_UPDATE_OCCURRED 0 0 CRTC_RANGE_TIMING_UPDATE_OCCURRED_INT 4 4 CRTC_RANGE_TIMING_UPDATE_OCCURRED_CLEAR 8 8 CRTC_RANGE_TIMING_UPDATE_OCCURRED_INT_MSK 12 12 CRTC_RANGE_TIMING_UPDATE_OCCURRED_INT_TYPE 16 16 mmCRTC3_CRTC_DRR_CONTROL 0 0xd3e 4 0 2 CRTC_XDMA_PREFETCH_DELAY 0 13 CRTC_V_TOTAL_LAST_USED_BY_DRR 14 27 CRTC_SET_V_TOTAL_MIN_AUTO_DIS 28 28 CRTC_DRR_MODE_DBUF_UPDATE_MODE 29 30 mmFMT3_FMT_CLAMP_COMPONENT_R 0 0xd42 2 0 2 FMT_CLAMP_LOWER_R 0 15 FMT_CLAMP_UPPER_R 16 31 mmFMT3_FMT_CLAMP_COMPONENT_G 0 0xd43 2 0 2 FMT_CLAMP_LOWER_G 0 15 FMT_CLAMP_UPPER_G 16 31 mmFMT3_FMT_CLAMP_COMPONENT_B 0 0xd44 2 0 2 FMT_CLAMP_LOWER_B 0 15 FMT_CLAMP_UPPER_B 16 31 mmFMT3_FMT_DYNAMIC_EXP_CNTL 0 0xd45 2 0 2 FMT_DYNAMIC_EXP_EN 0 0 FMT_DYNAMIC_EXP_MODE 4 4 mmFMT3_FMT_CONTROL 0 0xd46 11 0 2 FMT_STEREOSYNC_OVERRIDE 0 0 FMT_STEREOSYNC_OVR_POL 4 4 FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX 8 11 FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP 12 13 FMT_PIXEL_ENCODING 16 17 FMT_SUBSAMPLING_MODE 18 19 FMT_SUBSAMPLING_ORDER 20 20 FMT_CBCR_BIT_REDUCTION_BYPASS 21 21 FMT_SRC_SELECT 24 26 FMT_420_PIXEL_PHASE_LOCKED 30 30 FMT_420_PIXEL_PHASE_LOCKED_CLEAR 31 31 mmFMT3_FMT_BIT_DEPTH_CONTROL 0 0xd47 17 0 2 FMT_TRUNCATE_EN 0 0 FMT_TRUNCATE_MODE 1 1 FMT_TRUNCATE_DEPTH 4 5 FMT_SPATIAL_DITHER_EN 8 8 FMT_SPATIAL_DITHER_MODE 9 10 FMT_SPATIAL_DITHER_DEPTH 11 12 FMT_FRAME_RANDOM_ENABLE 13 13 FMT_RGB_RANDOM_ENABLE 14 14 FMT_HIGHPASS_RANDOM_ENABLE 15 15 FMT_TEMPORAL_DITHER_EN 16 16 FMT_TEMPORAL_DITHER_DEPTH 17 18 FMT_TEMPORAL_DITHER_OFFSET 21 22 FMT_TEMPORAL_LEVEL 24 24 FMT_TEMPORAL_DITHER_RESET 25 25 FMT_25FRC_SEL 26 27 FMT_50FRC_SEL 28 29 FMT_75FRC_SEL 30 31 mmFMT3_FMT_DITHER_RAND_R_SEED 0 0xd48 2 0 2 FMT_RAND_R_SEED 0 7 FMT_OFFSET_R_CR 16 31 mmFMT3_FMT_DITHER_RAND_G_SEED 0 0xd49 2 0 2 FMT_RAND_G_SEED 0 7 FMT_OFFSET_G_Y 16 31 mmFMT3_FMT_DITHER_RAND_B_SEED 0 0xd4a 2 0 2 FMT_RAND_B_SEED 0 7 FMT_OFFSET_B_CB 16 31 mmFMT3_FMT_CLAMP_CNTL 0 0xd4e 2 0 2 FMT_CLAMP_DATA_EN 0 0 FMT_CLAMP_COLOR_FORMAT 16 18 mmFMT3_FMT_CRC_CNTL 0 0xd4f 11 0 2 FMT_CRC_EN 0 0 FMT_DTMTEST_CRC_EN 1 1 FMT_CRC_CONT_EN 4 4 FMT_ONE_SHOT_CRC_PENDING 5 5 FMT_CRC_INCLUDE_OVERSCAN 6 6 FMT_CRC_ONLY_BLANKB 8 8 FMT_CRC_PSR_MODE_ENABLE 9 9 FMT_CRC_INTERLACE_MODE 12 13 FMT_CRC_USE_NEW_AND_REPEATED_PIXELS 16 16 FMT_CRC_EVEN_ODD_PIX_ENABLE 20 20 FMT_CRC_EVEN_ODD_PIX_SELECT 24 24 mmFMT3_FMT_CRC_SIG_RED_GREEN_MASK 0 0xd50 2 0 2 FMT_CRC_SIG_RED_MASK 0 15 FMT_CRC_SIG_GREEN_MASK 16 31 mmFMT3_FMT_CRC_SIG_BLUE_CONTROL_MASK 0 0xd51 2 0 2 FMT_CRC_SIG_BLUE_MASK 0 15 FMT_CRC_SIG_CONTROL_MASK 16 31 mmFMT3_FMT_CRC_SIG_RED_GREEN 0 0xd52 2 0 2 FMT_CRC_SIG_RED 0 15 FMT_CRC_SIG_GREEN 16 31 mmFMT3_FMT_CRC_SIG_BLUE_CONTROL 0 0xd53 2 0 2 FMT_CRC_SIG_BLUE 0 15 FMT_CRC_SIG_CONTROL 16 31 mmFMT3_FMT_SIDE_BY_SIDE_STEREO_CONTROL 0 0xd54 1 0 2 FMT_SIDE_BY_SIDE_STEREO_ACTIVE_WIDTH 0 12 mmFMT3_FMT_420_HBLANK_EARLY_START 0 0xd55 1 0 2 FMT_420_HBLANK_EARLY_START 0 11 mmDCP4_GRPH_ENABLE 0 0xd5a 2 0 2 GRPH_ENABLE 0 0 GRPH_KEYER_ALPHA_SEL 1 1 mmDCP4_GRPH_CONTROL 0 0xd5b 12 0 2 GRPH_DEPTH 0 1 GRPH_SE_ENABLE 2 2 GRPH_Z 4 5 GRPH_DIM_TYPE 6 7 GRPH_FORMAT 8 10 GRPH_NUM_BANKS 12 14 GRPH_ADDRESS_TRANSLATION_ENABLE 16 16 GRPH_PRIVILEGED_ACCESS_ENABLE 17 17 GRPH_NUM_SHADER_ENGINES 18 19 GRPH_SW_MODE 20 24 GRPH_NUM_PIPES 28 30 GRPH_COLOR_EXPANSION_MODE 31 31 mmDCP4_GRPH_LUT_10BIT_BYPASS 0 0xd5c 2 0 2 GRPH_LUT_10BIT_BYPASS_EN 8 8 GRPH_LUT_10BIT_BYPASS_DBL_BUF_EN 16 16 mmDCP4_GRPH_SWAP_CNTL 0 0xd5d 5 0 2 GRPH_ENDIAN_SWAP 0 1 GRPH_RED_CROSSBAR 4 5 GRPH_GREEN_CROSSBAR 6 7 GRPH_BLUE_CROSSBAR 8 9 GRPH_ALPHA_CROSSBAR 10 11 mmDCP4_GRPH_PRIMARY_SURFACE_ADDRESS 0 0xd5e 2 0 2 GRPH_PRIMARY_DFQ_ENABLE 0 0 GRPH_PRIMARY_SURFACE_ADDRESS 8 31 mmDCP4_GRPH_SECONDARY_SURFACE_ADDRESS 0 0xd5f 2 0 2 GRPH_SECONDARY_DFQ_ENABLE 0 0 GRPH_SECONDARY_SURFACE_ADDRESS 8 31 mmDCP4_GRPH_PITCH 0 0xd60 1 0 2 GRPH_PITCH 0 14 mmDCP4_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH 0 0xd61 1 0 2 GRPH_PRIMARY_SURFACE_ADDRESS_HIGH 0 7 mmDCP4_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH 0 0xd62 1 0 2 GRPH_SECONDARY_SURFACE_ADDRESS_HIGH 0 7 mmDCP4_GRPH_SURFACE_OFFSET_X 0 0xd63 1 0 2 GRPH_SURFACE_OFFSET_X 0 13 mmDCP4_GRPH_SURFACE_OFFSET_Y 0 0xd64 1 0 2 GRPH_SURFACE_OFFSET_Y 0 13 mmDCP4_GRPH_X_START 0 0xd65 1 0 2 GRPH_X_START 0 13 mmDCP4_GRPH_Y_START 0 0xd66 1 0 2 GRPH_Y_START 0 13 mmDCP4_GRPH_X_END 0 0xd67 1 0 2 GRPH_X_END 0 14 mmDCP4_GRPH_Y_END 0 0xd68 1 0 2 GRPH_Y_END 0 14 mmDCP4_INPUT_GAMMA_CONTROL 0 0xd69 1 0 2 GRPH_INPUT_GAMMA_MODE 0 0 mmDCP4_GRPH_UPDATE 0 0xd6a 11 0 2 GRPH_MODE_UPDATE_PENDING 0 0 GRPH_MODE_UPDATE_TAKEN 1 1 GRPH_SURFACE_UPDATE_PENDING 2 2 GRPH_SURFACE_UPDATE_TAKEN 3 3 GRPH_XDMA_FLIP_TYPE_CLEAR 8 8 GRPH_XDMA_DRR_MODE_ENABLE 9 9 GRPH_XDMA_MULTIFLIP_ENABLE 10 10 GRPH_UPDATE_LOCK 16 16 GRPH_SURFACE_IGNORE_UPDATE_LOCK 20 20 GRPH_MODE_DISABLE_MULTIPLE_UPDATE 24 24 GRPH_SURFACE_DISABLE_MULTIPLE_UPDATE 28 28 mmDCP4_GRPH_FLIP_CONTROL 0 0xd6b 4 0 2 GRPH_SURFACE_UPDATE_H_RETRACE_EN 0 0 GRPH_XDMA_SUPER_AA_EN 1 1 GRPH_SURFACE_UPDATE_IMMEDIATE_EN 4 4 GRPH_SURFACE_UPDATE_PENDING_MODE 5 5 mmDCP4_GRPH_SURFACE_ADDRESS_INUSE 0 0xd6c 1 0 2 GRPH_SURFACE_ADDRESS_INUSE 8 31 mmDCP4_GRPH_DFQ_CONTROL 0 0xd6d 3 0 2 GRPH_DFQ_RESET 0 0 GRPH_DFQ_SIZE 4 6 GRPH_DFQ_MIN_FREE_ENTRIES 8 10 mmDCP4_GRPH_DFQ_STATUS 0 0xd6e 4 0 2 GRPH_PRIMARY_DFQ_NUM_ENTRIES 0 3 GRPH_SECONDARY_DFQ_NUM_ENTRIES 4 7 GRPH_DFQ_RESET_FLAG 8 8 GRPH_DFQ_RESET_ACK 9 9 mmDCP4_GRPH_INTERRUPT_STATUS 0 0xd6f 2 0 2 GRPH_PFLIP_INT_OCCURRED 0 0 GRPH_PFLIP_INT_CLEAR 8 8 mmDCP4_GRPH_INTERRUPT_CONTROL 0 0xd70 2 0 2 GRPH_PFLIP_INT_MASK 0 0 GRPH_PFLIP_INT_TYPE 8 8 mmDCP4_GRPH_SURFACE_ADDRESS_HIGH_INUSE 0 0xd71 1 0 2 GRPH_SURFACE_ADDRESS_HIGH_INUSE 0 7 mmDCP4_GRPH_COMPRESS_SURFACE_ADDRESS 0 0xd72 1 0 2 GRPH_COMPRESS_SURFACE_ADDRESS 8 31 mmDCP4_GRPH_COMPRESS_PITCH 0 0xd73 1 0 2 GRPH_COMPRESS_PITCH 6 16 mmDCP4_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH 0 0xd74 1 0 2 GRPH_COMPRESS_SURFACE_ADDRESS_HIGH 0 7 mmDCP4_GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT 0 0xd75 1 0 2 GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT 0 7 mmDCP4_PRESCALE_GRPH_CONTROL 0 0xd76 5 0 2 GRPH_PRESCALE_SELECT 0 0 GRPH_PRESCALE_R_SIGN 1 1 GRPH_PRESCALE_G_SIGN 2 2 GRPH_PRESCALE_B_SIGN 3 3 GRPH_PRESCALE_BYPASS 4 4 mmDCP4_PRESCALE_VALUES_GRPH_R 0 0xd77 2 0 2 GRPH_PRESCALE_BIAS_R 0 15 GRPH_PRESCALE_SCALE_R 16 31 mmDCP4_PRESCALE_VALUES_GRPH_G 0 0xd78 2 0 2 GRPH_PRESCALE_BIAS_G 0 15 GRPH_PRESCALE_SCALE_G 16 31 mmDCP4_PRESCALE_VALUES_GRPH_B 0 0xd79 2 0 2 GRPH_PRESCALE_BIAS_B 0 15 GRPH_PRESCALE_SCALE_B 16 31 mmDCP4_INPUT_CSC_CONTROL 0 0xd7a 1 0 2 INPUT_CSC_GRPH_MODE 0 1 mmDCP4_INPUT_CSC_C11_C12 0 0xd7b 2 0 2 INPUT_CSC_C11 0 15 INPUT_CSC_C12 16 31 mmDCP4_INPUT_CSC_C13_C14 0 0xd7c 2 0 2 INPUT_CSC_C13 0 15 INPUT_CSC_C14 16 31 mmDCP4_INPUT_CSC_C21_C22 0 0xd7d 2 0 2 INPUT_CSC_C21 0 15 INPUT_CSC_C22 16 31 mmDCP4_INPUT_CSC_C23_C24 0 0xd7e 2 0 2 INPUT_CSC_C23 0 15 INPUT_CSC_C24 16 31 mmDCP4_INPUT_CSC_C31_C32 0 0xd7f 2 0 2 INPUT_CSC_C31 0 15 INPUT_CSC_C32 16 31 mmDCP4_INPUT_CSC_C33_C34 0 0xd80 2 0 2 INPUT_CSC_C33 0 15 INPUT_CSC_C34 16 31 mmDCP4_OUTPUT_CSC_CONTROL 0 0xd81 1 0 2 OUTPUT_CSC_GRPH_MODE 0 2 mmDCP4_OUTPUT_CSC_C11_C12 0 0xd82 2 0 2 OUTPUT_CSC_C11 0 15 OUTPUT_CSC_C12 16 31 mmDCP4_OUTPUT_CSC_C13_C14 0 0xd83 2 0 2 OUTPUT_CSC_C13 0 15 OUTPUT_CSC_C14 16 31 mmDCP4_OUTPUT_CSC_C21_C22 0 0xd84 2 0 2 OUTPUT_CSC_C21 0 15 OUTPUT_CSC_C22 16 31 mmDCP4_OUTPUT_CSC_C23_C24 0 0xd85 2 0 2 OUTPUT_CSC_C23 0 15 OUTPUT_CSC_C24 16 31 mmDCP4_OUTPUT_CSC_C31_C32 0 0xd86 2 0 2 OUTPUT_CSC_C31 0 15 OUTPUT_CSC_C32 16 31 mmDCP4_OUTPUT_CSC_C33_C34 0 0xd87 2 0 2 OUTPUT_CSC_C33 0 15 OUTPUT_CSC_C34 16 31 mmDCP4_COMM_MATRIXA_TRANS_C11_C12 0 0xd88 2 0 2 COMM_MATRIXA_TRANS_C11 0 15 COMM_MATRIXA_TRANS_C12 16 31 mmDCP4_COMM_MATRIXA_TRANS_C13_C14 0 0xd89 2 0 2 COMM_MATRIXA_TRANS_C13 0 15 COMM_MATRIXA_TRANS_C14 16 31 mmDCP4_COMM_MATRIXA_TRANS_C21_C22 0 0xd8a 2 0 2 COMM_MATRIXA_TRANS_C21 0 15 COMM_MATRIXA_TRANS_C22 16 31 mmDCP4_COMM_MATRIXA_TRANS_C23_C24 0 0xd8b 2 0 2 COMM_MATRIXA_TRANS_C23 0 15 COMM_MATRIXA_TRANS_C24 16 31 mmDCP4_COMM_MATRIXA_TRANS_C31_C32 0 0xd8c 2 0 2 COMM_MATRIXA_TRANS_C31 0 15 COMM_MATRIXA_TRANS_C32 16 31 mmDCP4_COMM_MATRIXA_TRANS_C33_C34 0 0xd8d 2 0 2 COMM_MATRIXA_TRANS_C33 0 15 COMM_MATRIXA_TRANS_C34 16 31 mmDCP4_COMM_MATRIXB_TRANS_C11_C12 0 0xd8e 2 0 2 COMM_MATRIXB_TRANS_C11 0 15 COMM_MATRIXB_TRANS_C12 16 31 mmDCP4_COMM_MATRIXB_TRANS_C13_C14 0 0xd8f 2 0 2 COMM_MATRIXB_TRANS_C13 0 15 COMM_MATRIXB_TRANS_C14 16 31 mmDCP4_COMM_MATRIXB_TRANS_C21_C22 0 0xd90 2 0 2 COMM_MATRIXB_TRANS_C21 0 15 COMM_MATRIXB_TRANS_C22 16 31 mmDCP4_COMM_MATRIXB_TRANS_C23_C24 0 0xd91 2 0 2 COMM_MATRIXB_TRANS_C23 0 15 COMM_MATRIXB_TRANS_C24 16 31 mmDCP4_COMM_MATRIXB_TRANS_C31_C32 0 0xd92 2 0 2 COMM_MATRIXB_TRANS_C31 0 15 COMM_MATRIXB_TRANS_C32 16 31 mmDCP4_COMM_MATRIXB_TRANS_C33_C34 0 0xd93 2 0 2 COMM_MATRIXB_TRANS_C33 0 15 COMM_MATRIXB_TRANS_C34 16 31 mmDCP4_DENORM_CONTROL 0 0xd94 2 0 2 DENORM_MODE 0 2 DENORM_14BIT_OUT 4 4 mmDCP4_OUT_ROUND_CONTROL 0 0xd95 1 0 2 OUT_ROUND_TRUNC_MODE 0 3 mmDCP4_OUT_CLAMP_CONTROL_R_CR 0 0xd96 2 0 2 OUT_CLAMP_MAX_R_CR 0 13 OUT_CLAMP_MIN_R_CR 16 29 mmDCP4_OUT_CLAMP_CONTROL_G_Y 0 0xd97 2 0 2 OUT_CLAMP_MAX_G_Y 0 13 OUT_CLAMP_MIN_G_Y 16 29 mmDCP4_OUT_CLAMP_CONTROL_B_CB 0 0xd98 2 0 2 OUT_CLAMP_MAX_B_CB 0 13 OUT_CLAMP_MIN_B_CB 16 29 mmDCP4_KEY_CONTROL 0 0xd99 1 0 2 KEY_MODE 1 2 mmDCP4_KEY_RANGE_ALPHA 0 0xd9a 2 0 2 KEY_ALPHA_LOW 0 15 KEY_ALPHA_HIGH 16 31 mmDCP4_KEY_RANGE_RED 0 0xd9b 2 0 2 KEY_RED_LOW 0 15 KEY_RED_HIGH 16 31 mmDCP4_KEY_RANGE_GREEN 0 0xd9c 2 0 2 KEY_GREEN_LOW 0 15 KEY_GREEN_HIGH 16 31 mmDCP4_KEY_RANGE_BLUE 0 0xd9d 2 0 2 KEY_BLUE_LOW 0 15 KEY_BLUE_HIGH 16 31 mmDCP4_DEGAMMA_CONTROL 0 0xd9e 3 0 2 GRPH_DEGAMMA_MODE 0 1 CURSOR2_DEGAMMA_MODE 8 9 CURSOR_DEGAMMA_MODE 12 13 mmDCP4_GAMUT_REMAP_CONTROL 0 0xd9f 1 0 2 GRPH_GAMUT_REMAP_MODE 0 1 mmDCP4_GAMUT_REMAP_C11_C12 0 0xda0 2 0 2 GAMUT_REMAP_C11 0 15 GAMUT_REMAP_C12 16 31 mmDCP4_GAMUT_REMAP_C13_C14 0 0xda1 2 0 2 GAMUT_REMAP_C13 0 15 GAMUT_REMAP_C14 16 31 mmDCP4_GAMUT_REMAP_C21_C22 0 0xda2 2 0 2 GAMUT_REMAP_C21 0 15 GAMUT_REMAP_C22 16 31 mmDCP4_GAMUT_REMAP_C23_C24 0 0xda3 2 0 2 GAMUT_REMAP_C23 0 15 GAMUT_REMAP_C24 16 31 mmDCP4_GAMUT_REMAP_C31_C32 0 0xda4 2 0 2 GAMUT_REMAP_C31 0 15 GAMUT_REMAP_C32 16 31 mmDCP4_GAMUT_REMAP_C33_C34 0 0xda5 2 0 2 GAMUT_REMAP_C33 0 15 GAMUT_REMAP_C34 16 31 mmDCP4_DCP_SPATIAL_DITHER_CNTL 0 0xda6 6 0 2 DCP_SPATIAL_DITHER_EN 0 0 DCP_SPATIAL_DITHER_MODE 4 5 DCP_SPATIAL_DITHER_DEPTH 6 7 DCP_FRAME_RANDOM_ENABLE 8 8 DCP_RGB_RANDOM_ENABLE 9 9 DCP_HIGHPASS_RANDOM_ENABLE 10 10 mmDCP4_DCP_RANDOM_SEEDS 0 0xda7 3 0 2 DCP_RAND_R_SEED 0 7 DCP_RAND_G_SEED 8 15 DCP_RAND_B_SEED 16 23 mmDCP4_DCP_FP_CONVERTED_FIELD 0 0xda8 2 0 2 DCP_FP_CONVERTED_FIELD_DATA 0 17 DCP_FP_CONVERTED_FIELD_INDEX 20 26 mmDCP4_CUR_CONTROL 0 0xda9 8 0 2 CURSOR_EN 0 0 CUR_INV_TRANS_CLAMP 4 4 CURSOR_MODE 8 9 CURSOR_MAX_OUTSTANDING_GROUP_NUM 11 11 CURSOR_BUSY_START_LINE_POSITION 12 15 CURSOR_2X_MAGNIFY 16 16 CURSOR_FORCE_MC_ON 20 20 CURSOR_URGENT_CONTROL 24 26 mmDCP4_CUR_SURFACE_ADDRESS 0 0xdaa 1 0 2 CURSOR_SURFACE_ADDRESS 0 31 mmDCP4_CUR_SIZE 0 0xdab 2 0 2 CURSOR_HEIGHT 0 6 CURSOR_WIDTH 16 22 mmDCP4_CUR_SURFACE_ADDRESS_HIGH 0 0xdac 1 0 2 CURSOR_SURFACE_ADDRESS_HIGH 0 7 mmDCP4_CUR_POSITION 0 0xdad 2 0 2 CURSOR_Y_POSITION 0 13 CURSOR_X_POSITION 16 29 mmDCP4_CUR_HOT_SPOT 0 0xdae 2 0 2 CURSOR_HOT_SPOT_Y 0 6 CURSOR_HOT_SPOT_X 16 22 mmDCP4_CUR_COLOR1 0 0xdaf 3 0 2 CUR_COLOR1_BLUE 0 7 CUR_COLOR1_GREEN 8 15 CUR_COLOR1_RED 16 23 mmDCP4_CUR_COLOR2 0 0xdb0 3 0 2 CUR_COLOR2_BLUE 0 7 CUR_COLOR2_GREEN 8 15 CUR_COLOR2_RED 16 23 mmDCP4_CUR_UPDATE 0 0xdb1 5 0 2 CURSOR_UPDATE_PENDING 0 0 CURSOR_UPDATE_TAKEN 1 1 CURSOR_UPDATE_LOCK 16 16 CURSOR_DISABLE_MULTIPLE_UPDATE 24 24 CURSOR_UPDATE_STEREO_MODE 25 26 mmDCP4_CUR_REQUEST_FILTER_CNTL 0 0xdbb 1 0 2 CUR_REQUEST_FILTER_DIS 0 0 mmDCP4_CUR_STEREO_CONTROL 0 0xdbc 3 0 2 CURSOR_STEREO_EN 0 0 CURSOR_PRIMARY_OFFSET 4 13 CURSOR_SECONDARY_OFFSET 16 25 mmDCP4_DC_LUT_RW_MODE 0 0xdbe 3 0 2 DC_LUT_RW_MODE 0 0 DC_LUT_ERROR 16 16 DC_LUT_ERROR_RST 17 17 mmDCP4_DC_LUT_RW_INDEX 0 0xdbf 1 0 2 DC_LUT_RW_INDEX 0 7 mmDCP4_DC_LUT_SEQ_COLOR 0 0xdc0 1 0 2 DC_LUT_SEQ_COLOR 0 15 mmDCP4_DC_LUT_PWL_DATA 0 0xdc1 2 0 2 DC_LUT_BASE 0 15 DC_LUT_DELTA 16 31 mmDCP4_DC_LUT_30_COLOR 0 0xdc2 3 0 2 DC_LUT_COLOR_10_BLUE 0 9 DC_LUT_COLOR_10_GREEN 10 19 DC_LUT_COLOR_10_RED 20 29 mmDCP4_DC_LUT_VGA_ACCESS_ENABLE 0 0xdc3 1 0 2 DC_LUT_VGA_ACCESS_ENABLE 0 0 mmDCP4_DC_LUT_WRITE_EN_MASK 0 0xdc4 1 0 2 DC_LUT_WRITE_EN_MASK 0 2 mmDCP4_DC_LUT_AUTOFILL 0 0xdc5 2 0 2 DC_LUT_AUTOFILL 0 0 DC_LUT_AUTOFILL_DONE 1 1 mmDCP4_DC_LUT_CONTROL 0 0xdc6 12 0 2 DC_LUT_INC_B 0 3 DC_LUT_DATA_B_SIGNED_EN 4 4 DC_LUT_DATA_B_FLOAT_POINT_EN 5 5 DC_LUT_DATA_B_FORMAT 6 7 DC_LUT_INC_G 8 11 DC_LUT_DATA_G_SIGNED_EN 12 12 DC_LUT_DATA_G_FLOAT_POINT_EN 13 13 DC_LUT_DATA_G_FORMAT 14 15 DC_LUT_INC_R 16 19 DC_LUT_DATA_R_SIGNED_EN 20 20 DC_LUT_DATA_R_FLOAT_POINT_EN 21 21 DC_LUT_DATA_R_FORMAT 22 23 mmDCP4_DC_LUT_BLACK_OFFSET_BLUE 0 0xdc7 1 0 2 DC_LUT_BLACK_OFFSET_BLUE 0 15 mmDCP4_DC_LUT_BLACK_OFFSET_GREEN 0 0xdc8 1 0 2 DC_LUT_BLACK_OFFSET_GREEN 0 15 mmDCP4_DC_LUT_BLACK_OFFSET_RED 0 0xdc9 1 0 2 DC_LUT_BLACK_OFFSET_RED 0 15 mmDCP4_DC_LUT_WHITE_OFFSET_BLUE 0 0xdca 1 0 2 DC_LUT_WHITE_OFFSET_BLUE 0 15 mmDCP4_DC_LUT_WHITE_OFFSET_GREEN 0 0xdcb 1 0 2 DC_LUT_WHITE_OFFSET_GREEN 0 15 mmDCP4_DC_LUT_WHITE_OFFSET_RED 0 0xdcc 1 0 2 DC_LUT_WHITE_OFFSET_RED 0 15 mmDCP4_DCP_CRC_CONTROL 0 0xdcd 3 0 2 DCP_CRC_ENABLE 0 0 DCP_CRC_SOURCE_SEL 2 4 DCP_CRC_LINE_SEL 8 9 mmDCP4_DCP_CRC_MASK 0 0xdce 1 0 2 DCP_CRC_MASK 0 31 mmDCP4_DCP_CRC_CURRENT 0 0xdcf 1 0 2 DCP_CRC_CURRENT 0 31 mmDCP4_DVMM_PTE_CONTROL 0 0xdd0 6 0 2 DVMM_USE_SINGLE_PTE 0 0 DVMM_PAGE_WIDTH 1 4 DVMM_PAGE_HEIGHT 5 8 DVMM_MIN_PTE_BEFORE_FLIP 9 18 DVMM_PTE_BUFFER_MODE0 20 20 DVMM_PTE_BUFFER_MODE1 21 21 mmDCP4_DCP_CRC_LAST 0 0xdd1 1 0 2 DCP_CRC_LAST 0 31 mmDCP4_DVMM_PTE_ARB_CONTROL 0 0xdd2 2 0 2 DVMM_PTE_REQ_PER_CHUNK 0 5 DVMM_MAX_PTE_REQ_OUTSTANDING 8 15 mmDCP4_GRPH_FLIP_RATE_CNTL 0 0xdd4 2 0 2 GRPH_FLIP_RATE 0 2 GRPH_FLIP_RATE_ENABLE 3 3 mmDCP4_DCP_GSL_CONTROL 0 0xdd5 11 0 2 DCP_GSL0_EN 0 0 DCP_GSL1_EN 1 1 DCP_GSL2_EN 2 2 DCP_GSL_HSYNC_FLIP_FORCE_DELAY 4 19 DCP_GSL_MASTER_EN 20 20 DCP_GSL_XDMA_GROUP 21 22 DCP_GSL_XDMA_GROUP_UNDERFLOW_EN 23 23 DCP_GSL_SYNC_SOURCE 24 25 DCP_GSL_USE_CHECKPOINT_WINDOW_IN_VSYNC 26 26 DCP_GSL_DELAY_SURFACE_UPDATE_PENDING 27 27 DCP_GSL_HSYNC_FLIP_CHECK_DELAY 28 31 mmDCP4_DCP_LB_DATA_GAP_BETWEEN_CHUNK 0 0xdd6 2 0 2 DCP_LB_GAP_BETWEEN_CHUNK_20BPP 0 3 DCP_LB_GAP_BETWEEN_CHUNK_30BPP 4 8 mmDCP4_GRPH_STEREOSYNC_FLIP 0 0xddc 5 0 2 GRPH_STEREOSYNC_FLIP_EN 0 0 GRPH_STEREOSYNC_FLIP_MODE 8 9 GRPH_PRIMARY_SURFACE_PENDING 16 16 GRPH_SECONDARY_SURFACE_PENDING 17 17 GRPH_STEREOSYNC_SELECT_DISABLE 28 28 mmDCP4_HW_ROTATION 0 0xdde 1 0 2 GRPH_ROTATION_ANGLE 0 2 mmDCP4_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL 0 0xddf 3 0 2 GRPH_XDMA_CACHE_UNDERFLOW_CNT_EN 0 0 GRPH_XDMA_CACHE_UNDERFLOW_CNT_MODE 1 1 GRPH_XDMA_CACHE_UNDERFLOW_FRAME_CNT 4 16 mmDCP4_REGAMMA_CONTROL 0 0xde0 1 0 2 GRPH_REGAMMA_MODE 0 2 mmDCP4_REGAMMA_LUT_INDEX 0 0xde1 1 0 2 REGAMMA_LUT_INDEX 0 8 mmDCP4_REGAMMA_LUT_DATA 0 0xde2 1 0 2 REGAMMA_LUT_DATA 0 18 mmDCP4_REGAMMA_LUT_WRITE_EN_MASK 0 0xde3 1 0 2 REGAMMA_LUT_WRITE_EN_MASK 0 2 mmDCP4_REGAMMA_CNTLA_START_CNTL 0 0xde4 2 0 2 REGAMMA_CNTLA_EXP_REGION_START 0 17 REGAMMA_CNTLA_EXP_REGION_START_SEGMENT 20 26 mmDCP4_REGAMMA_CNTLA_SLOPE_CNTL 0 0xde5 1 0 2 REGAMMA_CNTLA_EXP_REGION_LINEAR_SLOPE 0 17 mmDCP4_REGAMMA_CNTLA_END_CNTL1 0 0xde6 1 0 2 REGAMMA_CNTLA_EXP_REGION_END 0 15 mmDCP4_REGAMMA_CNTLA_END_CNTL2 0 0xde7 2 0 2 REGAMMA_CNTLA_EXP_REGION_END_SLOPE 0 15 REGAMMA_CNTLA_EXP_REGION_END_BASE 16 31 mmDCP4_REGAMMA_CNTLA_REGION_0_1 0 0xde8 4 0 2 REGAMMA_CNTLA_EXP_REGION0_LUT_OFFSET 0 8 REGAMMA_CNTLA_EXP_REGION0_NUM_SEGMENTS 12 14 REGAMMA_CNTLA_EXP_REGION1_LUT_OFFSET 16 24 REGAMMA_CNTLA_EXP_REGION1_NUM_SEGMENTS 28 30 mmDCP4_REGAMMA_CNTLA_REGION_2_3 0 0xde9 4 0 2 REGAMMA_CNTLA_EXP_REGION2_LUT_OFFSET 0 8 REGAMMA_CNTLA_EXP_REGION2_NUM_SEGMENTS 12 14 REGAMMA_CNTLA_EXP_REGION3_LUT_OFFSET 16 24 REGAMMA_CNTLA_EXP_REGION3_NUM_SEGMENTS 28 30 mmDCP4_REGAMMA_CNTLA_REGION_4_5 0 0xdea 4 0 2 REGAMMA_CNTLA_EXP_REGION4_LUT_OFFSET 0 8 REGAMMA_CNTLA_EXP_REGION4_NUM_SEGMENTS 12 14 REGAMMA_CNTLA_EXP_REGION5_LUT_OFFSET 16 24 REGAMMA_CNTLA_EXP_REGION5_NUM_SEGMENTS 28 30 mmDCP4_REGAMMA_CNTLA_REGION_6_7 0 0xdeb 4 0 2 REGAMMA_CNTLA_EXP_REGION6_LUT_OFFSET 0 8 REGAMMA_CNTLA_EXP_REGION6_NUM_SEGMENTS 12 14 REGAMMA_CNTLA_EXP_REGION7_LUT_OFFSET 16 24 REGAMMA_CNTLA_EXP_REGION7_NUM_SEGMENTS 28 30 mmDCP4_REGAMMA_CNTLA_REGION_8_9 0 0xdec 4 0 2 REGAMMA_CNTLA_EXP_REGION8_LUT_OFFSET 0 8 REGAMMA_CNTLA_EXP_REGION8_NUM_SEGMENTS 12 14 REGAMMA_CNTLA_EXP_REGION9_LUT_OFFSET 16 24 REGAMMA_CNTLA_EXP_REGION9_NUM_SEGMENTS 28 30 mmDCP4_REGAMMA_CNTLA_REGION_10_11 0 0xded 4 0 2 REGAMMA_CNTLA_EXP_REGION10_LUT_OFFSET 0 8 REGAMMA_CNTLA_EXP_REGION10_NUM_SEGMENTS 12 14 REGAMMA_CNTLA_EXP_REGION11_LUT_OFFSET 16 24 REGAMMA_CNTLA_EXP_REGION11_NUM_SEGMENTS 28 30 mmDCP4_REGAMMA_CNTLA_REGION_12_13 0 0xdee 4 0 2 REGAMMA_CNTLA_EXP_REGION12_LUT_OFFSET 0 8 REGAMMA_CNTLA_EXP_REGION12_NUM_SEGMENTS 12 14 REGAMMA_CNTLA_EXP_REGION13_LUT_OFFSET 16 24 REGAMMA_CNTLA_EXP_REGION13_NUM_SEGMENTS 28 30 mmDCP4_REGAMMA_CNTLA_REGION_14_15 0 0xdef 4 0 2 REGAMMA_CNTLA_EXP_REGION14_LUT_OFFSET 0 8 REGAMMA_CNTLA_EXP_REGION14_NUM_SEGMENTS 12 14 REGAMMA_CNTLA_EXP_REGION15_LUT_OFFSET 16 24 REGAMMA_CNTLA_EXP_REGION15_NUM_SEGMENTS 28 30 mmDCP4_REGAMMA_CNTLB_START_CNTL 0 0xdf0 2 0 2 REGAMMA_CNTLB_EXP_REGION_START 0 17 REGAMMA_CNTLB_EXP_REGION_START_SEGMENT 20 26 mmDCP4_REGAMMA_CNTLB_SLOPE_CNTL 0 0xdf1 1 0 2 REGAMMA_CNTLB_EXP_REGION_LINEAR_SLOPE 0 17 mmDCP4_REGAMMA_CNTLB_END_CNTL1 0 0xdf2 1 0 2 REGAMMA_CNTLB_EXP_REGION_END 0 15 mmDCP4_REGAMMA_CNTLB_END_CNTL2 0 0xdf3 2 0 2 REGAMMA_CNTLB_EXP_REGION_END_SLOPE 0 15 REGAMMA_CNTLB_EXP_REGION_END_BASE 16 31 mmDCP4_REGAMMA_CNTLB_REGION_0_1 0 0xdf4 4 0 2 REGAMMA_CNTLB_EXP_REGION0_LUT_OFFSET 0 8 REGAMMA_CNTLB_EXP_REGION0_NUM_SEGMENTS 12 14 REGAMMA_CNTLB_EXP_REGION1_LUT_OFFSET 16 24 REGAMMA_CNTLB_EXP_REGION1_NUM_SEGMENTS 28 30 mmDCP4_REGAMMA_CNTLB_REGION_2_3 0 0xdf5 4 0 2 REGAMMA_CNTLB_EXP_REGION2_LUT_OFFSET 0 8 REGAMMA_CNTLB_EXP_REGION2_NUM_SEGMENTS 12 14 REGAMMA_CNTLB_EXP_REGION3_LUT_OFFSET 16 24 REGAMMA_CNTLB_EXP_REGION3_NUM_SEGMENTS 28 30 mmDCP4_REGAMMA_CNTLB_REGION_4_5 0 0xdf6 4 0 2 REGAMMA_CNTLB_EXP_REGION4_LUT_OFFSET 0 8 REGAMMA_CNTLB_EXP_REGION4_NUM_SEGMENTS 12 14 REGAMMA_CNTLB_EXP_REGION5_LUT_OFFSET 16 24 REGAMMA_CNTLB_EXP_REGION5_NUM_SEGMENTS 28 30 mmDCP4_REGAMMA_CNTLB_REGION_6_7 0 0xdf7 4 0 2 REGAMMA_CNTLB_EXP_REGION6_LUT_OFFSET 0 8 REGAMMA_CNTLB_EXP_REGION6_NUM_SEGMENTS 12 14 REGAMMA_CNTLB_EXP_REGION7_LUT_OFFSET 16 24 REGAMMA_CNTLB_EXP_REGION7_NUM_SEGMENTS 28 30 mmDCP4_REGAMMA_CNTLB_REGION_8_9 0 0xdf8 4 0 2 REGAMMA_CNTLB_EXP_REGION8_LUT_OFFSET 0 8 REGAMMA_CNTLB_EXP_REGION8_NUM_SEGMENTS 12 14 REGAMMA_CNTLB_EXP_REGION9_LUT_OFFSET 16 24 REGAMMA_CNTLB_EXP_REGION9_NUM_SEGMENTS 28 30 mmDCP4_REGAMMA_CNTLB_REGION_10_11 0 0xdf9 4 0 2 REGAMMA_CNTLB_EXP_REGION10_LUT_OFFSET 0 8 REGAMMA_CNTLB_EXP_REGION10_NUM_SEGMENTS 12 14 REGAMMA_CNTLB_EXP_REGION11_LUT_OFFSET 16 24 REGAMMA_CNTLB_EXP_REGION11_NUM_SEGMENTS 28 30 mmDCP4_REGAMMA_CNTLB_REGION_12_13 0 0xdfa 4 0 2 REGAMMA_CNTLB_EXP_REGION12_LUT_OFFSET 0 8 REGAMMA_CNTLB_EXP_REGION12_NUM_SEGMENTS 12 14 REGAMMA_CNTLB_EXP_REGION13_LUT_OFFSET 16 24 REGAMMA_CNTLB_EXP_REGION13_NUM_SEGMENTS 28 30 mmDCP4_REGAMMA_CNTLB_REGION_14_15 0 0xdfb 4 0 2 REGAMMA_CNTLB_EXP_REGION14_LUT_OFFSET 0 8 REGAMMA_CNTLB_EXP_REGION14_NUM_SEGMENTS 12 14 REGAMMA_CNTLB_EXP_REGION15_LUT_OFFSET 16 24 REGAMMA_CNTLB_EXP_REGION15_NUM_SEGMENTS 28 30 mmDCP4_ALPHA_CONTROL 0 0xdfc 2 0 2 ALPHA_ROUND_TRUNC_MODE 0 0 CURSOR_ALPHA_BLND_ENA 1 1 mmDCP4_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS 0 0xdfd 1 0 2 GRPH_XDMA_RECOVERY_SURFACE_ADDRESS 8 31 mmDCP4_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH 0 0xdfe 1 0 2 GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH 0 7 mmDCP4_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS 0 0xdff 7 0 2 GRPH_XDMA_CACHE_UNDERFLOW_CNT 0 19 GRPH_XDMA_CACHE_UNDERFLOW_CNT_STATUS 24 24 GRPH_XDMA_CACHE_UNDERFLOW_FRAME_MASK 25 25 GRPH_XDMA_CACHE_UNDERFLOW_FRAME_ACK 26 26 GRPH_XDMA_CACHE_UNDERFLOW_INT 28 28 GRPH_XDMA_CACHE_UNDERFLOW_INT_MASK 29 29 GRPH_XDMA_CACHE_UNDERFLOW_INT_ACK 30 30 mmDCP4_GRPH_XDMA_FLIP_TIMEOUT 0 0xe00 3 0 2 GRPH_XDMA_FLIP_TIMEOUT_STATUS 0 0 GRPH_XDMA_FLIP_TIMEOUT_MASK 1 1 GRPH_XDMA_FLIP_TIMEOUT_ACK 2 2 mmDCP4_GRPH_XDMA_FLIP_AVG_DELAY 0 0xe01 2 0 2 GRPH_XDMA_FLIP_AVG_DELAY 0 15 GRPH_XDMA_FLIP_AVG_PERIOD 16 23 mmDCP4_GRPH_SURFACE_COUNTER_CONTROL 0 0xe02 3 0 2 GRPH_SURFACE_COUNTER_EN 0 0 GRPH_SURFACE_COUNTER_EVENT_SELECT 1 4 GRPH_SURFACE_COUNTER_ERR_WRAP_OCCURED 9 9 mmDCP4_GRPH_SURFACE_COUNTER_OUTPUT 0 0xe03 2 0 2 GRPH_SURFACE_COUNTER_MIN 0 15 GRPH_SURFACE_COUNTER_MAX 16 31 mmLB4_LB_DATA_FORMAT 0 0xe1a 9 0 2 PIXEL_DEPTH 0 1 PIXEL_EXPAN_MODE 2 2 INTERLEAVE_EN 3 3 PIXEL_REDUCE_MODE 4 4 DYNAMIC_PIXEL_DEPTH 5 5 PREFILL_EN 8 8 PREFETCH 12 12 REQUEST_MODE 24 24 ALPHA_EN 31 31 mmLB4_LB_MEMORY_CTRL 0 0xe1b 3 0 2 LB_MEMORY_SIZE 0 12 LB_NUM_PARTITIONS 16 19 LB_MEMORY_CONFIG 20 21 mmLB4_LB_MEMORY_SIZE_STATUS 0 0xe1c 1 0 2 LB_MEMORY_SIZE_STATUS 0 12 mmLB4_LB_DESKTOP_HEIGHT 0 0xe1d 1 0 2 DESKTOP_HEIGHT 0 14 mmLB4_LB_VLINE_START_END 0 0xe1e 3 0 2 VLINE_START 0 13 VLINE_END 16 30 VLINE_INV 31 31 mmLB4_LB_VLINE2_START_END 0 0xe1f 3 0 2 VLINE2_START 0 13 VLINE2_END 16 30 VLINE2_INV 31 31 mmLB4_LB_V_COUNTER 0 0xe20 1 0 2 V_COUNTER 0 14 mmLB4_LB_SNAPSHOT_V_COUNTER 0 0xe21 1 0 2 SNAPSHOT_V_COUNTER 0 14 mmLB4_LB_INTERRUPT_MASK 0 0xe22 3 0 2 VBLANK_INTERRUPT_MASK 0 0 VLINE_INTERRUPT_MASK 4 4 VLINE2_INTERRUPT_MASK 8 8 mmLB4_LB_VLINE_STATUS 0 0xe23 5 0 2 VLINE_OCCURRED 0 0 VLINE_ACK 4 4 VLINE_STAT 12 12 VLINE_INTERRUPT 16 16 VLINE_INTERRUPT_TYPE 17 17 mmLB4_LB_VLINE2_STATUS 0 0xe24 5 0 2 VLINE2_OCCURRED 0 0 VLINE2_ACK 4 4 VLINE2_STAT 12 12 VLINE2_INTERRUPT 16 16 VLINE2_INTERRUPT_TYPE 17 17 mmLB4_LB_VBLANK_STATUS 0 0xe25 5 0 2 VBLANK_OCCURRED 0 0 VBLANK_ACK 4 4 VBLANK_STAT 12 12 VBLANK_INTERRUPT 16 16 VBLANK_INTERRUPT_TYPE 17 17 mmLB4_LB_SYNC_RESET_SEL 0 0xe26 4 0 2 LB_SYNC_RESET_SEL 0 1 LB_SYNC_RESET_SEL2 4 4 LB_SYNC_RESET_DELAY 8 15 LB_SYNC_DURATION 22 23 mmLB4_LB_BLACK_KEYER_R_CR 0 0xe27 1 0 2 LB_BLACK_KEYER_R_CR 4 15 mmLB4_LB_BLACK_KEYER_G_Y 0 0xe28 1 0 2 LB_BLACK_KEYER_G_Y 4 15 mmLB4_LB_BLACK_KEYER_B_CB 0 0xe29 1 0 2 LB_BLACK_KEYER_B_CB 4 15 mmLB4_LB_KEYER_COLOR_CTRL 0 0xe2a 2 0 2 LB_KEYER_COLOR_EN 0 0 LB_KEYER_COLOR_REP_EN 8 8 mmLB4_LB_KEYER_COLOR_R_CR 0 0xe2b 1 0 2 LB_KEYER_COLOR_R_CR 4 15 mmLB4_LB_KEYER_COLOR_G_Y 0 0xe2c 1 0 2 LB_KEYER_COLOR_G_Y 4 15 mmLB4_LB_KEYER_COLOR_B_CB 0 0xe2d 1 0 2 LB_KEYER_COLOR_B_CB 4 15 mmLB4_LB_KEYER_COLOR_REP_R_CR 0 0xe2e 1 0 2 LB_KEYER_COLOR_REP_R_CR 4 15 mmLB4_LB_KEYER_COLOR_REP_G_Y 0 0xe2f 1 0 2 LB_KEYER_COLOR_REP_G_Y 4 15 mmLB4_LB_KEYER_COLOR_REP_B_CB 0 0xe30 1 0 2 LB_KEYER_COLOR_REP_B_CB 4 15 mmLB4_LB_BUFFER_LEVEL_STATUS 0 0xe31 4 0 2 REQ_FIFO_LEVEL 0 5 REQ_FIFO_FULL_CNTL 10 15 DATA_BUFFER_LEVEL 16 27 DATA_FIFO_FULL_CNTL 28 31 mmLB4_LB_BUFFER_URGENCY_CTRL 0 0xe32 2 0 2 LB_BUFFER_URGENCY_MARK_ON 0 11 LB_BUFFER_URGENCY_MARK_OFF 16 27 mmLB4_LB_BUFFER_URGENCY_STATUS 0 0xe33 2 0 2 LB_BUFFER_URGENCY_LEVEL 0 11 LB_BUFFER_URGENCY_STAT 16 16 mmLB4_LB_BUFFER_STATUS 0 0xe34 7 0 2 LB_BUFFER_EMPTY_MARGIN 0 3 LB_BUFFER_EMPTY_STAT 4 4 LB_BUFFER_EMPTY_OCCURRED 8 8 LB_BUFFER_EMPTY_ACK 12 12 LB_BUFFER_FULL_STAT 16 16 LB_BUFFER_FULL_OCCURRED 20 20 LB_BUFFER_FULL_ACK 24 24 mmLB4_LB_NO_OUTSTANDING_REQ_STATUS 0 0xe35 1 0 2 LB_NO_OUTSTANDING_REQ_STAT 0 0 mmLB4_MVP_AFR_FLIP_MODE 0 0xe36 1 0 2 MVP_AFR_FLIP_MODE 0 1 mmLB4_MVP_AFR_FLIP_FIFO_CNTL 0 0xe37 4 0 2 MVP_AFR_FLIP_FIFO_NUM_ENTRIES 0 3 MVP_AFR_FLIP_FIFO_RESET 4 4 MVP_AFR_FLIP_FIFO_RESET_FLAG 8 8 MVP_AFR_FLIP_FIFO_RESET_ACK 12 12 mmLB4_MVP_FLIP_LINE_NUM_INSERT 0 0xe38 4 0 2 MVP_FLIP_LINE_NUM_INSERT_MODE 0 1 MVP_FLIP_LINE_NUM_INSERT 8 22 MVP_FLIP_LINE_NUM_OFFSET 24 29 MVP_FLIP_AUTO_ENABLE 30 30 mmLB4_DC_MVP_LB_CONTROL 0 0xe39 7 0 2 MVP_SWAP_LOCK_IN_MODE 0 1 DC_MVP_SWAP_LOCK_OUT_SEL 8 8 DC_MVP_SWAP_LOCK_OUT_FORCE_ONE 12 12 DC_MVP_SWAP_LOCK_OUT_FORCE_ZERO 16 16 DC_MVP_SWAP_LOCK_STATUS 20 20 DC_MVP_SWAP_LOCK_IN_CAP 28 28 DC_MVP_SPARE_FLOPS 31 31 mmDCFE4_DCFE_CLOCK_CONTROL 0 0xe5a 7 0 2 DISPCLK_R_DCFE_GATE_DISABLE 4 4 DISPCLK_G_DCP_GATE_DISABLE 8 8 DISPCLK_G_SCL_GATE_DISABLE 12 12 DISPCLK_G_PSCL_GATE_DISABLE 15 15 DISPCLK_G_PIPE_REQUEST_DIS_GATE_DISABLE 17 17 DCFE_TEST_CLK_SEL 24 28 DCFE_CLOCK_ENABLE 31 31 mmDCFE4_DCFE_SOFT_RESET 0 0xe5b 6 0 2 DCP_PIXPIPE_SOFT_RESET 0 0 DCP_REQ_SOFT_RESET 1 1 SCL_ALU_SOFT_RESET 2 2 SCL_SOFT_RESET 3 3 CRTC_SOFT_RESET 4 4 PSCL_SOFT_RESET 5 5 mmDCFE4_DCFE_MEM_PWR_CTRL 0 0xe5d 20 0 2 DCP_LUT_MEM_PWR_FORCE 0 1 DCP_LUT_MEM_PWR_DIS 2 2 DCP_REGAMMA_MEM_PWR_FORCE 3 4 DCP_REGAMMA_MEM_PWR_DIS 5 5 SCL_COEFF_MEM_PWR_FORCE 6 7 SCL_COEFF_MEM_PWR_DIS 8 8 DCP_CURSOR_MEM_PWR_FORCE 9 10 DCP_CURSOR_MEM_PWR_DIS 11 11 LB0_ALPHA_MEM_PWR_FORCE 12 13 LB0_ALPHA_MEM_PWR_DIS 14 14 LB1_ALPHA_MEM_PWR_FORCE 15 16 LB1_ALPHA_MEM_PWR_DIS 17 17 LB2_ALPHA_MEM_PWR_FORCE 18 19 LB2_ALPHA_MEM_PWR_DIS 20 20 LB0_MEM_PWR_FORCE 21 22 LB0_MEM_PWR_DIS 23 23 LB1_MEM_PWR_FORCE 24 25 LB1_MEM_PWR_DIS 26 26 LB2_MEM_PWR_FORCE 27 28 LB2_MEM_PWR_DIS 29 29 mmDCFE4_DCFE_MEM_PWR_CTRL2 0 0xe5e 12 0 2 DCP_LUT_MEM_PWR_MODE_SEL 0 1 DCP_REGAMMA_MEM_PWR_MODE_SEL 2 3 SCL_COEFF_MEM_PWR_MODE_SEL 4 5 DCP_CURSOR_MEM_PWR_MODE_SEL 6 7 LB_ALPHA_MEM_PWR_MODE_SEL 8 9 LB_MEM_PWR_MODE_SEL 10 11 DCP_CURSOR2_MEM_PWR_MODE_SEL 12 13 BLND_MEM_PWR_MODE_SEL 14 15 BLND_MEM_PWR_FORCE 16 17 BLND_MEM_PWR_DIS 18 18 DCP_CURSOR2_MEM_PWR_FORCE 21 22 DCP_CURSOR2_MEM_PWR_DIS 23 23 mmDCFE4_DCFE_MEM_PWR_STATUS 0 0xe5f 12 0 2 DCP_LUT_MEM_PWR_STATE 0 1 DCP_REGAMMA_MEM_PWR_STATE 2 3 SCL_COEFF_MEM_PWR_STATE 4 5 DCP_CURSOR_MEM_PWR_STATE 6 7 DCP_CURSOR2_MEM_PWR_STATE 8 9 LB0_ALPHA_MEM_PWR_STATE 10 11 LB1_ALPHA_MEM_PWR_STATE 12 13 LB2_ALPHA_MEM_PWR_STATE 14 15 LB0_MEM_PWR_STATE 16 17 LB1_MEM_PWR_STATE 18 19 LB2_MEM_PWR_STATE 20 21 BLND_MEM_PWR_STATE 22 23 mmDCFE4_DCFE_MISC 0 0xe60 1 0 2 DCFE_DPG_ALLOW_SR_ECO_EN 0 0 mmDCFE4_DCFE_FLUSH 0 0xe61 5 0 2 FLUSH_OCCURED 0 0 CLEAR_FLUSH_OCCURED 1 1 FLUSH_DEEP 2 2 CLEAR_FLUSH_DEEP 3 3 ALL_MC_REQ_RET 4 4 mmDC_PERFMON7_PERFCOUNTER_CNTL 0 0xe6e 13 0 2 PERFCOUNTER_EVENT_SEL 0 8 PERFCOUNTER_CVALUE_SEL 9 11 PERFCOUNTER_INC_MODE 12 14 PERFCOUNTER_HW_CNTL_SEL 15 15 PERFCOUNTER_RUNEN_MODE 16 16 PERFCOUNTER_CNTOFF_SEL 17 21 PERFCOUNTER_CNTOFF_START_DIS 22 22 PERFCOUNTER_RESTART_EN 23 23 PERFCOUNTER_INT_EN 24 24 PERFCOUNTER_OFF_MASK 25 25 PERFCOUNTER_ACTIVE 26 26 PERFCOUNTER_INT_TYPE 27 27 PERFCOUNTER_CNTL_SEL 29 31 mmDC_PERFMON7_PERFCOUNTER_CNTL2 0 0xe6f 4 0 2 PERFCOUNTER_COUNTED_VALUE_TYPE 0 1 PERFCOUNTER_HW_STOP1_SEL 2 2 PERFCOUNTER_HW_STOP2_SEL 3 3 PERFCOUNTER_CNTL2_SEL 29 31 mmDC_PERFMON7_PERFCOUNTER_STATE 0 0xe70 16 0 2 PERFCOUNTER_CNT0_STATE 0 1 PERFCOUNTER_STATE_SEL0 2 2 PERFCOUNTER_CNT1_STATE 4 5 PERFCOUNTER_STATE_SEL1 6 6 PERFCOUNTER_CNT2_STATE 8 9 PERFCOUNTER_STATE_SEL2 10 10 PERFCOUNTER_CNT3_STATE 12 13 PERFCOUNTER_STATE_SEL3 14 14 PERFCOUNTER_CNT4_STATE 16 17 PERFCOUNTER_STATE_SEL4 18 18 PERFCOUNTER_CNT5_STATE 20 21 PERFCOUNTER_STATE_SEL5 22 22 PERFCOUNTER_CNT6_STATE 24 25 PERFCOUNTER_STATE_SEL6 26 26 PERFCOUNTER_CNT7_STATE 28 29 PERFCOUNTER_STATE_SEL7 30 30 mmDC_PERFMON7_PERFMON_CNTL 0 0xe71 6 0 2 PERFMON_STATE 0 1 PERFMON_RPT_COUNT 8 27 PERFMON_CNTOFF_AND_OR 28 28 PERFMON_CNTOFF_INT_EN 29 29 PERFMON_CNTOFF_INT_STATUS 30 30 PERFMON_CNTOFF_INT_ACK 31 31 mmDC_PERFMON7_PERFMON_CNTL2 0 0xe72 4 0 2 PERFMON_CNTOFF_INT_TYPE 0 0 PERFMON_CLK_ENABLE 1 1 PERFMON_RUN_ENABLE_START_SEL 2 9 PERFMON_RUN_ENABLE_STOP_SEL 10 17 mmDC_PERFMON7_PERFMON_CVALUE_INT_MISC 0 0xe73 17 0 2 PERFCOUNTER_INT0_STATUS 0 0 PERFCOUNTER_INT1_STATUS 1 1 PERFCOUNTER_INT2_STATUS 2 2 PERFCOUNTER_INT3_STATUS 3 3 PERFCOUNTER_INT4_STATUS 4 4 PERFCOUNTER_INT5_STATUS 5 5 PERFCOUNTER_INT6_STATUS 6 6 PERFCOUNTER_INT7_STATUS 7 7 PERFCOUNTER_INT0_ACK 8 8 PERFCOUNTER_INT1_ACK 9 9 PERFCOUNTER_INT2_ACK 10 10 PERFCOUNTER_INT3_ACK 11 11 PERFCOUNTER_INT4_ACK 12 12 PERFCOUNTER_INT5_ACK 13 13 PERFCOUNTER_INT6_ACK 14 14 PERFCOUNTER_INT7_ACK 15 15 PERFMON_CVALUE_HI 16 31 mmDC_PERFMON7_PERFMON_CVALUE_LOW 0 0xe74 1 0 2 PERFMON_CVALUE_LOW 0 31 mmDC_PERFMON7_PERFMON_HI 0 0xe75 2 0 2 PERFMON_HI 0 15 PERFMON_READ_SEL 29 31 mmDC_PERFMON7_PERFMON_LOW 0 0xe76 1 0 2 PERFMON_LOW 0 31 mmDMIF_PG4_DPG_PIPE_ARBITRATION_CONTROL1 0 0xe7a 2 0 2 PIXEL_DURATION 0 15 BASE_WEIGHT 16 31 mmDMIF_PG4_DPG_PIPE_ARBITRATION_CONTROL2 0 0xe7b 2 0 2 TIME_WEIGHT 0 15 URGENCY_WEIGHT 16 31 mmDMIF_PG4_DPG_WATERMARK_MASK_CONTROL 0 0xe7c 8 0 2 STUTTER_EXIT_SELF_REFRESH_WATERMARK_MASK 0 2 STUTTER_ENTER_SELF_REFRESH_WATERMARK_MASK 4 6 URGENCY_WATERMARK_MASK 8 10 URGENT_LEVEL_WATERMARK_MASK 12 14 PSTATE_CHANGE_WATERMARK_MASK 15 17 DISABLE_FLIP_URGENT 18 18 URGENT_LEVEL_RAMP_CONTROL 19 19 STATIC_URGENT_LEVEL 20 29 mmDMIF_PG4_DPG_PIPE_URGENCY_CONTROL 0 0xe7d 2 0 2 URGENCY_LOW_WATERMARK 0 15 URGENCY_HIGH_WATERMARK 16 31 mmDMIF_PG4_DPG_PIPE_URGENT_LEVEL_CONTROL 0 0xe7e 2 0 2 URGENT_LEVEL_LOW_WATERMARK 0 15 URGENT_LEVEL_HIGH_WATERMARK 16 31 mmDMIF_PG4_DPG_PIPE_STUTTER_CONTROL 0 0xe7f 14 0 2 STUTTER_ENABLE 0 0 STUTTER_IGNORE_CURSOR 4 4 STUTTER_IGNORE_ICON 5 5 STUTTER_IGNORE_VGA 6 6 STUTTER_IGNORE_FBC 7 7 STUTTER_URGENT_IN_NOT_SELF_REFRESH 10 10 STUTTER_SELF_REFRESH_FORCE_ON 11 11 STUTTER_ENABLE_NONLPTCH 16 16 STUTTER_IGNORE_CURSOR_NONLPTCH 20 20 STUTTER_IGNORE_ICON_NONLPTCH 21 21 STUTTER_IGNORE_VGA_NONLPTCH 22 22 STUTTER_IGNORE_FBC_NONLPTCH 23 23 STUTTER_URGENT_IN_NOT_SELF_REFRESH_NONLPTCH 26 26 STUTTER_SELF_REFRESH_FORCE_ON_NONLPTCH 27 27 mmDMIF_PG4_DPG_PIPE_STUTTER_CONTROL2 0 0xe80 2 0 2 STUTTER_EXIT_SELF_REFRESH_WATERMARK 0 15 STUTTER_ENTER_SELF_REFRESH_WATERMARK 16 31 mmDMIF_PG4_DPG_PIPE_LOW_POWER_CONTROL 0 0xe81 7 0 2 PSTATE_CHANGE_ENABLE 0 0 DPM_ENABLE 1 1 PSTATE_CHANGE_URGENT_DURING_REQUEST 4 4 PSTATE_CHANGE_NOT_SELF_REFRESH_DURING_REQUEST 8 8 PSTATE_CHANGE_FORCE_ON 9 9 PSTATE_ALLOW_FOR_URGENT 10 10 PSTATE_CHANGE_WATERMARK 15 31 mmDMIF_PG4_DPG_REPEATER_PROGRAM 0 0xe82 2 0 2 REG_DPG_DMIFRC_REPEATER 0 2 REG_DMIFRC_DPG_REPEATER 4 6 mmDMIF_PG4_DPG_CHK_PRE_PROC_CNTL 0 0xe86 1 0 2 DPG_DISABLE_DMIF_BUF_CHK 0 0 mmDMIF_PG4_DPG_DVMM_STATUS 0 0xe87 4 0 2 DPG_DVMM_FORCED_FLIP_TO_UNMAPPED 0 0 DPG_DVMM_FORCED_FLIP_TO_MAPPED 1 1 DPG_DVMM_FORCED_FLIP_TO_UNMAPPED_CLR 4 4 DPG_DVMM_FORCED_FLIP_TO_MAPPED_CLR 5 5 mmSCL4_SCL_COEF_RAM_SELECT 0 0xe9a 3 0 2 SCL_C_RAM_TAP_PAIR_IDX 0 3 SCL_C_RAM_PHASE 8 11 SCL_C_RAM_FILTER_TYPE 16 18 mmSCL4_SCL_COEF_RAM_TAP_DATA 0 0xe9b 4 0 2 SCL_C_RAM_EVEN_TAP_COEF 0 13 SCL_C_RAM_EVEN_TAP_COEF_EN 15 15 SCL_C_RAM_ODD_TAP_COEF 16 29 SCL_C_RAM_ODD_TAP_COEF_EN 31 31 mmSCL4_SCL_MODE 0 0xe9c 2 0 2 SCL_MODE 0 1 SCL_PSCL_EN 4 4 mmSCL4_SCL_TAP_CONTROL 0 0xe9d 2 0 2 SCL_V_NUM_OF_TAPS 0 2 SCL_H_NUM_OF_TAPS 8 11 mmSCL4_SCL_CONTROL 0 0xe9e 2 0 2 SCL_BOUNDARY_MODE 0 0 SCL_EARLY_EOL_MODE 4 4 mmSCL4_SCL_BYPASS_CONTROL 0 0xe9f 1 0 2 SCL_BYPASS_MODE 0 1 mmSCL4_SCL_MANUAL_REPLICATE_CONTROL 0 0xea0 2 0 2 SCL_V_MANUAL_REPLICATE_FACTOR 0 3 SCL_H_MANUAL_REPLICATE_FACTOR 8 11 mmSCL4_SCL_AUTOMATIC_MODE_CONTROL 0 0xea1 2 0 2 SCL_V_CALC_AUTO_RATIO_EN 0 0 SCL_H_CALC_AUTO_RATIO_EN 16 16 mmSCL4_SCL_HORZ_FILTER_CONTROL 0 0xea2 2 0 2 SCL_H_FILTER_PICK_NEAREST 0 0 SCL_H_2TAP_HARDCODE_COEF_EN 8 8 mmSCL4_SCL_HORZ_FILTER_SCALE_RATIO 0 0xea3 1 0 2 SCL_H_SCALE_RATIO 0 25 mmSCL4_SCL_HORZ_FILTER_INIT 0 0xea4 2 0 2 SCL_H_INIT_FRAC 0 23 SCL_H_INIT_INT 24 27 mmSCL4_SCL_VERT_FILTER_CONTROL 0 0xea5 2 0 2 SCL_V_FILTER_PICK_NEAREST 0 0 SCL_V_2TAP_HARDCODE_COEF_EN 8 8 mmSCL4_SCL_VERT_FILTER_SCALE_RATIO 0 0xea6 1 0 2 SCL_V_SCALE_RATIO 0 25 mmSCL4_SCL_VERT_FILTER_INIT 0 0xea7 2 0 2 SCL_V_INIT_FRAC 0 23 SCL_V_INIT_INT 24 26 mmSCL4_SCL_VERT_FILTER_INIT_BOT 0 0xea8 2 0 2 SCL_V_INIT_FRAC_BOT 0 23 SCL_V_INIT_INT_BOT 24 26 mmSCL4_SCL_ROUND_OFFSET 0 0xea9 2 0 2 SCL_ROUND_OFFSET_RGB_Y 0 15 SCL_ROUND_OFFSET_CBCR 16 31 mmSCL4_SCL_UPDATE 0 0xeaa 4 0 2 SCL_UPDATE_PENDING 0 0 SCL_UPDATE_TAKEN 8 8 SCL_UPDATE_LOCK 16 16 SCL_COEF_UPDATE_COMPLETE 24 24 mmSCL4_SCL_F_SHARP_CONTROL 0 0xeab 4 0 2 SCL_HF_SHARP_SCALE_FACTOR 0 2 SCL_HF_SHARP_EN 4 4 SCL_VF_SHARP_SCALE_FACTOR 8 10 SCL_VF_SHARP_EN 12 12 mmSCL4_SCL_ALU_CONTROL 0 0xeac 1 0 2 SCL_ALU_DISABLE 0 0 mmSCL4_SCL_COEF_RAM_CONFLICT_STATUS 0 0xead 4 0 2 SCL_HOST_CONFLICT_FLAG 0 0 SCL_HOST_CONFLICT_ACK 8 8 SCL_HOST_CONFLICT_MASK 12 12 SCL_HOST_CONFLICT_INT_STATUS 16 16 mmSCL4_VIEWPORT_START_SECONDARY 0 0xeae 2 0 2 VIEWPORT_Y_START_SECONDARY 0 13 VIEWPORT_X_START_SECONDARY 16 29 mmSCL4_VIEWPORT_START 0 0xeaf 2 0 2 VIEWPORT_Y_START 0 13 VIEWPORT_X_START 16 29 mmSCL4_VIEWPORT_SIZE 0 0xeb0 2 0 2 VIEWPORT_HEIGHT 0 13 VIEWPORT_WIDTH 16 29 mmSCL4_EXT_OVERSCAN_LEFT_RIGHT 0 0xeb1 2 0 2 EXT_OVERSCAN_RIGHT 0 12 EXT_OVERSCAN_LEFT 16 28 mmSCL4_EXT_OVERSCAN_TOP_BOTTOM 0 0xeb2 2 0 2 EXT_OVERSCAN_BOTTOM 0 12 EXT_OVERSCAN_TOP 16 28 mmSCL4_SCL_MODE_CHANGE_DET1 0 0xeb3 3 0 2 SCL_MODE_CHANGE 0 0 SCL_MODE_CHANGE_ACK 4 4 SCL_ALU_H_SCALE_RATIO 7 27 mmSCL4_SCL_MODE_CHANGE_DET2 0 0xeb4 1 0 2 SCL_ALU_V_SCALE_RATIO 0 20 mmSCL4_SCL_MODE_CHANGE_DET3 0 0xeb5 2 0 2 SCL_ALU_SOURCE_HEIGHT 0 13 SCL_ALU_SOURCE_WIDTH 16 29 mmSCL4_SCL_MODE_CHANGE_MASK 0 0xeb6 1 0 2 SCL_MODE_CHANGE_MASK 0 0 mmBLND4_BLND_CONTROL 0 0xec7 9 0 2 BLND_GLOBAL_GAIN 0 7 BLND_MODE 8 9 BLND_STEREO_TYPE 10 11 BLND_STEREO_POLARITY 12 12 BLND_FEEDTHROUGH_EN 13 13 BLND_ALPHA_MODE 16 17 BLND_ACTIVE_OVERLAP_ONLY 18 18 BLND_MULTIPLIED_MODE 20 20 BLND_GLOBAL_ALPHA 24 31 mmBLND4_BLND_SM_CONTROL2 0 0xec8 6 0 2 SM_MODE 0 2 SM_FRAME_ALTERNATE 4 4 SM_FIELD_ALTERNATE 5 5 SM_FORCE_NEXT_FRAME_POL 8 9 SM_FORCE_NEXT_TOP_POL 16 17 SM_CURRENT_FRAME_POL 24 24 mmBLND4_BLND_CONTROL2 0 0xec9 5 0 2 PTI_ENABLE 0 0 PTI_NEW_PIXEL_GAP 4 5 BLND_NEW_PIXEL_MODE 6 6 BLND_SUPERAA_DEGAMMA_EN 7 7 BLND_SUPERAA_REGAMMA_EN 8 8 mmBLND4_BLND_UPDATE 0 0xeca 3 0 2 BLND_UPDATE_PENDING 0 0 BLND_UPDATE_TAKEN 8 8 BLND_UPDATE_LOCK 16 16 mmBLND4_BLND_UNDERFLOW_INTERRUPT 0 0xecb 4 0 2 BLND_UNDERFLOW_INT_OCCURED 0 0 BLND_UNDERFLOW_INT_ACK 8 8 BLND_UNDERFLOW_INT_MASK 12 12 BLND_UNDERFLOW_INT_PIPE_INDEX 16 17 mmBLND4_BLND_V_UPDATE_LOCK 0 0xecc 6 0 2 BLND_DCP_GRPH_V_UPDATE_LOCK 0 0 BLND_DCP_GRPH_SURF_V_UPDATE_LOCK 1 1 BLND_DCP_CUR_V_UPDATE_LOCK 16 16 BLND_SCL_V_UPDATE_LOCK 28 28 BLND_BLND_V_UPDATE_LOCK 29 29 BLND_V_UPDATE_LOCK_MODE 31 31 mmBLND4_BLND_REG_UPDATE_STATUS 0 0xecd 10 0 2 DCP_BLNDC_GRPH_UPDATE_PENDING 0 0 DCP_BLNDO_GRPH_UPDATE_PENDING 1 1 DCP_BLNDC_GRPH_SURF_UPDATE_PENDING 2 2 DCP_BLNDO_GRPH_SURF_UPDATE_PENDING 3 3 DCP_BLNDC_CUR_UPDATE_PENDING 6 6 DCP_BLNDO_CUR_UPDATE_PENDING 7 7 SCL_BLNDC_UPDATE_PENDING 8 8 SCL_BLNDO_UPDATE_PENDING 9 9 BLND_BLNDC_UPDATE_PENDING 10 10 BLND_BLNDO_UPDATE_PENDING 11 11 mmCRTC4_CRTC_H_BLANK_EARLY_NUM 0 0xed2 2 0 2 CRTC_H_BLANK_EARLY_NUM 0 9 CRTC_H_BLANK_EARLY_NUM_DIS 16 16 mmCRTC4_CRTC_H_TOTAL 0 0xed3 1 0 2 CRTC_H_TOTAL 0 13 mmCRTC4_CRTC_H_BLANK_START_END 0 0xed4 2 0 2 CRTC_H_BLANK_START 0 13 CRTC_H_BLANK_END 16 29 mmCRTC4_CRTC_H_SYNC_A 0 0xed5 2 0 2 CRTC_H_SYNC_A_START 0 13 CRTC_H_SYNC_A_END 16 29 mmCRTC4_CRTC_H_SYNC_A_CNTL 0 0xed6 3 0 2 CRTC_H_SYNC_A_POL 0 0 CRTC_COMP_SYNC_A_EN 16 16 CRTC_H_SYNC_A_CUTOFF 17 17 mmCRTC4_CRTC_H_SYNC_B 0 0xed7 2 0 2 CRTC_H_SYNC_B_START 0 13 CRTC_H_SYNC_B_END 16 29 mmCRTC4_CRTC_H_SYNC_B_CNTL 0 0xed8 3 0 2 CRTC_H_SYNC_B_POL 0 0 CRTC_COMP_SYNC_B_EN 16 16 CRTC_H_SYNC_B_CUTOFF 17 17 mmCRTC4_CRTC_VBI_END 0 0xed9 2 0 2 CRTC_VBI_V_END 0 13 CRTC_VBI_H_END 16 29 mmCRTC4_CRTC_V_TOTAL 0 0xeda 1 0 2 CRTC_V_TOTAL 0 13 mmCRTC4_CRTC_V_TOTAL_MIN 0 0xedb 1 0 2 CRTC_V_TOTAL_MIN 0 13 mmCRTC4_CRTC_V_TOTAL_MAX 0 0xedc 2 0 2 CRTC_V_TOTAL_MAX 0 13 CRTC_ALLOW_VBLANK_EXTENSION_FOR_MC_TRAINING 16 16 mmCRTC4_CRTC_V_TOTAL_CONTROL 0 0xedd 6 0 2 CRTC_V_TOTAL_MIN_SEL 0 0 CRTC_V_TOTAL_MAX_SEL 4 4 CRTC_FORCE_LOCK_ON_EVENT 8 8 CRTC_FORCE_LOCK_TO_MASTER_VSYNC 12 12 CRTC_SET_V_TOTAL_MIN_MASK_EN 15 15 CRTC_SET_V_TOTAL_MIN_MASK 16 31 mmCRTC4_CRTC_V_TOTAL_INT_STATUS 0 0xede 4 0 2 CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED 0 0 CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT 4 4 CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_ACK 8 8 CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_MSK 12 12 mmCRTC4_CRTC_VSYNC_NOM_INT_STATUS 0 0xedf 2 0 2 CRTC_VSYNC_NOM 0 0 CRTC_VSYNC_NOM_INT_CLEAR 4 4 mmCRTC4_CRTC_V_BLANK_START_END 0 0xee0 2 0 2 CRTC_V_BLANK_START 0 13 CRTC_V_BLANK_END 16 29 mmCRTC4_CRTC_V_SYNC_A 0 0xee1 2 0 2 CRTC_V_SYNC_A_START 0 13 CRTC_V_SYNC_A_END 16 29 mmCRTC4_CRTC_V_SYNC_A_CNTL 0 0xee2 1 0 2 CRTC_V_SYNC_A_POL 0 0 mmCRTC4_CRTC_V_SYNC_B 0 0xee3 2 0 2 CRTC_V_SYNC_B_START 0 13 CRTC_V_SYNC_B_END 16 29 mmCRTC4_CRTC_V_SYNC_B_CNTL 0 0xee4 1 0 2 CRTC_V_SYNC_B_POL 0 0 mmCRTC4_CRTC_DTMTEST_CNTL 0 0xee5 2 0 2 CRTC_DTMTEST_CRTC_EN 0 0 CRTC_DTMTEST_CLK_DIV 1 4 mmCRTC4_CRTC_DTMTEST_STATUS_POSITION 0 0xee6 2 0 2 CRTC_DTMTEST_VERT_COUNT 0 13 CRTC_DTMTEST_HORZ_COUNT 16 29 mmCRTC4_CRTC_TRIGA_CNTL 0 0xee7 11 0 2 CRTC_TRIGA_SOURCE_SELECT 0 4 CRTC_TRIGA_POLARITY_SELECT 5 7 CRTC_TRIGA_RESYNC_BYPASS_EN 8 8 CRTC_TRIGA_INPUT_STATUS 9 9 CRTC_TRIGA_POLARITY_STATUS 10 10 CRTC_TRIGA_OCCURRED 11 11 CRTC_TRIGA_RISING_EDGE_DETECT_CNTL 12 13 CRTC_TRIGA_FALLING_EDGE_DETECT_CNTL 16 17 CRTC_TRIGA_FREQUENCY_SELECT 20 21 CRTC_TRIGA_DELAY 24 28 CRTC_TRIGA_CLEAR 31 31 mmCRTC4_CRTC_TRIGA_MANUAL_TRIG 0 0xee8 1 0 2 CRTC_TRIGA_MANUAL_TRIG 0 0 mmCRTC4_CRTC_TRIGB_CNTL 0 0xee9 11 0 2 CRTC_TRIGB_SOURCE_SELECT 0 4 CRTC_TRIGB_POLARITY_SELECT 5 7 CRTC_TRIGB_RESYNC_BYPASS_EN 8 8 CRTC_TRIGB_INPUT_STATUS 9 9 CRTC_TRIGB_POLARITY_STATUS 10 10 CRTC_TRIGB_OCCURRED 11 11 CRTC_TRIGB_RISING_EDGE_DETECT_CNTL 12 13 CRTC_TRIGB_FALLING_EDGE_DETECT_CNTL 16 17 CRTC_TRIGB_FREQUENCY_SELECT 20 21 CRTC_TRIGB_DELAY 24 28 CRTC_TRIGB_CLEAR 31 31 mmCRTC4_CRTC_TRIGB_MANUAL_TRIG 0 0xeea 1 0 2 CRTC_TRIGB_MANUAL_TRIG 0 0 mmCRTC4_CRTC_FORCE_COUNT_NOW_CNTL 0 0xeeb 5 0 2 CRTC_FORCE_COUNT_NOW_MODE 0 1 CRTC_FORCE_COUNT_NOW_CHECK 4 4 CRTC_FORCE_COUNT_NOW_TRIG_SEL 8 8 CRTC_FORCE_COUNT_NOW_OCCURRED 16 16 CRTC_FORCE_COUNT_NOW_CLEAR 24 24 mmCRTC4_CRTC_FLOW_CONTROL 0 0xeec 4 0 2 CRTC_FLOW_CONTROL_SOURCE_SELECT 0 4 CRTC_FLOW_CONTROL_POLARITY 8 8 CRTC_FLOW_CONTROL_GRANULARITY 16 16 CRTC_FLOW_CONTROL_INPUT_STATUS 24 24 mmCRTC4_CRTC_STEREO_FORCE_NEXT_EYE 0 0xeed 3 0 2 CRTC_STEREO_FORCE_NEXT_EYE 0 1 CRTC_AVSYNC_FRAME_COUNTER 8 15 CRTC_AVSYNC_LINE_COUNTER 16 28 mmCRTC4_CRTC_AVSYNC_COUNTER 0 0xeee 1 0 2 CRTC_AVSYNC_COUNTER 0 31 mmCRTC4_CRTC_CONTROL 0 0xeef 11 0 2 CRTC_MASTER_EN 0 0 CRTC_SYNC_RESET_SEL 4 4 CRTC_DISABLE_POINT_CNTL 8 9 CRTC_START_POINT_CNTL 12 12 CRTC_FIELD_NUMBER_CNTL 13 13 CRTC_FIELD_NUMBER_POLARITY 14 14 CRTC_CURRENT_MASTER_EN_STATE 16 16 CRTC_HBLANK_EARLY_CONTROL 20 22 CRTC_SOF_PULL_EN 29 29 CRTC_AVSYNC_LOCK_SNAPSHOT 30 30 CRTC_AVSYNC_VSYNC_N_HSYNC_MODE 31 31 mmCRTC4_CRTC_BLANK_CONTROL 0 0xef0 3 0 2 CRTC_CURRENT_BLANK_STATE 0 0 CRTC_BLANK_DATA_EN 8 8 CRTC_BLANK_DE_MODE 16 16 mmCRTC4_CRTC_INTERLACE_CONTROL 0 0xef1 2 0 2 CRTC_INTERLACE_ENABLE 0 0 CRTC_INTERLACE_FORCE_NEXT_FIELD 16 17 mmCRTC4_CRTC_INTERLACE_STATUS 0 0xef2 2 0 2 CRTC_INTERLACE_CURRENT_FIELD 0 0 CRTC_INTERLACE_NEXT_FIELD 1 1 mmCRTC4_CRTC_FIELD_INDICATION_CONTROL 0 0xef3 2 0 2 CRTC_FIELD_INDICATION_OUTPUT_POLARITY 0 0 CRTC_FIELD_ALIGNMENT 1 1 mmCRTC4_CRTC_PIXEL_DATA_READBACK0 0 0xef4 2 0 2 CRTC_PIXEL_DATA_BLUE_CB 0 11 CRTC_PIXEL_DATA_GREEN_Y 16 27 mmCRTC4_CRTC_PIXEL_DATA_READBACK1 0 0xef5 1 0 2 CRTC_PIXEL_DATA_RED_CR 0 11 mmCRTC4_CRTC_STATUS 0 0xef6 9 0 2 CRTC_V_BLANK 0 0 CRTC_V_ACTIVE_DISP 1 1 CRTC_V_SYNC_A 2 2 CRTC_V_UPDATE 3 3 CRTC_V_START_LINE 4 4 CRTC_V_BLANK_3D_STRUCTURE 5 5 CRTC_H_BLANK 16 16 CRTC_H_ACTIVE_DISP 17 17 CRTC_H_SYNC_A 18 18 mmCRTC4_CRTC_STATUS_POSITION 0 0xef7 2 0 2 CRTC_VERT_COUNT 0 13 CRTC_HORZ_COUNT 16 29 mmCRTC4_CRTC_NOM_VERT_POSITION 0 0xef8 1 0 2 CRTC_VERT_COUNT_NOM 0 13 mmCRTC4_CRTC_STATUS_FRAME_COUNT 0 0xef9 1 0 2 CRTC_FRAME_COUNT 0 23 mmCRTC4_CRTC_STATUS_VF_COUNT 0 0xefa 1 0 2 CRTC_VF_COUNT 0 29 mmCRTC4_CRTC_STATUS_HV_COUNT 0 0xefb 1 0 2 CRTC_HV_COUNT 0 29 mmCRTC4_CRTC_COUNT_CONTROL 0 0xefc 2 0 2 CRTC_HORZ_COUNT_BY2_EN 0 0 CRTC_HORZ_REPETITION_COUNT 1 4 mmCRTC4_CRTC_COUNT_RESET 0 0xefd 1 0 2 CRTC_RESET_FRAME_COUNT 0 0 mmCRTC4_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE 0 0xefe 1 0 2 CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE 0 0 mmCRTC4_CRTC_VERT_SYNC_CONTROL 0 0xeff 3 0 2 CRTC_FORCE_VSYNC_NEXT_LINE_OCCURRED 0 0 CRTC_FORCE_VSYNC_NEXT_LINE_CLEAR 8 8 CRTC_AUTO_FORCE_VSYNC_MODE 16 17 mmCRTC4_CRTC_STEREO_STATUS 0 0xf00 5 0 2 CRTC_STEREO_CURRENT_EYE 0 0 CRTC_STEREO_SYNC_OUTPUT 8 8 CRTC_STEREO_SYNC_SELECT 16 16 CRTC_STEREO_EYE_FLAG 20 20 CRTC_STEREO_FORCE_NEXT_EYE_PENDING 24 25 mmCRTC4_CRTC_STEREO_CONTROL 0 0xf01 8 0 2 CRTC_STEREO_SYNC_OUTPUT_LINE_NUM 0 13 CRTC_STEREO_SYNC_OUTPUT_POLARITY 15 15 CRTC_STEREO_SYNC_SELECT_POLARITY 16 16 CRTC_STEREO_EYE_FLAG_POLARITY 17 17 CRTC_DISABLE_STEREOSYNC_OUTPUT_FOR_DP 18 18 CRTC_DISABLE_FIELD_NUM 19 19 CRTC_DISABLE_V_BLANK_FOR_DP_FIX 20 20 CRTC_STEREO_EN 24 24 mmCRTC4_CRTC_SNAPSHOT_STATUS 0 0xf02 3 0 2 CRTC_SNAPSHOT_OCCURRED 0 0 CRTC_SNAPSHOT_CLEAR 1 1 CRTC_SNAPSHOT_MANUAL_TRIGGER 2 2 mmCRTC4_CRTC_SNAPSHOT_CONTROL 0 0xf03 1 0 2 CRTC_AUTO_SNAPSHOT_TRIG_SEL 0 1 mmCRTC4_CRTC_SNAPSHOT_POSITION 0 0xf04 2 0 2 CRTC_SNAPSHOT_VERT_COUNT 0 13 CRTC_SNAPSHOT_HORZ_COUNT 16 29 mmCRTC4_CRTC_SNAPSHOT_FRAME 0 0xf05 1 0 2 CRTC_SNAPSHOT_FRAME_COUNT 0 23 mmCRTC4_CRTC_START_LINE_CONTROL 0 0xf06 5 0 2 CRTC_PROGRESSIVE_START_LINE_EARLY 0 0 CRTC_INTERLACE_START_LINE_EARLY 1 1 CRTC_PREFETCH_EN 2 2 CRTC_LEGACY_REQUESTOR_EN 8 8 CRTC_ADVANCED_START_LINE_POSITION 12 19 mmCRTC4_CRTC_INTERRUPT_CONTROL 0 0xf07 16 0 2 CRTC_SNAPSHOT_INT_MSK 0 0 CRTC_SNAPSHOT_INT_TYPE 1 1 CRTC_V_UPDATE_INT_MSK 4 4 CRTC_V_UPDATE_INT_TYPE 5 5 CRTC_FORCE_COUNT_NOW_INT_MSK 8 8 CRTC_FORCE_COUNT_NOW_INT_TYPE 9 9 CRTC_FORCE_VSYNC_NEXT_LINE_INT_MSK 16 16 CRTC_FORCE_VSYNC_NEXT_LINE_INT_TYPE 17 17 CRTC_TRIGA_INT_MSK 24 24 CRTC_TRIGB_INT_MSK 25 25 CRTC_TRIGA_INT_TYPE 26 26 CRTC_TRIGB_INT_TYPE 27 27 CRTC_VSYNC_NOM_INT_MSK 28 28 CRTC_VSYNC_NOM_INT_TYPE 29 29 CRTC_GSL_VSYNC_GAP_INT_MSK 30 30 CRTC_GSL_VSYNC_GAP_INT_TYPE 31 31 mmCRTC4_CRTC_UPDATE_LOCK 0 0xf08 1 0 2 CRTC_UPDATE_LOCK 0 0 mmCRTC4_CRTC_DOUBLE_BUFFER_CONTROL 0 0xf09 5 0 2 CRTC_UPDATE_PENDING 0 0 CRTC_UPDATE_INSTANTLY 8 8 CRTC_BLANK_DATA_DOUBLE_BUFFER_EN 16 16 CRTC_RANGE_TIMING_DBUF_UPDATE_MODE 24 24 CRTC_RANGE_TIMING_DBUF_UPDATE_PENDING 25 25 mmCRTC4_CRTC_VGA_PARAMETER_CAPTURE_MODE 0 0xf0a 1 0 2 CRTC_VGA_PARAMETER_CAPTURE_MODE 0 0 mmCRTC4_CRTC_TEST_PATTERN_CONTROL 0 0xf0b 4 0 2 CRTC_TEST_PATTERN_EN 0 0 CRTC_TEST_PATTERN_MODE 8 10 CRTC_TEST_PATTERN_DYNAMIC_RANGE 16 16 CRTC_TEST_PATTERN_COLOR_FORMAT 24 31 mmCRTC4_CRTC_TEST_PATTERN_PARAMETERS 0 0xf0c 5 0 2 CRTC_TEST_PATTERN_INC0 0 3 CRTC_TEST_PATTERN_INC1 4 7 CRTC_TEST_PATTERN_VRES 8 11 CRTC_TEST_PATTERN_HRES 12 15 CRTC_TEST_PATTERN_RAMP0_OFFSET 16 31 mmCRTC4_CRTC_TEST_PATTERN_COLOR 0 0xf0d 2 0 2 CRTC_TEST_PATTERN_DATA 0 15 CRTC_TEST_PATTERN_MASK 16 21 mmCRTC4_CRTC_MASTER_UPDATE_LOCK 0 0xf0e 3 0 2 MASTER_UPDATE_LOCK 0 0 GSL_CONTROL_MASTER_UPDATE_LOCK 8 8 UNDERFLOW_UPDATE_LOCK 16 16 mmCRTC4_CRTC_MASTER_UPDATE_MODE 0 0xf0f 2 0 2 MASTER_UPDATE_MODE 0 2 MASTER_UPDATE_INTERLACED_MODE 16 17 mmCRTC4_CRTC_MVP_INBAND_CNTL_INSERT 0 0xf10 2 0 2 CRTC_MVP_INBAND_OUT_MODE 0 1 CRTC_MVP_INBAND_CNTL_CHAR_INSERT 8 31 mmCRTC4_CRTC_MVP_INBAND_CNTL_INSERT_TIMER 0 0xf11 1 0 2 CRTC_MVP_INBAND_CNTL_CHAR_INSERT_TIMER 0 7 mmCRTC4_CRTC_MVP_STATUS 0 0xf12 4 0 2 CRTC_FLIP_NOW_OCCURRED 0 0 CRTC_AFR_HSYNC_SWITCH_DONE_OCCURRED 4 4 CRTC_FLIP_NOW_CLEAR 16 16 CRTC_AFR_HSYNC_SWITCH_DONE_CLEAR 20 20 mmCRTC4_CRTC_MASTER_EN 0 0xf13 1 0 2 CRTC_MASTER_EN 0 0 mmCRTC4_CRTC_ALLOW_STOP_OFF_V_CNT 0 0xf14 2 0 2 CRTC_ALLOW_STOP_OFF_V_CNT 0 7 CRTC_DISABLE_ALLOW_STOP_OFF_V_CNT 16 16 mmCRTC4_CRTC_V_UPDATE_INT_STATUS 0 0xf15 2 0 2 CRTC_V_UPDATE_INT_OCCURRED 0 0 CRTC_V_UPDATE_INT_CLEAR 8 8 mmCRTC4_CRTC_OVERSCAN_COLOR 0 0xf17 3 0 2 CRTC_OVERSCAN_COLOR_BLUE 0 9 CRTC_OVERSCAN_COLOR_GREEN 10 19 CRTC_OVERSCAN_COLOR_RED 20 29 mmCRTC4_CRTC_OVERSCAN_COLOR_EXT 0 0xf18 3 0 2 CRTC_OVERSCAN_COLOR_BLUE_EXT 0 1 CRTC_OVERSCAN_COLOR_GREEN_EXT 8 9 CRTC_OVERSCAN_COLOR_RED_EXT 16 17 mmCRTC4_CRTC_BLANK_DATA_COLOR 0 0xf19 3 0 2 CRTC_BLANK_DATA_COLOR_BLUE_CB 0 9 CRTC_BLANK_DATA_COLOR_GREEN_Y 10 19 CRTC_BLANK_DATA_COLOR_RED_CR 20 29 mmCRTC4_CRTC_BLANK_DATA_COLOR_EXT 0 0xf1a 3 0 2 CRTC_BLANK_DATA_COLOR_BLUE_CB_EXT 0 1 CRTC_BLANK_DATA_COLOR_GREEN_Y_EXT 8 9 CRTC_BLANK_DATA_COLOR_RED_CR_EXT 16 17 mmCRTC4_CRTC_BLACK_COLOR 0 0xf1b 3 0 2 CRTC_BLACK_COLOR_B_CB 0 9 CRTC_BLACK_COLOR_G_Y 10 19 CRTC_BLACK_COLOR_R_CR 20 29 mmCRTC4_CRTC_BLACK_COLOR_EXT 0 0xf1c 3 0 2 CRTC_BLACK_COLOR_B_CB_EXT 0 1 CRTC_BLACK_COLOR_G_Y_EXT 8 9 CRTC_BLACK_COLOR_R_CR_EXT 16 17 mmCRTC4_CRTC_VERTICAL_INTERRUPT0_POSITION 0 0xf1d 2 0 2 CRTC_VERTICAL_INTERRUPT0_LINE_START 0 13 CRTC_VERTICAL_INTERRUPT0_LINE_END 16 29 mmCRTC4_CRTC_VERTICAL_INTERRUPT0_CONTROL 0 0xf1e 6 0 2 CRTC_VERTICAL_INTERRUPT0_OUTPUT_POLARITY 4 4 CRTC_VERTICAL_INTERRUPT0_INT_ENABLE 8 8 CRTC_VERTICAL_INTERRUPT0_STATUS 12 12 CRTC_VERTICAL_INTERRUPT0_INT_STATUS 16 16 CRTC_VERTICAL_INTERRUPT0_CLEAR 20 20 CRTC_VERTICAL_INTERRUPT0_INT_TYPE 24 24 mmCRTC4_CRTC_VERTICAL_INTERRUPT1_POSITION 0 0xf1f 1 0 2 CRTC_VERTICAL_INTERRUPT1_LINE_START 0 13 mmCRTC4_CRTC_VERTICAL_INTERRUPT1_CONTROL 0 0xf20 5 0 2 CRTC_VERTICAL_INTERRUPT1_INT_ENABLE 8 8 CRTC_VERTICAL_INTERRUPT1_STATUS 12 12 CRTC_VERTICAL_INTERRUPT1_INT_STATUS 16 16 CRTC_VERTICAL_INTERRUPT1_CLEAR 20 20 CRTC_VERTICAL_INTERRUPT1_INT_TYPE 24 24 mmCRTC4_CRTC_VERTICAL_INTERRUPT2_POSITION 0 0xf21 1 0 2 CRTC_VERTICAL_INTERRUPT2_LINE_START 0 13 mmCRTC4_CRTC_VERTICAL_INTERRUPT2_CONTROL 0 0xf22 5 0 2 CRTC_VERTICAL_INTERRUPT2_INT_ENABLE 8 8 CRTC_VERTICAL_INTERRUPT2_STATUS 12 12 CRTC_VERTICAL_INTERRUPT2_INT_STATUS 16 16 CRTC_VERTICAL_INTERRUPT2_CLEAR 20 20 CRTC_VERTICAL_INTERRUPT2_INT_TYPE 24 24 mmCRTC4_CRTC_CRC_CNTL 0 0xf23 7 0 2 CRTC_CRC_EN 0 0 CRTC_CRC_CONT_EN 4 4 CRTC_CRC_STEREO_MODE 8 9 CRTC_CRC_INTERLACE_MODE 12 13 CRTC_CRC_USE_NEW_AND_REPEATED_PIXELS 16 16 CRTC_CRC0_SELECT 20 22 CRTC_CRC1_SELECT 24 26 mmCRTC4_CRTC_CRC0_WINDOWA_X_CONTROL 0 0xf24 2 0 2 CRTC_CRC0_WINDOWA_X_START 0 13 CRTC_CRC0_WINDOWA_X_END 16 29 mmCRTC4_CRTC_CRC0_WINDOWA_Y_CONTROL 0 0xf25 2 0 2 CRTC_CRC0_WINDOWA_Y_START 0 13 CRTC_CRC0_WINDOWA_Y_END 16 29 mmCRTC4_CRTC_CRC0_WINDOWB_X_CONTROL 0 0xf26 2 0 2 CRTC_CRC0_WINDOWB_X_START 0 13 CRTC_CRC0_WINDOWB_X_END 16 29 mmCRTC4_CRTC_CRC0_WINDOWB_Y_CONTROL 0 0xf27 2 0 2 CRTC_CRC0_WINDOWB_Y_START 0 13 CRTC_CRC0_WINDOWB_Y_END 16 29 mmCRTC4_CRTC_CRC0_DATA_RG 0 0xf28 2 0 2 CRC0_R_CR 0 15 CRC0_G_Y 16 31 mmCRTC4_CRTC_CRC0_DATA_B 0 0xf29 1 0 2 CRC0_B_CB 0 15 mmCRTC4_CRTC_CRC1_WINDOWA_X_CONTROL 0 0xf2a 2 0 2 CRTC_CRC1_WINDOWA_X_START 0 13 CRTC_CRC1_WINDOWA_X_END 16 29 mmCRTC4_CRTC_CRC1_WINDOWA_Y_CONTROL 0 0xf2b 2 0 2 CRTC_CRC1_WINDOWA_Y_START 0 13 CRTC_CRC1_WINDOWA_Y_END 16 29 mmCRTC4_CRTC_CRC1_WINDOWB_X_CONTROL 0 0xf2c 2 0 2 CRTC_CRC1_WINDOWB_X_START 0 13 CRTC_CRC1_WINDOWB_X_END 16 29 mmCRTC4_CRTC_CRC1_WINDOWB_Y_CONTROL 0 0xf2d 2 0 2 CRTC_CRC1_WINDOWB_Y_START 0 13 CRTC_CRC1_WINDOWB_Y_END 16 29 mmCRTC4_CRTC_CRC1_DATA_RG 0 0xf2e 2 0 2 CRC1_R_CR 0 15 CRC1_G_Y 16 31 mmCRTC4_CRTC_CRC1_DATA_B 0 0xf2f 1 0 2 CRC1_B_CB 0 15 mmCRTC4_CRTC_EXT_TIMING_SYNC_CONTROL 0 0xf30 11 0 2 CRTC_EXT_TIMING_SYNC_ENABLE 0 1 CRTC_EXT_TIMING_SYNC_HCOUNT_MODE_ENABLE 3 3 CRTC_EXT_TIMING_SYNC_JITTER_FILTERING_ENABLE 4 4 CRTC_EXT_TIMING_SYNC_JITTER_FILTERING_WINDOW 5 6 CRTC_EXT_TIMING_SYNC_WINDOW_ENABLE 8 8 CRTC_EXT_TIMING_SYNC_WINDOW_UPDATE 9 9 CRTC_EXT_TIMING_SYNC_VSYNC_POLARITY 12 12 CRTC_EXT_TIMING_SYNC_HSYNC_POLARITY 13 13 CRTC_EXT_TIMING_SYNC_INTERLACE_MODE 14 14 CRTC_EXT_TIMING_SYNC_MASTER_FRAME_RATE 24 26 CRTC_EXT_TIMING_SYNC_SLAVE_FRAME_RATE 28 30 mmCRTC4_CRTC_EXT_TIMING_SYNC_WINDOW_START 0 0xf31 2 0 2 CRTC_EXT_TIMING_SYNC_WINDOW_START_X 0 13 CRTC_EXT_TIMING_SYNC_WINDOW_START_Y 16 29 mmCRTC4_CRTC_EXT_TIMING_SYNC_WINDOW_END 0 0xf32 2 0 2 CRTC_EXT_TIMING_SYNC_WINDOW_END_X 0 13 CRTC_EXT_TIMING_SYNC_WINDOW_END_Y 16 29 mmCRTC4_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL 0 0xf33 6 0 2 CRTC_EXT_TIMING_SYNC_LOSS_INT_ENABLE 0 0 CRTC_EXT_TIMING_SYNC_LOSS_STATUS 4 4 CRTC_EXT_TIMING_SYNC_LOSS_INT_STATUS 8 8 CRTC_EXT_TIMING_SYNC_LOSS_CLEAR 16 16 CRTC_EXT_TIMING_SYNC_LOSS_INT_TYPE 20 20 CRTC_EXT_TIMING_SYNC_LOSS_FRAME_COUNT 29 31 mmCRTC4_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL 0 0xf34 5 0 2 CRTC_EXT_TIMING_SYNC_INT_ENABLE 0 0 CRTC_EXT_TIMING_SYNC_STATUS 4 4 CRTC_EXT_TIMING_SYNC_INT_STATUS 8 8 CRTC_EXT_TIMING_SYNC_CLEAR 16 16 CRTC_EXT_TIMING_SYNC_INT_TYPE 20 20 mmCRTC4_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL 0 0xf35 5 0 2 CRTC_EXT_TIMING_SYNC_SIGNAL_INT_ENABLE 0 0 CRTC_EXT_TIMING_SYNC_SIGNAL_STATUS 4 4 CRTC_EXT_TIMING_SYNC_SIGNAL_INT_STATUS 8 8 CRTC_EXT_TIMING_SYNC_SIGNAL_CLEAR 16 16 CRTC_EXT_TIMING_SYNC_SIGNAL_INT_TYPE 20 20 mmCRTC4_CRTC_STATIC_SCREEN_CONTROL 0 0xf36 9 0 2 CRTC_STATIC_SCREEN_EVENT_MASK 0 15 CRTC_STATIC_SCREEN_FRAME_COUNT 16 23 CRTC_CPU_SS_INT_ENABLE 24 24 CRTC_SS_STATUS 25 25 CRTC_CPU_SS_INT_STATUS 26 26 CRTC_CPU_SS_INT_CLEAR 27 27 CRTC_CPU_SS_INT_TYPE 28 28 CRTC_STATIC_SCREEN_OVERRIDE 30 30 CRTC_STATIC_SCREEN_OVERRIDE_VALUE 31 31 mmCRTC4_CRTC_3D_STRUCTURE_CONTROL 0 0xf37 7 0 2 CRTC_3D_STRUCTURE_EN 0 0 CRTC_3D_STRUCTURE_EN_DB 4 4 CRTC_3D_STRUCTURE_V_UPDATE_MODE 8 9 CRTC_3D_STRUCTURE_STEREO_SEL_OVR 12 12 CRTC_3D_STRUCTURE_F_COUNT_RESET 16 16 CRTC_3D_STRUCTURE_F_COUNT_RESET_PENDING 17 17 CRTC_3D_STRUCTURE_F_COUNT 18 19 mmCRTC4_CRTC_GSL_VSYNC_GAP 0 0xf38 8 0 2 CRTC_GSL_VSYNC_GAP_LIMIT 0 7 CRTC_GSL_VSYNC_GAP_DELAY 8 15 CRTC_GSL_VSYNC_GAP_SOURCE_SEL 16 16 CRTC_GSL_VSYNC_GAP_MODE 17 18 CRTC_GSL_VSYNC_GAP_CLEAR 19 19 CRTC_GSL_VSYNC_GAP_OCCURRED 20 20 CRTC_GSL_VSYNC_GAP_MASTER_FASTER 23 23 CRTC_GSL_VSYNC_GAP 24 31 mmCRTC4_CRTC_GSL_WINDOW 0 0xf39 2 0 2 CRTC_GSL_WINDOW_START 0 13 CRTC_GSL_WINDOW_END 16 29 mmCRTC4_CRTC_GSL_CONTROL 0 0xf3a 3 0 2 CRTC_GSL_CHECK_LINE_NUM 0 13 CRTC_GSL_FORCE_DELAY 16 20 CRTC_GSL_CHECK_ALL_FIELDS 28 28 mmCRTC4_CRTC_RANGE_TIMING_INT_STATUS 0 0xf3d 5 0 2 CRTC_RANGE_TIMING_UPDATE_OCCURRED 0 0 CRTC_RANGE_TIMING_UPDATE_OCCURRED_INT 4 4 CRTC_RANGE_TIMING_UPDATE_OCCURRED_CLEAR 8 8 CRTC_RANGE_TIMING_UPDATE_OCCURRED_INT_MSK 12 12 CRTC_RANGE_TIMING_UPDATE_OCCURRED_INT_TYPE 16 16 mmCRTC4_CRTC_DRR_CONTROL 0 0xf3e 4 0 2 CRTC_XDMA_PREFETCH_DELAY 0 13 CRTC_V_TOTAL_LAST_USED_BY_DRR 14 27 CRTC_SET_V_TOTAL_MIN_AUTO_DIS 28 28 CRTC_DRR_MODE_DBUF_UPDATE_MODE 29 30 mmFMT4_FMT_CLAMP_COMPONENT_R 0 0xf42 2 0 2 FMT_CLAMP_LOWER_R 0 15 FMT_CLAMP_UPPER_R 16 31 mmFMT4_FMT_CLAMP_COMPONENT_G 0 0xf43 2 0 2 FMT_CLAMP_LOWER_G 0 15 FMT_CLAMP_UPPER_G 16 31 mmFMT4_FMT_CLAMP_COMPONENT_B 0 0xf44 2 0 2 FMT_CLAMP_LOWER_B 0 15 FMT_CLAMP_UPPER_B 16 31 mmFMT4_FMT_DYNAMIC_EXP_CNTL 0 0xf45 2 0 2 FMT_DYNAMIC_EXP_EN 0 0 FMT_DYNAMIC_EXP_MODE 4 4 mmFMT4_FMT_CONTROL 0 0xf46 11 0 2 FMT_STEREOSYNC_OVERRIDE 0 0 FMT_STEREOSYNC_OVR_POL 4 4 FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX 8 11 FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP 12 13 FMT_PIXEL_ENCODING 16 17 FMT_SUBSAMPLING_MODE 18 19 FMT_SUBSAMPLING_ORDER 20 20 FMT_CBCR_BIT_REDUCTION_BYPASS 21 21 FMT_SRC_SELECT 24 26 FMT_420_PIXEL_PHASE_LOCKED 30 30 FMT_420_PIXEL_PHASE_LOCKED_CLEAR 31 31 mmFMT4_FMT_BIT_DEPTH_CONTROL 0 0xf47 17 0 2 FMT_TRUNCATE_EN 0 0 FMT_TRUNCATE_MODE 1 1 FMT_TRUNCATE_DEPTH 4 5 FMT_SPATIAL_DITHER_EN 8 8 FMT_SPATIAL_DITHER_MODE 9 10 FMT_SPATIAL_DITHER_DEPTH 11 12 FMT_FRAME_RANDOM_ENABLE 13 13 FMT_RGB_RANDOM_ENABLE 14 14 FMT_HIGHPASS_RANDOM_ENABLE 15 15 FMT_TEMPORAL_DITHER_EN 16 16 FMT_TEMPORAL_DITHER_DEPTH 17 18 FMT_TEMPORAL_DITHER_OFFSET 21 22 FMT_TEMPORAL_LEVEL 24 24 FMT_TEMPORAL_DITHER_RESET 25 25 FMT_25FRC_SEL 26 27 FMT_50FRC_SEL 28 29 FMT_75FRC_SEL 30 31 mmFMT4_FMT_DITHER_RAND_R_SEED 0 0xf48 2 0 2 FMT_RAND_R_SEED 0 7 FMT_OFFSET_R_CR 16 31 mmFMT4_FMT_DITHER_RAND_G_SEED 0 0xf49 2 0 2 FMT_RAND_G_SEED 0 7 FMT_OFFSET_G_Y 16 31 mmFMT4_FMT_DITHER_RAND_B_SEED 0 0xf4a 2 0 2 FMT_RAND_B_SEED 0 7 FMT_OFFSET_B_CB 16 31 mmFMT4_FMT_CLAMP_CNTL 0 0xf4e 2 0 2 FMT_CLAMP_DATA_EN 0 0 FMT_CLAMP_COLOR_FORMAT 16 18 mmFMT4_FMT_CRC_CNTL 0 0xf4f 11 0 2 FMT_CRC_EN 0 0 FMT_DTMTEST_CRC_EN 1 1 FMT_CRC_CONT_EN 4 4 FMT_ONE_SHOT_CRC_PENDING 5 5 FMT_CRC_INCLUDE_OVERSCAN 6 6 FMT_CRC_ONLY_BLANKB 8 8 FMT_CRC_PSR_MODE_ENABLE 9 9 FMT_CRC_INTERLACE_MODE 12 13 FMT_CRC_USE_NEW_AND_REPEATED_PIXELS 16 16 FMT_CRC_EVEN_ODD_PIX_ENABLE 20 20 FMT_CRC_EVEN_ODD_PIX_SELECT 24 24 mmFMT4_FMT_CRC_SIG_RED_GREEN_MASK 0 0xf50 2 0 2 FMT_CRC_SIG_RED_MASK 0 15 FMT_CRC_SIG_GREEN_MASK 16 31 mmFMT4_FMT_CRC_SIG_BLUE_CONTROL_MASK 0 0xf51 2 0 2 FMT_CRC_SIG_BLUE_MASK 0 15 FMT_CRC_SIG_CONTROL_MASK 16 31 mmFMT4_FMT_CRC_SIG_RED_GREEN 0 0xf52 2 0 2 FMT_CRC_SIG_RED 0 15 FMT_CRC_SIG_GREEN 16 31 mmFMT4_FMT_CRC_SIG_BLUE_CONTROL 0 0xf53 2 0 2 FMT_CRC_SIG_BLUE 0 15 FMT_CRC_SIG_CONTROL 16 31 mmFMT4_FMT_SIDE_BY_SIDE_STEREO_CONTROL 0 0xf54 1 0 2 FMT_SIDE_BY_SIDE_STEREO_ACTIVE_WIDTH 0 12 mmFMT4_FMT_420_HBLANK_EARLY_START 0 0xf55 1 0 2 FMT_420_HBLANK_EARLY_START 0 11 mmDCP5_GRPH_ENABLE 0 0xf5a 2 0 2 GRPH_ENABLE 0 0 GRPH_KEYER_ALPHA_SEL 1 1 mmDCP5_GRPH_CONTROL 0 0xf5b 12 0 2 GRPH_DEPTH 0 1 GRPH_SE_ENABLE 2 2 GRPH_Z 4 5 GRPH_DIM_TYPE 6 7 GRPH_FORMAT 8 10 GRPH_NUM_BANKS 12 14 GRPH_ADDRESS_TRANSLATION_ENABLE 16 16 GRPH_PRIVILEGED_ACCESS_ENABLE 17 17 GRPH_NUM_SHADER_ENGINES 18 19 GRPH_SW_MODE 20 24 GRPH_NUM_PIPES 28 30 GRPH_COLOR_EXPANSION_MODE 31 31 mmDCP5_GRPH_LUT_10BIT_BYPASS 0 0xf5c 2 0 2 GRPH_LUT_10BIT_BYPASS_EN 8 8 GRPH_LUT_10BIT_BYPASS_DBL_BUF_EN 16 16 mmDCP5_GRPH_SWAP_CNTL 0 0xf5d 5 0 2 GRPH_ENDIAN_SWAP 0 1 GRPH_RED_CROSSBAR 4 5 GRPH_GREEN_CROSSBAR 6 7 GRPH_BLUE_CROSSBAR 8 9 GRPH_ALPHA_CROSSBAR 10 11 mmDCP5_GRPH_PRIMARY_SURFACE_ADDRESS 0 0xf5e 2 0 2 GRPH_PRIMARY_DFQ_ENABLE 0 0 GRPH_PRIMARY_SURFACE_ADDRESS 8 31 mmDCP5_GRPH_SECONDARY_SURFACE_ADDRESS 0 0xf5f 2 0 2 GRPH_SECONDARY_DFQ_ENABLE 0 0 GRPH_SECONDARY_SURFACE_ADDRESS 8 31 mmDCP5_GRPH_PITCH 0 0xf60 1 0 2 GRPH_PITCH 0 14 mmDCP5_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH 0 0xf61 1 0 2 GRPH_PRIMARY_SURFACE_ADDRESS_HIGH 0 7 mmDCP5_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH 0 0xf62 1 0 2 GRPH_SECONDARY_SURFACE_ADDRESS_HIGH 0 7 mmDCP5_GRPH_SURFACE_OFFSET_X 0 0xf63 1 0 2 GRPH_SURFACE_OFFSET_X 0 13 mmDCP5_GRPH_SURFACE_OFFSET_Y 0 0xf64 1 0 2 GRPH_SURFACE_OFFSET_Y 0 13 mmDCP5_GRPH_X_START 0 0xf65 1 0 2 GRPH_X_START 0 13 mmDCP5_GRPH_Y_START 0 0xf66 1 0 2 GRPH_Y_START 0 13 mmDCP5_GRPH_X_END 0 0xf67 1 0 2 GRPH_X_END 0 14 mmDCP5_GRPH_Y_END 0 0xf68 1 0 2 GRPH_Y_END 0 14 mmDCP5_INPUT_GAMMA_CONTROL 0 0xf69 1 0 2 GRPH_INPUT_GAMMA_MODE 0 0 mmDCP5_GRPH_UPDATE 0 0xf6a 11 0 2 GRPH_MODE_UPDATE_PENDING 0 0 GRPH_MODE_UPDATE_TAKEN 1 1 GRPH_SURFACE_UPDATE_PENDING 2 2 GRPH_SURFACE_UPDATE_TAKEN 3 3 GRPH_XDMA_FLIP_TYPE_CLEAR 8 8 GRPH_XDMA_DRR_MODE_ENABLE 9 9 GRPH_XDMA_MULTIFLIP_ENABLE 10 10 GRPH_UPDATE_LOCK 16 16 GRPH_SURFACE_IGNORE_UPDATE_LOCK 20 20 GRPH_MODE_DISABLE_MULTIPLE_UPDATE 24 24 GRPH_SURFACE_DISABLE_MULTIPLE_UPDATE 28 28 mmDCP5_GRPH_FLIP_CONTROL 0 0xf6b 4 0 2 GRPH_SURFACE_UPDATE_H_RETRACE_EN 0 0 GRPH_XDMA_SUPER_AA_EN 1 1 GRPH_SURFACE_UPDATE_IMMEDIATE_EN 4 4 GRPH_SURFACE_UPDATE_PENDING_MODE 5 5 mmDCP5_GRPH_SURFACE_ADDRESS_INUSE 0 0xf6c 1 0 2 GRPH_SURFACE_ADDRESS_INUSE 8 31 mmDCP5_GRPH_DFQ_CONTROL 0 0xf6d 3 0 2 GRPH_DFQ_RESET 0 0 GRPH_DFQ_SIZE 4 6 GRPH_DFQ_MIN_FREE_ENTRIES 8 10 mmDCP5_GRPH_DFQ_STATUS 0 0xf6e 4 0 2 GRPH_PRIMARY_DFQ_NUM_ENTRIES 0 3 GRPH_SECONDARY_DFQ_NUM_ENTRIES 4 7 GRPH_DFQ_RESET_FLAG 8 8 GRPH_DFQ_RESET_ACK 9 9 mmDCP5_GRPH_INTERRUPT_STATUS 0 0xf6f 2 0 2 GRPH_PFLIP_INT_OCCURRED 0 0 GRPH_PFLIP_INT_CLEAR 8 8 mmDCP5_GRPH_INTERRUPT_CONTROL 0 0xf70 2 0 2 GRPH_PFLIP_INT_MASK 0 0 GRPH_PFLIP_INT_TYPE 8 8 mmDCP5_GRPH_SURFACE_ADDRESS_HIGH_INUSE 0 0xf71 1 0 2 GRPH_SURFACE_ADDRESS_HIGH_INUSE 0 7 mmDCP5_GRPH_COMPRESS_SURFACE_ADDRESS 0 0xf72 1 0 2 GRPH_COMPRESS_SURFACE_ADDRESS 8 31 mmDCP5_GRPH_COMPRESS_PITCH 0 0xf73 1 0 2 GRPH_COMPRESS_PITCH 6 16 mmDCP5_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH 0 0xf74 1 0 2 GRPH_COMPRESS_SURFACE_ADDRESS_HIGH 0 7 mmDCP5_GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT 0 0xf75 1 0 2 GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT 0 7 mmDCP5_PRESCALE_GRPH_CONTROL 0 0xf76 5 0 2 GRPH_PRESCALE_SELECT 0 0 GRPH_PRESCALE_R_SIGN 1 1 GRPH_PRESCALE_G_SIGN 2 2 GRPH_PRESCALE_B_SIGN 3 3 GRPH_PRESCALE_BYPASS 4 4 mmDCP5_PRESCALE_VALUES_GRPH_R 0 0xf77 2 0 2 GRPH_PRESCALE_BIAS_R 0 15 GRPH_PRESCALE_SCALE_R 16 31 mmDCP5_PRESCALE_VALUES_GRPH_G 0 0xf78 2 0 2 GRPH_PRESCALE_BIAS_G 0 15 GRPH_PRESCALE_SCALE_G 16 31 mmDCP5_PRESCALE_VALUES_GRPH_B 0 0xf79 2 0 2 GRPH_PRESCALE_BIAS_B 0 15 GRPH_PRESCALE_SCALE_B 16 31 mmDCP5_INPUT_CSC_CONTROL 0 0xf7a 1 0 2 INPUT_CSC_GRPH_MODE 0 1 mmDCP5_INPUT_CSC_C11_C12 0 0xf7b 2 0 2 INPUT_CSC_C11 0 15 INPUT_CSC_C12 16 31 mmDCP5_INPUT_CSC_C13_C14 0 0xf7c 2 0 2 INPUT_CSC_C13 0 15 INPUT_CSC_C14 16 31 mmDCP5_INPUT_CSC_C21_C22 0 0xf7d 2 0 2 INPUT_CSC_C21 0 15 INPUT_CSC_C22 16 31 mmDCP5_INPUT_CSC_C23_C24 0 0xf7e 2 0 2 INPUT_CSC_C23 0 15 INPUT_CSC_C24 16 31 mmDCP5_INPUT_CSC_C31_C32 0 0xf7f 2 0 2 INPUT_CSC_C31 0 15 INPUT_CSC_C32 16 31 mmDCP5_INPUT_CSC_C33_C34 0 0xf80 2 0 2 INPUT_CSC_C33 0 15 INPUT_CSC_C34 16 31 mmDCP5_OUTPUT_CSC_CONTROL 0 0xf81 1 0 2 OUTPUT_CSC_GRPH_MODE 0 2 mmDCP5_OUTPUT_CSC_C11_C12 0 0xf82 2 0 2 OUTPUT_CSC_C11 0 15 OUTPUT_CSC_C12 16 31 mmDCP5_OUTPUT_CSC_C13_C14 0 0xf83 2 0 2 OUTPUT_CSC_C13 0 15 OUTPUT_CSC_C14 16 31 mmDCP5_OUTPUT_CSC_C21_C22 0 0xf84 2 0 2 OUTPUT_CSC_C21 0 15 OUTPUT_CSC_C22 16 31 mmDCP5_OUTPUT_CSC_C23_C24 0 0xf85 2 0 2 OUTPUT_CSC_C23 0 15 OUTPUT_CSC_C24 16 31 mmDCP5_OUTPUT_CSC_C31_C32 0 0xf86 2 0 2 OUTPUT_CSC_C31 0 15 OUTPUT_CSC_C32 16 31 mmDCP5_OUTPUT_CSC_C33_C34 0 0xf87 2 0 2 OUTPUT_CSC_C33 0 15 OUTPUT_CSC_C34 16 31 mmDCP5_COMM_MATRIXA_TRANS_C11_C12 0 0xf88 2 0 2 COMM_MATRIXA_TRANS_C11 0 15 COMM_MATRIXA_TRANS_C12 16 31 mmDCP5_COMM_MATRIXA_TRANS_C13_C14 0 0xf89 2 0 2 COMM_MATRIXA_TRANS_C13 0 15 COMM_MATRIXA_TRANS_C14 16 31 mmDCP5_COMM_MATRIXA_TRANS_C21_C22 0 0xf8a 2 0 2 COMM_MATRIXA_TRANS_C21 0 15 COMM_MATRIXA_TRANS_C22 16 31 mmDCP5_COMM_MATRIXA_TRANS_C23_C24 0 0xf8b 2 0 2 COMM_MATRIXA_TRANS_C23 0 15 COMM_MATRIXA_TRANS_C24 16 31 mmDCP5_COMM_MATRIXA_TRANS_C31_C32 0 0xf8c 2 0 2 COMM_MATRIXA_TRANS_C31 0 15 COMM_MATRIXA_TRANS_C32 16 31 mmDCP5_COMM_MATRIXA_TRANS_C33_C34 0 0xf8d 2 0 2 COMM_MATRIXA_TRANS_C33 0 15 COMM_MATRIXA_TRANS_C34 16 31 mmDCP5_COMM_MATRIXB_TRANS_C11_C12 0 0xf8e 2 0 2 COMM_MATRIXB_TRANS_C11 0 15 COMM_MATRIXB_TRANS_C12 16 31 mmDCP5_COMM_MATRIXB_TRANS_C13_C14 0 0xf8f 2 0 2 COMM_MATRIXB_TRANS_C13 0 15 COMM_MATRIXB_TRANS_C14 16 31 mmDCP5_COMM_MATRIXB_TRANS_C21_C22 0 0xf90 2 0 2 COMM_MATRIXB_TRANS_C21 0 15 COMM_MATRIXB_TRANS_C22 16 31 mmDCP5_COMM_MATRIXB_TRANS_C23_C24 0 0xf91 2 0 2 COMM_MATRIXB_TRANS_C23 0 15 COMM_MATRIXB_TRANS_C24 16 31 mmDCP5_COMM_MATRIXB_TRANS_C31_C32 0 0xf92 2 0 2 COMM_MATRIXB_TRANS_C31 0 15 COMM_MATRIXB_TRANS_C32 16 31 mmDCP5_COMM_MATRIXB_TRANS_C33_C34 0 0xf93 2 0 2 COMM_MATRIXB_TRANS_C33 0 15 COMM_MATRIXB_TRANS_C34 16 31 mmDCP5_DENORM_CONTROL 0 0xf94 2 0 2 DENORM_MODE 0 2 DENORM_14BIT_OUT 4 4 mmDCP5_OUT_ROUND_CONTROL 0 0xf95 1 0 2 OUT_ROUND_TRUNC_MODE 0 3 mmDCP5_OUT_CLAMP_CONTROL_R_CR 0 0xf96 2 0 2 OUT_CLAMP_MAX_R_CR 0 13 OUT_CLAMP_MIN_R_CR 16 29 mmDCP5_OUT_CLAMP_CONTROL_G_Y 0 0xf97 2 0 2 OUT_CLAMP_MAX_G_Y 0 13 OUT_CLAMP_MIN_G_Y 16 29 mmDCP5_OUT_CLAMP_CONTROL_B_CB 0 0xf98 2 0 2 OUT_CLAMP_MAX_B_CB 0 13 OUT_CLAMP_MIN_B_CB 16 29 mmDCP5_KEY_CONTROL 0 0xf99 1 0 2 KEY_MODE 1 2 mmDCP5_KEY_RANGE_ALPHA 0 0xf9a 2 0 2 KEY_ALPHA_LOW 0 15 KEY_ALPHA_HIGH 16 31 mmDCP5_KEY_RANGE_RED 0 0xf9b 2 0 2 KEY_RED_LOW 0 15 KEY_RED_HIGH 16 31 mmDCP5_KEY_RANGE_GREEN 0 0xf9c 2 0 2 KEY_GREEN_LOW 0 15 KEY_GREEN_HIGH 16 31 mmDCP5_KEY_RANGE_BLUE 0 0xf9d 2 0 2 KEY_BLUE_LOW 0 15 KEY_BLUE_HIGH 16 31 mmDCP5_DEGAMMA_CONTROL 0 0xf9e 3 0 2 GRPH_DEGAMMA_MODE 0 1 CURSOR2_DEGAMMA_MODE 8 9 CURSOR_DEGAMMA_MODE 12 13 mmDCP5_GAMUT_REMAP_CONTROL 0 0xf9f 1 0 2 GRPH_GAMUT_REMAP_MODE 0 1 mmDCP5_GAMUT_REMAP_C11_C12 0 0xfa0 2 0 2 GAMUT_REMAP_C11 0 15 GAMUT_REMAP_C12 16 31 mmDCP5_GAMUT_REMAP_C13_C14 0 0xfa1 2 0 2 GAMUT_REMAP_C13 0 15 GAMUT_REMAP_C14 16 31 mmDCP5_GAMUT_REMAP_C21_C22 0 0xfa2 2 0 2 GAMUT_REMAP_C21 0 15 GAMUT_REMAP_C22 16 31 mmDCP5_GAMUT_REMAP_C23_C24 0 0xfa3 2 0 2 GAMUT_REMAP_C23 0 15 GAMUT_REMAP_C24 16 31 mmDCP5_GAMUT_REMAP_C31_C32 0 0xfa4 2 0 2 GAMUT_REMAP_C31 0 15 GAMUT_REMAP_C32 16 31 mmDCP5_GAMUT_REMAP_C33_C34 0 0xfa5 2 0 2 GAMUT_REMAP_C33 0 15 GAMUT_REMAP_C34 16 31 mmDCP5_DCP_SPATIAL_DITHER_CNTL 0 0xfa6 6 0 2 DCP_SPATIAL_DITHER_EN 0 0 DCP_SPATIAL_DITHER_MODE 4 5 DCP_SPATIAL_DITHER_DEPTH 6 7 DCP_FRAME_RANDOM_ENABLE 8 8 DCP_RGB_RANDOM_ENABLE 9 9 DCP_HIGHPASS_RANDOM_ENABLE 10 10 mmDCP5_DCP_RANDOM_SEEDS 0 0xfa7 3 0 2 DCP_RAND_R_SEED 0 7 DCP_RAND_G_SEED 8 15 DCP_RAND_B_SEED 16 23 mmDCP5_DCP_FP_CONVERTED_FIELD 0 0xfa8 2 0 2 DCP_FP_CONVERTED_FIELD_DATA 0 17 DCP_FP_CONVERTED_FIELD_INDEX 20 26 mmDCP5_CUR_CONTROL 0 0xfa9 8 0 2 CURSOR_EN 0 0 CUR_INV_TRANS_CLAMP 4 4 CURSOR_MODE 8 9 CURSOR_MAX_OUTSTANDING_GROUP_NUM 11 11 CURSOR_BUSY_START_LINE_POSITION 12 15 CURSOR_2X_MAGNIFY 16 16 CURSOR_FORCE_MC_ON 20 20 CURSOR_URGENT_CONTROL 24 26 mmDCP5_CUR_SURFACE_ADDRESS 0 0xfaa 1 0 2 CURSOR_SURFACE_ADDRESS 0 31 mmDCP5_CUR_SIZE 0 0xfab 2 0 2 CURSOR_HEIGHT 0 6 CURSOR_WIDTH 16 22 mmDCP5_CUR_SURFACE_ADDRESS_HIGH 0 0xfac 1 0 2 CURSOR_SURFACE_ADDRESS_HIGH 0 7 mmDCP5_CUR_POSITION 0 0xfad 2 0 2 CURSOR_Y_POSITION 0 13 CURSOR_X_POSITION 16 29 mmDCP5_CUR_HOT_SPOT 0 0xfae 2 0 2 CURSOR_HOT_SPOT_Y 0 6 CURSOR_HOT_SPOT_X 16 22 mmDCP5_CUR_COLOR1 0 0xfaf 3 0 2 CUR_COLOR1_BLUE 0 7 CUR_COLOR1_GREEN 8 15 CUR_COLOR1_RED 16 23 mmDCP5_CUR_COLOR2 0 0xfb0 3 0 2 CUR_COLOR2_BLUE 0 7 CUR_COLOR2_GREEN 8 15 CUR_COLOR2_RED 16 23 mmDCP5_CUR_UPDATE 0 0xfb1 5 0 2 CURSOR_UPDATE_PENDING 0 0 CURSOR_UPDATE_TAKEN 1 1 CURSOR_UPDATE_LOCK 16 16 CURSOR_DISABLE_MULTIPLE_UPDATE 24 24 CURSOR_UPDATE_STEREO_MODE 25 26 mmDCP5_CUR_REQUEST_FILTER_CNTL 0 0xfbb 1 0 2 CUR_REQUEST_FILTER_DIS 0 0 mmDCP5_CUR_STEREO_CONTROL 0 0xfbc 3 0 2 CURSOR_STEREO_EN 0 0 CURSOR_PRIMARY_OFFSET 4 13 CURSOR_SECONDARY_OFFSET 16 25 mmDCP5_DC_LUT_RW_MODE 0 0xfbe 3 0 2 DC_LUT_RW_MODE 0 0 DC_LUT_ERROR 16 16 DC_LUT_ERROR_RST 17 17 mmDCP5_DC_LUT_RW_INDEX 0 0xfbf 1 0 2 DC_LUT_RW_INDEX 0 7 mmDCP5_DC_LUT_SEQ_COLOR 0 0xfc0 1 0 2 DC_LUT_SEQ_COLOR 0 15 mmDCP5_DC_LUT_PWL_DATA 0 0xfc1 2 0 2 DC_LUT_BASE 0 15 DC_LUT_DELTA 16 31 mmDCP5_DC_LUT_30_COLOR 0 0xfc2 3 0 2 DC_LUT_COLOR_10_BLUE 0 9 DC_LUT_COLOR_10_GREEN 10 19 DC_LUT_COLOR_10_RED 20 29 mmDCP5_DC_LUT_VGA_ACCESS_ENABLE 0 0xfc3 1 0 2 DC_LUT_VGA_ACCESS_ENABLE 0 0 mmDCP5_DC_LUT_WRITE_EN_MASK 0 0xfc4 1 0 2 DC_LUT_WRITE_EN_MASK 0 2 mmDCP5_DC_LUT_AUTOFILL 0 0xfc5 2 0 2 DC_LUT_AUTOFILL 0 0 DC_LUT_AUTOFILL_DONE 1 1 mmDCP5_DC_LUT_CONTROL 0 0xfc6 12 0 2 DC_LUT_INC_B 0 3 DC_LUT_DATA_B_SIGNED_EN 4 4 DC_LUT_DATA_B_FLOAT_POINT_EN 5 5 DC_LUT_DATA_B_FORMAT 6 7 DC_LUT_INC_G 8 11 DC_LUT_DATA_G_SIGNED_EN 12 12 DC_LUT_DATA_G_FLOAT_POINT_EN 13 13 DC_LUT_DATA_G_FORMAT 14 15 DC_LUT_INC_R 16 19 DC_LUT_DATA_R_SIGNED_EN 20 20 DC_LUT_DATA_R_FLOAT_POINT_EN 21 21 DC_LUT_DATA_R_FORMAT 22 23 mmDCP5_DC_LUT_BLACK_OFFSET_BLUE 0 0xfc7 1 0 2 DC_LUT_BLACK_OFFSET_BLUE 0 15 mmDCP5_DC_LUT_BLACK_OFFSET_GREEN 0 0xfc8 1 0 2 DC_LUT_BLACK_OFFSET_GREEN 0 15 mmDCP5_DC_LUT_BLACK_OFFSET_RED 0 0xfc9 1 0 2 DC_LUT_BLACK_OFFSET_RED 0 15 mmDCP5_DC_LUT_WHITE_OFFSET_BLUE 0 0xfca 1 0 2 DC_LUT_WHITE_OFFSET_BLUE 0 15 mmDCP5_DC_LUT_WHITE_OFFSET_GREEN 0 0xfcb 1 0 2 DC_LUT_WHITE_OFFSET_GREEN 0 15 mmDCP5_DC_LUT_WHITE_OFFSET_RED 0 0xfcc 1 0 2 DC_LUT_WHITE_OFFSET_RED 0 15 mmDCP5_DCP_CRC_CONTROL 0 0xfcd 3 0 2 DCP_CRC_ENABLE 0 0 DCP_CRC_SOURCE_SEL 2 4 DCP_CRC_LINE_SEL 8 9 mmDCP5_DCP_CRC_MASK 0 0xfce 1 0 2 DCP_CRC_MASK 0 31 mmDCP5_DCP_CRC_CURRENT 0 0xfcf 1 0 2 DCP_CRC_CURRENT 0 31 mmDCP5_DVMM_PTE_CONTROL 0 0xfd0 6 0 2 DVMM_USE_SINGLE_PTE 0 0 DVMM_PAGE_WIDTH 1 4 DVMM_PAGE_HEIGHT 5 8 DVMM_MIN_PTE_BEFORE_FLIP 9 18 DVMM_PTE_BUFFER_MODE0 20 20 DVMM_PTE_BUFFER_MODE1 21 21 mmDCP5_DCP_CRC_LAST 0 0xfd1 1 0 2 DCP_CRC_LAST 0 31 mmDCP5_DVMM_PTE_ARB_CONTROL 0 0xfd2 2 0 2 DVMM_PTE_REQ_PER_CHUNK 0 5 DVMM_MAX_PTE_REQ_OUTSTANDING 8 15 mmDCP5_GRPH_FLIP_RATE_CNTL 0 0xfd4 2 0 2 GRPH_FLIP_RATE 0 2 GRPH_FLIP_RATE_ENABLE 3 3 mmDCP5_DCP_GSL_CONTROL 0 0xfd5 11 0 2 DCP_GSL0_EN 0 0 DCP_GSL1_EN 1 1 DCP_GSL2_EN 2 2 DCP_GSL_HSYNC_FLIP_FORCE_DELAY 4 19 DCP_GSL_MASTER_EN 20 20 DCP_GSL_XDMA_GROUP 21 22 DCP_GSL_XDMA_GROUP_UNDERFLOW_EN 23 23 DCP_GSL_SYNC_SOURCE 24 25 DCP_GSL_USE_CHECKPOINT_WINDOW_IN_VSYNC 26 26 DCP_GSL_DELAY_SURFACE_UPDATE_PENDING 27 27 DCP_GSL_HSYNC_FLIP_CHECK_DELAY 28 31 mmDCP5_DCP_LB_DATA_GAP_BETWEEN_CHUNK 0 0xfd6 2 0 2 DCP_LB_GAP_BETWEEN_CHUNK_20BPP 0 3 DCP_LB_GAP_BETWEEN_CHUNK_30BPP 4 8 mmDCP5_GRPH_STEREOSYNC_FLIP 0 0xfdc 5 0 2 GRPH_STEREOSYNC_FLIP_EN 0 0 GRPH_STEREOSYNC_FLIP_MODE 8 9 GRPH_PRIMARY_SURFACE_PENDING 16 16 GRPH_SECONDARY_SURFACE_PENDING 17 17 GRPH_STEREOSYNC_SELECT_DISABLE 28 28 mmDCP5_HW_ROTATION 0 0xfde 1 0 2 GRPH_ROTATION_ANGLE 0 2 mmDCP5_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL 0 0xfdf 3 0 2 GRPH_XDMA_CACHE_UNDERFLOW_CNT_EN 0 0 GRPH_XDMA_CACHE_UNDERFLOW_CNT_MODE 1 1 GRPH_XDMA_CACHE_UNDERFLOW_FRAME_CNT 4 16 mmDCP5_REGAMMA_CONTROL 0 0xfe0 1 0 2 GRPH_REGAMMA_MODE 0 2 mmDCP5_REGAMMA_LUT_INDEX 0 0xfe1 1 0 2 REGAMMA_LUT_INDEX 0 8 mmDCP5_REGAMMA_LUT_DATA 0 0xfe2 1 0 2 REGAMMA_LUT_DATA 0 18 mmDCP5_REGAMMA_LUT_WRITE_EN_MASK 0 0xfe3 1 0 2 REGAMMA_LUT_WRITE_EN_MASK 0 2 mmDCP5_REGAMMA_CNTLA_START_CNTL 0 0xfe4 2 0 2 REGAMMA_CNTLA_EXP_REGION_START 0 17 REGAMMA_CNTLA_EXP_REGION_START_SEGMENT 20 26 mmDCP5_REGAMMA_CNTLA_SLOPE_CNTL 0 0xfe5 1 0 2 REGAMMA_CNTLA_EXP_REGION_LINEAR_SLOPE 0 17 mmDCP5_REGAMMA_CNTLA_END_CNTL1 0 0xfe6 1 0 2 REGAMMA_CNTLA_EXP_REGION_END 0 15 mmDCP5_REGAMMA_CNTLA_END_CNTL2 0 0xfe7 2 0 2 REGAMMA_CNTLA_EXP_REGION_END_SLOPE 0 15 REGAMMA_CNTLA_EXP_REGION_END_BASE 16 31 mmDCP5_REGAMMA_CNTLA_REGION_0_1 0 0xfe8 4 0 2 REGAMMA_CNTLA_EXP_REGION0_LUT_OFFSET 0 8 REGAMMA_CNTLA_EXP_REGION0_NUM_SEGMENTS 12 14 REGAMMA_CNTLA_EXP_REGION1_LUT_OFFSET 16 24 REGAMMA_CNTLA_EXP_REGION1_NUM_SEGMENTS 28 30 mmDCP5_REGAMMA_CNTLA_REGION_2_3 0 0xfe9 4 0 2 REGAMMA_CNTLA_EXP_REGION2_LUT_OFFSET 0 8 REGAMMA_CNTLA_EXP_REGION2_NUM_SEGMENTS 12 14 REGAMMA_CNTLA_EXP_REGION3_LUT_OFFSET 16 24 REGAMMA_CNTLA_EXP_REGION3_NUM_SEGMENTS 28 30 mmDCP5_REGAMMA_CNTLA_REGION_4_5 0 0xfea 4 0 2 REGAMMA_CNTLA_EXP_REGION4_LUT_OFFSET 0 8 REGAMMA_CNTLA_EXP_REGION4_NUM_SEGMENTS 12 14 REGAMMA_CNTLA_EXP_REGION5_LUT_OFFSET 16 24 REGAMMA_CNTLA_EXP_REGION5_NUM_SEGMENTS 28 30 mmDCP5_REGAMMA_CNTLA_REGION_6_7 0 0xfeb 4 0 2 REGAMMA_CNTLA_EXP_REGION6_LUT_OFFSET 0 8 REGAMMA_CNTLA_EXP_REGION6_NUM_SEGMENTS 12 14 REGAMMA_CNTLA_EXP_REGION7_LUT_OFFSET 16 24 REGAMMA_CNTLA_EXP_REGION7_NUM_SEGMENTS 28 30 mmDCP5_REGAMMA_CNTLA_REGION_8_9 0 0xfec 4 0 2 REGAMMA_CNTLA_EXP_REGION8_LUT_OFFSET 0 8 REGAMMA_CNTLA_EXP_REGION8_NUM_SEGMENTS 12 14 REGAMMA_CNTLA_EXP_REGION9_LUT_OFFSET 16 24 REGAMMA_CNTLA_EXP_REGION9_NUM_SEGMENTS 28 30 mmDCP5_REGAMMA_CNTLA_REGION_10_11 0 0xfed 4 0 2 REGAMMA_CNTLA_EXP_REGION10_LUT_OFFSET 0 8 REGAMMA_CNTLA_EXP_REGION10_NUM_SEGMENTS 12 14 REGAMMA_CNTLA_EXP_REGION11_LUT_OFFSET 16 24 REGAMMA_CNTLA_EXP_REGION11_NUM_SEGMENTS 28 30 mmDCP5_REGAMMA_CNTLA_REGION_12_13 0 0xfee 4 0 2 REGAMMA_CNTLA_EXP_REGION12_LUT_OFFSET 0 8 REGAMMA_CNTLA_EXP_REGION12_NUM_SEGMENTS 12 14 REGAMMA_CNTLA_EXP_REGION13_LUT_OFFSET 16 24 REGAMMA_CNTLA_EXP_REGION13_NUM_SEGMENTS 28 30 mmDCP5_REGAMMA_CNTLA_REGION_14_15 0 0xfef 4 0 2 REGAMMA_CNTLA_EXP_REGION14_LUT_OFFSET 0 8 REGAMMA_CNTLA_EXP_REGION14_NUM_SEGMENTS 12 14 REGAMMA_CNTLA_EXP_REGION15_LUT_OFFSET 16 24 REGAMMA_CNTLA_EXP_REGION15_NUM_SEGMENTS 28 30 mmDCP5_REGAMMA_CNTLB_START_CNTL 0 0xff0 2 0 2 REGAMMA_CNTLB_EXP_REGION_START 0 17 REGAMMA_CNTLB_EXP_REGION_START_SEGMENT 20 26 mmDCP5_REGAMMA_CNTLB_SLOPE_CNTL 0 0xff1 1 0 2 REGAMMA_CNTLB_EXP_REGION_LINEAR_SLOPE 0 17 mmDCP5_REGAMMA_CNTLB_END_CNTL1 0 0xff2 1 0 2 REGAMMA_CNTLB_EXP_REGION_END 0 15 mmDCP5_REGAMMA_CNTLB_END_CNTL2 0 0xff3 2 0 2 REGAMMA_CNTLB_EXP_REGION_END_SLOPE 0 15 REGAMMA_CNTLB_EXP_REGION_END_BASE 16 31 mmDCP5_REGAMMA_CNTLB_REGION_0_1 0 0xff4 4 0 2 REGAMMA_CNTLB_EXP_REGION0_LUT_OFFSET 0 8 REGAMMA_CNTLB_EXP_REGION0_NUM_SEGMENTS 12 14 REGAMMA_CNTLB_EXP_REGION1_LUT_OFFSET 16 24 REGAMMA_CNTLB_EXP_REGION1_NUM_SEGMENTS 28 30 mmDCP5_REGAMMA_CNTLB_REGION_2_3 0 0xff5 4 0 2 REGAMMA_CNTLB_EXP_REGION2_LUT_OFFSET 0 8 REGAMMA_CNTLB_EXP_REGION2_NUM_SEGMENTS 12 14 REGAMMA_CNTLB_EXP_REGION3_LUT_OFFSET 16 24 REGAMMA_CNTLB_EXP_REGION3_NUM_SEGMENTS 28 30 mmDCP5_REGAMMA_CNTLB_REGION_4_5 0 0xff6 4 0 2 REGAMMA_CNTLB_EXP_REGION4_LUT_OFFSET 0 8 REGAMMA_CNTLB_EXP_REGION4_NUM_SEGMENTS 12 14 REGAMMA_CNTLB_EXP_REGION5_LUT_OFFSET 16 24 REGAMMA_CNTLB_EXP_REGION5_NUM_SEGMENTS 28 30 mmDCP5_REGAMMA_CNTLB_REGION_6_7 0 0xff7 4 0 2 REGAMMA_CNTLB_EXP_REGION6_LUT_OFFSET 0 8 REGAMMA_CNTLB_EXP_REGION6_NUM_SEGMENTS 12 14 REGAMMA_CNTLB_EXP_REGION7_LUT_OFFSET 16 24 REGAMMA_CNTLB_EXP_REGION7_NUM_SEGMENTS 28 30 mmDCP5_REGAMMA_CNTLB_REGION_8_9 0 0xff8 4 0 2 REGAMMA_CNTLB_EXP_REGION8_LUT_OFFSET 0 8 REGAMMA_CNTLB_EXP_REGION8_NUM_SEGMENTS 12 14 REGAMMA_CNTLB_EXP_REGION9_LUT_OFFSET 16 24 REGAMMA_CNTLB_EXP_REGION9_NUM_SEGMENTS 28 30 mmDCP5_REGAMMA_CNTLB_REGION_10_11 0 0xff9 4 0 2 REGAMMA_CNTLB_EXP_REGION10_LUT_OFFSET 0 8 REGAMMA_CNTLB_EXP_REGION10_NUM_SEGMENTS 12 14 REGAMMA_CNTLB_EXP_REGION11_LUT_OFFSET 16 24 REGAMMA_CNTLB_EXP_REGION11_NUM_SEGMENTS 28 30 mmDCP5_REGAMMA_CNTLB_REGION_12_13 0 0xffa 4 0 2 REGAMMA_CNTLB_EXP_REGION12_LUT_OFFSET 0 8 REGAMMA_CNTLB_EXP_REGION12_NUM_SEGMENTS 12 14 REGAMMA_CNTLB_EXP_REGION13_LUT_OFFSET 16 24 REGAMMA_CNTLB_EXP_REGION13_NUM_SEGMENTS 28 30 mmDCP5_REGAMMA_CNTLB_REGION_14_15 0 0xffb 4 0 2 REGAMMA_CNTLB_EXP_REGION14_LUT_OFFSET 0 8 REGAMMA_CNTLB_EXP_REGION14_NUM_SEGMENTS 12 14 REGAMMA_CNTLB_EXP_REGION15_LUT_OFFSET 16 24 REGAMMA_CNTLB_EXP_REGION15_NUM_SEGMENTS 28 30 mmDCP5_ALPHA_CONTROL 0 0xffc 2 0 2 ALPHA_ROUND_TRUNC_MODE 0 0 CURSOR_ALPHA_BLND_ENA 1 1 mmDCP5_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS 0 0xffd 1 0 2 GRPH_XDMA_RECOVERY_SURFACE_ADDRESS 8 31 mmDCP5_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH 0 0xffe 1 0 2 GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH 0 7 mmDCP5_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS 0 0xfff 7 0 2 GRPH_XDMA_CACHE_UNDERFLOW_CNT 0 19 GRPH_XDMA_CACHE_UNDERFLOW_CNT_STATUS 24 24 GRPH_XDMA_CACHE_UNDERFLOW_FRAME_MASK 25 25 GRPH_XDMA_CACHE_UNDERFLOW_FRAME_ACK 26 26 GRPH_XDMA_CACHE_UNDERFLOW_INT 28 28 GRPH_XDMA_CACHE_UNDERFLOW_INT_MASK 29 29 GRPH_XDMA_CACHE_UNDERFLOW_INT_ACK 30 30 mmDCP5_GRPH_XDMA_FLIP_TIMEOUT 0 0x1000 3 0 2 GRPH_XDMA_FLIP_TIMEOUT_STATUS 0 0 GRPH_XDMA_FLIP_TIMEOUT_MASK 1 1 GRPH_XDMA_FLIP_TIMEOUT_ACK 2 2 mmDCP5_GRPH_XDMA_FLIP_AVG_DELAY 0 0x1001 2 0 2 GRPH_XDMA_FLIP_AVG_DELAY 0 15 GRPH_XDMA_FLIP_AVG_PERIOD 16 23 mmDCP5_GRPH_SURFACE_COUNTER_CONTROL 0 0x1002 3 0 2 GRPH_SURFACE_COUNTER_EN 0 0 GRPH_SURFACE_COUNTER_EVENT_SELECT 1 4 GRPH_SURFACE_COUNTER_ERR_WRAP_OCCURED 9 9 mmDCP5_GRPH_SURFACE_COUNTER_OUTPUT 0 0x1003 2 0 2 GRPH_SURFACE_COUNTER_MIN 0 15 GRPH_SURFACE_COUNTER_MAX 16 31 mmLB5_LB_DATA_FORMAT 0 0x101a 9 0 2 PIXEL_DEPTH 0 1 PIXEL_EXPAN_MODE 2 2 INTERLEAVE_EN 3 3 PIXEL_REDUCE_MODE 4 4 DYNAMIC_PIXEL_DEPTH 5 5 PREFILL_EN 8 8 PREFETCH 12 12 REQUEST_MODE 24 24 ALPHA_EN 31 31 mmLB5_LB_MEMORY_CTRL 0 0x101b 3 0 2 LB_MEMORY_SIZE 0 12 LB_NUM_PARTITIONS 16 19 LB_MEMORY_CONFIG 20 21 mmLB5_LB_MEMORY_SIZE_STATUS 0 0x101c 1 0 2 LB_MEMORY_SIZE_STATUS 0 12 mmLB5_LB_DESKTOP_HEIGHT 0 0x101d 1 0 2 DESKTOP_HEIGHT 0 14 mmLB5_LB_VLINE_START_END 0 0x101e 3 0 2 VLINE_START 0 13 VLINE_END 16 30 VLINE_INV 31 31 mmLB5_LB_VLINE2_START_END 0 0x101f 3 0 2 VLINE2_START 0 13 VLINE2_END 16 30 VLINE2_INV 31 31 mmLB5_LB_V_COUNTER 0 0x1020 1 0 2 V_COUNTER 0 14 mmLB5_LB_SNAPSHOT_V_COUNTER 0 0x1021 1 0 2 SNAPSHOT_V_COUNTER 0 14 mmLB5_LB_INTERRUPT_MASK 0 0x1022 3 0 2 VBLANK_INTERRUPT_MASK 0 0 VLINE_INTERRUPT_MASK 4 4 VLINE2_INTERRUPT_MASK 8 8 mmLB5_LB_VLINE_STATUS 0 0x1023 5 0 2 VLINE_OCCURRED 0 0 VLINE_ACK 4 4 VLINE_STAT 12 12 VLINE_INTERRUPT 16 16 VLINE_INTERRUPT_TYPE 17 17 mmLB5_LB_VLINE2_STATUS 0 0x1024 5 0 2 VLINE2_OCCURRED 0 0 VLINE2_ACK 4 4 VLINE2_STAT 12 12 VLINE2_INTERRUPT 16 16 VLINE2_INTERRUPT_TYPE 17 17 mmLB5_LB_VBLANK_STATUS 0 0x1025 5 0 2 VBLANK_OCCURRED 0 0 VBLANK_ACK 4 4 VBLANK_STAT 12 12 VBLANK_INTERRUPT 16 16 VBLANK_INTERRUPT_TYPE 17 17 mmLB5_LB_SYNC_RESET_SEL 0 0x1026 4 0 2 LB_SYNC_RESET_SEL 0 1 LB_SYNC_RESET_SEL2 4 4 LB_SYNC_RESET_DELAY 8 15 LB_SYNC_DURATION 22 23 mmLB5_LB_BLACK_KEYER_R_CR 0 0x1027 1 0 2 LB_BLACK_KEYER_R_CR 4 15 mmLB5_LB_BLACK_KEYER_G_Y 0 0x1028 1 0 2 LB_BLACK_KEYER_G_Y 4 15 mmLB5_LB_BLACK_KEYER_B_CB 0 0x1029 1 0 2 LB_BLACK_KEYER_B_CB 4 15 mmLB5_LB_KEYER_COLOR_CTRL 0 0x102a 2 0 2 LB_KEYER_COLOR_EN 0 0 LB_KEYER_COLOR_REP_EN 8 8 mmLB5_LB_KEYER_COLOR_R_CR 0 0x102b 1 0 2 LB_KEYER_COLOR_R_CR 4 15 mmLB5_LB_KEYER_COLOR_G_Y 0 0x102c 1 0 2 LB_KEYER_COLOR_G_Y 4 15 mmLB5_LB_KEYER_COLOR_B_CB 0 0x102d 1 0 2 LB_KEYER_COLOR_B_CB 4 15 mmLB5_LB_KEYER_COLOR_REP_R_CR 0 0x102e 1 0 2 LB_KEYER_COLOR_REP_R_CR 4 15 mmLB5_LB_KEYER_COLOR_REP_G_Y 0 0x102f 1 0 2 LB_KEYER_COLOR_REP_G_Y 4 15 mmLB5_LB_KEYER_COLOR_REP_B_CB 0 0x1030 1 0 2 LB_KEYER_COLOR_REP_B_CB 4 15 mmLB5_LB_BUFFER_LEVEL_STATUS 0 0x1031 4 0 2 REQ_FIFO_LEVEL 0 5 REQ_FIFO_FULL_CNTL 10 15 DATA_BUFFER_LEVEL 16 27 DATA_FIFO_FULL_CNTL 28 31 mmLB5_LB_BUFFER_URGENCY_CTRL 0 0x1032 2 0 2 LB_BUFFER_URGENCY_MARK_ON 0 11 LB_BUFFER_URGENCY_MARK_OFF 16 27 mmLB5_LB_BUFFER_URGENCY_STATUS 0 0x1033 2 0 2 LB_BUFFER_URGENCY_LEVEL 0 11 LB_BUFFER_URGENCY_STAT 16 16 mmLB5_LB_BUFFER_STATUS 0 0x1034 7 0 2 LB_BUFFER_EMPTY_MARGIN 0 3 LB_BUFFER_EMPTY_STAT 4 4 LB_BUFFER_EMPTY_OCCURRED 8 8 LB_BUFFER_EMPTY_ACK 12 12 LB_BUFFER_FULL_STAT 16 16 LB_BUFFER_FULL_OCCURRED 20 20 LB_BUFFER_FULL_ACK 24 24 mmLB5_LB_NO_OUTSTANDING_REQ_STATUS 0 0x1035 1 0 2 LB_NO_OUTSTANDING_REQ_STAT 0 0 mmLB5_MVP_AFR_FLIP_MODE 0 0x1036 1 0 2 MVP_AFR_FLIP_MODE 0 1 mmLB5_MVP_AFR_FLIP_FIFO_CNTL 0 0x1037 4 0 2 MVP_AFR_FLIP_FIFO_NUM_ENTRIES 0 3 MVP_AFR_FLIP_FIFO_RESET 4 4 MVP_AFR_FLIP_FIFO_RESET_FLAG 8 8 MVP_AFR_FLIP_FIFO_RESET_ACK 12 12 mmLB5_MVP_FLIP_LINE_NUM_INSERT 0 0x1038 4 0 2 MVP_FLIP_LINE_NUM_INSERT_MODE 0 1 MVP_FLIP_LINE_NUM_INSERT 8 22 MVP_FLIP_LINE_NUM_OFFSET 24 29 MVP_FLIP_AUTO_ENABLE 30 30 mmLB5_DC_MVP_LB_CONTROL 0 0x1039 7 0 2 MVP_SWAP_LOCK_IN_MODE 0 1 DC_MVP_SWAP_LOCK_OUT_SEL 8 8 DC_MVP_SWAP_LOCK_OUT_FORCE_ONE 12 12 DC_MVP_SWAP_LOCK_OUT_FORCE_ZERO 16 16 DC_MVP_SWAP_LOCK_STATUS 20 20 DC_MVP_SWAP_LOCK_IN_CAP 28 28 DC_MVP_SPARE_FLOPS 31 31 mmDCFE5_DCFE_CLOCK_CONTROL 0 0x105a 7 0 2 DISPCLK_R_DCFE_GATE_DISABLE 4 4 DISPCLK_G_DCP_GATE_DISABLE 8 8 DISPCLK_G_SCL_GATE_DISABLE 12 12 DISPCLK_G_PSCL_GATE_DISABLE 15 15 DISPCLK_G_PIPE_REQUEST_DIS_GATE_DISABLE 17 17 DCFE_TEST_CLK_SEL 24 28 DCFE_CLOCK_ENABLE 31 31 mmDCFE5_DCFE_SOFT_RESET 0 0x105b 6 0 2 DCP_PIXPIPE_SOFT_RESET 0 0 DCP_REQ_SOFT_RESET 1 1 SCL_ALU_SOFT_RESET 2 2 SCL_SOFT_RESET 3 3 CRTC_SOFT_RESET 4 4 PSCL_SOFT_RESET 5 5 mmDCFE5_DCFE_MEM_PWR_CTRL 0 0x105d 20 0 2 DCP_LUT_MEM_PWR_FORCE 0 1 DCP_LUT_MEM_PWR_DIS 2 2 DCP_REGAMMA_MEM_PWR_FORCE 3 4 DCP_REGAMMA_MEM_PWR_DIS 5 5 SCL_COEFF_MEM_PWR_FORCE 6 7 SCL_COEFF_MEM_PWR_DIS 8 8 DCP_CURSOR_MEM_PWR_FORCE 9 10 DCP_CURSOR_MEM_PWR_DIS 11 11 LB0_ALPHA_MEM_PWR_FORCE 12 13 LB0_ALPHA_MEM_PWR_DIS 14 14 LB1_ALPHA_MEM_PWR_FORCE 15 16 LB1_ALPHA_MEM_PWR_DIS 17 17 LB2_ALPHA_MEM_PWR_FORCE 18 19 LB2_ALPHA_MEM_PWR_DIS 20 20 LB0_MEM_PWR_FORCE 21 22 LB0_MEM_PWR_DIS 23 23 LB1_MEM_PWR_FORCE 24 25 LB1_MEM_PWR_DIS 26 26 LB2_MEM_PWR_FORCE 27 28 LB2_MEM_PWR_DIS 29 29 mmDCFE5_DCFE_MEM_PWR_CTRL2 0 0x105e 12 0 2 DCP_LUT_MEM_PWR_MODE_SEL 0 1 DCP_REGAMMA_MEM_PWR_MODE_SEL 2 3 SCL_COEFF_MEM_PWR_MODE_SEL 4 5 DCP_CURSOR_MEM_PWR_MODE_SEL 6 7 LB_ALPHA_MEM_PWR_MODE_SEL 8 9 LB_MEM_PWR_MODE_SEL 10 11 DCP_CURSOR2_MEM_PWR_MODE_SEL 12 13 BLND_MEM_PWR_MODE_SEL 14 15 BLND_MEM_PWR_FORCE 16 17 BLND_MEM_PWR_DIS 18 18 DCP_CURSOR2_MEM_PWR_FORCE 21 22 DCP_CURSOR2_MEM_PWR_DIS 23 23 mmDCFE5_DCFE_MEM_PWR_STATUS 0 0x105f 12 0 2 DCP_LUT_MEM_PWR_STATE 0 1 DCP_REGAMMA_MEM_PWR_STATE 2 3 SCL_COEFF_MEM_PWR_STATE 4 5 DCP_CURSOR_MEM_PWR_STATE 6 7 DCP_CURSOR2_MEM_PWR_STATE 8 9 LB0_ALPHA_MEM_PWR_STATE 10 11 LB1_ALPHA_MEM_PWR_STATE 12 13 LB2_ALPHA_MEM_PWR_STATE 14 15 LB0_MEM_PWR_STATE 16 17 LB1_MEM_PWR_STATE 18 19 LB2_MEM_PWR_STATE 20 21 BLND_MEM_PWR_STATE 22 23 mmDCFE5_DCFE_MISC 0 0x1060 1 0 2 DCFE_DPG_ALLOW_SR_ECO_EN 0 0 mmDCFE5_DCFE_FLUSH 0 0x1061 5 0 2 FLUSH_OCCURED 0 0 CLEAR_FLUSH_OCCURED 1 1 FLUSH_DEEP 2 2 CLEAR_FLUSH_DEEP 3 3 ALL_MC_REQ_RET 4 4 mmDC_PERFMON8_PERFCOUNTER_CNTL 0 0x106e 13 0 2 PERFCOUNTER_EVENT_SEL 0 8 PERFCOUNTER_CVALUE_SEL 9 11 PERFCOUNTER_INC_MODE 12 14 PERFCOUNTER_HW_CNTL_SEL 15 15 PERFCOUNTER_RUNEN_MODE 16 16 PERFCOUNTER_CNTOFF_SEL 17 21 PERFCOUNTER_CNTOFF_START_DIS 22 22 PERFCOUNTER_RESTART_EN 23 23 PERFCOUNTER_INT_EN 24 24 PERFCOUNTER_OFF_MASK 25 25 PERFCOUNTER_ACTIVE 26 26 PERFCOUNTER_INT_TYPE 27 27 PERFCOUNTER_CNTL_SEL 29 31 mmDC_PERFMON8_PERFCOUNTER_CNTL2 0 0x106f 4 0 2 PERFCOUNTER_COUNTED_VALUE_TYPE 0 1 PERFCOUNTER_HW_STOP1_SEL 2 2 PERFCOUNTER_HW_STOP2_SEL 3 3 PERFCOUNTER_CNTL2_SEL 29 31 mmDC_PERFMON8_PERFCOUNTER_STATE 0 0x1070 16 0 2 PERFCOUNTER_CNT0_STATE 0 1 PERFCOUNTER_STATE_SEL0 2 2 PERFCOUNTER_CNT1_STATE 4 5 PERFCOUNTER_STATE_SEL1 6 6 PERFCOUNTER_CNT2_STATE 8 9 PERFCOUNTER_STATE_SEL2 10 10 PERFCOUNTER_CNT3_STATE 12 13 PERFCOUNTER_STATE_SEL3 14 14 PERFCOUNTER_CNT4_STATE 16 17 PERFCOUNTER_STATE_SEL4 18 18 PERFCOUNTER_CNT5_STATE 20 21 PERFCOUNTER_STATE_SEL5 22 22 PERFCOUNTER_CNT6_STATE 24 25 PERFCOUNTER_STATE_SEL6 26 26 PERFCOUNTER_CNT7_STATE 28 29 PERFCOUNTER_STATE_SEL7 30 30 mmDC_PERFMON8_PERFMON_CNTL 0 0x1071 6 0 2 PERFMON_STATE 0 1 PERFMON_RPT_COUNT 8 27 PERFMON_CNTOFF_AND_OR 28 28 PERFMON_CNTOFF_INT_EN 29 29 PERFMON_CNTOFF_INT_STATUS 30 30 PERFMON_CNTOFF_INT_ACK 31 31 mmDC_PERFMON8_PERFMON_CNTL2 0 0x1072 4 0 2 PERFMON_CNTOFF_INT_TYPE 0 0 PERFMON_CLK_ENABLE 1 1 PERFMON_RUN_ENABLE_START_SEL 2 9 PERFMON_RUN_ENABLE_STOP_SEL 10 17 mmDC_PERFMON8_PERFMON_CVALUE_INT_MISC 0 0x1073 17 0 2 PERFCOUNTER_INT0_STATUS 0 0 PERFCOUNTER_INT1_STATUS 1 1 PERFCOUNTER_INT2_STATUS 2 2 PERFCOUNTER_INT3_STATUS 3 3 PERFCOUNTER_INT4_STATUS 4 4 PERFCOUNTER_INT5_STATUS 5 5 PERFCOUNTER_INT6_STATUS 6 6 PERFCOUNTER_INT7_STATUS 7 7 PERFCOUNTER_INT0_ACK 8 8 PERFCOUNTER_INT1_ACK 9 9 PERFCOUNTER_INT2_ACK 10 10 PERFCOUNTER_INT3_ACK 11 11 PERFCOUNTER_INT4_ACK 12 12 PERFCOUNTER_INT5_ACK 13 13 PERFCOUNTER_INT6_ACK 14 14 PERFCOUNTER_INT7_ACK 15 15 PERFMON_CVALUE_HI 16 31 mmDC_PERFMON8_PERFMON_CVALUE_LOW 0 0x1074 1 0 2 PERFMON_CVALUE_LOW 0 31 mmDC_PERFMON8_PERFMON_HI 0 0x1075 2 0 2 PERFMON_HI 0 15 PERFMON_READ_SEL 29 31 mmDC_PERFMON8_PERFMON_LOW 0 0x1076 1 0 2 PERFMON_LOW 0 31 mmDMIF_PG5_DPG_PIPE_ARBITRATION_CONTROL1 0 0x107a 2 0 2 PIXEL_DURATION 0 15 BASE_WEIGHT 16 31 mmDMIF_PG5_DPG_PIPE_ARBITRATION_CONTROL2 0 0x107b 2 0 2 TIME_WEIGHT 0 15 URGENCY_WEIGHT 16 31 mmDMIF_PG5_DPG_WATERMARK_MASK_CONTROL 0 0x107c 8 0 2 STUTTER_EXIT_SELF_REFRESH_WATERMARK_MASK 0 2 STUTTER_ENTER_SELF_REFRESH_WATERMARK_MASK 4 6 URGENCY_WATERMARK_MASK 8 10 URGENT_LEVEL_WATERMARK_MASK 12 14 PSTATE_CHANGE_WATERMARK_MASK 15 17 DISABLE_FLIP_URGENT 18 18 URGENT_LEVEL_RAMP_CONTROL 19 19 STATIC_URGENT_LEVEL 20 29 mmDMIF_PG5_DPG_PIPE_URGENCY_CONTROL 0 0x107d 2 0 2 URGENCY_LOW_WATERMARK 0 15 URGENCY_HIGH_WATERMARK 16 31 mmDMIF_PG5_DPG_PIPE_URGENT_LEVEL_CONTROL 0 0x107e 2 0 2 URGENT_LEVEL_LOW_WATERMARK 0 15 URGENT_LEVEL_HIGH_WATERMARK 16 31 mmDMIF_PG5_DPG_PIPE_STUTTER_CONTROL 0 0x107f 14 0 2 STUTTER_ENABLE 0 0 STUTTER_IGNORE_CURSOR 4 4 STUTTER_IGNORE_ICON 5 5 STUTTER_IGNORE_VGA 6 6 STUTTER_IGNORE_FBC 7 7 STUTTER_URGENT_IN_NOT_SELF_REFRESH 10 10 STUTTER_SELF_REFRESH_FORCE_ON 11 11 STUTTER_ENABLE_NONLPTCH 16 16 STUTTER_IGNORE_CURSOR_NONLPTCH 20 20 STUTTER_IGNORE_ICON_NONLPTCH 21 21 STUTTER_IGNORE_VGA_NONLPTCH 22 22 STUTTER_IGNORE_FBC_NONLPTCH 23 23 STUTTER_URGENT_IN_NOT_SELF_REFRESH_NONLPTCH 26 26 STUTTER_SELF_REFRESH_FORCE_ON_NONLPTCH 27 27 mmDMIF_PG5_DPG_PIPE_STUTTER_CONTROL2 0 0x1080 2 0 2 STUTTER_EXIT_SELF_REFRESH_WATERMARK 0 15 STUTTER_ENTER_SELF_REFRESH_WATERMARK 16 31 mmDMIF_PG5_DPG_PIPE_LOW_POWER_CONTROL 0 0x1081 7 0 2 PSTATE_CHANGE_ENABLE 0 0 DPM_ENABLE 1 1 PSTATE_CHANGE_URGENT_DURING_REQUEST 4 4 PSTATE_CHANGE_NOT_SELF_REFRESH_DURING_REQUEST 8 8 PSTATE_CHANGE_FORCE_ON 9 9 PSTATE_ALLOW_FOR_URGENT 10 10 PSTATE_CHANGE_WATERMARK 15 31 mmDMIF_PG5_DPG_REPEATER_PROGRAM 0 0x1082 2 0 2 REG_DPG_DMIFRC_REPEATER 0 2 REG_DMIFRC_DPG_REPEATER 4 6 mmDMIF_PG5_DPG_CHK_PRE_PROC_CNTL 0 0x1086 1 0 2 DPG_DISABLE_DMIF_BUF_CHK 0 0 mmDMIF_PG5_DPG_DVMM_STATUS 0 0x1087 4 0 2 DPG_DVMM_FORCED_FLIP_TO_UNMAPPED 0 0 DPG_DVMM_FORCED_FLIP_TO_MAPPED 1 1 DPG_DVMM_FORCED_FLIP_TO_UNMAPPED_CLR 4 4 DPG_DVMM_FORCED_FLIP_TO_MAPPED_CLR 5 5 mmSCL5_SCL_COEF_RAM_SELECT 0 0x109a 3 0 2 SCL_C_RAM_TAP_PAIR_IDX 0 3 SCL_C_RAM_PHASE 8 11 SCL_C_RAM_FILTER_TYPE 16 18 mmSCL5_SCL_COEF_RAM_TAP_DATA 0 0x109b 4 0 2 SCL_C_RAM_EVEN_TAP_COEF 0 13 SCL_C_RAM_EVEN_TAP_COEF_EN 15 15 SCL_C_RAM_ODD_TAP_COEF 16 29 SCL_C_RAM_ODD_TAP_COEF_EN 31 31 mmSCL5_SCL_MODE 0 0x109c 2 0 2 SCL_MODE 0 1 SCL_PSCL_EN 4 4 mmSCL5_SCL_TAP_CONTROL 0 0x109d 2 0 2 SCL_V_NUM_OF_TAPS 0 2 SCL_H_NUM_OF_TAPS 8 11 mmSCL5_SCL_CONTROL 0 0x109e 2 0 2 SCL_BOUNDARY_MODE 0 0 SCL_EARLY_EOL_MODE 4 4 mmSCL5_SCL_BYPASS_CONTROL 0 0x109f 1 0 2 SCL_BYPASS_MODE 0 1 mmSCL5_SCL_MANUAL_REPLICATE_CONTROL 0 0x10a0 2 0 2 SCL_V_MANUAL_REPLICATE_FACTOR 0 3 SCL_H_MANUAL_REPLICATE_FACTOR 8 11 mmSCL5_SCL_AUTOMATIC_MODE_CONTROL 0 0x10a1 2 0 2 SCL_V_CALC_AUTO_RATIO_EN 0 0 SCL_H_CALC_AUTO_RATIO_EN 16 16 mmSCL5_SCL_HORZ_FILTER_CONTROL 0 0x10a2 2 0 2 SCL_H_FILTER_PICK_NEAREST 0 0 SCL_H_2TAP_HARDCODE_COEF_EN 8 8 mmSCL5_SCL_HORZ_FILTER_SCALE_RATIO 0 0x10a3 1 0 2 SCL_H_SCALE_RATIO 0 25 mmSCL5_SCL_HORZ_FILTER_INIT 0 0x10a4 2 0 2 SCL_H_INIT_FRAC 0 23 SCL_H_INIT_INT 24 27 mmSCL5_SCL_VERT_FILTER_CONTROL 0 0x10a5 2 0 2 SCL_V_FILTER_PICK_NEAREST 0 0 SCL_V_2TAP_HARDCODE_COEF_EN 8 8 mmSCL5_SCL_VERT_FILTER_SCALE_RATIO 0 0x10a6 1 0 2 SCL_V_SCALE_RATIO 0 25 mmSCL5_SCL_VERT_FILTER_INIT 0 0x10a7 2 0 2 SCL_V_INIT_FRAC 0 23 SCL_V_INIT_INT 24 26 mmSCL5_SCL_VERT_FILTER_INIT_BOT 0 0x10a8 2 0 2 SCL_V_INIT_FRAC_BOT 0 23 SCL_V_INIT_INT_BOT 24 26 mmSCL5_SCL_ROUND_OFFSET 0 0x10a9 2 0 2 SCL_ROUND_OFFSET_RGB_Y 0 15 SCL_ROUND_OFFSET_CBCR 16 31 mmSCL5_SCL_UPDATE 0 0x10aa 4 0 2 SCL_UPDATE_PENDING 0 0 SCL_UPDATE_TAKEN 8 8 SCL_UPDATE_LOCK 16 16 SCL_COEF_UPDATE_COMPLETE 24 24 mmSCL5_SCL_F_SHARP_CONTROL 0 0x10ab 4 0 2 SCL_HF_SHARP_SCALE_FACTOR 0 2 SCL_HF_SHARP_EN 4 4 SCL_VF_SHARP_SCALE_FACTOR 8 10 SCL_VF_SHARP_EN 12 12 mmSCL5_SCL_ALU_CONTROL 0 0x10ac 1 0 2 SCL_ALU_DISABLE 0 0 mmSCL5_SCL_COEF_RAM_CONFLICT_STATUS 0 0x10ad 4 0 2 SCL_HOST_CONFLICT_FLAG 0 0 SCL_HOST_CONFLICT_ACK 8 8 SCL_HOST_CONFLICT_MASK 12 12 SCL_HOST_CONFLICT_INT_STATUS 16 16 mmSCL5_VIEWPORT_START_SECONDARY 0 0x10ae 2 0 2 VIEWPORT_Y_START_SECONDARY 0 13 VIEWPORT_X_START_SECONDARY 16 29 mmSCL5_VIEWPORT_START 0 0x10af 2 0 2 VIEWPORT_Y_START 0 13 VIEWPORT_X_START 16 29 mmSCL5_VIEWPORT_SIZE 0 0x10b0 2 0 2 VIEWPORT_HEIGHT 0 13 VIEWPORT_WIDTH 16 29 mmSCL5_EXT_OVERSCAN_LEFT_RIGHT 0 0x10b1 2 0 2 EXT_OVERSCAN_RIGHT 0 12 EXT_OVERSCAN_LEFT 16 28 mmSCL5_EXT_OVERSCAN_TOP_BOTTOM 0 0x10b2 2 0 2 EXT_OVERSCAN_BOTTOM 0 12 EXT_OVERSCAN_TOP 16 28 mmSCL5_SCL_MODE_CHANGE_DET1 0 0x10b3 3 0 2 SCL_MODE_CHANGE 0 0 SCL_MODE_CHANGE_ACK 4 4 SCL_ALU_H_SCALE_RATIO 7 27 mmSCL5_SCL_MODE_CHANGE_DET2 0 0x10b4 1 0 2 SCL_ALU_V_SCALE_RATIO 0 20 mmSCL5_SCL_MODE_CHANGE_DET3 0 0x10b5 2 0 2 SCL_ALU_SOURCE_HEIGHT 0 13 SCL_ALU_SOURCE_WIDTH 16 29 mmSCL5_SCL_MODE_CHANGE_MASK 0 0x10b6 1 0 2 SCL_MODE_CHANGE_MASK 0 0 mmBLND5_BLND_CONTROL 0 0x10c7 9 0 2 BLND_GLOBAL_GAIN 0 7 BLND_MODE 8 9 BLND_STEREO_TYPE 10 11 BLND_STEREO_POLARITY 12 12 BLND_FEEDTHROUGH_EN 13 13 BLND_ALPHA_MODE 16 17 BLND_ACTIVE_OVERLAP_ONLY 18 18 BLND_MULTIPLIED_MODE 20 20 BLND_GLOBAL_ALPHA 24 31 mmBLND5_BLND_SM_CONTROL2 0 0x10c8 6 0 2 SM_MODE 0 2 SM_FRAME_ALTERNATE 4 4 SM_FIELD_ALTERNATE 5 5 SM_FORCE_NEXT_FRAME_POL 8 9 SM_FORCE_NEXT_TOP_POL 16 17 SM_CURRENT_FRAME_POL 24 24 mmBLND5_BLND_CONTROL2 0 0x10c9 5 0 2 PTI_ENABLE 0 0 PTI_NEW_PIXEL_GAP 4 5 BLND_NEW_PIXEL_MODE 6 6 BLND_SUPERAA_DEGAMMA_EN 7 7 BLND_SUPERAA_REGAMMA_EN 8 8 mmBLND5_BLND_UPDATE 0 0x10ca 3 0 2 BLND_UPDATE_PENDING 0 0 BLND_UPDATE_TAKEN 8 8 BLND_UPDATE_LOCK 16 16 mmBLND5_BLND_UNDERFLOW_INTERRUPT 0 0x10cb 4 0 2 BLND_UNDERFLOW_INT_OCCURED 0 0 BLND_UNDERFLOW_INT_ACK 8 8 BLND_UNDERFLOW_INT_MASK 12 12 BLND_UNDERFLOW_INT_PIPE_INDEX 16 17 mmBLND5_BLND_V_UPDATE_LOCK 0 0x10cc 6 0 2 BLND_DCP_GRPH_V_UPDATE_LOCK 0 0 BLND_DCP_GRPH_SURF_V_UPDATE_LOCK 1 1 BLND_DCP_CUR_V_UPDATE_LOCK 16 16 BLND_SCL_V_UPDATE_LOCK 28 28 BLND_BLND_V_UPDATE_LOCK 29 29 BLND_V_UPDATE_LOCK_MODE 31 31 mmBLND5_BLND_REG_UPDATE_STATUS 0 0x10cd 10 0 2 DCP_BLNDC_GRPH_UPDATE_PENDING 0 0 DCP_BLNDO_GRPH_UPDATE_PENDING 1 1 DCP_BLNDC_GRPH_SURF_UPDATE_PENDING 2 2 DCP_BLNDO_GRPH_SURF_UPDATE_PENDING 3 3 DCP_BLNDC_CUR_UPDATE_PENDING 6 6 DCP_BLNDO_CUR_UPDATE_PENDING 7 7 SCL_BLNDC_UPDATE_PENDING 8 8 SCL_BLNDO_UPDATE_PENDING 9 9 BLND_BLNDC_UPDATE_PENDING 10 10 BLND_BLNDO_UPDATE_PENDING 11 11 mmCRTC5_CRTC_H_BLANK_EARLY_NUM 0 0x10d2 2 0 2 CRTC_H_BLANK_EARLY_NUM 0 9 CRTC_H_BLANK_EARLY_NUM_DIS 16 16 mmCRTC5_CRTC_H_TOTAL 0 0x10d3 1 0 2 CRTC_H_TOTAL 0 13 mmCRTC5_CRTC_H_BLANK_START_END 0 0x10d4 2 0 2 CRTC_H_BLANK_START 0 13 CRTC_H_BLANK_END 16 29 mmCRTC5_CRTC_H_SYNC_A 0 0x10d5 2 0 2 CRTC_H_SYNC_A_START 0 13 CRTC_H_SYNC_A_END 16 29 mmCRTC5_CRTC_H_SYNC_A_CNTL 0 0x10d6 3 0 2 CRTC_H_SYNC_A_POL 0 0 CRTC_COMP_SYNC_A_EN 16 16 CRTC_H_SYNC_A_CUTOFF 17 17 mmCRTC5_CRTC_H_SYNC_B 0 0x10d7 2 0 2 CRTC_H_SYNC_B_START 0 13 CRTC_H_SYNC_B_END 16 29 mmCRTC5_CRTC_H_SYNC_B_CNTL 0 0x10d8 3 0 2 CRTC_H_SYNC_B_POL 0 0 CRTC_COMP_SYNC_B_EN 16 16 CRTC_H_SYNC_B_CUTOFF 17 17 mmCRTC5_CRTC_VBI_END 0 0x10d9 2 0 2 CRTC_VBI_V_END 0 13 CRTC_VBI_H_END 16 29 mmCRTC5_CRTC_V_TOTAL 0 0x10da 1 0 2 CRTC_V_TOTAL 0 13 mmCRTC5_CRTC_V_TOTAL_MIN 0 0x10db 1 0 2 CRTC_V_TOTAL_MIN 0 13 mmCRTC5_CRTC_V_TOTAL_MAX 0 0x10dc 2 0 2 CRTC_V_TOTAL_MAX 0 13 CRTC_ALLOW_VBLANK_EXTENSION_FOR_MC_TRAINING 16 16 mmCRTC5_CRTC_V_TOTAL_CONTROL 0 0x10dd 6 0 2 CRTC_V_TOTAL_MIN_SEL 0 0 CRTC_V_TOTAL_MAX_SEL 4 4 CRTC_FORCE_LOCK_ON_EVENT 8 8 CRTC_FORCE_LOCK_TO_MASTER_VSYNC 12 12 CRTC_SET_V_TOTAL_MIN_MASK_EN 15 15 CRTC_SET_V_TOTAL_MIN_MASK 16 31 mmCRTC5_CRTC_V_TOTAL_INT_STATUS 0 0x10de 4 0 2 CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED 0 0 CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT 4 4 CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_ACK 8 8 CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_MSK 12 12 mmCRTC5_CRTC_VSYNC_NOM_INT_STATUS 0 0x10df 2 0 2 CRTC_VSYNC_NOM 0 0 CRTC_VSYNC_NOM_INT_CLEAR 4 4 mmCRTC5_CRTC_V_BLANK_START_END 0 0x10e0 2 0 2 CRTC_V_BLANK_START 0 13 CRTC_V_BLANK_END 16 29 mmCRTC5_CRTC_V_SYNC_A 0 0x10e1 2 0 2 CRTC_V_SYNC_A_START 0 13 CRTC_V_SYNC_A_END 16 29 mmCRTC5_CRTC_V_SYNC_A_CNTL 0 0x10e2 1 0 2 CRTC_V_SYNC_A_POL 0 0 mmCRTC5_CRTC_V_SYNC_B 0 0x10e3 2 0 2 CRTC_V_SYNC_B_START 0 13 CRTC_V_SYNC_B_END 16 29 mmCRTC5_CRTC_V_SYNC_B_CNTL 0 0x10e4 1 0 2 CRTC_V_SYNC_B_POL 0 0 mmCRTC5_CRTC_DTMTEST_CNTL 0 0x10e5 2 0 2 CRTC_DTMTEST_CRTC_EN 0 0 CRTC_DTMTEST_CLK_DIV 1 4 mmCRTC5_CRTC_DTMTEST_STATUS_POSITION 0 0x10e6 2 0 2 CRTC_DTMTEST_VERT_COUNT 0 13 CRTC_DTMTEST_HORZ_COUNT 16 29 mmCRTC5_CRTC_TRIGA_CNTL 0 0x10e7 11 0 2 CRTC_TRIGA_SOURCE_SELECT 0 4 CRTC_TRIGA_POLARITY_SELECT 5 7 CRTC_TRIGA_RESYNC_BYPASS_EN 8 8 CRTC_TRIGA_INPUT_STATUS 9 9 CRTC_TRIGA_POLARITY_STATUS 10 10 CRTC_TRIGA_OCCURRED 11 11 CRTC_TRIGA_RISING_EDGE_DETECT_CNTL 12 13 CRTC_TRIGA_FALLING_EDGE_DETECT_CNTL 16 17 CRTC_TRIGA_FREQUENCY_SELECT 20 21 CRTC_TRIGA_DELAY 24 28 CRTC_TRIGA_CLEAR 31 31 mmCRTC5_CRTC_TRIGA_MANUAL_TRIG 0 0x10e8 1 0 2 CRTC_TRIGA_MANUAL_TRIG 0 0 mmCRTC5_CRTC_TRIGB_CNTL 0 0x10e9 11 0 2 CRTC_TRIGB_SOURCE_SELECT 0 4 CRTC_TRIGB_POLARITY_SELECT 5 7 CRTC_TRIGB_RESYNC_BYPASS_EN 8 8 CRTC_TRIGB_INPUT_STATUS 9 9 CRTC_TRIGB_POLARITY_STATUS 10 10 CRTC_TRIGB_OCCURRED 11 11 CRTC_TRIGB_RISING_EDGE_DETECT_CNTL 12 13 CRTC_TRIGB_FALLING_EDGE_DETECT_CNTL 16 17 CRTC_TRIGB_FREQUENCY_SELECT 20 21 CRTC_TRIGB_DELAY 24 28 CRTC_TRIGB_CLEAR 31 31 mmCRTC5_CRTC_TRIGB_MANUAL_TRIG 0 0x10ea 1 0 2 CRTC_TRIGB_MANUAL_TRIG 0 0 mmCRTC5_CRTC_FORCE_COUNT_NOW_CNTL 0 0x10eb 5 0 2 CRTC_FORCE_COUNT_NOW_MODE 0 1 CRTC_FORCE_COUNT_NOW_CHECK 4 4 CRTC_FORCE_COUNT_NOW_TRIG_SEL 8 8 CRTC_FORCE_COUNT_NOW_OCCURRED 16 16 CRTC_FORCE_COUNT_NOW_CLEAR 24 24 mmCRTC5_CRTC_FLOW_CONTROL 0 0x10ec 4 0 2 CRTC_FLOW_CONTROL_SOURCE_SELECT 0 4 CRTC_FLOW_CONTROL_POLARITY 8 8 CRTC_FLOW_CONTROL_GRANULARITY 16 16 CRTC_FLOW_CONTROL_INPUT_STATUS 24 24 mmCRTC5_CRTC_STEREO_FORCE_NEXT_EYE 0 0x10ed 3 0 2 CRTC_STEREO_FORCE_NEXT_EYE 0 1 CRTC_AVSYNC_FRAME_COUNTER 8 15 CRTC_AVSYNC_LINE_COUNTER 16 28 mmCRTC5_CRTC_AVSYNC_COUNTER 0 0x10ee 1 0 2 CRTC_AVSYNC_COUNTER 0 31 mmCRTC5_CRTC_CONTROL 0 0x10ef 11 0 2 CRTC_MASTER_EN 0 0 CRTC_SYNC_RESET_SEL 4 4 CRTC_DISABLE_POINT_CNTL 8 9 CRTC_START_POINT_CNTL 12 12 CRTC_FIELD_NUMBER_CNTL 13 13 CRTC_FIELD_NUMBER_POLARITY 14 14 CRTC_CURRENT_MASTER_EN_STATE 16 16 CRTC_HBLANK_EARLY_CONTROL 20 22 CRTC_SOF_PULL_EN 29 29 CRTC_AVSYNC_LOCK_SNAPSHOT 30 30 CRTC_AVSYNC_VSYNC_N_HSYNC_MODE 31 31 mmCRTC5_CRTC_BLANK_CONTROL 0 0x10f0 3 0 2 CRTC_CURRENT_BLANK_STATE 0 0 CRTC_BLANK_DATA_EN 8 8 CRTC_BLANK_DE_MODE 16 16 mmCRTC5_CRTC_INTERLACE_CONTROL 0 0x10f1 2 0 2 CRTC_INTERLACE_ENABLE 0 0 CRTC_INTERLACE_FORCE_NEXT_FIELD 16 17 mmCRTC5_CRTC_INTERLACE_STATUS 0 0x10f2 2 0 2 CRTC_INTERLACE_CURRENT_FIELD 0 0 CRTC_INTERLACE_NEXT_FIELD 1 1 mmCRTC5_CRTC_FIELD_INDICATION_CONTROL 0 0x10f3 2 0 2 CRTC_FIELD_INDICATION_OUTPUT_POLARITY 0 0 CRTC_FIELD_ALIGNMENT 1 1 mmCRTC5_CRTC_PIXEL_DATA_READBACK0 0 0x10f4 2 0 2 CRTC_PIXEL_DATA_BLUE_CB 0 11 CRTC_PIXEL_DATA_GREEN_Y 16 27 mmCRTC5_CRTC_PIXEL_DATA_READBACK1 0 0x10f5 1 0 2 CRTC_PIXEL_DATA_RED_CR 0 11 mmCRTC5_CRTC_STATUS 0 0x10f6 9 0 2 CRTC_V_BLANK 0 0 CRTC_V_ACTIVE_DISP 1 1 CRTC_V_SYNC_A 2 2 CRTC_V_UPDATE 3 3 CRTC_V_START_LINE 4 4 CRTC_V_BLANK_3D_STRUCTURE 5 5 CRTC_H_BLANK 16 16 CRTC_H_ACTIVE_DISP 17 17 CRTC_H_SYNC_A 18 18 mmCRTC5_CRTC_STATUS_POSITION 0 0x10f7 2 0 2 CRTC_VERT_COUNT 0 13 CRTC_HORZ_COUNT 16 29 mmCRTC5_CRTC_NOM_VERT_POSITION 0 0x10f8 1 0 2 CRTC_VERT_COUNT_NOM 0 13 mmCRTC5_CRTC_STATUS_FRAME_COUNT 0 0x10f9 1 0 2 CRTC_FRAME_COUNT 0 23 mmCRTC5_CRTC_STATUS_VF_COUNT 0 0x10fa 1 0 2 CRTC_VF_COUNT 0 29 mmCRTC5_CRTC_STATUS_HV_COUNT 0 0x10fb 1 0 2 CRTC_HV_COUNT 0 29 mmCRTC5_CRTC_COUNT_CONTROL 0 0x10fc 2 0 2 CRTC_HORZ_COUNT_BY2_EN 0 0 CRTC_HORZ_REPETITION_COUNT 1 4 mmCRTC5_CRTC_COUNT_RESET 0 0x10fd 1 0 2 CRTC_RESET_FRAME_COUNT 0 0 mmCRTC5_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE 0 0x10fe 1 0 2 CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE 0 0 mmCRTC5_CRTC_VERT_SYNC_CONTROL 0 0x10ff 3 0 2 CRTC_FORCE_VSYNC_NEXT_LINE_OCCURRED 0 0 CRTC_FORCE_VSYNC_NEXT_LINE_CLEAR 8 8 CRTC_AUTO_FORCE_VSYNC_MODE 16 17 mmCRTC5_CRTC_STEREO_STATUS 0 0x1100 5 0 2 CRTC_STEREO_CURRENT_EYE 0 0 CRTC_STEREO_SYNC_OUTPUT 8 8 CRTC_STEREO_SYNC_SELECT 16 16 CRTC_STEREO_EYE_FLAG 20 20 CRTC_STEREO_FORCE_NEXT_EYE_PENDING 24 25 mmCRTC5_CRTC_STEREO_CONTROL 0 0x1101 8 0 2 CRTC_STEREO_SYNC_OUTPUT_LINE_NUM 0 13 CRTC_STEREO_SYNC_OUTPUT_POLARITY 15 15 CRTC_STEREO_SYNC_SELECT_POLARITY 16 16 CRTC_STEREO_EYE_FLAG_POLARITY 17 17 CRTC_DISABLE_STEREOSYNC_OUTPUT_FOR_DP 18 18 CRTC_DISABLE_FIELD_NUM 19 19 CRTC_DISABLE_V_BLANK_FOR_DP_FIX 20 20 CRTC_STEREO_EN 24 24 mmCRTC5_CRTC_SNAPSHOT_STATUS 0 0x1102 3 0 2 CRTC_SNAPSHOT_OCCURRED 0 0 CRTC_SNAPSHOT_CLEAR 1 1 CRTC_SNAPSHOT_MANUAL_TRIGGER 2 2 mmCRTC5_CRTC_SNAPSHOT_CONTROL 0 0x1103 1 0 2 CRTC_AUTO_SNAPSHOT_TRIG_SEL 0 1 mmCRTC5_CRTC_SNAPSHOT_POSITION 0 0x1104 2 0 2 CRTC_SNAPSHOT_VERT_COUNT 0 13 CRTC_SNAPSHOT_HORZ_COUNT 16 29 mmCRTC5_CRTC_SNAPSHOT_FRAME 0 0x1105 1 0 2 CRTC_SNAPSHOT_FRAME_COUNT 0 23 mmCRTC5_CRTC_START_LINE_CONTROL 0 0x1106 5 0 2 CRTC_PROGRESSIVE_START_LINE_EARLY 0 0 CRTC_INTERLACE_START_LINE_EARLY 1 1 CRTC_PREFETCH_EN 2 2 CRTC_LEGACY_REQUESTOR_EN 8 8 CRTC_ADVANCED_START_LINE_POSITION 12 19 mmCRTC5_CRTC_INTERRUPT_CONTROL 0 0x1107 16 0 2 CRTC_SNAPSHOT_INT_MSK 0 0 CRTC_SNAPSHOT_INT_TYPE 1 1 CRTC_V_UPDATE_INT_MSK 4 4 CRTC_V_UPDATE_INT_TYPE 5 5 CRTC_FORCE_COUNT_NOW_INT_MSK 8 8 CRTC_FORCE_COUNT_NOW_INT_TYPE 9 9 CRTC_FORCE_VSYNC_NEXT_LINE_INT_MSK 16 16 CRTC_FORCE_VSYNC_NEXT_LINE_INT_TYPE 17 17 CRTC_TRIGA_INT_MSK 24 24 CRTC_TRIGB_INT_MSK 25 25 CRTC_TRIGA_INT_TYPE 26 26 CRTC_TRIGB_INT_TYPE 27 27 CRTC_VSYNC_NOM_INT_MSK 28 28 CRTC_VSYNC_NOM_INT_TYPE 29 29 CRTC_GSL_VSYNC_GAP_INT_MSK 30 30 CRTC_GSL_VSYNC_GAP_INT_TYPE 31 31 mmCRTC5_CRTC_UPDATE_LOCK 0 0x1108 1 0 2 CRTC_UPDATE_LOCK 0 0 mmCRTC5_CRTC_DOUBLE_BUFFER_CONTROL 0 0x1109 5 0 2 CRTC_UPDATE_PENDING 0 0 CRTC_UPDATE_INSTANTLY 8 8 CRTC_BLANK_DATA_DOUBLE_BUFFER_EN 16 16 CRTC_RANGE_TIMING_DBUF_UPDATE_MODE 24 24 CRTC_RANGE_TIMING_DBUF_UPDATE_PENDING 25 25 mmCRTC5_CRTC_VGA_PARAMETER_CAPTURE_MODE 0 0x110a 1 0 2 CRTC_VGA_PARAMETER_CAPTURE_MODE 0 0 mmCRTC5_CRTC_TEST_PATTERN_CONTROL 0 0x110b 4 0 2 CRTC_TEST_PATTERN_EN 0 0 CRTC_TEST_PATTERN_MODE 8 10 CRTC_TEST_PATTERN_DYNAMIC_RANGE 16 16 CRTC_TEST_PATTERN_COLOR_FORMAT 24 31 mmCRTC5_CRTC_TEST_PATTERN_PARAMETERS 0 0x110c 5 0 2 CRTC_TEST_PATTERN_INC0 0 3 CRTC_TEST_PATTERN_INC1 4 7 CRTC_TEST_PATTERN_VRES 8 11 CRTC_TEST_PATTERN_HRES 12 15 CRTC_TEST_PATTERN_RAMP0_OFFSET 16 31 mmCRTC5_CRTC_TEST_PATTERN_COLOR 0 0x110d 2 0 2 CRTC_TEST_PATTERN_DATA 0 15 CRTC_TEST_PATTERN_MASK 16 21 mmCRTC5_CRTC_MASTER_UPDATE_LOCK 0 0x110e 3 0 2 MASTER_UPDATE_LOCK 0 0 GSL_CONTROL_MASTER_UPDATE_LOCK 8 8 UNDERFLOW_UPDATE_LOCK 16 16 mmCRTC5_CRTC_MASTER_UPDATE_MODE 0 0x110f 2 0 2 MASTER_UPDATE_MODE 0 2 MASTER_UPDATE_INTERLACED_MODE 16 17 mmCRTC5_CRTC_MVP_INBAND_CNTL_INSERT 0 0x1110 2 0 2 CRTC_MVP_INBAND_OUT_MODE 0 1 CRTC_MVP_INBAND_CNTL_CHAR_INSERT 8 31 mmCRTC5_CRTC_MVP_INBAND_CNTL_INSERT_TIMER 0 0x1111 1 0 2 CRTC_MVP_INBAND_CNTL_CHAR_INSERT_TIMER 0 7 mmCRTC5_CRTC_MVP_STATUS 0 0x1112 4 0 2 CRTC_FLIP_NOW_OCCURRED 0 0 CRTC_AFR_HSYNC_SWITCH_DONE_OCCURRED 4 4 CRTC_FLIP_NOW_CLEAR 16 16 CRTC_AFR_HSYNC_SWITCH_DONE_CLEAR 20 20 mmCRTC5_CRTC_MASTER_EN 0 0x1113 1 0 2 CRTC_MASTER_EN 0 0 mmCRTC5_CRTC_ALLOW_STOP_OFF_V_CNT 0 0x1114 2 0 2 CRTC_ALLOW_STOP_OFF_V_CNT 0 7 CRTC_DISABLE_ALLOW_STOP_OFF_V_CNT 16 16 mmCRTC5_CRTC_V_UPDATE_INT_STATUS 0 0x1115 2 0 2 CRTC_V_UPDATE_INT_OCCURRED 0 0 CRTC_V_UPDATE_INT_CLEAR 8 8 mmCRTC5_CRTC_OVERSCAN_COLOR 0 0x1117 3 0 2 CRTC_OVERSCAN_COLOR_BLUE 0 9 CRTC_OVERSCAN_COLOR_GREEN 10 19 CRTC_OVERSCAN_COLOR_RED 20 29 mmCRTC5_CRTC_OVERSCAN_COLOR_EXT 0 0x1118 3 0 2 CRTC_OVERSCAN_COLOR_BLUE_EXT 0 1 CRTC_OVERSCAN_COLOR_GREEN_EXT 8 9 CRTC_OVERSCAN_COLOR_RED_EXT 16 17 mmCRTC5_CRTC_BLANK_DATA_COLOR 0 0x1119 3 0 2 CRTC_BLANK_DATA_COLOR_BLUE_CB 0 9 CRTC_BLANK_DATA_COLOR_GREEN_Y 10 19 CRTC_BLANK_DATA_COLOR_RED_CR 20 29 mmCRTC5_CRTC_BLANK_DATA_COLOR_EXT 0 0x111a 3 0 2 CRTC_BLANK_DATA_COLOR_BLUE_CB_EXT 0 1 CRTC_BLANK_DATA_COLOR_GREEN_Y_EXT 8 9 CRTC_BLANK_DATA_COLOR_RED_CR_EXT 16 17 mmCRTC5_CRTC_BLACK_COLOR 0 0x111b 3 0 2 CRTC_BLACK_COLOR_B_CB 0 9 CRTC_BLACK_COLOR_G_Y 10 19 CRTC_BLACK_COLOR_R_CR 20 29 mmCRTC5_CRTC_BLACK_COLOR_EXT 0 0x111c 3 0 2 CRTC_BLACK_COLOR_B_CB_EXT 0 1 CRTC_BLACK_COLOR_G_Y_EXT 8 9 CRTC_BLACK_COLOR_R_CR_EXT 16 17 mmCRTC5_CRTC_VERTICAL_INTERRUPT0_POSITION 0 0x111d 2 0 2 CRTC_VERTICAL_INTERRUPT0_LINE_START 0 13 CRTC_VERTICAL_INTERRUPT0_LINE_END 16 29 mmCRTC5_CRTC_VERTICAL_INTERRUPT0_CONTROL 0 0x111e 6 0 2 CRTC_VERTICAL_INTERRUPT0_OUTPUT_POLARITY 4 4 CRTC_VERTICAL_INTERRUPT0_INT_ENABLE 8 8 CRTC_VERTICAL_INTERRUPT0_STATUS 12 12 CRTC_VERTICAL_INTERRUPT0_INT_STATUS 16 16 CRTC_VERTICAL_INTERRUPT0_CLEAR 20 20 CRTC_VERTICAL_INTERRUPT0_INT_TYPE 24 24 mmCRTC5_CRTC_VERTICAL_INTERRUPT1_POSITION 0 0x111f 1 0 2 CRTC_VERTICAL_INTERRUPT1_LINE_START 0 13 mmCRTC5_CRTC_VERTICAL_INTERRUPT1_CONTROL 0 0x1120 5 0 2 CRTC_VERTICAL_INTERRUPT1_INT_ENABLE 8 8 CRTC_VERTICAL_INTERRUPT1_STATUS 12 12 CRTC_VERTICAL_INTERRUPT1_INT_STATUS 16 16 CRTC_VERTICAL_INTERRUPT1_CLEAR 20 20 CRTC_VERTICAL_INTERRUPT1_INT_TYPE 24 24 mmCRTC5_CRTC_VERTICAL_INTERRUPT2_POSITION 0 0x1121 1 0 2 CRTC_VERTICAL_INTERRUPT2_LINE_START 0 13 mmCRTC5_CRTC_VERTICAL_INTERRUPT2_CONTROL 0 0x1122 5 0 2 CRTC_VERTICAL_INTERRUPT2_INT_ENABLE 8 8 CRTC_VERTICAL_INTERRUPT2_STATUS 12 12 CRTC_VERTICAL_INTERRUPT2_INT_STATUS 16 16 CRTC_VERTICAL_INTERRUPT2_CLEAR 20 20 CRTC_VERTICAL_INTERRUPT2_INT_TYPE 24 24 mmCRTC5_CRTC_CRC_CNTL 0 0x1123 7 0 2 CRTC_CRC_EN 0 0 CRTC_CRC_CONT_EN 4 4 CRTC_CRC_STEREO_MODE 8 9 CRTC_CRC_INTERLACE_MODE 12 13 CRTC_CRC_USE_NEW_AND_REPEATED_PIXELS 16 16 CRTC_CRC0_SELECT 20 22 CRTC_CRC1_SELECT 24 26 mmCRTC5_CRTC_CRC0_WINDOWA_X_CONTROL 0 0x1124 2 0 2 CRTC_CRC0_WINDOWA_X_START 0 13 CRTC_CRC0_WINDOWA_X_END 16 29 mmCRTC5_CRTC_CRC0_WINDOWA_Y_CONTROL 0 0x1125 2 0 2 CRTC_CRC0_WINDOWA_Y_START 0 13 CRTC_CRC0_WINDOWA_Y_END 16 29 mmCRTC5_CRTC_CRC0_WINDOWB_X_CONTROL 0 0x1126 2 0 2 CRTC_CRC0_WINDOWB_X_START 0 13 CRTC_CRC0_WINDOWB_X_END 16 29 mmCRTC5_CRTC_CRC0_WINDOWB_Y_CONTROL 0 0x1127 2 0 2 CRTC_CRC0_WINDOWB_Y_START 0 13 CRTC_CRC0_WINDOWB_Y_END 16 29 mmCRTC5_CRTC_CRC0_DATA_RG 0 0x1128 2 0 2 CRC0_R_CR 0 15 CRC0_G_Y 16 31 mmCRTC5_CRTC_CRC0_DATA_B 0 0x1129 1 0 2 CRC0_B_CB 0 15 mmCRTC5_CRTC_CRC1_WINDOWA_X_CONTROL 0 0x112a 2 0 2 CRTC_CRC1_WINDOWA_X_START 0 13 CRTC_CRC1_WINDOWA_X_END 16 29 mmCRTC5_CRTC_CRC1_WINDOWA_Y_CONTROL 0 0x112b 2 0 2 CRTC_CRC1_WINDOWA_Y_START 0 13 CRTC_CRC1_WINDOWA_Y_END 16 29 mmCRTC5_CRTC_CRC1_WINDOWB_X_CONTROL 0 0x112c 2 0 2 CRTC_CRC1_WINDOWB_X_START 0 13 CRTC_CRC1_WINDOWB_X_END 16 29 mmCRTC5_CRTC_CRC1_WINDOWB_Y_CONTROL 0 0x112d 2 0 2 CRTC_CRC1_WINDOWB_Y_START 0 13 CRTC_CRC1_WINDOWB_Y_END 16 29 mmCRTC5_CRTC_CRC1_DATA_RG 0 0x112e 2 0 2 CRC1_R_CR 0 15 CRC1_G_Y 16 31 mmCRTC5_CRTC_CRC1_DATA_B 0 0x112f 1 0 2 CRC1_B_CB 0 15 mmCRTC5_CRTC_EXT_TIMING_SYNC_CONTROL 0 0x1130 11 0 2 CRTC_EXT_TIMING_SYNC_ENABLE 0 1 CRTC_EXT_TIMING_SYNC_HCOUNT_MODE_ENABLE 3 3 CRTC_EXT_TIMING_SYNC_JITTER_FILTERING_ENABLE 4 4 CRTC_EXT_TIMING_SYNC_JITTER_FILTERING_WINDOW 5 6 CRTC_EXT_TIMING_SYNC_WINDOW_ENABLE 8 8 CRTC_EXT_TIMING_SYNC_WINDOW_UPDATE 9 9 CRTC_EXT_TIMING_SYNC_VSYNC_POLARITY 12 12 CRTC_EXT_TIMING_SYNC_HSYNC_POLARITY 13 13 CRTC_EXT_TIMING_SYNC_INTERLACE_MODE 14 14 CRTC_EXT_TIMING_SYNC_MASTER_FRAME_RATE 24 26 CRTC_EXT_TIMING_SYNC_SLAVE_FRAME_RATE 28 30 mmCRTC5_CRTC_EXT_TIMING_SYNC_WINDOW_START 0 0x1131 2 0 2 CRTC_EXT_TIMING_SYNC_WINDOW_START_X 0 13 CRTC_EXT_TIMING_SYNC_WINDOW_START_Y 16 29 mmCRTC5_CRTC_EXT_TIMING_SYNC_WINDOW_END 0 0x1132 2 0 2 CRTC_EXT_TIMING_SYNC_WINDOW_END_X 0 13 CRTC_EXT_TIMING_SYNC_WINDOW_END_Y 16 29 mmCRTC5_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL 0 0x1133 6 0 2 CRTC_EXT_TIMING_SYNC_LOSS_INT_ENABLE 0 0 CRTC_EXT_TIMING_SYNC_LOSS_STATUS 4 4 CRTC_EXT_TIMING_SYNC_LOSS_INT_STATUS 8 8 CRTC_EXT_TIMING_SYNC_LOSS_CLEAR 16 16 CRTC_EXT_TIMING_SYNC_LOSS_INT_TYPE 20 20 CRTC_EXT_TIMING_SYNC_LOSS_FRAME_COUNT 29 31 mmCRTC5_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL 0 0x1134 5 0 2 CRTC_EXT_TIMING_SYNC_INT_ENABLE 0 0 CRTC_EXT_TIMING_SYNC_STATUS 4 4 CRTC_EXT_TIMING_SYNC_INT_STATUS 8 8 CRTC_EXT_TIMING_SYNC_CLEAR 16 16 CRTC_EXT_TIMING_SYNC_INT_TYPE 20 20 mmCRTC5_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL 0 0x1135 5 0 2 CRTC_EXT_TIMING_SYNC_SIGNAL_INT_ENABLE 0 0 CRTC_EXT_TIMING_SYNC_SIGNAL_STATUS 4 4 CRTC_EXT_TIMING_SYNC_SIGNAL_INT_STATUS 8 8 CRTC_EXT_TIMING_SYNC_SIGNAL_CLEAR 16 16 CRTC_EXT_TIMING_SYNC_SIGNAL_INT_TYPE 20 20 mmCRTC5_CRTC_STATIC_SCREEN_CONTROL 0 0x1136 9 0 2 CRTC_STATIC_SCREEN_EVENT_MASK 0 15 CRTC_STATIC_SCREEN_FRAME_COUNT 16 23 CRTC_CPU_SS_INT_ENABLE 24 24 CRTC_SS_STATUS 25 25 CRTC_CPU_SS_INT_STATUS 26 26 CRTC_CPU_SS_INT_CLEAR 27 27 CRTC_CPU_SS_INT_TYPE 28 28 CRTC_STATIC_SCREEN_OVERRIDE 30 30 CRTC_STATIC_SCREEN_OVERRIDE_VALUE 31 31 mmCRTC5_CRTC_3D_STRUCTURE_CONTROL 0 0x1137 7 0 2 CRTC_3D_STRUCTURE_EN 0 0 CRTC_3D_STRUCTURE_EN_DB 4 4 CRTC_3D_STRUCTURE_V_UPDATE_MODE 8 9 CRTC_3D_STRUCTURE_STEREO_SEL_OVR 12 12 CRTC_3D_STRUCTURE_F_COUNT_RESET 16 16 CRTC_3D_STRUCTURE_F_COUNT_RESET_PENDING 17 17 CRTC_3D_STRUCTURE_F_COUNT 18 19 mmCRTC5_CRTC_GSL_VSYNC_GAP 0 0x1138 8 0 2 CRTC_GSL_VSYNC_GAP_LIMIT 0 7 CRTC_GSL_VSYNC_GAP_DELAY 8 15 CRTC_GSL_VSYNC_GAP_SOURCE_SEL 16 16 CRTC_GSL_VSYNC_GAP_MODE 17 18 CRTC_GSL_VSYNC_GAP_CLEAR 19 19 CRTC_GSL_VSYNC_GAP_OCCURRED 20 20 CRTC_GSL_VSYNC_GAP_MASTER_FASTER 23 23 CRTC_GSL_VSYNC_GAP 24 31 mmCRTC5_CRTC_GSL_WINDOW 0 0x1139 2 0 2 CRTC_GSL_WINDOW_START 0 13 CRTC_GSL_WINDOW_END 16 29 mmCRTC5_CRTC_GSL_CONTROL 0 0x113a 3 0 2 CRTC_GSL_CHECK_LINE_NUM 0 13 CRTC_GSL_FORCE_DELAY 16 20 CRTC_GSL_CHECK_ALL_FIELDS 28 28 mmCRTC5_CRTC_RANGE_TIMING_INT_STATUS 0 0x113d 5 0 2 CRTC_RANGE_TIMING_UPDATE_OCCURRED 0 0 CRTC_RANGE_TIMING_UPDATE_OCCURRED_INT 4 4 CRTC_RANGE_TIMING_UPDATE_OCCURRED_CLEAR 8 8 CRTC_RANGE_TIMING_UPDATE_OCCURRED_INT_MSK 12 12 CRTC_RANGE_TIMING_UPDATE_OCCURRED_INT_TYPE 16 16 mmCRTC5_CRTC_DRR_CONTROL 0 0x113e 4 0 2 CRTC_XDMA_PREFETCH_DELAY 0 13 CRTC_V_TOTAL_LAST_USED_BY_DRR 14 27 CRTC_SET_V_TOTAL_MIN_AUTO_DIS 28 28 CRTC_DRR_MODE_DBUF_UPDATE_MODE 29 30 mmFMT5_FMT_CLAMP_COMPONENT_R 0 0x1142 2 0 2 FMT_CLAMP_LOWER_R 0 15 FMT_CLAMP_UPPER_R 16 31 mmFMT5_FMT_CLAMP_COMPONENT_G 0 0x1143 2 0 2 FMT_CLAMP_LOWER_G 0 15 FMT_CLAMP_UPPER_G 16 31 mmFMT5_FMT_CLAMP_COMPONENT_B 0 0x1144 2 0 2 FMT_CLAMP_LOWER_B 0 15 FMT_CLAMP_UPPER_B 16 31 mmFMT5_FMT_DYNAMIC_EXP_CNTL 0 0x1145 2 0 2 FMT_DYNAMIC_EXP_EN 0 0 FMT_DYNAMIC_EXP_MODE 4 4 mmFMT5_FMT_CONTROL 0 0x1146 11 0 2 FMT_STEREOSYNC_OVERRIDE 0 0 FMT_STEREOSYNC_OVR_POL 4 4 FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX 8 11 FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP 12 13 FMT_PIXEL_ENCODING 16 17 FMT_SUBSAMPLING_MODE 18 19 FMT_SUBSAMPLING_ORDER 20 20 FMT_CBCR_BIT_REDUCTION_BYPASS 21 21 FMT_SRC_SELECT 24 26 FMT_420_PIXEL_PHASE_LOCKED 30 30 FMT_420_PIXEL_PHASE_LOCKED_CLEAR 31 31 mmFMT5_FMT_BIT_DEPTH_CONTROL 0 0x1147 17 0 2 FMT_TRUNCATE_EN 0 0 FMT_TRUNCATE_MODE 1 1 FMT_TRUNCATE_DEPTH 4 5 FMT_SPATIAL_DITHER_EN 8 8 FMT_SPATIAL_DITHER_MODE 9 10 FMT_SPATIAL_DITHER_DEPTH 11 12 FMT_FRAME_RANDOM_ENABLE 13 13 FMT_RGB_RANDOM_ENABLE 14 14 FMT_HIGHPASS_RANDOM_ENABLE 15 15 FMT_TEMPORAL_DITHER_EN 16 16 FMT_TEMPORAL_DITHER_DEPTH 17 18 FMT_TEMPORAL_DITHER_OFFSET 21 22 FMT_TEMPORAL_LEVEL 24 24 FMT_TEMPORAL_DITHER_RESET 25 25 FMT_25FRC_SEL 26 27 FMT_50FRC_SEL 28 29 FMT_75FRC_SEL 30 31 mmFMT5_FMT_DITHER_RAND_R_SEED 0 0x1148 2 0 2 FMT_RAND_R_SEED 0 7 FMT_OFFSET_R_CR 16 31 mmFMT5_FMT_DITHER_RAND_G_SEED 0 0x1149 2 0 2 FMT_RAND_G_SEED 0 7 FMT_OFFSET_G_Y 16 31 mmFMT5_FMT_DITHER_RAND_B_SEED 0 0x114a 2 0 2 FMT_RAND_B_SEED 0 7 FMT_OFFSET_B_CB 16 31 mmFMT5_FMT_CLAMP_CNTL 0 0x114e 2 0 2 FMT_CLAMP_DATA_EN 0 0 FMT_CLAMP_COLOR_FORMAT 16 18 mmFMT5_FMT_CRC_CNTL 0 0x114f 11 0 2 FMT_CRC_EN 0 0 FMT_DTMTEST_CRC_EN 1 1 FMT_CRC_CONT_EN 4 4 FMT_ONE_SHOT_CRC_PENDING 5 5 FMT_CRC_INCLUDE_OVERSCAN 6 6 FMT_CRC_ONLY_BLANKB 8 8 FMT_CRC_PSR_MODE_ENABLE 9 9 FMT_CRC_INTERLACE_MODE 12 13 FMT_CRC_USE_NEW_AND_REPEATED_PIXELS 16 16 FMT_CRC_EVEN_ODD_PIX_ENABLE 20 20 FMT_CRC_EVEN_ODD_PIX_SELECT 24 24 mmFMT5_FMT_CRC_SIG_RED_GREEN_MASK 0 0x1150 2 0 2 FMT_CRC_SIG_RED_MASK 0 15 FMT_CRC_SIG_GREEN_MASK 16 31 mmFMT5_FMT_CRC_SIG_BLUE_CONTROL_MASK 0 0x1151 2 0 2 FMT_CRC_SIG_BLUE_MASK 0 15 FMT_CRC_SIG_CONTROL_MASK 16 31 mmFMT5_FMT_CRC_SIG_RED_GREEN 0 0x1152 2 0 2 FMT_CRC_SIG_RED 0 15 FMT_CRC_SIG_GREEN 16 31 mmFMT5_FMT_CRC_SIG_BLUE_CONTROL 0 0x1153 2 0 2 FMT_CRC_SIG_BLUE 0 15 FMT_CRC_SIG_CONTROL 16 31 mmFMT5_FMT_SIDE_BY_SIDE_STEREO_CONTROL 0 0x1154 1 0 2 FMT_SIDE_BY_SIDE_STEREO_ACTIVE_WIDTH 0 12 mmFMT5_FMT_420_HBLANK_EARLY_START 0 0x1155 1 0 2 FMT_420_HBLANK_EARLY_START 0 11 mmUNP0_UNP_GRPH_ENABLE 0 0x115a 1 0 2 GRPH_ENABLE 0 0 mmUNP0_UNP_GRPH_CONTROL 0 0x115b 14 0 2 GRPH_DEPTH 0 1 GRPH_NUM_BANKS 2 3 GRPH_Z 4 5 GRPH_BANK_WIDTH_L 6 7 GRPH_FORMAT 8 10 GRPH_BANK_HEIGHT_L 11 12 GRPH_TILE_SPLIT_L 13 15 GRPH_ADDRESS_TRANSLATION_ENABLE 16 16 GRPH_PRIVILEGED_ACCESS_ENABLE 17 17 GRPH_MACRO_TILE_ASPECT_L 18 19 GRPH_ARRAY_MODE 20 23 GRPH_PIPE_CONFIG 24 28 GRPH_MICRO_TILE_MODE_L 29 30 GRPH_COLOR_EXPANSION_MODE 31 31 mmUNP0_UNP_GRPH_CONTROL_C 0 0x115c 5 0 2 GRPH_BANK_WIDTH_C 6 7 GRPH_BANK_HEIGHT_C 11 12 GRPH_TILE_SPLIT_C 13 15 GRPH_MACRO_TILE_ASPECT_C 18 19 GRPH_MICRO_TILE_MODE_C 29 30 mmUNP0_UNP_GRPH_CONTROL_EXP 0 0x115d 1 0 2 VIDEO_FORMAT 0 2 mmUNP0_UNP_GRPH_SWAP_CNTL 0 0x115e 4 0 2 GRPH_ENDIAN_SWAP 0 1 GRPH_RED_CROSSBAR 4 5 GRPH_GREEN_CROSSBAR 6 7 GRPH_BLUE_CROSSBAR 8 9 mmUNP0_UNP_GRPH_PRIMARY_SURFACE_ADDRESS_L 0 0x115f 1 0 2 GRPH_PRIMARY_SURFACE_ADDRESS_L 8 31 mmUNP0_UNP_GRPH_PRIMARY_SURFACE_ADDRESS_C 0 0x1160 1 0 2 GRPH_PRIMARY_SURFACE_ADDRESS_C 8 31 mmUNP0_UNP_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_L 0 0x1161 1 0 2 GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_L 0 7 mmUNP0_UNP_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_C 0 0x1162 1 0 2 GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_C 0 7 mmUNP0_UNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_L 0 0x1163 1 0 2 GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_L 8 31 mmUNP0_UNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_C 0 0x1164 1 0 2 GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_C 8 31 mmUNP0_UNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_HIGH_L 0 0x1165 1 0 2 GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_HIGH_L 0 7 mmUNP0_UNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_HIGH_C 0 0x1166 1 0 2 GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_HIGH_C 0 7 mmUNP0_UNP_GRPH_SECONDARY_SURFACE_ADDRESS_L 0 0x1167 1 0 2 GRPH_SECONDARY_SURFACE_ADDRESS_L 8 31 mmUNP0_UNP_GRPH_SECONDARY_SURFACE_ADDRESS_C 0 0x1168 1 0 2 GRPH_SECONDARY_SURFACE_ADDRESS_C 8 31 mmUNP0_UNP_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_L 0 0x1169 1 0 2 GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_L 0 7 mmUNP0_UNP_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_C 0 0x116a 1 0 2 GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_C 0 7 mmUNP0_UNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_L 0 0x116b 1 0 2 GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_L 8 31 mmUNP0_UNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_C 0 0x116c 1 0 2 GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_C 8 31 mmUNP0_UNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_HIGH_L 0 0x116d 1 0 2 GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_HIGH_L 0 7 mmUNP0_UNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_HIGH_C 0 0x116e 1 0 2 GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_HIGH_C 0 7 mmUNP0_UNP_GRPH_PITCH_L 0 0x116f 1 0 2 GRPH_PITCH_L 0 14 mmUNP0_UNP_GRPH_PITCH_C 0 0x1170 1 0 2 GRPH_PITCH_C 0 14 mmUNP0_UNP_GRPH_SURFACE_OFFSET_X_L 0 0x1171 1 0 2 GRPH_SURFACE_OFFSET_X_L 0 13 mmUNP0_UNP_GRPH_SURFACE_OFFSET_X_C 0 0x1172 1 0 2 GRPH_SURFACE_OFFSET_X_C 0 13 mmUNP0_UNP_GRPH_SURFACE_OFFSET_Y_L 0 0x1173 1 0 2 GRPH_SURFACE_OFFSET_Y_L 0 13 mmUNP0_UNP_GRPH_SURFACE_OFFSET_Y_C 0 0x1174 1 0 2 GRPH_SURFACE_OFFSET_Y_C 0 13 mmUNP0_UNP_GRPH_X_START_L 0 0x1175 1 0 2 GRPH_X_START_L 0 13 mmUNP0_UNP_GRPH_X_START_C 0 0x1176 1 0 2 GRPH_X_START_C 0 13 mmUNP0_UNP_GRPH_Y_START_L 0 0x1177 1 0 2 GRPH_Y_START_L 0 13 mmUNP0_UNP_GRPH_Y_START_C 0 0x1178 1 0 2 GRPH_Y_START_C 0 13 mmUNP0_UNP_GRPH_X_END_L 0 0x1179 1 0 2 GRPH_X_END_L 0 14 mmUNP0_UNP_GRPH_X_END_C 0 0x117a 1 0 2 GRPH_X_END_C 0 14 mmUNP0_UNP_GRPH_Y_END_L 0 0x117b 1 0 2 GRPH_Y_END_L 0 14 mmUNP0_UNP_GRPH_Y_END_C 0 0x117c 1 0 2 GRPH_Y_END_C 0 14 mmUNP0_UNP_GRPH_UPDATE 0 0x117d 8 0 2 GRPH_MODE_UPDATE_PENDING 0 0 GRPH_MODE_UPDATE_TAKEN 1 1 GRPH_SURFACE_UPDATE_PENDING 2 2 GRPH_SURFACE_UPDATE_TAKEN 3 3 GRPH_UPDATE_LOCK 16 16 GRPH_SURFACE_IGNORE_UPDATE_LOCK 20 20 GRPH_MODE_DISABLE_MULTIPLE_UPDATE 24 24 GRPH_SURFACE_DISABLE_MULTIPLE_UPDATE 28 28 mmUNP0_UNP_PIPE_OUTSTANDING_REQUEST_LIMIT 0 0x117e 2 0 2 UNP_PIPE_OUTSTANDING_REQUEST_LIMIT_L 0 7 UNP_PIPE_OUTSTANDING_REQUEST_LIMIT_C 8 15 mmUNP0_UNP_GRPH_SURFACE_ADDRESS_INUSE_L 0 0x117f 1 0 2 GRPH_SURFACE_ADDRESS_INUSE_L 8 31 mmUNP0_UNP_GRPH_SURFACE_ADDRESS_INUSE_C 0 0x1180 1 0 2 GRPH_SURFACE_ADDRESS_INUSE_C 8 31 mmUNP0_UNP_GRPH_SURFACE_ADDRESS_HIGH_INUSE_L 0 0x1181 1 0 2 GRPH_SURFACE_ADDRESS_HIGH_INUSE_L 0 7 mmUNP0_UNP_GRPH_SURFACE_ADDRESS_HIGH_INUSE_C 0 0x1182 1 0 2 GRPH_SURFACE_ADDRESS_HIGH_INUSE_C 0 7 mmUNP0_UNP_DVMM_PTE_CONTROL 0 0x1183 6 0 2 DVMM_USE_SINGLE_PTE 0 0 DVMM_PAGE_WIDTH 1 4 DVMM_PAGE_HEIGHT 5 8 DVMM_MIN_PTE_BEFORE_FLIP 9 18 DVMM_PTE_BUFFER_MODE0 20 20 DVMM_PTE_BUFFER_MODE1 21 21 mmUNP0_UNP_DVMM_PTE_CONTROL_C 0 0x1184 6 0 2 DVMM_USE_SINGLE_PTE_C 0 0 DVMM_PAGE_WIDTH_C 1 4 DVMM_PAGE_HEIGHT_C 5 8 DVMM_MIN_PTE_BEFORE_FLIP_C 9 18 DVMM_PTE_BUFFER_MODE0_C 20 20 DVMM_PTE_BUFFER_MODE1_C 21 21 mmUNP0_UNP_DVMM_PTE_ARB_CONTROL 0 0x1185 2 0 2 DVMM_PTE_REQ_PER_CHUNK 0 5 DVMM_MAX_PTE_REQ_OUTSTANDING 8 15 mmUNP0_UNP_DVMM_PTE_ARB_CONTROL_C 0 0x1186 2 0 2 DVMM_PTE_REQ_PER_CHUNK_C 0 5 DVMM_MAX_PTE_REQ_OUTSTANDING_C 8 15 mmUNP0_UNP_GRPH_INTERRUPT_STATUS 0 0x1187 2 0 2 GRPH_PFLIP_INT_OCCURRED 0 0 GRPH_PFLIP_INT_CLEAR 8 8 mmUNP0_UNP_GRPH_INTERRUPT_CONTROL 0 0x1188 2 0 2 GRPH_PFLIP_INT_MASK 0 0 GRPH_PFLIP_INT_TYPE 8 8 mmUNP0_UNP_GRPH_STEREOSYNC_FLIP 0 0x1189 9 0 2 GRPH_STEREOSYNC_FLIP_EN 0 0 GRPH_STEREOSYNC_FLIP_MODE 4 5 GRPH_STACK_INTERLACE_FLIP_EN 8 8 GRPH_STACK_INTERLACE_FLIP_MODE 12 13 GRPH_PRIMARY_SURFACE_PENDING 16 16 GRPH_SECONDARY_SURFACE_PENDING 17 17 GRPH_PRIMARY_BOTTOM_SURFACE_PENDING 18 18 GRPH_SECONDARY_BOTTOM_SURFACE_PENDING 19 19 GRPH_STEREOSYNC_SELECT_DISABLE 28 28 mmUNP0_UNP_FLIP_CONTROL 0 0x118a 1 0 2 GRPH_SURFACE_UPDATE_PENDING_MODE 0 0 mmUNP0_UNP_CRC_CONTROL 0 0x118b 3 0 2 UNP_CRC_ENABLE 0 0 UNP_CRC_SOURCE_SEL 2 4 UNP_CRC_LINE_SEL 8 9 mmUNP0_UNP_CRC_MASK 0 0x118c 1 0 2 UNP_CRC_MASK 0 31 mmUNP0_UNP_CRC_CURRENT 0 0x118d 1 0 2 UNP_CRC_CURRENT 0 31 mmUNP0_UNP_CRC_LAST 0 0x118e 1 0 2 UNP_CRC_LAST 0 31 mmUNP0_UNP_LB_DATA_GAP_BETWEEN_CHUNK 0 0x118f 1 0 2 UNP_LB_GAP_BETWEEN_CHUNK 4 8 mmUNP0_UNP_HW_ROTATION 0 0x1190 3 0 2 ROTATION_ANGLE 0 2 PIXEL_DROP 4 4 BUFFER_MODE 8 8 mmLBV0_LBV_DATA_FORMAT 0 0x1196 10 0 2 PIXEL_DEPTH 0 1 PIXEL_EXPAN_MODE 2 2 INTERLEAVE_EN 3 3 PIXEL_REDUCE_MODE 4 4 DYNAMIC_PIXEL_DEPTH 5 5 DITHER_EN 6 6 DOWNSCALE_PREFETCH_EN 7 7 PREFETCH 12 12 REQUEST_MODE 24 24 ALPHA_EN 31 31 mmLBV0_LBV_MEMORY_CTRL 0 0x1197 3 0 2 LB_MEMORY_SIZE 0 11 LB_NUM_PARTITIONS 16 19 LB_MEMORY_CONFIG 20 21 mmLBV0_LBV_MEMORY_SIZE_STATUS 0 0x1198 1 0 2 LB_MEMORY_SIZE_STATUS 0 11 mmLBV0_LBV_DESKTOP_HEIGHT 0 0x1199 1 0 2 DESKTOP_HEIGHT 0 14 mmLBV0_LBV_VLINE_START_END 0 0x119a 3 0 2 VLINE_START 0 13 VLINE_END 16 30 VLINE_INV 31 31 mmLBV0_LBV_VLINE2_START_END 0 0x119b 3 0 2 VLINE2_START 0 13 VLINE2_END 16 30 VLINE2_INV 31 31 mmLBV0_LBV_V_COUNTER 0 0x119c 1 0 2 V_COUNTER 0 14 mmLBV0_LBV_SNAPSHOT_V_COUNTER 0 0x119d 1 0 2 SNAPSHOT_V_COUNTER 0 14 mmLBV0_LBV_V_COUNTER_CHROMA 0 0x119e 1 0 2 V_COUNTER_CHROMA 0 14 mmLBV0_LBV_SNAPSHOT_V_COUNTER_CHROMA 0 0x119f 1 0 2 SNAPSHOT_V_COUNTER_CHROMA 0 14 mmLBV0_LBV_INTERRUPT_MASK 0 0x11a0 3 0 2 VBLANK_INTERRUPT_MASK 0 0 VLINE_INTERRUPT_MASK 4 4 VLINE2_INTERRUPT_MASK 8 8 mmLBV0_LBV_VLINE_STATUS 0 0x11a1 5 0 2 VLINE_OCCURRED 0 0 VLINE_ACK 4 4 VLINE_STAT 12 12 VLINE_INTERRUPT 16 16 VLINE_INTERRUPT_TYPE 17 17 mmLBV0_LBV_VLINE2_STATUS 0 0x11a2 5 0 2 VLINE2_OCCURRED 0 0 VLINE2_ACK 4 4 VLINE2_STAT 12 12 VLINE2_INTERRUPT 16 16 VLINE2_INTERRUPT_TYPE 17 17 mmLBV0_LBV_VBLANK_STATUS 0 0x11a3 5 0 2 VBLANK_OCCURRED 0 0 VBLANK_ACK 4 4 VBLANK_STAT 12 12 VBLANK_INTERRUPT 16 16 VBLANK_INTERRUPT_TYPE 17 17 mmLBV0_LBV_SYNC_RESET_SEL 0 0x11a4 4 0 2 LB_SYNC_RESET_SEL 0 1 LB_SYNC_RESET_SEL2 4 4 LB_SYNC_RESET_DELAY 8 15 LB_SYNC_DURATION 22 23 mmLBV0_LBV_BLACK_KEYER_R_CR 0 0x11a5 1 0 2 LB_BLACK_KEYER_R_CR 4 15 mmLBV0_LBV_BLACK_KEYER_G_Y 0 0x11a6 1 0 2 LB_BLACK_KEYER_G_Y 4 15 mmLBV0_LBV_BLACK_KEYER_B_CB 0 0x11a7 1 0 2 LB_BLACK_KEYER_B_CB 4 15 mmLBV0_LBV_KEYER_COLOR_CTRL 0 0x11a8 2 0 2 LB_KEYER_COLOR_EN 0 0 LB_KEYER_COLOR_REP_EN 8 8 mmLBV0_LBV_KEYER_COLOR_R_CR 0 0x11a9 1 0 2 LB_KEYER_COLOR_R_CR 4 15 mmLBV0_LBV_KEYER_COLOR_G_Y 0 0x11aa 1 0 2 LB_KEYER_COLOR_G_Y 4 15 mmLBV0_LBV_KEYER_COLOR_B_CB 0 0x11ab 1 0 2 LB_KEYER_COLOR_B_CB 4 15 mmLBV0_LBV_KEYER_COLOR_REP_R_CR 0 0x11ac 1 0 2 LB_KEYER_COLOR_REP_R_CR 4 15 mmLBV0_LBV_KEYER_COLOR_REP_G_Y 0 0x11ad 1 0 2 LB_KEYER_COLOR_REP_G_Y 4 15 mmLBV0_LBV_KEYER_COLOR_REP_B_CB 0 0x11ae 1 0 2 LB_KEYER_COLOR_REP_B_CB 4 15 mmLBV0_LBV_BUFFER_LEVEL_STATUS 0 0x11af 4 0 2 REQ_FIFO_LEVEL 0 5 REQ_FIFO_FULL_CNTL 10 15 DATA_BUFFER_LEVEL 16 27 DATA_FIFO_FULL_CNTL 28 31 mmLBV0_LBV_BUFFER_URGENCY_CTRL 0 0x11b0 2 0 2 LB_BUFFER_URGENCY_MARK_ON 0 11 LB_BUFFER_URGENCY_MARK_OFF 16 27 mmLBV0_LBV_BUFFER_URGENCY_STATUS 0 0x11b1 2 0 2 LB_BUFFER_URGENCY_LEVEL 0 11 LB_BUFFER_URGENCY_STAT 16 16 mmLBV0_LBV_BUFFER_STATUS 0 0x11b2 9 0 2 LB_BUFFER_EMPTY_MARGIN 0 3 LB_BUFFER_EMPTY_STAT 4 4 LB_BUFFER_EMPTY_OCCURRED 8 8 LB_BUFFER_EMPTY_ACK 12 12 LB_BUFFER_FULL_STAT 16 16 LB_BUFFER_FULL_OCCURRED 20 20 LB_BUFFER_FULL_ACK 24 24 LB_ENABLE_HIGH_THROUGHPUT 25 25 LB_HIGH_THROUGHPUT_CNTL 26 28 mmLBV0_LBV_NO_OUTSTANDING_REQ_STATUS 0 0x11b3 1 0 2 LB_NO_OUTSTANDING_REQ_STAT 0 0 mmSCLV0_SCLV_COEF_RAM_SELECT 0 0x11ca 3 0 2 SCL_C_RAM_TAP_PAIR_IDX 0 1 SCL_C_RAM_PHASE 8 14 SCL_C_RAM_FILTER_TYPE 16 17 mmSCLV0_SCLV_COEF_RAM_TAP_DATA 0 0x11cb 4 0 2 SCL_C_RAM_EVEN_TAP_COEF 0 13 SCL_C_RAM_EVEN_TAP_COEF_EN 15 15 SCL_C_RAM_ODD_TAP_COEF 16 29 SCL_C_RAM_ODD_TAP_COEF_EN 31 31 mmSCLV0_SCLV_MODE 0 0x11cc 5 0 2 SCL_MODE 0 1 SCL_MODE_C 2 3 SCL_PSCL_EN 4 4 SCL_PSCL_EN_C 5 5 SCL_INTERLACE_SOURCE 8 9 mmSCLV0_SCLV_TAP_CONTROL 0 0x11cd 4 0 2 SCL_V_NUM_OF_TAPS 0 2 SCL_H_NUM_OF_TAPS 4 6 SCL_V_NUM_OF_TAPS_C 8 10 SCL_H_NUM_OF_TAPS_C 12 14 mmSCLV0_SCLV_CONTROL 0 0x11ce 3 0 2 SCL_BOUNDARY_MODE 0 0 SCL_EARLY_EOL_MODE 4 4 SCL_TOTAL_PHASE 8 8 mmSCLV0_SCLV_MANUAL_REPLICATE_CONTROL 0 0x11cf 2 0 2 SCL_V_MANUAL_REPLICATE_FACTOR 0 3 SCL_H_MANUAL_REPLICATE_FACTOR 8 11 mmSCLV0_SCLV_AUTOMATIC_MODE_CONTROL 0 0x11d0 2 0 2 SCL_V_CALC_AUTO_RATIO_EN 0 0 SCL_H_CALC_AUTO_RATIO_EN 16 16 mmSCLV0_SCLV_HORZ_FILTER_CONTROL 0 0x11d1 1 0 2 SCL_H_2TAP_HARDCODE_COEF_EN 8 8 mmSCLV0_SCLV_HORZ_FILTER_SCALE_RATIO 0 0x11d2 1 0 2 SCL_H_SCALE_RATIO 0 25 mmSCLV0_SCLV_HORZ_FILTER_INIT 0 0x11d3 2 0 2 SCL_H_INIT_FRAC 0 23 SCL_H_INIT_INT 24 27 mmSCLV0_SCLV_HORZ_FILTER_SCALE_RATIO_C 0 0x11d4 1 0 2 SCL_H_SCALE_RATIO_C 0 25 mmSCLV0_SCLV_HORZ_FILTER_INIT_C 0 0x11d5 2 0 2 SCL_H_INIT_FRAC_C 0 23 SCL_H_INIT_INT_C 24 27 mmSCLV0_SCLV_VERT_FILTER_CONTROL 0 0x11d6 1 0 2 SCL_V_2TAP_HARDCODE_COEF_EN 8 8 mmSCLV0_SCLV_VERT_FILTER_SCALE_RATIO 0 0x11d7 1 0 2 SCL_V_SCALE_RATIO 0 25 mmSCLV0_SCLV_VERT_FILTER_INIT 0 0x11d8 2 0 2 SCL_V_INIT_FRAC 0 23 SCL_V_INIT_INT 24 26 mmSCLV0_SCLV_VERT_FILTER_INIT_BOT 0 0x11d9 2 0 2 SCL_V_INIT_FRAC_BOT 0 23 SCL_V_INIT_INT_BOT 24 26 mmSCLV0_SCLV_VERT_FILTER_SCALE_RATIO_C 0 0x11da 1 0 2 SCL_V_SCALE_RATIO_C 0 25 mmSCLV0_SCLV_VERT_FILTER_INIT_C 0 0x11db 2 0 2 SCL_V_INIT_FRAC_C 0 23 SCL_V_INIT_INT_C 24 26 mmSCLV0_SCLV_VERT_FILTER_INIT_BOT_C 0 0x11dc 2 0 2 SCL_V_INIT_FRAC_BOT_C 0 23 SCL_V_INIT_INT_BOT_C 24 26 mmSCLV0_SCLV_ROUND_OFFSET 0 0x11dd 2 0 2 SCL_ROUND_OFFSET_RGB_Y 0 15 SCL_ROUND_OFFSET_CBCR 16 31 mmSCLV0_SCLV_UPDATE 0 0x11de 4 0 2 SCL_UPDATE_PENDING 0 0 SCL_UPDATE_TAKEN 8 8 SCL_UPDATE_LOCK 16 16 SCL_COEF_UPDATE_COMPLETE 24 24 mmSCLV0_SCLV_ALU_CONTROL 0 0x11df 1 0 2 SCL_ALU_DISABLE 0 0 mmSCLV0_SCLV_VIEWPORT_START 0 0x11e0 2 0 2 VIEWPORT_Y_START 0 13 VIEWPORT_X_START 16 29 mmSCLV0_SCLV_VIEWPORT_START_SECONDARY 0 0x11e1 2 0 2 VIEWPORT_Y_START_SECONDARY 0 13 VIEWPORT_X_START_SECONDARY 16 29 mmSCLV0_SCLV_VIEWPORT_SIZE 0 0x11e2 2 0 2 VIEWPORT_HEIGHT 0 12 VIEWPORT_WIDTH 16 28 mmSCLV0_SCLV_VIEWPORT_START_C 0 0x11e3 2 0 2 VIEWPORT_Y_START_C 0 13 VIEWPORT_X_START_C 16 29 mmSCLV0_SCLV_VIEWPORT_START_SECONDARY_C 0 0x11e4 2 0 2 VIEWPORT_Y_START_SECONDARY_C 0 13 VIEWPORT_X_START_SECONDARY_C 16 29 mmSCLV0_SCLV_VIEWPORT_SIZE_C 0 0x11e5 2 0 2 VIEWPORT_HEIGHT_C 0 12 VIEWPORT_WIDTH_C 16 28 mmSCLV0_SCLV_EXT_OVERSCAN_LEFT_RIGHT 0 0x11e6 2 0 2 EXT_OVERSCAN_RIGHT 0 12 EXT_OVERSCAN_LEFT 16 28 mmSCLV0_SCLV_EXT_OVERSCAN_TOP_BOTTOM 0 0x11e7 2 0 2 EXT_OVERSCAN_BOTTOM 0 12 EXT_OVERSCAN_TOP 16 28 mmSCLV0_SCLV_MODE_CHANGE_DET1 0 0x11e8 3 0 2 SCL_MODE_CHANGE 0 0 SCL_MODE_CHANGE_ACK 4 4 SCL_ALU_H_SCALE_RATIO 7 27 mmSCLV0_SCLV_MODE_CHANGE_DET2 0 0x11e9 1 0 2 SCL_ALU_V_SCALE_RATIO 0 20 mmSCLV0_SCLV_MODE_CHANGE_DET3 0 0x11ea 2 0 2 SCL_ALU_SOURCE_HEIGHT 0 13 SCL_ALU_SOURCE_WIDTH 16 29 mmSCLV0_SCLV_MODE_CHANGE_MASK 0 0x11eb 1 0 2 SCL_MODE_CHANGE_MASK 0 0 mmSCLV0_SCLV_HORZ_FILTER_INIT_BOT 0 0x11ec 2 0 2 SCL_H_INIT_FRAC_BOT 0 23 SCL_H_INIT_INT_BOT 24 27 mmSCLV0_SCLV_HORZ_FILTER_INIT_BOT_C 0 0x11ed 2 0 2 SCL_H_INIT_FRAC_BOT_C 0 23 SCL_H_INIT_INT_BOT_C 24 27 mmCOL_MAN0_COL_MAN_UPDATE 0 0x11fe 4 0 2 COL_MAN_UPDATE_PENDING 0 0 COL_MAN_UPDATE_TAKEN 1 1 COL_MAN_UPDATE_LOCK 16 16 COL_MAN_DISABLE_MULTIPLE_UPDATE 24 24 mmCOL_MAN0_COL_MAN_INPUT_CSC_CONTROL 0 0x11ff 3 0 2 INPUT_CSC_MODE 0 1 INPUT_CSC_INPUT_TYPE 8 9 INPUT_CSC_CONVERSION_MODE 16 16 mmCOL_MAN0_INPUT_CSC_C11_C12_A 0 0x1200 2 0 2 INPUT_CSC_C11_A 0 15 INPUT_CSC_C12_A 16 31 mmCOL_MAN0_INPUT_CSC_C13_C14_A 0 0x1201 2 0 2 INPUT_CSC_C13_A 0 15 INPUT_CSC_C14_A 16 31 mmCOL_MAN0_INPUT_CSC_C21_C22_A 0 0x1202 2 0 2 INPUT_CSC_C21_A 0 15 INPUT_CSC_C22_A 16 31 mmCOL_MAN0_INPUT_CSC_C23_C24_A 0 0x1203 2 0 2 INPUT_CSC_C23_A 0 15 INPUT_CSC_C24_A 16 31 mmCOL_MAN0_INPUT_CSC_C31_C32_A 0 0x1204 2 0 2 INPUT_CSC_C31_A 0 15 INPUT_CSC_C32_A 16 31 mmCOL_MAN0_INPUT_CSC_C33_C34_A 0 0x1205 2 0 2 INPUT_CSC_C33_A 0 15 INPUT_CSC_C34_A 16 31 mmCOL_MAN0_INPUT_CSC_C11_C12_B 0 0x1206 2 0 2 INPUT_CSC_C11_B 0 15 INPUT_CSC_C12_B 16 31 mmCOL_MAN0_INPUT_CSC_C13_C14_B 0 0x1207 2 0 2 INPUT_CSC_C13_B 0 15 INPUT_CSC_C14_B 16 31 mmCOL_MAN0_INPUT_CSC_C21_C22_B 0 0x1208 2 0 2 INPUT_CSC_C21_B 0 15 INPUT_CSC_C22_B 16 31 mmCOL_MAN0_INPUT_CSC_C23_C24_B 0 0x1209 2 0 2 INPUT_CSC_C23_B 0 15 INPUT_CSC_C24_B 16 31 mmCOL_MAN0_INPUT_CSC_C31_C32_B 0 0x120a 2 0 2 INPUT_CSC_C31_B 0 15 INPUT_CSC_C32_B 16 31 mmCOL_MAN0_INPUT_CSC_C33_C34_B 0 0x120b 2 0 2 INPUT_CSC_C33_B 0 15 INPUT_CSC_C34_B 16 31 mmCOL_MAN0_PRESCALE_CONTROL 0 0x120c 1 0 2 PRESCALE_MODE 0 1 mmCOL_MAN0_PRESCALE_VALUES_R 0 0x120d 2 0 2 PRESCALE_BIAS_R 0 15 PRESCALE_SCALE_R 16 31 mmCOL_MAN0_PRESCALE_VALUES_G 0 0x120e 2 0 2 PRESCALE_BIAS_G 0 15 PRESCALE_SCALE_G 16 31 mmCOL_MAN0_PRESCALE_VALUES_B 0 0x120f 2 0 2 PRESCALE_BIAS_B 0 15 PRESCALE_SCALE_B 16 31 mmCOL_MAN0_COL_MAN_OUTPUT_CSC_CONTROL 0 0x1210 1 0 2 OUTPUT_CSC_MODE 0 2 mmCOL_MAN0_OUTPUT_CSC_C11_C12_A 0 0x1211 2 0 2 OUTPUT_CSC_C11_A 0 15 OUTPUT_CSC_C12_A 16 31 mmCOL_MAN0_OUTPUT_CSC_C13_C14_A 0 0x1212 2 0 2 OUTPUT_CSC_C13_A 0 15 OUTPUT_CSC_C14_A 16 31 mmCOL_MAN0_OUTPUT_CSC_C21_C22_A 0 0x1213 2 0 2 OUTPUT_CSC_C21_A 0 15 OUTPUT_CSC_C22_A 16 31 mmCOL_MAN0_OUTPUT_CSC_C23_C24_A 0 0x1214 2 0 2 OUTPUT_CSC_C23_A 0 15 OUTPUT_CSC_C24_A 16 31 mmCOL_MAN0_OUTPUT_CSC_C31_C32_A 0 0x1215 2 0 2 OUTPUT_CSC_C31_A 0 15 OUTPUT_CSC_C32_A 16 31 mmCOL_MAN0_OUTPUT_CSC_C33_C34_A 0 0x1216 2 0 2 OUTPUT_CSC_C33_A 0 15 OUTPUT_CSC_C34_A 16 31 mmCOL_MAN0_OUTPUT_CSC_C11_C12_B 0 0x1217 2 0 2 OUTPUT_CSC_C11_B 0 15 OUTPUT_CSC_C12_B 16 31 mmCOL_MAN0_OUTPUT_CSC_C13_C14_B 0 0x1218 2 0 2 OUTPUT_CSC_C13_B 0 15 OUTPUT_CSC_C14_B 16 31 mmCOL_MAN0_OUTPUT_CSC_C21_C22_B 0 0x1219 2 0 2 OUTPUT_CSC_C21_B 0 15 OUTPUT_CSC_C22_B 16 31 mmCOL_MAN0_OUTPUT_CSC_C23_C24_B 0 0x121a 2 0 2 OUTPUT_CSC_C23_B 0 15 OUTPUT_CSC_C24_B 16 31 mmCOL_MAN0_OUTPUT_CSC_C31_C32_B 0 0x121b 2 0 2 OUTPUT_CSC_C31_B 0 15 OUTPUT_CSC_C32_B 16 31 mmCOL_MAN0_OUTPUT_CSC_C33_C34_B 0 0x121c 2 0 2 OUTPUT_CSC_C33_B 0 15 OUTPUT_CSC_C34_B 16 31 mmCOL_MAN0_DENORM_CLAMP_CONTROL 0 0x121d 2 0 2 DENORM_MODE 0 1 DENORM_10BIT_OUT 8 8 mmCOL_MAN0_DENORM_CLAMP_RANGE_R_CR 0 0x121e 2 0 2 RANGE_CLAMP_MAX_R_CR 0 11 RANGE_CLAMP_MIN_R_CR 12 23 mmCOL_MAN0_DENORM_CLAMP_RANGE_G_Y 0 0x121f 2 0 2 RANGE_CLAMP_MAX_G_Y 0 11 RANGE_CLAMP_MIN_G_Y 12 23 mmCOL_MAN0_DENORM_CLAMP_RANGE_B_CB 0 0x1220 2 0 2 RANGE_CLAMP_MAX_B_CB 0 11 RANGE_CLAMP_MIN_B_CB 12 23 mmCOL_MAN0_COL_MAN_FP_CONVERTED_FIELD 0 0x1221 2 0 2 COL_MAN_FP_CONVERTED_FIELD_DATA 0 17 COL_MAN_FP_CONVERTED_FIELD_INDEX 20 26 mmCOL_MAN0_COL_MAN_REGAMMA_CONTROL 0 0x1222 1 0 2 COL_MAN_REGAMMA_MODE 0 2 mmCOL_MAN0_COL_MAN_REGAMMA_LUT_INDEX 0 0x1223 1 0 2 COL_MAN_REGAMMA_LUT_INDEX 0 8 mmCOL_MAN0_COL_MAN_REGAMMA_LUT_DATA 0 0x1224 1 0 2 COL_MAN_REGAMMA_LUT_DATA 0 18 mmCOL_MAN0_COL_MAN_REGAMMA_LUT_WRITE_EN_MASK 0 0x1225 1 0 2 COL_MAN_REGAMMA_LUT_WRITE_EN_MASK 0 2 mmCOL_MAN0_COL_MAN_REGAMMA_CNTLA_START_CNTL 0 0x1226 2 0 2 COL_MAN_REGAMMA_CNTLA_EXP_REGION_START 0 17 COL_MAN_REGAMMA_CNTLA_EXP_REGION_START_SEGMENT 20 26 mmCOL_MAN0_COL_MAN_REGAMMA_CNTLA_SLOPE_CNTL 0 0x1227 1 0 2 COL_MAN_REGAMMA_CNTLA_EXP_REGION_LINEAR_SLOPE 0 17 mmCOL_MAN0_COL_MAN_REGAMMA_CNTLA_END_CNTL1 0 0x1228 1 0 2 COL_MAN_REGAMMA_CNTLA_EXP_REGION_END 0 15 mmCOL_MAN0_COL_MAN_REGAMMA_CNTLA_END_CNTL2 0 0x1229 2 0 2 COL_MAN_REGAMMA_CNTLA_EXP_REGION_END_SLOPE 0 15 COL_MAN_REGAMMA_CNTLA_EXP_REGION_END_BASE 16 31 mmCOL_MAN0_COL_MAN_REGAMMA_CNTLA_REGION_0_1 0 0x122a 4 0 2 COL_MAN_REGAMMA_CNTLA_EXP_REGION0_LUT_OFFSET 0 8 COL_MAN_REGAMMA_CNTLA_EXP_REGION0_NUM_SEGMENTS 11 13 COL_MAN_REGAMMA_CNTLA_EXP_REGION1_LUT_OFFSET 15 23 COL_MAN_REGAMMA_CNTLA_EXP_REGION1_NUM_SEGMENTS 27 29 mmCOL_MAN0_COL_MAN_REGAMMA_CNTLA_REGION_2_3 0 0x122b 4 0 2 COL_MAN_REGAMMA_CNTLA_EXP_REGION2_LUT_OFFSET 0 8 COL_MAN_REGAMMA_CNTLA_EXP_REGION2_NUM_SEGMENTS 11 13 COL_MAN_REGAMMA_CNTLA_EXP_REGION3_LUT_OFFSET 15 23 COL_MAN_REGAMMA_CNTLA_EXP_REGION3_NUM_SEGMENTS 27 29 mmCOL_MAN0_COL_MAN_REGAMMA_CNTLA_REGION_4_5 0 0x122c 4 0 2 COL_MAN_REGAMMA_CNTLA_EXP_REGION4_LUT_OFFSET 0 8 COL_MAN_REGAMMA_CNTLA_EXP_REGION4_NUM_SEGMENTS 11 13 COL_MAN_REGAMMA_CNTLA_EXP_REGION5_LUT_OFFSET 15 23 COL_MAN_REGAMMA_CNTLA_EXP_REGION5_NUM_SEGMENTS 27 29 mmCOL_MAN0_COL_MAN_REGAMMA_CNTLA_REGION_6_7 0 0x122d 4 0 2 COL_MAN_REGAMMA_CNTLA_EXP_REGION6_LUT_OFFSET 0 8 COL_MAN_REGAMMA_CNTLA_EXP_REGION6_NUM_SEGMENTS 11 13 COL_MAN_REGAMMA_CNTLA_EXP_REGION7_LUT_OFFSET 15 23 COL_MAN_REGAMMA_CNTLA_EXP_REGION7_NUM_SEGMENTS 27 29 mmCOL_MAN0_COL_MAN_REGAMMA_CNTLA_REGION_8_9 0 0x122e 4 0 2 COL_MAN_REGAMMA_CNTLA_EXP_REGION8_LUT_OFFSET 0 8 COL_MAN_REGAMMA_CNTLA_EXP_REGION8_NUM_SEGMENTS 11 13 COL_MAN_REGAMMA_CNTLA_EXP_REGION9_LUT_OFFSET 15 23 COL_MAN_REGAMMA_CNTLA_EXP_REGION9_NUM_SEGMENTS 27 29 mmCOL_MAN0_COL_MAN_REGAMMA_CNTLA_REGION_10_11 0 0x122f 4 0 2 COL_MAN_REGAMMA_CNTLA_EXP_REGION10_LUT_OFFSET 0 8 COL_MAN_REGAMMA_CNTLA_EXP_REGION10_NUM_SEGMENTS 11 13 COL_MAN_REGAMMA_CNTLA_EXP_REGION11_LUT_OFFSET 15 23 COL_MAN_REGAMMA_CNTLA_EXP_REGION11_NUM_SEGMENTS 27 29 mmCOL_MAN0_COL_MAN_REGAMMA_CNTLA_REGION_12_13 0 0x1230 4 0 2 COL_MAN_REGAMMA_CNTLA_EXP_REGION12_LUT_OFFSET 0 8 COL_MAN_REGAMMA_CNTLA_EXP_REGION12_NUM_SEGMENTS 11 13 COL_MAN_REGAMMA_CNTLA_EXP_REGION13_LUT_OFFSET 15 23 COL_MAN_REGAMMA_CNTLA_EXP_REGION13_NUM_SEGMENTS 27 29 mmCOL_MAN0_COL_MAN_REGAMMA_CNTLA_REGION_14_15 0 0x1231 4 0 2 COL_MAN_REGAMMA_CNTLA_EXP_REGION14_LUT_OFFSET 0 8 COL_MAN_REGAMMA_CNTLA_EXP_REGION14_NUM_SEGMENTS 11 13 COL_MAN_REGAMMA_CNTLA_EXP_REGION15_LUT_OFFSET 15 23 COL_MAN_REGAMMA_CNTLA_EXP_REGION15_NUM_SEGMENTS 27 29 mmCOL_MAN0_COL_MAN_REGAMMA_CNTLB_START_CNTL 0 0x1232 2 0 2 COL_MAN_REGAMMA_CNTLB_EXP_REGION_START 0 17 COL_MAN_REGAMMA_CNTLB_EXP_REGION_START_SEGMENT 20 26 mmCOL_MAN0_COL_MAN_REGAMMA_CNTLB_SLOPE_CNTL 0 0x1233 1 0 2 COL_MAN_REGAMMA_CNTLB_EXP_REGION_LINEAR_SLOPE 0 17 mmCOL_MAN0_COL_MAN_REGAMMA_CNTLB_END_CNTL1 0 0x1234 1 0 2 COL_MAN_REGAMMA_CNTLB_EXP_REGION_END 0 15 mmCOL_MAN0_COL_MAN_REGAMMA_CNTLB_END_CNTL2 0 0x1235 2 0 2 COL_MAN_REGAMMA_CNTLB_EXP_REGION_END_SLOPE 0 15 COL_MAN_REGAMMA_CNTLB_EXP_REGION_END_BASE 16 31 mmCOL_MAN0_COL_MAN_REGAMMA_CNTLB_REGION_0_1 0 0x1236 4 0 2 COL_MAN_REGAMMA_CNTLB_EXP_REGION0_LUT_OFFSET 0 8 COL_MAN_REGAMMA_CNTLB_EXP_REGION0_NUM_SEGMENTS 11 13 COL_MAN_REGAMMA_CNTLB_EXP_REGION1_LUT_OFFSET 15 23 COL_MAN_REGAMMA_CNTLB_EXP_REGION1_NUM_SEGMENTS 27 29 mmCOL_MAN0_COL_MAN_REGAMMA_CNTLB_REGION_2_3 0 0x1237 4 0 2 COL_MAN_REGAMMA_CNTLB_EXP_REGION2_LUT_OFFSET 0 8 COL_MAN_REGAMMA_CNTLB_EXP_REGION2_NUM_SEGMENTS 11 13 COL_MAN_REGAMMA_CNTLB_EXP_REGION3_LUT_OFFSET 15 23 COL_MAN_REGAMMA_CNTLB_EXP_REGION3_NUM_SEGMENTS 27 29 mmCOL_MAN0_COL_MAN_REGAMMA_CNTLB_REGION_4_5 0 0x1238 4 0 2 COL_MAN_REGAMMA_CNTLB_EXP_REGION4_LUT_OFFSET 0 8 COL_MAN_REGAMMA_CNTLB_EXP_REGION4_NUM_SEGMENTS 11 13 COL_MAN_REGAMMA_CNTLB_EXP_REGION5_LUT_OFFSET 15 23 COL_MAN_REGAMMA_CNTLB_EXP_REGION5_NUM_SEGMENTS 27 29 mmCOL_MAN0_COL_MAN_REGAMMA_CNTLB_REGION_6_7 0 0x1239 4 0 2 COL_MAN_REGAMMA_CNTLB_EXP_REGION6_LUT_OFFSET 0 8 COL_MAN_REGAMMA_CNTLB_EXP_REGION6_NUM_SEGMENTS 11 13 COL_MAN_REGAMMA_CNTLB_EXP_REGION7_LUT_OFFSET 15 23 COL_MAN_REGAMMA_CNTLB_EXP_REGION7_NUM_SEGMENTS 27 29 mmCOL_MAN0_COL_MAN_REGAMMA_CNTLB_REGION_8_9 0 0x123a 4 0 2 COL_MAN_REGAMMA_CNTLB_EXP_REGION8_LUT_OFFSET 0 8 COL_MAN_REGAMMA_CNTLB_EXP_REGION8_NUM_SEGMENTS 11 13 COL_MAN_REGAMMA_CNTLB_EXP_REGION9_LUT_OFFSET 15 23 COL_MAN_REGAMMA_CNTLB_EXP_REGION9_NUM_SEGMENTS 27 29 mmCOL_MAN0_COL_MAN_REGAMMA_CNTLB_REGION_10_11 0 0x123b 4 0 2 COL_MAN_REGAMMA_CNTLB_EXP_REGION10_LUT_OFFSET 0 8 COL_MAN_REGAMMA_CNTLB_EXP_REGION10_NUM_SEGMENTS 11 13 COL_MAN_REGAMMA_CNTLB_EXP_REGION11_LUT_OFFSET 15 23 COL_MAN_REGAMMA_CNTLB_EXP_REGION11_NUM_SEGMENTS 27 29 mmCOL_MAN0_COL_MAN_REGAMMA_CNTLB_REGION_12_13 0 0x123c 4 0 2 COL_MAN_REGAMMA_CNTLB_EXP_REGION12_LUT_OFFSET 0 8 COL_MAN_REGAMMA_CNTLB_EXP_REGION12_NUM_SEGMENTS 11 13 COL_MAN_REGAMMA_CNTLB_EXP_REGION13_LUT_OFFSET 15 23 COL_MAN_REGAMMA_CNTLB_EXP_REGION13_NUM_SEGMENTS 27 29 mmCOL_MAN0_COL_MAN_REGAMMA_CNTLB_REGION_14_15 0 0x123d 4 0 2 COL_MAN_REGAMMA_CNTLB_EXP_REGION14_LUT_OFFSET 0 8 COL_MAN_REGAMMA_CNTLB_EXP_REGION14_NUM_SEGMENTS 11 13 COL_MAN_REGAMMA_CNTLB_EXP_REGION15_LUT_OFFSET 15 23 COL_MAN_REGAMMA_CNTLB_EXP_REGION15_NUM_SEGMENTS 27 29 mmCOL_MAN0_PACK_FIFO_ERROR 0 0x123e 8 0 2 PACK_FIFO_L_UNDERFLOW_OCCURED 0 0 PACK_FIFO_L_UNDERFLOW_ACK 1 1 PACK_FIFO_C_UNDERFLOW_OCCURED 8 8 PACK_FIFO_C_UNDERFLOW_ACK 9 9 PACK_FIFO_L_OVERFLOW_OCCURED 16 16 PACK_FIFO_L_OVERFLOW_ACK 17 17 PACK_FIFO_C_OVERFLOW_OCCURED 24 24 PACK_FIFO_C_OVERFLOW_ACK 25 25 mmCOL_MAN0_OUTPUT_FIFO_ERROR 0 0x123f 4 0 2 OUTPUT_FIFO_UNDERFLOW_OCCURED 0 0 OUTPUT_FIFO_UNDERFLOW_ACK 1 1 OUTPUT_FIFO_OVERFLOW_OCCURED 8 8 OUTPUT_FIFO_OVERFLOW_ACK 9 9 mmCOL_MAN0_INPUT_GAMMA_LUT_AUTOFILL 0 0x1240 2 0 2 INPUT_GAMMA_LUT_AUTOFILL 0 0 INPUT_GAMMA_LUT_AUTOFILL_DONE 1 1 mmCOL_MAN0_INPUT_GAMMA_LUT_RW_INDEX 0 0x1241 1 0 2 INPUT_GAMMA_LUT_RW_INDEX 0 7 mmCOL_MAN0_INPUT_GAMMA_LUT_SEQ_COLOR 0 0x1242 1 0 2 INPUT_GAMMA_LUT_SEQ_COLOR 0 15 mmCOL_MAN0_INPUT_GAMMA_LUT_PWL_DATA 0 0x1243 2 0 2 INPUT_GAMMA_LUT_BASE 0 15 INPUT_GAMMA_LUT_DELTA 16 31 mmCOL_MAN0_INPUT_GAMMA_LUT_30_COLOR 0 0x1244 3 0 2 INPUT_GAMMA_LUT_COLOR_10_BLUE 0 9 INPUT_GAMMA_LUT_COLOR_10_GREEN 10 19 INPUT_GAMMA_LUT_COLOR_10_RED 20 29 mmCOL_MAN0_COL_MAN_INPUT_GAMMA_CONTROL1 0 0x1245 2 0 2 INPUT_GAMMA_MODE 0 1 INPUT_GAMMA_LUT_10BIT_BYPASS_EN 26 26 mmCOL_MAN0_COL_MAN_INPUT_GAMMA_CONTROL2 0 0x1246 13 0 2 INPUT_GAMMA_INC_B 1 4 INPUT_GAMMA_DATA_B_SIGNED_EN 5 5 INPUT_GAMMA_DATA_B_FORMAT 6 7 INPUT_GAMMA_INC_G 8 11 INPUT_GAMMA_DATA_G_SIGNED_EN 12 12 INPUT_GAMMA_DATA_G_FORMAT 13 14 INPUT_GAMMA_INC_R 15 18 INPUT_GAMMA_DATA_R_SIGNED_EN 19 19 INPUT_GAMMA_DATA_R_FORMAT 20 21 INPUT_GAMMA_LUT_RW_MODE 22 22 INPUT_GAMMA_LUT_WRITE_EN_MASK 23 25 INPUT_GAMMA_LUT_VGA_ACCESS_ENABLE 26 26 INPUT_GAMMA_LUT_10BIT_BYPASS_DBL_BUF_EN 27 27 mmCOL_MAN0_INPUT_GAMMA_BW_OFFSETS_B 0 0x1247 2 0 2 INPUT_GAMMA_BLACK_OFFSET_B 0 15 INPUT_GAMMA_WHITE_OFFSET_B 16 31 mmCOL_MAN0_INPUT_GAMMA_BW_OFFSETS_G 0 0x1248 2 0 2 INPUT_GAMMA_BLACK_OFFSET_G 0 15 INPUT_GAMMA_WHITE_OFFSET_G 16 31 mmCOL_MAN0_INPUT_GAMMA_BW_OFFSETS_R 0 0x1249 2 0 2 INPUT_GAMMA_BLACK_OFFSET_R 0 15 INPUT_GAMMA_WHITE_OFFSET_R 16 31 mmCOL_MAN0_COL_MAN_DEGAMMA_CONTROL 0 0x124a 1 0 2 COL_MAN_DEGAMMA_MODE 0 1 mmCOL_MAN0_COL_MAN_GAMUT_REMAP_CONTROL 0 0x124b 1 0 2 COL_MAN_GAMUT_REMAP_MODE 0 1 mmCOL_MAN0_COL_MAN_GAMUT_REMAP_C11_C12 0 0x124c 2 0 2 COL_MAN_GAMUT_REMAP_C11 0 15 COL_MAN_GAMUT_REMAP_C12 16 31 mmCOL_MAN0_COL_MAN_GAMUT_REMAP_C13_C14 0 0x124d 2 0 2 COL_MAN_GAMUT_REMAP_C13 0 15 COL_MAN_GAMUT_REMAP_C14 16 31 mmCOL_MAN0_COL_MAN_GAMUT_REMAP_C21_C22 0 0x124e 2 0 2 COL_MAN_GAMUT_REMAP_C21 0 15 COL_MAN_GAMUT_REMAP_C22 16 31 mmCOL_MAN0_COL_MAN_GAMUT_REMAP_C23_C24 0 0x124f 2 0 2 COL_MAN_GAMUT_REMAP_C23 0 15 COL_MAN_GAMUT_REMAP_C24 16 31 mmCOL_MAN0_COL_MAN_GAMUT_REMAP_C31_C32 0 0x1250 2 0 2 COL_MAN_GAMUT_REMAP_C31 0 15 COL_MAN_GAMUT_REMAP_C32 16 31 mmCOL_MAN0_COL_MAN_GAMUT_REMAP_C33_C34 0 0x1251 2 0 2 COL_MAN_GAMUT_REMAP_C33 0 15 COL_MAN_GAMUT_REMAP_C34 16 31 mmDCFEV0_DCFEV_CLOCK_CONTROL 0 0x127e 8 0 2 DISPCLK_R_DCFEV_GATE_DISABLE 3 3 DISPCLK_G_UNP_GATE_DISABLE 7 7 DISPCLK_G_SCLV_GATE_DISABLE 9 9 DISPCLK_G_COL_MAN_GATE_DISABLE 11 11 DISPCLK_G_PSCLV_GATE_DISABLE 13 13 DISPCLK_G_CRTC_GATE_DISABLE 15 15 DCFEV_TEST_CLK_SEL 24 28 DCFEV_CLOCK_ENABLE 31 31 mmDCFEV0_DCFEV_SOFT_RESET 0 0x127f 7 0 2 UNP_PIXPIPE_SOFT_RESET 0 0 UNP_REQ_SOFT_RESET 1 1 SCLV_ALU_SOFT_RESET 2 2 SCLV_SOFT_RESET 3 3 CRTC_SOFT_RESET 4 4 PSCLV_SOFT_RESET 5 5 COL_MAN_SOFT_RESET 6 6 mmDCFEV0_DCFEV_DMIFV_CLOCK_CONTROL 0 0x1280 6 0 2 DMIFV_SCLK_G_DMIFTRK_GATE_DIS 3 3 DMIFV_DISPCLK_G_DMIFVL_GATE_DIS 4 4 DMIFV_DISPCLK_G_DMIFVC_GATE_DIS 5 5 DMIFV_SOFT_RESET 6 6 DMIFV_TEST_CLK_SEL 24 28 DMIFV_BUFFER_MODE 31 31 mmDCFEV0_DCFEV_DMIFV_MEM_PWR_CTRL 0 0x1282 11 0 2 DMIFV_MEM_PWR_SEL 0 1 DMIFV_MEM_PWR_LUMA_0_FORCE 2 2 DMIFV_MEM_PWR_LUMA_1_FORCE 3 3 DMIFV_MEM_PWR_LUMA_2_FORCE 4 4 DMIFV_MEM_PWR_LUMA_3_FORCE 5 5 DMIFV_MEM_PWR_LUMA_4_FORCE 6 6 DMIFV_MEM_PWR_CHROMA_0_FORCE 7 7 DMIFV_MEM_PWR_CHROMA_1_FORCE 8 8 DMIFV_MEM_PWR_CHROMA_2_FORCE 9 9 DMIFV_MEM_PWR_CHROMA_3_FORCE 10 10 DMIFV_MEM_PWR_CHROMA_4_FORCE 11 11 mmDCFEV0_DCFEV_DMIFV_MEM_PWR_STATUS 0 0x1283 10 0 2 DMIFV_MEM_PWR_LUMA_0_STATE 0 1 DMIFV_MEM_PWR_LUMA_1_STATE 2 3 DMIFV_MEM_PWR_LUMA_2_STATE 4 5 DMIFV_MEM_PWR_LUMA_3_STATE 6 7 DMIFV_MEM_PWR_LUMA_4_STATE 8 9 DMIFV_MEM_PWR_CHROMA_0_STATE 10 11 DMIFV_MEM_PWR_CHROMA_1_STATE 12 13 DMIFV_MEM_PWR_CHROMA_2_STATE 14 15 DMIFV_MEM_PWR_CHROMA_3_STATE 16 17 DMIFV_MEM_PWR_CHROMA_4_STATE 18 19 mmDCFEV0_DCFEV_MEM_PWR_CTRL 0 0x1284 12 0 2 COL_MAN_REGAMMA_MEM_PWR_FORCE 0 1 COL_MAN_REGAMMA_MEM_PWR_DIS 2 2 COL_MAN_INPUT_GAMMA_MEM_PWR_FORCE 3 4 COL_MAN_INPUT_GAMMA_MEM_PWR_DIS 5 5 SCLV_COEFF_MEM_PWR_FORCE 6 7 SCLV_COEFF_MEM_PWR_DIS 8 8 LBV0_MEM_PWR_FORCE 9 10 LBV0_MEM_PWR_DIS 11 11 LBV1_MEM_PWR_FORCE 12 13 LBV1_MEM_PWR_DIS 14 14 LBV2_MEM_PWR_FORCE 15 16 LBV2_MEM_PWR_DIS 17 17 mmDCFEV0_DCFEV_MEM_PWR_CTRL2 0 0x1285 4 0 2 COL_MAN_REGAMMA_MEM_PWR_MODE_SEL 0 1 COL_MAN_INPUT_GAMMA_MEM_PWR_MODE_SEL 2 3 SCLV_COEFF_MEM_PWR_MODE_SEL 4 5 LBV_MEM_PWR_MODE_SEL 6 7 mmDCFEV0_DCFEV_MEM_PWR_STATUS 0 0x1286 7 0 2 COL_MAN_REGAMMA_MEM_PWR_STATE 0 1 COL_MAN_INPUT_GAMMA_MEM_PWR_STATE 2 3 SCLV_COEFF_MEM_PWR_STATE 4 5 LBV0_MEM_PWR_STATE 6 7 LBV1_MEM_PWR_STATE 8 9 LBV2_MEM_PWR_STATE 10 11 LBV3_MEM_PWR_STATE 12 13 mmDCFEV0_DCFEV_L_FLUSH 0 0x1287 5 0 2 FLUSH_OCCURED 0 0 CLEAR_FLUSH_OCCURED 1 1 FLUSH_DEEP 2 2 CLEAR_FLUSH_DEEP 3 3 ALL_MC_REQ_RET 4 4 mmDCFEV0_DCFEV_C_FLUSH 0 0x1288 5 0 2 FLUSH_OCCURED 0 0 CLEAR_FLUSH_OCCURED 1 1 FLUSH_DEEP 2 2 CLEAR_FLUSH_DEEP 3 3 ALL_MC_REQ_RET 4 4 mmDCFEV0_DCFEV_MISC 0 0x128a 1 0 2 DCFEV_DPG_ALLOW_SR_ECO_EN 0 0 mmDC_PERFMON11_PERFCOUNTER_CNTL 0 0x1292 13 0 2 PERFCOUNTER_EVENT_SEL 0 8 PERFCOUNTER_CVALUE_SEL 9 11 PERFCOUNTER_INC_MODE 12 14 PERFCOUNTER_HW_CNTL_SEL 15 15 PERFCOUNTER_RUNEN_MODE 16 16 PERFCOUNTER_CNTOFF_SEL 17 21 PERFCOUNTER_CNTOFF_START_DIS 22 22 PERFCOUNTER_RESTART_EN 23 23 PERFCOUNTER_INT_EN 24 24 PERFCOUNTER_OFF_MASK 25 25 PERFCOUNTER_ACTIVE 26 26 PERFCOUNTER_INT_TYPE 27 27 PERFCOUNTER_CNTL_SEL 29 31 mmDC_PERFMON11_PERFCOUNTER_CNTL2 0 0x1293 4 0 2 PERFCOUNTER_COUNTED_VALUE_TYPE 0 1 PERFCOUNTER_HW_STOP1_SEL 2 2 PERFCOUNTER_HW_STOP2_SEL 3 3 PERFCOUNTER_CNTL2_SEL 29 31 mmDC_PERFMON11_PERFCOUNTER_STATE 0 0x1294 16 0 2 PERFCOUNTER_CNT0_STATE 0 1 PERFCOUNTER_STATE_SEL0 2 2 PERFCOUNTER_CNT1_STATE 4 5 PERFCOUNTER_STATE_SEL1 6 6 PERFCOUNTER_CNT2_STATE 8 9 PERFCOUNTER_STATE_SEL2 10 10 PERFCOUNTER_CNT3_STATE 12 13 PERFCOUNTER_STATE_SEL3 14 14 PERFCOUNTER_CNT4_STATE 16 17 PERFCOUNTER_STATE_SEL4 18 18 PERFCOUNTER_CNT5_STATE 20 21 PERFCOUNTER_STATE_SEL5 22 22 PERFCOUNTER_CNT6_STATE 24 25 PERFCOUNTER_STATE_SEL6 26 26 PERFCOUNTER_CNT7_STATE 28 29 PERFCOUNTER_STATE_SEL7 30 30 mmDC_PERFMON11_PERFMON_CNTL 0 0x1295 6 0 2 PERFMON_STATE 0 1 PERFMON_RPT_COUNT 8 27 PERFMON_CNTOFF_AND_OR 28 28 PERFMON_CNTOFF_INT_EN 29 29 PERFMON_CNTOFF_INT_STATUS 30 30 PERFMON_CNTOFF_INT_ACK 31 31 mmDC_PERFMON11_PERFMON_CNTL2 0 0x1296 4 0 2 PERFMON_CNTOFF_INT_TYPE 0 0 PERFMON_CLK_ENABLE 1 1 PERFMON_RUN_ENABLE_START_SEL 2 9 PERFMON_RUN_ENABLE_STOP_SEL 10 17 mmDC_PERFMON11_PERFMON_CVALUE_INT_MISC 0 0x1297 17 0 2 PERFCOUNTER_INT0_STATUS 0 0 PERFCOUNTER_INT1_STATUS 1 1 PERFCOUNTER_INT2_STATUS 2 2 PERFCOUNTER_INT3_STATUS 3 3 PERFCOUNTER_INT4_STATUS 4 4 PERFCOUNTER_INT5_STATUS 5 5 PERFCOUNTER_INT6_STATUS 6 6 PERFCOUNTER_INT7_STATUS 7 7 PERFCOUNTER_INT0_ACK 8 8 PERFCOUNTER_INT1_ACK 9 9 PERFCOUNTER_INT2_ACK 10 10 PERFCOUNTER_INT3_ACK 11 11 PERFCOUNTER_INT4_ACK 12 12 PERFCOUNTER_INT5_ACK 13 13 PERFCOUNTER_INT6_ACK 14 14 PERFCOUNTER_INT7_ACK 15 15 PERFMON_CVALUE_HI 16 31 mmDC_PERFMON11_PERFMON_CVALUE_LOW 0 0x1298 1 0 2 PERFMON_CVALUE_LOW 0 31 mmDC_PERFMON11_PERFMON_HI 0 0x1299 2 0 2 PERFMON_HI 0 15 PERFMON_READ_SEL 29 31 mmDC_PERFMON11_PERFMON_LOW 0 0x129a 1 0 2 PERFMON_LOW 0 31 mmDMIFV_PG0_DPGV0_PIPE_ARBITRATION_CONTROL1 0 0x129e 2 0 2 PIXEL_DURATION 0 15 BASE_WEIGHT 16 31 mmDMIFV_PG0_DPGV0_PIPE_ARBITRATION_CONTROL2 0 0x129f 2 0 2 TIME_WEIGHT 0 15 URGENCY_WEIGHT 16 31 mmDMIFV_PG0_DPGV0_WATERMARK_MASK_CONTROL 0 0x12a0 4 0 2 STUTTER_EXIT_SELF_REFRESH_WATERMARK_MASK 0 1 URGENCY_WATERMARK_MASK 8 9 NB_PSTATE_CHANGE_WATERMARK_MASK 16 17 DISABLE_FLIP_URGENT 24 24 mmDMIFV_PG0_DPGV0_PIPE_URGENCY_CONTROL 0 0x12a1 2 0 2 URGENCY_LOW_WATERMARK 0 15 URGENCY_HIGH_WATERMARK 16 31 mmDMIFV_PG0_DPGV0_PIPE_DPM_CONTROL 0 0x12a2 1 0 2 DPM_ENABLE 0 0 mmDMIFV_PG0_DPGV0_PIPE_STUTTER_CONTROL 0 0x12a3 10 0 2 STUTTER_ENABLE 0 0 STUTTER_IGNORE_CURSOR 4 4 STUTTER_IGNORE_ICON 5 5 STUTTER_IGNORE_VGA 6 6 STUTTER_IGNORE_FBC 7 7 STUTTER_WM_HIGH_FORCE_ON 8 8 STUTTER_WM_HIGH_EXCLUDES_VBLANK 9 9 STUTTER_URGENT_IN_NOT_SELF_REFRESH 10 10 STUTTER_SELF_REFRESH_FORCE_ON 11 11 STUTTER_EXIT_SELF_REFRESH_WATERMARK 16 31 mmDMIFV_PG0_DPGV0_PIPE_NB_PSTATE_CHANGE_CONTROL 0 0x12a4 6 0 2 NB_PSTATE_CHANGE_ENABLE 0 0 NB_PSTATE_CHANGE_URGENT_DURING_REQUEST 4 4 NB_PSTATE_CHANGE_NOT_SELF_REFRESH_DURING_REQUEST 8 8 NB_PSTATE_CHANGE_FORCE_ON 9 9 NB_PSTATE_ALLOW_FOR_URGENT 10 10 NB_PSTATE_CHANGE_WATERMARK 16 31 mmDMIFV_PG0_DPGV0_PIPE_STUTTER_CONTROL_NONLPTCH 0 0x12a5 9 0 2 STUTTER_ENABLE_NONLPTCH 0 0 STUTTER_IGNORE_CURSOR_NONLPTCH 4 4 STUTTER_IGNORE_ICON_NONLPTCH 5 5 STUTTER_IGNORE_VGA_NONLPTCH 6 6 STUTTER_IGNORE_FBC_NONLPTCH 7 7 STUTTER_WM_HIGH_FORCE_ON_NONLPTCH 8 8 STUTTER_WM_HIGH_EXCLUDES_VBLANK_NONLPTCH 9 9 STUTTER_URGENT_IN_NOT_SELF_REFRESH_NONLPTCH 10 10 STUTTER_SELF_REFRESH_FORCE_ON_NONLPTCH 11 11 mmDMIFV_PG0_DPGV0_REPEATER_PROGRAM 0 0x12a6 2 0 2 REG_DPG_DMIFRC_REPEATER 0 2 REG_DMIFRC_DPG_REPEATER 4 6 mmDMIFV_PG0_DPGV0_CHK_PRE_PROC_CNTL 0 0x12aa 1 0 2 DPG_DISABLE_DMIF_BUF_CHK 0 0 mmDMIFV_PG0_DPGV1_PIPE_ARBITRATION_CONTROL1 0 0x12ab 2 0 2 PIXEL_DURATION 0 15 BASE_WEIGHT 16 31 mmDMIFV_PG0_DPGV1_PIPE_ARBITRATION_CONTROL2 0 0x12ac 2 0 2 TIME_WEIGHT 0 15 URGENCY_WEIGHT 16 31 mmDMIFV_PG0_DPGV1_WATERMARK_MASK_CONTROL 0 0x12ad 4 0 2 STUTTER_EXIT_SELF_REFRESH_WATERMARK_MASK 0 1 URGENCY_WATERMARK_MASK 8 9 NB_PSTATE_CHANGE_WATERMARK_MASK 16 17 DISABLE_FLIP_URGENT 24 24 mmDMIFV_PG0_DPGV1_PIPE_URGENCY_CONTROL 0 0x12ae 2 0 2 URGENCY_LOW_WATERMARK 0 15 URGENCY_HIGH_WATERMARK 16 31 mmDMIFV_PG0_DPGV1_PIPE_DPM_CONTROL 0 0x12af 1 0 2 DPM_ENABLE 0 0 mmDMIFV_PG0_DPGV1_PIPE_STUTTER_CONTROL 0 0x12b0 10 0 2 STUTTER_ENABLE 0 0 STUTTER_IGNORE_CURSOR 4 4 STUTTER_IGNORE_ICON 5 5 STUTTER_IGNORE_VGA 6 6 STUTTER_IGNORE_FBC 7 7 STUTTER_WM_HIGH_FORCE_ON 8 8 STUTTER_WM_HIGH_EXCLUDES_VBLANK 9 9 STUTTER_URGENT_IN_NOT_SELF_REFRESH 10 10 STUTTER_SELF_REFRESH_FORCE_ON 11 11 STUTTER_EXIT_SELF_REFRESH_WATERMARK 16 31 mmDMIFV_PG0_DPGV1_PIPE_NB_PSTATE_CHANGE_CONTROL 0 0x12b1 6 0 2 NB_PSTATE_CHANGE_ENABLE 0 0 NB_PSTATE_CHANGE_URGENT_DURING_REQUEST 4 4 NB_PSTATE_CHANGE_NOT_SELF_REFRESH_DURING_REQUEST 8 8 NB_PSTATE_CHANGE_FORCE_ON 9 9 NB_PSTATE_ALLOW_FOR_URGENT 10 10 NB_PSTATE_CHANGE_WATERMARK 16 31 mmDMIFV_PG0_DPGV1_PIPE_STUTTER_CONTROL_NONLPTCH 0 0x12b2 9 0 2 STUTTER_ENABLE_NONLPTCH 0 0 STUTTER_IGNORE_CURSOR_NONLPTCH 4 4 STUTTER_IGNORE_ICON_NONLPTCH 5 5 STUTTER_IGNORE_VGA_NONLPTCH 6 6 STUTTER_IGNORE_FBC_NONLPTCH 7 7 STUTTER_WM_HIGH_FORCE_ON_NONLPTCH 8 8 STUTTER_WM_HIGH_EXCLUDES_VBLANK_NONLPTCH 9 9 STUTTER_URGENT_IN_NOT_SELF_REFRESH_NONLPTCH 10 10 STUTTER_SELF_REFRESH_FORCE_ON_NONLPTCH 11 11 mmDMIFV_PG0_DPGV1_REPEATER_PROGRAM 0 0x12b3 2 0 2 REG_DPG_DMIFRC_REPEATER 0 2 REG_DMIFRC_DPG_REPEATER 4 6 mmDMIFV_PG0_DPGV1_CHK_PRE_PROC_CNTL 0 0x12b7 1 0 2 DPG_DISABLE_DMIF_BUF_CHK 0 0 mmBLNDV0_BLNDV_CONTROL 0 0x12db 9 0 2 BLND_GLOBAL_GAIN 0 7 BLND_MODE 8 9 BLND_STEREO_TYPE 10 11 BLND_STEREO_POLARITY 12 12 BLND_FEEDTHROUGH_EN 13 13 BLND_ALPHA_MODE 16 17 BLND_ACTIVE_OVERLAP_ONLY 18 18 BLND_MULTIPLIED_MODE 20 20 BLND_GLOBAL_ALPHA 24 31 mmBLNDV0_BLNDV_SM_CONTROL2 0 0x12dc 6 0 2 SM_MODE 0 2 SM_FRAME_ALTERNATE 4 4 SM_FIELD_ALTERNATE 5 5 SM_FORCE_NEXT_FRAME_POL 8 9 SM_FORCE_NEXT_TOP_POL 16 17 SM_CURRENT_FRAME_POL 24 24 mmBLNDV0_BLNDV_CONTROL2 0 0x12dd 5 0 2 PTI_ENABLE 0 0 PTI_NEW_PIXEL_GAP 4 5 BLND_NEW_PIXEL_MODE 6 6 BLND_SUPERAA_DEGAMMA_EN 7 7 BLND_SUPERAA_REGAMMA_EN 8 8 mmBLNDV0_BLNDV_UPDATE 0 0x12de 3 0 2 BLND_UPDATE_PENDING 0 0 BLND_UPDATE_TAKEN 8 8 BLND_UPDATE_LOCK 16 16 mmBLNDV0_BLNDV_UNDERFLOW_INTERRUPT 0 0x12df 4 0 2 BLND_UNDERFLOW_INT_OCCURED 0 0 BLND_UNDERFLOW_INT_ACK 8 8 BLND_UNDERFLOW_INT_MASK 12 12 BLND_UNDERFLOW_INT_PIPE_INDEX 16 17 mmBLNDV0_BLNDV_V_UPDATE_LOCK 0 0x12e0 6 0 2 BLND_DCP_GRPH_V_UPDATE_LOCK 0 0 BLND_DCP_GRPH_SURF_V_UPDATE_LOCK 1 1 BLND_DCP_CUR_V_UPDATE_LOCK 16 16 BLND_SCL_V_UPDATE_LOCK 28 28 BLND_BLND_V_UPDATE_LOCK 29 29 BLND_V_UPDATE_LOCK_MODE 31 31 mmBLNDV0_BLNDV_REG_UPDATE_STATUS 0 0x12e1 10 0 2 DCP_BLNDC_GRPH_UPDATE_PENDING 0 0 DCP_BLNDO_GRPH_UPDATE_PENDING 1 1 DCP_BLNDC_GRPH_SURF_UPDATE_PENDING 2 2 DCP_BLNDO_GRPH_SURF_UPDATE_PENDING 3 3 DCP_BLNDC_CUR_UPDATE_PENDING 6 6 DCP_BLNDO_CUR_UPDATE_PENDING 7 7 SCL_BLNDC_UPDATE_PENDING 8 8 SCL_BLNDO_UPDATE_PENDING 9 9 BLND_BLNDC_UPDATE_PENDING 10 10 BLND_BLNDO_UPDATE_PENDING 11 11 mmCRTCV0_CRTCV_H_BLANK_EARLY_NUM 0 0x12e6 2 0 2 CRTC_H_BLANK_EARLY_NUM 0 9 CRTC_H_BLANK_EARLY_NUM_DIS 16 16 mmCRTCV0_CRTCV_H_TOTAL 0 0x12e7 1 0 2 CRTC_H_TOTAL 0 13 mmCRTCV0_CRTCV_H_BLANK_START_END 0 0x12e8 2 0 2 CRTC_H_BLANK_START 0 13 CRTC_H_BLANK_END 16 29 mmCRTCV0_CRTCV_H_SYNC_A 0 0x12e9 2 0 2 CRTC_H_SYNC_A_START 0 13 CRTC_H_SYNC_A_END 16 29 mmCRTCV0_CRTCV_H_SYNC_A_CNTL 0 0x12ea 3 0 2 CRTC_H_SYNC_A_POL 0 0 CRTC_COMP_SYNC_A_EN 16 16 CRTC_H_SYNC_A_CUTOFF 17 17 mmCRTCV0_CRTCV_H_SYNC_B 0 0x12eb 2 0 2 CRTC_H_SYNC_B_START 0 13 CRTC_H_SYNC_B_END 16 29 mmCRTCV0_CRTCV_H_SYNC_B_CNTL 0 0x12ec 3 0 2 CRTC_H_SYNC_B_POL 0 0 CRTC_COMP_SYNC_B_EN 16 16 CRTC_H_SYNC_B_CUTOFF 17 17 mmCRTCV0_CRTCV_VBI_END 0 0x12ed 2 0 2 CRTC_VBI_V_END 0 13 CRTC_VBI_H_END 16 29 mmCRTCV0_CRTCV_V_TOTAL 0 0x12ee 1 0 2 CRTC_V_TOTAL 0 13 mmCRTCV0_CRTCV_V_TOTAL_MIN 0 0x12ef 1 0 2 CRTC_V_TOTAL_MIN 0 13 mmCRTCV0_CRTCV_V_TOTAL_MAX 0 0x12f0 2 0 2 CRTC_V_TOTAL_MAX 0 13 CRTC_ALLOW_VBLANK_EXTENSION_FOR_MC_TRAINING 16 16 mmCRTCV0_CRTCV_V_TOTAL_CONTROL 0 0x12f1 6 0 2 CRTC_V_TOTAL_MIN_SEL 0 0 CRTC_V_TOTAL_MAX_SEL 4 4 CRTC_FORCE_LOCK_ON_EVENT 8 8 CRTC_FORCE_LOCK_TO_MASTER_VSYNC 12 12 CRTC_SET_V_TOTAL_MIN_MASK_EN 15 15 CRTC_SET_V_TOTAL_MIN_MASK 16 31 mmCRTCV0_CRTCV_V_TOTAL_INT_STATUS 0 0x12f2 4 0 2 CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED 0 0 CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT 4 4 CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_ACK 8 8 CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_MSK 12 12 mmCRTCV0_CRTCV_VSYNC_NOM_INT_STATUS 0 0x12f3 2 0 2 CRTC_VSYNC_NOM 0 0 CRTC_VSYNC_NOM_INT_CLEAR 4 4 mmCRTCV0_CRTCV_V_BLANK_START_END 0 0x12f4 2 0 2 CRTC_V_BLANK_START 0 13 CRTC_V_BLANK_END 16 29 mmCRTCV0_CRTCV_V_SYNC_A 0 0x12f5 2 0 2 CRTC_V_SYNC_A_START 0 13 CRTC_V_SYNC_A_END 16 29 mmCRTCV0_CRTCV_V_SYNC_A_CNTL 0 0x12f6 1 0 2 CRTC_V_SYNC_A_POL 0 0 mmCRTCV0_CRTCV_V_SYNC_B 0 0x12f7 2 0 2 CRTC_V_SYNC_B_START 0 13 CRTC_V_SYNC_B_END 16 29 mmCRTCV0_CRTCV_V_SYNC_B_CNTL 0 0x12f8 1 0 2 CRTC_V_SYNC_B_POL 0 0 mmCRTCV0_CRTCV_DTMTEST_CNTL 0 0x12f9 2 0 2 CRTC_DTMTEST_CRTC_EN 0 0 CRTC_DTMTEST_CLK_DIV 1 4 mmCRTCV0_CRTCV_DTMTEST_STATUS_POSITION 0 0x12fa 2 0 2 CRTC_DTMTEST_VERT_COUNT 0 13 CRTC_DTMTEST_HORZ_COUNT 16 29 mmCRTCV0_CRTCV_TRIGA_CNTL 0 0x12fb 11 0 2 CRTC_TRIGA_SOURCE_SELECT 0 4 CRTC_TRIGA_POLARITY_SELECT 5 7 CRTC_TRIGA_RESYNC_BYPASS_EN 8 8 CRTC_TRIGA_INPUT_STATUS 9 9 CRTC_TRIGA_POLARITY_STATUS 10 10 CRTC_TRIGA_OCCURRED 11 11 CRTC_TRIGA_RISING_EDGE_DETECT_CNTL 12 13 CRTC_TRIGA_FALLING_EDGE_DETECT_CNTL 16 17 CRTC_TRIGA_FREQUENCY_SELECT 20 21 CRTC_TRIGA_DELAY 24 28 CRTC_TRIGA_CLEAR 31 31 mmCRTCV0_CRTCV_TRIGA_MANUAL_TRIG 0 0x12fc 1 0 2 CRTC_TRIGA_MANUAL_TRIG 0 0 mmCRTCV0_CRTCV_TRIGB_CNTL 0 0x12fd 11 0 2 CRTC_TRIGB_SOURCE_SELECT 0 4 CRTC_TRIGB_POLARITY_SELECT 5 7 CRTC_TRIGB_RESYNC_BYPASS_EN 8 8 CRTC_TRIGB_INPUT_STATUS 9 9 CRTC_TRIGB_POLARITY_STATUS 10 10 CRTC_TRIGB_OCCURRED 11 11 CRTC_TRIGB_RISING_EDGE_DETECT_CNTL 12 13 CRTC_TRIGB_FALLING_EDGE_DETECT_CNTL 16 17 CRTC_TRIGB_FREQUENCY_SELECT 20 21 CRTC_TRIGB_DELAY 24 28 CRTC_TRIGB_CLEAR 31 31 mmCRTCV0_CRTCV_TRIGB_MANUAL_TRIG 0 0x12fe 1 0 2 CRTC_TRIGB_MANUAL_TRIG 0 0 mmCRTCV0_CRTCV_FORCE_COUNT_NOW_CNTL 0 0x12ff 5 0 2 CRTC_FORCE_COUNT_NOW_MODE 0 1 CRTC_FORCE_COUNT_NOW_CHECK 4 4 CRTC_FORCE_COUNT_NOW_TRIG_SEL 8 8 CRTC_FORCE_COUNT_NOW_OCCURRED 16 16 CRTC_FORCE_COUNT_NOW_CLEAR 24 24 mmCRTCV0_CRTCV_FLOW_CONTROL 0 0x1300 4 0 2 CRTC_FLOW_CONTROL_SOURCE_SELECT 0 4 CRTC_FLOW_CONTROL_POLARITY 8 8 CRTC_FLOW_CONTROL_GRANULARITY 16 16 CRTC_FLOW_CONTROL_INPUT_STATUS 24 24 mmCRTCV0_CRTCV_STEREO_FORCE_NEXT_EYE 0 0x1301 3 0 2 CRTC_STEREO_FORCE_NEXT_EYE 0 1 CRTC_AVSYNC_FRAME_COUNTER 8 15 CRTC_AVSYNC_LINE_COUNTER 16 28 mmCRTCV0_CRTCV_AVSYNC_COUNTER 0 0x1302 1 0 2 CRTC_AVSYNC_COUNTER 0 31 mmCRTCV0_CRTCV_CONTROL 0 0x1303 11 0 2 CRTC_MASTER_EN 0 0 CRTC_SYNC_RESET_SEL 4 4 CRTC_DISABLE_POINT_CNTL 8 9 CRTC_START_POINT_CNTL 12 12 CRTC_FIELD_NUMBER_CNTL 13 13 CRTC_FIELD_NUMBER_POLARITY 14 14 CRTC_CURRENT_MASTER_EN_STATE 16 16 CRTC_HBLANK_EARLY_CONTROL 20 22 CRTC_SOF_PULL_EN 29 29 CRTC_AVSYNC_LOCK_SNAPSHOT 30 30 CRTC_AVSYNC_VSYNC_N_HSYNC_MODE 31 31 mmCRTCV0_CRTCV_BLANK_CONTROL 0 0x1304 3 0 2 CRTC_CURRENT_BLANK_STATE 0 0 CRTC_BLANK_DATA_EN 8 8 CRTC_BLANK_DE_MODE 16 16 mmCRTCV0_CRTCV_INTERLACE_CONTROL 0 0x1305 2 0 2 CRTC_INTERLACE_ENABLE 0 0 CRTC_INTERLACE_FORCE_NEXT_FIELD 16 17 mmCRTCV0_CRTCV_INTERLACE_STATUS 0 0x1306 2 0 2 CRTC_INTERLACE_CURRENT_FIELD 0 0 CRTC_INTERLACE_NEXT_FIELD 1 1 mmCRTCV0_CRTCV_FIELD_INDICATION_CONTROL 0 0x1307 2 0 2 CRTC_FIELD_INDICATION_OUTPUT_POLARITY 0 0 CRTC_FIELD_ALIGNMENT 1 1 mmCRTCV0_CRTCV_PIXEL_DATA_READBACK0 0 0x1308 2 0 2 CRTC_PIXEL_DATA_BLUE_CB 0 11 CRTC_PIXEL_DATA_GREEN_Y 16 27 mmCRTCV0_CRTCV_PIXEL_DATA_READBACK1 0 0x1309 1 0 2 CRTC_PIXEL_DATA_RED_CR 0 11 mmCRTCV0_CRTCV_STATUS 0 0x130a 9 0 2 CRTC_V_BLANK 0 0 CRTC_V_ACTIVE_DISP 1 1 CRTC_V_SYNC_A 2 2 CRTC_V_UPDATE 3 3 CRTC_V_START_LINE 4 4 CRTC_V_BLANK_3D_STRUCTURE 5 5 CRTC_H_BLANK 16 16 CRTC_H_ACTIVE_DISP 17 17 CRTC_H_SYNC_A 18 18 mmCRTCV0_CRTCV_STATUS_POSITION 0 0x130b 2 0 2 CRTC_VERT_COUNT 0 13 CRTC_HORZ_COUNT 16 29 mmCRTCV0_CRTCV_NOM_VERT_POSITION 0 0x130c 1 0 2 CRTC_VERT_COUNT_NOM 0 13 mmCRTCV0_CRTCV_STATUS_FRAME_COUNT 0 0x130d 1 0 2 CRTC_FRAME_COUNT 0 23 mmCRTCV0_CRTCV_STATUS_VF_COUNT 0 0x130e 1 0 2 CRTC_VF_COUNT 0 29 mmCRTCV0_CRTCV_STATUS_HV_COUNT 0 0x130f 1 0 2 CRTC_HV_COUNT 0 29 mmCRTCV0_CRTCV_COUNT_CONTROL 0 0x1310 2 0 2 CRTC_HORZ_COUNT_BY2_EN 0 0 CRTC_HORZ_REPETITION_COUNT 1 4 mmCRTCV0_CRTCV_COUNT_RESET 0 0x1311 1 0 2 CRTC_RESET_FRAME_COUNT 0 0 mmCRTCV0_CRTCV_MANUAL_FORCE_VSYNC_NEXT_LINE 0 0x1312 1 0 2 CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE 0 0 mmCRTCV0_CRTCV_VERT_SYNC_CONTROL 0 0x1313 3 0 2 CRTC_FORCE_VSYNC_NEXT_LINE_OCCURRED 0 0 CRTC_FORCE_VSYNC_NEXT_LINE_CLEAR 8 8 CRTC_AUTO_FORCE_VSYNC_MODE 16 17 mmCRTCV0_CRTCV_STEREO_STATUS 0 0x1314 5 0 2 CRTC_STEREO_CURRENT_EYE 0 0 CRTC_STEREO_SYNC_OUTPUT 8 8 CRTC_STEREO_SYNC_SELECT 16 16 CRTC_STEREO_EYE_FLAG 20 20 CRTC_STEREO_FORCE_NEXT_EYE_PENDING 24 25 mmCRTCV0_CRTCV_STEREO_CONTROL 0 0x1315 8 0 2 CRTC_STEREO_SYNC_OUTPUT_LINE_NUM 0 13 CRTC_STEREO_SYNC_OUTPUT_POLARITY 15 15 CRTC_STEREO_SYNC_SELECT_POLARITY 16 16 CRTC_STEREO_EYE_FLAG_POLARITY 17 17 CRTC_DISABLE_STEREOSYNC_OUTPUT_FOR_DP 18 18 CRTC_DISABLE_FIELD_NUM 19 19 CRTC_DISABLE_V_BLANK_FOR_DP_FIX 20 20 CRTC_STEREO_EN 24 24 mmCRTCV0_CRTCV_SNAPSHOT_STATUS 0 0x1316 3 0 2 CRTC_SNAPSHOT_OCCURRED 0 0 CRTC_SNAPSHOT_CLEAR 1 1 CRTC_SNAPSHOT_MANUAL_TRIGGER 2 2 mmCRTCV0_CRTCV_SNAPSHOT_CONTROL 0 0x1317 1 0 2 CRTC_AUTO_SNAPSHOT_TRIG_SEL 0 1 mmCRTCV0_CRTCV_SNAPSHOT_POSITION 0 0x1318 2 0 2 CRTC_SNAPSHOT_VERT_COUNT 0 13 CRTC_SNAPSHOT_HORZ_COUNT 16 29 mmCRTCV0_CRTCV_SNAPSHOT_FRAME 0 0x1319 1 0 2 CRTC_SNAPSHOT_FRAME_COUNT 0 23 mmCRTCV0_CRTCV_START_LINE_CONTROL 0 0x131a 5 0 2 CRTC_PROGRESSIVE_START_LINE_EARLY 0 0 CRTC_INTERLACE_START_LINE_EARLY 1 1 CRTC_PREFETCH_EN 2 2 CRTC_LEGACY_REQUESTOR_EN 8 8 CRTC_ADVANCED_START_LINE_POSITION 12 19 mmCRTCV0_CRTCV_INTERRUPT_CONTROL 0 0x131b 16 0 2 CRTC_SNAPSHOT_INT_MSK 0 0 CRTC_SNAPSHOT_INT_TYPE 1 1 CRTC_V_UPDATE_INT_MSK 4 4 CRTC_V_UPDATE_INT_TYPE 5 5 CRTC_FORCE_COUNT_NOW_INT_MSK 8 8 CRTC_FORCE_COUNT_NOW_INT_TYPE 9 9 CRTC_FORCE_VSYNC_NEXT_LINE_INT_MSK 16 16 CRTC_FORCE_VSYNC_NEXT_LINE_INT_TYPE 17 17 CRTC_TRIGA_INT_MSK 24 24 CRTC_TRIGB_INT_MSK 25 25 CRTC_TRIGA_INT_TYPE 26 26 CRTC_TRIGB_INT_TYPE 27 27 CRTC_VSYNC_NOM_INT_MSK 28 28 CRTC_VSYNC_NOM_INT_TYPE 29 29 CRTC_GSL_VSYNC_GAP_INT_MSK 30 30 CRTC_GSL_VSYNC_GAP_INT_TYPE 31 31 mmCRTCV0_CRTCV_UPDATE_LOCK 0 0x131c 1 0 2 CRTC_UPDATE_LOCK 0 0 mmCRTCV0_CRTCV_DOUBLE_BUFFER_CONTROL 0 0x131d 5 0 2 CRTC_UPDATE_PENDING 0 0 CRTC_UPDATE_INSTANTLY 8 8 CRTC_BLANK_DATA_DOUBLE_BUFFER_EN 16 16 CRTC_RANGE_TIMING_DBUF_UPDATE_MODE 24 24 CRTC_RANGE_TIMING_DBUF_UPDATE_PENDING 25 25 mmCRTCV0_CRTCV_VGA_PARAMETER_CAPTURE_MODE 0 0x131e 1 0 2 CRTC_VGA_PARAMETER_CAPTURE_MODE 0 0 mmCRTCV0_CRTCV_TEST_PATTERN_CONTROL 0 0x131f 4 0 2 CRTC_TEST_PATTERN_EN 0 0 CRTC_TEST_PATTERN_MODE 8 10 CRTC_TEST_PATTERN_DYNAMIC_RANGE 16 16 CRTC_TEST_PATTERN_COLOR_FORMAT 24 31 mmCRTCV0_CRTCV_TEST_PATTERN_PARAMETERS 0 0x1320 5 0 2 CRTC_TEST_PATTERN_INC0 0 3 CRTC_TEST_PATTERN_INC1 4 7 CRTC_TEST_PATTERN_VRES 8 11 CRTC_TEST_PATTERN_HRES 12 15 CRTC_TEST_PATTERN_RAMP0_OFFSET 16 31 mmCRTCV0_CRTCV_TEST_PATTERN_COLOR 0 0x1321 2 0 2 CRTC_TEST_PATTERN_DATA 0 15 CRTC_TEST_PATTERN_MASK 16 21 mmCRTCV0_CRTCV_MASTER_UPDATE_LOCK 0 0x1322 3 0 2 MASTER_UPDATE_LOCK 0 0 GSL_CONTROL_MASTER_UPDATE_LOCK 8 8 UNDERFLOW_UPDATE_LOCK 16 16 mmCRTCV0_CRTCV_MASTER_UPDATE_MODE 0 0x1323 2 0 2 MASTER_UPDATE_MODE 0 2 MASTER_UPDATE_INTERLACED_MODE 16 17 mmCRTCV0_CRTCV_MVP_INBAND_CNTL_INSERT 0 0x1324 2 0 2 CRTC_MVP_INBAND_OUT_MODE 0 1 CRTC_MVP_INBAND_CNTL_CHAR_INSERT 8 31 mmCRTCV0_CRTCV_MVP_INBAND_CNTL_INSERT_TIMER 0 0x1325 1 0 2 CRTC_MVP_INBAND_CNTL_CHAR_INSERT_TIMER 0 7 mmCRTCV0_CRTCV_MVP_STATUS 0 0x1326 4 0 2 CRTC_FLIP_NOW_OCCURRED 0 0 CRTC_AFR_HSYNC_SWITCH_DONE_OCCURRED 4 4 CRTC_FLIP_NOW_CLEAR 16 16 CRTC_AFR_HSYNC_SWITCH_DONE_CLEAR 20 20 mmCRTCV0_CRTCV_MASTER_EN 0 0x1327 1 0 2 CRTC_MASTER_EN 0 0 mmCRTCV0_CRTCV_ALLOW_STOP_OFF_V_CNT 0 0x1328 2 0 2 CRTC_ALLOW_STOP_OFF_V_CNT 0 7 CRTC_DISABLE_ALLOW_STOP_OFF_V_CNT 16 16 mmCRTCV0_CRTCV_V_UPDATE_INT_STATUS 0 0x1329 2 0 2 CRTC_V_UPDATE_INT_OCCURRED 0 0 CRTC_V_UPDATE_INT_CLEAR 8 8 mmCRTCV0_CRTCV_OVERSCAN_COLOR 0 0x132b 3 0 2 CRTC_OVERSCAN_COLOR_BLUE 0 9 CRTC_OVERSCAN_COLOR_GREEN 10 19 CRTC_OVERSCAN_COLOR_RED 20 29 mmCRTCV0_CRTCV_OVERSCAN_COLOR_EXT 0 0x132c 3 0 2 CRTC_OVERSCAN_COLOR_BLUE_EXT 0 1 CRTC_OVERSCAN_COLOR_GREEN_EXT 8 9 CRTC_OVERSCAN_COLOR_RED_EXT 16 17 mmCRTCV0_CRTCV_BLANK_DATA_COLOR 0 0x132d 3 0 2 CRTC_BLANK_DATA_COLOR_BLUE_CB 0 9 CRTC_BLANK_DATA_COLOR_GREEN_Y 10 19 CRTC_BLANK_DATA_COLOR_RED_CR 20 29 mmCRTCV0_CRTCV_BLANK_DATA_COLOR_EXT 0 0x132e 3 0 2 CRTC_BLANK_DATA_COLOR_BLUE_CB_EXT 0 1 CRTC_BLANK_DATA_COLOR_GREEN_Y_EXT 8 9 CRTC_BLANK_DATA_COLOR_RED_CR_EXT 16 17 mmCRTCV0_CRTCV_BLACK_COLOR 0 0x132f 3 0 2 CRTC_BLACK_COLOR_B_CB 0 9 CRTC_BLACK_COLOR_G_Y 10 19 CRTC_BLACK_COLOR_R_CR 20 29 mmCRTCV0_CRTCV_BLACK_COLOR_EXT 0 0x1330 3 0 2 CRTC_BLACK_COLOR_B_CB_EXT 0 1 CRTC_BLACK_COLOR_G_Y_EXT 8 9 CRTC_BLACK_COLOR_R_CR_EXT 16 17 mmCRTCV0_CRTCV_VERTICAL_INTERRUPT0_POSITION 0 0x1331 2 0 2 CRTC_VERTICAL_INTERRUPT0_LINE_START 0 13 CRTC_VERTICAL_INTERRUPT0_LINE_END 16 29 mmCRTCV0_CRTCV_VERTICAL_INTERRUPT0_CONTROL 0 0x1332 6 0 2 CRTC_VERTICAL_INTERRUPT0_OUTPUT_POLARITY 4 4 CRTC_VERTICAL_INTERRUPT0_INT_ENABLE 8 8 CRTC_VERTICAL_INTERRUPT0_STATUS 12 12 CRTC_VERTICAL_INTERRUPT0_INT_STATUS 16 16 CRTC_VERTICAL_INTERRUPT0_CLEAR 20 20 CRTC_VERTICAL_INTERRUPT0_INT_TYPE 24 24 mmCRTCV0_CRTCV_VERTICAL_INTERRUPT1_POSITION 0 0x1333 1 0 2 CRTC_VERTICAL_INTERRUPT1_LINE_START 0 13 mmCRTCV0_CRTCV_VERTICAL_INTERRUPT1_CONTROL 0 0x1334 5 0 2 CRTC_VERTICAL_INTERRUPT1_INT_ENABLE 8 8 CRTC_VERTICAL_INTERRUPT1_STATUS 12 12 CRTC_VERTICAL_INTERRUPT1_INT_STATUS 16 16 CRTC_VERTICAL_INTERRUPT1_CLEAR 20 20 CRTC_VERTICAL_INTERRUPT1_INT_TYPE 24 24 mmCRTCV0_CRTCV_VERTICAL_INTERRUPT2_POSITION 0 0x1335 1 0 2 CRTC_VERTICAL_INTERRUPT2_LINE_START 0 13 mmCRTCV0_CRTCV_VERTICAL_INTERRUPT2_CONTROL 0 0x1336 5 0 2 CRTC_VERTICAL_INTERRUPT2_INT_ENABLE 8 8 CRTC_VERTICAL_INTERRUPT2_STATUS 12 12 CRTC_VERTICAL_INTERRUPT2_INT_STATUS 16 16 CRTC_VERTICAL_INTERRUPT2_CLEAR 20 20 CRTC_VERTICAL_INTERRUPT2_INT_TYPE 24 24 mmCRTCV0_CRTCV_CRC_CNTL 0 0x1337 7 0 2 CRTC_CRC_EN 0 0 CRTC_CRC_CONT_EN 4 4 CRTC_CRC_STEREO_MODE 8 9 CRTC_CRC_INTERLACE_MODE 12 13 CRTC_CRC_USE_NEW_AND_REPEATED_PIXELS 16 16 CRTC_CRC0_SELECT 20 22 CRTC_CRC1_SELECT 24 26 mmCRTCV0_CRTCV_CRC0_WINDOWA_X_CONTROL 0 0x1338 2 0 2 CRTC_CRC0_WINDOWA_X_START 0 13 CRTC_CRC0_WINDOWA_X_END 16 29 mmCRTCV0_CRTCV_CRC0_WINDOWA_Y_CONTROL 0 0x1339 2 0 2 CRTC_CRC0_WINDOWA_Y_START 0 13 CRTC_CRC0_WINDOWA_Y_END 16 29 mmCRTCV0_CRTCV_CRC0_WINDOWB_X_CONTROL 0 0x133a 2 0 2 CRTC_CRC0_WINDOWB_X_START 0 13 CRTC_CRC0_WINDOWB_X_END 16 29 mmCRTCV0_CRTCV_CRC0_WINDOWB_Y_CONTROL 0 0x133b 2 0 2 CRTC_CRC0_WINDOWB_Y_START 0 13 CRTC_CRC0_WINDOWB_Y_END 16 29 mmCRTCV0_CRTCV_CRC0_DATA_RG 0 0x133c 2 0 2 CRC0_R_CR 0 15 CRC0_G_Y 16 31 mmCRTCV0_CRTCV_CRC0_DATA_B 0 0x133d 1 0 2 CRC0_B_CB 0 15 mmCRTCV0_CRTCV_CRC1_WINDOWA_X_CONTROL 0 0x133e 2 0 2 CRTC_CRC1_WINDOWA_X_START 0 13 CRTC_CRC1_WINDOWA_X_END 16 29 mmCRTCV0_CRTCV_CRC1_WINDOWA_Y_CONTROL 0 0x133f 2 0 2 CRTC_CRC1_WINDOWA_Y_START 0 13 CRTC_CRC1_WINDOWA_Y_END 16 29 mmCRTCV0_CRTCV_CRC1_WINDOWB_X_CONTROL 0 0x1340 2 0 2 CRTC_CRC1_WINDOWB_X_START 0 13 CRTC_CRC1_WINDOWB_X_END 16 29 mmCRTCV0_CRTCV_CRC1_WINDOWB_Y_CONTROL 0 0x1341 2 0 2 CRTC_CRC1_WINDOWB_Y_START 0 13 CRTC_CRC1_WINDOWB_Y_END 16 29 mmCRTCV0_CRTCV_CRC1_DATA_RG 0 0x1342 2 0 2 CRC1_R_CR 0 15 CRC1_G_Y 16 31 mmCRTCV0_CRTCV_CRC1_DATA_B 0 0x1343 1 0 2 CRC1_B_CB 0 15 mmCRTCV0_CRTCV_EXT_TIMING_SYNC_CONTROL 0 0x1344 11 0 2 CRTC_EXT_TIMING_SYNC_ENABLE 0 1 CRTC_EXT_TIMING_SYNC_HCOUNT_MODE_ENABLE 3 3 CRTC_EXT_TIMING_SYNC_JITTER_FILTERING_ENABLE 4 4 CRTC_EXT_TIMING_SYNC_JITTER_FILTERING_WINDOW 5 6 CRTC_EXT_TIMING_SYNC_WINDOW_ENABLE 8 8 CRTC_EXT_TIMING_SYNC_WINDOW_UPDATE 9 9 CRTC_EXT_TIMING_SYNC_VSYNC_POLARITY 12 12 CRTC_EXT_TIMING_SYNC_HSYNC_POLARITY 13 13 CRTC_EXT_TIMING_SYNC_INTERLACE_MODE 14 14 CRTC_EXT_TIMING_SYNC_MASTER_FRAME_RATE 24 26 CRTC_EXT_TIMING_SYNC_SLAVE_FRAME_RATE 28 30 mmCRTCV0_CRTCV_EXT_TIMING_SYNC_WINDOW_START 0 0x1345 2 0 2 CRTC_EXT_TIMING_SYNC_WINDOW_START_X 0 13 CRTC_EXT_TIMING_SYNC_WINDOW_START_Y 16 29 mmCRTCV0_CRTCV_EXT_TIMING_SYNC_WINDOW_END 0 0x1346 2 0 2 CRTC_EXT_TIMING_SYNC_WINDOW_END_X 0 13 CRTC_EXT_TIMING_SYNC_WINDOW_END_Y 16 29 mmCRTCV0_CRTCV_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL 0 0x1347 6 0 2 CRTC_EXT_TIMING_SYNC_LOSS_INT_ENABLE 0 0 CRTC_EXT_TIMING_SYNC_LOSS_STATUS 4 4 CRTC_EXT_TIMING_SYNC_LOSS_INT_STATUS 8 8 CRTC_EXT_TIMING_SYNC_LOSS_CLEAR 16 16 CRTC_EXT_TIMING_SYNC_LOSS_INT_TYPE 20 20 CRTC_EXT_TIMING_SYNC_LOSS_FRAME_COUNT 29 31 mmCRTCV0_CRTCV_EXT_TIMING_SYNC_INTERRUPT_CONTROL 0 0x1348 5 0 2 CRTC_EXT_TIMING_SYNC_INT_ENABLE 0 0 CRTC_EXT_TIMING_SYNC_STATUS 4 4 CRTC_EXT_TIMING_SYNC_INT_STATUS 8 8 CRTC_EXT_TIMING_SYNC_CLEAR 16 16 CRTC_EXT_TIMING_SYNC_INT_TYPE 20 20 mmCRTCV0_CRTCV_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL 0 0x1349 5 0 2 CRTC_EXT_TIMING_SYNC_SIGNAL_INT_ENABLE 0 0 CRTC_EXT_TIMING_SYNC_SIGNAL_STATUS 4 4 CRTC_EXT_TIMING_SYNC_SIGNAL_INT_STATUS 8 8 CRTC_EXT_TIMING_SYNC_SIGNAL_CLEAR 16 16 CRTC_EXT_TIMING_SYNC_SIGNAL_INT_TYPE 20 20 mmCRTCV0_CRTCV_STATIC_SCREEN_CONTROL 0 0x134a 7 0 2 CRTC_STATIC_SCREEN_EVENT_MASK 0 15 CRTC_STATIC_SCREEN_FRAME_COUNT 16 23 CRTC_CPU_SS_INT_ENABLE 24 24 CRTC_SS_STATUS 25 25 CRTC_CPU_SS_INT_STATUS 26 26 CRTC_CPU_SS_INT_CLEAR 27 27 CRTC_CPU_SS_INT_TYPE 28 28 mmCRTCV0_CRTCV_3D_STRUCTURE_CONTROL 0 0x134b 7 0 2 CRTC_3D_STRUCTURE_EN 0 0 CRTC_3D_STRUCTURE_EN_DB 4 4 CRTC_3D_STRUCTURE_V_UPDATE_MODE 8 9 CRTC_3D_STRUCTURE_STEREO_SEL_OVR 12 12 CRTC_3D_STRUCTURE_F_COUNT_RESET 16 16 CRTC_3D_STRUCTURE_F_COUNT_RESET_PENDING 17 17 CRTC_3D_STRUCTURE_F_COUNT 18 19 mmCRTCV0_CRTCV_GSL_VSYNC_GAP 0 0x134c 8 0 2 CRTC_GSL_VSYNC_GAP_LIMIT 0 7 CRTC_GSL_VSYNC_GAP_DELAY 8 15 CRTC_GSL_VSYNC_GAP_SOURCE_SEL 16 16 CRTC_GSL_VSYNC_GAP_MODE 17 18 CRTC_GSL_VSYNC_GAP_CLEAR 19 19 CRTC_GSL_VSYNC_GAP_OCCURRED 20 20 CRTC_GSL_VSYNC_GAP_MASTER_FASTER 23 23 CRTC_GSL_VSYNC_GAP 24 31 mmCRTCV0_CRTCV_GSL_WINDOW 0 0x134d 2 0 2 CRTC_GSL_WINDOW_START 0 13 CRTC_GSL_WINDOW_END 16 29 mmCRTCV0_CRTCV_GSL_CONTROL 0 0x134e 3 0 2 CRTC_GSL_CHECK_LINE_NUM 0 13 CRTC_GSL_FORCE_DELAY 16 20 CRTC_GSL_CHECK_ALL_FIELDS 28 28 mmUNP1_UNP_GRPH_ENABLE 0 0x135a 1 0 2 GRPH_ENABLE 0 0 mmUNP1_UNP_GRPH_CONTROL 0 0x135b 14 0 2 GRPH_DEPTH 0 1 GRPH_NUM_BANKS 2 3 GRPH_Z 4 5 GRPH_BANK_WIDTH_L 6 7 GRPH_FORMAT 8 10 GRPH_BANK_HEIGHT_L 11 12 GRPH_TILE_SPLIT_L 13 15 GRPH_ADDRESS_TRANSLATION_ENABLE 16 16 GRPH_PRIVILEGED_ACCESS_ENABLE 17 17 GRPH_MACRO_TILE_ASPECT_L 18 19 GRPH_ARRAY_MODE 20 23 GRPH_PIPE_CONFIG 24 28 GRPH_MICRO_TILE_MODE_L 29 30 GRPH_COLOR_EXPANSION_MODE 31 31 mmUNP1_UNP_GRPH_CONTROL_C 0 0x135c 5 0 2 GRPH_BANK_WIDTH_C 6 7 GRPH_BANK_HEIGHT_C 11 12 GRPH_TILE_SPLIT_C 13 15 GRPH_MACRO_TILE_ASPECT_C 18 19 GRPH_MICRO_TILE_MODE_C 29 30 mmUNP1_UNP_GRPH_CONTROL_EXP 0 0x135d 1 0 2 VIDEO_FORMAT 0 2 mmUNP1_UNP_GRPH_SWAP_CNTL 0 0x135e 4 0 2 GRPH_ENDIAN_SWAP 0 1 GRPH_RED_CROSSBAR 4 5 GRPH_GREEN_CROSSBAR 6 7 GRPH_BLUE_CROSSBAR 8 9 mmUNP1_UNP_GRPH_PRIMARY_SURFACE_ADDRESS_L 0 0x135f 1 0 2 GRPH_PRIMARY_SURFACE_ADDRESS_L 8 31 mmUNP1_UNP_GRPH_PRIMARY_SURFACE_ADDRESS_C 0 0x1360 1 0 2 GRPH_PRIMARY_SURFACE_ADDRESS_C 8 31 mmUNP1_UNP_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_L 0 0x1361 1 0 2 GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_L 0 7 mmUNP1_UNP_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_C 0 0x1362 1 0 2 GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_C 0 7 mmUNP1_UNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_L 0 0x1363 1 0 2 GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_L 8 31 mmUNP1_UNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_C 0 0x1364 1 0 2 GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_C 8 31 mmUNP1_UNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_HIGH_L 0 0x1365 1 0 2 GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_HIGH_L 0 7 mmUNP1_UNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_HIGH_C 0 0x1366 1 0 2 GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_HIGH_C 0 7 mmUNP1_UNP_GRPH_SECONDARY_SURFACE_ADDRESS_L 0 0x1367 1 0 2 GRPH_SECONDARY_SURFACE_ADDRESS_L 8 31 mmUNP1_UNP_GRPH_SECONDARY_SURFACE_ADDRESS_C 0 0x1368 1 0 2 GRPH_SECONDARY_SURFACE_ADDRESS_C 8 31 mmUNP1_UNP_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_L 0 0x1369 1 0 2 GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_L 0 7 mmUNP1_UNP_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_C 0 0x136a 1 0 2 GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_C 0 7 mmUNP1_UNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_L 0 0x136b 1 0 2 GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_L 8 31 mmUNP1_UNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_C 0 0x136c 1 0 2 GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_C 8 31 mmUNP1_UNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_HIGH_L 0 0x136d 1 0 2 GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_HIGH_L 0 7 mmUNP1_UNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_HIGH_C 0 0x136e 1 0 2 GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_HIGH_C 0 7 mmUNP1_UNP_GRPH_PITCH_L 0 0x136f 1 0 2 GRPH_PITCH_L 0 14 mmUNP1_UNP_GRPH_PITCH_C 0 0x1370 1 0 2 GRPH_PITCH_C 0 14 mmUNP1_UNP_GRPH_SURFACE_OFFSET_X_L 0 0x1371 1 0 2 GRPH_SURFACE_OFFSET_X_L 0 13 mmUNP1_UNP_GRPH_SURFACE_OFFSET_X_C 0 0x1372 1 0 2 GRPH_SURFACE_OFFSET_X_C 0 13 mmUNP1_UNP_GRPH_SURFACE_OFFSET_Y_L 0 0x1373 1 0 2 GRPH_SURFACE_OFFSET_Y_L 0 13 mmUNP1_UNP_GRPH_SURFACE_OFFSET_Y_C 0 0x1374 1 0 2 GRPH_SURFACE_OFFSET_Y_C 0 13 mmUNP1_UNP_GRPH_X_START_L 0 0x1375 1 0 2 GRPH_X_START_L 0 13 mmUNP1_UNP_GRPH_X_START_C 0 0x1376 1 0 2 GRPH_X_START_C 0 13 mmUNP1_UNP_GRPH_Y_START_L 0 0x1377 1 0 2 GRPH_Y_START_L 0 13 mmUNP1_UNP_GRPH_Y_START_C 0 0x1378 1 0 2 GRPH_Y_START_C 0 13 mmUNP1_UNP_GRPH_X_END_L 0 0x1379 1 0 2 GRPH_X_END_L 0 14 mmUNP1_UNP_GRPH_X_END_C 0 0x137a 1 0 2 GRPH_X_END_C 0 14 mmUNP1_UNP_GRPH_Y_END_L 0 0x137b 1 0 2 GRPH_Y_END_L 0 14 mmUNP1_UNP_GRPH_Y_END_C 0 0x137c 1 0 2 GRPH_Y_END_C 0 14 mmUNP1_UNP_GRPH_UPDATE 0 0x137d 8 0 2 GRPH_MODE_UPDATE_PENDING 0 0 GRPH_MODE_UPDATE_TAKEN 1 1 GRPH_SURFACE_UPDATE_PENDING 2 2 GRPH_SURFACE_UPDATE_TAKEN 3 3 GRPH_UPDATE_LOCK 16 16 GRPH_SURFACE_IGNORE_UPDATE_LOCK 20 20 GRPH_MODE_DISABLE_MULTIPLE_UPDATE 24 24 GRPH_SURFACE_DISABLE_MULTIPLE_UPDATE 28 28 mmUNP1_UNP_PIPE_OUTSTANDING_REQUEST_LIMIT 0 0x137e 2 0 2 UNP_PIPE_OUTSTANDING_REQUEST_LIMIT_L 0 7 UNP_PIPE_OUTSTANDING_REQUEST_LIMIT_C 8 15 mmUNP1_UNP_GRPH_SURFACE_ADDRESS_INUSE_L 0 0x137f 1 0 2 GRPH_SURFACE_ADDRESS_INUSE_L 8 31 mmUNP1_UNP_GRPH_SURFACE_ADDRESS_INUSE_C 0 0x1380 1 0 2 GRPH_SURFACE_ADDRESS_INUSE_C 8 31 mmUNP1_UNP_GRPH_SURFACE_ADDRESS_HIGH_INUSE_L 0 0x1381 1 0 2 GRPH_SURFACE_ADDRESS_HIGH_INUSE_L 0 7 mmUNP1_UNP_GRPH_SURFACE_ADDRESS_HIGH_INUSE_C 0 0x1382 1 0 2 GRPH_SURFACE_ADDRESS_HIGH_INUSE_C 0 7 mmUNP1_UNP_DVMM_PTE_CONTROL 0 0x1383 6 0 2 DVMM_USE_SINGLE_PTE 0 0 DVMM_PAGE_WIDTH 1 4 DVMM_PAGE_HEIGHT 5 8 DVMM_MIN_PTE_BEFORE_FLIP 9 18 DVMM_PTE_BUFFER_MODE0 20 20 DVMM_PTE_BUFFER_MODE1 21 21 mmUNP1_UNP_DVMM_PTE_CONTROL_C 0 0x1384 6 0 2 DVMM_USE_SINGLE_PTE_C 0 0 DVMM_PAGE_WIDTH_C 1 4 DVMM_PAGE_HEIGHT_C 5 8 DVMM_MIN_PTE_BEFORE_FLIP_C 9 18 DVMM_PTE_BUFFER_MODE0_C 20 20 DVMM_PTE_BUFFER_MODE1_C 21 21 mmUNP1_UNP_DVMM_PTE_ARB_CONTROL 0 0x1385 2 0 2 DVMM_PTE_REQ_PER_CHUNK 0 5 DVMM_MAX_PTE_REQ_OUTSTANDING 8 15 mmUNP1_UNP_DVMM_PTE_ARB_CONTROL_C 0 0x1386 2 0 2 DVMM_PTE_REQ_PER_CHUNK_C 0 5 DVMM_MAX_PTE_REQ_OUTSTANDING_C 8 15 mmUNP1_UNP_GRPH_INTERRUPT_STATUS 0 0x1387 2 0 2 GRPH_PFLIP_INT_OCCURRED 0 0 GRPH_PFLIP_INT_CLEAR 8 8 mmUNP1_UNP_GRPH_INTERRUPT_CONTROL 0 0x1388 2 0 2 GRPH_PFLIP_INT_MASK 0 0 GRPH_PFLIP_INT_TYPE 8 8 mmUNP1_UNP_GRPH_STEREOSYNC_FLIP 0 0x1389 9 0 2 GRPH_STEREOSYNC_FLIP_EN 0 0 GRPH_STEREOSYNC_FLIP_MODE 4 5 GRPH_STACK_INTERLACE_FLIP_EN 8 8 GRPH_STACK_INTERLACE_FLIP_MODE 12 13 GRPH_PRIMARY_SURFACE_PENDING 16 16 GRPH_SECONDARY_SURFACE_PENDING 17 17 GRPH_PRIMARY_BOTTOM_SURFACE_PENDING 18 18 GRPH_SECONDARY_BOTTOM_SURFACE_PENDING 19 19 GRPH_STEREOSYNC_SELECT_DISABLE 28 28 mmUNP1_UNP_FLIP_CONTROL 0 0x138a 1 0 2 GRPH_SURFACE_UPDATE_PENDING_MODE 0 0 mmUNP1_UNP_CRC_CONTROL 0 0x138b 3 0 2 UNP_CRC_ENABLE 0 0 UNP_CRC_SOURCE_SEL 2 4 UNP_CRC_LINE_SEL 8 9 mmUNP1_UNP_CRC_MASK 0 0x138c 1 0 2 UNP_CRC_MASK 0 31 mmUNP1_UNP_CRC_CURRENT 0 0x138d 1 0 2 UNP_CRC_CURRENT 0 31 mmUNP1_UNP_CRC_LAST 0 0x138e 1 0 2 UNP_CRC_LAST 0 31 mmUNP1_UNP_LB_DATA_GAP_BETWEEN_CHUNK 0 0x138f 1 0 2 UNP_LB_GAP_BETWEEN_CHUNK 4 8 mmUNP1_UNP_HW_ROTATION 0 0x1390 3 0 2 ROTATION_ANGLE 0 2 PIXEL_DROP 4 4 BUFFER_MODE 8 8 mmLBV1_LBV_DATA_FORMAT 0 0x1396 10 0 2 PIXEL_DEPTH 0 1 PIXEL_EXPAN_MODE 2 2 INTERLEAVE_EN 3 3 PIXEL_REDUCE_MODE 4 4 DYNAMIC_PIXEL_DEPTH 5 5 DITHER_EN 6 6 DOWNSCALE_PREFETCH_EN 7 7 PREFETCH 12 12 REQUEST_MODE 24 24 ALPHA_EN 31 31 mmLBV1_LBV_MEMORY_CTRL 0 0x1397 3 0 2 LB_MEMORY_SIZE 0 11 LB_NUM_PARTITIONS 16 19 LB_MEMORY_CONFIG 20 21 mmLBV1_LBV_MEMORY_SIZE_STATUS 0 0x1398 1 0 2 LB_MEMORY_SIZE_STATUS 0 11 mmLBV1_LBV_DESKTOP_HEIGHT 0 0x1399 1 0 2 DESKTOP_HEIGHT 0 14 mmLBV1_LBV_VLINE_START_END 0 0x139a 3 0 2 VLINE_START 0 13 VLINE_END 16 30 VLINE_INV 31 31 mmLBV1_LBV_VLINE2_START_END 0 0x139b 3 0 2 VLINE2_START 0 13 VLINE2_END 16 30 VLINE2_INV 31 31 mmLBV1_LBV_V_COUNTER 0 0x139c 1 0 2 V_COUNTER 0 14 mmLBV1_LBV_SNAPSHOT_V_COUNTER 0 0x139d 1 0 2 SNAPSHOT_V_COUNTER 0 14 mmLBV1_LBV_V_COUNTER_CHROMA 0 0x139e 1 0 2 V_COUNTER_CHROMA 0 14 mmLBV1_LBV_SNAPSHOT_V_COUNTER_CHROMA 0 0x139f 1 0 2 SNAPSHOT_V_COUNTER_CHROMA 0 14 mmLBV1_LBV_INTERRUPT_MASK 0 0x13a0 3 0 2 VBLANK_INTERRUPT_MASK 0 0 VLINE_INTERRUPT_MASK 4 4 VLINE2_INTERRUPT_MASK 8 8 mmLBV1_LBV_VLINE_STATUS 0 0x13a1 5 0 2 VLINE_OCCURRED 0 0 VLINE_ACK 4 4 VLINE_STAT 12 12 VLINE_INTERRUPT 16 16 VLINE_INTERRUPT_TYPE 17 17 mmLBV1_LBV_VLINE2_STATUS 0 0x13a2 5 0 2 VLINE2_OCCURRED 0 0 VLINE2_ACK 4 4 VLINE2_STAT 12 12 VLINE2_INTERRUPT 16 16 VLINE2_INTERRUPT_TYPE 17 17 mmLBV1_LBV_VBLANK_STATUS 0 0x13a3 5 0 2 VBLANK_OCCURRED 0 0 VBLANK_ACK 4 4 VBLANK_STAT 12 12 VBLANK_INTERRUPT 16 16 VBLANK_INTERRUPT_TYPE 17 17 mmLBV1_LBV_SYNC_RESET_SEL 0 0x13a4 4 0 2 LB_SYNC_RESET_SEL 0 1 LB_SYNC_RESET_SEL2 4 4 LB_SYNC_RESET_DELAY 8 15 LB_SYNC_DURATION 22 23 mmLBV1_LBV_BLACK_KEYER_R_CR 0 0x13a5 1 0 2 LB_BLACK_KEYER_R_CR 4 15 mmLBV1_LBV_BLACK_KEYER_G_Y 0 0x13a6 1 0 2 LB_BLACK_KEYER_G_Y 4 15 mmLBV1_LBV_BLACK_KEYER_B_CB 0 0x13a7 1 0 2 LB_BLACK_KEYER_B_CB 4 15 mmLBV1_LBV_KEYER_COLOR_CTRL 0 0x13a8 2 0 2 LB_KEYER_COLOR_EN 0 0 LB_KEYER_COLOR_REP_EN 8 8 mmLBV1_LBV_KEYER_COLOR_R_CR 0 0x13a9 1 0 2 LB_KEYER_COLOR_R_CR 4 15 mmLBV1_LBV_KEYER_COLOR_G_Y 0 0x13aa 1 0 2 LB_KEYER_COLOR_G_Y 4 15 mmLBV1_LBV_KEYER_COLOR_B_CB 0 0x13ab 1 0 2 LB_KEYER_COLOR_B_CB 4 15 mmLBV1_LBV_KEYER_COLOR_REP_R_CR 0 0x13ac 1 0 2 LB_KEYER_COLOR_REP_R_CR 4 15 mmLBV1_LBV_KEYER_COLOR_REP_G_Y 0 0x13ad 1 0 2 LB_KEYER_COLOR_REP_G_Y 4 15 mmLBV1_LBV_KEYER_COLOR_REP_B_CB 0 0x13ae 1 0 2 LB_KEYER_COLOR_REP_B_CB 4 15 mmLBV1_LBV_BUFFER_LEVEL_STATUS 0 0x13af 4 0 2 REQ_FIFO_LEVEL 0 5 REQ_FIFO_FULL_CNTL 10 15 DATA_BUFFER_LEVEL 16 27 DATA_FIFO_FULL_CNTL 28 31 mmLBV1_LBV_BUFFER_URGENCY_CTRL 0 0x13b0 2 0 2 LB_BUFFER_URGENCY_MARK_ON 0 11 LB_BUFFER_URGENCY_MARK_OFF 16 27 mmLBV1_LBV_BUFFER_URGENCY_STATUS 0 0x13b1 2 0 2 LB_BUFFER_URGENCY_LEVEL 0 11 LB_BUFFER_URGENCY_STAT 16 16 mmLBV1_LBV_BUFFER_STATUS 0 0x13b2 9 0 2 LB_BUFFER_EMPTY_MARGIN 0 3 LB_BUFFER_EMPTY_STAT 4 4 LB_BUFFER_EMPTY_OCCURRED 8 8 LB_BUFFER_EMPTY_ACK 12 12 LB_BUFFER_FULL_STAT 16 16 LB_BUFFER_FULL_OCCURRED 20 20 LB_BUFFER_FULL_ACK 24 24 LB_ENABLE_HIGH_THROUGHPUT 25 25 LB_HIGH_THROUGHPUT_CNTL 26 28 mmLBV1_LBV_NO_OUTSTANDING_REQ_STATUS 0 0x13b3 1 0 2 LB_NO_OUTSTANDING_REQ_STAT 0 0 mmSCLV1_SCLV_COEF_RAM_SELECT 0 0x13ca 3 0 2 SCL_C_RAM_TAP_PAIR_IDX 0 1 SCL_C_RAM_PHASE 8 14 SCL_C_RAM_FILTER_TYPE 16 17 mmSCLV1_SCLV_COEF_RAM_TAP_DATA 0 0x13cb 4 0 2 SCL_C_RAM_EVEN_TAP_COEF 0 13 SCL_C_RAM_EVEN_TAP_COEF_EN 15 15 SCL_C_RAM_ODD_TAP_COEF 16 29 SCL_C_RAM_ODD_TAP_COEF_EN 31 31 mmSCLV1_SCLV_MODE 0 0x13cc 5 0 2 SCL_MODE 0 1 SCL_MODE_C 2 3 SCL_PSCL_EN 4 4 SCL_PSCL_EN_C 5 5 SCL_INTERLACE_SOURCE 8 9 mmSCLV1_SCLV_TAP_CONTROL 0 0x13cd 4 0 2 SCL_V_NUM_OF_TAPS 0 2 SCL_H_NUM_OF_TAPS 4 6 SCL_V_NUM_OF_TAPS_C 8 10 SCL_H_NUM_OF_TAPS_C 12 14 mmSCLV1_SCLV_CONTROL 0 0x13ce 3 0 2 SCL_BOUNDARY_MODE 0 0 SCL_EARLY_EOL_MODE 4 4 SCL_TOTAL_PHASE 8 8 mmSCLV1_SCLV_MANUAL_REPLICATE_CONTROL 0 0x13cf 2 0 2 SCL_V_MANUAL_REPLICATE_FACTOR 0 3 SCL_H_MANUAL_REPLICATE_FACTOR 8 11 mmSCLV1_SCLV_AUTOMATIC_MODE_CONTROL 0 0x13d0 2 0 2 SCL_V_CALC_AUTO_RATIO_EN 0 0 SCL_H_CALC_AUTO_RATIO_EN 16 16 mmSCLV1_SCLV_HORZ_FILTER_CONTROL 0 0x13d1 1 0 2 SCL_H_2TAP_HARDCODE_COEF_EN 8 8 mmSCLV1_SCLV_HORZ_FILTER_SCALE_RATIO 0 0x13d2 1 0 2 SCL_H_SCALE_RATIO 0 25 mmSCLV1_SCLV_HORZ_FILTER_INIT 0 0x13d3 2 0 2 SCL_H_INIT_FRAC 0 23 SCL_H_INIT_INT 24 27 mmSCLV1_SCLV_HORZ_FILTER_SCALE_RATIO_C 0 0x13d4 1 0 2 SCL_H_SCALE_RATIO_C 0 25 mmSCLV1_SCLV_HORZ_FILTER_INIT_C 0 0x13d5 2 0 2 SCL_H_INIT_FRAC_C 0 23 SCL_H_INIT_INT_C 24 27 mmSCLV1_SCLV_VERT_FILTER_CONTROL 0 0x13d6 1 0 2 SCL_V_2TAP_HARDCODE_COEF_EN 8 8 mmSCLV1_SCLV_VERT_FILTER_SCALE_RATIO 0 0x13d7 1 0 2 SCL_V_SCALE_RATIO 0 25 mmSCLV1_SCLV_VERT_FILTER_INIT 0 0x13d8 2 0 2 SCL_V_INIT_FRAC 0 23 SCL_V_INIT_INT 24 26 mmSCLV1_SCLV_VERT_FILTER_INIT_BOT 0 0x13d9 2 0 2 SCL_V_INIT_FRAC_BOT 0 23 SCL_V_INIT_INT_BOT 24 26 mmSCLV1_SCLV_VERT_FILTER_SCALE_RATIO_C 0 0x13da 1 0 2 SCL_V_SCALE_RATIO_C 0 25 mmSCLV1_SCLV_VERT_FILTER_INIT_C 0 0x13db 2 0 2 SCL_V_INIT_FRAC_C 0 23 SCL_V_INIT_INT_C 24 26 mmSCLV1_SCLV_VERT_FILTER_INIT_BOT_C 0 0x13dc 2 0 2 SCL_V_INIT_FRAC_BOT_C 0 23 SCL_V_INIT_INT_BOT_C 24 26 mmSCLV1_SCLV_ROUND_OFFSET 0 0x13dd 2 0 2 SCL_ROUND_OFFSET_RGB_Y 0 15 SCL_ROUND_OFFSET_CBCR 16 31 mmSCLV1_SCLV_UPDATE 0 0x13de 4 0 2 SCL_UPDATE_PENDING 0 0 SCL_UPDATE_TAKEN 8 8 SCL_UPDATE_LOCK 16 16 SCL_COEF_UPDATE_COMPLETE 24 24 mmSCLV1_SCLV_ALU_CONTROL 0 0x13df 1 0 2 SCL_ALU_DISABLE 0 0 mmSCLV1_SCLV_VIEWPORT_START 0 0x13e0 2 0 2 VIEWPORT_Y_START 0 13 VIEWPORT_X_START 16 29 mmSCLV1_SCLV_VIEWPORT_START_SECONDARY 0 0x13e1 2 0 2 VIEWPORT_Y_START_SECONDARY 0 13 VIEWPORT_X_START_SECONDARY 16 29 mmSCLV1_SCLV_VIEWPORT_SIZE 0 0x13e2 2 0 2 VIEWPORT_HEIGHT 0 12 VIEWPORT_WIDTH 16 28 mmSCLV1_SCLV_VIEWPORT_START_C 0 0x13e3 2 0 2 VIEWPORT_Y_START_C 0 13 VIEWPORT_X_START_C 16 29 mmSCLV1_SCLV_VIEWPORT_START_SECONDARY_C 0 0x13e4 2 0 2 VIEWPORT_Y_START_SECONDARY_C 0 13 VIEWPORT_X_START_SECONDARY_C 16 29 mmSCLV1_SCLV_VIEWPORT_SIZE_C 0 0x13e5 2 0 2 VIEWPORT_HEIGHT_C 0 12 VIEWPORT_WIDTH_C 16 28 mmSCLV1_SCLV_EXT_OVERSCAN_LEFT_RIGHT 0 0x13e6 2 0 2 EXT_OVERSCAN_RIGHT 0 12 EXT_OVERSCAN_LEFT 16 28 mmSCLV1_SCLV_EXT_OVERSCAN_TOP_BOTTOM 0 0x13e7 2 0 2 EXT_OVERSCAN_BOTTOM 0 12 EXT_OVERSCAN_TOP 16 28 mmSCLV1_SCLV_MODE_CHANGE_DET1 0 0x13e8 3 0 2 SCL_MODE_CHANGE 0 0 SCL_MODE_CHANGE_ACK 4 4 SCL_ALU_H_SCALE_RATIO 7 27 mmSCLV1_SCLV_MODE_CHANGE_DET2 0 0x13e9 1 0 2 SCL_ALU_V_SCALE_RATIO 0 20 mmSCLV1_SCLV_MODE_CHANGE_DET3 0 0x13ea 2 0 2 SCL_ALU_SOURCE_HEIGHT 0 13 SCL_ALU_SOURCE_WIDTH 16 29 mmSCLV1_SCLV_MODE_CHANGE_MASK 0 0x13eb 1 0 2 SCL_MODE_CHANGE_MASK 0 0 mmSCLV1_SCLV_HORZ_FILTER_INIT_BOT 0 0x13ec 2 0 2 SCL_H_INIT_FRAC_BOT 0 23 SCL_H_INIT_INT_BOT 24 27 mmSCLV1_SCLV_HORZ_FILTER_INIT_BOT_C 0 0x13ed 2 0 2 SCL_H_INIT_FRAC_BOT_C 0 23 SCL_H_INIT_INT_BOT_C 24 27 mmCOL_MAN1_COL_MAN_UPDATE 0 0x13fe 4 0 2 COL_MAN_UPDATE_PENDING 0 0 COL_MAN_UPDATE_TAKEN 1 1 COL_MAN_UPDATE_LOCK 16 16 COL_MAN_DISABLE_MULTIPLE_UPDATE 24 24 mmCOL_MAN1_COL_MAN_INPUT_CSC_CONTROL 0 0x13ff 3 0 2 INPUT_CSC_MODE 0 1 INPUT_CSC_INPUT_TYPE 8 9 INPUT_CSC_CONVERSION_MODE 16 16 mmCOL_MAN1_INPUT_CSC_C11_C12_A 0 0x1400 2 0 2 INPUT_CSC_C11_A 0 15 INPUT_CSC_C12_A 16 31 mmCOL_MAN1_INPUT_CSC_C13_C14_A 0 0x1401 2 0 2 INPUT_CSC_C13_A 0 15 INPUT_CSC_C14_A 16 31 mmCOL_MAN1_INPUT_CSC_C21_C22_A 0 0x1402 2 0 2 INPUT_CSC_C21_A 0 15 INPUT_CSC_C22_A 16 31 mmCOL_MAN1_INPUT_CSC_C23_C24_A 0 0x1403 2 0 2 INPUT_CSC_C23_A 0 15 INPUT_CSC_C24_A 16 31 mmCOL_MAN1_INPUT_CSC_C31_C32_A 0 0x1404 2 0 2 INPUT_CSC_C31_A 0 15 INPUT_CSC_C32_A 16 31 mmCOL_MAN1_INPUT_CSC_C33_C34_A 0 0x1405 2 0 2 INPUT_CSC_C33_A 0 15 INPUT_CSC_C34_A 16 31 mmCOL_MAN1_INPUT_CSC_C11_C12_B 0 0x1406 2 0 2 INPUT_CSC_C11_B 0 15 INPUT_CSC_C12_B 16 31 mmCOL_MAN1_INPUT_CSC_C13_C14_B 0 0x1407 2 0 2 INPUT_CSC_C13_B 0 15 INPUT_CSC_C14_B 16 31 mmCOL_MAN1_INPUT_CSC_C21_C22_B 0 0x1408 2 0 2 INPUT_CSC_C21_B 0 15 INPUT_CSC_C22_B 16 31 mmCOL_MAN1_INPUT_CSC_C23_C24_B 0 0x1409 2 0 2 INPUT_CSC_C23_B 0 15 INPUT_CSC_C24_B 16 31 mmCOL_MAN1_INPUT_CSC_C31_C32_B 0 0x140a 2 0 2 INPUT_CSC_C31_B 0 15 INPUT_CSC_C32_B 16 31 mmCOL_MAN1_INPUT_CSC_C33_C34_B 0 0x140b 2 0 2 INPUT_CSC_C33_B 0 15 INPUT_CSC_C34_B 16 31 mmCOL_MAN1_PRESCALE_CONTROL 0 0x140c 1 0 2 PRESCALE_MODE 0 1 mmCOL_MAN1_PRESCALE_VALUES_R 0 0x140d 2 0 2 PRESCALE_BIAS_R 0 15 PRESCALE_SCALE_R 16 31 mmCOL_MAN1_PRESCALE_VALUES_G 0 0x140e 2 0 2 PRESCALE_BIAS_G 0 15 PRESCALE_SCALE_G 16 31 mmCOL_MAN1_PRESCALE_VALUES_B 0 0x140f 2 0 2 PRESCALE_BIAS_B 0 15 PRESCALE_SCALE_B 16 31 mmCOL_MAN1_COL_MAN_OUTPUT_CSC_CONTROL 0 0x1410 1 0 2 OUTPUT_CSC_MODE 0 2 mmCOL_MAN1_OUTPUT_CSC_C11_C12_A 0 0x1411 2 0 2 OUTPUT_CSC_C11_A 0 15 OUTPUT_CSC_C12_A 16 31 mmCOL_MAN1_OUTPUT_CSC_C13_C14_A 0 0x1412 2 0 2 OUTPUT_CSC_C13_A 0 15 OUTPUT_CSC_C14_A 16 31 mmCOL_MAN1_OUTPUT_CSC_C21_C22_A 0 0x1413 2 0 2 OUTPUT_CSC_C21_A 0 15 OUTPUT_CSC_C22_A 16 31 mmCOL_MAN1_OUTPUT_CSC_C23_C24_A 0 0x1414 2 0 2 OUTPUT_CSC_C23_A 0 15 OUTPUT_CSC_C24_A 16 31 mmCOL_MAN1_OUTPUT_CSC_C31_C32_A 0 0x1415 2 0 2 OUTPUT_CSC_C31_A 0 15 OUTPUT_CSC_C32_A 16 31 mmCOL_MAN1_OUTPUT_CSC_C33_C34_A 0 0x1416 2 0 2 OUTPUT_CSC_C33_A 0 15 OUTPUT_CSC_C34_A 16 31 mmCOL_MAN1_OUTPUT_CSC_C11_C12_B 0 0x1417 2 0 2 OUTPUT_CSC_C11_B 0 15 OUTPUT_CSC_C12_B 16 31 mmCOL_MAN1_OUTPUT_CSC_C13_C14_B 0 0x1418 2 0 2 OUTPUT_CSC_C13_B 0 15 OUTPUT_CSC_C14_B 16 31 mmCOL_MAN1_OUTPUT_CSC_C21_C22_B 0 0x1419 2 0 2 OUTPUT_CSC_C21_B 0 15 OUTPUT_CSC_C22_B 16 31 mmCOL_MAN1_OUTPUT_CSC_C23_C24_B 0 0x141a 2 0 2 OUTPUT_CSC_C23_B 0 15 OUTPUT_CSC_C24_B 16 31 mmCOL_MAN1_OUTPUT_CSC_C31_C32_B 0 0x141b 2 0 2 OUTPUT_CSC_C31_B 0 15 OUTPUT_CSC_C32_B 16 31 mmCOL_MAN1_OUTPUT_CSC_C33_C34_B 0 0x141c 2 0 2 OUTPUT_CSC_C33_B 0 15 OUTPUT_CSC_C34_B 16 31 mmCOL_MAN1_DENORM_CLAMP_CONTROL 0 0x141d 2 0 2 DENORM_MODE 0 1 DENORM_10BIT_OUT 8 8 mmCOL_MAN1_DENORM_CLAMP_RANGE_R_CR 0 0x141e 2 0 2 RANGE_CLAMP_MAX_R_CR 0 11 RANGE_CLAMP_MIN_R_CR 12 23 mmCOL_MAN1_DENORM_CLAMP_RANGE_G_Y 0 0x141f 2 0 2 RANGE_CLAMP_MAX_G_Y 0 11 RANGE_CLAMP_MIN_G_Y 12 23 mmCOL_MAN1_DENORM_CLAMP_RANGE_B_CB 0 0x1420 2 0 2 RANGE_CLAMP_MAX_B_CB 0 11 RANGE_CLAMP_MIN_B_CB 12 23 mmCOL_MAN1_COL_MAN_FP_CONVERTED_FIELD 0 0x1421 2 0 2 COL_MAN_FP_CONVERTED_FIELD_DATA 0 17 COL_MAN_FP_CONVERTED_FIELD_INDEX 20 26 mmCOL_MAN1_COL_MAN_REGAMMA_CONTROL 0 0x1422 1 0 2 COL_MAN_REGAMMA_MODE 0 2 mmCOL_MAN1_COL_MAN_REGAMMA_LUT_INDEX 0 0x1423 1 0 2 COL_MAN_REGAMMA_LUT_INDEX 0 8 mmCOL_MAN1_COL_MAN_REGAMMA_LUT_DATA 0 0x1424 1 0 2 COL_MAN_REGAMMA_LUT_DATA 0 18 mmCOL_MAN1_COL_MAN_REGAMMA_LUT_WRITE_EN_MASK 0 0x1425 1 0 2 COL_MAN_REGAMMA_LUT_WRITE_EN_MASK 0 2 mmCOL_MAN1_COL_MAN_REGAMMA_CNTLA_START_CNTL 0 0x1426 2 0 2 COL_MAN_REGAMMA_CNTLA_EXP_REGION_START 0 17 COL_MAN_REGAMMA_CNTLA_EXP_REGION_START_SEGMENT 20 26 mmCOL_MAN1_COL_MAN_REGAMMA_CNTLA_SLOPE_CNTL 0 0x1427 1 0 2 COL_MAN_REGAMMA_CNTLA_EXP_REGION_LINEAR_SLOPE 0 17 mmCOL_MAN1_COL_MAN_REGAMMA_CNTLA_END_CNTL1 0 0x1428 1 0 2 COL_MAN_REGAMMA_CNTLA_EXP_REGION_END 0 15 mmCOL_MAN1_COL_MAN_REGAMMA_CNTLA_END_CNTL2 0 0x1429 2 0 2 COL_MAN_REGAMMA_CNTLA_EXP_REGION_END_SLOPE 0 15 COL_MAN_REGAMMA_CNTLA_EXP_REGION_END_BASE 16 31 mmCOL_MAN1_COL_MAN_REGAMMA_CNTLA_REGION_0_1 0 0x142a 4 0 2 COL_MAN_REGAMMA_CNTLA_EXP_REGION0_LUT_OFFSET 0 8 COL_MAN_REGAMMA_CNTLA_EXP_REGION0_NUM_SEGMENTS 11 13 COL_MAN_REGAMMA_CNTLA_EXP_REGION1_LUT_OFFSET 15 23 COL_MAN_REGAMMA_CNTLA_EXP_REGION1_NUM_SEGMENTS 27 29 mmCOL_MAN1_COL_MAN_REGAMMA_CNTLA_REGION_2_3 0 0x142b 4 0 2 COL_MAN_REGAMMA_CNTLA_EXP_REGION2_LUT_OFFSET 0 8 COL_MAN_REGAMMA_CNTLA_EXP_REGION2_NUM_SEGMENTS 11 13 COL_MAN_REGAMMA_CNTLA_EXP_REGION3_LUT_OFFSET 15 23 COL_MAN_REGAMMA_CNTLA_EXP_REGION3_NUM_SEGMENTS 27 29 mmCOL_MAN1_COL_MAN_REGAMMA_CNTLA_REGION_4_5 0 0x142c 4 0 2 COL_MAN_REGAMMA_CNTLA_EXP_REGION4_LUT_OFFSET 0 8 COL_MAN_REGAMMA_CNTLA_EXP_REGION4_NUM_SEGMENTS 11 13 COL_MAN_REGAMMA_CNTLA_EXP_REGION5_LUT_OFFSET 15 23 COL_MAN_REGAMMA_CNTLA_EXP_REGION5_NUM_SEGMENTS 27 29 mmCOL_MAN1_COL_MAN_REGAMMA_CNTLA_REGION_6_7 0 0x142d 4 0 2 COL_MAN_REGAMMA_CNTLA_EXP_REGION6_LUT_OFFSET 0 8 COL_MAN_REGAMMA_CNTLA_EXP_REGION6_NUM_SEGMENTS 11 13 COL_MAN_REGAMMA_CNTLA_EXP_REGION7_LUT_OFFSET 15 23 COL_MAN_REGAMMA_CNTLA_EXP_REGION7_NUM_SEGMENTS 27 29 mmCOL_MAN1_COL_MAN_REGAMMA_CNTLA_REGION_8_9 0 0x142e 4 0 2 COL_MAN_REGAMMA_CNTLA_EXP_REGION8_LUT_OFFSET 0 8 COL_MAN_REGAMMA_CNTLA_EXP_REGION8_NUM_SEGMENTS 11 13 COL_MAN_REGAMMA_CNTLA_EXP_REGION9_LUT_OFFSET 15 23 COL_MAN_REGAMMA_CNTLA_EXP_REGION9_NUM_SEGMENTS 27 29 mmCOL_MAN1_COL_MAN_REGAMMA_CNTLA_REGION_10_11 0 0x142f 4 0 2 COL_MAN_REGAMMA_CNTLA_EXP_REGION10_LUT_OFFSET 0 8 COL_MAN_REGAMMA_CNTLA_EXP_REGION10_NUM_SEGMENTS 11 13 COL_MAN_REGAMMA_CNTLA_EXP_REGION11_LUT_OFFSET 15 23 COL_MAN_REGAMMA_CNTLA_EXP_REGION11_NUM_SEGMENTS 27 29 mmCOL_MAN1_COL_MAN_REGAMMA_CNTLA_REGION_12_13 0 0x1430 4 0 2 COL_MAN_REGAMMA_CNTLA_EXP_REGION12_LUT_OFFSET 0 8 COL_MAN_REGAMMA_CNTLA_EXP_REGION12_NUM_SEGMENTS 11 13 COL_MAN_REGAMMA_CNTLA_EXP_REGION13_LUT_OFFSET 15 23 COL_MAN_REGAMMA_CNTLA_EXP_REGION13_NUM_SEGMENTS 27 29 mmCOL_MAN1_COL_MAN_REGAMMA_CNTLA_REGION_14_15 0 0x1431 4 0 2 COL_MAN_REGAMMA_CNTLA_EXP_REGION14_LUT_OFFSET 0 8 COL_MAN_REGAMMA_CNTLA_EXP_REGION14_NUM_SEGMENTS 11 13 COL_MAN_REGAMMA_CNTLA_EXP_REGION15_LUT_OFFSET 15 23 COL_MAN_REGAMMA_CNTLA_EXP_REGION15_NUM_SEGMENTS 27 29 mmCOL_MAN1_COL_MAN_REGAMMA_CNTLB_START_CNTL 0 0x1432 2 0 2 COL_MAN_REGAMMA_CNTLB_EXP_REGION_START 0 17 COL_MAN_REGAMMA_CNTLB_EXP_REGION_START_SEGMENT 20 26 mmCOL_MAN1_COL_MAN_REGAMMA_CNTLB_SLOPE_CNTL 0 0x1433 1 0 2 COL_MAN_REGAMMA_CNTLB_EXP_REGION_LINEAR_SLOPE 0 17 mmCOL_MAN1_COL_MAN_REGAMMA_CNTLB_END_CNTL1 0 0x1434 1 0 2 COL_MAN_REGAMMA_CNTLB_EXP_REGION_END 0 15 mmCOL_MAN1_COL_MAN_REGAMMA_CNTLB_END_CNTL2 0 0x1435 2 0 2 COL_MAN_REGAMMA_CNTLB_EXP_REGION_END_SLOPE 0 15 COL_MAN_REGAMMA_CNTLB_EXP_REGION_END_BASE 16 31 mmCOL_MAN1_COL_MAN_REGAMMA_CNTLB_REGION_0_1 0 0x1436 4 0 2 COL_MAN_REGAMMA_CNTLB_EXP_REGION0_LUT_OFFSET 0 8 COL_MAN_REGAMMA_CNTLB_EXP_REGION0_NUM_SEGMENTS 11 13 COL_MAN_REGAMMA_CNTLB_EXP_REGION1_LUT_OFFSET 15 23 COL_MAN_REGAMMA_CNTLB_EXP_REGION1_NUM_SEGMENTS 27 29 mmCOL_MAN1_COL_MAN_REGAMMA_CNTLB_REGION_2_3 0 0x1437 4 0 2 COL_MAN_REGAMMA_CNTLB_EXP_REGION2_LUT_OFFSET 0 8 COL_MAN_REGAMMA_CNTLB_EXP_REGION2_NUM_SEGMENTS 11 13 COL_MAN_REGAMMA_CNTLB_EXP_REGION3_LUT_OFFSET 15 23 COL_MAN_REGAMMA_CNTLB_EXP_REGION3_NUM_SEGMENTS 27 29 mmCOL_MAN1_COL_MAN_REGAMMA_CNTLB_REGION_4_5 0 0x1438 4 0 2 COL_MAN_REGAMMA_CNTLB_EXP_REGION4_LUT_OFFSET 0 8 COL_MAN_REGAMMA_CNTLB_EXP_REGION4_NUM_SEGMENTS 11 13 COL_MAN_REGAMMA_CNTLB_EXP_REGION5_LUT_OFFSET 15 23 COL_MAN_REGAMMA_CNTLB_EXP_REGION5_NUM_SEGMENTS 27 29 mmCOL_MAN1_COL_MAN_REGAMMA_CNTLB_REGION_6_7 0 0x1439 4 0 2 COL_MAN_REGAMMA_CNTLB_EXP_REGION6_LUT_OFFSET 0 8 COL_MAN_REGAMMA_CNTLB_EXP_REGION6_NUM_SEGMENTS 11 13 COL_MAN_REGAMMA_CNTLB_EXP_REGION7_LUT_OFFSET 15 23 COL_MAN_REGAMMA_CNTLB_EXP_REGION7_NUM_SEGMENTS 27 29 mmCOL_MAN1_COL_MAN_REGAMMA_CNTLB_REGION_8_9 0 0x143a 4 0 2 COL_MAN_REGAMMA_CNTLB_EXP_REGION8_LUT_OFFSET 0 8 COL_MAN_REGAMMA_CNTLB_EXP_REGION8_NUM_SEGMENTS 11 13 COL_MAN_REGAMMA_CNTLB_EXP_REGION9_LUT_OFFSET 15 23 COL_MAN_REGAMMA_CNTLB_EXP_REGION9_NUM_SEGMENTS 27 29 mmCOL_MAN1_COL_MAN_REGAMMA_CNTLB_REGION_10_11 0 0x143b 4 0 2 COL_MAN_REGAMMA_CNTLB_EXP_REGION10_LUT_OFFSET 0 8 COL_MAN_REGAMMA_CNTLB_EXP_REGION10_NUM_SEGMENTS 11 13 COL_MAN_REGAMMA_CNTLB_EXP_REGION11_LUT_OFFSET 15 23 COL_MAN_REGAMMA_CNTLB_EXP_REGION11_NUM_SEGMENTS 27 29 mmCOL_MAN1_COL_MAN_REGAMMA_CNTLB_REGION_12_13 0 0x143c 4 0 2 COL_MAN_REGAMMA_CNTLB_EXP_REGION12_LUT_OFFSET 0 8 COL_MAN_REGAMMA_CNTLB_EXP_REGION12_NUM_SEGMENTS 11 13 COL_MAN_REGAMMA_CNTLB_EXP_REGION13_LUT_OFFSET 15 23 COL_MAN_REGAMMA_CNTLB_EXP_REGION13_NUM_SEGMENTS 27 29 mmCOL_MAN1_COL_MAN_REGAMMA_CNTLB_REGION_14_15 0 0x143d 4 0 2 COL_MAN_REGAMMA_CNTLB_EXP_REGION14_LUT_OFFSET 0 8 COL_MAN_REGAMMA_CNTLB_EXP_REGION14_NUM_SEGMENTS 11 13 COL_MAN_REGAMMA_CNTLB_EXP_REGION15_LUT_OFFSET 15 23 COL_MAN_REGAMMA_CNTLB_EXP_REGION15_NUM_SEGMENTS 27 29 mmCOL_MAN1_PACK_FIFO_ERROR 0 0x143e 8 0 2 PACK_FIFO_L_UNDERFLOW_OCCURED 0 0 PACK_FIFO_L_UNDERFLOW_ACK 1 1 PACK_FIFO_C_UNDERFLOW_OCCURED 8 8 PACK_FIFO_C_UNDERFLOW_ACK 9 9 PACK_FIFO_L_OVERFLOW_OCCURED 16 16 PACK_FIFO_L_OVERFLOW_ACK 17 17 PACK_FIFO_C_OVERFLOW_OCCURED 24 24 PACK_FIFO_C_OVERFLOW_ACK 25 25 mmCOL_MAN1_OUTPUT_FIFO_ERROR 0 0x143f 4 0 2 OUTPUT_FIFO_UNDERFLOW_OCCURED 0 0 OUTPUT_FIFO_UNDERFLOW_ACK 1 1 OUTPUT_FIFO_OVERFLOW_OCCURED 8 8 OUTPUT_FIFO_OVERFLOW_ACK 9 9 mmCOL_MAN1_INPUT_GAMMA_LUT_AUTOFILL 0 0x1440 2 0 2 INPUT_GAMMA_LUT_AUTOFILL 0 0 INPUT_GAMMA_LUT_AUTOFILL_DONE 1 1 mmCOL_MAN1_INPUT_GAMMA_LUT_RW_INDEX 0 0x1441 1 0 2 INPUT_GAMMA_LUT_RW_INDEX 0 7 mmCOL_MAN1_INPUT_GAMMA_LUT_SEQ_COLOR 0 0x1442 1 0 2 INPUT_GAMMA_LUT_SEQ_COLOR 0 15 mmCOL_MAN1_INPUT_GAMMA_LUT_PWL_DATA 0 0x1443 2 0 2 INPUT_GAMMA_LUT_BASE 0 15 INPUT_GAMMA_LUT_DELTA 16 31 mmCOL_MAN1_INPUT_GAMMA_LUT_30_COLOR 0 0x1444 3 0 2 INPUT_GAMMA_LUT_COLOR_10_BLUE 0 9 INPUT_GAMMA_LUT_COLOR_10_GREEN 10 19 INPUT_GAMMA_LUT_COLOR_10_RED 20 29 mmCOL_MAN1_COL_MAN_INPUT_GAMMA_CONTROL1 0 0x1445 2 0 2 INPUT_GAMMA_MODE 0 1 INPUT_GAMMA_LUT_10BIT_BYPASS_EN 26 26 mmCOL_MAN1_COL_MAN_INPUT_GAMMA_CONTROL2 0 0x1446 13 0 2 INPUT_GAMMA_INC_B 1 4 INPUT_GAMMA_DATA_B_SIGNED_EN 5 5 INPUT_GAMMA_DATA_B_FORMAT 6 7 INPUT_GAMMA_INC_G 8 11 INPUT_GAMMA_DATA_G_SIGNED_EN 12 12 INPUT_GAMMA_DATA_G_FORMAT 13 14 INPUT_GAMMA_INC_R 15 18 INPUT_GAMMA_DATA_R_SIGNED_EN 19 19 INPUT_GAMMA_DATA_R_FORMAT 20 21 INPUT_GAMMA_LUT_RW_MODE 22 22 INPUT_GAMMA_LUT_WRITE_EN_MASK 23 25 INPUT_GAMMA_LUT_VGA_ACCESS_ENABLE 26 26 INPUT_GAMMA_LUT_10BIT_BYPASS_DBL_BUF_EN 27 27 mmCOL_MAN1_INPUT_GAMMA_BW_OFFSETS_B 0 0x1447 2 0 2 INPUT_GAMMA_BLACK_OFFSET_B 0 15 INPUT_GAMMA_WHITE_OFFSET_B 16 31 mmCOL_MAN1_INPUT_GAMMA_BW_OFFSETS_G 0 0x1448 2 0 2 INPUT_GAMMA_BLACK_OFFSET_G 0 15 INPUT_GAMMA_WHITE_OFFSET_G 16 31 mmCOL_MAN1_INPUT_GAMMA_BW_OFFSETS_R 0 0x1449 2 0 2 INPUT_GAMMA_BLACK_OFFSET_R 0 15 INPUT_GAMMA_WHITE_OFFSET_R 16 31 mmCOL_MAN1_COL_MAN_DEGAMMA_CONTROL 0 0x144a 1 0 2 COL_MAN_DEGAMMA_MODE 0 1 mmCOL_MAN1_COL_MAN_GAMUT_REMAP_CONTROL 0 0x144b 1 0 2 COL_MAN_GAMUT_REMAP_MODE 0 1 mmCOL_MAN1_COL_MAN_GAMUT_REMAP_C11_C12 0 0x144c 2 0 2 COL_MAN_GAMUT_REMAP_C11 0 15 COL_MAN_GAMUT_REMAP_C12 16 31 mmCOL_MAN1_COL_MAN_GAMUT_REMAP_C13_C14 0 0x144d 2 0 2 COL_MAN_GAMUT_REMAP_C13 0 15 COL_MAN_GAMUT_REMAP_C14 16 31 mmCOL_MAN1_COL_MAN_GAMUT_REMAP_C21_C22 0 0x144e 2 0 2 COL_MAN_GAMUT_REMAP_C21 0 15 COL_MAN_GAMUT_REMAP_C22 16 31 mmCOL_MAN1_COL_MAN_GAMUT_REMAP_C23_C24 0 0x144f 2 0 2 COL_MAN_GAMUT_REMAP_C23 0 15 COL_MAN_GAMUT_REMAP_C24 16 31 mmCOL_MAN1_COL_MAN_GAMUT_REMAP_C31_C32 0 0x1450 2 0 2 COL_MAN_GAMUT_REMAP_C31 0 15 COL_MAN_GAMUT_REMAP_C32 16 31 mmCOL_MAN1_COL_MAN_GAMUT_REMAP_C33_C34 0 0x1451 2 0 2 COL_MAN_GAMUT_REMAP_C33 0 15 COL_MAN_GAMUT_REMAP_C34 16 31 mmDCFEV1_DCFEV_CLOCK_CONTROL 0 0x147e 8 0 2 DISPCLK_R_DCFEV_GATE_DISABLE 3 3 DISPCLK_G_UNP_GATE_DISABLE 7 7 DISPCLK_G_SCLV_GATE_DISABLE 9 9 DISPCLK_G_COL_MAN_GATE_DISABLE 11 11 DISPCLK_G_PSCLV_GATE_DISABLE 13 13 DISPCLK_G_CRTC_GATE_DISABLE 15 15 DCFEV_TEST_CLK_SEL 24 28 DCFEV_CLOCK_ENABLE 31 31 mmDCFEV1_DCFEV_SOFT_RESET 0 0x147f 7 0 2 UNP_PIXPIPE_SOFT_RESET 0 0 UNP_REQ_SOFT_RESET 1 1 SCLV_ALU_SOFT_RESET 2 2 SCLV_SOFT_RESET 3 3 CRTC_SOFT_RESET 4 4 PSCLV_SOFT_RESET 5 5 COL_MAN_SOFT_RESET 6 6 mmDCFEV1_DCFEV_DMIFV_CLOCK_CONTROL 0 0x1480 6 0 2 DMIFV_SCLK_G_DMIFTRK_GATE_DIS 3 3 DMIFV_DISPCLK_G_DMIFVL_GATE_DIS 4 4 DMIFV_DISPCLK_G_DMIFVC_GATE_DIS 5 5 DMIFV_SOFT_RESET 6 6 DMIFV_TEST_CLK_SEL 24 28 DMIFV_BUFFER_MODE 31 31 mmDCFEV1_DCFEV_DMIFV_MEM_PWR_CTRL 0 0x1482 11 0 2 DMIFV_MEM_PWR_SEL 0 1 DMIFV_MEM_PWR_LUMA_0_FORCE 2 2 DMIFV_MEM_PWR_LUMA_1_FORCE 3 3 DMIFV_MEM_PWR_LUMA_2_FORCE 4 4 DMIFV_MEM_PWR_LUMA_3_FORCE 5 5 DMIFV_MEM_PWR_LUMA_4_FORCE 6 6 DMIFV_MEM_PWR_CHROMA_0_FORCE 7 7 DMIFV_MEM_PWR_CHROMA_1_FORCE 8 8 DMIFV_MEM_PWR_CHROMA_2_FORCE 9 9 DMIFV_MEM_PWR_CHROMA_3_FORCE 10 10 DMIFV_MEM_PWR_CHROMA_4_FORCE 11 11 mmDCFEV1_DCFEV_DMIFV_MEM_PWR_STATUS 0 0x1483 10 0 2 DMIFV_MEM_PWR_LUMA_0_STATE 0 1 DMIFV_MEM_PWR_LUMA_1_STATE 2 3 DMIFV_MEM_PWR_LUMA_2_STATE 4 5 DMIFV_MEM_PWR_LUMA_3_STATE 6 7 DMIFV_MEM_PWR_LUMA_4_STATE 8 9 DMIFV_MEM_PWR_CHROMA_0_STATE 10 11 DMIFV_MEM_PWR_CHROMA_1_STATE 12 13 DMIFV_MEM_PWR_CHROMA_2_STATE 14 15 DMIFV_MEM_PWR_CHROMA_3_STATE 16 17 DMIFV_MEM_PWR_CHROMA_4_STATE 18 19 mmDCFEV1_DCFEV_MEM_PWR_CTRL 0 0x1484 12 0 2 COL_MAN_REGAMMA_MEM_PWR_FORCE 0 1 COL_MAN_REGAMMA_MEM_PWR_DIS 2 2 COL_MAN_INPUT_GAMMA_MEM_PWR_FORCE 3 4 COL_MAN_INPUT_GAMMA_MEM_PWR_DIS 5 5 SCLV_COEFF_MEM_PWR_FORCE 6 7 SCLV_COEFF_MEM_PWR_DIS 8 8 LBV0_MEM_PWR_FORCE 9 10 LBV0_MEM_PWR_DIS 11 11 LBV1_MEM_PWR_FORCE 12 13 LBV1_MEM_PWR_DIS 14 14 LBV2_MEM_PWR_FORCE 15 16 LBV2_MEM_PWR_DIS 17 17 mmDCFEV1_DCFEV_MEM_PWR_CTRL2 0 0x1485 4 0 2 COL_MAN_REGAMMA_MEM_PWR_MODE_SEL 0 1 COL_MAN_INPUT_GAMMA_MEM_PWR_MODE_SEL 2 3 SCLV_COEFF_MEM_PWR_MODE_SEL 4 5 LBV_MEM_PWR_MODE_SEL 6 7 mmDCFEV1_DCFEV_MEM_PWR_STATUS 0 0x1486 7 0 2 COL_MAN_REGAMMA_MEM_PWR_STATE 0 1 COL_MAN_INPUT_GAMMA_MEM_PWR_STATE 2 3 SCLV_COEFF_MEM_PWR_STATE 4 5 LBV0_MEM_PWR_STATE 6 7 LBV1_MEM_PWR_STATE 8 9 LBV2_MEM_PWR_STATE 10 11 LBV3_MEM_PWR_STATE 12 13 mmDCFEV1_DCFEV_L_FLUSH 0 0x1487 5 0 2 FLUSH_OCCURED 0 0 CLEAR_FLUSH_OCCURED 1 1 FLUSH_DEEP 2 2 CLEAR_FLUSH_DEEP 3 3 ALL_MC_REQ_RET 4 4 mmDCFEV1_DCFEV_C_FLUSH 0 0x1488 5 0 2 FLUSH_OCCURED 0 0 CLEAR_FLUSH_OCCURED 1 1 FLUSH_DEEP 2 2 CLEAR_FLUSH_DEEP 3 3 ALL_MC_REQ_RET 4 4 mmDCFEV1_DCFEV_MISC 0 0x148a 1 0 2 DCFEV_DPG_ALLOW_SR_ECO_EN 0 0 mmDC_PERFMON12_PERFCOUNTER_CNTL 0 0x1492 13 0 2 PERFCOUNTER_EVENT_SEL 0 8 PERFCOUNTER_CVALUE_SEL 9 11 PERFCOUNTER_INC_MODE 12 14 PERFCOUNTER_HW_CNTL_SEL 15 15 PERFCOUNTER_RUNEN_MODE 16 16 PERFCOUNTER_CNTOFF_SEL 17 21 PERFCOUNTER_CNTOFF_START_DIS 22 22 PERFCOUNTER_RESTART_EN 23 23 PERFCOUNTER_INT_EN 24 24 PERFCOUNTER_OFF_MASK 25 25 PERFCOUNTER_ACTIVE 26 26 PERFCOUNTER_INT_TYPE 27 27 PERFCOUNTER_CNTL_SEL 29 31 mmDC_PERFMON12_PERFCOUNTER_CNTL2 0 0x1493 4 0 2 PERFCOUNTER_COUNTED_VALUE_TYPE 0 1 PERFCOUNTER_HW_STOP1_SEL 2 2 PERFCOUNTER_HW_STOP2_SEL 3 3 PERFCOUNTER_CNTL2_SEL 29 31 mmDC_PERFMON12_PERFCOUNTER_STATE 0 0x1494 16 0 2 PERFCOUNTER_CNT0_STATE 0 1 PERFCOUNTER_STATE_SEL0 2 2 PERFCOUNTER_CNT1_STATE 4 5 PERFCOUNTER_STATE_SEL1 6 6 PERFCOUNTER_CNT2_STATE 8 9 PERFCOUNTER_STATE_SEL2 10 10 PERFCOUNTER_CNT3_STATE 12 13 PERFCOUNTER_STATE_SEL3 14 14 PERFCOUNTER_CNT4_STATE 16 17 PERFCOUNTER_STATE_SEL4 18 18 PERFCOUNTER_CNT5_STATE 20 21 PERFCOUNTER_STATE_SEL5 22 22 PERFCOUNTER_CNT6_STATE 24 25 PERFCOUNTER_STATE_SEL6 26 26 PERFCOUNTER_CNT7_STATE 28 29 PERFCOUNTER_STATE_SEL7 30 30 mmDC_PERFMON12_PERFMON_CNTL 0 0x1495 6 0 2 PERFMON_STATE 0 1 PERFMON_RPT_COUNT 8 27 PERFMON_CNTOFF_AND_OR 28 28 PERFMON_CNTOFF_INT_EN 29 29 PERFMON_CNTOFF_INT_STATUS 30 30 PERFMON_CNTOFF_INT_ACK 31 31 mmDC_PERFMON12_PERFMON_CNTL2 0 0x1496 4 0 2 PERFMON_CNTOFF_INT_TYPE 0 0 PERFMON_CLK_ENABLE 1 1 PERFMON_RUN_ENABLE_START_SEL 2 9 PERFMON_RUN_ENABLE_STOP_SEL 10 17 mmDC_PERFMON12_PERFMON_CVALUE_INT_MISC 0 0x1497 17 0 2 PERFCOUNTER_INT0_STATUS 0 0 PERFCOUNTER_INT1_STATUS 1 1 PERFCOUNTER_INT2_STATUS 2 2 PERFCOUNTER_INT3_STATUS 3 3 PERFCOUNTER_INT4_STATUS 4 4 PERFCOUNTER_INT5_STATUS 5 5 PERFCOUNTER_INT6_STATUS 6 6 PERFCOUNTER_INT7_STATUS 7 7 PERFCOUNTER_INT0_ACK 8 8 PERFCOUNTER_INT1_ACK 9 9 PERFCOUNTER_INT2_ACK 10 10 PERFCOUNTER_INT3_ACK 11 11 PERFCOUNTER_INT4_ACK 12 12 PERFCOUNTER_INT5_ACK 13 13 PERFCOUNTER_INT6_ACK 14 14 PERFCOUNTER_INT7_ACK 15 15 PERFMON_CVALUE_HI 16 31 mmDC_PERFMON12_PERFMON_CVALUE_LOW 0 0x1498 1 0 2 PERFMON_CVALUE_LOW 0 31 mmDC_PERFMON12_PERFMON_HI 0 0x1499 2 0 2 PERFMON_HI 0 15 PERFMON_READ_SEL 29 31 mmDC_PERFMON12_PERFMON_LOW 0 0x149a 1 0 2 PERFMON_LOW 0 31 mmDMIFV_PG1_DPGV0_PIPE_ARBITRATION_CONTROL1 0 0x149e 2 0 2 PIXEL_DURATION 0 15 BASE_WEIGHT 16 31 mmDMIFV_PG1_DPGV0_PIPE_ARBITRATION_CONTROL2 0 0x149f 2 0 2 TIME_WEIGHT 0 15 URGENCY_WEIGHT 16 31 mmDMIFV_PG1_DPGV0_WATERMARK_MASK_CONTROL 0 0x14a0 4 0 2 STUTTER_EXIT_SELF_REFRESH_WATERMARK_MASK 0 1 URGENCY_WATERMARK_MASK 8 9 NB_PSTATE_CHANGE_WATERMARK_MASK 16 17 DISABLE_FLIP_URGENT 24 24 mmDMIFV_PG1_DPGV0_PIPE_URGENCY_CONTROL 0 0x14a1 2 0 2 URGENCY_LOW_WATERMARK 0 15 URGENCY_HIGH_WATERMARK 16 31 mmDMIFV_PG1_DPGV0_PIPE_DPM_CONTROL 0 0x14a2 1 0 2 DPM_ENABLE 0 0 mmDMIFV_PG1_DPGV0_PIPE_STUTTER_CONTROL 0 0x14a3 10 0 2 STUTTER_ENABLE 0 0 STUTTER_IGNORE_CURSOR 4 4 STUTTER_IGNORE_ICON 5 5 STUTTER_IGNORE_VGA 6 6 STUTTER_IGNORE_FBC 7 7 STUTTER_WM_HIGH_FORCE_ON 8 8 STUTTER_WM_HIGH_EXCLUDES_VBLANK 9 9 STUTTER_URGENT_IN_NOT_SELF_REFRESH 10 10 STUTTER_SELF_REFRESH_FORCE_ON 11 11 STUTTER_EXIT_SELF_REFRESH_WATERMARK 16 31 mmDMIFV_PG1_DPGV0_PIPE_NB_PSTATE_CHANGE_CONTROL 0 0x14a4 6 0 2 NB_PSTATE_CHANGE_ENABLE 0 0 NB_PSTATE_CHANGE_URGENT_DURING_REQUEST 4 4 NB_PSTATE_CHANGE_NOT_SELF_REFRESH_DURING_REQUEST 8 8 NB_PSTATE_CHANGE_FORCE_ON 9 9 NB_PSTATE_ALLOW_FOR_URGENT 10 10 NB_PSTATE_CHANGE_WATERMARK 16 31 mmDMIFV_PG1_DPGV0_PIPE_STUTTER_CONTROL_NONLPTCH 0 0x14a5 9 0 2 STUTTER_ENABLE_NONLPTCH 0 0 STUTTER_IGNORE_CURSOR_NONLPTCH 4 4 STUTTER_IGNORE_ICON_NONLPTCH 5 5 STUTTER_IGNORE_VGA_NONLPTCH 6 6 STUTTER_IGNORE_FBC_NONLPTCH 7 7 STUTTER_WM_HIGH_FORCE_ON_NONLPTCH 8 8 STUTTER_WM_HIGH_EXCLUDES_VBLANK_NONLPTCH 9 9 STUTTER_URGENT_IN_NOT_SELF_REFRESH_NONLPTCH 10 10 STUTTER_SELF_REFRESH_FORCE_ON_NONLPTCH 11 11 mmDMIFV_PG1_DPGV0_REPEATER_PROGRAM 0 0x14a6 2 0 2 REG_DPG_DMIFRC_REPEATER 0 2 REG_DMIFRC_DPG_REPEATER 4 6 mmDMIFV_PG1_DPGV0_CHK_PRE_PROC_CNTL 0 0x14aa 1 0 2 DPG_DISABLE_DMIF_BUF_CHK 0 0 mmDMIFV_PG1_DPGV1_PIPE_ARBITRATION_CONTROL1 0 0x14ab 2 0 2 PIXEL_DURATION 0 15 BASE_WEIGHT 16 31 mmDMIFV_PG1_DPGV1_PIPE_ARBITRATION_CONTROL2 0 0x14ac 2 0 2 TIME_WEIGHT 0 15 URGENCY_WEIGHT 16 31 mmDMIFV_PG1_DPGV1_WATERMARK_MASK_CONTROL 0 0x14ad 4 0 2 STUTTER_EXIT_SELF_REFRESH_WATERMARK_MASK 0 1 URGENCY_WATERMARK_MASK 8 9 NB_PSTATE_CHANGE_WATERMARK_MASK 16 17 DISABLE_FLIP_URGENT 24 24 mmDMIFV_PG1_DPGV1_PIPE_URGENCY_CONTROL 0 0x14ae 2 0 2 URGENCY_LOW_WATERMARK 0 15 URGENCY_HIGH_WATERMARK 16 31 mmDMIFV_PG1_DPGV1_PIPE_DPM_CONTROL 0 0x14af 1 0 2 DPM_ENABLE 0 0 mmDMIFV_PG1_DPGV1_PIPE_STUTTER_CONTROL 0 0x14b0 10 0 2 STUTTER_ENABLE 0 0 STUTTER_IGNORE_CURSOR 4 4 STUTTER_IGNORE_ICON 5 5 STUTTER_IGNORE_VGA 6 6 STUTTER_IGNORE_FBC 7 7 STUTTER_WM_HIGH_FORCE_ON 8 8 STUTTER_WM_HIGH_EXCLUDES_VBLANK 9 9 STUTTER_URGENT_IN_NOT_SELF_REFRESH 10 10 STUTTER_SELF_REFRESH_FORCE_ON 11 11 STUTTER_EXIT_SELF_REFRESH_WATERMARK 16 31 mmDMIFV_PG1_DPGV1_PIPE_NB_PSTATE_CHANGE_CONTROL 0 0x14b1 6 0 2 NB_PSTATE_CHANGE_ENABLE 0 0 NB_PSTATE_CHANGE_URGENT_DURING_REQUEST 4 4 NB_PSTATE_CHANGE_NOT_SELF_REFRESH_DURING_REQUEST 8 8 NB_PSTATE_CHANGE_FORCE_ON 9 9 NB_PSTATE_ALLOW_FOR_URGENT 10 10 NB_PSTATE_CHANGE_WATERMARK 16 31 mmDMIFV_PG1_DPGV1_PIPE_STUTTER_CONTROL_NONLPTCH 0 0x14b2 9 0 2 STUTTER_ENABLE_NONLPTCH 0 0 STUTTER_IGNORE_CURSOR_NONLPTCH 4 4 STUTTER_IGNORE_ICON_NONLPTCH 5 5 STUTTER_IGNORE_VGA_NONLPTCH 6 6 STUTTER_IGNORE_FBC_NONLPTCH 7 7 STUTTER_WM_HIGH_FORCE_ON_NONLPTCH 8 8 STUTTER_WM_HIGH_EXCLUDES_VBLANK_NONLPTCH 9 9 STUTTER_URGENT_IN_NOT_SELF_REFRESH_NONLPTCH 10 10 STUTTER_SELF_REFRESH_FORCE_ON_NONLPTCH 11 11 mmDMIFV_PG1_DPGV1_REPEATER_PROGRAM 0 0x14b3 2 0 2 REG_DPG_DMIFRC_REPEATER 0 2 REG_DMIFRC_DPG_REPEATER 4 6 mmDMIFV_PG1_DPGV1_CHK_PRE_PROC_CNTL 0 0x14b7 1 0 2 DPG_DISABLE_DMIF_BUF_CHK 0 0 mmBLNDV1_BLNDV_CONTROL 0 0x14db 9 0 2 BLND_GLOBAL_GAIN 0 7 BLND_MODE 8 9 BLND_STEREO_TYPE 10 11 BLND_STEREO_POLARITY 12 12 BLND_FEEDTHROUGH_EN 13 13 BLND_ALPHA_MODE 16 17 BLND_ACTIVE_OVERLAP_ONLY 18 18 BLND_MULTIPLIED_MODE 20 20 BLND_GLOBAL_ALPHA 24 31 mmBLNDV1_BLNDV_SM_CONTROL2 0 0x14dc 6 0 2 SM_MODE 0 2 SM_FRAME_ALTERNATE 4 4 SM_FIELD_ALTERNATE 5 5 SM_FORCE_NEXT_FRAME_POL 8 9 SM_FORCE_NEXT_TOP_POL 16 17 SM_CURRENT_FRAME_POL 24 24 mmBLNDV1_BLNDV_CONTROL2 0 0x14dd 5 0 2 PTI_ENABLE 0 0 PTI_NEW_PIXEL_GAP 4 5 BLND_NEW_PIXEL_MODE 6 6 BLND_SUPERAA_DEGAMMA_EN 7 7 BLND_SUPERAA_REGAMMA_EN 8 8 mmBLNDV1_BLNDV_UPDATE 0 0x14de 3 0 2 BLND_UPDATE_PENDING 0 0 BLND_UPDATE_TAKEN 8 8 BLND_UPDATE_LOCK 16 16 mmBLNDV1_BLNDV_UNDERFLOW_INTERRUPT 0 0x14df 4 0 2 BLND_UNDERFLOW_INT_OCCURED 0 0 BLND_UNDERFLOW_INT_ACK 8 8 BLND_UNDERFLOW_INT_MASK 12 12 BLND_UNDERFLOW_INT_PIPE_INDEX 16 17 mmBLNDV1_BLNDV_V_UPDATE_LOCK 0 0x14e0 6 0 2 BLND_DCP_GRPH_V_UPDATE_LOCK 0 0 BLND_DCP_GRPH_SURF_V_UPDATE_LOCK 1 1 BLND_DCP_CUR_V_UPDATE_LOCK 16 16 BLND_SCL_V_UPDATE_LOCK 28 28 BLND_BLND_V_UPDATE_LOCK 29 29 BLND_V_UPDATE_LOCK_MODE 31 31 mmBLNDV1_BLNDV_REG_UPDATE_STATUS 0 0x14e1 10 0 2 DCP_BLNDC_GRPH_UPDATE_PENDING 0 0 DCP_BLNDO_GRPH_UPDATE_PENDING 1 1 DCP_BLNDC_GRPH_SURF_UPDATE_PENDING 2 2 DCP_BLNDO_GRPH_SURF_UPDATE_PENDING 3 3 DCP_BLNDC_CUR_UPDATE_PENDING 6 6 DCP_BLNDO_CUR_UPDATE_PENDING 7 7 SCL_BLNDC_UPDATE_PENDING 8 8 SCL_BLNDO_UPDATE_PENDING 9 9 BLND_BLNDC_UPDATE_PENDING 10 10 BLND_BLNDO_UPDATE_PENDING 11 11 mmCRTCV1_CRTCV_H_BLANK_EARLY_NUM 0 0x14e6 2 0 2 CRTC_H_BLANK_EARLY_NUM 0 9 CRTC_H_BLANK_EARLY_NUM_DIS 16 16 mmCRTCV1_CRTCV_H_TOTAL 0 0x14e7 1 0 2 CRTC_H_TOTAL 0 13 mmCRTCV1_CRTCV_H_BLANK_START_END 0 0x14e8 2 0 2 CRTC_H_BLANK_START 0 13 CRTC_H_BLANK_END 16 29 mmCRTCV1_CRTCV_H_SYNC_A 0 0x14e9 2 0 2 CRTC_H_SYNC_A_START 0 13 CRTC_H_SYNC_A_END 16 29 mmCRTCV1_CRTCV_H_SYNC_A_CNTL 0 0x14ea 3 0 2 CRTC_H_SYNC_A_POL 0 0 CRTC_COMP_SYNC_A_EN 16 16 CRTC_H_SYNC_A_CUTOFF 17 17 mmCRTCV1_CRTCV_H_SYNC_B 0 0x14eb 2 0 2 CRTC_H_SYNC_B_START 0 13 CRTC_H_SYNC_B_END 16 29 mmCRTCV1_CRTCV_H_SYNC_B_CNTL 0 0x14ec 3 0 2 CRTC_H_SYNC_B_POL 0 0 CRTC_COMP_SYNC_B_EN 16 16 CRTC_H_SYNC_B_CUTOFF 17 17 mmCRTCV1_CRTCV_VBI_END 0 0x14ed 2 0 2 CRTC_VBI_V_END 0 13 CRTC_VBI_H_END 16 29 mmCRTCV1_CRTCV_V_TOTAL 0 0x14ee 1 0 2 CRTC_V_TOTAL 0 13 mmCRTCV1_CRTCV_V_TOTAL_MIN 0 0x14ef 1 0 2 CRTC_V_TOTAL_MIN 0 13 mmCRTCV1_CRTCV_V_TOTAL_MAX 0 0x14f0 2 0 2 CRTC_V_TOTAL_MAX 0 13 CRTC_ALLOW_VBLANK_EXTENSION_FOR_MC_TRAINING 16 16 mmCRTCV1_CRTCV_V_TOTAL_CONTROL 0 0x14f1 6 0 2 CRTC_V_TOTAL_MIN_SEL 0 0 CRTC_V_TOTAL_MAX_SEL 4 4 CRTC_FORCE_LOCK_ON_EVENT 8 8 CRTC_FORCE_LOCK_TO_MASTER_VSYNC 12 12 CRTC_SET_V_TOTAL_MIN_MASK_EN 15 15 CRTC_SET_V_TOTAL_MIN_MASK 16 31 mmCRTCV1_CRTCV_V_TOTAL_INT_STATUS 0 0x14f2 4 0 2 CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED 0 0 CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT 4 4 CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_ACK 8 8 CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_MSK 12 12 mmCRTCV1_CRTCV_VSYNC_NOM_INT_STATUS 0 0x14f3 2 0 2 CRTC_VSYNC_NOM 0 0 CRTC_VSYNC_NOM_INT_CLEAR 4 4 mmCRTCV1_CRTCV_V_BLANK_START_END 0 0x14f4 2 0 2 CRTC_V_BLANK_START 0 13 CRTC_V_BLANK_END 16 29 mmCRTCV1_CRTCV_V_SYNC_A 0 0x14f5 2 0 2 CRTC_V_SYNC_A_START 0 13 CRTC_V_SYNC_A_END 16 29 mmCRTCV1_CRTCV_V_SYNC_A_CNTL 0 0x14f6 1 0 2 CRTC_V_SYNC_A_POL 0 0 mmCRTCV1_CRTCV_V_SYNC_B 0 0x14f7 2 0 2 CRTC_V_SYNC_B_START 0 13 CRTC_V_SYNC_B_END 16 29 mmCRTCV1_CRTCV_V_SYNC_B_CNTL 0 0x14f8 1 0 2 CRTC_V_SYNC_B_POL 0 0 mmCRTCV1_CRTCV_DTMTEST_CNTL 0 0x14f9 2 0 2 CRTC_DTMTEST_CRTC_EN 0 0 CRTC_DTMTEST_CLK_DIV 1 4 mmCRTCV1_CRTCV_DTMTEST_STATUS_POSITION 0 0x14fa 2 0 2 CRTC_DTMTEST_VERT_COUNT 0 13 CRTC_DTMTEST_HORZ_COUNT 16 29 mmCRTCV1_CRTCV_TRIGA_CNTL 0 0x14fb 11 0 2 CRTC_TRIGA_SOURCE_SELECT 0 4 CRTC_TRIGA_POLARITY_SELECT 5 7 CRTC_TRIGA_RESYNC_BYPASS_EN 8 8 CRTC_TRIGA_INPUT_STATUS 9 9 CRTC_TRIGA_POLARITY_STATUS 10 10 CRTC_TRIGA_OCCURRED 11 11 CRTC_TRIGA_RISING_EDGE_DETECT_CNTL 12 13 CRTC_TRIGA_FALLING_EDGE_DETECT_CNTL 16 17 CRTC_TRIGA_FREQUENCY_SELECT 20 21 CRTC_TRIGA_DELAY 24 28 CRTC_TRIGA_CLEAR 31 31 mmCRTCV1_CRTCV_TRIGA_MANUAL_TRIG 0 0x14fc 1 0 2 CRTC_TRIGA_MANUAL_TRIG 0 0 mmCRTCV1_CRTCV_TRIGB_CNTL 0 0x14fd 11 0 2 CRTC_TRIGB_SOURCE_SELECT 0 4 CRTC_TRIGB_POLARITY_SELECT 5 7 CRTC_TRIGB_RESYNC_BYPASS_EN 8 8 CRTC_TRIGB_INPUT_STATUS 9 9 CRTC_TRIGB_POLARITY_STATUS 10 10 CRTC_TRIGB_OCCURRED 11 11 CRTC_TRIGB_RISING_EDGE_DETECT_CNTL 12 13 CRTC_TRIGB_FALLING_EDGE_DETECT_CNTL 16 17 CRTC_TRIGB_FREQUENCY_SELECT 20 21 CRTC_TRIGB_DELAY 24 28 CRTC_TRIGB_CLEAR 31 31 mmCRTCV1_CRTCV_TRIGB_MANUAL_TRIG 0 0x14fe 1 0 2 CRTC_TRIGB_MANUAL_TRIG 0 0 mmCRTCV1_CRTCV_FORCE_COUNT_NOW_CNTL 0 0x14ff 5 0 2 CRTC_FORCE_COUNT_NOW_MODE 0 1 CRTC_FORCE_COUNT_NOW_CHECK 4 4 CRTC_FORCE_COUNT_NOW_TRIG_SEL 8 8 CRTC_FORCE_COUNT_NOW_OCCURRED 16 16 CRTC_FORCE_COUNT_NOW_CLEAR 24 24 mmCRTCV1_CRTCV_FLOW_CONTROL 0 0x1500 4 0 2 CRTC_FLOW_CONTROL_SOURCE_SELECT 0 4 CRTC_FLOW_CONTROL_POLARITY 8 8 CRTC_FLOW_CONTROL_GRANULARITY 16 16 CRTC_FLOW_CONTROL_INPUT_STATUS 24 24 mmCRTCV1_CRTCV_STEREO_FORCE_NEXT_EYE 0 0x1501 3 0 2 CRTC_STEREO_FORCE_NEXT_EYE 0 1 CRTC_AVSYNC_FRAME_COUNTER 8 15 CRTC_AVSYNC_LINE_COUNTER 16 28 mmCRTCV1_CRTCV_AVSYNC_COUNTER 0 0x1502 1 0 2 CRTC_AVSYNC_COUNTER 0 31 mmCRTCV1_CRTCV_CONTROL 0 0x1503 11 0 2 CRTC_MASTER_EN 0 0 CRTC_SYNC_RESET_SEL 4 4 CRTC_DISABLE_POINT_CNTL 8 9 CRTC_START_POINT_CNTL 12 12 CRTC_FIELD_NUMBER_CNTL 13 13 CRTC_FIELD_NUMBER_POLARITY 14 14 CRTC_CURRENT_MASTER_EN_STATE 16 16 CRTC_HBLANK_EARLY_CONTROL 20 22 CRTC_SOF_PULL_EN 29 29 CRTC_AVSYNC_LOCK_SNAPSHOT 30 30 CRTC_AVSYNC_VSYNC_N_HSYNC_MODE 31 31 mmCRTCV1_CRTCV_BLANK_CONTROL 0 0x1504 3 0 2 CRTC_CURRENT_BLANK_STATE 0 0 CRTC_BLANK_DATA_EN 8 8 CRTC_BLANK_DE_MODE 16 16 mmCRTCV1_CRTCV_INTERLACE_CONTROL 0 0x1505 2 0 2 CRTC_INTERLACE_ENABLE 0 0 CRTC_INTERLACE_FORCE_NEXT_FIELD 16 17 mmCRTCV1_CRTCV_INTERLACE_STATUS 0 0x1506 2 0 2 CRTC_INTERLACE_CURRENT_FIELD 0 0 CRTC_INTERLACE_NEXT_FIELD 1 1 mmCRTCV1_CRTCV_FIELD_INDICATION_CONTROL 0 0x1507 2 0 2 CRTC_FIELD_INDICATION_OUTPUT_POLARITY 0 0 CRTC_FIELD_ALIGNMENT 1 1 mmCRTCV1_CRTCV_PIXEL_DATA_READBACK0 0 0x1508 2 0 2 CRTC_PIXEL_DATA_BLUE_CB 0 11 CRTC_PIXEL_DATA_GREEN_Y 16 27 mmCRTCV1_CRTCV_PIXEL_DATA_READBACK1 0 0x1509 1 0 2 CRTC_PIXEL_DATA_RED_CR 0 11 mmCRTCV1_CRTCV_STATUS 0 0x150a 9 0 2 CRTC_V_BLANK 0 0 CRTC_V_ACTIVE_DISP 1 1 CRTC_V_SYNC_A 2 2 CRTC_V_UPDATE 3 3 CRTC_V_START_LINE 4 4 CRTC_V_BLANK_3D_STRUCTURE 5 5 CRTC_H_BLANK 16 16 CRTC_H_ACTIVE_DISP 17 17 CRTC_H_SYNC_A 18 18 mmCRTCV1_CRTCV_STATUS_POSITION 0 0x150b 2 0 2 CRTC_VERT_COUNT 0 13 CRTC_HORZ_COUNT 16 29 mmCRTCV1_CRTCV_NOM_VERT_POSITION 0 0x150c 1 0 2 CRTC_VERT_COUNT_NOM 0 13 mmCRTCV1_CRTCV_STATUS_FRAME_COUNT 0 0x150d 1 0 2 CRTC_FRAME_COUNT 0 23 mmCRTCV1_CRTCV_STATUS_VF_COUNT 0 0x150e 1 0 2 CRTC_VF_COUNT 0 29 mmCRTCV1_CRTCV_STATUS_HV_COUNT 0 0x150f 1 0 2 CRTC_HV_COUNT 0 29 mmCRTCV1_CRTCV_COUNT_CONTROL 0 0x1510 2 0 2 CRTC_HORZ_COUNT_BY2_EN 0 0 CRTC_HORZ_REPETITION_COUNT 1 4 mmCRTCV1_CRTCV_COUNT_RESET 0 0x1511 1 0 2 CRTC_RESET_FRAME_COUNT 0 0 mmCRTCV1_CRTCV_MANUAL_FORCE_VSYNC_NEXT_LINE 0 0x1512 1 0 2 CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE 0 0 mmCRTCV1_CRTCV_VERT_SYNC_CONTROL 0 0x1513 3 0 2 CRTC_FORCE_VSYNC_NEXT_LINE_OCCURRED 0 0 CRTC_FORCE_VSYNC_NEXT_LINE_CLEAR 8 8 CRTC_AUTO_FORCE_VSYNC_MODE 16 17 mmCRTCV1_CRTCV_STEREO_STATUS 0 0x1514 5 0 2 CRTC_STEREO_CURRENT_EYE 0 0 CRTC_STEREO_SYNC_OUTPUT 8 8 CRTC_STEREO_SYNC_SELECT 16 16 CRTC_STEREO_EYE_FLAG 20 20 CRTC_STEREO_FORCE_NEXT_EYE_PENDING 24 25 mmCRTCV1_CRTCV_STEREO_CONTROL 0 0x1515 8 0 2 CRTC_STEREO_SYNC_OUTPUT_LINE_NUM 0 13 CRTC_STEREO_SYNC_OUTPUT_POLARITY 15 15 CRTC_STEREO_SYNC_SELECT_POLARITY 16 16 CRTC_STEREO_EYE_FLAG_POLARITY 17 17 CRTC_DISABLE_STEREOSYNC_OUTPUT_FOR_DP 18 18 CRTC_DISABLE_FIELD_NUM 19 19 CRTC_DISABLE_V_BLANK_FOR_DP_FIX 20 20 CRTC_STEREO_EN 24 24 mmCRTCV1_CRTCV_SNAPSHOT_STATUS 0 0x1516 3 0 2 CRTC_SNAPSHOT_OCCURRED 0 0 CRTC_SNAPSHOT_CLEAR 1 1 CRTC_SNAPSHOT_MANUAL_TRIGGER 2 2 mmCRTCV1_CRTCV_SNAPSHOT_CONTROL 0 0x1517 1 0 2 CRTC_AUTO_SNAPSHOT_TRIG_SEL 0 1 mmCRTCV1_CRTCV_SNAPSHOT_POSITION 0 0x1518 2 0 2 CRTC_SNAPSHOT_VERT_COUNT 0 13 CRTC_SNAPSHOT_HORZ_COUNT 16 29 mmCRTCV1_CRTCV_SNAPSHOT_FRAME 0 0x1519 1 0 2 CRTC_SNAPSHOT_FRAME_COUNT 0 23 mmCRTCV1_CRTCV_START_LINE_CONTROL 0 0x151a 5 0 2 CRTC_PROGRESSIVE_START_LINE_EARLY 0 0 CRTC_INTERLACE_START_LINE_EARLY 1 1 CRTC_PREFETCH_EN 2 2 CRTC_LEGACY_REQUESTOR_EN 8 8 CRTC_ADVANCED_START_LINE_POSITION 12 19 mmCRTCV1_CRTCV_INTERRUPT_CONTROL 0 0x151b 16 0 2 CRTC_SNAPSHOT_INT_MSK 0 0 CRTC_SNAPSHOT_INT_TYPE 1 1 CRTC_V_UPDATE_INT_MSK 4 4 CRTC_V_UPDATE_INT_TYPE 5 5 CRTC_FORCE_COUNT_NOW_INT_MSK 8 8 CRTC_FORCE_COUNT_NOW_INT_TYPE 9 9 CRTC_FORCE_VSYNC_NEXT_LINE_INT_MSK 16 16 CRTC_FORCE_VSYNC_NEXT_LINE_INT_TYPE 17 17 CRTC_TRIGA_INT_MSK 24 24 CRTC_TRIGB_INT_MSK 25 25 CRTC_TRIGA_INT_TYPE 26 26 CRTC_TRIGB_INT_TYPE 27 27 CRTC_VSYNC_NOM_INT_MSK 28 28 CRTC_VSYNC_NOM_INT_TYPE 29 29 CRTC_GSL_VSYNC_GAP_INT_MSK 30 30 CRTC_GSL_VSYNC_GAP_INT_TYPE 31 31 mmCRTCV1_CRTCV_UPDATE_LOCK 0 0x151c 1 0 2 CRTC_UPDATE_LOCK 0 0 mmCRTCV1_CRTCV_DOUBLE_BUFFER_CONTROL 0 0x151d 5 0 2 CRTC_UPDATE_PENDING 0 0 CRTC_UPDATE_INSTANTLY 8 8 CRTC_BLANK_DATA_DOUBLE_BUFFER_EN 16 16 CRTC_RANGE_TIMING_DBUF_UPDATE_MODE 24 24 CRTC_RANGE_TIMING_DBUF_UPDATE_PENDING 25 25 mmCRTCV1_CRTCV_VGA_PARAMETER_CAPTURE_MODE 0 0x151e 1 0 2 CRTC_VGA_PARAMETER_CAPTURE_MODE 0 0 mmCRTCV1_CRTCV_TEST_PATTERN_CONTROL 0 0x151f 4 0 2 CRTC_TEST_PATTERN_EN 0 0 CRTC_TEST_PATTERN_MODE 8 10 CRTC_TEST_PATTERN_DYNAMIC_RANGE 16 16 CRTC_TEST_PATTERN_COLOR_FORMAT 24 31 mmCRTCV1_CRTCV_TEST_PATTERN_PARAMETERS 0 0x1520 5 0 2 CRTC_TEST_PATTERN_INC0 0 3 CRTC_TEST_PATTERN_INC1 4 7 CRTC_TEST_PATTERN_VRES 8 11 CRTC_TEST_PATTERN_HRES 12 15 CRTC_TEST_PATTERN_RAMP0_OFFSET 16 31 mmCRTCV1_CRTCV_TEST_PATTERN_COLOR 0 0x1521 2 0 2 CRTC_TEST_PATTERN_DATA 0 15 CRTC_TEST_PATTERN_MASK 16 21 mmCRTCV1_CRTCV_MASTER_UPDATE_LOCK 0 0x1522 3 0 2 MASTER_UPDATE_LOCK 0 0 GSL_CONTROL_MASTER_UPDATE_LOCK 8 8 UNDERFLOW_UPDATE_LOCK 16 16 mmCRTCV1_CRTCV_MASTER_UPDATE_MODE 0 0x1523 2 0 2 MASTER_UPDATE_MODE 0 2 MASTER_UPDATE_INTERLACED_MODE 16 17 mmCRTCV1_CRTCV_MVP_INBAND_CNTL_INSERT 0 0x1524 2 0 2 CRTC_MVP_INBAND_OUT_MODE 0 1 CRTC_MVP_INBAND_CNTL_CHAR_INSERT 8 31 mmCRTCV1_CRTCV_MVP_INBAND_CNTL_INSERT_TIMER 0 0x1525 1 0 2 CRTC_MVP_INBAND_CNTL_CHAR_INSERT_TIMER 0 7 mmCRTCV1_CRTCV_MVP_STATUS 0 0x1526 4 0 2 CRTC_FLIP_NOW_OCCURRED 0 0 CRTC_AFR_HSYNC_SWITCH_DONE_OCCURRED 4 4 CRTC_FLIP_NOW_CLEAR 16 16 CRTC_AFR_HSYNC_SWITCH_DONE_CLEAR 20 20 mmCRTCV1_CRTCV_MASTER_EN 0 0x1527 1 0 2 CRTC_MASTER_EN 0 0 mmCRTCV1_CRTCV_ALLOW_STOP_OFF_V_CNT 0 0x1528 2 0 2 CRTC_ALLOW_STOP_OFF_V_CNT 0 7 CRTC_DISABLE_ALLOW_STOP_OFF_V_CNT 16 16 mmCRTCV1_CRTCV_V_UPDATE_INT_STATUS 0 0x1529 2 0 2 CRTC_V_UPDATE_INT_OCCURRED 0 0 CRTC_V_UPDATE_INT_CLEAR 8 8 mmCRTCV1_CRTCV_OVERSCAN_COLOR 0 0x152b 3 0 2 CRTC_OVERSCAN_COLOR_BLUE 0 9 CRTC_OVERSCAN_COLOR_GREEN 10 19 CRTC_OVERSCAN_COLOR_RED 20 29 mmCRTCV1_CRTCV_OVERSCAN_COLOR_EXT 0 0x152c 3 0 2 CRTC_OVERSCAN_COLOR_BLUE_EXT 0 1 CRTC_OVERSCAN_COLOR_GREEN_EXT 8 9 CRTC_OVERSCAN_COLOR_RED_EXT 16 17 mmCRTCV1_CRTCV_BLANK_DATA_COLOR 0 0x152d 3 0 2 CRTC_BLANK_DATA_COLOR_BLUE_CB 0 9 CRTC_BLANK_DATA_COLOR_GREEN_Y 10 19 CRTC_BLANK_DATA_COLOR_RED_CR 20 29 mmCRTCV1_CRTCV_BLANK_DATA_COLOR_EXT 0 0x152e 3 0 2 CRTC_BLANK_DATA_COLOR_BLUE_CB_EXT 0 1 CRTC_BLANK_DATA_COLOR_GREEN_Y_EXT 8 9 CRTC_BLANK_DATA_COLOR_RED_CR_EXT 16 17 mmCRTCV1_CRTCV_BLACK_COLOR 0 0x152f 3 0 2 CRTC_BLACK_COLOR_B_CB 0 9 CRTC_BLACK_COLOR_G_Y 10 19 CRTC_BLACK_COLOR_R_CR 20 29 mmCRTCV1_CRTCV_BLACK_COLOR_EXT 0 0x1530 3 0 2 CRTC_BLACK_COLOR_B_CB_EXT 0 1 CRTC_BLACK_COLOR_G_Y_EXT 8 9 CRTC_BLACK_COLOR_R_CR_EXT 16 17 mmCRTCV1_CRTCV_VERTICAL_INTERRUPT0_POSITION 0 0x1531 2 0 2 CRTC_VERTICAL_INTERRUPT0_LINE_START 0 13 CRTC_VERTICAL_INTERRUPT0_LINE_END 16 29 mmCRTCV1_CRTCV_VERTICAL_INTERRUPT0_CONTROL 0 0x1532 6 0 2 CRTC_VERTICAL_INTERRUPT0_OUTPUT_POLARITY 4 4 CRTC_VERTICAL_INTERRUPT0_INT_ENABLE 8 8 CRTC_VERTICAL_INTERRUPT0_STATUS 12 12 CRTC_VERTICAL_INTERRUPT0_INT_STATUS 16 16 CRTC_VERTICAL_INTERRUPT0_CLEAR 20 20 CRTC_VERTICAL_INTERRUPT0_INT_TYPE 24 24 mmCRTCV1_CRTCV_VERTICAL_INTERRUPT1_POSITION 0 0x1533 1 0 2 CRTC_VERTICAL_INTERRUPT1_LINE_START 0 13 mmCRTCV1_CRTCV_VERTICAL_INTERRUPT1_CONTROL 0 0x1534 5 0 2 CRTC_VERTICAL_INTERRUPT1_INT_ENABLE 8 8 CRTC_VERTICAL_INTERRUPT1_STATUS 12 12 CRTC_VERTICAL_INTERRUPT1_INT_STATUS 16 16 CRTC_VERTICAL_INTERRUPT1_CLEAR 20 20 CRTC_VERTICAL_INTERRUPT1_INT_TYPE 24 24 mmCRTCV1_CRTCV_VERTICAL_INTERRUPT2_POSITION 0 0x1535 1 0 2 CRTC_VERTICAL_INTERRUPT2_LINE_START 0 13 mmCRTCV1_CRTCV_VERTICAL_INTERRUPT2_CONTROL 0 0x1536 5 0 2 CRTC_VERTICAL_INTERRUPT2_INT_ENABLE 8 8 CRTC_VERTICAL_INTERRUPT2_STATUS 12 12 CRTC_VERTICAL_INTERRUPT2_INT_STATUS 16 16 CRTC_VERTICAL_INTERRUPT2_CLEAR 20 20 CRTC_VERTICAL_INTERRUPT2_INT_TYPE 24 24 mmCRTCV1_CRTCV_CRC_CNTL 0 0x1537 7 0 2 CRTC_CRC_EN 0 0 CRTC_CRC_CONT_EN 4 4 CRTC_CRC_STEREO_MODE 8 9 CRTC_CRC_INTERLACE_MODE 12 13 CRTC_CRC_USE_NEW_AND_REPEATED_PIXELS 16 16 CRTC_CRC0_SELECT 20 22 CRTC_CRC1_SELECT 24 26 mmCRTCV1_CRTCV_CRC0_WINDOWA_X_CONTROL 0 0x1538 2 0 2 CRTC_CRC0_WINDOWA_X_START 0 13 CRTC_CRC0_WINDOWA_X_END 16 29 mmCRTCV1_CRTCV_CRC0_WINDOWA_Y_CONTROL 0 0x1539 2 0 2 CRTC_CRC0_WINDOWA_Y_START 0 13 CRTC_CRC0_WINDOWA_Y_END 16 29 mmCRTCV1_CRTCV_CRC0_WINDOWB_X_CONTROL 0 0x153a 2 0 2 CRTC_CRC0_WINDOWB_X_START 0 13 CRTC_CRC0_WINDOWB_X_END 16 29 mmCRTCV1_CRTCV_CRC0_WINDOWB_Y_CONTROL 0 0x153b 2 0 2 CRTC_CRC0_WINDOWB_Y_START 0 13 CRTC_CRC0_WINDOWB_Y_END 16 29 mmCRTCV1_CRTCV_CRC0_DATA_RG 0 0x153c 2 0 2 CRC0_R_CR 0 15 CRC0_G_Y 16 31 mmCRTCV1_CRTCV_CRC0_DATA_B 0 0x153d 1 0 2 CRC0_B_CB 0 15 mmCRTCV1_CRTCV_CRC1_WINDOWA_X_CONTROL 0 0x153e 2 0 2 CRTC_CRC1_WINDOWA_X_START 0 13 CRTC_CRC1_WINDOWA_X_END 16 29 mmCRTCV1_CRTCV_CRC1_WINDOWA_Y_CONTROL 0 0x153f 2 0 2 CRTC_CRC1_WINDOWA_Y_START 0 13 CRTC_CRC1_WINDOWA_Y_END 16 29 mmCRTCV1_CRTCV_CRC1_WINDOWB_X_CONTROL 0 0x1540 2 0 2 CRTC_CRC1_WINDOWB_X_START 0 13 CRTC_CRC1_WINDOWB_X_END 16 29 mmCRTCV1_CRTCV_CRC1_WINDOWB_Y_CONTROL 0 0x1541 2 0 2 CRTC_CRC1_WINDOWB_Y_START 0 13 CRTC_CRC1_WINDOWB_Y_END 16 29 mmCRTCV1_CRTCV_CRC1_DATA_RG 0 0x1542 2 0 2 CRC1_R_CR 0 15 CRC1_G_Y 16 31 mmCRTCV1_CRTCV_CRC1_DATA_B 0 0x1543 1 0 2 CRC1_B_CB 0 15 mmCRTCV1_CRTCV_EXT_TIMING_SYNC_CONTROL 0 0x1544 11 0 2 CRTC_EXT_TIMING_SYNC_ENABLE 0 1 CRTC_EXT_TIMING_SYNC_HCOUNT_MODE_ENABLE 3 3 CRTC_EXT_TIMING_SYNC_JITTER_FILTERING_ENABLE 4 4 CRTC_EXT_TIMING_SYNC_JITTER_FILTERING_WINDOW 5 6 CRTC_EXT_TIMING_SYNC_WINDOW_ENABLE 8 8 CRTC_EXT_TIMING_SYNC_WINDOW_UPDATE 9 9 CRTC_EXT_TIMING_SYNC_VSYNC_POLARITY 12 12 CRTC_EXT_TIMING_SYNC_HSYNC_POLARITY 13 13 CRTC_EXT_TIMING_SYNC_INTERLACE_MODE 14 14 CRTC_EXT_TIMING_SYNC_MASTER_FRAME_RATE 24 26 CRTC_EXT_TIMING_SYNC_SLAVE_FRAME_RATE 28 30 mmCRTCV1_CRTCV_EXT_TIMING_SYNC_WINDOW_START 0 0x1545 2 0 2 CRTC_EXT_TIMING_SYNC_WINDOW_START_X 0 13 CRTC_EXT_TIMING_SYNC_WINDOW_START_Y 16 29 mmCRTCV1_CRTCV_EXT_TIMING_SYNC_WINDOW_END 0 0x1546 2 0 2 CRTC_EXT_TIMING_SYNC_WINDOW_END_X 0 13 CRTC_EXT_TIMING_SYNC_WINDOW_END_Y 16 29 mmCRTCV1_CRTCV_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL 0 0x1547 6 0 2 CRTC_EXT_TIMING_SYNC_LOSS_INT_ENABLE 0 0 CRTC_EXT_TIMING_SYNC_LOSS_STATUS 4 4 CRTC_EXT_TIMING_SYNC_LOSS_INT_STATUS 8 8 CRTC_EXT_TIMING_SYNC_LOSS_CLEAR 16 16 CRTC_EXT_TIMING_SYNC_LOSS_INT_TYPE 20 20 CRTC_EXT_TIMING_SYNC_LOSS_FRAME_COUNT 29 31 mmCRTCV1_CRTCV_EXT_TIMING_SYNC_INTERRUPT_CONTROL 0 0x1548 5 0 2 CRTC_EXT_TIMING_SYNC_INT_ENABLE 0 0 CRTC_EXT_TIMING_SYNC_STATUS 4 4 CRTC_EXT_TIMING_SYNC_INT_STATUS 8 8 CRTC_EXT_TIMING_SYNC_CLEAR 16 16 CRTC_EXT_TIMING_SYNC_INT_TYPE 20 20 mmCRTCV1_CRTCV_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL 0 0x1549 5 0 2 CRTC_EXT_TIMING_SYNC_SIGNAL_INT_ENABLE 0 0 CRTC_EXT_TIMING_SYNC_SIGNAL_STATUS 4 4 CRTC_EXT_TIMING_SYNC_SIGNAL_INT_STATUS 8 8 CRTC_EXT_TIMING_SYNC_SIGNAL_CLEAR 16 16 CRTC_EXT_TIMING_SYNC_SIGNAL_INT_TYPE 20 20 mmCRTCV1_CRTCV_STATIC_SCREEN_CONTROL 0 0x154a 7 0 2 CRTC_STATIC_SCREEN_EVENT_MASK 0 15 CRTC_STATIC_SCREEN_FRAME_COUNT 16 23 CRTC_CPU_SS_INT_ENABLE 24 24 CRTC_SS_STATUS 25 25 CRTC_CPU_SS_INT_STATUS 26 26 CRTC_CPU_SS_INT_CLEAR 27 27 CRTC_CPU_SS_INT_TYPE 28 28 mmCRTCV1_CRTCV_3D_STRUCTURE_CONTROL 0 0x154b 7 0 2 CRTC_3D_STRUCTURE_EN 0 0 CRTC_3D_STRUCTURE_EN_DB 4 4 CRTC_3D_STRUCTURE_V_UPDATE_MODE 8 9 CRTC_3D_STRUCTURE_STEREO_SEL_OVR 12 12 CRTC_3D_STRUCTURE_F_COUNT_RESET 16 16 CRTC_3D_STRUCTURE_F_COUNT_RESET_PENDING 17 17 CRTC_3D_STRUCTURE_F_COUNT 18 19 mmCRTCV1_CRTCV_GSL_VSYNC_GAP 0 0x154c 8 0 2 CRTC_GSL_VSYNC_GAP_LIMIT 0 7 CRTC_GSL_VSYNC_GAP_DELAY 8 15 CRTC_GSL_VSYNC_GAP_SOURCE_SEL 16 16 CRTC_GSL_VSYNC_GAP_MODE 17 18 CRTC_GSL_VSYNC_GAP_CLEAR 19 19 CRTC_GSL_VSYNC_GAP_OCCURRED 20 20 CRTC_GSL_VSYNC_GAP_MASTER_FASTER 23 23 CRTC_GSL_VSYNC_GAP 24 31 mmCRTCV1_CRTCV_GSL_WINDOW 0 0x154d 2 0 2 CRTC_GSL_WINDOW_START 0 13 CRTC_GSL_WINDOW_END 16 29 mmCRTCV1_CRTCV_GSL_CONTROL 0 0x154e 3 0 2 CRTC_GSL_CHECK_LINE_NUM 0 13 CRTC_GSL_FORCE_DELAY 16 20 CRTC_GSL_CHECK_ALL_FIELDS 28 28 mmHPD0_DC_HPD_INT_STATUS 0 0x1600 6 0 2 DC_HPD_INT_STATUS 0 0 DC_HPD_SENSE 1 1 DC_HPD_SENSE_DELAYED 4 4 DC_HPD_RX_INT_STATUS 8 8 DC_HPD_TOGGLE_FILT_CON_TIMER_VAL 12 19 DC_HPD_TOGGLE_FILT_DISCON_TIMER_VAL 24 31 mmHPD0_DC_HPD_INT_CONTROL 0 0x1601 5 0 2 DC_HPD_INT_ACK 0 0 DC_HPD_INT_POLARITY 8 8 DC_HPD_INT_EN 16 16 DC_HPD_RX_INT_ACK 20 20 DC_HPD_RX_INT_EN 24 24 mmHPD0_DC_HPD_CONTROL 0 0x1602 3 0 2 DC_HPD_CONNECTION_TIMER 0 12 DC_HPD_RX_INT_TIMER 16 25 DC_HPD_EN 28 28 mmHPD0_DC_HPD_FAST_TRAIN_CNTL 0 0x1603 4 0 2 DC_HPD_CONNECT_AUX_TX_DELAY 0 7 DC_HPD_CONNECT_FAST_TRAIN_DELAY 12 19 DC_HPD_CONNECT_AUX_TX_EN 24 24 DC_HPD_CONNECT_FAST_TRAIN_EN 28 28 mmHPD0_DC_HPD_TOGGLE_FILT_CNTL 0 0x1604 2 0 2 DC_HPD_CONNECT_INT_DELAY 0 7 DC_HPD_DISCONNECT_INT_DELAY 20 27 mmHPD1_DC_HPD_INT_STATUS 0 0x1608 6 0 2 DC_HPD_INT_STATUS 0 0 DC_HPD_SENSE 1 1 DC_HPD_SENSE_DELAYED 4 4 DC_HPD_RX_INT_STATUS 8 8 DC_HPD_TOGGLE_FILT_CON_TIMER_VAL 12 19 DC_HPD_TOGGLE_FILT_DISCON_TIMER_VAL 24 31 mmHPD1_DC_HPD_INT_CONTROL 0 0x1609 5 0 2 DC_HPD_INT_ACK 0 0 DC_HPD_INT_POLARITY 8 8 DC_HPD_INT_EN 16 16 DC_HPD_RX_INT_ACK 20 20 DC_HPD_RX_INT_EN 24 24 mmHPD1_DC_HPD_CONTROL 0 0x160a 3 0 2 DC_HPD_CONNECTION_TIMER 0 12 DC_HPD_RX_INT_TIMER 16 25 DC_HPD_EN 28 28 mmHPD1_DC_HPD_FAST_TRAIN_CNTL 0 0x160b 4 0 2 DC_HPD_CONNECT_AUX_TX_DELAY 0 7 DC_HPD_CONNECT_FAST_TRAIN_DELAY 12 19 DC_HPD_CONNECT_AUX_TX_EN 24 24 DC_HPD_CONNECT_FAST_TRAIN_EN 28 28 mmHPD1_DC_HPD_TOGGLE_FILT_CNTL 0 0x160c 2 0 2 DC_HPD_CONNECT_INT_DELAY 0 7 DC_HPD_DISCONNECT_INT_DELAY 20 27 mmHPD2_DC_HPD_INT_STATUS 0 0x1610 6 0 2 DC_HPD_INT_STATUS 0 0 DC_HPD_SENSE 1 1 DC_HPD_SENSE_DELAYED 4 4 DC_HPD_RX_INT_STATUS 8 8 DC_HPD_TOGGLE_FILT_CON_TIMER_VAL 12 19 DC_HPD_TOGGLE_FILT_DISCON_TIMER_VAL 24 31 mmHPD2_DC_HPD_INT_CONTROL 0 0x1611 5 0 2 DC_HPD_INT_ACK 0 0 DC_HPD_INT_POLARITY 8 8 DC_HPD_INT_EN 16 16 DC_HPD_RX_INT_ACK 20 20 DC_HPD_RX_INT_EN 24 24 mmHPD2_DC_HPD_CONTROL 0 0x1612 3 0 2 DC_HPD_CONNECTION_TIMER 0 12 DC_HPD_RX_INT_TIMER 16 25 DC_HPD_EN 28 28 mmHPD2_DC_HPD_FAST_TRAIN_CNTL 0 0x1613 4 0 2 DC_HPD_CONNECT_AUX_TX_DELAY 0 7 DC_HPD_CONNECT_FAST_TRAIN_DELAY 12 19 DC_HPD_CONNECT_AUX_TX_EN 24 24 DC_HPD_CONNECT_FAST_TRAIN_EN 28 28 mmHPD2_DC_HPD_TOGGLE_FILT_CNTL 0 0x1614 2 0 2 DC_HPD_CONNECT_INT_DELAY 0 7 DC_HPD_DISCONNECT_INT_DELAY 20 27 mmHPD3_DC_HPD_INT_STATUS 0 0x1618 6 0 2 DC_HPD_INT_STATUS 0 0 DC_HPD_SENSE 1 1 DC_HPD_SENSE_DELAYED 4 4 DC_HPD_RX_INT_STATUS 8 8 DC_HPD_TOGGLE_FILT_CON_TIMER_VAL 12 19 DC_HPD_TOGGLE_FILT_DISCON_TIMER_VAL 24 31 mmHPD3_DC_HPD_INT_CONTROL 0 0x1619 5 0 2 DC_HPD_INT_ACK 0 0 DC_HPD_INT_POLARITY 8 8 DC_HPD_INT_EN 16 16 DC_HPD_RX_INT_ACK 20 20 DC_HPD_RX_INT_EN 24 24 mmHPD3_DC_HPD_CONTROL 0 0x161a 3 0 2 DC_HPD_CONNECTION_TIMER 0 12 DC_HPD_RX_INT_TIMER 16 25 DC_HPD_EN 28 28 mmHPD3_DC_HPD_FAST_TRAIN_CNTL 0 0x161b 4 0 2 DC_HPD_CONNECT_AUX_TX_DELAY 0 7 DC_HPD_CONNECT_FAST_TRAIN_DELAY 12 19 DC_HPD_CONNECT_AUX_TX_EN 24 24 DC_HPD_CONNECT_FAST_TRAIN_EN 28 28 mmHPD3_DC_HPD_TOGGLE_FILT_CNTL 0 0x161c 2 0 2 DC_HPD_CONNECT_INT_DELAY 0 7 DC_HPD_DISCONNECT_INT_DELAY 20 27 mmHPD4_DC_HPD_INT_STATUS 0 0x1620 6 0 2 DC_HPD_INT_STATUS 0 0 DC_HPD_SENSE 1 1 DC_HPD_SENSE_DELAYED 4 4 DC_HPD_RX_INT_STATUS 8 8 DC_HPD_TOGGLE_FILT_CON_TIMER_VAL 12 19 DC_HPD_TOGGLE_FILT_DISCON_TIMER_VAL 24 31 mmHPD4_DC_HPD_INT_CONTROL 0 0x1621 5 0 2 DC_HPD_INT_ACK 0 0 DC_HPD_INT_POLARITY 8 8 DC_HPD_INT_EN 16 16 DC_HPD_RX_INT_ACK 20 20 DC_HPD_RX_INT_EN 24 24 mmHPD4_DC_HPD_CONTROL 0 0x1622 3 0 2 DC_HPD_CONNECTION_TIMER 0 12 DC_HPD_RX_INT_TIMER 16 25 DC_HPD_EN 28 28 mmHPD4_DC_HPD_FAST_TRAIN_CNTL 0 0x1623 4 0 2 DC_HPD_CONNECT_AUX_TX_DELAY 0 7 DC_HPD_CONNECT_FAST_TRAIN_DELAY 12 19 DC_HPD_CONNECT_AUX_TX_EN 24 24 DC_HPD_CONNECT_FAST_TRAIN_EN 28 28 mmHPD4_DC_HPD_TOGGLE_FILT_CNTL 0 0x1624 2 0 2 DC_HPD_CONNECT_INT_DELAY 0 7 DC_HPD_DISCONNECT_INT_DELAY 20 27 mmHPD5_DC_HPD_INT_STATUS 0 0x1628 6 0 2 DC_HPD_INT_STATUS 0 0 DC_HPD_SENSE 1 1 DC_HPD_SENSE_DELAYED 4 4 DC_HPD_RX_INT_STATUS 8 8 DC_HPD_TOGGLE_FILT_CON_TIMER_VAL 12 19 DC_HPD_TOGGLE_FILT_DISCON_TIMER_VAL 24 31 mmHPD5_DC_HPD_INT_CONTROL 0 0x1629 5 0 2 DC_HPD_INT_ACK 0 0 DC_HPD_INT_POLARITY 8 8 DC_HPD_INT_EN 16 16 DC_HPD_RX_INT_ACK 20 20 DC_HPD_RX_INT_EN 24 24 mmHPD5_DC_HPD_CONTROL 0 0x162a 3 0 2 DC_HPD_CONNECTION_TIMER 0 12 DC_HPD_RX_INT_TIMER 16 25 DC_HPD_EN 28 28 mmHPD5_DC_HPD_FAST_TRAIN_CNTL 0 0x162b 4 0 2 DC_HPD_CONNECT_AUX_TX_DELAY 0 7 DC_HPD_CONNECT_FAST_TRAIN_DELAY 12 19 DC_HPD_CONNECT_AUX_TX_EN 24 24 DC_HPD_CONNECT_FAST_TRAIN_EN 28 28 mmHPD5_DC_HPD_TOGGLE_FILT_CNTL 0 0x162c 2 0 2 DC_HPD_CONNECT_INT_DELAY 0 7 DC_HPD_DISCONNECT_INT_DELAY 20 27 mmDC_PERFMON2_PERFCOUNTER_CNTL 0 0x1630 13 0 2 PERFCOUNTER_EVENT_SEL 0 8 PERFCOUNTER_CVALUE_SEL 9 11 PERFCOUNTER_INC_MODE 12 14 PERFCOUNTER_HW_CNTL_SEL 15 15 PERFCOUNTER_RUNEN_MODE 16 16 PERFCOUNTER_CNTOFF_SEL 17 21 PERFCOUNTER_CNTOFF_START_DIS 22 22 PERFCOUNTER_RESTART_EN 23 23 PERFCOUNTER_INT_EN 24 24 PERFCOUNTER_OFF_MASK 25 25 PERFCOUNTER_ACTIVE 26 26 PERFCOUNTER_INT_TYPE 27 27 PERFCOUNTER_CNTL_SEL 29 31 mmDC_PERFMON2_PERFCOUNTER_CNTL2 0 0x1631 4 0 2 PERFCOUNTER_COUNTED_VALUE_TYPE 0 1 PERFCOUNTER_HW_STOP1_SEL 2 2 PERFCOUNTER_HW_STOP2_SEL 3 3 PERFCOUNTER_CNTL2_SEL 29 31 mmDC_PERFMON2_PERFCOUNTER_STATE 0 0x1632 16 0 2 PERFCOUNTER_CNT0_STATE 0 1 PERFCOUNTER_STATE_SEL0 2 2 PERFCOUNTER_CNT1_STATE 4 5 PERFCOUNTER_STATE_SEL1 6 6 PERFCOUNTER_CNT2_STATE 8 9 PERFCOUNTER_STATE_SEL2 10 10 PERFCOUNTER_CNT3_STATE 12 13 PERFCOUNTER_STATE_SEL3 14 14 PERFCOUNTER_CNT4_STATE 16 17 PERFCOUNTER_STATE_SEL4 18 18 PERFCOUNTER_CNT5_STATE 20 21 PERFCOUNTER_STATE_SEL5 22 22 PERFCOUNTER_CNT6_STATE 24 25 PERFCOUNTER_STATE_SEL6 26 26 PERFCOUNTER_CNT7_STATE 28 29 PERFCOUNTER_STATE_SEL7 30 30 mmDC_PERFMON2_PERFMON_CNTL 0 0x1633 6 0 2 PERFMON_STATE 0 1 PERFMON_RPT_COUNT 8 27 PERFMON_CNTOFF_AND_OR 28 28 PERFMON_CNTOFF_INT_EN 29 29 PERFMON_CNTOFF_INT_STATUS 30 30 PERFMON_CNTOFF_INT_ACK 31 31 mmDC_PERFMON2_PERFMON_CNTL2 0 0x1634 4 0 2 PERFMON_CNTOFF_INT_TYPE 0 0 PERFMON_CLK_ENABLE 1 1 PERFMON_RUN_ENABLE_START_SEL 2 9 PERFMON_RUN_ENABLE_STOP_SEL 10 17 mmDC_PERFMON2_PERFMON_CVALUE_INT_MISC 0 0x1635 17 0 2 PERFCOUNTER_INT0_STATUS 0 0 PERFCOUNTER_INT1_STATUS 1 1 PERFCOUNTER_INT2_STATUS 2 2 PERFCOUNTER_INT3_STATUS 3 3 PERFCOUNTER_INT4_STATUS 4 4 PERFCOUNTER_INT5_STATUS 5 5 PERFCOUNTER_INT6_STATUS 6 6 PERFCOUNTER_INT7_STATUS 7 7 PERFCOUNTER_INT0_ACK 8 8 PERFCOUNTER_INT1_ACK 9 9 PERFCOUNTER_INT2_ACK 10 10 PERFCOUNTER_INT3_ACK 11 11 PERFCOUNTER_INT4_ACK 12 12 PERFCOUNTER_INT5_ACK 13 13 PERFCOUNTER_INT6_ACK 14 14 PERFCOUNTER_INT7_ACK 15 15 PERFMON_CVALUE_HI 16 31 mmDC_PERFMON2_PERFMON_CVALUE_LOW 0 0x1636 1 0 2 PERFMON_CVALUE_LOW 0 31 mmDC_PERFMON2_PERFMON_HI 0 0x1637 2 0 2 PERFMON_HI 0 15 PERFMON_READ_SEL 29 31 mmDC_PERFMON2_PERFMON_LOW 0 0x1638 1 0 2 PERFMON_LOW 0 31 mmDP_AUX0_AUX_CONTROL 0 0x1766 13 0 2 AUX_EN 0 0 AUX_RESET 4 4 AUX_RESET_DONE 5 5 AUX_LS_READ_EN 8 8 AUX_LS_UPDATE_DISABLE 12 12 AUX_IGNORE_HPD_DISCON 16 16 AUX_MODE_DET_EN 18 18 AUX_HPD_SEL 20 22 AUX_IMPCAL_REQ_EN 24 24 AUX_TEST_MODE 28 28 AUX_DEGLITCH_EN 29 29 SPARE_0 30 30 SPARE_1 31 31 mmDP_AUX0_AUX_SW_CONTROL 0 0x1767 4 0 2 AUX_SW_GO 0 0 AUX_LS_READ_TRIG 2 2 AUX_SW_START_DELAY 4 7 AUX_SW_WR_BYTES 16 20 mmDP_AUX0_AUX_ARB_CONTROL 0 0x1768 10 0 2 AUX_ARB_PRIORITY 0 1 AUX_REG_RW_CNTL_STATUS 2 3 AUX_NO_QUEUED_SW_GO 8 8 AUX_NO_QUEUED_LS_GO 10 10 AUX_SW_USE_AUX_REG_REQ 16 16 AUX_SW_PENDING_USE_AUX_REG_REQ 16 16 AUX_SW_DONE_USING_AUX_REG 17 17 AUX_DMCU_USE_AUX_REG_REQ 24 24 AUX_DMCU_PENDING_USE_AUX_REG_REQ 24 24 AUX_DMCU_DONE_USING_AUX_REG 25 25 mmDP_AUX0_AUX_INTERRUPT_CONTROL 0 0x1769 12 0 2 AUX_SW_DONE_INT 0 0 AUX_SW_DONE_ACK 1 1 AUX_SW_DONE_MASK 2 2 AUX_LS_DONE_INT 4 4 AUX_LS_DONE_ACK 5 5 AUX_LS_DONE_MASK 6 6 AUX_GTC_SYNC_LOCK_DONE_INT 8 8 AUX_GTC_SYNC_LOCK_DONE_ACK 9 9 AUX_GTC_SYNC_LOCK_DONE_INT_MASK 10 10 AUX_GTC_SYNC_ERROR_INT 12 12 AUX_GTC_SYNC_ERROR_ACK 13 13 AUX_GTC_SYNC_ERROR_INT_MASK 14 14 mmDP_AUX0_AUX_SW_STATUS 0 0x176a 18 0 2 AUX_SW_DONE 0 0 AUX_SW_REQ 1 1 AUX_SW_RX_TIMEOUT_STATE 4 6 AUX_SW_RX_TIMEOUT 7 7 AUX_SW_RX_OVERFLOW 8 8 AUX_SW_HPD_DISCON 9 9 AUX_SW_RX_PARTIAL_BYTE 10 10 AUX_SW_NON_AUX_MODE 11 11 AUX_SW_RX_MIN_COUNT_VIOL 12 12 AUX_SW_RX_INVALID_STOP 14 14 AUX_SW_RX_SYNC_INVALID_L 17 17 AUX_SW_RX_SYNC_INVALID_H 18 18 AUX_SW_RX_INVALID_START 19 19 AUX_SW_RX_RECV_NO_DET 20 20 AUX_SW_RX_RECV_INVALID_H 22 22 AUX_SW_RX_RECV_INVALID_L 23 23 AUX_SW_REPLY_BYTE_COUNT 24 28 AUX_ARB_STATUS 30 31 mmDP_AUX0_AUX_LS_STATUS 0 0x176b 20 0 2 AUX_LS_DONE 0 0 AUX_LS_REQ 1 1 AUX_LS_RX_TIMEOUT_STATE 4 6 AUX_LS_RX_TIMEOUT 7 7 AUX_LS_RX_OVERFLOW 8 8 AUX_LS_HPD_DISCON 9 9 AUX_LS_RX_PARTIAL_BYTE 10 10 AUX_LS_NON_AUX_MODE 11 11 AUX_LS_RX_MIN_COUNT_VIOL 12 12 AUX_LS_RX_INVALID_STOP 14 14 AUX_LS_RX_SYNC_INVALID_L 17 17 AUX_LS_RX_SYNC_INVALID_H 18 18 AUX_LS_RX_INVALID_START 19 19 AUX_LS_RX_RECV_NO_DET 20 20 AUX_LS_RX_RECV_INVALID_H 22 22 AUX_LS_RX_RECV_INVALID_L 23 23 AUX_LS_REPLY_BYTE_COUNT 24 28 AUX_LS_CP_IRQ 29 29 AUX_LS_UPDATED 30 30 AUX_LS_UPDATED_ACK 31 31 mmDP_AUX0_AUX_SW_DATA 0 0x176c 4 0 2 AUX_SW_DATA_RW 0 0 AUX_SW_DATA 8 15 AUX_SW_INDEX 16 20 AUX_SW_AUTOINCREMENT_DISABLE 31 31 mmDP_AUX0_AUX_LS_DATA 0 0x176d 2 0 2 AUX_LS_DATA 8 15 AUX_LS_INDEX 16 20 mmDP_AUX0_AUX_DPHY_TX_REF_CONTROL 0 0x176e 3 0 2 AUX_TX_REF_SEL 0 0 AUX_TX_RATE 4 5 AUX_TX_REF_DIV 16 24 mmDP_AUX0_AUX_DPHY_TX_CONTROL 0 0x176f 3 0 2 AUX_TX_PRECHARGE_LEN 0 2 AUX_TX_PRECHARGE_SYMBOLS 8 13 AUX_MODE_DET_CHECK_DELAY 16 18 mmDP_AUX0_AUX_DPHY_RX_CONTROL0 0 0x1770 10 0 2 AUX_RX_START_WINDOW 4 6 AUX_RX_RECEIVE_WINDOW 8 10 AUX_RX_HALF_SYM_DETECT_LEN 12 13 AUX_RX_TRANSITION_FILTER_EN 16 16 AUX_RX_ALLOW_BELOW_THRESHOLD_PHASE_DETECT 17 17 AUX_RX_ALLOW_BELOW_THRESHOLD_START 18 18 AUX_RX_ALLOW_BELOW_THRESHOLD_STOP 19 19 AUX_RX_PHASE_DETECT_LEN 20 21 AUX_RX_TIMEOUT_LEN 24 26 AUX_RX_DETECTION_THRESHOLD 28 30 mmDP_AUX0_AUX_DPHY_RX_CONTROL1 0 0x1771 1 0 2 AUX_RX_PRECHARGE_SKIP 0 7 mmDP_AUX0_AUX_DPHY_TX_STATUS 0 0x1772 3 0 2 AUX_TX_ACTIVE 0 0 AUX_TX_STATE 4 6 AUX_TX_HALF_SYM_PERIOD 16 24 mmDP_AUX0_AUX_DPHY_RX_STATUS 0 0x1773 4 0 2 AUX_RX_STATE 0 2 AUX_RX_SYNC_VALID_COUNT 8 12 AUX_RX_HALF_SYM_PERIOD_FRACT 16 20 AUX_RX_HALF_SYM_PERIOD 21 29 mmDP_AUX0_AUX_GTC_SYNC_ERROR_CONTROL 0 0x1775 4 0 2 AUX_GTC_POTENTIAL_ERROR_THRESHOLD 0 4 AUX_GTC_DEFINITE_ERROR_THRESHOLD 8 12 AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_LEN 16 17 AUX_GTC_SYNC_NUM_RETRY_FOR_LOCK_MAINT 20 21 mmDP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS 0 0x1776 12 0 2 AUX_GTC_SYNC_LOCK_ACQ_COMPLETE 0 0 AUX_GTC_SYNC_LOCK_LOST 4 4 AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_OCCURRED 8 8 AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_STATE 9 12 AUX_GTC_SYNC_PHASE_ADJUST_TIME_VIOL 16 16 AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED 20 20 AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED_ACK 21 21 AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED 22 22 AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED_ACK 23 23 AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED 24 24 AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED_ACK 25 25 AUX_GTC_SYNC_CTRL_STATE 28 31 mmDP_AUX0_AUX_GTC_SYNC_STATUS 0 0x1777 19 0 2 AUX_GTC_SYNC_DONE 0 0 AUX_GTC_SYNC_REQ 1 1 AUX_GTC_SYNC_RX_TIMEOUT_STATE 4 6 AUX_GTC_SYNC_TIMEOUT 7 7 AUX_GTC_SYNC_RX_OVERFLOW 8 8 AUX_GTC_SYNC_HPD_DISCON 9 9 AUX_GTC_SYNC_RX_PARTIAL_BYTE 10 10 AUX_GTC_SYNC_NON_AUX_MODE 11 11 AUX_GTC_SYNC_RX_MIN_COUNT_VIOL 12 12 AUX_GTC_SYNC_RX_INVALID_STOP 14 14 AUX_GTC_SYNC_RX_SYNC_INVALID_L 17 17 AUX_GTC_SYNC_RX_SYNC_INVALID_H 18 18 AUX_GTC_SYNC_RX_INVALID_START 19 19 AUX_GTC_SYNC_RX_RECV_NO_DET 20 20 AUX_GTC_SYNC_RX_RECV_INVALID_H 22 22 AUX_GTC_SYNC_RX_RECV_INVALID_L 23 23 AUX_GTC_SYNC_REPLY_BYTE_COUNT 24 28 AUX_GTC_SYNC_NACKED 29 29 AUX_GTC_MASTER_REQ_BY_RX 30 30 mmDP_AUX1_AUX_CONTROL 0 0x1782 13 0 2 AUX_EN 0 0 AUX_RESET 4 4 AUX_RESET_DONE 5 5 AUX_LS_READ_EN 8 8 AUX_LS_UPDATE_DISABLE 12 12 AUX_IGNORE_HPD_DISCON 16 16 AUX_MODE_DET_EN 18 18 AUX_HPD_SEL 20 22 AUX_IMPCAL_REQ_EN 24 24 AUX_TEST_MODE 28 28 AUX_DEGLITCH_EN 29 29 SPARE_0 30 30 SPARE_1 31 31 mmDP_AUX1_AUX_SW_CONTROL 0 0x1783 4 0 2 AUX_SW_GO 0 0 AUX_LS_READ_TRIG 2 2 AUX_SW_START_DELAY 4 7 AUX_SW_WR_BYTES 16 20 mmDP_AUX1_AUX_ARB_CONTROL 0 0x1784 10 0 2 AUX_ARB_PRIORITY 0 1 AUX_REG_RW_CNTL_STATUS 2 3 AUX_NO_QUEUED_SW_GO 8 8 AUX_NO_QUEUED_LS_GO 10 10 AUX_SW_USE_AUX_REG_REQ 16 16 AUX_SW_PENDING_USE_AUX_REG_REQ 16 16 AUX_SW_DONE_USING_AUX_REG 17 17 AUX_DMCU_USE_AUX_REG_REQ 24 24 AUX_DMCU_PENDING_USE_AUX_REG_REQ 24 24 AUX_DMCU_DONE_USING_AUX_REG 25 25 mmDP_AUX1_AUX_INTERRUPT_CONTROL 0 0x1785 12 0 2 AUX_SW_DONE_INT 0 0 AUX_SW_DONE_ACK 1 1 AUX_SW_DONE_MASK 2 2 AUX_LS_DONE_INT 4 4 AUX_LS_DONE_ACK 5 5 AUX_LS_DONE_MASK 6 6 AUX_GTC_SYNC_LOCK_DONE_INT 8 8 AUX_GTC_SYNC_LOCK_DONE_ACK 9 9 AUX_GTC_SYNC_LOCK_DONE_INT_MASK 10 10 AUX_GTC_SYNC_ERROR_INT 12 12 AUX_GTC_SYNC_ERROR_ACK 13 13 AUX_GTC_SYNC_ERROR_INT_MASK 14 14 mmDP_AUX1_AUX_SW_STATUS 0 0x1786 18 0 2 AUX_SW_DONE 0 0 AUX_SW_REQ 1 1 AUX_SW_RX_TIMEOUT_STATE 4 6 AUX_SW_RX_TIMEOUT 7 7 AUX_SW_RX_OVERFLOW 8 8 AUX_SW_HPD_DISCON 9 9 AUX_SW_RX_PARTIAL_BYTE 10 10 AUX_SW_NON_AUX_MODE 11 11 AUX_SW_RX_MIN_COUNT_VIOL 12 12 AUX_SW_RX_INVALID_STOP 14 14 AUX_SW_RX_SYNC_INVALID_L 17 17 AUX_SW_RX_SYNC_INVALID_H 18 18 AUX_SW_RX_INVALID_START 19 19 AUX_SW_RX_RECV_NO_DET 20 20 AUX_SW_RX_RECV_INVALID_H 22 22 AUX_SW_RX_RECV_INVALID_L 23 23 AUX_SW_REPLY_BYTE_COUNT 24 28 AUX_ARB_STATUS 30 31 mmDP_AUX1_AUX_LS_STATUS 0 0x1787 20 0 2 AUX_LS_DONE 0 0 AUX_LS_REQ 1 1 AUX_LS_RX_TIMEOUT_STATE 4 6 AUX_LS_RX_TIMEOUT 7 7 AUX_LS_RX_OVERFLOW 8 8 AUX_LS_HPD_DISCON 9 9 AUX_LS_RX_PARTIAL_BYTE 10 10 AUX_LS_NON_AUX_MODE 11 11 AUX_LS_RX_MIN_COUNT_VIOL 12 12 AUX_LS_RX_INVALID_STOP 14 14 AUX_LS_RX_SYNC_INVALID_L 17 17 AUX_LS_RX_SYNC_INVALID_H 18 18 AUX_LS_RX_INVALID_START 19 19 AUX_LS_RX_RECV_NO_DET 20 20 AUX_LS_RX_RECV_INVALID_H 22 22 AUX_LS_RX_RECV_INVALID_L 23 23 AUX_LS_REPLY_BYTE_COUNT 24 28 AUX_LS_CP_IRQ 29 29 AUX_LS_UPDATED 30 30 AUX_LS_UPDATED_ACK 31 31 mmDP_AUX1_AUX_SW_DATA 0 0x1788 4 0 2 AUX_SW_DATA_RW 0 0 AUX_SW_DATA 8 15 AUX_SW_INDEX 16 20 AUX_SW_AUTOINCREMENT_DISABLE 31 31 mmDP_AUX1_AUX_LS_DATA 0 0x1789 2 0 2 AUX_LS_DATA 8 15 AUX_LS_INDEX 16 20 mmDP_AUX1_AUX_DPHY_TX_REF_CONTROL 0 0x178a 3 0 2 AUX_TX_REF_SEL 0 0 AUX_TX_RATE 4 5 AUX_TX_REF_DIV 16 24 mmDP_AUX1_AUX_DPHY_TX_CONTROL 0 0x178b 3 0 2 AUX_TX_PRECHARGE_LEN 0 2 AUX_TX_PRECHARGE_SYMBOLS 8 13 AUX_MODE_DET_CHECK_DELAY 16 18 mmDP_AUX1_AUX_DPHY_RX_CONTROL0 0 0x178c 10 0 2 AUX_RX_START_WINDOW 4 6 AUX_RX_RECEIVE_WINDOW 8 10 AUX_RX_HALF_SYM_DETECT_LEN 12 13 AUX_RX_TRANSITION_FILTER_EN 16 16 AUX_RX_ALLOW_BELOW_THRESHOLD_PHASE_DETECT 17 17 AUX_RX_ALLOW_BELOW_THRESHOLD_START 18 18 AUX_RX_ALLOW_BELOW_THRESHOLD_STOP 19 19 AUX_RX_PHASE_DETECT_LEN 20 21 AUX_RX_TIMEOUT_LEN 24 26 AUX_RX_DETECTION_THRESHOLD 28 30 mmDP_AUX1_AUX_DPHY_RX_CONTROL1 0 0x178d 1 0 2 AUX_RX_PRECHARGE_SKIP 0 7 mmDP_AUX1_AUX_DPHY_TX_STATUS 0 0x178e 3 0 2 AUX_TX_ACTIVE 0 0 AUX_TX_STATE 4 6 AUX_TX_HALF_SYM_PERIOD 16 24 mmDP_AUX1_AUX_DPHY_RX_STATUS 0 0x178f 4 0 2 AUX_RX_STATE 0 2 AUX_RX_SYNC_VALID_COUNT 8 12 AUX_RX_HALF_SYM_PERIOD_FRACT 16 20 AUX_RX_HALF_SYM_PERIOD 21 29 mmDP_AUX1_AUX_GTC_SYNC_ERROR_CONTROL 0 0x1791 4 0 2 AUX_GTC_POTENTIAL_ERROR_THRESHOLD 0 4 AUX_GTC_DEFINITE_ERROR_THRESHOLD 8 12 AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_LEN 16 17 AUX_GTC_SYNC_NUM_RETRY_FOR_LOCK_MAINT 20 21 mmDP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS 0 0x1792 12 0 2 AUX_GTC_SYNC_LOCK_ACQ_COMPLETE 0 0 AUX_GTC_SYNC_LOCK_LOST 4 4 AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_OCCURRED 8 8 AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_STATE 9 12 AUX_GTC_SYNC_PHASE_ADJUST_TIME_VIOL 16 16 AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED 20 20 AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED_ACK 21 21 AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED 22 22 AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED_ACK 23 23 AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED 24 24 AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED_ACK 25 25 AUX_GTC_SYNC_CTRL_STATE 28 31 mmDP_AUX1_AUX_GTC_SYNC_STATUS 0 0x1793 19 0 2 AUX_GTC_SYNC_DONE 0 0 AUX_GTC_SYNC_REQ 1 1 AUX_GTC_SYNC_RX_TIMEOUT_STATE 4 6 AUX_GTC_SYNC_TIMEOUT 7 7 AUX_GTC_SYNC_RX_OVERFLOW 8 8 AUX_GTC_SYNC_HPD_DISCON 9 9 AUX_GTC_SYNC_RX_PARTIAL_BYTE 10 10 AUX_GTC_SYNC_NON_AUX_MODE 11 11 AUX_GTC_SYNC_RX_MIN_COUNT_VIOL 12 12 AUX_GTC_SYNC_RX_INVALID_STOP 14 14 AUX_GTC_SYNC_RX_SYNC_INVALID_L 17 17 AUX_GTC_SYNC_RX_SYNC_INVALID_H 18 18 AUX_GTC_SYNC_RX_INVALID_START 19 19 AUX_GTC_SYNC_RX_RECV_NO_DET 20 20 AUX_GTC_SYNC_RX_RECV_INVALID_H 22 22 AUX_GTC_SYNC_RX_RECV_INVALID_L 23 23 AUX_GTC_SYNC_REPLY_BYTE_COUNT 24 28 AUX_GTC_SYNC_NACKED 29 29 AUX_GTC_MASTER_REQ_BY_RX 30 30 mmDP_AUX2_AUX_CONTROL 0 0x179e 13 0 2 AUX_EN 0 0 AUX_RESET 4 4 AUX_RESET_DONE 5 5 AUX_LS_READ_EN 8 8 AUX_LS_UPDATE_DISABLE 12 12 AUX_IGNORE_HPD_DISCON 16 16 AUX_MODE_DET_EN 18 18 AUX_HPD_SEL 20 22 AUX_IMPCAL_REQ_EN 24 24 AUX_TEST_MODE 28 28 AUX_DEGLITCH_EN 29 29 SPARE_0 30 30 SPARE_1 31 31 mmDP_AUX2_AUX_SW_CONTROL 0 0x179f 4 0 2 AUX_SW_GO 0 0 AUX_LS_READ_TRIG 2 2 AUX_SW_START_DELAY 4 7 AUX_SW_WR_BYTES 16 20 mmDP_AUX2_AUX_ARB_CONTROL 0 0x17a0 10 0 2 AUX_ARB_PRIORITY 0 1 AUX_REG_RW_CNTL_STATUS 2 3 AUX_NO_QUEUED_SW_GO 8 8 AUX_NO_QUEUED_LS_GO 10 10 AUX_SW_USE_AUX_REG_REQ 16 16 AUX_SW_PENDING_USE_AUX_REG_REQ 16 16 AUX_SW_DONE_USING_AUX_REG 17 17 AUX_DMCU_USE_AUX_REG_REQ 24 24 AUX_DMCU_PENDING_USE_AUX_REG_REQ 24 24 AUX_DMCU_DONE_USING_AUX_REG 25 25 mmDP_AUX2_AUX_INTERRUPT_CONTROL 0 0x17a1 12 0 2 AUX_SW_DONE_INT 0 0 AUX_SW_DONE_ACK 1 1 AUX_SW_DONE_MASK 2 2 AUX_LS_DONE_INT 4 4 AUX_LS_DONE_ACK 5 5 AUX_LS_DONE_MASK 6 6 AUX_GTC_SYNC_LOCK_DONE_INT 8 8 AUX_GTC_SYNC_LOCK_DONE_ACK 9 9 AUX_GTC_SYNC_LOCK_DONE_INT_MASK 10 10 AUX_GTC_SYNC_ERROR_INT 12 12 AUX_GTC_SYNC_ERROR_ACK 13 13 AUX_GTC_SYNC_ERROR_INT_MASK 14 14 mmDP_AUX2_AUX_SW_STATUS 0 0x17a2 18 0 2 AUX_SW_DONE 0 0 AUX_SW_REQ 1 1 AUX_SW_RX_TIMEOUT_STATE 4 6 AUX_SW_RX_TIMEOUT 7 7 AUX_SW_RX_OVERFLOW 8 8 AUX_SW_HPD_DISCON 9 9 AUX_SW_RX_PARTIAL_BYTE 10 10 AUX_SW_NON_AUX_MODE 11 11 AUX_SW_RX_MIN_COUNT_VIOL 12 12 AUX_SW_RX_INVALID_STOP 14 14 AUX_SW_RX_SYNC_INVALID_L 17 17 AUX_SW_RX_SYNC_INVALID_H 18 18 AUX_SW_RX_INVALID_START 19 19 AUX_SW_RX_RECV_NO_DET 20 20 AUX_SW_RX_RECV_INVALID_H 22 22 AUX_SW_RX_RECV_INVALID_L 23 23 AUX_SW_REPLY_BYTE_COUNT 24 28 AUX_ARB_STATUS 30 31 mmDP_AUX2_AUX_LS_STATUS 0 0x17a3 20 0 2 AUX_LS_DONE 0 0 AUX_LS_REQ 1 1 AUX_LS_RX_TIMEOUT_STATE 4 6 AUX_LS_RX_TIMEOUT 7 7 AUX_LS_RX_OVERFLOW 8 8 AUX_LS_HPD_DISCON 9 9 AUX_LS_RX_PARTIAL_BYTE 10 10 AUX_LS_NON_AUX_MODE 11 11 AUX_LS_RX_MIN_COUNT_VIOL 12 12 AUX_LS_RX_INVALID_STOP 14 14 AUX_LS_RX_SYNC_INVALID_L 17 17 AUX_LS_RX_SYNC_INVALID_H 18 18 AUX_LS_RX_INVALID_START 19 19 AUX_LS_RX_RECV_NO_DET 20 20 AUX_LS_RX_RECV_INVALID_H 22 22 AUX_LS_RX_RECV_INVALID_L 23 23 AUX_LS_REPLY_BYTE_COUNT 24 28 AUX_LS_CP_IRQ 29 29 AUX_LS_UPDATED 30 30 AUX_LS_UPDATED_ACK 31 31 mmDP_AUX2_AUX_SW_DATA 0 0x17a4 4 0 2 AUX_SW_DATA_RW 0 0 AUX_SW_DATA 8 15 AUX_SW_INDEX 16 20 AUX_SW_AUTOINCREMENT_DISABLE 31 31 mmDP_AUX2_AUX_LS_DATA 0 0x17a5 2 0 2 AUX_LS_DATA 8 15 AUX_LS_INDEX 16 20 mmDP_AUX2_AUX_DPHY_TX_REF_CONTROL 0 0x17a6 3 0 2 AUX_TX_REF_SEL 0 0 AUX_TX_RATE 4 5 AUX_TX_REF_DIV 16 24 mmDP_AUX2_AUX_DPHY_TX_CONTROL 0 0x17a7 3 0 2 AUX_TX_PRECHARGE_LEN 0 2 AUX_TX_PRECHARGE_SYMBOLS 8 13 AUX_MODE_DET_CHECK_DELAY 16 18 mmDP_AUX2_AUX_DPHY_RX_CONTROL0 0 0x17a8 10 0 2 AUX_RX_START_WINDOW 4 6 AUX_RX_RECEIVE_WINDOW 8 10 AUX_RX_HALF_SYM_DETECT_LEN 12 13 AUX_RX_TRANSITION_FILTER_EN 16 16 AUX_RX_ALLOW_BELOW_THRESHOLD_PHASE_DETECT 17 17 AUX_RX_ALLOW_BELOW_THRESHOLD_START 18 18 AUX_RX_ALLOW_BELOW_THRESHOLD_STOP 19 19 AUX_RX_PHASE_DETECT_LEN 20 21 AUX_RX_TIMEOUT_LEN 24 26 AUX_RX_DETECTION_THRESHOLD 28 30 mmDP_AUX2_AUX_DPHY_RX_CONTROL1 0 0x17a9 1 0 2 AUX_RX_PRECHARGE_SKIP 0 7 mmDP_AUX2_AUX_DPHY_TX_STATUS 0 0x17aa 3 0 2 AUX_TX_ACTIVE 0 0 AUX_TX_STATE 4 6 AUX_TX_HALF_SYM_PERIOD 16 24 mmDP_AUX2_AUX_DPHY_RX_STATUS 0 0x17ab 4 0 2 AUX_RX_STATE 0 2 AUX_RX_SYNC_VALID_COUNT 8 12 AUX_RX_HALF_SYM_PERIOD_FRACT 16 20 AUX_RX_HALF_SYM_PERIOD 21 29 mmDP_AUX2_AUX_GTC_SYNC_ERROR_CONTROL 0 0x17ad 4 0 2 AUX_GTC_POTENTIAL_ERROR_THRESHOLD 0 4 AUX_GTC_DEFINITE_ERROR_THRESHOLD 8 12 AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_LEN 16 17 AUX_GTC_SYNC_NUM_RETRY_FOR_LOCK_MAINT 20 21 mmDP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS 0 0x17ae 12 0 2 AUX_GTC_SYNC_LOCK_ACQ_COMPLETE 0 0 AUX_GTC_SYNC_LOCK_LOST 4 4 AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_OCCURRED 8 8 AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_STATE 9 12 AUX_GTC_SYNC_PHASE_ADJUST_TIME_VIOL 16 16 AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED 20 20 AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED_ACK 21 21 AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED 22 22 AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED_ACK 23 23 AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED 24 24 AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED_ACK 25 25 AUX_GTC_SYNC_CTRL_STATE 28 31 mmDP_AUX2_AUX_GTC_SYNC_STATUS 0 0x17af 19 0 2 AUX_GTC_SYNC_DONE 0 0 AUX_GTC_SYNC_REQ 1 1 AUX_GTC_SYNC_RX_TIMEOUT_STATE 4 6 AUX_GTC_SYNC_TIMEOUT 7 7 AUX_GTC_SYNC_RX_OVERFLOW 8 8 AUX_GTC_SYNC_HPD_DISCON 9 9 AUX_GTC_SYNC_RX_PARTIAL_BYTE 10 10 AUX_GTC_SYNC_NON_AUX_MODE 11 11 AUX_GTC_SYNC_RX_MIN_COUNT_VIOL 12 12 AUX_GTC_SYNC_RX_INVALID_STOP 14 14 AUX_GTC_SYNC_RX_SYNC_INVALID_L 17 17 AUX_GTC_SYNC_RX_SYNC_INVALID_H 18 18 AUX_GTC_SYNC_RX_INVALID_START 19 19 AUX_GTC_SYNC_RX_RECV_NO_DET 20 20 AUX_GTC_SYNC_RX_RECV_INVALID_H 22 22 AUX_GTC_SYNC_RX_RECV_INVALID_L 23 23 AUX_GTC_SYNC_REPLY_BYTE_COUNT 24 28 AUX_GTC_SYNC_NACKED 29 29 AUX_GTC_MASTER_REQ_BY_RX 30 30 mmDP_AUX3_AUX_CONTROL 0 0x17ba 13 0 2 AUX_EN 0 0 AUX_RESET 4 4 AUX_RESET_DONE 5 5 AUX_LS_READ_EN 8 8 AUX_LS_UPDATE_DISABLE 12 12 AUX_IGNORE_HPD_DISCON 16 16 AUX_MODE_DET_EN 18 18 AUX_HPD_SEL 20 22 AUX_IMPCAL_REQ_EN 24 24 AUX_TEST_MODE 28 28 AUX_DEGLITCH_EN 29 29 SPARE_0 30 30 SPARE_1 31 31 mmDP_AUX3_AUX_SW_CONTROL 0 0x17bb 4 0 2 AUX_SW_GO 0 0 AUX_LS_READ_TRIG 2 2 AUX_SW_START_DELAY 4 7 AUX_SW_WR_BYTES 16 20 mmDP_AUX3_AUX_ARB_CONTROL 0 0x17bc 10 0 2 AUX_ARB_PRIORITY 0 1 AUX_REG_RW_CNTL_STATUS 2 3 AUX_NO_QUEUED_SW_GO 8 8 AUX_NO_QUEUED_LS_GO 10 10 AUX_SW_USE_AUX_REG_REQ 16 16 AUX_SW_PENDING_USE_AUX_REG_REQ 16 16 AUX_SW_DONE_USING_AUX_REG 17 17 AUX_DMCU_USE_AUX_REG_REQ 24 24 AUX_DMCU_PENDING_USE_AUX_REG_REQ 24 24 AUX_DMCU_DONE_USING_AUX_REG 25 25 mmDP_AUX3_AUX_INTERRUPT_CONTROL 0 0x17bd 12 0 2 AUX_SW_DONE_INT 0 0 AUX_SW_DONE_ACK 1 1 AUX_SW_DONE_MASK 2 2 AUX_LS_DONE_INT 4 4 AUX_LS_DONE_ACK 5 5 AUX_LS_DONE_MASK 6 6 AUX_GTC_SYNC_LOCK_DONE_INT 8 8 AUX_GTC_SYNC_LOCK_DONE_ACK 9 9 AUX_GTC_SYNC_LOCK_DONE_INT_MASK 10 10 AUX_GTC_SYNC_ERROR_INT 12 12 AUX_GTC_SYNC_ERROR_ACK 13 13 AUX_GTC_SYNC_ERROR_INT_MASK 14 14 mmDP_AUX3_AUX_SW_STATUS 0 0x17be 18 0 2 AUX_SW_DONE 0 0 AUX_SW_REQ 1 1 AUX_SW_RX_TIMEOUT_STATE 4 6 AUX_SW_RX_TIMEOUT 7 7 AUX_SW_RX_OVERFLOW 8 8 AUX_SW_HPD_DISCON 9 9 AUX_SW_RX_PARTIAL_BYTE 10 10 AUX_SW_NON_AUX_MODE 11 11 AUX_SW_RX_MIN_COUNT_VIOL 12 12 AUX_SW_RX_INVALID_STOP 14 14 AUX_SW_RX_SYNC_INVALID_L 17 17 AUX_SW_RX_SYNC_INVALID_H 18 18 AUX_SW_RX_INVALID_START 19 19 AUX_SW_RX_RECV_NO_DET 20 20 AUX_SW_RX_RECV_INVALID_H 22 22 AUX_SW_RX_RECV_INVALID_L 23 23 AUX_SW_REPLY_BYTE_COUNT 24 28 AUX_ARB_STATUS 30 31 mmDP_AUX3_AUX_LS_STATUS 0 0x17bf 20 0 2 AUX_LS_DONE 0 0 AUX_LS_REQ 1 1 AUX_LS_RX_TIMEOUT_STATE 4 6 AUX_LS_RX_TIMEOUT 7 7 AUX_LS_RX_OVERFLOW 8 8 AUX_LS_HPD_DISCON 9 9 AUX_LS_RX_PARTIAL_BYTE 10 10 AUX_LS_NON_AUX_MODE 11 11 AUX_LS_RX_MIN_COUNT_VIOL 12 12 AUX_LS_RX_INVALID_STOP 14 14 AUX_LS_RX_SYNC_INVALID_L 17 17 AUX_LS_RX_SYNC_INVALID_H 18 18 AUX_LS_RX_INVALID_START 19 19 AUX_LS_RX_RECV_NO_DET 20 20 AUX_LS_RX_RECV_INVALID_H 22 22 AUX_LS_RX_RECV_INVALID_L 23 23 AUX_LS_REPLY_BYTE_COUNT 24 28 AUX_LS_CP_IRQ 29 29 AUX_LS_UPDATED 30 30 AUX_LS_UPDATED_ACK 31 31 mmDP_AUX3_AUX_SW_DATA 0 0x17c0 4 0 2 AUX_SW_DATA_RW 0 0 AUX_SW_DATA 8 15 AUX_SW_INDEX 16 20 AUX_SW_AUTOINCREMENT_DISABLE 31 31 mmDP_AUX3_AUX_LS_DATA 0 0x17c1 2 0 2 AUX_LS_DATA 8 15 AUX_LS_INDEX 16 20 mmDP_AUX3_AUX_DPHY_TX_REF_CONTROL 0 0x17c2 3 0 2 AUX_TX_REF_SEL 0 0 AUX_TX_RATE 4 5 AUX_TX_REF_DIV 16 24 mmDP_AUX3_AUX_DPHY_TX_CONTROL 0 0x17c3 3 0 2 AUX_TX_PRECHARGE_LEN 0 2 AUX_TX_PRECHARGE_SYMBOLS 8 13 AUX_MODE_DET_CHECK_DELAY 16 18 mmDP_AUX3_AUX_DPHY_RX_CONTROL0 0 0x17c4 10 0 2 AUX_RX_START_WINDOW 4 6 AUX_RX_RECEIVE_WINDOW 8 10 AUX_RX_HALF_SYM_DETECT_LEN 12 13 AUX_RX_TRANSITION_FILTER_EN 16 16 AUX_RX_ALLOW_BELOW_THRESHOLD_PHASE_DETECT 17 17 AUX_RX_ALLOW_BELOW_THRESHOLD_START 18 18 AUX_RX_ALLOW_BELOW_THRESHOLD_STOP 19 19 AUX_RX_PHASE_DETECT_LEN 20 21 AUX_RX_TIMEOUT_LEN 24 26 AUX_RX_DETECTION_THRESHOLD 28 30 mmDP_AUX3_AUX_DPHY_RX_CONTROL1 0 0x17c5 1 0 2 AUX_RX_PRECHARGE_SKIP 0 7 mmDP_AUX3_AUX_DPHY_TX_STATUS 0 0x17c6 3 0 2 AUX_TX_ACTIVE 0 0 AUX_TX_STATE 4 6 AUX_TX_HALF_SYM_PERIOD 16 24 mmDP_AUX3_AUX_DPHY_RX_STATUS 0 0x17c7 4 0 2 AUX_RX_STATE 0 2 AUX_RX_SYNC_VALID_COUNT 8 12 AUX_RX_HALF_SYM_PERIOD_FRACT 16 20 AUX_RX_HALF_SYM_PERIOD 21 29 mmDP_AUX3_AUX_GTC_SYNC_ERROR_CONTROL 0 0x17c9 4 0 2 AUX_GTC_POTENTIAL_ERROR_THRESHOLD 0 4 AUX_GTC_DEFINITE_ERROR_THRESHOLD 8 12 AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_LEN 16 17 AUX_GTC_SYNC_NUM_RETRY_FOR_LOCK_MAINT 20 21 mmDP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS 0 0x17ca 12 0 2 AUX_GTC_SYNC_LOCK_ACQ_COMPLETE 0 0 AUX_GTC_SYNC_LOCK_LOST 4 4 AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_OCCURRED 8 8 AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_STATE 9 12 AUX_GTC_SYNC_PHASE_ADJUST_TIME_VIOL 16 16 AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED 20 20 AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED_ACK 21 21 AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED 22 22 AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED_ACK 23 23 AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED 24 24 AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED_ACK 25 25 AUX_GTC_SYNC_CTRL_STATE 28 31 mmDP_AUX3_AUX_GTC_SYNC_STATUS 0 0x17cb 19 0 2 AUX_GTC_SYNC_DONE 0 0 AUX_GTC_SYNC_REQ 1 1 AUX_GTC_SYNC_RX_TIMEOUT_STATE 4 6 AUX_GTC_SYNC_TIMEOUT 7 7 AUX_GTC_SYNC_RX_OVERFLOW 8 8 AUX_GTC_SYNC_HPD_DISCON 9 9 AUX_GTC_SYNC_RX_PARTIAL_BYTE 10 10 AUX_GTC_SYNC_NON_AUX_MODE 11 11 AUX_GTC_SYNC_RX_MIN_COUNT_VIOL 12 12 AUX_GTC_SYNC_RX_INVALID_STOP 14 14 AUX_GTC_SYNC_RX_SYNC_INVALID_L 17 17 AUX_GTC_SYNC_RX_SYNC_INVALID_H 18 18 AUX_GTC_SYNC_RX_INVALID_START 19 19 AUX_GTC_SYNC_RX_RECV_NO_DET 20 20 AUX_GTC_SYNC_RX_RECV_INVALID_H 22 22 AUX_GTC_SYNC_RX_RECV_INVALID_L 23 23 AUX_GTC_SYNC_REPLY_BYTE_COUNT 24 28 AUX_GTC_SYNC_NACKED 29 29 AUX_GTC_MASTER_REQ_BY_RX 30 30 mmDP_AUX4_AUX_CONTROL 0 0x17d6 13 0 2 AUX_EN 0 0 AUX_RESET 4 4 AUX_RESET_DONE 5 5 AUX_LS_READ_EN 8 8 AUX_LS_UPDATE_DISABLE 12 12 AUX_IGNORE_HPD_DISCON 16 16 AUX_MODE_DET_EN 18 18 AUX_HPD_SEL 20 22 AUX_IMPCAL_REQ_EN 24 24 AUX_TEST_MODE 28 28 AUX_DEGLITCH_EN 29 29 SPARE_0 30 30 SPARE_1 31 31 mmDP_AUX4_AUX_SW_CONTROL 0 0x17d7 4 0 2 AUX_SW_GO 0 0 AUX_LS_READ_TRIG 2 2 AUX_SW_START_DELAY 4 7 AUX_SW_WR_BYTES 16 20 mmDP_AUX4_AUX_ARB_CONTROL 0 0x17d8 10 0 2 AUX_ARB_PRIORITY 0 1 AUX_REG_RW_CNTL_STATUS 2 3 AUX_NO_QUEUED_SW_GO 8 8 AUX_NO_QUEUED_LS_GO 10 10 AUX_SW_USE_AUX_REG_REQ 16 16 AUX_SW_PENDING_USE_AUX_REG_REQ 16 16 AUX_SW_DONE_USING_AUX_REG 17 17 AUX_DMCU_USE_AUX_REG_REQ 24 24 AUX_DMCU_PENDING_USE_AUX_REG_REQ 24 24 AUX_DMCU_DONE_USING_AUX_REG 25 25 mmDP_AUX4_AUX_INTERRUPT_CONTROL 0 0x17d9 12 0 2 AUX_SW_DONE_INT 0 0 AUX_SW_DONE_ACK 1 1 AUX_SW_DONE_MASK 2 2 AUX_LS_DONE_INT 4 4 AUX_LS_DONE_ACK 5 5 AUX_LS_DONE_MASK 6 6 AUX_GTC_SYNC_LOCK_DONE_INT 8 8 AUX_GTC_SYNC_LOCK_DONE_ACK 9 9 AUX_GTC_SYNC_LOCK_DONE_INT_MASK 10 10 AUX_GTC_SYNC_ERROR_INT 12 12 AUX_GTC_SYNC_ERROR_ACK 13 13 AUX_GTC_SYNC_ERROR_INT_MASK 14 14 mmDP_AUX4_AUX_SW_STATUS 0 0x17da 18 0 2 AUX_SW_DONE 0 0 AUX_SW_REQ 1 1 AUX_SW_RX_TIMEOUT_STATE 4 6 AUX_SW_RX_TIMEOUT 7 7 AUX_SW_RX_OVERFLOW 8 8 AUX_SW_HPD_DISCON 9 9 AUX_SW_RX_PARTIAL_BYTE 10 10 AUX_SW_NON_AUX_MODE 11 11 AUX_SW_RX_MIN_COUNT_VIOL 12 12 AUX_SW_RX_INVALID_STOP 14 14 AUX_SW_RX_SYNC_INVALID_L 17 17 AUX_SW_RX_SYNC_INVALID_H 18 18 AUX_SW_RX_INVALID_START 19 19 AUX_SW_RX_RECV_NO_DET 20 20 AUX_SW_RX_RECV_INVALID_H 22 22 AUX_SW_RX_RECV_INVALID_L 23 23 AUX_SW_REPLY_BYTE_COUNT 24 28 AUX_ARB_STATUS 30 31 mmDP_AUX4_AUX_LS_STATUS 0 0x17db 20 0 2 AUX_LS_DONE 0 0 AUX_LS_REQ 1 1 AUX_LS_RX_TIMEOUT_STATE 4 6 AUX_LS_RX_TIMEOUT 7 7 AUX_LS_RX_OVERFLOW 8 8 AUX_LS_HPD_DISCON 9 9 AUX_LS_RX_PARTIAL_BYTE 10 10 AUX_LS_NON_AUX_MODE 11 11 AUX_LS_RX_MIN_COUNT_VIOL 12 12 AUX_LS_RX_INVALID_STOP 14 14 AUX_LS_RX_SYNC_INVALID_L 17 17 AUX_LS_RX_SYNC_INVALID_H 18 18 AUX_LS_RX_INVALID_START 19 19 AUX_LS_RX_RECV_NO_DET 20 20 AUX_LS_RX_RECV_INVALID_H 22 22 AUX_LS_RX_RECV_INVALID_L 23 23 AUX_LS_REPLY_BYTE_COUNT 24 28 AUX_LS_CP_IRQ 29 29 AUX_LS_UPDATED 30 30 AUX_LS_UPDATED_ACK 31 31 mmDP_AUX4_AUX_SW_DATA 0 0x17dc 4 0 2 AUX_SW_DATA_RW 0 0 AUX_SW_DATA 8 15 AUX_SW_INDEX 16 20 AUX_SW_AUTOINCREMENT_DISABLE 31 31 mmDP_AUX4_AUX_LS_DATA 0 0x17dd 2 0 2 AUX_LS_DATA 8 15 AUX_LS_INDEX 16 20 mmDP_AUX4_AUX_DPHY_TX_REF_CONTROL 0 0x17de 3 0 2 AUX_TX_REF_SEL 0 0 AUX_TX_RATE 4 5 AUX_TX_REF_DIV 16 24 mmDP_AUX4_AUX_DPHY_TX_CONTROL 0 0x17df 3 0 2 AUX_TX_PRECHARGE_LEN 0 2 AUX_TX_PRECHARGE_SYMBOLS 8 13 AUX_MODE_DET_CHECK_DELAY 16 18 mmDP_AUX4_AUX_DPHY_RX_CONTROL0 0 0x17e0 10 0 2 AUX_RX_START_WINDOW 4 6 AUX_RX_RECEIVE_WINDOW 8 10 AUX_RX_HALF_SYM_DETECT_LEN 12 13 AUX_RX_TRANSITION_FILTER_EN 16 16 AUX_RX_ALLOW_BELOW_THRESHOLD_PHASE_DETECT 17 17 AUX_RX_ALLOW_BELOW_THRESHOLD_START 18 18 AUX_RX_ALLOW_BELOW_THRESHOLD_STOP 19 19 AUX_RX_PHASE_DETECT_LEN 20 21 AUX_RX_TIMEOUT_LEN 24 26 AUX_RX_DETECTION_THRESHOLD 28 30 mmDP_AUX4_AUX_DPHY_RX_CONTROL1 0 0x17e1 1 0 2 AUX_RX_PRECHARGE_SKIP 0 7 mmDP_AUX4_AUX_DPHY_TX_STATUS 0 0x17e2 3 0 2 AUX_TX_ACTIVE 0 0 AUX_TX_STATE 4 6 AUX_TX_HALF_SYM_PERIOD 16 24 mmDP_AUX4_AUX_DPHY_RX_STATUS 0 0x17e3 4 0 2 AUX_RX_STATE 0 2 AUX_RX_SYNC_VALID_COUNT 8 12 AUX_RX_HALF_SYM_PERIOD_FRACT 16 20 AUX_RX_HALF_SYM_PERIOD 21 29 mmDP_AUX4_AUX_GTC_SYNC_ERROR_CONTROL 0 0x17e5 4 0 2 AUX_GTC_POTENTIAL_ERROR_THRESHOLD 0 4 AUX_GTC_DEFINITE_ERROR_THRESHOLD 8 12 AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_LEN 16 17 AUX_GTC_SYNC_NUM_RETRY_FOR_LOCK_MAINT 20 21 mmDP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS 0 0x17e6 12 0 2 AUX_GTC_SYNC_LOCK_ACQ_COMPLETE 0 0 AUX_GTC_SYNC_LOCK_LOST 4 4 AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_OCCURRED 8 8 AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_STATE 9 12 AUX_GTC_SYNC_PHASE_ADJUST_TIME_VIOL 16 16 AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED 20 20 AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED_ACK 21 21 AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED 22 22 AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED_ACK 23 23 AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED 24 24 AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED_ACK 25 25 AUX_GTC_SYNC_CTRL_STATE 28 31 mmDP_AUX4_AUX_GTC_SYNC_STATUS 0 0x17e7 19 0 2 AUX_GTC_SYNC_DONE 0 0 AUX_GTC_SYNC_REQ 1 1 AUX_GTC_SYNC_RX_TIMEOUT_STATE 4 6 AUX_GTC_SYNC_TIMEOUT 7 7 AUX_GTC_SYNC_RX_OVERFLOW 8 8 AUX_GTC_SYNC_HPD_DISCON 9 9 AUX_GTC_SYNC_RX_PARTIAL_BYTE 10 10 AUX_GTC_SYNC_NON_AUX_MODE 11 11 AUX_GTC_SYNC_RX_MIN_COUNT_VIOL 12 12 AUX_GTC_SYNC_RX_INVALID_STOP 14 14 AUX_GTC_SYNC_RX_SYNC_INVALID_L 17 17 AUX_GTC_SYNC_RX_SYNC_INVALID_H 18 18 AUX_GTC_SYNC_RX_INVALID_START 19 19 AUX_GTC_SYNC_RX_RECV_NO_DET 20 20 AUX_GTC_SYNC_RX_RECV_INVALID_H 22 22 AUX_GTC_SYNC_RX_RECV_INVALID_L 23 23 AUX_GTC_SYNC_REPLY_BYTE_COUNT 24 28 AUX_GTC_SYNC_NACKED 29 29 AUX_GTC_MASTER_REQ_BY_RX 30 30 mmDP_AUX5_AUX_CONTROL 0 0x17f2 13 0 2 AUX_EN 0 0 AUX_RESET 4 4 AUX_RESET_DONE 5 5 AUX_LS_READ_EN 8 8 AUX_LS_UPDATE_DISABLE 12 12 AUX_IGNORE_HPD_DISCON 16 16 AUX_MODE_DET_EN 18 18 AUX_HPD_SEL 20 22 AUX_IMPCAL_REQ_EN 24 24 AUX_TEST_MODE 28 28 AUX_DEGLITCH_EN 29 29 SPARE_0 30 30 SPARE_1 31 31 mmDP_AUX5_AUX_SW_CONTROL 0 0x17f3 4 0 2 AUX_SW_GO 0 0 AUX_LS_READ_TRIG 2 2 AUX_SW_START_DELAY 4 7 AUX_SW_WR_BYTES 16 20 mmDP_AUX5_AUX_ARB_CONTROL 0 0x17f4 10 0 2 AUX_ARB_PRIORITY 0 1 AUX_REG_RW_CNTL_STATUS 2 3 AUX_NO_QUEUED_SW_GO 8 8 AUX_NO_QUEUED_LS_GO 10 10 AUX_SW_USE_AUX_REG_REQ 16 16 AUX_SW_PENDING_USE_AUX_REG_REQ 16 16 AUX_SW_DONE_USING_AUX_REG 17 17 AUX_DMCU_USE_AUX_REG_REQ 24 24 AUX_DMCU_PENDING_USE_AUX_REG_REQ 24 24 AUX_DMCU_DONE_USING_AUX_REG 25 25 mmDP_AUX5_AUX_INTERRUPT_CONTROL 0 0x17f5 12 0 2 AUX_SW_DONE_INT 0 0 AUX_SW_DONE_ACK 1 1 AUX_SW_DONE_MASK 2 2 AUX_LS_DONE_INT 4 4 AUX_LS_DONE_ACK 5 5 AUX_LS_DONE_MASK 6 6 AUX_GTC_SYNC_LOCK_DONE_INT 8 8 AUX_GTC_SYNC_LOCK_DONE_ACK 9 9 AUX_GTC_SYNC_LOCK_DONE_INT_MASK 10 10 AUX_GTC_SYNC_ERROR_INT 12 12 AUX_GTC_SYNC_ERROR_ACK 13 13 AUX_GTC_SYNC_ERROR_INT_MASK 14 14 mmDP_AUX5_AUX_SW_STATUS 0 0x17f6 18 0 2 AUX_SW_DONE 0 0 AUX_SW_REQ 1 1 AUX_SW_RX_TIMEOUT_STATE 4 6 AUX_SW_RX_TIMEOUT 7 7 AUX_SW_RX_OVERFLOW 8 8 AUX_SW_HPD_DISCON 9 9 AUX_SW_RX_PARTIAL_BYTE 10 10 AUX_SW_NON_AUX_MODE 11 11 AUX_SW_RX_MIN_COUNT_VIOL 12 12 AUX_SW_RX_INVALID_STOP 14 14 AUX_SW_RX_SYNC_INVALID_L 17 17 AUX_SW_RX_SYNC_INVALID_H 18 18 AUX_SW_RX_INVALID_START 19 19 AUX_SW_RX_RECV_NO_DET 20 20 AUX_SW_RX_RECV_INVALID_H 22 22 AUX_SW_RX_RECV_INVALID_L 23 23 AUX_SW_REPLY_BYTE_COUNT 24 28 AUX_ARB_STATUS 30 31 mmDP_AUX5_AUX_LS_STATUS 0 0x17f7 20 0 2 AUX_LS_DONE 0 0 AUX_LS_REQ 1 1 AUX_LS_RX_TIMEOUT_STATE 4 6 AUX_LS_RX_TIMEOUT 7 7 AUX_LS_RX_OVERFLOW 8 8 AUX_LS_HPD_DISCON 9 9 AUX_LS_RX_PARTIAL_BYTE 10 10 AUX_LS_NON_AUX_MODE 11 11 AUX_LS_RX_MIN_COUNT_VIOL 12 12 AUX_LS_RX_INVALID_STOP 14 14 AUX_LS_RX_SYNC_INVALID_L 17 17 AUX_LS_RX_SYNC_INVALID_H 18 18 AUX_LS_RX_INVALID_START 19 19 AUX_LS_RX_RECV_NO_DET 20 20 AUX_LS_RX_RECV_INVALID_H 22 22 AUX_LS_RX_RECV_INVALID_L 23 23 AUX_LS_REPLY_BYTE_COUNT 24 28 AUX_LS_CP_IRQ 29 29 AUX_LS_UPDATED 30 30 AUX_LS_UPDATED_ACK 31 31 mmDP_AUX5_AUX_SW_DATA 0 0x17f8 4 0 2 AUX_SW_DATA_RW 0 0 AUX_SW_DATA 8 15 AUX_SW_INDEX 16 20 AUX_SW_AUTOINCREMENT_DISABLE 31 31 mmDP_AUX5_AUX_LS_DATA 0 0x17f9 2 0 2 AUX_LS_DATA 8 15 AUX_LS_INDEX 16 20 mmDP_AUX5_AUX_DPHY_TX_REF_CONTROL 0 0x17fa 3 0 2 AUX_TX_REF_SEL 0 0 AUX_TX_RATE 4 5 AUX_TX_REF_DIV 16 24 mmDP_AUX5_AUX_DPHY_TX_CONTROL 0 0x17fb 3 0 2 AUX_TX_PRECHARGE_LEN 0 2 AUX_TX_PRECHARGE_SYMBOLS 8 13 AUX_MODE_DET_CHECK_DELAY 16 18 mmDP_AUX5_AUX_DPHY_RX_CONTROL0 0 0x17fc 10 0 2 AUX_RX_START_WINDOW 4 6 AUX_RX_RECEIVE_WINDOW 8 10 AUX_RX_HALF_SYM_DETECT_LEN 12 13 AUX_RX_TRANSITION_FILTER_EN 16 16 AUX_RX_ALLOW_BELOW_THRESHOLD_PHASE_DETECT 17 17 AUX_RX_ALLOW_BELOW_THRESHOLD_START 18 18 AUX_RX_ALLOW_BELOW_THRESHOLD_STOP 19 19 AUX_RX_PHASE_DETECT_LEN 20 21 AUX_RX_TIMEOUT_LEN 24 26 AUX_RX_DETECTION_THRESHOLD 28 30 mmDP_AUX5_AUX_DPHY_RX_CONTROL1 0 0x17fd 1 0 2 AUX_RX_PRECHARGE_SKIP 0 7 mmDP_AUX5_AUX_DPHY_TX_STATUS 0 0x17fe 3 0 2 AUX_TX_ACTIVE 0 0 AUX_TX_STATE 4 6 AUX_TX_HALF_SYM_PERIOD 16 24 mmDP_AUX5_AUX_DPHY_RX_STATUS 0 0x17ff 4 0 2 AUX_RX_STATE 0 2 AUX_RX_SYNC_VALID_COUNT 8 12 AUX_RX_HALF_SYM_PERIOD_FRACT 16 20 AUX_RX_HALF_SYM_PERIOD 21 29 mmDP_AUX5_AUX_GTC_SYNC_ERROR_CONTROL 0 0x1801 4 0 2 AUX_GTC_POTENTIAL_ERROR_THRESHOLD 0 4 AUX_GTC_DEFINITE_ERROR_THRESHOLD 8 12 AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_LEN 16 17 AUX_GTC_SYNC_NUM_RETRY_FOR_LOCK_MAINT 20 21 mmDP_AUX5_AUX_GTC_SYNC_CONTROLLER_STATUS 0 0x1802 12 0 2 AUX_GTC_SYNC_LOCK_ACQ_COMPLETE 0 0 AUX_GTC_SYNC_LOCK_LOST 4 4 AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_OCCURRED 8 8 AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_STATE 9 12 AUX_GTC_SYNC_PHASE_ADJUST_TIME_VIOL 16 16 AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED 20 20 AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED_ACK 21 21 AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED 22 22 AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED_ACK 23 23 AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED 24 24 AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED_ACK 25 25 AUX_GTC_SYNC_CTRL_STATE 28 31 mmDP_AUX5_AUX_GTC_SYNC_STATUS 0 0x1803 19 0 2 AUX_GTC_SYNC_DONE 0 0 AUX_GTC_SYNC_REQ 1 1 AUX_GTC_SYNC_RX_TIMEOUT_STATE 4 6 AUX_GTC_SYNC_TIMEOUT 7 7 AUX_GTC_SYNC_RX_OVERFLOW 8 8 AUX_GTC_SYNC_HPD_DISCON 9 9 AUX_GTC_SYNC_RX_PARTIAL_BYTE 10 10 AUX_GTC_SYNC_NON_AUX_MODE 11 11 AUX_GTC_SYNC_RX_MIN_COUNT_VIOL 12 12 AUX_GTC_SYNC_RX_INVALID_STOP 14 14 AUX_GTC_SYNC_RX_SYNC_INVALID_L 17 17 AUX_GTC_SYNC_RX_SYNC_INVALID_H 18 18 AUX_GTC_SYNC_RX_INVALID_START 19 19 AUX_GTC_SYNC_RX_RECV_NO_DET 20 20 AUX_GTC_SYNC_RX_RECV_INVALID_H 22 22 AUX_GTC_SYNC_RX_RECV_INVALID_L 23 23 AUX_GTC_SYNC_REPLY_BYTE_COUNT 24 28 AUX_GTC_SYNC_NACKED 29 29 AUX_GTC_MASTER_REQ_BY_RX 30 30 mmDIG0_DIG_FE_CNTL 0 0x187e 7 0 2 DIG_SOURCE_SELECT 0 2 DIG_STEREOSYNC_SELECT 4 6 DIG_STEREOSYNC_GATE_EN 8 8 DIG_START 10 10 DIG_SYMCLK_FE_ON 24 24 TMDS_PIXEL_ENCODING 28 28 TMDS_COLOR_FORMAT 30 31 mmDIG0_DIG_OUTPUT_CRC_CNTL 0 0x187f 3 0 2 DIG_OUTPUT_CRC_EN 0 0 DIG_OUTPUT_CRC_LINK_SEL 4 4 DIG_OUTPUT_CRC_DATA_SEL 8 9 mmDIG0_DIG_OUTPUT_CRC_RESULT 0 0x1880 1 0 2 DIG_OUTPUT_CRC_RESULT 0 29 mmDIG0_DIG_CLOCK_PATTERN 0 0x1881 1 0 2 DIG_CLOCK_PATTERN 0 9 mmDIG0_DIG_TEST_PATTERN 0 0x1882 6 0 2 DIG_TEST_PATTERN_OUT_EN 0 0 DIG_HALF_CLOCK_PATTERN_SEL 1 1 DIG_RANDOM_PATTERN_OUT_EN 4 4 DIG_RANDOM_PATTERN_RESET 5 5 DIG_TEST_PATTERN_EXTERNAL_RESET_EN 6 6 DIG_STATIC_TEST_PATTERN 16 25 mmDIG0_DIG_RANDOM_PATTERN_SEED 0 0x1883 2 0 2 DIG_RANDOM_PATTERN_SEED 0 23 DIG_RAN_PAT_DURING_DE_ONLY 24 24 mmDIG0_DIG_FIFO_STATUS 0 0x1884 11 0 2 DIG_FIFO_LEVEL_ERROR 0 0 DIG_FIFO_USE_OVERWRITE_LEVEL 1 1 DIG_FIFO_OVERWRITE_LEVEL 2 7 DIG_FIFO_ERROR_ACK 8 8 DIG_FIFO_CAL_AVERAGE_LEVEL 10 15 DIG_FIFO_MAXIMUM_LEVEL 16 20 DIG_FIFO_MINIMUM_LEVEL 22 25 DIG_FIFO_READ_CLOCK_SRC 26 26 DIG_FIFO_CALIBRATED 29 29 DIG_FIFO_FORCE_RECAL_AVERAGE 30 30 DIG_FIFO_FORCE_RECOMP_MINMAX 31 31 mmDIG0_HDMI_CONTROL 0 0x1887 9 0 2 HDMI_KEEPOUT_MODE 0 0 HDMI_DATA_SCRAMBLE_EN 1 1 HDMI_CLOCK_CHANNEL_RATE 2 2 HDMI_NO_EXTRA_NULL_PACKET_FILLED 3 3 HDMI_PACKET_GEN_VERSION 4 4 HDMI_ERROR_ACK 8 8 HDMI_ERROR_MASK 9 9 HDMI_DEEP_COLOR_ENABLE 24 24 HDMI_DEEP_COLOR_DEPTH 28 29 mmDIG0_HDMI_STATUS 0 0x1888 4 0 2 HDMI_ACTIVE_AVMUTE 0 0 HDMI_AUDIO_PACKET_ERROR 16 16 HDMI_VBI_PACKET_ERROR 20 20 HDMI_ERROR_INT 27 27 mmDIG0_HDMI_AUDIO_PACKET_CONTROL 0 0x1889 2 0 2 HDMI_AUDIO_DELAY_EN 4 5 HDMI_AUDIO_PACKETS_PER_LINE 16 20 mmDIG0_HDMI_ACR_PACKET_CONTROL 0 0x188a 7 0 2 HDMI_ACR_SEND 0 0 HDMI_ACR_CONT 1 1 HDMI_ACR_SELECT 4 5 HDMI_ACR_SOURCE 8 8 HDMI_ACR_AUTO_SEND 12 12 HDMI_ACR_N_MULTIPLE 16 18 HDMI_ACR_AUDIO_PRIORITY 31 31 mmDIG0_HDMI_VBI_PACKET_CONTROL 0 0x188b 6 0 2 HDMI_NULL_SEND 0 0 HDMI_GC_SEND 4 4 HDMI_GC_CONT 5 5 HDMI_ISRC_SEND 8 8 HDMI_ISRC_CONT 9 9 HDMI_ISRC_LINE 16 21 mmDIG0_HDMI_INFOFRAME_CONTROL0 0 0x188c 6 0 2 HDMI_AVI_INFO_SEND 0 0 HDMI_AVI_INFO_CONT 1 1 HDMI_AUDIO_INFO_SEND 4 4 HDMI_AUDIO_INFO_CONT 5 5 HDMI_MPEG_INFO_SEND 8 8 HDMI_MPEG_INFO_CONT 9 9 mmDIG0_HDMI_INFOFRAME_CONTROL1 0 0x188d 3 0 2 HDMI_AVI_INFO_LINE 0 5 HDMI_AUDIO_INFO_LINE 8 13 HDMI_MPEG_INFO_LINE 16 21 mmDIG0_HDMI_GENERIC_PACKET_CONTROL0 0 0x188e 6 0 2 HDMI_GENERIC0_SEND 0 0 HDMI_GENERIC0_CONT 1 1 HDMI_GENERIC1_SEND 4 4 HDMI_GENERIC1_CONT 5 5 HDMI_GENERIC0_LINE 16 21 HDMI_GENERIC1_LINE 24 29 mmDIG0_AFMT_INTERRUPT_STATUS 0 0x188f 0 0 2 mmDIG0_HDMI_GC 0 0x1891 5 0 2 HDMI_GC_AVMUTE 0 0 HDMI_GC_AVMUTE_CONT 2 2 HDMI_DEFAULT_PHASE 4 4 HDMI_PACKING_PHASE 8 11 HDMI_PACKING_PHASE_OVERRIDE 12 12 mmDIG0_AFMT_AUDIO_PACKET_CONTROL2 0 0x1892 6 0 2 AFMT_AUDIO_LAYOUT_OVRD 0 0 AFMT_AUDIO_LAYOUT_SELECT 1 1 AFMT_AUDIO_CHANNEL_ENABLE 8 15 AFMT_DP_AUDIO_STREAM_ID 16 23 AFMT_HBR_ENABLE_OVRD 24 24 AFMT_60958_OSF_OVRD 28 28 mmDIG0_AFMT_ISRC1_0 0 0x1893 3 0 2 AFMT_ISRC_STATUS 0 2 AFMT_ISRC_CONTINUE 6 6 AFMT_ISRC_VALID 7 7 mmDIG0_AFMT_ISRC1_1 0 0x1894 4 0 2 AFMT_UPC_EAN_ISRC0 0 7 AFMT_UPC_EAN_ISRC1 8 15 AFMT_UPC_EAN_ISRC2 16 23 AFMT_UPC_EAN_ISRC3 24 31 mmDIG0_AFMT_ISRC1_2 0 0x1895 4 0 2 AFMT_UPC_EAN_ISRC4 0 7 AFMT_UPC_EAN_ISRC5 8 15 AFMT_UPC_EAN_ISRC6 16 23 AFMT_UPC_EAN_ISRC7 24 31 mmDIG0_AFMT_ISRC1_3 0 0x1896 4 0 2 AFMT_UPC_EAN_ISRC8 0 7 AFMT_UPC_EAN_ISRC9 8 15 AFMT_UPC_EAN_ISRC10 16 23 AFMT_UPC_EAN_ISRC11 24 31 mmDIG0_AFMT_ISRC1_4 0 0x1897 4 0 2 AFMT_UPC_EAN_ISRC12 0 7 AFMT_UPC_EAN_ISRC13 8 15 AFMT_UPC_EAN_ISRC14 16 23 AFMT_UPC_EAN_ISRC15 24 31 mmDIG0_AFMT_ISRC2_0 0 0x1898 4 0 2 AFMT_UPC_EAN_ISRC16 0 7 AFMT_UPC_EAN_ISRC17 8 15 AFMT_UPC_EAN_ISRC18 16 23 AFMT_UPC_EAN_ISRC19 24 31 mmDIG0_AFMT_ISRC2_1 0 0x1899 4 0 2 AFMT_UPC_EAN_ISRC20 0 7 AFMT_UPC_EAN_ISRC21 8 15 AFMT_UPC_EAN_ISRC22 16 23 AFMT_UPC_EAN_ISRC23 24 31 mmDIG0_AFMT_ISRC2_2 0 0x189a 4 0 2 AFMT_UPC_EAN_ISRC24 0 7 AFMT_UPC_EAN_ISRC25 8 15 AFMT_UPC_EAN_ISRC26 16 23 AFMT_UPC_EAN_ISRC27 24 31 mmDIG0_AFMT_ISRC2_3 0 0x189b 4 0 2 AFMT_UPC_EAN_ISRC28 0 7 AFMT_UPC_EAN_ISRC29 8 15 AFMT_UPC_EAN_ISRC30 16 23 AFMT_UPC_EAN_ISRC31 24 31 mmDIG0_AFMT_AVI_INFO0 0 0x189c 12 0 2 AFMT_AVI_INFO_CHECKSUM 0 7 AFMT_AVI_INFO_S 8 9 AFMT_AVI_INFO_B 10 11 AFMT_AVI_INFO_A 12 12 AFMT_AVI_INFO_Y 13 15 AFMT_AVI_INFO_R 16 19 AFMT_AVI_INFO_M 20 21 AFMT_AVI_INFO_C 22 23 AFMT_AVI_INFO_SC 24 25 AFMT_AVI_INFO_Q 26 27 AFMT_AVI_INFO_EC 28 30 AFMT_AVI_INFO_ITC 31 31 mmDIG0_AFMT_AVI_INFO1 0 0x189d 5 0 2 AFMT_AVI_INFO_VIC 0 7 AFMT_AVI_INFO_PR 8 11 AFMT_AVI_INFO_CN 12 13 AFMT_AVI_INFO_YQ 14 15 AFMT_AVI_INFO_TOP 16 31 mmDIG0_AFMT_AVI_INFO2 0 0x189e 2 0 2 AFMT_AVI_INFO_BOTTOM 0 15 AFMT_AVI_INFO_LEFT 16 31 mmDIG0_AFMT_AVI_INFO3 0 0x189f 2 0 2 AFMT_AVI_INFO_RIGHT 0 15 AFMT_AVI_INFO_VERSION 24 31 mmDIG0_AFMT_MPEG_INFO0 0 0x18a0 4 0 2 AFMT_MPEG_INFO_CHECKSUM 0 7 AFMT_MPEG_INFO_MB0 8 15 AFMT_MPEG_INFO_MB1 16 23 AFMT_MPEG_INFO_MB2 24 31 mmDIG0_AFMT_MPEG_INFO1 0 0x18a1 3 0 2 AFMT_MPEG_INFO_MB3 0 7 AFMT_MPEG_INFO_MF 8 9 AFMT_MPEG_INFO_FR 12 12 mmDIG0_AFMT_GENERIC_HDR 0 0x18a2 4 0 2 AFMT_GENERIC_HB0 0 7 AFMT_GENERIC_HB1 8 15 AFMT_GENERIC_HB2 16 23 AFMT_GENERIC_HB3 24 31 mmDIG0_AFMT_GENERIC_0 0 0x18a3 4 0 2 AFMT_GENERIC_BYTE0 0 7 AFMT_GENERIC_BYTE1 8 15 AFMT_GENERIC_BYTE2 16 23 AFMT_GENERIC_BYTE3 24 31 mmDIG0_AFMT_GENERIC_1 0 0x18a4 4 0 2 AFMT_GENERIC_BYTE4 0 7 AFMT_GENERIC_BYTE5 8 15 AFMT_GENERIC_BYTE6 16 23 AFMT_GENERIC_BYTE7 24 31 mmDIG0_AFMT_GENERIC_2 0 0x18a5 4 0 2 AFMT_GENERIC_BYTE8 0 7 AFMT_GENERIC_BYTE9 8 15 AFMT_GENERIC_BYTE10 16 23 AFMT_GENERIC_BYTE11 24 31 mmDIG0_AFMT_GENERIC_3 0 0x18a6 4 0 2 AFMT_GENERIC_BYTE12 0 7 AFMT_GENERIC_BYTE13 8 15 AFMT_GENERIC_BYTE14 16 23 AFMT_GENERIC_BYTE15 24 31 mmDIG0_AFMT_GENERIC_4 0 0x18a7 4 0 2 AFMT_GENERIC_BYTE16 0 7 AFMT_GENERIC_BYTE17 8 15 AFMT_GENERIC_BYTE18 16 23 AFMT_GENERIC_BYTE19 24 31 mmDIG0_AFMT_GENERIC_5 0 0x18a8 4 0 2 AFMT_GENERIC_BYTE20 0 7 AFMT_GENERIC_BYTE21 8 15 AFMT_GENERIC_BYTE22 16 23 AFMT_GENERIC_BYTE23 24 31 mmDIG0_AFMT_GENERIC_6 0 0x18a9 4 0 2 AFMT_GENERIC_BYTE24 0 7 AFMT_GENERIC_BYTE25 8 15 AFMT_GENERIC_BYTE26 16 23 AFMT_GENERIC_BYTE27 24 31 mmDIG0_AFMT_GENERIC_7 0 0x18aa 4 0 2 AFMT_GENERIC_BYTE28 0 7 AFMT_GENERIC_BYTE29 8 15 AFMT_GENERIC_BYTE30 16 23 AFMT_GENERIC_BYTE31 24 31 mmDIG0_HDMI_GENERIC_PACKET_CONTROL1 0 0x18ab 6 0 2 HDMI_GENERIC2_SEND 0 0 HDMI_GENERIC2_CONT 1 1 HDMI_GENERIC3_SEND 4 4 HDMI_GENERIC3_CONT 5 5 HDMI_GENERIC2_LINE 16 21 HDMI_GENERIC3_LINE 24 29 mmDIG0_HDMI_ACR_32_0 0 0x18ac 1 0 2 HDMI_ACR_CTS_32 12 31 mmDIG0_HDMI_ACR_32_1 0 0x18ad 1 0 2 HDMI_ACR_N_32 0 19 mmDIG0_HDMI_ACR_44_0 0 0x18ae 1 0 2 HDMI_ACR_CTS_44 12 31 mmDIG0_HDMI_ACR_44_1 0 0x18af 1 0 2 HDMI_ACR_N_44 0 19 mmDIG0_HDMI_ACR_48_0 0 0x18b0 1 0 2 HDMI_ACR_CTS_48 12 31 mmDIG0_HDMI_ACR_48_1 0 0x18b1 1 0 2 HDMI_ACR_N_48 0 19 mmDIG0_HDMI_ACR_STATUS_0 0 0x18b2 1 0 2 HDMI_ACR_CTS 12 31 mmDIG0_HDMI_ACR_STATUS_1 0 0x18b3 1 0 2 HDMI_ACR_N 0 19 mmDIG0_AFMT_AUDIO_INFO0 0 0x18b4 5 0 2 AFMT_AUDIO_INFO_CHECKSUM 0 7 AFMT_AUDIO_INFO_CC 8 10 AFMT_AUDIO_INFO_CT 11 14 AFMT_AUDIO_INFO_CHECKSUM_OFFSET 16 23 AFMT_AUDIO_INFO_CXT 24 28 mmDIG0_AFMT_AUDIO_INFO1 0 0x18b5 4 0 2 AFMT_AUDIO_INFO_CA 0 7 AFMT_AUDIO_INFO_LSV 11 14 AFMT_AUDIO_INFO_DM_INH 15 15 AFMT_AUDIO_INFO_LFEPBL 16 17 mmDIG0_AFMT_60958_0 0 0x18b6 10 0 2 AFMT_60958_CS_A 0 0 AFMT_60958_CS_B 1 1 AFMT_60958_CS_C 2 2 AFMT_60958_CS_D 3 5 AFMT_60958_CS_MODE 6 7 AFMT_60958_CS_CATEGORY_CODE 8 15 AFMT_60958_CS_SOURCE_NUMBER 16 19 AFMT_60958_CS_CHANNEL_NUMBER_L 20 23 AFMT_60958_CS_SAMPLING_FREQUENCY 24 27 AFMT_60958_CS_CLOCK_ACCURACY 28 29 mmDIG0_AFMT_60958_1 0 0x18b7 5 0 2 AFMT_60958_CS_WORD_LENGTH 0 3 AFMT_60958_CS_ORIGINAL_SAMPLING_FREQUENCY 4 7 AFMT_60958_VALID_L 16 16 AFMT_60958_VALID_R 18 18 AFMT_60958_CS_CHANNEL_NUMBER_R 20 23 mmDIG0_AFMT_AUDIO_CRC_CONTROL 0 0x18b8 5 0 2 AFMT_AUDIO_CRC_EN 0 0 AFMT_AUDIO_CRC_CONT 4 4 AFMT_AUDIO_CRC_SOURCE 8 8 AFMT_AUDIO_CRC_CH_SEL 12 15 AFMT_AUDIO_CRC_COUNT 16 31 mmDIG0_AFMT_RAMP_CONTROL0 0 0x18b9 2 0 2 AFMT_RAMP_MAX_COUNT 0 23 AFMT_RAMP_DATA_SIGN 31 31 mmDIG0_AFMT_RAMP_CONTROL1 0 0x18ba 2 0 2 AFMT_RAMP_MIN_COUNT 0 23 AFMT_AUDIO_TEST_CH_DISABLE 24 31 mmDIG0_AFMT_RAMP_CONTROL2 0 0x18bb 1 0 2 AFMT_RAMP_INC_COUNT 0 23 mmDIG0_AFMT_RAMP_CONTROL3 0 0x18bc 1 0 2 AFMT_RAMP_DEC_COUNT 0 23 mmDIG0_AFMT_60958_2 0 0x18bd 6 0 2 AFMT_60958_CS_CHANNEL_NUMBER_2 0 3 AFMT_60958_CS_CHANNEL_NUMBER_3 4 7 AFMT_60958_CS_CHANNEL_NUMBER_4 8 11 AFMT_60958_CS_CHANNEL_NUMBER_5 12 15 AFMT_60958_CS_CHANNEL_NUMBER_6 16 19 AFMT_60958_CS_CHANNEL_NUMBER_7 20 23 mmDIG0_AFMT_AUDIO_CRC_RESULT 0 0x18be 2 0 2 AFMT_AUDIO_CRC_DONE 0 0 AFMT_AUDIO_CRC 8 31 mmDIG0_AFMT_STATUS 0 0x18bf 4 0 2 AFMT_AUDIO_ENABLE 4 4 AFMT_AZ_HBR_ENABLE 8 8 AFMT_AUDIO_FIFO_OVERFLOW 24 24 AFMT_AZ_AUDIO_ENABLE_CHG 30 30 mmDIG0_AFMT_AUDIO_PACKET_CONTROL 0 0x18c0 8 0 2 AFMT_AUDIO_SAMPLE_SEND 0 0 AFMT_RESET_FIFO_WHEN_AUDIO_DIS 11 11 AFMT_AUDIO_TEST_EN 12 12 AFMT_AUDIO_TEST_MODE 14 14 AFMT_AUDIO_FIFO_OVERFLOW_ACK 23 23 AFMT_AUDIO_CHANNEL_SWAP 24 24 AFMT_60958_CS_UPDATE 26 26 AFMT_AZ_AUDIO_ENABLE_CHG_ACK 30 30 mmDIG0_AFMT_VBI_PACKET_CONTROL 0 0x18c1 3 0 2 AFMT_GENERIC0_UPDATE 2 2 AFMT_GENERIC2_UPDATE 3 3 AFMT_GENERIC_INDEX 30 31 mmDIG0_AFMT_INFOFRAME_CONTROL0 0 0x18c2 3 0 2 AFMT_AUDIO_INFO_SOURCE 6 6 AFMT_AUDIO_INFO_UPDATE 7 7 AFMT_MPEG_INFO_UPDATE 10 10 mmDIG0_AFMT_AUDIO_SRC_CONTROL 0 0x18c3 1 0 2 AFMT_AUDIO_SRC_SELECT 0 2 mmDIG0_DIG_BE_CNTL 0 0x18c5 5 0 2 DIG_DUAL_LINK_ENABLE 0 0 DIG_SWAP 1 1 DIG_FE_SOURCE_SELECT 8 14 DIG_MODE 16 18 DIG_HPD_SELECT 28 30 mmDIG0_DIG_BE_EN_CNTL 0 0x18c6 2 0 2 DIG_ENABLE 0 0 DIG_SYMCLK_BE_ON 8 8 mmDIG0_TMDS_CNTL 0 0x18e9 1 0 2 TMDS_SYNC_PHASE 0 0 mmDIG0_TMDS_CONTROL_CHAR 0 0x18ea 4 0 2 TMDS_CONTROL_CHAR0_OUT_EN 0 0 TMDS_CONTROL_CHAR1_OUT_EN 1 1 TMDS_CONTROL_CHAR2_OUT_EN 2 2 TMDS_CONTROL_CHAR3_OUT_EN 3 3 mmDIG0_TMDS_CONTROL0_FEEDBACK 0 0x18eb 2 0 2 TMDS_CONTROL0_FEEDBACK_SELECT 0 1 TMDS_CONTROL0_FEEDBACK_DELAY 8 9 mmDIG0_TMDS_STEREOSYNC_CTL_SEL 0 0x18ec 1 0 2 TMDS_STEREOSYNC_CTL_SEL 0 1 mmDIG0_TMDS_SYNC_CHAR_PATTERN_0_1 0 0x18ed 2 0 2 TMDS_SYNC_CHAR_PATTERN0 0 9 TMDS_SYNC_CHAR_PATTERN1 16 25 mmDIG0_TMDS_SYNC_CHAR_PATTERN_2_3 0 0x18ee 2 0 2 TMDS_SYNC_CHAR_PATTERN2 0 9 TMDS_SYNC_CHAR_PATTERN3 16 25 mmDIG0_TMDS_CTL_BITS 0 0x18f0 4 0 2 TMDS_CTL0 0 0 TMDS_CTL1 8 8 TMDS_CTL2 16 16 TMDS_CTL3 24 24 mmDIG0_TMDS_DCBALANCER_CONTROL 0 0x18f1 4 0 2 TMDS_DCBALANCER_EN 0 0 TMDS_DCBALANCER_TEST_EN 8 8 TMDS_DCBALANCER_TEST_IN 16 19 TMDS_DCBALANCER_FORCE 24 24 mmDIG0_TMDS_CTL0_1_GEN_CNTL 0 0x18f3 15 0 2 TMDS_CTL0_DATA_SEL 0 3 TMDS_CTL0_DATA_DELAY 4 6 TMDS_CTL0_DATA_INVERT 7 7 TMDS_CTL0_DATA_MODULATION 8 9 TMDS_CTL0_USE_FEEDBACK_PATH 10 10 TMDS_CTL0_FB_SYNC_CONT 11 11 TMDS_CTL0_PATTERN_OUT_EN 12 12 TMDS_CTL1_DATA_SEL 16 19 TMDS_CTL1_DATA_DELAY 20 22 TMDS_CTL1_DATA_INVERT 23 23 TMDS_CTL1_DATA_MODULATION 24 25 TMDS_CTL1_USE_FEEDBACK_PATH 26 26 TMDS_CTL1_FB_SYNC_CONT 27 27 TMDS_CTL1_PATTERN_OUT_EN 28 28 TMDS_2BIT_COUNTER_EN 31 31 mmDIG0_TMDS_CTL2_3_GEN_CNTL 0 0x18f4 14 0 2 TMDS_CTL2_DATA_SEL 0 3 TMDS_CTL2_DATA_DELAY 4 6 TMDS_CTL2_DATA_INVERT 7 7 TMDS_CTL2_DATA_MODULATION 8 9 TMDS_CTL2_USE_FEEDBACK_PATH 10 10 TMDS_CTL2_FB_SYNC_CONT 11 11 TMDS_CTL2_PATTERN_OUT_EN 12 12 TMDS_CTL3_DATA_SEL 16 19 TMDS_CTL3_DATA_DELAY 20 22 TMDS_CTL3_DATA_INVERT 23 23 TMDS_CTL3_DATA_MODULATION 24 25 TMDS_CTL3_USE_FEEDBACK_PATH 26 26 TMDS_CTL3_FB_SYNC_CONT 27 27 TMDS_CTL3_PATTERN_OUT_EN 28 28 mmDIG0_DIG_VERSION 0 0x18f6 1 0 2 DIG_TYPE 0 0 mmDIG0_DIG_LANE_ENABLE 0 0x18f7 5 0 2 DIG_LANE0EN 0 0 DIG_LANE1EN 1 1 DIG_LANE2EN 2 2 DIG_LANE3EN 3 3 DIG_CLK_EN 8 8 mmDIG0_AFMT_CNTL 0 0x18fc 2 0 2 AFMT_AUDIO_CLOCK_EN 0 0 AFMT_AUDIO_CLOCK_ON 8 8 mmDP0_DP_LINK_CNTL 0 0x191e 3 0 2 DP_LINK_TRAINING_COMPLETE 4 4 DP_LINK_STATUS 8 8 DP_EMBEDDED_PANEL_MODE 17 17 mmDP0_DP_PIXEL_FORMAT 0 0x191f 4 0 2 DP_PIXEL_ENCODING 0 2 DP_DYN_RANGE 8 8 DP_YCBCR_RANGE 16 16 DP_COMPONENT_DEPTH 24 26 mmDP0_DP_MSA_COLORIMETRY 0 0x1920 4 0 2 DP_MSA_MISC0_OVERRIDE 0 7 DP_MSA_MISC0_OVERRIDE_ENABLE 8 8 DP_MSA_MISC1_BIT7_OVERRIDE 9 9 DP_MSA_MISC1_BIT7_OVERRIDE_ENABLE 17 17 mmDP0_DP_CONFIG 0 0x1921 1 0 2 DP_UDI_LANES 0 1 mmDP0_DP_VID_STREAM_CNTL 0 0x1922 4 0 2 DP_VID_STREAM_ENABLE 0 0 DP_VID_STREAM_DIS_DEFER 8 9 DP_VID_STREAM_STATUS 16 16 DP_VID_STREAM_CHANGE_KEEPOUT 20 20 mmDP0_DP_STEER_FIFO 0 0x1923 7 0 2 DP_STEER_FIFO_RESET 0 0 DP_STEER_OVERFLOW_FLAG 4 4 DP_STEER_OVERFLOW_INT 5 5 DP_STEER_OVERFLOW_ACK 6 6 DP_STEER_OVERFLOW_MASK 7 7 DP_TU_OVERFLOW_FLAG 8 8 DP_TU_OVERFLOW_ACK 12 12 mmDP0_DP_MSA_MISC 0 0x1924 4 0 2 DP_MSA_MISC1 3 6 DP_MSA_MISC2 8 15 DP_MSA_MISC3 16 23 DP_MSA_MISC4 24 31 mmDP0_DP_VID_TIMING 0 0x1926 5 0 2 DP_VID_TIMING_MODE 0 0 DP_VID_M_N_DOUBLE_BUFFER_MODE 4 4 DP_VID_M_N_GEN_EN 8 8 DP_VID_M_DOUBLE_VALUE_EN 9 9 DP_VID_N_DIV 24 31 mmDP0_DP_VID_N 0 0x1927 1 0 2 DP_VID_N 0 23 mmDP0_DP_VID_M 0 0x1928 1 0 2 DP_VID_M 0 23 mmDP0_DP_LINK_FRAMING_CNTL 0 0x1929 3 0 2 DP_IDLE_BS_INTERVAL 0 17 DP_VBID_DISABLE 24 24 DP_VID_ENHANCED_FRAME_MODE 28 28 mmDP0_DP_HBR2_EYE_PATTERN 0 0x192a 1 0 2 DP_HBR2_EYE_PATTERN_ENABLE 0 0 mmDP0_DP_VID_MSA_VBID 0 0x192b 3 0 2 DP_VID_MSA_LOCATION 0 11 DP_VID_MSA_TOP_FIELD_MODE 16 16 DP_VID_VBID_FIELD_POL 24 24 mmDP0_DP_VID_INTERRUPT_CNTL 0 0x192c 3 0 2 DP_VID_STREAM_DISABLE_INT 0 0 DP_VID_STREAM_DISABLE_ACK 1 1 DP_VID_STREAM_DISABLE_MASK 2 2 mmDP0_DP_DPHY_CNTL 0 0x192d 6 0 2 DPHY_ATEST_SEL_LANE0 0 0 DPHY_ATEST_SEL_LANE1 1 1 DPHY_ATEST_SEL_LANE2 2 2 DPHY_ATEST_SEL_LANE3 3 3 DPHY_BYPASS 16 16 DPHY_SKEW_BYPASS 24 24 mmDP0_DP_DPHY_TRAINING_PATTERN_SEL 0 0x192e 1 0 2 DPHY_TRAINING_PATTERN_SEL 0 1 mmDP0_DP_DPHY_SYM0 0 0x192f 3 0 2 DPHY_SYM1 0 9 DPHY_SYM2 10 19 DPHY_SYM3 20 29 mmDP0_DP_DPHY_SYM1 0 0x1930 3 0 2 DPHY_SYM4 0 9 DPHY_SYM5 10 19 DPHY_SYM6 20 29 mmDP0_DP_DPHY_SYM2 0 0x1931 2 0 2 DPHY_SYM7 0 9 DPHY_SYM8 10 19 mmDP0_DP_DPHY_8B10B_CNTL 0 0x1932 3 0 2 DPHY_8B10B_RESET 8 8 DPHY_8B10B_EXT_DISP 16 16 DPHY_8B10B_CUR_DISP 24 24 mmDP0_DP_DPHY_PRBS_CNTL 0 0x1933 3 0 2 DPHY_PRBS_EN 0 0 DPHY_PRBS_SEL 4 5 DPHY_PRBS_SEED 8 30 mmDP0_DP_DPHY_SCRAM_CNTL 0 0x1934 4 0 2 DPHY_SCRAMBLER_DIS 0 0 DPHY_SCRAMBLER_ADVANCE 4 4 DPHY_SCRAMBLER_BS_COUNT 8 17 DPHY_SCRAMBLER_KCODE 24 24 mmDP0_DP_DPHY_CRC_EN 0 0x1935 3 0 2 DPHY_CRC_EN 0 0 DPHY_CRC_CONT_EN 4 4 DPHY_CRC_RESULT_VALID 8 8 mmDP0_DP_DPHY_CRC_CNTL 0 0x1936 3 0 2 DPHY_CRC_FIELD 0 0 DPHY_CRC_SEL 4 5 DPHY_CRC_MASK 16 23 mmDP0_DP_DPHY_CRC_RESULT 0 0x1937 4 0 2 DPHY_CRC_RESULT 0 7 DPHY_CRC_RESULT1 8 15 DPHY_CRC_RESULT2 16 23 DPHY_CRC_RESULT3 24 31 mmDP0_DP_DPHY_CRC_MST_CNTL 0 0x1938 2 0 2 DPHY_CRC_MST_FIRST_SLOT 0 5 DPHY_CRC_MST_LAST_SLOT 8 13 mmDP0_DP_DPHY_CRC_MST_STATUS 0 0x1939 3 0 2 DPHY_CRC_MST_PHASE_LOCK 0 0 DPHY_CRC_MST_PHASE_ERROR 8 8 DPHY_CRC_MST_PHASE_ERROR_ACK 16 16 mmDP0_DP_DPHY_FAST_TRAINING 0 0x193a 5 0 2 DPHY_RX_FAST_TRAINING_CAPABLE 0 0 DPHY_SW_FAST_TRAINING_START 1 1 DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN 2 2 DPHY_FAST_TRAINING_TP1_TIME 8 19 DPHY_FAST_TRAINING_TP2_TIME 20 31 mmDP0_DP_DPHY_FAST_TRAINING_STATUS 0 0x193b 4 0 2 DPHY_FAST_TRAINING_STATE 0 2 DPHY_FAST_TRAINING_COMPLETE_OCCURRED 4 4 DPHY_FAST_TRAINING_COMPLETE_MASK 8 8 DPHY_FAST_TRAINING_COMPLETE_ACK 12 12 mmDP0_DP_MSA_V_TIMING_OVERRIDE1 0 0x193c 2 0 2 DP_MSA_V_TIMING_OVERRIDE_EN 0 0 DP_MSA_V_TOTAL_OVERRIDE 4 17 mmDP0_DP_MSA_V_TIMING_OVERRIDE2 0 0x193d 2 0 2 DP_MSA_V_BLANK_START_OVERRIDE 0 13 DP_MSA_V_BLANK_END_OVERRIDE 16 29 mmDP0_DP_SEC_CNTL 0 0x1941 11 0 2 DP_SEC_STREAM_ENABLE 0 0 DP_SEC_ASP_ENABLE 4 4 DP_SEC_ATP_ENABLE 8 8 DP_SEC_AIP_ENABLE 12 12 DP_SEC_ACM_ENABLE 16 16 DP_SEC_GSP0_ENABLE 20 20 DP_SEC_GSP1_ENABLE 21 21 DP_SEC_GSP2_ENABLE 22 22 DP_SEC_GSP3_ENABLE 23 23 DP_SEC_AVI_ENABLE 24 24 DP_SEC_MPG_ENABLE 28 28 mmDP0_DP_SEC_CNTL1 0 0x1942 6 0 2 DP_SEC_ISRC_ENABLE 0 0 DP_SEC_GSP0_PRIORITY 4 4 DP_SEC_GSP0_SEND 5 5 DP_SEC_GSP0_SEND_PENDING 6 6 DP_SEC_GSP0_SEND_DEADLINE_MISSED 7 7 DP_SEC_GSP0_LINE_NUM 16 31 mmDP0_DP_SEC_FRAMING1 0 0x1943 2 0 2 DP_SEC_FRAME_START_LOCATION 0 11 DP_SEC_VBLANK_TRANSMIT_WIDTH 16 31 mmDP0_DP_SEC_FRAMING2 0 0x1944 2 0 2 DP_SEC_START_POSITION 0 15 DP_SEC_HBLANK_TRANSMIT_WIDTH 16 31 mmDP0_DP_SEC_FRAMING3 0 0x1945 2 0 2 DP_SEC_IDLE_FRAME_SIZE 0 13 DP_SEC_IDLE_TRANSMIT_WIDTH 16 31 mmDP0_DP_SEC_FRAMING4 0 0x1946 4 0 2 DP_SEC_COLLISION_STATUS 20 20 DP_SEC_COLLISION_ACK 24 24 DP_SEC_AUDIO_MUTE 28 28 DP_SEC_AUDIO_MUTE_STATUS 29 29 mmDP0_DP_SEC_AUD_N 0 0x1947 1 0 2 DP_SEC_AUD_N 0 23 mmDP0_DP_SEC_AUD_N_READBACK 0 0x1948 1 0 2 DP_SEC_AUD_N_READBACK 0 23 mmDP0_DP_SEC_AUD_M 0 0x1949 1 0 2 DP_SEC_AUD_M 0 23 mmDP0_DP_SEC_AUD_M_READBACK 0 0x194a 1 0 2 DP_SEC_AUD_M_READBACK 0 23 mmDP0_DP_SEC_TIMESTAMP 0 0x194b 1 0 2 DP_SEC_TIMESTAMP_MODE 0 0 mmDP0_DP_SEC_PACKET_CNTL 0 0x194c 4 0 2 DP_SEC_ASP_CODING_TYPE 1 3 DP_SEC_ASP_PRIORITY 4 4 DP_SEC_VERSION 8 13 DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE 16 16 mmDP0_DP_MSE_RATE_CNTL 0 0x194d 2 0 2 DP_MSE_RATE_Y 0 25 DP_MSE_RATE_X 26 31 mmDP0_DP_MSE_RATE_UPDATE 0 0x194f 1 0 2 DP_MSE_RATE_UPDATE_PENDING 0 0 mmDP0_DP_MSE_SAT0 0 0x1950 4 0 2 DP_MSE_SAT_SRC0 0 2 DP_MSE_SAT_SLOT_COUNT0 8 13 DP_MSE_SAT_SRC1 16 18 DP_MSE_SAT_SLOT_COUNT1 24 29 mmDP0_DP_MSE_SAT1 0 0x1951 4 0 2 DP_MSE_SAT_SRC2 0 2 DP_MSE_SAT_SLOT_COUNT2 8 13 DP_MSE_SAT_SRC3 16 18 DP_MSE_SAT_SLOT_COUNT3 24 29 mmDP0_DP_MSE_SAT2 0 0x1952 4 0 2 DP_MSE_SAT_SRC4 0 2 DP_MSE_SAT_SLOT_COUNT4 8 13 DP_MSE_SAT_SRC5 16 18 DP_MSE_SAT_SLOT_COUNT5 24 29 mmDP0_DP_MSE_SAT_UPDATE 0 0x1953 2 0 2 DP_MSE_SAT_UPDATE 0 1 DP_MSE_16_MTP_KEEPOUT 8 8 mmDP0_DP_MSE_LINK_TIMING 0 0x1954 2 0 2 DP_MSE_LINK_FRAME 0 9 DP_MSE_LINK_LINE 16 17 mmDP0_DP_MSE_MISC_CNTL 0 0x1955 3 0 2 DP_MSE_BLANK_CODE 0 0 DP_MSE_TIMESTAMP_MODE 4 4 DP_MSE_ZERO_ENCODER 8 8 mmDP0_DP_DPHY_BS_SR_SWAP_CNTL 0 0x195a 3 0 2 DPHY_LOAD_BS_COUNT 0 9 DPHY_BS_SR_SWAP_DONE 15 15 DPHY_LOAD_BS_COUNT_START 16 16 mmDP0_DP_DPHY_HBR2_PATTERN_CONTROL 0 0x195b 1 0 2 DP_DPHY_HBR2_PATTERN_CONTROL 0 2 mmDP0_DP_MSE_SAT0_STATUS 0 0x195d 4 0 2 DP_MSE_SAT_SRC0_STATUS 0 2 DP_MSE_SAT_SLOT_COUNT0_STATUS 8 13 DP_MSE_SAT_SRC1_STATUS 16 18 DP_MSE_SAT_SLOT_COUNT1_STATUS 24 29 mmDP0_DP_MSE_SAT1_STATUS 0 0x195e 4 0 2 DP_MSE_SAT_SRC2_STATUS 0 2 DP_MSE_SAT_SLOT_COUNT2_STATUS 8 13 DP_MSE_SAT_SRC3_STATUS 16 18 DP_MSE_SAT_SLOT_COUNT3_STATUS 24 29 mmDP0_DP_MSE_SAT2_STATUS 0 0x195f 4 0 2 DP_MSE_SAT_SRC4_STATUS 0 2 DP_MSE_SAT_SLOT_COUNT4_STATUS 8 13 DP_MSE_SAT_SRC5_STATUS 16 18 DP_MSE_SAT_SLOT_COUNT5_STATUS 24 29 mmDIG1_DIG_FE_CNTL 0 0x197e 7 0 2 DIG_SOURCE_SELECT 0 2 DIG_STEREOSYNC_SELECT 4 6 DIG_STEREOSYNC_GATE_EN 8 8 DIG_START 10 10 DIG_SYMCLK_FE_ON 24 24 TMDS_PIXEL_ENCODING 28 28 TMDS_COLOR_FORMAT 30 31 mmDIG1_DIG_OUTPUT_CRC_CNTL 0 0x197f 3 0 2 DIG_OUTPUT_CRC_EN 0 0 DIG_OUTPUT_CRC_LINK_SEL 4 4 DIG_OUTPUT_CRC_DATA_SEL 8 9 mmDIG1_DIG_OUTPUT_CRC_RESULT 0 0x1980 1 0 2 DIG_OUTPUT_CRC_RESULT 0 29 mmDIG1_DIG_CLOCK_PATTERN 0 0x1981 1 0 2 DIG_CLOCK_PATTERN 0 9 mmDIG1_DIG_TEST_PATTERN 0 0x1982 6 0 2 DIG_TEST_PATTERN_OUT_EN 0 0 DIG_HALF_CLOCK_PATTERN_SEL 1 1 DIG_RANDOM_PATTERN_OUT_EN 4 4 DIG_RANDOM_PATTERN_RESET 5 5 DIG_TEST_PATTERN_EXTERNAL_RESET_EN 6 6 DIG_STATIC_TEST_PATTERN 16 25 mmDIG1_DIG_RANDOM_PATTERN_SEED 0 0x1983 2 0 2 DIG_RANDOM_PATTERN_SEED 0 23 DIG_RAN_PAT_DURING_DE_ONLY 24 24 mmDIG1_DIG_FIFO_STATUS 0 0x1984 11 0 2 DIG_FIFO_LEVEL_ERROR 0 0 DIG_FIFO_USE_OVERWRITE_LEVEL 1 1 DIG_FIFO_OVERWRITE_LEVEL 2 7 DIG_FIFO_ERROR_ACK 8 8 DIG_FIFO_CAL_AVERAGE_LEVEL 10 15 DIG_FIFO_MAXIMUM_LEVEL 16 20 DIG_FIFO_MINIMUM_LEVEL 22 25 DIG_FIFO_READ_CLOCK_SRC 26 26 DIG_FIFO_CALIBRATED 29 29 DIG_FIFO_FORCE_RECAL_AVERAGE 30 30 DIG_FIFO_FORCE_RECOMP_MINMAX 31 31 mmDIG1_HDMI_CONTROL 0 0x1987 9 0 2 HDMI_KEEPOUT_MODE 0 0 HDMI_DATA_SCRAMBLE_EN 1 1 HDMI_CLOCK_CHANNEL_RATE 2 2 HDMI_NO_EXTRA_NULL_PACKET_FILLED 3 3 HDMI_PACKET_GEN_VERSION 4 4 HDMI_ERROR_ACK 8 8 HDMI_ERROR_MASK 9 9 HDMI_DEEP_COLOR_ENABLE 24 24 HDMI_DEEP_COLOR_DEPTH 28 29 mmDIG1_HDMI_STATUS 0 0x1988 4 0 2 HDMI_ACTIVE_AVMUTE 0 0 HDMI_AUDIO_PACKET_ERROR 16 16 HDMI_VBI_PACKET_ERROR 20 20 HDMI_ERROR_INT 27 27 mmDIG1_HDMI_AUDIO_PACKET_CONTROL 0 0x1989 2 0 2 HDMI_AUDIO_DELAY_EN 4 5 HDMI_AUDIO_PACKETS_PER_LINE 16 20 mmDIG1_HDMI_ACR_PACKET_CONTROL 0 0x198a 7 0 2 HDMI_ACR_SEND 0 0 HDMI_ACR_CONT 1 1 HDMI_ACR_SELECT 4 5 HDMI_ACR_SOURCE 8 8 HDMI_ACR_AUTO_SEND 12 12 HDMI_ACR_N_MULTIPLE 16 18 HDMI_ACR_AUDIO_PRIORITY 31 31 mmDIG1_HDMI_VBI_PACKET_CONTROL 0 0x198b 6 0 2 HDMI_NULL_SEND 0 0 HDMI_GC_SEND 4 4 HDMI_GC_CONT 5 5 HDMI_ISRC_SEND 8 8 HDMI_ISRC_CONT 9 9 HDMI_ISRC_LINE 16 21 mmDIG1_HDMI_INFOFRAME_CONTROL0 0 0x198c 6 0 2 HDMI_AVI_INFO_SEND 0 0 HDMI_AVI_INFO_CONT 1 1 HDMI_AUDIO_INFO_SEND 4 4 HDMI_AUDIO_INFO_CONT 5 5 HDMI_MPEG_INFO_SEND 8 8 HDMI_MPEG_INFO_CONT 9 9 mmDIG1_HDMI_INFOFRAME_CONTROL1 0 0x198d 3 0 2 HDMI_AVI_INFO_LINE 0 5 HDMI_AUDIO_INFO_LINE 8 13 HDMI_MPEG_INFO_LINE 16 21 mmDIG1_HDMI_GENERIC_PACKET_CONTROL0 0 0x198e 6 0 2 HDMI_GENERIC0_SEND 0 0 HDMI_GENERIC0_CONT 1 1 HDMI_GENERIC1_SEND 4 4 HDMI_GENERIC1_CONT 5 5 HDMI_GENERIC0_LINE 16 21 HDMI_GENERIC1_LINE 24 29 mmDIG1_AFMT_INTERRUPT_STATUS 0 0x198f 0 0 2 mmDIG1_HDMI_GC 0 0x1991 5 0 2 HDMI_GC_AVMUTE 0 0 HDMI_GC_AVMUTE_CONT 2 2 HDMI_DEFAULT_PHASE 4 4 HDMI_PACKING_PHASE 8 11 HDMI_PACKING_PHASE_OVERRIDE 12 12 mmDIG1_AFMT_AUDIO_PACKET_CONTROL2 0 0x1992 6 0 2 AFMT_AUDIO_LAYOUT_OVRD 0 0 AFMT_AUDIO_LAYOUT_SELECT 1 1 AFMT_AUDIO_CHANNEL_ENABLE 8 15 AFMT_DP_AUDIO_STREAM_ID 16 23 AFMT_HBR_ENABLE_OVRD 24 24 AFMT_60958_OSF_OVRD 28 28 mmDIG1_AFMT_ISRC1_0 0 0x1993 3 0 2 AFMT_ISRC_STATUS 0 2 AFMT_ISRC_CONTINUE 6 6 AFMT_ISRC_VALID 7 7 mmDIG1_AFMT_ISRC1_1 0 0x1994 4 0 2 AFMT_UPC_EAN_ISRC0 0 7 AFMT_UPC_EAN_ISRC1 8 15 AFMT_UPC_EAN_ISRC2 16 23 AFMT_UPC_EAN_ISRC3 24 31 mmDIG1_AFMT_ISRC1_2 0 0x1995 4 0 2 AFMT_UPC_EAN_ISRC4 0 7 AFMT_UPC_EAN_ISRC5 8 15 AFMT_UPC_EAN_ISRC6 16 23 AFMT_UPC_EAN_ISRC7 24 31 mmDIG1_AFMT_ISRC1_3 0 0x1996 4 0 2 AFMT_UPC_EAN_ISRC8 0 7 AFMT_UPC_EAN_ISRC9 8 15 AFMT_UPC_EAN_ISRC10 16 23 AFMT_UPC_EAN_ISRC11 24 31 mmDIG1_AFMT_ISRC1_4 0 0x1997 4 0 2 AFMT_UPC_EAN_ISRC12 0 7 AFMT_UPC_EAN_ISRC13 8 15 AFMT_UPC_EAN_ISRC14 16 23 AFMT_UPC_EAN_ISRC15 24 31 mmDIG1_AFMT_ISRC2_0 0 0x1998 4 0 2 AFMT_UPC_EAN_ISRC16 0 7 AFMT_UPC_EAN_ISRC17 8 15 AFMT_UPC_EAN_ISRC18 16 23 AFMT_UPC_EAN_ISRC19 24 31 mmDIG1_AFMT_ISRC2_1 0 0x1999 4 0 2 AFMT_UPC_EAN_ISRC20 0 7 AFMT_UPC_EAN_ISRC21 8 15 AFMT_UPC_EAN_ISRC22 16 23 AFMT_UPC_EAN_ISRC23 24 31 mmDIG1_AFMT_ISRC2_2 0 0x199a 4 0 2 AFMT_UPC_EAN_ISRC24 0 7 AFMT_UPC_EAN_ISRC25 8 15 AFMT_UPC_EAN_ISRC26 16 23 AFMT_UPC_EAN_ISRC27 24 31 mmDIG1_AFMT_ISRC2_3 0 0x199b 4 0 2 AFMT_UPC_EAN_ISRC28 0 7 AFMT_UPC_EAN_ISRC29 8 15 AFMT_UPC_EAN_ISRC30 16 23 AFMT_UPC_EAN_ISRC31 24 31 mmDIG1_AFMT_AVI_INFO0 0 0x199c 12 0 2 AFMT_AVI_INFO_CHECKSUM 0 7 AFMT_AVI_INFO_S 8 9 AFMT_AVI_INFO_B 10 11 AFMT_AVI_INFO_A 12 12 AFMT_AVI_INFO_Y 13 15 AFMT_AVI_INFO_R 16 19 AFMT_AVI_INFO_M 20 21 AFMT_AVI_INFO_C 22 23 AFMT_AVI_INFO_SC 24 25 AFMT_AVI_INFO_Q 26 27 AFMT_AVI_INFO_EC 28 30 AFMT_AVI_INFO_ITC 31 31 mmDIG1_AFMT_AVI_INFO1 0 0x199d 5 0 2 AFMT_AVI_INFO_VIC 0 7 AFMT_AVI_INFO_PR 8 11 AFMT_AVI_INFO_CN 12 13 AFMT_AVI_INFO_YQ 14 15 AFMT_AVI_INFO_TOP 16 31 mmDIG1_AFMT_AVI_INFO2 0 0x199e 2 0 2 AFMT_AVI_INFO_BOTTOM 0 15 AFMT_AVI_INFO_LEFT 16 31 mmDIG1_AFMT_AVI_INFO3 0 0x199f 2 0 2 AFMT_AVI_INFO_RIGHT 0 15 AFMT_AVI_INFO_VERSION 24 31 mmDIG1_AFMT_MPEG_INFO0 0 0x19a0 4 0 2 AFMT_MPEG_INFO_CHECKSUM 0 7 AFMT_MPEG_INFO_MB0 8 15 AFMT_MPEG_INFO_MB1 16 23 AFMT_MPEG_INFO_MB2 24 31 mmDIG1_AFMT_MPEG_INFO1 0 0x19a1 3 0 2 AFMT_MPEG_INFO_MB3 0 7 AFMT_MPEG_INFO_MF 8 9 AFMT_MPEG_INFO_FR 12 12 mmDIG1_AFMT_GENERIC_HDR 0 0x19a2 4 0 2 AFMT_GENERIC_HB0 0 7 AFMT_GENERIC_HB1 8 15 AFMT_GENERIC_HB2 16 23 AFMT_GENERIC_HB3 24 31 mmDIG1_AFMT_GENERIC_0 0 0x19a3 4 0 2 AFMT_GENERIC_BYTE0 0 7 AFMT_GENERIC_BYTE1 8 15 AFMT_GENERIC_BYTE2 16 23 AFMT_GENERIC_BYTE3 24 31 mmDIG1_AFMT_GENERIC_1 0 0x19a4 4 0 2 AFMT_GENERIC_BYTE4 0 7 AFMT_GENERIC_BYTE5 8 15 AFMT_GENERIC_BYTE6 16 23 AFMT_GENERIC_BYTE7 24 31 mmDIG1_AFMT_GENERIC_2 0 0x19a5 4 0 2 AFMT_GENERIC_BYTE8 0 7 AFMT_GENERIC_BYTE9 8 15 AFMT_GENERIC_BYTE10 16 23 AFMT_GENERIC_BYTE11 24 31 mmDIG1_AFMT_GENERIC_3 0 0x19a6 4 0 2 AFMT_GENERIC_BYTE12 0 7 AFMT_GENERIC_BYTE13 8 15 AFMT_GENERIC_BYTE14 16 23 AFMT_GENERIC_BYTE15 24 31 mmDIG1_AFMT_GENERIC_4 0 0x19a7 4 0 2 AFMT_GENERIC_BYTE16 0 7 AFMT_GENERIC_BYTE17 8 15 AFMT_GENERIC_BYTE18 16 23 AFMT_GENERIC_BYTE19 24 31 mmDIG1_AFMT_GENERIC_5 0 0x19a8 4 0 2 AFMT_GENERIC_BYTE20 0 7 AFMT_GENERIC_BYTE21 8 15 AFMT_GENERIC_BYTE22 16 23 AFMT_GENERIC_BYTE23 24 31 mmDIG1_AFMT_GENERIC_6 0 0x19a9 4 0 2 AFMT_GENERIC_BYTE24 0 7 AFMT_GENERIC_BYTE25 8 15 AFMT_GENERIC_BYTE26 16 23 AFMT_GENERIC_BYTE27 24 31 mmDIG1_AFMT_GENERIC_7 0 0x19aa 4 0 2 AFMT_GENERIC_BYTE28 0 7 AFMT_GENERIC_BYTE29 8 15 AFMT_GENERIC_BYTE30 16 23 AFMT_GENERIC_BYTE31 24 31 mmDIG1_HDMI_GENERIC_PACKET_CONTROL1 0 0x19ab 6 0 2 HDMI_GENERIC2_SEND 0 0 HDMI_GENERIC2_CONT 1 1 HDMI_GENERIC3_SEND 4 4 HDMI_GENERIC3_CONT 5 5 HDMI_GENERIC2_LINE 16 21 HDMI_GENERIC3_LINE 24 29 mmDIG1_HDMI_ACR_32_0 0 0x19ac 1 0 2 HDMI_ACR_CTS_32 12 31 mmDIG1_HDMI_ACR_32_1 0 0x19ad 1 0 2 HDMI_ACR_N_32 0 19 mmDIG1_HDMI_ACR_44_0 0 0x19ae 1 0 2 HDMI_ACR_CTS_44 12 31 mmDIG1_HDMI_ACR_44_1 0 0x19af 1 0 2 HDMI_ACR_N_44 0 19 mmDIG1_HDMI_ACR_48_0 0 0x19b0 1 0 2 HDMI_ACR_CTS_48 12 31 mmDIG1_HDMI_ACR_48_1 0 0x19b1 1 0 2 HDMI_ACR_N_48 0 19 mmDIG1_HDMI_ACR_STATUS_0 0 0x19b2 1 0 2 HDMI_ACR_CTS 12 31 mmDIG1_HDMI_ACR_STATUS_1 0 0x19b3 1 0 2 HDMI_ACR_N 0 19 mmDIG1_AFMT_AUDIO_INFO0 0 0x19b4 5 0 2 AFMT_AUDIO_INFO_CHECKSUM 0 7 AFMT_AUDIO_INFO_CC 8 10 AFMT_AUDIO_INFO_CT 11 14 AFMT_AUDIO_INFO_CHECKSUM_OFFSET 16 23 AFMT_AUDIO_INFO_CXT 24 28 mmDIG1_AFMT_AUDIO_INFO1 0 0x19b5 4 0 2 AFMT_AUDIO_INFO_CA 0 7 AFMT_AUDIO_INFO_LSV 11 14 AFMT_AUDIO_INFO_DM_INH 15 15 AFMT_AUDIO_INFO_LFEPBL 16 17 mmDIG1_AFMT_60958_0 0 0x19b6 10 0 2 AFMT_60958_CS_A 0 0 AFMT_60958_CS_B 1 1 AFMT_60958_CS_C 2 2 AFMT_60958_CS_D 3 5 AFMT_60958_CS_MODE 6 7 AFMT_60958_CS_CATEGORY_CODE 8 15 AFMT_60958_CS_SOURCE_NUMBER 16 19 AFMT_60958_CS_CHANNEL_NUMBER_L 20 23 AFMT_60958_CS_SAMPLING_FREQUENCY 24 27 AFMT_60958_CS_CLOCK_ACCURACY 28 29 mmDIG1_AFMT_60958_1 0 0x19b7 5 0 2 AFMT_60958_CS_WORD_LENGTH 0 3 AFMT_60958_CS_ORIGINAL_SAMPLING_FREQUENCY 4 7 AFMT_60958_VALID_L 16 16 AFMT_60958_VALID_R 18 18 AFMT_60958_CS_CHANNEL_NUMBER_R 20 23 mmDIG1_AFMT_AUDIO_CRC_CONTROL 0 0x19b8 5 0 2 AFMT_AUDIO_CRC_EN 0 0 AFMT_AUDIO_CRC_CONT 4 4 AFMT_AUDIO_CRC_SOURCE 8 8 AFMT_AUDIO_CRC_CH_SEL 12 15 AFMT_AUDIO_CRC_COUNT 16 31 mmDIG1_AFMT_RAMP_CONTROL0 0 0x19b9 2 0 2 AFMT_RAMP_MAX_COUNT 0 23 AFMT_RAMP_DATA_SIGN 31 31 mmDIG1_AFMT_RAMP_CONTROL1 0 0x19ba 2 0 2 AFMT_RAMP_MIN_COUNT 0 23 AFMT_AUDIO_TEST_CH_DISABLE 24 31 mmDIG1_AFMT_RAMP_CONTROL2 0 0x19bb 1 0 2 AFMT_RAMP_INC_COUNT 0 23 mmDIG1_AFMT_RAMP_CONTROL3 0 0x19bc 1 0 2 AFMT_RAMP_DEC_COUNT 0 23 mmDIG1_AFMT_60958_2 0 0x19bd 6 0 2 AFMT_60958_CS_CHANNEL_NUMBER_2 0 3 AFMT_60958_CS_CHANNEL_NUMBER_3 4 7 AFMT_60958_CS_CHANNEL_NUMBER_4 8 11 AFMT_60958_CS_CHANNEL_NUMBER_5 12 15 AFMT_60958_CS_CHANNEL_NUMBER_6 16 19 AFMT_60958_CS_CHANNEL_NUMBER_7 20 23 mmDIG1_AFMT_AUDIO_CRC_RESULT 0 0x19be 2 0 2 AFMT_AUDIO_CRC_DONE 0 0 AFMT_AUDIO_CRC 8 31 mmDIG1_AFMT_STATUS 0 0x19bf 4 0 2 AFMT_AUDIO_ENABLE 4 4 AFMT_AZ_HBR_ENABLE 8 8 AFMT_AUDIO_FIFO_OVERFLOW 24 24 AFMT_AZ_AUDIO_ENABLE_CHG 30 30 mmDIG1_AFMT_AUDIO_PACKET_CONTROL 0 0x19c0 8 0 2 AFMT_AUDIO_SAMPLE_SEND 0 0 AFMT_RESET_FIFO_WHEN_AUDIO_DIS 11 11 AFMT_AUDIO_TEST_EN 12 12 AFMT_AUDIO_TEST_MODE 14 14 AFMT_AUDIO_FIFO_OVERFLOW_ACK 23 23 AFMT_AUDIO_CHANNEL_SWAP 24 24 AFMT_60958_CS_UPDATE 26 26 AFMT_AZ_AUDIO_ENABLE_CHG_ACK 30 30 mmDIG1_AFMT_VBI_PACKET_CONTROL 0 0x19c1 3 0 2 AFMT_GENERIC0_UPDATE 2 2 AFMT_GENERIC2_UPDATE 3 3 AFMT_GENERIC_INDEX 30 31 mmDIG1_AFMT_INFOFRAME_CONTROL0 0 0x19c2 3 0 2 AFMT_AUDIO_INFO_SOURCE 6 6 AFMT_AUDIO_INFO_UPDATE 7 7 AFMT_MPEG_INFO_UPDATE 10 10 mmDIG1_AFMT_AUDIO_SRC_CONTROL 0 0x19c3 1 0 2 AFMT_AUDIO_SRC_SELECT 0 2 mmDIG1_DIG_BE_CNTL 0 0x19c5 5 0 2 DIG_DUAL_LINK_ENABLE 0 0 DIG_SWAP 1 1 DIG_FE_SOURCE_SELECT 8 14 DIG_MODE 16 18 DIG_HPD_SELECT 28 30 mmDIG1_DIG_BE_EN_CNTL 0 0x19c6 2 0 2 DIG_ENABLE 0 0 DIG_SYMCLK_BE_ON 8 8 mmDIG1_TMDS_CNTL 0 0x19e9 1 0 2 TMDS_SYNC_PHASE 0 0 mmDIG1_TMDS_CONTROL_CHAR 0 0x19ea 4 0 2 TMDS_CONTROL_CHAR0_OUT_EN 0 0 TMDS_CONTROL_CHAR1_OUT_EN 1 1 TMDS_CONTROL_CHAR2_OUT_EN 2 2 TMDS_CONTROL_CHAR3_OUT_EN 3 3 mmDIG1_TMDS_CONTROL0_FEEDBACK 0 0x19eb 2 0 2 TMDS_CONTROL0_FEEDBACK_SELECT 0 1 TMDS_CONTROL0_FEEDBACK_DELAY 8 9 mmDIG1_TMDS_STEREOSYNC_CTL_SEL 0 0x19ec 1 0 2 TMDS_STEREOSYNC_CTL_SEL 0 1 mmDIG1_TMDS_SYNC_CHAR_PATTERN_0_1 0 0x19ed 2 0 2 TMDS_SYNC_CHAR_PATTERN0 0 9 TMDS_SYNC_CHAR_PATTERN1 16 25 mmDIG1_TMDS_SYNC_CHAR_PATTERN_2_3 0 0x19ee 2 0 2 TMDS_SYNC_CHAR_PATTERN2 0 9 TMDS_SYNC_CHAR_PATTERN3 16 25 mmDIG1_TMDS_CTL_BITS 0 0x19f0 4 0 2 TMDS_CTL0 0 0 TMDS_CTL1 8 8 TMDS_CTL2 16 16 TMDS_CTL3 24 24 mmDIG1_TMDS_DCBALANCER_CONTROL 0 0x19f1 4 0 2 TMDS_DCBALANCER_EN 0 0 TMDS_DCBALANCER_TEST_EN 8 8 TMDS_DCBALANCER_TEST_IN 16 19 TMDS_DCBALANCER_FORCE 24 24 mmDIG1_TMDS_CTL0_1_GEN_CNTL 0 0x19f3 15 0 2 TMDS_CTL0_DATA_SEL 0 3 TMDS_CTL0_DATA_DELAY 4 6 TMDS_CTL0_DATA_INVERT 7 7 TMDS_CTL0_DATA_MODULATION 8 9 TMDS_CTL0_USE_FEEDBACK_PATH 10 10 TMDS_CTL0_FB_SYNC_CONT 11 11 TMDS_CTL0_PATTERN_OUT_EN 12 12 TMDS_CTL1_DATA_SEL 16 19 TMDS_CTL1_DATA_DELAY 20 22 TMDS_CTL1_DATA_INVERT 23 23 TMDS_CTL1_DATA_MODULATION 24 25 TMDS_CTL1_USE_FEEDBACK_PATH 26 26 TMDS_CTL1_FB_SYNC_CONT 27 27 TMDS_CTL1_PATTERN_OUT_EN 28 28 TMDS_2BIT_COUNTER_EN 31 31 mmDIG1_TMDS_CTL2_3_GEN_CNTL 0 0x19f4 14 0 2 TMDS_CTL2_DATA_SEL 0 3 TMDS_CTL2_DATA_DELAY 4 6 TMDS_CTL2_DATA_INVERT 7 7 TMDS_CTL2_DATA_MODULATION 8 9 TMDS_CTL2_USE_FEEDBACK_PATH 10 10 TMDS_CTL2_FB_SYNC_CONT 11 11 TMDS_CTL2_PATTERN_OUT_EN 12 12 TMDS_CTL3_DATA_SEL 16 19 TMDS_CTL3_DATA_DELAY 20 22 TMDS_CTL3_DATA_INVERT 23 23 TMDS_CTL3_DATA_MODULATION 24 25 TMDS_CTL3_USE_FEEDBACK_PATH 26 26 TMDS_CTL3_FB_SYNC_CONT 27 27 TMDS_CTL3_PATTERN_OUT_EN 28 28 mmDIG1_DIG_VERSION 0 0x19f6 1 0 2 DIG_TYPE 0 0 mmDIG1_DIG_LANE_ENABLE 0 0x19f7 5 0 2 DIG_LANE0EN 0 0 DIG_LANE1EN 1 1 DIG_LANE2EN 2 2 DIG_LANE3EN 3 3 DIG_CLK_EN 8 8 mmDIG1_AFMT_CNTL 0 0x19fc 2 0 2 AFMT_AUDIO_CLOCK_EN 0 0 AFMT_AUDIO_CLOCK_ON 8 8 mmDP1_DP_LINK_CNTL 0 0x1a1e 3 0 2 DP_LINK_TRAINING_COMPLETE 4 4 DP_LINK_STATUS 8 8 DP_EMBEDDED_PANEL_MODE 17 17 mmDP1_DP_PIXEL_FORMAT 0 0x1a1f 4 0 2 DP_PIXEL_ENCODING 0 2 DP_DYN_RANGE 8 8 DP_YCBCR_RANGE 16 16 DP_COMPONENT_DEPTH 24 26 mmDP1_DP_MSA_COLORIMETRY 0 0x1a20 4 0 2 DP_MSA_MISC0_OVERRIDE 0 7 DP_MSA_MISC0_OVERRIDE_ENABLE 8 8 DP_MSA_MISC1_BIT7_OVERRIDE 9 9 DP_MSA_MISC1_BIT7_OVERRIDE_ENABLE 17 17 mmDP1_DP_CONFIG 0 0x1a21 1 0 2 DP_UDI_LANES 0 1 mmDP1_DP_VID_STREAM_CNTL 0 0x1a22 4 0 2 DP_VID_STREAM_ENABLE 0 0 DP_VID_STREAM_DIS_DEFER 8 9 DP_VID_STREAM_STATUS 16 16 DP_VID_STREAM_CHANGE_KEEPOUT 20 20 mmDP1_DP_STEER_FIFO 0 0x1a23 7 0 2 DP_STEER_FIFO_RESET 0 0 DP_STEER_OVERFLOW_FLAG 4 4 DP_STEER_OVERFLOW_INT 5 5 DP_STEER_OVERFLOW_ACK 6 6 DP_STEER_OVERFLOW_MASK 7 7 DP_TU_OVERFLOW_FLAG 8 8 DP_TU_OVERFLOW_ACK 12 12 mmDP1_DP_MSA_MISC 0 0x1a24 4 0 2 DP_MSA_MISC1 3 6 DP_MSA_MISC2 8 15 DP_MSA_MISC3 16 23 DP_MSA_MISC4 24 31 mmDP1_DP_VID_TIMING 0 0x1a26 5 0 2 DP_VID_TIMING_MODE 0 0 DP_VID_M_N_DOUBLE_BUFFER_MODE 4 4 DP_VID_M_N_GEN_EN 8 8 DP_VID_M_DOUBLE_VALUE_EN 9 9 DP_VID_N_DIV 24 31 mmDP1_DP_VID_N 0 0x1a27 1 0 2 DP_VID_N 0 23 mmDP1_DP_VID_M 0 0x1a28 1 0 2 DP_VID_M 0 23 mmDP1_DP_LINK_FRAMING_CNTL 0 0x1a29 3 0 2 DP_IDLE_BS_INTERVAL 0 17 DP_VBID_DISABLE 24 24 DP_VID_ENHANCED_FRAME_MODE 28 28 mmDP1_DP_HBR2_EYE_PATTERN 0 0x1a2a 1 0 2 DP_HBR2_EYE_PATTERN_ENABLE 0 0 mmDP1_DP_VID_MSA_VBID 0 0x1a2b 3 0 2 DP_VID_MSA_LOCATION 0 11 DP_VID_MSA_TOP_FIELD_MODE 16 16 DP_VID_VBID_FIELD_POL 24 24 mmDP1_DP_VID_INTERRUPT_CNTL 0 0x1a2c 3 0 2 DP_VID_STREAM_DISABLE_INT 0 0 DP_VID_STREAM_DISABLE_ACK 1 1 DP_VID_STREAM_DISABLE_MASK 2 2 mmDP1_DP_DPHY_CNTL 0 0x1a2d 6 0 2 DPHY_ATEST_SEL_LANE0 0 0 DPHY_ATEST_SEL_LANE1 1 1 DPHY_ATEST_SEL_LANE2 2 2 DPHY_ATEST_SEL_LANE3 3 3 DPHY_BYPASS 16 16 DPHY_SKEW_BYPASS 24 24 mmDP1_DP_DPHY_TRAINING_PATTERN_SEL 0 0x1a2e 1 0 2 DPHY_TRAINING_PATTERN_SEL 0 1 mmDP1_DP_DPHY_SYM0 0 0x1a2f 3 0 2 DPHY_SYM1 0 9 DPHY_SYM2 10 19 DPHY_SYM3 20 29 mmDP1_DP_DPHY_SYM1 0 0x1a30 3 0 2 DPHY_SYM4 0 9 DPHY_SYM5 10 19 DPHY_SYM6 20 29 mmDP1_DP_DPHY_SYM2 0 0x1a31 2 0 2 DPHY_SYM7 0 9 DPHY_SYM8 10 19 mmDP1_DP_DPHY_8B10B_CNTL 0 0x1a32 3 0 2 DPHY_8B10B_RESET 8 8 DPHY_8B10B_EXT_DISP 16 16 DPHY_8B10B_CUR_DISP 24 24 mmDP1_DP_DPHY_PRBS_CNTL 0 0x1a33 3 0 2 DPHY_PRBS_EN 0 0 DPHY_PRBS_SEL 4 5 DPHY_PRBS_SEED 8 30 mmDP1_DP_DPHY_SCRAM_CNTL 0 0x1a34 4 0 2 DPHY_SCRAMBLER_DIS 0 0 DPHY_SCRAMBLER_ADVANCE 4 4 DPHY_SCRAMBLER_BS_COUNT 8 17 DPHY_SCRAMBLER_KCODE 24 24 mmDP1_DP_DPHY_CRC_EN 0 0x1a35 3 0 2 DPHY_CRC_EN 0 0 DPHY_CRC_CONT_EN 4 4 DPHY_CRC_RESULT_VALID 8 8 mmDP1_DP_DPHY_CRC_CNTL 0 0x1a36 3 0 2 DPHY_CRC_FIELD 0 0 DPHY_CRC_SEL 4 5 DPHY_CRC_MASK 16 23 mmDP1_DP_DPHY_CRC_RESULT 0 0x1a37 4 0 2 DPHY_CRC_RESULT 0 7 DPHY_CRC_RESULT1 8 15 DPHY_CRC_RESULT2 16 23 DPHY_CRC_RESULT3 24 31 mmDP1_DP_DPHY_CRC_MST_CNTL 0 0x1a38 2 0 2 DPHY_CRC_MST_FIRST_SLOT 0 5 DPHY_CRC_MST_LAST_SLOT 8 13 mmDP1_DP_DPHY_CRC_MST_STATUS 0 0x1a39 3 0 2 DPHY_CRC_MST_PHASE_LOCK 0 0 DPHY_CRC_MST_PHASE_ERROR 8 8 DPHY_CRC_MST_PHASE_ERROR_ACK 16 16 mmDP1_DP_DPHY_FAST_TRAINING 0 0x1a3a 5 0 2 DPHY_RX_FAST_TRAINING_CAPABLE 0 0 DPHY_SW_FAST_TRAINING_START 1 1 DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN 2 2 DPHY_FAST_TRAINING_TP1_TIME 8 19 DPHY_FAST_TRAINING_TP2_TIME 20 31 mmDP1_DP_DPHY_FAST_TRAINING_STATUS 0 0x1a3b 4 0 2 DPHY_FAST_TRAINING_STATE 0 2 DPHY_FAST_TRAINING_COMPLETE_OCCURRED 4 4 DPHY_FAST_TRAINING_COMPLETE_MASK 8 8 DPHY_FAST_TRAINING_COMPLETE_ACK 12 12 mmDP1_DP_MSA_V_TIMING_OVERRIDE1 0 0x1a3c 2 0 2 DP_MSA_V_TIMING_OVERRIDE_EN 0 0 DP_MSA_V_TOTAL_OVERRIDE 4 17 mmDP1_DP_MSA_V_TIMING_OVERRIDE2 0 0x1a3d 2 0 2 DP_MSA_V_BLANK_START_OVERRIDE 0 13 DP_MSA_V_BLANK_END_OVERRIDE 16 29 mmDP1_DP_SEC_CNTL 0 0x1a41 11 0 2 DP_SEC_STREAM_ENABLE 0 0 DP_SEC_ASP_ENABLE 4 4 DP_SEC_ATP_ENABLE 8 8 DP_SEC_AIP_ENABLE 12 12 DP_SEC_ACM_ENABLE 16 16 DP_SEC_GSP0_ENABLE 20 20 DP_SEC_GSP1_ENABLE 21 21 DP_SEC_GSP2_ENABLE 22 22 DP_SEC_GSP3_ENABLE 23 23 DP_SEC_AVI_ENABLE 24 24 DP_SEC_MPG_ENABLE 28 28 mmDP1_DP_SEC_CNTL1 0 0x1a42 6 0 2 DP_SEC_ISRC_ENABLE 0 0 DP_SEC_GSP0_PRIORITY 4 4 DP_SEC_GSP0_SEND 5 5 DP_SEC_GSP0_SEND_PENDING 6 6 DP_SEC_GSP0_SEND_DEADLINE_MISSED 7 7 DP_SEC_GSP0_LINE_NUM 16 31 mmDP1_DP_SEC_FRAMING1 0 0x1a43 2 0 2 DP_SEC_FRAME_START_LOCATION 0 11 DP_SEC_VBLANK_TRANSMIT_WIDTH 16 31 mmDP1_DP_SEC_FRAMING2 0 0x1a44 2 0 2 DP_SEC_START_POSITION 0 15 DP_SEC_HBLANK_TRANSMIT_WIDTH 16 31 mmDP1_DP_SEC_FRAMING3 0 0x1a45 2 0 2 DP_SEC_IDLE_FRAME_SIZE 0 13 DP_SEC_IDLE_TRANSMIT_WIDTH 16 31 mmDP1_DP_SEC_FRAMING4 0 0x1a46 4 0 2 DP_SEC_COLLISION_STATUS 20 20 DP_SEC_COLLISION_ACK 24 24 DP_SEC_AUDIO_MUTE 28 28 DP_SEC_AUDIO_MUTE_STATUS 29 29 mmDP1_DP_SEC_AUD_N 0 0x1a47 1 0 2 DP_SEC_AUD_N 0 23 mmDP1_DP_SEC_AUD_N_READBACK 0 0x1a48 1 0 2 DP_SEC_AUD_N_READBACK 0 23 mmDP1_DP_SEC_AUD_M 0 0x1a49 1 0 2 DP_SEC_AUD_M 0 23 mmDP1_DP_SEC_AUD_M_READBACK 0 0x1a4a 1 0 2 DP_SEC_AUD_M_READBACK 0 23 mmDP1_DP_SEC_TIMESTAMP 0 0x1a4b 1 0 2 DP_SEC_TIMESTAMP_MODE 0 0 mmDP1_DP_SEC_PACKET_CNTL 0 0x1a4c 4 0 2 DP_SEC_ASP_CODING_TYPE 1 3 DP_SEC_ASP_PRIORITY 4 4 DP_SEC_VERSION 8 13 DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE 16 16 mmDP1_DP_MSE_RATE_CNTL 0 0x1a4d 2 0 2 DP_MSE_RATE_Y 0 25 DP_MSE_RATE_X 26 31 mmDP1_DP_MSE_RATE_UPDATE 0 0x1a4f 1 0 2 DP_MSE_RATE_UPDATE_PENDING 0 0 mmDP1_DP_MSE_SAT0 0 0x1a50 4 0 2 DP_MSE_SAT_SRC0 0 2 DP_MSE_SAT_SLOT_COUNT0 8 13 DP_MSE_SAT_SRC1 16 18 DP_MSE_SAT_SLOT_COUNT1 24 29 mmDP1_DP_MSE_SAT1 0 0x1a51 4 0 2 DP_MSE_SAT_SRC2 0 2 DP_MSE_SAT_SLOT_COUNT2 8 13 DP_MSE_SAT_SRC3 16 18 DP_MSE_SAT_SLOT_COUNT3 24 29 mmDP1_DP_MSE_SAT2 0 0x1a52 4 0 2 DP_MSE_SAT_SRC4 0 2 DP_MSE_SAT_SLOT_COUNT4 8 13 DP_MSE_SAT_SRC5 16 18 DP_MSE_SAT_SLOT_COUNT5 24 29 mmDP1_DP_MSE_SAT_UPDATE 0 0x1a53 2 0 2 DP_MSE_SAT_UPDATE 0 1 DP_MSE_16_MTP_KEEPOUT 8 8 mmDP1_DP_MSE_LINK_TIMING 0 0x1a54 2 0 2 DP_MSE_LINK_FRAME 0 9 DP_MSE_LINK_LINE 16 17 mmDP1_DP_MSE_MISC_CNTL 0 0x1a55 3 0 2 DP_MSE_BLANK_CODE 0 0 DP_MSE_TIMESTAMP_MODE 4 4 DP_MSE_ZERO_ENCODER 8 8 mmDP1_DP_DPHY_BS_SR_SWAP_CNTL 0 0x1a5a 3 0 2 DPHY_LOAD_BS_COUNT 0 9 DPHY_BS_SR_SWAP_DONE 15 15 DPHY_LOAD_BS_COUNT_START 16 16 mmDP1_DP_DPHY_HBR2_PATTERN_CONTROL 0 0x1a5b 1 0 2 DP_DPHY_HBR2_PATTERN_CONTROL 0 2 mmDP1_DP_MSE_SAT0_STATUS 0 0x1a5d 4 0 2 DP_MSE_SAT_SRC0_STATUS 0 2 DP_MSE_SAT_SLOT_COUNT0_STATUS 8 13 DP_MSE_SAT_SRC1_STATUS 16 18 DP_MSE_SAT_SLOT_COUNT1_STATUS 24 29 mmDP1_DP_MSE_SAT1_STATUS 0 0x1a5e 4 0 2 DP_MSE_SAT_SRC2_STATUS 0 2 DP_MSE_SAT_SLOT_COUNT2_STATUS 8 13 DP_MSE_SAT_SRC3_STATUS 16 18 DP_MSE_SAT_SLOT_COUNT3_STATUS 24 29 mmDP1_DP_MSE_SAT2_STATUS 0 0x1a5f 4 0 2 DP_MSE_SAT_SRC4_STATUS 0 2 DP_MSE_SAT_SLOT_COUNT4_STATUS 8 13 DP_MSE_SAT_SRC5_STATUS 16 18 DP_MSE_SAT_SLOT_COUNT5_STATUS 24 29 mmDIG2_DIG_FE_CNTL 0 0x1a7e 7 0 2 DIG_SOURCE_SELECT 0 2 DIG_STEREOSYNC_SELECT 4 6 DIG_STEREOSYNC_GATE_EN 8 8 DIG_START 10 10 DIG_SYMCLK_FE_ON 24 24 TMDS_PIXEL_ENCODING 28 28 TMDS_COLOR_FORMAT 30 31 mmDIG2_DIG_OUTPUT_CRC_CNTL 0 0x1a7f 3 0 2 DIG_OUTPUT_CRC_EN 0 0 DIG_OUTPUT_CRC_LINK_SEL 4 4 DIG_OUTPUT_CRC_DATA_SEL 8 9 mmDIG2_DIG_OUTPUT_CRC_RESULT 0 0x1a80 1 0 2 DIG_OUTPUT_CRC_RESULT 0 29 mmDIG2_DIG_CLOCK_PATTERN 0 0x1a81 1 0 2 DIG_CLOCK_PATTERN 0 9 mmDIG2_DIG_TEST_PATTERN 0 0x1a82 6 0 2 DIG_TEST_PATTERN_OUT_EN 0 0 DIG_HALF_CLOCK_PATTERN_SEL 1 1 DIG_RANDOM_PATTERN_OUT_EN 4 4 DIG_RANDOM_PATTERN_RESET 5 5 DIG_TEST_PATTERN_EXTERNAL_RESET_EN 6 6 DIG_STATIC_TEST_PATTERN 16 25 mmDIG2_DIG_RANDOM_PATTERN_SEED 0 0x1a83 2 0 2 DIG_RANDOM_PATTERN_SEED 0 23 DIG_RAN_PAT_DURING_DE_ONLY 24 24 mmDIG2_DIG_FIFO_STATUS 0 0x1a84 11 0 2 DIG_FIFO_LEVEL_ERROR 0 0 DIG_FIFO_USE_OVERWRITE_LEVEL 1 1 DIG_FIFO_OVERWRITE_LEVEL 2 7 DIG_FIFO_ERROR_ACK 8 8 DIG_FIFO_CAL_AVERAGE_LEVEL 10 15 DIG_FIFO_MAXIMUM_LEVEL 16 20 DIG_FIFO_MINIMUM_LEVEL 22 25 DIG_FIFO_READ_CLOCK_SRC 26 26 DIG_FIFO_CALIBRATED 29 29 DIG_FIFO_FORCE_RECAL_AVERAGE 30 30 DIG_FIFO_FORCE_RECOMP_MINMAX 31 31 mmDIG2_HDMI_CONTROL 0 0x1a87 9 0 2 HDMI_KEEPOUT_MODE 0 0 HDMI_DATA_SCRAMBLE_EN 1 1 HDMI_CLOCK_CHANNEL_RATE 2 2 HDMI_NO_EXTRA_NULL_PACKET_FILLED 3 3 HDMI_PACKET_GEN_VERSION 4 4 HDMI_ERROR_ACK 8 8 HDMI_ERROR_MASK 9 9 HDMI_DEEP_COLOR_ENABLE 24 24 HDMI_DEEP_COLOR_DEPTH 28 29 mmDIG2_HDMI_STATUS 0 0x1a88 4 0 2 HDMI_ACTIVE_AVMUTE 0 0 HDMI_AUDIO_PACKET_ERROR 16 16 HDMI_VBI_PACKET_ERROR 20 20 HDMI_ERROR_INT 27 27 mmDIG2_HDMI_AUDIO_PACKET_CONTROL 0 0x1a89 2 0 2 HDMI_AUDIO_DELAY_EN 4 5 HDMI_AUDIO_PACKETS_PER_LINE 16 20 mmDIG2_HDMI_ACR_PACKET_CONTROL 0 0x1a8a 7 0 2 HDMI_ACR_SEND 0 0 HDMI_ACR_CONT 1 1 HDMI_ACR_SELECT 4 5 HDMI_ACR_SOURCE 8 8 HDMI_ACR_AUTO_SEND 12 12 HDMI_ACR_N_MULTIPLE 16 18 HDMI_ACR_AUDIO_PRIORITY 31 31 mmDIG2_HDMI_VBI_PACKET_CONTROL 0 0x1a8b 6 0 2 HDMI_NULL_SEND 0 0 HDMI_GC_SEND 4 4 HDMI_GC_CONT 5 5 HDMI_ISRC_SEND 8 8 HDMI_ISRC_CONT 9 9 HDMI_ISRC_LINE 16 21 mmDIG2_HDMI_INFOFRAME_CONTROL0 0 0x1a8c 6 0 2 HDMI_AVI_INFO_SEND 0 0 HDMI_AVI_INFO_CONT 1 1 HDMI_AUDIO_INFO_SEND 4 4 HDMI_AUDIO_INFO_CONT 5 5 HDMI_MPEG_INFO_SEND 8 8 HDMI_MPEG_INFO_CONT 9 9 mmDIG2_HDMI_INFOFRAME_CONTROL1 0 0x1a8d 3 0 2 HDMI_AVI_INFO_LINE 0 5 HDMI_AUDIO_INFO_LINE 8 13 HDMI_MPEG_INFO_LINE 16 21 mmDIG2_HDMI_GENERIC_PACKET_CONTROL0 0 0x1a8e 6 0 2 HDMI_GENERIC0_SEND 0 0 HDMI_GENERIC0_CONT 1 1 HDMI_GENERIC1_SEND 4 4 HDMI_GENERIC1_CONT 5 5 HDMI_GENERIC0_LINE 16 21 HDMI_GENERIC1_LINE 24 29 mmDIG2_AFMT_INTERRUPT_STATUS 0 0x1a8f 0 0 2 mmDIG2_HDMI_GC 0 0x1a91 5 0 2 HDMI_GC_AVMUTE 0 0 HDMI_GC_AVMUTE_CONT 2 2 HDMI_DEFAULT_PHASE 4 4 HDMI_PACKING_PHASE 8 11 HDMI_PACKING_PHASE_OVERRIDE 12 12 mmDIG2_AFMT_AUDIO_PACKET_CONTROL2 0 0x1a92 6 0 2 AFMT_AUDIO_LAYOUT_OVRD 0 0 AFMT_AUDIO_LAYOUT_SELECT 1 1 AFMT_AUDIO_CHANNEL_ENABLE 8 15 AFMT_DP_AUDIO_STREAM_ID 16 23 AFMT_HBR_ENABLE_OVRD 24 24 AFMT_60958_OSF_OVRD 28 28 mmDIG2_AFMT_ISRC1_0 0 0x1a93 3 0 2 AFMT_ISRC_STATUS 0 2 AFMT_ISRC_CONTINUE 6 6 AFMT_ISRC_VALID 7 7 mmDIG2_AFMT_ISRC1_1 0 0x1a94 4 0 2 AFMT_UPC_EAN_ISRC0 0 7 AFMT_UPC_EAN_ISRC1 8 15 AFMT_UPC_EAN_ISRC2 16 23 AFMT_UPC_EAN_ISRC3 24 31 mmDIG2_AFMT_ISRC1_2 0 0x1a95 4 0 2 AFMT_UPC_EAN_ISRC4 0 7 AFMT_UPC_EAN_ISRC5 8 15 AFMT_UPC_EAN_ISRC6 16 23 AFMT_UPC_EAN_ISRC7 24 31 mmDIG2_AFMT_ISRC1_3 0 0x1a96 4 0 2 AFMT_UPC_EAN_ISRC8 0 7 AFMT_UPC_EAN_ISRC9 8 15 AFMT_UPC_EAN_ISRC10 16 23 AFMT_UPC_EAN_ISRC11 24 31 mmDIG2_AFMT_ISRC1_4 0 0x1a97 4 0 2 AFMT_UPC_EAN_ISRC12 0 7 AFMT_UPC_EAN_ISRC13 8 15 AFMT_UPC_EAN_ISRC14 16 23 AFMT_UPC_EAN_ISRC15 24 31 mmDIG2_AFMT_ISRC2_0 0 0x1a98 4 0 2 AFMT_UPC_EAN_ISRC16 0 7 AFMT_UPC_EAN_ISRC17 8 15 AFMT_UPC_EAN_ISRC18 16 23 AFMT_UPC_EAN_ISRC19 24 31 mmDIG2_AFMT_ISRC2_1 0 0x1a99 4 0 2 AFMT_UPC_EAN_ISRC20 0 7 AFMT_UPC_EAN_ISRC21 8 15 AFMT_UPC_EAN_ISRC22 16 23 AFMT_UPC_EAN_ISRC23 24 31 mmDIG2_AFMT_ISRC2_2 0 0x1a9a 4 0 2 AFMT_UPC_EAN_ISRC24 0 7 AFMT_UPC_EAN_ISRC25 8 15 AFMT_UPC_EAN_ISRC26 16 23 AFMT_UPC_EAN_ISRC27 24 31 mmDIG2_AFMT_ISRC2_3 0 0x1a9b 4 0 2 AFMT_UPC_EAN_ISRC28 0 7 AFMT_UPC_EAN_ISRC29 8 15 AFMT_UPC_EAN_ISRC30 16 23 AFMT_UPC_EAN_ISRC31 24 31 mmDIG2_AFMT_AVI_INFO0 0 0x1a9c 12 0 2 AFMT_AVI_INFO_CHECKSUM 0 7 AFMT_AVI_INFO_S 8 9 AFMT_AVI_INFO_B 10 11 AFMT_AVI_INFO_A 12 12 AFMT_AVI_INFO_Y 13 15 AFMT_AVI_INFO_R 16 19 AFMT_AVI_INFO_M 20 21 AFMT_AVI_INFO_C 22 23 AFMT_AVI_INFO_SC 24 25 AFMT_AVI_INFO_Q 26 27 AFMT_AVI_INFO_EC 28 30 AFMT_AVI_INFO_ITC 31 31 mmDIG2_AFMT_AVI_INFO1 0 0x1a9d 5 0 2 AFMT_AVI_INFO_VIC 0 7 AFMT_AVI_INFO_PR 8 11 AFMT_AVI_INFO_CN 12 13 AFMT_AVI_INFO_YQ 14 15 AFMT_AVI_INFO_TOP 16 31 mmDIG2_AFMT_AVI_INFO2 0 0x1a9e 2 0 2 AFMT_AVI_INFO_BOTTOM 0 15 AFMT_AVI_INFO_LEFT 16 31 mmDIG2_AFMT_AVI_INFO3 0 0x1a9f 2 0 2 AFMT_AVI_INFO_RIGHT 0 15 AFMT_AVI_INFO_VERSION 24 31 mmDIG2_AFMT_MPEG_INFO0 0 0x1aa0 4 0 2 AFMT_MPEG_INFO_CHECKSUM 0 7 AFMT_MPEG_INFO_MB0 8 15 AFMT_MPEG_INFO_MB1 16 23 AFMT_MPEG_INFO_MB2 24 31 mmDIG2_AFMT_MPEG_INFO1 0 0x1aa1 3 0 2 AFMT_MPEG_INFO_MB3 0 7 AFMT_MPEG_INFO_MF 8 9 AFMT_MPEG_INFO_FR 12 12 mmDIG2_AFMT_GENERIC_HDR 0 0x1aa2 4 0 2 AFMT_GENERIC_HB0 0 7 AFMT_GENERIC_HB1 8 15 AFMT_GENERIC_HB2 16 23 AFMT_GENERIC_HB3 24 31 mmDIG2_AFMT_GENERIC_0 0 0x1aa3 4 0 2 AFMT_GENERIC_BYTE0 0 7 AFMT_GENERIC_BYTE1 8 15 AFMT_GENERIC_BYTE2 16 23 AFMT_GENERIC_BYTE3 24 31 mmDIG2_AFMT_GENERIC_1 0 0x1aa4 4 0 2 AFMT_GENERIC_BYTE4 0 7 AFMT_GENERIC_BYTE5 8 15 AFMT_GENERIC_BYTE6 16 23 AFMT_GENERIC_BYTE7 24 31 mmDIG2_AFMT_GENERIC_2 0 0x1aa5 4 0 2 AFMT_GENERIC_BYTE8 0 7 AFMT_GENERIC_BYTE9 8 15 AFMT_GENERIC_BYTE10 16 23 AFMT_GENERIC_BYTE11 24 31 mmDIG2_AFMT_GENERIC_3 0 0x1aa6 4 0 2 AFMT_GENERIC_BYTE12 0 7 AFMT_GENERIC_BYTE13 8 15 AFMT_GENERIC_BYTE14 16 23 AFMT_GENERIC_BYTE15 24 31 mmDIG2_AFMT_GENERIC_4 0 0x1aa7 4 0 2 AFMT_GENERIC_BYTE16 0 7 AFMT_GENERIC_BYTE17 8 15 AFMT_GENERIC_BYTE18 16 23 AFMT_GENERIC_BYTE19 24 31 mmDIG2_AFMT_GENERIC_5 0 0x1aa8 4 0 2 AFMT_GENERIC_BYTE20 0 7 AFMT_GENERIC_BYTE21 8 15 AFMT_GENERIC_BYTE22 16 23 AFMT_GENERIC_BYTE23 24 31 mmDIG2_AFMT_GENERIC_6 0 0x1aa9 4 0 2 AFMT_GENERIC_BYTE24 0 7 AFMT_GENERIC_BYTE25 8 15 AFMT_GENERIC_BYTE26 16 23 AFMT_GENERIC_BYTE27 24 31 mmDIG2_AFMT_GENERIC_7 0 0x1aaa 4 0 2 AFMT_GENERIC_BYTE28 0 7 AFMT_GENERIC_BYTE29 8 15 AFMT_GENERIC_BYTE30 16 23 AFMT_GENERIC_BYTE31 24 31 mmDIG2_HDMI_GENERIC_PACKET_CONTROL1 0 0x1aab 6 0 2 HDMI_GENERIC2_SEND 0 0 HDMI_GENERIC2_CONT 1 1 HDMI_GENERIC3_SEND 4 4 HDMI_GENERIC3_CONT 5 5 HDMI_GENERIC2_LINE 16 21 HDMI_GENERIC3_LINE 24 29 mmDIG2_HDMI_ACR_32_0 0 0x1aac 1 0 2 HDMI_ACR_CTS_32 12 31 mmDIG2_HDMI_ACR_32_1 0 0x1aad 1 0 2 HDMI_ACR_N_32 0 19 mmDIG2_HDMI_ACR_44_0 0 0x1aae 1 0 2 HDMI_ACR_CTS_44 12 31 mmDIG2_HDMI_ACR_44_1 0 0x1aaf 1 0 2 HDMI_ACR_N_44 0 19 mmDIG2_HDMI_ACR_48_0 0 0x1ab0 1 0 2 HDMI_ACR_CTS_48 12 31 mmDIG2_HDMI_ACR_48_1 0 0x1ab1 1 0 2 HDMI_ACR_N_48 0 19 mmDIG2_HDMI_ACR_STATUS_0 0 0x1ab2 1 0 2 HDMI_ACR_CTS 12 31 mmDIG2_HDMI_ACR_STATUS_1 0 0x1ab3 1 0 2 HDMI_ACR_N 0 19 mmDIG2_AFMT_AUDIO_INFO0 0 0x1ab4 5 0 2 AFMT_AUDIO_INFO_CHECKSUM 0 7 AFMT_AUDIO_INFO_CC 8 10 AFMT_AUDIO_INFO_CT 11 14 AFMT_AUDIO_INFO_CHECKSUM_OFFSET 16 23 AFMT_AUDIO_INFO_CXT 24 28 mmDIG2_AFMT_AUDIO_INFO1 0 0x1ab5 4 0 2 AFMT_AUDIO_INFO_CA 0 7 AFMT_AUDIO_INFO_LSV 11 14 AFMT_AUDIO_INFO_DM_INH 15 15 AFMT_AUDIO_INFO_LFEPBL 16 17 mmDIG2_AFMT_60958_0 0 0x1ab6 10 0 2 AFMT_60958_CS_A 0 0 AFMT_60958_CS_B 1 1 AFMT_60958_CS_C 2 2 AFMT_60958_CS_D 3 5 AFMT_60958_CS_MODE 6 7 AFMT_60958_CS_CATEGORY_CODE 8 15 AFMT_60958_CS_SOURCE_NUMBER 16 19 AFMT_60958_CS_CHANNEL_NUMBER_L 20 23 AFMT_60958_CS_SAMPLING_FREQUENCY 24 27 AFMT_60958_CS_CLOCK_ACCURACY 28 29 mmDIG2_AFMT_60958_1 0 0x1ab7 5 0 2 AFMT_60958_CS_WORD_LENGTH 0 3 AFMT_60958_CS_ORIGINAL_SAMPLING_FREQUENCY 4 7 AFMT_60958_VALID_L 16 16 AFMT_60958_VALID_R 18 18 AFMT_60958_CS_CHANNEL_NUMBER_R 20 23 mmDIG2_AFMT_AUDIO_CRC_CONTROL 0 0x1ab8 5 0 2 AFMT_AUDIO_CRC_EN 0 0 AFMT_AUDIO_CRC_CONT 4 4 AFMT_AUDIO_CRC_SOURCE 8 8 AFMT_AUDIO_CRC_CH_SEL 12 15 AFMT_AUDIO_CRC_COUNT 16 31 mmDIG2_AFMT_RAMP_CONTROL0 0 0x1ab9 2 0 2 AFMT_RAMP_MAX_COUNT 0 23 AFMT_RAMP_DATA_SIGN 31 31 mmDIG2_AFMT_RAMP_CONTROL1 0 0x1aba 2 0 2 AFMT_RAMP_MIN_COUNT 0 23 AFMT_AUDIO_TEST_CH_DISABLE 24 31 mmDIG2_AFMT_RAMP_CONTROL2 0 0x1abb 1 0 2 AFMT_RAMP_INC_COUNT 0 23 mmDIG2_AFMT_RAMP_CONTROL3 0 0x1abc 1 0 2 AFMT_RAMP_DEC_COUNT 0 23 mmDIG2_AFMT_60958_2 0 0x1abd 6 0 2 AFMT_60958_CS_CHANNEL_NUMBER_2 0 3 AFMT_60958_CS_CHANNEL_NUMBER_3 4 7 AFMT_60958_CS_CHANNEL_NUMBER_4 8 11 AFMT_60958_CS_CHANNEL_NUMBER_5 12 15 AFMT_60958_CS_CHANNEL_NUMBER_6 16 19 AFMT_60958_CS_CHANNEL_NUMBER_7 20 23 mmDIG2_AFMT_AUDIO_CRC_RESULT 0 0x1abe 2 0 2 AFMT_AUDIO_CRC_DONE 0 0 AFMT_AUDIO_CRC 8 31 mmDIG2_AFMT_STATUS 0 0x1abf 4 0 2 AFMT_AUDIO_ENABLE 4 4 AFMT_AZ_HBR_ENABLE 8 8 AFMT_AUDIO_FIFO_OVERFLOW 24 24 AFMT_AZ_AUDIO_ENABLE_CHG 30 30 mmDIG2_AFMT_AUDIO_PACKET_CONTROL 0 0x1ac0 8 0 2 AFMT_AUDIO_SAMPLE_SEND 0 0 AFMT_RESET_FIFO_WHEN_AUDIO_DIS 11 11 AFMT_AUDIO_TEST_EN 12 12 AFMT_AUDIO_TEST_MODE 14 14 AFMT_AUDIO_FIFO_OVERFLOW_ACK 23 23 AFMT_AUDIO_CHANNEL_SWAP 24 24 AFMT_60958_CS_UPDATE 26 26 AFMT_AZ_AUDIO_ENABLE_CHG_ACK 30 30 mmDIG2_AFMT_VBI_PACKET_CONTROL 0 0x1ac1 3 0 2 AFMT_GENERIC0_UPDATE 2 2 AFMT_GENERIC2_UPDATE 3 3 AFMT_GENERIC_INDEX 30 31 mmDIG2_AFMT_INFOFRAME_CONTROL0 0 0x1ac2 3 0 2 AFMT_AUDIO_INFO_SOURCE 6 6 AFMT_AUDIO_INFO_UPDATE 7 7 AFMT_MPEG_INFO_UPDATE 10 10 mmDIG2_AFMT_AUDIO_SRC_CONTROL 0 0x1ac3 1 0 2 AFMT_AUDIO_SRC_SELECT 0 2 mmDIG2_DIG_BE_CNTL 0 0x1ac5 5 0 2 DIG_DUAL_LINK_ENABLE 0 0 DIG_SWAP 1 1 DIG_FE_SOURCE_SELECT 8 14 DIG_MODE 16 18 DIG_HPD_SELECT 28 30 mmDIG2_DIG_BE_EN_CNTL 0 0x1ac6 2 0 2 DIG_ENABLE 0 0 DIG_SYMCLK_BE_ON 8 8 mmDIG2_TMDS_CNTL 0 0x1ae9 1 0 2 TMDS_SYNC_PHASE 0 0 mmDIG2_TMDS_CONTROL_CHAR 0 0x1aea 4 0 2 TMDS_CONTROL_CHAR0_OUT_EN 0 0 TMDS_CONTROL_CHAR1_OUT_EN 1 1 TMDS_CONTROL_CHAR2_OUT_EN 2 2 TMDS_CONTROL_CHAR3_OUT_EN 3 3 mmDIG2_TMDS_CONTROL0_FEEDBACK 0 0x1aeb 2 0 2 TMDS_CONTROL0_FEEDBACK_SELECT 0 1 TMDS_CONTROL0_FEEDBACK_DELAY 8 9 mmDIG2_TMDS_STEREOSYNC_CTL_SEL 0 0x1aec 1 0 2 TMDS_STEREOSYNC_CTL_SEL 0 1 mmDIG2_TMDS_SYNC_CHAR_PATTERN_0_1 0 0x1aed 2 0 2 TMDS_SYNC_CHAR_PATTERN0 0 9 TMDS_SYNC_CHAR_PATTERN1 16 25 mmDIG2_TMDS_SYNC_CHAR_PATTERN_2_3 0 0x1aee 2 0 2 TMDS_SYNC_CHAR_PATTERN2 0 9 TMDS_SYNC_CHAR_PATTERN3 16 25 mmDIG2_TMDS_CTL_BITS 0 0x1af0 4 0 2 TMDS_CTL0 0 0 TMDS_CTL1 8 8 TMDS_CTL2 16 16 TMDS_CTL3 24 24 mmDIG2_TMDS_DCBALANCER_CONTROL 0 0x1af1 4 0 2 TMDS_DCBALANCER_EN 0 0 TMDS_DCBALANCER_TEST_EN 8 8 TMDS_DCBALANCER_TEST_IN 16 19 TMDS_DCBALANCER_FORCE 24 24 mmDIG2_TMDS_CTL0_1_GEN_CNTL 0 0x1af3 15 0 2 TMDS_CTL0_DATA_SEL 0 3 TMDS_CTL0_DATA_DELAY 4 6 TMDS_CTL0_DATA_INVERT 7 7 TMDS_CTL0_DATA_MODULATION 8 9 TMDS_CTL0_USE_FEEDBACK_PATH 10 10 TMDS_CTL0_FB_SYNC_CONT 11 11 TMDS_CTL0_PATTERN_OUT_EN 12 12 TMDS_CTL1_DATA_SEL 16 19 TMDS_CTL1_DATA_DELAY 20 22 TMDS_CTL1_DATA_INVERT 23 23 TMDS_CTL1_DATA_MODULATION 24 25 TMDS_CTL1_USE_FEEDBACK_PATH 26 26 TMDS_CTL1_FB_SYNC_CONT 27 27 TMDS_CTL1_PATTERN_OUT_EN 28 28 TMDS_2BIT_COUNTER_EN 31 31 mmDIG2_TMDS_CTL2_3_GEN_CNTL 0 0x1af4 14 0 2 TMDS_CTL2_DATA_SEL 0 3 TMDS_CTL2_DATA_DELAY 4 6 TMDS_CTL2_DATA_INVERT 7 7 TMDS_CTL2_DATA_MODULATION 8 9 TMDS_CTL2_USE_FEEDBACK_PATH 10 10 TMDS_CTL2_FB_SYNC_CONT 11 11 TMDS_CTL2_PATTERN_OUT_EN 12 12 TMDS_CTL3_DATA_SEL 16 19 TMDS_CTL3_DATA_DELAY 20 22 TMDS_CTL3_DATA_INVERT 23 23 TMDS_CTL3_DATA_MODULATION 24 25 TMDS_CTL3_USE_FEEDBACK_PATH 26 26 TMDS_CTL3_FB_SYNC_CONT 27 27 TMDS_CTL3_PATTERN_OUT_EN 28 28 mmDIG2_DIG_VERSION 0 0x1af6 1 0 2 DIG_TYPE 0 0 mmDIG2_DIG_LANE_ENABLE 0 0x1af7 5 0 2 DIG_LANE0EN 0 0 DIG_LANE1EN 1 1 DIG_LANE2EN 2 2 DIG_LANE3EN 3 3 DIG_CLK_EN 8 8 mmDIG2_AFMT_CNTL 0 0x1afc 2 0 2 AFMT_AUDIO_CLOCK_EN 0 0 AFMT_AUDIO_CLOCK_ON 8 8 mmDP2_DP_LINK_CNTL 0 0x1b1e 3 0 2 DP_LINK_TRAINING_COMPLETE 4 4 DP_LINK_STATUS 8 8 DP_EMBEDDED_PANEL_MODE 17 17 mmDP2_DP_PIXEL_FORMAT 0 0x1b1f 4 0 2 DP_PIXEL_ENCODING 0 2 DP_DYN_RANGE 8 8 DP_YCBCR_RANGE 16 16 DP_COMPONENT_DEPTH 24 26 mmDP2_DP_MSA_COLORIMETRY 0 0x1b20 4 0 2 DP_MSA_MISC0_OVERRIDE 0 7 DP_MSA_MISC0_OVERRIDE_ENABLE 8 8 DP_MSA_MISC1_BIT7_OVERRIDE 9 9 DP_MSA_MISC1_BIT7_OVERRIDE_ENABLE 17 17 mmDP2_DP_CONFIG 0 0x1b21 1 0 2 DP_UDI_LANES 0 1 mmDP2_DP_VID_STREAM_CNTL 0 0x1b22 4 0 2 DP_VID_STREAM_ENABLE 0 0 DP_VID_STREAM_DIS_DEFER 8 9 DP_VID_STREAM_STATUS 16 16 DP_VID_STREAM_CHANGE_KEEPOUT 20 20 mmDP2_DP_STEER_FIFO 0 0x1b23 7 0 2 DP_STEER_FIFO_RESET 0 0 DP_STEER_OVERFLOW_FLAG 4 4 DP_STEER_OVERFLOW_INT 5 5 DP_STEER_OVERFLOW_ACK 6 6 DP_STEER_OVERFLOW_MASK 7 7 DP_TU_OVERFLOW_FLAG 8 8 DP_TU_OVERFLOW_ACK 12 12 mmDP2_DP_MSA_MISC 0 0x1b24 4 0 2 DP_MSA_MISC1 3 6 DP_MSA_MISC2 8 15 DP_MSA_MISC3 16 23 DP_MSA_MISC4 24 31 mmDP2_DP_VID_TIMING 0 0x1b26 5 0 2 DP_VID_TIMING_MODE 0 0 DP_VID_M_N_DOUBLE_BUFFER_MODE 4 4 DP_VID_M_N_GEN_EN 8 8 DP_VID_M_DOUBLE_VALUE_EN 9 9 DP_VID_N_DIV 24 31 mmDP2_DP_VID_N 0 0x1b27 1 0 2 DP_VID_N 0 23 mmDP2_DP_VID_M 0 0x1b28 1 0 2 DP_VID_M 0 23 mmDP2_DP_LINK_FRAMING_CNTL 0 0x1b29 3 0 2 DP_IDLE_BS_INTERVAL 0 17 DP_VBID_DISABLE 24 24 DP_VID_ENHANCED_FRAME_MODE 28 28 mmDP2_DP_HBR2_EYE_PATTERN 0 0x1b2a 1 0 2 DP_HBR2_EYE_PATTERN_ENABLE 0 0 mmDP2_DP_VID_MSA_VBID 0 0x1b2b 3 0 2 DP_VID_MSA_LOCATION 0 11 DP_VID_MSA_TOP_FIELD_MODE 16 16 DP_VID_VBID_FIELD_POL 24 24 mmDP2_DP_VID_INTERRUPT_CNTL 0 0x1b2c 3 0 2 DP_VID_STREAM_DISABLE_INT 0 0 DP_VID_STREAM_DISABLE_ACK 1 1 DP_VID_STREAM_DISABLE_MASK 2 2 mmDP2_DP_DPHY_CNTL 0 0x1b2d 6 0 2 DPHY_ATEST_SEL_LANE0 0 0 DPHY_ATEST_SEL_LANE1 1 1 DPHY_ATEST_SEL_LANE2 2 2 DPHY_ATEST_SEL_LANE3 3 3 DPHY_BYPASS 16 16 DPHY_SKEW_BYPASS 24 24 mmDP2_DP_DPHY_TRAINING_PATTERN_SEL 0 0x1b2e 1 0 2 DPHY_TRAINING_PATTERN_SEL 0 1 mmDP2_DP_DPHY_SYM0 0 0x1b2f 3 0 2 DPHY_SYM1 0 9 DPHY_SYM2 10 19 DPHY_SYM3 20 29 mmDP2_DP_DPHY_SYM1 0 0x1b30 3 0 2 DPHY_SYM4 0 9 DPHY_SYM5 10 19 DPHY_SYM6 20 29 mmDP2_DP_DPHY_SYM2 0 0x1b31 2 0 2 DPHY_SYM7 0 9 DPHY_SYM8 10 19 mmDP2_DP_DPHY_8B10B_CNTL 0 0x1b32 3 0 2 DPHY_8B10B_RESET 8 8 DPHY_8B10B_EXT_DISP 16 16 DPHY_8B10B_CUR_DISP 24 24 mmDP2_DP_DPHY_PRBS_CNTL 0 0x1b33 3 0 2 DPHY_PRBS_EN 0 0 DPHY_PRBS_SEL 4 5 DPHY_PRBS_SEED 8 30 mmDP2_DP_DPHY_SCRAM_CNTL 0 0x1b34 4 0 2 DPHY_SCRAMBLER_DIS 0 0 DPHY_SCRAMBLER_ADVANCE 4 4 DPHY_SCRAMBLER_BS_COUNT 8 17 DPHY_SCRAMBLER_KCODE 24 24 mmDP2_DP_DPHY_CRC_EN 0 0x1b35 3 0 2 DPHY_CRC_EN 0 0 DPHY_CRC_CONT_EN 4 4 DPHY_CRC_RESULT_VALID 8 8 mmDP2_DP_DPHY_CRC_CNTL 0 0x1b36 3 0 2 DPHY_CRC_FIELD 0 0 DPHY_CRC_SEL 4 5 DPHY_CRC_MASK 16 23 mmDP2_DP_DPHY_CRC_RESULT 0 0x1b37 4 0 2 DPHY_CRC_RESULT 0 7 DPHY_CRC_RESULT1 8 15 DPHY_CRC_RESULT2 16 23 DPHY_CRC_RESULT3 24 31 mmDP2_DP_DPHY_CRC_MST_CNTL 0 0x1b38 2 0 2 DPHY_CRC_MST_FIRST_SLOT 0 5 DPHY_CRC_MST_LAST_SLOT 8 13 mmDP2_DP_DPHY_CRC_MST_STATUS 0 0x1b39 3 0 2 DPHY_CRC_MST_PHASE_LOCK 0 0 DPHY_CRC_MST_PHASE_ERROR 8 8 DPHY_CRC_MST_PHASE_ERROR_ACK 16 16 mmDP2_DP_DPHY_FAST_TRAINING 0 0x1b3a 5 0 2 DPHY_RX_FAST_TRAINING_CAPABLE 0 0 DPHY_SW_FAST_TRAINING_START 1 1 DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN 2 2 DPHY_FAST_TRAINING_TP1_TIME 8 19 DPHY_FAST_TRAINING_TP2_TIME 20 31 mmDP2_DP_DPHY_FAST_TRAINING_STATUS 0 0x1b3b 4 0 2 DPHY_FAST_TRAINING_STATE 0 2 DPHY_FAST_TRAINING_COMPLETE_OCCURRED 4 4 DPHY_FAST_TRAINING_COMPLETE_MASK 8 8 DPHY_FAST_TRAINING_COMPLETE_ACK 12 12 mmDP2_DP_MSA_V_TIMING_OVERRIDE1 0 0x1b3c 2 0 2 DP_MSA_V_TIMING_OVERRIDE_EN 0 0 DP_MSA_V_TOTAL_OVERRIDE 4 17 mmDP2_DP_MSA_V_TIMING_OVERRIDE2 0 0x1b3d 2 0 2 DP_MSA_V_BLANK_START_OVERRIDE 0 13 DP_MSA_V_BLANK_END_OVERRIDE 16 29 mmDP2_DP_SEC_CNTL 0 0x1b41 11 0 2 DP_SEC_STREAM_ENABLE 0 0 DP_SEC_ASP_ENABLE 4 4 DP_SEC_ATP_ENABLE 8 8 DP_SEC_AIP_ENABLE 12 12 DP_SEC_ACM_ENABLE 16 16 DP_SEC_GSP0_ENABLE 20 20 DP_SEC_GSP1_ENABLE 21 21 DP_SEC_GSP2_ENABLE 22 22 DP_SEC_GSP3_ENABLE 23 23 DP_SEC_AVI_ENABLE 24 24 DP_SEC_MPG_ENABLE 28 28 mmDP2_DP_SEC_CNTL1 0 0x1b42 6 0 2 DP_SEC_ISRC_ENABLE 0 0 DP_SEC_GSP0_PRIORITY 4 4 DP_SEC_GSP0_SEND 5 5 DP_SEC_GSP0_SEND_PENDING 6 6 DP_SEC_GSP0_SEND_DEADLINE_MISSED 7 7 DP_SEC_GSP0_LINE_NUM 16 31 mmDP2_DP_SEC_FRAMING1 0 0x1b43 2 0 2 DP_SEC_FRAME_START_LOCATION 0 11 DP_SEC_VBLANK_TRANSMIT_WIDTH 16 31 mmDP2_DP_SEC_FRAMING2 0 0x1b44 2 0 2 DP_SEC_START_POSITION 0 15 DP_SEC_HBLANK_TRANSMIT_WIDTH 16 31 mmDP2_DP_SEC_FRAMING3 0 0x1b45 2 0 2 DP_SEC_IDLE_FRAME_SIZE 0 13 DP_SEC_IDLE_TRANSMIT_WIDTH 16 31 mmDP2_DP_SEC_FRAMING4 0 0x1b46 4 0 2 DP_SEC_COLLISION_STATUS 20 20 DP_SEC_COLLISION_ACK 24 24 DP_SEC_AUDIO_MUTE 28 28 DP_SEC_AUDIO_MUTE_STATUS 29 29 mmDP2_DP_SEC_AUD_N 0 0x1b47 1 0 2 DP_SEC_AUD_N 0 23 mmDP2_DP_SEC_AUD_N_READBACK 0 0x1b48 1 0 2 DP_SEC_AUD_N_READBACK 0 23 mmDP2_DP_SEC_AUD_M 0 0x1b49 1 0 2 DP_SEC_AUD_M 0 23 mmDP2_DP_SEC_AUD_M_READBACK 0 0x1b4a 1 0 2 DP_SEC_AUD_M_READBACK 0 23 mmDP2_DP_SEC_TIMESTAMP 0 0x1b4b 1 0 2 DP_SEC_TIMESTAMP_MODE 0 0 mmDP2_DP_SEC_PACKET_CNTL 0 0x1b4c 4 0 2 DP_SEC_ASP_CODING_TYPE 1 3 DP_SEC_ASP_PRIORITY 4 4 DP_SEC_VERSION 8 13 DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE 16 16 mmDP2_DP_MSE_RATE_CNTL 0 0x1b4d 2 0 2 DP_MSE_RATE_Y 0 25 DP_MSE_RATE_X 26 31 mmDP2_DP_MSE_RATE_UPDATE 0 0x1b4f 1 0 2 DP_MSE_RATE_UPDATE_PENDING 0 0 mmDP2_DP_MSE_SAT0 0 0x1b50 4 0 2 DP_MSE_SAT_SRC0 0 2 DP_MSE_SAT_SLOT_COUNT0 8 13 DP_MSE_SAT_SRC1 16 18 DP_MSE_SAT_SLOT_COUNT1 24 29 mmDP2_DP_MSE_SAT1 0 0x1b51 4 0 2 DP_MSE_SAT_SRC2 0 2 DP_MSE_SAT_SLOT_COUNT2 8 13 DP_MSE_SAT_SRC3 16 18 DP_MSE_SAT_SLOT_COUNT3 24 29 mmDP2_DP_MSE_SAT2 0 0x1b52 4 0 2 DP_MSE_SAT_SRC4 0 2 DP_MSE_SAT_SLOT_COUNT4 8 13 DP_MSE_SAT_SRC5 16 18 DP_MSE_SAT_SLOT_COUNT5 24 29 mmDP2_DP_MSE_SAT_UPDATE 0 0x1b53 2 0 2 DP_MSE_SAT_UPDATE 0 1 DP_MSE_16_MTP_KEEPOUT 8 8 mmDP2_DP_MSE_LINK_TIMING 0 0x1b54 2 0 2 DP_MSE_LINK_FRAME 0 9 DP_MSE_LINK_LINE 16 17 mmDP2_DP_MSE_MISC_CNTL 0 0x1b55 3 0 2 DP_MSE_BLANK_CODE 0 0 DP_MSE_TIMESTAMP_MODE 4 4 DP_MSE_ZERO_ENCODER 8 8 mmDP2_DP_DPHY_BS_SR_SWAP_CNTL 0 0x1b5a 3 0 2 DPHY_LOAD_BS_COUNT 0 9 DPHY_BS_SR_SWAP_DONE 15 15 DPHY_LOAD_BS_COUNT_START 16 16 mmDP2_DP_DPHY_HBR2_PATTERN_CONTROL 0 0x1b5b 1 0 2 DP_DPHY_HBR2_PATTERN_CONTROL 0 2 mmDP2_DP_MSE_SAT0_STATUS 0 0x1b5d 4 0 2 DP_MSE_SAT_SRC0_STATUS 0 2 DP_MSE_SAT_SLOT_COUNT0_STATUS 8 13 DP_MSE_SAT_SRC1_STATUS 16 18 DP_MSE_SAT_SLOT_COUNT1_STATUS 24 29 mmDP2_DP_MSE_SAT1_STATUS 0 0x1b5e 4 0 2 DP_MSE_SAT_SRC2_STATUS 0 2 DP_MSE_SAT_SLOT_COUNT2_STATUS 8 13 DP_MSE_SAT_SRC3_STATUS 16 18 DP_MSE_SAT_SLOT_COUNT3_STATUS 24 29 mmDP2_DP_MSE_SAT2_STATUS 0 0x1b5f 4 0 2 DP_MSE_SAT_SRC4_STATUS 0 2 DP_MSE_SAT_SLOT_COUNT4_STATUS 8 13 DP_MSE_SAT_SRC5_STATUS 16 18 DP_MSE_SAT_SLOT_COUNT5_STATUS 24 29 mmDIG3_DIG_FE_CNTL 0 0x1b7e 7 0 2 DIG_SOURCE_SELECT 0 2 DIG_STEREOSYNC_SELECT 4 6 DIG_STEREOSYNC_GATE_EN 8 8 DIG_START 10 10 DIG_SYMCLK_FE_ON 24 24 TMDS_PIXEL_ENCODING 28 28 TMDS_COLOR_FORMAT 30 31 mmDIG3_DIG_OUTPUT_CRC_CNTL 0 0x1b7f 3 0 2 DIG_OUTPUT_CRC_EN 0 0 DIG_OUTPUT_CRC_LINK_SEL 4 4 DIG_OUTPUT_CRC_DATA_SEL 8 9 mmDIG3_DIG_OUTPUT_CRC_RESULT 0 0x1b80 1 0 2 DIG_OUTPUT_CRC_RESULT 0 29 mmDIG3_DIG_CLOCK_PATTERN 0 0x1b81 1 0 2 DIG_CLOCK_PATTERN 0 9 mmDIG3_DIG_TEST_PATTERN 0 0x1b82 6 0 2 DIG_TEST_PATTERN_OUT_EN 0 0 DIG_HALF_CLOCK_PATTERN_SEL 1 1 DIG_RANDOM_PATTERN_OUT_EN 4 4 DIG_RANDOM_PATTERN_RESET 5 5 DIG_TEST_PATTERN_EXTERNAL_RESET_EN 6 6 DIG_STATIC_TEST_PATTERN 16 25 mmDIG3_DIG_RANDOM_PATTERN_SEED 0 0x1b83 2 0 2 DIG_RANDOM_PATTERN_SEED 0 23 DIG_RAN_PAT_DURING_DE_ONLY 24 24 mmDIG3_DIG_FIFO_STATUS 0 0x1b84 11 0 2 DIG_FIFO_LEVEL_ERROR 0 0 DIG_FIFO_USE_OVERWRITE_LEVEL 1 1 DIG_FIFO_OVERWRITE_LEVEL 2 7 DIG_FIFO_ERROR_ACK 8 8 DIG_FIFO_CAL_AVERAGE_LEVEL 10 15 DIG_FIFO_MAXIMUM_LEVEL 16 20 DIG_FIFO_MINIMUM_LEVEL 22 25 DIG_FIFO_READ_CLOCK_SRC 26 26 DIG_FIFO_CALIBRATED 29 29 DIG_FIFO_FORCE_RECAL_AVERAGE 30 30 DIG_FIFO_FORCE_RECOMP_MINMAX 31 31 mmDIG3_HDMI_CONTROL 0 0x1b87 9 0 2 HDMI_KEEPOUT_MODE 0 0 HDMI_DATA_SCRAMBLE_EN 1 1 HDMI_CLOCK_CHANNEL_RATE 2 2 HDMI_NO_EXTRA_NULL_PACKET_FILLED 3 3 HDMI_PACKET_GEN_VERSION 4 4 HDMI_ERROR_ACK 8 8 HDMI_ERROR_MASK 9 9 HDMI_DEEP_COLOR_ENABLE 24 24 HDMI_DEEP_COLOR_DEPTH 28 29 mmDIG3_HDMI_STATUS 0 0x1b88 4 0 2 HDMI_ACTIVE_AVMUTE 0 0 HDMI_AUDIO_PACKET_ERROR 16 16 HDMI_VBI_PACKET_ERROR 20 20 HDMI_ERROR_INT 27 27 mmDIG3_HDMI_AUDIO_PACKET_CONTROL 0 0x1b89 2 0 2 HDMI_AUDIO_DELAY_EN 4 5 HDMI_AUDIO_PACKETS_PER_LINE 16 20 mmDIG3_HDMI_ACR_PACKET_CONTROL 0 0x1b8a 7 0 2 HDMI_ACR_SEND 0 0 HDMI_ACR_CONT 1 1 HDMI_ACR_SELECT 4 5 HDMI_ACR_SOURCE 8 8 HDMI_ACR_AUTO_SEND 12 12 HDMI_ACR_N_MULTIPLE 16 18 HDMI_ACR_AUDIO_PRIORITY 31 31 mmDIG3_HDMI_VBI_PACKET_CONTROL 0 0x1b8b 6 0 2 HDMI_NULL_SEND 0 0 HDMI_GC_SEND 4 4 HDMI_GC_CONT 5 5 HDMI_ISRC_SEND 8 8 HDMI_ISRC_CONT 9 9 HDMI_ISRC_LINE 16 21 mmDIG3_HDMI_INFOFRAME_CONTROL0 0 0x1b8c 6 0 2 HDMI_AVI_INFO_SEND 0 0 HDMI_AVI_INFO_CONT 1 1 HDMI_AUDIO_INFO_SEND 4 4 HDMI_AUDIO_INFO_CONT 5 5 HDMI_MPEG_INFO_SEND 8 8 HDMI_MPEG_INFO_CONT 9 9 mmDIG3_HDMI_INFOFRAME_CONTROL1 0 0x1b8d 3 0 2 HDMI_AVI_INFO_LINE 0 5 HDMI_AUDIO_INFO_LINE 8 13 HDMI_MPEG_INFO_LINE 16 21 mmDIG3_HDMI_GENERIC_PACKET_CONTROL0 0 0x1b8e 6 0 2 HDMI_GENERIC0_SEND 0 0 HDMI_GENERIC0_CONT 1 1 HDMI_GENERIC1_SEND 4 4 HDMI_GENERIC1_CONT 5 5 HDMI_GENERIC0_LINE 16 21 HDMI_GENERIC1_LINE 24 29 mmDIG3_AFMT_INTERRUPT_STATUS 0 0x1b8f 0 0 2 mmDIG3_HDMI_GC 0 0x1b91 5 0 2 HDMI_GC_AVMUTE 0 0 HDMI_GC_AVMUTE_CONT 2 2 HDMI_DEFAULT_PHASE 4 4 HDMI_PACKING_PHASE 8 11 HDMI_PACKING_PHASE_OVERRIDE 12 12 mmDIG3_AFMT_AUDIO_PACKET_CONTROL2 0 0x1b92 6 0 2 AFMT_AUDIO_LAYOUT_OVRD 0 0 AFMT_AUDIO_LAYOUT_SELECT 1 1 AFMT_AUDIO_CHANNEL_ENABLE 8 15 AFMT_DP_AUDIO_STREAM_ID 16 23 AFMT_HBR_ENABLE_OVRD 24 24 AFMT_60958_OSF_OVRD 28 28 mmDIG3_AFMT_ISRC1_0 0 0x1b93 3 0 2 AFMT_ISRC_STATUS 0 2 AFMT_ISRC_CONTINUE 6 6 AFMT_ISRC_VALID 7 7 mmDIG3_AFMT_ISRC1_1 0 0x1b94 4 0 2 AFMT_UPC_EAN_ISRC0 0 7 AFMT_UPC_EAN_ISRC1 8 15 AFMT_UPC_EAN_ISRC2 16 23 AFMT_UPC_EAN_ISRC3 24 31 mmDIG3_AFMT_ISRC1_2 0 0x1b95 4 0 2 AFMT_UPC_EAN_ISRC4 0 7 AFMT_UPC_EAN_ISRC5 8 15 AFMT_UPC_EAN_ISRC6 16 23 AFMT_UPC_EAN_ISRC7 24 31 mmDIG3_AFMT_ISRC1_3 0 0x1b96 4 0 2 AFMT_UPC_EAN_ISRC8 0 7 AFMT_UPC_EAN_ISRC9 8 15 AFMT_UPC_EAN_ISRC10 16 23 AFMT_UPC_EAN_ISRC11 24 31 mmDIG3_AFMT_ISRC1_4 0 0x1b97 4 0 2 AFMT_UPC_EAN_ISRC12 0 7 AFMT_UPC_EAN_ISRC13 8 15 AFMT_UPC_EAN_ISRC14 16 23 AFMT_UPC_EAN_ISRC15 24 31 mmDIG3_AFMT_ISRC2_0 0 0x1b98 4 0 2 AFMT_UPC_EAN_ISRC16 0 7 AFMT_UPC_EAN_ISRC17 8 15 AFMT_UPC_EAN_ISRC18 16 23 AFMT_UPC_EAN_ISRC19 24 31 mmDIG3_AFMT_ISRC2_1 0 0x1b99 4 0 2 AFMT_UPC_EAN_ISRC20 0 7 AFMT_UPC_EAN_ISRC21 8 15 AFMT_UPC_EAN_ISRC22 16 23 AFMT_UPC_EAN_ISRC23 24 31 mmDIG3_AFMT_ISRC2_2 0 0x1b9a 4 0 2 AFMT_UPC_EAN_ISRC24 0 7 AFMT_UPC_EAN_ISRC25 8 15 AFMT_UPC_EAN_ISRC26 16 23 AFMT_UPC_EAN_ISRC27 24 31 mmDIG3_AFMT_ISRC2_3 0 0x1b9b 4 0 2 AFMT_UPC_EAN_ISRC28 0 7 AFMT_UPC_EAN_ISRC29 8 15 AFMT_UPC_EAN_ISRC30 16 23 AFMT_UPC_EAN_ISRC31 24 31 mmDIG3_AFMT_AVI_INFO0 0 0x1b9c 12 0 2 AFMT_AVI_INFO_CHECKSUM 0 7 AFMT_AVI_INFO_S 8 9 AFMT_AVI_INFO_B 10 11 AFMT_AVI_INFO_A 12 12 AFMT_AVI_INFO_Y 13 15 AFMT_AVI_INFO_R 16 19 AFMT_AVI_INFO_M 20 21 AFMT_AVI_INFO_C 22 23 AFMT_AVI_INFO_SC 24 25 AFMT_AVI_INFO_Q 26 27 AFMT_AVI_INFO_EC 28 30 AFMT_AVI_INFO_ITC 31 31 mmDIG3_AFMT_AVI_INFO1 0 0x1b9d 5 0 2 AFMT_AVI_INFO_VIC 0 7 AFMT_AVI_INFO_PR 8 11 AFMT_AVI_INFO_CN 12 13 AFMT_AVI_INFO_YQ 14 15 AFMT_AVI_INFO_TOP 16 31 mmDIG3_AFMT_AVI_INFO2 0 0x1b9e 2 0 2 AFMT_AVI_INFO_BOTTOM 0 15 AFMT_AVI_INFO_LEFT 16 31 mmDIG3_AFMT_AVI_INFO3 0 0x1b9f 2 0 2 AFMT_AVI_INFO_RIGHT 0 15 AFMT_AVI_INFO_VERSION 24 31 mmDIG3_AFMT_MPEG_INFO0 0 0x1ba0 4 0 2 AFMT_MPEG_INFO_CHECKSUM 0 7 AFMT_MPEG_INFO_MB0 8 15 AFMT_MPEG_INFO_MB1 16 23 AFMT_MPEG_INFO_MB2 24 31 mmDIG3_AFMT_MPEG_INFO1 0 0x1ba1 3 0 2 AFMT_MPEG_INFO_MB3 0 7 AFMT_MPEG_INFO_MF 8 9 AFMT_MPEG_INFO_FR 12 12 mmDIG3_AFMT_GENERIC_HDR 0 0x1ba2 4 0 2 AFMT_GENERIC_HB0 0 7 AFMT_GENERIC_HB1 8 15 AFMT_GENERIC_HB2 16 23 AFMT_GENERIC_HB3 24 31 mmDIG3_AFMT_GENERIC_0 0 0x1ba3 4 0 2 AFMT_GENERIC_BYTE0 0 7 AFMT_GENERIC_BYTE1 8 15 AFMT_GENERIC_BYTE2 16 23 AFMT_GENERIC_BYTE3 24 31 mmDIG3_AFMT_GENERIC_1 0 0x1ba4 4 0 2 AFMT_GENERIC_BYTE4 0 7 AFMT_GENERIC_BYTE5 8 15 AFMT_GENERIC_BYTE6 16 23 AFMT_GENERIC_BYTE7 24 31 mmDIG3_AFMT_GENERIC_2 0 0x1ba5 4 0 2 AFMT_GENERIC_BYTE8 0 7 AFMT_GENERIC_BYTE9 8 15 AFMT_GENERIC_BYTE10 16 23 AFMT_GENERIC_BYTE11 24 31 mmDIG3_AFMT_GENERIC_3 0 0x1ba6 4 0 2 AFMT_GENERIC_BYTE12 0 7 AFMT_GENERIC_BYTE13 8 15 AFMT_GENERIC_BYTE14 16 23 AFMT_GENERIC_BYTE15 24 31 mmDIG3_AFMT_GENERIC_4 0 0x1ba7 4 0 2 AFMT_GENERIC_BYTE16 0 7 AFMT_GENERIC_BYTE17 8 15 AFMT_GENERIC_BYTE18 16 23 AFMT_GENERIC_BYTE19 24 31 mmDIG3_AFMT_GENERIC_5 0 0x1ba8 4 0 2 AFMT_GENERIC_BYTE20 0 7 AFMT_GENERIC_BYTE21 8 15 AFMT_GENERIC_BYTE22 16 23 AFMT_GENERIC_BYTE23 24 31 mmDIG3_AFMT_GENERIC_6 0 0x1ba9 4 0 2 AFMT_GENERIC_BYTE24 0 7 AFMT_GENERIC_BYTE25 8 15 AFMT_GENERIC_BYTE26 16 23 AFMT_GENERIC_BYTE27 24 31 mmDIG3_AFMT_GENERIC_7 0 0x1baa 4 0 2 AFMT_GENERIC_BYTE28 0 7 AFMT_GENERIC_BYTE29 8 15 AFMT_GENERIC_BYTE30 16 23 AFMT_GENERIC_BYTE31 24 31 mmDIG3_HDMI_GENERIC_PACKET_CONTROL1 0 0x1bab 6 0 2 HDMI_GENERIC2_SEND 0 0 HDMI_GENERIC2_CONT 1 1 HDMI_GENERIC3_SEND 4 4 HDMI_GENERIC3_CONT 5 5 HDMI_GENERIC2_LINE 16 21 HDMI_GENERIC3_LINE 24 29 mmDIG3_HDMI_ACR_32_0 0 0x1bac 1 0 2 HDMI_ACR_CTS_32 12 31 mmDIG3_HDMI_ACR_32_1 0 0x1bad 1 0 2 HDMI_ACR_N_32 0 19 mmDIG3_HDMI_ACR_44_0 0 0x1bae 1 0 2 HDMI_ACR_CTS_44 12 31 mmDIG3_HDMI_ACR_44_1 0 0x1baf 1 0 2 HDMI_ACR_N_44 0 19 mmDIG3_HDMI_ACR_48_0 0 0x1bb0 1 0 2 HDMI_ACR_CTS_48 12 31 mmDIG3_HDMI_ACR_48_1 0 0x1bb1 1 0 2 HDMI_ACR_N_48 0 19 mmDIG3_HDMI_ACR_STATUS_0 0 0x1bb2 1 0 2 HDMI_ACR_CTS 12 31 mmDIG3_HDMI_ACR_STATUS_1 0 0x1bb3 1 0 2 HDMI_ACR_N 0 19 mmDIG3_AFMT_AUDIO_INFO0 0 0x1bb4 5 0 2 AFMT_AUDIO_INFO_CHECKSUM 0 7 AFMT_AUDIO_INFO_CC 8 10 AFMT_AUDIO_INFO_CT 11 14 AFMT_AUDIO_INFO_CHECKSUM_OFFSET 16 23 AFMT_AUDIO_INFO_CXT 24 28 mmDIG3_AFMT_AUDIO_INFO1 0 0x1bb5 4 0 2 AFMT_AUDIO_INFO_CA 0 7 AFMT_AUDIO_INFO_LSV 11 14 AFMT_AUDIO_INFO_DM_INH 15 15 AFMT_AUDIO_INFO_LFEPBL 16 17 mmDIG3_AFMT_60958_0 0 0x1bb6 10 0 2 AFMT_60958_CS_A 0 0 AFMT_60958_CS_B 1 1 AFMT_60958_CS_C 2 2 AFMT_60958_CS_D 3 5 AFMT_60958_CS_MODE 6 7 AFMT_60958_CS_CATEGORY_CODE 8 15 AFMT_60958_CS_SOURCE_NUMBER 16 19 AFMT_60958_CS_CHANNEL_NUMBER_L 20 23 AFMT_60958_CS_SAMPLING_FREQUENCY 24 27 AFMT_60958_CS_CLOCK_ACCURACY 28 29 mmDIG3_AFMT_60958_1 0 0x1bb7 5 0 2 AFMT_60958_CS_WORD_LENGTH 0 3 AFMT_60958_CS_ORIGINAL_SAMPLING_FREQUENCY 4 7 AFMT_60958_VALID_L 16 16 AFMT_60958_VALID_R 18 18 AFMT_60958_CS_CHANNEL_NUMBER_R 20 23 mmDIG3_AFMT_AUDIO_CRC_CONTROL 0 0x1bb8 5 0 2 AFMT_AUDIO_CRC_EN 0 0 AFMT_AUDIO_CRC_CONT 4 4 AFMT_AUDIO_CRC_SOURCE 8 8 AFMT_AUDIO_CRC_CH_SEL 12 15 AFMT_AUDIO_CRC_COUNT 16 31 mmDIG3_AFMT_RAMP_CONTROL0 0 0x1bb9 2 0 2 AFMT_RAMP_MAX_COUNT 0 23 AFMT_RAMP_DATA_SIGN 31 31 mmDIG3_AFMT_RAMP_CONTROL1 0 0x1bba 2 0 2 AFMT_RAMP_MIN_COUNT 0 23 AFMT_AUDIO_TEST_CH_DISABLE 24 31 mmDIG3_AFMT_RAMP_CONTROL2 0 0x1bbb 1 0 2 AFMT_RAMP_INC_COUNT 0 23 mmDIG3_AFMT_RAMP_CONTROL3 0 0x1bbc 1 0 2 AFMT_RAMP_DEC_COUNT 0 23 mmDIG3_AFMT_60958_2 0 0x1bbd 6 0 2 AFMT_60958_CS_CHANNEL_NUMBER_2 0 3 AFMT_60958_CS_CHANNEL_NUMBER_3 4 7 AFMT_60958_CS_CHANNEL_NUMBER_4 8 11 AFMT_60958_CS_CHANNEL_NUMBER_5 12 15 AFMT_60958_CS_CHANNEL_NUMBER_6 16 19 AFMT_60958_CS_CHANNEL_NUMBER_7 20 23 mmDIG3_AFMT_AUDIO_CRC_RESULT 0 0x1bbe 2 0 2 AFMT_AUDIO_CRC_DONE 0 0 AFMT_AUDIO_CRC 8 31 mmDIG3_AFMT_STATUS 0 0x1bbf 4 0 2 AFMT_AUDIO_ENABLE 4 4 AFMT_AZ_HBR_ENABLE 8 8 AFMT_AUDIO_FIFO_OVERFLOW 24 24 AFMT_AZ_AUDIO_ENABLE_CHG 30 30 mmDIG3_AFMT_AUDIO_PACKET_CONTROL 0 0x1bc0 8 0 2 AFMT_AUDIO_SAMPLE_SEND 0 0 AFMT_RESET_FIFO_WHEN_AUDIO_DIS 11 11 AFMT_AUDIO_TEST_EN 12 12 AFMT_AUDIO_TEST_MODE 14 14 AFMT_AUDIO_FIFO_OVERFLOW_ACK 23 23 AFMT_AUDIO_CHANNEL_SWAP 24 24 AFMT_60958_CS_UPDATE 26 26 AFMT_AZ_AUDIO_ENABLE_CHG_ACK 30 30 mmDIG3_AFMT_VBI_PACKET_CONTROL 0 0x1bc1 3 0 2 AFMT_GENERIC0_UPDATE 2 2 AFMT_GENERIC2_UPDATE 3 3 AFMT_GENERIC_INDEX 30 31 mmDIG3_AFMT_INFOFRAME_CONTROL0 0 0x1bc2 3 0 2 AFMT_AUDIO_INFO_SOURCE 6 6 AFMT_AUDIO_INFO_UPDATE 7 7 AFMT_MPEG_INFO_UPDATE 10 10 mmDIG3_AFMT_AUDIO_SRC_CONTROL 0 0x1bc3 1 0 2 AFMT_AUDIO_SRC_SELECT 0 2 mmDIG3_DIG_BE_CNTL 0 0x1bc5 5 0 2 DIG_DUAL_LINK_ENABLE 0 0 DIG_SWAP 1 1 DIG_FE_SOURCE_SELECT 8 14 DIG_MODE 16 18 DIG_HPD_SELECT 28 30 mmDIG3_DIG_BE_EN_CNTL 0 0x1bc6 2 0 2 DIG_ENABLE 0 0 DIG_SYMCLK_BE_ON 8 8 mmDIG3_TMDS_CNTL 0 0x1be9 1 0 2 TMDS_SYNC_PHASE 0 0 mmDIG3_TMDS_CONTROL_CHAR 0 0x1bea 4 0 2 TMDS_CONTROL_CHAR0_OUT_EN 0 0 TMDS_CONTROL_CHAR1_OUT_EN 1 1 TMDS_CONTROL_CHAR2_OUT_EN 2 2 TMDS_CONTROL_CHAR3_OUT_EN 3 3 mmDIG3_TMDS_CONTROL0_FEEDBACK 0 0x1beb 2 0 2 TMDS_CONTROL0_FEEDBACK_SELECT 0 1 TMDS_CONTROL0_FEEDBACK_DELAY 8 9 mmDIG3_TMDS_STEREOSYNC_CTL_SEL 0 0x1bec 1 0 2 TMDS_STEREOSYNC_CTL_SEL 0 1 mmDIG3_TMDS_SYNC_CHAR_PATTERN_0_1 0 0x1bed 2 0 2 TMDS_SYNC_CHAR_PATTERN0 0 9 TMDS_SYNC_CHAR_PATTERN1 16 25 mmDIG3_TMDS_SYNC_CHAR_PATTERN_2_3 0 0x1bee 2 0 2 TMDS_SYNC_CHAR_PATTERN2 0 9 TMDS_SYNC_CHAR_PATTERN3 16 25 mmDIG3_TMDS_CTL_BITS 0 0x1bf0 4 0 2 TMDS_CTL0 0 0 TMDS_CTL1 8 8 TMDS_CTL2 16 16 TMDS_CTL3 24 24 mmDIG3_TMDS_DCBALANCER_CONTROL 0 0x1bf1 4 0 2 TMDS_DCBALANCER_EN 0 0 TMDS_DCBALANCER_TEST_EN 8 8 TMDS_DCBALANCER_TEST_IN 16 19 TMDS_DCBALANCER_FORCE 24 24 mmDIG3_TMDS_CTL0_1_GEN_CNTL 0 0x1bf3 15 0 2 TMDS_CTL0_DATA_SEL 0 3 TMDS_CTL0_DATA_DELAY 4 6 TMDS_CTL0_DATA_INVERT 7 7 TMDS_CTL0_DATA_MODULATION 8 9 TMDS_CTL0_USE_FEEDBACK_PATH 10 10 TMDS_CTL0_FB_SYNC_CONT 11 11 TMDS_CTL0_PATTERN_OUT_EN 12 12 TMDS_CTL1_DATA_SEL 16 19 TMDS_CTL1_DATA_DELAY 20 22 TMDS_CTL1_DATA_INVERT 23 23 TMDS_CTL1_DATA_MODULATION 24 25 TMDS_CTL1_USE_FEEDBACK_PATH 26 26 TMDS_CTL1_FB_SYNC_CONT 27 27 TMDS_CTL1_PATTERN_OUT_EN 28 28 TMDS_2BIT_COUNTER_EN 31 31 mmDIG3_TMDS_CTL2_3_GEN_CNTL 0 0x1bf4 14 0 2 TMDS_CTL2_DATA_SEL 0 3 TMDS_CTL2_DATA_DELAY 4 6 TMDS_CTL2_DATA_INVERT 7 7 TMDS_CTL2_DATA_MODULATION 8 9 TMDS_CTL2_USE_FEEDBACK_PATH 10 10 TMDS_CTL2_FB_SYNC_CONT 11 11 TMDS_CTL2_PATTERN_OUT_EN 12 12 TMDS_CTL3_DATA_SEL 16 19 TMDS_CTL3_DATA_DELAY 20 22 TMDS_CTL3_DATA_INVERT 23 23 TMDS_CTL3_DATA_MODULATION 24 25 TMDS_CTL3_USE_FEEDBACK_PATH 26 26 TMDS_CTL3_FB_SYNC_CONT 27 27 TMDS_CTL3_PATTERN_OUT_EN 28 28 mmDIG3_DIG_VERSION 0 0x1bf6 1 0 2 DIG_TYPE 0 0 mmDIG3_DIG_LANE_ENABLE 0 0x1bf7 5 0 2 DIG_LANE0EN 0 0 DIG_LANE1EN 1 1 DIG_LANE2EN 2 2 DIG_LANE3EN 3 3 DIG_CLK_EN 8 8 mmDIG3_AFMT_CNTL 0 0x1bfc 2 0 2 AFMT_AUDIO_CLOCK_EN 0 0 AFMT_AUDIO_CLOCK_ON 8 8 mmDP3_DP_LINK_CNTL 0 0x1c1e 3 0 2 DP_LINK_TRAINING_COMPLETE 4 4 DP_LINK_STATUS 8 8 DP_EMBEDDED_PANEL_MODE 17 17 mmDP3_DP_PIXEL_FORMAT 0 0x1c1f 4 0 2 DP_PIXEL_ENCODING 0 2 DP_DYN_RANGE 8 8 DP_YCBCR_RANGE 16 16 DP_COMPONENT_DEPTH 24 26 mmDP3_DP_MSA_COLORIMETRY 0 0x1c20 4 0 2 DP_MSA_MISC0_OVERRIDE 0 7 DP_MSA_MISC0_OVERRIDE_ENABLE 8 8 DP_MSA_MISC1_BIT7_OVERRIDE 9 9 DP_MSA_MISC1_BIT7_OVERRIDE_ENABLE 17 17 mmDP3_DP_CONFIG 0 0x1c21 1 0 2 DP_UDI_LANES 0 1 mmDP3_DP_VID_STREAM_CNTL 0 0x1c22 4 0 2 DP_VID_STREAM_ENABLE 0 0 DP_VID_STREAM_DIS_DEFER 8 9 DP_VID_STREAM_STATUS 16 16 DP_VID_STREAM_CHANGE_KEEPOUT 20 20 mmDP3_DP_STEER_FIFO 0 0x1c23 7 0 2 DP_STEER_FIFO_RESET 0 0 DP_STEER_OVERFLOW_FLAG 4 4 DP_STEER_OVERFLOW_INT 5 5 DP_STEER_OVERFLOW_ACK 6 6 DP_STEER_OVERFLOW_MASK 7 7 DP_TU_OVERFLOW_FLAG 8 8 DP_TU_OVERFLOW_ACK 12 12 mmDP3_DP_MSA_MISC 0 0x1c24 4 0 2 DP_MSA_MISC1 3 6 DP_MSA_MISC2 8 15 DP_MSA_MISC3 16 23 DP_MSA_MISC4 24 31 mmDP3_DP_VID_TIMING 0 0x1c26 5 0 2 DP_VID_TIMING_MODE 0 0 DP_VID_M_N_DOUBLE_BUFFER_MODE 4 4 DP_VID_M_N_GEN_EN 8 8 DP_VID_M_DOUBLE_VALUE_EN 9 9 DP_VID_N_DIV 24 31 mmDP3_DP_VID_N 0 0x1c27 1 0 2 DP_VID_N 0 23 mmDP3_DP_VID_M 0 0x1c28 1 0 2 DP_VID_M 0 23 mmDP3_DP_LINK_FRAMING_CNTL 0 0x1c29 3 0 2 DP_IDLE_BS_INTERVAL 0 17 DP_VBID_DISABLE 24 24 DP_VID_ENHANCED_FRAME_MODE 28 28 mmDP3_DP_HBR2_EYE_PATTERN 0 0x1c2a 1 0 2 DP_HBR2_EYE_PATTERN_ENABLE 0 0 mmDP3_DP_VID_MSA_VBID 0 0x1c2b 3 0 2 DP_VID_MSA_LOCATION 0 11 DP_VID_MSA_TOP_FIELD_MODE 16 16 DP_VID_VBID_FIELD_POL 24 24 mmDP3_DP_VID_INTERRUPT_CNTL 0 0x1c2c 3 0 2 DP_VID_STREAM_DISABLE_INT 0 0 DP_VID_STREAM_DISABLE_ACK 1 1 DP_VID_STREAM_DISABLE_MASK 2 2 mmDP3_DP_DPHY_CNTL 0 0x1c2d 6 0 2 DPHY_ATEST_SEL_LANE0 0 0 DPHY_ATEST_SEL_LANE1 1 1 DPHY_ATEST_SEL_LANE2 2 2 DPHY_ATEST_SEL_LANE3 3 3 DPHY_BYPASS 16 16 DPHY_SKEW_BYPASS 24 24 mmDP3_DP_DPHY_TRAINING_PATTERN_SEL 0 0x1c2e 1 0 2 DPHY_TRAINING_PATTERN_SEL 0 1 mmDP3_DP_DPHY_SYM0 0 0x1c2f 3 0 2 DPHY_SYM1 0 9 DPHY_SYM2 10 19 DPHY_SYM3 20 29 mmDP3_DP_DPHY_SYM1 0 0x1c30 3 0 2 DPHY_SYM4 0 9 DPHY_SYM5 10 19 DPHY_SYM6 20 29 mmDP3_DP_DPHY_SYM2 0 0x1c31 2 0 2 DPHY_SYM7 0 9 DPHY_SYM8 10 19 mmDP3_DP_DPHY_8B10B_CNTL 0 0x1c32 3 0 2 DPHY_8B10B_RESET 8 8 DPHY_8B10B_EXT_DISP 16 16 DPHY_8B10B_CUR_DISP 24 24 mmDP3_DP_DPHY_PRBS_CNTL 0 0x1c33 3 0 2 DPHY_PRBS_EN 0 0 DPHY_PRBS_SEL 4 5 DPHY_PRBS_SEED 8 30 mmDP3_DP_DPHY_SCRAM_CNTL 0 0x1c34 4 0 2 DPHY_SCRAMBLER_DIS 0 0 DPHY_SCRAMBLER_ADVANCE 4 4 DPHY_SCRAMBLER_BS_COUNT 8 17 DPHY_SCRAMBLER_KCODE 24 24 mmDP3_DP_DPHY_CRC_EN 0 0x1c35 3 0 2 DPHY_CRC_EN 0 0 DPHY_CRC_CONT_EN 4 4 DPHY_CRC_RESULT_VALID 8 8 mmDP3_DP_DPHY_CRC_CNTL 0 0x1c36 3 0 2 DPHY_CRC_FIELD 0 0 DPHY_CRC_SEL 4 5 DPHY_CRC_MASK 16 23 mmDP3_DP_DPHY_CRC_RESULT 0 0x1c37 4 0 2 DPHY_CRC_RESULT 0 7 DPHY_CRC_RESULT1 8 15 DPHY_CRC_RESULT2 16 23 DPHY_CRC_RESULT3 24 31 mmDP3_DP_DPHY_CRC_MST_CNTL 0 0x1c38 2 0 2 DPHY_CRC_MST_FIRST_SLOT 0 5 DPHY_CRC_MST_LAST_SLOT 8 13 mmDP3_DP_DPHY_CRC_MST_STATUS 0 0x1c39 3 0 2 DPHY_CRC_MST_PHASE_LOCK 0 0 DPHY_CRC_MST_PHASE_ERROR 8 8 DPHY_CRC_MST_PHASE_ERROR_ACK 16 16 mmDP3_DP_DPHY_FAST_TRAINING 0 0x1c3a 5 0 2 DPHY_RX_FAST_TRAINING_CAPABLE 0 0 DPHY_SW_FAST_TRAINING_START 1 1 DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN 2 2 DPHY_FAST_TRAINING_TP1_TIME 8 19 DPHY_FAST_TRAINING_TP2_TIME 20 31 mmDP3_DP_DPHY_FAST_TRAINING_STATUS 0 0x1c3b 4 0 2 DPHY_FAST_TRAINING_STATE 0 2 DPHY_FAST_TRAINING_COMPLETE_OCCURRED 4 4 DPHY_FAST_TRAINING_COMPLETE_MASK 8 8 DPHY_FAST_TRAINING_COMPLETE_ACK 12 12 mmDP3_DP_MSA_V_TIMING_OVERRIDE1 0 0x1c3c 2 0 2 DP_MSA_V_TIMING_OVERRIDE_EN 0 0 DP_MSA_V_TOTAL_OVERRIDE 4 17 mmDP3_DP_MSA_V_TIMING_OVERRIDE2 0 0x1c3d 2 0 2 DP_MSA_V_BLANK_START_OVERRIDE 0 13 DP_MSA_V_BLANK_END_OVERRIDE 16 29 mmDP3_DP_SEC_CNTL 0 0x1c41 11 0 2 DP_SEC_STREAM_ENABLE 0 0 DP_SEC_ASP_ENABLE 4 4 DP_SEC_ATP_ENABLE 8 8 DP_SEC_AIP_ENABLE 12 12 DP_SEC_ACM_ENABLE 16 16 DP_SEC_GSP0_ENABLE 20 20 DP_SEC_GSP1_ENABLE 21 21 DP_SEC_GSP2_ENABLE 22 22 DP_SEC_GSP3_ENABLE 23 23 DP_SEC_AVI_ENABLE 24 24 DP_SEC_MPG_ENABLE 28 28 mmDP3_DP_SEC_CNTL1 0 0x1c42 6 0 2 DP_SEC_ISRC_ENABLE 0 0 DP_SEC_GSP0_PRIORITY 4 4 DP_SEC_GSP0_SEND 5 5 DP_SEC_GSP0_SEND_PENDING 6 6 DP_SEC_GSP0_SEND_DEADLINE_MISSED 7 7 DP_SEC_GSP0_LINE_NUM 16 31 mmDP3_DP_SEC_FRAMING1 0 0x1c43 2 0 2 DP_SEC_FRAME_START_LOCATION 0 11 DP_SEC_VBLANK_TRANSMIT_WIDTH 16 31 mmDP3_DP_SEC_FRAMING2 0 0x1c44 2 0 2 DP_SEC_START_POSITION 0 15 DP_SEC_HBLANK_TRANSMIT_WIDTH 16 31 mmDP3_DP_SEC_FRAMING3 0 0x1c45 2 0 2 DP_SEC_IDLE_FRAME_SIZE 0 13 DP_SEC_IDLE_TRANSMIT_WIDTH 16 31 mmDP3_DP_SEC_FRAMING4 0 0x1c46 4 0 2 DP_SEC_COLLISION_STATUS 20 20 DP_SEC_COLLISION_ACK 24 24 DP_SEC_AUDIO_MUTE 28 28 DP_SEC_AUDIO_MUTE_STATUS 29 29 mmDP3_DP_SEC_AUD_N 0 0x1c47 1 0 2 DP_SEC_AUD_N 0 23 mmDP3_DP_SEC_AUD_N_READBACK 0 0x1c48 1 0 2 DP_SEC_AUD_N_READBACK 0 23 mmDP3_DP_SEC_AUD_M 0 0x1c49 1 0 2 DP_SEC_AUD_M 0 23 mmDP3_DP_SEC_AUD_M_READBACK 0 0x1c4a 1 0 2 DP_SEC_AUD_M_READBACK 0 23 mmDP3_DP_SEC_TIMESTAMP 0 0x1c4b 1 0 2 DP_SEC_TIMESTAMP_MODE 0 0 mmDP3_DP_SEC_PACKET_CNTL 0 0x1c4c 4 0 2 DP_SEC_ASP_CODING_TYPE 1 3 DP_SEC_ASP_PRIORITY 4 4 DP_SEC_VERSION 8 13 DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE 16 16 mmDP3_DP_MSE_RATE_CNTL 0 0x1c4d 2 0 2 DP_MSE_RATE_Y 0 25 DP_MSE_RATE_X 26 31 mmDP3_DP_MSE_RATE_UPDATE 0 0x1c4f 1 0 2 DP_MSE_RATE_UPDATE_PENDING 0 0 mmDP3_DP_MSE_SAT0 0 0x1c50 4 0 2 DP_MSE_SAT_SRC0 0 2 DP_MSE_SAT_SLOT_COUNT0 8 13 DP_MSE_SAT_SRC1 16 18 DP_MSE_SAT_SLOT_COUNT1 24 29 mmDP3_DP_MSE_SAT1 0 0x1c51 4 0 2 DP_MSE_SAT_SRC2 0 2 DP_MSE_SAT_SLOT_COUNT2 8 13 DP_MSE_SAT_SRC3 16 18 DP_MSE_SAT_SLOT_COUNT3 24 29 mmDP3_DP_MSE_SAT2 0 0x1c52 4 0 2 DP_MSE_SAT_SRC4 0 2 DP_MSE_SAT_SLOT_COUNT4 8 13 DP_MSE_SAT_SRC5 16 18 DP_MSE_SAT_SLOT_COUNT5 24 29 mmDP3_DP_MSE_SAT_UPDATE 0 0x1c53 2 0 2 DP_MSE_SAT_UPDATE 0 1 DP_MSE_16_MTP_KEEPOUT 8 8 mmDP3_DP_MSE_LINK_TIMING 0 0x1c54 2 0 2 DP_MSE_LINK_FRAME 0 9 DP_MSE_LINK_LINE 16 17 mmDP3_DP_MSE_MISC_CNTL 0 0x1c55 3 0 2 DP_MSE_BLANK_CODE 0 0 DP_MSE_TIMESTAMP_MODE 4 4 DP_MSE_ZERO_ENCODER 8 8 mmDP3_DP_DPHY_BS_SR_SWAP_CNTL 0 0x1c5a 3 0 2 DPHY_LOAD_BS_COUNT 0 9 DPHY_BS_SR_SWAP_DONE 15 15 DPHY_LOAD_BS_COUNT_START 16 16 mmDP3_DP_DPHY_HBR2_PATTERN_CONTROL 0 0x1c5b 1 0 2 DP_DPHY_HBR2_PATTERN_CONTROL 0 2 mmDP3_DP_MSE_SAT0_STATUS 0 0x1c5d 4 0 2 DP_MSE_SAT_SRC0_STATUS 0 2 DP_MSE_SAT_SLOT_COUNT0_STATUS 8 13 DP_MSE_SAT_SRC1_STATUS 16 18 DP_MSE_SAT_SLOT_COUNT1_STATUS 24 29 mmDP3_DP_MSE_SAT1_STATUS 0 0x1c5e 4 0 2 DP_MSE_SAT_SRC2_STATUS 0 2 DP_MSE_SAT_SLOT_COUNT2_STATUS 8 13 DP_MSE_SAT_SRC3_STATUS 16 18 DP_MSE_SAT_SLOT_COUNT3_STATUS 24 29 mmDP3_DP_MSE_SAT2_STATUS 0 0x1c5f 4 0 2 DP_MSE_SAT_SRC4_STATUS 0 2 DP_MSE_SAT_SLOT_COUNT4_STATUS 8 13 DP_MSE_SAT_SRC5_STATUS 16 18 DP_MSE_SAT_SLOT_COUNT5_STATUS 24 29 mmDIG4_DIG_FE_CNTL 0 0x1c7e 7 0 2 DIG_SOURCE_SELECT 0 2 DIG_STEREOSYNC_SELECT 4 6 DIG_STEREOSYNC_GATE_EN 8 8 DIG_START 10 10 DIG_SYMCLK_FE_ON 24 24 TMDS_PIXEL_ENCODING 28 28 TMDS_COLOR_FORMAT 30 31 mmDIG4_DIG_OUTPUT_CRC_CNTL 0 0x1c7f 3 0 2 DIG_OUTPUT_CRC_EN 0 0 DIG_OUTPUT_CRC_LINK_SEL 4 4 DIG_OUTPUT_CRC_DATA_SEL 8 9 mmDIG4_DIG_OUTPUT_CRC_RESULT 0 0x1c80 1 0 2 DIG_OUTPUT_CRC_RESULT 0 29 mmDIG4_DIG_CLOCK_PATTERN 0 0x1c81 1 0 2 DIG_CLOCK_PATTERN 0 9 mmDIG4_DIG_TEST_PATTERN 0 0x1c82 6 0 2 DIG_TEST_PATTERN_OUT_EN 0 0 DIG_HALF_CLOCK_PATTERN_SEL 1 1 DIG_RANDOM_PATTERN_OUT_EN 4 4 DIG_RANDOM_PATTERN_RESET 5 5 DIG_TEST_PATTERN_EXTERNAL_RESET_EN 6 6 DIG_STATIC_TEST_PATTERN 16 25 mmDIG4_DIG_RANDOM_PATTERN_SEED 0 0x1c83 2 0 2 DIG_RANDOM_PATTERN_SEED 0 23 DIG_RAN_PAT_DURING_DE_ONLY 24 24 mmDIG4_DIG_FIFO_STATUS 0 0x1c84 11 0 2 DIG_FIFO_LEVEL_ERROR 0 0 DIG_FIFO_USE_OVERWRITE_LEVEL 1 1 DIG_FIFO_OVERWRITE_LEVEL 2 7 DIG_FIFO_ERROR_ACK 8 8 DIG_FIFO_CAL_AVERAGE_LEVEL 10 15 DIG_FIFO_MAXIMUM_LEVEL 16 20 DIG_FIFO_MINIMUM_LEVEL 22 25 DIG_FIFO_READ_CLOCK_SRC 26 26 DIG_FIFO_CALIBRATED 29 29 DIG_FIFO_FORCE_RECAL_AVERAGE 30 30 DIG_FIFO_FORCE_RECOMP_MINMAX 31 31 mmDIG4_HDMI_CONTROL 0 0x1c87 9 0 2 HDMI_KEEPOUT_MODE 0 0 HDMI_DATA_SCRAMBLE_EN 1 1 HDMI_CLOCK_CHANNEL_RATE 2 2 HDMI_NO_EXTRA_NULL_PACKET_FILLED 3 3 HDMI_PACKET_GEN_VERSION 4 4 HDMI_ERROR_ACK 8 8 HDMI_ERROR_MASK 9 9 HDMI_DEEP_COLOR_ENABLE 24 24 HDMI_DEEP_COLOR_DEPTH 28 29 mmDIG4_HDMI_STATUS 0 0x1c88 4 0 2 HDMI_ACTIVE_AVMUTE 0 0 HDMI_AUDIO_PACKET_ERROR 16 16 HDMI_VBI_PACKET_ERROR 20 20 HDMI_ERROR_INT 27 27 mmDIG4_HDMI_AUDIO_PACKET_CONTROL 0 0x1c89 2 0 2 HDMI_AUDIO_DELAY_EN 4 5 HDMI_AUDIO_PACKETS_PER_LINE 16 20 mmDIG4_HDMI_ACR_PACKET_CONTROL 0 0x1c8a 7 0 2 HDMI_ACR_SEND 0 0 HDMI_ACR_CONT 1 1 HDMI_ACR_SELECT 4 5 HDMI_ACR_SOURCE 8 8 HDMI_ACR_AUTO_SEND 12 12 HDMI_ACR_N_MULTIPLE 16 18 HDMI_ACR_AUDIO_PRIORITY 31 31 mmDIG4_HDMI_VBI_PACKET_CONTROL 0 0x1c8b 6 0 2 HDMI_NULL_SEND 0 0 HDMI_GC_SEND 4 4 HDMI_GC_CONT 5 5 HDMI_ISRC_SEND 8 8 HDMI_ISRC_CONT 9 9 HDMI_ISRC_LINE 16 21 mmDIG4_HDMI_INFOFRAME_CONTROL0 0 0x1c8c 6 0 2 HDMI_AVI_INFO_SEND 0 0 HDMI_AVI_INFO_CONT 1 1 HDMI_AUDIO_INFO_SEND 4 4 HDMI_AUDIO_INFO_CONT 5 5 HDMI_MPEG_INFO_SEND 8 8 HDMI_MPEG_INFO_CONT 9 9 mmDIG4_HDMI_INFOFRAME_CONTROL1 0 0x1c8d 3 0 2 HDMI_AVI_INFO_LINE 0 5 HDMI_AUDIO_INFO_LINE 8 13 HDMI_MPEG_INFO_LINE 16 21 mmDIG4_HDMI_GENERIC_PACKET_CONTROL0 0 0x1c8e 6 0 2 HDMI_GENERIC0_SEND 0 0 HDMI_GENERIC0_CONT 1 1 HDMI_GENERIC1_SEND 4 4 HDMI_GENERIC1_CONT 5 5 HDMI_GENERIC0_LINE 16 21 HDMI_GENERIC1_LINE 24 29 mmDIG4_AFMT_INTERRUPT_STATUS 0 0x1c8f 0 0 2 mmDIG4_HDMI_GC 0 0x1c91 5 0 2 HDMI_GC_AVMUTE 0 0 HDMI_GC_AVMUTE_CONT 2 2 HDMI_DEFAULT_PHASE 4 4 HDMI_PACKING_PHASE 8 11 HDMI_PACKING_PHASE_OVERRIDE 12 12 mmDIG4_AFMT_AUDIO_PACKET_CONTROL2 0 0x1c92 6 0 2 AFMT_AUDIO_LAYOUT_OVRD 0 0 AFMT_AUDIO_LAYOUT_SELECT 1 1 AFMT_AUDIO_CHANNEL_ENABLE 8 15 AFMT_DP_AUDIO_STREAM_ID 16 23 AFMT_HBR_ENABLE_OVRD 24 24 AFMT_60958_OSF_OVRD 28 28 mmDIG4_AFMT_ISRC1_0 0 0x1c93 3 0 2 AFMT_ISRC_STATUS 0 2 AFMT_ISRC_CONTINUE 6 6 AFMT_ISRC_VALID 7 7 mmDIG4_AFMT_ISRC1_1 0 0x1c94 4 0 2 AFMT_UPC_EAN_ISRC0 0 7 AFMT_UPC_EAN_ISRC1 8 15 AFMT_UPC_EAN_ISRC2 16 23 AFMT_UPC_EAN_ISRC3 24 31 mmDIG4_AFMT_ISRC1_2 0 0x1c95 4 0 2 AFMT_UPC_EAN_ISRC4 0 7 AFMT_UPC_EAN_ISRC5 8 15 AFMT_UPC_EAN_ISRC6 16 23 AFMT_UPC_EAN_ISRC7 24 31 mmDIG4_AFMT_ISRC1_3 0 0x1c96 4 0 2 AFMT_UPC_EAN_ISRC8 0 7 AFMT_UPC_EAN_ISRC9 8 15 AFMT_UPC_EAN_ISRC10 16 23 AFMT_UPC_EAN_ISRC11 24 31 mmDIG4_AFMT_ISRC1_4 0 0x1c97 4 0 2 AFMT_UPC_EAN_ISRC12 0 7 AFMT_UPC_EAN_ISRC13 8 15 AFMT_UPC_EAN_ISRC14 16 23 AFMT_UPC_EAN_ISRC15 24 31 mmDIG4_AFMT_ISRC2_0 0 0x1c98 4 0 2 AFMT_UPC_EAN_ISRC16 0 7 AFMT_UPC_EAN_ISRC17 8 15 AFMT_UPC_EAN_ISRC18 16 23 AFMT_UPC_EAN_ISRC19 24 31 mmDIG4_AFMT_ISRC2_1 0 0x1c99 4 0 2 AFMT_UPC_EAN_ISRC20 0 7 AFMT_UPC_EAN_ISRC21 8 15 AFMT_UPC_EAN_ISRC22 16 23 AFMT_UPC_EAN_ISRC23 24 31 mmDIG4_AFMT_ISRC2_2 0 0x1c9a 4 0 2 AFMT_UPC_EAN_ISRC24 0 7 AFMT_UPC_EAN_ISRC25 8 15 AFMT_UPC_EAN_ISRC26 16 23 AFMT_UPC_EAN_ISRC27 24 31 mmDIG4_AFMT_ISRC2_3 0 0x1c9b 4 0 2 AFMT_UPC_EAN_ISRC28 0 7 AFMT_UPC_EAN_ISRC29 8 15 AFMT_UPC_EAN_ISRC30 16 23 AFMT_UPC_EAN_ISRC31 24 31 mmDIG4_AFMT_AVI_INFO0 0 0x1c9c 12 0 2 AFMT_AVI_INFO_CHECKSUM 0 7 AFMT_AVI_INFO_S 8 9 AFMT_AVI_INFO_B 10 11 AFMT_AVI_INFO_A 12 12 AFMT_AVI_INFO_Y 13 15 AFMT_AVI_INFO_R 16 19 AFMT_AVI_INFO_M 20 21 AFMT_AVI_INFO_C 22 23 AFMT_AVI_INFO_SC 24 25 AFMT_AVI_INFO_Q 26 27 AFMT_AVI_INFO_EC 28 30 AFMT_AVI_INFO_ITC 31 31 mmDIG4_AFMT_AVI_INFO1 0 0x1c9d 5 0 2 AFMT_AVI_INFO_VIC 0 7 AFMT_AVI_INFO_PR 8 11 AFMT_AVI_INFO_CN 12 13 AFMT_AVI_INFO_YQ 14 15 AFMT_AVI_INFO_TOP 16 31 mmDIG4_AFMT_AVI_INFO2 0 0x1c9e 2 0 2 AFMT_AVI_INFO_BOTTOM 0 15 AFMT_AVI_INFO_LEFT 16 31 mmDIG4_AFMT_AVI_INFO3 0 0x1c9f 2 0 2 AFMT_AVI_INFO_RIGHT 0 15 AFMT_AVI_INFO_VERSION 24 31 mmDIG4_AFMT_MPEG_INFO0 0 0x1ca0 4 0 2 AFMT_MPEG_INFO_CHECKSUM 0 7 AFMT_MPEG_INFO_MB0 8 15 AFMT_MPEG_INFO_MB1 16 23 AFMT_MPEG_INFO_MB2 24 31 mmDIG4_AFMT_MPEG_INFO1 0 0x1ca1 3 0 2 AFMT_MPEG_INFO_MB3 0 7 AFMT_MPEG_INFO_MF 8 9 AFMT_MPEG_INFO_FR 12 12 mmDIG4_AFMT_GENERIC_HDR 0 0x1ca2 4 0 2 AFMT_GENERIC_HB0 0 7 AFMT_GENERIC_HB1 8 15 AFMT_GENERIC_HB2 16 23 AFMT_GENERIC_HB3 24 31 mmDIG4_AFMT_GENERIC_0 0 0x1ca3 4 0 2 AFMT_GENERIC_BYTE0 0 7 AFMT_GENERIC_BYTE1 8 15 AFMT_GENERIC_BYTE2 16 23 AFMT_GENERIC_BYTE3 24 31 mmDIG4_AFMT_GENERIC_1 0 0x1ca4 4 0 2 AFMT_GENERIC_BYTE4 0 7 AFMT_GENERIC_BYTE5 8 15 AFMT_GENERIC_BYTE6 16 23 AFMT_GENERIC_BYTE7 24 31 mmDIG4_AFMT_GENERIC_2 0 0x1ca5 4 0 2 AFMT_GENERIC_BYTE8 0 7 AFMT_GENERIC_BYTE9 8 15 AFMT_GENERIC_BYTE10 16 23 AFMT_GENERIC_BYTE11 24 31 mmDIG4_AFMT_GENERIC_3 0 0x1ca6 4 0 2 AFMT_GENERIC_BYTE12 0 7 AFMT_GENERIC_BYTE13 8 15 AFMT_GENERIC_BYTE14 16 23 AFMT_GENERIC_BYTE15 24 31 mmDIG4_AFMT_GENERIC_4 0 0x1ca7 4 0 2 AFMT_GENERIC_BYTE16 0 7 AFMT_GENERIC_BYTE17 8 15 AFMT_GENERIC_BYTE18 16 23 AFMT_GENERIC_BYTE19 24 31 mmDIG4_AFMT_GENERIC_5 0 0x1ca8 4 0 2 AFMT_GENERIC_BYTE20 0 7 AFMT_GENERIC_BYTE21 8 15 AFMT_GENERIC_BYTE22 16 23 AFMT_GENERIC_BYTE23 24 31 mmDIG4_AFMT_GENERIC_6 0 0x1ca9 4 0 2 AFMT_GENERIC_BYTE24 0 7 AFMT_GENERIC_BYTE25 8 15 AFMT_GENERIC_BYTE26 16 23 AFMT_GENERIC_BYTE27 24 31 mmDIG4_AFMT_GENERIC_7 0 0x1caa 4 0 2 AFMT_GENERIC_BYTE28 0 7 AFMT_GENERIC_BYTE29 8 15 AFMT_GENERIC_BYTE30 16 23 AFMT_GENERIC_BYTE31 24 31 mmDIG4_HDMI_GENERIC_PACKET_CONTROL1 0 0x1cab 6 0 2 HDMI_GENERIC2_SEND 0 0 HDMI_GENERIC2_CONT 1 1 HDMI_GENERIC3_SEND 4 4 HDMI_GENERIC3_CONT 5 5 HDMI_GENERIC2_LINE 16 21 HDMI_GENERIC3_LINE 24 29 mmDIG4_HDMI_ACR_32_0 0 0x1cac 1 0 2 HDMI_ACR_CTS_32 12 31 mmDIG4_HDMI_ACR_32_1 0 0x1cad 1 0 2 HDMI_ACR_N_32 0 19 mmDIG4_HDMI_ACR_44_0 0 0x1cae 1 0 2 HDMI_ACR_CTS_44 12 31 mmDIG4_HDMI_ACR_44_1 0 0x1caf 1 0 2 HDMI_ACR_N_44 0 19 mmDIG4_HDMI_ACR_48_0 0 0x1cb0 1 0 2 HDMI_ACR_CTS_48 12 31 mmDIG4_HDMI_ACR_48_1 0 0x1cb1 1 0 2 HDMI_ACR_N_48 0 19 mmDIG4_HDMI_ACR_STATUS_0 0 0x1cb2 1 0 2 HDMI_ACR_CTS 12 31 mmDIG4_HDMI_ACR_STATUS_1 0 0x1cb3 1 0 2 HDMI_ACR_N 0 19 mmDIG4_AFMT_AUDIO_INFO0 0 0x1cb4 5 0 2 AFMT_AUDIO_INFO_CHECKSUM 0 7 AFMT_AUDIO_INFO_CC 8 10 AFMT_AUDIO_INFO_CT 11 14 AFMT_AUDIO_INFO_CHECKSUM_OFFSET 16 23 AFMT_AUDIO_INFO_CXT 24 28 mmDIG4_AFMT_AUDIO_INFO1 0 0x1cb5 4 0 2 AFMT_AUDIO_INFO_CA 0 7 AFMT_AUDIO_INFO_LSV 11 14 AFMT_AUDIO_INFO_DM_INH 15 15 AFMT_AUDIO_INFO_LFEPBL 16 17 mmDIG4_AFMT_60958_0 0 0x1cb6 10 0 2 AFMT_60958_CS_A 0 0 AFMT_60958_CS_B 1 1 AFMT_60958_CS_C 2 2 AFMT_60958_CS_D 3 5 AFMT_60958_CS_MODE 6 7 AFMT_60958_CS_CATEGORY_CODE 8 15 AFMT_60958_CS_SOURCE_NUMBER 16 19 AFMT_60958_CS_CHANNEL_NUMBER_L 20 23 AFMT_60958_CS_SAMPLING_FREQUENCY 24 27 AFMT_60958_CS_CLOCK_ACCURACY 28 29 mmDIG4_AFMT_60958_1 0 0x1cb7 5 0 2 AFMT_60958_CS_WORD_LENGTH 0 3 AFMT_60958_CS_ORIGINAL_SAMPLING_FREQUENCY 4 7 AFMT_60958_VALID_L 16 16 AFMT_60958_VALID_R 18 18 AFMT_60958_CS_CHANNEL_NUMBER_R 20 23 mmDIG4_AFMT_AUDIO_CRC_CONTROL 0 0x1cb8 5 0 2 AFMT_AUDIO_CRC_EN 0 0 AFMT_AUDIO_CRC_CONT 4 4 AFMT_AUDIO_CRC_SOURCE 8 8 AFMT_AUDIO_CRC_CH_SEL 12 15 AFMT_AUDIO_CRC_COUNT 16 31 mmDIG4_AFMT_RAMP_CONTROL0 0 0x1cb9 2 0 2 AFMT_RAMP_MAX_COUNT 0 23 AFMT_RAMP_DATA_SIGN 31 31 mmDIG4_AFMT_RAMP_CONTROL1 0 0x1cba 2 0 2 AFMT_RAMP_MIN_COUNT 0 23 AFMT_AUDIO_TEST_CH_DISABLE 24 31 mmDIG4_AFMT_RAMP_CONTROL2 0 0x1cbb 1 0 2 AFMT_RAMP_INC_COUNT 0 23 mmDIG4_AFMT_RAMP_CONTROL3 0 0x1cbc 1 0 2 AFMT_RAMP_DEC_COUNT 0 23 mmDIG4_AFMT_60958_2 0 0x1cbd 6 0 2 AFMT_60958_CS_CHANNEL_NUMBER_2 0 3 AFMT_60958_CS_CHANNEL_NUMBER_3 4 7 AFMT_60958_CS_CHANNEL_NUMBER_4 8 11 AFMT_60958_CS_CHANNEL_NUMBER_5 12 15 AFMT_60958_CS_CHANNEL_NUMBER_6 16 19 AFMT_60958_CS_CHANNEL_NUMBER_7 20 23 mmDIG4_AFMT_AUDIO_CRC_RESULT 0 0x1cbe 2 0 2 AFMT_AUDIO_CRC_DONE 0 0 AFMT_AUDIO_CRC 8 31 mmDIG4_AFMT_STATUS 0 0x1cbf 4 0 2 AFMT_AUDIO_ENABLE 4 4 AFMT_AZ_HBR_ENABLE 8 8 AFMT_AUDIO_FIFO_OVERFLOW 24 24 AFMT_AZ_AUDIO_ENABLE_CHG 30 30 mmDIG4_AFMT_AUDIO_PACKET_CONTROL 0 0x1cc0 8 0 2 AFMT_AUDIO_SAMPLE_SEND 0 0 AFMT_RESET_FIFO_WHEN_AUDIO_DIS 11 11 AFMT_AUDIO_TEST_EN 12 12 AFMT_AUDIO_TEST_MODE 14 14 AFMT_AUDIO_FIFO_OVERFLOW_ACK 23 23 AFMT_AUDIO_CHANNEL_SWAP 24 24 AFMT_60958_CS_UPDATE 26 26 AFMT_AZ_AUDIO_ENABLE_CHG_ACK 30 30 mmDIG4_AFMT_VBI_PACKET_CONTROL 0 0x1cc1 3 0 2 AFMT_GENERIC0_UPDATE 2 2 AFMT_GENERIC2_UPDATE 3 3 AFMT_GENERIC_INDEX 30 31 mmDIG4_AFMT_INFOFRAME_CONTROL0 0 0x1cc2 3 0 2 AFMT_AUDIO_INFO_SOURCE 6 6 AFMT_AUDIO_INFO_UPDATE 7 7 AFMT_MPEG_INFO_UPDATE 10 10 mmDIG4_AFMT_AUDIO_SRC_CONTROL 0 0x1cc3 1 0 2 AFMT_AUDIO_SRC_SELECT 0 2 mmDIG4_DIG_BE_CNTL 0 0x1cc5 5 0 2 DIG_DUAL_LINK_ENABLE 0 0 DIG_SWAP 1 1 DIG_FE_SOURCE_SELECT 8 14 DIG_MODE 16 18 DIG_HPD_SELECT 28 30 mmDIG4_DIG_BE_EN_CNTL 0 0x1cc6 2 0 2 DIG_ENABLE 0 0 DIG_SYMCLK_BE_ON 8 8 mmDIG4_TMDS_CNTL 0 0x1ce9 1 0 2 TMDS_SYNC_PHASE 0 0 mmDIG4_TMDS_CONTROL_CHAR 0 0x1cea 4 0 2 TMDS_CONTROL_CHAR0_OUT_EN 0 0 TMDS_CONTROL_CHAR1_OUT_EN 1 1 TMDS_CONTROL_CHAR2_OUT_EN 2 2 TMDS_CONTROL_CHAR3_OUT_EN 3 3 mmDIG4_TMDS_CONTROL0_FEEDBACK 0 0x1ceb 2 0 2 TMDS_CONTROL0_FEEDBACK_SELECT 0 1 TMDS_CONTROL0_FEEDBACK_DELAY 8 9 mmDIG4_TMDS_STEREOSYNC_CTL_SEL 0 0x1cec 1 0 2 TMDS_STEREOSYNC_CTL_SEL 0 1 mmDIG4_TMDS_SYNC_CHAR_PATTERN_0_1 0 0x1ced 2 0 2 TMDS_SYNC_CHAR_PATTERN0 0 9 TMDS_SYNC_CHAR_PATTERN1 16 25 mmDIG4_TMDS_SYNC_CHAR_PATTERN_2_3 0 0x1cee 2 0 2 TMDS_SYNC_CHAR_PATTERN2 0 9 TMDS_SYNC_CHAR_PATTERN3 16 25 mmDIG4_TMDS_CTL_BITS 0 0x1cf0 4 0 2 TMDS_CTL0 0 0 TMDS_CTL1 8 8 TMDS_CTL2 16 16 TMDS_CTL3 24 24 mmDIG4_TMDS_DCBALANCER_CONTROL 0 0x1cf1 4 0 2 TMDS_DCBALANCER_EN 0 0 TMDS_DCBALANCER_TEST_EN 8 8 TMDS_DCBALANCER_TEST_IN 16 19 TMDS_DCBALANCER_FORCE 24 24 mmDIG4_TMDS_CTL0_1_GEN_CNTL 0 0x1cf3 15 0 2 TMDS_CTL0_DATA_SEL 0 3 TMDS_CTL0_DATA_DELAY 4 6 TMDS_CTL0_DATA_INVERT 7 7 TMDS_CTL0_DATA_MODULATION 8 9 TMDS_CTL0_USE_FEEDBACK_PATH 10 10 TMDS_CTL0_FB_SYNC_CONT 11 11 TMDS_CTL0_PATTERN_OUT_EN 12 12 TMDS_CTL1_DATA_SEL 16 19 TMDS_CTL1_DATA_DELAY 20 22 TMDS_CTL1_DATA_INVERT 23 23 TMDS_CTL1_DATA_MODULATION 24 25 TMDS_CTL1_USE_FEEDBACK_PATH 26 26 TMDS_CTL1_FB_SYNC_CONT 27 27 TMDS_CTL1_PATTERN_OUT_EN 28 28 TMDS_2BIT_COUNTER_EN 31 31 mmDIG4_TMDS_CTL2_3_GEN_CNTL 0 0x1cf4 14 0 2 TMDS_CTL2_DATA_SEL 0 3 TMDS_CTL2_DATA_DELAY 4 6 TMDS_CTL2_DATA_INVERT 7 7 TMDS_CTL2_DATA_MODULATION 8 9 TMDS_CTL2_USE_FEEDBACK_PATH 10 10 TMDS_CTL2_FB_SYNC_CONT 11 11 TMDS_CTL2_PATTERN_OUT_EN 12 12 TMDS_CTL3_DATA_SEL 16 19 TMDS_CTL3_DATA_DELAY 20 22 TMDS_CTL3_DATA_INVERT 23 23 TMDS_CTL3_DATA_MODULATION 24 25 TMDS_CTL3_USE_FEEDBACK_PATH 26 26 TMDS_CTL3_FB_SYNC_CONT 27 27 TMDS_CTL3_PATTERN_OUT_EN 28 28 mmDIG4_DIG_VERSION 0 0x1cf6 1 0 2 DIG_TYPE 0 0 mmDIG4_DIG_LANE_ENABLE 0 0x1cf7 5 0 2 DIG_LANE0EN 0 0 DIG_LANE1EN 1 1 DIG_LANE2EN 2 2 DIG_LANE3EN 3 3 DIG_CLK_EN 8 8 mmDIG4_AFMT_CNTL 0 0x1cfc 2 0 2 AFMT_AUDIO_CLOCK_EN 0 0 AFMT_AUDIO_CLOCK_ON 8 8 mmDP4_DP_LINK_CNTL 0 0x1d1e 3 0 2 DP_LINK_TRAINING_COMPLETE 4 4 DP_LINK_STATUS 8 8 DP_EMBEDDED_PANEL_MODE 17 17 mmDP4_DP_PIXEL_FORMAT 0 0x1d1f 4 0 2 DP_PIXEL_ENCODING 0 2 DP_DYN_RANGE 8 8 DP_YCBCR_RANGE 16 16 DP_COMPONENT_DEPTH 24 26 mmDP4_DP_MSA_COLORIMETRY 0 0x1d20 4 0 2 DP_MSA_MISC0_OVERRIDE 0 7 DP_MSA_MISC0_OVERRIDE_ENABLE 8 8 DP_MSA_MISC1_BIT7_OVERRIDE 9 9 DP_MSA_MISC1_BIT7_OVERRIDE_ENABLE 17 17 mmDP4_DP_CONFIG 0 0x1d21 1 0 2 DP_UDI_LANES 0 1 mmDP4_DP_VID_STREAM_CNTL 0 0x1d22 4 0 2 DP_VID_STREAM_ENABLE 0 0 DP_VID_STREAM_DIS_DEFER 8 9 DP_VID_STREAM_STATUS 16 16 DP_VID_STREAM_CHANGE_KEEPOUT 20 20 mmDP4_DP_STEER_FIFO 0 0x1d23 7 0 2 DP_STEER_FIFO_RESET 0 0 DP_STEER_OVERFLOW_FLAG 4 4 DP_STEER_OVERFLOW_INT 5 5 DP_STEER_OVERFLOW_ACK 6 6 DP_STEER_OVERFLOW_MASK 7 7 DP_TU_OVERFLOW_FLAG 8 8 DP_TU_OVERFLOW_ACK 12 12 mmDP4_DP_MSA_MISC 0 0x1d24 4 0 2 DP_MSA_MISC1 3 6 DP_MSA_MISC2 8 15 DP_MSA_MISC3 16 23 DP_MSA_MISC4 24 31 mmDP4_DP_VID_TIMING 0 0x1d26 5 0 2 DP_VID_TIMING_MODE 0 0 DP_VID_M_N_DOUBLE_BUFFER_MODE 4 4 DP_VID_M_N_GEN_EN 8 8 DP_VID_M_DOUBLE_VALUE_EN 9 9 DP_VID_N_DIV 24 31 mmDP4_DP_VID_N 0 0x1d27 1 0 2 DP_VID_N 0 23 mmDP4_DP_VID_M 0 0x1d28 1 0 2 DP_VID_M 0 23 mmDP4_DP_LINK_FRAMING_CNTL 0 0x1d29 3 0 2 DP_IDLE_BS_INTERVAL 0 17 DP_VBID_DISABLE 24 24 DP_VID_ENHANCED_FRAME_MODE 28 28 mmDP4_DP_HBR2_EYE_PATTERN 0 0x1d2a 1 0 2 DP_HBR2_EYE_PATTERN_ENABLE 0 0 mmDP4_DP_VID_MSA_VBID 0 0x1d2b 3 0 2 DP_VID_MSA_LOCATION 0 11 DP_VID_MSA_TOP_FIELD_MODE 16 16 DP_VID_VBID_FIELD_POL 24 24 mmDP4_DP_VID_INTERRUPT_CNTL 0 0x1d2c 3 0 2 DP_VID_STREAM_DISABLE_INT 0 0 DP_VID_STREAM_DISABLE_ACK 1 1 DP_VID_STREAM_DISABLE_MASK 2 2 mmDP4_DP_DPHY_CNTL 0 0x1d2d 6 0 2 DPHY_ATEST_SEL_LANE0 0 0 DPHY_ATEST_SEL_LANE1 1 1 DPHY_ATEST_SEL_LANE2 2 2 DPHY_ATEST_SEL_LANE3 3 3 DPHY_BYPASS 16 16 DPHY_SKEW_BYPASS 24 24 mmDP4_DP_DPHY_TRAINING_PATTERN_SEL 0 0x1d2e 1 0 2 DPHY_TRAINING_PATTERN_SEL 0 1 mmDP4_DP_DPHY_SYM0 0 0x1d2f 3 0 2 DPHY_SYM1 0 9 DPHY_SYM2 10 19 DPHY_SYM3 20 29 mmDP4_DP_DPHY_SYM1 0 0x1d30 3 0 2 DPHY_SYM4 0 9 DPHY_SYM5 10 19 DPHY_SYM6 20 29 mmDP4_DP_DPHY_SYM2 0 0x1d31 2 0 2 DPHY_SYM7 0 9 DPHY_SYM8 10 19 mmDP4_DP_DPHY_8B10B_CNTL 0 0x1d32 3 0 2 DPHY_8B10B_RESET 8 8 DPHY_8B10B_EXT_DISP 16 16 DPHY_8B10B_CUR_DISP 24 24 mmDP4_DP_DPHY_PRBS_CNTL 0 0x1d33 3 0 2 DPHY_PRBS_EN 0 0 DPHY_PRBS_SEL 4 5 DPHY_PRBS_SEED 8 30 mmDP4_DP_DPHY_SCRAM_CNTL 0 0x1d34 4 0 2 DPHY_SCRAMBLER_DIS 0 0 DPHY_SCRAMBLER_ADVANCE 4 4 DPHY_SCRAMBLER_BS_COUNT 8 17 DPHY_SCRAMBLER_KCODE 24 24 mmDP4_DP_DPHY_CRC_EN 0 0x1d35 3 0 2 DPHY_CRC_EN 0 0 DPHY_CRC_CONT_EN 4 4 DPHY_CRC_RESULT_VALID 8 8 mmDP4_DP_DPHY_CRC_CNTL 0 0x1d36 3 0 2 DPHY_CRC_FIELD 0 0 DPHY_CRC_SEL 4 5 DPHY_CRC_MASK 16 23 mmDP4_DP_DPHY_CRC_RESULT 0 0x1d37 4 0 2 DPHY_CRC_RESULT 0 7 DPHY_CRC_RESULT1 8 15 DPHY_CRC_RESULT2 16 23 DPHY_CRC_RESULT3 24 31 mmDP4_DP_DPHY_CRC_MST_CNTL 0 0x1d38 2 0 2 DPHY_CRC_MST_FIRST_SLOT 0 5 DPHY_CRC_MST_LAST_SLOT 8 13 mmDP4_DP_DPHY_CRC_MST_STATUS 0 0x1d39 3 0 2 DPHY_CRC_MST_PHASE_LOCK 0 0 DPHY_CRC_MST_PHASE_ERROR 8 8 DPHY_CRC_MST_PHASE_ERROR_ACK 16 16 mmDP4_DP_DPHY_FAST_TRAINING 0 0x1d3a 5 0 2 DPHY_RX_FAST_TRAINING_CAPABLE 0 0 DPHY_SW_FAST_TRAINING_START 1 1 DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN 2 2 DPHY_FAST_TRAINING_TP1_TIME 8 19 DPHY_FAST_TRAINING_TP2_TIME 20 31 mmDP4_DP_DPHY_FAST_TRAINING_STATUS 0 0x1d3b 4 0 2 DPHY_FAST_TRAINING_STATE 0 2 DPHY_FAST_TRAINING_COMPLETE_OCCURRED 4 4 DPHY_FAST_TRAINING_COMPLETE_MASK 8 8 DPHY_FAST_TRAINING_COMPLETE_ACK 12 12 mmDP4_DP_MSA_V_TIMING_OVERRIDE1 0 0x1d3c 2 0 2 DP_MSA_V_TIMING_OVERRIDE_EN 0 0 DP_MSA_V_TOTAL_OVERRIDE 4 17 mmDP4_DP_MSA_V_TIMING_OVERRIDE2 0 0x1d3d 2 0 2 DP_MSA_V_BLANK_START_OVERRIDE 0 13 DP_MSA_V_BLANK_END_OVERRIDE 16 29 mmDP4_DP_SEC_CNTL 0 0x1d41 11 0 2 DP_SEC_STREAM_ENABLE 0 0 DP_SEC_ASP_ENABLE 4 4 DP_SEC_ATP_ENABLE 8 8 DP_SEC_AIP_ENABLE 12 12 DP_SEC_ACM_ENABLE 16 16 DP_SEC_GSP0_ENABLE 20 20 DP_SEC_GSP1_ENABLE 21 21 DP_SEC_GSP2_ENABLE 22 22 DP_SEC_GSP3_ENABLE 23 23 DP_SEC_AVI_ENABLE 24 24 DP_SEC_MPG_ENABLE 28 28 mmDP4_DP_SEC_CNTL1 0 0x1d42 6 0 2 DP_SEC_ISRC_ENABLE 0 0 DP_SEC_GSP0_PRIORITY 4 4 DP_SEC_GSP0_SEND 5 5 DP_SEC_GSP0_SEND_PENDING 6 6 DP_SEC_GSP0_SEND_DEADLINE_MISSED 7 7 DP_SEC_GSP0_LINE_NUM 16 31 mmDP4_DP_SEC_FRAMING1 0 0x1d43 2 0 2 DP_SEC_FRAME_START_LOCATION 0 11 DP_SEC_VBLANK_TRANSMIT_WIDTH 16 31 mmDP4_DP_SEC_FRAMING2 0 0x1d44 2 0 2 DP_SEC_START_POSITION 0 15 DP_SEC_HBLANK_TRANSMIT_WIDTH 16 31 mmDP4_DP_SEC_FRAMING3 0 0x1d45 2 0 2 DP_SEC_IDLE_FRAME_SIZE 0 13 DP_SEC_IDLE_TRANSMIT_WIDTH 16 31 mmDP4_DP_SEC_FRAMING4 0 0x1d46 4 0 2 DP_SEC_COLLISION_STATUS 20 20 DP_SEC_COLLISION_ACK 24 24 DP_SEC_AUDIO_MUTE 28 28 DP_SEC_AUDIO_MUTE_STATUS 29 29 mmDP4_DP_SEC_AUD_N 0 0x1d47 1 0 2 DP_SEC_AUD_N 0 23 mmDP4_DP_SEC_AUD_N_READBACK 0 0x1d48 1 0 2 DP_SEC_AUD_N_READBACK 0 23 mmDP4_DP_SEC_AUD_M 0 0x1d49 1 0 2 DP_SEC_AUD_M 0 23 mmDP4_DP_SEC_AUD_M_READBACK 0 0x1d4a 1 0 2 DP_SEC_AUD_M_READBACK 0 23 mmDP4_DP_SEC_TIMESTAMP 0 0x1d4b 1 0 2 DP_SEC_TIMESTAMP_MODE 0 0 mmDP4_DP_SEC_PACKET_CNTL 0 0x1d4c 4 0 2 DP_SEC_ASP_CODING_TYPE 1 3 DP_SEC_ASP_PRIORITY 4 4 DP_SEC_VERSION 8 13 DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE 16 16 mmDP4_DP_MSE_RATE_CNTL 0 0x1d4d 2 0 2 DP_MSE_RATE_Y 0 25 DP_MSE_RATE_X 26 31 mmDP4_DP_MSE_RATE_UPDATE 0 0x1d4f 1 0 2 DP_MSE_RATE_UPDATE_PENDING 0 0 mmDP4_DP_MSE_SAT0 0 0x1d50 4 0 2 DP_MSE_SAT_SRC0 0 2 DP_MSE_SAT_SLOT_COUNT0 8 13 DP_MSE_SAT_SRC1 16 18 DP_MSE_SAT_SLOT_COUNT1 24 29 mmDP4_DP_MSE_SAT1 0 0x1d51 4 0 2 DP_MSE_SAT_SRC2 0 2 DP_MSE_SAT_SLOT_COUNT2 8 13 DP_MSE_SAT_SRC3 16 18 DP_MSE_SAT_SLOT_COUNT3 24 29 mmDP4_DP_MSE_SAT2 0 0x1d52 4 0 2 DP_MSE_SAT_SRC4 0 2 DP_MSE_SAT_SLOT_COUNT4 8 13 DP_MSE_SAT_SRC5 16 18 DP_MSE_SAT_SLOT_COUNT5 24 29 mmDP4_DP_MSE_SAT_UPDATE 0 0x1d53 2 0 2 DP_MSE_SAT_UPDATE 0 1 DP_MSE_16_MTP_KEEPOUT 8 8 mmDP4_DP_MSE_LINK_TIMING 0 0x1d54 2 0 2 DP_MSE_LINK_FRAME 0 9 DP_MSE_LINK_LINE 16 17 mmDP4_DP_MSE_MISC_CNTL 0 0x1d55 3 0 2 DP_MSE_BLANK_CODE 0 0 DP_MSE_TIMESTAMP_MODE 4 4 DP_MSE_ZERO_ENCODER 8 8 mmDP4_DP_DPHY_BS_SR_SWAP_CNTL 0 0x1d5a 3 0 2 DPHY_LOAD_BS_COUNT 0 9 DPHY_BS_SR_SWAP_DONE 15 15 DPHY_LOAD_BS_COUNT_START 16 16 mmDP4_DP_DPHY_HBR2_PATTERN_CONTROL 0 0x1d5b 1 0 2 DP_DPHY_HBR2_PATTERN_CONTROL 0 2 mmDP4_DP_MSE_SAT0_STATUS 0 0x1d5d 4 0 2 DP_MSE_SAT_SRC0_STATUS 0 2 DP_MSE_SAT_SLOT_COUNT0_STATUS 8 13 DP_MSE_SAT_SRC1_STATUS 16 18 DP_MSE_SAT_SLOT_COUNT1_STATUS 24 29 mmDP4_DP_MSE_SAT1_STATUS 0 0x1d5e 4 0 2 DP_MSE_SAT_SRC2_STATUS 0 2 DP_MSE_SAT_SLOT_COUNT2_STATUS 8 13 DP_MSE_SAT_SRC3_STATUS 16 18 DP_MSE_SAT_SLOT_COUNT3_STATUS 24 29 mmDP4_DP_MSE_SAT2_STATUS 0 0x1d5f 4 0 2 DP_MSE_SAT_SRC4_STATUS 0 2 DP_MSE_SAT_SLOT_COUNT4_STATUS 8 13 DP_MSE_SAT_SRC5_STATUS 16 18 DP_MSE_SAT_SLOT_COUNT5_STATUS 24 29 mmDIG5_DIG_FE_CNTL 0 0x1d7e 7 0 2 DIG_SOURCE_SELECT 0 2 DIG_STEREOSYNC_SELECT 4 6 DIG_STEREOSYNC_GATE_EN 8 8 DIG_START 10 10 DIG_SYMCLK_FE_ON 24 24 TMDS_PIXEL_ENCODING 28 28 TMDS_COLOR_FORMAT 30 31 mmDIG5_DIG_OUTPUT_CRC_CNTL 0 0x1d7f 3 0 2 DIG_OUTPUT_CRC_EN 0 0 DIG_OUTPUT_CRC_LINK_SEL 4 4 DIG_OUTPUT_CRC_DATA_SEL 8 9 mmDIG5_DIG_OUTPUT_CRC_RESULT 0 0x1d80 1 0 2 DIG_OUTPUT_CRC_RESULT 0 29 mmDIG5_DIG_CLOCK_PATTERN 0 0x1d81 1 0 2 DIG_CLOCK_PATTERN 0 9 mmDIG5_DIG_TEST_PATTERN 0 0x1d82 6 0 2 DIG_TEST_PATTERN_OUT_EN 0 0 DIG_HALF_CLOCK_PATTERN_SEL 1 1 DIG_RANDOM_PATTERN_OUT_EN 4 4 DIG_RANDOM_PATTERN_RESET 5 5 DIG_TEST_PATTERN_EXTERNAL_RESET_EN 6 6 DIG_STATIC_TEST_PATTERN 16 25 mmDIG5_DIG_RANDOM_PATTERN_SEED 0 0x1d83 2 0 2 DIG_RANDOM_PATTERN_SEED 0 23 DIG_RAN_PAT_DURING_DE_ONLY 24 24 mmDIG5_DIG_FIFO_STATUS 0 0x1d84 11 0 2 DIG_FIFO_LEVEL_ERROR 0 0 DIG_FIFO_USE_OVERWRITE_LEVEL 1 1 DIG_FIFO_OVERWRITE_LEVEL 2 7 DIG_FIFO_ERROR_ACK 8 8 DIG_FIFO_CAL_AVERAGE_LEVEL 10 15 DIG_FIFO_MAXIMUM_LEVEL 16 20 DIG_FIFO_MINIMUM_LEVEL 22 25 DIG_FIFO_READ_CLOCK_SRC 26 26 DIG_FIFO_CALIBRATED 29 29 DIG_FIFO_FORCE_RECAL_AVERAGE 30 30 DIG_FIFO_FORCE_RECOMP_MINMAX 31 31 mmDIG5_HDMI_CONTROL 0 0x1d87 9 0 2 HDMI_KEEPOUT_MODE 0 0 HDMI_DATA_SCRAMBLE_EN 1 1 HDMI_CLOCK_CHANNEL_RATE 2 2 HDMI_NO_EXTRA_NULL_PACKET_FILLED 3 3 HDMI_PACKET_GEN_VERSION 4 4 HDMI_ERROR_ACK 8 8 HDMI_ERROR_MASK 9 9 HDMI_DEEP_COLOR_ENABLE 24 24 HDMI_DEEP_COLOR_DEPTH 28 29 mmDIG5_HDMI_STATUS 0 0x1d88 4 0 2 HDMI_ACTIVE_AVMUTE 0 0 HDMI_AUDIO_PACKET_ERROR 16 16 HDMI_VBI_PACKET_ERROR 20 20 HDMI_ERROR_INT 27 27 mmDIG5_HDMI_AUDIO_PACKET_CONTROL 0 0x1d89 2 0 2 HDMI_AUDIO_DELAY_EN 4 5 HDMI_AUDIO_PACKETS_PER_LINE 16 20 mmDIG5_HDMI_ACR_PACKET_CONTROL 0 0x1d8a 7 0 2 HDMI_ACR_SEND 0 0 HDMI_ACR_CONT 1 1 HDMI_ACR_SELECT 4 5 HDMI_ACR_SOURCE 8 8 HDMI_ACR_AUTO_SEND 12 12 HDMI_ACR_N_MULTIPLE 16 18 HDMI_ACR_AUDIO_PRIORITY 31 31 mmDIG5_HDMI_VBI_PACKET_CONTROL 0 0x1d8b 6 0 2 HDMI_NULL_SEND 0 0 HDMI_GC_SEND 4 4 HDMI_GC_CONT 5 5 HDMI_ISRC_SEND 8 8 HDMI_ISRC_CONT 9 9 HDMI_ISRC_LINE 16 21 mmDIG5_HDMI_INFOFRAME_CONTROL0 0 0x1d8c 6 0 2 HDMI_AVI_INFO_SEND 0 0 HDMI_AVI_INFO_CONT 1 1 HDMI_AUDIO_INFO_SEND 4 4 HDMI_AUDIO_INFO_CONT 5 5 HDMI_MPEG_INFO_SEND 8 8 HDMI_MPEG_INFO_CONT 9 9 mmDIG5_HDMI_INFOFRAME_CONTROL1 0 0x1d8d 3 0 2 HDMI_AVI_INFO_LINE 0 5 HDMI_AUDIO_INFO_LINE 8 13 HDMI_MPEG_INFO_LINE 16 21 mmDIG5_HDMI_GENERIC_PACKET_CONTROL0 0 0x1d8e 6 0 2 HDMI_GENERIC0_SEND 0 0 HDMI_GENERIC0_CONT 1 1 HDMI_GENERIC1_SEND 4 4 HDMI_GENERIC1_CONT 5 5 HDMI_GENERIC0_LINE 16 21 HDMI_GENERIC1_LINE 24 29 mmDIG5_AFMT_INTERRUPT_STATUS 0 0x1d8f 0 0 2 mmDIG5_HDMI_GC 0 0x1d91 5 0 2 HDMI_GC_AVMUTE 0 0 HDMI_GC_AVMUTE_CONT 2 2 HDMI_DEFAULT_PHASE 4 4 HDMI_PACKING_PHASE 8 11 HDMI_PACKING_PHASE_OVERRIDE 12 12 mmDIG5_AFMT_AUDIO_PACKET_CONTROL2 0 0x1d92 6 0 2 AFMT_AUDIO_LAYOUT_OVRD 0 0 AFMT_AUDIO_LAYOUT_SELECT 1 1 AFMT_AUDIO_CHANNEL_ENABLE 8 15 AFMT_DP_AUDIO_STREAM_ID 16 23 AFMT_HBR_ENABLE_OVRD 24 24 AFMT_60958_OSF_OVRD 28 28 mmDIG5_AFMT_ISRC1_0 0 0x1d93 3 0 2 AFMT_ISRC_STATUS 0 2 AFMT_ISRC_CONTINUE 6 6 AFMT_ISRC_VALID 7 7 mmDIG5_AFMT_ISRC1_1 0 0x1d94 4 0 2 AFMT_UPC_EAN_ISRC0 0 7 AFMT_UPC_EAN_ISRC1 8 15 AFMT_UPC_EAN_ISRC2 16 23 AFMT_UPC_EAN_ISRC3 24 31 mmDIG5_AFMT_ISRC1_2 0 0x1d95 4 0 2 AFMT_UPC_EAN_ISRC4 0 7 AFMT_UPC_EAN_ISRC5 8 15 AFMT_UPC_EAN_ISRC6 16 23 AFMT_UPC_EAN_ISRC7 24 31 mmDIG5_AFMT_ISRC1_3 0 0x1d96 4 0 2 AFMT_UPC_EAN_ISRC8 0 7 AFMT_UPC_EAN_ISRC9 8 15 AFMT_UPC_EAN_ISRC10 16 23 AFMT_UPC_EAN_ISRC11 24 31 mmDIG5_AFMT_ISRC1_4 0 0x1d97 4 0 2 AFMT_UPC_EAN_ISRC12 0 7 AFMT_UPC_EAN_ISRC13 8 15 AFMT_UPC_EAN_ISRC14 16 23 AFMT_UPC_EAN_ISRC15 24 31 mmDIG5_AFMT_ISRC2_0 0 0x1d98 4 0 2 AFMT_UPC_EAN_ISRC16 0 7 AFMT_UPC_EAN_ISRC17 8 15 AFMT_UPC_EAN_ISRC18 16 23 AFMT_UPC_EAN_ISRC19 24 31 mmDIG5_AFMT_ISRC2_1 0 0x1d99 4 0 2 AFMT_UPC_EAN_ISRC20 0 7 AFMT_UPC_EAN_ISRC21 8 15 AFMT_UPC_EAN_ISRC22 16 23 AFMT_UPC_EAN_ISRC23 24 31 mmDIG5_AFMT_ISRC2_2 0 0x1d9a 4 0 2 AFMT_UPC_EAN_ISRC24 0 7 AFMT_UPC_EAN_ISRC25 8 15 AFMT_UPC_EAN_ISRC26 16 23 AFMT_UPC_EAN_ISRC27 24 31 mmDIG5_AFMT_ISRC2_3 0 0x1d9b 4 0 2 AFMT_UPC_EAN_ISRC28 0 7 AFMT_UPC_EAN_ISRC29 8 15 AFMT_UPC_EAN_ISRC30 16 23 AFMT_UPC_EAN_ISRC31 24 31 mmDIG5_AFMT_AVI_INFO0 0 0x1d9c 12 0 2 AFMT_AVI_INFO_CHECKSUM 0 7 AFMT_AVI_INFO_S 8 9 AFMT_AVI_INFO_B 10 11 AFMT_AVI_INFO_A 12 12 AFMT_AVI_INFO_Y 13 15 AFMT_AVI_INFO_R 16 19 AFMT_AVI_INFO_M 20 21 AFMT_AVI_INFO_C 22 23 AFMT_AVI_INFO_SC 24 25 AFMT_AVI_INFO_Q 26 27 AFMT_AVI_INFO_EC 28 30 AFMT_AVI_INFO_ITC 31 31 mmDIG5_AFMT_AVI_INFO1 0 0x1d9d 5 0 2 AFMT_AVI_INFO_VIC 0 7 AFMT_AVI_INFO_PR 8 11 AFMT_AVI_INFO_CN 12 13 AFMT_AVI_INFO_YQ 14 15 AFMT_AVI_INFO_TOP 16 31 mmDIG5_AFMT_AVI_INFO2 0 0x1d9e 2 0 2 AFMT_AVI_INFO_BOTTOM 0 15 AFMT_AVI_INFO_LEFT 16 31 mmDIG5_AFMT_AVI_INFO3 0 0x1d9f 2 0 2 AFMT_AVI_INFO_RIGHT 0 15 AFMT_AVI_INFO_VERSION 24 31 mmDIG5_AFMT_MPEG_INFO0 0 0x1da0 4 0 2 AFMT_MPEG_INFO_CHECKSUM 0 7 AFMT_MPEG_INFO_MB0 8 15 AFMT_MPEG_INFO_MB1 16 23 AFMT_MPEG_INFO_MB2 24 31 mmDIG5_AFMT_MPEG_INFO1 0 0x1da1 3 0 2 AFMT_MPEG_INFO_MB3 0 7 AFMT_MPEG_INFO_MF 8 9 AFMT_MPEG_INFO_FR 12 12 mmDIG5_AFMT_GENERIC_HDR 0 0x1da2 4 0 2 AFMT_GENERIC_HB0 0 7 AFMT_GENERIC_HB1 8 15 AFMT_GENERIC_HB2 16 23 AFMT_GENERIC_HB3 24 31 mmDIG5_AFMT_GENERIC_0 0 0x1da3 4 0 2 AFMT_GENERIC_BYTE0 0 7 AFMT_GENERIC_BYTE1 8 15 AFMT_GENERIC_BYTE2 16 23 AFMT_GENERIC_BYTE3 24 31 mmDIG5_AFMT_GENERIC_1 0 0x1da4 4 0 2 AFMT_GENERIC_BYTE4 0 7 AFMT_GENERIC_BYTE5 8 15 AFMT_GENERIC_BYTE6 16 23 AFMT_GENERIC_BYTE7 24 31 mmDIG5_AFMT_GENERIC_2 0 0x1da5 4 0 2 AFMT_GENERIC_BYTE8 0 7 AFMT_GENERIC_BYTE9 8 15 AFMT_GENERIC_BYTE10 16 23 AFMT_GENERIC_BYTE11 24 31 mmDIG5_AFMT_GENERIC_3 0 0x1da6 4 0 2 AFMT_GENERIC_BYTE12 0 7 AFMT_GENERIC_BYTE13 8 15 AFMT_GENERIC_BYTE14 16 23 AFMT_GENERIC_BYTE15 24 31 mmDIG5_AFMT_GENERIC_4 0 0x1da7 4 0 2 AFMT_GENERIC_BYTE16 0 7 AFMT_GENERIC_BYTE17 8 15 AFMT_GENERIC_BYTE18 16 23 AFMT_GENERIC_BYTE19 24 31 mmDIG5_AFMT_GENERIC_5 0 0x1da8 4 0 2 AFMT_GENERIC_BYTE20 0 7 AFMT_GENERIC_BYTE21 8 15 AFMT_GENERIC_BYTE22 16 23 AFMT_GENERIC_BYTE23 24 31 mmDIG5_AFMT_GENERIC_6 0 0x1da9 4 0 2 AFMT_GENERIC_BYTE24 0 7 AFMT_GENERIC_BYTE25 8 15 AFMT_GENERIC_BYTE26 16 23 AFMT_GENERIC_BYTE27 24 31 mmDIG5_AFMT_GENERIC_7 0 0x1daa 4 0 2 AFMT_GENERIC_BYTE28 0 7 AFMT_GENERIC_BYTE29 8 15 AFMT_GENERIC_BYTE30 16 23 AFMT_GENERIC_BYTE31 24 31 mmDIG5_HDMI_GENERIC_PACKET_CONTROL1 0 0x1dab 6 0 2 HDMI_GENERIC2_SEND 0 0 HDMI_GENERIC2_CONT 1 1 HDMI_GENERIC3_SEND 4 4 HDMI_GENERIC3_CONT 5 5 HDMI_GENERIC2_LINE 16 21 HDMI_GENERIC3_LINE 24 29 mmDIG5_HDMI_ACR_32_0 0 0x1dac 1 0 2 HDMI_ACR_CTS_32 12 31 mmDIG5_HDMI_ACR_32_1 0 0x1dad 1 0 2 HDMI_ACR_N_32 0 19 mmDIG5_HDMI_ACR_44_0 0 0x1dae 1 0 2 HDMI_ACR_CTS_44 12 31 mmDIG5_HDMI_ACR_44_1 0 0x1daf 1 0 2 HDMI_ACR_N_44 0 19 mmDIG5_HDMI_ACR_48_0 0 0x1db0 1 0 2 HDMI_ACR_CTS_48 12 31 mmDIG5_HDMI_ACR_48_1 0 0x1db1 1 0 2 HDMI_ACR_N_48 0 19 mmDIG5_HDMI_ACR_STATUS_0 0 0x1db2 1 0 2 HDMI_ACR_CTS 12 31 mmDIG5_HDMI_ACR_STATUS_1 0 0x1db3 1 0 2 HDMI_ACR_N 0 19 mmDIG5_AFMT_AUDIO_INFO0 0 0x1db4 5 0 2 AFMT_AUDIO_INFO_CHECKSUM 0 7 AFMT_AUDIO_INFO_CC 8 10 AFMT_AUDIO_INFO_CT 11 14 AFMT_AUDIO_INFO_CHECKSUM_OFFSET 16 23 AFMT_AUDIO_INFO_CXT 24 28 mmDIG5_AFMT_AUDIO_INFO1 0 0x1db5 4 0 2 AFMT_AUDIO_INFO_CA 0 7 AFMT_AUDIO_INFO_LSV 11 14 AFMT_AUDIO_INFO_DM_INH 15 15 AFMT_AUDIO_INFO_LFEPBL 16 17 mmDIG5_AFMT_60958_0 0 0x1db6 10 0 2 AFMT_60958_CS_A 0 0 AFMT_60958_CS_B 1 1 AFMT_60958_CS_C 2 2 AFMT_60958_CS_D 3 5 AFMT_60958_CS_MODE 6 7 AFMT_60958_CS_CATEGORY_CODE 8 15 AFMT_60958_CS_SOURCE_NUMBER 16 19 AFMT_60958_CS_CHANNEL_NUMBER_L 20 23 AFMT_60958_CS_SAMPLING_FREQUENCY 24 27 AFMT_60958_CS_CLOCK_ACCURACY 28 29 mmDIG5_AFMT_60958_1 0 0x1db7 5 0 2 AFMT_60958_CS_WORD_LENGTH 0 3 AFMT_60958_CS_ORIGINAL_SAMPLING_FREQUENCY 4 7 AFMT_60958_VALID_L 16 16 AFMT_60958_VALID_R 18 18 AFMT_60958_CS_CHANNEL_NUMBER_R 20 23 mmDIG5_AFMT_AUDIO_CRC_CONTROL 0 0x1db8 5 0 2 AFMT_AUDIO_CRC_EN 0 0 AFMT_AUDIO_CRC_CONT 4 4 AFMT_AUDIO_CRC_SOURCE 8 8 AFMT_AUDIO_CRC_CH_SEL 12 15 AFMT_AUDIO_CRC_COUNT 16 31 mmDIG5_AFMT_RAMP_CONTROL0 0 0x1db9 2 0 2 AFMT_RAMP_MAX_COUNT 0 23 AFMT_RAMP_DATA_SIGN 31 31 mmDIG5_AFMT_RAMP_CONTROL1 0 0x1dba 2 0 2 AFMT_RAMP_MIN_COUNT 0 23 AFMT_AUDIO_TEST_CH_DISABLE 24 31 mmDIG5_AFMT_RAMP_CONTROL2 0 0x1dbb 1 0 2 AFMT_RAMP_INC_COUNT 0 23 mmDIG5_AFMT_RAMP_CONTROL3 0 0x1dbc 1 0 2 AFMT_RAMP_DEC_COUNT 0 23 mmDIG5_AFMT_60958_2 0 0x1dbd 6 0 2 AFMT_60958_CS_CHANNEL_NUMBER_2 0 3 AFMT_60958_CS_CHANNEL_NUMBER_3 4 7 AFMT_60958_CS_CHANNEL_NUMBER_4 8 11 AFMT_60958_CS_CHANNEL_NUMBER_5 12 15 AFMT_60958_CS_CHANNEL_NUMBER_6 16 19 AFMT_60958_CS_CHANNEL_NUMBER_7 20 23 mmDIG5_AFMT_AUDIO_CRC_RESULT 0 0x1dbe 2 0 2 AFMT_AUDIO_CRC_DONE 0 0 AFMT_AUDIO_CRC 8 31 mmDIG5_AFMT_STATUS 0 0x1dbf 4 0 2 AFMT_AUDIO_ENABLE 4 4 AFMT_AZ_HBR_ENABLE 8 8 AFMT_AUDIO_FIFO_OVERFLOW 24 24 AFMT_AZ_AUDIO_ENABLE_CHG 30 30 mmDIG5_AFMT_AUDIO_PACKET_CONTROL 0 0x1dc0 8 0 2 AFMT_AUDIO_SAMPLE_SEND 0 0 AFMT_RESET_FIFO_WHEN_AUDIO_DIS 11 11 AFMT_AUDIO_TEST_EN 12 12 AFMT_AUDIO_TEST_MODE 14 14 AFMT_AUDIO_FIFO_OVERFLOW_ACK 23 23 AFMT_AUDIO_CHANNEL_SWAP 24 24 AFMT_60958_CS_UPDATE 26 26 AFMT_AZ_AUDIO_ENABLE_CHG_ACK 30 30 mmDIG5_AFMT_VBI_PACKET_CONTROL 0 0x1dc1 3 0 2 AFMT_GENERIC0_UPDATE 2 2 AFMT_GENERIC2_UPDATE 3 3 AFMT_GENERIC_INDEX 30 31 mmDIG5_AFMT_INFOFRAME_CONTROL0 0 0x1dc2 3 0 2 AFMT_AUDIO_INFO_SOURCE 6 6 AFMT_AUDIO_INFO_UPDATE 7 7 AFMT_MPEG_INFO_UPDATE 10 10 mmDIG5_AFMT_AUDIO_SRC_CONTROL 0 0x1dc3 1 0 2 AFMT_AUDIO_SRC_SELECT 0 2 mmDIG5_DIG_BE_CNTL 0 0x1dc5 5 0 2 DIG_DUAL_LINK_ENABLE 0 0 DIG_SWAP 1 1 DIG_FE_SOURCE_SELECT 8 14 DIG_MODE 16 18 DIG_HPD_SELECT 28 30 mmDIG5_DIG_BE_EN_CNTL 0 0x1dc6 2 0 2 DIG_ENABLE 0 0 DIG_SYMCLK_BE_ON 8 8 mmDIG5_TMDS_CNTL 0 0x1de9 1 0 2 TMDS_SYNC_PHASE 0 0 mmDIG5_TMDS_CONTROL_CHAR 0 0x1dea 4 0 2 TMDS_CONTROL_CHAR0_OUT_EN 0 0 TMDS_CONTROL_CHAR1_OUT_EN 1 1 TMDS_CONTROL_CHAR2_OUT_EN 2 2 TMDS_CONTROL_CHAR3_OUT_EN 3 3 mmDIG5_TMDS_CONTROL0_FEEDBACK 0 0x1deb 2 0 2 TMDS_CONTROL0_FEEDBACK_SELECT 0 1 TMDS_CONTROL0_FEEDBACK_DELAY 8 9 mmDIG5_TMDS_STEREOSYNC_CTL_SEL 0 0x1dec 1 0 2 TMDS_STEREOSYNC_CTL_SEL 0 1 mmDIG5_TMDS_SYNC_CHAR_PATTERN_0_1 0 0x1ded 2 0 2 TMDS_SYNC_CHAR_PATTERN0 0 9 TMDS_SYNC_CHAR_PATTERN1 16 25 mmDIG5_TMDS_SYNC_CHAR_PATTERN_2_3 0 0x1dee 2 0 2 TMDS_SYNC_CHAR_PATTERN2 0 9 TMDS_SYNC_CHAR_PATTERN3 16 25 mmDIG5_TMDS_CTL_BITS 0 0x1df0 4 0 2 TMDS_CTL0 0 0 TMDS_CTL1 8 8 TMDS_CTL2 16 16 TMDS_CTL3 24 24 mmDIG5_TMDS_DCBALANCER_CONTROL 0 0x1df1 4 0 2 TMDS_DCBALANCER_EN 0 0 TMDS_DCBALANCER_TEST_EN 8 8 TMDS_DCBALANCER_TEST_IN 16 19 TMDS_DCBALANCER_FORCE 24 24 mmDIG5_TMDS_CTL0_1_GEN_CNTL 0 0x1df3 15 0 2 TMDS_CTL0_DATA_SEL 0 3 TMDS_CTL0_DATA_DELAY 4 6 TMDS_CTL0_DATA_INVERT 7 7 TMDS_CTL0_DATA_MODULATION 8 9 TMDS_CTL0_USE_FEEDBACK_PATH 10 10 TMDS_CTL0_FB_SYNC_CONT 11 11 TMDS_CTL0_PATTERN_OUT_EN 12 12 TMDS_CTL1_DATA_SEL 16 19 TMDS_CTL1_DATA_DELAY 20 22 TMDS_CTL1_DATA_INVERT 23 23 TMDS_CTL1_DATA_MODULATION 24 25 TMDS_CTL1_USE_FEEDBACK_PATH 26 26 TMDS_CTL1_FB_SYNC_CONT 27 27 TMDS_CTL1_PATTERN_OUT_EN 28 28 TMDS_2BIT_COUNTER_EN 31 31 mmDIG5_TMDS_CTL2_3_GEN_CNTL 0 0x1df4 14 0 2 TMDS_CTL2_DATA_SEL 0 3 TMDS_CTL2_DATA_DELAY 4 6 TMDS_CTL2_DATA_INVERT 7 7 TMDS_CTL2_DATA_MODULATION 8 9 TMDS_CTL2_USE_FEEDBACK_PATH 10 10 TMDS_CTL2_FB_SYNC_CONT 11 11 TMDS_CTL2_PATTERN_OUT_EN 12 12 TMDS_CTL3_DATA_SEL 16 19 TMDS_CTL3_DATA_DELAY 20 22 TMDS_CTL3_DATA_INVERT 23 23 TMDS_CTL3_DATA_MODULATION 24 25 TMDS_CTL3_USE_FEEDBACK_PATH 26 26 TMDS_CTL3_FB_SYNC_CONT 27 27 TMDS_CTL3_PATTERN_OUT_EN 28 28 mmDIG5_DIG_VERSION 0 0x1df6 1 0 2 DIG_TYPE 0 0 mmDIG5_DIG_LANE_ENABLE 0 0x1df7 5 0 2 DIG_LANE0EN 0 0 DIG_LANE1EN 1 1 DIG_LANE2EN 2 2 DIG_LANE3EN 3 3 DIG_CLK_EN 8 8 mmDIG5_AFMT_CNTL 0 0x1dfc 2 0 2 AFMT_AUDIO_CLOCK_EN 0 0 AFMT_AUDIO_CLOCK_ON 8 8 mmDP5_DP_LINK_CNTL 0 0x1e1e 3 0 2 DP_LINK_TRAINING_COMPLETE 4 4 DP_LINK_STATUS 8 8 DP_EMBEDDED_PANEL_MODE 17 17 mmDP5_DP_PIXEL_FORMAT 0 0x1e1f 4 0 2 DP_PIXEL_ENCODING 0 2 DP_DYN_RANGE 8 8 DP_YCBCR_RANGE 16 16 DP_COMPONENT_DEPTH 24 26 mmDP5_DP_MSA_COLORIMETRY 0 0x1e20 4 0 2 DP_MSA_MISC0_OVERRIDE 0 7 DP_MSA_MISC0_OVERRIDE_ENABLE 8 8 DP_MSA_MISC1_BIT7_OVERRIDE 9 9 DP_MSA_MISC1_BIT7_OVERRIDE_ENABLE 17 17 mmDP5_DP_CONFIG 0 0x1e21 1 0 2 DP_UDI_LANES 0 1 mmDP5_DP_VID_STREAM_CNTL 0 0x1e22 4 0 2 DP_VID_STREAM_ENABLE 0 0 DP_VID_STREAM_DIS_DEFER 8 9 DP_VID_STREAM_STATUS 16 16 DP_VID_STREAM_CHANGE_KEEPOUT 20 20 mmDP5_DP_STEER_FIFO 0 0x1e23 7 0 2 DP_STEER_FIFO_RESET 0 0 DP_STEER_OVERFLOW_FLAG 4 4 DP_STEER_OVERFLOW_INT 5 5 DP_STEER_OVERFLOW_ACK 6 6 DP_STEER_OVERFLOW_MASK 7 7 DP_TU_OVERFLOW_FLAG 8 8 DP_TU_OVERFLOW_ACK 12 12 mmDP5_DP_MSA_MISC 0 0x1e24 4 0 2 DP_MSA_MISC1 3 6 DP_MSA_MISC2 8 15 DP_MSA_MISC3 16 23 DP_MSA_MISC4 24 31 mmDP5_DP_VID_TIMING 0 0x1e26 5 0 2 DP_VID_TIMING_MODE 0 0 DP_VID_M_N_DOUBLE_BUFFER_MODE 4 4 DP_VID_M_N_GEN_EN 8 8 DP_VID_M_DOUBLE_VALUE_EN 9 9 DP_VID_N_DIV 24 31 mmDP5_DP_VID_N 0 0x1e27 1 0 2 DP_VID_N 0 23 mmDP5_DP_VID_M 0 0x1e28 1 0 2 DP_VID_M 0 23 mmDP5_DP_LINK_FRAMING_CNTL 0 0x1e29 3 0 2 DP_IDLE_BS_INTERVAL 0 17 DP_VBID_DISABLE 24 24 DP_VID_ENHANCED_FRAME_MODE 28 28 mmDP5_DP_HBR2_EYE_PATTERN 0 0x1e2a 1 0 2 DP_HBR2_EYE_PATTERN_ENABLE 0 0 mmDP5_DP_VID_MSA_VBID 0 0x1e2b 3 0 2 DP_VID_MSA_LOCATION 0 11 DP_VID_MSA_TOP_FIELD_MODE 16 16 DP_VID_VBID_FIELD_POL 24 24 mmDP5_DP_VID_INTERRUPT_CNTL 0 0x1e2c 3 0 2 DP_VID_STREAM_DISABLE_INT 0 0 DP_VID_STREAM_DISABLE_ACK 1 1 DP_VID_STREAM_DISABLE_MASK 2 2 mmDP5_DP_DPHY_CNTL 0 0x1e2d 6 0 2 DPHY_ATEST_SEL_LANE0 0 0 DPHY_ATEST_SEL_LANE1 1 1 DPHY_ATEST_SEL_LANE2 2 2 DPHY_ATEST_SEL_LANE3 3 3 DPHY_BYPASS 16 16 DPHY_SKEW_BYPASS 24 24 mmDP5_DP_DPHY_TRAINING_PATTERN_SEL 0 0x1e2e 1 0 2 DPHY_TRAINING_PATTERN_SEL 0 1 mmDP5_DP_DPHY_SYM0 0 0x1e2f 3 0 2 DPHY_SYM1 0 9 DPHY_SYM2 10 19 DPHY_SYM3 20 29 mmDP5_DP_DPHY_SYM1 0 0x1e30 3 0 2 DPHY_SYM4 0 9 DPHY_SYM5 10 19 DPHY_SYM6 20 29 mmDP5_DP_DPHY_SYM2 0 0x1e31 2 0 2 DPHY_SYM7 0 9 DPHY_SYM8 10 19 mmDP5_DP_DPHY_8B10B_CNTL 0 0x1e32 3 0 2 DPHY_8B10B_RESET 8 8 DPHY_8B10B_EXT_DISP 16 16 DPHY_8B10B_CUR_DISP 24 24 mmDP5_DP_DPHY_PRBS_CNTL 0 0x1e33 3 0 2 DPHY_PRBS_EN 0 0 DPHY_PRBS_SEL 4 5 DPHY_PRBS_SEED 8 30 mmDP5_DP_DPHY_SCRAM_CNTL 0 0x1e34 4 0 2 DPHY_SCRAMBLER_DIS 0 0 DPHY_SCRAMBLER_ADVANCE 4 4 DPHY_SCRAMBLER_BS_COUNT 8 17 DPHY_SCRAMBLER_KCODE 24 24 mmDP5_DP_DPHY_CRC_EN 0 0x1e35 3 0 2 DPHY_CRC_EN 0 0 DPHY_CRC_CONT_EN 4 4 DPHY_CRC_RESULT_VALID 8 8 mmDP5_DP_DPHY_CRC_CNTL 0 0x1e36 3 0 2 DPHY_CRC_FIELD 0 0 DPHY_CRC_SEL 4 5 DPHY_CRC_MASK 16 23 mmDP5_DP_DPHY_CRC_RESULT 0 0x1e37 4 0 2 DPHY_CRC_RESULT 0 7 DPHY_CRC_RESULT1 8 15 DPHY_CRC_RESULT2 16 23 DPHY_CRC_RESULT3 24 31 mmDP5_DP_DPHY_CRC_MST_CNTL 0 0x1e38 2 0 2 DPHY_CRC_MST_FIRST_SLOT 0 5 DPHY_CRC_MST_LAST_SLOT 8 13 mmDP5_DP_DPHY_CRC_MST_STATUS 0 0x1e39 3 0 2 DPHY_CRC_MST_PHASE_LOCK 0 0 DPHY_CRC_MST_PHASE_ERROR 8 8 DPHY_CRC_MST_PHASE_ERROR_ACK 16 16 mmDP5_DP_DPHY_FAST_TRAINING 0 0x1e3a 5 0 2 DPHY_RX_FAST_TRAINING_CAPABLE 0 0 DPHY_SW_FAST_TRAINING_START 1 1 DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN 2 2 DPHY_FAST_TRAINING_TP1_TIME 8 19 DPHY_FAST_TRAINING_TP2_TIME 20 31 mmDP5_DP_DPHY_FAST_TRAINING_STATUS 0 0x1e3b 4 0 2 DPHY_FAST_TRAINING_STATE 0 2 DPHY_FAST_TRAINING_COMPLETE_OCCURRED 4 4 DPHY_FAST_TRAINING_COMPLETE_MASK 8 8 DPHY_FAST_TRAINING_COMPLETE_ACK 12 12 mmDP5_DP_MSA_V_TIMING_OVERRIDE1 0 0x1e3c 2 0 2 DP_MSA_V_TIMING_OVERRIDE_EN 0 0 DP_MSA_V_TOTAL_OVERRIDE 4 17 mmDP5_DP_MSA_V_TIMING_OVERRIDE2 0 0x1e3d 2 0 2 DP_MSA_V_BLANK_START_OVERRIDE 0 13 DP_MSA_V_BLANK_END_OVERRIDE 16 29 mmDP5_DP_SEC_CNTL 0 0x1e41 11 0 2 DP_SEC_STREAM_ENABLE 0 0 DP_SEC_ASP_ENABLE 4 4 DP_SEC_ATP_ENABLE 8 8 DP_SEC_AIP_ENABLE 12 12 DP_SEC_ACM_ENABLE 16 16 DP_SEC_GSP0_ENABLE 20 20 DP_SEC_GSP1_ENABLE 21 21 DP_SEC_GSP2_ENABLE 22 22 DP_SEC_GSP3_ENABLE 23 23 DP_SEC_AVI_ENABLE 24 24 DP_SEC_MPG_ENABLE 28 28 mmDP5_DP_SEC_CNTL1 0 0x1e42 6 0 2 DP_SEC_ISRC_ENABLE 0 0 DP_SEC_GSP0_PRIORITY 4 4 DP_SEC_GSP0_SEND 5 5 DP_SEC_GSP0_SEND_PENDING 6 6 DP_SEC_GSP0_SEND_DEADLINE_MISSED 7 7 DP_SEC_GSP0_LINE_NUM 16 31 mmDP5_DP_SEC_FRAMING1 0 0x1e43 2 0 2 DP_SEC_FRAME_START_LOCATION 0 11 DP_SEC_VBLANK_TRANSMIT_WIDTH 16 31 mmDP5_DP_SEC_FRAMING2 0 0x1e44 2 0 2 DP_SEC_START_POSITION 0 15 DP_SEC_HBLANK_TRANSMIT_WIDTH 16 31 mmDP5_DP_SEC_FRAMING3 0 0x1e45 2 0 2 DP_SEC_IDLE_FRAME_SIZE 0 13 DP_SEC_IDLE_TRANSMIT_WIDTH 16 31 mmDP5_DP_SEC_FRAMING4 0 0x1e46 4 0 2 DP_SEC_COLLISION_STATUS 20 20 DP_SEC_COLLISION_ACK 24 24 DP_SEC_AUDIO_MUTE 28 28 DP_SEC_AUDIO_MUTE_STATUS 29 29 mmDP5_DP_SEC_AUD_N 0 0x1e47 1 0 2 DP_SEC_AUD_N 0 23 mmDP5_DP_SEC_AUD_N_READBACK 0 0x1e48 1 0 2 DP_SEC_AUD_N_READBACK 0 23 mmDP5_DP_SEC_AUD_M 0 0x1e49 1 0 2 DP_SEC_AUD_M 0 23 mmDP5_DP_SEC_AUD_M_READBACK 0 0x1e4a 1 0 2 DP_SEC_AUD_M_READBACK 0 23 mmDP5_DP_SEC_TIMESTAMP 0 0x1e4b 1 0 2 DP_SEC_TIMESTAMP_MODE 0 0 mmDP5_DP_SEC_PACKET_CNTL 0 0x1e4c 4 0 2 DP_SEC_ASP_CODING_TYPE 1 3 DP_SEC_ASP_PRIORITY 4 4 DP_SEC_VERSION 8 13 DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE 16 16 mmDP5_DP_MSE_RATE_CNTL 0 0x1e4d 2 0 2 DP_MSE_RATE_Y 0 25 DP_MSE_RATE_X 26 31 mmDP5_DP_MSE_RATE_UPDATE 0 0x1e4f 1 0 2 DP_MSE_RATE_UPDATE_PENDING 0 0 mmDP5_DP_MSE_SAT0 0 0x1e50 4 0 2 DP_MSE_SAT_SRC0 0 2 DP_MSE_SAT_SLOT_COUNT0 8 13 DP_MSE_SAT_SRC1 16 18 DP_MSE_SAT_SLOT_COUNT1 24 29 mmDP5_DP_MSE_SAT1 0 0x1e51 4 0 2 DP_MSE_SAT_SRC2 0 2 DP_MSE_SAT_SLOT_COUNT2 8 13 DP_MSE_SAT_SRC3 16 18 DP_MSE_SAT_SLOT_COUNT3 24 29 mmDP5_DP_MSE_SAT2 0 0x1e52 4 0 2 DP_MSE_SAT_SRC4 0 2 DP_MSE_SAT_SLOT_COUNT4 8 13 DP_MSE_SAT_SRC5 16 18 DP_MSE_SAT_SLOT_COUNT5 24 29 mmDP5_DP_MSE_SAT_UPDATE 0 0x1e53 2 0 2 DP_MSE_SAT_UPDATE 0 1 DP_MSE_16_MTP_KEEPOUT 8 8 mmDP5_DP_MSE_LINK_TIMING 0 0x1e54 2 0 2 DP_MSE_LINK_FRAME 0 9 DP_MSE_LINK_LINE 16 17 mmDP5_DP_MSE_MISC_CNTL 0 0x1e55 3 0 2 DP_MSE_BLANK_CODE 0 0 DP_MSE_TIMESTAMP_MODE 4 4 DP_MSE_ZERO_ENCODER 8 8 mmDP5_DP_DPHY_BS_SR_SWAP_CNTL 0 0x1e5a 3 0 2 DPHY_LOAD_BS_COUNT 0 9 DPHY_BS_SR_SWAP_DONE 15 15 DPHY_LOAD_BS_COUNT_START 16 16 mmDP5_DP_DPHY_HBR2_PATTERN_CONTROL 0 0x1e5b 1 0 2 DP_DPHY_HBR2_PATTERN_CONTROL 0 2 mmDP5_DP_MSE_SAT0_STATUS 0 0x1e5d 4 0 2 DP_MSE_SAT_SRC0_STATUS 0 2 DP_MSE_SAT_SLOT_COUNT0_STATUS 8 13 DP_MSE_SAT_SRC1_STATUS 16 18 DP_MSE_SAT_SLOT_COUNT1_STATUS 24 29 mmDP5_DP_MSE_SAT1_STATUS 0 0x1e5e 4 0 2 DP_MSE_SAT_SRC2_STATUS 0 2 DP_MSE_SAT_SLOT_COUNT2_STATUS 8 13 DP_MSE_SAT_SRC3_STATUS 16 18 DP_MSE_SAT_SLOT_COUNT3_STATUS 24 29 mmDP5_DP_MSE_SAT2_STATUS 0 0x1e5f 4 0 2 DP_MSE_SAT_SRC4_STATUS 0 2 DP_MSE_SAT_SLOT_COUNT4_STATUS 8 13 DP_MSE_SAT_SRC5_STATUS 16 18 DP_MSE_SAT_SLOT_COUNT5_STATUS 24 29 mmDIG6_DIG_FE_CNTL 0 0x1e7e 7 0 2 DIG_SOURCE_SELECT 0 2 DIG_STEREOSYNC_SELECT 4 6 DIG_STEREOSYNC_GATE_EN 8 8 DIG_START 10 10 DIG_SYMCLK_FE_ON 24 24 TMDS_PIXEL_ENCODING 28 28 TMDS_COLOR_FORMAT 30 31 mmDIG6_DIG_OUTPUT_CRC_CNTL 0 0x1e7f 3 0 2 DIG_OUTPUT_CRC_EN 0 0 DIG_OUTPUT_CRC_LINK_SEL 4 4 DIG_OUTPUT_CRC_DATA_SEL 8 9 mmDIG6_DIG_OUTPUT_CRC_RESULT 0 0x1e80 1 0 2 DIG_OUTPUT_CRC_RESULT 0 29 mmDIG6_DIG_CLOCK_PATTERN 0 0x1e81 1 0 2 DIG_CLOCK_PATTERN 0 9 mmDIG6_DIG_TEST_PATTERN 0 0x1e82 6 0 2 DIG_TEST_PATTERN_OUT_EN 0 0 DIG_HALF_CLOCK_PATTERN_SEL 1 1 DIG_RANDOM_PATTERN_OUT_EN 4 4 DIG_RANDOM_PATTERN_RESET 5 5 DIG_TEST_PATTERN_EXTERNAL_RESET_EN 6 6 DIG_STATIC_TEST_PATTERN 16 25 mmDIG6_DIG_RANDOM_PATTERN_SEED 0 0x1e83 2 0 2 DIG_RANDOM_PATTERN_SEED 0 23 DIG_RAN_PAT_DURING_DE_ONLY 24 24 mmDIG6_DIG_FIFO_STATUS 0 0x1e84 11 0 2 DIG_FIFO_LEVEL_ERROR 0 0 DIG_FIFO_USE_OVERWRITE_LEVEL 1 1 DIG_FIFO_OVERWRITE_LEVEL 2 7 DIG_FIFO_ERROR_ACK 8 8 DIG_FIFO_CAL_AVERAGE_LEVEL 10 15 DIG_FIFO_MAXIMUM_LEVEL 16 20 DIG_FIFO_MINIMUM_LEVEL 22 25 DIG_FIFO_READ_CLOCK_SRC 26 26 DIG_FIFO_CALIBRATED 29 29 DIG_FIFO_FORCE_RECAL_AVERAGE 30 30 DIG_FIFO_FORCE_RECOMP_MINMAX 31 31 mmDIG6_HDMI_CONTROL 0 0x1e87 9 0 2 HDMI_KEEPOUT_MODE 0 0 HDMI_DATA_SCRAMBLE_EN 1 1 HDMI_CLOCK_CHANNEL_RATE 2 2 HDMI_NO_EXTRA_NULL_PACKET_FILLED 3 3 HDMI_PACKET_GEN_VERSION 4 4 HDMI_ERROR_ACK 8 8 HDMI_ERROR_MASK 9 9 HDMI_DEEP_COLOR_ENABLE 24 24 HDMI_DEEP_COLOR_DEPTH 28 29 mmDIG6_HDMI_STATUS 0 0x1e88 4 0 2 HDMI_ACTIVE_AVMUTE 0 0 HDMI_AUDIO_PACKET_ERROR 16 16 HDMI_VBI_PACKET_ERROR 20 20 HDMI_ERROR_INT 27 27 mmDIG6_HDMI_AUDIO_PACKET_CONTROL 0 0x1e89 2 0 2 HDMI_AUDIO_DELAY_EN 4 5 HDMI_AUDIO_PACKETS_PER_LINE 16 20 mmDIG6_HDMI_ACR_PACKET_CONTROL 0 0x1e8a 7 0 2 HDMI_ACR_SEND 0 0 HDMI_ACR_CONT 1 1 HDMI_ACR_SELECT 4 5 HDMI_ACR_SOURCE 8 8 HDMI_ACR_AUTO_SEND 12 12 HDMI_ACR_N_MULTIPLE 16 18 HDMI_ACR_AUDIO_PRIORITY 31 31 mmDIG6_HDMI_VBI_PACKET_CONTROL 0 0x1e8b 6 0 2 HDMI_NULL_SEND 0 0 HDMI_GC_SEND 4 4 HDMI_GC_CONT 5 5 HDMI_ISRC_SEND 8 8 HDMI_ISRC_CONT 9 9 HDMI_ISRC_LINE 16 21 mmDIG6_HDMI_INFOFRAME_CONTROL0 0 0x1e8c 6 0 2 HDMI_AVI_INFO_SEND 0 0 HDMI_AVI_INFO_CONT 1 1 HDMI_AUDIO_INFO_SEND 4 4 HDMI_AUDIO_INFO_CONT 5 5 HDMI_MPEG_INFO_SEND 8 8 HDMI_MPEG_INFO_CONT 9 9 mmDIG6_HDMI_INFOFRAME_CONTROL1 0 0x1e8d 3 0 2 HDMI_AVI_INFO_LINE 0 5 HDMI_AUDIO_INFO_LINE 8 13 HDMI_MPEG_INFO_LINE 16 21 mmDIG6_HDMI_GENERIC_PACKET_CONTROL0 0 0x1e8e 6 0 2 HDMI_GENERIC0_SEND 0 0 HDMI_GENERIC0_CONT 1 1 HDMI_GENERIC1_SEND 4 4 HDMI_GENERIC1_CONT 5 5 HDMI_GENERIC0_LINE 16 21 HDMI_GENERIC1_LINE 24 29 mmDIG6_AFMT_INTERRUPT_STATUS 0 0x1e8f 0 0 2 mmDIG6_HDMI_GC 0 0x1e91 5 0 2 HDMI_GC_AVMUTE 0 0 HDMI_GC_AVMUTE_CONT 2 2 HDMI_DEFAULT_PHASE 4 4 HDMI_PACKING_PHASE 8 11 HDMI_PACKING_PHASE_OVERRIDE 12 12 mmDIG6_AFMT_AUDIO_PACKET_CONTROL2 0 0x1e92 6 0 2 AFMT_AUDIO_LAYOUT_OVRD 0 0 AFMT_AUDIO_LAYOUT_SELECT 1 1 AFMT_AUDIO_CHANNEL_ENABLE 8 15 AFMT_DP_AUDIO_STREAM_ID 16 23 AFMT_HBR_ENABLE_OVRD 24 24 AFMT_60958_OSF_OVRD 28 28 mmDIG6_AFMT_ISRC1_0 0 0x1e93 3 0 2 AFMT_ISRC_STATUS 0 2 AFMT_ISRC_CONTINUE 6 6 AFMT_ISRC_VALID 7 7 mmDIG6_AFMT_ISRC1_1 0 0x1e94 4 0 2 AFMT_UPC_EAN_ISRC0 0 7 AFMT_UPC_EAN_ISRC1 8 15 AFMT_UPC_EAN_ISRC2 16 23 AFMT_UPC_EAN_ISRC3 24 31 mmDIG6_AFMT_ISRC1_2 0 0x1e95 4 0 2 AFMT_UPC_EAN_ISRC4 0 7 AFMT_UPC_EAN_ISRC5 8 15 AFMT_UPC_EAN_ISRC6 16 23 AFMT_UPC_EAN_ISRC7 24 31 mmDIG6_AFMT_ISRC1_3 0 0x1e96 4 0 2 AFMT_UPC_EAN_ISRC8 0 7 AFMT_UPC_EAN_ISRC9 8 15 AFMT_UPC_EAN_ISRC10 16 23 AFMT_UPC_EAN_ISRC11 24 31 mmDIG6_AFMT_ISRC1_4 0 0x1e97 4 0 2 AFMT_UPC_EAN_ISRC12 0 7 AFMT_UPC_EAN_ISRC13 8 15 AFMT_UPC_EAN_ISRC14 16 23 AFMT_UPC_EAN_ISRC15 24 31 mmDIG6_AFMT_ISRC2_0 0 0x1e98 4 0 2 AFMT_UPC_EAN_ISRC16 0 7 AFMT_UPC_EAN_ISRC17 8 15 AFMT_UPC_EAN_ISRC18 16 23 AFMT_UPC_EAN_ISRC19 24 31 mmDIG6_AFMT_ISRC2_1 0 0x1e99 4 0 2 AFMT_UPC_EAN_ISRC20 0 7 AFMT_UPC_EAN_ISRC21 8 15 AFMT_UPC_EAN_ISRC22 16 23 AFMT_UPC_EAN_ISRC23 24 31 mmDIG6_AFMT_ISRC2_2 0 0x1e9a 4 0 2 AFMT_UPC_EAN_ISRC24 0 7 AFMT_UPC_EAN_ISRC25 8 15 AFMT_UPC_EAN_ISRC26 16 23 AFMT_UPC_EAN_ISRC27 24 31 mmDIG6_AFMT_ISRC2_3 0 0x1e9b 4 0 2 AFMT_UPC_EAN_ISRC28 0 7 AFMT_UPC_EAN_ISRC29 8 15 AFMT_UPC_EAN_ISRC30 16 23 AFMT_UPC_EAN_ISRC31 24 31 mmDIG6_AFMT_AVI_INFO0 0 0x1e9c 12 0 2 AFMT_AVI_INFO_CHECKSUM 0 7 AFMT_AVI_INFO_S 8 9 AFMT_AVI_INFO_B 10 11 AFMT_AVI_INFO_A 12 12 AFMT_AVI_INFO_Y 13 15 AFMT_AVI_INFO_R 16 19 AFMT_AVI_INFO_M 20 21 AFMT_AVI_INFO_C 22 23 AFMT_AVI_INFO_SC 24 25 AFMT_AVI_INFO_Q 26 27 AFMT_AVI_INFO_EC 28 30 AFMT_AVI_INFO_ITC 31 31 mmDIG6_AFMT_AVI_INFO1 0 0x1e9d 5 0 2 AFMT_AVI_INFO_VIC 0 7 AFMT_AVI_INFO_PR 8 11 AFMT_AVI_INFO_CN 12 13 AFMT_AVI_INFO_YQ 14 15 AFMT_AVI_INFO_TOP 16 31 mmDIG6_AFMT_AVI_INFO2 0 0x1e9e 2 0 2 AFMT_AVI_INFO_BOTTOM 0 15 AFMT_AVI_INFO_LEFT 16 31 mmDIG6_AFMT_AVI_INFO3 0 0x1e9f 2 0 2 AFMT_AVI_INFO_RIGHT 0 15 AFMT_AVI_INFO_VERSION 24 31 mmDIG6_AFMT_MPEG_INFO0 0 0x1ea0 4 0 2 AFMT_MPEG_INFO_CHECKSUM 0 7 AFMT_MPEG_INFO_MB0 8 15 AFMT_MPEG_INFO_MB1 16 23 AFMT_MPEG_INFO_MB2 24 31 mmDIG6_AFMT_MPEG_INFO1 0 0x1ea1 3 0 2 AFMT_MPEG_INFO_MB3 0 7 AFMT_MPEG_INFO_MF 8 9 AFMT_MPEG_INFO_FR 12 12 mmDIG6_AFMT_GENERIC_HDR 0 0x1ea2 4 0 2 AFMT_GENERIC_HB0 0 7 AFMT_GENERIC_HB1 8 15 AFMT_GENERIC_HB2 16 23 AFMT_GENERIC_HB3 24 31 mmDIG6_AFMT_GENERIC_0 0 0x1ea3 4 0 2 AFMT_GENERIC_BYTE0 0 7 AFMT_GENERIC_BYTE1 8 15 AFMT_GENERIC_BYTE2 16 23 AFMT_GENERIC_BYTE3 24 31 mmDIG6_AFMT_GENERIC_1 0 0x1ea4 4 0 2 AFMT_GENERIC_BYTE4 0 7 AFMT_GENERIC_BYTE5 8 15 AFMT_GENERIC_BYTE6 16 23 AFMT_GENERIC_BYTE7 24 31 mmDIG6_AFMT_GENERIC_2 0 0x1ea5 4 0 2 AFMT_GENERIC_BYTE8 0 7 AFMT_GENERIC_BYTE9 8 15 AFMT_GENERIC_BYTE10 16 23 AFMT_GENERIC_BYTE11 24 31 mmDIG6_AFMT_GENERIC_3 0 0x1ea6 4 0 2 AFMT_GENERIC_BYTE12 0 7 AFMT_GENERIC_BYTE13 8 15 AFMT_GENERIC_BYTE14 16 23 AFMT_GENERIC_BYTE15 24 31 mmDIG6_AFMT_GENERIC_4 0 0x1ea7 4 0 2 AFMT_GENERIC_BYTE16 0 7 AFMT_GENERIC_BYTE17 8 15 AFMT_GENERIC_BYTE18 16 23 AFMT_GENERIC_BYTE19 24 31 mmDIG6_AFMT_GENERIC_5 0 0x1ea8 4 0 2 AFMT_GENERIC_BYTE20 0 7 AFMT_GENERIC_BYTE21 8 15 AFMT_GENERIC_BYTE22 16 23 AFMT_GENERIC_BYTE23 24 31 mmDIG6_AFMT_GENERIC_6 0 0x1ea9 4 0 2 AFMT_GENERIC_BYTE24 0 7 AFMT_GENERIC_BYTE25 8 15 AFMT_GENERIC_BYTE26 16 23 AFMT_GENERIC_BYTE27 24 31 mmDIG6_AFMT_GENERIC_7 0 0x1eaa 4 0 2 AFMT_GENERIC_BYTE28 0 7 AFMT_GENERIC_BYTE29 8 15 AFMT_GENERIC_BYTE30 16 23 AFMT_GENERIC_BYTE31 24 31 mmDIG6_HDMI_GENERIC_PACKET_CONTROL1 0 0x1eab 6 0 2 HDMI_GENERIC2_SEND 0 0 HDMI_GENERIC2_CONT 1 1 HDMI_GENERIC3_SEND 4 4 HDMI_GENERIC3_CONT 5 5 HDMI_GENERIC2_LINE 16 21 HDMI_GENERIC3_LINE 24 29 mmDIG6_HDMI_ACR_32_0 0 0x1eac 1 0 2 HDMI_ACR_CTS_32 12 31 mmDIG6_HDMI_ACR_32_1 0 0x1ead 1 0 2 HDMI_ACR_N_32 0 19 mmDIG6_HDMI_ACR_44_0 0 0x1eae 1 0 2 HDMI_ACR_CTS_44 12 31 mmDIG6_HDMI_ACR_44_1 0 0x1eaf 1 0 2 HDMI_ACR_N_44 0 19 mmDIG6_HDMI_ACR_48_0 0 0x1eb0 1 0 2 HDMI_ACR_CTS_48 12 31 mmDIG6_HDMI_ACR_48_1 0 0x1eb1 1 0 2 HDMI_ACR_N_48 0 19 mmDIG6_HDMI_ACR_STATUS_0 0 0x1eb2 1 0 2 HDMI_ACR_CTS 12 31 mmDIG6_HDMI_ACR_STATUS_1 0 0x1eb3 1 0 2 HDMI_ACR_N 0 19 mmDIG6_AFMT_AUDIO_INFO0 0 0x1eb4 5 0 2 AFMT_AUDIO_INFO_CHECKSUM 0 7 AFMT_AUDIO_INFO_CC 8 10 AFMT_AUDIO_INFO_CT 11 14 AFMT_AUDIO_INFO_CHECKSUM_OFFSET 16 23 AFMT_AUDIO_INFO_CXT 24 28 mmDIG6_AFMT_AUDIO_INFO1 0 0x1eb5 4 0 2 AFMT_AUDIO_INFO_CA 0 7 AFMT_AUDIO_INFO_LSV 11 14 AFMT_AUDIO_INFO_DM_INH 15 15 AFMT_AUDIO_INFO_LFEPBL 16 17 mmDIG6_AFMT_60958_0 0 0x1eb6 10 0 2 AFMT_60958_CS_A 0 0 AFMT_60958_CS_B 1 1 AFMT_60958_CS_C 2 2 AFMT_60958_CS_D 3 5 AFMT_60958_CS_MODE 6 7 AFMT_60958_CS_CATEGORY_CODE 8 15 AFMT_60958_CS_SOURCE_NUMBER 16 19 AFMT_60958_CS_CHANNEL_NUMBER_L 20 23 AFMT_60958_CS_SAMPLING_FREQUENCY 24 27 AFMT_60958_CS_CLOCK_ACCURACY 28 29 mmDIG6_AFMT_60958_1 0 0x1eb7 5 0 2 AFMT_60958_CS_WORD_LENGTH 0 3 AFMT_60958_CS_ORIGINAL_SAMPLING_FREQUENCY 4 7 AFMT_60958_VALID_L 16 16 AFMT_60958_VALID_R 18 18 AFMT_60958_CS_CHANNEL_NUMBER_R 20 23 mmDIG6_AFMT_AUDIO_CRC_CONTROL 0 0x1eb8 5 0 2 AFMT_AUDIO_CRC_EN 0 0 AFMT_AUDIO_CRC_CONT 4 4 AFMT_AUDIO_CRC_SOURCE 8 8 AFMT_AUDIO_CRC_CH_SEL 12 15 AFMT_AUDIO_CRC_COUNT 16 31 mmDIG6_AFMT_RAMP_CONTROL0 0 0x1eb9 2 0 2 AFMT_RAMP_MAX_COUNT 0 23 AFMT_RAMP_DATA_SIGN 31 31 mmDIG6_AFMT_RAMP_CONTROL1 0 0x1eba 2 0 2 AFMT_RAMP_MIN_COUNT 0 23 AFMT_AUDIO_TEST_CH_DISABLE 24 31 mmDIG6_AFMT_RAMP_CONTROL2 0 0x1ebb 1 0 2 AFMT_RAMP_INC_COUNT 0 23 mmDIG6_AFMT_RAMP_CONTROL3 0 0x1ebc 1 0 2 AFMT_RAMP_DEC_COUNT 0 23 mmDIG6_AFMT_60958_2 0 0x1ebd 6 0 2 AFMT_60958_CS_CHANNEL_NUMBER_2 0 3 AFMT_60958_CS_CHANNEL_NUMBER_3 4 7 AFMT_60958_CS_CHANNEL_NUMBER_4 8 11 AFMT_60958_CS_CHANNEL_NUMBER_5 12 15 AFMT_60958_CS_CHANNEL_NUMBER_6 16 19 AFMT_60958_CS_CHANNEL_NUMBER_7 20 23 mmDIG6_AFMT_AUDIO_CRC_RESULT 0 0x1ebe 2 0 2 AFMT_AUDIO_CRC_DONE 0 0 AFMT_AUDIO_CRC 8 31 mmDIG6_AFMT_STATUS 0 0x1ebf 4 0 2 AFMT_AUDIO_ENABLE 4 4 AFMT_AZ_HBR_ENABLE 8 8 AFMT_AUDIO_FIFO_OVERFLOW 24 24 AFMT_AZ_AUDIO_ENABLE_CHG 30 30 mmDIG6_AFMT_AUDIO_PACKET_CONTROL 0 0x1ec0 8 0 2 AFMT_AUDIO_SAMPLE_SEND 0 0 AFMT_RESET_FIFO_WHEN_AUDIO_DIS 11 11 AFMT_AUDIO_TEST_EN 12 12 AFMT_AUDIO_TEST_MODE 14 14 AFMT_AUDIO_FIFO_OVERFLOW_ACK 23 23 AFMT_AUDIO_CHANNEL_SWAP 24 24 AFMT_60958_CS_UPDATE 26 26 AFMT_AZ_AUDIO_ENABLE_CHG_ACK 30 30 mmDIG6_AFMT_VBI_PACKET_CONTROL 0 0x1ec1 3 0 2 AFMT_GENERIC0_UPDATE 2 2 AFMT_GENERIC2_UPDATE 3 3 AFMT_GENERIC_INDEX 30 31 mmDIG6_AFMT_INFOFRAME_CONTROL0 0 0x1ec2 3 0 2 AFMT_AUDIO_INFO_SOURCE 6 6 AFMT_AUDIO_INFO_UPDATE 7 7 AFMT_MPEG_INFO_UPDATE 10 10 mmDIG6_AFMT_AUDIO_SRC_CONTROL 0 0x1ec3 1 0 2 AFMT_AUDIO_SRC_SELECT 0 2 mmDIG6_DIG_BE_CNTL 0 0x1ec5 5 0 2 DIG_DUAL_LINK_ENABLE 0 0 DIG_SWAP 1 1 DIG_FE_SOURCE_SELECT 8 14 DIG_MODE 16 18 DIG_HPD_SELECT 28 30 mmDIG6_DIG_BE_EN_CNTL 0 0x1ec6 2 0 2 DIG_ENABLE 0 0 DIG_SYMCLK_BE_ON 8 8 mmDIG6_TMDS_CNTL 0 0x1ee9 1 0 2 TMDS_SYNC_PHASE 0 0 mmDIG6_TMDS_CONTROL_CHAR 0 0x1eea 4 0 2 TMDS_CONTROL_CHAR0_OUT_EN 0 0 TMDS_CONTROL_CHAR1_OUT_EN 1 1 TMDS_CONTROL_CHAR2_OUT_EN 2 2 TMDS_CONTROL_CHAR3_OUT_EN 3 3 mmDIG6_TMDS_CONTROL0_FEEDBACK 0 0x1eeb 2 0 2 TMDS_CONTROL0_FEEDBACK_SELECT 0 1 TMDS_CONTROL0_FEEDBACK_DELAY 8 9 mmDIG6_TMDS_STEREOSYNC_CTL_SEL 0 0x1eec 1 0 2 TMDS_STEREOSYNC_CTL_SEL 0 1 mmDIG6_TMDS_SYNC_CHAR_PATTERN_0_1 0 0x1eed 2 0 2 TMDS_SYNC_CHAR_PATTERN0 0 9 TMDS_SYNC_CHAR_PATTERN1 16 25 mmDIG6_TMDS_SYNC_CHAR_PATTERN_2_3 0 0x1eee 2 0 2 TMDS_SYNC_CHAR_PATTERN2 0 9 TMDS_SYNC_CHAR_PATTERN3 16 25 mmDIG6_TMDS_CTL_BITS 0 0x1ef0 4 0 2 TMDS_CTL0 0 0 TMDS_CTL1 8 8 TMDS_CTL2 16 16 TMDS_CTL3 24 24 mmDIG6_TMDS_DCBALANCER_CONTROL 0 0x1ef1 4 0 2 TMDS_DCBALANCER_EN 0 0 TMDS_DCBALANCER_TEST_EN 8 8 TMDS_DCBALANCER_TEST_IN 16 19 TMDS_DCBALANCER_FORCE 24 24 mmDIG6_TMDS_CTL0_1_GEN_CNTL 0 0x1ef3 15 0 2 TMDS_CTL0_DATA_SEL 0 3 TMDS_CTL0_DATA_DELAY 4 6 TMDS_CTL0_DATA_INVERT 7 7 TMDS_CTL0_DATA_MODULATION 8 9 TMDS_CTL0_USE_FEEDBACK_PATH 10 10 TMDS_CTL0_FB_SYNC_CONT 11 11 TMDS_CTL0_PATTERN_OUT_EN 12 12 TMDS_CTL1_DATA_SEL 16 19 TMDS_CTL1_DATA_DELAY 20 22 TMDS_CTL1_DATA_INVERT 23 23 TMDS_CTL1_DATA_MODULATION 24 25 TMDS_CTL1_USE_FEEDBACK_PATH 26 26 TMDS_CTL1_FB_SYNC_CONT 27 27 TMDS_CTL1_PATTERN_OUT_EN 28 28 TMDS_2BIT_COUNTER_EN 31 31 mmDIG6_TMDS_CTL2_3_GEN_CNTL 0 0x1ef4 14 0 2 TMDS_CTL2_DATA_SEL 0 3 TMDS_CTL2_DATA_DELAY 4 6 TMDS_CTL2_DATA_INVERT 7 7 TMDS_CTL2_DATA_MODULATION 8 9 TMDS_CTL2_USE_FEEDBACK_PATH 10 10 TMDS_CTL2_FB_SYNC_CONT 11 11 TMDS_CTL2_PATTERN_OUT_EN 12 12 TMDS_CTL3_DATA_SEL 16 19 TMDS_CTL3_DATA_DELAY 20 22 TMDS_CTL3_DATA_INVERT 23 23 TMDS_CTL3_DATA_MODULATION 24 25 TMDS_CTL3_USE_FEEDBACK_PATH 26 26 TMDS_CTL3_FB_SYNC_CONT 27 27 TMDS_CTL3_PATTERN_OUT_EN 28 28 mmDIG6_DIG_VERSION 0 0x1ef6 1 0 2 DIG_TYPE 0 0 mmDIG6_DIG_LANE_ENABLE 0 0x1ef7 5 0 2 DIG_LANE0EN 0 0 DIG_LANE1EN 1 1 DIG_LANE2EN 2 2 DIG_LANE3EN 3 3 DIG_CLK_EN 8 8 mmDIG6_AFMT_CNTL 0 0x1efc 2 0 2 AFMT_AUDIO_CLOCK_EN 0 0 AFMT_AUDIO_CLOCK_ON 8 8 mmDP6_DP_LINK_CNTL 0 0x1f1e 3 0 2 DP_LINK_TRAINING_COMPLETE 4 4 DP_LINK_STATUS 8 8 DP_EMBEDDED_PANEL_MODE 17 17 mmDP6_DP_PIXEL_FORMAT 0 0x1f1f 4 0 2 DP_PIXEL_ENCODING 0 2 DP_DYN_RANGE 8 8 DP_YCBCR_RANGE 16 16 DP_COMPONENT_DEPTH 24 26 mmDP6_DP_MSA_COLORIMETRY 0 0x1f20 4 0 2 DP_MSA_MISC0_OVERRIDE 0 7 DP_MSA_MISC0_OVERRIDE_ENABLE 8 8 DP_MSA_MISC1_BIT7_OVERRIDE 9 9 DP_MSA_MISC1_BIT7_OVERRIDE_ENABLE 17 17 mmDP6_DP_CONFIG 0 0x1f21 1 0 2 DP_UDI_LANES 0 1 mmDP6_DP_VID_STREAM_CNTL 0 0x1f22 4 0 2 DP_VID_STREAM_ENABLE 0 0 DP_VID_STREAM_DIS_DEFER 8 9 DP_VID_STREAM_STATUS 16 16 DP_VID_STREAM_CHANGE_KEEPOUT 20 20 mmDP6_DP_STEER_FIFO 0 0x1f23 7 0 2 DP_STEER_FIFO_RESET 0 0 DP_STEER_OVERFLOW_FLAG 4 4 DP_STEER_OVERFLOW_INT 5 5 DP_STEER_OVERFLOW_ACK 6 6 DP_STEER_OVERFLOW_MASK 7 7 DP_TU_OVERFLOW_FLAG 8 8 DP_TU_OVERFLOW_ACK 12 12 mmDP6_DP_MSA_MISC 0 0x1f24 4 0 2 DP_MSA_MISC1 3 6 DP_MSA_MISC2 8 15 DP_MSA_MISC3 16 23 DP_MSA_MISC4 24 31 mmDP6_DP_VID_TIMING 0 0x1f26 5 0 2 DP_VID_TIMING_MODE 0 0 DP_VID_M_N_DOUBLE_BUFFER_MODE 4 4 DP_VID_M_N_GEN_EN 8 8 DP_VID_M_DOUBLE_VALUE_EN 9 9 DP_VID_N_DIV 24 31 mmDP6_DP_VID_N 0 0x1f27 1 0 2 DP_VID_N 0 23 mmDP6_DP_VID_M 0 0x1f28 1 0 2 DP_VID_M 0 23 mmDP6_DP_LINK_FRAMING_CNTL 0 0x1f29 3 0 2 DP_IDLE_BS_INTERVAL 0 17 DP_VBID_DISABLE 24 24 DP_VID_ENHANCED_FRAME_MODE 28 28 mmDP6_DP_HBR2_EYE_PATTERN 0 0x1f2a 1 0 2 DP_HBR2_EYE_PATTERN_ENABLE 0 0 mmDP6_DP_VID_MSA_VBID 0 0x1f2b 3 0 2 DP_VID_MSA_LOCATION 0 11 DP_VID_MSA_TOP_FIELD_MODE 16 16 DP_VID_VBID_FIELD_POL 24 24 mmDP6_DP_VID_INTERRUPT_CNTL 0 0x1f2c 3 0 2 DP_VID_STREAM_DISABLE_INT 0 0 DP_VID_STREAM_DISABLE_ACK 1 1 DP_VID_STREAM_DISABLE_MASK 2 2 mmDP6_DP_DPHY_CNTL 0 0x1f2d 6 0 2 DPHY_ATEST_SEL_LANE0 0 0 DPHY_ATEST_SEL_LANE1 1 1 DPHY_ATEST_SEL_LANE2 2 2 DPHY_ATEST_SEL_LANE3 3 3 DPHY_BYPASS 16 16 DPHY_SKEW_BYPASS 24 24 mmDP6_DP_DPHY_TRAINING_PATTERN_SEL 0 0x1f2e 1 0 2 DPHY_TRAINING_PATTERN_SEL 0 1 mmDP6_DP_DPHY_SYM0 0 0x1f2f 3 0 2 DPHY_SYM1 0 9 DPHY_SYM2 10 19 DPHY_SYM3 20 29 mmDP6_DP_DPHY_SYM1 0 0x1f30 3 0 2 DPHY_SYM4 0 9 DPHY_SYM5 10 19 DPHY_SYM6 20 29 mmDP6_DP_DPHY_SYM2 0 0x1f31 2 0 2 DPHY_SYM7 0 9 DPHY_SYM8 10 19 mmDP6_DP_DPHY_8B10B_CNTL 0 0x1f32 3 0 2 DPHY_8B10B_RESET 8 8 DPHY_8B10B_EXT_DISP 16 16 DPHY_8B10B_CUR_DISP 24 24 mmDP6_DP_DPHY_PRBS_CNTL 0 0x1f33 3 0 2 DPHY_PRBS_EN 0 0 DPHY_PRBS_SEL 4 5 DPHY_PRBS_SEED 8 30 mmDP6_DP_DPHY_SCRAM_CNTL 0 0x1f34 4 0 2 DPHY_SCRAMBLER_DIS 0 0 DPHY_SCRAMBLER_ADVANCE 4 4 DPHY_SCRAMBLER_BS_COUNT 8 17 DPHY_SCRAMBLER_KCODE 24 24 mmDP6_DP_DPHY_CRC_EN 0 0x1f35 3 0 2 DPHY_CRC_EN 0 0 DPHY_CRC_CONT_EN 4 4 DPHY_CRC_RESULT_VALID 8 8 mmDP6_DP_DPHY_CRC_CNTL 0 0x1f36 3 0 2 DPHY_CRC_FIELD 0 0 DPHY_CRC_SEL 4 5 DPHY_CRC_MASK 16 23 mmDP6_DP_DPHY_CRC_RESULT 0 0x1f37 4 0 2 DPHY_CRC_RESULT 0 7 DPHY_CRC_RESULT1 8 15 DPHY_CRC_RESULT2 16 23 DPHY_CRC_RESULT3 24 31 mmDP6_DP_DPHY_CRC_MST_CNTL 0 0x1f38 2 0 2 DPHY_CRC_MST_FIRST_SLOT 0 5 DPHY_CRC_MST_LAST_SLOT 8 13 mmDP6_DP_DPHY_CRC_MST_STATUS 0 0x1f39 3 0 2 DPHY_CRC_MST_PHASE_LOCK 0 0 DPHY_CRC_MST_PHASE_ERROR 8 8 DPHY_CRC_MST_PHASE_ERROR_ACK 16 16 mmDP6_DP_DPHY_FAST_TRAINING 0 0x1f3a 5 0 2 DPHY_RX_FAST_TRAINING_CAPABLE 0 0 DPHY_SW_FAST_TRAINING_START 1 1 DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN 2 2 DPHY_FAST_TRAINING_TP1_TIME 8 19 DPHY_FAST_TRAINING_TP2_TIME 20 31 mmDP6_DP_DPHY_FAST_TRAINING_STATUS 0 0x1f3b 4 0 2 DPHY_FAST_TRAINING_STATE 0 2 DPHY_FAST_TRAINING_COMPLETE_OCCURRED 4 4 DPHY_FAST_TRAINING_COMPLETE_MASK 8 8 DPHY_FAST_TRAINING_COMPLETE_ACK 12 12 mmDP6_DP_MSA_V_TIMING_OVERRIDE1 0 0x1f3c 2 0 2 DP_MSA_V_TIMING_OVERRIDE_EN 0 0 DP_MSA_V_TOTAL_OVERRIDE 4 17 mmDP6_DP_MSA_V_TIMING_OVERRIDE2 0 0x1f3d 2 0 2 DP_MSA_V_BLANK_START_OVERRIDE 0 13 DP_MSA_V_BLANK_END_OVERRIDE 16 29 mmDP6_DP_SEC_CNTL 0 0x1f41 11 0 2 DP_SEC_STREAM_ENABLE 0 0 DP_SEC_ASP_ENABLE 4 4 DP_SEC_ATP_ENABLE 8 8 DP_SEC_AIP_ENABLE 12 12 DP_SEC_ACM_ENABLE 16 16 DP_SEC_GSP0_ENABLE 20 20 DP_SEC_GSP1_ENABLE 21 21 DP_SEC_GSP2_ENABLE 22 22 DP_SEC_GSP3_ENABLE 23 23 DP_SEC_AVI_ENABLE 24 24 DP_SEC_MPG_ENABLE 28 28 mmDP6_DP_SEC_CNTL1 0 0x1f42 6 0 2 DP_SEC_ISRC_ENABLE 0 0 DP_SEC_GSP0_PRIORITY 4 4 DP_SEC_GSP0_SEND 5 5 DP_SEC_GSP0_SEND_PENDING 6 6 DP_SEC_GSP0_SEND_DEADLINE_MISSED 7 7 DP_SEC_GSP0_LINE_NUM 16 31 mmDP6_DP_SEC_FRAMING1 0 0x1f43 2 0 2 DP_SEC_FRAME_START_LOCATION 0 11 DP_SEC_VBLANK_TRANSMIT_WIDTH 16 31 mmDP6_DP_SEC_FRAMING2 0 0x1f44 2 0 2 DP_SEC_START_POSITION 0 15 DP_SEC_HBLANK_TRANSMIT_WIDTH 16 31 mmDP6_DP_SEC_FRAMING3 0 0x1f45 2 0 2 DP_SEC_IDLE_FRAME_SIZE 0 13 DP_SEC_IDLE_TRANSMIT_WIDTH 16 31 mmDP6_DP_SEC_FRAMING4 0 0x1f46 4 0 2 DP_SEC_COLLISION_STATUS 20 20 DP_SEC_COLLISION_ACK 24 24 DP_SEC_AUDIO_MUTE 28 28 DP_SEC_AUDIO_MUTE_STATUS 29 29 mmDP6_DP_SEC_AUD_N 0 0x1f47 1 0 2 DP_SEC_AUD_N 0 23 mmDP6_DP_SEC_AUD_N_READBACK 0 0x1f48 1 0 2 DP_SEC_AUD_N_READBACK 0 23 mmDP6_DP_SEC_AUD_M 0 0x1f49 1 0 2 DP_SEC_AUD_M 0 23 mmDP6_DP_SEC_AUD_M_READBACK 0 0x1f4a 1 0 2 DP_SEC_AUD_M_READBACK 0 23 mmDP6_DP_SEC_TIMESTAMP 0 0x1f4b 1 0 2 DP_SEC_TIMESTAMP_MODE 0 0 mmDP6_DP_SEC_PACKET_CNTL 0 0x1f4c 4 0 2 DP_SEC_ASP_CODING_TYPE 1 3 DP_SEC_ASP_PRIORITY 4 4 DP_SEC_VERSION 8 13 DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE 16 16 mmDP6_DP_MSE_RATE_CNTL 0 0x1f4d 2 0 2 DP_MSE_RATE_Y 0 25 DP_MSE_RATE_X 26 31 mmDP6_DP_MSE_RATE_UPDATE 0 0x1f4f 1 0 2 DP_MSE_RATE_UPDATE_PENDING 0 0 mmDP6_DP_MSE_SAT0 0 0x1f50 4 0 2 DP_MSE_SAT_SRC0 0 2 DP_MSE_SAT_SLOT_COUNT0 8 13 DP_MSE_SAT_SRC1 16 18 DP_MSE_SAT_SLOT_COUNT1 24 29 mmDP6_DP_MSE_SAT1 0 0x1f51 4 0 2 DP_MSE_SAT_SRC2 0 2 DP_MSE_SAT_SLOT_COUNT2 8 13 DP_MSE_SAT_SRC3 16 18 DP_MSE_SAT_SLOT_COUNT3 24 29 mmDP6_DP_MSE_SAT2 0 0x1f52 4 0 2 DP_MSE_SAT_SRC4 0 2 DP_MSE_SAT_SLOT_COUNT4 8 13 DP_MSE_SAT_SRC5 16 18 DP_MSE_SAT_SLOT_COUNT5 24 29 mmDP6_DP_MSE_SAT_UPDATE 0 0x1f53 2 0 2 DP_MSE_SAT_UPDATE 0 1 DP_MSE_16_MTP_KEEPOUT 8 8 mmDP6_DP_MSE_LINK_TIMING 0 0x1f54 2 0 2 DP_MSE_LINK_FRAME 0 9 DP_MSE_LINK_LINE 16 17 mmDP6_DP_MSE_MISC_CNTL 0 0x1f55 3 0 2 DP_MSE_BLANK_CODE 0 0 DP_MSE_TIMESTAMP_MODE 4 4 DP_MSE_ZERO_ENCODER 8 8 mmDP6_DP_DPHY_BS_SR_SWAP_CNTL 0 0x1f5a 3 0 2 DPHY_LOAD_BS_COUNT 0 9 DPHY_BS_SR_SWAP_DONE 15 15 DPHY_LOAD_BS_COUNT_START 16 16 mmDP6_DP_DPHY_HBR2_PATTERN_CONTROL 0 0x1f5b 1 0 2 DP_DPHY_HBR2_PATTERN_CONTROL 0 2 mmDP6_DP_MSE_SAT0_STATUS 0 0x1f5d 4 0 2 DP_MSE_SAT_SRC0_STATUS 0 2 DP_MSE_SAT_SLOT_COUNT0_STATUS 8 13 DP_MSE_SAT_SRC1_STATUS 16 18 DP_MSE_SAT_SLOT_COUNT1_STATUS 24 29 mmDP6_DP_MSE_SAT1_STATUS 0 0x1f5e 4 0 2 DP_MSE_SAT_SRC2_STATUS 0 2 DP_MSE_SAT_SLOT_COUNT2_STATUS 8 13 DP_MSE_SAT_SRC3_STATUS 16 18 DP_MSE_SAT_SLOT_COUNT3_STATUS 24 29 mmDP6_DP_MSE_SAT2_STATUS 0 0x1f5f 4 0 2 DP_MSE_SAT_SRC4_STATUS 0 2 DP_MSE_SAT_SLOT_COUNT4_STATUS 8 13 DP_MSE_SAT_SRC5_STATUS 16 18 DP_MSE_SAT_SLOT_COUNT5_STATUS 24 29 mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED0 0 0x213e 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED1 0 0x213f 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED2 0 0x2140 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED3 0 0x2141 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED4 0 0x2142 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED5 0 0x2143 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED6 0 0x2144 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED7 0 0x2145 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED8 0 0x2146 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED9 0 0x2147 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED10 0 0x2148 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED11 0 0x2149 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED12 0 0x214a 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED13 0 0x214b 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED14 0 0x214c 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED15 0 0x214d 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED16 0 0x214e 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED17 0 0x214f 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED18 0 0x2150 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED19 0 0x2151 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED20 0 0x2152 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED21 0 0x2153 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED22 0 0x2154 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED23 0 0x2155 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED24 0 0x2156 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED25 0 0x2157 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED26 0 0x2158 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED27 0 0x2159 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED28 0 0x215a 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED29 0 0x215b 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED30 0 0x215c 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED31 0 0x215d 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED32 0 0x215e 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED33 0 0x215f 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED34 0 0x2160 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED35 0 0x2161 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED36 0 0x2162 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED37 0 0x2163 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED38 0 0x2164 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED39 0 0x2165 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED40 0 0x2166 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED41 0 0x2167 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED42 0 0x2168 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED43 0 0x2169 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED44 0 0x216a 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED45 0 0x216b 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED46 0 0x216c 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED47 0 0x216d 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED48 0 0x216e 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED49 0 0x216f 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED50 0 0x2170 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED51 0 0x2171 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED52 0 0x2172 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED53 0 0x2173 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED54 0 0x2174 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED55 0 0x2175 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED56 0 0x2176 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED57 0 0x2177 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED58 0 0x2178 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED59 0 0x2179 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED60 0 0x217a 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED61 0 0x217b 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED62 0 0x217c 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED63 0 0x217d 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED64 0 0x217e 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED65 0 0x217f 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED66 0 0x2180 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED67 0 0x2181 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED68 0 0x2182 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED69 0 0x2183 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED70 0 0x2184 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED71 0 0x2185 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED72 0 0x2186 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED73 0 0x2187 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED74 0 0x2188 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED75 0 0x2189 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED76 0 0x218a 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED77 0 0x218b 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED78 0 0x218c 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED79 0 0x218d 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED80 0 0x218e 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED81 0 0x218f 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED82 0 0x2190 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED83 0 0x2191 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED84 0 0x2192 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED85 0 0x2193 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED86 0 0x2194 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED87 0 0x2195 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED88 0 0x2196 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED89 0 0x2197 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED90 0 0x2198 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED91 0 0x2199 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED92 0 0x219a 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED93 0 0x219b 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED94 0 0x219c 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED95 0 0x219d 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED96 0 0x219e 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED97 0 0x219f 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED98 0 0x21a0 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED99 0 0x21a1 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED100 0 0x21a2 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED101 0 0x21a3 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED102 0 0x21a4 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED103 0 0x21a5 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED104 0 0x21a6 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED105 0 0x21a7 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED106 0 0x21a8 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED107 0 0x21a9 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED108 0 0x21aa 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED109 0 0x21ab 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED110 0 0x21ac 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED111 0 0x21ad 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED112 0 0x21ae 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED113 0 0x21af 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED114 0 0x21b0 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED115 0 0x21b1 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED116 0 0x21b2 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED117 0 0x21b3 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED118 0 0x21b4 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED119 0 0x21b5 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED120 0 0x21b6 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED121 0 0x21b7 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED122 0 0x21b8 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED123 0 0x21b9 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED124 0 0x21ba 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED125 0 0x21bb 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED126 0 0x21bc 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED127 0 0x21bd 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED128 0 0x21be 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED129 0 0x21bf 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED130 0 0x21c0 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED131 0 0x21c1 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED132 0 0x21c2 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED133 0 0x21c3 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED134 0 0x21c4 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED135 0 0x21c5 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED136 0 0x21c6 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED137 0 0x21c7 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED138 0 0x21c8 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED139 0 0x21c9 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED140 0 0x21ca 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED141 0 0x21cb 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED142 0 0x21cc 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED143 0 0x21cd 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED144 0 0x21ce 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED145 0 0x21cf 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED146 0 0x21d0 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED147 0 0x21d1 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED148 0 0x21d2 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED149 0 0x21d3 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED150 0 0x21d4 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED151 0 0x21d5 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED152 0 0x21d6 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED153 0 0x21d7 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED154 0 0x21d8 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED155 0 0x21d9 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED156 0 0x21da 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED157 0 0x21db 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED158 0 0x21dc 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED159 0 0x21dd 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDC_COMBOPHYCMREGS0_COMMON_FUSE1 0 0x213e 11 0 2 fuse1_valid 0 0 fuse1_unpopulated0 1 2 fuse1_ron_override_val 3 8 fuse1_unpopulated1 9 9 fuse1_ron_ctl 10 11 fuse1_unpopulated2 12 12 fuse1_rtt_override_val 13 18 fuse1_unpopulated3 19 19 fuse1_rtt_ctl 20 21 fuse1_refresh_cal_en 22 22 fuse1_spare 23 31 mmDC_COMBOPHYCMREGS0_COMMON_FUSE2 0 0x213f 4 0 2 fuse2_valid 0 0 fuse2_unpopulated 1 8 fuse2_tx_fifo_ptr 9 13 fuse2_spare 14 31 mmDC_COMBOPHYCMREGS0_COMMON_FUSE3 0 0x2140 4 0 2 fuse3_valid 0 0 fuse3_unpopulated 1 9 fuse3_ei_det_thresh_sel 10 12 fuse3_spare 29 31 mmDC_COMBOPHYCMREGS0_COMMON_MAR_DEEMPH_NOM 0 0x2141 4 0 2 tx_margin_nom 0 7 deemph_gen1_nom 8 15 deemph35_gen2_nom 16 23 deemph60_gen2_nom 24 31 mmDC_COMBOPHYCMREGS0_COMMON_LANE_PWRMGMT 0 0x2142 3 0 2 pgdelay 0 3 pgmask 4 9 vprot_en 11 11 mmDC_COMBOPHYCMREGS0_COMMON_TXCNTRL 0 0x2143 7 0 2 rdptr_rst_val_gen3 0 4 clkgate_dis 5 5 slew_rate_ctl_gen1 6 8 slew_rate_ctl_gen2 9 11 slew_rate_ctl_gen3 12 14 dual_dvi_mstr_en 15 15 dual_dvi_en 16 16 mmDC_COMBOPHYCMREGS0_COMMON_TMDP 0 0x2144 1 0 2 tmdp_spare 0 31 mmDC_COMBOPHYCMREGS0_COMMON_LANE_RESETS 0 0x2145 8 0 2 lane_0_reset_l 0 0 lane_1_reset_l 1 1 lane_2_reset_l 2 2 lane_3_reset_l 3 3 lane_4_reset_l 4 4 lane_5_reset_l 5 5 lane_6_reset_l 6 6 lane_7_reset_l 7 7 mmDC_COMBOPHYCMREGS0_COMMON_ZCALCODE_CTRL 0 0x2146 3 0 2 zcalcode_override 0 0 tx_binary_code_override_val 1 5 tx_driver_fifty_ohms 21 21 mmDC_COMBOPHYCMREGS0_COMMON_DISP_RFU1 0 0x2147 1 0 2 rfu_value1 0 31 mmDC_COMBOPHYCMREGS0_COMMON_DISP_RFU2 0 0x2148 1 0 2 rfu_value2 0 31 mmDC_COMBOPHYCMREGS0_COMMON_DISP_RFU3 0 0x2149 1 0 2 rfu_value3 0 31 mmDC_COMBOPHYCMREGS0_COMMON_DISP_RFU4 0 0x214a 1 0 2 rfu_value4 0 31 mmDC_COMBOPHYCMREGS0_COMMON_DISP_RFU5 0 0x214b 1 0 2 rfu_value5 0 31 mmDC_COMBOPHYCMREGS0_COMMON_DISP_RFU6 0 0x214c 1 0 2 rfu_value6 0 31 mmDC_COMBOPHYCMREGS0_COMMON_DISP_RFU7 0 0x214d 1 0 2 rfu_value7 0 31 mmDC_COMBOPHYTXREGS0_CMD_BUS_TX_CONTROL_LANE0 0 0x215e 3 0 2 tx_pwr 0 2 tx_pg_en 3 4 tx_rdy 8 8 mmDC_COMBOPHYTXREGS0_MARGIN_DEEMPH_LANE0 0 0x215f 3 0 2 txmarg_sel 0 2 deemph_sel 3 4 tx_margin_en 5 5 mmDC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE0 0 0x2160 12 0 2 twosym_en 1 2 link_speed 3 4 gang_mode 5 7 max_linkrate 8 9 pcs_freq 10 11 pcs_clken 12 12 pcs_clkdone 13 13 pll1_always_on 14 14 rdclk_div2_en 15 15 tx_boost_adj 16 19 tx_boost_en 20 20 tx_binary_ron_code_offset 22 23 mmDC_COMBOPHYTXREGS0_TX_DISP_RFU0_LANE0 0 0x2161 1 0 2 rfu_value0 0 31 mmDC_COMBOPHYTXREGS0_TX_DISP_RFU1_LANE0 0 0x2162 1 0 2 rfu_value1 0 31 mmDC_COMBOPHYTXREGS0_TX_DISP_RFU2_LANE0 0 0x2163 1 0 2 rfu_value2 0 31 mmDC_COMBOPHYTXREGS0_TX_DISP_RFU3_LANE0 0 0x2164 1 0 2 rfu_value3 0 31 mmDC_COMBOPHYTXREGS0_TX_DISP_RFU4_LANE0 0 0x2165 1 0 2 rfu_value4 0 31 mmDC_COMBOPHYTXREGS0_TX_DISP_RFU5_LANE0 0 0x2166 1 0 2 rfu_value5 0 31 mmDC_COMBOPHYTXREGS0_TX_DISP_RFU6_LANE0 0 0x2167 1 0 2 rfu_value6 0 31 mmDC_COMBOPHYTXREGS0_TX_DISP_RFU7_LANE0 0 0x2168 1 0 2 rfu_value7 0 31 mmDC_COMBOPHYTXREGS0_TX_DISP_RFU8_LANE0 0 0x2169 1 0 2 rfu_value8 0 31 mmDC_COMBOPHYTXREGS0_TX_DISP_RFU9_LANE0 0 0x216a 1 0 2 rfu_value9 0 31 mmDC_COMBOPHYTXREGS0_TX_DISP_RFU10_LANE0 0 0x216b 1 0 2 rfu_value10 0 31 mmDC_COMBOPHYTXREGS0_TX_DISP_RFU11_LANE0 0 0x216c 1 0 2 rfu_value11 0 31 mmDC_COMBOPHYTXREGS0_TX_DISP_RFU12_LANE0 0 0x216d 1 0 2 rfu_value12 0 31 mmDC_COMBOPHYTXREGS0_CMD_BUS_TX_CONTROL_LANE1 0 0x216e 3 0 2 tx_pwr 0 2 tx_pg_en 3 4 tx_rdy 8 8 mmDC_COMBOPHYTXREGS0_MARGIN_DEEMPH_LANE1 0 0x216f 3 0 2 txmarg_sel 0 2 deemph_sel 3 4 tx_margin_en 5 5 mmDC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE1 0 0x2170 12 0 2 twosym_en 1 2 link_speed 3 4 gang_mode 5 7 max_linkrate 8 9 pcs_freq 10 11 pcs_clken 12 12 pcs_clkdone 13 13 pll1_always_on 14 14 rdclk_div2_en 15 15 tx_boost_adj 16 19 tx_boost_en 20 20 tx_binary_ron_code_offset 22 23 mmDC_COMBOPHYTXREGS0_TX_DISP_RFU0_LANE1 0 0x2171 1 0 2 rfu_value0 0 31 mmDC_COMBOPHYTXREGS0_TX_DISP_RFU1_LANE1 0 0x2172 1 0 2 rfu_value1 0 31 mmDC_COMBOPHYTXREGS0_TX_DISP_RFU2_LANE1 0 0x2173 1 0 2 rfu_value2 0 31 mmDC_COMBOPHYTXREGS0_TX_DISP_RFU3_LANE1 0 0x2174 1 0 2 rfu_value3 0 31 mmDC_COMBOPHYTXREGS0_TX_DISP_RFU4_LANE1 0 0x2175 1 0 2 rfu_value4 0 31 mmDC_COMBOPHYTXREGS0_TX_DISP_RFU5_LANE1 0 0x2176 1 0 2 rfu_value5 0 31 mmDC_COMBOPHYTXREGS0_TX_DISP_RFU6_LANE1 0 0x2177 1 0 2 rfu_value6 0 31 mmDC_COMBOPHYTXREGS0_TX_DISP_RFU7_LANE1 0 0x2178 1 0 2 rfu_value7 0 31 mmDC_COMBOPHYTXREGS0_TX_DISP_RFU8_LANE1 0 0x2179 1 0 2 rfu_value8 0 31 mmDC_COMBOPHYTXREGS0_TX_DISP_RFU9_LANE1 0 0x217a 1 0 2 rfu_value9 0 31 mmDC_COMBOPHYTXREGS0_TX_DISP_RFU10_LANE1 0 0x217b 1 0 2 rfu_value10 0 31 mmDC_COMBOPHYTXREGS0_TX_DISP_RFU11_LANE1 0 0x217c 1 0 2 rfu_value11 0 31 mmDC_COMBOPHYTXREGS0_TX_DISP_RFU12_LANE1 0 0x217d 1 0 2 rfu_value12 0 31 mmDC_COMBOPHYTXREGS0_CMD_BUS_TX_CONTROL_LANE2 0 0x217e 3 0 2 tx_pwr 0 2 tx_pg_en 3 4 tx_rdy 8 8 mmDC_COMBOPHYTXREGS0_MARGIN_DEEMPH_LANE2 0 0x217f 3 0 2 txmarg_sel 0 2 deemph_sel 3 4 tx_margin_en 5 5 mmDC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE2 0 0x2180 12 0 2 twosym_en 1 2 link_speed 3 4 gang_mode 5 7 max_linkrate 8 9 pcs_freq 10 11 pcs_clken 12 12 pcs_clkdone 13 13 pll1_always_on 14 14 rdclk_div2_en 15 15 tx_boost_adj 16 19 tx_boost_en 20 20 tx_binary_ron_code_offset 22 23 mmDC_COMBOPHYTXREGS0_TX_DISP_RFU0_LANE2 0 0x2181 1 0 2 rfu_value0 0 31 mmDC_COMBOPHYTXREGS0_TX_DISP_RFU1_LANE2 0 0x2182 1 0 2 rfu_value1 0 31 mmDC_COMBOPHYTXREGS0_TX_DISP_RFU2_LANE2 0 0x2183 1 0 2 rfu_value2 0 31 mmDC_COMBOPHYTXREGS0_TX_DISP_RFU3_LANE2 0 0x2184 1 0 2 rfu_value3 0 31 mmDC_COMBOPHYTXREGS0_TX_DISP_RFU4_LANE2 0 0x2185 1 0 2 rfu_value4 0 31 mmDC_COMBOPHYTXREGS0_TX_DISP_RFU5_LANE2 0 0x2186 1 0 2 rfu_value5 0 31 mmDC_COMBOPHYTXREGS0_TX_DISP_RFU6_LANE2 0 0x2187 1 0 2 rfu_value6 0 31 mmDC_COMBOPHYTXREGS0_TX_DISP_RFU7_LANE2 0 0x2188 1 0 2 rfu_value7 0 31 mmDC_COMBOPHYTXREGS0_TX_DISP_RFU8_LANE2 0 0x2189 1 0 2 rfu_value8 0 31 mmDC_COMBOPHYTXREGS0_TX_DISP_RFU9_LANE2 0 0x218a 1 0 2 rfu_value9 0 31 mmDC_COMBOPHYTXREGS0_TX_DISP_RFU10_LANE2 0 0x218b 1 0 2 rfu_value10 0 31 mmDC_COMBOPHYTXREGS0_TX_DISP_RFU11_LANE2 0 0x218c 1 0 2 rfu_value11 0 31 mmDC_COMBOPHYTXREGS0_TX_DISP_RFU12_LANE2 0 0x218d 1 0 2 rfu_value12 0 31 mmDC_COMBOPHYTXREGS0_CMD_BUS_TX_CONTROL_LANE3 0 0x218e 3 0 2 tx_pwr 0 2 tx_pg_en 3 4 tx_rdy 8 8 mmDC_COMBOPHYTXREGS0_MARGIN_DEEMPH_LANE3 0 0x218f 3 0 2 txmarg_sel 0 2 deemph_sel 3 4 tx_margin_en 5 5 mmDC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE3 0 0x2190 12 0 2 twosym_en 1 2 link_speed 3 4 gang_mode 5 7 max_linkrate 8 9 pcs_freq 10 11 pcs_clken 12 12 pcs_clkdone 13 13 pll1_always_on 14 14 rdclk_div2_en 15 15 tx_boost_adj 16 19 tx_boost_en 20 20 tx_binary_ron_code_offset 22 23 mmDC_COMBOPHYTXREGS0_TX_DISP_RFU0_LANE3 0 0x2191 1 0 2 rfu_value0 0 31 mmDC_COMBOPHYTXREGS0_TX_DISP_RFU1_LANE3 0 0x2192 1 0 2 rfu_value1 0 31 mmDC_COMBOPHYTXREGS0_TX_DISP_RFU2_LANE3 0 0x2193 1 0 2 rfu_value2 0 31 mmDC_COMBOPHYTXREGS0_TX_DISP_RFU3_LANE3 0 0x2194 1 0 2 rfu_value3 0 31 mmDC_COMBOPHYTXREGS0_TX_DISP_RFU4_LANE3 0 0x2195 1 0 2 rfu_value4 0 31 mmDC_COMBOPHYTXREGS0_TX_DISP_RFU5_LANE3 0 0x2196 1 0 2 rfu_value5 0 31 mmDC_COMBOPHYTXREGS0_TX_DISP_RFU6_LANE3 0 0x2197 1 0 2 rfu_value6 0 31 mmDC_COMBOPHYTXREGS0_TX_DISP_RFU7_LANE3 0 0x2198 1 0 2 rfu_value7 0 31 mmDC_COMBOPHYTXREGS0_TX_DISP_RFU8_LANE3 0 0x2199 1 0 2 rfu_value8 0 31 mmDC_COMBOPHYTXREGS0_TX_DISP_RFU9_LANE3 0 0x219a 1 0 2 rfu_value9 0 31 mmDC_COMBOPHYTXREGS0_TX_DISP_RFU10_LANE3 0 0x219b 1 0 2 rfu_value10 0 31 mmDC_COMBOPHYTXREGS0_TX_DISP_RFU11_LANE3 0 0x219c 1 0 2 rfu_value11 0 31 mmDC_COMBOPHYTXREGS0_TX_DISP_RFU12_LANE3 0 0x219d 1 0 2 rfu_value12 0 31 mmDC_COMBOPHYPLLREGS0_FREQ_CTRL0 0 0x219e 2 0 2 fcw0_frac 0 15 fcw0_int 16 24 mmDC_COMBOPHYPLLREGS0_FREQ_CTRL1 0 0x219f 2 0 2 fcw1_frac 0 15 fcw1_int 16 24 mmDC_COMBOPHYPLLREGS0_FREQ_CTRL2 0 0x21a0 2 0 2 fcw_denom 0 15 fcw_slew_frac 16 31 mmDC_COMBOPHYPLLREGS0_FREQ_CTRL3 0 0x21a1 8 0 2 refclk_div 0 1 vco_pre_div 3 4 fracn_en 6 6 ssc_en 8 8 fcw_sel 10 10 freq_jump_en 12 12 tdc_resolution 16 23 dpll_cfg_1 24 31 mmDC_COMBOPHYPLLREGS0_BW_CTRL_COARSE 0 0x21a2 6 0 2 gi_coarse_mant 0 1 gi_coarse_exp 2 5 gp_coarse_mant 7 10 gp_coarse_exp 12 15 nctl_coarse_res 17 22 nctl_coarse_frac_res 24 25 mmDC_COMBOPHYPLLREGS0_BW_CTRL_FINE 0 0x21a3 1 0 2 dpll_cfg_3 0 9 mmDC_COMBOPHYPLLREGS0_CAL_CTRL 0 0x21a4 9 0 2 bypass_freq_lock 0 0 tdc_cal_en 1 1 tdc_cal_ctrl 3 8 meas_win_sel 9 10 kdco_cal_dis 11 11 kdco_ratio 13 20 kdco_incr_cal_dis 22 22 nctl_adj_dis 23 23 refclk_rate 24 31 mmDC_COMBOPHYPLLREGS0_LOOP_CTRL 0 0x21a5 10 0 2 fbdiv_mask_en 0 0 fb_slip_dis 2 2 clk_tdc_sel 4 5 clk_nctl_sel 7 8 sig_del_patt_sel 10 10 nctl_sig_del_dis 12 12 fbclk_track_refclk 14 14 prbs_en 16 16 tdc_clk_gate_en 18 18 phase_offset 20 26 mmDC_COMBOPHYPLLREGS0_VREG_CFG 0 0x21a7 14 0 2 bleeder_ac 0 0 bleeder_en 1 1 is_1p2 2 2 reg_obs_sel 3 4 reg_on_mode 5 6 rlad_tap_sel 7 10 reg_off_hi 11 11 reg_off_lo 12 12 scale_driver 13 14 sel_bump 15 15 sel_rladder_x 16 16 short_rc_filt_x 17 17 vref_pwr_on 18 18 dpll_cfg_2 20 27 mmDC_COMBOPHYPLLREGS0_OBSERVE0 0 0x21a8 5 0 2 lock_det_tdc_steps 0 4 clear_sticky_lock 6 6 lock_det_dis 8 8 dco_cfg 10 17 anaobs_sel 21 23 mmDC_COMBOPHYPLLREGS0_OBSERVE1 0 0x21a9 5 0 2 digobs_sel 0 3 digobs_trig_sel 5 8 digobs_div 10 11 digobs_trig_div 13 14 lock_timer 16 29 mmDC_COMBOPHYPLLREGS0_DFT_OUT 0 0x21aa 1 0 2 dft_data 0 31 mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED0 0 0x2206 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED1 0 0x2207 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED2 0 0x2208 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED3 0 0x2209 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED4 0 0x220a 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED5 0 0x220b 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED6 0 0x220c 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED7 0 0x220d 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED8 0 0x220e 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED9 0 0x220f 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED10 0 0x2210 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED11 0 0x2211 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED12 0 0x2212 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED13 0 0x2213 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED14 0 0x2214 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED15 0 0x2215 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED16 0 0x2216 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED17 0 0x2217 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED18 0 0x2218 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED19 0 0x2219 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED20 0 0x221a 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED21 0 0x221b 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED22 0 0x221c 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED23 0 0x221d 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED24 0 0x221e 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED25 0 0x221f 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED26 0 0x2220 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED27 0 0x2221 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED28 0 0x2222 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED29 0 0x2223 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED30 0 0x2224 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED31 0 0x2225 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED32 0 0x2226 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED33 0 0x2227 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED34 0 0x2228 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED35 0 0x2229 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED36 0 0x222a 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED37 0 0x222b 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED38 0 0x222c 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED39 0 0x222d 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED40 0 0x222e 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED41 0 0x222f 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED42 0 0x2230 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED43 0 0x2231 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED44 0 0x2232 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED45 0 0x2233 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED46 0 0x2234 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED47 0 0x2235 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED48 0 0x2236 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED49 0 0x2237 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED50 0 0x2238 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED51 0 0x2239 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED52 0 0x223a 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED53 0 0x223b 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED54 0 0x223c 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED55 0 0x223d 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED56 0 0x223e 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED57 0 0x223f 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED58 0 0x2240 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED59 0 0x2241 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED60 0 0x2242 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED61 0 0x2243 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED62 0 0x2244 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED63 0 0x2245 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED64 0 0x2246 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED65 0 0x2247 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED66 0 0x2248 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED67 0 0x2249 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED68 0 0x224a 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED69 0 0x224b 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED70 0 0x224c 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED71 0 0x224d 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED72 0 0x224e 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED73 0 0x224f 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED74 0 0x2250 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED75 0 0x2251 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED76 0 0x2252 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED77 0 0x2253 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED78 0 0x2254 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED79 0 0x2255 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED80 0 0x2256 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED81 0 0x2257 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED82 0 0x2258 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED83 0 0x2259 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED84 0 0x225a 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED85 0 0x225b 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED86 0 0x225c 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED87 0 0x225d 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED88 0 0x225e 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED89 0 0x225f 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED90 0 0x2260 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED91 0 0x2261 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED92 0 0x2262 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED93 0 0x2263 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED94 0 0x2264 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED95 0 0x2265 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED96 0 0x2266 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED97 0 0x2267 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED98 0 0x2268 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED99 0 0x2269 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED100 0 0x226a 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED101 0 0x226b 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED102 0 0x226c 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED103 0 0x226d 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED104 0 0x226e 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED105 0 0x226f 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED106 0 0x2270 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED107 0 0x2271 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED108 0 0x2272 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED109 0 0x2273 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED110 0 0x2274 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED111 0 0x2275 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED112 0 0x2276 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED113 0 0x2277 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED114 0 0x2278 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED115 0 0x2279 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED116 0 0x227a 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED117 0 0x227b 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED118 0 0x227c 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED119 0 0x227d 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED120 0 0x227e 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED121 0 0x227f 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED122 0 0x2280 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED123 0 0x2281 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED124 0 0x2282 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED125 0 0x2283 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED126 0 0x2284 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED127 0 0x2285 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED128 0 0x2286 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED129 0 0x2287 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED130 0 0x2288 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED131 0 0x2289 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED132 0 0x228a 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED133 0 0x228b 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED134 0 0x228c 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED135 0 0x228d 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED136 0 0x228e 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED137 0 0x228f 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED138 0 0x2290 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED139 0 0x2291 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED140 0 0x2292 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED141 0 0x2293 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED142 0 0x2294 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED143 0 0x2295 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED144 0 0x2296 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED145 0 0x2297 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED146 0 0x2298 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED147 0 0x2299 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED148 0 0x229a 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED149 0 0x229b 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED150 0 0x229c 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED151 0 0x229d 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED152 0 0x229e 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED153 0 0x229f 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED154 0 0x22a0 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED155 0 0x22a1 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED156 0 0x22a2 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED157 0 0x22a3 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED158 0 0x22a4 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED159 0 0x22a5 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDC_COMBOPHYCMREGS1_COMMON_FUSE1 0 0x2206 11 0 2 fuse1_valid 0 0 fuse1_unpopulated0 1 2 fuse1_ron_override_val 3 8 fuse1_unpopulated1 9 9 fuse1_ron_ctl 10 11 fuse1_unpopulated2 12 12 fuse1_rtt_override_val 13 18 fuse1_unpopulated3 19 19 fuse1_rtt_ctl 20 21 fuse1_refresh_cal_en 22 22 fuse1_spare 23 31 mmDC_COMBOPHYCMREGS1_COMMON_FUSE2 0 0x2207 4 0 2 fuse2_valid 0 0 fuse2_unpopulated 1 8 fuse2_tx_fifo_ptr 9 13 fuse2_spare 14 31 mmDC_COMBOPHYCMREGS1_COMMON_FUSE3 0 0x2208 4 0 2 fuse3_valid 0 0 fuse3_unpopulated 1 9 fuse3_ei_det_thresh_sel 10 12 fuse3_spare 29 31 mmDC_COMBOPHYCMREGS1_COMMON_MAR_DEEMPH_NOM 0 0x2209 4 0 2 tx_margin_nom 0 7 deemph_gen1_nom 8 15 deemph35_gen2_nom 16 23 deemph60_gen2_nom 24 31 mmDC_COMBOPHYCMREGS1_COMMON_LANE_PWRMGMT 0 0x220a 3 0 2 pgdelay 0 3 pgmask 4 9 vprot_en 11 11 mmDC_COMBOPHYCMREGS1_COMMON_TXCNTRL 0 0x220b 7 0 2 rdptr_rst_val_gen3 0 4 clkgate_dis 5 5 slew_rate_ctl_gen1 6 8 slew_rate_ctl_gen2 9 11 slew_rate_ctl_gen3 12 14 dual_dvi_mstr_en 15 15 dual_dvi_en 16 16 mmDC_COMBOPHYCMREGS1_COMMON_TMDP 0 0x220c 1 0 2 tmdp_spare 0 31 mmDC_COMBOPHYCMREGS1_COMMON_LANE_RESETS 0 0x220d 8 0 2 lane_0_reset_l 0 0 lane_1_reset_l 1 1 lane_2_reset_l 2 2 lane_3_reset_l 3 3 lane_4_reset_l 4 4 lane_5_reset_l 5 5 lane_6_reset_l 6 6 lane_7_reset_l 7 7 mmDC_COMBOPHYCMREGS1_COMMON_ZCALCODE_CTRL 0 0x220e 3 0 2 zcalcode_override 0 0 tx_binary_code_override_val 1 5 tx_driver_fifty_ohms 21 21 mmDC_COMBOPHYCMREGS1_COMMON_DISP_RFU1 0 0x220f 1 0 2 rfu_value1 0 31 mmDC_COMBOPHYCMREGS1_COMMON_DISP_RFU2 0 0x2210 1 0 2 rfu_value2 0 31 mmDC_COMBOPHYCMREGS1_COMMON_DISP_RFU3 0 0x2211 1 0 2 rfu_value3 0 31 mmDC_COMBOPHYCMREGS1_COMMON_DISP_RFU4 0 0x2212 1 0 2 rfu_value4 0 31 mmDC_COMBOPHYCMREGS1_COMMON_DISP_RFU5 0 0x2213 1 0 2 rfu_value5 0 31 mmDC_COMBOPHYCMREGS1_COMMON_DISP_RFU6 0 0x2214 1 0 2 rfu_value6 0 31 mmDC_COMBOPHYCMREGS1_COMMON_DISP_RFU7 0 0x2215 1 0 2 rfu_value7 0 31 mmDC_COMBOPHYTXREGS1_CMD_BUS_TX_CONTROL_LANE0 0 0x2226 3 0 2 tx_pwr 0 2 tx_pg_en 3 4 tx_rdy 8 8 mmDC_COMBOPHYTXREGS1_MARGIN_DEEMPH_LANE0 0 0x2227 3 0 2 txmarg_sel 0 2 deemph_sel 3 4 tx_margin_en 5 5 mmDC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE0 0 0x2228 12 0 2 twosym_en 1 2 link_speed 3 4 gang_mode 5 7 max_linkrate 8 9 pcs_freq 10 11 pcs_clken 12 12 pcs_clkdone 13 13 pll1_always_on 14 14 rdclk_div2_en 15 15 tx_boost_adj 16 19 tx_boost_en 20 20 tx_binary_ron_code_offset 22 23 mmDC_COMBOPHYTXREGS1_TX_DISP_RFU0_LANE0 0 0x2229 1 0 2 rfu_value0 0 31 mmDC_COMBOPHYTXREGS1_TX_DISP_RFU1_LANE0 0 0x222a 1 0 2 rfu_value1 0 31 mmDC_COMBOPHYTXREGS1_TX_DISP_RFU2_LANE0 0 0x222b 1 0 2 rfu_value2 0 31 mmDC_COMBOPHYTXREGS1_TX_DISP_RFU3_LANE0 0 0x222c 1 0 2 rfu_value3 0 31 mmDC_COMBOPHYTXREGS1_TX_DISP_RFU4_LANE0 0 0x222d 1 0 2 rfu_value4 0 31 mmDC_COMBOPHYTXREGS1_TX_DISP_RFU5_LANE0 0 0x222e 1 0 2 rfu_value5 0 31 mmDC_COMBOPHYTXREGS1_TX_DISP_RFU6_LANE0 0 0x222f 1 0 2 rfu_value6 0 31 mmDC_COMBOPHYTXREGS1_TX_DISP_RFU7_LANE0 0 0x2230 1 0 2 rfu_value7 0 31 mmDC_COMBOPHYTXREGS1_TX_DISP_RFU8_LANE0 0 0x2231 1 0 2 rfu_value8 0 31 mmDC_COMBOPHYTXREGS1_TX_DISP_RFU9_LANE0 0 0x2232 1 0 2 rfu_value9 0 31 mmDC_COMBOPHYTXREGS1_TX_DISP_RFU10_LANE0 0 0x2233 1 0 2 rfu_value10 0 31 mmDC_COMBOPHYTXREGS1_TX_DISP_RFU11_LANE0 0 0x2234 1 0 2 rfu_value11 0 31 mmDC_COMBOPHYTXREGS1_TX_DISP_RFU12_LANE0 0 0x2235 1 0 2 rfu_value12 0 31 mmDC_COMBOPHYTXREGS1_CMD_BUS_TX_CONTROL_LANE1 0 0x2236 3 0 2 tx_pwr 0 2 tx_pg_en 3 4 tx_rdy 8 8 mmDC_COMBOPHYTXREGS1_MARGIN_DEEMPH_LANE1 0 0x2237 3 0 2 txmarg_sel 0 2 deemph_sel 3 4 tx_margin_en 5 5 mmDC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE1 0 0x2238 12 0 2 twosym_en 1 2 link_speed 3 4 gang_mode 5 7 max_linkrate 8 9 pcs_freq 10 11 pcs_clken 12 12 pcs_clkdone 13 13 pll1_always_on 14 14 rdclk_div2_en 15 15 tx_boost_adj 16 19 tx_boost_en 20 20 tx_binary_ron_code_offset 22 23 mmDC_COMBOPHYTXREGS1_TX_DISP_RFU0_LANE1 0 0x2239 1 0 2 rfu_value0 0 31 mmDC_COMBOPHYTXREGS1_TX_DISP_RFU1_LANE1 0 0x223a 1 0 2 rfu_value1 0 31 mmDC_COMBOPHYTXREGS1_TX_DISP_RFU2_LANE1 0 0x223b 1 0 2 rfu_value2 0 31 mmDC_COMBOPHYTXREGS1_TX_DISP_RFU3_LANE1 0 0x223c 1 0 2 rfu_value3 0 31 mmDC_COMBOPHYTXREGS1_TX_DISP_RFU4_LANE1 0 0x223d 1 0 2 rfu_value4 0 31 mmDC_COMBOPHYTXREGS1_TX_DISP_RFU5_LANE1 0 0x223e 1 0 2 rfu_value5 0 31 mmDC_COMBOPHYTXREGS1_TX_DISP_RFU6_LANE1 0 0x223f 1 0 2 rfu_value6 0 31 mmDC_COMBOPHYTXREGS1_TX_DISP_RFU7_LANE1 0 0x2240 1 0 2 rfu_value7 0 31 mmDC_COMBOPHYTXREGS1_TX_DISP_RFU8_LANE1 0 0x2241 1 0 2 rfu_value8 0 31 mmDC_COMBOPHYTXREGS1_TX_DISP_RFU9_LANE1 0 0x2242 1 0 2 rfu_value9 0 31 mmDC_COMBOPHYTXREGS1_TX_DISP_RFU10_LANE1 0 0x2243 1 0 2 rfu_value10 0 31 mmDC_COMBOPHYTXREGS1_TX_DISP_RFU11_LANE1 0 0x2244 1 0 2 rfu_value11 0 31 mmDC_COMBOPHYTXREGS1_TX_DISP_RFU12_LANE1 0 0x2245 1 0 2 rfu_value12 0 31 mmDC_COMBOPHYTXREGS1_CMD_BUS_TX_CONTROL_LANE2 0 0x2246 3 0 2 tx_pwr 0 2 tx_pg_en 3 4 tx_rdy 8 8 mmDC_COMBOPHYTXREGS1_MARGIN_DEEMPH_LANE2 0 0x2247 3 0 2 txmarg_sel 0 2 deemph_sel 3 4 tx_margin_en 5 5 mmDC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE2 0 0x2248 12 0 2 twosym_en 1 2 link_speed 3 4 gang_mode 5 7 max_linkrate 8 9 pcs_freq 10 11 pcs_clken 12 12 pcs_clkdone 13 13 pll1_always_on 14 14 rdclk_div2_en 15 15 tx_boost_adj 16 19 tx_boost_en 20 20 tx_binary_ron_code_offset 22 23 mmDC_COMBOPHYTXREGS1_TX_DISP_RFU0_LANE2 0 0x2249 1 0 2 rfu_value0 0 31 mmDC_COMBOPHYTXREGS1_TX_DISP_RFU1_LANE2 0 0x224a 1 0 2 rfu_value1 0 31 mmDC_COMBOPHYTXREGS1_TX_DISP_RFU2_LANE2 0 0x224b 1 0 2 rfu_value2 0 31 mmDC_COMBOPHYTXREGS1_TX_DISP_RFU3_LANE2 0 0x224c 1 0 2 rfu_value3 0 31 mmDC_COMBOPHYTXREGS1_TX_DISP_RFU4_LANE2 0 0x224d 1 0 2 rfu_value4 0 31 mmDC_COMBOPHYTXREGS1_TX_DISP_RFU5_LANE2 0 0x224e 1 0 2 rfu_value5 0 31 mmDC_COMBOPHYTXREGS1_TX_DISP_RFU6_LANE2 0 0x224f 1 0 2 rfu_value6 0 31 mmDC_COMBOPHYTXREGS1_TX_DISP_RFU7_LANE2 0 0x2250 1 0 2 rfu_value7 0 31 mmDC_COMBOPHYTXREGS1_TX_DISP_RFU8_LANE2 0 0x2251 1 0 2 rfu_value8 0 31 mmDC_COMBOPHYTXREGS1_TX_DISP_RFU9_LANE2 0 0x2252 1 0 2 rfu_value9 0 31 mmDC_COMBOPHYTXREGS1_TX_DISP_RFU10_LANE2 0 0x2253 1 0 2 rfu_value10 0 31 mmDC_COMBOPHYTXREGS1_TX_DISP_RFU11_LANE2 0 0x2254 1 0 2 rfu_value11 0 31 mmDC_COMBOPHYTXREGS1_TX_DISP_RFU12_LANE2 0 0x2255 1 0 2 rfu_value12 0 31 mmDC_COMBOPHYTXREGS1_CMD_BUS_TX_CONTROL_LANE3 0 0x2256 3 0 2 tx_pwr 0 2 tx_pg_en 3 4 tx_rdy 8 8 mmDC_COMBOPHYTXREGS1_MARGIN_DEEMPH_LANE3 0 0x2257 3 0 2 txmarg_sel 0 2 deemph_sel 3 4 tx_margin_en 5 5 mmDC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE3 0 0x2258 12 0 2 twosym_en 1 2 link_speed 3 4 gang_mode 5 7 max_linkrate 8 9 pcs_freq 10 11 pcs_clken 12 12 pcs_clkdone 13 13 pll1_always_on 14 14 rdclk_div2_en 15 15 tx_boost_adj 16 19 tx_boost_en 20 20 tx_binary_ron_code_offset 22 23 mmDC_COMBOPHYTXREGS1_TX_DISP_RFU0_LANE3 0 0x2259 1 0 2 rfu_value0 0 31 mmDC_COMBOPHYTXREGS1_TX_DISP_RFU1_LANE3 0 0x225a 1 0 2 rfu_value1 0 31 mmDC_COMBOPHYTXREGS1_TX_DISP_RFU2_LANE3 0 0x225b 1 0 2 rfu_value2 0 31 mmDC_COMBOPHYTXREGS1_TX_DISP_RFU3_LANE3 0 0x225c 1 0 2 rfu_value3 0 31 mmDC_COMBOPHYTXREGS1_TX_DISP_RFU4_LANE3 0 0x225d 1 0 2 rfu_value4 0 31 mmDC_COMBOPHYTXREGS1_TX_DISP_RFU5_LANE3 0 0x225e 1 0 2 rfu_value5 0 31 mmDC_COMBOPHYTXREGS1_TX_DISP_RFU6_LANE3 0 0x225f 1 0 2 rfu_value6 0 31 mmDC_COMBOPHYTXREGS1_TX_DISP_RFU7_LANE3 0 0x2260 1 0 2 rfu_value7 0 31 mmDC_COMBOPHYTXREGS1_TX_DISP_RFU8_LANE3 0 0x2261 1 0 2 rfu_value8 0 31 mmDC_COMBOPHYTXREGS1_TX_DISP_RFU9_LANE3 0 0x2262 1 0 2 rfu_value9 0 31 mmDC_COMBOPHYTXREGS1_TX_DISP_RFU10_LANE3 0 0x2263 1 0 2 rfu_value10 0 31 mmDC_COMBOPHYTXREGS1_TX_DISP_RFU11_LANE3 0 0x2264 1 0 2 rfu_value11 0 31 mmDC_COMBOPHYTXREGS1_TX_DISP_RFU12_LANE3 0 0x2265 1 0 2 rfu_value12 0 31 mmDC_COMBOPHYPLLREGS1_FREQ_CTRL0 0 0x2266 2 0 2 fcw0_frac 0 15 fcw0_int 16 24 mmDC_COMBOPHYPLLREGS1_FREQ_CTRL1 0 0x2267 2 0 2 fcw1_frac 0 15 fcw1_int 16 24 mmDC_COMBOPHYPLLREGS1_FREQ_CTRL2 0 0x2268 2 0 2 fcw_denom 0 15 fcw_slew_frac 16 31 mmDC_COMBOPHYPLLREGS1_FREQ_CTRL3 0 0x2269 8 0 2 refclk_div 0 1 vco_pre_div 3 4 fracn_en 6 6 ssc_en 8 8 fcw_sel 10 10 freq_jump_en 12 12 tdc_resolution 16 23 dpll_cfg_1 24 31 mmDC_COMBOPHYPLLREGS1_BW_CTRL_COARSE 0 0x226a 6 0 2 gi_coarse_mant 0 1 gi_coarse_exp 2 5 gp_coarse_mant 7 10 gp_coarse_exp 12 15 nctl_coarse_res 17 22 nctl_coarse_frac_res 24 25 mmDC_COMBOPHYPLLREGS1_BW_CTRL_FINE 0 0x226b 1 0 2 dpll_cfg_3 0 9 mmDC_COMBOPHYPLLREGS1_CAL_CTRL 0 0x226c 9 0 2 bypass_freq_lock 0 0 tdc_cal_en 1 1 tdc_cal_ctrl 3 8 meas_win_sel 9 10 kdco_cal_dis 11 11 kdco_ratio 13 20 kdco_incr_cal_dis 22 22 nctl_adj_dis 23 23 refclk_rate 24 31 mmDC_COMBOPHYPLLREGS1_LOOP_CTRL 0 0x226d 10 0 2 fbdiv_mask_en 0 0 fb_slip_dis 2 2 clk_tdc_sel 4 5 clk_nctl_sel 7 8 sig_del_patt_sel 10 10 nctl_sig_del_dis 12 12 fbclk_track_refclk 14 14 prbs_en 16 16 tdc_clk_gate_en 18 18 phase_offset 20 26 mmDC_COMBOPHYPLLREGS1_VREG_CFG 0 0x226f 14 0 2 bleeder_ac 0 0 bleeder_en 1 1 is_1p2 2 2 reg_obs_sel 3 4 reg_on_mode 5 6 rlad_tap_sel 7 10 reg_off_hi 11 11 reg_off_lo 12 12 scale_driver 13 14 sel_bump 15 15 sel_rladder_x 16 16 short_rc_filt_x 17 17 vref_pwr_on 18 18 dpll_cfg_2 20 27 mmDC_COMBOPHYPLLREGS1_OBSERVE0 0 0x2270 5 0 2 lock_det_tdc_steps 0 4 clear_sticky_lock 6 6 lock_det_dis 8 8 dco_cfg 10 17 anaobs_sel 21 23 mmDC_COMBOPHYPLLREGS1_OBSERVE1 0 0x2271 5 0 2 digobs_sel 0 3 digobs_trig_sel 5 8 digobs_div 10 11 digobs_trig_div 13 14 lock_timer 16 29 mmDC_COMBOPHYPLLREGS1_DFT_OUT 0 0x2272 1 0 2 dft_data 0 31 mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED0 0 0x22ce 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED1 0 0x22cf 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED2 0 0x22d0 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED3 0 0x22d1 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED4 0 0x22d2 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED5 0 0x22d3 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED6 0 0x22d4 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED7 0 0x22d5 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED8 0 0x22d6 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED9 0 0x22d7 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED10 0 0x22d8 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED11 0 0x22d9 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED12 0 0x22da 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED13 0 0x22db 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED14 0 0x22dc 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED15 0 0x22dd 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED16 0 0x22de 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED17 0 0x22df 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED18 0 0x22e0 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED19 0 0x22e1 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED20 0 0x22e2 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED21 0 0x22e3 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED22 0 0x22e4 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED23 0 0x22e5 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED24 0 0x22e6 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED25 0 0x22e7 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED26 0 0x22e8 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED27 0 0x22e9 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED28 0 0x22ea 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED29 0 0x22eb 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED30 0 0x22ec 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED31 0 0x22ed 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED32 0 0x22ee 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED33 0 0x22ef 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED34 0 0x22f0 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED35 0 0x22f1 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED36 0 0x22f2 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED37 0 0x22f3 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED38 0 0x22f4 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED39 0 0x22f5 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED40 0 0x22f6 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED41 0 0x22f7 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED42 0 0x22f8 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED43 0 0x22f9 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED44 0 0x22fa 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED45 0 0x22fb 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED46 0 0x22fc 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED47 0 0x22fd 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED48 0 0x22fe 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED49 0 0x22ff 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED50 0 0x2300 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED51 0 0x2301 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED52 0 0x2302 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED53 0 0x2303 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED54 0 0x2304 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED55 0 0x2305 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED56 0 0x2306 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED57 0 0x2307 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED58 0 0x2308 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED59 0 0x2309 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED60 0 0x230a 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED61 0 0x230b 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED62 0 0x230c 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED63 0 0x230d 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED64 0 0x230e 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED65 0 0x230f 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED66 0 0x2310 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED67 0 0x2311 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED68 0 0x2312 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED69 0 0x2313 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED70 0 0x2314 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED71 0 0x2315 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED72 0 0x2316 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED73 0 0x2317 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED74 0 0x2318 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED75 0 0x2319 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED76 0 0x231a 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED77 0 0x231b 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED78 0 0x231c 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED79 0 0x231d 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED80 0 0x231e 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED81 0 0x231f 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED82 0 0x2320 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED83 0 0x2321 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED84 0 0x2322 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED85 0 0x2323 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED86 0 0x2324 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED87 0 0x2325 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED88 0 0x2326 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED89 0 0x2327 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED90 0 0x2328 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED91 0 0x2329 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED92 0 0x232a 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED93 0 0x232b 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED94 0 0x232c 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED95 0 0x232d 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED96 0 0x232e 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED97 0 0x232f 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED98 0 0x2330 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED99 0 0x2331 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED100 0 0x2332 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED101 0 0x2333 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED102 0 0x2334 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED103 0 0x2335 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED104 0 0x2336 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED105 0 0x2337 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED106 0 0x2338 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED107 0 0x2339 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED108 0 0x233a 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED109 0 0x233b 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED110 0 0x233c 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED111 0 0x233d 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED112 0 0x233e 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED113 0 0x233f 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED114 0 0x2340 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED115 0 0x2341 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED116 0 0x2342 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED117 0 0x2343 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED118 0 0x2344 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED119 0 0x2345 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED120 0 0x2346 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED121 0 0x2347 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED122 0 0x2348 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED123 0 0x2349 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED124 0 0x234a 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED125 0 0x234b 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED126 0 0x234c 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED127 0 0x234d 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED128 0 0x234e 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED129 0 0x234f 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED130 0 0x2350 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED131 0 0x2351 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED132 0 0x2352 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED133 0 0x2353 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED134 0 0x2354 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED135 0 0x2355 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED136 0 0x2356 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED137 0 0x2357 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED138 0 0x2358 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED139 0 0x2359 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED140 0 0x235a 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED141 0 0x235b 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED142 0 0x235c 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED143 0 0x235d 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED144 0 0x235e 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED145 0 0x235f 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED146 0 0x2360 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED147 0 0x2361 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED148 0 0x2362 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED149 0 0x2363 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED150 0 0x2364 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED151 0 0x2365 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED152 0 0x2366 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED153 0 0x2367 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED154 0 0x2368 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED155 0 0x2369 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED156 0 0x236a 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED157 0 0x236b 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED158 0 0x236c 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED159 0 0x236d 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDC_COMBOPHYCMREGS2_COMMON_FUSE1 0 0x22ce 11 0 2 fuse1_valid 0 0 fuse1_unpopulated0 1 2 fuse1_ron_override_val 3 8 fuse1_unpopulated1 9 9 fuse1_ron_ctl 10 11 fuse1_unpopulated2 12 12 fuse1_rtt_override_val 13 18 fuse1_unpopulated3 19 19 fuse1_rtt_ctl 20 21 fuse1_refresh_cal_en 22 22 fuse1_spare 23 31 mmDC_COMBOPHYCMREGS2_COMMON_FUSE2 0 0x22cf 4 0 2 fuse2_valid 0 0 fuse2_unpopulated 1 8 fuse2_tx_fifo_ptr 9 13 fuse2_spare 14 31 mmDC_COMBOPHYCMREGS2_COMMON_FUSE3 0 0x22d0 4 0 2 fuse3_valid 0 0 fuse3_unpopulated 1 9 fuse3_ei_det_thresh_sel 10 12 fuse3_spare 29 31 mmDC_COMBOPHYCMREGS2_COMMON_MAR_DEEMPH_NOM 0 0x22d1 4 0 2 tx_margin_nom 0 7 deemph_gen1_nom 8 15 deemph35_gen2_nom 16 23 deemph60_gen2_nom 24 31 mmDC_COMBOPHYCMREGS2_COMMON_LANE_PWRMGMT 0 0x22d2 3 0 2 pgdelay 0 3 pgmask 4 9 vprot_en 11 11 mmDC_COMBOPHYCMREGS2_COMMON_TXCNTRL 0 0x22d3 7 0 2 rdptr_rst_val_gen3 0 4 clkgate_dis 5 5 slew_rate_ctl_gen1 6 8 slew_rate_ctl_gen2 9 11 slew_rate_ctl_gen3 12 14 dual_dvi_mstr_en 15 15 dual_dvi_en 16 16 mmDC_COMBOPHYCMREGS2_COMMON_TMDP 0 0x22d4 1 0 2 tmdp_spare 0 31 mmDC_COMBOPHYCMREGS2_COMMON_LANE_RESETS 0 0x22d5 8 0 2 lane_0_reset_l 0 0 lane_1_reset_l 1 1 lane_2_reset_l 2 2 lane_3_reset_l 3 3 lane_4_reset_l 4 4 lane_5_reset_l 5 5 lane_6_reset_l 6 6 lane_7_reset_l 7 7 mmDC_COMBOPHYCMREGS2_COMMON_ZCALCODE_CTRL 0 0x22d6 3 0 2 zcalcode_override 0 0 tx_binary_code_override_val 1 5 tx_driver_fifty_ohms 21 21 mmDC_COMBOPHYCMREGS2_COMMON_DISP_RFU1 0 0x22d7 1 0 2 rfu_value1 0 31 mmDC_COMBOPHYCMREGS2_COMMON_DISP_RFU2 0 0x22d8 1 0 2 rfu_value2 0 31 mmDC_COMBOPHYCMREGS2_COMMON_DISP_RFU3 0 0x22d9 1 0 2 rfu_value3 0 31 mmDC_COMBOPHYCMREGS2_COMMON_DISP_RFU4 0 0x22da 1 0 2 rfu_value4 0 31 mmDC_COMBOPHYCMREGS2_COMMON_DISP_RFU5 0 0x22db 1 0 2 rfu_value5 0 31 mmDC_COMBOPHYCMREGS2_COMMON_DISP_RFU6 0 0x22dc 1 0 2 rfu_value6 0 31 mmDC_COMBOPHYCMREGS2_COMMON_DISP_RFU7 0 0x22dd 1 0 2 rfu_value7 0 31 mmDC_COMBOPHYTXREGS2_CMD_BUS_TX_CONTROL_LANE0 0 0x22ee 3 0 2 tx_pwr 0 2 tx_pg_en 3 4 tx_rdy 8 8 mmDC_COMBOPHYTXREGS2_MARGIN_DEEMPH_LANE0 0 0x22ef 3 0 2 txmarg_sel 0 2 deemph_sel 3 4 tx_margin_en 5 5 mmDC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE0 0 0x22f0 12 0 2 twosym_en 1 2 link_speed 3 4 gang_mode 5 7 max_linkrate 8 9 pcs_freq 10 11 pcs_clken 12 12 pcs_clkdone 13 13 pll1_always_on 14 14 rdclk_div2_en 15 15 tx_boost_adj 16 19 tx_boost_en 20 20 tx_binary_ron_code_offset 22 23 mmDC_COMBOPHYTXREGS2_TX_DISP_RFU0_LANE0 0 0x22f1 1 0 2 rfu_value0 0 31 mmDC_COMBOPHYTXREGS2_TX_DISP_RFU1_LANE0 0 0x22f2 1 0 2 rfu_value1 0 31 mmDC_COMBOPHYTXREGS2_TX_DISP_RFU2_LANE0 0 0x22f3 1 0 2 rfu_value2 0 31 mmDC_COMBOPHYTXREGS2_TX_DISP_RFU3_LANE0 0 0x22f4 1 0 2 rfu_value3 0 31 mmDC_COMBOPHYTXREGS2_TX_DISP_RFU4_LANE0 0 0x22f5 1 0 2 rfu_value4 0 31 mmDC_COMBOPHYTXREGS2_TX_DISP_RFU5_LANE0 0 0x22f6 1 0 2 rfu_value5 0 31 mmDC_COMBOPHYTXREGS2_TX_DISP_RFU6_LANE0 0 0x22f7 1 0 2 rfu_value6 0 31 mmDC_COMBOPHYTXREGS2_TX_DISP_RFU7_LANE0 0 0x22f8 1 0 2 rfu_value7 0 31 mmDC_COMBOPHYTXREGS2_TX_DISP_RFU8_LANE0 0 0x22f9 1 0 2 rfu_value8 0 31 mmDC_COMBOPHYTXREGS2_TX_DISP_RFU9_LANE0 0 0x22fa 1 0 2 rfu_value9 0 31 mmDC_COMBOPHYTXREGS2_TX_DISP_RFU10_LANE0 0 0x22fb 1 0 2 rfu_value10 0 31 mmDC_COMBOPHYTXREGS2_TX_DISP_RFU11_LANE0 0 0x22fc 1 0 2 rfu_value11 0 31 mmDC_COMBOPHYTXREGS2_TX_DISP_RFU12_LANE0 0 0x22fd 1 0 2 rfu_value12 0 31 mmDC_COMBOPHYTXREGS2_CMD_BUS_TX_CONTROL_LANE1 0 0x22fe 3 0 2 tx_pwr 0 2 tx_pg_en 3 4 tx_rdy 8 8 mmDC_COMBOPHYTXREGS2_MARGIN_DEEMPH_LANE1 0 0x22ff 3 0 2 txmarg_sel 0 2 deemph_sel 3 4 tx_margin_en 5 5 mmDC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE1 0 0x2300 12 0 2 twosym_en 1 2 link_speed 3 4 gang_mode 5 7 max_linkrate 8 9 pcs_freq 10 11 pcs_clken 12 12 pcs_clkdone 13 13 pll1_always_on 14 14 rdclk_div2_en 15 15 tx_boost_adj 16 19 tx_boost_en 20 20 tx_binary_ron_code_offset 22 23 mmDC_COMBOPHYTXREGS2_TX_DISP_RFU0_LANE1 0 0x2301 1 0 2 rfu_value0 0 31 mmDC_COMBOPHYTXREGS2_TX_DISP_RFU1_LANE1 0 0x2302 1 0 2 rfu_value1 0 31 mmDC_COMBOPHYTXREGS2_TX_DISP_RFU2_LANE1 0 0x2303 1 0 2 rfu_value2 0 31 mmDC_COMBOPHYTXREGS2_TX_DISP_RFU3_LANE1 0 0x2304 1 0 2 rfu_value3 0 31 mmDC_COMBOPHYTXREGS2_TX_DISP_RFU4_LANE1 0 0x2305 1 0 2 rfu_value4 0 31 mmDC_COMBOPHYTXREGS2_TX_DISP_RFU5_LANE1 0 0x2306 1 0 2 rfu_value5 0 31 mmDC_COMBOPHYTXREGS2_TX_DISP_RFU6_LANE1 0 0x2307 1 0 2 rfu_value6 0 31 mmDC_COMBOPHYTXREGS2_TX_DISP_RFU7_LANE1 0 0x2308 1 0 2 rfu_value7 0 31 mmDC_COMBOPHYTXREGS2_TX_DISP_RFU8_LANE1 0 0x2309 1 0 2 rfu_value8 0 31 mmDC_COMBOPHYTXREGS2_TX_DISP_RFU9_LANE1 0 0x230a 1 0 2 rfu_value9 0 31 mmDC_COMBOPHYTXREGS2_TX_DISP_RFU10_LANE1 0 0x230b 1 0 2 rfu_value10 0 31 mmDC_COMBOPHYTXREGS2_TX_DISP_RFU11_LANE1 0 0x230c 1 0 2 rfu_value11 0 31 mmDC_COMBOPHYTXREGS2_TX_DISP_RFU12_LANE1 0 0x230d 1 0 2 rfu_value12 0 31 mmDC_COMBOPHYTXREGS2_CMD_BUS_TX_CONTROL_LANE2 0 0x230e 3 0 2 tx_pwr 0 2 tx_pg_en 3 4 tx_rdy 8 8 mmDC_COMBOPHYTXREGS2_MARGIN_DEEMPH_LANE2 0 0x230f 3 0 2 txmarg_sel 0 2 deemph_sel 3 4 tx_margin_en 5 5 mmDC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE2 0 0x2310 12 0 2 twosym_en 1 2 link_speed 3 4 gang_mode 5 7 max_linkrate 8 9 pcs_freq 10 11 pcs_clken 12 12 pcs_clkdone 13 13 pll1_always_on 14 14 rdclk_div2_en 15 15 tx_boost_adj 16 19 tx_boost_en 20 20 tx_binary_ron_code_offset 22 23 mmDC_COMBOPHYTXREGS2_TX_DISP_RFU0_LANE2 0 0x2311 1 0 2 rfu_value0 0 31 mmDC_COMBOPHYTXREGS2_TX_DISP_RFU1_LANE2 0 0x2312 1 0 2 rfu_value1 0 31 mmDC_COMBOPHYTXREGS2_TX_DISP_RFU2_LANE2 0 0x2313 1 0 2 rfu_value2 0 31 mmDC_COMBOPHYTXREGS2_TX_DISP_RFU3_LANE2 0 0x2314 1 0 2 rfu_value3 0 31 mmDC_COMBOPHYTXREGS2_TX_DISP_RFU4_LANE2 0 0x2315 1 0 2 rfu_value4 0 31 mmDC_COMBOPHYTXREGS2_TX_DISP_RFU5_LANE2 0 0x2316 1 0 2 rfu_value5 0 31 mmDC_COMBOPHYTXREGS2_TX_DISP_RFU6_LANE2 0 0x2317 1 0 2 rfu_value6 0 31 mmDC_COMBOPHYTXREGS2_TX_DISP_RFU7_LANE2 0 0x2318 1 0 2 rfu_value7 0 31 mmDC_COMBOPHYTXREGS2_TX_DISP_RFU8_LANE2 0 0x2319 1 0 2 rfu_value8 0 31 mmDC_COMBOPHYTXREGS2_TX_DISP_RFU9_LANE2 0 0x231a 1 0 2 rfu_value9 0 31 mmDC_COMBOPHYTXREGS2_TX_DISP_RFU10_LANE2 0 0x231b 1 0 2 rfu_value10 0 31 mmDC_COMBOPHYTXREGS2_TX_DISP_RFU11_LANE2 0 0x231c 1 0 2 rfu_value11 0 31 mmDC_COMBOPHYTXREGS2_TX_DISP_RFU12_LANE2 0 0x231d 1 0 2 rfu_value12 0 31 mmDC_COMBOPHYTXREGS2_CMD_BUS_TX_CONTROL_LANE3 0 0x231e 3 0 2 tx_pwr 0 2 tx_pg_en 3 4 tx_rdy 8 8 mmDC_COMBOPHYTXREGS2_MARGIN_DEEMPH_LANE3 0 0x231f 3 0 2 txmarg_sel 0 2 deemph_sel 3 4 tx_margin_en 5 5 mmDC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE3 0 0x2320 12 0 2 twosym_en 1 2 link_speed 3 4 gang_mode 5 7 max_linkrate 8 9 pcs_freq 10 11 pcs_clken 12 12 pcs_clkdone 13 13 pll1_always_on 14 14 rdclk_div2_en 15 15 tx_boost_adj 16 19 tx_boost_en 20 20 tx_binary_ron_code_offset 22 23 mmDC_COMBOPHYTXREGS2_TX_DISP_RFU0_LANE3 0 0x2321 1 0 2 rfu_value0 0 31 mmDC_COMBOPHYTXREGS2_TX_DISP_RFU1_LANE3 0 0x2322 1 0 2 rfu_value1 0 31 mmDC_COMBOPHYTXREGS2_TX_DISP_RFU2_LANE3 0 0x2323 1 0 2 rfu_value2 0 31 mmDC_COMBOPHYTXREGS2_TX_DISP_RFU3_LANE3 0 0x2324 1 0 2 rfu_value3 0 31 mmDC_COMBOPHYTXREGS2_TX_DISP_RFU4_LANE3 0 0x2325 1 0 2 rfu_value4 0 31 mmDC_COMBOPHYTXREGS2_TX_DISP_RFU5_LANE3 0 0x2326 1 0 2 rfu_value5 0 31 mmDC_COMBOPHYTXREGS2_TX_DISP_RFU6_LANE3 0 0x2327 1 0 2 rfu_value6 0 31 mmDC_COMBOPHYTXREGS2_TX_DISP_RFU7_LANE3 0 0x2328 1 0 2 rfu_value7 0 31 mmDC_COMBOPHYTXREGS2_TX_DISP_RFU8_LANE3 0 0x2329 1 0 2 rfu_value8 0 31 mmDC_COMBOPHYTXREGS2_TX_DISP_RFU9_LANE3 0 0x232a 1 0 2 rfu_value9 0 31 mmDC_COMBOPHYTXREGS2_TX_DISP_RFU10_LANE3 0 0x232b 1 0 2 rfu_value10 0 31 mmDC_COMBOPHYTXREGS2_TX_DISP_RFU11_LANE3 0 0x232c 1 0 2 rfu_value11 0 31 mmDC_COMBOPHYTXREGS2_TX_DISP_RFU12_LANE3 0 0x232d 1 0 2 rfu_value12 0 31 mmDC_COMBOPHYPLLREGS2_FREQ_CTRL0 0 0x232e 2 0 2 fcw0_frac 0 15 fcw0_int 16 24 mmDC_COMBOPHYPLLREGS2_FREQ_CTRL1 0 0x232f 2 0 2 fcw1_frac 0 15 fcw1_int 16 24 mmDC_COMBOPHYPLLREGS2_FREQ_CTRL2 0 0x2330 2 0 2 fcw_denom 0 15 fcw_slew_frac 16 31 mmDC_COMBOPHYPLLREGS2_FREQ_CTRL3 0 0x2331 8 0 2 refclk_div 0 1 vco_pre_div 3 4 fracn_en 6 6 ssc_en 8 8 fcw_sel 10 10 freq_jump_en 12 12 tdc_resolution 16 23 dpll_cfg_1 24 31 mmDC_COMBOPHYPLLREGS2_BW_CTRL_COARSE 0 0x2332 6 0 2 gi_coarse_mant 0 1 gi_coarse_exp 2 5 gp_coarse_mant 7 10 gp_coarse_exp 12 15 nctl_coarse_res 17 22 nctl_coarse_frac_res 24 25 mmDC_COMBOPHYPLLREGS2_BW_CTRL_FINE 0 0x2333 1 0 2 dpll_cfg_3 0 9 mmDC_COMBOPHYPLLREGS2_CAL_CTRL 0 0x2334 9 0 2 bypass_freq_lock 0 0 tdc_cal_en 1 1 tdc_cal_ctrl 3 8 meas_win_sel 9 10 kdco_cal_dis 11 11 kdco_ratio 13 20 kdco_incr_cal_dis 22 22 nctl_adj_dis 23 23 refclk_rate 24 31 mmDC_COMBOPHYPLLREGS2_LOOP_CTRL 0 0x2335 10 0 2 fbdiv_mask_en 0 0 fb_slip_dis 2 2 clk_tdc_sel 4 5 clk_nctl_sel 7 8 sig_del_patt_sel 10 10 nctl_sig_del_dis 12 12 fbclk_track_refclk 14 14 prbs_en 16 16 tdc_clk_gate_en 18 18 phase_offset 20 26 mmDC_COMBOPHYPLLREGS2_VREG_CFG 0 0x2337 14 0 2 bleeder_ac 0 0 bleeder_en 1 1 is_1p2 2 2 reg_obs_sel 3 4 reg_on_mode 5 6 rlad_tap_sel 7 10 reg_off_hi 11 11 reg_off_lo 12 12 scale_driver 13 14 sel_bump 15 15 sel_rladder_x 16 16 short_rc_filt_x 17 17 vref_pwr_on 18 18 dpll_cfg_2 20 27 mmDC_COMBOPHYPLLREGS2_OBSERVE0 0 0x2338 5 0 2 lock_det_tdc_steps 0 4 clear_sticky_lock 6 6 lock_det_dis 8 8 dco_cfg 10 17 anaobs_sel 21 23 mmDC_COMBOPHYPLLREGS2_OBSERVE1 0 0x2339 5 0 2 digobs_sel 0 3 digobs_trig_sel 5 8 digobs_div 10 11 digobs_trig_div 13 14 lock_timer 16 29 mmDC_COMBOPHYPLLREGS2_DFT_OUT 0 0x233a 1 0 2 dft_data 0 31 mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED0 0 0x2396 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED1 0 0x2397 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED2 0 0x2398 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED3 0 0x2399 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED4 0 0x239a 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED5 0 0x239b 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED6 0 0x239c 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED7 0 0x239d 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED8 0 0x239e 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED9 0 0x239f 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED10 0 0x23a0 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED11 0 0x23a1 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED12 0 0x23a2 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED13 0 0x23a3 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED14 0 0x23a4 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED15 0 0x23a5 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED16 0 0x23a6 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED17 0 0x23a7 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED18 0 0x23a8 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED19 0 0x23a9 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED20 0 0x23aa 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED21 0 0x23ab 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED22 0 0x23ac 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED23 0 0x23ad 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED24 0 0x23ae 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED25 0 0x23af 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED26 0 0x23b0 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED27 0 0x23b1 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED28 0 0x23b2 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED29 0 0x23b3 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED30 0 0x23b4 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED31 0 0x23b5 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED32 0 0x23b6 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED33 0 0x23b7 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED34 0 0x23b8 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED35 0 0x23b9 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED36 0 0x23ba 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED37 0 0x23bb 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED38 0 0x23bc 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED39 0 0x23bd 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED40 0 0x23be 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED41 0 0x23bf 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED42 0 0x23c0 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED43 0 0x23c1 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED44 0 0x23c2 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED45 0 0x23c3 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED46 0 0x23c4 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED47 0 0x23c5 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED48 0 0x23c6 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED49 0 0x23c7 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED50 0 0x23c8 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED51 0 0x23c9 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED52 0 0x23ca 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED53 0 0x23cb 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED54 0 0x23cc 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED55 0 0x23cd 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED56 0 0x23ce 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED57 0 0x23cf 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED58 0 0x23d0 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED59 0 0x23d1 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED60 0 0x23d2 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED61 0 0x23d3 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED62 0 0x23d4 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED63 0 0x23d5 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED64 0 0x23d6 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED65 0 0x23d7 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED66 0 0x23d8 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED67 0 0x23d9 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED68 0 0x23da 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED69 0 0x23db 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED70 0 0x23dc 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED71 0 0x23dd 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED72 0 0x23de 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED73 0 0x23df 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED74 0 0x23e0 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED75 0 0x23e1 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED76 0 0x23e2 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED77 0 0x23e3 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED78 0 0x23e4 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED79 0 0x23e5 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED80 0 0x23e6 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED81 0 0x23e7 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED82 0 0x23e8 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED83 0 0x23e9 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED84 0 0x23ea 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED85 0 0x23eb 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED86 0 0x23ec 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED87 0 0x23ed 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED88 0 0x23ee 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED89 0 0x23ef 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED90 0 0x23f0 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED91 0 0x23f1 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED92 0 0x23f2 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED93 0 0x23f3 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED94 0 0x23f4 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED95 0 0x23f5 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED96 0 0x23f6 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED97 0 0x23f7 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED98 0 0x23f8 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED99 0 0x23f9 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED100 0 0x23fa 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED101 0 0x23fb 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED102 0 0x23fc 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED103 0 0x23fd 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED104 0 0x23fe 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED105 0 0x23ff 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED106 0 0x2400 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED107 0 0x2401 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED108 0 0x2402 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED109 0 0x2403 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED110 0 0x2404 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED111 0 0x2405 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED112 0 0x2406 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED113 0 0x2407 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED114 0 0x2408 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED115 0 0x2409 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED116 0 0x240a 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED117 0 0x240b 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED118 0 0x240c 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED119 0 0x240d 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED120 0 0x240e 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED121 0 0x240f 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED122 0 0x2410 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED123 0 0x2411 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED124 0 0x2412 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED125 0 0x2413 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED126 0 0x2414 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED127 0 0x2415 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED128 0 0x2416 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED129 0 0x2417 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED130 0 0x2418 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED131 0 0x2419 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED132 0 0x241a 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED133 0 0x241b 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED134 0 0x241c 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED135 0 0x241d 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED136 0 0x241e 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED137 0 0x241f 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED138 0 0x2420 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED139 0 0x2421 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED140 0 0x2422 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED141 0 0x2423 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED142 0 0x2424 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED143 0 0x2425 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED144 0 0x2426 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED145 0 0x2427 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED146 0 0x2428 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED147 0 0x2429 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED148 0 0x242a 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED149 0 0x242b 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED150 0 0x242c 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED151 0 0x242d 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED152 0 0x242e 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED153 0 0x242f 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED154 0 0x2430 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED155 0 0x2431 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED156 0 0x2432 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED157 0 0x2433 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED158 0 0x2434 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED159 0 0x2435 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDC_COMBOPHYCMREGS3_COMMON_FUSE1 0 0x2396 11 0 2 fuse1_valid 0 0 fuse1_unpopulated0 1 2 fuse1_ron_override_val 3 8 fuse1_unpopulated1 9 9 fuse1_ron_ctl 10 11 fuse1_unpopulated2 12 12 fuse1_rtt_override_val 13 18 fuse1_unpopulated3 19 19 fuse1_rtt_ctl 20 21 fuse1_refresh_cal_en 22 22 fuse1_spare 23 31 mmDC_COMBOPHYCMREGS3_COMMON_FUSE2 0 0x2397 4 0 2 fuse2_valid 0 0 fuse2_unpopulated 1 8 fuse2_tx_fifo_ptr 9 13 fuse2_spare 14 31 mmDC_COMBOPHYCMREGS3_COMMON_FUSE3 0 0x2398 4 0 2 fuse3_valid 0 0 fuse3_unpopulated 1 9 fuse3_ei_det_thresh_sel 10 12 fuse3_spare 29 31 mmDC_COMBOPHYCMREGS3_COMMON_MAR_DEEMPH_NOM 0 0x2399 4 0 2 tx_margin_nom 0 7 deemph_gen1_nom 8 15 deemph35_gen2_nom 16 23 deemph60_gen2_nom 24 31 mmDC_COMBOPHYCMREGS3_COMMON_LANE_PWRMGMT 0 0x239a 3 0 2 pgdelay 0 3 pgmask 4 9 vprot_en 11 11 mmDC_COMBOPHYCMREGS3_COMMON_TXCNTRL 0 0x239b 7 0 2 rdptr_rst_val_gen3 0 4 clkgate_dis 5 5 slew_rate_ctl_gen1 6 8 slew_rate_ctl_gen2 9 11 slew_rate_ctl_gen3 12 14 dual_dvi_mstr_en 15 15 dual_dvi_en 16 16 mmDC_COMBOPHYCMREGS3_COMMON_TMDP 0 0x239c 1 0 2 tmdp_spare 0 31 mmDC_COMBOPHYCMREGS3_COMMON_LANE_RESETS 0 0x239d 8 0 2 lane_0_reset_l 0 0 lane_1_reset_l 1 1 lane_2_reset_l 2 2 lane_3_reset_l 3 3 lane_4_reset_l 4 4 lane_5_reset_l 5 5 lane_6_reset_l 6 6 lane_7_reset_l 7 7 mmDC_COMBOPHYCMREGS3_COMMON_ZCALCODE_CTRL 0 0x239e 3 0 2 zcalcode_override 0 0 tx_binary_code_override_val 1 5 tx_driver_fifty_ohms 21 21 mmDC_COMBOPHYCMREGS3_COMMON_DISP_RFU1 0 0x239f 1 0 2 rfu_value1 0 31 mmDC_COMBOPHYCMREGS3_COMMON_DISP_RFU2 0 0x23a0 1 0 2 rfu_value2 0 31 mmDC_COMBOPHYCMREGS3_COMMON_DISP_RFU3 0 0x23a1 1 0 2 rfu_value3 0 31 mmDC_COMBOPHYCMREGS3_COMMON_DISP_RFU4 0 0x23a2 1 0 2 rfu_value4 0 31 mmDC_COMBOPHYCMREGS3_COMMON_DISP_RFU5 0 0x23a3 1 0 2 rfu_value5 0 31 mmDC_COMBOPHYCMREGS3_COMMON_DISP_RFU6 0 0x23a4 1 0 2 rfu_value6 0 31 mmDC_COMBOPHYCMREGS3_COMMON_DISP_RFU7 0 0x23a5 1 0 2 rfu_value7 0 31 mmDC_COMBOPHYTXREGS3_CMD_BUS_TX_CONTROL_LANE0 0 0x23b6 3 0 2 tx_pwr 0 2 tx_pg_en 3 4 tx_rdy 8 8 mmDC_COMBOPHYTXREGS3_MARGIN_DEEMPH_LANE0 0 0x23b7 3 0 2 txmarg_sel 0 2 deemph_sel 3 4 tx_margin_en 5 5 mmDC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE0 0 0x23b8 12 0 2 twosym_en 1 2 link_speed 3 4 gang_mode 5 7 max_linkrate 8 9 pcs_freq 10 11 pcs_clken 12 12 pcs_clkdone 13 13 pll1_always_on 14 14 rdclk_div2_en 15 15 tx_boost_adj 16 19 tx_boost_en 20 20 tx_binary_ron_code_offset 22 23 mmDC_COMBOPHYTXREGS3_TX_DISP_RFU0_LANE0 0 0x23b9 1 0 2 rfu_value0 0 31 mmDC_COMBOPHYTXREGS3_TX_DISP_RFU1_LANE0 0 0x23ba 1 0 2 rfu_value1 0 31 mmDC_COMBOPHYTXREGS3_TX_DISP_RFU2_LANE0 0 0x23bb 1 0 2 rfu_value2 0 31 mmDC_COMBOPHYTXREGS3_TX_DISP_RFU3_LANE0 0 0x23bc 1 0 2 rfu_value3 0 31 mmDC_COMBOPHYTXREGS3_TX_DISP_RFU4_LANE0 0 0x23bd 1 0 2 rfu_value4 0 31 mmDC_COMBOPHYTXREGS3_TX_DISP_RFU5_LANE0 0 0x23be 1 0 2 rfu_value5 0 31 mmDC_COMBOPHYTXREGS3_TX_DISP_RFU6_LANE0 0 0x23bf 1 0 2 rfu_value6 0 31 mmDC_COMBOPHYTXREGS3_TX_DISP_RFU7_LANE0 0 0x23c0 1 0 2 rfu_value7 0 31 mmDC_COMBOPHYTXREGS3_TX_DISP_RFU8_LANE0 0 0x23c1 1 0 2 rfu_value8 0 31 mmDC_COMBOPHYTXREGS3_TX_DISP_RFU9_LANE0 0 0x23c2 1 0 2 rfu_value9 0 31 mmDC_COMBOPHYTXREGS3_TX_DISP_RFU10_LANE0 0 0x23c3 1 0 2 rfu_value10 0 31 mmDC_COMBOPHYTXREGS3_TX_DISP_RFU11_LANE0 0 0x23c4 1 0 2 rfu_value11 0 31 mmDC_COMBOPHYTXREGS3_TX_DISP_RFU12_LANE0 0 0x23c5 1 0 2 rfu_value12 0 31 mmDC_COMBOPHYTXREGS3_CMD_BUS_TX_CONTROL_LANE1 0 0x23c6 3 0 2 tx_pwr 0 2 tx_pg_en 3 4 tx_rdy 8 8 mmDC_COMBOPHYTXREGS3_MARGIN_DEEMPH_LANE1 0 0x23c7 3 0 2 txmarg_sel 0 2 deemph_sel 3 4 tx_margin_en 5 5 mmDC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE1 0 0x23c8 12 0 2 twosym_en 1 2 link_speed 3 4 gang_mode 5 7 max_linkrate 8 9 pcs_freq 10 11 pcs_clken 12 12 pcs_clkdone 13 13 pll1_always_on 14 14 rdclk_div2_en 15 15 tx_boost_adj 16 19 tx_boost_en 20 20 tx_binary_ron_code_offset 22 23 mmDC_COMBOPHYTXREGS3_TX_DISP_RFU0_LANE1 0 0x23c9 1 0 2 rfu_value0 0 31 mmDC_COMBOPHYTXREGS3_TX_DISP_RFU1_LANE1 0 0x23ca 1 0 2 rfu_value1 0 31 mmDC_COMBOPHYTXREGS3_TX_DISP_RFU2_LANE1 0 0x23cb 1 0 2 rfu_value2 0 31 mmDC_COMBOPHYTXREGS3_TX_DISP_RFU3_LANE1 0 0x23cc 1 0 2 rfu_value3 0 31 mmDC_COMBOPHYTXREGS3_TX_DISP_RFU4_LANE1 0 0x23cd 1 0 2 rfu_value4 0 31 mmDC_COMBOPHYTXREGS3_TX_DISP_RFU5_LANE1 0 0x23ce 1 0 2 rfu_value5 0 31 mmDC_COMBOPHYTXREGS3_TX_DISP_RFU6_LANE1 0 0x23cf 1 0 2 rfu_value6 0 31 mmDC_COMBOPHYTXREGS3_TX_DISP_RFU7_LANE1 0 0x23d0 1 0 2 rfu_value7 0 31 mmDC_COMBOPHYTXREGS3_TX_DISP_RFU8_LANE1 0 0x23d1 1 0 2 rfu_value8 0 31 mmDC_COMBOPHYTXREGS3_TX_DISP_RFU9_LANE1 0 0x23d2 1 0 2 rfu_value9 0 31 mmDC_COMBOPHYTXREGS3_TX_DISP_RFU10_LANE1 0 0x23d3 1 0 2 rfu_value10 0 31 mmDC_COMBOPHYTXREGS3_TX_DISP_RFU11_LANE1 0 0x23d4 1 0 2 rfu_value11 0 31 mmDC_COMBOPHYTXREGS3_TX_DISP_RFU12_LANE1 0 0x23d5 1 0 2 rfu_value12 0 31 mmDC_COMBOPHYTXREGS3_CMD_BUS_TX_CONTROL_LANE2 0 0x23d6 3 0 2 tx_pwr 0 2 tx_pg_en 3 4 tx_rdy 8 8 mmDC_COMBOPHYTXREGS3_MARGIN_DEEMPH_LANE2 0 0x23d7 3 0 2 txmarg_sel 0 2 deemph_sel 3 4 tx_margin_en 5 5 mmDC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE2 0 0x23d8 12 0 2 twosym_en 1 2 link_speed 3 4 gang_mode 5 7 max_linkrate 8 9 pcs_freq 10 11 pcs_clken 12 12 pcs_clkdone 13 13 pll1_always_on 14 14 rdclk_div2_en 15 15 tx_boost_adj 16 19 tx_boost_en 20 20 tx_binary_ron_code_offset 22 23 mmDC_COMBOPHYTXREGS3_TX_DISP_RFU0_LANE2 0 0x23d9 1 0 2 rfu_value0 0 31 mmDC_COMBOPHYTXREGS3_TX_DISP_RFU1_LANE2 0 0x23da 1 0 2 rfu_value1 0 31 mmDC_COMBOPHYTXREGS3_TX_DISP_RFU2_LANE2 0 0x23db 1 0 2 rfu_value2 0 31 mmDC_COMBOPHYTXREGS3_TX_DISP_RFU3_LANE2 0 0x23dc 1 0 2 rfu_value3 0 31 mmDC_COMBOPHYTXREGS3_TX_DISP_RFU4_LANE2 0 0x23dd 1 0 2 rfu_value4 0 31 mmDC_COMBOPHYTXREGS3_TX_DISP_RFU5_LANE2 0 0x23de 1 0 2 rfu_value5 0 31 mmDC_COMBOPHYTXREGS3_TX_DISP_RFU6_LANE2 0 0x23df 1 0 2 rfu_value6 0 31 mmDC_COMBOPHYTXREGS3_TX_DISP_RFU7_LANE2 0 0x23e0 1 0 2 rfu_value7 0 31 mmDC_COMBOPHYTXREGS3_TX_DISP_RFU8_LANE2 0 0x23e1 1 0 2 rfu_value8 0 31 mmDC_COMBOPHYTXREGS3_TX_DISP_RFU9_LANE2 0 0x23e2 1 0 2 rfu_value9 0 31 mmDC_COMBOPHYTXREGS3_TX_DISP_RFU10_LANE2 0 0x23e3 1 0 2 rfu_value10 0 31 mmDC_COMBOPHYTXREGS3_TX_DISP_RFU11_LANE2 0 0x23e4 1 0 2 rfu_value11 0 31 mmDC_COMBOPHYTXREGS3_TX_DISP_RFU12_LANE2 0 0x23e5 1 0 2 rfu_value12 0 31 mmDC_COMBOPHYTXREGS3_CMD_BUS_TX_CONTROL_LANE3 0 0x23e6 3 0 2 tx_pwr 0 2 tx_pg_en 3 4 tx_rdy 8 8 mmDC_COMBOPHYTXREGS3_MARGIN_DEEMPH_LANE3 0 0x23e7 3 0 2 txmarg_sel 0 2 deemph_sel 3 4 tx_margin_en 5 5 mmDC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE3 0 0x23e8 12 0 2 twosym_en 1 2 link_speed 3 4 gang_mode 5 7 max_linkrate 8 9 pcs_freq 10 11 pcs_clken 12 12 pcs_clkdone 13 13 pll1_always_on 14 14 rdclk_div2_en 15 15 tx_boost_adj 16 19 tx_boost_en 20 20 tx_binary_ron_code_offset 22 23 mmDC_COMBOPHYTXREGS3_TX_DISP_RFU0_LANE3 0 0x23e9 1 0 2 rfu_value0 0 31 mmDC_COMBOPHYTXREGS3_TX_DISP_RFU1_LANE3 0 0x23ea 1 0 2 rfu_value1 0 31 mmDC_COMBOPHYTXREGS3_TX_DISP_RFU2_LANE3 0 0x23eb 1 0 2 rfu_value2 0 31 mmDC_COMBOPHYTXREGS3_TX_DISP_RFU3_LANE3 0 0x23ec 1 0 2 rfu_value3 0 31 mmDC_COMBOPHYTXREGS3_TX_DISP_RFU4_LANE3 0 0x23ed 1 0 2 rfu_value4 0 31 mmDC_COMBOPHYTXREGS3_TX_DISP_RFU5_LANE3 0 0x23ee 1 0 2 rfu_value5 0 31 mmDC_COMBOPHYTXREGS3_TX_DISP_RFU6_LANE3 0 0x23ef 1 0 2 rfu_value6 0 31 mmDC_COMBOPHYTXREGS3_TX_DISP_RFU7_LANE3 0 0x23f0 1 0 2 rfu_value7 0 31 mmDC_COMBOPHYTXREGS3_TX_DISP_RFU8_LANE3 0 0x23f1 1 0 2 rfu_value8 0 31 mmDC_COMBOPHYTXREGS3_TX_DISP_RFU9_LANE3 0 0x23f2 1 0 2 rfu_value9 0 31 mmDC_COMBOPHYTXREGS3_TX_DISP_RFU10_LANE3 0 0x23f3 1 0 2 rfu_value10 0 31 mmDC_COMBOPHYTXREGS3_TX_DISP_RFU11_LANE3 0 0x23f4 1 0 2 rfu_value11 0 31 mmDC_COMBOPHYTXREGS3_TX_DISP_RFU12_LANE3 0 0x23f5 1 0 2 rfu_value12 0 31 mmDC_COMBOPHYPLLREGS3_FREQ_CTRL0 0 0x23f6 2 0 2 fcw0_frac 0 15 fcw0_int 16 24 mmDC_COMBOPHYPLLREGS3_FREQ_CTRL1 0 0x23f7 2 0 2 fcw1_frac 0 15 fcw1_int 16 24 mmDC_COMBOPHYPLLREGS3_FREQ_CTRL2 0 0x23f8 2 0 2 fcw_denom 0 15 fcw_slew_frac 16 31 mmDC_COMBOPHYPLLREGS3_FREQ_CTRL3 0 0x23f9 8 0 2 refclk_div 0 1 vco_pre_div 3 4 fracn_en 6 6 ssc_en 8 8 fcw_sel 10 10 freq_jump_en 12 12 tdc_resolution 16 23 dpll_cfg_1 24 31 mmDC_COMBOPHYPLLREGS3_BW_CTRL_COARSE 0 0x23fa 6 0 2 gi_coarse_mant 0 1 gi_coarse_exp 2 5 gp_coarse_mant 7 10 gp_coarse_exp 12 15 nctl_coarse_res 17 22 nctl_coarse_frac_res 24 25 mmDC_COMBOPHYPLLREGS3_BW_CTRL_FINE 0 0x23fb 1 0 2 dpll_cfg_3 0 9 mmDC_COMBOPHYPLLREGS3_CAL_CTRL 0 0x23fc 9 0 2 bypass_freq_lock 0 0 tdc_cal_en 1 1 tdc_cal_ctrl 3 8 meas_win_sel 9 10 kdco_cal_dis 11 11 kdco_ratio 13 20 kdco_incr_cal_dis 22 22 nctl_adj_dis 23 23 refclk_rate 24 31 mmDC_COMBOPHYPLLREGS3_LOOP_CTRL 0 0x23fd 10 0 2 fbdiv_mask_en 0 0 fb_slip_dis 2 2 clk_tdc_sel 4 5 clk_nctl_sel 7 8 sig_del_patt_sel 10 10 nctl_sig_del_dis 12 12 fbclk_track_refclk 14 14 prbs_en 16 16 tdc_clk_gate_en 18 18 phase_offset 20 26 mmDC_COMBOPHYPLLREGS3_VREG_CFG 0 0x23ff 14 0 2 bleeder_ac 0 0 bleeder_en 1 1 is_1p2 2 2 reg_obs_sel 3 4 reg_on_mode 5 6 rlad_tap_sel 7 10 reg_off_hi 11 11 reg_off_lo 12 12 scale_driver 13 14 sel_bump 15 15 sel_rladder_x 16 16 short_rc_filt_x 17 17 vref_pwr_on 18 18 dpll_cfg_2 20 27 mmDC_COMBOPHYPLLREGS3_OBSERVE0 0 0x2400 5 0 2 lock_det_tdc_steps 0 4 clear_sticky_lock 6 6 lock_det_dis 8 8 dco_cfg 10 17 anaobs_sel 21 23 mmDC_COMBOPHYPLLREGS3_OBSERVE1 0 0x2401 5 0 2 digobs_sel 0 3 digobs_trig_sel 5 8 digobs_div 10 11 digobs_trig_div 13 14 lock_timer 16 29 mmDC_COMBOPHYPLLREGS3_DFT_OUT 0 0x2402 1 0 2 dft_data 0 31 mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED0 0 0x245e 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED1 0 0x245f 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED2 0 0x2460 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED3 0 0x2461 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED4 0 0x2462 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED5 0 0x2463 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED6 0 0x2464 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED7 0 0x2465 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED8 0 0x2466 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED9 0 0x2467 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED10 0 0x2468 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED11 0 0x2469 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED12 0 0x246a 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED13 0 0x246b 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED14 0 0x246c 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED15 0 0x246d 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED16 0 0x246e 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED17 0 0x246f 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED18 0 0x2470 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED19 0 0x2471 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED20 0 0x2472 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED21 0 0x2473 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED22 0 0x2474 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED23 0 0x2475 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED24 0 0x2476 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED25 0 0x2477 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED26 0 0x2478 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED27 0 0x2479 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED28 0 0x247a 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED29 0 0x247b 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED30 0 0x247c 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED31 0 0x247d 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED32 0 0x247e 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED33 0 0x247f 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED34 0 0x2480 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED35 0 0x2481 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED36 0 0x2482 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED37 0 0x2483 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED38 0 0x2484 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED39 0 0x2485 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED40 0 0x2486 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED41 0 0x2487 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED42 0 0x2488 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED43 0 0x2489 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED44 0 0x248a 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED45 0 0x248b 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED46 0 0x248c 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED47 0 0x248d 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED48 0 0x248e 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED49 0 0x248f 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED50 0 0x2490 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED51 0 0x2491 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED52 0 0x2492 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED53 0 0x2493 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED54 0 0x2494 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED55 0 0x2495 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED56 0 0x2496 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED57 0 0x2497 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED58 0 0x2498 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED59 0 0x2499 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED60 0 0x249a 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED61 0 0x249b 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED62 0 0x249c 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED63 0 0x249d 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED64 0 0x249e 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED65 0 0x249f 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED66 0 0x24a0 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED67 0 0x24a1 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED68 0 0x24a2 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED69 0 0x24a3 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED70 0 0x24a4 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED71 0 0x24a5 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED72 0 0x24a6 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED73 0 0x24a7 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED74 0 0x24a8 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED75 0 0x24a9 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED76 0 0x24aa 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED77 0 0x24ab 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED78 0 0x24ac 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED79 0 0x24ad 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED80 0 0x24ae 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED81 0 0x24af 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED82 0 0x24b0 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED83 0 0x24b1 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED84 0 0x24b2 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED85 0 0x24b3 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED86 0 0x24b4 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED87 0 0x24b5 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED88 0 0x24b6 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED89 0 0x24b7 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED90 0 0x24b8 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED91 0 0x24b9 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED92 0 0x24ba 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED93 0 0x24bb 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED94 0 0x24bc 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED95 0 0x24bd 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED96 0 0x24be 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED97 0 0x24bf 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED98 0 0x24c0 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED99 0 0x24c1 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED100 0 0x24c2 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED101 0 0x24c3 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED102 0 0x24c4 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED103 0 0x24c5 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED104 0 0x24c6 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED105 0 0x24c7 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED106 0 0x24c8 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED107 0 0x24c9 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED108 0 0x24ca 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED109 0 0x24cb 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED110 0 0x24cc 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED111 0 0x24cd 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED112 0 0x24ce 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED113 0 0x24cf 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED114 0 0x24d0 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED115 0 0x24d1 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED116 0 0x24d2 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED117 0 0x24d3 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED118 0 0x24d4 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED119 0 0x24d5 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED120 0 0x24d6 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED121 0 0x24d7 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED122 0 0x24d8 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED123 0 0x24d9 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED124 0 0x24da 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED125 0 0x24db 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED126 0 0x24dc 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED127 0 0x24dd 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED128 0 0x24de 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED129 0 0x24df 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED130 0 0x24e0 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED131 0 0x24e1 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED132 0 0x24e2 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED133 0 0x24e3 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED134 0 0x24e4 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED135 0 0x24e5 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED136 0 0x24e6 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED137 0 0x24e7 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED138 0 0x24e8 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED139 0 0x24e9 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED140 0 0x24ea 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED141 0 0x24eb 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED142 0 0x24ec 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED143 0 0x24ed 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED144 0 0x24ee 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED145 0 0x24ef 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED146 0 0x24f0 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED147 0 0x24f1 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED148 0 0x24f2 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED149 0 0x24f3 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED150 0 0x24f4 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED151 0 0x24f5 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED152 0 0x24f6 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED153 0 0x24f7 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED154 0 0x24f8 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED155 0 0x24f9 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED156 0 0x24fa 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED157 0 0x24fb 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED158 0 0x24fc 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED159 0 0x24fd 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDC_COMBOPHYCMREGS4_COMMON_FUSE1 0 0x245e 11 0 2 fuse1_valid 0 0 fuse1_unpopulated0 1 2 fuse1_ron_override_val 3 8 fuse1_unpopulated1 9 9 fuse1_ron_ctl 10 11 fuse1_unpopulated2 12 12 fuse1_rtt_override_val 13 18 fuse1_unpopulated3 19 19 fuse1_rtt_ctl 20 21 fuse1_refresh_cal_en 22 22 fuse1_spare 23 31 mmDC_COMBOPHYCMREGS4_COMMON_FUSE2 0 0x245f 4 0 2 fuse2_valid 0 0 fuse2_unpopulated 1 8 fuse2_tx_fifo_ptr 9 13 fuse2_spare 14 31 mmDC_COMBOPHYCMREGS4_COMMON_FUSE3 0 0x2460 4 0 2 fuse3_valid 0 0 fuse3_unpopulated 1 9 fuse3_ei_det_thresh_sel 10 12 fuse3_spare 29 31 mmDC_COMBOPHYCMREGS4_COMMON_MAR_DEEMPH_NOM 0 0x2461 4 0 2 tx_margin_nom 0 7 deemph_gen1_nom 8 15 deemph35_gen2_nom 16 23 deemph60_gen2_nom 24 31 mmDC_COMBOPHYCMREGS4_COMMON_LANE_PWRMGMT 0 0x2462 3 0 2 pgdelay 0 3 pgmask 4 9 vprot_en 11 11 mmDC_COMBOPHYCMREGS4_COMMON_TXCNTRL 0 0x2463 7 0 2 rdptr_rst_val_gen3 0 4 clkgate_dis 5 5 slew_rate_ctl_gen1 6 8 slew_rate_ctl_gen2 9 11 slew_rate_ctl_gen3 12 14 dual_dvi_mstr_en 15 15 dual_dvi_en 16 16 mmDC_COMBOPHYCMREGS4_COMMON_TMDP 0 0x2464 1 0 2 tmdp_spare 0 31 mmDC_COMBOPHYCMREGS4_COMMON_LANE_RESETS 0 0x2465 8 0 2 lane_0_reset_l 0 0 lane_1_reset_l 1 1 lane_2_reset_l 2 2 lane_3_reset_l 3 3 lane_4_reset_l 4 4 lane_5_reset_l 5 5 lane_6_reset_l 6 6 lane_7_reset_l 7 7 mmDC_COMBOPHYCMREGS4_COMMON_ZCALCODE_CTRL 0 0x2466 3 0 2 zcalcode_override 0 0 tx_binary_code_override_val 1 5 tx_driver_fifty_ohms 21 21 mmDC_COMBOPHYCMREGS4_COMMON_DISP_RFU1 0 0x2467 1 0 2 rfu_value1 0 31 mmDC_COMBOPHYCMREGS4_COMMON_DISP_RFU2 0 0x2468 1 0 2 rfu_value2 0 31 mmDC_COMBOPHYCMREGS4_COMMON_DISP_RFU3 0 0x2469 1 0 2 rfu_value3 0 31 mmDC_COMBOPHYCMREGS4_COMMON_DISP_RFU4 0 0x246a 1 0 2 rfu_value4 0 31 mmDC_COMBOPHYCMREGS4_COMMON_DISP_RFU5 0 0x246b 1 0 2 rfu_value5 0 31 mmDC_COMBOPHYCMREGS4_COMMON_DISP_RFU6 0 0x246c 1 0 2 rfu_value6 0 31 mmDC_COMBOPHYCMREGS4_COMMON_DISP_RFU7 0 0x246d 1 0 2 rfu_value7 0 31 mmDC_COMBOPHYTXREGS4_CMD_BUS_TX_CONTROL_LANE0 0 0x247e 3 0 2 tx_pwr 0 2 tx_pg_en 3 4 tx_rdy 8 8 mmDC_COMBOPHYTXREGS4_MARGIN_DEEMPH_LANE0 0 0x247f 3 0 2 txmarg_sel 0 2 deemph_sel 3 4 tx_margin_en 5 5 mmDC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE0 0 0x2480 12 0 2 twosym_en 1 2 link_speed 3 4 gang_mode 5 7 max_linkrate 8 9 pcs_freq 10 11 pcs_clken 12 12 pcs_clkdone 13 13 pll1_always_on 14 14 rdclk_div2_en 15 15 tx_boost_adj 16 19 tx_boost_en 20 20 tx_binary_ron_code_offset 22 23 mmDC_COMBOPHYTXREGS4_TX_DISP_RFU0_LANE0 0 0x2481 1 0 2 rfu_value0 0 31 mmDC_COMBOPHYTXREGS4_TX_DISP_RFU1_LANE0 0 0x2482 1 0 2 rfu_value1 0 31 mmDC_COMBOPHYTXREGS4_TX_DISP_RFU2_LANE0 0 0x2483 1 0 2 rfu_value2 0 31 mmDC_COMBOPHYTXREGS4_TX_DISP_RFU3_LANE0 0 0x2484 1 0 2 rfu_value3 0 31 mmDC_COMBOPHYTXREGS4_TX_DISP_RFU4_LANE0 0 0x2485 1 0 2 rfu_value4 0 31 mmDC_COMBOPHYTXREGS4_TX_DISP_RFU5_LANE0 0 0x2486 1 0 2 rfu_value5 0 31 mmDC_COMBOPHYTXREGS4_TX_DISP_RFU6_LANE0 0 0x2487 1 0 2 rfu_value6 0 31 mmDC_COMBOPHYTXREGS4_TX_DISP_RFU7_LANE0 0 0x2488 1 0 2 rfu_value7 0 31 mmDC_COMBOPHYTXREGS4_TX_DISP_RFU8_LANE0 0 0x2489 1 0 2 rfu_value8 0 31 mmDC_COMBOPHYTXREGS4_TX_DISP_RFU9_LANE0 0 0x248a 1 0 2 rfu_value9 0 31 mmDC_COMBOPHYTXREGS4_TX_DISP_RFU10_LANE0 0 0x248b 1 0 2 rfu_value10 0 31 mmDC_COMBOPHYTXREGS4_TX_DISP_RFU11_LANE0 0 0x248c 1 0 2 rfu_value11 0 31 mmDC_COMBOPHYTXREGS4_TX_DISP_RFU12_LANE0 0 0x248d 1 0 2 rfu_value12 0 31 mmDC_COMBOPHYTXREGS4_CMD_BUS_TX_CONTROL_LANE1 0 0x248e 3 0 2 tx_pwr 0 2 tx_pg_en 3 4 tx_rdy 8 8 mmDC_COMBOPHYTXREGS4_MARGIN_DEEMPH_LANE1 0 0x248f 3 0 2 txmarg_sel 0 2 deemph_sel 3 4 tx_margin_en 5 5 mmDC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE1 0 0x2490 12 0 2 twosym_en 1 2 link_speed 3 4 gang_mode 5 7 max_linkrate 8 9 pcs_freq 10 11 pcs_clken 12 12 pcs_clkdone 13 13 pll1_always_on 14 14 rdclk_div2_en 15 15 tx_boost_adj 16 19 tx_boost_en 20 20 tx_binary_ron_code_offset 22 23 mmDC_COMBOPHYTXREGS4_TX_DISP_RFU0_LANE1 0 0x2491 1 0 2 rfu_value0 0 31 mmDC_COMBOPHYTXREGS4_TX_DISP_RFU1_LANE1 0 0x2492 1 0 2 rfu_value1 0 31 mmDC_COMBOPHYTXREGS4_TX_DISP_RFU2_LANE1 0 0x2493 1 0 2 rfu_value2 0 31 mmDC_COMBOPHYTXREGS4_TX_DISP_RFU3_LANE1 0 0x2494 1 0 2 rfu_value3 0 31 mmDC_COMBOPHYTXREGS4_TX_DISP_RFU4_LANE1 0 0x2495 1 0 2 rfu_value4 0 31 mmDC_COMBOPHYTXREGS4_TX_DISP_RFU5_LANE1 0 0x2496 1 0 2 rfu_value5 0 31 mmDC_COMBOPHYTXREGS4_TX_DISP_RFU6_LANE1 0 0x2497 1 0 2 rfu_value6 0 31 mmDC_COMBOPHYTXREGS4_TX_DISP_RFU7_LANE1 0 0x2498 1 0 2 rfu_value7 0 31 mmDC_COMBOPHYTXREGS4_TX_DISP_RFU8_LANE1 0 0x2499 1 0 2 rfu_value8 0 31 mmDC_COMBOPHYTXREGS4_TX_DISP_RFU9_LANE1 0 0x249a 1 0 2 rfu_value9 0 31 mmDC_COMBOPHYTXREGS4_TX_DISP_RFU10_LANE1 0 0x249b 1 0 2 rfu_value10 0 31 mmDC_COMBOPHYTXREGS4_TX_DISP_RFU11_LANE1 0 0x249c 1 0 2 rfu_value11 0 31 mmDC_COMBOPHYTXREGS4_TX_DISP_RFU12_LANE1 0 0x249d 1 0 2 rfu_value12 0 31 mmDC_COMBOPHYTXREGS4_CMD_BUS_TX_CONTROL_LANE2 0 0x249e 3 0 2 tx_pwr 0 2 tx_pg_en 3 4 tx_rdy 8 8 mmDC_COMBOPHYTXREGS4_MARGIN_DEEMPH_LANE2 0 0x249f 3 0 2 txmarg_sel 0 2 deemph_sel 3 4 tx_margin_en 5 5 mmDC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE2 0 0x24a0 12 0 2 twosym_en 1 2 link_speed 3 4 gang_mode 5 7 max_linkrate 8 9 pcs_freq 10 11 pcs_clken 12 12 pcs_clkdone 13 13 pll1_always_on 14 14 rdclk_div2_en 15 15 tx_boost_adj 16 19 tx_boost_en 20 20 tx_binary_ron_code_offset 22 23 mmDC_COMBOPHYTXREGS4_TX_DISP_RFU0_LANE2 0 0x24a1 1 0 2 rfu_value0 0 31 mmDC_COMBOPHYTXREGS4_TX_DISP_RFU1_LANE2 0 0x24a2 1 0 2 rfu_value1 0 31 mmDC_COMBOPHYTXREGS4_TX_DISP_RFU2_LANE2 0 0x24a3 1 0 2 rfu_value2 0 31 mmDC_COMBOPHYTXREGS4_TX_DISP_RFU3_LANE2 0 0x24a4 1 0 2 rfu_value3 0 31 mmDC_COMBOPHYTXREGS4_TX_DISP_RFU4_LANE2 0 0x24a5 1 0 2 rfu_value4 0 31 mmDC_COMBOPHYTXREGS4_TX_DISP_RFU5_LANE2 0 0x24a6 1 0 2 rfu_value5 0 31 mmDC_COMBOPHYTXREGS4_TX_DISP_RFU6_LANE2 0 0x24a7 1 0 2 rfu_value6 0 31 mmDC_COMBOPHYTXREGS4_TX_DISP_RFU7_LANE2 0 0x24a8 1 0 2 rfu_value7 0 31 mmDC_COMBOPHYTXREGS4_TX_DISP_RFU8_LANE2 0 0x24a9 1 0 2 rfu_value8 0 31 mmDC_COMBOPHYTXREGS4_TX_DISP_RFU9_LANE2 0 0x24aa 1 0 2 rfu_value9 0 31 mmDC_COMBOPHYTXREGS4_TX_DISP_RFU10_LANE2 0 0x24ab 1 0 2 rfu_value10 0 31 mmDC_COMBOPHYTXREGS4_TX_DISP_RFU11_LANE2 0 0x24ac 1 0 2 rfu_value11 0 31 mmDC_COMBOPHYTXREGS4_TX_DISP_RFU12_LANE2 0 0x24ad 1 0 2 rfu_value12 0 31 mmDC_COMBOPHYTXREGS4_CMD_BUS_TX_CONTROL_LANE3 0 0x24ae 3 0 2 tx_pwr 0 2 tx_pg_en 3 4 tx_rdy 8 8 mmDC_COMBOPHYTXREGS4_MARGIN_DEEMPH_LANE3 0 0x24af 3 0 2 txmarg_sel 0 2 deemph_sel 3 4 tx_margin_en 5 5 mmDC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE3 0 0x24b0 12 0 2 twosym_en 1 2 link_speed 3 4 gang_mode 5 7 max_linkrate 8 9 pcs_freq 10 11 pcs_clken 12 12 pcs_clkdone 13 13 pll1_always_on 14 14 rdclk_div2_en 15 15 tx_boost_adj 16 19 tx_boost_en 20 20 tx_binary_ron_code_offset 22 23 mmDC_COMBOPHYTXREGS4_TX_DISP_RFU0_LANE3 0 0x24b1 1 0 2 rfu_value0 0 31 mmDC_COMBOPHYTXREGS4_TX_DISP_RFU1_LANE3 0 0x24b2 1 0 2 rfu_value1 0 31 mmDC_COMBOPHYTXREGS4_TX_DISP_RFU2_LANE3 0 0x24b3 1 0 2 rfu_value2 0 31 mmDC_COMBOPHYTXREGS4_TX_DISP_RFU3_LANE3 0 0x24b4 1 0 2 rfu_value3 0 31 mmDC_COMBOPHYTXREGS4_TX_DISP_RFU4_LANE3 0 0x24b5 1 0 2 rfu_value4 0 31 mmDC_COMBOPHYTXREGS4_TX_DISP_RFU5_LANE3 0 0x24b6 1 0 2 rfu_value5 0 31 mmDC_COMBOPHYTXREGS4_TX_DISP_RFU6_LANE3 0 0x24b7 1 0 2 rfu_value6 0 31 mmDC_COMBOPHYTXREGS4_TX_DISP_RFU7_LANE3 0 0x24b8 1 0 2 rfu_value7 0 31 mmDC_COMBOPHYTXREGS4_TX_DISP_RFU8_LANE3 0 0x24b9 1 0 2 rfu_value8 0 31 mmDC_COMBOPHYTXREGS4_TX_DISP_RFU9_LANE3 0 0x24ba 1 0 2 rfu_value9 0 31 mmDC_COMBOPHYTXREGS4_TX_DISP_RFU10_LANE3 0 0x24bb 1 0 2 rfu_value10 0 31 mmDC_COMBOPHYTXREGS4_TX_DISP_RFU11_LANE3 0 0x24bc 1 0 2 rfu_value11 0 31 mmDC_COMBOPHYTXREGS4_TX_DISP_RFU12_LANE3 0 0x24bd 1 0 2 rfu_value12 0 31 mmDC_COMBOPHYPLLREGS4_FREQ_CTRL0 0 0x24be 2 0 2 fcw0_frac 0 15 fcw0_int 16 24 mmDC_COMBOPHYPLLREGS4_FREQ_CTRL1 0 0x24bf 2 0 2 fcw1_frac 0 15 fcw1_int 16 24 mmDC_COMBOPHYPLLREGS4_FREQ_CTRL2 0 0x24c0 2 0 2 fcw_denom 0 15 fcw_slew_frac 16 31 mmDC_COMBOPHYPLLREGS4_FREQ_CTRL3 0 0x24c1 8 0 2 refclk_div 0 1 vco_pre_div 3 4 fracn_en 6 6 ssc_en 8 8 fcw_sel 10 10 freq_jump_en 12 12 tdc_resolution 16 23 dpll_cfg_1 24 31 mmDC_COMBOPHYPLLREGS4_BW_CTRL_COARSE 0 0x24c2 6 0 2 gi_coarse_mant 0 1 gi_coarse_exp 2 5 gp_coarse_mant 7 10 gp_coarse_exp 12 15 nctl_coarse_res 17 22 nctl_coarse_frac_res 24 25 mmDC_COMBOPHYPLLREGS4_BW_CTRL_FINE 0 0x24c3 1 0 2 dpll_cfg_3 0 9 mmDC_COMBOPHYPLLREGS4_CAL_CTRL 0 0x24c4 9 0 2 bypass_freq_lock 0 0 tdc_cal_en 1 1 tdc_cal_ctrl 3 8 meas_win_sel 9 10 kdco_cal_dis 11 11 kdco_ratio 13 20 kdco_incr_cal_dis 22 22 nctl_adj_dis 23 23 refclk_rate 24 31 mmDC_COMBOPHYPLLREGS4_LOOP_CTRL 0 0x24c5 10 0 2 fbdiv_mask_en 0 0 fb_slip_dis 2 2 clk_tdc_sel 4 5 clk_nctl_sel 7 8 sig_del_patt_sel 10 10 nctl_sig_del_dis 12 12 fbclk_track_refclk 14 14 prbs_en 16 16 tdc_clk_gate_en 18 18 phase_offset 20 26 mmDC_COMBOPHYPLLREGS4_VREG_CFG 0 0x24c7 14 0 2 bleeder_ac 0 0 bleeder_en 1 1 is_1p2 2 2 reg_obs_sel 3 4 reg_on_mode 5 6 rlad_tap_sel 7 10 reg_off_hi 11 11 reg_off_lo 12 12 scale_driver 13 14 sel_bump 15 15 sel_rladder_x 16 16 short_rc_filt_x 17 17 vref_pwr_on 18 18 dpll_cfg_2 20 27 mmDC_COMBOPHYPLLREGS4_OBSERVE0 0 0x24c8 5 0 2 lock_det_tdc_steps 0 4 clear_sticky_lock 6 6 lock_det_dis 8 8 dco_cfg 10 17 anaobs_sel 21 23 mmDC_COMBOPHYPLLREGS4_OBSERVE1 0 0x24c9 5 0 2 digobs_sel 0 3 digobs_trig_sel 5 8 digobs_div 10 11 digobs_trig_div 13 14 lock_timer 16 29 mmDC_COMBOPHYPLLREGS4_DFT_OUT 0 0x24ca 1 0 2 dft_data 0 31 mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED0 0 0x2526 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED1 0 0x2527 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED2 0 0x2528 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED3 0 0x2529 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED4 0 0x252a 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED5 0 0x252b 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED6 0 0x252c 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED7 0 0x252d 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED8 0 0x252e 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED9 0 0x252f 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED10 0 0x2530 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED11 0 0x2531 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED12 0 0x2532 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED13 0 0x2533 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED14 0 0x2534 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED15 0 0x2535 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED16 0 0x2536 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED17 0 0x2537 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED18 0 0x2538 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED19 0 0x2539 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED20 0 0x253a 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED21 0 0x253b 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED22 0 0x253c 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED23 0 0x253d 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED24 0 0x253e 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED25 0 0x253f 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED26 0 0x2540 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED27 0 0x2541 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED28 0 0x2542 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED29 0 0x2543 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED30 0 0x2544 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED31 0 0x2545 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED32 0 0x2546 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED33 0 0x2547 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED34 0 0x2548 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED35 0 0x2549 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED36 0 0x254a 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED37 0 0x254b 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED38 0 0x254c 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED39 0 0x254d 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED40 0 0x254e 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED41 0 0x254f 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED42 0 0x2550 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED43 0 0x2551 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED44 0 0x2552 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED45 0 0x2553 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED46 0 0x2554 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED47 0 0x2555 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED48 0 0x2556 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED49 0 0x2557 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED50 0 0x2558 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED51 0 0x2559 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED52 0 0x255a 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED53 0 0x255b 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED54 0 0x255c 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED55 0 0x255d 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED56 0 0x255e 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED57 0 0x255f 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED58 0 0x2560 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED59 0 0x2561 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED60 0 0x2562 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED61 0 0x2563 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED62 0 0x2564 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED63 0 0x2565 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED64 0 0x2566 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED65 0 0x2567 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED66 0 0x2568 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED67 0 0x2569 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED68 0 0x256a 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED69 0 0x256b 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED70 0 0x256c 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED71 0 0x256d 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED72 0 0x256e 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED73 0 0x256f 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED74 0 0x2570 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED75 0 0x2571 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED76 0 0x2572 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED77 0 0x2573 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED78 0 0x2574 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED79 0 0x2575 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED80 0 0x2576 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED81 0 0x2577 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED82 0 0x2578 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED83 0 0x2579 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED84 0 0x257a 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED85 0 0x257b 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED86 0 0x257c 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED87 0 0x257d 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED88 0 0x257e 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED89 0 0x257f 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED90 0 0x2580 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED91 0 0x2581 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED92 0 0x2582 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED93 0 0x2583 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED94 0 0x2584 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED95 0 0x2585 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED96 0 0x2586 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED97 0 0x2587 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED98 0 0x2588 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED99 0 0x2589 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED100 0 0x258a 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED101 0 0x258b 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED102 0 0x258c 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED103 0 0x258d 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED104 0 0x258e 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED105 0 0x258f 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED106 0 0x2590 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED107 0 0x2591 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED108 0 0x2592 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED109 0 0x2593 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED110 0 0x2594 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED111 0 0x2595 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED112 0 0x2596 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED113 0 0x2597 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED114 0 0x2598 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED115 0 0x2599 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED116 0 0x259a 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED117 0 0x259b 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED118 0 0x259c 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED119 0 0x259d 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED120 0 0x259e 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED121 0 0x259f 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED122 0 0x25a0 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED123 0 0x25a1 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED124 0 0x25a2 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED125 0 0x25a3 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED126 0 0x25a4 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED127 0 0x25a5 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED128 0 0x25a6 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED129 0 0x25a7 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED130 0 0x25a8 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED131 0 0x25a9 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED132 0 0x25aa 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED133 0 0x25ab 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED134 0 0x25ac 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED135 0 0x25ad 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED136 0 0x25ae 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED137 0 0x25af 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED138 0 0x25b0 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED139 0 0x25b1 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED140 0 0x25b2 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED141 0 0x25b3 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED142 0 0x25b4 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED143 0 0x25b5 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED144 0 0x25b6 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED145 0 0x25b7 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED146 0 0x25b8 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED147 0 0x25b9 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED148 0 0x25ba 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED149 0 0x25bb 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED150 0 0x25bc 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED151 0 0x25bd 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED152 0 0x25be 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED153 0 0x25bf 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED154 0 0x25c0 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED155 0 0x25c1 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED156 0 0x25c2 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED157 0 0x25c3 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED158 0 0x25c4 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED159 0 0x25c5 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDC_COMBOPHYCMREGS5_COMMON_FUSE1 0 0x2526 11 0 2 fuse1_valid 0 0 fuse1_unpopulated0 1 2 fuse1_ron_override_val 3 8 fuse1_unpopulated1 9 9 fuse1_ron_ctl 10 11 fuse1_unpopulated2 12 12 fuse1_rtt_override_val 13 18 fuse1_unpopulated3 19 19 fuse1_rtt_ctl 20 21 fuse1_refresh_cal_en 22 22 fuse1_spare 23 31 mmDC_COMBOPHYCMREGS5_COMMON_FUSE2 0 0x2527 4 0 2 fuse2_valid 0 0 fuse2_unpopulated 1 8 fuse2_tx_fifo_ptr 9 13 fuse2_spare 14 31 mmDC_COMBOPHYCMREGS5_COMMON_FUSE3 0 0x2528 4 0 2 fuse3_valid 0 0 fuse3_unpopulated 1 9 fuse3_ei_det_thresh_sel 10 12 fuse3_spare 29 31 mmDC_COMBOPHYCMREGS5_COMMON_MAR_DEEMPH_NOM 0 0x2529 4 0 2 tx_margin_nom 0 7 deemph_gen1_nom 8 15 deemph35_gen2_nom 16 23 deemph60_gen2_nom 24 31 mmDC_COMBOPHYCMREGS5_COMMON_LANE_PWRMGMT 0 0x252a 3 0 2 pgdelay 0 3 pgmask 4 9 vprot_en 11 11 mmDC_COMBOPHYCMREGS5_COMMON_TXCNTRL 0 0x252b 7 0 2 rdptr_rst_val_gen3 0 4 clkgate_dis 5 5 slew_rate_ctl_gen1 6 8 slew_rate_ctl_gen2 9 11 slew_rate_ctl_gen3 12 14 dual_dvi_mstr_en 15 15 dual_dvi_en 16 16 mmDC_COMBOPHYCMREGS5_COMMON_TMDP 0 0x252c 1 0 2 tmdp_spare 0 31 mmDC_COMBOPHYCMREGS5_COMMON_LANE_RESETS 0 0x252d 8 0 2 lane_0_reset_l 0 0 lane_1_reset_l 1 1 lane_2_reset_l 2 2 lane_3_reset_l 3 3 lane_4_reset_l 4 4 lane_5_reset_l 5 5 lane_6_reset_l 6 6 lane_7_reset_l 7 7 mmDC_COMBOPHYCMREGS5_COMMON_ZCALCODE_CTRL 0 0x252e 3 0 2 zcalcode_override 0 0 tx_binary_code_override_val 1 5 tx_driver_fifty_ohms 21 21 mmDC_COMBOPHYCMREGS5_COMMON_DISP_RFU1 0 0x252f 1 0 2 rfu_value1 0 31 mmDC_COMBOPHYCMREGS5_COMMON_DISP_RFU2 0 0x2530 1 0 2 rfu_value2 0 31 mmDC_COMBOPHYCMREGS5_COMMON_DISP_RFU3 0 0x2531 1 0 2 rfu_value3 0 31 mmDC_COMBOPHYCMREGS5_COMMON_DISP_RFU4 0 0x2532 1 0 2 rfu_value4 0 31 mmDC_COMBOPHYCMREGS5_COMMON_DISP_RFU5 0 0x2533 1 0 2 rfu_value5 0 31 mmDC_COMBOPHYCMREGS5_COMMON_DISP_RFU6 0 0x2534 1 0 2 rfu_value6 0 31 mmDC_COMBOPHYCMREGS5_COMMON_DISP_RFU7 0 0x2535 1 0 2 rfu_value7 0 31 mmDC_COMBOPHYTXREGS5_CMD_BUS_TX_CONTROL_LANE0 0 0x2546 3 0 2 tx_pwr 0 2 tx_pg_en 3 4 tx_rdy 8 8 mmDC_COMBOPHYTXREGS5_MARGIN_DEEMPH_LANE0 0 0x2547 3 0 2 txmarg_sel 0 2 deemph_sel 3 4 tx_margin_en 5 5 mmDC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE0 0 0x2548 12 0 2 twosym_en 1 2 link_speed 3 4 gang_mode 5 7 max_linkrate 8 9 pcs_freq 10 11 pcs_clken 12 12 pcs_clkdone 13 13 pll1_always_on 14 14 rdclk_div2_en 15 15 tx_boost_adj 16 19 tx_boost_en 20 20 tx_binary_ron_code_offset 22 23 mmDC_COMBOPHYTXREGS5_TX_DISP_RFU0_LANE0 0 0x2549 1 0 2 rfu_value0 0 31 mmDC_COMBOPHYTXREGS5_TX_DISP_RFU1_LANE0 0 0x254a 1 0 2 rfu_value1 0 31 mmDC_COMBOPHYTXREGS5_TX_DISP_RFU2_LANE0 0 0x254b 1 0 2 rfu_value2 0 31 mmDC_COMBOPHYTXREGS5_TX_DISP_RFU3_LANE0 0 0x254c 1 0 2 rfu_value3 0 31 mmDC_COMBOPHYTXREGS5_TX_DISP_RFU4_LANE0 0 0x254d 1 0 2 rfu_value4 0 31 mmDC_COMBOPHYTXREGS5_TX_DISP_RFU5_LANE0 0 0x254e 1 0 2 rfu_value5 0 31 mmDC_COMBOPHYTXREGS5_TX_DISP_RFU6_LANE0 0 0x254f 1 0 2 rfu_value6 0 31 mmDC_COMBOPHYTXREGS5_TX_DISP_RFU7_LANE0 0 0x2550 1 0 2 rfu_value7 0 31 mmDC_COMBOPHYTXREGS5_TX_DISP_RFU8_LANE0 0 0x2551 1 0 2 rfu_value8 0 31 mmDC_COMBOPHYTXREGS5_TX_DISP_RFU9_LANE0 0 0x2552 1 0 2 rfu_value9 0 31 mmDC_COMBOPHYTXREGS5_TX_DISP_RFU10_LANE0 0 0x2553 1 0 2 rfu_value10 0 31 mmDC_COMBOPHYTXREGS5_TX_DISP_RFU11_LANE0 0 0x2554 1 0 2 rfu_value11 0 31 mmDC_COMBOPHYTXREGS5_TX_DISP_RFU12_LANE0 0 0x2555 1 0 2 rfu_value12 0 31 mmDC_COMBOPHYTXREGS5_CMD_BUS_TX_CONTROL_LANE1 0 0x2556 3 0 2 tx_pwr 0 2 tx_pg_en 3 4 tx_rdy 8 8 mmDC_COMBOPHYTXREGS5_MARGIN_DEEMPH_LANE1 0 0x2557 3 0 2 txmarg_sel 0 2 deemph_sel 3 4 tx_margin_en 5 5 mmDC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE1 0 0x2558 12 0 2 twosym_en 1 2 link_speed 3 4 gang_mode 5 7 max_linkrate 8 9 pcs_freq 10 11 pcs_clken 12 12 pcs_clkdone 13 13 pll1_always_on 14 14 rdclk_div2_en 15 15 tx_boost_adj 16 19 tx_boost_en 20 20 tx_binary_ron_code_offset 22 23 mmDC_COMBOPHYTXREGS5_TX_DISP_RFU0_LANE1 0 0x2559 1 0 2 rfu_value0 0 31 mmDC_COMBOPHYTXREGS5_TX_DISP_RFU1_LANE1 0 0x255a 1 0 2 rfu_value1 0 31 mmDC_COMBOPHYTXREGS5_TX_DISP_RFU2_LANE1 0 0x255b 1 0 2 rfu_value2 0 31 mmDC_COMBOPHYTXREGS5_TX_DISP_RFU3_LANE1 0 0x255c 1 0 2 rfu_value3 0 31 mmDC_COMBOPHYTXREGS5_TX_DISP_RFU4_LANE1 0 0x255d 1 0 2 rfu_value4 0 31 mmDC_COMBOPHYTXREGS5_TX_DISP_RFU5_LANE1 0 0x255e 1 0 2 rfu_value5 0 31 mmDC_COMBOPHYTXREGS5_TX_DISP_RFU6_LANE1 0 0x255f 1 0 2 rfu_value6 0 31 mmDC_COMBOPHYTXREGS5_TX_DISP_RFU7_LANE1 0 0x2560 1 0 2 rfu_value7 0 31 mmDC_COMBOPHYTXREGS5_TX_DISP_RFU8_LANE1 0 0x2561 1 0 2 rfu_value8 0 31 mmDC_COMBOPHYTXREGS5_TX_DISP_RFU9_LANE1 0 0x2562 1 0 2 rfu_value9 0 31 mmDC_COMBOPHYTXREGS5_TX_DISP_RFU10_LANE1 0 0x2563 1 0 2 rfu_value10 0 31 mmDC_COMBOPHYTXREGS5_TX_DISP_RFU11_LANE1 0 0x2564 1 0 2 rfu_value11 0 31 mmDC_COMBOPHYTXREGS5_TX_DISP_RFU12_LANE1 0 0x2565 1 0 2 rfu_value12 0 31 mmDC_COMBOPHYTXREGS5_CMD_BUS_TX_CONTROL_LANE2 0 0x2566 3 0 2 tx_pwr 0 2 tx_pg_en 3 4 tx_rdy 8 8 mmDC_COMBOPHYTXREGS5_MARGIN_DEEMPH_LANE2 0 0x2567 3 0 2 txmarg_sel 0 2 deemph_sel 3 4 tx_margin_en 5 5 mmDC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE2 0 0x2568 12 0 2 twosym_en 1 2 link_speed 3 4 gang_mode 5 7 max_linkrate 8 9 pcs_freq 10 11 pcs_clken 12 12 pcs_clkdone 13 13 pll1_always_on 14 14 rdclk_div2_en 15 15 tx_boost_adj 16 19 tx_boost_en 20 20 tx_binary_ron_code_offset 22 23 mmDC_COMBOPHYTXREGS5_TX_DISP_RFU0_LANE2 0 0x2569 1 0 2 rfu_value0 0 31 mmDC_COMBOPHYTXREGS5_TX_DISP_RFU1_LANE2 0 0x256a 1 0 2 rfu_value1 0 31 mmDC_COMBOPHYTXREGS5_TX_DISP_RFU2_LANE2 0 0x256b 1 0 2 rfu_value2 0 31 mmDC_COMBOPHYTXREGS5_TX_DISP_RFU3_LANE2 0 0x256c 1 0 2 rfu_value3 0 31 mmDC_COMBOPHYTXREGS5_TX_DISP_RFU4_LANE2 0 0x256d 1 0 2 rfu_value4 0 31 mmDC_COMBOPHYTXREGS5_TX_DISP_RFU5_LANE2 0 0x256e 1 0 2 rfu_value5 0 31 mmDC_COMBOPHYTXREGS5_TX_DISP_RFU6_LANE2 0 0x256f 1 0 2 rfu_value6 0 31 mmDC_COMBOPHYTXREGS5_TX_DISP_RFU7_LANE2 0 0x2570 1 0 2 rfu_value7 0 31 mmDC_COMBOPHYTXREGS5_TX_DISP_RFU8_LANE2 0 0x2571 1 0 2 rfu_value8 0 31 mmDC_COMBOPHYTXREGS5_TX_DISP_RFU9_LANE2 0 0x2572 1 0 2 rfu_value9 0 31 mmDC_COMBOPHYTXREGS5_TX_DISP_RFU10_LANE2 0 0x2573 1 0 2 rfu_value10 0 31 mmDC_COMBOPHYTXREGS5_TX_DISP_RFU11_LANE2 0 0x2574 1 0 2 rfu_value11 0 31 mmDC_COMBOPHYTXREGS5_TX_DISP_RFU12_LANE2 0 0x2575 1 0 2 rfu_value12 0 31 mmDC_COMBOPHYTXREGS5_CMD_BUS_TX_CONTROL_LANE3 0 0x2576 3 0 2 tx_pwr 0 2 tx_pg_en 3 4 tx_rdy 8 8 mmDC_COMBOPHYTXREGS5_MARGIN_DEEMPH_LANE3 0 0x2577 3 0 2 txmarg_sel 0 2 deemph_sel 3 4 tx_margin_en 5 5 mmDC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE3 0 0x2578 12 0 2 twosym_en 1 2 link_speed 3 4 gang_mode 5 7 max_linkrate 8 9 pcs_freq 10 11 pcs_clken 12 12 pcs_clkdone 13 13 pll1_always_on 14 14 rdclk_div2_en 15 15 tx_boost_adj 16 19 tx_boost_en 20 20 tx_binary_ron_code_offset 22 23 mmDC_COMBOPHYTXREGS5_TX_DISP_RFU0_LANE3 0 0x2579 1 0 2 rfu_value0 0 31 mmDC_COMBOPHYTXREGS5_TX_DISP_RFU1_LANE3 0 0x257a 1 0 2 rfu_value1 0 31 mmDC_COMBOPHYTXREGS5_TX_DISP_RFU2_LANE3 0 0x257b 1 0 2 rfu_value2 0 31 mmDC_COMBOPHYTXREGS5_TX_DISP_RFU3_LANE3 0 0x257c 1 0 2 rfu_value3 0 31 mmDC_COMBOPHYTXREGS5_TX_DISP_RFU4_LANE3 0 0x257d 1 0 2 rfu_value4 0 31 mmDC_COMBOPHYTXREGS5_TX_DISP_RFU5_LANE3 0 0x257e 1 0 2 rfu_value5 0 31 mmDC_COMBOPHYTXREGS5_TX_DISP_RFU6_LANE3 0 0x257f 1 0 2 rfu_value6 0 31 mmDC_COMBOPHYTXREGS5_TX_DISP_RFU7_LANE3 0 0x2580 1 0 2 rfu_value7 0 31 mmDC_COMBOPHYTXREGS5_TX_DISP_RFU8_LANE3 0 0x2581 1 0 2 rfu_value8 0 31 mmDC_COMBOPHYTXREGS5_TX_DISP_RFU9_LANE3 0 0x2582 1 0 2 rfu_value9 0 31 mmDC_COMBOPHYTXREGS5_TX_DISP_RFU10_LANE3 0 0x2583 1 0 2 rfu_value10 0 31 mmDC_COMBOPHYTXREGS5_TX_DISP_RFU11_LANE3 0 0x2584 1 0 2 rfu_value11 0 31 mmDC_COMBOPHYTXREGS5_TX_DISP_RFU12_LANE3 0 0x2585 1 0 2 rfu_value12 0 31 mmDC_COMBOPHYPLLREGS5_FREQ_CTRL0 0 0x2586 2 0 2 fcw0_frac 0 15 fcw0_int 16 24 mmDC_COMBOPHYPLLREGS5_FREQ_CTRL1 0 0x2587 2 0 2 fcw1_frac 0 15 fcw1_int 16 24 mmDC_COMBOPHYPLLREGS5_FREQ_CTRL2 0 0x2588 2 0 2 fcw_denom 0 15 fcw_slew_frac 16 31 mmDC_COMBOPHYPLLREGS5_FREQ_CTRL3 0 0x2589 8 0 2 refclk_div 0 1 vco_pre_div 3 4 fracn_en 6 6 ssc_en 8 8 fcw_sel 10 10 freq_jump_en 12 12 tdc_resolution 16 23 dpll_cfg_1 24 31 mmDC_COMBOPHYPLLREGS5_BW_CTRL_COARSE 0 0x258a 6 0 2 gi_coarse_mant 0 1 gi_coarse_exp 2 5 gp_coarse_mant 7 10 gp_coarse_exp 12 15 nctl_coarse_res 17 22 nctl_coarse_frac_res 24 25 mmDC_COMBOPHYPLLREGS5_BW_CTRL_FINE 0 0x258b 1 0 2 dpll_cfg_3 0 9 mmDC_COMBOPHYPLLREGS5_CAL_CTRL 0 0x258c 9 0 2 bypass_freq_lock 0 0 tdc_cal_en 1 1 tdc_cal_ctrl 3 8 meas_win_sel 9 10 kdco_cal_dis 11 11 kdco_ratio 13 20 kdco_incr_cal_dis 22 22 nctl_adj_dis 23 23 refclk_rate 24 31 mmDC_COMBOPHYPLLREGS5_LOOP_CTRL 0 0x258d 10 0 2 fbdiv_mask_en 0 0 fb_slip_dis 2 2 clk_tdc_sel 4 5 clk_nctl_sel 7 8 sig_del_patt_sel 10 10 nctl_sig_del_dis 12 12 fbclk_track_refclk 14 14 prbs_en 16 16 tdc_clk_gate_en 18 18 phase_offset 20 26 mmDC_COMBOPHYPLLREGS5_VREG_CFG 0 0x258f 14 0 2 bleeder_ac 0 0 bleeder_en 1 1 is_1p2 2 2 reg_obs_sel 3 4 reg_on_mode 5 6 rlad_tap_sel 7 10 reg_off_hi 11 11 reg_off_lo 12 12 scale_driver 13 14 sel_bump 15 15 sel_rladder_x 16 16 short_rc_filt_x 17 17 vref_pwr_on 18 18 dpll_cfg_2 20 27 mmDC_COMBOPHYPLLREGS5_OBSERVE0 0 0x2590 5 0 2 lock_det_tdc_steps 0 4 clear_sticky_lock 6 6 lock_det_dis 8 8 dco_cfg 10 17 anaobs_sel 21 23 mmDC_COMBOPHYPLLREGS5_OBSERVE1 0 0x2591 5 0 2 digobs_sel 0 3 digobs_trig_sel 5 8 digobs_div 10 11 digobs_trig_div 13 14 lock_timer 16 29 mmDC_COMBOPHYPLLREGS5_DFT_OUT 0 0x2592 1 0 2 dft_data 0 31 mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED0 0 0x25ee 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED1 0 0x25ef 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED2 0 0x25f0 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED3 0 0x25f1 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED4 0 0x25f2 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED5 0 0x25f3 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED6 0 0x25f4 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED7 0 0x25f5 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED8 0 0x25f6 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED9 0 0x25f7 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED10 0 0x25f8 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED11 0 0x25f9 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED12 0 0x25fa 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED13 0 0x25fb 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED14 0 0x25fc 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED15 0 0x25fd 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED16 0 0x25fe 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED17 0 0x25ff 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED18 0 0x2600 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED19 0 0x2601 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED20 0 0x2602 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED21 0 0x2603 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED22 0 0x2604 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED23 0 0x2605 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED24 0 0x2606 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED25 0 0x2607 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED26 0 0x2608 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED27 0 0x2609 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED28 0 0x260a 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED29 0 0x260b 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED30 0 0x260c 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED31 0 0x260d 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED32 0 0x260e 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED33 0 0x260f 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED34 0 0x2610 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED35 0 0x2611 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED36 0 0x2612 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED37 0 0x2613 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED38 0 0x2614 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED39 0 0x2615 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED40 0 0x2616 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED41 0 0x2617 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED42 0 0x2618 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED43 0 0x2619 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED44 0 0x261a 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED45 0 0x261b 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED46 0 0x261c 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED47 0 0x261d 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED48 0 0x261e 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED49 0 0x261f 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED50 0 0x2620 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED51 0 0x2621 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED52 0 0x2622 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED53 0 0x2623 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED54 0 0x2624 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED55 0 0x2625 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED56 0 0x2626 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED57 0 0x2627 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED58 0 0x2628 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED59 0 0x2629 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED60 0 0x262a 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED61 0 0x262b 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED62 0 0x262c 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED63 0 0x262d 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED64 0 0x262e 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED65 0 0x262f 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED66 0 0x2630 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED67 0 0x2631 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED68 0 0x2632 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED69 0 0x2633 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED70 0 0x2634 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED71 0 0x2635 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED72 0 0x2636 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED73 0 0x2637 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED74 0 0x2638 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED75 0 0x2639 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED76 0 0x263a 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED77 0 0x263b 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED78 0 0x263c 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED79 0 0x263d 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED80 0 0x263e 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED81 0 0x263f 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED82 0 0x2640 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED83 0 0x2641 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED84 0 0x2642 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED85 0 0x2643 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED86 0 0x2644 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED87 0 0x2645 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED88 0 0x2646 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED89 0 0x2647 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED90 0 0x2648 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED91 0 0x2649 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED92 0 0x264a 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED93 0 0x264b 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED94 0 0x264c 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED95 0 0x264d 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED96 0 0x264e 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED97 0 0x264f 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED98 0 0x2650 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED99 0 0x2651 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED100 0 0x2652 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED101 0 0x2653 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED102 0 0x2654 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED103 0 0x2655 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED104 0 0x2656 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED105 0 0x2657 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED106 0 0x2658 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED107 0 0x2659 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED108 0 0x265a 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED109 0 0x265b 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED110 0 0x265c 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED111 0 0x265d 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED112 0 0x265e 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED113 0 0x265f 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED114 0 0x2660 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED115 0 0x2661 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED116 0 0x2662 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED117 0 0x2663 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED118 0 0x2664 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED119 0 0x2665 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED120 0 0x2666 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED121 0 0x2667 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED122 0 0x2668 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED123 0 0x2669 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED124 0 0x266a 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED125 0 0x266b 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED126 0 0x266c 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED127 0 0x266d 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED128 0 0x266e 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED129 0 0x266f 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED130 0 0x2670 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED131 0 0x2671 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED132 0 0x2672 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED133 0 0x2673 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED134 0 0x2674 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED135 0 0x2675 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED136 0 0x2676 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED137 0 0x2677 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED138 0 0x2678 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED139 0 0x2679 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED140 0 0x267a 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED141 0 0x267b 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED142 0 0x267c 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED143 0 0x267d 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED144 0 0x267e 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED145 0 0x267f 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED146 0 0x2680 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED147 0 0x2681 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED148 0 0x2682 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED149 0 0x2683 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED150 0 0x2684 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED151 0 0x2685 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED152 0 0x2686 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED153 0 0x2687 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED154 0 0x2688 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED155 0 0x2689 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED156 0 0x268a 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED157 0 0x268b 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED158 0 0x268c 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED159 0 0x268d 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDC_COMBOPHYCMREGS6_COMMON_FUSE1 0 0x25ee 11 0 2 fuse1_valid 0 0 fuse1_unpopulated0 1 2 fuse1_ron_override_val 3 8 fuse1_unpopulated1 9 9 fuse1_ron_ctl 10 11 fuse1_unpopulated2 12 12 fuse1_rtt_override_val 13 18 fuse1_unpopulated3 19 19 fuse1_rtt_ctl 20 21 fuse1_refresh_cal_en 22 22 fuse1_spare 23 31 mmDC_COMBOPHYCMREGS6_COMMON_FUSE2 0 0x25ef 4 0 2 fuse2_valid 0 0 fuse2_unpopulated 1 8 fuse2_tx_fifo_ptr 9 13 fuse2_spare 14 31 mmDC_COMBOPHYCMREGS6_COMMON_FUSE3 0 0x25f0 4 0 2 fuse3_valid 0 0 fuse3_unpopulated 1 9 fuse3_ei_det_thresh_sel 10 12 fuse3_spare 29 31 mmDC_COMBOPHYCMREGS6_COMMON_MAR_DEEMPH_NOM 0 0x25f1 4 0 2 tx_margin_nom 0 7 deemph_gen1_nom 8 15 deemph35_gen2_nom 16 23 deemph60_gen2_nom 24 31 mmDC_COMBOPHYCMREGS6_COMMON_LANE_PWRMGMT 0 0x25f2 3 0 2 pgdelay 0 3 pgmask 4 9 vprot_en 11 11 mmDC_COMBOPHYCMREGS6_COMMON_TXCNTRL 0 0x25f3 7 0 2 rdptr_rst_val_gen3 0 4 clkgate_dis 5 5 slew_rate_ctl_gen1 6 8 slew_rate_ctl_gen2 9 11 slew_rate_ctl_gen3 12 14 dual_dvi_mstr_en 15 15 dual_dvi_en 16 16 mmDC_COMBOPHYCMREGS6_COMMON_TMDP 0 0x25f4 1 0 2 tmdp_spare 0 31 mmDC_COMBOPHYCMREGS6_COMMON_LANE_RESETS 0 0x25f5 8 0 2 lane_0_reset_l 0 0 lane_1_reset_l 1 1 lane_2_reset_l 2 2 lane_3_reset_l 3 3 lane_4_reset_l 4 4 lane_5_reset_l 5 5 lane_6_reset_l 6 6 lane_7_reset_l 7 7 mmDC_COMBOPHYCMREGS6_COMMON_ZCALCODE_CTRL 0 0x25f6 3 0 2 zcalcode_override 0 0 tx_binary_code_override_val 1 5 tx_driver_fifty_ohms 21 21 mmDC_COMBOPHYCMREGS6_COMMON_DISP_RFU1 0 0x25f7 1 0 2 rfu_value1 0 31 mmDC_COMBOPHYCMREGS6_COMMON_DISP_RFU2 0 0x25f8 1 0 2 rfu_value2 0 31 mmDC_COMBOPHYCMREGS6_COMMON_DISP_RFU3 0 0x25f9 1 0 2 rfu_value3 0 31 mmDC_COMBOPHYCMREGS6_COMMON_DISP_RFU4 0 0x25fa 1 0 2 rfu_value4 0 31 mmDC_COMBOPHYCMREGS6_COMMON_DISP_RFU5 0 0x25fb 1 0 2 rfu_value5 0 31 mmDC_COMBOPHYCMREGS6_COMMON_DISP_RFU6 0 0x25fc 1 0 2 rfu_value6 0 31 mmDC_COMBOPHYCMREGS6_COMMON_DISP_RFU7 0 0x25fd 1 0 2 rfu_value7 0 31 mmDC_COMBOPHYTXREGS6_CMD_BUS_TX_CONTROL_LANE0 0 0x260e 3 0 2 tx_pwr 0 2 tx_pg_en 3 4 tx_rdy 8 8 mmDC_COMBOPHYTXREGS6_MARGIN_DEEMPH_LANE0 0 0x260f 3 0 2 txmarg_sel 0 2 deemph_sel 3 4 tx_margin_en 5 5 mmDC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE0 0 0x2610 12 0 2 twosym_en 1 2 link_speed 3 4 gang_mode 5 7 max_linkrate 8 9 pcs_freq 10 11 pcs_clken 12 12 pcs_clkdone 13 13 pll1_always_on 14 14 rdclk_div2_en 15 15 tx_boost_adj 16 19 tx_boost_en 20 20 tx_binary_ron_code_offset 22 23 mmDC_COMBOPHYTXREGS6_TX_DISP_RFU0_LANE0 0 0x2611 1 0 2 rfu_value0 0 31 mmDC_COMBOPHYTXREGS6_TX_DISP_RFU1_LANE0 0 0x2612 1 0 2 rfu_value1 0 31 mmDC_COMBOPHYTXREGS6_TX_DISP_RFU2_LANE0 0 0x2613 1 0 2 rfu_value2 0 31 mmDC_COMBOPHYTXREGS6_TX_DISP_RFU3_LANE0 0 0x2614 1 0 2 rfu_value3 0 31 mmDC_COMBOPHYTXREGS6_TX_DISP_RFU4_LANE0 0 0x2615 1 0 2 rfu_value4 0 31 mmDC_COMBOPHYTXREGS6_TX_DISP_RFU5_LANE0 0 0x2616 1 0 2 rfu_value5 0 31 mmDC_COMBOPHYTXREGS6_TX_DISP_RFU6_LANE0 0 0x2617 1 0 2 rfu_value6 0 31 mmDC_COMBOPHYTXREGS6_TX_DISP_RFU7_LANE0 0 0x2618 1 0 2 rfu_value7 0 31 mmDC_COMBOPHYTXREGS6_TX_DISP_RFU8_LANE0 0 0x2619 1 0 2 rfu_value8 0 31 mmDC_COMBOPHYTXREGS6_TX_DISP_RFU9_LANE0 0 0x261a 1 0 2 rfu_value9 0 31 mmDC_COMBOPHYTXREGS6_TX_DISP_RFU10_LANE0 0 0x261b 1 0 2 rfu_value10 0 31 mmDC_COMBOPHYTXREGS6_TX_DISP_RFU11_LANE0 0 0x261c 1 0 2 rfu_value11 0 31 mmDC_COMBOPHYTXREGS6_TX_DISP_RFU12_LANE0 0 0x261d 1 0 2 rfu_value12 0 31 mmDC_COMBOPHYTXREGS6_CMD_BUS_TX_CONTROL_LANE1 0 0x261e 3 0 2 tx_pwr 0 2 tx_pg_en 3 4 tx_rdy 8 8 mmDC_COMBOPHYTXREGS6_MARGIN_DEEMPH_LANE1 0 0x261f 3 0 2 txmarg_sel 0 2 deemph_sel 3 4 tx_margin_en 5 5 mmDC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE1 0 0x2620 12 0 2 twosym_en 1 2 link_speed 3 4 gang_mode 5 7 max_linkrate 8 9 pcs_freq 10 11 pcs_clken 12 12 pcs_clkdone 13 13 pll1_always_on 14 14 rdclk_div2_en 15 15 tx_boost_adj 16 19 tx_boost_en 20 20 tx_binary_ron_code_offset 22 23 mmDC_COMBOPHYTXREGS6_TX_DISP_RFU0_LANE1 0 0x2621 1 0 2 rfu_value0 0 31 mmDC_COMBOPHYTXREGS6_TX_DISP_RFU1_LANE1 0 0x2622 1 0 2 rfu_value1 0 31 mmDC_COMBOPHYTXREGS6_TX_DISP_RFU2_LANE1 0 0x2623 1 0 2 rfu_value2 0 31 mmDC_COMBOPHYTXREGS6_TX_DISP_RFU3_LANE1 0 0x2624 1 0 2 rfu_value3 0 31 mmDC_COMBOPHYTXREGS6_TX_DISP_RFU4_LANE1 0 0x2625 1 0 2 rfu_value4 0 31 mmDC_COMBOPHYTXREGS6_TX_DISP_RFU5_LANE1 0 0x2626 1 0 2 rfu_value5 0 31 mmDC_COMBOPHYTXREGS6_TX_DISP_RFU6_LANE1 0 0x2627 1 0 2 rfu_value6 0 31 mmDC_COMBOPHYTXREGS6_TX_DISP_RFU7_LANE1 0 0x2628 1 0 2 rfu_value7 0 31 mmDC_COMBOPHYTXREGS6_TX_DISP_RFU8_LANE1 0 0x2629 1 0 2 rfu_value8 0 31 mmDC_COMBOPHYTXREGS6_TX_DISP_RFU9_LANE1 0 0x262a 1 0 2 rfu_value9 0 31 mmDC_COMBOPHYTXREGS6_TX_DISP_RFU10_LANE1 0 0x262b 1 0 2 rfu_value10 0 31 mmDC_COMBOPHYTXREGS6_TX_DISP_RFU11_LANE1 0 0x262c 1 0 2 rfu_value11 0 31 mmDC_COMBOPHYTXREGS6_TX_DISP_RFU12_LANE1 0 0x262d 1 0 2 rfu_value12 0 31 mmDC_COMBOPHYTXREGS6_CMD_BUS_TX_CONTROL_LANE2 0 0x262e 3 0 2 tx_pwr 0 2 tx_pg_en 3 4 tx_rdy 8 8 mmDC_COMBOPHYTXREGS6_MARGIN_DEEMPH_LANE2 0 0x262f 3 0 2 txmarg_sel 0 2 deemph_sel 3 4 tx_margin_en 5 5 mmDC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE2 0 0x2630 12 0 2 twosym_en 1 2 link_speed 3 4 gang_mode 5 7 max_linkrate 8 9 pcs_freq 10 11 pcs_clken 12 12 pcs_clkdone 13 13 pll1_always_on 14 14 rdclk_div2_en 15 15 tx_boost_adj 16 19 tx_boost_en 20 20 tx_binary_ron_code_offset 22 23 mmDC_COMBOPHYTXREGS6_TX_DISP_RFU0_LANE2 0 0x2631 1 0 2 rfu_value0 0 31 mmDC_COMBOPHYTXREGS6_TX_DISP_RFU1_LANE2 0 0x2632 1 0 2 rfu_value1 0 31 mmDC_COMBOPHYTXREGS6_TX_DISP_RFU2_LANE2 0 0x2633 1 0 2 rfu_value2 0 31 mmDC_COMBOPHYTXREGS6_TX_DISP_RFU3_LANE2 0 0x2634 1 0 2 rfu_value3 0 31 mmDC_COMBOPHYTXREGS6_TX_DISP_RFU4_LANE2 0 0x2635 1 0 2 rfu_value4 0 31 mmDC_COMBOPHYTXREGS6_TX_DISP_RFU5_LANE2 0 0x2636 1 0 2 rfu_value5 0 31 mmDC_COMBOPHYTXREGS6_TX_DISP_RFU6_LANE2 0 0x2637 1 0 2 rfu_value6 0 31 mmDC_COMBOPHYTXREGS6_TX_DISP_RFU7_LANE2 0 0x2638 1 0 2 rfu_value7 0 31 mmDC_COMBOPHYTXREGS6_TX_DISP_RFU8_LANE2 0 0x2639 1 0 2 rfu_value8 0 31 mmDC_COMBOPHYTXREGS6_TX_DISP_RFU9_LANE2 0 0x263a 1 0 2 rfu_value9 0 31 mmDC_COMBOPHYTXREGS6_TX_DISP_RFU10_LANE2 0 0x263b 1 0 2 rfu_value10 0 31 mmDC_COMBOPHYTXREGS6_TX_DISP_RFU11_LANE2 0 0x263c 1 0 2 rfu_value11 0 31 mmDC_COMBOPHYTXREGS6_TX_DISP_RFU12_LANE2 0 0x263d 1 0 2 rfu_value12 0 31 mmDC_COMBOPHYTXREGS6_CMD_BUS_TX_CONTROL_LANE3 0 0x263e 3 0 2 tx_pwr 0 2 tx_pg_en 3 4 tx_rdy 8 8 mmDC_COMBOPHYTXREGS6_MARGIN_DEEMPH_LANE3 0 0x263f 3 0 2 txmarg_sel 0 2 deemph_sel 3 4 tx_margin_en 5 5 mmDC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE3 0 0x2640 12 0 2 twosym_en 1 2 link_speed 3 4 gang_mode 5 7 max_linkrate 8 9 pcs_freq 10 11 pcs_clken 12 12 pcs_clkdone 13 13 pll1_always_on 14 14 rdclk_div2_en 15 15 tx_boost_adj 16 19 tx_boost_en 20 20 tx_binary_ron_code_offset 22 23 mmDC_COMBOPHYTXREGS6_TX_DISP_RFU0_LANE3 0 0x2641 1 0 2 rfu_value0 0 31 mmDC_COMBOPHYTXREGS6_TX_DISP_RFU1_LANE3 0 0x2642 1 0 2 rfu_value1 0 31 mmDC_COMBOPHYTXREGS6_TX_DISP_RFU2_LANE3 0 0x2643 1 0 2 rfu_value2 0 31 mmDC_COMBOPHYTXREGS6_TX_DISP_RFU3_LANE3 0 0x2644 1 0 2 rfu_value3 0 31 mmDC_COMBOPHYTXREGS6_TX_DISP_RFU4_LANE3 0 0x2645 1 0 2 rfu_value4 0 31 mmDC_COMBOPHYTXREGS6_TX_DISP_RFU5_LANE3 0 0x2646 1 0 2 rfu_value5 0 31 mmDC_COMBOPHYTXREGS6_TX_DISP_RFU6_LANE3 0 0x2647 1 0 2 rfu_value6 0 31 mmDC_COMBOPHYTXREGS6_TX_DISP_RFU7_LANE3 0 0x2648 1 0 2 rfu_value7 0 31 mmDC_COMBOPHYTXREGS6_TX_DISP_RFU8_LANE3 0 0x2649 1 0 2 rfu_value8 0 31 mmDC_COMBOPHYTXREGS6_TX_DISP_RFU9_LANE3 0 0x264a 1 0 2 rfu_value9 0 31 mmDC_COMBOPHYTXREGS6_TX_DISP_RFU10_LANE3 0 0x264b 1 0 2 rfu_value10 0 31 mmDC_COMBOPHYTXREGS6_TX_DISP_RFU11_LANE3 0 0x264c 1 0 2 rfu_value11 0 31 mmDC_COMBOPHYTXREGS6_TX_DISP_RFU12_LANE3 0 0x264d 1 0 2 rfu_value12 0 31 mmDC_COMBOPHYPLLREGS6_FREQ_CTRL0 0 0x264e 2 0 2 fcw0_frac 0 15 fcw0_int 16 24 mmDC_COMBOPHYPLLREGS6_FREQ_CTRL1 0 0x264f 2 0 2 fcw1_frac 0 15 fcw1_int 16 24 mmDC_COMBOPHYPLLREGS6_FREQ_CTRL2 0 0x2650 2 0 2 fcw_denom 0 15 fcw_slew_frac 16 31 mmDC_COMBOPHYPLLREGS6_FREQ_CTRL3 0 0x2651 8 0 2 refclk_div 0 1 vco_pre_div 3 4 fracn_en 6 6 ssc_en 8 8 fcw_sel 10 10 freq_jump_en 12 12 tdc_resolution 16 23 dpll_cfg_1 24 31 mmDC_COMBOPHYPLLREGS6_BW_CTRL_COARSE 0 0x2652 6 0 2 gi_coarse_mant 0 1 gi_coarse_exp 2 5 gp_coarse_mant 7 10 gp_coarse_exp 12 15 nctl_coarse_res 17 22 nctl_coarse_frac_res 24 25 mmDC_COMBOPHYPLLREGS6_BW_CTRL_FINE 0 0x2653 1 0 2 dpll_cfg_3 0 9 mmDC_COMBOPHYPLLREGS6_CAL_CTRL 0 0x2654 9 0 2 bypass_freq_lock 0 0 tdc_cal_en 1 1 tdc_cal_ctrl 3 8 meas_win_sel 9 10 kdco_cal_dis 11 11 kdco_ratio 13 20 kdco_incr_cal_dis 22 22 nctl_adj_dis 23 23 refclk_rate 24 31 mmDC_COMBOPHYPLLREGS6_LOOP_CTRL 0 0x2655 10 0 2 fbdiv_mask_en 0 0 fb_slip_dis 2 2 clk_tdc_sel 4 5 clk_nctl_sel 7 8 sig_del_patt_sel 10 10 nctl_sig_del_dis 12 12 fbclk_track_refclk 14 14 prbs_en 16 16 tdc_clk_gate_en 18 18 phase_offset 20 26 mmDC_COMBOPHYPLLREGS6_VREG_CFG 0 0x2657 14 0 2 bleeder_ac 0 0 bleeder_en 1 1 is_1p2 2 2 reg_obs_sel 3 4 reg_on_mode 5 6 rlad_tap_sel 7 10 reg_off_hi 11 11 reg_off_lo 12 12 scale_driver 13 14 sel_bump 15 15 sel_rladder_x 16 16 short_rc_filt_x 17 17 vref_pwr_on 18 18 dpll_cfg_2 20 27 mmDC_COMBOPHYPLLREGS6_OBSERVE0 0 0x2658 5 0 2 lock_det_tdc_steps 0 4 clear_sticky_lock 6 6 lock_det_dis 8 8 dco_cfg 10 17 anaobs_sel 21 23 mmDC_COMBOPHYPLLREGS6_OBSERVE1 0 0x2659 5 0 2 digobs_sel 0 3 digobs_trig_sel 5 8 digobs_div 10 11 digobs_trig_div 13 14 lock_timer 16 29 mmDC_COMBOPHYPLLREGS6_DFT_OUT 0 0x265a 1 0 2 dft_data 0 31 mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED0 0 0x26b6 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED1 0 0x26b7 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED2 0 0x26b8 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED3 0 0x26b9 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED4 0 0x26ba 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED5 0 0x26bb 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED6 0 0x26bc 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED7 0 0x26bd 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED8 0 0x26be 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED9 0 0x26bf 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED10 0 0x26c0 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED11 0 0x26c1 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED12 0 0x26c2 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED13 0 0x26c3 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED14 0 0x26c4 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED15 0 0x26c5 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED16 0 0x26c6 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED17 0 0x26c7 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED18 0 0x26c8 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED19 0 0x26c9 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED20 0 0x26ca 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED21 0 0x26cb 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED22 0 0x26cc 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED23 0 0x26cd 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED24 0 0x26ce 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED25 0 0x26cf 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED26 0 0x26d0 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED27 0 0x26d1 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED28 0 0x26d2 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED29 0 0x26d3 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED30 0 0x26d4 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED31 0 0x26d5 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED32 0 0x26d6 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED33 0 0x26d7 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED34 0 0x26d8 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED35 0 0x26d9 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED36 0 0x26da 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED37 0 0x26db 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED38 0 0x26dc 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED39 0 0x26dd 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED40 0 0x26de 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED41 0 0x26df 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED42 0 0x26e0 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED43 0 0x26e1 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED44 0 0x26e2 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED45 0 0x26e3 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED46 0 0x26e4 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED47 0 0x26e5 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED48 0 0x26e6 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED49 0 0x26e7 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED50 0 0x26e8 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED51 0 0x26e9 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED52 0 0x26ea 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED53 0 0x26eb 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED54 0 0x26ec 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED55 0 0x26ed 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED56 0 0x26ee 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED57 0 0x26ef 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED58 0 0x26f0 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED59 0 0x26f1 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED60 0 0x26f2 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED61 0 0x26f3 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED62 0 0x26f4 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED63 0 0x26f5 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED64 0 0x26f6 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED65 0 0x26f7 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED66 0 0x26f8 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED67 0 0x26f9 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED68 0 0x26fa 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED69 0 0x26fb 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED70 0 0x26fc 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED71 0 0x26fd 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED72 0 0x26fe 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED73 0 0x26ff 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED74 0 0x2700 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED75 0 0x2701 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED76 0 0x2702 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED77 0 0x2703 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED78 0 0x2704 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED79 0 0x2705 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED80 0 0x2706 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED81 0 0x2707 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED82 0 0x2708 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED83 0 0x2709 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED84 0 0x270a 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED85 0 0x270b 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED86 0 0x270c 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED87 0 0x270d 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED88 0 0x270e 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED89 0 0x270f 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED90 0 0x2710 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED91 0 0x2711 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED92 0 0x2712 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED93 0 0x2713 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED94 0 0x2714 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED95 0 0x2715 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED96 0 0x2716 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED97 0 0x2717 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED98 0 0x2718 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED99 0 0x2719 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED100 0 0x271a 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED101 0 0x271b 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED102 0 0x271c 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED103 0 0x271d 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED104 0 0x271e 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED105 0 0x271f 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED106 0 0x2720 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED107 0 0x2721 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED108 0 0x2722 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED109 0 0x2723 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED110 0 0x2724 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED111 0 0x2725 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED112 0 0x2726 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED113 0 0x2727 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED114 0 0x2728 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED115 0 0x2729 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED116 0 0x272a 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED117 0 0x272b 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED118 0 0x272c 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED119 0 0x272d 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED120 0 0x272e 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED121 0 0x272f 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED122 0 0x2730 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED123 0 0x2731 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED124 0 0x2732 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED125 0 0x2733 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED126 0 0x2734 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED127 0 0x2735 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED128 0 0x2736 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED129 0 0x2737 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED130 0 0x2738 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED131 0 0x2739 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED132 0 0x273a 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED133 0 0x273b 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED134 0 0x273c 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED135 0 0x273d 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED136 0 0x273e 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED137 0 0x273f 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED138 0 0x2740 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED139 0 0x2741 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED140 0 0x2742 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED141 0 0x2743 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED142 0 0x2744 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED143 0 0x2745 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED144 0 0x2746 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED145 0 0x2747 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED146 0 0x2748 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED147 0 0x2749 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED148 0 0x274a 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED149 0 0x274b 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED150 0 0x274c 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED151 0 0x274d 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED152 0 0x274e 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED153 0 0x274f 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED154 0 0x2750 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED155 0 0x2751 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED156 0 0x2752 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED157 0 0x2753 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED158 0 0x2754 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED159 0 0x2755 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDC_COMBOPHYCMREGS8_COMMON_FUSE1 0 0x26b6 11 0 2 fuse1_valid 0 0 fuse1_unpopulated0 1 2 fuse1_ron_override_val 3 8 fuse1_unpopulated1 9 9 fuse1_ron_ctl 10 11 fuse1_unpopulated2 12 12 fuse1_rtt_override_val 13 18 fuse1_unpopulated3 19 19 fuse1_rtt_ctl 20 21 fuse1_refresh_cal_en 22 22 fuse1_spare 23 31 mmDC_COMBOPHYCMREGS8_COMMON_FUSE2 0 0x26b7 4 0 2 fuse2_valid 0 0 fuse2_unpopulated 1 8 fuse2_tx_fifo_ptr 9 13 fuse2_spare 14 31 mmDC_COMBOPHYCMREGS8_COMMON_FUSE3 0 0x26b8 4 0 2 fuse3_valid 0 0 fuse3_unpopulated 1 9 fuse3_ei_det_thresh_sel 10 12 fuse3_spare 29 31 mmDC_COMBOPHYCMREGS8_COMMON_MAR_DEEMPH_NOM 0 0x26b9 4 0 2 tx_margin_nom 0 7 deemph_gen1_nom 8 15 deemph35_gen2_nom 16 23 deemph60_gen2_nom 24 31 mmDC_COMBOPHYCMREGS8_COMMON_LANE_PWRMGMT 0 0x26ba 3 0 2 pgdelay 0 3 pgmask 4 9 vprot_en 11 11 mmDC_COMBOPHYCMREGS8_COMMON_TXCNTRL 0 0x26bb 7 0 2 rdptr_rst_val_gen3 0 4 clkgate_dis 5 5 slew_rate_ctl_gen1 6 8 slew_rate_ctl_gen2 9 11 slew_rate_ctl_gen3 12 14 dual_dvi_mstr_en 15 15 dual_dvi_en 16 16 mmDC_COMBOPHYCMREGS8_COMMON_TMDP 0 0x26bc 1 0 2 tmdp_spare 0 31 mmDC_COMBOPHYCMREGS8_COMMON_LANE_RESETS 0 0x26bd 8 0 2 lane_0_reset_l 0 0 lane_1_reset_l 1 1 lane_2_reset_l 2 2 lane_3_reset_l 3 3 lane_4_reset_l 4 4 lane_5_reset_l 5 5 lane_6_reset_l 6 6 lane_7_reset_l 7 7 mmDC_COMBOPHYCMREGS8_COMMON_ZCALCODE_CTRL 0 0x26be 3 0 2 zcalcode_override 0 0 tx_binary_code_override_val 1 5 tx_driver_fifty_ohms 21 21 mmDC_COMBOPHYCMREGS8_COMMON_DISP_RFU1 0 0x26bf 1 0 2 rfu_value1 0 31 mmDC_COMBOPHYCMREGS8_COMMON_DISP_RFU2 0 0x26c0 1 0 2 rfu_value2 0 31 mmDC_COMBOPHYCMREGS8_COMMON_DISP_RFU3 0 0x26c1 1 0 2 rfu_value3 0 31 mmDC_COMBOPHYCMREGS8_COMMON_DISP_RFU4 0 0x26c2 1 0 2 rfu_value4 0 31 mmDC_COMBOPHYCMREGS8_COMMON_DISP_RFU5 0 0x26c3 1 0 2 rfu_value5 0 31 mmDC_COMBOPHYCMREGS8_COMMON_DISP_RFU6 0 0x26c4 1 0 2 rfu_value6 0 31 mmDC_COMBOPHYCMREGS8_COMMON_DISP_RFU7 0 0x26c5 1 0 2 rfu_value7 0 31 mmDC_COMBOPHYTXREGS8_CMD_BUS_TX_CONTROL_LANE0 0 0x26d6 3 0 2 tx_pwr 0 2 tx_pg_en 3 4 tx_rdy 8 8 mmDC_COMBOPHYTXREGS8_MARGIN_DEEMPH_LANE0 0 0x26d7 3 0 2 txmarg_sel 0 2 deemph_sel 3 4 tx_margin_en 5 5 mmDC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE0 0 0x26d8 12 0 2 twosym_en 1 2 link_speed 3 4 gang_mode 5 7 max_linkrate 8 9 pcs_freq 10 11 pcs_clken 12 12 pcs_clkdone 13 13 pll1_always_on 14 14 rdclk_div2_en 15 15 tx_boost_adj 16 19 tx_boost_en 20 20 tx_binary_ron_code_offset 22 23 mmDC_COMBOPHYTXREGS8_TX_DISP_RFU0_LANE0 0 0x26d9 1 0 2 rfu_value0 0 31 mmDC_COMBOPHYTXREGS8_TX_DISP_RFU1_LANE0 0 0x26da 1 0 2 rfu_value1 0 31 mmDC_COMBOPHYTXREGS8_TX_DISP_RFU2_LANE0 0 0x26db 1 0 2 rfu_value2 0 31 mmDC_COMBOPHYTXREGS8_TX_DISP_RFU3_LANE0 0 0x26dc 1 0 2 rfu_value3 0 31 mmDC_COMBOPHYTXREGS8_TX_DISP_RFU4_LANE0 0 0x26dd 1 0 2 rfu_value4 0 31 mmDC_COMBOPHYTXREGS8_TX_DISP_RFU5_LANE0 0 0x26de 1 0 2 rfu_value5 0 31 mmDC_COMBOPHYTXREGS8_TX_DISP_RFU6_LANE0 0 0x26df 1 0 2 rfu_value6 0 31 mmDC_COMBOPHYTXREGS8_TX_DISP_RFU7_LANE0 0 0x26e0 1 0 2 rfu_value7 0 31 mmDC_COMBOPHYTXREGS8_TX_DISP_RFU8_LANE0 0 0x26e1 1 0 2 rfu_value8 0 31 mmDC_COMBOPHYTXREGS8_TX_DISP_RFU9_LANE0 0 0x26e2 1 0 2 rfu_value9 0 31 mmDC_COMBOPHYTXREGS8_TX_DISP_RFU10_LANE0 0 0x26e3 1 0 2 rfu_value10 0 31 mmDC_COMBOPHYTXREGS8_TX_DISP_RFU11_LANE0 0 0x26e4 1 0 2 rfu_value11 0 31 mmDC_COMBOPHYTXREGS8_TX_DISP_RFU12_LANE0 0 0x26e5 1 0 2 rfu_value12 0 31 mmDC_COMBOPHYTXREGS8_CMD_BUS_TX_CONTROL_LANE1 0 0x26e6 3 0 2 tx_pwr 0 2 tx_pg_en 3 4 tx_rdy 8 8 mmDC_COMBOPHYTXREGS8_MARGIN_DEEMPH_LANE1 0 0x26e7 3 0 2 txmarg_sel 0 2 deemph_sel 3 4 tx_margin_en 5 5 mmDC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE1 0 0x26e8 12 0 2 twosym_en 1 2 link_speed 3 4 gang_mode 5 7 max_linkrate 8 9 pcs_freq 10 11 pcs_clken 12 12 pcs_clkdone 13 13 pll1_always_on 14 14 rdclk_div2_en 15 15 tx_boost_adj 16 19 tx_boost_en 20 20 tx_binary_ron_code_offset 22 23 mmDC_COMBOPHYTXREGS8_TX_DISP_RFU0_LANE1 0 0x26e9 1 0 2 rfu_value0 0 31 mmDC_COMBOPHYTXREGS8_TX_DISP_RFU1_LANE1 0 0x26ea 1 0 2 rfu_value1 0 31 mmDC_COMBOPHYTXREGS8_TX_DISP_RFU2_LANE1 0 0x26eb 1 0 2 rfu_value2 0 31 mmDC_COMBOPHYTXREGS8_TX_DISP_RFU3_LANE1 0 0x26ec 1 0 2 rfu_value3 0 31 mmDC_COMBOPHYTXREGS8_TX_DISP_RFU4_LANE1 0 0x26ed 1 0 2 rfu_value4 0 31 mmDC_COMBOPHYTXREGS8_TX_DISP_RFU5_LANE1 0 0x26ee 1 0 2 rfu_value5 0 31 mmDC_COMBOPHYTXREGS8_TX_DISP_RFU6_LANE1 0 0x26ef 1 0 2 rfu_value6 0 31 mmDC_COMBOPHYTXREGS8_TX_DISP_RFU7_LANE1 0 0x26f0 1 0 2 rfu_value7 0 31 mmDC_COMBOPHYTXREGS8_TX_DISP_RFU8_LANE1 0 0x26f1 1 0 2 rfu_value8 0 31 mmDC_COMBOPHYTXREGS8_TX_DISP_RFU9_LANE1 0 0x26f2 1 0 2 rfu_value9 0 31 mmDC_COMBOPHYTXREGS8_TX_DISP_RFU10_LANE1 0 0x26f3 1 0 2 rfu_value10 0 31 mmDC_COMBOPHYTXREGS8_TX_DISP_RFU11_LANE1 0 0x26f4 1 0 2 rfu_value11 0 31 mmDC_COMBOPHYTXREGS8_TX_DISP_RFU12_LANE1 0 0x26f5 1 0 2 rfu_value12 0 31 mmDC_COMBOPHYTXREGS8_CMD_BUS_TX_CONTROL_LANE2 0 0x26f6 3 0 2 tx_pwr 0 2 tx_pg_en 3 4 tx_rdy 8 8 mmDC_COMBOPHYTXREGS8_MARGIN_DEEMPH_LANE2 0 0x26f7 3 0 2 txmarg_sel 0 2 deemph_sel 3 4 tx_margin_en 5 5 mmDC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE2 0 0x26f8 12 0 2 twosym_en 1 2 link_speed 3 4 gang_mode 5 7 max_linkrate 8 9 pcs_freq 10 11 pcs_clken 12 12 pcs_clkdone 13 13 pll1_always_on 14 14 rdclk_div2_en 15 15 tx_boost_adj 16 19 tx_boost_en 20 20 tx_binary_ron_code_offset 22 23 mmDC_COMBOPHYTXREGS8_TX_DISP_RFU0_LANE2 0 0x26f9 1 0 2 rfu_value0 0 31 mmDC_COMBOPHYTXREGS8_TX_DISP_RFU1_LANE2 0 0x26fa 1 0 2 rfu_value1 0 31 mmDC_COMBOPHYTXREGS8_TX_DISP_RFU2_LANE2 0 0x26fb 1 0 2 rfu_value2 0 31 mmDC_COMBOPHYTXREGS8_TX_DISP_RFU3_LANE2 0 0x26fc 1 0 2 rfu_value3 0 31 mmDC_COMBOPHYTXREGS8_TX_DISP_RFU4_LANE2 0 0x26fd 1 0 2 rfu_value4 0 31 mmDC_COMBOPHYTXREGS8_TX_DISP_RFU5_LANE2 0 0x26fe 1 0 2 rfu_value5 0 31 mmDC_COMBOPHYTXREGS8_TX_DISP_RFU6_LANE2 0 0x26ff 1 0 2 rfu_value6 0 31 mmDC_COMBOPHYTXREGS8_TX_DISP_RFU7_LANE2 0 0x2700 1 0 2 rfu_value7 0 31 mmDC_COMBOPHYTXREGS8_TX_DISP_RFU8_LANE2 0 0x2701 1 0 2 rfu_value8 0 31 mmDC_COMBOPHYTXREGS8_TX_DISP_RFU9_LANE2 0 0x2702 1 0 2 rfu_value9 0 31 mmDC_COMBOPHYTXREGS8_TX_DISP_RFU10_LANE2 0 0x2703 1 0 2 rfu_value10 0 31 mmDC_COMBOPHYTXREGS8_TX_DISP_RFU11_LANE2 0 0x2704 1 0 2 rfu_value11 0 31 mmDC_COMBOPHYTXREGS8_TX_DISP_RFU12_LANE2 0 0x2705 1 0 2 rfu_value12 0 31 mmDC_COMBOPHYTXREGS8_CMD_BUS_TX_CONTROL_LANE3 0 0x2706 3 0 2 tx_pwr 0 2 tx_pg_en 3 4 tx_rdy 8 8 mmDC_COMBOPHYTXREGS8_MARGIN_DEEMPH_LANE3 0 0x2707 3 0 2 txmarg_sel 0 2 deemph_sel 3 4 tx_margin_en 5 5 mmDC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE3 0 0x2708 12 0 2 twosym_en 1 2 link_speed 3 4 gang_mode 5 7 max_linkrate 8 9 pcs_freq 10 11 pcs_clken 12 12 pcs_clkdone 13 13 pll1_always_on 14 14 rdclk_div2_en 15 15 tx_boost_adj 16 19 tx_boost_en 20 20 tx_binary_ron_code_offset 22 23 mmDC_COMBOPHYTXREGS8_TX_DISP_RFU0_LANE3 0 0x2709 1 0 2 rfu_value0 0 31 mmDC_COMBOPHYTXREGS8_TX_DISP_RFU1_LANE3 0 0x270a 1 0 2 rfu_value1 0 31 mmDC_COMBOPHYTXREGS8_TX_DISP_RFU2_LANE3 0 0x270b 1 0 2 rfu_value2 0 31 mmDC_COMBOPHYTXREGS8_TX_DISP_RFU3_LANE3 0 0x270c 1 0 2 rfu_value3 0 31 mmDC_COMBOPHYTXREGS8_TX_DISP_RFU4_LANE3 0 0x270d 1 0 2 rfu_value4 0 31 mmDC_COMBOPHYTXREGS8_TX_DISP_RFU5_LANE3 0 0x270e 1 0 2 rfu_value5 0 31 mmDC_COMBOPHYTXREGS8_TX_DISP_RFU6_LANE3 0 0x270f 1 0 2 rfu_value6 0 31 mmDC_COMBOPHYTXREGS8_TX_DISP_RFU7_LANE3 0 0x2710 1 0 2 rfu_value7 0 31 mmDC_COMBOPHYTXREGS8_TX_DISP_RFU8_LANE3 0 0x2711 1 0 2 rfu_value8 0 31 mmDC_COMBOPHYTXREGS8_TX_DISP_RFU9_LANE3 0 0x2712 1 0 2 rfu_value9 0 31 mmDC_COMBOPHYTXREGS8_TX_DISP_RFU10_LANE3 0 0x2713 1 0 2 rfu_value10 0 31 mmDC_COMBOPHYTXREGS8_TX_DISP_RFU11_LANE3 0 0x2714 1 0 2 rfu_value11 0 31 mmDC_COMBOPHYTXREGS8_TX_DISP_RFU12_LANE3 0 0x2715 1 0 2 rfu_value12 0 31 mmDC_COMBOPHYPLLREGS8_FREQ_CTRL0 0 0x2716 2 0 2 fcw0_frac 0 15 fcw0_int 16 24 mmDC_COMBOPHYPLLREGS8_FREQ_CTRL1 0 0x2717 2 0 2 fcw1_frac 0 15 fcw1_int 16 24 mmDC_COMBOPHYPLLREGS8_FREQ_CTRL2 0 0x2718 2 0 2 fcw_denom 0 15 fcw_slew_frac 16 31 mmDC_COMBOPHYPLLREGS8_FREQ_CTRL3 0 0x2719 8 0 2 refclk_div 0 1 vco_pre_div 3 4 fracn_en 6 6 ssc_en 8 8 fcw_sel 10 10 freq_jump_en 12 12 tdc_resolution 16 23 dpll_cfg_1 24 31 mmDC_COMBOPHYPLLREGS8_BW_CTRL_COARSE 0 0x271a 6 0 2 gi_coarse_mant 0 1 gi_coarse_exp 2 5 gp_coarse_mant 7 10 gp_coarse_exp 12 15 nctl_coarse_res 17 22 nctl_coarse_frac_res 24 25 mmDC_COMBOPHYPLLREGS8_BW_CTRL_FINE 0 0x271b 1 0 2 dpll_cfg_3 0 9 mmDC_COMBOPHYPLLREGS8_CAL_CTRL 0 0x271c 9 0 2 bypass_freq_lock 0 0 tdc_cal_en 1 1 tdc_cal_ctrl 3 8 meas_win_sel 9 10 kdco_cal_dis 11 11 kdco_ratio 13 20 kdco_incr_cal_dis 22 22 nctl_adj_dis 23 23 refclk_rate 24 31 mmDC_COMBOPHYPLLREGS8_LOOP_CTRL 0 0x271d 10 0 2 fbdiv_mask_en 0 0 fb_slip_dis 2 2 clk_tdc_sel 4 5 clk_nctl_sel 7 8 sig_del_patt_sel 10 10 nctl_sig_del_dis 12 12 fbclk_track_refclk 14 14 prbs_en 16 16 tdc_clk_gate_en 18 18 phase_offset 20 26 mmDC_COMBOPHYPLLREGS8_VREG_CFG 0 0x271f 14 0 2 bleeder_ac 0 0 bleeder_en 1 1 is_1p2 2 2 reg_obs_sel 3 4 reg_on_mode 5 6 rlad_tap_sel 7 10 reg_off_hi 11 11 reg_off_lo 12 12 scale_driver 13 14 sel_bump 15 15 sel_rladder_x 16 16 short_rc_filt_x 17 17 vref_pwr_on 18 18 dpll_cfg_2 20 27 mmDC_COMBOPHYPLLREGS8_OBSERVE0 0 0x2720 5 0 2 lock_det_tdc_steps 0 4 clear_sticky_lock 6 6 lock_det_dis 8 8 dco_cfg 10 17 anaobs_sel 21 23 mmDC_COMBOPHYPLLREGS8_OBSERVE1 0 0x2721 5 0 2 digobs_sel 0 3 digobs_trig_sel 5 8 digobs_div 10 11 digobs_trig_div 13 14 lock_timer 16 29 mmDC_COMBOPHYPLLREGS8_DFT_OUT 0 0x2722 1 0 2 dft_data 0 31 mmDSI0_DISP_DSI_CTRL 0 0x27be 22 0 2 DSI_EN 0 0 VIDEO_MODE_EN 1 1 CMD_MODE_EN 2 2 DLN0_EN 4 4 DLN1_EN 5 5 DLN2_EN 6 6 DLN3_EN 7 7 CLKLN_EN 8 8 DLN0_PHY_EN 12 12 DLN1_PHY_EN 13 13 DLN2_PHY_EN 14 14 DLN3_PHY_EN 15 15 RESET_DISPCLK 16 16 RESET_DSICLK 17 17 RESET_BYTECLK 18 18 RESET_ESCCLK 19 19 CRTC_SEL 20 22 ECC_CHK_EN 24 24 CRC_CHK_EN 25 25 PACKET_BYTE_MSB_LSB_FLIP 28 28 PRE_TRIGGER_EN 29 29 NEW_INTERLEAVE_MODE_EN 30 30 mmDSI0_DISP_DSI_STATUS 0 0x27bf 41 0 2 CMD_MODE_ENGINE_BUSY 0 0 CMD_MODE_DMA_BUSY 1 1 CMD_MODE_DENG_BUSY 2 2 VIDEO_MODE_ENGINE_BUSY 3 3 BTA_BUSY 4 4 GENERIC_TRIGGER_BUSY 5 5 PHY_RESET_BUSY 6 6 DLN0_HS_FIFO_EMPTY 8 8 DLN0_HS_FIFO_FULL 9 9 DLN1_HS_FIFO_EMPTY 10 10 DLN1_HS_FIFO_FULL 11 11 DLN2_HS_FIFO_EMPTY 12 12 DLN2_HS_FIFO_FULL 13 13 DLN3_HS_FIFO_EMPTY 14 14 DLN3_HS_FIFO_FULL 15 15 DLN0_HS_FIFO_OVERFLOW 16 16 DLN0_HS_FIFO_OVERFLOW_CLR 16 16 DLN1_HS_FIFO_OVERFLOW 17 17 DLN1_HS_FIFO_OVERFLOW_CLR 17 17 DLN2_HS_FIFO_OVERFLOW 18 18 DLN2_HS_FIFO_OVERFLOW_CLR 18 18 DLN3_HS_FIFO_OVERFLOW 19 19 DLN3_HS_FIFO_OVERFLOW_CLR 19 19 DLN0_LP_FIFO_EMPTY 20 20 DLN0_LP_FIFO_FULL 21 21 DLN0_LP_FIFO_OVERFLOW 22 22 DLN0_LP_FIFO_OVERFLOW_CLR 22 22 CMDFIFO_UNDERFLOW 23 23 CMDFIFO_UNDERFLOW_CLR 23 23 INTERLEAVE_PACKET_BLOCK 24 24 INTERLEAVE_PACKET_BLOCK_CLR 24 24 TE_ABORT 25 25 TE_ABORT_CLR 25 25 DMAFIFO_RD_WATERMARK_REACH 28 28 DMAFIFO_RD_WATERMARK_REACH_CLR 28 28 DMAFIFO_WR_WATERMARK_REACH 29 29 DMAFIFO_WR_WATERMARK_REACH_CLR 29 29 DMAFIFO_UNDERFLOW 30 30 DMAFIFO_UNDERFLOW_CLR 30 30 INTERLEAVE_OP_CONTENTION 31 31 INTERLEAVE_OP_CONTENTION_CLR 31 31 mmDSI0_DISP_DSI_VIDEO_MODE_CTRL 0 0x27c0 9 0 2 VC 0 1 DST_FORMAT 4 5 TRAFFIC_MODE 8 9 BLLP_PWR_MODE 12 12 EOF_BLLP_PWR_MODE 15 15 HSA_PWR_MODE 16 16 HBP_PWR_MODE 20 20 HFP_PWR_MODE 24 24 PULSE_MODE_OPT 28 28 mmDSI0_DISP_DSI_VIDEO_MODE_SYNC_DATATYPE 0 0x27c1 4 0 2 VS 0 5 VE 8 13 HS 16 21 HE 24 29 mmDSI0_DISP_DSI_VIDEO_MODE_VSYNC_PAYLOAD 0 0x27c2 2 0 2 VS_PAYLOAD 0 15 VE_PAYLOAD 16 31 mmDSI0_DISP_DSI_VIDEO_MODE_HSYNC_PAYLOAD 0 0x27c3 2 0 2 HS_PAYLOAD 0 15 HE_PAYLOAD 16 31 mmDSI0_DISP_DSI_VIDEO_MODE_PIXEL_DATATYPE 0 0x27c4 4 0 2 RGB565 0 5 RGB666_PACKED 8 13 RGB666 16 21 RGB888 24 29 mmDSI0_DISP_DSI_VIDEO_MODE_BLANKING_DATATYPE 0 0x27c5 2 0 2 BLANK_PKT_DATA 0 7 BLANK_PKT_DATATYPE 8 13 mmDSI0_DISP_DSI_VIDEO_MODE_DATA_CTRL 0 0x27c6 4 0 2 R_SEL 0 0 G_SEL 4 4 B_SEL 8 8 RGB_SWAP 12 14 mmDSI0_DISP_DSI_COMMAND_MODE_CTRL 0 0x27c7 7 0 2 WC 0 15 DT 16 21 VC 22 23 PACKET_TYPE 24 24 POWER_MODE 26 26 EMBEDDED_MODE 28 28 CMD_DATA_ORDER 31 31 mmDSI0_DISP_DSI_COMMAND_MODE_DATA_CTRL 0 0x27c8 9 0 2 SRC_FORMAT 0 3 DST_FORMAT 4 7 DATA_BUFFER_ID 8 8 SHADOW_DATA_BUFFER_ID 12 12 R_SEL 16 16 G_SEL 17 17 B_SEL 18 18 RGB_SWAP 20 22 DWORD_BYTE_SWAP 24 25 mmDSI0_DISP_DSI_COMMAND_MODE_DCS_CMD_CTRL 0 0x27c9 3 0 2 WR_MEM_START 0 7 WR_MEM_CONTINUE 8 15 INSERT_DCS_COMMAND 16 16 mmDSI0_DISP_DSI_DMA_CMD_OFFSET 0 0x27ca 1 0 2 CMD_OFFSET 0 31 mmDSI0_DISP_DSI_DMA_CMD_LENGTH 0 0x27cb 1 0 2 CMD_LENGTH 0 23 mmDSI0_DISP_DSI_DMA_DATA_OFFSET_0 0 0x27cc 1 0 2 DATA_SRC_OFFSET0 0 31 mmDSI0_DISP_DSI_DMA_DATA_OFFSET_1 0 0x27cd 1 0 2 DATA_SRC_OFFSET1 0 31 mmDSI0_DISP_DSI_DMA_DATA_PITCH 0 0x27ce 1 0 2 DATA_SRC_PITCH 0 14 mmDSI0_DISP_DSI_DMA_DATA_WIDTH 0 0x27cf 2 0 2 DATA_SRC_WIDTH 0 19 DATA_SRC_WIDTH_ALIGN 24 26 mmDSI0_DISP_DSI_DMA_DATA_HEIGHT 0 0x27d0 1 0 2 DATA_SRC_HEIGHT 0 11 mmDSI0_DISP_DSI_DMA_FIFO_CTRL 0 0x27d1 2 0 2 WRITE_WATERMARK 0 1 READ_WATERMARK 4 5 mmDSI0_DISP_DSI_DMA_NULL_PACKET_DATA 0 0x27d2 2 0 2 NULL_DATA 0 7 NULL_DATATYPE 8 13 mmDSI0_DISP_DSI_DENG_DATA_LENGTH 0 0x27d3 2 0 2 DENG_LENGTH 0 23 USE_DENG_LENGTH 31 31 mmDSI0_DISP_DSI_ACK_ERROR_REPORT 0 0x27d4 42 0 2 SOT_ERR 0 0 SOT_ERR_CLR 0 0 SOT_SYNC_ERR 1 1 SOT_SYNC_ERR_CLR 1 1 EOT_ERR 2 2 EOT_ERR_CLR 2 2 ESC_ERR 3 3 ESC_ERR_CLR 3 3 LP_ERR 4 4 LP_ERR_CLR 4 4 HRX_TO 5 5 HRX_TO_CLR 5 5 FALSE_CTRL_ERR 6 6 FALSE_CTRL_ERR_CLR 6 6 CONTENTION_ERR 7 7 CONTENTION_ERR_CLR 7 7 ECC_ERR 8 8 ECC_ERR_CLR 8 8 MULTI_ECC_ERR 9 9 MULTI_ECC_ERR_CLR 9 9 CRC_ERR 10 10 CRC_ERR_CLR 10 10 DT_ERR 11 11 DT_ERR_CLR 11 11 VC_ERR 12 12 VC_ERR_CLR 12 12 PROTOCOL_VIOLATION 13 13 PROTOCOL_VIOLATION_CLR 13 13 PANEL_SPECIFIC_ERR 15 15 PANEL_SPECIFIC_ERR_CLR 15 15 RDBK_DATA_ECC_ERR 16 16 RDBK_DATA_ECC_ERR_CLR 16 16 RDBK_DATA_MULTI_ECC_ERR 17 17 RDBK_DATA_MULTI_ECC_ERR_CLR 17 17 RDBK_DATA_CRC_ERR 20 20 RDBK_DATA_CRC_ERR_CLR 20 20 RDBK_INCOMPLETE_PACKET_ERR 23 23 RDBK_INCOMPLETE_PACKET_ERR_CLR 23 23 ERROR 24 24 ERROR_CLR 24 24 ACK 28 28 ACK_CLR 28 28 mmDSI0_DISP_DSI_RDBK_DATA0 0 0x27d5 1 0 2 RD_DATA0 0 31 mmDSI0_DISP_DSI_RDBK_DATA1 0 0x27d6 1 0 2 RD_DATA1 0 31 mmDSI0_DISP_DSI_RDBK_DATA2 0 0x27d7 1 0 2 RD_DATA2 0 31 mmDSI0_DISP_DSI_RDBK_DATA3 0 0x27d8 1 0 2 RD_DATA3 0 31 mmDSI0_DISP_DSI_RDBK_DATATYPE0 0 0x27d9 4 0 2 GENERIC_SHORT_RD_1_BYTE 0 5 GENERIC_SHORT_RD_2_BYTE 8 13 DCS_SHORT_RD_1_BYTE 16 21 DCS_SHORT_RD_2_BYTE 24 29 mmDSI0_DISP_DSI_RDBK_DATATYPE1 0 0x27da 3 0 2 ERROR_REPORT 0 5 GENERIC_LONG_RD 8 13 DCS_LONG_RD 16 21 mmDSI0_DISP_DSI_TRIG_CTRL 0 0x27db 7 0 2 COMMAND_MODE_DMA_TRIGGER_MODE 0 0 COMMAND_MODE_DMA_TRIGGER_SEL 4 5 COMMAND_MODE_DENG_TRIGGER_MODE 16 16 COMMAND_MODE_DENG_TRIGGER_SEL 20 21 HW_SOURCE_SEL 24 27 COMMAND_MODE_DMA_DENG_ORDER 28 28 TE_SEL 31 31 mmDSI0_DISP_DSI_EXT_MUX 0 0x27dc 6 0 2 EXT_TE_MUX 0 3 EXT_TE_MODE 4 5 EXT_RESET_POL 6 6 EXT_TE_POL 7 7 EXT_TE_HSYNC_TRIG_CNT 8 19 EXT_TE_HSYNC_TOTAL 20 31 mmDSI0_DISP_DSI_EXT_TE_PULSE_DETECTION_CTRL 0 0x27dd 2 0 2 TE_HSYNC_MAX_WIDTH 0 15 TE_VSYNC_MIN_WIDTH 16 31 mmDSI0_DISP_DSI_CMD_MODE_DMA_SW_TRIGGER 0 0x27de 1 0 2 SW_TRIGGER 0 0 mmDSI0_DISP_DSI_CMD_MODE_DENG_SW_TRIGGER 0 0x27df 1 0 2 SW_TRIGGER 0 0 mmDSI0_DISP_DSI_CMD_MODE_BTA_SW_TRIGGER 0 0x27e0 1 0 2 SW_TRIGGER 0 0 mmDSI0_DISP_DSI_RESET_SW_TRIGGER 0 0x27e1 1 0 2 SW_TRIGGER 0 0 mmDSI0_DISP_DSI_EXT_RESET 0 0x27e2 1 0 2 RESET_PANEL 0 0 mmDSI0_DISP_DSI_LANE_CRC_HS_MODE 0 0x27e3 4 0 2 DLN0_HS_CRC 0 7 DLN1_HS_CRC 8 15 DLN2_HS_CRC 16 23 DLN3_HS_CRC 24 31 mmDSI0_DISP_DSI_LANE_CRC_LP_MODE 0 0x27e4 1 0 2 DLN0_LP_CRC 0 7 mmDSI0_DISP_DSI_LANE_CRC_CTRL 0 0x27e5 5 0 2 CRC_MAX_HS_DONE_COUNT 0 7 CRC_MAX_LP_DONE_COUNT 8 15 CRC_ENABLE 16 16 CRC_DONE_HS 20 20 CRC_DONE_LP 24 24 mmDSI0_DISP_DSI_PIXEL_CRC_CTRL 0 0x27e6 3 0 2 CRC_MAX_PIXEL_COUNT 0 7 PIXEL_CRC 8 15 CRC_DONE_PIXEL 16 16 mmDSI0_DISP_DSI_LANE_CTRL 0 0x27e7 16 0 2 DLN0_ULPS_REQUEST 0 0 DLN1_ULPS_REQUEST 1 1 DLN2_ULPS_REQUEST 2 2 DLN3_ULPS_REQUEST 3 3 DLN0_ULPS_EXIT 4 4 DLN1_ULPS_EXIT 5 5 DLN2_ULPS_EXIT 6 6 DLN3_ULPS_EXIT 7 7 DLN0_FORCE_TX_STOP 8 8 DLN1_FORCE_TX_STOP 9 9 DLN2_FORCE_TX_STOP 10 10 DLN3_FORCE_TX_STOP 11 11 CLKLN_ULPS_REQUEST 12 12 CLKLN_ULPS_EXIT 16 16 CLKLN_FORCE_TX_STOP 20 20 CLKLN_HS_FORCE_REQUEST 24 24 mmDSI0_DISP_DSI_DLN0_PHY_ERROR 0 0x27e8 15 0 2 DLN0_ERR_ESC 0 0 DLN0_ERR_ESC_CLR 0 0 DLN0_ERR_ESC_MASK 3 3 DLN0_ERR_SYNC_ESC 4 4 DLN0_ERR_SYNC_ESC_CLR 4 4 DLN0_ERR_SYNC_ESC_MASK 7 7 DLN0_ERR_CONTROL 8 8 DLN0_ERR_CONTROL_CLR 8 8 DLN0_ERR_CONTROL_MASK 11 11 DLN0_ERR_CONTENTION_LP0 12 12 DLN0_ERR_CONTENTION_LP0_CLR 12 12 DLN0_ERR_CONTENTION_LP0_MASK 15 15 DLN0_ERR_CONTENTION_LP1 16 16 DLN0_ERR_CONTENTION_LP1_CLR 16 16 DLN0_ERR_CONTENTION_LP1_MASK 19 19 mmDSI0_DISP_DSI_LP_TIMER_CTRL 0 0x27e9 2 0 2 LP_RX_TO 0 15 BTA_TO 16 31 mmDSI0_DISP_DSI_HS_TIMER_CTRL 0 0x27ea 1 0 2 HS_TX_TO 0 15 mmDSI0_DISP_DSI_TIMEOUT_STATUS 0 0x27eb 6 0 2 HS_TX_TIMEOUT 0 0 HS_TX_TIMEOUT_CLR 0 0 LP_RX_TIMEOUT 4 4 LP_RX_TIMEOUT_CLR 4 4 BTA_TIMEOUT 8 8 BTA_TIMEOUT_CLR 8 8 mmDSI0_DISP_DSI_PHY_CLK_TIMING_CTRL 0 0x27ec 2 0 2 T_CLK_PRE 0 7 T_CLK_POST 8 13 mmDSI0_DISP_DSI_PHY_CLK_TIMING_CTRL2 0 0x27ed 2 0 2 T_PRE_TRIGGER 0 10 T_INTER_STOP 16 31 mmDSI0_DISP_DSI_EOT_PACKET 0 0x27ee 3 0 2 DI 0 7 WC 8 23 ECC 24 31 mmDSI0_DISP_DSI_EOT_PACKET_CTRL 0 0x27ef 2 0 2 TX_EOT_APPEND 0 0 RX_EOT_IGNORE 4 4 mmDSI0_DISP_DSI_GENERIC_ESC_TX_TRIGGER 0 0x27f0 2 0 2 SW_TRIGGER 0 0 ENTRY_COMMAND 16 23 mmDSI0_DISP_DSI_MIPI_BIST_CTRL 0 0x27f1 2 0 2 MIPI_BIST_RESET 0 0 MIPI_BIST_EN 1 1 mmDSI0_DISP_DSI_MIPI_BIST_FRAME_SIZE 0 0x27f2 2 0 2 MIPI_H_SIZE 0 15 MIPI_V_SIZE 16 31 mmDSI0_DISP_DSI_MIPI_BIST_BLOCK_SIZE 0 0x27f3 2 0 2 MIPI_H_SIZE 0 7 MIPI_V_SIZE 8 15 mmDSI0_DISP_DSI_MIPI_BIST_FRAME_CONFIG 0 0x27f4 3 0 2 MIPI_BLANKING_CYCLES 0 15 MIPI_FRAME_REPEAT 16 23 MIPI_BIST_VIDEO_FRMT 24 24 mmDSI0_DISP_DSI_MIPI_BIST_LSFR_CTRL 0 0x27f5 6 0 2 MIPI_Y_LSFR_POLYNOMIAL 0 7 MIPI_U_LSFR_POLYNOMIAL 8 15 MIPI_V_LSFR_POLYNOMIAL 16 23 MIPI_Y_LSFR_EN 24 24 MIPI_U_LSFR_EN 25 25 MIPI_V_LSFR_EN 26 26 mmDSI0_DISP_DSI_MIPI_BIST_LSFR_INIT 0 0x27f6 3 0 2 MIPI_Y_INIT_LSFR_VAL 0 7 MIPI_U_INIT_LSFR_VAL 8 15 MIPI_V_INIT_LSFR_VAL 16 23 mmDSI0_DISP_DSI_MIPI_BIST_START 0 0x27f7 1 0 2 MIPI_BIST_START 0 0 mmDSI0_DISP_DSI_MIPI_BIST_STATUS 0 0x27f8 3 0 2 MIPI_BIST_STATUS_BUSY 0 0 MIPI_BIST_DONE 4 4 MIPI_BIST_DONE_CLR 4 4 mmDSI0_DISP_DSI_ERROR_INTERRUPT_MASK 0 0x27f9 24 0 2 RDBK_DATA_ECC_ERR_MASK 0 0 RDBK_DATA_MULTI_ECC_ERR_MASK 1 1 RDBK_DATA_CRC_ERR_MASK 2 2 RDBK_INCOMPLETE_PACKET_ERR_MASK 3 3 ERROR_PACKET_MASK 4 4 INTERLEAVE_PACKET_BLOCK_MASK 5 5 TE_ABORT_MASK 6 6 DLN0_ERR_ESC_MASK 8 8 DLN0_ERR_SYNC_ESC_MASK 9 9 DLN0_ERR_CONTROL_MASK 10 10 DLN0_ERR_CONTENTION_LP0_MASK 12 12 DLN0_ERR_CONTENTION_LP1_MASK 13 13 LP_RX_TO_MASK 16 16 HS_TX_TO_MASK 17 17 BTA_TO_MASK 18 18 DMAFIFO_UNDERFLOW_MASK 20 20 CMDFIFO_UNDERFLOW_MASK 21 21 DENGFIFO_OVERFLOW_UNDERFLOW_MASK 24 24 DLN0_HS_FIFO_OVERFLOW_MASK 26 26 DLN1_HS_FIFO_OVERFLOW_MASK 27 27 DLN2_HS_FIFO_OVERFLOW_MASK 28 28 DLN3_HS_FIFO_OVERFLOW_MASK 29 29 DLN0_LP_FIFO_OVERFLOW_MASK 30 30 INTERLEAVE_OP_CONTENTION_MASK 31 31 mmDSI0_DISP_DSI_INTERRUPT_CTRL 0 0x27fa 21 0 2 DSI_CMD_MODE_DMA_DONE_STAT 0 0 DSI_CMD_MODE_DMA_DONE_AK 0 0 DSI_CMD_MODE_DMA_DONE_MASK 1 1 DSI_CMD_MODE_DENG_DONE_STAT 4 4 DSI_CMD_MODE_DENG_DONE_AK 4 4 DSI_CMD_MODE_DENG_DONE_MASK 5 5 DSI_VIDEO_MODE_DONE_STAT 8 8 DSI_VIDEO_MODE_DONE_AK 8 8 DSI_VIDEO_MODE_DONE_MASK 9 9 DSI_ERROR_STAT 12 12 DSI_ERROR_AK 12 12 DSI_ERROR_MASK 13 13 DSI_SW_BTA_DONE_STAT 16 16 DSI_SW_BTA_DONE_AK 16 16 DSI_SW_BTA_DONE_MASK 17 17 DSI_CMDFIFO_DONE_STAT 20 20 DSI_CMDFIFO_DONE_AK 20 20 DSI_CMDFIFO_DONE_MASK 21 21 DSI_CAL_DONE_STAT 24 24 DSI_CAL_DONE_AK 24 24 DSI_CAL_DONE_MASK 25 25 mmDSI0_DISP_DSI_CLK_CTRL 0 0x27fb 8 0 2 DISPCLK_G_ON 0 0 DISPCLK_R_ON 1 1 DSICLK_G_ON 4 4 DSICLK_R_ON 5 5 DSICLK_TRN_ON 6 6 BYTECLK_G_ON 8 8 ESCCLK_G_ON 16 16 TEST_CLK_SEL 24 27 mmDSI0_DISP_DSI_CLK_STATUS 0 0x27fc 7 0 2 DISPCLK_R_ACTIVE 0 0 DISPCLK_G_ACTIVE 1 1 DSICLK_R_ACTIVE 4 4 DSICLK_G_ACTIVE 5 5 DSICLK_TRN_ACTIVE 6 6 BYTECLK_G_ACTIVE 8 8 ESCCLK_G_ACTIVE 16 16 mmDSI0_DISP_DSI_DENG_FIFO_STATUS 0 0x27fd 10 0 2 DENG_FIFO_LEVEL_ERROR 0 0 DENG_FIFO_USE_OVERWRITE_LEVEL 1 1 DENG_FIFO_OVERWRITE_LEVEL 2 8 DENG_FIFO_ERROR_ACK 9 9 DENG_FIFO_CAL_AVERAGE_LEVEL 10 16 DENG_FIFO_MAXIMUM_LEVEL 17 22 DENG_FIFO_MINIMUM_LEVEL 23 27 DENG_FIFO_CALIBRATED 29 29 DENG_FIFO_FORCE_RECAL_AVERAGE 30 30 DENG_FIFO_FORCE_RECOMP_MINMAX 31 31 mmDSI0_DISP_DSI_DENG_FIFO_CTRL 0 0x27fe 3 0 2 DENG_FIFO_EN 0 0 DENG_FIFO_START 4 4 DENG_DSICLK_ON 8 8 mmDSI0_DISP_DSI_CMD_FIFO_DATA 0 0x27ff 1 0 2 CMDFIFO_DATA 0 31 mmDSI0_DISP_DSI_CMD_FIFO_CTRL 0 0x2800 2 0 2 USE_CMDFIFO 0 0 CMDFIFO_DW_LEVEL 4 10 mmDSI0_DISP_DSI_TE_CTRL 0 0x2801 5 0 2 FREEZE_CRTC_HYSTERESIS 0 11 DISABLE_CRTC_FREEZE 16 16 DISABLE_CRTC_FORCE 20 20 CRTC_FREEZE 24 24 CRTC_FREEZE_TRIG 24 24 mmDSI0_DISP_DSI_LANE_STATUS 0 0x2805 11 0 2 DLN0_STOPSTATE 0 0 DLN1_STOPSTATE 1 1 DLN2_STOPSTATE 2 2 DLN3_STOPSTATE 3 3 DLN0_ULPS_ACTIVE_NOT 4 4 DLN1_ULPS_ACTIVE_NOT 5 5 DLN2_ULPS_ACTIVE_NOT 6 6 DLN3_ULPS_ACTIVE_NOT 7 7 DLN0_DIRECTION 8 8 CLKLN_STOPSTATE 24 24 CLKLN_ULPS_ACTIVE_NOT 28 28 mmDSI0_DISP_DSI_PERF_CTRL 0 0x2806 2 0 2 PERF_LP_HS_LATENCY_SEL 0 1 PERF_HS_LP_LATENCY_SEL 4 5 mmDSI0_DISP_DSI_HSYNC_LENGTH 0 0x2807 2 0 2 HSYNC_LENGTH_MAX 0 15 HSYNC_LENGTH_MIN 16 31 mmDSI0_DISP_DSI_RDBK_NUM 0 0x2808 2 0 2 RD_NUM 0 15 ALL_NUM 16 31 mmDSI0_DISP_DSI_CMD_MEM_PWR_CTRL 0 0x2809 4 0 2 CMD_MEM_PWR_DIS 0 0 CMD_MEM_PWR_FORCE 4 5 CMD_MEM_PWR_STATE 8 9 CMD_MEM_PWR_MODE_SEL 12 13 mmDSI1_DISP_DSI_CTRL 0 0x28be 22 0 2 DSI_EN 0 0 VIDEO_MODE_EN 1 1 CMD_MODE_EN 2 2 DLN0_EN 4 4 DLN1_EN 5 5 DLN2_EN 6 6 DLN3_EN 7 7 CLKLN_EN 8 8 DLN0_PHY_EN 12 12 DLN1_PHY_EN 13 13 DLN2_PHY_EN 14 14 DLN3_PHY_EN 15 15 RESET_DISPCLK 16 16 RESET_DSICLK 17 17 RESET_BYTECLK 18 18 RESET_ESCCLK 19 19 CRTC_SEL 20 22 ECC_CHK_EN 24 24 CRC_CHK_EN 25 25 PACKET_BYTE_MSB_LSB_FLIP 28 28 PRE_TRIGGER_EN 29 29 NEW_INTERLEAVE_MODE_EN 30 30 mmDSI1_DISP_DSI_STATUS 0 0x28bf 41 0 2 CMD_MODE_ENGINE_BUSY 0 0 CMD_MODE_DMA_BUSY 1 1 CMD_MODE_DENG_BUSY 2 2 VIDEO_MODE_ENGINE_BUSY 3 3 BTA_BUSY 4 4 GENERIC_TRIGGER_BUSY 5 5 PHY_RESET_BUSY 6 6 DLN0_HS_FIFO_EMPTY 8 8 DLN0_HS_FIFO_FULL 9 9 DLN1_HS_FIFO_EMPTY 10 10 DLN1_HS_FIFO_FULL 11 11 DLN2_HS_FIFO_EMPTY 12 12 DLN2_HS_FIFO_FULL 13 13 DLN3_HS_FIFO_EMPTY 14 14 DLN3_HS_FIFO_FULL 15 15 DLN0_HS_FIFO_OVERFLOW 16 16 DLN0_HS_FIFO_OVERFLOW_CLR 16 16 DLN1_HS_FIFO_OVERFLOW 17 17 DLN1_HS_FIFO_OVERFLOW_CLR 17 17 DLN2_HS_FIFO_OVERFLOW 18 18 DLN2_HS_FIFO_OVERFLOW_CLR 18 18 DLN3_HS_FIFO_OVERFLOW 19 19 DLN3_HS_FIFO_OVERFLOW_CLR 19 19 DLN0_LP_FIFO_EMPTY 20 20 DLN0_LP_FIFO_FULL 21 21 DLN0_LP_FIFO_OVERFLOW 22 22 DLN0_LP_FIFO_OVERFLOW_CLR 22 22 CMDFIFO_UNDERFLOW 23 23 CMDFIFO_UNDERFLOW_CLR 23 23 INTERLEAVE_PACKET_BLOCK 24 24 INTERLEAVE_PACKET_BLOCK_CLR 24 24 TE_ABORT 25 25 TE_ABORT_CLR 25 25 DMAFIFO_RD_WATERMARK_REACH 28 28 DMAFIFO_RD_WATERMARK_REACH_CLR 28 28 DMAFIFO_WR_WATERMARK_REACH 29 29 DMAFIFO_WR_WATERMARK_REACH_CLR 29 29 DMAFIFO_UNDERFLOW 30 30 DMAFIFO_UNDERFLOW_CLR 30 30 INTERLEAVE_OP_CONTENTION 31 31 INTERLEAVE_OP_CONTENTION_CLR 31 31 mmDSI1_DISP_DSI_VIDEO_MODE_CTRL 0 0x28c0 9 0 2 VC 0 1 DST_FORMAT 4 5 TRAFFIC_MODE 8 9 BLLP_PWR_MODE 12 12 EOF_BLLP_PWR_MODE 15 15 HSA_PWR_MODE 16 16 HBP_PWR_MODE 20 20 HFP_PWR_MODE 24 24 PULSE_MODE_OPT 28 28 mmDSI1_DISP_DSI_VIDEO_MODE_SYNC_DATATYPE 0 0x28c1 4 0 2 VS 0 5 VE 8 13 HS 16 21 HE 24 29 mmDSI1_DISP_DSI_VIDEO_MODE_VSYNC_PAYLOAD 0 0x28c2 2 0 2 VS_PAYLOAD 0 15 VE_PAYLOAD 16 31 mmDSI1_DISP_DSI_VIDEO_MODE_HSYNC_PAYLOAD 0 0x28c3 2 0 2 HS_PAYLOAD 0 15 HE_PAYLOAD 16 31 mmDSI1_DISP_DSI_VIDEO_MODE_PIXEL_DATATYPE 0 0x28c4 4 0 2 RGB565 0 5 RGB666_PACKED 8 13 RGB666 16 21 RGB888 24 29 mmDSI1_DISP_DSI_VIDEO_MODE_BLANKING_DATATYPE 0 0x28c5 2 0 2 BLANK_PKT_DATA 0 7 BLANK_PKT_DATATYPE 8 13 mmDSI1_DISP_DSI_VIDEO_MODE_DATA_CTRL 0 0x28c6 4 0 2 R_SEL 0 0 G_SEL 4 4 B_SEL 8 8 RGB_SWAP 12 14 mmDSI1_DISP_DSI_COMMAND_MODE_CTRL 0 0x28c7 7 0 2 WC 0 15 DT 16 21 VC 22 23 PACKET_TYPE 24 24 POWER_MODE 26 26 EMBEDDED_MODE 28 28 CMD_DATA_ORDER 31 31 mmDSI1_DISP_DSI_COMMAND_MODE_DATA_CTRL 0 0x28c8 9 0 2 SRC_FORMAT 0 3 DST_FORMAT 4 7 DATA_BUFFER_ID 8 8 SHADOW_DATA_BUFFER_ID 12 12 R_SEL 16 16 G_SEL 17 17 B_SEL 18 18 RGB_SWAP 20 22 DWORD_BYTE_SWAP 24 25 mmDSI1_DISP_DSI_COMMAND_MODE_DCS_CMD_CTRL 0 0x28c9 3 0 2 WR_MEM_START 0 7 WR_MEM_CONTINUE 8 15 INSERT_DCS_COMMAND 16 16 mmDSI1_DISP_DSI_DMA_CMD_OFFSET 0 0x28ca 1 0 2 CMD_OFFSET 0 31 mmDSI1_DISP_DSI_DMA_CMD_LENGTH 0 0x28cb 1 0 2 CMD_LENGTH 0 23 mmDSI1_DISP_DSI_DMA_DATA_OFFSET_0 0 0x28cc 1 0 2 DATA_SRC_OFFSET0 0 31 mmDSI1_DISP_DSI_DMA_DATA_OFFSET_1 0 0x28cd 1 0 2 DATA_SRC_OFFSET1 0 31 mmDSI1_DISP_DSI_DMA_DATA_PITCH 0 0x28ce 1 0 2 DATA_SRC_PITCH 0 14 mmDSI1_DISP_DSI_DMA_DATA_WIDTH 0 0x28cf 2 0 2 DATA_SRC_WIDTH 0 19 DATA_SRC_WIDTH_ALIGN 24 26 mmDSI1_DISP_DSI_DMA_DATA_HEIGHT 0 0x28d0 1 0 2 DATA_SRC_HEIGHT 0 11 mmDSI1_DISP_DSI_DMA_FIFO_CTRL 0 0x28d1 2 0 2 WRITE_WATERMARK 0 1 READ_WATERMARK 4 5 mmDSI1_DISP_DSI_DMA_NULL_PACKET_DATA 0 0x28d2 2 0 2 NULL_DATA 0 7 NULL_DATATYPE 8 13 mmDSI1_DISP_DSI_DENG_DATA_LENGTH 0 0x28d3 2 0 2 DENG_LENGTH 0 23 USE_DENG_LENGTH 31 31 mmDSI1_DISP_DSI_ACK_ERROR_REPORT 0 0x28d4 42 0 2 SOT_ERR 0 0 SOT_ERR_CLR 0 0 SOT_SYNC_ERR 1 1 SOT_SYNC_ERR_CLR 1 1 EOT_ERR 2 2 EOT_ERR_CLR 2 2 ESC_ERR 3 3 ESC_ERR_CLR 3 3 LP_ERR 4 4 LP_ERR_CLR 4 4 HRX_TO 5 5 HRX_TO_CLR 5 5 FALSE_CTRL_ERR 6 6 FALSE_CTRL_ERR_CLR 6 6 CONTENTION_ERR 7 7 CONTENTION_ERR_CLR 7 7 ECC_ERR 8 8 ECC_ERR_CLR 8 8 MULTI_ECC_ERR 9 9 MULTI_ECC_ERR_CLR 9 9 CRC_ERR 10 10 CRC_ERR_CLR 10 10 DT_ERR 11 11 DT_ERR_CLR 11 11 VC_ERR 12 12 VC_ERR_CLR 12 12 PROTOCOL_VIOLATION 13 13 PROTOCOL_VIOLATION_CLR 13 13 PANEL_SPECIFIC_ERR 15 15 PANEL_SPECIFIC_ERR_CLR 15 15 RDBK_DATA_ECC_ERR 16 16 RDBK_DATA_ECC_ERR_CLR 16 16 RDBK_DATA_MULTI_ECC_ERR 17 17 RDBK_DATA_MULTI_ECC_ERR_CLR 17 17 RDBK_DATA_CRC_ERR 20 20 RDBK_DATA_CRC_ERR_CLR 20 20 RDBK_INCOMPLETE_PACKET_ERR 23 23 RDBK_INCOMPLETE_PACKET_ERR_CLR 23 23 ERROR 24 24 ERROR_CLR 24 24 ACK 28 28 ACK_CLR 28 28 mmDSI1_DISP_DSI_RDBK_DATA0 0 0x28d5 1 0 2 RD_DATA0 0 31 mmDSI1_DISP_DSI_RDBK_DATA1 0 0x28d6 1 0 2 RD_DATA1 0 31 mmDSI1_DISP_DSI_RDBK_DATA2 0 0x28d7 1 0 2 RD_DATA2 0 31 mmDSI1_DISP_DSI_RDBK_DATA3 0 0x28d8 1 0 2 RD_DATA3 0 31 mmDSI1_DISP_DSI_RDBK_DATATYPE0 0 0x28d9 4 0 2 GENERIC_SHORT_RD_1_BYTE 0 5 GENERIC_SHORT_RD_2_BYTE 8 13 DCS_SHORT_RD_1_BYTE 16 21 DCS_SHORT_RD_2_BYTE 24 29 mmDSI1_DISP_DSI_RDBK_DATATYPE1 0 0x28da 3 0 2 ERROR_REPORT 0 5 GENERIC_LONG_RD 8 13 DCS_LONG_RD 16 21 mmDSI1_DISP_DSI_TRIG_CTRL 0 0x28db 7 0 2 COMMAND_MODE_DMA_TRIGGER_MODE 0 0 COMMAND_MODE_DMA_TRIGGER_SEL 4 5 COMMAND_MODE_DENG_TRIGGER_MODE 16 16 COMMAND_MODE_DENG_TRIGGER_SEL 20 21 HW_SOURCE_SEL 24 27 COMMAND_MODE_DMA_DENG_ORDER 28 28 TE_SEL 31 31 mmDSI1_DISP_DSI_EXT_MUX 0 0x28dc 6 0 2 EXT_TE_MUX 0 3 EXT_TE_MODE 4 5 EXT_RESET_POL 6 6 EXT_TE_POL 7 7 EXT_TE_HSYNC_TRIG_CNT 8 19 EXT_TE_HSYNC_TOTAL 20 31 mmDSI1_DISP_DSI_EXT_TE_PULSE_DETECTION_CTRL 0 0x28dd 2 0 2 TE_HSYNC_MAX_WIDTH 0 15 TE_VSYNC_MIN_WIDTH 16 31 mmDSI1_DISP_DSI_CMD_MODE_DMA_SW_TRIGGER 0 0x28de 1 0 2 SW_TRIGGER 0 0 mmDSI1_DISP_DSI_CMD_MODE_DENG_SW_TRIGGER 0 0x28df 1 0 2 SW_TRIGGER 0 0 mmDSI1_DISP_DSI_CMD_MODE_BTA_SW_TRIGGER 0 0x28e0 1 0 2 SW_TRIGGER 0 0 mmDSI1_DISP_DSI_RESET_SW_TRIGGER 0 0x28e1 1 0 2 SW_TRIGGER 0 0 mmDSI1_DISP_DSI_EXT_RESET 0 0x28e2 1 0 2 RESET_PANEL 0 0 mmDSI1_DISP_DSI_LANE_CRC_HS_MODE 0 0x28e3 4 0 2 DLN0_HS_CRC 0 7 DLN1_HS_CRC 8 15 DLN2_HS_CRC 16 23 DLN3_HS_CRC 24 31 mmDSI1_DISP_DSI_LANE_CRC_LP_MODE 0 0x28e4 1 0 2 DLN0_LP_CRC 0 7 mmDSI1_DISP_DSI_LANE_CRC_CTRL 0 0x28e5 5 0 2 CRC_MAX_HS_DONE_COUNT 0 7 CRC_MAX_LP_DONE_COUNT 8 15 CRC_ENABLE 16 16 CRC_DONE_HS 20 20 CRC_DONE_LP 24 24 mmDSI1_DISP_DSI_PIXEL_CRC_CTRL 0 0x28e6 3 0 2 CRC_MAX_PIXEL_COUNT 0 7 PIXEL_CRC 8 15 CRC_DONE_PIXEL 16 16 mmDSI1_DISP_DSI_LANE_CTRL 0 0x28e7 16 0 2 DLN0_ULPS_REQUEST 0 0 DLN1_ULPS_REQUEST 1 1 DLN2_ULPS_REQUEST 2 2 DLN3_ULPS_REQUEST 3 3 DLN0_ULPS_EXIT 4 4 DLN1_ULPS_EXIT 5 5 DLN2_ULPS_EXIT 6 6 DLN3_ULPS_EXIT 7 7 DLN0_FORCE_TX_STOP 8 8 DLN1_FORCE_TX_STOP 9 9 DLN2_FORCE_TX_STOP 10 10 DLN3_FORCE_TX_STOP 11 11 CLKLN_ULPS_REQUEST 12 12 CLKLN_ULPS_EXIT 16 16 CLKLN_FORCE_TX_STOP 20 20 CLKLN_HS_FORCE_REQUEST 24 24 mmDSI1_DISP_DSI_DLN0_PHY_ERROR 0 0x28e8 15 0 2 DLN0_ERR_ESC 0 0 DLN0_ERR_ESC_CLR 0 0 DLN0_ERR_ESC_MASK 3 3 DLN0_ERR_SYNC_ESC 4 4 DLN0_ERR_SYNC_ESC_CLR 4 4 DLN0_ERR_SYNC_ESC_MASK 7 7 DLN0_ERR_CONTROL 8 8 DLN0_ERR_CONTROL_CLR 8 8 DLN0_ERR_CONTROL_MASK 11 11 DLN0_ERR_CONTENTION_LP0 12 12 DLN0_ERR_CONTENTION_LP0_CLR 12 12 DLN0_ERR_CONTENTION_LP0_MASK 15 15 DLN0_ERR_CONTENTION_LP1 16 16 DLN0_ERR_CONTENTION_LP1_CLR 16 16 DLN0_ERR_CONTENTION_LP1_MASK 19 19 mmDSI1_DISP_DSI_LP_TIMER_CTRL 0 0x28e9 2 0 2 LP_RX_TO 0 15 BTA_TO 16 31 mmDSI1_DISP_DSI_HS_TIMER_CTRL 0 0x28ea 1 0 2 HS_TX_TO 0 15 mmDSI1_DISP_DSI_TIMEOUT_STATUS 0 0x28eb 6 0 2 HS_TX_TIMEOUT 0 0 HS_TX_TIMEOUT_CLR 0 0 LP_RX_TIMEOUT 4 4 LP_RX_TIMEOUT_CLR 4 4 BTA_TIMEOUT 8 8 BTA_TIMEOUT_CLR 8 8 mmDSI1_DISP_DSI_PHY_CLK_TIMING_CTRL 0 0x28ec 2 0 2 T_CLK_PRE 0 7 T_CLK_POST 8 13 mmDSI1_DISP_DSI_PHY_CLK_TIMING_CTRL2 0 0x28ed 2 0 2 T_PRE_TRIGGER 0 10 T_INTER_STOP 16 31 mmDSI1_DISP_DSI_EOT_PACKET 0 0x28ee 3 0 2 DI 0 7 WC 8 23 ECC 24 31 mmDSI1_DISP_DSI_EOT_PACKET_CTRL 0 0x28ef 2 0 2 TX_EOT_APPEND 0 0 RX_EOT_IGNORE 4 4 mmDSI1_DISP_DSI_GENERIC_ESC_TX_TRIGGER 0 0x28f0 2 0 2 SW_TRIGGER 0 0 ENTRY_COMMAND 16 23 mmDSI1_DISP_DSI_MIPI_BIST_CTRL 0 0x28f1 2 0 2 MIPI_BIST_RESET 0 0 MIPI_BIST_EN 1 1 mmDSI1_DISP_DSI_MIPI_BIST_FRAME_SIZE 0 0x28f2 2 0 2 MIPI_H_SIZE 0 15 MIPI_V_SIZE 16 31 mmDSI1_DISP_DSI_MIPI_BIST_BLOCK_SIZE 0 0x28f3 2 0 2 MIPI_H_SIZE 0 7 MIPI_V_SIZE 8 15 mmDSI1_DISP_DSI_MIPI_BIST_FRAME_CONFIG 0 0x28f4 3 0 2 MIPI_BLANKING_CYCLES 0 15 MIPI_FRAME_REPEAT 16 23 MIPI_BIST_VIDEO_FRMT 24 24 mmDSI1_DISP_DSI_MIPI_BIST_LSFR_CTRL 0 0x28f5 6 0 2 MIPI_Y_LSFR_POLYNOMIAL 0 7 MIPI_U_LSFR_POLYNOMIAL 8 15 MIPI_V_LSFR_POLYNOMIAL 16 23 MIPI_Y_LSFR_EN 24 24 MIPI_U_LSFR_EN 25 25 MIPI_V_LSFR_EN 26 26 mmDSI1_DISP_DSI_MIPI_BIST_LSFR_INIT 0 0x28f6 3 0 2 MIPI_Y_INIT_LSFR_VAL 0 7 MIPI_U_INIT_LSFR_VAL 8 15 MIPI_V_INIT_LSFR_VAL 16 23 mmDSI1_DISP_DSI_MIPI_BIST_START 0 0x28f7 1 0 2 MIPI_BIST_START 0 0 mmDSI1_DISP_DSI_MIPI_BIST_STATUS 0 0x28f8 3 0 2 MIPI_BIST_STATUS_BUSY 0 0 MIPI_BIST_DONE 4 4 MIPI_BIST_DONE_CLR 4 4 mmDSI1_DISP_DSI_ERROR_INTERRUPT_MASK 0 0x28f9 24 0 2 RDBK_DATA_ECC_ERR_MASK 0 0 RDBK_DATA_MULTI_ECC_ERR_MASK 1 1 RDBK_DATA_CRC_ERR_MASK 2 2 RDBK_INCOMPLETE_PACKET_ERR_MASK 3 3 ERROR_PACKET_MASK 4 4 INTERLEAVE_PACKET_BLOCK_MASK 5 5 TE_ABORT_MASK 6 6 DLN0_ERR_ESC_MASK 8 8 DLN0_ERR_SYNC_ESC_MASK 9 9 DLN0_ERR_CONTROL_MASK 10 10 DLN0_ERR_CONTENTION_LP0_MASK 12 12 DLN0_ERR_CONTENTION_LP1_MASK 13 13 LP_RX_TO_MASK 16 16 HS_TX_TO_MASK 17 17 BTA_TO_MASK 18 18 DMAFIFO_UNDERFLOW_MASK 20 20 CMDFIFO_UNDERFLOW_MASK 21 21 DENGFIFO_OVERFLOW_UNDERFLOW_MASK 24 24 DLN0_HS_FIFO_OVERFLOW_MASK 26 26 DLN1_HS_FIFO_OVERFLOW_MASK 27 27 DLN2_HS_FIFO_OVERFLOW_MASK 28 28 DLN3_HS_FIFO_OVERFLOW_MASK 29 29 DLN0_LP_FIFO_OVERFLOW_MASK 30 30 INTERLEAVE_OP_CONTENTION_MASK 31 31 mmDSI1_DISP_DSI_INTERRUPT_CTRL 0 0x28fa 21 0 2 DSI_CMD_MODE_DMA_DONE_STAT 0 0 DSI_CMD_MODE_DMA_DONE_AK 0 0 DSI_CMD_MODE_DMA_DONE_MASK 1 1 DSI_CMD_MODE_DENG_DONE_STAT 4 4 DSI_CMD_MODE_DENG_DONE_AK 4 4 DSI_CMD_MODE_DENG_DONE_MASK 5 5 DSI_VIDEO_MODE_DONE_STAT 8 8 DSI_VIDEO_MODE_DONE_AK 8 8 DSI_VIDEO_MODE_DONE_MASK 9 9 DSI_ERROR_STAT 12 12 DSI_ERROR_AK 12 12 DSI_ERROR_MASK 13 13 DSI_SW_BTA_DONE_STAT 16 16 DSI_SW_BTA_DONE_AK 16 16 DSI_SW_BTA_DONE_MASK 17 17 DSI_CMDFIFO_DONE_STAT 20 20 DSI_CMDFIFO_DONE_AK 20 20 DSI_CMDFIFO_DONE_MASK 21 21 DSI_CAL_DONE_STAT 24 24 DSI_CAL_DONE_AK 24 24 DSI_CAL_DONE_MASK 25 25 mmDSI1_DISP_DSI_CLK_CTRL 0 0x28fb 8 0 2 DISPCLK_G_ON 0 0 DISPCLK_R_ON 1 1 DSICLK_G_ON 4 4 DSICLK_R_ON 5 5 DSICLK_TRN_ON 6 6 BYTECLK_G_ON 8 8 ESCCLK_G_ON 16 16 TEST_CLK_SEL 24 27 mmDSI1_DISP_DSI_CLK_STATUS 0 0x28fc 7 0 2 DISPCLK_R_ACTIVE 0 0 DISPCLK_G_ACTIVE 1 1 DSICLK_R_ACTIVE 4 4 DSICLK_G_ACTIVE 5 5 DSICLK_TRN_ACTIVE 6 6 BYTECLK_G_ACTIVE 8 8 ESCCLK_G_ACTIVE 16 16 mmDSI1_DISP_DSI_DENG_FIFO_STATUS 0 0x28fd 10 0 2 DENG_FIFO_LEVEL_ERROR 0 0 DENG_FIFO_USE_OVERWRITE_LEVEL 1 1 DENG_FIFO_OVERWRITE_LEVEL 2 8 DENG_FIFO_ERROR_ACK 9 9 DENG_FIFO_CAL_AVERAGE_LEVEL 10 16 DENG_FIFO_MAXIMUM_LEVEL 17 22 DENG_FIFO_MINIMUM_LEVEL 23 27 DENG_FIFO_CALIBRATED 29 29 DENG_FIFO_FORCE_RECAL_AVERAGE 30 30 DENG_FIFO_FORCE_RECOMP_MINMAX 31 31 mmDSI1_DISP_DSI_DENG_FIFO_CTRL 0 0x28fe 3 0 2 DENG_FIFO_EN 0 0 DENG_FIFO_START 4 4 DENG_DSICLK_ON 8 8 mmDSI1_DISP_DSI_CMD_FIFO_DATA 0 0x28ff 1 0 2 CMDFIFO_DATA 0 31 mmDSI1_DISP_DSI_CMD_FIFO_CTRL 0 0x2900 2 0 2 USE_CMDFIFO 0 0 CMDFIFO_DW_LEVEL 4 10 mmDSI1_DISP_DSI_TE_CTRL 0 0x2901 5 0 2 FREEZE_CRTC_HYSTERESIS 0 11 DISABLE_CRTC_FREEZE 16 16 DISABLE_CRTC_FORCE 20 20 CRTC_FREEZE 24 24 CRTC_FREEZE_TRIG 24 24 mmDSI1_DISP_DSI_LANE_STATUS 0 0x2905 11 0 2 DLN0_STOPSTATE 0 0 DLN1_STOPSTATE 1 1 DLN2_STOPSTATE 2 2 DLN3_STOPSTATE 3 3 DLN0_ULPS_ACTIVE_NOT 4 4 DLN1_ULPS_ACTIVE_NOT 5 5 DLN2_ULPS_ACTIVE_NOT 6 6 DLN3_ULPS_ACTIVE_NOT 7 7 DLN0_DIRECTION 8 8 CLKLN_STOPSTATE 24 24 CLKLN_ULPS_ACTIVE_NOT 28 28 mmDSI1_DISP_DSI_PERF_CTRL 0 0x2906 2 0 2 PERF_LP_HS_LATENCY_SEL 0 1 PERF_HS_LP_LATENCY_SEL 4 5 mmDSI1_DISP_DSI_HSYNC_LENGTH 0 0x2907 2 0 2 HSYNC_LENGTH_MAX 0 15 HSYNC_LENGTH_MIN 16 31 mmDSI1_DISP_DSI_RDBK_NUM 0 0x2908 2 0 2 RD_NUM 0 15 ALL_NUM 16 31 mmDSI1_DISP_DSI_CMD_MEM_PWR_CTRL 0 0x2909 4 0 2 CMD_MEM_PWR_DIS 0 0 CMD_MEM_PWR_FORCE 4 5 CMD_MEM_PWR_STATE 8 9 CMD_MEM_PWR_MODE_SEL 12 13 mmDPRX_SD0_DPRX_SD_CONTROL 0 0x29be 4 0 2 SD_ENABLE 0 0 SD_RESET 4 4 SD_CLOCK_ENABLE 8 8 SD_CLOCK_ON 12 12 mmDPRX_SD0_DPRX_SD_STREAM_ENABLE 0 0x29bf 2 0 2 VID_STREAM_ENABLE 0 0 VID_STREAM_STATUS 8 8 mmDPRX_SD0_DPRX_SD_MSA0 0 0x29c0 1 0 2 MSA0 0 31 mmDPRX_SD0_DPRX_SD_MSA1 0 0x29c1 1 0 2 MSA1 0 31 mmDPRX_SD0_DPRX_SD_MSA2 0 0x29c2 1 0 2 MSA2 0 31 mmDPRX_SD0_DPRX_SD_MSA3 0 0x29c3 1 0 2 MSA3 0 31 mmDPRX_SD0_DPRX_SD_MSA4 0 0x29c4 1 0 2 MSA4 0 31 mmDPRX_SD0_DPRX_SD_MSA5 0 0x29c5 1 0 2 MSA5 0 31 mmDPRX_SD0_DPRX_SD_MSA6 0 0x29c6 1 0 2 MSA6 0 31 mmDPRX_SD0_DPRX_SD_MSA7 0 0x29c7 1 0 2 MSA7 0 31 mmDPRX_SD0_DPRX_SD_MSA8 0 0x29c8 1 0 2 MSA8 0 31 mmDPRX_SD0_DPRX_SD_VBID 0 0x29c9 1 0 2 VBID 0 7 mmDPRX_SD0_DPRX_SD_CURRENT_LINE 0 0x29ca 2 0 2 CURRENT_LINE 0 15 CURRENT_FRAME 16 23 mmDPRX_SD0_DPRX_SD_DISPLAY_TIMER_SNAPSHOT 0 0x29cb 1 0 2 DISPLAY_TIMER_SNAPSHOT 0 31 mmDPRX_SD0_DPRX_SD_DISPLAY_TIMER_MODE 0 0x29cc 2 0 2 DISPLAY_TIMER_MODE 0 0 DISPLAY_TIMER_UPDATE_LOCKED 8 8 mmDPRX_SD0_DPRX_SD_MSE_SAT 0 0x29ce 2 0 2 MSE_SAT_SLOT_START 0 5 MSE_SAT_SLOT_END 8 13 mmDPRX_SD0_DPRX_SD_MSE_FORCE_UPDATE 0 0x29cf 1 0 2 MSE_SAT_FORCE_UPDATE 0 0 mmDPRX_SD0_DPRX_SD_MSE_SAT_ACTIVE 0 0x29d0 2 0 2 MSE_SAT_SLOT_START_ACTIVE 0 5 MSE_SAT_SLOT_END_ACTIVE 8 13 mmDPRX_SD0_DPRX_SD_V_PARAMETER 0 0x29d1 1 0 2 V_BLANK_HEIGHT 0 15 mmDPRX_SD0_DPRX_SD_PIXEL_FORMAT 0 0x29d2 2 0 2 PIXEL_ENCODING 0 1 COMPONENT_DEPTH 8 10 mmDPRX_SD0_DPRX_SD_MSA_RECEIVED_STATUS 0 0x29d3 3 0 2 MSA_RECEIVED_FLAG 0 0 MSA_RECEIVED_ACK 4 4 MSA_RECEIVED_MASK 8 8 mmDPRX_SD0_DPRX_SD_VIDEO_STREAM_STATUS_TOGGLED 0 0x29d4 3 0 2 VBID_VID_STREAM_STATUS_TOGGLED_FLAG 0 0 VBID_VID_STREAM_STATUS_TOGGLED_ACK 4 4 VBID_VID_STREAM_STATUS_TOGGLED_MASK 8 8 mmDPRX_SD0_DPRX_SD_LINE_NUMBER0_STATUS 0 0x29d5 4 0 2 LINE_NUMBER0_FLAG 0 0 LINE_NUMBER0_ACK 4 4 LINE_NUMBER0_MASK 8 8 LINE_NUMBER0_TYPE 12 12 mmDPRX_SD0_DPRX_SD_LINE_NUMBER0_CONTROL 0 0x29d6 1 0 2 LINE_NUMBER0_INTERRUPT 0 15 mmDPRX_SD0_DPRX_SD_LINE_NUMBER1_STATUS 0 0x29d7 4 0 2 LINE_NUMBER1_FLAG 0 0 LINE_NUMBER1_ACK 4 4 LINE_NUMBER1_MASK 8 8 LINE_NUMBER1_TYPE 12 12 mmDPRX_SD0_DPRX_SD_LINE_NUMBER1_CONTROL 0 0x29d8 1 0 2 LINE_NUMBER1_INTERRUPT 0 15 mmDPRX_SD0_DPRX_SD_MAIN_DEFRAMING_ERROR 0 0x29d9 15 0 2 BS1_ERROR 0 0 VBID_ERROR 1 1 MVID_ERROR 2 2 MAUD_ERROR 3 3 IDLE_ERROR 4 4 BE_BS_ERROR 5 5 BE_OTHER_ERROR 6 6 PIX_ERROR 7 7 FS_BS_ERROR 8 8 FS_OTHER_ERROR 9 9 FILL_BS_ERROR 10 10 FILL_OTHER_ERROR 11 11 FE_BS_ERROR 12 12 FE_OTHER_ERROR 13 13 FILTER_BE_ERROR 14 14 mmDPRX_SD0_DPRX_SD_VBID_MAJORITY_VOTE 0 0x29da 3 0 2 VBID_MAJORITY_VOTE_1_ERROR 0 0 VBID_MAJORITY_VOTE_2_ERROR 1 1 VBID_MAJORITY_VOTE_FAIL 2 2 mmDPRX_SD0_DPRX_SD_SECONDARY_DEFRAMING_ERROR 0 0x29db 12 0 2 SEC_SDP_MSA_SS0_ERROR 0 0 SEC_MSA_SS1_ERROR 1 1 SEC_MSA_DATA_ERROR 2 2 SEC_SDP_DATA_EXPIRE_ERROR 4 4 SEC_SDP_DATA_SE_ILLEGAL_SE_ERROR 5 5 SEC_SDP_DATA_ERROR 6 6 SEC_NESTED_MSA_SS1_ERROR 8 8 SEC_NESTED_MSA_SS2_ERROR 9 9 SEC_NESTED_MSA_DATA_ERROR 10 10 SEC_NESTED_MSA_SE_EXPIRE_ERROR 11 11 SEC_NESTED_MSA_SE_ILLEGAL_SE_ERROR 12 12 SEC_NESTED_MSA_SE_ERROR 13 13 mmDPRX_SD0_DPRX_SD_VCPF_PHASE_LOCKED 0 0x29dc 1 0 2 VCPF_PHASE_LOCKED 0 0 mmDPRX_SD0_DPRX_SD_VCPF_PHASE_ERROR 0 0x29dd 3 0 2 VCPF_PHASE_ERROR 0 0 VCPF_1_SYMBOL_ERROR 1 1 VCPF_2_SYMBOL_ERROR 2 2 mmDPRX_SD0_DPRX_SD_MAJORITY_VOTE_ERROR 0 0x29de 2 0 2 CORRECTED_CONTROL_SEQUENCE_ERROR 0 0 CORRECTED_DATA_SEQUENCE_ERROR 8 8 mmDPRX_SD0_DPRX_SD_PIXEL_FIFO_ERROR 0 0x29df 1 0 2 PIXEL_FIFO_OVERFLOW_ERROR 0 0 mmDPRX_SD0_DPRX_SD_MAXIMUM_SDP_PAYLOAD_LENGTH 0 0x29e1 1 0 2 MAXIMUM_SDP_PAYLOAD_LENGTH 0 9 mmDPRX_SD0_DPRX_SD_SDP_STEER 0 0x29e3 1 0 2 FILTER_AUDIO_TIMESTAMP_SDP_EN 0 0 mmDPRX_SD0_DPRX_SD_SDP_RECEIVED_STATUS 0 0x29e4 3 0 2 SDP_RECEIVED_FLAG 0 0 SDP_RECEIVED_ACK 4 4 SDP_RECEIVED_MASK 8 8 mmDPRX_SD0_DPRX_SD_SDP_LEVEL 0 0x29e5 2 0 2 SDP_FIFO_LEVEL 0 4 SDP_CURRENT_SLICE 8 11 mmDPRX_SD0_DPRX_SD_SDP_DATA 0 0x29e6 1 0 2 SDP_DATA 0 31 mmDPRX_SD0_DPRX_SD_SDP_ERROR 0 0x29e7 7 0 2 SDP_FIFO_OVERFLOW_ERROR 0 0 SDP_HEADER_ERROR 1 1 SDP_NON_AUDIO_PAYLOAD_ERROR 2 2 SDP_NON_AUDIO_LENGTH_ERROR 3 3 SDP_RS_CORRECTED_ERROR 4 4 SDP_RS_UNCORRECTABLE_ERROR 5 5 SDP_AUDIO_PAYLOAD_ERROR 6 6 mmDPRX_SD0_DPRX_SD_AUDIO_HEADER 0 0x29e8 1 0 2 AUDIO_HEADER 0 31 mmDPRX_SD0_DPRX_SD_AUDIO_FIFO_ERROR 0 0x29e9 1 0 2 AUDIO_FIFO_OVERFLOW_ERROR 0 0 mmDPRX_SD0_DPRX_SD_SDP_CONTROL 0 0x29ea 2 0 2 RS_DECODER_ENABLE 0 0 RS_ERROR_CORRECTION_ENABLE 4 4 mmDPRX_SD0_DPRX_SD_V_TOTAL_MEASURED 0 0x29eb 2 0 2 V_ACTIVE_LINE_TOTAL 0 15 V_LINE_TOTAL 16 31 mmDPRX_SD0_DPRX_SD_H_TOTAL_MEASURED 0 0x29ec 1 0 2 H_ACTIVE_SYMBOL_TOTAL 0 15 mmDPRX_SD0_DPRX_SD_BS_COUNTER 0 0x29ed 1 0 2 BS_COUNTER 0 9 mmDPRX_SD0_DPRX_SD_MSE_ACT_HANDLED 0 0x29ee 1 0 2 MSE_ACT_HANDLED 0 0 mmDPRX_SD1_DPRX_SD_CONTROL 0 0x2a1e 4 0 2 SD_ENABLE 0 0 SD_RESET 4 4 SD_CLOCK_ENABLE 8 8 SD_CLOCK_ON 12 12 mmDPRX_SD1_DPRX_SD_STREAM_ENABLE 0 0x2a1f 2 0 2 VID_STREAM_ENABLE 0 0 VID_STREAM_STATUS 8 8 mmDPRX_SD1_DPRX_SD_MSA0 0 0x2a20 1 0 2 MSA0 0 31 mmDPRX_SD1_DPRX_SD_MSA1 0 0x2a21 1 0 2 MSA1 0 31 mmDPRX_SD1_DPRX_SD_MSA2 0 0x2a22 1 0 2 MSA2 0 31 mmDPRX_SD1_DPRX_SD_MSA3 0 0x2a23 1 0 2 MSA3 0 31 mmDPRX_SD1_DPRX_SD_MSA4 0 0x2a24 1 0 2 MSA4 0 31 mmDPRX_SD1_DPRX_SD_MSA5 0 0x2a25 1 0 2 MSA5 0 31 mmDPRX_SD1_DPRX_SD_MSA6 0 0x2a26 1 0 2 MSA6 0 31 mmDPRX_SD1_DPRX_SD_MSA7 0 0x2a27 1 0 2 MSA7 0 31 mmDPRX_SD1_DPRX_SD_MSA8 0 0x2a28 1 0 2 MSA8 0 31 mmDPRX_SD1_DPRX_SD_VBID 0 0x2a29 1 0 2 VBID 0 7 mmDPRX_SD1_DPRX_SD_CURRENT_LINE 0 0x2a2a 2 0 2 CURRENT_LINE 0 15 CURRENT_FRAME 16 23 mmDPRX_SD1_DPRX_SD_DISPLAY_TIMER_SNAPSHOT 0 0x2a2b 1 0 2 DISPLAY_TIMER_SNAPSHOT 0 31 mmDPRX_SD1_DPRX_SD_DISPLAY_TIMER_MODE 0 0x2a2c 2 0 2 DISPLAY_TIMER_MODE 0 0 DISPLAY_TIMER_UPDATE_LOCKED 8 8 mmDPRX_SD1_DPRX_SD_MSE_SAT 0 0x2a2e 2 0 2 MSE_SAT_SLOT_START 0 5 MSE_SAT_SLOT_END 8 13 mmDPRX_SD1_DPRX_SD_MSE_FORCE_UPDATE 0 0x2a2f 1 0 2 MSE_SAT_FORCE_UPDATE 0 0 mmDPRX_SD1_DPRX_SD_MSE_SAT_ACTIVE 0 0x2a30 2 0 2 MSE_SAT_SLOT_START_ACTIVE 0 5 MSE_SAT_SLOT_END_ACTIVE 8 13 mmDPRX_SD1_DPRX_SD_V_PARAMETER 0 0x2a31 1 0 2 V_BLANK_HEIGHT 0 15 mmDPRX_SD1_DPRX_SD_PIXEL_FORMAT 0 0x2a32 2 0 2 PIXEL_ENCODING 0 1 COMPONENT_DEPTH 8 10 mmDPRX_SD1_DPRX_SD_MSA_RECEIVED_STATUS 0 0x2a33 3 0 2 MSA_RECEIVED_FLAG 0 0 MSA_RECEIVED_ACK 4 4 MSA_RECEIVED_MASK 8 8 mmDPRX_SD1_DPRX_SD_VIDEO_STREAM_STATUS_TOGGLED 0 0x2a34 3 0 2 VBID_VID_STREAM_STATUS_TOGGLED_FLAG 0 0 VBID_VID_STREAM_STATUS_TOGGLED_ACK 4 4 VBID_VID_STREAM_STATUS_TOGGLED_MASK 8 8 mmDPRX_SD1_DPRX_SD_LINE_NUMBER0_STATUS 0 0x2a35 4 0 2 LINE_NUMBER0_FLAG 0 0 LINE_NUMBER0_ACK 4 4 LINE_NUMBER0_MASK 8 8 LINE_NUMBER0_TYPE 12 12 mmDPRX_SD1_DPRX_SD_LINE_NUMBER0_CONTROL 0 0x2a36 1 0 2 LINE_NUMBER0_INTERRUPT 0 15 mmDPRX_SD1_DPRX_SD_LINE_NUMBER1_STATUS 0 0x2a37 4 0 2 LINE_NUMBER1_FLAG 0 0 LINE_NUMBER1_ACK 4 4 LINE_NUMBER1_MASK 8 8 LINE_NUMBER1_TYPE 12 12 mmDPRX_SD1_DPRX_SD_LINE_NUMBER1_CONTROL 0 0x2a38 1 0 2 LINE_NUMBER1_INTERRUPT 0 15 mmDPRX_SD1_DPRX_SD_MAIN_DEFRAMING_ERROR 0 0x2a39 15 0 2 BS1_ERROR 0 0 VBID_ERROR 1 1 MVID_ERROR 2 2 MAUD_ERROR 3 3 IDLE_ERROR 4 4 BE_BS_ERROR 5 5 BE_OTHER_ERROR 6 6 PIX_ERROR 7 7 FS_BS_ERROR 8 8 FS_OTHER_ERROR 9 9 FILL_BS_ERROR 10 10 FILL_OTHER_ERROR 11 11 FE_BS_ERROR 12 12 FE_OTHER_ERROR 13 13 FILTER_BE_ERROR 14 14 mmDPRX_SD1_DPRX_SD_VBID_MAJORITY_VOTE 0 0x2a3a 3 0 2 VBID_MAJORITY_VOTE_1_ERROR 0 0 VBID_MAJORITY_VOTE_2_ERROR 1 1 VBID_MAJORITY_VOTE_FAIL 2 2 mmDPRX_SD1_DPRX_SD_SECONDARY_DEFRAMING_ERROR 0 0x2a3b 12 0 2 SEC_SDP_MSA_SS0_ERROR 0 0 SEC_MSA_SS1_ERROR 1 1 SEC_MSA_DATA_ERROR 2 2 SEC_SDP_DATA_EXPIRE_ERROR 4 4 SEC_SDP_DATA_SE_ILLEGAL_SE_ERROR 5 5 SEC_SDP_DATA_ERROR 6 6 SEC_NESTED_MSA_SS1_ERROR 8 8 SEC_NESTED_MSA_SS2_ERROR 9 9 SEC_NESTED_MSA_DATA_ERROR 10 10 SEC_NESTED_MSA_SE_EXPIRE_ERROR 11 11 SEC_NESTED_MSA_SE_ILLEGAL_SE_ERROR 12 12 SEC_NESTED_MSA_SE_ERROR 13 13 mmDPRX_SD1_DPRX_SD_VCPF_PHASE_LOCKED 0 0x2a3c 1 0 2 VCPF_PHASE_LOCKED 0 0 mmDPRX_SD1_DPRX_SD_VCPF_PHASE_ERROR 0 0x2a3d 3 0 2 VCPF_PHASE_ERROR 0 0 VCPF_1_SYMBOL_ERROR 1 1 VCPF_2_SYMBOL_ERROR 2 2 mmDPRX_SD1_DPRX_SD_MAJORITY_VOTE_ERROR 0 0x2a3e 2 0 2 CORRECTED_CONTROL_SEQUENCE_ERROR 0 0 CORRECTED_DATA_SEQUENCE_ERROR 8 8 mmDPRX_SD1_DPRX_SD_PIXEL_FIFO_ERROR 0 0x2a3f 1 0 2 PIXEL_FIFO_OVERFLOW_ERROR 0 0 mmDPRX_SD1_DPRX_SD_MAXIMUM_SDP_PAYLOAD_LENGTH 0 0x2a41 1 0 2 MAXIMUM_SDP_PAYLOAD_LENGTH 0 9 mmDPRX_SD1_DPRX_SD_SDP_STEER 0 0x2a43 1 0 2 FILTER_AUDIO_TIMESTAMP_SDP_EN 0 0 mmDPRX_SD1_DPRX_SD_SDP_RECEIVED_STATUS 0 0x2a44 3 0 2 SDP_RECEIVED_FLAG 0 0 SDP_RECEIVED_ACK 4 4 SDP_RECEIVED_MASK 8 8 mmDPRX_SD1_DPRX_SD_SDP_LEVEL 0 0x2a45 2 0 2 SDP_FIFO_LEVEL 0 4 SDP_CURRENT_SLICE 8 11 mmDPRX_SD1_DPRX_SD_SDP_DATA 0 0x2a46 1 0 2 SDP_DATA 0 31 mmDPRX_SD1_DPRX_SD_SDP_ERROR 0 0x2a47 7 0 2 SDP_FIFO_OVERFLOW_ERROR 0 0 SDP_HEADER_ERROR 1 1 SDP_NON_AUDIO_PAYLOAD_ERROR 2 2 SDP_NON_AUDIO_LENGTH_ERROR 3 3 SDP_RS_CORRECTED_ERROR 4 4 SDP_RS_UNCORRECTABLE_ERROR 5 5 SDP_AUDIO_PAYLOAD_ERROR 6 6 mmDPRX_SD1_DPRX_SD_AUDIO_HEADER 0 0x2a48 1 0 2 AUDIO_HEADER 0 31 mmDPRX_SD1_DPRX_SD_AUDIO_FIFO_ERROR 0 0x2a49 1 0 2 AUDIO_FIFO_OVERFLOW_ERROR 0 0 mmDPRX_SD1_DPRX_SD_SDP_CONTROL 0 0x2a4a 2 0 2 RS_DECODER_ENABLE 0 0 RS_ERROR_CORRECTION_ENABLE 4 4 mmDPRX_SD1_DPRX_SD_V_TOTAL_MEASURED 0 0x2a4b 2 0 2 V_ACTIVE_LINE_TOTAL 0 15 V_LINE_TOTAL 16 31 mmDPRX_SD1_DPRX_SD_H_TOTAL_MEASURED 0 0x2a4c 1 0 2 H_ACTIVE_SYMBOL_TOTAL 0 15 mmDPRX_SD1_DPRX_SD_BS_COUNTER 0 0x2a4d 1 0 2 BS_COUNTER 0 9 mmDPRX_SD1_DPRX_SD_MSE_ACT_HANDLED 0 0x2a4e 1 0 2 MSE_ACT_HANDLED 0 0 mmDC_PERFMON10_PERFCOUNTER_CNTL 0 0x2b5e 13 0 2 PERFCOUNTER_EVENT_SEL 0 8 PERFCOUNTER_CVALUE_SEL 9 11 PERFCOUNTER_INC_MODE 12 14 PERFCOUNTER_HW_CNTL_SEL 15 15 PERFCOUNTER_RUNEN_MODE 16 16 PERFCOUNTER_CNTOFF_SEL 17 21 PERFCOUNTER_CNTOFF_START_DIS 22 22 PERFCOUNTER_RESTART_EN 23 23 PERFCOUNTER_INT_EN 24 24 PERFCOUNTER_OFF_MASK 25 25 PERFCOUNTER_ACTIVE 26 26 PERFCOUNTER_INT_TYPE 27 27 PERFCOUNTER_CNTL_SEL 29 31 mmDC_PERFMON10_PERFCOUNTER_CNTL2 0 0x2b5f 4 0 2 PERFCOUNTER_COUNTED_VALUE_TYPE 0 1 PERFCOUNTER_HW_STOP1_SEL 2 2 PERFCOUNTER_HW_STOP2_SEL 3 3 PERFCOUNTER_CNTL2_SEL 29 31 mmDC_PERFMON10_PERFCOUNTER_STATE 0 0x2b60 16 0 2 PERFCOUNTER_CNT0_STATE 0 1 PERFCOUNTER_STATE_SEL0 2 2 PERFCOUNTER_CNT1_STATE 4 5 PERFCOUNTER_STATE_SEL1 6 6 PERFCOUNTER_CNT2_STATE 8 9 PERFCOUNTER_STATE_SEL2 10 10 PERFCOUNTER_CNT3_STATE 12 13 PERFCOUNTER_STATE_SEL3 14 14 PERFCOUNTER_CNT4_STATE 16 17 PERFCOUNTER_STATE_SEL4 18 18 PERFCOUNTER_CNT5_STATE 20 21 PERFCOUNTER_STATE_SEL5 22 22 PERFCOUNTER_CNT6_STATE 24 25 PERFCOUNTER_STATE_SEL6 26 26 PERFCOUNTER_CNT7_STATE 28 29 PERFCOUNTER_STATE_SEL7 30 30 mmDC_PERFMON10_PERFMON_CNTL 0 0x2b61 6 0 2 PERFMON_STATE 0 1 PERFMON_RPT_COUNT 8 27 PERFMON_CNTOFF_AND_OR 28 28 PERFMON_CNTOFF_INT_EN 29 29 PERFMON_CNTOFF_INT_STATUS 30 30 PERFMON_CNTOFF_INT_ACK 31 31 mmDC_PERFMON10_PERFMON_CNTL2 0 0x2b62 4 0 2 PERFMON_CNTOFF_INT_TYPE 0 0 PERFMON_CLK_ENABLE 1 1 PERFMON_RUN_ENABLE_START_SEL 2 9 PERFMON_RUN_ENABLE_STOP_SEL 10 17 mmDC_PERFMON10_PERFMON_CVALUE_INT_MISC 0 0x2b63 17 0 2 PERFCOUNTER_INT0_STATUS 0 0 PERFCOUNTER_INT1_STATUS 1 1 PERFCOUNTER_INT2_STATUS 2 2 PERFCOUNTER_INT3_STATUS 3 3 PERFCOUNTER_INT4_STATUS 4 4 PERFCOUNTER_INT5_STATUS 5 5 PERFCOUNTER_INT6_STATUS 6 6 PERFCOUNTER_INT7_STATUS 7 7 PERFCOUNTER_INT0_ACK 8 8 PERFCOUNTER_INT1_ACK 9 9 PERFCOUNTER_INT2_ACK 10 10 PERFCOUNTER_INT3_ACK 11 11 PERFCOUNTER_INT4_ACK 12 12 PERFCOUNTER_INT5_ACK 13 13 PERFCOUNTER_INT6_ACK 14 14 PERFCOUNTER_INT7_ACK 15 15 PERFMON_CVALUE_HI 16 31 mmDC_PERFMON10_PERFMON_CVALUE_LOW 0 0x2b64 1 0 2 PERFMON_CVALUE_LOW 0 31 mmDC_PERFMON10_PERFMON_HI 0 0x2b65 2 0 2 PERFMON_HI 0 15 PERFMON_READ_SEL 29 31 mmDC_PERFMON10_PERFMON_LOW 0 0x2b66 1 0 2 PERFMON_LOW 0 31 mmCOMP_EN_CTL 0 0x2d96 12 0 2 comp_en 0 0 comp_en_override 2 2 comp_done 4 4 zcal_code_override 6 6 zcal_cal_rtt 7 7 zcal_base_en 8 8 zcal_ht_rtt_sel 9 9 zcal_code 10 14 zcal_ron_cal_mode 16 16 zcal_ana_dbg_sel 17 18 cfg_cml_cmos_sel 19 19 dsm_sel 20 23 mmCOMP_EN_DFX 0 0x2d97 6 0 2 autocal_ron_code 0 4 autocal_rtt_code 5 9 pre_fused_ron_code 11 15 pre_fused_rtt_code 16 20 broadcast_ron_code 22 26 broadcast_rtt_code 27 31 mmZCAL_FUSES 0 0x2d98 7 0 2 fuse_valid 0 0 fuse_ron_override_val 3 8 fuse_ron_ctl 10 11 fuse_rtt_override_val 13 18 fuse_rtt_ctl 20 21 fuse_refresh_cal_en 22 22 fuse_spare 23 31 mmCORB_WRITE_POINTER 0 0x0 1 0 0 CORB_WRITE_POINTER 0 7 mmCORB_READ_POINTER 0 0x0 2 0 0 CORB_READ_POINTER 0 7 CORB_READ_POINTER_RESET 15 15 mmCORB_CONTROL 0 0x1 2 0 0 CORB_MEMORY_ERROR_INTERRUPT_ENABLE 0 0 ENABLE_CORB_DMA_ENGINE 1 1 mmCORB_STATUS 0 0x1 1 0 0 CORB_MEMORY_ERROR_INDICATION 0 0 mmCORB_SIZE 0 0x1 2 0 0 CORB_SIZE 0 1 CORB_SIZE_CAPABILITY 4 7 mmRIRB_LOWER_BASE_ADDRESS 0 0x2 2 0 0 RIRB_LOWER_BASE_UNIMPLEMENTED_BITS 0 6 RIRB_LOWER_BASE_ADDRESS 7 31 mmRIRB_UPPER_BASE_ADDRESS 0 0x3 1 0 0 RIRB_UPPER_BASE_ADDRESS 0 31 mmRIRB_WRITE_POINTER 0 0x4 2 0 0 RIRB_WRITE_POINTER 0 7 RIRB_WRITE_POINTER_RESET 15 15 mmRESPONSE_INTERRUPT_COUNT 0 0x4 1 0 0 N_RESPONSE_INTERRUPT_COUNT 0 7 mmRIRB_CONTROL 0 0x5 3 0 0 RESPONSE_INTERRUPT_CONTROL 0 0 RIRB_DMA_ENABLE 1 1 RESPONSE_OVERRUN_INTERRUPT_CONTROL 2 2 mmRIRB_STATUS 0 0x5 2 0 0 RESPONSE_INTERRUPT 0 0 RESPONSE_OVERRUN_INTERRUPT_STATUS 2 2 mmRIRB_SIZE 0 0x5 2 0 0 RIRB_SIZE 0 1 RIRB_SIZE_CAPABILITY 4 7 mmAZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_DATA 0 0x6 1 0 0 IMMEDIATE_COMMAND_WRITE 0 31 mmAZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_INDEX 0 0x6 1 0 0 IMMEDIATE_COMMAND_WRITE 0 16 mmAZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA 0 0x6 1 0 0 IMMEDIATE_COMMAND_WRITE 0 31 mmAZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX 0 0x6 1 0 0 IMMEDIATE_COMMAND_WRITE 0 16 mmAZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA 0 0x6 1 0 0 IMMEDIATE_COMMAND_WRITE 0 31 mmAZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX 0 0x6 1 0 0 IMMEDIATE_COMMAND_WRITE 0 16 mmIMMEDIATE_COMMAND_OUTPUT_INTERFACE 0 0x6 2 0 0 IMMEDIATE_COMMAND_WRITE_VERB_AND_PAYLOAD 0 27 IMMEDIATE_COMMAND_WRITE_CODEC_ADDRESS 28 31 mmIMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA 0 0x6 1 0 0 IMMEDIATE_COMMAND_WRITE 0 31 mmIMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX 0 0x6 1 0 0 IMMEDIATE_COMMAND_WRITE 0 15 mmIMMEDIATE_RESPONSE_INPUT_INTERFACE 0 0x7 1 0 0 IMMEDIATE_RESPONSE_READ 0 31 mmIMMEDIATE_COMMAND_STATUS 0 0x8 2 0 0 IMMEDIATE_COMMAND_BUSY 0 0 IMMEDIATE_RESULT_VALID 1 1 mmDMA_POSITION_LOWER_BASE_ADDRESS 0 0xa 3 0 0 DMA_POSITION_BUFFER_ENABLE 0 0 DMA_POSITION_LOWER_BASE_UNIMPLEMENTED_BITS 1 6 DMA_POSITION_LOWER_BASE_ADDRESS 7 31 mmDMA_POSITION_UPPER_BASE_ADDRESS 0 0xb 1 0 0 DMA_POSITION_UPPER_BASE_ADDRESS 0 31 mmWALL_CLOCK_COUNTER_ALIAS 0 0x74c 1 0 1 WALL_CLOCK_COUNTER_ALIAS 0 31 mmAZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS 0 0xe 12 0 0 STREAM_RESET 0 0 STREAM_RUN 1 1 INTERRUPT_ON_COMPLETION_ENABLE 2 2 FIFO_ERROR_INTERRUPT_ENABLE 3 3 DESCRIPTOR_ERROR_INTERRUPT_ENABLE 4 4 STRIPE_CONTROL 16 17 TRAFFIC_PRIORITY 18 18 STREAM_NUMBER 20 23 BUFFER_COMPLETION_INTERRUPT_STATUS 26 26 FIFO_ERROR 27 27 DESCRIPTOR_ERROR 28 28 FIFO_READY 29 29 mmAZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER 0 0xf 1 0 0 LINK_POSITION_IN_BUFFER 0 31 mmAZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH 0 0x10 1 0 0 CYCLIC_BUFFER_LENGTH 0 31 mmAZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX 0 0x11 1 0 0 LAST_VALID_INDEX 0 7 mmAZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE 0 0x12 1 0 0 FIFO_SIZE 0 15 mmAZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_FORMAT 0 0x12 5 0 0 NUMBER_OF_CHANNELS 0 3 BITS_PER_SAMPLE 4 6 SAMPLE_BASE_DIVISOR 8 10 SAMPLE_BASE_MULTIPLE 11 13 SAMPLE_BASE_RATE 14 14 mmAZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS 0 0x14 2 0 0 BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_UNIMPLEMENTED_BITS 0 6 BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS 7 31 mmAZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS 0 0x15 1 0 0 BUFFER_DESCRIPTOR_LIST_UPPER_BASE_ADDRESS 0 31 mmAZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS 0 0x761 1 0 1 LINK_POSITION_IN_BUFFER_ALIAS 0 31 mmAZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS 0 0x16 12 0 0 STREAM_RESET 0 0 STREAM_RUN 1 1 INTERRUPT_ON_COMPLETION_ENABLE 2 2 FIFO_ERROR_INTERRUPT_ENABLE 3 3 DESCRIPTOR_ERROR_INTERRUPT_ENABLE 4 4 STRIPE_CONTROL 16 17 TRAFFIC_PRIORITY 18 18 STREAM_NUMBER 20 23 BUFFER_COMPLETION_INTERRUPT_STATUS 26 26 FIFO_ERROR 27 27 DESCRIPTOR_ERROR 28 28 FIFO_READY 29 29 mmAZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER 0 0x17 1 0 0 LINK_POSITION_IN_BUFFER 0 31 mmAZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH 0 0x18 1 0 0 CYCLIC_BUFFER_LENGTH 0 31 mmAZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX 0 0x19 1 0 0 LAST_VALID_INDEX 0 7 mmAZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE 0 0x1a 1 0 0 FIFO_SIZE 0 15 mmAZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_FORMAT 0 0x1a 5 0 0 NUMBER_OF_CHANNELS 0 3 BITS_PER_SAMPLE 4 6 SAMPLE_BASE_DIVISOR 8 10 SAMPLE_BASE_MULTIPLE 11 13 SAMPLE_BASE_RATE 14 14 mmAZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS 0 0x1c 2 0 0 BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_UNIMPLEMENTED_BITS 0 6 BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS 7 31 mmAZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS 0 0x1d 1 0 0 BUFFER_DESCRIPTOR_LIST_UPPER_BASE_ADDRESS 0 31 mmAZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS 0 0x769 1 0 1 LINK_POSITION_IN_BUFFER_ALIAS 0 31 mmAZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS 0 0x1e 12 0 0 STREAM_RESET 0 0 STREAM_RUN 1 1 INTERRUPT_ON_COMPLETION_ENABLE 2 2 FIFO_ERROR_INTERRUPT_ENABLE 3 3 DESCRIPTOR_ERROR_INTERRUPT_ENABLE 4 4 STRIPE_CONTROL 16 17 TRAFFIC_PRIORITY 18 18 STREAM_NUMBER 20 23 BUFFER_COMPLETION_INTERRUPT_STATUS 26 26 FIFO_ERROR 27 27 DESCRIPTOR_ERROR 28 28 FIFO_READY 29 29 mmAZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER 0 0x1f 1 0 0 LINK_POSITION_IN_BUFFER 0 31 mmAZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH 0 0x20 1 0 0 CYCLIC_BUFFER_LENGTH 0 31 mmAZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX 0 0x21 1 0 0 LAST_VALID_INDEX 0 7 mmAZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE 0 0x22 1 0 0 FIFO_SIZE 0 15 mmAZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_FORMAT 0 0x22 5 0 0 NUMBER_OF_CHANNELS 0 3 BITS_PER_SAMPLE 4 6 SAMPLE_BASE_DIVISOR 8 10 SAMPLE_BASE_MULTIPLE 11 13 SAMPLE_BASE_RATE 14 14 mmAZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS 0 0x24 2 0 0 BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_UNIMPLEMENTED_BITS 0 6 BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS 7 31 mmAZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS 0 0x25 1 0 0 BUFFER_DESCRIPTOR_LIST_UPPER_BASE_ADDRESS 0 31 mmAZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS 0 0x771 1 0 1 LINK_POSITION_IN_BUFFER_ALIAS 0 31 mmAZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS 0 0x26 12 0 0 STREAM_RESET 0 0 STREAM_RUN 1 1 INTERRUPT_ON_COMPLETION_ENABLE 2 2 FIFO_ERROR_INTERRUPT_ENABLE 3 3 DESCRIPTOR_ERROR_INTERRUPT_ENABLE 4 4 STRIPE_CONTROL 16 17 TRAFFIC_PRIORITY 18 18 STREAM_NUMBER 20 23 BUFFER_COMPLETION_INTERRUPT_STATUS 26 26 FIFO_ERROR 27 27 DESCRIPTOR_ERROR 28 28 FIFO_READY 29 29 mmAZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER 0 0x27 1 0 0 LINK_POSITION_IN_BUFFER 0 31 mmAZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH 0 0x28 1 0 0 CYCLIC_BUFFER_LENGTH 0 31 mmAZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX 0 0x29 1 0 0 LAST_VALID_INDEX 0 7 mmAZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE 0 0x2a 1 0 0 FIFO_SIZE 0 15 mmAZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_FORMAT 0 0x2a 5 0 0 NUMBER_OF_CHANNELS 0 3 BITS_PER_SAMPLE 4 6 SAMPLE_BASE_DIVISOR 8 10 SAMPLE_BASE_MULTIPLE 11 13 SAMPLE_BASE_RATE 14 14 mmAZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS 0 0x2c 2 0 0 BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_UNIMPLEMENTED_BITS 0 6 BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS 7 31 mmAZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS 0 0x2d 1 0 0 BUFFER_DESCRIPTOR_LIST_UPPER_BASE_ADDRESS 0 31 mmAZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS 0 0x779 1 0 1 LINK_POSITION_IN_BUFFER_ALIAS 0 31 mmAZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS 0 0x2e 12 0 0 STREAM_RESET 0 0 STREAM_RUN 1 1 INTERRUPT_ON_COMPLETION_ENABLE 2 2 FIFO_ERROR_INTERRUPT_ENABLE 3 3 DESCRIPTOR_ERROR_INTERRUPT_ENABLE 4 4 STRIPE_CONTROL 16 17 TRAFFIC_PRIORITY 18 18 STREAM_NUMBER 20 23 BUFFER_COMPLETION_INTERRUPT_STATUS 26 26 FIFO_ERROR 27 27 DESCRIPTOR_ERROR 28 28 FIFO_READY 29 29 mmAZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER 0 0x2f 1 0 0 LINK_POSITION_IN_BUFFER 0 31 mmAZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH 0 0x30 1 0 0 CYCLIC_BUFFER_LENGTH 0 31 mmAZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX 0 0x31 1 0 0 LAST_VALID_INDEX 0 7 mmAZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE 0 0x32 1 0 0 FIFO_SIZE 0 15 mmAZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_FORMAT 0 0x32 5 0 0 NUMBER_OF_CHANNELS 0 3 BITS_PER_SAMPLE 4 6 SAMPLE_BASE_DIVISOR 8 10 SAMPLE_BASE_MULTIPLE 11 13 SAMPLE_BASE_RATE 14 14 mmAZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS 0 0x34 2 0 0 BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_UNIMPLEMENTED_BITS 0 6 BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS 7 31 mmAZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS 0 0x35 1 0 0 BUFFER_DESCRIPTOR_LIST_UPPER_BASE_ADDRESS 0 31 mmAZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS 0 0x781 1 0 1 LINK_POSITION_IN_BUFFER_ALIAS 0 31 mmAZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS 0 0x36 12 0 0 STREAM_RESET 0 0 STREAM_RUN 1 1 INTERRUPT_ON_COMPLETION_ENABLE 2 2 FIFO_ERROR_INTERRUPT_ENABLE 3 3 DESCRIPTOR_ERROR_INTERRUPT_ENABLE 4 4 STRIPE_CONTROL 16 17 TRAFFIC_PRIORITY 18 18 STREAM_NUMBER 20 23 BUFFER_COMPLETION_INTERRUPT_STATUS 26 26 FIFO_ERROR 27 27 DESCRIPTOR_ERROR 28 28 FIFO_READY 29 29 mmAZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER 0 0x37 1 0 0 LINK_POSITION_IN_BUFFER 0 31 mmAZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH 0 0x38 1 0 0 CYCLIC_BUFFER_LENGTH 0 31 mmAZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX 0 0x39 1 0 0 LAST_VALID_INDEX 0 7 mmAZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE 0 0x3a 1 0 0 FIFO_SIZE 0 15 mmAZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_FORMAT 0 0x3a 5 0 0 NUMBER_OF_CHANNELS 0 3 BITS_PER_SAMPLE 4 6 SAMPLE_BASE_DIVISOR 8 10 SAMPLE_BASE_MULTIPLE 11 13 SAMPLE_BASE_RATE 14 14 mmAZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS 0 0x3c 2 0 0 BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_UNIMPLEMENTED_BITS 0 6 BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS 7 31 mmAZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS 0 0x3d 1 0 0 BUFFER_DESCRIPTOR_LIST_UPPER_BASE_ADDRESS 0 31 mmAZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS 0 0x789 1 0 1 LINK_POSITION_IN_BUFFER_ALIAS 0 31 mmAZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS 0 0x3e 12 0 0 STREAM_RESET 0 0 STREAM_RUN 1 1 INTERRUPT_ON_COMPLETION_ENABLE 2 2 FIFO_ERROR_INTERRUPT_ENABLE 3 3 DESCRIPTOR_ERROR_INTERRUPT_ENABLE 4 4 STRIPE_CONTROL 16 17 TRAFFIC_PRIORITY 18 18 STREAM_NUMBER 20 23 BUFFER_COMPLETION_INTERRUPT_STATUS 26 26 FIFO_ERROR 27 27 DESCRIPTOR_ERROR 28 28 FIFO_READY 29 29 mmAZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER 0 0x3f 1 0 0 LINK_POSITION_IN_BUFFER 0 31 mmAZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH 0 0x40 1 0 0 CYCLIC_BUFFER_LENGTH 0 31 mmAZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX 0 0x41 1 0 0 LAST_VALID_INDEX 0 7 mmAZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE 0 0x42 1 0 0 FIFO_SIZE 0 15 mmAZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_FORMAT 0 0x42 5 0 0 NUMBER_OF_CHANNELS 0 3 BITS_PER_SAMPLE 4 6 SAMPLE_BASE_DIVISOR 8 10 SAMPLE_BASE_MULTIPLE 11 13 SAMPLE_BASE_RATE 14 14 mmAZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS 0 0x44 2 0 0 BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_UNIMPLEMENTED_BITS 0 6 BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS 7 31 mmAZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS 0 0x45 1 0 0 BUFFER_DESCRIPTOR_LIST_UPPER_BASE_ADDRESS 0 31 mmAZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS 0 0x791 1 0 1 LINK_POSITION_IN_BUFFER_ALIAS 0 31 mmAZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS 0 0x46 12 0 0 STREAM_RESET 0 0 STREAM_RUN 1 1 INTERRUPT_ON_COMPLETION_ENABLE 2 2 FIFO_ERROR_INTERRUPT_ENABLE 3 3 DESCRIPTOR_ERROR_INTERRUPT_ENABLE 4 4 STRIPE_CONTROL 16 17 TRAFFIC_PRIORITY 18 18 STREAM_NUMBER 20 23 BUFFER_COMPLETION_INTERRUPT_STATUS 26 26 FIFO_ERROR 27 27 DESCRIPTOR_ERROR 28 28 FIFO_READY 29 29 mmAZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER 0 0x47 1 0 0 LINK_POSITION_IN_BUFFER 0 31 mmAZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH 0 0x48 1 0 0 CYCLIC_BUFFER_LENGTH 0 31 mmAZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX 0 0x49 1 0 0 LAST_VALID_INDEX 0 7 mmAZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE 0 0x4a 1 0 0 FIFO_SIZE 0 15 mmAZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_FORMAT 0 0x4a 5 0 0 NUMBER_OF_CHANNELS 0 3 BITS_PER_SAMPLE 4 6 SAMPLE_BASE_DIVISOR 8 10 SAMPLE_BASE_MULTIPLE 11 13 SAMPLE_BASE_RATE 14 14 mmAZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS 0 0x4c 2 0 0 BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_UNIMPLEMENTED_BITS 0 6 BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS 7 31 mmAZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS 0 0x4d 1 0 0 BUFFER_DESCRIPTOR_LIST_UPPER_BASE_ADDRESS 0 31 mmAZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS 0 0x799 1 0 1 LINK_POSITION_IN_BUFFER_ALIAS 0 31 ixAZF0STREAM0_AZALIA_FIFO_SIZE_CONTROL 2 0x0 3 0 4294967295 MIN_FIFO_SIZE 0 6 MAX_FIFO_SIZE 8 14 MAX_LATENCY_SUPPORT 16 23 ixAZF0STREAM0_AZALIA_LATENCY_COUNTER_CONTROL 2 0x1 1 0 4294967295 AZALIA_LATENCY_COUNTER_RESET 0 0 ixAZF0STREAM0_AZALIA_WORSTCASE_LATENCY_COUNT 2 0x2 1 0 4294967295 AZALIA_WORSTCASE_LATENCY_COUNT 0 31 ixAZF0STREAM0_AZALIA_CUMULATIVE_LATENCY_COUNT 2 0x3 1 0 4294967295 AZALIA_CUMULATIVE_LATENCY_COUNT 0 31 ixAZF0STREAM0_AZALIA_CUMULATIVE_REQUEST_COUNT 2 0x4 1 0 4294967295 AZALIA_CUMULATIVE_REQUEST_COUNT 0 31 ixAZF0STREAM1_AZALIA_FIFO_SIZE_CONTROL 2 0x0 3 0 4294967295 MIN_FIFO_SIZE 0 6 MAX_FIFO_SIZE 8 14 MAX_LATENCY_SUPPORT 16 23 ixAZF0STREAM1_AZALIA_LATENCY_COUNTER_CONTROL 2 0x1 1 0 4294967295 AZALIA_LATENCY_COUNTER_RESET 0 0 ixAZF0STREAM1_AZALIA_WORSTCASE_LATENCY_COUNT 2 0x2 1 0 4294967295 AZALIA_WORSTCASE_LATENCY_COUNT 0 31 ixAZF0STREAM1_AZALIA_CUMULATIVE_LATENCY_COUNT 2 0x3 1 0 4294967295 AZALIA_CUMULATIVE_LATENCY_COUNT 0 31 ixAZF0STREAM1_AZALIA_CUMULATIVE_REQUEST_COUNT 2 0x4 1 0 4294967295 AZALIA_CUMULATIVE_REQUEST_COUNT 0 31 ixAZF0STREAM2_AZALIA_FIFO_SIZE_CONTROL 2 0x0 3 0 4294967295 MIN_FIFO_SIZE 0 6 MAX_FIFO_SIZE 8 14 MAX_LATENCY_SUPPORT 16 23 ixAZF0STREAM2_AZALIA_LATENCY_COUNTER_CONTROL 2 0x1 1 0 4294967295 AZALIA_LATENCY_COUNTER_RESET 0 0 ixAZF0STREAM2_AZALIA_WORSTCASE_LATENCY_COUNT 2 0x2 1 0 4294967295 AZALIA_WORSTCASE_LATENCY_COUNT 0 31 ixAZF0STREAM2_AZALIA_CUMULATIVE_LATENCY_COUNT 2 0x3 1 0 4294967295 AZALIA_CUMULATIVE_LATENCY_COUNT 0 31 ixAZF0STREAM2_AZALIA_CUMULATIVE_REQUEST_COUNT 2 0x4 1 0 4294967295 AZALIA_CUMULATIVE_REQUEST_COUNT 0 31 ixAZF0STREAM3_AZALIA_FIFO_SIZE_CONTROL 2 0x0 3 0 4294967295 MIN_FIFO_SIZE 0 6 MAX_FIFO_SIZE 8 14 MAX_LATENCY_SUPPORT 16 23 ixAZF0STREAM3_AZALIA_LATENCY_COUNTER_CONTROL 2 0x1 1 0 4294967295 AZALIA_LATENCY_COUNTER_RESET 0 0 ixAZF0STREAM3_AZALIA_WORSTCASE_LATENCY_COUNT 2 0x2 1 0 4294967295 AZALIA_WORSTCASE_LATENCY_COUNT 0 31 ixAZF0STREAM3_AZALIA_CUMULATIVE_LATENCY_COUNT 2 0x3 1 0 4294967295 AZALIA_CUMULATIVE_LATENCY_COUNT 0 31 ixAZF0STREAM3_AZALIA_CUMULATIVE_REQUEST_COUNT 2 0x4 1 0 4294967295 AZALIA_CUMULATIVE_REQUEST_COUNT 0 31 ixAZF0STREAM4_AZALIA_FIFO_SIZE_CONTROL 2 0x0 3 0 4294967295 MIN_FIFO_SIZE 0 6 MAX_FIFO_SIZE 8 14 MAX_LATENCY_SUPPORT 16 23 ixAZF0STREAM4_AZALIA_LATENCY_COUNTER_CONTROL 2 0x1 1 0 4294967295 AZALIA_LATENCY_COUNTER_RESET 0 0 ixAZF0STREAM4_AZALIA_WORSTCASE_LATENCY_COUNT 2 0x2 1 0 4294967295 AZALIA_WORSTCASE_LATENCY_COUNT 0 31 ixAZF0STREAM4_AZALIA_CUMULATIVE_LATENCY_COUNT 2 0x3 1 0 4294967295 AZALIA_CUMULATIVE_LATENCY_COUNT 0 31 ixAZF0STREAM4_AZALIA_CUMULATIVE_REQUEST_COUNT 2 0x4 1 0 4294967295 AZALIA_CUMULATIVE_REQUEST_COUNT 0 31 ixAZF0STREAM5_AZALIA_FIFO_SIZE_CONTROL 2 0x0 3 0 4294967295 MIN_FIFO_SIZE 0 6 MAX_FIFO_SIZE 8 14 MAX_LATENCY_SUPPORT 16 23 ixAZF0STREAM5_AZALIA_LATENCY_COUNTER_CONTROL 2 0x1 1 0 4294967295 AZALIA_LATENCY_COUNTER_RESET 0 0 ixAZF0STREAM5_AZALIA_WORSTCASE_LATENCY_COUNT 2 0x2 1 0 4294967295 AZALIA_WORSTCASE_LATENCY_COUNT 0 31 ixAZF0STREAM5_AZALIA_CUMULATIVE_LATENCY_COUNT 2 0x3 1 0 4294967295 AZALIA_CUMULATIVE_LATENCY_COUNT 0 31 ixAZF0STREAM5_AZALIA_CUMULATIVE_REQUEST_COUNT 2 0x4 1 0 4294967295 AZALIA_CUMULATIVE_REQUEST_COUNT 0 31 ixAZF0STREAM6_AZALIA_FIFO_SIZE_CONTROL 2 0x0 3 0 4294967295 MIN_FIFO_SIZE 0 6 MAX_FIFO_SIZE 8 14 MAX_LATENCY_SUPPORT 16 23 ixAZF0STREAM6_AZALIA_LATENCY_COUNTER_CONTROL 2 0x1 1 0 4294967295 AZALIA_LATENCY_COUNTER_RESET 0 0 ixAZF0STREAM6_AZALIA_WORSTCASE_LATENCY_COUNT 2 0x2 1 0 4294967295 AZALIA_WORSTCASE_LATENCY_COUNT 0 31 ixAZF0STREAM6_AZALIA_CUMULATIVE_LATENCY_COUNT 2 0x3 1 0 4294967295 AZALIA_CUMULATIVE_LATENCY_COUNT 0 31 ixAZF0STREAM6_AZALIA_CUMULATIVE_REQUEST_COUNT 2 0x4 1 0 4294967295 AZALIA_CUMULATIVE_REQUEST_COUNT 0 31 ixAZF0STREAM7_AZALIA_FIFO_SIZE_CONTROL 2 0x0 3 0 4294967295 MIN_FIFO_SIZE 0 6 MAX_FIFO_SIZE 8 14 MAX_LATENCY_SUPPORT 16 23 ixAZF0STREAM7_AZALIA_LATENCY_COUNTER_CONTROL 2 0x1 1 0 4294967295 AZALIA_LATENCY_COUNTER_RESET 0 0 ixAZF0STREAM7_AZALIA_WORSTCASE_LATENCY_COUNT 2 0x2 1 0 4294967295 AZALIA_WORSTCASE_LATENCY_COUNT 0 31 ixAZF0STREAM7_AZALIA_CUMULATIVE_LATENCY_COUNT 2 0x3 1 0 4294967295 AZALIA_CUMULATIVE_LATENCY_COUNT 0 31 ixAZF0STREAM7_AZALIA_CUMULATIVE_REQUEST_COUNT 2 0x4 1 0 4294967295 AZALIA_CUMULATIVE_REQUEST_COUNT 0 31 ixAZF0STREAM8_AZALIA_FIFO_SIZE_CONTROL 2 0x0 3 0 4294967295 MIN_FIFO_SIZE 0 6 MAX_FIFO_SIZE 8 14 MAX_LATENCY_SUPPORT 16 23 ixAZF0STREAM8_AZALIA_LATENCY_COUNTER_CONTROL 2 0x1 1 0 4294967295 AZALIA_LATENCY_COUNTER_RESET 0 0 ixAZF0STREAM8_AZALIA_WORSTCASE_LATENCY_COUNT 2 0x2 1 0 4294967295 AZALIA_WORSTCASE_LATENCY_COUNT 0 31 ixAZF0STREAM8_AZALIA_CUMULATIVE_LATENCY_COUNT 2 0x3 1 0 4294967295 AZALIA_CUMULATIVE_LATENCY_COUNT 0 31 ixAZF0STREAM8_AZALIA_CUMULATIVE_REQUEST_COUNT 2 0x4 1 0 4294967295 AZALIA_CUMULATIVE_REQUEST_COUNT 0 31 ixAZF0STREAM9_AZALIA_FIFO_SIZE_CONTROL 2 0x0 3 0 4294967295 MIN_FIFO_SIZE 0 6 MAX_FIFO_SIZE 8 14 MAX_LATENCY_SUPPORT 16 23 ixAZF0STREAM9_AZALIA_LATENCY_COUNTER_CONTROL 2 0x1 1 0 4294967295 AZALIA_LATENCY_COUNTER_RESET 0 0 ixAZF0STREAM9_AZALIA_WORSTCASE_LATENCY_COUNT 2 0x2 1 0 4294967295 AZALIA_WORSTCASE_LATENCY_COUNT 0 31 ixAZF0STREAM9_AZALIA_CUMULATIVE_LATENCY_COUNT 2 0x3 1 0 4294967295 AZALIA_CUMULATIVE_LATENCY_COUNT 0 31 ixAZF0STREAM9_AZALIA_CUMULATIVE_REQUEST_COUNT 2 0x4 1 0 4294967295 AZALIA_CUMULATIVE_REQUEST_COUNT 0 31 ixAZF0STREAM10_AZALIA_FIFO_SIZE_CONTROL 2 0x0 3 0 4294967295 MIN_FIFO_SIZE 0 6 MAX_FIFO_SIZE 8 14 MAX_LATENCY_SUPPORT 16 23 ixAZF0STREAM10_AZALIA_LATENCY_COUNTER_CONTROL 2 0x1 1 0 4294967295 AZALIA_LATENCY_COUNTER_RESET 0 0 ixAZF0STREAM10_AZALIA_WORSTCASE_LATENCY_COUNT 2 0x2 1 0 4294967295 AZALIA_WORSTCASE_LATENCY_COUNT 0 31 ixAZF0STREAM10_AZALIA_CUMULATIVE_LATENCY_COUNT 2 0x3 1 0 4294967295 AZALIA_CUMULATIVE_LATENCY_COUNT 0 31 ixAZF0STREAM10_AZALIA_CUMULATIVE_REQUEST_COUNT 2 0x4 1 0 4294967295 AZALIA_CUMULATIVE_REQUEST_COUNT 0 31 ixAZF0STREAM11_AZALIA_FIFO_SIZE_CONTROL 2 0x0 3 0 4294967295 MIN_FIFO_SIZE 0 6 MAX_FIFO_SIZE 8 14 MAX_LATENCY_SUPPORT 16 23 ixAZF0STREAM11_AZALIA_LATENCY_COUNTER_CONTROL 2 0x1 1 0 4294967295 AZALIA_LATENCY_COUNTER_RESET 0 0 ixAZF0STREAM11_AZALIA_WORSTCASE_LATENCY_COUNT 2 0x2 1 0 4294967295 AZALIA_WORSTCASE_LATENCY_COUNT 0 31 ixAZF0STREAM11_AZALIA_CUMULATIVE_LATENCY_COUNT 2 0x3 1 0 4294967295 AZALIA_CUMULATIVE_LATENCY_COUNT 0 31 ixAZF0STREAM11_AZALIA_CUMULATIVE_REQUEST_COUNT 2 0x4 1 0 4294967295 AZALIA_CUMULATIVE_REQUEST_COUNT 0 31 ixAZF0STREAM12_AZALIA_FIFO_SIZE_CONTROL 2 0x0 3 0 4294967295 MIN_FIFO_SIZE 0 6 MAX_FIFO_SIZE 8 14 MAX_LATENCY_SUPPORT 16 23 ixAZF0STREAM12_AZALIA_LATENCY_COUNTER_CONTROL 2 0x1 1 0 4294967295 AZALIA_LATENCY_COUNTER_RESET 0 0 ixAZF0STREAM12_AZALIA_WORSTCASE_LATENCY_COUNT 2 0x2 1 0 4294967295 AZALIA_WORSTCASE_LATENCY_COUNT 0 31 ixAZF0STREAM12_AZALIA_CUMULATIVE_LATENCY_COUNT 2 0x3 1 0 4294967295 AZALIA_CUMULATIVE_LATENCY_COUNT 0 31 ixAZF0STREAM12_AZALIA_CUMULATIVE_REQUEST_COUNT 2 0x4 1 0 4294967295 AZALIA_CUMULATIVE_REQUEST_COUNT 0 31 ixAZF0STREAM13_AZALIA_FIFO_SIZE_CONTROL 2 0x0 3 0 4294967295 MIN_FIFO_SIZE 0 6 MAX_FIFO_SIZE 8 14 MAX_LATENCY_SUPPORT 16 23 ixAZF0STREAM13_AZALIA_LATENCY_COUNTER_CONTROL 2 0x1 1 0 4294967295 AZALIA_LATENCY_COUNTER_RESET 0 0 ixAZF0STREAM13_AZALIA_WORSTCASE_LATENCY_COUNT 2 0x2 1 0 4294967295 AZALIA_WORSTCASE_LATENCY_COUNT 0 31 ixAZF0STREAM13_AZALIA_CUMULATIVE_LATENCY_COUNT 2 0x3 1 0 4294967295 AZALIA_CUMULATIVE_LATENCY_COUNT 0 31 ixAZF0STREAM13_AZALIA_CUMULATIVE_REQUEST_COUNT 2 0x4 1 0 4294967295 AZALIA_CUMULATIVE_REQUEST_COUNT 0 31 ixAZF0STREAM14_AZALIA_FIFO_SIZE_CONTROL 2 0x0 3 0 4294967295 MIN_FIFO_SIZE 0 6 MAX_FIFO_SIZE 8 14 MAX_LATENCY_SUPPORT 16 23 ixAZF0STREAM14_AZALIA_LATENCY_COUNTER_CONTROL 2 0x1 1 0 4294967295 AZALIA_LATENCY_COUNTER_RESET 0 0 ixAZF0STREAM14_AZALIA_WORSTCASE_LATENCY_COUNT 2 0x2 1 0 4294967295 AZALIA_WORSTCASE_LATENCY_COUNT 0 31 ixAZF0STREAM14_AZALIA_CUMULATIVE_LATENCY_COUNT 2 0x3 1 0 4294967295 AZALIA_CUMULATIVE_LATENCY_COUNT 0 31 ixAZF0STREAM14_AZALIA_CUMULATIVE_REQUEST_COUNT 2 0x4 1 0 4294967295 AZALIA_CUMULATIVE_REQUEST_COUNT 0 31 ixAZF0STREAM15_AZALIA_FIFO_SIZE_CONTROL 2 0x0 3 0 4294967295 MIN_FIFO_SIZE 0 6 MAX_FIFO_SIZE 8 14 MAX_LATENCY_SUPPORT 16 23 ixAZF0STREAM15_AZALIA_LATENCY_COUNTER_CONTROL 2 0x1 1 0 4294967295 AZALIA_LATENCY_COUNTER_RESET 0 0 ixAZF0STREAM15_AZALIA_WORSTCASE_LATENCY_COUNT 2 0x2 1 0 4294967295 AZALIA_WORSTCASE_LATENCY_COUNT 0 31 ixAZF0STREAM15_AZALIA_CUMULATIVE_LATENCY_COUNT 2 0x3 1 0 4294967295 AZALIA_CUMULATIVE_LATENCY_COUNT 0 31 ixAZF0STREAM15_AZALIA_CUMULATIVE_REQUEST_COUNT 2 0x4 1 0 4294967295 AZALIA_CUMULATIVE_REQUEST_COUNT 0 31 ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 2 0x1 14 0 4294967295 AUDIO_CHANNEL_CAPABILITIES 0 0 INPUT_AMPLIFIER_PRESENT 1 1 OUTPUT_AMPLIFIER_PRESENT 2 2 AMPLIFIER_PARAMETER_OVERRIDE 3 3 FORMAT_OVERRIDE 4 4 STRIPE 5 5 PROCESSING_WIDGET 6 6 UNSOLICITED_RESPONSE_CAPABILITY 7 7 CONNECTION_LIST 8 8 DIGITAL 9 9 POWER_CONTROL 10 10 LR_SWAP 11 11 AUDIO_WIDGET_CAPABILITIES_DELAY 16 19 TYPE 20 23 ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT 2 0x2 6 0 4294967295 NUMBER_OF_CHANNELS 0 3 BITS_PER_SAMPLE 4 6 SAMPLE_BASE_DIVISOR 8 10 SAMPLE_BASE_MULTIPLE 11 13 SAMPLE_BASE_RATE 14 14 STREAM_TYPE 15 15 ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID 2 0x3 2 0 4294967295 CHANNEL_ID 0 3 STREAM_ID 4 7 ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER 2 0x4 10 0 4294967295 DIGEN 0 0 V 1 1 VCFG 2 2 PRE 3 3 COPY 4 4 NON_AUDIO 5 5 PRO 6 6 L 7 7 CC 8 14 KEEPALIVE 23 23 ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS 2 0x5 1 0 4294967295 STREAM_FORMATS 0 31 ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 2 0x6 2 0 4294967295 AUDIO_RATE_CAPABILITIES 0 11 AUDIO_BIT_CAPABILITIES 16 20 ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL 2 0x7 2 0 4294967295 STRIPE_CONTROL 0 1 STRIPE_CAPABILITY 20 22 ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE 2 0x8 1 0 4294967295 RAMP_RATE 0 7 ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING 2 0x9 4 0 4294967295 PRESENTATION_TIME_EMBEDDING_ENABLE 0 0 PRESENTATION_TIME_OFFSET_CHANGED 1 1 CLEAR_GTC_COUNTER_MIN_MAX_DELTA 2 2 PRESENTATION_TIME_EMBEDDING_GROUP 4 6 ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA 2 0xc 1 0 4294967295 GTC_COUNTER_DELTA 0 31 ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN 2 0xd 1 0 4294967295 GTC_COUNTER_DELTA_MIN 0 31 ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX 2 0xe 1 0 4294967295 GTC_COUNTER_DELTA_MAX 0 31 ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 2 0x20 13 0 4294967295 AUDIO_CHANNEL_CAPABILITIES 0 0 INPUT_AMPLIFIER_PRESENT 1 1 OUTPUT_AMPLIFIER_PRESENT 2 2 AMPLIFIER_PARAMETER_OVERRIDE 3 3 STRIPE 5 5 PROCESSING_WIDGET 6 6 UNSOLICITED_RESPONSE_CAPABILITY 7 7 CONNECTION_LIST 8 8 DIGITAL 9 9 POWER_CONTROL 10 10 LR_SWAP 11 11 AUDIO_WIDGET_CAPABILITIES_DELAY 16 19 TYPE 20 23 ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES 2 0x21 11 0 4294967295 IMPEDANCE_SENSE_CAPABLE 0 0 TRIGGER_REQUIRED 1 1 JACK_DETECTION_CAPABILITY 2 2 HEADPHONE_DRIVE_CAPABLE 3 3 OUTPUT_CAPABLE 4 4 INPUT_CAPABLE 5 5 BALANCED_I_O_PINS 6 6 HDMI 7 7 VREF_CONTROL 8 15 EAPD_CAPABLE 16 16 DP 24 24 ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE 2 0x22 2 0 4294967295 TAG 0 5 ENABLE 7 7 ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE 2 0x23 1 0 4294967295 IMPEDANCE_SENSE 0 30 ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL 2 0x24 1 0 4294967295 OUT_ENABLE 6 6 ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER 2 0x25 8 0 4294967295 SPEAKER_ALLOCATION 0 6 CHANNEL_ALLOCATION 8 15 HDMI_CONNECTION 16 16 DP_CONNECTION 17 17 EXTRA_CONNECTION_INFO 18 23 LFE_PLAYBACK_LEVEL 24 25 LEVEL_SHIFT 27 30 DOWN_MIX_INHIBIT 31 31 ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 2 0x28 4 0 4294967295 MAX_CHANNELS 0 2 SUPPORTED_FREQUENCIES 8 15 DESCRIPTOR_BYTE_2 16 23 SUPPORTED_FREQUENCIES_STEREO 24 31 ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 2 0x29 3 0 4294967295 MAX_CHANNELS 0 2 SUPPORTED_FREQUENCIES 8 15 DESCRIPTOR_BYTE_2 16 23 ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 2 0x2a 3 0 4294967295 MAX_CHANNELS 0 2 SUPPORTED_FREQUENCIES 8 15 DESCRIPTOR_BYTE_2 16 23 ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 2 0x2b 3 0 4294967295 MAX_CHANNELS 0 2 SUPPORTED_FREQUENCIES 8 15 DESCRIPTOR_BYTE_2 16 23 ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 2 0x2c 3 0 4294967295 MAX_CHANNELS 0 2 SUPPORTED_FREQUENCIES 8 15 DESCRIPTOR_BYTE_2 16 23 ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 2 0x2d 3 0 4294967295 MAX_CHANNELS 0 2 SUPPORTED_FREQUENCIES 8 15 DESCRIPTOR_BYTE_2 16 23 ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 2 0x2e 3 0 4294967295 MAX_CHANNELS 0 2 SUPPORTED_FREQUENCIES 8 15 DESCRIPTOR_BYTE_2 16 23 ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 2 0x2f 3 0 4294967295 MAX_CHANNELS 0 2 SUPPORTED_FREQUENCIES 8 15 DESCRIPTOR_BYTE_2 16 23 ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 2 0x30 3 0 4294967295 MAX_CHANNELS 0 2 SUPPORTED_FREQUENCIES 8 15 DESCRIPTOR_BYTE_2 16 23 ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 2 0x31 3 0 4294967295 MAX_CHANNELS 0 2 SUPPORTED_FREQUENCIES 8 15 DESCRIPTOR_BYTE_2 16 23 ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 2 0x32 3 0 4294967295 MAX_CHANNELS 0 2 SUPPORTED_FREQUENCIES 8 15 DESCRIPTOR_BYTE_2 16 23 ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 2 0x33 3 0 4294967295 MAX_CHANNELS 0 2 SUPPORTED_FREQUENCIES 8 15 DESCRIPTOR_BYTE_2 16 23 ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 2 0x34 3 0 4294967295 MAX_CHANNELS 0 2 SUPPORTED_FREQUENCIES 8 15 DESCRIPTOR_BYTE_2 16 23 ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 2 0x35 3 0 4294967295 MAX_CHANNELS 0 2 SUPPORTED_FREQUENCIES 8 15 DESCRIPTOR_BYTE_2 16 23 ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE 2 0x36 12 0 4294967295 MULTICHANNEL01_ENABLE 0 0 MULTICHANNEL01_MUTE 1 1 MULTICHANNEL01_CHANNEL_ID 4 7 MULTICHANNEL23_ENABLE 8 8 MULTICHANNEL23_MUTE 9 9 MULTICHANNEL23_CHANNEL_ID 12 15 MULTICHANNEL45_ENABLE 16 16 MULTICHANNEL45_MUTE 17 17 MULTICHANNEL45_CHANNEL_ID 20 23 MULTICHANNEL67_ENABLE 24 24 MULTICHANNEL67_MUTE 25 25 MULTICHANNEL67_CHANNEL_ID 28 31 ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC 2 0x37 2 0 4294967295 VIDEO_LIPSYNC 0 7 AUDIO_LIPSYNC 8 15 ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR 2 0x38 2 0 4294967295 HBR_CAPABLE 0 0 HBR_ENABLE 4 4 ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0 2 0x3a 2 0 4294967295 MANUFACTURER_ID 0 15 PRODUCT_ID 16 31 ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1 2 0x3b 1 0 4294967295 SINK_DESCRIPTION_LEN 0 7 ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2 2 0x3c 1 0 4294967295 PORT_ID0 0 31 ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3 2 0x3d 1 0 4294967295 PORT_ID1 0 31 ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4 2 0x3e 4 0 4294967295 DESCRIPTION0 0 7 DESCRIPTION1 8 15 DESCRIPTION2 16 23 DESCRIPTION3 24 31 ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5 2 0x3f 4 0 4294967295 DESCRIPTION4 0 7 DESCRIPTION5 8 15 DESCRIPTION6 16 23 DESCRIPTION7 24 31 ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6 2 0x40 4 0 4294967295 DESCRIPTION8 0 7 DESCRIPTION9 8 15 DESCRIPTION10 16 23 DESCRIPTION11 24 31 ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7 2 0x41 4 0 4294967295 DESCRIPTION12 0 7 DESCRIPTION13 8 15 DESCRIPTION14 16 23 DESCRIPTION15 24 31 ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8 2 0x42 2 0 4294967295 DESCRIPTION16 0 7 DESCRIPTION17 8 15 ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL 2 0x54 3 0 4294967295 CLOCK_GATING_DISABLE 0 0 CLOCK_ON_STATE 4 4 AUDIO_ENABLED 31 31 ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 2 0x55 2 0 4294967295 UNSOLICITED_RESPONSE_PAYLOAD 0 25 UNSOLICITED_RESPONSE_FORCE 28 28 ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 2 0x56 8 0 4294967295 SEQUENCE 0 3 DEFAULT_ASSOCIATION 4 7 MISC 8 11 COLOR 12 15 CONNECTION_TYPE 16 19 DEFAULT_DEVICE 20 23 LOCATION 24 29 PORT_CONNECTIVITY 30 31 ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2 2 0x57 12 0 4294967295 MULTICHANNEL1_ENABLE 0 0 MULTICHANNEL1_MUTE 1 1 MULTICHANNEL1_CHANNEL_ID 4 7 MULTICHANNEL3_ENABLE 8 8 MULTICHANNEL3_MUTE 9 9 MULTICHANNEL3_CHANNEL_ID 12 15 MULTICHANNEL5_ENABLE 16 16 MULTICHANNEL5_MUTE 17 17 MULTICHANNEL5_CHANNEL_ID 20 23 MULTICHANNEL7_ENABLE 24 24 MULTICHANNEL7_MUTE 25 25 MULTICHANNEL7_CHANNEL_ID 28 31 ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE 2 0x58 1 0 4294967295 MULTICHANNEL_MODE 0 0 ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0 2 0x59 2 0 4294967295 IEC_60958_CS_MODE 0 1 IEC_60958_CS_SOURCE_NUMBER 2 5 ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1 2 0x5a 4 0 4294967295 IEC_60958_CS_CLOCK_ACCURACY 0 1 IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN 2 2 IEC_60958_CS_WORD_LENGTH 3 6 IEC_60958_CS_WORD_LENGTH_OVRRD_EN 7 7 ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2 2 0x5b 2 0 4294967295 IEC_60958_CS_SAMPLING_FREQUENCY 0 5 IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN 6 6 ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3 2 0x5c 2 0 4294967295 IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY 0 3 IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN 4 4 ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4 2 0x5d 4 0 4294967295 IEC_60958_CS_SAMPLING_FREQUENCY_COEFF 0 3 IEC_60958_CS_MPEG_SURROUND_INFO 4 4 IEC_60958_CS_CGMS_A 5 6 IEC_60958_CS_CGMS_A_VALID 7 7 ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5 2 0x5e 2 0 4294967295 IEC_60958_CS_CHANNEL_NUMBER_L 0 3 IEC_60958_CS_CHANNEL_NUMBER_R 4 7 ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6 2 0x5f 2 0 4294967295 IEC_60958_CS_CHANNEL_NUMBER_2 0 3 IEC_60958_CS_CHANNEL_NUMBER_3 4 7 ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7 2 0x60 2 0 4294967295 IEC_60958_CS_CHANNEL_NUMBER_4 0 3 IEC_60958_CS_CHANNEL_NUMBER_5 4 7 ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8 2 0x61 2 0 4294967295 IEC_60958_CS_CHANNEL_NUMBER_6 0 3 IEC_60958_CS_CHANNEL_NUMBER_7 4 7 ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO 2 0x62 1 0 4294967295 ASSOCIATION_INFO 0 31 ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS 2 0x63 1 0 4294967295 OUTPUT_ACTIVE 0 0 ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 2 0x64 2 0 4294967295 LPIB_SNAPSHOT_LOCK 0 0 CYCLIC_BUFFER_WRAP_COUNT 8 15 ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB 2 0x65 1 0 4294967295 LPIB 0 31 ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 2 0x66 1 0 4294967295 LPIB_TIMER_SNAPSHOT 0 31 ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE 2 0x67 1 0 4294967295 CODING_TYPE 0 7 ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED 2 0x68 4 0 4294967295 FORMAT_CHANGED 0 0 FORMAT_CHANGED_ACK_UR_ENABLE 1 1 FORMAT_CHANGE_REASON 8 15 FORMAT_CHANGE_RESPONSE 16 23 ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION 2 0x69 1 0 4294967295 WIRELESS_DISPLAY_IDENTIFICATION 0 1 ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE 2 0x6a 2 0 4294967295 REMOTE_KEEP_ALIVE_ENABLE 0 0 REMOTE_KEEP_ALIVE_CAPABILITY 4 4 ixAZF0ENDPOINT0_AZALIA_F0_AUDIO_ENABLE_STATUS 2 0x6b 1 0 4294967295 AUDIO_ENABLE_STATUS 0 0 ixAZF0ENDPOINT0_AZALIA_F0_AUDIO_ENABLED_INT_STATUS 2 0x6c 3 0 4294967295 AUDIO_ENABLED_FLAG 0 0 AUDIO_ENABLED_MASK 4 4 AUDIO_ENABLED_TYPE 8 8 ixAZF0ENDPOINT0_AZALIA_F0_AUDIO_DISABLED_INT_STATUS 2 0x6d 3 0 4294967295 AUDIO_DISABLED_FLAG 0 0 AUDIO_DISABLED_MASK 4 4 AUDIO_DISABLED_TYPE 8 8 ixAZF0ENDPOINT0_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS 2 0x6e 3 0 4294967295 AUDIO_FORMAT_CHANGED_FLAG 0 0 AUDIO_FORMAT_CHANGED_MASK 4 4 AUDIO_FORMAT_CHANGED_TYPE 8 8 ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 2 0x1 14 0 4294967295 AUDIO_CHANNEL_CAPABILITIES 0 0 INPUT_AMPLIFIER_PRESENT 1 1 OUTPUT_AMPLIFIER_PRESENT 2 2 AMPLIFIER_PARAMETER_OVERRIDE 3 3 FORMAT_OVERRIDE 4 4 STRIPE 5 5 PROCESSING_WIDGET 6 6 UNSOLICITED_RESPONSE_CAPABILITY 7 7 CONNECTION_LIST 8 8 DIGITAL 9 9 POWER_CONTROL 10 10 LR_SWAP 11 11 AUDIO_WIDGET_CAPABILITIES_DELAY 16 19 TYPE 20 23 ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT 2 0x2 6 0 4294967295 NUMBER_OF_CHANNELS 0 3 BITS_PER_SAMPLE 4 6 SAMPLE_BASE_DIVISOR 8 10 SAMPLE_BASE_MULTIPLE 11 13 SAMPLE_BASE_RATE 14 14 STREAM_TYPE 15 15 ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID 2 0x3 2 0 4294967295 CHANNEL_ID 0 3 STREAM_ID 4 7 ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER 2 0x4 10 0 4294967295 DIGEN 0 0 V 1 1 VCFG 2 2 PRE 3 3 COPY 4 4 NON_AUDIO 5 5 PRO 6 6 L 7 7 CC 8 14 KEEPALIVE 23 23 ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS 2 0x5 1 0 4294967295 STREAM_FORMATS 0 31 ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 2 0x6 2 0 4294967295 AUDIO_RATE_CAPABILITIES 0 11 AUDIO_BIT_CAPABILITIES 16 20 ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL 2 0x7 2 0 4294967295 STRIPE_CONTROL 0 1 STRIPE_CAPABILITY 20 22 ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE 2 0x8 1 0 4294967295 RAMP_RATE 0 7 ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING 2 0x9 4 0 4294967295 PRESENTATION_TIME_EMBEDDING_ENABLE 0 0 PRESENTATION_TIME_OFFSET_CHANGED 1 1 CLEAR_GTC_COUNTER_MIN_MAX_DELTA 2 2 PRESENTATION_TIME_EMBEDDING_GROUP 4 6 ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA 2 0xc 1 0 4294967295 GTC_COUNTER_DELTA 0 31 ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN 2 0xd 1 0 4294967295 GTC_COUNTER_DELTA_MIN 0 31 ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX 2 0xe 1 0 4294967295 GTC_COUNTER_DELTA_MAX 0 31 ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 2 0x20 13 0 4294967295 AUDIO_CHANNEL_CAPABILITIES 0 0 INPUT_AMPLIFIER_PRESENT 1 1 OUTPUT_AMPLIFIER_PRESENT 2 2 AMPLIFIER_PARAMETER_OVERRIDE 3 3 STRIPE 5 5 PROCESSING_WIDGET 6 6 UNSOLICITED_RESPONSE_CAPABILITY 7 7 CONNECTION_LIST 8 8 DIGITAL 9 9 POWER_CONTROL 10 10 LR_SWAP 11 11 AUDIO_WIDGET_CAPABILITIES_DELAY 16 19 TYPE 20 23 ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES 2 0x21 11 0 4294967295 IMPEDANCE_SENSE_CAPABLE 0 0 TRIGGER_REQUIRED 1 1 JACK_DETECTION_CAPABILITY 2 2 HEADPHONE_DRIVE_CAPABLE 3 3 OUTPUT_CAPABLE 4 4 INPUT_CAPABLE 5 5 BALANCED_I_O_PINS 6 6 HDMI 7 7 VREF_CONTROL 8 15 EAPD_CAPABLE 16 16 DP 24 24 ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE 2 0x22 2 0 4294967295 TAG 0 5 ENABLE 7 7 ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE 2 0x23 1 0 4294967295 IMPEDANCE_SENSE 0 30 ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL 2 0x24 1 0 4294967295 OUT_ENABLE 6 6 ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER 2 0x25 8 0 4294967295 SPEAKER_ALLOCATION 0 6 CHANNEL_ALLOCATION 8 15 HDMI_CONNECTION 16 16 DP_CONNECTION 17 17 EXTRA_CONNECTION_INFO 18 23 LFE_PLAYBACK_LEVEL 24 25 LEVEL_SHIFT 27 30 DOWN_MIX_INHIBIT 31 31 ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 2 0x28 4 0 4294967295 MAX_CHANNELS 0 2 SUPPORTED_FREQUENCIES 8 15 DESCRIPTOR_BYTE_2 16 23 SUPPORTED_FREQUENCIES_STEREO 24 31 ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 2 0x29 3 0 4294967295 MAX_CHANNELS 0 2 SUPPORTED_FREQUENCIES 8 15 DESCRIPTOR_BYTE_2 16 23 ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 2 0x2a 3 0 4294967295 MAX_CHANNELS 0 2 SUPPORTED_FREQUENCIES 8 15 DESCRIPTOR_BYTE_2 16 23 ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 2 0x2b 3 0 4294967295 MAX_CHANNELS 0 2 SUPPORTED_FREQUENCIES 8 15 DESCRIPTOR_BYTE_2 16 23 ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 2 0x2c 3 0 4294967295 MAX_CHANNELS 0 2 SUPPORTED_FREQUENCIES 8 15 DESCRIPTOR_BYTE_2 16 23 ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 2 0x2d 3 0 4294967295 MAX_CHANNELS 0 2 SUPPORTED_FREQUENCIES 8 15 DESCRIPTOR_BYTE_2 16 23 ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 2 0x2e 3 0 4294967295 MAX_CHANNELS 0 2 SUPPORTED_FREQUENCIES 8 15 DESCRIPTOR_BYTE_2 16 23 ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 2 0x2f 3 0 4294967295 MAX_CHANNELS 0 2 SUPPORTED_FREQUENCIES 8 15 DESCRIPTOR_BYTE_2 16 23 ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 2 0x30 3 0 4294967295 MAX_CHANNELS 0 2 SUPPORTED_FREQUENCIES 8 15 DESCRIPTOR_BYTE_2 16 23 ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 2 0x31 3 0 4294967295 MAX_CHANNELS 0 2 SUPPORTED_FREQUENCIES 8 15 DESCRIPTOR_BYTE_2 16 23 ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 2 0x32 3 0 4294967295 MAX_CHANNELS 0 2 SUPPORTED_FREQUENCIES 8 15 DESCRIPTOR_BYTE_2 16 23 ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 2 0x33 3 0 4294967295 MAX_CHANNELS 0 2 SUPPORTED_FREQUENCIES 8 15 DESCRIPTOR_BYTE_2 16 23 ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 2 0x34 3 0 4294967295 MAX_CHANNELS 0 2 SUPPORTED_FREQUENCIES 8 15 DESCRIPTOR_BYTE_2 16 23 ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 2 0x35 3 0 4294967295 MAX_CHANNELS 0 2 SUPPORTED_FREQUENCIES 8 15 DESCRIPTOR_BYTE_2 16 23 ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE 2 0x36 12 0 4294967295 MULTICHANNEL01_ENABLE 0 0 MULTICHANNEL01_MUTE 1 1 MULTICHANNEL01_CHANNEL_ID 4 7 MULTICHANNEL23_ENABLE 8 8 MULTICHANNEL23_MUTE 9 9 MULTICHANNEL23_CHANNEL_ID 12 15 MULTICHANNEL45_ENABLE 16 16 MULTICHANNEL45_MUTE 17 17 MULTICHANNEL45_CHANNEL_ID 20 23 MULTICHANNEL67_ENABLE 24 24 MULTICHANNEL67_MUTE 25 25 MULTICHANNEL67_CHANNEL_ID 28 31 ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC 2 0x37 2 0 4294967295 VIDEO_LIPSYNC 0 7 AUDIO_LIPSYNC 8 15 ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR 2 0x38 2 0 4294967295 HBR_CAPABLE 0 0 HBR_ENABLE 4 4 ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0 2 0x3a 2 0 4294967295 MANUFACTURER_ID 0 15 PRODUCT_ID 16 31 ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1 2 0x3b 1 0 4294967295 SINK_DESCRIPTION_LEN 0 7 ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2 2 0x3c 1 0 4294967295 PORT_ID0 0 31 ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3 2 0x3d 1 0 4294967295 PORT_ID1 0 31 ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4 2 0x3e 4 0 4294967295 DESCRIPTION0 0 7 DESCRIPTION1 8 15 DESCRIPTION2 16 23 DESCRIPTION3 24 31 ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5 2 0x3f 4 0 4294967295 DESCRIPTION4 0 7 DESCRIPTION5 8 15 DESCRIPTION6 16 23 DESCRIPTION7 24 31 ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6 2 0x40 4 0 4294967295 DESCRIPTION8 0 7 DESCRIPTION9 8 15 DESCRIPTION10 16 23 DESCRIPTION11 24 31 ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7 2 0x41 4 0 4294967295 DESCRIPTION12 0 7 DESCRIPTION13 8 15 DESCRIPTION14 16 23 DESCRIPTION15 24 31 ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8 2 0x42 2 0 4294967295 DESCRIPTION16 0 7 DESCRIPTION17 8 15 ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL 2 0x54 3 0 4294967295 CLOCK_GATING_DISABLE 0 0 CLOCK_ON_STATE 4 4 AUDIO_ENABLED 31 31 ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 2 0x55 2 0 4294967295 UNSOLICITED_RESPONSE_PAYLOAD 0 25 UNSOLICITED_RESPONSE_FORCE 28 28 ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 2 0x56 8 0 4294967295 SEQUENCE 0 3 DEFAULT_ASSOCIATION 4 7 MISC 8 11 COLOR 12 15 CONNECTION_TYPE 16 19 DEFAULT_DEVICE 20 23 LOCATION 24 29 PORT_CONNECTIVITY 30 31 ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2 2 0x57 12 0 4294967295 MULTICHANNEL1_ENABLE 0 0 MULTICHANNEL1_MUTE 1 1 MULTICHANNEL1_CHANNEL_ID 4 7 MULTICHANNEL3_ENABLE 8 8 MULTICHANNEL3_MUTE 9 9 MULTICHANNEL3_CHANNEL_ID 12 15 MULTICHANNEL5_ENABLE 16 16 MULTICHANNEL5_MUTE 17 17 MULTICHANNEL5_CHANNEL_ID 20 23 MULTICHANNEL7_ENABLE 24 24 MULTICHANNEL7_MUTE 25 25 MULTICHANNEL7_CHANNEL_ID 28 31 ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE 2 0x58 1 0 4294967295 MULTICHANNEL_MODE 0 0 ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0 2 0x59 2 0 4294967295 IEC_60958_CS_MODE 0 1 IEC_60958_CS_SOURCE_NUMBER 2 5 ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1 2 0x5a 4 0 4294967295 IEC_60958_CS_CLOCK_ACCURACY 0 1 IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN 2 2 IEC_60958_CS_WORD_LENGTH 3 6 IEC_60958_CS_WORD_LENGTH_OVRRD_EN 7 7 ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2 2 0x5b 2 0 4294967295 IEC_60958_CS_SAMPLING_FREQUENCY 0 5 IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN 6 6 ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3 2 0x5c 2 0 4294967295 IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY 0 3 IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN 4 4 ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4 2 0x5d 4 0 4294967295 IEC_60958_CS_SAMPLING_FREQUENCY_COEFF 0 3 IEC_60958_CS_MPEG_SURROUND_INFO 4 4 IEC_60958_CS_CGMS_A 5 6 IEC_60958_CS_CGMS_A_VALID 7 7 ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5 2 0x5e 2 0 4294967295 IEC_60958_CS_CHANNEL_NUMBER_L 0 3 IEC_60958_CS_CHANNEL_NUMBER_R 4 7 ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6 2 0x5f 2 0 4294967295 IEC_60958_CS_CHANNEL_NUMBER_2 0 3 IEC_60958_CS_CHANNEL_NUMBER_3 4 7 ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7 2 0x60 2 0 4294967295 IEC_60958_CS_CHANNEL_NUMBER_4 0 3 IEC_60958_CS_CHANNEL_NUMBER_5 4 7 ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8 2 0x61 2 0 4294967295 IEC_60958_CS_CHANNEL_NUMBER_6 0 3 IEC_60958_CS_CHANNEL_NUMBER_7 4 7 ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO 2 0x62 1 0 4294967295 ASSOCIATION_INFO 0 31 ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS 2 0x63 1 0 4294967295 OUTPUT_ACTIVE 0 0 ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 2 0x64 2 0 4294967295 LPIB_SNAPSHOT_LOCK 0 0 CYCLIC_BUFFER_WRAP_COUNT 8 15 ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB 2 0x65 1 0 4294967295 LPIB 0 31 ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 2 0x66 1 0 4294967295 LPIB_TIMER_SNAPSHOT 0 31 ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE 2 0x67 1 0 4294967295 CODING_TYPE 0 7 ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED 2 0x68 4 0 4294967295 FORMAT_CHANGED 0 0 FORMAT_CHANGED_ACK_UR_ENABLE 1 1 FORMAT_CHANGE_REASON 8 15 FORMAT_CHANGE_RESPONSE 16 23 ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION 2 0x69 1 0 4294967295 WIRELESS_DISPLAY_IDENTIFICATION 0 1 ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE 2 0x6a 2 0 4294967295 REMOTE_KEEP_ALIVE_ENABLE 0 0 REMOTE_KEEP_ALIVE_CAPABILITY 4 4 ixAZF0ENDPOINT1_AZALIA_F0_AUDIO_ENABLE_STATUS 2 0x6b 1 0 4294967295 AUDIO_ENABLE_STATUS 0 0 ixAZF0ENDPOINT1_AZALIA_F0_AUDIO_ENABLED_INT_STATUS 2 0x6c 3 0 4294967295 AUDIO_ENABLED_FLAG 0 0 AUDIO_ENABLED_MASK 4 4 AUDIO_ENABLED_TYPE 8 8 ixAZF0ENDPOINT1_AZALIA_F0_AUDIO_DISABLED_INT_STATUS 2 0x6d 3 0 4294967295 AUDIO_DISABLED_FLAG 0 0 AUDIO_DISABLED_MASK 4 4 AUDIO_DISABLED_TYPE 8 8 ixAZF0ENDPOINT1_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS 2 0x6e 3 0 4294967295 AUDIO_FORMAT_CHANGED_FLAG 0 0 AUDIO_FORMAT_CHANGED_MASK 4 4 AUDIO_FORMAT_CHANGED_TYPE 8 8 ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 2 0x1 14 0 4294967295 AUDIO_CHANNEL_CAPABILITIES 0 0 INPUT_AMPLIFIER_PRESENT 1 1 OUTPUT_AMPLIFIER_PRESENT 2 2 AMPLIFIER_PARAMETER_OVERRIDE 3 3 FORMAT_OVERRIDE 4 4 STRIPE 5 5 PROCESSING_WIDGET 6 6 UNSOLICITED_RESPONSE_CAPABILITY 7 7 CONNECTION_LIST 8 8 DIGITAL 9 9 POWER_CONTROL 10 10 LR_SWAP 11 11 AUDIO_WIDGET_CAPABILITIES_DELAY 16 19 TYPE 20 23 ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT 2 0x2 6 0 4294967295 NUMBER_OF_CHANNELS 0 3 BITS_PER_SAMPLE 4 6 SAMPLE_BASE_DIVISOR 8 10 SAMPLE_BASE_MULTIPLE 11 13 SAMPLE_BASE_RATE 14 14 STREAM_TYPE 15 15 ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID 2 0x3 2 0 4294967295 CHANNEL_ID 0 3 STREAM_ID 4 7 ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER 2 0x4 10 0 4294967295 DIGEN 0 0 V 1 1 VCFG 2 2 PRE 3 3 COPY 4 4 NON_AUDIO 5 5 PRO 6 6 L 7 7 CC 8 14 KEEPALIVE 23 23 ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS 2 0x5 1 0 4294967295 STREAM_FORMATS 0 31 ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 2 0x6 2 0 4294967295 AUDIO_RATE_CAPABILITIES 0 11 AUDIO_BIT_CAPABILITIES 16 20 ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL 2 0x7 2 0 4294967295 STRIPE_CONTROL 0 1 STRIPE_CAPABILITY 20 22 ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE 2 0x8 1 0 4294967295 RAMP_RATE 0 7 ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING 2 0x9 4 0 4294967295 PRESENTATION_TIME_EMBEDDING_ENABLE 0 0 PRESENTATION_TIME_OFFSET_CHANGED 1 1 CLEAR_GTC_COUNTER_MIN_MAX_DELTA 2 2 PRESENTATION_TIME_EMBEDDING_GROUP 4 6 ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA 2 0xc 1 0 4294967295 GTC_COUNTER_DELTA 0 31 ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN 2 0xd 1 0 4294967295 GTC_COUNTER_DELTA_MIN 0 31 ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX 2 0xe 1 0 4294967295 GTC_COUNTER_DELTA_MAX 0 31 ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 2 0x20 13 0 4294967295 AUDIO_CHANNEL_CAPABILITIES 0 0 INPUT_AMPLIFIER_PRESENT 1 1 OUTPUT_AMPLIFIER_PRESENT 2 2 AMPLIFIER_PARAMETER_OVERRIDE 3 3 STRIPE 5 5 PROCESSING_WIDGET 6 6 UNSOLICITED_RESPONSE_CAPABILITY 7 7 CONNECTION_LIST 8 8 DIGITAL 9 9 POWER_CONTROL 10 10 LR_SWAP 11 11 AUDIO_WIDGET_CAPABILITIES_DELAY 16 19 TYPE 20 23 ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES 2 0x21 11 0 4294967295 IMPEDANCE_SENSE_CAPABLE 0 0 TRIGGER_REQUIRED 1 1 JACK_DETECTION_CAPABILITY 2 2 HEADPHONE_DRIVE_CAPABLE 3 3 OUTPUT_CAPABLE 4 4 INPUT_CAPABLE 5 5 BALANCED_I_O_PINS 6 6 HDMI 7 7 VREF_CONTROL 8 15 EAPD_CAPABLE 16 16 DP 24 24 ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE 2 0x22 2 0 4294967295 TAG 0 5 ENABLE 7 7 ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE 2 0x23 1 0 4294967295 IMPEDANCE_SENSE 0 30 ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL 2 0x24 1 0 4294967295 OUT_ENABLE 6 6 ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER 2 0x25 8 0 4294967295 SPEAKER_ALLOCATION 0 6 CHANNEL_ALLOCATION 8 15 HDMI_CONNECTION 16 16 DP_CONNECTION 17 17 EXTRA_CONNECTION_INFO 18 23 LFE_PLAYBACK_LEVEL 24 25 LEVEL_SHIFT 27 30 DOWN_MIX_INHIBIT 31 31 ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 2 0x28 4 0 4294967295 MAX_CHANNELS 0 2 SUPPORTED_FREQUENCIES 8 15 DESCRIPTOR_BYTE_2 16 23 SUPPORTED_FREQUENCIES_STEREO 24 31 ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 2 0x29 3 0 4294967295 MAX_CHANNELS 0 2 SUPPORTED_FREQUENCIES 8 15 DESCRIPTOR_BYTE_2 16 23 ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 2 0x2a 3 0 4294967295 MAX_CHANNELS 0 2 SUPPORTED_FREQUENCIES 8 15 DESCRIPTOR_BYTE_2 16 23 ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 2 0x2b 3 0 4294967295 MAX_CHANNELS 0 2 SUPPORTED_FREQUENCIES 8 15 DESCRIPTOR_BYTE_2 16 23 ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 2 0x2c 3 0 4294967295 MAX_CHANNELS 0 2 SUPPORTED_FREQUENCIES 8 15 DESCRIPTOR_BYTE_2 16 23 ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 2 0x2d 3 0 4294967295 MAX_CHANNELS 0 2 SUPPORTED_FREQUENCIES 8 15 DESCRIPTOR_BYTE_2 16 23 ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 2 0x2e 3 0 4294967295 MAX_CHANNELS 0 2 SUPPORTED_FREQUENCIES 8 15 DESCRIPTOR_BYTE_2 16 23 ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 2 0x2f 3 0 4294967295 MAX_CHANNELS 0 2 SUPPORTED_FREQUENCIES 8 15 DESCRIPTOR_BYTE_2 16 23 ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 2 0x30 3 0 4294967295 MAX_CHANNELS 0 2 SUPPORTED_FREQUENCIES 8 15 DESCRIPTOR_BYTE_2 16 23 ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 2 0x31 3 0 4294967295 MAX_CHANNELS 0 2 SUPPORTED_FREQUENCIES 8 15 DESCRIPTOR_BYTE_2 16 23 ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 2 0x32 3 0 4294967295 MAX_CHANNELS 0 2 SUPPORTED_FREQUENCIES 8 15 DESCRIPTOR_BYTE_2 16 23 ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 2 0x33 3 0 4294967295 MAX_CHANNELS 0 2 SUPPORTED_FREQUENCIES 8 15 DESCRIPTOR_BYTE_2 16 23 ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 2 0x34 3 0 4294967295 MAX_CHANNELS 0 2 SUPPORTED_FREQUENCIES 8 15 DESCRIPTOR_BYTE_2 16 23 ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 2 0x35 3 0 4294967295 MAX_CHANNELS 0 2 SUPPORTED_FREQUENCIES 8 15 DESCRIPTOR_BYTE_2 16 23 ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE 2 0x36 12 0 4294967295 MULTICHANNEL01_ENABLE 0 0 MULTICHANNEL01_MUTE 1 1 MULTICHANNEL01_CHANNEL_ID 4 7 MULTICHANNEL23_ENABLE 8 8 MULTICHANNEL23_MUTE 9 9 MULTICHANNEL23_CHANNEL_ID 12 15 MULTICHANNEL45_ENABLE 16 16 MULTICHANNEL45_MUTE 17 17 MULTICHANNEL45_CHANNEL_ID 20 23 MULTICHANNEL67_ENABLE 24 24 MULTICHANNEL67_MUTE 25 25 MULTICHANNEL67_CHANNEL_ID 28 31 ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC 2 0x37 2 0 4294967295 VIDEO_LIPSYNC 0 7 AUDIO_LIPSYNC 8 15 ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR 2 0x38 2 0 4294967295 HBR_CAPABLE 0 0 HBR_ENABLE 4 4 ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0 2 0x3a 2 0 4294967295 MANUFACTURER_ID 0 15 PRODUCT_ID 16 31 ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1 2 0x3b 1 0 4294967295 SINK_DESCRIPTION_LEN 0 7 ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2 2 0x3c 1 0 4294967295 PORT_ID0 0 31 ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3 2 0x3d 1 0 4294967295 PORT_ID1 0 31 ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4 2 0x3e 4 0 4294967295 DESCRIPTION0 0 7 DESCRIPTION1 8 15 DESCRIPTION2 16 23 DESCRIPTION3 24 31 ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5 2 0x3f 4 0 4294967295 DESCRIPTION4 0 7 DESCRIPTION5 8 15 DESCRIPTION6 16 23 DESCRIPTION7 24 31 ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6 2 0x40 4 0 4294967295 DESCRIPTION8 0 7 DESCRIPTION9 8 15 DESCRIPTION10 16 23 DESCRIPTION11 24 31 ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7 2 0x41 4 0 4294967295 DESCRIPTION12 0 7 DESCRIPTION13 8 15 DESCRIPTION14 16 23 DESCRIPTION15 24 31 ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8 2 0x42 2 0 4294967295 DESCRIPTION16 0 7 DESCRIPTION17 8 15 ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL 2 0x54 3 0 4294967295 CLOCK_GATING_DISABLE 0 0 CLOCK_ON_STATE 4 4 AUDIO_ENABLED 31 31 ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 2 0x55 2 0 4294967295 UNSOLICITED_RESPONSE_PAYLOAD 0 25 UNSOLICITED_RESPONSE_FORCE 28 28 ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 2 0x56 8 0 4294967295 SEQUENCE 0 3 DEFAULT_ASSOCIATION 4 7 MISC 8 11 COLOR 12 15 CONNECTION_TYPE 16 19 DEFAULT_DEVICE 20 23 LOCATION 24 29 PORT_CONNECTIVITY 30 31 ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2 2 0x57 12 0 4294967295 MULTICHANNEL1_ENABLE 0 0 MULTICHANNEL1_MUTE 1 1 MULTICHANNEL1_CHANNEL_ID 4 7 MULTICHANNEL3_ENABLE 8 8 MULTICHANNEL3_MUTE 9 9 MULTICHANNEL3_CHANNEL_ID 12 15 MULTICHANNEL5_ENABLE 16 16 MULTICHANNEL5_MUTE 17 17 MULTICHANNEL5_CHANNEL_ID 20 23 MULTICHANNEL7_ENABLE 24 24 MULTICHANNEL7_MUTE 25 25 MULTICHANNEL7_CHANNEL_ID 28 31 ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE 2 0x58 1 0 4294967295 MULTICHANNEL_MODE 0 0 ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0 2 0x59 2 0 4294967295 IEC_60958_CS_MODE 0 1 IEC_60958_CS_SOURCE_NUMBER 2 5 ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1 2 0x5a 4 0 4294967295 IEC_60958_CS_CLOCK_ACCURACY 0 1 IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN 2 2 IEC_60958_CS_WORD_LENGTH 3 6 IEC_60958_CS_WORD_LENGTH_OVRRD_EN 7 7 ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2 2 0x5b 2 0 4294967295 IEC_60958_CS_SAMPLING_FREQUENCY 0 5 IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN 6 6 ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3 2 0x5c 2 0 4294967295 IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY 0 3 IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN 4 4 ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4 2 0x5d 4 0 4294967295 IEC_60958_CS_SAMPLING_FREQUENCY_COEFF 0 3 IEC_60958_CS_MPEG_SURROUND_INFO 4 4 IEC_60958_CS_CGMS_A 5 6 IEC_60958_CS_CGMS_A_VALID 7 7 ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5 2 0x5e 2 0 4294967295 IEC_60958_CS_CHANNEL_NUMBER_L 0 3 IEC_60958_CS_CHANNEL_NUMBER_R 4 7 ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6 2 0x5f 2 0 4294967295 IEC_60958_CS_CHANNEL_NUMBER_2 0 3 IEC_60958_CS_CHANNEL_NUMBER_3 4 7 ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7 2 0x60 2 0 4294967295 IEC_60958_CS_CHANNEL_NUMBER_4 0 3 IEC_60958_CS_CHANNEL_NUMBER_5 4 7 ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8 2 0x61 2 0 4294967295 IEC_60958_CS_CHANNEL_NUMBER_6 0 3 IEC_60958_CS_CHANNEL_NUMBER_7 4 7 ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO 2 0x62 1 0 4294967295 ASSOCIATION_INFO 0 31 ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS 2 0x63 1 0 4294967295 OUTPUT_ACTIVE 0 0 ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 2 0x64 2 0 4294967295 LPIB_SNAPSHOT_LOCK 0 0 CYCLIC_BUFFER_WRAP_COUNT 8 15 ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB 2 0x65 1 0 4294967295 LPIB 0 31 ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 2 0x66 1 0 4294967295 LPIB_TIMER_SNAPSHOT 0 31 ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE 2 0x67 1 0 4294967295 CODING_TYPE 0 7 ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED 2 0x68 4 0 4294967295 FORMAT_CHANGED 0 0 FORMAT_CHANGED_ACK_UR_ENABLE 1 1 FORMAT_CHANGE_REASON 8 15 FORMAT_CHANGE_RESPONSE 16 23 ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION 2 0x69 1 0 4294967295 WIRELESS_DISPLAY_IDENTIFICATION 0 1 ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE 2 0x6a 2 0 4294967295 REMOTE_KEEP_ALIVE_ENABLE 0 0 REMOTE_KEEP_ALIVE_CAPABILITY 4 4 ixAZF0ENDPOINT2_AZALIA_F0_AUDIO_ENABLE_STATUS 2 0x6b 1 0 4294967295 AUDIO_ENABLE_STATUS 0 0 ixAZF0ENDPOINT2_AZALIA_F0_AUDIO_ENABLED_INT_STATUS 2 0x6c 3 0 4294967295 AUDIO_ENABLED_FLAG 0 0 AUDIO_ENABLED_MASK 4 4 AUDIO_ENABLED_TYPE 8 8 ixAZF0ENDPOINT2_AZALIA_F0_AUDIO_DISABLED_INT_STATUS 2 0x6d 3 0 4294967295 AUDIO_DISABLED_FLAG 0 0 AUDIO_DISABLED_MASK 4 4 AUDIO_DISABLED_TYPE 8 8 ixAZF0ENDPOINT2_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS 2 0x6e 3 0 4294967295 AUDIO_FORMAT_CHANGED_FLAG 0 0 AUDIO_FORMAT_CHANGED_MASK 4 4 AUDIO_FORMAT_CHANGED_TYPE 8 8 ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 2 0x1 14 0 4294967295 AUDIO_CHANNEL_CAPABILITIES 0 0 INPUT_AMPLIFIER_PRESENT 1 1 OUTPUT_AMPLIFIER_PRESENT 2 2 AMPLIFIER_PARAMETER_OVERRIDE 3 3 FORMAT_OVERRIDE 4 4 STRIPE 5 5 PROCESSING_WIDGET 6 6 UNSOLICITED_RESPONSE_CAPABILITY 7 7 CONNECTION_LIST 8 8 DIGITAL 9 9 POWER_CONTROL 10 10 LR_SWAP 11 11 AUDIO_WIDGET_CAPABILITIES_DELAY 16 19 TYPE 20 23 ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT 2 0x2 6 0 4294967295 NUMBER_OF_CHANNELS 0 3 BITS_PER_SAMPLE 4 6 SAMPLE_BASE_DIVISOR 8 10 SAMPLE_BASE_MULTIPLE 11 13 SAMPLE_BASE_RATE 14 14 STREAM_TYPE 15 15 ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID 2 0x3 2 0 4294967295 CHANNEL_ID 0 3 STREAM_ID 4 7 ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER 2 0x4 10 0 4294967295 DIGEN 0 0 V 1 1 VCFG 2 2 PRE 3 3 COPY 4 4 NON_AUDIO 5 5 PRO 6 6 L 7 7 CC 8 14 KEEPALIVE 23 23 ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS 2 0x5 1 0 4294967295 STREAM_FORMATS 0 31 ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 2 0x6 2 0 4294967295 AUDIO_RATE_CAPABILITIES 0 11 AUDIO_BIT_CAPABILITIES 16 20 ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL 2 0x7 2 0 4294967295 STRIPE_CONTROL 0 1 STRIPE_CAPABILITY 20 22 ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE 2 0x8 1 0 4294967295 RAMP_RATE 0 7 ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING 2 0x9 4 0 4294967295 PRESENTATION_TIME_EMBEDDING_ENABLE 0 0 PRESENTATION_TIME_OFFSET_CHANGED 1 1 CLEAR_GTC_COUNTER_MIN_MAX_DELTA 2 2 PRESENTATION_TIME_EMBEDDING_GROUP 4 6 ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA 2 0xc 1 0 4294967295 GTC_COUNTER_DELTA 0 31 ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN 2 0xd 1 0 4294967295 GTC_COUNTER_DELTA_MIN 0 31 ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX 2 0xe 1 0 4294967295 GTC_COUNTER_DELTA_MAX 0 31 ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 2 0x20 13 0 4294967295 AUDIO_CHANNEL_CAPABILITIES 0 0 INPUT_AMPLIFIER_PRESENT 1 1 OUTPUT_AMPLIFIER_PRESENT 2 2 AMPLIFIER_PARAMETER_OVERRIDE 3 3 STRIPE 5 5 PROCESSING_WIDGET 6 6 UNSOLICITED_RESPONSE_CAPABILITY 7 7 CONNECTION_LIST 8 8 DIGITAL 9 9 POWER_CONTROL 10 10 LR_SWAP 11 11 AUDIO_WIDGET_CAPABILITIES_DELAY 16 19 TYPE 20 23 ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES 2 0x21 11 0 4294967295 IMPEDANCE_SENSE_CAPABLE 0 0 TRIGGER_REQUIRED 1 1 JACK_DETECTION_CAPABILITY 2 2 HEADPHONE_DRIVE_CAPABLE 3 3 OUTPUT_CAPABLE 4 4 INPUT_CAPABLE 5 5 BALANCED_I_O_PINS 6 6 HDMI 7 7 VREF_CONTROL 8 15 EAPD_CAPABLE 16 16 DP 24 24 ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE 2 0x22 2 0 4294967295 TAG 0 5 ENABLE 7 7 ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE 2 0x23 1 0 4294967295 IMPEDANCE_SENSE 0 30 ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL 2 0x24 1 0 4294967295 OUT_ENABLE 6 6 ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER 2 0x25 8 0 4294967295 SPEAKER_ALLOCATION 0 6 CHANNEL_ALLOCATION 8 15 HDMI_CONNECTION 16 16 DP_CONNECTION 17 17 EXTRA_CONNECTION_INFO 18 23 LFE_PLAYBACK_LEVEL 24 25 LEVEL_SHIFT 27 30 DOWN_MIX_INHIBIT 31 31 ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 2 0x28 4 0 4294967295 MAX_CHANNELS 0 2 SUPPORTED_FREQUENCIES 8 15 DESCRIPTOR_BYTE_2 16 23 SUPPORTED_FREQUENCIES_STEREO 24 31 ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 2 0x29 3 0 4294967295 MAX_CHANNELS 0 2 SUPPORTED_FREQUENCIES 8 15 DESCRIPTOR_BYTE_2 16 23 ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 2 0x2a 3 0 4294967295 MAX_CHANNELS 0 2 SUPPORTED_FREQUENCIES 8 15 DESCRIPTOR_BYTE_2 16 23 ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 2 0x2b 3 0 4294967295 MAX_CHANNELS 0 2 SUPPORTED_FREQUENCIES 8 15 DESCRIPTOR_BYTE_2 16 23 ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 2 0x2c 3 0 4294967295 MAX_CHANNELS 0 2 SUPPORTED_FREQUENCIES 8 15 DESCRIPTOR_BYTE_2 16 23 ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 2 0x2d 3 0 4294967295 MAX_CHANNELS 0 2 SUPPORTED_FREQUENCIES 8 15 DESCRIPTOR_BYTE_2 16 23 ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 2 0x2e 3 0 4294967295 MAX_CHANNELS 0 2 SUPPORTED_FREQUENCIES 8 15 DESCRIPTOR_BYTE_2 16 23 ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 2 0x2f 3 0 4294967295 MAX_CHANNELS 0 2 SUPPORTED_FREQUENCIES 8 15 DESCRIPTOR_BYTE_2 16 23 ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 2 0x30 3 0 4294967295 MAX_CHANNELS 0 2 SUPPORTED_FREQUENCIES 8 15 DESCRIPTOR_BYTE_2 16 23 ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 2 0x31 3 0 4294967295 MAX_CHANNELS 0 2 SUPPORTED_FREQUENCIES 8 15 DESCRIPTOR_BYTE_2 16 23 ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 2 0x32 3 0 4294967295 MAX_CHANNELS 0 2 SUPPORTED_FREQUENCIES 8 15 DESCRIPTOR_BYTE_2 16 23 ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 2 0x33 3 0 4294967295 MAX_CHANNELS 0 2 SUPPORTED_FREQUENCIES 8 15 DESCRIPTOR_BYTE_2 16 23 ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 2 0x34 3 0 4294967295 MAX_CHANNELS 0 2 SUPPORTED_FREQUENCIES 8 15 DESCRIPTOR_BYTE_2 16 23 ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 2 0x35 3 0 4294967295 MAX_CHANNELS 0 2 SUPPORTED_FREQUENCIES 8 15 DESCRIPTOR_BYTE_2 16 23 ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE 2 0x36 12 0 4294967295 MULTICHANNEL01_ENABLE 0 0 MULTICHANNEL01_MUTE 1 1 MULTICHANNEL01_CHANNEL_ID 4 7 MULTICHANNEL23_ENABLE 8 8 MULTICHANNEL23_MUTE 9 9 MULTICHANNEL23_CHANNEL_ID 12 15 MULTICHANNEL45_ENABLE 16 16 MULTICHANNEL45_MUTE 17 17 MULTICHANNEL45_CHANNEL_ID 20 23 MULTICHANNEL67_ENABLE 24 24 MULTICHANNEL67_MUTE 25 25 MULTICHANNEL67_CHANNEL_ID 28 31 ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC 2 0x37 2 0 4294967295 VIDEO_LIPSYNC 0 7 AUDIO_LIPSYNC 8 15 ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR 2 0x38 2 0 4294967295 HBR_CAPABLE 0 0 HBR_ENABLE 4 4 ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0 2 0x3a 2 0 4294967295 MANUFACTURER_ID 0 15 PRODUCT_ID 16 31 ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1 2 0x3b 1 0 4294967295 SINK_DESCRIPTION_LEN 0 7 ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2 2 0x3c 1 0 4294967295 PORT_ID0 0 31 ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3 2 0x3d 1 0 4294967295 PORT_ID1 0 31 ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4 2 0x3e 4 0 4294967295 DESCRIPTION0 0 7 DESCRIPTION1 8 15 DESCRIPTION2 16 23 DESCRIPTION3 24 31 ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5 2 0x3f 4 0 4294967295 DESCRIPTION4 0 7 DESCRIPTION5 8 15 DESCRIPTION6 16 23 DESCRIPTION7 24 31 ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6 2 0x40 4 0 4294967295 DESCRIPTION8 0 7 DESCRIPTION9 8 15 DESCRIPTION10 16 23 DESCRIPTION11 24 31 ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7 2 0x41 4 0 4294967295 DESCRIPTION12 0 7 DESCRIPTION13 8 15 DESCRIPTION14 16 23 DESCRIPTION15 24 31 ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8 2 0x42 2 0 4294967295 DESCRIPTION16 0 7 DESCRIPTION17 8 15 ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL 2 0x54 3 0 4294967295 CLOCK_GATING_DISABLE 0 0 CLOCK_ON_STATE 4 4 AUDIO_ENABLED 31 31 ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 2 0x55 2 0 4294967295 UNSOLICITED_RESPONSE_PAYLOAD 0 25 UNSOLICITED_RESPONSE_FORCE 28 28 ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 2 0x56 8 0 4294967295 SEQUENCE 0 3 DEFAULT_ASSOCIATION 4 7 MISC 8 11 COLOR 12 15 CONNECTION_TYPE 16 19 DEFAULT_DEVICE 20 23 LOCATION 24 29 PORT_CONNECTIVITY 30 31 ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2 2 0x57 12 0 4294967295 MULTICHANNEL1_ENABLE 0 0 MULTICHANNEL1_MUTE 1 1 MULTICHANNEL1_CHANNEL_ID 4 7 MULTICHANNEL3_ENABLE 8 8 MULTICHANNEL3_MUTE 9 9 MULTICHANNEL3_CHANNEL_ID 12 15 MULTICHANNEL5_ENABLE 16 16 MULTICHANNEL5_MUTE 17 17 MULTICHANNEL5_CHANNEL_ID 20 23 MULTICHANNEL7_ENABLE 24 24 MULTICHANNEL7_MUTE 25 25 MULTICHANNEL7_CHANNEL_ID 28 31 ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE 2 0x58 1 0 4294967295 MULTICHANNEL_MODE 0 0 ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0 2 0x59 2 0 4294967295 IEC_60958_CS_MODE 0 1 IEC_60958_CS_SOURCE_NUMBER 2 5 ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1 2 0x5a 4 0 4294967295 IEC_60958_CS_CLOCK_ACCURACY 0 1 IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN 2 2 IEC_60958_CS_WORD_LENGTH 3 6 IEC_60958_CS_WORD_LENGTH_OVRRD_EN 7 7 ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2 2 0x5b 2 0 4294967295 IEC_60958_CS_SAMPLING_FREQUENCY 0 5 IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN 6 6 ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3 2 0x5c 2 0 4294967295 IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY 0 3 IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN 4 4 ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4 2 0x5d 4 0 4294967295 IEC_60958_CS_SAMPLING_FREQUENCY_COEFF 0 3 IEC_60958_CS_MPEG_SURROUND_INFO 4 4 IEC_60958_CS_CGMS_A 5 6 IEC_60958_CS_CGMS_A_VALID 7 7 ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5 2 0x5e 2 0 4294967295 IEC_60958_CS_CHANNEL_NUMBER_L 0 3 IEC_60958_CS_CHANNEL_NUMBER_R 4 7 ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6 2 0x5f 2 0 4294967295 IEC_60958_CS_CHANNEL_NUMBER_2 0 3 IEC_60958_CS_CHANNEL_NUMBER_3 4 7 ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7 2 0x60 2 0 4294967295 IEC_60958_CS_CHANNEL_NUMBER_4 0 3 IEC_60958_CS_CHANNEL_NUMBER_5 4 7 ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8 2 0x61 2 0 4294967295 IEC_60958_CS_CHANNEL_NUMBER_6 0 3 IEC_60958_CS_CHANNEL_NUMBER_7 4 7 ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO 2 0x62 1 0 4294967295 ASSOCIATION_INFO 0 31 ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS 2 0x63 1 0 4294967295 OUTPUT_ACTIVE 0 0 ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 2 0x64 2 0 4294967295 LPIB_SNAPSHOT_LOCK 0 0 CYCLIC_BUFFER_WRAP_COUNT 8 15 ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB 2 0x65 1 0 4294967295 LPIB 0 31 ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 2 0x66 1 0 4294967295 LPIB_TIMER_SNAPSHOT 0 31 ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE 2 0x67 1 0 4294967295 CODING_TYPE 0 7 ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED 2 0x68 4 0 4294967295 FORMAT_CHANGED 0 0 FORMAT_CHANGED_ACK_UR_ENABLE 1 1 FORMAT_CHANGE_REASON 8 15 FORMAT_CHANGE_RESPONSE 16 23 ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION 2 0x69 1 0 4294967295 WIRELESS_DISPLAY_IDENTIFICATION 0 1 ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE 2 0x6a 2 0 4294967295 REMOTE_KEEP_ALIVE_ENABLE 0 0 REMOTE_KEEP_ALIVE_CAPABILITY 4 4 ixAZF0ENDPOINT3_AZALIA_F0_AUDIO_ENABLE_STATUS 2 0x6b 1 0 4294967295 AUDIO_ENABLE_STATUS 0 0 ixAZF0ENDPOINT3_AZALIA_F0_AUDIO_ENABLED_INT_STATUS 2 0x6c 3 0 4294967295 AUDIO_ENABLED_FLAG 0 0 AUDIO_ENABLED_MASK 4 4 AUDIO_ENABLED_TYPE 8 8 ixAZF0ENDPOINT3_AZALIA_F0_AUDIO_DISABLED_INT_STATUS 2 0x6d 3 0 4294967295 AUDIO_DISABLED_FLAG 0 0 AUDIO_DISABLED_MASK 4 4 AUDIO_DISABLED_TYPE 8 8 ixAZF0ENDPOINT3_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS 2 0x6e 3 0 4294967295 AUDIO_FORMAT_CHANGED_FLAG 0 0 AUDIO_FORMAT_CHANGED_MASK 4 4 AUDIO_FORMAT_CHANGED_TYPE 8 8 ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 2 0x1 14 0 4294967295 AUDIO_CHANNEL_CAPABILITIES 0 0 INPUT_AMPLIFIER_PRESENT 1 1 OUTPUT_AMPLIFIER_PRESENT 2 2 AMPLIFIER_PARAMETER_OVERRIDE 3 3 FORMAT_OVERRIDE 4 4 STRIPE 5 5 PROCESSING_WIDGET 6 6 UNSOLICITED_RESPONSE_CAPABILITY 7 7 CONNECTION_LIST 8 8 DIGITAL 9 9 POWER_CONTROL 10 10 LR_SWAP 11 11 AUDIO_WIDGET_CAPABILITIES_DELAY 16 19 TYPE 20 23 ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT 2 0x2 6 0 4294967295 NUMBER_OF_CHANNELS 0 3 BITS_PER_SAMPLE 4 6 SAMPLE_BASE_DIVISOR 8 10 SAMPLE_BASE_MULTIPLE 11 13 SAMPLE_BASE_RATE 14 14 STREAM_TYPE 15 15 ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID 2 0x3 2 0 4294967295 CHANNEL_ID 0 3 STREAM_ID 4 7 ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER 2 0x4 10 0 4294967295 DIGEN 0 0 V 1 1 VCFG 2 2 PRE 3 3 COPY 4 4 NON_AUDIO 5 5 PRO 6 6 L 7 7 CC 8 14 KEEPALIVE 23 23 ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS 2 0x5 1 0 4294967295 STREAM_FORMATS 0 31 ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 2 0x6 2 0 4294967295 AUDIO_RATE_CAPABILITIES 0 11 AUDIO_BIT_CAPABILITIES 16 20 ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL 2 0x7 2 0 4294967295 STRIPE_CONTROL 0 1 STRIPE_CAPABILITY 20 22 ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE 2 0x8 1 0 4294967295 RAMP_RATE 0 7 ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING 2 0x9 4 0 4294967295 PRESENTATION_TIME_EMBEDDING_ENABLE 0 0 PRESENTATION_TIME_OFFSET_CHANGED 1 1 CLEAR_GTC_COUNTER_MIN_MAX_DELTA 2 2 PRESENTATION_TIME_EMBEDDING_GROUP 4 6 ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA 2 0xc 1 0 4294967295 GTC_COUNTER_DELTA 0 31 ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN 2 0xd 1 0 4294967295 GTC_COUNTER_DELTA_MIN 0 31 ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX 2 0xe 1 0 4294967295 GTC_COUNTER_DELTA_MAX 0 31 ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 2 0x20 13 0 4294967295 AUDIO_CHANNEL_CAPABILITIES 0 0 INPUT_AMPLIFIER_PRESENT 1 1 OUTPUT_AMPLIFIER_PRESENT 2 2 AMPLIFIER_PARAMETER_OVERRIDE 3 3 STRIPE 5 5 PROCESSING_WIDGET 6 6 UNSOLICITED_RESPONSE_CAPABILITY 7 7 CONNECTION_LIST 8 8 DIGITAL 9 9 POWER_CONTROL 10 10 LR_SWAP 11 11 AUDIO_WIDGET_CAPABILITIES_DELAY 16 19 TYPE 20 23 ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES 2 0x21 11 0 4294967295 IMPEDANCE_SENSE_CAPABLE 0 0 TRIGGER_REQUIRED 1 1 JACK_DETECTION_CAPABILITY 2 2 HEADPHONE_DRIVE_CAPABLE 3 3 OUTPUT_CAPABLE 4 4 INPUT_CAPABLE 5 5 BALANCED_I_O_PINS 6 6 HDMI 7 7 VREF_CONTROL 8 15 EAPD_CAPABLE 16 16 DP 24 24 ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE 2 0x22 2 0 4294967295 TAG 0 5 ENABLE 7 7 ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE 2 0x23 1 0 4294967295 IMPEDANCE_SENSE 0 30 ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL 2 0x24 1 0 4294967295 OUT_ENABLE 6 6 ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER 2 0x25 8 0 4294967295 SPEAKER_ALLOCATION 0 6 CHANNEL_ALLOCATION 8 15 HDMI_CONNECTION 16 16 DP_CONNECTION 17 17 EXTRA_CONNECTION_INFO 18 23 LFE_PLAYBACK_LEVEL 24 25 LEVEL_SHIFT 27 30 DOWN_MIX_INHIBIT 31 31 ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 2 0x28 4 0 4294967295 MAX_CHANNELS 0 2 SUPPORTED_FREQUENCIES 8 15 DESCRIPTOR_BYTE_2 16 23 SUPPORTED_FREQUENCIES_STEREO 24 31 ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 2 0x29 3 0 4294967295 MAX_CHANNELS 0 2 SUPPORTED_FREQUENCIES 8 15 DESCRIPTOR_BYTE_2 16 23 ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 2 0x2a 3 0 4294967295 MAX_CHANNELS 0 2 SUPPORTED_FREQUENCIES 8 15 DESCRIPTOR_BYTE_2 16 23 ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 2 0x2b 3 0 4294967295 MAX_CHANNELS 0 2 SUPPORTED_FREQUENCIES 8 15 DESCRIPTOR_BYTE_2 16 23 ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 2 0x2c 3 0 4294967295 MAX_CHANNELS 0 2 SUPPORTED_FREQUENCIES 8 15 DESCRIPTOR_BYTE_2 16 23 ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 2 0x2d 3 0 4294967295 MAX_CHANNELS 0 2 SUPPORTED_FREQUENCIES 8 15 DESCRIPTOR_BYTE_2 16 23 ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 2 0x2e 3 0 4294967295 MAX_CHANNELS 0 2 SUPPORTED_FREQUENCIES 8 15 DESCRIPTOR_BYTE_2 16 23 ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 2 0x2f 3 0 4294967295 MAX_CHANNELS 0 2 SUPPORTED_FREQUENCIES 8 15 DESCRIPTOR_BYTE_2 16 23 ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 2 0x30 3 0 4294967295 MAX_CHANNELS 0 2 SUPPORTED_FREQUENCIES 8 15 DESCRIPTOR_BYTE_2 16 23 ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 2 0x31 3 0 4294967295 MAX_CHANNELS 0 2 SUPPORTED_FREQUENCIES 8 15 DESCRIPTOR_BYTE_2 16 23 ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 2 0x32 3 0 4294967295 MAX_CHANNELS 0 2 SUPPORTED_FREQUENCIES 8 15 DESCRIPTOR_BYTE_2 16 23 ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 2 0x33 3 0 4294967295 MAX_CHANNELS 0 2 SUPPORTED_FREQUENCIES 8 15 DESCRIPTOR_BYTE_2 16 23 ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 2 0x34 3 0 4294967295 MAX_CHANNELS 0 2 SUPPORTED_FREQUENCIES 8 15 DESCRIPTOR_BYTE_2 16 23 ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 2 0x35 3 0 4294967295 MAX_CHANNELS 0 2 SUPPORTED_FREQUENCIES 8 15 DESCRIPTOR_BYTE_2 16 23 ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE 2 0x36 12 0 4294967295 MULTICHANNEL01_ENABLE 0 0 MULTICHANNEL01_MUTE 1 1 MULTICHANNEL01_CHANNEL_ID 4 7 MULTICHANNEL23_ENABLE 8 8 MULTICHANNEL23_MUTE 9 9 MULTICHANNEL23_CHANNEL_ID 12 15 MULTICHANNEL45_ENABLE 16 16 MULTICHANNEL45_MUTE 17 17 MULTICHANNEL45_CHANNEL_ID 20 23 MULTICHANNEL67_ENABLE 24 24 MULTICHANNEL67_MUTE 25 25 MULTICHANNEL67_CHANNEL_ID 28 31 ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC 2 0x37 2 0 4294967295 VIDEO_LIPSYNC 0 7 AUDIO_LIPSYNC 8 15 ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR 2 0x38 2 0 4294967295 HBR_CAPABLE 0 0 HBR_ENABLE 4 4 ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0 2 0x3a 2 0 4294967295 MANUFACTURER_ID 0 15 PRODUCT_ID 16 31 ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1 2 0x3b 1 0 4294967295 SINK_DESCRIPTION_LEN 0 7 ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2 2 0x3c 1 0 4294967295 PORT_ID0 0 31 ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3 2 0x3d 1 0 4294967295 PORT_ID1 0 31 ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4 2 0x3e 4 0 4294967295 DESCRIPTION0 0 7 DESCRIPTION1 8 15 DESCRIPTION2 16 23 DESCRIPTION3 24 31 ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5 2 0x3f 4 0 4294967295 DESCRIPTION4 0 7 DESCRIPTION5 8 15 DESCRIPTION6 16 23 DESCRIPTION7 24 31 ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6 2 0x40 4 0 4294967295 DESCRIPTION8 0 7 DESCRIPTION9 8 15 DESCRIPTION10 16 23 DESCRIPTION11 24 31 ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7 2 0x41 4 0 4294967295 DESCRIPTION12 0 7 DESCRIPTION13 8 15 DESCRIPTION14 16 23 DESCRIPTION15 24 31 ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8 2 0x42 2 0 4294967295 DESCRIPTION16 0 7 DESCRIPTION17 8 15 ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL 2 0x54 3 0 4294967295 CLOCK_GATING_DISABLE 0 0 CLOCK_ON_STATE 4 4 AUDIO_ENABLED 31 31 ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 2 0x55 2 0 4294967295 UNSOLICITED_RESPONSE_PAYLOAD 0 25 UNSOLICITED_RESPONSE_FORCE 28 28 ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 2 0x56 8 0 4294967295 SEQUENCE 0 3 DEFAULT_ASSOCIATION 4 7 MISC 8 11 COLOR 12 15 CONNECTION_TYPE 16 19 DEFAULT_DEVICE 20 23 LOCATION 24 29 PORT_CONNECTIVITY 30 31 ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2 2 0x57 12 0 4294967295 MULTICHANNEL1_ENABLE 0 0 MULTICHANNEL1_MUTE 1 1 MULTICHANNEL1_CHANNEL_ID 4 7 MULTICHANNEL3_ENABLE 8 8 MULTICHANNEL3_MUTE 9 9 MULTICHANNEL3_CHANNEL_ID 12 15 MULTICHANNEL5_ENABLE 16 16 MULTICHANNEL5_MUTE 17 17 MULTICHANNEL5_CHANNEL_ID 20 23 MULTICHANNEL7_ENABLE 24 24 MULTICHANNEL7_MUTE 25 25 MULTICHANNEL7_CHANNEL_ID 28 31 ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE 2 0x58 1 0 4294967295 MULTICHANNEL_MODE 0 0 ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0 2 0x59 2 0 4294967295 IEC_60958_CS_MODE 0 1 IEC_60958_CS_SOURCE_NUMBER 2 5 ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1 2 0x5a 4 0 4294967295 IEC_60958_CS_CLOCK_ACCURACY 0 1 IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN 2 2 IEC_60958_CS_WORD_LENGTH 3 6 IEC_60958_CS_WORD_LENGTH_OVRRD_EN 7 7 ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2 2 0x5b 2 0 4294967295 IEC_60958_CS_SAMPLING_FREQUENCY 0 5 IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN 6 6 ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3 2 0x5c 2 0 4294967295 IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY 0 3 IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN 4 4 ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4 2 0x5d 4 0 4294967295 IEC_60958_CS_SAMPLING_FREQUENCY_COEFF 0 3 IEC_60958_CS_MPEG_SURROUND_INFO 4 4 IEC_60958_CS_CGMS_A 5 6 IEC_60958_CS_CGMS_A_VALID 7 7 ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5 2 0x5e 2 0 4294967295 IEC_60958_CS_CHANNEL_NUMBER_L 0 3 IEC_60958_CS_CHANNEL_NUMBER_R 4 7 ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6 2 0x5f 2 0 4294967295 IEC_60958_CS_CHANNEL_NUMBER_2 0 3 IEC_60958_CS_CHANNEL_NUMBER_3 4 7 ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7 2 0x60 2 0 4294967295 IEC_60958_CS_CHANNEL_NUMBER_4 0 3 IEC_60958_CS_CHANNEL_NUMBER_5 4 7 ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8 2 0x61 2 0 4294967295 IEC_60958_CS_CHANNEL_NUMBER_6 0 3 IEC_60958_CS_CHANNEL_NUMBER_7 4 7 ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO 2 0x62 1 0 4294967295 ASSOCIATION_INFO 0 31 ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS 2 0x63 1 0 4294967295 OUTPUT_ACTIVE 0 0 ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 2 0x64 2 0 4294967295 LPIB_SNAPSHOT_LOCK 0 0 CYCLIC_BUFFER_WRAP_COUNT 8 15 ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB 2 0x65 1 0 4294967295 LPIB 0 31 ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 2 0x66 1 0 4294967295 LPIB_TIMER_SNAPSHOT 0 31 ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE 2 0x67 1 0 4294967295 CODING_TYPE 0 7 ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED 2 0x68 4 0 4294967295 FORMAT_CHANGED 0 0 FORMAT_CHANGED_ACK_UR_ENABLE 1 1 FORMAT_CHANGE_REASON 8 15 FORMAT_CHANGE_RESPONSE 16 23 ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION 2 0x69 1 0 4294967295 WIRELESS_DISPLAY_IDENTIFICATION 0 1 ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE 2 0x6a 2 0 4294967295 REMOTE_KEEP_ALIVE_ENABLE 0 0 REMOTE_KEEP_ALIVE_CAPABILITY 4 4 ixAZF0ENDPOINT4_AZALIA_F0_AUDIO_ENABLE_STATUS 2 0x6b 1 0 4294967295 AUDIO_ENABLE_STATUS 0 0 ixAZF0ENDPOINT4_AZALIA_F0_AUDIO_ENABLED_INT_STATUS 2 0x6c 3 0 4294967295 AUDIO_ENABLED_FLAG 0 0 AUDIO_ENABLED_MASK 4 4 AUDIO_ENABLED_TYPE 8 8 ixAZF0ENDPOINT4_AZALIA_F0_AUDIO_DISABLED_INT_STATUS 2 0x6d 3 0 4294967295 AUDIO_DISABLED_FLAG 0 0 AUDIO_DISABLED_MASK 4 4 AUDIO_DISABLED_TYPE 8 8 ixAZF0ENDPOINT4_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS 2 0x6e 3 0 4294967295 AUDIO_FORMAT_CHANGED_FLAG 0 0 AUDIO_FORMAT_CHANGED_MASK 4 4 AUDIO_FORMAT_CHANGED_TYPE 8 8 ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 2 0x1 14 0 4294967295 AUDIO_CHANNEL_CAPABILITIES 0 0 INPUT_AMPLIFIER_PRESENT 1 1 OUTPUT_AMPLIFIER_PRESENT 2 2 AMPLIFIER_PARAMETER_OVERRIDE 3 3 FORMAT_OVERRIDE 4 4 STRIPE 5 5 PROCESSING_WIDGET 6 6 UNSOLICITED_RESPONSE_CAPABILITY 7 7 CONNECTION_LIST 8 8 DIGITAL 9 9 POWER_CONTROL 10 10 LR_SWAP 11 11 AUDIO_WIDGET_CAPABILITIES_DELAY 16 19 TYPE 20 23 ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT 2 0x2 6 0 4294967295 NUMBER_OF_CHANNELS 0 3 BITS_PER_SAMPLE 4 6 SAMPLE_BASE_DIVISOR 8 10 SAMPLE_BASE_MULTIPLE 11 13 SAMPLE_BASE_RATE 14 14 STREAM_TYPE 15 15 ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID 2 0x3 2 0 4294967295 CHANNEL_ID 0 3 STREAM_ID 4 7 ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER 2 0x4 10 0 4294967295 DIGEN 0 0 V 1 1 VCFG 2 2 PRE 3 3 COPY 4 4 NON_AUDIO 5 5 PRO 6 6 L 7 7 CC 8 14 KEEPALIVE 23 23 ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS 2 0x5 1 0 4294967295 STREAM_FORMATS 0 31 ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 2 0x6 2 0 4294967295 AUDIO_RATE_CAPABILITIES 0 11 AUDIO_BIT_CAPABILITIES 16 20 ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL 2 0x7 2 0 4294967295 STRIPE_CONTROL 0 1 STRIPE_CAPABILITY 20 22 ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE 2 0x8 1 0 4294967295 RAMP_RATE 0 7 ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING 2 0x9 4 0 4294967295 PRESENTATION_TIME_EMBEDDING_ENABLE 0 0 PRESENTATION_TIME_OFFSET_CHANGED 1 1 CLEAR_GTC_COUNTER_MIN_MAX_DELTA 2 2 PRESENTATION_TIME_EMBEDDING_GROUP 4 6 ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA 2 0xc 1 0 4294967295 GTC_COUNTER_DELTA 0 31 ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN 2 0xd 1 0 4294967295 GTC_COUNTER_DELTA_MIN 0 31 ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX 2 0xe 1 0 4294967295 GTC_COUNTER_DELTA_MAX 0 31 ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 2 0x20 13 0 4294967295 AUDIO_CHANNEL_CAPABILITIES 0 0 INPUT_AMPLIFIER_PRESENT 1 1 OUTPUT_AMPLIFIER_PRESENT 2 2 AMPLIFIER_PARAMETER_OVERRIDE 3 3 STRIPE 5 5 PROCESSING_WIDGET 6 6 UNSOLICITED_RESPONSE_CAPABILITY 7 7 CONNECTION_LIST 8 8 DIGITAL 9 9 POWER_CONTROL 10 10 LR_SWAP 11 11 AUDIO_WIDGET_CAPABILITIES_DELAY 16 19 TYPE 20 23 ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES 2 0x21 11 0 4294967295 IMPEDANCE_SENSE_CAPABLE 0 0 TRIGGER_REQUIRED 1 1 JACK_DETECTION_CAPABILITY 2 2 HEADPHONE_DRIVE_CAPABLE 3 3 OUTPUT_CAPABLE 4 4 INPUT_CAPABLE 5 5 BALANCED_I_O_PINS 6 6 HDMI 7 7 VREF_CONTROL 8 15 EAPD_CAPABLE 16 16 DP 24 24 ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE 2 0x22 2 0 4294967295 TAG 0 5 ENABLE 7 7 ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE 2 0x23 1 0 4294967295 IMPEDANCE_SENSE 0 30 ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL 2 0x24 1 0 4294967295 OUT_ENABLE 6 6 ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER 2 0x25 8 0 4294967295 SPEAKER_ALLOCATION 0 6 CHANNEL_ALLOCATION 8 15 HDMI_CONNECTION 16 16 DP_CONNECTION 17 17 EXTRA_CONNECTION_INFO 18 23 LFE_PLAYBACK_LEVEL 24 25 LEVEL_SHIFT 27 30 DOWN_MIX_INHIBIT 31 31 ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 2 0x28 4 0 4294967295 MAX_CHANNELS 0 2 SUPPORTED_FREQUENCIES 8 15 DESCRIPTOR_BYTE_2 16 23 SUPPORTED_FREQUENCIES_STEREO 24 31 ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 2 0x29 3 0 4294967295 MAX_CHANNELS 0 2 SUPPORTED_FREQUENCIES 8 15 DESCRIPTOR_BYTE_2 16 23 ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 2 0x2a 3 0 4294967295 MAX_CHANNELS 0 2 SUPPORTED_FREQUENCIES 8 15 DESCRIPTOR_BYTE_2 16 23 ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 2 0x2b 3 0 4294967295 MAX_CHANNELS 0 2 SUPPORTED_FREQUENCIES 8 15 DESCRIPTOR_BYTE_2 16 23 ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 2 0x2c 3 0 4294967295 MAX_CHANNELS 0 2 SUPPORTED_FREQUENCIES 8 15 DESCRIPTOR_BYTE_2 16 23 ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 2 0x2d 3 0 4294967295 MAX_CHANNELS 0 2 SUPPORTED_FREQUENCIES 8 15 DESCRIPTOR_BYTE_2 16 23 ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 2 0x2e 3 0 4294967295 MAX_CHANNELS 0 2 SUPPORTED_FREQUENCIES 8 15 DESCRIPTOR_BYTE_2 16 23 ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 2 0x2f 3 0 4294967295 MAX_CHANNELS 0 2 SUPPORTED_FREQUENCIES 8 15 DESCRIPTOR_BYTE_2 16 23 ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 2 0x30 3 0 4294967295 MAX_CHANNELS 0 2 SUPPORTED_FREQUENCIES 8 15 DESCRIPTOR_BYTE_2 16 23 ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 2 0x31 3 0 4294967295 MAX_CHANNELS 0 2 SUPPORTED_FREQUENCIES 8 15 DESCRIPTOR_BYTE_2 16 23 ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 2 0x32 3 0 4294967295 MAX_CHANNELS 0 2 SUPPORTED_FREQUENCIES 8 15 DESCRIPTOR_BYTE_2 16 23 ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 2 0x33 3 0 4294967295 MAX_CHANNELS 0 2 SUPPORTED_FREQUENCIES 8 15 DESCRIPTOR_BYTE_2 16 23 ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 2 0x34 3 0 4294967295 MAX_CHANNELS 0 2 SUPPORTED_FREQUENCIES 8 15 DESCRIPTOR_BYTE_2 16 23 ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 2 0x35 3 0 4294967295 MAX_CHANNELS 0 2 SUPPORTED_FREQUENCIES 8 15 DESCRIPTOR_BYTE_2 16 23 ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE 2 0x36 12 0 4294967295 MULTICHANNEL01_ENABLE 0 0 MULTICHANNEL01_MUTE 1 1 MULTICHANNEL01_CHANNEL_ID 4 7 MULTICHANNEL23_ENABLE 8 8 MULTICHANNEL23_MUTE 9 9 MULTICHANNEL23_CHANNEL_ID 12 15 MULTICHANNEL45_ENABLE 16 16 MULTICHANNEL45_MUTE 17 17 MULTICHANNEL45_CHANNEL_ID 20 23 MULTICHANNEL67_ENABLE 24 24 MULTICHANNEL67_MUTE 25 25 MULTICHANNEL67_CHANNEL_ID 28 31 ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC 2 0x37 2 0 4294967295 VIDEO_LIPSYNC 0 7 AUDIO_LIPSYNC 8 15 ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR 2 0x38 2 0 4294967295 HBR_CAPABLE 0 0 HBR_ENABLE 4 4 ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0 2 0x3a 2 0 4294967295 MANUFACTURER_ID 0 15 PRODUCT_ID 16 31 ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1 2 0x3b 1 0 4294967295 SINK_DESCRIPTION_LEN 0 7 ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2 2 0x3c 1 0 4294967295 PORT_ID0 0 31 ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3 2 0x3d 1 0 4294967295 PORT_ID1 0 31 ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4 2 0x3e 4 0 4294967295 DESCRIPTION0 0 7 DESCRIPTION1 8 15 DESCRIPTION2 16 23 DESCRIPTION3 24 31 ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5 2 0x3f 4 0 4294967295 DESCRIPTION4 0 7 DESCRIPTION5 8 15 DESCRIPTION6 16 23 DESCRIPTION7 24 31 ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6 2 0x40 4 0 4294967295 DESCRIPTION8 0 7 DESCRIPTION9 8 15 DESCRIPTION10 16 23 DESCRIPTION11 24 31 ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7 2 0x41 4 0 4294967295 DESCRIPTION12 0 7 DESCRIPTION13 8 15 DESCRIPTION14 16 23 DESCRIPTION15 24 31 ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8 2 0x42 2 0 4294967295 DESCRIPTION16 0 7 DESCRIPTION17 8 15 ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL 2 0x54 3 0 4294967295 CLOCK_GATING_DISABLE 0 0 CLOCK_ON_STATE 4 4 AUDIO_ENABLED 31 31 ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 2 0x55 2 0 4294967295 UNSOLICITED_RESPONSE_PAYLOAD 0 25 UNSOLICITED_RESPONSE_FORCE 28 28 ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 2 0x56 8 0 4294967295 SEQUENCE 0 3 DEFAULT_ASSOCIATION 4 7 MISC 8 11 COLOR 12 15 CONNECTION_TYPE 16 19 DEFAULT_DEVICE 20 23 LOCATION 24 29 PORT_CONNECTIVITY 30 31 ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2 2 0x57 12 0 4294967295 MULTICHANNEL1_ENABLE 0 0 MULTICHANNEL1_MUTE 1 1 MULTICHANNEL1_CHANNEL_ID 4 7 MULTICHANNEL3_ENABLE 8 8 MULTICHANNEL3_MUTE 9 9 MULTICHANNEL3_CHANNEL_ID 12 15 MULTICHANNEL5_ENABLE 16 16 MULTICHANNEL5_MUTE 17 17 MULTICHANNEL5_CHANNEL_ID 20 23 MULTICHANNEL7_ENABLE 24 24 MULTICHANNEL7_MUTE 25 25 MULTICHANNEL7_CHANNEL_ID 28 31 ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE 2 0x58 1 0 4294967295 MULTICHANNEL_MODE 0 0 ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0 2 0x59 2 0 4294967295 IEC_60958_CS_MODE 0 1 IEC_60958_CS_SOURCE_NUMBER 2 5 ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1 2 0x5a 4 0 4294967295 IEC_60958_CS_CLOCK_ACCURACY 0 1 IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN 2 2 IEC_60958_CS_WORD_LENGTH 3 6 IEC_60958_CS_WORD_LENGTH_OVRRD_EN 7 7 ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2 2 0x5b 2 0 4294967295 IEC_60958_CS_SAMPLING_FREQUENCY 0 5 IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN 6 6 ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3 2 0x5c 2 0 4294967295 IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY 0 3 IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN 4 4 ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4 2 0x5d 4 0 4294967295 IEC_60958_CS_SAMPLING_FREQUENCY_COEFF 0 3 IEC_60958_CS_MPEG_SURROUND_INFO 4 4 IEC_60958_CS_CGMS_A 5 6 IEC_60958_CS_CGMS_A_VALID 7 7 ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5 2 0x5e 2 0 4294967295 IEC_60958_CS_CHANNEL_NUMBER_L 0 3 IEC_60958_CS_CHANNEL_NUMBER_R 4 7 ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6 2 0x5f 2 0 4294967295 IEC_60958_CS_CHANNEL_NUMBER_2 0 3 IEC_60958_CS_CHANNEL_NUMBER_3 4 7 ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7 2 0x60 2 0 4294967295 IEC_60958_CS_CHANNEL_NUMBER_4 0 3 IEC_60958_CS_CHANNEL_NUMBER_5 4 7 ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8 2 0x61 2 0 4294967295 IEC_60958_CS_CHANNEL_NUMBER_6 0 3 IEC_60958_CS_CHANNEL_NUMBER_7 4 7 ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO 2 0x62 1 0 4294967295 ASSOCIATION_INFO 0 31 ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS 2 0x63 1 0 4294967295 OUTPUT_ACTIVE 0 0 ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 2 0x64 2 0 4294967295 LPIB_SNAPSHOT_LOCK 0 0 CYCLIC_BUFFER_WRAP_COUNT 8 15 ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB 2 0x65 1 0 4294967295 LPIB 0 31 ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 2 0x66 1 0 4294967295 LPIB_TIMER_SNAPSHOT 0 31 ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE 2 0x67 1 0 4294967295 CODING_TYPE 0 7 ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED 2 0x68 4 0 4294967295 FORMAT_CHANGED 0 0 FORMAT_CHANGED_ACK_UR_ENABLE 1 1 FORMAT_CHANGE_REASON 8 15 FORMAT_CHANGE_RESPONSE 16 23 ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION 2 0x69 1 0 4294967295 WIRELESS_DISPLAY_IDENTIFICATION 0 1 ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE 2 0x6a 2 0 4294967295 REMOTE_KEEP_ALIVE_ENABLE 0 0 REMOTE_KEEP_ALIVE_CAPABILITY 4 4 ixAZF0ENDPOINT5_AZALIA_F0_AUDIO_ENABLE_STATUS 2 0x6b 1 0 4294967295 AUDIO_ENABLE_STATUS 0 0 ixAZF0ENDPOINT5_AZALIA_F0_AUDIO_ENABLED_INT_STATUS 2 0x6c 3 0 4294967295 AUDIO_ENABLED_FLAG 0 0 AUDIO_ENABLED_MASK 4 4 AUDIO_ENABLED_TYPE 8 8 ixAZF0ENDPOINT5_AZALIA_F0_AUDIO_DISABLED_INT_STATUS 2 0x6d 3 0 4294967295 AUDIO_DISABLED_FLAG 0 0 AUDIO_DISABLED_MASK 4 4 AUDIO_DISABLED_TYPE 8 8 ixAZF0ENDPOINT5_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS 2 0x6e 3 0 4294967295 AUDIO_FORMAT_CHANGED_FLAG 0 0 AUDIO_FORMAT_CHANGED_MASK 4 4 AUDIO_FORMAT_CHANGED_TYPE 8 8 ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 2 0x1 14 0 4294967295 AUDIO_CHANNEL_CAPABILITIES 0 0 INPUT_AMPLIFIER_PRESENT 1 1 OUTPUT_AMPLIFIER_PRESENT 2 2 AMPLIFIER_PARAMETER_OVERRIDE 3 3 FORMAT_OVERRIDE 4 4 STRIPE 5 5 PROCESSING_WIDGET 6 6 UNSOLICITED_RESPONSE_CAPABILITY 7 7 CONNECTION_LIST 8 8 DIGITAL 9 9 POWER_CONTROL 10 10 LR_SWAP 11 11 AUDIO_WIDGET_CAPABILITIES_DELAY 16 19 TYPE 20 23 ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT 2 0x2 6 0 4294967295 NUMBER_OF_CHANNELS 0 3 BITS_PER_SAMPLE 4 6 SAMPLE_BASE_DIVISOR 8 10 SAMPLE_BASE_MULTIPLE 11 13 SAMPLE_BASE_RATE 14 14 STREAM_TYPE 15 15 ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID 2 0x3 2 0 4294967295 CHANNEL_ID 0 3 STREAM_ID 4 7 ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER 2 0x4 10 0 4294967295 DIGEN 0 0 V 1 1 VCFG 2 2 PRE 3 3 COPY 4 4 NON_AUDIO 5 5 PRO 6 6 L 7 7 CC 8 14 KEEPALIVE 23 23 ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS 2 0x5 1 0 4294967295 STREAM_FORMATS 0 31 ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 2 0x6 2 0 4294967295 AUDIO_RATE_CAPABILITIES 0 11 AUDIO_BIT_CAPABILITIES 16 20 ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL 2 0x7 2 0 4294967295 STRIPE_CONTROL 0 1 STRIPE_CAPABILITY 20 22 ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE 2 0x8 1 0 4294967295 RAMP_RATE 0 7 ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING 2 0x9 4 0 4294967295 PRESENTATION_TIME_EMBEDDING_ENABLE 0 0 PRESENTATION_TIME_OFFSET_CHANGED 1 1 CLEAR_GTC_COUNTER_MIN_MAX_DELTA 2 2 PRESENTATION_TIME_EMBEDDING_GROUP 4 6 ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA 2 0xc 1 0 4294967295 GTC_COUNTER_DELTA 0 31 ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN 2 0xd 1 0 4294967295 GTC_COUNTER_DELTA_MIN 0 31 ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX 2 0xe 1 0 4294967295 GTC_COUNTER_DELTA_MAX 0 31 ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 2 0x20 13 0 4294967295 AUDIO_CHANNEL_CAPABILITIES 0 0 INPUT_AMPLIFIER_PRESENT 1 1 OUTPUT_AMPLIFIER_PRESENT 2 2 AMPLIFIER_PARAMETER_OVERRIDE 3 3 STRIPE 5 5 PROCESSING_WIDGET 6 6 UNSOLICITED_RESPONSE_CAPABILITY 7 7 CONNECTION_LIST 8 8 DIGITAL 9 9 POWER_CONTROL 10 10 LR_SWAP 11 11 AUDIO_WIDGET_CAPABILITIES_DELAY 16 19 TYPE 20 23 ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES 2 0x21 11 0 4294967295 IMPEDANCE_SENSE_CAPABLE 0 0 TRIGGER_REQUIRED 1 1 JACK_DETECTION_CAPABILITY 2 2 HEADPHONE_DRIVE_CAPABLE 3 3 OUTPUT_CAPABLE 4 4 INPUT_CAPABLE 5 5 BALANCED_I_O_PINS 6 6 HDMI 7 7 VREF_CONTROL 8 15 EAPD_CAPABLE 16 16 DP 24 24 ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE 2 0x22 2 0 4294967295 TAG 0 5 ENABLE 7 7 ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE 2 0x23 1 0 4294967295 IMPEDANCE_SENSE 0 30 ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL 2 0x24 1 0 4294967295 OUT_ENABLE 6 6 ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER 2 0x25 8 0 4294967295 SPEAKER_ALLOCATION 0 6 CHANNEL_ALLOCATION 8 15 HDMI_CONNECTION 16 16 DP_CONNECTION 17 17 EXTRA_CONNECTION_INFO 18 23 LFE_PLAYBACK_LEVEL 24 25 LEVEL_SHIFT 27 30 DOWN_MIX_INHIBIT 31 31 ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 2 0x28 4 0 4294967295 MAX_CHANNELS 0 2 SUPPORTED_FREQUENCIES 8 15 DESCRIPTOR_BYTE_2 16 23 SUPPORTED_FREQUENCIES_STEREO 24 31 ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 2 0x29 3 0 4294967295 MAX_CHANNELS 0 2 SUPPORTED_FREQUENCIES 8 15 DESCRIPTOR_BYTE_2 16 23 ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 2 0x2a 3 0 4294967295 MAX_CHANNELS 0 2 SUPPORTED_FREQUENCIES 8 15 DESCRIPTOR_BYTE_2 16 23 ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 2 0x2b 3 0 4294967295 MAX_CHANNELS 0 2 SUPPORTED_FREQUENCIES 8 15 DESCRIPTOR_BYTE_2 16 23 ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 2 0x2c 3 0 4294967295 MAX_CHANNELS 0 2 SUPPORTED_FREQUENCIES 8 15 DESCRIPTOR_BYTE_2 16 23 ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 2 0x2d 3 0 4294967295 MAX_CHANNELS 0 2 SUPPORTED_FREQUENCIES 8 15 DESCRIPTOR_BYTE_2 16 23 ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 2 0x2e 3 0 4294967295 MAX_CHANNELS 0 2 SUPPORTED_FREQUENCIES 8 15 DESCRIPTOR_BYTE_2 16 23 ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 2 0x2f 3 0 4294967295 MAX_CHANNELS 0 2 SUPPORTED_FREQUENCIES 8 15 DESCRIPTOR_BYTE_2 16 23 ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 2 0x30 3 0 4294967295 MAX_CHANNELS 0 2 SUPPORTED_FREQUENCIES 8 15 DESCRIPTOR_BYTE_2 16 23 ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 2 0x31 3 0 4294967295 MAX_CHANNELS 0 2 SUPPORTED_FREQUENCIES 8 15 DESCRIPTOR_BYTE_2 16 23 ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 2 0x32 3 0 4294967295 MAX_CHANNELS 0 2 SUPPORTED_FREQUENCIES 8 15 DESCRIPTOR_BYTE_2 16 23 ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 2 0x33 3 0 4294967295 MAX_CHANNELS 0 2 SUPPORTED_FREQUENCIES 8 15 DESCRIPTOR_BYTE_2 16 23 ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 2 0x34 3 0 4294967295 MAX_CHANNELS 0 2 SUPPORTED_FREQUENCIES 8 15 DESCRIPTOR_BYTE_2 16 23 ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 2 0x35 3 0 4294967295 MAX_CHANNELS 0 2 SUPPORTED_FREQUENCIES 8 15 DESCRIPTOR_BYTE_2 16 23 ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE 2 0x36 12 0 4294967295 MULTICHANNEL01_ENABLE 0 0 MULTICHANNEL01_MUTE 1 1 MULTICHANNEL01_CHANNEL_ID 4 7 MULTICHANNEL23_ENABLE 8 8 MULTICHANNEL23_MUTE 9 9 MULTICHANNEL23_CHANNEL_ID 12 15 MULTICHANNEL45_ENABLE 16 16 MULTICHANNEL45_MUTE 17 17 MULTICHANNEL45_CHANNEL_ID 20 23 MULTICHANNEL67_ENABLE 24 24 MULTICHANNEL67_MUTE 25 25 MULTICHANNEL67_CHANNEL_ID 28 31 ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC 2 0x37 2 0 4294967295 VIDEO_LIPSYNC 0 7 AUDIO_LIPSYNC 8 15 ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR 2 0x38 2 0 4294967295 HBR_CAPABLE 0 0 HBR_ENABLE 4 4 ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0 2 0x3a 2 0 4294967295 MANUFACTURER_ID 0 15 PRODUCT_ID 16 31 ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1 2 0x3b 1 0 4294967295 SINK_DESCRIPTION_LEN 0 7 ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2 2 0x3c 1 0 4294967295 PORT_ID0 0 31 ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3 2 0x3d 1 0 4294967295 PORT_ID1 0 31 ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4 2 0x3e 4 0 4294967295 DESCRIPTION0 0 7 DESCRIPTION1 8 15 DESCRIPTION2 16 23 DESCRIPTION3 24 31 ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5 2 0x3f 4 0 4294967295 DESCRIPTION4 0 7 DESCRIPTION5 8 15 DESCRIPTION6 16 23 DESCRIPTION7 24 31 ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6 2 0x40 4 0 4294967295 DESCRIPTION8 0 7 DESCRIPTION9 8 15 DESCRIPTION10 16 23 DESCRIPTION11 24 31 ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7 2 0x41 4 0 4294967295 DESCRIPTION12 0 7 DESCRIPTION13 8 15 DESCRIPTION14 16 23 DESCRIPTION15 24 31 ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8 2 0x42 2 0 4294967295 DESCRIPTION16 0 7 DESCRIPTION17 8 15 ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL 2 0x54 3 0 4294967295 CLOCK_GATING_DISABLE 0 0 CLOCK_ON_STATE 4 4 AUDIO_ENABLED 31 31 ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 2 0x55 2 0 4294967295 UNSOLICITED_RESPONSE_PAYLOAD 0 25 UNSOLICITED_RESPONSE_FORCE 28 28 ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 2 0x56 8 0 4294967295 SEQUENCE 0 3 DEFAULT_ASSOCIATION 4 7 MISC 8 11 COLOR 12 15 CONNECTION_TYPE 16 19 DEFAULT_DEVICE 20 23 LOCATION 24 29 PORT_CONNECTIVITY 30 31 ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2 2 0x57 12 0 4294967295 MULTICHANNEL1_ENABLE 0 0 MULTICHANNEL1_MUTE 1 1 MULTICHANNEL1_CHANNEL_ID 4 7 MULTICHANNEL3_ENABLE 8 8 MULTICHANNEL3_MUTE 9 9 MULTICHANNEL3_CHANNEL_ID 12 15 MULTICHANNEL5_ENABLE 16 16 MULTICHANNEL5_MUTE 17 17 MULTICHANNEL5_CHANNEL_ID 20 23 MULTICHANNEL7_ENABLE 24 24 MULTICHANNEL7_MUTE 25 25 MULTICHANNEL7_CHANNEL_ID 28 31 ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE 2 0x58 1 0 4294967295 MULTICHANNEL_MODE 0 0 ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0 2 0x59 2 0 4294967295 IEC_60958_CS_MODE 0 1 IEC_60958_CS_SOURCE_NUMBER 2 5 ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1 2 0x5a 4 0 4294967295 IEC_60958_CS_CLOCK_ACCURACY 0 1 IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN 2 2 IEC_60958_CS_WORD_LENGTH 3 6 IEC_60958_CS_WORD_LENGTH_OVRRD_EN 7 7 ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2 2 0x5b 2 0 4294967295 IEC_60958_CS_SAMPLING_FREQUENCY 0 5 IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN 6 6 ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3 2 0x5c 2 0 4294967295 IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY 0 3 IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN 4 4 ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4 2 0x5d 4 0 4294967295 IEC_60958_CS_SAMPLING_FREQUENCY_COEFF 0 3 IEC_60958_CS_MPEG_SURROUND_INFO 4 4 IEC_60958_CS_CGMS_A 5 6 IEC_60958_CS_CGMS_A_VALID 7 7 ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5 2 0x5e 2 0 4294967295 IEC_60958_CS_CHANNEL_NUMBER_L 0 3 IEC_60958_CS_CHANNEL_NUMBER_R 4 7 ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6 2 0x5f 2 0 4294967295 IEC_60958_CS_CHANNEL_NUMBER_2 0 3 IEC_60958_CS_CHANNEL_NUMBER_3 4 7 ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7 2 0x60 2 0 4294967295 IEC_60958_CS_CHANNEL_NUMBER_4 0 3 IEC_60958_CS_CHANNEL_NUMBER_5 4 7 ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8 2 0x61 2 0 4294967295 IEC_60958_CS_CHANNEL_NUMBER_6 0 3 IEC_60958_CS_CHANNEL_NUMBER_7 4 7 ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO 2 0x62 1 0 4294967295 ASSOCIATION_INFO 0 31 ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS 2 0x63 1 0 4294967295 OUTPUT_ACTIVE 0 0 ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 2 0x64 2 0 4294967295 LPIB_SNAPSHOT_LOCK 0 0 CYCLIC_BUFFER_WRAP_COUNT 8 15 ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB 2 0x65 1 0 4294967295 LPIB 0 31 ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 2 0x66 1 0 4294967295 LPIB_TIMER_SNAPSHOT 0 31 ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE 2 0x67 1 0 4294967295 CODING_TYPE 0 7 ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED 2 0x68 4 0 4294967295 FORMAT_CHANGED 0 0 FORMAT_CHANGED_ACK_UR_ENABLE 1 1 FORMAT_CHANGE_REASON 8 15 FORMAT_CHANGE_RESPONSE 16 23 ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION 2 0x69 1 0 4294967295 WIRELESS_DISPLAY_IDENTIFICATION 0 1 ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE 2 0x6a 2 0 4294967295 REMOTE_KEEP_ALIVE_ENABLE 0 0 REMOTE_KEEP_ALIVE_CAPABILITY 4 4 ixAZF0ENDPOINT6_AZALIA_F0_AUDIO_ENABLE_STATUS 2 0x6b 1 0 4294967295 AUDIO_ENABLE_STATUS 0 0 ixAZF0ENDPOINT6_AZALIA_F0_AUDIO_ENABLED_INT_STATUS 2 0x6c 3 0 4294967295 AUDIO_ENABLED_FLAG 0 0 AUDIO_ENABLED_MASK 4 4 AUDIO_ENABLED_TYPE 8 8 ixAZF0ENDPOINT6_AZALIA_F0_AUDIO_DISABLED_INT_STATUS 2 0x6d 3 0 4294967295 AUDIO_DISABLED_FLAG 0 0 AUDIO_DISABLED_MASK 4 4 AUDIO_DISABLED_TYPE 8 8 ixAZF0ENDPOINT6_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS 2 0x6e 3 0 4294967295 AUDIO_FORMAT_CHANGED_FLAG 0 0 AUDIO_FORMAT_CHANGED_MASK 4 4 AUDIO_FORMAT_CHANGED_TYPE 8 8 ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 2 0x1 14 0 4294967295 AUDIO_CHANNEL_CAPABILITIES 0 0 INPUT_AMPLIFIER_PRESENT 1 1 OUTPUT_AMPLIFIER_PRESENT 2 2 AMPLIFIER_PARAMETER_OVERRIDE 3 3 FORMAT_OVERRIDE 4 4 STRIPE 5 5 PROCESSING_WIDGET 6 6 UNSOLICITED_RESPONSE_CAPABILITY 7 7 CONNECTION_LIST 8 8 DIGITAL 9 9 POWER_CONTROL 10 10 LR_SWAP 11 11 AUDIO_WIDGET_CAPABILITIES_DELAY 16 19 TYPE 20 23 ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT 2 0x2 6 0 4294967295 NUMBER_OF_CHANNELS 0 3 BITS_PER_SAMPLE 4 6 SAMPLE_BASE_DIVISOR 8 10 SAMPLE_BASE_MULTIPLE 11 13 SAMPLE_BASE_RATE 14 14 STREAM_TYPE 15 15 ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID 2 0x3 2 0 4294967295 CHANNEL_ID 0 3 STREAM_ID 4 7 ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER 2 0x4 10 0 4294967295 DIGEN 0 0 V 1 1 VCFG 2 2 PRE 3 3 COPY 4 4 NON_AUDIO 5 5 PRO 6 6 L 7 7 CC 8 14 KEEPALIVE 23 23 ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS 2 0x5 1 0 4294967295 STREAM_FORMATS 0 31 ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 2 0x6 2 0 4294967295 AUDIO_RATE_CAPABILITIES 0 11 AUDIO_BIT_CAPABILITIES 16 20 ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL 2 0x7 2 0 4294967295 STRIPE_CONTROL 0 1 STRIPE_CAPABILITY 20 22 ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE 2 0x8 1 0 4294967295 RAMP_RATE 0 7 ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING 2 0x9 4 0 4294967295 PRESENTATION_TIME_EMBEDDING_ENABLE 0 0 PRESENTATION_TIME_OFFSET_CHANGED 1 1 CLEAR_GTC_COUNTER_MIN_MAX_DELTA 2 2 PRESENTATION_TIME_EMBEDDING_GROUP 4 6 ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA 2 0xc 1 0 4294967295 GTC_COUNTER_DELTA 0 31 ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN 2 0xd 1 0 4294967295 GTC_COUNTER_DELTA_MIN 0 31 ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX 2 0xe 1 0 4294967295 GTC_COUNTER_DELTA_MAX 0 31 ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 2 0x20 13 0 4294967295 AUDIO_CHANNEL_CAPABILITIES 0 0 INPUT_AMPLIFIER_PRESENT 1 1 OUTPUT_AMPLIFIER_PRESENT 2 2 AMPLIFIER_PARAMETER_OVERRIDE 3 3 STRIPE 5 5 PROCESSING_WIDGET 6 6 UNSOLICITED_RESPONSE_CAPABILITY 7 7 CONNECTION_LIST 8 8 DIGITAL 9 9 POWER_CONTROL 10 10 LR_SWAP 11 11 AUDIO_WIDGET_CAPABILITIES_DELAY 16 19 TYPE 20 23 ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES 2 0x21 11 0 4294967295 IMPEDANCE_SENSE_CAPABLE 0 0 TRIGGER_REQUIRED 1 1 JACK_DETECTION_CAPABILITY 2 2 HEADPHONE_DRIVE_CAPABLE 3 3 OUTPUT_CAPABLE 4 4 INPUT_CAPABLE 5 5 BALANCED_I_O_PINS 6 6 HDMI 7 7 VREF_CONTROL 8 15 EAPD_CAPABLE 16 16 DP 24 24 ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE 2 0x22 2 0 4294967295 TAG 0 5 ENABLE 7 7 ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE 2 0x23 1 0 4294967295 IMPEDANCE_SENSE 0 30 ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL 2 0x24 1 0 4294967295 OUT_ENABLE 6 6 ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER 2 0x25 8 0 4294967295 SPEAKER_ALLOCATION 0 6 CHANNEL_ALLOCATION 8 15 HDMI_CONNECTION 16 16 DP_CONNECTION 17 17 EXTRA_CONNECTION_INFO 18 23 LFE_PLAYBACK_LEVEL 24 25 LEVEL_SHIFT 27 30 DOWN_MIX_INHIBIT 31 31 ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 2 0x28 4 0 4294967295 MAX_CHANNELS 0 2 SUPPORTED_FREQUENCIES 8 15 DESCRIPTOR_BYTE_2 16 23 SUPPORTED_FREQUENCIES_STEREO 24 31 ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 2 0x29 3 0 4294967295 MAX_CHANNELS 0 2 SUPPORTED_FREQUENCIES 8 15 DESCRIPTOR_BYTE_2 16 23 ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 2 0x2a 3 0 4294967295 MAX_CHANNELS 0 2 SUPPORTED_FREQUENCIES 8 15 DESCRIPTOR_BYTE_2 16 23 ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 2 0x2b 3 0 4294967295 MAX_CHANNELS 0 2 SUPPORTED_FREQUENCIES 8 15 DESCRIPTOR_BYTE_2 16 23 ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 2 0x2c 3 0 4294967295 MAX_CHANNELS 0 2 SUPPORTED_FREQUENCIES 8 15 DESCRIPTOR_BYTE_2 16 23 ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 2 0x2d 3 0 4294967295 MAX_CHANNELS 0 2 SUPPORTED_FREQUENCIES 8 15 DESCRIPTOR_BYTE_2 16 23 ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 2 0x2e 3 0 4294967295 MAX_CHANNELS 0 2 SUPPORTED_FREQUENCIES 8 15 DESCRIPTOR_BYTE_2 16 23 ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 2 0x2f 3 0 4294967295 MAX_CHANNELS 0 2 SUPPORTED_FREQUENCIES 8 15 DESCRIPTOR_BYTE_2 16 23 ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 2 0x30 3 0 4294967295 MAX_CHANNELS 0 2 SUPPORTED_FREQUENCIES 8 15 DESCRIPTOR_BYTE_2 16 23 ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 2 0x31 3 0 4294967295 MAX_CHANNELS 0 2 SUPPORTED_FREQUENCIES 8 15 DESCRIPTOR_BYTE_2 16 23 ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 2 0x32 3 0 4294967295 MAX_CHANNELS 0 2 SUPPORTED_FREQUENCIES 8 15 DESCRIPTOR_BYTE_2 16 23 ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 2 0x33 3 0 4294967295 MAX_CHANNELS 0 2 SUPPORTED_FREQUENCIES 8 15 DESCRIPTOR_BYTE_2 16 23 ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 2 0x34 3 0 4294967295 MAX_CHANNELS 0 2 SUPPORTED_FREQUENCIES 8 15 DESCRIPTOR_BYTE_2 16 23 ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 2 0x35 3 0 4294967295 MAX_CHANNELS 0 2 SUPPORTED_FREQUENCIES 8 15 DESCRIPTOR_BYTE_2 16 23 ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE 2 0x36 12 0 4294967295 MULTICHANNEL01_ENABLE 0 0 MULTICHANNEL01_MUTE 1 1 MULTICHANNEL01_CHANNEL_ID 4 7 MULTICHANNEL23_ENABLE 8 8 MULTICHANNEL23_MUTE 9 9 MULTICHANNEL23_CHANNEL_ID 12 15 MULTICHANNEL45_ENABLE 16 16 MULTICHANNEL45_MUTE 17 17 MULTICHANNEL45_CHANNEL_ID 20 23 MULTICHANNEL67_ENABLE 24 24 MULTICHANNEL67_MUTE 25 25 MULTICHANNEL67_CHANNEL_ID 28 31 ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC 2 0x37 2 0 4294967295 VIDEO_LIPSYNC 0 7 AUDIO_LIPSYNC 8 15 ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR 2 0x38 2 0 4294967295 HBR_CAPABLE 0 0 HBR_ENABLE 4 4 ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0 2 0x3a 2 0 4294967295 MANUFACTURER_ID 0 15 PRODUCT_ID 16 31 ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1 2 0x3b 1 0 4294967295 SINK_DESCRIPTION_LEN 0 7 ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2 2 0x3c 1 0 4294967295 PORT_ID0 0 31 ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3 2 0x3d 1 0 4294967295 PORT_ID1 0 31 ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4 2 0x3e 4 0 4294967295 DESCRIPTION0 0 7 DESCRIPTION1 8 15 DESCRIPTION2 16 23 DESCRIPTION3 24 31 ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5 2 0x3f 4 0 4294967295 DESCRIPTION4 0 7 DESCRIPTION5 8 15 DESCRIPTION6 16 23 DESCRIPTION7 24 31 ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6 2 0x40 4 0 4294967295 DESCRIPTION8 0 7 DESCRIPTION9 8 15 DESCRIPTION10 16 23 DESCRIPTION11 24 31 ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7 2 0x41 4 0 4294967295 DESCRIPTION12 0 7 DESCRIPTION13 8 15 DESCRIPTION14 16 23 DESCRIPTION15 24 31 ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8 2 0x42 2 0 4294967295 DESCRIPTION16 0 7 DESCRIPTION17 8 15 ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL 2 0x54 3 0 4294967295 CLOCK_GATING_DISABLE 0 0 CLOCK_ON_STATE 4 4 AUDIO_ENABLED 31 31 ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 2 0x55 2 0 4294967295 UNSOLICITED_RESPONSE_PAYLOAD 0 25 UNSOLICITED_RESPONSE_FORCE 28 28 ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 2 0x56 8 0 4294967295 SEQUENCE 0 3 DEFAULT_ASSOCIATION 4 7 MISC 8 11 COLOR 12 15 CONNECTION_TYPE 16 19 DEFAULT_DEVICE 20 23 LOCATION 24 29 PORT_CONNECTIVITY 30 31 ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2 2 0x57 12 0 4294967295 MULTICHANNEL1_ENABLE 0 0 MULTICHANNEL1_MUTE 1 1 MULTICHANNEL1_CHANNEL_ID 4 7 MULTICHANNEL3_ENABLE 8 8 MULTICHANNEL3_MUTE 9 9 MULTICHANNEL3_CHANNEL_ID 12 15 MULTICHANNEL5_ENABLE 16 16 MULTICHANNEL5_MUTE 17 17 MULTICHANNEL5_CHANNEL_ID 20 23 MULTICHANNEL7_ENABLE 24 24 MULTICHANNEL7_MUTE 25 25 MULTICHANNEL7_CHANNEL_ID 28 31 ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE 2 0x58 1 0 4294967295 MULTICHANNEL_MODE 0 0 ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0 2 0x59 2 0 4294967295 IEC_60958_CS_MODE 0 1 IEC_60958_CS_SOURCE_NUMBER 2 5 ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1 2 0x5a 4 0 4294967295 IEC_60958_CS_CLOCK_ACCURACY 0 1 IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN 2 2 IEC_60958_CS_WORD_LENGTH 3 6 IEC_60958_CS_WORD_LENGTH_OVRRD_EN 7 7 ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2 2 0x5b 2 0 4294967295 IEC_60958_CS_SAMPLING_FREQUENCY 0 5 IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN 6 6 ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3 2 0x5c 2 0 4294967295 IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY 0 3 IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN 4 4 ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4 2 0x5d 4 0 4294967295 IEC_60958_CS_SAMPLING_FREQUENCY_COEFF 0 3 IEC_60958_CS_MPEG_SURROUND_INFO 4 4 IEC_60958_CS_CGMS_A 5 6 IEC_60958_CS_CGMS_A_VALID 7 7 ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5 2 0x5e 2 0 4294967295 IEC_60958_CS_CHANNEL_NUMBER_L 0 3 IEC_60958_CS_CHANNEL_NUMBER_R 4 7 ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6 2 0x5f 2 0 4294967295 IEC_60958_CS_CHANNEL_NUMBER_2 0 3 IEC_60958_CS_CHANNEL_NUMBER_3 4 7 ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7 2 0x60 2 0 4294967295 IEC_60958_CS_CHANNEL_NUMBER_4 0 3 IEC_60958_CS_CHANNEL_NUMBER_5 4 7 ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8 2 0x61 2 0 4294967295 IEC_60958_CS_CHANNEL_NUMBER_6 0 3 IEC_60958_CS_CHANNEL_NUMBER_7 4 7 ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO 2 0x62 1 0 4294967295 ASSOCIATION_INFO 0 31 ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS 2 0x63 1 0 4294967295 OUTPUT_ACTIVE 0 0 ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 2 0x64 2 0 4294967295 LPIB_SNAPSHOT_LOCK 0 0 CYCLIC_BUFFER_WRAP_COUNT 8 15 ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB 2 0x65 1 0 4294967295 LPIB 0 31 ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 2 0x66 1 0 4294967295 LPIB_TIMER_SNAPSHOT 0 31 ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE 2 0x67 1 0 4294967295 CODING_TYPE 0 7 ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED 2 0x68 4 0 4294967295 FORMAT_CHANGED 0 0 FORMAT_CHANGED_ACK_UR_ENABLE 1 1 FORMAT_CHANGE_REASON 8 15 FORMAT_CHANGE_RESPONSE 16 23 ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION 2 0x69 1 0 4294967295 WIRELESS_DISPLAY_IDENTIFICATION 0 1 ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE 2 0x6a 2 0 4294967295 REMOTE_KEEP_ALIVE_ENABLE 0 0 REMOTE_KEEP_ALIVE_CAPABILITY 4 4 ixAZF0ENDPOINT7_AZALIA_F0_AUDIO_ENABLE_STATUS 2 0x6b 1 0 4294967295 AUDIO_ENABLE_STATUS 0 0 ixAZF0ENDPOINT7_AZALIA_F0_AUDIO_ENABLED_INT_STATUS 2 0x6c 3 0 4294967295 AUDIO_ENABLED_FLAG 0 0 AUDIO_ENABLED_MASK 4 4 AUDIO_ENABLED_TYPE 8 8 ixAZF0ENDPOINT7_AZALIA_F0_AUDIO_DISABLED_INT_STATUS 2 0x6d 3 0 4294967295 AUDIO_DISABLED_FLAG 0 0 AUDIO_DISABLED_MASK 4 4 AUDIO_DISABLED_TYPE 8 8 ixAZF0ENDPOINT7_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS 2 0x6e 3 0 4294967295 AUDIO_FORMAT_CHANGED_FLAG 0 0 AUDIO_FORMAT_CHANGED_MASK 4 4 AUDIO_FORMAT_CHANGED_TYPE 8 8 ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 2 0x1 14 0 4294967295 AUDIO_CHANNEL_CAPABILITIES 0 0 INPUT_AMPLIFIER_PRESENT 1 1 OUTPUT_AMPLIFIER_PRESENT 2 2 AMPLIFIER_PARAMETER_OVERRIDE 3 3 FORMAT_OVERRIDE 4 4 STRIPE 5 5 PROCESSING_WIDGET 6 6 UNSOLICITED_RESPONSE_CAPABILITY 7 7 CONNECTION_LIST 8 8 DIGITAL 9 9 POWER_CONTROL 10 10 LR_SWAP 11 11 AUDIO_WIDGET_CAPABILITIES_DELAY 16 19 TYPE 20 23 ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT 2 0x2 6 0 4294967295 NUMBER_OF_CHANNELS 0 3 BITS_PER_SAMPLE 4 6 SAMPLE_BASE_DIVISOR 8 10 SAMPLE_BASE_MULTIPLE 11 13 SAMPLE_BASE_RATE 14 14 STREAM_TYPE 15 15 ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID 2 0x3 2 0 4294967295 CHANNEL_ID 0 3 STREAM_ID 4 7 ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER 2 0x4 10 0 4294967295 DIGEN 0 0 V 1 1 VCFG 2 2 PRE 3 3 COPY 4 4 NON_AUDIO 5 5 PRO 6 6 L 7 7 CC 8 14 KEEPALIVE 23 23 ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS 2 0x5 1 0 4294967295 STREAM_FORMATS 0 31 ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 2 0x6 2 0 4294967295 AUDIO_RATE_CAPABILITIES 0 11 AUDIO_BIT_CAPABILITIES 16 20 ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 2 0x20 13 0 4294967295 AUDIO_CHANNEL_CAPABILITIES 0 0 INPUT_AMPLIFIER_PRESENT 1 1 OUTPUT_AMPLIFIER_PRESENT 2 2 AMPLIFIER_PARAMETER_OVERRIDE 3 3 STRIPE 5 5 PROCESSING_WIDGET 6 6 UNSOLICITED_RESPONSE_CAPABILITY 7 7 CONNECTION_LIST 8 8 DIGITAL 9 9 POWER_CONTROL 10 10 LR_SWAP 11 11 AUDIO_WIDGET_CAPABILITIES_DELAY 16 19 TYPE 20 23 ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES 2 0x21 11 0 4294967295 IMPEDANCE_SENSE_CAPABLE 0 0 TRIGGER_REQUIRED 1 1 JACK_DETECTION_CAPABILITY 2 2 HEADPHONE_DRIVE_CAPABLE 3 3 OUTPUT_CAPABLE 4 4 INPUT_CAPABLE 5 5 BALANCED_I_O_PINS 6 6 HDMI 7 7 VREF_CONTROL 8 15 EAPD_CAPABLE 16 16 DP 24 24 ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE 2 0x22 2 0 4294967295 TAG 0 5 ENABLE 7 7 ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE 2 0x23 2 0 4294967295 IMPEDANCE_SENSE 0 30 PRESENCE_DETECT 31 31 ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL 2 0x24 1 0 4294967295 IN_ENABLE 5 5 ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE 2 0x36 12 0 4294967295 MULTICHANNEL0_ENABLE 0 0 MULTICHANNEL0_MUTE 1 1 MULTICHANNEL0_CHANNEL_ID 4 7 MULTICHANNEL1_ENABLE 8 8 MULTICHANNEL1_MUTE 9 9 MULTICHANNEL1_CHANNEL_ID 12 15 MULTICHANNEL2_ENABLE 16 16 MULTICHANNEL2_MUTE 17 17 MULTICHANNEL2_CHANNEL_ID 20 23 MULTICHANNEL3_ENABLE 24 24 MULTICHANNEL3_MUTE 25 25 MULTICHANNEL3_CHANNEL_ID 28 31 ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2 2 0x37 12 0 4294967295 MULTICHANNEL4_ENABLE 0 0 MULTICHANNEL4_MUTE 1 1 MULTICHANNEL4_CHANNEL_ID 4 7 MULTICHANNEL5_ENABLE 8 8 MULTICHANNEL5_MUTE 9 9 MULTICHANNEL5_CHANNEL_ID 12 15 MULTICHANNEL6_ENABLE 16 16 MULTICHANNEL6_MUTE 17 17 MULTICHANNEL6_CHANNEL_ID 20 23 MULTICHANNEL7_ENABLE 24 24 MULTICHANNEL7_MUTE 25 25 MULTICHANNEL7_CHANNEL_ID 28 31 ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR 2 0x38 2 0 4294967295 HBR_CAPABLE 0 0 HBR_ENABLE 4 4 ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION 2 0x53 1 0 4294967295 CHANNEL_ALLOCATION 0 7 ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL 2 0x54 3 0 4294967295 CLOCK_GATING_DISABLE 0 0 CLOCK_ON_STATE 4 4 AUDIO_ENABLED 31 31 ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 2 0x55 2 0 4294967295 UNSOLICITED_RESPONSE_PAYLOAD 0 25 UNSOLICITED_RESPONSE_FORCE 28 28 ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 2 0x56 8 0 4294967295 SEQUENCE 0 3 DEFAULT_ASSOCIATION 4 7 MISC 8 11 COLOR 12 15 CONNECTION_TYPE 16 19 DEFAULT_DEVICE 20 23 LOCATION 24 29 PORT_CONNECTIVITY 30 31 ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 2 0x64 2 0 4294967295 LPIB_SNAPSHOT_LOCK 0 0 CYCLIC_BUFFER_WRAP_COUNT 8 15 ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB 2 0x65 1 0 4294967295 LPIB 0 31 ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 2 0x66 1 0 4294967295 LPIB_TIMER_SNAPSHOT 0 31 ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL 2 0x67 4 0 4294967295 INPUT_ACTIVITY 0 0 CHANNEL_LAYOUT 1 2 INPUT_ACTIVITY_UR_ENABLE 4 4 INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE 5 5 ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME 2 0x68 4 0 4294967295 CHANNEL_COUNT 0 2 CHANNEL_ALLOCATION 8 15 INFOFRAME_BYTE_5 16 23 INFOFRAME_VALID 31 31 ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 2 0x1 14 0 4294967295 AUDIO_CHANNEL_CAPABILITIES 0 0 INPUT_AMPLIFIER_PRESENT 1 1 OUTPUT_AMPLIFIER_PRESENT 2 2 AMPLIFIER_PARAMETER_OVERRIDE 3 3 FORMAT_OVERRIDE 4 4 STRIPE 5 5 PROCESSING_WIDGET 6 6 UNSOLICITED_RESPONSE_CAPABILITY 7 7 CONNECTION_LIST 8 8 DIGITAL 9 9 POWER_CONTROL 10 10 LR_SWAP 11 11 AUDIO_WIDGET_CAPABILITIES_DELAY 16 19 TYPE 20 23 ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT 2 0x2 6 0 4294967295 NUMBER_OF_CHANNELS 0 3 BITS_PER_SAMPLE 4 6 SAMPLE_BASE_DIVISOR 8 10 SAMPLE_BASE_MULTIPLE 11 13 SAMPLE_BASE_RATE 14 14 STREAM_TYPE 15 15 ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID 2 0x3 2 0 4294967295 CHANNEL_ID 0 3 STREAM_ID 4 7 ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER 2 0x4 10 0 4294967295 DIGEN 0 0 V 1 1 VCFG 2 2 PRE 3 3 COPY 4 4 NON_AUDIO 5 5 PRO 6 6 L 7 7 CC 8 14 KEEPALIVE 23 23 ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS 2 0x5 1 0 4294967295 STREAM_FORMATS 0 31 ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 2 0x6 2 0 4294967295 AUDIO_RATE_CAPABILITIES 0 11 AUDIO_BIT_CAPABILITIES 16 20 ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 2 0x20 13 0 4294967295 AUDIO_CHANNEL_CAPABILITIES 0 0 INPUT_AMPLIFIER_PRESENT 1 1 OUTPUT_AMPLIFIER_PRESENT 2 2 AMPLIFIER_PARAMETER_OVERRIDE 3 3 STRIPE 5 5 PROCESSING_WIDGET 6 6 UNSOLICITED_RESPONSE_CAPABILITY 7 7 CONNECTION_LIST 8 8 DIGITAL 9 9 POWER_CONTROL 10 10 LR_SWAP 11 11 AUDIO_WIDGET_CAPABILITIES_DELAY 16 19 TYPE 20 23 ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES 2 0x21 11 0 4294967295 IMPEDANCE_SENSE_CAPABLE 0 0 TRIGGER_REQUIRED 1 1 JACK_DETECTION_CAPABILITY 2 2 HEADPHONE_DRIVE_CAPABLE 3 3 OUTPUT_CAPABLE 4 4 INPUT_CAPABLE 5 5 BALANCED_I_O_PINS 6 6 HDMI 7 7 VREF_CONTROL 8 15 EAPD_CAPABLE 16 16 DP 24 24 ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE 2 0x22 2 0 4294967295 TAG 0 5 ENABLE 7 7 ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE 2 0x23 2 0 4294967295 IMPEDANCE_SENSE 0 30 PRESENCE_DETECT 31 31 ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL 2 0x24 1 0 4294967295 IN_ENABLE 5 5 ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE 2 0x36 12 0 4294967295 MULTICHANNEL0_ENABLE 0 0 MULTICHANNEL0_MUTE 1 1 MULTICHANNEL0_CHANNEL_ID 4 7 MULTICHANNEL1_ENABLE 8 8 MULTICHANNEL1_MUTE 9 9 MULTICHANNEL1_CHANNEL_ID 12 15 MULTICHANNEL2_ENABLE 16 16 MULTICHANNEL2_MUTE 17 17 MULTICHANNEL2_CHANNEL_ID 20 23 MULTICHANNEL3_ENABLE 24 24 MULTICHANNEL3_MUTE 25 25 MULTICHANNEL3_CHANNEL_ID 28 31 ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2 2 0x37 12 0 4294967295 MULTICHANNEL4_ENABLE 0 0 MULTICHANNEL4_MUTE 1 1 MULTICHANNEL4_CHANNEL_ID 4 7 MULTICHANNEL5_ENABLE 8 8 MULTICHANNEL5_MUTE 9 9 MULTICHANNEL5_CHANNEL_ID 12 15 MULTICHANNEL6_ENABLE 16 16 MULTICHANNEL6_MUTE 17 17 MULTICHANNEL6_CHANNEL_ID 20 23 MULTICHANNEL7_ENABLE 24 24 MULTICHANNEL7_MUTE 25 25 MULTICHANNEL7_CHANNEL_ID 28 31 ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR 2 0x38 2 0 4294967295 HBR_CAPABLE 0 0 HBR_ENABLE 4 4 ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION 2 0x53 1 0 4294967295 CHANNEL_ALLOCATION 0 7 ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL 2 0x54 3 0 4294967295 CLOCK_GATING_DISABLE 0 0 CLOCK_ON_STATE 4 4 AUDIO_ENABLED 31 31 ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 2 0x55 2 0 4294967295 UNSOLICITED_RESPONSE_PAYLOAD 0 25 UNSOLICITED_RESPONSE_FORCE 28 28 ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 2 0x56 8 0 4294967295 SEQUENCE 0 3 DEFAULT_ASSOCIATION 4 7 MISC 8 11 COLOR 12 15 CONNECTION_TYPE 16 19 DEFAULT_DEVICE 20 23 LOCATION 24 29 PORT_CONNECTIVITY 30 31 ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 2 0x64 2 0 4294967295 LPIB_SNAPSHOT_LOCK 0 0 CYCLIC_BUFFER_WRAP_COUNT 8 15 ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB 2 0x65 1 0 4294967295 LPIB 0 31 ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 2 0x66 1 0 4294967295 LPIB_TIMER_SNAPSHOT 0 31 ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL 2 0x67 4 0 4294967295 INPUT_ACTIVITY 0 0 CHANNEL_LAYOUT 1 2 INPUT_ACTIVITY_UR_ENABLE 4 4 INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE 5 5 ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME 2 0x68 4 0 4294967295 CHANNEL_COUNT 0 2 CHANNEL_ALLOCATION 8 15 INFOFRAME_BYTE_5 16 23 INFOFRAME_VALID 31 31 ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 2 0x1 14 0 4294967295 AUDIO_CHANNEL_CAPABILITIES 0 0 INPUT_AMPLIFIER_PRESENT 1 1 OUTPUT_AMPLIFIER_PRESENT 2 2 AMPLIFIER_PARAMETER_OVERRIDE 3 3 FORMAT_OVERRIDE 4 4 STRIPE 5 5 PROCESSING_WIDGET 6 6 UNSOLICITED_RESPONSE_CAPABILITY 7 7 CONNECTION_LIST 8 8 DIGITAL 9 9 POWER_CONTROL 10 10 LR_SWAP 11 11 AUDIO_WIDGET_CAPABILITIES_DELAY 16 19 TYPE 20 23 ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT 2 0x2 6 0 4294967295 NUMBER_OF_CHANNELS 0 3 BITS_PER_SAMPLE 4 6 SAMPLE_BASE_DIVISOR 8 10 SAMPLE_BASE_MULTIPLE 11 13 SAMPLE_BASE_RATE 14 14 STREAM_TYPE 15 15 ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID 2 0x3 2 0 4294967295 CHANNEL_ID 0 3 STREAM_ID 4 7 ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER 2 0x4 10 0 4294967295 DIGEN 0 0 V 1 1 VCFG 2 2 PRE 3 3 COPY 4 4 NON_AUDIO 5 5 PRO 6 6 L 7 7 CC 8 14 KEEPALIVE 23 23 ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS 2 0x5 1 0 4294967295 STREAM_FORMATS 0 31 ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 2 0x6 2 0 4294967295 AUDIO_RATE_CAPABILITIES 0 11 AUDIO_BIT_CAPABILITIES 16 20 ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 2 0x20 13 0 4294967295 AUDIO_CHANNEL_CAPABILITIES 0 0 INPUT_AMPLIFIER_PRESENT 1 1 OUTPUT_AMPLIFIER_PRESENT 2 2 AMPLIFIER_PARAMETER_OVERRIDE 3 3 STRIPE 5 5 PROCESSING_WIDGET 6 6 UNSOLICITED_RESPONSE_CAPABILITY 7 7 CONNECTION_LIST 8 8 DIGITAL 9 9 POWER_CONTROL 10 10 LR_SWAP 11 11 AUDIO_WIDGET_CAPABILITIES_DELAY 16 19 TYPE 20 23 ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES 2 0x21 11 0 4294967295 IMPEDANCE_SENSE_CAPABLE 0 0 TRIGGER_REQUIRED 1 1 JACK_DETECTION_CAPABILITY 2 2 HEADPHONE_DRIVE_CAPABLE 3 3 OUTPUT_CAPABLE 4 4 INPUT_CAPABLE 5 5 BALANCED_I_O_PINS 6 6 HDMI 7 7 VREF_CONTROL 8 15 EAPD_CAPABLE 16 16 DP 24 24 ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE 2 0x22 2 0 4294967295 TAG 0 5 ENABLE 7 7 ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE 2 0x23 2 0 4294967295 IMPEDANCE_SENSE 0 30 PRESENCE_DETECT 31 31 ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL 2 0x24 1 0 4294967295 IN_ENABLE 5 5 ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE 2 0x36 12 0 4294967295 MULTICHANNEL0_ENABLE 0 0 MULTICHANNEL0_MUTE 1 1 MULTICHANNEL0_CHANNEL_ID 4 7 MULTICHANNEL1_ENABLE 8 8 MULTICHANNEL1_MUTE 9 9 MULTICHANNEL1_CHANNEL_ID 12 15 MULTICHANNEL2_ENABLE 16 16 MULTICHANNEL2_MUTE 17 17 MULTICHANNEL2_CHANNEL_ID 20 23 MULTICHANNEL3_ENABLE 24 24 MULTICHANNEL3_MUTE 25 25 MULTICHANNEL3_CHANNEL_ID 28 31 ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2 2 0x37 12 0 4294967295 MULTICHANNEL4_ENABLE 0 0 MULTICHANNEL4_MUTE 1 1 MULTICHANNEL4_CHANNEL_ID 4 7 MULTICHANNEL5_ENABLE 8 8 MULTICHANNEL5_MUTE 9 9 MULTICHANNEL5_CHANNEL_ID 12 15 MULTICHANNEL6_ENABLE 16 16 MULTICHANNEL6_MUTE 17 17 MULTICHANNEL6_CHANNEL_ID 20 23 MULTICHANNEL7_ENABLE 24 24 MULTICHANNEL7_MUTE 25 25 MULTICHANNEL7_CHANNEL_ID 28 31 ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR 2 0x38 2 0 4294967295 HBR_CAPABLE 0 0 HBR_ENABLE 4 4 ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION 2 0x53 1 0 4294967295 CHANNEL_ALLOCATION 0 7 ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL 2 0x54 3 0 4294967295 CLOCK_GATING_DISABLE 0 0 CLOCK_ON_STATE 4 4 AUDIO_ENABLED 31 31 ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 2 0x55 2 0 4294967295 UNSOLICITED_RESPONSE_PAYLOAD 0 25 UNSOLICITED_RESPONSE_FORCE 28 28 ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 2 0x56 8 0 4294967295 SEQUENCE 0 3 DEFAULT_ASSOCIATION 4 7 MISC 8 11 COLOR 12 15 CONNECTION_TYPE 16 19 DEFAULT_DEVICE 20 23 LOCATION 24 29 PORT_CONNECTIVITY 30 31 ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 2 0x64 2 0 4294967295 LPIB_SNAPSHOT_LOCK 0 0 CYCLIC_BUFFER_WRAP_COUNT 8 15 ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB 2 0x65 1 0 4294967295 LPIB 0 31 ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 2 0x66 1 0 4294967295 LPIB_TIMER_SNAPSHOT 0 31 ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL 2 0x67 4 0 4294967295 INPUT_ACTIVITY 0 0 CHANNEL_LAYOUT 1 2 INPUT_ACTIVITY_UR_ENABLE 4 4 INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE 5 5 ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME 2 0x68 4 0 4294967295 CHANNEL_COUNT 0 2 CHANNEL_ALLOCATION 8 15 INFOFRAME_BYTE_5 16 23 INFOFRAME_VALID 31 31 ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 2 0x1 14 0 4294967295 AUDIO_CHANNEL_CAPABILITIES 0 0 INPUT_AMPLIFIER_PRESENT 1 1 OUTPUT_AMPLIFIER_PRESENT 2 2 AMPLIFIER_PARAMETER_OVERRIDE 3 3 FORMAT_OVERRIDE 4 4 STRIPE 5 5 PROCESSING_WIDGET 6 6 UNSOLICITED_RESPONSE_CAPABILITY 7 7 CONNECTION_LIST 8 8 DIGITAL 9 9 POWER_CONTROL 10 10 LR_SWAP 11 11 AUDIO_WIDGET_CAPABILITIES_DELAY 16 19 TYPE 20 23 ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT 2 0x2 6 0 4294967295 NUMBER_OF_CHANNELS 0 3 BITS_PER_SAMPLE 4 6 SAMPLE_BASE_DIVISOR 8 10 SAMPLE_BASE_MULTIPLE 11 13 SAMPLE_BASE_RATE 14 14 STREAM_TYPE 15 15 ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID 2 0x3 2 0 4294967295 CHANNEL_ID 0 3 STREAM_ID 4 7 ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER 2 0x4 10 0 4294967295 DIGEN 0 0 V 1 1 VCFG 2 2 PRE 3 3 COPY 4 4 NON_AUDIO 5 5 PRO 6 6 L 7 7 CC 8 14 KEEPALIVE 23 23 ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS 2 0x5 1 0 4294967295 STREAM_FORMATS 0 31 ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 2 0x6 2 0 4294967295 AUDIO_RATE_CAPABILITIES 0 11 AUDIO_BIT_CAPABILITIES 16 20 ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 2 0x20 13 0 4294967295 AUDIO_CHANNEL_CAPABILITIES 0 0 INPUT_AMPLIFIER_PRESENT 1 1 OUTPUT_AMPLIFIER_PRESENT 2 2 AMPLIFIER_PARAMETER_OVERRIDE 3 3 STRIPE 5 5 PROCESSING_WIDGET 6 6 UNSOLICITED_RESPONSE_CAPABILITY 7 7 CONNECTION_LIST 8 8 DIGITAL 9 9 POWER_CONTROL 10 10 LR_SWAP 11 11 AUDIO_WIDGET_CAPABILITIES_DELAY 16 19 TYPE 20 23 ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES 2 0x21 11 0 4294967295 IMPEDANCE_SENSE_CAPABLE 0 0 TRIGGER_REQUIRED 1 1 JACK_DETECTION_CAPABILITY 2 2 HEADPHONE_DRIVE_CAPABLE 3 3 OUTPUT_CAPABLE 4 4 INPUT_CAPABLE 5 5 BALANCED_I_O_PINS 6 6 HDMI 7 7 VREF_CONTROL 8 15 EAPD_CAPABLE 16 16 DP 24 24 ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE 2 0x22 2 0 4294967295 TAG 0 5 ENABLE 7 7 ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE 2 0x23 2 0 4294967295 IMPEDANCE_SENSE 0 30 PRESENCE_DETECT 31 31 ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL 2 0x24 1 0 4294967295 IN_ENABLE 5 5 ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE 2 0x36 12 0 4294967295 MULTICHANNEL0_ENABLE 0 0 MULTICHANNEL0_MUTE 1 1 MULTICHANNEL0_CHANNEL_ID 4 7 MULTICHANNEL1_ENABLE 8 8 MULTICHANNEL1_MUTE 9 9 MULTICHANNEL1_CHANNEL_ID 12 15 MULTICHANNEL2_ENABLE 16 16 MULTICHANNEL2_MUTE 17 17 MULTICHANNEL2_CHANNEL_ID 20 23 MULTICHANNEL3_ENABLE 24 24 MULTICHANNEL3_MUTE 25 25 MULTICHANNEL3_CHANNEL_ID 28 31 ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2 2 0x37 12 0 4294967295 MULTICHANNEL4_ENABLE 0 0 MULTICHANNEL4_MUTE 1 1 MULTICHANNEL4_CHANNEL_ID 4 7 MULTICHANNEL5_ENABLE 8 8 MULTICHANNEL5_MUTE 9 9 MULTICHANNEL5_CHANNEL_ID 12 15 MULTICHANNEL6_ENABLE 16 16 MULTICHANNEL6_MUTE 17 17 MULTICHANNEL6_CHANNEL_ID 20 23 MULTICHANNEL7_ENABLE 24 24 MULTICHANNEL7_MUTE 25 25 MULTICHANNEL7_CHANNEL_ID 28 31 ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR 2 0x38 2 0 4294967295 HBR_CAPABLE 0 0 HBR_ENABLE 4 4 ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION 2 0x53 1 0 4294967295 CHANNEL_ALLOCATION 0 7 ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL 2 0x54 3 0 4294967295 CLOCK_GATING_DISABLE 0 0 CLOCK_ON_STATE 4 4 AUDIO_ENABLED 31 31 ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 2 0x55 2 0 4294967295 UNSOLICITED_RESPONSE_PAYLOAD 0 25 UNSOLICITED_RESPONSE_FORCE 28 28 ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 2 0x56 8 0 4294967295 SEQUENCE 0 3 DEFAULT_ASSOCIATION 4 7 MISC 8 11 COLOR 12 15 CONNECTION_TYPE 16 19 DEFAULT_DEVICE 20 23 LOCATION 24 29 PORT_CONNECTIVITY 30 31 ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 2 0x64 2 0 4294967295 LPIB_SNAPSHOT_LOCK 0 0 CYCLIC_BUFFER_WRAP_COUNT 8 15 ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB 2 0x65 1 0 4294967295 LPIB 0 31 ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 2 0x66 1 0 4294967295 LPIB_TIMER_SNAPSHOT 0 31 ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL 2 0x67 4 0 4294967295 INPUT_ACTIVITY 0 0 CHANNEL_LAYOUT 1 2 INPUT_ACTIVITY_UR_ENABLE 4 4 INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE 5 5 ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME 2 0x68 4 0 4294967295 CHANNEL_COUNT 0 2 CHANNEL_ALLOCATION 8 15 INFOFRAME_BYTE_5 16 23 INFOFRAME_VALID 31 31 ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 2 0x1 14 0 4294967295 AUDIO_CHANNEL_CAPABILITIES 0 0 INPUT_AMPLIFIER_PRESENT 1 1 OUTPUT_AMPLIFIER_PRESENT 2 2 AMPLIFIER_PARAMETER_OVERRIDE 3 3 FORMAT_OVERRIDE 4 4 STRIPE 5 5 PROCESSING_WIDGET 6 6 UNSOLICITED_RESPONSE_CAPABILITY 7 7 CONNECTION_LIST 8 8 DIGITAL 9 9 POWER_CONTROL 10 10 LR_SWAP 11 11 AUDIO_WIDGET_CAPABILITIES_DELAY 16 19 TYPE 20 23 ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT 2 0x2 6 0 4294967295 NUMBER_OF_CHANNELS 0 3 BITS_PER_SAMPLE 4 6 SAMPLE_BASE_DIVISOR 8 10 SAMPLE_BASE_MULTIPLE 11 13 SAMPLE_BASE_RATE 14 14 STREAM_TYPE 15 15 ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID 2 0x3 2 0 4294967295 CHANNEL_ID 0 3 STREAM_ID 4 7 ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER 2 0x4 10 0 4294967295 DIGEN 0 0 V 1 1 VCFG 2 2 PRE 3 3 COPY 4 4 NON_AUDIO 5 5 PRO 6 6 L 7 7 CC 8 14 KEEPALIVE 23 23 ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS 2 0x5 1 0 4294967295 STREAM_FORMATS 0 31 ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 2 0x6 2 0 4294967295 AUDIO_RATE_CAPABILITIES 0 11 AUDIO_BIT_CAPABILITIES 16 20 ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 2 0x20 13 0 4294967295 AUDIO_CHANNEL_CAPABILITIES 0 0 INPUT_AMPLIFIER_PRESENT 1 1 OUTPUT_AMPLIFIER_PRESENT 2 2 AMPLIFIER_PARAMETER_OVERRIDE 3 3 STRIPE 5 5 PROCESSING_WIDGET 6 6 UNSOLICITED_RESPONSE_CAPABILITY 7 7 CONNECTION_LIST 8 8 DIGITAL 9 9 POWER_CONTROL 10 10 LR_SWAP 11 11 AUDIO_WIDGET_CAPABILITIES_DELAY 16 19 TYPE 20 23 ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES 2 0x21 11 0 4294967295 IMPEDANCE_SENSE_CAPABLE 0 0 TRIGGER_REQUIRED 1 1 JACK_DETECTION_CAPABILITY 2 2 HEADPHONE_DRIVE_CAPABLE 3 3 OUTPUT_CAPABLE 4 4 INPUT_CAPABLE 5 5 BALANCED_I_O_PINS 6 6 HDMI 7 7 VREF_CONTROL 8 15 EAPD_CAPABLE 16 16 DP 24 24 ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE 2 0x22 2 0 4294967295 TAG 0 5 ENABLE 7 7 ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE 2 0x23 2 0 4294967295 IMPEDANCE_SENSE 0 30 PRESENCE_DETECT 31 31 ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL 2 0x24 1 0 4294967295 IN_ENABLE 5 5 ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE 2 0x36 12 0 4294967295 MULTICHANNEL0_ENABLE 0 0 MULTICHANNEL0_MUTE 1 1 MULTICHANNEL0_CHANNEL_ID 4 7 MULTICHANNEL1_ENABLE 8 8 MULTICHANNEL1_MUTE 9 9 MULTICHANNEL1_CHANNEL_ID 12 15 MULTICHANNEL2_ENABLE 16 16 MULTICHANNEL2_MUTE 17 17 MULTICHANNEL2_CHANNEL_ID 20 23 MULTICHANNEL3_ENABLE 24 24 MULTICHANNEL3_MUTE 25 25 MULTICHANNEL3_CHANNEL_ID 28 31 ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2 2 0x37 12 0 4294967295 MULTICHANNEL4_ENABLE 0 0 MULTICHANNEL4_MUTE 1 1 MULTICHANNEL4_CHANNEL_ID 4 7 MULTICHANNEL5_ENABLE 8 8 MULTICHANNEL5_MUTE 9 9 MULTICHANNEL5_CHANNEL_ID 12 15 MULTICHANNEL6_ENABLE 16 16 MULTICHANNEL6_MUTE 17 17 MULTICHANNEL6_CHANNEL_ID 20 23 MULTICHANNEL7_ENABLE 24 24 MULTICHANNEL7_MUTE 25 25 MULTICHANNEL7_CHANNEL_ID 28 31 ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR 2 0x38 2 0 4294967295 HBR_CAPABLE 0 0 HBR_ENABLE 4 4 ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION 2 0x53 1 0 4294967295 CHANNEL_ALLOCATION 0 7 ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL 2 0x54 3 0 4294967295 CLOCK_GATING_DISABLE 0 0 CLOCK_ON_STATE 4 4 AUDIO_ENABLED 31 31 ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 2 0x55 2 0 4294967295 UNSOLICITED_RESPONSE_PAYLOAD 0 25 UNSOLICITED_RESPONSE_FORCE 28 28 ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 2 0x56 8 0 4294967295 SEQUENCE 0 3 DEFAULT_ASSOCIATION 4 7 MISC 8 11 COLOR 12 15 CONNECTION_TYPE 16 19 DEFAULT_DEVICE 20 23 LOCATION 24 29 PORT_CONNECTIVITY 30 31 ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 2 0x64 2 0 4294967295 LPIB_SNAPSHOT_LOCK 0 0 CYCLIC_BUFFER_WRAP_COUNT 8 15 ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB 2 0x65 1 0 4294967295 LPIB 0 31 ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 2 0x66 1 0 4294967295 LPIB_TIMER_SNAPSHOT 0 31 ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL 2 0x67 4 0 4294967295 INPUT_ACTIVITY 0 0 CHANNEL_LAYOUT 1 2 INPUT_ACTIVITY_UR_ENABLE 4 4 INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE 5 5 ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME 2 0x68 4 0 4294967295 CHANNEL_COUNT 0 2 CHANNEL_ALLOCATION 8 15 INFOFRAME_BYTE_5 16 23 INFOFRAME_VALID 31 31 ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 2 0x1 14 0 4294967295 AUDIO_CHANNEL_CAPABILITIES 0 0 INPUT_AMPLIFIER_PRESENT 1 1 OUTPUT_AMPLIFIER_PRESENT 2 2 AMPLIFIER_PARAMETER_OVERRIDE 3 3 FORMAT_OVERRIDE 4 4 STRIPE 5 5 PROCESSING_WIDGET 6 6 UNSOLICITED_RESPONSE_CAPABILITY 7 7 CONNECTION_LIST 8 8 DIGITAL 9 9 POWER_CONTROL 10 10 LR_SWAP 11 11 AUDIO_WIDGET_CAPABILITIES_DELAY 16 19 TYPE 20 23 ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT 2 0x2 6 0 4294967295 NUMBER_OF_CHANNELS 0 3 BITS_PER_SAMPLE 4 6 SAMPLE_BASE_DIVISOR 8 10 SAMPLE_BASE_MULTIPLE 11 13 SAMPLE_BASE_RATE 14 14 STREAM_TYPE 15 15 ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID 2 0x3 2 0 4294967295 CHANNEL_ID 0 3 STREAM_ID 4 7 ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER 2 0x4 10 0 4294967295 DIGEN 0 0 V 1 1 VCFG 2 2 PRE 3 3 COPY 4 4 NON_AUDIO 5 5 PRO 6 6 L 7 7 CC 8 14 KEEPALIVE 23 23 ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS 2 0x5 1 0 4294967295 STREAM_FORMATS 0 31 ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 2 0x6 2 0 4294967295 AUDIO_RATE_CAPABILITIES 0 11 AUDIO_BIT_CAPABILITIES 16 20 ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 2 0x20 13 0 4294967295 AUDIO_CHANNEL_CAPABILITIES 0 0 INPUT_AMPLIFIER_PRESENT 1 1 OUTPUT_AMPLIFIER_PRESENT 2 2 AMPLIFIER_PARAMETER_OVERRIDE 3 3 STRIPE 5 5 PROCESSING_WIDGET 6 6 UNSOLICITED_RESPONSE_CAPABILITY 7 7 CONNECTION_LIST 8 8 DIGITAL 9 9 POWER_CONTROL 10 10 LR_SWAP 11 11 AUDIO_WIDGET_CAPABILITIES_DELAY 16 19 TYPE 20 23 ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES 2 0x21 11 0 4294967295 IMPEDANCE_SENSE_CAPABLE 0 0 TRIGGER_REQUIRED 1 1 JACK_DETECTION_CAPABILITY 2 2 HEADPHONE_DRIVE_CAPABLE 3 3 OUTPUT_CAPABLE 4 4 INPUT_CAPABLE 5 5 BALANCED_I_O_PINS 6 6 HDMI 7 7 VREF_CONTROL 8 15 EAPD_CAPABLE 16 16 DP 24 24 ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE 2 0x22 2 0 4294967295 TAG 0 5 ENABLE 7 7 ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE 2 0x23 2 0 4294967295 IMPEDANCE_SENSE 0 30 PRESENCE_DETECT 31 31 ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL 2 0x24 1 0 4294967295 IN_ENABLE 5 5 ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE 2 0x36 12 0 4294967295 MULTICHANNEL0_ENABLE 0 0 MULTICHANNEL0_MUTE 1 1 MULTICHANNEL0_CHANNEL_ID 4 7 MULTICHANNEL1_ENABLE 8 8 MULTICHANNEL1_MUTE 9 9 MULTICHANNEL1_CHANNEL_ID 12 15 MULTICHANNEL2_ENABLE 16 16 MULTICHANNEL2_MUTE 17 17 MULTICHANNEL2_CHANNEL_ID 20 23 MULTICHANNEL3_ENABLE 24 24 MULTICHANNEL3_MUTE 25 25 MULTICHANNEL3_CHANNEL_ID 28 31 ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2 2 0x37 12 0 4294967295 MULTICHANNEL4_ENABLE 0 0 MULTICHANNEL4_MUTE 1 1 MULTICHANNEL4_CHANNEL_ID 4 7 MULTICHANNEL5_ENABLE 8 8 MULTICHANNEL5_MUTE 9 9 MULTICHANNEL5_CHANNEL_ID 12 15 MULTICHANNEL6_ENABLE 16 16 MULTICHANNEL6_MUTE 17 17 MULTICHANNEL6_CHANNEL_ID 20 23 MULTICHANNEL7_ENABLE 24 24 MULTICHANNEL7_MUTE 25 25 MULTICHANNEL7_CHANNEL_ID 28 31 ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR 2 0x38 2 0 4294967295 HBR_CAPABLE 0 0 HBR_ENABLE 4 4 ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION 2 0x53 1 0 4294967295 CHANNEL_ALLOCATION 0 7 ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL 2 0x54 3 0 4294967295 CLOCK_GATING_DISABLE 0 0 CLOCK_ON_STATE 4 4 AUDIO_ENABLED 31 31 ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 2 0x55 2 0 4294967295 UNSOLICITED_RESPONSE_PAYLOAD 0 25 UNSOLICITED_RESPONSE_FORCE 28 28 ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 2 0x56 8 0 4294967295 SEQUENCE 0 3 DEFAULT_ASSOCIATION 4 7 MISC 8 11 COLOR 12 15 CONNECTION_TYPE 16 19 DEFAULT_DEVICE 20 23 LOCATION 24 29 PORT_CONNECTIVITY 30 31 ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 2 0x64 2 0 4294967295 LPIB_SNAPSHOT_LOCK 0 0 CYCLIC_BUFFER_WRAP_COUNT 8 15 ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB 2 0x65 1 0 4294967295 LPIB 0 31 ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 2 0x66 1 0 4294967295 LPIB_TIMER_SNAPSHOT 0 31 ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL 2 0x67 4 0 4294967295 INPUT_ACTIVITY 0 0 CHANNEL_LAYOUT 1 2 INPUT_ACTIVITY_UR_ENABLE 4 4 INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE 5 5 ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME 2 0x68 4 0 4294967295 CHANNEL_COUNT 0 2 CHANNEL_ALLOCATION 8 15 INFOFRAME_BYTE_5 16 23 INFOFRAME_VALID 31 31 ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 2 0x1 14 0 4294967295 AUDIO_CHANNEL_CAPABILITIES 0 0 INPUT_AMPLIFIER_PRESENT 1 1 OUTPUT_AMPLIFIER_PRESENT 2 2 AMPLIFIER_PARAMETER_OVERRIDE 3 3 FORMAT_OVERRIDE 4 4 STRIPE 5 5 PROCESSING_WIDGET 6 6 UNSOLICITED_RESPONSE_CAPABILITY 7 7 CONNECTION_LIST 8 8 DIGITAL 9 9 POWER_CONTROL 10 10 LR_SWAP 11 11 AUDIO_WIDGET_CAPABILITIES_DELAY 16 19 TYPE 20 23 ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT 2 0x2 6 0 4294967295 NUMBER_OF_CHANNELS 0 3 BITS_PER_SAMPLE 4 6 SAMPLE_BASE_DIVISOR 8 10 SAMPLE_BASE_MULTIPLE 11 13 SAMPLE_BASE_RATE 14 14 STREAM_TYPE 15 15 ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID 2 0x3 2 0 4294967295 CHANNEL_ID 0 3 STREAM_ID 4 7 ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER 2 0x4 10 0 4294967295 DIGEN 0 0 V 1 1 VCFG 2 2 PRE 3 3 COPY 4 4 NON_AUDIO 5 5 PRO 6 6 L 7 7 CC 8 14 KEEPALIVE 23 23 ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS 2 0x5 1 0 4294967295 STREAM_FORMATS 0 31 ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 2 0x6 2 0 4294967295 AUDIO_RATE_CAPABILITIES 0 11 AUDIO_BIT_CAPABILITIES 16 20 ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 2 0x20 13 0 4294967295 AUDIO_CHANNEL_CAPABILITIES 0 0 INPUT_AMPLIFIER_PRESENT 1 1 OUTPUT_AMPLIFIER_PRESENT 2 2 AMPLIFIER_PARAMETER_OVERRIDE 3 3 STRIPE 5 5 PROCESSING_WIDGET 6 6 UNSOLICITED_RESPONSE_CAPABILITY 7 7 CONNECTION_LIST 8 8 DIGITAL 9 9 POWER_CONTROL 10 10 LR_SWAP 11 11 AUDIO_WIDGET_CAPABILITIES_DELAY 16 19 TYPE 20 23 ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES 2 0x21 11 0 4294967295 IMPEDANCE_SENSE_CAPABLE 0 0 TRIGGER_REQUIRED 1 1 JACK_DETECTION_CAPABILITY 2 2 HEADPHONE_DRIVE_CAPABLE 3 3 OUTPUT_CAPABLE 4 4 INPUT_CAPABLE 5 5 BALANCED_I_O_PINS 6 6 HDMI 7 7 VREF_CONTROL 8 15 EAPD_CAPABLE 16 16 DP 24 24 ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE 2 0x22 2 0 4294967295 TAG 0 5 ENABLE 7 7 ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE 2 0x23 2 0 4294967295 IMPEDANCE_SENSE 0 30 PRESENCE_DETECT 31 31 ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL 2 0x24 1 0 4294967295 IN_ENABLE 5 5 ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE 2 0x36 12 0 4294967295 MULTICHANNEL0_ENABLE 0 0 MULTICHANNEL0_MUTE 1 1 MULTICHANNEL0_CHANNEL_ID 4 7 MULTICHANNEL1_ENABLE 8 8 MULTICHANNEL1_MUTE 9 9 MULTICHANNEL1_CHANNEL_ID 12 15 MULTICHANNEL2_ENABLE 16 16 MULTICHANNEL2_MUTE 17 17 MULTICHANNEL2_CHANNEL_ID 20 23 MULTICHANNEL3_ENABLE 24 24 MULTICHANNEL3_MUTE 25 25 MULTICHANNEL3_CHANNEL_ID 28 31 ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2 2 0x37 12 0 4294967295 MULTICHANNEL4_ENABLE 0 0 MULTICHANNEL4_MUTE 1 1 MULTICHANNEL4_CHANNEL_ID 4 7 MULTICHANNEL5_ENABLE 8 8 MULTICHANNEL5_MUTE 9 9 MULTICHANNEL5_CHANNEL_ID 12 15 MULTICHANNEL6_ENABLE 16 16 MULTICHANNEL6_MUTE 17 17 MULTICHANNEL6_CHANNEL_ID 20 23 MULTICHANNEL7_ENABLE 24 24 MULTICHANNEL7_MUTE 25 25 MULTICHANNEL7_CHANNEL_ID 28 31 ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR 2 0x38 2 0 4294967295 HBR_CAPABLE 0 0 HBR_ENABLE 4 4 ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION 2 0x53 1 0 4294967295 CHANNEL_ALLOCATION 0 7 ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL 2 0x54 3 0 4294967295 CLOCK_GATING_DISABLE 0 0 CLOCK_ON_STATE 4 4 AUDIO_ENABLED 31 31 ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 2 0x55 2 0 4294967295 UNSOLICITED_RESPONSE_PAYLOAD 0 25 UNSOLICITED_RESPONSE_FORCE 28 28 ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 2 0x56 8 0 4294967295 SEQUENCE 0 3 DEFAULT_ASSOCIATION 4 7 MISC 8 11 COLOR 12 15 CONNECTION_TYPE 16 19 DEFAULT_DEVICE 20 23 LOCATION 24 29 PORT_CONNECTIVITY 30 31 ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 2 0x64 2 0 4294967295 LPIB_SNAPSHOT_LOCK 0 0 CYCLIC_BUFFER_WRAP_COUNT 8 15 ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB 2 0x65 1 0 4294967295 LPIB 0 31 ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 2 0x66 1 0 4294967295 LPIB_TIMER_SNAPSHOT 0 31 ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL 2 0x67 4 0 4294967295 INPUT_ACTIVITY 0 0 CHANNEL_LAYOUT 1 2 INPUT_ACTIVITY_UR_ENABLE 4 4 INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE 5 5 ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME 2 0x68 4 0 4294967295 CHANNEL_COUNT 0 2 CHANNEL_ALLOCATION 8 15 INFOFRAME_BYTE_5 16 23 INFOFRAME_VALID 31 31 ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 2 0x1 14 0 4294967295 AUDIO_CHANNEL_CAPABILITIES 0 0 INPUT_AMPLIFIER_PRESENT 1 1 OUTPUT_AMPLIFIER_PRESENT 2 2 AMPLIFIER_PARAMETER_OVERRIDE 3 3 FORMAT_OVERRIDE 4 4 STRIPE 5 5 PROCESSING_WIDGET 6 6 UNSOLICITED_RESPONSE_CAPABILITY 7 7 CONNECTION_LIST 8 8 DIGITAL 9 9 POWER_CONTROL 10 10 LR_SWAP 11 11 AUDIO_WIDGET_CAPABILITIES_DELAY 16 19 TYPE 20 23 ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT 2 0x2 6 0 4294967295 NUMBER_OF_CHANNELS 0 3 BITS_PER_SAMPLE 4 6 SAMPLE_BASE_DIVISOR 8 10 SAMPLE_BASE_MULTIPLE 11 13 SAMPLE_BASE_RATE 14 14 STREAM_TYPE 15 15 ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID 2 0x3 2 0 4294967295 CHANNEL_ID 0 3 STREAM_ID 4 7 ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER 2 0x4 10 0 4294967295 DIGEN 0 0 V 1 1 VCFG 2 2 PRE 3 3 COPY 4 4 NON_AUDIO 5 5 PRO 6 6 L 7 7 CC 8 14 KEEPALIVE 23 23 ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS 2 0x5 1 0 4294967295 STREAM_FORMATS 0 31 ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 2 0x6 2 0 4294967295 AUDIO_RATE_CAPABILITIES 0 11 AUDIO_BIT_CAPABILITIES 16 20 ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 2 0x20 13 0 4294967295 AUDIO_CHANNEL_CAPABILITIES 0 0 INPUT_AMPLIFIER_PRESENT 1 1 OUTPUT_AMPLIFIER_PRESENT 2 2 AMPLIFIER_PARAMETER_OVERRIDE 3 3 STRIPE 5 5 PROCESSING_WIDGET 6 6 UNSOLICITED_RESPONSE_CAPABILITY 7 7 CONNECTION_LIST 8 8 DIGITAL 9 9 POWER_CONTROL 10 10 LR_SWAP 11 11 AUDIO_WIDGET_CAPABILITIES_DELAY 16 19 TYPE 20 23 ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES 2 0x21 11 0 4294967295 IMPEDANCE_SENSE_CAPABLE 0 0 TRIGGER_REQUIRED 1 1 JACK_DETECTION_CAPABILITY 2 2 HEADPHONE_DRIVE_CAPABLE 3 3 OUTPUT_CAPABLE 4 4 INPUT_CAPABLE 5 5 BALANCED_I_O_PINS 6 6 HDMI 7 7 VREF_CONTROL 8 15 EAPD_CAPABLE 16 16 DP 24 24 ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE 2 0x22 2 0 4294967295 TAG 0 5 ENABLE 7 7 ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE 2 0x23 2 0 4294967295 IMPEDANCE_SENSE 0 30 PRESENCE_DETECT 31 31 ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL 2 0x24 1 0 4294967295 IN_ENABLE 5 5 ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE 2 0x36 12 0 4294967295 MULTICHANNEL0_ENABLE 0 0 MULTICHANNEL0_MUTE 1 1 MULTICHANNEL0_CHANNEL_ID 4 7 MULTICHANNEL1_ENABLE 8 8 MULTICHANNEL1_MUTE 9 9 MULTICHANNEL1_CHANNEL_ID 12 15 MULTICHANNEL2_ENABLE 16 16 MULTICHANNEL2_MUTE 17 17 MULTICHANNEL2_CHANNEL_ID 20 23 MULTICHANNEL3_ENABLE 24 24 MULTICHANNEL3_MUTE 25 25 MULTICHANNEL3_CHANNEL_ID 28 31 ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2 2 0x37 12 0 4294967295 MULTICHANNEL4_ENABLE 0 0 MULTICHANNEL4_MUTE 1 1 MULTICHANNEL4_CHANNEL_ID 4 7 MULTICHANNEL5_ENABLE 8 8 MULTICHANNEL5_MUTE 9 9 MULTICHANNEL5_CHANNEL_ID 12 15 MULTICHANNEL6_ENABLE 16 16 MULTICHANNEL6_MUTE 17 17 MULTICHANNEL6_CHANNEL_ID 20 23 MULTICHANNEL7_ENABLE 24 24 MULTICHANNEL7_MUTE 25 25 MULTICHANNEL7_CHANNEL_ID 28 31 ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR 2 0x38 2 0 4294967295 HBR_CAPABLE 0 0 HBR_ENABLE 4 4 ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION 2 0x53 1 0 4294967295 CHANNEL_ALLOCATION 0 7 ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL 2 0x54 3 0 4294967295 CLOCK_GATING_DISABLE 0 0 CLOCK_ON_STATE 4 4 AUDIO_ENABLED 31 31 ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 2 0x55 2 0 4294967295 UNSOLICITED_RESPONSE_PAYLOAD 0 25 UNSOLICITED_RESPONSE_FORCE 28 28 ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 2 0x56 8 0 4294967295 SEQUENCE 0 3 DEFAULT_ASSOCIATION 4 7 MISC 8 11 COLOR 12 15 CONNECTION_TYPE 16 19 DEFAULT_DEVICE 20 23 LOCATION 24 29 PORT_CONNECTIVITY 30 31 ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 2 0x64 2 0 4294967295 LPIB_SNAPSHOT_LOCK 0 0 CYCLIC_BUFFER_WRAP_COUNT 8 15 ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB 2 0x65 1 0 4294967295 LPIB 0 31 ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 2 0x66 1 0 4294967295 LPIB_TIMER_SNAPSHOT 0 31 ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL 2 0x67 4 0 4294967295 INPUT_ACTIVITY 0 0 CHANNEL_LAYOUT 1 2 INPUT_ACTIVITY_UR_ENABLE 4 4 INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE 5 5 ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME 2 0x68 4 0 4294967295 CHANNEL_COUNT 0 2 CHANNEL_ALLOCATION 8 15 INFOFRAME_BYTE_5 16 23 INFOFRAME_VALID 31 31 ixAZALIA_F2_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID 2 0xf00 1 0 4294967295 AZALIA_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID 0 31 ixAZALIA_F2_CODEC_ROOT_PARAMETER_REVISION_ID 2 0xf02 1 0 4294967295 AZALIA_CODEC_ROOT_PARAMETER_REVISION_ID 0 31 ixAZALIA_F2_CODEC_ROOT_PARAMETER_SUBORDINATE_NODE_COUNT 2 0xf04 1 0 4294967295 AZALIA_CODEC_ROOT_PARAMETER_SUBORDINATE_NODE_COUNT 0 31 ixAZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE 2 0x1705 4 0 4294967295 POWER_STATE_SET 0 3 POWER_STATE_ACT 4 7 CLKSTOPOK 9 9 POWER_STATE_SETTINGS_RESET 10 10 ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID 2 0x1720 4 0 4294967295 SUBSYSTEM_ID_BYTE0 0 7 SUBSYSTEM_ID_BYTE1 8 15 SUBSYSTEM_ID_BYTE2 16 23 SUBSYSTEM_ID_BYTE3 24 31 ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_2 2 0x1721 1 0 4294967295 SUBSYSTEM_ID_BYTE1 0 7 ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_3 2 0x1722 1 0 4294967295 SUBSYSTEM_ID_BYTE2 0 7 ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_4 2 0x1723 1 0 4294967295 SUBSYSTEM_ID_BYTE3 0 7 ixAZALIA_F2_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION 2 0x1770 1 0 4294967295 CONVERTER_SYNCHRONIZATION 0 7 ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESET 2 0x17ff 1 0 4294967295 CODEC_RESET 0 0 ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_SUBORDINATE_NODE_COUNT 2 0x1f04 1 0 4294967295 AZALIA_CODEC_FUNCTION_PARAMETER_SUBORDINATE_NODE_COUNT 0 31 ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_GROUP_TYPE 2 0x1f05 1 0 4294967295 AZALIA_CODEC_FUNCTION_PARAMETER_GROUP_TYPE 0 31 ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES 2 0x1f0a 2 0 4294967295 AUDIO_RATE_CAPABILITIES 0 11 AUDIO_BIT_CAPABILITIES 16 20 ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS 2 0x1f0b 1 0 4294967295 AZALIA_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS 0 31 ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES 2 0x1f0f 3 0 4294967295 AZALIA_CODEC_FUNCTION_PARAMETER_POWER_STATES 0 29 CLKSTOP 30 30 EPSS 31 31 ixAZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT 2 0x2200 7 0 4294967295 NUMBER_OF_CHANNELS 0 3 BITS_PER_SAMPLE 4 6 SAMPLE_BASE_DIVISOR 8 10 SAMPLE_BASE_MULTIPLE 11 13 SAMPLE_BASE_RATE 14 14 STREAM_TYPE 15 15 STREAM_TYPE_R 15 15 ixAZALIA_F2_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID 2 0x2706 2 0 4294967295 CHANNEL_ID 0 3 STREAM_ID 4 7 ixAZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER 2 0x270d 10 0 4294967295 DIGEN 0 0 V 1 1 VCFG 2 2 PRE 3 3 COPY 4 4 NON_AUDIO 5 5 PRO 6 6 L 7 7 CC 8 14 KEEPALIVE 23 23 ixAZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_2 2 0x270e 1 0 4294967295 CC 0 6 ixAZALIA_F2_CODEC_CONVERTER_STRIPE_CONTROL 2 0x2724 2 0 4294967295 STRIPE_CONTROL 0 1 STRIPE_CAPABILITY 20 22 ixAZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3 2 0x273e 1 0 4294967295 KEEPALIVE 7 7 ixAZALIA_F2_CODEC_CONVERTER_CONTROL_RAMP_RATE 2 0x2770 1 0 4294967295 RAMP_RATE 0 7 ixAZALIA_F2_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING 2 0x2771 3 0 4294967295 PRESENTATION_TIME_EMBEDDING_ENABLE 0 0 PRESENTATION_TIME_OFFSET_CHANGED 1 1 PRESENTATION_TIME_EMBEDDING_GROUP 4 6 ixAZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 2 0x2f09 14 0 4294967295 AUDIO_CHANNEL_CAPABILITIES 0 0 INPUT_AMPLIFIER_PRESENT 1 1 OUTPUT_AMPLIFIER_PRESENT 2 2 AMPLIFIER_PARAMETER_OVERRIDE 3 3 FORMAT_OVERRIDE 4 4 STRIPE 5 5 PROCESSING_WIDGET 6 6 UNSOLICITED_RESPONSE_CAPABILITY 7 7 CONNECTION_LIST 8 8 DIGITAL 9 9 POWER_CONTROL 10 10 LR_SWAP 11 11 AUDIO_WIDGET_CAPABILITIES_DELAY 16 19 TYPE 20 23 ixAZALIA_F2_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 2 0x2f0a 2 0 4294967295 AUDIO_RATE_CAPABILITIES 0 11 AUDIO_BIT_CAPABILITIES 16 20 ixAZALIA_F2_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS 2 0x2f0b 1 0 4294967295 STREAM_FORMATS 0 31 ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONNECTION_LIST_ENTRY 2 0x3702 1 0 4294967295 CONNECTION_LIST_ENTRY 0 31 ixAZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL 2 0x3707 1 0 4294967295 OUT_ENABLE 6 6 ixAZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE 2 0x3708 2 0 4294967295 TAG 0 5 ENABLE 7 7 ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE 2 0x3709 2 0 4294967295 IMPEDANCE_SENSE 0 30 PRESENCE_DETECT 31 31 ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 2 0x371c 8 0 4294967295 SEQUENCE 0 3 DEFAULT_ASSOCIATION 4 7 MISC 8 11 COLOR 12 15 CONNECTION_TYPE 16 19 DEFAULT_DEVICE 20 23 LOCATION 24 29 PORT_CONNECTIVITY 30 31 ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2 2 0x371d 2 0 4294967295 MISC 0 3 COLOR 4 7 ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3 2 0x371e 2 0 4294967295 CONNECTION_TYPE 0 3 DEFAULT_DEVICE 4 7 ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4 2 0x371f 2 0 4294967295 LOCATION 0 5 PORT_CONNECTIVITY 6 7 ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION 2 0x3770 4 0 4294967295 SPEAKER_ALLOCATION 0 6 HDMI_CONNECTION 8 8 DP_CONNECTION 9 9 EXTRA_CONNECTION_INFO 10 15 ixAZALIA_F2_CODEC_PIN_CONTROL_CHANNEL_ALLOCATION 2 0x3771 1 0 4294967295 CHANNEL_ALLOCATION 0 7 ixAZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO 2 0x3772 3 0 4294967295 LFE_PLAYBACK_LEVEL 0 1 LEVEL_SHIFT 3 6 DOWN_MIX_INHIBIT 7 7 ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR 2 0x3776 5 0 4294967295 MAX_CHANNELS 0 2 FORMAT_CODE 3 6 SUPPORTED_FREQUENCIES 8 15 DESCRIPTOR_BYTE_2 16 23 SUPPORTED_FREQUENCIES_STEREO 24 31 ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_DATA 2 0x3776 1 0 4294967295 DESCRIPTOR 0 31 ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE 2 0x3777 3 0 4294967295 MULTICHANNEL01_ENABLE 0 0 MULTICHANNEL01_MUTE 1 1 MULTICHANNEL01_CHANNEL_ID 4 7 ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE 2 0x3778 3 0 4294967295 MULTICHANNEL23_ENABLE 0 0 MULTICHANNEL23_MUTE 1 1 MULTICHANNEL23_CHANNEL_ID 4 7 ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE 2 0x3779 3 0 4294967295 MULTICHANNEL45_ENABLE 0 0 MULTICHANNEL45_MUTE 1 1 MULTICHANNEL45_CHANNEL_ID 4 7 ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE 2 0x377a 3 0 4294967295 MULTICHANNEL67_ENABLE 0 0 MULTICHANNEL67_MUTE 1 1 MULTICHANNEL67_CHANNEL_ID 4 7 ixAZALIA_F2_CODEC_PIN_CONTROL_LIPSYNC 2 0x377b 2 0 4294967295 VIDEO_LIPSYNC 0 7 AUDIO_LIPSYNC 8 15 ixAZALIA_F2_CODEC_PIN_CONTROL_HBR 2 0x377c 2 0 4294967295 HBR_CAPABLE 0 0 HBR_ENABLE 4 4 ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_INDEX 2 0x3780 1 0 4294967295 SINK_INFO_INDEX 0 7 ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_DATA 2 0x3781 1 0 4294967295 SINK_DATA 0 31 ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE 2 0x3785 3 0 4294967295 MULTICHANNEL1_ENABLE 0 0 MULTICHANNEL1_MUTE 1 1 MULTICHANNEL1_CHANNEL_ID 4 7 ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE 2 0x3786 3 0 4294967295 MULTICHANNEL3_ENABLE 0 0 MULTICHANNEL3_MUTE 1 1 MULTICHANNEL3_CHANNEL_ID 4 7 ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE 2 0x3787 3 0 4294967295 MULTICHANNEL5_ENABLE 0 0 MULTICHANNEL5_MUTE 1 1 MULTICHANNEL5_CHANNEL_ID 4 7 ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE 2 0x3788 3 0 4294967295 MULTICHANNEL7_ENABLE 0 0 MULTICHANNEL7_MUTE 1 1 MULTICHANNEL7_CHANNEL_ID 4 7 ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE 2 0x3789 1 0 4294967295 MULTICHANNEL_MODE 0 0 ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_0 2 0x378a 2 0 4294967295 IEC_60958_CS_MODE 0 1 IEC_60958_CS_SOURCE_NUMBER 2 5 ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1 2 0x378b 4 0 4294967295 IEC_60958_CS_CLOCK_ACCURACY 0 1 IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN 2 2 IEC_60958_CS_WORD_LENGTH 3 6 IEC_60958_CS_WORD_LENGTH_OVRRD_EN 7 7 ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_2 2 0x378c 2 0 4294967295 IEC_60958_CS_SAMPLING_FREQUENCY 0 5 IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN 6 6 ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_3 2 0x378d 2 0 4294967295 IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY 0 3 IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN 4 4 ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4 2 0x378e 4 0 4294967295 IEC_60958_CS_SAMPLING_FREQUENCY_COEFF 0 3 IEC_60958_CS_MPEG_SURROUND_INFO 4 4 IEC_60958_CS_CGMS_A 5 6 IEC_60958_CS_CGMS_A_VALID 7 7 ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_5 2 0x378f 2 0 4294967295 IEC_60958_CS_CHANNEL_NUMBER_L 0 3 IEC_60958_CS_CHANNEL_NUMBER_R 4 7 ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_6 2 0x3790 2 0 4294967295 IEC_60958_CS_CHANNEL_NUMBER_2 0 3 IEC_60958_CS_CHANNEL_NUMBER_3 4 7 ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_7 2 0x3791 2 0 4294967295 IEC_60958_CS_CHANNEL_NUMBER_4 0 3 IEC_60958_CS_CHANNEL_NUMBER_5 4 7 ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_8 2 0x3792 2 0 4294967295 IEC_60958_CS_CHANNEL_NUMBER_6 0 3 IEC_60958_CS_CHANNEL_NUMBER_7 4 7 ixAZALIA_F2_CODEC_PIN_ASSOCIATION_INFO 2 0x3793 1 0 4294967295 ASSOCIATION_INFO 0 31 ixAZALIA_F2_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS 2 0x3797 1 0 4294967295 OUTPUT_ACTIVE 0 0 ixAZALIA_F2_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 2 0x3798 2 0 4294967295 LPIB_SNAPSHOT_LOCK 0 0 CYCLIC_BUFFER_WRAP_COUNT 8 15 ixAZALIA_F2_CODEC_PIN_CONTROL_LPIB 2 0x3799 1 0 4294967295 LPIB 0 31 ixAZALIA_F2_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 2 0x379a 1 0 4294967295 LPIB_TIMER_SNAPSHOT 0 31 ixAZALIA_F2_CODEC_PIN_CONTROL_CODING_TYPE 2 0x379b 1 0 4294967295 CODING_TYPE 0 7 ixAZALIA_F2_CODEC_PIN_CONTROL_FORMAT_CHANGED 2 0x379c 4 0 4294967295 FORMAT_CHANGED 0 0 FORMAT_CHANGED_ACK_UR_ENABLE 1 1 FORMAT_CHANGE_REASON 8 15 FORMAT_CHANGE_RESPONSE 16 23 ixAZALIA_F2_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION 2 0x379d 1 0 4294967295 WIRELESS_DISPLAY_IDENTIFICATION 0 1 ixAZALIA_F2_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE 2 0x379e 2 0 4294967295 REMOTE_KEEP_ALIVE_ENABLE 0 0 REMOTE_KEEP_ALIVE_CAPABILITY 4 4 ixAZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 2 0x3f09 13 0 4294967295 AUDIO_CHANNEL_CAPABILITIES 0 0 INPUT_AMPLIFIER_PRESENT 1 1 OUTPUT_AMPLIFIER_PRESENT 2 2 AMPLIFIER_PARAMETER_OVERRIDE 3 3 STRIPE 5 5 PROCESSING_WIDGET 6 6 UNSOLICITED_RESPONSE_CAPABILITY 7 7 CONNECTION_LIST 8 8 DIGITAL 9 9 POWER_CONTROL 10 10 LR_SWAP 11 11 AUDIO_WIDGET_CAPABILITIES_DELAY 16 19 TYPE 20 23 ixAZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES 2 0x3f0c 11 0 4294967295 IMPEDANCE_SENSE_CAPABLE 0 0 TRIGGER_REQUIRED 1 1 JACK_DETECTION_CAPABILITY 2 2 HEADPHONE_DRIVE_CAPABLE 3 3 OUTPUT_CAPABLE 4 4 INPUT_CAPABLE 5 5 BALANCED_I_O_PINS 6 6 HDMI 7 7 VREF_CONTROL 8 15 EAPD_CAPABLE 16 16 DP 24 24 ixAZALIA_F2_CODEC_PIN_PARAMETER_CONNECTION_LIST_LENGTH 2 0x3f0e 1 0 4294967295 CONNECTION_LIST_LENGTH 0 31 ixAZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT 2 0x6200 6 0 4294967295 NUMBER_OF_CHANNELS 0 3 BITS_PER_SAMPLE 4 6 SAMPLE_BASE_DIVISOR 8 10 SAMPLE_BASE_MULTIPLE 11 13 SAMPLE_BASE_RATE 14 14 STREAM_TYPE 15 15 ixAZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID 2 0x6706 2 0 4294967295 CHANNEL_ID 0 3 STREAM_ID 4 7 ixAZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER 2 0x670d 10 0 4294967295 DIGEN 0 0 V 1 1 VCFG 2 2 PRE 3 3 COPY 4 4 NON_AUDIO 5 5 PRO 6 6 L 7 7 CC 8 14 KEEPALIVE 23 23 ixAZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 2 0x6f09 14 0 4294967295 AUDIO_CHANNEL_CAPABILITIES 0 0 INPUT_AMPLIFIER_PRESENT 1 1 OUTPUT_AMPLIFIER_PRESENT 2 2 AMPLIFIER_PARAMETER_OVERRIDE 3 3 FORMAT_OVERRIDE 4 4 STRIPE 5 5 PROCESSING_WIDGET 6 6 UNSOLICITED_RESPONSE_CAPABILITY 7 7 CONNECTION_LIST 8 8 DIGITAL 9 9 POWER_CONTROL 10 10 LR_SWAP 11 11 AUDIO_WIDGET_CAPABILITIES_DELAY 16 19 TYPE 20 23 ixAZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 2 0x6f0a 2 0 4294967295 AUDIO_RATE_CAPABILITIES 0 11 AUDIO_BIT_CAPABILITIES 16 20 ixAZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS 2 0x6f0b 1 0 4294967295 STREAM_FORMATS 0 31 ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL 2 0x7707 1 0 4294967295 IN_ENABLE 5 5 ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE 2 0x7708 2 0 4294967295 TAG 0 5 ENABLE 7 7 ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_PIN_SENSE 2 0x7709 2 0 4294967295 IMPEDANCE_SENSE 0 30 PRESENCE_DETECT 31 31 ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 2 0x771c 8 0 4294967295 SEQUENCE 0 3 DEFAULT_ASSOCIATION 4 7 MISC 8 11 COLOR 12 15 CONNECTION_TYPE 16 19 DEFAULT_DEVICE 20 23 LOCATION 24 29 PORT_CONNECTIVITY 30 31 ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2 2 0x771d 2 0 4294967295 MISC 0 3 COLOR 4 7 ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3 2 0x771e 2 0 4294967295 CONNECTION_TYPE 0 3 DEFAULT_DEVICE 4 7 ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4 2 0x771f 2 0 4294967295 LOCATION 0 5 PORT_CONNECTIVITY 6 7 ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION 2 0x7771 1 0 4294967295 CHANNEL_ALLOCATION 0 7 ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE 2 0x7777 3 0 4294967295 MULTICHANNEL0_ENABLE 0 0 MULTICHANNEL0_MUTE 1 1 MULTICHANNEL0_CHANNEL_ID 4 7 ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE 2 0x7778 3 0 4294967295 MULTICHANNEL2_ENABLE 0 0 MULTICHANNEL2_MUTE 1 1 MULTICHANNEL2_CHANNEL_ID 4 7 ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE 2 0x7779 3 0 4294967295 MULTICHANNEL4_ENABLE 0 0 MULTICHANNEL4_MUTE 1 1 MULTICHANNEL4_CHANNEL_ID 4 7 ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE 2 0x777a 3 0 4294967295 MULTICHANNEL6_ENABLE 0 0 MULTICHANNEL6_MUTE 1 1 MULTICHANNEL6_CHANNEL_ID 4 7 ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_HBR 2 0x777c 2 0 4294967295 HBR_CAPABLE 0 0 HBR_ENABLE 4 4 ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE 2 0x7785 3 0 4294967295 MULTICHANNEL1_ENABLE 0 0 MULTICHANNEL1_MUTE 1 1 MULTICHANNEL1_CHANNEL_ID 4 7 ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE 2 0x7786 3 0 4294967295 MULTICHANNEL3_ENABLE 0 0 MULTICHANNEL3_MUTE 1 1 MULTICHANNEL3_CHANNEL_ID 4 7 ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE 2 0x7787 3 0 4294967295 MULTICHANNEL5_ENABLE 0 0 MULTICHANNEL5_MUTE 1 1 MULTICHANNEL5_CHANNEL_ID 4 7 ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE 2 0x7788 3 0 4294967295 MULTICHANNEL7_ENABLE 0 0 MULTICHANNEL7_MUTE 1 1 MULTICHANNEL7_CHANNEL_ID 4 7 ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 2 0x7798 2 0 4294967295 LPIB_SNAPSHOT_LOCK 0 0 CYCLIC_BUFFER_WRAP_COUNT 8 15 ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB 2 0x7799 1 0 4294967295 LPIB 0 31 ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 2 0x779a 1 0 4294967295 LPIB_TIMER_SNAPSHOT 0 31 ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL 2 0x779b 4 0 4294967295 INPUT_ACTIVITY 0 0 CHANNEL_LAYOUT 1 2 INPUT_ACTIVITY_UR_ENABLE 4 4 INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE 5 5 ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_INFOFRAME 2 0x779c 4 0 4294967295 CHANNEL_COUNT 0 2 CHANNEL_ALLOCATION 8 15 INFOFRAME_BYTE_5 16 23 INFOFRAME_VALID 31 31 ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_STATUS_L 2 0x779d 1 0 4294967295 CHANNEL_STATUS_L 0 31 ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_STATUS_H 2 0x779e 1 0 4294967295 CHANNEL_STATUS_H 0 31 ixAZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 2 0x7f09 13 0 4294967295 AUDIO_CHANNEL_CAPABILITIES 0 0 INPUT_AMPLIFIER_PRESENT 1 1 OUTPUT_AMPLIFIER_PRESENT 2 2 AMPLIFIER_PARAMETER_OVERRIDE 3 3 STRIPE 5 5 PROCESSING_WIDGET 6 6 UNSOLICITED_RESPONSE_CAPABILITY 7 7 CONNECTION_LIST 8 8 DIGITAL 9 9 POWER_CONTROL 10 10 LR_SWAP 11 11 AUDIO_WIDGET_CAPABILITIES_DELAY 16 19 TYPE 20 23 ixAZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES 2 0x7f0c 11 0 4294967295 IMPEDANCE_SENSE_CAPABLE 0 0 TRIGGER_REQUIRED 1 1 JACK_DETECTION_CAPABILITY 2 2 HEADPHONE_DRIVE_CAPABLE 3 3 OUTPUT_CAPABLE 4 4 INPUT_CAPABLE 5 5 BALANCED_I_O_PINS 6 6 HDMI 7 7 VREF_CONTROL 8 15 EAPD_CAPABLE 16 16 DP 24 24 ixAUDIO_DESCRIPTOR0 2 0x1 4 0 4294967295 MAX_CHANNELS 0 2 SUPPORTED_FREQUENCIES 8 15 DESCRIPTOR_BYTE_2 16 23 SUPPORTED_FREQUENCIES_STEREO 24 31 ixAUDIO_DESCRIPTOR1 2 0x2 4 0 4294967295 MAX_CHANNELS 0 2 SUPPORTED_FREQUENCIES 8 15 DESCRIPTOR_BYTE_2 16 23 SUPPORTED_FREQUENCIES_STEREO 24 31 ixAUDIO_DESCRIPTOR2 2 0x3 4 0 4294967295 MAX_CHANNELS 0 2 SUPPORTED_FREQUENCIES 8 15 DESCRIPTOR_BYTE_2 16 23 SUPPORTED_FREQUENCIES_STEREO 24 31 ixAUDIO_DESCRIPTOR3 2 0x4 4 0 4294967295 MAX_CHANNELS 0 2 SUPPORTED_FREQUENCIES 8 15 DESCRIPTOR_BYTE_2 16 23 SUPPORTED_FREQUENCIES_STEREO 24 31 ixAUDIO_DESCRIPTOR4 2 0x5 4 0 4294967295 MAX_CHANNELS 0 2 SUPPORTED_FREQUENCIES 8 15 DESCRIPTOR_BYTE_2 16 23 SUPPORTED_FREQUENCIES_STEREO 24 31 ixAUDIO_DESCRIPTOR5 2 0x6 4 0 4294967295 MAX_CHANNELS 0 2 SUPPORTED_FREQUENCIES 8 15 DESCRIPTOR_BYTE_2 16 23 SUPPORTED_FREQUENCIES_STEREO 24 31 ixAUDIO_DESCRIPTOR6 2 0x7 4 0 4294967295 MAX_CHANNELS 0 2 SUPPORTED_FREQUENCIES 8 15 DESCRIPTOR_BYTE_2 16 23 SUPPORTED_FREQUENCIES_STEREO 24 31 ixAUDIO_DESCRIPTOR7 2 0x8 4 0 4294967295 MAX_CHANNELS 0 2 SUPPORTED_FREQUENCIES 8 15 DESCRIPTOR_BYTE_2 16 23 SUPPORTED_FREQUENCIES_STEREO 24 31 ixAUDIO_DESCRIPTOR8 2 0x9 4 0 4294967295 MAX_CHANNELS 0 2 SUPPORTED_FREQUENCIES 8 15 DESCRIPTOR_BYTE_2 16 23 SUPPORTED_FREQUENCIES_STEREO 24 31 ixAUDIO_DESCRIPTOR9 2 0xa 4 0 4294967295 MAX_CHANNELS 0 2 SUPPORTED_FREQUENCIES 8 15 DESCRIPTOR_BYTE_2 16 23 SUPPORTED_FREQUENCIES_STEREO 24 31 ixAUDIO_DESCRIPTOR10 2 0xb 4 0 4294967295 MAX_CHANNELS 0 2 SUPPORTED_FREQUENCIES 8 15 DESCRIPTOR_BYTE_2 16 23 SUPPORTED_FREQUENCIES_STEREO 24 31 ixAUDIO_DESCRIPTOR11 2 0xc 4 0 4294967295 MAX_CHANNELS 0 2 SUPPORTED_FREQUENCIES 8 15 DESCRIPTOR_BYTE_2 16 23 SUPPORTED_FREQUENCIES_STEREO 24 31 ixAUDIO_DESCRIPTOR12 2 0xd 4 0 4294967295 MAX_CHANNELS 0 2 SUPPORTED_FREQUENCIES 8 15 DESCRIPTOR_BYTE_2 16 23 SUPPORTED_FREQUENCIES_STEREO 24 31 ixAUDIO_DESCRIPTOR13 2 0xe 4 0 4294967295 MAX_CHANNELS 0 2 SUPPORTED_FREQUENCIES 8 15 DESCRIPTOR_BYTE_2 16 23 SUPPORTED_FREQUENCIES_STEREO 24 31 ixAZALIA_F2_CODEC_PIN_CONTROL_MANUFACTURER_ID 2 0x0 1 0 4294967295 MANUFACTURER_ID 0 15 ixAZALIA_F2_CODEC_PIN_CONTROL_PRODUCT_ID 2 0x1 1 0 4294967295 PRODUCT_ID 0 15 ixAZALIA_F2_CODEC_PIN_CONTROL_SINK_DESCRIPTION_LEN 2 0x2 1 0 4294967295 SINK_DESCRIPTION_LEN 0 7 ixAZALIA_F2_CODEC_PIN_CONTROL_PORTID0 2 0x3 1 0 4294967295 PORTID 0 31 ixAZALIA_F2_CODEC_PIN_CONTROL_PORTID1 2 0x4 1 0 4294967295 PORTID 0 31 ixSINK_DESCRIPTION0 2 0x5 1 0 4294967295 DESCRIPTION 0 7 ixSINK_DESCRIPTION1 2 0x6 1 0 4294967295 DESCRIPTION 0 7 ixSINK_DESCRIPTION2 2 0x7 1 0 4294967295 DESCRIPTION 0 7 ixSINK_DESCRIPTION3 2 0x8 1 0 4294967295 DESCRIPTION 0 7 ixSINK_DESCRIPTION4 2 0x9 1 0 4294967295 DESCRIPTION 0 7 ixSINK_DESCRIPTION5 2 0xa 1 0 4294967295 DESCRIPTION 0 7 ixSINK_DESCRIPTION6 2 0xb 1 0 4294967295 DESCRIPTION 0 7 ixSINK_DESCRIPTION7 2 0xc 1 0 4294967295 DESCRIPTION 0 7 ixSINK_DESCRIPTION8 2 0xd 1 0 4294967295 DESCRIPTION 0 7 ixSINK_DESCRIPTION9 2 0xe 1 0 4294967295 DESCRIPTION 0 7 ixSINK_DESCRIPTION10 2 0xf 1 0 4294967295 DESCRIPTION 0 7 ixSINK_DESCRIPTION11 2 0x10 1 0 4294967295 DESCRIPTION 0 7 ixSINK_DESCRIPTION12 2 0x11 1 0 4294967295 DESCRIPTION 0 7 ixSINK_DESCRIPTION13 2 0x12 1 0 4294967295 DESCRIPTION 0 7 ixSINK_DESCRIPTION14 2 0x13 1 0 4294967295 DESCRIPTION 0 7 ixSINK_DESCRIPTION15 2 0x14 1 0 4294967295 DESCRIPTION 0 7 ixSINK_DESCRIPTION16 2 0x15 1 0 4294967295 DESCRIPTION 0 7 ixSINK_DESCRIPTION17 2 0x16 1 0 4294967295 DESCRIPTION 0 7 ixAZALIA_INPUT_CRC0_CHANNEL0 2 0x0 1 0 4294967295 INPUT_CRC_CHANNEL0 0 31 ixAZALIA_INPUT_CRC0_CHANNEL1 2 0x1 1 0 4294967295 INPUT_CRC_CHANNEL1 0 31 ixAZALIA_INPUT_CRC0_CHANNEL2 2 0x2 1 0 4294967295 INPUT_CRC_CHANNEL2 0 31 ixAZALIA_INPUT_CRC0_CHANNEL3 2 0x3 1 0 4294967295 INPUT_CRC_CHANNEL3 0 31 ixAZALIA_INPUT_CRC0_CHANNEL4 2 0x4 1 0 4294967295 INPUT_CRC_CHANNEL4 0 31 ixAZALIA_INPUT_CRC0_CHANNEL5 2 0x5 1 0 4294967295 INPUT_CRC_CHANNEL5 0 31 ixAZALIA_INPUT_CRC0_CHANNEL6 2 0x6 1 0 4294967295 INPUT_CRC_CHANNEL6 0 31 ixAZALIA_INPUT_CRC0_CHANNEL7 2 0x7 1 0 4294967295 INPUT_CRC_CHANNEL7 0 31 ixAZALIA_INPUT_CRC1_CHANNEL0 2 0x0 1 0 4294967295 INPUT_CRC_CHANNEL0 0 31 ixAZALIA_INPUT_CRC1_CHANNEL1 2 0x1 1 0 4294967295 INPUT_CRC_CHANNEL1 0 31 ixAZALIA_INPUT_CRC1_CHANNEL2 2 0x2 1 0 4294967295 INPUT_CRC_CHANNEL2 0 31 ixAZALIA_INPUT_CRC1_CHANNEL3 2 0x3 1 0 4294967295 INPUT_CRC_CHANNEL3 0 31 ixAZALIA_INPUT_CRC1_CHANNEL4 2 0x4 1 0 4294967295 INPUT_CRC_CHANNEL4 0 31 ixAZALIA_INPUT_CRC1_CHANNEL5 2 0x5 1 0 4294967295 INPUT_CRC_CHANNEL5 0 31 ixAZALIA_INPUT_CRC1_CHANNEL6 2 0x6 1 0 4294967295 INPUT_CRC_CHANNEL6 0 31 ixAZALIA_INPUT_CRC1_CHANNEL7 2 0x7 1 0 4294967295 INPUT_CRC_CHANNEL7 0 31 ixAZALIA_CRC0_CHANNEL0 2 0x0 1 0 4294967295 CRC_CHANNEL0 0 31 ixAZALIA_CRC0_CHANNEL1 2 0x1 1 0 4294967295 CRC_CHANNEL1 0 31 ixAZALIA_CRC0_CHANNEL2 2 0x2 1 0 4294967295 CRC_CHANNEL2 0 31 ixAZALIA_CRC0_CHANNEL3 2 0x3 1 0 4294967295 CRC_CHANNEL3 0 31 ixAZALIA_CRC0_CHANNEL4 2 0x4 1 0 4294967295 CRC_CHANNEL4 0 31 ixAZALIA_CRC0_CHANNEL5 2 0x5 1 0 4294967295 CRC_CHANNEL5 0 31 ixAZALIA_CRC0_CHANNEL6 2 0x6 1 0 4294967295 CRC_CHANNEL6 0 31 ixAZALIA_CRC0_CHANNEL7 2 0x7 1 0 4294967295 CRC_CHANNEL7 0 31 ixAZALIA_CRC1_CHANNEL0 2 0x0 1 0 4294967295 CRC_CHANNEL0 0 31 ixAZALIA_CRC1_CHANNEL1 2 0x1 1 0 4294967295 CRC_CHANNEL1 0 31 ixAZALIA_CRC1_CHANNEL2 2 0x2 1 0 4294967295 CRC_CHANNEL2 0 31 ixAZALIA_CRC1_CHANNEL3 2 0x3 1 0 4294967295 CRC_CHANNEL3 0 31 ixAZALIA_CRC1_CHANNEL4 2 0x4 1 0 4294967295 CRC_CHANNEL4 0 31 ixAZALIA_CRC1_CHANNEL5 2 0x5 1 0 4294967295 CRC_CHANNEL5 0 31 ixAZALIA_CRC1_CHANNEL6 2 0x6 1 0 4294967295 CRC_CHANNEL6 0 31 ixAZALIA_CRC1_CHANNEL7 2 0x7 1 0 4294967295 CRC_CHANNEL7 0 31 ixSEQ00 2 0x0 2 0 4294967295 SEQ_RST0B 0 0 SEQ_RST1B 1 1 ixSEQ01 2 0x1 5 0 4294967295 SEQ_DOT8 0 0 SEQ_SHIFT2 2 2 SEQ_PCLKBY2 3 3 SEQ_SHIFT4 4 4 SEQ_MAXBW 5 5 ixSEQ02 2 0x2 4 0 4294967295 SEQ_MAP0_EN 0 0 SEQ_MAP1_EN 1 1 SEQ_MAP2_EN 2 2 SEQ_MAP3_EN 3 3 ixSEQ03 2 0x3 6 0 4294967295 SEQ_FONT_B1 0 0 SEQ_FONT_B2 1 1 SEQ_FONT_A1 2 2 SEQ_FONT_A2 3 3 SEQ_FONT_B0 4 4 SEQ_FONT_A0 5 5 ixSEQ04 2 0x4 3 0 4294967295 SEQ_256K 1 1 SEQ_ODDEVEN 2 2 SEQ_CHAIN 3 3 ixCRT00 2 0x0 1 0 4294967295 H_TOTAL 0 7 ixCRT01 2 0x1 1 0 4294967295 H_DISP_END 0 7 ixCRT02 2 0x2 1 0 4294967295 H_BLANK_START 0 7 ixCRT03 2 0x3 3 0 4294967295 H_BLANK_END 0 4 H_DE_SKEW 5 6 CR10CR11_R_DIS_B 7 7 ixCRT04 2 0x4 1 0 4294967295 H_SYNC_START 0 7 ixCRT05 2 0x5 3 0 4294967295 H_SYNC_END 0 4 H_SYNC_SKEW 5 6 H_BLANK_END_B5 7 7 ixCRT06 2 0x6 1 0 4294967295 V_TOTAL 0 7 ixCRT07 2 0x7 8 0 4294967295 V_TOTAL_B8 0 0 V_DISP_END_B8 1 1 V_SYNC_START_B8 2 2 V_BLANK_START_B8 3 3 LINE_CMP_B8 4 4 V_TOTAL_B9 5 5 V_DISP_END_B9 6 6 V_SYNC_START_B9 7 7 ixCRT08 2 0x8 2 0 4294967295 ROW_SCAN_START 0 4 BYTE_PAN 5 6 ixCRT09 2 0x9 4 0 4294967295 MAX_ROW_SCAN 0 4 V_BLANK_START_B9 5 5 LINE_CMP_B9 6 6 DOUBLE_CHAR_HEIGHT 7 7 ixCRT0A 2 0xa 2 0 4294967295 CURSOR_START 0 4 CURSOR_DISABLE 5 5 ixCRT0B 2 0xb 2 0 4294967295 CURSOR_END 0 4 CURSOR_SKEW 5 6 ixCRT0C 2 0xc 1 0 4294967295 DISP_START 0 7 ixCRT0D 2 0xd 1 0 4294967295 DISP_START 0 7 ixCRT0E 2 0xe 1 0 4294967295 CURSOR_LOC_HI 0 7 ixCRT0F 2 0xf 1 0 4294967295 CURSOR_LOC_LO 0 7 ixCRT10 2 0x10 1 0 4294967295 V_SYNC_START 0 7 ixCRT11 2 0x11 5 0 4294967295 V_SYNC_END 0 3 V_INTR_CLR 4 4 V_INTR_EN 5 5 SEL5_REFRESH_CYC 6 6 C0T7_WR_ONLY 7 7 ixCRT12 2 0x12 1 0 4294967295 V_DISP_END 0 7 ixCRT13 2 0x13 1 0 4294967295 DISP_PITCH 0 7 ixCRT14 2 0x14 3 0 4294967295 UNDRLN_LOC 0 4 ADDR_CNT_BY4 5 5 DOUBLE_WORD 6 6 ixCRT15 2 0x15 1 0 4294967295 V_BLANK_START 0 7 ixCRT16 2 0x16 1 0 4294967295 V_BLANK_END 0 7 ixCRT17 2 0x17 7 0 4294967295 RA0_AS_A13B 0 0 RA1_AS_A14B 1 1 VCOUNT_BY2 2 2 ADDR_CNT_BY2 3 3 WRAP_A15TOA0 5 5 BYTE_MODE 6 6 CRTC_SYNC_EN 7 7 ixCRT18 2 0x18 1 0 4294967295 LINE_CMP 0 7 ixCRT1E 2 0x1e 1 0 4294967295 GRPH_DEC_RD1 1 1 ixCRT1F 2 0x1f 1 0 4294967295 GRPH_DEC_RD0 0 7 ixCRT22 2 0x22 1 0 4294967295 GRPH_LATCH_DATA 0 7 ixGRA00 2 0x0 4 0 4294967295 GRPH_SET_RESET0 0 0 GRPH_SET_RESET1 1 1 GRPH_SET_RESET2 2 2 GRPH_SET_RESET3 3 3 ixGRA01 2 0x1 4 0 4294967295 GRPH_SET_RESET_ENA0 0 0 GRPH_SET_RESET_ENA1 1 1 GRPH_SET_RESET_ENA2 2 2 GRPH_SET_RESET_ENA3 3 3 ixGRA02 2 0x2 1 0 4294967295 GRPH_CCOMP 0 3 ixGRA03 2 0x3 2 0 4294967295 GRPH_ROTATE 0 2 GRPH_FN_SEL 3 4 ixGRA04 2 0x4 1 0 4294967295 GRPH_RMAP 0 1 ixGRA05 2 0x5 5 0 4294967295 GRPH_WRITE_MODE 0 1 GRPH_READ1 3 3 CGA_ODDEVEN 4 4 GRPH_OES 5 5 GRPH_PACK 6 6 ixGRA06 2 0x6 3 0 4294967295 GRPH_GRAPHICS 0 0 GRPH_ODDEVEN 1 1 GRPH_ADRSEL 2 3 ixGRA07 2 0x7 4 0 4294967295 GRPH_XCARE0 0 0 GRPH_XCARE1 1 1 GRPH_XCARE2 2 2 GRPH_XCARE3 3 3 ixGRA08 2 0x8 1 0 4294967295 GRPH_BMSK 0 7 ixATTR00 2 0x0 1 0 4294967295 ATTR_PAL 0 5 ixATTR01 2 0x1 1 0 4294967295 ATTR_PAL 0 5 ixATTR02 2 0x2 1 0 4294967295 ATTR_PAL 0 5 ixATTR03 2 0x3 1 0 4294967295 ATTR_PAL 0 5 ixATTR04 2 0x4 1 0 4294967295 ATTR_PAL 0 5 ixATTR05 2 0x5 1 0 4294967295 ATTR_PAL 0 5 ixATTR06 2 0x6 1 0 4294967295 ATTR_PAL 0 5 ixATTR07 2 0x7 1 0 4294967295 ATTR_PAL 0 5 ixATTR08 2 0x8 1 0 4294967295 ATTR_PAL 0 5 ixATTR09 2 0x9 1 0 4294967295 ATTR_PAL 0 5 ixATTR0A 2 0xa 1 0 4294967295 ATTR_PAL 0 5 ixATTR0B 2 0xb 1 0 4294967295 ATTR_PAL 0 5 ixATTR0C 2 0xc 1 0 4294967295 ATTR_PAL 0 5 ixATTR0D 2 0xd 1 0 4294967295 ATTR_PAL 0 5 ixATTR0E 2 0xe 1 0 4294967295 ATTR_PAL 0 5 ixATTR0F 2 0xf 1 0 4294967295 ATTR_PAL 0 5 ixATTR10 2 0x10 7 0 4294967295 ATTR_GRPH_MODE 0 0 ATTR_MONO_EN 1 1 ATTR_LGRPH_EN 2 2 ATTR_BLINK_EN 3 3 ATTR_PANTOPONLY 5 5 ATTR_PCLKBY2 6 6 ATTR_CSEL_EN 7 7 ixATTR11 2 0x11 1 0 4294967295 ATTR_OVSC 0 7 ixATTR12 2 0x12 2 0 4294967295 ATTR_MAP_EN 0 3 ATTR_VSMUX 4 5 ixATTR13 2 0x13 1 0 4294967295 ATTR_PPAN 0 3 ixATTR14 2 0x14 2 0 4294967295 ATTR_CSEL1 0 1 ATTR_CSEL2 2 3