4502 ixATTR00 2 0x0 1 0 4294967295 ATTR_PAL 0 5 ixATTR01 2 0x1 1 0 4294967295 ATTR_PAL 0 5 ixATTR02 2 0x2 1 0 4294967295 ATTR_PAL 0 5 ixATTR03 2 0x3 1 0 4294967295 ATTR_PAL 0 5 ixATTR04 2 0x4 1 0 4294967295 ATTR_PAL 0 5 ixATTR05 2 0x5 1 0 4294967295 ATTR_PAL 0 5 ixATTR06 2 0x6 1 0 4294967295 ATTR_PAL 0 5 ixATTR07 2 0x7 1 0 4294967295 ATTR_PAL 0 5 ixATTR08 2 0x8 1 0 4294967295 ATTR_PAL 0 5 ixATTR09 2 0x9 1 0 4294967295 ATTR_PAL 0 5 ixATTR0A 2 0xa 1 0 4294967295 ATTR_PAL 0 5 ixATTR0B 2 0xb 1 0 4294967295 ATTR_PAL 0 5 ixATTR0C 2 0xc 1 0 4294967295 ATTR_PAL 0 5 ixATTR0D 2 0xd 1 0 4294967295 ATTR_PAL 0 5 ixATTR0E 2 0xe 1 0 4294967295 ATTR_PAL 0 5 ixATTR0F 2 0xf 1 0 4294967295 ATTR_PAL 0 5 ixATTR10 2 0x10 7 0 4294967295 ATTR_BLINK_EN 3 3 ATTR_CSEL_EN 7 7 ATTR_GRPH_MODE 0 0 ATTR_LGRPH_EN 2 2 ATTR_MONO_EN 1 1 ATTR_PANTOPONLY 5 5 ATTR_PCLKBY2 6 6 ixATTR11 2 0x11 1 0 4294967295 ATTR_OVSC 0 7 ixATTR12 2 0x12 2 0 4294967295 ATTR_MAP_EN 0 3 ATTR_VSMUX 4 5 ixATTR13 2 0x13 1 0 4294967295 ATTR_PPAN 0 3 ixATTR14 2 0x14 2 0 4294967295 ATTR_CSEL1 0 1 ATTR_CSEL2 2 3 ixAUDIO_DESCRIPTOR0 2 0x1 4 0 4294967295 DESCRIPTOR_BYTE_2 16 23 MAX_CHANNELS 0 2 SUPPORTED_FREQUENCIES 8 15 SUPPORTED_FREQUENCIES_STEREO 24 31 ixAUDIO_DESCRIPTOR10 2 0xb 4 0 4294967295 DESCRIPTOR_BYTE_2 16 23 MAX_CHANNELS 0 2 SUPPORTED_FREQUENCIES 8 15 SUPPORTED_FREQUENCIES_STEREO 24 31 ixAUDIO_DESCRIPTOR1 2 0x2 4 0 4294967295 DESCRIPTOR_BYTE_2 16 23 MAX_CHANNELS 0 2 SUPPORTED_FREQUENCIES 8 15 SUPPORTED_FREQUENCIES_STEREO 24 31 ixAUDIO_DESCRIPTOR11 2 0xc 4 0 4294967295 DESCRIPTOR_BYTE_2 16 23 MAX_CHANNELS 0 2 SUPPORTED_FREQUENCIES 8 15 SUPPORTED_FREQUENCIES_STEREO 24 31 ixAUDIO_DESCRIPTOR12 2 0xd 4 0 4294967295 DESCRIPTOR_BYTE_2 16 23 MAX_CHANNELS 0 2 SUPPORTED_FREQUENCIES 8 15 SUPPORTED_FREQUENCIES_STEREO 24 31 ixAUDIO_DESCRIPTOR13 2 0xe 4 0 4294967295 DESCRIPTOR_BYTE_2 16 23 MAX_CHANNELS 0 2 SUPPORTED_FREQUENCIES 8 15 SUPPORTED_FREQUENCIES_STEREO 24 31 ixAUDIO_DESCRIPTOR2 2 0x3 4 0 4294967295 DESCRIPTOR_BYTE_2 16 23 MAX_CHANNELS 0 2 SUPPORTED_FREQUENCIES 8 15 SUPPORTED_FREQUENCIES_STEREO 24 31 ixAUDIO_DESCRIPTOR3 2 0x4 4 0 4294967295 DESCRIPTOR_BYTE_2 16 23 MAX_CHANNELS 0 2 SUPPORTED_FREQUENCIES 8 15 SUPPORTED_FREQUENCIES_STEREO 24 31 ixAUDIO_DESCRIPTOR4 2 0x5 4 0 4294967295 DESCRIPTOR_BYTE_2 16 23 MAX_CHANNELS 0 2 SUPPORTED_FREQUENCIES 8 15 SUPPORTED_FREQUENCIES_STEREO 24 31 ixAUDIO_DESCRIPTOR5 2 0x6 4 0 4294967295 DESCRIPTOR_BYTE_2 16 23 MAX_CHANNELS 0 2 SUPPORTED_FREQUENCIES 8 15 SUPPORTED_FREQUENCIES_STEREO 24 31 ixAUDIO_DESCRIPTOR6 2 0x7 4 0 4294967295 DESCRIPTOR_BYTE_2 16 23 MAX_CHANNELS 0 2 SUPPORTED_FREQUENCIES 8 15 SUPPORTED_FREQUENCIES_STEREO 24 31 ixAUDIO_DESCRIPTOR7 2 0x8 4 0 4294967295 DESCRIPTOR_BYTE_2 16 23 MAX_CHANNELS 0 2 SUPPORTED_FREQUENCIES 8 15 SUPPORTED_FREQUENCIES_STEREO 24 31 ixAUDIO_DESCRIPTOR8 2 0x9 4 0 4294967295 DESCRIPTOR_BYTE_2 16 23 MAX_CHANNELS 0 2 SUPPORTED_FREQUENCIES 8 15 SUPPORTED_FREQUENCIES_STEREO 24 31 ixAUDIO_DESCRIPTOR9 2 0xa 4 0 4294967295 DESCRIPTOR_BYTE_2 16 23 MAX_CHANNELS 0 2 SUPPORTED_FREQUENCIES 8 15 SUPPORTED_FREQUENCIES_STEREO 24 31 ixAZALIA_CUMULATIVE_LATENCY_COUNT 2 0x3 1 0 4294967295 AZALIA_CUMULATIVE_LATENCY_COUNT 0 31 ixAZALIA_CUMULATIVE_REQUEST_COUNT 2 0x4 1 0 4294967295 AZALIA_CUMULATIVE_REQUEST_COUNT 0 31 ixAZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID 2 0x3 2 0 4294967295 CHANNEL_ID 0 3 STREAM_ID 4 7 ixAZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT 2 0x2 6 0 4294967295 BITS_PER_SAMPLE 4 6 NUMBER_OF_CHANNELS 0 3 SAMPLE_BASE_DIVISOR 8 10 SAMPLE_BASE_MULTIPLE 11 13 SAMPLE_BASE_RATE 14 14 STREAM_TYPE 15 15 ixAZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER 2 0x4 10 0 4294967295 CC 8 14 COPY 4 4 DIGEN 0 0 KEEPALIVE 23 23 L 7 7 NON_AUDIO 5 5 PRE 3 3 PRO 6 6 VCFG 2 2 V 1 1 ixAZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING 2 0x9 1 0 4294967295 PRESENTATION_TIME_EMBEDDING_ENABLE 0 0 ixAZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE 2 0x8 1 0 4294967295 RAMP_RATE 0 7 ixAZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 2 0x1 14 0 4294967295 AMPLIFIER_PARAMETER_OVERRIDE 3 3 AUDIO_CHANNEL_CAPABILITIES 0 0 AUDIO_WIDGET_CAPABILITIES_DELAY 16 19 CONNECTION_LIST 8 8 DIGITAL 9 9 FORMAT_OVERRIDE 4 4 INPUT_AMPLIFIER_PRESENT 1 1 LR_SWAP 11 11 OUTPUT_AMPLIFIER_PRESENT 2 2 POWER_CONTROL 10 10 PROCESSING_WIDGET 6 6 STRIPE 5 5 TYPE 20 23 UNSOLICITED_RESPONSE_CAPABILITY 7 7 ixAZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS 2 0x5 1 0 4294967295 STREAM_FORMATS 0 31 ixAZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 2 0x6 2 0 4294967295 AUDIO_BIT_CAPABILITIES 16 20 AUDIO_RATE_CAPABILITIES 0 11 ixAZALIA_F0_CODEC_CONVERTER_PIN_DEBUG 2 0x0 1 0 4294967295 AZALIA_DEBUG 0 0 ixAZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL 2 0x7 2 0 4294967295 STRIPE_CAPABILITY 20 22 STRIPE_CONTROL 0 1 ixAZALIA_F0_CODEC_PIN_ASSOCIATION_INFO 2 0x62 1 0 4294967295 ASSOCIATION_INFO 0 31 ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 2 0x28 4 0 4294967295 DESCRIPTOR_BYTE_2 16 23 MAX_CHANNELS 0 2 SUPPORTED_FREQUENCIES 8 15 SUPPORTED_FREQUENCIES_STEREO 24 31 ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 2 0x32 3 0 4294967295 DESCRIPTOR_BYTE_2 16 23 MAX_CHANNELS 0 2 SUPPORTED_FREQUENCIES 8 15 ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 2 0x29 3 0 4294967295 DESCRIPTOR_BYTE_2 16 23 MAX_CHANNELS 0 2 SUPPORTED_FREQUENCIES 8 15 ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 2 0x33 3 0 4294967295 DESCRIPTOR_BYTE_2 16 23 MAX_CHANNELS 0 2 SUPPORTED_FREQUENCIES 8 15 ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 2 0x34 3 0 4294967295 DESCRIPTOR_BYTE_2 16 23 MAX_CHANNELS 0 2 SUPPORTED_FREQUENCIES 8 15 ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 2 0x35 3 0 4294967295 DESCRIPTOR_BYTE_2 16 23 MAX_CHANNELS 0 2 SUPPORTED_FREQUENCIES 8 15 ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 2 0x2a 3 0 4294967295 DESCRIPTOR_BYTE_2 16 23 MAX_CHANNELS 0 2 SUPPORTED_FREQUENCIES 8 15 ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 2 0x2b 3 0 4294967295 DESCRIPTOR_BYTE_2 16 23 MAX_CHANNELS 0 2 SUPPORTED_FREQUENCIES 8 15 ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 2 0x2c 3 0 4294967295 DESCRIPTOR_BYTE_2 16 23 MAX_CHANNELS 0 2 SUPPORTED_FREQUENCIES 8 15 ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 2 0x2d 3 0 4294967295 DESCRIPTOR_BYTE_2 16 23 MAX_CHANNELS 0 2 SUPPORTED_FREQUENCIES 8 15 ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 2 0x2e 3 0 4294967295 DESCRIPTOR_BYTE_2 16 23 MAX_CHANNELS 0 2 SUPPORTED_FREQUENCIES 8 15 ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 2 0x2f 3 0 4294967295 DESCRIPTOR_BYTE_2 16 23 MAX_CHANNELS 0 2 SUPPORTED_FREQUENCIES 8 15 ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 2 0x30 3 0 4294967295 DESCRIPTOR_BYTE_2 16 23 MAX_CHANNELS 0 2 SUPPORTED_FREQUENCIES 8 15 ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 2 0x31 3 0 4294967295 DESCRIPTOR_BYTE_2 16 23 MAX_CHANNELS 0 2 SUPPORTED_FREQUENCIES 8 15 ixAZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER 2 0x25 7 0 4294967295 CHANNEL_ALLOCATION 8 15 DOWN_MIX_INHIBIT 31 31 DP_CONNECTION 17 17 EXTRA_CONNECTION_INFO 18 23 HDMI_CONNECTION 16 16 LEVEL_SHIFT 27 30 SPEAKER_ALLOCATION 0 6 ixAZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL 2 0x54 1 0 4294967295 AUDIO_ENABLED 31 31 ixAZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE 2 0x36 12 0 4294967295 MULTICHANNEL01_CHANNEL_ID 4 7 MULTICHANNEL01_ENABLE 0 0 MULTICHANNEL01_MUTE 1 1 MULTICHANNEL23_CHANNEL_ID 12 15 MULTICHANNEL23_ENABLE 8 8 MULTICHANNEL23_MUTE 9 9 MULTICHANNEL45_CHANNEL_ID 20 23 MULTICHANNEL45_ENABLE 16 16 MULTICHANNEL45_MUTE 17 17 MULTICHANNEL67_CHANNEL_ID 28 31 MULTICHANNEL67_ENABLE 24 24 MULTICHANNEL67_MUTE 25 25 ixAZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2 2 0x57 12 0 4294967295 MULTICHANNEL1_CHANNEL_ID 4 7 MULTICHANNEL1_ENABLE 0 0 MULTICHANNEL1_MUTE 1 1 MULTICHANNEL3_CHANNEL_ID 12 15 MULTICHANNEL3_ENABLE 8 8 MULTICHANNEL3_MUTE 9 9 MULTICHANNEL5_CHANNEL_ID 20 23 MULTICHANNEL5_ENABLE 16 16 MULTICHANNEL5_MUTE 17 17 MULTICHANNEL7_CHANNEL_ID 28 31 MULTICHANNEL7_ENABLE 24 24 MULTICHANNEL7_MUTE 25 25 ixAZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE 2 0x58 1 0 4294967295 MULTICHANNEL_MODE 0 0 ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 2 0x56 8 0 4294967295 COLOR 12 15 CONNECTION_TYPE 16 19 DEFAULT_ASSOCIATION 4 7 DEFAULT_DEVICE 20 23 LOCATION 24 29 MISC 8 11 PORT_CONNECTIVITY 30 31 SEQUENCE 0 3 ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR 2 0x38 2 0 4294967295 HBR_CAPABLE 0 0 HBR_ENABLE 4 4 ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC 2 0x37 2 0 4294967295 AUDIO_LIPSYNC 8 15 VIDEO_LIPSYNC 0 7 ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE 2 0x23 1 0 4294967295 IMPEDANCE_SENSE 0 30 ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0 2 0x3a 2 0 4294967295 MANUFACTURER_ID 0 15 PRODUCT_ID 16 31 ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1 2 0x3b 1 0 4294967295 SINK_DESCRIPTION_LEN 0 7 ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2 2 0x3c 1 0 4294967295 PORT_ID0 0 31 ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3 2 0x3d 1 0 4294967295 PORT_ID1 0 31 ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4 2 0x3e 4 0 4294967295 DESCRIPTION0 0 7 DESCRIPTION1 8 15 DESCRIPTION2 16 23 DESCRIPTION3 24 31 ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5 2 0x3f 4 0 4294967295 DESCRIPTION4 0 7 DESCRIPTION5 8 15 DESCRIPTION6 16 23 DESCRIPTION7 24 31 ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6 2 0x40 4 0 4294967295 DESCRIPTION10 16 23 DESCRIPTION11 24 31 DESCRIPTION8 0 7 DESCRIPTION9 8 15 ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7 2 0x41 4 0 4294967295 DESCRIPTION12 0 7 DESCRIPTION13 8 15 DESCRIPTION14 16 23 DESCRIPTION15 24 31 ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8 2 0x42 2 0 4294967295 DESCRIPTION16 0 7 DESCRIPTION17 8 15 ixAZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE 2 0x22 2 0 4294967295 ENABLE 7 7 TAG 0 5 ixAZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 2 0x55 2 0 4294967295 UNSOLICITED_RESPONSE_FORCE 28 28 UNSOLICITED_RESPONSE_PAYLOAD 0 25 ixAZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL 2 0x24 1 0 4294967295 OUT_ENABLE 6 6 ixAZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 2 0x20 13 0 4294967295 AMPLIFIER_PARAMETER_OVERRIDE 3 3 AUDIO_CHANNEL_CAPABILITIES 0 0 AUDIO_WIDGET_CAPABILITIES_DELAY 16 19 CONNECTION_LIST 8 8 DIGITAL 9 9 INPUT_AMPLIFIER_PRESENT 1 1 LR_SWAP 11 11 OUTPUT_AMPLIFIER_PRESENT 2 2 POWER_CONTROL 10 10 PROCESSING_WIDGET 6 6 STRIPE 5 5 TYPE 20 23 UNSOLICITED_RESPONSE_CAPABILITY 7 7 ixAZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES 2 0x21 11 0 4294967295 BALANCED_I_O_PINS 6 6 DP 24 24 EAPD_CAPABLE 16 16 HDMI 7 7 HEADPHONE_DRIVE_CAPABLE 3 3 IMPEDANCE_SENSE_CAPABLE 0 0 INPUT_CAPABLE 5 5 JACK_DETECTION_CAPABILITY 2 2 OUTPUT_CAPABLE 4 4 TRIGGER_REQUIRED 1 1 VREF_CONTROL 8 15 ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0 2 0x59 2 0 4294967295 IEC_60958_CS_MODE 0 1 IEC_60958_CS_SOURCE_NUMBER 2 5 ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1 2 0x5a 4 0 4294967295 IEC_60958_CS_CLOCK_ACCURACY 0 1 IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN 2 2 IEC_60958_CS_WORD_LENGTH 3 6 IEC_60958_CS_WORD_LENGTH_OVRRD_EN 7 7 ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2 2 0x5b 2 0 4294967295 IEC_60958_CS_SAMPLING_FREQUENCY 0 5 IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN 6 6 ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3 2 0x5c 2 0 4294967295 IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY 0 3 IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN 4 4 ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4 2 0x5d 4 0 4294967295 IEC_60958_CS_CGMS_A 5 6 IEC_60958_CS_CGMS_A_VALID 7 7 IEC_60958_CS_MPEG_SURROUND_INFO 4 4 IEC_60958_CS_SAMPLING_FREQUENCY_COEFF 0 3 ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5 2 0x5e 2 0 4294967295 IEC_60958_CS_CHANNEL_NUMBER_L 0 3 IEC_60958_CS_CHANNEL_NUMBER_R 4 7 ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6 2 0x5f 2 0 4294967295 IEC_60958_CS_CHANNEL_NUMBER_2 0 3 IEC_60958_CS_CHANNEL_NUMBER_3 4 7 ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7 2 0x60 2 0 4294967295 IEC_60958_CS_CHANNEL_NUMBER_4 0 3 IEC_60958_CS_CHANNEL_NUMBER_5 4 7 ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8 2 0x61 2 0 4294967295 IEC_60958_CS_CHANNEL_NUMBER_6 0 3 IEC_60958_CS_CHANNEL_NUMBER_7 4 7 ixAZALIA_F2_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID 2 0x2706 2 0 4294967295 CHANNEL_ID 0 3 STREAM_ID 4 7 ixAZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT 2 0x2200 7 0 4294967295 BITS_PER_SAMPLE 4 6 NUMBER_OF_CHANNELS 0 3 SAMPLE_BASE_DIVISOR 8 10 SAMPLE_BASE_MULTIPLE 11 13 SAMPLE_BASE_RATE 14 14 STREAM_TYPE 15 15 STREAM_TYPE_R 15 15 ixAZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER 2 0x270d 10 0 4294967295 CC 8 14 COPY 4 4 DIGEN 0 0 KEEPALIVE 23 23 L 7 7 NON_AUDIO 5 5 PRE 3 3 PRO 6 6 VCFG 2 2 V 1 1 ixAZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_2 2 0x270e 1 0 4294967295 CC 0 6 ixAZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3 2 0x273e 1 0 4294967295 KEEPALIVE 7 7 ixAZALIA_F2_CODEC_CONVERTER_CONTROL_RAMP_RATE 2 0x2770 1 0 4294967295 RAMP_RATE 0 7 ixAZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 2 0x2f09 14 0 4294967295 AMPLIFIER_PARAMETER_OVERRIDE 3 3 AUDIO_CHANNEL_CAPABILITIES 0 0 AUDIO_WIDGET_CAPABILITIES_DELAY 16 19 CONNECTION_LIST 8 8 DIGITAL 9 9 FORMAT_OVERRIDE 4 4 INPUT_AMPLIFIER_PRESENT 1 1 LR_SWAP 11 11 OUTPUT_AMPLIFIER_PRESENT 2 2 POWER_CONTROL 10 10 PROCESSING_WIDGET 6 6 STRIPE 5 5 TYPE 20 23 UNSOLICITED_RESPONSE_CAPABILITY 7 7 ixAZALIA_F2_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS 2 0x2f0b 1 0 4294967295 STREAM_FORMATS 0 31 ixAZALIA_F2_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 2 0x2f0a 2 0 4294967295 AUDIO_BIT_CAPABILITIES 16 20 AUDIO_RATE_CAPABILITIES 0 11 ixAZALIA_F2_CODEC_CONVERTER_STRIPE_CONTROL 2 0x2724 2 0 4294967295 STRIPE_CAPABILITY 20 22 STRIPE_CONTROL 0 1 ixAZALIA_F2_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION 2 0x1770 1 0 4294967295 CONVERTER_SYNCHRONIZATION 0 5 ixAZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE 2 0x1705 4 0 4294967295 CLKSTOPOK 9 9 POWER_STATE_ACT 4 7 POWER_STATE_SET 0 3 POWER_STATE_SETTINGS_RESET 10 10 ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESET 2 0x17ff 1 0 4294967295 CODEC_RESET 0 0 ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID 2 0x1720 4 0 4294967295 SUBSYSTEM_ID_BYTE0 0 7 SUBSYSTEM_ID_BYTE1 8 15 SUBSYSTEM_ID_BYTE2 16 23 SUBSYSTEM_ID_BYTE3 24 31 ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_2 2 0x1721 1 0 4294967295 SUBSYSTEM_ID_BYTE1 0 7 ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_3 2 0x1722 1 0 4294967295 SUBSYSTEM_ID_BYTE2 0 7 ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_4 2 0x1723 1 0 4294967295 SUBSYSTEM_ID_BYTE3 0 7 ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_GROUP_TYPE 2 0x1f05 1 0 4294967295 AZALIA_CODEC_FUNCTION_PARAMETER_GROUP_TYPE 0 31 ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES 2 0x1f0f 3 0 4294967295 AZALIA_CODEC_FUNCTION_PARAMETER_POWER_STATES 0 29 CLKSTOP 30 30 EPSS 31 31 ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS 2 0x1f0b 1 0 4294967295 AZALIA_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS 0 31 ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_SUBORDINATE_NODE_COUNT 2 0x1f04 1 0 4294967295 AZALIA_CODEC_FUNCTION_PARAMETER_SUBORDINATE_NODE_COUNT 0 31 ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES 2 0x1f0a 2 0 4294967295 AUDIO_BIT_CAPABILITIES 16 20 AUDIO_RATE_CAPABILITIES 0 11 ixAZALIA_F2_CODEC_PIN_ASSOCIATION_INFO 2 0x3793 1 0 4294967295 ASSOCIATION_INFO 0 31 ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR 2 0x3776 5 0 4294967295 DESCRIPTOR_BYTE_2 16 23 FORMAT_CODE 3 6 MAX_CHANNELS 0 2 SUPPORTED_FREQUENCIES 8 15 SUPPORTED_FREQUENCIES_STEREO 24 31 ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_DATA 2 0x3776 1 0 4294967295 DESCRIPTOR 0 31 ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_DATA 2 0x3781 1 0 4294967295 SINK_DATA 0 31 ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_INDEX 2 0x3780 1 0 4294967295 SINK_INFO_INDEX 0 7 ixAZALIA_F2_CODEC_PIN_CONTROL_CHANNEL_ALLOCATION 2 0x3771 1 0 4294967295 CHANNEL_ALLOCATION 0 7 ixAZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO 2 0x3772 2 0 4294967295 DOWN_MIX_INHIBIT 7 7 LEVEL_SHIFT 3 6 ixAZALIA_F2_CODEC_PIN_CONTROL_HBR 2 0x377c 2 0 4294967295 HBR_CAPABLE 0 0 HBR_ENABLE 4 4 ixAZALIA_F2_CODEC_PIN_CONTROL_LIPSYNC 2 0x377b 2 0 4294967295 AUDIO_LIPSYNC 8 15 VIDEO_LIPSYNC 0 7 ixAZALIA_F2_CODEC_PIN_CONTROL_MANUFACTURER_ID 2 0x0 1 0 4294967295 MANUFACTURER_ID 0 15 ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE 2 0x3777 3 0 4294967295 MULTICHANNEL01_CHANNEL_ID 4 7 MULTICHANNEL01_ENABLE 0 0 MULTICHANNEL01_MUTE 1 1 ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE 2 0x3785 3 0 4294967295 MULTICHANNEL1_CHANNEL_ID 4 7 MULTICHANNEL1_ENABLE 0 0 MULTICHANNEL1_MUTE 1 1 ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE 2 0x3778 3 0 4294967295 MULTICHANNEL23_CHANNEL_ID 4 7 MULTICHANNEL23_ENABLE 0 0 MULTICHANNEL23_MUTE 1 1 ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE 2 0x3786 3 0 4294967295 MULTICHANNEL3_CHANNEL_ID 4 7 MULTICHANNEL3_ENABLE 0 0 MULTICHANNEL3_MUTE 1 1 ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE 2 0x3779 3 0 4294967295 MULTICHANNEL45_CHANNEL_ID 4 7 MULTICHANNEL45_ENABLE 0 0 MULTICHANNEL45_MUTE 1 1 ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE 2 0x3787 3 0 4294967295 MULTICHANNEL5_CHANNEL_ID 4 7 MULTICHANNEL5_ENABLE 0 0 MULTICHANNEL5_MUTE 1 1 ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE 2 0x377a 3 0 4294967295 MULTICHANNEL67_CHANNEL_ID 4 7 MULTICHANNEL67_ENABLE 0 0 MULTICHANNEL67_MUTE 1 1 ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE 2 0x3788 3 0 4294967295 MULTICHANNEL7_CHANNEL_ID 4 7 MULTICHANNEL7_ENABLE 0 0 MULTICHANNEL7_MUTE 1 1 ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE 2 0x3789 1 0 4294967295 MULTICHANNEL_MODE 0 0 ixAZALIA_F2_CODEC_PIN_CONTROL_PORTID0 2 0x3 1 0 4294967295 PORTID 0 31 ixAZALIA_F2_CODEC_PIN_CONTROL_PORTID1 2 0x4 1 0 4294967295 PORTID 0 31 ixAZALIA_F2_CODEC_PIN_CONTROL_PRODUCT_ID 2 0x1 1 0 4294967295 PRODUCT_ID 0 15 ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 2 0x371c 8 0 4294967295 COLOR 12 15 CONNECTION_TYPE 16 19 DEFAULT_ASSOCIATION 4 7 DEFAULT_DEVICE 20 23 LOCATION 24 29 MISC 8 11 PORT_CONNECTIVITY 30 31 SEQUENCE 0 3 ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2 2 0x371d 2 0 4294967295 COLOR 4 7 MISC 0 3 ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3 2 0x371e 2 0 4294967295 CONNECTION_TYPE 0 3 DEFAULT_DEVICE 4 7 ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4 2 0x371f 2 0 4294967295 LOCATION 0 5 PORT_CONNECTIVITY 6 7 ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONNECTION_LIST_ENTRY 2 0x3702 1 0 4294967295 CONNECTION_LIST_ENTRY 0 31 ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE 2 0x3709 2 0 4294967295 IMPEDANCE_SENSE 0 30 PRESENCE_DETECT 31 31 ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION 2 0x3770 4 0 4294967295 DP_CONNECTION 9 9 EXTRA_CONNECTION_INFO 10 15 HDMI_CONNECTION 8 8 SPEAKER_ALLOCATION 0 6 ixAZALIA_F2_CODEC_PIN_CONTROL_SINK_DESCRIPTION_LEN 2 0x2 1 0 4294967295 SINK_DESCRIPTION_LEN 0 7 ixAZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE 2 0x3708 2 0 4294967295 ENABLE 7 7 TAG 0 5 ixAZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL 2 0x3707 1 0 4294967295 OUT_ENABLE 6 6 ixAZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 2 0x3f09 13 0 4294967295 AMPLIFIER_PARAMETER_OVERRIDE 3 3 AUDIO_CHANNEL_CAPABILITIES 0 0 AUDIO_WIDGET_CAPABILITIES_DELAY 16 19 CONNECTION_LIST 8 8 DIGITAL 9 9 INPUT_AMPLIFIER_PRESENT 1 1 LR_SWAP 11 11 OUTPUT_AMPLIFIER_PRESENT 2 2 POWER_CONTROL 10 10 PROCESSING_WIDGET 6 6 STRIPE 5 5 TYPE 20 23 UNSOLICITED_RESPONSE_CAPABILITY 7 7 ixAZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES 2 0x3f0c 11 0 4294967295 BALANCED_I_O_PINS 6 6 DP 24 24 EAPD_CAPABLE 16 16 HDMI 7 7 HEADPHONE_DRIVE_CAPABLE 3 3 IMPEDANCE_SENSE_CAPABLE 0 0 INPUT_CAPABLE 5 5 JACK_DETECTION_CAPABILITY 2 2 OUTPUT_CAPABLE 4 4 TRIGGER_REQUIRED 1 1 VREF_CONTROL 8 15 ixAZALIA_F2_CODEC_PIN_PARAMETER_CONNECTION_LIST_LENGTH 2 0x3f0e 1 0 4294967295 CONNECTION_LIST_LENGTH 0 31 ixAZALIA_F2_CODEC_ROOT_PARAMETER_REVISION_ID 2 0xf02 1 0 4294967295 AZALIA_CODEC_ROOT_PARAMETER_REVISION_ID 0 31 ixAZALIA_F2_CODEC_ROOT_PARAMETER_SUBORDINATE_NODE_COUNT 2 0xf04 1 0 4294967295 AZALIA_CODEC_ROOT_PARAMETER_SUBORDINATE_NODE_COUNT 0 31 ixAZALIA_F2_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID 2 0xf00 1 0 4294967295 AZALIA_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID 0 31 ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_0 2 0x378a 2 0 4294967295 IEC_60958_CS_MODE 0 1 IEC_60958_CS_SOURCE_NUMBER 2 5 ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1 2 0x378b 4 0 4294967295 IEC_60958_CS_CLOCK_ACCURACY 0 1 IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN 2 2 IEC_60958_CS_WORD_LENGTH 3 6 IEC_60958_CS_WORD_LENGTH_OVRRD_EN 7 7 ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_2 2 0x378c 2 0 4294967295 IEC_60958_CS_SAMPLING_FREQUENCY 0 5 IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN 6 6 ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_3 2 0x378d 2 0 4294967295 IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY 0 3 IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN 4 4 ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4 2 0x378e 4 0 4294967295 IEC_60958_CS_CGMS_A 5 6 IEC_60958_CS_CGMS_A_VALID 7 7 IEC_60958_CS_MPEG_SURROUND_INFO 4 4 IEC_60958_CS_SAMPLING_FREQUENCY_COEFF 0 3 ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_5 2 0x378f 2 0 4294967295 IEC_60958_CS_CHANNEL_NUMBER_L 0 3 IEC_60958_CS_CHANNEL_NUMBER_R 4 7 ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_6 2 0x3790 2 0 4294967295 IEC_60958_CS_CHANNEL_NUMBER_2 0 3 IEC_60958_CS_CHANNEL_NUMBER_3 4 7 ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_7 2 0x3791 2 0 4294967295 IEC_60958_CS_CHANNEL_NUMBER_4 0 3 IEC_60958_CS_CHANNEL_NUMBER_5 4 7 ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_8 2 0x3792 2 0 4294967295 IEC_60958_CS_CHANNEL_NUMBER_6 0 3 IEC_60958_CS_CHANNEL_NUMBER_7 4 7 ixAZALIA_FIFO_SIZE_CONTROL 2 0x0 3 0 4294967295 MAX_FIFO_SIZE 8 14 MAX_LATENCY_SUPPORT 16 23 MIN_FIFO_SIZE 0 6 ixAZALIA_LATENCY_COUNTER_CONTROL 2 0x1 1 0 4294967295 AZALIA_LATENCY_COUNTER_RESET 0 0 ixAZALIA_STREAM_DEBUG 2 0x5 1 0 4294967295 STREAM_DEBUG_DATA 0 31 ixAZALIA_WORSTCASE_LATENCY_COUNT 2 0x2 1 0 4294967295 AZALIA_WORSTCASE_LATENCY_COUNT 0 31 ixCRT00 2 0x0 1 0 4294967295 H_TOTAL 0 7 ixCRT01 2 0x1 1 0 4294967295 H_DISP_END 0 7 ixCRT02 2 0x2 1 0 4294967295 H_BLANK_START 0 7 ixCRT03 2 0x3 3 0 4294967295 CR10CR11_R_DIS_B 7 7 H_BLANK_END 0 4 H_DE_SKEW 5 6 ixCRT04 2 0x4 1 0 4294967295 H_SYNC_START 0 7 ixCRT05 2 0x5 3 0 4294967295 H_BLANK_END_B5 7 7 H_SYNC_END 0 4 H_SYNC_SKEW 5 6 ixCRT06 2 0x6 1 0 4294967295 V_TOTAL 0 7 ixCRT07 2 0x7 8 0 4294967295 LINE_CMP_B8 4 4 V_BLANK_START_B8 3 3 V_DISP_END_B8 1 1 V_DISP_END_B9 6 6 V_SYNC_START_B8 2 2 V_SYNC_START_B9 7 7 V_TOTAL_B8 0 0 V_TOTAL_B9 5 5 ixCRT08 2 0x8 2 0 4294967295 BYTE_PAN 5 6 ROW_SCAN_START 0 4 ixCRT09 2 0x9 4 0 4294967295 DOUBLE_CHAR_HEIGHT 7 7 LINE_CMP_B9 6 6 MAX_ROW_SCAN 0 4 V_BLANK_START_B9 5 5 ixCRT0A 2 0xa 2 0 4294967295 CURSOR_DISABLE 5 5 CURSOR_START 0 4 ixCRT0B 2 0xb 2 0 4294967295 CURSOR_END 0 4 CURSOR_SKEW 5 6 ixCRT0C 2 0xc 1 0 4294967295 DISP_START 0 7 ixCRT0D 2 0xd 1 0 4294967295 DISP_START 0 7 ixCRT0E 2 0xe 1 0 4294967295 CURSOR_LOC_HI 0 7 ixCRT0F 2 0xf 1 0 4294967295 CURSOR_LOC_LO 0 7 ixCRT10 2 0x10 1 0 4294967295 V_SYNC_START 0 7 ixCRT11 2 0x11 5 0 4294967295 C0T7_WR_ONLY 7 7 SEL5_REFRESH_CYC 6 6 V_INTR_CLR 4 4 V_INTR_EN 5 5 V_SYNC_END 0 3 ixCRT12 2 0x12 1 0 4294967295 V_DISP_END 0 7 ixCRT13 2 0x13 1 0 4294967295 DISP_PITCH 0 7 ixCRT14 2 0x14 3 0 4294967295 ADDR_CNT_BY4 5 5 DOUBLE_WORD 6 6 UNDRLN_LOC 0 4 ixCRT15 2 0x15 1 0 4294967295 V_BLANK_START 0 7 ixCRT16 2 0x16 1 0 4294967295 V_BLANK_END 0 7 ixCRT17 2 0x17 7 0 4294967295 ADDR_CNT_BY2 3 3 BYTE_MODE 6 6 CRTC_SYNC_EN 7 7 RA0_AS_A13B 0 0 RA1_AS_A14B 1 1 VCOUNT_BY2 2 2 WRAP_A15TOA0 5 5 ixCRT18 2 0x18 1 0 4294967295 LINE_CMP 0 7 ixCRT1E 2 0x1e 1 0 4294967295 GRPH_DEC_RD1 1 1 ixCRT1F 2 0x1f 1 0 4294967295 GRPH_DEC_RD0 0 7 ixCRT22 2 0x22 1 0 4294967295 GRPH_LATCH_DATA 0 7 ixDCIO_DEBUG10 2 0x10 1 0 4294967295 DCIO_DIGC_DEBUG 0 31 ixDCIO_DEBUG1 2 0x1 22 0 4294967295 DOUT_DCIO_DVO_CLK_TRISTATE 18 18 DOUT_DCIO_DVOCNTL1_A0 15 15 DOUT_DCIO_DVOCNTL1_A0_PREMUX 14 14 DOUT_DCIO_DVOCNTL1_A0_REG 13 13 DOUT_DCIO_DVOCNTL1_EN 20 20 DOUT_DCIO_DVOCNTL1_EN_PREMUX 19 19 DOUT_DCIO_DVOCNTL1_EN_REG 16 16 DOUT_DCIO_DVOCNTL1_MASK_REG 22 22 DOUT_DCIO_DVOCNTL1_MUX 21 21 DOUT_DCIO_DVOCNTL1_SEL0 27 27 DOUT_DCIO_DVOCNTL1_SEL0_PREMUX 26 26 DOUT_DCIO_DVO_ENABLE 23 23 DOUT_DCIO_DVO_HSYNC_TRISTATE 17 17 DOUT_DCIO_DVO_RATE_SEL 25 25 DOUT_DCIO_DVO_VSYNC_TRISTATE 24 24 DOUT_DCIO_MVP_DVOCLK_C 12 12 DOUT_DCIO_MVP_DVOCNTL_A0 6 7 DOUT_DCIO_MVP_DVOCNTL_A0_REG 0 1 DOUT_DCIO_MVP_DVOCNTL_EN 10 11 DOUT_DCIO_MVP_DVOCNTL_EN_REG 4 5 DOUT_DCIO_MVP_DVOCNTL_MASK_REG 2 3 DOUT_DCIO_MVP_DVOCNTL_SEL0 8 9 ixDCIO_DEBUG11 2 0x11 1 0 4294967295 DCIO_DIGD_DEBUG 0 31 ixDCIO_DEBUG12 2 0x12 1 0 4294967295 DCIO_DIGE_DEBUG 0 31 ixDCIO_DEBUG13 2 0x13 1 0 4294967295 DCIO_DIGF_DEBUG 0 31 ixDCIO_DEBUG2 2 0x2 1 0 4294967295 DCIO_DEBUG2 0 31 ixDCIO_DEBUG3 2 0x3 1 0 4294967295 DCIO_DEBUG3 0 31 ixDCIO_DEBUG4 2 0x4 1 0 4294967295 DCIO_DEBUG4 0 31 ixDCIO_DEBUG5 2 0x5 1 0 4294967295 DCIO_DEBUG5 0 31 ixDCIO_DEBUG6 2 0x6 1 0 4294967295 DCIO_DEBUG6 0 31 ixDCIO_DEBUG7 2 0x7 1 0 4294967295 DCIO_DEBUG7 0 31 ixDCIO_DEBUG8 2 0x8 1 0 4294967295 DCIO_DEBUG8 0 31 ixDCIO_DEBUG9 2 0x9 1 0 4294967295 DCIO_DEBUG9 0 31 ixDCIO_DEBUGA 2 0xa 1 0 4294967295 DCIO_DEBUGA 0 31 ixDCIO_DEBUGB 2 0xb 1 0 4294967295 DCIO_DEBUGB 0 31 ixDCIO_DEBUGC 2 0xc 1 0 4294967295 DCIO_DEBUGC 0 31 ixDCIO_DEBUGD 2 0xd 1 0 4294967295 DCIO_DEBUGD 0 31 ixDCIO_DEBUGE 2 0xe 1 0 4294967295 DCIO_DIGA_DEBUG 0 31 ixDCIO_DEBUGF 2 0xf 1 0 4294967295 DCIO_DIGB_DEBUG 0 31 ixDCIO_DEBUG_ID 2 0x0 1 0 4294967295 DCIO_DEBUG_ID 0 31 ixDMIF_DEBUG02_CORE0 2 0x2 3 0 4294967295 DB_DATA 0 15 MC_RDRET_COUNT_EN 16 16 MC_RDRET_COUNTER 17 27 ixDMIF_DEBUG02_CORE1 2 0xa 3 0 4294967295 DB_DATA 0 15 MC_RDRET_COUNT_EN 16 16 MC_RDRET_COUNTER 17 27 ixDP_AUX1_DEBUG_A 2 0x10 1 0 4294967295 DP_AUX1_DEBUG_A 0 31 ixDP_AUX1_DEBUG_B 2 0x11 1 0 4294967295 DP_AUX1_DEBUG_B 0 31 ixDP_AUX1_DEBUG_C 2 0x12 1 0 4294967295 DP_AUX1_DEBUG_C 0 31 ixDP_AUX1_DEBUG_D 2 0x13 1 0 4294967295 DP_AUX1_DEBUG_D 0 31 ixDP_AUX1_DEBUG_E 2 0x14 1 0 4294967295 DP_AUX1_DEBUG_E 0 31 ixDP_AUX1_DEBUG_F 2 0x15 1 0 4294967295 DP_AUX1_DEBUG_F 0 31 ixDP_AUX1_DEBUG_G 2 0x16 1 0 4294967295 DP_AUX1_DEBUG_G 0 31 ixDP_AUX1_DEBUG_H 2 0x17 1 0 4294967295 DP_AUX1_DEBUG_H 0 31 ixDP_AUX1_DEBUG_I 2 0x18 1 0 4294967295 DP_AUX1_DEBUG_I 0 31 ixDP_AUX2_DEBUG_A 2 0x20 1 0 4294967295 DP_AUX2_DEBUG_A 0 31 ixDP_AUX2_DEBUG_B 2 0x21 1 0 4294967295 DP_AUX2_DEBUG_B 0 31 ixDP_AUX2_DEBUG_C 2 0x22 1 0 4294967295 DP_AUX2_DEBUG_C 0 31 ixDP_AUX2_DEBUG_D 2 0x23 1 0 4294967295 DP_AUX2_DEBUG_D 0 31 ixDP_AUX2_DEBUG_E 2 0x24 1 0 4294967295 DP_AUX2_DEBUG_E 0 31 ixDP_AUX2_DEBUG_F 2 0x25 1 0 4294967295 DP_AUX2_DEBUG_F 0 31 ixDP_AUX2_DEBUG_G 2 0x26 1 0 4294967295 DP_AUX2_DEBUG_G 0 31 ixDP_AUX2_DEBUG_H 2 0x27 1 0 4294967295 DP_AUX2_DEBUG_H 0 31 ixDP_AUX2_DEBUG_I 2 0x28 1 0 4294967295 DP_AUX2_DEBUG_I 0 31 ixDP_AUX3_DEBUG_A 2 0x30 1 0 4294967295 DP_AUX3_DEBUG_A 0 31 ixDP_AUX3_DEBUG_B 2 0x31 1 0 4294967295 DP_AUX3_DEBUG_B 0 31 ixDP_AUX3_DEBUG_C 2 0x32 1 0 4294967295 DP_AUX3_DEBUG_C 0 31 ixDP_AUX3_DEBUG_D 2 0x33 1 0 4294967295 DP_AUX3_DEBUG_D 0 31 ixDP_AUX3_DEBUG_E 2 0x34 1 0 4294967295 DP_AUX3_DEBUG_E 0 31 ixDP_AUX3_DEBUG_F 2 0x35 1 0 4294967295 DP_AUX3_DEBUG_F 0 31 ixDP_AUX3_DEBUG_G 2 0x36 1 0 4294967295 DP_AUX3_DEBUG_G 0 31 ixDP_AUX3_DEBUG_H 2 0x37 1 0 4294967295 DP_AUX3_DEBUG_H 0 31 ixDP_AUX3_DEBUG_I 2 0x38 1 0 4294967295 DP_AUX3_DEBUG_I 0 31 ixDP_AUX4_DEBUG_A 2 0x40 1 0 4294967295 DP_AUX4_DEBUG_A 0 31 ixDP_AUX4_DEBUG_B 2 0x41 1 0 4294967295 DP_AUX4_DEBUG_B 0 31 ixDP_AUX4_DEBUG_C 2 0x42 1 0 4294967295 DP_AUX4_DEBUG_C 0 31 ixDP_AUX4_DEBUG_D 2 0x43 1 0 4294967295 DP_AUX4_DEBUG_D 0 31 ixDP_AUX4_DEBUG_E 2 0x44 1 0 4294967295 DP_AUX4_DEBUG_E 0 31 ixDP_AUX4_DEBUG_F 2 0x45 1 0 4294967295 DP_AUX4_DEBUG_F 0 31 ixDP_AUX4_DEBUG_G 2 0x46 1 0 4294967295 DP_AUX4_DEBUG_G 0 31 ixDP_AUX4_DEBUG_H 2 0x47 1 0 4294967295 DP_AUX4_DEBUG_H 0 31 ixDP_AUX4_DEBUG_I 2 0x48 1 0 4294967295 DP_AUX4_DEBUG_I 0 31 ixDP_AUX5_DEBUG_A 2 0x70 1 0 4294967295 DP_AUX5_DEBUG_A 0 31 ixDP_AUX5_DEBUG_B 2 0x71 1 0 4294967295 DP_AUX5_DEBUG_B 0 31 ixDP_AUX5_DEBUG_C 2 0x72 1 0 4294967295 DP_AUX5_DEBUG_C 0 31 ixDP_AUX5_DEBUG_D 2 0x73 1 0 4294967295 DP_AUX5_DEBUG_D 0 31 ixDP_AUX5_DEBUG_E 2 0x74 1 0 4294967295 DP_AUX5_DEBUG_E 0 31 ixDP_AUX5_DEBUG_F 2 0x75 1 0 4294967295 DP_AUX5_DEBUG_F 0 31 ixDP_AUX5_DEBUG_G 2 0x76 1 0 4294967295 DP_AUX5_DEBUG_G 0 31 ixDP_AUX5_DEBUG_H 2 0x77 1 0 4294967295 DP_AUX5_DEBUG_H 0 31 ixDP_AUX5_DEBUG_I 2 0x78 1 0 4294967295 DP_AUX5_DEBUG_I 0 31 ixDP_AUX6_DEBUG_A 2 0x80 1 0 4294967295 DP_AUX6_DEBUG_A 0 31 ixDP_AUX6_DEBUG_B 2 0x81 1 0 4294967295 DP_AUX6_DEBUG_B 0 31 ixDP_AUX6_DEBUG_C 2 0x82 1 0 4294967295 DP_AUX6_DEBUG_C 0 31 ixDP_AUX6_DEBUG_D 2 0x83 1 0 4294967295 DP_AUX6_DEBUG_D 0 31 ixDP_AUX6_DEBUG_E 2 0x84 1 0 4294967295 DP_AUX6_DEBUG_E 0 31 ixDP_AUX6_DEBUG_F 2 0x85 1 0 4294967295 DP_AUX6_DEBUG_F 0 31 ixDP_AUX6_DEBUG_G 2 0x86 1 0 4294967295 DP_AUX6_DEBUG_G 0 31 ixDP_AUX6_DEBUG_H 2 0x87 1 0 4294967295 DP_AUX6_DEBUG_H 0 31 ixDP_AUX6_DEBUG_I 2 0x88 1 0 4294967295 DP_AUX6_DEBUG_I 0 31 ixFMT_DEBUG0 2 0x1 1 0 4294967295 FMT_DEBUG0 0 31 ixFMT_DEBUG1 2 0x2 1 0 4294967295 FMT_DEBUG1 0 31 ixFMT_DEBUG2 2 0x3 1 0 4294967295 FMT_DEBUG2 0 31 ixFMT_DEBUG_ID 2 0x0 1 0 4294967295 FMT_DEBUG_ID 0 31 ixGRA00 2 0x0 4 0 4294967295 GRPH_SET_RESET0 0 0 GRPH_SET_RESET1 1 1 GRPH_SET_RESET2 2 2 GRPH_SET_RESET3 3 3 ixGRA01 2 0x1 4 0 4294967295 GRPH_SET_RESET_ENA0 0 0 GRPH_SET_RESET_ENA1 1 1 GRPH_SET_RESET_ENA2 2 2 GRPH_SET_RESET_ENA3 3 3 ixGRA02 2 0x2 1 0 4294967295 GRPH_CCOMP 0 3 ixGRA03 2 0x3 2 0 4294967295 GRPH_FN_SEL 3 4 GRPH_ROTATE 0 2 ixGRA04 2 0x4 1 0 4294967295 GRPH_RMAP 0 1 ixGRA05 2 0x5 5 0 4294967295 CGA_ODDEVEN 4 4 GRPH_OES 5 5 GRPH_PACK 6 6 GRPH_READ1 3 3 GRPH_WRITE_MODE 0 1 ixGRA06 2 0x6 3 0 4294967295 GRPH_ADRSEL 2 3 GRPH_GRAPHICS 0 0 GRPH_ODDEVEN 1 1 ixGRA07 2 0x7 4 0 4294967295 GRPH_XCARE0 0 0 GRPH_XCARE1 1 1 GRPH_XCARE2 2 2 GRPH_XCARE3 3 3 ixGRA08 2 0x8 1 0 4294967295 GRPH_BMSK 0 7 ixIDDCCIF02_DBG_DCCIF_C 2 0x9 1 0 4294967295 DBG_DCCIF_C 0 31 ixIDDCCIF04_DBG_DCCIF_E 2 0xb 1 0 4294967295 DBG_DCCIF_E 0 31 ixIDDCCIF05_DBG_DCCIF_F 2 0xc 1 0 4294967295 DBG_DCCIF_F 0 31 ixMVP_DEBUG_12 2 0xc 2 0 4294967295 IDEC_MVP_DATA_A_H 0 0 IDEC_MVP_DATA_A 1 24 ixMVP_DEBUG_13 2 0xd 5 0 4294967295 IDED_MVP_DATA_B_H 0 0 IDED_MVP_DATA_B 1 24 IDED_READ_FIFO_ENTRY_DE_B 26 26 IDED_START_READ_B 25 25 IDED_WRITE_ADD_B 27 29 ixMVP_DEBUG_14 2 0xe 15 0 4294967295 IDEE_CRC_PHASE 20 20 IDEE_CRTC1_CNTL_CAPTURE_START_A 19 19 IDEE_READ_ADD 0 2 IDEE_READ_FIFO_DE_B 17 17 IDEE_READ_FIFO_DE 16 16 IDEE_READ_FIFO_ENABLE 18 18 IDEE_READ_FIFO_ENTRY_DE_B 15 15 IDEE_READ_FIFO_ENTRY_DE 14 14 IDEE_START_INCR_WR_A 11 11 IDEE_START_INCR_WR_B 12 12 IDEE_START_READ_B 10 10 IDEE_START_READ 9 9 IDEE_WRITE2FIFO 13 13 IDEE_WRITE_ADD_A 3 5 IDEE_WRITE_ADD_B 6 8 ixMVP_DEBUG_15 2 0xf 2 0 4294967295 IDEF_MVP_ASYNC_FIFO_WDATA 4 31 IDEF_MVP_ASYNC_FIFO_WEN 0 0 ixMVP_DEBUG_16 2 0x10 9 0 4294967295 IDCC_FLOW_CONTROL_OUT 3 3 IDCC_MVP_ASYNC_FIFO_EXCEED_PAUSE_LEVEL 2 2 IDCC_MVP_ASYNC_FIFO_EXCEED_STOP_LEVEL 1 1 IDCC_MVP_ASYNC_FIFO_NUM_ENTRIES 4 11 IDCC_MVP_ASYNC_FIFO_OVERFLOW 12 12 IDCC_MVP_ASYNC_FIFO_READ 0 0 IDCC_MVP_ASYNC_FIFO_UNDERFLOW 13 13 IDCC_MVP_ASYNC_READ_ADDR 16 23 IDCC_MVP_ASYNC_WRITE_ADDR 24 31 ixMVP_DEBUG_17 2 0x11 3 0 4294967295 IDCD_MVP_ASYNC_FIFO_PHASE 1 1 IDCD_MVP_ASYNC_FIFO_READ_DATA 2 31 IDCD_MVP_ASYNC_FIFO_READ 0 0 ixSEQ00 2 0x0 2 0 4294967295 SEQ_RST0B 0 0 SEQ_RST1B 1 1 ixSEQ01 2 0x1 5 0 4294967295 SEQ_DOT8 0 0 SEQ_MAXBW 5 5 SEQ_PCLKBY2 3 3 SEQ_SHIFT2 2 2 SEQ_SHIFT4 4 4 ixSEQ02 2 0x2 4 0 4294967295 SEQ_MAP0_EN 0 0 SEQ_MAP1_EN 1 1 SEQ_MAP2_EN 2 2 SEQ_MAP3_EN 3 3 ixSEQ03 2 0x3 6 0 4294967295 SEQ_FONT_A0 5 5 SEQ_FONT_A1 2 2 SEQ_FONT_A2 3 3 SEQ_FONT_B0 4 4 SEQ_FONT_B1 0 0 SEQ_FONT_B2 1 1 ixSEQ04 2 0x4 3 0 4294967295 SEQ_256K 1 1 SEQ_CHAIN 3 3 SEQ_ODDEVEN 2 2 ixSINK_DESCRIPTION0 2 0x5 1 0 4294967295 DESCRIPTION 0 7 ixSINK_DESCRIPTION10 2 0xf 1 0 4294967295 DESCRIPTION 0 7 ixSINK_DESCRIPTION1 2 0x6 1 0 4294967295 DESCRIPTION 0 7 ixSINK_DESCRIPTION11 2 0x10 1 0 4294967295 DESCRIPTION 0 7 ixSINK_DESCRIPTION12 2 0x11 1 0 4294967295 DESCRIPTION 0 7 ixSINK_DESCRIPTION13 2 0x12 1 0 4294967295 DESCRIPTION 0 7 ixSINK_DESCRIPTION14 2 0x13 1 0 4294967295 DESCRIPTION 0 7 ixSINK_DESCRIPTION15 2 0x14 1 0 4294967295 DESCRIPTION 0 7 ixSINK_DESCRIPTION16 2 0x15 1 0 4294967295 DESCRIPTION 0 7 ixSINK_DESCRIPTION17 2 0x16 1 0 4294967295 DESCRIPTION 0 7 ixSINK_DESCRIPTION2 2 0x7 1 0 4294967295 DESCRIPTION 0 7 ixSINK_DESCRIPTION3 2 0x8 1 0 4294967295 DESCRIPTION 0 7 ixSINK_DESCRIPTION4 2 0x9 1 0 4294967295 DESCRIPTION 0 7 ixSINK_DESCRIPTION5 2 0xa 1 0 4294967295 DESCRIPTION 0 7 ixSINK_DESCRIPTION6 2 0xb 1 0 4294967295 DESCRIPTION 0 7 ixSINK_DESCRIPTION7 2 0xc 1 0 4294967295 DESCRIPTION 0 7 ixSINK_DESCRIPTION8 2 0xd 1 0 4294967295 DESCRIPTION 0 7 ixSINK_DESCRIPTION9 2 0xe 1 0 4294967295 DESCRIPTION 0 7 ixVGADCC_DBG_DCCIF_C 2 0x7e 1 0 4294967295 DBG_DCCIF_C 0 31 mmABM_TEST_DEBUG_DATA 0 0x169f 1 0 4294967295 ABM_TEST_DEBUG_DATA 0 31 mmABM_TEST_DEBUG_INDEX 0 0x169e 2 0 4294967295 ABM_TEST_DEBUG_INDEX 0 7 ABM_TEST_DEBUG_WRITE_EN 8 8 mmAFMT_60958_0 0 0x1c41 10 0 4294967295 AFMT_60958_CS_A 0 0 AFMT_60958_CS_B 1 1 AFMT_60958_CS_CATEGORY_CODE 8 15 AFMT_60958_CS_CHANNEL_NUMBER_L 20 23 AFMT_60958_CS_CLOCK_ACCURACY 28 29 AFMT_60958_CS_C 2 2 AFMT_60958_CS_D 3 5 AFMT_60958_CS_MODE 6 7 AFMT_60958_CS_SAMPLING_FREQUENCY 24 27 AFMT_60958_CS_SOURCE_NUMBER 16 19 mmAFMT_60958_1 0 0x1c42 5 0 4294967295 AFMT_60958_CS_CHANNEL_NUMBER_R 20 23 AFMT_60958_CS_ORIGINAL_SAMPLING_FREQUENCY 4 7 AFMT_60958_CS_WORD_LENGTH 0 3 AFMT_60958_VALID_L 16 16 AFMT_60958_VALID_R 18 18 mmAFMT_60958_2 0 0x1c48 6 0 4294967295 AFMT_60958_CS_CHANNEL_NUMBER_2 0 3 AFMT_60958_CS_CHANNEL_NUMBER_3 4 7 AFMT_60958_CS_CHANNEL_NUMBER_4 8 11 AFMT_60958_CS_CHANNEL_NUMBER_5 12 15 AFMT_60958_CS_CHANNEL_NUMBER_6 16 19 AFMT_60958_CS_CHANNEL_NUMBER_7 20 23 mmAFMT_AUDIO_CRC_CONTROL 0 0x1c43 5 0 4294967295 AFMT_AUDIO_CRC_CH_SEL 12 15 AFMT_AUDIO_CRC_CONT 4 4 AFMT_AUDIO_CRC_COUNT 16 31 AFMT_AUDIO_CRC_EN 0 0 AFMT_AUDIO_CRC_SOURCE 8 8 mmAFMT_AUDIO_CRC_RESULT 0 0x1c49 2 0 4294967295 AFMT_AUDIO_CRC_DONE 0 0 AFMT_AUDIO_CRC 8 31 mmAFMT_AUDIO_DBG_DTO_CNTL 0 0x1c52 4 0 4294967295 AFMT_AUDIO_DTO_DBG_BASE 8 8 AFMT_AUDIO_DTO_DBG_DIV 16 18 AFMT_AUDIO_DTO_DBG_MULTI 12 14 AFMT_AUDIO_DTO_FS_DIV_SEL 0 2 mmAFMT_AUDIO_INFO0 0 0x1c3f 5 0 4294967295 AFMT_AUDIO_INFO_CC 8 10 AFMT_AUDIO_INFO_CHECKSUM 0 7 AFMT_AUDIO_INFO_CHECKSUM_OFFSET 16 23 AFMT_AUDIO_INFO_CT 11 14 AFMT_AUDIO_INFO_CXT 24 28 mmAFMT_AUDIO_INFO1 0 0x1c40 4 0 4294967295 AFMT_AUDIO_INFO_CA 0 7 AFMT_AUDIO_INFO_DM_INH 15 15 AFMT_AUDIO_INFO_LFEPBL 16 17 AFMT_AUDIO_INFO_LSV 11 14 mmAFMT_AUDIO_PACKET_CONTROL 0 0x1c4b 9 0 4294967295 AFMT_60958_CS_UPDATE 26 26 AFMT_AUDIO_CHANNEL_SWAP 24 24 AFMT_AUDIO_FIFO_OVERFLOW_ACK 23 23 AFMT_AUDIO_SAMPLE_SEND 0 0 AFMT_AUDIO_TEST_EN 12 12 AFMT_AUDIO_TEST_MODE 14 14 AFMT_AZ_AUDIO_ENABLE_CHG_ACK 30 30 AFMT_BLANK_TEST_DATA_ON_ENC_ENB 31 31 AFMT_RESET_FIFO_WHEN_AUDIO_DIS 11 11 mmAFMT_AUDIO_PACKET_CONTROL2 0 0x1c17 6 0 4294967295 AFMT_60958_OSF_OVRD 28 28 AFMT_AUDIO_CHANNEL_ENABLE 8 15 AFMT_AUDIO_LAYOUT_OVRD 0 0 AFMT_AUDIO_LAYOUT_SELECT 1 1 AFMT_DP_AUDIO_STREAM_ID 16 23 AFMT_HBR_ENABLE_OVRD 24 24 mmAFMT_AUDIO_SRC_CONTROL 0 0x1c4f 1 0 4294967295 AFMT_AUDIO_SRC_SELECT 0 2 mmAFMT_AVI_INFO0 0 0x1c21 13 0 4294967295 AFMT_AVI_INFO_A 12 12 AFMT_AVI_INFO_B 10 11 AFMT_AVI_INFO_CHECKSUM 0 7 AFMT_AVI_INFO_C 22 23 AFMT_AVI_INFO_EC 28 30 AFMT_AVI_INFO_ITC 31 31 AFMT_AVI_INFO_M 20 21 AFMT_AVI_INFO_PB1_RSVD 15 15 AFMT_AVI_INFO_Q 26 27 AFMT_AVI_INFO_R 16 19 AFMT_AVI_INFO_SC 24 25 AFMT_AVI_INFO_S 8 9 AFMT_AVI_INFO_Y 13 14 mmAFMT_AVI_INFO1 0 0x1c22 6 0 4294967295 AFMT_AVI_INFO_CN 12 13 AFMT_AVI_INFO_PB4_RSVD 7 7 AFMT_AVI_INFO_PR 8 11 AFMT_AVI_INFO_TOP 16 31 AFMT_AVI_INFO_VIC 0 6 AFMT_AVI_INFO_YQ 14 15 mmAFMT_AVI_INFO2 0 0x1c23 2 0 4294967295 AFMT_AVI_INFO_BOTTOM 0 15 AFMT_AVI_INFO_LEFT 16 31 mmAFMT_AVI_INFO3 0 0x1c24 2 0 4294967295 AFMT_AVI_INFO_RIGHT 0 15 AFMT_AVI_INFO_VERSION 24 31 mmAFMT_GENERIC_0 0 0x1c28 4 0 4294967295 AFMT_GENERIC_BYTE0 0 7 AFMT_GENERIC_BYTE1 8 15 AFMT_GENERIC_BYTE2 16 23 AFMT_GENERIC_BYTE3 24 31 mmAFMT_GENERIC_1 0 0x1c29 4 0 4294967295 AFMT_GENERIC_BYTE4 0 7 AFMT_GENERIC_BYTE5 8 15 AFMT_GENERIC_BYTE6 16 23 AFMT_GENERIC_BYTE7 24 31 mmAFMT_GENERIC_2 0 0x1c2a 4 0 4294967295 AFMT_GENERIC_BYTE10 16 23 AFMT_GENERIC_BYTE11 24 31 AFMT_GENERIC_BYTE8 0 7 AFMT_GENERIC_BYTE9 8 15 mmAFMT_GENERIC_3 0 0x1c2b 4 0 4294967295 AFMT_GENERIC_BYTE12 0 7 AFMT_GENERIC_BYTE13 8 15 AFMT_GENERIC_BYTE14 16 23 AFMT_GENERIC_BYTE15 24 31 mmAFMT_GENERIC_4 0 0x1c2c 4 0 4294967295 AFMT_GENERIC_BYTE16 0 7 AFMT_GENERIC_BYTE17 8 15 AFMT_GENERIC_BYTE18 16 23 AFMT_GENERIC_BYTE19 24 31 mmAFMT_GENERIC_5 0 0x1c2d 4 0 4294967295 AFMT_GENERIC_BYTE20 0 7 AFMT_GENERIC_BYTE21 8 15 AFMT_GENERIC_BYTE22 16 23 AFMT_GENERIC_BYTE23 24 31 mmAFMT_GENERIC_6 0 0x1c2e 4 0 4294967295 AFMT_GENERIC_BYTE24 0 7 AFMT_GENERIC_BYTE25 8 15 AFMT_GENERIC_BYTE26 16 23 AFMT_GENERIC_BYTE27 24 31 mmAFMT_GENERIC_7 0 0x1c2f 4 0 4294967295 AFMT_GENERIC_BYTE28 0 7 AFMT_GENERIC_BYTE29 8 15 AFMT_GENERIC_BYTE30 16 23 AFMT_GENERIC_BYTE31 24 31 mmAFMT_GENERIC_HDR 0 0x1c27 4 0 4294967295 AFMT_GENERIC_HB0 0 7 AFMT_GENERIC_HB1 8 15 AFMT_GENERIC_HB2 16 23 AFMT_GENERIC_HB3 24 31 mmAFMT_INFOFRAME_CONTROL0 0 0x1c4d 3 0 4294967295 AFMT_AUDIO_INFO_SOURCE 6 6 AFMT_AUDIO_INFO_UPDATE 7 7 AFMT_MPEG_INFO_UPDATE 10 10 mmAFMT_INTERRUPT_STATUS 0 0x1c14 0 0 4294967295 mmAFMT_ISRC1_0 0 0x1c18 3 0 4294967295 AFMT_ISRC_CONTINUE 6 6 AFMT_ISRC_STATUS 0 2 AFMT_ISRC_VALID 7 7 mmAFMT_ISRC1_1 0 0x1c19 4 0 4294967295 AFMT_UPC_EAN_ISRC0 0 7 AFMT_UPC_EAN_ISRC1 8 15 AFMT_UPC_EAN_ISRC2 16 23 AFMT_UPC_EAN_ISRC3 24 31 mmAFMT_ISRC1_2 0 0x1c1a 4 0 4294967295 AFMT_UPC_EAN_ISRC4 0 7 AFMT_UPC_EAN_ISRC5 8 15 AFMT_UPC_EAN_ISRC6 16 23 AFMT_UPC_EAN_ISRC7 24 31 mmAFMT_ISRC1_3 0 0x1c1b 4 0 4294967295 AFMT_UPC_EAN_ISRC10 16 23 AFMT_UPC_EAN_ISRC11 24 31 AFMT_UPC_EAN_ISRC8 0 7 AFMT_UPC_EAN_ISRC9 8 15 mmAFMT_ISRC1_4 0 0x1c1c 4 0 4294967295 AFMT_UPC_EAN_ISRC12 0 7 AFMT_UPC_EAN_ISRC13 8 15 AFMT_UPC_EAN_ISRC14 16 23 AFMT_UPC_EAN_ISRC15 24 31 mmAFMT_ISRC2_0 0 0x1c1d 4 0 4294967295 AFMT_UPC_EAN_ISRC16 0 7 AFMT_UPC_EAN_ISRC17 8 15 AFMT_UPC_EAN_ISRC18 16 23 AFMT_UPC_EAN_ISRC19 24 31 mmAFMT_ISRC2_1 0 0x1c1e 4 0 4294967295 AFMT_UPC_EAN_ISRC20 0 7 AFMT_UPC_EAN_ISRC21 8 15 AFMT_UPC_EAN_ISRC22 16 23 AFMT_UPC_EAN_ISRC23 24 31 mmAFMT_ISRC2_2 0 0x1c1f 4 0 4294967295 AFMT_UPC_EAN_ISRC24 0 7 AFMT_UPC_EAN_ISRC25 8 15 AFMT_UPC_EAN_ISRC26 16 23 AFMT_UPC_EAN_ISRC27 24 31 mmAFMT_ISRC2_3 0 0x1c20 4 0 4294967295 AFMT_UPC_EAN_ISRC28 0 7 AFMT_UPC_EAN_ISRC29 8 15 AFMT_UPC_EAN_ISRC30 16 23 AFMT_UPC_EAN_ISRC31 24 31 mmAFMT_MPEG_INFO0 0 0x1c25 4 0 4294967295 AFMT_MPEG_INFO_CHECKSUM 0 7 AFMT_MPEG_INFO_MB0 8 15 AFMT_MPEG_INFO_MB1 16 23 AFMT_MPEG_INFO_MB2 24 31 mmAFMT_MPEG_INFO1 0 0x1c26 3 0 4294967295 AFMT_MPEG_INFO_FR 12 12 AFMT_MPEG_INFO_MB3 0 7 AFMT_MPEG_INFO_MF 8 9 mmAFMT_RAMP_CONTROL0 0 0x1c44 2 0 4294967295 AFMT_RAMP_DATA_SIGN 31 31 AFMT_RAMP_MAX_COUNT 0 23 mmAFMT_RAMP_CONTROL1 0 0x1c45 2 0 4294967295 AFMT_AUDIO_TEST_CH_DISABLE 24 31 AFMT_RAMP_MIN_COUNT 0 23 mmAFMT_RAMP_CONTROL2 0 0x1c46 1 0 4294967295 AFMT_RAMP_INC_COUNT 0 23 mmAFMT_RAMP_CONTROL3 0 0x1c47 1 0 4294967295 AFMT_RAMP_DEC_COUNT 0 23 mmAFMT_STATUS 0 0x1c4a 4 0 4294967295 AFMT_AUDIO_ENABLE 4 4 AFMT_AUDIO_FIFO_OVERFLOW 24 24 AFMT_AZ_AUDIO_ENABLE_CHG 30 30 AFMT_AZ_HBR_ENABLE 8 8 mmAFMT_VBI_PACKET_CONTROL 0 0x1c4c 3 0 4294967295 AFMT_GENERIC0_UPDATE 2 2 AFMT_GENERIC2_UPDATE 3 3 AFMT_GENERIC_INDEX 30 31 mmATTRDR 0 0xf0 1 0 4294967295 ATTR_DATA 0 7 mmATTRDW 0 0xf0 1 0 4294967295 ATTR_DATA 0 7 mmATTRX 0 0xf0 2 0 4294967295 ATTR_IDX 0 4 ATTR_PAL_RW_ENB 5 5 mmAUX_ARB_CONTROL 0 0x1882 10 0 4294967295 AUX_ARB_PRIORITY 0 1 AUX_DMCU_DONE_USING_AUX_REG 25 25 AUX_DMCU_PENDING_USE_AUX_REG_REQ 24 24 AUX_DMCU_USE_AUX_REG_REQ 24 24 AUX_NO_QUEUED_LS_GO 10 10 AUX_NO_QUEUED_SW_GO 8 8 AUX_REG_RW_CNTL_STATUS 2 3 AUX_SW_DONE_USING_AUX_REG 17 17 AUX_SW_PENDING_USE_AUX_REG_REQ 16 16 AUX_SW_USE_AUX_REG_REQ 16 16 mmAUX_CONTROL 0 0x1880 11 0 4294967295 AUX_DEGLITCH_EN 29 29 AUX_EN 0 0 AUX_HPD_SEL 20 22 AUX_IGNORE_HPD_DISCON 16 16 AUX_IMPCAL_REQ_EN 24 24 AUX_LS_READ_EN 8 8 AUX_LS_UPDATE_DISABLE 12 12 AUX_MODE_DET_EN 18 18 AUX_TEST_MODE 28 28 SPARE_0 30 30 SPARE_1 31 31 mmAUX_DPHY_RX_CONTROL0 0 0x188a 10 0 4294967295 AUX_RX_ALLOW_BELOW_THRESHOLD_PHASE_DETECT 17 17 AUX_RX_ALLOW_BELOW_THRESHOLD_START 18 18 AUX_RX_ALLOW_BELOW_THRESHOLD_STOP 19 19 AUX_RX_DETECTION_THRESHOLD 28 30 AUX_RX_HALF_SYM_DETECT_LEN 12 13 AUX_RX_PHASE_DETECT_LEN 20 21 AUX_RX_RECEIVE_WINDOW 8 10 AUX_RX_START_WINDOW 4 6 AUX_RX_TIMEOUT_LEN 24 26 AUX_RX_TRANSITION_FILTER_EN 16 16 mmAUX_DPHY_RX_CONTROL1 0 0x188b 1 0 4294967295 AUX_RX_PRECHARGE_SKIP 0 7 mmAUX_DPHY_RX_STATUS 0 0x188d 4 0 4294967295 AUX_RX_HALF_SYM_PERIOD_FRACT 16 20 AUX_RX_HALF_SYM_PERIOD 21 29 AUX_RX_STATE 0 2 AUX_RX_SYNC_VALID_COUNT 8 12 mmAUX_DPHY_TX_CONTROL 0 0x1889 2 0 4294967295 AUX_TX_PRECHARGE_LEN 0 2 AUX_TX_PRECHARGE_SYMBOLS 8 13 mmAUX_DPHY_TX_REF_CONTROL 0 0x1888 3 0 4294967295 AUX_TX_RATE 4 5 AUX_TX_REF_DIV 16 24 AUX_TX_REF_SEL 0 0 mmAUX_DPHY_TX_STATUS 0 0x188c 3 0 4294967295 AUX_TX_ACTIVE 0 0 AUX_TX_HALF_SYM_PERIOD 16 24 AUX_TX_STATE 4 6 mmAUX_GTC_SYNC_CONTROL 0 0x188e 1 0 4294967295 AUX_GTC_SYNC_EN 0 0 mmAUX_GTC_SYNC_DATA 0 0x1890 0 0 4294967295 mmAUX_INTERRUPT_CONTROL 0 0x1883 6 0 4294967295 AUX_LS_DONE_ACK 5 5 AUX_LS_DONE_INT 4 4 AUX_LS_DONE_MASK 6 6 AUX_SW_DONE_ACK 1 1 AUX_SW_DONE_INT 0 0 AUX_SW_DONE_MASK 2 2 mmAUX_LS_DATA 0 0x1887 2 0 4294967295 AUX_LS_DATA 8 15 AUX_LS_INDEX 16 20 mmAUX_LS_STATUS 0 0x1885 20 0 4294967295 AUX_LS_CP_IRQ 29 29 AUX_LS_DONE 0 0 AUX_LS_HPD_DISCON 9 9 AUX_LS_NON_AUX_MODE 11 11 AUX_LS_REPLY_BYTE_COUNT 24 28 AUX_LS_REQ 1 1 AUX_LS_RX_INVALID_START 19 19 AUX_LS_RX_INVALID_STOP 14 14 AUX_LS_RX_MIN_COUNT_VIOL 12 12 AUX_LS_RX_OVERFLOW 8 8 AUX_LS_RX_PARTIAL_BYTE 10 10 AUX_LS_RX_RECV_INVALID_H 22 22 AUX_LS_RX_RECV_INVALID_L 23 23 AUX_LS_RX_RECV_NO_DET 20 20 AUX_LS_RX_SYNC_INVALID_H 18 18 AUX_LS_RX_SYNC_INVALID_L 17 17 AUX_LS_RX_TIMEOUT 7 7 AUX_LS_RX_TIMEOUT_STATE 4 6 AUX_LS_UPDATED_ACK 31 31 AUX_LS_UPDATED 30 30 mmAUXN_IMPCAL 0 0x190c 8 0 4294967295 AUXN_CALOUT_ERROR_AK 10 10 AUXN_CALOUT_ERROR 9 9 AUXN_IMPCAL_CALOUT 8 8 AUXN_IMPCAL_ENABLE 0 0 AUXN_IMPCAL_OVERRIDE_ENABLE 28 28 AUXN_IMPCAL_OVERRIDE 24 27 AUXN_IMPCAL_STEP_DELAY 20 23 AUXN_IMPCAL_VALUE 16 19 mmAUXP_IMPCAL 0 0x190b 8 0 4294967295 AUXP_CALOUT_ERROR_AK 10 10 AUXP_CALOUT_ERROR 9 9 AUXP_IMPCAL_CALOUT 8 8 AUXP_IMPCAL_ENABLE 0 0 AUXP_IMPCAL_OVERRIDE_ENABLE 28 28 AUXP_IMPCAL_OVERRIDE 24 27 AUXP_IMPCAL_STEP_DELAY 20 23 AUXP_IMPCAL_VALUE 16 19 mmAUX_SW_CONTROL 0 0x1881 4 0 4294967295 AUX_LS_READ_TRIG 2 2 AUX_SW_GO 0 0 AUX_SW_START_DELAY 4 7 AUX_SW_WR_BYTES 16 20 mmAUX_SW_DATA 0 0x1886 4 0 4294967295 AUX_SW_AUTOINCREMENT_DISABLE 31 31 AUX_SW_DATA 8 15 AUX_SW_DATA_RW 0 0 AUX_SW_INDEX 16 20 mmAUX_SW_STATUS 0 0x1884 18 0 4294967295 AUX_ARB_STATUS 30 31 AUX_SW_DONE 0 0 AUX_SW_HPD_DISCON 9 9 AUX_SW_NON_AUX_MODE 11 11 AUX_SW_REPLY_BYTE_COUNT 24 28 AUX_SW_REQ 1 1 AUX_SW_RX_INVALID_START 19 19 AUX_SW_RX_INVALID_STOP 14 14 AUX_SW_RX_MIN_COUNT_VIOL 12 12 AUX_SW_RX_OVERFLOW 8 8 AUX_SW_RX_PARTIAL_BYTE 10 10 AUX_SW_RX_RECV_INVALID_H 22 22 AUX_SW_RX_RECV_INVALID_L 23 23 AUX_SW_RX_RECV_NO_DET 20 20 AUX_SW_RX_SYNC_INVALID_H 18 18 AUX_SW_RX_SYNC_INVALID_L 17 17 AUX_SW_RX_TIMEOUT 7 7 AUX_SW_RX_TIMEOUT_STATE 4 6 mmAZALIA_APPLICATION_POSITION_IN_CYCLIC_BUFFER 0 0x17c9 1 0 4294967295 APPLICATION_POSITION_IN_CYCLIC_BUFFER 0 31 mmAZALIA_AUDIO_DTO 0 0x17ba 2 0 4294967295 AZALIA_AUDIO_DTO_MODULE 16 31 AZALIA_AUDIO_DTO_PHASE 0 15 mmAZALIA_AUDIO_DTO_CONTROL 0 0x17bb 1 0 4294967295 AZALIA_AUDIO_FORCE_DTO 8 9 mmAZALIA_BDL_DMA_CONTROL 0 0x17bf 2 0 4294967295 BDL_DMA_ISOCHRONOUS 4 5 BDL_DMA_NON_SNOOP 0 1 mmAZALIA_CONTROLLER_DEBUG 0 0x17cf 1 0 4294967295 CONTROLLER_DEBUG 0 31 mmAZALIA_CORB_DMA_CONTROL 0 0x17c1 2 0 4294967295 CORB_DMA_ISOCHRONOUS 4 4 CORB_DMA_NON_SNOOP 0 0 mmAZALIA_CYCLIC_BUFFER_SYNC 0 0x17ca 1 0 4294967295 CYCLIC_BUFFER_SYNC_ENABLE 0 0 mmAZALIA_DATA_DMA_CONTROL 0 0x17be 4 0 4294967295 AZALIA_IOC_GENERATION_METHOD 16 16 AZALIA_UNDERFLOW_CONTROL 17 17 DATA_DMA_ISOCHRONOUS 4 5 DATA_DMA_NON_SNOOP 0 1 mmAZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL 0 0x17d5 2 0 4294967295 COMPRESSED_CHANNEL_COUNT 4 6 HBR_CHANNEL_COUNT 0 2 mmAZALIA_F0_CODEC_DEBUG 0 0x17df 1 0 4294967295 CODEC_DEBUG 0 31 mmAZALIA_F0_CODEC_ENDPOINT_DATA 0 0x1781 1 0 4294967295 AZALIA_ENDPOINT_REG_DATA 0 31 mmAZALIA_F0_CODEC_ENDPOINT_INDEX 0 0x1780 2 0 4294967295 AZALIA_ENDPOINT_REG_INDEX 0 7 AZALIA_ENDPOINT_REG_WRITE_EN 8 8 mmAZALIA_F0_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION 0 0x17de 1 0 4294967295 CONVERTER_SYNCHRONIZATION 0 5 mmAZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE 0 0x17db 4 0 4294967295 CLKSTOPOK 9 9 POWER_STATE_ACT 4 7 POWER_STATE_SET 0 3 POWER_STATE_SETTINGS_RESET 10 10 mmAZALIA_F0_CODEC_FUNCTION_CONTROL_RESET 0 0x17dc 1 0 4294967295 CODEC_RESET 0 0 mmAZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID 0 0x17dd 4 0 4294967295 SUBSYSTEM_ID_BYTE0 0 7 SUBSYSTEM_ID_BYTE1 8 15 SUBSYSTEM_ID_BYTE2 16 23 SUBSYSTEM_ID_BYTE3 24 31 mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_GROUP_TYPE 0 0x17d7 1 0 4294967295 AZALIA_CODEC_FUNCTION_PARAMETER_GROUP_TYPE 0 31 mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES 0 0x17da 3 0 4294967295 AZALIA_CODEC_FUNCTION_PARAMETER_POWER_STATES 0 29 CLKSTOP 30 30 EPSS 31 31 mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS 0 0x17d9 1 0 4294967295 AZALIA_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS 0 31 mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES 0 0x17d8 2 0 4294967295 AUDIO_BIT_CAPABILITIES 16 20 AUDIO_RATE_CAPABILITIES 0 11 mmAZALIA_F0_CODEC_RESYNC_FIFO_CONTROL 0 0x17d6 1 0 4294967295 RESYNC_FIFO_STARTUP_KEEPOUT_WINDOW 0 5 mmAZALIA_F0_CODEC_ROOT_PARAMETER_REVISION_ID 0 0x17d3 1 0 4294967295 AZALIA_CODEC_ROOT_PARAMETER_REVISION_ID 0 31 mmAZALIA_F0_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID 0 0x17d2 1 0 4294967295 AZALIA_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID 0 31 mmAZALIA_GLOBAL_CAPABILITIES 0 0x17cb 1 0 4294967295 NUMBER_OF_SERIAL_DATA_OUTPUT_SIGNALS 1 2 mmAZALIA_OUTPUT_PAYLOAD_CAPABILITY 0 0x17cc 2 0 4294967295 OUTPUT_PAYLOAD_CAPABILITY 0 15 OUTSTRMPAY 16 31 mmAZALIA_OUTPUT_STREAM_ARBITER_CONTROL 0 0x17cd 2 0 4294967295 LATENCY_HIDING_LEVEL 0 7 SYS_MEM_ACTIVE_ENABLE 8 8 mmAZALIA_RIRB_AND_DP_CONTROL 0 0x17c0 2 0 4294967295 DP_DMA_NON_SNOOP 4 4 RIRB_NON_SNOOP 0 0 mmAZALIA_SCLK_CONTROL 0 0x17bc 1 0 4294967295 AUDIO_SCLK_CONTROL 4 5 mmAZALIA_STREAM_DATA 0 0x17e9 1 0 4294967295 AZALIA_STREAM_REG_DATA 0 31 mmAZALIA_STREAM_INDEX 0 0x17e8 2 0 4294967295 AZALIA_STREAM_REG_INDEX 0 7 AZALIA_STREAM_REG_WRITE_EN 8 8 mmAZALIA_UNDERFLOW_FILLER_SAMPLE 0 0x17bd 1 0 4294967295 AZALIA_UNDERFLOW_FILLER_SAMPLE 0 31 mmAZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA 0 0x1781 0 0 4294967295 mmAZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX 0 0x1780 0 0 4294967295 mmAZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_DATA 0 0x1787 0 0 4294967295 mmAZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_INDEX 0 0x1786 0 0 4294967295 mmAZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_DATA 0 0x178d 0 0 4294967295 mmAZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_INDEX 0 0x178c 0 0 4294967295 mmAZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_DATA 0 0x1793 0 0 4294967295 mmAZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_INDEX 0 0x1792 0 0 4294967295 mmAZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_DATA 0 0x1799 0 0 4294967295 mmAZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_INDEX 0 0x1798 0 0 4294967295 mmAZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_DATA 0 0x179f 0 0 4294967295 mmAZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_INDEX 0 0x179e 0 0 4294967295 mmAZF0STREAM0_AZALIA_STREAM_DATA 0 0x17e9 0 0 4294967295 mmAZF0STREAM0_AZALIA_STREAM_INDEX 0 0x17e8 0 0 4294967295 mmAZF0STREAM1_AZALIA_STREAM_DATA 0 0x17ed 0 0 4294967295 mmAZF0STREAM1_AZALIA_STREAM_INDEX 0 0x17ec 0 0 4294967295 mmAZF0STREAM2_AZALIA_STREAM_DATA 0 0x17f1 0 0 4294967295 mmAZF0STREAM2_AZALIA_STREAM_INDEX 0 0x17f0 0 0 4294967295 mmAZF0STREAM3_AZALIA_STREAM_DATA 0 0x17f5 0 0 4294967295 mmAZF0STREAM3_AZALIA_STREAM_INDEX 0 0x17f4 0 0 4294967295 mmAZF0STREAM4_AZALIA_STREAM_DATA 0 0x17f9 0 0 4294967295 mmAZF0STREAM4_AZALIA_STREAM_INDEX 0 0x17f8 0 0 4294967295 mmAZF0STREAM5_AZALIA_STREAM_DATA 0 0x17fd 0 0 4294967295 mmAZF0STREAM5_AZALIA_STREAM_INDEX 0 0x17fc 0 0 4294967295 mmAZ_TEST_DEBUG_DATA 0 0x17d1 1 0 4294967295 AZ_TEST_DEBUG_DATA 0 31 mmAZ_TEST_DEBUG_INDEX 0 0x17d0 2 0 4294967295 AZ_TEST_DEBUG_INDEX 0 7 AZ_TEST_DEBUG_WRITE_EN 8 8 mmBL1_PWM_ABM_CNTL 0 0x162e 5 0 4294967295 BL1_PWM_AUTO_CALC_FINAL_DUTY_CYCLE_EN 3 3 BL1_PWM_AUTO_UPDATE_CURRENT_ABM_LEVEL_EN 2 2 BL1_PWM_AUTO_UPDATE_CURRENT_ABM_STEP_SIZE 16 31 BL1_PWM_USE_ABM_EN 0 0 BL1_PWM_USE_AMBIENT_LEVEL_EN 1 1 mmBL1_PWM_AMBIENT_LIGHT_LEVEL 0 0x1628 1 0 4294967295 BL1_PWM_AMBIENT_LIGHT_LEVEL 0 16 mmBL1_PWM_BL_UPDATE_SAMPLE_RATE 0 0x162f 5 0 4294967295 ABM1_HGLS_REG_LOCK 31 31 BL1_PWM_BL_UPDATE_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET 16 23 BL1_PWM_BL_UPDATE_RESET_SAMPLE_RATE_FRAME_COUNTER 1 1 BL1_PWM_BL_UPDATE_SAMPLE_RATE_COUNT_EN 0 0 BL1_PWM_BL_UPDATE_SAMPLE_RATE_FRAME_COUNT 8 15 mmBL1_PWM_CURRENT_ABM_LEVEL 0 0x162b 1 0 4294967295 BL1_PWM_CURRENT_ABM_LEVEL 0 16 mmBL1_PWM_FINAL_DUTY_CYCLE 0 0x162c 1 0 4294967295 BL1_PWM_FINAL_DUTY_CYCLE 0 16 mmBL1_PWM_GRP2_REG_LOCK 0 0x1630 6 0 4294967295 BL1_PWM_GRP2_FRAME_START_DISP_SEL 17 19 BL1_PWM_GRP2_IGNORE_MASTER_LOCK_EN 31 31 BL1_PWM_GRP2_READBACK_DB_REG_VALUE_EN 24 24 BL1_PWM_GRP2_REG_LOCK 0 0 BL1_PWM_GRP2_REG_UPDATE_PENDING 8 8 BL1_PWM_GRP2_UPDATE_AT_FRAME_START 16 16 mmBL1_PWM_MINIMUM_DUTY_CYCLE 0 0x162d 1 0 4294967295 BL1_PWM_MINIMUM_DUTY_CYCLE 0 16 mmBL1_PWM_TARGET_ABM_LEVEL 0 0x162a 1 0 4294967295 BL1_PWM_TARGET_ABM_LEVEL 0 16 mmBL1_PWM_USER_LEVEL 0 0x1629 1 0 4294967295 BL1_PWM_USER_LEVEL 0 16 mmBL_PWM_CNTL 0 0x191e 3 0 4294967295 BL_ACTIVE_INT_FRAC_CNT 0 15 BL_PWM_EN 31 31 BL_PWM_FRACTIONAL_EN 30 30 mmBL_PWM_CNTL2 0 0x191f 4 0 4294967295 BL_PWM_OVERRIDE_BL_OUT_ENABLE 30 30 BL_PWM_OVERRIDE_LVTMA_PWRSEQ_EN 31 31 BL_PWM_POST_FRAME_START_DELAY_BEFORE_UPDATE 0 15 DBG_BL_PWM_INPUT_REFCLK_SELECT 28 29 mmBL_PWM_GRP1_REG_LOCK 0 0x1921 6 0 4294967295 BL_PWM_GRP1_FRAME_START_DISP_SEL 17 19 BL_PWM_GRP1_IGNORE_MASTER_LOCK_EN 31 31 BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN 24 24 BL_PWM_GRP1_REG_LOCK 0 0 BL_PWM_GRP1_REG_UPDATE_PENDING 8 8 BL_PWM_GRP1_UPDATE_AT_FRAME_START 16 16 mmBL_PWM_PERIOD_CNTL 0 0x1920 2 0 4294967295 BL_PWM_PERIOD_BITCNT 16 19 BL_PWM_PERIOD 0 15 mmBPHYC_DAC_AUTO_CALIB_CONTROL 0 0x19fe 6 0 4294967295 BPHYC_DAC_CAL_COMPLETE 28 28 BPHYC_DAC_CAL_DACADJ_EN 2 2 BPHYC_DAC_CAL_EN 1 1 BPHYC_DAC_CAL_INITB 0 0 BPHYC_DAC_CAL_MASK 20 22 BPHYC_DAC_CAL_WAIT_ADJUST 4 13 mmBPHYC_DAC_MACRO_CNTL 0 0x19fd 5 0 4294967295 BPHYC_DAC_ANALOG_MONITOR 24 27 BPHYC_DAC_BANDGAP_ADJUSTMENT 16 21 BPHYC_DAC_COREMON 28 28 BPHYC_DAC_WHITE_FINE_CONTROL 8 13 BPHYC_DAC_WHITE_LEVEL 0 1 mmCC_DC_PIPE_DIS 0 0x177f 1 0 4294967295 DC_PIPE_DIS 1 6 mmCC_RCU_DC_AUDIO_PORT_CONNECTIVITY 0 0x17d4 2 0 4294967295 PORT_CONNECTIVITY 0 2 PORT_CONNECTIVITY_OVERRIDE_ENABLE 4 4 mmCOMM_MATRIXA_TRANS_C11_C12 0 0x1a43 2 0 4294967295 COMM_MATRIXA_TRANS_C11 0 15 COMM_MATRIXA_TRANS_C12 16 31 mmCOMM_MATRIXA_TRANS_C13_C14 0 0x1a44 2 0 4294967295 COMM_MATRIXA_TRANS_C13 0 15 COMM_MATRIXA_TRANS_C14 16 31 mmCOMM_MATRIXA_TRANS_C21_C22 0 0x1a45 2 0 4294967295 COMM_MATRIXA_TRANS_C21 0 15 COMM_MATRIXA_TRANS_C22 16 31 mmCOMM_MATRIXA_TRANS_C23_C24 0 0x1a46 2 0 4294967295 COMM_MATRIXA_TRANS_C23 0 15 COMM_MATRIXA_TRANS_C24 16 31 mmCOMM_MATRIXA_TRANS_C31_C32 0 0x1a47 2 0 4294967295 COMM_MATRIXA_TRANS_C31 0 15 COMM_MATRIXA_TRANS_C32 16 31 mmCOMM_MATRIXA_TRANS_C33_C34 0 0x1a48 2 0 4294967295 COMM_MATRIXA_TRANS_C33 0 15 COMM_MATRIXA_TRANS_C34 16 31 mmCOMM_MATRIXB_TRANS_C11_C12 0 0x1a49 2 0 4294967295 COMM_MATRIXB_TRANS_C11 0 15 COMM_MATRIXB_TRANS_C12 16 31 mmCOMM_MATRIXB_TRANS_C13_C14 0 0x1a4a 2 0 4294967295 COMM_MATRIXB_TRANS_C13 0 15 COMM_MATRIXB_TRANS_C14 16 31 mmCOMM_MATRIXB_TRANS_C21_C22 0 0x1a4b 2 0 4294967295 COMM_MATRIXB_TRANS_C21 0 15 COMM_MATRIXB_TRANS_C22 16 31 mmCOMM_MATRIXB_TRANS_C23_C24 0 0x1a4c 2 0 4294967295 COMM_MATRIXB_TRANS_C23 0 15 COMM_MATRIXB_TRANS_C24 16 31 mmCOMM_MATRIXB_TRANS_C31_C32 0 0x1a4d 2 0 4294967295 COMM_MATRIXB_TRANS_C31 0 15 COMM_MATRIXB_TRANS_C32 16 31 mmCOMM_MATRIXB_TRANS_C33_C34 0 0x1a4e 2 0 4294967295 COMM_MATRIXB_TRANS_C33 0 15 COMM_MATRIXB_TRANS_C34 16 31 mmCRTC0_CRTC_3D_STRUCTURE_CONTROL 0 0x1b78 0 0 4294967295 mmCRTC0_CRTC_ALLOW_STOP_OFF_V_CNT 0 0x1bc3 0 0 4294967295 mmCRTC0_CRTC_BLACK_COLOR 0 0x1ba2 0 0 4294967295 mmCRTC0_CRTC_BLANK_CONTROL 0 0x1b9d 0 0 4294967295 mmCRTC0_CRTC_BLANK_DATA_COLOR 0 0x1ba1 0 0 4294967295 mmCRTC0_CRTC_CONTROL 0 0x1b9c 0 0 4294967295 mmCRTC0_CRTC_COUNT_CONTROL 0 0x1ba9 0 0 4294967295 mmCRTC0_CRTC_COUNT_RESET 0 0x1baa 0 0 4294967295 mmCRTC0_CRTC_DCFE_CLOCK_CONTROL 0 0x1b7c 0 0 4294967295 mmCRTC0_CRTC_DOUBLE_BUFFER_CONTROL 0 0x1bb6 0 0 4294967295 mmCRTC0_CRTC_DTMTEST_CNTL 0 0x1b92 0 0 4294967295 mmCRTC0_CRTC_DTMTEST_STATUS_POSITION 0 0x1b93 0 0 4294967295 mmCRTC0_CRTC_FLOW_CONTROL 0 0x1b99 0 0 4294967295 mmCRTC0_CRTC_FORCE_COUNT_NOW_CNTL 0 0x1b98 0 0 4294967295 mmCRTC0_CRTC_GSL_CONTROL 0 0x1b7b 0 0 4294967295 mmCRTC0_CRTC_GSL_VSYNC_GAP 0 0x1b79 0 0 4294967295 mmCRTC0_CRTC_GSL_WINDOW 0 0x1b7a 0 0 4294967295 mmCRTC0_CRTC_H_BLANK_EARLY_NUM 0 0x1b7d 0 0 4294967295 mmCRTC0_CRTC_H_BLANK_START_END 0 0x1b81 0 0 4294967295 mmCRTC0_CRTC_H_SYNC_A 0 0x1b82 0 0 4294967295 mmCRTC0_CRTC_H_SYNC_A_CNTL 0 0x1b83 0 0 4294967295 mmCRTC0_CRTC_H_SYNC_B 0 0x1b84 0 0 4294967295 mmCRTC0_CRTC_H_SYNC_B_CNTL 0 0x1b85 0 0 4294967295 mmCRTC0_CRTC_H_TOTAL 0 0x1b80 0 0 4294967295 mmCRTC0_CRTC_INTERLACE_CONTROL 0 0x1b9e 0 0 4294967295 mmCRTC0_CRTC_INTERLACE_STATUS 0 0x1b9f 0 0 4294967295 mmCRTC0_CRTC_INTERRUPT_CONTROL 0 0x1bb4 0 0 4294967295 mmCRTC0_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE 0 0x1bab 0 0 4294967295 mmCRTC0_CRTC_MASTER_EN 0 0x1bc2 0 0 4294967295 mmCRTC0_CRTC_MVP_INBAND_CNTL_INSERT 0 0x1bbf 0 0 4294967295 mmCRTC0_CRTC_MVP_INBAND_CNTL_INSERT_TIMER 0 0x1bc0 0 0 4294967295 mmCRTC0_CRTC_MVP_STATUS 0 0x1bc1 0 0 4294967295 mmCRTC0_CRTC_NOM_VERT_POSITION 0 0x1ba5 0 0 4294967295 mmCRTC0_CRTC_OVERSCAN_COLOR 0 0x1ba0 0 0 4294967295 mmCRTC0_CRTC_SNAPSHOT_CONTROL 0 0x1bb0 0 0 4294967295 mmCRTC0_CRTC_SNAPSHOT_FRAME 0 0x1bb2 0 0 4294967295 mmCRTC0_CRTC_SNAPSHOT_POSITION 0 0x1bb1 0 0 4294967295 mmCRTC0_CRTC_SNAPSHOT_STATUS 0 0x1baf 0 0 4294967295 mmCRTC0_CRTC_START_LINE_CONTROL 0 0x1bb3 0 0 4294967295 mmCRTC0_CRTC_STATUS 0 0x1ba3 0 0 4294967295 mmCRTC0_CRTC_STATUS_FRAME_COUNT 0 0x1ba6 0 0 4294967295 mmCRTC0_CRTC_STATUS_HV_COUNT 0 0x1ba8 0 0 4294967295 mmCRTC0_CRTC_STATUS_POSITION 0 0x1ba4 0 0 4294967295 mmCRTC0_CRTC_STATUS_VF_COUNT 0 0x1ba7 0 0 4294967295 mmCRTC0_CRTC_STEREO_CONTROL 0 0x1bae 0 0 4294967295 mmCRTC0_CRTC_STEREO_FORCE_NEXT_EYE 0 0x1b9b 0 0 4294967295 mmCRTC0_CRTC_STEREO_STATUS 0 0x1bad 0 0 4294967295 mmCRTC0_CRTC_TEST_DEBUG_DATA 0 0x1bc7 0 0 4294967295 mmCRTC0_CRTC_TEST_DEBUG_INDEX 0 0x1bc6 0 0 4294967295 mmCRTC0_CRTC_TEST_PATTERN_COLOR 0 0x1bbc 0 0 4294967295 mmCRTC0_CRTC_TEST_PATTERN_CONTROL 0 0x1bba 0 0 4294967295 mmCRTC0_CRTC_TEST_PATTERN_PARAMETERS 0 0x1bbb 0 0 4294967295 mmCRTC0_CRTC_TRIGA_CNTL 0 0x1b94 0 0 4294967295 mmCRTC0_CRTC_TRIGA_MANUAL_TRIG 0 0x1b95 0 0 4294967295 mmCRTC0_CRTC_TRIGB_CNTL 0 0x1b96 0 0 4294967295 mmCRTC0_CRTC_TRIGB_MANUAL_TRIG 0 0x1b97 0 0 4294967295 mmCRTC0_CRTC_UPDATE_LOCK 0 0x1bb5 0 0 4294967295 mmCRTC0_CRTC_VBI_END 0 0x1b86 0 0 4294967295 mmCRTC0_CRTC_V_BLANK_START_END 0 0x1b8d 0 0 4294967295 mmCRTC0_CRTC_VERT_SYNC_CONTROL 0 0x1bac 0 0 4294967295 mmCRTC0_CRTC_VGA_PARAMETER_CAPTURE_MODE 0 0x1bb7 0 0 4294967295 mmCRTC0_CRTC_V_SYNC_A 0 0x1b8e 0 0 4294967295 mmCRTC0_CRTC_V_SYNC_A_CNTL 0 0x1b8f 0 0 4294967295 mmCRTC0_CRTC_V_SYNC_B 0 0x1b90 0 0 4294967295 mmCRTC0_CRTC_V_SYNC_B_CNTL 0 0x1b91 0 0 4294967295 mmCRTC0_CRTC_VSYNC_NOM_INT_STATUS 0 0x1b8c 0 0 4294967295 mmCRTC0_CRTC_V_TOTAL 0 0x1b87 0 0 4294967295 mmCRTC0_CRTC_V_TOTAL_CONTROL 0 0x1b8a 0 0 4294967295 mmCRTC0_CRTC_V_TOTAL_INT_STATUS 0 0x1b8b 0 0 4294967295 mmCRTC0_CRTC_V_TOTAL_MAX 0 0x1b89 0 0 4294967295 mmCRTC0_CRTC_V_TOTAL_MIN 0 0x1b88 0 0 4294967295 mmCRTC0_CRTC_V_UPDATE_INT_STATUS 0 0x1bc4 0 0 4294967295 mmCRTC0_DCFE_DBG_SEL 0 0x1b7e 0 0 4294967295 mmCRTC0_DCFE_MEM_LIGHT_SLEEP_CNTL 0 0x1b7f 0 0 4294967295 mmCRTC0_MASTER_UPDATE_LOCK 0 0x1bbd 0 0 4294967295 mmCRTC0_MASTER_UPDATE_MODE 0 0x1bbe 0 0 4294967295 mmCRTC0_PIXEL_RATE_CNTL 0 0x140 6 0 4294967295 CRTC0_ADD_PIXEL 8 8 CRTC0_DISPOUT_ERROR_COUNT 16 27 CRTC0_DISPOUT_FIFO_ERROR 14 15 CRTC0_DROP_PIXEL 9 9 CRTC0_PIXEL_RATE_SOURCE 0 1 DP_DTO0_ENABLE 4 4 mmCRTC1_CRTC_3D_STRUCTURE_CONTROL 0 0x1e78 0 0 4294967295 mmCRTC1_CRTC_ALLOW_STOP_OFF_V_CNT 0 0x1ec3 0 0 4294967295 mmCRTC1_CRTC_BLACK_COLOR 0 0x1ea2 0 0 4294967295 mmCRTC1_CRTC_BLANK_CONTROL 0 0x1e9d 0 0 4294967295 mmCRTC1_CRTC_BLANK_DATA_COLOR 0 0x1ea1 0 0 4294967295 mmCRTC1_CRTC_CONTROL 0 0x1e9c 0 0 4294967295 mmCRTC1_CRTC_COUNT_CONTROL 0 0x1ea9 0 0 4294967295 mmCRTC1_CRTC_COUNT_RESET 0 0x1eaa 0 0 4294967295 mmCRTC1_CRTC_DCFE_CLOCK_CONTROL 0 0x1e7c 0 0 4294967295 mmCRTC1_CRTC_DOUBLE_BUFFER_CONTROL 0 0x1eb6 0 0 4294967295 mmCRTC1_CRTC_DTMTEST_CNTL 0 0x1e92 0 0 4294967295 mmCRTC1_CRTC_DTMTEST_STATUS_POSITION 0 0x1e93 0 0 4294967295 mmCRTC1_CRTC_FLOW_CONTROL 0 0x1e99 0 0 4294967295 mmCRTC1_CRTC_FORCE_COUNT_NOW_CNTL 0 0x1e98 0 0 4294967295 mmCRTC1_CRTC_GSL_CONTROL 0 0x1e7b 0 0 4294967295 mmCRTC1_CRTC_GSL_VSYNC_GAP 0 0x1e79 0 0 4294967295 mmCRTC1_CRTC_GSL_WINDOW 0 0x1e7a 0 0 4294967295 mmCRTC1_CRTC_H_BLANK_EARLY_NUM 0 0x1e7d 0 0 4294967295 mmCRTC1_CRTC_H_BLANK_START_END 0 0x1e81 0 0 4294967295 mmCRTC1_CRTC_H_SYNC_A 0 0x1e82 0 0 4294967295 mmCRTC1_CRTC_H_SYNC_A_CNTL 0 0x1e83 0 0 4294967295 mmCRTC1_CRTC_H_SYNC_B 0 0x1e84 0 0 4294967295 mmCRTC1_CRTC_H_SYNC_B_CNTL 0 0x1e85 0 0 4294967295 mmCRTC1_CRTC_H_TOTAL 0 0x1e80 0 0 4294967295 mmCRTC1_CRTC_INTERLACE_CONTROL 0 0x1e9e 0 0 4294967295 mmCRTC1_CRTC_INTERLACE_STATUS 0 0x1e9f 0 0 4294967295 mmCRTC1_CRTC_INTERRUPT_CONTROL 0 0x1eb4 0 0 4294967295 mmCRTC1_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE 0 0x1eab 0 0 4294967295 mmCRTC1_CRTC_MASTER_EN 0 0x1ec2 0 0 4294967295 mmCRTC1_CRTC_MVP_INBAND_CNTL_INSERT 0 0x1ebf 0 0 4294967295 mmCRTC1_CRTC_MVP_INBAND_CNTL_INSERT_TIMER 0 0x1ec0 0 0 4294967295 mmCRTC1_CRTC_MVP_STATUS 0 0x1ec1 0 0 4294967295 mmCRTC1_CRTC_NOM_VERT_POSITION 0 0x1ea5 0 0 4294967295 mmCRTC1_CRTC_OVERSCAN_COLOR 0 0x1ea0 0 0 4294967295 mmCRTC1_CRTC_SNAPSHOT_CONTROL 0 0x1eb0 0 0 4294967295 mmCRTC1_CRTC_SNAPSHOT_FRAME 0 0x1eb2 0 0 4294967295 mmCRTC1_CRTC_SNAPSHOT_POSITION 0 0x1eb1 0 0 4294967295 mmCRTC1_CRTC_SNAPSHOT_STATUS 0 0x1eaf 0 0 4294967295 mmCRTC1_CRTC_START_LINE_CONTROL 0 0x1eb3 0 0 4294967295 mmCRTC1_CRTC_STATUS 0 0x1ea3 0 0 4294967295 mmCRTC1_CRTC_STATUS_FRAME_COUNT 0 0x1ea6 0 0 4294967295 mmCRTC1_CRTC_STATUS_HV_COUNT 0 0x1ea8 0 0 4294967295 mmCRTC1_CRTC_STATUS_POSITION 0 0x1ea4 0 0 4294967295 mmCRTC1_CRTC_STATUS_VF_COUNT 0 0x1ea7 0 0 4294967295 mmCRTC1_CRTC_STEREO_CONTROL 0 0x1eae 0 0 4294967295 mmCRTC1_CRTC_STEREO_FORCE_NEXT_EYE 0 0x1e9b 0 0 4294967295 mmCRTC1_CRTC_STEREO_STATUS 0 0x1ead 0 0 4294967295 mmCRTC1_CRTC_TEST_DEBUG_DATA 0 0x1ec7 0 0 4294967295 mmCRTC1_CRTC_TEST_DEBUG_INDEX 0 0x1ec6 0 0 4294967295 mmCRTC1_CRTC_TEST_PATTERN_COLOR 0 0x1ebc 0 0 4294967295 mmCRTC1_CRTC_TEST_PATTERN_CONTROL 0 0x1eba 0 0 4294967295 mmCRTC1_CRTC_TEST_PATTERN_PARAMETERS 0 0x1ebb 0 0 4294967295 mmCRTC1_CRTC_TRIGA_CNTL 0 0x1e94 0 0 4294967295 mmCRTC1_CRTC_TRIGA_MANUAL_TRIG 0 0x1e95 0 0 4294967295 mmCRTC1_CRTC_TRIGB_CNTL 0 0x1e96 0 0 4294967295 mmCRTC1_CRTC_TRIGB_MANUAL_TRIG 0 0x1e97 0 0 4294967295 mmCRTC1_CRTC_UPDATE_LOCK 0 0x1eb5 0 0 4294967295 mmCRTC1_CRTC_VBI_END 0 0x1e86 0 0 4294967295 mmCRTC1_CRTC_V_BLANK_START_END 0 0x1e8d 0 0 4294967295 mmCRTC1_CRTC_VERT_SYNC_CONTROL 0 0x1eac 0 0 4294967295 mmCRTC1_CRTC_VGA_PARAMETER_CAPTURE_MODE 0 0x1eb7 0 0 4294967295 mmCRTC1_CRTC_V_SYNC_A 0 0x1e8e 0 0 4294967295 mmCRTC1_CRTC_V_SYNC_A_CNTL 0 0x1e8f 0 0 4294967295 mmCRTC1_CRTC_V_SYNC_B 0 0x1e90 0 0 4294967295 mmCRTC1_CRTC_V_SYNC_B_CNTL 0 0x1e91 0 0 4294967295 mmCRTC1_CRTC_VSYNC_NOM_INT_STATUS 0 0x1e8c 0 0 4294967295 mmCRTC1_CRTC_V_TOTAL 0 0x1e87 0 0 4294967295 mmCRTC1_CRTC_V_TOTAL_CONTROL 0 0x1e8a 0 0 4294967295 mmCRTC1_CRTC_V_TOTAL_INT_STATUS 0 0x1e8b 0 0 4294967295 mmCRTC1_CRTC_V_TOTAL_MAX 0 0x1e89 0 0 4294967295 mmCRTC1_CRTC_V_TOTAL_MIN 0 0x1e88 0 0 4294967295 mmCRTC1_CRTC_V_UPDATE_INT_STATUS 0 0x1ec4 0 0 4294967295 mmCRTC1_DCFE_DBG_SEL 0 0x1e7e 0 0 4294967295 mmCRTC1_DCFE_MEM_LIGHT_SLEEP_CNTL 0 0x1e7f 0 0 4294967295 mmCRTC1_MASTER_UPDATE_LOCK 0 0x1ebd 0 0 4294967295 mmCRTC1_MASTER_UPDATE_MODE 0 0x1ebe 0 0 4294967295 mmCRTC1_PIXEL_RATE_CNTL 0 0x144 6 0 4294967295 CRTC1_ADD_PIXEL 8 8 CRTC1_DISPOUT_ERROR_COUNT 16 27 CRTC1_DISPOUT_FIFO_ERROR 14 15 CRTC1_DROP_PIXEL 9 9 CRTC1_PIXEL_RATE_SOURCE 0 1 DP_DTO1_ENABLE 4 4 mmCRTC2_CRTC_3D_STRUCTURE_CONTROL 0 0x4178 0 0 4294967295 mmCRTC2_CRTC_ALLOW_STOP_OFF_V_CNT 0 0x41c3 0 0 4294967295 mmCRTC2_CRTC_BLACK_COLOR 0 0x41a2 0 0 4294967295 mmCRTC2_CRTC_BLANK_CONTROL 0 0x419d 0 0 4294967295 mmCRTC2_CRTC_BLANK_DATA_COLOR 0 0x41a1 0 0 4294967295 mmCRTC2_CRTC_CONTROL 0 0x419c 0 0 4294967295 mmCRTC2_CRTC_COUNT_CONTROL 0 0x41a9 0 0 4294967295 mmCRTC2_CRTC_COUNT_RESET 0 0x41aa 0 0 4294967295 mmCRTC2_CRTC_DCFE_CLOCK_CONTROL 0 0x417c 0 0 4294967295 mmCRTC2_CRTC_DOUBLE_BUFFER_CONTROL 0 0x41b6 0 0 4294967295 mmCRTC2_CRTC_DTMTEST_CNTL 0 0x4192 0 0 4294967295 mmCRTC2_CRTC_DTMTEST_STATUS_POSITION 0 0x4193 0 0 4294967295 mmCRTC2_CRTC_FLOW_CONTROL 0 0x4199 0 0 4294967295 mmCRTC2_CRTC_FORCE_COUNT_NOW_CNTL 0 0x4198 0 0 4294967295 mmCRTC2_CRTC_GSL_CONTROL 0 0x417b 0 0 4294967295 mmCRTC2_CRTC_GSL_VSYNC_GAP 0 0x4179 0 0 4294967295 mmCRTC2_CRTC_GSL_WINDOW 0 0x417a 0 0 4294967295 mmCRTC2_CRTC_H_BLANK_EARLY_NUM 0 0x417d 0 0 4294967295 mmCRTC2_CRTC_H_BLANK_START_END 0 0x4181 0 0 4294967295 mmCRTC2_CRTC_H_SYNC_A 0 0x4182 0 0 4294967295 mmCRTC2_CRTC_H_SYNC_A_CNTL 0 0x4183 0 0 4294967295 mmCRTC2_CRTC_H_SYNC_B 0 0x4184 0 0 4294967295 mmCRTC2_CRTC_H_SYNC_B_CNTL 0 0x4185 0 0 4294967295 mmCRTC2_CRTC_H_TOTAL 0 0x4180 0 0 4294967295 mmCRTC2_CRTC_INTERLACE_CONTROL 0 0x419e 0 0 4294967295 mmCRTC2_CRTC_INTERLACE_STATUS 0 0x419f 0 0 4294967295 mmCRTC2_CRTC_INTERRUPT_CONTROL 0 0x41b4 0 0 4294967295 mmCRTC2_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE 0 0x41ab 0 0 4294967295 mmCRTC2_CRTC_MASTER_EN 0 0x41c2 0 0 4294967295 mmCRTC2_CRTC_MVP_INBAND_CNTL_INSERT 0 0x41bf 0 0 4294967295 mmCRTC2_CRTC_MVP_INBAND_CNTL_INSERT_TIMER 0 0x41c0 0 0 4294967295 mmCRTC2_CRTC_MVP_STATUS 0 0x41c1 0 0 4294967295 mmCRTC2_CRTC_NOM_VERT_POSITION 0 0x41a5 0 0 4294967295 mmCRTC2_CRTC_OVERSCAN_COLOR 0 0x41a0 0 0 4294967295 mmCRTC2_CRTC_SNAPSHOT_CONTROL 0 0x41b0 0 0 4294967295 mmCRTC2_CRTC_SNAPSHOT_FRAME 0 0x41b2 0 0 4294967295 mmCRTC2_CRTC_SNAPSHOT_POSITION 0 0x41b1 0 0 4294967295 mmCRTC2_CRTC_SNAPSHOT_STATUS 0 0x41af 0 0 4294967295 mmCRTC2_CRTC_START_LINE_CONTROL 0 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4294967295 CRTC2_ADD_PIXEL 8 8 CRTC2_DISPOUT_ERROR_COUNT 16 27 CRTC2_DISPOUT_FIFO_ERROR 14 15 CRTC2_DROP_PIXEL 9 9 CRTC2_PIXEL_RATE_SOURCE 0 1 DP_DTO2_ENABLE 4 4 mmCRTC3_CRTC_3D_STRUCTURE_CONTROL 0 0x4478 0 0 4294967295 mmCRTC3_CRTC_ALLOW_STOP_OFF_V_CNT 0 0x44c3 0 0 4294967295 mmCRTC3_CRTC_BLACK_COLOR 0 0x44a2 0 0 4294967295 mmCRTC3_CRTC_BLANK_CONTROL 0 0x449d 0 0 4294967295 mmCRTC3_CRTC_BLANK_DATA_COLOR 0 0x44a1 0 0 4294967295 mmCRTC3_CRTC_CONTROL 0 0x449c 0 0 4294967295 mmCRTC3_CRTC_COUNT_CONTROL 0 0x44a9 0 0 4294967295 mmCRTC3_CRTC_COUNT_RESET 0 0x44aa 0 0 4294967295 mmCRTC3_CRTC_DCFE_CLOCK_CONTROL 0 0x447c 0 0 4294967295 mmCRTC3_CRTC_DOUBLE_BUFFER_CONTROL 0 0x44b6 0 0 4294967295 mmCRTC3_CRTC_DTMTEST_CNTL 0 0x4492 0 0 4294967295 mmCRTC3_CRTC_DTMTEST_STATUS_POSITION 0 0x4493 0 0 4294967295 mmCRTC3_CRTC_FLOW_CONTROL 0 0x4499 0 0 4294967295 mmCRTC3_CRTC_FORCE_COUNT_NOW_CNTL 0 0x4498 0 0 4294967295 mmCRTC3_CRTC_GSL_CONTROL 0 0x447b 0 0 4294967295 mmCRTC3_CRTC_GSL_VSYNC_GAP 0 0x4479 0 0 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0x44b0 0 0 4294967295 mmCRTC3_CRTC_SNAPSHOT_FRAME 0 0x44b2 0 0 4294967295 mmCRTC3_CRTC_SNAPSHOT_POSITION 0 0x44b1 0 0 4294967295 mmCRTC3_CRTC_SNAPSHOT_STATUS 0 0x44af 0 0 4294967295 mmCRTC3_CRTC_START_LINE_CONTROL 0 0x44b3 0 0 4294967295 mmCRTC3_CRTC_STATUS 0 0x44a3 0 0 4294967295 mmCRTC3_CRTC_STATUS_FRAME_COUNT 0 0x44a6 0 0 4294967295 mmCRTC3_CRTC_STATUS_HV_COUNT 0 0x44a8 0 0 4294967295 mmCRTC3_CRTC_STATUS_POSITION 0 0x44a4 0 0 4294967295 mmCRTC3_CRTC_STATUS_VF_COUNT 0 0x44a7 0 0 4294967295 mmCRTC3_CRTC_STEREO_CONTROL 0 0x44ae 0 0 4294967295 mmCRTC3_CRTC_STEREO_FORCE_NEXT_EYE 0 0x449b 0 0 4294967295 mmCRTC3_CRTC_STEREO_STATUS 0 0x44ad 0 0 4294967295 mmCRTC3_CRTC_TEST_DEBUG_DATA 0 0x44c7 0 0 4294967295 mmCRTC3_CRTC_TEST_DEBUG_INDEX 0 0x44c6 0 0 4294967295 mmCRTC3_CRTC_TEST_PATTERN_COLOR 0 0x44bc 0 0 4294967295 mmCRTC3_CRTC_TEST_PATTERN_CONTROL 0 0x44ba 0 0 4294967295 mmCRTC3_CRTC_TEST_PATTERN_PARAMETERS 0 0x44bb 0 0 4294967295 mmCRTC3_CRTC_TRIGA_CNTL 0 0x4494 0 0 4294967295 mmCRTC3_CRTC_TRIGA_MANUAL_TRIG 0 0x4495 0 0 4294967295 mmCRTC3_CRTC_TRIGB_CNTL 0 0x4496 0 0 4294967295 mmCRTC3_CRTC_TRIGB_MANUAL_TRIG 0 0x4497 0 0 4294967295 mmCRTC3_CRTC_UPDATE_LOCK 0 0x44b5 0 0 4294967295 mmCRTC3_CRTC_VBI_END 0 0x4486 0 0 4294967295 mmCRTC3_CRTC_V_BLANK_START_END 0 0x448d 0 0 4294967295 mmCRTC3_CRTC_VERT_SYNC_CONTROL 0 0x44ac 0 0 4294967295 mmCRTC3_CRTC_VGA_PARAMETER_CAPTURE_MODE 0 0x44b7 0 0 4294967295 mmCRTC3_CRTC_V_SYNC_A 0 0x448e 0 0 4294967295 mmCRTC3_CRTC_V_SYNC_A_CNTL 0 0x448f 0 0 4294967295 mmCRTC3_CRTC_V_SYNC_B 0 0x4490 0 0 4294967295 mmCRTC3_CRTC_V_SYNC_B_CNTL 0 0x4491 0 0 4294967295 mmCRTC3_CRTC_VSYNC_NOM_INT_STATUS 0 0x448c 0 0 4294967295 mmCRTC3_CRTC_V_TOTAL 0 0x4487 0 0 4294967295 mmCRTC3_CRTC_V_TOTAL_CONTROL 0 0x448a 0 0 4294967295 mmCRTC3_CRTC_V_TOTAL_INT_STATUS 0 0x448b 0 0 4294967295 mmCRTC3_CRTC_V_TOTAL_MAX 0 0x4489 0 0 4294967295 mmCRTC3_CRTC_V_TOTAL_MIN 0 0x4488 0 0 4294967295 mmCRTC3_CRTC_V_UPDATE_INT_STATUS 0 0x44c4 0 0 4294967295 mmCRTC3_DCFE_DBG_SEL 0 0x447e 0 0 4294967295 mmCRTC3_DCFE_MEM_LIGHT_SLEEP_CNTL 0 0x447f 0 0 4294967295 mmCRTC_3D_STRUCTURE_CONTROL 0 0x1b78 7 0 4294967295 CRTC_3D_STRUCTURE_EN_DB 4 4 CRTC_3D_STRUCTURE_EN 0 0 CRTC_3D_STRUCTURE_F_COUNT 18 19 CRTC_3D_STRUCTURE_F_COUNT_RESET 16 16 CRTC_3D_STRUCTURE_F_COUNT_RESET_PENDING 17 17 CRTC_3D_STRUCTURE_STEREO_SEL_OVR 12 12 CRTC_3D_STRUCTURE_V_UPDATE_MODE 8 9 mmCRTC3_MASTER_UPDATE_LOCK 0 0x44bd 0 0 4294967295 mmCRTC3_MASTER_UPDATE_MODE 0 0x44be 0 0 4294967295 mmCRTC3_PIXEL_RATE_CNTL 0 0x14c 6 0 4294967295 CRTC3_ADD_PIXEL 8 8 CRTC3_DISPOUT_ERROR_COUNT 16 27 CRTC3_DISPOUT_FIFO_ERROR 14 15 CRTC3_DROP_PIXEL 9 9 CRTC3_PIXEL_RATE_SOURCE 0 1 DP_DTO3_ENABLE 4 4 mmCRTC4_CRTC_3D_STRUCTURE_CONTROL 0 0x4778 0 0 4294967295 mmCRTC4_CRTC_ALLOW_STOP_OFF_V_CNT 0 0x47c3 0 0 4294967295 mmCRTC4_CRTC_BLACK_COLOR 0 0x47a2 0 0 4294967295 mmCRTC4_CRTC_BLANK_CONTROL 0 0x479d 0 0 4294967295 mmCRTC4_CRTC_BLANK_DATA_COLOR 0 0x47a1 0 0 4294967295 mmCRTC4_CRTC_CONTROL 0 0x479c 0 0 4294967295 mmCRTC4_CRTC_COUNT_CONTROL 0 0x47a9 0 0 4294967295 mmCRTC4_CRTC_COUNT_RESET 0 0x47aa 0 0 4294967295 mmCRTC4_CRTC_DCFE_CLOCK_CONTROL 0 0x477c 0 0 4294967295 mmCRTC4_CRTC_DOUBLE_BUFFER_CONTROL 0 0x47b6 0 0 4294967295 mmCRTC4_CRTC_DTMTEST_CNTL 0 0x4792 0 0 4294967295 mmCRTC4_CRTC_DTMTEST_STATUS_POSITION 0 0x4793 0 0 4294967295 mmCRTC4_CRTC_FLOW_CONTROL 0 0x4799 0 0 4294967295 mmCRTC4_CRTC_FORCE_COUNT_NOW_CNTL 0 0x4798 0 0 4294967295 mmCRTC4_CRTC_GSL_CONTROL 0 0x477b 0 0 4294967295 mmCRTC4_CRTC_GSL_VSYNC_GAP 0 0x4779 0 0 4294967295 mmCRTC4_CRTC_GSL_WINDOW 0 0x477a 0 0 4294967295 mmCRTC4_CRTC_H_BLANK_EARLY_NUM 0 0x477d 0 0 4294967295 mmCRTC4_CRTC_H_BLANK_START_END 0 0x4781 0 0 4294967295 mmCRTC4_CRTC_H_SYNC_A 0 0x4782 0 0 4294967295 mmCRTC4_CRTC_H_SYNC_A_CNTL 0 0x4783 0 0 4294967295 mmCRTC4_CRTC_H_SYNC_B 0 0x4784 0 0 4294967295 mmCRTC4_CRTC_H_SYNC_B_CNTL 0 0x4785 0 0 4294967295 mmCRTC4_CRTC_H_TOTAL 0 0x4780 0 0 4294967295 mmCRTC4_CRTC_INTERLACE_CONTROL 0 0x479e 0 0 4294967295 mmCRTC4_CRTC_INTERLACE_STATUS 0 0x479f 0 0 4294967295 mmCRTC4_CRTC_INTERRUPT_CONTROL 0 0x47b4 0 0 4294967295 mmCRTC4_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE 0 0x47ab 0 0 4294967295 mmCRTC4_CRTC_MASTER_EN 0 0x47c2 0 0 4294967295 mmCRTC4_CRTC_MVP_INBAND_CNTL_INSERT 0 0x47bf 0 0 4294967295 mmCRTC4_CRTC_MVP_INBAND_CNTL_INSERT_TIMER 0 0x47c0 0 0 4294967295 mmCRTC4_CRTC_MVP_STATUS 0 0x47c1 0 0 4294967295 mmCRTC4_CRTC_NOM_VERT_POSITION 0 0x47a5 0 0 4294967295 mmCRTC4_CRTC_OVERSCAN_COLOR 0 0x47a0 0 0 4294967295 mmCRTC4_CRTC_SNAPSHOT_CONTROL 0 0x47b0 0 0 4294967295 mmCRTC4_CRTC_SNAPSHOT_FRAME 0 0x47b2 0 0 4294967295 mmCRTC4_CRTC_SNAPSHOT_POSITION 0 0x47b1 0 0 4294967295 mmCRTC4_CRTC_SNAPSHOT_STATUS 0 0x47af 0 0 4294967295 mmCRTC4_CRTC_START_LINE_CONTROL 0 0x47b3 0 0 4294967295 mmCRTC4_CRTC_STATUS 0 0x47a3 0 0 4294967295 mmCRTC4_CRTC_STATUS_FRAME_COUNT 0 0x47a6 0 0 4294967295 mmCRTC4_CRTC_STATUS_HV_COUNT 0 0x47a8 0 0 4294967295 mmCRTC4_CRTC_STATUS_POSITION 0 0x47a4 0 0 4294967295 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mmCRTC5_CRTC_ALLOW_STOP_OFF_V_CNT 0 0x4ac3 0 0 4294967295 mmCRTC5_CRTC_BLACK_COLOR 0 0x4aa2 0 0 4294967295 mmCRTC5_CRTC_BLANK_CONTROL 0 0x4a9d 0 0 4294967295 mmCRTC5_CRTC_BLANK_DATA_COLOR 0 0x4aa1 0 0 4294967295 mmCRTC5_CRTC_CONTROL 0 0x4a9c 0 0 4294967295 mmCRTC5_CRTC_COUNT_CONTROL 0 0x4aa9 0 0 4294967295 mmCRTC5_CRTC_COUNT_RESET 0 0x4aaa 0 0 4294967295 mmCRTC5_CRTC_DCFE_CLOCK_CONTROL 0 0x4a7c 0 0 4294967295 mmCRTC5_CRTC_DOUBLE_BUFFER_CONTROL 0 0x4ab6 0 0 4294967295 mmCRTC5_CRTC_DTMTEST_CNTL 0 0x4a92 0 0 4294967295 mmCRTC5_CRTC_DTMTEST_STATUS_POSITION 0 0x4a93 0 0 4294967295 mmCRTC5_CRTC_FLOW_CONTROL 0 0x4a99 0 0 4294967295 mmCRTC5_CRTC_FORCE_COUNT_NOW_CNTL 0 0x4a98 0 0 4294967295 mmCRTC5_CRTC_GSL_CONTROL 0 0x4a7b 0 0 4294967295 mmCRTC5_CRTC_GSL_VSYNC_GAP 0 0x4a79 0 0 4294967295 mmCRTC5_CRTC_GSL_WINDOW 0 0x4a7a 0 0 4294967295 mmCRTC5_CRTC_H_BLANK_EARLY_NUM 0 0x4a7d 0 0 4294967295 mmCRTC5_CRTC_H_BLANK_START_END 0 0x4a81 0 0 4294967295 mmCRTC5_CRTC_H_SYNC_A 0 0x4a82 0 0 4294967295 mmCRTC5_CRTC_H_SYNC_A_CNTL 0 0x4a83 0 0 4294967295 mmCRTC5_CRTC_H_SYNC_B 0 0x4a84 0 0 4294967295 mmCRTC5_CRTC_H_SYNC_B_CNTL 0 0x4a85 0 0 4294967295 mmCRTC5_CRTC_H_TOTAL 0 0x4a80 0 0 4294967295 mmCRTC5_CRTC_INTERLACE_CONTROL 0 0x4a9e 0 0 4294967295 mmCRTC5_CRTC_INTERLACE_STATUS 0 0x4a9f 0 0 4294967295 mmCRTC5_CRTC_INTERRUPT_CONTROL 0 0x4ab4 0 0 4294967295 mmCRTC5_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE 0 0x4aab 0 0 4294967295 mmCRTC5_CRTC_MASTER_EN 0 0x4ac2 0 0 4294967295 mmCRTC5_CRTC_MVP_INBAND_CNTL_INSERT 0 0x4abf 0 0 4294967295 mmCRTC5_CRTC_MVP_INBAND_CNTL_INSERT_TIMER 0 0x4ac0 0 0 4294967295 mmCRTC5_CRTC_MVP_STATUS 0 0x4ac1 0 0 4294967295 mmCRTC5_CRTC_NOM_VERT_POSITION 0 0x4aa5 0 0 4294967295 mmCRTC5_CRTC_OVERSCAN_COLOR 0 0x4aa0 0 0 4294967295 mmCRTC5_CRTC_SNAPSHOT_CONTROL 0 0x4ab0 0 0 4294967295 mmCRTC5_CRTC_SNAPSHOT_FRAME 0 0x4ab2 0 0 4294967295 mmCRTC5_CRTC_SNAPSHOT_POSITION 0 0x4ab1 0 0 4294967295 mmCRTC5_CRTC_SNAPSHOT_STATUS 0 0x4aaf 0 0 4294967295 mmCRTC5_CRTC_START_LINE_CONTROL 0 0x4ab3 0 0 4294967295 mmCRTC5_CRTC_STATUS 0 0x4aa3 0 0 4294967295 mmCRTC5_CRTC_STATUS_FRAME_COUNT 0 0x4aa6 0 0 4294967295 mmCRTC5_CRTC_STATUS_HV_COUNT 0 0x4aa8 0 0 4294967295 mmCRTC5_CRTC_STATUS_POSITION 0 0x4aa4 0 0 4294967295 mmCRTC5_CRTC_STATUS_VF_COUNT 0 0x4aa7 0 0 4294967295 mmCRTC5_CRTC_STEREO_CONTROL 0 0x4aae 0 0 4294967295 mmCRTC5_CRTC_STEREO_FORCE_NEXT_EYE 0 0x4a9b 0 0 4294967295 mmCRTC5_CRTC_STEREO_STATUS 0 0x4aad 0 0 4294967295 mmCRTC5_CRTC_TEST_DEBUG_DATA 0 0x4ac7 0 0 4294967295 mmCRTC5_CRTC_TEST_DEBUG_INDEX 0 0x4ac6 0 0 4294967295 mmCRTC5_CRTC_TEST_PATTERN_COLOR 0 0x4abc 0 0 4294967295 mmCRTC5_CRTC_TEST_PATTERN_CONTROL 0 0x4aba 0 0 4294967295 mmCRTC5_CRTC_TEST_PATTERN_PARAMETERS 0 0x4abb 0 0 4294967295 mmCRTC5_CRTC_TRIGA_CNTL 0 0x4a94 0 0 4294967295 mmCRTC5_CRTC_TRIGA_MANUAL_TRIG 0 0x4a95 0 0 4294967295 mmCRTC5_CRTC_TRIGB_CNTL 0 0x4a96 0 0 4294967295 mmCRTC5_CRTC_TRIGB_MANUAL_TRIG 0 0x4a97 0 0 4294967295 mmCRTC5_CRTC_UPDATE_LOCK 0 0x4ab5 0 0 4294967295 mmCRTC5_CRTC_VBI_END 0 0x4a86 0 0 4294967295 mmCRTC5_CRTC_V_BLANK_START_END 0 0x4a8d 0 0 4294967295 mmCRTC5_CRTC_VERT_SYNC_CONTROL 0 0x4aac 0 0 4294967295 mmCRTC5_CRTC_VGA_PARAMETER_CAPTURE_MODE 0 0x4ab7 0 0 4294967295 mmCRTC5_CRTC_V_SYNC_A 0 0x4a8e 0 0 4294967295 mmCRTC5_CRTC_V_SYNC_A_CNTL 0 0x4a8f 0 0 4294967295 mmCRTC5_CRTC_V_SYNC_B 0 0x4a90 0 0 4294967295 mmCRTC5_CRTC_V_SYNC_B_CNTL 0 0x4a91 0 0 4294967295 mmCRTC5_CRTC_VSYNC_NOM_INT_STATUS 0 0x4a8c 0 0 4294967295 mmCRTC5_CRTC_V_TOTAL 0 0x4a87 0 0 4294967295 mmCRTC5_CRTC_V_TOTAL_CONTROL 0 0x4a8a 0 0 4294967295 mmCRTC5_CRTC_V_TOTAL_INT_STATUS 0 0x4a8b 0 0 4294967295 mmCRTC5_CRTC_V_TOTAL_MAX 0 0x4a89 0 0 4294967295 mmCRTC5_CRTC_V_TOTAL_MIN 0 0x4a88 0 0 4294967295 mmCRTC5_CRTC_V_UPDATE_INT_STATUS 0 0x4ac4 0 0 4294967295 mmCRTC5_DCFE_DBG_SEL 0 0x4a7e 0 0 4294967295 mmCRTC5_DCFE_MEM_LIGHT_SLEEP_CNTL 0 0x4a7f 0 0 4294967295 mmCRTC5_MASTER_UPDATE_LOCK 0 0x4abd 0 0 4294967295 mmCRTC5_MASTER_UPDATE_MODE 0 0x4abe 0 0 4294967295 mmCRTC5_PIXEL_RATE_CNTL 0 0x154 6 0 4294967295 CRTC5_ADD_PIXEL 8 8 CRTC5_DISPOUT_ERROR_COUNT 16 27 CRTC5_DISPOUT_FIFO_ERROR 14 15 CRTC5_DROP_PIXEL 9 9 CRTC5_PIXEL_RATE_SOURCE 0 1 DP_DTO5_ENABLE 4 4 mmCRTC8_DATA 0 0xed 1 0 4294967295 VCRTC_DATA 0 7 mmCRTC8_IDX 0 0xed 1 0 4294967295 VCRTC_IDX 0 5 mmCRTC_ALLOW_STOP_OFF_V_CNT 0 0x1bc3 2 0 4294967295 CRTC_ALLOW_STOP_OFF_V_CNT 0 7 CRTC_DISABLE_ALLOW_STOP_OFF_V_CNT 16 16 mmCRTC_BLACK_COLOR 0 0x1ba2 3 0 4294967295 CRTC_BLACK_COLOR_B_CB 0 9 CRTC_BLACK_COLOR_G_Y 10 19 CRTC_BLACK_COLOR_R_CR 20 29 mmCRTC_BLANK_CONTROL 0 0x1b9d 3 0 4294967295 CRTC_BLANK_DATA_EN 8 8 CRTC_BLANK_DE_MODE 16 16 CRTC_CURRENT_BLANK_STATE 0 0 mmCRTC_BLANK_DATA_COLOR 0 0x1ba1 3 0 4294967295 CRTC_BLANK_DATA_COLOR_BLUE_CB 0 9 CRTC_BLANK_DATA_COLOR_GREEN_Y 10 19 CRTC_BLANK_DATA_COLOR_RED_CR 20 29 mmCRTC_CONTROL 0 0x1b9c 10 0 4294967295 CRTC_CURRENT_MASTER_EN_STATE 16 16 CRTC_DISABLE_POINT_CNTL 8 9 CRTC_DISP_READ_REQUEST_DISABLE 24 24 CRTC_FIELD_NUMBER_CNTL 13 13 CRTC_HBLANK_EARLY_CONTROL 20 22 CRTC_MASTER_EN 0 0 CRTC_SOF_PULL_EN 29 29 CRTC_START_POINT_CNTL 12 12 CRTC_SYNC_RESET_SEL 4 4 CRTC_PREFETCH_EN 28 28 mmCRTC_COUNT_CONTROL 0 0x1ba9 2 0 4294967295 CRTC_HORZ_COUNT_BY2_EN 0 0 CRTC_HORZ_REPETITION_COUNT 1 4 mmCRTC_COUNT_RESET 0 0x1baa 1 0 4294967295 CRTC_RESET_FRAME_COUNT 0 0 mmCRTC_DCFE_CLOCK_CONTROL 0 0x1b7c 5 0 4294967295 CRTC_DCFE_CLOCK_ENABLE 31 31 CRTC_DCFE_TEST_CLK_SEL 24 28 CRTC_DISPCLK_G_DCP_GATE_DISABLE 8 8 CRTC_DISPCLK_G_SCL_GATE_DISABLE 12 12 CRTC_DISPCLK_R_DCFE_GATE_DISABLE 4 4 mmCRTC_DOUBLE_BUFFER_CONTROL 0 0x1bb6 3 0 4294967295 CRTC_BLANK_DATA_DOUBLE_BUFFER_EN 16 16 CRTC_UPDATE_INSTANTLY 8 8 CRTC_UPDATE_PENDING 0 0 mmCRTC_DTMTEST_CNTL 0 0x1b92 2 0 4294967295 CRTC_DTMTEST_CLK_DIV 1 4 CRTC_DTMTEST_CRTC_EN 0 0 mmCRTC_DTMTEST_STATUS_POSITION 0 0x1b93 2 0 4294967295 CRTC_DTMTEST_HORZ_COUNT 16 28 CRTC_DTMTEST_VERT_COUNT 0 12 mmCRTC_FLOW_CONTROL 0 0x1b99 4 0 4294967295 CRTC_FLOW_CONTROL_GRANULARITY 16 16 CRTC_FLOW_CONTROL_INPUT_STATUS 24 24 CRTC_FLOW_CONTROL_POLARITY 8 8 CRTC_FLOW_CONTROL_SOURCE_SELECT 0 4 mmCRTC_FORCE_COUNT_NOW_CNTL 0 0x1b98 5 0 4294967295 CRTC_FORCE_COUNT_NOW_CHECK 4 4 CRTC_FORCE_COUNT_NOW_CLEAR 24 24 CRTC_FORCE_COUNT_NOW_MODE 0 1 CRTC_FORCE_COUNT_NOW_OCCURRED 16 16 CRTC_FORCE_COUNT_NOW_TRIG_SEL 8 8 mmCRTC_GSL_CONTROL 0 0x1b7b 3 0 4294967295 CRTC_GSL_CHECK_ALL_FIELDS 28 28 CRTC_GSL_CHECK_LINE_NUM 0 12 CRTC_GSL_FORCE_DELAY 16 20 mmCRTC_GSL_VSYNC_GAP 0 0x1b79 8 0 4294967295 CRTC_GSL_VSYNC_GAP_CLEAR 19 19 CRTC_GSL_VSYNC_GAP_DELAY 8 15 CRTC_GSL_VSYNC_GAP_LIMIT 0 7 CRTC_GSL_VSYNC_GAP 24 31 CRTC_GSL_VSYNC_GAP_MASTER_FASTER 23 23 CRTC_GSL_VSYNC_GAP_MODE 17 18 CRTC_GSL_VSYNC_GAP_OCCURRED 20 20 CRTC_GSL_VSYNC_GAP_SOURCE_SEL 16 16 mmCRTC_GSL_WINDOW 0 0x1b7a 2 0 4294967295 CRTC_GSL_WINDOW_END 16 28 CRTC_GSL_WINDOW_START 0 12 mmCRTC_H_BLANK_EARLY_NUM 0 0x1b7d 2 0 4294967295 CRTC_H_BLANK_EARLY_NUM_DIS 16 16 CRTC_H_BLANK_EARLY_NUM 0 9 mmCRTC_H_BLANK_START_END 0 0x1b81 2 0 4294967295 CRTC_H_BLANK_END 16 28 CRTC_H_BLANK_START 0 12 mmCRTC_H_SYNC_A 0 0x1b82 2 0 4294967295 CRTC_H_SYNC_A_END 16 28 CRTC_H_SYNC_A_START 0 12 mmCRTC_H_SYNC_A_CNTL 0 0x1b83 3 0 4294967295 CRTC_COMP_SYNC_A_EN 16 16 CRTC_H_SYNC_A_CUTOFF 17 17 CRTC_H_SYNC_A_POL 0 0 mmCRTC_H_SYNC_B 0 0x1b84 2 0 4294967295 CRTC_H_SYNC_B_END 16 28 CRTC_H_SYNC_B_START 0 12 mmCRTC_H_SYNC_B_CNTL 0 0x1b85 3 0 4294967295 CRTC_COMP_SYNC_B_EN 16 16 CRTC_H_SYNC_B_CUTOFF 17 17 CRTC_H_SYNC_B_POL 0 0 mmCRTC_H_TOTAL 0 0x1b80 1 0 4294967295 CRTC_H_TOTAL 0 12 mmCRTC_INTERLACE_CONTROL 0 0x1b9e 2 0 4294967295 CRTC_INTERLACE_ENABLE 0 0 CRTC_INTERLACE_FORCE_NEXT_FIELD 16 17 mmCRTC_INTERLACE_STATUS 0 0x1b9f 2 0 4294967295 CRTC_INTERLACE_CURRENT_FIELD 0 0 CRTC_INTERLACE_NEXT_FIELD 1 1 mmCRTC_INTERRUPT_CONTROL 0 0x1bb4 16 0 4294967295 CRTC_FORCE_COUNT_NOW_INT_MSK 8 8 CRTC_FORCE_COUNT_NOW_INT_TYPE 9 9 CRTC_FORCE_VSYNC_NEXT_LINE_INT_MSK 16 16 CRTC_FORCE_VSYNC_NEXT_LINE_INT_TYPE 17 17 CRTC_GSL_VSYNC_GAP_INT_MSK 30 30 CRTC_GSL_VSYNC_GAP_INT_TYPE 31 31 CRTC_SNAPSHOT_INT_MSK 0 0 CRTC_SNAPSHOT_INT_TYPE 1 1 CRTC_TRIGA_INT_MSK 24 24 CRTC_TRIGA_INT_TYPE 26 26 CRTC_TRIGB_INT_MSK 25 25 CRTC_TRIGB_INT_TYPE 27 27 CRTC_VSYNC_NOM_INT_MSK 28 28 CRTC_VSYNC_NOM_INT_TYPE 29 29 CRTC_V_UPDATE_INT_MSK 4 4 CRTC_V_UPDATE_INT_TYPE 5 5 mmCRTC_MANUAL_FORCE_VSYNC_NEXT_LINE 0 0x1bab 1 0 4294967295 CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE 0 0 mmCRTC_MASTER_EN 0 0x1bc2 1 0 4294967295 CRTC_MASTER_EN 0 0 mmCRTC_MVP_INBAND_CNTL_INSERT 0 0x1bbf 2 0 4294967295 CRTC_MVP_INBAND_CNTL_CHAR_INSERT 8 31 CRTC_MVP_INBAND_OUT_MODE 0 1 mmCRTC_MVP_INBAND_CNTL_INSERT_TIMER 0 0x1bc0 1 0 4294967295 CRTC_MVP_INBAND_CNTL_CHAR_INSERT_TIMER 0 7 mmCRTC_MVP_STATUS 0 0x1bc1 4 0 4294967295 CRTC_AFR_HSYNC_SWITCH_DONE_CLEAR 20 20 CRTC_AFR_HSYNC_SWITCH_DONE_OCCURRED 4 4 CRTC_FLIP_NOW_CLEAR 16 16 CRTC_FLIP_NOW_OCCURRED 0 0 mmCRTC_NOM_VERT_POSITION 0 0x1ba5 1 0 4294967295 CRTC_VERT_COUNT_NOM 0 12 mmCRTC_OVERSCAN_COLOR 0 0x1ba0 3 0 4294967295 CRTC_OVERSCAN_COLOR_BLUE 0 9 CRTC_OVERSCAN_COLOR_GREEN 10 19 CRTC_OVERSCAN_COLOR_RED 20 29 mmCRTC_SNAPSHOT_CONTROL 0 0x1bb0 1 0 4294967295 CRTC_AUTO_SNAPSHOT_TRIG_SEL 0 1 mmCRTC_SNAPSHOT_FRAME 0 0x1bb2 1 0 4294967295 CRTC_SNAPSHOT_FRAME_COUNT 0 23 mmCRTC_SNAPSHOT_POSITION 0 0x1bb1 2 0 4294967295 CRTC_SNAPSHOT_HORZ_COUNT 16 28 CRTC_SNAPSHOT_VERT_COUNT 0 12 mmCRTC_SNAPSHOT_STATUS 0 0x1baf 3 0 4294967295 CRTC_SNAPSHOT_CLEAR 1 1 CRTC_SNAPSHOT_MANUAL_TRIGGER 2 2 CRTC_SNAPSHOT_OCCURRED 0 0 mmCRTC_START_LINE_CONTROL 0 0x1bb3 3 0 4294967295 CRTC_ADVANCED_START_LINE_POSITION 16 19 CRTC_INTERLACE_START_LINE_EARLY 8 8 CRTC_PROGRESSIVE_START_LINE_EARLY 0 0 mmCRTC_STATUS 0 0x1ba3 9 0 4294967295 CRTC_H_ACTIVE_DISP 17 17 CRTC_H_BLANK 16 16 CRTC_H_SYNC_A 18 18 CRTC_V_ACTIVE_DISP 1 1 CRTC_V_BLANK_3D_STRUCTURE 5 5 CRTC_V_BLANK 0 0 CRTC_V_START_LINE 4 4 CRTC_V_SYNC_A 2 2 CRTC_V_UPDATE 3 3 mmCRTC_STATUS_FRAME_COUNT 0 0x1ba6 1 0 4294967295 CRTC_FRAME_COUNT 0 23 mmCRTC_STATUS_HV_COUNT 0 0x1ba8 1 0 4294967295 CRTC_HV_COUNT 0 28 mmCRTC_STATUS_POSITION 0 0x1ba4 2 0 4294967295 CRTC_HORZ_COUNT 16 28 CRTC_VERT_COUNT 0 12 mmCRTC_STATUS_VF_COUNT 0 0x1ba7 1 0 4294967295 CRTC_VF_COUNT 0 28 mmCRTC_STEREO_CONTROL 0 0x1bae 4 0 4294967295 CRTC_STEREO_EN 24 24 CRTC_STEREO_SYNC_OUTPUT_LINE_NUM 0 12 CRTC_STEREO_SYNC_OUTPUT_POLARITY 15 15 CRTC_STEREO_SYNC_SELECT_POLARITY 16 16 mmCRTC_STEREO_FORCE_NEXT_EYE 0 0x1b9b 1 0 4294967295 CRTC_STEREO_FORCE_NEXT_EYE 0 1 mmCRTC_STEREO_STATUS 0 0x1bad 4 0 4294967295 CRTC_STEREO_CURRENT_EYE 0 0 CRTC_STEREO_FORCE_NEXT_EYE_PENDING 24 25 CRTC_STEREO_SYNC_OUTPUT 8 8 CRTC_STEREO_SYNC_SELECT 16 16 mmCRTC_TEST_DEBUG_DATA 0 0x1bc7 1 0 4294967295 CRTC_TEST_DEBUG_DATA 0 31 mmCRTC_TEST_DEBUG_INDEX 0 0x1bc6 2 0 4294967295 CRTC_TEST_DEBUG_INDEX 0 7 CRTC_TEST_DEBUG_WRITE_EN 8 8 mmCRTC_TEST_PATTERN_COLOR 0 0x1bbc 2 0 4294967295 CRTC_TEST_PATTERN_DATA 0 15 CRTC_TEST_PATTERN_MASK 16 21 mmCRTC_TEST_PATTERN_CONTROL 0 0x1bba 4 0 4294967295 CRTC_TEST_PATTERN_COLOR_FORMAT 24 31 CRTC_TEST_PATTERN_DYNAMIC_RANGE 16 16 CRTC_TEST_PATTERN_EN 0 0 CRTC_TEST_PATTERN_MODE 8 10 mmCRTC_TEST_PATTERN_PARAMETERS 0 0x1bbb 5 0 4294967295 CRTC_TEST_PATTERN_HRES 12 15 CRTC_TEST_PATTERN_INC0 0 3 CRTC_TEST_PATTERN_INC1 4 7 CRTC_TEST_PATTERN_RAMP0_OFFSET 16 31 CRTC_TEST_PATTERN_VRES 8 11 mmCRTC_TRIGA_CNTL 0 0x1b94 11 0 4294967295 CRTC_TRIGA_CLEAR 31 31 CRTC_TRIGA_DELAY 24 28 CRTC_TRIGA_FALLING_EDGE_DETECT_CNTL 16 17 CRTC_TRIGA_FREQUENCY_SELECT 20 21 CRTC_TRIGA_INPUT_STATUS 9 9 CRTC_TRIGA_OCCURRED 11 11 CRTC_TRIGA_POLARITY_SELECT 5 7 CRTC_TRIGA_POLARITY_STATUS 10 10 CRTC_TRIGA_RESYNC_BYPASS_EN 8 8 CRTC_TRIGA_RISING_EDGE_DETECT_CNTL 12 13 CRTC_TRIGA_SOURCE_SELECT 0 4 mmCRTC_TRIGA_MANUAL_TRIG 0 0x1b95 1 0 4294967295 CRTC_TRIGA_MANUAL_TRIG 0 0 mmCRTC_TRIGB_CNTL 0 0x1b96 11 0 4294967295 CRTC_TRIGB_CLEAR 31 31 CRTC_TRIGB_DELAY 24 28 CRTC_TRIGB_FALLING_EDGE_DETECT_CNTL 16 17 CRTC_TRIGB_FREQUENCY_SELECT 20 21 CRTC_TRIGB_INPUT_STATUS 9 9 CRTC_TRIGB_OCCURRED 11 11 CRTC_TRIGB_POLARITY_SELECT 5 7 CRTC_TRIGB_POLARITY_STATUS 10 10 CRTC_TRIGB_RESYNC_BYPASS_EN 8 8 CRTC_TRIGB_RISING_EDGE_DETECT_CNTL 12 13 CRTC_TRIGB_SOURCE_SELECT 0 4 mmCRTC_TRIGB_MANUAL_TRIG 0 0x1b97 1 0 4294967295 CRTC_TRIGB_MANUAL_TRIG 0 0 mmCRTC_UPDATE_LOCK 0 0x1bb5 1 0 4294967295 CRTC_UPDATE_LOCK 0 0 mmCRTC_VBI_END 0 0x1b86 2 0 4294967295 CRTC_VBI_H_END 16 28 CRTC_VBI_V_END 0 12 mmCRTC_V_BLANK_START_END 0 0x1b8d 2 0 4294967295 CRTC_V_BLANK_END 16 28 CRTC_V_BLANK_START 0 12 mmCRTC_VERT_SYNC_CONTROL 0 0x1bac 3 0 4294967295 CRTC_AUTO_FORCE_VSYNC_MODE 16 17 CRTC_FORCE_VSYNC_NEXT_LINE_CLEAR 8 8 CRTC_FORCE_VSYNC_NEXT_LINE_OCCURRED 0 0 mmCRTC_VGA_PARAMETER_CAPTURE_MODE 0 0x1bb7 1 0 4294967295 CRTC_VGA_PARAMETER_CAPTURE_MODE 0 0 mmCRTC_V_SYNC_A 0 0x1b8e 2 0 4294967295 CRTC_V_SYNC_A_END 16 28 CRTC_V_SYNC_A_START 0 12 mmCRTC_V_SYNC_A_CNTL 0 0x1b8f 1 0 4294967295 CRTC_V_SYNC_A_POL 0 0 mmCRTC_V_SYNC_B 0 0x1b90 2 0 4294967295 CRTC_V_SYNC_B_END 16 28 CRTC_V_SYNC_B_START 0 12 mmCRTC_V_SYNC_B_CNTL 0 0x1b91 1 0 4294967295 CRTC_V_SYNC_B_POL 0 0 mmCRTC_VSYNC_NOM_INT_STATUS 0 0x1b8c 2 0 4294967295 CRTC_VSYNC_NOM_INT_CLEAR 4 4 CRTC_VSYNC_NOM 0 0 mmCRTC_V_TOTAL 0 0x1b87 1 0 4294967295 CRTC_V_TOTAL 0 12 mmCRTC_V_TOTAL_CONTROL 0 0x1b8a 5 0 4294967295 CRTC_FORCE_LOCK_ON_EVENT 8 8 CRTC_FORCE_LOCK_TO_MASTER_VSYNC 12 12 CRTC_SET_V_TOTAL_MIN_MASK 16 31 CRTC_V_TOTAL_MAX_SEL 4 4 CRTC_V_TOTAL_MIN_SEL 0 0 mmCRTC_V_TOTAL_INT_STATUS 0 0x1b8b 4 0 4294967295 CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_ACK 8 8 CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT 4 4 CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED 0 0 CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_MSK 12 12 mmCRTC_V_TOTAL_MAX 0 0x1b89 2 0 4294967295 CRTC_ALLOW_VBLANK_EXTENSION_FOR_MC_TRAINING 16 16 CRTC_V_TOTAL_MAX 0 12 mmCRTC_V_TOTAL_MIN 0 0x1b88 1 0 4294967295 CRTC_V_TOTAL_MIN 0 12 mmCRTC_V_UPDATE_INT_STATUS 0 0x1bc4 2 0 4294967295 CRTC_V_UPDATE_INT_CLEAR 8 8 CRTC_V_UPDATE_INT_OCCURRED 0 0 mmCUR_COLOR1 0 0x1a6c 3 0 4294967295 CUR_COLOR1_BLUE 0 7 CUR_COLOR1_GREEN 8 15 CUR_COLOR1_RED 16 23 mmCUR_COLOR2 0 0x1a6d 3 0 4294967295 CUR_COLOR2_BLUE 0 7 CUR_COLOR2_GREEN 8 15 CUR_COLOR2_RED 16 23 mmCUR_CONTROL 0 0x1a66 6 0 4294967295 CUR_INV_TRANS_CLAMP 4 4 CURSOR_2X_MAGNIFY 16 16 CURSOR_EN 0 0 CURSOR_FORCE_MC_ON 20 20 CURSOR_MODE 8 9 CURSOR_URGENT_CONTROL 24 26 mmCUR_HOT_SPOT 0 0x1a6b 2 0 4294967295 CURSOR_HOT_SPOT_X 16 21 CURSOR_HOT_SPOT_Y 0 5 mmCUR_POSITION 0 0x1a6a 2 0 4294967295 CURSOR_X_POSITION 16 29 CURSOR_Y_POSITION 0 13 mmCUR_REQUEST_FILTER_CNTL 0 0x1a99 1 0 4294967295 CUR_REQUEST_FILTER_DIS 0 0 mmCUR_SIZE 0 0x1a68 2 0 4294967295 CURSOR_HEIGHT 0 5 CURSOR_WIDTH 16 21 mmCUR_SURFACE_ADDRESS 0 0x1a67 1 0 4294967295 CURSOR_SURFACE_ADDRESS 0 31 mmCUR_SURFACE_ADDRESS_HIGH 0 0x1a69 1 0 4294967295 CURSOR_SURFACE_ADDRESS_HIGH 0 7 mmCUR_UPDATE 0 0x1a6e 4 0 4294967295 CURSOR_DISABLE_MULTIPLE_UPDATE 24 24 CURSOR_UPDATE_LOCK 16 16 CURSOR_UPDATE_PENDING 0 0 CURSOR_UPDATE_TAKEN 1 1 mmD1VGA_CONTROL 0 0xcc 5 0 4294967295 D1VGA_MODE_ENABLE 0 0 D1VGA_OVERSCAN_COLOR_EN 16 16 D1VGA_ROTATE 24 25 D1VGA_SYNC_POLARITY_SELECT 9 9 D1VGA_TIMING_SELECT 8 8 mmD2VGA_CONTROL 0 0xce 5 0 4294967295 D2VGA_MODE_ENABLE 0 0 D2VGA_OVERSCAN_COLOR_EN 16 16 D2VGA_ROTATE 24 25 D2VGA_SYNC_POLARITY_SELECT 9 9 D2VGA_TIMING_SELECT 8 8 mmD3VGA_CONTROL 0 0xf8 5 0 4294967295 D3VGA_MODE_ENABLE 0 0 D3VGA_OVERSCAN_COLOR_EN 16 16 D3VGA_ROTATE 24 25 D3VGA_SYNC_POLARITY_SELECT 9 9 D3VGA_TIMING_SELECT 8 8 mmD4VGA_CONTROL 0 0xf9 5 0 4294967295 D4VGA_MODE_ENABLE 0 0 D4VGA_OVERSCAN_COLOR_EN 16 16 D4VGA_ROTATE 24 25 D4VGA_SYNC_POLARITY_SELECT 9 9 D4VGA_TIMING_SELECT 8 8 mmD5VGA_CONTROL 0 0xfa 5 0 4294967295 D5VGA_MODE_ENABLE 0 0 D5VGA_OVERSCAN_COLOR_EN 16 16 D5VGA_ROTATE 24 25 D5VGA_SYNC_POLARITY_SELECT 9 9 D5VGA_TIMING_SELECT 8 8 mmD6VGA_CONTROL 0 0xfb 5 0 4294967295 D6VGA_MODE_ENABLE 0 0 D6VGA_OVERSCAN_COLOR_EN 16 16 D6VGA_ROTATE 24 25 D6VGA_SYNC_POLARITY_SELECT 9 9 D6VGA_TIMING_SELECT 8 8 mmDAC_AUTODETECT_CONTROL 0 0x19ee 3 0 4294967295 DAC_AUTODETECT_CHECK_MASK 16 18 DAC_AUTODETECT_FRAME_TIME_COUNTER 8 15 DAC_AUTODETECT_MODE 0 1 mmDAC_AUTODETECT_CONTROL2 0 0x19ef 2 0 4294967295 DAC_AUTODETECT_POWERUP_COUNTER 0 7 DAC_AUTODETECT_TESTMODE 8 8 mmDAC_AUTODETECT_CONTROL3 0 0x19f0 2 0 4294967295 DAC_AUTODET_COMPARATOR_IN_DELAY 0 7 DAC_AUTODET_COMPARATOR_OUT_DELAY 8 15 mmDAC_AUTODETECT_INT_CONTROL 0 0x19f2 2 0 4294967295 DAC_AUTODETECT_ACK 0 0 DAC_AUTODETECT_INT_ENABLE 16 16 mmDAC_AUTODETECT_STATUS 0 0x19f1 5 0 4294967295 DAC_AUTODETECT_BLUE_SENSE 24 25 DAC_AUTODETECT_CONNECT 4 4 DAC_AUTODETECT_GREEN_SENSE 16 17 DAC_AUTODETECT_RED_SENSE 8 9 DAC_AUTODETECT_STATUS 0 0 mmDAC_CLK_ENABLE 0 0x128 2 0 4294967295 DACA_CLK_ENABLE 0 0 DACB_CLK_ENABLE 4 4 mmDAC_COMPARATOR_ENABLE 0 0x19f7 5 0 4294967295 DAC_B_ASYNC_ENABLE 18 18 DAC_COMP_DDET_REF_EN 0 0 DAC_COMP_SDET_REF_EN 8 8 DAC_G_ASYNC_ENABLE 17 17 DAC_R_ASYNC_ENABLE 16 16 mmDAC_COMPARATOR_OUTPUT 0 0x19f8 4 0 4294967295 DAC_COMPARATOR_OUTPUT_BLUE 1 1 DAC_COMPARATOR_OUTPUT_GREEN 2 2 DAC_COMPARATOR_OUTPUT 0 0 DAC_COMPARATOR_OUTPUT_RED 3 3 mmDAC_CONTROL 0 0x19f6 3 0 4294967295 DAC_DFORCE_EN 0 0 DAC_TV_ENABLE 8 8 DAC_ZSCALE_SHIFT 16 16 mmDAC_CRC_CONTROL 0 0x19e7 2 0 4294967295 DAC_CRC_FIELD 0 0 DAC_CRC_ONLY_BLANKb 8 8 mmDAC_CRC_EN 0 0x19e6 2 0 4294967295 DAC_CRC_CONT_EN 16 16 DAC_CRC_EN 0 0 mmDAC_CRC_SIG_CONTROL 0 0x19eb 1 0 4294967295 DAC_CRC_SIG_CONTROL 0 5 mmDAC_CRC_SIG_CONTROL_MASK 0 0x19e9 1 0 4294967295 DAC_CRC_SIG_CONTROL_MASK 0 5 mmDAC_CRC_SIG_RGB 0 0x19ea 3 0 4294967295 DAC_CRC_SIG_BLUE 0 9 DAC_CRC_SIG_GREEN 10 19 DAC_CRC_SIG_RED 20 29 mmDAC_CRC_SIG_RGB_MASK 0 0x19e8 3 0 4294967295 DAC_CRC_SIG_BLUE_MASK 0 9 DAC_CRC_SIG_GREEN_MASK 10 19 DAC_CRC_SIG_RED_MASK 20 29 mmDAC_DATA 0 0xf2 1 0 4294967295 DAC_DATA 0 5 mmDAC_DFT_CONFIG 0 0x19fa 1 0 4294967295 DAC_DFT_CONFIG 0 31 mmDAC_ENABLE 0 0x19e4 6 0 4294967295 DAC_ENABLE 0 0 DAC_RESYNC_FIFO_ENABLE 1 1 DAC_RESYNC_FIFO_ERROR_ACK 5 5 DAC_RESYNC_FIFO_ERROR 4 4 DAC_RESYNC_FIFO_POINTER_SKEW 2 3 DAC_RESYNC_FIFO_TVOUT_SIM 8 8 mmDAC_FIFO_STATUS 0 0x19fb 8 0 4294967295 DAC_FIFO_CAL_AVERAGE_LEVEL 10 15 DAC_FIFO_CALIBRATED 29 29 DAC_FIFO_FORCE_RECAL_AVERAGE 30 30 DAC_FIFO_FORCE_RECOMP_MINMAX 31 31 DAC_FIFO_MAXIMUM_LEVEL 16 19 DAC_FIFO_MINIMUM_LEVEL 22 25 DAC_FIFO_OVERWRITE_LEVEL 2 7 DAC_FIFO_USE_OVERWRITE_LEVEL 1 1 mmDAC_FORCE_DATA 0 0x19f4 1 0 4294967295 DAC_FORCE_DATA 0 9 mmDAC_FORCE_OUTPUT_CNTL 0 0x19f3 3 0 4294967295 DAC_FORCE_DATA_EN 0 0 DAC_FORCE_DATA_ON_BLANKb_ONLY 24 24 DAC_FORCE_DATA_SEL 8 10 mmDAC_MACRO_CNTL_RESERVED0 0 0x19fc 1 0 4294967295 DAC_MACRO_CNTL_RESERVED 0 31 mmDAC_MACRO_CNTL_RESERVED1 0 0x19fd 1 0 4294967295 DAC_MACRO_CNTL_RESERVED 0 31 mmDAC_MACRO_CNTL_RESERVED2 0 0x19fe 1 0 4294967295 DAC_MACRO_CNTL_RESERVED 0 31 mmDAC_MACRO_CNTL_RESERVED3 0 0x19ff 1 0 4294967295 DAC_MACRO_CNTL_RESERVED 0 31 mmDAC_MASK 0 0xf1 1 0 4294967295 DAC_MASK 0 7 mmDAC_POWERDOWN 0 0x19f5 4 0 4294967295 DAC_POWERDOWN_BLUE 8 8 DAC_POWERDOWN_GREEN 16 16 DAC_POWERDOWN 0 0 DAC_POWERDOWN_RED 24 24 mmDAC_PWR_CNTL 0 0x19f9 2 0 4294967295 DAC_BG_MODE 0 1 DAC_PWRCNTL 16 17 mmDAC_R_INDEX 0 0xf1 1 0 4294967295 DAC_R_INDEX 0 7 mmDAC_SOURCE_SELECT 0 0x19e5 2 0 4294967295 DAC_SOURCE_SELECT 0 2 DAC_TV_SELECT 3 3 mmDAC_STEREOSYNC_SELECT 0 0x19ed 1 0 4294967295 DAC_STEREOSYNC_SELECT 0 2 mmDAC_SYNC_TRISTATE_CONTROL 0 0x19ec 3 0 4294967295 DAC_HSYNCA_TRISTATE 0 0 DAC_SYNCA_TRISTATE 16 16 DAC_VSYNCA_TRISTATE 8 8 mmDAC_W_INDEX 0 0xf2 1 0 4294967295 DAC_W_INDEX 0 7 mmDC_ABM1_ACE_CNTL_MISC 0 0x1641 2 0 4294967295 ABM1_ACE_REG_WR_MISSED_FRAME_CLEAR 8 8 ABM1_ACE_REG_WR_MISSED_FRAME 0 0 mmDC_ABM1_ACE_OFFSET_SLOPE_0 0 0x163a 3 0 4294967295 ABM1_ACE_LOCK 31 31 ABM1_ACE_OFFSET_0 16 26 ABM1_ACE_SLOPE_0 0 14 mmDC_ABM1_ACE_OFFSET_SLOPE_1 0 0x163b 3 0 4294967295 ABM1_ACE_LOCK 31 31 ABM1_ACE_OFFSET_1 16 26 ABM1_ACE_SLOPE_1 0 14 mmDC_ABM1_ACE_OFFSET_SLOPE_2 0 0x163c 3 0 4294967295 ABM1_ACE_LOCK 31 31 ABM1_ACE_OFFSET_2 16 26 ABM1_ACE_SLOPE_2 0 14 mmDC_ABM1_ACE_OFFSET_SLOPE_3 0 0x163d 3 0 4294967295 ABM1_ACE_LOCK 31 31 ABM1_ACE_OFFSET_3 16 26 ABM1_ACE_SLOPE_3 0 14 mmDC_ABM1_ACE_OFFSET_SLOPE_4 0 0x163e 3 0 4294967295 ABM1_ACE_LOCK 31 31 ABM1_ACE_OFFSET_4 16 26 ABM1_ACE_SLOPE_4 0 14 mmDC_ABM1_ACE_THRES_12 0 0x163f 3 0 4294967295 ABM1_ACE_LOCK 31 31 ABM1_ACE_THRES_1 0 9 ABM1_ACE_THRES_2 16 25 mmDC_ABM1_ACE_THRES_34 0 0x1640 6 0 4294967295 ABM1_ACE_DBUF_REG_UPDATE_PENDING 30 30 ABM1_ACE_IGNORE_MASTER_LOCK_EN 28 28 ABM1_ACE_LOCK 31 31 ABM1_ACE_READBACK_DB_REG_VALUE_EN 29 29 ABM1_ACE_THRES_3 0 9 ABM1_ACE_THRES_4 16 25 mmDC_ABM1_BL_MASTER_LOCK 0 0x169c 1 0 4294967295 ABM1_BL_MASTER_LOCK 31 31 mmDC_ABM1_CNTL 0 0x1638 3 0 4294967295 ABM1_BLANK_MODE_SUPPORT_ENABLE 31 31 ABM1_EN 0 0 ABM1_SOURCE_SELECT 8 10 mmDC_ABM1_DEBUG_MISC 0 0x1649 3 0 4294967295 ABM1_BL_FORCE_INTERRUPT 16 16 ABM1_HG_FORCE_INTERRUPT 0 0 ABM1_LS_FORCE_INTERRUPT 8 8 mmDC_ABM1_HG_BIN_1_32_SHIFT_FLAG 0 0x1656 1 0 4294967295 ABM1_HG_BIN_1_32_SHIFT_FLAG 0 31 mmDC_ABM1_HG_BIN_17_24_SHIFT_INDEX 0 0x1659 1 0 4294967295 ABM1_HG_BIN_17_24_SHIFT_INDEX 0 31 mmDC_ABM1_HG_BIN_1_8_SHIFT_INDEX 0 0x1657 1 0 4294967295 ABM1_HG_BIN_1_8_SHIFT_INDEX 0 31 mmDC_ABM1_HG_BIN_25_32_SHIFT_INDEX 0 0x165a 1 0 4294967295 ABM1_HG_BIN_25_32_SHIFT_INDEX 0 31 mmDC_ABM1_HG_BIN_9_16_SHIFT_INDEX 0 0x1658 1 0 4294967295 ABM1_HG_BIN_9_16_SHIFT_INDEX 0 31 mmDC_ABM1_HGLS_REG_READ_PROGRESS 0 0x164a 9 0 4294967295 ABM1_BL_REG_READ_IN_PROGRESS 2 2 ABM1_BL_REG_READ_MISSED_FRAME_CLEAR 31 31 ABM1_BL_REG_READ_MISSED_FRAME 10 10 ABM1_HG_REG_READ_IN_PROGRESS 0 0 ABM1_HG_REG_READ_MISSED_FRAME_CLEAR 16 16 ABM1_HG_REG_READ_MISSED_FRAME 8 8 ABM1_LS_REG_READ_IN_PROGRESS 1 1 ABM1_LS_REG_READ_MISSED_FRAME_CLEAR 24 24 ABM1_LS_REG_READ_MISSED_FRAME 9 9 mmDC_ABM1_HG_MISC_CTRL 0 0x164b 11 0 4294967295 ABM1_DBUF_HGLS_READBACK_DB_REG_VALUE_EN 23 23 ABM1_DBUF_HGLS_REG_FRAME_START_DISP_SEL 24 26 ABM1_DBUF_HGLS_REG_UPDATE_AT_FRAME_START 28 28 ABM1_DBUF_HGLS_REG_UPDATE_PENDING 30 30 ABM1_HG_BIN_BITWIDTH_SIZE_SEL 16 17 ABM1_HG_FINE_MODE_BIN_SEL 12 12 ABM1_HGLS_IGNORE_MASTER_LOCK_EN 29 29 ABM1_HGLS_REG_LOCK 31 31 ABM1_HG_NUM_OF_BINS_SEL 0 1 ABM1_HG_VMAX_SEL 8 8 ABM1_OVR_SCAN_PIXEL_PROCESS_EN 20 20 mmDC_ABM1_HG_RESULT_10 0 0x1664 1 0 4294967295 ABM1_HG_RESULT_10 0 31 mmDC_ABM1_HG_RESULT_1 0 0x165b 1 0 4294967295 ABM1_HG_RESULT_1 0 31 mmDC_ABM1_HG_RESULT_11 0 0x1665 1 0 4294967295 ABM1_HG_RESULT_11 0 31 mmDC_ABM1_HG_RESULT_12 0 0x1666 1 0 4294967295 ABM1_HG_RESULT_12 0 31 mmDC_ABM1_HG_RESULT_13 0 0x1667 1 0 4294967295 ABM1_HG_RESULT_13 0 31 mmDC_ABM1_HG_RESULT_14 0 0x1668 1 0 4294967295 ABM1_HG_RESULT_14 0 31 mmDC_ABM1_HG_RESULT_15 0 0x1669 1 0 4294967295 ABM1_HG_RESULT_15 0 31 mmDC_ABM1_HG_RESULT_16 0 0x166a 1 0 4294967295 ABM1_HG_RESULT_16 0 31 mmDC_ABM1_HG_RESULT_17 0 0x166b 1 0 4294967295 ABM1_HG_RESULT_17 0 31 mmDC_ABM1_HG_RESULT_18 0 0x166c 1 0 4294967295 ABM1_HG_RESULT_18 0 31 mmDC_ABM1_HG_RESULT_19 0 0x166d 1 0 4294967295 ABM1_HG_RESULT_19 0 31 mmDC_ABM1_HG_RESULT_20 0 0x166e 1 0 4294967295 ABM1_HG_RESULT_20 0 31 mmDC_ABM1_HG_RESULT_2 0 0x165c 1 0 4294967295 ABM1_HG_RESULT_2 0 31 mmDC_ABM1_HG_RESULT_21 0 0x166f 1 0 4294967295 ABM1_HG_RESULT_21 0 31 mmDC_ABM1_HG_RESULT_22 0 0x1670 1 0 4294967295 ABM1_HG_RESULT_22 0 31 mmDC_ABM1_HG_RESULT_23 0 0x1671 1 0 4294967295 ABM1_HG_RESULT_23 0 31 mmDC_ABM1_HG_RESULT_24 0 0x1672 1 0 4294967295 ABM1_HG_RESULT_24 0 31 mmDC_ABM1_HG_RESULT_3 0 0x165d 1 0 4294967295 ABM1_HG_RESULT_3 0 31 mmDC_ABM1_HG_RESULT_4 0 0x165e 1 0 4294967295 ABM1_HG_RESULT_4 0 31 mmDC_ABM1_HG_RESULT_5 0 0x165f 1 0 4294967295 ABM1_HG_RESULT_5 0 31 mmDC_ABM1_HG_RESULT_6 0 0x1660 1 0 4294967295 ABM1_HG_RESULT_6 0 31 mmDC_ABM1_HG_RESULT_7 0 0x1661 1 0 4294967295 ABM1_HG_RESULT_7 0 31 mmDC_ABM1_HG_RESULT_8 0 0x1662 1 0 4294967295 ABM1_HG_RESULT_8 0 31 mmDC_ABM1_HG_RESULT_9 0 0x1663 1 0 4294967295 ABM1_HG_RESULT_9 0 31 mmDC_ABM1_HG_SAMPLE_RATE 0 0x1654 5 0 4294967295 ABM1_HG_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET 16 23 ABM1_HGLS_REG_LOCK 31 31 ABM1_HG_RESET_SAMPLE_RATE_FRAME_COUNTER 1 1 ABM1_HG_SAMPLE_RATE_COUNT_EN 0 0 ABM1_HG_SAMPLE_RATE_FRAME_COUNT 8 15 mmDC_ABM1_IPCSC_COEFF_SEL 0 0x1639 4 0 4294967295 ABM1_HGLS_REG_LOCK 31 31 ABM1_IPCSC_COEFF_SEL_B 0 3 ABM1_IPCSC_COEFF_SEL_G 8 11 ABM1_IPCSC_COEFF_SEL_R 16 19 mmDC_ABM1_LS_FILTERED_MIN_MAX_LUMA 0 0x164e 2 0 4294967295 ABM1_LS_FILTERED_MAX_LUMA 16 25 ABM1_LS_FILTERED_MIN_LUMA 0 9 mmDC_ABM1_LS_MAX_PIXEL_VALUE_COUNT 0 0x1653 1 0 4294967295 ABM1_LS_MAX_PIXEL_VALUE_COUNT 0 23 mmDC_ABM1_LS_MIN_MAX_LUMA 0 0x164d 2 0 4294967295 ABM1_LS_MAX_LUMA 16 25 ABM1_LS_MIN_LUMA 0 9 mmDC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES 0 0x1651 3 0 4294967295 ABM1_HGLS_REG_LOCK 31 31 ABM1_LS_MAX_PIXEL_VALUE_THRES 16 25 ABM1_LS_MIN_PIXEL_VALUE_THRES 0 9 mmDC_ABM1_LS_MIN_PIXEL_VALUE_COUNT 0 0x1652 1 0 4294967295 ABM1_LS_MIN_PIXEL_VALUE_COUNT 0 23 mmDC_ABM1_LS_OVR_SCAN_BIN 0 0x1650 1 0 4294967295 ABM1_LS_OVR_SCAN_BIN 0 23 mmDC_ABM1_LS_PIXEL_COUNT 0 0x164f 1 0 4294967295 ABM1_LS_PIXEL_COUNT 0 23 mmDC_ABM1_LS_SAMPLE_RATE 0 0x1655 5 0 4294967295 ABM1_HGLS_REG_LOCK 31 31 ABM1_LS_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET 16 23 ABM1_LS_RESET_SAMPLE_RATE_FRAME_COUNTER 1 1 ABM1_LS_SAMPLE_RATE_COUNT_EN 0 0 ABM1_LS_SAMPLE_RATE_FRAME_COUNT 8 15 mmDC_ABM1_LS_SUM_OF_LUMA 0 0x164c 1 0 4294967295 ABM1_LS_SUM_OF_LUMA 0 31 mmDC_ABM1_OVERSCAN_PIXEL_VALUE 0 0x169b 3 0 4294967295 ABM1_OVERSCAN_B_PIXEL_VALUE 20 29 ABM1_OVERSCAN_G_PIXEL_VALUE 10 19 ABM1_OVERSCAN_R_PIXEL_VALUE 0 9 mmDCCG_AUDIO_DTO0_MODULE 0 0x16d 1 0 4294967295 DCCG_AUDIO_DTO0_MODULE 0 31 mmDCCG_AUDIO_DTO0_PHASE 0 0x16c 1 0 4294967295 DCCG_AUDIO_DTO0_PHASE 0 31 mmDCCG_AUDIO_DTO1_MODULE 0 0x171 1 0 4294967295 DCCG_AUDIO_DTO1_MODULE 0 31 mmDCCG_AUDIO_DTO1_PHASE 0 0x170 1 0 4294967295 DCCG_AUDIO_DTO1_PHASE 0 31 mmDCCG_AUDIO_DTO_SOURCE 0 0x16b 2 0 4294967295 DCCG_AUDIO_DTO0_SOURCE_SEL 0 2 DCCG_AUDIO_DTO_SEL 4 4 mmDCCG_CAC_STATUS 0 0x137 1 0 4294967295 CAC_STATUS_RDDATA 0 31 mmDCCG_GATE_DISABLE_CNTL 0 0x134 16 0 4294967295 DACACLK_GATE_DISABLE 4 4 DACBCLK_GATE_DISABLE 5 5 DISPCLK_DCCG_GATE_DISABLE 0 0 DISPCLK_RAMP_DIV_ID 24 26 DISPCLK_R_DCCG_GATE_DISABLE 1 1 DISPCLK_R_DCCG_RAMP_DISABLE 20 20 DVOACLK_GATE_DISABLE 6 6 PCLK_TV_GATE_DISABLE 16 16 SCLK_GATE_DISABLE 2 2 SCLK_RAMP_DIV_ID 28 30 SYMCLKA_GATE_DISABLE 8 8 SYMCLKB_GATE_DISABLE 9 9 SYMCLKC_GATE_DISABLE 10 10 SYMCLKD_GATE_DISABLE 11 11 SYMCLKE_GATE_DISABLE 12 12 SYMCLKF_GATE_DISABLE 13 13 mmDCCG_GTC_CNTL 0 0x120 1 0 4294967295 DCCG_GTC_ENABLE 0 0 mmDCCG_GTC_CURRENT 0 0x123 1 0 4294967295 DCCG_GTC_CURRENT 0 31 mmDCCG_GTC_DTO_MODULO 0 0x122 1 0 4294967295 DCCG_GTC_DTO_MODULO 0 31 mmDCCG_PERFMON_CNTL 0 0x133 9 0 4294967295 DCCG_PERF_CRTC_SEL 8 10 DCCG_PERF_DISPCLK_ENABLE 0 0 DCCG_PERF_DPREFCLK_ENABLE 1 1 DCCG_PERF_MODE_HSYNC 7 7 DCCG_PERF_MODE_VSYNC 6 6 DCCG_PERF_PIXCLK0_ENABLE 4 4 DCCG_PERF_PIXCLK1_ENABLE 2 2 DCCG_PERF_PIXCLK2_ENABLE 3 3 DCCG_PERF_RUN 5 5 mmDCCG_PLL0_PLL_ANALOG 0 0x1708 0 0 4294967295 mmDCCG_PLL0_PLL_CNTL 0 0x1707 0 0 4294967295 mmDCCG_PLL0_PLL_DEBUG_CNTL 0 0x170b 0 0 4294967295 mmDCCG_PLL0_PLL_DISPCLK_CURRENT_DTO_PHASE 0 0x170f 0 0 4294967295 mmDCCG_PLL0_PLL_DISPCLK_DTO_CNTL 0 0x170e 0 0 4294967295 mmDCCG_PLL0_PLL_DS_CNTL 0 0x1705 0 0 4294967295 mmDCCG_PLL0_PLL_FB_DIV 0 0x1701 0 0 4294967295 mmDCCG_PLL0_PLL_IDCLK_CNTL 0 0x1706 0 0 4294967295 mmDCCG_PLL0_PLL_POST_DIV 0 0x1702 0 0 4294967295 mmDCCG_PLL0_PLL_REF_DIV 0 0x1700 0 0 4294967295 mmDCCG_PLL0_PLL_SS_AMOUNT_DSFRAC 0 0x1703 0 0 4294967295 mmDCCG_PLL0_PLL_SS_CNTL 0 0x1704 0 0 4294967295 mmDCCG_PLL0_PLL_UNLOCK_DETECT_CNTL 0 0x170a 0 0 4294967295 mmDCCG_PLL0_PLL_UPDATE_CNTL 0 0x170d 0 0 4294967295 mmDCCG_PLL0_PLL_UPDATE_LOCK 0 0x170c 0 0 4294967295 mmDCCG_PLL0_PLL_VREG_CNTL 0 0x1709 0 0 4294967295 mmDCCG_PLL1_PLL_ANALOG 0 0x1718 0 0 4294967295 mmDCCG_PLL1_PLL_CNTL 0 0x1717 0 0 4294967295 mmDCCG_PLL1_PLL_DEBUG_CNTL 0 0x171b 0 0 4294967295 mmDCCG_PLL1_PLL_DISPCLK_CURRENT_DTO_PHASE 0 0x171f 0 0 4294967295 mmDCCG_PLL1_PLL_DISPCLK_DTO_CNTL 0 0x171e 0 0 4294967295 mmDCCG_PLL1_PLL_DS_CNTL 0 0x1715 0 0 4294967295 mmDCCG_PLL1_PLL_FB_DIV 0 0x1711 0 0 4294967295 mmDCCG_PLL1_PLL_IDCLK_CNTL 0 0x1716 0 0 4294967295 mmDCCG_PLL1_PLL_POST_DIV 0 0x1712 0 0 4294967295 mmDCCG_PLL1_PLL_REF_DIV 0 0x1710 0 0 4294967295 mmDCCG_PLL1_PLL_SS_AMOUNT_DSFRAC 0 0x1713 0 0 4294967295 mmDCCG_PLL1_PLL_SS_CNTL 0 0x1714 0 0 4294967295 mmDCCG_PLL1_PLL_UNLOCK_DETECT_CNTL 0 0x171a 0 0 4294967295 mmDCCG_PLL1_PLL_UPDATE_CNTL 0 0x171d 0 0 4294967295 mmDCCG_PLL1_PLL_UPDATE_LOCK 0 0x171c 0 0 4294967295 mmDCCG_PLL1_PLL_VREG_CNTL 0 0x1719 0 0 4294967295 mmDCCG_PLL2_PLL_ANALOG 0 0x1728 0 0 4294967295 mmDCCG_PLL2_PLL_CNTL 0 0x1727 0 0 4294967295 mmDCCG_PLL2_PLL_DEBUG_CNTL 0 0x172b 0 0 4294967295 mmDCCG_PLL2_PLL_DISPCLK_CURRENT_DTO_PHASE 0 0x172f 0 0 4294967295 mmDCCG_PLL2_PLL_DISPCLK_DTO_CNTL 0 0x172e 0 0 4294967295 mmDCCG_PLL2_PLL_DS_CNTL 0 0x1725 0 0 4294967295 mmDCCG_PLL2_PLL_FB_DIV 0 0x1721 0 0 4294967295 mmDCCG_PLL2_PLL_IDCLK_CNTL 0 0x1726 0 0 4294967295 mmDCCG_PLL2_PLL_POST_DIV 0 0x1722 0 0 4294967295 mmDCCG_PLL2_PLL_REF_DIV 0 0x1720 0 0 4294967295 mmDCCG_PLL2_PLL_SS_AMOUNT_DSFRAC 0 0x1723 0 0 4294967295 mmDCCG_PLL2_PLL_SS_CNTL 0 0x1724 0 0 4294967295 mmDCCG_PLL2_PLL_UNLOCK_DETECT_CNTL 0 0x172a 0 0 4294967295 mmDCCG_PLL2_PLL_UPDATE_CNTL 0 0x172d 0 0 4294967295 mmDCCG_PLL2_PLL_UPDATE_LOCK 0 0x172c 0 0 4294967295 mmDCCG_PLL2_PLL_VREG_CNTL 0 0x1729 0 0 4294967295 mmDCCG_SOFT_RESET 0 0x15f 1 0 4294967295 REFCLK_SOFT_RESET 0 0 mmDCCG_TEST_CLK_SEL 0 0x17e 4 0 4294967295 DCCG_TEST_CLK_GENERICA_INV 16 16 DCCG_TEST_CLK_GENERICA_SEL 0 7 DCCG_TEST_CLK_GENERICB_INV 24 24 DCCG_TEST_CLK_GENERICB_SEL 8 15 mmDCCG_TEST_DEBUG_DATA 0 0x17d 1 0 4294967295 DCCG_TEST_DEBUG_DATA 0 31 mmDCCG_TEST_DEBUG_INDEX 0 0x17c 3 0 4294967295 DCCG_DBG_SEL 12 12 DCCG_TEST_DEBUG_INDEX 0 7 DCCG_TEST_DEBUG_WRITE_EN 8 8 mmDCCG_VPCLK_CNTL 0 0x31f 25 0 4294967295 AZ_LIGHT_SLEEP_DIS 2 2 AZ_MEM_SHUTDOWN_DIS 26 26 DCCG_VPCLK_POL 0 0 DMCU_LIGHT_SLEEP_DIS 3 3 DMCU_MEM_SHUTDOWN_DIS 16 16 DMIF0_LIGHT_SLEEP_DIS 8 8 DMIF0_MEM_SHUTDOWN_DIS 20 20 DMIF1_LIGHT_SLEEP_DIS 9 9 DMIF1_MEM_SHUTDOWN_DIS 21 21 DMIF2_LIGHT_SLEEP_DIS 10 10 DMIF2_MEM_SHUTDOWN_DIS 22 22 DMIF3_LIGHT_SLEEP_DIS 11 11 DMIF3_MEM_SHUTDOWN_DIS 23 23 DMIF4_LIGHT_SLEEP_DIS 12 12 DMIF4_MEM_SHUTDOWN_DIS 24 24 DMIF5_LIGHT_SLEEP_DIS 13 13 DMIF5_MEM_SHUTDOWN_DIS 25 25 DMIF_XLR_LIGHT_SLEEP_MODE_FORCE 5 5 DMIF_XLR_MEM_SHUTDOWN_MODE_FORCE 18 18 FBC_LIGHT_SLEEP_DIS 14 14 FBC_MEM_SHUTDOWN_DIS 19 19 MCIF_LIGHT_SLEEP_MODE_FORCE 4 4 MCIF_MEM_SHUTDOWN_MODE_FORCE 17 17 VGA_LIGHT_SLEEP_MODE_FORCE 1 1 VIP_LIGHT_SLEEP_DIS 15 15 mmDCDEBUG_BUS_CLK1_SEL 0 0x1860 1 0 4294967295 DCDEBUG_BUS_CLK1_SEL 0 31 mmDCDEBUG_BUS_CLK2_SEL 0 0x1861 1 0 4294967295 DCDEBUG_BUS_CLK2_SEL 0 31 mmDCDEBUG_BUS_CLK3_SEL 0 0x1862 1 0 4294967295 DCDEBUG_BUS_CLK3_SEL 0 31 mmDCDEBUG_BUS_CLK4_SEL 0 0x1863 1 0 4294967295 DCDEBUG_BUS_CLK4_SEL 0 31 mmDCDEBUG_OUT_CNTL 0 0x186b 6 0 4294967295 DCDEBUG_BLOCK_SEL 0 4 DCDEBUG_OUT_EN 5 5 DCDEBUG_OUT_PIN_SEL 6 6 DCDEBUG_OUT_SEL 20 21 DCDEBUG_OUT_TEST_DATA_EN 7 7 DCDEBUG_OUT_TEST_DATA 8 19 mmDCDEBUG_OUT_DATA 0 0x186e 1 0 4294967295 DCDEBUG_OUT_DATA 0 31 mmDCDEBUG_OUT_PIN_OVERRIDE 0 0x186a 6 0 4294967295 DCDEBUG_OUT_OVERRIDE1_EN 12 12 DCDEBUG_OUT_OVERRIDE1_PIN_SEL 0 3 DCDEBUG_OUT_OVERRIDE1_REGBIT_SEL 4 8 DCDEBUG_OUT_OVERRIDE2_EN 28 28 DCDEBUG_OUT_OVERRIDE2_PIN_SEL 16 19 DCDEBUG_OUT_OVERRIDE2_REGBIT_SEL 20 24 mmDC_DMCU_SCRATCH 0 0x1618 1 0 4294967295 DMCU_SCRATCH 0 31 mmDC_DVODATA_CONFIG 0 0x1905 3 0 4294967295 DVO_ALTER_MAPPING_EN 21 21 VIP_ALTER_MAPPING_EN 20 20 VIP_MUX_EN 19 19 mmDCFE0_SOFT_RESET 0 0x158 5 0 4294967295 CRTC0_SOFT_RESET 4 4 DCP0_PIXPIPE_SOFT_RESET 0 0 DCP0_REQ_SOFT_RESET 1 1 SCL0_ALU_SOFT_RESET 2 2 SCL0_SOFT_RESET 3 3 mmDCFE1_SOFT_RESET 0 0x159 5 0 4294967295 CRTC1_SOFT_RESET 4 4 DCP1_PIXPIPE_SOFT_RESET 0 0 DCP1_REQ_SOFT_RESET 1 1 SCL1_ALU_SOFT_RESET 2 2 SCL1_SOFT_RESET 3 3 mmDCFE2_SOFT_RESET 0 0x15a 5 0 4294967295 CRTC2_SOFT_RESET 4 4 DCP2_PIXPIPE_SOFT_RESET 0 0 DCP2_REQ_SOFT_RESET 1 1 SCL2_ALU_SOFT_RESET 2 2 SCL2_SOFT_RESET 3 3 mmDCFE3_SOFT_RESET 0 0x15b 5 0 4294967295 CRTC3_SOFT_RESET 4 4 DCP3_PIXPIPE_SOFT_RESET 0 0 DCP3_REQ_SOFT_RESET 1 1 SCL3_ALU_SOFT_RESET 2 2 SCL3_SOFT_RESET 3 3 mmDCFE4_SOFT_RESET 0 0x15c 5 0 4294967295 CRTC4_SOFT_RESET 4 4 DCP4_PIXPIPE_SOFT_RESET 0 0 DCP4_REQ_SOFT_RESET 1 1 SCL4_ALU_SOFT_RESET 2 2 SCL4_SOFT_RESET 3 3 mmDCFE5_SOFT_RESET 0 0x15d 5 0 4294967295 CRTC5_SOFT_RESET 4 4 DCP5_PIXPIPE_SOFT_RESET 0 0 DCP5_REQ_SOFT_RESET 1 1 SCL5_ALU_SOFT_RESET 2 2 SCL5_SOFT_RESET 3 3 mmDCFE_DBG_SEL 0 0x1b7e 1 0 4294967295 DCFE_DBG_SEL 0 3 mmDCFE_MEM_LIGHT_SLEEP_CNTL 0 0x1b7f 17 0 4294967295 DCP_CURSOR_LIGHT_SLEEP_DIS 0 0 DCP_CURSOR_MEM_PWR_STATE 8 9 DCP_LUT_LIGHT_SLEEP_DIS 2 2 DCP_LUT_MEM_PWR_STATE 12 13 LB1_MEM_SHUTDOWN_DIS 29 29 LB2_MEM_SHUTDOWN_DIS 30 30 LB_LIGHT_SLEEP_DIS 4 4 LB_MEM_PWR_STATE_0 16 17 LB_MEM_PWR_STATE_1 22 23 LB_MEM_PWR_STATE_2 24 25 OVLSCL_LIGHT_SLEEP_DIS 3 3 OVLSCL_MEM_PWR_STATE 14 15 PIPE_MEM_SHUTDOWN_DIS 28 28 REGAMMA_LUT_LIGHT_SLEEP_DIS 6 6 REGAMMA_LUT_MEM_PWR_STATE 20 21 SCL_LIGHT_SLEEP_DIS 5 5 SCL_MEM_PWR_STATE 18 19 mmDC_GENERICA 0 0x1900 6 0 4294967295 GENERICA_EN 0 0 GENERICA_SEL 8 11 GENERICA_UNIPHY_FBDIV_CLK_DIV2_SEL 24 26 GENERICA_UNIPHY_FBDIV_CLK_SEL 16 18 GENERICA_UNIPHY_FBDIV_SSC_CLK_SEL 20 22 GENERICA_UNIPHY_REFDIV_CLK_SEL 12 14 mmDC_GENERICB 0 0x1901 6 0 4294967295 GENERICB_EN 0 0 GENERICB_SEL 8 11 GENERICB_UNIPHY_FBDIV_CLK_DIV2_SEL 24 26 GENERICB_UNIPHY_FBDIV_CLK_SEL 16 18 GENERICB_UNIPHY_FBDIV_SSC_CLK_SEL 20 22 GENERICB_UNIPHY_REFDIV_CLK_SEL 12 14 mmDC_GPIO_DDC1_A 0 0x194d 2 0 4294967295 DC_GPIO_DDC1CLK_A 0 0 DC_GPIO_DDC1DATA_A 8 8 mmDC_GPIO_DDC1_EN 0 0x194e 2 0 4294967295 DC_GPIO_DDC1CLK_EN 0 0 DC_GPIO_DDC1DATA_EN 8 8 mmDC_GPIO_DDC1_MASK 0 0x194c 11 0 4294967295 ALLOW_HW_DDC1_PD_EN 22 22 AUX1_POL 20 20 AUX_PAD1_MODE 16 16 DC_GPIO_DDC1CLK_MASK 0 0 DC_GPIO_DDC1CLK_PD_EN 4 4 DC_GPIO_DDC1CLK_RECV 6 6 DC_GPIO_DDC1CLK_STR 24 27 DC_GPIO_DDC1DATA_MASK 8 8 DC_GPIO_DDC1DATA_PD_EN 12 12 DC_GPIO_DDC1DATA_RECV 14 14 DC_GPIO_DDC1DATA_STR 28 31 mmDC_GPIO_DDC1_Y 0 0x194f 2 0 4294967295 DC_GPIO_DDC1CLK_Y 0 0 DC_GPIO_DDC1DATA_Y 8 8 mmDC_GPIO_DDC2_A 0 0x1951 2 0 4294967295 DC_GPIO_DDC2CLK_A 0 0 DC_GPIO_DDC2DATA_A 8 8 mmDC_GPIO_DDC2_EN 0 0x1952 2 0 4294967295 DC_GPIO_DDC2CLK_EN 0 0 DC_GPIO_DDC2DATA_EN 8 8 mmDC_GPIO_DDC2_MASK 0 0x1950 11 0 4294967295 ALLOW_HW_DDC2_PD_EN 22 22 AUX2_POL 20 20 AUX_PAD2_MODE 16 16 DC_GPIO_DDC2CLK_MASK 0 0 DC_GPIO_DDC2CLK_PD_EN 4 4 DC_GPIO_DDC2CLK_RECV 6 6 DC_GPIO_DDC2CLK_STR 24 27 DC_GPIO_DDC2DATA_MASK 8 8 DC_GPIO_DDC2DATA_PD_EN 12 12 DC_GPIO_DDC2DATA_RECV 14 14 DC_GPIO_DDC2DATA_STR 28 31 mmDC_GPIO_DDC2_Y 0 0x1953 2 0 4294967295 DC_GPIO_DDC2CLK_Y 0 0 DC_GPIO_DDC2DATA_Y 8 8 mmDC_GPIO_DDC3_A 0 0x1955 2 0 4294967295 DC_GPIO_DDC3CLK_A 0 0 DC_GPIO_DDC3DATA_A 8 8 mmDC_GPIO_DDC3_EN 0 0x1956 2 0 4294967295 DC_GPIO_DDC3CLK_EN 0 0 DC_GPIO_DDC3DATA_EN 8 8 mmDC_GPIO_DDC3_MASK 0 0x1954 11 0 4294967295 ALLOW_HW_DDC3_PD_EN 22 22 AUX3_POL 20 20 AUX_PAD3_MODE 16 16 DC_GPIO_DDC3CLK_MASK 0 0 DC_GPIO_DDC3CLK_PD_EN 4 4 DC_GPIO_DDC3CLK_RECV 6 6 DC_GPIO_DDC3CLK_STR 24 27 DC_GPIO_DDC3DATA_MASK 8 8 DC_GPIO_DDC3DATA_PD_EN 12 12 DC_GPIO_DDC3DATA_RECV 14 14 DC_GPIO_DDC3DATA_STR 28 31 mmDC_GPIO_DDC3_Y 0 0x1957 2 0 4294967295 DC_GPIO_DDC3CLK_Y 0 0 DC_GPIO_DDC3DATA_Y 8 8 mmDC_GPIO_DDC4_A 0 0x1959 2 0 4294967295 DC_GPIO_DDC4CLK_A 0 0 DC_GPIO_DDC4DATA_A 8 8 mmDC_GPIO_DDC4_EN 0 0x195a 2 0 4294967295 DC_GPIO_DDC4CLK_EN 0 0 DC_GPIO_DDC4DATA_EN 8 8 mmDC_GPIO_DDC4_MASK 0 0x1958 11 0 4294967295 ALLOW_HW_DDC4_PD_EN 22 22 AUX4_POL 20 20 AUX_PAD4_MODE 16 16 DC_GPIO_DDC4CLK_MASK 0 0 DC_GPIO_DDC4CLK_PD_EN 4 4 DC_GPIO_DDC4CLK_RECV 6 6 DC_GPIO_DDC4CLK_STR 24 27 DC_GPIO_DDC4DATA_MASK 8 8 DC_GPIO_DDC4DATA_PD_EN 12 12 DC_GPIO_DDC4DATA_RECV 14 14 DC_GPIO_DDC4DATA_STR 28 31 mmDC_GPIO_DDC4_Y 0 0x195b 2 0 4294967295 DC_GPIO_DDC4CLK_Y 0 0 DC_GPIO_DDC4DATA_Y 8 8 mmDC_GPIO_DDC5_A 0 0x195d 2 0 4294967295 DC_GPIO_DDC5CLK_A 0 0 DC_GPIO_DDC5DATA_A 8 8 mmDC_GPIO_DDC5_EN 0 0x195e 2 0 4294967295 DC_GPIO_DDC5CLK_EN 0 0 DC_GPIO_DDC5DATA_EN 8 8 mmDC_GPIO_DDC5_MASK 0 0x195c 11 0 4294967295 ALLOW_HW_DDC5_PD_EN 22 22 AUX5_POL 20 20 AUX_PAD5_MODE 16 16 DC_GPIO_DDC5CLK_MASK 0 0 DC_GPIO_DDC5CLK_PD_EN 4 4 DC_GPIO_DDC5CLK_RECV 6 6 DC_GPIO_DDC5CLK_STR 24 27 DC_GPIO_DDC5DATA_MASK 8 8 DC_GPIO_DDC5DATA_PD_EN 12 12 DC_GPIO_DDC5DATA_RECV 14 14 DC_GPIO_DDC5DATA_STR 28 31 mmDC_GPIO_DDC5_Y 0 0x195f 2 0 4294967295 DC_GPIO_DDC5CLK_Y 0 0 DC_GPIO_DDC5DATA_Y 8 8 mmDC_GPIO_DDC6_A 0 0x1961 2 0 4294967295 DC_GPIO_DDC6CLK_A 0 0 DC_GPIO_DDC6DATA_A 8 8 mmDC_GPIO_DDC6_EN 0 0x1962 2 0 4294967295 DC_GPIO_DDC6CLK_EN 0 0 DC_GPIO_DDC6DATA_EN 8 8 mmDC_GPIO_DDC6_MASK 0 0x1960 11 0 4294967295 ALLOW_HW_DDC6_PD_EN 22 22 AUX6_POL 20 20 AUX_PAD6_MODE 16 16 DC_GPIO_DDC6CLK_MASK 0 0 DC_GPIO_DDC6CLK_PD_EN 4 4 DC_GPIO_DDC6CLK_RECV 6 6 DC_GPIO_DDC6CLK_STR 24 27 DC_GPIO_DDC6DATA_MASK 8 8 DC_GPIO_DDC6DATA_PD_EN 12 12 DC_GPIO_DDC6DATA_RECV 14 14 DC_GPIO_DDC6DATA_STR 28 31 mmDC_GPIO_DDC6_Y 0 0x1963 2 0 4294967295 DC_GPIO_DDC6CLK_Y 0 0 DC_GPIO_DDC6DATA_Y 8 8 mmDC_GPIO_DDCVGA_A 0 0x1971 2 0 4294967295 DC_GPIO_DDCVGACLK_A 0 0 DC_GPIO_DDCVGADATA_A 8 8 mmDC_GPIO_DDCVGA_EN 0 0x1972 2 0 4294967295 DC_GPIO_DDCVGACLK_EN 0 0 DC_GPIO_DDCVGADATA_EN 8 8 mmDC_GPIO_DDCVGA_MASK 0 0x1970 10 0 4294967295 ALLOW_HW_DDCVGA_PD_EN 22 22 AUX_PADVGA_MODE 16 16 AUXVGA_POL 20 20 DC_GPIO_DDCVGACLK_MASK 0 0 DC_GPIO_DDCVGACLK_RECV 6 6 DC_GPIO_DDCVGACLK_STR 24 27 DC_GPIO_DDCVGADATA_MASK 8 8 DC_GPIO_DDCVGADATA_PD_EN 12 12 DC_GPIO_DDCVGADATA_RECV 14 14 DC_GPIO_DDCVGADATA_STR 28 31 mmDC_GPIO_DDCVGA_Y 0 0x1973 2 0 4294967295 DC_GPIO_DDCVGACLK_Y 0 0 DC_GPIO_DDCVGADATA_Y 8 8 mmDC_GPIO_DEBUG 0 0x1904 3 0 4294967295 DC_GPIO_CHIP_DEBUG_OUT_PIN_SEL 16 16 DC_GPIO_MACRO_DEBUG 8 9 DC_GPIO_VIP_DEBUG 0 0 mmDC_GPIO_DVODATA_A 0 0x1949 4 0 4294967295 DC_GPIO_DVOCLK_A 28 28 DC_GPIO_DVOCNTL_A 24 26 DC_GPIO_DVODATA_A 0 23 DC_GPIO_MVP_DVOCNTL_A 30 31 mmDC_GPIO_DVODATA_EN 0 0x194a 4 0 4294967295 DC_GPIO_DVOCLK_EN 28 28 DC_GPIO_DVOCNTL_EN 24 26 DC_GPIO_DVODATA_EN 0 23 DC_GPIO_MVP_DVOCNTL_EN 30 31 mmDC_GPIO_DVODATA_MASK 0 0x1948 4 0 4294967295 DC_GPIO_DVOCLK_MASK 28 28 DC_GPIO_DVOCNTL_MASK 24 26 DC_GPIO_DVODATA_MASK 0 23 DC_GPIO_MVP_DVOCNTL_MASK 30 31 mmDC_GPIO_DVODATA_Y 0 0x194b 4 0 4294967295 DC_GPIO_DVOCLK_Y 28 28 DC_GPIO_DVOCNTL_Y 24 26 DC_GPIO_DVODATA_Y 0 23 DC_GPIO_MVP_DVOCNTL_Y 30 31 mmDC_GPIO_GENERIC_A 0 0x1945 7 0 4294967295 DC_GPIO_GENERICA_A 0 0 DC_GPIO_GENERICB_A 8 8 DC_GPIO_GENERICC_A 16 16 DC_GPIO_GENERICD_A 20 20 DC_GPIO_GENERICE_A 21 21 DC_GPIO_GENERICF_A 22 22 DC_GPIO_GENERICG_A 23 23 mmDC_GPIO_GENERIC_EN 0 0x1946 7 0 4294967295 DC_GPIO_GENERICA_EN 0 0 DC_GPIO_GENERICB_EN 8 8 DC_GPIO_GENERICC_EN 16 16 DC_GPIO_GENERICD_EN 20 20 DC_GPIO_GENERICE_EN 21 21 DC_GPIO_GENERICF_EN 22 22 DC_GPIO_GENERICG_EN 23 23 mmDC_GPIO_GENERIC_MASK 0 0x1944 21 0 4294967295 DC_GPIO_GENERICA_MASK 0 0 DC_GPIO_GENERICA_PD_DIS 1 1 DC_GPIO_GENERICA_RECV 2 2 DC_GPIO_GENERICB_MASK 4 4 DC_GPIO_GENERICB_PD_DIS 5 5 DC_GPIO_GENERICB_RECV 6 6 DC_GPIO_GENERICC_MASK 8 8 DC_GPIO_GENERICC_PD_DIS 9 9 DC_GPIO_GENERICC_RECV 10 10 DC_GPIO_GENERICD_MASK 12 12 DC_GPIO_GENERICD_PD_DIS 13 13 DC_GPIO_GENERICD_RECV 14 14 DC_GPIO_GENERICE_MASK 16 16 DC_GPIO_GENERICE_PD_DIS 17 17 DC_GPIO_GENERICE_RECV 18 18 DC_GPIO_GENERICF_MASK 20 20 DC_GPIO_GENERICF_PD_DIS 21 21 DC_GPIO_GENERICF_RECV 22 22 DC_GPIO_GENERICG_MASK 24 24 DC_GPIO_GENERICG_PD_DIS 25 25 DC_GPIO_GENERICG_RECV 26 26 mmDC_GPIO_GENERIC_Y 0 0x1947 7 0 4294967295 DC_GPIO_GENERICA_Y 0 0 DC_GPIO_GENERICB_Y 8 8 DC_GPIO_GENERICC_Y 16 16 DC_GPIO_GENERICD_Y 20 20 DC_GPIO_GENERICE_Y 21 21 DC_GPIO_GENERICF_Y 22 22 DC_GPIO_GENERICG_Y 23 23 mmDC_GPIO_GENLK_A 0 0x1969 4 0 4294967295 DC_GPIO_GENLK_CLK_A 0 0 DC_GPIO_GENLK_VSYNC_A 8 8 DC_GPIO_SWAPLOCK_A_A 16 16 DC_GPIO_SWAPLOCK_B_A 24 24 mmDC_GPIO_GENLK_EN 0 0x196a 4 0 4294967295 DC_GPIO_GENLK_CLK_EN 0 0 DC_GPIO_GENLK_VSYNC_EN 8 8 DC_GPIO_SWAPLOCK_A_EN 16 16 DC_GPIO_SWAPLOCK_B_EN 24 24 mmDC_GPIO_GENLK_MASK 0 0x1968 16 0 4294967295 DC_GPIO_GENLK_CLK_MASK 0 0 DC_GPIO_GENLK_CLK_PD_DIS 1 1 DC_GPIO_GENLK_CLK_PU_EN 3 3 DC_GPIO_GENLK_CLK_RECV 2 2 DC_GPIO_GENLK_VSYNC_MASK 8 8 DC_GPIO_GENLK_VSYNC_PD_DIS 9 9 DC_GPIO_GENLK_VSYNC_PU_EN 11 11 DC_GPIO_GENLK_VSYNC_RECV 10 10 DC_GPIO_SWAPLOCK_A_MASK 16 16 DC_GPIO_SWAPLOCK_A_PD_DIS 17 17 DC_GPIO_SWAPLOCK_A_PU_EN 19 19 DC_GPIO_SWAPLOCK_A_RECV 18 18 DC_GPIO_SWAPLOCK_B_MASK 24 24 DC_GPIO_SWAPLOCK_B_PD_DIS 25 25 DC_GPIO_SWAPLOCK_B_PU_EN 27 27 DC_GPIO_SWAPLOCK_B_RECV 26 26 mmDC_GPIO_GENLK_Y 0 0x196b 4 0 4294967295 DC_GPIO_GENLK_CLK_Y 0 0 DC_GPIO_GENLK_VSYNC_Y 8 8 DC_GPIO_SWAPLOCK_A_Y 16 16 DC_GPIO_SWAPLOCK_B_Y 24 24 mmDC_GPIO_HPD_A 0 0x196d 6 0 4294967295 DC_GPIO_HPD1_A 0 0 DC_GPIO_HPD2_A 8 8 DC_GPIO_HPD3_A 16 16 DC_GPIO_HPD4_A 24 24 DC_GPIO_HPD5_A 26 26 DC_GPIO_HPD6_A 28 28 mmDC_GPIO_HPD_EN 0 0x196e 6 0 4294967295 DC_GPIO_HPD1_EN 0 0 DC_GPIO_HPD2_EN 8 8 DC_GPIO_HPD3_EN 16 16 DC_GPIO_HPD4_EN 24 24 DC_GPIO_HPD5_EN 26 26 DC_GPIO_HPD6_EN 28 28 mmDC_GPIO_HPD_MASK 0 0x196c 18 0 4294967295 DC_GPIO_HPD1_MASK 0 0 DC_GPIO_HPD1_PD_DIS 4 4 DC_GPIO_HPD1_RECV 6 6 DC_GPIO_HPD2_MASK 8 8 DC_GPIO_HPD2_PD_DIS 9 9 DC_GPIO_HPD2_RECV 10 10 DC_GPIO_HPD3_MASK 16 16 DC_GPIO_HPD3_PD_DIS 17 17 DC_GPIO_HPD3_RECV 18 18 DC_GPIO_HPD4_MASK 20 20 DC_GPIO_HPD4_PD_DIS 21 21 DC_GPIO_HPD4_RECV 22 22 DC_GPIO_HPD5_MASK 24 24 DC_GPIO_HPD5_PD_DIS 25 25 DC_GPIO_HPD5_RECV 26 26 DC_GPIO_HPD6_MASK 28 28 DC_GPIO_HPD6_PD_DIS 29 29 DC_GPIO_HPD6_RECV 30 30 mmDC_GPIO_HPD_Y 0 0x196f 6 0 4294967295 DC_GPIO_HPD1_Y 0 0 DC_GPIO_HPD2_Y 8 8 DC_GPIO_HPD3_Y 16 16 DC_GPIO_HPD4_Y 24 24 DC_GPIO_HPD5_Y 26 26 DC_GPIO_HPD6_Y 28 28 mmDC_GPIO_I2CPAD_A 0 0x1975 2 0 4294967295 DC_GPIO_SCL_A 0 0 DC_GPIO_SDA_A 1 1 mmDC_GPIO_I2CPAD_EN 0 0x1976 2 0 4294967295 DC_GPIO_SCL_EN 0 0 DC_GPIO_SDA_EN 1 1 mmDC_GPIO_I2CPAD_MASK 0 0x1974 6 0 4294967295 DC_GPIO_SCL_MASK 0 0 DC_GPIO_SCL_PD_DIS 1 1 DC_GPIO_SCL_RECV 2 2 DC_GPIO_SDA_MASK 4 4 DC_GPIO_SDA_PD_DIS 5 5 DC_GPIO_SDA_RECV 6 6 mmDC_GPIO_I2CPAD_STRENGTH 0 0x197a 2 0 4294967295 I2C_STRENGTH_SN 0 3 I2C_STRENGTH_SP 4 7 mmDC_GPIO_I2CPAD_Y 0 0x1977 2 0 4294967295 DC_GPIO_SCL_Y 0 0 DC_GPIO_SDA_Y 1 1 mmDC_GPIO_PAD_STRENGTH_1 0 0x1978 4 0 4294967295 GENLK_STRENGTH_SN 0 3 GENLK_STRENGTH_SP 4 7 SYNC_STRENGTH_SN 24 27 SYNC_STRENGTH_SP 28 31 mmDC_GPIO_PAD_STRENGTH_2 0 0x1979 4 0 4294967295 PWRSEQ_STRENGTH_SN 16 19 PWRSEQ_STRENGTH_SP 20 23 STRENGTH_SN 0 3 STRENGTH_SP 4 7 mmDC_GPIO_PWRSEQ_A 0 0x1941 3 0 4294967295 DC_GPIO_BLON_A 0 0 DC_GPIO_DIGON_A 8 8 DC_GPIO_ENA_BL_A 16 16 mmDC_GPIO_PWRSEQ_EN 0 0x1942 4 0 4294967295 DC_GPIO_BLON_EN 0 0 DC_GPIO_DIGON_EN 8 8 DC_GPIO_ENA_BL_EN 16 16 DC_GPIO_VARY_BL_GENERICA_EN 1 1 mmDC_GPIO_PWRSEQ_MASK 0 0x1940 9 0 4294967295 DC_GPIO_BLON_MASK 0 0 DC_GPIO_BLON_PD_DIS 4 4 DC_GPIO_BLON_RECV 6 6 DC_GPIO_DIGON_MASK 8 8 DC_GPIO_DIGON_PD_DIS 12 12 DC_GPIO_DIGON_RECV 14 14 DC_GPIO_ENA_BL_MASK 16 16 DC_GPIO_ENA_BL_PD_DIS 20 20 DC_GPIO_ENA_BL_RECV 22 22 mmDC_GPIO_PWRSEQ_Y 0 0x1943 3 0 4294967295 DC_GPIO_BLON_Y 0 0 DC_GPIO_DIGON_Y 8 8 DC_GPIO_ENA_BL_Y 16 16 mmDC_GPIO_SYNCA_A 0 0x1965 2 0 4294967295 DC_GPIO_HSYNCA_A 0 0 DC_GPIO_VSYNCA_A 8 8 mmDC_GPIO_SYNCA_EN 0 0x1966 2 0 4294967295 DC_GPIO_HSYNCA_EN 0 0 DC_GPIO_VSYNCA_EN 8 8 mmDC_GPIO_SYNCA_MASK 0 0x1964 8 0 4294967295 DC_GPIO_HSYNCA_CRTC_HSYNC_MASK 24 26 DC_GPIO_HSYNCA_MASK 0 0 DC_GPIO_HSYNCA_PD_DIS 4 4 DC_GPIO_HSYNCA_RECV 6 6 DC_GPIO_VSYNCA_CRTC_VSYNC_MASK 28 30 DC_GPIO_VSYNCA_MASK 8 8 DC_GPIO_VSYNCA_PD_DIS 12 12 DC_GPIO_VSYNCA_RECV 14 14 mmDC_GPIO_SYNCA_Y 0 0x1967 2 0 4294967295 DC_GPIO_HSYNCA_Y 0 0 DC_GPIO_VSYNCA_Y 8 8 mmDC_GPU_TIMER_READ 0 0x1929 1 0 4294967295 DC_GPU_TIMER_READ 0 31 mmDC_GPU_TIMER_READ_CNTL 0 0x192a 7 0 4294967295 DC_GPU_TIMER_READ_SELECT 0 5 DC_GPU_TIMER_START_POSITION_D1_VSYNC_NOM 8 10 DC_GPU_TIMER_START_POSITION_D2_VSYNC_NOM 11 13 DC_GPU_TIMER_START_POSITION_D3_VSYNC_NOM 14 16 DC_GPU_TIMER_START_POSITION_D4_VSYNC_NOM 17 19 DC_GPU_TIMER_START_POSITION_D5_VSYNC_NOM 20 22 DC_GPU_TIMER_START_POSITION_D6_VSYNC_NOM 23 25 mmDC_GPU_TIMER_START_POSITION_P_FLIP 0 0x1928 6 0 4294967295 DC_GPU_TIMER_START_POSITION_D1_P_FLIP 0 2 DC_GPU_TIMER_START_POSITION_D2_P_FLIP 4 6 DC_GPU_TIMER_START_POSITION_D3_P_FLIP 8 10 DC_GPU_TIMER_START_POSITION_D4_P_FLIP 12 14 DC_GPU_TIMER_START_POSITION_D5_P_FLIP 16 18 DC_GPU_TIMER_START_POSITION_D6_P_FLIP 20 22 mmDC_GPU_TIMER_START_POSITION_V_UPDATE 0 0x1927 6 0 4294967295 DC_GPU_TIMER_START_POSITION_D1_V_UPDATE 0 2 DC_GPU_TIMER_START_POSITION_D2_V_UPDATE 4 6 DC_GPU_TIMER_START_POSITION_D3_V_UPDATE 8 10 DC_GPU_TIMER_START_POSITION_D4_V_UPDATE 12 14 DC_GPU_TIMER_START_POSITION_D5_V_UPDATE 16 18 DC_GPU_TIMER_START_POSITION_D6_V_UPDATE 20 22 mmDC_HPD1_CONTROL 0 0x1809 3 0 4294967295 DC_HPD1_CONNECTION_TIMER 0 12 DC_HPD1_EN 28 28 DC_HPD1_RX_INT_TIMER 16 25 mmDC_HPD1_FAST_TRAIN_CNTL 0 0x1864 4 0 4294967295 DC_HPD1_CONNECT_AUX_TX_DELAY 0 7 DC_HPD1_CONNECT_AUX_TX_EN 24 24 DC_HPD1_CONNECT_FAST_TRAIN_DELAY 12 19 DC_HPD1_CONNECT_FAST_TRAIN_EN 28 28 mmDC_HPD1_INT_CONTROL 0 0x1808 5 0 4294967295 DC_HPD1_INT_ACK 0 0 DC_HPD1_INT_EN 16 16 DC_HPD1_INT_POLARITY 8 8 DC_HPD1_RX_INT_ACK 20 20 DC_HPD1_RX_INT_EN 24 24 mmDC_HPD1_INT_STATUS 0 0x1807 6 0 4294967295 DC_HPD1_INT_STATUS 0 0 DC_HPD1_RX_INT_STATUS 8 8 DC_HPD1_SENSE_DELAYED 4 4 DC_HPD1_SENSE 1 1 DC_HPD1_TOGGLE_FILT_CON_TIMER_VAL 12 19 DC_HPD1_TOGGLE_FILT_DISCON_TIMER_VAL 24 31 mmDC_HPD1_TOGGLE_FILT_CNTL 0 0x18bc 2 0 4294967295 DC_HPD1_CONNECT_INT_DELAY 0 7 DC_HPD1_DISCONNECT_INT_DELAY 20 27 mmDC_HPD2_CONTROL 0 0x180c 3 0 4294967295 DC_HPD2_CONNECTION_TIMER 0 12 DC_HPD2_EN 28 28 DC_HPD2_RX_INT_TIMER 16 25 mmDC_HPD2_FAST_TRAIN_CNTL 0 0x1865 4 0 4294967295 DC_HPD2_CONNECT_AUX_TX_DELAY 0 7 DC_HPD2_CONNECT_AUX_TX_EN 24 24 DC_HPD2_CONNECT_FAST_TRAIN_DELAY 12 19 DC_HPD2_CONNECT_FAST_TRAIN_EN 28 28 mmDC_HPD2_INT_CONTROL 0 0x180b 5 0 4294967295 DC_HPD2_INT_ACK 0 0 DC_HPD2_INT_EN 16 16 DC_HPD2_INT_POLARITY 8 8 DC_HPD2_RX_INT_ACK 20 20 DC_HPD2_RX_INT_EN 24 24 mmDC_HPD2_INT_STATUS 0 0x180a 6 0 4294967295 DC_HPD2_INT_STATUS 0 0 DC_HPD2_RX_INT_STATUS 8 8 DC_HPD2_SENSE_DELAYED 4 4 DC_HPD2_SENSE 1 1 DC_HPD2_TOGGLE_FILT_CON_TIMER_VAL 12 19 DC_HPD2_TOGGLE_FILT_DISCON_TIMER_VAL 24 31 mmDC_HPD2_TOGGLE_FILT_CNTL 0 0x18bd 2 0 4294967295 DC_HPD2_CONNECT_INT_DELAY 0 7 DC_HPD2_DISCONNECT_INT_DELAY 20 27 mmDC_HPD3_CONTROL 0 0x180f 3 0 4294967295 DC_HPD3_CONNECTION_TIMER 0 12 DC_HPD3_EN 28 28 DC_HPD3_RX_INT_TIMER 16 25 mmDC_HPD3_FAST_TRAIN_CNTL 0 0x1866 4 0 4294967295 DC_HPD3_CONNECT_AUX_TX_DELAY 0 7 DC_HPD3_CONNECT_AUX_TX_EN 24 24 DC_HPD3_CONNECT_FAST_TRAIN_DELAY 12 19 DC_HPD3_CONNECT_FAST_TRAIN_EN 28 28 mmDC_HPD3_INT_CONTROL 0 0x180e 5 0 4294967295 DC_HPD3_INT_ACK 0 0 DC_HPD3_INT_EN 16 16 DC_HPD3_INT_POLARITY 8 8 DC_HPD3_RX_INT_ACK 20 20 DC_HPD3_RX_INT_EN 24 24 mmDC_HPD3_INT_STATUS 0 0x180d 6 0 4294967295 DC_HPD3_INT_STATUS 0 0 DC_HPD3_RX_INT_STATUS 8 8 DC_HPD3_SENSE_DELAYED 4 4 DC_HPD3_SENSE 1 1 DC_HPD3_TOGGLE_FILT_CON_TIMER_VAL 12 19 DC_HPD3_TOGGLE_FILT_DISCON_TIMER_VAL 24 31 mmDC_HPD3_TOGGLE_FILT_CNTL 0 0x18be 2 0 4294967295 DC_HPD3_CONNECT_INT_DELAY 0 7 DC_HPD3_DISCONNECT_INT_DELAY 20 27 mmDC_HPD4_CONTROL 0 0x1812 3 0 4294967295 DC_HPD4_CONNECTION_TIMER 0 12 DC_HPD4_EN 28 28 DC_HPD4_RX_INT_TIMER 16 25 mmDC_HPD4_FAST_TRAIN_CNTL 0 0x1867 4 0 4294967295 DC_HPD4_CONNECT_AUX_TX_DELAY 0 7 DC_HPD4_CONNECT_AUX_TX_EN 24 24 DC_HPD4_CONNECT_FAST_TRAIN_DELAY 12 19 DC_HPD4_CONNECT_FAST_TRAIN_EN 28 28 mmDC_HPD4_INT_CONTROL 0 0x1811 5 0 4294967295 DC_HPD4_INT_ACK 0 0 DC_HPD4_INT_EN 16 16 DC_HPD4_INT_POLARITY 8 8 DC_HPD4_RX_INT_ACK 20 20 DC_HPD4_RX_INT_EN 24 24 mmDC_HPD4_INT_STATUS 0 0x1810 6 0 4294967295 DC_HPD4_INT_STATUS 0 0 DC_HPD4_RX_INT_STATUS 8 8 DC_HPD4_SENSE_DELAYED 4 4 DC_HPD4_SENSE 1 1 DC_HPD4_TOGGLE_FILT_CON_TIMER_VAL 12 19 DC_HPD4_TOGGLE_FILT_DISCON_TIMER_VAL 24 31 mmDC_HPD4_TOGGLE_FILT_CNTL 0 0x18fc 2 0 4294967295 DC_HPD4_CONNECT_INT_DELAY 0 7 DC_HPD4_DISCONNECT_INT_DELAY 20 27 mmDC_HPD5_CONTROL 0 0x1815 3 0 4294967295 DC_HPD5_CONNECTION_TIMER 0 12 DC_HPD5_EN 28 28 DC_HPD5_RX_INT_TIMER 16 25 mmDC_HPD5_FAST_TRAIN_CNTL 0 0x1868 4 0 4294967295 DC_HPD5_CONNECT_AUX_TX_DELAY 0 7 DC_HPD5_CONNECT_AUX_TX_EN 24 24 DC_HPD5_CONNECT_FAST_TRAIN_DELAY 12 19 DC_HPD5_CONNECT_FAST_TRAIN_EN 28 28 mmDC_HPD5_INT_CONTROL 0 0x1814 5 0 4294967295 DC_HPD5_INT_ACK 0 0 DC_HPD5_INT_EN 16 16 DC_HPD5_INT_POLARITY 8 8 DC_HPD5_RX_INT_ACK 20 20 DC_HPD5_RX_INT_EN 24 24 mmDC_HPD5_INT_STATUS 0 0x1813 6 0 4294967295 DC_HPD5_INT_STATUS 0 0 DC_HPD5_RX_INT_STATUS 8 8 DC_HPD5_SENSE_DELAYED 4 4 DC_HPD5_SENSE 1 1 DC_HPD5_TOGGLE_FILT_CON_TIMER_VAL 12 19 DC_HPD5_TOGGLE_FILT_DISCON_TIMER_VAL 24 31 mmDC_HPD5_TOGGLE_FILT_CNTL 0 0x18fd 2 0 4294967295 DC_HPD5_CONNECT_INT_DELAY 0 7 DC_HPD5_DISCONNECT_INT_DELAY 20 27 mmDC_HPD6_CONTROL 0 0x1818 3 0 4294967295 DC_HPD6_CONNECTION_TIMER 0 12 DC_HPD6_EN 28 28 DC_HPD6_RX_INT_TIMER 16 25 mmDC_HPD6_FAST_TRAIN_CNTL 0 0x1869 4 0 4294967295 DC_HPD6_CONNECT_AUX_TX_DELAY 0 7 DC_HPD6_CONNECT_AUX_TX_EN 24 24 DC_HPD6_CONNECT_FAST_TRAIN_DELAY 12 19 DC_HPD6_CONNECT_FAST_TRAIN_EN 28 28 mmDC_HPD6_INT_CONTROL 0 0x1817 5 0 4294967295 DC_HPD6_INT_ACK 0 0 DC_HPD6_INT_EN 16 16 DC_HPD6_INT_POLARITY 8 8 DC_HPD6_RX_INT_ACK 20 20 DC_HPD6_RX_INT_EN 24 24 mmDC_HPD6_INT_STATUS 0 0x1816 6 0 4294967295 DC_HPD6_INT_STATUS 0 0 DC_HPD6_RX_INT_STATUS 8 8 DC_HPD6_SENSE_DELAYED 4 4 DC_HPD6_SENSE 1 1 DC_HPD6_TOGGLE_FILT_CON_TIMER_VAL 12 19 DC_HPD6_TOGGLE_FILT_DISCON_TIMER_VAL 24 31 mmDC_HPD6_TOGGLE_FILT_CNTL 0 0x18fe 2 0 4294967295 DC_HPD6_CONNECT_INT_DELAY 0 7 DC_HPD6_DISCONNECT_INT_DELAY 20 27 mmDC_I2C_ARBITRATION 0 0x181a 9 0 4294967295 DC_I2C_ABORT_HW_XFER 8 8 DC_I2C_ABORT_SW_XFER 12 12 DC_I2C_DMCU_DONE_USING_I2C_REG 25 25 DC_I2C_DMCU_USE_I2C_REG_REQ 24 24 DC_I2C_NO_QUEUED_SW_GO 4 4 DC_I2C_REG_RW_CNTL_STATUS 2 3 DC_I2C_SW_DONE_USING_I2C_REG 21 21 DC_I2C_SW_PRIORITY 0 1 DC_I2C_SW_USE_I2C_REG_REQ 20 20 mmDC_I2C_CONTROL 0 0x1819 7 0 4294967295 DC_I2C_DBG_REF_SEL 31 31 DC_I2C_DDC_SELECT 8 10 DC_I2C_GO 0 0 DC_I2C_SEND_RESET 2 2 DC_I2C_SOFT_RESET 1 1 DC_I2C_SW_STATUS_RESET 3 3 DC_I2C_TRANSACTION_COUNT 20 21 mmDC_I2C_DATA 0 0x1833 4 0 4294967295 DC_I2C_DATA 8 15 DC_I2C_DATA_RW 0 0 DC_I2C_INDEX 16 23 DC_I2C_INDEX_WRITE 31 31 mmDC_I2C_DDC1_HW_STATUS 0 0x181d 7 0 4294967295 DC_I2C_DDC1_EDID_DETECT_NUM_VALID_TRIES 24 27 DC_I2C_DDC1_EDID_DETECT_STATE 28 30 DC_I2C_DDC1_EDID_DETECT_STATUS 20 20 DC_I2C_DDC1_HW_DONE 3 3 DC_I2C_DDC1_HW_REQ 16 16 DC_I2C_DDC1_HW_STATUS 0 1 DC_I2C_DDC1_HW_URG 17 17 mmDC_I2C_DDC1_SETUP 0 0x1824 9 0 4294967295 DC_I2C_DDC1_CLK_DRIVE_EN 7 7 DC_I2C_DDC1_DATA_DRIVE_EN 0 0 DC_I2C_DDC1_DATA_DRIVE_SEL 1 1 DC_I2C_DDC1_EDID_DETECT_ENABLE 4 4 DC_I2C_DDC1_EDID_DETECT_MODE 5 5 DC_I2C_DDC1_ENABLE 6 6 DC_I2C_DDC1_INTRA_BYTE_DELAY 8 15 DC_I2C_DDC1_INTRA_TRANSACTION_DELAY 16 23 DC_I2C_DDC1_TIME_LIMIT 24 31 mmDC_I2C_DDC1_SPEED 0 0x1823 3 0 4294967295 DC_I2C_DDC1_DISABLE_FILTER_DURING_STALL 4 4 DC_I2C_DDC1_PRESCALE 16 31 DC_I2C_DDC1_THRESHOLD 0 1 mmDC_I2C_DDC2_HW_STATUS 0 0x181e 7 0 4294967295 DC_I2C_DDC2_EDID_DETECT_NUM_VALID_TRIES 24 27 DC_I2C_DDC2_EDID_DETECT_STATE 28 30 DC_I2C_DDC2_EDID_DETECT_STATUS 20 20 DC_I2C_DDC2_HW_DONE 3 3 DC_I2C_DDC2_HW_REQ 16 16 DC_I2C_DDC2_HW_STATUS 0 1 DC_I2C_DDC2_HW_URG 17 17 mmDC_I2C_DDC2_SETUP 0 0x1826 9 0 4294967295 DC_I2C_DDC2_CLK_DRIVE_EN 7 7 DC_I2C_DDC2_DATA_DRIVE_EN 0 0 DC_I2C_DDC2_DATA_DRIVE_SEL 1 1 DC_I2C_DDC2_EDID_DETECT_ENABLE 4 4 DC_I2C_DDC2_EDID_DETECT_MODE 5 5 DC_I2C_DDC2_ENABLE 6 6 DC_I2C_DDC2_INTRA_BYTE_DELAY 8 15 DC_I2C_DDC2_INTRA_TRANSACTION_DELAY 16 23 DC_I2C_DDC2_TIME_LIMIT 24 31 mmDC_I2C_DDC2_SPEED 0 0x1825 3 0 4294967295 DC_I2C_DDC2_DISABLE_FILTER_DURING_STALL 4 4 DC_I2C_DDC2_PRESCALE 16 31 DC_I2C_DDC2_THRESHOLD 0 1 mmDC_I2C_DDC3_HW_STATUS 0 0x181f 7 0 4294967295 DC_I2C_DDC3_EDID_DETECT_NUM_VALID_TRIES 24 27 DC_I2C_DDC3_EDID_DETECT_STATE 28 30 DC_I2C_DDC3_EDID_DETECT_STATUS 20 20 DC_I2C_DDC3_HW_DONE 3 3 DC_I2C_DDC3_HW_REQ 16 16 DC_I2C_DDC3_HW_STATUS 0 1 DC_I2C_DDC3_HW_URG 17 17 mmDC_I2C_DDC3_SETUP 0 0x1828 9 0 4294967295 DC_I2C_DDC3_CLK_DRIVE_EN 7 7 DC_I2C_DDC3_DATA_DRIVE_EN 0 0 DC_I2C_DDC3_DATA_DRIVE_SEL 1 1 DC_I2C_DDC3_EDID_DETECT_ENABLE 4 4 DC_I2C_DDC3_EDID_DETECT_MODE 5 5 DC_I2C_DDC3_ENABLE 6 6 DC_I2C_DDC3_INTRA_BYTE_DELAY 8 15 DC_I2C_DDC3_INTRA_TRANSACTION_DELAY 16 23 DC_I2C_DDC3_TIME_LIMIT 24 31 mmDC_I2C_DDC3_SPEED 0 0x1827 3 0 4294967295 DC_I2C_DDC3_DISABLE_FILTER_DURING_STALL 4 4 DC_I2C_DDC3_PRESCALE 16 31 DC_I2C_DDC3_THRESHOLD 0 1 mmDC_I2C_DDC4_HW_STATUS 0 0x1820 7 0 4294967295 DC_I2C_DDC4_EDID_DETECT_NUM_VALID_TRIES 24 27 DC_I2C_DDC4_EDID_DETECT_STATE 28 30 DC_I2C_DDC4_EDID_DETECT_STATUS 20 20 DC_I2C_DDC4_HW_DONE 3 3 DC_I2C_DDC4_HW_REQ 16 16 DC_I2C_DDC4_HW_STATUS 0 1 DC_I2C_DDC4_HW_URG 17 17 mmDC_I2C_DDC4_SETUP 0 0x182a 9 0 4294967295 DC_I2C_DDC4_CLK_DRIVE_EN 7 7 DC_I2C_DDC4_DATA_DRIVE_EN 0 0 DC_I2C_DDC4_DATA_DRIVE_SEL 1 1 DC_I2C_DDC4_EDID_DETECT_ENABLE 4 4 DC_I2C_DDC4_EDID_DETECT_MODE 5 5 DC_I2C_DDC4_ENABLE 6 6 DC_I2C_DDC4_INTRA_BYTE_DELAY 8 15 DC_I2C_DDC4_INTRA_TRANSACTION_DELAY 16 23 DC_I2C_DDC4_TIME_LIMIT 24 31 mmDC_I2C_DDC4_SPEED 0 0x1829 3 0 4294967295 DC_I2C_DDC4_DISABLE_FILTER_DURING_STALL 4 4 DC_I2C_DDC4_PRESCALE 16 31 DC_I2C_DDC4_THRESHOLD 0 1 mmDC_I2C_DDC5_HW_STATUS 0 0x1821 7 0 4294967295 DC_I2C_DDC5_EDID_DETECT_NUM_VALID_TRIES 24 27 DC_I2C_DDC5_EDID_DETECT_STATE 28 30 DC_I2C_DDC5_EDID_DETECT_STATUS 20 20 DC_I2C_DDC5_HW_DONE 3 3 DC_I2C_DDC5_HW_REQ 16 16 DC_I2C_DDC5_HW_STATUS 0 1 DC_I2C_DDC5_HW_URG 17 17 mmDC_I2C_DDC5_SETUP 0 0x182c 9 0 4294967295 DC_I2C_DDC5_CLK_DRIVE_EN 7 7 DC_I2C_DDC5_DATA_DRIVE_EN 0 0 DC_I2C_DDC5_DATA_DRIVE_SEL 1 1 DC_I2C_DDC5_EDID_DETECT_ENABLE 4 4 DC_I2C_DDC5_EDID_DETECT_MODE 5 5 DC_I2C_DDC5_ENABLE 6 6 DC_I2C_DDC5_INTRA_BYTE_DELAY 8 15 DC_I2C_DDC5_INTRA_TRANSACTION_DELAY 16 23 DC_I2C_DDC5_TIME_LIMIT 24 31 mmDC_I2C_DDC5_SPEED 0 0x182b 3 0 4294967295 DC_I2C_DDC5_DISABLE_FILTER_DURING_STALL 4 4 DC_I2C_DDC5_PRESCALE 16 31 DC_I2C_DDC5_THRESHOLD 0 1 mmDC_I2C_DDC6_HW_STATUS 0 0x1822 7 0 4294967295 DC_I2C_DDC6_EDID_DETECT_NUM_VALID_TRIES 24 27 DC_I2C_DDC6_EDID_DETECT_STATE 28 30 DC_I2C_DDC6_EDID_DETECT_STATUS 20 20 DC_I2C_DDC6_HW_DONE 3 3 DC_I2C_DDC6_HW_REQ 16 16 DC_I2C_DDC6_HW_STATUS 0 1 DC_I2C_DDC6_HW_URG 17 17 mmDC_I2C_DDC6_SETUP 0 0x182e 9 0 4294967295 DC_I2C_DDC6_CLK_DRIVE_EN 7 7 DC_I2C_DDC6_DATA_DRIVE_EN 0 0 DC_I2C_DDC6_DATA_DRIVE_SEL 1 1 DC_I2C_DDC6_EDID_DETECT_ENABLE 4 4 DC_I2C_DDC6_EDID_DETECT_MODE 5 5 DC_I2C_DDC6_ENABLE 6 6 DC_I2C_DDC6_INTRA_BYTE_DELAY 8 15 DC_I2C_DDC6_INTRA_TRANSACTION_DELAY 16 23 DC_I2C_DDC6_TIME_LIMIT 24 31 mmDC_I2C_DDC6_SPEED 0 0x182d 3 0 4294967295 DC_I2C_DDC6_DISABLE_FILTER_DURING_STALL 4 4 DC_I2C_DDC6_PRESCALE 16 31 DC_I2C_DDC6_THRESHOLD 0 1 mmDC_I2C_DDCVGA_HW_STATUS 0 0x1855 7 0 4294967295 DC_I2C_DDCVGA_EDID_DETECT_NUM_VALID_TRIES 24 27 DC_I2C_DDCVGA_EDID_DETECT_STATE 28 30 DC_I2C_DDCVGA_EDID_DETECT_STATUS 20 20 DC_I2C_DDCVGA_HW_DONE 3 3 DC_I2C_DDCVGA_HW_REQ 16 16 DC_I2C_DDCVGA_HW_STATUS 0 1 DC_I2C_DDCVGA_HW_URG 17 17 mmDC_I2C_DDCVGA_SETUP 0 0x1857 9 0 4294967295 DC_I2C_DDCVGA_CLK_DRIVE_EN 7 7 DC_I2C_DDCVGA_DATA_DRIVE_EN 0 0 DC_I2C_DDCVGA_DATA_DRIVE_SEL 1 1 DC_I2C_DDCVGA_EDID_DETECT_ENABLE 4 4 DC_I2C_DDCVGA_EDID_DETECT_MODE 5 5 DC_I2C_DDCVGA_ENABLE 6 6 DC_I2C_DDCVGA_INTRA_BYTE_DELAY 8 15 DC_I2C_DDCVGA_INTRA_TRANSACTION_DELAY 16 23 DC_I2C_DDCVGA_TIME_LIMIT 24 31 mmDC_I2C_DDCVGA_SPEED 0 0x1856 3 0 4294967295 DC_I2C_DDCVGA_DISABLE_FILTER_DURING_STALL 4 4 DC_I2C_DDCVGA_PRESCALE 16 31 DC_I2C_DDCVGA_THRESHOLD 0 1 mmDC_I2C_EDID_DETECT_CTRL 0 0x186f 3 0 4294967295 DC_I2C_EDID_DETECT_NUM_TRIES_UNTIL_VALID 20 23 DC_I2C_EDID_DETECT_SEND_RESET 28 28 DC_I2C_EDID_DETECT_WAIT_TIME 0 15 mmDC_I2C_INTERRUPT_CONTROL 0 0x181b 24 0 4294967295 DC_I2C_DDC1_HW_DONE_ACK 5 5 DC_I2C_DDC1_HW_DONE_INT 4 4 DC_I2C_DDC1_HW_DONE_MASK 6 6 DC_I2C_DDC2_HW_DONE_ACK 9 9 DC_I2C_DDC2_HW_DONE_INT 8 8 DC_I2C_DDC2_HW_DONE_MASK 10 10 DC_I2C_DDC3_HW_DONE_ACK 13 13 DC_I2C_DDC3_HW_DONE_INT 12 12 DC_I2C_DDC3_HW_DONE_MASK 14 14 DC_I2C_DDC4_HW_DONE_ACK 17 17 DC_I2C_DDC4_HW_DONE_INT 16 16 DC_I2C_DDC4_HW_DONE_MASK 18 18 DC_I2C_DDC5_HW_DONE_ACK 21 21 DC_I2C_DDC5_HW_DONE_INT 20 20 DC_I2C_DDC5_HW_DONE_MASK 22 22 DC_I2C_DDC6_HW_DONE_ACK 25 25 DC_I2C_DDC6_HW_DONE_INT 24 24 DC_I2C_DDC6_HW_DONE_MASK 26 26 DC_I2C_DDCVGA_HW_DONE_ACK 28 28 DC_I2C_DDCVGA_HW_DONE_INT 27 27 DC_I2C_DDCVGA_HW_DONE_MASK 29 29 DC_I2C_SW_DONE_ACK 1 1 DC_I2C_SW_DONE_INT 0 0 DC_I2C_SW_DONE_MASK 2 2 mmDC_I2C_SW_STATUS 0 0x181c 12 0 4294967295 DC_I2C_SW_ABORTED 4 4 DC_I2C_SW_BUFFER_OVERFLOW 7 7 DC_I2C_SW_DONE 2 2 DC_I2C_SW_INTERRUPTED 6 6 DC_I2C_SW_NACK0 12 12 DC_I2C_SW_NACK1 13 13 DC_I2C_SW_NACK2 14 14 DC_I2C_SW_NACK3 15 15 DC_I2C_SW_REQ 18 18 DC_I2C_SW_STATUS 0 1 DC_I2C_SW_STOPPED_ON_NACK 8 8 DC_I2C_SW_TIMEOUT 5 5 mmDC_I2C_TRANSACTION0 0 0x182f 5 0 4294967295 DC_I2C_COUNT0 16 23 DC_I2C_RW0 0 0 DC_I2C_START0 12 12 DC_I2C_STOP0 13 13 DC_I2C_STOP_ON_NACK0 8 8 mmDC_I2C_TRANSACTION1 0 0x1830 5 0 4294967295 DC_I2C_COUNT1 16 23 DC_I2C_RW1 0 0 DC_I2C_START1 12 12 DC_I2C_STOP1 13 13 DC_I2C_STOP_ON_NACK1 8 8 mmDC_I2C_TRANSACTION2 0 0x1831 5 0 4294967295 DC_I2C_COUNT2 16 23 DC_I2C_RW2 0 0 DC_I2C_START2 12 12 DC_I2C_STOP2 13 13 DC_I2C_STOP_ON_NACK2 8 8 mmDC_I2C_TRANSACTION3 0 0x1832 5 0 4294967295 DC_I2C_COUNT3 16 23 DC_I2C_RW3 0 0 DC_I2C_START3 12 12 DC_I2C_STOP3 13 13 DC_I2C_STOP_ON_NACK3 8 8 mmDCI_CLK_CNTL 0 0x31e 20 0 4294967295 DCI_PG_TEST_CLK_SEL 27 31 DCI_TEST_CLK_SEL 0 4 DISPCLK_G_DMCU_GATE_DIS 15 15 DISPCLK_G_DMIF0_GATE_DIS 16 16 DISPCLK_G_DMIF1_GATE_DIS 17 17 DISPCLK_G_DMIF2_GATE_DIS 18 18 DISPCLK_G_DMIF3_GATE_DIS 19 19 DISPCLK_G_DMIF4_GATE_DIS 20 20 DISPCLK_G_DMIF5_GATE_DIS 21 21 DISPCLK_G_FBC_GATE_DIS 9 9 DISPCLK_G_VGA_GATE_DIS 11 11 DISPCLK_G_VIP_GATE_DIS 13 13 DISPCLK_M_GATE_DIS 6 6 DISPCLK_R_DCI_GATE_DIS 5 5 DISPCLK_R_DMCU_GATE_DIS 14 14 DISPCLK_R_VGA_GATE_DIS 10 10 DISPCLK_R_VIP_GATE_DIS 12 12 SCLK_G_DMIF_GATE_DIS 22 22 SCLK_G_DMIFTRK_GATE_DIS 23 23 SCLK_R_AZ_GATE_DIS 8 8 mmDCI_CLK_RAMP_CNTL 0 0x324 0 0 4294967295 mmDCI_DEBUG_CONFIG 0 0x323 1 0 4294967295 DCI_DBG_SEL 0 3 mmDCI_MEM_PWR_CNTL 0 0x326 18 0 4294967295 DMIF0_ASYNC_LIGHT_SLEEP_DIS 0 0 DMIF0_ASYNC_MEM_PWR_STATE 12 13 DMIF0_ASYNC_MEM_SHUTDOWN_DIS 6 6 DMIF1_ASYNC_LIGHT_SLEEP_DIS 1 1 DMIF1_ASYNC_MEM_PWR_STATE 14 15 DMIF1_ASYNC_MEM_SHUTDOWN_DIS 7 7 DMIF2_ASYNC_LIGHT_SLEEP_DIS 2 2 DMIF2_ASYNC_MEM_PWR_STATE 16 17 DMIF2_ASYNC_MEM_SHUTDOWN_DIS 8 8 DMIF3_ASYNC_LIGHT_SLEEP_DIS 3 3 DMIF3_ASYNC_MEM_PWR_STATE 18 19 DMIF3_ASYNC_MEM_SHUTDOWN_DIS 9 9 DMIF4_ASYNC_LIGHT_SLEEP_DIS 4 4 DMIF4_ASYNC_MEM_PWR_STATE 20 21 DMIF4_ASYNC_MEM_SHUTDOWN_DIS 10 10 DMIF5_ASYNC_LIGHT_SLEEP_DIS 5 5 DMIF5_ASYNC_MEM_PWR_STATE 22 23 DMIF5_ASYNC_MEM_SHUTDOWN_DIS 11 11 mmDCI_MEM_PWR_STATE 0 0x31b 15 0 4294967295 AZ_MEM_PWR_STATE 22 23 DMCU_IRAM_PWR_STATE 28 29 DMCU_MEM_PWR_STATE 0 1 DMIF0_MEM_PWR_STATE 2 3 DMIF1_MEM_PWR_STATE 4 5 DMIF2_MEM_PWR_STATE 6 7 DMIF3_MEM_PWR_STATE 8 9 DMIF4_MEM_PWR_STATE 10 11 DMIF5_MEM_PWR_STATE 12 13 DMIF_XLR_MEM1_PWR_STATE 26 27 DMIF_XLR_MEM_PWR_STATE 24 25 FBC_MEM_PWR_STATE 16 17 MCIF_MEM_PWR_STATE 18 19 VGA_MEM_PWR_STATE 14 15 VIP_MEM_PWR_STATE 20 21 mmDCI_MEM_PWR_STATE2 0 0x322 3 0 4294967295 DMCU_ERAM1_PWR_STATE 0 1 DMCU_ERAM2_PWR_STATE 2 3 DMCU_ERAM3_PWR_STATE 4 5 mmDCIO_DEBUG 0 0x192e 1 0 4294967295 DCIO_DEBUG 0 31 mmDCIO_GSL0_CNTL 0 0x1924 3 0 4294967295 DCIO_GSL0_GLOBAL_UNLOCK_SEL 16 18 DCIO_GSL0_TIMING_SYNC_SEL 8 10 DCIO_GSL0_VSYNC_SEL 0 2 mmDCIO_GSL1_CNTL 0 0x1925 3 0 4294967295 DCIO_GSL1_GLOBAL_UNLOCK_SEL 16 18 DCIO_GSL1_TIMING_SYNC_SEL 8 10 DCIO_GSL1_VSYNC_SEL 0 2 mmDCIO_GSL2_CNTL 0 0x1926 3 0 4294967295 DCIO_GSL2_GLOBAL_UNLOCK_SEL 16 18 DCIO_GSL2_TIMING_SYNC_SEL 8 10 DCIO_GSL2_VSYNC_SEL 0 2 mmDCIO_GSL_GENLK_PAD_CNTL 0 0x1922 6 0 4294967295 DCIO_GENLK_CLK_GSL_FLIP_LOCK_SEL 4 5 DCIO_GENLK_CLK_GSL_MASK 8 9 DCIO_GENLK_CLK_GSL_TIMING_SYNC_SEL 0 1 DCIO_GENLK_VSYNC_GSL_FLIP_LOCK_SEL 20 21 DCIO_GENLK_VSYNC_GSL_MASK 24 25 DCIO_GENLK_VSYNC_GSL_TIMING_SYNC_SEL 16 17 mmDCIO_GSL_SWAPLOCK_PAD_CNTL 0 0x1923 6 0 4294967295 DCIO_SWAPLOCK_A_GSL_FLIP_LOCK_SEL 4 5 DCIO_SWAPLOCK_A_GSL_MASK 8 9 DCIO_SWAPLOCK_A_GSL_TIMING_SYNC_SEL 0 1 DCIO_SWAPLOCK_B_GSL_FLIP_LOCK_SEL 20 21 DCIO_SWAPLOCK_B_GSL_MASK 24 25 DCIO_SWAPLOCK_B_GSL_TIMING_SYNC_SEL 16 17 mmDCIO_IMPCAL_CNTL_AB 0 0x190d 4 0 4294967295 CALR_CNTL_OVERRIDE 0 3 IMPCAL_ARB_STATE 12 14 IMPCAL_SOFT_RESET 5 5 IMPCAL_STATUS 8 9 mmDCIO_IMPCAL_CNTL_CD 0 0x1911 4 0 4294967295 CALR_CNTL_OVERRIDE 0 3 IMPCAL_ARB_STATE 12 14 IMPCAL_SOFT_RESET 5 5 IMPCAL_STATUS 8 9 mmDCIO_IMPCAL_CNTL_EF 0 0x1915 4 0 4294967295 CALR_CNTL_OVERRIDE 0 3 IMPCAL_ARB_STATE 12 14 IMPCAL_SOFT_RESET 5 5 IMPCAL_STATUS 8 9 mmDCIO_TEST_DEBUG_DATA 0 0x1930 1 0 4294967295 DCIO_TEST_DEBUG_DATA 0 31 mmDCIO_TEST_DEBUG_INDEX 0 0x192f 2 0 4294967295 DCIO_TEST_DEBUG_INDEX 0 7 DCIO_TEST_DEBUG_WRITE_EN 8 8 mmDCIO_UNIPHY0_UNIPHY_ANG_BIST_CNTL 0 0x198c 0 0 4294967295 mmDCIO_UNIPHY0_UNIPHY_CHANNEL_XBAR_CNTL 0 0x198e 0 0 4294967295 mmDCIO_UNIPHY0_UNIPHY_DATA_SYNCHRONIZATION 0 0x198a 0 0 4294967295 mmDCIO_UNIPHY0_UNIPHY_LINK_CNTL 0 0x198d 0 0 4294967295 mmDCIO_UNIPHY0_UNIPHY_PLL_CONTROL1 0 0x1986 0 0 4294967295 mmDCIO_UNIPHY0_UNIPHY_PLL_CONTROL2 0 0x1987 0 0 4294967295 mmDCIO_UNIPHY0_UNIPHY_PLL_FBDIV 0 0x1985 0 0 4294967295 mmDCIO_UNIPHY0_UNIPHY_PLL_SS_CNTL 0 0x1989 0 0 4294967295 mmDCIO_UNIPHY0_UNIPHY_PLL_SS_STEP_SIZE 0 0x1988 0 0 4294967295 mmDCIO_UNIPHY0_UNIPHY_POWER_CONTROL 0 0x1984 0 0 4294967295 mmDCIO_UNIPHY0_UNIPHY_REG_TEST_OUTPUT 0 0x198b 0 0 4294967295 mmDCIO_UNIPHY0_UNIPHY_TX_CONTROL1 0 0x1980 0 0 4294967295 mmDCIO_UNIPHY0_UNIPHY_TX_CONTROL2 0 0x1981 0 0 4294967295 mmDCIO_UNIPHY0_UNIPHY_TX_CONTROL3 0 0x1982 0 0 4294967295 mmDCIO_UNIPHY0_UNIPHY_TX_CONTROL4 0 0x1983 0 0 4294967295 mmDCIO_UNIPHY1_UNIPHY_ANG_BIST_CNTL 0 0x199c 0 0 4294967295 mmDCIO_UNIPHY1_UNIPHY_CHANNEL_XBAR_CNTL 0 0x199e 0 0 4294967295 mmDCIO_UNIPHY1_UNIPHY_DATA_SYNCHRONIZATION 0 0x199a 0 0 4294967295 mmDCIO_UNIPHY1_UNIPHY_LINK_CNTL 0 0x199d 0 0 4294967295 mmDCIO_UNIPHY1_UNIPHY_PLL_CONTROL1 0 0x1996 0 0 4294967295 mmDCIO_UNIPHY1_UNIPHY_PLL_CONTROL2 0 0x1997 0 0 4294967295 mmDCIO_UNIPHY1_UNIPHY_PLL_FBDIV 0 0x1995 0 0 4294967295 mmDCIO_UNIPHY1_UNIPHY_PLL_SS_CNTL 0 0x1999 0 0 4294967295 mmDCIO_UNIPHY1_UNIPHY_PLL_SS_STEP_SIZE 0 0x1998 0 0 4294967295 mmDCIO_UNIPHY1_UNIPHY_POWER_CONTROL 0 0x1994 0 0 4294967295 mmDCIO_UNIPHY1_UNIPHY_REG_TEST_OUTPUT 0 0x199b 0 0 4294967295 mmDCIO_UNIPHY1_UNIPHY_TX_CONTROL1 0 0x1990 0 0 4294967295 mmDCIO_UNIPHY1_UNIPHY_TX_CONTROL2 0 0x1991 0 0 4294967295 mmDCIO_UNIPHY1_UNIPHY_TX_CONTROL3 0 0x1992 0 0 4294967295 mmDCIO_UNIPHY1_UNIPHY_TX_CONTROL4 0 0x1993 0 0 4294967295 mmDCIO_UNIPHY2_UNIPHY_ANG_BIST_CNTL 0 0x19ac 0 0 4294967295 mmDCIO_UNIPHY2_UNIPHY_CHANNEL_XBAR_CNTL 0 0x19ae 0 0 4294967295 mmDCIO_UNIPHY2_UNIPHY_DATA_SYNCHRONIZATION 0 0x19aa 0 0 4294967295 mmDCIO_UNIPHY2_UNIPHY_LINK_CNTL 0 0x19ad 0 0 4294967295 mmDCIO_UNIPHY2_UNIPHY_PLL_CONTROL1 0 0x19a6 0 0 4294967295 mmDCIO_UNIPHY2_UNIPHY_PLL_CONTROL2 0 0x19a7 0 0 4294967295 mmDCIO_UNIPHY2_UNIPHY_PLL_FBDIV 0 0x19a5 0 0 4294967295 mmDCIO_UNIPHY2_UNIPHY_PLL_SS_CNTL 0 0x19a9 0 0 4294967295 mmDCIO_UNIPHY2_UNIPHY_PLL_SS_STEP_SIZE 0 0x19a8 0 0 4294967295 mmDCIO_UNIPHY2_UNIPHY_POWER_CONTROL 0 0x19a4 0 0 4294967295 mmDCIO_UNIPHY2_UNIPHY_REG_TEST_OUTPUT 0 0x19ab 0 0 4294967295 mmDCIO_UNIPHY2_UNIPHY_TX_CONTROL1 0 0x19a0 0 0 4294967295 mmDCIO_UNIPHY2_UNIPHY_TX_CONTROL2 0 0x19a1 0 0 4294967295 mmDCIO_UNIPHY2_UNIPHY_TX_CONTROL3 0 0x19a2 0 0 4294967295 mmDCIO_UNIPHY2_UNIPHY_TX_CONTROL4 0 0x19a3 0 0 4294967295 mmDCIO_UNIPHY3_UNIPHY_ANG_BIST_CNTL 0 0x19bc 0 0 4294967295 mmDCIO_UNIPHY3_UNIPHY_CHANNEL_XBAR_CNTL 0 0x19be 0 0 4294967295 mmDCIO_UNIPHY3_UNIPHY_DATA_SYNCHRONIZATION 0 0x19ba 0 0 4294967295 mmDCIO_UNIPHY3_UNIPHY_LINK_CNTL 0 0x19bd 0 0 4294967295 mmDCIO_UNIPHY3_UNIPHY_PLL_CONTROL1 0 0x19b6 0 0 4294967295 mmDCIO_UNIPHY3_UNIPHY_PLL_CONTROL2 0 0x19b7 0 0 4294967295 mmDCIO_UNIPHY3_UNIPHY_PLL_FBDIV 0 0x19b5 0 0 4294967295 mmDCIO_UNIPHY3_UNIPHY_PLL_SS_CNTL 0 0x19b9 0 0 4294967295 mmDCIO_UNIPHY3_UNIPHY_PLL_SS_STEP_SIZE 0 0x19b8 0 0 4294967295 mmDCIO_UNIPHY3_UNIPHY_POWER_CONTROL 0 0x19b4 0 0 4294967295 mmDCIO_UNIPHY3_UNIPHY_REG_TEST_OUTPUT 0 0x19bb 0 0 4294967295 mmDCIO_UNIPHY3_UNIPHY_TX_CONTROL1 0 0x19b0 0 0 4294967295 mmDCIO_UNIPHY3_UNIPHY_TX_CONTROL2 0 0x19b1 0 0 4294967295 mmDCIO_UNIPHY3_UNIPHY_TX_CONTROL3 0 0x19b2 0 0 4294967295 mmDCIO_UNIPHY3_UNIPHY_TX_CONTROL4 0 0x19b3 0 0 4294967295 mmDCIO_UNIPHY4_UNIPHY_ANG_BIST_CNTL 0 0x19cc 0 0 4294967295 mmDCIO_UNIPHY4_UNIPHY_CHANNEL_XBAR_CNTL 0 0x19ce 0 0 4294967295 mmDCIO_UNIPHY4_UNIPHY_DATA_SYNCHRONIZATION 0 0x19ca 0 0 4294967295 mmDCIO_UNIPHY4_UNIPHY_LINK_CNTL 0 0x19cd 0 0 4294967295 mmDCIO_UNIPHY4_UNIPHY_PLL_CONTROL1 0 0x19c6 0 0 4294967295 mmDCIO_UNIPHY4_UNIPHY_PLL_CONTROL2 0 0x19c7 0 0 4294967295 mmDCIO_UNIPHY4_UNIPHY_PLL_FBDIV 0 0x19c5 0 0 4294967295 mmDCIO_UNIPHY4_UNIPHY_PLL_SS_CNTL 0 0x19c9 0 0 4294967295 mmDCIO_UNIPHY4_UNIPHY_PLL_SS_STEP_SIZE 0 0x19c8 0 0 4294967295 mmDCIO_UNIPHY4_UNIPHY_POWER_CONTROL 0 0x19c4 0 0 4294967295 mmDCIO_UNIPHY4_UNIPHY_REG_TEST_OUTPUT 0 0x19cb 0 0 4294967295 mmDCIO_UNIPHY4_UNIPHY_TX_CONTROL1 0 0x19c0 0 0 4294967295 mmDCIO_UNIPHY4_UNIPHY_TX_CONTROL2 0 0x19c1 0 0 4294967295 mmDCIO_UNIPHY4_UNIPHY_TX_CONTROL3 0 0x19c2 0 0 4294967295 mmDCIO_UNIPHY4_UNIPHY_TX_CONTROL4 0 0x19c3 0 0 4294967295 mmDCIO_UNIPHY5_UNIPHY_ANG_BIST_CNTL 0 0x19dc 0 0 4294967295 mmDCIO_UNIPHY5_UNIPHY_CHANNEL_XBAR_CNTL 0 0x19de 0 0 4294967295 mmDCIO_UNIPHY5_UNIPHY_DATA_SYNCHRONIZATION 0 0x19da 0 0 4294967295 mmDCIO_UNIPHY5_UNIPHY_LINK_CNTL 0 0x19dd 0 0 4294967295 mmDCIO_UNIPHY5_UNIPHY_PLL_CONTROL1 0 0x19d6 0 0 4294967295 mmDCIO_UNIPHY5_UNIPHY_PLL_CONTROL2 0 0x19d7 0 0 4294967295 mmDCIO_UNIPHY5_UNIPHY_PLL_FBDIV 0 0x19d5 0 0 4294967295 mmDCIO_UNIPHY5_UNIPHY_PLL_SS_CNTL 0 0x19d9 0 0 4294967295 mmDCIO_UNIPHY5_UNIPHY_PLL_SS_STEP_SIZE 0 0x19d8 0 0 4294967295 mmDCIO_UNIPHY5_UNIPHY_POWER_CONTROL 0 0x19d4 0 0 4294967295 mmDCIO_UNIPHY5_UNIPHY_REG_TEST_OUTPUT 0 0x19db 0 0 4294967295 mmDCIO_UNIPHY5_UNIPHY_TX_CONTROL1 0 0x19d0 0 0 4294967295 mmDCIO_UNIPHY5_UNIPHY_TX_CONTROL2 0 0x19d1 0 0 4294967295 mmDCIO_UNIPHY5_UNIPHY_TX_CONTROL3 0 0x19d2 0 0 4294967295 mmDCIO_UNIPHY5_UNIPHY_TX_CONTROL4 0 0x19d3 0 0 4294967295 mmDCI_SOFT_RESET 0 0x15e 11 0 4294967295 DMIF0_SOFT_RESET 4 4 DMIF1_SOFT_RESET 5 5 DMIF2_SOFT_RESET 6 6 DMIF3_SOFT_RESET 7 7 DMIF4_SOFT_RESET 8 8 DMIF5_SOFT_RESET 9 9 DMIFARB_SOFT_RESET 12 12 FBC_SOFT_RESET 3 3 MCIF_SOFT_RESET 2 2 VGA_SOFT_RESET 0 0 VIP_SOFT_RESET 1 1 mmDCI_TEST_DEBUG_DATA 0 0x321 1 0 4294967295 DCI_TEST_DEBUG_DATA 0 31 mmDCI_TEST_DEBUG_INDEX 0 0x320 2 0 4294967295 DCI_TEST_DEBUG_INDEX 0 7 DCI_TEST_DEBUG_WRITE_EN 8 8 mmDC_LUT_30_COLOR 0 0x1a7c 3 0 4294967295 DC_LUT_COLOR_10_BLUE 0 9 DC_LUT_COLOR_10_GREEN 10 19 DC_LUT_COLOR_10_RED 20 29 mmDC_LUT_AUTOFILL 0 0x1a7f 2 0 4294967295 DC_LUT_AUTOFILL_DONE 1 1 DC_LUT_AUTOFILL 0 0 mmDC_LUT_BLACK_OFFSET_BLUE 0 0x1a81 1 0 4294967295 DC_LUT_BLACK_OFFSET_BLUE 0 15 mmDC_LUT_BLACK_OFFSET_GREEN 0 0x1a82 1 0 4294967295 DC_LUT_BLACK_OFFSET_GREEN 0 15 mmDC_LUT_BLACK_OFFSET_RED 0 0x1a83 1 0 4294967295 DC_LUT_BLACK_OFFSET_RED 0 15 mmDC_LUT_CONTROL 0 0x1a80 12 0 4294967295 DC_LUT_DATA_B_FLOAT_POINT_EN 5 5 DC_LUT_DATA_B_FORMAT 6 7 DC_LUT_DATA_B_SIGNED_EN 4 4 DC_LUT_DATA_G_FLOAT_POINT_EN 13 13 DC_LUT_DATA_G_FORMAT 14 15 DC_LUT_DATA_G_SIGNED_EN 12 12 DC_LUT_DATA_R_FLOAT_POINT_EN 21 21 DC_LUT_DATA_R_FORMAT 22 23 DC_LUT_DATA_R_SIGNED_EN 20 20 DC_LUT_INC_B 0 3 DC_LUT_INC_G 8 11 DC_LUT_INC_R 16 19 mmDC_LUT_PWL_DATA 0 0x1a7b 2 0 4294967295 DC_LUT_BASE 0 15 DC_LUT_DELTA 16 31 mmDC_LUT_RW_INDEX 0 0x1a79 1 0 4294967295 DC_LUT_RW_INDEX 0 7 mmDC_LUT_RW_MODE 0 0x1a78 1 0 4294967295 DC_LUT_RW_MODE 0 0 mmDC_LUT_SEQ_COLOR 0 0x1a7a 1 0 4294967295 DC_LUT_SEQ_COLOR 0 15 mmDC_LUT_VGA_ACCESS_ENABLE 0 0x1a7d 1 0 4294967295 DC_LUT_VGA_ACCESS_ENABLE 0 0 mmDC_LUT_WHITE_OFFSET_BLUE 0 0x1a84 1 0 4294967295 DC_LUT_WHITE_OFFSET_BLUE 0 15 mmDC_LUT_WHITE_OFFSET_GREEN 0 0x1a85 1 0 4294967295 DC_LUT_WHITE_OFFSET_GREEN 0 15 mmDC_LUT_WHITE_OFFSET_RED 0 0x1a86 1 0 4294967295 DC_LUT_WHITE_OFFSET_RED 0 15 mmDC_LUT_WRITE_EN_MASK 0 0x1a7e 1 0 4294967295 DC_LUT_WRITE_EN_MASK 0 2 mmDC_MVP_LB_CONTROL 0 0x1adb 7 0 4294967295 DC_MVP_SPARE_FLOPS 31 31 DC_MVP_SWAP_LOCK_IN_CAP 28 28 DC_MVP_SWAP_LOCK_OUT_FORCE_ONE 12 12 DC_MVP_SWAP_LOCK_OUT_FORCE_ZERO 16 16 DC_MVP_SWAP_LOCK_OUT_SEL 8 8 DC_MVP_SWAP_LOCK_STATUS 20 20 MVP_SWAP_LOCK_IN_MODE 0 1 mmDCO_CLK_CNTL 0 0x192b 19 0 4294967295 DCO_TEST_CLK_SEL 0 4 DISPCLK_G_ABM_GATE_DIS 6 6 DISPCLK_G_DACA_GATE_DIS 8 8 DISPCLK_G_DACB_GATE_DIS 9 9 DISPCLK_G_DIGA_GATE_DIS 24 24 DISPCLK_G_DIGB_GATE_DIS 25 25 DISPCLK_G_DIGC_GATE_DIS 26 26 DISPCLK_G_DIGD_GATE_DIS 27 27 DISPCLK_G_DIGE_GATE_DIS 28 28 DISPCLK_G_DIGF_GATE_DIS 29 29 DISPCLK_G_DVO_GATE_DIS 7 7 DISPCLK_G_FMT0_GATE_DIS 16 16 DISPCLK_G_FMT1_GATE_DIS 17 17 DISPCLK_G_FMT2_GATE_DIS 18 18 DISPCLK_G_FMT3_GATE_DIS 19 19 DISPCLK_G_FMT4_GATE_DIS 20 20 DISPCLK_G_FMT5_GATE_DIS 21 21 DISPCLK_R_ABM_GATE_DIS 12 12 DISPCLK_R_DCO_GATE_DIS 5 5 mmDCO_CLK_RAMP_CNTL 0 0x192c 18 0 4294967295 DISPCLK_G_ABM_RAMP_DIS 6 6 DISPCLK_G_DACA_RAMP_DIS 8 8 DISPCLK_G_DACB_RAMP_DIS 9 9 DISPCLK_G_DIGA_RAMP_DIS 24 24 DISPCLK_G_DIGB_RAMP_DIS 25 25 DISPCLK_G_DIGC_RAMP_DIS 26 26 DISPCLK_G_DIGD_RAMP_DIS 27 27 DISPCLK_G_DIGE_RAMP_DIS 28 28 DISPCLK_G_DIGF_RAMP_DIS 29 29 DISPCLK_G_DVO_RAMP_DIS 7 7 DISPCLK_G_FMT0_RAMP_DIS 16 16 DISPCLK_G_FMT1_RAMP_DIS 17 17 DISPCLK_G_FMT2_RAMP_DIS 18 18 DISPCLK_G_FMT3_RAMP_DIS 19 19 DISPCLK_G_FMT4_RAMP_DIS 20 20 DISPCLK_G_FMT5_RAMP_DIS 21 21 DISPCLK_R_ABM_RAMP_DIS 12 12 DISPCLK_R_DCO_RAMP_DIS 5 5 mmDCO_LIGHT_SLEEP_DIS 0 0x1907 22 0 4294967295 DPA_LIGHT_SLEEP_DIS 3 3 DPA_MEM_SHUTDOWN_DIS 17 17 DPB_LIGHT_SLEEP_DIS 4 4 DPB_MEM_SHUTDOWN_DIS 18 18 DPC_LIGHT_SLEEP_DIS 5 5 DPC_MEM_SHUTDOWN_DIS 19 19 DPD_LIGHT_SLEEP_DIS 6 6 DPD_MEM_SHUTDOWN_DIS 20 20 DPE_LIGHT_SLEEP_DIS 7 7 DPE_MEM_SHUTDOWN_DIS 21 21 DPF_LIGHT_SLEEP_DIS 8 8 DPF_MEM_SHUTDOWN_DIS 22 22 HDMI0_LIGHT_SLEEP_DIS 9 9 HDMI1_LIGHT_SLEEP_DIS 10 10 HDMI2_LIGHT_SLEEP_DIS 11 11 HDMI3_LIGHT_SLEEP_DIS 12 12 HDMI4_LIGHT_SLEEP_DIS 13 13 HDMI5_LIGHT_SLEEP_DIS 14 14 I2C_LIGHT_SLEEP_FORCE 1 1 MVP_LIGHT_SLEEP_DIS 2 2 MVP_MEM_SHUTDOWN_DIS 16 16 TVOUT_LIGHT_SLEEP_DIS 0 0 mmDCO_MEM_POWER_STATE 0 0x1906 15 0 4294967295 DPA_MEM_PWR_STATE 6 7 DPB_MEM_PWR_STATE 8 9 DPC_MEM_PWR_STATE 10 11 DPD_MEM_PWR_STATE 12 13 DPE_MEM_PWR_STATE 14 15 DPF_MEM_PWR_STATE 16 17 HDMI0_MEM_PWR_STATE 18 19 HDMI1_MEM_PWR_STATE 20 21 HDMI2_MEM_PWR_STATE 22 23 HDMI3_MEM_PWR_STATE 24 25 HDMI4_MEM_PWR_STATE 26 27 HDMI5_MEM_PWR_STATE 28 29 I2C_MEM_PWR_STATE 2 3 MVP_MEM_PWR_STATE 4 5 TVOUT_MEM_PWR_STATE 0 1 mmDCO_SOFT_RESET 0 0x167 16 0 4294967295 ABM_SOFT_RESET 25 25 DACA_CFG_IF_SOFT_RESET 29 29 DACA_SOFT_RESET 0 0 DACB_SOFT_RESET 1 1 DVO_ENABLE_RST 3 3 DVO_SOFT_RESET 27 27 FMT0_SOFT_RESET 16 16 FMT1_SOFT_RESET 17 17 FMT2_SOFT_RESET 18 18 FMT3_SOFT_RESET 19 19 FMT4_SOFT_RESET 20 20 FMT5_SOFT_RESET 21 21 MVP_SOFT_RESET 24 24 SOFT_RESET_DVO 2 2 SRBM_SOFT_RESET_ENABLE 28 28 TVOUT_SOFT_RESET 26 26 mmDCP0_COMM_MATRIXA_TRANS_C11_C12 0 0x1a43 0 0 4294967295 mmDCP0_COMM_MATRIXA_TRANS_C13_C14 0 0x1a44 0 0 4294967295 mmDCP0_COMM_MATRIXA_TRANS_C21_C22 0 0x1a45 0 0 4294967295 mmDCP0_COMM_MATRIXA_TRANS_C23_C24 0 0x1a46 0 0 4294967295 mmDCP0_COMM_MATRIXA_TRANS_C31_C32 0 0x1a47 0 0 4294967295 mmDCP0_COMM_MATRIXA_TRANS_C33_C34 0 0x1a48 0 0 4294967295 mmDCP0_COMM_MATRIXB_TRANS_C11_C12 0 0x1a49 0 0 4294967295 mmDCP0_COMM_MATRIXB_TRANS_C13_C14 0 0x1a4a 0 0 4294967295 mmDCP0_COMM_MATRIXB_TRANS_C21_C22 0 0x1a4b 0 0 4294967295 mmDCP0_COMM_MATRIXB_TRANS_C23_C24 0 0x1a4c 0 0 4294967295 mmDCP0_COMM_MATRIXB_TRANS_C31_C32 0 0x1a4d 0 0 4294967295 mmDCP0_COMM_MATRIXB_TRANS_C33_C34 0 0x1a4e 0 0 4294967295 mmDCP0_CUR_COLOR1 0 0x1a6c 0 0 4294967295 mmDCP0_CUR_COLOR2 0 0x1a6d 0 0 4294967295 mmDCP0_CUR_CONTROL 0 0x1a66 0 0 4294967295 mmDCP0_CUR_HOT_SPOT 0 0x1a6b 0 0 4294967295 mmDCP0_CUR_POSITION 0 0x1a6a 0 0 4294967295 mmDCP0_CUR_REQUEST_FILTER_CNTL 0 0x1a99 0 0 4294967295 mmDCP0_CUR_SIZE 0 0x1a68 0 0 4294967295 mmDCP0_CUR_SURFACE_ADDRESS 0 0x1a67 0 0 4294967295 mmDCP0_CUR_SURFACE_ADDRESS_HIGH 0 0x1a69 0 0 4294967295 mmDCP0_CUR_UPDATE 0 0x1a6e 0 0 4294967295 mmDCP0_DC_LUT_30_COLOR 0 0x1a7c 0 0 4294967295 mmDCP0_DC_LUT_AUTOFILL 0 0x1a7f 0 0 4294967295 mmDCP0_DC_LUT_BLACK_OFFSET_BLUE 0 0x1a81 0 0 4294967295 mmDCP0_DC_LUT_BLACK_OFFSET_GREEN 0 0x1a82 0 0 4294967295 mmDCP0_DC_LUT_BLACK_OFFSET_RED 0 0x1a83 0 0 4294967295 mmDCP0_DC_LUT_CONTROL 0 0x1a80 0 0 4294967295 mmDCP0_DC_LUT_PWL_DATA 0 0x1a7b 0 0 4294967295 mmDCP0_DC_LUT_RW_INDEX 0 0x1a79 0 0 4294967295 mmDCP0_DC_LUT_RW_MODE 0 0x1a78 0 0 4294967295 mmDCP0_DC_LUT_SEQ_COLOR 0 0x1a7a 0 0 4294967295 mmDCP0_DC_LUT_VGA_ACCESS_ENABLE 0 0x1a7d 0 0 4294967295 mmDCP0_DC_LUT_WHITE_OFFSET_BLUE 0 0x1a84 0 0 4294967295 mmDCP0_DC_LUT_WHITE_OFFSET_GREEN 0 0x1a85 0 0 4294967295 mmDCP0_DC_LUT_WHITE_OFFSET_RED 0 0x1a86 0 0 4294967295 mmDCP0_DC_LUT_WRITE_EN_MASK 0 0x1a7e 0 0 4294967295 mmDCP0_DCP_CRC_CONTROL 0 0x1a87 0 0 4294967295 mmDCP0_DCP_CRC_CURRENT 0 0x1a89 0 0 4294967295 mmDCP0_DCP_CRC_LAST 0 0x1a8b 0 0 4294967295 mmDCP0_DCP_CRC_MASK 0 0x1a88 0 0 4294967295 mmDCP0_DCP_DEBUG 0 0x1a8d 0 0 4294967295 mmDCP0_DCP_DEBUG2 0 0x1a98 0 0 4294967295 mmDCP0_DCP_FP_CONVERTED_FIELD 0 0x1a65 0 0 4294967295 mmDCP0_DCP_GSL_CONTROL 0 0x1a90 0 0 4294967295 mmDCP0_DCP_LB_DATA_GAP_BETWEEN_CHUNK 0 0x1a91 0 0 4294967295 mmDCP0_DCP_RANDOM_SEEDS 0 0x1a61 0 0 4294967295 mmDCP0_DCP_SPATIAL_DITHER_CNTL 0 0x1a60 0 0 4294967295 mmDCP0_DCP_TEST_DEBUG_DATA 0 0x1a96 0 0 4294967295 mmDCP0_DCP_TEST_DEBUG_INDEX 0 0x1a95 0 0 4294967295 mmDCP0_DEGAMMA_CONTROL 0 0x1a58 0 0 4294967295 mmDCP0_DENORM_CONTROL 0 0x1a50 0 0 4294967295 mmDCP0_GAMUT_REMAP_C11_C12 0 0x1a5a 0 0 4294967295 mmDCP0_GAMUT_REMAP_C13_C14 0 0x1a5b 0 0 4294967295 mmDCP0_GAMUT_REMAP_C21_C22 0 0x1a5c 0 0 4294967295 mmDCP0_GAMUT_REMAP_C23_C24 0 0x1a5d 0 0 4294967295 mmDCP0_GAMUT_REMAP_C31_C32 0 0x1a5e 0 0 4294967295 mmDCP0_GAMUT_REMAP_C33_C34 0 0x1a5f 0 0 4294967295 mmDCP0_GAMUT_REMAP_CONTROL 0 0x1a59 0 0 4294967295 mmDCP0_GRPH_COMPRESS_PITCH 0 0x1a1a 0 0 4294967295 mmDCP0_GRPH_COMPRESS_SURFACE_ADDRESS 0 0x1a19 0 0 4294967295 mmDCP0_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH 0 0x1a1b 0 0 4294967295 mmDCP0_GRPH_CONTROL 0 0x1a01 0 0 4294967295 mmDCP0_GRPH_DFQ_CONTROL 0 0x1a14 0 0 4294967295 mmDCP0_GRPH_DFQ_STATUS 0 0x1a15 0 0 4294967295 mmDCP0_GRPH_ENABLE 0 0x1a00 0 0 4294967295 mmDCP0_GRPH_FLIP_CONTROL 0 0x1a12 0 0 4294967295 mmDCP0_GRPH_INTERRUPT_CONTROL 0 0x1a17 0 0 4294967295 mmDCP0_GRPH_INTERRUPT_STATUS 0 0x1a16 0 0 4294967295 mmDCP0_GRPH_LUT_10BIT_BYPASS 0 0x1a02 0 0 4294967295 mmDCP0_GRPH_PITCH 0 0x1a06 0 0 4294967295 mmDCP0_GRPH_PRIMARY_SURFACE_ADDRESS 0 0x1a04 0 0 4294967295 mmDCP0_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH 0 0x1a07 0 0 4294967295 mmDCP0_GRPH_SECONDARY_SURFACE_ADDRESS 0 0x1a05 0 0 4294967295 mmDCP0_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH 0 0x1a08 0 0 4294967295 mmDCP0_GRPH_STEREOSYNC_FLIP 0 0x1a97 0 0 4294967295 mmDCP0_GRPH_SURFACE_ADDRESS_HIGH_INUSE 0 0x1a18 0 0 4294967295 mmDCP0_GRPH_SURFACE_ADDRESS_INUSE 0 0x1a13 0 0 4294967295 mmDCP0_GRPH_SURFACE_OFFSET_X 0 0x1a09 0 0 4294967295 mmDCP0_GRPH_SURFACE_OFFSET_Y 0 0x1a0a 0 0 4294967295 mmDCP0_GRPH_SWAP_CNTL 0 0x1a03 0 0 4294967295 mmDCP0_GRPH_UPDATE 0 0x1a11 0 0 4294967295 mmDCP0_GRPH_X_END 0 0x1a0d 0 0 4294967295 mmDCP0_GRPH_X_START 0 0x1a0b 0 0 4294967295 mmDCP0_GRPH_Y_END 0 0x1a0e 0 0 4294967295 mmDCP0_GRPH_Y_START 0 0x1a0c 0 0 4294967295 mmDCP0_INPUT_CSC_C11_C12 0 0x1a36 0 0 4294967295 mmDCP0_INPUT_CSC_C13_C14 0 0x1a37 0 0 4294967295 mmDCP0_INPUT_CSC_C21_C22 0 0x1a38 0 0 4294967295 mmDCP0_INPUT_CSC_C23_C24 0 0x1a39 0 0 4294967295 mmDCP0_INPUT_CSC_C31_C32 0 0x1a3a 0 0 4294967295 mmDCP0_INPUT_CSC_C33_C34 0 0x1a3b 0 0 4294967295 mmDCP0_INPUT_CSC_CONTROL 0 0x1a35 0 0 4294967295 mmDCP0_INPUT_GAMMA_CONTROL 0 0x1a10 0 0 4294967295 mmDCP0_KEY_CONTROL 0 0x1a53 0 0 4294967295 mmDCP0_KEY_RANGE_ALPHA 0 0x1a54 0 0 4294967295 mmDCP0_KEY_RANGE_BLUE 0 0x1a57 0 0 4294967295 mmDCP0_KEY_RANGE_GREEN 0 0x1a56 0 0 4294967295 mmDCP0_KEY_RANGE_RED 0 0x1a55 0 0 4294967295 mmDCP0_OUTPUT_CSC_C11_C12 0 0x1a3d 0 0 4294967295 mmDCP0_OUTPUT_CSC_C13_C14 0 0x1a3e 0 0 4294967295 mmDCP0_OUTPUT_CSC_C21_C22 0 0x1a3f 0 0 4294967295 mmDCP0_OUTPUT_CSC_C23_C24 0 0x1a40 0 0 4294967295 mmDCP0_OUTPUT_CSC_C31_C32 0 0x1a41 0 0 4294967295 mmDCP0_OUTPUT_CSC_C33_C34 0 0x1a42 0 0 4294967295 mmDCP0_OUTPUT_CSC_CONTROL 0 0x1a3c 0 0 4294967295 mmDCP0_OUT_ROUND_CONTROL 0 0x1a51 0 0 4294967295 mmDCP0_OVL_CONTROL1 0 0x1a1d 0 0 4294967295 mmDCP0_OVL_CONTROL2 0 0x1a1e 0 0 4294967295 mmDCP0_OVL_DFQ_CONTROL 0 0x1a29 0 0 4294967295 mmDCP0_OVL_DFQ_STATUS 0 0x1a2a 0 0 4294967295 mmDCP0_OVL_ENABLE 0 0x1a1c 0 0 4294967295 mmDCP0_OVL_END 0 0x1a26 0 0 4294967295 mmDCP0_OVL_PITCH 0 0x1a21 0 0 4294967295 mmDCP0_OVLSCL_EDGE_PIXEL_CNTL 0 0x1a2c 0 0 4294967295 mmDCP0_OVL_SECONDARY_SURFACE_ADDRESS 0 0x1a92 0 0 4294967295 mmDCP0_OVL_SECONDARY_SURFACE_ADDRESS_HIGH 0 0x1a94 0 0 4294967295 mmDCP0_OVL_START 0 0x1a25 0 0 4294967295 mmDCP0_OVL_STEREOSYNC_FLIP 0 0x1a93 0 0 4294967295 mmDCP0_OVL_SURFACE_ADDRESS 0 0x1a20 0 0 4294967295 mmDCP0_OVL_SURFACE_ADDRESS_HIGH 0 0x1a22 0 0 4294967295 mmDCP0_OVL_SURFACE_ADDRESS_HIGH_INUSE 0 0x1a2b 0 0 4294967295 mmDCP0_OVL_SURFACE_ADDRESS_INUSE 0 0x1a28 0 0 4294967295 mmDCP0_OVL_SURFACE_OFFSET_X 0 0x1a23 0 0 4294967295 mmDCP0_OVL_SURFACE_OFFSET_Y 0 0x1a24 0 0 4294967295 mmDCP0_OVL_SWAP_CNTL 0 0x1a1f 0 0 4294967295 mmDCP0_OVL_UPDATE 0 0x1a27 0 0 4294967295 mmDCP0_PRESCALE_GRPH_CONTROL 0 0x1a2d 0 0 4294967295 mmDCP0_PRESCALE_OVL_CONTROL 0 0x1a31 0 0 4294967295 mmDCP0_PRESCALE_VALUES_GRPH_B 0 0x1a30 0 0 4294967295 mmDCP0_PRESCALE_VALUES_GRPH_G 0 0x1a2f 0 0 4294967295 mmDCP0_PRESCALE_VALUES_GRPH_R 0 0x1a2e 0 0 4294967295 mmDCP0_PRESCALE_VALUES_OVL_CB 0 0x1a32 0 0 4294967295 mmDCP0_PRESCALE_VALUES_OVL_CR 0 0x1a34 0 0 4294967295 mmDCP0_PRESCALE_VALUES_OVL_Y 0 0x1a33 0 0 4294967295 mmDCP0_REGAMMA_CNTLA_END_CNTL1 0 0x1aa6 0 0 4294967295 mmDCP0_REGAMMA_CNTLA_END_CNTL2 0 0x1aa7 0 0 4294967295 mmDCP0_REGAMMA_CNTLA_REGION_0_1 0 0x1aa8 0 0 4294967295 mmDCP0_REGAMMA_CNTLA_REGION_10_11 0 0x1aad 0 0 4294967295 mmDCP0_REGAMMA_CNTLA_REGION_12_13 0 0x1aae 0 0 4294967295 mmDCP0_REGAMMA_CNTLA_REGION_14_15 0 0x1aaf 0 0 4294967295 mmDCP0_REGAMMA_CNTLA_REGION_2_3 0 0x1aa9 0 0 4294967295 mmDCP0_REGAMMA_CNTLA_REGION_4_5 0 0x1aaa 0 0 4294967295 mmDCP0_REGAMMA_CNTLA_REGION_6_7 0 0x1aab 0 0 4294967295 mmDCP0_REGAMMA_CNTLA_REGION_8_9 0 0x1aac 0 0 4294967295 mmDCP0_REGAMMA_CNTLA_SLOPE_CNTL 0 0x1aa5 0 0 4294967295 mmDCP0_REGAMMA_CNTLA_START_CNTL 0 0x1aa4 0 0 4294967295 mmDCP0_REGAMMA_CNTLB_END_CNTL1 0 0x1ab2 0 0 4294967295 mmDCP0_REGAMMA_CNTLB_END_CNTL2 0 0x1ab3 0 0 4294967295 mmDCP0_REGAMMA_CNTLB_REGION_0_1 0 0x1ab4 0 0 4294967295 mmDCP0_REGAMMA_CNTLB_REGION_10_11 0 0x1ab9 0 0 4294967295 mmDCP0_REGAMMA_CNTLB_REGION_12_13 0 0x1aba 0 0 4294967295 mmDCP0_REGAMMA_CNTLB_REGION_14_15 0 0x1abb 0 0 4294967295 mmDCP0_REGAMMA_CNTLB_REGION_2_3 0 0x1ab5 0 0 4294967295 mmDCP0_REGAMMA_CNTLB_REGION_4_5 0 0x1ab6 0 0 4294967295 mmDCP0_REGAMMA_CNTLB_REGION_6_7 0 0x1ab7 0 0 4294967295 mmDCP0_REGAMMA_CNTLB_REGION_8_9 0 0x1ab8 0 0 4294967295 mmDCP0_REGAMMA_CNTLB_SLOPE_CNTL 0 0x1ab1 0 0 4294967295 mmDCP0_REGAMMA_CNTLB_START_CNTL 0 0x1ab0 0 0 4294967295 mmDCP0_REGAMMA_CONTROL 0 0x1aa0 0 0 4294967295 mmDCP0_REGAMMA_LUT_DATA 0 0x1aa2 0 0 4294967295 mmDCP0_REGAMMA_LUT_INDEX 0 0x1aa1 0 0 4294967295 mmDCP0_REGAMMA_LUT_WRITE_EN_MASK 0 0x1aa3 0 0 4294967295 mmDCP1_COMM_MATRIXA_TRANS_C11_C12 0 0x1d43 0 0 4294967295 mmDCP1_COMM_MATRIXA_TRANS_C13_C14 0 0x1d44 0 0 4294967295 mmDCP1_COMM_MATRIXA_TRANS_C21_C22 0 0x1d45 0 0 4294967295 mmDCP1_COMM_MATRIXA_TRANS_C23_C24 0 0x1d46 0 0 4294967295 mmDCP1_COMM_MATRIXA_TRANS_C31_C32 0 0x1d47 0 0 4294967295 mmDCP1_COMM_MATRIXA_TRANS_C33_C34 0 0x1d48 0 0 4294967295 mmDCP1_COMM_MATRIXB_TRANS_C11_C12 0 0x1d49 0 0 4294967295 mmDCP1_COMM_MATRIXB_TRANS_C13_C14 0 0x1d4a 0 0 4294967295 mmDCP1_COMM_MATRIXB_TRANS_C21_C22 0 0x1d4b 0 0 4294967295 mmDCP1_COMM_MATRIXB_TRANS_C23_C24 0 0x1d4c 0 0 4294967295 mmDCP1_COMM_MATRIXB_TRANS_C31_C32 0 0x1d4d 0 0 4294967295 mmDCP1_COMM_MATRIXB_TRANS_C33_C34 0 0x1d4e 0 0 4294967295 mmDCP1_CUR_COLOR1 0 0x1d6c 0 0 4294967295 mmDCP1_CUR_COLOR2 0 0x1d6d 0 0 4294967295 mmDCP1_CUR_CONTROL 0 0x1d66 0 0 4294967295 mmDCP1_CUR_HOT_SPOT 0 0x1d6b 0 0 4294967295 mmDCP1_CUR_POSITION 0 0x1d6a 0 0 4294967295 mmDCP1_CUR_REQUEST_FILTER_CNTL 0 0x1d99 0 0 4294967295 mmDCP1_CUR_SIZE 0 0x1d68 0 0 4294967295 mmDCP1_CUR_SURFACE_ADDRESS 0 0x1d67 0 0 4294967295 mmDCP1_CUR_SURFACE_ADDRESS_HIGH 0 0x1d69 0 0 4294967295 mmDCP1_CUR_UPDATE 0 0x1d6e 0 0 4294967295 mmDCP1_DC_LUT_30_COLOR 0 0x1d7c 0 0 4294967295 mmDCP1_DC_LUT_AUTOFILL 0 0x1d7f 0 0 4294967295 mmDCP1_DC_LUT_BLACK_OFFSET_BLUE 0 0x1d81 0 0 4294967295 mmDCP1_DC_LUT_BLACK_OFFSET_GREEN 0 0x1d82 0 0 4294967295 mmDCP1_DC_LUT_BLACK_OFFSET_RED 0 0x1d83 0 0 4294967295 mmDCP1_DC_LUT_CONTROL 0 0x1d80 0 0 4294967295 mmDCP1_DC_LUT_PWL_DATA 0 0x1d7b 0 0 4294967295 mmDCP1_DC_LUT_RW_INDEX 0 0x1d79 0 0 4294967295 mmDCP1_DC_LUT_RW_MODE 0 0x1d78 0 0 4294967295 mmDCP1_DC_LUT_SEQ_COLOR 0 0x1d7a 0 0 4294967295 mmDCP1_DC_LUT_VGA_ACCESS_ENABLE 0 0x1d7d 0 0 4294967295 mmDCP1_DC_LUT_WHITE_OFFSET_BLUE 0 0x1d84 0 0 4294967295 mmDCP1_DC_LUT_WHITE_OFFSET_GREEN 0 0x1d85 0 0 4294967295 mmDCP1_DC_LUT_WHITE_OFFSET_RED 0 0x1d86 0 0 4294967295 mmDCP1_DC_LUT_WRITE_EN_MASK 0 0x1d7e 0 0 4294967295 mmDCP1_DCP_CRC_CONTROL 0 0x1d87 0 0 4294967295 mmDCP1_DCP_CRC_CURRENT 0 0x1d89 0 0 4294967295 mmDCP1_DCP_CRC_LAST 0 0x1d8b 0 0 4294967295 mmDCP1_DCP_CRC_MASK 0 0x1d88 0 0 4294967295 mmDCP1_DCP_DEBUG 0 0x1d8d 0 0 4294967295 mmDCP1_DCP_DEBUG2 0 0x1d98 0 0 4294967295 mmDCP1_DCP_FP_CONVERTED_FIELD 0 0x1d65 0 0 4294967295 mmDCP1_DCP_GSL_CONTROL 0 0x1d90 0 0 4294967295 mmDCP1_DCP_LB_DATA_GAP_BETWEEN_CHUNK 0 0x1d91 0 0 4294967295 mmDCP1_DCP_RANDOM_SEEDS 0 0x1d61 0 0 4294967295 mmDCP1_DCP_SPATIAL_DITHER_CNTL 0 0x1d60 0 0 4294967295 mmDCP1_DCP_TEST_DEBUG_DATA 0 0x1d96 0 0 4294967295 mmDCP1_DCP_TEST_DEBUG_INDEX 0 0x1d95 0 0 4294967295 mmDCP1_DEGAMMA_CONTROL 0 0x1d58 0 0 4294967295 mmDCP1_DENORM_CONTROL 0 0x1d50 0 0 4294967295 mmDCP1_GAMUT_REMAP_C11_C12 0 0x1d5a 0 0 4294967295 mmDCP1_GAMUT_REMAP_C13_C14 0 0x1d5b 0 0 4294967295 mmDCP1_GAMUT_REMAP_C21_C22 0 0x1d5c 0 0 4294967295 mmDCP1_GAMUT_REMAP_C23_C24 0 0x1d5d 0 0 4294967295 mmDCP1_GAMUT_REMAP_C31_C32 0 0x1d5e 0 0 4294967295 mmDCP1_GAMUT_REMAP_C33_C34 0 0x1d5f 0 0 4294967295 mmDCP1_GAMUT_REMAP_CONTROL 0 0x1d59 0 0 4294967295 mmDCP1_GRPH_COMPRESS_PITCH 0 0x1d1a 0 0 4294967295 mmDCP1_GRPH_COMPRESS_SURFACE_ADDRESS 0 0x1d19 0 0 4294967295 mmDCP1_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH 0 0x1d1b 0 0 4294967295 mmDCP1_GRPH_CONTROL 0 0x1d01 0 0 4294967295 mmDCP1_GRPH_DFQ_CONTROL 0 0x1d14 0 0 4294967295 mmDCP1_GRPH_DFQ_STATUS 0 0x1d15 0 0 4294967295 mmDCP1_GRPH_ENABLE 0 0x1d00 0 0 4294967295 mmDCP1_GRPH_FLIP_CONTROL 0 0x1d12 0 0 4294967295 mmDCP1_GRPH_INTERRUPT_CONTROL 0 0x1d17 0 0 4294967295 mmDCP1_GRPH_INTERRUPT_STATUS 0 0x1d16 0 0 4294967295 mmDCP1_GRPH_LUT_10BIT_BYPASS 0 0x1d02 0 0 4294967295 mmDCP1_GRPH_PITCH 0 0x1d06 0 0 4294967295 mmDCP1_GRPH_PRIMARY_SURFACE_ADDRESS 0 0x1d04 0 0 4294967295 mmDCP1_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH 0 0x1d07 0 0 4294967295 mmDCP1_GRPH_SECONDARY_SURFACE_ADDRESS 0 0x1d05 0 0 4294967295 mmDCP1_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH 0 0x1d08 0 0 4294967295 mmDCP1_GRPH_STEREOSYNC_FLIP 0 0x1d97 0 0 4294967295 mmDCP1_GRPH_SURFACE_ADDRESS_HIGH_INUSE 0 0x1d18 0 0 4294967295 mmDCP1_GRPH_SURFACE_ADDRESS_INUSE 0 0x1d13 0 0 4294967295 mmDCP1_GRPH_SURFACE_OFFSET_X 0 0x1d09 0 0 4294967295 mmDCP1_GRPH_SURFACE_OFFSET_Y 0 0x1d0a 0 0 4294967295 mmDCP1_GRPH_SWAP_CNTL 0 0x1d03 0 0 4294967295 mmDCP1_GRPH_UPDATE 0 0x1d11 0 0 4294967295 mmDCP1_GRPH_X_END 0 0x1d0d 0 0 4294967295 mmDCP1_GRPH_X_START 0 0x1d0b 0 0 4294967295 mmDCP1_GRPH_Y_END 0 0x1d0e 0 0 4294967295 mmDCP1_GRPH_Y_START 0 0x1d0c 0 0 4294967295 mmDCP1_INPUT_CSC_C11_C12 0 0x1d36 0 0 4294967295 mmDCP1_INPUT_CSC_C13_C14 0 0x1d37 0 0 4294967295 mmDCP1_INPUT_CSC_C21_C22 0 0x1d38 0 0 4294967295 mmDCP1_INPUT_CSC_C23_C24 0 0x1d39 0 0 4294967295 mmDCP1_INPUT_CSC_C31_C32 0 0x1d3a 0 0 4294967295 mmDCP1_INPUT_CSC_C33_C34 0 0x1d3b 0 0 4294967295 mmDCP1_INPUT_CSC_CONTROL 0 0x1d35 0 0 4294967295 mmDCP1_INPUT_GAMMA_CONTROL 0 0x1d10 0 0 4294967295 mmDCP1_KEY_CONTROL 0 0x1d53 0 0 4294967295 mmDCP1_KEY_RANGE_ALPHA 0 0x1d54 0 0 4294967295 mmDCP1_KEY_RANGE_BLUE 0 0x1d57 0 0 4294967295 mmDCP1_KEY_RANGE_GREEN 0 0x1d56 0 0 4294967295 mmDCP1_KEY_RANGE_RED 0 0x1d55 0 0 4294967295 mmDCP1_OUTPUT_CSC_C11_C12 0 0x1d3d 0 0 4294967295 mmDCP1_OUTPUT_CSC_C13_C14 0 0x1d3e 0 0 4294967295 mmDCP1_OUTPUT_CSC_C21_C22 0 0x1d3f 0 0 4294967295 mmDCP1_OUTPUT_CSC_C23_C24 0 0x1d40 0 0 4294967295 mmDCP1_OUTPUT_CSC_C31_C32 0 0x1d41 0 0 4294967295 mmDCP1_OUTPUT_CSC_C33_C34 0 0x1d42 0 0 4294967295 mmDCP1_OUTPUT_CSC_CONTROL 0 0x1d3c 0 0 4294967295 mmDCP1_OUT_ROUND_CONTROL 0 0x1d51 0 0 4294967295 mmDCP1_OVL_CONTROL1 0 0x1d1d 0 0 4294967295 mmDCP1_OVL_CONTROL2 0 0x1d1e 0 0 4294967295 mmDCP1_OVL_DFQ_CONTROL 0 0x1d29 0 0 4294967295 mmDCP1_OVL_DFQ_STATUS 0 0x1d2a 0 0 4294967295 mmDCP1_OVL_ENABLE 0 0x1d1c 0 0 4294967295 mmDCP1_OVL_END 0 0x1d26 0 0 4294967295 mmDCP1_OVL_PITCH 0 0x1d21 0 0 4294967295 mmDCP1_OVLSCL_EDGE_PIXEL_CNTL 0 0x1d2c 0 0 4294967295 mmDCP1_OVL_SECONDARY_SURFACE_ADDRESS 0 0x1d92 0 0 4294967295 mmDCP1_OVL_SECONDARY_SURFACE_ADDRESS_HIGH 0 0x1d94 0 0 4294967295 mmDCP1_OVL_START 0 0x1d25 0 0 4294967295 mmDCP1_OVL_STEREOSYNC_FLIP 0 0x1d93 0 0 4294967295 mmDCP1_OVL_SURFACE_ADDRESS 0 0x1d20 0 0 4294967295 mmDCP1_OVL_SURFACE_ADDRESS_HIGH 0 0x1d22 0 0 4294967295 mmDCP1_OVL_SURFACE_ADDRESS_HIGH_INUSE 0 0x1d2b 0 0 4294967295 mmDCP1_OVL_SURFACE_ADDRESS_INUSE 0 0x1d28 0 0 4294967295 mmDCP1_OVL_SURFACE_OFFSET_X 0 0x1d23 0 0 4294967295 mmDCP1_OVL_SURFACE_OFFSET_Y 0 0x1d24 0 0 4294967295 mmDCP1_OVL_SWAP_CNTL 0 0x1d1f 0 0 4294967295 mmDCP1_OVL_UPDATE 0 0x1d27 0 0 4294967295 mmDCP1_PRESCALE_GRPH_CONTROL 0 0x1d2d 0 0 4294967295 mmDCP1_PRESCALE_OVL_CONTROL 0 0x1d31 0 0 4294967295 mmDCP1_PRESCALE_VALUES_GRPH_B 0 0x1d30 0 0 4294967295 mmDCP1_PRESCALE_VALUES_GRPH_G 0 0x1d2f 0 0 4294967295 mmDCP1_PRESCALE_VALUES_GRPH_R 0 0x1d2e 0 0 4294967295 mmDCP1_PRESCALE_VALUES_OVL_CB 0 0x1d32 0 0 4294967295 mmDCP1_PRESCALE_VALUES_OVL_CR 0 0x1d34 0 0 4294967295 mmDCP1_PRESCALE_VALUES_OVL_Y 0 0x1d33 0 0 4294967295 mmDCP1_REGAMMA_CNTLA_END_CNTL1 0 0x1da6 0 0 4294967295 mmDCP1_REGAMMA_CNTLA_END_CNTL2 0 0x1da7 0 0 4294967295 mmDCP1_REGAMMA_CNTLA_REGION_0_1 0 0x1da8 0 0 4294967295 mmDCP1_REGAMMA_CNTLA_REGION_10_11 0 0x1dad 0 0 4294967295 mmDCP1_REGAMMA_CNTLA_REGION_12_13 0 0x1dae 0 0 4294967295 mmDCP1_REGAMMA_CNTLA_REGION_14_15 0 0x1daf 0 0 4294967295 mmDCP1_REGAMMA_CNTLA_REGION_2_3 0 0x1da9 0 0 4294967295 mmDCP1_REGAMMA_CNTLA_REGION_4_5 0 0x1daa 0 0 4294967295 mmDCP1_REGAMMA_CNTLA_REGION_6_7 0 0x1dab 0 0 4294967295 mmDCP1_REGAMMA_CNTLA_REGION_8_9 0 0x1dac 0 0 4294967295 mmDCP1_REGAMMA_CNTLA_SLOPE_CNTL 0 0x1da5 0 0 4294967295 mmDCP1_REGAMMA_CNTLA_START_CNTL 0 0x1da4 0 0 4294967295 mmDCP1_REGAMMA_CNTLB_END_CNTL1 0 0x1db2 0 0 4294967295 mmDCP1_REGAMMA_CNTLB_END_CNTL2 0 0x1db3 0 0 4294967295 mmDCP1_REGAMMA_CNTLB_REGION_0_1 0 0x1db4 0 0 4294967295 mmDCP1_REGAMMA_CNTLB_REGION_10_11 0 0x1db9 0 0 4294967295 mmDCP1_REGAMMA_CNTLB_REGION_12_13 0 0x1dba 0 0 4294967295 mmDCP1_REGAMMA_CNTLB_REGION_14_15 0 0x1dbb 0 0 4294967295 mmDCP1_REGAMMA_CNTLB_REGION_2_3 0 0x1db5 0 0 4294967295 mmDCP1_REGAMMA_CNTLB_REGION_4_5 0 0x1db6 0 0 4294967295 mmDCP1_REGAMMA_CNTLB_REGION_6_7 0 0x1db7 0 0 4294967295 mmDCP1_REGAMMA_CNTLB_REGION_8_9 0 0x1db8 0 0 4294967295 mmDCP1_REGAMMA_CNTLB_SLOPE_CNTL 0 0x1db1 0 0 4294967295 mmDCP1_REGAMMA_CNTLB_START_CNTL 0 0x1db0 0 0 4294967295 mmDCP1_REGAMMA_CONTROL 0 0x1da0 0 0 4294967295 mmDCP1_REGAMMA_LUT_DATA 0 0x1da2 0 0 4294967295 mmDCP1_REGAMMA_LUT_INDEX 0 0x1da1 0 0 4294967295 mmDCP1_REGAMMA_LUT_WRITE_EN_MASK 0 0x1da3 0 0 4294967295 mmDCP2_COMM_MATRIXA_TRANS_C11_C12 0 0x4043 0 0 4294967295 mmDCP2_COMM_MATRIXA_TRANS_C13_C14 0 0x4044 0 0 4294967295 mmDCP2_COMM_MATRIXA_TRANS_C21_C22 0 0x4045 0 0 4294967295 mmDCP2_COMM_MATRIXA_TRANS_C23_C24 0 0x4046 0 0 4294967295 mmDCP2_COMM_MATRIXA_TRANS_C31_C32 0 0x4047 0 0 4294967295 mmDCP2_COMM_MATRIXA_TRANS_C33_C34 0 0x4048 0 0 4294967295 mmDCP2_COMM_MATRIXB_TRANS_C11_C12 0 0x4049 0 0 4294967295 mmDCP2_COMM_MATRIXB_TRANS_C13_C14 0 0x404a 0 0 4294967295 mmDCP2_COMM_MATRIXB_TRANS_C21_C22 0 0x404b 0 0 4294967295 mmDCP2_COMM_MATRIXB_TRANS_C23_C24 0 0x404c 0 0 4294967295 mmDCP2_COMM_MATRIXB_TRANS_C31_C32 0 0x404d 0 0 4294967295 mmDCP2_COMM_MATRIXB_TRANS_C33_C34 0 0x404e 0 0 4294967295 mmDCP2_CUR_COLOR1 0 0x406c 0 0 4294967295 mmDCP2_CUR_COLOR2 0 0x406d 0 0 4294967295 mmDCP2_CUR_CONTROL 0 0x4066 0 0 4294967295 mmDCP2_CUR_HOT_SPOT 0 0x406b 0 0 4294967295 mmDCP2_CUR_POSITION 0 0x406a 0 0 4294967295 mmDCP2_CUR_REQUEST_FILTER_CNTL 0 0x4099 0 0 4294967295 mmDCP2_CUR_SIZE 0 0x4068 0 0 4294967295 mmDCP2_CUR_SURFACE_ADDRESS 0 0x4067 0 0 4294967295 mmDCP2_CUR_SURFACE_ADDRESS_HIGH 0 0x4069 0 0 4294967295 mmDCP2_CUR_UPDATE 0 0x406e 0 0 4294967295 mmDCP2_DC_LUT_30_COLOR 0 0x407c 0 0 4294967295 mmDCP2_DC_LUT_AUTOFILL 0 0x407f 0 0 4294967295 mmDCP2_DC_LUT_BLACK_OFFSET_BLUE 0 0x4081 0 0 4294967295 mmDCP2_DC_LUT_BLACK_OFFSET_GREEN 0 0x4082 0 0 4294967295 mmDCP2_DC_LUT_BLACK_OFFSET_RED 0 0x4083 0 0 4294967295 mmDCP2_DC_LUT_CONTROL 0 0x4080 0 0 4294967295 mmDCP2_DC_LUT_PWL_DATA 0 0x407b 0 0 4294967295 mmDCP2_DC_LUT_RW_INDEX 0 0x4079 0 0 4294967295 mmDCP2_DC_LUT_RW_MODE 0 0x4078 0 0 4294967295 mmDCP2_DC_LUT_SEQ_COLOR 0 0x407a 0 0 4294967295 mmDCP2_DC_LUT_VGA_ACCESS_ENABLE 0 0x407d 0 0 4294967295 mmDCP2_DC_LUT_WHITE_OFFSET_BLUE 0 0x4084 0 0 4294967295 mmDCP2_DC_LUT_WHITE_OFFSET_GREEN 0 0x4085 0 0 4294967295 mmDCP2_DC_LUT_WHITE_OFFSET_RED 0 0x4086 0 0 4294967295 mmDCP2_DC_LUT_WRITE_EN_MASK 0 0x407e 0 0 4294967295 mmDCP2_DCP_CRC_CONTROL 0 0x4087 0 0 4294967295 mmDCP2_DCP_CRC_CURRENT 0 0x4089 0 0 4294967295 mmDCP2_DCP_CRC_LAST 0 0x408b 0 0 4294967295 mmDCP2_DCP_CRC_MASK 0 0x4088 0 0 4294967295 mmDCP2_DCP_DEBUG 0 0x408d 0 0 4294967295 mmDCP2_DCP_DEBUG2 0 0x4098 0 0 4294967295 mmDCP2_DCP_FP_CONVERTED_FIELD 0 0x4065 0 0 4294967295 mmDCP2_DCP_GSL_CONTROL 0 0x4090 0 0 4294967295 mmDCP2_DCP_LB_DATA_GAP_BETWEEN_CHUNK 0 0x4091 0 0 4294967295 mmDCP2_DCP_RANDOM_SEEDS 0 0x4061 0 0 4294967295 mmDCP2_DCP_SPATIAL_DITHER_CNTL 0 0x4060 0 0 4294967295 mmDCP2_DCP_TEST_DEBUG_DATA 0 0x4096 0 0 4294967295 mmDCP2_DCP_TEST_DEBUG_INDEX 0 0x4095 0 0 4294967295 mmDCP2_DEGAMMA_CONTROL 0 0x4058 0 0 4294967295 mmDCP2_DENORM_CONTROL 0 0x4050 0 0 4294967295 mmDCP2_GAMUT_REMAP_C11_C12 0 0x405a 0 0 4294967295 mmDCP2_GAMUT_REMAP_C13_C14 0 0x405b 0 0 4294967295 mmDCP2_GAMUT_REMAP_C21_C22 0 0x405c 0 0 4294967295 mmDCP2_GAMUT_REMAP_C23_C24 0 0x405d 0 0 4294967295 mmDCP2_GAMUT_REMAP_C31_C32 0 0x405e 0 0 4294967295 mmDCP2_GAMUT_REMAP_C33_C34 0 0x405f 0 0 4294967295 mmDCP2_GAMUT_REMAP_CONTROL 0 0x4059 0 0 4294967295 mmDCP2_GRPH_COMPRESS_PITCH 0 0x401a 0 0 4294967295 mmDCP2_GRPH_COMPRESS_SURFACE_ADDRESS 0 0x4019 0 0 4294967295 mmDCP2_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH 0 0x401b 0 0 4294967295 mmDCP2_GRPH_CONTROL 0 0x4001 0 0 4294967295 mmDCP2_GRPH_DFQ_CONTROL 0 0x4014 0 0 4294967295 mmDCP2_GRPH_DFQ_STATUS 0 0x4015 0 0 4294967295 mmDCP2_GRPH_ENABLE 0 0x4000 0 0 4294967295 mmDCP2_GRPH_FLIP_CONTROL 0 0x4012 0 0 4294967295 mmDCP2_GRPH_INTERRUPT_CONTROL 0 0x4017 0 0 4294967295 mmDCP2_GRPH_INTERRUPT_STATUS 0 0x4016 0 0 4294967295 mmDCP2_GRPH_LUT_10BIT_BYPASS 0 0x4002 0 0 4294967295 mmDCP2_GRPH_PITCH 0 0x4006 0 0 4294967295 mmDCP2_GRPH_PRIMARY_SURFACE_ADDRESS 0 0x4004 0 0 4294967295 mmDCP2_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH 0 0x4007 0 0 4294967295 mmDCP2_GRPH_SECONDARY_SURFACE_ADDRESS 0 0x4005 0 0 4294967295 mmDCP2_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH 0 0x4008 0 0 4294967295 mmDCP2_GRPH_STEREOSYNC_FLIP 0 0x4097 0 0 4294967295 mmDCP2_GRPH_SURFACE_ADDRESS_HIGH_INUSE 0 0x4018 0 0 4294967295 mmDCP2_GRPH_SURFACE_ADDRESS_INUSE 0 0x4013 0 0 4294967295 mmDCP2_GRPH_SURFACE_OFFSET_X 0 0x4009 0 0 4294967295 mmDCP2_GRPH_SURFACE_OFFSET_Y 0 0x400a 0 0 4294967295 mmDCP2_GRPH_SWAP_CNTL 0 0x4003 0 0 4294967295 mmDCP2_GRPH_UPDATE 0 0x4011 0 0 4294967295 mmDCP2_GRPH_X_END 0 0x400d 0 0 4294967295 mmDCP2_GRPH_X_START 0 0x400b 0 0 4294967295 mmDCP2_GRPH_Y_END 0 0x400e 0 0 4294967295 mmDCP2_GRPH_Y_START 0 0x400c 0 0 4294967295 mmDCP2_INPUT_CSC_C11_C12 0 0x4036 0 0 4294967295 mmDCP2_INPUT_CSC_C13_C14 0 0x4037 0 0 4294967295 mmDCP2_INPUT_CSC_C21_C22 0 0x4038 0 0 4294967295 mmDCP2_INPUT_CSC_C23_C24 0 0x4039 0 0 4294967295 mmDCP2_INPUT_CSC_C31_C32 0 0x403a 0 0 4294967295 mmDCP2_INPUT_CSC_C33_C34 0 0x403b 0 0 4294967295 mmDCP2_INPUT_CSC_CONTROL 0 0x4035 0 0 4294967295 mmDCP2_INPUT_GAMMA_CONTROL 0 0x4010 0 0 4294967295 mmDCP2_KEY_CONTROL 0 0x4053 0 0 4294967295 mmDCP2_KEY_RANGE_ALPHA 0 0x4054 0 0 4294967295 mmDCP2_KEY_RANGE_BLUE 0 0x4057 0 0 4294967295 mmDCP2_KEY_RANGE_GREEN 0 0x4056 0 0 4294967295 mmDCP2_KEY_RANGE_RED 0 0x4055 0 0 4294967295 mmDCP2_OUTPUT_CSC_C11_C12 0 0x403d 0 0 4294967295 mmDCP2_OUTPUT_CSC_C13_C14 0 0x403e 0 0 4294967295 mmDCP2_OUTPUT_CSC_C21_C22 0 0x403f 0 0 4294967295 mmDCP2_OUTPUT_CSC_C23_C24 0 0x4040 0 0 4294967295 mmDCP2_OUTPUT_CSC_C31_C32 0 0x4041 0 0 4294967295 mmDCP2_OUTPUT_CSC_C33_C34 0 0x4042 0 0 4294967295 mmDCP2_OUTPUT_CSC_CONTROL 0 0x403c 0 0 4294967295 mmDCP2_OUT_ROUND_CONTROL 0 0x4051 0 0 4294967295 mmDCP2_OVL_CONTROL1 0 0x401d 0 0 4294967295 mmDCP2_OVL_CONTROL2 0 0x401e 0 0 4294967295 mmDCP2_OVL_DFQ_CONTROL 0 0x4029 0 0 4294967295 mmDCP2_OVL_DFQ_STATUS 0 0x402a 0 0 4294967295 mmDCP2_OVL_ENABLE 0 0x401c 0 0 4294967295 mmDCP2_OVL_END 0 0x4026 0 0 4294967295 mmDCP2_OVL_PITCH 0 0x4021 0 0 4294967295 mmDCP2_OVLSCL_EDGE_PIXEL_CNTL 0 0x402c 0 0 4294967295 mmDCP2_OVL_SECONDARY_SURFACE_ADDRESS 0 0x4092 0 0 4294967295 mmDCP2_OVL_SECONDARY_SURFACE_ADDRESS_HIGH 0 0x4094 0 0 4294967295 mmDCP2_OVL_START 0 0x4025 0 0 4294967295 mmDCP2_OVL_STEREOSYNC_FLIP 0 0x4093 0 0 4294967295 mmDCP2_OVL_SURFACE_ADDRESS 0 0x4020 0 0 4294967295 mmDCP2_OVL_SURFACE_ADDRESS_HIGH 0 0x4022 0 0 4294967295 mmDCP2_OVL_SURFACE_ADDRESS_HIGH_INUSE 0 0x402b 0 0 4294967295 mmDCP2_OVL_SURFACE_ADDRESS_INUSE 0 0x4028 0 0 4294967295 mmDCP2_OVL_SURFACE_OFFSET_X 0 0x4023 0 0 4294967295 mmDCP2_OVL_SURFACE_OFFSET_Y 0 0x4024 0 0 4294967295 mmDCP2_OVL_SWAP_CNTL 0 0x401f 0 0 4294967295 mmDCP2_OVL_UPDATE 0 0x4027 0 0 4294967295 mmDCP2_PRESCALE_GRPH_CONTROL 0 0x402d 0 0 4294967295 mmDCP2_PRESCALE_OVL_CONTROL 0 0x4031 0 0 4294967295 mmDCP2_PRESCALE_VALUES_GRPH_B 0 0x4030 0 0 4294967295 mmDCP2_PRESCALE_VALUES_GRPH_G 0 0x402f 0 0 4294967295 mmDCP2_PRESCALE_VALUES_GRPH_R 0 0x402e 0 0 4294967295 mmDCP2_PRESCALE_VALUES_OVL_CB 0 0x4032 0 0 4294967295 mmDCP2_PRESCALE_VALUES_OVL_CR 0 0x4034 0 0 4294967295 mmDCP2_PRESCALE_VALUES_OVL_Y 0 0x4033 0 0 4294967295 mmDCP2_REGAMMA_CNTLA_END_CNTL1 0 0x40a6 0 0 4294967295 mmDCP2_REGAMMA_CNTLA_END_CNTL2 0 0x40a7 0 0 4294967295 mmDCP2_REGAMMA_CNTLA_REGION_0_1 0 0x40a8 0 0 4294967295 mmDCP2_REGAMMA_CNTLA_REGION_10_11 0 0x40ad 0 0 4294967295 mmDCP2_REGAMMA_CNTLA_REGION_12_13 0 0x40ae 0 0 4294967295 mmDCP2_REGAMMA_CNTLA_REGION_14_15 0 0x40af 0 0 4294967295 mmDCP2_REGAMMA_CNTLA_REGION_2_3 0 0x40a9 0 0 4294967295 mmDCP2_REGAMMA_CNTLA_REGION_4_5 0 0x40aa 0 0 4294967295 mmDCP2_REGAMMA_CNTLA_REGION_6_7 0 0x40ab 0 0 4294967295 mmDCP2_REGAMMA_CNTLA_REGION_8_9 0 0x40ac 0 0 4294967295 mmDCP2_REGAMMA_CNTLA_SLOPE_CNTL 0 0x40a5 0 0 4294967295 mmDCP2_REGAMMA_CNTLA_START_CNTL 0 0x40a4 0 0 4294967295 mmDCP2_REGAMMA_CNTLB_END_CNTL1 0 0x40b2 0 0 4294967295 mmDCP2_REGAMMA_CNTLB_END_CNTL2 0 0x40b3 0 0 4294967295 mmDCP2_REGAMMA_CNTLB_REGION_0_1 0 0x40b4 0 0 4294967295 mmDCP2_REGAMMA_CNTLB_REGION_10_11 0 0x40b9 0 0 4294967295 mmDCP2_REGAMMA_CNTLB_REGION_12_13 0 0x40ba 0 0 4294967295 mmDCP2_REGAMMA_CNTLB_REGION_14_15 0 0x40bb 0 0 4294967295 mmDCP2_REGAMMA_CNTLB_REGION_2_3 0 0x40b5 0 0 4294967295 mmDCP2_REGAMMA_CNTLB_REGION_4_5 0 0x40b6 0 0 4294967295 mmDCP2_REGAMMA_CNTLB_REGION_6_7 0 0x40b7 0 0 4294967295 mmDCP2_REGAMMA_CNTLB_REGION_8_9 0 0x40b8 0 0 4294967295 mmDCP2_REGAMMA_CNTLB_SLOPE_CNTL 0 0x40b1 0 0 4294967295 mmDCP2_REGAMMA_CNTLB_START_CNTL 0 0x40b0 0 0 4294967295 mmDCP2_REGAMMA_CONTROL 0 0x40a0 0 0 4294967295 mmDCP2_REGAMMA_LUT_DATA 0 0x40a2 0 0 4294967295 mmDCP2_REGAMMA_LUT_INDEX 0 0x40a1 0 0 4294967295 mmDCP2_REGAMMA_LUT_WRITE_EN_MASK 0 0x40a3 0 0 4294967295 mmDCP3_COMM_MATRIXA_TRANS_C11_C12 0 0x4343 0 0 4294967295 mmDCP3_COMM_MATRIXA_TRANS_C13_C14 0 0x4344 0 0 4294967295 mmDCP3_COMM_MATRIXA_TRANS_C21_C22 0 0x4345 0 0 4294967295 mmDCP3_COMM_MATRIXA_TRANS_C23_C24 0 0x4346 0 0 4294967295 mmDCP3_COMM_MATRIXA_TRANS_C31_C32 0 0x4347 0 0 4294967295 mmDCP3_COMM_MATRIXA_TRANS_C33_C34 0 0x4348 0 0 4294967295 mmDCP3_COMM_MATRIXB_TRANS_C11_C12 0 0x4349 0 0 4294967295 mmDCP3_COMM_MATRIXB_TRANS_C13_C14 0 0x434a 0 0 4294967295 mmDCP3_COMM_MATRIXB_TRANS_C21_C22 0 0x434b 0 0 4294967295 mmDCP3_COMM_MATRIXB_TRANS_C23_C24 0 0x434c 0 0 4294967295 mmDCP3_COMM_MATRIXB_TRANS_C31_C32 0 0x434d 0 0 4294967295 mmDCP3_COMM_MATRIXB_TRANS_C33_C34 0 0x434e 0 0 4294967295 mmDCP3_CUR_COLOR1 0 0x436c 0 0 4294967295 mmDCP3_CUR_COLOR2 0 0x436d 0 0 4294967295 mmDCP3_CUR_CONTROL 0 0x4366 0 0 4294967295 mmDCP3_CUR_HOT_SPOT 0 0x436b 0 0 4294967295 mmDCP3_CUR_POSITION 0 0x436a 0 0 4294967295 mmDCP3_CUR_REQUEST_FILTER_CNTL 0 0x4399 0 0 4294967295 mmDCP3_CUR_SIZE 0 0x4368 0 0 4294967295 mmDCP3_CUR_SURFACE_ADDRESS 0 0x4367 0 0 4294967295 mmDCP3_CUR_SURFACE_ADDRESS_HIGH 0 0x4369 0 0 4294967295 mmDCP3_CUR_UPDATE 0 0x436e 0 0 4294967295 mmDCP3_DC_LUT_30_COLOR 0 0x437c 0 0 4294967295 mmDCP3_DC_LUT_AUTOFILL 0 0x437f 0 0 4294967295 mmDCP3_DC_LUT_BLACK_OFFSET_BLUE 0 0x4381 0 0 4294967295 mmDCP3_DC_LUT_BLACK_OFFSET_GREEN 0 0x4382 0 0 4294967295 mmDCP3_DC_LUT_BLACK_OFFSET_RED 0 0x4383 0 0 4294967295 mmDCP3_DC_LUT_CONTROL 0 0x4380 0 0 4294967295 mmDCP3_DC_LUT_PWL_DATA 0 0x437b 0 0 4294967295 mmDCP3_DC_LUT_RW_INDEX 0 0x4379 0 0 4294967295 mmDCP3_DC_LUT_RW_MODE 0 0x4378 0 0 4294967295 mmDCP3_DC_LUT_SEQ_COLOR 0 0x437a 0 0 4294967295 mmDCP3_DC_LUT_VGA_ACCESS_ENABLE 0 0x437d 0 0 4294967295 mmDCP3_DC_LUT_WHITE_OFFSET_BLUE 0 0x4384 0 0 4294967295 mmDCP3_DC_LUT_WHITE_OFFSET_GREEN 0 0x4385 0 0 4294967295 mmDCP3_DC_LUT_WHITE_OFFSET_RED 0 0x4386 0 0 4294967295 mmDCP3_DC_LUT_WRITE_EN_MASK 0 0x437e 0 0 4294967295 mmDCP3_DCP_CRC_CONTROL 0 0x4387 0 0 4294967295 mmDCP3_DCP_CRC_CURRENT 0 0x4389 0 0 4294967295 mmDCP3_DCP_CRC_LAST 0 0x438b 0 0 4294967295 mmDCP3_DCP_CRC_MASK 0 0x4388 0 0 4294967295 mmDCP3_DCP_DEBUG 0 0x438d 0 0 4294967295 mmDCP3_DCP_DEBUG2 0 0x4398 0 0 4294967295 mmDCP3_DCP_FP_CONVERTED_FIELD 0 0x4365 0 0 4294967295 mmDCP3_DCP_GSL_CONTROL 0 0x4390 0 0 4294967295 mmDCP3_DCP_LB_DATA_GAP_BETWEEN_CHUNK 0 0x4391 0 0 4294967295 mmDCP3_DCP_RANDOM_SEEDS 0 0x4361 0 0 4294967295 mmDCP3_DCP_SPATIAL_DITHER_CNTL 0 0x4360 0 0 4294967295 mmDCP3_DCP_TEST_DEBUG_DATA 0 0x4396 0 0 4294967295 mmDCP3_DCP_TEST_DEBUG_INDEX 0 0x4395 0 0 4294967295 mmDCP3_DEGAMMA_CONTROL 0 0x4358 0 0 4294967295 mmDCP3_DENORM_CONTROL 0 0x4350 0 0 4294967295 mmDCP3_GAMUT_REMAP_C11_C12 0 0x435a 0 0 4294967295 mmDCP3_GAMUT_REMAP_C13_C14 0 0x435b 0 0 4294967295 mmDCP3_GAMUT_REMAP_C21_C22 0 0x435c 0 0 4294967295 mmDCP3_GAMUT_REMAP_C23_C24 0 0x435d 0 0 4294967295 mmDCP3_GAMUT_REMAP_C31_C32 0 0x435e 0 0 4294967295 mmDCP3_GAMUT_REMAP_C33_C34 0 0x435f 0 0 4294967295 mmDCP3_GAMUT_REMAP_CONTROL 0 0x4359 0 0 4294967295 mmDCP3_GRPH_COMPRESS_PITCH 0 0x431a 0 0 4294967295 mmDCP3_GRPH_COMPRESS_SURFACE_ADDRESS 0 0x4319 0 0 4294967295 mmDCP3_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH 0 0x431b 0 0 4294967295 mmDCP3_GRPH_CONTROL 0 0x4301 0 0 4294967295 mmDCP3_GRPH_DFQ_CONTROL 0 0x4314 0 0 4294967295 mmDCP3_GRPH_DFQ_STATUS 0 0x4315 0 0 4294967295 mmDCP3_GRPH_ENABLE 0 0x4300 0 0 4294967295 mmDCP3_GRPH_FLIP_CONTROL 0 0x4312 0 0 4294967295 mmDCP3_GRPH_INTERRUPT_CONTROL 0 0x4317 0 0 4294967295 mmDCP3_GRPH_INTERRUPT_STATUS 0 0x4316 0 0 4294967295 mmDCP3_GRPH_LUT_10BIT_BYPASS 0 0x4302 0 0 4294967295 mmDCP3_GRPH_PITCH 0 0x4306 0 0 4294967295 mmDCP3_GRPH_PRIMARY_SURFACE_ADDRESS 0 0x4304 0 0 4294967295 mmDCP3_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH 0 0x4307 0 0 4294967295 mmDCP3_GRPH_SECONDARY_SURFACE_ADDRESS 0 0x4305 0 0 4294967295 mmDCP3_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH 0 0x4308 0 0 4294967295 mmDCP3_GRPH_STEREOSYNC_FLIP 0 0x4397 0 0 4294967295 mmDCP3_GRPH_SURFACE_ADDRESS_HIGH_INUSE 0 0x4318 0 0 4294967295 mmDCP3_GRPH_SURFACE_ADDRESS_INUSE 0 0x4313 0 0 4294967295 mmDCP3_GRPH_SURFACE_OFFSET_X 0 0x4309 0 0 4294967295 mmDCP3_GRPH_SURFACE_OFFSET_Y 0 0x430a 0 0 4294967295 mmDCP3_GRPH_SWAP_CNTL 0 0x4303 0 0 4294967295 mmDCP3_GRPH_UPDATE 0 0x4311 0 0 4294967295 mmDCP3_GRPH_X_END 0 0x430d 0 0 4294967295 mmDCP3_GRPH_X_START 0 0x430b 0 0 4294967295 mmDCP3_GRPH_Y_END 0 0x430e 0 0 4294967295 mmDCP3_GRPH_Y_START 0 0x430c 0 0 4294967295 mmDCP3_INPUT_CSC_C11_C12 0 0x4336 0 0 4294967295 mmDCP3_INPUT_CSC_C13_C14 0 0x4337 0 0 4294967295 mmDCP3_INPUT_CSC_C21_C22 0 0x4338 0 0 4294967295 mmDCP3_INPUT_CSC_C23_C24 0 0x4339 0 0 4294967295 mmDCP3_INPUT_CSC_C31_C32 0 0x433a 0 0 4294967295 mmDCP3_INPUT_CSC_C33_C34 0 0x433b 0 0 4294967295 mmDCP3_INPUT_CSC_CONTROL 0 0x4335 0 0 4294967295 mmDCP3_INPUT_GAMMA_CONTROL 0 0x4310 0 0 4294967295 mmDCP3_KEY_CONTROL 0 0x4353 0 0 4294967295 mmDCP3_KEY_RANGE_ALPHA 0 0x4354 0 0 4294967295 mmDCP3_KEY_RANGE_BLUE 0 0x4357 0 0 4294967295 mmDCP3_KEY_RANGE_GREEN 0 0x4356 0 0 4294967295 mmDCP3_KEY_RANGE_RED 0 0x4355 0 0 4294967295 mmDCP3_OUTPUT_CSC_C11_C12 0 0x433d 0 0 4294967295 mmDCP3_OUTPUT_CSC_C13_C14 0 0x433e 0 0 4294967295 mmDCP3_OUTPUT_CSC_C21_C22 0 0x433f 0 0 4294967295 mmDCP3_OUTPUT_CSC_C23_C24 0 0x4340 0 0 4294967295 mmDCP3_OUTPUT_CSC_C31_C32 0 0x4341 0 0 4294967295 mmDCP3_OUTPUT_CSC_C33_C34 0 0x4342 0 0 4294967295 mmDCP3_OUTPUT_CSC_CONTROL 0 0x433c 0 0 4294967295 mmDCP3_OUT_ROUND_CONTROL 0 0x4351 0 0 4294967295 mmDCP3_OVL_CONTROL1 0 0x431d 0 0 4294967295 mmDCP3_OVL_CONTROL2 0 0x431e 0 0 4294967295 mmDCP3_OVL_DFQ_CONTROL 0 0x4329 0 0 4294967295 mmDCP3_OVL_DFQ_STATUS 0 0x432a 0 0 4294967295 mmDCP3_OVL_ENABLE 0 0x431c 0 0 4294967295 mmDCP3_OVL_END 0 0x4326 0 0 4294967295 mmDCP3_OVL_PITCH 0 0x4321 0 0 4294967295 mmDCP3_OVLSCL_EDGE_PIXEL_CNTL 0 0x432c 0 0 4294967295 mmDCP3_OVL_SECONDARY_SURFACE_ADDRESS 0 0x4392 0 0 4294967295 mmDCP3_OVL_SECONDARY_SURFACE_ADDRESS_HIGH 0 0x4394 0 0 4294967295 mmDCP3_OVL_START 0 0x4325 0 0 4294967295 mmDCP3_OVL_STEREOSYNC_FLIP 0 0x4393 0 0 4294967295 mmDCP3_OVL_SURFACE_ADDRESS 0 0x4320 0 0 4294967295 mmDCP3_OVL_SURFACE_ADDRESS_HIGH 0 0x4322 0 0 4294967295 mmDCP3_OVL_SURFACE_ADDRESS_HIGH_INUSE 0 0x432b 0 0 4294967295 mmDCP3_OVL_SURFACE_ADDRESS_INUSE 0 0x4328 0 0 4294967295 mmDCP3_OVL_SURFACE_OFFSET_X 0 0x4323 0 0 4294967295 mmDCP3_OVL_SURFACE_OFFSET_Y 0 0x4324 0 0 4294967295 mmDCP3_OVL_SWAP_CNTL 0 0x431f 0 0 4294967295 mmDCP3_OVL_UPDATE 0 0x4327 0 0 4294967295 mmDCP3_PRESCALE_GRPH_CONTROL 0 0x432d 0 0 4294967295 mmDCP3_PRESCALE_OVL_CONTROL 0 0x4331 0 0 4294967295 mmDCP3_PRESCALE_VALUES_GRPH_B 0 0x4330 0 0 4294967295 mmDCP3_PRESCALE_VALUES_GRPH_G 0 0x432f 0 0 4294967295 mmDCP3_PRESCALE_VALUES_GRPH_R 0 0x432e 0 0 4294967295 mmDCP3_PRESCALE_VALUES_OVL_CB 0 0x4332 0 0 4294967295 mmDCP3_PRESCALE_VALUES_OVL_CR 0 0x4334 0 0 4294967295 mmDCP3_PRESCALE_VALUES_OVL_Y 0 0x4333 0 0 4294967295 mmDCP3_REGAMMA_CNTLA_END_CNTL1 0 0x43a6 0 0 4294967295 mmDCP3_REGAMMA_CNTLA_END_CNTL2 0 0x43a7 0 0 4294967295 mmDCP3_REGAMMA_CNTLA_REGION_0_1 0 0x43a8 0 0 4294967295 mmDCP3_REGAMMA_CNTLA_REGION_10_11 0 0x43ad 0 0 4294967295 mmDCP3_REGAMMA_CNTLA_REGION_12_13 0 0x43ae 0 0 4294967295 mmDCP3_REGAMMA_CNTLA_REGION_14_15 0 0x43af 0 0 4294967295 mmDCP3_REGAMMA_CNTLA_REGION_2_3 0 0x43a9 0 0 4294967295 mmDCP3_REGAMMA_CNTLA_REGION_4_5 0 0x43aa 0 0 4294967295 mmDCP3_REGAMMA_CNTLA_REGION_6_7 0 0x43ab 0 0 4294967295 mmDCP3_REGAMMA_CNTLA_REGION_8_9 0 0x43ac 0 0 4294967295 mmDCP3_REGAMMA_CNTLA_SLOPE_CNTL 0 0x43a5 0 0 4294967295 mmDCP3_REGAMMA_CNTLA_START_CNTL 0 0x43a4 0 0 4294967295 mmDCP3_REGAMMA_CNTLB_END_CNTL1 0 0x43b2 0 0 4294967295 mmDCP3_REGAMMA_CNTLB_END_CNTL2 0 0x43b3 0 0 4294967295 mmDCP3_REGAMMA_CNTLB_REGION_0_1 0 0x43b4 0 0 4294967295 mmDCP3_REGAMMA_CNTLB_REGION_10_11 0 0x43b9 0 0 4294967295 mmDCP3_REGAMMA_CNTLB_REGION_12_13 0 0x43ba 0 0 4294967295 mmDCP3_REGAMMA_CNTLB_REGION_14_15 0 0x43bb 0 0 4294967295 mmDCP3_REGAMMA_CNTLB_REGION_2_3 0 0x43b5 0 0 4294967295 mmDCP3_REGAMMA_CNTLB_REGION_4_5 0 0x43b6 0 0 4294967295 mmDCP3_REGAMMA_CNTLB_REGION_6_7 0 0x43b7 0 0 4294967295 mmDCP3_REGAMMA_CNTLB_REGION_8_9 0 0x43b8 0 0 4294967295 mmDCP3_REGAMMA_CNTLB_SLOPE_CNTL 0 0x43b1 0 0 4294967295 mmDCP3_REGAMMA_CNTLB_START_CNTL 0 0x43b0 0 0 4294967295 mmDCP3_REGAMMA_CONTROL 0 0x43a0 0 0 4294967295 mmDCP3_REGAMMA_LUT_DATA 0 0x43a2 0 0 4294967295 mmDCP3_REGAMMA_LUT_INDEX 0 0x43a1 0 0 4294967295 mmDCP3_REGAMMA_LUT_WRITE_EN_MASK 0 0x43a3 0 0 4294967295 mmDCP4_COMM_MATRIXA_TRANS_C11_C12 0 0x4643 0 0 4294967295 mmDCP4_COMM_MATRIXA_TRANS_C13_C14 0 0x4644 0 0 4294967295 mmDCP4_COMM_MATRIXA_TRANS_C21_C22 0 0x4645 0 0 4294967295 mmDCP4_COMM_MATRIXA_TRANS_C23_C24 0 0x4646 0 0 4294967295 mmDCP4_COMM_MATRIXA_TRANS_C31_C32 0 0x4647 0 0 4294967295 mmDCP4_COMM_MATRIXA_TRANS_C33_C34 0 0x4648 0 0 4294967295 mmDCP4_COMM_MATRIXB_TRANS_C11_C12 0 0x4649 0 0 4294967295 mmDCP4_COMM_MATRIXB_TRANS_C13_C14 0 0x464a 0 0 4294967295 mmDCP4_COMM_MATRIXB_TRANS_C21_C22 0 0x464b 0 0 4294967295 mmDCP4_COMM_MATRIXB_TRANS_C23_C24 0 0x464c 0 0 4294967295 mmDCP4_COMM_MATRIXB_TRANS_C31_C32 0 0x464d 0 0 4294967295 mmDCP4_COMM_MATRIXB_TRANS_C33_C34 0 0x464e 0 0 4294967295 mmDCP4_CUR_COLOR1 0 0x466c 0 0 4294967295 mmDCP4_CUR_COLOR2 0 0x466d 0 0 4294967295 mmDCP4_CUR_CONTROL 0 0x4666 0 0 4294967295 mmDCP4_CUR_HOT_SPOT 0 0x466b 0 0 4294967295 mmDCP4_CUR_POSITION 0 0x466a 0 0 4294967295 mmDCP4_CUR_REQUEST_FILTER_CNTL 0 0x4699 0 0 4294967295 mmDCP4_CUR_SIZE 0 0x4668 0 0 4294967295 mmDCP4_CUR_SURFACE_ADDRESS 0 0x4667 0 0 4294967295 mmDCP4_CUR_SURFACE_ADDRESS_HIGH 0 0x4669 0 0 4294967295 mmDCP4_CUR_UPDATE 0 0x466e 0 0 4294967295 mmDCP4_DC_LUT_30_COLOR 0 0x467c 0 0 4294967295 mmDCP4_DC_LUT_AUTOFILL 0 0x467f 0 0 4294967295 mmDCP4_DC_LUT_BLACK_OFFSET_BLUE 0 0x4681 0 0 4294967295 mmDCP4_DC_LUT_BLACK_OFFSET_GREEN 0 0x4682 0 0 4294967295 mmDCP4_DC_LUT_BLACK_OFFSET_RED 0 0x4683 0 0 4294967295 mmDCP4_DC_LUT_CONTROL 0 0x4680 0 0 4294967295 mmDCP4_DC_LUT_PWL_DATA 0 0x467b 0 0 4294967295 mmDCP4_DC_LUT_RW_INDEX 0 0x4679 0 0 4294967295 mmDCP4_DC_LUT_RW_MODE 0 0x4678 0 0 4294967295 mmDCP4_DC_LUT_SEQ_COLOR 0 0x467a 0 0 4294967295 mmDCP4_DC_LUT_VGA_ACCESS_ENABLE 0 0x467d 0 0 4294967295 mmDCP4_DC_LUT_WHITE_OFFSET_BLUE 0 0x4684 0 0 4294967295 mmDCP4_DC_LUT_WHITE_OFFSET_GREEN 0 0x4685 0 0 4294967295 mmDCP4_DC_LUT_WHITE_OFFSET_RED 0 0x4686 0 0 4294967295 mmDCP4_DC_LUT_WRITE_EN_MASK 0 0x467e 0 0 4294967295 mmDCP4_DCP_CRC_CONTROL 0 0x4687 0 0 4294967295 mmDCP4_DCP_CRC_CURRENT 0 0x4689 0 0 4294967295 mmDCP4_DCP_CRC_LAST 0 0x468b 0 0 4294967295 mmDCP4_DCP_CRC_MASK 0 0x4688 0 0 4294967295 mmDCP4_DCP_DEBUG 0 0x468d 0 0 4294967295 mmDCP4_DCP_DEBUG2 0 0x4698 0 0 4294967295 mmDCP4_DCP_FP_CONVERTED_FIELD 0 0x4665 0 0 4294967295 mmDCP4_DCP_GSL_CONTROL 0 0x4690 0 0 4294967295 mmDCP4_DCP_LB_DATA_GAP_BETWEEN_CHUNK 0 0x4691 0 0 4294967295 mmDCP4_DCP_RANDOM_SEEDS 0 0x4661 0 0 4294967295 mmDCP4_DCP_SPATIAL_DITHER_CNTL 0 0x4660 0 0 4294967295 mmDCP4_DCP_TEST_DEBUG_DATA 0 0x4696 0 0 4294967295 mmDCP4_DCP_TEST_DEBUG_INDEX 0 0x4695 0 0 4294967295 mmDCP4_DEGAMMA_CONTROL 0 0x4658 0 0 4294967295 mmDCP4_DENORM_CONTROL 0 0x4650 0 0 4294967295 mmDCP4_GAMUT_REMAP_C11_C12 0 0x465a 0 0 4294967295 mmDCP4_GAMUT_REMAP_C13_C14 0 0x465b 0 0 4294967295 mmDCP4_GAMUT_REMAP_C21_C22 0 0x465c 0 0 4294967295 mmDCP4_GAMUT_REMAP_C23_C24 0 0x465d 0 0 4294967295 mmDCP4_GAMUT_REMAP_C31_C32 0 0x465e 0 0 4294967295 mmDCP4_GAMUT_REMAP_C33_C34 0 0x465f 0 0 4294967295 mmDCP4_GAMUT_REMAP_CONTROL 0 0x4659 0 0 4294967295 mmDCP4_GRPH_COMPRESS_PITCH 0 0x461a 0 0 4294967295 mmDCP4_GRPH_COMPRESS_SURFACE_ADDRESS 0 0x4619 0 0 4294967295 mmDCP4_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH 0 0x461b 0 0 4294967295 mmDCP4_GRPH_CONTROL 0 0x4601 0 0 4294967295 mmDCP4_GRPH_DFQ_CONTROL 0 0x4614 0 0 4294967295 mmDCP4_GRPH_DFQ_STATUS 0 0x4615 0 0 4294967295 mmDCP4_GRPH_ENABLE 0 0x4600 0 0 4294967295 mmDCP4_GRPH_FLIP_CONTROL 0 0x4612 0 0 4294967295 mmDCP4_GRPH_INTERRUPT_CONTROL 0 0x4617 0 0 4294967295 mmDCP4_GRPH_INTERRUPT_STATUS 0 0x4616 0 0 4294967295 mmDCP4_GRPH_LUT_10BIT_BYPASS 0 0x4602 0 0 4294967295 mmDCP4_GRPH_PITCH 0 0x4606 0 0 4294967295 mmDCP4_GRPH_PRIMARY_SURFACE_ADDRESS 0 0x4604 0 0 4294967295 mmDCP4_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH 0 0x4607 0 0 4294967295 mmDCP4_GRPH_SECONDARY_SURFACE_ADDRESS 0 0x4605 0 0 4294967295 mmDCP4_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH 0 0x4608 0 0 4294967295 mmDCP4_GRPH_STEREOSYNC_FLIP 0 0x4697 0 0 4294967295 mmDCP4_GRPH_SURFACE_ADDRESS_HIGH_INUSE 0 0x4618 0 0 4294967295 mmDCP4_GRPH_SURFACE_ADDRESS_INUSE 0 0x4613 0 0 4294967295 mmDCP4_GRPH_SURFACE_OFFSET_X 0 0x4609 0 0 4294967295 mmDCP4_GRPH_SURFACE_OFFSET_Y 0 0x460a 0 0 4294967295 mmDCP4_GRPH_SWAP_CNTL 0 0x4603 0 0 4294967295 mmDCP4_GRPH_UPDATE 0 0x4611 0 0 4294967295 mmDCP4_GRPH_X_END 0 0x460d 0 0 4294967295 mmDCP4_GRPH_X_START 0 0x460b 0 0 4294967295 mmDCP4_GRPH_Y_END 0 0x460e 0 0 4294967295 mmDCP4_GRPH_Y_START 0 0x460c 0 0 4294967295 mmDCP4_INPUT_CSC_C11_C12 0 0x4636 0 0 4294967295 mmDCP4_INPUT_CSC_C13_C14 0 0x4637 0 0 4294967295 mmDCP4_INPUT_CSC_C21_C22 0 0x4638 0 0 4294967295 mmDCP4_INPUT_CSC_C23_C24 0 0x4639 0 0 4294967295 mmDCP4_INPUT_CSC_C31_C32 0 0x463a 0 0 4294967295 mmDCP4_INPUT_CSC_C33_C34 0 0x463b 0 0 4294967295 mmDCP4_INPUT_CSC_CONTROL 0 0x4635 0 0 4294967295 mmDCP4_INPUT_GAMMA_CONTROL 0 0x4610 0 0 4294967295 mmDCP4_KEY_CONTROL 0 0x4653 0 0 4294967295 mmDCP4_KEY_RANGE_ALPHA 0 0x4654 0 0 4294967295 mmDCP4_KEY_RANGE_BLUE 0 0x4657 0 0 4294967295 mmDCP4_KEY_RANGE_GREEN 0 0x4656 0 0 4294967295 mmDCP4_KEY_RANGE_RED 0 0x4655 0 0 4294967295 mmDCP4_OUTPUT_CSC_C11_C12 0 0x463d 0 0 4294967295 mmDCP4_OUTPUT_CSC_C13_C14 0 0x463e 0 0 4294967295 mmDCP4_OUTPUT_CSC_C21_C22 0 0x463f 0 0 4294967295 mmDCP4_OUTPUT_CSC_C23_C24 0 0x4640 0 0 4294967295 mmDCP4_OUTPUT_CSC_C31_C32 0 0x4641 0 0 4294967295 mmDCP4_OUTPUT_CSC_C33_C34 0 0x4642 0 0 4294967295 mmDCP4_OUTPUT_CSC_CONTROL 0 0x463c 0 0 4294967295 mmDCP4_OUT_ROUND_CONTROL 0 0x4651 0 0 4294967295 mmDCP4_OVL_CONTROL1 0 0x461d 0 0 4294967295 mmDCP4_OVL_CONTROL2 0 0x461e 0 0 4294967295 mmDCP4_OVL_DFQ_CONTROL 0 0x4629 0 0 4294967295 mmDCP4_OVL_DFQ_STATUS 0 0x462a 0 0 4294967295 mmDCP4_OVL_ENABLE 0 0x461c 0 0 4294967295 mmDCP4_OVL_END 0 0x4626 0 0 4294967295 mmDCP4_OVL_PITCH 0 0x4621 0 0 4294967295 mmDCP4_OVLSCL_EDGE_PIXEL_CNTL 0 0x462c 0 0 4294967295 mmDCP4_OVL_SECONDARY_SURFACE_ADDRESS 0 0x4692 0 0 4294967295 mmDCP4_OVL_SECONDARY_SURFACE_ADDRESS_HIGH 0 0x4694 0 0 4294967295 mmDCP4_OVL_START 0 0x4625 0 0 4294967295 mmDCP4_OVL_STEREOSYNC_FLIP 0 0x4693 0 0 4294967295 mmDCP4_OVL_SURFACE_ADDRESS 0 0x4620 0 0 4294967295 mmDCP4_OVL_SURFACE_ADDRESS_HIGH 0 0x4622 0 0 4294967295 mmDCP4_OVL_SURFACE_ADDRESS_HIGH_INUSE 0 0x462b 0 0 4294967295 mmDCP4_OVL_SURFACE_ADDRESS_INUSE 0 0x4628 0 0 4294967295 mmDCP4_OVL_SURFACE_OFFSET_X 0 0x4623 0 0 4294967295 mmDCP4_OVL_SURFACE_OFFSET_Y 0 0x4624 0 0 4294967295 mmDCP4_OVL_SWAP_CNTL 0 0x461f 0 0 4294967295 mmDCP4_OVL_UPDATE 0 0x4627 0 0 4294967295 mmDCP4_PRESCALE_GRPH_CONTROL 0 0x462d 0 0 4294967295 mmDCP4_PRESCALE_OVL_CONTROL 0 0x4631 0 0 4294967295 mmDCP4_PRESCALE_VALUES_GRPH_B 0 0x4630 0 0 4294967295 mmDCP4_PRESCALE_VALUES_GRPH_G 0 0x462f 0 0 4294967295 mmDCP4_PRESCALE_VALUES_GRPH_R 0 0x462e 0 0 4294967295 mmDCP4_PRESCALE_VALUES_OVL_CB 0 0x4632 0 0 4294967295 mmDCP4_PRESCALE_VALUES_OVL_CR 0 0x4634 0 0 4294967295 mmDCP4_PRESCALE_VALUES_OVL_Y 0 0x4633 0 0 4294967295 mmDCP4_REGAMMA_CNTLA_END_CNTL1 0 0x46a6 0 0 4294967295 mmDCP4_REGAMMA_CNTLA_END_CNTL2 0 0x46a7 0 0 4294967295 mmDCP4_REGAMMA_CNTLA_REGION_0_1 0 0x46a8 0 0 4294967295 mmDCP4_REGAMMA_CNTLA_REGION_10_11 0 0x46ad 0 0 4294967295 mmDCP4_REGAMMA_CNTLA_REGION_12_13 0 0x46ae 0 0 4294967295 mmDCP4_REGAMMA_CNTLA_REGION_14_15 0 0x46af 0 0 4294967295 mmDCP4_REGAMMA_CNTLA_REGION_2_3 0 0x46a9 0 0 4294967295 mmDCP4_REGAMMA_CNTLA_REGION_4_5 0 0x46aa 0 0 4294967295 mmDCP4_REGAMMA_CNTLA_REGION_6_7 0 0x46ab 0 0 4294967295 mmDCP4_REGAMMA_CNTLA_REGION_8_9 0 0x46ac 0 0 4294967295 mmDCP4_REGAMMA_CNTLA_SLOPE_CNTL 0 0x46a5 0 0 4294967295 mmDCP4_REGAMMA_CNTLA_START_CNTL 0 0x46a4 0 0 4294967295 mmDCP4_REGAMMA_CNTLB_END_CNTL1 0 0x46b2 0 0 4294967295 mmDCP4_REGAMMA_CNTLB_END_CNTL2 0 0x46b3 0 0 4294967295 mmDCP4_REGAMMA_CNTLB_REGION_0_1 0 0x46b4 0 0 4294967295 mmDCP4_REGAMMA_CNTLB_REGION_10_11 0 0x46b9 0 0 4294967295 mmDCP4_REGAMMA_CNTLB_REGION_12_13 0 0x46ba 0 0 4294967295 mmDCP4_REGAMMA_CNTLB_REGION_14_15 0 0x46bb 0 0 4294967295 mmDCP4_REGAMMA_CNTLB_REGION_2_3 0 0x46b5 0 0 4294967295 mmDCP4_REGAMMA_CNTLB_REGION_4_5 0 0x46b6 0 0 4294967295 mmDCP4_REGAMMA_CNTLB_REGION_6_7 0 0x46b7 0 0 4294967295 mmDCP4_REGAMMA_CNTLB_REGION_8_9 0 0x46b8 0 0 4294967295 mmDCP4_REGAMMA_CNTLB_SLOPE_CNTL 0 0x46b1 0 0 4294967295 mmDCP4_REGAMMA_CNTLB_START_CNTL 0 0x46b0 0 0 4294967295 mmDCP4_REGAMMA_CONTROL 0 0x46a0 0 0 4294967295 mmDCP4_REGAMMA_LUT_DATA 0 0x46a2 0 0 4294967295 mmDCP4_REGAMMA_LUT_INDEX 0 0x46a1 0 0 4294967295 mmDCP4_REGAMMA_LUT_WRITE_EN_MASK 0 0x46a3 0 0 4294967295 mmDCP5_COMM_MATRIXA_TRANS_C11_C12 0 0x4943 0 0 4294967295 mmDCP5_COMM_MATRIXA_TRANS_C13_C14 0 0x4944 0 0 4294967295 mmDCP5_COMM_MATRIXA_TRANS_C21_C22 0 0x4945 0 0 4294967295 mmDCP5_COMM_MATRIXA_TRANS_C23_C24 0 0x4946 0 0 4294967295 mmDCP5_COMM_MATRIXA_TRANS_C31_C32 0 0x4947 0 0 4294967295 mmDCP5_COMM_MATRIXA_TRANS_C33_C34 0 0x4948 0 0 4294967295 mmDCP5_COMM_MATRIXB_TRANS_C11_C12 0 0x4949 0 0 4294967295 mmDCP5_COMM_MATRIXB_TRANS_C13_C14 0 0x494a 0 0 4294967295 mmDCP5_COMM_MATRIXB_TRANS_C21_C22 0 0x494b 0 0 4294967295 mmDCP5_COMM_MATRIXB_TRANS_C23_C24 0 0x494c 0 0 4294967295 mmDCP5_COMM_MATRIXB_TRANS_C31_C32 0 0x494d 0 0 4294967295 mmDCP5_COMM_MATRIXB_TRANS_C33_C34 0 0x494e 0 0 4294967295 mmDCP5_CUR_COLOR1 0 0x496c 0 0 4294967295 mmDCP5_CUR_COLOR2 0 0x496d 0 0 4294967295 mmDCP5_CUR_CONTROL 0 0x4966 0 0 4294967295 mmDCP5_CUR_HOT_SPOT 0 0x496b 0 0 4294967295 mmDCP5_CUR_POSITION 0 0x496a 0 0 4294967295 mmDCP5_CUR_REQUEST_FILTER_CNTL 0 0x4999 0 0 4294967295 mmDCP5_CUR_SIZE 0 0x4968 0 0 4294967295 mmDCP5_CUR_SURFACE_ADDRESS 0 0x4967 0 0 4294967295 mmDCP5_CUR_SURFACE_ADDRESS_HIGH 0 0x4969 0 0 4294967295 mmDCP5_CUR_UPDATE 0 0x496e 0 0 4294967295 mmDCP5_DC_LUT_30_COLOR 0 0x497c 0 0 4294967295 mmDCP5_DC_LUT_AUTOFILL 0 0x497f 0 0 4294967295 mmDCP5_DC_LUT_BLACK_OFFSET_BLUE 0 0x4981 0 0 4294967295 mmDCP5_DC_LUT_BLACK_OFFSET_GREEN 0 0x4982 0 0 4294967295 mmDCP5_DC_LUT_BLACK_OFFSET_RED 0 0x4983 0 0 4294967295 mmDCP5_DC_LUT_CONTROL 0 0x4980 0 0 4294967295 mmDCP5_DC_LUT_PWL_DATA 0 0x497b 0 0 4294967295 mmDCP5_DC_LUT_RW_INDEX 0 0x4979 0 0 4294967295 mmDCP5_DC_LUT_RW_MODE 0 0x4978 0 0 4294967295 mmDCP5_DC_LUT_SEQ_COLOR 0 0x497a 0 0 4294967295 mmDCP5_DC_LUT_VGA_ACCESS_ENABLE 0 0x497d 0 0 4294967295 mmDCP5_DC_LUT_WHITE_OFFSET_BLUE 0 0x4984 0 0 4294967295 mmDCP5_DC_LUT_WHITE_OFFSET_GREEN 0 0x4985 0 0 4294967295 mmDCP5_DC_LUT_WHITE_OFFSET_RED 0 0x4986 0 0 4294967295 mmDCP5_DC_LUT_WRITE_EN_MASK 0 0x497e 0 0 4294967295 mmDCP5_DCP_CRC_CONTROL 0 0x4987 0 0 4294967295 mmDCP5_DCP_CRC_CURRENT 0 0x4989 0 0 4294967295 mmDCP5_DCP_CRC_LAST 0 0x498b 0 0 4294967295 mmDCP5_DCP_CRC_MASK 0 0x4988 0 0 4294967295 mmDCP5_DCP_DEBUG 0 0x498d 0 0 4294967295 mmDCP5_DCP_DEBUG2 0 0x4998 0 0 4294967295 mmDCP5_DCP_FP_CONVERTED_FIELD 0 0x4965 0 0 4294967295 mmDCP5_DCP_GSL_CONTROL 0 0x4990 0 0 4294967295 mmDCP5_DCP_LB_DATA_GAP_BETWEEN_CHUNK 0 0x4991 0 0 4294967295 mmDCP5_DCP_RANDOM_SEEDS 0 0x4961 0 0 4294967295 mmDCP5_DCP_SPATIAL_DITHER_CNTL 0 0x4960 0 0 4294967295 mmDCP5_DCP_TEST_DEBUG_DATA 0 0x4996 0 0 4294967295 mmDCP5_DCP_TEST_DEBUG_INDEX 0 0x4995 0 0 4294967295 mmDCP5_DEGAMMA_CONTROL 0 0x4958 0 0 4294967295 mmDCP5_DENORM_CONTROL 0 0x4950 0 0 4294967295 mmDCP5_GAMUT_REMAP_C11_C12 0 0x495a 0 0 4294967295 mmDCP5_GAMUT_REMAP_C13_C14 0 0x495b 0 0 4294967295 mmDCP5_GAMUT_REMAP_C21_C22 0 0x495c 0 0 4294967295 mmDCP5_GAMUT_REMAP_C23_C24 0 0x495d 0 0 4294967295 mmDCP5_GAMUT_REMAP_C31_C32 0 0x495e 0 0 4294967295 mmDCP5_GAMUT_REMAP_C33_C34 0 0x495f 0 0 4294967295 mmDCP5_GAMUT_REMAP_CONTROL 0 0x4959 0 0 4294967295 mmDCP5_GRPH_COMPRESS_PITCH 0 0x491a 0 0 4294967295 mmDCP5_GRPH_COMPRESS_SURFACE_ADDRESS 0 0x4919 0 0 4294967295 mmDCP5_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH 0 0x491b 0 0 4294967295 mmDCP5_GRPH_CONTROL 0 0x4901 0 0 4294967295 mmDCP5_GRPH_DFQ_CONTROL 0 0x4914 0 0 4294967295 mmDCP5_GRPH_DFQ_STATUS 0 0x4915 0 0 4294967295 mmDCP5_GRPH_ENABLE 0 0x4900 0 0 4294967295 mmDCP5_GRPH_FLIP_CONTROL 0 0x4912 0 0 4294967295 mmDCP5_GRPH_INTERRUPT_CONTROL 0 0x4917 0 0 4294967295 mmDCP5_GRPH_INTERRUPT_STATUS 0 0x4916 0 0 4294967295 mmDCP5_GRPH_LUT_10BIT_BYPASS 0 0x4902 0 0 4294967295 mmDCP5_GRPH_PITCH 0 0x4906 0 0 4294967295 mmDCP5_GRPH_PRIMARY_SURFACE_ADDRESS 0 0x4904 0 0 4294967295 mmDCP5_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH 0 0x4907 0 0 4294967295 mmDCP5_GRPH_SECONDARY_SURFACE_ADDRESS 0 0x4905 0 0 4294967295 mmDCP5_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH 0 0x4908 0 0 4294967295 mmDCP5_GRPH_STEREOSYNC_FLIP 0 0x4997 0 0 4294967295 mmDCP5_GRPH_SURFACE_ADDRESS_HIGH_INUSE 0 0x4918 0 0 4294967295 mmDCP5_GRPH_SURFACE_ADDRESS_INUSE 0 0x4913 0 0 4294967295 mmDCP5_GRPH_SURFACE_OFFSET_X 0 0x4909 0 0 4294967295 mmDCP5_GRPH_SURFACE_OFFSET_Y 0 0x490a 0 0 4294967295 mmDCP5_GRPH_SWAP_CNTL 0 0x4903 0 0 4294967295 mmDCP5_GRPH_UPDATE 0 0x4911 0 0 4294967295 mmDCP5_GRPH_X_END 0 0x490d 0 0 4294967295 mmDCP5_GRPH_X_START 0 0x490b 0 0 4294967295 mmDCP5_GRPH_Y_END 0 0x490e 0 0 4294967295 mmDCP5_GRPH_Y_START 0 0x490c 0 0 4294967295 mmDCP5_INPUT_CSC_C11_C12 0 0x4936 0 0 4294967295 mmDCP5_INPUT_CSC_C13_C14 0 0x4937 0 0 4294967295 mmDCP5_INPUT_CSC_C21_C22 0 0x4938 0 0 4294967295 mmDCP5_INPUT_CSC_C23_C24 0 0x4939 0 0 4294967295 mmDCP5_INPUT_CSC_C31_C32 0 0x493a 0 0 4294967295 mmDCP5_INPUT_CSC_C33_C34 0 0x493b 0 0 4294967295 mmDCP5_INPUT_CSC_CONTROL 0 0x4935 0 0 4294967295 mmDCP5_INPUT_GAMMA_CONTROL 0 0x4910 0 0 4294967295 mmDCP5_KEY_CONTROL 0 0x4953 0 0 4294967295 mmDCP5_KEY_RANGE_ALPHA 0 0x4954 0 0 4294967295 mmDCP5_KEY_RANGE_BLUE 0 0x4957 0 0 4294967295 mmDCP5_KEY_RANGE_GREEN 0 0x4956 0 0 4294967295 mmDCP5_KEY_RANGE_RED 0 0x4955 0 0 4294967295 mmDCP5_OUTPUT_CSC_C11_C12 0 0x493d 0 0 4294967295 mmDCP5_OUTPUT_CSC_C13_C14 0 0x493e 0 0 4294967295 mmDCP5_OUTPUT_CSC_C21_C22 0 0x493f 0 0 4294967295 mmDCP5_OUTPUT_CSC_C23_C24 0 0x4940 0 0 4294967295 mmDCP5_OUTPUT_CSC_C31_C32 0 0x4941 0 0 4294967295 mmDCP5_OUTPUT_CSC_C33_C34 0 0x4942 0 0 4294967295 mmDCP5_OUTPUT_CSC_CONTROL 0 0x493c 0 0 4294967295 mmDCP5_OUT_ROUND_CONTROL 0 0x4951 0 0 4294967295 mmDCP5_OVL_CONTROL1 0 0x491d 0 0 4294967295 mmDCP5_OVL_CONTROL2 0 0x491e 0 0 4294967295 mmDCP5_OVL_DFQ_CONTROL 0 0x4929 0 0 4294967295 mmDCP5_OVL_DFQ_STATUS 0 0x492a 0 0 4294967295 mmDCP5_OVL_ENABLE 0 0x491c 0 0 4294967295 mmDCP5_OVL_END 0 0x4926 0 0 4294967295 mmDCP5_OVL_PITCH 0 0x4921 0 0 4294967295 mmDCP5_OVLSCL_EDGE_PIXEL_CNTL 0 0x492c 0 0 4294967295 mmDCP5_OVL_SECONDARY_SURFACE_ADDRESS 0 0x4992 0 0 4294967295 mmDCP5_OVL_SECONDARY_SURFACE_ADDRESS_HIGH 0 0x4994 0 0 4294967295 mmDCP5_OVL_START 0 0x4925 0 0 4294967295 mmDCP5_OVL_STEREOSYNC_FLIP 0 0x4993 0 0 4294967295 mmDCP5_OVL_SURFACE_ADDRESS 0 0x4920 0 0 4294967295 mmDCP5_OVL_SURFACE_ADDRESS_HIGH 0 0x4922 0 0 4294967295 mmDCP5_OVL_SURFACE_ADDRESS_HIGH_INUSE 0 0x492b 0 0 4294967295 mmDCP5_OVL_SURFACE_ADDRESS_INUSE 0 0x4928 0 0 4294967295 mmDCP5_OVL_SURFACE_OFFSET_X 0 0x4923 0 0 4294967295 mmDCP5_OVL_SURFACE_OFFSET_Y 0 0x4924 0 0 4294967295 mmDCP5_OVL_SWAP_CNTL 0 0x491f 0 0 4294967295 mmDCP5_OVL_UPDATE 0 0x4927 0 0 4294967295 mmDCP5_PRESCALE_GRPH_CONTROL 0 0x492d 0 0 4294967295 mmDCP5_PRESCALE_OVL_CONTROL 0 0x4931 0 0 4294967295 mmDCP5_PRESCALE_VALUES_GRPH_B 0 0x4930 0 0 4294967295 mmDCP5_PRESCALE_VALUES_GRPH_G 0 0x492f 0 0 4294967295 mmDCP5_PRESCALE_VALUES_GRPH_R 0 0x492e 0 0 4294967295 mmDCP5_PRESCALE_VALUES_OVL_CB 0 0x4932 0 0 4294967295 mmDCP5_PRESCALE_VALUES_OVL_CR 0 0x4934 0 0 4294967295 mmDCP5_PRESCALE_VALUES_OVL_Y 0 0x4933 0 0 4294967295 mmDCP5_REGAMMA_CNTLA_END_CNTL1 0 0x49a6 0 0 4294967295 mmDCP5_REGAMMA_CNTLA_END_CNTL2 0 0x49a7 0 0 4294967295 mmDCP5_REGAMMA_CNTLA_REGION_0_1 0 0x49a8 0 0 4294967295 mmDCP5_REGAMMA_CNTLA_REGION_10_11 0 0x49ad 0 0 4294967295 mmDCP5_REGAMMA_CNTLA_REGION_12_13 0 0x49ae 0 0 4294967295 mmDCP5_REGAMMA_CNTLA_REGION_14_15 0 0x49af 0 0 4294967295 mmDCP5_REGAMMA_CNTLA_REGION_2_3 0 0x49a9 0 0 4294967295 mmDCP5_REGAMMA_CNTLA_REGION_4_5 0 0x49aa 0 0 4294967295 mmDCP5_REGAMMA_CNTLA_REGION_6_7 0 0x49ab 0 0 4294967295 mmDCP5_REGAMMA_CNTLA_REGION_8_9 0 0x49ac 0 0 4294967295 mmDCP5_REGAMMA_CNTLA_SLOPE_CNTL 0 0x49a5 0 0 4294967295 mmDCP5_REGAMMA_CNTLA_START_CNTL 0 0x49a4 0 0 4294967295 mmDCP5_REGAMMA_CNTLB_END_CNTL1 0 0x49b2 0 0 4294967295 mmDCP5_REGAMMA_CNTLB_END_CNTL2 0 0x49b3 0 0 4294967295 mmDCP5_REGAMMA_CNTLB_REGION_0_1 0 0x49b4 0 0 4294967295 mmDCP5_REGAMMA_CNTLB_REGION_10_11 0 0x49b9 0 0 4294967295 mmDCP5_REGAMMA_CNTLB_REGION_12_13 0 0x49ba 0 0 4294967295 mmDCP5_REGAMMA_CNTLB_REGION_14_15 0 0x49bb 0 0 4294967295 mmDCP5_REGAMMA_CNTLB_REGION_2_3 0 0x49b5 0 0 4294967295 mmDCP5_REGAMMA_CNTLB_REGION_4_5 0 0x49b6 0 0 4294967295 mmDCP5_REGAMMA_CNTLB_REGION_6_7 0 0x49b7 0 0 4294967295 mmDCP5_REGAMMA_CNTLB_REGION_8_9 0 0x49b8 0 0 4294967295 mmDCP5_REGAMMA_CNTLB_SLOPE_CNTL 0 0x49b1 0 0 4294967295 mmDCP5_REGAMMA_CNTLB_START_CNTL 0 0x49b0 0 0 4294967295 mmDCP5_REGAMMA_CONTROL 0 0x49a0 0 0 4294967295 mmDCP5_REGAMMA_LUT_DATA 0 0x49a2 0 0 4294967295 mmDCP5_REGAMMA_LUT_INDEX 0 0x49a1 0 0 4294967295 mmDCP5_REGAMMA_LUT_WRITE_EN_MASK 0 0x49a3 0 0 4294967295 mmDC_PAD_EXTERN_SIG 0 0x1902 2 0 4294967295 DC_PAD_EXTERN_SIG_SEL 0 3 MVP_PIXEL_SRC_STATUS 4 5 mmDCP_CRC_CONTROL 0 0x1a87 3 0 4294967295 DCP_CRC_ENABLE 0 0 DCP_CRC_LINE_SEL 8 9 DCP_CRC_SOURCE_SEL 2 4 mmDCP_CRC_CURRENT 0 0x1a89 1 0 4294967295 DCP_CRC_CURRENT 0 31 mmDCP_CRC_LAST 0 0x1a8b 1 0 4294967295 DCP_CRC_LAST 0 31 mmDCP_CRC_MASK 0 0x1a88 1 0 4294967295 DCP_CRC_MASK 0 31 mmDCP_DEBUG 0 0x1a8d 1 0 4294967295 DCP_DEBUG 0 31 mmDCP_DEBUG2 0 0x1a98 1 0 4294967295 DCP_DEBUG2 0 31 mmDCP_FP_CONVERTED_FIELD 0 0x1a65 2 0 4294967295 DCP_FP_CONVERTED_FIELD_DATA 0 17 DCP_FP_CONVERTED_FIELD_INDEX 20 26 mmDC_PGCNTL_STATUS_REG 0 0x177e 4 0 4294967295 DCPG_ECO_DEBUG 16 31 IPREQ_IGNORE_STATUS 2 2 SWREQ_RWOP_BUSY 0 0 SWREQ_RWOP_FORCE 1 1 mmDC_PGFSM_CONFIG_REG 0 0x177c 1 0 4294967295 PGFSM_CONFIG_REG 0 31 mmDC_PGFSM_WRITE_REG 0 0x177d 1 0 4294967295 PGFSM_WRITE_REG 0 31 mmDCP_GSL_CONTROL 0 0x1a90 9 0 4294967295 DCP_GSL0_EN 0 0 DCP_GSL1_EN 1 1 DCP_GSL2_EN 2 2 DCP_GSL_DELAY_SURFACE_UPDATE_PENDING 27 27 DCP_GSL_HSYNC_FLIP_CHECK_DELAY 28 31 DCP_GSL_HSYNC_FLIP_FORCE_DELAY 12 15 DCP_GSL_MASTER_EN 16 16 DCP_GSL_MODE 8 9 DCP_GSL_SYNC_SOURCE 24 25 mmDCPG_TEST_DEBUG_DATA 0 0x177b 1 0 4294967295 DCPG_TEST_DEBUG_DATA 0 31 mmDCPG_TEST_DEBUG_INDEX 0 0x1779 2 0 4294967295 DCPG_TEST_DEBUG_INDEX 0 7 DCPG_TEST_DEBUG_WRITE_EN 8 8 mmDC_PINSTRAPS 0 0x1917 5 0 4294967295 DC_PINSTRAPS_AUDIO 14 15 DC_PINSTRAPS_BIF_CEC_DIS 10 10 DC_PINSTRAPS_CCBYPASS 16 16 DC_PINSTRAPS_SMS_EN_HARD 13 13 DC_PINSTRAPS_VIP_DEVICE 11 11 mmDCP_LB_DATA_GAP_BETWEEN_CHUNK 0 0x1a91 2 0 4294967295 DCP_LB_GAP_BETWEEN_CHUNK_20BPP 0 3 DCP_LB_GAP_BETWEEN_CHUNK_30BPP 4 7 mmDCP_RANDOM_SEEDS 0 0x1a61 3 0 4294967295 DCP_RAND_B_SEED 16 23 DCP_RAND_G_SEED 8 15 DCP_RAND_R_SEED 0 7 mmDCP_SPATIAL_DITHER_CNTL 0 0x1a60 6 0 4294967295 DCP_FRAME_RANDOM_ENABLE 8 8 DCP_HIGHPASS_RANDOM_ENABLE 10 10 DCP_RGB_RANDOM_ENABLE 9 9 DCP_SPATIAL_DITHER_DEPTH 6 6 DCP_SPATIAL_DITHER_EN 0 0 DCP_SPATIAL_DITHER_MODE 4 5 mmDCP_TEST_DEBUG_DATA 0 0x1a96 1 0 4294967295 DCP_TEST_DEBUG_DATA 0 31 mmDCP_TEST_DEBUG_INDEX 0 0x1a95 2 0 4294967295 DCP_TEST_DEBUG_INDEX 0 7 DCP_TEST_DEBUG_WRITE_EN 8 8 mmDC_RBBMIF_RDWR_CNTL1 0 0x31a 10 0 4294967295 DC_RBBMIF_CLIENT0_RDWR_DELAY 0 2 DC_RBBMIF_CLIENT0_RDWR_TIMEOUT_DIS 3 3 DC_RBBMIF_CLIENT1_RDWR_DELAY 4 6 DC_RBBMIF_CLIENT1_RDWR_TIMEOUT_DIS 7 7 DC_RBBMIF_CLIENT2_RDWR_DELAY 8 10 DC_RBBMIF_CLIENT2_RDWR_TIMEOUT_DIS 11 11 DC_RBBMIF_CLIENT3_RDWR_DELAY 12 14 DC_RBBMIF_CLIENT3_RDWR_TIMEOUT_DIS 15 15 DC_RBBMIF_CLIENT4_RDWR_DELAY 16 18 DC_RBBMIF_CLIENT4_RDWR_TIMEOUT_DIS 19 19 mmDC_RBBMIF_RDWR_CNTL2 0 0x31d 4 0 4294967295 DC_RBBMIF_CLIENT8_RDWR_DELAY 0 2 DC_RBBMIF_CLIENT8_RDWR_TIMEOUT_DIS 3 3 DC_RBBMIF_CLIENT9_RDWR_DELAY 4 6 DC_RBBMIF_CLIENT9_RDWR_TIMEOUT_DIS 7 7 mmDC_REF_CLK_CNTL 0 0x1903 2 0 4294967295 GENLK_CLK_OUTPUT_SEL 8 9 HSYNCA_OUTPUT_SEL 0 1 mmDC_XDMA_INTERFACE_CNTL 0 0x327 6 0 4294967295 DC_FLIP_PENDING_TO_DCP 22 22 DC_XDMA_FLIP_PENDING 16 16 XDMA_M_FLIP_PENDING_TO_DCP 20 20 XDMA_PIPE_ENABLE 0 5 XDMA_PIPE_SEL 8 10 XDMA_S_FLIP_PENDING_TO_DCP 21 21 mmDEGAMMA_CONTROL 0 0x1a58 3 0 4294967295 CURSOR_DEGAMMA_MODE 12 13 GRPH_DEGAMMA_MODE 0 1 OVL_DEGAMMA_MODE 4 5 mmDENORM_CONTROL 0 0x1a50 1 0 4294967295 DENORM_MODE 0 2 mmDENTIST_DISPCLK_CNTL 0 0x124 10 0 4294967295 DENTIST_DISPCLK_CHG_DONE 19 19 DENTIST_DISPCLK_CHG_MODE 15 16 DENTIST_DISPCLK_CHGTOG 17 17 DENTIST_DISPCLK_DONETOG 18 18 DENTIST_DISPCLK_RDIVIDER 8 14 DENTIST_DISPCLK_WDIVIDER 0 6 DENTIST_DPREFCLK_CHG_DONE 20 20 DENTIST_DPREFCLK_CHGTOG 21 21 DENTIST_DPREFCLK_DONETOG 22 22 DENTIST_DPREFCLK_WDIVIDER 24 30 mmDIG0_AFMT_60958_0 0 0x1c41 0 0 4294967295 mmDIG0_AFMT_60958_1 0 0x1c42 0 0 4294967295 mmDIG0_AFMT_60958_2 0 0x1c48 0 0 4294967295 mmDIG0_AFMT_AUDIO_CRC_CONTROL 0 0x1c43 0 0 4294967295 mmDIG0_AFMT_AUDIO_CRC_RESULT 0 0x1c49 0 0 4294967295 mmDIG0_AFMT_AUDIO_DBG_DTO_CNTL 0 0x1c52 0 0 4294967295 mmDIG0_AFMT_AUDIO_INFO0 0 0x1c3f 0 0 4294967295 mmDIG0_AFMT_AUDIO_INFO1 0 0x1c40 0 0 4294967295 mmDIG0_AFMT_AUDIO_PACKET_CONTROL 0 0x1c4b 0 0 4294967295 mmDIG0_AFMT_AUDIO_PACKET_CONTROL2 0 0x1c17 0 0 4294967295 mmDIG0_AFMT_AUDIO_SRC_CONTROL 0 0x1c4f 0 0 4294967295 mmDIG0_AFMT_AVI_INFO0 0 0x1c21 0 0 4294967295 mmDIG0_AFMT_AVI_INFO1 0 0x1c22 0 0 4294967295 mmDIG0_AFMT_AVI_INFO2 0 0x1c23 0 0 4294967295 mmDIG0_AFMT_AVI_INFO3 0 0x1c24 0 0 4294967295 mmDIG0_AFMT_GENERIC_0 0 0x1c28 0 0 4294967295 mmDIG0_AFMT_GENERIC_1 0 0x1c29 0 0 4294967295 mmDIG0_AFMT_GENERIC_2 0 0x1c2a 0 0 4294967295 mmDIG0_AFMT_GENERIC_3 0 0x1c2b 0 0 4294967295 mmDIG0_AFMT_GENERIC_4 0 0x1c2c 0 0 4294967295 mmDIG0_AFMT_GENERIC_5 0 0x1c2d 0 0 4294967295 mmDIG0_AFMT_GENERIC_6 0 0x1c2e 0 0 4294967295 mmDIG0_AFMT_GENERIC_7 0 0x1c2f 0 0 4294967295 mmDIG0_AFMT_GENERIC_HDR 0 0x1c27 0 0 4294967295 mmDIG0_AFMT_INFOFRAME_CONTROL0 0 0x1c4d 0 0 4294967295 mmDIG0_AFMT_INTERRUPT_STATUS 0 0x1c14 0 0 4294967295 mmDIG0_AFMT_ISRC1_0 0 0x1c18 0 0 4294967295 mmDIG0_AFMT_ISRC1_1 0 0x1c19 0 0 4294967295 mmDIG0_AFMT_ISRC1_2 0 0x1c1a 0 0 4294967295 mmDIG0_AFMT_ISRC1_3 0 0x1c1b 0 0 4294967295 mmDIG0_AFMT_ISRC1_4 0 0x1c1c 0 0 4294967295 mmDIG0_AFMT_ISRC2_0 0 0x1c1d 0 0 4294967295 mmDIG0_AFMT_ISRC2_1 0 0x1c1e 0 0 4294967295 mmDIG0_AFMT_ISRC2_2 0 0x1c1f 0 0 4294967295 mmDIG0_AFMT_ISRC2_3 0 0x1c20 0 0 4294967295 mmDIG0_AFMT_MPEG_INFO0 0 0x1c25 0 0 4294967295 mmDIG0_AFMT_MPEG_INFO1 0 0x1c26 0 0 4294967295 mmDIG0_AFMT_RAMP_CONTROL0 0 0x1c44 0 0 4294967295 mmDIG0_AFMT_RAMP_CONTROL1 0 0x1c45 0 0 4294967295 mmDIG0_AFMT_RAMP_CONTROL2 0 0x1c46 0 0 4294967295 mmDIG0_AFMT_RAMP_CONTROL3 0 0x1c47 0 0 4294967295 mmDIG0_AFMT_STATUS 0 0x1c4a 0 0 4294967295 mmDIG0_AFMT_VBI_PACKET_CONTROL 0 0x1c4c 0 0 4294967295 mmDIG0_DIG_BE_CNTL 0 0x1c50 0 0 4294967295 mmDIG0_DIG_BE_EN_CNTL 0 0x1c51 0 0 4294967295 mmDIG0_DIG_CLOCK_PATTERN 0 0x1c03 0 0 4294967295 mmDIG0_DIG_DISPCLK_SWITCH_CNTL 0 0x1c08 0 0 4294967295 mmDIG0_DIG_DISPCLK_SWITCH_STATUS 0 0x1c09 0 0 4294967295 mmDIG0_DIG_FE_CNTL 0 0x1c00 0 0 4294967295 mmDIG0_DIG_FIFO_STATUS 0 0x1c0a 0 0 4294967295 mmDIG0_DIG_LANE_ENABLE 0 0x1c8d 0 0 4294967295 mmDIG0_DIG_OUTPUT_CRC_CNTL 0 0x1c01 0 0 4294967295 mmDIG0_DIG_OUTPUT_CRC_RESULT 0 0x1c02 0 0 4294967295 mmDIG0_DIG_RANDOM_PATTERN_SEED 0 0x1c05 0 0 4294967295 mmDIG0_DIG_TEST_PATTERN 0 0x1c04 0 0 4294967295 mmDIG0_HDMI_ACR_32_0 0 0x1c37 0 0 4294967295 mmDIG0_HDMI_ACR_32_1 0 0x1c38 0 0 4294967295 mmDIG0_HDMI_ACR_44_0 0 0x1c39 0 0 4294967295 mmDIG0_HDMI_ACR_44_1 0 0x1c3a 0 0 4294967295 mmDIG0_HDMI_ACR_48_0 0 0x1c3b 0 0 4294967295 mmDIG0_HDMI_ACR_48_1 0 0x1c3c 0 0 4294967295 mmDIG0_HDMI_ACR_PACKET_CONTROL 0 0x1c0f 0 0 4294967295 mmDIG0_HDMI_ACR_STATUS_0 0 0x1c3d 0 0 4294967295 mmDIG0_HDMI_ACR_STATUS_1 0 0x1c3e 0 0 4294967295 mmDIG0_HDMI_AUDIO_PACKET_CONTROL 0 0x1c0e 0 0 4294967295 mmDIG0_HDMI_CONTROL 0 0x1c0c 0 0 4294967295 mmDIG0_HDMI_GC 0 0x1c16 0 0 4294967295 mmDIG0_HDMI_GENERIC_PACKET_CONTROL0 0 0x1c13 0 0 4294967295 mmDIG0_HDMI_GENERIC_PACKET_CONTROL1 0 0x1c30 0 0 4294967295 mmDIG0_HDMI_INFOFRAME_CONTROL0 0 0x1c11 0 0 4294967295 mmDIG0_HDMI_INFOFRAME_CONTROL1 0 0x1c12 0 0 4294967295 mmDIG0_HDMI_STATUS 0 0x1c0d 0 0 4294967295 mmDIG0_HDMI_VBI_PACKET_CONTROL 0 0x1c10 0 0 4294967295 mmDIG0_LVDS_DATA_CNTL 0 0x1c8c 0 0 4294967295 mmDIG0_TMDS_CNTL 0 0x1c7c 0 0 4294967295 mmDIG0_TMDS_CONTROL0_FEEDBACK 0 0x1c7e 0 0 4294967295 mmDIG0_TMDS_CONTROL_CHAR 0 0x1c7d 0 0 4294967295 mmDIG0_TMDS_CTL0_1_GEN_CNTL 0 0x1c86 0 0 4294967295 mmDIG0_TMDS_CTL2_3_GEN_CNTL 0 0x1c87 0 0 4294967295 mmDIG0_TMDS_CTL_BITS 0 0x1c83 0 0 4294967295 mmDIG0_TMDS_DCBALANCER_CONTROL 0 0x1c84 0 0 4294967295 mmDIG0_TMDS_DEBUG 0 0x1c82 0 0 4294967295 mmDIG0_TMDS_STEREOSYNC_CTL_SEL 0 0x1c7f 0 0 4294967295 mmDIG0_TMDS_SYNC_CHAR_PATTERN_0_1 0 0x1c80 0 0 4294967295 mmDIG0_TMDS_SYNC_CHAR_PATTERN_2_3 0 0x1c81 0 0 4294967295 mmDIG1_AFMT_60958_0 0 0x1f41 0 0 4294967295 mmDIG1_AFMT_60958_1 0 0x1f42 0 0 4294967295 mmDIG1_AFMT_60958_2 0 0x1f48 0 0 4294967295 mmDIG1_AFMT_AUDIO_CRC_CONTROL 0 0x1f43 0 0 4294967295 mmDIG1_AFMT_AUDIO_CRC_RESULT 0 0x1f49 0 0 4294967295 mmDIG1_AFMT_AUDIO_DBG_DTO_CNTL 0 0x1f52 0 0 4294967295 mmDIG1_AFMT_AUDIO_INFO0 0 0x1f3f 0 0 4294967295 mmDIG1_AFMT_AUDIO_INFO1 0 0x1f40 0 0 4294967295 mmDIG1_AFMT_AUDIO_PACKET_CONTROL 0 0x1f4b 0 0 4294967295 mmDIG1_AFMT_AUDIO_PACKET_CONTROL2 0 0x1f17 0 0 4294967295 mmDIG1_AFMT_AUDIO_SRC_CONTROL 0 0x1f4f 0 0 4294967295 mmDIG1_AFMT_AVI_INFO0 0 0x1f21 0 0 4294967295 mmDIG1_AFMT_AVI_INFO1 0 0x1f22 0 0 4294967295 mmDIG1_AFMT_AVI_INFO2 0 0x1f23 0 0 4294967295 mmDIG1_AFMT_AVI_INFO3 0 0x1f24 0 0 4294967295 mmDIG1_AFMT_GENERIC_0 0 0x1f28 0 0 4294967295 mmDIG1_AFMT_GENERIC_1 0 0x1f29 0 0 4294967295 mmDIG1_AFMT_GENERIC_2 0 0x1f2a 0 0 4294967295 mmDIG1_AFMT_GENERIC_3 0 0x1f2b 0 0 4294967295 mmDIG1_AFMT_GENERIC_4 0 0x1f2c 0 0 4294967295 mmDIG1_AFMT_GENERIC_5 0 0x1f2d 0 0 4294967295 mmDIG1_AFMT_GENERIC_6 0 0x1f2e 0 0 4294967295 mmDIG1_AFMT_GENERIC_7 0 0x1f2f 0 0 4294967295 mmDIG1_AFMT_GENERIC_HDR 0 0x1f27 0 0 4294967295 mmDIG1_AFMT_INFOFRAME_CONTROL0 0 0x1f4d 0 0 4294967295 mmDIG1_AFMT_INTERRUPT_STATUS 0 0x1f14 0 0 4294967295 mmDIG1_AFMT_ISRC1_0 0 0x1f18 0 0 4294967295 mmDIG1_AFMT_ISRC1_1 0 0x1f19 0 0 4294967295 mmDIG1_AFMT_ISRC1_2 0 0x1f1a 0 0 4294967295 mmDIG1_AFMT_ISRC1_3 0 0x1f1b 0 0 4294967295 mmDIG1_AFMT_ISRC1_4 0 0x1f1c 0 0 4294967295 mmDIG1_AFMT_ISRC2_0 0 0x1f1d 0 0 4294967295 mmDIG1_AFMT_ISRC2_1 0 0x1f1e 0 0 4294967295 mmDIG1_AFMT_ISRC2_2 0 0x1f1f 0 0 4294967295 mmDIG1_AFMT_ISRC2_3 0 0x1f20 0 0 4294967295 mmDIG1_AFMT_MPEG_INFO0 0 0x1f25 0 0 4294967295 mmDIG1_AFMT_MPEG_INFO1 0 0x1f26 0 0 4294967295 mmDIG1_AFMT_RAMP_CONTROL0 0 0x1f44 0 0 4294967295 mmDIG1_AFMT_RAMP_CONTROL1 0 0x1f45 0 0 4294967295 mmDIG1_AFMT_RAMP_CONTROL2 0 0x1f46 0 0 4294967295 mmDIG1_AFMT_RAMP_CONTROL3 0 0x1f47 0 0 4294967295 mmDIG1_AFMT_STATUS 0 0x1f4a 0 0 4294967295 mmDIG1_AFMT_VBI_PACKET_CONTROL 0 0x1f4c 0 0 4294967295 mmDIG1_DIG_BE_CNTL 0 0x1f50 0 0 4294967295 mmDIG1_DIG_BE_EN_CNTL 0 0x1f51 0 0 4294967295 mmDIG1_DIG_CLOCK_PATTERN 0 0x1f03 0 0 4294967295 mmDIG1_DIG_DISPCLK_SWITCH_CNTL 0 0x1f08 0 0 4294967295 mmDIG1_DIG_DISPCLK_SWITCH_STATUS 0 0x1f09 0 0 4294967295 mmDIG1_DIG_FE_CNTL 0 0x1f00 0 0 4294967295 mmDIG1_DIG_FIFO_STATUS 0 0x1f0a 0 0 4294967295 mmDIG1_DIG_LANE_ENABLE 0 0x1f8d 0 0 4294967295 mmDIG1_DIG_OUTPUT_CRC_CNTL 0 0x1f01 0 0 4294967295 mmDIG1_DIG_OUTPUT_CRC_RESULT 0 0x1f02 0 0 4294967295 mmDIG1_DIG_RANDOM_PATTERN_SEED 0 0x1f05 0 0 4294967295 mmDIG1_DIG_TEST_PATTERN 0 0x1f04 0 0 4294967295 mmDIG1_HDMI_ACR_32_0 0 0x1f37 0 0 4294967295 mmDIG1_HDMI_ACR_32_1 0 0x1f38 0 0 4294967295 mmDIG1_HDMI_ACR_44_0 0 0x1f39 0 0 4294967295 mmDIG1_HDMI_ACR_44_1 0 0x1f3a 0 0 4294967295 mmDIG1_HDMI_ACR_48_0 0 0x1f3b 0 0 4294967295 mmDIG1_HDMI_ACR_48_1 0 0x1f3c 0 0 4294967295 mmDIG1_HDMI_ACR_PACKET_CONTROL 0 0x1f0f 0 0 4294967295 mmDIG1_HDMI_ACR_STATUS_0 0 0x1f3d 0 0 4294967295 mmDIG1_HDMI_ACR_STATUS_1 0 0x1f3e 0 0 4294967295 mmDIG1_HDMI_AUDIO_PACKET_CONTROL 0 0x1f0e 0 0 4294967295 mmDIG1_HDMI_CONTROL 0 0x1f0c 0 0 4294967295 mmDIG1_HDMI_GC 0 0x1f16 0 0 4294967295 mmDIG1_HDMI_GENERIC_PACKET_CONTROL0 0 0x1f13 0 0 4294967295 mmDIG1_HDMI_GENERIC_PACKET_CONTROL1 0 0x1f30 0 0 4294967295 mmDIG1_HDMI_INFOFRAME_CONTROL0 0 0x1f11 0 0 4294967295 mmDIG1_HDMI_INFOFRAME_CONTROL1 0 0x1f12 0 0 4294967295 mmDIG1_HDMI_STATUS 0 0x1f0d 0 0 4294967295 mmDIG1_HDMI_VBI_PACKET_CONTROL 0 0x1f10 0 0 4294967295 mmDIG1_LVDS_DATA_CNTL 0 0x1f8c 0 0 4294967295 mmDIG1_TMDS_CNTL 0 0x1f7c 0 0 4294967295 mmDIG1_TMDS_CONTROL0_FEEDBACK 0 0x1f7e 0 0 4294967295 mmDIG1_TMDS_CONTROL_CHAR 0 0x1f7d 0 0 4294967295 mmDIG1_TMDS_CTL0_1_GEN_CNTL 0 0x1f86 0 0 4294967295 mmDIG1_TMDS_CTL2_3_GEN_CNTL 0 0x1f87 0 0 4294967295 mmDIG1_TMDS_CTL_BITS 0 0x1f83 0 0 4294967295 mmDIG1_TMDS_DCBALANCER_CONTROL 0 0x1f84 0 0 4294967295 mmDIG1_TMDS_DEBUG 0 0x1f82 0 0 4294967295 mmDIG1_TMDS_STEREOSYNC_CTL_SEL 0 0x1f7f 0 0 4294967295 mmDIG1_TMDS_SYNC_CHAR_PATTERN_0_1 0 0x1f80 0 0 4294967295 mmDIG1_TMDS_SYNC_CHAR_PATTERN_2_3 0 0x1f81 0 0 4294967295 mmDIG2_AFMT_60958_0 0 0x4241 0 0 4294967295 mmDIG2_AFMT_60958_1 0 0x4242 0 0 4294967295 mmDIG2_AFMT_60958_2 0 0x4248 0 0 4294967295 mmDIG2_AFMT_AUDIO_CRC_CONTROL 0 0x4243 0 0 4294967295 mmDIG2_AFMT_AUDIO_CRC_RESULT 0 0x4249 0 0 4294967295 mmDIG2_AFMT_AUDIO_DBG_DTO_CNTL 0 0x4252 0 0 4294967295 mmDIG2_AFMT_AUDIO_INFO0 0 0x423f 0 0 4294967295 mmDIG2_AFMT_AUDIO_INFO1 0 0x4240 0 0 4294967295 mmDIG2_AFMT_AUDIO_PACKET_CONTROL 0 0x424b 0 0 4294967295 mmDIG2_AFMT_AUDIO_PACKET_CONTROL2 0 0x4217 0 0 4294967295 mmDIG2_AFMT_AUDIO_SRC_CONTROL 0 0x424f 0 0 4294967295 mmDIG2_AFMT_AVI_INFO0 0 0x4221 0 0 4294967295 mmDIG2_AFMT_AVI_INFO1 0 0x4222 0 0 4294967295 mmDIG2_AFMT_AVI_INFO2 0 0x4223 0 0 4294967295 mmDIG2_AFMT_AVI_INFO3 0 0x4224 0 0 4294967295 mmDIG2_AFMT_GENERIC_0 0 0x4228 0 0 4294967295 mmDIG2_AFMT_GENERIC_1 0 0x4229 0 0 4294967295 mmDIG2_AFMT_GENERIC_2 0 0x422a 0 0 4294967295 mmDIG2_AFMT_GENERIC_3 0 0x422b 0 0 4294967295 mmDIG2_AFMT_GENERIC_4 0 0x422c 0 0 4294967295 mmDIG2_AFMT_GENERIC_5 0 0x422d 0 0 4294967295 mmDIG2_AFMT_GENERIC_6 0 0x422e 0 0 4294967295 mmDIG2_AFMT_GENERIC_7 0 0x422f 0 0 4294967295 mmDIG2_AFMT_GENERIC_HDR 0 0x4227 0 0 4294967295 mmDIG2_AFMT_INFOFRAME_CONTROL0 0 0x424d 0 0 4294967295 mmDIG2_AFMT_INTERRUPT_STATUS 0 0x4214 0 0 4294967295 mmDIG2_AFMT_ISRC1_0 0 0x4218 0 0 4294967295 mmDIG2_AFMT_ISRC1_1 0 0x4219 0 0 4294967295 mmDIG2_AFMT_ISRC1_2 0 0x421a 0 0 4294967295 mmDIG2_AFMT_ISRC1_3 0 0x421b 0 0 4294967295 mmDIG2_AFMT_ISRC1_4 0 0x421c 0 0 4294967295 mmDIG2_AFMT_ISRC2_0 0 0x421d 0 0 4294967295 mmDIG2_AFMT_ISRC2_1 0 0x421e 0 0 4294967295 mmDIG2_AFMT_ISRC2_2 0 0x421f 0 0 4294967295 mmDIG2_AFMT_ISRC2_3 0 0x4220 0 0 4294967295 mmDIG2_AFMT_MPEG_INFO0 0 0x4225 0 0 4294967295 mmDIG2_AFMT_MPEG_INFO1 0 0x4226 0 0 4294967295 mmDIG2_AFMT_RAMP_CONTROL0 0 0x4244 0 0 4294967295 mmDIG2_AFMT_RAMP_CONTROL1 0 0x4245 0 0 4294967295 mmDIG2_AFMT_RAMP_CONTROL2 0 0x4246 0 0 4294967295 mmDIG2_AFMT_RAMP_CONTROL3 0 0x4247 0 0 4294967295 mmDIG2_AFMT_STATUS 0 0x424a 0 0 4294967295 mmDIG2_AFMT_VBI_PACKET_CONTROL 0 0x424c 0 0 4294967295 mmDIG2_DIG_BE_CNTL 0 0x4250 0 0 4294967295 mmDIG2_DIG_BE_EN_CNTL 0 0x4251 0 0 4294967295 mmDIG2_DIG_CLOCK_PATTERN 0 0x4203 0 0 4294967295 mmDIG2_DIG_DISPCLK_SWITCH_CNTL 0 0x4208 0 0 4294967295 mmDIG2_DIG_DISPCLK_SWITCH_STATUS 0 0x4209 0 0 4294967295 mmDIG2_DIG_FE_CNTL 0 0x4200 0 0 4294967295 mmDIG2_DIG_FIFO_STATUS 0 0x420a 0 0 4294967295 mmDIG2_DIG_LANE_ENABLE 0 0x428d 0 0 4294967295 mmDIG2_DIG_OUTPUT_CRC_CNTL 0 0x4201 0 0 4294967295 mmDIG2_DIG_OUTPUT_CRC_RESULT 0 0x4202 0 0 4294967295 mmDIG2_DIG_RANDOM_PATTERN_SEED 0 0x4205 0 0 4294967295 mmDIG2_DIG_TEST_PATTERN 0 0x4204 0 0 4294967295 mmDIG2_HDMI_ACR_32_0 0 0x4237 0 0 4294967295 mmDIG2_HDMI_ACR_32_1 0 0x4238 0 0 4294967295 mmDIG2_HDMI_ACR_44_0 0 0x4239 0 0 4294967295 mmDIG2_HDMI_ACR_44_1 0 0x423a 0 0 4294967295 mmDIG2_HDMI_ACR_48_0 0 0x423b 0 0 4294967295 mmDIG2_HDMI_ACR_48_1 0 0x423c 0 0 4294967295 mmDIG2_HDMI_ACR_PACKET_CONTROL 0 0x420f 0 0 4294967295 mmDIG2_HDMI_ACR_STATUS_0 0 0x423d 0 0 4294967295 mmDIG2_HDMI_ACR_STATUS_1 0 0x423e 0 0 4294967295 mmDIG2_HDMI_AUDIO_PACKET_CONTROL 0 0x420e 0 0 4294967295 mmDIG2_HDMI_CONTROL 0 0x420c 0 0 4294967295 mmDIG2_HDMI_GC 0 0x4216 0 0 4294967295 mmDIG2_HDMI_GENERIC_PACKET_CONTROL0 0 0x4213 0 0 4294967295 mmDIG2_HDMI_GENERIC_PACKET_CONTROL1 0 0x4230 0 0 4294967295 mmDIG2_HDMI_INFOFRAME_CONTROL0 0 0x4211 0 0 4294967295 mmDIG2_HDMI_INFOFRAME_CONTROL1 0 0x4212 0 0 4294967295 mmDIG2_HDMI_STATUS 0 0x420d 0 0 4294967295 mmDIG2_HDMI_VBI_PACKET_CONTROL 0 0x4210 0 0 4294967295 mmDIG2_LVDS_DATA_CNTL 0 0x428c 0 0 4294967295 mmDIG2_TMDS_CNTL 0 0x427c 0 0 4294967295 mmDIG2_TMDS_CONTROL0_FEEDBACK 0 0x427e 0 0 4294967295 mmDIG2_TMDS_CONTROL_CHAR 0 0x427d 0 0 4294967295 mmDIG2_TMDS_CTL0_1_GEN_CNTL 0 0x4286 0 0 4294967295 mmDIG2_TMDS_CTL2_3_GEN_CNTL 0 0x4287 0 0 4294967295 mmDIG2_TMDS_CTL_BITS 0 0x4283 0 0 4294967295 mmDIG2_TMDS_DCBALANCER_CONTROL 0 0x4284 0 0 4294967295 mmDIG2_TMDS_DEBUG 0 0x4282 0 0 4294967295 mmDIG2_TMDS_STEREOSYNC_CTL_SEL 0 0x427f 0 0 4294967295 mmDIG2_TMDS_SYNC_CHAR_PATTERN_0_1 0 0x4280 0 0 4294967295 mmDIG2_TMDS_SYNC_CHAR_PATTERN_2_3 0 0x4281 0 0 4294967295 mmDIG3_AFMT_60958_0 0 0x4541 0 0 4294967295 mmDIG3_AFMT_60958_1 0 0x4542 0 0 4294967295 mmDIG3_AFMT_60958_2 0 0x4548 0 0 4294967295 mmDIG3_AFMT_AUDIO_CRC_CONTROL 0 0x4543 0 0 4294967295 mmDIG3_AFMT_AUDIO_CRC_RESULT 0 0x4549 0 0 4294967295 mmDIG3_AFMT_AUDIO_DBG_DTO_CNTL 0 0x4552 0 0 4294967295 mmDIG3_AFMT_AUDIO_INFO0 0 0x453f 0 0 4294967295 mmDIG3_AFMT_AUDIO_INFO1 0 0x4540 0 0 4294967295 mmDIG3_AFMT_AUDIO_PACKET_CONTROL 0 0x454b 0 0 4294967295 mmDIG3_AFMT_AUDIO_PACKET_CONTROL2 0 0x4517 0 0 4294967295 mmDIG3_AFMT_AUDIO_SRC_CONTROL 0 0x454f 0 0 4294967295 mmDIG3_AFMT_AVI_INFO0 0 0x4521 0 0 4294967295 mmDIG3_AFMT_AVI_INFO1 0 0x4522 0 0 4294967295 mmDIG3_AFMT_AVI_INFO2 0 0x4523 0 0 4294967295 mmDIG3_AFMT_AVI_INFO3 0 0x4524 0 0 4294967295 mmDIG3_AFMT_GENERIC_0 0 0x4528 0 0 4294967295 mmDIG3_AFMT_GENERIC_1 0 0x4529 0 0 4294967295 mmDIG3_AFMT_GENERIC_2 0 0x452a 0 0 4294967295 mmDIG3_AFMT_GENERIC_3 0 0x452b 0 0 4294967295 mmDIG3_AFMT_GENERIC_4 0 0x452c 0 0 4294967295 mmDIG3_AFMT_GENERIC_5 0 0x452d 0 0 4294967295 mmDIG3_AFMT_GENERIC_6 0 0x452e 0 0 4294967295 mmDIG3_AFMT_GENERIC_7 0 0x452f 0 0 4294967295 mmDIG3_AFMT_GENERIC_HDR 0 0x4527 0 0 4294967295 mmDIG3_AFMT_INFOFRAME_CONTROL0 0 0x454d 0 0 4294967295 mmDIG3_AFMT_INTERRUPT_STATUS 0 0x4514 0 0 4294967295 mmDIG3_AFMT_ISRC1_0 0 0x4518 0 0 4294967295 mmDIG3_AFMT_ISRC1_1 0 0x4519 0 0 4294967295 mmDIG3_AFMT_ISRC1_2 0 0x451a 0 0 4294967295 mmDIG3_AFMT_ISRC1_3 0 0x451b 0 0 4294967295 mmDIG3_AFMT_ISRC1_4 0 0x451c 0 0 4294967295 mmDIG3_AFMT_ISRC2_0 0 0x451d 0 0 4294967295 mmDIG3_AFMT_ISRC2_1 0 0x451e 0 0 4294967295 mmDIG3_AFMT_ISRC2_2 0 0x451f 0 0 4294967295 mmDIG3_AFMT_ISRC2_3 0 0x4520 0 0 4294967295 mmDIG3_AFMT_MPEG_INFO0 0 0x4525 0 0 4294967295 mmDIG3_AFMT_MPEG_INFO1 0 0x4526 0 0 4294967295 mmDIG3_AFMT_RAMP_CONTROL0 0 0x4544 0 0 4294967295 mmDIG3_AFMT_RAMP_CONTROL1 0 0x4545 0 0 4294967295 mmDIG3_AFMT_RAMP_CONTROL2 0 0x4546 0 0 4294967295 mmDIG3_AFMT_RAMP_CONTROL3 0 0x4547 0 0 4294967295 mmDIG3_AFMT_STATUS 0 0x454a 0 0 4294967295 mmDIG3_AFMT_VBI_PACKET_CONTROL 0 0x454c 0 0 4294967295 mmDIG3_DIG_BE_CNTL 0 0x4550 0 0 4294967295 mmDIG3_DIG_BE_EN_CNTL 0 0x4551 0 0 4294967295 mmDIG3_DIG_CLOCK_PATTERN 0 0x4503 0 0 4294967295 mmDIG3_DIG_DISPCLK_SWITCH_CNTL 0 0x4508 0 0 4294967295 mmDIG3_DIG_DISPCLK_SWITCH_STATUS 0 0x4509 0 0 4294967295 mmDIG3_DIG_FE_CNTL 0 0x4500 0 0 4294967295 mmDIG3_DIG_FIFO_STATUS 0 0x450a 0 0 4294967295 mmDIG3_DIG_LANE_ENABLE 0 0x458d 0 0 4294967295 mmDIG3_DIG_OUTPUT_CRC_CNTL 0 0x4501 0 0 4294967295 mmDIG3_DIG_OUTPUT_CRC_RESULT 0 0x4502 0 0 4294967295 mmDIG3_DIG_RANDOM_PATTERN_SEED 0 0x4505 0 0 4294967295 mmDIG3_DIG_TEST_PATTERN 0 0x4504 0 0 4294967295 mmDIG3_HDMI_ACR_32_0 0 0x4537 0 0 4294967295 mmDIG3_HDMI_ACR_32_1 0 0x4538 0 0 4294967295 mmDIG3_HDMI_ACR_44_0 0 0x4539 0 0 4294967295 mmDIG3_HDMI_ACR_44_1 0 0x453a 0 0 4294967295 mmDIG3_HDMI_ACR_48_0 0 0x453b 0 0 4294967295 mmDIG3_HDMI_ACR_48_1 0 0x453c 0 0 4294967295 mmDIG3_HDMI_ACR_PACKET_CONTROL 0 0x450f 0 0 4294967295 mmDIG3_HDMI_ACR_STATUS_0 0 0x453d 0 0 4294967295 mmDIG3_HDMI_ACR_STATUS_1 0 0x453e 0 0 4294967295 mmDIG3_HDMI_AUDIO_PACKET_CONTROL 0 0x450e 0 0 4294967295 mmDIG3_HDMI_CONTROL 0 0x450c 0 0 4294967295 mmDIG3_HDMI_GC 0 0x4516 0 0 4294967295 mmDIG3_HDMI_GENERIC_PACKET_CONTROL0 0 0x4513 0 0 4294967295 mmDIG3_HDMI_GENERIC_PACKET_CONTROL1 0 0x4530 0 0 4294967295 mmDIG3_HDMI_INFOFRAME_CONTROL0 0 0x4511 0 0 4294967295 mmDIG3_HDMI_INFOFRAME_CONTROL1 0 0x4512 0 0 4294967295 mmDIG3_HDMI_STATUS 0 0x450d 0 0 4294967295 mmDIG3_HDMI_VBI_PACKET_CONTROL 0 0x4510 0 0 4294967295 mmDIG3_LVDS_DATA_CNTL 0 0x458c 0 0 4294967295 mmDIG3_TMDS_CNTL 0 0x457c 0 0 4294967295 mmDIG3_TMDS_CONTROL0_FEEDBACK 0 0x457e 0 0 4294967295 mmDIG3_TMDS_CONTROL_CHAR 0 0x457d 0 0 4294967295 mmDIG3_TMDS_CTL0_1_GEN_CNTL 0 0x4586 0 0 4294967295 mmDIG3_TMDS_CTL2_3_GEN_CNTL 0 0x4587 0 0 4294967295 mmDIG3_TMDS_CTL_BITS 0 0x4583 0 0 4294967295 mmDIG3_TMDS_DCBALANCER_CONTROL 0 0x4584 0 0 4294967295 mmDIG3_TMDS_DEBUG 0 0x4582 0 0 4294967295 mmDIG3_TMDS_STEREOSYNC_CTL_SEL 0 0x457f 0 0 4294967295 mmDIG3_TMDS_SYNC_CHAR_PATTERN_0_1 0 0x4580 0 0 4294967295 mmDIG3_TMDS_SYNC_CHAR_PATTERN_2_3 0 0x4581 0 0 4294967295 mmDIG4_AFMT_60958_0 0 0x4841 0 0 4294967295 mmDIG4_AFMT_60958_1 0 0x4842 0 0 4294967295 mmDIG4_AFMT_60958_2 0 0x4848 0 0 4294967295 mmDIG4_AFMT_AUDIO_CRC_CONTROL 0 0x4843 0 0 4294967295 mmDIG4_AFMT_AUDIO_CRC_RESULT 0 0x4849 0 0 4294967295 mmDIG4_AFMT_AUDIO_DBG_DTO_CNTL 0 0x4852 0 0 4294967295 mmDIG4_AFMT_AUDIO_INFO0 0 0x483f 0 0 4294967295 mmDIG4_AFMT_AUDIO_INFO1 0 0x4840 0 0 4294967295 mmDIG4_AFMT_AUDIO_PACKET_CONTROL 0 0x484b 0 0 4294967295 mmDIG4_AFMT_AUDIO_PACKET_CONTROL2 0 0x4817 0 0 4294967295 mmDIG4_AFMT_AUDIO_SRC_CONTROL 0 0x484f 0 0 4294967295 mmDIG4_AFMT_AVI_INFO0 0 0x4821 0 0 4294967295 mmDIG4_AFMT_AVI_INFO1 0 0x4822 0 0 4294967295 mmDIG4_AFMT_AVI_INFO2 0 0x4823 0 0 4294967295 mmDIG4_AFMT_AVI_INFO3 0 0x4824 0 0 4294967295 mmDIG4_AFMT_GENERIC_0 0 0x4828 0 0 4294967295 mmDIG4_AFMT_GENERIC_1 0 0x4829 0 0 4294967295 mmDIG4_AFMT_GENERIC_2 0 0x482a 0 0 4294967295 mmDIG4_AFMT_GENERIC_3 0 0x482b 0 0 4294967295 mmDIG4_AFMT_GENERIC_4 0 0x482c 0 0 4294967295 mmDIG4_AFMT_GENERIC_5 0 0x482d 0 0 4294967295 mmDIG4_AFMT_GENERIC_6 0 0x482e 0 0 4294967295 mmDIG4_AFMT_GENERIC_7 0 0x482f 0 0 4294967295 mmDIG4_AFMT_GENERIC_HDR 0 0x4827 0 0 4294967295 mmDIG4_AFMT_INFOFRAME_CONTROL0 0 0x484d 0 0 4294967295 mmDIG4_AFMT_INTERRUPT_STATUS 0 0x4814 0 0 4294967295 mmDIG4_AFMT_ISRC1_0 0 0x4818 0 0 4294967295 mmDIG4_AFMT_ISRC1_1 0 0x4819 0 0 4294967295 mmDIG4_AFMT_ISRC1_2 0 0x481a 0 0 4294967295 mmDIG4_AFMT_ISRC1_3 0 0x481b 0 0 4294967295 mmDIG4_AFMT_ISRC1_4 0 0x481c 0 0 4294967295 mmDIG4_AFMT_ISRC2_0 0 0x481d 0 0 4294967295 mmDIG4_AFMT_ISRC2_1 0 0x481e 0 0 4294967295 mmDIG4_AFMT_ISRC2_2 0 0x481f 0 0 4294967295 mmDIG4_AFMT_ISRC2_3 0 0x4820 0 0 4294967295 mmDIG4_AFMT_MPEG_INFO0 0 0x4825 0 0 4294967295 mmDIG4_AFMT_MPEG_INFO1 0 0x4826 0 0 4294967295 mmDIG4_AFMT_RAMP_CONTROL0 0 0x4844 0 0 4294967295 mmDIG4_AFMT_RAMP_CONTROL1 0 0x4845 0 0 4294967295 mmDIG4_AFMT_RAMP_CONTROL2 0 0x4846 0 0 4294967295 mmDIG4_AFMT_RAMP_CONTROL3 0 0x4847 0 0 4294967295 mmDIG4_AFMT_STATUS 0 0x484a 0 0 4294967295 mmDIG4_AFMT_VBI_PACKET_CONTROL 0 0x484c 0 0 4294967295 mmDIG4_DIG_BE_CNTL 0 0x4850 0 0 4294967295 mmDIG4_DIG_BE_EN_CNTL 0 0x4851 0 0 4294967295 mmDIG4_DIG_CLOCK_PATTERN 0 0x4803 0 0 4294967295 mmDIG4_DIG_DISPCLK_SWITCH_CNTL 0 0x4808 0 0 4294967295 mmDIG4_DIG_DISPCLK_SWITCH_STATUS 0 0x4809 0 0 4294967295 mmDIG4_DIG_FE_CNTL 0 0x4800 0 0 4294967295 mmDIG4_DIG_FIFO_STATUS 0 0x480a 0 0 4294967295 mmDIG4_DIG_LANE_ENABLE 0 0x488d 0 0 4294967295 mmDIG4_DIG_OUTPUT_CRC_CNTL 0 0x4801 0 0 4294967295 mmDIG4_DIG_OUTPUT_CRC_RESULT 0 0x4802 0 0 4294967295 mmDIG4_DIG_RANDOM_PATTERN_SEED 0 0x4805 0 0 4294967295 mmDIG4_DIG_TEST_PATTERN 0 0x4804 0 0 4294967295 mmDIG4_HDMI_ACR_32_0 0 0x4837 0 0 4294967295 mmDIG4_HDMI_ACR_32_1 0 0x4838 0 0 4294967295 mmDIG4_HDMI_ACR_44_0 0 0x4839 0 0 4294967295 mmDIG4_HDMI_ACR_44_1 0 0x483a 0 0 4294967295 mmDIG4_HDMI_ACR_48_0 0 0x483b 0 0 4294967295 mmDIG4_HDMI_ACR_48_1 0 0x483c 0 0 4294967295 mmDIG4_HDMI_ACR_PACKET_CONTROL 0 0x480f 0 0 4294967295 mmDIG4_HDMI_ACR_STATUS_0 0 0x483d 0 0 4294967295 mmDIG4_HDMI_ACR_STATUS_1 0 0x483e 0 0 4294967295 mmDIG4_HDMI_AUDIO_PACKET_CONTROL 0 0x480e 0 0 4294967295 mmDIG4_HDMI_CONTROL 0 0x480c 0 0 4294967295 mmDIG4_HDMI_GC 0 0x4816 0 0 4294967295 mmDIG4_HDMI_GENERIC_PACKET_CONTROL0 0 0x4813 0 0 4294967295 mmDIG4_HDMI_GENERIC_PACKET_CONTROL1 0 0x4830 0 0 4294967295 mmDIG4_HDMI_INFOFRAME_CONTROL0 0 0x4811 0 0 4294967295 mmDIG4_HDMI_INFOFRAME_CONTROL1 0 0x4812 0 0 4294967295 mmDIG4_HDMI_STATUS 0 0x480d 0 0 4294967295 mmDIG4_HDMI_VBI_PACKET_CONTROL 0 0x4810 0 0 4294967295 mmDIG4_LVDS_DATA_CNTL 0 0x488c 0 0 4294967295 mmDIG4_TMDS_CNTL 0 0x487c 0 0 4294967295 mmDIG4_TMDS_CONTROL0_FEEDBACK 0 0x487e 0 0 4294967295 mmDIG4_TMDS_CONTROL_CHAR 0 0x487d 0 0 4294967295 mmDIG4_TMDS_CTL0_1_GEN_CNTL 0 0x4886 0 0 4294967295 mmDIG4_TMDS_CTL2_3_GEN_CNTL 0 0x4887 0 0 4294967295 mmDIG4_TMDS_CTL_BITS 0 0x4883 0 0 4294967295 mmDIG4_TMDS_DCBALANCER_CONTROL 0 0x4884 0 0 4294967295 mmDIG4_TMDS_DEBUG 0 0x4882 0 0 4294967295 mmDIG4_TMDS_STEREOSYNC_CTL_SEL 0 0x487f 0 0 4294967295 mmDIG4_TMDS_SYNC_CHAR_PATTERN_0_1 0 0x4880 0 0 4294967295 mmDIG4_TMDS_SYNC_CHAR_PATTERN_2_3 0 0x4881 0 0 4294967295 mmDIG5_AFMT_60958_0 0 0x4b41 0 0 4294967295 mmDIG5_AFMT_60958_1 0 0x4b42 0 0 4294967295 mmDIG5_AFMT_60958_2 0 0x4b48 0 0 4294967295 mmDIG5_AFMT_AUDIO_CRC_CONTROL 0 0x4b43 0 0 4294967295 mmDIG5_AFMT_AUDIO_CRC_RESULT 0 0x4b49 0 0 4294967295 mmDIG5_AFMT_AUDIO_DBG_DTO_CNTL 0 0x4b52 0 0 4294967295 mmDIG5_AFMT_AUDIO_INFO0 0 0x4b3f 0 0 4294967295 mmDIG5_AFMT_AUDIO_INFO1 0 0x4b40 0 0 4294967295 mmDIG5_AFMT_AUDIO_PACKET_CONTROL 0 0x4b4b 0 0 4294967295 mmDIG5_AFMT_AUDIO_PACKET_CONTROL2 0 0x4b17 0 0 4294967295 mmDIG5_AFMT_AUDIO_SRC_CONTROL 0 0x4b4f 0 0 4294967295 mmDIG5_AFMT_AVI_INFO0 0 0x4b21 0 0 4294967295 mmDIG5_AFMT_AVI_INFO1 0 0x4b22 0 0 4294967295 mmDIG5_AFMT_AVI_INFO2 0 0x4b23 0 0 4294967295 mmDIG5_AFMT_AVI_INFO3 0 0x4b24 0 0 4294967295 mmDIG5_AFMT_GENERIC_0 0 0x4b28 0 0 4294967295 mmDIG5_AFMT_GENERIC_1 0 0x4b29 0 0 4294967295 mmDIG5_AFMT_GENERIC_2 0 0x4b2a 0 0 4294967295 mmDIG5_AFMT_GENERIC_3 0 0x4b2b 0 0 4294967295 mmDIG5_AFMT_GENERIC_4 0 0x4b2c 0 0 4294967295 mmDIG5_AFMT_GENERIC_5 0 0x4b2d 0 0 4294967295 mmDIG5_AFMT_GENERIC_6 0 0x4b2e 0 0 4294967295 mmDIG5_AFMT_GENERIC_7 0 0x4b2f 0 0 4294967295 mmDIG5_AFMT_GENERIC_HDR 0 0x4b27 0 0 4294967295 mmDIG5_AFMT_INFOFRAME_CONTROL0 0 0x4b4d 0 0 4294967295 mmDIG5_AFMT_INTERRUPT_STATUS 0 0x4b14 0 0 4294967295 mmDIG5_AFMT_ISRC1_0 0 0x4b18 0 0 4294967295 mmDIG5_AFMT_ISRC1_1 0 0x4b19 0 0 4294967295 mmDIG5_AFMT_ISRC1_2 0 0x4b1a 0 0 4294967295 mmDIG5_AFMT_ISRC1_3 0 0x4b1b 0 0 4294967295 mmDIG5_AFMT_ISRC1_4 0 0x4b1c 0 0 4294967295 mmDIG5_AFMT_ISRC2_0 0 0x4b1d 0 0 4294967295 mmDIG5_AFMT_ISRC2_1 0 0x4b1e 0 0 4294967295 mmDIG5_AFMT_ISRC2_2 0 0x4b1f 0 0 4294967295 mmDIG5_AFMT_ISRC2_3 0 0x4b20 0 0 4294967295 mmDIG5_AFMT_MPEG_INFO0 0 0x4b25 0 0 4294967295 mmDIG5_AFMT_MPEG_INFO1 0 0x4b26 0 0 4294967295 mmDIG5_AFMT_RAMP_CONTROL0 0 0x4b44 0 0 4294967295 mmDIG5_AFMT_RAMP_CONTROL1 0 0x4b45 0 0 4294967295 mmDIG5_AFMT_RAMP_CONTROL2 0 0x4b46 0 0 4294967295 mmDIG5_AFMT_RAMP_CONTROL3 0 0x4b47 0 0 4294967295 mmDIG5_AFMT_STATUS 0 0x4b4a 0 0 4294967295 mmDIG5_AFMT_VBI_PACKET_CONTROL 0 0x4b4c 0 0 4294967295 mmDIG5_DIG_BE_CNTL 0 0x4b50 0 0 4294967295 mmDIG5_DIG_BE_EN_CNTL 0 0x4b51 0 0 4294967295 mmDIG5_DIG_CLOCK_PATTERN 0 0x4b03 0 0 4294967295 mmDIG5_DIG_DISPCLK_SWITCH_CNTL 0 0x4b08 0 0 4294967295 mmDIG5_DIG_DISPCLK_SWITCH_STATUS 0 0x4b09 0 0 4294967295 mmDIG5_DIG_FE_CNTL 0 0x4b00 0 0 4294967295 mmDIG5_DIG_FIFO_STATUS 0 0x4b0a 0 0 4294967295 mmDIG5_DIG_LANE_ENABLE 0 0x4b8d 0 0 4294967295 mmDIG5_DIG_OUTPUT_CRC_CNTL 0 0x4b01 0 0 4294967295 mmDIG5_DIG_OUTPUT_CRC_RESULT 0 0x4b02 0 0 4294967295 mmDIG5_DIG_RANDOM_PATTERN_SEED 0 0x4b05 0 0 4294967295 mmDIG5_DIG_TEST_PATTERN 0 0x4b04 0 0 4294967295 mmDIG5_HDMI_ACR_32_0 0 0x4b37 0 0 4294967295 mmDIG5_HDMI_ACR_32_1 0 0x4b38 0 0 4294967295 mmDIG5_HDMI_ACR_44_0 0 0x4b39 0 0 4294967295 mmDIG5_HDMI_ACR_44_1 0 0x4b3a 0 0 4294967295 mmDIG5_HDMI_ACR_48_0 0 0x4b3b 0 0 4294967295 mmDIG5_HDMI_ACR_48_1 0 0x4b3c 0 0 4294967295 mmDIG5_HDMI_ACR_PACKET_CONTROL 0 0x4b0f 0 0 4294967295 mmDIG5_HDMI_ACR_STATUS_0 0 0x4b3d 0 0 4294967295 mmDIG5_HDMI_ACR_STATUS_1 0 0x4b3e 0 0 4294967295 mmDIG5_HDMI_AUDIO_PACKET_CONTROL 0 0x4b0e 0 0 4294967295 mmDIG5_HDMI_CONTROL 0 0x4b0c 0 0 4294967295 mmDIG5_HDMI_GC 0 0x4b16 0 0 4294967295 mmDIG5_HDMI_GENERIC_PACKET_CONTROL0 0 0x4b13 0 0 4294967295 mmDIG5_HDMI_GENERIC_PACKET_CONTROL1 0 0x4b30 0 0 4294967295 mmDIG5_HDMI_INFOFRAME_CONTROL0 0 0x4b11 0 0 4294967295 mmDIG5_HDMI_INFOFRAME_CONTROL1 0 0x4b12 0 0 4294967295 mmDIG5_HDMI_STATUS 0 0x4b0d 0 0 4294967295 mmDIG5_HDMI_VBI_PACKET_CONTROL 0 0x4b10 0 0 4294967295 mmDIG5_LVDS_DATA_CNTL 0 0x4b8c 0 0 4294967295 mmDIG5_TMDS_CNTL 0 0x4b7c 0 0 4294967295 mmDIG5_TMDS_CONTROL0_FEEDBACK 0 0x4b7e 0 0 4294967295 mmDIG5_TMDS_CONTROL_CHAR 0 0x4b7d 0 0 4294967295 mmDIG5_TMDS_CTL0_1_GEN_CNTL 0 0x4b86 0 0 4294967295 mmDIG5_TMDS_CTL2_3_GEN_CNTL 0 0x4b87 0 0 4294967295 mmDIG5_TMDS_CTL_BITS 0 0x4b83 0 0 4294967295 mmDIG5_TMDS_DCBALANCER_CONTROL 0 0x4b84 0 0 4294967295 mmDIG5_TMDS_DEBUG 0 0x4b82 0 0 4294967295 mmDIG5_TMDS_STEREOSYNC_CTL_SEL 0 0x4b7f 0 0 4294967295 mmDIG5_TMDS_SYNC_CHAR_PATTERN_0_1 0 0x4b80 0 0 4294967295 mmDIG5_TMDS_SYNC_CHAR_PATTERN_2_3 0 0x4b81 0 0 4294967295 mmDIG_BE_CNTL 0 0x1c50 3 0 4294967295 DIG_FE_SOURCE_SELECT 8 13 DIG_HPD_SELECT 28 30 DIG_MODE 16 18 mmDIG_BE_EN_CNTL 0 0x1c51 2 0 4294967295 DIG_ENABLE 0 0 DIG_SYMCLK_BE_ON 8 8 mmDIG_CLOCK_PATTERN 0 0x1c03 1 0 4294967295 DIG_CLOCK_PATTERN 0 9 mmDIG_DISPCLK_SWITCH_CNTL 0 0x1c08 1 0 4294967295 DIG_DISPCLK_SWITCH_POINT 0 0 mmDIG_DISPCLK_SWITCH_STATUS 0 0x1c09 4 0 4294967295 DIG_DISPCLK_SWITCH_ALLOWED_INT_ACK 8 8 DIG_DISPCLK_SWITCH_ALLOWED_INT 4 4 DIG_DISPCLK_SWITCH_ALLOWED_INT_MASK 12 12 DIG_DISPCLK_SWITCH_ALLOWED 0 0 mmDIG_FE_CNTL 0 0x1c00 8 0 4294967295 DIG_DUAL_LINK_ENABLE 16 16 DIG_RB_SWITCH_EN 20 20 DIG_SOURCE_SELECT 0 2 DIG_START 10 10 DIG_STEREOSYNC_GATE_EN 8 8 DIG_STEREOSYNC_SELECT 4 6 DIG_SWAP 18 18 DIG_SYMCLK_FE_ON 24 24 mmDIG_FIFO_STATUS 0 0x1c0a 10 0 4294967295 DIG_FIFO_CAL_AVERAGE_LEVEL 10 15 DIG_FIFO_CALIBRATED 29 29 DIG_FIFO_ERROR_ACK 8 8 DIG_FIFO_FORCE_RECAL_AVERAGE 30 30 DIG_FIFO_FORCE_RECOMP_MINMAX 31 31 DIG_FIFO_LEVEL_ERROR 0 0 DIG_FIFO_MAXIMUM_LEVEL 16 20 DIG_FIFO_MINIMUM_LEVEL 22 25 DIG_FIFO_OVERWRITE_LEVEL 2 7 DIG_FIFO_USE_OVERWRITE_LEVEL 1 1 mmDIG_LANE_ENABLE 0 0x1c8d 5 0 4294967295 DIG_CLK_EN 8 8 DIG_LANE0EN 0 0 DIG_LANE1EN 1 1 DIG_LANE2EN 2 2 DIG_LANE3EN 3 3 mmDIG_OUTPUT_CRC_CNTL 0 0x1c01 3 0 4294967295 DIG_OUTPUT_CRC_DATA_SEL 8 9 DIG_OUTPUT_CRC_EN 0 0 DIG_OUTPUT_CRC_LINK_SEL 4 4 mmDIG_OUTPUT_CRC_RESULT 0 0x1c02 1 0 4294967295 DIG_OUTPUT_CRC_RESULT 0 29 mmDIG_RANDOM_PATTERN_SEED 0 0x1c05 2 0 4294967295 DIG_RANDOM_PATTERN_SEED 0 23 DIG_RAN_PAT_DURING_DE_ONLY 24 24 mmDIG_SOFT_RESET 0 0x13d 12 0 4294967295 DIGA_BE_SOFT_RESET 1 1 DIGA_FE_SOFT_RESET 0 0 DIGB_BE_SOFT_RESET 5 5 DIGB_FE_SOFT_RESET 4 4 DIGC_BE_SOFT_RESET 9 9 DIGC_FE_SOFT_RESET 8 8 DIGD_BE_SOFT_RESET 13 13 DIGD_FE_SOFT_RESET 12 12 DIGE_BE_SOFT_RESET 17 17 DIGE_FE_SOFT_RESET 16 16 DIGF_BE_SOFT_RESET 21 21 DIGF_FE_SOFT_RESET 20 20 mmDIG_TEST_PATTERN 0 0x1c04 8 0 4294967295 DIG_HALF_CLOCK_PATTERN_SEL 1 1 DIG_RANDOM_PATTERN_OUT_EN 4 4 DIG_RANDOM_PATTERN_RESET 5 5 DIG_STATIC_TEST_PATTERN 16 25 DIG_TEST_PATTERN_EXTERNAL_RESET_EN 6 6 DIG_TEST_PATTERN_OUT_EN 0 0 LVDS_EYE_PATTERN 8 8 LVDS_TEST_CLOCK_DATA 2 2 mmDISPCLK_CGTT_BLK_CTRL_REG 0 0x135 2 0 4294967295 DISPCLK_TURN_OFF_DELAY 4 11 DISPCLK_TURN_ON_DELAY 0 3 mmDISPCLK_FREQ_CHANGE_CNTL 0 0x131 8 0 4294967295 DCCG_FIFO_ERRDET_OVR_EN 30 30 DCCG_FIFO_ERRDET_RESET 28 28 DCCG_FIFO_ERRDET_STATE 29 29 DISPCLK_CHG_FWD_CORR_DISABLE 31 31 DISPCLK_FREQ_RAMP_DONE 20 20 DISPCLK_MAX_ERRDET_CYCLES 25 27 DISPCLK_STEP_DELAY 0 13 DISPCLK_STEP_SIZE 16 19 mmDISP_INTERRUPT_STATUS 0 0x183d 27 0 4294967295 ABM1_BL_UPDATE_INT 30 30 ABM1_HG_READY_INT 28 28 ABM1_LS_READY_INT 29 29 AUX1_LS_DONE_INTERRUPT 20 20 AUX1_SW_DONE_INTERRUPT 19 19 CRTC1_FORCE_COUNT_NOW_INTERRUPT 6 6 CRTC1_FORCE_VSYNC_NEXT_LINE_INTERRUPT 5 5 CRTC1_SET_V_TOTAL_MIN_EVENT_OCCURED_INT 10 10 CRTC1_SNAPSHOT_INTERRUPT 4 4 CRTC1_TRIGA_INTERRUPT 7 7 CRTC1_TRIGB_INTERRUPT 8 8 CRTC1_VSYNC_NOM_INTERRUPT 9 9 DACA_AUTODETECT_INTERRUPT 22 22 DACB_AUTODETECT_INTERRUPT 23 23 DC_HPD1_INTERRUPT 17 17 DC_HPD1_RX_INTERRUPT 18 18 DC_I2C_HW_DONE_INTERRUPT 25 25 DC_I2C_SW_DONE_INTERRUPT 24 24 DIGA_DISPCLK_SWITCH_ALLOWED_INTERRUPT 21 21 DIGA_DP_FAST_TRAINING_COMPLETE_INTERRUPT 15 15 DIGA_DP_VID_STREAM_DISABLE_INTERRUPT 16 16 DISP_INTERRUPT_STATUS_CONTINUE 31 31 DMCU_SCP_INT 27 27 DMCU_UC_INTERNAL_INT 26 26 LB_D1_VBLANK_INTERRUPT 3 3 LB_D1_VLINE_INTERRUPT 2 2 SCL_DISP1_MODE_CHANGE_INTERRUPT 0 0 mmDISP_INTERRUPT_STATUS_CONTINUE 0 0x183e 18 0 4294967295 AUX2_LS_DONE_INTERRUPT 20 20 AUX2_SW_DONE_INTERRUPT 19 19 CRTC2_FORCE_COUNT_NOW_INTERRUPT 6 6 CRTC2_FORCE_VSYNC_NEXT_LINE_INTERRUPT 5 5 CRTC2_SET_V_TOTAL_MIN_EVENT_OCCURED_INT 10 10 CRTC2_SNAPSHOT_INTERRUPT 4 4 CRTC2_TRIGA_INTERRUPT 7 7 CRTC2_TRIGB_INTERRUPT 8 8 CRTC2_VSYNC_NOM_INTERRUPT 9 9 DC_HPD2_INTERRUPT 17 17 DC_HPD2_RX_INTERRUPT 18 18 DIGB_DP_FAST_TRAINING_COMPLETE_INTERRUPT 15 15 DIGB_DP_VID_STREAM_DISABLE_INTERRUPT 16 16 DISP_INTERRUPT_STATUS_CONTINUE2 31 31 DISP_TIMER_INTERRUPT 24 24 LB_D2_VBLANK_INTERRUPT 3 3 LB_D2_VLINE_INTERRUPT 2 2 SCL_DISP2_MODE_CHANGE_INTERRUPT 0 0 mmDISP_INTERRUPT_STATUS_CONTINUE2 0 0x183f 17 0 4294967295 AUX3_LS_DONE_INTERRUPT 20 20 AUX3_SW_DONE_INTERRUPT 19 19 CRTC3_FORCE_COUNT_NOW_INTERRUPT 6 6 CRTC3_FORCE_VSYNC_NEXT_LINE_INTERRUPT 5 5 CRTC3_SET_V_TOTAL_MIN_EVENT_OCCURED_INT 10 10 CRTC3_SNAPSHOT_INTERRUPT 4 4 CRTC3_TRIGA_INTERRUPT 7 7 CRTC3_TRIGB_INTERRUPT 8 8 CRTC3_VSYNC_NOM_INTERRUPT 9 9 DC_HPD3_INTERRUPT 17 17 DC_HPD3_RX_INTERRUPT 18 18 DIGC_DP_FAST_TRAINING_COMPLETE_INTERRUPT 15 15 DIGC_DP_VID_STREAM_DISABLE_INTERRUPT 16 16 DISP_INTERRUPT_STATUS_CONTINUE3 31 31 LB_D3_VBLANK_INTERRUPT 3 3 LB_D3_VLINE_INTERRUPT 2 2 SCL_DISP3_MODE_CHANGE_INTERRUPT 0 0 mmDISP_INTERRUPT_STATUS_CONTINUE3 0 0x1840 17 0 4294967295 AUX4_LS_DONE_INTERRUPT 20 20 AUX4_SW_DONE_INTERRUPT 19 19 CRTC4_FORCE_COUNT_NOW_INTERRUPT 6 6 CRTC4_FORCE_VSYNC_NEXT_LINE_INTERRUPT 5 5 CRTC4_SET_V_TOTAL_MIN_EVENT_OCCURED_INT 10 10 CRTC4_SNAPSHOT_INTERRUPT 4 4 CRTC4_TRIGA_INTERRUPT 7 7 CRTC4_TRIGB_INTERRUPT 8 8 CRTC4_VSYNC_NOM_INTERRUPT 9 9 DC_HPD4_INTERRUPT 17 17 DC_HPD4_RX_INTERRUPT 18 18 DIGD_DP_FAST_TRAINING_COMPLETE_INTERRUPT 15 15 DIGD_DP_VID_STREAM_DISABLE_INTERRUPT 16 16 DISP_INTERRUPT_STATUS_CONTINUE4 31 31 LB_D4_VBLANK_INTERRUPT 3 3 LB_D4_VLINE_INTERRUPT 2 2 SCL_DISP4_MODE_CHANGE_INTERRUPT 0 0 mmDISP_INTERRUPT_STATUS_CONTINUE4 0 0x1853 17 0 4294967295 AUX5_LS_DONE_INTERRUPT 20 20 AUX5_SW_DONE_INTERRUPT 19 19 CRTC5_FORCE_COUNT_NOW_INTERRUPT 6 6 CRTC5_FORCE_VSYNC_NEXT_LINE_INTERRUPT 5 5 CRTC5_SET_V_TOTAL_MIN_EVENT_OCCURED_INT 10 10 CRTC5_SNAPSHOT_INTERRUPT 4 4 CRTC5_TRIGA_INTERRUPT 7 7 CRTC5_TRIGB_INTERRUPT 8 8 CRTC5_VSYNC_NOM_INTERRUPT 9 9 DC_HPD5_INTERRUPT 17 17 DC_HPD5_RX_INTERRUPT 18 18 DIGE_DP_FAST_TRAINING_COMPLETE_INTERRUPT 15 15 DIGE_DP_VID_STREAM_DISABLE_INTERRUPT 16 16 DISP_INTERRUPT_STATUS_CONTINUE5 31 31 LB_D5_VBLANK_INTERRUPT 3 3 LB_D5_VLINE_INTERRUPT 2 2 SCL_DISP5_MODE_CHANGE_INTERRUPT 0 0 mmDISP_INTERRUPT_STATUS_CONTINUE5 0 0x1854 16 0 4294967295 AUX6_LS_DONE_INTERRUPT 20 20 AUX6_SW_DONE_INTERRUPT 19 19 CRTC6_FORCE_COUNT_NOW_INTERRUPT 6 6 CRTC6_FORCE_VSYNC_NEXT_LINE_INTERRUPT 5 5 CRTC6_SET_V_TOTAL_MIN_EVENT_OCCURED_INT 10 10 CRTC6_SNAPSHOT_INTERRUPT 4 4 CRTC6_TRIGA_INTERRUPT 7 7 CRTC6_TRIGB_INTERRUPT 8 8 CRTC6_VSYNC_NOM_INTERRUPT 9 9 DC_HPD6_INTERRUPT 17 17 DC_HPD6_RX_INTERRUPT 18 18 DIGF_DP_FAST_TRAINING_COMPLETE_INTERRUPT 15 15 DIGF_DP_VID_STREAM_DISABLE_INTERRUPT 16 16 LB_D6_VBLANK_INTERRUPT 3 3 LB_D6_VLINE_INTERRUPT 2 2 SCL_DISP6_MODE_CHANGE_INTERRUPT 0 0 mmDISPOUT_STEREOSYNC_SEL 0 0x18bf 2 0 4294967295 GENERICA_STEREOSYNC_SEL 0 2 GENERICB_STEREOSYNC_SEL 16 18 mmDISPPLL_BG_CNTL 0 0x13c 2 0 4294967295 DISPPLL_BG_ADJ 4 7 DISPPLL_BG_PDN 0 0 mmDISP_TIMER_CONTROL 0 0x1842 7 0 4294967295 DISP_TIMER_INT_COUNT 0 24 DISP_TIMER_INT_ENABLE 25 25 DISP_TIMER_INT 30 30 DISP_TIMER_INT_MSK 27 27 DISP_TIMER_INT_RUNNING 26 26 DISP_TIMER_INT_STAT_AK 29 29 DISP_TIMER_INT_STAT 28 28 mmDMCU_CTRL 0 0x1600 6 0 4294967295 DISABLE_IRQ_TO_UC 2 2 DISABLE_XIRQ_TO_UC 3 3 DMCU_ENABLE 4 4 IGNORE_PWRMGT 1 1 RESET_UC 0 0 UC_REG_RD_TIMEOUT 22 31 mmDMCU_ERAM_RD_CTRL 0 0x160b 3 0 4294967295 ERAM_RD_ADDR 0 15 ERAM_RD_BE 16 19 ERAM_RD_BYTE_MODE 20 20 mmDMCU_ERAM_RD_DATA 0 0x160c 1 0 4294967295 ERAM_RD_DATA 0 31 mmDMCU_ERAM_WR_CTRL 0 0x1609 3 0 4294967295 ERAM_WR_ADDR 0 15 ERAM_WR_BE 16 19 ERAM_WR_BYTE_MODE 20 20 mmDMCU_ERAM_WR_DATA 0 0x160a 1 0 4294967295 ERAM_WR_DATA 0 31 mmDMCU_EVENT_TRIGGER 0 0x1611 3 0 4294967295 GEN_SW_INT_TO_UC 0 0 GEN_UC_INTERNAL_INT_TO_HOST 23 23 UC_INTERNAL_INT_CODE 16 22 mmDMCU_FW_CHECKSUM_SMPL_BYTE_POS 0 0x161a 2 0 4294967295 DMCU_FW_CHECKSUM_HI_SMPL_BYTE_POS 2 3 DMCU_FW_CHECKSUM_LO_SMPL_BYTE_POS 0 1 mmDMCU_FW_CS_HI 0 0x1606 1 0 4294967295 FW_CHECKSUM_HI 0 31 mmDMCU_FW_CS_LO 0 0x1607 1 0 4294967295 FW_CHECKSUM_LO 0 31 mmDMCU_FW_END_ADDR 0 0x1604 2 0 4294967295 FW_END_ADDR_LSB 0 7 FW_END_ADDR_MSB 8 15 mmDMCU_FW_ISR_START_ADDR 0 0x1605 2 0 4294967295 FW_ISR_START_ADDR_LSB 0 7 FW_ISR_START_ADDR_MSB 8 15 mmDMCU_FW_START_ADDR 0 0x1603 2 0 4294967295 FW_START_ADDR_LSB 0 7 FW_START_ADDR_MSB 8 15 mmDMCU_INT_CNT 0 0x1619 3 0 4294967295 DMCU_ABM1_BL_UPDATE_INT_CNT 16 23 DMCU_ABM1_HG_READY_INT_CNT 0 7 DMCU_ABM1_LS_READY_INT_CNT 8 15 mmDMCU_INTERRUPT_STATUS 0 0x1614 50 0 4294967295 ABM1_BL_UPDATE_INT_CLEAR 2 2 ABM1_BL_UPDATE_INT_OCCURRED 2 2 ABM1_HG_READY_INT_CLEAR 0 0 ABM1_HG_READY_INT_OCCURRED 0 0 ABM1_LS_READY_INT_CLEAR 1 1 ABM1_LS_READY_INT_OCCURRED 1 1 DCPG_IHC_DCFE0_POWER_DOWN_INT_CLEAR 18 18 DCPG_IHC_DCFE0_POWER_DOWN_INT_OCCURRED 18 18 DCPG_IHC_DCFE0_POWER_UP_INT_CLEAR 12 12 DCPG_IHC_DCFE0_POWER_UP_INT_OCCURRED 12 12 DCPG_IHC_DCFE1_POWER_DOWN_INT_CLEAR 19 19 DCPG_IHC_DCFE1_POWER_DOWN_INT_OCCURRED 19 19 DCPG_IHC_DCFE1_POWER_UP_INT_CLEAR 13 13 DCPG_IHC_DCFE1_POWER_UP_INT_OCCURRED 13 13 DCPG_IHC_DCFE2_POWER_DOWN_INT_CLEAR 20 20 DCPG_IHC_DCFE2_POWER_DOWN_INT_OCCURRED 20 20 DCPG_IHC_DCFE2_POWER_UP_INT_CLEAR 14 14 DCPG_IHC_DCFE2_POWER_UP_INT_OCCURRED 14 14 DCPG_IHC_DCFE3_POWER_DOWN_INT_CLEAR 21 21 DCPG_IHC_DCFE3_POWER_DOWN_INT_OCCURRED 21 21 DCPG_IHC_DCFE3_POWER_UP_INT_CLEAR 15 15 DCPG_IHC_DCFE3_POWER_UP_INT_OCCURRED 15 15 DCPG_IHC_DCFE4_POWER_DOWN_INT_CLEAR 22 22 DCPG_IHC_DCFE4_POWER_DOWN_INT_OCCURRED 22 22 DCPG_IHC_DCFE4_POWER_UP_INT_CLEAR 16 16 DCPG_IHC_DCFE4_POWER_UP_INT_OCCURRED 16 16 DCPG_IHC_DCFE5_POWER_DOWN_INT_CLEAR 23 23 DCPG_IHC_DCFE5_POWER_DOWN_INT_OCCURRED 23 23 DCPG_IHC_DCFE5_POWER_UP_INT_CLEAR 17 17 DCPG_IHC_DCFE5_POWER_UP_INT_OCCURRED 17 17 EXTERNAL_SW_INT_CLEAR 8 8 EXTERNAL_SW_INT_OCCURRED 8 8 MCP_INT_OCCURRED 3 3 SCP_INT_OCCURRED 9 9 UC_INTERNAL_INT_CLEAR 10 10 UC_INTERNAL_INT_OCCURRED 10 10 UC_REG_RD_TIMEOUT_INT_CLEAR 11 11 UC_REG_RD_TIMEOUT_INT_OCCURRED 11 11 VBLANK1_INT_CLEAR 24 24 VBLANK1_INT_OCCURRED 24 24 VBLANK2_INT_CLEAR 25 25 VBLANK2_INT_OCCURRED 25 25 VBLANK3_INT_CLEAR 26 26 VBLANK3_INT_OCCURRED 26 26 VBLANK4_INT_CLEAR 27 27 VBLANK4_INT_OCCURRED 27 27 VBLANK5_INT_CLEAR 28 28 VBLANK5_INT_OCCURRED 28 28 VBLANK6_INT_CLEAR 29 29 VBLANK6_INT_OCCURRED 29 29 mmDMCU_INTERRUPT_TO_HOST_EN_MASK 0 0x1615 18 0 4294967295 ABM1_BL_UPDATE_INT_MASK 2 2 ABM1_HG_READY_INT_MASK 0 0 ABM1_LS_READY_INT_MASK 1 1 DCPG_IHC_DCFE0_POWER_DOWN_INT_MASK 18 18 DCPG_IHC_DCFE0_POWER_UP_INT_MASK 12 12 DCPG_IHC_DCFE1_POWER_DOWN_INT_MASK 19 19 DCPG_IHC_DCFE1_POWER_UP_INT_MASK 13 13 DCPG_IHC_DCFE2_POWER_DOWN_INT_MASK 20 20 DCPG_IHC_DCFE2_POWER_UP_INT_MASK 14 14 DCPG_IHC_DCFE3_POWER_DOWN_INT_MASK 21 21 DCPG_IHC_DCFE3_POWER_UP_INT_MASK 15 15 DCPG_IHC_DCFE4_POWER_DOWN_INT_MASK 22 22 DCPG_IHC_DCFE4_POWER_UP_INT_MASK 16 16 DCPG_IHC_DCFE5_POWER_DOWN_INT_MASK 23 23 DCPG_IHC_DCFE5_POWER_UP_INT_MASK 17 17 SCP_INT_MASK 9 9 UC_INTERNAL_INT_MASK 10 10 UC_REG_RD_TIMEOUT_INT_MASK 11 11 mmDMCU_INTERRUPT_TO_UC_EN_MASK 0 0x1616 23 0 4294967295 ABM1_BL_UPDATE_INT_TO_UC_EN 2 2 ABM1_HG_READY_INT_TO_UC_EN 0 0 ABM1_LS_READY_INT_TO_UC_EN 1 1 DCPG_IHC_DCFE0_POWER_DOWN_INT_TO_UC_EN 18 18 DCPG_IHC_DCFE0_POWER_UP_INT_TO_UC_EN 12 12 DCPG_IHC_DCFE1_POWER_DOWN_INT_TO_UC_EN 19 19 DCPG_IHC_DCFE1_POWER_UP_INT_TO_UC_EN 13 13 DCPG_IHC_DCFE2_POWER_DOWN_INT_TO_UC_EN 20 20 DCPG_IHC_DCFE2_POWER_UP_INT_TO_UC_EN 14 14 DCPG_IHC_DCFE3_POWER_DOWN_INT_TO_UC_EN 21 21 DCPG_IHC_DCFE3_POWER_UP_INT_TO_UC_EN 15 15 DCPG_IHC_DCFE4_POWER_DOWN_INT_TO_UC_EN 22 22 DCPG_IHC_DCFE4_POWER_UP_INT_TO_UC_EN 16 16 DCPG_IHC_DCFE5_POWER_DOWN_INT_TO_UC_EN 23 23 DCPG_IHC_DCFE5_POWER_UP_INT_TO_UC_EN 17 17 EXTERNAL_SW_INT_TO_UC_EN 8 8 MCP_INT_TO_UC_EN 3 3 VBLANK1_INT_TO_UC_EN 24 24 VBLANK2_INT_TO_UC_EN 25 25 VBLANK3_INT_TO_UC_EN 26 26 VBLANK4_INT_TO_UC_EN 27 27 VBLANK5_INT_TO_UC_EN 28 28 VBLANK6_INT_TO_UC_EN 29 29 mmDMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL 0 0x1617 23 0 4294967295 ABM1_BL_UPDATE_INT_XIRQ_IRQ_SEL 2 2 ABM1_HG_READY_INT_XIRQ_IRQ_SEL 0 0 ABM1_LS_READY_INT_XIRQ_IRQ_SEL 1 1 DCPG_IHC_DCFE0_POWER_DOWN_INT_XIRQ_IRQ_SEL 18 18 DCPG_IHC_DCFE0_POWER_UP_INT_XIRQ_IRQ_SEL 12 12 DCPG_IHC_DCFE1_POWER_DOWN_INT_XIRQ_IRQ_SEL 19 19 DCPG_IHC_DCFE1_POWER_UP_INT_XIRQ_IRQ_SEL 13 13 DCPG_IHC_DCFE2_POWER_DOWN_INT_XIRQ_IRQ_SEL 20 20 DCPG_IHC_DCFE2_POWER_UP_INT_XIRQ_IRQ_SEL 14 14 DCPG_IHC_DCFE3_POWER_DOWN_INT_XIRQ_IRQ_SEL 21 21 DCPG_IHC_DCFE3_POWER_UP_INT_XIRQ_IRQ_SEL 15 15 DCPG_IHC_DCFE4_POWER_DOWN_INT_XIRQ_IRQ_SEL 22 22 DCPG_IHC_DCFE4_POWER_UP_INT_XIRQ_IRQ_SEL 16 16 DCPG_IHC_DCFE5_POWER_DOWN_INT_XIRQ_IRQ_SEL 23 23 DCPG_IHC_DCFE5_POWER_UP_INT_XIRQ_IRQ_SEL 17 17 EXTERNAL_SW_INT_XIRQ_IRQ_SEL 8 8 MCP_INT_XIRQ_IRQ_SEL 3 3 VBLANK1_INT_XIRQ_IRQ_SEL 24 24 VBLANK2_INT_XIRQ_IRQ_SEL 25 25 VBLANK3_INT_XIRQ_IRQ_SEL 26 26 VBLANK4_INT_XIRQ_IRQ_SEL 27 27 VBLANK5_INT_XIRQ_IRQ_SEL 28 28 VBLANK6_INT_XIRQ_IRQ_SEL 29 29 mmDMCU_IRAM_RD_CTRL 0 0x160f 1 0 4294967295 IRAM_RD_ADDR 0 9 mmDMCU_IRAM_RD_DATA 0 0x1610 1 0 4294967295 IRAM_RD_DATA 0 7 mmDMCU_IRAM_WR_CTRL 0 0x160d 1 0 4294967295 IRAM_WR_ADDR 0 9 mmDMCU_IRAM_WR_DATA 0 0x160e 1 0 4294967295 IRAM_WR_DATA 0 7 mmDMCU_PC_START_ADDR 0 0x1602 2 0 4294967295 PC_START_ADDR_LSB 0 7 PC_START_ADDR_MSB 8 15 mmDMCU_RAM_ACCESS_CTRL 0 0x1608 7 0 4294967295 ERAM_HOST_ACCESS_EN 4 4 ERAM_RD_ADDR_AUTO_INC 1 1 ERAM_WR_ADDR_AUTO_INC 0 0 IRAM_HOST_ACCESS_EN 5 5 IRAM_RD_ADDR_AUTO_INC 3 3 IRAM_WR_ADDR_AUTO_INC 2 2 UC_RST_RELEASE_DELAY_CNT 8 15 mmDMCU_STATUS 0 0x1601 3 0 4294967295 UC_IN_RESET 0 0 UC_IN_STOP_MODE 2 2 UC_IN_WAIT_MODE 1 1 mmDMCU_TEST_DEBUG_DATA 0 0x1627 1 0 4294967295 DMCU_TEST_DEBUG_DATA 0 31 mmDMCU_TEST_DEBUG_INDEX 0 0x1626 2 0 4294967295 DMCU_TEST_DEBUG_INDEX 0 7 DMCU_TEST_DEBUG_WRITE_EN 8 8 mmDMCU_UC_CLK_GATING_CNTL 0 0x161b 3 0 4294967295 UC_ERAM_RD_DELAY 8 10 UC_IRAM_RD_DELAY 0 2 UC_RBBM_RD_CLK_GATING_EN 16 16 mmDMCU_UC_INTERNAL_INT_STATUS 0 0x1612 16 0 4294967295 UC_INT_ILLEGAL_OPCODE_TRAP 3 3 UC_INT_IRQ_N_PIN 0 0 UC_INT_PULSE_ACCUMULATOR_INPUT_EDGE 14 14 UC_INT_PULSE_ACCUMULATOR_OVERFLOW 15 15 UC_INT_REAL_TIME_INTERRUPT 9 9 UC_INT_SOFTWARE_INTERRUPT 2 2 UC_INT_TIMER_INPUT_CAPTURE_1 13 13 UC_INT_TIMER_INPUT_CAPTURE_2 12 12 UC_INT_TIMER_INPUT_CAPTURE_3 11 11 UC_INT_TIMER_INPUT_CAPTURE_4_OUTPUT_COMPARE_5 10 10 UC_INT_TIMER_OUTPUT_COMPARE_1 7 7 UC_INT_TIMER_OUTPUT_COMPARE_2 6 6 UC_INT_TIMER_OUTPUT_COMPARE_3 5 5 UC_INT_TIMER_OUTPUT_COMPARE_4 4 4 UC_INT_TIMER_OVERFLOW 8 8 UC_INT_XIRQ_N_PIN 1 1 mmDMIF_ADDR_CALC 0 0x300 2 0 4294967295 ADDR_CONFIG_PIPE_INTERLEAVE_SIZE 4 6 ADDR_CONFIG_ROW_SIZE 28 29 mmDMIF_ADDR_CONFIG 0 0x2f5 7 0 4294967295 BANK_INTERLEAVE_SIZE 8 10 NUM_LOWER_PIPES 30 30 NUM_PIPES 0 2 NUM_SHADER_ENGINES 12 13 PIPE_INTERLEAVE_SIZE 4 6 ROW_SIZE 28 29 SHADER_ENGINE_TILE_SIZE 16 18 mmDMIF_ARBITRATION_CONTROL 0 0x2f9 2 0 4294967295 DMIF_ARBITRATION_REFERENCE_CLOCK_PERIOD 0 15 PIPE_SWITCH_EFFICIENCY_WEIGHT 16 31 mmDMIF_CONTROL 0 0x2f6 8 0 4294967295 DMIF_BUFF_SIZE 0 1 DMIF_CHUNK_BUFF_MARGIN 29 30 DMIF_DELAY_ARBITRATION 24 28 DMIF_DISABLE_EARLY_RECEIVED_LEVEL_COUNT 4 4 DMIF_FORCE_TOTAL_REQ_BURST_SIZE 12 15 DMIF_GROUP_REQUESTS_IN_CHUNK 2 2 DMIF_MAX_TOTAL_OUTSTANDING_CHUNK_REQUESTS 16 21 DMIF_REQ_BURST_SIZE 8 10 mmDMIF_HW_DEBUG 0 0x2f8 1 0 4294967295 DMIF_HW_DEBUG 0 31 mmDMIF_PG0_DPG_PIPE_ARBITRATION_CONTROL1 0 0x1b30 0 0 4294967295 mmDMIF_PG0_DPG_PIPE_ARBITRATION_CONTROL2 0 0x1b31 0 0 4294967295 mmDMIF_PG0_DPG_PIPE_DPM_CONTROL 0 0x1b34 0 0 4294967295 mmDMIF_PG0_DPG_PIPE_NB_PSTATE_CHANGE_CONTROL 0 0x1b36 0 0 4294967295 mmDMIF_PG0_DPG_PIPE_STUTTER_CONTROL 0 0x1b35 0 0 4294967295 mmDMIF_PG0_DPG_PIPE_STUTTER_CONTROL_NONLPTCH 0 0x1b37 0 0 4294967295 mmDMIF_PG0_DPG_PIPE_URGENCY_CONTROL 0 0x1b33 0 0 4294967295 mmDMIF_PG0_DPG_TEST_DEBUG_DATA 0 0x1b39 0 0 4294967295 mmDMIF_PG0_DPG_TEST_DEBUG_INDEX 0 0x1b38 0 0 4294967295 mmDMIF_PG1_DPG_PIPE_ARBITRATION_CONTROL1 0 0x1e30 0 0 4294967295 mmDMIF_PG1_DPG_PIPE_ARBITRATION_CONTROL2 0 0x1e31 0 0 4294967295 mmDMIF_PG1_DPG_PIPE_DPM_CONTROL 0 0x1e34 0 0 4294967295 mmDMIF_PG1_DPG_PIPE_NB_PSTATE_CHANGE_CONTROL 0 0x1e36 0 0 4294967295 mmDMIF_PG1_DPG_PIPE_STUTTER_CONTROL 0 0x1e35 0 0 4294967295 mmDMIF_PG1_DPG_PIPE_STUTTER_CONTROL_NONLPTCH 0 0x1e37 0 0 4294967295 mmDMIF_PG1_DPG_PIPE_URGENCY_CONTROL 0 0x1e33 0 0 4294967295 mmDMIF_PG1_DPG_TEST_DEBUG_DATA 0 0x1e39 0 0 4294967295 mmDMIF_PG1_DPG_TEST_DEBUG_INDEX 0 0x1e38 0 0 4294967295 mmDMIF_PG2_DPG_PIPE_ARBITRATION_CONTROL1 0 0x4130 0 0 4294967295 mmDMIF_PG2_DPG_PIPE_ARBITRATION_CONTROL2 0 0x4131 0 0 4294967295 mmDMIF_PG2_DPG_PIPE_DPM_CONTROL 0 0x4134 0 0 4294967295 mmDMIF_PG2_DPG_PIPE_NB_PSTATE_CHANGE_CONTROL 0 0x4136 0 0 4294967295 mmDMIF_PG2_DPG_PIPE_STUTTER_CONTROL 0 0x4135 0 0 4294967295 mmDMIF_PG2_DPG_PIPE_STUTTER_CONTROL_NONLPTCH 0 0x4137 0 0 4294967295 mmDMIF_PG2_DPG_PIPE_URGENCY_CONTROL 0 0x4133 0 0 4294967295 mmDMIF_PG2_DPG_TEST_DEBUG_DATA 0 0x4139 0 0 4294967295 mmDMIF_PG2_DPG_TEST_DEBUG_INDEX 0 0x4138 0 0 4294967295 mmDMIF_PG3_DPG_PIPE_ARBITRATION_CONTROL1 0 0x4430 0 0 4294967295 mmDMIF_PG3_DPG_PIPE_ARBITRATION_CONTROL2 0 0x4431 0 0 4294967295 mmDMIF_PG3_DPG_PIPE_DPM_CONTROL 0 0x4434 0 0 4294967295 mmDMIF_PG3_DPG_PIPE_NB_PSTATE_CHANGE_CONTROL 0 0x4436 0 0 4294967295 mmDMIF_PG3_DPG_PIPE_STUTTER_CONTROL 0 0x4435 0 0 4294967295 mmDMIF_PG3_DPG_PIPE_STUTTER_CONTROL_NONLPTCH 0 0x4437 0 0 4294967295 mmDMIF_PG3_DPG_PIPE_URGENCY_CONTROL 0 0x4433 0 0 4294967295 mmDMIF_PG3_DPG_TEST_DEBUG_DATA 0 0x4439 0 0 4294967295 mmDMIF_PG3_DPG_TEST_DEBUG_INDEX 0 0x4438 0 0 4294967295 mmDMIF_PG4_DPG_PIPE_ARBITRATION_CONTROL1 0 0x4730 0 0 4294967295 mmDMIF_PG4_DPG_PIPE_ARBITRATION_CONTROL2 0 0x4731 0 0 4294967295 mmDMIF_PG4_DPG_PIPE_DPM_CONTROL 0 0x4734 0 0 4294967295 mmDMIF_PG4_DPG_PIPE_NB_PSTATE_CHANGE_CONTROL 0 0x4736 0 0 4294967295 mmDMIF_PG4_DPG_PIPE_STUTTER_CONTROL 0 0x4735 0 0 4294967295 mmDMIF_PG4_DPG_PIPE_STUTTER_CONTROL_NONLPTCH 0 0x4737 0 0 4294967295 mmDMIF_PG4_DPG_PIPE_URGENCY_CONTROL 0 0x4733 0 0 4294967295 mmDMIF_PG4_DPG_TEST_DEBUG_DATA 0 0x4739 0 0 4294967295 mmDMIF_PG4_DPG_TEST_DEBUG_INDEX 0 0x4738 0 0 4294967295 mmDMIF_PG5_DPG_PIPE_ARBITRATION_CONTROL1 0 0x4a30 0 0 4294967295 mmDMIF_PG5_DPG_PIPE_ARBITRATION_CONTROL2 0 0x4a31 0 0 4294967295 mmDMIF_PG5_DPG_PIPE_DPM_CONTROL 0 0x4a34 0 0 4294967295 mmDMIF_PG5_DPG_PIPE_NB_PSTATE_CHANGE_CONTROL 0 0x4a36 0 0 4294967295 mmDMIF_PG5_DPG_PIPE_STUTTER_CONTROL 0 0x4a35 0 0 4294967295 mmDMIF_PG5_DPG_PIPE_STUTTER_CONTROL_NONLPTCH 0 0x4a37 0 0 4294967295 mmDMIF_PG5_DPG_PIPE_URGENCY_CONTROL 0 0x4a33 0 0 4294967295 mmDMIF_PG5_DPG_TEST_DEBUG_DATA 0 0x4a39 0 0 4294967295 mmDMIF_PG5_DPG_TEST_DEBUG_INDEX 0 0x4a38 0 0 4294967295 mmDMIF_STATUS 0 0x2f7 7 0 4294967295 DMIF_CLEAR_MC_SEND_ON_IDLE 8 13 DMIF_MC_LATENCY_COUNTER_ENABLE 16 16 DMIF_MC_LATENCY_COUNTER_SOURCE_SELECT 20 22 DMIF_MC_LATENCY_COUNTER_URGENT_ONLY 17 17 DMIF_MC_SEND_ON_IDLE 0 5 DMIF_PERFORMANCE_COUNTER_SOURCE_SELECT 24 26 DMIF_UNDERFLOW 28 28 mmDMIF_STATUS2 0 0x301 8 0 4294967295 DMIF_CHUNK_TRACKER_SCLK_STATUS 8 8 DMIF_FBC_TRACKER_SCLK_STATUS 9 9 DMIF_PIPE0_DISPCLK_STATUS 0 0 DMIF_PIPE1_DISPCLK_STATUS 1 1 DMIF_PIPE2_DISPCLK_STATUS 2 2 DMIF_PIPE3_DISPCLK_STATUS 3 3 DMIF_PIPE4_DISPCLK_STATUS 4 4 DMIF_PIPE5_DISPCLK_STATUS 5 5 mmDMIF_TEST_DEBUG_DATA 0 0x313 1 0 4294967295 DMIF_TEST_DEBUG_DATA 0 31 mmDMIF_TEST_DEBUG_INDEX 0 0x312 2 0 4294967295 DMIF_TEST_DEBUG_INDEX 0 7 DMIF_TEST_DEBUG_WRITE_EN 8 8 mmDOUT_DCE_VCE_CONTROL 0 0x18ff 2 0 4294967295 DC_VCE_AUDIO_STREAM_SELECT 4 6 DC_VCE_VIDEO_PIPE_SELECT 0 2 mmDOUT_POWER_MANAGEMENT_CNTL 0 0x1841 2 0 4294967295 PM_ALL_BUSY_OFF 8 8 PM_ASSERT_RESET 0 0 mmDOUT_SCRATCH0 0 0x1844 1 0 4294967295 DOUT_SCRATCH0 0 31 mmDOUT_SCRATCH1 0 0x1845 1 0 4294967295 DOUT_SCRATCH1 0 31 mmDOUT_SCRATCH2 0 0x1846 1 0 4294967295 DOUT_SCRATCH2 0 31 mmDOUT_SCRATCH3 0 0x1847 1 0 4294967295 DOUT_SCRATCH3 0 31 mmDOUT_SCRATCH4 0 0x1848 1 0 4294967295 DOUT_SCRATCH4 0 31 mmDOUT_SCRATCH5 0 0x1849 1 0 4294967295 DOUT_SCRATCH5 0 31 mmDOUT_SCRATCH6 0 0x184a 1 0 4294967295 DOUT_SCRATCH6 0 31 mmDOUT_SCRATCH7 0 0x184b 1 0 4294967295 DOUT_SCRATCH7 0 31 mmDOUT_TEST_DEBUG_DATA 0 0x184e 1 0 4294967295 DOUT_TEST_DEBUG_DATA 0 31 mmDOUT_TEST_DEBUG_INDEX 0 0x184d 2 0 4294967295 DOUT_TEST_DEBUG_INDEX 0 7 DOUT_TEST_DEBUG_WRITE_EN 8 8 mmDP0_DP_CONFIG 0 0x1cc2 0 0 4294967295 mmDP0_DP_DPHY_8B10B_CNTL 0 0x1cd3 0 0 4294967295 mmDP0_DP_DPHY_CNTL 0 0x1cd0 0 0 4294967295 mmDP0_DP_DPHY_CRC_CNTL 0 0x1cd7 0 0 4294967295 mmDP0_DP_DPHY_CRC_EN 0 0x1cd6 0 0 4294967295 mmDP0_DP_DPHY_CRC_MST_CNTL 0 0x1cc6 0 0 4294967295 mmDP0_DP_DPHY_CRC_MST_STATUS 0 0x1cc7 0 0 4294967295 mmDP0_DP_DPHY_CRC_RESULT 0 0x1cd8 0 0 4294967295 mmDP0_DP_DPHY_FAST_TRAINING 0 0x1cce 0 0 4294967295 mmDP0_DP_DPHY_FAST_TRAINING_STATUS 0 0x1ce9 0 0 4294967295 mmDP0_DP_DPHY_PRBS_CNTL 0 0x1cd4 0 0 4294967295 mmDP0_DP_DPHY_SYM0 0 0x1cd2 0 0 4294967295 mmDP0_DP_DPHY_SYM1 0 0x1ce0 0 0 4294967295 mmDP0_DP_DPHY_SYM2 0 0x1cdf 0 0 4294967295 mmDP0_DP_DPHY_TRAINING_PATTERN_SEL 0 0x1cd1 0 0 4294967295 mmDP0_DP_HBR2_EYE_PATTERN 0 0x1cc8 0 0 4294967295 mmDP0_DP_LINK_CNTL 0 0x1cc0 0 0 4294967295 mmDP0_DP_LINK_FRAMING_CNTL 0 0x1ccc 0 0 4294967295 mmDP0_DP_MSA_COLORIMETRY 0 0x1cda 0 0 4294967295 mmDP0_DP_MSA_MISC 0 0x1cc5 0 0 4294967295 mmDP0_DP_MSA_V_TIMING_OVERRIDE1 0 0x1cea 0 0 4294967295 mmDP0_DP_MSA_V_TIMING_OVERRIDE2 0 0x1ceb 0 0 4294967295 mmDP0_DP_MSE_LINK_TIMING 0 0x1ce8 0 0 4294967295 mmDP0_DP_MSE_MISC_CNTL 0 0x1cdb 0 0 4294967295 mmDP0_DP_MSE_RATE_CNTL 0 0x1ce1 0 0 4294967295 mmDP0_DP_MSE_RATE_UPDATE 0 0x1ce3 0 0 4294967295 mmDP0_DP_MSE_SAT0 0 0x1ce4 0 0 4294967295 mmDP0_DP_MSE_SAT1 0 0x1ce5 0 0 4294967295 mmDP0_DP_MSE_SAT2 0 0x1ce6 0 0 4294967295 mmDP0_DP_MSE_SAT_UPDATE 0 0x1ce7 0 0 4294967295 mmDP0_DP_PIXEL_FORMAT 0 0x1cc1 0 0 4294967295 mmDP0_DP_SEC_AUD_M 0 0x1ca7 0 0 4294967295 mmDP0_DP_SEC_AUD_M_READBACK 0 0x1ca8 0 0 4294967295 mmDP0_DP_SEC_AUD_N 0 0x1ca5 0 0 4294967295 mmDP0_DP_SEC_AUD_N_READBACK 0 0x1ca6 0 0 4294967295 mmDP0_DP_SEC_CNTL 0 0x1ca0 0 0 4294967295 mmDP0_DP_SEC_CNTL1 0 0x1cab 0 0 4294967295 mmDP0_DP_SEC_FRAMING1 0 0x1ca1 0 0 4294967295 mmDP0_DP_SEC_FRAMING2 0 0x1ca2 0 0 4294967295 mmDP0_DP_SEC_FRAMING3 0 0x1ca3 0 0 4294967295 mmDP0_DP_SEC_FRAMING4 0 0x1ca4 0 0 4294967295 mmDP0_DP_SEC_PACKET_CNTL 0 0x1caa 0 0 4294967295 mmDP0_DP_SEC_TIMESTAMP 0 0x1ca9 0 0 4294967295 mmDP0_DP_STEER_FIFO 0 0x1cc4 0 0 4294967295 mmDP0_DP_TEST_DEBUG_DATA 0 0x1cfd 0 0 4294967295 mmDP0_DP_TEST_DEBUG_INDEX 0 0x1cfc 0 0 4294967295 mmDP0_DP_VID_INTERRUPT_CNTL 0 0x1ccf 0 0 4294967295 mmDP0_DP_VID_M 0 0x1ccb 0 0 4294967295 mmDP0_DP_VID_MSA_VBID 0 0x1ccd 0 0 4294967295 mmDP0_DP_VID_N 0 0x1cca 0 0 4294967295 mmDP0_DP_VID_STREAM_CNTL 0 0x1cc3 0 0 4294967295 mmDP0_DP_VID_TIMING 0 0x1cc9 0 0 4294967295 mmDP1_DP_CONFIG 0 0x1fc2 0 0 4294967295 mmDP1_DP_DPHY_8B10B_CNTL 0 0x1fd3 0 0 4294967295 mmDP1_DP_DPHY_CNTL 0 0x1fd0 0 0 4294967295 mmDP1_DP_DPHY_CRC_CNTL 0 0x1fd7 0 0 4294967295 mmDP1_DP_DPHY_CRC_EN 0 0x1fd6 0 0 4294967295 mmDP1_DP_DPHY_CRC_MST_CNTL 0 0x1fc6 0 0 4294967295 mmDP1_DP_DPHY_CRC_MST_STATUS 0 0x1fc7 0 0 4294967295 mmDP1_DP_DPHY_CRC_RESULT 0 0x1fd8 0 0 4294967295 mmDP1_DP_DPHY_FAST_TRAINING 0 0x1fce 0 0 4294967295 mmDP1_DP_DPHY_FAST_TRAINING_STATUS 0 0x1fe9 0 0 4294967295 mmDP1_DP_DPHY_PRBS_CNTL 0 0x1fd4 0 0 4294967295 mmDP1_DP_DPHY_SYM0 0 0x1fd2 0 0 4294967295 mmDP1_DP_DPHY_SYM1 0 0x1fe0 0 0 4294967295 mmDP1_DP_DPHY_SYM2 0 0x1fdf 0 0 4294967295 mmDP1_DP_DPHY_TRAINING_PATTERN_SEL 0 0x1fd1 0 0 4294967295 mmDP1_DP_HBR2_EYE_PATTERN 0 0x1fc8 0 0 4294967295 mmDP1_DP_LINK_CNTL 0 0x1fc0 0 0 4294967295 mmDP1_DP_LINK_FRAMING_CNTL 0 0x1fcc 0 0 4294967295 mmDP1_DP_MSA_COLORIMETRY 0 0x1fda 0 0 4294967295 mmDP1_DP_MSA_MISC 0 0x1fc5 0 0 4294967295 mmDP1_DP_MSA_V_TIMING_OVERRIDE1 0 0x1fea 0 0 4294967295 mmDP1_DP_MSA_V_TIMING_OVERRIDE2 0 0x1feb 0 0 4294967295 mmDP1_DP_MSE_LINK_TIMING 0 0x1fe8 0 0 4294967295 mmDP1_DP_MSE_MISC_CNTL 0 0x1fdb 0 0 4294967295 mmDP1_DP_MSE_RATE_CNTL 0 0x1fe1 0 0 4294967295 mmDP1_DP_MSE_RATE_UPDATE 0 0x1fe3 0 0 4294967295 mmDP1_DP_MSE_SAT0 0 0x1fe4 0 0 4294967295 mmDP1_DP_MSE_SAT1 0 0x1fe5 0 0 4294967295 mmDP1_DP_MSE_SAT2 0 0x1fe6 0 0 4294967295 mmDP1_DP_MSE_SAT_UPDATE 0 0x1fe7 0 0 4294967295 mmDP1_DP_PIXEL_FORMAT 0 0x1fc1 0 0 4294967295 mmDP1_DP_SEC_AUD_M 0 0x1fa7 0 0 4294967295 mmDP1_DP_SEC_AUD_M_READBACK 0 0x1fa8 0 0 4294967295 mmDP1_DP_SEC_AUD_N 0 0x1fa5 0 0 4294967295 mmDP1_DP_SEC_AUD_N_READBACK 0 0x1fa6 0 0 4294967295 mmDP1_DP_SEC_CNTL 0 0x1fa0 0 0 4294967295 mmDP1_DP_SEC_CNTL1 0 0x1fab 0 0 4294967295 mmDP1_DP_SEC_FRAMING1 0 0x1fa1 0 0 4294967295 mmDP1_DP_SEC_FRAMING2 0 0x1fa2 0 0 4294967295 mmDP1_DP_SEC_FRAMING3 0 0x1fa3 0 0 4294967295 mmDP1_DP_SEC_FRAMING4 0 0x1fa4 0 0 4294967295 mmDP1_DP_SEC_PACKET_CNTL 0 0x1faa 0 0 4294967295 mmDP1_DP_SEC_TIMESTAMP 0 0x1fa9 0 0 4294967295 mmDP1_DP_STEER_FIFO 0 0x1fc4 0 0 4294967295 mmDP1_DP_TEST_DEBUG_DATA 0 0x1ffd 0 0 4294967295 mmDP1_DP_TEST_DEBUG_INDEX 0 0x1ffc 0 0 4294967295 mmDP1_DP_VID_INTERRUPT_CNTL 0 0x1fcf 0 0 4294967295 mmDP1_DP_VID_M 0 0x1fcb 0 0 4294967295 mmDP1_DP_VID_MSA_VBID 0 0x1fcd 0 0 4294967295 mmDP1_DP_VID_N 0 0x1fca 0 0 4294967295 mmDP1_DP_VID_STREAM_CNTL 0 0x1fc3 0 0 4294967295 mmDP1_DP_VID_TIMING 0 0x1fc9 0 0 4294967295 mmDP2_DP_CONFIG 0 0x42c2 0 0 4294967295 mmDP2_DP_DPHY_8B10B_CNTL 0 0x42d3 0 0 4294967295 mmDP2_DP_DPHY_CNTL 0 0x42d0 0 0 4294967295 mmDP2_DP_DPHY_CRC_CNTL 0 0x42d7 0 0 4294967295 mmDP2_DP_DPHY_CRC_EN 0 0x42d6 0 0 4294967295 mmDP2_DP_DPHY_CRC_MST_CNTL 0 0x42c6 0 0 4294967295 mmDP2_DP_DPHY_CRC_MST_STATUS 0 0x42c7 0 0 4294967295 mmDP2_DP_DPHY_CRC_RESULT 0 0x42d8 0 0 4294967295 mmDP2_DP_DPHY_FAST_TRAINING 0 0x42ce 0 0 4294967295 mmDP2_DP_DPHY_FAST_TRAINING_STATUS 0 0x42e9 0 0 4294967295 mmDP2_DP_DPHY_PRBS_CNTL 0 0x42d4 0 0 4294967295 mmDP2_DP_DPHY_SYM0 0 0x42d2 0 0 4294967295 mmDP2_DP_DPHY_SYM1 0 0x42e0 0 0 4294967295 mmDP2_DP_DPHY_SYM2 0 0x42df 0 0 4294967295 mmDP2_DP_DPHY_TRAINING_PATTERN_SEL 0 0x42d1 0 0 4294967295 mmDP2_DP_HBR2_EYE_PATTERN 0 0x42c8 0 0 4294967295 mmDP2_DP_LINK_CNTL 0 0x42c0 0 0 4294967295 mmDP2_DP_LINK_FRAMING_CNTL 0 0x42cc 0 0 4294967295 mmDP2_DP_MSA_COLORIMETRY 0 0x42da 0 0 4294967295 mmDP2_DP_MSA_MISC 0 0x42c5 0 0 4294967295 mmDP2_DP_MSA_V_TIMING_OVERRIDE1 0 0x42ea 0 0 4294967295 mmDP2_DP_MSA_V_TIMING_OVERRIDE2 0 0x42eb 0 0 4294967295 mmDP2_DP_MSE_LINK_TIMING 0 0x42e8 0 0 4294967295 mmDP2_DP_MSE_MISC_CNTL 0 0x42db 0 0 4294967295 mmDP2_DP_MSE_RATE_CNTL 0 0x42e1 0 0 4294967295 mmDP2_DP_MSE_RATE_UPDATE 0 0x42e3 0 0 4294967295 mmDP2_DP_MSE_SAT0 0 0x42e4 0 0 4294967295 mmDP2_DP_MSE_SAT1 0 0x42e5 0 0 4294967295 mmDP2_DP_MSE_SAT2 0 0x42e6 0 0 4294967295 mmDP2_DP_MSE_SAT_UPDATE 0 0x42e7 0 0 4294967295 mmDP2_DP_PIXEL_FORMAT 0 0x42c1 0 0 4294967295 mmDP2_DP_SEC_AUD_M 0 0x42a7 0 0 4294967295 mmDP2_DP_SEC_AUD_M_READBACK 0 0x42a8 0 0 4294967295 mmDP2_DP_SEC_AUD_N 0 0x42a5 0 0 4294967295 mmDP2_DP_SEC_AUD_N_READBACK 0 0x42a6 0 0 4294967295 mmDP2_DP_SEC_CNTL 0 0x42a0 0 0 4294967295 mmDP2_DP_SEC_CNTL1 0 0x42ab 0 0 4294967295 mmDP2_DP_SEC_FRAMING1 0 0x42a1 0 0 4294967295 mmDP2_DP_SEC_FRAMING2 0 0x42a2 0 0 4294967295 mmDP2_DP_SEC_FRAMING3 0 0x42a3 0 0 4294967295 mmDP2_DP_SEC_FRAMING4 0 0x42a4 0 0 4294967295 mmDP2_DP_SEC_PACKET_CNTL 0 0x42aa 0 0 4294967295 mmDP2_DP_SEC_TIMESTAMP 0 0x42a9 0 0 4294967295 mmDP2_DP_STEER_FIFO 0 0x42c4 0 0 4294967295 mmDP2_DP_TEST_DEBUG_DATA 0 0x42fd 0 0 4294967295 mmDP2_DP_TEST_DEBUG_INDEX 0 0x42fc 0 0 4294967295 mmDP2_DP_VID_INTERRUPT_CNTL 0 0x42cf 0 0 4294967295 mmDP2_DP_VID_M 0 0x42cb 0 0 4294967295 mmDP2_DP_VID_MSA_VBID 0 0x42cd 0 0 4294967295 mmDP2_DP_VID_N 0 0x42ca 0 0 4294967295 mmDP2_DP_VID_STREAM_CNTL 0 0x42c3 0 0 4294967295 mmDP2_DP_VID_TIMING 0 0x42c9 0 0 4294967295 mmDP3_DP_CONFIG 0 0x45c2 0 0 4294967295 mmDP3_DP_DPHY_8B10B_CNTL 0 0x45d3 0 0 4294967295 mmDP3_DP_DPHY_CNTL 0 0x45d0 0 0 4294967295 mmDP3_DP_DPHY_CRC_CNTL 0 0x45d7 0 0 4294967295 mmDP3_DP_DPHY_CRC_EN 0 0x45d6 0 0 4294967295 mmDP3_DP_DPHY_CRC_MST_CNTL 0 0x45c6 0 0 4294967295 mmDP3_DP_DPHY_CRC_MST_STATUS 0 0x45c7 0 0 4294967295 mmDP3_DP_DPHY_CRC_RESULT 0 0x45d8 0 0 4294967295 mmDP3_DP_DPHY_FAST_TRAINING 0 0x45ce 0 0 4294967295 mmDP3_DP_DPHY_FAST_TRAINING_STATUS 0 0x45e9 0 0 4294967295 mmDP3_DP_DPHY_PRBS_CNTL 0 0x45d4 0 0 4294967295 mmDP3_DP_DPHY_SYM0 0 0x45d2 0 0 4294967295 mmDP3_DP_DPHY_SYM1 0 0x45e0 0 0 4294967295 mmDP3_DP_DPHY_SYM2 0 0x45df 0 0 4294967295 mmDP3_DP_DPHY_TRAINING_PATTERN_SEL 0 0x45d1 0 0 4294967295 mmDP3_DP_HBR2_EYE_PATTERN 0 0x45c8 0 0 4294967295 mmDP3_DP_LINK_CNTL 0 0x45c0 0 0 4294967295 mmDP3_DP_LINK_FRAMING_CNTL 0 0x45cc 0 0 4294967295 mmDP3_DP_MSA_COLORIMETRY 0 0x45da 0 0 4294967295 mmDP3_DP_MSA_MISC 0 0x45c5 0 0 4294967295 mmDP3_DP_MSA_V_TIMING_OVERRIDE1 0 0x45ea 0 0 4294967295 mmDP3_DP_MSA_V_TIMING_OVERRIDE2 0 0x45eb 0 0 4294967295 mmDP3_DP_MSE_LINK_TIMING 0 0x45e8 0 0 4294967295 mmDP3_DP_MSE_MISC_CNTL 0 0x45db 0 0 4294967295 mmDP3_DP_MSE_RATE_CNTL 0 0x45e1 0 0 4294967295 mmDP3_DP_MSE_RATE_UPDATE 0 0x45e3 0 0 4294967295 mmDP3_DP_MSE_SAT0 0 0x45e4 0 0 4294967295 mmDP3_DP_MSE_SAT1 0 0x45e5 0 0 4294967295 mmDP3_DP_MSE_SAT2 0 0x45e6 0 0 4294967295 mmDP3_DP_MSE_SAT_UPDATE 0 0x45e7 0 0 4294967295 mmDP3_DP_PIXEL_FORMAT 0 0x45c1 0 0 4294967295 mmDP3_DP_SEC_AUD_M 0 0x45a7 0 0 4294967295 mmDP3_DP_SEC_AUD_M_READBACK 0 0x45a8 0 0 4294967295 mmDP3_DP_SEC_AUD_N 0 0x45a5 0 0 4294967295 mmDP3_DP_SEC_AUD_N_READBACK 0 0x45a6 0 0 4294967295 mmDP3_DP_SEC_CNTL 0 0x45a0 0 0 4294967295 mmDP3_DP_SEC_CNTL1 0 0x45ab 0 0 4294967295 mmDP3_DP_SEC_FRAMING1 0 0x45a1 0 0 4294967295 mmDP3_DP_SEC_FRAMING2 0 0x45a2 0 0 4294967295 mmDP3_DP_SEC_FRAMING3 0 0x45a3 0 0 4294967295 mmDP3_DP_SEC_FRAMING4 0 0x45a4 0 0 4294967295 mmDP3_DP_SEC_PACKET_CNTL 0 0x45aa 0 0 4294967295 mmDP3_DP_SEC_TIMESTAMP 0 0x45a9 0 0 4294967295 mmDP3_DP_STEER_FIFO 0 0x45c4 0 0 4294967295 mmDP3_DP_TEST_DEBUG_DATA 0 0x45fd 0 0 4294967295 mmDP3_DP_TEST_DEBUG_INDEX 0 0x45fc 0 0 4294967295 mmDP3_DP_VID_INTERRUPT_CNTL 0 0x45cf 0 0 4294967295 mmDP3_DP_VID_M 0 0x45cb 0 0 4294967295 mmDP3_DP_VID_MSA_VBID 0 0x45cd 0 0 4294967295 mmDP3_DP_VID_N 0 0x45ca 0 0 4294967295 mmDP3_DP_VID_STREAM_CNTL 0 0x45c3 0 0 4294967295 mmDP3_DP_VID_TIMING 0 0x45c9 0 0 4294967295 mmDP4_DP_CONFIG 0 0x48c2 0 0 4294967295 mmDP4_DP_DPHY_8B10B_CNTL 0 0x48d3 0 0 4294967295 mmDP4_DP_DPHY_CNTL 0 0x48d0 0 0 4294967295 mmDP4_DP_DPHY_CRC_CNTL 0 0x48d7 0 0 4294967295 mmDP4_DP_DPHY_CRC_EN 0 0x48d6 0 0 4294967295 mmDP4_DP_DPHY_CRC_MST_CNTL 0 0x48c6 0 0 4294967295 mmDP4_DP_DPHY_CRC_MST_STATUS 0 0x48c7 0 0 4294967295 mmDP4_DP_DPHY_CRC_RESULT 0 0x48d8 0 0 4294967295 mmDP4_DP_DPHY_FAST_TRAINING 0 0x48ce 0 0 4294967295 mmDP4_DP_DPHY_FAST_TRAINING_STATUS 0 0x48e9 0 0 4294967295 mmDP4_DP_DPHY_PRBS_CNTL 0 0x48d4 0 0 4294967295 mmDP4_DP_DPHY_SYM0 0 0x48d2 0 0 4294967295 mmDP4_DP_DPHY_SYM1 0 0x48e0 0 0 4294967295 mmDP4_DP_DPHY_SYM2 0 0x48df 0 0 4294967295 mmDP4_DP_DPHY_TRAINING_PATTERN_SEL 0 0x48d1 0 0 4294967295 mmDP4_DP_HBR2_EYE_PATTERN 0 0x48c8 0 0 4294967295 mmDP4_DP_LINK_CNTL 0 0x48c0 0 0 4294967295 mmDP4_DP_LINK_FRAMING_CNTL 0 0x48cc 0 0 4294967295 mmDP4_DP_MSA_COLORIMETRY 0 0x48da 0 0 4294967295 mmDP4_DP_MSA_MISC 0 0x48c5 0 0 4294967295 mmDP4_DP_MSA_V_TIMING_OVERRIDE1 0 0x48ea 0 0 4294967295 mmDP4_DP_MSA_V_TIMING_OVERRIDE2 0 0x48eb 0 0 4294967295 mmDP4_DP_MSE_LINK_TIMING 0 0x48e8 0 0 4294967295 mmDP4_DP_MSE_MISC_CNTL 0 0x48db 0 0 4294967295 mmDP4_DP_MSE_RATE_CNTL 0 0x48e1 0 0 4294967295 mmDP4_DP_MSE_RATE_UPDATE 0 0x48e3 0 0 4294967295 mmDP4_DP_MSE_SAT0 0 0x48e4 0 0 4294967295 mmDP4_DP_MSE_SAT1 0 0x48e5 0 0 4294967295 mmDP4_DP_MSE_SAT2 0 0x48e6 0 0 4294967295 mmDP4_DP_MSE_SAT_UPDATE 0 0x48e7 0 0 4294967295 mmDP4_DP_PIXEL_FORMAT 0 0x48c1 0 0 4294967295 mmDP4_DP_SEC_AUD_M 0 0x48a7 0 0 4294967295 mmDP4_DP_SEC_AUD_M_READBACK 0 0x48a8 0 0 4294967295 mmDP4_DP_SEC_AUD_N 0 0x48a5 0 0 4294967295 mmDP4_DP_SEC_AUD_N_READBACK 0 0x48a6 0 0 4294967295 mmDP4_DP_SEC_CNTL 0 0x48a0 0 0 4294967295 mmDP4_DP_SEC_CNTL1 0 0x48ab 0 0 4294967295 mmDP4_DP_SEC_FRAMING1 0 0x48a1 0 0 4294967295 mmDP4_DP_SEC_FRAMING2 0 0x48a2 0 0 4294967295 mmDP4_DP_SEC_FRAMING3 0 0x48a3 0 0 4294967295 mmDP4_DP_SEC_FRAMING4 0 0x48a4 0 0 4294967295 mmDP4_DP_SEC_PACKET_CNTL 0 0x48aa 0 0 4294967295 mmDP4_DP_SEC_TIMESTAMP 0 0x48a9 0 0 4294967295 mmDP4_DP_STEER_FIFO 0 0x48c4 0 0 4294967295 mmDP4_DP_TEST_DEBUG_DATA 0 0x48fd 0 0 4294967295 mmDP4_DP_TEST_DEBUG_INDEX 0 0x48fc 0 0 4294967295 mmDP4_DP_VID_INTERRUPT_CNTL 0 0x48cf 0 0 4294967295 mmDP4_DP_VID_M 0 0x48cb 0 0 4294967295 mmDP4_DP_VID_MSA_VBID 0 0x48cd 0 0 4294967295 mmDP4_DP_VID_N 0 0x48ca 0 0 4294967295 mmDP4_DP_VID_STREAM_CNTL 0 0x48c3 0 0 4294967295 mmDP4_DP_VID_TIMING 0 0x48c9 0 0 4294967295 mmDP5_DP_CONFIG 0 0x4bc2 0 0 4294967295 mmDP5_DP_DPHY_8B10B_CNTL 0 0x4bd3 0 0 4294967295 mmDP5_DP_DPHY_CNTL 0 0x4bd0 0 0 4294967295 mmDP5_DP_DPHY_CRC_CNTL 0 0x4bd7 0 0 4294967295 mmDP5_DP_DPHY_CRC_EN 0 0x4bd6 0 0 4294967295 mmDP5_DP_DPHY_CRC_MST_CNTL 0 0x4bc6 0 0 4294967295 mmDP5_DP_DPHY_CRC_MST_STATUS 0 0x4bc7 0 0 4294967295 mmDP5_DP_DPHY_CRC_RESULT 0 0x4bd8 0 0 4294967295 mmDP5_DP_DPHY_FAST_TRAINING 0 0x4bce 0 0 4294967295 mmDP5_DP_DPHY_FAST_TRAINING_STATUS 0 0x4be9 0 0 4294967295 mmDP5_DP_DPHY_PRBS_CNTL 0 0x4bd4 0 0 4294967295 mmDP5_DP_DPHY_SYM0 0 0x4bd2 0 0 4294967295 mmDP5_DP_DPHY_SYM1 0 0x4be0 0 0 4294967295 mmDP5_DP_DPHY_SYM2 0 0x4bdf 0 0 4294967295 mmDP5_DP_DPHY_TRAINING_PATTERN_SEL 0 0x4bd1 0 0 4294967295 mmDP5_DP_HBR2_EYE_PATTERN 0 0x4bc8 0 0 4294967295 mmDP5_DP_LINK_CNTL 0 0x4bc0 0 0 4294967295 mmDP5_DP_LINK_FRAMING_CNTL 0 0x4bcc 0 0 4294967295 mmDP5_DP_MSA_COLORIMETRY 0 0x4bda 0 0 4294967295 mmDP5_DP_MSA_MISC 0 0x4bc5 0 0 4294967295 mmDP5_DP_MSA_V_TIMING_OVERRIDE1 0 0x4bea 0 0 4294967295 mmDP5_DP_MSA_V_TIMING_OVERRIDE2 0 0x4beb 0 0 4294967295 mmDP5_DP_MSE_LINK_TIMING 0 0x4be8 0 0 4294967295 mmDP5_DP_MSE_MISC_CNTL 0 0x4bdb 0 0 4294967295 mmDP5_DP_MSE_RATE_CNTL 0 0x4be1 0 0 4294967295 mmDP5_DP_MSE_RATE_UPDATE 0 0x4be3 0 0 4294967295 mmDP5_DP_MSE_SAT0 0 0x4be4 0 0 4294967295 mmDP5_DP_MSE_SAT1 0 0x4be5 0 0 4294967295 mmDP5_DP_MSE_SAT2 0 0x4be6 0 0 4294967295 mmDP5_DP_MSE_SAT_UPDATE 0 0x4be7 0 0 4294967295 mmDP5_DP_PIXEL_FORMAT 0 0x4bc1 0 0 4294967295 mmDP5_DP_SEC_AUD_M 0 0x4ba7 0 0 4294967295 mmDP5_DP_SEC_AUD_M_READBACK 0 0x4ba8 0 0 4294967295 mmDP5_DP_SEC_AUD_N 0 0x4ba5 0 0 4294967295 mmDP5_DP_SEC_AUD_N_READBACK 0 0x4ba6 0 0 4294967295 mmDP5_DP_SEC_CNTL 0 0x4ba0 0 0 4294967295 mmDP5_DP_SEC_CNTL1 0 0x4bab 0 0 4294967295 mmDP5_DP_SEC_FRAMING1 0 0x4ba1 0 0 4294967295 mmDP5_DP_SEC_FRAMING2 0 0x4ba2 0 0 4294967295 mmDP5_DP_SEC_FRAMING3 0 0x4ba3 0 0 4294967295 mmDP5_DP_SEC_FRAMING4 0 0x4ba4 0 0 4294967295 mmDP5_DP_SEC_PACKET_CNTL 0 0x4baa 0 0 4294967295 mmDP5_DP_SEC_TIMESTAMP 0 0x4ba9 0 0 4294967295 mmDP5_DP_STEER_FIFO 0 0x4bc4 0 0 4294967295 mmDP5_DP_TEST_DEBUG_DATA 0 0x4bfd 0 0 4294967295 mmDP5_DP_TEST_DEBUG_INDEX 0 0x4bfc 0 0 4294967295 mmDP5_DP_VID_INTERRUPT_CNTL 0 0x4bcf 0 0 4294967295 mmDP5_DP_VID_M 0 0x4bcb 0 0 4294967295 mmDP5_DP_VID_MSA_VBID 0 0x4bcd 0 0 4294967295 mmDP5_DP_VID_N 0 0x4bca 0 0 4294967295 mmDP5_DP_VID_STREAM_CNTL 0 0x4bc3 0 0 4294967295 mmDP5_DP_VID_TIMING 0 0x4bc9 0 0 4294967295 mmDP_AUX0_AUX_ARB_CONTROL 0 0x1882 0 0 4294967295 mmDP_AUX0_AUX_CONTROL 0 0x1880 0 0 4294967295 mmDP_AUX0_AUX_DPHY_RX_CONTROL0 0 0x188a 0 0 4294967295 mmDP_AUX0_AUX_DPHY_RX_CONTROL1 0 0x188b 0 0 4294967295 mmDP_AUX0_AUX_DPHY_RX_STATUS 0 0x188d 0 0 4294967295 mmDP_AUX0_AUX_DPHY_TX_CONTROL 0 0x1889 0 0 4294967295 mmDP_AUX0_AUX_DPHY_TX_REF_CONTROL 0 0x1888 0 0 4294967295 mmDP_AUX0_AUX_DPHY_TX_STATUS 0 0x188c 0 0 4294967295 mmDP_AUX0_AUX_GTC_SYNC_CONTROL 0 0x188e 0 0 4294967295 mmDP_AUX0_AUX_GTC_SYNC_DATA 0 0x1890 0 0 4294967295 mmDP_AUX0_AUX_INTERRUPT_CONTROL 0 0x1883 0 0 4294967295 mmDP_AUX0_AUX_LS_DATA 0 0x1887 0 0 4294967295 mmDP_AUX0_AUX_LS_STATUS 0 0x1885 0 0 4294967295 mmDP_AUX0_AUX_SW_CONTROL 0 0x1881 0 0 4294967295 mmDP_AUX0_AUX_SW_DATA 0 0x1886 0 0 4294967295 mmDP_AUX0_AUX_SW_STATUS 0 0x1884 0 0 4294967295 mmDP_AUX1_AUX_ARB_CONTROL 0 0x1896 0 0 4294967295 mmDP_AUX1_AUX_CONTROL 0 0x1894 0 0 4294967295 mmDP_AUX1_AUX_DPHY_RX_CONTROL0 0 0x189e 0 0 4294967295 mmDP_AUX1_AUX_DPHY_RX_CONTROL1 0 0x189f 0 0 4294967295 mmDP_AUX1_AUX_DPHY_RX_STATUS 0 0x18a1 0 0 4294967295 mmDP_AUX1_AUX_DPHY_TX_CONTROL 0 0x189d 0 0 4294967295 mmDP_AUX1_AUX_DPHY_TX_REF_CONTROL 0 0x189c 0 0 4294967295 mmDP_AUX1_AUX_DPHY_TX_STATUS 0 0x18a0 0 0 4294967295 mmDP_AUX1_AUX_GTC_SYNC_CONTROL 0 0x18a2 0 0 4294967295 mmDP_AUX1_AUX_GTC_SYNC_DATA 0 0x18a4 0 0 4294967295 mmDP_AUX1_AUX_INTERRUPT_CONTROL 0 0x1897 0 0 4294967295 mmDP_AUX1_AUX_LS_DATA 0 0x189b 0 0 4294967295 mmDP_AUX1_AUX_LS_STATUS 0 0x1899 0 0 4294967295 mmDP_AUX1_AUX_SW_CONTROL 0 0x1895 0 0 4294967295 mmDP_AUX1_AUX_SW_DATA 0 0x189a 0 0 4294967295 mmDP_AUX1_AUX_SW_STATUS 0 0x1898 0 0 4294967295 mmDP_AUX2_AUX_ARB_CONTROL 0 0x18aa 0 0 4294967295 mmDP_AUX2_AUX_CONTROL 0 0x18a8 0 0 4294967295 mmDP_AUX2_AUX_DPHY_RX_CONTROL0 0 0x18b2 0 0 4294967295 mmDP_AUX2_AUX_DPHY_RX_CONTROL1 0 0x18b3 0 0 4294967295 mmDP_AUX2_AUX_DPHY_RX_STATUS 0 0x18b5 0 0 4294967295 mmDP_AUX2_AUX_DPHY_TX_CONTROL 0 0x18b1 0 0 4294967295 mmDP_AUX2_AUX_DPHY_TX_REF_CONTROL 0 0x18b0 0 0 4294967295 mmDP_AUX2_AUX_DPHY_TX_STATUS 0 0x18b4 0 0 4294967295 mmDP_AUX2_AUX_GTC_SYNC_CONTROL 0 0x18b6 0 0 4294967295 mmDP_AUX2_AUX_GTC_SYNC_DATA 0 0x18b8 0 0 4294967295 mmDP_AUX2_AUX_INTERRUPT_CONTROL 0 0x18ab 0 0 4294967295 mmDP_AUX2_AUX_LS_DATA 0 0x18af 0 0 4294967295 mmDP_AUX2_AUX_LS_STATUS 0 0x18ad 0 0 4294967295 mmDP_AUX2_AUX_SW_CONTROL 0 0x18a9 0 0 4294967295 mmDP_AUX2_AUX_SW_DATA 0 0x18ae 0 0 4294967295 mmDP_AUX2_AUX_SW_STATUS 0 0x18ac 0 0 4294967295 mmDP_AUX3_AUX_ARB_CONTROL 0 0x18c2 0 0 4294967295 mmDP_AUX3_AUX_CONTROL 0 0x18c0 0 0 4294967295 mmDP_AUX3_AUX_DPHY_RX_CONTROL0 0 0x18ca 0 0 4294967295 mmDP_AUX3_AUX_DPHY_RX_CONTROL1 0 0x18cb 0 0 4294967295 mmDP_AUX3_AUX_DPHY_RX_STATUS 0 0x18cd 0 0 4294967295 mmDP_AUX3_AUX_DPHY_TX_CONTROL 0 0x18c9 0 0 4294967295 mmDP_AUX3_AUX_DPHY_TX_REF_CONTROL 0 0x18c8 0 0 4294967295 mmDP_AUX3_AUX_DPHY_TX_STATUS 0 0x18cc 0 0 4294967295 mmDP_AUX3_AUX_GTC_SYNC_CONTROL 0 0x18ce 0 0 4294967295 mmDP_AUX3_AUX_GTC_SYNC_DATA 0 0x18d0 0 0 4294967295 mmDP_AUX3_AUX_INTERRUPT_CONTROL 0 0x18c3 0 0 4294967295 mmDP_AUX3_AUX_LS_DATA 0 0x18c7 0 0 4294967295 mmDP_AUX3_AUX_LS_STATUS 0 0x18c5 0 0 4294967295 mmDP_AUX3_AUX_SW_CONTROL 0 0x18c1 0 0 4294967295 mmDP_AUX3_AUX_SW_DATA 0 0x18c6 0 0 4294967295 mmDP_AUX3_AUX_SW_STATUS 0 0x18c4 0 0 4294967295 mmDP_AUX4_AUX_ARB_CONTROL 0 0x18d6 0 0 4294967295 mmDP_AUX4_AUX_CONTROL 0 0x18d4 0 0 4294967295 mmDP_AUX4_AUX_DPHY_RX_CONTROL0 0 0x18de 0 0 4294967295 mmDP_AUX4_AUX_DPHY_RX_CONTROL1 0 0x18df 0 0 4294967295 mmDP_AUX4_AUX_DPHY_RX_STATUS 0 0x18e1 0 0 4294967295 mmDP_AUX4_AUX_DPHY_TX_CONTROL 0 0x18dd 0 0 4294967295 mmDP_AUX4_AUX_DPHY_TX_REF_CONTROL 0 0x18dc 0 0 4294967295 mmDP_AUX4_AUX_DPHY_TX_STATUS 0 0x18e0 0 0 4294967295 mmDP_AUX4_AUX_GTC_SYNC_CONTROL 0 0x18e2 0 0 4294967295 mmDP_AUX4_AUX_GTC_SYNC_DATA 0 0x18e4 0 0 4294967295 mmDP_AUX4_AUX_INTERRUPT_CONTROL 0 0x18d7 0 0 4294967295 mmDP_AUX4_AUX_LS_DATA 0 0x18db 0 0 4294967295 mmDP_AUX4_AUX_LS_STATUS 0 0x18d9 0 0 4294967295 mmDP_AUX4_AUX_SW_CONTROL 0 0x18d5 0 0 4294967295 mmDP_AUX4_AUX_SW_DATA 0 0x18da 0 0 4294967295 mmDP_AUX4_AUX_SW_STATUS 0 0x18d8 0 0 4294967295 mmDP_AUX5_AUX_ARB_CONTROL 0 0x18ea 0 0 4294967295 mmDP_AUX5_AUX_CONTROL 0 0x18e8 0 0 4294967295 mmDP_AUX5_AUX_DPHY_RX_CONTROL0 0 0x18f2 0 0 4294967295 mmDP_AUX5_AUX_DPHY_RX_CONTROL1 0 0x18f3 0 0 4294967295 mmDP_AUX5_AUX_DPHY_RX_STATUS 0 0x18f5 0 0 4294967295 mmDP_AUX5_AUX_DPHY_TX_CONTROL 0 0x18f1 0 0 4294967295 mmDP_AUX5_AUX_DPHY_TX_REF_CONTROL 0 0x18f0 0 0 4294967295 mmDP_AUX5_AUX_DPHY_TX_STATUS 0 0x18f4 0 0 4294967295 mmDP_AUX5_AUX_GTC_SYNC_CONTROL 0 0x18f6 0 0 4294967295 mmDP_AUX5_AUX_GTC_SYNC_DATA 0 0x18f8 0 0 4294967295 mmDP_AUX5_AUX_INTERRUPT_CONTROL 0 0x18eb 0 0 4294967295 mmDP_AUX5_AUX_LS_DATA 0 0x18ef 0 0 4294967295 mmDP_AUX5_AUX_LS_STATUS 0 0x18ed 0 0 4294967295 mmDP_AUX5_AUX_SW_CONTROL 0 0x18e9 0 0 4294967295 mmDP_AUX5_AUX_SW_DATA 0 0x18ee 0 0 4294967295 mmDP_AUX5_AUX_SW_STATUS 0 0x18ec 0 0 4294967295 mmDP_CONFIG 0 0x1cc2 1 0 4294967295 DP_UDI_LANES 0 1 mmDP_DPHY_8B10B_CNTL 0 0x1cd3 3 0 4294967295 DPHY_8B10B_CUR_DISP 24 24 DPHY_8B10B_EXT_DISP 16 16 DPHY_8B10B_RESET 8 8 mmDP_DPHY_CNTL 0 0x1cd0 6 0 4294967295 DPHY_ATEST_SEL_LANE0 0 0 DPHY_ATEST_SEL_LANE1 1 1 DPHY_ATEST_SEL_LANE2 2 2 DPHY_ATEST_SEL_LANE3 3 3 DPHY_BYPASS 16 16 DPHY_SKEW_BYPASS 24 24 mmDP_DPHY_CRC_CNTL 0 0x1cd7 3 0 4294967295 DPHY_CRC_FIELD 0 0 DPHY_CRC_MASK 16 23 DPHY_CRC_SEL 4 5 mmDP_DPHY_CRC_EN 0 0x1cd6 3 0 4294967295 DPHY_CRC_CONT_EN 4 4 DPHY_CRC_EN 0 0 DPHY_CRC_RESULT_VALID 8 8 mmDP_DPHY_CRC_MST_CNTL 0 0x1cc6 2 0 4294967295 DPHY_CRC_MST_FIRST_SLOT 0 5 DPHY_CRC_MST_LAST_SLOT 8 13 mmDP_DPHY_CRC_MST_STATUS 0 0x1cc7 3 0 4294967295 DPHY_CRC_MST_PHASE_ERROR_ACK 16 16 DPHY_CRC_MST_PHASE_ERROR 8 8 DPHY_CRC_MST_PHASE_LOCK 0 0 mmDP_DPHY_CRC_RESULT 0 0x1cd8 4 0 4294967295 DPHY_CRC_RESULT1 8 15 DPHY_CRC_RESULT2 16 23 DPHY_CRC_RESULT3 24 31 DPHY_CRC_RESULT 0 7 mmDP_DPHY_FAST_TRAINING 0 0x1cce 5 0 4294967295 DPHY_FAST_TRAINING_TP1_TIME 8 19 DPHY_FAST_TRAINING_TP2_TIME 20 31 DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN 2 2 DPHY_RX_FAST_TRAINING_CAPABLE 0 0 DPHY_SW_FAST_TRAINING_START 1 1 mmDP_DPHY_FAST_TRAINING_STATUS 0 0x1ce9 4 0 4294967295 DPHY_FAST_TRAINING_COMPLETE_ACK 12 12 DPHY_FAST_TRAINING_COMPLETE_MASK 8 8 DPHY_FAST_TRAINING_COMPLETE_OCCURRED 4 4 DPHY_FAST_TRAINING_STATE 0 2 mmDP_DPHY_PRBS_CNTL 0 0x1cd4 3 0 4294967295 DPHY_PRBS_EN 0 0 DPHY_PRBS_SEED 8 30 DPHY_PRBS_SEL 4 5 mmDP_DPHY_SYM0 0 0x1cd2 3 0 4294967295 DPHY_SYM1 0 9 DPHY_SYM2 10 19 DPHY_SYM3 20 29 mmDP_DPHY_SYM1 0 0x1ce0 3 0 4294967295 DPHY_SYM4 0 9 DPHY_SYM5 10 19 DPHY_SYM6 20 29 mmDP_DPHY_SYM2 0 0x1cdf 2 0 4294967295 DPHY_SYM7 0 9 DPHY_SYM8 10 19 mmDP_DPHY_TRAINING_PATTERN_SEL 0 0x1cd1 1 0 4294967295 DPHY_TRAINING_PATTERN_SEL 0 1 mmDP_DTO0_MODULO 0 0x142 1 0 4294967295 DP_DTO0_MODULO 0 31 mmDP_DTO0_PHASE 0 0x141 1 0 4294967295 DP_DTO0_PHASE 0 31 mmDP_DTO1_MODULO 0 0x146 1 0 4294967295 DP_DTO1_MODULO 0 31 mmDP_DTO1_PHASE 0 0x145 1 0 4294967295 DP_DTO1_PHASE 0 31 mmDP_DTO2_MODULO 0 0x14a 1 0 4294967295 DP_DTO2_MODULO 0 31 mmDP_DTO2_PHASE 0 0x149 1 0 4294967295 DP_DTO2_PHASE 0 31 mmDP_DTO3_MODULO 0 0x14e 1 0 4294967295 DP_DTO3_MODULO 0 31 mmDP_DTO3_PHASE 0 0x14d 1 0 4294967295 DP_DTO3_PHASE 0 31 mmDP_DTO4_MODULO 0 0x152 1 0 4294967295 DP_DTO4_MODULO 0 31 mmDP_DTO4_PHASE 0 0x151 1 0 4294967295 DP_DTO4_PHASE 0 31 mmDP_DTO5_MODULO 0 0x156 1 0 4294967295 DP_DTO5_MODULO 0 31 mmDP_DTO5_PHASE 0 0x155 1 0 4294967295 DP_DTO5_PHASE 0 31 mmDPG_PIPE_ARBITRATION_CONTROL1 0 0x1b30 2 0 4294967295 BASE_WEIGHT 16 31 PIXEL_DURATION 0 15 mmDPG_PIPE_ARBITRATION_CONTROL2 0 0x1b31 2 0 4294967295 TIME_WEIGHT 0 15 URGENCY_WEIGHT 16 31 mmDPG_PIPE_DPM_CONTROL 0 0x1b34 5 0 4294967295 DPM_ENABLE 0 0 MCLK_CHANGE_ENABLE 4 4 MCLK_CHANGE_FORCE_ON 8 8 MCLK_CHANGE_WATERMARK 16 31 MCLK_CHANGE_WATERMARK_MASK 12 13 mmDPG_PIPE_NB_PSTATE_CHANGE_CONTROL 0 0x1b36 7 0 4294967295 NB_PSTATE_ALLOW_FOR_URGENT 10 10 NB_PSTATE_CHANGE_ENABLE 0 0 NB_PSTATE_CHANGE_FORCE_ON 9 9 NB_PSTATE_CHANGE_NOT_SELF_REFRESH_DURING_REQUEST 8 8 NB_PSTATE_CHANGE_URGENT_DURING_REQUEST 4 4 NB_PSTATE_CHANGE_WATERMARK_MASK 12 13 NB_PSTATE_CHANGE_WATERMARK 16 31 mmDPG_PIPE_STUTTER_CONTROL 0 0x1b35 11 0 4294967295 STUTTER_ENABLE 0 0 STUTTER_EXIT_SELF_REFRESH_WATERMARK_MASK 12 13 STUTTER_EXIT_SELF_REFRESH_WATERMARK 16 31 STUTTER_IGNORE_CURSOR 4 4 STUTTER_IGNORE_FBC 7 7 STUTTER_IGNORE_ICON 5 5 STUTTER_IGNORE_VGA 6 6 STUTTER_SELF_REFRESH_FORCE_ON 11 11 STUTTER_URGENT_IN_NOT_SELF_REFRESH 10 10 STUTTER_WM_HIGH_EXCLUDES_VBLANK 9 9 STUTTER_WM_HIGH_FORCE_ON 8 8 mmDPG_PIPE_STUTTER_CONTROL_NONLPTCH 0 0x1b37 9 0 4294967295 STUTTER_ENABLE_NONLPTCH 0 0 STUTTER_IGNORE_CURSOR_NONLPTCH 4 4 STUTTER_IGNORE_FBC_NONLPTCH 7 7 STUTTER_IGNORE_ICON_NONLPTCH 5 5 STUTTER_IGNORE_VGA_NONLPTCH 6 6 STUTTER_SELF_REFRESH_FORCE_ON_NONLPTCH 11 11 STUTTER_URGENT_IN_NOT_SELF_REFRESH_NONLPTCH 10 10 STUTTER_WM_HIGH_EXCLUDES_VBLANK_NONLPTCH 9 9 STUTTER_WM_HIGH_FORCE_ON_NONLPTCH 8 8 mmDPG_PIPE_URGENCY_CONTROL 0 0x1b33 2 0 4294967295 URGENCY_HIGH_WATERMARK 16 31 URGENCY_LOW_WATERMARK 0 15 mmDPG_TEST_DEBUG_DATA 0 0x1b39 1 0 4294967295 DPG_TEST_DEBUG_DATA 0 31 mmDPG_TEST_DEBUG_INDEX 0 0x1b38 2 0 4294967295 DPG_TEST_DEBUG_INDEX 0 7 DPG_TEST_DEBUG_WRITE_EN 8 8 mmDP_HBR2_EYE_PATTERN 0 0x1cc8 1 0 4294967295 DP_HBR2_EYE_PATTERN_ENABLE 0 0 mmDP_LINK_CNTL 0 0x1cc0 3 0 4294967295 DP_EMBEDDED_PANEL_MODE 17 17 DP_LINK_STATUS 8 8 DP_LINK_TRAINING_COMPLETE 4 4 mmDP_LINK_FRAMING_CNTL 0 0x1ccc 3 0 4294967295 DP_IDLE_BS_INTERVAL 0 17 DP_VBID_DISABLE 24 24 DP_VID_ENHANCED_FRAME_MODE 28 28 mmDP_MSA_COLORIMETRY 0 0x1cda 2 0 4294967295 DP_MSA_MISC0_OVERRIDE_ENABLE 8 8 DP_MSA_MISC0_OVERRIDE 0 7 mmDP_MSA_MISC 0 0x1cc5 4 0 4294967295 DP_MSA_MISC1 3 7 DP_MSA_MISC2 8 15 DP_MSA_MISC3 16 23 DP_MSA_MISC4 24 31 mmDP_MSA_V_TIMING_OVERRIDE1 0 0x1cea 2 0 4294967295 DP_MSA_V_TIMING_OVERRIDE_EN 0 0 DP_MSA_V_TOTAL_OVERRIDE 4 16 mmDP_MSA_V_TIMING_OVERRIDE2 0 0x1ceb 2 0 4294967295 DP_MSA_V_BLANK_END_OVERRIDE 16 28 DP_MSA_V_BLANK_START_OVERRIDE 0 12 mmDP_MSE_LINK_TIMING 0 0x1ce8 2 0 4294967295 DP_MSE_LINK_FRAME 0 9 DP_MSE_LINK_LINE 16 17 mmDP_MSE_MISC_CNTL 0 0x1cdb 3 0 4294967295 DP_MSE_BLANK_CODE 0 0 DP_MSE_TIMESTAMP_MODE 4 4 DP_MSE_ZERO_ENCODER 8 8 mmDP_MSE_RATE_CNTL 0 0x1ce1 2 0 4294967295 DP_MSE_RATE_X 26 31 DP_MSE_RATE_Y 0 25 mmDP_MSE_RATE_UPDATE 0 0x1ce3 1 0 4294967295 DP_MSE_RATE_UPDATE_PENDING 0 0 mmDP_MSE_SAT0 0 0x1ce4 4 0 4294967295 DP_MSE_SAT_SLOT_COUNT0 8 13 DP_MSE_SAT_SLOT_COUNT1 24 29 DP_MSE_SAT_SRC0 0 2 DP_MSE_SAT_SRC1 16 18 mmDP_MSE_SAT1 0 0x1ce5 4 0 4294967295 DP_MSE_SAT_SLOT_COUNT2 8 13 DP_MSE_SAT_SLOT_COUNT3 24 29 DP_MSE_SAT_SRC2 0 2 DP_MSE_SAT_SRC3 16 18 mmDP_MSE_SAT2 0 0x1ce6 4 0 4294967295 DP_MSE_SAT_SLOT_COUNT4 8 13 DP_MSE_SAT_SLOT_COUNT5 24 29 DP_MSE_SAT_SRC4 0 2 DP_MSE_SAT_SRC5 16 18 mmDP_MSE_SAT_UPDATE 0 0x1ce7 2 0 4294967295 DP_MSE_16_MTP_KEEPOUT 8 8 DP_MSE_SAT_UPDATE 0 1 mmDP_PIXEL_FORMAT 0 0x1cc1 4 0 4294967295 DP_COMPONENT_DEPTH 24 26 DP_DYN_RANGE 8 8 DP_PIXEL_ENCODING 0 1 DP_YCBCR_RANGE 16 16 mmDP_SEC_AUD_M 0 0x1ca7 1 0 4294967295 DP_SEC_AUD_M 0 23 mmDP_SEC_AUD_M_READBACK 0 0x1ca8 1 0 4294967295 DP_SEC_AUD_M_READBACK 0 23 mmDP_SEC_AUD_N 0 0x1ca5 1 0 4294967295 DP_SEC_AUD_N 0 23 mmDP_SEC_AUD_N_READBACK 0 0x1ca6 1 0 4294967295 DP_SEC_AUD_N_READBACK 0 23 mmDP_SEC_CNTL 0 0x1ca0 11 0 4294967295 DP_SEC_ACM_ENABLE 16 16 DP_SEC_AIP_ENABLE 12 12 DP_SEC_ASP_ENABLE 4 4 DP_SEC_ATP_ENABLE 8 8 DP_SEC_AVI_ENABLE 24 24 DP_SEC_GSP0_ENABLE 20 20 DP_SEC_GSP1_ENABLE 21 21 DP_SEC_GSP2_ENABLE 22 22 DP_SEC_GSP3_ENABLE 23 23 DP_SEC_MPG_ENABLE 28 28 DP_SEC_STREAM_ENABLE 0 0 mmDP_SEC_CNTL1 0 0x1cab 1 0 4294967295 DP_SEC_ISRC_ENABLE 0 0 mmDP_SEC_FRAMING1 0 0x1ca1 2 0 4294967295 DP_SEC_FRAME_START_LOCATION 0 11 DP_SEC_VBLANK_TRANSMIT_WIDTH 16 31 mmDP_SEC_FRAMING2 0 0x1ca2 2 0 4294967295 DP_SEC_HBLANK_TRANSMIT_WIDTH 16 31 DP_SEC_START_POSITION 0 15 mmDP_SEC_FRAMING3 0 0x1ca3 2 0 4294967295 DP_SEC_IDLE_FRAME_SIZE 0 13 DP_SEC_IDLE_TRANSMIT_WIDTH 16 31 mmDP_SEC_FRAMING4 0 0x1ca4 4 0 4294967295 DP_SEC_AUDIO_MUTE 28 28 DP_SEC_AUDIO_MUTE_STATUS 29 29 DP_SEC_COLLISION_ACK 24 24 DP_SEC_COLLISION_STATUS 20 20 mmDP_SEC_PACKET_CNTL 0 0x1caa 4 0 4294967295 DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE 16 16 DP_SEC_ASP_CODING_TYPE 1 3 DP_SEC_ASP_PRIORITY 4 4 DP_SEC_VERSION 8 13 mmDP_SEC_TIMESTAMP 0 0x1ca9 1 0 4294967295 DP_SEC_TIMESTAMP_MODE 0 0 mmDP_STEER_FIFO 0 0x1cc4 7 0 4294967295 DP_STEER_FIFO_RESET 0 0 DP_STEER_OVERFLOW_ACK 6 6 DP_STEER_OVERFLOW_FLAG 4 4 DP_STEER_OVERFLOW_INT 5 5 DP_STEER_OVERFLOW_MASK 7 7 DP_TU_OVERFLOW_ACK 12 12 DP_TU_OVERFLOW_FLAG 8 8 mmDP_TEST_DEBUG_DATA 0 0x1cfd 1 0 4294967295 DP_TEST_DEBUG_DATA 0 31 mmDP_TEST_DEBUG_INDEX 0 0x1cfc 2 0 4294967295 DP_TEST_DEBUG_INDEX 0 7 DP_TEST_DEBUG_WRITE_EN 8 8 mmDP_VID_INTERRUPT_CNTL 0 0x1ccf 3 0 4294967295 DP_VID_STREAM_DISABLE_ACK 1 1 DP_VID_STREAM_DISABLE_INT 0 0 DP_VID_STREAM_DISABLE_MASK 2 2 mmDP_VID_M 0 0x1ccb 1 0 4294967295 DP_VID_M 0 23 mmDP_VID_MSA_VBID 0 0x1ccd 3 0 4294967295 DP_VID_MSA_LOCATION 0 11 DP_VID_MSA_TOP_FIELD_MODE 16 16 DP_VID_VBID_FIELD_POL 24 24 mmDP_VID_N 0 0x1cca 1 0 4294967295 DP_VID_N 0 23 mmDP_VID_STREAM_CNTL 0 0x1cc3 4 0 4294967295 DP_VID_STREAM_CHANGE_KEEPOUT 20 20 DP_VID_STREAM_DIS_DEFER 8 9 DP_VID_STREAM_ENABLE 0 0 DP_VID_STREAM_STATUS 16 16 mmDP_VID_TIMING 0 0x1cc9 3 0 4294967295 DP_VID_M_N_GEN_EN 8 8 DP_VID_N_DIV 24 31 DP_VID_TIMING_MODE 0 0 mmDVOACLKC_CNTL 0 0x16a 5 0 4294967295 DVOACLKC_COARSE_ADJUST_EN 17 17 DVOACLKC_COARSE_SKEW_CNTL 8 12 DVOACLKC_FINE_ADJUST_EN 16 16 DVOACLKC_FINE_SKEW_CNTL 0 2 DVOACLKC_IN_PHASE 18 18 mmDVOACLKC_MVP_CNTL 0 0x169 8 0 4294967295 DVOACLKC_MVP_COARSE_ADJUST_EN 17 17 DVOACLKC_MVP_COARSE_SKEW_CNTL 8 12 DVOACLKC_MVP_FINE_ADJUST_EN 16 16 DVOACLKC_MVP_FINE_SKEW_CNTL 0 2 DVOACLKC_MVP_IN_PHASE 18 18 DVOACLKC_MVP_SKEW_PHASE_OVERRIDE 20 20 MVP_CLK_A_SRC_SEL 24 25 MVP_CLK_B_SRC_SEL 28 29 mmDVOACLKD_CNTL 0 0x168 5 0 4294967295 DVOACLKD_COARSE_ADJUST_EN 17 17 DVOACLKD_COARSE_SKEW_CNTL 8 12 DVOACLKD_FINE_ADJUST_EN 16 16 DVOACLKD_FINE_SKEW_CNTL 0 2 DVOACLKD_IN_PHASE 18 18 mmDVO_CLK_ENABLE 0 0x129 1 0 4294967295 DVO_CLK_ENABLE 0 0 mmDVO_CONTROL 0 0x185b 8 0 4294967295 DVO_COLOR_FORMAT 24 25 DVO_CTL3 31 31 DVO_DUAL_CHANNEL_EN 8 8 DVO_INVERT_DVOCLK 18 18 DVO_RATE_SELECT 0 0 DVO_RESET_FIFO 16 16 DVO_SDRCLK_SEL 1 1 DVO_SYNC_PHASE 17 17 mmDVO_CRC2_SIG_MASK 0 0x185d 1 0 4294967295 DVO_CRC2_SIG_MASK 0 26 mmDVO_CRC2_SIG_RESULT 0 0x185e 1 0 4294967295 DVO_CRC2_SIG_RESULT 0 26 mmDVO_CRC_EN 0 0x185c 1 0 4294967295 DVO_CRC2_EN 16 16 mmDVO_ENABLE 0 0x1858 1 0 4294967295 DVO_ENABLE 0 0 mmDVO_FIFO_ERROR_STATUS 0 0x185f 10 0 4294967295 DVO_FIFO_CAL_AVERAGE_LEVEL 10 15 DVO_FIFO_CALIBRATED 29 29 DVO_FIFO_ERROR_ACK 8 8 DVO_FIFO_FORCE_RECAL_AVERAGE 30 30 DVO_FIFO_FORCE_RECOMP_MINMAX 31 31 DVO_FIFO_LEVEL_ERROR 0 0 DVO_FIFO_MAXIMUM_LEVEL 16 19 DVO_FIFO_MINIMUM_LEVEL 22 25 DVO_FIFO_OVERWRITE_LEVEL 2 7 DVO_FIFO_USE_OVERWRITE_LEVEL 1 1 mmDVO_OUTPUT 0 0x185a 2 0 4294967295 DVO_CLOCK_MODE 8 8 DVO_OUTPUT_ENABLE_MODE 0 1 mmDVO_SKEW_ADJUST 0 0x197d 1 0 4294967295 DVO_SKEW_ADJUST 0 31 mmDVO_SOURCE_SELECT 0 0x1859 2 0 4294967295 DVO_SOURCE_SELECT 0 2 DVO_STEREOSYNC_SELECT 16 18 mmDVO_STRENGTH_CONTROL 0 0x197b 6 0 4294967295 DVOCLK_SN 12 15 DVOCLK_SP 8 11 DVO_LSB_VMODE 28 28 DVO_MSB_VMODE 29 29 DVO_SN 4 7 DVO_SP 0 3 mmDVO_VREF_CONTROL 0 0x197c 3 0 4294967295 DVO_VREFCAL 4 7 DVO_VREFPON 0 0 DVO_VREFSEL 1 1 mmEXT_OVERSCAN_LEFT_RIGHT 0 0x1b5e 2 0 4294967295 EXT_OVERSCAN_LEFT 16 27 EXT_OVERSCAN_RIGHT 0 11 mmEXT_OVERSCAN_TOP_BOTTOM 0 0x1b5f 2 0 4294967295 EXT_OVERSCAN_BOTTOM 0 11 EXT_OVERSCAN_TOP 16 27 mmFBC_CLIENT_REGION_MASK 0 0x16eb 1 0 4294967295 FBC_MEMORY_REGION_MASK 16 19 mmFBC_CNTL 0 0x16d0 5 0 4294967295 FBC_COHERENCY_MODE 16 17 FBC_EN 31 31 FBC_GRPH_COMP_EN 0 0 FBC_SOFT_COMPRESS_EN 25 25 FBC_SRC_SEL 1 3 mmFBC_COMP_CNTL 0 0x16d4 6 0 4294967295 FBC_DEPTH_MONO08_EN 16 16 FBC_DEPTH_MONO16_EN 17 17 FBC_DEPTH_RGB04_EN 18 18 FBC_DEPTH_RGB08_EN 19 19 FBC_DEPTH_RGB16_EN 20 20 FBC_MIN_COMPRESSION 0 3 mmFBC_COMP_MODE 0 0x16d5 6 0 4294967295 FBC_DPCM4_RGB_EN 8 8 FBC_DPCM4_YUV_EN 10 10 FBC_DPCM8_RGB_EN 9 9 FBC_DPCM8_YUV_EN 11 11 FBC_IND_EN 16 16 FBC_RLE_EN 0 0 mmFBC_CSM_REGION_OFFSET_01 0 0x16e9 2 0 4294967295 FBC_CSM_REGION_OFFSET_0 0 9 FBC_CSM_REGION_OFFSET_1 16 25 mmFBC_CSM_REGION_OFFSET_23 0 0x16ea 2 0 4294967295 FBC_CSM_REGION_OFFSET_2 0 9 FBC_CSM_REGION_OFFSET_3 16 25 mmFBC_DEBUG0 0 0x16d6 5 0 4294967295 FBC_COMP_WAKE_DIS 16 16 FBC_DEBUG0 17 23 FBC_DEBUG_MUX 24 31 FBC_PERF_MUX0 0 7 FBC_PERF_MUX1 8 15 mmFBC_DEBUG1 0 0x16d7 1 0 4294967295 FBC_DEBUG1 0 31 mmFBC_DEBUG2 0 0x16d8 1 0 4294967295 FBC_DEBUG2 0 31 mmFBC_DEBUG_COMP 0 0x16ec 6 0 4294967295 FBC_COMP_ADDRESS_TRANSLATION_ENABLE 11 11 FBC_COMP_BUSY_HYSTERESIS 4 7 FBC_COMP_CLK_CNTL 8 9 FBC_COMP_PRIVILEGED_ACCESS_ENABLE 10 10 FBC_COMP_RSIZE 3 3 FBC_COMP_SWAP 0 1 mmFBC_DEBUG_CSR 0 0x16ed 4 0 4294967295 FBC_DEBUG_CSR_ADDR 0 9 FBC_DEBUG_CSR_EN 31 31 FBC_DEBUG_CSR_RD_DATA 17 17 FBC_DEBUG_CSR_WR_DATA 16 16 mmFBC_DEBUG_CSR_RDATA 0 0x16ee 1 0 4294967295 FBC_DEBUG_CSR_RDATA 0 31 mmFBC_DEBUG_CSR_RDATA_HI 0 0x16f6 1 0 4294967295 FBC_DEBUG_CSR_RDATA_HI 0 7 mmFBC_DEBUG_CSR_WDATA 0 0x16ef 1 0 4294967295 FBC_DEBUG_CSR_WDATA 0 31 mmFBC_DEBUG_CSR_WDATA_HI 0 0x16f7 1 0 4294967295 FBC_DEBUG_CSR_WDATA_HI 0 7 mmFBC_IDLE_FORCE_CLEAR_MASK 0 0x16d2 1 0 4294967295 FBC_IDLE_FORCE_CLEAR_MASK 0 31 mmFBC_IDLE_MASK 0 0x16d1 1 0 4294967295 FBC_IDLE_MASK 0 31 mmFBC_IND_LUT0 0 0x16d9 1 0 4294967295 FBC_IND_LUT0 0 23 mmFBC_IND_LUT10 0 0x16e3 1 0 4294967295 FBC_IND_LUT10 0 23 mmFBC_IND_LUT1 0 0x16da 1 0 4294967295 FBC_IND_LUT1 0 23 mmFBC_IND_LUT11 0 0x16e4 1 0 4294967295 FBC_IND_LUT11 0 23 mmFBC_IND_LUT12 0 0x16e5 1 0 4294967295 FBC_IND_LUT12 0 23 mmFBC_IND_LUT13 0 0x16e6 1 0 4294967295 FBC_IND_LUT13 0 23 mmFBC_IND_LUT14 0 0x16e7 1 0 4294967295 FBC_IND_LUT14 0 23 mmFBC_IND_LUT15 0 0x16e8 1 0 4294967295 FBC_IND_LUT15 0 23 mmFBC_IND_LUT2 0 0x16db 1 0 4294967295 FBC_IND_LUT2 0 23 mmFBC_IND_LUT3 0 0x16dc 1 0 4294967295 FBC_IND_LUT3 0 23 mmFBC_IND_LUT4 0 0x16dd 1 0 4294967295 FBC_IND_LUT4 0 23 mmFBC_IND_LUT5 0 0x16de 1 0 4294967295 FBC_IND_LUT5 0 23 mmFBC_IND_LUT6 0 0x16df 1 0 4294967295 FBC_IND_LUT6 0 23 mmFBC_IND_LUT7 0 0x16e0 1 0 4294967295 FBC_IND_LUT7 0 23 mmFBC_IND_LUT8 0 0x16e1 1 0 4294967295 FBC_IND_LUT8 0 23 mmFBC_IND_LUT9 0 0x16e2 1 0 4294967295 FBC_IND_LUT9 0 23 mmFBC_MISC 0 0x16f0 12 0 4294967295 FBC_DECOMPRESS_ERROR_CLEAR 16 16 FBC_DECOMPRESS_ERROR 0 1 FBC_DIVIDE_X 8 9 FBC_DIVIDE_Y 10 10 FBC_ERROR_PIXEL 4 7 FBC_INVALIDATE_ON_ERROR 3 3 FBC_RESET_AT_DISABLE 21 21 FBC_RESET_AT_ENABLE 20 20 FBC_RSM_UNCOMP_DATA_IMMEDIATELY 12 12 FBC_RSM_WRITE_VALUE 11 11 FBC_SLOW_REQ_INTERVAL 28 31 FBC_STOP_ON_ERROR 2 2 mmFBC_START_STOP_DELAY 0 0x16d3 3 0 4294967295 FBC_COMP_START_DELAY 8 12 FBC_DECOMP_START_DELAY 0 4 FBC_DECOMP_STOP_DELAY 7 7 mmFBC_STATUS 0 0x16f1 1 0 4294967295 FBC_ENABLE_STATUS 0 0 mmFBC_TEST_DEBUG_DATA 0 0x16f5 1 0 4294967295 FBC_TEST_DEBUG_DATA 0 31 mmFBC_TEST_DEBUG_INDEX 0 0x16f4 2 0 4294967295 FBC_TEST_DEBUG_INDEX 0 7 FBC_TEST_DEBUG_WRITE_EN 8 8 mmFMT0_FMT_BIT_DEPTH_CONTROL 0 0x1bf2 0 0 4294967295 mmFMT0_FMT_CLAMP_CNTL 0 0x1bf9 0 0 4294967295 mmFMT0_FMT_CONTROL 0 0x1bee 0 0 4294967295 mmFMT0_FMT_CRC_CNTL 0 0x1bfa 0 0 4294967295 mmFMT0_FMT_CRC_SIG_BLUE_CONTROL 0 0x1bfe 0 0 4294967295 mmFMT0_FMT_CRC_SIG_BLUE_CONTROL_MASK 0 0x1bfc 0 0 4294967295 mmFMT0_FMT_CRC_SIG_RED_GREEN 0 0x1bfd 0 0 4294967295 mmFMT0_FMT_CRC_SIG_RED_GREEN_MASK 0 0x1bfb 0 0 4294967295 mmFMT0_FMT_DEBUG_CNTL 0 0x1bff 0 0 4294967295 mmFMT0_FMT_DITHER_RAND_B_SEED 0 0x1bf5 0 0 4294967295 mmFMT0_FMT_DITHER_RAND_G_SEED 0 0x1bf4 0 0 4294967295 mmFMT0_FMT_DITHER_RAND_R_SEED 0 0x1bf3 0 0 4294967295 mmFMT0_FMT_DYNAMIC_EXP_CNTL 0 0x1bed 0 0 4294967295 mmFMT0_FMT_FORCE_DATA_0_1 0 0x1bf0 0 0 4294967295 mmFMT0_FMT_FORCE_DATA_2_3 0 0x1bf1 0 0 4294967295 mmFMT0_FMT_FORCE_OUTPUT_CNTL 0 0x1bef 0 0 4294967295 mmFMT0_FMT_TEMPORAL_DITHER_PATTERN_CONTROL 0 0x1bf6 0 0 4294967295 mmFMT0_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX 0 0x1bf7 0 0 4294967295 mmFMT0_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX 0 0x1bf8 0 0 4294967295 mmFMT0_FMT_TEST_DEBUG_DATA 0 0x1bec 0 0 4294967295 mmFMT0_FMT_TEST_DEBUG_INDEX 0 0x1beb 0 0 4294967295 mmFMT1_FMT_BIT_DEPTH_CONTROL 0 0x1ef2 0 0 4294967295 mmFMT1_FMT_CLAMP_CNTL 0 0x1ef9 0 0 4294967295 mmFMT1_FMT_CONTROL 0 0x1eee 0 0 4294967295 mmFMT1_FMT_CRC_CNTL 0 0x1efa 0 0 4294967295 mmFMT1_FMT_CRC_SIG_BLUE_CONTROL 0 0x1efe 0 0 4294967295 mmFMT1_FMT_CRC_SIG_BLUE_CONTROL_MASK 0 0x1efc 0 0 4294967295 mmFMT1_FMT_CRC_SIG_RED_GREEN 0 0x1efd 0 0 4294967295 mmFMT1_FMT_CRC_SIG_RED_GREEN_MASK 0 0x1efb 0 0 4294967295 mmFMT1_FMT_DEBUG_CNTL 0 0x1eff 0 0 4294967295 mmFMT1_FMT_DITHER_RAND_B_SEED 0 0x1ef5 0 0 4294967295 mmFMT1_FMT_DITHER_RAND_G_SEED 0 0x1ef4 0 0 4294967295 mmFMT1_FMT_DITHER_RAND_R_SEED 0 0x1ef3 0 0 4294967295 mmFMT1_FMT_DYNAMIC_EXP_CNTL 0 0x1eed 0 0 4294967295 mmFMT1_FMT_FORCE_DATA_0_1 0 0x1ef0 0 0 4294967295 mmFMT1_FMT_FORCE_DATA_2_3 0 0x1ef1 0 0 4294967295 mmFMT1_FMT_FORCE_OUTPUT_CNTL 0 0x1eef 0 0 4294967295 mmFMT1_FMT_TEMPORAL_DITHER_PATTERN_CONTROL 0 0x1ef6 0 0 4294967295 mmFMT1_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX 0 0x1ef7 0 0 4294967295 mmFMT1_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX 0 0x1ef8 0 0 4294967295 mmFMT1_FMT_TEST_DEBUG_DATA 0 0x1eec 0 0 4294967295 mmFMT1_FMT_TEST_DEBUG_INDEX 0 0x1eeb 0 0 4294967295 mmFMT2_FMT_BIT_DEPTH_CONTROL 0 0x41f2 0 0 4294967295 mmFMT2_FMT_CLAMP_CNTL 0 0x41f9 0 0 4294967295 mmFMT2_FMT_CONTROL 0 0x41ee 0 0 4294967295 mmFMT2_FMT_CRC_CNTL 0 0x41fa 0 0 4294967295 mmFMT2_FMT_CRC_SIG_BLUE_CONTROL 0 0x41fe 0 0 4294967295 mmFMT2_FMT_CRC_SIG_BLUE_CONTROL_MASK 0 0x41fc 0 0 4294967295 mmFMT2_FMT_CRC_SIG_RED_GREEN 0 0x41fd 0 0 4294967295 mmFMT2_FMT_CRC_SIG_RED_GREEN_MASK 0 0x41fb 0 0 4294967295 mmFMT2_FMT_DEBUG_CNTL 0 0x41ff 0 0 4294967295 mmFMT2_FMT_DITHER_RAND_B_SEED 0 0x41f5 0 0 4294967295 mmFMT2_FMT_DITHER_RAND_G_SEED 0 0x41f4 0 0 4294967295 mmFMT2_FMT_DITHER_RAND_R_SEED 0 0x41f3 0 0 4294967295 mmFMT2_FMT_DYNAMIC_EXP_CNTL 0 0x41ed 0 0 4294967295 mmFMT2_FMT_FORCE_DATA_0_1 0 0x41f0 0 0 4294967295 mmFMT2_FMT_FORCE_DATA_2_3 0 0x41f1 0 0 4294967295 mmFMT2_FMT_FORCE_OUTPUT_CNTL 0 0x41ef 0 0 4294967295 mmFMT2_FMT_TEMPORAL_DITHER_PATTERN_CONTROL 0 0x41f6 0 0 4294967295 mmFMT2_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX 0 0x41f7 0 0 4294967295 mmFMT2_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX 0 0x41f8 0 0 4294967295 mmFMT2_FMT_TEST_DEBUG_DATA 0 0x41ec 0 0 4294967295 mmFMT2_FMT_TEST_DEBUG_INDEX 0 0x41eb 0 0 4294967295 mmFMT3_FMT_BIT_DEPTH_CONTROL 0 0x44f2 0 0 4294967295 mmFMT3_FMT_CLAMP_CNTL 0 0x44f9 0 0 4294967295 mmFMT3_FMT_CONTROL 0 0x44ee 0 0 4294967295 mmFMT3_FMT_CRC_CNTL 0 0x44fa 0 0 4294967295 mmFMT3_FMT_CRC_SIG_BLUE_CONTROL 0 0x44fe 0 0 4294967295 mmFMT3_FMT_CRC_SIG_BLUE_CONTROL_MASK 0 0x44fc 0 0 4294967295 mmFMT3_FMT_CRC_SIG_RED_GREEN 0 0x44fd 0 0 4294967295 mmFMT3_FMT_CRC_SIG_RED_GREEN_MASK 0 0x44fb 0 0 4294967295 mmFMT3_FMT_DEBUG_CNTL 0 0x44ff 0 0 4294967295 mmFMT3_FMT_DITHER_RAND_B_SEED 0 0x44f5 0 0 4294967295 mmFMT3_FMT_DITHER_RAND_G_SEED 0 0x44f4 0 0 4294967295 mmFMT3_FMT_DITHER_RAND_R_SEED 0 0x44f3 0 0 4294967295 mmFMT3_FMT_DYNAMIC_EXP_CNTL 0 0x44ed 0 0 4294967295 mmFMT3_FMT_FORCE_DATA_0_1 0 0x44f0 0 0 4294967295 mmFMT3_FMT_FORCE_DATA_2_3 0 0x44f1 0 0 4294967295 mmFMT3_FMT_FORCE_OUTPUT_CNTL 0 0x44ef 0 0 4294967295 mmFMT3_FMT_TEMPORAL_DITHER_PATTERN_CONTROL 0 0x44f6 0 0 4294967295 mmFMT3_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX 0 0x44f7 0 0 4294967295 mmFMT3_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX 0 0x44f8 0 0 4294967295 mmFMT3_FMT_TEST_DEBUG_DATA 0 0x44ec 0 0 4294967295 mmFMT3_FMT_TEST_DEBUG_INDEX 0 0x44eb 0 0 4294967295 mmFMT4_FMT_BIT_DEPTH_CONTROL 0 0x47f2 0 0 4294967295 mmFMT4_FMT_CLAMP_CNTL 0 0x47f9 0 0 4294967295 mmFMT4_FMT_CONTROL 0 0x47ee 0 0 4294967295 mmFMT4_FMT_CRC_CNTL 0 0x47fa 0 0 4294967295 mmFMT4_FMT_CRC_SIG_BLUE_CONTROL 0 0x47fe 0 0 4294967295 mmFMT4_FMT_CRC_SIG_BLUE_CONTROL_MASK 0 0x47fc 0 0 4294967295 mmFMT4_FMT_CRC_SIG_RED_GREEN 0 0x47fd 0 0 4294967295 mmFMT4_FMT_CRC_SIG_RED_GREEN_MASK 0 0x47fb 0 0 4294967295 mmFMT4_FMT_DEBUG_CNTL 0 0x47ff 0 0 4294967295 mmFMT4_FMT_DITHER_RAND_B_SEED 0 0x47f5 0 0 4294967295 mmFMT4_FMT_DITHER_RAND_G_SEED 0 0x47f4 0 0 4294967295 mmFMT4_FMT_DITHER_RAND_R_SEED 0 0x47f3 0 0 4294967295 mmFMT4_FMT_DYNAMIC_EXP_CNTL 0 0x47ed 0 0 4294967295 mmFMT4_FMT_FORCE_DATA_0_1 0 0x47f0 0 0 4294967295 mmFMT4_FMT_FORCE_DATA_2_3 0 0x47f1 0 0 4294967295 mmFMT4_FMT_FORCE_OUTPUT_CNTL 0 0x47ef 0 0 4294967295 mmFMT4_FMT_TEMPORAL_DITHER_PATTERN_CONTROL 0 0x47f6 0 0 4294967295 mmFMT4_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX 0 0x47f7 0 0 4294967295 mmFMT4_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX 0 0x47f8 0 0 4294967295 mmFMT4_FMT_TEST_DEBUG_DATA 0 0x47ec 0 0 4294967295 mmFMT4_FMT_TEST_DEBUG_INDEX 0 0x47eb 0 0 4294967295 mmFMT5_FMT_BIT_DEPTH_CONTROL 0 0x4af2 0 0 4294967295 mmFMT5_FMT_CLAMP_CNTL 0 0x4af9 0 0 4294967295 mmFMT5_FMT_CONTROL 0 0x4aee 0 0 4294967295 mmFMT5_FMT_CRC_CNTL 0 0x4afa 0 0 4294967295 mmFMT5_FMT_CRC_SIG_BLUE_CONTROL 0 0x4afe 0 0 4294967295 mmFMT5_FMT_CRC_SIG_BLUE_CONTROL_MASK 0 0x4afc 0 0 4294967295 mmFMT5_FMT_CRC_SIG_RED_GREEN 0 0x4afd 0 0 4294967295 mmFMT5_FMT_CRC_SIG_RED_GREEN_MASK 0 0x4afb 0 0 4294967295 mmFMT5_FMT_DEBUG_CNTL 0 0x4aff 0 0 4294967295 mmFMT5_FMT_DITHER_RAND_B_SEED 0 0x4af5 0 0 4294967295 mmFMT5_FMT_DITHER_RAND_G_SEED 0 0x4af4 0 0 4294967295 mmFMT5_FMT_DITHER_RAND_R_SEED 0 0x4af3 0 0 4294967295 mmFMT5_FMT_DYNAMIC_EXP_CNTL 0 0x4aed 0 0 4294967295 mmFMT5_FMT_FORCE_DATA_0_1 0 0x4af0 0 0 4294967295 mmFMT5_FMT_FORCE_DATA_2_3 0 0x4af1 0 0 4294967295 mmFMT5_FMT_FORCE_OUTPUT_CNTL 0 0x4aef 0 0 4294967295 mmFMT5_FMT_TEMPORAL_DITHER_PATTERN_CONTROL 0 0x4af6 0 0 4294967295 mmFMT5_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX 0 0x4af7 0 0 4294967295 mmFMT5_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX 0 0x4af8 0 0 4294967295 mmFMT5_FMT_TEST_DEBUG_DATA 0 0x4aec 0 0 4294967295 mmFMT5_FMT_TEST_DEBUG_INDEX 0 0x4aeb 0 0 4294967295 mmFMT_BIT_DEPTH_CONTROL 0 0x1bf2 16 0 4294967295 FMT_25FRC_SEL 26 27 FMT_50FRC_SEL 28 29 FMT_75FRC_SEL 30 31 FMT_FRAME_RANDOM_ENABLE 13 13 FMT_HIGHPASS_RANDOM_ENABLE 15 15 FMT_RGB_RANDOM_ENABLE 14 14 FMT_SPATIAL_DITHER_DEPTH 12 12 FMT_SPATIAL_DITHER_EN 8 8 FMT_SPATIAL_DITHER_MODE 9 10 FMT_TEMPORAL_DITHER_DEPTH 20 20 FMT_TEMPORAL_DITHER_EN 16 16 FMT_TEMPORAL_DITHER_OFFSET 21 22 FMT_TEMPORAL_DITHER_RESET 25 25 FMT_TEMPORAL_LEVEL 24 24 FMT_TRUNCATE_DEPTH 4 4 FMT_TRUNCATE_EN 0 0 mmFMT_CLAMP_CNTL 0 0x1bf9 2 0 4294967295 FMT_CLAMP_COLOR_FORMAT 16 18 FMT_CLAMP_DATA_EN 0 0 mmFMT_CONTROL 0 0x1bee 3 0 4294967295 FMT_PIXEL_ENCODING 16 16 FMT_STEREOSYNC_OVERRIDE 0 0 FMT_STEREOSYNC_OVR_POL 4 4 mmFMT_CRC_CNTL 0 0x1bfa 7 0 4294967295 FMT_CRC_CONT_EN 4 4 FMT_CRC_EN 0 0 FMT_CRC_EVEN_ODD_PIX_ENABLE 20 20 FMT_CRC_EVEN_ODD_PIX_SELECT 24 24 FMT_CRC_INTERLACE_MODE 12 13 FMT_CRC_ONLY_BLANKb 8 8 FMT_CRC_USE_NEW_AND_REPEATED_PIXELS 16 16 mmFMT_CRC_SIG_BLUE_CONTROL 0 0x1bfe 2 0 4294967295 FMT_CRC_SIG_BLUE 0 15 FMT_CRC_SIG_CONTROL 16 31 mmFMT_CRC_SIG_BLUE_CONTROL_MASK 0 0x1bfc 2 0 4294967295 FMT_CRC_SIG_BLUE_MASK 0 15 FMT_CRC_SIG_CONTROL_MASK 16 31 mmFMT_CRC_SIG_RED_GREEN 0 0x1bfd 2 0 4294967295 FMT_CRC_SIG_GREEN 16 31 FMT_CRC_SIG_RED 0 15 mmFMT_CRC_SIG_RED_GREEN_MASK 0 0x1bfb 2 0 4294967295 FMT_CRC_SIG_GREEN_MASK 16 31 FMT_CRC_SIG_RED_MASK 0 15 mmFMT_DEBUG_CNTL 0 0x1bff 1 0 4294967295 FMT_DEBUG_COLOR_SELECT 0 1 mmFMT_DITHER_RAND_B_SEED 0 0x1bf5 1 0 4294967295 FMT_RAND_B_SEED 0 7 mmFMT_DITHER_RAND_G_SEED 0 0x1bf4 1 0 4294967295 FMT_RAND_G_SEED 0 7 mmFMT_DITHER_RAND_R_SEED 0 0x1bf3 1 0 4294967295 FMT_RAND_R_SEED 0 7 mmFMT_DYNAMIC_EXP_CNTL 0 0x1bed 2 0 4294967295 FMT_DYNAMIC_EXP_EN 0 0 FMT_DYNAMIC_EXP_MODE 4 4 mmFMT_FORCE_DATA_0_1 0 0x1bf0 2 0 4294967295 FMT_FORCE_DATA0 0 15 FMT_FORCE_DATA1 16 31 mmFMT_FORCE_DATA_2_3 0 0x1bf1 2 0 4294967295 FMT_FORCE_DATA2 0 15 FMT_FORCE_DATA3 16 31 mmFMT_FORCE_OUTPUT_CNTL 0 0x1bef 4 0 4294967295 FMT_FORCE_DATA_EN 0 0 FMT_FORCE_DATA_ON_BLANKb_ONLY 16 16 FMT_FORCE_DATA_SEL_COLOR 8 10 FMT_FORCE_DATA_SEL_SLOT 12 15 mmFMT_TEMPORAL_DITHER_PATTERN_CONTROL 0 0x1bf6 2 0 4294967295 FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_RGB1_BGR0 4 4 FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_SELECT 0 0 mmFMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX 0 0x1bf7 1 0 4294967295 FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX 0 31 mmFMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX 0 0x1bf8 1 0 4294967295 FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX 0 31 mmFMT_TEST_DEBUG_DATA 0 0x1bec 1 0 4294967295 FMT_TEST_DEBUG_DATA 0 31 mmFMT_TEST_DEBUG_INDEX 0 0x1beb 2 0 4294967295 FMT_TEST_DEBUG_INDEX 0 7 FMT_TEST_DEBUG_WRITE_EN 8 8 mmGAMUT_REMAP_C11_C12 0 0x1a5a 2 0 4294967295 GAMUT_REMAP_C11 0 15 GAMUT_REMAP_C12 16 31 mmGAMUT_REMAP_C13_C14 0 0x1a5b 2 0 4294967295 GAMUT_REMAP_C13 0 15 GAMUT_REMAP_C14 16 31 mmGAMUT_REMAP_C21_C22 0 0x1a5c 2 0 4294967295 GAMUT_REMAP_C21 0 15 GAMUT_REMAP_C22 16 31 mmGAMUT_REMAP_C23_C24 0 0x1a5d 2 0 4294967295 GAMUT_REMAP_C23 0 15 GAMUT_REMAP_C24 16 31 mmGAMUT_REMAP_C31_C32 0 0x1a5e 2 0 4294967295 GAMUT_REMAP_C31 0 15 GAMUT_REMAP_C32 16 31 mmGAMUT_REMAP_C33_C34 0 0x1a5f 2 0 4294967295 GAMUT_REMAP_C33 0 15 GAMUT_REMAP_C34 16 31 mmGAMUT_REMAP_CONTROL 0 0x1a59 2 0 4294967295 GRPH_GAMUT_REMAP_MODE 0 1 OVL_GAMUT_REMAP_MODE 4 5 mmGENENB 0 0xf0 1 0 4294967295 BLK_IO_BASE 0 7 mmGENERIC_I2C_CONTROL 0 0x1834 5 0 4294967295 GENERIC_I2C_DBG_REF_SEL 31 31 GENERIC_I2C_ENABLE 3 3 GENERIC_I2C_GO 0 0 GENERIC_I2C_SEND_RESET 2 2 GENERIC_I2C_SOFT_RESET 1 1 mmGENERIC_I2C_DATA 0 0x183a 4 0 4294967295 GENERIC_I2C_DATA 8 15 GENERIC_I2C_DATA_RW 0 0 GENERIC_I2C_INDEX 16 19 GENERIC_I2C_INDEX_WRITE 31 31 mmGENERIC_I2C_INTERRUPT_CONTROL 0 0x1835 3 0 4294967295 GENERIC_I2C_DONE_ACK 1 1 GENERIC_I2C_DONE_INT 0 0 GENERIC_I2C_DONE_MASK 2 2 mmGENERIC_I2C_PIN_DEBUG 0 0x183c 6 0 4294967295 GENERIC_I2C_SCL_EN 2 2 GENERIC_I2C_SCL_INPUT 1 1 GENERIC_I2C_SCL_OUTPUT 0 0 GENERIC_I2C_SDA_EN 6 6 GENERIC_I2C_SDA_INPUT 5 5 GENERIC_I2C_SDA_OUTPUT 4 4 mmGENERIC_I2C_PIN_SELECTION 0 0x183b 2 0 4294967295 GENERIC_I2C_SCL_PIN_SEL 0 6 GENERIC_I2C_SDA_PIN_SEL 8 14 mmGENERIC_I2C_SETUP 0 0x1838 5 0 4294967295 GENERIC_I2C_CLK_DRIVE_EN 7 7 GENERIC_I2C_DATA_DRIVE_EN 0 0 GENERIC_I2C_DATA_DRIVE_SEL 1 1 GENERIC_I2C_INTRA_BYTE_DELAY 8 15 GENERIC_I2C_TIME_LIMIT 24 31 mmGENERIC_I2C_SPEED 0 0x1837 3 0 4294967295 GENERIC_I2C_DISABLE_FILTER_DURING_STALL 4 4 GENERIC_I2C_PRESCALE 16 31 GENERIC_I2C_THRESHOLD 0 1 mmGENERIC_I2C_STATUS 0 0x1836 6 0 4294967295 GENERIC_I2C_ABORTED 5 5 GENERIC_I2C_DONE 4 4 GENERIC_I2C_NACK 10 10 GENERIC_I2C_STATUS 0 3 GENERIC_I2C_STOPPED_ON_NACK 9 9 GENERIC_I2C_TIMEOUT 6 6 mmGENERIC_I2C_TRANSACTION 0 0x1839 6 0 4294967295 GENERIC_I2C_ACK_ON_READ 9 9 GENERIC_I2C_COUNT 16 19 GENERIC_I2C_RW 0 0 GENERIC_I2C_START 12 12 GENERIC_I2C_STOP 13 13 GENERIC_I2C_STOP_ON_NACK 8 8 mmGENFC_RD 0 0xf2 1 0 4294967295 VSYNC_SEL_R 3 3 mmGENFC_WT 0 0xee 1 0 4294967295 VSYNC_SEL_W 3 3 mmGENMO_RD 0 0xf3 6 0 4294967295 GENMO_MONO_ADDRESS_B 0 0 ODD_EVEN_MD_PGSEL 5 5 VGA_CKSEL 2 3 VGA_HSYNC_POL 6 6 VGA_RAM_EN 1 1 VGA_VSYNC_POL 7 7 mmGENMO_WT 0 0xf0 6 0 4294967295 GENMO_MONO_ADDRESS_B 0 0 ODD_EVEN_MD_PGSEL 5 5 VGA_CKSEL 2 3 VGA_HSYNC_POL 6 6 VGA_RAM_EN 1 1 VGA_VSYNC_POL 7 7 mmGENS0 0 0xf0 2 0 4294967295 CRT_INTR 7 7 SENSE_SWITCH 4 4 mmGENS1 0 0xee 3 0 4294967295 NO_DISPLAY 0 0 PIXEL_READ_BACK 4 5 VGA_VSTATUS 3 3 mmGRPH8_DATA 0 0xf3 1 0 4294967295 GRPH_DATA 0 7 mmGRPH8_IDX 0 0xf3 1 0 4294967295 GRPH_IDX 0 3 mmGRPH_COMPRESS_PITCH 0 0x1a1a 1 0 4294967295 GRPH_COMPRESS_PITCH 6 16 mmGRPH_COMPRESS_SURFACE_ADDRESS 0 0x1a19 1 0 4294967295 GRPH_COMPRESS_SURFACE_ADDRESS 8 31 mmGRPH_COMPRESS_SURFACE_ADDRESS_HIGH 0 0x1a1b 1 0 4294967295 GRPH_COMPRESS_SURFACE_ADDRESS_HIGH 0 7 mmGRPH_CONTROL 0 0x1a01 13 0 4294967295 GRPH_ADDRESS_TRANSLATION_ENABLE 16 16 GRPH_ARRAY_MODE 20 23 GRPH_BANK_HEIGHT 11 12 GRPH_BANK_WIDTH 6 7 GRPH_COLOR_EXPANSION_MODE 31 31 GRPH_DEPTH 0 1 GRPH_FORMAT 8 10 GRPH_MACRO_TILE_ASPECT 18 19 GRPH_NUM_BANKS 2 3 GRPH_PIPE_CONFIG 24 28 GRPH_PRIVILEGED_ACCESS_ENABLE 17 17 GRPH_TILE_SPLIT 13 15 GRPH_Z 4 5 mmGRPH_DFQ_CONTROL 0 0x1a14 3 0 4294967295 GRPH_DFQ_MIN_FREE_ENTRIES 8 10 GRPH_DFQ_RESET 0 0 GRPH_DFQ_SIZE 4 6 mmGRPH_DFQ_STATUS 0 0x1a15 4 0 4294967295 GRPH_DFQ_RESET_ACK 9 9 GRPH_DFQ_RESET_FLAG 8 8 GRPH_PRIMARY_DFQ_NUM_ENTRIES 0 3 GRPH_SECONDARY_DFQ_NUM_ENTRIES 4 7 mmGRPH_ENABLE 0 0x1a00 1 0 4294967295 GRPH_ENABLE 0 0 mmGRPH_FLIP_CONTROL 0 0x1a12 1 0 4294967295 GRPH_SURFACE_UPDATE_H_RETRACE_EN 0 0 mmGRPH_INTERRUPT_CONTROL 0 0x1a17 2 0 4294967295 GRPH_PFLIP_INT_MASK 0 0 GRPH_PFLIP_INT_TYPE 8 8 mmGRPH_INTERRUPT_STATUS 0 0x1a16 2 0 4294967295 GRPH_PFLIP_INT_CLEAR 8 8 GRPH_PFLIP_INT_OCCURRED 0 0 mmGRPH_LUT_10BIT_BYPASS 0 0x1a02 2 0 4294967295 GRPH_LUT_10BIT_BYPASS_DBL_BUF_EN 16 16 GRPH_LUT_10BIT_BYPASS_EN 8 8 mmGRPH_PITCH 0 0x1a06 1 0 4294967295 GRPH_PITCH 0 14 mmGRPH_PRIMARY_SURFACE_ADDRESS 0 0x1a04 2 0 4294967295 GRPH_PRIMARY_DFQ_ENABLE 0 0 GRPH_PRIMARY_SURFACE_ADDRESS 8 31 mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH 0 0x1a07 1 0 4294967295 GRPH_PRIMARY_SURFACE_ADDRESS_HIGH 0 7 mmGRPH_SECONDARY_SURFACE_ADDRESS 0 0x1a05 2 0 4294967295 GRPH_SECONDARY_DFQ_ENABLE 0 0 GRPH_SECONDARY_SURFACE_ADDRESS 8 31 mmGRPH_SECONDARY_SURFACE_ADDRESS_HIGH 0 0x1a08 1 0 4294967295 GRPH_SECONDARY_SURFACE_ADDRESS_HIGH 0 7 mmGRPH_STEREOSYNC_FLIP 0 0x1a97 5 0 4294967295 GRPH_PRIMARY_SURFACE_PENDING 16 16 GRPH_SECONDARY_SURFACE_PENDING 17 17 GRPH_STEREOSYNC_FLIP_EN 0 0 GRPH_STEREOSYNC_FLIP_MODE 8 9 GRPH_STEREOSYNC_SELECT_DISABLE 28 28 mmGRPH_SURFACE_ADDRESS_HIGH_INUSE 0 0x1a18 1 0 4294967295 GRPH_SURFACE_ADDRESS_HIGH_INUSE 0 7 mmGRPH_SURFACE_ADDRESS_INUSE 0 0x1a13 1 0 4294967295 GRPH_SURFACE_ADDRESS_INUSE 8 31 mmGRPH_SURFACE_OFFSET_X 0 0x1a09 1 0 4294967295 GRPH_SURFACE_OFFSET_X 0 13 mmGRPH_SURFACE_OFFSET_Y 0 0x1a0a 1 0 4294967295 GRPH_SURFACE_OFFSET_Y 0 13 mmGRPH_SWAP_CNTL 0 0x1a03 5 0 4294967295 GRPH_ALPHA_CROSSBAR 10 11 GRPH_BLUE_CROSSBAR 8 9 GRPH_ENDIAN_SWAP 0 1 GRPH_GREEN_CROSSBAR 6 7 GRPH_RED_CROSSBAR 4 5 mmGRPH_UPDATE 0 0x1a11 8 0 4294967295 GRPH_MODE_DISABLE_MULTIPLE_UPDATE 24 24 GRPH_MODE_UPDATE_PENDING 0 0 GRPH_MODE_UPDATE_TAKEN 1 1 GRPH_SURFACE_DISABLE_MULTIPLE_UPDATE 28 28 GRPH_SURFACE_UPDATE_PENDING 2 2 GRPH_SURFACE_UPDATE_TAKEN 3 3 GRPH_SURFACE_XDMA_PENDING_ENABLE 8 8 GRPH_UPDATE_LOCK 16 16 mmGRPH_X_END 0 0x1a0d 1 0 4294967295 GRPH_X_END 0 14 mmGRPH_X_START 0 0x1a0b 1 0 4294967295 GRPH_X_START 0 13 mmGRPH_Y_END 0 0x1a0e 1 0 4294967295 GRPH_Y_END 0 14 mmGRPH_Y_START 0 0x1a0c 1 0 4294967295 GRPH_Y_START 0 13 mmHDMI_ACR_32_0 0 0x1c37 1 0 4294967295 HDMI_ACR_CTS_32 12 31 mmHDMI_ACR_32_1 0 0x1c38 1 0 4294967295 HDMI_ACR_N_32 0 19 mmHDMI_ACR_44_0 0 0x1c39 1 0 4294967295 HDMI_ACR_CTS_44 12 31 mmHDMI_ACR_44_1 0 0x1c3a 1 0 4294967295 HDMI_ACR_N_44 0 19 mmHDMI_ACR_48_0 0 0x1c3b 1 0 4294967295 HDMI_ACR_CTS_48 12 31 mmHDMI_ACR_48_1 0 0x1c3c 1 0 4294967295 HDMI_ACR_N_48 0 19 mmHDMI_ACR_PACKET_CONTROL 0 0x1c0f 7 0 4294967295 HDMI_ACR_AUDIO_PRIORITY 31 31 HDMI_ACR_AUTO_SEND 12 12 HDMI_ACR_CONT 1 1 HDMI_ACR_N_MULTIPLE 16 18 HDMI_ACR_SELECT 4 5 HDMI_ACR_SEND 0 0 HDMI_ACR_SOURCE 8 8 mmHDMI_ACR_STATUS_0 0 0x1c3d 1 0 4294967295 HDMI_ACR_CTS 12 31 mmHDMI_ACR_STATUS_1 0 0x1c3e 1 0 4294967295 HDMI_ACR_N 0 19 mmHDMI_AUDIO_PACKET_CONTROL 0 0x1c0e 3 0 4294967295 HDMI_AUDIO_DELAY_EN 4 5 HDMI_AUDIO_PACKETS_PER_LINE 16 20 HDMI_AUDIO_SEND_MAX_PACKETS 8 8 mmHDMI_CONTROL 0 0x1c0c 6 0 4294967295 HDMI_DEEP_COLOR_DEPTH 28 29 HDMI_DEEP_COLOR_ENABLE 24 24 HDMI_ERROR_ACK 8 8 HDMI_ERROR_MASK 9 9 HDMI_KEEPOUT_MODE 0 0 HDMI_PACKET_GEN_VERSION 4 4 mmHDMI_GC 0 0x1c16 5 0 4294967295 HDMI_DEFAULT_PHASE 4 4 HDMI_GC_AVMUTE_CONT 2 2 HDMI_GC_AVMUTE 0 0 HDMI_PACKING_PHASE 8 11 HDMI_PACKING_PHASE_OVERRIDE 12 12 mmHDMI_GENERIC_PACKET_CONTROL0 0 0x1c13 6 0 4294967295 HDMI_GENERIC0_CONT 1 1 HDMI_GENERIC0_LINE 16 21 HDMI_GENERIC0_SEND 0 0 HDMI_GENERIC1_CONT 5 5 HDMI_GENERIC1_LINE 24 29 HDMI_GENERIC1_SEND 4 4 mmHDMI_GENERIC_PACKET_CONTROL1 0 0x1c30 6 0 4294967295 HDMI_GENERIC2_CONT 1 1 HDMI_GENERIC2_LINE 16 21 HDMI_GENERIC2_SEND 0 0 HDMI_GENERIC3_CONT 5 5 HDMI_GENERIC3_LINE 24 29 HDMI_GENERIC3_SEND 4 4 mmHDMI_INFOFRAME_CONTROL0 0 0x1c11 6 0 4294967295 HDMI_AUDIO_INFO_CONT 5 5 HDMI_AUDIO_INFO_SEND 4 4 HDMI_AVI_INFO_CONT 1 1 HDMI_AVI_INFO_SEND 0 0 HDMI_MPEG_INFO_CONT 9 9 HDMI_MPEG_INFO_SEND 8 8 mmHDMI_INFOFRAME_CONTROL1 0 0x1c12 3 0 4294967295 HDMI_AUDIO_INFO_LINE 8 13 HDMI_AVI_INFO_LINE 0 5 HDMI_MPEG_INFO_LINE 16 21 mmHDMI_STATUS 0 0x1c0d 4 0 4294967295 HDMI_ACTIVE_AVMUTE 0 0 HDMI_AUDIO_PACKET_ERROR 16 16 HDMI_ERROR_INT 27 27 HDMI_VBI_PACKET_ERROR 20 20 mmHDMI_VBI_PACKET_CONTROL 0 0x1c10 6 0 4294967295 HDMI_GC_CONT 5 5 HDMI_GC_SEND 4 4 HDMI_ISRC_CONT 9 9 HDMI_ISRC_LINE 16 21 HDMI_ISRC_SEND 8 8 HDMI_NULL_SEND 0 0 mmINPUT_CSC_C11_C12 0 0x1a36 2 0 4294967295 INPUT_CSC_C11 0 15 INPUT_CSC_C12 16 31 mmINPUT_CSC_C13_C14 0 0x1a37 2 0 4294967295 INPUT_CSC_C13 0 15 INPUT_CSC_C14 16 31 mmINPUT_CSC_C21_C22 0 0x1a38 2 0 4294967295 INPUT_CSC_C21 0 15 INPUT_CSC_C22 16 31 mmINPUT_CSC_C23_C24 0 0x1a39 2 0 4294967295 INPUT_CSC_C23 0 15 INPUT_CSC_C24 16 31 mmINPUT_CSC_C31_C32 0 0x1a3a 2 0 4294967295 INPUT_CSC_C31 0 15 INPUT_CSC_C32 16 31 mmINPUT_CSC_C33_C34 0 0x1a3b 2 0 4294967295 INPUT_CSC_C33 0 15 INPUT_CSC_C34 16 31 mmINPUT_CSC_CONTROL 0 0x1a35 2 0 4294967295 INPUT_CSC_GRPH_MODE 0 1 INPUT_CSC_OVL_MODE 4 5 mmINPUT_GAMMA_CONTROL 0 0x1a10 2 0 4294967295 GRPH_INPUT_GAMMA_MODE 0 1 OVL_INPUT_GAMMA_MODE 4 5 mmKEY_CONTROL 0 0x1a53 3 0 4294967295 GRPH_OVL_HALF_BLEND 28 28 KEY_MODE 1 2 KEY_SELECT 0 0 mmKEY_RANGE_ALPHA 0 0x1a54 2 0 4294967295 KEY_ALPHA_HIGH 16 31 KEY_ALPHA_LOW 0 15 mmKEY_RANGE_BLUE 0 0x1a57 2 0 4294967295 KEY_BLUE_HIGH 16 31 KEY_BLUE_LOW 0 15 mmKEY_RANGE_GREEN 0 0x1a56 2 0 4294967295 KEY_GREEN_HIGH 16 31 KEY_GREEN_LOW 0 15 mmKEY_RANGE_RED 0 0x1a55 2 0 4294967295 KEY_RED_HIGH 16 31 KEY_RED_LOW 0 15 mmLB0_DC_MVP_LB_CONTROL 0 0x1adb 0 0 4294967295 mmLB0_LB_DEBUG 0 0x1afc 0 0 4294967295 mmLB0_LB_DEBUG2 0 0x1ac9 0 0 4294967295 mmLB0_LB_NO_OUTSTANDING_REQ_STATUS 0 0x1ac8 0 0 4294967295 mmLB0_LB_SYNC_RESET_SEL 0 0x1aca 0 0 4294967295 mmLB0_LB_TEST_DEBUG_DATA 0 0x1aff 0 0 4294967295 mmLB0_LB_TEST_DEBUG_INDEX 0 0x1afe 0 0 4294967295 mmLB0_MVP_AFR_FLIP_FIFO_CNTL 0 0x1ad9 0 0 4294967295 mmLB0_MVP_AFR_FLIP_MODE 0 0x1ad8 0 0 4294967295 mmLB0_MVP_FLIP_LINE_NUM_INSERT 0 0x1ada 0 0 4294967295 mmLB1_DC_MVP_LB_CONTROL 0 0x1ddb 0 0 4294967295 mmLB1_LB_DEBUG 0 0x1dfc 0 0 4294967295 mmLB1_LB_DEBUG2 0 0x1dc9 0 0 4294967295 mmLB1_LB_NO_OUTSTANDING_REQ_STATUS 0 0x1dc8 0 0 4294967295 mmLB1_LB_SYNC_RESET_SEL 0 0x1dca 0 0 4294967295 mmLB1_LB_TEST_DEBUG_DATA 0 0x1dff 0 0 4294967295 mmLB1_LB_TEST_DEBUG_INDEX 0 0x1dfe 0 0 4294967295 mmLB1_MVP_AFR_FLIP_FIFO_CNTL 0 0x1dd9 0 0 4294967295 mmLB1_MVP_AFR_FLIP_MODE 0 0x1dd8 0 0 4294967295 mmLB1_MVP_FLIP_LINE_NUM_INSERT 0 0x1dda 0 0 4294967295 mmLB2_DC_MVP_LB_CONTROL 0 0x40db 0 0 4294967295 mmLB2_LB_DEBUG 0 0x40fc 0 0 4294967295 mmLB2_LB_DEBUG2 0 0x40c9 0 0 4294967295 mmLB2_LB_NO_OUTSTANDING_REQ_STATUS 0 0x40c8 0 0 4294967295 mmLB2_LB_SYNC_RESET_SEL 0 0x40ca 0 0 4294967295 mmLB2_LB_TEST_DEBUG_DATA 0 0x40ff 0 0 4294967295 mmLB2_LB_TEST_DEBUG_INDEX 0 0x40fe 0 0 4294967295 mmLB2_MVP_AFR_FLIP_FIFO_CNTL 0 0x40d9 0 0 4294967295 mmLB2_MVP_AFR_FLIP_MODE 0 0x40d8 0 0 4294967295 mmLB2_MVP_FLIP_LINE_NUM_INSERT 0 0x40da 0 0 4294967295 mmLB3_DC_MVP_LB_CONTROL 0 0x43db 0 0 4294967295 mmLB3_LB_DEBUG 0 0x43fc 0 0 4294967295 mmLB3_LB_DEBUG2 0 0x43c9 0 0 4294967295 mmLB3_LB_NO_OUTSTANDING_REQ_STATUS 0 0x43c8 0 0 4294967295 mmLB3_LB_SYNC_RESET_SEL 0 0x43ca 0 0 4294967295 mmLB3_LB_TEST_DEBUG_DATA 0 0x43ff 0 0 4294967295 mmLB3_LB_TEST_DEBUG_INDEX 0 0x43fe 0 0 4294967295 mmLB3_MVP_AFR_FLIP_FIFO_CNTL 0 0x43d9 0 0 4294967295 mmLB3_MVP_AFR_FLIP_MODE 0 0x43d8 0 0 4294967295 mmLB3_MVP_FLIP_LINE_NUM_INSERT 0 0x43da 0 0 4294967295 mmLB4_DC_MVP_LB_CONTROL 0 0x46db 0 0 4294967295 mmLB4_LB_DEBUG 0 0x46fc 0 0 4294967295 mmLB4_LB_DEBUG2 0 0x46c9 0 0 4294967295 mmLB4_LB_NO_OUTSTANDING_REQ_STATUS 0 0x46c8 0 0 4294967295 mmLB4_LB_SYNC_RESET_SEL 0 0x46ca 0 0 4294967295 mmLB4_LB_TEST_DEBUG_DATA 0 0x46ff 0 0 4294967295 mmLB4_LB_TEST_DEBUG_INDEX 0 0x46fe 0 0 4294967295 mmLB4_MVP_AFR_FLIP_FIFO_CNTL 0 0x46d9 0 0 4294967295 mmLB4_MVP_AFR_FLIP_MODE 0 0x46d8 0 0 4294967295 mmLB4_MVP_FLIP_LINE_NUM_INSERT 0 0x46da 0 0 4294967295 mmLB5_DC_MVP_LB_CONTROL 0 0x49db 0 0 4294967295 mmLB5_LB_DEBUG 0 0x49fc 0 0 4294967295 mmLB5_LB_DEBUG2 0 0x49c9 0 0 4294967295 mmLB5_LB_NO_OUTSTANDING_REQ_STATUS 0 0x49c8 0 0 4294967295 mmLB5_LB_SYNC_RESET_SEL 0 0x49ca 0 0 4294967295 mmLB5_LB_TEST_DEBUG_DATA 0 0x49ff 0 0 4294967295 mmLB5_LB_TEST_DEBUG_INDEX 0 0x49fe 0 0 4294967295 mmLB5_MVP_AFR_FLIP_FIFO_CNTL 0 0x49d9 0 0 4294967295 mmLB5_MVP_AFR_FLIP_MODE 0 0x49d8 0 0 4294967295 mmLB5_MVP_FLIP_LINE_NUM_INSERT 0 0x49da 0 0 4294967295 mmLB_DEBUG 0 0x1afc 1 0 4294967295 LB_DEBUG 0 31 mmLB_DEBUG2 0 0x1ac9 1 0 4294967295 LB_DEBUG2 0 31 mmLB_NO_OUTSTANDING_REQ_STATUS 0 0x1ac8 1 0 4294967295 LB_NO_OUTSTANDING_REQ_STAT 0 0 mmLB_SYNC_RESET_SEL 0 0x1aca 2 0 4294967295 LB_SYNC_RESET_SEL2 4 4 LB_SYNC_RESET_SEL 0 1 mmLB_TEST_DEBUG_DATA 0 0x1aff 1 0 4294967295 LB_TEST_DEBUG_DATA 0 31 mmLB_TEST_DEBUG_INDEX 0 0x1afe 2 0 4294967295 LB_TEST_DEBUG_INDEX 0 7 LB_TEST_DEBUG_WRITE_EN 8 8 mmLIGHT_SLEEP_CNTL 0 0x132 2 0 4294967295 LIGHT_SLEEP_DIS 0 0 MEM_SHUTDOWN_DIS 8 8 mmLOW_POWER_TILING_CONTROL 0 0x325 7 0 4294967295 LOW_POWER_TILING_ENABLE 0 0 LOW_POWER_TILING_MODE 3 4 LOW_POWER_TILING_NUM_BANKS 8 10 LOW_POWER_TILING_NUM_PIPES 5 7 LOW_POWER_TILING_PIPE_INTERLEAVE_SIZE 11 11 LOW_POWER_TILING_ROW_SIZE 12 14 LOW_POWER_TILING_ROWS_PER_CHAN 16 27 mmLVDS_DATA_CNTL 0 0x1c8c 9 0 4294967295 LVDS_24BIT_ENABLE 0 0 LVDS_24BIT_FORMAT 4 4 LVDS_2ND_CHAN_DE 8 8 LVDS_2ND_CHAN_HS 10 10 LVDS_2ND_CHAN_VS 9 9 LVDS_2ND_LINK_CNTL_BITS 12 14 LVDS_DTMG_POL 18 18 LVDS_FP_POL 16 16 LVDS_LP_POL 17 17 mmLVTMA_PWRSEQ_CNTL 0 0x1919 12 0 4294967295 LVTMA_BLON 24 24 LVTMA_BLON_OVRD 25 25 LVTMA_BLON_POL 26 26 LVTMA_DIGON 16 16 LVTMA_DIGON_OVRD 17 17 LVTMA_DIGON_POL 18 18 LVTMA_PWRSEQ_DISABLE_SYNCEN_CONTROL_OF_TX_EN 1 1 LVTMA_PWRSEQ_EN 0 0 LVTMA_PWRSEQ_TARGET_STATE 4 4 LVTMA_SYNCEN 8 8 LVTMA_SYNCEN_OVRD 9 9 LVTMA_SYNCEN_POL 10 10 mmLVTMA_PWRSEQ_DELAY1 0 0x191c 4 0 4294967295 LVTMA_PWRDN_DELAY1 16 23 LVTMA_PWRDN_DELAY2 24 31 LVTMA_PWRUP_DELAY1 0 7 LVTMA_PWRUP_DELAY2 8 15 mmLVTMA_PWRSEQ_DELAY2 0 0x191d 4 0 4294967295 LVTMA_PWRDN_DELAY3 16 23 LVTMA_PWRDN_MIN_LENGTH 0 7 LVTMA_PWRUP_DELAY3 8 15 LVTMA_VARY_BL_OVERRIDE_EN 24 24 mmLVTMA_PWRSEQ_REF_DIV 0 0x191b 2 0 4294967295 BL_PWM_REF_DIV 16 31 LVTMA_PWRSEQ_REF_DIV 0 11 mmLVTMA_PWRSEQ_STATE 0 0x191a 6 0 4294967295 LVTMA_PWRSEQ_BLON 3 3 LVTMA_PWRSEQ_DIGON 1 1 LVTMA_PWRSEQ_DONE 4 4 LVTMA_PWRSEQ_STATE 8 11 LVTMA_PWRSEQ_SYNCEN 2 2 LVTMA_PWRSEQ_TARGET_STATE_R 0 0 mmMASTER_COMM_CMD_REG 0 0x161f 4 0 4294967295 MASTER_COMM_CMD_REG_BYTE0 0 7 MASTER_COMM_CMD_REG_BYTE1 8 15 MASTER_COMM_CMD_REG_BYTE2 16 23 MASTER_COMM_CMD_REG_BYTE3 24 31 mmMASTER_COMM_CNTL_REG 0 0x1620 1 0 4294967295 MASTER_COMM_INTERRUPT 0 0 mmMASTER_COMM_DATA_REG1 0 0x161c 4 0 4294967295 MASTER_COMM_DATA_REG1_BYTE0 0 7 MASTER_COMM_DATA_REG1_BYTE1 8 15 MASTER_COMM_DATA_REG1_BYTE2 16 23 MASTER_COMM_DATA_REG1_BYTE3 24 31 mmMASTER_COMM_DATA_REG2 0 0x161d 4 0 4294967295 MASTER_COMM_DATA_REG2_BYTE0 0 7 MASTER_COMM_DATA_REG2_BYTE1 8 15 MASTER_COMM_DATA_REG2_BYTE2 16 23 MASTER_COMM_DATA_REG2_BYTE3 24 31 mmMASTER_COMM_DATA_REG3 0 0x161e 4 0 4294967295 MASTER_COMM_DATA_REG3_BYTE0 0 7 MASTER_COMM_DATA_REG3_BYTE1 8 15 MASTER_COMM_DATA_REG3_BYTE2 16 23 MASTER_COMM_DATA_REG3_BYTE3 24 31 mmMASTER_UPDATE_LOCK 0 0x1bbd 2 0 4294967295 GSL_CONTROL_MASTER_UPDATE_LOCK 8 8 MASTER_UPDATE_LOCK 0 0 mmMASTER_UPDATE_MODE 0 0x1bbe 2 0 4294967295 MASTER_UPDATE_INTERLACED_MODE 16 17 MASTER_UPDATE_MODE 0 2 mmMC_DC_INTERFACE_NACK_STATUS 0 0x31c 8 0 4294967295 DMIF_RDRET_NACK_CLEAR 4 4 DMIF_RDRET_NACK_OCCURRED 0 0 MCIF_RDRET_NACK_CLEAR 20 20 MCIF_RDRET_NACK_OCCURRED 16 16 MCIF_WRRET_NACK_CLEAR 28 28 MCIF_WRRET_NACK_OCCURRED 24 24 VIP_WRRET_NACK_CLEAR 12 12 VIP_WRRET_NACK_OCCURRED 8 8 mmMCIF_CONTROL 0 0x314 8 0 4294967295 ADDRESS_TRANSLATION_ENABLE 4 4 LOW_READ_URG_LEVEL 16 23 MC_CLEAN_DEASSERT_LATENCY 24 29 MCIF_BUFF_SIZE 0 1 MCIF_MC_LATENCY_COUNTER_ENABLE 30 30 MCIF_MC_LATENCY_COUNTER_URGENT_ONLY 31 31 MCIF_SLOW_REQ_INTERVAL 12 15 PRIVILEGED_ACCESS_ENABLE 8 8 mmMCIF_MEM_CONTROL 0 0x319 5 0 4294967295 MCIFMEM_CACHE_MODE_DIS 0 0 MCIFMEM_CACHE_MODE 4 5 MCIFMEM_CACHE_PIPE 16 18 MCIFMEM_CACHE_SIZE 8 14 MCIFMEM_CACHE_TYPE 19 20 mmMCIF_TEST_DEBUG_DATA 0 0x317 1 0 4294967295 MCIF_TEST_DEBUG_DATA 0 31 mmMCIF_TEST_DEBUG_INDEX 0 0x316 2 0 4294967295 MCIF_TEST_DEBUG_INDEX 0 7 MCIF_TEST_DEBUG_WRITE_EN 8 8 mmMCIF_VMID 0 0x318 2 0 4294967295 MCIF_WR_VMID 0 3 VIP_WR_VMID 4 7 mmMCIF_WRITE_COMBINE_CONTROL 0 0x315 2 0 4294967295 MCIF_WRITE_COMBINE_TIMEOUT 0 7 VIP_WRITE_COMBINE_TIMEOUT 8 15 mmMICROSECOND_TIME_BASE_DIV 0 0x13b 5 0 4294967295 MICROSECOND_TIME_BASE_CLOCK_SOURCE_SEL 20 20 MICROSECOND_TIME_BASE_DIV 0 6 XTAL_REF_CLOCK_SOURCE_SEL 17 17 XTAL_REF_DIV 8 14 XTAL_REF_SEL 16 16 mmMILLISECOND_TIME_BASE_DIV 0 0x130 2 0 4294967295 MILLISECOND_TIME_BASE_CLOCK_SOURCE_SEL 20 20 MILLISECOND_TIME_BASE_DIV 0 16 mmMVP_AFR_FLIP_FIFO_CNTL 0 0x1ad9 4 0 4294967295 MVP_AFR_FLIP_FIFO_NUM_ENTRIES 0 3 MVP_AFR_FLIP_FIFO_RESET_ACK 12 12 MVP_AFR_FLIP_FIFO_RESET_FLAG 8 8 MVP_AFR_FLIP_FIFO_RESET 4 4 mmMVP_AFR_FLIP_MODE 0 0x1ad8 1 0 4294967295 MVP_AFR_FLIP_MODE 0 1 mmMVP_BLACK_KEYER 0 0x1686 3 0 4294967295 MVP_BLACK_KEYER_B 20 29 MVP_BLACK_KEYER_G 10 19 MVP_BLACK_KEYER_R 0 9 mmMVP_CONTROL1 0 0x1680 12 0 4294967295 MVP_30BPP_EN 28 28 MVP_ARBITRATION_MODE_FOR_AFR_MANUAL_SWITCH_MODE 10 10 MVP_CHANNEL_CONTROL 16 16 MVP_DISABLE_MSB_EXPAND 24 24 MVP_EN 0 0 MVP_GPU_CHAIN_LOCATION 20 21 MVP_MIXER_MODE 4 6 MVP_MIXER_SLAVE_SEL_DELAY_UNTIL_END_OF_BLANK 9 9 MVP_MIXER_SLAVE_SEL 8 8 MVP_RATE_CONTROL 12 12 MVP_TERMINATION_CNTL_A 30 30 MVP_TERMINATION_CNTL_B 31 31 mmMVP_CONTROL2 0 0x1681 8 0 4294967295 MVP_DVOCNTL_MUX 16 16 MVP_FLOW_CONTROL_OUT_EN 20 20 MVP_MUXA_CLK_SEL 8 8 MVP_MUXB_CLK_SEL 12 12 MVP_MUX_DE_DVOCNTL0_SEL 0 0 MVP_MUX_DE_DVOCNTL2_SEL 4 4 MVP_SWAP_AB_IN_DC_DDR 28 28 MVP_SWAP_LOCK_OUT_EN 24 24 mmMVP_CONTROL3 0 0x168a 8 0 4294967295 MVP_DDR_SC_AB_SEL 4 4 MVP_DDR_SC_B_START_MODE 8 8 MVP_FLOW_CONTROL_CASCADE_EN 20 20 MVP_FLOW_CONTROL_IN_CAP 28 28 MVP_FLOW_CONTROL_OUT_FORCE_ONE 12 12 MVP_FLOW_CONTROL_OUT_FORCE_ZERO 16 16 MVP_RESET_IN_BETWEEN_FRAMES 0 0 MVP_SWAP_48BIT_EN 24 24 mmMVP_CRC_CNTL 0 0x1687 6 0 4294967295 MVP_CRC_BLUE_MASK 0 7 MVP_CRC_CONT_EN 29 29 MVP_CRC_EN 28 28 MVP_CRC_GREEN_MASK 8 15 MVP_CRC_RED_MASK 16 23 MVP_DC_DDR_CRC_EVEN_ODD_PIX_SEL 30 30 mmMVP_CRC_RESULT_BLUE_GREEN 0 0x1688 2 0 4294967295 MVP_CRC_BLUE_RESULT 0 15 MVP_CRC_GREEN_RESULT 16 31 mmMVP_CRC_RESULT_RED 0 0x1689 1 0 4294967295 MVP_CRC_RED_RESULT 0 15 mmMVP_DEBUG 0 0x168f 9 0 4294967295 MVP_DEBUG_BITS 8 31 MVP_DIS_FIX_AFR_AUTO_VSYNC_FLIP 5 5 MVP_DIS_FIX_AFR_MANUAL_HSYNC_FLIP 4 4 MVP_DIS_READ_POINTER_RESET_DELAY 7 7 MVP_EN_FIX_AFR_MANUAL_SWITCH_IN_SFR 6 6 MVP_FLOW_CONTROL_IN_EN 1 1 MVP_FLOW_CONTROL_IN_SEL 3 3 MVP_SWAP_LOCK_IN_EN 0 0 MVP_SWAP_LOCK_IN_SEL 2 2 mmMVP_FIFO_CONTROL 0 0x1682 3 0 4294967295 MVP_PAUSE_SLAVE_CNT 16 23 MVP_PAUSE_SLAVE_WM 8 15 MVP_STOP_SLAVE_WM 0 7 mmMVP_FIFO_STATUS 0 0x1683 9 0 4294967295 MVP_FIFO_ERROR_INT_STATUS 31 31 MVP_FIFO_ERROR_MASK 30 30 MVP_FIFO_LEVEL 0 7 MVP_FIFO_OVERFLOW_ACK 16 16 MVP_FIFO_OVERFLOW 8 8 MVP_FIFO_OVERFLOW_OCCURRED 12 12 MVP_FIFO_UNDERFLOW_ACK 28 28 MVP_FIFO_UNDERFLOW 20 20 MVP_FIFO_UNDERFLOW_OCCURRED 24 24 mmMVP_FLIP_LINE_NUM_INSERT 0 0x1ada 4 0 4294967295 MVP_FLIP_AUTO_ENABLE 30 30 MVP_FLIP_LINE_NUM_INSERT 8 22 MVP_FLIP_LINE_NUM_INSERT_MODE 0 1 MVP_FLIP_LINE_NUM_OFFSET 24 29 mmMVP_INBAND_CNTL_CAP 0 0x1685 3 0 4294967295 MVP_IGNOR_INBAND_CNTL 0 0 MVP_INBAND_CNTL_CHAR_CAP 8 31 MVP_PASSING_INBAND_CNTL_EN 4 4 mmMVP_RECEIVE_CNT_CNTL1 0 0x168b 3 0 4294967295 MVP_SLAVE_DATA_CHK_EN 31 31 MVP_SLAVE_LINE_ERROR_CNT 16 28 MVP_SLAVE_PIXEL_ERROR_CNT 0 12 mmMVP_RECEIVE_CNT_CNTL2 0 0x168c 2 0 4294967295 MVP_SLAVE_FRAME_ERROR_CNT 0 12 MVP_SLAVE_FRAME_ERROR_CNT_RESET 31 31 mmMVP_SLAVE_STATUS 0 0x1684 2 0 4294967295 MVP_SLAVE_LINES_PER_FRAME_RCVED 16 28 MVP_SLAVE_PIXELS_PER_LINE_RCVED 0 12 mmMVP_TEST_DEBUG_DATA 0 0x168e 1 0 4294967295 MVP_TEST_DEBUG_DATA 0 31 mmMVP_TEST_DEBUG_INDEX 0 0x168d 2 0 4294967295 MVP_TEST_DEBUG_INDEX 0 7 MVP_TEST_DEBUG_WRITE_EN 8 8 mmOUTPUT_CSC_C11_C12 0 0x1a3d 2 0 4294967295 OUTPUT_CSC_C11 0 15 OUTPUT_CSC_C12 16 31 mmOUTPUT_CSC_C13_C14 0 0x1a3e 2 0 4294967295 OUTPUT_CSC_C13 0 15 OUTPUT_CSC_C14 16 31 mmOUTPUT_CSC_C21_C22 0 0x1a3f 2 0 4294967295 OUTPUT_CSC_C21 0 15 OUTPUT_CSC_C22 16 31 mmOUTPUT_CSC_C23_C24 0 0x1a40 2 0 4294967295 OUTPUT_CSC_C23 0 15 OUTPUT_CSC_C24 16 31 mmOUTPUT_CSC_C31_C32 0 0x1a41 2 0 4294967295 OUTPUT_CSC_C31 0 15 OUTPUT_CSC_C32 16 31 mmOUTPUT_CSC_C33_C34 0 0x1a42 2 0 4294967295 OUTPUT_CSC_C33 0 15 OUTPUT_CSC_C34 16 31 mmOUTPUT_CSC_CONTROL 0 0x1a3c 2 0 4294967295 OUTPUT_CSC_GRPH_MODE 0 2 OUTPUT_CSC_OVL_MODE 4 6 mmOUT_ROUND_CONTROL 0 0x1a51 1 0 4294967295 OUT_ROUND_TRUNC_MODE 0 3 mmOVL_CONTROL1 0 0x1a1d 13 0 4294967295 OVL_ADDRESS_TRANSLATION_ENABLE 16 16 OVL_ARRAY_MODE 20 23 OVL_BANK_HEIGHT 11 12 OVL_BANK_WIDTH 6 7 OVL_COLOR_EXPANSION_MODE 24 24 OVL_DEPTH 0 1 OVL_FORMAT 8 10 OVL_MACRO_TILE_ASPECT 18 19 OVL_NUM_BANKS 2 3 OVL_PIPE_CONFIG 25 29 OVL_PRIVILEGED_ACCESS_ENABLE 17 17 OVL_TILE_SPLIT 13 15 OVL_Z 4 5 mmOVL_CONTROL2 0 0x1a1e 1 0 4294967295 OVL_HALF_RESOLUTION_ENABLE 0 0 mmOVL_DFQ_CONTROL 0 0x1a29 3 0 4294967295 OVL_DFQ_MIN_FREE_ENTRIES 8 10 OVL_DFQ_RESET 0 0 OVL_DFQ_SIZE 4 6 mmOVL_DFQ_STATUS 0 0x1a2a 4 0 4294967295 OVL_DFQ_NUM_ENTRIES 0 3 OVL_DFQ_RESET_ACK 9 9 OVL_DFQ_RESET_FLAG 8 8 OVL_SECONDARY_DFQ_NUM_ENTRIES 4 7 mmOVL_ENABLE 0 0x1a1c 2 0 4294967295 OVL_ENABLE 0 0 OVLSCL_EN 8 8 mmOVL_END 0 0x1a26 2 0 4294967295 OVL_X_END 16 30 OVL_Y_END 0 14 mmOVL_PITCH 0 0x1a21 1 0 4294967295 OVL_PITCH 0 14 mmOVLSCL_EDGE_PIXEL_CNTL 0 0x1a2c 4 0 4294967295 OVLSCL_BLACK_COLOR_BCB 0 9 OVLSCL_BLACK_COLOR_GY 10 19 OVLSCL_BLACK_COLOR_RCR 20 29 OVLSCL_EDGE_PIXEL_SEL 31 31 mmOVL_SECONDARY_SURFACE_ADDRESS 0 0x1a92 2 0 4294967295 OVL_SECONDARY_DFQ_ENABLE 0 0 OVL_SECONDARY_SURFACE_ADDRESS 8 31 mmOVL_SECONDARY_SURFACE_ADDRESS_HIGH 0 0x1a94 1 0 4294967295 OVL_SECONDARY_SURFACE_ADDRESS_HIGH 0 7 mmOVL_START 0 0x1a25 2 0 4294967295 OVL_X_START 16 29 OVL_Y_START 0 13 mmOVL_STEREOSYNC_FLIP 0 0x1a93 5 0 4294967295 OVL_PRIMARY_SURFACE_PENDING 16 16 OVL_SECONDARY_SURFACE_PENDING 17 17 OVL_STEREOSYNC_FLIP_EN 0 0 OVL_STEREOSYNC_FLIP_MODE 8 9 OVL_STEREOSYNC_SELECT_DISABLE 28 28 mmOVL_SURFACE_ADDRESS 0 0x1a20 2 0 4294967295 OVL_DFQ_ENABLE 0 0 OVL_SURFACE_ADDRESS 8 31 mmOVL_SURFACE_ADDRESS_HIGH 0 0x1a22 1 0 4294967295 OVL_SURFACE_ADDRESS_HIGH 0 7 mmOVL_SURFACE_ADDRESS_HIGH_INUSE 0 0x1a2b 1 0 4294967295 OVL_SURFACE_ADDRESS_HIGH_INUSE 0 7 mmOVL_SURFACE_ADDRESS_INUSE 0 0x1a28 1 0 4294967295 OVL_SURFACE_ADDRESS_INUSE 8 31 mmOVL_SURFACE_OFFSET_X 0 0x1a23 1 0 4294967295 OVL_SURFACE_OFFSET_X 0 13 mmOVL_SURFACE_OFFSET_Y 0 0x1a24 1 0 4294967295 OVL_SURFACE_OFFSET_Y 0 13 mmOVL_SWAP_CNTL 0 0x1a1f 5 0 4294967295 OVL_ALPHA_CROSSBAR 10 11 OVL_BLUE_CROSSBAR 8 9 OVL_ENDIAN_SWAP 0 1 OVL_GREEN_CROSSBAR 6 7 OVL_RED_CROSSBAR 4 5 mmOVL_UPDATE 0 0x1a27 4 0 4294967295 OVL_DISABLE_MULTIPLE_UPDATE 24 24 OVL_UPDATE_LOCK 16 16 OVL_UPDATE_PENDING 0 0 OVL_UPDATE_TAKEN 1 1 mmPHY_AUX_CNTL 0 0x197f 3 0 4294967295 AUX_PAD_RXSEL 16 16 AUX_PAD_SLEWN 12 12 AUX_PAD_WAKE 14 14 mmPIPE0_ARBITRATION_CONTROL3 0 0x2fa 1 0 4294967295 EFFICIENCY_WEIGHT 0 15 mmPIPE0_DMIF_BUFFER_CONTROL 0 0x328 2 0 4294967295 DMIF_BUFFERS_ALLOCATED 0 2 DMIF_BUFFERS_ALLOCATION_COMPLETED 4 4 mmPIPE0_MAX_REQUESTS 0 0x302 1 0 4294967295 MAX_REQUESTS 0 9 mmPIPE0_PG_CONFIG 0 0x1760 1 0 4294967295 PIPE0_POWER_FORCEON 0 0 mmPIPE0_PG_ENABLE 0 0x1761 1 0 4294967295 PIPE0_POWER_GATE 0 0 mmPIPE0_PG_STATUS 0 0x1762 4 0 4294967295 PIPE0_DESIRED_PWR_STATE 28 28 PIPE0_PGFSM_PWR_STATUS 30 31 PIPE0_PGFSM_READ_DATA 0 23 PIPE0_REQUESTED_PWR_STATE 29 29 mmPIPE1_ARBITRATION_CONTROL3 0 0x2fb 1 0 4294967295 EFFICIENCY_WEIGHT 0 15 mmPIPE1_DMIF_BUFFER_CONTROL 0 0x330 2 0 4294967295 DMIF_BUFFERS_ALLOCATED 0 2 DMIF_BUFFERS_ALLOCATION_COMPLETED 4 4 mmPIPE1_MAX_REQUESTS 0 0x303 1 0 4294967295 MAX_REQUESTS 0 9 mmPIPE1_PG_CONFIG 0 0x1764 1 0 4294967295 PIPE1_POWER_FORCEON 0 0 mmPIPE1_PG_ENABLE 0 0x1765 1 0 4294967295 PIPE1_POWER_GATE 0 0 mmPIPE1_PG_STATUS 0 0x1766 4 0 4294967295 PIPE1_DESIRED_PWR_STATE 28 28 PIPE1_PGFSM_PWR_STATUS 30 31 PIPE1_PGFSM_READ_DATA 0 23 PIPE1_REQUESTED_PWR_STATE 29 29 mmPIPE2_ARBITRATION_CONTROL3 0 0x2fc 1 0 4294967295 EFFICIENCY_WEIGHT 0 15 mmPIPE2_DMIF_BUFFER_CONTROL 0 0x338 2 0 4294967295 DMIF_BUFFERS_ALLOCATED 0 2 DMIF_BUFFERS_ALLOCATION_COMPLETED 4 4 mmPIPE2_MAX_REQUESTS 0 0x304 1 0 4294967295 MAX_REQUESTS 0 9 mmPIPE2_PG_CONFIG 0 0x1768 1 0 4294967295 PIPE2_POWER_FORCEON 0 0 mmPIPE2_PG_ENABLE 0 0x1769 1 0 4294967295 PIPE2_POWER_GATE 0 0 mmPIPE2_PG_STATUS 0 0x176a 4 0 4294967295 PIPE2_DESIRED_PWR_STATE 28 28 PIPE2_PGFSM_PWR_STATUS 30 31 PIPE2_PGFSM_READ_DATA 0 23 PIPE2_REQUESTED_PWR_STATE 29 29 mmPIPE3_ARBITRATION_CONTROL3 0 0x2fd 1 0 4294967295 EFFICIENCY_WEIGHT 0 15 mmPIPE3_DMIF_BUFFER_CONTROL 0 0x340 2 0 4294967295 DMIF_BUFFERS_ALLOCATED 0 2 DMIF_BUFFERS_ALLOCATION_COMPLETED 4 4 mmPIPE3_MAX_REQUESTS 0 0x305 1 0 4294967295 MAX_REQUESTS 0 9 mmPIPE3_PG_CONFIG 0 0x176c 1 0 4294967295 PIPE3_POWER_FORCEON 0 0 mmPIPE3_PG_ENABLE 0 0x176d 1 0 4294967295 PIPE3_POWER_GATE 0 0 mmPIPE3_PG_STATUS 0 0x176e 4 0 4294967295 PIPE3_DESIRED_PWR_STATE 28 28 PIPE3_PGFSM_PWR_STATUS 30 31 PIPE3_PGFSM_READ_DATA 0 23 PIPE3_REQUESTED_PWR_STATE 29 29 mmPIPE4_ARBITRATION_CONTROL3 0 0x2fe 1 0 4294967295 EFFICIENCY_WEIGHT 0 15 mmPIPE4_DMIF_BUFFER_CONTROL 0 0x348 2 0 4294967295 DMIF_BUFFERS_ALLOCATED 0 2 DMIF_BUFFERS_ALLOCATION_COMPLETED 4 4 mmPIPE4_MAX_REQUESTS 0 0x306 1 0 4294967295 MAX_REQUESTS 0 9 mmPIPE4_PG_CONFIG 0 0x1770 1 0 4294967295 PIPE4_POWER_FORCEON 0 0 mmPIPE4_PG_ENABLE 0 0x1771 1 0 4294967295 PIPE4_POWER_GATE 0 0 mmPIPE4_PG_STATUS 0 0x1772 4 0 4294967295 PIPE4_DESIRED_PWR_STATE 28 28 PIPE4_PGFSM_PWR_STATUS 30 31 PIPE4_PGFSM_READ_DATA 0 23 PIPE4_REQUESTED_PWR_STATE 29 29 mmPIPE5_ARBITRATION_CONTROL3 0 0x2ff 1 0 4294967295 EFFICIENCY_WEIGHT 0 15 mmPIPE5_DMIF_BUFFER_CONTROL 0 0x350 2 0 4294967295 DMIF_BUFFERS_ALLOCATED 0 2 DMIF_BUFFERS_ALLOCATION_COMPLETED 4 4 mmPIPE5_MAX_REQUESTS 0 0x307 1 0 4294967295 MAX_REQUESTS 0 9 mmPIPE5_PG_CONFIG 0 0x1774 1 0 4294967295 PIPE5_POWER_FORCEON 0 0 mmPIPE5_PG_ENABLE 0 0x1775 1 0 4294967295 PIPE5_POWER_GATE 0 0 mmPIPE5_PG_STATUS 0 0x1776 4 0 4294967295 PIPE5_DESIRED_PWR_STATE 28 28 PIPE5_PGFSM_PWR_STATUS 30 31 PIPE5_PGFSM_READ_DATA 0 23 PIPE5_REQUESTED_PWR_STATE 29 29 mmPIXCLK0_RESYNC_CNTL 0 0x13a 2 0 4294967295 DCCG_DEEP_COLOR_CNTL0 4 5 PIXCLK0_RESYNC_ENABLE 0 0 mmPIXCLK1_RESYNC_CNTL 0 0x138 2 0 4294967295 DCCG_DEEP_COLOR_CNTL1 4 5 PIXCLK1_RESYNC_ENABLE 0 0 mmPIXCLK2_RESYNC_CNTL 0 0x139 2 0 4294967295 DCCG_DEEP_COLOR_CNTL2 4 5 PIXCLK2_RESYNC_ENABLE 0 0 mmPLL_ANALOG 0 0x1708 5 0 4294967295 PLL_CAL_MODE 0 4 PLL_CP 8 11 PLL_IBIAS 24 31 PLL_LF_MODE 12 20 PLL_PFD_PULSE_SEL 5 6 mmPLL_CNTL 0 0x1707 17 0 4294967295 PLL_ANTIGLITCH_RESETB 7 7 PLL_ANTI_GLITCH_RESET 13 13 PLL_BYPASS_CAL 2 2 PLL_CAL_BYPASS_REFDIV 10 10 PLL_CALIB_DONE 20 20 PLL_CALREF 8 9 PLL_DIG_SPARE 26 31 PLL_LOCKED 21 21 PLL_LOCK_FREQ_SEL 19 19 PLL_PCIE_REFCLK_SEL 6 6 PLL_POST_DIV_SRC 3 3 PLL_POWER_DOWN 1 1 PLL_REFCLK_SEL 11 12 PLL_REF_DIV_SRC 16 18 PLL_RESET 0 0 PLL_TIMING_MODE_STATUS 24 25 PLL_VCOREF 4 5 mmPLL_DEBUG_CNTL 0 0x170b 3 0 4294967295 PLL_DEBUG_CLK_SEL 8 11 PLL_DEBUG_MUXOUT_SEL 4 7 PLL_DEBUG_SIGNALS_ENABLE 0 0 mmPLL_DISPCLK_CURRENT_DTO_PHASE 0 0x170f 1 0 4294967295 PLL_DISPCLK_CURRENT_DTO_PHASE 0 8 mmPLL_DISPCLK_DTO_CNTL 0 0x170e 7 0 4294967295 PLL_DISPCLK_DTO_COMPL_DELAY 24 31 PLL_DISPCLK_DTO_DIS 16 16 PLL_DISPCLK_DTO_PHASE 0 8 PLL_DISPCLK_DTO_UPDATE_ACK 22 22 PLL_DISPCLK_DTO_UPDATE_MODE 17 18 PLL_DISPCLK_DTO_UPDATE_PENDING 20 20 PLL_DISPCLK_DTO_UPDATE_REQ 21 21 mmPLL_DS_CNTL 0 0x1705 4 0 4294967295 PLL_DS_FRAC 0 15 PLL_DS_MODE 18 18 PLL_DS_ORDER 16 17 PLL_DS_PRBS_EN 19 19 mmPLL_FB_DIV 0 0x1701 3 0 4294967295 PLL_FB_DIV_FRACTION_CNTL 4 5 PLL_FB_DIV_FRACTION 0 3 PLL_FB_DIV 16 27 mmPLL_IDCLK_CNTL 0 0x1706 8 0 4294967295 PLL_DIFF_POST_DIV 16 19 PLL_DIFF_POST_DIV_RESET 8 8 PLL_DIFF_POST_DIV_SELECT 12 12 PLL_LTDP_IDCLK_DIFF_EN 1 1 PLL_LTDP_IDCLK_EN 0 0 PLL_TMDP_IDCLK_DIFF_EN 3 3 PLL_TMDP_IDCLK_EN 2 2 PLL_UNIPHY_IDCLK_DIFF_EN 4 4 mmPLL_POST_DIV 0 0x1702 5 0 4294967295 PLL_POST_DIV1P5_DISPCLK 7 7 PLL_POST_DIV1P5_DPREFCLK 15 15 PLL_POST_DIV_DVOCLK 8 14 PLL_POST_DIV_IDCLK 16 22 PLL_POST_DIV_PIXCLK 0 6 mmPLL_REF_DIV 0 0x1700 2 0 4294967295 PLL_CALIBRATION_REF_DIV 12 15 PLL_REF_DIV 0 9 mmPLL_SS_AMOUNT_DSFRAC 0 0x1703 1 0 4294967295 PLL_SS_AMOUNT_DSFRAC 0 15 mmPLL_SS_CNTL 0 0x1704 5 0 4294967295 PLL_SS_AMOUNT_FBDIV 0 7 PLL_SS_AMOUNT_NFRAC_SLIP 8 11 PLL_SS_EN 12 12 PLL_SS_MODE 13 13 PLL_SS_STEP_SIZE_DSFRAC 16 31 mmPLL_UNLOCK_DETECT_CNTL 0 0x170a 5 0 4294967295 PLL_UNLOCK_DET_COUNT 4 6 PLL_UNLOCK_DETECT_ENABLE 0 0 PLL_UNLOCK_DET_RES100_SELECT 1 1 PLL_UNLOCK_STICKY_CLEAR 3 3 PLL_UNLOCK_STICKY_STATUS 2 2 mmPLL_UPDATE_CNTL 0 0x170d 3 0 4294967295 PLL_AUTO_RESET_DISABLE 16 16 PLL_UPDATE_PENDING 0 0 PLL_UPDATE_POINT 8 8 mmPLL_UPDATE_LOCK 0 0x170c 1 0 4294967295 PLL_UPDATE_LOCK 0 0 mmPLL_VREG_CNTL 0 0x1709 3 0 4294967295 PLL_VREF_SEL 26 26 PLL_VREG_BIAS 28 31 PLL_VREG_CNTL 0 19 mmPRESCALE_GRPH_CONTROL 0 0x1a2d 5 0 4294967295 GRPH_PRESCALE_B_SIGN 3 3 GRPH_PRESCALE_BYPASS 4 4 GRPH_PRESCALE_G_SIGN 2 2 GRPH_PRESCALE_R_SIGN 1 1 GRPH_PRESCALE_SELECT 0 0 mmPRESCALE_OVL_CONTROL 0 0x1a31 5 0 4294967295 OVL_PRESCALE_BYPASS 4 4 OVL_PRESCALE_CB_SIGN 1 1 OVL_PRESCALE_CR_SIGN 3 3 OVL_PRESCALE_SELECT 0 0 OVL_PRESCALE_Y_SIGN 2 2 mmPRESCALE_VALUES_GRPH_B 0 0x1a30 2 0 4294967295 GRPH_PRESCALE_BIAS_B 0 15 GRPH_PRESCALE_SCALE_B 16 31 mmPRESCALE_VALUES_GRPH_G 0 0x1a2f 2 0 4294967295 GRPH_PRESCALE_BIAS_G 0 15 GRPH_PRESCALE_SCALE_G 16 31 mmPRESCALE_VALUES_GRPH_R 0 0x1a2e 2 0 4294967295 GRPH_PRESCALE_BIAS_R 0 15 GRPH_PRESCALE_SCALE_R 16 31 mmPRESCALE_VALUES_OVL_CB 0 0x1a32 2 0 4294967295 OVL_PRESCALE_BIAS_CB 0 15 OVL_PRESCALE_SCALE_CB 16 31 mmPRESCALE_VALUES_OVL_CR 0 0x1a34 2 0 4294967295 OVL_PRESCALE_BIAS_CR 0 15 OVL_PRESCALE_SCALE_CR 16 31 mmPRESCALE_VALUES_OVL_Y 0 0x1a33 2 0 4294967295 OVL_PRESCALE_BIAS_Y 0 15 OVL_PRESCALE_SCALE_Y 16 31 mmREGAMMA_CNTLA_END_CNTL1 0 0x1aa6 1 0 4294967295 REGAMMA_CNTLA_EXP_REGION_END 0 15 mmREGAMMA_CNTLA_END_CNTL2 0 0x1aa7 2 0 4294967295 REGAMMA_CNTLA_EXP_REGION_END_BASE 16 31 REGAMMA_CNTLA_EXP_REGION_END_SLOPE 0 15 mmREGAMMA_CNTLA_REGION_0_1 0 0x1aa8 4 0 4294967295 REGAMMA_CNTLA_EXP_REGION0_LUT_OFFSET 0 8 REGAMMA_CNTLA_EXP_REGION0_NUM_SEGMENTS 12 14 REGAMMA_CNTLA_EXP_REGION1_LUT_OFFSET 16 24 REGAMMA_CNTLA_EXP_REGION1_NUM_SEGMENTS 28 30 mmREGAMMA_CNTLA_REGION_10_11 0 0x1aad 4 0 4294967295 REGAMMA_CNTLA_EXP_REGION10_LUT_OFFSET 0 8 REGAMMA_CNTLA_EXP_REGION10_NUM_SEGMENTS 12 14 REGAMMA_CNTLA_EXP_REGION11_LUT_OFFSET 16 24 REGAMMA_CNTLA_EXP_REGION11_NUM_SEGMENTS 28 30 mmREGAMMA_CNTLA_REGION_12_13 0 0x1aae 4 0 4294967295 REGAMMA_CNTLA_EXP_REGION12_LUT_OFFSET 0 8 REGAMMA_CNTLA_EXP_REGION12_NUM_SEGMENTS 12 14 REGAMMA_CNTLA_EXP_REGION13_LUT_OFFSET 16 24 REGAMMA_CNTLA_EXP_REGION13_NUM_SEGMENTS 28 30 mmREGAMMA_CNTLA_REGION_14_15 0 0x1aaf 4 0 4294967295 REGAMMA_CNTLA_EXP_REGION14_LUT_OFFSET 0 8 REGAMMA_CNTLA_EXP_REGION14_NUM_SEGMENTS 12 14 REGAMMA_CNTLA_EXP_REGION15_LUT_OFFSET 16 24 REGAMMA_CNTLA_EXP_REGION15_NUM_SEGMENTS 28 30 mmREGAMMA_CNTLA_REGION_2_3 0 0x1aa9 4 0 4294967295 REGAMMA_CNTLA_EXP_REGION2_LUT_OFFSET 0 8 REGAMMA_CNTLA_EXP_REGION2_NUM_SEGMENTS 12 14 REGAMMA_CNTLA_EXP_REGION3_LUT_OFFSET 16 24 REGAMMA_CNTLA_EXP_REGION3_NUM_SEGMENTS 28 30 mmREGAMMA_CNTLA_REGION_4_5 0 0x1aaa 4 0 4294967295 REGAMMA_CNTLA_EXP_REGION4_LUT_OFFSET 0 8 REGAMMA_CNTLA_EXP_REGION4_NUM_SEGMENTS 12 14 REGAMMA_CNTLA_EXP_REGION5_LUT_OFFSET 16 24 REGAMMA_CNTLA_EXP_REGION5_NUM_SEGMENTS 28 30 mmREGAMMA_CNTLA_REGION_6_7 0 0x1aab 4 0 4294967295 REGAMMA_CNTLA_EXP_REGION6_LUT_OFFSET 0 8 REGAMMA_CNTLA_EXP_REGION6_NUM_SEGMENTS 12 14 REGAMMA_CNTLA_EXP_REGION7_LUT_OFFSET 16 24 REGAMMA_CNTLA_EXP_REGION7_NUM_SEGMENTS 28 30 mmREGAMMA_CNTLA_REGION_8_9 0 0x1aac 4 0 4294967295 REGAMMA_CNTLA_EXP_REGION8_LUT_OFFSET 0 8 REGAMMA_CNTLA_EXP_REGION8_NUM_SEGMENTS 12 14 REGAMMA_CNTLA_EXP_REGION9_LUT_OFFSET 16 24 REGAMMA_CNTLA_EXP_REGION9_NUM_SEGMENTS 28 30 mmREGAMMA_CNTLA_SLOPE_CNTL 0 0x1aa5 1 0 4294967295 REGAMMA_CNTLA_EXP_REGION_LINEAR_SLOPE 0 17 mmREGAMMA_CNTLA_START_CNTL 0 0x1aa4 2 0 4294967295 REGAMMA_CNTLA_EXP_REGION_START 0 17 REGAMMA_CNTLA_EXP_REGION_START_SEGMENT 20 26 mmREGAMMA_CNTLB_END_CNTL1 0 0x1ab2 1 0 4294967295 REGAMMA_CNTLB_EXP_REGION_END 0 15 mmREGAMMA_CNTLB_END_CNTL2 0 0x1ab3 2 0 4294967295 REGAMMA_CNTLB_EXP_REGION_END_BASE 16 31 REGAMMA_CNTLB_EXP_REGION_END_SLOPE 0 15 mmREGAMMA_CNTLB_REGION_0_1 0 0x1ab4 4 0 4294967295 REGAMMA_CNTLB_EXP_REGION0_LUT_OFFSET 0 8 REGAMMA_CNTLB_EXP_REGION0_NUM_SEGMENTS 12 14 REGAMMA_CNTLB_EXP_REGION1_LUT_OFFSET 16 24 REGAMMA_CNTLB_EXP_REGION1_NUM_SEGMENTS 28 30 mmREGAMMA_CNTLB_REGION_10_11 0 0x1ab9 4 0 4294967295 REGAMMA_CNTLB_EXP_REGION10_LUT_OFFSET 0 8 REGAMMA_CNTLB_EXP_REGION10_NUM_SEGMENTS 12 14 REGAMMA_CNTLB_EXP_REGION11_LUT_OFFSET 16 24 REGAMMA_CNTLB_EXP_REGION11_NUM_SEGMENTS 28 30 mmREGAMMA_CNTLB_REGION_12_13 0 0x1aba 4 0 4294967295 REGAMMA_CNTLB_EXP_REGION12_LUT_OFFSET 0 8 REGAMMA_CNTLB_EXP_REGION12_NUM_SEGMENTS 12 14 REGAMMA_CNTLB_EXP_REGION13_LUT_OFFSET 16 24 REGAMMA_CNTLB_EXP_REGION13_NUM_SEGMENTS 28 30 mmREGAMMA_CNTLB_REGION_14_15 0 0x1abb 4 0 4294967295 REGAMMA_CNTLB_EXP_REGION14_LUT_OFFSET 0 8 REGAMMA_CNTLB_EXP_REGION14_NUM_SEGMENTS 12 14 REGAMMA_CNTLB_EXP_REGION15_LUT_OFFSET 16 24 REGAMMA_CNTLB_EXP_REGION15_NUM_SEGMENTS 28 30 mmREGAMMA_CNTLB_REGION_2_3 0 0x1ab5 4 0 4294967295 REGAMMA_CNTLB_EXP_REGION2_LUT_OFFSET 0 8 REGAMMA_CNTLB_EXP_REGION2_NUM_SEGMENTS 12 14 REGAMMA_CNTLB_EXP_REGION3_LUT_OFFSET 16 24 REGAMMA_CNTLB_EXP_REGION3_NUM_SEGMENTS 28 30 mmREGAMMA_CNTLB_REGION_4_5 0 0x1ab6 4 0 4294967295 REGAMMA_CNTLB_EXP_REGION4_LUT_OFFSET 0 8 REGAMMA_CNTLB_EXP_REGION4_NUM_SEGMENTS 12 14 REGAMMA_CNTLB_EXP_REGION5_LUT_OFFSET 16 24 REGAMMA_CNTLB_EXP_REGION5_NUM_SEGMENTS 28 30 mmREGAMMA_CNTLB_REGION_6_7 0 0x1ab7 4 0 4294967295 REGAMMA_CNTLB_EXP_REGION6_LUT_OFFSET 0 8 REGAMMA_CNTLB_EXP_REGION6_NUM_SEGMENTS 12 14 REGAMMA_CNTLB_EXP_REGION7_LUT_OFFSET 16 24 REGAMMA_CNTLB_EXP_REGION7_NUM_SEGMENTS 28 30 mmREGAMMA_CNTLB_REGION_8_9 0 0x1ab8 4 0 4294967295 REGAMMA_CNTLB_EXP_REGION8_LUT_OFFSET 0 8 REGAMMA_CNTLB_EXP_REGION8_NUM_SEGMENTS 12 14 REGAMMA_CNTLB_EXP_REGION9_LUT_OFFSET 16 24 REGAMMA_CNTLB_EXP_REGION9_NUM_SEGMENTS 28 30 mmREGAMMA_CNTLB_SLOPE_CNTL 0 0x1ab1 1 0 4294967295 REGAMMA_CNTLB_EXP_REGION_LINEAR_SLOPE 0 17 mmREGAMMA_CNTLB_START_CNTL 0 0x1ab0 2 0 4294967295 REGAMMA_CNTLB_EXP_REGION_START 0 17 REGAMMA_CNTLB_EXP_REGION_START_SEGMENT 20 26 mmREGAMMA_CONTROL 0 0x1aa0 2 0 4294967295 GRPH_REGAMMA_MODE 0 2 OVL_REGAMMA_MODE 4 6 mmREGAMMA_LUT_DATA 0 0x1aa2 1 0 4294967295 REGAMMA_LUT_DATA 0 18 mmREGAMMA_LUT_INDEX 0 0x1aa1 1 0 4294967295 REGAMMA_LUT_INDEX 0 8 mmREGAMMA_LUT_WRITE_EN_MASK 0 0x1aa3 1 0 4294967295 REGAMMA_LUT_WRITE_EN_MASK 0 2 mmSCL0_EXT_OVERSCAN_LEFT_RIGHT 0 0x1b5e 0 0 4294967295 mmSCL0_EXT_OVERSCAN_TOP_BOTTOM 0 0x1b5f 0 0 4294967295 mmSCL0_SCL_ALU_CONTROL 0 0x1b54 0 0 4294967295 mmSCL0_SCL_AUTOMATIC_MODE_CONTROL 0 0x1b47 0 0 4294967295 mmSCL0_SCL_BYPASS_CONTROL 0 0x1b45 0 0 4294967295 mmSCL0_SCL_COEF_RAM_CONFLICT_STATUS 0 0x1b55 0 0 4294967295 mmSCL0_SCL_COEF_RAM_SELECT 0 0x1b40 0 0 4294967295 mmSCL0_SCL_COEF_RAM_TAP_DATA 0 0x1b41 0 0 4294967295 mmSCL0_SCL_CONTROL 0 0x1b44 0 0 4294967295 mmSCL0_SCL_DEBUG 0 0x1b6a 0 0 4294967295 mmSCL0_SCL_DEBUG2 0 0x1b69 0 0 4294967295 mmSCL0_SCL_F_SHARP_CONTROL 0 0x1b53 0 0 4294967295 mmSCL0_SCL_HORZ_FILTER_CONTROL 0 0x1b4a 0 0 4294967295 mmSCL0_SCL_HORZ_FILTER_SCALE_RATIO 0 0x1b4b 0 0 4294967295 mmSCL0_SCL_MANUAL_REPLICATE_CONTROL 0 0x1b46 0 0 4294967295 mmSCL0_SCL_MODE_CHANGE_DET1 0 0x1b60 0 0 4294967295 mmSCL0_SCL_MODE_CHANGE_DET2 0 0x1b61 0 0 4294967295 mmSCL0_SCL_MODE_CHANGE_DET3 0 0x1b62 0 0 4294967295 mmSCL0_SCL_MODE_CHANGE_MASK 0 0x1b63 0 0 4294967295 mmSCL0_SCL_TAP_CONTROL 0 0x1b43 0 0 4294967295 mmSCL0_SCL_TEST_DEBUG_DATA 0 0x1b6c 0 0 4294967295 mmSCL0_SCL_TEST_DEBUG_INDEX 0 0x1b6b 0 0 4294967295 mmSCL0_SCL_UPDATE 0 0x1b51 0 0 4294967295 mmSCL0_SCL_VERT_FILTER_CONTROL 0 0x1b4e 0 0 4294967295 mmSCL0_SCL_VERT_FILTER_INIT 0 0x1b50 0 0 4294967295 mmSCL0_SCL_VERT_FILTER_INIT_BOT 0 0x1b57 0 0 4294967295 mmSCL0_SCL_VERT_FILTER_SCALE_RATIO 0 0x1b4f 0 0 4294967295 mmSCL0_VIEWPORT_SIZE 0 0x1b5d 0 0 4294967295 mmSCL0_VIEWPORT_START 0 0x1b5c 0 0 4294967295 mmSCL1_EXT_OVERSCAN_LEFT_RIGHT 0 0x1e5e 0 0 4294967295 mmSCL1_EXT_OVERSCAN_TOP_BOTTOM 0 0x1e5f 0 0 4294967295 mmSCL1_SCL_ALU_CONTROL 0 0x1e54 0 0 4294967295 mmSCL1_SCL_AUTOMATIC_MODE_CONTROL 0 0x1e47 0 0 4294967295 mmSCL1_SCL_BYPASS_CONTROL 0 0x1e45 0 0 4294967295 mmSCL1_SCL_COEF_RAM_CONFLICT_STATUS 0 0x1e55 0 0 4294967295 mmSCL1_SCL_COEF_RAM_SELECT 0 0x1e40 0 0 4294967295 mmSCL1_SCL_COEF_RAM_TAP_DATA 0 0x1e41 0 0 4294967295 mmSCL1_SCL_CONTROL 0 0x1e44 0 0 4294967295 mmSCL1_SCL_DEBUG 0 0x1e6a 0 0 4294967295 mmSCL1_SCL_DEBUG2 0 0x1e69 0 0 4294967295 mmSCL1_SCL_F_SHARP_CONTROL 0 0x1e53 0 0 4294967295 mmSCL1_SCL_HORZ_FILTER_CONTROL 0 0x1e4a 0 0 4294967295 mmSCL1_SCL_HORZ_FILTER_SCALE_RATIO 0 0x1e4b 0 0 4294967295 mmSCL1_SCL_MANUAL_REPLICATE_CONTROL 0 0x1e46 0 0 4294967295 mmSCL1_SCL_MODE_CHANGE_DET1 0 0x1e60 0 0 4294967295 mmSCL1_SCL_MODE_CHANGE_DET2 0 0x1e61 0 0 4294967295 mmSCL1_SCL_MODE_CHANGE_DET3 0 0x1e62 0 0 4294967295 mmSCL1_SCL_MODE_CHANGE_MASK 0 0x1e63 0 0 4294967295 mmSCL1_SCL_TAP_CONTROL 0 0x1e43 0 0 4294967295 mmSCL1_SCL_TEST_DEBUG_DATA 0 0x1e6c 0 0 4294967295 mmSCL1_SCL_TEST_DEBUG_INDEX 0 0x1e6b 0 0 4294967295 mmSCL1_SCL_UPDATE 0 0x1e51 0 0 4294967295 mmSCL1_SCL_VERT_FILTER_CONTROL 0 0x1e4e 0 0 4294967295 mmSCL1_SCL_VERT_FILTER_INIT 0 0x1e50 0 0 4294967295 mmSCL1_SCL_VERT_FILTER_INIT_BOT 0 0x1e57 0 0 4294967295 mmSCL1_SCL_VERT_FILTER_SCALE_RATIO 0 0x1e4f 0 0 4294967295 mmSCL1_VIEWPORT_SIZE 0 0x1e5d 0 0 4294967295 mmSCL1_VIEWPORT_START 0 0x1e5c 0 0 4294967295 mmSCL2_EXT_OVERSCAN_LEFT_RIGHT 0 0x415e 0 0 4294967295 mmSCL2_EXT_OVERSCAN_TOP_BOTTOM 0 0x415f 0 0 4294967295 mmSCL2_SCL_ALU_CONTROL 0 0x4154 0 0 4294967295 mmSCL2_SCL_AUTOMATIC_MODE_CONTROL 0 0x4147 0 0 4294967295 mmSCL2_SCL_BYPASS_CONTROL 0 0x4145 0 0 4294967295 mmSCL2_SCL_COEF_RAM_CONFLICT_STATUS 0 0x4155 0 0 4294967295 mmSCL2_SCL_COEF_RAM_SELECT 0 0x4140 0 0 4294967295 mmSCL2_SCL_COEF_RAM_TAP_DATA 0 0x4141 0 0 4294967295 mmSCL2_SCL_CONTROL 0 0x4144 0 0 4294967295 mmSCL2_SCL_DEBUG 0 0x416a 0 0 4294967295 mmSCL2_SCL_DEBUG2 0 0x4169 0 0 4294967295 mmSCL2_SCL_F_SHARP_CONTROL 0 0x4153 0 0 4294967295 mmSCL2_SCL_HORZ_FILTER_CONTROL 0 0x414a 0 0 4294967295 mmSCL2_SCL_HORZ_FILTER_SCALE_RATIO 0 0x414b 0 0 4294967295 mmSCL2_SCL_MANUAL_REPLICATE_CONTROL 0 0x4146 0 0 4294967295 mmSCL2_SCL_MODE_CHANGE_DET1 0 0x4160 0 0 4294967295 mmSCL2_SCL_MODE_CHANGE_DET2 0 0x4161 0 0 4294967295 mmSCL2_SCL_MODE_CHANGE_DET3 0 0x4162 0 0 4294967295 mmSCL2_SCL_MODE_CHANGE_MASK 0 0x4163 0 0 4294967295 mmSCL2_SCL_TAP_CONTROL 0 0x4143 0 0 4294967295 mmSCL2_SCL_TEST_DEBUG_DATA 0 0x416c 0 0 4294967295 mmSCL2_SCL_TEST_DEBUG_INDEX 0 0x416b 0 0 4294967295 mmSCL2_SCL_UPDATE 0 0x4151 0 0 4294967295 mmSCL2_SCL_VERT_FILTER_CONTROL 0 0x414e 0 0 4294967295 mmSCL2_SCL_VERT_FILTER_INIT 0 0x4150 0 0 4294967295 mmSCL2_SCL_VERT_FILTER_INIT_BOT 0 0x4157 0 0 4294967295 mmSCL2_SCL_VERT_FILTER_SCALE_RATIO 0 0x414f 0 0 4294967295 mmSCL2_VIEWPORT_SIZE 0 0x415d 0 0 4294967295 mmSCL2_VIEWPORT_START 0 0x415c 0 0 4294967295 mmSCL3_EXT_OVERSCAN_LEFT_RIGHT 0 0x445e 0 0 4294967295 mmSCL3_EXT_OVERSCAN_TOP_BOTTOM 0 0x445f 0 0 4294967295 mmSCL3_SCL_ALU_CONTROL 0 0x4454 0 0 4294967295 mmSCL3_SCL_AUTOMATIC_MODE_CONTROL 0 0x4447 0 0 4294967295 mmSCL3_SCL_BYPASS_CONTROL 0 0x4445 0 0 4294967295 mmSCL3_SCL_COEF_RAM_CONFLICT_STATUS 0 0x4455 0 0 4294967295 mmSCL3_SCL_COEF_RAM_SELECT 0 0x4440 0 0 4294967295 mmSCL3_SCL_COEF_RAM_TAP_DATA 0 0x4441 0 0 4294967295 mmSCL3_SCL_CONTROL 0 0x4444 0 0 4294967295 mmSCL3_SCL_DEBUG 0 0x446a 0 0 4294967295 mmSCL3_SCL_DEBUG2 0 0x4469 0 0 4294967295 mmSCL3_SCL_F_SHARP_CONTROL 0 0x4453 0 0 4294967295 mmSCL3_SCL_HORZ_FILTER_CONTROL 0 0x444a 0 0 4294967295 mmSCL3_SCL_HORZ_FILTER_SCALE_RATIO 0 0x444b 0 0 4294967295 mmSCL3_SCL_MANUAL_REPLICATE_CONTROL 0 0x4446 0 0 4294967295 mmSCL3_SCL_MODE_CHANGE_DET1 0 0x4460 0 0 4294967295 mmSCL3_SCL_MODE_CHANGE_DET2 0 0x4461 0 0 4294967295 mmSCL3_SCL_MODE_CHANGE_DET3 0 0x4462 0 0 4294967295 mmSCL3_SCL_MODE_CHANGE_MASK 0 0x4463 0 0 4294967295 mmSCL3_SCL_TAP_CONTROL 0 0x4443 0 0 4294967295 mmSCL3_SCL_TEST_DEBUG_DATA 0 0x446c 0 0 4294967295 mmSCL3_SCL_TEST_DEBUG_INDEX 0 0x446b 0 0 4294967295 mmSCL3_SCL_UPDATE 0 0x4451 0 0 4294967295 mmSCL3_SCL_VERT_FILTER_CONTROL 0 0x444e 0 0 4294967295 mmSCL3_SCL_VERT_FILTER_INIT 0 0x4450 0 0 4294967295 mmSCL3_SCL_VERT_FILTER_INIT_BOT 0 0x4457 0 0 4294967295 mmSCL3_SCL_VERT_FILTER_SCALE_RATIO 0 0x444f 0 0 4294967295 mmSCL3_VIEWPORT_SIZE 0 0x445d 0 0 4294967295 mmSCL3_VIEWPORT_START 0 0x445c 0 0 4294967295 mmSCL4_EXT_OVERSCAN_LEFT_RIGHT 0 0x475e 0 0 4294967295 mmSCL4_EXT_OVERSCAN_TOP_BOTTOM 0 0x475f 0 0 4294967295 mmSCL4_SCL_ALU_CONTROL 0 0x4754 0 0 4294967295 mmSCL4_SCL_AUTOMATIC_MODE_CONTROL 0 0x4747 0 0 4294967295 mmSCL4_SCL_BYPASS_CONTROL 0 0x4745 0 0 4294967295 mmSCL4_SCL_COEF_RAM_CONFLICT_STATUS 0 0x4755 0 0 4294967295 mmSCL4_SCL_COEF_RAM_SELECT 0 0x4740 0 0 4294967295 mmSCL4_SCL_COEF_RAM_TAP_DATA 0 0x4741 0 0 4294967295 mmSCL4_SCL_CONTROL 0 0x4744 0 0 4294967295 mmSCL4_SCL_DEBUG 0 0x476a 0 0 4294967295 mmSCL4_SCL_DEBUG2 0 0x4769 0 0 4294967295 mmSCL4_SCL_F_SHARP_CONTROL 0 0x4753 0 0 4294967295 mmSCL4_SCL_HORZ_FILTER_CONTROL 0 0x474a 0 0 4294967295 mmSCL4_SCL_HORZ_FILTER_SCALE_RATIO 0 0x474b 0 0 4294967295 mmSCL4_SCL_MANUAL_REPLICATE_CONTROL 0 0x4746 0 0 4294967295 mmSCL4_SCL_MODE_CHANGE_DET1 0 0x4760 0 0 4294967295 mmSCL4_SCL_MODE_CHANGE_DET2 0 0x4761 0 0 4294967295 mmSCL4_SCL_MODE_CHANGE_DET3 0 0x4762 0 0 4294967295 mmSCL4_SCL_MODE_CHANGE_MASK 0 0x4763 0 0 4294967295 mmSCL4_SCL_TAP_CONTROL 0 0x4743 0 0 4294967295 mmSCL4_SCL_TEST_DEBUG_DATA 0 0x476c 0 0 4294967295 mmSCL4_SCL_TEST_DEBUG_INDEX 0 0x476b 0 0 4294967295 mmSCL4_SCL_UPDATE 0 0x4751 0 0 4294967295 mmSCL4_SCL_VERT_FILTER_CONTROL 0 0x474e 0 0 4294967295 mmSCL4_SCL_VERT_FILTER_INIT 0 0x4750 0 0 4294967295 mmSCL4_SCL_VERT_FILTER_INIT_BOT 0 0x4757 0 0 4294967295 mmSCL4_SCL_VERT_FILTER_SCALE_RATIO 0 0x474f 0 0 4294967295 mmSCL4_VIEWPORT_SIZE 0 0x475d 0 0 4294967295 mmSCL4_VIEWPORT_START 0 0x475c 0 0 4294967295 mmSCL5_EXT_OVERSCAN_LEFT_RIGHT 0 0x4a5e 0 0 4294967295 mmSCL5_EXT_OVERSCAN_TOP_BOTTOM 0 0x4a5f 0 0 4294967295 mmSCL5_SCL_ALU_CONTROL 0 0x4a54 0 0 4294967295 mmSCL5_SCL_AUTOMATIC_MODE_CONTROL 0 0x4a47 0 0 4294967295 mmSCL5_SCL_BYPASS_CONTROL 0 0x4a45 0 0 4294967295 mmSCL5_SCL_COEF_RAM_CONFLICT_STATUS 0 0x4a55 0 0 4294967295 mmSCL5_SCL_COEF_RAM_SELECT 0 0x4a40 0 0 4294967295 mmSCL5_SCL_COEF_RAM_TAP_DATA 0 0x4a41 0 0 4294967295 mmSCL5_SCL_CONTROL 0 0x4a44 0 0 4294967295 mmSCL5_SCL_DEBUG 0 0x4a6a 0 0 4294967295 mmSCL5_SCL_DEBUG2 0 0x4a69 0 0 4294967295 mmSCL5_SCL_F_SHARP_CONTROL 0 0x4a53 0 0 4294967295 mmSCL5_SCL_HORZ_FILTER_CONTROL 0 0x4a4a 0 0 4294967295 mmSCL5_SCL_HORZ_FILTER_SCALE_RATIO 0 0x4a4b 0 0 4294967295 mmSCL5_SCL_MANUAL_REPLICATE_CONTROL 0 0x4a46 0 0 4294967295 mmSCL5_SCL_MODE_CHANGE_DET1 0 0x4a60 0 0 4294967295 mmSCL5_SCL_MODE_CHANGE_DET2 0 0x4a61 0 0 4294967295 mmSCL5_SCL_MODE_CHANGE_DET3 0 0x4a62 0 0 4294967295 mmSCL5_SCL_MODE_CHANGE_MASK 0 0x4a63 0 0 4294967295 mmSCL5_SCL_TAP_CONTROL 0 0x4a43 0 0 4294967295 mmSCL5_SCL_TEST_DEBUG_DATA 0 0x4a6c 0 0 4294967295 mmSCL5_SCL_TEST_DEBUG_INDEX 0 0x4a6b 0 0 4294967295 mmSCL5_SCL_UPDATE 0 0x4a51 0 0 4294967295 mmSCL5_SCL_VERT_FILTER_CONTROL 0 0x4a4e 0 0 4294967295 mmSCL5_SCL_VERT_FILTER_INIT 0 0x4a50 0 0 4294967295 mmSCL5_SCL_VERT_FILTER_INIT_BOT 0 0x4a57 0 0 4294967295 mmSCL5_SCL_VERT_FILTER_SCALE_RATIO 0 0x4a4f 0 0 4294967295 mmSCL5_VIEWPORT_SIZE 0 0x4a5d 0 0 4294967295 mmSCL5_VIEWPORT_START 0 0x4a5c 0 0 4294967295 mmSCL_ALU_CONTROL 0 0x1b54 1 0 4294967295 SCL_ALU_DISABLE 0 0 mmSCL_AUTOMATIC_MODE_CONTROL 0 0x1b47 0 0 4294967295 mmSCL_BYPASS_CONTROL 0 0x1b45 1 0 4294967295 SCL_BYPASS_MODE 0 1 mmSCL_COEF_RAM_CONFLICT_STATUS 0 0x1b55 4 0 4294967295 SCL_HOST_CONFLICT_ACK 8 8 SCL_HOST_CONFLICT_FLAG 0 0 SCL_HOST_CONFLICT_INT_STATUS 16 16 SCL_HOST_CONFLICT_MASK 12 12 mmSCL_COEF_RAM_SELECT 0 0x1b40 3 0 4294967295 SCL_C_RAM_FILTER_TYPE 16 17 SCL_C_RAM_PHASE 8 11 SCL_C_RAM_TAP_PAIR_IDX 0 3 mmSCL_COEF_RAM_TAP_DATA 0 0x1b41 4 0 4294967295 SCL_C_RAM_EVEN_TAP_COEF_EN 15 15 SCL_C_RAM_EVEN_TAP_COEF 0 13 SCL_C_RAM_ODD_TAP_COEF_EN 31 31 SCL_C_RAM_ODD_TAP_COEF 16 29 mmSCL_CONTROL 0 0x1b44 0 0 4294967295 mmSCL_DEBUG 0 0x1b6a 1 0 4294967295 SCL_DEBUG 0 31 mmSCL_DEBUG2 0 0x1b69 1 0 4294967295 SCL_DEBUG2 0 31 mmSCL_F_SHARP_CONTROL 0 0x1b53 4 0 4294967295 SCL_HF_SHARP_EN 4 4 SCL_HF_SHARP_SCALE_FACTOR 0 2 SCL_VF_SHARP_EN 12 12 SCL_VF_SHARP_SCALE_FACTOR 8 10 mmSCL_HORZ_FILTER_CONTROL 0 0x1b4a 1 0 4294967295 SCL_H_FILTER_PICK_NEAREST 0 0 mmSCL_HORZ_FILTER_SCALE_RATIO 0 0x1b4b 1 0 4294967295 SCL_H_SCALE_RATIO 0 25 mmSCLK_CGTT_BLK_CTRL_REG 0 0x136 2 0 4294967295 SCLK_TURN_OFF_DELAY 4 11 SCLK_TURN_ON_DELAY 0 3 mmSCL_MANUAL_REPLICATE_CONTROL 0 0x1b46 2 0 4294967295 SCL_H_MANUAL_REPLICATE_FACTOR 8 11 SCL_V_MANUAL_REPLICATE_FACTOR 0 3 mmSCL_MODE_CHANGE_DET1 0 0x1b60 3 0 4294967295 SCL_ALU_H_SCALE_RATIO 7 27 SCL_MODE_CHANGE_ACK 4 4 SCL_MODE_CHANGE 0 0 mmSCL_MODE_CHANGE_DET2 0 0x1b61 1 0 4294967295 SCL_ALU_V_SCALE_RATIO 0 20 mmSCL_MODE_CHANGE_DET3 0 0x1b62 2 0 4294967295 SCL_ALU_SOURCE_HEIGHT 0 13 SCL_ALU_SOURCE_WIDTH 16 29 mmSCL_MODE_CHANGE_MASK 0 0x1b63 1 0 4294967295 SCL_MODE_CHANGE_MASK 0 0 mmSCL_TAP_CONTROL 0 0x1b43 2 0 4294967295 SCL_V_NUM_OF_TAPS 0 2 SCL_H_NUM_OF_TAPS 8 11 mmSCL_TEST_DEBUG_DATA 0 0x1b6c 1 0 4294967295 SCL_TEST_DEBUG_DATA 0 31 mmSCL_TEST_DEBUG_INDEX 0 0x1b6b 2 0 4294967295 SCL_TEST_DEBUG_INDEX 0 7 SCL_TEST_DEBUG_WRITE_EN 8 8 mmSCL_UPDATE 0 0x1b51 3 0 4294967295 SCL_UPDATE_LOCK 16 16 SCL_UPDATE_PENDING 0 0 SCL_UPDATE_TAKEN 8 8 mmSCL_VERT_FILTER_CONTROL 0 0x1b4e 1 0 4294967295 SCL_V_FILTER_PICK_NEAREST 0 0 mmSCL_VERT_FILTER_INIT 0 0x1b50 2 0 4294967295 SCL_V_INIT_FRAC 0 15 SCL_V_INIT_INT 16 18 mmSCL_VERT_FILTER_INIT_BOT 0 0x1b57 2 0 4294967295 SCL_V_INIT_FRAC_BOT 0 15 SCL_V_INIT_INT_BOT 16 18 mmSCL_VERT_FILTER_SCALE_RATIO 0 0x1b4f 1 0 4294967295 SCL_V_SCALE_RATIO 0 25 mmSEQ8_DATA 0 0xf1 1 0 4294967295 SEQ_DATA 0 7 mmSEQ8_IDX 0 0xf1 1 0 4294967295 SEQ_IDX 0 2 mmSLAVE_COMM_CMD_REG 0 0x1624 4 0 4294967295 SLAVE_COMM_CMD_REG_BYTE0 0 7 SLAVE_COMM_CMD_REG_BYTE1 8 15 SLAVE_COMM_CMD_REG_BYTE2 16 23 SLAVE_COMM_CMD_REG_BYTE3 24 31 mmSLAVE_COMM_CNTL_REG 0 0x1625 2 0 4294967295 COMM_PORT_MSG_TO_HOST_IN_PROGRESS 8 8 SLAVE_COMM_INTERRUPT 0 0 mmSLAVE_COMM_DATA_REG1 0 0x1621 4 0 4294967295 SLAVE_COMM_DATA_REG1_BYTE0 0 7 SLAVE_COMM_DATA_REG1_BYTE1 8 15 SLAVE_COMM_DATA_REG1_BYTE2 16 23 SLAVE_COMM_DATA_REG1_BYTE3 24 31 mmSLAVE_COMM_DATA_REG2 0 0x1622 4 0 4294967295 SLAVE_COMM_DATA_REG2_BYTE0 0 7 SLAVE_COMM_DATA_REG2_BYTE1 8 15 SLAVE_COMM_DATA_REG2_BYTE2 16 23 SLAVE_COMM_DATA_REG2_BYTE3 24 31 mmSLAVE_COMM_DATA_REG3 0 0x1623 4 0 4294967295 SLAVE_COMM_DATA_REG3_BYTE0 0 7 SLAVE_COMM_DATA_REG3_BYTE1 8 15 SLAVE_COMM_DATA_REG3_BYTE2 16 23 SLAVE_COMM_DATA_REG3_BYTE3 24 31 mmSYMCLKA_CLOCK_ENABLE 0 0x160 3 0 4294967295 SYMCLKA_CLOCK_ENABLE 0 0 SYMCLKA_FE_FORCE_EN 4 4 SYMCLKA_FE_FORCE_SRC 8 10 mmSYMCLKB_CLOCK_ENABLE 0 0x161 3 0 4294967295 SYMCLKB_CLOCK_ENABLE 0 0 SYMCLKB_FE_FORCE_EN 4 4 SYMCLKB_FE_FORCE_SRC 8 10 mmSYMCLKC_CLOCK_ENABLE 0 0x162 3 0 4294967295 SYMCLKC_CLOCK_ENABLE 0 0 SYMCLKC_FE_FORCE_EN 4 4 SYMCLKC_FE_FORCE_SRC 8 10 mmSYMCLKD_CLOCK_ENABLE 0 0x163 3 0 4294967295 SYMCLKD_CLOCK_ENABLE 0 0 SYMCLKD_FE_FORCE_EN 4 4 SYMCLKD_FE_FORCE_SRC 8 10 mmSYMCLKE_CLOCK_ENABLE 0 0x164 3 0 4294967295 SYMCLKE_CLOCK_ENABLE 0 0 SYMCLKE_FE_FORCE_EN 4 4 SYMCLKE_FE_FORCE_SRC 8 10 mmSYMCLKF_CLOCK_ENABLE 0 0x165 3 0 4294967295 SYMCLKF_CLOCK_ENABLE 0 0 SYMCLKF_FE_FORCE_EN 4 4 SYMCLKF_FE_FORCE_SRC 8 10 mmTMDS_CNTL 0 0x1c7c 3 0 4294967295 TMDS_COLOR_FORMAT 8 9 TMDS_PIXEL_ENCODING 4 4 TMDS_SYNC_PHASE 0 0 mmTMDS_CONTROL0_FEEDBACK 0 0x1c7e 2 0 4294967295 TMDS_CONTROL0_FEEDBACK_DELAY 8 9 TMDS_CONTROL0_FEEDBACK_SELECT 0 1 mmTMDS_CONTROL_CHAR 0 0x1c7d 4 0 4294967295 TMDS_CONTROL_CHAR0_OUT_EN 0 0 TMDS_CONTROL_CHAR1_OUT_EN 1 1 TMDS_CONTROL_CHAR2_OUT_EN 2 2 TMDS_CONTROL_CHAR3_OUT_EN 3 3 mmTMDS_CTL0_1_GEN_CNTL 0 0x1c86 15 0 4294967295 TMDS_2BIT_COUNTER_EN 31 31 TMDS_CTL0_DATA_DELAY 4 6 TMDS_CTL0_DATA_INVERT 7 7 TMDS_CTL0_DATA_MODULATION 8 9 TMDS_CTL0_DATA_SEL 0 3 TMDS_CTL0_FB_SYNC_CONT 11 11 TMDS_CTL0_PATTERN_OUT_EN 12 12 TMDS_CTL0_USE_FEEDBACK_PATH 10 10 TMDS_CTL1_DATA_DELAY 20 22 TMDS_CTL1_DATA_INVERT 23 23 TMDS_CTL1_DATA_MODULATION 24 25 TMDS_CTL1_DATA_SEL 16 19 TMDS_CTL1_FB_SYNC_CONT 27 27 TMDS_CTL1_PATTERN_OUT_EN 28 28 TMDS_CTL1_USE_FEEDBACK_PATH 26 26 mmTMDS_CTL2_3_GEN_CNTL 0 0x1c87 14 0 4294967295 TMDS_CTL2_DATA_DELAY 4 6 TMDS_CTL2_DATA_INVERT 7 7 TMDS_CTL2_DATA_MODULATION 8 9 TMDS_CTL2_DATA_SEL 0 3 TMDS_CTL2_FB_SYNC_CONT 11 11 TMDS_CTL2_PATTERN_OUT_EN 12 12 TMDS_CTL2_USE_FEEDBACK_PATH 10 10 TMDS_CTL3_DATA_DELAY 20 22 TMDS_CTL3_DATA_INVERT 23 23 TMDS_CTL3_DATA_MODULATION 24 25 TMDS_CTL3_DATA_SEL 16 19 TMDS_CTL3_FB_SYNC_CONT 27 27 TMDS_CTL3_PATTERN_OUT_EN 28 28 TMDS_CTL3_USE_FEEDBACK_PATH 26 26 mmTMDS_CTL_BITS 0 0x1c83 4 0 4294967295 TMDS_CTL0 0 0 TMDS_CTL1 8 8 TMDS_CTL2 16 16 TMDS_CTL3 24 24 mmTMDS_DCBALANCER_CONTROL 0 0x1c84 5 0 4294967295 TMDS_DCBALANCER_EN 0 0 TMDS_DCBALANCER_FORCE 24 24 TMDS_DCBALANCER_TEST_EN 8 8 TMDS_DCBALANCER_TEST_IN 16 19 TMDS_SYNC_DCBAL_EN 4 6 mmTMDS_DEBUG 0 0x1c82 7 0 4294967295 TMDS_DEBUG_DE_EN 25 25 TMDS_DEBUG_DE 24 24 TMDS_DEBUG_EN 0 0 TMDS_DEBUG_HSYNC_EN 9 9 TMDS_DEBUG_HSYNC 8 8 TMDS_DEBUG_VSYNC_EN 17 17 TMDS_DEBUG_VSYNC 16 16 mmTMDS_STEREOSYNC_CTL_SEL 0 0x1c7f 1 0 4294967295 TMDS_STEREOSYNC_CTL_SEL 0 1 mmTMDS_SYNC_CHAR_PATTERN_0_1 0 0x1c80 2 0 4294967295 TMDS_SYNC_CHAR_PATTERN0 0 9 TMDS_SYNC_CHAR_PATTERN1 16 25 mmTMDS_SYNC_CHAR_PATTERN_2_3 0 0x1c81 2 0 4294967295 TMDS_SYNC_CHAR_PATTERN2 0 9 TMDS_SYNC_CHAR_PATTERN3 16 25 mmUNIPHYAB_TPG_CONTROL 0 0x1931 3 0 4294967295 UNIPHYAB_STATIC_TEST_PATTERN 0 9 UNIPHYAB_TPG_EN 16 16 UNIPHYAB_TPG_SEL 17 19 mmUNIPHYAB_TPG_SEED 0 0x1932 1 0 4294967295 UNIPHYAB_TPG_SEED 0 22 mmUNIPHY_ANG_BIST_CNTL 0 0x198c 5 0 4294967295 UNIPHY_ANG_BIST_ERROR 16 20 UNIPHY_ANG_BIST_RESET 1 1 UNIPHY_PRESETB 24 24 UNIPHY_RX_BIAS 8 11 UNIPHY_TEST_RX_EN 0 0 mmUNIPHYCD_TPG_CONTROL 0 0x1933 3 0 4294967295 UNIPHYCD_STATIC_TEST_PATTERN 0 9 UNIPHYCD_TPG_EN 16 16 UNIPHYCD_TPG_SEL 17 19 mmUNIPHYCD_TPG_SEED 0 0x1934 1 0 4294967295 UNIPHYCD_TPG_SEED 0 22 mmUNIPHY_CHANNEL_XBAR_CNTL 0 0x198e 4 0 4294967295 UNIPHY_CHANNEL0_XBAR_SOURCE 0 1 UNIPHY_CHANNEL1_XBAR_SOURCE 8 9 UNIPHY_CHANNEL2_XBAR_SOURCE 16 17 UNIPHY_CHANNEL3_XBAR_SOURCE 24 25 mmUNIPHY_DATA_SYNCHRONIZATION 0 0x198a 6 0 4294967295 UNIPHY_DSYN_ERROR 6 6 UNIPHY_DSYN_LEVEL 4 5 UNIPHY_DSYNSEL 0 0 UNIPHY_DUAL_LINK_PHASE 16 16 UNIPHY_LINK_ENABLE 12 12 UNIPHY_SOURCE_SELECT 8 8 mmUNIPHYEF_TPG_CONTROL 0 0x1935 3 0 4294967295 UNIPHYEF_STATIC_TEST_PATTERN 0 9 UNIPHYEF_TPG_EN 16 16 UNIPHYEF_TPG_SEL 17 19 mmUNIPHYEF_TPG_SEED 0 0x1936 1 0 4294967295 UNIPHYEF_TPG_SEED 0 22 mmUNIPHY_IMPCAL_LINKA 0 0x1908 9 0 4294967295 UNIPHY_CALOUT_ERROR_LINKA_AK 10 10 UNIPHY_CALOUT_ERROR_LINKA 9 9 UNIPHY_IMPCAL_CALOUT_LINKA 8 8 UNIPHY_IMPCAL_ENABLE_LINKA 0 0 UNIPHY_IMPCAL_OVERRIDE_ENABLE_LINKA 28 28 UNIPHY_IMPCAL_OVERRIDE_LINKA 24 27 UNIPHY_IMPCAL_SEL_LINKA 30 30 UNIPHY_IMPCAL_STEP_DELAY_LINKA 20 23 UNIPHY_IMPCAL_VALUE_LINKA 16 19 mmUNIPHY_IMPCAL_LINKB 0 0x1909 9 0 4294967295 UNIPHY_CALOUT_ERROR_LINKB_AK 10 10 UNIPHY_CALOUT_ERROR_LINKB 9 9 UNIPHY_IMPCAL_CALOUT_LINKB 8 8 UNIPHY_IMPCAL_ENABLE_LINKB 0 0 UNIPHY_IMPCAL_OVERRIDE_ENABLE_LINKB 28 28 UNIPHY_IMPCAL_OVERRIDE_LINKB 24 27 UNIPHY_IMPCAL_SEL_LINKB 30 30 UNIPHY_IMPCAL_STEP_DELAY_LINKB 20 23 UNIPHY_IMPCAL_VALUE_LINKB 16 19 mmUNIPHY_IMPCAL_LINKC 0 0x190f 9 0 4294967295 UNIPHY_CALOUT_ERROR_LINKC_AK 10 10 UNIPHY_CALOUT_ERROR_LINKC 9 9 UNIPHY_IMPCAL_CALOUT_LINKC 8 8 UNIPHY_IMPCAL_ENABLE_LINKC 0 0 UNIPHY_IMPCAL_OVERRIDE_ENABLE_LINKC 28 28 UNIPHY_IMPCAL_OVERRIDE_LINKC 24 27 UNIPHY_IMPCAL_SEL_LINKC 30 30 UNIPHY_IMPCAL_STEP_DELAY_LINKC 20 23 UNIPHY_IMPCAL_VALUE_LINKC 16 19 mmUNIPHY_IMPCAL_LINKD 0 0x1910 9 0 4294967295 UNIPHY_CALOUT_ERROR_LINKD_AK 10 10 UNIPHY_CALOUT_ERROR_LINKD 9 9 UNIPHY_IMPCAL_CALOUT_LINKD 8 8 UNIPHY_IMPCAL_ENABLE_LINKD 0 0 UNIPHY_IMPCAL_OVERRIDE_ENABLE_LINKD 28 28 UNIPHY_IMPCAL_OVERRIDE_LINKD 24 27 UNIPHY_IMPCAL_SEL_LINKD 30 30 UNIPHY_IMPCAL_STEP_DELAY_LINKD 20 23 UNIPHY_IMPCAL_VALUE_LINKD 16 19 mmUNIPHY_IMPCAL_LINKE 0 0x1913 9 0 4294967295 UNIPHY_CALOUT_ERROR_LINKE_AK 10 10 UNIPHY_CALOUT_ERROR_LINKE 9 9 UNIPHY_IMPCAL_CALOUT_LINKE 8 8 UNIPHY_IMPCAL_ENABLE_LINKE 0 0 UNIPHY_IMPCAL_OVERRIDE_ENABLE_LINKE 28 28 UNIPHY_IMPCAL_OVERRIDE_LINKE 24 27 UNIPHY_IMPCAL_SEL_LINKE 30 30 UNIPHY_IMPCAL_STEP_DELAY_LINKE 20 23 UNIPHY_IMPCAL_VALUE_LINKE 16 19 mmUNIPHY_IMPCAL_LINKF 0 0x1914 9 0 4294967295 UNIPHY_CALOUT_ERROR_LINKF_AK 10 10 UNIPHY_CALOUT_ERROR_LINKF 9 9 UNIPHY_IMPCAL_CALOUT_LINKF 8 8 UNIPHY_IMPCAL_ENABLE_LINKF 0 0 UNIPHY_IMPCAL_OVERRIDE_ENABLE_LINKF 28 28 UNIPHY_IMPCAL_OVERRIDE_LINKF 24 27 UNIPHY_IMPCAL_SEL_LINKF 30 30 UNIPHY_IMPCAL_STEP_DELAY_LINKF 20 23 UNIPHY_IMPCAL_VALUE_LINKF 16 19 mmUNIPHY_IMPCAL_PERIOD 0 0x190a 1 0 4294967295 UNIPHY_IMPCAL_PERIOD 0 31 mmUNIPHY_IMPCAL_PSW_AB 0 0x190e 2 0 4294967295 UNIPHY_IMPCAL_PSW_LINKA 0 14 UNIPHY_IMPCAL_PSW_LINKB 16 30 mmUNIPHY_IMPCAL_PSW_CD 0 0x1912 2 0 4294967295 UNIPHY_IMPCAL_PSW_LINKC 0 14 UNIPHY_IMPCAL_PSW_LINKD 16 30 mmUNIPHY_IMPCAL_PSW_EF 0 0x1916 2 0 4294967295 UNIPHY_IMPCAL_PSW_LINKE 0 14 UNIPHY_IMPCAL_PSW_LINKF 16 30 mmUNIPHY_LINK_CNTL 0 0x198d 9 0 4294967295 UNIPHY_CHANNEL0_INVERT 12 12 UNIPHY_CHANNEL1_INVERT 13 13 UNIPHY_CHANNEL2_INVERT 14 14 UNIPHY_CHANNEL3_INVERT 15 15 UNIPHY_LANE_STAGGER_DELAY 20 22 UNIPHY_LINK_ENABLE_HPD_MASK 16 17 UNIPHY_MINIMUM_PIXVLD_LOW_DURATION 8 10 UNIPHY_PFREQCHG 0 0 UNIPHY_PIXVLD_RESET 4 4 mmUNIPHY_PLL_CONTROL1 0 0x1986 11 0 4294967295 UNIPHY_PLL_BW_CNTL 16 23 UNIPHY_PLL_CLK_EN 3 3 UNIPHY_PLL_CLKPH_EN 4 7 UNIPHY_PLL_ENABLE 0 0 UNIPHY_PLL_EXT_RESET_EN 2 2 UNIPHY_PLL_LF_CNTL 8 14 UNIPHY_PLL_RESET 1 1 UNIPHY_PLL_TEST_BYPCLK_EN 25 25 UNIPHY_PLL_TEST_BYPCLK_SRC 24 24 UNIPHY_PLL_TEST_VCTL_ADC_EN 26 26 UNIPHY_VCO_MODE 28 29 mmUNIPHY_PLL_CONTROL2 0 0x1987 14 0 4294967295 UNIPHY_CLKINV 13 13 UNIPHY_DPLLSEL 2 3 UNIPHY_IDCLK_EN 12 12 UNIPHY_IDCLK_SEL 4 4 UNIPHY_IPCIE_REFCLK_SEL 5 5 UNIPHY_IXTALIN_SEL 6 6 UNIPHY_PCIEREF_CLK_EN 11 11 UNIPHY_PDIVFRAC_SEL 20 20 UNIPHY_PDIV_SEL 29 31 UNIPHY_PLL_DISPCLK_MODE 0 1 UNIPHY_PLL_REFCLK_SRC 8 10 UNIPHY_PLL_REFDIV 24 28 UNIPHY_PLL_TEST_FBDIV_FRAC_BYPASS 19 19 UNIPHY_PLL_VTOI_BIAS_CNTL 16 16 mmUNIPHY_PLL_FBDIV 0 0x1985 2 0 4294967295 UNIPHY_PLL_FBDIV_FRACTION 2 15 UNIPHY_PLL_FBDIV 16 27 mmUNIPHY_PLL_SS_CNTL 0 0x1989 3 0 4294967295 UNIPHY_PLL_DSMOD_EN 12 12 UNIPHY_PLL_SS_EN 13 13 UNIPHY_PLL_SS_STEP_NUM 0 11 mmUNIPHY_PLL_SS_STEP_SIZE 0 0x1988 1 0 4294967295 UNIPHY_PLL_SS_STEP_SIZE 0 25 mmUNIPHY_POWER_CONTROL 0 0x1984 6 0 4294967295 UNIPHY_BGADJ0P45 16 19 UNIPHY_BGADJ1P00 8 11 UNIPHY_BGADJ1P25 12 15 UNIPHY_BGPDN 0 0 UNIPHY_BIASREF_SEL 2 2 UNIPHY_RST_LOGIC 1 1 mmUNIPHY_REG_TEST_OUTPUT 0 0x198b 8 0 4294967295 UNIPHY_DIG_BIST_ERROR 20 24 UNIPHY_DIG_BIST_RESET 15 15 UNIPHY_DIG_BIST_SEL 16 16 UNIPHY_PLL_INTRESET 29 29 UNIPHY_PLL_TEST_FREQ_LOCK 28 28 UNIPHY_PLL_TEST_VCTL_ADC 25 27 UNIPHY_TEST_CNTL 0 4 UNIPHY_TEST_VCTL_EN 17 17 mmUNIPHY_SOFT_RESET 0 0x166 6 0 4294967295 DSYNCA_SOFT_RESET 0 0 DSYNCB_SOFT_RESET 1 1 DSYNCC_SOFT_RESET 2 2 DSYNCD_SOFT_RESET 3 3 DSYNCE_SOFT_RESET 4 4 DSYNCF_SOFT_RESET 5 5 mmUNIPHY_TX_CONTROL1 0 0x1980 10 0 4294967295 UNIPHY_PREMPH_STR0 0 2 UNIPHY_PREMPH_STR1 4 6 UNIPHY_PREMPH_STR2 8 10 UNIPHY_PREMPH_STR3 12 14 UNIPHY_PREMPH_STR4 16 18 UNIPHY_TX_VS0 20 21 UNIPHY_TX_VS1 22 23 UNIPHY_TX_VS2 24 25 UNIPHY_TX_VS3 26 27 UNIPHY_TX_VS4 28 29 mmUNIPHY_TX_CONTROL2 0 0x1981 11 0 4294967295 UNIPHY_PREMPH0_PC 0 1 UNIPHY_PREMPH1_PC 4 5 UNIPHY_PREMPH2_PC 8 9 UNIPHY_PREMPH3_PC 12 13 UNIPHY_PREMPH4_PC 16 17 UNIPHY_PREMPH_SEL 20 20 UNIPHY_RT0_CPSEL 21 22 UNIPHY_RT1_CPSEL 23 24 UNIPHY_RT2_CPSEL 25 26 UNIPHY_RT3_CPSEL 27 28 UNIPHY_RT4_CPSEL 29 30 mmUNIPHY_TX_CONTROL3 0 0x1982 12 0 4294967295 UNIPHY_LVDS_PULLDWN 31 31 UNIPHY_PESEL0 20 20 UNIPHY_PESEL1 21 21 UNIPHY_PESEL2 22 22 UNIPHY_PESEL3 23 23 UNIPHY_PREMPH_CS_CLK 4 7 UNIPHY_PREMPH_CS_DAT 8 11 UNIPHY_PREMPH_PW_CLK 0 1 UNIPHY_PREMPH_PW_DAT 2 3 UNIPHY_PREMPH_STR_CLK 12 14 UNIPHY_PREMPH_STR_DAT 16 18 UNIPHY_TX_VS_ADJ 24 28 mmUNIPHY_TX_CONTROL4 0 0x1983 6 0 4294967295 UNIPHY_TX_NVS_CLK 0 4 UNIPHY_TX_NVS_DAT 5 9 UNIPHY_TX_OP_CLK 24 26 UNIPHY_TX_OP_DAT 28 30 UNIPHY_TX_PVS_CLK 12 16 UNIPHY_TX_PVS_DAT 17 21 mmVGA25_PPLL_ANALOG 0 0xe4 5 0 4294967295 VGA25_CAL_MODE 0 4 VGA25_PPLL_CP 8 11 VGA25_PPLL_IBIAS 24 31 VGA25_PPLL_LF_MODE 12 20 VGA25_PPLL_PFD_PULSE_SEL 5 6 mmVGA25_PPLL_FB_DIV 0 0xdc 3 0 4294967295 VGA25_PPLL_FB_DIV_FRACTION_CNTL 4 5 VGA25_PPLL_FB_DIV_FRACTION 0 3 VGA25_PPLL_FB_DIV 16 26 mmVGA25_PPLL_POST_DIV 0 0xe0 3 0 4294967295 VGA25_PPLL_POST_DIV_DVOCLK 8 14 VGA25_PPLL_POST_DIV_IDCLK 16 22 VGA25_PPLL_POST_DIV_PIXCLK 0 6 mmVGA25_PPLL_REF_DIV 0 0xd8 1 0 4294967295 VGA25_PPLL_REF_DIV 0 9 mmVGA28_PPLL_ANALOG 0 0xe5 5 0 4294967295 VGA28_CAL_MODE 0 4 VGA28_PPLL_CP 8 11 VGA28_PPLL_IBIAS 24 31 VGA28_PPLL_LF_MODE 12 20 VGA28_PPLL_PFD_PULSE_SEL 5 6 mmVGA28_PPLL_FB_DIV 0 0xdd 3 0 4294967295 VGA28_PPLL_FB_DIV_FRACTION_CNTL 4 5 VGA28_PPLL_FB_DIV_FRACTION 0 3 VGA28_PPLL_FB_DIV 16 26 mmVGA28_PPLL_POST_DIV 0 0xe1 3 0 4294967295 VGA28_PPLL_POST_DIV_DVOCLK 8 14 VGA28_PPLL_POST_DIV_IDCLK 16 22 VGA28_PPLL_POST_DIV_PIXCLK 0 6 mmVGA28_PPLL_REF_DIV 0 0xd9 1 0 4294967295 VGA28_PPLL_REF_DIV 0 9 mmVGA41_PPLL_ANALOG 0 0xe6 5 0 4294967295 VGA41_CAL_MODE 0 4 VGA41_PPLL_CP 8 11 VGA41_PPLL_IBIAS 24 31 VGA41_PPLL_LF_MODE 12 20 VGA41_PPLL_PFD_PULSE_SEL 5 6 mmVGA41_PPLL_FB_DIV 0 0xde 3 0 4294967295 VGA41_PPLL_FB_DIV_FRACTION_CNTL 4 5 VGA41_PPLL_FB_DIV_FRACTION 0 3 VGA41_PPLL_FB_DIV 16 26 mmVGA41_PPLL_POST_DIV 0 0xe2 3 0 4294967295 VGA41_PPLL_POST_DIV_DVOCLK 8 14 VGA41_PPLL_POST_DIV_IDCLK 16 22 VGA41_PPLL_POST_DIV_PIXCLK 0 6 mmVGA41_PPLL_REF_DIV 0 0xda 1 0 4294967295 VGA41_PPLL_REF_DIV 0 9 mmVGA_CACHE_CONTROL 0 0xcb 5 0 4294967295 VGA_DCCIF_W256ONLY 20 20 VGA_DCCIF_WC_TIMEOUT 24 29 VGA_READ_BUFFER_INVALIDATE 16 16 VGA_READ_CACHE_DISABLE 8 8 VGA_WRITE_THROUGH_CACHE_DIS 0 0 mmVGA_DEBUG_READBACK_DATA 0 0xd7 1 0 4294967295 VGA_DEBUG_READBACK_DATA 0 31 mmVGA_DEBUG_READBACK_INDEX 0 0xd6 1 0 4294967295 VGA_DEBUG_READBACK_INDEX 0 7 mmVGA_DISPBUF1_SURFACE_ADDR 0 0xc6 1 0 4294967295 VGA_DISPBUF1_SURFACE_ADDR 0 24 mmVGA_DISPBUF2_SURFACE_ADDR 0 0xc8 1 0 4294967295 VGA_DISPBUF2_SURFACE_ADDR 0 24 mmVGA_HDP_CONTROL 0 0xca 5 0 4294967295 VGA_MEMORY_DISABLE 4 4 VGA_MEM_PAGE_SELECT_EN 0 0 VGA_RBBM_LOCK_DISABLE 8 8 VGA_SOFT_RESET 16 16 VGA_TEST_RESET_CONTROL 24 24 mmVGA_HW_DEBUG 0 0xcf 1 0 4294967295 VGA_HW_DEBUG 0 31 mmVGA_INTERRUPT_CONTROL 0 0xd1 4 0 4294967295 VGA_DISPLAY_SWITCH_INT_MASK 16 16 VGA_MEM_ACCESS_INT_MASK 0 0 VGA_MODE_AUTO_TRIGGER_INT_MASK 24 24 VGA_REG_ACCESS_INT_MASK 8 8 mmVGA_INTERRUPT_STATUS 0 0xd3 4 0 4294967295 VGA_DISPLAY_SWITCH_INT_STATUS 2 2 VGA_MEM_ACCESS_INT_STATUS 0 0 VGA_MODE_AUTO_TRIGGER_INT_STATUS 3 3 VGA_REG_ACCESS_INT_STATUS 1 1 mmVGA_MAIN_CONTROL 0 0xd4 11 0 4294967295 VGA_CRTC_TIMEOUT 0 1 VGA_EXTERNAL_DAC_SENSE 29 29 VGA_MAIN_TEST_VSTATUS_NO_DISPLAY_CRTC_TIMEOUT 31 31 VGA_READBACK_CRT_INTR_SOURCE_SELECT 24 25 VGA_READBACK_NO_DISPLAY_SOURCE_SELECT 16 17 VGA_READBACK_SENSE_SWITCH_SELECT 26 26 VGA_READBACK_VGA_VSTATUS_SOURCE_SELECT 8 9 VGA_READ_URGENT_ENABLE 27 27 VGA_RENDER_TIMEOUT_COUNT 3 4 VGA_VIRTUAL_VERTICAL_RETRACE_DURATION 5 7 VGA_WRITES_URGENT_ENABLE 28 28 mmVGA_MEMORY_BASE_ADDRESS 0 0xc4 1 0 4294967295 VGA_MEMORY_BASE_ADDRESS 0 31 mmVGA_MEMORY_BASE_ADDRESS_HIGH 0 0xc9 1 0 4294967295 VGA_MEMORY_BASE_ADDRESS_HIGH 0 7 mmVGA_MEM_READ_PAGE_ADDR 0 0x13 2 0 4294967295 VGA_MEM_READ_PAGE0_ADDR 0 9 VGA_MEM_READ_PAGE1_ADDR 16 25 mmVGA_MEM_WRITE_PAGE_ADDR 0 0x12 2 0 4294967295 VGA_MEM_WRITE_PAGE0_ADDR 0 9 VGA_MEM_WRITE_PAGE1_ADDR 16 25 mmVGA_MODE_CONTROL 0 0xc2 4 0 4294967295 VGA_128K_APERTURE_PAGING 8 8 VGA_ATI_LINEAR 0 0 VGA_LUT_PALETTE_UPDATE_MODE 4 5 VGA_TEXT_132_COLUMNS_EN 16 16 mmVGA_RENDER_CONTROL 0 0xc0 7 0 4294967295 VGA_BLINK_MODE 5 6 VGA_BLINK_RATE 0 4 VGA_CURSOR_BLINK_INVERT 7 7 VGA_EXTD_ADDR_COUNT_ENABLE 8 8 VGA_LOCK_8DOT 24 24 VGAREG_LINECMP_COMPATIBILITY_SEL 25 25 VGA_VSTATUS_CNTL 16 17 mmVGA_SEQUENCER_RESET_CONTROL 0 0xc1 15 0 4294967295 D1_BLANK_DISPLAY_WHEN_SEQUENCER_RESET 0 0 D1_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET 8 8 D2_BLANK_DISPLAY_WHEN_SEQUENCER_RESET 1 1 D2_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET 9 9 D3_BLANK_DISPLAY_WHEN_SEQUENCER_RESET 2 2 D3_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET 10 10 D4_BLANK_DISPLAY_WHEN_SEQUENCER_RESET 3 3 D4_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET 11 11 D5_BLANK_DISPLAY_WHEN_SEQUENCER_RESET 4 4 D5_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET 12 12 D6_BLANK_DISPLAY_WHEN_SEQUENCER_RESET 5 5 D6_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET 13 13 VGA_MODE_AUTO_TRIGGER_ENABLE 16 16 VGA_MODE_AUTO_TRIGGER_INDEX_SELECT 18 23 VGA_MODE_AUTO_TRIGGER_REGISTER_SELECT 17 17 mmVGA_SOURCE_SELECT 0 0xfc 2 0 4294967295 VGA_SOURCE_SEL_A 0 2 VGA_SOURCE_SEL_B 8 10 mmVGA_STATUS 0 0xd0 4 0 4294967295 VGA_DISPLAY_SWITCH_STATUS 2 2 VGA_MEM_ACCESS_STATUS 0 0 VGA_MODE_AUTO_TRIGGER_STATUS 3 3 VGA_REG_ACCESS_STATUS 1 1 mmVGA_STATUS_CLEAR 0 0xd2 4 0 4294967295 VGA_DISPLAY_SWITCH_INT_CLEAR 16 16 VGA_MEM_ACCESS_INT_CLEAR 0 0 VGA_MODE_AUTO_TRIGGER_INT_CLEAR 24 24 VGA_REG_ACCESS_INT_CLEAR 8 8 mmVGA_SURFACE_PITCH_SELECT 0 0xc3 2 0 4294967295 VGA_SURFACE_HEIGHT_SELECT 8 9 VGA_SURFACE_PITCH_SELECT 0 1 mmVGA_TEST_CONTROL 0 0xd5 4 0 4294967295 VGA_TEST_ENABLE 0 0 VGA_TEST_RENDER_DISPBUF_SELECT 24 24 VGA_TEST_RENDER_DONE 16 16 VGA_TEST_RENDER_START 8 8 mmVGA_TEST_DEBUG_DATA 0 0xc7 1 0 4294967295 VGA_TEST_DEBUG_DATA 0 31 mmVGA_TEST_DEBUG_INDEX 0 0xc5 2 0 4294967295 VGA_TEST_DEBUG_INDEX 0 7 VGA_TEST_DEBUG_WRITE_EN 8 8 mmVIEWPORT_SIZE 0 0x1b5d 2 0 4294967295 VIEWPORT_HEIGHT 0 13 VIEWPORT_WIDTH 16 29 mmVIEWPORT_START 0 0x1b5c 2 0 4294967295 VIEWPORT_X_START 16 29 VIEWPORT_Y_START 0 13 mmXDMA_CLOCK_GATING_CNTL 0 0x409 7 0 4294967295 XDMA_SCLK_GATE_DIS 15 15 XDMA_SCLK_G_MSTAT_GATE_DIS 19 19 XDMA_SCLK_G_SDYN_GATE_DIS 18 18 XDMA_SCLK_G_SSTAT_GATE_DIS 20 20 XDMA_SCLK_REG_GATE_DIS 16 16 XDMA_SCLK_TURN_OFF_DELAY 4 11 XDMA_SCLK_TURN_ON_DELAY 0 3 mmXDMA_IF_BIF_STATUS 0 0x418 2 0 4294967295 XDMA_IF_BIF_ERROR_CLEAR 8 8 XDMA_IF_BIF_ERROR_STATUS 0 3 mmXDMA_INTERRUPT 0 0x406 9 0 4294967295 XDMA_MSTR_MEM_URGENT_ACK 10 10 XDMA_MSTR_MEM_URGENT_MASK 9 9 XDMA_MSTR_MEM_URGENT_STAT 8 8 XDMA_MSTR_UNDERFLOW_ACK 14 14 XDMA_MSTR_UNDERFLOW_MASK 13 13 XDMA_MSTR_UNDERFLOW_STAT 12 12 XDMA_SLV_READ_URGENT_ACK 18 18 XDMA_SLV_READ_URGENT_MASK 17 17 XDMA_SLV_READ_URGENT_STAT 16 16 mmXDMA_LOCAL_SURFACE_TILING1 0 0x3f4 6 0 4294967295 XDMA_LOCAL_ARRAY_MODE 0 3 XDMA_LOCAL_BANK_HEIGHT 10 11 XDMA_LOCAL_BANK_WIDTH 8 9 XDMA_LOCAL_MACRO_TILE_ASPECT 12 13 XDMA_LOCAL_NUM_BANKS 20 21 XDMA_LOCAL_TILE_SPLIT 4 6 mmXDMA_LOCAL_SURFACE_TILING2 0 0x3f5 3 0 4294967295 XDMA_LOCAL_MICRO_TILE_MODE 22 23 XDMA_LOCAL_PIPE_CONFIG 27 31 XDMA_LOCAL_PIPE_INTERLEAVE_SIZE 0 2 mmXDMA_MC_PCIE_CLIENT_CONFIG 0 0x3e9 3 0 4294967295 XDMA_MC_PCIE_PRIV 16 16 XDMA_MC_PCIE_SWAP 8 9 XDMA_MC_PCIE_VMID 12 15 mmXDMA_MEM_POWER_CNTL 0 0x40b 5 0 4294967295 XDMA_MEM_LIGHT_SLEEP_DIS 0 0 XDMA_MEM_LIGHT_SLEEP_MODE_FORCE 16 16 XDMA_MEM_POWER_STATE 30 31 XDMA_MEM_SHUTDOWN_DIS 8 8 XDMA_MEM_SHUTDOWN_MODE_FORCE 24 24 mmXDMA_MSTR_CMD_URGENT_CNTL 0 0x3f6 1 0 4294967295 XDMA_MSTR_CMD_URGENT_LEVEL 8 11 mmXDMA_MSTR_CNTL 0 0x3e0 4 0 4294967295 XDMA_MSTR_DEBUG_MODE 18 18 XDMA_MSTR_ENABLE 16 16 XDMA_MSTR_MEM_READY 9 9 XDMA_MSTR_SOFT_RESET 20 20 mmXDMA_MSTR_HEIGHT 0 0x3e3 2 0 4294967295 XDMA_MSTR_ACTIVE_HEIGHT 0 13 XDMA_MSTR_FRAME_HEIGHT 16 29 mmXDMA_MSTR_LOCAL_SURFACE_BASE_ADDR 0 0x3f1 1 0 4294967295 XDMA_MSTR_LOCAL_SURFACE_BASE_ADDR 0 31 mmXDMA_MSTR_LOCAL_SURFACE_BASE_ADDR_HIGH 0 0x3f2 1 0 4294967295 XDMA_MSTR_LOCAL_SURFACE_BASE_ADDR_HIGH 0 7 mmXDMA_MSTR_LOCAL_SURFACE_PITCH 0 0x3f3 1 0 4294967295 XDMA_MSTR_LOCAL_SURFACE_PITCH 0 13 mmXDMA_MSTR_MEM_CLIENT_CONFIG 0 0x3ea 3 0 4294967295 XDMA_MSTR_MEM_CLIENT_PRIV 16 16 XDMA_MSTR_MEM_CLIENT_SWAP 8 9 XDMA_MSTR_MEM_CLIENT_VMID 12 15 mmXDMA_MSTR_MEM_NACK_STATUS 0 0x40d 3 0 4294967295 XDMA_MSTR_MEM_NACK_CLR 16 16 XDMA_MSTR_MEM_NACK 12 13 XDMA_MSTR_MEM_NACK_TAG 0 9 mmXDMA_MSTR_MEM_URGENT_CNTL 0 0x3f7 5 0 4294967295 XDMA_MSTR_MEM_CLIENT_STALL 0 0 XDMA_MSTR_MEM_STALL_DELAY 12 15 XDMA_MSTR_MEM_URGENT_LEVEL 8 11 XDMA_MSTR_MEM_URGENT_LIMIT 4 7 XDMA_MSTR_MEM_URGENT_TIMER 16 31 mmXDMA_MSTR_PCIE_NACK_STATUS 0 0x40c 3 0 4294967295 XDMA_MSTR_PCIE_NACK_CLR 16 16 XDMA_MSTR_PCIE_NACK 12 13 XDMA_MSTR_PCIE_NACK_TAG 0 9 mmXDMA_MSTR_READ_COMMAND 0 0x3e1 2 0 4294967295 XDMA_MSTR_REQUEST_PREFETCH 16 29 XDMA_MSTR_REQUEST_SIZE 0 13 mmXDMA_MSTR_REMOTE_GPU_ADDRESS 0 0x3e6 1 0 4294967295 XDMA_MSTR_REMOTE_GPU_ADDRESS 0 31 mmXDMA_MSTR_REMOTE_GPU_ADDRESS_HIGH 0 0x3e7 1 0 4294967295 XDMA_MSTR_REMOTE_GPU_ADDRESS_HIGH 0 7 mmXDMA_MSTR_REMOTE_SURFACE_BASE 0 0x3e4 1 0 4294967295 XDMA_MSTR_REMOTE_SURFACE_BASE 0 31 mmXDMA_MSTR_REMOTE_SURFACE_BASE_HIGH 0 0x3e5 1 0 4294967295 XDMA_MSTR_REMOTE_SURFACE_BASE_HIGH 0 7 mmXDMA_MSTR_STATUS 0 0x3e8 2 0 4294967295 XDMA_MSTR_VCOUNT_CURRENT 0 13 XDMA_MSTR_WRITE_LINE_CURRENT 16 29 mmXDMA_RBBMIF_RDWR_CNTL 0 0x40a 3 0 4294967295 XDMA_RBBMIF_RDWR_DELAY 0 2 XDMA_RBBMIF_RDWR_TIMEOUT_DIS 3 3 XDMA_RBBMIF_TIMEOUT_DELAY 15 31 mmXDMA_SLV_CNTL 0 0x3fb 5 0 4294967295 XDMA_SLV_ACTIVE 8 8 XDMA_SLV_ENABLE 16 16 XDMA_SLV_MEM_READY 9 9 XDMA_SLV_READ_LAT_TEST_EN 19 19 XDMA_SLV_SOFT_RESET 20 20 mmXDMA_SLV_FLIP_PENDING 0 0x407 1 0 4294967295 XDMA_SLV_FLIP_PENDING 0 0 mmXDMA_SLV_MEM_CLIENT_CONFIG 0 0x3fd 3 0 4294967295 XDMA_SLV_MEM_CLIENT_PRIV 16 16 XDMA_SLV_MEM_CLIENT_SWAP 8 9 XDMA_SLV_MEM_CLIENT_VMID 12 15 mmXDMA_SLV_MEM_NACK_STATUS 0 0x40f 3 0 4294967295 XDMA_SLV_MEM_NACK_CLR 31 31 XDMA_SLV_MEM_NACK 16 17 XDMA_SLV_MEM_NACK_TAG 0 15 mmXDMA_SLV_PCIE_NACK_STATUS 0 0x40e 3 0 4294967295 XDMA_SLV_PCIE_NACK_CLR 16 16 XDMA_SLV_PCIE_NACK 12 13 XDMA_SLV_PCIE_NACK_TAG 0 9 mmXDMA_SLV_READ_LATENCY_AVE 0 0x405 2 0 4294967295 XDMA_SLV_READ_LATENCY_ACC 0 19 XDMA_SLV_READ_LATENCY_COUNT 20 31 mmXDMA_SLV_READ_LATENCY_MINMAX 0 0x404 2 0 4294967295 XDMA_SLV_READ_LATENCY_MAX 16 31 XDMA_SLV_READ_LATENCY_MIN 0 15 mmXDMA_SLV_READ_LATENCY_TIMER 0 0x412 1 0 4294967295 XDMA_SLV_READ_LATENCY_TIMER 0 15 mmXDMA_SLV_READ_URGENT_CNTL 0 0x3ff 5 0 4294967295 XDMA_SLV_READ_CLIENT_STALL 0 0 XDMA_SLV_READ_STALL_DELAY 12 15 XDMA_SLV_READ_URGENT_LEVEL 8 11 XDMA_SLV_READ_URGENT_LIMIT 4 7 XDMA_SLV_READ_URGENT_TIMER 16 31 mmXDMA_SLV_REMOTE_GPU_ADDRESS 0 0x402 1 0 4294967295 XDMA_SLV_REMOTE_GPU_ADDRESS 0 31 mmXDMA_SLV_REMOTE_GPU_ADDRESS_HIGH 0 0x403 1 0 4294967295 XDMA_SLV_REMOTE_GPU_ADDRESS_HIGH 0 7 mmXDMA_SLV_SLS_PITCH 0 0x3fe 2 0 4294967295 XDMA_SLV_SLS_PITCH 0 13 XDMA_SLV_SLS_WIDTH 16 29 mmXDMA_SLV_WB_RATE_CNTL 0 0x401 2 0 4294967295 XDMA_SLV_WB_BURST_PERIOD 16 31 XDMA_SLV_WB_BURST_SIZE 0 8 mmXDMA_SLV_WRITE_URGENT_CNTL 0 0x400 3 0 4294967295 XDMA_SLV_WRITE_STALL_DELAY 12 15 XDMA_SLV_WRITE_STALL 0 0 XDMA_SLV_WRITE_URGENT_LEVEL 8 11 mmXDMA_TEST_DEBUG_DATA 0 0x41d 1 0 4294967295 XDMA_TEST_DEBUG_DATA 0 31 mmXDMA_TEST_DEBUG_INDEX 0 0x41c 2 0 4294967295 XDMA_TEST_DEBUG_INDEX 0 7 XDMA_TEST_DEBUG_WRITE_EN 8 8 mmDATA_FORMAT 0 0x1ac0 6 0 4294967295 INTERLEAVE_EN 0 0 RESET_REQ_AT_EOL 4 4 PREFETCH 12 12 SOF_READ_PT 16 20 REQUEST_MODE 24 25 ALLOW_REQ_MODE_1_2 28 28 mmLB0_DATA_FORMAT 0 0x1ac0 0 0 4294967295 mmLB1_DATA_FORMAT 0 0x1dc0 0 0 4294967295 mmLB2_DATA_FORMAT 0 0x40c0 0 0 4294967295 mmLB3_DATA_FORMAT 0 0x43c0 0 0 4294967295 mmLB4_DATA_FORMAT 0 0x46c0 0 0 4294967295 mmLB5_DATA_FORMAT 0 0x49c0 0 0 4294967295 mmDESKTOP_HEIGHT 0 0x1ac1 0 0 4294967295 mmLB0_DESKTOP_HEIGHT 0 0x1ac1 0 0 4294967295 mmLB1_DESKTOP_HEIGHT 0 0x1dc1 0 0 4294967295 mmLB2_DESKTOP_HEIGHT 0 0x40c1 0 0 4294967295 mmLB3_DESKTOP_HEIGHT 0 0x43c1 0 0 4294967295 mmLB4_DESKTOP_HEIGHT 0 0x46c1 0 0 4294967295 mmLB5_DESKTOP_HEIGHT 0 0x49c1 0 0 4294967295 mmDC_LB_MEMORY_SPLIT 0 0x1ac3 2 0 4294967295 LB_NUM_PARTITIONS 16 19 DC_LB_MEMORY_CONFIG 20 21 mmLB0_DC_LB_MEMORY_SPLIT 0 0x1ac3 0 0 4294967295 mmLB1_DC_LB_MEMORY_SPLIT 0 0x1dc3 0 0 4294967295 mmLB2_DC_LB_MEMORY_SPLIT 0 0x40c3 0 0 4294967295 mmLB3_DC_LB_MEMORY_SPLIT 0 0x43c3 0 0 4294967295 mmLB4_DC_LB_MEMORY_SPLIT 0 0x46c3 0 0 4294967295 mmLB5_DC_LB_MEMORY_SPLIT 0 0x49c3 0 0 4294967295 mmDC_LB_MEM_SIZE 0 0x1ac4 1 0 4294967295 DC_LB_MEM_SIZE 0 10 mmLB0_DC_LB_MEM_SIZE 0 0x1ac4 0 0 4294967295 mmLB1_DC_LB_MEM_SIZE 0 0x1dc4 0 0 4294967295 mmLB2_DC_LB_MEM_SIZE 0 0x40c4 0 0 4294967295 mmLB3_DC_LB_MEM_SIZE 0 0x43c4 0 0 4294967295 mmLB4_DC_LB_MEM_SIZE 0 0x46c4 0 0 4294967295 mmLB5_DC_LB_MEM_SIZE 0 0x49c4 0 0 4294967295 mmPRIORITY_A_CNT 0 0x1ac6 4 0 4294967295 PRIORITY_MARK_A 0 14 PRIORITY_A_OFF 16 16 PRIORITY_A_ALWAYS_ON 20 20 PRIORITY_A_FORCE_MASK 24 24 mmLB0_PRIORITY_A_CNT 0 0x1ac6 0 0 4294967295 mmLB1_PRIORITY_A_CNT 0 0x1dc6 0 0 4294967295 mmLB2_PRIORITY_A_CNT 0 0x40c6 0 0 4294967295 mmLB3_PRIORITY_A_CNT 0 0x43c6 0 0 4294967295 mmLB4_PRIORITY_A_CNT 0 0x46c6 0 0 4294967295 mmLB5_PRIORITY_A_CNT 0 0x49c6 0 0 4294967295 mmPRIORITY_B_CNT 0 0x1ac7 4 0 4294967295 PRIORITY_MARK_B 0 14 PRIORITY_B_OFF 16 16 PRIORITY_B_ALWAYS_ON 20 20 PRIORITY_B_FORCE_MASK 24 24 mmLB0_PRIORITY_B_CNT 0 0x1ac7 0 0 4294967295 mmLB1_PRIORITY_B_CNT 0 0x1dc7 0 0 4294967295 mmLB2_PRIORITY_B_CNT 0 0x40c7 0 0 4294967295 mmLB3_PRIORITY_B_CNT 0 0x43c7 0 0 4294967295 mmLB4_PRIORITY_B_CNT 0 0x46c7 0 0 4294967295 mmLB5_PRIORITY_B_CNT 0 0x49c7 0 0 4294967295 mmDPG_PIPE_ARBITRATION_CONTROL3 0 0x1b32 1 0 4294967295 URGENCY_WATERMARK_MASK 16 17 mmDMIF_PG0_DPG_PIPE_ARBITRATION_CONTROL3 0 0x1b32 0 0 4294967295 mmDMIF_PG1_DPG_PIPE_ARBITRATION_CONTROL3 0 0x1e32 0 0 4294967295 mmDMIF_PG2_DPG_PIPE_ARBITRATION_CONTROL3 0 0x4132 0 0 4294967295 mmDMIF_PG3_DPG_PIPE_ARBITRATION_CONTROL3 0 0x4432 0 0 4294967295 mmDMIF_PG4_DPG_PIPE_ARBITRATION_CONTROL3 0 0x4732 0 0 4294967295 mmDMIF_PG5_DPG_PIPE_ARBITRATION_CONTROL3 0 0x4a32 0 0 4294967295 mmINT_MASK 0 0x1ad0 2 0 4294967295 VBLANK_INT 0 0 VLINE_INT 4 4 mmLB0_INT_MASK 0 0x1ad0 0 0 4294967295 mmLB1_INT_MASK 0 0x1dd0 0 0 4294967295 mmLB2_INT_MASK 0 0x40d0 0 0 4294967295 mmLB3_INT_MASK 0 0x43d0 0 0 4294967295 mmLB4_INT_MASK 0 0x46d0 0 0 4294967295 mmLB5_INT_MASK 0 0x49d0 0 0 4294967295 mmVLINE_STATUS 0 0x1aee 5 0 4294967295 VLINE_OCCURRED 0 0 VLINE_ACK 4 4 VLINE_STAT 12 12 VLINE_INTERRUPT 16 16 VLINE_INTERRUPT_TYPE 17 17 mmLB0_VLINE_STATUS 0 0x1aee 0 0 4294967295 mmLB1_VLINE_STATUS 0 0x1dee 0 0 4294967295 mmLB2_VLINE_STATUS 0 0x40ee 0 0 4294967295 mmLB3_VLINE_STATUS 0 0x43ee 0 0 4294967295 mmLB4_VLINE_STATUS 0 0x46ee 0 0 4294967295 mmLB5_VLINE_STATUS 0 0x49ee 0 0 4294967295 mmVBLANK_STATUS 0 0x1aef 5 0 4294967295 VBLANK_OCCURRED 0 0 VBLANK_ACK 4 4 VBLANK_STAT 12 12 VBLANK_INTERRUPT 16 16 VBLANK_INTERRUPT_TYPE 17 17 mmLB0_VBLANK_STATUS 0 0x1aef 0 0 4294967295 mmLB1_VBLANK_STATUS 0 0x1def 0 0 4294967295 mmLB2_VBLANK_STATUS 0 0x40ef 0 0 4294967295 mmLB3_VBLANK_STATUS 0 0x43ef 0 0 4294967295 mmLB4_VBLANK_STATUS 0 0x46ef 0 0 4294967295 mmLB5_VBLANK_STATUS 0 0x49ef 0 0 4294967295 mmSCL_HORZ_FILTER_INIT_RGB_LUMA 0 0x1b4c 2 0 4294967295 SCL_H_INIT_FRAC_RGB_Y 0 15 SCL_H_INIT_INT_RGB_Y 16 19 mmSCL0_SCL_HORZ_FILTER_INIT_RGB_LUMA 0 0x1b4c 0 0 4294967295 mmSCL1_SCL_HORZ_FILTER_INIT_RGB_LUMA 0 0x1e4c 0 0 4294967295 mmSCL2_SCL_HORZ_FILTER_INIT_RGB_LUMA 0 0x414c 0 0 4294967295 mmSCL3_SCL_HORZ_FILTER_INIT_RGB_LUMA 0 0x444c 0 0 4294967295 mmSCL4_SCL_HORZ_FILTER_INIT_RGB_LUMA 0 0x474c 0 0 4294967295 mmSCL5_SCL_HORZ_FILTER_INIT_RGB_LUMA 0 0x4a4c 0 0 4294967295 mmSCL_HORZ_FILTER_INIT_CHROMA 0 0x1b4d 2 0 4294967295 SCL_H_INIT_FRAC_CBCR 0 15 SCL_H_INIT_INT_CBCR 16 18 mmSCL0_SCL_HORZ_FILTER_INIT_CHROMA 0 0x1b4d 0 0 4294967295 mmSCL1_SCL_HORZ_FILTER_INIT_CHROMA 0 0x1e4d 0 0 4294967295 mmSCL2_SCL_HORZ_FILTER_INIT_CHROMA 0 0x414d 0 0 4294967295 mmSCL3_SCL_HORZ_FILTER_INIT_CHROMA 0 0x444d 0 0 4294967295 mmSCL4_SCL_HORZ_FILTER_INIT_CHROMA 0 0x474d 0 0 4294967295 mmSCL5_SCL_HORZ_FILTER_INIT_CHROMA 0 0x4a4d 0 0 4294967295