6954 mmVGA_MEM_WRITE_PAGE_ADDR 0 0x0 2 0 0 VGA_MEM_WRITE_PAGE0_ADDR 0 9 VGA_MEM_WRITE_PAGE1_ADDR 16 25 mmVGA_MEM_READ_PAGE_ADDR 0 0x1 2 0 0 VGA_MEM_READ_PAGE0_ADDR 0 9 VGA_MEM_READ_PAGE1_ADDR 16 25 mmCRTC8_IDX 0 0x2d 1 0 1 VCRTC_IDX 0 5 mmCRTC8_DATA 0 0x2d 1 0 1 VCRTC_DATA 0 7 mmGENFC_WT 0 0x2e 1 0 1 VSYNC_SEL_W 3 3 mmGENS1 0 0x2e 3 0 1 NO_DISPLAY 0 0 VGA_VSTATUS 3 3 PIXEL_READ_BACK 4 5 mmATTRDW 0 0x30 1 0 1 ATTR_DATA 0 7 mmATTRX 0 0x30 2 0 1 ATTR_IDX 0 4 ATTR_PAL_RW_ENB 5 5 mmATTRDR 0 0x30 1 0 1 ATTR_DATA 0 7 mmGENMO_WT 0 0x30 6 0 1 GENMO_MONO_ADDRESS_B 0 0 VGA_RAM_EN 1 1 VGA_CKSEL 2 3 ODD_EVEN_MD_PGSEL 5 5 VGA_HSYNC_POL 6 6 VGA_VSYNC_POL 7 7 mmGENS0 0 0x30 2 0 1 SENSE_SWITCH 4 4 CRT_INTR 7 7 mmGENENB 0 0x30 1 0 1 BLK_IO_BASE 0 7 mmSEQ8_IDX 0 0x31 1 0 1 SEQ_IDX 0 2 mmSEQ8_DATA 0 0x31 1 0 1 SEQ_DATA 0 7 mmDAC_MASK 0 0x31 1 0 1 DAC_MASK 0 7 mmDAC_R_INDEX 0 0x31 1 0 1 DAC_R_INDEX 0 7 mmDAC_W_INDEX 0 0x32 1 0 1 DAC_W_INDEX 0 7 mmDAC_DATA 0 0x32 1 0 1 DAC_DATA 0 5 mmGENFC_RD 0 0x32 1 0 1 VSYNC_SEL_R 3 3 mmGENMO_RD 0 0x33 6 0 1 GENMO_MONO_ADDRESS_B 0 0 VGA_RAM_EN 1 1 VGA_CKSEL 2 3 ODD_EVEN_MD_PGSEL 5 5 VGA_HSYNC_POL 6 6 VGA_VSYNC_POL 7 7 mmGRPH8_IDX 0 0x33 1 0 1 GRPH_IDX 0 3 mmGRPH8_DATA 0 0x33 1 0 1 GRPH_DATA 0 7 mmCRTC8_IDX_1 0 0x35 1 0 1 VCRTC_IDX 0 5 mmCRTC8_DATA_1 0 0x35 1 0 1 VCRTC_DATA 0 7 mmGENFC_WT_1 0 0x36 1 0 1 VSYNC_SEL_W 3 3 mmGENS1_1 0 0x36 3 0 1 NO_DISPLAY 0 0 VGA_VSTATUS 3 3 PIXEL_READ_BACK 4 5 mmCORB_WRITE_POINTER 0 0x0 1 0 0 CORB_WRITE_POINTER 0 7 mmCORB_READ_POINTER 0 0x0 2 0 0 CORB_READ_POINTER 0 7 CORB_READ_POINTER_RESET 15 15 mmCORB_CONTROL 0 0x1 2 0 0 CORB_MEMORY_ERROR_INTERRUPT_ENABLE 0 0 ENABLE_CORB_DMA_ENGINE 1 1 mmCORB_STATUS 0 0x1 1 0 0 CORB_MEMORY_ERROR_INDICATION 0 0 mmCORB_SIZE 0 0x1 2 0 0 CORB_SIZE 0 1 CORB_SIZE_CAPABILITY 4 7 mmRIRB_LOWER_BASE_ADDRESS 0 0x2 2 0 0 RIRB_LOWER_BASE_UNIMPLEMENTED_BITS 0 6 RIRB_LOWER_BASE_ADDRESS 7 31 mmRIRB_UPPER_BASE_ADDRESS 0 0x3 1 0 0 RIRB_UPPER_BASE_ADDRESS 0 31 mmRIRB_WRITE_POINTER 0 0x4 2 0 0 RIRB_WRITE_POINTER 0 7 RIRB_WRITE_POINTER_RESET 15 15 mmRESPONSE_INTERRUPT_COUNT 0 0x4 1 0 0 N_RESPONSE_INTERRUPT_COUNT 0 7 mmRIRB_CONTROL 0 0x5 3 0 0 RESPONSE_INTERRUPT_CONTROL 0 0 RIRB_DMA_ENABLE 1 1 RESPONSE_OVERRUN_INTERRUPT_CONTROL 2 2 mmRIRB_STATUS 0 0x5 2 0 0 RESPONSE_INTERRUPT 0 0 RESPONSE_OVERRUN_INTERRUPT_STATUS 2 2 mmRIRB_SIZE 0 0x5 2 0 0 RIRB_SIZE 0 1 RIRB_SIZE_CAPABILITY 4 7 mmIMMEDIATE_COMMAND_OUTPUT_INTERFACE 0 0x6 2 0 0 IMMEDIATE_COMMAND_WRITE_VERB_AND_PAYLOAD 0 27 IMMEDIATE_COMMAND_WRITE_CODEC_ADDRESS 28 31 mmIMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA 0 0x6 1 0 0 IMMEDIATE_COMMAND_WRITE 0 31 mmIMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX 0 0x6 1 0 0 IMMEDIATE_COMMAND_WRITE 0 15 mmIMMEDIATE_RESPONSE_INPUT_INTERFACE 0 0x7 1 0 0 IMMEDIATE_RESPONSE_READ 0 31 mmIMMEDIATE_COMMAND_STATUS 0 0x8 2 0 0 IMMEDIATE_COMMAND_BUSY 0 0 IMMEDIATE_RESULT_VALID 1 1 mmDMA_POSITION_LOWER_BASE_ADDRESS 0 0xa 3 0 0 DMA_POSITION_BUFFER_ENABLE 0 0 DMA_POSITION_LOWER_BASE_UNIMPLEMENTED_BITS 1 6 DMA_POSITION_LOWER_BASE_ADDRESS 7 31 mmDMA_POSITION_UPPER_BASE_ADDRESS 0 0xb 1 0 0 DMA_POSITION_UPPER_BASE_ADDRESS 0 31 mmWALL_CLOCK_COUNTER_ALIAS 0 0x74c 1 0 1 WALL_CLOCK_COUNTER_ALIAS 0 31 mmAZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA 0 0x6 1 0 0 IMMEDIATE_COMMAND_WRITE 0 31 mmAZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX 0 0x6 1 0 0 IMMEDIATE_COMMAND_WRITE 0 16 mmAZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_DATA 0 0x6 1 0 0 IMMEDIATE_COMMAND_WRITE 0 31 mmAZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_INDEX 0 0x6 1 0 0 IMMEDIATE_COMMAND_WRITE 0 16 mmAZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA 0 0x6 1 0 0 IMMEDIATE_COMMAND_WRITE 0 31 mmAZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX 0 0x6 1 0 0 IMMEDIATE_COMMAND_WRITE 0 16 mmAZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS 0 0xe 12 0 0 STREAM_RESET 0 0 STREAM_RUN 1 1 INTERRUPT_ON_COMPLETION_ENABLE 2 2 FIFO_ERROR_INTERRUPT_ENABLE 3 3 DESCRIPTOR_ERROR_INTERRUPT_ENABLE 4 4 STRIPE_CONTROL 16 17 TRAFFIC_PRIORITY 18 18 STREAM_NUMBER 20 23 BUFFER_COMPLETION_INTERRUPT_STATUS 26 26 FIFO_ERROR 27 27 DESCRIPTOR_ERROR 28 28 FIFO_READY 29 29 mmAZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER 0 0xf 1 0 0 LINK_POSITION_IN_BUFFER 0 31 mmAZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH 0 0x10 1 0 0 CYCLIC_BUFFER_LENGTH 0 31 mmAZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX 0 0x11 1 0 0 LAST_VALID_INDEX 0 7 mmAZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE 0 0x12 1 0 0 FIFO_SIZE 0 15 mmAZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT 0 0x12 5 0 0 NUMBER_OF_CHANNELS 0 3 BITS_PER_SAMPLE 4 6 SAMPLE_BASE_DIVISOR 8 10 SAMPLE_BASE_MULTIPLE 11 13 SAMPLE_BASE_RATE 14 14 mmAZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS 0 0x14 2 0 0 BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_UNIMPLEMENTED_BITS 0 6 BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS 7 31 mmAZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS 0 0x15 1 0 0 BUFFER_DESCRIPTOR_LIST_UPPER_BASE_ADDRESS 0 31 mmAZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS 0 0x761 1 0 1 LINK_POSITION_IN_BUFFER_ALIAS 0 31 mmAZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS 0 0x16 12 0 0 STREAM_RESET 0 0 STREAM_RUN 1 1 INTERRUPT_ON_COMPLETION_ENABLE 2 2 FIFO_ERROR_INTERRUPT_ENABLE 3 3 DESCRIPTOR_ERROR_INTERRUPT_ENABLE 4 4 STRIPE_CONTROL 16 17 TRAFFIC_PRIORITY 18 18 STREAM_NUMBER 20 23 BUFFER_COMPLETION_INTERRUPT_STATUS 26 26 FIFO_ERROR 27 27 DESCRIPTOR_ERROR 28 28 FIFO_READY 29 29 mmAZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER 0 0x17 1 0 0 LINK_POSITION_IN_BUFFER 0 31 mmAZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH 0 0x18 1 0 0 CYCLIC_BUFFER_LENGTH 0 31 mmAZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX 0 0x19 1 0 0 LAST_VALID_INDEX 0 7 mmAZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE 0 0x1a 1 0 0 FIFO_SIZE 0 15 mmAZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT 0 0x1a 5 0 0 NUMBER_OF_CHANNELS 0 3 BITS_PER_SAMPLE 4 6 SAMPLE_BASE_DIVISOR 8 10 SAMPLE_BASE_MULTIPLE 11 13 SAMPLE_BASE_RATE 14 14 mmAZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS 0 0x1c 2 0 0 BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_UNIMPLEMENTED_BITS 0 6 BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS 7 31 mmAZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS 0 0x1d 1 0 0 BUFFER_DESCRIPTOR_LIST_UPPER_BASE_ADDRESS 0 31 mmAZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS 0 0x769 1 0 1 LINK_POSITION_IN_BUFFER_ALIAS 0 31 mmAZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS 0 0x1e 12 0 0 STREAM_RESET 0 0 STREAM_RUN 1 1 INTERRUPT_ON_COMPLETION_ENABLE 2 2 FIFO_ERROR_INTERRUPT_ENABLE 3 3 DESCRIPTOR_ERROR_INTERRUPT_ENABLE 4 4 STRIPE_CONTROL 16 17 TRAFFIC_PRIORITY 18 18 STREAM_NUMBER 20 23 BUFFER_COMPLETION_INTERRUPT_STATUS 26 26 FIFO_ERROR 27 27 DESCRIPTOR_ERROR 28 28 FIFO_READY 29 29 mmAZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER 0 0x1f 1 0 0 LINK_POSITION_IN_BUFFER 0 31 mmAZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH 0 0x20 1 0 0 CYCLIC_BUFFER_LENGTH 0 31 mmAZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX 0 0x21 1 0 0 LAST_VALID_INDEX 0 7 mmAZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE 0 0x22 1 0 0 FIFO_SIZE 0 15 mmAZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT 0 0x22 5 0 0 NUMBER_OF_CHANNELS 0 3 BITS_PER_SAMPLE 4 6 SAMPLE_BASE_DIVISOR 8 10 SAMPLE_BASE_MULTIPLE 11 13 SAMPLE_BASE_RATE 14 14 mmAZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS 0 0x24 2 0 0 BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_UNIMPLEMENTED_BITS 0 6 BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS 7 31 mmAZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS 0 0x25 1 0 0 BUFFER_DESCRIPTOR_LIST_UPPER_BASE_ADDRESS 0 31 mmAZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS 0 0x771 1 0 1 LINK_POSITION_IN_BUFFER_ALIAS 0 31 mmAZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS 0 0x26 12 0 0 STREAM_RESET 0 0 STREAM_RUN 1 1 INTERRUPT_ON_COMPLETION_ENABLE 2 2 FIFO_ERROR_INTERRUPT_ENABLE 3 3 DESCRIPTOR_ERROR_INTERRUPT_ENABLE 4 4 STRIPE_CONTROL 16 17 TRAFFIC_PRIORITY 18 18 STREAM_NUMBER 20 23 BUFFER_COMPLETION_INTERRUPT_STATUS 26 26 FIFO_ERROR 27 27 DESCRIPTOR_ERROR 28 28 FIFO_READY 29 29 mmAZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER 0 0x27 1 0 0 LINK_POSITION_IN_BUFFER 0 31 mmAZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH 0 0x28 1 0 0 CYCLIC_BUFFER_LENGTH 0 31 mmAZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX 0 0x29 1 0 0 LAST_VALID_INDEX 0 7 mmAZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE 0 0x2a 1 0 0 FIFO_SIZE 0 15 mmAZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT 0 0x2a 5 0 0 NUMBER_OF_CHANNELS 0 3 BITS_PER_SAMPLE 4 6 SAMPLE_BASE_DIVISOR 8 10 SAMPLE_BASE_MULTIPLE 11 13 SAMPLE_BASE_RATE 14 14 mmAZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS 0 0x2c 2 0 0 BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_UNIMPLEMENTED_BITS 0 6 BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS 7 31 mmAZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS 0 0x2d 1 0 0 BUFFER_DESCRIPTOR_LIST_UPPER_BASE_ADDRESS 0 31 mmAZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS 0 0x779 1 0 1 LINK_POSITION_IN_BUFFER_ALIAS 0 31 mmAZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS 0 0x2e 12 0 0 STREAM_RESET 0 0 STREAM_RUN 1 1 INTERRUPT_ON_COMPLETION_ENABLE 2 2 FIFO_ERROR_INTERRUPT_ENABLE 3 3 DESCRIPTOR_ERROR_INTERRUPT_ENABLE 4 4 STRIPE_CONTROL 16 17 TRAFFIC_PRIORITY 18 18 STREAM_NUMBER 20 23 BUFFER_COMPLETION_INTERRUPT_STATUS 26 26 FIFO_ERROR 27 27 DESCRIPTOR_ERROR 28 28 FIFO_READY 29 29 mmAZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER 0 0x2f 1 0 0 LINK_POSITION_IN_BUFFER 0 31 mmAZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH 0 0x30 1 0 0 CYCLIC_BUFFER_LENGTH 0 31 mmAZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX 0 0x31 1 0 0 LAST_VALID_INDEX 0 7 mmAZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE 0 0x32 1 0 0 FIFO_SIZE 0 15 mmAZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT 0 0x32 5 0 0 NUMBER_OF_CHANNELS 0 3 BITS_PER_SAMPLE 4 6 SAMPLE_BASE_DIVISOR 8 10 SAMPLE_BASE_MULTIPLE 11 13 SAMPLE_BASE_RATE 14 14 mmAZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS 0 0x34 2 0 0 BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_UNIMPLEMENTED_BITS 0 6 BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS 7 31 mmAZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS 0 0x35 1 0 0 BUFFER_DESCRIPTOR_LIST_UPPER_BASE_ADDRESS 0 31 mmAZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS 0 0x781 1 0 1 LINK_POSITION_IN_BUFFER_ALIAS 0 31 mmAZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS 0 0x36 12 0 0 STREAM_RESET 0 0 STREAM_RUN 1 1 INTERRUPT_ON_COMPLETION_ENABLE 2 2 FIFO_ERROR_INTERRUPT_ENABLE 3 3 DESCRIPTOR_ERROR_INTERRUPT_ENABLE 4 4 STRIPE_CONTROL 16 17 TRAFFIC_PRIORITY 18 18 STREAM_NUMBER 20 23 BUFFER_COMPLETION_INTERRUPT_STATUS 26 26 FIFO_ERROR 27 27 DESCRIPTOR_ERROR 28 28 FIFO_READY 29 29 mmAZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER 0 0x37 1 0 0 LINK_POSITION_IN_BUFFER 0 31 mmAZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH 0 0x38 1 0 0 CYCLIC_BUFFER_LENGTH 0 31 mmAZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX 0 0x39 1 0 0 LAST_VALID_INDEX 0 7 mmAZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE 0 0x3a 1 0 0 FIFO_SIZE 0 15 mmAZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT 0 0x3a 5 0 0 NUMBER_OF_CHANNELS 0 3 BITS_PER_SAMPLE 4 6 SAMPLE_BASE_DIVISOR 8 10 SAMPLE_BASE_MULTIPLE 11 13 SAMPLE_BASE_RATE 14 14 mmAZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS 0 0x3c 2 0 0 BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_UNIMPLEMENTED_BITS 0 6 BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS 7 31 mmAZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS 0 0x3d 1 0 0 BUFFER_DESCRIPTOR_LIST_UPPER_BASE_ADDRESS 0 31 mmAZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS 0 0x789 1 0 1 LINK_POSITION_IN_BUFFER_ALIAS 0 31 mmAZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS 0 0x3e 12 0 0 STREAM_RESET 0 0 STREAM_RUN 1 1 INTERRUPT_ON_COMPLETION_ENABLE 2 2 FIFO_ERROR_INTERRUPT_ENABLE 3 3 DESCRIPTOR_ERROR_INTERRUPT_ENABLE 4 4 STRIPE_CONTROL 16 17 TRAFFIC_PRIORITY 18 18 STREAM_NUMBER 20 23 BUFFER_COMPLETION_INTERRUPT_STATUS 26 26 FIFO_ERROR 27 27 DESCRIPTOR_ERROR 28 28 FIFO_READY 29 29 mmAZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER 0 0x3f 1 0 0 LINK_POSITION_IN_BUFFER 0 31 mmAZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH 0 0x40 1 0 0 CYCLIC_BUFFER_LENGTH 0 31 mmAZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX 0 0x41 1 0 0 LAST_VALID_INDEX 0 7 mmAZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE 0 0x42 1 0 0 FIFO_SIZE 0 15 mmAZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT 0 0x42 5 0 0 NUMBER_OF_CHANNELS 0 3 BITS_PER_SAMPLE 4 6 SAMPLE_BASE_DIVISOR 8 10 SAMPLE_BASE_MULTIPLE 11 13 SAMPLE_BASE_RATE 14 14 mmAZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS 0 0x44 2 0 0 BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_UNIMPLEMENTED_BITS 0 6 BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS 7 31 mmAZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS 0 0x45 1 0 0 BUFFER_DESCRIPTOR_LIST_UPPER_BASE_ADDRESS 0 31 mmAZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS 0 0x791 1 0 1 LINK_POSITION_IN_BUFFER_ALIAS 0 31 mmAZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS 0 0x46 12 0 0 STREAM_RESET 0 0 STREAM_RUN 1 1 INTERRUPT_ON_COMPLETION_ENABLE 2 2 FIFO_ERROR_INTERRUPT_ENABLE 3 3 DESCRIPTOR_ERROR_INTERRUPT_ENABLE 4 4 STRIPE_CONTROL 16 17 TRAFFIC_PRIORITY 18 18 STREAM_NUMBER 20 23 BUFFER_COMPLETION_INTERRUPT_STATUS 26 26 FIFO_ERROR 27 27 DESCRIPTOR_ERROR 28 28 FIFO_READY 29 29 mmAZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER 0 0x47 1 0 0 LINK_POSITION_IN_BUFFER 0 31 mmAZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH 0 0x48 1 0 0 CYCLIC_BUFFER_LENGTH 0 31 mmAZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX 0 0x49 1 0 0 LAST_VALID_INDEX 0 7 mmAZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE 0 0x4a 1 0 0 FIFO_SIZE 0 15 mmAZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT 0 0x4a 5 0 0 NUMBER_OF_CHANNELS 0 3 BITS_PER_SAMPLE 4 6 SAMPLE_BASE_DIVISOR 8 10 SAMPLE_BASE_MULTIPLE 11 13 SAMPLE_BASE_RATE 14 14 mmAZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS 0 0x4c 2 0 0 BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_UNIMPLEMENTED_BITS 0 6 BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS 7 31 mmAZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS 0 0x4d 1 0 0 BUFFER_DESCRIPTOR_LIST_UPPER_BASE_ADDRESS 0 31 mmAZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS 0 0x799 1 0 1 LINK_POSITION_IN_BUFFER_ALIAS 0 31 mmVGA_RENDER_CONTROL 0 0x0 7 0 1 VGA_BLINK_RATE 0 4 VGA_BLINK_MODE 5 6 VGA_CURSOR_BLINK_INVERT 7 7 VGA_EXTD_ADDR_COUNT_ENABLE 8 8 VGA_VSTATUS_CNTL 16 17 VGA_LOCK_8DOT 24 24 VGAREG_LINECMP_COMPATIBILITY_SEL 25 25 mmVGA_SEQUENCER_RESET_CONTROL 0 0x1 15 0 1 D1_BLANK_DISPLAY_WHEN_SEQUENCER_RESET 0 0 D2_BLANK_DISPLAY_WHEN_SEQUENCER_RESET 1 1 D3_BLANK_DISPLAY_WHEN_SEQUENCER_RESET 2 2 D4_BLANK_DISPLAY_WHEN_SEQUENCER_RESET 3 3 D5_BLANK_DISPLAY_WHEN_SEQUENCER_RESET 4 4 D6_BLANK_DISPLAY_WHEN_SEQUENCER_RESET 5 5 D1_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET 8 8 D2_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET 9 9 D3_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET 10 10 D4_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET 11 11 D5_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET 12 12 D6_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET 13 13 VGA_MODE_AUTO_TRIGGER_ENABLE 16 16 VGA_MODE_AUTO_TRIGGER_REGISTER_SELECT 17 17 VGA_MODE_AUTO_TRIGGER_INDEX_SELECT 18 23 mmVGA_MODE_CONTROL 0 0x2 5 0 1 VGA_ATI_LINEAR 0 0 VGA_LUT_PALETTE_UPDATE_MODE 4 5 VGA_128K_APERTURE_PAGING 8 8 VGA_TEXT_132_COLUMNS_EN 16 16 VGA_DEEP_SLEEP_FORCE_EXIT 24 24 mmVGA_SURFACE_PITCH_SELECT 0 0x3 2 0 1 VGA_SURFACE_PITCH_SELECT 0 1 VGA_SURFACE_HEIGHT_SELECT 8 9 mmVGA_MEMORY_BASE_ADDRESS 0 0x4 1 0 1 VGA_MEMORY_BASE_ADDRESS 0 31 mmVGA_DISPBUF1_SURFACE_ADDR 0 0x6 1 0 1 VGA_DISPBUF1_SURFACE_ADDR 0 24 mmVGA_DISPBUF2_SURFACE_ADDR 0 0x8 1 0 1 VGA_DISPBUF2_SURFACE_ADDR 0 24 mmVGA_MEMORY_BASE_ADDRESS_HIGH 0 0x9 1 0 1 VGA_MEMORY_BASE_ADDRESS_HIGH 0 7 mmVGA_HDP_CONTROL 0 0xa 5 0 1 VGA_MEM_PAGE_SELECT_EN 0 0 VGA_MEMORY_DISABLE 4 4 VGA_RBBM_LOCK_DISABLE 8 8 VGA_SOFT_RESET 16 16 VGA_TEST_RESET_CONTROL 24 24 mmVGA_CACHE_CONTROL 0 0xb 5 0 1 VGA_WRITE_THROUGH_CACHE_DIS 0 0 VGA_READ_CACHE_DISABLE 8 8 VGA_READ_BUFFER_INVALIDATE 16 16 VGA_DCCIF_W256ONLY 20 20 VGA_DCCIF_WC_TIMEOUT 24 29 mmD1VGA_CONTROL 0 0xc 5 0 1 D1VGA_MODE_ENABLE 0 0 D1VGA_TIMING_SELECT 8 8 D1VGA_SYNC_POLARITY_SELECT 9 9 D1VGA_OVERSCAN_COLOR_EN 16 16 D1VGA_ROTATE 24 25 mmD2VGA_CONTROL 0 0xe 5 0 1 D2VGA_MODE_ENABLE 0 0 D2VGA_TIMING_SELECT 8 8 D2VGA_SYNC_POLARITY_SELECT 9 9 D2VGA_OVERSCAN_COLOR_EN 16 16 D2VGA_ROTATE 24 25 mmVGA_STATUS 0 0x10 4 0 1 VGA_MEM_ACCESS_STATUS 0 0 VGA_REG_ACCESS_STATUS 1 1 VGA_DISPLAY_SWITCH_STATUS 2 2 VGA_MODE_AUTO_TRIGGER_STATUS 3 3 mmVGA_INTERRUPT_CONTROL 0 0x11 4 0 1 VGA_MEM_ACCESS_INT_MASK 0 0 VGA_REG_ACCESS_INT_MASK 8 8 VGA_DISPLAY_SWITCH_INT_MASK 16 16 VGA_MODE_AUTO_TRIGGER_INT_MASK 24 24 mmVGA_STATUS_CLEAR 0 0x12 4 0 1 VGA_MEM_ACCESS_INT_CLEAR 0 0 VGA_REG_ACCESS_INT_CLEAR 8 8 VGA_DISPLAY_SWITCH_INT_CLEAR 16 16 VGA_MODE_AUTO_TRIGGER_INT_CLEAR 24 24 mmVGA_INTERRUPT_STATUS 0 0x13 4 0 1 VGA_MEM_ACCESS_INT_STATUS 0 0 VGA_REG_ACCESS_INT_STATUS 1 1 VGA_DISPLAY_SWITCH_INT_STATUS 2 2 VGA_MODE_AUTO_TRIGGER_INT_STATUS 3 3 mmVGA_MAIN_CONTROL 0 0x14 10 0 1 VGA_CRTC_TIMEOUT 0 1 VGA_RENDER_TIMEOUT_COUNT 3 4 VGA_VIRTUAL_VERTICAL_RETRACE_DURATION 5 7 VGA_READBACK_VGA_VSTATUS_SOURCE_SELECT 8 9 VGA_MC_WRITE_CLEAN_WAIT_DELAY 12 15 VGA_READBACK_NO_DISPLAY_SOURCE_SELECT 16 17 VGA_READBACK_CRT_INTR_SOURCE_SELECT 24 25 VGA_READBACK_SENSE_SWITCH_SELECT 26 26 VGA_EXTERNAL_DAC_SENSE 29 29 VGA_MAIN_TEST_VSTATUS_NO_DISPLAY_CRTC_TIMEOUT 31 31 mmVGA_TEST_CONTROL 0 0x15 4 0 1 VGA_TEST_ENABLE 0 0 VGA_TEST_RENDER_START 8 8 VGA_TEST_RENDER_DONE 16 16 VGA_TEST_RENDER_DISPBUF_SELECT 24 24 mmVGA_QOS_CTRL 0 0x18 2 0 1 VGA_READ_QOS 0 3 VGA_WRITE_QOS 4 7 mmD3VGA_CONTROL 0 0x38 5 0 1 D3VGA_MODE_ENABLE 0 0 D3VGA_TIMING_SELECT 8 8 D3VGA_SYNC_POLARITY_SELECT 9 9 D3VGA_OVERSCAN_COLOR_EN 16 16 D3VGA_ROTATE 24 25 mmD4VGA_CONTROL 0 0x39 5 0 1 D4VGA_MODE_ENABLE 0 0 D4VGA_TIMING_SELECT 8 8 D4VGA_SYNC_POLARITY_SELECT 9 9 D4VGA_OVERSCAN_COLOR_EN 16 16 D4VGA_ROTATE 24 25 mmD5VGA_CONTROL 0 0x3a 5 0 1 D5VGA_MODE_ENABLE 0 0 D5VGA_TIMING_SELECT 8 8 D5VGA_SYNC_POLARITY_SELECT 9 9 D5VGA_OVERSCAN_COLOR_EN 16 16 D5VGA_ROTATE 24 25 mmD6VGA_CONTROL 0 0x3b 5 0 1 D6VGA_MODE_ENABLE 0 0 D6VGA_TIMING_SELECT 8 8 D6VGA_SYNC_POLARITY_SELECT 9 9 D6VGA_OVERSCAN_COLOR_EN 16 16 D6VGA_ROTATE 24 25 mmVGA_SOURCE_SELECT 0 0x3c 2 0 1 VGA_SOURCE_SEL_A 0 2 VGA_SOURCE_SEL_B 8 10 mmPHYPLLA_PIXCLK_RESYNC_CNTL 0 0x40 3 0 1 PHYPLLA_PIXCLK_RESYNC_ENABLE 0 0 PHYPLLA_DCCG_DEEP_COLOR_CNTL 4 5 PHYPLLA_PIXCLK_ENABLE 8 8 mmPHYPLLB_PIXCLK_RESYNC_CNTL 0 0x41 3 0 1 PHYPLLB_PIXCLK_RESYNC_ENABLE 0 0 PHYPLLB_DCCG_DEEP_COLOR_CNTL 4 5 PHYPLLB_PIXCLK_ENABLE 8 8 mmPHYPLLC_PIXCLK_RESYNC_CNTL 0 0x42 3 0 1 PHYPLLC_PIXCLK_RESYNC_ENABLE 0 0 PHYPLLC_DCCG_DEEP_COLOR_CNTL 4 5 PHYPLLC_PIXCLK_ENABLE 8 8 mmPHYPLLD_PIXCLK_RESYNC_CNTL 0 0x43 3 0 1 PHYPLLD_PIXCLK_RESYNC_ENABLE 0 0 PHYPLLD_DCCG_DEEP_COLOR_CNTL 4 5 PHYPLLD_PIXCLK_ENABLE 8 8 mmDP_DTO_DBUF_EN 0 0x44 8 0 1 DP_DTO0_DBUF_EN 0 0 DP_DTO1_DBUF_EN 1 1 DP_DTO2_DBUF_EN 2 2 DP_DTO3_DBUF_EN 3 3 DP_DTO4_DBUF_EN 4 4 DP_DTO5_DBUF_EN 5 5 DP_DTO6_DBUF_EN 6 6 DP_DTO7_DBUF_EN 7 7 mmDPREFCLK_CGTT_BLK_CTRL_REG 0 0x48 2 0 1 DPREFCLK_TURN_ON_DELAY 0 3 DPREFCLK_TURN_OFF_DELAY 4 11 mmREFCLK_CNTL 0 0x49 2 0 1 REFCLK_CLOCK_EN 0 0 REFCLK_SRC_SEL 1 1 mmMIPI_CLK_CNTL 0 0x4a 3 0 1 DSICLK_CLOCK_ENABLE 0 0 BYTECLK_CLOCK_ENABLE 1 1 ESCCLK_CLOCK_ENABLE 2 2 mmREFCLK_CGTT_BLK_CTRL_REG 0 0x4b 2 0 1 REFCLK_TURN_ON_DELAY 0 3 REFCLK_TURN_OFF_DELAY 4 11 mmPHYPLLE_PIXCLK_RESYNC_CNTL 0 0x4c 3 0 1 PHYPLLE_PIXCLK_RESYNC_ENABLE 0 0 PHYPLLE_DCCG_DEEP_COLOR_CNTL 4 5 PHYPLLE_PIXCLK_ENABLE 8 8 mmDCCG_PERFMON_CNTL2 0 0x4e 9 0 1 DCCG_PERF_DSICLK_ENABLE 0 0 DCCG_PERF_REFCLK_ENABLE 1 1 DCCG_PERF_PIXCLK1_ENABLE 2 2 DCCG_PERF_PIXCLK2_ENABLE 3 3 DCCG_PERF_UNIPHYC_PIXCLK_ENABLE 4 4 DCCG_PERF_UNIPHYD_PIXCLK_ENABLE 5 5 DCCG_PERF_UNIPHYE_PIXCLK_ENABLE 6 6 DCCG_PERF_UNIPHYF_PIXCLK_ENABLE 7 7 DCCG_PERF_UNIPHYG_PIXCLK_ENABLE 8 8 mmDSICLK_CGTT_BLK_CTRL_REG 0 0x4f 2 0 1 DSICLK_TURN_ON_DELAY 0 3 DSICLK_TURN_OFF_DELAY 4 11 mmDCCG_CBUS_WRCMD_DELAY 0 0x50 1 0 1 CBUS_PLL_WRCMD_DELAY 0 3 mmDCCG_DS_DTO_INCR 0 0x53 1 0 1 DCCG_DS_DTO_INCR 0 31 mmDCCG_DS_DTO_MODULO 0 0x54 1 0 1 DCCG_DS_DTO_MODULO 0 31 mmDCCG_DS_CNTL 0 0x55 7 0 1 DCCG_DS_ENABLE 0 0 DCCG_DS_REF_SRC 4 5 DCCG_DS_HW_CAL_ENABLE 8 8 DCCG_DS_ENABLED_STATUS 9 9 DCCG_DS_XTALIN_RATE_DIV 16 17 DCCG_DS_JITTER_REMOVE_DIS 24 24 DCCG_DS_DELAY_XTAL_SEL 25 25 mmDCCG_DS_HW_CAL_INTERVAL 0 0x56 1 0 1 DCCG_DS_HW_CAL_INTERVAL 0 31 mmSYMCLKG_CLOCK_ENABLE 0 0x57 3 0 1 SYMCLKG_CLOCK_ENABLE 0 0 SYMCLKG_FE_FORCE_EN 4 4 SYMCLKG_FE_FORCE_SRC 8 10 mmDPREFCLK_CNTL 0 0x58 2 0 1 DPREFCLK_SRC_SEL 0 2 UNB_DB_CLK_ENABLE 8 8 mmAOMCLK0_CNTL 0 0x59 1 0 1 AOMCLK0_CLOCK_EN 0 0 mmAOMCLK1_CNTL 0 0x5a 1 0 1 AOMCLK1_CLOCK_EN 0 0 mmAOMCLK2_CNTL 0 0x5b 1 0 1 AOMCLK2_CLOCK_EN 0 0 mmDCCG_AUDIO_DTO2_PHASE 0 0x5c 1 0 1 DCCG_AUDIO_DTO2_PHASE 0 31 mmDCCG_AUDIO_DTO2_MODULO 0 0x5d 1 0 1 DCCG_AUDIO_DTO2_MODULO 0 31 mmDCE_VERSION 0 0x5e 2 0 1 MAJOR_VERSION 0 7 MINOR_VERSION 8 15 mmPHYPLLG_PIXCLK_RESYNC_CNTL 0 0x5f 3 0 1 PHYPLLG_PIXCLK_RESYNC_ENABLE 0 0 PHYPLLG_DCCG_DEEP_COLOR_CNTL 4 5 PHYPLLG_PIXCLK_ENABLE 8 8 mmDCCG_GTC_CNTL 0 0x60 1 0 1 DCCG_GTC_ENABLE 0 0 mmDCCG_GTC_DTO_INCR 0 0x61 1 0 1 DCCG_GTC_DTO_INCR 0 31 mmDCCG_GTC_DTO_MODULO 0 0x62 1 0 1 DCCG_GTC_DTO_MODULO 0 31 mmDCCG_GTC_CURRENT 0 0x63 1 0 1 DCCG_GTC_CURRENT 0 31 mmMIPI_DTO_CNTL 0 0x65 1 0 1 MIPI_DTO_ENABLE 0 0 mmMIPI_DTO_PHASE 0 0x66 1 0 1 MIPI_DTO_PHASE 0 31 mmMIPI_DTO_MODULO 0 0x67 1 0 1 MIPI_DTO_MODULO 0 31 mmDAC_CLK_ENABLE 0 0x68 1 0 1 DACA_CLK_ENABLE 0 0 mmDVO_CLK_ENABLE 0 0x69 1 0 1 DVO_CLK_ENABLE 0 0 mmAVSYNC_COUNTER_WRITE 0 0x6a 1 0 1 AVSYNC_COUNTER_WRVALUE 0 31 mmAVSYNC_COUNTER_CONTROL 0 0x6b 1 0 1 AVSYNC_COUNTER_ENABLE 0 0 mmAVSYNC_COUNTER_READ 0 0x6f 1 0 1 AVSYNC_COUNTER_RDVALUE 0 31 mmMILLISECOND_TIME_BASE_DIV 0 0x70 2 0 1 MILLISECOND_TIME_BASE_DIV 0 16 MILLISECOND_TIME_BASE_CLOCK_SOURCE_SEL 20 20 mmDISPCLK_FREQ_CHANGE_CNTL 0 0x71 8 0 1 DISPCLK_STEP_DELAY 0 13 DISPCLK_STEP_SIZE 16 19 DISPCLK_FREQ_RAMP_DONE 20 20 DISPCLK_MAX_ERRDET_CYCLES 25 27 DCCG_FIFO_ERRDET_RESET 28 28 DCCG_FIFO_ERRDET_STATE 29 29 DCCG_FIFO_ERRDET_OVR_EN 30 30 DISPCLK_CHG_FWD_CORR_DISABLE 31 31 mmDC_MEM_GLOBAL_PWR_REQ_CNTL 0 0x72 1 0 1 DC_MEM_GLOBAL_PWR_REQ_DIS 0 0 mmDCCG_PERFMON_CNTL 0 0x73 10 0 1 DCCG_PERF_DISPCLK_ENABLE 0 0 DCCG_PERF_DPREFCLK_ENABLE 1 1 DCCG_PERF_UNIPHYA_PIXCLK_ENABLE 2 2 DCCG_PERF_UNIPHYB_PIXCLK_ENABLE 3 3 DCCG_PERF_PIXCLK0_ENABLE 4 4 DCCG_PERF_RUN 5 5 DCCG_PERF_MODE_VSYNC 6 6 DCCG_PERF_MODE_HSYNC 7 7 DCCG_PERF_OTG_SEL 8 10 DCCG_PERF_XTALIN_PULSE_DIV 11 31 mmDCCG_GATE_DISABLE_CNTL 0 0x74 19 0 1 DISPCLK_DCCG_GATE_DISABLE 0 0 DISPCLK_R_DCCG_GATE_DISABLE 1 1 SOCCLK_GATE_DISABLE 2 2 DPREFCLK_GATE_DISABLE 3 3 DACACLK_GATE_DISABLE 4 4 DVOACLK_GATE_DISABLE 6 6 DPREFCLK_R_DCCG_GATE_DISABLE 8 8 DPPCLK_GATE_DISABLE 9 9 AOMCLK0_GATE_DISABLE 17 17 AOMCLK1_GATE_DISABLE 18 18 AOMCLK2_GATE_DISABLE 19 19 AUDIO_DTO2_CLK_GATE_DISABLE 21 21 DPREFCLK_GTC_GATE_DISABLE 22 22 UNB_DB_CLK_GATE_DISABLE 23 23 REFCLK_GATE_DISABLE 26 26 REFCLK_R_DIG_GATE_DISABLE 27 27 DSICLK_GATE_DISABLE 28 28 BYTECLK_GATE_DISABLE 29 29 ESCCLK_GATE_DISABLE 30 30 mmDISPCLK_CGTT_BLK_CTRL_REG 0 0x75 2 0 1 DISPCLK_TURN_ON_DELAY 0 3 DISPCLK_TURN_OFF_DELAY 4 11 mmSOCCLK_CGTT_BLK_CTRL_REG 0 0x76 2 0 1 SOCCLK_TURN_ON_DELAY 0 3 SOCCLK_TURN_OFF_DELAY 4 11 mmDCCG_CAC_STATUS 0 0x77 1 0 1 CAC_STATUS_RDDATA 0 31 mmPIXCLK1_RESYNC_CNTL 0 0x78 2 0 1 PIXCLK1_RESYNC_ENABLE 0 0 DCCG_DEEP_COLOR_CNTL1 4 5 mmPIXCLK2_RESYNC_CNTL 0 0x79 2 0 1 PIXCLK2_RESYNC_ENABLE 0 0 DCCG_DEEP_COLOR_CNTL2 4 5 mmPIXCLK0_RESYNC_CNTL 0 0x7a 2 0 1 PIXCLK0_RESYNC_ENABLE 0 0 DCCG_DEEP_COLOR_CNTL0 4 5 mmMICROSECOND_TIME_BASE_DIV 0 0x7b 5 0 1 MICROSECOND_TIME_BASE_DIV 0 6 XTAL_REF_DIV 8 14 XTAL_REF_SEL 16 16 XTAL_REF_CLOCK_SOURCE_SEL 17 17 MICROSECOND_TIME_BASE_CLOCK_SOURCE_SEL 20 20 mmDCCG_GATE_DISABLE_CNTL2 0 0x7c 14 0 1 SYMCLKA_FE_GATE_DISABLE 0 0 SYMCLKB_FE_GATE_DISABLE 1 1 SYMCLKC_FE_GATE_DISABLE 2 2 SYMCLKD_FE_GATE_DISABLE 3 3 SYMCLKE_FE_GATE_DISABLE 4 4 SYMCLKF_FE_GATE_DISABLE 5 5 SYMCLKG_FE_GATE_DISABLE 6 6 SYMCLKA_GATE_DISABLE 16 16 SYMCLKB_GATE_DISABLE 17 17 SYMCLKC_GATE_DISABLE 18 18 SYMCLKD_GATE_DISABLE 19 19 SYMCLKE_GATE_DISABLE 20 20 SYMCLKF_GATE_DISABLE 21 21 SYMCLKG_GATE_DISABLE 22 22 mmSYMCLK_CGTT_BLK_CTRL_REG 0 0x7d 2 0 1 SYMCLK_TURN_ON_DELAY 0 3 SYMCLK_TURN_OFF_DELAY 4 11 mmPHYPLLF_PIXCLK_RESYNC_CNTL 0 0x7e 3 0 1 PHYPLLF_PIXCLK_RESYNC_ENABLE 0 0 PHYPLLF_DCCG_DEEP_COLOR_CNTL 4 5 PHYPLLF_PIXCLK_ENABLE 8 8 mmDCCG_DISP_CNTL_REG 0 0x7f 1 0 1 ALLOW_SR_ON_TRANS_REQ 8 8 mmOTG0_PIXEL_RATE_CNTL 0 0x80 7 0 1 OTG0_PIXEL_RATE_SOURCE 0 1 DP_DTO0_ENABLE 4 4 DP_DTO0_DS_DISABLE 5 5 OTG0_ADD_PIXEL 8 8 OTG0_DROP_PIXEL 9 9 OTG0_DISPOUT_FIFO_ERROR 14 15 OTG0_DISPOUT_ERROR_COUNT 16 27 mmDP_DTO0_PHASE 0 0x81 1 0 1 DP_DTO0_PHASE 0 31 mmDP_DTO0_MODULO 0 0x82 1 0 1 DP_DTO0_MODULO 0 31 mmOTG0_PHYPLL_PIXEL_RATE_CNTL 0 0x83 2 0 1 OTG0_PHYPLL_PIXEL_RATE_SOURCE 0 2 OTG0_PIXEL_RATE_PLL_SOURCE 4 4 mmOTG1_PIXEL_RATE_CNTL 0 0x84 7 0 1 OTG1_PIXEL_RATE_SOURCE 0 1 DP_DTO1_ENABLE 4 4 DP_DTO1_DS_DISABLE 5 5 OTG1_ADD_PIXEL 8 8 OTG1_DROP_PIXEL 9 9 OTG1_DISPOUT_FIFO_ERROR 14 15 OTG1_DISPOUT_ERROR_COUNT 16 27 mmDP_DTO1_PHASE 0 0x85 1 0 1 DP_DTO1_PHASE 0 31 mmDP_DTO1_MODULO 0 0x86 1 0 1 DP_DTO1_MODULO 0 31 mmOTG1_PHYPLL_PIXEL_RATE_CNTL 0 0x87 2 0 1 OTG1_PHYPLL_PIXEL_RATE_SOURCE 0 2 OTG1_PIXEL_RATE_PLL_SOURCE 4 4 mmOTG2_PIXEL_RATE_CNTL 0 0x88 7 0 1 OTG2_PIXEL_RATE_SOURCE 0 1 DP_DTO2_ENABLE 4 4 DP_DTO2_DS_DISABLE 5 5 OTG2_ADD_PIXEL 8 8 OTG2_DROP_PIXEL 9 9 OTG2_DISPOUT_FIFO_ERROR 14 15 OTG2_DISPOUT_ERROR_COUNT 16 27 mmDP_DTO2_PHASE 0 0x89 1 0 1 DP_DTO2_PHASE 0 31 mmDP_DTO2_MODULO 0 0x8a 1 0 1 DP_DTO2_MODULO 0 31 mmOTG2_PHYPLL_PIXEL_RATE_CNTL 0 0x8b 2 0 1 OTG2_PHYPLL_PIXEL_RATE_SOURCE 0 2 OTG2_PIXEL_RATE_PLL_SOURCE 4 4 mmOTG3_PIXEL_RATE_CNTL 0 0x8c 7 0 1 OTG3_PIXEL_RATE_SOURCE 0 1 DP_DTO3_ENABLE 4 4 DP_DTO3_DS_DISABLE 5 5 OTG3_ADD_PIXEL 8 8 OTG3_DROP_PIXEL 9 9 OTG3_DISPOUT_FIFO_ERROR 14 15 OTG3_DISPOUT_ERROR_COUNT 16 27 mmDP_DTO3_PHASE 0 0x8d 1 0 1 DP_DTO3_PHASE 0 31 mmDP_DTO3_MODULO 0 0x8e 1 0 1 DP_DTO3_MODULO 0 31 mmOTG3_PHYPLL_PIXEL_RATE_CNTL 0 0x8f 2 0 1 OTG3_PHYPLL_PIXEL_RATE_SOURCE 0 2 OTG3_PIXEL_RATE_PLL_SOURCE 4 4 mmOTG4_PIXEL_RATE_CNTL 0 0x90 7 0 1 OTG4_PIXEL_RATE_SOURCE 0 1 DP_DTO4_ENABLE 4 4 DP_DTO4_DS_DISABLE 5 5 OTG4_ADD_PIXEL 8 8 OTG4_DROP_PIXEL 9 9 OTG4_DISPOUT_FIFO_ERROR 14 15 OTG4_DISPOUT_ERROR_COUNT 16 27 mmDP_DTO4_PHASE 0 0x91 1 0 1 DP_DTO4_PHASE 0 31 mmDP_DTO4_MODULO 0 0x92 1 0 1 DP_DTO4_MODULO 0 31 mmOTG4_PHYPLL_PIXEL_RATE_CNTL 0 0x93 2 0 1 OTG4_PHYPLL_PIXEL_RATE_SOURCE 0 2 OTG4_PIXEL_RATE_PLL_SOURCE 4 4 mmOTG5_PIXEL_RATE_CNTL 0 0x94 7 0 1 OTG5_PIXEL_RATE_SOURCE 0 1 DP_DTO5_ENABLE 4 4 DP_DTO5_DS_DISABLE 5 5 OTG5_ADD_PIXEL 8 8 OTG5_DROP_PIXEL 9 9 OTG5_DISPOUT_FIFO_ERROR 14 15 OTG5_DISPOUT_ERROR_COUNT 16 27 mmDP_DTO5_PHASE 0 0x95 1 0 1 DP_DTO5_PHASE 0 31 mmDP_DTO5_MODULO 0 0x96 1 0 1 DP_DTO5_MODULO 0 31 mmOTG5_PHYPLL_PIXEL_RATE_CNTL 0 0x97 2 0 1 OTG5_PHYPLL_PIXEL_RATE_SOURCE 0 2 OTG5_PIXEL_RATE_PLL_SOURCE 4 4 mmDPPCLK_CGTT_BLK_CTRL_REG 0 0x98 2 0 1 DPPCLK_TURN_ON_DELAY 0 3 DPPCLK_TURN_OFF_DELAY 4 11 mmSYMCLKA_CLOCK_ENABLE 0 0xa0 3 0 1 SYMCLKA_CLOCK_ENABLE 0 0 SYMCLKA_FE_FORCE_EN 4 4 SYMCLKA_FE_FORCE_SRC 8 10 mmSYMCLKB_CLOCK_ENABLE 0 0xa1 3 0 1 SYMCLKB_CLOCK_ENABLE 0 0 SYMCLKB_FE_FORCE_EN 4 4 SYMCLKB_FE_FORCE_SRC 8 10 mmSYMCLKC_CLOCK_ENABLE 0 0xa2 3 0 1 SYMCLKC_CLOCK_ENABLE 0 0 SYMCLKC_FE_FORCE_EN 4 4 SYMCLKC_FE_FORCE_SRC 8 10 mmSYMCLKD_CLOCK_ENABLE 0 0xa3 3 0 1 SYMCLKD_CLOCK_ENABLE 0 0 SYMCLKD_FE_FORCE_EN 4 4 SYMCLKD_FE_FORCE_SRC 8 10 mmSYMCLKE_CLOCK_ENABLE 0 0xa4 3 0 1 SYMCLKE_CLOCK_ENABLE 0 0 SYMCLKE_FE_FORCE_EN 4 4 SYMCLKE_FE_FORCE_SRC 8 10 mmSYMCLKF_CLOCK_ENABLE 0 0xa5 3 0 1 SYMCLKF_CLOCK_ENABLE 0 0 SYMCLKF_FE_FORCE_EN 4 4 SYMCLKF_FE_FORCE_SRC 8 10 mmDCCG_SOFT_RESET 0 0xa6 16 0 1 REFCLK_SOFT_RESET 0 0 PCIE_REFCLK_SOFT_RESET 1 1 SOFT_RESET_DVO 2 2 DVO_ENABLE_RST 3 3 AUDIO_DTO2_CLK_SOFT_RESET 4 4 DPREFCLK_SOFT_RESET 8 8 AMCLK0_SOFT_RESET 12 12 AMCLK1_SOFT_RESET 13 13 P0PLL_CFG_IF_SOFT_RESET 14 14 P1PLL_CFG_IF_SOFT_RESET 15 15 P2PLL_CFG_IF_SOFT_RESET 16 16 A0PLL_CFG_IF_SOFT_RESET 17 17 A1PLL_CFG_IF_SOFT_RESET 18 18 C0PLL_CFG_IF_SOFT_RESET 19 19 C1PLL_CFG_IF_SOFT_RESET 20 20 C2PLL_CFG_IF_SOFT_RESET 21 21 mmDVOACLKD_CNTL 0 0xa8 5 0 1 DVOACLKD_FINE_SKEW_CNTL 0 2 DVOACLKD_COARSE_SKEW_CNTL 8 12 DVOACLKD_FINE_ADJUST_EN 16 16 DVOACLKD_COARSE_ADJUST_EN 17 17 DVOACLKD_IN_PHASE 18 18 mmDVOACLKC_MVP_CNTL 0 0xa9 6 0 1 DVOACLKC_MVP_FINE_SKEW_CNTL 0 2 DVOACLKC_MVP_COARSE_SKEW_CNTL 8 12 DVOACLKC_MVP_FINE_ADJUST_EN 16 16 DVOACLKC_MVP_COARSE_ADJUST_EN 17 17 DVOACLKC_MVP_IN_PHASE 18 18 DVOACLKC_MVP_SKEW_PHASE_OVERRIDE 20 20 mmDVOACLKC_CNTL 0 0xaa 5 0 1 DVOACLKC_FINE_SKEW_CNTL 0 2 DVOACLKC_COARSE_SKEW_CNTL 8 12 DVOACLKC_FINE_ADJUST_EN 16 16 DVOACLKC_COARSE_ADJUST_EN 17 17 DVOACLKC_IN_PHASE 18 18 mmDCCG_AUDIO_DTO_SOURCE 0 0xab 7 0 1 DCCG_AUDIO_DTO0_SOURCE_SEL 0 2 DCCG_AUDIO_DTO_SEL 4 5 DCCG_AUDIO_DTO2_SOURCE_SEL 12 13 DCCG_AUDIO_DTO2_CLOCK_EN 16 16 DCCG_AUDIO_DTO2_USE_512FBR_DTO 20 20 DCCG_AUDIO_DTO0_USE_512FBR_DTO 24 24 DCCG_AUDIO_DTO1_USE_512FBR_DTO 28 28 mmDCCG_AUDIO_DTO0_PHASE 0 0xac 1 0 1 DCCG_AUDIO_DTO0_PHASE 0 31 mmDCCG_AUDIO_DTO0_MODULE 0 0xad 1 0 1 DCCG_AUDIO_DTO0_MODULE 0 31 mmDCCG_AUDIO_DTO1_PHASE 0 0xae 1 0 1 DCCG_AUDIO_DTO1_PHASE 0 31 mmDCCG_AUDIO_DTO1_MODULE 0 0xaf 1 0 1 DCCG_AUDIO_DTO1_MODULE 0 31 mmDCCG_VSYNC_OTG0_LATCH_VALUE 0 0xb0 1 0 1 DCCG_VSYNC_CNT_OTG0_LATCH_VALUE 0 31 mmDCCG_VSYNC_OTG1_LATCH_VALUE 0 0xb1 1 0 1 DCCG_VSYNC_CNT_OTG1_LATCH_VALUE 0 31 mmDCCG_VSYNC_OTG2_LATCH_VALUE 0 0xb2 1 0 1 DCCG_VSYNC_CNT_OTG2_LATCH_VALUE 0 31 mmDCCG_VSYNC_OTG3_LATCH_VALUE 0 0xb3 1 0 1 DCCG_VSYNC_CNT_OTG3_LATCH_VALUE 0 31 mmDCCG_VSYNC_OTG4_LATCH_VALUE 0 0xb4 1 0 1 DCCG_VSYNC_CNT_OTG4_LATCH_VALUE 0 31 mmDCCG_VSYNC_OTG5_LATCH_VALUE 0 0xb5 1 0 1 DCCG_VSYNC_CNT_OTG5_LATCH_VALUE 0 31 mmDCCG_VSYNC_CNT_CTRL 0 0xb8 18 0 1 DCCG_VSYNC_CNT_ENABLE 0 0 DCCG_VSYNC_CNT_REFCLK_SEL 1 1 DCCG_VSYNC_CNT_SW_RESET 2 2 DCCG_VSYNC_CNT_RESET_SEL 3 3 DCCG_VSYNC_CNT_EXT_TRIG_SEL 4 7 DCCG_VSYNC_CNT_FRAME_CNT 8 11 DCCG_VSYNC_OTG0_LATCH_EN 16 16 DCCG_VSYNC_OTG1_LATCH_EN 17 17 DCCG_VSYNC_OTG2_LATCH_EN 18 18 DCCG_VSYNC_OTG3_LATCH_EN 19 19 DCCG_VSYNC_OTG4_LATCH_EN 20 20 DCCG_VSYNC_OTG5_LATCH_EN 21 21 DCCG_VSYNC_OTG0_VSYNC_TRIG_SEL 24 24 DCCG_VSYNC_OTG1_VSYNC_TRIG_SEL 25 25 DCCG_VSYNC_OTG2_VSYNC_TRIG_SEL 26 26 DCCG_VSYNC_OTG3_VSYNC_TRIG_SEL 27 27 DCCG_VSYNC_OTG4_VSYNC_TRIG_SEL 28 28 DCCG_VSYNC_OTG5_VSYNC_TRIG_SEL 29 29 mmDCCG_VSYNC_CNT_INT_CTRL 0 0xb9 18 0 1 DCCG_VSYNC_CNT_OTG0_LATCH_INTERRUPT 0 0 DCCG_VSYNC_CNT_OTG0_LATCH_INTERRUPT_CLEAR 0 0 DCCG_VSYNC_CNT_OTG1_LATCH_INTERRUPT 1 1 DCCG_VSYNC_CNT_OTG1_LATCH_INTERRUPT_CLEAR 1 1 DCCG_VSYNC_CNT_OTG2_LATCH_INTERRUPT 2 2 DCCG_VSYNC_CNT_OTG2_LATCH_INTERRUPT_CLEAR 2 2 DCCG_VSYNC_CNT_OTG3_LATCH_INTERRUPT 3 3 DCCG_VSYNC_CNT_OTG3_LATCH_INTERRUPT_CLEAR 3 3 DCCG_VSYNC_CNT_OTG4_LATCH_INTERRUPT 4 4 DCCG_VSYNC_CNT_OTG4_LATCH_INTERRUPT_CLEAR 4 4 DCCG_VSYNC_CNT_OTG5_LATCH_INTERRUPT 5 5 DCCG_VSYNC_CNT_OTG5_LATCH_INTERRUPT_CLEAR 5 5 DCCG_VSYNC_CNT_OTG0_LATCH_MASK 8 8 DCCG_VSYNC_CNT_OTG1_LATCH_MASK 9 9 DCCG_VSYNC_CNT_OTG2_LATCH_MASK 10 10 DCCG_VSYNC_CNT_OTG3_LATCH_MASK 11 11 DCCG_VSYNC_CNT_OTG4_LATCH_MASK 12 12 DCCG_VSYNC_CNT_OTG5_LATCH_MASK 13 13 mmDCCG_TEST_CLK_SEL 0 0xbe 4 0 1 DCCG_TEST_CLK_GENERICA_SEL 0 8 DCCG_TEST_CLK_GENERICA_INV 12 12 DCCG_TEST_CLK_GENERICB_SEL 16 24 DCCG_TEST_CLK_GENERICB_INV 28 28 mmDENTIST_DISPCLK_CNTL 0 0x64 10 0 1 DENTIST_DISPCLK_WDIVIDER 0 6 DENTIST_DISPCLK_RDIVIDER 8 14 DENTIST_DISPCLK_CHG_MODE 15 16 DENTIST_DISPCLK_CHGTOG 17 17 DENTIST_DISPCLK_DONETOG 18 18 DENTIST_DISPCLK_CHG_DONE 19 19 DENTIST_DPREFCLK_CHG_DONE 20 20 DENTIST_DPREFCLK_CHGTOG 21 21 DENTIST_DPREFCLK_DONETOG 22 22 DENTIST_DPREFCLK_WDIVIDER 24 30 mmDC_PERFMON0_PERFCOUNTER_CNTL 0 0x0 11 0 2 PERFCOUNTER_EVENT_SEL 0 8 PERFCOUNTER_CVALUE_SEL 9 11 PERFCOUNTER_INC_MODE 12 14 PERFCOUNTER_HW_CNTL_SEL 15 15 PERFCOUNTER_RUNEN_MODE 16 16 PERFCOUNTER_CNTOFF_START_DIS 22 22 PERFCOUNTER_RESTART_EN 23 23 PERFCOUNTER_INT_EN 24 24 PERFCOUNTER_OFF_MASK 25 25 PERFCOUNTER_ACTIVE 26 26 PERFCOUNTER_CNTL_SEL 29 31 mmDC_PERFMON0_PERFCOUNTER_CNTL2 0 0x1 5 0 2 PERFCOUNTER_COUNTED_VALUE_TYPE 0 1 PERFCOUNTER_HW_STOP1_SEL 2 2 PERFCOUNTER_HW_STOP2_SEL 3 3 PERFCOUNTER_CNTOFF_SEL 8 13 PERFCOUNTER_CNTL2_SEL 29 31 mmDC_PERFMON0_PERFCOUNTER_STATE 0 0x2 16 0 2 PERFCOUNTER_CNT0_STATE 0 1 PERFCOUNTER_STATE_SEL0 2 2 PERFCOUNTER_CNT1_STATE 4 5 PERFCOUNTER_STATE_SEL1 6 6 PERFCOUNTER_CNT2_STATE 8 9 PERFCOUNTER_STATE_SEL2 10 10 PERFCOUNTER_CNT3_STATE 12 13 PERFCOUNTER_STATE_SEL3 14 14 PERFCOUNTER_CNT4_STATE 16 17 PERFCOUNTER_STATE_SEL4 18 18 PERFCOUNTER_CNT5_STATE 20 21 PERFCOUNTER_STATE_SEL5 22 22 PERFCOUNTER_CNT6_STATE 24 25 PERFCOUNTER_STATE_SEL6 26 26 PERFCOUNTER_CNT7_STATE 28 29 PERFCOUNTER_STATE_SEL7 30 30 mmDC_PERFMON0_PERFMON_CNTL 0 0x3 6 0 2 PERFMON_STATE 0 1 PERFMON_RPT_COUNT 8 27 PERFMON_CNTOFF_AND_OR 28 28 PERFMON_CNTOFF_INT_EN 29 29 PERFMON_CNTOFF_INT_STATUS 30 30 PERFMON_CNTOFF_INT_ACK 31 31 mmDC_PERFMON0_PERFMON_CNTL2 0 0x4 4 0 2 PERFMON_CNTOFF_INT_TYPE 0 0 PERFMON_CLK_ENABLE 1 1 PERFMON_RUN_ENABLE_START_SEL 2 9 PERFMON_RUN_ENABLE_STOP_SEL 10 17 mmDC_PERFMON0_PERFMON_CVALUE_INT_MISC 0 0x5 17 0 2 PERFCOUNTER_INT0_STATUS 0 0 PERFCOUNTER_INT1_STATUS 1 1 PERFCOUNTER_INT2_STATUS 2 2 PERFCOUNTER_INT3_STATUS 3 3 PERFCOUNTER_INT4_STATUS 4 4 PERFCOUNTER_INT5_STATUS 5 5 PERFCOUNTER_INT6_STATUS 6 6 PERFCOUNTER_INT7_STATUS 7 7 PERFCOUNTER_INT0_ACK 8 8 PERFCOUNTER_INT1_ACK 9 9 PERFCOUNTER_INT2_ACK 10 10 PERFCOUNTER_INT3_ACK 11 11 PERFCOUNTER_INT4_ACK 12 12 PERFCOUNTER_INT5_ACK 13 13 PERFCOUNTER_INT6_ACK 14 14 PERFCOUNTER_INT7_ACK 15 15 PERFMON_CVALUE_HI 16 31 mmDC_PERFMON0_PERFMON_CVALUE_LOW 0 0x6 1 0 2 PERFMON_CVALUE_LOW 0 31 mmDC_PERFMON0_PERFMON_HI 0 0x7 2 0 2 PERFMON_HI 0 15 PERFMON_READ_SEL 29 31 mmDC_PERFMON0_PERFMON_LOW 0 0x8 1 0 2 PERFMON_LOW 0 31 mmDC_PERFMON1_PERFCOUNTER_CNTL 0 0xc 11 0 2 PERFCOUNTER_EVENT_SEL 0 8 PERFCOUNTER_CVALUE_SEL 9 11 PERFCOUNTER_INC_MODE 12 14 PERFCOUNTER_HW_CNTL_SEL 15 15 PERFCOUNTER_RUNEN_MODE 16 16 PERFCOUNTER_CNTOFF_START_DIS 22 22 PERFCOUNTER_RESTART_EN 23 23 PERFCOUNTER_INT_EN 24 24 PERFCOUNTER_OFF_MASK 25 25 PERFCOUNTER_ACTIVE 26 26 PERFCOUNTER_CNTL_SEL 29 31 mmDC_PERFMON1_PERFCOUNTER_CNTL2 0 0xd 5 0 2 PERFCOUNTER_COUNTED_VALUE_TYPE 0 1 PERFCOUNTER_HW_STOP1_SEL 2 2 PERFCOUNTER_HW_STOP2_SEL 3 3 PERFCOUNTER_CNTOFF_SEL 8 13 PERFCOUNTER_CNTL2_SEL 29 31 mmDC_PERFMON1_PERFCOUNTER_STATE 0 0xe 16 0 2 PERFCOUNTER_CNT0_STATE 0 1 PERFCOUNTER_STATE_SEL0 2 2 PERFCOUNTER_CNT1_STATE 4 5 PERFCOUNTER_STATE_SEL1 6 6 PERFCOUNTER_CNT2_STATE 8 9 PERFCOUNTER_STATE_SEL2 10 10 PERFCOUNTER_CNT3_STATE 12 13 PERFCOUNTER_STATE_SEL3 14 14 PERFCOUNTER_CNT4_STATE 16 17 PERFCOUNTER_STATE_SEL4 18 18 PERFCOUNTER_CNT5_STATE 20 21 PERFCOUNTER_STATE_SEL5 22 22 PERFCOUNTER_CNT6_STATE 24 25 PERFCOUNTER_STATE_SEL6 26 26 PERFCOUNTER_CNT7_STATE 28 29 PERFCOUNTER_STATE_SEL7 30 30 mmDC_PERFMON1_PERFMON_CNTL 0 0xf 6 0 2 PERFMON_STATE 0 1 PERFMON_RPT_COUNT 8 27 PERFMON_CNTOFF_AND_OR 28 28 PERFMON_CNTOFF_INT_EN 29 29 PERFMON_CNTOFF_INT_STATUS 30 30 PERFMON_CNTOFF_INT_ACK 31 31 mmDC_PERFMON1_PERFMON_CNTL2 0 0x10 4 0 2 PERFMON_CNTOFF_INT_TYPE 0 0 PERFMON_CLK_ENABLE 1 1 PERFMON_RUN_ENABLE_START_SEL 2 9 PERFMON_RUN_ENABLE_STOP_SEL 10 17 mmDC_PERFMON1_PERFMON_CVALUE_INT_MISC 0 0x11 17 0 2 PERFCOUNTER_INT0_STATUS 0 0 PERFCOUNTER_INT1_STATUS 1 1 PERFCOUNTER_INT2_STATUS 2 2 PERFCOUNTER_INT3_STATUS 3 3 PERFCOUNTER_INT4_STATUS 4 4 PERFCOUNTER_INT5_STATUS 5 5 PERFCOUNTER_INT6_STATUS 6 6 PERFCOUNTER_INT7_STATUS 7 7 PERFCOUNTER_INT0_ACK 8 8 PERFCOUNTER_INT1_ACK 9 9 PERFCOUNTER_INT2_ACK 10 10 PERFCOUNTER_INT3_ACK 11 11 PERFCOUNTER_INT4_ACK 12 12 PERFCOUNTER_INT5_ACK 13 13 PERFCOUNTER_INT6_ACK 14 14 PERFCOUNTER_INT7_ACK 15 15 PERFMON_CVALUE_HI 16 31 mmDC_PERFMON1_PERFMON_CVALUE_LOW 0 0x12 1 0 2 PERFMON_CVALUE_LOW 0 31 mmDC_PERFMON1_PERFMON_HI 0 0x13 2 0 2 PERFMON_HI 0 15 PERFMON_READ_SEL 29 31 mmDC_PERFMON1_PERFMON_LOW 0 0x14 1 0 2 PERFMON_LOW 0 31 mmPLL_MACRO_CNTL_RESERVED0 0 0x18 1 0 2 PLL_MACRO_CNTL_RESERVED 0 31 mmPLL_MACRO_CNTL_RESERVED1 0 0x19 1 0 2 PLL_MACRO_CNTL_RESERVED 0 31 mmPLL_MACRO_CNTL_RESERVED2 0 0x1a 1 0 2 PLL_MACRO_CNTL_RESERVED 0 31 mmPLL_MACRO_CNTL_RESERVED3 0 0x1b 1 0 2 PLL_MACRO_CNTL_RESERVED 0 31 mmPLL_MACRO_CNTL_RESERVED4 0 0x1c 1 0 2 PLL_MACRO_CNTL_RESERVED 0 31 mmPLL_MACRO_CNTL_RESERVED5 0 0x1d 1 0 2 PLL_MACRO_CNTL_RESERVED 0 31 mmPLL_MACRO_CNTL_RESERVED6 0 0x1e 1 0 2 PLL_MACRO_CNTL_RESERVED 0 31 mmPLL_MACRO_CNTL_RESERVED7 0 0x1f 1 0 2 PLL_MACRO_CNTL_RESERVED 0 31 mmPLL_MACRO_CNTL_RESERVED8 0 0x20 1 0 2 PLL_MACRO_CNTL_RESERVED 0 31 mmPLL_MACRO_CNTL_RESERVED9 0 0x21 1 0 2 PLL_MACRO_CNTL_RESERVED 0 31 mmPLL_MACRO_CNTL_RESERVED10 0 0x22 1 0 2 PLL_MACRO_CNTL_RESERVED 0 31 mmPLL_MACRO_CNTL_RESERVED11 0 0x23 1 0 2 PLL_MACRO_CNTL_RESERVED 0 31 mmPLL_MACRO_CNTL_RESERVED12 0 0x24 1 0 2 PLL_MACRO_CNTL_RESERVED 0 31 mmPLL_MACRO_CNTL_RESERVED13 0 0x25 1 0 2 PLL_MACRO_CNTL_RESERVED 0 31 mmPLL_MACRO_CNTL_RESERVED14 0 0x26 1 0 2 PLL_MACRO_CNTL_RESERVED 0 31 mmPLL_MACRO_CNTL_RESERVED15 0 0x27 1 0 2 PLL_MACRO_CNTL_RESERVED 0 31 mmPLL_MACRO_CNTL_RESERVED16 0 0x28 1 0 2 PLL_MACRO_CNTL_RESERVED 0 31 mmPLL_MACRO_CNTL_RESERVED17 0 0x29 1 0 2 PLL_MACRO_CNTL_RESERVED 0 31 mmPLL_MACRO_CNTL_RESERVED18 0 0x2a 1 0 2 PLL_MACRO_CNTL_RESERVED 0 31 mmPLL_MACRO_CNTL_RESERVED19 0 0x2b 1 0 2 PLL_MACRO_CNTL_RESERVED 0 31 mmPLL_MACRO_CNTL_RESERVED20 0 0x2c 1 0 2 PLL_MACRO_CNTL_RESERVED 0 31 mmPLL_MACRO_CNTL_RESERVED21 0 0x2d 1 0 2 PLL_MACRO_CNTL_RESERVED 0 31 mmPLL_MACRO_CNTL_RESERVED22 0 0x2e 1 0 2 PLL_MACRO_CNTL_RESERVED 0 31 mmPLL_MACRO_CNTL_RESERVED23 0 0x2f 1 0 2 PLL_MACRO_CNTL_RESERVED 0 31 mmPLL_MACRO_CNTL_RESERVED24 0 0x30 1 0 2 PLL_MACRO_CNTL_RESERVED 0 31 mmPLL_MACRO_CNTL_RESERVED25 0 0x31 1 0 2 PLL_MACRO_CNTL_RESERVED 0 31 mmPLL_MACRO_CNTL_RESERVED26 0 0x32 1 0 2 PLL_MACRO_CNTL_RESERVED 0 31 mmPLL_MACRO_CNTL_RESERVED27 0 0x33 1 0 2 PLL_MACRO_CNTL_RESERVED 0 31 mmPLL_MACRO_CNTL_RESERVED28 0 0x34 1 0 2 PLL_MACRO_CNTL_RESERVED 0 31 mmPLL_MACRO_CNTL_RESERVED29 0 0x35 1 0 2 PLL_MACRO_CNTL_RESERVED 0 31 mmPLL_MACRO_CNTL_RESERVED30 0 0x36 1 0 2 PLL_MACRO_CNTL_RESERVED 0 31 mmPLL_MACRO_CNTL_RESERVED31 0 0x37 1 0 2 PLL_MACRO_CNTL_RESERVED 0 31 mmPLL_MACRO_CNTL_RESERVED32 0 0x38 1 0 2 PLL_MACRO_CNTL_RESERVED 0 31 mmPLL_MACRO_CNTL_RESERVED33 0 0x39 1 0 2 PLL_MACRO_CNTL_RESERVED 0 31 mmPLL_MACRO_CNTL_RESERVED34 0 0x3a 1 0 2 PLL_MACRO_CNTL_RESERVED 0 31 mmPLL_MACRO_CNTL_RESERVED35 0 0x3b 1 0 2 PLL_MACRO_CNTL_RESERVED 0 31 mmPLL_MACRO_CNTL_RESERVED36 0 0x3c 1 0 2 PLL_MACRO_CNTL_RESERVED 0 31 mmPLL_MACRO_CNTL_RESERVED37 0 0x3d 1 0 2 PLL_MACRO_CNTL_RESERVED 0 31 mmPLL_MACRO_CNTL_RESERVED38 0 0x3e 1 0 2 PLL_MACRO_CNTL_RESERVED 0 31 mmPLL_MACRO_CNTL_RESERVED39 0 0x3f 1 0 2 PLL_MACRO_CNTL_RESERVED 0 31 mmPLL_MACRO_CNTL_RESERVED40 0 0x40 1 0 2 PLL_MACRO_CNTL_RESERVED 0 31 mmPLL_MACRO_CNTL_RESERVED41 0 0x41 1 0 2 PLL_MACRO_CNTL_RESERVED 0 31 mmRBBMIF_TIMEOUT 0 0x55 2 0 2 RBBMIF_TIMEOUT_DELAY 0 19 RBBMIF_TIMEOUT_TO_REQ_HOLD 20 31 mmRBBMIF_STATUS 0 0x56 1 0 2 RBBMIF_TIMEOUT_CLIENTS_DEC 0 29 mmRBBMIF_INT_STATUS 0 0x57 4 0 2 RBBMIF_TIMEOUT_OP 28 28 RBBMIF_TIMEOUT_RDWR_STATUS 29 29 RBBMIF_TIMEOUT_ACK 30 30 RBBMIF_TIMEOUT_MASK 31 31 mmRBBMIF_TIMEOUT_DIS 0 0x58 30 0 2 CLIENT0_TIMEOUT_DIS 0 0 CLIENT1_TIMEOUT_DIS 1 1 CLIENT2_TIMEOUT_DIS 2 2 CLIENT3_TIMEOUT_DIS 3 3 CLIENT4_TIMEOUT_DIS 4 4 CLIENT5_TIMEOUT_DIS 5 5 CLIENT6_TIMEOUT_DIS 6 6 CLIENT7_TIMEOUT_DIS 7 7 CLIENT8_TIMEOUT_DIS 8 8 CLIENT9_TIMEOUT_DIS 9 9 CLIENT10_TIMEOUT_DIS 10 10 CLIENT11_TIMEOUT_DIS 11 11 CLIENT12_TIMEOUT_DIS 12 12 CLIENT13_TIMEOUT_DIS 13 13 CLIENT14_TIMEOUT_DIS 14 14 CLIENT15_TIMEOUT_DIS 15 15 CLIENT16_TIMEOUT_DIS 16 16 CLIENT17_TIMEOUT_DIS 17 17 CLIENT18_TIMEOUT_DIS 18 18 CLIENT19_TIMEOUT_DIS 19 19 CLIENT20_TIMEOUT_DIS 20 20 CLIENT21_TIMEOUT_DIS 21 21 CLIENT22_TIMEOUT_DIS 22 22 CLIENT23_TIMEOUT_DIS 23 23 CLIENT24_TIMEOUT_DIS 24 24 CLIENT25_TIMEOUT_DIS 25 25 CLIENT26_TIMEOUT_DIS 26 26 CLIENT27_TIMEOUT_DIS 27 27 CLIENT28_TIMEOUT_DIS 28 28 CLIENT29_TIMEOUT_DIS 29 29 mmRBBMIF_STATUS_FLAG 0 0x59 7 0 2 RBBMIF_STATE 0 1 RBBMIF_READ_TIMEOUT 4 4 RBBMIF_FIFO_EMPTY 5 5 RBBMIF_FIFO_FULL 6 6 RBBMIF_INVALID_ACCESS_FLAG 8 8 RBBMIF_INVALID_ACCESS_TYPE 9 11 RBBMIF_INVALID_ACCESS_ADDR 16 31 mmDOMAIN0_PG_CONFIG 0 0x8a 2 0 2 DOMAIN0_POWER_FORCEON 0 0 DOMAIN0_POWER_GATE 8 8 mmDOMAIN0_PG_STATUS 0 0x8b 2 0 2 DOMAIN0_DESIRED_PWR_STATE 28 28 DOMAIN0_PGFSM_PWR_STATUS 30 31 mmDOMAIN1_PG_CONFIG 0 0x8c 2 0 2 DOMAIN1_POWER_FORCEON 0 0 DOMAIN1_POWER_GATE 8 8 mmDOMAIN1_PG_STATUS 0 0x8d 2 0 2 DOMAIN1_DESIRED_PWR_STATE 28 28 DOMAIN1_PGFSM_PWR_STATUS 30 31 mmDOMAIN2_PG_CONFIG 0 0x8e 2 0 2 DOMAIN2_POWER_FORCEON 0 0 DOMAIN2_POWER_GATE 8 8 mmDOMAIN2_PG_STATUS 0 0x8f 2 0 2 DOMAIN2_DESIRED_PWR_STATE 28 28 DOMAIN2_PGFSM_PWR_STATUS 30 31 mmDOMAIN3_PG_CONFIG 0 0x90 2 0 2 DOMAIN3_POWER_FORCEON 0 0 DOMAIN3_POWER_GATE 8 8 mmDOMAIN3_PG_STATUS 0 0x91 2 0 2 DOMAIN3_DESIRED_PWR_STATE 28 28 DOMAIN3_PGFSM_PWR_STATUS 30 31 mmDOMAIN4_PG_CONFIG 0 0x92 2 0 2 DOMAIN4_POWER_FORCEON 0 0 DOMAIN4_POWER_GATE 8 8 mmDOMAIN4_PG_STATUS 0 0x93 2 0 2 DOMAIN4_DESIRED_PWR_STATE 28 28 DOMAIN4_PGFSM_PWR_STATUS 30 31 mmDOMAIN5_PG_CONFIG 0 0x94 2 0 2 DOMAIN5_POWER_FORCEON 0 0 DOMAIN5_POWER_GATE 8 8 mmDOMAIN5_PG_STATUS 0 0x95 2 0 2 DOMAIN5_DESIRED_PWR_STATE 28 28 DOMAIN5_PGFSM_PWR_STATUS 30 31 mmDOMAIN6_PG_CONFIG 0 0x96 2 0 2 DOMAIN6_POWER_FORCEON 0 0 DOMAIN6_POWER_GATE 8 8 mmDOMAIN6_PG_STATUS 0 0x97 2 0 2 DOMAIN6_DESIRED_PWR_STATE 28 28 DOMAIN6_PGFSM_PWR_STATUS 30 31 mmDOMAIN7_PG_CONFIG 0 0x98 2 0 2 DOMAIN7_POWER_FORCEON 0 0 DOMAIN7_POWER_GATE 8 8 mmDOMAIN7_PG_STATUS 0 0x99 2 0 2 DOMAIN7_DESIRED_PWR_STATE 28 28 DOMAIN7_PGFSM_PWR_STATUS 30 31 mmDOMAIN8_PG_CONFIG 0 0x9a 2 0 2 DOMAIN8_POWER_FORCEON 0 0 DOMAIN8_POWER_GATE 8 8 mmDOMAIN8_PG_STATUS 0 0x9b 2 0 2 DOMAIN8_DESIRED_PWR_STATE 28 28 DOMAIN8_PGFSM_PWR_STATUS 30 31 mmDOMAIN9_PG_CONFIG 0 0x9c 2 0 2 DOMAIN9_POWER_FORCEON 0 0 DOMAIN9_POWER_GATE 8 8 mmDOMAIN9_PG_STATUS 0 0x9d 2 0 2 DOMAIN9_DESIRED_PWR_STATE 28 28 DOMAIN9_PGFSM_PWR_STATUS 30 31 mmDOMAIN10_PG_CONFIG 0 0x9e 2 0 2 DOMAIN10_POWER_FORCEON 0 0 DOMAIN10_POWER_GATE 8 8 mmDOMAIN10_PG_STATUS 0 0x9f 2 0 2 DOMAIN10_DESIRED_PWR_STATE 28 28 DOMAIN10_PGFSM_PWR_STATUS 30 31 mmDOMAIN11_PG_CONFIG 0 0xa0 2 0 2 DOMAIN11_POWER_FORCEON 0 0 DOMAIN11_POWER_GATE 8 8 mmDOMAIN11_PG_STATUS 0 0xa1 2 0 2 DOMAIN11_DESIRED_PWR_STATE 28 28 DOMAIN11_PGFSM_PWR_STATUS 30 31 mmDOMAIN12_PG_CONFIG 0 0xa2 2 0 2 DOMAIN12_POWER_FORCEON 0 0 DOMAIN12_POWER_GATE 8 8 mmDOMAIN12_PG_STATUS 0 0xa3 2 0 2 DOMAIN12_DESIRED_PWR_STATE 28 28 DOMAIN12_PGFSM_PWR_STATUS 30 31 mmDOMAIN13_PG_CONFIG 0 0xa4 2 0 2 DOMAIN13_POWER_FORCEON 0 0 DOMAIN13_POWER_GATE 8 8 mmDOMAIN13_PG_STATUS 0 0xa5 2 0 2 DOMAIN13_DESIRED_PWR_STATE 28 28 DOMAIN13_PGFSM_PWR_STATUS 30 31 mmDOMAIN14_PG_CONFIG 0 0xa6 2 0 2 DOMAIN14_POWER_FORCEON 0 0 DOMAIN14_POWER_GATE 8 8 mmDOMAIN14_PG_STATUS 0 0xa7 2 0 2 DOMAIN14_DESIRED_PWR_STATE 28 28 DOMAIN14_PGFSM_PWR_STATUS 30 31 mmDOMAIN15_PG_CONFIG 0 0xa8 2 0 2 DOMAIN15_POWER_FORCEON 0 0 DOMAIN15_POWER_GATE 8 8 mmDOMAIN15_PG_STATUS 0 0xa9 2 0 2 DOMAIN15_DESIRED_PWR_STATE 28 28 DOMAIN15_PGFSM_PWR_STATUS 30 31 mmDCPG_INTERRUPT_STATUS 0 0xaa 32 0 2 DOMAIN0_POWER_UP_INT_OCCURRED 0 0 DOMAIN0_POWER_DOWN_INT_OCCURRED 1 1 DOMAIN1_POWER_UP_INT_OCCURRED 2 2 DOMAIN1_POWER_DOWN_INT_OCCURRED 3 3 DOMAIN2_POWER_UP_INT_OCCURRED 4 4 DOMAIN2_POWER_DOWN_INT_OCCURRED 5 5 DOMAIN3_POWER_UP_INT_OCCURRED 6 6 DOMAIN3_POWER_DOWN_INT_OCCURRED 7 7 DOMAIN4_POWER_UP_INT_OCCURRED 8 8 DOMAIN4_POWER_DOWN_INT_OCCURRED 9 9 DOMAIN5_POWER_UP_INT_OCCURRED 10 10 DOMAIN5_POWER_DOWN_INT_OCCURRED 11 11 DOMAIN6_POWER_UP_INT_OCCURRED 12 12 DOMAIN6_POWER_DOWN_INT_OCCURRED 13 13 DOMAIN7_POWER_UP_INT_OCCURRED 14 14 DOMAIN7_POWER_DOWN_INT_OCCURRED 15 15 DOMAIN8_POWER_UP_INT_OCCURRED 16 16 DOMAIN8_POWER_DOWN_INT_OCCURRED 17 17 DOMAIN9_POWER_UP_INT_OCCURRED 18 18 DOMAIN9_POWER_DOWN_INT_OCCURRED 19 19 DOMAIN10_POWER_UP_INT_OCCURRED 20 20 DOMAIN10_POWER_DOWN_INT_OCCURRED 21 21 DOMAIN11_POWER_UP_INT_OCCURRED 22 22 DOMAIN11_POWER_DOWN_INT_OCCURRED 23 23 DOMAIN12_POWER_UP_INT_OCCURRED 24 24 DOMAIN12_POWER_DOWN_INT_OCCURRED 25 25 DOMAIN13_POWER_UP_INT_OCCURRED 26 26 DOMAIN13_POWER_DOWN_INT_OCCURRED 27 27 DOMAIN14_POWER_UP_INT_OCCURRED 28 28 DOMAIN14_POWER_DOWN_INT_OCCURRED 29 29 DOMAIN15_POWER_UP_INT_OCCURRED 30 30 DOMAIN15_POWER_DOWN_INT_OCCURRED 31 31 mmDCPG_INTERRUPT_CONTROL_1 0 0xab 32 0 2 DOMAIN0_POWER_UP_INT_MASK 0 0 DOMAIN0_POWER_UP_INT_CLEAR 1 1 DOMAIN0_POWER_DOWN_INT_MASK 2 2 DOMAIN0_POWER_DOWN_INT_CLEAR 3 3 DOMAIN1_POWER_UP_INT_MASK 4 4 DOMAIN1_POWER_UP_INT_CLEAR 5 5 DOMAIN1_POWER_DOWN_INT_MASK 6 6 DOMAIN1_POWER_DOWN_INT_CLEAR 7 7 DOMAIN2_POWER_UP_INT_MASK 8 8 DOMAIN2_POWER_UP_INT_CLEAR 9 9 DOMAIN2_POWER_DOWN_INT_MASK 10 10 DOMAIN2_POWER_DOWN_INT_CLEAR 11 11 DOMAIN3_POWER_UP_INT_MASK 12 12 DOMAIN3_POWER_UP_INT_CLEAR 13 13 DOMAIN3_POWER_DOWN_INT_MASK 14 14 DOMAIN3_POWER_DOWN_INT_CLEAR 15 15 DOMAIN4_POWER_UP_INT_MASK 16 16 DOMAIN4_POWER_UP_INT_CLEAR 17 17 DOMAIN4_POWER_DOWN_INT_MASK 18 18 DOMAIN4_POWER_DOWN_INT_CLEAR 19 19 DOMAIN5_POWER_UP_INT_MASK 20 20 DOMAIN5_POWER_UP_INT_CLEAR 21 21 DOMAIN5_POWER_DOWN_INT_MASK 22 22 DOMAIN5_POWER_DOWN_INT_CLEAR 23 23 DOMAIN6_POWER_UP_INT_MASK 24 24 DOMAIN6_POWER_UP_INT_CLEAR 25 25 DOMAIN6_POWER_DOWN_INT_MASK 26 26 DOMAIN6_POWER_DOWN_INT_CLEAR 27 27 DOMAIN7_POWER_UP_INT_MASK 28 28 DOMAIN7_POWER_UP_INT_CLEAR 29 29 DOMAIN7_POWER_DOWN_INT_MASK 30 30 DOMAIN7_POWER_DOWN_INT_CLEAR 31 31 mmDCPG_INTERRUPT_CONTROL_2 0 0xac 32 0 2 DOMAIN8_POWER_UP_INT_MASK 0 0 DOMAIN8_POWER_UP_INT_CLEAR 1 1 DOMAIN8_POWER_DOWN_INT_MASK 2 2 DOMAIN8_POWER_DOWN_INT_CLEAR 3 3 DOMAIN9_POWER_UP_INT_MASK 4 4 DOMAIN9_POWER_UP_INT_CLEAR 5 5 DOMAIN9_POWER_DOWN_INT_MASK 6 6 DOMAIN9_POWER_DOWN_INT_CLEAR 7 7 DOMAIN10_POWER_UP_INT_MASK 8 8 DOMAIN10_POWER_UP_INT_CLEAR 9 9 DOMAIN10_POWER_DOWN_INT_MASK 10 10 DOMAIN10_POWER_DOWN_INT_CLEAR 11 11 DOMAIN11_POWER_UP_INT_MASK 12 12 DOMAIN11_POWER_UP_INT_CLEAR 13 13 DOMAIN11_POWER_DOWN_INT_MASK 14 14 DOMAIN11_POWER_DOWN_INT_CLEAR 15 15 DOMAIN12_POWER_UP_INT_MASK 16 16 DOMAIN12_POWER_UP_INT_CLEAR 17 17 DOMAIN12_POWER_DOWN_INT_MASK 18 18 DOMAIN12_POWER_DOWN_INT_CLEAR 19 19 DOMAIN13_POWER_UP_INT_MASK 20 20 DOMAIN13_POWER_UP_INT_CLEAR 21 21 DOMAIN13_POWER_DOWN_INT_MASK 22 22 DOMAIN13_POWER_DOWN_INT_CLEAR 23 23 DOMAIN14_POWER_UP_INT_MASK 24 24 DOMAIN14_POWER_UP_INT_CLEAR 25 25 DOMAIN14_POWER_DOWN_INT_MASK 26 26 DOMAIN14_POWER_DOWN_INT_CLEAR 27 27 DOMAIN15_POWER_UP_INT_MASK 28 28 DOMAIN15_POWER_UP_INT_CLEAR 29 29 DOMAIN15_POWER_DOWN_INT_MASK 30 30 DOMAIN15_POWER_DOWN_INT_CLEAR 31 31 mmDC_IP_REQUEST_CNTL 0 0xad 1 0 2 IP_REQUEST_EN 0 0 mmDC_PGCNTL_STATUS_REG 0 0xae 0 0 2 mmDC_PERFMON2_PERFCOUNTER_CNTL 0 0xbe 11 0 2 PERFCOUNTER_EVENT_SEL 0 8 PERFCOUNTER_CVALUE_SEL 9 11 PERFCOUNTER_INC_MODE 12 14 PERFCOUNTER_HW_CNTL_SEL 15 15 PERFCOUNTER_RUNEN_MODE 16 16 PERFCOUNTER_CNTOFF_START_DIS 22 22 PERFCOUNTER_RESTART_EN 23 23 PERFCOUNTER_INT_EN 24 24 PERFCOUNTER_OFF_MASK 25 25 PERFCOUNTER_ACTIVE 26 26 PERFCOUNTER_CNTL_SEL 29 31 mmDC_PERFMON2_PERFCOUNTER_CNTL2 0 0xbf 5 0 2 PERFCOUNTER_COUNTED_VALUE_TYPE 0 1 PERFCOUNTER_HW_STOP1_SEL 2 2 PERFCOUNTER_HW_STOP2_SEL 3 3 PERFCOUNTER_CNTOFF_SEL 8 13 PERFCOUNTER_CNTL2_SEL 29 31 mmDC_PERFMON2_PERFCOUNTER_STATE 0 0xc0 16 0 2 PERFCOUNTER_CNT0_STATE 0 1 PERFCOUNTER_STATE_SEL0 2 2 PERFCOUNTER_CNT1_STATE 4 5 PERFCOUNTER_STATE_SEL1 6 6 PERFCOUNTER_CNT2_STATE 8 9 PERFCOUNTER_STATE_SEL2 10 10 PERFCOUNTER_CNT3_STATE 12 13 PERFCOUNTER_STATE_SEL3 14 14 PERFCOUNTER_CNT4_STATE 16 17 PERFCOUNTER_STATE_SEL4 18 18 PERFCOUNTER_CNT5_STATE 20 21 PERFCOUNTER_STATE_SEL5 22 22 PERFCOUNTER_CNT6_STATE 24 25 PERFCOUNTER_STATE_SEL6 26 26 PERFCOUNTER_CNT7_STATE 28 29 PERFCOUNTER_STATE_SEL7 30 30 mmDC_PERFMON2_PERFMON_CNTL 0 0xc1 6 0 2 PERFMON_STATE 0 1 PERFMON_RPT_COUNT 8 27 PERFMON_CNTOFF_AND_OR 28 28 PERFMON_CNTOFF_INT_EN 29 29 PERFMON_CNTOFF_INT_STATUS 30 30 PERFMON_CNTOFF_INT_ACK 31 31 mmDC_PERFMON2_PERFMON_CNTL2 0 0xc2 4 0 2 PERFMON_CNTOFF_INT_TYPE 0 0 PERFMON_CLK_ENABLE 1 1 PERFMON_RUN_ENABLE_START_SEL 2 9 PERFMON_RUN_ENABLE_STOP_SEL 10 17 mmDC_PERFMON2_PERFMON_CVALUE_INT_MISC 0 0xc3 17 0 2 PERFCOUNTER_INT0_STATUS 0 0 PERFCOUNTER_INT1_STATUS 1 1 PERFCOUNTER_INT2_STATUS 2 2 PERFCOUNTER_INT3_STATUS 3 3 PERFCOUNTER_INT4_STATUS 4 4 PERFCOUNTER_INT5_STATUS 5 5 PERFCOUNTER_INT6_STATUS 6 6 PERFCOUNTER_INT7_STATUS 7 7 PERFCOUNTER_INT0_ACK 8 8 PERFCOUNTER_INT1_ACK 9 9 PERFCOUNTER_INT2_ACK 10 10 PERFCOUNTER_INT3_ACK 11 11 PERFCOUNTER_INT4_ACK 12 12 PERFCOUNTER_INT5_ACK 13 13 PERFCOUNTER_INT6_ACK 14 14 PERFCOUNTER_INT7_ACK 15 15 PERFMON_CVALUE_HI 16 31 mmDC_PERFMON2_PERFMON_CVALUE_LOW 0 0xc4 1 0 2 PERFMON_CVALUE_LOW 0 31 mmDC_PERFMON2_PERFMON_HI 0 0xc5 2 0 2 PERFMON_HI 0 15 PERFMON_READ_SEL 29 31 mmDC_PERFMON2_PERFMON_LOW 0 0xc6 1 0 2 PERFMON_LOW 0 31 mmCC_DC_PIPE_DIS 0 0xca 1 0 2 DC_PIPE_DIS 0 7 mmDMU_CLK_CNTL 0 0xcb 3 0 2 DMU_TEST_CLK_SEL 0 1 DISPCLK_R_DMU_GATE_DIS 2 2 DISPCLK_G_DMCU_GATE_DIS 3 3 mmDMU_MEM_PWR_CNTL 0 0xcc 7 0 2 DMCU_ERAM_MEM_PWR_MODE_SEL 0 0 DMCU_ERAM_MEM_PWR_FORCE 1 2 DMCU_ERAM_MEM_PWR_DIS 3 3 DMCU_ERAM_MEM_PWR_STATE 4 5 DMCU_IRAM_MEM_PWR_FORCE 8 8 DMCU_IRAM_MEM_PWR_DIS 9 9 DMCU_IRAM_MEM_PWR_STATE 10 10 mmDMCU_SMU_INTERRUPT_CNTL 0 0xcd 2 0 2 DMCU_SMU_STATIC_SCREEN_INT 0 0 DMCU_SMU_STATIC_SCREEN_STATUS 16 31 mmSMU_INTERRUPT_CONTROL 0 0xce 3 0 2 DC_SMU_INT_ENABLE 0 0 DC_SMU_INT_STATUS 4 4 DC_SMU_INT_EVENT 16 31 mmDMCU_CTRL 0 0xda 7 0 2 RESET_UC 0 0 IGNORE_PWRMGT 1 1 DISABLE_IRQ_TO_UC 2 2 DISABLE_XIRQ_TO_UC 3 3 DMCU_ENABLE 4 4 DMCU_DYN_CLK_GATING_EN 8 8 UC_REG_RD_TIMEOUT 16 31 mmDMCU_STATUS 0 0xdb 3 0 2 UC_IN_RESET 0 0 UC_IN_WAIT_MODE 1 1 UC_IN_STOP_MODE 2 2 mmDMCU_PC_START_ADDR 0 0xdc 2 0 2 PC_START_ADDR_LSB 0 7 PC_START_ADDR_MSB 8 15 mmDMCU_FW_START_ADDR 0 0xdd 2 0 2 FW_START_ADDR_LSB 0 7 FW_START_ADDR_MSB 8 15 mmDMCU_FW_END_ADDR 0 0xde 2 0 2 FW_END_ADDR_LSB 0 7 FW_END_ADDR_MSB 8 15 mmDMCU_FW_ISR_START_ADDR 0 0xdf 2 0 2 FW_ISR_START_ADDR_LSB 0 7 FW_ISR_START_ADDR_MSB 8 15 mmDMCU_FW_CS_HI 0 0xe0 1 0 2 FW_CHECKSUM_HI 0 31 mmDMCU_FW_CS_LO 0 0xe1 1 0 2 FW_CHECKSUM_LO 0 31 mmDMCU_RAM_ACCESS_CTRL 0 0xe2 6 0 2 ERAM_WR_ADDR_AUTO_INC 0 0 ERAM_RD_ADDR_AUTO_INC 1 1 IRAM_WR_ADDR_AUTO_INC 2 2 IRAM_RD_ADDR_AUTO_INC 3 3 ERAM_HOST_ACCESS_EN 4 4 IRAM_HOST_ACCESS_EN 5 5 mmDMCU_ERAM_WR_CTRL 0 0xe3 3 0 2 ERAM_WR_ADDR 0 15 ERAM_WR_BE 16 19 ERAM_WR_BYTE_MODE 20 20 mmDMCU_ERAM_WR_DATA 0 0xe4 1 0 2 ERAM_WR_DATA 0 31 mmDMCU_ERAM_RD_CTRL 0 0xe5 3 0 2 ERAM_RD_ADDR 0 15 ERAM_RD_BE 16 19 ERAM_RD_BYTE_MODE 20 20 mmDMCU_ERAM_RD_DATA 0 0xe6 1 0 2 ERAM_RD_DATA 0 31 mmDMCU_IRAM_WR_CTRL 0 0xe7 1 0 2 IRAM_WR_ADDR 0 9 mmDMCU_IRAM_WR_DATA 0 0xe8 1 0 2 IRAM_WR_DATA 0 7 mmDMCU_IRAM_RD_CTRL 0 0xe9 1 0 2 IRAM_RD_ADDR 0 9 mmDMCU_IRAM_RD_DATA 0 0xea 1 0 2 IRAM_RD_DATA 0 7 mmDMCU_EVENT_TRIGGER 0 0xeb 3 0 2 GEN_SW_INT_TO_UC 0 0 UC_INTERNAL_INT_CODE 16 22 GEN_UC_INTERNAL_INT_TO_HOST 23 23 mmDMCU_UC_INTERNAL_INT_STATUS 0 0xec 16 0 2 UC_INT_IRQ_N_PIN 0 0 UC_INT_XIRQ_N_PIN 1 1 UC_INT_SOFTWARE_INTERRUPT 2 2 UC_INT_ILLEGAL_OPCODE_TRAP 3 3 UC_INT_TIMER_OUTPUT_COMPARE_4 4 4 UC_INT_TIMER_OUTPUT_COMPARE_3 5 5 UC_INT_TIMER_OUTPUT_COMPARE_2 6 6 UC_INT_TIMER_OUTPUT_COMPARE_1 7 7 UC_INT_TIMER_OVERFLOW 8 8 UC_INT_REAL_TIME_INTERRUPT 9 9 UC_INT_TIMER_INPUT_CAPTURE_4_OUTPUT_COMPARE_5 10 10 UC_INT_TIMER_INPUT_CAPTURE_3 11 11 UC_INT_TIMER_INPUT_CAPTURE_2 12 12 UC_INT_TIMER_INPUT_CAPTURE_1 13 13 UC_INT_PULSE_ACCUMULATOR_INPUT_EDGE 14 14 UC_INT_PULSE_ACCUMULATOR_OVERFLOW 15 15 mmDMCU_SS_INTERRUPT_CNTL_STATUS 0 0xed 18 0 2 STATIC_SCREEN1_INT_STATUS 13 13 STATIC_SCREEN1_INT_OCCURRED 14 14 STATIC_SCREEN1_INT_CLEAR 14 14 STATIC_SCREEN2_INT_STATUS 15 15 STATIC_SCREEN2_INT_OCCURRED 16 16 STATIC_SCREEN2_INT_CLEAR 16 16 STATIC_SCREEN3_INT_STATUS 17 17 STATIC_SCREEN3_INT_OCCURRED 18 18 STATIC_SCREEN3_INT_CLEAR 18 18 STATIC_SCREEN4_INT_STATUS 19 19 STATIC_SCREEN4_INT_OCCURRED 20 20 STATIC_SCREEN4_INT_CLEAR 20 20 STATIC_SCREEN5_INT_STATUS 21 21 STATIC_SCREEN5_INT_OCCURRED 22 22 STATIC_SCREEN5_INT_CLEAR 22 22 STATIC_SCREEN6_INT_STATUS 23 23 STATIC_SCREEN6_INT_OCCURRED 24 24 STATIC_SCREEN6_INT_CLEAR 24 24 mmDMCU_INTERRUPT_STATUS 0 0xee 50 0 2 ABM1_HG_READY_INT_OCCURRED 0 0 ABM1_HG_READY_INT_CLEAR 0 0 ABM1_LS_READY_INT_OCCURRED 1 1 ABM1_LS_READY_INT_CLEAR 1 1 ABM1_BL_UPDATE_INT_OCCURRED 2 2 ABM1_BL_UPDATE_INT_CLEAR 2 2 MCP_INT_OCCURRED 3 3 EXTERNAL_SW_INT_OCCURRED 8 8 EXTERNAL_SW_INT_CLEAR 8 8 SCP_INT_OCCURRED 9 9 UC_INTERNAL_INT_OCCURRED 10 10 UC_INTERNAL_INT_CLEAR 10 10 UC_REG_RD_TIMEOUT_INT_OCCURRED 11 11 UC_REG_RD_TIMEOUT_INT_CLEAR 11 11 DCPG_IHC_DOMAIN0_POWER_UP_INT_OCCURRED 12 12 DCPG_IHC_DOMAIN0_POWER_UP_INT_CLEAR 12 12 DCPG_IHC_DOMAIN1_POWER_UP_INT_OCCURRED 13 13 DCPG_IHC_DOMAIN1_POWER_UP_INT_CLEAR 13 13 DCPG_IHC_DOMAIN2_POWER_UP_INT_OCCURRED 14 14 DCPG_IHC_DOMAIN2_POWER_UP_INT_CLEAR 14 14 DCPG_IHC_DOMAIN3_POWER_UP_INT_OCCURRED 15 15 DCPG_IHC_DOMAIN3_POWER_UP_INT_CLEAR 15 15 DCPG_IHC_DOMAIN4_POWER_UP_INT_OCCURRED 16 16 DCPG_IHC_DOMAIN4_POWER_UP_INT_CLEAR 16 16 DCPG_IHC_DOMAIN5_POWER_UP_INT_OCCURRED 17 17 DCPG_IHC_DOMAIN5_POWER_UP_INT_CLEAR 17 17 DCPG_IHC_DOMAIN0_POWER_DOWN_INT_OCCURRED 18 18 DCPG_IHC_DOMAIN0_POWER_DOWN_INT_CLEAR 18 18 DCPG_IHC_DOMAIN1_POWER_DOWN_INT_OCCURRED 19 19 DCPG_IHC_DOMAIN1_POWER_DOWN_INT_CLEAR 19 19 DCPG_IHC_DOMAIN2_POWER_DOWN_INT_OCCURRED 20 20 DCPG_IHC_DOMAIN2_POWER_DOWN_INT_CLEAR 20 20 DCPG_IHC_DOMAIN3_POWER_DOWN_INT_OCCURRED 21 21 DCPG_IHC_DOMAIN3_POWER_DOWN_INT_CLEAR 21 21 DCPG_IHC_DOMAIN4_POWER_DOWN_INT_OCCURRED 22 22 DCPG_IHC_DOMAIN4_POWER_DOWN_INT_CLEAR 22 22 DCPG_IHC_DOMAIN5_POWER_DOWN_INT_OCCURRED 23 23 DCPG_IHC_DOMAIN5_POWER_DOWN_INT_CLEAR 23 23 VBLANK1_INT_OCCURRED 24 24 VBLANK1_INT_CLEAR 24 24 VBLANK2_INT_OCCURRED 25 25 VBLANK2_INT_CLEAR 25 25 VBLANK3_INT_OCCURRED 26 26 VBLANK3_INT_CLEAR 26 26 VBLANK4_INT_OCCURRED 27 27 VBLANK4_INT_CLEAR 27 27 VBLANK5_INT_OCCURRED 28 28 VBLANK5_INT_CLEAR 28 28 VBLANK6_INT_OCCURRED 29 29 VBLANK6_INT_CLEAR 29 29 mmDMCU_INTERRUPT_STATUS_1 0 0xef 14 0 2 OTG0_RANGE_TIMING_UPDATE_OCCURRED 6 6 OTG0_RANGE_TIMING_UPDATE_CLEAR 6 6 OTG1_RANGE_TIMING_UPDATE_OCCURRED 7 7 OTG1_RANGE_TIMING_UPDATE_CLEAR 7 7 OTG2_RANGE_TIMING_UPDATE_OCCURRED 8 8 OTG2_RANGE_TIMING_UPDATE_CLEAR 8 8 OTG3_RANGE_TIMING_UPDATE_OCCURRED 9 9 OTG3_RANGE_TIMING_UPDATE_CLEAR 9 9 OTG4_RANGE_TIMING_UPDATE_OCCURRED 10 10 OTG4_RANGE_TIMING_UPDATE_CLEAR 10 10 OTG5_RANGE_TIMING_UPDATE_OCCURRED 11 11 OTG5_RANGE_TIMING_UPDATE_CLEAR 11 11 DMCU_GENERIC_INTERRUPT_OCCURRED 13 13 DMCU_GENERIC_INTERRUPT_CLEAR 13 13 mmDMCU_INTERRUPT_TO_HOST_EN_MASK 0 0xf0 9 0 2 ABM0_HG_READY_INT_MASK 0 0 ABM0_LS_READY_INT_MASK 1 1 ABM0_BL_UPDATE_INT_MASK 2 2 ABM1_HG_READY_INT_MASK 3 3 ABM1_LS_READY_INT_MASK 4 4 ABM1_BL_UPDATE_INT_MASK 5 5 SCP_INT_MASK 9 9 UC_INTERNAL_INT_MASK 10 10 UC_REG_RD_TIMEOUT_INT_MASK 11 11 mmDMCU_INTERRUPT_TO_UC_EN_MASK 0 0xf1 29 0 2 ABM1_HG_READY_INT_TO_UC_EN 0 0 ABM1_LS_READY_INT_TO_UC_EN 1 1 ABM1_BL_UPDATE_INT_TO_UC_EN 2 2 MCP_INT_TO_UC_EN 3 3 STATIC_SCREEN1_INT_TO_UC_EN 6 6 STATIC_SCREEN2_INT_TO_UC_EN 7 7 EXTERNAL_SW_INT_TO_UC_EN 8 8 STATIC_SCREEN3_INT_TO_UC_EN 9 9 STATIC_SCREEN4_INT_TO_UC_EN 10 10 STATIC_SCREEN5_INT_TO_UC_EN 11 11 DCPG_IHC_DOMAIN0_POWER_UP_INT_TO_UC_EN 12 12 DCPG_IHC_DOMAIN1_POWER_UP_INT_TO_UC_EN 13 13 DCPG_IHC_DOMAIN2_POWER_UP_INT_TO_UC_EN 14 14 DCPG_IHC_DOMAIN3_POWER_UP_INT_TO_UC_EN 15 15 DCPG_IHC_DOMAIN4_POWER_UP_INT_TO_UC_EN 16 16 DCPG_IHC_DOMAIN5_POWER_UP_INT_TO_UC_EN 17 17 DCPG_IHC_DOMAIN0_POWER_DOWN_INT_TO_UC_EN 18 18 DCPG_IHC_DOMAIN1_POWER_DOWN_INT_TO_UC_EN 19 19 DCPG_IHC_DOMAIN2_POWER_DOWN_INT_TO_UC_EN 20 20 DCPG_IHC_DOMAIN3_POWER_DOWN_INT_TO_UC_EN 21 21 DCPG_IHC_DOMAIN4_POWER_DOWN_INT_TO_UC_EN 22 22 DCPG_IHC_DOMAIN5_POWER_DOWN_INT_TO_UC_EN 23 23 VBLANK1_INT_TO_UC_EN 24 24 VBLANK2_INT_TO_UC_EN 25 25 VBLANK3_INT_TO_UC_EN 26 26 VBLANK4_INT_TO_UC_EN 27 27 VBLANK5_INT_TO_UC_EN 28 28 VBLANK6_INT_TO_UC_EN 29 29 STATIC_SCREEN6_INT_TO_UC_EN 30 30 mmDMCU_INTERRUPT_TO_UC_EN_MASK_1 0 0xf2 7 0 2 OTG0_RANGE_TIMING_UPDATE_INT_TO_UC_EN 6 6 OTG1_RANGE_TIMING_UPDATE_INT_TO_UC_EN 7 7 OTG2_RANGE_TIMING_UPDATE_INT_TO_UC_EN 8 8 OTG3_RANGE_TIMING_UPDATE_INT_TO_UC_EN 9 9 OTG4_RANGE_TIMING_UPDATE_INT_TO_UC_EN 10 10 OTG5_RANGE_TIMING_UPDATE_INT_TO_UC_EN 11 11 DMCU_GENERIC_INT_TO_UC_EN 13 13 mmDMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL 0 0xf3 29 0 2 ABM1_HG_READY_INT_XIRQ_IRQ_SEL 0 0 ABM1_LS_READY_INT_XIRQ_IRQ_SEL 1 1 ABM1_BL_UPDATE_INT_XIRQ_IRQ_SEL 2 2 MCP_INT_XIRQ_IRQ_SEL 3 3 STATIC_SCREEN1_INT_XIRQ_IRQ_SEL 6 6 STATIC_SCREEN2_INT_XIRQ_IRQ_SEL 7 7 EXTERNAL_SW_INT_XIRQ_IRQ_SEL 8 8 STATIC_SCREEN3_INT_XIRQ_IRQ_SEL 9 9 STATIC_SCREEN4_INT_XIRQ_IRQ_SEL 10 10 STATIC_SCREEN5_INT_XIRQ_IRQ_SEL 11 11 DCPG_IHC_DOMAIN0_POWER_UP_INT_XIRQ_IRQ_SEL 12 12 DCPG_IHC_DOMAIN1_POWER_UP_INT_XIRQ_IRQ_SEL 13 13 DCPG_IHC_DOMAIN2_POWER_UP_INT_XIRQ_IRQ_SEL 14 14 DCPG_IHC_DOMAIN3_POWER_UP_INT_XIRQ_IRQ_SEL 15 15 DCPG_IHC_DOMAIN4_POWER_UP_INT_XIRQ_IRQ_SEL 16 16 DCPG_IHC_DOMAIN5_POWER_UP_INT_XIRQ_IRQ_SEL 17 17 DCPG_IHC_DOMAIN0_POWER_DOWN_INT_XIRQ_IRQ_SEL 18 18 DCPG_IHC_DOMAIN1_POWER_DOWN_INT_XIRQ_IRQ_SEL 19 19 DCPG_IHC_DOMAIN2_POWER_DOWN_INT_XIRQ_IRQ_SEL 20 20 DCPG_IHC_DOMAIN3_POWER_DOWN_INT_XIRQ_IRQ_SEL 21 21 DCPG_IHC_DOMAIN4_POWER_DOWN_INT_XIRQ_IRQ_SEL 22 22 DCPG_IHC_DOMAIN5_POWER_DOWN_INT_XIRQ_IRQ_SEL 23 23 VBLANK1_INT_XIRQ_IRQ_SEL 24 24 VBLANK2_INT_XIRQ_IRQ_SEL 25 25 VBLANK3_INT_XIRQ_IRQ_SEL 26 26 VBLANK4_INT_XIRQ_IRQ_SEL 27 27 VBLANK5_INT_XIRQ_IRQ_SEL 28 28 VBLANK6_INT_XIRQ_IRQ_SEL 29 29 STATIC_SCREEN6_INT_XIRQ_IRQ_SEL 30 30 mmDMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1 0 0xf4 7 0 2 OTG0_RANGE_TIMING_UPDATE_INT_XIRQ_IRQ_SEL 6 6 OTG1_RANGE_TIMING_UPDATE_INT_XIRQ_IRQ_SEL 7 7 OTG2_RANGE_TIMING_UPDATE_INT_XIRQ_IRQ_SEL 8 8 OTG3_RANGE_TIMING_UPDATE_INT_XIRQ_IRQ_SEL 9 9 OTG4_RANGE_TIMING_UPDATE_INT_XIRQ_IRQ_SEL 10 10 OTG5_RANGE_TIMING_UPDATE_INT_XIRQ_IRQ_SEL 11 11 DMCU_GENERIC_INT_XIRQ_IRQ_SEL 13 13 mmDC_DMCU_SCRATCH 0 0xf5 1 0 2 DMCU_SCRATCH 0 31 mmDMCU_INT_CNT 0 0xf6 3 0 2 DMCU_ABM1_HG_READY_INT_CNT 0 7 DMCU_ABM1_LS_READY_INT_CNT 8 15 DMCU_ABM1_BL_UPDATE_INT_CNT 16 23 mmDMCU_FW_CHECKSUM_SMPL_BYTE_POS 0 0xf7 2 0 2 DMCU_FW_CHECKSUM_LO_SMPL_BYTE_POS 0 1 DMCU_FW_CHECKSUM_HI_SMPL_BYTE_POS 2 3 mmDMCU_UC_CLK_GATING_CNTL 0 0xf8 3 0 2 UC_IRAM_RD_DELAY 0 2 UC_ERAM_RD_DELAY 8 10 UC_RBBM_RD_CLK_GATING_EN 16 16 mmMASTER_COMM_DATA_REG1 0 0xf9 4 0 2 MASTER_COMM_DATA_REG1_BYTE0 0 7 MASTER_COMM_DATA_REG1_BYTE1 8 15 MASTER_COMM_DATA_REG1_BYTE2 16 23 MASTER_COMM_DATA_REG1_BYTE3 24 31 mmMASTER_COMM_DATA_REG2 0 0xfa 4 0 2 MASTER_COMM_DATA_REG2_BYTE0 0 7 MASTER_COMM_DATA_REG2_BYTE1 8 15 MASTER_COMM_DATA_REG2_BYTE2 16 23 MASTER_COMM_DATA_REG2_BYTE3 24 31 mmMASTER_COMM_DATA_REG3 0 0xfb 4 0 2 MASTER_COMM_DATA_REG3_BYTE0 0 7 MASTER_COMM_DATA_REG3_BYTE1 8 15 MASTER_COMM_DATA_REG3_BYTE2 16 23 MASTER_COMM_DATA_REG3_BYTE3 24 31 mmMASTER_COMM_CMD_REG 0 0xfc 4 0 2 MASTER_COMM_CMD_REG_BYTE0 0 7 MASTER_COMM_CMD_REG_BYTE1 8 15 MASTER_COMM_CMD_REG_BYTE2 16 23 MASTER_COMM_CMD_REG_BYTE3 24 31 mmMASTER_COMM_CNTL_REG 0 0xfd 1 0 2 MASTER_COMM_INTERRUPT 0 0 mmSLAVE_COMM_DATA_REG1 0 0xfe 4 0 2 SLAVE_COMM_DATA_REG1_BYTE0 0 7 SLAVE_COMM_DATA_REG1_BYTE1 8 15 SLAVE_COMM_DATA_REG1_BYTE2 16 23 SLAVE_COMM_DATA_REG1_BYTE3 24 31 mmSLAVE_COMM_DATA_REG2 0 0xff 4 0 2 SLAVE_COMM_DATA_REG2_BYTE0 0 7 SLAVE_COMM_DATA_REG2_BYTE1 8 15 SLAVE_COMM_DATA_REG2_BYTE2 16 23 SLAVE_COMM_DATA_REG2_BYTE3 24 31 mmSLAVE_COMM_DATA_REG3 0 0x100 4 0 2 SLAVE_COMM_DATA_REG3_BYTE0 0 7 SLAVE_COMM_DATA_REG3_BYTE1 8 15 SLAVE_COMM_DATA_REG3_BYTE2 16 23 SLAVE_COMM_DATA_REG3_BYTE3 24 31 mmSLAVE_COMM_CMD_REG 0 0x101 4 0 2 SLAVE_COMM_CMD_REG_BYTE0 0 7 SLAVE_COMM_CMD_REG_BYTE1 8 15 SLAVE_COMM_CMD_REG_BYTE2 16 23 SLAVE_COMM_CMD_REG_BYTE3 24 31 mmSLAVE_COMM_CNTL_REG 0 0x102 2 0 2 SLAVE_COMM_INTERRUPT 0 0 COMM_PORT_MSG_TO_HOST_IN_PROGRESS 8 8 mmDMCU_PERFMON_INTERRUPT_STATUS1 0 0x105 6 0 2 DMU_PERFMON_COUNTER_INT_OCCURRED 0 0 DMU_PERFMON_COUNTER_INT_CLEAR 0 0 DIO_PERFMON_COUNTER_INT_OCCURRED 1 1 DIO_PERFMON_COUNTER_INT_CLEAR 1 1 DCCG_PERFMON_COUNTER_INT_OCCURRED 2 2 DCCG_PERFMON_COUNTER_INT_CLEAR 2 2 mmDMCU_PERFMON_INTERRUPT_STATUS2 0 0x106 18 0 2 HUBP0_PERFMON_COUNTER_INT_OCCURRED 0 0 HUBP0_PERFMON_COUNTER_INT_CLEAR 0 0 HUBP1_PERFMON_COUNTER_INT_OCCURRED 1 1 HUBP1_PERFMON_COUNTER_INT_CLEAR 1 1 HUBP2_PERFMON_COUNTER_INT_OCCURRED 2 2 HUBP2_PERFMON_COUNTER_INT_CLEAR 2 2 HUBP3_PERFMON_COUNTER_INT_OCCURRED 3 3 HUBP3_PERFMON_COUNTER_INT_CLEAR 3 3 HUBP4_PERFMON_COUNTER_INT_OCCURRED 4 4 HUBP4_PERFMON_COUNTER_INT_CLEAR 4 4 HUBP5_PERFMON_COUNTER_INT_OCCURRED 5 5 HUBP5_PERFMON_COUNTER_INT_CLEAR 5 5 HUBP6_PERFMON_COUNTER_INT_OCCURRED 6 6 HUBP6_PERFMON_COUNTER_INT_CLEAR 6 6 HUBP7_PERFMON_COUNTER_INT_OCCURRED 7 7 HUBP7_PERFMON_COUNTER_INT_CLEAR 7 7 HUBBUB_PERFMON_COUNTER_INT_OCCURRED 8 8 HUBBUB_PERFMON_COUNTER_INT_CLEAR 8 8 mmDMCU_PERFMON_INTERRUPT_STATUS3 0 0x107 16 0 2 DPP0_PERFMON_COUNTER_INT_OCCURRED 0 0 DPP0_PERFMON_COUNTER_INT_CLEAR 0 0 DPP1_PERFMON_COUNTER_INT_OCCURRED 1 1 DPP1_PERFMON_COUNTER_INT_CLEAR 1 1 DPP2_PERFMON_COUNTER_INT_OCCURRED 2 2 DPP2_PERFMON_COUNTER_INT_CLEAR 2 2 DPP3_PERFMON_COUNTER_INT_OCCURRED 3 3 DPP3_PERFMON_COUNTER_INT_CLEAR 3 3 DPP4_PERFMON_COUNTER_INT_OCCURRED 4 4 DPP4_PERFMON_COUNTER_INT_CLEAR 4 4 DPP5_PERFMON_COUNTER_INT_OCCURRED 5 5 DPP5_PERFMON_COUNTER_INT_CLEAR 5 5 DPP6_PERFMON_COUNTER_INT_OCCURRED 6 6 DPP6_PERFMON_COUNTER_INT_CLEAR 6 6 DPP7_PERFMON_COUNTER_INT_OCCURRED 7 7 DPP7_PERFMON_COUNTER_INT_CLEAR 7 7 mmDMCU_PERFMON_INTERRUPT_STATUS4 0 0x108 8 0 2 WB0_PERFMON_COUNTER_INT_OCCURRED 0 0 WB0_PERFMON_COUNTER_INT_CLEAR 0 0 WB1_PERFMON_COUNTER_INT_OCCURRED 1 1 WB1_PERFMON_COUNTER_INT_CLEAR 1 1 DCCG_PERFMON2_COUNTER_INT_OCCURRED 2 2 DCCG_PERFMON2_COUNTER_INT_CLEAR 2 2 MMHUBBUB_PERFMON_COUNTER_INT_OCCURRED 3 3 MMHUBBUB_PERFMON_COUNTER_INT_CLEAR 3 3 mmDMCU_PERFMON_INTERRUPT_STATUS5 0 0x109 8 0 2 MPC_PERFMON_COUNTER_INT_OCCURRED 0 0 MPC_PERFMON_COUNTER_INT_CLEAR 0 0 OPP_PERFMON_COUNTER_INT_OCCURRED 1 1 OPP_PERFMON_COUNTER_INT_CLEAR 1 1 OPTC_PERFMON_COUNTER_INT_OCCURRED 2 2 OPTC_PERFMON_COUNTER_INT_CLEAR 2 2 HDA_PERFMON_COUNTER_INT_OCCURRED 3 3 HDA_PERFMON_COUNTER_INT_CLEAR 3 3 mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1 0 0x10a 3 0 2 DMU_PERFMON_COUNTER_INT_TO_UC_EN 0 0 DIO_PERFMON_COUNTER_INT_TO_UC_EN 1 1 DCCG_PERFMON_COUNTER_INT_TO_UC_EN 2 2 mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2 0 0x10b 9 0 2 HUBP0_PERFMON_COUNTER_INT_TO_UC_EN 0 0 HUBP1_PERFMON_COUNTER_INT_TO_UC_EN 1 1 HUBP2_PERFMON_COUNTER_INT_TO_UC_EN 2 2 HUBP3_PERFMON_COUNTER_INT_TO_UC_EN 3 3 HUBP4_PERFMON_COUNTER_INT_TO_UC_EN 4 4 HUBP5_PERFMON_COUNTER_INT_TO_UC_EN 5 5 HUBP6_PERFMON_COUNTER_INT_TO_UC_EN 6 6 HUBP7_PERFMON_COUNTER_INT_TO_UC_EN 7 7 HUBBUB_PERFMON_COUNTER_INT_TO_UC_EN 8 8 mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3 0 0x10c 8 0 2 DPP0_PERFMON_COUNTER_INT_TO_UC_EN 0 0 DPP1_PERFMON_COUNTER_INT_TO_UC_EN 1 1 DPP2_PERFMON_COUNTER_INT_TO_UC_EN 2 2 DPP3_PERFMON_COUNTER_INT_TO_UC_EN 3 3 DPP4_PERFMON_COUNTER_INT_TO_UC_EN 4 4 DPP5_PERFMON_COUNTER_INT_TO_UC_EN 5 5 DPP6_PERFMON_COUNTER_INT_TO_UC_EN 6 6 DPP7_PERFMON_COUNTER_INT_TO_UC_EN 7 7 mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4 0 0x10d 4 0 2 WB0_PERFMON_COUNTER_INT_TO_UC_EN 0 0 WB1_PERFMON_COUNTER_INT_TO_UC_EN 1 1 DCCG_PERFMON2_COUNTER_INT_TO_UC_EN 2 2 MMHUBBUB_PERFMON_COUNTER_INT_TO_UC_EN 3 3 mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5 0 0x10e 4 0 2 MPC_PERFMON_COUNTER_INT_TO_UC_EN 0 0 OPP_PERFMON_COUNTER_INT_TO_UC_EN 1 1 OPTC_PERFMON_COUNTER_INT_TO_UC_EN 2 2 HDA_PERFMON_COUNTER_INT_TO_UC_EN 3 3 mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1 0 0x10f 3 0 2 DMU_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL 0 0 DIO_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL 1 1 DCCG_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL 2 2 mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2 0 0x110 9 0 2 HUBP0_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL 0 0 HUBP1_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL 1 1 HUBP2_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL 2 2 HUBP3_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL 3 3 HUBP4_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL 4 4 HUBP5_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL 5 5 HUBP6_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL 6 6 HUBP7_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL 7 7 HUBBUB_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL 8 8 mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3 0 0x111 8 0 2 DPP0_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL 0 0 DPP1_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL 1 1 DPP2_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL 2 2 DPP3_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL 3 3 DPP4_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL 4 4 DPP5_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL 5 5 DPP6_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL 6 6 DPP7_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL 7 7 mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4 0 0x112 4 0 2 WB0_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL 0 0 WB1_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL 1 1 DCCG_PERFMON2_COUNTER_INT_XIRQ_IRQ_SEL 2 2 MMHUBBUB_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL 3 3 mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5 0 0x113 4 0 2 MPC_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL 0 0 OPTC_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL 1 1 OPP_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL 2 2 HDA_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL 3 3 mmDMCU_DPRX_INTERRUPT_STATUS1 0 0x114 58 0 2 DPRX_SD0P0_MSA_RECEIVED_INT_OCCURRED 0 0 DPRX_SD0P0_MSA_RECEIVED_INT_CLEAR 0 0 DPRX_SD0P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_OCCURRED 1 1 DPRX_SD0P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_CLEAR 1 1 DPRX_SD0P0_VERTICAL_INT0_OCCURRED 2 2 DPRX_SD0P0_VERTICAL_INT0_CLEAR 2 2 DPRX_SD0P0_VERTICAL_INT1_OCCURRED 3 3 DPRX_SD0P0_VERTICAL_INT1_CLEAR 3 3 DPRX_SD0P0_SDP_RECEIVED_INT_OCCURRED 4 4 DPRX_SD0P0_SDP_RECEIVED_INT_CLEAR 4 4 DPRX_SD1P0_MSA_RECEIVED_INT_OCCURRED 5 5 DPRX_SD1P0_MSA_RECEIVED_INT_CLEAR 5 5 DPRX_SD1P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_OCCURRED 6 6 DPRX_SD1P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_CLEAR 6 6 DPRX_SD1P0_VERTICAL_INT0_OCCURRED 7 7 DPRX_SD1P0_VERTICAL_INT0_CLEAR 7 7 DPRX_SD1P0_VERTICAL_INT1_OCCURRED 8 8 DPRX_SD1P0_VERTICAL_INT1_CLEAR 8 8 DPRX_SD1P0_SDP_RECEIVED_INT_OCCURRED 9 9 DPRX_SD1P0_SDP_RECEIVED_INT_CLEAR 9 9 DPRX_DPHY_P0_BS_INTERVAL_ERROR_THRESH_EXCEEDED_INT_OCCURRED 10 10 DPRX_DPHY_P0_BS_INTERVAL_ERROR_THRESH_EXCEEDED_INT_CLEAR 10 10 DPRX_DPHY_P0_SR_INTERVAL_ERROR_THRESH_EXCEEDED_INT_OCCURRED 11 11 DPRX_DPHY_P0_SR_INTERVAL_ERROR_THRESH_EXCEEDED_INT_CLEAR 11 11 DPRX_DPHY_P0_SYMBOL_ERROR_THRESH_EXCEEDED_INT_OCCURRED 12 12 DPRX_DPHY_P0_SYMBOL_ERROR_THRESH_EXCEEDED_INT_CLEAR 12 12 DPRX_DPHY_P0_DISPARITY_ERROR_THRESH_EXCEEDED_INT_OCCURRED 13 13 DPRX_DPHY_P0_DISPARITY_ERROR_THRESH_EXCEEDED_INT_CLEAR 13 13 DPRX_DPHY_P0_TRAINING_ERROR_THRESH_EXCEEDED_INT_OCCURRED 14 14 DPRX_DPHY_P0_TRAINING_ERROR_THRESH_EXCEEDED_INT_CLEAR 14 14 DPRX_DPHY_P0_TEST_PATTERN_ERROR_THRESH_EXCEEDED_INT_OCCURRED 15 15 DPRX_DPHY_P0_TEST_PATTERN_ERROR_THRESH_EXCEEDED_INT_CLEAR 15 15 DPRX_DPHY_P0_ECF_ERROR_THRESH_EXCEEDED_INT_OCCURRED 16 16 DPRX_DPHY_P0_ECF_ERROR_THRESH_EXCEEDED_INT_CLEAR 16 16 DPRX_DPHY_P0_DETECT_SR_LOCK_INT_OCCURRED 17 17 DPRX_DPHY_P0_DETECT_SR_LOCK_INT_CLEAR 17 17 DPRX_DPHY_P0_LOSS_OF_ALIGN_INT_OCCURRED 18 18 DPRX_DPHY_P0_LOSS_OF_ALIGN_INT_CLEAR 18 18 DPRX_DPHY_P0_LOSS_OF_DESKEW_INT_OCCURRED 19 19 DPRX_DPHY_P0_LOSS_OF_DESKEW_INT_CLEAR 19 19 DPRX_DPHY_P0_EXCESSIVE_ERROR_INT_OCCURRED 20 20 DPRX_DPHY_P0_EXCESSIVE_ERROR_INT_CLEAR 20 20 DPRX_DPHY_P0_DESKEW_FIFO_OVERFLOW_INT_OCCURRED 21 21 DPRX_DPHY_P0_DESKEW_FIFO_OVERFLOW_INT_CLEAR 21 21 DPRX_AUX_P0_AUX_INT_OCCURRED 22 22 DPRX_AUX_P0_AUX_INT_CLEAR 22 22 DPRX_AUX_P0_I2C_INT_OCCURRED 23 23 DPRX_AUX_P0_I2C_INT_CLEAR 23 23 DPRX_AUX_P0_CPU_INT_OCCURRED 24 24 DPRX_AUX_P0_CPU_INT_CLEAR 24 24 DPRX_AUX_P0_MSG1_TIMEOUT_INT_OCCURRED 25 25 DPRX_AUX_P0_MSG1_TIMEOUT_INT_CLEAR 25 25 DPRX_AUX_P0_MSG2_TIMEOUT_INT_OCCURRED 26 26 DPRX_AUX_P0_MSG2_TIMEOUT_INT_CLEAR 26 26 DPRX_AUX_P0_MSG3_TIMEOUT_INT_OCCURRED 27 27 DPRX_AUX_P0_MSG3_TIMEOUT_INT_CLEAR 27 27 DPRX_AUX_P0_MSG4_TIMEOUT_INT_OCCURRED 28 28 DPRX_AUX_P0_MSG4_TIMEOUT_INT_CLEAR 28 28 mmDMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1 0 0x115 29 0 2 DPRX_SD0P0_MSA_RECEIVED_INT_TO_UC_EN 0 0 DPRX_SD0P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_TO_UC_EN 1 1 DPRX_SD0P0_VERTICAL_INT0_TO_UC_EN 2 2 DPRX_SD0P0_VERTICAL_INT1_TO_UC_EN 3 3 DPRX_SD0P0_SDP_RECEIVED_INT_TO_UC_EN 4 4 DPRX_SD1P0_MSA_RECEIVED_INT_TO_UC_EN 5 5 DPRX_SD1P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_TO_UC_EN 6 6 DPRX_SD1P0_VERTICAL_INT0_TO_UC_EN 7 7 DPRX_SD1P0_VERTICAL_INT1_TO_UC_EN 8 8 DPRX_SD1P0_SDP_RECEIVED_INT_TO_UC_EN 9 9 DPRX_DPHY_P0_BS_INTERVAL_ERROR_THRESH_EXCEEDED_INT_TO_UC_EN 10 10 DPRX_DPHY_P0_SR_INTERVAL_ERROR_THRESH_EXCEEDED_INT_TO_UC_EN 11 11 DPRX_DPHY_P0_SYMBOL_ERROR_THRESH_EXCEEDED_INT_TO_UC_EN 12 12 DPRX_DPHY_P0_DISPARITY_ERROR_THRESH_EXCEEDED_INT_TO_UC_EN 13 13 DPRX_DPHY_P0_TRAINING_ERROR_THRESH_EXCEEDED_INT_TO_UC_EN 14 14 DPRX_DPHY_P0_TEST_PATTERN_ERROR_THRESH_EXCEEDED_INT_TO_UC_EN 15 15 DPRX_DPHY_P0_ECF_ERROR_THRESH_EXCEEDED_INT_TO_UC_EN 16 16 DPRX_DPHY_P0_DETECT_SR_LOCK_INT_TO_UC_EN 17 17 DPRX_DPHY_P0_LOSS_OF_ALIGN_INT_TO_UC_EN 18 18 DPRX_DPHY_P0_LOSS_OF_DESKEW_INT_TO_UC_EN 19 19 DPRX_DPHY_P0_EXCESSIVE_ERROR_INT_TO_UC_EN 20 20 DPRX_DPHY_P0_DESKEW_FIFO_OVERFLOW_INT_TO_UC_EN 21 21 DPRX_AUX_P0_AUX_INT_TO_UC_EN 22 22 DPRX_AUX_P0_I2C_INT_TO_UC_EN 23 23 DPRX_AUX_P0_CPU_INT_TO_UC_EN 24 24 DPRX_AUX_P0_MSG1_TIMEOUT_INT_TO_UC_EN 25 25 DPRX_AUX_P0_MSG2_TIMEOUT_INT_TO_UC_EN 26 26 DPRX_AUX_P0_MSG3_TIMEOUT_INT_TO_UC_EN 27 27 DPRX_AUX_P0_MSG4_TIMEOUT_INT_TO_UC_EN 28 28 mmDMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1 0 0x116 29 0 2 DPRX_SD0P0_MSA_RECEIVED_INT_XIRQ_IRQ_SEL 0 0 DPRX_SD0P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_XIRQ_IRQ_SEL 1 1 DPRX_SD0P0_VERTICAL_INT0_XIRQ_IRQ_SEL 2 2 DPRX_SD0P0_VERTICAL_INT1_XIRQ_IRQ_SEL 3 3 DPRX_SD0P0_SDP_RECEIVED_INT_XIRQ_IRQ_SEL 4 4 DPRX_SD1P0_MSA_RECEIVED_INT_XIRQ_IRQ_SEL 5 5 DPRX_SD1P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_XIRQ_IRQ_SEL 6 6 DPRX_SD1P0_VERTICAL_INT0_XIRQ_IRQ_SEL 7 7 DPRX_SD1P0_VERTICAL_INT1_XIRQ_IRQ_SEL 8 8 DPRX_SD1P0_SDP_RECEIVED_INT_XIRQ_IRQ_SEL 9 9 DPRX_DPHY_P0_BS_INTERVAL_ERROR_THRESH_EXCEEDED_INT_XIRQ_IRQ_SEL 10 10 DPRX_DPHY_P0_SR_INTERVAL_ERROR_THRESH_EXCEEDED_INT_XIRQ_IRQ_SEL 11 11 DPRX_DPHY_P0_SYMBOL_ERROR_THRESH_EXCEEDED_INT_XIRQ_IRQ_SEL 12 12 DPRX_DPHY_P0_DISPARITY_ERROR_THRESH_EXCEEDED_INT_XIRQ_IRQ_SEL 13 13 DPRX_DPHY_P0_TRAINING_ERROR_THRESH_EXCEEDED_INT_XIRQ_IRQ_SEL 14 14 DPRX_DPHY_P0_TEST_PATTERN_ERROR_THRESH_EXCEEDED_INT_XIRQ_IRQ_SEL 15 15 DPRX_DPHY_P0_ECF_ERROR_THRESH_EXCEEDED_INT_XIRQ_IRQ_SEL 16 16 DPRX_DPHY_P0_DETECT_SR_LOCK_INT_XIRQ_IRQ_SEL 17 17 DPRX_DPHY_P0_LOSS_OF_ALIGN_INT_XIRQ_IRQ_SEL 18 18 DPRX_DPHY_P0_LOSS_OF_DESKEW_INT_XIRQ_IRQ_SEL 19 19 DPRX_DPHY_P0_EXCESSIVE_ERROR_INT_XIRQ_IRQ_SEL 20 20 DPRX_DPHY_P0_DESKEW_FIFO_OVERFLOW_INT_XIRQ_IRQ_SEL 21 21 DPRX_AUX_P0_AUX_INT_XIRQ_IRQ_SEL 22 22 DPRX_AUX_P0_I2C_INT_XIRQ_IRQ_SEL 23 23 DPRX_AUX_P0_CPU_INT_XIRQ_IRQ_SEL 24 24 DPRX_AUX_P0_MSG1_TIMEOUT_INT_XIRQ_IRQ_SEL 25 25 DPRX_AUX_P0_MSG2_TIMEOUT_INT_XIRQ_IRQ_SEL 26 26 DPRX_AUX_P0_MSG3_TIMEOUT_INT_XIRQ_IRQ_SEL 27 27 DPRX_AUX_P0_MSG4_TIMEOUT_INT_XIRQ_IRQ_SEL 28 28 mmDMCU_INTERRUPT_STATUS_CONTINUE 0 0x119 58 0 2 DCPG_IHC_DOMAIN6_POWER_UP_INT_OCCURRED 0 0 DCPG_IHC_DOMAIN6_POWER_UP_INT_CLEAR 0 0 DCPG_IHC_DOMAIN7_POWER_UP_INT_OCCURRED 1 1 DCPG_IHC_DOMAIN7_POWER_UP_INT_CLEAR 1 1 DCPG_IHC_DOMAIN8_POWER_UP_INT_OCCURRED 2 2 DCPG_IHC_DOMAIN8_POWER_UP_INT_CLEAR 2 2 DCPG_IHC_DOMAIN9_POWER_UP_INT_OCCURRED 3 3 DCPG_IHC_DOMAIN9_POWER_UP_INT_CLEAR 3 3 DCPG_IHC_DOMAIN10_POWER_UP_INT_OCCURRED 4 4 DCPG_IHC_DOMAIN10_POWER_UP_INT_CLEAR 4 4 DCPG_IHC_DOMAIN11_POWER_UP_INT_OCCURRED 5 5 DCPG_IHC_DOMAIN11_POWER_UP_INT_CLEAR 5 5 DCPG_IHC_DOMAIN12_POWER_UP_INT_OCCURRED 6 6 DCPG_IHC_DOMAIN12_POWER_UP_INT_CLEAR 6 6 DCPG_IHC_DOMAIN13_POWER_UP_INT_OCCURRED 7 7 DCPG_IHC_DOMAIN13_POWER_UP_INT_CLEAR 7 7 DCPG_IHC_DOMAIN14_POWER_UP_INT_OCCURRED 8 8 DCPG_IHC_DOMAIN14_POWER_UP_INT_CLEAR 8 8 DCPG_IHC_DOMAIN15_POWER_UP_INT_OCCURRED 9 9 DCPG_IHC_DOMAIN15_POWER_UP_INT_CLEAR 9 9 DCPG_IHC_DOMAIN6_POWER_DOWN_INT_OCCURRED 10 10 DCPG_IHC_DOMAIN6_POWER_DOWN_INT_CLEAR 10 10 DCPG_IHC_DOMAIN7_POWER_DOWN_INT_OCCURRED 11 11 DCPG_IHC_DOMAIN7_POWER_DOWN_INT_CLEAR 11 11 DCPG_IHC_DOMAIN8_POWER_DOWN_INT_OCCURRED 12 12 DCPG_IHC_DOMAIN8_POWER_DOWN_INT_CLEAR 12 12 DCPG_IHC_DOMAIN9_POWER_DOWN_INT_OCCURRED 13 13 DCPG_IHC_DOMAIN9_POWER_DOWN_INT_CLEAR 13 13 DCPG_IHC_DOMAIN10_POWER_DOWN_INT_OCCURRED 14 14 DCPG_IHC_DOMAIN10_POWER_DOWN_INT_CLEAR 14 14 DCPG_IHC_DOMAIN11_POWER_DOWN_INT_OCCURRED 15 15 DCPG_IHC_DOMAIN11_POWER_DOWN_INT_CLEAR 15 15 DCPG_IHC_DOMAIN12_POWER_DOWN_INT_OCCURRED 16 16 DCPG_IHC_DOMAIN12_POWER_DOWN_INT_CLEAR 16 16 DCPG_IHC_DOMAIN13_POWER_DOWN_INT_OCCURRED 17 17 DCPG_IHC_DOMAIN13_POWER_DOWN_INT_CLEAR 17 17 DCPG_IHC_DOMAIN14_POWER_DOWN_INT_OCCURRED 18 18 DCPG_IHC_DOMAIN14_POWER_DOWN_INT_CLEAR 18 18 DCPG_IHC_DOMAIN15_POWER_DOWN_INT_OCCURRED 19 19 DCPG_IHC_DOMAIN15_POWER_DOWN_INT_CLEAR 19 19 DCCG_DMCU_INT_VSYNC_CNT_OTG0_OCCURRED 20 20 DCCG_DMCU_INT_VSYNC_CNT_OTG0_CLEAR 20 20 DCCG_DMCU_INT_VSYNC_CNT_OTG1_OCCURRED 21 21 DCCG_DMCU_INT_VSYNC_CNT_OTG1_CLEAR 21 21 DCCG_DMCU_INT_VSYNC_CNT_OTG2_OCCURRED 22 22 DCCG_DMCU_INT_VSYNC_CNT_OTG2_CLEAR 22 22 DCCG_DMCU_INT_VSYNC_CNT_OTG3_OCCURRED 23 23 DCCG_DMCU_INT_VSYNC_CNT_OTG3_CLEAR 23 23 DCCG_DMCU_INT_VSYNC_CNT_OTG4_OCCURRED 24 24 DCCG_DMCU_INT_VSYNC_CNT_OTG4_CLEAR 24 24 DCCG_DMCU_INT_VSYNC_CNT_OTG5_OCCURRED 25 25 DCCG_DMCU_INT_VSYNC_CNT_OTG5_CLEAR 25 25 ABM0_HG_READY_INT_OCCURRED 26 26 ABM0_HG_READY_INT_CLEAR 26 26 ABM0_LS_READY_INT_OCCURRED 27 27 ABM0_LS_READY_INT_CLEAR 27 27 ABM0_BL_UPDATE_INT_OCCURRED 28 28 ABM0_BL_UPDATE_INT_CLEAR 28 28 mmDMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE 0 0x11a 29 0 2 DCPG_IHC_DOMAIN6_POWER_UP_INT_TO_UC_EN 0 0 DCPG_IHC_DOMAIN7_POWER_UP_INT_TO_UC_EN 1 1 DCPG_IHC_DOMAIN8_POWER_UP_INT_TO_UC_EN 2 2 DCPG_IHC_DOMAIN9_POWER_UP_INT_TO_UC_EN 3 3 DCPG_IHC_DOMAIN10_POWER_UP_INT_TO_UC_EN 4 4 DCPG_IHC_DOMAIN11_POWER_UP_INT_TO_UC_EN 5 5 DCPG_IHC_DOMAIN12_POWER_UP_INT_TO_UC_EN 6 6 DCPG_IHC_DOMAIN13_POWER_UP_INT_TO_UC_EN 7 7 DCPG_IHC_DOMAIN14_POWER_UP_INT_TO_UC_EN 8 8 DCPG_IHC_DOMAIN15_POWER_UP_INT_TO_UC_EN 9 9 DCPG_IHC_DOMAIN6_POWER_DOWN_INT_TO_UC_EN 10 10 DCPG_IHC_DOMAIN7_POWER_DOWN_INT_TO_UC_EN 11 11 DCPG_IHC_DOMAIN8_POWER_DOWN_INT_TO_UC_EN 12 12 DCPG_IHC_DOMAIN9_POWER_DOWN_INT_TO_UC_EN 13 13 DCPG_IHC_DOMAIN10_POWER_DOWN_INT_TO_UC_EN 14 14 DCPG_IHC_DOMAIN11_POWER_DOWN_INT_TO_UC_EN 15 15 DCPG_IHC_DOMAIN12_POWER_DOWN_INT_TO_UC_EN 16 16 DCPG_IHC_DOMAIN13_POWER_DOWN_INT_TO_UC_EN 17 17 DCPG_IHC_DOMAIN14_POWER_DOWN_INT_TO_UC_EN 18 18 DCPG_IHC_DOMAIN15_POWER_DOWN_INT_TO_UC_EN 19 19 DCCG_DMCU_INT_VSYNC_CNT_OTG0_TO_UC_EN 20 20 DCCG_DMCU_INT_VSYNC_CNT_OTG1_TO_UC_EN 21 21 DCCG_DMCU_INT_VSYNC_CNT_OTG2_TO_UC_EN 22 22 DCCG_DMCU_INT_VSYNC_CNT_OTG3_TO_UC_EN 23 23 DCCG_DMCU_INT_VSYNC_CNT_OTG4_TO_UC_EN 24 24 DCCG_DMCU_INT_VSYNC_CNT_OTG5_TO_UC_EN 25 25 ABM0_HG_READY_INT_TO_UC_EN 26 26 ABM0_LS_READY_INT_TO_UC_EN 27 27 ABM0_BL_UPDATE_INT_TO_UC_EN 28 28 mmDMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE 0 0x11b 29 0 2 DCPG_IHC_DOMAIN6_POWER_UP_INT_XIRQ_IRQ_SEL 0 0 DCPG_IHC_DOMAIN7_POWER_UP_INT_XIRQ_IRQ_SEL 1 1 DCPG_IHC_DOMAIN8_POWER_UP_INT_XIRQ_IRQ_SEL 2 2 DCPG_IHC_DOMAIN9_POWER_UP_INT_XIRQ_IRQ_SEL 3 3 DCPG_IHC_DOMAIN10_POWER_UP_INT_XIRQ_IRQ_SEL 4 4 DCPG_IHC_DOMAIN11_POWER_UP_INT_XIRQ_IRQ_SEL 5 5 DCPG_IHC_DOMAIN12_POWER_UP_INT_XIRQ_IRQ_SEL 6 6 DCPG_IHC_DOMAIN13_POWER_UP_INT_XIRQ_IRQ_SEL 7 7 DCPG_IHC_DOMAIN14_POWER_UP_INT_XIRQ_IRQ_SEL 8 8 DCPG_IHC_DOMAIN15_POWER_UP_INT_XIRQ_IRQ_SEL 9 9 DCPG_IHC_DOMAIN6_POWER_DOWN_INT_XIRQ_IRQ_SEL 10 10 DCPG_IHC_DOMAIN7_POWER_DOWN_INT_XIRQ_IRQ_SEL 11 11 DCPG_IHC_DOMAIN8_POWER_DOWN_INT_XIRQ_IRQ_SEL 12 12 DCPG_IHC_DOMAIN9_POWER_DOWN_INT_XIRQ_IRQ_SEL 13 13 DCPG_IHC_DOMAIN10_POWER_DOWN_INT_XIRQ_IRQ_SEL 14 14 DCPG_IHC_DOMAIN11_POWER_DOWN_INT_XIRQ_IRQ_SEL 15 15 DCPG_IHC_DOMAIN12_POWER_DOWN_INT_XIRQ_IRQ_SEL 16 16 DCPG_IHC_DOMAIN13_POWER_DOWN_INT_XIRQ_IRQ_SEL 17 17 DCPG_IHC_DOMAIN14_POWER_DOWN_INT_XIRQ_IRQ_SEL 18 18 DCPG_IHC_DOMAIN15_POWER_DOWN_INT_XIRQ_IRQ_SEL 19 19 DCCG_DMCU_INT_VSYNC_CNT_OTG0_XIRQ_IRQ_SEL 20 20 DCCG_DMCU_INT_VSYNC_CNT_OTG1_XIRQ_IRQ_SEL 21 21 DCCG_DMCU_INT_VSYNC_CNT_OTG2_XIRQ_IRQ_SEL 22 22 DCCG_DMCU_INT_VSYNC_CNT_OTG3_XIRQ_IRQ_SEL 23 23 DCCG_DMCU_INT_VSYNC_CNT_OTG4_XIRQ_IRQ_SEL 24 24 DCCG_DMCU_INT_VSYNC_CNT_OTG5_XIRQ_IRQ_SEL 25 25 ABM0_HG_READY_INT_XIRQ_IRQ_SEL 26 26 ABM0_LS_READY_INT_XIRQ_IRQ_SEL 27 27 ABM0_BL_UPDATE_INT_XIRQ_IRQ_SEL 28 28 mmDMCU_INT_CNT_CONTINUE 0 0x11c 3 0 2 DMCU_ABM0_HG_READY_INT_CNT 0 7 DMCU_ABM0_LS_READY_INT_CNT 8 15 DMCU_ABM0_BL_UPDATE_INT_CNT 16 23 mmDC_GPU_TIMER_START_POSITION_V_UPDATE 0 0x126 6 0 2 DC_GPU_TIMER_START_POSITION_D1_V_UPDATE 0 2 DC_GPU_TIMER_START_POSITION_D2_V_UPDATE 4 6 DC_GPU_TIMER_START_POSITION_D3_V_UPDATE 8 10 DC_GPU_TIMER_START_POSITION_D4_V_UPDATE 12 14 DC_GPU_TIMER_START_POSITION_D5_V_UPDATE 16 18 DC_GPU_TIMER_START_POSITION_D6_V_UPDATE 20 22 mmDC_GPU_TIMER_START_POSITION_VSTARTUP 0 0x127 6 0 2 DC_GPU_TIMER_START_POSITION_D1_VSTARTUP 0 2 DC_GPU_TIMER_START_POSITION_D2_VSTARTUP 4 6 DC_GPU_TIMER_START_POSITION_D3_VSTARTUP 8 10 DC_GPU_TIMER_START_POSITION_D4_VSTARTUP 12 14 DC_GPU_TIMER_START_POSITION_D5_VSTARTUP 16 18 DC_GPU_TIMER_START_POSITION_D6_VSTARTUP 20 22 mmDC_GPU_TIMER_READ 0 0x128 1 0 2 DC_GPU_TIMER_READ 0 31 mmDC_GPU_TIMER_READ_CNTL 0 0x129 7 0 2 DC_GPU_TIMER_READ_SELECT 0 6 DC_GPU_TIMER_START_POSITION_D1_VSYNC_NOM 8 10 DC_GPU_TIMER_START_POSITION_D2_VSYNC_NOM 11 13 DC_GPU_TIMER_START_POSITION_D3_VSYNC_NOM 14 16 DC_GPU_TIMER_START_POSITION_D4_VSYNC_NOM 17 19 DC_GPU_TIMER_START_POSITION_D5_VSYNC_NOM 20 22 DC_GPU_TIMER_START_POSITION_D6_VSYNC_NOM 23 25 mmDISP_INTERRUPT_STATUS 0 0x12a 22 0 2 OPTC1_DATA_UNDERFLOW_INTERRUPT 1 1 OTG1_IHC_SNAPSHOT_INTERRUPT 4 4 OTG1_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT 5 5 OTG1_IHC_FORCE_COUNT_NOW_INTERRUPT 6 6 OTG1_IHC_TRIGA_INTERRUPT 7 7 OTG1_IHC_TRIGB_INTERRUPT 8 8 OTG1_IHC_VSYNC_NOM_INTERRUPT 9 9 OTG1_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT 10 10 DIGA_DP_FAST_TRAINING_COMPLETE_INTERRUPT 15 15 DIGA_DP_VID_STREAM_DISABLE_INTERRUPT 16 16 DC_HPD1_INTERRUPT 17 17 DC_HPD1_RX_INTERRUPT 18 18 AUX1_SW_DONE_INTERRUPT 19 19 AUX1_LS_DONE_INTERRUPT 20 20 DACA_AUTODETECT_GENERITE_INTERRUPT 22 22 RBBMIF_IHC_TIMEOUT_INTERRUPT 23 23 DC_I2C_SW_DONE_INTERRUPT 24 24 DMCU_UC_INTERNAL_INT 26 26 ABM1_HG_READY_INT 28 28 ABM1_LS_READY_INT 29 29 ABM1_BL_UPDATE_INT 30 30 DISP_INTERRUPT_STATUS_CONTINUE 31 31 mmDISP_INTERRUPT_STATUS_CONTINUE 0 0x12b 21 0 2 OPTC2_DATA_UNDERFLOW_INTERRUPT 1 1 OTG2_IHC_SNAPSHOT_INTERRUPT 4 4 OTG2_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT 5 5 OTG2_IHC_FORCE_COUNT_NOW_INTERRUPT 6 6 OTG2_IHC_TRIGA_INTERRUPT 7 7 OTG2_IHC_TRIGB_INTERRUPT 8 8 OTG2_IHC_VSYNC_NOM_INTERRUPT 9 9 OTG2_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT 10 10 DIGB_DP_FAST_TRAINING_COMPLETE_INTERRUPT 15 15 DIGB_DP_VID_STREAM_DISABLE_INTERRUPT 16 16 DC_HPD2_INTERRUPT 17 17 DC_HPD2_RX_INTERRUPT 18 18 AUX2_SW_DONE_INTERRUPT 19 19 AUX2_LS_DONE_INTERRUPT 20 20 OTG1_IHC_EXT_TIMING_SYNC_LOSS_INTERRUPT 25 25 OTG1_IHC_EXT_TIMING_SYNC_INTERRUPT 26 26 OTG1_IHC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT 27 27 OTG1_IHC_VERTICAL_INTERRUPT0 28 28 OTG1_IHC_VERTICAL_INTERRUPT1 29 29 OTG1_IHC_VERTICAL_INTERRUPT2 30 30 DISP_INTERRUPT_STATUS_CONTINUE2 31 31 mmDISP_INTERRUPT_STATUS_CONTINUE2 0 0x12c 21 0 2 OPTC3_DATA_UNDERFLOW_INTERRUPT 1 1 OTG3_IHC_SNAPSHOT_INTERRUPT 4 4 OTG3_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT 5 5 OTG3_IHC_FORCE_COUNT_NOW_INTERRUPT 6 6 OTG3_IHC_TRIGA_INTERRUPT 7 7 OTG3_IHC_TRIGB_INTERRUPT 8 8 OTG3_IHC_VSYNC_NOM_INTERRUPT 9 9 OTG3_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT 10 10 DIGC_DP_FAST_TRAINING_COMPLETE_INTERRUPT 15 15 DIGC_DP_VID_STREAM_DISABLE_INTERRUPT 16 16 DC_HPD3_INTERRUPT 17 17 DC_HPD3_RX_INTERRUPT 18 18 AUX3_SW_DONE_INTERRUPT 19 19 AUX3_LS_DONE_INTERRUPT 20 20 OTG2_IHC_EXT_TIMING_SYNC_LOSS_INTERRUPT 25 25 OTG2_IHC_EXT_TIMING_SYNC_INTERRUPT 26 26 OTG2_IHC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT 27 27 OTG2_IHC_VERTICAL_INTERRUPT0 28 28 OTG2_IHC_VERTICAL_INTERRUPT1 29 29 OTG2_IHC_VERTICAL_INTERRUPT2 30 30 DISP_INTERRUPT_STATUS_CONTINUE3 31 31 mmDISP_INTERRUPT_STATUS_CONTINUE3 0 0x12d 23 0 2 OPTC4_DATA_UNDERFLOW_INTERRUPT 1 1 OTG4_IHC_SNAPSHOT_INTERRUPT 4 4 OTG4_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT 5 5 OTG4_IHC_FORCE_COUNT_NOW_INTERRUPT 6 6 OTG4_IHC_TRIGA_INTERRUPT 7 7 OTG4_IHC_TRIGB_INTERRUPT 8 8 OTG4_IHC_VSYNC_NOM_INTERRUPT 9 9 OTG4_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT 10 10 DIGD_DP_FAST_TRAINING_COMPLETE_INTERRUPT 15 15 DIGD_DP_VID_STREAM_DISABLE_INTERRUPT 16 16 DC_HPD4_INTERRUPT 17 17 DC_HPD4_RX_INTERRUPT 18 18 AUX4_SW_DONE_INTERRUPT 19 19 AUX4_LS_DONE_INTERRUPT 20 20 WBSCL0_HOST_CONFLICT_INTERRUPT 23 23 WBSCL0_DATA_OVERFLOW_INTERRUPT 24 24 OTG3_IHC_EXT_TIMING_SYNC_LOSS_INTERRUPT 25 25 OTG3_IHC_EXT_TIMING_SYNC_INTERRUPT 26 26 OTG3_IHC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT 27 27 OTG3_IHC_VERTICAL_INTERRUPT0 28 28 OTG3_IHC_VERTICAL_INTERRUPT1 29 29 OTG3_IHC_VERTICAL_INTERRUPT2 30 30 DISP_INTERRUPT_STATUS_CONTINUE4 31 31 mmDISP_INTERRUPT_STATUS_CONTINUE4 0 0x12e 25 0 2 OPTC5_DATA_UNDERFLOW_INTERRUPT 0 0 OPTC6_DATA_UNDERFLOW_INTERRUPT 1 1 OTG5_IHC_SNAPSHOT_INTERRUPT 4 4 OTG5_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT 5 5 OTG5_IHC_FORCE_COUNT_NOW_INTERRUPT 6 6 OTG5_IHC_TRIGA_INTERRUPT 7 7 OTG5_IHC_TRIGB_INTERRUPT 8 8 OTG5_IHC_VSYNC_NOM_INTERRUPT 9 9 OTG5_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT 10 10 DIGE_DP_FAST_TRAINING_COMPLETE_INTERRUPT 15 15 DIGE_DP_VID_STREAM_DISABLE_INTERRUPT 16 16 DC_HPD5_INTERRUPT 17 17 DC_HPD5_RX_INTERRUPT 18 18 AUX5_SW_DONE_INTERRUPT 19 19 AUX5_LS_DONE_INTERRUPT 20 20 OTG4_IHC_EXT_TIMING_SYNC_LOSS_INTERRUPT 22 22 OTG4_IHC_EXT_TIMING_SYNC_INTERRUPT 23 23 OTG4_IHC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT 24 24 OTG5_IHC_EXT_TIMING_SYNC_LOSS_INTERRUPT 25 25 OTG5_IHC_EXT_TIMING_SYNC_INTERRUPT 26 26 OTG5_IHC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT 27 27 OTG4_IHC_VERTICAL_INTERRUPT0 28 28 OTG4_IHC_VERTICAL_INTERRUPT1 29 29 OTG4_IHC_VERTICAL_INTERRUPT2 30 30 DISP_INTERRUPT_STATUS_CONTINUE5 31 31 mmDISP_INTERRUPT_STATUS_CONTINUE5 0 0x12f 23 0 2 OTG6_IHC_SNAPSHOT_INTERRUPT 4 4 OTG6_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT 5 5 OTG6_IHC_FORCE_COUNT_NOW_INTERRUPT 6 6 OTG6_IHC_TRIGA_INTERRUPT 7 7 OTG6_IHC_TRIGB_INTERRUPT 8 8 OTG6_IHC_VSYNC_NOM_INTERRUPT 9 9 OTG6_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT 10 10 DIGF_DP_FAST_TRAINING_COMPLETE_INTERRUPT 15 15 DIGF_DP_VID_STREAM_DISABLE_INTERRUPT 16 16 DC_HPD6_INTERRUPT 17 17 DC_HPD6_RX_INTERRUPT 18 18 AUX6_SW_DONE_INTERRUPT 19 19 AUX6_LS_DONE_INTERRUPT 20 20 OTG6_IHC_EXT_TIMING_SYNC_LOSS_INTERRUPT 22 22 OTG6_IHC_EXT_TIMING_SYNC_INTERRUPT 23 23 OTG6_IHC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT 24 24 OTG5_IHC_VERTICAL_INTERRUPT0 25 25 OTG5_IHC_VERTICAL_INTERRUPT1 26 26 OTG5_IHC_VERTICAL_INTERRUPT2 27 27 OTG6_IHC_VERTICAL_INTERRUPT0 28 28 OTG6_IHC_VERTICAL_INTERRUPT1 29 29 OTG6_IHC_VERTICAL_INTERRUPT2 30 30 DISP_INTERRUPT_STATUS_CONTINUE6 31 31 mmDISP_INTERRUPT_STATUS_CONTINUE6 0 0x130 17 0 2 MCIF_CWB0_IHIF_INTERRUPT 9 9 MCIF_CWB1_IHIF_INTERRUPT 10 10 AUX1_GTC_SYNC_LOCK_DONE_INTERRUPT 17 17 AUX1_GTC_SYNC_ERROR_INTERRUPT 18 18 AUX2_GTC_SYNC_LOCK_DONE_INTERRUPT 19 19 AUX2_GTC_SYNC_ERROR_INTERRUPT 20 20 AUX3_GTC_SYNC_LOCK_DONE_INTERRUPT 21 21 AUX3_GTC_SYNC_ERROR_INTERRUPT 22 22 AUX4_GTC_SYNC_LOCK_DONE_INTERRUPT 23 23 AUX4_GTC_SYNC_ERROR_INTERRUPT 24 24 AUX5_GTC_SYNC_LOCK_DONE_INTERRUPT 25 25 AUX5_GTC_SYNC_ERROR_INTERRUPT 26 26 AUX6_GTC_SYNC_LOCK_DONE_INTERRUPT 27 27 AUX6_GTC_SYNC_ERROR_INTERRUPT 28 28 MCIF_DWB0_IHIF_INTERRUPT 29 29 MCIF_DWB1_IHIF_INTERRUPT 30 30 DISP_INTERRUPT_STATUS_CONTINUE7 31 31 mmDISP_INTERRUPT_STATUS_CONTINUE7 0 0x131 9 0 2 DCCG_PERFMON_COUNTER0_INTERRUPT 0 0 DCCG_PERFMON_COUNTER1_INTERRUPT 1 1 DMU_PERFMON_COUNTER0_INTERRUPT 9 9 DMU_PERFMON_COUNTER1_INTERRUPT 10 10 DIO_PERFMON_COUNTER0_INTERRUPT 18 18 DIO_PERFMON_COUNTER1_INTERRUPT 19 19 WB0_PERFMON_COUNTER0_INTERRUPT 27 27 WB0_PERFMON_COUNTER1_INTERRUPT 28 28 DISP_INTERRUPT_STATUS_CONTINUE8 31 31 mmDISP_INTERRUPT_STATUS_CONTINUE8 0 0x132 7 0 2 DPP0_PERFMON_COUNTER0_INTERRUPT 0 0 DPP0_PERFMON_COUNTER1_INTERRUPT 1 1 DPP1_PERFMON_COUNTER0_INTERRUPT 9 9 DPP1_PERFMON_COUNTER1_INTERRUPT 10 10 DPP2_PERFMON_COUNTER0_INTERRUPT 18 18 DPP2_PERFMON_COUNTER1_INTERRUPT 19 19 DISP_INTERRUPT_STATUS_CONTINUE9 31 31 mmDISP_INTERRUPT_STATUS_CONTINUE9 0 0x133 9 0 2 DPP3_PERFMON_COUNTER0_INTERRUPT 0 0 DPP3_PERFMON_COUNTER1_INTERRUPT 1 1 DPP4_PERFMON_COUNTER0_INTERRUPT 9 9 DPP4_PERFMON_COUNTER1_INTERRUPT 10 10 DPP5_PERFMON_COUNTER0_INTERRUPT 18 18 DPP5_PERFMON_COUNTER1_INTERRUPT 19 19 WBSCL1_HOST_CONFLICT_INTERRUPT 28 28 WBSCL1_DATA_OVERFLOW_INTERRUPT 29 29 DISP_INTERRUPT_STATUS_CONTINUE10 31 31 mmDISP_INTERRUPT_STATUS_CONTINUE10 0 0x134 15 0 2 DCCG_IHC_VSYNC_OTG0_LATCH_INT 0 0 DCCG_IHC_VSYNC_OTG1_LATCH_INT 1 1 DCCG_IHC_VSYNC_OTG2_LATCH_INT 2 2 DCCG_IHC_VSYNC_OTG3_LATCH_INT 3 3 DCCG_IHC_VSYNC_OTG4_LATCH_INT 4 4 DCCG_IHC_VSYNC_OTG5_LATCH_INT 5 5 DCCG_PERFMON2_COUNTER0_INTERRUPT 12 12 DCCG_PERFMON2_COUNTER1_INTERRUPT 13 13 OTG1_IHC_RANGE_TIMING_UPDATE 22 22 OTG2_IHC_RANGE_TIMING_UPDATE 23 23 OTG3_IHC_RANGE_TIMING_UPDATE 24 24 OTG4_IHC_RANGE_TIMING_UPDATE 25 25 OTG5_IHC_RANGE_TIMING_UPDATE 26 26 OTG6_IHC_RANGE_TIMING_UPDATE 27 27 DISP_INTERRUPT_STATUS_CONTINUE11 31 31 mmDISP_INTERRUPT_STATUS_CONTINUE11 0 0x135 12 0 2 WB1_PERFMON_COUNTER0_INTERRUPT 6 6 WB1_PERFMON_COUNTER1_INTERRUPT 7 7 MPCC0_STALL_INTERRUPT 15 15 MPCC1_STALL_INTERRUPT 16 16 MPCC2_STALL_INTERRUPT 17 17 MPCC3_STALL_INTERRUPT 18 18 MPCC4_STALL_INTERRUPT 19 19 MPCC5_STALL_INTERRUPT 20 20 MPCC6_STALL_INTERRUPT 21 21 MPCC7_STALL_INTERRUPT 22 22 VGA_IHC_VGA_CRT_INTERRUPT 23 23 DISP_INTERRUPT_STATUS_CONTINUE12 31 31 mmDISP_INTERRUPT_STATUS_CONTINUE12 0 0x136 7 0 2 MPC_PERFMON_COUNTER0_INTERRUPT 0 0 MPC_PERFMON_COUNTER1_INTERRUPT 1 1 DPP6_PERFMON_COUNTER0_INTERRUPT 9 9 DPP6_PERFMON_COUNTER1_INTERRUPT 10 10 DPP7_PERFMON_COUNTER0_INTERRUPT 18 18 DPP7_PERFMON_COUNTER1_INTERRUPT 19 19 DISP_INTERRUPT_STATUS_CONTINUE13 31 31 mmDISP_INTERRUPT_STATUS_CONTINUE13 0 0x137 17 0 2 HUBBUB_PERFMON_COUNTER0_INTERRUPT 0 0 HUBBUB_PERFMON_COUNTER1_INTERRUPT 1 1 DCPG_IHC_DOMAIN0_POWER_UP_INTERRUPT 9 9 DCPG_IHC_DOMAIN1_POWER_UP_INTERRUPT 10 10 DCPG_IHC_DOMAIN2_POWER_UP_INTERRUPT 11 11 DCPG_IHC_DOMAIN3_POWER_UP_INTERRUPT 12 12 DCPG_IHC_DOMAIN4_POWER_UP_INTERRUPT 13 13 DCPG_IHC_DOMAIN5_POWER_UP_INTERRUPT 14 14 DCPG_IHC_DOMAIN6_POWER_UP_INTERRUPT 15 15 DCPG_IHC_DOMAIN7_POWER_UP_INTERRUPT 16 16 HUBP0_PERFMON_COUNTER0_INTERRUPT 18 18 HUBP0_PERFMON_COUNTER1_INTERRUPT 19 19 HUBP0_IHC_VBLANK_INTERRUPT 27 27 HUBP0_IHC_VLINE_INTERRUPT 28 28 HUBP0_IHC_VLINE2_INTERRUPT 29 29 HUBP0_IHC_VM_CONTEXT_ERROR_INTERRUPT 30 30 DISP_INTERRUPT_STATUS_CONTINUE14 31 31 mmDISP_INTERRUPT_STATUS_CONTINUE14 0 0x138 11 0 2 HUBP1_PERFMON_COUNTER0_INTERRUPT 0 0 HUBP1_PERFMON_COUNTER1_INTERRUPT 1 1 HUBP2_PERFMON_COUNTER0_INTERRUPT 9 9 HUBP2_PERFMON_COUNTER1_INTERRUPT 10 10 HUBP3_PERFMON_COUNTER0_INTERRUPT 18 18 HUBP3_PERFMON_COUNTER1_INTERRUPT 19 19 HUBP1_IHC_VBLANK_INTERRUPT 27 27 HUBP1_IHC_VLINE_INTERRUPT 28 28 HUBP1_IHC_VLINE2_INTERRUPT 29 29 HUBP1_IHC_VM_CONTEXT_ERROR_INTERRUPT 30 30 DISP_INTERRUPT_STATUS_CONTINUE15 31 31 mmDISP_INTERRUPT_STATUS_CONTINUE15 0 0x139 11 0 2 HUBP4_PERFMON_COUNTER0_INTERRUPT 0 0 HUBP4_PERFMON_COUNTER1_INTERRUPT 1 1 HUBP5_PERFMON_COUNTER0_INTERRUPT 9 9 HUBP5_PERFMON_COUNTER1_INTERRUPT 10 10 HUBP6_PERFMON_COUNTER0_INTERRUPT 18 18 HUBP6_PERFMON_COUNTER1_INTERRUPT 19 19 HUBP2_IHC_VBLANK_INTERRUPT 27 27 HUBP2_IHC_VLINE_INTERRUPT 28 28 HUBP2_IHC_VLINE2_INTERRUPT 29 29 HUBP2_IHC_VM_CONTEXT_ERROR_INTERRUPT 30 30 DISP_INTERRUPT_STATUS_CONTINUE16 31 31 mmDISP_INTERRUPT_STATUS_CONTINUE16 0 0x13a 23 0 2 HUBP7_PERFMON_COUNTER0_INTERRUPT 0 0 HUBP7_PERFMON_COUNTER1_INTERRUPT 1 1 HUBP3_IHC_VBLANK_INTERRUPT 9 9 HUBP3_IHC_VLINE_INTERRUPT 10 10 HUBP3_IHC_VLINE2_INTERRUPT 11 11 HUBP4_IHC_VBLANK_INTERRUPT 12 12 HUBP4_IHC_VLINE_INTERRUPT 13 13 HUBP4_IHC_VLINE2_INTERRUPT 14 14 HUBP5_IHC_VBLANK_INTERRUPT 15 15 HUBP5_IHC_VLINE_INTERRUPT 16 16 HUBP5_IHC_VLINE2_INTERRUPT 17 17 HUBP6_IHC_VBLANK_INTERRUPT 18 18 HUBP6_IHC_VLINE_INTERRUPT 19 19 HUBP6_IHC_VLINE2_INTERRUPT 20 20 HUBP7_IHC_VBLANK_INTERRUPT 21 21 HUBP7_IHC_VLINE_INTERRUPT 22 22 HUBP7_IHC_VLINE2_INTERRUPT 23 23 HUBP3_IHC_VM_CONTEXT_ERROR_INTERRUPT 24 24 HUBP4_IHC_VM_CONTEXT_ERROR_INTERRUPT 25 25 HUBP5_IHC_VM_CONTEXT_ERROR_INTERRUPT 26 26 HUBP6_IHC_VM_CONTEXT_ERROR_INTERRUPT 27 27 HUBP7_IHC_VM_CONTEXT_ERROR_INTERRUPT 28 28 DISP_INTERRUPT_STATUS_CONTINUE17 31 31 mmDISP_INTERRUPT_STATUS_CONTINUE17 0 0x13b 23 0 2 OPP_PERFMON_COUNTER0_INTERRUPT 0 0 OPP_PERFMON_COUNTER1_INTERRUPT 1 1 HUBP0_IHC_FLIP_INTERRUPT 2 2 HUBP1_IHC_FLIP_INTERRUPT 3 3 HUBP2_IHC_FLIP_INTERRUPT 4 4 HUBP3_IHC_FLIP_INTERRUPT 5 5 HUBP4_IHC_FLIP_INTERRUPT 6 6 HUBP5_IHC_FLIP_INTERRUPT 7 7 HUBP6_IHC_FLIP_INTERRUPT 8 8 HUBP7_IHC_FLIP_INTERRUPT 9 9 OPTC_PERFMON_COUNTER0_INTERRUPT 10 10 OPTC_PERFMON_COUNTER1_INTERRUPT 11 11 MMHUBBUB_PERFMON_COUNTER0_INTERRUPT 18 18 MMHUBBUB_PERFMON_COUNTER1_INTERRUPT 19 19 HUBP0_IHC_FLIP_AWAY_INTERRUPT 20 20 HUBP1_IHC_FLIP_AWAY_INTERRUPT 21 21 HUBP2_IHC_FLIP_AWAY_INTERRUPT 22 22 HUBP3_IHC_FLIP_AWAY_INTERRUPT 23 23 HUBP4_IHC_FLIP_AWAY_INTERRUPT 24 24 HUBP5_IHC_FLIP_AWAY_INTERRUPT 25 25 HUBP6_IHC_FLIP_AWAY_INTERRUPT 26 26 HUBP7_IHC_FLIP_AWAY_INTERRUPT 27 27 DISP_INTERRUPT_STATUS_CONTINUE18 31 31 mmDISP_INTERRUPT_STATUS_CONTINUE18 0 0x13c 19 0 2 AZ_PERFMON_COUNTER0_INTERRUPT 0 0 AZ_PERFMON_COUNTER1_INTERRUPT 1 1 DCIO_DPCS_TXA_IHC_ERROR_INTERRUPT 9 9 DCIO_DPCS_TXB_IHC_ERROR_INTERRUPT 10 10 DCIO_DPCS_TXC_IHC_ERROR_INTERRUPT 11 11 DCIO_DPCS_TXD_IHC_ERROR_INTERRUPT 12 12 DCIO_DPCS_TXE_IHC_ERROR_INTERRUPT 13 13 DCIO_DPCS_TXF_IHC_ERROR_INTERRUPT 14 14 DCIO_DPCS_TXG_IHC_ERROR_INTERRUPT 15 15 DCIO_DPCS_RXA_IHC_ERROR_INTERRUPT 16 16 DCPG_IHC_DOMAIN0_POWER_DOWN_INTERRUPT 17 17 DCPG_IHC_DOMAIN1_POWER_DOWN_INTERRUPT 18 18 DCPG_IHC_DOMAIN2_POWER_DOWN_INTERRUPT 19 19 DCPG_IHC_DOMAIN3_POWER_DOWN_INTERRUPT 20 20 DCPG_IHC_DOMAIN4_POWER_DOWN_INTERRUPT 21 21 DCPG_IHC_DOMAIN5_POWER_DOWN_INTERRUPT 22 22 DCPG_IHC_DOMAIN6_POWER_DOWN_INTERRUPT 23 23 DCPG_IHC_DOMAIN7_POWER_DOWN_INTERRUPT 24 24 DISP_INTERRUPT_STATUS_CONTINUE19 31 31 mmDISP_INTERRUPT_STATUS_CONTINUE19 0 0x13d 27 0 2 AZ_IHC_ENDPOINT0_AUDIO_FORMAT_CHANGED_INT 0 0 AZ_IHC_ENDPOINT1_AUDIO_FORMAT_CHANGED_INT 1 1 AZ_IHC_ENDPOINT2_AUDIO_FORMAT_CHANGED_INT 2 2 AZ_IHC_ENDPOINT3_AUDIO_FORMAT_CHANGED_INT 3 3 AZ_IHC_ENDPOINT4_AUDIO_FORMAT_CHANGED_INT 4 4 AZ_IHC_ENDPOINT5_AUDIO_FORMAT_CHANGED_INT 5 5 AZ_IHC_ENDPOINT6_AUDIO_FORMAT_CHANGED_INT 6 6 AZ_IHC_ENDPOINT7_AUDIO_FORMAT_CHANGED_INT 7 7 AZ_IHC_ENDPOINT0_AUDIO_ENABLED_INT 8 8 AZ_IHC_ENDPOINT1_AUDIO_ENABLED_INT 9 9 AZ_IHC_ENDPOINT2_AUDIO_ENABLED_INT 10 10 AZ_IHC_ENDPOINT3_AUDIO_ENABLED_INT 11 11 AZ_IHC_ENDPOINT4_AUDIO_ENABLED_INT 12 12 AZ_IHC_ENDPOINT5_AUDIO_ENABLED_INT 13 13 AZ_IHC_ENDPOINT6_AUDIO_ENABLED_INT 14 14 AZ_IHC_ENDPOINT7_AUDIO_ENABLED_INT 15 15 AZ_IHC_ENDPOINT0_AUDIO_DISABLED_INT 16 16 AZ_IHC_ENDPOINT1_AUDIO_DISABLED_INT 17 17 AZ_IHC_ENDPOINT2_AUDIO_DISABLED_INT 18 18 AZ_IHC_ENDPOINT3_AUDIO_DISABLED_INT 19 19 AZ_IHC_ENDPOINT4_AUDIO_DISABLED_INT 20 20 AZ_IHC_ENDPOINT5_AUDIO_DISABLED_INT 21 21 AZ_IHC_ENDPOINT6_AUDIO_DISABLED_INT 22 22 AZ_IHC_ENDPOINT7_AUDIO_DISABLED_INT 23 23 DIGG_DP_FAST_TRAINING_COMPLETE_INTERRUPT 28 28 DIGG_DP_VID_STREAM_DISABLE_INTERRUPT 29 29 DISP_INTERRUPT_STATUS_CONTINUE20 31 31 mmDISP_INTERRUPT_STATUS_CONTINUE20 0 0x13e 31 0 2 OTG1_IHC_CPU_SS_INTERRUPT 0 0 OTG2_IHC_CPU_SS_INTERRUPT 1 1 OTG3_IHC_CPU_SS_INTERRUPT 2 2 OTG4_IHC_CPU_SS_INTERRUPT 3 3 OTG5_IHC_CPU_SS_INTERRUPT 4 4 OTG6_IHC_CPU_SS_INTERRUPT 5 5 OTG1_IHC_V_UPDATE_INTERRUPT 6 6 OTG2_IHC_V_UPDATE_INTERRUPT 7 7 OTG3_IHC_V_UPDATE_INTERRUPT 8 8 OTG4_IHC_V_UPDATE_INTERRUPT 9 9 OTG5_IHC_V_UPDATE_INTERRUPT 10 10 OTG6_IHC_V_UPDATE_INTERRUPT 11 11 OTG1_IHC_GSL_VSYNC_GAP_INTERRUPT 12 12 OTG2_IHC_GSL_VSYNC_GAP_INTERRUPT 13 13 OTG3_IHC_GSL_VSYNC_GAP_INTERRUPT 14 14 OTG4_IHC_GSL_VSYNC_GAP_INTERRUPT 15 15 OTG5_IHC_GSL_VSYNC_GAP_INTERRUPT 16 16 OTG6_IHC_GSL_VSYNC_GAP_INTERRUPT 17 17 OTG1_IHC_VSTARTUP_INTERRUPT 18 18 OTG2_IHC_VSTARTUP_INTERRUPT 19 19 OTG3_IHC_VSTARTUP_INTERRUPT 20 20 OTG4_IHC_VSTARTUP_INTERRUPT 21 21 OTG5_IHC_VSTARTUP_INTERRUPT 22 22 OTG6_IHC_VSTARTUP_INTERRUPT 23 23 OTG1_IHC_VREADY_INTERRUPT 24 24 OTG2_IHC_VREADY_INTERRUPT 25 25 OTG3_IHC_VREADY_INTERRUPT 26 26 OTG4_IHC_VREADY_INTERRUPT 27 27 OTG5_IHC_VREADY_INTERRUPT 28 28 OTG6_IHC_VREADY_INTERRUPT 29 29 DISP_INTERRUPT_STATUS_CONTINUE21 31 31 mmDISP_INTERRUPT_STATUS_CONTINUE21 0 0x13f 18 0 2 DOUT_IHC_I2C_DDC1_HW_DONE_INTERRUPT 0 0 DOUT_IHC_I2C_DDC2_HW_DONE_INTERRUPT 1 1 DOUT_IHC_I2C_DDC3_HW_DONE_INTERRUPT 2 2 DOUT_IHC_I2C_DDC4_HW_DONE_INTERRUPT 3 3 DOUT_IHC_I2C_DDC5_HW_DONE_INTERRUPT 4 4 DOUT_IHC_I2C_DDC6_HW_DONE_INTERRUPT 5 5 DOUT_IHC_I2C_DDCVGA_HW_DONE_INTERRUPT 6 6 DC_I2C_DDC1_READ_REQUEST_INTERRUPT 7 7 DC_I2C_DDC2_READ_REQUEST_INTERRUPT 8 8 DC_I2C_DDC3_READ_REQUEST_INTERRUPT 9 9 DC_I2C_DDC4_READ_REQUEST_INTERRUPT 10 10 DC_I2C_DDC5_READ_REQUEST_INTERRUPT 11 11 DC_I2C_DDC6_READ_REQUEST_INTERRUPT 12 12 DC_I2C_VGA_READ_REQUEST_INTERRUPT 13 13 GENERIC_I2C_DDC_READ_REUEST_INTERRUPT 14 14 DIGH_DP_FAST_TRAINING_COMPLETE_INTERRUPT 28 28 DIGH_DP_VID_STREAM_DISABLE_INTERRUPT 29 29 DISP_INTERRUPT_STATUS_CONTINUE22 31 31 mmDISP_INTERRUPT_STATUS_CONTINUE22 0 0x140 25 0 2 DCPG_IHC_DOMAIN8_POWER_UP_INTERRUPT 0 0 DCPG_IHC_DOMAIN9_POWER_UP_INTERRUPT 1 1 DCPG_IHC_DOMAIN10_POWER_UP_INTERRUPT 2 2 DCPG_IHC_DOMAIN11_POWER_UP_INTERRUPT 3 3 DCPG_IHC_DOMAIN12_POWER_UP_INTERRUPT 4 4 DCPG_IHC_DOMAIN13_POWER_UP_INTERRUPT 5 5 DCPG_IHC_DOMAIN14_POWER_UP_INTERRUPT 6 6 DCPG_IHC_DOMAIN15_POWER_UP_INTERRUPT 7 7 DCPG_IHC_DOMAIN8_POWER_DOWN_INTERRUPT 8 8 DCPG_IHC_DOMAIN9_POWER_DOWN_INTERRUPT 9 9 DCPG_IHC_DOMAIN10_POWER_DOWN_INTERRUPT 10 10 DCPG_IHC_DOMAIN11_POWER_DOWN_INTERRUPT 11 11 DCPG_IHC_DOMAIN12_POWER_DOWN_INTERRUPT 12 12 DCPG_IHC_DOMAIN13_POWER_DOWN_INTERRUPT 13 13 DCPG_IHC_DOMAIN14_POWER_DOWN_INTERRUPT 14 14 DCPG_IHC_DOMAIN15_POWER_DOWN_INTERRUPT 15 15 ABM0_HG_READY_INT 16 16 ABM0_LS_READY_INT 17 17 ABM0_BL_UPDATE_INT 18 18 OTG0_IHC_V_UPDATE_NO_LOCK_INTERRUPT 19 19 OTG1_IHC_V_UPDATE_NO_LOCK_INTERRUPT 20 20 OTG2_IHC_V_UPDATE_NO_LOCK_INTERRUPT 21 21 OTG3_IHC_V_UPDATE_NO_LOCK_INTERRUPT 22 22 OTG4_IHC_V_UPDATE_NO_LOCK_INTERRUPT 23 23 OTG5_IHC_V_UPDATE_NO_LOCK_INTERRUPT 24 24 mmDC_GPU_TIMER_START_POSITION_VREADY 0 0x141 6 0 2 DC_GPU_TIMER_START_POSITION_D1_VREADY 0 2 DC_GPU_TIMER_START_POSITION_D2_VREADY 4 6 DC_GPU_TIMER_START_POSITION_D3_VREADY 8 10 DC_GPU_TIMER_START_POSITION_D4_VREADY 12 14 DC_GPU_TIMER_START_POSITION_D5_VREADY 16 18 DC_GPU_TIMER_START_POSITION_D6_VREADY 20 22 mmDC_GPU_TIMER_START_POSITION_FLIP 0 0x142 8 0 2 DC_GPU_TIMER_START_POSITION_D1_FLIP 0 2 DC_GPU_TIMER_START_POSITION_D2_FLIP 4 6 DC_GPU_TIMER_START_POSITION_D3_FLIP 8 10 DC_GPU_TIMER_START_POSITION_D4_FLIP 12 14 DC_GPU_TIMER_START_POSITION_D5_FLIP 16 18 DC_GPU_TIMER_START_POSITION_D6_FLIP 20 22 DC_GPU_TIMER_START_POSITION_D7_FLIP 24 26 DC_GPU_TIMER_START_POSITION_D8_FLIP 28 30 mmDC_GPU_TIMER_START_POSITION_V_UPDATE_NO_LOCK 0 0x143 6 0 2 DC_GPU_TIMER_START_POSITION_D1_V_UPDATE_NO_LOCK 0 2 DC_GPU_TIMER_START_POSITION_D2_V_UPDATE_NO_LOCK 4 6 DC_GPU_TIMER_START_POSITION_D3_V_UPDATE_NO_LOCK 8 10 DC_GPU_TIMER_START_POSITION_D4_V_UPDATE_NO_LOCK 12 14 DC_GPU_TIMER_START_POSITION_D5_V_UPDATE_NO_LOCK 16 18 DC_GPU_TIMER_START_POSITION_D6_V_UPDATE_NO_LOCK 20 22 mmDC_GPU_TIMER_START_POSITION_FLIP_AWAY 0 0x144 8 0 2 DC_GPU_TIMER_START_POSITION_D1_FLIP_AWAY 0 2 DC_GPU_TIMER_START_POSITION_D2_FLIP_AWAY 4 6 DC_GPU_TIMER_START_POSITION_D3_FLIP_AWAY 8 10 DC_GPU_TIMER_START_POSITION_D4_FLIP_AWAY 12 14 DC_GPU_TIMER_START_POSITION_D5_FLIP_AWAY 16 18 DC_GPU_TIMER_START_POSITION_D6_FLIP_AWAY 20 22 DC_GPU_TIMER_START_POSITION_D7_FLIP_AWAY 24 26 DC_GPU_TIMER_START_POSITION_D8_FLIP_AWAY 28 30 mmCNV0_WB_ENABLE 0 0x1da 1 0 2 WB_ENABLE 0 0 mmCNV0_WB_EC_CONFIG 0 0x1db 18 0 2 DISPCLK_R_WB_GATE_DIS 0 0 DISPCLK_G_WB_GATE_DIS 1 1 DISPCLK_G_WBSCL_GATE_DIS 2 2 WB_TEST_CLK_SEL 3 6 WB_LB_LS_DIS 7 7 WB_LB_SD_DIS 8 8 WB_LUT_LS_DIS 9 9 WBSCL_LB_MEM_PWR_MODE_SEL 12 13 WBSCL_LB_MEM_PWR_DIS 14 14 WBSCL_LB_MEM_PWR_FORCE 15 16 WBSCL_LB_MEM_PWR_STATE_SM 17 18 WBSCL_LB_MEM_PWR_STATE_BG 19 20 WBSCL_LB_MEM_PWR_STATE 21 22 WB_RAM_PW_SAVE_MODE 23 23 LB_MEM_PWR_STATE_SM 24 25 LB_MEM_PWR_STATE_BG 26 27 LB_MEM_PWR_STATE 28 29 LUT_MEM_PWR_STATE 30 31 mmCNV0_CNV_MODE 0 0x1dc 10 0 2 CNV_FRAME_CAPTURE_RATE 8 9 CNV_WINDOW_CROP_EN 12 12 CNV_STEREO_TYPE 13 14 CNV_INTERLACED_MODE 15 15 CNV_EYE_SELECTION 16 17 CNV_STEREO_POLARITY 18 18 CNV_INTERLACED_FIELD_ORDER 19 19 CNV_STEREO_SPLIT 20 20 CNV_NEW_CONTENT 24 24 CNV_FRAME_CAPTURE_EN 31 31 mmCNV0_CNV_WINDOW_START 0 0x1dd 2 0 2 CNV_WINDOW_START_X 0 11 CNV_WINDOW_START_Y 16 27 mmCNV0_CNV_WINDOW_SIZE 0 0x1de 2 0 2 CNV_WINDOW_WIDTH 0 11 CNV_WINDOW_HEIGHT 16 27 mmCNV0_CNV_UPDATE 0 0x1df 3 0 2 CNV_UPDATE_PENDING 0 0 CNV_UPDATE_TAKEN 8 8 CNV_UPDATE_LOCK 16 16 mmCNV0_CNV_SOURCE_SIZE 0 0x1e0 2 0 2 CNV_SOURCE_WIDTH 0 14 CNV_SOURCE_HEIGHT 16 30 mmCNV0_CNV_CSC_CONTROL 0 0x1e1 1 0 2 CNV_CSC_BYPASS 0 0 mmCNV0_CNV_CSC_C11_C12 0 0x1e2 2 0 2 CNV_CSC_C11 0 12 CNV_CSC_C12 16 28 mmCNV0_CNV_CSC_C13_C14 0 0x1e3 2 0 2 CNV_CSC_C13 0 12 CNV_CSC_C14 16 30 mmCNV0_CNV_CSC_C21_C22 0 0x1e4 2 0 2 CNV_CSC_C21 0 12 CNV_CSC_C22 16 28 mmCNV0_CNV_CSC_C23_C24 0 0x1e5 2 0 2 CNV_CSC_C23 0 12 CNV_CSC_C24 16 30 mmCNV0_CNV_CSC_C31_C32 0 0x1e6 2 0 2 CNV_CSC_C31 0 12 CNV_CSC_C32 16 28 mmCNV0_CNV_CSC_C33_C34 0 0x1e7 2 0 2 CNV_CSC_C33 0 12 CNV_CSC_C34 16 30 mmCNV0_CNV_CSC_ROUND_OFFSET_R 0 0x1e8 1 0 2 CNV_CSC_ROUND_OFFSET_R 0 15 mmCNV0_CNV_CSC_ROUND_OFFSET_G 0 0x1e9 1 0 2 CNV_CSC_ROUND_OFFSET_G 0 15 mmCNV0_CNV_CSC_ROUND_OFFSET_B 0 0x1ea 1 0 2 CNV_CSC_ROUND_OFFSET_B 0 15 mmCNV0_CNV_CSC_CLAMP_R 0 0x1eb 2 0 2 CNV_CSC_CLAMP_UPPER_R 0 15 CNV_CSC_CLAMP_LOWER_R 16 31 mmCNV0_CNV_CSC_CLAMP_G 0 0x1ec 2 0 2 CNV_CSC_CLAMP_UPPER_G 0 15 CNV_CSC_CLAMP_LOWER_G 16 31 mmCNV0_CNV_CSC_CLAMP_B 0 0x1ed 2 0 2 CNV_CSC_CLAMP_UPPER_B 0 15 CNV_CSC_CLAMP_LOWER_B 16 31 mmCNV0_CNV_TEST_CNTL 0 0x1ee 3 0 2 CNV_TEST_CRC_EN 4 4 CNV_TEST_CRC_CONT_EN 8 8 CNV_TEST_CRC_DE_ONLY 16 16 mmCNV0_CNV_TEST_CRC_RED 0 0x1ef 2 0 2 CNV_TEST_CRC_RED_MASK 4 15 CNV_TEST_CRC_SIG_RED 16 31 mmCNV0_CNV_TEST_CRC_GREEN 0 0x1f0 2 0 2 CNV_TEST_CRC_GREEN_MASK 4 15 CNV_TEST_CRC_SIG_GREEN 16 31 mmCNV0_CNV_TEST_CRC_BLUE 0 0x1f1 2 0 2 CNV_TEST_CRC_BLUE_MASK 4 15 CNV_TEST_CRC_SIG_BLUE 16 31 mmCNV0_CNV_INPUT_SELECT 0 0x1f5 2 0 2 CNV_INPUT_SRC_SELECT 0 1 CNV_INPUT_PIPE_SELECT 2 4 mmCNV0_WB_SOFT_RESET 0 0x1f8 1 0 2 WB_SOFT_RESET 0 0 mmCNV0_WB_WARM_UP_MODE_CTL1 0 0x1f9 3 0 2 WIDTH_WARMUP 0 14 HEIGHT_WARMUP 16 30 GMC_WARM_UP_ENABLE 31 31 mmCNV0_WB_WARM_UP_MODE_CTL2 0 0x1fa 2 0 2 DATA_VALUE_WARMUP 0 7 MODE_WARMUP 8 8 mmWBSCL0_WBSCL_COEF_RAM_SELECT 0 0x20a 3 0 2 WBSCL_COEF_RAM_TAP_PAIR_IDX 0 2 WBSCL_COEF_RAM_PHASE 8 11 WBSCL_COEF_RAM_FILTER_TYPE 16 17 mmWBSCL0_WBSCL_COEF_RAM_TAP_DATA 0 0x20b 4 0 2 WBSCL_COEF_RAM_EVEN_TAP_COEF 0 13 WBSCL_COEF_RAM_EVEN_TAP_COEF_EN 15 15 WBSCL_COEF_RAM_ODD_TAP_COEF 16 29 WBSCL_COEF_RAM_ODD_TAP_COEF_EN 31 31 mmWBSCL0_WBSCL_MODE 0 0x20c 1 0 2 WBSCL_MODE 0 1 mmWBSCL0_WBSCL_TAP_CONTROL 0 0x20d 4 0 2 WBSCL_V_NUM_OF_TAPS_Y_RGB 0 3 WBSCL_V_NUM_OF_TAPS_CBCR 4 7 WBSCL_H_NUM_OF_TAPS_Y_RGB 8 11 WBSCL_H_NUM_OF_TAPS_CBCR 12 15 mmWBSCL0_WBSCL_DEST_SIZE 0 0x20e 2 0 2 WBSCL_DEST_HEIGHT 0 14 WBSCL_DEST_WIDTH 16 30 mmWBSCL0_WBSCL_HORZ_FILTER_SCALE_RATIO 0 0x20f 1 0 2 WBSCL_H_SCALE_RATIO 0 26 mmWBSCL0_WBSCL_HORZ_FILTER_INIT_Y_RGB 0 0x210 2 0 2 WBSCL_H_INIT_FRAC_Y_RGB 0 23 WBSCL_H_INIT_INT_Y_RGB 24 28 mmWBSCL0_WBSCL_HORZ_FILTER_INIT_CBCR 0 0x211 2 0 2 WBSCL_H_INIT_FRAC_CBCR 0 23 WBSCL_H_INIT_INT_CBCR 24 28 mmWBSCL0_WBSCL_VERT_FILTER_SCALE_RATIO 0 0x212 1 0 2 WBSCL_V_SCALE_RATIO 0 26 mmWBSCL0_WBSCL_VERT_FILTER_INIT_Y_RGB 0 0x213 2 0 2 WBSCL_V_INIT_FRAC_Y_RGB 0 23 WBSCL_V_INIT_INT_Y_RGB 24 28 mmWBSCL0_WBSCL_VERT_FILTER_INIT_CBCR 0 0x214 2 0 2 WBSCL_V_INIT_FRAC_CBCR 0 23 WBSCL_V_INIT_INT_CBCR 24 28 mmWBSCL0_WBSCL_ROUND_OFFSET 0 0x215 2 0 2 WBSCL_ROUND_OFFSET_Y_RGB 0 15 WBSCL_ROUND_OFFSET_CBCR 16 31 mmWBSCL0_WBSCL_CLAMP 0 0x216 4 0 2 WBSCL_CLAMP_UPPER_Y_RGB 0 7 WBSCL_CLAMP_LOWER_Y_RGB 8 15 WBSCL_CLAMP_UPPER_CBCR 16 23 WBSCL_CLAMP_LOWER_CBCR 24 31 mmWBSCL0_WBSCL_OVERFLOW_STATUS 0 0x217 5 0 2 WBSCL_DATA_OVERFLOW_FLAG 0 0 WBSCL_DATA_OVERFLOW_ACK 8 8 WBSCL_DATA_OVERFLOW_MASK 12 12 WBSCL_DATA_OVERFLOW_INT_STATUS 16 16 WBSCL_DATA_OVERFLOW_INT_TYPE 20 20 mmWBSCL0_WBSCL_COEF_RAM_CONFLICT_STATUS 0 0x218 5 0 2 WBSCL_HOST_CONFLICT_FLAG 0 0 WBSCL_HOST_CONFLICT_ACK 8 8 WBSCL_HOST_CONFLICT_MASK 12 12 WBSCL_HOST_CONFLICT_INT_STATUS 16 16 WBSCL_HOST_CONFLICT_INT_TYPE 20 20 mmWBSCL0_WBSCL_OUTSIDE_PIX_STRATEGY 0 0x219 4 0 2 WBSCL_OUTSIDE_PIX_STRATEGY 0 0 WBSCL_BLACK_COLOR_B_CB 8 15 WBSCL_BLACK_COLOR_G_Y 16 23 WBSCL_BLACK_COLOR_R_CR 24 31 mmWBSCL0_WBSCL_TEST_CNTL 0 0x21a 3 0 2 WBSCL_TEST_CRC_EN 4 4 WBSCL_TEST_CRC_CONT_EN 8 8 WBSCL_TEST_CRC_DE_ONLY 16 16 mmWBSCL0_WBSCL_TEST_CRC_RED 0 0x21b 2 0 2 WBSCL_TEST_CRC_RED_MASK 8 15 WBSCL_TEST_CRC_SIG_RED 16 31 mmWBSCL0_WBSCL_TEST_CRC_GREEN 0 0x21c 2 0 2 WBSCL_TEST_CRC_GREEN_MASK 0 15 WBSCL_TEST_CRC_SIG_GREEN 16 31 mmWBSCL0_WBSCL_TEST_CRC_BLUE 0 0x21d 2 0 2 WBSCL_TEST_CRC_BLUE_MASK 8 15 WBSCL_TEST_CRC_SIG_BLUE 16 31 mmWBSCL0_WBSCL_BACKPRESSURE_CNT_EN 0 0x21e 1 0 2 WBSCL_BACKPRESSURE_CNT_EN 0 0 mmWBSCL0_WB_MCIF_BACKPRESSURE_CNT 0 0x21f 2 0 2 WB_MCIF_Y_MAX_BACKPRESSURE 0 15 WB_MCIF_C_MAX_BACKPRESSURE 16 31 mmWBSCL0_WBSCL_RAM_SHUTDOWN 0 0x222 1 0 2 WBSCL_RAM_SHUTDOWN_SEL 0 1 mmDC_PERFMON3_PERFCOUNTER_CNTL 0 0x23a 11 0 2 PERFCOUNTER_EVENT_SEL 0 8 PERFCOUNTER_CVALUE_SEL 9 11 PERFCOUNTER_INC_MODE 12 14 PERFCOUNTER_HW_CNTL_SEL 15 15 PERFCOUNTER_RUNEN_MODE 16 16 PERFCOUNTER_CNTOFF_START_DIS 22 22 PERFCOUNTER_RESTART_EN 23 23 PERFCOUNTER_INT_EN 24 24 PERFCOUNTER_OFF_MASK 25 25 PERFCOUNTER_ACTIVE 26 26 PERFCOUNTER_CNTL_SEL 29 31 mmDC_PERFMON3_PERFCOUNTER_CNTL2 0 0x23b 5 0 2 PERFCOUNTER_COUNTED_VALUE_TYPE 0 1 PERFCOUNTER_HW_STOP1_SEL 2 2 PERFCOUNTER_HW_STOP2_SEL 3 3 PERFCOUNTER_CNTOFF_SEL 8 13 PERFCOUNTER_CNTL2_SEL 29 31 mmDC_PERFMON3_PERFCOUNTER_STATE 0 0x23c 16 0 2 PERFCOUNTER_CNT0_STATE 0 1 PERFCOUNTER_STATE_SEL0 2 2 PERFCOUNTER_CNT1_STATE 4 5 PERFCOUNTER_STATE_SEL1 6 6 PERFCOUNTER_CNT2_STATE 8 9 PERFCOUNTER_STATE_SEL2 10 10 PERFCOUNTER_CNT3_STATE 12 13 PERFCOUNTER_STATE_SEL3 14 14 PERFCOUNTER_CNT4_STATE 16 17 PERFCOUNTER_STATE_SEL4 18 18 PERFCOUNTER_CNT5_STATE 20 21 PERFCOUNTER_STATE_SEL5 22 22 PERFCOUNTER_CNT6_STATE 24 25 PERFCOUNTER_STATE_SEL6 26 26 PERFCOUNTER_CNT7_STATE 28 29 PERFCOUNTER_STATE_SEL7 30 30 mmDC_PERFMON3_PERFMON_CNTL 0 0x23d 6 0 2 PERFMON_STATE 0 1 PERFMON_RPT_COUNT 8 27 PERFMON_CNTOFF_AND_OR 28 28 PERFMON_CNTOFF_INT_EN 29 29 PERFMON_CNTOFF_INT_STATUS 30 30 PERFMON_CNTOFF_INT_ACK 31 31 mmDC_PERFMON3_PERFMON_CNTL2 0 0x23e 4 0 2 PERFMON_CNTOFF_INT_TYPE 0 0 PERFMON_CLK_ENABLE 1 1 PERFMON_RUN_ENABLE_START_SEL 2 9 PERFMON_RUN_ENABLE_STOP_SEL 10 17 mmDC_PERFMON3_PERFMON_CVALUE_INT_MISC 0 0x23f 17 0 2 PERFCOUNTER_INT0_STATUS 0 0 PERFCOUNTER_INT1_STATUS 1 1 PERFCOUNTER_INT2_STATUS 2 2 PERFCOUNTER_INT3_STATUS 3 3 PERFCOUNTER_INT4_STATUS 4 4 PERFCOUNTER_INT5_STATUS 5 5 PERFCOUNTER_INT6_STATUS 6 6 PERFCOUNTER_INT7_STATUS 7 7 PERFCOUNTER_INT0_ACK 8 8 PERFCOUNTER_INT1_ACK 9 9 PERFCOUNTER_INT2_ACK 10 10 PERFCOUNTER_INT3_ACK 11 11 PERFCOUNTER_INT4_ACK 12 12 PERFCOUNTER_INT5_ACK 13 13 PERFCOUNTER_INT6_ACK 14 14 PERFCOUNTER_INT7_ACK 15 15 PERFMON_CVALUE_HI 16 31 mmDC_PERFMON3_PERFMON_CVALUE_LOW 0 0x240 1 0 2 PERFMON_CVALUE_LOW 0 31 mmDC_PERFMON3_PERFMON_HI 0 0x241 2 0 2 PERFMON_HI 0 15 PERFMON_READ_SEL 29 31 mmDC_PERFMON3_PERFMON_LOW 0 0x242 1 0 2 PERFMON_LOW 0 31 mmCNV1_WB_ENABLE 0 0x246 1 0 2 WB_ENABLE 0 0 mmCNV1_WB_EC_CONFIG 0 0x247 18 0 2 DISPCLK_R_WB_GATE_DIS 0 0 DISPCLK_G_WB_GATE_DIS 1 1 DISPCLK_G_WBSCL_GATE_DIS 2 2 WB_TEST_CLK_SEL 3 6 WB_LB_LS_DIS 7 7 WB_LB_SD_DIS 8 8 WB_LUT_LS_DIS 9 9 WBSCL_LB_MEM_PWR_MODE_SEL 12 13 WBSCL_LB_MEM_PWR_DIS 14 14 WBSCL_LB_MEM_PWR_FORCE 15 16 WBSCL_LB_MEM_PWR_STATE_SM 17 18 WBSCL_LB_MEM_PWR_STATE_BG 19 20 WBSCL_LB_MEM_PWR_STATE 21 22 WB_RAM_PW_SAVE_MODE 23 23 LB_MEM_PWR_STATE_SM 24 25 LB_MEM_PWR_STATE_BG 26 27 LB_MEM_PWR_STATE 28 29 LUT_MEM_PWR_STATE 30 31 mmCNV1_CNV_MODE 0 0x248 10 0 2 CNV_FRAME_CAPTURE_RATE 8 9 CNV_WINDOW_CROP_EN 12 12 CNV_STEREO_TYPE 13 14 CNV_INTERLACED_MODE 15 15 CNV_EYE_SELECTION 16 17 CNV_STEREO_POLARITY 18 18 CNV_INTERLACED_FIELD_ORDER 19 19 CNV_STEREO_SPLIT 20 20 CNV_NEW_CONTENT 24 24 CNV_FRAME_CAPTURE_EN 31 31 mmCNV1_CNV_WINDOW_START 0 0x249 2 0 2 CNV_WINDOW_START_X 0 11 CNV_WINDOW_START_Y 16 27 mmCNV1_CNV_WINDOW_SIZE 0 0x24a 2 0 2 CNV_WINDOW_WIDTH 0 11 CNV_WINDOW_HEIGHT 16 27 mmCNV1_CNV_UPDATE 0 0x24b 3 0 2 CNV_UPDATE_PENDING 0 0 CNV_UPDATE_TAKEN 8 8 CNV_UPDATE_LOCK 16 16 mmCNV1_CNV_SOURCE_SIZE 0 0x24c 2 0 2 CNV_SOURCE_WIDTH 0 14 CNV_SOURCE_HEIGHT 16 30 mmCNV1_CNV_CSC_CONTROL 0 0x24d 1 0 2 CNV_CSC_BYPASS 0 0 mmCNV1_CNV_CSC_C11_C12 0 0x24e 2 0 2 CNV_CSC_C11 0 12 CNV_CSC_C12 16 28 mmCNV1_CNV_CSC_C13_C14 0 0x24f 2 0 2 CNV_CSC_C13 0 12 CNV_CSC_C14 16 30 mmCNV1_CNV_CSC_C21_C22 0 0x250 2 0 2 CNV_CSC_C21 0 12 CNV_CSC_C22 16 28 mmCNV1_CNV_CSC_C23_C24 0 0x251 2 0 2 CNV_CSC_C23 0 12 CNV_CSC_C24 16 30 mmCNV1_CNV_CSC_C31_C32 0 0x252 2 0 2 CNV_CSC_C31 0 12 CNV_CSC_C32 16 28 mmCNV1_CNV_CSC_C33_C34 0 0x253 2 0 2 CNV_CSC_C33 0 12 CNV_CSC_C34 16 30 mmCNV1_CNV_CSC_ROUND_OFFSET_R 0 0x254 1 0 2 CNV_CSC_ROUND_OFFSET_R 0 15 mmCNV1_CNV_CSC_ROUND_OFFSET_G 0 0x255 1 0 2 CNV_CSC_ROUND_OFFSET_G 0 15 mmCNV1_CNV_CSC_ROUND_OFFSET_B 0 0x256 1 0 2 CNV_CSC_ROUND_OFFSET_B 0 15 mmCNV1_CNV_CSC_CLAMP_R 0 0x257 2 0 2 CNV_CSC_CLAMP_UPPER_R 0 15 CNV_CSC_CLAMP_LOWER_R 16 31 mmCNV1_CNV_CSC_CLAMP_G 0 0x258 2 0 2 CNV_CSC_CLAMP_UPPER_G 0 15 CNV_CSC_CLAMP_LOWER_G 16 31 mmCNV1_CNV_CSC_CLAMP_B 0 0x259 2 0 2 CNV_CSC_CLAMP_UPPER_B 0 15 CNV_CSC_CLAMP_LOWER_B 16 31 mmCNV1_CNV_TEST_CNTL 0 0x25a 3 0 2 CNV_TEST_CRC_EN 4 4 CNV_TEST_CRC_CONT_EN 8 8 CNV_TEST_CRC_DE_ONLY 16 16 mmCNV1_CNV_TEST_CRC_RED 0 0x25b 2 0 2 CNV_TEST_CRC_RED_MASK 4 15 CNV_TEST_CRC_SIG_RED 16 31 mmCNV1_CNV_TEST_CRC_GREEN 0 0x25c 2 0 2 CNV_TEST_CRC_GREEN_MASK 4 15 CNV_TEST_CRC_SIG_GREEN 16 31 mmCNV1_CNV_TEST_CRC_BLUE 0 0x25d 2 0 2 CNV_TEST_CRC_BLUE_MASK 4 15 CNV_TEST_CRC_SIG_BLUE 16 31 mmCNV1_CNV_INPUT_SELECT 0 0x261 2 0 2 CNV_INPUT_SRC_SELECT 0 1 CNV_INPUT_PIPE_SELECT 2 4 mmCNV1_WB_SOFT_RESET 0 0x264 1 0 2 WB_SOFT_RESET 0 0 mmCNV1_WB_WARM_UP_MODE_CTL1 0 0x265 3 0 2 WIDTH_WARMUP 0 14 HEIGHT_WARMUP 16 30 GMC_WARM_UP_ENABLE 31 31 mmCNV1_WB_WARM_UP_MODE_CTL2 0 0x266 2 0 2 DATA_VALUE_WARMUP 0 7 MODE_WARMUP 8 8 mmWBSCL1_WBSCL_COEF_RAM_SELECT 0 0x276 3 0 2 WBSCL_COEF_RAM_TAP_PAIR_IDX 0 2 WBSCL_COEF_RAM_PHASE 8 11 WBSCL_COEF_RAM_FILTER_TYPE 16 17 mmWBSCL1_WBSCL_COEF_RAM_TAP_DATA 0 0x277 4 0 2 WBSCL_COEF_RAM_EVEN_TAP_COEF 0 13 WBSCL_COEF_RAM_EVEN_TAP_COEF_EN 15 15 WBSCL_COEF_RAM_ODD_TAP_COEF 16 29 WBSCL_COEF_RAM_ODD_TAP_COEF_EN 31 31 mmWBSCL1_WBSCL_MODE 0 0x278 1 0 2 WBSCL_MODE 0 1 mmWBSCL1_WBSCL_TAP_CONTROL 0 0x279 4 0 2 WBSCL_V_NUM_OF_TAPS_Y_RGB 0 3 WBSCL_V_NUM_OF_TAPS_CBCR 4 7 WBSCL_H_NUM_OF_TAPS_Y_RGB 8 11 WBSCL_H_NUM_OF_TAPS_CBCR 12 15 mmWBSCL1_WBSCL_DEST_SIZE 0 0x27a 2 0 2 WBSCL_DEST_HEIGHT 0 14 WBSCL_DEST_WIDTH 16 30 mmWBSCL1_WBSCL_HORZ_FILTER_SCALE_RATIO 0 0x27b 1 0 2 WBSCL_H_SCALE_RATIO 0 26 mmWBSCL1_WBSCL_HORZ_FILTER_INIT_Y_RGB 0 0x27c 2 0 2 WBSCL_H_INIT_FRAC_Y_RGB 0 23 WBSCL_H_INIT_INT_Y_RGB 24 28 mmWBSCL1_WBSCL_HORZ_FILTER_INIT_CBCR 0 0x27d 2 0 2 WBSCL_H_INIT_FRAC_CBCR 0 23 WBSCL_H_INIT_INT_CBCR 24 28 mmWBSCL1_WBSCL_VERT_FILTER_SCALE_RATIO 0 0x27e 1 0 2 WBSCL_V_SCALE_RATIO 0 26 mmWBSCL1_WBSCL_VERT_FILTER_INIT_Y_RGB 0 0x27f 2 0 2 WBSCL_V_INIT_FRAC_Y_RGB 0 23 WBSCL_V_INIT_INT_Y_RGB 24 28 mmWBSCL1_WBSCL_VERT_FILTER_INIT_CBCR 0 0x280 2 0 2 WBSCL_V_INIT_FRAC_CBCR 0 23 WBSCL_V_INIT_INT_CBCR 24 28 mmWBSCL1_WBSCL_ROUND_OFFSET 0 0x281 2 0 2 WBSCL_ROUND_OFFSET_Y_RGB 0 15 WBSCL_ROUND_OFFSET_CBCR 16 31 mmWBSCL1_WBSCL_CLAMP 0 0x282 4 0 2 WBSCL_CLAMP_UPPER_Y_RGB 0 7 WBSCL_CLAMP_LOWER_Y_RGB 8 15 WBSCL_CLAMP_UPPER_CBCR 16 23 WBSCL_CLAMP_LOWER_CBCR 24 31 mmWBSCL1_WBSCL_OVERFLOW_STATUS 0 0x283 5 0 2 WBSCL_DATA_OVERFLOW_FLAG 0 0 WBSCL_DATA_OVERFLOW_ACK 8 8 WBSCL_DATA_OVERFLOW_MASK 12 12 WBSCL_DATA_OVERFLOW_INT_STATUS 16 16 WBSCL_DATA_OVERFLOW_INT_TYPE 20 20 mmWBSCL1_WBSCL_COEF_RAM_CONFLICT_STATUS 0 0x284 5 0 2 WBSCL_HOST_CONFLICT_FLAG 0 0 WBSCL_HOST_CONFLICT_ACK 8 8 WBSCL_HOST_CONFLICT_MASK 12 12 WBSCL_HOST_CONFLICT_INT_STATUS 16 16 WBSCL_HOST_CONFLICT_INT_TYPE 20 20 mmWBSCL1_WBSCL_OUTSIDE_PIX_STRATEGY 0 0x285 4 0 2 WBSCL_OUTSIDE_PIX_STRATEGY 0 0 WBSCL_BLACK_COLOR_B_CB 8 15 WBSCL_BLACK_COLOR_G_Y 16 23 WBSCL_BLACK_COLOR_R_CR 24 31 mmWBSCL1_WBSCL_TEST_CNTL 0 0x286 3 0 2 WBSCL_TEST_CRC_EN 4 4 WBSCL_TEST_CRC_CONT_EN 8 8 WBSCL_TEST_CRC_DE_ONLY 16 16 mmWBSCL1_WBSCL_TEST_CRC_RED 0 0x287 2 0 2 WBSCL_TEST_CRC_RED_MASK 8 15 WBSCL_TEST_CRC_SIG_RED 16 31 mmWBSCL1_WBSCL_TEST_CRC_GREEN 0 0x288 2 0 2 WBSCL_TEST_CRC_GREEN_MASK 0 15 WBSCL_TEST_CRC_SIG_GREEN 16 31 mmWBSCL1_WBSCL_TEST_CRC_BLUE 0 0x289 2 0 2 WBSCL_TEST_CRC_BLUE_MASK 8 15 WBSCL_TEST_CRC_SIG_BLUE 16 31 mmWBSCL1_WBSCL_BACKPRESSURE_CNT_EN 0 0x28a 1 0 2 WBSCL_BACKPRESSURE_CNT_EN 0 0 mmWBSCL1_WB_MCIF_BACKPRESSURE_CNT 0 0x28b 2 0 2 WB_MCIF_Y_MAX_BACKPRESSURE 0 15 WB_MCIF_C_MAX_BACKPRESSURE 16 31 mmWBSCL1_WBSCL_RAM_SHUTDOWN 0 0x28e 1 0 2 WBSCL_RAM_SHUTDOWN_SEL 0 1 mmDC_PERFMON4_PERFCOUNTER_CNTL 0 0x2a6 11 0 2 PERFCOUNTER_EVENT_SEL 0 8 PERFCOUNTER_CVALUE_SEL 9 11 PERFCOUNTER_INC_MODE 12 14 PERFCOUNTER_HW_CNTL_SEL 15 15 PERFCOUNTER_RUNEN_MODE 16 16 PERFCOUNTER_CNTOFF_START_DIS 22 22 PERFCOUNTER_RESTART_EN 23 23 PERFCOUNTER_INT_EN 24 24 PERFCOUNTER_OFF_MASK 25 25 PERFCOUNTER_ACTIVE 26 26 PERFCOUNTER_CNTL_SEL 29 31 mmDC_PERFMON4_PERFCOUNTER_CNTL2 0 0x2a7 5 0 2 PERFCOUNTER_COUNTED_VALUE_TYPE 0 1 PERFCOUNTER_HW_STOP1_SEL 2 2 PERFCOUNTER_HW_STOP2_SEL 3 3 PERFCOUNTER_CNTOFF_SEL 8 13 PERFCOUNTER_CNTL2_SEL 29 31 mmDC_PERFMON4_PERFCOUNTER_STATE 0 0x2a8 16 0 2 PERFCOUNTER_CNT0_STATE 0 1 PERFCOUNTER_STATE_SEL0 2 2 PERFCOUNTER_CNT1_STATE 4 5 PERFCOUNTER_STATE_SEL1 6 6 PERFCOUNTER_CNT2_STATE 8 9 PERFCOUNTER_STATE_SEL2 10 10 PERFCOUNTER_CNT3_STATE 12 13 PERFCOUNTER_STATE_SEL3 14 14 PERFCOUNTER_CNT4_STATE 16 17 PERFCOUNTER_STATE_SEL4 18 18 PERFCOUNTER_CNT5_STATE 20 21 PERFCOUNTER_STATE_SEL5 22 22 PERFCOUNTER_CNT6_STATE 24 25 PERFCOUNTER_STATE_SEL6 26 26 PERFCOUNTER_CNT7_STATE 28 29 PERFCOUNTER_STATE_SEL7 30 30 mmDC_PERFMON4_PERFMON_CNTL 0 0x2a9 6 0 2 PERFMON_STATE 0 1 PERFMON_RPT_COUNT 8 27 PERFMON_CNTOFF_AND_OR 28 28 PERFMON_CNTOFF_INT_EN 29 29 PERFMON_CNTOFF_INT_STATUS 30 30 PERFMON_CNTOFF_INT_ACK 31 31 mmDC_PERFMON4_PERFMON_CNTL2 0 0x2aa 4 0 2 PERFMON_CNTOFF_INT_TYPE 0 0 PERFMON_CLK_ENABLE 1 1 PERFMON_RUN_ENABLE_START_SEL 2 9 PERFMON_RUN_ENABLE_STOP_SEL 10 17 mmDC_PERFMON4_PERFMON_CVALUE_INT_MISC 0 0x2ab 17 0 2 PERFCOUNTER_INT0_STATUS 0 0 PERFCOUNTER_INT1_STATUS 1 1 PERFCOUNTER_INT2_STATUS 2 2 PERFCOUNTER_INT3_STATUS 3 3 PERFCOUNTER_INT4_STATUS 4 4 PERFCOUNTER_INT5_STATUS 5 5 PERFCOUNTER_INT6_STATUS 6 6 PERFCOUNTER_INT7_STATUS 7 7 PERFCOUNTER_INT0_ACK 8 8 PERFCOUNTER_INT1_ACK 9 9 PERFCOUNTER_INT2_ACK 10 10 PERFCOUNTER_INT3_ACK 11 11 PERFCOUNTER_INT4_ACK 12 12 PERFCOUNTER_INT5_ACK 13 13 PERFCOUNTER_INT6_ACK 14 14 PERFCOUNTER_INT7_ACK 15 15 PERFMON_CVALUE_HI 16 31 mmDC_PERFMON4_PERFMON_CVALUE_LOW 0 0x2ac 1 0 2 PERFMON_CVALUE_LOW 0 31 mmDC_PERFMON4_PERFMON_HI 0 0x2ad 2 0 2 PERFMON_HI 0 15 PERFMON_READ_SEL 29 31 mmDC_PERFMON4_PERFMON_LOW 0 0x2ae 1 0 2 PERFMON_LOW 0 31 mmMCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL 0 0x2b2 9 0 2 MCIF_WB_BUFMGR_ENABLE 0 0 MCIF_WB_BUF_DUALSIZE_REQ 1 1 MCIF_WB_BUFMGR_SW_INT_EN 4 4 MCIF_WB_BUFMGR_SW_INT_ACK 5 5 MCIF_WB_BUFMGR_SW_SLICE_INT_EN 6 6 MCIF_WB_BUFMGR_SW_OVERRUN_INT_EN 7 7 MCIF_WB_BUFMGR_SW_LOCK 8 11 MCIF_WB_P_VMID 16 19 MCIF_WB_BUF_ADDR_FENCE_EN 24 24 mmMCIF_WB0_MCIF_WB_BUFMGR_CUR_LINE_R 0 0x2b3 1 0 2 MCIF_WB_BUFMGR_CUR_LINE_R 0 12 mmMCIF_WB0_MCIF_WB_BUFMGR_STATUS 0 0x2b4 8 0 2 MCIF_WB_BUFMGR_VCE_INT_STATUS 0 0 MCIF_WB_BUFMGR_SW_INT_STATUS 1 1 MCIF_WB_BUFMGR_SW_OVERRUN_INT_STATUS 2 2 MCIF_WB_BUFMGR_CUR_BUF 4 6 MCIF_WB_BUF_DUALSIZE_STATUS 7 7 MCIF_WB_BUFMGR_BUFTAG 8 11 MCIF_WB_BUFMGR_CUR_LINE_L 12 24 MCIF_WB_BUFMGR_NEXT_BUF 28 30 mmMCIF_WB0_MCIF_WB_BUF_PITCH 0 0x2b5 2 0 2 MCIF_WB_BUF_LUMA_PITCH 8 15 MCIF_WB_BUF_CHROMA_PITCH 24 31 mmMCIF_WB0_MCIF_WB_BUF_1_STATUS 0 0x2b6 13 0 2 MCIF_WB_BUF_1_ACTIVE 0 0 MCIF_WB_BUF_1_SW_LOCKED 1 1 MCIF_WB_BUF_1_VCE_LOCKED 2 2 MCIF_WB_BUF_1_OVERFLOW 3 3 MCIF_WB_BUF_1_DISABLE 4 4 MCIF_WB_BUF_1_MODE 5 7 MCIF_WB_BUF_1_BUFTAG 8 11 MCIF_WB_BUF_1_NXT_BUF 12 14 MCIF_WB_BUF_1_FIELD 15 15 MCIF_WB_BUF_1_CUR_LINE_L 16 28 MCIF_WB_BUF_1_LONG_LINE_ERROR 29 29 MCIF_WB_BUF_1_SHORT_LINE_ERROR 30 30 MCIF_WB_BUF_1_FRAME_LENGTH_ERROR 31 31 mmMCIF_WB0_MCIF_WB_BUF_1_STATUS2 0 0x2b7 5 0 2 MCIF_WB_BUF_1_CUR_LINE_R 0 12 MCIF_WB_BUF_1_NEW_CONTENT 13 13 MCIF_WB_BUF_1_COLOR_DEPTH 14 14 MCIF_WB_BUF_1_Y_OVERRUN 17 17 MCIF_WB_BUF_1_C_OVERRUN 18 18 mmMCIF_WB0_MCIF_WB_BUF_2_STATUS 0 0x2b8 13 0 2 MCIF_WB_BUF_2_ACTIVE 0 0 MCIF_WB_BUF_2_SW_LOCKED 1 1 MCIF_WB_BUF_2_VCE_LOCKED 2 2 MCIF_WB_BUF_2_OVERFLOW 3 3 MCIF_WB_BUF_2_DISABLE 4 4 MCIF_WB_BUF_2_MODE 5 7 MCIF_WB_BUF_2_BUFTAG 8 11 MCIF_WB_BUF_2_NXT_BUF 12 14 MCIF_WB_BUF_2_FIELD 15 15 MCIF_WB_BUF_2_CUR_LINE_L 16 28 MCIF_WB_BUF_2_LONG_LINE_ERROR 29 29 MCIF_WB_BUF_2_SHORT_LINE_ERROR 30 30 MCIF_WB_BUF_2_FRAME_LENGTH_ERROR 31 31 mmMCIF_WB0_MCIF_WB_BUF_2_STATUS2 0 0x2b9 5 0 2 MCIF_WB_BUF_2_CUR_LINE_R 0 12 MCIF_WB_BUF_2_NEW_CONTENT 13 13 MCIF_WB_BUF_2_COLOR_DEPTH 14 14 MCIF_WB_BUF_2_Y_OVERRUN 17 17 MCIF_WB_BUF_2_C_OVERRUN 18 18 mmMCIF_WB0_MCIF_WB_BUF_3_STATUS 0 0x2ba 13 0 2 MCIF_WB_BUF_3_ACTIVE 0 0 MCIF_WB_BUF_3_SW_LOCKED 1 1 MCIF_WB_BUF_3_VCE_LOCKED 2 2 MCIF_WB_BUF_3_OVERFLOW 3 3 MCIF_WB_BUF_3_DISABLE 4 4 MCIF_WB_BUF_3_MODE 5 7 MCIF_WB_BUF_3_BUFTAG 8 11 MCIF_WB_BUF_3_NXT_BUF 12 14 MCIF_WB_BUF_3_FIELD 15 15 MCIF_WB_BUF_3_CUR_LINE_L 16 28 MCIF_WB_BUF_3_LONG_LINE_ERROR 29 29 MCIF_WB_BUF_3_SHORT_LINE_ERROR 30 30 MCIF_WB_BUF_3_FRAME_LENGTH_ERROR 31 31 mmMCIF_WB0_MCIF_WB_BUF_3_STATUS2 0 0x2bb 5 0 2 MCIF_WB_BUF_3_CUR_LINE_R 0 12 MCIF_WB_BUF_3_NEW_CONTENT 13 13 MCIF_WB_BUF_3_COLOR_DEPTH 14 14 MCIF_WB_BUF_3_Y_OVERRUN 17 17 MCIF_WB_BUF_3_C_OVERRUN 18 18 mmMCIF_WB0_MCIF_WB_BUF_4_STATUS 0 0x2bc 13 0 2 MCIF_WB_BUF_4_ACTIVE 0 0 MCIF_WB_BUF_4_SW_LOCKED 1 1 MCIF_WB_BUF_4_VCE_LOCKED 2 2 MCIF_WB_BUF_4_OVERFLOW 3 3 MCIF_WB_BUF_4_DISABLE 4 4 MCIF_WB_BUF_4_MODE 5 7 MCIF_WB_BUF_4_BUFTAG 8 11 MCIF_WB_BUF_4_NXT_BUF 12 14 MCIF_WB_BUF_4_FIELD 15 15 MCIF_WB_BUF_4_CUR_LINE_L 16 28 MCIF_WB_BUF_4_LONG_LINE_ERROR 29 29 MCIF_WB_BUF_4_SHORT_LINE_ERROR 30 30 MCIF_WB_BUF_4_FRAME_LENGTH_ERROR 31 31 mmMCIF_WB0_MCIF_WB_BUF_4_STATUS2 0 0x2bd 5 0 2 MCIF_WB_BUF_4_CUR_LINE_R 0 12 MCIF_WB_BUF_4_NEW_CONTENT 13 13 MCIF_WB_BUF_4_COLOR_DEPTH 14 14 MCIF_WB_BUF_4_Y_OVERRUN 17 17 MCIF_WB_BUF_4_C_OVERRUN 18 18 mmMCIF_WB0_MCIF_WB_ARBITRATION_CONTROL 0 0x2be 2 0 2 MCIF_WB_CLIENT_ARBITRATION_SLICE 0 1 MCIF_WB_TIME_PER_PIXEL 22 31 mmMCIF_WB0_MCIF_WB_SCLK_CHANGE 0 0x2bf 2 0 2 WM_CHANGE_ACK_FORCE_ON 0 0 MCIF_WB_CLI_WATERMARK_MASK 1 3 mmMCIF_WB0_MCIF_WB_BUF_1_ADDR_Y 0 0x2c2 1 0 2 MCIF_WB_BUF_1_ADDR_Y 0 31 mmMCIF_WB0_MCIF_WB_BUF_1_ADDR_Y_OFFSET 0 0x2c3 1 0 2 MCIF_WB_BUF_1_ADDR_Y_OFFSET 0 17 mmMCIF_WB0_MCIF_WB_BUF_1_ADDR_C 0 0x2c4 1 0 2 MCIF_WB_BUF_1_ADDR_C 0 31 mmMCIF_WB0_MCIF_WB_BUF_1_ADDR_C_OFFSET 0 0x2c5 1 0 2 MCIF_WB_BUF_1_ADDR_C_OFFSET 0 17 mmMCIF_WB0_MCIF_WB_BUF_2_ADDR_Y 0 0x2c6 1 0 2 MCIF_WB_BUF_2_ADDR_Y 0 31 mmMCIF_WB0_MCIF_WB_BUF_2_ADDR_Y_OFFSET 0 0x2c7 1 0 2 MCIF_WB_BUF_2_ADDR_Y_OFFSET 0 17 mmMCIF_WB0_MCIF_WB_BUF_2_ADDR_C 0 0x2c8 1 0 2 MCIF_WB_BUF_2_ADDR_C 0 31 mmMCIF_WB0_MCIF_WB_BUF_2_ADDR_C_OFFSET 0 0x2c9 1 0 2 MCIF_WB_BUF_2_ADDR_C_OFFSET 0 17 mmMCIF_WB0_MCIF_WB_BUF_3_ADDR_Y 0 0x2ca 1 0 2 MCIF_WB_BUF_3_ADDR_Y 0 31 mmMCIF_WB0_MCIF_WB_BUF_3_ADDR_Y_OFFSET 0 0x2cb 1 0 2 MCIF_WB_BUF_3_ADDR_Y_OFFSET 0 17 mmMCIF_WB0_MCIF_WB_BUF_3_ADDR_C 0 0x2cc 1 0 2 MCIF_WB_BUF_3_ADDR_C 0 31 mmMCIF_WB0_MCIF_WB_BUF_3_ADDR_C_OFFSET 0 0x2cd 1 0 2 MCIF_WB_BUF_3_ADDR_C_OFFSET 0 17 mmMCIF_WB0_MCIF_WB_BUF_4_ADDR_Y 0 0x2ce 1 0 2 MCIF_WB_BUF_4_ADDR_Y 0 31 mmMCIF_WB0_MCIF_WB_BUF_4_ADDR_Y_OFFSET 0 0x2cf 1 0 2 MCIF_WB_BUF_4_ADDR_Y_OFFSET 0 17 mmMCIF_WB0_MCIF_WB_BUF_4_ADDR_C 0 0x2d0 1 0 2 MCIF_WB_BUF_4_ADDR_C 0 31 mmMCIF_WB0_MCIF_WB_BUF_4_ADDR_C_OFFSET 0 0x2d1 1 0 2 MCIF_WB_BUF_4_ADDR_C_OFFSET 0 17 mmMCIF_WB0_MCIF_WB_BUFMGR_VCE_CONTROL 0 0x2d2 6 0 2 MCIF_WB_BUFMGR_VCE_LOCK_IGNORE 0 0 MCIF_WB_BUFMGR_VCE_INT_EN 4 4 MCIF_WB_BUFMGR_VCE_INT_ACK 5 5 MCIF_WB_BUFMGR_VCE_SLICE_INT_EN 6 6 MCIF_WB_BUFMGR_VCE_LOCK 8 11 MCIF_WB_BUFMGR_SLICE_SIZE 16 28 mmMCIF_WB0_MCIF_WB_NB_PSTATE_LATENCY_WATERMARK 0 0x2d3 1 0 2 NB_PSTATE_CHANGE_REFRESH_WATERMARK 0 16 mmMCIF_WB0_MCIF_WB_NB_PSTATE_CONTROL 0 0x2d4 4 0 2 NB_PSTATE_CHANGE_URGENT_DURING_REQUEST 0 0 NB_PSTATE_CHANGE_FORCE_ON 1 1 NB_PSTATE_ALLOW_FOR_URGENT 2 2 NB_PSTATE_CHANGE_WATERMARK_MASK 4 6 mmMCIF_WB0_MCIF_WB_WATERMARK 0 0x2d5 1 0 2 MCIF_WB_CLI_WATERMARK 0 15 mmMCIF_WB0_MCIF_WB_CLOCK_GATER_CONTROL 0 0x2d6 1 0 2 MCIF_WB_CLI_CLOCK_GATER_OVERRIDE 0 0 mmMCIF_WB0_MCIF_WB_WARM_UP_CNTL 0 0x2d7 1 0 2 MCIF_WB_PITCH_SIZE_WARMUP 8 15 mmMCIF_WB0_MCIF_WB_SELF_REFRESH_CONTROL 0 0x2d8 2 0 2 DIS_REFRESH_UNDER_NBPREQ 0 0 PERFRAME_SELF_REFRESH 1 1 mmMCIF_WB0_MULTI_LEVEL_QOS_CTRL 0 0x2d9 1 0 2 MAX_SCALED_TIME_TO_URGENT 0 21 mmMCIF_WB0_MCIF_WB_BUF_LUMA_SIZE 0 0x2db 1 0 2 MCIF_WB_BUF_LUMA_SIZE 0 19 mmMCIF_WB0_MCIF_WB_BUF_CHROMA_SIZE 0 0x2dc 1 0 2 MCIF_WB_BUF_CHROMA_SIZE 0 19 mmMCIF_WB1_MCIF_WB_BUFMGR_SW_CONTROL 0 0x2f2 9 0 2 MCIF_WB_BUFMGR_ENABLE 0 0 MCIF_WB_BUF_DUALSIZE_REQ 1 1 MCIF_WB_BUFMGR_SW_INT_EN 4 4 MCIF_WB_BUFMGR_SW_INT_ACK 5 5 MCIF_WB_BUFMGR_SW_SLICE_INT_EN 6 6 MCIF_WB_BUFMGR_SW_OVERRUN_INT_EN 7 7 MCIF_WB_BUFMGR_SW_LOCK 8 11 MCIF_WB_P_VMID 16 19 MCIF_WB_BUF_ADDR_FENCE_EN 24 24 mmMCIF_WB1_MCIF_WB_BUFMGR_CUR_LINE_R 0 0x2f3 1 0 2 MCIF_WB_BUFMGR_CUR_LINE_R 0 12 mmMCIF_WB1_MCIF_WB_BUFMGR_STATUS 0 0x2f4 8 0 2 MCIF_WB_BUFMGR_VCE_INT_STATUS 0 0 MCIF_WB_BUFMGR_SW_INT_STATUS 1 1 MCIF_WB_BUFMGR_SW_OVERRUN_INT_STATUS 2 2 MCIF_WB_BUFMGR_CUR_BUF 4 6 MCIF_WB_BUF_DUALSIZE_STATUS 7 7 MCIF_WB_BUFMGR_BUFTAG 8 11 MCIF_WB_BUFMGR_CUR_LINE_L 12 24 MCIF_WB_BUFMGR_NEXT_BUF 28 30 mmMCIF_WB1_MCIF_WB_BUF_PITCH 0 0x2f5 2 0 2 MCIF_WB_BUF_LUMA_PITCH 8 15 MCIF_WB_BUF_CHROMA_PITCH 24 31 mmMCIF_WB1_MCIF_WB_BUF_1_STATUS 0 0x2f6 13 0 2 MCIF_WB_BUF_1_ACTIVE 0 0 MCIF_WB_BUF_1_SW_LOCKED 1 1 MCIF_WB_BUF_1_VCE_LOCKED 2 2 MCIF_WB_BUF_1_OVERFLOW 3 3 MCIF_WB_BUF_1_DISABLE 4 4 MCIF_WB_BUF_1_MODE 5 7 MCIF_WB_BUF_1_BUFTAG 8 11 MCIF_WB_BUF_1_NXT_BUF 12 14 MCIF_WB_BUF_1_FIELD 15 15 MCIF_WB_BUF_1_CUR_LINE_L 16 28 MCIF_WB_BUF_1_LONG_LINE_ERROR 29 29 MCIF_WB_BUF_1_SHORT_LINE_ERROR 30 30 MCIF_WB_BUF_1_FRAME_LENGTH_ERROR 31 31 mmMCIF_WB1_MCIF_WB_BUF_1_STATUS2 0 0x2f7 5 0 2 MCIF_WB_BUF_1_CUR_LINE_R 0 12 MCIF_WB_BUF_1_NEW_CONTENT 13 13 MCIF_WB_BUF_1_COLOR_DEPTH 14 14 MCIF_WB_BUF_1_Y_OVERRUN 17 17 MCIF_WB_BUF_1_C_OVERRUN 18 18 mmMCIF_WB1_MCIF_WB_BUF_2_STATUS 0 0x2f8 13 0 2 MCIF_WB_BUF_2_ACTIVE 0 0 MCIF_WB_BUF_2_SW_LOCKED 1 1 MCIF_WB_BUF_2_VCE_LOCKED 2 2 MCIF_WB_BUF_2_OVERFLOW 3 3 MCIF_WB_BUF_2_DISABLE 4 4 MCIF_WB_BUF_2_MODE 5 7 MCIF_WB_BUF_2_BUFTAG 8 11 MCIF_WB_BUF_2_NXT_BUF 12 14 MCIF_WB_BUF_2_FIELD 15 15 MCIF_WB_BUF_2_CUR_LINE_L 16 28 MCIF_WB_BUF_2_LONG_LINE_ERROR 29 29 MCIF_WB_BUF_2_SHORT_LINE_ERROR 30 30 MCIF_WB_BUF_2_FRAME_LENGTH_ERROR 31 31 mmMCIF_WB1_MCIF_WB_BUF_2_STATUS2 0 0x2f9 5 0 2 MCIF_WB_BUF_2_CUR_LINE_R 0 12 MCIF_WB_BUF_2_NEW_CONTENT 13 13 MCIF_WB_BUF_2_COLOR_DEPTH 14 14 MCIF_WB_BUF_2_Y_OVERRUN 17 17 MCIF_WB_BUF_2_C_OVERRUN 18 18 mmMCIF_WB1_MCIF_WB_BUF_3_STATUS 0 0x2fa 13 0 2 MCIF_WB_BUF_3_ACTIVE 0 0 MCIF_WB_BUF_3_SW_LOCKED 1 1 MCIF_WB_BUF_3_VCE_LOCKED 2 2 MCIF_WB_BUF_3_OVERFLOW 3 3 MCIF_WB_BUF_3_DISABLE 4 4 MCIF_WB_BUF_3_MODE 5 7 MCIF_WB_BUF_3_BUFTAG 8 11 MCIF_WB_BUF_3_NXT_BUF 12 14 MCIF_WB_BUF_3_FIELD 15 15 MCIF_WB_BUF_3_CUR_LINE_L 16 28 MCIF_WB_BUF_3_LONG_LINE_ERROR 29 29 MCIF_WB_BUF_3_SHORT_LINE_ERROR 30 30 MCIF_WB_BUF_3_FRAME_LENGTH_ERROR 31 31 mmMCIF_WB1_MCIF_WB_BUF_3_STATUS2 0 0x2fb 5 0 2 MCIF_WB_BUF_3_CUR_LINE_R 0 12 MCIF_WB_BUF_3_NEW_CONTENT 13 13 MCIF_WB_BUF_3_COLOR_DEPTH 14 14 MCIF_WB_BUF_3_Y_OVERRUN 17 17 MCIF_WB_BUF_3_C_OVERRUN 18 18 mmMCIF_WB1_MCIF_WB_BUF_4_STATUS 0 0x2fc 13 0 2 MCIF_WB_BUF_4_ACTIVE 0 0 MCIF_WB_BUF_4_SW_LOCKED 1 1 MCIF_WB_BUF_4_VCE_LOCKED 2 2 MCIF_WB_BUF_4_OVERFLOW 3 3 MCIF_WB_BUF_4_DISABLE 4 4 MCIF_WB_BUF_4_MODE 5 7 MCIF_WB_BUF_4_BUFTAG 8 11 MCIF_WB_BUF_4_NXT_BUF 12 14 MCIF_WB_BUF_4_FIELD 15 15 MCIF_WB_BUF_4_CUR_LINE_L 16 28 MCIF_WB_BUF_4_LONG_LINE_ERROR 29 29 MCIF_WB_BUF_4_SHORT_LINE_ERROR 30 30 MCIF_WB_BUF_4_FRAME_LENGTH_ERROR 31 31 mmMCIF_WB1_MCIF_WB_BUF_4_STATUS2 0 0x2fd 5 0 2 MCIF_WB_BUF_4_CUR_LINE_R 0 12 MCIF_WB_BUF_4_NEW_CONTENT 13 13 MCIF_WB_BUF_4_COLOR_DEPTH 14 14 MCIF_WB_BUF_4_Y_OVERRUN 17 17 MCIF_WB_BUF_4_C_OVERRUN 18 18 mmMCIF_WB1_MCIF_WB_ARBITRATION_CONTROL 0 0x2fe 2 0 2 MCIF_WB_CLIENT_ARBITRATION_SLICE 0 1 MCIF_WB_TIME_PER_PIXEL 22 31 mmMCIF_WB1_MCIF_WB_SCLK_CHANGE 0 0x2ff 2 0 2 WM_CHANGE_ACK_FORCE_ON 0 0 MCIF_WB_CLI_WATERMARK_MASK 1 3 mmMCIF_WB1_MCIF_WB_BUF_1_ADDR_Y 0 0x302 1 0 2 MCIF_WB_BUF_1_ADDR_Y 0 31 mmMCIF_WB1_MCIF_WB_BUF_1_ADDR_Y_OFFSET 0 0x303 1 0 2 MCIF_WB_BUF_1_ADDR_Y_OFFSET 0 17 mmMCIF_WB1_MCIF_WB_BUF_1_ADDR_C 0 0x304 1 0 2 MCIF_WB_BUF_1_ADDR_C 0 31 mmMCIF_WB1_MCIF_WB_BUF_1_ADDR_C_OFFSET 0 0x305 1 0 2 MCIF_WB_BUF_1_ADDR_C_OFFSET 0 17 mmMCIF_WB1_MCIF_WB_BUF_2_ADDR_Y 0 0x306 1 0 2 MCIF_WB_BUF_2_ADDR_Y 0 31 mmMCIF_WB1_MCIF_WB_BUF_2_ADDR_Y_OFFSET 0 0x307 1 0 2 MCIF_WB_BUF_2_ADDR_Y_OFFSET 0 17 mmMCIF_WB1_MCIF_WB_BUF_2_ADDR_C 0 0x308 1 0 2 MCIF_WB_BUF_2_ADDR_C 0 31 mmMCIF_WB1_MCIF_WB_BUF_2_ADDR_C_OFFSET 0 0x309 1 0 2 MCIF_WB_BUF_2_ADDR_C_OFFSET 0 17 mmMCIF_WB1_MCIF_WB_BUF_3_ADDR_Y 0 0x30a 1 0 2 MCIF_WB_BUF_3_ADDR_Y 0 31 mmMCIF_WB1_MCIF_WB_BUF_3_ADDR_Y_OFFSET 0 0x30b 1 0 2 MCIF_WB_BUF_3_ADDR_Y_OFFSET 0 17 mmMCIF_WB1_MCIF_WB_BUF_3_ADDR_C 0 0x30c 1 0 2 MCIF_WB_BUF_3_ADDR_C 0 31 mmMCIF_WB1_MCIF_WB_BUF_3_ADDR_C_OFFSET 0 0x30d 1 0 2 MCIF_WB_BUF_3_ADDR_C_OFFSET 0 17 mmMCIF_WB1_MCIF_WB_BUF_4_ADDR_Y 0 0x30e 1 0 2 MCIF_WB_BUF_4_ADDR_Y 0 31 mmMCIF_WB1_MCIF_WB_BUF_4_ADDR_Y_OFFSET 0 0x30f 1 0 2 MCIF_WB_BUF_4_ADDR_Y_OFFSET 0 17 mmMCIF_WB1_MCIF_WB_BUF_4_ADDR_C 0 0x310 1 0 2 MCIF_WB_BUF_4_ADDR_C 0 31 mmMCIF_WB1_MCIF_WB_BUF_4_ADDR_C_OFFSET 0 0x311 1 0 2 MCIF_WB_BUF_4_ADDR_C_OFFSET 0 17 mmMCIF_WB1_MCIF_WB_BUFMGR_VCE_CONTROL 0 0x312 6 0 2 MCIF_WB_BUFMGR_VCE_LOCK_IGNORE 0 0 MCIF_WB_BUFMGR_VCE_INT_EN 4 4 MCIF_WB_BUFMGR_VCE_INT_ACK 5 5 MCIF_WB_BUFMGR_VCE_SLICE_INT_EN 6 6 MCIF_WB_BUFMGR_VCE_LOCK 8 11 MCIF_WB_BUFMGR_SLICE_SIZE 16 28 mmMCIF_WB1_MCIF_WB_NB_PSTATE_LATENCY_WATERMARK 0 0x313 1 0 2 NB_PSTATE_CHANGE_REFRESH_WATERMARK 0 16 mmMCIF_WB1_MCIF_WB_NB_PSTATE_CONTROL 0 0x314 4 0 2 NB_PSTATE_CHANGE_URGENT_DURING_REQUEST 0 0 NB_PSTATE_CHANGE_FORCE_ON 1 1 NB_PSTATE_ALLOW_FOR_URGENT 2 2 NB_PSTATE_CHANGE_WATERMARK_MASK 4 6 mmMCIF_WB1_MCIF_WB_WATERMARK 0 0x315 1 0 2 MCIF_WB_CLI_WATERMARK 0 15 mmMCIF_WB1_MCIF_WB_CLOCK_GATER_CONTROL 0 0x316 1 0 2 MCIF_WB_CLI_CLOCK_GATER_OVERRIDE 0 0 mmMCIF_WB1_MCIF_WB_WARM_UP_CNTL 0 0x317 1 0 2 MCIF_WB_PITCH_SIZE_WARMUP 8 15 mmMCIF_WB1_MCIF_WB_SELF_REFRESH_CONTROL 0 0x318 2 0 2 DIS_REFRESH_UNDER_NBPREQ 0 0 PERFRAME_SELF_REFRESH 1 1 mmMCIF_WB1_MULTI_LEVEL_QOS_CTRL 0 0x319 1 0 2 MAX_SCALED_TIME_TO_URGENT 0 21 mmMCIF_WB1_MCIF_WB_BUF_LUMA_SIZE 0 0x31b 1 0 2 MCIF_WB_BUF_LUMA_SIZE 0 19 mmMCIF_WB1_MCIF_WB_BUF_CHROMA_SIZE 0 0x31c 1 0 2 MCIF_WB_BUF_CHROMA_SIZE 0 19 mmWBIF0_MISC_CTRL 0 0x333 2 0 2 MCIFWB0_WR_COMBINE_TIMEOUT_THRESH 0 9 MCIF_WB0_SOCCLK_DS_ENABLE 16 16 mmWBIF0_SMU_WM_CONTROL 0 0x334 4 0 2 MCIF_WB0_WM_CHG_SEL 20 21 MCIF_WB0_WM_CHG_REQ 22 22 MCIF_WB0_WM_CHG_ACK_INT_DIS 24 24 MCIF_WB0_WM_CHG_ACK_INT_STATUS 25 25 mmWBIF0_PHASE0_OUTSTANDING_COUNTER 0 0x335 1 0 2 MCIF_WB0_PHASE0_OUTSTANDING_COUNTER 0 26 mmWBIF0_PHASE1_OUTSTANDING_COUNTER 0 0x336 1 0 2 MCIF_WB0_PHASE1_OUTSTANDING_COUNTER 0 26 mmWBIF1_MISC_CTRL 0 0x337 2 0 2 MCIFWB1_WR_COMBINE_TIMEOUT_THRESH 0 9 MCIF_WB1_SOCCLK_DS_ENABLE 16 16 mmWBIF1_SMU_WM_CONTROL 0 0x338 4 0 2 MCIF_WB1_WM_CHG_SEL 20 21 MCIF_WB1_WM_CHG_REQ 22 22 MCIF_WB1_WM_CHG_ACK_INT_DIS 24 24 MCIF_WB1_WM_CHG_ACK_INT_STATUS 25 25 mmWBIF1_PHASE0_OUTSTANDING_COUNTER 0 0x339 1 0 2 MCIF_WB1_PHASE0_OUTSTANDING_COUNTER 0 26 mmWBIF1_PHASE1_OUTSTANDING_COUNTER 0 0x33a 1 0 2 MCIF_WB1_PHASE1_OUTSTANDING_COUNTER 0 26 mmVGA_SRC_SPLIT_CNTL 0 0x33b 1 0 2 VGA_SPLIT_SEL 0 1 mmMMHUBBUB_MEM_PWR_STATUS 0 0x33c 9 0 2 MCIF_DWB0_LUMA_MEM0_PWR_STATE 0 1 MCIF_DWB0_LUMA_MEM1_PWR_STATE 2 3 MCIF_DWB0_CHROMA_MEM0_PWR_STATE 4 5 MCIF_DWB0_CHROMA_MEM1_PWR_STATE 6 7 MCIF_DWB1_LUMA_MEM0_PWR_STATE 8 9 MCIF_DWB1_LUMA_MEM1_PWR_STATE 10 11 MCIF_DWB1_CHROMA_MEM0_PWR_STATE 12 13 MCIF_DWB1_CHROMA_MEM1_PWR_STATE 14 15 VGA_MEM_PWR_STATE 31 31 mmMMHUBBUB_MEM_PWR_CNTL 0 0x33d 12 0 2 VGA_MEM_PWR_FORCE 0 0 VGA_MEM_PWR_DIS 1 1 MCIF_DWB0_MEM_PWR_FORCE 2 3 MCIF_DWB0_MEM_PWR_DIS 4 4 MCIF_DWB0_MEM_PWR_MODE_SEL 5 6 MCIF_DWB0_LUMA_MEM_EN_NUM 7 7 MCIF_DWB0_CHROMA_MEM_EN_NUM 8 8 MCIF_DWB1_MEM_PWR_FORCE 9 10 MCIF_DWB1_MEM_PWR_DIS 11 11 MCIF_DWB1_MEM_PWR_MODE_SEL 12 13 MCIF_DWB1_LUMA_MEM_EN_NUM 14 14 MCIF_DWB1_CHROMA_MEM_EN_NUM 15 15 mmMMHUBBUB_CLOCK_CNTL 0 0x33e 9 0 2 MMHUBBUB_TEST_CLK_SEL 0 4 DISPCLK_R_MMHUBBUB_GATE_DIS 5 5 DISPCLK_G_VGAIF_GATE_DIS 6 6 SOCCLK_G_VGAIF_GATE_DIS 7 7 DISPCLK_G_VGA_GATE_DIS 8 8 DISPCLK_G_WBIF0_GATE_DIS 9 9 SOCCLK_G_WBIF0_GATE_DIS 10 10 DISPCLK_G_WBIF1_GATE_DIS 11 11 SOCCLK_G_WBIF1_GATE_DIS 12 12 mmMMHUBBUB_SOFT_RESET 0 0x33f 4 0 2 VGA_SOFT_RESET 0 0 VGAIF_SOFT_RESET 1 1 WBIF0_SOFT_RESET 2 2 WBIF1_SOFT_RESET 3 3 mmMCIF_CONTROL 0 0x34a 2 0 2 MCIF_MC_LATENCY_COUNTER_ENABLE 30 30 MCIF_MC_LATENCY_COUNTER_URGENT_ONLY 31 31 mmMCIF_WRITE_COMBINE_CONTROL 0 0x34b 1 0 2 MCIF_WRITE_COMBINE_TIMEOUT 0 9 mmMCIF_PHASE0_OUTSTANDING_COUNTER 0 0x34e 1 0 2 MCIF_PHASE0_OUTSTANDING_COUNTER 0 26 mmMCIF_PHASE1_OUTSTANDING_COUNTER 0 0x34f 1 0 2 MCIF_PHASE1_OUTSTANDING_COUNTER 0 26 mmMCIF_PHASE2_OUTSTANDING_COUNTER 0 0x350 1 0 2 MCIF_PHASE2_OUTSTANDING_COUNTER 0 26 mmDC_PERFMON5_PERFCOUNTER_CNTL 0 0x352 11 0 2 PERFCOUNTER_EVENT_SEL 0 8 PERFCOUNTER_CVALUE_SEL 9 11 PERFCOUNTER_INC_MODE 12 14 PERFCOUNTER_HW_CNTL_SEL 15 15 PERFCOUNTER_RUNEN_MODE 16 16 PERFCOUNTER_CNTOFF_START_DIS 22 22 PERFCOUNTER_RESTART_EN 23 23 PERFCOUNTER_INT_EN 24 24 PERFCOUNTER_OFF_MASK 25 25 PERFCOUNTER_ACTIVE 26 26 PERFCOUNTER_CNTL_SEL 29 31 mmDC_PERFMON5_PERFCOUNTER_CNTL2 0 0x353 5 0 2 PERFCOUNTER_COUNTED_VALUE_TYPE 0 1 PERFCOUNTER_HW_STOP1_SEL 2 2 PERFCOUNTER_HW_STOP2_SEL 3 3 PERFCOUNTER_CNTOFF_SEL 8 13 PERFCOUNTER_CNTL2_SEL 29 31 mmDC_PERFMON5_PERFCOUNTER_STATE 0 0x354 16 0 2 PERFCOUNTER_CNT0_STATE 0 1 PERFCOUNTER_STATE_SEL0 2 2 PERFCOUNTER_CNT1_STATE 4 5 PERFCOUNTER_STATE_SEL1 6 6 PERFCOUNTER_CNT2_STATE 8 9 PERFCOUNTER_STATE_SEL2 10 10 PERFCOUNTER_CNT3_STATE 12 13 PERFCOUNTER_STATE_SEL3 14 14 PERFCOUNTER_CNT4_STATE 16 17 PERFCOUNTER_STATE_SEL4 18 18 PERFCOUNTER_CNT5_STATE 20 21 PERFCOUNTER_STATE_SEL5 22 22 PERFCOUNTER_CNT6_STATE 24 25 PERFCOUNTER_STATE_SEL6 26 26 PERFCOUNTER_CNT7_STATE 28 29 PERFCOUNTER_STATE_SEL7 30 30 mmDC_PERFMON5_PERFMON_CNTL 0 0x355 6 0 2 PERFMON_STATE 0 1 PERFMON_RPT_COUNT 8 27 PERFMON_CNTOFF_AND_OR 28 28 PERFMON_CNTOFF_INT_EN 29 29 PERFMON_CNTOFF_INT_STATUS 30 30 PERFMON_CNTOFF_INT_ACK 31 31 mmDC_PERFMON5_PERFMON_CNTL2 0 0x356 4 0 2 PERFMON_CNTOFF_INT_TYPE 0 0 PERFMON_CLK_ENABLE 1 1 PERFMON_RUN_ENABLE_START_SEL 2 9 PERFMON_RUN_ENABLE_STOP_SEL 10 17 mmDC_PERFMON5_PERFMON_CVALUE_INT_MISC 0 0x357 17 0 2 PERFCOUNTER_INT0_STATUS 0 0 PERFCOUNTER_INT1_STATUS 1 1 PERFCOUNTER_INT2_STATUS 2 2 PERFCOUNTER_INT3_STATUS 3 3 PERFCOUNTER_INT4_STATUS 4 4 PERFCOUNTER_INT5_STATUS 5 5 PERFCOUNTER_INT6_STATUS 6 6 PERFCOUNTER_INT7_STATUS 7 7 PERFCOUNTER_INT0_ACK 8 8 PERFCOUNTER_INT1_ACK 9 9 PERFCOUNTER_INT2_ACK 10 10 PERFCOUNTER_INT3_ACK 11 11 PERFCOUNTER_INT4_ACK 12 12 PERFCOUNTER_INT5_ACK 13 13 PERFCOUNTER_INT6_ACK 14 14 PERFCOUNTER_INT7_ACK 15 15 PERFMON_CVALUE_HI 16 31 mmDC_PERFMON5_PERFMON_CVALUE_LOW 0 0x358 1 0 2 PERFMON_CVALUE_LOW 0 31 mmDC_PERFMON5_PERFMON_HI 0 0x359 2 0 2 PERFMON_HI 0 15 PERFMON_READ_SEL 29 31 mmDC_PERFMON5_PERFMON_LOW 0 0x35a 1 0 2 PERFMON_LOW 0 31 mmAZF0STREAM0_AZALIA_STREAM_INDEX 0 0x35e 2 0 2 AZALIA_STREAM_REG_INDEX 0 7 AZALIA_STREAM_REG_WRITE_EN 8 8 mmAZF0STREAM0_AZALIA_STREAM_DATA 0 0x35f 1 0 2 AZALIA_STREAM_REG_DATA 0 31 mmAZF0STREAM1_AZALIA_STREAM_INDEX 0 0x360 2 0 2 AZALIA_STREAM_REG_INDEX 0 7 AZALIA_STREAM_REG_WRITE_EN 8 8 mmAZF0STREAM1_AZALIA_STREAM_DATA 0 0x361 1 0 2 AZALIA_STREAM_REG_DATA 0 31 mmAZF0STREAM2_AZALIA_STREAM_INDEX 0 0x362 2 0 2 AZALIA_STREAM_REG_INDEX 0 7 AZALIA_STREAM_REG_WRITE_EN 8 8 mmAZF0STREAM2_AZALIA_STREAM_DATA 0 0x363 1 0 2 AZALIA_STREAM_REG_DATA 0 31 mmAZF0STREAM3_AZALIA_STREAM_INDEX 0 0x364 2 0 2 AZALIA_STREAM_REG_INDEX 0 7 AZALIA_STREAM_REG_WRITE_EN 8 8 mmAZF0STREAM3_AZALIA_STREAM_DATA 0 0x365 1 0 2 AZALIA_STREAM_REG_DATA 0 31 mmAZF0STREAM4_AZALIA_STREAM_INDEX 0 0x366 2 0 2 AZALIA_STREAM_REG_INDEX 0 7 AZALIA_STREAM_REG_WRITE_EN 8 8 mmAZF0STREAM4_AZALIA_STREAM_DATA 0 0x367 1 0 2 AZALIA_STREAM_REG_DATA 0 31 mmAZF0STREAM5_AZALIA_STREAM_INDEX 0 0x368 2 0 2 AZALIA_STREAM_REG_INDEX 0 7 AZALIA_STREAM_REG_WRITE_EN 8 8 mmAZF0STREAM5_AZALIA_STREAM_DATA 0 0x369 1 0 2 AZALIA_STREAM_REG_DATA 0 31 mmAZF0STREAM6_AZALIA_STREAM_INDEX 0 0x36a 2 0 2 AZALIA_STREAM_REG_INDEX 0 7 AZALIA_STREAM_REG_WRITE_EN 8 8 mmAZF0STREAM6_AZALIA_STREAM_DATA 0 0x36b 1 0 2 AZALIA_STREAM_REG_DATA 0 31 mmAZF0STREAM7_AZALIA_STREAM_INDEX 0 0x36c 2 0 2 AZALIA_STREAM_REG_INDEX 0 7 AZALIA_STREAM_REG_WRITE_EN 8 8 mmAZF0STREAM7_AZALIA_STREAM_DATA 0 0x36d 1 0 2 AZALIA_STREAM_REG_DATA 0 31 mmAZ_CLOCK_CNTL 0 0x372 4 0 2 SCLK_G_STREAM_AZ_GATE_DIS 0 0 SCLK_R_AZ_GATE_DIS 8 8 SCLK_G_CNTL_AZ_GATE_DIS 16 16 DCIPG_TEST_CLK_SEL 24 28 mmDC_PERFMON6_PERFCOUNTER_CNTL 0 0x37a 11 0 2 PERFCOUNTER_EVENT_SEL 0 8 PERFCOUNTER_CVALUE_SEL 9 11 PERFCOUNTER_INC_MODE 12 14 PERFCOUNTER_HW_CNTL_SEL 15 15 PERFCOUNTER_RUNEN_MODE 16 16 PERFCOUNTER_CNTOFF_START_DIS 22 22 PERFCOUNTER_RESTART_EN 23 23 PERFCOUNTER_INT_EN 24 24 PERFCOUNTER_OFF_MASK 25 25 PERFCOUNTER_ACTIVE 26 26 PERFCOUNTER_CNTL_SEL 29 31 mmDC_PERFMON6_PERFCOUNTER_CNTL2 0 0x37b 5 0 2 PERFCOUNTER_COUNTED_VALUE_TYPE 0 1 PERFCOUNTER_HW_STOP1_SEL 2 2 PERFCOUNTER_HW_STOP2_SEL 3 3 PERFCOUNTER_CNTOFF_SEL 8 13 PERFCOUNTER_CNTL2_SEL 29 31 mmDC_PERFMON6_PERFCOUNTER_STATE 0 0x37c 16 0 2 PERFCOUNTER_CNT0_STATE 0 1 PERFCOUNTER_STATE_SEL0 2 2 PERFCOUNTER_CNT1_STATE 4 5 PERFCOUNTER_STATE_SEL1 6 6 PERFCOUNTER_CNT2_STATE 8 9 PERFCOUNTER_STATE_SEL2 10 10 PERFCOUNTER_CNT3_STATE 12 13 PERFCOUNTER_STATE_SEL3 14 14 PERFCOUNTER_CNT4_STATE 16 17 PERFCOUNTER_STATE_SEL4 18 18 PERFCOUNTER_CNT5_STATE 20 21 PERFCOUNTER_STATE_SEL5 22 22 PERFCOUNTER_CNT6_STATE 24 25 PERFCOUNTER_STATE_SEL6 26 26 PERFCOUNTER_CNT7_STATE 28 29 PERFCOUNTER_STATE_SEL7 30 30 mmDC_PERFMON6_PERFMON_CNTL 0 0x37d 6 0 2 PERFMON_STATE 0 1 PERFMON_RPT_COUNT 8 27 PERFMON_CNTOFF_AND_OR 28 28 PERFMON_CNTOFF_INT_EN 29 29 PERFMON_CNTOFF_INT_STATUS 30 30 PERFMON_CNTOFF_INT_ACK 31 31 mmDC_PERFMON6_PERFMON_CNTL2 0 0x37e 4 0 2 PERFMON_CNTOFF_INT_TYPE 0 0 PERFMON_CLK_ENABLE 1 1 PERFMON_RUN_ENABLE_START_SEL 2 9 PERFMON_RUN_ENABLE_STOP_SEL 10 17 mmDC_PERFMON6_PERFMON_CVALUE_INT_MISC 0 0x37f 17 0 2 PERFCOUNTER_INT0_STATUS 0 0 PERFCOUNTER_INT1_STATUS 1 1 PERFCOUNTER_INT2_STATUS 2 2 PERFCOUNTER_INT3_STATUS 3 3 PERFCOUNTER_INT4_STATUS 4 4 PERFCOUNTER_INT5_STATUS 5 5 PERFCOUNTER_INT6_STATUS 6 6 PERFCOUNTER_INT7_STATUS 7 7 PERFCOUNTER_INT0_ACK 8 8 PERFCOUNTER_INT1_ACK 9 9 PERFCOUNTER_INT2_ACK 10 10 PERFCOUNTER_INT3_ACK 11 11 PERFCOUNTER_INT4_ACK 12 12 PERFCOUNTER_INT5_ACK 13 13 PERFCOUNTER_INT6_ACK 14 14 PERFCOUNTER_INT7_ACK 15 15 PERFMON_CVALUE_HI 16 31 mmDC_PERFMON6_PERFMON_CVALUE_LOW 0 0x380 1 0 2 PERFMON_CVALUE_LOW 0 31 mmDC_PERFMON6_PERFMON_HI 0 0x381 2 0 2 PERFMON_HI 0 15 PERFMON_READ_SEL 29 31 mmDC_PERFMON6_PERFMON_LOW 0 0x382 1 0 2 PERFMON_LOW 0 31 mmAZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX 0 0x386 1 0 2 AZALIA_ENDPOINT_REG_INDEX 0 13 mmAZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA 0 0x387 1 0 2 AZALIA_ENDPOINT_REG_DATA 0 31 mmAZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_INDEX 0 0x38c 1 0 2 AZALIA_ENDPOINT_REG_INDEX 0 13 mmAZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_DATA 0 0x38d 1 0 2 AZALIA_ENDPOINT_REG_DATA 0 31 mmAZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_INDEX 0 0x392 1 0 2 AZALIA_ENDPOINT_REG_INDEX 0 13 mmAZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_DATA 0 0x393 1 0 2 AZALIA_ENDPOINT_REG_DATA 0 31 mmAZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_INDEX 0 0x398 1 0 2 AZALIA_ENDPOINT_REG_INDEX 0 13 mmAZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_DATA 0 0x399 1 0 2 AZALIA_ENDPOINT_REG_DATA 0 31 mmAZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_INDEX 0 0x39e 1 0 2 AZALIA_ENDPOINT_REG_INDEX 0 13 mmAZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_DATA 0 0x39f 1 0 2 AZALIA_ENDPOINT_REG_DATA 0 31 mmAZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_INDEX 0 0x3a4 1 0 2 AZALIA_ENDPOINT_REG_INDEX 0 13 mmAZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_DATA 0 0x3a5 1 0 2 AZALIA_ENDPOINT_REG_DATA 0 31 mmAZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_INDEX 0 0x3aa 1 0 2 AZALIA_ENDPOINT_REG_INDEX 0 13 mmAZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_DATA 0 0x3ab 1 0 2 AZALIA_ENDPOINT_REG_DATA 0 31 mmAZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_INDEX 0 0x3b0 1 0 2 AZALIA_ENDPOINT_REG_INDEX 0 13 mmAZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_DATA 0 0x3b1 1 0 2 AZALIA_ENDPOINT_REG_DATA 0 31 mmAZALIA_CONTROLLER_CLOCK_GATING 0 0x3c2 2 0 2 ENABLE_CLOCK_GATING 0 0 CLOCK_ON_STATE 4 4 mmAZALIA_AUDIO_DTO 0 0x3c3 2 0 2 AZALIA_AUDIO_DTO_PHASE 0 15 AZALIA_AUDIO_DTO_MODULE 16 31 mmAZALIA_AUDIO_DTO_CONTROL 0 0x3c4 1 0 2 AZALIA_AUDIO_FORCE_DTO 8 9 mmAZALIA_SOCCLK_CONTROL 0 0x3c5 1 0 2 AUDIO_STREAM_SOCCLK_DEEP_SLEEP_EXIT_EN 1 1 mmAZALIA_UNDERFLOW_FILLER_SAMPLE 0 0x3c6 1 0 2 AZALIA_UNDERFLOW_FILLER_SAMPLE 0 31 mmAZALIA_DATA_DMA_CONTROL 0 0x3c7 6 0 2 DATA_DMA_NON_SNOOP 0 1 INPUT_DATA_DMA_NON_SNOOP 2 3 DATA_DMA_ISOCHRONOUS 4 5 INPUT_DATA_DMA_ISOCHRONOUS 6 7 AZALIA_IOC_GENERATION_METHOD 16 16 AZALIA_UNDERFLOW_CONTROL 17 17 mmAZALIA_BDL_DMA_CONTROL 0 0x3c8 4 0 2 BDL_DMA_NON_SNOOP 0 1 INPUT_BDL_DMA_NON_SNOOP 2 3 BDL_DMA_ISOCHRONOUS 4 5 INPUT_BDL_DMA_ISOCHRONOUS 6 7 mmAZALIA_RIRB_AND_DP_CONTROL 0 0x3c9 3 0 2 RIRB_NON_SNOOP 0 0 DP_DMA_NON_SNOOP 4 4 DP_UPDATE_FREQ_DIVIDER 5 8 mmAZALIA_CORB_DMA_CONTROL 0 0x3ca 2 0 2 CORB_DMA_NON_SNOOP 0 0 CORB_DMA_ISOCHRONOUS 4 4 mmAZALIA_APPLICATION_POSITION_IN_CYCLIC_BUFFER 0 0x3d1 1 0 2 APPLICATION_POSITION_IN_CYCLIC_BUFFER 0 31 mmAZALIA_CYCLIC_BUFFER_SYNC 0 0x3d2 1 0 2 CYCLIC_BUFFER_SYNC_ENABLE 0 0 mmAZALIA_GLOBAL_CAPABILITIES 0 0x3d3 1 0 2 NUMBER_OF_SERIAL_DATA_OUTPUT_SIGNALS 1 2 mmAZALIA_OUTPUT_PAYLOAD_CAPABILITY 0 0x3d4 2 0 2 OUTPUT_PAYLOAD_CAPABILITY 0 15 OUTSTRMPAY 16 31 mmAZALIA_OUTPUT_STREAM_ARBITER_CONTROL 0 0x3d5 3 0 2 LATENCY_HIDING_LEVEL 0 7 SYS_MEM_ACTIVE_ENABLE 8 8 INPUT_LATENCY_HIDING_LEVEL 16 23 mmAZALIA_INPUT_PAYLOAD_CAPABILITY 0 0x3d6 2 0 2 INPUT_PAYLOAD_CAPABILITY 0 15 INSTRMPAY 16 31 mmAZALIA_INPUT_CRC0_CONTROL0 0 0x3d9 3 0 2 INPUT_CRC_EN 0 0 INPUT_CRC_BLOCK_MODE 4 4 INPUT_CRC_INSTANCE_SEL 8 10 mmAZALIA_INPUT_CRC0_CONTROL1 0 0x3da 1 0 2 INPUT_CRC_BLOCK_SIZE 0 31 mmAZALIA_INPUT_CRC0_CONTROL2 0 0x3db 1 0 2 INPUT_CRC_BLOCK_ITERATION 0 15 mmAZALIA_INPUT_CRC0_CONTROL3 0 0x3dc 3 0 2 INPUT_CRC_COMPLETE 0 0 INPUT_CRC_BLOCK_COMPLETE_PHASE 4 4 INPUT_CRC_CHANNEL_RESULT_SEL 8 10 mmAZALIA_INPUT_CRC0_RESULT 0 0x3dd 1 0 2 INPUT_CRC_RESULT 0 31 mmAZALIA_INPUT_CRC1_CONTROL0 0 0x3de 3 0 2 INPUT_CRC_EN 0 0 INPUT_CRC_BLOCK_MODE 4 4 INPUT_CRC_INSTANCE_SEL 8 10 mmAZALIA_INPUT_CRC1_CONTROL1 0 0x3df 1 0 2 INPUT_CRC_BLOCK_SIZE 0 31 mmAZALIA_INPUT_CRC1_CONTROL2 0 0x3e0 1 0 2 INPUT_CRC_BLOCK_ITERATION 0 15 mmAZALIA_INPUT_CRC1_CONTROL3 0 0x3e1 3 0 2 INPUT_CRC_COMPLETE 0 0 INPUT_CRC_BLOCK_COMPLETE_PHASE 4 4 INPUT_CRC_CHANNEL_RESULT_SEL 8 10 mmAZALIA_INPUT_CRC1_RESULT 0 0x3e2 1 0 2 INPUT_CRC_RESULT 0 31 mmAZALIA_CRC0_CONTROL0 0 0x3e3 4 0 2 CRC_EN 0 0 CRC_BLOCK_MODE 4 4 CRC_INSTANCE_SEL 8 10 CRC_SOURCE_SEL 12 12 mmAZALIA_CRC0_CONTROL1 0 0x3e4 1 0 2 CRC_BLOCK_SIZE 0 31 mmAZALIA_CRC0_CONTROL2 0 0x3e5 1 0 2 CRC_BLOCK_ITERATION 0 15 mmAZALIA_CRC0_CONTROL3 0 0x3e6 3 0 2 CRC_COMPLETE 0 0 CRC_BLOCK_COMPLETE_PHASE 4 4 CRC_CHANNEL_RESULT_SEL 8 10 mmAZALIA_CRC0_RESULT 0 0x3e7 1 0 2 CRC_RESULT 0 31 mmAZALIA_CRC1_CONTROL0 0 0x3e8 4 0 2 CRC_EN 0 0 CRC_BLOCK_MODE 4 4 CRC_INSTANCE_SEL 8 10 CRC_SOURCE_SEL 12 12 mmAZALIA_CRC1_CONTROL1 0 0x3e9 1 0 2 CRC_BLOCK_SIZE 0 31 mmAZALIA_CRC1_CONTROL2 0 0x3ea 1 0 2 CRC_BLOCK_ITERATION 0 15 mmAZALIA_CRC1_CONTROL3 0 0x3eb 3 0 2 CRC_COMPLETE 0 0 CRC_BLOCK_COMPLETE_PHASE 4 4 CRC_CHANNEL_RESULT_SEL 8 10 mmAZALIA_CRC1_RESULT 0 0x3ec 1 0 2 CRC_RESULT 0 31 mmAZALIA_MEM_PWR_CTRL 0 0x3ee 15 0 2 AZ_MEM_PWR_FORCE 0 1 AZ_MEM_PWR_DIS 2 2 AZ_INPUT_STREAM0_MEM_PWR_FORCE 3 4 AZ_INPUT_STREAM0_MEM_PWR_DIS 5 5 AZ_INPUT_STREAM1_MEM_PWR_FORCE 6 7 AZ_INPUT_STREAM1_MEM_PWR_DIS 8 8 AZ_INPUT_STREAM2_MEM_PWR_FORCE 9 10 AZ_INPUT_STREAM2_MEM_PWR_DIS 11 11 AZ_INPUT_STREAM3_MEM_PWR_FORCE 12 13 AZ_INPUT_STREAM3_MEM_PWR_DIS 14 14 AZ_INPUT_STREAM4_MEM_PWR_FORCE 15 16 AZ_INPUT_STREAM4_MEM_PWR_DIS 17 17 AZ_INPUT_STREAM5_MEM_PWR_FORCE 18 19 AZ_INPUT_STREAM5_MEM_PWR_DIS 20 20 AZ_MEM_PWR_MODE_SEL 28 29 mmAZALIA_MEM_PWR_STATUS 0 0x3ef 7 0 2 AZ_MEM_PWR_STATE 0 1 AZ_INPUT_STREAM0_MEM_PWR_STATE 2 3 AZ_INPUT_STREAM1_MEM_PWR_STATE 4 5 AZ_INPUT_STREAM2_MEM_PWR_STATE 6 7 AZ_INPUT_STREAM3_MEM_PWR_STATE 8 9 AZ_INPUT_STREAM4_MEM_PWR_STATE 10 11 AZ_INPUT_STREAM5_MEM_PWR_STATE 12 13 mmAZALIA_F0_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID 0 0x406 1 0 2 AZALIA_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID 0 31 mmAZALIA_F0_CODEC_ROOT_PARAMETER_REVISION_ID 0 0x407 1 0 2 AZALIA_CODEC_ROOT_PARAMETER_REVISION_ID 0 31 mmAZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL 0 0x408 2 0 2 HBR_CHANNEL_COUNT 0 2 COMPRESSED_CHANNEL_COUNT 4 6 mmAZALIA_F0_CODEC_RESYNC_FIFO_CONTROL 0 0x409 1 0 2 RESYNC_FIFO_STARTUP_KEEPOUT_WINDOW 0 5 mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_GROUP_TYPE 0 0x40a 1 0 2 AZALIA_CODEC_FUNCTION_PARAMETER_GROUP_TYPE 0 31 mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES 0 0x40b 2 0 2 AUDIO_RATE_CAPABILITIES 0 11 AUDIO_BIT_CAPABILITIES 16 20 mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS 0 0x40c 1 0 2 AZALIA_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS 0 31 mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES 0 0x40d 3 0 2 AZALIA_CODEC_FUNCTION_PARAMETER_POWER_STATES 0 29 CLKSTOP 30 30 EPSS 31 31 mmAZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE 0 0x40e 4 0 2 POWER_STATE_SET 0 3 POWER_STATE_ACT 4 7 CLKSTOPOK 9 9 POWER_STATE_SETTINGS_RESET 10 10 mmAZALIA_F0_CODEC_FUNCTION_CONTROL_RESET 0 0x40f 1 0 2 CODEC_RESET 0 0 mmAZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID 0 0x410 4 0 2 SUBSYSTEM_ID_BYTE0 0 7 SUBSYSTEM_ID_BYTE1 8 15 SUBSYSTEM_ID_BYTE2 16 23 SUBSYSTEM_ID_BYTE3 24 31 mmAZALIA_F0_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION 0 0x411 1 0 2 CONVERTER_SYNCHRONIZATION 0 7 mmCC_RCU_DC_AUDIO_PORT_CONNECTIVITY 0 0x412 2 0 2 PORT_CONNECTIVITY 0 2 PORT_CONNECTIVITY_OVERRIDE_ENABLE 4 4 mmCC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY 0 0x413 2 0 2 INPUT_PORT_CONNECTIVITY 0 2 INPUT_PORT_CONNECTIVITY_OVERRIDE_ENABLE 4 4 mmAZALIA_F0_GTC_GROUP_OFFSET0 0 0x415 1 0 2 GTC_GROUP_OFFSET0 0 31 mmAZALIA_F0_GTC_GROUP_OFFSET1 0 0x416 1 0 2 GTC_GROUP_OFFSET1 0 31 mmAZALIA_F0_GTC_GROUP_OFFSET2 0 0x417 1 0 2 GTC_GROUP_OFFSET2 0 31 mmAZALIA_F0_GTC_GROUP_OFFSET3 0 0x418 1 0 2 GTC_GROUP_OFFSET3 0 31 mmAZALIA_F0_GTC_GROUP_OFFSET4 0 0x419 1 0 2 GTC_GROUP_OFFSET4 0 31 mmAZALIA_F0_GTC_GROUP_OFFSET5 0 0x41a 1 0 2 GTC_GROUP_OFFSET5 0 31 mmAZALIA_F0_GTC_GROUP_OFFSET6 0 0x41b 1 0 2 GTC_GROUP_OFFSET6 0 31 mmREG_DC_AUDIO_PORT_CONNECTIVITY 0 0x41c 2 0 2 REG_PORT_CONNECTIVITY 0 2 REG_PORT_CONNECTIVITY_OVERRIDE_ENABLE 4 4 mmREG_DC_AUDIO_INPUT_PORT_CONNECTIVITY 0 0x41d 2 0 2 REG_INPUT_PORT_CONNECTIVITY 0 2 REG_INPUT_PORT_CONNECTIVITY_OVERRIDE_ENABLE 4 4 mmAZF0STREAM8_AZALIA_STREAM_INDEX 0 0x426 2 0 2 AZALIA_STREAM_REG_INDEX 0 7 AZALIA_STREAM_REG_WRITE_EN 8 8 mmAZF0STREAM8_AZALIA_STREAM_DATA 0 0x427 1 0 2 AZALIA_STREAM_REG_DATA 0 31 mmAZF0STREAM9_AZALIA_STREAM_INDEX 0 0x428 2 0 2 AZALIA_STREAM_REG_INDEX 0 7 AZALIA_STREAM_REG_WRITE_EN 8 8 mmAZF0STREAM9_AZALIA_STREAM_DATA 0 0x429 1 0 2 AZALIA_STREAM_REG_DATA 0 31 mmAZF0STREAM10_AZALIA_STREAM_INDEX 0 0x42a 2 0 2 AZALIA_STREAM_REG_INDEX 0 7 AZALIA_STREAM_REG_WRITE_EN 8 8 mmAZF0STREAM10_AZALIA_STREAM_DATA 0 0x42b 1 0 2 AZALIA_STREAM_REG_DATA 0 31 mmAZF0STREAM11_AZALIA_STREAM_INDEX 0 0x42c 2 0 2 AZALIA_STREAM_REG_INDEX 0 7 AZALIA_STREAM_REG_WRITE_EN 8 8 mmAZF0STREAM11_AZALIA_STREAM_DATA 0 0x42d 1 0 2 AZALIA_STREAM_REG_DATA 0 31 mmAZF0STREAM12_AZALIA_STREAM_INDEX 0 0x42e 2 0 2 AZALIA_STREAM_REG_INDEX 0 7 AZALIA_STREAM_REG_WRITE_EN 8 8 mmAZF0STREAM12_AZALIA_STREAM_DATA 0 0x42f 1 0 2 AZALIA_STREAM_REG_DATA 0 31 mmAZF0STREAM13_AZALIA_STREAM_INDEX 0 0x430 2 0 2 AZALIA_STREAM_REG_INDEX 0 7 AZALIA_STREAM_REG_WRITE_EN 8 8 mmAZF0STREAM13_AZALIA_STREAM_DATA 0 0x431 1 0 2 AZALIA_STREAM_REG_DATA 0 31 mmAZF0STREAM14_AZALIA_STREAM_INDEX 0 0x432 2 0 2 AZALIA_STREAM_REG_INDEX 0 7 AZALIA_STREAM_REG_WRITE_EN 8 8 mmAZF0STREAM14_AZALIA_STREAM_DATA 0 0x433 1 0 2 AZALIA_STREAM_REG_DATA 0 31 mmAZF0STREAM15_AZALIA_STREAM_INDEX 0 0x434 2 0 2 AZALIA_STREAM_REG_INDEX 0 7 AZALIA_STREAM_REG_WRITE_EN 8 8 mmAZF0STREAM15_AZALIA_STREAM_DATA 0 0x435 1 0 2 AZALIA_STREAM_REG_DATA 0 31 mmAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0 0x43a 1 0 2 AZALIA_INPUT_ENDPOINT_REG_INDEX 0 13 mmAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0 0x43b 1 0 2 AZALIA_INPUT_ENDPOINT_REG_DATA 0 31 mmAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0 0x43e 1 0 2 AZALIA_INPUT_ENDPOINT_REG_INDEX 0 13 mmAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0 0x43f 1 0 2 AZALIA_INPUT_ENDPOINT_REG_DATA 0 31 mmAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0 0x442 1 0 2 AZALIA_INPUT_ENDPOINT_REG_INDEX 0 13 mmAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0 0x443 1 0 2 AZALIA_INPUT_ENDPOINT_REG_DATA 0 31 mmAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0 0x446 1 0 2 AZALIA_INPUT_ENDPOINT_REG_INDEX 0 13 mmAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0 0x447 1 0 2 AZALIA_INPUT_ENDPOINT_REG_DATA 0 31 mmAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0 0x44a 1 0 2 AZALIA_INPUT_ENDPOINT_REG_INDEX 0 13 mmAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0 0x44b 1 0 2 AZALIA_INPUT_ENDPOINT_REG_DATA 0 31 mmAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0 0x44e 1 0 2 AZALIA_INPUT_ENDPOINT_REG_INDEX 0 13 mmAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0 0x44f 1 0 2 AZALIA_INPUT_ENDPOINT_REG_DATA 0 31 mmAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0 0x452 1 0 2 AZALIA_INPUT_ENDPOINT_REG_INDEX 0 13 mmAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0 0x453 1 0 2 AZALIA_INPUT_ENDPOINT_REG_DATA 0 31 mmAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0 0x456 1 0 2 AZALIA_INPUT_ENDPOINT_REG_INDEX 0 13 mmAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0 0x457 1 0 2 AZALIA_INPUT_ENDPOINT_REG_DATA 0 31 mmDCHUBBUB_SDPIF_CFG0 0 0x48f 11 0 2 SDPIF_NO_OUTSTANDING_REQ 0 0 SDPIF_PORT_STATUS 1 2 SDPIF_DATA_RESPONSE_STATUS 3 5 SDPIF_REQ_CREDIT_ERROR 6 6 SDPIF_DATA_RESPONSE_STATUS_CLEAR 7 7 SDPIF_REQ_CREDIT_ERROR_CLEAR 8 8 SDPIF_FLUSH_REQ_CREDIT_EN 9 9 SDPIF_REQ_CREDIT_EN 10 10 SDPIF_PORT_CONTROL 11 11 SDPIF_UNIT_ID_BITMASK 12 19 SDPIF_CREDIT_DISCONNECT_DELAY 20 25 mmDCHUBBUB_SDPIF_CFG1 0 0x490 4 0 2 SDPIF_INSIDE_FB_IO 0 0 SDPIF_INSIDE_FB_VC 1 3 SDPIF_OUTSIDE_FB_IO 4 4 SDPIF_OUTSIDE_FB_VC 5 7 mmDCHUBBUB_FORCE_IO_STATUS_0 0 0x491 6 0 2 SDPIF_FORCE_IO_STATUS 0 0 SDPIF_FORCE_IO_STATUS_STICKY 1 1 SDPIF_FORCE_IO_STATUS_CLEAR 2 2 SDPIF_FORCE_IO_STATUS_PIPE_ID 3 6 SDPIF_FORCE_IO_STATUS_REQUEST_TYPE 7 9 SDPIF_FORCE_IO_STATUS_ADDR_LO 10 31 mmDCHUBBUB_FORCE_IO_STATUS_1 0 0x492 1 0 2 SDPIF_FORCE_IO_STATUS_ADDR_HI 0 20 mmDCHUBBUB_SDPIF_FB_BASE 0 0x493 1 0 2 SDPIF_FB_BASE 0 23 mmDCHUBBUB_SDPIF_FB_TOP 0 0x494 1 0 2 SDPIF_FB_TOP 0 23 mmDCHUBBUB_SDPIF_FB_OFFSET 0 0x495 1 0 2 SDPIF_FB_OFFSET 0 23 mmDCHUBBUB_SDPIF_AGP_BOT 0 0x496 1 0 2 SDPIF_AGP_BOT 0 25 mmDCHUBBUB_SDPIF_AGP_TOP 0 0x497 1 0 2 SDPIF_AGP_TOP 0 25 mmDCHUBBUB_SDPIF_AGP_BASE 0 0x498 1 0 2 SDPIF_AGP_BASE 0 25 mmDCHUBBUB_SDPIF_APER_BASE 0 0x499 2 0 2 SDPIF_APER_BASE 0 27 SDPIF_LOCK_DRAM_REGS 28 28 mmDCHUBBUB_SDPIF_APER_TOP 0 0x49a 1 0 2 SDPIF_APER_TOP 0 27 mmDCHUBBUB_SDPIF_APER_DEF_0 0 0x49b 1 0 2 SDPIF_APER_DEF_0 0 31 mmDCHUBBUB_SDPIF_APER_DEF_1 0 0x49c 1 0 2 SDPIF_APER_DEF_1 0 3 mmDCHUBBUB_SDPIF_MMIO_CNTRL_0 0 0x49d 1 0 2 SDPIF_IOMMU_EN 0 0 mmDCHUBBUB_SDPIF_MMIO_CNTRL_1 0 0x49e 1 0 2 SDPIF_MARC_EN 8 8 mmDCHUBBUB_SDPIF_MMIO_CNTRL_W 0 0x49f 1 0 2 SDPIF_GMC_IOMMU_BYPASS 13 13 mmDCHUBBUB_SDPIF_MARC_BASE_LO_0 0 0x4a0 1 0 2 SDPIF_MARC_BASE_LO_0 12 31 mmDCHUBBUB_SDPIF_MARC_BASE_HI_0 0 0x4a1 1 0 2 SDPIF_MARC_BASE_HI_0 0 15 mmDCHUBBUB_SDPIF_MARC_RELOC_LO_0 0 0x4a2 2 0 2 SDPIF_MARC_EN_0 0 0 SDPIF_MARC_RELOC_LO_0 12 31 mmDCHUBBUB_SDPIF_MARC_RELOC_HI_0 0 0x4a3 1 0 2 SDPIF_MARC_RELOC_HI_0 0 15 mmDCHUBBUB_SDPIF_MARC_LENGTH_LO_0 0 0x4a4 1 0 2 SDPIF_MARC_LENGTH_LO_0 12 31 mmDCHUBBUB_SDPIF_MARC_LENGTH_HI_0 0 0x4a5 1 0 2 SDPIF_MARC_LENGTH_HI_0 0 15 mmDCHUBBUB_SDPIF_MARC_BASE_LO_1 0 0x4a6 1 0 2 SDPIF_MARC_BASE_LO_1 12 31 mmDCHUBBUB_SDPIF_MARC_BASE_HI_1 0 0x4a7 1 0 2 SDPIF_MARC_BASE_HI_1 0 15 mmDCHUBBUB_SDPIF_MARC_RELOC_LO_1 0 0x4a8 2 0 2 SDPIF_MARC_EN_1 0 0 SDPIF_MARC_RELOC_LO_1 12 31 mmDCHUBBUB_SDPIF_MARC_RELOC_HI_1 0 0x4a9 1 0 2 SDPIF_MARC_RELOC_HI_1 0 15 mmDCHUBBUB_SDPIF_MARC_LENGTH_LO_1 0 0x4aa 1 0 2 SDPIF_MARC_LENGTH_LO_1 12 31 mmDCHUBBUB_SDPIF_MARC_LENGTH_HI_1 0 0x4ab 1 0 2 SDPIF_MARC_LENGTH_HI_1 0 15 mmDCHUBBUB_SDPIF_MARC_BASE_LO_2 0 0x4ac 1 0 2 SDPIF_MARC_BASE_LO_2 12 31 mmDCHUBBUB_SDPIF_MARC_BASE_HI_2 0 0x4ad 1 0 2 SDPIF_MARC_BASE_HI_2 0 15 mmDCHUBBUB_SDPIF_MARC_RELOC_LO_2 0 0x4ae 2 0 2 SDPIF_MARC_EN_2 0 0 SDPIF_MARC_RELOC_LO_2 12 31 mmDCHUBBUB_SDPIF_MARC_RELOC_HI_2 0 0x4af 1 0 2 SDPIF_MARC_RELOC_HI_2 0 15 mmDCHUBBUB_SDPIF_MARC_LENGTH_LO_2 0 0x4b0 1 0 2 SDPIF_MARC_LENGTH_LO_2 12 31 mmDCHUBBUB_SDPIF_MARC_LENGTH_HI_2 0 0x4b1 1 0 2 SDPIF_MARC_LENGTH_HI_2 0 15 mmDCHUBBUB_SDPIF_MARC_BASE_LO_3 0 0x4b2 1 0 2 SDPIF_MARC_BASE_LO_3 12 31 mmDCHUBBUB_SDPIF_MARC_BASE_HI_3 0 0x4b3 1 0 2 SDPIF_MARC_BASE_HI_3 0 15 mmDCHUBBUB_SDPIF_MARC_RELOC_LO_3 0 0x4b4 2 0 2 SDPIF_MARC_EN_3 0 0 SDPIF_MARC_RELOC_LO_3 12 31 mmDCHUBBUB_SDPIF_MARC_RELOC_HI_3 0 0x4b5 1 0 2 SDPIF_MARC_RELOC_HI_3 0 15 mmDCHUBBUB_SDPIF_MARC_LENGTH_LO_3 0 0x4b6 1 0 2 SDPIF_MARC_LENGTH_LO_3 12 31 mmDCHUBBUB_SDPIF_MARC_LENGTH_HI_3 0 0x4b7 1 0 2 SDPIF_MARC_LENGTH_HI_3 0 15 mmDCHUBBUB_SDPIF_PIPE_SEC_LVL 0 0x4b8 4 0 2 SDPIF_PIPE0_SEC_LVL 0 2 SDPIF_PIPE1_SEC_LVL 3 5 SDPIF_PIPE2_SEC_LVL 6 8 SDPIF_PIPE3_SEC_LVL 9 11 mmDCHUBBUB_SDPIF_MEM_PWR_CTRL 0 0x4b9 2 0 2 DCHUBBUB_SDPIF_MEM_PWR_FORCE 0 1 DCHUBBUB_SDPIF_MEM_PWR_DIS 2 2 mmDCHUBBUB_SDPIF_MEM_PWR_STATUS 0 0x4ba 1 0 2 DCHUBBUB_SDPIF_MEM_PWR_STATE 0 1 mmDCHUBBUB_RET_PATH_DCC_CFG 0 0x4cf 1 0 2 DCC_VIDEO_FORMAT_EN 0 0 mmDCHUBBUB_RET_PATH_DCC_CFG0_0 0 0x4d0 1 0 2 DCC_CFG0_CONSTANT_0 0 31 mmDCHUBBUB_RET_PATH_DCC_CFG0_1 0 0x4d1 1 0 2 DCC_CFG0_CONSTANT_1 0 31 mmDCHUBBUB_RET_PATH_DCC_CFG1_0 0 0x4d2 1 0 2 DCC_CFG1_CONSTANT_0 0 31 mmDCHUBBUB_RET_PATH_DCC_CFG1_1 0 0x4d3 1 0 2 DCC_CFG1_CONSTANT_1 0 31 mmDCHUBBUB_RET_PATH_DCC_CFG2_0 0 0x4d4 1 0 2 DCC_CFG2_CONSTANT_0 0 31 mmDCHUBBUB_RET_PATH_DCC_CFG2_1 0 0x4d5 1 0 2 DCC_CFG2_CONSTANT_1 0 31 mmDCHUBBUB_RET_PATH_DCC_CFG3_0 0 0x4d6 1 0 2 DCC_CFG3_CONSTANT_0 0 31 mmDCHUBBUB_RET_PATH_DCC_CFG3_1 0 0x4d7 1 0 2 DCC_CFG3_CONSTANT_1 0 31 mmDCHUBBUB_RET_PATH_DCC_CFG4_0 0 0x4d8 1 0 2 DCC_CFG4_CONSTANT_0 0 31 mmDCHUBBUB_RET_PATH_DCC_CFG4_1 0 0x4d9 1 0 2 DCC_CFG4_CONSTANT_1 0 31 mmDCHUBBUB_RET_PATH_DCC_CFG5_0 0 0x4da 1 0 2 DCC_CFG5_CONSTANT_0 0 31 mmDCHUBBUB_RET_PATH_DCC_CFG5_1 0 0x4db 1 0 2 DCC_CFG5_CONSTANT_1 0 31 mmDCHUBBUB_RET_PATH_DCC_CFG6_0 0 0x4dc 1 0 2 DCC_CFG6_CONSTANT_0 0 31 mmDCHUBBUB_RET_PATH_DCC_CFG6_1 0 0x4dd 1 0 2 DCC_CFG6_CONSTANT_1 0 31 mmDCHUBBUB_RET_PATH_DCC_CFG7_0 0 0x4de 1 0 2 DCC_CFG7_CONSTANT_0 0 31 mmDCHUBBUB_RET_PATH_DCC_CFG7_1 0 0x4df 1 0 2 DCC_CFG7_CONSTANT_1 0 31 mmDCHUBBUB_RET_PATH_MEM_PWR_CTRL 0 0x4e0 2 0 2 DCHUBBUB_RET_PATH_MEM_PWR_FORCE 0 1 DCHUBBUB_RET_PATH_MEM_PWR_DIS 2 2 mmDCHUBBUB_RET_PATH_MEM_PWR_STATUS 0 0x4e1 1 0 2 DCHUBBUB_RET_PATH_MEM_PWR_STATE 0 1 mmDCHUBBUB_CRC_CTRL 0 0x4e2 9 0 2 DCHUBBUB_CRC_EN 0 0 DCHUBBUB_CRC_CONT_EN 1 1 DCHUBBUB_CRC0_ONE_SHOT_PENDING 2 2 DCHUBBUB_CRC1_ONE_SHOT_PENDING 3 3 DCHUBBUB_CRC0_SRC_SEL 4 5 DCHUBBUB_CRC1_SRC_SEL 6 7 DCHUBBUB_CRC_PIPE_SEL 8 11 DCHUBBUB_CRC_SURF_SEL 12 13 DCHUBBUB_CRC_DATA_SRC_SEL 14 14 mmDCHUBBUB_CRC0_VAL_R_G 0 0x4e3 2 0 2 DCHUBBUB_CRC0_R_CR 0 15 DCHUBBUB_CRC0_G_Y 16 31 mmDCHUBBUB_CRC0_VAL_B_A 0 0x4e4 2 0 2 DCHUBBUB_CRC0_B_CB 0 15 DCHUBBUB_CRC0_ALPHA 16 31 mmDCHUBBUB_CRC1_VAL_R_G 0 0x4e5 2 0 2 DCHUBBUB_CRC1_R_CR 0 15 DCHUBBUB_CRC1_G_Y 16 31 mmDCHUBBUB_CRC1_VAL_B_A 0 0x4e6 2 0 2 DCHUBBUB_CRC1_B_CB 0 15 DCHUBBUB_CRC1_ALPHA 16 31 mmDCHUBBUB_ARB_DF_REQ_OUTSTAND 0 0x505 2 0 2 DCHUBBUB_ARB_MAX_REQ_OUTSTAND 0 8 DCHUBBUB_ARB_MIN_REQ_OUTSTAND 16 24 mmDCHUBBUB_ARB_SAT_LEVEL 0 0x506 1 0 2 DCHUBBUB_ARB_SAT_LEVEL 0 31 mmDCHUBBUB_ARB_QOS_FORCE 0 0x507 2 0 2 DCHUBBUB_ARB_QOS_FORCE_VALUE 0 3 DCHUBBUB_ARB_QOS_FORCE_ENABLE 8 8 mmDCHUBBUB_ARB_DRAM_STATE_CNTL 0 0x508 5 0 2 DCHUBBUB_ARB_ALLOW_SELF_REFRESH_FORCE_VALUE 0 0 DCHUBBUB_ARB_ALLOW_SELF_REFRESH_FORCE_ENABLE 1 1 DCHUBBUB_ARB_ALLOW_SELF_REFRESH_FORCED_CLEAR_DISABLE 2 2 DCHUBBUB_ARB_ALLOW_PSTATE_CHANGE_FORCE_VALUE 4 4 DCHUBBUB_ARB_ALLOW_PSTATE_CHANGE_FORCE_ENABLE 5 5 mmDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A 0 0x509 1 0 2 DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A 0 20 mmDCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_A 0 0x50a 1 0 2 DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_A 0 20 mmDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A 0 0x50b 1 0 2 DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A 0 20 mmDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A 0 0x50c 1 0 2 DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A 0 20 mmDCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A 0 0x50d 1 0 2 DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A 0 20 mmDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B 0 0x50e 1 0 2 DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B 0 20 mmDCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_B 0 0x50f 1 0 2 DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_B 0 20 mmDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B 0 0x510 1 0 2 DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B 0 20 mmDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B 0 0x511 1 0 2 DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B 0 20 mmDCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B 0 0x512 1 0 2 DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B 0 20 mmDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C 0 0x513 1 0 2 DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C 0 20 mmDCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_C 0 0x514 1 0 2 DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_C 0 20 mmDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C 0 0x515 1 0 2 DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C 0 20 mmDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C 0 0x516 1 0 2 DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C 0 20 mmDCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_C 0 0x517 1 0 2 DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_C 0 20 mmDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D 0 0x518 1 0 2 DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D 0 20 mmDCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_D 0 0x519 1 0 2 DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_D 0 20 mmDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D 0 0x51a 1 0 2 DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D 0 20 mmDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D 0 0x51b 1 0 2 DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D 0 20 mmDCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D 0 0x51c 1 0 2 DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D 0 20 mmDCHUBBUB_ARB_WATERMARK_CHANGE_CNTL 0 0x51d 5 0 2 DCHUBBUB_ARB_WATERMARK_CHANGE_SELECT 0 1 DCHUBBUB_ARB_WATERMARK_CHANGE_DONE_INTERRUPT_DISABLE 4 4 DCHUBBUB_ARB_WATERMARK_CHANGE_DONE_INTERRUPT_STATUS 5 5 DCHUBBUB_ARB_WATERMARK_CHANGE_DONE_INTERRUPT_ACK 6 6 DCHUBBUB_ARB_WATERMARK_CHANGE_REQUEST 8 8 mmDCHUBBUB_ARB_TIMEOUT_ENABLE 0 0x51e 1 0 2 DCHUBBUB_ARB_TIMEOUT_ENABLE 0 0 mmDCHUBBUB_GLOBAL_TIMER_CNTL 0 0x51f 3 0 2 DCHUBBUB_GLOBAL_TIMER_REFDIV 0 3 DCHUBBUB_GLOBAL_TIMER_ENABLE 12 12 DCHUBBUB_GLOBAL_TIMER_INIT 16 31 mmSURFACE_CHECK0_ADDRESS_LSB 0 0x520 1 0 2 SURFACE_CHECK0_ADDRESS_LSB 0 31 mmSURFACE_CHECK0_ADDRESS_MSB 0 0x521 2 0 2 SURFACE_CHECK0_ADDRESS_MSB 0 15 CHECKER0_SURFACE_INUSE 31 31 mmSURFACE_CHECK1_ADDRESS_LSB 0 0x522 1 0 2 SURFACE_CHECK1_ADDRESS_LSB 0 31 mmSURFACE_CHECK1_ADDRESS_MSB 0 0x523 2 0 2 SURFACE_CHECK1_ADDRESS_MSB 0 15 CHECKER1_SURFACE_INUSE 31 31 mmSURFACE_CHECK2_ADDRESS_LSB 0 0x524 1 0 2 SURFACE_CHECK2_ADDRESS_LSB 0 31 mmSURFACE_CHECK2_ADDRESS_MSB 0 0x525 2 0 2 SURFACE_CHECK2_ADDRESS_MSB 0 15 CHECKER2_SURFACE_INUSE 31 31 mmSURFACE_CHECK3_ADDRESS_LSB 0 0x526 1 0 2 SURFACE_CHECK3_ADDRESS_LSB 0 31 mmSURFACE_CHECK3_ADDRESS_MSB 0 0x527 2 0 2 SURFACE_CHECK3_ADDRESS_MSB 0 15 CHECKER3_SURFACE_INUSE 31 31 mmVTG0_CONTROL 0 0x528 3 0 2 VTG0_FP2 0 14 VTG0_VCOUNT_INIT 15 29 VTG0_ENABLE 31 31 mmVTG1_CONTROL 0 0x529 3 0 2 VTG1_FP2 0 14 VTG1_VCOUNT_INIT 15 29 VTG1_ENABLE 31 31 mmVTG2_CONTROL 0 0x52a 3 0 2 VTG2_FP2 0 14 VTG2_VCOUNT_INIT 15 29 VTG2_ENABLE 31 31 mmVTG3_CONTROL 0 0x52b 3 0 2 VTG3_FP2 0 14 VTG3_VCOUNT_INIT 15 29 VTG3_ENABLE 31 31 mmVTG4_CONTROL 0 0x52c 3 0 2 VTG4_FP2 0 14 VTG4_VCOUNT_INIT 15 29 VTG4_ENABLE 31 31 mmVTG5_CONTROL 0 0x52d 3 0 2 VTG5_FP2 0 14 VTG5_VCOUNT_INIT 15 29 VTG5_ENABLE 31 31 mmDCHUBBUB_SOFT_RESET 0 0x52e 3 0 2 DCHUBBUB_GLOBAL_SOFT_RESET 0 0 ALLOW_CSTATE_SOFT_RESET 1 1 GLBFLIP_SOFT_RESET 4 4 mmDCHUBBUB_CLOCK_CNTL 0 0x52f 3 0 2 DCHUBBUB_TEST_CLK_SEL 0 4 DISPCLK_R_DCHUBBUB_GATE_DIS 5 5 DCFCLK_R_DCHUBBUB_GATE_DIS 6 6 mmDCFCLK_CNTL 0 0x530 3 0 2 DCFCLK_TURN_ON_DELAY 0 3 DCFCLK_TURN_OFF_DELAY 4 11 DCFCLK_GATE_DIS 31 31 mmDCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL 0 0x531 7 0 2 DCHUBBUB_LATENCY_CNT_EN 0 0 ARB_LATENCY_PIPE_SEL 3 6 ARB_LATENCY_REQ_TYPE_SEL 7 9 DF_LATENCY_URGENT_ONLY 10 10 ROB_FIFO_LEVEL 11 20 ROB_MAX_FIFO_LEVEL 21 30 ROB_MAX_FIFO_LEVEL_RESET 31 31 mmDCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL2 0 0x532 4 0 2 DCHUBBUB_LATENCY_FRAME_WIN_EN 0 0 DCHUBBUB_LATENCY_FRAME_WIN_SRC_SEL 1 3 DCHUBBUB_LATENCY_FRAME_WIN_DUR 4 11 LATENCY_SOURCE_SEL 12 14 mmDCHUBBUB_VLINE_SNAPSHOT 0 0x533 1 0 2 DCHUBBUB_VLINE_SNAPSHOT 0 0 mmDCHUBBUB_SPARE 0 0x534 1 0 2 DCHUBBUB_SPARE 0 31 mmDCHUBBUB_TEST_DEBUG_INDEX 0 0x53a 0 0 2 mmDCHUBBUB_TEST_DEBUG_DATA 0 0x53b 0 0 2 mmDC_PERFMON7_PERFCOUNTER_CNTL 0 0x54d 11 0 2 PERFCOUNTER_EVENT_SEL 0 8 PERFCOUNTER_CVALUE_SEL 9 11 PERFCOUNTER_INC_MODE 12 14 PERFCOUNTER_HW_CNTL_SEL 15 15 PERFCOUNTER_RUNEN_MODE 16 16 PERFCOUNTER_CNTOFF_START_DIS 22 22 PERFCOUNTER_RESTART_EN 23 23 PERFCOUNTER_INT_EN 24 24 PERFCOUNTER_OFF_MASK 25 25 PERFCOUNTER_ACTIVE 26 26 PERFCOUNTER_CNTL_SEL 29 31 mmDC_PERFMON7_PERFCOUNTER_CNTL2 0 0x54e 5 0 2 PERFCOUNTER_COUNTED_VALUE_TYPE 0 1 PERFCOUNTER_HW_STOP1_SEL 2 2 PERFCOUNTER_HW_STOP2_SEL 3 3 PERFCOUNTER_CNTOFF_SEL 8 13 PERFCOUNTER_CNTL2_SEL 29 31 mmDC_PERFMON7_PERFCOUNTER_STATE 0 0x54f 16 0 2 PERFCOUNTER_CNT0_STATE 0 1 PERFCOUNTER_STATE_SEL0 2 2 PERFCOUNTER_CNT1_STATE 4 5 PERFCOUNTER_STATE_SEL1 6 6 PERFCOUNTER_CNT2_STATE 8 9 PERFCOUNTER_STATE_SEL2 10 10 PERFCOUNTER_CNT3_STATE 12 13 PERFCOUNTER_STATE_SEL3 14 14 PERFCOUNTER_CNT4_STATE 16 17 PERFCOUNTER_STATE_SEL4 18 18 PERFCOUNTER_CNT5_STATE 20 21 PERFCOUNTER_STATE_SEL5 22 22 PERFCOUNTER_CNT6_STATE 24 25 PERFCOUNTER_STATE_SEL6 26 26 PERFCOUNTER_CNT7_STATE 28 29 PERFCOUNTER_STATE_SEL7 30 30 mmDC_PERFMON7_PERFMON_CNTL 0 0x550 6 0 2 PERFMON_STATE 0 1 PERFMON_RPT_COUNT 8 27 PERFMON_CNTOFF_AND_OR 28 28 PERFMON_CNTOFF_INT_EN 29 29 PERFMON_CNTOFF_INT_STATUS 30 30 PERFMON_CNTOFF_INT_ACK 31 31 mmDC_PERFMON7_PERFMON_CNTL2 0 0x551 4 0 2 PERFMON_CNTOFF_INT_TYPE 0 0 PERFMON_CLK_ENABLE 1 1 PERFMON_RUN_ENABLE_START_SEL 2 9 PERFMON_RUN_ENABLE_STOP_SEL 10 17 mmDC_PERFMON7_PERFMON_CVALUE_INT_MISC 0 0x552 17 0 2 PERFCOUNTER_INT0_STATUS 0 0 PERFCOUNTER_INT1_STATUS 1 1 PERFCOUNTER_INT2_STATUS 2 2 PERFCOUNTER_INT3_STATUS 3 3 PERFCOUNTER_INT4_STATUS 4 4 PERFCOUNTER_INT5_STATUS 5 5 PERFCOUNTER_INT6_STATUS 6 6 PERFCOUNTER_INT7_STATUS 7 7 PERFCOUNTER_INT0_ACK 8 8 PERFCOUNTER_INT1_ACK 9 9 PERFCOUNTER_INT2_ACK 10 10 PERFCOUNTER_INT3_ACK 11 11 PERFCOUNTER_INT4_ACK 12 12 PERFCOUNTER_INT5_ACK 13 13 PERFCOUNTER_INT6_ACK 14 14 PERFCOUNTER_INT7_ACK 15 15 PERFMON_CVALUE_HI 16 31 mmDC_PERFMON7_PERFMON_CVALUE_LOW 0 0x553 1 0 2 PERFMON_CVALUE_LOW 0 31 mmDC_PERFMON7_PERFMON_HI 0 0x554 2 0 2 PERFMON_HI 0 15 PERFMON_READ_SEL 29 31 mmDC_PERFMON7_PERFMON_LOW 0 0x555 1 0 2 PERFMON_LOW 0 31 mmHUBP0_DCSURF_SURFACE_CONFIG 0 0x559 3 0 2 SURFACE_PIXEL_FORMAT 0 6 ROTATION_ANGLE 8 9 H_MIRROR_EN 10 10 mmHUBP0_DCSURF_ADDR_CONFIG 0 0x55a 6 0 2 NUM_PIPES 0 2 NUM_BANKS 3 5 PIPE_INTERLEAVE 6 7 NUM_SE 8 9 NUM_RB_PER_SE 10 11 MAX_COMPRESSED_FRAGS 12 13 mmHUBP0_DCSURF_TILING_CONFIG 0 0x55b 5 0 2 SW_MODE 0 4 DIM_TYPE 7 8 META_LINEAR 9 9 RB_ALIGNED 10 10 PIPE_ALIGNED 11 11 mmHUBP0_DCSURF_PRI_VIEWPORT_START 0 0x55c 2 0 2 PRI_VIEWPORT_X_START 0 13 PRI_VIEWPORT_Y_START 16 29 mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION 0 0x55d 2 0 2 PRI_VIEWPORT_WIDTH 0 13 PRI_VIEWPORT_HEIGHT 16 29 mmHUBP0_DCSURF_PRI_VIEWPORT_START_C 0 0x55e 2 0 2 PRI_VIEWPORT_X_START_C 0 13 PRI_VIEWPORT_Y_START_C 16 29 mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_C 0 0x55f 2 0 2 PRI_VIEWPORT_WIDTH_C 0 13 PRI_VIEWPORT_HEIGHT_C 16 29 mmHUBP0_DCSURF_SEC_VIEWPORT_START 0 0x560 2 0 2 SEC_VIEWPORT_X_START 0 13 SEC_VIEWPORT_Y_START 16 29 mmHUBP0_DCSURF_SEC_VIEWPORT_DIMENSION 0 0x561 2 0 2 SEC_VIEWPORT_WIDTH 0 13 SEC_VIEWPORT_HEIGHT 16 29 mmHUBP0_DCSURF_SEC_VIEWPORT_START_C 0 0x562 2 0 2 SEC_VIEWPORT_X_START_C 0 13 SEC_VIEWPORT_Y_START_C 16 29 mmHUBP0_DCSURF_SEC_VIEWPORT_DIMENSION_C 0 0x563 2 0 2 SEC_VIEWPORT_WIDTH_C 0 13 SEC_VIEWPORT_HEIGHT_C 16 29 mmHUBP0_DCHUBP_REQ_SIZE_CONFIG 0 0x564 8 0 2 SWATH_HEIGHT 0 2 PTE_ROW_HEIGHT_LINEAR 4 6 CHUNK_SIZE 8 10 MIN_CHUNK_SIZE 11 12 META_CHUNK_SIZE 16 17 MIN_META_CHUNK_SIZE 18 19 DPTE_GROUP_SIZE 20 22 MPTE_GROUP_SIZE 24 26 mmHUBP0_DCHUBP_REQ_SIZE_CONFIG_C 0 0x565 8 0 2 SWATH_HEIGHT_C 0 2 PTE_ROW_HEIGHT_LINEAR_C 4 6 CHUNK_SIZE_C 8 10 MIN_CHUNK_SIZE_C 11 12 META_CHUNK_SIZE_C 16 17 MIN_META_CHUNK_SIZE_C 18 19 DPTE_GROUP_SIZE_C 20 22 MPTE_GROUP_SIZE_C 24 26 mmHUBP0_DCHUBP_CNTL 0 0x566 9 0 2 HUBP_BLANK_EN 0 0 HUBP_NO_OUTSTANDING_REQ 1 1 HUBP_DISABLE 2 2 HUBP_IN_BLANK 3 3 HUBP_VTG_SEL 4 7 HUBP_TTU_DISABLE 12 12 HUBP_TTU_MODE 13 15 HUBP_UNDERFLOW_STATUS 28 30 HUBP_UNDERFLOW_CLEAR 31 31 mmHUBP0_HUBP_CLK_CNTL 0 0x567 10 0 2 HUBP_CLOCK_ENABLE 0 0 HUBP_DISPCLK_R_GATE_DIS 4 4 HUBP_DPPCLK_G_GATE_DIS 8 8 HUBP_DCFCLK_R_GATE_DIS 12 12 HUBP_DCFCLK_G_GATE_DIS 16 16 HUBP_DISPCLK_R_CLOCK_ON 20 20 HUBP_DPPCLK_G_CLOCK_ON 21 21 HUBP_DCFCLK_R_CLOCK_ON 22 22 HUBP_DCFCLK_G_CLOCK_ON 23 23 HUBP_TEST_CLK_SEL 28 31 mmHUBP0_DCHUBP_VMPG_CONFIG 0 0x568 1 0 2 VMPG_SIZE 0 0 mmHUBP0_HUBPREQ_DEBUG_DB 0 0x569 1 0 2 HUBPREQ_DEBUG 0 31 mmHUBP0_HUBPREQ_DEBUG 0 0x56a 0 0 2 mmHUBP0_HUBP_MEASURE_WIN_CTRL_DCFCLK 0 0x56e 5 0 2 HUBP_MEASURE_WIN_EN_DCFCLK 0 0 HUBP_MEASURE_WIN_PERIOD_M1_DCFCLK 4 11 HUBP_PERFMON_START_SEL_DCFCLK 12 16 HUBP_PERFMON_STOP_SEL_DCFCLK 20 24 HUBP_MEASURE_WIN_MODE_DCFCLK 28 29 mmHUBP0_HUBP_MEASURE_WIN_CTRL_DPPCLK 0 0x56f 5 0 2 HUBP_MEASURE_WIN_EN_DPPCLK 0 0 HUBP_MEASURE_WIN_SRC_SEL_DPPCLK 1 1 HUBP_MEASURE_WIN_PERIOD_M1_DPPCLK 4 11 HUBP_PERFMON_START_SEL_DPPCLK 12 16 HUBP_PERFMON_STOP_SEL_DPPCLK 20 24 mmHUBPREQ0_DCSURF_SURFACE_PITCH 0 0x57b 2 0 2 PITCH 0 13 META_PITCH 16 29 mmHUBPREQ0_DCSURF_SURFACE_PITCH_C 0 0x57c 2 0 2 PITCH_C 0 13 META_PITCH_C 16 29 mmHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS 0 0x57d 1 0 2 PRIMARY_SURFACE_ADDRESS 0 31 mmHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH 0 0x57e 1 0 2 PRIMARY_SURFACE_ADDRESS_HIGH 0 15 mmHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_C 0 0x57f 1 0 2 PRIMARY_SURFACE_ADDRESS_C 0 31 mmHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C 0 0x580 1 0 2 PRIMARY_SURFACE_ADDRESS_HIGH_C 0 15 mmHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS 0 0x581 1 0 2 SECONDARY_SURFACE_ADDRESS 0 31 mmHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH 0 0x582 1 0 2 SECONDARY_SURFACE_ADDRESS_HIGH 0 15 mmHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_C 0 0x583 1 0 2 SECONDARY_SURFACE_ADDRESS_C 0 31 mmHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C 0 0x584 1 0 2 SECONDARY_SURFACE_ADDRESS_HIGH_C 0 15 mmHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS 0 0x585 1 0 2 PRIMARY_META_SURFACE_ADDRESS 0 31 mmHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH 0 0x586 1 0 2 PRIMARY_META_SURFACE_ADDRESS_HIGH 0 15 mmHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C 0 0x587 1 0 2 PRIMARY_META_SURFACE_ADDRESS_C 0 31 mmHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C 0 0x588 1 0 2 PRIMARY_META_SURFACE_ADDRESS_HIGH_C 0 15 mmHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS 0 0x589 1 0 2 SECONDARY_META_SURFACE_ADDRESS 0 31 mmHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH 0 0x58a 1 0 2 SECONDARY_META_SURFACE_ADDRESS_HIGH 0 15 mmHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C 0 0x58b 1 0 2 SECONDARY_META_SURFACE_ADDRESS_C 0 31 mmHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C 0 0x58c 1 0 2 SECONDARY_META_SURFACE_ADDRESS_HIGH_C 0 15 mmHUBPREQ0_DCSURF_SURFACE_CONTROL 0 0x58d 14 0 2 PRIMARY_SURFACE_TMZ 0 0 PRIMARY_SURFACE_DCC_EN 1 1 PRIMARY_SURFACE_DCC_IND_64B_BLK 2 2 PRIMARY_SURFACE_TMZ_C 4 4 PRIMARY_SURFACE_DCC_IND_64B_BLK_C 5 5 SECONDARY_SURFACE_TMZ 8 8 SECONDARY_SURFACE_DCC_EN 9 9 SECONDARY_SURFACE_DCC_IND_64B_BLK 10 10 SECONDARY_SURFACE_TMZ_C 12 12 SECONDARY_SURFACE_DCC_IND_64B_BLK_C 13 13 PRIMARY_META_SURFACE_TMZ 16 16 PRIMARY_META_SURFACE_TMZ_C 20 20 SECONDARY_META_SURFACE_TMZ 24 24 SECONDARY_META_SURFACE_TMZ_C 28 28 mmHUBPREQ0_DCSURF_FLIP_CONTROL 0 0x58e 10 0 2 SURFACE_UPDATE_LOCK 0 0 SURFACE_FLIP_TYPE 1 1 SURFACE_FLIP_VUPDATE_SKIP_NUM 4 7 SURFACE_FLIP_MODE_FOR_STEREOSYNC 12 13 SURFACE_FLIP_IN_STEREOSYNC 16 16 SURFACE_FLIP_STEREO_SELECT_DISABLE 17 17 SURFACE_FLIP_STEREO_SELECT_POLARITY 18 18 SURFACE_FLIP_PENDING_DELAY 20 29 SURFACE_UPDATE_PENDING 30 30 SURFACE_FLIP_PENDING 31 31 mmHUBPREQ0_DCSURF_FLIP_CONTROL2 0 0x58f 3 0 2 SURFACE_UPDATE_FLIP_PENDING_MIN_TIME 0 7 SURFACE_UPDATE_PENDING_HIGH_EXTEND_ENABLE 12 12 SURFACE_FLIP_PENDING_HIGH_EXTEND_ENABLE 13 13 mmHUBPREQ0_DCSURF_FRAME_PACING_CONTROL 0 0x590 4 0 2 SURFACE_FRAME_PACING_ENABLE 0 0 SURFACE_FRAME_PACING_MODE 1 1 SURFACE_FRAME_PACING_QUEUE_RESET 8 8 SURFACE_FRAME_PACING_QUEUE_FREE_ENTRY 24 26 mmHUBPREQ0_DCSURF_FRAME_PACING_TIME 0 0x591 1 0 2 SURFACE_FRAME_PACING_TIME 0 31 mmHUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT 0 0x592 10 0 2 SURFACE_FLIP_INT_MASK 0 0 SURFACE_FLIP_INT_TYPE 1 1 SURFACE_FLIP_AWAY_INT_MASK 2 2 SURFACE_FLIP_AWAY_INT_TYPE 3 3 SURFACE_FLIP_CLEAR 8 8 SURFACE_FLIP_AWAY_CLEAR 9 9 SURFACE_FLIP_OCCURRED 16 16 SURFACE_FLIP_INT_STATUS 17 17 SURFACE_FLIP_AWAY_OCCURRED 18 18 SURFACE_FLIP_AWAY_INT_STATUS 19 19 mmHUBPREQ0_DCSURF_SURFACE_INUSE 0 0x593 1 0 2 SURFACE_INUSE_ADDRESS 0 31 mmHUBPREQ0_DCSURF_SURFACE_INUSE_HIGH 0 0x594 1 0 2 SURFACE_INUSE_ADDRESS_HIGH 0 15 mmHUBPREQ0_DCSURF_SURFACE_INUSE_C 0 0x595 1 0 2 SURFACE_INUSE_ADDRESS_C 0 31 mmHUBPREQ0_DCSURF_SURFACE_INUSE_HIGH_C 0 0x596 1 0 2 SURFACE_INUSE_ADDRESS_HIGH_C 0 15 mmHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE 0 0x597 1 0 2 SURFACE_EARLIEST_INUSE_ADDRESS 0 31 mmHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH 0 0x598 1 0 2 SURFACE_EARLIEST_INUSE_ADDRESS_HIGH 0 15 mmHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_C 0 0x599 1 0 2 SURFACE_EARLIEST_INUSE_ADDRESS_C 0 31 mmHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C 0 0x59a 1 0 2 SURFACE_EARLIEST_INUSE_ADDRESS_HIGH_C 0 15 mmHUBPREQ0_DCN_EXPANSION_MODE 0 0x59b 4 0 2 DRQ_EXPANSION_MODE 0 1 CRQ_EXPANSION_MODE 2 3 MRQ_EXPANSION_MODE 4 5 PRQ_EXPANSION_MODE 6 7 mmHUBPREQ0_DCN_TTU_QOS_WM 0 0x59c 2 0 2 QoS_LEVEL_LOW_WM 0 13 QoS_LEVEL_HIGH_WM 16 29 mmHUBPREQ0_DCN_GLOBAL_TTU_CNTL 0 0x59d 2 0 2 MIN_TTU_VBLANK 0 23 QoS_LEVEL_FLIP 28 31 mmHUBPREQ0_DCN_SURF0_TTU_CNTL0 0 0x59e 3 0 2 REFCYC_PER_REQ_DELIVERY 0 22 QoS_LEVEL_FIXED 24 27 QoS_RAMP_DISABLE 28 28 mmHUBPREQ0_DCN_SURF0_TTU_CNTL1 0 0x59f 1 0 2 REFCYC_PER_REQ_DELIVERY_PRE 0 22 mmHUBPREQ0_DCN_SURF1_TTU_CNTL0 0 0x5a0 3 0 2 REFCYC_PER_REQ_DELIVERY 0 22 QoS_LEVEL_FIXED 24 27 QoS_RAMP_DISABLE 28 28 mmHUBPREQ0_DCN_SURF1_TTU_CNTL1 0 0x5a1 1 0 2 REFCYC_PER_REQ_DELIVERY_PRE 0 22 mmHUBPREQ0_DCN_CUR0_TTU_CNTL0 0 0x5a2 3 0 2 REFCYC_PER_REQ_DELIVERY 0 22 QoS_LEVEL_FIXED 24 27 QoS_RAMP_DISABLE 28 28 mmHUBPREQ0_DCN_CUR0_TTU_CNTL1 0 0x5a3 1 0 2 REFCYC_PER_REQ_DELIVERY_PRE 0 22 mmHUBPREQ0_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_LSB 0 0x5a4 1 0 2 MC_VM_SYSTEM_APERTURE_LOW_ADDR_LSB 0 31 mmHUBPREQ0_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_MSB 0 0x5a5 1 0 2 MC_VM_SYSTEM_APERTURE_LOW_ADDR_MSB 0 3 mmHUBPREQ0_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_LSB 0 0x5a6 1 0 2 MC_VM_SYSTEM_APERTURE_HIGH_ADDR_LSB 0 31 mmHUBPREQ0_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_MSB 0 0x5a7 1 0 2 MC_VM_SYSTEM_APERTURE_HIGH_ADDR_MSB 0 3 mmHUBPREQ0_DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB 0 0x5a8 1 0 2 MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB 0 31 mmHUBPREQ0_DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB 0 0x5a9 3 0 2 MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB 0 3 MC_VM_SYSTEM_APERTURE_DEFAULT_SYSTEM 28 28 MC_VM_SYSTEM_APERTURE_DEFAULT_SNOOP 29 29 mmHUBPREQ0_DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_LSB 0 0x5aa 1 0 2 VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_LSB 0 31 mmHUBPREQ0_DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB 0 0x5ab 4 0 2 VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB 0 3 VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_SYSTEM 28 28 VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_SNOOP 29 29 VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_TMZ 30 30 mmHUBPREQ0_DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LSB 0 0x5ac 1 0 2 VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LSB 0 31 mmHUBPREQ0_DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_MSB 0 0x5ad 1 0 2 VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_MSB 0 31 mmHUBPREQ0_DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LSB 0 0x5ae 1 0 2 VM_CONTEXT0_PAGE_TABLE_START_ADDR_LSB 0 31 mmHUBPREQ0_DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_MSB 0 0x5af 1 0 2 VM_CONTEXT0_PAGE_TABLE_START_ADDR_MSB 0 3 mmHUBPREQ0_DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LSB 0 0x5b0 1 0 2 VM_CONTEXT0_PAGE_TABLE_END_ADDR_LSB 0 31 mmHUBPREQ0_DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_MSB 0 0x5b1 1 0 2 VM_CONTEXT0_PAGE_TABLE_END_ADDR_MSB 0 3 mmHUBPREQ0_DCN_VM_CONTEXT0_STATUS 0 0x5b2 4 0 2 DCN_VM_CONTEXT0_ERROR_STATUS 0 15 DCN_VM_CONTEXT0_PROTECTION_FAULT_ADDR_MSB 24 27 DCN_VM_CONTEXT0_ERROR_STATUS_MODE 30 30 DCN_VM_CONTEXT0_ERROR_STATUS_CLEAR 31 31 mmHUBPREQ0_DCN_VM_CONTEXT0_PROTECTION_FAULT_ADDR_LSB 0 0x5b3 1 0 2 DCN_VM_CONTEXT0_PROTECTION_FAULT_ADDR_LSB 0 31 mmHUBPREQ0_DCN_VM_CONTEXT0_CNTL 0 0x5b4 7 0 2 PAGE_TABLE_DEPTH 1 2 RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT 3 3 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT 4 4 VALID_PROTECTION_FAULT_ENABLE_INTERRUPT 12 12 VALID_PROTECTION_FAULT_ENABLE_DEFAULT 13 13 READ_PROTECTION_FAULT_ENABLE_INTERRUPT 15 15 READ_PROTECTION_FAULT_ENABLE_DEFAULT 16 16 mmHUBPREQ0_DCN_VM_MX_L1_TLB_CNTL 0 0x5b5 2 0 2 ENABLE_L1_TLB 0 0 SYSTEM_ACCESS_MODE 3 4 mmHUBPREQ0_BLANK_OFFSET_0 0 0x5b6 2 0 2 REFCYC_H_BLANK_END 0 12 DLG_V_BLANK_END 16 30 mmHUBPREQ0_BLANK_OFFSET_1 0 0x5b7 1 0 2 MIN_DST_Y_NEXT_START 0 17 mmHUBPREQ0_DST_DIMENSIONS 0 0x5b8 1 0 2 REFCYC_PER_HTOTAL 0 20 mmHUBPREQ0_DST_AFTER_SCALER 0 0x5b9 2 0 2 REFCYC_X_AFTER_SCALER 0 12 DST_Y_AFTER_SCALER 16 18 mmHUBPREQ0_PREFETCH_SETTINS 0 0x5ba 2 0 2 VRATIO_PREFETCH 0 20 DST_Y_PREFETCH 24 31 mmHUBPREQ0_PREFETCH_SETTINS_C 0 0x5bb 1 0 2 VRATIO_PREFETCH_C 0 20 mmHUBPREQ0_VBLANK_PARAMETERS_0 0 0x5bc 2 0 2 DST_Y_PER_VM_VBLANK 0 4 DST_Y_PER_ROW_VBLANK 8 13 mmHUBPREQ0_VBLANK_PARAMETERS_1 0 0x5bd 1 0 2 REFCYC_PER_PTE_GROUP_VBLANK_L 0 22 mmHUBPREQ0_VBLANK_PARAMETERS_2 0 0x5be 1 0 2 REFCYC_PER_PTE_GROUP_VBLANK_C 0 22 mmHUBPREQ0_VBLANK_PARAMETERS_3 0 0x5bf 1 0 2 REFCYC_PER_META_CHUNK_VBLANK_L 0 22 mmHUBPREQ0_VBLANK_PARAMETERS_4 0 0x5c0 1 0 2 REFCYC_PER_META_CHUNK_VBLANK_C 0 22 mmHUBPREQ0_NOM_PARAMETERS_0 0 0x5c1 1 0 2 DST_Y_PER_PTE_ROW_NOM_L 0 16 mmHUBPREQ0_NOM_PARAMETERS_1 0 0x5c2 1 0 2 REFCYC_PER_PTE_GROUP_NOM_L 0 22 mmHUBPREQ0_NOM_PARAMETERS_2 0 0x5c3 1 0 2 DST_Y_PER_PTE_ROW_NOM_C 0 16 mmHUBPREQ0_NOM_PARAMETERS_3 0 0x5c4 1 0 2 REFCYC_PER_PTE_GROUP_NOM_C 0 22 mmHUBPREQ0_NOM_PARAMETERS_4 0 0x5c5 1 0 2 DST_Y_PER_META_ROW_NOM_L 0 16 mmHUBPREQ0_NOM_PARAMETERS_5 0 0x5c6 1 0 2 REFCYC_PER_META_CHUNK_NOM_L 0 22 mmHUBPREQ0_NOM_PARAMETERS_6 0 0x5c7 1 0 2 DST_Y_PER_META_ROW_NOM_C 0 16 mmHUBPREQ0_NOM_PARAMETERS_7 0 0x5c8 1 0 2 REFCYC_PER_META_CHUNK_NOM_C 0 22 mmHUBPREQ0_PER_LINE_DELIVERY_PRE 0 0x5c9 2 0 2 REFCYC_PER_LINE_DELIVERY_PRE_L 0 12 REFCYC_PER_LINE_DELIVERY_PRE_C 16 28 mmHUBPREQ0_PER_LINE_DELIVERY 0 0x5ca 2 0 2 REFCYC_PER_LINE_DELIVERY_L 0 12 REFCYC_PER_LINE_DELIVERY_C 16 28 mmHUBPREQ0_CURSOR_SETTINS 0 0x5cb 2 0 2 CURSOR0_DST_Y_OFFSET 0 7 CURSOR0_CHUNK_HDL_ADJUST 8 9 mmHUBPREQ0_REF_FREQ_TO_PIX_FREQ 0 0x5cc 1 0 2 REF_FREQ_TO_PIX_FREQ 0 20 mmHUBPREQ0_HUBPREQ_MEM_PWR_CTRL 0 0x5cd 11 0 2 REQ_DPTE_MEM_PWR_FORCE 0 1 REQ_DPTE_MEM_PWR_DIS 2 2 REQ_MPTE_MEM_PWR_FORCE 4 5 REQ_MPTE_MEM_PWR_DIS 6 6 REQ_META_MEM_PWR_FORCE 8 9 REQ_META_MEM_PWR_DIS 10 10 REQ_DPTE_FINE_GRAIN_DIS 16 16 REQ_DPTE_FINE_GRAIN_DIS_C 17 17 REQ_META_FINE_GRAIN_DIS 20 20 REQ_META_FINE_GRAIN_DIS_C 21 21 REQ_MPTE_FINE_GRAIN_DIS 24 24 mmHUBPREQ0_HUBPREQ_MEM_PWR_STATUS 0 0x5ce 3 0 2 REQ_DPTE_MEM_PWR_STATE 0 1 REQ_MPTE_MEM_PWR_STATE 2 3 REQ_META_MEM_PWR_STATE 4 5 mmHUBPRET0_HUBPRET_CONTROL 0 0x5e0 7 0 2 DET_BUF_PLANE1_BASE_ADDRESS 0 11 PACK_3TO2_ELEMENT_DISABLE 12 12 CROSSBAR_SRC_ALPHA 16 17 CROSSBAR_SRC_Y_G 18 19 CROSSBAR_SRC_CB_B 20 21 CROSSBAR_SRC_CR_R 22 23 HUBPRET_CONTROL_SPARE 24 31 mmHUBPRET0_HUBPRET_MEM_PWR_CTRL 0 0x5e1 4 0 2 DET_MEM_PWR_FORCE 0 1 DET_MEM_PWR_DIS 2 2 DET_MEM_PWR_LS_MODE 4 5 HUBPRET_MEM_PWR_CTRL_SPARE 8 31 mmHUBPRET0_HUBPRET_MEM_PWR_STATUS 0 0x5e2 1 0 2 DET_MEM_PWR_STATE 0 1 mmHUBPRET0_HUBPRET_READ_LINE_CTRL0 0 0x5e3 2 0 2 PIPE_READ_LINE_INTERVAL_IN_NONACTIVE 0 15 PIPE_READ_LINE_VBLANK_MAXIMUM 16 29 mmHUBPRET0_HUBPRET_READ_LINE_CTRL1 0 0x5e4 2 0 2 PIPE_READ_LINE_REPORTED_WHEN_REQ_DISABLED 0 13 HUBPRET_READ_LINE_CTRL1_SPARE 16 31 mmHUBPRET0_HUBPRET_READ_LINE0 0 0x5e5 2 0 2 PIPE_READ_LINE0_START 0 13 PIPE_READ_LINE0_END 16 29 mmHUBPRET0_HUBPRET_READ_LINE1 0 0x5e6 2 0 2 PIPE_READ_LINE1_START 0 13 PIPE_READ_LINE1_END 16 29 mmHUBPRET0_HUBPRET_INTERRUPT 0 0x5e7 15 0 2 PIPE_VBLANK_INT_MASK 0 0 PIPE_READ_LINE0_INT_MASK 1 1 PIPE_READ_LINE1_INT_MASK 2 2 PIPE_VBLANK_INT_TYPE 4 4 PIPE_READ_LINE0_INT_TYPE 5 5 PIPE_READ_LINE1_INT_TYPE 6 6 PIPE_VBLANK_INT_CLEAR 8 8 PIPE_READ_LINE0_INT_CLEAR 9 9 PIPE_READ_LINE1_INT_CLEAR 10 10 PIPE_VBLANK_STATUS 12 12 PIPE_READ_LINE0_STATUS 13 13 PIPE_READ_LINE1_STATUS 14 14 PIPE_VBLANK_INT_STATUS 16 16 PIPE_READ_LINE0_INT_STATUS 17 17 PIPE_READ_LINE1_INT_STATUS 18 18 mmHUBPRET0_HUBPRET_READ_LINE_VALUE 0 0x5e8 2 0 2 PIPE_READ_LINE 0 13 PIPE_READ_LINE_SNAPSHOT 16 29 mmHUBPRET0_HUBPRET_READ_LINE_STATUS 0 0x5e9 5 0 2 PIPE_READ_VBLANK 0 0 PIPE_READ_LINE0_INSIDE 4 4 PIPE_READ_LINE0_OUTSIDE 5 5 PIPE_READ_LINE1_INSIDE 8 8 PIPE_READ_LINE1_OUTSIDE 10 10 mmCURSOR0_CURSOR_CONTROL 0 0x5ec 9 0 2 CURSOR_ENABLE 0 0 CURSOR_MODE 8 9 CURSOR_SNOOP 13 13 CURSOR_SYSTEM 14 14 CURSOR_PITCH 16 17 CURSOR_XY_POSITION_ROTATION_AND_MIRRORING_BYPASS 20 20 CURSOR_LINES_PER_CHUNK 24 28 CURSOR_PERFMON_LATENCY_MEASURE_EN 30 30 CURSOR_PERFMON_LATENCY_MEASURE_SEL 31 31 mmCURSOR0_CURSOR_SURFACE_ADDRESS 0 0x5ed 1 0 2 CURSOR_SURFACE_ADDRESS 0 31 mmCURSOR0_CURSOR_SURFACE_ADDRESS_HIGH 0 0x5ee 1 0 2 CURSOR_SURFACE_ADDRESS_HIGH 0 15 mmCURSOR0_CURSOR_SIZE 0 0x5ef 2 0 2 CURSOR_HEIGHT 0 8 CURSOR_WIDTH 16 24 mmCURSOR0_CURSOR_POSITION 0 0x5f0 2 0 2 CURSOR_Y_POSITION 0 13 CURSOR_X_POSITION 16 29 mmCURSOR0_CURSOR_HOT_SPOT 0 0x5f1 2 0 2 CURSOR_HOT_SPOT_Y 0 7 CURSOR_HOT_SPOT_X 16 23 mmCURSOR0_CURSOR_STEREO_CONTROL 0 0x5f2 3 0 2 CURSOR_STEREO_EN 0 0 CURSOR_PRIMARY_OFFSET 4 17 CURSOR_SECONDARY_OFFSET 18 31 mmCURSOR0_CURSOR_DST_OFFSET 0 0x5f3 1 0 2 CURSOR_DST_X_OFFSET 0 12 mmCURSOR0_CURSOR_MEM_PWR_CTRL 0 0x5f4 3 0 2 CROB_MEM_PWR_FORCE 0 1 CROB_MEM_PWR_DIS 2 2 CROB_MEM_PWR_LS_MODE 4 5 mmCURSOR0_CURSOR_MEM_PWR_STATUS 0 0x5f5 1 0 2 CROB_MEM_PWR_STATE 0 1 mmDC_PERFMON8_PERFCOUNTER_CNTL 0 0x611 11 0 2 PERFCOUNTER_EVENT_SEL 0 8 PERFCOUNTER_CVALUE_SEL 9 11 PERFCOUNTER_INC_MODE 12 14 PERFCOUNTER_HW_CNTL_SEL 15 15 PERFCOUNTER_RUNEN_MODE 16 16 PERFCOUNTER_CNTOFF_START_DIS 22 22 PERFCOUNTER_RESTART_EN 23 23 PERFCOUNTER_INT_EN 24 24 PERFCOUNTER_OFF_MASK 25 25 PERFCOUNTER_ACTIVE 26 26 PERFCOUNTER_CNTL_SEL 29 31 mmDC_PERFMON8_PERFCOUNTER_CNTL2 0 0x612 5 0 2 PERFCOUNTER_COUNTED_VALUE_TYPE 0 1 PERFCOUNTER_HW_STOP1_SEL 2 2 PERFCOUNTER_HW_STOP2_SEL 3 3 PERFCOUNTER_CNTOFF_SEL 8 13 PERFCOUNTER_CNTL2_SEL 29 31 mmDC_PERFMON8_PERFCOUNTER_STATE 0 0x613 16 0 2 PERFCOUNTER_CNT0_STATE 0 1 PERFCOUNTER_STATE_SEL0 2 2 PERFCOUNTER_CNT1_STATE 4 5 PERFCOUNTER_STATE_SEL1 6 6 PERFCOUNTER_CNT2_STATE 8 9 PERFCOUNTER_STATE_SEL2 10 10 PERFCOUNTER_CNT3_STATE 12 13 PERFCOUNTER_STATE_SEL3 14 14 PERFCOUNTER_CNT4_STATE 16 17 PERFCOUNTER_STATE_SEL4 18 18 PERFCOUNTER_CNT5_STATE 20 21 PERFCOUNTER_STATE_SEL5 22 22 PERFCOUNTER_CNT6_STATE 24 25 PERFCOUNTER_STATE_SEL6 26 26 PERFCOUNTER_CNT7_STATE 28 29 PERFCOUNTER_STATE_SEL7 30 30 mmDC_PERFMON8_PERFMON_CNTL 0 0x614 6 0 2 PERFMON_STATE 0 1 PERFMON_RPT_COUNT 8 27 PERFMON_CNTOFF_AND_OR 28 28 PERFMON_CNTOFF_INT_EN 29 29 PERFMON_CNTOFF_INT_STATUS 30 30 PERFMON_CNTOFF_INT_ACK 31 31 mmDC_PERFMON8_PERFMON_CNTL2 0 0x615 4 0 2 PERFMON_CNTOFF_INT_TYPE 0 0 PERFMON_CLK_ENABLE 1 1 PERFMON_RUN_ENABLE_START_SEL 2 9 PERFMON_RUN_ENABLE_STOP_SEL 10 17 mmDC_PERFMON8_PERFMON_CVALUE_INT_MISC 0 0x616 17 0 2 PERFCOUNTER_INT0_STATUS 0 0 PERFCOUNTER_INT1_STATUS 1 1 PERFCOUNTER_INT2_STATUS 2 2 PERFCOUNTER_INT3_STATUS 3 3 PERFCOUNTER_INT4_STATUS 4 4 PERFCOUNTER_INT5_STATUS 5 5 PERFCOUNTER_INT6_STATUS 6 6 PERFCOUNTER_INT7_STATUS 7 7 PERFCOUNTER_INT0_ACK 8 8 PERFCOUNTER_INT1_ACK 9 9 PERFCOUNTER_INT2_ACK 10 10 PERFCOUNTER_INT3_ACK 11 11 PERFCOUNTER_INT4_ACK 12 12 PERFCOUNTER_INT5_ACK 13 13 PERFCOUNTER_INT6_ACK 14 14 PERFCOUNTER_INT7_ACK 15 15 PERFMON_CVALUE_HI 16 31 mmDC_PERFMON8_PERFMON_CVALUE_LOW 0 0x617 1 0 2 PERFMON_CVALUE_LOW 0 31 mmDC_PERFMON8_PERFMON_HI 0 0x618 2 0 2 PERFMON_HI 0 15 PERFMON_READ_SEL 29 31 mmDC_PERFMON8_PERFMON_LOW 0 0x619 1 0 2 PERFMON_LOW 0 31 mmHUBP1_DCSURF_SURFACE_CONFIG 0 0x61d 3 0 2 SURFACE_PIXEL_FORMAT 0 6 ROTATION_ANGLE 8 9 H_MIRROR_EN 10 10 mmHUBP1_DCSURF_ADDR_CONFIG 0 0x61e 6 0 2 NUM_PIPES 0 2 NUM_BANKS 3 5 PIPE_INTERLEAVE 6 7 NUM_SE 8 9 NUM_RB_PER_SE 10 11 MAX_COMPRESSED_FRAGS 12 13 mmHUBP1_DCSURF_TILING_CONFIG 0 0x61f 5 0 2 SW_MODE 0 4 DIM_TYPE 7 8 META_LINEAR 9 9 RB_ALIGNED 10 10 PIPE_ALIGNED 11 11 mmHUBP1_DCSURF_PRI_VIEWPORT_START 0 0x620 2 0 2 PRI_VIEWPORT_X_START 0 13 PRI_VIEWPORT_Y_START 16 29 mmHUBP1_DCSURF_PRI_VIEWPORT_DIMENSION 0 0x621 2 0 2 PRI_VIEWPORT_WIDTH 0 13 PRI_VIEWPORT_HEIGHT 16 29 mmHUBP1_DCSURF_PRI_VIEWPORT_START_C 0 0x622 2 0 2 PRI_VIEWPORT_X_START_C 0 13 PRI_VIEWPORT_Y_START_C 16 29 mmHUBP1_DCSURF_PRI_VIEWPORT_DIMENSION_C 0 0x623 2 0 2 PRI_VIEWPORT_WIDTH_C 0 13 PRI_VIEWPORT_HEIGHT_C 16 29 mmHUBP1_DCSURF_SEC_VIEWPORT_START 0 0x624 2 0 2 SEC_VIEWPORT_X_START 0 13 SEC_VIEWPORT_Y_START 16 29 mmHUBP1_DCSURF_SEC_VIEWPORT_DIMENSION 0 0x625 2 0 2 SEC_VIEWPORT_WIDTH 0 13 SEC_VIEWPORT_HEIGHT 16 29 mmHUBP1_DCSURF_SEC_VIEWPORT_START_C 0 0x626 2 0 2 SEC_VIEWPORT_X_START_C 0 13 SEC_VIEWPORT_Y_START_C 16 29 mmHUBP1_DCSURF_SEC_VIEWPORT_DIMENSION_C 0 0x627 2 0 2 SEC_VIEWPORT_WIDTH_C 0 13 SEC_VIEWPORT_HEIGHT_C 16 29 mmHUBP1_DCHUBP_REQ_SIZE_CONFIG 0 0x628 8 0 2 SWATH_HEIGHT 0 2 PTE_ROW_HEIGHT_LINEAR 4 6 CHUNK_SIZE 8 10 MIN_CHUNK_SIZE 11 12 META_CHUNK_SIZE 16 17 MIN_META_CHUNK_SIZE 18 19 DPTE_GROUP_SIZE 20 22 MPTE_GROUP_SIZE 24 26 mmHUBP1_DCHUBP_REQ_SIZE_CONFIG_C 0 0x629 8 0 2 SWATH_HEIGHT_C 0 2 PTE_ROW_HEIGHT_LINEAR_C 4 6 CHUNK_SIZE_C 8 10 MIN_CHUNK_SIZE_C 11 12 META_CHUNK_SIZE_C 16 17 MIN_META_CHUNK_SIZE_C 18 19 DPTE_GROUP_SIZE_C 20 22 MPTE_GROUP_SIZE_C 24 26 mmHUBP1_DCHUBP_CNTL 0 0x62a 9 0 2 HUBP_BLANK_EN 0 0 HUBP_NO_OUTSTANDING_REQ 1 1 HUBP_DISABLE 2 2 HUBP_IN_BLANK 3 3 HUBP_VTG_SEL 4 7 HUBP_TTU_DISABLE 12 12 HUBP_TTU_MODE 13 15 HUBP_UNDERFLOW_STATUS 28 30 HUBP_UNDERFLOW_CLEAR 31 31 mmHUBP1_HUBP_CLK_CNTL 0 0x62b 10 0 2 HUBP_CLOCK_ENABLE 0 0 HUBP_DISPCLK_R_GATE_DIS 4 4 HUBP_DPPCLK_G_GATE_DIS 8 8 HUBP_DCFCLK_R_GATE_DIS 12 12 HUBP_DCFCLK_G_GATE_DIS 16 16 HUBP_DISPCLK_R_CLOCK_ON 20 20 HUBP_DPPCLK_G_CLOCK_ON 21 21 HUBP_DCFCLK_R_CLOCK_ON 22 22 HUBP_DCFCLK_G_CLOCK_ON 23 23 HUBP_TEST_CLK_SEL 28 31 mmHUBP1_DCHUBP_VMPG_CONFIG 0 0x62c 1 0 2 VMPG_SIZE 0 0 mmHUBP1_HUBPREQ_DEBUG_DB 0 0x62d 1 0 2 HUBPREQ_DEBUG 0 31 mmHUBP1_HUBPREQ_DEBUG 0 0x62e 0 0 2 mmHUBP1_HUBP_MEASURE_WIN_CTRL_DCFCLK 0 0x632 5 0 2 HUBP_MEASURE_WIN_EN_DCFCLK 0 0 HUBP_MEASURE_WIN_PERIOD_M1_DCFCLK 4 11 HUBP_PERFMON_START_SEL_DCFCLK 12 16 HUBP_PERFMON_STOP_SEL_DCFCLK 20 24 HUBP_MEASURE_WIN_MODE_DCFCLK 28 29 mmHUBP1_HUBP_MEASURE_WIN_CTRL_DPPCLK 0 0x633 5 0 2 HUBP_MEASURE_WIN_EN_DPPCLK 0 0 HUBP_MEASURE_WIN_SRC_SEL_DPPCLK 1 1 HUBP_MEASURE_WIN_PERIOD_M1_DPPCLK 4 11 HUBP_PERFMON_START_SEL_DPPCLK 12 16 HUBP_PERFMON_STOP_SEL_DPPCLK 20 24 mmHUBPREQ1_DCSURF_SURFACE_PITCH 0 0x63f 2 0 2 PITCH 0 13 META_PITCH 16 29 mmHUBPREQ1_DCSURF_SURFACE_PITCH_C 0 0x640 2 0 2 PITCH_C 0 13 META_PITCH_C 16 29 mmHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS 0 0x641 1 0 2 PRIMARY_SURFACE_ADDRESS 0 31 mmHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH 0 0x642 1 0 2 PRIMARY_SURFACE_ADDRESS_HIGH 0 15 mmHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_C 0 0x643 1 0 2 PRIMARY_SURFACE_ADDRESS_C 0 31 mmHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C 0 0x644 1 0 2 PRIMARY_SURFACE_ADDRESS_HIGH_C 0 15 mmHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS 0 0x645 1 0 2 SECONDARY_SURFACE_ADDRESS 0 31 mmHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH 0 0x646 1 0 2 SECONDARY_SURFACE_ADDRESS_HIGH 0 15 mmHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_C 0 0x647 1 0 2 SECONDARY_SURFACE_ADDRESS_C 0 31 mmHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C 0 0x648 1 0 2 SECONDARY_SURFACE_ADDRESS_HIGH_C 0 15 mmHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS 0 0x649 1 0 2 PRIMARY_META_SURFACE_ADDRESS 0 31 mmHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH 0 0x64a 1 0 2 PRIMARY_META_SURFACE_ADDRESS_HIGH 0 15 mmHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C 0 0x64b 1 0 2 PRIMARY_META_SURFACE_ADDRESS_C 0 31 mmHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C 0 0x64c 1 0 2 PRIMARY_META_SURFACE_ADDRESS_HIGH_C 0 15 mmHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS 0 0x64d 1 0 2 SECONDARY_META_SURFACE_ADDRESS 0 31 mmHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH 0 0x64e 1 0 2 SECONDARY_META_SURFACE_ADDRESS_HIGH 0 15 mmHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C 0 0x64f 1 0 2 SECONDARY_META_SURFACE_ADDRESS_C 0 31 mmHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C 0 0x650 1 0 2 SECONDARY_META_SURFACE_ADDRESS_HIGH_C 0 15 mmHUBPREQ1_DCSURF_SURFACE_CONTROL 0 0x651 6 0 2 PRIMARY_SURFACE_DCC_EN 1 1 PRIMARY_SURFACE_DCC_IND_64B_BLK 2 2 PRIMARY_SURFACE_DCC_IND_64B_BLK_C 5 5 SECONDARY_SURFACE_DCC_EN 9 9 SECONDARY_SURFACE_DCC_IND_64B_BLK 10 10 SECONDARY_SURFACE_DCC_IND_64B_BLK_C 13 13 mmHUBPREQ1_DCSURF_FLIP_CONTROL 0 0x652 10 0 2 SURFACE_UPDATE_LOCK 0 0 SURFACE_FLIP_TYPE 1 1 SURFACE_FLIP_VUPDATE_SKIP_NUM 4 7 SURFACE_FLIP_MODE_FOR_STEREOSYNC 12 13 SURFACE_FLIP_IN_STEREOSYNC 16 16 SURFACE_FLIP_STEREO_SELECT_DISABLE 17 17 SURFACE_FLIP_STEREO_SELECT_POLARITY 18 18 SURFACE_FLIP_PENDING_DELAY 20 29 SURFACE_UPDATE_PENDING 30 30 SURFACE_FLIP_PENDING 31 31 mmHUBPREQ1_DCSURF_FLIP_CONTROL2 0 0x653 3 0 2 SURFACE_UPDATE_FLIP_PENDING_MIN_TIME 0 7 SURFACE_UPDATE_PENDING_HIGH_EXTEND_ENABLE 12 12 SURFACE_FLIP_PENDING_HIGH_EXTEND_ENABLE 13 13 mmHUBPREQ1_DCSURF_FRAME_PACING_CONTROL 0 0x654 4 0 2 SURFACE_FRAME_PACING_ENABLE 0 0 SURFACE_FRAME_PACING_MODE 1 1 SURFACE_FRAME_PACING_QUEUE_RESET 8 8 SURFACE_FRAME_PACING_QUEUE_FREE_ENTRY 24 26 mmHUBPREQ1_DCSURF_FRAME_PACING_TIME 0 0x655 1 0 2 SURFACE_FRAME_PACING_TIME 0 31 mmHUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT 0 0x656 10 0 2 SURFACE_FLIP_INT_MASK 0 0 SURFACE_FLIP_INT_TYPE 1 1 SURFACE_FLIP_AWAY_INT_MASK 2 2 SURFACE_FLIP_AWAY_INT_TYPE 3 3 SURFACE_FLIP_CLEAR 8 8 SURFACE_FLIP_AWAY_CLEAR 9 9 SURFACE_FLIP_OCCURRED 16 16 SURFACE_FLIP_INT_STATUS 17 17 SURFACE_FLIP_AWAY_OCCURRED 18 18 SURFACE_FLIP_AWAY_INT_STATUS 19 19 mmHUBPREQ1_DCSURF_SURFACE_INUSE 0 0x657 1 0 2 SURFACE_INUSE_ADDRESS 0 31 mmHUBPREQ1_DCSURF_SURFACE_INUSE_HIGH 0 0x658 1 0 2 SURFACE_INUSE_ADDRESS_HIGH 0 15 mmHUBPREQ1_DCSURF_SURFACE_INUSE_C 0 0x659 1 0 2 SURFACE_INUSE_ADDRESS_C 0 31 mmHUBPREQ1_DCSURF_SURFACE_INUSE_HIGH_C 0 0x65a 1 0 2 SURFACE_INUSE_ADDRESS_HIGH_C 0 15 mmHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE 0 0x65b 1 0 2 SURFACE_EARLIEST_INUSE_ADDRESS 0 31 mmHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_HIGH 0 0x65c 1 0 2 SURFACE_EARLIEST_INUSE_ADDRESS_HIGH 0 15 mmHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_C 0 0x65d 1 0 2 SURFACE_EARLIEST_INUSE_ADDRESS_C 0 31 mmHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C 0 0x65e 1 0 2 SURFACE_EARLIEST_INUSE_ADDRESS_HIGH_C 0 15 mmHUBPREQ1_DCN_EXPANSION_MODE 0 0x65f 4 0 2 DRQ_EXPANSION_MODE 0 1 CRQ_EXPANSION_MODE 2 3 MRQ_EXPANSION_MODE 4 5 PRQ_EXPANSION_MODE 6 7 mmHUBPREQ1_DCN_TTU_QOS_WM 0 0x660 2 0 2 QoS_LEVEL_LOW_WM 0 13 QoS_LEVEL_HIGH_WM 16 29 mmHUBPREQ1_DCN_GLOBAL_TTU_CNTL 0 0x661 2 0 2 MIN_TTU_VBLANK 0 23 QoS_LEVEL_FLIP 28 31 mmHUBPREQ1_DCN_SURF0_TTU_CNTL0 0 0x662 3 0 2 REFCYC_PER_REQ_DELIVERY 0 22 QoS_LEVEL_FIXED 24 27 QoS_RAMP_DISABLE 28 28 mmHUBPREQ1_DCN_SURF0_TTU_CNTL1 0 0x663 1 0 2 REFCYC_PER_REQ_DELIVERY_PRE 0 22 mmHUBPREQ1_DCN_SURF1_TTU_CNTL0 0 0x664 3 0 2 REFCYC_PER_REQ_DELIVERY 0 22 QoS_LEVEL_FIXED 24 27 QoS_RAMP_DISABLE 28 28 mmHUBPREQ1_DCN_SURF1_TTU_CNTL1 0 0x665 1 0 2 REFCYC_PER_REQ_DELIVERY_PRE 0 22 mmHUBPREQ1_DCN_CUR0_TTU_CNTL0 0 0x666 3 0 2 REFCYC_PER_REQ_DELIVERY 0 22 QoS_LEVEL_FIXED 24 27 QoS_RAMP_DISABLE 28 28 mmHUBPREQ1_DCN_CUR0_TTU_CNTL1 0 0x667 1 0 2 REFCYC_PER_REQ_DELIVERY_PRE 0 22 mmHUBPREQ1_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_LSB 0 0x668 1 0 2 MC_VM_SYSTEM_APERTURE_LOW_ADDR_LSB 0 31 mmHUBPREQ1_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_MSB 0 0x669 1 0 2 MC_VM_SYSTEM_APERTURE_LOW_ADDR_MSB 0 3 mmHUBPREQ1_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_LSB 0 0x66a 1 0 2 MC_VM_SYSTEM_APERTURE_HIGH_ADDR_LSB 0 31 mmHUBPREQ1_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_MSB 0 0x66b 1 0 2 MC_VM_SYSTEM_APERTURE_HIGH_ADDR_MSB 0 3 mmHUBPREQ1_DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB 0 0x66c 1 0 2 MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB 0 31 mmHUBPREQ1_DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB 0 0x66d 3 0 2 MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB 0 3 MC_VM_SYSTEM_APERTURE_DEFAULT_SYSTEM 28 28 MC_VM_SYSTEM_APERTURE_DEFAULT_SNOOP 29 29 mmHUBPREQ1_DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_LSB 0 0x66e 1 0 2 VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_LSB 0 31 mmHUBPREQ1_DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB 0 0x66f 4 0 2 VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB 0 3 VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_SYSTEM 28 28 VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_SNOOP 29 29 VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_TMZ 30 30 mmHUBPREQ1_DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LSB 0 0x670 1 0 2 VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LSB 0 31 mmHUBPREQ1_DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_MSB 0 0x671 1 0 2 VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_MSB 0 31 mmHUBPREQ1_DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LSB 0 0x672 1 0 2 VM_CONTEXT0_PAGE_TABLE_START_ADDR_LSB 0 31 mmHUBPREQ1_DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_MSB 0 0x673 1 0 2 VM_CONTEXT0_PAGE_TABLE_START_ADDR_MSB 0 3 mmHUBPREQ1_DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LSB 0 0x674 1 0 2 VM_CONTEXT0_PAGE_TABLE_END_ADDR_LSB 0 31 mmHUBPREQ1_DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_MSB 0 0x675 1 0 2 VM_CONTEXT0_PAGE_TABLE_END_ADDR_MSB 0 3 mmHUBPREQ1_DCN_VM_CONTEXT0_STATUS 0 0x676 4 0 2 DCN_VM_CONTEXT0_ERROR_STATUS 0 15 DCN_VM_CONTEXT0_PROTECTION_FAULT_ADDR_MSB 24 27 DCN_VM_CONTEXT0_ERROR_STATUS_MODE 30 30 DCN_VM_CONTEXT0_ERROR_STATUS_CLEAR 31 31 mmHUBPREQ1_DCN_VM_CONTEXT0_PROTECTION_FAULT_ADDR_LSB 0 0x677 1 0 2 DCN_VM_CONTEXT0_PROTECTION_FAULT_ADDR_LSB 0 31 mmHUBPREQ1_DCN_VM_CONTEXT0_CNTL 0 0x678 7 0 2 PAGE_TABLE_DEPTH 1 2 RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT 3 3 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT 4 4 VALID_PROTECTION_FAULT_ENABLE_INTERRUPT 12 12 VALID_PROTECTION_FAULT_ENABLE_DEFAULT 13 13 READ_PROTECTION_FAULT_ENABLE_INTERRUPT 15 15 READ_PROTECTION_FAULT_ENABLE_DEFAULT 16 16 mmHUBPREQ1_DCN_VM_MX_L1_TLB_CNTL 0 0x679 2 0 2 ENABLE_L1_TLB 0 0 SYSTEM_ACCESS_MODE 3 4 mmHUBPREQ1_BLANK_OFFSET_0 0 0x67a 2 0 2 REFCYC_H_BLANK_END 0 12 DLG_V_BLANK_END 16 30 mmHUBPREQ1_BLANK_OFFSET_1 0 0x67b 1 0 2 MIN_DST_Y_NEXT_START 0 17 mmHUBPREQ1_DST_DIMENSIONS 0 0x67c 1 0 2 REFCYC_PER_HTOTAL 0 20 mmHUBPREQ1_DST_AFTER_SCALER 0 0x67d 2 0 2 REFCYC_X_AFTER_SCALER 0 12 DST_Y_AFTER_SCALER 16 18 mmHUBPREQ1_PREFETCH_SETTINS 0 0x67e 2 0 2 VRATIO_PREFETCH 0 20 DST_Y_PREFETCH 24 31 mmHUBPREQ1_PREFETCH_SETTINS_C 0 0x67f 1 0 2 VRATIO_PREFETCH_C 0 20 mmHUBPREQ1_VBLANK_PARAMETERS_0 0 0x680 2 0 2 DST_Y_PER_VM_VBLANK 0 4 DST_Y_PER_ROW_VBLANK 8 13 mmHUBPREQ1_VBLANK_PARAMETERS_1 0 0x681 1 0 2 REFCYC_PER_PTE_GROUP_VBLANK_L 0 22 mmHUBPREQ1_VBLANK_PARAMETERS_2 0 0x682 1 0 2 REFCYC_PER_PTE_GROUP_VBLANK_C 0 22 mmHUBPREQ1_VBLANK_PARAMETERS_3 0 0x683 1 0 2 REFCYC_PER_META_CHUNK_VBLANK_L 0 22 mmHUBPREQ1_VBLANK_PARAMETERS_4 0 0x684 1 0 2 REFCYC_PER_META_CHUNK_VBLANK_C 0 22 mmHUBPREQ1_NOM_PARAMETERS_0 0 0x685 1 0 2 DST_Y_PER_PTE_ROW_NOM_L 0 16 mmHUBPREQ1_NOM_PARAMETERS_1 0 0x686 1 0 2 REFCYC_PER_PTE_GROUP_NOM_L 0 22 mmHUBPREQ1_NOM_PARAMETERS_2 0 0x687 1 0 2 DST_Y_PER_PTE_ROW_NOM_C 0 16 mmHUBPREQ1_NOM_PARAMETERS_3 0 0x688 1 0 2 REFCYC_PER_PTE_GROUP_NOM_C 0 22 mmHUBPREQ1_NOM_PARAMETERS_4 0 0x689 1 0 2 DST_Y_PER_META_ROW_NOM_L 0 16 mmHUBPREQ1_NOM_PARAMETERS_5 0 0x68a 1 0 2 REFCYC_PER_META_CHUNK_NOM_L 0 22 mmHUBPREQ1_NOM_PARAMETERS_6 0 0x68b 1 0 2 DST_Y_PER_META_ROW_NOM_C 0 16 mmHUBPREQ1_NOM_PARAMETERS_7 0 0x68c 1 0 2 REFCYC_PER_META_CHUNK_NOM_C 0 22 mmHUBPREQ1_PER_LINE_DELIVERY_PRE 0 0x68d 2 0 2 REFCYC_PER_LINE_DELIVERY_PRE_L 0 12 REFCYC_PER_LINE_DELIVERY_PRE_C 16 28 mmHUBPREQ1_PER_LINE_DELIVERY 0 0x68e 2 0 2 REFCYC_PER_LINE_DELIVERY_L 0 12 REFCYC_PER_LINE_DELIVERY_C 16 28 mmHUBPREQ1_CURSOR_SETTINS 0 0x68f 2 0 2 CURSOR0_DST_Y_OFFSET 0 7 CURSOR0_CHUNK_HDL_ADJUST 8 9 mmHUBPREQ1_REF_FREQ_TO_PIX_FREQ 0 0x690 1 0 2 REF_FREQ_TO_PIX_FREQ 0 20 mmHUBPREQ1_HUBPREQ_MEM_PWR_CTRL 0 0x691 11 0 2 REQ_DPTE_MEM_PWR_FORCE 0 1 REQ_DPTE_MEM_PWR_DIS 2 2 REQ_MPTE_MEM_PWR_FORCE 4 5 REQ_MPTE_MEM_PWR_DIS 6 6 REQ_META_MEM_PWR_FORCE 8 9 REQ_META_MEM_PWR_DIS 10 10 REQ_DPTE_FINE_GRAIN_DIS 16 16 REQ_DPTE_FINE_GRAIN_DIS_C 17 17 REQ_META_FINE_GRAIN_DIS 20 20 REQ_META_FINE_GRAIN_DIS_C 21 21 REQ_MPTE_FINE_GRAIN_DIS 24 24 mmHUBPREQ1_HUBPREQ_MEM_PWR_STATUS 0 0x692 3 0 2 REQ_DPTE_MEM_PWR_STATE 0 1 REQ_MPTE_MEM_PWR_STATE 2 3 REQ_META_MEM_PWR_STATE 4 5 mmHUBPRET1_HUBPRET_CONTROL 0 0x6a4 7 0 2 DET_BUF_PLANE1_BASE_ADDRESS 0 11 PACK_3TO2_ELEMENT_DISABLE 12 12 CROSSBAR_SRC_ALPHA 16 17 CROSSBAR_SRC_Y_G 18 19 CROSSBAR_SRC_CB_B 20 21 CROSSBAR_SRC_CR_R 22 23 HUBPRET_CONTROL_SPARE 24 31 mmHUBPRET1_HUBPRET_MEM_PWR_CTRL 0 0x6a5 4 0 2 DET_MEM_PWR_FORCE 0 1 DET_MEM_PWR_DIS 2 2 DET_MEM_PWR_LS_MODE 4 5 HUBPRET_MEM_PWR_CTRL_SPARE 8 31 mmHUBPRET1_HUBPRET_MEM_PWR_STATUS 0 0x6a6 1 0 2 DET_MEM_PWR_STATE 0 1 mmHUBPRET1_HUBPRET_READ_LINE_CTRL0 0 0x6a7 2 0 2 PIPE_READ_LINE_INTERVAL_IN_NONACTIVE 0 15 PIPE_READ_LINE_VBLANK_MAXIMUM 16 29 mmHUBPRET1_HUBPRET_READ_LINE_CTRL1 0 0x6a8 2 0 2 PIPE_READ_LINE_REPORTED_WHEN_REQ_DISABLED 0 13 HUBPRET_READ_LINE_CTRL1_SPARE 16 31 mmHUBPRET1_HUBPRET_READ_LINE0 0 0x6a9 2 0 2 PIPE_READ_LINE0_START 0 13 PIPE_READ_LINE0_END 16 29 mmHUBPRET1_HUBPRET_READ_LINE1 0 0x6aa 2 0 2 PIPE_READ_LINE1_START 0 13 PIPE_READ_LINE1_END 16 29 mmHUBPRET1_HUBPRET_INTERRUPT 0 0x6ab 15 0 2 PIPE_VBLANK_INT_MASK 0 0 PIPE_READ_LINE0_INT_MASK 1 1 PIPE_READ_LINE1_INT_MASK 2 2 PIPE_VBLANK_INT_TYPE 4 4 PIPE_READ_LINE0_INT_TYPE 5 5 PIPE_READ_LINE1_INT_TYPE 6 6 PIPE_VBLANK_INT_CLEAR 8 8 PIPE_READ_LINE0_INT_CLEAR 9 9 PIPE_READ_LINE1_INT_CLEAR 10 10 PIPE_VBLANK_STATUS 12 12 PIPE_READ_LINE0_STATUS 13 13 PIPE_READ_LINE1_STATUS 14 14 PIPE_VBLANK_INT_STATUS 16 16 PIPE_READ_LINE0_INT_STATUS 17 17 PIPE_READ_LINE1_INT_STATUS 18 18 mmHUBPRET1_HUBPRET_READ_LINE_VALUE 0 0x6ac 2 0 2 PIPE_READ_LINE 0 13 PIPE_READ_LINE_SNAPSHOT 16 29 mmHUBPRET1_HUBPRET_READ_LINE_STATUS 0 0x6ad 5 0 2 PIPE_READ_VBLANK 0 0 PIPE_READ_LINE0_INSIDE 4 4 PIPE_READ_LINE0_OUTSIDE 5 5 PIPE_READ_LINE1_INSIDE 8 8 PIPE_READ_LINE1_OUTSIDE 10 10 mmCURSOR1_CURSOR_CONTROL 0 0x6b0 9 0 2 CURSOR_ENABLE 0 0 CURSOR_MODE 8 9 CURSOR_SNOOP 13 13 CURSOR_SYSTEM 14 14 CURSOR_PITCH 16 17 CURSOR_XY_POSITION_ROTATION_AND_MIRRORING_BYPASS 20 20 CURSOR_LINES_PER_CHUNK 24 28 CURSOR_PERFMON_LATENCY_MEASURE_EN 30 30 CURSOR_PERFMON_LATENCY_MEASURE_SEL 31 31 mmCURSOR1_CURSOR_SURFACE_ADDRESS 0 0x6b1 1 0 2 CURSOR_SURFACE_ADDRESS 0 31 mmCURSOR1_CURSOR_SURFACE_ADDRESS_HIGH 0 0x6b2 1 0 2 CURSOR_SURFACE_ADDRESS_HIGH 0 15 mmCURSOR1_CURSOR_SIZE 0 0x6b3 2 0 2 CURSOR_HEIGHT 0 8 CURSOR_WIDTH 16 24 mmCURSOR1_CURSOR_POSITION 0 0x6b4 2 0 2 CURSOR_Y_POSITION 0 13 CURSOR_X_POSITION 16 29 mmCURSOR1_CURSOR_HOT_SPOT 0 0x6b5 2 0 2 CURSOR_HOT_SPOT_Y 0 7 CURSOR_HOT_SPOT_X 16 23 mmCURSOR1_CURSOR_STEREO_CONTROL 0 0x6b6 3 0 2 CURSOR_STEREO_EN 0 0 CURSOR_PRIMARY_OFFSET 4 17 CURSOR_SECONDARY_OFFSET 18 31 mmCURSOR1_CURSOR_DST_OFFSET 0 0x6b7 1 0 2 CURSOR_DST_X_OFFSET 0 12 mmCURSOR1_CURSOR_MEM_PWR_CTRL 0 0x6b8 3 0 2 CROB_MEM_PWR_FORCE 0 1 CROB_MEM_PWR_DIS 2 2 CROB_MEM_PWR_LS_MODE 4 5 mmCURSOR1_CURSOR_MEM_PWR_STATUS 0 0x6b9 1 0 2 CROB_MEM_PWR_STATE 0 1 mmDC_PERFMON9_PERFCOUNTER_CNTL 0 0x6d5 11 0 2 PERFCOUNTER_EVENT_SEL 0 8 PERFCOUNTER_CVALUE_SEL 9 11 PERFCOUNTER_INC_MODE 12 14 PERFCOUNTER_HW_CNTL_SEL 15 15 PERFCOUNTER_RUNEN_MODE 16 16 PERFCOUNTER_CNTOFF_START_DIS 22 22 PERFCOUNTER_RESTART_EN 23 23 PERFCOUNTER_INT_EN 24 24 PERFCOUNTER_OFF_MASK 25 25 PERFCOUNTER_ACTIVE 26 26 PERFCOUNTER_CNTL_SEL 29 31 mmDC_PERFMON9_PERFCOUNTER_CNTL2 0 0x6d6 5 0 2 PERFCOUNTER_COUNTED_VALUE_TYPE 0 1 PERFCOUNTER_HW_STOP1_SEL 2 2 PERFCOUNTER_HW_STOP2_SEL 3 3 PERFCOUNTER_CNTOFF_SEL 8 13 PERFCOUNTER_CNTL2_SEL 29 31 mmDC_PERFMON9_PERFCOUNTER_STATE 0 0x6d7 16 0 2 PERFCOUNTER_CNT0_STATE 0 1 PERFCOUNTER_STATE_SEL0 2 2 PERFCOUNTER_CNT1_STATE 4 5 PERFCOUNTER_STATE_SEL1 6 6 PERFCOUNTER_CNT2_STATE 8 9 PERFCOUNTER_STATE_SEL2 10 10 PERFCOUNTER_CNT3_STATE 12 13 PERFCOUNTER_STATE_SEL3 14 14 PERFCOUNTER_CNT4_STATE 16 17 PERFCOUNTER_STATE_SEL4 18 18 PERFCOUNTER_CNT5_STATE 20 21 PERFCOUNTER_STATE_SEL5 22 22 PERFCOUNTER_CNT6_STATE 24 25 PERFCOUNTER_STATE_SEL6 26 26 PERFCOUNTER_CNT7_STATE 28 29 PERFCOUNTER_STATE_SEL7 30 30 mmDC_PERFMON9_PERFMON_CNTL 0 0x6d8 6 0 2 PERFMON_STATE 0 1 PERFMON_RPT_COUNT 8 27 PERFMON_CNTOFF_AND_OR 28 28 PERFMON_CNTOFF_INT_EN 29 29 PERFMON_CNTOFF_INT_STATUS 30 30 PERFMON_CNTOFF_INT_ACK 31 31 mmDC_PERFMON9_PERFMON_CNTL2 0 0x6d9 4 0 2 PERFMON_CNTOFF_INT_TYPE 0 0 PERFMON_CLK_ENABLE 1 1 PERFMON_RUN_ENABLE_START_SEL 2 9 PERFMON_RUN_ENABLE_STOP_SEL 10 17 mmDC_PERFMON9_PERFMON_CVALUE_INT_MISC 0 0x6da 17 0 2 PERFCOUNTER_INT0_STATUS 0 0 PERFCOUNTER_INT1_STATUS 1 1 PERFCOUNTER_INT2_STATUS 2 2 PERFCOUNTER_INT3_STATUS 3 3 PERFCOUNTER_INT4_STATUS 4 4 PERFCOUNTER_INT5_STATUS 5 5 PERFCOUNTER_INT6_STATUS 6 6 PERFCOUNTER_INT7_STATUS 7 7 PERFCOUNTER_INT0_ACK 8 8 PERFCOUNTER_INT1_ACK 9 9 PERFCOUNTER_INT2_ACK 10 10 PERFCOUNTER_INT3_ACK 11 11 PERFCOUNTER_INT4_ACK 12 12 PERFCOUNTER_INT5_ACK 13 13 PERFCOUNTER_INT6_ACK 14 14 PERFCOUNTER_INT7_ACK 15 15 PERFMON_CVALUE_HI 16 31 mmDC_PERFMON9_PERFMON_CVALUE_LOW 0 0x6db 1 0 2 PERFMON_CVALUE_LOW 0 31 mmDC_PERFMON9_PERFMON_HI 0 0x6dc 2 0 2 PERFMON_HI 0 15 PERFMON_READ_SEL 29 31 mmDC_PERFMON9_PERFMON_LOW 0 0x6dd 1 0 2 PERFMON_LOW 0 31 mmHUBP2_DCSURF_SURFACE_CONFIG 0 0x6e1 3 0 2 SURFACE_PIXEL_FORMAT 0 6 ROTATION_ANGLE 8 9 H_MIRROR_EN 10 10 mmHUBP2_DCSURF_ADDR_CONFIG 0 0x6e2 6 0 2 NUM_PIPES 0 2 NUM_BANKS 3 5 PIPE_INTERLEAVE 6 7 NUM_SE 8 9 NUM_RB_PER_SE 10 11 MAX_COMPRESSED_FRAGS 12 13 mmHUBP2_DCSURF_TILING_CONFIG 0 0x6e3 5 0 2 SW_MODE 0 4 DIM_TYPE 7 8 META_LINEAR 9 9 RB_ALIGNED 10 10 PIPE_ALIGNED 11 11 mmHUBP2_DCSURF_PRI_VIEWPORT_START 0 0x6e4 2 0 2 PRI_VIEWPORT_X_START 0 13 PRI_VIEWPORT_Y_START 16 29 mmHUBP2_DCSURF_PRI_VIEWPORT_DIMENSION 0 0x6e5 2 0 2 PRI_VIEWPORT_WIDTH 0 13 PRI_VIEWPORT_HEIGHT 16 29 mmHUBP2_DCSURF_PRI_VIEWPORT_START_C 0 0x6e6 2 0 2 PRI_VIEWPORT_X_START_C 0 13 PRI_VIEWPORT_Y_START_C 16 29 mmHUBP2_DCSURF_PRI_VIEWPORT_DIMENSION_C 0 0x6e7 2 0 2 PRI_VIEWPORT_WIDTH_C 0 13 PRI_VIEWPORT_HEIGHT_C 16 29 mmHUBP2_DCSURF_SEC_VIEWPORT_START 0 0x6e8 2 0 2 SEC_VIEWPORT_X_START 0 13 SEC_VIEWPORT_Y_START 16 29 mmHUBP2_DCSURF_SEC_VIEWPORT_DIMENSION 0 0x6e9 2 0 2 SEC_VIEWPORT_WIDTH 0 13 SEC_VIEWPORT_HEIGHT 16 29 mmHUBP2_DCSURF_SEC_VIEWPORT_START_C 0 0x6ea 2 0 2 SEC_VIEWPORT_X_START_C 0 13 SEC_VIEWPORT_Y_START_C 16 29 mmHUBP2_DCSURF_SEC_VIEWPORT_DIMENSION_C 0 0x6eb 2 0 2 SEC_VIEWPORT_WIDTH_C 0 13 SEC_VIEWPORT_HEIGHT_C 16 29 mmHUBP2_DCHUBP_REQ_SIZE_CONFIG 0 0x6ec 8 0 2 SWATH_HEIGHT 0 2 PTE_ROW_HEIGHT_LINEAR 4 6 CHUNK_SIZE 8 10 MIN_CHUNK_SIZE 11 12 META_CHUNK_SIZE 16 17 MIN_META_CHUNK_SIZE 18 19 DPTE_GROUP_SIZE 20 22 MPTE_GROUP_SIZE 24 26 mmHUBP2_DCHUBP_REQ_SIZE_CONFIG_C 0 0x6ed 8 0 2 SWATH_HEIGHT_C 0 2 PTE_ROW_HEIGHT_LINEAR_C 4 6 CHUNK_SIZE_C 8 10 MIN_CHUNK_SIZE_C 11 12 META_CHUNK_SIZE_C 16 17 MIN_META_CHUNK_SIZE_C 18 19 DPTE_GROUP_SIZE_C 20 22 MPTE_GROUP_SIZE_C 24 26 mmHUBP2_DCHUBP_CNTL 0 0x6ee 9 0 2 HUBP_BLANK_EN 0 0 HUBP_NO_OUTSTANDING_REQ 1 1 HUBP_DISABLE 2 2 HUBP_IN_BLANK 3 3 HUBP_VTG_SEL 4 7 HUBP_TTU_DISABLE 12 12 HUBP_TTU_MODE 13 15 HUBP_UNDERFLOW_STATUS 28 30 HUBP_UNDERFLOW_CLEAR 31 31 mmHUBP2_HUBP_CLK_CNTL 0 0x6ef 10 0 2 HUBP_CLOCK_ENABLE 0 0 HUBP_DISPCLK_R_GATE_DIS 4 4 HUBP_DPPCLK_G_GATE_DIS 8 8 HUBP_DCFCLK_R_GATE_DIS 12 12 HUBP_DCFCLK_G_GATE_DIS 16 16 HUBP_DISPCLK_R_CLOCK_ON 20 20 HUBP_DPPCLK_G_CLOCK_ON 21 21 HUBP_DCFCLK_R_CLOCK_ON 22 22 HUBP_DCFCLK_G_CLOCK_ON 23 23 HUBP_TEST_CLK_SEL 28 31 mmHUBP2_DCHUBP_VMPG_CONFIG 0 0x6f0 1 0 2 VMPG_SIZE 0 0 mmHUBP2_HUBPREQ_DEBUG_DB 0 0x6f1 1 0 2 HUBPREQ_DEBUG 0 31 mmHUBP2_HUBPREQ_DEBUG 0 0x6f2 0 0 2 mmHUBP2_HUBP_MEASURE_WIN_CTRL_DCFCLK 0 0x6f6 5 0 2 HUBP_MEASURE_WIN_EN_DCFCLK 0 0 HUBP_MEASURE_WIN_PERIOD_M1_DCFCLK 4 11 HUBP_PERFMON_START_SEL_DCFCLK 12 16 HUBP_PERFMON_STOP_SEL_DCFCLK 20 24 HUBP_MEASURE_WIN_MODE_DCFCLK 28 29 mmHUBP2_HUBP_MEASURE_WIN_CTRL_DPPCLK 0 0x6f7 5 0 2 HUBP_MEASURE_WIN_EN_DPPCLK 0 0 HUBP_MEASURE_WIN_SRC_SEL_DPPCLK 1 1 HUBP_MEASURE_WIN_PERIOD_M1_DPPCLK 4 11 HUBP_PERFMON_START_SEL_DPPCLK 12 16 HUBP_PERFMON_STOP_SEL_DPPCLK 20 24 mmHUBPREQ2_DCSURF_SURFACE_PITCH 0 0x703 2 0 2 PITCH 0 13 META_PITCH 16 29 mmHUBPREQ2_DCSURF_SURFACE_PITCH_C 0 0x704 2 0 2 PITCH_C 0 13 META_PITCH_C 16 29 mmHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS 0 0x705 1 0 2 PRIMARY_SURFACE_ADDRESS 0 31 mmHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH 0 0x706 1 0 2 PRIMARY_SURFACE_ADDRESS_HIGH 0 15 mmHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_C 0 0x707 1 0 2 PRIMARY_SURFACE_ADDRESS_C 0 31 mmHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C 0 0x708 1 0 2 PRIMARY_SURFACE_ADDRESS_HIGH_C 0 15 mmHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS 0 0x709 1 0 2 SECONDARY_SURFACE_ADDRESS 0 31 mmHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH 0 0x70a 1 0 2 SECONDARY_SURFACE_ADDRESS_HIGH 0 15 mmHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_C 0 0x70b 1 0 2 SECONDARY_SURFACE_ADDRESS_C 0 31 mmHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C 0 0x70c 1 0 2 SECONDARY_SURFACE_ADDRESS_HIGH_C 0 15 mmHUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS 0 0x70d 1 0 2 PRIMARY_META_SURFACE_ADDRESS 0 31 mmHUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH 0 0x70e 1 0 2 PRIMARY_META_SURFACE_ADDRESS_HIGH 0 15 mmHUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C 0 0x70f 1 0 2 PRIMARY_META_SURFACE_ADDRESS_C 0 31 mmHUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C 0 0x710 1 0 2 PRIMARY_META_SURFACE_ADDRESS_HIGH_C 0 15 mmHUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS 0 0x711 1 0 2 SECONDARY_META_SURFACE_ADDRESS 0 31 mmHUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH 0 0x712 1 0 2 SECONDARY_META_SURFACE_ADDRESS_HIGH 0 15 mmHUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C 0 0x713 1 0 2 SECONDARY_META_SURFACE_ADDRESS_C 0 31 mmHUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C 0 0x714 1 0 2 SECONDARY_META_SURFACE_ADDRESS_HIGH_C 0 15 mmHUBPREQ2_DCSURF_SURFACE_CONTROL 0 0x715 6 0 2 PRIMARY_SURFACE_DCC_EN 1 1 PRIMARY_SURFACE_DCC_IND_64B_BLK 2 2 PRIMARY_SURFACE_DCC_IND_64B_BLK_C 5 5 SECONDARY_SURFACE_DCC_EN 9 9 SECONDARY_SURFACE_DCC_IND_64B_BLK 10 10 SECONDARY_SURFACE_DCC_IND_64B_BLK_C 13 13 mmHUBPREQ2_DCSURF_FLIP_CONTROL 0 0x716 10 0 2 SURFACE_UPDATE_LOCK 0 0 SURFACE_FLIP_TYPE 1 1 SURFACE_FLIP_VUPDATE_SKIP_NUM 4 7 SURFACE_FLIP_MODE_FOR_STEREOSYNC 12 13 SURFACE_FLIP_IN_STEREOSYNC 16 16 SURFACE_FLIP_STEREO_SELECT_DISABLE 17 17 SURFACE_FLIP_STEREO_SELECT_POLARITY 18 18 SURFACE_FLIP_PENDING_DELAY 20 29 SURFACE_UPDATE_PENDING 30 30 SURFACE_FLIP_PENDING 31 31 mmHUBPREQ2_DCSURF_FLIP_CONTROL2 0 0x717 3 0 2 SURFACE_UPDATE_FLIP_PENDING_MIN_TIME 0 7 SURFACE_UPDATE_PENDING_HIGH_EXTEND_ENABLE 12 12 SURFACE_FLIP_PENDING_HIGH_EXTEND_ENABLE 13 13 mmHUBPREQ2_DCSURF_FRAME_PACING_CONTROL 0 0x718 4 0 2 SURFACE_FRAME_PACING_ENABLE 0 0 SURFACE_FRAME_PACING_MODE 1 1 SURFACE_FRAME_PACING_QUEUE_RESET 8 8 SURFACE_FRAME_PACING_QUEUE_FREE_ENTRY 24 26 mmHUBPREQ2_DCSURF_FRAME_PACING_TIME 0 0x719 1 0 2 SURFACE_FRAME_PACING_TIME 0 31 mmHUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT 0 0x71a 10 0 2 SURFACE_FLIP_INT_MASK 0 0 SURFACE_FLIP_INT_TYPE 1 1 SURFACE_FLIP_AWAY_INT_MASK 2 2 SURFACE_FLIP_AWAY_INT_TYPE 3 3 SURFACE_FLIP_CLEAR 8 8 SURFACE_FLIP_AWAY_CLEAR 9 9 SURFACE_FLIP_OCCURRED 16 16 SURFACE_FLIP_INT_STATUS 17 17 SURFACE_FLIP_AWAY_OCCURRED 18 18 SURFACE_FLIP_AWAY_INT_STATUS 19 19 mmHUBPREQ2_DCSURF_SURFACE_INUSE 0 0x71b 1 0 2 SURFACE_INUSE_ADDRESS 0 31 mmHUBPREQ2_DCSURF_SURFACE_INUSE_HIGH 0 0x71c 1 0 2 SURFACE_INUSE_ADDRESS_HIGH 0 15 mmHUBPREQ2_DCSURF_SURFACE_INUSE_C 0 0x71d 1 0 2 SURFACE_INUSE_ADDRESS_C 0 31 mmHUBPREQ2_DCSURF_SURFACE_INUSE_HIGH_C 0 0x71e 1 0 2 SURFACE_INUSE_ADDRESS_HIGH_C 0 15 mmHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE 0 0x71f 1 0 2 SURFACE_EARLIEST_INUSE_ADDRESS 0 31 mmHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_HIGH 0 0x720 1 0 2 SURFACE_EARLIEST_INUSE_ADDRESS_HIGH 0 15 mmHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_C 0 0x721 1 0 2 SURFACE_EARLIEST_INUSE_ADDRESS_C 0 31 mmHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C 0 0x722 1 0 2 SURFACE_EARLIEST_INUSE_ADDRESS_HIGH_C 0 15 mmHUBPREQ2_DCN_EXPANSION_MODE 0 0x723 4 0 2 DRQ_EXPANSION_MODE 0 1 CRQ_EXPANSION_MODE 2 3 MRQ_EXPANSION_MODE 4 5 PRQ_EXPANSION_MODE 6 7 mmHUBPREQ2_DCN_TTU_QOS_WM 0 0x724 2 0 2 QoS_LEVEL_LOW_WM 0 13 QoS_LEVEL_HIGH_WM 16 29 mmHUBPREQ2_DCN_GLOBAL_TTU_CNTL 0 0x725 2 0 2 MIN_TTU_VBLANK 0 23 QoS_LEVEL_FLIP 28 31 mmHUBPREQ2_DCN_SURF0_TTU_CNTL0 0 0x726 3 0 2 REFCYC_PER_REQ_DELIVERY 0 22 QoS_LEVEL_FIXED 24 27 QoS_RAMP_DISABLE 28 28 mmHUBPREQ2_DCN_SURF0_TTU_CNTL1 0 0x727 1 0 2 REFCYC_PER_REQ_DELIVERY_PRE 0 22 mmHUBPREQ2_DCN_SURF1_TTU_CNTL0 0 0x728 3 0 2 REFCYC_PER_REQ_DELIVERY 0 22 QoS_LEVEL_FIXED 24 27 QoS_RAMP_DISABLE 28 28 mmHUBPREQ2_DCN_SURF1_TTU_CNTL1 0 0x729 1 0 2 REFCYC_PER_REQ_DELIVERY_PRE 0 22 mmHUBPREQ2_DCN_CUR0_TTU_CNTL0 0 0x72a 3 0 2 REFCYC_PER_REQ_DELIVERY 0 22 QoS_LEVEL_FIXED 24 27 QoS_RAMP_DISABLE 28 28 mmHUBPREQ2_DCN_CUR0_TTU_CNTL1 0 0x72b 1 0 2 REFCYC_PER_REQ_DELIVERY_PRE 0 22 mmHUBPREQ2_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_LSB 0 0x72c 1 0 2 MC_VM_SYSTEM_APERTURE_LOW_ADDR_LSB 0 31 mmHUBPREQ2_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_MSB 0 0x72d 1 0 2 MC_VM_SYSTEM_APERTURE_LOW_ADDR_MSB 0 3 mmHUBPREQ2_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_LSB 0 0x72e 1 0 2 MC_VM_SYSTEM_APERTURE_HIGH_ADDR_LSB 0 31 mmHUBPREQ2_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_MSB 0 0x72f 1 0 2 MC_VM_SYSTEM_APERTURE_HIGH_ADDR_MSB 0 3 mmHUBPREQ2_DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB 0 0x730 1 0 2 MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB 0 31 mmHUBPREQ2_DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB 0 0x731 3 0 2 MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB 0 3 MC_VM_SYSTEM_APERTURE_DEFAULT_SYSTEM 28 28 MC_VM_SYSTEM_APERTURE_DEFAULT_SNOOP 29 29 mmHUBPREQ2_DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_LSB 0 0x732 1 0 2 VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_LSB 0 31 mmHUBPREQ2_DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB 0 0x733 4 0 2 VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB 0 3 VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_SYSTEM 28 28 VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_SNOOP 29 29 VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_TMZ 30 30 mmHUBPREQ2_DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LSB 0 0x734 1 0 2 VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LSB 0 31 mmHUBPREQ2_DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_MSB 0 0x735 1 0 2 VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_MSB 0 31 mmHUBPREQ2_DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LSB 0 0x736 1 0 2 VM_CONTEXT0_PAGE_TABLE_START_ADDR_LSB 0 31 mmHUBPREQ2_DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_MSB 0 0x737 1 0 2 VM_CONTEXT0_PAGE_TABLE_START_ADDR_MSB 0 3 mmHUBPREQ2_DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LSB 0 0x738 1 0 2 VM_CONTEXT0_PAGE_TABLE_END_ADDR_LSB 0 31 mmHUBPREQ2_DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_MSB 0 0x739 1 0 2 VM_CONTEXT0_PAGE_TABLE_END_ADDR_MSB 0 3 mmHUBPREQ2_DCN_VM_CONTEXT0_STATUS 0 0x73a 4 0 2 DCN_VM_CONTEXT0_ERROR_STATUS 0 15 DCN_VM_CONTEXT0_PROTECTION_FAULT_ADDR_MSB 24 27 DCN_VM_CONTEXT0_ERROR_STATUS_MODE 30 30 DCN_VM_CONTEXT0_ERROR_STATUS_CLEAR 31 31 mmHUBPREQ2_DCN_VM_CONTEXT0_PROTECTION_FAULT_ADDR_LSB 0 0x73b 1 0 2 DCN_VM_CONTEXT0_PROTECTION_FAULT_ADDR_LSB 0 31 mmHUBPREQ2_DCN_VM_CONTEXT0_CNTL 0 0x73c 7 0 2 PAGE_TABLE_DEPTH 1 2 RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT 3 3 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT 4 4 VALID_PROTECTION_FAULT_ENABLE_INTERRUPT 12 12 VALID_PROTECTION_FAULT_ENABLE_DEFAULT 13 13 READ_PROTECTION_FAULT_ENABLE_INTERRUPT 15 15 READ_PROTECTION_FAULT_ENABLE_DEFAULT 16 16 mmHUBPREQ2_DCN_VM_MX_L1_TLB_CNTL 0 0x73d 2 0 2 ENABLE_L1_TLB 0 0 SYSTEM_ACCESS_MODE 3 4 mmHUBPREQ2_BLANK_OFFSET_0 0 0x73e 2 0 2 REFCYC_H_BLANK_END 0 12 DLG_V_BLANK_END 16 30 mmHUBPREQ2_BLANK_OFFSET_1 0 0x73f 1 0 2 MIN_DST_Y_NEXT_START 0 17 mmHUBPREQ2_DST_DIMENSIONS 0 0x740 1 0 2 REFCYC_PER_HTOTAL 0 20 mmHUBPREQ2_DST_AFTER_SCALER 0 0x741 2 0 2 REFCYC_X_AFTER_SCALER 0 12 DST_Y_AFTER_SCALER 16 18 mmHUBPREQ2_PREFETCH_SETTINS 0 0x742 2 0 2 VRATIO_PREFETCH 0 20 DST_Y_PREFETCH 24 31 mmHUBPREQ2_PREFETCH_SETTINS_C 0 0x743 1 0 2 VRATIO_PREFETCH_C 0 20 mmHUBPREQ2_VBLANK_PARAMETERS_0 0 0x744 2 0 2 DST_Y_PER_VM_VBLANK 0 4 DST_Y_PER_ROW_VBLANK 8 13 mmHUBPREQ2_VBLANK_PARAMETERS_1 0 0x745 1 0 2 REFCYC_PER_PTE_GROUP_VBLANK_L 0 22 mmHUBPREQ2_VBLANK_PARAMETERS_2 0 0x746 1 0 2 REFCYC_PER_PTE_GROUP_VBLANK_C 0 22 mmHUBPREQ2_VBLANK_PARAMETERS_3 0 0x747 1 0 2 REFCYC_PER_META_CHUNK_VBLANK_L 0 22 mmHUBPREQ2_VBLANK_PARAMETERS_4 0 0x748 1 0 2 REFCYC_PER_META_CHUNK_VBLANK_C 0 22 mmHUBPREQ2_NOM_PARAMETERS_0 0 0x749 1 0 2 DST_Y_PER_PTE_ROW_NOM_L 0 16 mmHUBPREQ2_NOM_PARAMETERS_1 0 0x74a 1 0 2 REFCYC_PER_PTE_GROUP_NOM_L 0 22 mmHUBPREQ2_NOM_PARAMETERS_2 0 0x74b 1 0 2 DST_Y_PER_PTE_ROW_NOM_C 0 16 mmHUBPREQ2_NOM_PARAMETERS_3 0 0x74c 1 0 2 REFCYC_PER_PTE_GROUP_NOM_C 0 22 mmHUBPREQ2_NOM_PARAMETERS_4 0 0x74d 1 0 2 DST_Y_PER_META_ROW_NOM_L 0 16 mmHUBPREQ2_NOM_PARAMETERS_5 0 0x74e 1 0 2 REFCYC_PER_META_CHUNK_NOM_L 0 22 mmHUBPREQ2_NOM_PARAMETERS_6 0 0x74f 1 0 2 DST_Y_PER_META_ROW_NOM_C 0 16 mmHUBPREQ2_NOM_PARAMETERS_7 0 0x750 1 0 2 REFCYC_PER_META_CHUNK_NOM_C 0 22 mmHUBPREQ2_PER_LINE_DELIVERY_PRE 0 0x751 2 0 2 REFCYC_PER_LINE_DELIVERY_PRE_L 0 12 REFCYC_PER_LINE_DELIVERY_PRE_C 16 28 mmHUBPREQ2_PER_LINE_DELIVERY 0 0x752 2 0 2 REFCYC_PER_LINE_DELIVERY_L 0 12 REFCYC_PER_LINE_DELIVERY_C 16 28 mmHUBPREQ2_CURSOR_SETTINS 0 0x753 2 0 2 CURSOR0_DST_Y_OFFSET 0 7 CURSOR0_CHUNK_HDL_ADJUST 8 9 mmHUBPREQ2_REF_FREQ_TO_PIX_FREQ 0 0x754 1 0 2 REF_FREQ_TO_PIX_FREQ 0 20 mmHUBPREQ2_HUBPREQ_MEM_PWR_CTRL 0 0x755 11 0 2 REQ_DPTE_MEM_PWR_FORCE 0 1 REQ_DPTE_MEM_PWR_DIS 2 2 REQ_MPTE_MEM_PWR_FORCE 4 5 REQ_MPTE_MEM_PWR_DIS 6 6 REQ_META_MEM_PWR_FORCE 8 9 REQ_META_MEM_PWR_DIS 10 10 REQ_DPTE_FINE_GRAIN_DIS 16 16 REQ_DPTE_FINE_GRAIN_DIS_C 17 17 REQ_META_FINE_GRAIN_DIS 20 20 REQ_META_FINE_GRAIN_DIS_C 21 21 REQ_MPTE_FINE_GRAIN_DIS 24 24 mmHUBPREQ2_HUBPREQ_MEM_PWR_STATUS 0 0x756 3 0 2 REQ_DPTE_MEM_PWR_STATE 0 1 REQ_MPTE_MEM_PWR_STATE 2 3 REQ_META_MEM_PWR_STATE 4 5 mmHUBPRET2_HUBPRET_CONTROL 0 0x768 7 0 2 DET_BUF_PLANE1_BASE_ADDRESS 0 11 PACK_3TO2_ELEMENT_DISABLE 12 12 CROSSBAR_SRC_ALPHA 16 17 CROSSBAR_SRC_Y_G 18 19 CROSSBAR_SRC_CB_B 20 21 CROSSBAR_SRC_CR_R 22 23 HUBPRET_CONTROL_SPARE 24 31 mmHUBPRET2_HUBPRET_MEM_PWR_CTRL 0 0x769 4 0 2 DET_MEM_PWR_FORCE 0 1 DET_MEM_PWR_DIS 2 2 DET_MEM_PWR_LS_MODE 4 5 HUBPRET_MEM_PWR_CTRL_SPARE 8 31 mmHUBPRET2_HUBPRET_MEM_PWR_STATUS 0 0x76a 1 0 2 DET_MEM_PWR_STATE 0 1 mmHUBPRET2_HUBPRET_READ_LINE_CTRL0 0 0x76b 2 0 2 PIPE_READ_LINE_INTERVAL_IN_NONACTIVE 0 15 PIPE_READ_LINE_VBLANK_MAXIMUM 16 29 mmHUBPRET2_HUBPRET_READ_LINE_CTRL1 0 0x76c 2 0 2 PIPE_READ_LINE_REPORTED_WHEN_REQ_DISABLED 0 13 HUBPRET_READ_LINE_CTRL1_SPARE 16 31 mmHUBPRET2_HUBPRET_READ_LINE0 0 0x76d 2 0 2 PIPE_READ_LINE0_START 0 13 PIPE_READ_LINE0_END 16 29 mmHUBPRET2_HUBPRET_READ_LINE1 0 0x76e 2 0 2 PIPE_READ_LINE1_START 0 13 PIPE_READ_LINE1_END 16 29 mmHUBPRET2_HUBPRET_INTERRUPT 0 0x76f 15 0 2 PIPE_VBLANK_INT_MASK 0 0 PIPE_READ_LINE0_INT_MASK 1 1 PIPE_READ_LINE1_INT_MASK 2 2 PIPE_VBLANK_INT_TYPE 4 4 PIPE_READ_LINE0_INT_TYPE 5 5 PIPE_READ_LINE1_INT_TYPE 6 6 PIPE_VBLANK_INT_CLEAR 8 8 PIPE_READ_LINE0_INT_CLEAR 9 9 PIPE_READ_LINE1_INT_CLEAR 10 10 PIPE_VBLANK_STATUS 12 12 PIPE_READ_LINE0_STATUS 13 13 PIPE_READ_LINE1_STATUS 14 14 PIPE_VBLANK_INT_STATUS 16 16 PIPE_READ_LINE0_INT_STATUS 17 17 PIPE_READ_LINE1_INT_STATUS 18 18 mmHUBPRET2_HUBPRET_READ_LINE_VALUE 0 0x770 2 0 2 PIPE_READ_LINE 0 13 PIPE_READ_LINE_SNAPSHOT 16 29 mmHUBPRET2_HUBPRET_READ_LINE_STATUS 0 0x771 5 0 2 PIPE_READ_VBLANK 0 0 PIPE_READ_LINE0_INSIDE 4 4 PIPE_READ_LINE0_OUTSIDE 5 5 PIPE_READ_LINE1_INSIDE 8 8 PIPE_READ_LINE1_OUTSIDE 10 10 mmCURSOR2_CURSOR_CONTROL 0 0x774 9 0 2 CURSOR_ENABLE 0 0 CURSOR_MODE 8 9 CURSOR_SNOOP 13 13 CURSOR_SYSTEM 14 14 CURSOR_PITCH 16 17 CURSOR_XY_POSITION_ROTATION_AND_MIRRORING_BYPASS 20 20 CURSOR_LINES_PER_CHUNK 24 28 CURSOR_PERFMON_LATENCY_MEASURE_EN 30 30 CURSOR_PERFMON_LATENCY_MEASURE_SEL 31 31 mmCURSOR2_CURSOR_SURFACE_ADDRESS 0 0x775 1 0 2 CURSOR_SURFACE_ADDRESS 0 31 mmCURSOR2_CURSOR_SURFACE_ADDRESS_HIGH 0 0x776 1 0 2 CURSOR_SURFACE_ADDRESS_HIGH 0 15 mmCURSOR2_CURSOR_SIZE 0 0x777 2 0 2 CURSOR_HEIGHT 0 8 CURSOR_WIDTH 16 24 mmCURSOR2_CURSOR_POSITION 0 0x778 2 0 2 CURSOR_Y_POSITION 0 13 CURSOR_X_POSITION 16 29 mmCURSOR2_CURSOR_HOT_SPOT 0 0x779 2 0 2 CURSOR_HOT_SPOT_Y 0 7 CURSOR_HOT_SPOT_X 16 23 mmCURSOR2_CURSOR_STEREO_CONTROL 0 0x77a 3 0 2 CURSOR_STEREO_EN 0 0 CURSOR_PRIMARY_OFFSET 4 17 CURSOR_SECONDARY_OFFSET 18 31 mmCURSOR2_CURSOR_DST_OFFSET 0 0x77b 1 0 2 CURSOR_DST_X_OFFSET 0 12 mmCURSOR2_CURSOR_MEM_PWR_CTRL 0 0x77c 3 0 2 CROB_MEM_PWR_FORCE 0 1 CROB_MEM_PWR_DIS 2 2 CROB_MEM_PWR_LS_MODE 4 5 mmCURSOR2_CURSOR_MEM_PWR_STATUS 0 0x77d 1 0 2 CROB_MEM_PWR_STATE 0 1 mmDC_PERFMON10_PERFCOUNTER_CNTL 0 0x799 11 0 2 PERFCOUNTER_EVENT_SEL 0 8 PERFCOUNTER_CVALUE_SEL 9 11 PERFCOUNTER_INC_MODE 12 14 PERFCOUNTER_HW_CNTL_SEL 15 15 PERFCOUNTER_RUNEN_MODE 16 16 PERFCOUNTER_CNTOFF_START_DIS 22 22 PERFCOUNTER_RESTART_EN 23 23 PERFCOUNTER_INT_EN 24 24 PERFCOUNTER_OFF_MASK 25 25 PERFCOUNTER_ACTIVE 26 26 PERFCOUNTER_CNTL_SEL 29 31 mmDC_PERFMON10_PERFCOUNTER_CNTL2 0 0x79a 5 0 2 PERFCOUNTER_COUNTED_VALUE_TYPE 0 1 PERFCOUNTER_HW_STOP1_SEL 2 2 PERFCOUNTER_HW_STOP2_SEL 3 3 PERFCOUNTER_CNTOFF_SEL 8 13 PERFCOUNTER_CNTL2_SEL 29 31 mmDC_PERFMON10_PERFCOUNTER_STATE 0 0x79b 16 0 2 PERFCOUNTER_CNT0_STATE 0 1 PERFCOUNTER_STATE_SEL0 2 2 PERFCOUNTER_CNT1_STATE 4 5 PERFCOUNTER_STATE_SEL1 6 6 PERFCOUNTER_CNT2_STATE 8 9 PERFCOUNTER_STATE_SEL2 10 10 PERFCOUNTER_CNT3_STATE 12 13 PERFCOUNTER_STATE_SEL3 14 14 PERFCOUNTER_CNT4_STATE 16 17 PERFCOUNTER_STATE_SEL4 18 18 PERFCOUNTER_CNT5_STATE 20 21 PERFCOUNTER_STATE_SEL5 22 22 PERFCOUNTER_CNT6_STATE 24 25 PERFCOUNTER_STATE_SEL6 26 26 PERFCOUNTER_CNT7_STATE 28 29 PERFCOUNTER_STATE_SEL7 30 30 mmDC_PERFMON10_PERFMON_CNTL 0 0x79c 6 0 2 PERFMON_STATE 0 1 PERFMON_RPT_COUNT 8 27 PERFMON_CNTOFF_AND_OR 28 28 PERFMON_CNTOFF_INT_EN 29 29 PERFMON_CNTOFF_INT_STATUS 30 30 PERFMON_CNTOFF_INT_ACK 31 31 mmDC_PERFMON10_PERFMON_CNTL2 0 0x79d 4 0 2 PERFMON_CNTOFF_INT_TYPE 0 0 PERFMON_CLK_ENABLE 1 1 PERFMON_RUN_ENABLE_START_SEL 2 9 PERFMON_RUN_ENABLE_STOP_SEL 10 17 mmDC_PERFMON10_PERFMON_CVALUE_INT_MISC 0 0x79e 17 0 2 PERFCOUNTER_INT0_STATUS 0 0 PERFCOUNTER_INT1_STATUS 1 1 PERFCOUNTER_INT2_STATUS 2 2 PERFCOUNTER_INT3_STATUS 3 3 PERFCOUNTER_INT4_STATUS 4 4 PERFCOUNTER_INT5_STATUS 5 5 PERFCOUNTER_INT6_STATUS 6 6 PERFCOUNTER_INT7_STATUS 7 7 PERFCOUNTER_INT0_ACK 8 8 PERFCOUNTER_INT1_ACK 9 9 PERFCOUNTER_INT2_ACK 10 10 PERFCOUNTER_INT3_ACK 11 11 PERFCOUNTER_INT4_ACK 12 12 PERFCOUNTER_INT5_ACK 13 13 PERFCOUNTER_INT6_ACK 14 14 PERFCOUNTER_INT7_ACK 15 15 PERFMON_CVALUE_HI 16 31 mmDC_PERFMON10_PERFMON_CVALUE_LOW 0 0x79f 1 0 2 PERFMON_CVALUE_LOW 0 31 mmDC_PERFMON10_PERFMON_HI 0 0x7a0 2 0 2 PERFMON_HI 0 15 PERFMON_READ_SEL 29 31 mmDC_PERFMON10_PERFMON_LOW 0 0x7a1 1 0 2 PERFMON_LOW 0 31 mmHUBP3_DCSURF_SURFACE_CONFIG 0 0x7a5 3 0 2 SURFACE_PIXEL_FORMAT 0 6 ROTATION_ANGLE 8 9 H_MIRROR_EN 10 10 mmHUBP3_DCSURF_ADDR_CONFIG 0 0x7a6 6 0 2 NUM_PIPES 0 2 NUM_BANKS 3 5 PIPE_INTERLEAVE 6 7 NUM_SE 8 9 NUM_RB_PER_SE 10 11 MAX_COMPRESSED_FRAGS 12 13 mmHUBP3_DCSURF_TILING_CONFIG 0 0x7a7 5 0 2 SW_MODE 0 4 DIM_TYPE 7 8 META_LINEAR 9 9 RB_ALIGNED 10 10 PIPE_ALIGNED 11 11 mmHUBP3_DCSURF_PRI_VIEWPORT_START 0 0x7a8 2 0 2 PRI_VIEWPORT_X_START 0 13 PRI_VIEWPORT_Y_START 16 29 mmHUBP3_DCSURF_PRI_VIEWPORT_DIMENSION 0 0x7a9 2 0 2 PRI_VIEWPORT_WIDTH 0 13 PRI_VIEWPORT_HEIGHT 16 29 mmHUBP3_DCSURF_PRI_VIEWPORT_START_C 0 0x7aa 2 0 2 PRI_VIEWPORT_X_START_C 0 13 PRI_VIEWPORT_Y_START_C 16 29 mmHUBP3_DCSURF_PRI_VIEWPORT_DIMENSION_C 0 0x7ab 2 0 2 PRI_VIEWPORT_WIDTH_C 0 13 PRI_VIEWPORT_HEIGHT_C 16 29 mmHUBP3_DCSURF_SEC_VIEWPORT_START 0 0x7ac 2 0 2 SEC_VIEWPORT_X_START 0 13 SEC_VIEWPORT_Y_START 16 29 mmHUBP3_DCSURF_SEC_VIEWPORT_DIMENSION 0 0x7ad 2 0 2 SEC_VIEWPORT_WIDTH 0 13 SEC_VIEWPORT_HEIGHT 16 29 mmHUBP3_DCSURF_SEC_VIEWPORT_START_C 0 0x7ae 2 0 2 SEC_VIEWPORT_X_START_C 0 13 SEC_VIEWPORT_Y_START_C 16 29 mmHUBP3_DCSURF_SEC_VIEWPORT_DIMENSION_C 0 0x7af 2 0 2 SEC_VIEWPORT_WIDTH_C 0 13 SEC_VIEWPORT_HEIGHT_C 16 29 mmHUBP3_DCHUBP_REQ_SIZE_CONFIG 0 0x7b0 8 0 2 SWATH_HEIGHT 0 2 PTE_ROW_HEIGHT_LINEAR 4 6 CHUNK_SIZE 8 10 MIN_CHUNK_SIZE 11 12 META_CHUNK_SIZE 16 17 MIN_META_CHUNK_SIZE 18 19 DPTE_GROUP_SIZE 20 22 MPTE_GROUP_SIZE 24 26 mmHUBP3_DCHUBP_REQ_SIZE_CONFIG_C 0 0x7b1 8 0 2 SWATH_HEIGHT_C 0 2 PTE_ROW_HEIGHT_LINEAR_C 4 6 CHUNK_SIZE_C 8 10 MIN_CHUNK_SIZE_C 11 12 META_CHUNK_SIZE_C 16 17 MIN_META_CHUNK_SIZE_C 18 19 DPTE_GROUP_SIZE_C 20 22 MPTE_GROUP_SIZE_C 24 26 mmHUBP3_DCHUBP_CNTL 0 0x7b2 9 0 2 HUBP_BLANK_EN 0 0 HUBP_NO_OUTSTANDING_REQ 1 1 HUBP_DISABLE 2 2 HUBP_IN_BLANK 3 3 HUBP_VTG_SEL 4 7 HUBP_TTU_DISABLE 12 12 HUBP_TTU_MODE 13 15 HUBP_UNDERFLOW_STATUS 28 30 HUBP_UNDERFLOW_CLEAR 31 31 mmHUBP3_HUBP_CLK_CNTL 0 0x7b3 10 0 2 HUBP_CLOCK_ENABLE 0 0 HUBP_DISPCLK_R_GATE_DIS 4 4 HUBP_DPPCLK_G_GATE_DIS 8 8 HUBP_DCFCLK_R_GATE_DIS 12 12 HUBP_DCFCLK_G_GATE_DIS 16 16 HUBP_DISPCLK_R_CLOCK_ON 20 20 HUBP_DPPCLK_G_CLOCK_ON 21 21 HUBP_DCFCLK_R_CLOCK_ON 22 22 HUBP_DCFCLK_G_CLOCK_ON 23 23 HUBP_TEST_CLK_SEL 28 31 mmHUBP3_DCHUBP_VMPG_CONFIG 0 0x7b4 1 0 2 VMPG_SIZE 0 0 mmHUBP3_HUBPREQ_DEBUG_DB 0 0x7b5 1 0 2 HUBPREQ_DEBUG 0 31 mmHUBP3_HUBPREQ_DEBUG 0 0x7b6 0 0 2 mmHUBP3_HUBP_MEASURE_WIN_CTRL_DCFCLK 0 0x7ba 5 0 2 HUBP_MEASURE_WIN_EN_DCFCLK 0 0 HUBP_MEASURE_WIN_PERIOD_M1_DCFCLK 4 11 HUBP_PERFMON_START_SEL_DCFCLK 12 16 HUBP_PERFMON_STOP_SEL_DCFCLK 20 24 HUBP_MEASURE_WIN_MODE_DCFCLK 28 29 mmHUBP3_HUBP_MEASURE_WIN_CTRL_DPPCLK 0 0x7bb 5 0 2 HUBP_MEASURE_WIN_EN_DPPCLK 0 0 HUBP_MEASURE_WIN_SRC_SEL_DPPCLK 1 1 HUBP_MEASURE_WIN_PERIOD_M1_DPPCLK 4 11 HUBP_PERFMON_START_SEL_DPPCLK 12 16 HUBP_PERFMON_STOP_SEL_DPPCLK 20 24 mmHUBPREQ3_DCSURF_SURFACE_PITCH 0 0x7c7 2 0 2 PITCH 0 13 META_PITCH 16 29 mmHUBPREQ3_DCSURF_SURFACE_PITCH_C 0 0x7c8 2 0 2 PITCH_C 0 13 META_PITCH_C 16 29 mmHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS 0 0x7c9 1 0 2 PRIMARY_SURFACE_ADDRESS 0 31 mmHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH 0 0x7ca 1 0 2 PRIMARY_SURFACE_ADDRESS_HIGH 0 15 mmHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_C 0 0x7cb 1 0 2 PRIMARY_SURFACE_ADDRESS_C 0 31 mmHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C 0 0x7cc 1 0 2 PRIMARY_SURFACE_ADDRESS_HIGH_C 0 15 mmHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS 0 0x7cd 1 0 2 SECONDARY_SURFACE_ADDRESS 0 31 mmHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH 0 0x7ce 1 0 2 SECONDARY_SURFACE_ADDRESS_HIGH 0 15 mmHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_C 0 0x7cf 1 0 2 SECONDARY_SURFACE_ADDRESS_C 0 31 mmHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C 0 0x7d0 1 0 2 SECONDARY_SURFACE_ADDRESS_HIGH_C 0 15 mmHUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS 0 0x7d1 1 0 2 PRIMARY_META_SURFACE_ADDRESS 0 31 mmHUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH 0 0x7d2 1 0 2 PRIMARY_META_SURFACE_ADDRESS_HIGH 0 15 mmHUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C 0 0x7d3 1 0 2 PRIMARY_META_SURFACE_ADDRESS_C 0 31 mmHUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C 0 0x7d4 1 0 2 PRIMARY_META_SURFACE_ADDRESS_HIGH_C 0 15 mmHUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS 0 0x7d5 1 0 2 SECONDARY_META_SURFACE_ADDRESS 0 31 mmHUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH 0 0x7d6 1 0 2 SECONDARY_META_SURFACE_ADDRESS_HIGH 0 15 mmHUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C 0 0x7d7 1 0 2 SECONDARY_META_SURFACE_ADDRESS_C 0 31 mmHUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C 0 0x7d8 1 0 2 SECONDARY_META_SURFACE_ADDRESS_HIGH_C 0 15 mmHUBPREQ3_DCSURF_SURFACE_CONTROL 0 0x7d9 6 0 2 PRIMARY_SURFACE_DCC_EN 1 1 PRIMARY_SURFACE_DCC_IND_64B_BLK 2 2 PRIMARY_SURFACE_DCC_IND_64B_BLK_C 5 5 SECONDARY_SURFACE_DCC_EN 9 9 SECONDARY_SURFACE_DCC_IND_64B_BLK 10 10 SECONDARY_SURFACE_DCC_IND_64B_BLK_C 13 13 mmHUBPREQ3_DCSURF_FLIP_CONTROL 0 0x7da 10 0 2 SURFACE_UPDATE_LOCK 0 0 SURFACE_FLIP_TYPE 1 1 SURFACE_FLIP_VUPDATE_SKIP_NUM 4 7 SURFACE_FLIP_MODE_FOR_STEREOSYNC 12 13 SURFACE_FLIP_IN_STEREOSYNC 16 16 SURFACE_FLIP_STEREO_SELECT_DISABLE 17 17 SURFACE_FLIP_STEREO_SELECT_POLARITY 18 18 SURFACE_FLIP_PENDING_DELAY 20 29 SURFACE_UPDATE_PENDING 30 30 SURFACE_FLIP_PENDING 31 31 mmHUBPREQ3_DCSURF_FLIP_CONTROL2 0 0x7db 3 0 2 SURFACE_UPDATE_FLIP_PENDING_MIN_TIME 0 7 SURFACE_UPDATE_PENDING_HIGH_EXTEND_ENABLE 12 12 SURFACE_FLIP_PENDING_HIGH_EXTEND_ENABLE 13 13 mmHUBPREQ3_DCSURF_FRAME_PACING_CONTROL 0 0x7dc 4 0 2 SURFACE_FRAME_PACING_ENABLE 0 0 SURFACE_FRAME_PACING_MODE 1 1 SURFACE_FRAME_PACING_QUEUE_RESET 8 8 SURFACE_FRAME_PACING_QUEUE_FREE_ENTRY 24 26 mmHUBPREQ3_DCSURF_FRAME_PACING_TIME 0 0x7dd 1 0 2 SURFACE_FRAME_PACING_TIME 0 31 mmHUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT 0 0x7de 10 0 2 SURFACE_FLIP_INT_MASK 0 0 SURFACE_FLIP_INT_TYPE 1 1 SURFACE_FLIP_AWAY_INT_MASK 2 2 SURFACE_FLIP_AWAY_INT_TYPE 3 3 SURFACE_FLIP_CLEAR 8 8 SURFACE_FLIP_AWAY_CLEAR 9 9 SURFACE_FLIP_OCCURRED 16 16 SURFACE_FLIP_INT_STATUS 17 17 SURFACE_FLIP_AWAY_OCCURRED 18 18 SURFACE_FLIP_AWAY_INT_STATUS 19 19 mmHUBPREQ3_DCSURF_SURFACE_INUSE 0 0x7df 1 0 2 SURFACE_INUSE_ADDRESS 0 31 mmHUBPREQ3_DCSURF_SURFACE_INUSE_HIGH 0 0x7e0 1 0 2 SURFACE_INUSE_ADDRESS_HIGH 0 15 mmHUBPREQ3_DCSURF_SURFACE_INUSE_C 0 0x7e1 1 0 2 SURFACE_INUSE_ADDRESS_C 0 31 mmHUBPREQ3_DCSURF_SURFACE_INUSE_HIGH_C 0 0x7e2 1 0 2 SURFACE_INUSE_ADDRESS_HIGH_C 0 15 mmHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE 0 0x7e3 1 0 2 SURFACE_EARLIEST_INUSE_ADDRESS 0 31 mmHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_HIGH 0 0x7e4 1 0 2 SURFACE_EARLIEST_INUSE_ADDRESS_HIGH 0 15 mmHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_C 0 0x7e5 1 0 2 SURFACE_EARLIEST_INUSE_ADDRESS_C 0 31 mmHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C 0 0x7e6 1 0 2 SURFACE_EARLIEST_INUSE_ADDRESS_HIGH_C 0 15 mmHUBPREQ3_DCN_EXPANSION_MODE 0 0x7e7 4 0 2 DRQ_EXPANSION_MODE 0 1 CRQ_EXPANSION_MODE 2 3 MRQ_EXPANSION_MODE 4 5 PRQ_EXPANSION_MODE 6 7 mmHUBPREQ3_DCN_TTU_QOS_WM 0 0x7e8 2 0 2 QoS_LEVEL_LOW_WM 0 13 QoS_LEVEL_HIGH_WM 16 29 mmHUBPREQ3_DCN_GLOBAL_TTU_CNTL 0 0x7e9 2 0 2 MIN_TTU_VBLANK 0 23 QoS_LEVEL_FLIP 28 31 mmHUBPREQ3_DCN_SURF0_TTU_CNTL0 0 0x7ea 3 0 2 REFCYC_PER_REQ_DELIVERY 0 22 QoS_LEVEL_FIXED 24 27 QoS_RAMP_DISABLE 28 28 mmHUBPREQ3_DCN_SURF0_TTU_CNTL1 0 0x7eb 1 0 2 REFCYC_PER_REQ_DELIVERY_PRE 0 22 mmHUBPREQ3_DCN_SURF1_TTU_CNTL0 0 0x7ec 3 0 2 REFCYC_PER_REQ_DELIVERY 0 22 QoS_LEVEL_FIXED 24 27 QoS_RAMP_DISABLE 28 28 mmHUBPREQ3_DCN_SURF1_TTU_CNTL1 0 0x7ed 1 0 2 REFCYC_PER_REQ_DELIVERY_PRE 0 22 mmHUBPREQ3_DCN_CUR0_TTU_CNTL0 0 0x7ee 3 0 2 REFCYC_PER_REQ_DELIVERY 0 22 QoS_LEVEL_FIXED 24 27 QoS_RAMP_DISABLE 28 28 mmHUBPREQ3_DCN_CUR0_TTU_CNTL1 0 0x7ef 1 0 2 REFCYC_PER_REQ_DELIVERY_PRE 0 22 mmHUBPREQ3_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_LSB 0 0x7f0 1 0 2 MC_VM_SYSTEM_APERTURE_LOW_ADDR_LSB 0 31 mmHUBPREQ3_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_MSB 0 0x7f1 1 0 2 MC_VM_SYSTEM_APERTURE_LOW_ADDR_MSB 0 3 mmHUBPREQ3_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_LSB 0 0x7f2 1 0 2 MC_VM_SYSTEM_APERTURE_HIGH_ADDR_LSB 0 31 mmHUBPREQ3_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_MSB 0 0x7f3 1 0 2 MC_VM_SYSTEM_APERTURE_HIGH_ADDR_MSB 0 3 mmHUBPREQ3_DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB 0 0x7f4 1 0 2 MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB 0 31 mmHUBPREQ3_DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB 0 0x7f5 3 0 2 MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB 0 3 MC_VM_SYSTEM_APERTURE_DEFAULT_SYSTEM 28 28 MC_VM_SYSTEM_APERTURE_DEFAULT_SNOOP 29 29 mmHUBPREQ3_DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_LSB 0 0x7f6 1 0 2 VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_LSB 0 31 mmHUBPREQ3_DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB 0 0x7f7 4 0 2 VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB 0 3 VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_SYSTEM 28 28 VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_SNOOP 29 29 VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_TMZ 30 30 mmHUBPREQ3_DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LSB 0 0x7f8 1 0 2 VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LSB 0 31 mmHUBPREQ3_DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_MSB 0 0x7f9 1 0 2 VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_MSB 0 31 mmHUBPREQ3_DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LSB 0 0x7fa 1 0 2 VM_CONTEXT0_PAGE_TABLE_START_ADDR_LSB 0 31 mmHUBPREQ3_DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_MSB 0 0x7fb 1 0 2 VM_CONTEXT0_PAGE_TABLE_START_ADDR_MSB 0 3 mmHUBPREQ3_DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LSB 0 0x7fc 1 0 2 VM_CONTEXT0_PAGE_TABLE_END_ADDR_LSB 0 31 mmHUBPREQ3_DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_MSB 0 0x7fd 1 0 2 VM_CONTEXT0_PAGE_TABLE_END_ADDR_MSB 0 3 mmHUBPREQ3_DCN_VM_CONTEXT0_STATUS 0 0x7fe 4 0 2 DCN_VM_CONTEXT0_ERROR_STATUS 0 15 DCN_VM_CONTEXT0_PROTECTION_FAULT_ADDR_MSB 24 27 DCN_VM_CONTEXT0_ERROR_STATUS_MODE 30 30 DCN_VM_CONTEXT0_ERROR_STATUS_CLEAR 31 31 mmHUBPREQ3_DCN_VM_CONTEXT0_PROTECTION_FAULT_ADDR_LSB 0 0x7ff 1 0 2 DCN_VM_CONTEXT0_PROTECTION_FAULT_ADDR_LSB 0 31 mmHUBPREQ3_DCN_VM_CONTEXT0_CNTL 0 0x800 7 0 2 PAGE_TABLE_DEPTH 1 2 RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT 3 3 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT 4 4 VALID_PROTECTION_FAULT_ENABLE_INTERRUPT 12 12 VALID_PROTECTION_FAULT_ENABLE_DEFAULT 13 13 READ_PROTECTION_FAULT_ENABLE_INTERRUPT 15 15 READ_PROTECTION_FAULT_ENABLE_DEFAULT 16 16 mmHUBPREQ3_DCN_VM_MX_L1_TLB_CNTL 0 0x801 2 0 2 ENABLE_L1_TLB 0 0 SYSTEM_ACCESS_MODE 3 4 mmHUBPREQ3_BLANK_OFFSET_0 0 0x802 2 0 2 REFCYC_H_BLANK_END 0 12 DLG_V_BLANK_END 16 30 mmHUBPREQ3_BLANK_OFFSET_1 0 0x803 1 0 2 MIN_DST_Y_NEXT_START 0 17 mmHUBPREQ3_DST_DIMENSIONS 0 0x804 1 0 2 REFCYC_PER_HTOTAL 0 20 mmHUBPREQ3_DST_AFTER_SCALER 0 0x805 2 0 2 REFCYC_X_AFTER_SCALER 0 12 DST_Y_AFTER_SCALER 16 18 mmHUBPREQ3_PREFETCH_SETTINS 0 0x806 2 0 2 VRATIO_PREFETCH 0 20 DST_Y_PREFETCH 24 31 mmHUBPREQ3_PREFETCH_SETTINS_C 0 0x807 1 0 2 VRATIO_PREFETCH_C 0 20 mmHUBPREQ3_VBLANK_PARAMETERS_0 0 0x808 2 0 2 DST_Y_PER_VM_VBLANK 0 4 DST_Y_PER_ROW_VBLANK 8 13 mmHUBPREQ3_VBLANK_PARAMETERS_1 0 0x809 1 0 2 REFCYC_PER_PTE_GROUP_VBLANK_L 0 22 mmHUBPREQ3_VBLANK_PARAMETERS_2 0 0x80a 1 0 2 REFCYC_PER_PTE_GROUP_VBLANK_C 0 22 mmHUBPREQ3_VBLANK_PARAMETERS_3 0 0x80b 1 0 2 REFCYC_PER_META_CHUNK_VBLANK_L 0 22 mmHUBPREQ3_VBLANK_PARAMETERS_4 0 0x80c 1 0 2 REFCYC_PER_META_CHUNK_VBLANK_C 0 22 mmHUBPREQ3_NOM_PARAMETERS_0 0 0x80d 1 0 2 DST_Y_PER_PTE_ROW_NOM_L 0 16 mmHUBPREQ3_NOM_PARAMETERS_1 0 0x80e 1 0 2 REFCYC_PER_PTE_GROUP_NOM_L 0 22 mmHUBPREQ3_NOM_PARAMETERS_2 0 0x80f 1 0 2 DST_Y_PER_PTE_ROW_NOM_C 0 16 mmHUBPREQ3_NOM_PARAMETERS_3 0 0x810 1 0 2 REFCYC_PER_PTE_GROUP_NOM_C 0 22 mmHUBPREQ3_NOM_PARAMETERS_4 0 0x811 1 0 2 DST_Y_PER_META_ROW_NOM_L 0 16 mmHUBPREQ3_NOM_PARAMETERS_5 0 0x812 1 0 2 REFCYC_PER_META_CHUNK_NOM_L 0 22 mmHUBPREQ3_NOM_PARAMETERS_6 0 0x813 1 0 2 DST_Y_PER_META_ROW_NOM_C 0 16 mmHUBPREQ3_NOM_PARAMETERS_7 0 0x814 1 0 2 REFCYC_PER_META_CHUNK_NOM_C 0 22 mmHUBPREQ3_PER_LINE_DELIVERY_PRE 0 0x815 2 0 2 REFCYC_PER_LINE_DELIVERY_PRE_L 0 12 REFCYC_PER_LINE_DELIVERY_PRE_C 16 28 mmHUBPREQ3_PER_LINE_DELIVERY 0 0x816 2 0 2 REFCYC_PER_LINE_DELIVERY_L 0 12 REFCYC_PER_LINE_DELIVERY_C 16 28 mmHUBPREQ3_CURSOR_SETTINS 0 0x817 2 0 2 CURSOR0_DST_Y_OFFSET 0 7 CURSOR0_CHUNK_HDL_ADJUST 8 9 mmHUBPREQ3_REF_FREQ_TO_PIX_FREQ 0 0x818 1 0 2 REF_FREQ_TO_PIX_FREQ 0 20 mmHUBPREQ3_HUBPREQ_MEM_PWR_CTRL 0 0x819 11 0 2 REQ_DPTE_MEM_PWR_FORCE 0 1 REQ_DPTE_MEM_PWR_DIS 2 2 REQ_MPTE_MEM_PWR_FORCE 4 5 REQ_MPTE_MEM_PWR_DIS 6 6 REQ_META_MEM_PWR_FORCE 8 9 REQ_META_MEM_PWR_DIS 10 10 REQ_DPTE_FINE_GRAIN_DIS 16 16 REQ_DPTE_FINE_GRAIN_DIS_C 17 17 REQ_META_FINE_GRAIN_DIS 20 20 REQ_META_FINE_GRAIN_DIS_C 21 21 REQ_MPTE_FINE_GRAIN_DIS 24 24 mmHUBPREQ3_HUBPREQ_MEM_PWR_STATUS 0 0x81a 3 0 2 REQ_DPTE_MEM_PWR_STATE 0 1 REQ_MPTE_MEM_PWR_STATE 2 3 REQ_META_MEM_PWR_STATE 4 5 mmHUBPRET3_HUBPRET_CONTROL 0 0x82c 7 0 2 DET_BUF_PLANE1_BASE_ADDRESS 0 11 PACK_3TO2_ELEMENT_DISABLE 12 12 CROSSBAR_SRC_ALPHA 16 17 CROSSBAR_SRC_Y_G 18 19 CROSSBAR_SRC_CB_B 20 21 CROSSBAR_SRC_CR_R 22 23 HUBPRET_CONTROL_SPARE 24 31 mmHUBPRET3_HUBPRET_MEM_PWR_CTRL 0 0x82d 4 0 2 DET_MEM_PWR_FORCE 0 1 DET_MEM_PWR_DIS 2 2 DET_MEM_PWR_LS_MODE 4 5 HUBPRET_MEM_PWR_CTRL_SPARE 8 31 mmHUBPRET3_HUBPRET_MEM_PWR_STATUS 0 0x82e 1 0 2 DET_MEM_PWR_STATE 0 1 mmHUBPRET3_HUBPRET_READ_LINE_CTRL0 0 0x82f 2 0 2 PIPE_READ_LINE_INTERVAL_IN_NONACTIVE 0 15 PIPE_READ_LINE_VBLANK_MAXIMUM 16 29 mmHUBPRET3_HUBPRET_READ_LINE_CTRL1 0 0x830 2 0 2 PIPE_READ_LINE_REPORTED_WHEN_REQ_DISABLED 0 13 HUBPRET_READ_LINE_CTRL1_SPARE 16 31 mmHUBPRET3_HUBPRET_READ_LINE0 0 0x831 2 0 2 PIPE_READ_LINE0_START 0 13 PIPE_READ_LINE0_END 16 29 mmHUBPRET3_HUBPRET_READ_LINE1 0 0x832 2 0 2 PIPE_READ_LINE1_START 0 13 PIPE_READ_LINE1_END 16 29 mmHUBPRET3_HUBPRET_INTERRUPT 0 0x833 15 0 2 PIPE_VBLANK_INT_MASK 0 0 PIPE_READ_LINE0_INT_MASK 1 1 PIPE_READ_LINE1_INT_MASK 2 2 PIPE_VBLANK_INT_TYPE 4 4 PIPE_READ_LINE0_INT_TYPE 5 5 PIPE_READ_LINE1_INT_TYPE 6 6 PIPE_VBLANK_INT_CLEAR 8 8 PIPE_READ_LINE0_INT_CLEAR 9 9 PIPE_READ_LINE1_INT_CLEAR 10 10 PIPE_VBLANK_STATUS 12 12 PIPE_READ_LINE0_STATUS 13 13 PIPE_READ_LINE1_STATUS 14 14 PIPE_VBLANK_INT_STATUS 16 16 PIPE_READ_LINE0_INT_STATUS 17 17 PIPE_READ_LINE1_INT_STATUS 18 18 mmHUBPRET3_HUBPRET_READ_LINE_VALUE 0 0x834 2 0 2 PIPE_READ_LINE 0 13 PIPE_READ_LINE_SNAPSHOT 16 29 mmHUBPRET3_HUBPRET_READ_LINE_STATUS 0 0x835 5 0 2 PIPE_READ_VBLANK 0 0 PIPE_READ_LINE0_INSIDE 4 4 PIPE_READ_LINE0_OUTSIDE 5 5 PIPE_READ_LINE1_INSIDE 8 8 PIPE_READ_LINE1_OUTSIDE 10 10 mmCURSOR3_CURSOR_CONTROL 0 0x838 9 0 2 CURSOR_ENABLE 0 0 CURSOR_MODE 8 9 CURSOR_SNOOP 13 13 CURSOR_SYSTEM 14 14 CURSOR_PITCH 16 17 CURSOR_XY_POSITION_ROTATION_AND_MIRRORING_BYPASS 20 20 CURSOR_LINES_PER_CHUNK 24 28 CURSOR_PERFMON_LATENCY_MEASURE_EN 30 30 CURSOR_PERFMON_LATENCY_MEASURE_SEL 31 31 mmCURSOR3_CURSOR_SURFACE_ADDRESS 0 0x839 1 0 2 CURSOR_SURFACE_ADDRESS 0 31 mmCURSOR3_CURSOR_SURFACE_ADDRESS_HIGH 0 0x83a 1 0 2 CURSOR_SURFACE_ADDRESS_HIGH 0 15 mmCURSOR3_CURSOR_SIZE 0 0x83b 2 0 2 CURSOR_HEIGHT 0 8 CURSOR_WIDTH 16 24 mmCURSOR3_CURSOR_POSITION 0 0x83c 2 0 2 CURSOR_Y_POSITION 0 13 CURSOR_X_POSITION 16 29 mmCURSOR3_CURSOR_HOT_SPOT 0 0x83d 2 0 2 CURSOR_HOT_SPOT_Y 0 7 CURSOR_HOT_SPOT_X 16 23 mmCURSOR3_CURSOR_STEREO_CONTROL 0 0x83e 3 0 2 CURSOR_STEREO_EN 0 0 CURSOR_PRIMARY_OFFSET 4 17 CURSOR_SECONDARY_OFFSET 18 31 mmCURSOR3_CURSOR_DST_OFFSET 0 0x83f 1 0 2 CURSOR_DST_X_OFFSET 0 12 mmCURSOR3_CURSOR_MEM_PWR_CTRL 0 0x840 3 0 2 CROB_MEM_PWR_FORCE 0 1 CROB_MEM_PWR_DIS 2 2 CROB_MEM_PWR_LS_MODE 4 5 mmCURSOR3_CURSOR_MEM_PWR_STATUS 0 0x841 1 0 2 CROB_MEM_PWR_STATE 0 1 mmDC_PERFMON11_PERFCOUNTER_CNTL 0 0x85d 11 0 2 PERFCOUNTER_EVENT_SEL 0 8 PERFCOUNTER_CVALUE_SEL 9 11 PERFCOUNTER_INC_MODE 12 14 PERFCOUNTER_HW_CNTL_SEL 15 15 PERFCOUNTER_RUNEN_MODE 16 16 PERFCOUNTER_CNTOFF_START_DIS 22 22 PERFCOUNTER_RESTART_EN 23 23 PERFCOUNTER_INT_EN 24 24 PERFCOUNTER_OFF_MASK 25 25 PERFCOUNTER_ACTIVE 26 26 PERFCOUNTER_CNTL_SEL 29 31 mmDC_PERFMON11_PERFCOUNTER_CNTL2 0 0x85e 5 0 2 PERFCOUNTER_COUNTED_VALUE_TYPE 0 1 PERFCOUNTER_HW_STOP1_SEL 2 2 PERFCOUNTER_HW_STOP2_SEL 3 3 PERFCOUNTER_CNTOFF_SEL 8 13 PERFCOUNTER_CNTL2_SEL 29 31 mmDC_PERFMON11_PERFCOUNTER_STATE 0 0x85f 16 0 2 PERFCOUNTER_CNT0_STATE 0 1 PERFCOUNTER_STATE_SEL0 2 2 PERFCOUNTER_CNT1_STATE 4 5 PERFCOUNTER_STATE_SEL1 6 6 PERFCOUNTER_CNT2_STATE 8 9 PERFCOUNTER_STATE_SEL2 10 10 PERFCOUNTER_CNT3_STATE 12 13 PERFCOUNTER_STATE_SEL3 14 14 PERFCOUNTER_CNT4_STATE 16 17 PERFCOUNTER_STATE_SEL4 18 18 PERFCOUNTER_CNT5_STATE 20 21 PERFCOUNTER_STATE_SEL5 22 22 PERFCOUNTER_CNT6_STATE 24 25 PERFCOUNTER_STATE_SEL6 26 26 PERFCOUNTER_CNT7_STATE 28 29 PERFCOUNTER_STATE_SEL7 30 30 mmDC_PERFMON11_PERFMON_CNTL 0 0x860 6 0 2 PERFMON_STATE 0 1 PERFMON_RPT_COUNT 8 27 PERFMON_CNTOFF_AND_OR 28 28 PERFMON_CNTOFF_INT_EN 29 29 PERFMON_CNTOFF_INT_STATUS 30 30 PERFMON_CNTOFF_INT_ACK 31 31 mmDC_PERFMON11_PERFMON_CNTL2 0 0x861 4 0 2 PERFMON_CNTOFF_INT_TYPE 0 0 PERFMON_CLK_ENABLE 1 1 PERFMON_RUN_ENABLE_START_SEL 2 9 PERFMON_RUN_ENABLE_STOP_SEL 10 17 mmDC_PERFMON11_PERFMON_CVALUE_INT_MISC 0 0x862 17 0 2 PERFCOUNTER_INT0_STATUS 0 0 PERFCOUNTER_INT1_STATUS 1 1 PERFCOUNTER_INT2_STATUS 2 2 PERFCOUNTER_INT3_STATUS 3 3 PERFCOUNTER_INT4_STATUS 4 4 PERFCOUNTER_INT5_STATUS 5 5 PERFCOUNTER_INT6_STATUS 6 6 PERFCOUNTER_INT7_STATUS 7 7 PERFCOUNTER_INT0_ACK 8 8 PERFCOUNTER_INT1_ACK 9 9 PERFCOUNTER_INT2_ACK 10 10 PERFCOUNTER_INT3_ACK 11 11 PERFCOUNTER_INT4_ACK 12 12 PERFCOUNTER_INT5_ACK 13 13 PERFCOUNTER_INT6_ACK 14 14 PERFCOUNTER_INT7_ACK 15 15 PERFMON_CVALUE_HI 16 31 mmDC_PERFMON11_PERFMON_CVALUE_LOW 0 0x863 1 0 2 PERFMON_CVALUE_LOW 0 31 mmDC_PERFMON11_PERFMON_HI 0 0x864 2 0 2 PERFMON_HI 0 15 PERFMON_READ_SEL 29 31 mmDC_PERFMON11_PERFMON_LOW 0 0x865 1 0 2 PERFMON_LOW 0 31 mmDPP_TOP0_DPP_CONTROL 0 0xc3d 9 0 2 DPP_CLOCK_ENABLE 4 4 DPPCLK_G_GATE_DISABLE 8 8 DPPCLK_G_DYN_GATE_DISABLE 10 10 DPPCLK_G_DSCL_GATE_DISABLE 12 12 DPPCLK_R_GATE_DISABLE 16 16 DISPCLK_R_GATE_DISABLE 18 18 DISPCLK_G_GATE_DISABLE 20 20 DPPCLK_RATE_CONTROL 24 24 DPP_TEST_CLK_SEL 28 30 mmDPP_TOP0_DPP_SOFT_RESET 0 0xc3e 4 0 2 CNVC_SOFT_RESET 0 0 DSCL_SOFT_RESET 4 4 CM_SOFT_RESET 8 8 OBUF_SOFT_RESET 12 12 mmDPP_TOP0_DPP_CRC_VAL_R_G 0 0xc3f 2 0 2 DPP_CRC_R_CR 0 15 DPP_CRC_G_Y 16 31 mmDPP_TOP0_DPP_CRC_VAL_B_A 0 0xc40 2 0 2 DPP_CRC_B_CB 0 15 DPP_CRC_ALPHA 16 31 mmDPP_TOP0_DPP_CRC_CTRL 0 0xc41 11 0 2 DPP_CRC_EN 0 0 DPP_CRC_CONT_EN 1 1 DPP_CRC_ONE_SHOT_PENDING 2 2 DPP_CRC_420_COMP_SEL 3 3 DPP_CRC_SRC_SEL 4 5 DPP_CRC_STEREO_EN 7 7 DPP_CRC_STEREO_MODE 8 9 DPP_CRC_INTERLACE_MODE 10 11 DPP_CRC_PIX_FORMAT_SEL 12 14 DPP_CRC_CURSOR_FORMAT_SEL 15 15 DPP_CRC_MASK 16 31 mmDPP_TOP0_HOST_READ_CONTROL 0 0xc42 1 0 2 HOST_READ_RATE_CONTROL 0 7 mmCNVC_CFG0_CNVC_SURFACE_PIXEL_FORMAT 0 0xc47 1 0 2 CNVC_SURFACE_PIXEL_FORMAT 0 6 mmCNVC_CFG0_FORMAT_CONTROL 0 0xc48 6 0 2 FORMAT_EXPANSION_MODE 0 0 FORMAT_CNV16 4 4 ALPHA_EN 8 8 CNVC_BYPASS 12 12 OUTPUT_FP 16 16 CNVC_UPDATE_PENDING 20 20 mmCNVC_CFG0_FCNV_FP_SCALE_BIAS 0 0xc49 2 0 2 FCNV_FP_SCALE 0 15 FCNV_FP_BIAS 16 31 mmCNVC_CFG0_DENORM_CONTROL 0 0xc4a 4 0 2 DENORM_SCALE 0 14 CLAMP_POSITIVE 15 15 DENORM_BIAS 16 30 DENORM_TRUNCATE 31 31 mmCNVC_CFG0_COLOR_KEYER_CONTROL 0 0xc4c 2 0 2 COLOR_KEYER_EN 0 0 COLOR_KEYER_MODE 4 5 mmCNVC_CFG0_COLOR_KEYER_ALPHA 0 0xc4d 2 0 2 COLOR_KEYER_ALPHA_LOW 0 15 COLOR_KEYER_ALPHA_HIGH 16 31 mmCNVC_CFG0_COLOR_KEYER_RED 0 0xc4e 2 0 2 COLOR_KEYER_RED_LOW 0 15 COLOR_KEYER_RED_HIGH 16 31 mmCNVC_CFG0_COLOR_KEYER_GREEN 0 0xc4f 2 0 2 COLOR_KEYER_GREEN_LOW 0 15 COLOR_KEYER_GREEN_HIGH 16 31 mmCNVC_CFG0_COLOR_KEYER_BLUE 0 0xc50 2 0 2 COLOR_KEYER_BLUE_LOW 0 15 COLOR_KEYER_BLUE_HIGH 16 31 mmCNVC_CUR0_CURSOR0_CONTROL 0 0xc58 7 0 2 CUR0_ENABLE 0 0 CUR0_EXPANSION_MODE 1 1 CUR0_INVERT_MODE 2 2 CUR0_MODE 4 5 CUR0_UPDATE_PENDING 6 6 CUR0_MAX 8 19 CUR0_MIN 20 31 mmCNVC_CUR0_CURSOR0_COLOR0 0 0xc59 1 0 2 CUR0_COLOR0 0 23 mmCNVC_CUR0_CURSOR0_COLOR1 0 0xc5a 1 0 2 CUR0_COLOR1 0 23 mmCNVC_CUR0_CURSOR0_FP_SCALE_BIAS 0 0xc5b 2 0 2 CUR0_FP_SCALE 0 15 CUR0_FP_BIAS 16 31 mmDSCL0_SCL_COEF_RAM_TAP_SELECT 0 0xc62 3 0 2 SCL_COEF_RAM_TAP_PAIR_IDX 0 1 SCL_COEF_RAM_PHASE 8 13 SCL_COEF_RAM_FILTER_TYPE 16 18 mmDSCL0_SCL_COEF_RAM_TAP_DATA 0 0xc63 4 0 2 SCL_COEF_RAM_EVEN_TAP_COEF 0 13 SCL_COEF_RAM_EVEN_TAP_COEF_EN 15 15 SCL_COEF_RAM_ODD_TAP_COEF 16 29 SCL_COEF_RAM_ODD_TAP_COEF_EN 31 31 mmDSCL0_SCL_MODE 0 0xc64 6 0 2 DSCL_MODE 0 2 SCL_COEF_RAM_SELECT 8 8 SCL_COEF_RAM_SELECT_CURRENT 12 12 SCL_CHROMA_COEF_MODE 16 16 SCL_ALPHA_COEF_MODE 20 20 SCL_COEF_RAM_SELECT_RD 24 24 mmDSCL0_SCL_TAP_CONTROL 0 0xc65 4 0 2 SCL_V_NUM_TAPS 0 2 SCL_H_NUM_TAPS 4 6 SCL_V_NUM_TAPS_C 8 10 SCL_H_NUM_TAPS_C 12 14 mmDSCL0_DSCL_CONTROL 0 0xc66 1 0 2 SCL_BOUNDARY_MODE 0 0 mmDSCL0_DSCL_2TAP_CONTROL 0 0xc67 6 0 2 SCL_H_2TAP_HARDCODE_COEF_EN 0 0 SCL_H_2TAP_SHARP_EN 4 4 SCL_H_2TAP_SHARP_FACTOR 8 10 SCL_V_2TAP_HARDCODE_COEF_EN 16 16 SCL_V_2TAP_SHARP_EN 20 20 SCL_V_2TAP_SHARP_FACTOR 24 26 mmDSCL0_SCL_MANUAL_REPLICATE_CONTROL 0 0xc68 2 0 2 SCL_V_MANUAL_REPLICATE_FACTOR 0 3 SCL_H_MANUAL_REPLICATE_FACTOR 8 11 mmDSCL0_SCL_HORZ_FILTER_SCALE_RATIO 0 0xc69 1 0 2 SCL_H_SCALE_RATIO 0 25 mmDSCL0_SCL_HORZ_FILTER_INIT 0 0xc6a 2 0 2 SCL_H_INIT_FRAC 0 23 SCL_H_INIT_INT 24 27 mmDSCL0_SCL_HORZ_FILTER_SCALE_RATIO_C 0 0xc6b 1 0 2 SCL_H_SCALE_RATIO_C 0 25 mmDSCL0_SCL_HORZ_FILTER_INIT_C 0 0xc6c 2 0 2 SCL_H_INIT_FRAC_C 0 23 SCL_H_INIT_INT_C 24 27 mmDSCL0_SCL_VERT_FILTER_SCALE_RATIO 0 0xc6d 1 0 2 SCL_V_SCALE_RATIO 0 25 mmDSCL0_SCL_VERT_FILTER_INIT 0 0xc6e 2 0 2 SCL_V_INIT_FRAC 0 23 SCL_V_INIT_INT 24 27 mmDSCL0_SCL_VERT_FILTER_INIT_BOT 0 0xc6f 2 0 2 SCL_V_INIT_FRAC_BOT 0 23 SCL_V_INIT_INT_BOT 24 27 mmDSCL0_SCL_VERT_FILTER_SCALE_RATIO_C 0 0xc70 1 0 2 SCL_V_SCALE_RATIO_C 0 25 mmDSCL0_SCL_VERT_FILTER_INIT_C 0 0xc71 2 0 2 SCL_V_INIT_FRAC_C 0 23 SCL_V_INIT_INT_C 24 27 mmDSCL0_SCL_VERT_FILTER_INIT_BOT_C 0 0xc72 2 0 2 SCL_V_INIT_FRAC_BOT_C 0 23 SCL_V_INIT_INT_BOT_C 24 27 mmDSCL0_SCL_BLACK_OFFSET 0 0xc73 2 0 2 SCL_BLACK_OFFSET_RGB_Y 0 15 SCL_BLACK_OFFSET_CBCR 16 31 mmDSCL0_DSCL_UPDATE 0 0xc74 1 0 2 SCL_UPDATE_PENDING 0 0 mmDSCL0_DSCL_AUTOCAL 0 0xc75 3 0 2 AUTOCAL_MODE 0 1 AUTOCAL_NUM_PIPE 8 9 AUTOCAL_PIPE_ID 12 13 mmDSCL0_DSCL_EXT_OVERSCAN_LEFT_RIGHT 0 0xc76 2 0 2 EXT_OVERSCAN_RIGHT 0 12 EXT_OVERSCAN_LEFT 16 28 mmDSCL0_DSCL_EXT_OVERSCAN_TOP_BOTTOM 0 0xc77 2 0 2 EXT_OVERSCAN_BOTTOM 0 12 EXT_OVERSCAN_TOP 16 28 mmDSCL0_OTG_H_BLANK 0 0xc78 2 0 2 OTG_H_BLANK_START 0 13 OTG_H_BLANK_END 16 29 mmDSCL0_OTG_V_BLANK 0 0xc79 2 0 2 OTG_V_BLANK_START 0 13 OTG_V_BLANK_END 16 29 mmDSCL0_RECOUT_START 0 0xc7a 2 0 2 RECOUT_START_X 0 12 RECOUT_START_Y 16 28 mmDSCL0_RECOUT_SIZE 0 0xc7b 2 0 2 RECOUT_WIDTH 0 13 RECOUT_HEIGHT 16 29 mmDSCL0_MPC_SIZE 0 0xc7c 2 0 2 MPC_WIDTH 0 13 MPC_HEIGHT 16 29 mmDSCL0_LB_DATA_FORMAT 0 0xc7d 7 0 2 PIXEL_DEPTH 0 1 PIXEL_EXPAN_MODE 8 8 PIXEL_REDUCE_MODE 12 12 DYNAMIC_PIXEL_DEPTH 16 16 DITHER_EN 20 20 INTERLEAVE_EN 24 24 ALPHA_EN 31 31 mmDSCL0_LB_MEMORY_CTRL 0 0xc7e 4 0 2 MEMORY_CONFIG 0 1 LB_MAX_PARTITIONS 8 13 LB_NUM_PARTITIONS 16 22 LB_NUM_PARTITIONS_C 24 30 mmDSCL0_LB_V_COUNTER 0 0xc7f 2 0 2 V_COUNTER 0 12 V_COUNTER_C 16 28 mmDSCL0_DSCL_MEM_PWR_CTRL 0 0xc80 14 0 2 LUT_MEM_PWR_FORCE 0 1 LUT_MEM_PWR_DIS 2 2 LB_G1_MEM_PWR_FORCE 4 5 LB_G1_MEM_PWR_DIS 6 6 LB_G2_MEM_PWR_FORCE 8 9 LB_G2_MEM_PWR_DIS 10 10 LB_G3_MEM_PWR_FORCE 12 13 LB_G3_MEM_PWR_DIS 14 14 LB_G4_MEM_PWR_FORCE 16 17 LB_G4_MEM_PWR_DIS 18 18 LB_G5_MEM_PWR_FORCE 20 21 LB_G5_MEM_PWR_DIS 22 22 LB_G6_MEM_PWR_FORCE 24 25 LB_G6_MEM_PWR_DIS 26 26 mmDSCL0_DSCL_MEM_PWR_STATUS 0 0xc81 7 0 2 LUT_MEM_PWR_STATE 0 1 LB_G1_MEM_PWR_STATE 2 3 LB_G2_MEM_PWR_STATE 4 5 LB_G3_MEM_PWR_STATE 6 7 LB_G4_MEM_PWR_STATE 8 9 LB_G5_MEM_PWR_STATE 10 11 LB_G6_MEM_PWR_STATE 12 13 mmDSCL0_OBUF_CONTROL 0 0xc82 7 0 2 OBUF_BYPASS 0 0 OBUF_USE_FULL_BUFFER 4 4 OBUF_H_2X_UPSCALE_EN 8 8 OBUF_IS_HALF_RECOUT_WIDTH 12 12 OBUF_H_2X_COEF_PHASE0_SEL 16 16 OBUF_H_2X_COEF_PHASE1_SEL 24 24 OBUF_OUT_HOLD_CNT 28 31 mmDSCL0_OBUF_MEM_PWR_CTRL 0 0xc83 3 0 2 OBUF_MEM_PWR_FORCE 0 1 OBUF_MEM_PWR_DIS 2 2 OBUF_MEM_PWR_STATE 16 17 mmCM0_CM_CONTROL 0 0xc92 2 0 2 CM_BYPASS_EN 0 0 CM_UPDATE_PENDING 8 8 mmCM0_CM_COMA_C11_C12 0 0xc93 2 0 2 CM_COMA_C11 0 15 CM_COMA_C12 16 31 mmCM0_CM_COMA_C13_C14 0 0xc94 2 0 2 CM_COMA_C13 0 15 CM_COMA_C14 16 31 mmCM0_CM_COMA_C21_C22 0 0xc95 2 0 2 CM_COMA_C21 0 15 CM_COMA_C22 16 31 mmCM0_CM_COMA_C23_C24 0 0xc96 2 0 2 CM_COMA_C23 0 15 CM_COMA_C24 16 31 mmCM0_CM_COMA_C31_C32 0 0xc97 2 0 2 CM_COMA_C31 0 15 CM_COMA_C32 16 31 mmCM0_CM_COMA_C33_C34 0 0xc98 2 0 2 CM_COMA_C33 0 15 CM_COMA_C34 16 31 mmCM0_CM_COMB_C11_C12 0 0xc99 2 0 2 CM_COMB_C11 0 15 CM_COMB_C12 16 31 mmCM0_CM_COMB_C13_C14 0 0xc9a 2 0 2 CM_COMB_C13 0 15 CM_COMB_C14 16 31 mmCM0_CM_COMB_C21_C22 0 0xc9b 2 0 2 CM_COMB_C21 0 15 CM_COMB_C22 16 31 mmCM0_CM_COMB_C23_C24 0 0xc9c 2 0 2 CM_COMB_C23 0 15 CM_COMB_C24 16 31 mmCM0_CM_COMB_C31_C32 0 0xc9d 2 0 2 CM_COMB_C31 0 15 CM_COMB_C32 16 31 mmCM0_CM_COMB_C33_C34 0 0xc9e 2 0 2 CM_COMB_C33 0 15 CM_COMB_C34 16 31 mmCM0_CM_IGAM_CONTROL 0 0xc9f 14 0 2 CM_IGAM_LUT_MODE 0 1 CM_IGAM_LUT_DATA_SIGNED_EN_B 2 2 CM_IGAM_LUT_DATA_SIGNED_EN_G 3 3 CM_IGAM_LUT_DATA_SIGNED_EN_R 4 4 CM_IGAM_LUT_INC_B 5 8 CM_IGAM_LUT_INC_G 9 12 CM_IGAM_LUT_INC_R 13 16 CM_IGAM_LUT_FORMAT_B 17 18 CM_IGAM_LUT_FORMAT_G 19 20 CM_IGAM_LUT_FORMAT_R 21 22 CM_IGAM_LUT_B_FLOAT_POINT_EN 23 23 CM_IGAM_LUT_G_FLOAT_POINT_EN 24 24 CM_IGAM_LUT_R_FLOAT_POINT_EN 25 25 CM_IGAM_INPUT_FORMAT 26 27 mmCM0_CM_IGAM_LUT_RW_CONTROL 0 0xca0 5 0 2 CM_IGAM_LUT_RW_MODE 0 0 CM_IGAM_LUT_WRITE_EN_MASK 4 6 CM_IGAM_LUT_SEL 8 8 CM_IGAM_LUT_HOST_EN 12 12 CM_IGAM_DGAM_CONFIG_STATUS 16 19 mmCM0_CM_IGAM_LUT_RW_INDEX 0 0xca1 1 0 2 CM_IGAM_LUT_RW_INDEX 0 7 mmCM0_CM_IGAM_LUT_SEQ_COLOR 0 0xca2 1 0 2 CM_IGAM_LUT_SEQ_COLOR 0 15 mmCM0_CM_IGAM_LUT_30_COLOR 0 0xca3 3 0 2 CM_IGAM_LUT_10_BLUE 0 9 CM_IGAM_LUT_10_GREEN 10 19 CM_IGAM_LUT_10_RED 20 29 mmCM0_CM_IGAM_LUT_PWL_DATA 0 0xca4 2 0 2 CM_IGAM_LUT_PWL_BASE 0 15 CM_IGAM_LUT_PWL_DELTA 16 31 mmCM0_CM_IGAM_LUT_AUTOFILL 0 0xca5 2 0 2 CM_IGAM_LUT_AUTOFILL 0 0 CM_IGAM_LUT_AUTOFILL_DONE 4 4 mmCM0_CM_IGAM_LUT_BW_OFFSET_BLUE 0 0xca6 2 0 2 CM_IGAM_LUT_BLACK_OFFSET_BLUE 0 15 CM_IGAM_LUT_WHITE_OFFSET_BLUE 16 31 mmCM0_CM_IGAM_LUT_BW_OFFSET_GREEN 0 0xca7 2 0 2 CM_IGAM_LUT_BLACK_OFFSET_GREEN 0 15 CM_IGAM_LUT_WHITE_OFFSET_GREEN 16 31 mmCM0_CM_IGAM_LUT_BW_OFFSET_RED 0 0xca8 2 0 2 CM_IGAM_LUT_BLACK_OFFSET_RED 0 15 CM_IGAM_LUT_WHITE_OFFSET_RED 16 31 mmCM0_CM_ICSC_CONTROL 0 0xca9 1 0 2 CM_ICSC_MODE 0 1 mmCM0_CM_ICSC_C11_C12 0 0xcaa 2 0 2 CM_ICSC_C11 0 15 CM_ICSC_C12 16 31 mmCM0_CM_ICSC_C13_C14 0 0xcab 2 0 2 CM_ICSC_C13 0 15 CM_ICSC_C14 16 31 mmCM0_CM_ICSC_C21_C22 0 0xcac 2 0 2 CM_ICSC_C21 0 15 CM_ICSC_C22 16 31 mmCM0_CM_ICSC_C23_C24 0 0xcad 2 0 2 CM_ICSC_C23 0 15 CM_ICSC_C24 16 31 mmCM0_CM_ICSC_C31_C32 0 0xcae 2 0 2 CM_ICSC_C31 0 15 CM_ICSC_C32 16 31 mmCM0_CM_ICSC_C33_C34 0 0xcaf 2 0 2 CM_ICSC_C33 0 15 CM_ICSC_C34 16 31 mmCM0_CM_GAMUT_REMAP_CONTROL 0 0xcb0 1 0 2 CM_GAMUT_REMAP_MODE 0 1 mmCM0_CM_GAMUT_REMAP_C11_C12 0 0xcb1 2 0 2 CM_GAMUT_REMAP_C11 0 15 CM_GAMUT_REMAP_C12 16 31 mmCM0_CM_GAMUT_REMAP_C13_C14 0 0xcb2 2 0 2 CM_GAMUT_REMAP_C13 0 15 CM_GAMUT_REMAP_C14 16 31 mmCM0_CM_GAMUT_REMAP_C21_C22 0 0xcb3 2 0 2 CM_GAMUT_REMAP_C21 0 15 CM_GAMUT_REMAP_C22 16 31 mmCM0_CM_GAMUT_REMAP_C23_C24 0 0xcb4 2 0 2 CM_GAMUT_REMAP_C23 0 15 CM_GAMUT_REMAP_C24 16 31 mmCM0_CM_GAMUT_REMAP_C31_C32 0 0xcb5 2 0 2 CM_GAMUT_REMAP_C31 0 15 CM_GAMUT_REMAP_C32 16 31 mmCM0_CM_GAMUT_REMAP_C33_C34 0 0xcb6 2 0 2 CM_GAMUT_REMAP_C33 0 15 CM_GAMUT_REMAP_C34 16 31 mmCM0_CM_OCSC_CONTROL 0 0xcb7 1 0 2 CM_OCSC_MODE 0 2 mmCM0_CM_OCSC_C11_C12 0 0xcb8 2 0 2 CM_OCSC_C11 0 15 CM_OCSC_C12 16 31 mmCM0_CM_OCSC_C13_C14 0 0xcb9 2 0 2 CM_OCSC_C13 0 15 CM_OCSC_C14 16 31 mmCM0_CM_OCSC_C21_C22 0 0xcba 2 0 2 CM_OCSC_C21 0 15 CM_OCSC_C22 16 31 mmCM0_CM_OCSC_C23_C24 0 0xcbb 2 0 2 CM_OCSC_C23 0 15 CM_OCSC_C24 16 31 mmCM0_CM_OCSC_C31_C32 0 0xcbc 2 0 2 CM_OCSC_C31 0 15 CM_OCSC_C32 16 31 mmCM0_CM_OCSC_C33_C34 0 0xcbd 2 0 2 CM_OCSC_C33 0 15 CM_OCSC_C34 16 31 mmCM0_CM_BNS_VALUES_R 0 0xcbe 2 0 2 CM_BNS_BIAS_R 0 15 CM_BNS_SCALE_R 16 31 mmCM0_CM_BNS_VALUES_G 0 0xcbf 2 0 2 CM_BNS_BIAS_G 0 15 CM_BNS_SCALE_G 16 31 mmCM0_CM_BNS_VALUES_B 0 0xcc0 2 0 2 CM_BNS_BIAS_B 0 15 CM_BNS_SCALE_B 16 31 mmCM0_CM_DGAM_CONTROL 0 0xcc1 1 0 2 CM_DGAM_LUT_MODE 0 2 mmCM0_CM_DGAM_LUT_INDEX 0 0xcc2 1 0 2 CM_DGAM_LUT_INDEX 0 8 mmCM0_CM_DGAM_LUT_DATA 0 0xcc3 1 0 2 CM_DGAM_LUT_DATA 0 18 mmCM0_CM_DGAM_LUT_WRITE_EN_MASK 0 0xcc4 2 0 2 CM_DGAM_LUT_WRITE_EN_MASK 0 2 CM_DGAM_LUT_WRITE_SEL 4 4 mmCM0_CM_DGAM_RAMA_START_CNTL_B 0 0xcc5 2 0 2 CM_DGAM_RAMA_EXP_REGION_START_B 0 17 CM_DGAM_RAMA_EXP_REGION_START_SEGMENT_B 20 26 mmCM0_CM_DGAM_RAMA_START_CNTL_G 0 0xcc6 2 0 2 CM_DGAM_RAMA_EXP_REGION_START_G 0 17 CM_DGAM_RAMA_EXP_REGION_START_SEGMENT_G 20 26 mmCM0_CM_DGAM_RAMA_START_CNTL_R 0 0xcc7 2 0 2 CM_DGAM_RAMA_EXP_REGION_START_R 0 17 CM_DGAM_RAMA_EXP_REGION_START_SEGMENT_R 20 26 mmCM0_CM_DGAM_RAMA_SLOPE_CNTL_B 0 0xcc8 1 0 2 CM_DGAM_RAMA_EXP_REGION_LINEAR_SLOPE_B 0 17 mmCM0_CM_DGAM_RAMA_SLOPE_CNTL_G 0 0xcc9 1 0 2 CM_DGAM_RAMA_EXP_REGION_LINEAR_SLOPE_G 0 17 mmCM0_CM_DGAM_RAMA_SLOPE_CNTL_R 0 0xcca 1 0 2 CM_DGAM_RAMA_EXP_REGION_LINEAR_SLOPE_R 0 17 mmCM0_CM_DGAM_RAMA_END_CNTL1_B 0 0xccb 1 0 2 CM_DGAM_RAMA_EXP_REGION_END_B 0 15 mmCM0_CM_DGAM_RAMA_END_CNTL2_B 0 0xccc 2 0 2 CM_DGAM_RAMA_EXP_REGION_END_SLOPE_B 0 15 CM_DGAM_RAMA_EXP_REGION_END_BASE_B 16 31 mmCM0_CM_DGAM_RAMA_END_CNTL1_G 0 0xccd 1 0 2 CM_DGAM_RAMA_EXP_REGION_END_G 0 15 mmCM0_CM_DGAM_RAMA_END_CNTL2_G 0 0xcce 2 0 2 CM_DGAM_RAMA_EXP_REGION_END_SLOPE_G 0 15 CM_DGAM_RAMA_EXP_REGION_END_BASE_G 16 31 mmCM0_CM_DGAM_RAMA_END_CNTL1_R 0 0xccf 1 0 2 CM_DGAM_RAMA_EXP_REGION_END_R 0 15 mmCM0_CM_DGAM_RAMA_END_CNTL2_R 0 0xcd0 2 0 2 CM_DGAM_RAMA_EXP_REGION_END_SLOPE_R 0 15 CM_DGAM_RAMA_EXP_REGION_END_BASE_R 16 31 mmCM0_CM_DGAM_RAMA_REGION_0_1 0 0xcd1 4 0 2 CM_DGAM_RAMA_EXP_REGION0_LUT_OFFSET 0 8 CM_DGAM_RAMA_EXP_REGION0_NUM_SEGMENTS 12 14 CM_DGAM_RAMA_EXP_REGION1_LUT_OFFSET 16 24 CM_DGAM_RAMA_EXP_REGION1_NUM_SEGMENTS 28 30 mmCM0_CM_DGAM_RAMA_REGION_2_3 0 0xcd2 4 0 2 CM_DGAM_RAMA_EXP_REGION2_LUT_OFFSET 0 8 CM_DGAM_RAMA_EXP_REGION2_NUM_SEGMENTS 12 14 CM_DGAM_RAMA_EXP_REGION3_LUT_OFFSET 16 24 CM_DGAM_RAMA_EXP_REGION3_NUM_SEGMENTS 28 30 mmCM0_CM_DGAM_RAMA_REGION_4_5 0 0xcd3 4 0 2 CM_DGAM_RAMA_EXP_REGION4_LUT_OFFSET 0 8 CM_DGAM_RAMA_EXP_REGION4_NUM_SEGMENTS 12 14 CM_DGAM_RAMA_EXP_REGION5_LUT_OFFSET 16 24 CM_DGAM_RAMA_EXP_REGION5_NUM_SEGMENTS 28 30 mmCM0_CM_DGAM_RAMA_REGION_6_7 0 0xcd4 4 0 2 CM_DGAM_RAMA_EXP_REGION6_LUT_OFFSET 0 8 CM_DGAM_RAMA_EXP_REGION6_NUM_SEGMENTS 12 14 CM_DGAM_RAMA_EXP_REGION7_LUT_OFFSET 16 24 CM_DGAM_RAMA_EXP_REGION7_NUM_SEGMENTS 28 30 mmCM0_CM_DGAM_RAMA_REGION_8_9 0 0xcd5 4 0 2 CM_DGAM_RAMA_EXP_REGION8_LUT_OFFSET 0 8 CM_DGAM_RAMA_EXP_REGION8_NUM_SEGMENTS 12 14 CM_DGAM_RAMA_EXP_REGION9_LUT_OFFSET 16 24 CM_DGAM_RAMA_EXP_REGION9_NUM_SEGMENTS 28 30 mmCM0_CM_DGAM_RAMA_REGION_10_11 0 0xcd6 4 0 2 CM_DGAM_RAMA_EXP_REGION10_LUT_OFFSET 0 8 CM_DGAM_RAMA_EXP_REGION10_NUM_SEGMENTS 12 14 CM_DGAM_RAMA_EXP_REGION11_LUT_OFFSET 16 24 CM_DGAM_RAMA_EXP_REGION11_NUM_SEGMENTS 28 30 mmCM0_CM_DGAM_RAMA_REGION_12_13 0 0xcd7 4 0 2 CM_DGAM_RAMA_EXP_REGION12_LUT_OFFSET 0 8 CM_DGAM_RAMA_EXP_REGION12_NUM_SEGMENTS 12 14 CM_DGAM_RAMA_EXP_REGION13_LUT_OFFSET 16 24 CM_DGAM_RAMA_EXP_REGION13_NUM_SEGMENTS 28 30 mmCM0_CM_DGAM_RAMA_REGION_14_15 0 0xcd8 4 0 2 CM_DGAM_RAMA_EXP_REGION14_LUT_OFFSET 0 8 CM_DGAM_RAMA_EXP_REGION14_NUM_SEGMENTS 12 14 CM_DGAM_RAMA_EXP_REGION15_LUT_OFFSET 16 24 CM_DGAM_RAMA_EXP_REGION15_NUM_SEGMENTS 28 30 mmCM0_CM_DGAM_RAMB_START_CNTL_B 0 0xcd9 2 0 2 CM_DGAM_RAMB_EXP_REGION_START_B 0 17 CM_DGAM_RAMB_EXP_REGION_START_SEGMENT_B 20 26 mmCM0_CM_DGAM_RAMB_START_CNTL_G 0 0xcda 2 0 2 CM_DGAM_RAMB_EXP_REGION_START_G 0 17 CM_DGAM_RAMB_EXP_REGION_START_SEGMENT_G 20 26 mmCM0_CM_DGAM_RAMB_START_CNTL_R 0 0xcdb 2 0 2 CM_DGAM_RAMB_EXP_REGION_START_R 0 17 CM_DGAM_RAMB_EXP_REGION_START_SEGMENT_R 20 26 mmCM0_CM_DGAM_RAMB_SLOPE_CNTL_B 0 0xcdc 1 0 2 CM_DGAM_RAMB_EXP_REGION_LINEAR_SLOPE_B 0 17 mmCM0_CM_DGAM_RAMB_SLOPE_CNTL_G 0 0xcdd 1 0 2 CM_DGAM_RAMB_EXP_REGION_LINEAR_SLOPE_G 0 17 mmCM0_CM_DGAM_RAMB_SLOPE_CNTL_R 0 0xcde 1 0 2 CM_DGAM_RAMB_EXP_REGION_LINEAR_SLOPE_R 0 17 mmCM0_CM_DGAM_RAMB_END_CNTL1_B 0 0xcdf 1 0 2 CM_DGAM_RAMB_EXP_REGION_END_B 0 15 mmCM0_CM_DGAM_RAMB_END_CNTL2_B 0 0xce0 2 0 2 CM_DGAM_RAMB_EXP_REGION_END_SLOPE_B 0 15 CM_DGAM_RAMB_EXP_REGION_END_BASE_B 16 31 mmCM0_CM_DGAM_RAMB_END_CNTL1_G 0 0xce1 1 0 2 CM_DGAM_RAMB_EXP_REGION_END_G 0 15 mmCM0_CM_DGAM_RAMB_END_CNTL2_G 0 0xce2 2 0 2 CM_DGAM_RAMB_EXP_REGION_END_SLOPE_G 0 15 CM_DGAM_RAMB_EXP_REGION_END_BASE_G 16 31 mmCM0_CM_DGAM_RAMB_END_CNTL1_R 0 0xce3 1 0 2 CM_DGAM_RAMB_EXP_REGION_END_R 0 15 mmCM0_CM_DGAM_RAMB_END_CNTL2_R 0 0xce4 2 0 2 CM_DGAM_RAMB_EXP_REGION_END_SLOPE_R 0 15 CM_DGAM_RAMB_EXP_REGION_END_BASE_R 16 31 mmCM0_CM_DGAM_RAMB_REGION_0_1 0 0xce5 4 0 2 CM_DGAM_RAMB_EXP_REGION0_LUT_OFFSET 0 8 CM_DGAM_RAMB_EXP_REGION0_NUM_SEGMENTS 12 14 CM_DGAM_RAMB_EXP_REGION1_LUT_OFFSET 16 24 CM_DGAM_RAMB_EXP_REGION1_NUM_SEGMENTS 28 30 mmCM0_CM_DGAM_RAMB_REGION_2_3 0 0xce6 4 0 2 CM_DGAM_RAMB_EXP_REGION2_LUT_OFFSET 0 8 CM_DGAM_RAMB_EXP_REGION2_NUM_SEGMENTS 12 14 CM_DGAM_RAMB_EXP_REGION3_LUT_OFFSET 16 24 CM_DGAM_RAMB_EXP_REGION3_NUM_SEGMENTS 28 30 mmCM0_CM_DGAM_RAMB_REGION_4_5 0 0xce7 4 0 2 CM_DGAM_RAMB_EXP_REGION4_LUT_OFFSET 0 8 CM_DGAM_RAMB_EXP_REGION4_NUM_SEGMENTS 12 14 CM_DGAM_RAMB_EXP_REGION5_LUT_OFFSET 16 24 CM_DGAM_RAMB_EXP_REGION5_NUM_SEGMENTS 28 30 mmCM0_CM_DGAM_RAMB_REGION_6_7 0 0xce8 4 0 2 CM_DGAM_RAMB_EXP_REGION6_LUT_OFFSET 0 8 CM_DGAM_RAMB_EXP_REGION6_NUM_SEGMENTS 12 14 CM_DGAM_RAMB_EXP_REGION7_LUT_OFFSET 16 24 CM_DGAM_RAMB_EXP_REGION7_NUM_SEGMENTS 28 30 mmCM0_CM_DGAM_RAMB_REGION_8_9 0 0xce9 4 0 2 CM_DGAM_RAMB_EXP_REGION8_LUT_OFFSET 0 8 CM_DGAM_RAMB_EXP_REGION8_NUM_SEGMENTS 12 14 CM_DGAM_RAMB_EXP_REGION9_LUT_OFFSET 16 24 CM_DGAM_RAMB_EXP_REGION9_NUM_SEGMENTS 28 30 mmCM0_CM_DGAM_RAMB_REGION_10_11 0 0xcea 4 0 2 CM_DGAM_RAMB_EXP_REGION10_LUT_OFFSET 0 8 CM_DGAM_RAMB_EXP_REGION10_NUM_SEGMENTS 12 14 CM_DGAM_RAMB_EXP_REGION11_LUT_OFFSET 16 24 CM_DGAM_RAMB_EXP_REGION11_NUM_SEGMENTS 28 30 mmCM0_CM_DGAM_RAMB_REGION_12_13 0 0xceb 4 0 2 CM_DGAM_RAMB_EXP_REGION12_LUT_OFFSET 0 8 CM_DGAM_RAMB_EXP_REGION12_NUM_SEGMENTS 12 14 CM_DGAM_RAMB_EXP_REGION13_LUT_OFFSET 16 24 CM_DGAM_RAMB_EXP_REGION13_NUM_SEGMENTS 28 30 mmCM0_CM_DGAM_RAMB_REGION_14_15 0 0xcec 4 0 2 CM_DGAM_RAMB_EXP_REGION14_LUT_OFFSET 0 8 CM_DGAM_RAMB_EXP_REGION14_NUM_SEGMENTS 12 14 CM_DGAM_RAMB_EXP_REGION15_LUT_OFFSET 16 24 CM_DGAM_RAMB_EXP_REGION15_NUM_SEGMENTS 28 30 mmCM0_CM_RGAM_CONTROL 0 0xced 1 0 2 CM_RGAM_LUT_MODE 0 2 mmCM0_CM_RGAM_LUT_INDEX 0 0xcee 1 0 2 CM_RGAM_LUT_INDEX 0 8 mmCM0_CM_RGAM_LUT_DATA 0 0xcef 1 0 2 CM_RGAM_LUT_DATA 0 18 mmCM0_CM_RGAM_LUT_WRITE_EN_MASK 0 0xcf0 3 0 2 CM_RGAM_LUT_WRITE_EN_MASK 0 2 CM_RGAM_LUT_WRITE_SEL 4 4 CM_RGAM_CONFIG_STATUS 8 10 mmCM0_CM_RGAM_RAMA_START_CNTL_B 0 0xcf1 2 0 2 CM_RGAM_RAMA_EXP_REGION_START_B 0 17 CM_RGAM_RAMA_EXP_REGION_START_SEGMENT_B 20 26 mmCM0_CM_RGAM_RAMA_START_CNTL_G 0 0xcf2 2 0 2 CM_RGAM_RAMA_EXP_REGION_START_G 0 17 CM_RGAM_RAMA_EXP_REGION_START_SEGMENT_G 20 26 mmCM0_CM_RGAM_RAMA_START_CNTL_R 0 0xcf3 2 0 2 CM_RGAM_RAMA_EXP_REGION_START_R 0 17 CM_RGAM_RAMA_EXP_REGION_START_SEGMENT_R 20 26 mmCM0_CM_RGAM_RAMA_SLOPE_CNTL_B 0 0xcf4 1 0 2 CM_RGAM_RAMA_EXP_REGION_LINEAR_SLOPE_B 0 17 mmCM0_CM_RGAM_RAMA_SLOPE_CNTL_G 0 0xcf5 1 0 2 CM_RGAM_RAMA_EXP_REGION_LINEAR_SLOPE_G 0 17 mmCM0_CM_RGAM_RAMA_SLOPE_CNTL_R 0 0xcf6 1 0 2 CM_RGAM_RAMA_EXP_REGION_LINEAR_SLOPE_R 0 17 mmCM0_CM_RGAM_RAMA_END_CNTL1_B 0 0xcf7 1 0 2 CM_RGAM_RAMA_EXP_REGION_END_B 0 15 mmCM0_CM_RGAM_RAMA_END_CNTL2_B 0 0xcf8 2 0 2 CM_RGAM_RAMA_EXP_REGION_END_SLOPE_B 0 15 CM_RGAM_RAMA_EXP_REGION_END_BASE_B 16 31 mmCM0_CM_RGAM_RAMA_END_CNTL1_G 0 0xcf9 1 0 2 CM_RGAM_RAMA_EXP_REGION_END_G 0 15 mmCM0_CM_RGAM_RAMA_END_CNTL2_G 0 0xcfa 2 0 2 CM_RGAM_RAMA_EXP_REGION_END_SLOPE_G 0 15 CM_RGAM_RAMA_EXP_REGION_END_BASE_G 16 31 mmCM0_CM_RGAM_RAMA_END_CNTL1_R 0 0xcfb 1 0 2 CM_RGAM_RAMA_EXP_REGION_END_R 0 15 mmCM0_CM_RGAM_RAMA_END_CNTL2_R 0 0xcfc 2 0 2 CM_RGAM_RAMA_EXP_REGION_END_SLOPE_R 0 15 CM_RGAM_RAMA_EXP_REGION_END_BASE_R 16 31 mmCM0_CM_RGAM_RAMA_REGION_0_1 0 0xcfd 4 0 2 CM_RGAM_RAMA_EXP_REGION0_LUT_OFFSET 0 8 CM_RGAM_RAMA_EXP_REGION0_NUM_SEGMENTS 12 14 CM_RGAM_RAMA_EXP_REGION1_LUT_OFFSET 16 24 CM_RGAM_RAMA_EXP_REGION1_NUM_SEGMENTS 28 30 mmCM0_CM_RGAM_RAMA_REGION_2_3 0 0xcfe 4 0 2 CM_RGAM_RAMA_EXP_REGION2_LUT_OFFSET 0 8 CM_RGAM_RAMA_EXP_REGION2_NUM_SEGMENTS 12 14 CM_RGAM_RAMA_EXP_REGION3_LUT_OFFSET 16 24 CM_RGAM_RAMA_EXP_REGION3_NUM_SEGMENTS 28 30 mmCM0_CM_RGAM_RAMA_REGION_4_5 0 0xcff 4 0 2 CM_RGAM_RAMA_EXP_REGION4_LUT_OFFSET 0 8 CM_RGAM_RAMA_EXP_REGION4_NUM_SEGMENTS 12 14 CM_RGAM_RAMA_EXP_REGION5_LUT_OFFSET 16 24 CM_RGAM_RAMA_EXP_REGION5_NUM_SEGMENTS 28 30 mmCM0_CM_RGAM_RAMA_REGION_6_7 0 0xd00 4 0 2 CM_RGAM_RAMA_EXP_REGION6_LUT_OFFSET 0 8 CM_RGAM_RAMA_EXP_REGION6_NUM_SEGMENTS 12 14 CM_RGAM_RAMA_EXP_REGION7_LUT_OFFSET 16 24 CM_RGAM_RAMA_EXP_REGION7_NUM_SEGMENTS 28 30 mmCM0_CM_RGAM_RAMA_REGION_8_9 0 0xd01 4 0 2 CM_RGAM_RAMA_EXP_REGION8_LUT_OFFSET 0 8 CM_RGAM_RAMA_EXP_REGION8_NUM_SEGMENTS 12 14 CM_RGAM_RAMA_EXP_REGION9_LUT_OFFSET 16 24 CM_RGAM_RAMA_EXP_REGION9_NUM_SEGMENTS 28 30 mmCM0_CM_RGAM_RAMA_REGION_10_11 0 0xd02 4 0 2 CM_RGAM_RAMA_EXP_REGION10_LUT_OFFSET 0 8 CM_RGAM_RAMA_EXP_REGION10_NUM_SEGMENTS 12 14 CM_RGAM_RAMA_EXP_REGION11_LUT_OFFSET 16 24 CM_RGAM_RAMA_EXP_REGION11_NUM_SEGMENTS 28 30 mmCM0_CM_RGAM_RAMA_REGION_12_13 0 0xd03 4 0 2 CM_RGAM_RAMA_EXP_REGION12_LUT_OFFSET 0 8 CM_RGAM_RAMA_EXP_REGION12_NUM_SEGMENTS 12 14 CM_RGAM_RAMA_EXP_REGION13_LUT_OFFSET 16 24 CM_RGAM_RAMA_EXP_REGION13_NUM_SEGMENTS 28 30 mmCM0_CM_RGAM_RAMA_REGION_14_15 0 0xd04 4 0 2 CM_RGAM_RAMA_EXP_REGION14_LUT_OFFSET 0 8 CM_RGAM_RAMA_EXP_REGION14_NUM_SEGMENTS 12 14 CM_RGAM_RAMA_EXP_REGION15_LUT_OFFSET 16 24 CM_RGAM_RAMA_EXP_REGION15_NUM_SEGMENTS 28 30 mmCM0_CM_RGAM_RAMA_REGION_16_17 0 0xd05 4 0 2 CM_RGAM_RAMA_EXP_REGION16_LUT_OFFSET 0 8 CM_RGAM_RAMA_EXP_REGION16_NUM_SEGMENTS 12 14 CM_RGAM_RAMA_EXP_REGION17_LUT_OFFSET 16 24 CM_RGAM_RAMA_EXP_REGION17_NUM_SEGMENTS 28 30 mmCM0_CM_RGAM_RAMA_REGION_18_19 0 0xd06 4 0 2 CM_RGAM_RAMA_EXP_REGION18_LUT_OFFSET 0 8 CM_RGAM_RAMA_EXP_REGION18_NUM_SEGMENTS 12 14 CM_RGAM_RAMA_EXP_REGION19_LUT_OFFSET 16 24 CM_RGAM_RAMA_EXP_REGION19_NUM_SEGMENTS 28 30 mmCM0_CM_RGAM_RAMA_REGION_20_21 0 0xd07 4 0 2 CM_RGAM_RAMA_EXP_REGION20_LUT_OFFSET 0 8 CM_RGAM_RAMA_EXP_REGION20_NUM_SEGMENTS 12 14 CM_RGAM_RAMA_EXP_REGION21_LUT_OFFSET 16 24 CM_RGAM_RAMA_EXP_REGION21_NUM_SEGMENTS 28 30 mmCM0_CM_RGAM_RAMA_REGION_22_23 0 0xd08 4 0 2 CM_RGAM_RAMA_EXP_REGION22_LUT_OFFSET 0 8 CM_RGAM_RAMA_EXP_REGION22_NUM_SEGMENTS 12 14 CM_RGAM_RAMA_EXP_REGION23_LUT_OFFSET 16 24 CM_RGAM_RAMA_EXP_REGION23_NUM_SEGMENTS 28 30 mmCM0_CM_RGAM_RAMA_REGION_24_25 0 0xd09 4 0 2 CM_RGAM_RAMA_EXP_REGION24_LUT_OFFSET 0 8 CM_RGAM_RAMA_EXP_REGION24_NUM_SEGMENTS 12 14 CM_RGAM_RAMA_EXP_REGION25_LUT_OFFSET 16 24 CM_RGAM_RAMA_EXP_REGION25_NUM_SEGMENTS 28 30 mmCM0_CM_RGAM_RAMA_REGION_26_27 0 0xd0a 4 0 2 CM_RGAM_RAMA_EXP_REGION26_LUT_OFFSET 0 8 CM_RGAM_RAMA_EXP_REGION26_NUM_SEGMENTS 12 14 CM_RGAM_RAMA_EXP_REGION27_LUT_OFFSET 16 24 CM_RGAM_RAMA_EXP_REGION27_NUM_SEGMENTS 28 30 mmCM0_CM_RGAM_RAMA_REGION_28_29 0 0xd0b 4 0 2 CM_RGAM_RAMA_EXP_REGION28_LUT_OFFSET 0 8 CM_RGAM_RAMA_EXP_REGION28_NUM_SEGMENTS 12 14 CM_RGAM_RAMA_EXP_REGION29_LUT_OFFSET 16 24 CM_RGAM_RAMA_EXP_REGION29_NUM_SEGMENTS 28 30 mmCM0_CM_RGAM_RAMA_REGION_30_31 0 0xd0c 4 0 2 CM_RGAM_RAMA_EXP_REGION30_LUT_OFFSET 0 8 CM_RGAM_RAMA_EXP_REGION30_NUM_SEGMENTS 12 14 CM_RGAM_RAMA_EXP_REGION31_LUT_OFFSET 16 24 CM_RGAM_RAMA_EXP_REGION31_NUM_SEGMENTS 28 30 mmCM0_CM_RGAM_RAMA_REGION_32_33 0 0xd0d 4 0 2 CM_RGAM_RAMA_EXP_REGION32_LUT_OFFSET 0 8 CM_RGAM_RAMA_EXP_REGION32_NUM_SEGMENTS 12 14 CM_RGAM_RAMA_EXP_REGION33_LUT_OFFSET 16 24 CM_RGAM_RAMA_EXP_REGION33_NUM_SEGMENTS 28 30 mmCM0_CM_RGAM_RAMB_START_CNTL_B 0 0xd0e 2 0 2 CM_RGAM_RAMB_EXP_REGION_START_B 0 17 CM_RGAM_RAMB_EXP_REGION_START_SEGMENT_B 20 26 mmCM0_CM_RGAM_RAMB_START_CNTL_G 0 0xd0f 2 0 2 CM_RGAM_RAMB_EXP_REGION_START_G 0 17 CM_RGAM_RAMB_EXP_REGION_START_SEGMENT_G 20 26 mmCM0_CM_RGAM_RAMB_START_CNTL_R 0 0xd10 2 0 2 CM_RGAM_RAMB_EXP_REGION_START_R 0 17 CM_RGAM_RAMB_EXP_REGION_START_SEGMENT_R 20 26 mmCM0_CM_RGAM_RAMB_SLOPE_CNTL_B 0 0xd11 1 0 2 CM_RGAM_RAMB_EXP_REGION_LINEAR_SLOPE_B 0 17 mmCM0_CM_RGAM_RAMB_SLOPE_CNTL_G 0 0xd12 1 0 2 CM_RGAM_RAMB_EXP_REGION_LINEAR_SLOPE_G 0 17 mmCM0_CM_RGAM_RAMB_SLOPE_CNTL_R 0 0xd13 1 0 2 CM_RGAM_RAMB_EXP_REGION_LINEAR_SLOPE_R 0 17 mmCM0_CM_RGAM_RAMB_END_CNTL1_B 0 0xd14 1 0 2 CM_RGAM_RAMB_EXP_REGION_END_B 0 15 mmCM0_CM_RGAM_RAMB_END_CNTL2_B 0 0xd15 2 0 2 CM_RGAM_RAMB_EXP_REGION_END_SLOPE_B 0 15 CM_RGAM_RAMB_EXP_REGION_END_BASE_B 16 31 mmCM0_CM_RGAM_RAMB_END_CNTL1_G 0 0xd16 1 0 2 CM_RGAM_RAMB_EXP_REGION_END_G 0 15 mmCM0_CM_RGAM_RAMB_END_CNTL2_G 0 0xd17 2 0 2 CM_RGAM_RAMB_EXP_REGION_END_SLOPE_G 0 15 CM_RGAM_RAMB_EXP_REGION_END_BASE_G 16 31 mmCM0_CM_RGAM_RAMB_END_CNTL1_R 0 0xd18 1 0 2 CM_RGAM_RAMB_EXP_REGION_END_R 0 15 mmCM0_CM_RGAM_RAMB_END_CNTL2_R 0 0xd19 2 0 2 CM_RGAM_RAMB_EXP_REGION_END_SLOPE_R 0 15 CM_RGAM_RAMB_EXP_REGION_END_BASE_R 16 31 mmCM0_CM_RGAM_RAMB_REGION_0_1 0 0xd1a 4 0 2 CM_RGAM_RAMB_EXP_REGION0_LUT_OFFSET 0 8 CM_RGAM_RAMB_EXP_REGION0_NUM_SEGMENTS 12 14 CM_RGAM_RAMB_EXP_REGION1_LUT_OFFSET 16 24 CM_RGAM_RAMB_EXP_REGION1_NUM_SEGMENTS 28 30 mmCM0_CM_RGAM_RAMB_REGION_2_3 0 0xd1b 4 0 2 CM_RGAM_RAMB_EXP_REGION2_LUT_OFFSET 0 8 CM_RGAM_RAMB_EXP_REGION2_NUM_SEGMENTS 12 14 CM_RGAM_RAMB_EXP_REGION3_LUT_OFFSET 16 24 CM_RGAM_RAMB_EXP_REGION3_NUM_SEGMENTS 28 30 mmCM0_CM_RGAM_RAMB_REGION_4_5 0 0xd1c 4 0 2 CM_RGAM_RAMB_EXP_REGION4_LUT_OFFSET 0 8 CM_RGAM_RAMB_EXP_REGION4_NUM_SEGMENTS 12 14 CM_RGAM_RAMB_EXP_REGION5_LUT_OFFSET 16 24 CM_RGAM_RAMB_EXP_REGION5_NUM_SEGMENTS 28 30 mmCM0_CM_RGAM_RAMB_REGION_6_7 0 0xd1d 4 0 2 CM_RGAM_RAMB_EXP_REGION6_LUT_OFFSET 0 8 CM_RGAM_RAMB_EXP_REGION6_NUM_SEGMENTS 12 14 CM_RGAM_RAMB_EXP_REGION7_LUT_OFFSET 16 24 CM_RGAM_RAMB_EXP_REGION7_NUM_SEGMENTS 28 30 mmCM0_CM_RGAM_RAMB_REGION_8_9 0 0xd1e 4 0 2 CM_RGAM_RAMB_EXP_REGION8_LUT_OFFSET 0 8 CM_RGAM_RAMB_EXP_REGION8_NUM_SEGMENTS 12 14 CM_RGAM_RAMB_EXP_REGION9_LUT_OFFSET 16 24 CM_RGAM_RAMB_EXP_REGION9_NUM_SEGMENTS 28 30 mmCM0_CM_RGAM_RAMB_REGION_10_11 0 0xd1f 4 0 2 CM_RGAM_RAMB_EXP_REGION10_LUT_OFFSET 0 8 CM_RGAM_RAMB_EXP_REGION10_NUM_SEGMENTS 12 14 CM_RGAM_RAMB_EXP_REGION11_LUT_OFFSET 16 24 CM_RGAM_RAMB_EXP_REGION11_NUM_SEGMENTS 28 30 mmCM0_CM_RGAM_RAMB_REGION_12_13 0 0xd20 4 0 2 CM_RGAM_RAMB_EXP_REGION12_LUT_OFFSET 0 8 CM_RGAM_RAMB_EXP_REGION12_NUM_SEGMENTS 12 14 CM_RGAM_RAMB_EXP_REGION13_LUT_OFFSET 16 24 CM_RGAM_RAMB_EXP_REGION13_NUM_SEGMENTS 28 30 mmCM0_CM_RGAM_RAMB_REGION_14_15 0 0xd21 4 0 2 CM_RGAM_RAMB_EXP_REGION14_LUT_OFFSET 0 8 CM_RGAM_RAMB_EXP_REGION14_NUM_SEGMENTS 12 14 CM_RGAM_RAMB_EXP_REGION15_LUT_OFFSET 16 24 CM_RGAM_RAMB_EXP_REGION15_NUM_SEGMENTS 28 30 mmCM0_CM_RGAM_RAMB_REGION_16_17 0 0xd22 4 0 2 CM_RGAM_RAMB_EXP_REGION16_LUT_OFFSET 0 8 CM_RGAM_RAMB_EXP_REGION16_NUM_SEGMENTS 12 14 CM_RGAM_RAMB_EXP_REGION17_LUT_OFFSET 16 24 CM_RGAM_RAMB_EXP_REGION17_NUM_SEGMENTS 28 30 mmCM0_CM_RGAM_RAMB_REGION_18_19 0 0xd23 4 0 2 CM_RGAM_RAMB_EXP_REGION18_LUT_OFFSET 0 8 CM_RGAM_RAMB_EXP_REGION18_NUM_SEGMENTS 12 14 CM_RGAM_RAMB_EXP_REGION19_LUT_OFFSET 16 24 CM_RGAM_RAMB_EXP_REGION19_NUM_SEGMENTS 28 30 mmCM0_CM_RGAM_RAMB_REGION_20_21 0 0xd24 4 0 2 CM_RGAM_RAMB_EXP_REGION20_LUT_OFFSET 0 8 CM_RGAM_RAMB_EXP_REGION20_NUM_SEGMENTS 12 14 CM_RGAM_RAMB_EXP_REGION21_LUT_OFFSET 16 24 CM_RGAM_RAMB_EXP_REGION21_NUM_SEGMENTS 28 30 mmCM0_CM_RGAM_RAMB_REGION_22_23 0 0xd25 4 0 2 CM_RGAM_RAMB_EXP_REGION22_LUT_OFFSET 0 8 CM_RGAM_RAMB_EXP_REGION22_NUM_SEGMENTS 12 14 CM_RGAM_RAMB_EXP_REGION23_LUT_OFFSET 16 24 CM_RGAM_RAMB_EXP_REGION23_NUM_SEGMENTS 28 30 mmCM0_CM_RGAM_RAMB_REGION_24_25 0 0xd26 4 0 2 CM_RGAM_RAMB_EXP_REGION24_LUT_OFFSET 0 8 CM_RGAM_RAMB_EXP_REGION24_NUM_SEGMENTS 12 14 CM_RGAM_RAMB_EXP_REGION25_LUT_OFFSET 16 24 CM_RGAM_RAMB_EXP_REGION25_NUM_SEGMENTS 28 30 mmCM0_CM_RGAM_RAMB_REGION_26_27 0 0xd27 4 0 2 CM_RGAM_RAMB_EXP_REGION26_LUT_OFFSET 0 8 CM_RGAM_RAMB_EXP_REGION26_NUM_SEGMENTS 12 14 CM_RGAM_RAMB_EXP_REGION27_LUT_OFFSET 16 24 CM_RGAM_RAMB_EXP_REGION27_NUM_SEGMENTS 28 30 mmCM0_CM_RGAM_RAMB_REGION_28_29 0 0xd28 4 0 2 CM_RGAM_RAMB_EXP_REGION28_LUT_OFFSET 0 8 CM_RGAM_RAMB_EXP_REGION28_NUM_SEGMENTS 12 14 CM_RGAM_RAMB_EXP_REGION29_LUT_OFFSET 16 24 CM_RGAM_RAMB_EXP_REGION29_NUM_SEGMENTS 28 30 mmCM0_CM_RGAM_RAMB_REGION_30_31 0 0xd29 4 0 2 CM_RGAM_RAMB_EXP_REGION30_LUT_OFFSET 0 8 CM_RGAM_RAMB_EXP_REGION30_NUM_SEGMENTS 12 14 CM_RGAM_RAMB_EXP_REGION31_LUT_OFFSET 16 24 CM_RGAM_RAMB_EXP_REGION31_NUM_SEGMENTS 28 30 mmCM0_CM_RGAM_RAMB_REGION_32_33 0 0xd2a 4 0 2 CM_RGAM_RAMB_EXP_REGION32_LUT_OFFSET 0 8 CM_RGAM_RAMB_EXP_REGION32_NUM_SEGMENTS 12 14 CM_RGAM_RAMB_EXP_REGION33_LUT_OFFSET 16 24 CM_RGAM_RAMB_EXP_REGION33_NUM_SEGMENTS 28 30 mmCM0_CM_HDR_MULT_COEF 0 0xd2b 1 0 2 CM_HDR_MULT_COEF 0 18 mmCM0_CM_RANGE_CLAMP_CONTROL_R 0 0xd2c 2 0 2 CM_RANGE_CLAMP_MAX_R 0 15 CM_RANGE_CLAMP_MIN_R 16 31 mmCM0_CM_RANGE_CLAMP_CONTROL_G 0 0xd2d 2 0 2 CM_RANGE_CLAMP_MAX_G 0 15 CM_RANGE_CLAMP_MIN_G 16 31 mmCM0_CM_RANGE_CLAMP_CONTROL_B 0 0xd2e 2 0 2 CM_RANGE_CLAMP_MAX_B 0 15 CM_RANGE_CLAMP_MIN_B 16 31 mmCM0_CM_DENORM_CONTROL 0 0xd2f 2 0 2 CM_DENORM_MODE 0 2 CM_DENORM_ROUND_CLAMP 4 4 mmCM0_CM_CMOUT_CONTROL 0 0xd30 7 0 2 CM_CMOUT_ROUND_TRUNC_MODE 0 3 CM_CMOUT_SPATIAL_DITHER_EN 4 4 CM_CMOUT_SPATIAL_DITHER_MODE 8 9 CM_CMOUT_SPATIAL_DITHER_DEPTH 12 13 CM_CMOUT_FRAME_RANDOM_ENABLE 16 16 CM_CMOUT_RGB_RANDOM_EN 20 20 CM_CMOUT_HIGHPASS_RANDOM_ENABLE 24 24 mmCM0_CM_CMOUT_RANDOM_SEEDS 0 0xd31 3 0 2 CM_CMOUT_RAND_R_SEED 0 7 CM_CMOUT_RAND_G_SEED 8 15 CM_CMOUT_RAND_B_SEED 16 23 mmCM0_CM_MEM_PWR_CTRL 0 0xd32 4 0 2 SHARED_MEM_PWR_FORCE 0 1 SHARED_MEM_PWR_DIS 2 2 RGAM_MEM_PWR_FORCE 4 5 RGAM_MEM_PWR_DIS 6 6 mmCM0_CM_MEM_PWR_STATUS 0 0xd33 2 0 2 SHARED_MEM_PWR_STATE 0 1 RGAM_MEM_PWR_STATE 2 3 mmCM0_CM_TEST_DEBUG_INDEX 0 0xd35 2 0 2 CM_TEST_DEBUG_INDEX 0 7 CM_TEST_DEBUG_WRITE_EN 8 8 mmCM0_CM_TEST_DEBUG_DATA 0 0xd36 1 0 2 CM_TEST_DEBUG_DATA 0 31 mmDC_PERFMON12_PERFCOUNTER_CNTL 0 0xd4c 11 0 2 PERFCOUNTER_EVENT_SEL 0 8 PERFCOUNTER_CVALUE_SEL 9 11 PERFCOUNTER_INC_MODE 12 14 PERFCOUNTER_HW_CNTL_SEL 15 15 PERFCOUNTER_RUNEN_MODE 16 16 PERFCOUNTER_CNTOFF_START_DIS 22 22 PERFCOUNTER_RESTART_EN 23 23 PERFCOUNTER_INT_EN 24 24 PERFCOUNTER_OFF_MASK 25 25 PERFCOUNTER_ACTIVE 26 26 PERFCOUNTER_CNTL_SEL 29 31 mmDC_PERFMON12_PERFCOUNTER_CNTL2 0 0xd4d 5 0 2 PERFCOUNTER_COUNTED_VALUE_TYPE 0 1 PERFCOUNTER_HW_STOP1_SEL 2 2 PERFCOUNTER_HW_STOP2_SEL 3 3 PERFCOUNTER_CNTOFF_SEL 8 13 PERFCOUNTER_CNTL2_SEL 29 31 mmDC_PERFMON12_PERFCOUNTER_STATE 0 0xd4e 16 0 2 PERFCOUNTER_CNT0_STATE 0 1 PERFCOUNTER_STATE_SEL0 2 2 PERFCOUNTER_CNT1_STATE 4 5 PERFCOUNTER_STATE_SEL1 6 6 PERFCOUNTER_CNT2_STATE 8 9 PERFCOUNTER_STATE_SEL2 10 10 PERFCOUNTER_CNT3_STATE 12 13 PERFCOUNTER_STATE_SEL3 14 14 PERFCOUNTER_CNT4_STATE 16 17 PERFCOUNTER_STATE_SEL4 18 18 PERFCOUNTER_CNT5_STATE 20 21 PERFCOUNTER_STATE_SEL5 22 22 PERFCOUNTER_CNT6_STATE 24 25 PERFCOUNTER_STATE_SEL6 26 26 PERFCOUNTER_CNT7_STATE 28 29 PERFCOUNTER_STATE_SEL7 30 30 mmDC_PERFMON12_PERFMON_CNTL 0 0xd4f 6 0 2 PERFMON_STATE 0 1 PERFMON_RPT_COUNT 8 27 PERFMON_CNTOFF_AND_OR 28 28 PERFMON_CNTOFF_INT_EN 29 29 PERFMON_CNTOFF_INT_STATUS 30 30 PERFMON_CNTOFF_INT_ACK 31 31 mmDC_PERFMON12_PERFMON_CNTL2 0 0xd50 4 0 2 PERFMON_CNTOFF_INT_TYPE 0 0 PERFMON_CLK_ENABLE 1 1 PERFMON_RUN_ENABLE_START_SEL 2 9 PERFMON_RUN_ENABLE_STOP_SEL 10 17 mmDC_PERFMON12_PERFMON_CVALUE_INT_MISC 0 0xd51 17 0 2 PERFCOUNTER_INT0_STATUS 0 0 PERFCOUNTER_INT1_STATUS 1 1 PERFCOUNTER_INT2_STATUS 2 2 PERFCOUNTER_INT3_STATUS 3 3 PERFCOUNTER_INT4_STATUS 4 4 PERFCOUNTER_INT5_STATUS 5 5 PERFCOUNTER_INT6_STATUS 6 6 PERFCOUNTER_INT7_STATUS 7 7 PERFCOUNTER_INT0_ACK 8 8 PERFCOUNTER_INT1_ACK 9 9 PERFCOUNTER_INT2_ACK 10 10 PERFCOUNTER_INT3_ACK 11 11 PERFCOUNTER_INT4_ACK 12 12 PERFCOUNTER_INT5_ACK 13 13 PERFCOUNTER_INT6_ACK 14 14 PERFCOUNTER_INT7_ACK 15 15 PERFMON_CVALUE_HI 16 31 mmDC_PERFMON12_PERFMON_CVALUE_LOW 0 0xd52 1 0 2 PERFMON_CVALUE_LOW 0 31 mmDC_PERFMON12_PERFMON_HI 0 0xd53 2 0 2 PERFMON_HI 0 15 PERFMON_READ_SEL 29 31 mmDC_PERFMON12_PERFMON_LOW 0 0xd54 1 0 2 PERFMON_LOW 0 31 mmDPP_TOP1_DPP_CONTROL 0 0xd58 9 0 2 DPP_CLOCK_ENABLE 4 4 DPPCLK_G_GATE_DISABLE 8 8 DPPCLK_G_DYN_GATE_DISABLE 10 10 DPPCLK_G_DSCL_GATE_DISABLE 12 12 DPPCLK_R_GATE_DISABLE 16 16 DISPCLK_R_GATE_DISABLE 18 18 DISPCLK_G_GATE_DISABLE 20 20 DPPCLK_RATE_CONTROL 24 24 DPP_TEST_CLK_SEL 28 30 mmDPP_TOP1_DPP_SOFT_RESET 0 0xd59 4 0 2 CNVC_SOFT_RESET 0 0 DSCL_SOFT_RESET 4 4 CM_SOFT_RESET 8 8 OBUF_SOFT_RESET 12 12 mmDPP_TOP1_DPP_CRC_VAL_R_G 0 0xd5a 2 0 2 DPP_CRC_R_CR 0 15 DPP_CRC_G_Y 16 31 mmDPP_TOP1_DPP_CRC_VAL_B_A 0 0xd5b 2 0 2 DPP_CRC_B_CB 0 15 DPP_CRC_ALPHA 16 31 mmDPP_TOP1_DPP_CRC_CTRL 0 0xd5c 11 0 2 DPP_CRC_EN 0 0 DPP_CRC_CONT_EN 1 1 DPP_CRC_ONE_SHOT_PENDING 2 2 DPP_CRC_420_COMP_SEL 3 3 DPP_CRC_SRC_SEL 4 5 DPP_CRC_STEREO_EN 7 7 DPP_CRC_STEREO_MODE 8 9 DPP_CRC_INTERLACE_MODE 10 11 DPP_CRC_PIX_FORMAT_SEL 12 14 DPP_CRC_CURSOR_FORMAT_SEL 15 15 DPP_CRC_MASK 16 31 mmDPP_TOP1_HOST_READ_CONTROL 0 0xd5d 1 0 2 HOST_READ_RATE_CONTROL 0 7 mmCNVC_CFG1_CNVC_SURFACE_PIXEL_FORMAT 0 0xd62 1 0 2 CNVC_SURFACE_PIXEL_FORMAT 0 6 mmCNVC_CFG1_FORMAT_CONTROL 0 0xd63 6 0 2 FORMAT_EXPANSION_MODE 0 0 FORMAT_CNV16 4 4 ALPHA_EN 8 8 CNVC_BYPASS 12 12 OUTPUT_FP 16 16 CNVC_UPDATE_PENDING 20 20 mmCNVC_CFG1_FCNV_FP_SCALE_BIAS 0 0xd64 2 0 2 FCNV_FP_SCALE 0 15 FCNV_FP_BIAS 16 31 mmCNVC_CFG1_DENORM_CONTROL 0 0xd65 4 0 2 DENORM_SCALE 0 14 CLAMP_POSITIVE 15 15 DENORM_BIAS 16 30 DENORM_TRUNCATE 31 31 mmCNVC_CFG1_COLOR_KEYER_CONTROL 0 0xd67 2 0 2 COLOR_KEYER_EN 0 0 COLOR_KEYER_MODE 4 5 mmCNVC_CFG1_COLOR_KEYER_ALPHA 0 0xd68 2 0 2 COLOR_KEYER_ALPHA_LOW 0 15 COLOR_KEYER_ALPHA_HIGH 16 31 mmCNVC_CFG1_COLOR_KEYER_RED 0 0xd69 2 0 2 COLOR_KEYER_RED_LOW 0 15 COLOR_KEYER_RED_HIGH 16 31 mmCNVC_CFG1_COLOR_KEYER_GREEN 0 0xd6a 2 0 2 COLOR_KEYER_GREEN_LOW 0 15 COLOR_KEYER_GREEN_HIGH 16 31 mmCNVC_CFG1_COLOR_KEYER_BLUE 0 0xd6b 2 0 2 COLOR_KEYER_BLUE_LOW 0 15 COLOR_KEYER_BLUE_HIGH 16 31 mmCNVC_CUR1_CURSOR0_CONTROL 0 0xd73 7 0 2 CUR0_ENABLE 0 0 CUR0_EXPANSION_MODE 1 1 CUR0_INVERT_MODE 2 2 CUR0_MODE 4 5 CUR0_UPDATE_PENDING 6 6 CUR0_MAX 8 19 CUR0_MIN 20 31 mmCNVC_CUR1_CURSOR0_COLOR0 0 0xd74 1 0 2 CUR0_COLOR0 0 23 mmCNVC_CUR1_CURSOR0_COLOR1 0 0xd75 1 0 2 CUR0_COLOR1 0 23 mmCNVC_CUR1_CURSOR0_FP_SCALE_BIAS 0 0xd76 2 0 2 CUR0_FP_SCALE 0 15 CUR0_FP_BIAS 16 31 mmDSCL1_SCL_COEF_RAM_TAP_SELECT 0 0xd7d 3 0 2 SCL_COEF_RAM_TAP_PAIR_IDX 0 1 SCL_COEF_RAM_PHASE 8 13 SCL_COEF_RAM_FILTER_TYPE 16 18 mmDSCL1_SCL_COEF_RAM_TAP_DATA 0 0xd7e 4 0 2 SCL_COEF_RAM_EVEN_TAP_COEF 0 13 SCL_COEF_RAM_EVEN_TAP_COEF_EN 15 15 SCL_COEF_RAM_ODD_TAP_COEF 16 29 SCL_COEF_RAM_ODD_TAP_COEF_EN 31 31 mmDSCL1_SCL_MODE 0 0xd7f 6 0 2 DSCL_MODE 0 2 SCL_COEF_RAM_SELECT 8 8 SCL_COEF_RAM_SELECT_CURRENT 12 12 SCL_CHROMA_COEF_MODE 16 16 SCL_ALPHA_COEF_MODE 20 20 SCL_COEF_RAM_SELECT_RD 24 24 mmDSCL1_SCL_TAP_CONTROL 0 0xd80 4 0 2 SCL_V_NUM_TAPS 0 2 SCL_H_NUM_TAPS 4 6 SCL_V_NUM_TAPS_C 8 10 SCL_H_NUM_TAPS_C 12 14 mmDSCL1_DSCL_CONTROL 0 0xd81 1 0 2 SCL_BOUNDARY_MODE 0 0 mmDSCL1_DSCL_2TAP_CONTROL 0 0xd82 6 0 2 SCL_H_2TAP_HARDCODE_COEF_EN 0 0 SCL_H_2TAP_SHARP_EN 4 4 SCL_H_2TAP_SHARP_FACTOR 8 10 SCL_V_2TAP_HARDCODE_COEF_EN 16 16 SCL_V_2TAP_SHARP_EN 20 20 SCL_V_2TAP_SHARP_FACTOR 24 26 mmDSCL1_SCL_MANUAL_REPLICATE_CONTROL 0 0xd83 2 0 2 SCL_V_MANUAL_REPLICATE_FACTOR 0 3 SCL_H_MANUAL_REPLICATE_FACTOR 8 11 mmDSCL1_SCL_HORZ_FILTER_SCALE_RATIO 0 0xd84 1 0 2 SCL_H_SCALE_RATIO 0 25 mmDSCL1_SCL_HORZ_FILTER_INIT 0 0xd85 2 0 2 SCL_H_INIT_FRAC 0 23 SCL_H_INIT_INT 24 27 mmDSCL1_SCL_HORZ_FILTER_SCALE_RATIO_C 0 0xd86 1 0 2 SCL_H_SCALE_RATIO_C 0 25 mmDSCL1_SCL_HORZ_FILTER_INIT_C 0 0xd87 2 0 2 SCL_H_INIT_FRAC_C 0 23 SCL_H_INIT_INT_C 24 27 mmDSCL1_SCL_VERT_FILTER_SCALE_RATIO 0 0xd88 1 0 2 SCL_V_SCALE_RATIO 0 25 mmDSCL1_SCL_VERT_FILTER_INIT 0 0xd89 2 0 2 SCL_V_INIT_FRAC 0 23 SCL_V_INIT_INT 24 27 mmDSCL1_SCL_VERT_FILTER_INIT_BOT 0 0xd8a 2 0 2 SCL_V_INIT_FRAC_BOT 0 23 SCL_V_INIT_INT_BOT 24 27 mmDSCL1_SCL_VERT_FILTER_SCALE_RATIO_C 0 0xd8b 1 0 2 SCL_V_SCALE_RATIO_C 0 25 mmDSCL1_SCL_VERT_FILTER_INIT_C 0 0xd8c 2 0 2 SCL_V_INIT_FRAC_C 0 23 SCL_V_INIT_INT_C 24 27 mmDSCL1_SCL_VERT_FILTER_INIT_BOT_C 0 0xd8d 2 0 2 SCL_V_INIT_FRAC_BOT_C 0 23 SCL_V_INIT_INT_BOT_C 24 27 mmDSCL1_SCL_BLACK_OFFSET 0 0xd8e 2 0 2 SCL_BLACK_OFFSET_RGB_Y 0 15 SCL_BLACK_OFFSET_CBCR 16 31 mmDSCL1_DSCL_UPDATE 0 0xd8f 1 0 2 SCL_UPDATE_PENDING 0 0 mmDSCL1_DSCL_AUTOCAL 0 0xd90 3 0 2 AUTOCAL_MODE 0 1 AUTOCAL_NUM_PIPE 8 9 AUTOCAL_PIPE_ID 12 13 mmDSCL1_DSCL_EXT_OVERSCAN_LEFT_RIGHT 0 0xd91 2 0 2 EXT_OVERSCAN_RIGHT 0 12 EXT_OVERSCAN_LEFT 16 28 mmDSCL1_DSCL_EXT_OVERSCAN_TOP_BOTTOM 0 0xd92 2 0 2 EXT_OVERSCAN_BOTTOM 0 12 EXT_OVERSCAN_TOP 16 28 mmDSCL1_OTG_H_BLANK 0 0xd93 2 0 2 OTG_H_BLANK_START 0 13 OTG_H_BLANK_END 16 29 mmDSCL1_OTG_V_BLANK 0 0xd94 2 0 2 OTG_V_BLANK_START 0 13 OTG_V_BLANK_END 16 29 mmDSCL1_RECOUT_START 0 0xd95 2 0 2 RECOUT_START_X 0 12 RECOUT_START_Y 16 28 mmDSCL1_RECOUT_SIZE 0 0xd96 2 0 2 RECOUT_WIDTH 0 13 RECOUT_HEIGHT 16 29 mmDSCL1_MPC_SIZE 0 0xd97 2 0 2 MPC_WIDTH 0 13 MPC_HEIGHT 16 29 mmDSCL1_LB_DATA_FORMAT 0 0xd98 7 0 2 PIXEL_DEPTH 0 1 PIXEL_EXPAN_MODE 8 8 PIXEL_REDUCE_MODE 12 12 DYNAMIC_PIXEL_DEPTH 16 16 DITHER_EN 20 20 INTERLEAVE_EN 24 24 ALPHA_EN 31 31 mmDSCL1_LB_MEMORY_CTRL 0 0xd99 4 0 2 MEMORY_CONFIG 0 1 LB_MAX_PARTITIONS 8 13 LB_NUM_PARTITIONS 16 22 LB_NUM_PARTITIONS_C 24 30 mmDSCL1_LB_V_COUNTER 0 0xd9a 2 0 2 V_COUNTER 0 12 V_COUNTER_C 16 28 mmDSCL1_DSCL_MEM_PWR_CTRL 0 0xd9b 14 0 2 LUT_MEM_PWR_FORCE 0 1 LUT_MEM_PWR_DIS 2 2 LB_G1_MEM_PWR_FORCE 4 5 LB_G1_MEM_PWR_DIS 6 6 LB_G2_MEM_PWR_FORCE 8 9 LB_G2_MEM_PWR_DIS 10 10 LB_G3_MEM_PWR_FORCE 12 13 LB_G3_MEM_PWR_DIS 14 14 LB_G4_MEM_PWR_FORCE 16 17 LB_G4_MEM_PWR_DIS 18 18 LB_G5_MEM_PWR_FORCE 20 21 LB_G5_MEM_PWR_DIS 22 22 LB_G6_MEM_PWR_FORCE 24 25 LB_G6_MEM_PWR_DIS 26 26 mmDSCL1_DSCL_MEM_PWR_STATUS 0 0xd9c 7 0 2 LUT_MEM_PWR_STATE 0 1 LB_G1_MEM_PWR_STATE 2 3 LB_G2_MEM_PWR_STATE 4 5 LB_G3_MEM_PWR_STATE 6 7 LB_G4_MEM_PWR_STATE 8 9 LB_G5_MEM_PWR_STATE 10 11 LB_G6_MEM_PWR_STATE 12 13 mmDSCL1_OBUF_CONTROL 0 0xd9d 7 0 2 OBUF_BYPASS 0 0 OBUF_USE_FULL_BUFFER 4 4 OBUF_H_2X_UPSCALE_EN 8 8 OBUF_IS_HALF_RECOUT_WIDTH 12 12 OBUF_H_2X_COEF_PHASE0_SEL 16 16 OBUF_H_2X_COEF_PHASE1_SEL 24 24 OBUF_OUT_HOLD_CNT 28 31 mmDSCL1_OBUF_MEM_PWR_CTRL 0 0xd9e 3 0 2 OBUF_MEM_PWR_FORCE 0 1 OBUF_MEM_PWR_DIS 2 2 OBUF_MEM_PWR_STATE 16 17 mmCM1_CM_CONTROL 0 0xdad 2 0 2 CM_BYPASS_EN 0 0 CM_UPDATE_PENDING 8 8 mmCM1_CM_COMA_C11_C12 0 0xdae 2 0 2 CM_COMA_C11 0 15 CM_COMA_C12 16 31 mmCM1_CM_COMA_C13_C14 0 0xdaf 2 0 2 CM_COMA_C13 0 15 CM_COMA_C14 16 31 mmCM1_CM_COMA_C21_C22 0 0xdb0 2 0 2 CM_COMA_C21 0 15 CM_COMA_C22 16 31 mmCM1_CM_COMA_C23_C24 0 0xdb1 2 0 2 CM_COMA_C23 0 15 CM_COMA_C24 16 31 mmCM1_CM_COMA_C31_C32 0 0xdb2 2 0 2 CM_COMA_C31 0 15 CM_COMA_C32 16 31 mmCM1_CM_COMA_C33_C34 0 0xdb3 2 0 2 CM_COMA_C33 0 15 CM_COMA_C34 16 31 mmCM1_CM_COMB_C11_C12 0 0xdb4 2 0 2 CM_COMB_C11 0 15 CM_COMB_C12 16 31 mmCM1_CM_COMB_C13_C14 0 0xdb5 2 0 2 CM_COMB_C13 0 15 CM_COMB_C14 16 31 mmCM1_CM_COMB_C21_C22 0 0xdb6 2 0 2 CM_COMB_C21 0 15 CM_COMB_C22 16 31 mmCM1_CM_COMB_C23_C24 0 0xdb7 2 0 2 CM_COMB_C23 0 15 CM_COMB_C24 16 31 mmCM1_CM_COMB_C31_C32 0 0xdb8 2 0 2 CM_COMB_C31 0 15 CM_COMB_C32 16 31 mmCM1_CM_COMB_C33_C34 0 0xdb9 2 0 2 CM_COMB_C33 0 15 CM_COMB_C34 16 31 mmCM1_CM_IGAM_CONTROL 0 0xdba 14 0 2 CM_IGAM_LUT_MODE 0 1 CM_IGAM_LUT_DATA_SIGNED_EN_B 2 2 CM_IGAM_LUT_DATA_SIGNED_EN_G 3 3 CM_IGAM_LUT_DATA_SIGNED_EN_R 4 4 CM_IGAM_LUT_INC_B 5 8 CM_IGAM_LUT_INC_G 9 12 CM_IGAM_LUT_INC_R 13 16 CM_IGAM_LUT_FORMAT_B 17 18 CM_IGAM_LUT_FORMAT_G 19 20 CM_IGAM_LUT_FORMAT_R 21 22 CM_IGAM_LUT_B_FLOAT_POINT_EN 23 23 CM_IGAM_LUT_G_FLOAT_POINT_EN 24 24 CM_IGAM_LUT_R_FLOAT_POINT_EN 25 25 CM_IGAM_INPUT_FORMAT 26 27 mmCM1_CM_IGAM_LUT_RW_CONTROL 0 0xdbb 5 0 2 CM_IGAM_LUT_RW_MODE 0 0 CM_IGAM_LUT_WRITE_EN_MASK 4 6 CM_IGAM_LUT_SEL 8 8 CM_IGAM_LUT_HOST_EN 12 12 CM_IGAM_DGAM_CONFIG_STATUS 16 19 mmCM1_CM_IGAM_LUT_RW_INDEX 0 0xdbc 1 0 2 CM_IGAM_LUT_RW_INDEX 0 7 mmCM1_CM_IGAM_LUT_SEQ_COLOR 0 0xdbd 1 0 2 CM_IGAM_LUT_SEQ_COLOR 0 15 mmCM1_CM_IGAM_LUT_30_COLOR 0 0xdbe 3 0 2 CM_IGAM_LUT_10_BLUE 0 9 CM_IGAM_LUT_10_GREEN 10 19 CM_IGAM_LUT_10_RED 20 29 mmCM1_CM_IGAM_LUT_PWL_DATA 0 0xdbf 2 0 2 CM_IGAM_LUT_PWL_BASE 0 15 CM_IGAM_LUT_PWL_DELTA 16 31 mmCM1_CM_IGAM_LUT_AUTOFILL 0 0xdc0 2 0 2 CM_IGAM_LUT_AUTOFILL 0 0 CM_IGAM_LUT_AUTOFILL_DONE 4 4 mmCM1_CM_IGAM_LUT_BW_OFFSET_BLUE 0 0xdc1 2 0 2 CM_IGAM_LUT_BLACK_OFFSET_BLUE 0 15 CM_IGAM_LUT_WHITE_OFFSET_BLUE 16 31 mmCM1_CM_IGAM_LUT_BW_OFFSET_GREEN 0 0xdc2 2 0 2 CM_IGAM_LUT_BLACK_OFFSET_GREEN 0 15 CM_IGAM_LUT_WHITE_OFFSET_GREEN 16 31 mmCM1_CM_IGAM_LUT_BW_OFFSET_RED 0 0xdc3 2 0 2 CM_IGAM_LUT_BLACK_OFFSET_RED 0 15 CM_IGAM_LUT_WHITE_OFFSET_RED 16 31 mmCM1_CM_ICSC_CONTROL 0 0xdc4 1 0 2 CM_ICSC_MODE 0 1 mmCM1_CM_ICSC_C11_C12 0 0xdc5 2 0 2 CM_ICSC_C11 0 15 CM_ICSC_C12 16 31 mmCM1_CM_ICSC_C13_C14 0 0xdc6 2 0 2 CM_ICSC_C13 0 15 CM_ICSC_C14 16 31 mmCM1_CM_ICSC_C21_C22 0 0xdc7 2 0 2 CM_ICSC_C21 0 15 CM_ICSC_C22 16 31 mmCM1_CM_ICSC_C23_C24 0 0xdc8 2 0 2 CM_ICSC_C23 0 15 CM_ICSC_C24 16 31 mmCM1_CM_ICSC_C31_C32 0 0xdc9 2 0 2 CM_ICSC_C31 0 15 CM_ICSC_C32 16 31 mmCM1_CM_ICSC_C33_C34 0 0xdca 2 0 2 CM_ICSC_C33 0 15 CM_ICSC_C34 16 31 mmCM1_CM_GAMUT_REMAP_CONTROL 0 0xdcb 1 0 2 CM_GAMUT_REMAP_MODE 0 1 mmCM1_CM_GAMUT_REMAP_C11_C12 0 0xdcc 2 0 2 CM_GAMUT_REMAP_C11 0 15 CM_GAMUT_REMAP_C12 16 31 mmCM1_CM_GAMUT_REMAP_C13_C14 0 0xdcd 2 0 2 CM_GAMUT_REMAP_C13 0 15 CM_GAMUT_REMAP_C14 16 31 mmCM1_CM_GAMUT_REMAP_C21_C22 0 0xdce 2 0 2 CM_GAMUT_REMAP_C21 0 15 CM_GAMUT_REMAP_C22 16 31 mmCM1_CM_GAMUT_REMAP_C23_C24 0 0xdcf 2 0 2 CM_GAMUT_REMAP_C23 0 15 CM_GAMUT_REMAP_C24 16 31 mmCM1_CM_GAMUT_REMAP_C31_C32 0 0xdd0 2 0 2 CM_GAMUT_REMAP_C31 0 15 CM_GAMUT_REMAP_C32 16 31 mmCM1_CM_GAMUT_REMAP_C33_C34 0 0xdd1 2 0 2 CM_GAMUT_REMAP_C33 0 15 CM_GAMUT_REMAP_C34 16 31 mmCM1_CM_OCSC_CONTROL 0 0xdd2 1 0 2 CM_OCSC_MODE 0 2 mmCM1_CM_OCSC_C11_C12 0 0xdd3 2 0 2 CM_OCSC_C11 0 15 CM_OCSC_C12 16 31 mmCM1_CM_OCSC_C13_C14 0 0xdd4 2 0 2 CM_OCSC_C13 0 15 CM_OCSC_C14 16 31 mmCM1_CM_OCSC_C21_C22 0 0xdd5 2 0 2 CM_OCSC_C21 0 15 CM_OCSC_C22 16 31 mmCM1_CM_OCSC_C23_C24 0 0xdd6 2 0 2 CM_OCSC_C23 0 15 CM_OCSC_C24 16 31 mmCM1_CM_OCSC_C31_C32 0 0xdd7 2 0 2 CM_OCSC_C31 0 15 CM_OCSC_C32 16 31 mmCM1_CM_OCSC_C33_C34 0 0xdd8 2 0 2 CM_OCSC_C33 0 15 CM_OCSC_C34 16 31 mmCM1_CM_BNS_VALUES_R 0 0xdd9 2 0 2 CM_BNS_BIAS_R 0 15 CM_BNS_SCALE_R 16 31 mmCM1_CM_BNS_VALUES_G 0 0xdda 2 0 2 CM_BNS_BIAS_G 0 15 CM_BNS_SCALE_G 16 31 mmCM1_CM_BNS_VALUES_B 0 0xddb 2 0 2 CM_BNS_BIAS_B 0 15 CM_BNS_SCALE_B 16 31 mmCM1_CM_DGAM_CONTROL 0 0xddc 1 0 2 CM_DGAM_LUT_MODE 0 2 mmCM1_CM_DGAM_LUT_INDEX 0 0xddd 1 0 2 CM_DGAM_LUT_INDEX 0 8 mmCM1_CM_DGAM_LUT_DATA 0 0xdde 1 0 2 CM_DGAM_LUT_DATA 0 18 mmCM1_CM_DGAM_LUT_WRITE_EN_MASK 0 0xddf 2 0 2 CM_DGAM_LUT_WRITE_EN_MASK 0 2 CM_DGAM_LUT_WRITE_SEL 4 4 mmCM1_CM_DGAM_RAMA_START_CNTL_B 0 0xde0 2 0 2 CM_DGAM_RAMA_EXP_REGION_START_B 0 17 CM_DGAM_RAMA_EXP_REGION_START_SEGMENT_B 20 26 mmCM1_CM_DGAM_RAMA_START_CNTL_G 0 0xde1 2 0 2 CM_DGAM_RAMA_EXP_REGION_START_G 0 17 CM_DGAM_RAMA_EXP_REGION_START_SEGMENT_G 20 26 mmCM1_CM_DGAM_RAMA_START_CNTL_R 0 0xde2 2 0 2 CM_DGAM_RAMA_EXP_REGION_START_R 0 17 CM_DGAM_RAMA_EXP_REGION_START_SEGMENT_R 20 26 mmCM1_CM_DGAM_RAMA_SLOPE_CNTL_B 0 0xde3 1 0 2 CM_DGAM_RAMA_EXP_REGION_LINEAR_SLOPE_B 0 17 mmCM1_CM_DGAM_RAMA_SLOPE_CNTL_G 0 0xde4 1 0 2 CM_DGAM_RAMA_EXP_REGION_LINEAR_SLOPE_G 0 17 mmCM1_CM_DGAM_RAMA_SLOPE_CNTL_R 0 0xde5 1 0 2 CM_DGAM_RAMA_EXP_REGION_LINEAR_SLOPE_R 0 17 mmCM1_CM_DGAM_RAMA_END_CNTL1_B 0 0xde6 1 0 2 CM_DGAM_RAMA_EXP_REGION_END_B 0 15 mmCM1_CM_DGAM_RAMA_END_CNTL2_B 0 0xde7 2 0 2 CM_DGAM_RAMA_EXP_REGION_END_SLOPE_B 0 15 CM_DGAM_RAMA_EXP_REGION_END_BASE_B 16 31 mmCM1_CM_DGAM_RAMA_END_CNTL1_G 0 0xde8 1 0 2 CM_DGAM_RAMA_EXP_REGION_END_G 0 15 mmCM1_CM_DGAM_RAMA_END_CNTL2_G 0 0xde9 2 0 2 CM_DGAM_RAMA_EXP_REGION_END_SLOPE_G 0 15 CM_DGAM_RAMA_EXP_REGION_END_BASE_G 16 31 mmCM1_CM_DGAM_RAMA_END_CNTL1_R 0 0xdea 1 0 2 CM_DGAM_RAMA_EXP_REGION_END_R 0 15 mmCM1_CM_DGAM_RAMA_END_CNTL2_R 0 0xdeb 2 0 2 CM_DGAM_RAMA_EXP_REGION_END_SLOPE_R 0 15 CM_DGAM_RAMA_EXP_REGION_END_BASE_R 16 31 mmCM1_CM_DGAM_RAMA_REGION_0_1 0 0xdec 4 0 2 CM_DGAM_RAMA_EXP_REGION0_LUT_OFFSET 0 8 CM_DGAM_RAMA_EXP_REGION0_NUM_SEGMENTS 12 14 CM_DGAM_RAMA_EXP_REGION1_LUT_OFFSET 16 24 CM_DGAM_RAMA_EXP_REGION1_NUM_SEGMENTS 28 30 mmCM1_CM_DGAM_RAMA_REGION_2_3 0 0xded 4 0 2 CM_DGAM_RAMA_EXP_REGION2_LUT_OFFSET 0 8 CM_DGAM_RAMA_EXP_REGION2_NUM_SEGMENTS 12 14 CM_DGAM_RAMA_EXP_REGION3_LUT_OFFSET 16 24 CM_DGAM_RAMA_EXP_REGION3_NUM_SEGMENTS 28 30 mmCM1_CM_DGAM_RAMA_REGION_4_5 0 0xdee 4 0 2 CM_DGAM_RAMA_EXP_REGION4_LUT_OFFSET 0 8 CM_DGAM_RAMA_EXP_REGION4_NUM_SEGMENTS 12 14 CM_DGAM_RAMA_EXP_REGION5_LUT_OFFSET 16 24 CM_DGAM_RAMA_EXP_REGION5_NUM_SEGMENTS 28 30 mmCM1_CM_DGAM_RAMA_REGION_6_7 0 0xdef 4 0 2 CM_DGAM_RAMA_EXP_REGION6_LUT_OFFSET 0 8 CM_DGAM_RAMA_EXP_REGION6_NUM_SEGMENTS 12 14 CM_DGAM_RAMA_EXP_REGION7_LUT_OFFSET 16 24 CM_DGAM_RAMA_EXP_REGION7_NUM_SEGMENTS 28 30 mmCM1_CM_DGAM_RAMA_REGION_8_9 0 0xdf0 4 0 2 CM_DGAM_RAMA_EXP_REGION8_LUT_OFFSET 0 8 CM_DGAM_RAMA_EXP_REGION8_NUM_SEGMENTS 12 14 CM_DGAM_RAMA_EXP_REGION9_LUT_OFFSET 16 24 CM_DGAM_RAMA_EXP_REGION9_NUM_SEGMENTS 28 30 mmCM1_CM_DGAM_RAMA_REGION_10_11 0 0xdf1 4 0 2 CM_DGAM_RAMA_EXP_REGION10_LUT_OFFSET 0 8 CM_DGAM_RAMA_EXP_REGION10_NUM_SEGMENTS 12 14 CM_DGAM_RAMA_EXP_REGION11_LUT_OFFSET 16 24 CM_DGAM_RAMA_EXP_REGION11_NUM_SEGMENTS 28 30 mmCM1_CM_DGAM_RAMA_REGION_12_13 0 0xdf2 4 0 2 CM_DGAM_RAMA_EXP_REGION12_LUT_OFFSET 0 8 CM_DGAM_RAMA_EXP_REGION12_NUM_SEGMENTS 12 14 CM_DGAM_RAMA_EXP_REGION13_LUT_OFFSET 16 24 CM_DGAM_RAMA_EXP_REGION13_NUM_SEGMENTS 28 30 mmCM1_CM_DGAM_RAMA_REGION_14_15 0 0xdf3 4 0 2 CM_DGAM_RAMA_EXP_REGION14_LUT_OFFSET 0 8 CM_DGAM_RAMA_EXP_REGION14_NUM_SEGMENTS 12 14 CM_DGAM_RAMA_EXP_REGION15_LUT_OFFSET 16 24 CM_DGAM_RAMA_EXP_REGION15_NUM_SEGMENTS 28 30 mmCM1_CM_DGAM_RAMB_START_CNTL_B 0 0xdf4 2 0 2 CM_DGAM_RAMB_EXP_REGION_START_B 0 17 CM_DGAM_RAMB_EXP_REGION_START_SEGMENT_B 20 26 mmCM1_CM_DGAM_RAMB_START_CNTL_G 0 0xdf5 2 0 2 CM_DGAM_RAMB_EXP_REGION_START_G 0 17 CM_DGAM_RAMB_EXP_REGION_START_SEGMENT_G 20 26 mmCM1_CM_DGAM_RAMB_START_CNTL_R 0 0xdf6 2 0 2 CM_DGAM_RAMB_EXP_REGION_START_R 0 17 CM_DGAM_RAMB_EXP_REGION_START_SEGMENT_R 20 26 mmCM1_CM_DGAM_RAMB_SLOPE_CNTL_B 0 0xdf7 1 0 2 CM_DGAM_RAMB_EXP_REGION_LINEAR_SLOPE_B 0 17 mmCM1_CM_DGAM_RAMB_SLOPE_CNTL_G 0 0xdf8 1 0 2 CM_DGAM_RAMB_EXP_REGION_LINEAR_SLOPE_G 0 17 mmCM1_CM_DGAM_RAMB_SLOPE_CNTL_R 0 0xdf9 1 0 2 CM_DGAM_RAMB_EXP_REGION_LINEAR_SLOPE_R 0 17 mmCM1_CM_DGAM_RAMB_END_CNTL1_B 0 0xdfa 1 0 2 CM_DGAM_RAMB_EXP_REGION_END_B 0 15 mmCM1_CM_DGAM_RAMB_END_CNTL2_B 0 0xdfb 2 0 2 CM_DGAM_RAMB_EXP_REGION_END_SLOPE_B 0 15 CM_DGAM_RAMB_EXP_REGION_END_BASE_B 16 31 mmCM1_CM_DGAM_RAMB_END_CNTL1_G 0 0xdfc 1 0 2 CM_DGAM_RAMB_EXP_REGION_END_G 0 15 mmCM1_CM_DGAM_RAMB_END_CNTL2_G 0 0xdfd 2 0 2 CM_DGAM_RAMB_EXP_REGION_END_SLOPE_G 0 15 CM_DGAM_RAMB_EXP_REGION_END_BASE_G 16 31 mmCM1_CM_DGAM_RAMB_END_CNTL1_R 0 0xdfe 1 0 2 CM_DGAM_RAMB_EXP_REGION_END_R 0 15 mmCM1_CM_DGAM_RAMB_END_CNTL2_R 0 0xdff 2 0 2 CM_DGAM_RAMB_EXP_REGION_END_SLOPE_R 0 15 CM_DGAM_RAMB_EXP_REGION_END_BASE_R 16 31 mmCM1_CM_DGAM_RAMB_REGION_0_1 0 0xe00 4 0 2 CM_DGAM_RAMB_EXP_REGION0_LUT_OFFSET 0 8 CM_DGAM_RAMB_EXP_REGION0_NUM_SEGMENTS 12 14 CM_DGAM_RAMB_EXP_REGION1_LUT_OFFSET 16 24 CM_DGAM_RAMB_EXP_REGION1_NUM_SEGMENTS 28 30 mmCM1_CM_DGAM_RAMB_REGION_2_3 0 0xe01 4 0 2 CM_DGAM_RAMB_EXP_REGION2_LUT_OFFSET 0 8 CM_DGAM_RAMB_EXP_REGION2_NUM_SEGMENTS 12 14 CM_DGAM_RAMB_EXP_REGION3_LUT_OFFSET 16 24 CM_DGAM_RAMB_EXP_REGION3_NUM_SEGMENTS 28 30 mmCM1_CM_DGAM_RAMB_REGION_4_5 0 0xe02 4 0 2 CM_DGAM_RAMB_EXP_REGION4_LUT_OFFSET 0 8 CM_DGAM_RAMB_EXP_REGION4_NUM_SEGMENTS 12 14 CM_DGAM_RAMB_EXP_REGION5_LUT_OFFSET 16 24 CM_DGAM_RAMB_EXP_REGION5_NUM_SEGMENTS 28 30 mmCM1_CM_DGAM_RAMB_REGION_6_7 0 0xe03 4 0 2 CM_DGAM_RAMB_EXP_REGION6_LUT_OFFSET 0 8 CM_DGAM_RAMB_EXP_REGION6_NUM_SEGMENTS 12 14 CM_DGAM_RAMB_EXP_REGION7_LUT_OFFSET 16 24 CM_DGAM_RAMB_EXP_REGION7_NUM_SEGMENTS 28 30 mmCM1_CM_DGAM_RAMB_REGION_8_9 0 0xe04 4 0 2 CM_DGAM_RAMB_EXP_REGION8_LUT_OFFSET 0 8 CM_DGAM_RAMB_EXP_REGION8_NUM_SEGMENTS 12 14 CM_DGAM_RAMB_EXP_REGION9_LUT_OFFSET 16 24 CM_DGAM_RAMB_EXP_REGION9_NUM_SEGMENTS 28 30 mmCM1_CM_DGAM_RAMB_REGION_10_11 0 0xe05 4 0 2 CM_DGAM_RAMB_EXP_REGION10_LUT_OFFSET 0 8 CM_DGAM_RAMB_EXP_REGION10_NUM_SEGMENTS 12 14 CM_DGAM_RAMB_EXP_REGION11_LUT_OFFSET 16 24 CM_DGAM_RAMB_EXP_REGION11_NUM_SEGMENTS 28 30 mmCM1_CM_DGAM_RAMB_REGION_12_13 0 0xe06 4 0 2 CM_DGAM_RAMB_EXP_REGION12_LUT_OFFSET 0 8 CM_DGAM_RAMB_EXP_REGION12_NUM_SEGMENTS 12 14 CM_DGAM_RAMB_EXP_REGION13_LUT_OFFSET 16 24 CM_DGAM_RAMB_EXP_REGION13_NUM_SEGMENTS 28 30 mmCM1_CM_DGAM_RAMB_REGION_14_15 0 0xe07 4 0 2 CM_DGAM_RAMB_EXP_REGION14_LUT_OFFSET 0 8 CM_DGAM_RAMB_EXP_REGION14_NUM_SEGMENTS 12 14 CM_DGAM_RAMB_EXP_REGION15_LUT_OFFSET 16 24 CM_DGAM_RAMB_EXP_REGION15_NUM_SEGMENTS 28 30 mmCM1_CM_RGAM_CONTROL 0 0xe08 1 0 2 CM_RGAM_LUT_MODE 0 2 mmCM1_CM_RGAM_LUT_INDEX 0 0xe09 1 0 2 CM_RGAM_LUT_INDEX 0 8 mmCM1_CM_RGAM_LUT_DATA 0 0xe0a 1 0 2 CM_RGAM_LUT_DATA 0 18 mmCM1_CM_RGAM_LUT_WRITE_EN_MASK 0 0xe0b 3 0 2 CM_RGAM_LUT_WRITE_EN_MASK 0 2 CM_RGAM_LUT_WRITE_SEL 4 4 CM_RGAM_CONFIG_STATUS 8 10 mmCM1_CM_RGAM_RAMA_START_CNTL_B 0 0xe0c 2 0 2 CM_RGAM_RAMA_EXP_REGION_START_B 0 17 CM_RGAM_RAMA_EXP_REGION_START_SEGMENT_B 20 26 mmCM1_CM_RGAM_RAMA_START_CNTL_G 0 0xe0d 2 0 2 CM_RGAM_RAMA_EXP_REGION_START_G 0 17 CM_RGAM_RAMA_EXP_REGION_START_SEGMENT_G 20 26 mmCM1_CM_RGAM_RAMA_START_CNTL_R 0 0xe0e 2 0 2 CM_RGAM_RAMA_EXP_REGION_START_R 0 17 CM_RGAM_RAMA_EXP_REGION_START_SEGMENT_R 20 26 mmCM1_CM_RGAM_RAMA_SLOPE_CNTL_B 0 0xe0f 1 0 2 CM_RGAM_RAMA_EXP_REGION_LINEAR_SLOPE_B 0 17 mmCM1_CM_RGAM_RAMA_SLOPE_CNTL_G 0 0xe10 1 0 2 CM_RGAM_RAMA_EXP_REGION_LINEAR_SLOPE_G 0 17 mmCM1_CM_RGAM_RAMA_SLOPE_CNTL_R 0 0xe11 1 0 2 CM_RGAM_RAMA_EXP_REGION_LINEAR_SLOPE_R 0 17 mmCM1_CM_RGAM_RAMA_END_CNTL1_B 0 0xe12 1 0 2 CM_RGAM_RAMA_EXP_REGION_END_B 0 15 mmCM1_CM_RGAM_RAMA_END_CNTL2_B 0 0xe13 2 0 2 CM_RGAM_RAMA_EXP_REGION_END_SLOPE_B 0 15 CM_RGAM_RAMA_EXP_REGION_END_BASE_B 16 31 mmCM1_CM_RGAM_RAMA_END_CNTL1_G 0 0xe14 1 0 2 CM_RGAM_RAMA_EXP_REGION_END_G 0 15 mmCM1_CM_RGAM_RAMA_END_CNTL2_G 0 0xe15 2 0 2 CM_RGAM_RAMA_EXP_REGION_END_SLOPE_G 0 15 CM_RGAM_RAMA_EXP_REGION_END_BASE_G 16 31 mmCM1_CM_RGAM_RAMA_END_CNTL1_R 0 0xe16 1 0 2 CM_RGAM_RAMA_EXP_REGION_END_R 0 15 mmCM1_CM_RGAM_RAMA_END_CNTL2_R 0 0xe17 2 0 2 CM_RGAM_RAMA_EXP_REGION_END_SLOPE_R 0 15 CM_RGAM_RAMA_EXP_REGION_END_BASE_R 16 31 mmCM1_CM_RGAM_RAMA_REGION_0_1 0 0xe18 4 0 2 CM_RGAM_RAMA_EXP_REGION0_LUT_OFFSET 0 8 CM_RGAM_RAMA_EXP_REGION0_NUM_SEGMENTS 12 14 CM_RGAM_RAMA_EXP_REGION1_LUT_OFFSET 16 24 CM_RGAM_RAMA_EXP_REGION1_NUM_SEGMENTS 28 30 mmCM1_CM_RGAM_RAMA_REGION_2_3 0 0xe19 4 0 2 CM_RGAM_RAMA_EXP_REGION2_LUT_OFFSET 0 8 CM_RGAM_RAMA_EXP_REGION2_NUM_SEGMENTS 12 14 CM_RGAM_RAMA_EXP_REGION3_LUT_OFFSET 16 24 CM_RGAM_RAMA_EXP_REGION3_NUM_SEGMENTS 28 30 mmCM1_CM_RGAM_RAMA_REGION_4_5 0 0xe1a 4 0 2 CM_RGAM_RAMA_EXP_REGION4_LUT_OFFSET 0 8 CM_RGAM_RAMA_EXP_REGION4_NUM_SEGMENTS 12 14 CM_RGAM_RAMA_EXP_REGION5_LUT_OFFSET 16 24 CM_RGAM_RAMA_EXP_REGION5_NUM_SEGMENTS 28 30 mmCM1_CM_RGAM_RAMA_REGION_6_7 0 0xe1b 4 0 2 CM_RGAM_RAMA_EXP_REGION6_LUT_OFFSET 0 8 CM_RGAM_RAMA_EXP_REGION6_NUM_SEGMENTS 12 14 CM_RGAM_RAMA_EXP_REGION7_LUT_OFFSET 16 24 CM_RGAM_RAMA_EXP_REGION7_NUM_SEGMENTS 28 30 mmCM1_CM_RGAM_RAMA_REGION_8_9 0 0xe1c 4 0 2 CM_RGAM_RAMA_EXP_REGION8_LUT_OFFSET 0 8 CM_RGAM_RAMA_EXP_REGION8_NUM_SEGMENTS 12 14 CM_RGAM_RAMA_EXP_REGION9_LUT_OFFSET 16 24 CM_RGAM_RAMA_EXP_REGION9_NUM_SEGMENTS 28 30 mmCM1_CM_RGAM_RAMA_REGION_10_11 0 0xe1d 4 0 2 CM_RGAM_RAMA_EXP_REGION10_LUT_OFFSET 0 8 CM_RGAM_RAMA_EXP_REGION10_NUM_SEGMENTS 12 14 CM_RGAM_RAMA_EXP_REGION11_LUT_OFFSET 16 24 CM_RGAM_RAMA_EXP_REGION11_NUM_SEGMENTS 28 30 mmCM1_CM_RGAM_RAMA_REGION_12_13 0 0xe1e 4 0 2 CM_RGAM_RAMA_EXP_REGION12_LUT_OFFSET 0 8 CM_RGAM_RAMA_EXP_REGION12_NUM_SEGMENTS 12 14 CM_RGAM_RAMA_EXP_REGION13_LUT_OFFSET 16 24 CM_RGAM_RAMA_EXP_REGION13_NUM_SEGMENTS 28 30 mmCM1_CM_RGAM_RAMA_REGION_14_15 0 0xe1f 4 0 2 CM_RGAM_RAMA_EXP_REGION14_LUT_OFFSET 0 8 CM_RGAM_RAMA_EXP_REGION14_NUM_SEGMENTS 12 14 CM_RGAM_RAMA_EXP_REGION15_LUT_OFFSET 16 24 CM_RGAM_RAMA_EXP_REGION15_NUM_SEGMENTS 28 30 mmCM1_CM_RGAM_RAMA_REGION_16_17 0 0xe20 4 0 2 CM_RGAM_RAMA_EXP_REGION16_LUT_OFFSET 0 8 CM_RGAM_RAMA_EXP_REGION16_NUM_SEGMENTS 12 14 CM_RGAM_RAMA_EXP_REGION17_LUT_OFFSET 16 24 CM_RGAM_RAMA_EXP_REGION17_NUM_SEGMENTS 28 30 mmCM1_CM_RGAM_RAMA_REGION_18_19 0 0xe21 4 0 2 CM_RGAM_RAMA_EXP_REGION18_LUT_OFFSET 0 8 CM_RGAM_RAMA_EXP_REGION18_NUM_SEGMENTS 12 14 CM_RGAM_RAMA_EXP_REGION19_LUT_OFFSET 16 24 CM_RGAM_RAMA_EXP_REGION19_NUM_SEGMENTS 28 30 mmCM1_CM_RGAM_RAMA_REGION_20_21 0 0xe22 4 0 2 CM_RGAM_RAMA_EXP_REGION20_LUT_OFFSET 0 8 CM_RGAM_RAMA_EXP_REGION20_NUM_SEGMENTS 12 14 CM_RGAM_RAMA_EXP_REGION21_LUT_OFFSET 16 24 CM_RGAM_RAMA_EXP_REGION21_NUM_SEGMENTS 28 30 mmCM1_CM_RGAM_RAMA_REGION_22_23 0 0xe23 4 0 2 CM_RGAM_RAMA_EXP_REGION22_LUT_OFFSET 0 8 CM_RGAM_RAMA_EXP_REGION22_NUM_SEGMENTS 12 14 CM_RGAM_RAMA_EXP_REGION23_LUT_OFFSET 16 24 CM_RGAM_RAMA_EXP_REGION23_NUM_SEGMENTS 28 30 mmCM1_CM_RGAM_RAMA_REGION_24_25 0 0xe24 4 0 2 CM_RGAM_RAMA_EXP_REGION24_LUT_OFFSET 0 8 CM_RGAM_RAMA_EXP_REGION24_NUM_SEGMENTS 12 14 CM_RGAM_RAMA_EXP_REGION25_LUT_OFFSET 16 24 CM_RGAM_RAMA_EXP_REGION25_NUM_SEGMENTS 28 30 mmCM1_CM_RGAM_RAMA_REGION_26_27 0 0xe25 4 0 2 CM_RGAM_RAMA_EXP_REGION26_LUT_OFFSET 0 8 CM_RGAM_RAMA_EXP_REGION26_NUM_SEGMENTS 12 14 CM_RGAM_RAMA_EXP_REGION27_LUT_OFFSET 16 24 CM_RGAM_RAMA_EXP_REGION27_NUM_SEGMENTS 28 30 mmCM1_CM_RGAM_RAMA_REGION_28_29 0 0xe26 4 0 2 CM_RGAM_RAMA_EXP_REGION28_LUT_OFFSET 0 8 CM_RGAM_RAMA_EXP_REGION28_NUM_SEGMENTS 12 14 CM_RGAM_RAMA_EXP_REGION29_LUT_OFFSET 16 24 CM_RGAM_RAMA_EXP_REGION29_NUM_SEGMENTS 28 30 mmCM1_CM_RGAM_RAMA_REGION_30_31 0 0xe27 4 0 2 CM_RGAM_RAMA_EXP_REGION30_LUT_OFFSET 0 8 CM_RGAM_RAMA_EXP_REGION30_NUM_SEGMENTS 12 14 CM_RGAM_RAMA_EXP_REGION31_LUT_OFFSET 16 24 CM_RGAM_RAMA_EXP_REGION31_NUM_SEGMENTS 28 30 mmCM1_CM_RGAM_RAMA_REGION_32_33 0 0xe28 4 0 2 CM_RGAM_RAMA_EXP_REGION32_LUT_OFFSET 0 8 CM_RGAM_RAMA_EXP_REGION32_NUM_SEGMENTS 12 14 CM_RGAM_RAMA_EXP_REGION33_LUT_OFFSET 16 24 CM_RGAM_RAMA_EXP_REGION33_NUM_SEGMENTS 28 30 mmCM1_CM_RGAM_RAMB_START_CNTL_B 0 0xe29 2 0 2 CM_RGAM_RAMB_EXP_REGION_START_B 0 17 CM_RGAM_RAMB_EXP_REGION_START_SEGMENT_B 20 26 mmCM1_CM_RGAM_RAMB_START_CNTL_G 0 0xe2a 2 0 2 CM_RGAM_RAMB_EXP_REGION_START_G 0 17 CM_RGAM_RAMB_EXP_REGION_START_SEGMENT_G 20 26 mmCM1_CM_RGAM_RAMB_START_CNTL_R 0 0xe2b 2 0 2 CM_RGAM_RAMB_EXP_REGION_START_R 0 17 CM_RGAM_RAMB_EXP_REGION_START_SEGMENT_R 20 26 mmCM1_CM_RGAM_RAMB_SLOPE_CNTL_B 0 0xe2c 1 0 2 CM_RGAM_RAMB_EXP_REGION_LINEAR_SLOPE_B 0 17 mmCM1_CM_RGAM_RAMB_SLOPE_CNTL_G 0 0xe2d 1 0 2 CM_RGAM_RAMB_EXP_REGION_LINEAR_SLOPE_G 0 17 mmCM1_CM_RGAM_RAMB_SLOPE_CNTL_R 0 0xe2e 1 0 2 CM_RGAM_RAMB_EXP_REGION_LINEAR_SLOPE_R 0 17 mmCM1_CM_RGAM_RAMB_END_CNTL1_B 0 0xe2f 1 0 2 CM_RGAM_RAMB_EXP_REGION_END_B 0 15 mmCM1_CM_RGAM_RAMB_END_CNTL2_B 0 0xe30 2 0 2 CM_RGAM_RAMB_EXP_REGION_END_SLOPE_B 0 15 CM_RGAM_RAMB_EXP_REGION_END_BASE_B 16 31 mmCM1_CM_RGAM_RAMB_END_CNTL1_G 0 0xe31 1 0 2 CM_RGAM_RAMB_EXP_REGION_END_G 0 15 mmCM1_CM_RGAM_RAMB_END_CNTL2_G 0 0xe32 2 0 2 CM_RGAM_RAMB_EXP_REGION_END_SLOPE_G 0 15 CM_RGAM_RAMB_EXP_REGION_END_BASE_G 16 31 mmCM1_CM_RGAM_RAMB_END_CNTL1_R 0 0xe33 1 0 2 CM_RGAM_RAMB_EXP_REGION_END_R 0 15 mmCM1_CM_RGAM_RAMB_END_CNTL2_R 0 0xe34 2 0 2 CM_RGAM_RAMB_EXP_REGION_END_SLOPE_R 0 15 CM_RGAM_RAMB_EXP_REGION_END_BASE_R 16 31 mmCM1_CM_RGAM_RAMB_REGION_0_1 0 0xe35 4 0 2 CM_RGAM_RAMB_EXP_REGION0_LUT_OFFSET 0 8 CM_RGAM_RAMB_EXP_REGION0_NUM_SEGMENTS 12 14 CM_RGAM_RAMB_EXP_REGION1_LUT_OFFSET 16 24 CM_RGAM_RAMB_EXP_REGION1_NUM_SEGMENTS 28 30 mmCM1_CM_RGAM_RAMB_REGION_2_3 0 0xe36 4 0 2 CM_RGAM_RAMB_EXP_REGION2_LUT_OFFSET 0 8 CM_RGAM_RAMB_EXP_REGION2_NUM_SEGMENTS 12 14 CM_RGAM_RAMB_EXP_REGION3_LUT_OFFSET 16 24 CM_RGAM_RAMB_EXP_REGION3_NUM_SEGMENTS 28 30 mmCM1_CM_RGAM_RAMB_REGION_4_5 0 0xe37 4 0 2 CM_RGAM_RAMB_EXP_REGION4_LUT_OFFSET 0 8 CM_RGAM_RAMB_EXP_REGION4_NUM_SEGMENTS 12 14 CM_RGAM_RAMB_EXP_REGION5_LUT_OFFSET 16 24 CM_RGAM_RAMB_EXP_REGION5_NUM_SEGMENTS 28 30 mmCM1_CM_RGAM_RAMB_REGION_6_7 0 0xe38 4 0 2 CM_RGAM_RAMB_EXP_REGION6_LUT_OFFSET 0 8 CM_RGAM_RAMB_EXP_REGION6_NUM_SEGMENTS 12 14 CM_RGAM_RAMB_EXP_REGION7_LUT_OFFSET 16 24 CM_RGAM_RAMB_EXP_REGION7_NUM_SEGMENTS 28 30 mmCM1_CM_RGAM_RAMB_REGION_8_9 0 0xe39 4 0 2 CM_RGAM_RAMB_EXP_REGION8_LUT_OFFSET 0 8 CM_RGAM_RAMB_EXP_REGION8_NUM_SEGMENTS 12 14 CM_RGAM_RAMB_EXP_REGION9_LUT_OFFSET 16 24 CM_RGAM_RAMB_EXP_REGION9_NUM_SEGMENTS 28 30 mmCM1_CM_RGAM_RAMB_REGION_10_11 0 0xe3a 4 0 2 CM_RGAM_RAMB_EXP_REGION10_LUT_OFFSET 0 8 CM_RGAM_RAMB_EXP_REGION10_NUM_SEGMENTS 12 14 CM_RGAM_RAMB_EXP_REGION11_LUT_OFFSET 16 24 CM_RGAM_RAMB_EXP_REGION11_NUM_SEGMENTS 28 30 mmCM1_CM_RGAM_RAMB_REGION_12_13 0 0xe3b 4 0 2 CM_RGAM_RAMB_EXP_REGION12_LUT_OFFSET 0 8 CM_RGAM_RAMB_EXP_REGION12_NUM_SEGMENTS 12 14 CM_RGAM_RAMB_EXP_REGION13_LUT_OFFSET 16 24 CM_RGAM_RAMB_EXP_REGION13_NUM_SEGMENTS 28 30 mmCM1_CM_RGAM_RAMB_REGION_14_15 0 0xe3c 4 0 2 CM_RGAM_RAMB_EXP_REGION14_LUT_OFFSET 0 8 CM_RGAM_RAMB_EXP_REGION14_NUM_SEGMENTS 12 14 CM_RGAM_RAMB_EXP_REGION15_LUT_OFFSET 16 24 CM_RGAM_RAMB_EXP_REGION15_NUM_SEGMENTS 28 30 mmCM1_CM_RGAM_RAMB_REGION_16_17 0 0xe3d 4 0 2 CM_RGAM_RAMB_EXP_REGION16_LUT_OFFSET 0 8 CM_RGAM_RAMB_EXP_REGION16_NUM_SEGMENTS 12 14 CM_RGAM_RAMB_EXP_REGION17_LUT_OFFSET 16 24 CM_RGAM_RAMB_EXP_REGION17_NUM_SEGMENTS 28 30 mmCM1_CM_RGAM_RAMB_REGION_18_19 0 0xe3e 4 0 2 CM_RGAM_RAMB_EXP_REGION18_LUT_OFFSET 0 8 CM_RGAM_RAMB_EXP_REGION18_NUM_SEGMENTS 12 14 CM_RGAM_RAMB_EXP_REGION19_LUT_OFFSET 16 24 CM_RGAM_RAMB_EXP_REGION19_NUM_SEGMENTS 28 30 mmCM1_CM_RGAM_RAMB_REGION_20_21 0 0xe3f 4 0 2 CM_RGAM_RAMB_EXP_REGION20_LUT_OFFSET 0 8 CM_RGAM_RAMB_EXP_REGION20_NUM_SEGMENTS 12 14 CM_RGAM_RAMB_EXP_REGION21_LUT_OFFSET 16 24 CM_RGAM_RAMB_EXP_REGION21_NUM_SEGMENTS 28 30 mmCM1_CM_RGAM_RAMB_REGION_22_23 0 0xe40 4 0 2 CM_RGAM_RAMB_EXP_REGION22_LUT_OFFSET 0 8 CM_RGAM_RAMB_EXP_REGION22_NUM_SEGMENTS 12 14 CM_RGAM_RAMB_EXP_REGION23_LUT_OFFSET 16 24 CM_RGAM_RAMB_EXP_REGION23_NUM_SEGMENTS 28 30 mmCM1_CM_RGAM_RAMB_REGION_24_25 0 0xe41 4 0 2 CM_RGAM_RAMB_EXP_REGION24_LUT_OFFSET 0 8 CM_RGAM_RAMB_EXP_REGION24_NUM_SEGMENTS 12 14 CM_RGAM_RAMB_EXP_REGION25_LUT_OFFSET 16 24 CM_RGAM_RAMB_EXP_REGION25_NUM_SEGMENTS 28 30 mmCM1_CM_RGAM_RAMB_REGION_26_27 0 0xe42 4 0 2 CM_RGAM_RAMB_EXP_REGION26_LUT_OFFSET 0 8 CM_RGAM_RAMB_EXP_REGION26_NUM_SEGMENTS 12 14 CM_RGAM_RAMB_EXP_REGION27_LUT_OFFSET 16 24 CM_RGAM_RAMB_EXP_REGION27_NUM_SEGMENTS 28 30 mmCM1_CM_RGAM_RAMB_REGION_28_29 0 0xe43 4 0 2 CM_RGAM_RAMB_EXP_REGION28_LUT_OFFSET 0 8 CM_RGAM_RAMB_EXP_REGION28_NUM_SEGMENTS 12 14 CM_RGAM_RAMB_EXP_REGION29_LUT_OFFSET 16 24 CM_RGAM_RAMB_EXP_REGION29_NUM_SEGMENTS 28 30 mmCM1_CM_RGAM_RAMB_REGION_30_31 0 0xe44 4 0 2 CM_RGAM_RAMB_EXP_REGION30_LUT_OFFSET 0 8 CM_RGAM_RAMB_EXP_REGION30_NUM_SEGMENTS 12 14 CM_RGAM_RAMB_EXP_REGION31_LUT_OFFSET 16 24 CM_RGAM_RAMB_EXP_REGION31_NUM_SEGMENTS 28 30 mmCM1_CM_RGAM_RAMB_REGION_32_33 0 0xe45 4 0 2 CM_RGAM_RAMB_EXP_REGION32_LUT_OFFSET 0 8 CM_RGAM_RAMB_EXP_REGION32_NUM_SEGMENTS 12 14 CM_RGAM_RAMB_EXP_REGION33_LUT_OFFSET 16 24 CM_RGAM_RAMB_EXP_REGION33_NUM_SEGMENTS 28 30 mmCM1_CM_HDR_MULT_COEF 0 0xe46 1 0 2 CM_HDR_MULT_COEF 0 18 mmCM1_CM_RANGE_CLAMP_CONTROL_R 0 0xe47 2 0 2 CM_RANGE_CLAMP_MAX_R 0 15 CM_RANGE_CLAMP_MIN_R 16 31 mmCM1_CM_RANGE_CLAMP_CONTROL_G 0 0xe48 2 0 2 CM_RANGE_CLAMP_MAX_G 0 15 CM_RANGE_CLAMP_MIN_G 16 31 mmCM1_CM_RANGE_CLAMP_CONTROL_B 0 0xe49 2 0 2 CM_RANGE_CLAMP_MAX_B 0 15 CM_RANGE_CLAMP_MIN_B 16 31 mmCM1_CM_DENORM_CONTROL 0 0xe4a 2 0 2 CM_DENORM_MODE 0 2 CM_DENORM_ROUND_CLAMP 4 4 mmCM1_CM_CMOUT_CONTROL 0 0xe4b 7 0 2 CM_CMOUT_ROUND_TRUNC_MODE 0 3 CM_CMOUT_SPATIAL_DITHER_EN 4 4 CM_CMOUT_SPATIAL_DITHER_MODE 8 9 CM_CMOUT_SPATIAL_DITHER_DEPTH 12 13 CM_CMOUT_FRAME_RANDOM_ENABLE 16 16 CM_CMOUT_RGB_RANDOM_EN 20 20 CM_CMOUT_HIGHPASS_RANDOM_ENABLE 24 24 mmCM1_CM_CMOUT_RANDOM_SEEDS 0 0xe4c 3 0 2 CM_CMOUT_RAND_R_SEED 0 7 CM_CMOUT_RAND_G_SEED 8 15 CM_CMOUT_RAND_B_SEED 16 23 mmCM1_CM_MEM_PWR_CTRL 0 0xe4d 4 0 2 SHARED_MEM_PWR_FORCE 0 1 SHARED_MEM_PWR_DIS 2 2 RGAM_MEM_PWR_FORCE 4 5 RGAM_MEM_PWR_DIS 6 6 mmCM1_CM_MEM_PWR_STATUS 0 0xe4e 2 0 2 SHARED_MEM_PWR_STATE 0 1 RGAM_MEM_PWR_STATE 2 3 mmCM1_CM_TEST_DEBUG_INDEX 0 0xe50 0 0 2 mmCM1_CM_TEST_DEBUG_DATA 0 0xe51 0 0 2 mmDC_PERFMON13_PERFCOUNTER_CNTL 0 0xe67 11 0 2 PERFCOUNTER_EVENT_SEL 0 8 PERFCOUNTER_CVALUE_SEL 9 11 PERFCOUNTER_INC_MODE 12 14 PERFCOUNTER_HW_CNTL_SEL 15 15 PERFCOUNTER_RUNEN_MODE 16 16 PERFCOUNTER_CNTOFF_START_DIS 22 22 PERFCOUNTER_RESTART_EN 23 23 PERFCOUNTER_INT_EN 24 24 PERFCOUNTER_OFF_MASK 25 25 PERFCOUNTER_ACTIVE 26 26 PERFCOUNTER_CNTL_SEL 29 31 mmDC_PERFMON13_PERFCOUNTER_CNTL2 0 0xe68 5 0 2 PERFCOUNTER_COUNTED_VALUE_TYPE 0 1 PERFCOUNTER_HW_STOP1_SEL 2 2 PERFCOUNTER_HW_STOP2_SEL 3 3 PERFCOUNTER_CNTOFF_SEL 8 13 PERFCOUNTER_CNTL2_SEL 29 31 mmDC_PERFMON13_PERFCOUNTER_STATE 0 0xe69 16 0 2 PERFCOUNTER_CNT0_STATE 0 1 PERFCOUNTER_STATE_SEL0 2 2 PERFCOUNTER_CNT1_STATE 4 5 PERFCOUNTER_STATE_SEL1 6 6 PERFCOUNTER_CNT2_STATE 8 9 PERFCOUNTER_STATE_SEL2 10 10 PERFCOUNTER_CNT3_STATE 12 13 PERFCOUNTER_STATE_SEL3 14 14 PERFCOUNTER_CNT4_STATE 16 17 PERFCOUNTER_STATE_SEL4 18 18 PERFCOUNTER_CNT5_STATE 20 21 PERFCOUNTER_STATE_SEL5 22 22 PERFCOUNTER_CNT6_STATE 24 25 PERFCOUNTER_STATE_SEL6 26 26 PERFCOUNTER_CNT7_STATE 28 29 PERFCOUNTER_STATE_SEL7 30 30 mmDC_PERFMON13_PERFMON_CNTL 0 0xe6a 6 0 2 PERFMON_STATE 0 1 PERFMON_RPT_COUNT 8 27 PERFMON_CNTOFF_AND_OR 28 28 PERFMON_CNTOFF_INT_EN 29 29 PERFMON_CNTOFF_INT_STATUS 30 30 PERFMON_CNTOFF_INT_ACK 31 31 mmDC_PERFMON13_PERFMON_CNTL2 0 0xe6b 4 0 2 PERFMON_CNTOFF_INT_TYPE 0 0 PERFMON_CLK_ENABLE 1 1 PERFMON_RUN_ENABLE_START_SEL 2 9 PERFMON_RUN_ENABLE_STOP_SEL 10 17 mmDC_PERFMON13_PERFMON_CVALUE_INT_MISC 0 0xe6c 17 0 2 PERFCOUNTER_INT0_STATUS 0 0 PERFCOUNTER_INT1_STATUS 1 1 PERFCOUNTER_INT2_STATUS 2 2 PERFCOUNTER_INT3_STATUS 3 3 PERFCOUNTER_INT4_STATUS 4 4 PERFCOUNTER_INT5_STATUS 5 5 PERFCOUNTER_INT6_STATUS 6 6 PERFCOUNTER_INT7_STATUS 7 7 PERFCOUNTER_INT0_ACK 8 8 PERFCOUNTER_INT1_ACK 9 9 PERFCOUNTER_INT2_ACK 10 10 PERFCOUNTER_INT3_ACK 11 11 PERFCOUNTER_INT4_ACK 12 12 PERFCOUNTER_INT5_ACK 13 13 PERFCOUNTER_INT6_ACK 14 14 PERFCOUNTER_INT7_ACK 15 15 PERFMON_CVALUE_HI 16 31 mmDC_PERFMON13_PERFMON_CVALUE_LOW 0 0xe6d 1 0 2 PERFMON_CVALUE_LOW 0 31 mmDC_PERFMON13_PERFMON_HI 0 0xe6e 2 0 2 PERFMON_HI 0 15 PERFMON_READ_SEL 29 31 mmDC_PERFMON13_PERFMON_LOW 0 0xe6f 1 0 2 PERFMON_LOW 0 31 mmDPP_TOP2_DPP_CONTROL 0 0xe73 9 0 2 DPP_CLOCK_ENABLE 4 4 DPPCLK_G_GATE_DISABLE 8 8 DPPCLK_G_DYN_GATE_DISABLE 10 10 DPPCLK_G_DSCL_GATE_DISABLE 12 12 DPPCLK_R_GATE_DISABLE 16 16 DISPCLK_R_GATE_DISABLE 18 18 DISPCLK_G_GATE_DISABLE 20 20 DPPCLK_RATE_CONTROL 24 24 DPP_TEST_CLK_SEL 28 30 mmDPP_TOP2_DPP_SOFT_RESET 0 0xe74 4 0 2 CNVC_SOFT_RESET 0 0 DSCL_SOFT_RESET 4 4 CM_SOFT_RESET 8 8 OBUF_SOFT_RESET 12 12 mmDPP_TOP2_DPP_CRC_VAL_R_G 0 0xe75 2 0 2 DPP_CRC_R_CR 0 15 DPP_CRC_G_Y 16 31 mmDPP_TOP2_DPP_CRC_VAL_B_A 0 0xe76 2 0 2 DPP_CRC_B_CB 0 15 DPP_CRC_ALPHA 16 31 mmDPP_TOP2_DPP_CRC_CTRL 0 0xe77 11 0 2 DPP_CRC_EN 0 0 DPP_CRC_CONT_EN 1 1 DPP_CRC_ONE_SHOT_PENDING 2 2 DPP_CRC_420_COMP_SEL 3 3 DPP_CRC_SRC_SEL 4 5 DPP_CRC_STEREO_EN 7 7 DPP_CRC_STEREO_MODE 8 9 DPP_CRC_INTERLACE_MODE 10 11 DPP_CRC_PIX_FORMAT_SEL 12 14 DPP_CRC_CURSOR_FORMAT_SEL 15 15 DPP_CRC_MASK 16 31 mmDPP_TOP2_HOST_READ_CONTROL 0 0xe78 1 0 2 HOST_READ_RATE_CONTROL 0 7 mmCNVC_CFG2_CNVC_SURFACE_PIXEL_FORMAT 0 0xe7d 1 0 2 CNVC_SURFACE_PIXEL_FORMAT 0 6 mmCNVC_CFG2_FORMAT_CONTROL 0 0xe7e 6 0 2 FORMAT_EXPANSION_MODE 0 0 FORMAT_CNV16 4 4 ALPHA_EN 8 8 CNVC_BYPASS 12 12 OUTPUT_FP 16 16 CNVC_UPDATE_PENDING 20 20 mmCNVC_CFG2_FCNV_FP_SCALE_BIAS 0 0xe7f 2 0 2 FCNV_FP_SCALE 0 15 FCNV_FP_BIAS 16 31 mmCNVC_CFG2_DENORM_CONTROL 0 0xe80 4 0 2 DENORM_SCALE 0 14 CLAMP_POSITIVE 15 15 DENORM_BIAS 16 30 DENORM_TRUNCATE 31 31 mmCNVC_CFG2_COLOR_KEYER_CONTROL 0 0xe82 2 0 2 COLOR_KEYER_EN 0 0 COLOR_KEYER_MODE 4 5 mmCNVC_CFG2_COLOR_KEYER_ALPHA 0 0xe83 2 0 2 COLOR_KEYER_ALPHA_LOW 0 15 COLOR_KEYER_ALPHA_HIGH 16 31 mmCNVC_CFG2_COLOR_KEYER_RED 0 0xe84 2 0 2 COLOR_KEYER_RED_LOW 0 15 COLOR_KEYER_RED_HIGH 16 31 mmCNVC_CFG2_COLOR_KEYER_GREEN 0 0xe85 2 0 2 COLOR_KEYER_GREEN_LOW 0 15 COLOR_KEYER_GREEN_HIGH 16 31 mmCNVC_CFG2_COLOR_KEYER_BLUE 0 0xe86 2 0 2 COLOR_KEYER_BLUE_LOW 0 15 COLOR_KEYER_BLUE_HIGH 16 31 mmCNVC_CUR2_CURSOR0_CONTROL 0 0xe8e 7 0 2 CUR0_ENABLE 0 0 CUR0_EXPANSION_MODE 1 1 CUR0_INVERT_MODE 2 2 CUR0_MODE 4 5 CUR0_UPDATE_PENDING 6 6 CUR0_MAX 8 19 CUR0_MIN 20 31 mmCNVC_CUR2_CURSOR0_COLOR0 0 0xe8f 1 0 2 CUR0_COLOR0 0 23 mmCNVC_CUR2_CURSOR0_COLOR1 0 0xe90 1 0 2 CUR0_COLOR1 0 23 mmCNVC_CUR2_CURSOR0_FP_SCALE_BIAS 0 0xe91 2 0 2 CUR0_FP_SCALE 0 15 CUR0_FP_BIAS 16 31 mmDSCL2_SCL_COEF_RAM_TAP_SELECT 0 0xe98 3 0 2 SCL_COEF_RAM_TAP_PAIR_IDX 0 1 SCL_COEF_RAM_PHASE 8 13 SCL_COEF_RAM_FILTER_TYPE 16 18 mmDSCL2_SCL_COEF_RAM_TAP_DATA 0 0xe99 4 0 2 SCL_COEF_RAM_EVEN_TAP_COEF 0 13 SCL_COEF_RAM_EVEN_TAP_COEF_EN 15 15 SCL_COEF_RAM_ODD_TAP_COEF 16 29 SCL_COEF_RAM_ODD_TAP_COEF_EN 31 31 mmDSCL2_SCL_MODE 0 0xe9a 6 0 2 DSCL_MODE 0 2 SCL_COEF_RAM_SELECT 8 8 SCL_COEF_RAM_SELECT_CURRENT 12 12 SCL_CHROMA_COEF_MODE 16 16 SCL_ALPHA_COEF_MODE 20 20 SCL_COEF_RAM_SELECT_RD 24 24 mmDSCL2_SCL_TAP_CONTROL 0 0xe9b 4 0 2 SCL_V_NUM_TAPS 0 2 SCL_H_NUM_TAPS 4 6 SCL_V_NUM_TAPS_C 8 10 SCL_H_NUM_TAPS_C 12 14 mmDSCL2_DSCL_CONTROL 0 0xe9c 1 0 2 SCL_BOUNDARY_MODE 0 0 mmDSCL2_DSCL_2TAP_CONTROL 0 0xe9d 6 0 2 SCL_H_2TAP_HARDCODE_COEF_EN 0 0 SCL_H_2TAP_SHARP_EN 4 4 SCL_H_2TAP_SHARP_FACTOR 8 10 SCL_V_2TAP_HARDCODE_COEF_EN 16 16 SCL_V_2TAP_SHARP_EN 20 20 SCL_V_2TAP_SHARP_FACTOR 24 26 mmDSCL2_SCL_MANUAL_REPLICATE_CONTROL 0 0xe9e 2 0 2 SCL_V_MANUAL_REPLICATE_FACTOR 0 3 SCL_H_MANUAL_REPLICATE_FACTOR 8 11 mmDSCL2_SCL_HORZ_FILTER_SCALE_RATIO 0 0xe9f 1 0 2 SCL_H_SCALE_RATIO 0 25 mmDSCL2_SCL_HORZ_FILTER_INIT 0 0xea0 2 0 2 SCL_H_INIT_FRAC 0 23 SCL_H_INIT_INT 24 27 mmDSCL2_SCL_HORZ_FILTER_SCALE_RATIO_C 0 0xea1 1 0 2 SCL_H_SCALE_RATIO_C 0 25 mmDSCL2_SCL_HORZ_FILTER_INIT_C 0 0xea2 2 0 2 SCL_H_INIT_FRAC_C 0 23 SCL_H_INIT_INT_C 24 27 mmDSCL2_SCL_VERT_FILTER_SCALE_RATIO 0 0xea3 1 0 2 SCL_V_SCALE_RATIO 0 25 mmDSCL2_SCL_VERT_FILTER_INIT 0 0xea4 2 0 2 SCL_V_INIT_FRAC 0 23 SCL_V_INIT_INT 24 27 mmDSCL2_SCL_VERT_FILTER_INIT_BOT 0 0xea5 2 0 2 SCL_V_INIT_FRAC_BOT 0 23 SCL_V_INIT_INT_BOT 24 27 mmDSCL2_SCL_VERT_FILTER_SCALE_RATIO_C 0 0xea6 1 0 2 SCL_V_SCALE_RATIO_C 0 25 mmDSCL2_SCL_VERT_FILTER_INIT_C 0 0xea7 2 0 2 SCL_V_INIT_FRAC_C 0 23 SCL_V_INIT_INT_C 24 27 mmDSCL2_SCL_VERT_FILTER_INIT_BOT_C 0 0xea8 2 0 2 SCL_V_INIT_FRAC_BOT_C 0 23 SCL_V_INIT_INT_BOT_C 24 27 mmDSCL2_SCL_BLACK_OFFSET 0 0xea9 2 0 2 SCL_BLACK_OFFSET_RGB_Y 0 15 SCL_BLACK_OFFSET_CBCR 16 31 mmDSCL2_DSCL_UPDATE 0 0xeaa 1 0 2 SCL_UPDATE_PENDING 0 0 mmDSCL2_DSCL_AUTOCAL 0 0xeab 3 0 2 AUTOCAL_MODE 0 1 AUTOCAL_NUM_PIPE 8 9 AUTOCAL_PIPE_ID 12 13 mmDSCL2_DSCL_EXT_OVERSCAN_LEFT_RIGHT 0 0xeac 2 0 2 EXT_OVERSCAN_RIGHT 0 12 EXT_OVERSCAN_LEFT 16 28 mmDSCL2_DSCL_EXT_OVERSCAN_TOP_BOTTOM 0 0xead 2 0 2 EXT_OVERSCAN_BOTTOM 0 12 EXT_OVERSCAN_TOP 16 28 mmDSCL2_OTG_H_BLANK 0 0xeae 2 0 2 OTG_H_BLANK_START 0 13 OTG_H_BLANK_END 16 29 mmDSCL2_OTG_V_BLANK 0 0xeaf 2 0 2 OTG_V_BLANK_START 0 13 OTG_V_BLANK_END 16 29 mmDSCL2_RECOUT_START 0 0xeb0 2 0 2 RECOUT_START_X 0 12 RECOUT_START_Y 16 28 mmDSCL2_RECOUT_SIZE 0 0xeb1 2 0 2 RECOUT_WIDTH 0 13 RECOUT_HEIGHT 16 29 mmDSCL2_MPC_SIZE 0 0xeb2 2 0 2 MPC_WIDTH 0 13 MPC_HEIGHT 16 29 mmDSCL2_LB_DATA_FORMAT 0 0xeb3 7 0 2 PIXEL_DEPTH 0 1 PIXEL_EXPAN_MODE 8 8 PIXEL_REDUCE_MODE 12 12 DYNAMIC_PIXEL_DEPTH 16 16 DITHER_EN 20 20 INTERLEAVE_EN 24 24 ALPHA_EN 31 31 mmDSCL2_LB_MEMORY_CTRL 0 0xeb4 4 0 2 MEMORY_CONFIG 0 1 LB_MAX_PARTITIONS 8 13 LB_NUM_PARTITIONS 16 22 LB_NUM_PARTITIONS_C 24 30 mmDSCL2_LB_V_COUNTER 0 0xeb5 2 0 2 V_COUNTER 0 12 V_COUNTER_C 16 28 mmDSCL2_DSCL_MEM_PWR_CTRL 0 0xeb6 14 0 2 LUT_MEM_PWR_FORCE 0 1 LUT_MEM_PWR_DIS 2 2 LB_G1_MEM_PWR_FORCE 4 5 LB_G1_MEM_PWR_DIS 6 6 LB_G2_MEM_PWR_FORCE 8 9 LB_G2_MEM_PWR_DIS 10 10 LB_G3_MEM_PWR_FORCE 12 13 LB_G3_MEM_PWR_DIS 14 14 LB_G4_MEM_PWR_FORCE 16 17 LB_G4_MEM_PWR_DIS 18 18 LB_G5_MEM_PWR_FORCE 20 21 LB_G5_MEM_PWR_DIS 22 22 LB_G6_MEM_PWR_FORCE 24 25 LB_G6_MEM_PWR_DIS 26 26 mmDSCL2_DSCL_MEM_PWR_STATUS 0 0xeb7 7 0 2 LUT_MEM_PWR_STATE 0 1 LB_G1_MEM_PWR_STATE 2 3 LB_G2_MEM_PWR_STATE 4 5 LB_G3_MEM_PWR_STATE 6 7 LB_G4_MEM_PWR_STATE 8 9 LB_G5_MEM_PWR_STATE 10 11 LB_G6_MEM_PWR_STATE 12 13 mmDSCL2_OBUF_CONTROL 0 0xeb8 7 0 2 OBUF_BYPASS 0 0 OBUF_USE_FULL_BUFFER 4 4 OBUF_H_2X_UPSCALE_EN 8 8 OBUF_IS_HALF_RECOUT_WIDTH 12 12 OBUF_H_2X_COEF_PHASE0_SEL 16 16 OBUF_H_2X_COEF_PHASE1_SEL 24 24 OBUF_OUT_HOLD_CNT 28 31 mmDSCL2_OBUF_MEM_PWR_CTRL 0 0xeb9 3 0 2 OBUF_MEM_PWR_FORCE 0 1 OBUF_MEM_PWR_DIS 2 2 OBUF_MEM_PWR_STATE 16 17 mmCM2_CM_CONTROL 0 0xec8 2 0 2 CM_BYPASS_EN 0 0 CM_UPDATE_PENDING 8 8 mmCM2_CM_COMA_C11_C12 0 0xec9 2 0 2 CM_COMA_C11 0 15 CM_COMA_C12 16 31 mmCM2_CM_COMA_C13_C14 0 0xeca 2 0 2 CM_COMA_C13 0 15 CM_COMA_C14 16 31 mmCM2_CM_COMA_C21_C22 0 0xecb 2 0 2 CM_COMA_C21 0 15 CM_COMA_C22 16 31 mmCM2_CM_COMA_C23_C24 0 0xecc 2 0 2 CM_COMA_C23 0 15 CM_COMA_C24 16 31 mmCM2_CM_COMA_C31_C32 0 0xecd 2 0 2 CM_COMA_C31 0 15 CM_COMA_C32 16 31 mmCM2_CM_COMA_C33_C34 0 0xece 2 0 2 CM_COMA_C33 0 15 CM_COMA_C34 16 31 mmCM2_CM_COMB_C11_C12 0 0xecf 2 0 2 CM_COMB_C11 0 15 CM_COMB_C12 16 31 mmCM2_CM_COMB_C13_C14 0 0xed0 2 0 2 CM_COMB_C13 0 15 CM_COMB_C14 16 31 mmCM2_CM_COMB_C21_C22 0 0xed1 2 0 2 CM_COMB_C21 0 15 CM_COMB_C22 16 31 mmCM2_CM_COMB_C23_C24 0 0xed2 2 0 2 CM_COMB_C23 0 15 CM_COMB_C24 16 31 mmCM2_CM_COMB_C31_C32 0 0xed3 2 0 2 CM_COMB_C31 0 15 CM_COMB_C32 16 31 mmCM2_CM_COMB_C33_C34 0 0xed4 2 0 2 CM_COMB_C33 0 15 CM_COMB_C34 16 31 mmCM2_CM_IGAM_CONTROL 0 0xed5 14 0 2 CM_IGAM_LUT_MODE 0 1 CM_IGAM_LUT_DATA_SIGNED_EN_B 2 2 CM_IGAM_LUT_DATA_SIGNED_EN_G 3 3 CM_IGAM_LUT_DATA_SIGNED_EN_R 4 4 CM_IGAM_LUT_INC_B 5 8 CM_IGAM_LUT_INC_G 9 12 CM_IGAM_LUT_INC_R 13 16 CM_IGAM_LUT_FORMAT_B 17 18 CM_IGAM_LUT_FORMAT_G 19 20 CM_IGAM_LUT_FORMAT_R 21 22 CM_IGAM_LUT_B_FLOAT_POINT_EN 23 23 CM_IGAM_LUT_G_FLOAT_POINT_EN 24 24 CM_IGAM_LUT_R_FLOAT_POINT_EN 25 25 CM_IGAM_INPUT_FORMAT 26 27 mmCM2_CM_IGAM_LUT_RW_CONTROL 0 0xed6 5 0 2 CM_IGAM_LUT_RW_MODE 0 0 CM_IGAM_LUT_WRITE_EN_MASK 4 6 CM_IGAM_LUT_SEL 8 8 CM_IGAM_LUT_HOST_EN 12 12 CM_IGAM_DGAM_CONFIG_STATUS 16 19 mmCM2_CM_IGAM_LUT_RW_INDEX 0 0xed7 1 0 2 CM_IGAM_LUT_RW_INDEX 0 7 mmCM2_CM_IGAM_LUT_SEQ_COLOR 0 0xed8 1 0 2 CM_IGAM_LUT_SEQ_COLOR 0 15 mmCM2_CM_IGAM_LUT_30_COLOR 0 0xed9 3 0 2 CM_IGAM_LUT_10_BLUE 0 9 CM_IGAM_LUT_10_GREEN 10 19 CM_IGAM_LUT_10_RED 20 29 mmCM2_CM_IGAM_LUT_PWL_DATA 0 0xeda 2 0 2 CM_IGAM_LUT_PWL_BASE 0 15 CM_IGAM_LUT_PWL_DELTA 16 31 mmCM2_CM_IGAM_LUT_AUTOFILL 0 0xedb 2 0 2 CM_IGAM_LUT_AUTOFILL 0 0 CM_IGAM_LUT_AUTOFILL_DONE 4 4 mmCM2_CM_IGAM_LUT_BW_OFFSET_BLUE 0 0xedc 2 0 2 CM_IGAM_LUT_BLACK_OFFSET_BLUE 0 15 CM_IGAM_LUT_WHITE_OFFSET_BLUE 16 31 mmCM2_CM_IGAM_LUT_BW_OFFSET_GREEN 0 0xedd 2 0 2 CM_IGAM_LUT_BLACK_OFFSET_GREEN 0 15 CM_IGAM_LUT_WHITE_OFFSET_GREEN 16 31 mmCM2_CM_IGAM_LUT_BW_OFFSET_RED 0 0xede 2 0 2 CM_IGAM_LUT_BLACK_OFFSET_RED 0 15 CM_IGAM_LUT_WHITE_OFFSET_RED 16 31 mmCM2_CM_ICSC_CONTROL 0 0xedf 1 0 2 CM_ICSC_MODE 0 1 mmCM2_CM_ICSC_C11_C12 0 0xee0 2 0 2 CM_ICSC_C11 0 15 CM_ICSC_C12 16 31 mmCM2_CM_ICSC_C13_C14 0 0xee1 2 0 2 CM_ICSC_C13 0 15 CM_ICSC_C14 16 31 mmCM2_CM_ICSC_C21_C22 0 0xee2 2 0 2 CM_ICSC_C21 0 15 CM_ICSC_C22 16 31 mmCM2_CM_ICSC_C23_C24 0 0xee3 2 0 2 CM_ICSC_C23 0 15 CM_ICSC_C24 16 31 mmCM2_CM_ICSC_C31_C32 0 0xee4 2 0 2 CM_ICSC_C31 0 15 CM_ICSC_C32 16 31 mmCM2_CM_ICSC_C33_C34 0 0xee5 2 0 2 CM_ICSC_C33 0 15 CM_ICSC_C34 16 31 mmCM2_CM_GAMUT_REMAP_CONTROL 0 0xee6 1 0 2 CM_GAMUT_REMAP_MODE 0 1 mmCM2_CM_GAMUT_REMAP_C11_C12 0 0xee7 2 0 2 CM_GAMUT_REMAP_C11 0 15 CM_GAMUT_REMAP_C12 16 31 mmCM2_CM_GAMUT_REMAP_C13_C14 0 0xee8 2 0 2 CM_GAMUT_REMAP_C13 0 15 CM_GAMUT_REMAP_C14 16 31 mmCM2_CM_GAMUT_REMAP_C21_C22 0 0xee9 2 0 2 CM_GAMUT_REMAP_C21 0 15 CM_GAMUT_REMAP_C22 16 31 mmCM2_CM_GAMUT_REMAP_C23_C24 0 0xeea 2 0 2 CM_GAMUT_REMAP_C23 0 15 CM_GAMUT_REMAP_C24 16 31 mmCM2_CM_GAMUT_REMAP_C31_C32 0 0xeeb 2 0 2 CM_GAMUT_REMAP_C31 0 15 CM_GAMUT_REMAP_C32 16 31 mmCM2_CM_GAMUT_REMAP_C33_C34 0 0xeec 2 0 2 CM_GAMUT_REMAP_C33 0 15 CM_GAMUT_REMAP_C34 16 31 mmCM2_CM_OCSC_CONTROL 0 0xeed 1 0 2 CM_OCSC_MODE 0 2 mmCM2_CM_OCSC_C11_C12 0 0xeee 2 0 2 CM_OCSC_C11 0 15 CM_OCSC_C12 16 31 mmCM2_CM_OCSC_C13_C14 0 0xeef 2 0 2 CM_OCSC_C13 0 15 CM_OCSC_C14 16 31 mmCM2_CM_OCSC_C21_C22 0 0xef0 2 0 2 CM_OCSC_C21 0 15 CM_OCSC_C22 16 31 mmCM2_CM_OCSC_C23_C24 0 0xef1 2 0 2 CM_OCSC_C23 0 15 CM_OCSC_C24 16 31 mmCM2_CM_OCSC_C31_C32 0 0xef2 2 0 2 CM_OCSC_C31 0 15 CM_OCSC_C32 16 31 mmCM2_CM_OCSC_C33_C34 0 0xef3 2 0 2 CM_OCSC_C33 0 15 CM_OCSC_C34 16 31 mmCM2_CM_BNS_VALUES_R 0 0xef4 2 0 2 CM_BNS_BIAS_R 0 15 CM_BNS_SCALE_R 16 31 mmCM2_CM_BNS_VALUES_G 0 0xef5 2 0 2 CM_BNS_BIAS_G 0 15 CM_BNS_SCALE_G 16 31 mmCM2_CM_BNS_VALUES_B 0 0xef6 2 0 2 CM_BNS_BIAS_B 0 15 CM_BNS_SCALE_B 16 31 mmCM2_CM_DGAM_CONTROL 0 0xef7 1 0 2 CM_DGAM_LUT_MODE 0 2 mmCM2_CM_DGAM_LUT_INDEX 0 0xef8 1 0 2 CM_DGAM_LUT_INDEX 0 8 mmCM2_CM_DGAM_LUT_DATA 0 0xef9 1 0 2 CM_DGAM_LUT_DATA 0 18 mmCM2_CM_DGAM_LUT_WRITE_EN_MASK 0 0xefa 2 0 2 CM_DGAM_LUT_WRITE_EN_MASK 0 2 CM_DGAM_LUT_WRITE_SEL 4 4 mmCM2_CM_DGAM_RAMA_START_CNTL_B 0 0xefb 2 0 2 CM_DGAM_RAMA_EXP_REGION_START_B 0 17 CM_DGAM_RAMA_EXP_REGION_START_SEGMENT_B 20 26 mmCM2_CM_DGAM_RAMA_START_CNTL_G 0 0xefc 2 0 2 CM_DGAM_RAMA_EXP_REGION_START_G 0 17 CM_DGAM_RAMA_EXP_REGION_START_SEGMENT_G 20 26 mmCM2_CM_DGAM_RAMA_START_CNTL_R 0 0xefd 2 0 2 CM_DGAM_RAMA_EXP_REGION_START_R 0 17 CM_DGAM_RAMA_EXP_REGION_START_SEGMENT_R 20 26 mmCM2_CM_DGAM_RAMA_SLOPE_CNTL_B 0 0xefe 1 0 2 CM_DGAM_RAMA_EXP_REGION_LINEAR_SLOPE_B 0 17 mmCM2_CM_DGAM_RAMA_SLOPE_CNTL_G 0 0xeff 1 0 2 CM_DGAM_RAMA_EXP_REGION_LINEAR_SLOPE_G 0 17 mmCM2_CM_DGAM_RAMA_SLOPE_CNTL_R 0 0xf00 1 0 2 CM_DGAM_RAMA_EXP_REGION_LINEAR_SLOPE_R 0 17 mmCM2_CM_DGAM_RAMA_END_CNTL1_B 0 0xf01 1 0 2 CM_DGAM_RAMA_EXP_REGION_END_B 0 15 mmCM2_CM_DGAM_RAMA_END_CNTL2_B 0 0xf02 2 0 2 CM_DGAM_RAMA_EXP_REGION_END_SLOPE_B 0 15 CM_DGAM_RAMA_EXP_REGION_END_BASE_B 16 31 mmCM2_CM_DGAM_RAMA_END_CNTL1_G 0 0xf03 1 0 2 CM_DGAM_RAMA_EXP_REGION_END_G 0 15 mmCM2_CM_DGAM_RAMA_END_CNTL2_G 0 0xf04 2 0 2 CM_DGAM_RAMA_EXP_REGION_END_SLOPE_G 0 15 CM_DGAM_RAMA_EXP_REGION_END_BASE_G 16 31 mmCM2_CM_DGAM_RAMA_END_CNTL1_R 0 0xf05 1 0 2 CM_DGAM_RAMA_EXP_REGION_END_R 0 15 mmCM2_CM_DGAM_RAMA_END_CNTL2_R 0 0xf06 2 0 2 CM_DGAM_RAMA_EXP_REGION_END_SLOPE_R 0 15 CM_DGAM_RAMA_EXP_REGION_END_BASE_R 16 31 mmCM2_CM_DGAM_RAMA_REGION_0_1 0 0xf07 4 0 2 CM_DGAM_RAMA_EXP_REGION0_LUT_OFFSET 0 8 CM_DGAM_RAMA_EXP_REGION0_NUM_SEGMENTS 12 14 CM_DGAM_RAMA_EXP_REGION1_LUT_OFFSET 16 24 CM_DGAM_RAMA_EXP_REGION1_NUM_SEGMENTS 28 30 mmCM2_CM_DGAM_RAMA_REGION_2_3 0 0xf08 4 0 2 CM_DGAM_RAMA_EXP_REGION2_LUT_OFFSET 0 8 CM_DGAM_RAMA_EXP_REGION2_NUM_SEGMENTS 12 14 CM_DGAM_RAMA_EXP_REGION3_LUT_OFFSET 16 24 CM_DGAM_RAMA_EXP_REGION3_NUM_SEGMENTS 28 30 mmCM2_CM_DGAM_RAMA_REGION_4_5 0 0xf09 4 0 2 CM_DGAM_RAMA_EXP_REGION4_LUT_OFFSET 0 8 CM_DGAM_RAMA_EXP_REGION4_NUM_SEGMENTS 12 14 CM_DGAM_RAMA_EXP_REGION5_LUT_OFFSET 16 24 CM_DGAM_RAMA_EXP_REGION5_NUM_SEGMENTS 28 30 mmCM2_CM_DGAM_RAMA_REGION_6_7 0 0xf0a 4 0 2 CM_DGAM_RAMA_EXP_REGION6_LUT_OFFSET 0 8 CM_DGAM_RAMA_EXP_REGION6_NUM_SEGMENTS 12 14 CM_DGAM_RAMA_EXP_REGION7_LUT_OFFSET 16 24 CM_DGAM_RAMA_EXP_REGION7_NUM_SEGMENTS 28 30 mmCM2_CM_DGAM_RAMA_REGION_8_9 0 0xf0b 4 0 2 CM_DGAM_RAMA_EXP_REGION8_LUT_OFFSET 0 8 CM_DGAM_RAMA_EXP_REGION8_NUM_SEGMENTS 12 14 CM_DGAM_RAMA_EXP_REGION9_LUT_OFFSET 16 24 CM_DGAM_RAMA_EXP_REGION9_NUM_SEGMENTS 28 30 mmCM2_CM_DGAM_RAMA_REGION_10_11 0 0xf0c 4 0 2 CM_DGAM_RAMA_EXP_REGION10_LUT_OFFSET 0 8 CM_DGAM_RAMA_EXP_REGION10_NUM_SEGMENTS 12 14 CM_DGAM_RAMA_EXP_REGION11_LUT_OFFSET 16 24 CM_DGAM_RAMA_EXP_REGION11_NUM_SEGMENTS 28 30 mmCM2_CM_DGAM_RAMA_REGION_12_13 0 0xf0d 4 0 2 CM_DGAM_RAMA_EXP_REGION12_LUT_OFFSET 0 8 CM_DGAM_RAMA_EXP_REGION12_NUM_SEGMENTS 12 14 CM_DGAM_RAMA_EXP_REGION13_LUT_OFFSET 16 24 CM_DGAM_RAMA_EXP_REGION13_NUM_SEGMENTS 28 30 mmCM2_CM_DGAM_RAMA_REGION_14_15 0 0xf0e 4 0 2 CM_DGAM_RAMA_EXP_REGION14_LUT_OFFSET 0 8 CM_DGAM_RAMA_EXP_REGION14_NUM_SEGMENTS 12 14 CM_DGAM_RAMA_EXP_REGION15_LUT_OFFSET 16 24 CM_DGAM_RAMA_EXP_REGION15_NUM_SEGMENTS 28 30 mmCM2_CM_DGAM_RAMB_START_CNTL_B 0 0xf0f 2 0 2 CM_DGAM_RAMB_EXP_REGION_START_B 0 17 CM_DGAM_RAMB_EXP_REGION_START_SEGMENT_B 20 26 mmCM2_CM_DGAM_RAMB_START_CNTL_G 0 0xf10 2 0 2 CM_DGAM_RAMB_EXP_REGION_START_G 0 17 CM_DGAM_RAMB_EXP_REGION_START_SEGMENT_G 20 26 mmCM2_CM_DGAM_RAMB_START_CNTL_R 0 0xf11 2 0 2 CM_DGAM_RAMB_EXP_REGION_START_R 0 17 CM_DGAM_RAMB_EXP_REGION_START_SEGMENT_R 20 26 mmCM2_CM_DGAM_RAMB_SLOPE_CNTL_B 0 0xf12 1 0 2 CM_DGAM_RAMB_EXP_REGION_LINEAR_SLOPE_B 0 17 mmCM2_CM_DGAM_RAMB_SLOPE_CNTL_G 0 0xf13 1 0 2 CM_DGAM_RAMB_EXP_REGION_LINEAR_SLOPE_G 0 17 mmCM2_CM_DGAM_RAMB_SLOPE_CNTL_R 0 0xf14 1 0 2 CM_DGAM_RAMB_EXP_REGION_LINEAR_SLOPE_R 0 17 mmCM2_CM_DGAM_RAMB_END_CNTL1_B 0 0xf15 1 0 2 CM_DGAM_RAMB_EXP_REGION_END_B 0 15 mmCM2_CM_DGAM_RAMB_END_CNTL2_B 0 0xf16 2 0 2 CM_DGAM_RAMB_EXP_REGION_END_SLOPE_B 0 15 CM_DGAM_RAMB_EXP_REGION_END_BASE_B 16 31 mmCM2_CM_DGAM_RAMB_END_CNTL1_G 0 0xf17 1 0 2 CM_DGAM_RAMB_EXP_REGION_END_G 0 15 mmCM2_CM_DGAM_RAMB_END_CNTL2_G 0 0xf18 2 0 2 CM_DGAM_RAMB_EXP_REGION_END_SLOPE_G 0 15 CM_DGAM_RAMB_EXP_REGION_END_BASE_G 16 31 mmCM2_CM_DGAM_RAMB_END_CNTL1_R 0 0xf19 1 0 2 CM_DGAM_RAMB_EXP_REGION_END_R 0 15 mmCM2_CM_DGAM_RAMB_END_CNTL2_R 0 0xf1a 2 0 2 CM_DGAM_RAMB_EXP_REGION_END_SLOPE_R 0 15 CM_DGAM_RAMB_EXP_REGION_END_BASE_R 16 31 mmCM2_CM_DGAM_RAMB_REGION_0_1 0 0xf1b 4 0 2 CM_DGAM_RAMB_EXP_REGION0_LUT_OFFSET 0 8 CM_DGAM_RAMB_EXP_REGION0_NUM_SEGMENTS 12 14 CM_DGAM_RAMB_EXP_REGION1_LUT_OFFSET 16 24 CM_DGAM_RAMB_EXP_REGION1_NUM_SEGMENTS 28 30 mmCM2_CM_DGAM_RAMB_REGION_2_3 0 0xf1c 4 0 2 CM_DGAM_RAMB_EXP_REGION2_LUT_OFFSET 0 8 CM_DGAM_RAMB_EXP_REGION2_NUM_SEGMENTS 12 14 CM_DGAM_RAMB_EXP_REGION3_LUT_OFFSET 16 24 CM_DGAM_RAMB_EXP_REGION3_NUM_SEGMENTS 28 30 mmCM2_CM_DGAM_RAMB_REGION_4_5 0 0xf1d 4 0 2 CM_DGAM_RAMB_EXP_REGION4_LUT_OFFSET 0 8 CM_DGAM_RAMB_EXP_REGION4_NUM_SEGMENTS 12 14 CM_DGAM_RAMB_EXP_REGION5_LUT_OFFSET 16 24 CM_DGAM_RAMB_EXP_REGION5_NUM_SEGMENTS 28 30 mmCM2_CM_DGAM_RAMB_REGION_6_7 0 0xf1e 4 0 2 CM_DGAM_RAMB_EXP_REGION6_LUT_OFFSET 0 8 CM_DGAM_RAMB_EXP_REGION6_NUM_SEGMENTS 12 14 CM_DGAM_RAMB_EXP_REGION7_LUT_OFFSET 16 24 CM_DGAM_RAMB_EXP_REGION7_NUM_SEGMENTS 28 30 mmCM2_CM_DGAM_RAMB_REGION_8_9 0 0xf1f 4 0 2 CM_DGAM_RAMB_EXP_REGION8_LUT_OFFSET 0 8 CM_DGAM_RAMB_EXP_REGION8_NUM_SEGMENTS 12 14 CM_DGAM_RAMB_EXP_REGION9_LUT_OFFSET 16 24 CM_DGAM_RAMB_EXP_REGION9_NUM_SEGMENTS 28 30 mmCM2_CM_DGAM_RAMB_REGION_10_11 0 0xf20 4 0 2 CM_DGAM_RAMB_EXP_REGION10_LUT_OFFSET 0 8 CM_DGAM_RAMB_EXP_REGION10_NUM_SEGMENTS 12 14 CM_DGAM_RAMB_EXP_REGION11_LUT_OFFSET 16 24 CM_DGAM_RAMB_EXP_REGION11_NUM_SEGMENTS 28 30 mmCM2_CM_DGAM_RAMB_REGION_12_13 0 0xf21 4 0 2 CM_DGAM_RAMB_EXP_REGION12_LUT_OFFSET 0 8 CM_DGAM_RAMB_EXP_REGION12_NUM_SEGMENTS 12 14 CM_DGAM_RAMB_EXP_REGION13_LUT_OFFSET 16 24 CM_DGAM_RAMB_EXP_REGION13_NUM_SEGMENTS 28 30 mmCM2_CM_DGAM_RAMB_REGION_14_15 0 0xf22 4 0 2 CM_DGAM_RAMB_EXP_REGION14_LUT_OFFSET 0 8 CM_DGAM_RAMB_EXP_REGION14_NUM_SEGMENTS 12 14 CM_DGAM_RAMB_EXP_REGION15_LUT_OFFSET 16 24 CM_DGAM_RAMB_EXP_REGION15_NUM_SEGMENTS 28 30 mmCM2_CM_RGAM_CONTROL 0 0xf23 1 0 2 CM_RGAM_LUT_MODE 0 2 mmCM2_CM_RGAM_LUT_INDEX 0 0xf24 1 0 2 CM_RGAM_LUT_INDEX 0 8 mmCM2_CM_RGAM_LUT_DATA 0 0xf25 1 0 2 CM_RGAM_LUT_DATA 0 18 mmCM2_CM_RGAM_LUT_WRITE_EN_MASK 0 0xf26 3 0 2 CM_RGAM_LUT_WRITE_EN_MASK 0 2 CM_RGAM_LUT_WRITE_SEL 4 4 CM_RGAM_CONFIG_STATUS 8 10 mmCM2_CM_RGAM_RAMA_START_CNTL_B 0 0xf27 2 0 2 CM_RGAM_RAMA_EXP_REGION_START_B 0 17 CM_RGAM_RAMA_EXP_REGION_START_SEGMENT_B 20 26 mmCM2_CM_RGAM_RAMA_START_CNTL_G 0 0xf28 2 0 2 CM_RGAM_RAMA_EXP_REGION_START_G 0 17 CM_RGAM_RAMA_EXP_REGION_START_SEGMENT_G 20 26 mmCM2_CM_RGAM_RAMA_START_CNTL_R 0 0xf29 2 0 2 CM_RGAM_RAMA_EXP_REGION_START_R 0 17 CM_RGAM_RAMA_EXP_REGION_START_SEGMENT_R 20 26 mmCM2_CM_RGAM_RAMA_SLOPE_CNTL_B 0 0xf2a 1 0 2 CM_RGAM_RAMA_EXP_REGION_LINEAR_SLOPE_B 0 17 mmCM2_CM_RGAM_RAMA_SLOPE_CNTL_G 0 0xf2b 1 0 2 CM_RGAM_RAMA_EXP_REGION_LINEAR_SLOPE_G 0 17 mmCM2_CM_RGAM_RAMA_SLOPE_CNTL_R 0 0xf2c 1 0 2 CM_RGAM_RAMA_EXP_REGION_LINEAR_SLOPE_R 0 17 mmCM2_CM_RGAM_RAMA_END_CNTL1_B 0 0xf2d 1 0 2 CM_RGAM_RAMA_EXP_REGION_END_B 0 15 mmCM2_CM_RGAM_RAMA_END_CNTL2_B 0 0xf2e 2 0 2 CM_RGAM_RAMA_EXP_REGION_END_SLOPE_B 0 15 CM_RGAM_RAMA_EXP_REGION_END_BASE_B 16 31 mmCM2_CM_RGAM_RAMA_END_CNTL1_G 0 0xf2f 1 0 2 CM_RGAM_RAMA_EXP_REGION_END_G 0 15 mmCM2_CM_RGAM_RAMA_END_CNTL2_G 0 0xf30 2 0 2 CM_RGAM_RAMA_EXP_REGION_END_SLOPE_G 0 15 CM_RGAM_RAMA_EXP_REGION_END_BASE_G 16 31 mmCM2_CM_RGAM_RAMA_END_CNTL1_R 0 0xf31 1 0 2 CM_RGAM_RAMA_EXP_REGION_END_R 0 15 mmCM2_CM_RGAM_RAMA_END_CNTL2_R 0 0xf32 2 0 2 CM_RGAM_RAMA_EXP_REGION_END_SLOPE_R 0 15 CM_RGAM_RAMA_EXP_REGION_END_BASE_R 16 31 mmCM2_CM_RGAM_RAMA_REGION_0_1 0 0xf33 4 0 2 CM_RGAM_RAMA_EXP_REGION0_LUT_OFFSET 0 8 CM_RGAM_RAMA_EXP_REGION0_NUM_SEGMENTS 12 14 CM_RGAM_RAMA_EXP_REGION1_LUT_OFFSET 16 24 CM_RGAM_RAMA_EXP_REGION1_NUM_SEGMENTS 28 30 mmCM2_CM_RGAM_RAMA_REGION_2_3 0 0xf34 4 0 2 CM_RGAM_RAMA_EXP_REGION2_LUT_OFFSET 0 8 CM_RGAM_RAMA_EXP_REGION2_NUM_SEGMENTS 12 14 CM_RGAM_RAMA_EXP_REGION3_LUT_OFFSET 16 24 CM_RGAM_RAMA_EXP_REGION3_NUM_SEGMENTS 28 30 mmCM2_CM_RGAM_RAMA_REGION_4_5 0 0xf35 4 0 2 CM_RGAM_RAMA_EXP_REGION4_LUT_OFFSET 0 8 CM_RGAM_RAMA_EXP_REGION4_NUM_SEGMENTS 12 14 CM_RGAM_RAMA_EXP_REGION5_LUT_OFFSET 16 24 CM_RGAM_RAMA_EXP_REGION5_NUM_SEGMENTS 28 30 mmCM2_CM_RGAM_RAMA_REGION_6_7 0 0xf36 4 0 2 CM_RGAM_RAMA_EXP_REGION6_LUT_OFFSET 0 8 CM_RGAM_RAMA_EXP_REGION6_NUM_SEGMENTS 12 14 CM_RGAM_RAMA_EXP_REGION7_LUT_OFFSET 16 24 CM_RGAM_RAMA_EXP_REGION7_NUM_SEGMENTS 28 30 mmCM2_CM_RGAM_RAMA_REGION_8_9 0 0xf37 4 0 2 CM_RGAM_RAMA_EXP_REGION8_LUT_OFFSET 0 8 CM_RGAM_RAMA_EXP_REGION8_NUM_SEGMENTS 12 14 CM_RGAM_RAMA_EXP_REGION9_LUT_OFFSET 16 24 CM_RGAM_RAMA_EXP_REGION9_NUM_SEGMENTS 28 30 mmCM2_CM_RGAM_RAMA_REGION_10_11 0 0xf38 4 0 2 CM_RGAM_RAMA_EXP_REGION10_LUT_OFFSET 0 8 CM_RGAM_RAMA_EXP_REGION10_NUM_SEGMENTS 12 14 CM_RGAM_RAMA_EXP_REGION11_LUT_OFFSET 16 24 CM_RGAM_RAMA_EXP_REGION11_NUM_SEGMENTS 28 30 mmCM2_CM_RGAM_RAMA_REGION_12_13 0 0xf39 4 0 2 CM_RGAM_RAMA_EXP_REGION12_LUT_OFFSET 0 8 CM_RGAM_RAMA_EXP_REGION12_NUM_SEGMENTS 12 14 CM_RGAM_RAMA_EXP_REGION13_LUT_OFFSET 16 24 CM_RGAM_RAMA_EXP_REGION13_NUM_SEGMENTS 28 30 mmCM2_CM_RGAM_RAMA_REGION_14_15 0 0xf3a 4 0 2 CM_RGAM_RAMA_EXP_REGION14_LUT_OFFSET 0 8 CM_RGAM_RAMA_EXP_REGION14_NUM_SEGMENTS 12 14 CM_RGAM_RAMA_EXP_REGION15_LUT_OFFSET 16 24 CM_RGAM_RAMA_EXP_REGION15_NUM_SEGMENTS 28 30 mmCM2_CM_RGAM_RAMA_REGION_16_17 0 0xf3b 4 0 2 CM_RGAM_RAMA_EXP_REGION16_LUT_OFFSET 0 8 CM_RGAM_RAMA_EXP_REGION16_NUM_SEGMENTS 12 14 CM_RGAM_RAMA_EXP_REGION17_LUT_OFFSET 16 24 CM_RGAM_RAMA_EXP_REGION17_NUM_SEGMENTS 28 30 mmCM2_CM_RGAM_RAMA_REGION_18_19 0 0xf3c 4 0 2 CM_RGAM_RAMA_EXP_REGION18_LUT_OFFSET 0 8 CM_RGAM_RAMA_EXP_REGION18_NUM_SEGMENTS 12 14 CM_RGAM_RAMA_EXP_REGION19_LUT_OFFSET 16 24 CM_RGAM_RAMA_EXP_REGION19_NUM_SEGMENTS 28 30 mmCM2_CM_RGAM_RAMA_REGION_20_21 0 0xf3d 4 0 2 CM_RGAM_RAMA_EXP_REGION20_LUT_OFFSET 0 8 CM_RGAM_RAMA_EXP_REGION20_NUM_SEGMENTS 12 14 CM_RGAM_RAMA_EXP_REGION21_LUT_OFFSET 16 24 CM_RGAM_RAMA_EXP_REGION21_NUM_SEGMENTS 28 30 mmCM2_CM_RGAM_RAMA_REGION_22_23 0 0xf3e 4 0 2 CM_RGAM_RAMA_EXP_REGION22_LUT_OFFSET 0 8 CM_RGAM_RAMA_EXP_REGION22_NUM_SEGMENTS 12 14 CM_RGAM_RAMA_EXP_REGION23_LUT_OFFSET 16 24 CM_RGAM_RAMA_EXP_REGION23_NUM_SEGMENTS 28 30 mmCM2_CM_RGAM_RAMA_REGION_24_25 0 0xf3f 4 0 2 CM_RGAM_RAMA_EXP_REGION24_LUT_OFFSET 0 8 CM_RGAM_RAMA_EXP_REGION24_NUM_SEGMENTS 12 14 CM_RGAM_RAMA_EXP_REGION25_LUT_OFFSET 16 24 CM_RGAM_RAMA_EXP_REGION25_NUM_SEGMENTS 28 30 mmCM2_CM_RGAM_RAMA_REGION_26_27 0 0xf40 4 0 2 CM_RGAM_RAMA_EXP_REGION26_LUT_OFFSET 0 8 CM_RGAM_RAMA_EXP_REGION26_NUM_SEGMENTS 12 14 CM_RGAM_RAMA_EXP_REGION27_LUT_OFFSET 16 24 CM_RGAM_RAMA_EXP_REGION27_NUM_SEGMENTS 28 30 mmCM2_CM_RGAM_RAMA_REGION_28_29 0 0xf41 4 0 2 CM_RGAM_RAMA_EXP_REGION28_LUT_OFFSET 0 8 CM_RGAM_RAMA_EXP_REGION28_NUM_SEGMENTS 12 14 CM_RGAM_RAMA_EXP_REGION29_LUT_OFFSET 16 24 CM_RGAM_RAMA_EXP_REGION29_NUM_SEGMENTS 28 30 mmCM2_CM_RGAM_RAMA_REGION_30_31 0 0xf42 4 0 2 CM_RGAM_RAMA_EXP_REGION30_LUT_OFFSET 0 8 CM_RGAM_RAMA_EXP_REGION30_NUM_SEGMENTS 12 14 CM_RGAM_RAMA_EXP_REGION31_LUT_OFFSET 16 24 CM_RGAM_RAMA_EXP_REGION31_NUM_SEGMENTS 28 30 mmCM2_CM_RGAM_RAMA_REGION_32_33 0 0xf43 4 0 2 CM_RGAM_RAMA_EXP_REGION32_LUT_OFFSET 0 8 CM_RGAM_RAMA_EXP_REGION32_NUM_SEGMENTS 12 14 CM_RGAM_RAMA_EXP_REGION33_LUT_OFFSET 16 24 CM_RGAM_RAMA_EXP_REGION33_NUM_SEGMENTS 28 30 mmCM2_CM_RGAM_RAMB_START_CNTL_B 0 0xf44 2 0 2 CM_RGAM_RAMB_EXP_REGION_START_B 0 17 CM_RGAM_RAMB_EXP_REGION_START_SEGMENT_B 20 26 mmCM2_CM_RGAM_RAMB_START_CNTL_G 0 0xf45 2 0 2 CM_RGAM_RAMB_EXP_REGION_START_G 0 17 CM_RGAM_RAMB_EXP_REGION_START_SEGMENT_G 20 26 mmCM2_CM_RGAM_RAMB_START_CNTL_R 0 0xf46 2 0 2 CM_RGAM_RAMB_EXP_REGION_START_R 0 17 CM_RGAM_RAMB_EXP_REGION_START_SEGMENT_R 20 26 mmCM2_CM_RGAM_RAMB_SLOPE_CNTL_B 0 0xf47 1 0 2 CM_RGAM_RAMB_EXP_REGION_LINEAR_SLOPE_B 0 17 mmCM2_CM_RGAM_RAMB_SLOPE_CNTL_G 0 0xf48 1 0 2 CM_RGAM_RAMB_EXP_REGION_LINEAR_SLOPE_G 0 17 mmCM2_CM_RGAM_RAMB_SLOPE_CNTL_R 0 0xf49 1 0 2 CM_RGAM_RAMB_EXP_REGION_LINEAR_SLOPE_R 0 17 mmCM2_CM_RGAM_RAMB_END_CNTL1_B 0 0xf4a 1 0 2 CM_RGAM_RAMB_EXP_REGION_END_B 0 15 mmCM2_CM_RGAM_RAMB_END_CNTL2_B 0 0xf4b 2 0 2 CM_RGAM_RAMB_EXP_REGION_END_SLOPE_B 0 15 CM_RGAM_RAMB_EXP_REGION_END_BASE_B 16 31 mmCM2_CM_RGAM_RAMB_END_CNTL1_G 0 0xf4c 1 0 2 CM_RGAM_RAMB_EXP_REGION_END_G 0 15 mmCM2_CM_RGAM_RAMB_END_CNTL2_G 0 0xf4d 2 0 2 CM_RGAM_RAMB_EXP_REGION_END_SLOPE_G 0 15 CM_RGAM_RAMB_EXP_REGION_END_BASE_G 16 31 mmCM2_CM_RGAM_RAMB_END_CNTL1_R 0 0xf4e 1 0 2 CM_RGAM_RAMB_EXP_REGION_END_R 0 15 mmCM2_CM_RGAM_RAMB_END_CNTL2_R 0 0xf4f 2 0 2 CM_RGAM_RAMB_EXP_REGION_END_SLOPE_R 0 15 CM_RGAM_RAMB_EXP_REGION_END_BASE_R 16 31 mmCM2_CM_RGAM_RAMB_REGION_0_1 0 0xf50 4 0 2 CM_RGAM_RAMB_EXP_REGION0_LUT_OFFSET 0 8 CM_RGAM_RAMB_EXP_REGION0_NUM_SEGMENTS 12 14 CM_RGAM_RAMB_EXP_REGION1_LUT_OFFSET 16 24 CM_RGAM_RAMB_EXP_REGION1_NUM_SEGMENTS 28 30 mmCM2_CM_RGAM_RAMB_REGION_2_3 0 0xf51 4 0 2 CM_RGAM_RAMB_EXP_REGION2_LUT_OFFSET 0 8 CM_RGAM_RAMB_EXP_REGION2_NUM_SEGMENTS 12 14 CM_RGAM_RAMB_EXP_REGION3_LUT_OFFSET 16 24 CM_RGAM_RAMB_EXP_REGION3_NUM_SEGMENTS 28 30 mmCM2_CM_RGAM_RAMB_REGION_4_5 0 0xf52 4 0 2 CM_RGAM_RAMB_EXP_REGION4_LUT_OFFSET 0 8 CM_RGAM_RAMB_EXP_REGION4_NUM_SEGMENTS 12 14 CM_RGAM_RAMB_EXP_REGION5_LUT_OFFSET 16 24 CM_RGAM_RAMB_EXP_REGION5_NUM_SEGMENTS 28 30 mmCM2_CM_RGAM_RAMB_REGION_6_7 0 0xf53 4 0 2 CM_RGAM_RAMB_EXP_REGION6_LUT_OFFSET 0 8 CM_RGAM_RAMB_EXP_REGION6_NUM_SEGMENTS 12 14 CM_RGAM_RAMB_EXP_REGION7_LUT_OFFSET 16 24 CM_RGAM_RAMB_EXP_REGION7_NUM_SEGMENTS 28 30 mmCM2_CM_RGAM_RAMB_REGION_8_9 0 0xf54 4 0 2 CM_RGAM_RAMB_EXP_REGION8_LUT_OFFSET 0 8 CM_RGAM_RAMB_EXP_REGION8_NUM_SEGMENTS 12 14 CM_RGAM_RAMB_EXP_REGION9_LUT_OFFSET 16 24 CM_RGAM_RAMB_EXP_REGION9_NUM_SEGMENTS 28 30 mmCM2_CM_RGAM_RAMB_REGION_10_11 0 0xf55 4 0 2 CM_RGAM_RAMB_EXP_REGION10_LUT_OFFSET 0 8 CM_RGAM_RAMB_EXP_REGION10_NUM_SEGMENTS 12 14 CM_RGAM_RAMB_EXP_REGION11_LUT_OFFSET 16 24 CM_RGAM_RAMB_EXP_REGION11_NUM_SEGMENTS 28 30 mmCM2_CM_RGAM_RAMB_REGION_12_13 0 0xf56 4 0 2 CM_RGAM_RAMB_EXP_REGION12_LUT_OFFSET 0 8 CM_RGAM_RAMB_EXP_REGION12_NUM_SEGMENTS 12 14 CM_RGAM_RAMB_EXP_REGION13_LUT_OFFSET 16 24 CM_RGAM_RAMB_EXP_REGION13_NUM_SEGMENTS 28 30 mmCM2_CM_RGAM_RAMB_REGION_14_15 0 0xf57 4 0 2 CM_RGAM_RAMB_EXP_REGION14_LUT_OFFSET 0 8 CM_RGAM_RAMB_EXP_REGION14_NUM_SEGMENTS 12 14 CM_RGAM_RAMB_EXP_REGION15_LUT_OFFSET 16 24 CM_RGAM_RAMB_EXP_REGION15_NUM_SEGMENTS 28 30 mmCM2_CM_RGAM_RAMB_REGION_16_17 0 0xf58 4 0 2 CM_RGAM_RAMB_EXP_REGION16_LUT_OFFSET 0 8 CM_RGAM_RAMB_EXP_REGION16_NUM_SEGMENTS 12 14 CM_RGAM_RAMB_EXP_REGION17_LUT_OFFSET 16 24 CM_RGAM_RAMB_EXP_REGION17_NUM_SEGMENTS 28 30 mmCM2_CM_RGAM_RAMB_REGION_18_19 0 0xf59 4 0 2 CM_RGAM_RAMB_EXP_REGION18_LUT_OFFSET 0 8 CM_RGAM_RAMB_EXP_REGION18_NUM_SEGMENTS 12 14 CM_RGAM_RAMB_EXP_REGION19_LUT_OFFSET 16 24 CM_RGAM_RAMB_EXP_REGION19_NUM_SEGMENTS 28 30 mmCM2_CM_RGAM_RAMB_REGION_20_21 0 0xf5a 4 0 2 CM_RGAM_RAMB_EXP_REGION20_LUT_OFFSET 0 8 CM_RGAM_RAMB_EXP_REGION20_NUM_SEGMENTS 12 14 CM_RGAM_RAMB_EXP_REGION21_LUT_OFFSET 16 24 CM_RGAM_RAMB_EXP_REGION21_NUM_SEGMENTS 28 30 mmCM2_CM_RGAM_RAMB_REGION_22_23 0 0xf5b 4 0 2 CM_RGAM_RAMB_EXP_REGION22_LUT_OFFSET 0 8 CM_RGAM_RAMB_EXP_REGION22_NUM_SEGMENTS 12 14 CM_RGAM_RAMB_EXP_REGION23_LUT_OFFSET 16 24 CM_RGAM_RAMB_EXP_REGION23_NUM_SEGMENTS 28 30 mmCM2_CM_RGAM_RAMB_REGION_24_25 0 0xf5c 4 0 2 CM_RGAM_RAMB_EXP_REGION24_LUT_OFFSET 0 8 CM_RGAM_RAMB_EXP_REGION24_NUM_SEGMENTS 12 14 CM_RGAM_RAMB_EXP_REGION25_LUT_OFFSET 16 24 CM_RGAM_RAMB_EXP_REGION25_NUM_SEGMENTS 28 30 mmCM2_CM_RGAM_RAMB_REGION_26_27 0 0xf5d 4 0 2 CM_RGAM_RAMB_EXP_REGION26_LUT_OFFSET 0 8 CM_RGAM_RAMB_EXP_REGION26_NUM_SEGMENTS 12 14 CM_RGAM_RAMB_EXP_REGION27_LUT_OFFSET 16 24 CM_RGAM_RAMB_EXP_REGION27_NUM_SEGMENTS 28 30 mmCM2_CM_RGAM_RAMB_REGION_28_29 0 0xf5e 4 0 2 CM_RGAM_RAMB_EXP_REGION28_LUT_OFFSET 0 8 CM_RGAM_RAMB_EXP_REGION28_NUM_SEGMENTS 12 14 CM_RGAM_RAMB_EXP_REGION29_LUT_OFFSET 16 24 CM_RGAM_RAMB_EXP_REGION29_NUM_SEGMENTS 28 30 mmCM2_CM_RGAM_RAMB_REGION_30_31 0 0xf5f 4 0 2 CM_RGAM_RAMB_EXP_REGION30_LUT_OFFSET 0 8 CM_RGAM_RAMB_EXP_REGION30_NUM_SEGMENTS 12 14 CM_RGAM_RAMB_EXP_REGION31_LUT_OFFSET 16 24 CM_RGAM_RAMB_EXP_REGION31_NUM_SEGMENTS 28 30 mmCM2_CM_RGAM_RAMB_REGION_32_33 0 0xf60 4 0 2 CM_RGAM_RAMB_EXP_REGION32_LUT_OFFSET 0 8 CM_RGAM_RAMB_EXP_REGION32_NUM_SEGMENTS 12 14 CM_RGAM_RAMB_EXP_REGION33_LUT_OFFSET 16 24 CM_RGAM_RAMB_EXP_REGION33_NUM_SEGMENTS 28 30 mmCM2_CM_HDR_MULT_COEF 0 0xf61 1 0 2 CM_HDR_MULT_COEF 0 18 mmCM2_CM_RANGE_CLAMP_CONTROL_R 0 0xf62 2 0 2 CM_RANGE_CLAMP_MAX_R 0 15 CM_RANGE_CLAMP_MIN_R 16 31 mmCM2_CM_RANGE_CLAMP_CONTROL_G 0 0xf63 2 0 2 CM_RANGE_CLAMP_MAX_G 0 15 CM_RANGE_CLAMP_MIN_G 16 31 mmCM2_CM_RANGE_CLAMP_CONTROL_B 0 0xf64 2 0 2 CM_RANGE_CLAMP_MAX_B 0 15 CM_RANGE_CLAMP_MIN_B 16 31 mmCM2_CM_DENORM_CONTROL 0 0xf65 2 0 2 CM_DENORM_MODE 0 2 CM_DENORM_ROUND_CLAMP 4 4 mmCM2_CM_CMOUT_CONTROL 0 0xf66 7 0 2 CM_CMOUT_ROUND_TRUNC_MODE 0 3 CM_CMOUT_SPATIAL_DITHER_EN 4 4 CM_CMOUT_SPATIAL_DITHER_MODE 8 9 CM_CMOUT_SPATIAL_DITHER_DEPTH 12 13 CM_CMOUT_FRAME_RANDOM_ENABLE 16 16 CM_CMOUT_RGB_RANDOM_EN 20 20 CM_CMOUT_HIGHPASS_RANDOM_ENABLE 24 24 mmCM2_CM_CMOUT_RANDOM_SEEDS 0 0xf67 3 0 2 CM_CMOUT_RAND_R_SEED 0 7 CM_CMOUT_RAND_G_SEED 8 15 CM_CMOUT_RAND_B_SEED 16 23 mmCM2_CM_MEM_PWR_CTRL 0 0xf68 4 0 2 SHARED_MEM_PWR_FORCE 0 1 SHARED_MEM_PWR_DIS 2 2 RGAM_MEM_PWR_FORCE 4 5 RGAM_MEM_PWR_DIS 6 6 mmCM2_CM_MEM_PWR_STATUS 0 0xf69 2 0 2 SHARED_MEM_PWR_STATE 0 1 RGAM_MEM_PWR_STATE 2 3 mmCM2_CM_TEST_DEBUG_INDEX 0 0xf6b 0 0 2 mmCM2_CM_TEST_DEBUG_DATA 0 0xf6c 0 0 2 mmDC_PERFMON14_PERFCOUNTER_CNTL 0 0xf82 11 0 2 PERFCOUNTER_EVENT_SEL 0 8 PERFCOUNTER_CVALUE_SEL 9 11 PERFCOUNTER_INC_MODE 12 14 PERFCOUNTER_HW_CNTL_SEL 15 15 PERFCOUNTER_RUNEN_MODE 16 16 PERFCOUNTER_CNTOFF_START_DIS 22 22 PERFCOUNTER_RESTART_EN 23 23 PERFCOUNTER_INT_EN 24 24 PERFCOUNTER_OFF_MASK 25 25 PERFCOUNTER_ACTIVE 26 26 PERFCOUNTER_CNTL_SEL 29 31 mmDC_PERFMON14_PERFCOUNTER_CNTL2 0 0xf83 5 0 2 PERFCOUNTER_COUNTED_VALUE_TYPE 0 1 PERFCOUNTER_HW_STOP1_SEL 2 2 PERFCOUNTER_HW_STOP2_SEL 3 3 PERFCOUNTER_CNTOFF_SEL 8 13 PERFCOUNTER_CNTL2_SEL 29 31 mmDC_PERFMON14_PERFCOUNTER_STATE 0 0xf84 16 0 2 PERFCOUNTER_CNT0_STATE 0 1 PERFCOUNTER_STATE_SEL0 2 2 PERFCOUNTER_CNT1_STATE 4 5 PERFCOUNTER_STATE_SEL1 6 6 PERFCOUNTER_CNT2_STATE 8 9 PERFCOUNTER_STATE_SEL2 10 10 PERFCOUNTER_CNT3_STATE 12 13 PERFCOUNTER_STATE_SEL3 14 14 PERFCOUNTER_CNT4_STATE 16 17 PERFCOUNTER_STATE_SEL4 18 18 PERFCOUNTER_CNT5_STATE 20 21 PERFCOUNTER_STATE_SEL5 22 22 PERFCOUNTER_CNT6_STATE 24 25 PERFCOUNTER_STATE_SEL6 26 26 PERFCOUNTER_CNT7_STATE 28 29 PERFCOUNTER_STATE_SEL7 30 30 mmDC_PERFMON14_PERFMON_CNTL 0 0xf85 6 0 2 PERFMON_STATE 0 1 PERFMON_RPT_COUNT 8 27 PERFMON_CNTOFF_AND_OR 28 28 PERFMON_CNTOFF_INT_EN 29 29 PERFMON_CNTOFF_INT_STATUS 30 30 PERFMON_CNTOFF_INT_ACK 31 31 mmDC_PERFMON14_PERFMON_CNTL2 0 0xf86 4 0 2 PERFMON_CNTOFF_INT_TYPE 0 0 PERFMON_CLK_ENABLE 1 1 PERFMON_RUN_ENABLE_START_SEL 2 9 PERFMON_RUN_ENABLE_STOP_SEL 10 17 mmDC_PERFMON14_PERFMON_CVALUE_INT_MISC 0 0xf87 17 0 2 PERFCOUNTER_INT0_STATUS 0 0 PERFCOUNTER_INT1_STATUS 1 1 PERFCOUNTER_INT2_STATUS 2 2 PERFCOUNTER_INT3_STATUS 3 3 PERFCOUNTER_INT4_STATUS 4 4 PERFCOUNTER_INT5_STATUS 5 5 PERFCOUNTER_INT6_STATUS 6 6 PERFCOUNTER_INT7_STATUS 7 7 PERFCOUNTER_INT0_ACK 8 8 PERFCOUNTER_INT1_ACK 9 9 PERFCOUNTER_INT2_ACK 10 10 PERFCOUNTER_INT3_ACK 11 11 PERFCOUNTER_INT4_ACK 12 12 PERFCOUNTER_INT5_ACK 13 13 PERFCOUNTER_INT6_ACK 14 14 PERFCOUNTER_INT7_ACK 15 15 PERFMON_CVALUE_HI 16 31 mmDC_PERFMON14_PERFMON_CVALUE_LOW 0 0xf88 1 0 2 PERFMON_CVALUE_LOW 0 31 mmDC_PERFMON14_PERFMON_HI 0 0xf89 2 0 2 PERFMON_HI 0 15 PERFMON_READ_SEL 29 31 mmDC_PERFMON14_PERFMON_LOW 0 0xf8a 1 0 2 PERFMON_LOW 0 31 mmDPP_TOP3_DPP_CONTROL 0 0xf8e 9 0 2 DPP_CLOCK_ENABLE 4 4 DPPCLK_G_GATE_DISABLE 8 8 DPPCLK_G_DYN_GATE_DISABLE 10 10 DPPCLK_G_DSCL_GATE_DISABLE 12 12 DPPCLK_R_GATE_DISABLE 16 16 DISPCLK_R_GATE_DISABLE 18 18 DISPCLK_G_GATE_DISABLE 20 20 DPPCLK_RATE_CONTROL 24 24 DPP_TEST_CLK_SEL 28 30 mmDPP_TOP3_DPP_SOFT_RESET 0 0xf8f 4 0 2 CNVC_SOFT_RESET 0 0 DSCL_SOFT_RESET 4 4 CM_SOFT_RESET 8 8 OBUF_SOFT_RESET 12 12 mmDPP_TOP3_DPP_CRC_VAL_R_G 0 0xf90 2 0 2 DPP_CRC_R_CR 0 15 DPP_CRC_G_Y 16 31 mmDPP_TOP3_DPP_CRC_VAL_B_A 0 0xf91 2 0 2 DPP_CRC_B_CB 0 15 DPP_CRC_ALPHA 16 31 mmDPP_TOP3_DPP_CRC_CTRL 0 0xf92 11 0 2 DPP_CRC_EN 0 0 DPP_CRC_CONT_EN 1 1 DPP_CRC_ONE_SHOT_PENDING 2 2 DPP_CRC_420_COMP_SEL 3 3 DPP_CRC_SRC_SEL 4 5 DPP_CRC_STEREO_EN 7 7 DPP_CRC_STEREO_MODE 8 9 DPP_CRC_INTERLACE_MODE 10 11 DPP_CRC_PIX_FORMAT_SEL 12 14 DPP_CRC_CURSOR_FORMAT_SEL 15 15 DPP_CRC_MASK 16 31 mmDPP_TOP3_HOST_READ_CONTROL 0 0xf93 1 0 2 HOST_READ_RATE_CONTROL 0 7 mmCNVC_CFG3_CNVC_SURFACE_PIXEL_FORMAT 0 0xf98 1 0 2 CNVC_SURFACE_PIXEL_FORMAT 0 6 mmCNVC_CFG3_FORMAT_CONTROL 0 0xf99 6 0 2 FORMAT_EXPANSION_MODE 0 0 FORMAT_CNV16 4 4 ALPHA_EN 8 8 CNVC_BYPASS 12 12 OUTPUT_FP 16 16 CNVC_UPDATE_PENDING 20 20 mmCNVC_CFG3_FCNV_FP_SCALE_BIAS 0 0xf9a 2 0 2 FCNV_FP_SCALE 0 15 FCNV_FP_BIAS 16 31 mmCNVC_CFG3_DENORM_CONTROL 0 0xf9b 4 0 2 DENORM_SCALE 0 14 CLAMP_POSITIVE 15 15 DENORM_BIAS 16 30 DENORM_TRUNCATE 31 31 mmCNVC_CFG3_COLOR_KEYER_CONTROL 0 0xf9d 2 0 2 COLOR_KEYER_EN 0 0 COLOR_KEYER_MODE 4 5 mmCNVC_CFG3_COLOR_KEYER_ALPHA 0 0xf9e 2 0 2 COLOR_KEYER_ALPHA_LOW 0 15 COLOR_KEYER_ALPHA_HIGH 16 31 mmCNVC_CFG3_COLOR_KEYER_RED 0 0xf9f 2 0 2 COLOR_KEYER_RED_LOW 0 15 COLOR_KEYER_RED_HIGH 16 31 mmCNVC_CFG3_COLOR_KEYER_GREEN 0 0xfa0 2 0 2 COLOR_KEYER_GREEN_LOW 0 15 COLOR_KEYER_GREEN_HIGH 16 31 mmCNVC_CFG3_COLOR_KEYER_BLUE 0 0xfa1 2 0 2 COLOR_KEYER_BLUE_LOW 0 15 COLOR_KEYER_BLUE_HIGH 16 31 mmCNVC_CUR3_CURSOR0_CONTROL 0 0xfa9 7 0 2 CUR0_ENABLE 0 0 CUR0_EXPANSION_MODE 1 1 CUR0_INVERT_MODE 2 2 CUR0_MODE 4 5 CUR0_UPDATE_PENDING 6 6 CUR0_MAX 8 19 CUR0_MIN 20 31 mmCNVC_CUR3_CURSOR0_COLOR0 0 0xfaa 1 0 2 CUR0_COLOR0 0 23 mmCNVC_CUR3_CURSOR0_COLOR1 0 0xfab 1 0 2 CUR0_COLOR1 0 23 mmCNVC_CUR3_CURSOR0_FP_SCALE_BIAS 0 0xfac 2 0 2 CUR0_FP_SCALE 0 15 CUR0_FP_BIAS 16 31 mmDSCL3_SCL_COEF_RAM_TAP_SELECT 0 0xfb3 3 0 2 SCL_COEF_RAM_TAP_PAIR_IDX 0 1 SCL_COEF_RAM_PHASE 8 13 SCL_COEF_RAM_FILTER_TYPE 16 18 mmDSCL3_SCL_COEF_RAM_TAP_DATA 0 0xfb4 4 0 2 SCL_COEF_RAM_EVEN_TAP_COEF 0 13 SCL_COEF_RAM_EVEN_TAP_COEF_EN 15 15 SCL_COEF_RAM_ODD_TAP_COEF 16 29 SCL_COEF_RAM_ODD_TAP_COEF_EN 31 31 mmDSCL3_SCL_MODE 0 0xfb5 6 0 2 DSCL_MODE 0 2 SCL_COEF_RAM_SELECT 8 8 SCL_COEF_RAM_SELECT_CURRENT 12 12 SCL_CHROMA_COEF_MODE 16 16 SCL_ALPHA_COEF_MODE 20 20 SCL_COEF_RAM_SELECT_RD 24 24 mmDSCL3_SCL_TAP_CONTROL 0 0xfb6 4 0 2 SCL_V_NUM_TAPS 0 2 SCL_H_NUM_TAPS 4 6 SCL_V_NUM_TAPS_C 8 10 SCL_H_NUM_TAPS_C 12 14 mmDSCL3_DSCL_CONTROL 0 0xfb7 1 0 2 SCL_BOUNDARY_MODE 0 0 mmDSCL3_DSCL_2TAP_CONTROL 0 0xfb8 6 0 2 SCL_H_2TAP_HARDCODE_COEF_EN 0 0 SCL_H_2TAP_SHARP_EN 4 4 SCL_H_2TAP_SHARP_FACTOR 8 10 SCL_V_2TAP_HARDCODE_COEF_EN 16 16 SCL_V_2TAP_SHARP_EN 20 20 SCL_V_2TAP_SHARP_FACTOR 24 26 mmDSCL3_SCL_MANUAL_REPLICATE_CONTROL 0 0xfb9 2 0 2 SCL_V_MANUAL_REPLICATE_FACTOR 0 3 SCL_H_MANUAL_REPLICATE_FACTOR 8 11 mmDSCL3_SCL_HORZ_FILTER_SCALE_RATIO 0 0xfba 1 0 2 SCL_H_SCALE_RATIO 0 25 mmDSCL3_SCL_HORZ_FILTER_INIT 0 0xfbb 2 0 2 SCL_H_INIT_FRAC 0 23 SCL_H_INIT_INT 24 27 mmDSCL3_SCL_HORZ_FILTER_SCALE_RATIO_C 0 0xfbc 1 0 2 SCL_H_SCALE_RATIO_C 0 25 mmDSCL3_SCL_HORZ_FILTER_INIT_C 0 0xfbd 2 0 2 SCL_H_INIT_FRAC_C 0 23 SCL_H_INIT_INT_C 24 27 mmDSCL3_SCL_VERT_FILTER_SCALE_RATIO 0 0xfbe 1 0 2 SCL_V_SCALE_RATIO 0 25 mmDSCL3_SCL_VERT_FILTER_INIT 0 0xfbf 2 0 2 SCL_V_INIT_FRAC 0 23 SCL_V_INIT_INT 24 27 mmDSCL3_SCL_VERT_FILTER_INIT_BOT 0 0xfc0 2 0 2 SCL_V_INIT_FRAC_BOT 0 23 SCL_V_INIT_INT_BOT 24 27 mmDSCL3_SCL_VERT_FILTER_SCALE_RATIO_C 0 0xfc1 1 0 2 SCL_V_SCALE_RATIO_C 0 25 mmDSCL3_SCL_VERT_FILTER_INIT_C 0 0xfc2 2 0 2 SCL_V_INIT_FRAC_C 0 23 SCL_V_INIT_INT_C 24 27 mmDSCL3_SCL_VERT_FILTER_INIT_BOT_C 0 0xfc3 2 0 2 SCL_V_INIT_FRAC_BOT_C 0 23 SCL_V_INIT_INT_BOT_C 24 27 mmDSCL3_SCL_BLACK_OFFSET 0 0xfc4 2 0 2 SCL_BLACK_OFFSET_RGB_Y 0 15 SCL_BLACK_OFFSET_CBCR 16 31 mmDSCL3_DSCL_UPDATE 0 0xfc5 1 0 2 SCL_UPDATE_PENDING 0 0 mmDSCL3_DSCL_AUTOCAL 0 0xfc6 3 0 2 AUTOCAL_MODE 0 1 AUTOCAL_NUM_PIPE 8 9 AUTOCAL_PIPE_ID 12 13 mmDSCL3_DSCL_EXT_OVERSCAN_LEFT_RIGHT 0 0xfc7 2 0 2 EXT_OVERSCAN_RIGHT 0 12 EXT_OVERSCAN_LEFT 16 28 mmDSCL3_DSCL_EXT_OVERSCAN_TOP_BOTTOM 0 0xfc8 2 0 2 EXT_OVERSCAN_BOTTOM 0 12 EXT_OVERSCAN_TOP 16 28 mmDSCL3_OTG_H_BLANK 0 0xfc9 2 0 2 OTG_H_BLANK_START 0 13 OTG_H_BLANK_END 16 29 mmDSCL3_OTG_V_BLANK 0 0xfca 2 0 2 OTG_V_BLANK_START 0 13 OTG_V_BLANK_END 16 29 mmDSCL3_RECOUT_START 0 0xfcb 2 0 2 RECOUT_START_X 0 12 RECOUT_START_Y 16 28 mmDSCL3_RECOUT_SIZE 0 0xfcc 2 0 2 RECOUT_WIDTH 0 13 RECOUT_HEIGHT 16 29 mmDSCL3_MPC_SIZE 0 0xfcd 2 0 2 MPC_WIDTH 0 13 MPC_HEIGHT 16 29 mmDSCL3_LB_DATA_FORMAT 0 0xfce 7 0 2 PIXEL_DEPTH 0 1 PIXEL_EXPAN_MODE 8 8 PIXEL_REDUCE_MODE 12 12 DYNAMIC_PIXEL_DEPTH 16 16 DITHER_EN 20 20 INTERLEAVE_EN 24 24 ALPHA_EN 31 31 mmDSCL3_LB_MEMORY_CTRL 0 0xfcf 4 0 2 MEMORY_CONFIG 0 1 LB_MAX_PARTITIONS 8 13 LB_NUM_PARTITIONS 16 22 LB_NUM_PARTITIONS_C 24 30 mmDSCL3_LB_V_COUNTER 0 0xfd0 2 0 2 V_COUNTER 0 12 V_COUNTER_C 16 28 mmDSCL3_DSCL_MEM_PWR_CTRL 0 0xfd1 14 0 2 LUT_MEM_PWR_FORCE 0 1 LUT_MEM_PWR_DIS 2 2 LB_G1_MEM_PWR_FORCE 4 5 LB_G1_MEM_PWR_DIS 6 6 LB_G2_MEM_PWR_FORCE 8 9 LB_G2_MEM_PWR_DIS 10 10 LB_G3_MEM_PWR_FORCE 12 13 LB_G3_MEM_PWR_DIS 14 14 LB_G4_MEM_PWR_FORCE 16 17 LB_G4_MEM_PWR_DIS 18 18 LB_G5_MEM_PWR_FORCE 20 21 LB_G5_MEM_PWR_DIS 22 22 LB_G6_MEM_PWR_FORCE 24 25 LB_G6_MEM_PWR_DIS 26 26 mmDSCL3_DSCL_MEM_PWR_STATUS 0 0xfd2 7 0 2 LUT_MEM_PWR_STATE 0 1 LB_G1_MEM_PWR_STATE 2 3 LB_G2_MEM_PWR_STATE 4 5 LB_G3_MEM_PWR_STATE 6 7 LB_G4_MEM_PWR_STATE 8 9 LB_G5_MEM_PWR_STATE 10 11 LB_G6_MEM_PWR_STATE 12 13 mmDSCL3_OBUF_CONTROL 0 0xfd3 7 0 2 OBUF_BYPASS 0 0 OBUF_USE_FULL_BUFFER 4 4 OBUF_H_2X_UPSCALE_EN 8 8 OBUF_IS_HALF_RECOUT_WIDTH 12 12 OBUF_H_2X_COEF_PHASE0_SEL 16 16 OBUF_H_2X_COEF_PHASE1_SEL 24 24 OBUF_OUT_HOLD_CNT 28 31 mmDSCL3_OBUF_MEM_PWR_CTRL 0 0xfd4 3 0 2 OBUF_MEM_PWR_FORCE 0 1 OBUF_MEM_PWR_DIS 2 2 OBUF_MEM_PWR_STATE 16 17 mmCM3_CM_CONTROL 0 0xfe3 2 0 2 CM_BYPASS_EN 0 0 CM_UPDATE_PENDING 8 8 mmCM3_CM_COMA_C11_C12 0 0xfe4 2 0 2 CM_COMA_C11 0 15 CM_COMA_C12 16 31 mmCM3_CM_COMA_C13_C14 0 0xfe5 2 0 2 CM_COMA_C13 0 15 CM_COMA_C14 16 31 mmCM3_CM_COMA_C21_C22 0 0xfe6 2 0 2 CM_COMA_C21 0 15 CM_COMA_C22 16 31 mmCM3_CM_COMA_C23_C24 0 0xfe7 2 0 2 CM_COMA_C23 0 15 CM_COMA_C24 16 31 mmCM3_CM_COMA_C31_C32 0 0xfe8 2 0 2 CM_COMA_C31 0 15 CM_COMA_C32 16 31 mmCM3_CM_COMA_C33_C34 0 0xfe9 2 0 2 CM_COMA_C33 0 15 CM_COMA_C34 16 31 mmCM3_CM_COMB_C11_C12 0 0xfea 2 0 2 CM_COMB_C11 0 15 CM_COMB_C12 16 31 mmCM3_CM_COMB_C13_C14 0 0xfeb 2 0 2 CM_COMB_C13 0 15 CM_COMB_C14 16 31 mmCM3_CM_COMB_C21_C22 0 0xfec 2 0 2 CM_COMB_C21 0 15 CM_COMB_C22 16 31 mmCM3_CM_COMB_C23_C24 0 0xfed 2 0 2 CM_COMB_C23 0 15 CM_COMB_C24 16 31 mmCM3_CM_COMB_C31_C32 0 0xfee 2 0 2 CM_COMB_C31 0 15 CM_COMB_C32 16 31 mmCM3_CM_COMB_C33_C34 0 0xfef 2 0 2 CM_COMB_C33 0 15 CM_COMB_C34 16 31 mmCM3_CM_IGAM_CONTROL 0 0xff0 14 0 2 CM_IGAM_LUT_MODE 0 1 CM_IGAM_LUT_DATA_SIGNED_EN_B 2 2 CM_IGAM_LUT_DATA_SIGNED_EN_G 3 3 CM_IGAM_LUT_DATA_SIGNED_EN_R 4 4 CM_IGAM_LUT_INC_B 5 8 CM_IGAM_LUT_INC_G 9 12 CM_IGAM_LUT_INC_R 13 16 CM_IGAM_LUT_FORMAT_B 17 18 CM_IGAM_LUT_FORMAT_G 19 20 CM_IGAM_LUT_FORMAT_R 21 22 CM_IGAM_LUT_B_FLOAT_POINT_EN 23 23 CM_IGAM_LUT_G_FLOAT_POINT_EN 24 24 CM_IGAM_LUT_R_FLOAT_POINT_EN 25 25 CM_IGAM_INPUT_FORMAT 26 27 mmCM3_CM_IGAM_LUT_RW_CONTROL 0 0xff1 5 0 2 CM_IGAM_LUT_RW_MODE 0 0 CM_IGAM_LUT_WRITE_EN_MASK 4 6 CM_IGAM_LUT_SEL 8 8 CM_IGAM_LUT_HOST_EN 12 12 CM_IGAM_DGAM_CONFIG_STATUS 16 19 mmCM3_CM_IGAM_LUT_RW_INDEX 0 0xff2 1 0 2 CM_IGAM_LUT_RW_INDEX 0 7 mmCM3_CM_IGAM_LUT_SEQ_COLOR 0 0xff3 1 0 2 CM_IGAM_LUT_SEQ_COLOR 0 15 mmCM3_CM_IGAM_LUT_30_COLOR 0 0xff4 3 0 2 CM_IGAM_LUT_10_BLUE 0 9 CM_IGAM_LUT_10_GREEN 10 19 CM_IGAM_LUT_10_RED 20 29 mmCM3_CM_IGAM_LUT_PWL_DATA 0 0xff5 2 0 2 CM_IGAM_LUT_PWL_BASE 0 15 CM_IGAM_LUT_PWL_DELTA 16 31 mmCM3_CM_IGAM_LUT_AUTOFILL 0 0xff6 2 0 2 CM_IGAM_LUT_AUTOFILL 0 0 CM_IGAM_LUT_AUTOFILL_DONE 4 4 mmCM3_CM_IGAM_LUT_BW_OFFSET_BLUE 0 0xff7 2 0 2 CM_IGAM_LUT_BLACK_OFFSET_BLUE 0 15 CM_IGAM_LUT_WHITE_OFFSET_BLUE 16 31 mmCM3_CM_IGAM_LUT_BW_OFFSET_GREEN 0 0xff8 2 0 2 CM_IGAM_LUT_BLACK_OFFSET_GREEN 0 15 CM_IGAM_LUT_WHITE_OFFSET_GREEN 16 31 mmCM3_CM_IGAM_LUT_BW_OFFSET_RED 0 0xff9 2 0 2 CM_IGAM_LUT_BLACK_OFFSET_RED 0 15 CM_IGAM_LUT_WHITE_OFFSET_RED 16 31 mmCM3_CM_ICSC_CONTROL 0 0xffa 1 0 2 CM_ICSC_MODE 0 1 mmCM3_CM_ICSC_C11_C12 0 0xffb 2 0 2 CM_ICSC_C11 0 15 CM_ICSC_C12 16 31 mmCM3_CM_ICSC_C13_C14 0 0xffc 2 0 2 CM_ICSC_C13 0 15 CM_ICSC_C14 16 31 mmCM3_CM_ICSC_C21_C22 0 0xffd 2 0 2 CM_ICSC_C21 0 15 CM_ICSC_C22 16 31 mmCM3_CM_ICSC_C23_C24 0 0xffe 2 0 2 CM_ICSC_C23 0 15 CM_ICSC_C24 16 31 mmCM3_CM_ICSC_C31_C32 0 0xfff 2 0 2 CM_ICSC_C31 0 15 CM_ICSC_C32 16 31 mmCM3_CM_ICSC_C33_C34 0 0x1000 2 0 2 CM_ICSC_C33 0 15 CM_ICSC_C34 16 31 mmCM3_CM_GAMUT_REMAP_CONTROL 0 0x1001 1 0 2 CM_GAMUT_REMAP_MODE 0 1 mmCM3_CM_GAMUT_REMAP_C11_C12 0 0x1002 2 0 2 CM_GAMUT_REMAP_C11 0 15 CM_GAMUT_REMAP_C12 16 31 mmCM3_CM_GAMUT_REMAP_C13_C14 0 0x1003 2 0 2 CM_GAMUT_REMAP_C13 0 15 CM_GAMUT_REMAP_C14 16 31 mmCM3_CM_GAMUT_REMAP_C21_C22 0 0x1004 2 0 2 CM_GAMUT_REMAP_C21 0 15 CM_GAMUT_REMAP_C22 16 31 mmCM3_CM_GAMUT_REMAP_C23_C24 0 0x1005 2 0 2 CM_GAMUT_REMAP_C23 0 15 CM_GAMUT_REMAP_C24 16 31 mmCM3_CM_GAMUT_REMAP_C31_C32 0 0x1006 2 0 2 CM_GAMUT_REMAP_C31 0 15 CM_GAMUT_REMAP_C32 16 31 mmCM3_CM_GAMUT_REMAP_C33_C34 0 0x1007 2 0 2 CM_GAMUT_REMAP_C33 0 15 CM_GAMUT_REMAP_C34 16 31 mmCM3_CM_OCSC_CONTROL 0 0x1008 1 0 2 CM_OCSC_MODE 0 2 mmCM3_CM_OCSC_C11_C12 0 0x1009 2 0 2 CM_OCSC_C11 0 15 CM_OCSC_C12 16 31 mmCM3_CM_OCSC_C13_C14 0 0x100a 2 0 2 CM_OCSC_C13 0 15 CM_OCSC_C14 16 31 mmCM3_CM_OCSC_C21_C22 0 0x100b 2 0 2 CM_OCSC_C21 0 15 CM_OCSC_C22 16 31 mmCM3_CM_OCSC_C23_C24 0 0x100c 2 0 2 CM_OCSC_C23 0 15 CM_OCSC_C24 16 31 mmCM3_CM_OCSC_C31_C32 0 0x100d 2 0 2 CM_OCSC_C31 0 15 CM_OCSC_C32 16 31 mmCM3_CM_OCSC_C33_C34 0 0x100e 2 0 2 CM_OCSC_C33 0 15 CM_OCSC_C34 16 31 mmCM3_CM_BNS_VALUES_R 0 0x100f 2 0 2 CM_BNS_BIAS_R 0 15 CM_BNS_SCALE_R 16 31 mmCM3_CM_BNS_VALUES_G 0 0x1010 2 0 2 CM_BNS_BIAS_G 0 15 CM_BNS_SCALE_G 16 31 mmCM3_CM_BNS_VALUES_B 0 0x1011 2 0 2 CM_BNS_BIAS_B 0 15 CM_BNS_SCALE_B 16 31 mmCM3_CM_DGAM_CONTROL 0 0x1012 1 0 2 CM_DGAM_LUT_MODE 0 2 mmCM3_CM_DGAM_LUT_INDEX 0 0x1013 1 0 2 CM_DGAM_LUT_INDEX 0 8 mmCM3_CM_DGAM_LUT_DATA 0 0x1014 1 0 2 CM_DGAM_LUT_DATA 0 18 mmCM3_CM_DGAM_LUT_WRITE_EN_MASK 0 0x1015 2 0 2 CM_DGAM_LUT_WRITE_EN_MASK 0 2 CM_DGAM_LUT_WRITE_SEL 4 4 mmCM3_CM_DGAM_RAMA_START_CNTL_B 0 0x1016 2 0 2 CM_DGAM_RAMA_EXP_REGION_START_B 0 17 CM_DGAM_RAMA_EXP_REGION_START_SEGMENT_B 20 26 mmCM3_CM_DGAM_RAMA_START_CNTL_G 0 0x1017 2 0 2 CM_DGAM_RAMA_EXP_REGION_START_G 0 17 CM_DGAM_RAMA_EXP_REGION_START_SEGMENT_G 20 26 mmCM3_CM_DGAM_RAMA_START_CNTL_R 0 0x1018 2 0 2 CM_DGAM_RAMA_EXP_REGION_START_R 0 17 CM_DGAM_RAMA_EXP_REGION_START_SEGMENT_R 20 26 mmCM3_CM_DGAM_RAMA_SLOPE_CNTL_B 0 0x1019 1 0 2 CM_DGAM_RAMA_EXP_REGION_LINEAR_SLOPE_B 0 17 mmCM3_CM_DGAM_RAMA_SLOPE_CNTL_G 0 0x101a 1 0 2 CM_DGAM_RAMA_EXP_REGION_LINEAR_SLOPE_G 0 17 mmCM3_CM_DGAM_RAMA_SLOPE_CNTL_R 0 0x101b 1 0 2 CM_DGAM_RAMA_EXP_REGION_LINEAR_SLOPE_R 0 17 mmCM3_CM_DGAM_RAMA_END_CNTL1_B 0 0x101c 1 0 2 CM_DGAM_RAMA_EXP_REGION_END_B 0 15 mmCM3_CM_DGAM_RAMA_END_CNTL2_B 0 0x101d 2 0 2 CM_DGAM_RAMA_EXP_REGION_END_SLOPE_B 0 15 CM_DGAM_RAMA_EXP_REGION_END_BASE_B 16 31 mmCM3_CM_DGAM_RAMA_END_CNTL1_G 0 0x101e 1 0 2 CM_DGAM_RAMA_EXP_REGION_END_G 0 15 mmCM3_CM_DGAM_RAMA_END_CNTL2_G 0 0x101f 2 0 2 CM_DGAM_RAMA_EXP_REGION_END_SLOPE_G 0 15 CM_DGAM_RAMA_EXP_REGION_END_BASE_G 16 31 mmCM3_CM_DGAM_RAMA_END_CNTL1_R 0 0x1020 1 0 2 CM_DGAM_RAMA_EXP_REGION_END_R 0 15 mmCM3_CM_DGAM_RAMA_END_CNTL2_R 0 0x1021 2 0 2 CM_DGAM_RAMA_EXP_REGION_END_SLOPE_R 0 15 CM_DGAM_RAMA_EXP_REGION_END_BASE_R 16 31 mmCM3_CM_DGAM_RAMA_REGION_0_1 0 0x1022 4 0 2 CM_DGAM_RAMA_EXP_REGION0_LUT_OFFSET 0 8 CM_DGAM_RAMA_EXP_REGION0_NUM_SEGMENTS 12 14 CM_DGAM_RAMA_EXP_REGION1_LUT_OFFSET 16 24 CM_DGAM_RAMA_EXP_REGION1_NUM_SEGMENTS 28 30 mmCM3_CM_DGAM_RAMA_REGION_2_3 0 0x1023 4 0 2 CM_DGAM_RAMA_EXP_REGION2_LUT_OFFSET 0 8 CM_DGAM_RAMA_EXP_REGION2_NUM_SEGMENTS 12 14 CM_DGAM_RAMA_EXP_REGION3_LUT_OFFSET 16 24 CM_DGAM_RAMA_EXP_REGION3_NUM_SEGMENTS 28 30 mmCM3_CM_DGAM_RAMA_REGION_4_5 0 0x1024 4 0 2 CM_DGAM_RAMA_EXP_REGION4_LUT_OFFSET 0 8 CM_DGAM_RAMA_EXP_REGION4_NUM_SEGMENTS 12 14 CM_DGAM_RAMA_EXP_REGION5_LUT_OFFSET 16 24 CM_DGAM_RAMA_EXP_REGION5_NUM_SEGMENTS 28 30 mmCM3_CM_DGAM_RAMA_REGION_6_7 0 0x1025 4 0 2 CM_DGAM_RAMA_EXP_REGION6_LUT_OFFSET 0 8 CM_DGAM_RAMA_EXP_REGION6_NUM_SEGMENTS 12 14 CM_DGAM_RAMA_EXP_REGION7_LUT_OFFSET 16 24 CM_DGAM_RAMA_EXP_REGION7_NUM_SEGMENTS 28 30 mmCM3_CM_DGAM_RAMA_REGION_8_9 0 0x1026 4 0 2 CM_DGAM_RAMA_EXP_REGION8_LUT_OFFSET 0 8 CM_DGAM_RAMA_EXP_REGION8_NUM_SEGMENTS 12 14 CM_DGAM_RAMA_EXP_REGION9_LUT_OFFSET 16 24 CM_DGAM_RAMA_EXP_REGION9_NUM_SEGMENTS 28 30 mmCM3_CM_DGAM_RAMA_REGION_10_11 0 0x1027 4 0 2 CM_DGAM_RAMA_EXP_REGION10_LUT_OFFSET 0 8 CM_DGAM_RAMA_EXP_REGION10_NUM_SEGMENTS 12 14 CM_DGAM_RAMA_EXP_REGION11_LUT_OFFSET 16 24 CM_DGAM_RAMA_EXP_REGION11_NUM_SEGMENTS 28 30 mmCM3_CM_DGAM_RAMA_REGION_12_13 0 0x1028 4 0 2 CM_DGAM_RAMA_EXP_REGION12_LUT_OFFSET 0 8 CM_DGAM_RAMA_EXP_REGION12_NUM_SEGMENTS 12 14 CM_DGAM_RAMA_EXP_REGION13_LUT_OFFSET 16 24 CM_DGAM_RAMA_EXP_REGION13_NUM_SEGMENTS 28 30 mmCM3_CM_DGAM_RAMA_REGION_14_15 0 0x1029 4 0 2 CM_DGAM_RAMA_EXP_REGION14_LUT_OFFSET 0 8 CM_DGAM_RAMA_EXP_REGION14_NUM_SEGMENTS 12 14 CM_DGAM_RAMA_EXP_REGION15_LUT_OFFSET 16 24 CM_DGAM_RAMA_EXP_REGION15_NUM_SEGMENTS 28 30 mmCM3_CM_DGAM_RAMB_START_CNTL_B 0 0x102a 2 0 2 CM_DGAM_RAMB_EXP_REGION_START_B 0 17 CM_DGAM_RAMB_EXP_REGION_START_SEGMENT_B 20 26 mmCM3_CM_DGAM_RAMB_START_CNTL_G 0 0x102b 2 0 2 CM_DGAM_RAMB_EXP_REGION_START_G 0 17 CM_DGAM_RAMB_EXP_REGION_START_SEGMENT_G 20 26 mmCM3_CM_DGAM_RAMB_START_CNTL_R 0 0x102c 2 0 2 CM_DGAM_RAMB_EXP_REGION_START_R 0 17 CM_DGAM_RAMB_EXP_REGION_START_SEGMENT_R 20 26 mmCM3_CM_DGAM_RAMB_SLOPE_CNTL_B 0 0x102d 1 0 2 CM_DGAM_RAMB_EXP_REGION_LINEAR_SLOPE_B 0 17 mmCM3_CM_DGAM_RAMB_SLOPE_CNTL_G 0 0x102e 1 0 2 CM_DGAM_RAMB_EXP_REGION_LINEAR_SLOPE_G 0 17 mmCM3_CM_DGAM_RAMB_SLOPE_CNTL_R 0 0x102f 1 0 2 CM_DGAM_RAMB_EXP_REGION_LINEAR_SLOPE_R 0 17 mmCM3_CM_DGAM_RAMB_END_CNTL1_B 0 0x1030 1 0 2 CM_DGAM_RAMB_EXP_REGION_END_B 0 15 mmCM3_CM_DGAM_RAMB_END_CNTL2_B 0 0x1031 2 0 2 CM_DGAM_RAMB_EXP_REGION_END_SLOPE_B 0 15 CM_DGAM_RAMB_EXP_REGION_END_BASE_B 16 31 mmCM3_CM_DGAM_RAMB_END_CNTL1_G 0 0x1032 1 0 2 CM_DGAM_RAMB_EXP_REGION_END_G 0 15 mmCM3_CM_DGAM_RAMB_END_CNTL2_G 0 0x1033 2 0 2 CM_DGAM_RAMB_EXP_REGION_END_SLOPE_G 0 15 CM_DGAM_RAMB_EXP_REGION_END_BASE_G 16 31 mmCM3_CM_DGAM_RAMB_END_CNTL1_R 0 0x1034 1 0 2 CM_DGAM_RAMB_EXP_REGION_END_R 0 15 mmCM3_CM_DGAM_RAMB_END_CNTL2_R 0 0x1035 2 0 2 CM_DGAM_RAMB_EXP_REGION_END_SLOPE_R 0 15 CM_DGAM_RAMB_EXP_REGION_END_BASE_R 16 31 mmCM3_CM_DGAM_RAMB_REGION_0_1 0 0x1036 4 0 2 CM_DGAM_RAMB_EXP_REGION0_LUT_OFFSET 0 8 CM_DGAM_RAMB_EXP_REGION0_NUM_SEGMENTS 12 14 CM_DGAM_RAMB_EXP_REGION1_LUT_OFFSET 16 24 CM_DGAM_RAMB_EXP_REGION1_NUM_SEGMENTS 28 30 mmCM3_CM_DGAM_RAMB_REGION_2_3 0 0x1037 4 0 2 CM_DGAM_RAMB_EXP_REGION2_LUT_OFFSET 0 8 CM_DGAM_RAMB_EXP_REGION2_NUM_SEGMENTS 12 14 CM_DGAM_RAMB_EXP_REGION3_LUT_OFFSET 16 24 CM_DGAM_RAMB_EXP_REGION3_NUM_SEGMENTS 28 30 mmCM3_CM_DGAM_RAMB_REGION_4_5 0 0x1038 4 0 2 CM_DGAM_RAMB_EXP_REGION4_LUT_OFFSET 0 8 CM_DGAM_RAMB_EXP_REGION4_NUM_SEGMENTS 12 14 CM_DGAM_RAMB_EXP_REGION5_LUT_OFFSET 16 24 CM_DGAM_RAMB_EXP_REGION5_NUM_SEGMENTS 28 30 mmCM3_CM_DGAM_RAMB_REGION_6_7 0 0x1039 4 0 2 CM_DGAM_RAMB_EXP_REGION6_LUT_OFFSET 0 8 CM_DGAM_RAMB_EXP_REGION6_NUM_SEGMENTS 12 14 CM_DGAM_RAMB_EXP_REGION7_LUT_OFFSET 16 24 CM_DGAM_RAMB_EXP_REGION7_NUM_SEGMENTS 28 30 mmCM3_CM_DGAM_RAMB_REGION_8_9 0 0x103a 4 0 2 CM_DGAM_RAMB_EXP_REGION8_LUT_OFFSET 0 8 CM_DGAM_RAMB_EXP_REGION8_NUM_SEGMENTS 12 14 CM_DGAM_RAMB_EXP_REGION9_LUT_OFFSET 16 24 CM_DGAM_RAMB_EXP_REGION9_NUM_SEGMENTS 28 30 mmCM3_CM_DGAM_RAMB_REGION_10_11 0 0x103b 4 0 2 CM_DGAM_RAMB_EXP_REGION10_LUT_OFFSET 0 8 CM_DGAM_RAMB_EXP_REGION10_NUM_SEGMENTS 12 14 CM_DGAM_RAMB_EXP_REGION11_LUT_OFFSET 16 24 CM_DGAM_RAMB_EXP_REGION11_NUM_SEGMENTS 28 30 mmCM3_CM_DGAM_RAMB_REGION_12_13 0 0x103c 4 0 2 CM_DGAM_RAMB_EXP_REGION12_LUT_OFFSET 0 8 CM_DGAM_RAMB_EXP_REGION12_NUM_SEGMENTS 12 14 CM_DGAM_RAMB_EXP_REGION13_LUT_OFFSET 16 24 CM_DGAM_RAMB_EXP_REGION13_NUM_SEGMENTS 28 30 mmCM3_CM_DGAM_RAMB_REGION_14_15 0 0x103d 4 0 2 CM_DGAM_RAMB_EXP_REGION14_LUT_OFFSET 0 8 CM_DGAM_RAMB_EXP_REGION14_NUM_SEGMENTS 12 14 CM_DGAM_RAMB_EXP_REGION15_LUT_OFFSET 16 24 CM_DGAM_RAMB_EXP_REGION15_NUM_SEGMENTS 28 30 mmCM3_CM_RGAM_CONTROL 0 0x103e 1 0 2 CM_RGAM_LUT_MODE 0 2 mmCM3_CM_RGAM_LUT_INDEX 0 0x103f 1 0 2 CM_RGAM_LUT_INDEX 0 8 mmCM3_CM_RGAM_LUT_DATA 0 0x1040 1 0 2 CM_RGAM_LUT_DATA 0 18 mmCM3_CM_RGAM_LUT_WRITE_EN_MASK 0 0x1041 3 0 2 CM_RGAM_LUT_WRITE_EN_MASK 0 2 CM_RGAM_LUT_WRITE_SEL 4 4 CM_RGAM_CONFIG_STATUS 8 10 mmCM3_CM_RGAM_RAMA_START_CNTL_B 0 0x1042 2 0 2 CM_RGAM_RAMA_EXP_REGION_START_B 0 17 CM_RGAM_RAMA_EXP_REGION_START_SEGMENT_B 20 26 mmCM3_CM_RGAM_RAMA_START_CNTL_G 0 0x1043 2 0 2 CM_RGAM_RAMA_EXP_REGION_START_G 0 17 CM_RGAM_RAMA_EXP_REGION_START_SEGMENT_G 20 26 mmCM3_CM_RGAM_RAMA_START_CNTL_R 0 0x1044 2 0 2 CM_RGAM_RAMA_EXP_REGION_START_R 0 17 CM_RGAM_RAMA_EXP_REGION_START_SEGMENT_R 20 26 mmCM3_CM_RGAM_RAMA_SLOPE_CNTL_B 0 0x1045 1 0 2 CM_RGAM_RAMA_EXP_REGION_LINEAR_SLOPE_B 0 17 mmCM3_CM_RGAM_RAMA_SLOPE_CNTL_G 0 0x1046 1 0 2 CM_RGAM_RAMA_EXP_REGION_LINEAR_SLOPE_G 0 17 mmCM3_CM_RGAM_RAMA_SLOPE_CNTL_R 0 0x1047 1 0 2 CM_RGAM_RAMA_EXP_REGION_LINEAR_SLOPE_R 0 17 mmCM3_CM_RGAM_RAMA_END_CNTL1_B 0 0x1048 1 0 2 CM_RGAM_RAMA_EXP_REGION_END_B 0 15 mmCM3_CM_RGAM_RAMA_END_CNTL2_B 0 0x1049 2 0 2 CM_RGAM_RAMA_EXP_REGION_END_SLOPE_B 0 15 CM_RGAM_RAMA_EXP_REGION_END_BASE_B 16 31 mmCM3_CM_RGAM_RAMA_END_CNTL1_G 0 0x104a 1 0 2 CM_RGAM_RAMA_EXP_REGION_END_G 0 15 mmCM3_CM_RGAM_RAMA_END_CNTL2_G 0 0x104b 2 0 2 CM_RGAM_RAMA_EXP_REGION_END_SLOPE_G 0 15 CM_RGAM_RAMA_EXP_REGION_END_BASE_G 16 31 mmCM3_CM_RGAM_RAMA_END_CNTL1_R 0 0x104c 1 0 2 CM_RGAM_RAMA_EXP_REGION_END_R 0 15 mmCM3_CM_RGAM_RAMA_END_CNTL2_R 0 0x104d 2 0 2 CM_RGAM_RAMA_EXP_REGION_END_SLOPE_R 0 15 CM_RGAM_RAMA_EXP_REGION_END_BASE_R 16 31 mmCM3_CM_RGAM_RAMA_REGION_0_1 0 0x104e 4 0 2 CM_RGAM_RAMA_EXP_REGION0_LUT_OFFSET 0 8 CM_RGAM_RAMA_EXP_REGION0_NUM_SEGMENTS 12 14 CM_RGAM_RAMA_EXP_REGION1_LUT_OFFSET 16 24 CM_RGAM_RAMA_EXP_REGION1_NUM_SEGMENTS 28 30 mmCM3_CM_RGAM_RAMA_REGION_2_3 0 0x104f 4 0 2 CM_RGAM_RAMA_EXP_REGION2_LUT_OFFSET 0 8 CM_RGAM_RAMA_EXP_REGION2_NUM_SEGMENTS 12 14 CM_RGAM_RAMA_EXP_REGION3_LUT_OFFSET 16 24 CM_RGAM_RAMA_EXP_REGION3_NUM_SEGMENTS 28 30 mmCM3_CM_RGAM_RAMA_REGION_4_5 0 0x1050 4 0 2 CM_RGAM_RAMA_EXP_REGION4_LUT_OFFSET 0 8 CM_RGAM_RAMA_EXP_REGION4_NUM_SEGMENTS 12 14 CM_RGAM_RAMA_EXP_REGION5_LUT_OFFSET 16 24 CM_RGAM_RAMA_EXP_REGION5_NUM_SEGMENTS 28 30 mmCM3_CM_RGAM_RAMA_REGION_6_7 0 0x1051 4 0 2 CM_RGAM_RAMA_EXP_REGION6_LUT_OFFSET 0 8 CM_RGAM_RAMA_EXP_REGION6_NUM_SEGMENTS 12 14 CM_RGAM_RAMA_EXP_REGION7_LUT_OFFSET 16 24 CM_RGAM_RAMA_EXP_REGION7_NUM_SEGMENTS 28 30 mmCM3_CM_RGAM_RAMA_REGION_8_9 0 0x1052 4 0 2 CM_RGAM_RAMA_EXP_REGION8_LUT_OFFSET 0 8 CM_RGAM_RAMA_EXP_REGION8_NUM_SEGMENTS 12 14 CM_RGAM_RAMA_EXP_REGION9_LUT_OFFSET 16 24 CM_RGAM_RAMA_EXP_REGION9_NUM_SEGMENTS 28 30 mmCM3_CM_RGAM_RAMA_REGION_10_11 0 0x1053 4 0 2 CM_RGAM_RAMA_EXP_REGION10_LUT_OFFSET 0 8 CM_RGAM_RAMA_EXP_REGION10_NUM_SEGMENTS 12 14 CM_RGAM_RAMA_EXP_REGION11_LUT_OFFSET 16 24 CM_RGAM_RAMA_EXP_REGION11_NUM_SEGMENTS 28 30 mmCM3_CM_RGAM_RAMA_REGION_12_13 0 0x1054 4 0 2 CM_RGAM_RAMA_EXP_REGION12_LUT_OFFSET 0 8 CM_RGAM_RAMA_EXP_REGION12_NUM_SEGMENTS 12 14 CM_RGAM_RAMA_EXP_REGION13_LUT_OFFSET 16 24 CM_RGAM_RAMA_EXP_REGION13_NUM_SEGMENTS 28 30 mmCM3_CM_RGAM_RAMA_REGION_14_15 0 0x1055 4 0 2 CM_RGAM_RAMA_EXP_REGION14_LUT_OFFSET 0 8 CM_RGAM_RAMA_EXP_REGION14_NUM_SEGMENTS 12 14 CM_RGAM_RAMA_EXP_REGION15_LUT_OFFSET 16 24 CM_RGAM_RAMA_EXP_REGION15_NUM_SEGMENTS 28 30 mmCM3_CM_RGAM_RAMA_REGION_16_17 0 0x1056 4 0 2 CM_RGAM_RAMA_EXP_REGION16_LUT_OFFSET 0 8 CM_RGAM_RAMA_EXP_REGION16_NUM_SEGMENTS 12 14 CM_RGAM_RAMA_EXP_REGION17_LUT_OFFSET 16 24 CM_RGAM_RAMA_EXP_REGION17_NUM_SEGMENTS 28 30 mmCM3_CM_RGAM_RAMA_REGION_18_19 0 0x1057 4 0 2 CM_RGAM_RAMA_EXP_REGION18_LUT_OFFSET 0 8 CM_RGAM_RAMA_EXP_REGION18_NUM_SEGMENTS 12 14 CM_RGAM_RAMA_EXP_REGION19_LUT_OFFSET 16 24 CM_RGAM_RAMA_EXP_REGION19_NUM_SEGMENTS 28 30 mmCM3_CM_RGAM_RAMA_REGION_20_21 0 0x1058 4 0 2 CM_RGAM_RAMA_EXP_REGION20_LUT_OFFSET 0 8 CM_RGAM_RAMA_EXP_REGION20_NUM_SEGMENTS 12 14 CM_RGAM_RAMA_EXP_REGION21_LUT_OFFSET 16 24 CM_RGAM_RAMA_EXP_REGION21_NUM_SEGMENTS 28 30 mmCM3_CM_RGAM_RAMA_REGION_22_23 0 0x1059 4 0 2 CM_RGAM_RAMA_EXP_REGION22_LUT_OFFSET 0 8 CM_RGAM_RAMA_EXP_REGION22_NUM_SEGMENTS 12 14 CM_RGAM_RAMA_EXP_REGION23_LUT_OFFSET 16 24 CM_RGAM_RAMA_EXP_REGION23_NUM_SEGMENTS 28 30 mmCM3_CM_RGAM_RAMA_REGION_24_25 0 0x105a 4 0 2 CM_RGAM_RAMA_EXP_REGION24_LUT_OFFSET 0 8 CM_RGAM_RAMA_EXP_REGION24_NUM_SEGMENTS 12 14 CM_RGAM_RAMA_EXP_REGION25_LUT_OFFSET 16 24 CM_RGAM_RAMA_EXP_REGION25_NUM_SEGMENTS 28 30 mmCM3_CM_RGAM_RAMA_REGION_26_27 0 0x105b 4 0 2 CM_RGAM_RAMA_EXP_REGION26_LUT_OFFSET 0 8 CM_RGAM_RAMA_EXP_REGION26_NUM_SEGMENTS 12 14 CM_RGAM_RAMA_EXP_REGION27_LUT_OFFSET 16 24 CM_RGAM_RAMA_EXP_REGION27_NUM_SEGMENTS 28 30 mmCM3_CM_RGAM_RAMA_REGION_28_29 0 0x105c 4 0 2 CM_RGAM_RAMA_EXP_REGION28_LUT_OFFSET 0 8 CM_RGAM_RAMA_EXP_REGION28_NUM_SEGMENTS 12 14 CM_RGAM_RAMA_EXP_REGION29_LUT_OFFSET 16 24 CM_RGAM_RAMA_EXP_REGION29_NUM_SEGMENTS 28 30 mmCM3_CM_RGAM_RAMA_REGION_30_31 0 0x105d 4 0 2 CM_RGAM_RAMA_EXP_REGION30_LUT_OFFSET 0 8 CM_RGAM_RAMA_EXP_REGION30_NUM_SEGMENTS 12 14 CM_RGAM_RAMA_EXP_REGION31_LUT_OFFSET 16 24 CM_RGAM_RAMA_EXP_REGION31_NUM_SEGMENTS 28 30 mmCM3_CM_RGAM_RAMA_REGION_32_33 0 0x105e 4 0 2 CM_RGAM_RAMA_EXP_REGION32_LUT_OFFSET 0 8 CM_RGAM_RAMA_EXP_REGION32_NUM_SEGMENTS 12 14 CM_RGAM_RAMA_EXP_REGION33_LUT_OFFSET 16 24 CM_RGAM_RAMA_EXP_REGION33_NUM_SEGMENTS 28 30 mmCM3_CM_RGAM_RAMB_START_CNTL_B 0 0x105f 2 0 2 CM_RGAM_RAMB_EXP_REGION_START_B 0 17 CM_RGAM_RAMB_EXP_REGION_START_SEGMENT_B 20 26 mmCM3_CM_RGAM_RAMB_START_CNTL_G 0 0x1060 2 0 2 CM_RGAM_RAMB_EXP_REGION_START_G 0 17 CM_RGAM_RAMB_EXP_REGION_START_SEGMENT_G 20 26 mmCM3_CM_RGAM_RAMB_START_CNTL_R 0 0x1061 2 0 2 CM_RGAM_RAMB_EXP_REGION_START_R 0 17 CM_RGAM_RAMB_EXP_REGION_START_SEGMENT_R 20 26 mmCM3_CM_RGAM_RAMB_SLOPE_CNTL_B 0 0x1062 1 0 2 CM_RGAM_RAMB_EXP_REGION_LINEAR_SLOPE_B 0 17 mmCM3_CM_RGAM_RAMB_SLOPE_CNTL_G 0 0x1063 1 0 2 CM_RGAM_RAMB_EXP_REGION_LINEAR_SLOPE_G 0 17 mmCM3_CM_RGAM_RAMB_SLOPE_CNTL_R 0 0x1064 1 0 2 CM_RGAM_RAMB_EXP_REGION_LINEAR_SLOPE_R 0 17 mmCM3_CM_RGAM_RAMB_END_CNTL1_B 0 0x1065 1 0 2 CM_RGAM_RAMB_EXP_REGION_END_B 0 15 mmCM3_CM_RGAM_RAMB_END_CNTL2_B 0 0x1066 2 0 2 CM_RGAM_RAMB_EXP_REGION_END_SLOPE_B 0 15 CM_RGAM_RAMB_EXP_REGION_END_BASE_B 16 31 mmCM3_CM_RGAM_RAMB_END_CNTL1_G 0 0x1067 1 0 2 CM_RGAM_RAMB_EXP_REGION_END_G 0 15 mmCM3_CM_RGAM_RAMB_END_CNTL2_G 0 0x1068 2 0 2 CM_RGAM_RAMB_EXP_REGION_END_SLOPE_G 0 15 CM_RGAM_RAMB_EXP_REGION_END_BASE_G 16 31 mmCM3_CM_RGAM_RAMB_END_CNTL1_R 0 0x1069 1 0 2 CM_RGAM_RAMB_EXP_REGION_END_R 0 15 mmCM3_CM_RGAM_RAMB_END_CNTL2_R 0 0x106a 2 0 2 CM_RGAM_RAMB_EXP_REGION_END_SLOPE_R 0 15 CM_RGAM_RAMB_EXP_REGION_END_BASE_R 16 31 mmCM3_CM_RGAM_RAMB_REGION_0_1 0 0x106b 4 0 2 CM_RGAM_RAMB_EXP_REGION0_LUT_OFFSET 0 8 CM_RGAM_RAMB_EXP_REGION0_NUM_SEGMENTS 12 14 CM_RGAM_RAMB_EXP_REGION1_LUT_OFFSET 16 24 CM_RGAM_RAMB_EXP_REGION1_NUM_SEGMENTS 28 30 mmCM3_CM_RGAM_RAMB_REGION_2_3 0 0x106c 4 0 2 CM_RGAM_RAMB_EXP_REGION2_LUT_OFFSET 0 8 CM_RGAM_RAMB_EXP_REGION2_NUM_SEGMENTS 12 14 CM_RGAM_RAMB_EXP_REGION3_LUT_OFFSET 16 24 CM_RGAM_RAMB_EXP_REGION3_NUM_SEGMENTS 28 30 mmCM3_CM_RGAM_RAMB_REGION_4_5 0 0x106d 4 0 2 CM_RGAM_RAMB_EXP_REGION4_LUT_OFFSET 0 8 CM_RGAM_RAMB_EXP_REGION4_NUM_SEGMENTS 12 14 CM_RGAM_RAMB_EXP_REGION5_LUT_OFFSET 16 24 CM_RGAM_RAMB_EXP_REGION5_NUM_SEGMENTS 28 30 mmCM3_CM_RGAM_RAMB_REGION_6_7 0 0x106e 4 0 2 CM_RGAM_RAMB_EXP_REGION6_LUT_OFFSET 0 8 CM_RGAM_RAMB_EXP_REGION6_NUM_SEGMENTS 12 14 CM_RGAM_RAMB_EXP_REGION7_LUT_OFFSET 16 24 CM_RGAM_RAMB_EXP_REGION7_NUM_SEGMENTS 28 30 mmCM3_CM_RGAM_RAMB_REGION_8_9 0 0x106f 4 0 2 CM_RGAM_RAMB_EXP_REGION8_LUT_OFFSET 0 8 CM_RGAM_RAMB_EXP_REGION8_NUM_SEGMENTS 12 14 CM_RGAM_RAMB_EXP_REGION9_LUT_OFFSET 16 24 CM_RGAM_RAMB_EXP_REGION9_NUM_SEGMENTS 28 30 mmCM3_CM_RGAM_RAMB_REGION_10_11 0 0x1070 4 0 2 CM_RGAM_RAMB_EXP_REGION10_LUT_OFFSET 0 8 CM_RGAM_RAMB_EXP_REGION10_NUM_SEGMENTS 12 14 CM_RGAM_RAMB_EXP_REGION11_LUT_OFFSET 16 24 CM_RGAM_RAMB_EXP_REGION11_NUM_SEGMENTS 28 30 mmCM3_CM_RGAM_RAMB_REGION_12_13 0 0x1071 4 0 2 CM_RGAM_RAMB_EXP_REGION12_LUT_OFFSET 0 8 CM_RGAM_RAMB_EXP_REGION12_NUM_SEGMENTS 12 14 CM_RGAM_RAMB_EXP_REGION13_LUT_OFFSET 16 24 CM_RGAM_RAMB_EXP_REGION13_NUM_SEGMENTS 28 30 mmCM3_CM_RGAM_RAMB_REGION_14_15 0 0x1072 4 0 2 CM_RGAM_RAMB_EXP_REGION14_LUT_OFFSET 0 8 CM_RGAM_RAMB_EXP_REGION14_NUM_SEGMENTS 12 14 CM_RGAM_RAMB_EXP_REGION15_LUT_OFFSET 16 24 CM_RGAM_RAMB_EXP_REGION15_NUM_SEGMENTS 28 30 mmCM3_CM_RGAM_RAMB_REGION_16_17 0 0x1073 4 0 2 CM_RGAM_RAMB_EXP_REGION16_LUT_OFFSET 0 8 CM_RGAM_RAMB_EXP_REGION16_NUM_SEGMENTS 12 14 CM_RGAM_RAMB_EXP_REGION17_LUT_OFFSET 16 24 CM_RGAM_RAMB_EXP_REGION17_NUM_SEGMENTS 28 30 mmCM3_CM_RGAM_RAMB_REGION_18_19 0 0x1074 4 0 2 CM_RGAM_RAMB_EXP_REGION18_LUT_OFFSET 0 8 CM_RGAM_RAMB_EXP_REGION18_NUM_SEGMENTS 12 14 CM_RGAM_RAMB_EXP_REGION19_LUT_OFFSET 16 24 CM_RGAM_RAMB_EXP_REGION19_NUM_SEGMENTS 28 30 mmCM3_CM_RGAM_RAMB_REGION_20_21 0 0x1075 4 0 2 CM_RGAM_RAMB_EXP_REGION20_LUT_OFFSET 0 8 CM_RGAM_RAMB_EXP_REGION20_NUM_SEGMENTS 12 14 CM_RGAM_RAMB_EXP_REGION21_LUT_OFFSET 16 24 CM_RGAM_RAMB_EXP_REGION21_NUM_SEGMENTS 28 30 mmCM3_CM_RGAM_RAMB_REGION_22_23 0 0x1076 4 0 2 CM_RGAM_RAMB_EXP_REGION22_LUT_OFFSET 0 8 CM_RGAM_RAMB_EXP_REGION22_NUM_SEGMENTS 12 14 CM_RGAM_RAMB_EXP_REGION23_LUT_OFFSET 16 24 CM_RGAM_RAMB_EXP_REGION23_NUM_SEGMENTS 28 30 mmCM3_CM_RGAM_RAMB_REGION_24_25 0 0x1077 4 0 2 CM_RGAM_RAMB_EXP_REGION24_LUT_OFFSET 0 8 CM_RGAM_RAMB_EXP_REGION24_NUM_SEGMENTS 12 14 CM_RGAM_RAMB_EXP_REGION25_LUT_OFFSET 16 24 CM_RGAM_RAMB_EXP_REGION25_NUM_SEGMENTS 28 30 mmCM3_CM_RGAM_RAMB_REGION_26_27 0 0x1078 4 0 2 CM_RGAM_RAMB_EXP_REGION26_LUT_OFFSET 0 8 CM_RGAM_RAMB_EXP_REGION26_NUM_SEGMENTS 12 14 CM_RGAM_RAMB_EXP_REGION27_LUT_OFFSET 16 24 CM_RGAM_RAMB_EXP_REGION27_NUM_SEGMENTS 28 30 mmCM3_CM_RGAM_RAMB_REGION_28_29 0 0x1079 4 0 2 CM_RGAM_RAMB_EXP_REGION28_LUT_OFFSET 0 8 CM_RGAM_RAMB_EXP_REGION28_NUM_SEGMENTS 12 14 CM_RGAM_RAMB_EXP_REGION29_LUT_OFFSET 16 24 CM_RGAM_RAMB_EXP_REGION29_NUM_SEGMENTS 28 30 mmCM3_CM_RGAM_RAMB_REGION_30_31 0 0x107a 4 0 2 CM_RGAM_RAMB_EXP_REGION30_LUT_OFFSET 0 8 CM_RGAM_RAMB_EXP_REGION30_NUM_SEGMENTS 12 14 CM_RGAM_RAMB_EXP_REGION31_LUT_OFFSET 16 24 CM_RGAM_RAMB_EXP_REGION31_NUM_SEGMENTS 28 30 mmCM3_CM_RGAM_RAMB_REGION_32_33 0 0x107b 4 0 2 CM_RGAM_RAMB_EXP_REGION32_LUT_OFFSET 0 8 CM_RGAM_RAMB_EXP_REGION32_NUM_SEGMENTS 12 14 CM_RGAM_RAMB_EXP_REGION33_LUT_OFFSET 16 24 CM_RGAM_RAMB_EXP_REGION33_NUM_SEGMENTS 28 30 mmCM3_CM_HDR_MULT_COEF 0 0x107c 1 0 2 CM_HDR_MULT_COEF 0 18 mmCM3_CM_RANGE_CLAMP_CONTROL_R 0 0x107d 2 0 2 CM_RANGE_CLAMP_MAX_R 0 15 CM_RANGE_CLAMP_MIN_R 16 31 mmCM3_CM_RANGE_CLAMP_CONTROL_G 0 0x107e 2 0 2 CM_RANGE_CLAMP_MAX_G 0 15 CM_RANGE_CLAMP_MIN_G 16 31 mmCM3_CM_RANGE_CLAMP_CONTROL_B 0 0x107f 2 0 2 CM_RANGE_CLAMP_MAX_B 0 15 CM_RANGE_CLAMP_MIN_B 16 31 mmCM3_CM_DENORM_CONTROL 0 0x1080 2 0 2 CM_DENORM_MODE 0 2 CM_DENORM_ROUND_CLAMP 4 4 mmCM3_CM_CMOUT_CONTROL 0 0x1081 7 0 2 CM_CMOUT_ROUND_TRUNC_MODE 0 3 CM_CMOUT_SPATIAL_DITHER_EN 4 4 CM_CMOUT_SPATIAL_DITHER_MODE 8 9 CM_CMOUT_SPATIAL_DITHER_DEPTH 12 13 CM_CMOUT_FRAME_RANDOM_ENABLE 16 16 CM_CMOUT_RGB_RANDOM_EN 20 20 CM_CMOUT_HIGHPASS_RANDOM_ENABLE 24 24 mmCM3_CM_CMOUT_RANDOM_SEEDS 0 0x1082 3 0 2 CM_CMOUT_RAND_R_SEED 0 7 CM_CMOUT_RAND_G_SEED 8 15 CM_CMOUT_RAND_B_SEED 16 23 mmCM3_CM_MEM_PWR_CTRL 0 0x1083 4 0 2 SHARED_MEM_PWR_FORCE 0 1 SHARED_MEM_PWR_DIS 2 2 RGAM_MEM_PWR_FORCE 4 5 RGAM_MEM_PWR_DIS 6 6 mmCM3_CM_MEM_PWR_STATUS 0 0x1084 2 0 2 SHARED_MEM_PWR_STATE 0 1 RGAM_MEM_PWR_STATE 2 3 mmCM3_CM_TEST_DEBUG_INDEX 0 0x1086 0 0 2 mmCM3_CM_TEST_DEBUG_DATA 0 0x1087 0 0 2 mmDC_PERFMON15_PERFCOUNTER_CNTL 0 0x109d 11 0 2 PERFCOUNTER_EVENT_SEL 0 8 PERFCOUNTER_CVALUE_SEL 9 11 PERFCOUNTER_INC_MODE 12 14 PERFCOUNTER_HW_CNTL_SEL 15 15 PERFCOUNTER_RUNEN_MODE 16 16 PERFCOUNTER_CNTOFF_START_DIS 22 22 PERFCOUNTER_RESTART_EN 23 23 PERFCOUNTER_INT_EN 24 24 PERFCOUNTER_OFF_MASK 25 25 PERFCOUNTER_ACTIVE 26 26 PERFCOUNTER_CNTL_SEL 29 31 mmDC_PERFMON15_PERFCOUNTER_CNTL2 0 0x109e 5 0 2 PERFCOUNTER_COUNTED_VALUE_TYPE 0 1 PERFCOUNTER_HW_STOP1_SEL 2 2 PERFCOUNTER_HW_STOP2_SEL 3 3 PERFCOUNTER_CNTOFF_SEL 8 13 PERFCOUNTER_CNTL2_SEL 29 31 mmDC_PERFMON15_PERFCOUNTER_STATE 0 0x109f 16 0 2 PERFCOUNTER_CNT0_STATE 0 1 PERFCOUNTER_STATE_SEL0 2 2 PERFCOUNTER_CNT1_STATE 4 5 PERFCOUNTER_STATE_SEL1 6 6 PERFCOUNTER_CNT2_STATE 8 9 PERFCOUNTER_STATE_SEL2 10 10 PERFCOUNTER_CNT3_STATE 12 13 PERFCOUNTER_STATE_SEL3 14 14 PERFCOUNTER_CNT4_STATE 16 17 PERFCOUNTER_STATE_SEL4 18 18 PERFCOUNTER_CNT5_STATE 20 21 PERFCOUNTER_STATE_SEL5 22 22 PERFCOUNTER_CNT6_STATE 24 25 PERFCOUNTER_STATE_SEL6 26 26 PERFCOUNTER_CNT7_STATE 28 29 PERFCOUNTER_STATE_SEL7 30 30 mmDC_PERFMON15_PERFMON_CNTL 0 0x10a0 6 0 2 PERFMON_STATE 0 1 PERFMON_RPT_COUNT 8 27 PERFMON_CNTOFF_AND_OR 28 28 PERFMON_CNTOFF_INT_EN 29 29 PERFMON_CNTOFF_INT_STATUS 30 30 PERFMON_CNTOFF_INT_ACK 31 31 mmDC_PERFMON15_PERFMON_CNTL2 0 0x10a1 4 0 2 PERFMON_CNTOFF_INT_TYPE 0 0 PERFMON_CLK_ENABLE 1 1 PERFMON_RUN_ENABLE_START_SEL 2 9 PERFMON_RUN_ENABLE_STOP_SEL 10 17 mmDC_PERFMON15_PERFMON_CVALUE_INT_MISC 0 0x10a2 17 0 2 PERFCOUNTER_INT0_STATUS 0 0 PERFCOUNTER_INT1_STATUS 1 1 PERFCOUNTER_INT2_STATUS 2 2 PERFCOUNTER_INT3_STATUS 3 3 PERFCOUNTER_INT4_STATUS 4 4 PERFCOUNTER_INT5_STATUS 5 5 PERFCOUNTER_INT6_STATUS 6 6 PERFCOUNTER_INT7_STATUS 7 7 PERFCOUNTER_INT0_ACK 8 8 PERFCOUNTER_INT1_ACK 9 9 PERFCOUNTER_INT2_ACK 10 10 PERFCOUNTER_INT3_ACK 11 11 PERFCOUNTER_INT4_ACK 12 12 PERFCOUNTER_INT5_ACK 13 13 PERFCOUNTER_INT6_ACK 14 14 PERFCOUNTER_INT7_ACK 15 15 PERFMON_CVALUE_HI 16 31 mmDC_PERFMON15_PERFMON_CVALUE_LOW 0 0x10a3 1 0 2 PERFMON_CVALUE_LOW 0 31 mmDC_PERFMON15_PERFMON_HI 0 0x10a4 2 0 2 PERFMON_HI 0 15 PERFMON_READ_SEL 29 31 mmDC_PERFMON15_PERFMON_LOW 0 0x10a5 1 0 2 PERFMON_LOW 0 31 mmMPCC0_MPCC_TOP_SEL 0 0x1630 1 0 2 MPCC_TOP_SEL 0 3 mmMPCC0_MPCC_BOT_SEL 0 0x1631 1 0 2 MPCC_BOT_SEL 0 3 mmMPCC0_MPCC_OPP_ID 0 0x1632 1 0 2 MPCC_OPP_ID 0 3 mmMPCC0_MPCC_CONTROL 0 0x1633 6 0 2 MPCC_MODE 0 1 MPCC_ALPHA_BLND_MODE 4 5 MPCC_ALPHA_MULTIPLIED_MODE 6 6 MPCC_BLND_ACTIVE_OVERLAP_ONLY 7 7 MPCC_GLOBAL_ALPHA 16 23 MPCC_GLOBAL_GAIN 24 31 mmMPCC0_MPCC_SM_CONTROL 0 0x1634 7 0 2 MPCC_SM_EN 0 0 MPCC_SM_MODE 1 3 MPCC_SM_FRAME_ALT 4 4 MPCC_SM_FIELD_ALT 5 5 MPCC_SM_FORCE_NEXT_FRAME_POL 8 9 MPCC_SM_FORCE_NEXT_TOP_POL 16 17 MPCC_SM_CURRENT_FRAME_POL 24 24 mmMPCC0_MPCC_UPDATE_LOCK_SEL 0 0x1635 2 0 2 MPCC_UPDATE_LOCK_SEL 0 3 MPCC_UPDATE_LOCKED_STATUS 4 7 mmMPCC0_MPCC_TOP_OFFSET 0 0x1636 2 0 2 MPCC_TOP_OFFSET_L 0 11 MPCC_TOP_OFFSET_C 16 27 mmMPCC0_MPCC_BOT_OFFSET 0 0x1637 2 0 2 MPCC_BOT_OFFSET_L 0 11 MPCC_BOT_OFFSET_C 16 27 mmMPCC0_MPCC_OFFSET 0 0x1638 2 0 2 MPCC_OFFSET_L 0 11 MPCC_OFFSET_C 16 27 mmMPCC0_MPCC_BG_R_CR 0 0x1639 1 0 2 MPCC_BG_R_CR 0 11 mmMPCC0_MPCC_BG_G_Y 0 0x163a 1 0 2 MPCC_BG_G_Y 0 11 mmMPCC0_MPCC_BG_B_CB 0 0x163b 1 0 2 MPCC_BG_B_CB 0 11 mmMPCC0_MPCC_STALL_STATUS 0 0x163c 4 0 2 MPCC_STALL_INT_OCCURED 0 0 MPCC_STALL_INT_ACK 8 8 MPCC_STALL_INT_MASK 12 12 MPCC_STALL_INFO 16 17 mmMPCC0_MPCC_STATUS 0 0x163d 12 0 2 MPCC_IDLE 0 0 MPCC_BUSY 1 1 DPP_MPCC_EOL_MISSED 16 16 DPP_MPCC_MULTI_EOL 17 17 DPP_MPCC_EOF_MISSED 18 18 DPP_MPCC_MULTI_EOF 19 19 DPP_MPCC_LESS_PIXEL 20 20 DPP_MPCC_MORE_PIXEL 21 21 DPP_MPCC_LESS_LINES 22 22 DPP_MPCC_MORE_LINES 23 23 DPP_MPCC_INPUT_CHECK_ENABLE 30 30 DPP_MPCC_EXCEPTION_ACK 31 31 mmMPCC1_MPCC_TOP_SEL 0 0x164b 1 0 2 MPCC_TOP_SEL 0 3 mmMPCC1_MPCC_BOT_SEL 0 0x164c 1 0 2 MPCC_BOT_SEL 0 3 mmMPCC1_MPCC_OPP_ID 0 0x164d 1 0 2 MPCC_OPP_ID 0 3 mmMPCC1_MPCC_CONTROL 0 0x164e 6 0 2 MPCC_MODE 0 1 MPCC_ALPHA_BLND_MODE 4 5 MPCC_ALPHA_MULTIPLIED_MODE 6 6 MPCC_BLND_ACTIVE_OVERLAP_ONLY 7 7 MPCC_GLOBAL_ALPHA 16 23 MPCC_GLOBAL_GAIN 24 31 mmMPCC1_MPCC_SM_CONTROL 0 0x164f 7 0 2 MPCC_SM_EN 0 0 MPCC_SM_MODE 1 3 MPCC_SM_FRAME_ALT 4 4 MPCC_SM_FIELD_ALT 5 5 MPCC_SM_FORCE_NEXT_FRAME_POL 8 9 MPCC_SM_FORCE_NEXT_TOP_POL 16 17 MPCC_SM_CURRENT_FRAME_POL 24 24 mmMPCC1_MPCC_UPDATE_LOCK_SEL 0 0x1650 2 0 2 MPCC_UPDATE_LOCK_SEL 0 3 MPCC_UPDATE_LOCKED_STATUS 4 7 mmMPCC1_MPCC_TOP_OFFSET 0 0x1651 2 0 2 MPCC_TOP_OFFSET_L 0 11 MPCC_TOP_OFFSET_C 16 27 mmMPCC1_MPCC_BOT_OFFSET 0 0x1652 2 0 2 MPCC_BOT_OFFSET_L 0 11 MPCC_BOT_OFFSET_C 16 27 mmMPCC1_MPCC_OFFSET 0 0x1653 2 0 2 MPCC_OFFSET_L 0 11 MPCC_OFFSET_C 16 27 mmMPCC1_MPCC_BG_R_CR 0 0x1654 1 0 2 MPCC_BG_R_CR 0 11 mmMPCC1_MPCC_BG_G_Y 0 0x1655 1 0 2 MPCC_BG_G_Y 0 11 mmMPCC1_MPCC_BG_B_CB 0 0x1656 1 0 2 MPCC_BG_B_CB 0 11 mmMPCC1_MPCC_STALL_STATUS 0 0x1657 4 0 2 MPCC_STALL_INT_OCCURED 0 0 MPCC_STALL_INT_ACK 8 8 MPCC_STALL_INT_MASK 12 12 MPCC_STALL_INFO 16 17 mmMPCC1_MPCC_STATUS 0 0x1658 12 0 2 MPCC_IDLE 0 0 MPCC_BUSY 1 1 DPP_MPCC_EOL_MISSED 16 16 DPP_MPCC_MULTI_EOL 17 17 DPP_MPCC_EOF_MISSED 18 18 DPP_MPCC_MULTI_EOF 19 19 DPP_MPCC_LESS_PIXEL 20 20 DPP_MPCC_MORE_PIXEL 21 21 DPP_MPCC_LESS_LINES 22 22 DPP_MPCC_MORE_LINES 23 23 DPP_MPCC_INPUT_CHECK_ENABLE 30 30 DPP_MPCC_EXCEPTION_ACK 31 31 mmMPCC2_MPCC_TOP_SEL 0 0x1666 1 0 2 MPCC_TOP_SEL 0 3 mmMPCC2_MPCC_BOT_SEL 0 0x1667 1 0 2 MPCC_BOT_SEL 0 3 mmMPCC2_MPCC_OPP_ID 0 0x1668 1 0 2 MPCC_OPP_ID 0 3 mmMPCC2_MPCC_CONTROL 0 0x1669 6 0 2 MPCC_MODE 0 1 MPCC_ALPHA_BLND_MODE 4 5 MPCC_ALPHA_MULTIPLIED_MODE 6 6 MPCC_BLND_ACTIVE_OVERLAP_ONLY 7 7 MPCC_GLOBAL_ALPHA 16 23 MPCC_GLOBAL_GAIN 24 31 mmMPCC2_MPCC_SM_CONTROL 0 0x166a 7 0 2 MPCC_SM_EN 0 0 MPCC_SM_MODE 1 3 MPCC_SM_FRAME_ALT 4 4 MPCC_SM_FIELD_ALT 5 5 MPCC_SM_FORCE_NEXT_FRAME_POL 8 9 MPCC_SM_FORCE_NEXT_TOP_POL 16 17 MPCC_SM_CURRENT_FRAME_POL 24 24 mmMPCC2_MPCC_UPDATE_LOCK_SEL 0 0x166b 2 0 2 MPCC_UPDATE_LOCK_SEL 0 3 MPCC_UPDATE_LOCKED_STATUS 4 7 mmMPCC2_MPCC_TOP_OFFSET 0 0x166c 2 0 2 MPCC_TOP_OFFSET_L 0 11 MPCC_TOP_OFFSET_C 16 27 mmMPCC2_MPCC_BOT_OFFSET 0 0x166d 2 0 2 MPCC_BOT_OFFSET_L 0 11 MPCC_BOT_OFFSET_C 16 27 mmMPCC2_MPCC_OFFSET 0 0x166e 2 0 2 MPCC_OFFSET_L 0 11 MPCC_OFFSET_C 16 27 mmMPCC2_MPCC_BG_R_CR 0 0x166f 1 0 2 MPCC_BG_R_CR 0 11 mmMPCC2_MPCC_BG_G_Y 0 0x1670 1 0 2 MPCC_BG_G_Y 0 11 mmMPCC2_MPCC_BG_B_CB 0 0x1671 1 0 2 MPCC_BG_B_CB 0 11 mmMPCC2_MPCC_STALL_STATUS 0 0x1672 4 0 2 MPCC_STALL_INT_OCCURED 0 0 MPCC_STALL_INT_ACK 8 8 MPCC_STALL_INT_MASK 12 12 MPCC_STALL_INFO 16 17 mmMPCC2_MPCC_STATUS 0 0x1673 12 0 2 MPCC_IDLE 0 0 MPCC_BUSY 1 1 DPP_MPCC_EOL_MISSED 16 16 DPP_MPCC_MULTI_EOL 17 17 DPP_MPCC_EOF_MISSED 18 18 DPP_MPCC_MULTI_EOF 19 19 DPP_MPCC_LESS_PIXEL 20 20 DPP_MPCC_MORE_PIXEL 21 21 DPP_MPCC_LESS_LINES 22 22 DPP_MPCC_MORE_LINES 23 23 DPP_MPCC_INPUT_CHECK_ENABLE 30 30 DPP_MPCC_EXCEPTION_ACK 31 31 mmMPCC3_MPCC_TOP_SEL 0 0x1681 1 0 2 MPCC_TOP_SEL 0 3 mmMPCC3_MPCC_BOT_SEL 0 0x1682 1 0 2 MPCC_BOT_SEL 0 3 mmMPCC3_MPCC_OPP_ID 0 0x1683 1 0 2 MPCC_OPP_ID 0 3 mmMPCC3_MPCC_CONTROL 0 0x1684 6 0 2 MPCC_MODE 0 1 MPCC_ALPHA_BLND_MODE 4 5 MPCC_ALPHA_MULTIPLIED_MODE 6 6 MPCC_BLND_ACTIVE_OVERLAP_ONLY 7 7 MPCC_GLOBAL_ALPHA 16 23 MPCC_GLOBAL_GAIN 24 31 mmMPCC3_MPCC_SM_CONTROL 0 0x1685 7 0 2 MPCC_SM_EN 0 0 MPCC_SM_MODE 1 3 MPCC_SM_FRAME_ALT 4 4 MPCC_SM_FIELD_ALT 5 5 MPCC_SM_FORCE_NEXT_FRAME_POL 8 9 MPCC_SM_FORCE_NEXT_TOP_POL 16 17 MPCC_SM_CURRENT_FRAME_POL 24 24 mmMPCC3_MPCC_UPDATE_LOCK_SEL 0 0x1686 2 0 2 MPCC_UPDATE_LOCK_SEL 0 3 MPCC_UPDATE_LOCKED_STATUS 4 7 mmMPCC3_MPCC_TOP_OFFSET 0 0x1687 2 0 2 MPCC_TOP_OFFSET_L 0 11 MPCC_TOP_OFFSET_C 16 27 mmMPCC3_MPCC_BOT_OFFSET 0 0x1688 2 0 2 MPCC_BOT_OFFSET_L 0 11 MPCC_BOT_OFFSET_C 16 27 mmMPCC3_MPCC_OFFSET 0 0x1689 2 0 2 MPCC_OFFSET_L 0 11 MPCC_OFFSET_C 16 27 mmMPCC3_MPCC_BG_R_CR 0 0x168a 1 0 2 MPCC_BG_R_CR 0 11 mmMPCC3_MPCC_BG_G_Y 0 0x168b 1 0 2 MPCC_BG_G_Y 0 11 mmMPCC3_MPCC_BG_B_CB 0 0x168c 1 0 2 MPCC_BG_B_CB 0 11 mmMPCC3_MPCC_STALL_STATUS 0 0x168d 4 0 2 MPCC_STALL_INT_OCCURED 0 0 MPCC_STALL_INT_ACK 8 8 MPCC_STALL_INT_MASK 12 12 MPCC_STALL_INFO 16 17 mmMPCC3_MPCC_STATUS 0 0x168e 12 0 2 MPCC_IDLE 0 0 MPCC_BUSY 1 1 DPP_MPCC_EOL_MISSED 16 16 DPP_MPCC_MULTI_EOL 17 17 DPP_MPCC_EOF_MISSED 18 18 DPP_MPCC_MULTI_EOF 19 19 DPP_MPCC_LESS_PIXEL 20 20 DPP_MPCC_MORE_PIXEL 21 21 DPP_MPCC_LESS_LINES 22 22 DPP_MPCC_MORE_LINES 23 23 DPP_MPCC_INPUT_CHECK_ENABLE 30 30 DPP_MPCC_EXCEPTION_ACK 31 31 mmMPC_CLOCK_CONTROL 0 0x1723 2 0 2 DISPCLK_R_GATE_DISABLE 1 1 MPC_TEST_CLK_SEL 4 5 mmMPC_SOFT_RESET 0 0x1724 13 0 2 MPCC0_SOFT_RESET 0 0 MPCC1_SOFT_RESET 1 1 MPCC2_SOFT_RESET 2 2 MPCC3_SOFT_RESET 3 3 MPC_SFR0_SOFT_RESET 10 10 MPC_SFR1_SOFT_RESET 11 11 MPC_SFR2_SOFT_RESET 12 12 MPC_SFR3_SOFT_RESET 13 13 MPC_SFT0_SOFT_RESET 20 20 MPC_SFT1_SOFT_RESET 21 21 MPC_SFT2_SOFT_RESET 22 22 MPC_SFT3_SOFT_RESET 23 23 MPC_SOFT_RESET 31 31 mmMPC_CRC_CTRL 0 0x1725 8 0 2 MPC_CRC_EN 0 0 MPC_CRC_CONT_EN 4 4 MPC_CRC_STEREO_MODE 8 9 MPC_CRC_STEREO_EN 10 10 MPC_CRC_INTERLACE_MODE 12 13 MPC_CRC_SRC_SEL 24 25 MPC_CRC_ONE_SHOT_PENDING 28 28 MPC_CRC_UPDATE_LOCK 31 31 mmMPC_CRC_SEL_CONTROL 0 0x1726 3 0 2 MPC_CRC_DPP_SEL 0 3 MPC_CRC_OPP_SEL 4 7 MPC_CRC_MASK 16 31 mmMPC_CRC_RESULT_AR 0 0x1727 2 0 2 MPC_CRC_RESULT_A 0 15 MPC_CRC_RESULT_R 16 31 mmMPC_CRC_RESULT_GB 0 0x1728 2 0 2 MPC_CRC_RESULT_G 0 15 MPC_CRC_RESULT_B 16 31 mmMPC_CRC_RESULT_C 0 0x1729 1 0 2 MPC_CRC_RESULT_C 0 15 mmMPC_PERFMON_EVENT_CTRL 0 0x172c 1 0 2 MPC_PERFMON_EVENT_EN 0 0 mmMPC_BYPASS_BG_AR 0 0x172d 2 0 2 MPC_BYPASS_BG_ALPHA 0 15 MPC_BYPASS_BG_R_CR 16 31 mmMPC_BYPASS_BG_GB 0 0x172e 2 0 2 MPC_BYPASS_BG_G_Y 0 15 MPC_BYPASS_BG_B_CB 16 31 mmMPC_OUT0_MUX 0 0x172f 1 0 2 MPC_OUT_MUX 0 3 mmMPC_OUT1_MUX 0 0x1730 1 0 2 MPC_OUT_MUX 0 3 mmMPC_OUT2_MUX 0 0x1731 1 0 2 MPC_OUT_MUX 0 3 mmMPC_OUT3_MUX 0 0x1732 1 0 2 MPC_OUT_MUX 0 3 mmMPC_STALL_GRACE_WINDOW 0 0x1756 1 0 2 MPC_STALL_GRACE_WINDOW_PERIOD 0 7 mmADR_CFG_VUPDATE_LOCK_SET0 0 0x175b 2 0 2 ADR_CFG_VUPDATE_LOCK_SET 0 0 CFG_VUPDATE_LOCK_SET 4 4 mmADR_VUPDATE_LOCK_SET0 0 0x175c 1 0 2 ADR_VUPDATE_LOCK_SET 0 0 mmCUR0_VUPDATE_LOCK_SET0 0 0x175d 1 0 2 CUR0_VUPDATE_LOCK_SET 0 0 mmCUR1_VUPDATE_LOCK_SET0 0 0x175e 1 0 2 CUR1_VUPDATE_LOCK_SET 0 0 mmADR_CFG_VUPDATE_LOCK_SET1 0 0x175f 2 0 2 ADR_CFG_VUPDATE_LOCK_SET 0 0 CFG_VUPDATE_LOCK_SET 4 4 mmADR_VUPDATE_LOCK_SET1 0 0x1760 1 0 2 ADR_VUPDATE_LOCK_SET 0 0 mmCUR0_VUPDATE_LOCK_SET1 0 0x1761 1 0 2 CUR0_VUPDATE_LOCK_SET 0 0 mmCUR1_VUPDATE_LOCK_SET1 0 0x1762 1 0 2 CUR1_VUPDATE_LOCK_SET 0 0 mmADR_CFG_VUPDATE_LOCK_SET2 0 0x1763 2 0 2 ADR_CFG_VUPDATE_LOCK_SET 0 0 CFG_VUPDATE_LOCK_SET 4 4 mmADR_VUPDATE_LOCK_SET2 0 0x1764 1 0 2 ADR_VUPDATE_LOCK_SET 0 0 mmCUR0_VUPDATE_LOCK_SET2 0 0x1765 1 0 2 CUR0_VUPDATE_LOCK_SET 0 0 mmCUR1_VUPDATE_LOCK_SET2 0 0x1766 1 0 2 CUR1_VUPDATE_LOCK_SET 0 0 mmADR_CFG_VUPDATE_LOCK_SET3 0 0x1767 2 0 2 ADR_CFG_VUPDATE_LOCK_SET 0 0 CFG_VUPDATE_LOCK_SET 4 4 mmADR_VUPDATE_LOCK_SET3 0 0x1768 1 0 2 ADR_VUPDATE_LOCK_SET 0 0 mmCUR0_VUPDATE_LOCK_SET3 0 0x1769 1 0 2 CUR0_VUPDATE_LOCK_SET 0 0 mmCUR1_VUPDATE_LOCK_SET3 0 0x176a 1 0 2 CUR1_VUPDATE_LOCK_SET 0 0 mmDC_PERFMON16_PERFCOUNTER_CNTL 0 0x17a4 11 0 2 PERFCOUNTER_EVENT_SEL 0 8 PERFCOUNTER_CVALUE_SEL 9 11 PERFCOUNTER_INC_MODE 12 14 PERFCOUNTER_HW_CNTL_SEL 15 15 PERFCOUNTER_RUNEN_MODE 16 16 PERFCOUNTER_CNTOFF_START_DIS 22 22 PERFCOUNTER_RESTART_EN 23 23 PERFCOUNTER_INT_EN 24 24 PERFCOUNTER_OFF_MASK 25 25 PERFCOUNTER_ACTIVE 26 26 PERFCOUNTER_CNTL_SEL 29 31 mmDC_PERFMON16_PERFCOUNTER_CNTL2 0 0x17a5 5 0 2 PERFCOUNTER_COUNTED_VALUE_TYPE 0 1 PERFCOUNTER_HW_STOP1_SEL 2 2 PERFCOUNTER_HW_STOP2_SEL 3 3 PERFCOUNTER_CNTOFF_SEL 8 13 PERFCOUNTER_CNTL2_SEL 29 31 mmDC_PERFMON16_PERFCOUNTER_STATE 0 0x17a6 16 0 2 PERFCOUNTER_CNT0_STATE 0 1 PERFCOUNTER_STATE_SEL0 2 2 PERFCOUNTER_CNT1_STATE 4 5 PERFCOUNTER_STATE_SEL1 6 6 PERFCOUNTER_CNT2_STATE 8 9 PERFCOUNTER_STATE_SEL2 10 10 PERFCOUNTER_CNT3_STATE 12 13 PERFCOUNTER_STATE_SEL3 14 14 PERFCOUNTER_CNT4_STATE 16 17 PERFCOUNTER_STATE_SEL4 18 18 PERFCOUNTER_CNT5_STATE 20 21 PERFCOUNTER_STATE_SEL5 22 22 PERFCOUNTER_CNT6_STATE 24 25 PERFCOUNTER_STATE_SEL6 26 26 PERFCOUNTER_CNT7_STATE 28 29 PERFCOUNTER_STATE_SEL7 30 30 mmDC_PERFMON16_PERFMON_CNTL 0 0x17a7 6 0 2 PERFMON_STATE 0 1 PERFMON_RPT_COUNT 8 27 PERFMON_CNTOFF_AND_OR 28 28 PERFMON_CNTOFF_INT_EN 29 29 PERFMON_CNTOFF_INT_STATUS 30 30 PERFMON_CNTOFF_INT_ACK 31 31 mmDC_PERFMON16_PERFMON_CNTL2 0 0x17a8 4 0 2 PERFMON_CNTOFF_INT_TYPE 0 0 PERFMON_CLK_ENABLE 1 1 PERFMON_RUN_ENABLE_START_SEL 2 9 PERFMON_RUN_ENABLE_STOP_SEL 10 17 mmDC_PERFMON16_PERFMON_CVALUE_INT_MISC 0 0x17a9 17 0 2 PERFCOUNTER_INT0_STATUS 0 0 PERFCOUNTER_INT1_STATUS 1 1 PERFCOUNTER_INT2_STATUS 2 2 PERFCOUNTER_INT3_STATUS 3 3 PERFCOUNTER_INT4_STATUS 4 4 PERFCOUNTER_INT5_STATUS 5 5 PERFCOUNTER_INT6_STATUS 6 6 PERFCOUNTER_INT7_STATUS 7 7 PERFCOUNTER_INT0_ACK 8 8 PERFCOUNTER_INT1_ACK 9 9 PERFCOUNTER_INT2_ACK 10 10 PERFCOUNTER_INT3_ACK 11 11 PERFCOUNTER_INT4_ACK 12 12 PERFCOUNTER_INT5_ACK 13 13 PERFCOUNTER_INT6_ACK 14 14 PERFCOUNTER_INT7_ACK 15 15 PERFMON_CVALUE_HI 16 31 mmDC_PERFMON16_PERFMON_CVALUE_LOW 0 0x17aa 1 0 2 PERFMON_CVALUE_LOW 0 31 mmDC_PERFMON16_PERFMON_HI 0 0x17ab 2 0 2 PERFMON_HI 0 15 PERFMON_READ_SEL 29 31 mmDC_PERFMON16_PERFMON_LOW 0 0x17ac 1 0 2 PERFMON_LOW 0 31 mmABM0_BL1_PWM_AMBIENT_LIGHT_LEVEL 0 0x17b0 1 0 2 BL1_PWM_AMBIENT_LIGHT_LEVEL 0 16 mmABM0_BL1_PWM_USER_LEVEL 0 0x17b1 1 0 2 BL1_PWM_USER_LEVEL 0 16 mmABM0_BL1_PWM_TARGET_ABM_LEVEL 0 0x17b2 1 0 2 BL1_PWM_TARGET_ABM_LEVEL 0 16 mmABM0_BL1_PWM_CURRENT_ABM_LEVEL 0 0x17b3 1 0 2 BL1_PWM_CURRENT_ABM_LEVEL 0 16 mmABM0_BL1_PWM_FINAL_DUTY_CYCLE 0 0x17b4 1 0 2 BL1_PWM_FINAL_DUTY_CYCLE 0 16 mmABM0_BL1_PWM_MINIMUM_DUTY_CYCLE 0 0x17b5 1 0 2 BL1_PWM_MINIMUM_DUTY_CYCLE 0 16 mmABM0_BL1_PWM_ABM_CNTL 0 0x17b6 5 0 2 BL1_PWM_USE_ABM_EN 0 0 BL1_PWM_USE_AMBIENT_LEVEL_EN 1 1 BL1_PWM_AUTO_UPDATE_CURRENT_ABM_LEVEL_EN 2 2 BL1_PWM_AUTO_CALC_FINAL_DUTY_CYCLE_EN 3 3 BL1_PWM_AUTO_UPDATE_CURRENT_ABM_STEP_SIZE 16 31 mmABM0_BL1_PWM_BL_UPDATE_SAMPLE_RATE 0 0x17b7 5 0 2 BL1_PWM_BL_UPDATE_SAMPLE_RATE_COUNT_EN 0 0 BL1_PWM_BL_UPDATE_RESET_SAMPLE_RATE_FRAME_COUNTER 1 1 BL1_PWM_BL_UPDATE_SAMPLE_RATE_FRAME_COUNT 8 15 BL1_PWM_BL_UPDATE_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET 16 23 ABM1_HGLS_REG_LOCK 31 31 mmABM0_BL1_PWM_GRP2_REG_LOCK 0 0x17b8 6 0 2 BL1_PWM_GRP2_REG_LOCK 0 0 BL1_PWM_GRP2_REG_UPDATE_PENDING 8 8 BL1_PWM_GRP2_UPDATE_AT_FRAME_START 16 16 BL1_PWM_GRP2_FRAME_START_DISP_SEL 17 19 BL1_PWM_GRP2_READBACK_DB_REG_VALUE_EN 24 24 BL1_PWM_GRP2_IGNORE_MASTER_LOCK_EN 31 31 mmABM0_DC_ABM1_CNTL 0 0x17b9 2 0 2 ABM1_EN 0 0 ABM1_SOURCE_SELECT 8 10 mmABM0_DC_ABM1_IPCSC_COEFF_SEL 0 0x17ba 4 0 2 ABM1_IPCSC_COEFF_SEL_B 0 3 ABM1_IPCSC_COEFF_SEL_G 8 11 ABM1_IPCSC_COEFF_SEL_R 16 19 ABM1_HGLS_REG_LOCK 31 31 mmABM0_DC_ABM1_ACE_OFFSET_SLOPE_0 0 0x17bb 3 0 2 ABM1_ACE_SLOPE_0 0 14 ABM1_ACE_OFFSET_0 16 26 ABM1_ACE_LOCK 31 31 mmABM0_DC_ABM1_ACE_OFFSET_SLOPE_1 0 0x17bc 3 0 2 ABM1_ACE_SLOPE_1 0 14 ABM1_ACE_OFFSET_1 16 26 ABM1_ACE_LOCK 31 31 mmABM0_DC_ABM1_ACE_OFFSET_SLOPE_2 0 0x17bd 3 0 2 ABM1_ACE_SLOPE_2 0 14 ABM1_ACE_OFFSET_2 16 26 ABM1_ACE_LOCK 31 31 mmABM0_DC_ABM1_ACE_OFFSET_SLOPE_3 0 0x17be 3 0 2 ABM1_ACE_SLOPE_3 0 14 ABM1_ACE_OFFSET_3 16 26 ABM1_ACE_LOCK 31 31 mmABM0_DC_ABM1_ACE_OFFSET_SLOPE_4 0 0x17bf 3 0 2 ABM1_ACE_SLOPE_4 0 14 ABM1_ACE_OFFSET_4 16 26 ABM1_ACE_LOCK 31 31 mmABM0_DC_ABM1_ACE_THRES_12 0 0x17c0 3 0 2 ABM1_ACE_THRES_1 0 9 ABM1_ACE_THRES_2 16 25 ABM1_ACE_LOCK 31 31 mmABM0_DC_ABM1_ACE_THRES_34 0 0x17c1 6 0 2 ABM1_ACE_THRES_3 0 9 ABM1_ACE_THRES_4 16 25 ABM1_ACE_IGNORE_MASTER_LOCK_EN 28 28 ABM1_ACE_READBACK_DB_REG_VALUE_EN 29 29 ABM1_ACE_DBUF_REG_UPDATE_PENDING 30 30 ABM1_ACE_LOCK 31 31 mmABM0_DC_ABM1_ACE_CNTL_MISC 0 0x17c2 2 0 2 ABM1_ACE_REG_WR_MISSED_FRAME 0 0 ABM1_ACE_REG_WR_MISSED_FRAME_CLEAR 8 8 mmABM0_DC_ABM1_HGLS_REG_READ_PROGRESS 0 0x17c4 9 0 2 ABM1_HG_REG_READ_IN_PROGRESS 0 0 ABM1_LS_REG_READ_IN_PROGRESS 1 1 ABM1_BL_REG_READ_IN_PROGRESS 2 2 ABM1_HG_REG_READ_MISSED_FRAME 8 8 ABM1_LS_REG_READ_MISSED_FRAME 9 9 ABM1_BL_REG_READ_MISSED_FRAME 10 10 ABM1_HG_REG_READ_MISSED_FRAME_CLEAR 16 16 ABM1_LS_REG_READ_MISSED_FRAME_CLEAR 24 24 ABM1_BL_REG_READ_MISSED_FRAME_CLEAR 31 31 mmABM0_DC_ABM1_HG_MISC_CTRL 0 0x17c5 11 0 2 ABM1_HG_NUM_OF_BINS_SEL 0 1 ABM1_HG_VMAX_SEL 8 8 ABM1_HG_FINE_MODE_BIN_SEL 12 12 ABM1_HG_BIN_BITWIDTH_SIZE_SEL 16 17 ABM1_OVR_SCAN_PIXEL_PROCESS_EN 20 20 ABM1_DBUF_HGLS_READBACK_DB_REG_VALUE_EN 23 23 ABM1_DBUF_HGLS_REG_FRAME_START_DISP_SEL 24 26 ABM1_DBUF_HGLS_REG_UPDATE_AT_FRAME_START 28 28 ABM1_HGLS_IGNORE_MASTER_LOCK_EN 29 29 ABM1_DBUF_HGLS_REG_UPDATE_PENDING 30 30 ABM1_HGLS_REG_LOCK 31 31 mmABM0_DC_ABM1_LS_SUM_OF_LUMA 0 0x17c6 1 0 2 ABM1_LS_SUM_OF_LUMA 0 31 mmABM0_DC_ABM1_LS_MIN_MAX_LUMA 0 0x17c7 2 0 2 ABM1_LS_MIN_LUMA 0 9 ABM1_LS_MAX_LUMA 16 25 mmABM0_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA 0 0x17c8 2 0 2 ABM1_LS_FILTERED_MIN_LUMA 0 9 ABM1_LS_FILTERED_MAX_LUMA 16 25 mmABM0_DC_ABM1_LS_PIXEL_COUNT 0 0x17c9 2 0 2 ABM1_LS_PIXEL_COUNT 0 23 ABM1_LS_SUM_OF_LUMA_MSB 24 31 mmABM0_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES 0 0x17ca 3 0 2 ABM1_LS_MIN_PIXEL_VALUE_THRES 0 9 ABM1_LS_MAX_PIXEL_VALUE_THRES 16 25 ABM1_HGLS_REG_LOCK 31 31 mmABM0_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT 0 0x17cb 1 0 2 ABM1_LS_MIN_PIXEL_VALUE_COUNT 0 23 mmABM0_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT 0 0x17cc 1 0 2 ABM1_LS_MAX_PIXEL_VALUE_COUNT 0 23 mmABM0_DC_ABM1_HG_SAMPLE_RATE 0 0x17cd 5 0 2 ABM1_HG_SAMPLE_RATE_COUNT_EN 0 0 ABM1_HG_RESET_SAMPLE_RATE_FRAME_COUNTER 1 1 ABM1_HG_SAMPLE_RATE_FRAME_COUNT 8 15 ABM1_HG_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET 16 23 ABM1_HGLS_REG_LOCK 31 31 mmABM0_DC_ABM1_LS_SAMPLE_RATE 0 0x17ce 5 0 2 ABM1_LS_SAMPLE_RATE_COUNT_EN 0 0 ABM1_LS_RESET_SAMPLE_RATE_FRAME_COUNTER 1 1 ABM1_LS_SAMPLE_RATE_FRAME_COUNT 8 15 ABM1_LS_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET 16 23 ABM1_HGLS_REG_LOCK 31 31 mmABM0_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG 0 0x17cf 1 0 2 ABM1_HG_BIN_1_32_SHIFT_FLAG 0 31 mmABM0_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX 0 0x17d0 1 0 2 ABM1_HG_BIN_1_8_SHIFT_INDEX 0 31 mmABM0_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX 0 0x17d1 1 0 2 ABM1_HG_BIN_9_16_SHIFT_INDEX 0 31 mmABM0_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX 0 0x17d2 1 0 2 ABM1_HG_BIN_17_24_SHIFT_INDEX 0 31 mmABM0_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX 0 0x17d3 1 0 2 ABM1_HG_BIN_25_32_SHIFT_INDEX 0 31 mmABM0_DC_ABM1_HG_RESULT_1 0 0x17d4 1 0 2 ABM1_HG_RESULT_1 0 31 mmABM0_DC_ABM1_HG_RESULT_2 0 0x17d5 1 0 2 ABM1_HG_RESULT_2 0 31 mmABM0_DC_ABM1_HG_RESULT_3 0 0x17d6 1 0 2 ABM1_HG_RESULT_3 0 31 mmABM0_DC_ABM1_HG_RESULT_4 0 0x17d7 1 0 2 ABM1_HG_RESULT_4 0 31 mmABM0_DC_ABM1_HG_RESULT_5 0 0x17d8 1 0 2 ABM1_HG_RESULT_5 0 31 mmABM0_DC_ABM1_HG_RESULT_6 0 0x17d9 1 0 2 ABM1_HG_RESULT_6 0 31 mmABM0_DC_ABM1_HG_RESULT_7 0 0x17da 1 0 2 ABM1_HG_RESULT_7 0 31 mmABM0_DC_ABM1_HG_RESULT_8 0 0x17db 1 0 2 ABM1_HG_RESULT_8 0 31 mmABM0_DC_ABM1_HG_RESULT_9 0 0x17dc 1 0 2 ABM1_HG_RESULT_9 0 31 mmABM0_DC_ABM1_HG_RESULT_10 0 0x17dd 1 0 2 ABM1_HG_RESULT_10 0 31 mmABM0_DC_ABM1_HG_RESULT_11 0 0x17de 1 0 2 ABM1_HG_RESULT_11 0 31 mmABM0_DC_ABM1_HG_RESULT_12 0 0x17df 1 0 2 ABM1_HG_RESULT_12 0 31 mmABM0_DC_ABM1_HG_RESULT_13 0 0x17e0 1 0 2 ABM1_HG_RESULT_13 0 31 mmABM0_DC_ABM1_HG_RESULT_14 0 0x17e1 1 0 2 ABM1_HG_RESULT_14 0 31 mmABM0_DC_ABM1_HG_RESULT_15 0 0x17e2 1 0 2 ABM1_HG_RESULT_15 0 31 mmABM0_DC_ABM1_HG_RESULT_16 0 0x17e3 1 0 2 ABM1_HG_RESULT_16 0 31 mmABM0_DC_ABM1_HG_RESULT_17 0 0x17e4 1 0 2 ABM1_HG_RESULT_17 0 31 mmABM0_DC_ABM1_HG_RESULT_18 0 0x17e5 1 0 2 ABM1_HG_RESULT_18 0 31 mmABM0_DC_ABM1_HG_RESULT_19 0 0x17e6 1 0 2 ABM1_HG_RESULT_19 0 31 mmABM0_DC_ABM1_HG_RESULT_20 0 0x17e7 1 0 2 ABM1_HG_RESULT_20 0 31 mmABM0_DC_ABM1_HG_RESULT_21 0 0x17e8 1 0 2 ABM1_HG_RESULT_21 0 31 mmABM0_DC_ABM1_HG_RESULT_22 0 0x17e9 1 0 2 ABM1_HG_RESULT_22 0 31 mmABM0_DC_ABM1_HG_RESULT_23 0 0x17ea 1 0 2 ABM1_HG_RESULT_23 0 31 mmABM0_DC_ABM1_HG_RESULT_24 0 0x17eb 1 0 2 ABM1_HG_RESULT_24 0 31 mmABM0_DC_ABM1_BL_MASTER_LOCK 0 0x17ec 1 0 2 ABM1_BL_MASTER_LOCK 31 31 mmABM1_BL1_PWM_AMBIENT_LIGHT_LEVEL 0 0x17f6 1 0 2 BL1_PWM_AMBIENT_LIGHT_LEVEL 0 16 mmABM1_BL1_PWM_USER_LEVEL 0 0x17f7 1 0 2 BL1_PWM_USER_LEVEL 0 16 mmABM1_BL1_PWM_TARGET_ABM_LEVEL 0 0x17f8 1 0 2 BL1_PWM_TARGET_ABM_LEVEL 0 16 mmABM1_BL1_PWM_CURRENT_ABM_LEVEL 0 0x17f9 1 0 2 BL1_PWM_CURRENT_ABM_LEVEL 0 16 mmABM1_BL1_PWM_FINAL_DUTY_CYCLE 0 0x17fa 1 0 2 BL1_PWM_FINAL_DUTY_CYCLE 0 16 mmABM1_BL1_PWM_MINIMUM_DUTY_CYCLE 0 0x17fb 1 0 2 BL1_PWM_MINIMUM_DUTY_CYCLE 0 16 mmABM1_BL1_PWM_ABM_CNTL 0 0x17fc 5 0 2 BL1_PWM_USE_ABM_EN 0 0 BL1_PWM_USE_AMBIENT_LEVEL_EN 1 1 BL1_PWM_AUTO_UPDATE_CURRENT_ABM_LEVEL_EN 2 2 BL1_PWM_AUTO_CALC_FINAL_DUTY_CYCLE_EN 3 3 BL1_PWM_AUTO_UPDATE_CURRENT_ABM_STEP_SIZE 16 31 mmABM1_BL1_PWM_BL_UPDATE_SAMPLE_RATE 0 0x17fd 5 0 2 BL1_PWM_BL_UPDATE_SAMPLE_RATE_COUNT_EN 0 0 BL1_PWM_BL_UPDATE_RESET_SAMPLE_RATE_FRAME_COUNTER 1 1 BL1_PWM_BL_UPDATE_SAMPLE_RATE_FRAME_COUNT 8 15 BL1_PWM_BL_UPDATE_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET 16 23 ABM1_HGLS_REG_LOCK 31 31 mmABM1_BL1_PWM_GRP2_REG_LOCK 0 0x17fe 6 0 2 BL1_PWM_GRP2_REG_LOCK 0 0 BL1_PWM_GRP2_REG_UPDATE_PENDING 8 8 BL1_PWM_GRP2_UPDATE_AT_FRAME_START 16 16 BL1_PWM_GRP2_FRAME_START_DISP_SEL 17 19 BL1_PWM_GRP2_READBACK_DB_REG_VALUE_EN 24 24 BL1_PWM_GRP2_IGNORE_MASTER_LOCK_EN 31 31 mmABM1_DC_ABM1_CNTL 0 0x17ff 2 0 2 ABM1_EN 0 0 ABM1_SOURCE_SELECT 8 10 mmABM1_DC_ABM1_IPCSC_COEFF_SEL 0 0x1800 4 0 2 ABM1_IPCSC_COEFF_SEL_B 0 3 ABM1_IPCSC_COEFF_SEL_G 8 11 ABM1_IPCSC_COEFF_SEL_R 16 19 ABM1_HGLS_REG_LOCK 31 31 mmABM1_DC_ABM1_ACE_OFFSET_SLOPE_0 0 0x1801 3 0 2 ABM1_ACE_SLOPE_0 0 14 ABM1_ACE_OFFSET_0 16 26 ABM1_ACE_LOCK 31 31 mmABM1_DC_ABM1_ACE_OFFSET_SLOPE_1 0 0x1802 3 0 2 ABM1_ACE_SLOPE_1 0 14 ABM1_ACE_OFFSET_1 16 26 ABM1_ACE_LOCK 31 31 mmABM1_DC_ABM1_ACE_OFFSET_SLOPE_2 0 0x1803 3 0 2 ABM1_ACE_SLOPE_2 0 14 ABM1_ACE_OFFSET_2 16 26 ABM1_ACE_LOCK 31 31 mmABM1_DC_ABM1_ACE_OFFSET_SLOPE_3 0 0x1804 3 0 2 ABM1_ACE_SLOPE_3 0 14 ABM1_ACE_OFFSET_3 16 26 ABM1_ACE_LOCK 31 31 mmABM1_DC_ABM1_ACE_OFFSET_SLOPE_4 0 0x1805 3 0 2 ABM1_ACE_SLOPE_4 0 14 ABM1_ACE_OFFSET_4 16 26 ABM1_ACE_LOCK 31 31 mmABM1_DC_ABM1_ACE_THRES_12 0 0x1806 3 0 2 ABM1_ACE_THRES_1 0 9 ABM1_ACE_THRES_2 16 25 ABM1_ACE_LOCK 31 31 mmABM1_DC_ABM1_ACE_THRES_34 0 0x1807 6 0 2 ABM1_ACE_THRES_3 0 9 ABM1_ACE_THRES_4 16 25 ABM1_ACE_IGNORE_MASTER_LOCK_EN 28 28 ABM1_ACE_READBACK_DB_REG_VALUE_EN 29 29 ABM1_ACE_DBUF_REG_UPDATE_PENDING 30 30 ABM1_ACE_LOCK 31 31 mmABM1_DC_ABM1_ACE_CNTL_MISC 0 0x1808 2 0 2 ABM1_ACE_REG_WR_MISSED_FRAME 0 0 ABM1_ACE_REG_WR_MISSED_FRAME_CLEAR 8 8 mmABM1_DC_ABM1_HGLS_REG_READ_PROGRESS 0 0x180a 9 0 2 ABM1_HG_REG_READ_IN_PROGRESS 0 0 ABM1_LS_REG_READ_IN_PROGRESS 1 1 ABM1_BL_REG_READ_IN_PROGRESS 2 2 ABM1_HG_REG_READ_MISSED_FRAME 8 8 ABM1_LS_REG_READ_MISSED_FRAME 9 9 ABM1_BL_REG_READ_MISSED_FRAME 10 10 ABM1_HG_REG_READ_MISSED_FRAME_CLEAR 16 16 ABM1_LS_REG_READ_MISSED_FRAME_CLEAR 24 24 ABM1_BL_REG_READ_MISSED_FRAME_CLEAR 31 31 mmABM1_DC_ABM1_HG_MISC_CTRL 0 0x180b 11 0 2 ABM1_HG_NUM_OF_BINS_SEL 0 1 ABM1_HG_VMAX_SEL 8 8 ABM1_HG_FINE_MODE_BIN_SEL 12 12 ABM1_HG_BIN_BITWIDTH_SIZE_SEL 16 17 ABM1_OVR_SCAN_PIXEL_PROCESS_EN 20 20 ABM1_DBUF_HGLS_READBACK_DB_REG_VALUE_EN 23 23 ABM1_DBUF_HGLS_REG_FRAME_START_DISP_SEL 24 26 ABM1_DBUF_HGLS_REG_UPDATE_AT_FRAME_START 28 28 ABM1_HGLS_IGNORE_MASTER_LOCK_EN 29 29 ABM1_DBUF_HGLS_REG_UPDATE_PENDING 30 30 ABM1_HGLS_REG_LOCK 31 31 mmABM1_DC_ABM1_LS_SUM_OF_LUMA 0 0x180c 1 0 2 ABM1_LS_SUM_OF_LUMA 0 31 mmABM1_DC_ABM1_LS_MIN_MAX_LUMA 0 0x180d 2 0 2 ABM1_LS_MIN_LUMA 0 9 ABM1_LS_MAX_LUMA 16 25 mmABM1_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA 0 0x180e 2 0 2 ABM1_LS_FILTERED_MIN_LUMA 0 9 ABM1_LS_FILTERED_MAX_LUMA 16 25 mmABM1_DC_ABM1_LS_PIXEL_COUNT 0 0x180f 2 0 2 ABM1_LS_PIXEL_COUNT 0 23 ABM1_LS_SUM_OF_LUMA_MSB 24 31 mmABM1_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES 0 0x1810 3 0 2 ABM1_LS_MIN_PIXEL_VALUE_THRES 0 9 ABM1_LS_MAX_PIXEL_VALUE_THRES 16 25 ABM1_HGLS_REG_LOCK 31 31 mmABM1_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT 0 0x1811 1 0 2 ABM1_LS_MIN_PIXEL_VALUE_COUNT 0 23 mmABM1_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT 0 0x1812 1 0 2 ABM1_LS_MAX_PIXEL_VALUE_COUNT 0 23 mmABM1_DC_ABM1_HG_SAMPLE_RATE 0 0x1813 5 0 2 ABM1_HG_SAMPLE_RATE_COUNT_EN 0 0 ABM1_HG_RESET_SAMPLE_RATE_FRAME_COUNTER 1 1 ABM1_HG_SAMPLE_RATE_FRAME_COUNT 8 15 ABM1_HG_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET 16 23 ABM1_HGLS_REG_LOCK 31 31 mmABM1_DC_ABM1_LS_SAMPLE_RATE 0 0x1814 5 0 2 ABM1_LS_SAMPLE_RATE_COUNT_EN 0 0 ABM1_LS_RESET_SAMPLE_RATE_FRAME_COUNTER 1 1 ABM1_LS_SAMPLE_RATE_FRAME_COUNT 8 15 ABM1_LS_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET 16 23 ABM1_HGLS_REG_LOCK 31 31 mmABM1_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG 0 0x1815 1 0 2 ABM1_HG_BIN_1_32_SHIFT_FLAG 0 31 mmABM1_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX 0 0x1816 1 0 2 ABM1_HG_BIN_1_8_SHIFT_INDEX 0 31 mmABM1_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX 0 0x1817 1 0 2 ABM1_HG_BIN_9_16_SHIFT_INDEX 0 31 mmABM1_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX 0 0x1818 1 0 2 ABM1_HG_BIN_17_24_SHIFT_INDEX 0 31 mmABM1_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX 0 0x1819 1 0 2 ABM1_HG_BIN_25_32_SHIFT_INDEX 0 31 mmABM1_DC_ABM1_HG_RESULT_1 0 0x181a 1 0 2 ABM1_HG_RESULT_1 0 31 mmABM1_DC_ABM1_HG_RESULT_2 0 0x181b 1 0 2 ABM1_HG_RESULT_2 0 31 mmABM1_DC_ABM1_HG_RESULT_3 0 0x181c 1 0 2 ABM1_HG_RESULT_3 0 31 mmABM1_DC_ABM1_HG_RESULT_4 0 0x181d 1 0 2 ABM1_HG_RESULT_4 0 31 mmABM1_DC_ABM1_HG_RESULT_5 0 0x181e 1 0 2 ABM1_HG_RESULT_5 0 31 mmABM1_DC_ABM1_HG_RESULT_6 0 0x181f 1 0 2 ABM1_HG_RESULT_6 0 31 mmABM1_DC_ABM1_HG_RESULT_7 0 0x1820 1 0 2 ABM1_HG_RESULT_7 0 31 mmABM1_DC_ABM1_HG_RESULT_8 0 0x1821 1 0 2 ABM1_HG_RESULT_8 0 31 mmABM1_DC_ABM1_HG_RESULT_9 0 0x1822 1 0 2 ABM1_HG_RESULT_9 0 31 mmABM1_DC_ABM1_HG_RESULT_10 0 0x1823 1 0 2 ABM1_HG_RESULT_10 0 31 mmABM1_DC_ABM1_HG_RESULT_11 0 0x1824 1 0 2 ABM1_HG_RESULT_11 0 31 mmABM1_DC_ABM1_HG_RESULT_12 0 0x1825 1 0 2 ABM1_HG_RESULT_12 0 31 mmABM1_DC_ABM1_HG_RESULT_13 0 0x1826 1 0 2 ABM1_HG_RESULT_13 0 31 mmABM1_DC_ABM1_HG_RESULT_14 0 0x1827 1 0 2 ABM1_HG_RESULT_14 0 31 mmABM1_DC_ABM1_HG_RESULT_15 0 0x1828 1 0 2 ABM1_HG_RESULT_15 0 31 mmABM1_DC_ABM1_HG_RESULT_16 0 0x1829 1 0 2 ABM1_HG_RESULT_16 0 31 mmABM1_DC_ABM1_HG_RESULT_17 0 0x182a 1 0 2 ABM1_HG_RESULT_17 0 31 mmABM1_DC_ABM1_HG_RESULT_18 0 0x182b 1 0 2 ABM1_HG_RESULT_18 0 31 mmABM1_DC_ABM1_HG_RESULT_19 0 0x182c 1 0 2 ABM1_HG_RESULT_19 0 31 mmABM1_DC_ABM1_HG_RESULT_20 0 0x182d 1 0 2 ABM1_HG_RESULT_20 0 31 mmABM1_DC_ABM1_HG_RESULT_21 0 0x182e 1 0 2 ABM1_HG_RESULT_21 0 31 mmABM1_DC_ABM1_HG_RESULT_22 0 0x182f 1 0 2 ABM1_HG_RESULT_22 0 31 mmABM1_DC_ABM1_HG_RESULT_23 0 0x1830 1 0 2 ABM1_HG_RESULT_23 0 31 mmABM1_DC_ABM1_HG_RESULT_24 0 0x1831 1 0 2 ABM1_HG_RESULT_24 0 31 mmABM1_DC_ABM1_BL_MASTER_LOCK 0 0x1832 1 0 2 ABM1_BL_MASTER_LOCK 31 31 mmFMT0_FMT_CLAMP_COMPONENT_R 0 0x183c 2 0 2 FMT_CLAMP_LOWER_R 0 15 FMT_CLAMP_UPPER_R 16 31 mmFMT0_FMT_CLAMP_COMPONENT_G 0 0x183d 2 0 2 FMT_CLAMP_LOWER_G 0 15 FMT_CLAMP_UPPER_G 16 31 mmFMT0_FMT_CLAMP_COMPONENT_B 0 0x183e 2 0 2 FMT_CLAMP_LOWER_B 0 15 FMT_CLAMP_UPPER_B 16 31 mmFMT0_FMT_DYNAMIC_EXP_CNTL 0 0x183f 2 0 2 FMT_DYNAMIC_EXP_EN 0 0 FMT_DYNAMIC_EXP_MODE 4 4 mmFMT0_FMT_CONTROL 0 0x1840 8 0 2 FMT_STEREOSYNC_OVERRIDE 0 0 FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX 8 11 FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP 12 13 FMT_PIXEL_ENCODING 16 17 FMT_SUBSAMPLING_MODE 18 19 FMT_SUBSAMPLING_ORDER 20 20 FMT_CBCR_BIT_REDUCTION_BYPASS 21 21 FMT_DOUBLE_BUFFER_REG_UPDATE_PENDING 24 24 mmFMT0_FMT_BIT_DEPTH_CONTROL 0 0x1841 17 0 2 FMT_TRUNCATE_EN 0 0 FMT_TRUNCATE_MODE 1 1 FMT_TRUNCATE_DEPTH 4 5 FMT_SPATIAL_DITHER_EN 8 8 FMT_SPATIAL_DITHER_MODE 9 10 FMT_SPATIAL_DITHER_DEPTH 11 12 FMT_FRAME_RANDOM_ENABLE 13 13 FMT_RGB_RANDOM_ENABLE 14 14 FMT_HIGHPASS_RANDOM_ENABLE 15 15 FMT_TEMPORAL_DITHER_EN 16 16 FMT_TEMPORAL_DITHER_DEPTH 17 18 FMT_TEMPORAL_DITHER_OFFSET 21 22 FMT_TEMPORAL_LEVEL 24 24 FMT_TEMPORAL_DITHER_RESET 25 25 FMT_25FRC_SEL 26 27 FMT_50FRC_SEL 28 29 FMT_75FRC_SEL 30 31 mmFMT0_FMT_DITHER_RAND_R_SEED 0 0x1842 2 0 2 FMT_RAND_R_SEED 0 7 FMT_OFFSET_R_CR 16 31 mmFMT0_FMT_DITHER_RAND_G_SEED 0 0x1843 2 0 2 FMT_RAND_G_SEED 0 7 FMT_OFFSET_G_Y 16 31 mmFMT0_FMT_DITHER_RAND_B_SEED 0 0x1844 2 0 2 FMT_RAND_B_SEED 0 7 FMT_OFFSET_B_CB 16 31 mmFMT0_FMT_CLAMP_CNTL 0 0x1848 2 0 2 FMT_CLAMP_DATA_EN 0 0 FMT_CLAMP_COLOR_FORMAT 16 18 mmFMT0_FMT_SIDE_BY_SIDE_STEREO_CONTROL 0 0x1849 1 0 2 FMT_SIDE_BY_SIDE_STEREO_ACTIVE_WIDTH 0 12 mmFMT0_FMT_MAP420_MEMORY_CONTROL 0 0x184a 3 0 2 FMT_MAP420MEM_PWR_FORCE 0 1 FMT_MAP420MEM_PWR_DIS 4 4 FMT_MAP420MEM_PWR_STATE 8 9 mmOPPBUF0_OPPBUF_CONTROL 0 0x1884 5 0 2 OPPBUF_ACTIVE_WIDTH 0 13 OPPBUF_DISPLAY_SEGMENTATION 16 18 OPPBUF_OVERLAP_PIXEL_NUM 20 23 OPPBUF_PIXEL_REPETITION 24 27 OPPBUF_DOUBLE_BUFFER_PENDING 28 28 mmOPPBUF0_OPPBUF_3D_PARAMETERS_0 0 0x1885 3 0 2 OPPBUF_3D_VACT_SPACE1_SIZE 0 9 OPPBUF_3D_VACT_SPACE2_SIZE 10 19 OPPBUF_DUMMY_DATA_R 20 31 mmOPPBUF0_OPPBUF_3D_PARAMETERS_1 0 0x1886 2 0 2 OPPBUF_DUMMY_DATA_G 0 11 OPPBUF_DUMMY_DATA_B 16 27 mmOPP_PIPE0_OPP_PIPE_CONTROL 0 0x188c 3 0 2 OPP_PIPE_CLOCK_EN 0 0 OPP_PIPE_CLOCK_ON 1 1 OPP_PIPE_DIGITAL_BYPASS_EN 4 4 mmOPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL 0 0x1891 9 0 2 OPP_PIPE_CRC_EN 0 0 OPP_PIPE_CRC_CONT_EN 4 4 OPP_PIPE_CRC_STEREO_MODE 8 9 OPP_PIPE_CRC_STEREO_EN 10 10 OPP_PIPE_CRC_INTERLACE_MODE 12 13 OPP_PIPE_CRC_INTERLACE_EN 14 14 OPP_PIPE_CRC_PIXEL_SELECT 20 21 OPP_PIPE_CRC_SOURCE_SELECT 24 24 OPP_PIPE_CRC_ONE_SHOT_PENDING 28 28 mmOPP_PIPE_CRC0_OPP_PIPE_CRC_MASK 0 0x1892 1 0 2 OPP_PIPE_CRC_MASK 0 15 mmOPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT0 0 0x1893 2 0 2 OPP_PIPE_CRC_RESULT_A 0 15 OPP_PIPE_CRC_RESULT_R 16 31 mmOPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT1 0 0x1894 2 0 2 OPP_PIPE_CRC_RESULT_G 0 15 OPP_PIPE_CRC_RESULT_B 16 31 mmOPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT2 0 0x1895 1 0 2 OPP_PIPE_CRC_RESULT_C 0 15 mmFMT1_FMT_CLAMP_COMPONENT_R 0 0x1896 2 0 2 FMT_CLAMP_LOWER_R 0 15 FMT_CLAMP_UPPER_R 16 31 mmFMT1_FMT_CLAMP_COMPONENT_G 0 0x1897 2 0 2 FMT_CLAMP_LOWER_G 0 15 FMT_CLAMP_UPPER_G 16 31 mmFMT1_FMT_CLAMP_COMPONENT_B 0 0x1898 2 0 2 FMT_CLAMP_LOWER_B 0 15 FMT_CLAMP_UPPER_B 16 31 mmFMT1_FMT_DYNAMIC_EXP_CNTL 0 0x1899 2 0 2 FMT_DYNAMIC_EXP_EN 0 0 FMT_DYNAMIC_EXP_MODE 4 4 mmFMT1_FMT_CONTROL 0 0x189a 8 0 2 FMT_STEREOSYNC_OVERRIDE 0 0 FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX 8 11 FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP 12 13 FMT_PIXEL_ENCODING 16 17 FMT_SUBSAMPLING_MODE 18 19 FMT_SUBSAMPLING_ORDER 20 20 FMT_CBCR_BIT_REDUCTION_BYPASS 21 21 FMT_DOUBLE_BUFFER_REG_UPDATE_PENDING 24 24 mmFMT1_FMT_BIT_DEPTH_CONTROL 0 0x189b 17 0 2 FMT_TRUNCATE_EN 0 0 FMT_TRUNCATE_MODE 1 1 FMT_TRUNCATE_DEPTH 4 5 FMT_SPATIAL_DITHER_EN 8 8 FMT_SPATIAL_DITHER_MODE 9 10 FMT_SPATIAL_DITHER_DEPTH 11 12 FMT_FRAME_RANDOM_ENABLE 13 13 FMT_RGB_RANDOM_ENABLE 14 14 FMT_HIGHPASS_RANDOM_ENABLE 15 15 FMT_TEMPORAL_DITHER_EN 16 16 FMT_TEMPORAL_DITHER_DEPTH 17 18 FMT_TEMPORAL_DITHER_OFFSET 21 22 FMT_TEMPORAL_LEVEL 24 24 FMT_TEMPORAL_DITHER_RESET 25 25 FMT_25FRC_SEL 26 27 FMT_50FRC_SEL 28 29 FMT_75FRC_SEL 30 31 mmFMT1_FMT_DITHER_RAND_R_SEED 0 0x189c 2 0 2 FMT_RAND_R_SEED 0 7 FMT_OFFSET_R_CR 16 31 mmFMT1_FMT_DITHER_RAND_G_SEED 0 0x189d 2 0 2 FMT_RAND_G_SEED 0 7 FMT_OFFSET_G_Y 16 31 mmFMT1_FMT_DITHER_RAND_B_SEED 0 0x189e 2 0 2 FMT_RAND_B_SEED 0 7 FMT_OFFSET_B_CB 16 31 mmFMT1_FMT_CLAMP_CNTL 0 0x18a2 2 0 2 FMT_CLAMP_DATA_EN 0 0 FMT_CLAMP_COLOR_FORMAT 16 18 mmFMT1_FMT_SIDE_BY_SIDE_STEREO_CONTROL 0 0x18a3 1 0 2 FMT_SIDE_BY_SIDE_STEREO_ACTIVE_WIDTH 0 12 mmFMT1_FMT_MAP420_MEMORY_CONTROL 0 0x18a4 3 0 2 FMT_MAP420MEM_PWR_FORCE 0 1 FMT_MAP420MEM_PWR_DIS 4 4 FMT_MAP420MEM_PWR_STATE 8 9 mmOPPBUF1_OPPBUF_CONTROL 0 0x18de 5 0 2 OPPBUF_ACTIVE_WIDTH 0 13 OPPBUF_DISPLAY_SEGMENTATION 16 18 OPPBUF_OVERLAP_PIXEL_NUM 20 23 OPPBUF_PIXEL_REPETITION 24 27 OPPBUF_DOUBLE_BUFFER_PENDING 28 28 mmOPPBUF1_OPPBUF_3D_PARAMETERS_0 0 0x18df 3 0 2 OPPBUF_3D_VACT_SPACE1_SIZE 0 9 OPPBUF_3D_VACT_SPACE2_SIZE 10 19 OPPBUF_DUMMY_DATA_R 20 31 mmOPPBUF1_OPPBUF_3D_PARAMETERS_1 0 0x18e0 2 0 2 OPPBUF_DUMMY_DATA_G 0 11 OPPBUF_DUMMY_DATA_B 16 27 mmOPP_PIPE1_OPP_PIPE_CONTROL 0 0x18e6 3 0 2 OPP_PIPE_CLOCK_EN 0 0 OPP_PIPE_CLOCK_ON 1 1 OPP_PIPE_DIGITAL_BYPASS_EN 4 4 mmOPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL 0 0x18eb 9 0 2 OPP_PIPE_CRC_EN 0 0 OPP_PIPE_CRC_CONT_EN 4 4 OPP_PIPE_CRC_STEREO_MODE 8 9 OPP_PIPE_CRC_STEREO_EN 10 10 OPP_PIPE_CRC_INTERLACE_MODE 12 13 OPP_PIPE_CRC_INTERLACE_EN 14 14 OPP_PIPE_CRC_PIXEL_SELECT 20 21 OPP_PIPE_CRC_SOURCE_SELECT 24 24 OPP_PIPE_CRC_ONE_SHOT_PENDING 28 28 mmOPP_PIPE_CRC1_OPP_PIPE_CRC_MASK 0 0x18ec 1 0 2 OPP_PIPE_CRC_MASK 0 15 mmOPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT0 0 0x18ed 2 0 2 OPP_PIPE_CRC_RESULT_A 0 15 OPP_PIPE_CRC_RESULT_R 16 31 mmOPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT1 0 0x18ee 2 0 2 OPP_PIPE_CRC_RESULT_G 0 15 OPP_PIPE_CRC_RESULT_B 16 31 mmOPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT2 0 0x18ef 1 0 2 OPP_PIPE_CRC_RESULT_C 0 15 mmFMT2_FMT_CLAMP_COMPONENT_R 0 0x18f0 2 0 2 FMT_CLAMP_LOWER_R 0 15 FMT_CLAMP_UPPER_R 16 31 mmFMT2_FMT_CLAMP_COMPONENT_G 0 0x18f1 2 0 2 FMT_CLAMP_LOWER_G 0 15 FMT_CLAMP_UPPER_G 16 31 mmFMT2_FMT_CLAMP_COMPONENT_B 0 0x18f2 2 0 2 FMT_CLAMP_LOWER_B 0 15 FMT_CLAMP_UPPER_B 16 31 mmFMT2_FMT_DYNAMIC_EXP_CNTL 0 0x18f3 2 0 2 FMT_DYNAMIC_EXP_EN 0 0 FMT_DYNAMIC_EXP_MODE 4 4 mmFMT2_FMT_CONTROL 0 0x18f4 8 0 2 FMT_STEREOSYNC_OVERRIDE 0 0 FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX 8 11 FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP 12 13 FMT_PIXEL_ENCODING 16 17 FMT_SUBSAMPLING_MODE 18 19 FMT_SUBSAMPLING_ORDER 20 20 FMT_CBCR_BIT_REDUCTION_BYPASS 21 21 FMT_DOUBLE_BUFFER_REG_UPDATE_PENDING 24 24 mmFMT2_FMT_BIT_DEPTH_CONTROL 0 0x18f5 17 0 2 FMT_TRUNCATE_EN 0 0 FMT_TRUNCATE_MODE 1 1 FMT_TRUNCATE_DEPTH 4 5 FMT_SPATIAL_DITHER_EN 8 8 FMT_SPATIAL_DITHER_MODE 9 10 FMT_SPATIAL_DITHER_DEPTH 11 12 FMT_FRAME_RANDOM_ENABLE 13 13 FMT_RGB_RANDOM_ENABLE 14 14 FMT_HIGHPASS_RANDOM_ENABLE 15 15 FMT_TEMPORAL_DITHER_EN 16 16 FMT_TEMPORAL_DITHER_DEPTH 17 18 FMT_TEMPORAL_DITHER_OFFSET 21 22 FMT_TEMPORAL_LEVEL 24 24 FMT_TEMPORAL_DITHER_RESET 25 25 FMT_25FRC_SEL 26 27 FMT_50FRC_SEL 28 29 FMT_75FRC_SEL 30 31 mmFMT2_FMT_DITHER_RAND_R_SEED 0 0x18f6 2 0 2 FMT_RAND_R_SEED 0 7 FMT_OFFSET_R_CR 16 31 mmFMT2_FMT_DITHER_RAND_G_SEED 0 0x18f7 2 0 2 FMT_RAND_G_SEED 0 7 FMT_OFFSET_G_Y 16 31 mmFMT2_FMT_DITHER_RAND_B_SEED 0 0x18f8 2 0 2 FMT_RAND_B_SEED 0 7 FMT_OFFSET_B_CB 16 31 mmFMT2_FMT_CLAMP_CNTL 0 0x18fc 2 0 2 FMT_CLAMP_DATA_EN 0 0 FMT_CLAMP_COLOR_FORMAT 16 18 mmFMT2_FMT_SIDE_BY_SIDE_STEREO_CONTROL 0 0x18fd 1 0 2 FMT_SIDE_BY_SIDE_STEREO_ACTIVE_WIDTH 0 12 mmFMT2_FMT_MAP420_MEMORY_CONTROL 0 0x18fe 3 0 2 FMT_MAP420MEM_PWR_FORCE 0 1 FMT_MAP420MEM_PWR_DIS 4 4 FMT_MAP420MEM_PWR_STATE 8 9 mmOPPBUF2_OPPBUF_CONTROL 0 0x1938 5 0 2 OPPBUF_ACTIVE_WIDTH 0 13 OPPBUF_DISPLAY_SEGMENTATION 16 18 OPPBUF_OVERLAP_PIXEL_NUM 20 23 OPPBUF_PIXEL_REPETITION 24 27 OPPBUF_DOUBLE_BUFFER_PENDING 28 28 mmOPPBUF2_OPPBUF_3D_PARAMETERS_0 0 0x1939 3 0 2 OPPBUF_3D_VACT_SPACE1_SIZE 0 9 OPPBUF_3D_VACT_SPACE2_SIZE 10 19 OPPBUF_DUMMY_DATA_R 20 31 mmOPPBUF2_OPPBUF_3D_PARAMETERS_1 0 0x193a 2 0 2 OPPBUF_DUMMY_DATA_G 0 11 OPPBUF_DUMMY_DATA_B 16 27 mmOPP_PIPE2_OPP_PIPE_CONTROL 0 0x1940 3 0 2 OPP_PIPE_CLOCK_EN 0 0 OPP_PIPE_CLOCK_ON 1 1 OPP_PIPE_DIGITAL_BYPASS_EN 4 4 mmOPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL 0 0x1945 9 0 2 OPP_PIPE_CRC_EN 0 0 OPP_PIPE_CRC_CONT_EN 4 4 OPP_PIPE_CRC_STEREO_MODE 8 9 OPP_PIPE_CRC_STEREO_EN 10 10 OPP_PIPE_CRC_INTERLACE_MODE 12 13 OPP_PIPE_CRC_INTERLACE_EN 14 14 OPP_PIPE_CRC_PIXEL_SELECT 20 21 OPP_PIPE_CRC_SOURCE_SELECT 24 24 OPP_PIPE_CRC_ONE_SHOT_PENDING 28 28 mmOPP_PIPE_CRC2_OPP_PIPE_CRC_MASK 0 0x1946 1 0 2 OPP_PIPE_CRC_MASK 0 15 mmOPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT0 0 0x1947 2 0 2 OPP_PIPE_CRC_RESULT_A 0 15 OPP_PIPE_CRC_RESULT_R 16 31 mmOPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT1 0 0x1948 2 0 2 OPP_PIPE_CRC_RESULT_G 0 15 OPP_PIPE_CRC_RESULT_B 16 31 mmOPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT2 0 0x1949 1 0 2 OPP_PIPE_CRC_RESULT_C 0 15 mmFMT3_FMT_CLAMP_COMPONENT_R 0 0x194a 2 0 2 FMT_CLAMP_LOWER_R 0 15 FMT_CLAMP_UPPER_R 16 31 mmFMT3_FMT_CLAMP_COMPONENT_G 0 0x194b 2 0 2 FMT_CLAMP_LOWER_G 0 15 FMT_CLAMP_UPPER_G 16 31 mmFMT3_FMT_CLAMP_COMPONENT_B 0 0x194c 2 0 2 FMT_CLAMP_LOWER_B 0 15 FMT_CLAMP_UPPER_B 16 31 mmFMT3_FMT_DYNAMIC_EXP_CNTL 0 0x194d 2 0 2 FMT_DYNAMIC_EXP_EN 0 0 FMT_DYNAMIC_EXP_MODE 4 4 mmFMT3_FMT_CONTROL 0 0x194e 8 0 2 FMT_STEREOSYNC_OVERRIDE 0 0 FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX 8 11 FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP 12 13 FMT_PIXEL_ENCODING 16 17 FMT_SUBSAMPLING_MODE 18 19 FMT_SUBSAMPLING_ORDER 20 20 FMT_CBCR_BIT_REDUCTION_BYPASS 21 21 FMT_DOUBLE_BUFFER_REG_UPDATE_PENDING 24 24 mmFMT3_FMT_BIT_DEPTH_CONTROL 0 0x194f 17 0 2 FMT_TRUNCATE_EN 0 0 FMT_TRUNCATE_MODE 1 1 FMT_TRUNCATE_DEPTH 4 5 FMT_SPATIAL_DITHER_EN 8 8 FMT_SPATIAL_DITHER_MODE 9 10 FMT_SPATIAL_DITHER_DEPTH 11 12 FMT_FRAME_RANDOM_ENABLE 13 13 FMT_RGB_RANDOM_ENABLE 14 14 FMT_HIGHPASS_RANDOM_ENABLE 15 15 FMT_TEMPORAL_DITHER_EN 16 16 FMT_TEMPORAL_DITHER_DEPTH 17 18 FMT_TEMPORAL_DITHER_OFFSET 21 22 FMT_TEMPORAL_LEVEL 24 24 FMT_TEMPORAL_DITHER_RESET 25 25 FMT_25FRC_SEL 26 27 FMT_50FRC_SEL 28 29 FMT_75FRC_SEL 30 31 mmFMT3_FMT_DITHER_RAND_R_SEED 0 0x1950 2 0 2 FMT_RAND_R_SEED 0 7 FMT_OFFSET_R_CR 16 31 mmFMT3_FMT_DITHER_RAND_G_SEED 0 0x1951 2 0 2 FMT_RAND_G_SEED 0 7 FMT_OFFSET_G_Y 16 31 mmFMT3_FMT_DITHER_RAND_B_SEED 0 0x1952 2 0 2 FMT_RAND_B_SEED 0 7 FMT_OFFSET_B_CB 16 31 mmFMT3_FMT_CLAMP_CNTL 0 0x1956 2 0 2 FMT_CLAMP_DATA_EN 0 0 FMT_CLAMP_COLOR_FORMAT 16 18 mmFMT3_FMT_SIDE_BY_SIDE_STEREO_CONTROL 0 0x1957 1 0 2 FMT_SIDE_BY_SIDE_STEREO_ACTIVE_WIDTH 0 12 mmFMT3_FMT_MAP420_MEMORY_CONTROL 0 0x1958 3 0 2 FMT_MAP420MEM_PWR_FORCE 0 1 FMT_MAP420MEM_PWR_DIS 4 4 FMT_MAP420MEM_PWR_STATE 8 9 mmOPPBUF3_OPPBUF_CONTROL 0 0x1992 5 0 2 OPPBUF_ACTIVE_WIDTH 0 13 OPPBUF_DISPLAY_SEGMENTATION 16 18 OPPBUF_OVERLAP_PIXEL_NUM 20 23 OPPBUF_PIXEL_REPETITION 24 27 OPPBUF_DOUBLE_BUFFER_PENDING 28 28 mmOPPBUF3_OPPBUF_3D_PARAMETERS_0 0 0x1993 3 0 2 OPPBUF_3D_VACT_SPACE1_SIZE 0 9 OPPBUF_3D_VACT_SPACE2_SIZE 10 19 OPPBUF_DUMMY_DATA_R 20 31 mmOPPBUF3_OPPBUF_3D_PARAMETERS_1 0 0x1994 2 0 2 OPPBUF_DUMMY_DATA_G 0 11 OPPBUF_DUMMY_DATA_B 16 27 mmOPP_PIPE3_OPP_PIPE_CONTROL 0 0x199a 3 0 2 OPP_PIPE_CLOCK_EN 0 0 OPP_PIPE_CLOCK_ON 1 1 OPP_PIPE_DIGITAL_BYPASS_EN 4 4 mmOPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL 0 0x199f 9 0 2 OPP_PIPE_CRC_EN 0 0 OPP_PIPE_CRC_CONT_EN 4 4 OPP_PIPE_CRC_STEREO_MODE 8 9 OPP_PIPE_CRC_STEREO_EN 10 10 OPP_PIPE_CRC_INTERLACE_MODE 12 13 OPP_PIPE_CRC_INTERLACE_EN 14 14 OPP_PIPE_CRC_PIXEL_SELECT 20 21 OPP_PIPE_CRC_SOURCE_SELECT 24 24 OPP_PIPE_CRC_ONE_SHOT_PENDING 28 28 mmOPP_PIPE_CRC3_OPP_PIPE_CRC_MASK 0 0x19a0 1 0 2 OPP_PIPE_CRC_MASK 0 15 mmOPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT0 0 0x19a1 2 0 2 OPP_PIPE_CRC_RESULT_A 0 15 OPP_PIPE_CRC_RESULT_R 16 31 mmOPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT1 0 0x19a2 2 0 2 OPP_PIPE_CRC_RESULT_G 0 15 OPP_PIPE_CRC_RESULT_B 16 31 mmOPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT2 0 0x19a3 1 0 2 OPP_PIPE_CRC_RESULT_C 0 15 mmFMT4_FMT_CLAMP_COMPONENT_R 0 0x19a4 2 0 2 FMT_CLAMP_LOWER_R 0 15 FMT_CLAMP_UPPER_R 16 31 mmFMT4_FMT_CLAMP_COMPONENT_G 0 0x19a5 2 0 2 FMT_CLAMP_LOWER_G 0 15 FMT_CLAMP_UPPER_G 16 31 mmFMT4_FMT_CLAMP_COMPONENT_B 0 0x19a6 2 0 2 FMT_CLAMP_LOWER_B 0 15 FMT_CLAMP_UPPER_B 16 31 mmFMT4_FMT_DYNAMIC_EXP_CNTL 0 0x19a7 2 0 2 FMT_DYNAMIC_EXP_EN 0 0 FMT_DYNAMIC_EXP_MODE 4 4 mmFMT4_FMT_CONTROL 0 0x19a8 8 0 2 FMT_STEREOSYNC_OVERRIDE 0 0 FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX 8 11 FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP 12 13 FMT_PIXEL_ENCODING 16 17 FMT_SUBSAMPLING_MODE 18 19 FMT_SUBSAMPLING_ORDER 20 20 FMT_CBCR_BIT_REDUCTION_BYPASS 21 21 FMT_DOUBLE_BUFFER_REG_UPDATE_PENDING 24 24 mmFMT4_FMT_BIT_DEPTH_CONTROL 0 0x19a9 17 0 2 FMT_TRUNCATE_EN 0 0 FMT_TRUNCATE_MODE 1 1 FMT_TRUNCATE_DEPTH 4 5 FMT_SPATIAL_DITHER_EN 8 8 FMT_SPATIAL_DITHER_MODE 9 10 FMT_SPATIAL_DITHER_DEPTH 11 12 FMT_FRAME_RANDOM_ENABLE 13 13 FMT_RGB_RANDOM_ENABLE 14 14 FMT_HIGHPASS_RANDOM_ENABLE 15 15 FMT_TEMPORAL_DITHER_EN 16 16 FMT_TEMPORAL_DITHER_DEPTH 17 18 FMT_TEMPORAL_DITHER_OFFSET 21 22 FMT_TEMPORAL_LEVEL 24 24 FMT_TEMPORAL_DITHER_RESET 25 25 FMT_25FRC_SEL 26 27 FMT_50FRC_SEL 28 29 FMT_75FRC_SEL 30 31 mmFMT4_FMT_DITHER_RAND_R_SEED 0 0x19aa 2 0 2 FMT_RAND_R_SEED 0 7 FMT_OFFSET_R_CR 16 31 mmFMT4_FMT_DITHER_RAND_G_SEED 0 0x19ab 2 0 2 FMT_RAND_G_SEED 0 7 FMT_OFFSET_G_Y 16 31 mmFMT4_FMT_DITHER_RAND_B_SEED 0 0x19ac 2 0 2 FMT_RAND_B_SEED 0 7 FMT_OFFSET_B_CB 16 31 mmFMT4_FMT_CLAMP_CNTL 0 0x19b0 2 0 2 FMT_CLAMP_DATA_EN 0 0 FMT_CLAMP_COLOR_FORMAT 16 18 mmFMT4_FMT_SIDE_BY_SIDE_STEREO_CONTROL 0 0x19b1 1 0 2 FMT_SIDE_BY_SIDE_STEREO_ACTIVE_WIDTH 0 12 mmFMT4_FMT_MAP420_MEMORY_CONTROL 0 0x19b2 3 0 2 FMT_MAP420MEM_PWR_FORCE 0 1 FMT_MAP420MEM_PWR_DIS 4 4 FMT_MAP420MEM_PWR_STATE 8 9 mmOPPBUF4_OPPBUF_CONTROL 0 0x19ec 5 0 2 OPPBUF_ACTIVE_WIDTH 0 13 OPPBUF_DISPLAY_SEGMENTATION 16 18 OPPBUF_OVERLAP_PIXEL_NUM 20 23 OPPBUF_PIXEL_REPETITION 24 27 OPPBUF_DOUBLE_BUFFER_PENDING 28 28 mmOPPBUF4_OPPBUF_3D_PARAMETERS_0 0 0x19ed 3 0 2 OPPBUF_3D_VACT_SPACE1_SIZE 0 9 OPPBUF_3D_VACT_SPACE2_SIZE 10 19 OPPBUF_DUMMY_DATA_R 20 31 mmOPPBUF4_OPPBUF_3D_PARAMETERS_1 0 0x19ee 2 0 2 OPPBUF_DUMMY_DATA_G 0 11 OPPBUF_DUMMY_DATA_B 16 27 mmOPP_PIPE4_OPP_PIPE_CONTROL 0 0x19f4 3 0 2 OPP_PIPE_CLOCK_EN 0 0 OPP_PIPE_CLOCK_ON 1 1 OPP_PIPE_DIGITAL_BYPASS_EN 4 4 mmOPP_PIPE_CRC4_OPP_PIPE_CRC_CONTROL 0 0x19f9 9 0 2 OPP_PIPE_CRC_EN 0 0 OPP_PIPE_CRC_CONT_EN 4 4 OPP_PIPE_CRC_STEREO_MODE 8 9 OPP_PIPE_CRC_STEREO_EN 10 10 OPP_PIPE_CRC_INTERLACE_MODE 12 13 OPP_PIPE_CRC_INTERLACE_EN 14 14 OPP_PIPE_CRC_PIXEL_SELECT 20 21 OPP_PIPE_CRC_SOURCE_SELECT 24 24 OPP_PIPE_CRC_ONE_SHOT_PENDING 28 28 mmOPP_PIPE_CRC4_OPP_PIPE_CRC_MASK 0 0x19fa 1 0 2 OPP_PIPE_CRC_MASK 0 15 mmOPP_PIPE_CRC4_OPP_PIPE_CRC_RESULT0 0 0x19fb 2 0 2 OPP_PIPE_CRC_RESULT_A 0 15 OPP_PIPE_CRC_RESULT_R 16 31 mmOPP_PIPE_CRC4_OPP_PIPE_CRC_RESULT1 0 0x19fc 2 0 2 OPP_PIPE_CRC_RESULT_G 0 15 OPP_PIPE_CRC_RESULT_B 16 31 mmOPP_PIPE_CRC4_OPP_PIPE_CRC_RESULT2 0 0x19fd 1 0 2 OPP_PIPE_CRC_RESULT_C 0 15 mmFMT5_FMT_CLAMP_COMPONENT_R 0 0x19fe 2 0 2 FMT_CLAMP_LOWER_R 0 15 FMT_CLAMP_UPPER_R 16 31 mmFMT5_FMT_CLAMP_COMPONENT_G 0 0x19ff 2 0 2 FMT_CLAMP_LOWER_G 0 15 FMT_CLAMP_UPPER_G 16 31 mmFMT5_FMT_CLAMP_COMPONENT_B 0 0x1a00 2 0 2 FMT_CLAMP_LOWER_B 0 15 FMT_CLAMP_UPPER_B 16 31 mmFMT5_FMT_DYNAMIC_EXP_CNTL 0 0x1a01 2 0 2 FMT_DYNAMIC_EXP_EN 0 0 FMT_DYNAMIC_EXP_MODE 4 4 mmFMT5_FMT_CONTROL 0 0x1a02 8 0 2 FMT_STEREOSYNC_OVERRIDE 0 0 FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX 8 11 FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP 12 13 FMT_PIXEL_ENCODING 16 17 FMT_SUBSAMPLING_MODE 18 19 FMT_SUBSAMPLING_ORDER 20 20 FMT_CBCR_BIT_REDUCTION_BYPASS 21 21 FMT_DOUBLE_BUFFER_REG_UPDATE_PENDING 24 24 mmFMT5_FMT_BIT_DEPTH_CONTROL 0 0x1a03 17 0 2 FMT_TRUNCATE_EN 0 0 FMT_TRUNCATE_MODE 1 1 FMT_TRUNCATE_DEPTH 4 5 FMT_SPATIAL_DITHER_EN 8 8 FMT_SPATIAL_DITHER_MODE 9 10 FMT_SPATIAL_DITHER_DEPTH 11 12 FMT_FRAME_RANDOM_ENABLE 13 13 FMT_RGB_RANDOM_ENABLE 14 14 FMT_HIGHPASS_RANDOM_ENABLE 15 15 FMT_TEMPORAL_DITHER_EN 16 16 FMT_TEMPORAL_DITHER_DEPTH 17 18 FMT_TEMPORAL_DITHER_OFFSET 21 22 FMT_TEMPORAL_LEVEL 24 24 FMT_TEMPORAL_DITHER_RESET 25 25 FMT_25FRC_SEL 26 27 FMT_50FRC_SEL 28 29 FMT_75FRC_SEL 30 31 mmFMT5_FMT_DITHER_RAND_R_SEED 0 0x1a04 2 0 2 FMT_RAND_R_SEED 0 7 FMT_OFFSET_R_CR 16 31 mmFMT5_FMT_DITHER_RAND_G_SEED 0 0x1a05 2 0 2 FMT_RAND_G_SEED 0 7 FMT_OFFSET_G_Y 16 31 mmFMT5_FMT_DITHER_RAND_B_SEED 0 0x1a06 2 0 2 FMT_RAND_B_SEED 0 7 FMT_OFFSET_B_CB 16 31 mmFMT5_FMT_CLAMP_CNTL 0 0x1a0a 2 0 2 FMT_CLAMP_DATA_EN 0 0 FMT_CLAMP_COLOR_FORMAT 16 18 mmFMT5_FMT_SIDE_BY_SIDE_STEREO_CONTROL 0 0x1a0b 1 0 2 FMT_SIDE_BY_SIDE_STEREO_ACTIVE_WIDTH 0 12 mmFMT5_FMT_MAP420_MEMORY_CONTROL 0 0x1a0c 3 0 2 FMT_MAP420MEM_PWR_FORCE 0 1 FMT_MAP420MEM_PWR_DIS 4 4 FMT_MAP420MEM_PWR_STATE 8 9 mmOPPBUF5_OPPBUF_CONTROL 0 0x1a46 5 0 2 OPPBUF_ACTIVE_WIDTH 0 13 OPPBUF_DISPLAY_SEGMENTATION 16 18 OPPBUF_OVERLAP_PIXEL_NUM 20 23 OPPBUF_PIXEL_REPETITION 24 27 OPPBUF_DOUBLE_BUFFER_PENDING 28 28 mmOPPBUF5_OPPBUF_3D_PARAMETERS_0 0 0x1a47 3 0 2 OPPBUF_3D_VACT_SPACE1_SIZE 0 9 OPPBUF_3D_VACT_SPACE2_SIZE 10 19 OPPBUF_DUMMY_DATA_R 20 31 mmOPPBUF5_OPPBUF_3D_PARAMETERS_1 0 0x1a48 2 0 2 OPPBUF_DUMMY_DATA_G 0 11 OPPBUF_DUMMY_DATA_B 16 27 mmOPP_PIPE5_OPP_PIPE_CONTROL 0 0x1a4e 3 0 2 OPP_PIPE_CLOCK_EN 0 0 OPP_PIPE_CLOCK_ON 1 1 OPP_PIPE_DIGITAL_BYPASS_EN 4 4 mmOPP_PIPE_CRC5_OPP_PIPE_CRC_CONTROL 0 0x1a53 9 0 2 OPP_PIPE_CRC_EN 0 0 OPP_PIPE_CRC_CONT_EN 4 4 OPP_PIPE_CRC_STEREO_MODE 8 9 OPP_PIPE_CRC_STEREO_EN 10 10 OPP_PIPE_CRC_INTERLACE_MODE 12 13 OPP_PIPE_CRC_INTERLACE_EN 14 14 OPP_PIPE_CRC_PIXEL_SELECT 20 21 OPP_PIPE_CRC_SOURCE_SELECT 24 24 OPP_PIPE_CRC_ONE_SHOT_PENDING 28 28 mmOPP_PIPE_CRC5_OPP_PIPE_CRC_MASK 0 0x1a54 1 0 2 OPP_PIPE_CRC_MASK 0 15 mmOPP_PIPE_CRC5_OPP_PIPE_CRC_RESULT0 0 0x1a55 2 0 2 OPP_PIPE_CRC_RESULT_A 0 15 OPP_PIPE_CRC_RESULT_R 16 31 mmOPP_PIPE_CRC5_OPP_PIPE_CRC_RESULT1 0 0x1a56 2 0 2 OPP_PIPE_CRC_RESULT_G 0 15 OPP_PIPE_CRC_RESULT_B 16 31 mmOPP_PIPE_CRC5_OPP_PIPE_CRC_RESULT2 0 0x1a57 1 0 2 OPP_PIPE_CRC_RESULT_C 0 15 mmOPP_TOP_CLK_CONTROL 0 0x1a5e 5 0 2 OPP_DISPCLK_R_GATE_DIS 0 0 OPP_DISPCLK_G_ABM_GATE_DIS 4 4 OPP_TEST_CLK_SEL 8 11 OPP_ABM0_CLOCK_ON 12 12 OPP_ABM1_CLOCK_ON 13 13 mmDC_PERFMON17_PERFCOUNTER_CNTL 0 0x1abe 11 0 2 PERFCOUNTER_EVENT_SEL 0 8 PERFCOUNTER_CVALUE_SEL 9 11 PERFCOUNTER_INC_MODE 12 14 PERFCOUNTER_HW_CNTL_SEL 15 15 PERFCOUNTER_RUNEN_MODE 16 16 PERFCOUNTER_CNTOFF_START_DIS 22 22 PERFCOUNTER_RESTART_EN 23 23 PERFCOUNTER_INT_EN 24 24 PERFCOUNTER_OFF_MASK 25 25 PERFCOUNTER_ACTIVE 26 26 PERFCOUNTER_CNTL_SEL 29 31 mmDC_PERFMON17_PERFCOUNTER_CNTL2 0 0x1abf 5 0 2 PERFCOUNTER_COUNTED_VALUE_TYPE 0 1 PERFCOUNTER_HW_STOP1_SEL 2 2 PERFCOUNTER_HW_STOP2_SEL 3 3 PERFCOUNTER_CNTOFF_SEL 8 13 PERFCOUNTER_CNTL2_SEL 29 31 mmDC_PERFMON17_PERFCOUNTER_STATE 0 0x1ac0 16 0 2 PERFCOUNTER_CNT0_STATE 0 1 PERFCOUNTER_STATE_SEL0 2 2 PERFCOUNTER_CNT1_STATE 4 5 PERFCOUNTER_STATE_SEL1 6 6 PERFCOUNTER_CNT2_STATE 8 9 PERFCOUNTER_STATE_SEL2 10 10 PERFCOUNTER_CNT3_STATE 12 13 PERFCOUNTER_STATE_SEL3 14 14 PERFCOUNTER_CNT4_STATE 16 17 PERFCOUNTER_STATE_SEL4 18 18 PERFCOUNTER_CNT5_STATE 20 21 PERFCOUNTER_STATE_SEL5 22 22 PERFCOUNTER_CNT6_STATE 24 25 PERFCOUNTER_STATE_SEL6 26 26 PERFCOUNTER_CNT7_STATE 28 29 PERFCOUNTER_STATE_SEL7 30 30 mmDC_PERFMON17_PERFMON_CNTL 0 0x1ac1 6 0 2 PERFMON_STATE 0 1 PERFMON_RPT_COUNT 8 27 PERFMON_CNTOFF_AND_OR 28 28 PERFMON_CNTOFF_INT_EN 29 29 PERFMON_CNTOFF_INT_STATUS 30 30 PERFMON_CNTOFF_INT_ACK 31 31 mmDC_PERFMON17_PERFMON_CNTL2 0 0x1ac2 4 0 2 PERFMON_CNTOFF_INT_TYPE 0 0 PERFMON_CLK_ENABLE 1 1 PERFMON_RUN_ENABLE_START_SEL 2 9 PERFMON_RUN_ENABLE_STOP_SEL 10 17 mmDC_PERFMON17_PERFMON_CVALUE_INT_MISC 0 0x1ac3 17 0 2 PERFCOUNTER_INT0_STATUS 0 0 PERFCOUNTER_INT1_STATUS 1 1 PERFCOUNTER_INT2_STATUS 2 2 PERFCOUNTER_INT3_STATUS 3 3 PERFCOUNTER_INT4_STATUS 4 4 PERFCOUNTER_INT5_STATUS 5 5 PERFCOUNTER_INT6_STATUS 6 6 PERFCOUNTER_INT7_STATUS 7 7 PERFCOUNTER_INT0_ACK 8 8 PERFCOUNTER_INT1_ACK 9 9 PERFCOUNTER_INT2_ACK 10 10 PERFCOUNTER_INT3_ACK 11 11 PERFCOUNTER_INT4_ACK 12 12 PERFCOUNTER_INT5_ACK 13 13 PERFCOUNTER_INT6_ACK 14 14 PERFCOUNTER_INT7_ACK 15 15 PERFMON_CVALUE_HI 16 31 mmDC_PERFMON17_PERFMON_CVALUE_LOW 0 0x1ac4 1 0 2 PERFMON_CVALUE_LOW 0 31 mmDC_PERFMON17_PERFMON_HI 0 0x1ac5 2 0 2 PERFMON_HI 0 15 PERFMON_READ_SEL 29 31 mmDC_PERFMON17_PERFMON_LOW 0 0x1ac6 1 0 2 PERFMON_LOW 0 31 mmODM0_OPTC_INPUT_GLOBAL_CONTROL 0 0x1aca 6 0 2 OPTC_INPUT_SOFT_RESET 0 0 OPTC_UNDERFLOW_INT_EN 8 8 OPTC_UNDERFLOW_INT_TYPE 9 9 OPTC_UNDERFLOW_OCCURRED_STATUS 10 10 OPTC_UNDERFLOW_INT_STATUS 11 11 OPTC_UNDERFLOW_CLEAR 12 12 mmODM0_OPTC_DATA_SOURCE_SELECT 0 0x1acb 1 0 2 OPTC_SRC_SEL 8 10 mmODM0_OPTC_INPUT_CLOCK_CONTROL 0 0x1acd 3 0 2 OPTC_INPUT_CLK_GATE_DIS 0 0 OPTC_INPUT_CLK_EN 1 1 OPTC_INPUT_CLK_ON 2 2 mmODM0_OPTC_INPUT_SPARE_REGISTER 0 0x1acf 1 0 2 OPTC_INPUT_SPARE_REG 0 31 mmODM1_OPTC_INPUT_GLOBAL_CONTROL 0 0x1ada 6 0 2 OPTC_INPUT_SOFT_RESET 0 0 OPTC_UNDERFLOW_INT_EN 8 8 OPTC_UNDERFLOW_INT_TYPE 9 9 OPTC_UNDERFLOW_OCCURRED_STATUS 10 10 OPTC_UNDERFLOW_INT_STATUS 11 11 OPTC_UNDERFLOW_CLEAR 12 12 mmODM1_OPTC_DATA_SOURCE_SELECT 0 0x1adb 1 0 2 OPTC_SRC_SEL 8 10 mmODM1_OPTC_INPUT_CLOCK_CONTROL 0 0x1add 3 0 2 OPTC_INPUT_CLK_GATE_DIS 0 0 OPTC_INPUT_CLK_EN 1 1 OPTC_INPUT_CLK_ON 2 2 mmODM1_OPTC_INPUT_SPARE_REGISTER 0 0x1adf 1 0 2 OPTC_INPUT_SPARE_REG 0 31 mmODM2_OPTC_INPUT_GLOBAL_CONTROL 0 0x1aea 6 0 2 OPTC_INPUT_SOFT_RESET 0 0 OPTC_UNDERFLOW_INT_EN 8 8 OPTC_UNDERFLOW_INT_TYPE 9 9 OPTC_UNDERFLOW_OCCURRED_STATUS 10 10 OPTC_UNDERFLOW_INT_STATUS 11 11 OPTC_UNDERFLOW_CLEAR 12 12 mmODM2_OPTC_DATA_SOURCE_SELECT 0 0x1aeb 1 0 2 OPTC_SRC_SEL 8 10 mmODM2_OPTC_INPUT_CLOCK_CONTROL 0 0x1aed 3 0 2 OPTC_INPUT_CLK_GATE_DIS 0 0 OPTC_INPUT_CLK_EN 1 1 OPTC_INPUT_CLK_ON 2 2 mmODM2_OPTC_INPUT_SPARE_REGISTER 0 0x1aef 1 0 2 OPTC_INPUT_SPARE_REG 0 31 mmODM3_OPTC_INPUT_GLOBAL_CONTROL 0 0x1afa 6 0 2 OPTC_INPUT_SOFT_RESET 0 0 OPTC_UNDERFLOW_INT_EN 8 8 OPTC_UNDERFLOW_INT_TYPE 9 9 OPTC_UNDERFLOW_OCCURRED_STATUS 10 10 OPTC_UNDERFLOW_INT_STATUS 11 11 OPTC_UNDERFLOW_CLEAR 12 12 mmODM3_OPTC_DATA_SOURCE_SELECT 0 0x1afb 1 0 2 OPTC_SRC_SEL 8 10 mmODM3_OPTC_INPUT_CLOCK_CONTROL 0 0x1afd 3 0 2 OPTC_INPUT_CLK_GATE_DIS 0 0 OPTC_INPUT_CLK_EN 1 1 OPTC_INPUT_CLK_ON 2 2 mmODM3_OPTC_INPUT_SPARE_REGISTER 0 0x1aff 1 0 2 OPTC_INPUT_SPARE_REG 0 31 mmODM4_OPTC_INPUT_GLOBAL_CONTROL 0 0x1b0a 6 0 2 OPTC_INPUT_SOFT_RESET 0 0 OPTC_UNDERFLOW_INT_EN 8 8 OPTC_UNDERFLOW_INT_TYPE 9 9 OPTC_UNDERFLOW_OCCURRED_STATUS 10 10 OPTC_UNDERFLOW_INT_STATUS 11 11 OPTC_UNDERFLOW_CLEAR 12 12 mmODM4_OPTC_DATA_SOURCE_SELECT 0 0x1b0b 1 0 2 OPTC_SRC_SEL 8 10 mmODM4_OPTC_INPUT_CLOCK_CONTROL 0 0x1b0d 3 0 2 OPTC_INPUT_CLK_GATE_DIS 0 0 OPTC_INPUT_CLK_EN 1 1 OPTC_INPUT_CLK_ON 2 2 mmODM4_OPTC_INPUT_SPARE_REGISTER 0 0x1b0f 1 0 2 OPTC_INPUT_SPARE_REG 0 31 mmODM5_OPTC_INPUT_GLOBAL_CONTROL 0 0x1b1a 6 0 2 OPTC_INPUT_SOFT_RESET 0 0 OPTC_UNDERFLOW_INT_EN 8 8 OPTC_UNDERFLOW_INT_TYPE 9 9 OPTC_UNDERFLOW_OCCURRED_STATUS 10 10 OPTC_UNDERFLOW_INT_STATUS 11 11 OPTC_UNDERFLOW_CLEAR 12 12 mmODM5_OPTC_DATA_SOURCE_SELECT 0 0x1b1b 1 0 2 OPTC_SRC_SEL 8 10 mmODM5_OPTC_INPUT_CLOCK_CONTROL 0 0x1b1d 3 0 2 OPTC_INPUT_CLK_GATE_DIS 0 0 OPTC_INPUT_CLK_EN 1 1 OPTC_INPUT_CLK_ON 2 2 mmODM5_OPTC_INPUT_SPARE_REGISTER 0 0x1b1f 1 0 2 OPTC_INPUT_SPARE_REG 0 31 mmOTG0_OTG_H_TOTAL 0 0x1b2a 1 0 2 OTG_H_TOTAL 0 14 mmOTG0_OTG_H_BLANK_START_END 0 0x1b2b 2 0 2 OTG_H_BLANK_START 0 14 OTG_H_BLANK_END 16 30 mmOTG0_OTG_H_SYNC_A 0 0x1b2c 2 0 2 OTG_H_SYNC_A_START 0 14 OTG_H_SYNC_A_END 16 30 mmOTG0_OTG_H_SYNC_A_CNTL 0 0x1b2d 3 0 2 OTG_H_SYNC_A_POL 0 0 OTG_COMP_SYNC_A_EN 16 16 OTG_H_SYNC_A_CUTOFF 17 17 mmOTG0_OTG_H_TIMING_CNTL 0 0x1b2e 2 0 2 OTG_H_TIMING_DIV_BY2 0 0 OTG_H_TIMING_DIV_BY2_UPDATE_MODE 8 8 mmOTG0_OTG_V_TOTAL 0 0x1b2f 1 0 2 OTG_V_TOTAL 0 14 mmOTG0_OTG_V_TOTAL_MIN 0 0x1b30 1 0 2 OTG_V_TOTAL_MIN 0 14 mmOTG0_OTG_V_TOTAL_MAX 0 0x1b31 1 0 2 OTG_V_TOTAL_MAX 0 14 mmOTG0_OTG_V_TOTAL_MID 0 0x1b32 1 0 2 OTG_V_TOTAL_MID 0 14 mmOTG0_OTG_V_TOTAL_CONTROL 0 0x1b33 8 0 2 OTG_V_TOTAL_MIN_SEL 0 0 OTG_V_TOTAL_MAX_SEL 1 1 OTG_VTOTAL_MID_REPLACING_MAX_EN 2 2 OTG_VTOTAL_MID_REPLACING_MIN_EN 3 3 OTG_FORCE_LOCK_ON_EVENT 4 4 OTG_SET_V_TOTAL_MIN_MASK_EN 7 7 OTG_VTOTAL_MID_FRAME_NUM 8 15 OTG_SET_V_TOTAL_MIN_MASK 16 31 mmOTG0_OTG_V_TOTAL_INT_STATUS 0 0x1b34 4 0 2 OTG_SET_V_TOTAL_MIN_EVENT_OCCURED 0 0 OTG_SET_V_TOTAL_MIN_EVENT_OCCURED_INT 4 4 OTG_SET_V_TOTAL_MIN_EVENT_OCCURED_ACK 8 8 OTG_SET_V_TOTAL_MIN_EVENT_OCCURED_MSK 12 12 mmOTG0_OTG_VSYNC_NOM_INT_STATUS 0 0x1b35 2 0 2 OTG_VSYNC_NOM 0 0 OTG_VSYNC_NOM_INT_CLEAR 4 4 mmOTG0_OTG_V_BLANK_START_END 0 0x1b36 2 0 2 OTG_V_BLANK_START 0 14 OTG_V_BLANK_END 16 30 mmOTG0_OTG_V_SYNC_A 0 0x1b37 2 0 2 OTG_V_SYNC_A_START 0 14 OTG_V_SYNC_A_END 16 30 mmOTG0_OTG_V_SYNC_A_CNTL 0 0x1b38 1 0 2 OTG_V_SYNC_A_POL 0 0 mmOTG0_OTG_TRIGA_CNTL 0 0x1b39 12 0 2 OTG_TRIGA_SOURCE_SELECT 0 4 OTG_TRIGA_SOURCE_PIPE_SELECT 5 7 OTG_TRIGA_POLARITY_SELECT 8 10 OTG_TRIGA_RESYNC_BYPASS_EN 11 11 OTG_TRIGA_INPUT_STATUS 12 12 OTG_TRIGA_POLARITY_STATUS 13 13 OTG_TRIGA_OCCURRED 14 14 OTG_TRIGA_RISING_EDGE_DETECT_CNTL 16 17 OTG_TRIGA_FALLING_EDGE_DETECT_CNTL 18 19 OTG_TRIGA_FREQUENCY_SELECT 20 21 OTG_TRIGA_DELAY 24 28 OTG_TRIGA_CLEAR 31 31 mmOTG0_OTG_TRIGA_MANUAL_TRIG 0 0x1b3a 1 0 2 OTG_TRIGA_MANUAL_TRIG 0 0 mmOTG0_OTG_TRIGB_CNTL 0 0x1b3b 12 0 2 OTG_TRIGB_SOURCE_SELECT 0 4 OTG_TRIGB_SOURCE_PIPE_SELECT 5 7 OTG_TRIGB_POLARITY_SELECT 8 10 OTG_TRIGB_RESYNC_BYPASS_EN 11 11 OTG_TRIGB_INPUT_STATUS 12 12 OTG_TRIGB_POLARITY_STATUS 13 13 OTG_TRIGB_OCCURRED 14 14 OTG_TRIGB_RISING_EDGE_DETECT_CNTL 16 17 OTG_TRIGB_FALLING_EDGE_DETECT_CNTL 18 19 OTG_TRIGB_FREQUENCY_SELECT 20 21 OTG_TRIGB_DELAY 24 28 OTG_TRIGB_CLEAR 31 31 mmOTG0_OTG_TRIGB_MANUAL_TRIG 0 0x1b3c 1 0 2 OTG_TRIGB_MANUAL_TRIG 0 0 mmOTG0_OTG_FORCE_COUNT_NOW_CNTL 0 0x1b3d 5 0 2 OTG_FORCE_COUNT_NOW_MODE 0 1 OTG_FORCE_COUNT_NOW_CHECK 4 4 OTG_FORCE_COUNT_NOW_TRIG_SEL 8 8 OTG_FORCE_COUNT_NOW_OCCURRED 16 16 OTG_FORCE_COUNT_NOW_CLEAR 24 24 mmOTG0_OTG_FLOW_CONTROL 0 0x1b3e 4 0 2 OTG_FLOW_CONTROL_SOURCE_SELECT 0 4 OTG_FLOW_CONTROL_POLARITY 8 8 OTG_FLOW_CONTROL_GRANULARITY 16 16 OTG_FLOW_CONTROL_INPUT_STATUS 24 24 mmOTG0_OTG_STEREO_FORCE_NEXT_EYE 0 0x1b3f 3 0 2 OTG_STEREO_FORCE_NEXT_EYE 0 1 OTG_AVSYNC_FRAME_COUNTER 8 15 OTG_AVSYNC_LINE_COUNTER 16 28 mmOTG0_OTG_AVSYNC_COUNTER 0 0x1b40 1 0 2 OTG_AVSYNC_COUNTER 0 31 mmOTG0_OTG_CONTROL 0 0x1b41 6 0 2 OTG_MASTER_EN 0 0 OTG_DISABLE_POINT_CNTL 8 9 OTG_START_POINT_CNTL 12 12 OTG_FIELD_NUMBER_CNTL 13 13 OTG_FIELD_NUMBER_POLARITY 14 14 OTG_CURRENT_MASTER_EN_STATE 16 16 mmOTG0_OTG_BLANK_CONTROL 0 0x1b42 3 0 2 OTG_CURRENT_BLANK_STATE 0 0 OTG_BLANK_DATA_EN 8 8 OTG_BLANK_DE_MODE 16 16 mmOTG0_OTG_PIPE_ABORT_CONTROL 0 0x1b43 2 0 2 OTG_PIPE_ABORT 0 0 OTG_PIPE_ABORT_DONE 8 8 mmOTG0_OTG_INTERLACE_CONTROL 0 0x1b44 2 0 2 OTG_INTERLACE_ENABLE 0 0 OTG_INTERLACE_FORCE_NEXT_FIELD 16 17 mmOTG0_OTG_INTERLACE_STATUS 0 0x1b45 2 0 2 OTG_INTERLACE_CURRENT_FIELD 0 0 OTG_INTERLACE_NEXT_FIELD 1 1 mmOTG0_OTG_FIELD_INDICATION_CONTROL 0 0x1b46 2 0 2 OTG_FIELD_INDICATION_OUTPUT_POLARITY 0 0 OTG_FIELD_ALIGNMENT 1 1 mmOTG0_OTG_PIXEL_DATA_READBACK0 0 0x1b47 2 0 2 OTG_PIXEL_DATA_BLUE_CB 0 15 OTG_PIXEL_DATA_GREEN_Y 16 31 mmOTG0_OTG_PIXEL_DATA_READBACK1 0 0x1b48 1 0 2 OTG_PIXEL_DATA_RED_CR 0 15 mmOTG0_OTG_STATUS 0 0x1b49 8 0 2 OTG_V_BLANK 0 0 OTG_V_ACTIVE_DISP 1 1 OTG_V_SYNC_A 2 2 OTG_V_UPDATE 3 3 OTG_V_BLANK_3D_STRUCTURE 5 5 OTG_H_BLANK 16 16 OTG_H_ACTIVE_DISP 17 17 OTG_H_SYNC_A 18 18 mmOTG0_OTG_STATUS_POSITION 0 0x1b4a 2 0 2 OTG_VERT_COUNT 0 14 OTG_HORZ_COUNT 16 30 mmOTG0_OTG_NOM_VERT_POSITION 0 0x1b4b 1 0 2 OTG_VERT_COUNT_NOM 0 14 mmOTG0_OTG_STATUS_FRAME_COUNT 0 0x1b4c 1 0 2 OTG_FRAME_COUNT 0 23 mmOTG0_OTG_STATUS_VF_COUNT 0 0x1b4d 1 0 2 OTG_VF_COUNT 0 30 mmOTG0_OTG_STATUS_HV_COUNT 0 0x1b4e 1 0 2 OTG_HV_COUNT 0 30 mmOTG0_OTG_COUNT_CONTROL 0 0x1b4f 2 0 2 OTG_HORZ_COUNT_BY2_EN 0 0 OTG_HORZ_REPETITION_COUNT 1 4 mmOTG0_OTG_COUNT_RESET 0 0x1b50 1 0 2 OTG_RESET_FRAME_COUNT 0 0 mmOTG0_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE 0 0x1b51 1 0 2 OTG_MANUAL_FORCE_VSYNC_NEXT_LINE 0 0 mmOTG0_OTG_VERT_SYNC_CONTROL 0 0x1b52 3 0 2 OTG_FORCE_VSYNC_NEXT_LINE_OCCURRED 0 0 OTG_FORCE_VSYNC_NEXT_LINE_CLEAR 8 8 OTG_AUTO_FORCE_VSYNC_MODE 16 17 mmOTG0_OTG_STEREO_STATUS 0 0x1b53 7 0 2 OTG_STEREO_CURRENT_EYE 0 0 OTG_STEREO_SYNC_OUTPUT 8 8 OTG_STEREO_SYNC_SELECT 16 16 OTG_STEREO_EYE_FLAG 20 20 OTG_STEREO_FORCE_NEXT_EYE_PENDING 24 25 OTG_CURRENT_3D_STRUCTURE_STATE 30 30 OTG_CURRENT_STEREOSYNC_EN_STATE 31 31 mmOTG0_OTG_STEREO_CONTROL 0 0x1b54 7 0 2 OTG_STEREO_SYNC_OUTPUT_LINE_NUM 0 14 OTG_STEREO_SYNC_OUTPUT_POLARITY 15 15 OTG_STEREO_EYE_FLAG_POLARITY 17 17 OTG_DISABLE_STEREOSYNC_OUTPUT_FOR_DP 18 18 OTG_DISABLE_FIELD_NUM 19 19 OTG_DISABLE_V_BLANK_FOR_DP_FIX 20 20 OTG_STEREO_EN 24 24 mmOTG0_OTG_SNAPSHOT_STATUS 0 0x1b55 3 0 2 OTG_SNAPSHOT_OCCURRED 0 0 OTG_SNAPSHOT_CLEAR 1 1 OTG_SNAPSHOT_MANUAL_TRIGGER 2 2 mmOTG0_OTG_SNAPSHOT_CONTROL 0 0x1b56 1 0 2 OTG_AUTO_SNAPSHOT_TRIG_SEL 0 1 mmOTG0_OTG_SNAPSHOT_POSITION 0 0x1b57 2 0 2 OTG_SNAPSHOT_VERT_COUNT 0 14 OTG_SNAPSHOT_HORZ_COUNT 16 30 mmOTG0_OTG_SNAPSHOT_FRAME 0 0x1b58 1 0 2 OTG_SNAPSHOT_FRAME_COUNT 0 23 mmOTG0_OTG_INTERRUPT_CONTROL 0 0x1b59 14 0 2 OTG_SNAPSHOT_INT_MSK 0 0 OTG_SNAPSHOT_INT_TYPE 1 1 OTG_FORCE_COUNT_NOW_INT_MSK 8 8 OTG_FORCE_COUNT_NOW_INT_TYPE 9 9 OTG_FORCE_VSYNC_NEXT_LINE_INT_MSK 16 16 OTG_FORCE_VSYNC_NEXT_LINE_INT_TYPE 17 17 OTG_TRIGA_INT_MSK 24 24 OTG_TRIGB_INT_MSK 25 25 OTG_TRIGA_INT_TYPE 26 26 OTG_TRIGB_INT_TYPE 27 27 OTG_VSYNC_NOM_INT_MSK 28 28 OTG_VSYNC_NOM_INT_TYPE 29 29 OTG_GSL_VSYNC_GAP_INT_MSK 30 30 OTG_GSL_VSYNC_GAP_INT_TYPE 31 31 mmOTG0_OTG_UPDATE_LOCK 0 0x1b5a 1 0 2 OTG_UPDATE_LOCK 0 0 mmOTG0_OTG_DOUBLE_BUFFER_CONTROL 0 0x1b5b 10 0 2 OTG_UPDATE_PENDING 0 0 OTG_H_TIMING_DIV_BY2_DB_UPDATE_PENDING 2 2 OTG_BLANK_DATA_EN_UPDATE_PENDING 3 3 OTG_RANGE_TIMING_DBUF_UPDATE_PENDING 4 4 OTG_TIMING_DB_UPDATE_PENDING 5 5 OTG_3D_CTRL_DB_UPDATE_PENDING 6 6 OTG_3D_STRUCTURE_EN_DB_UPDATE_PENDING 7 7 OTG_UPDATE_INSTANTLY 8 8 OTG_BLANK_DATA_DOUBLE_BUFFER_EN 16 16 OTG_RANGE_TIMING_DBUF_UPDATE_MODE 24 25 mmOTG0_OTG_TEST_PATTERN_CONTROL 0 0x1b5c 4 0 2 OTG_TEST_PATTERN_EN 0 0 OTG_TEST_PATTERN_MODE 8 10 OTG_TEST_PATTERN_DYNAMIC_RANGE 16 16 OTG_TEST_PATTERN_COLOR_FORMAT 24 31 mmOTG0_OTG_TEST_PATTERN_PARAMETERS 0 0x1b5d 5 0 2 OTG_TEST_PATTERN_INC0 0 3 OTG_TEST_PATTERN_INC1 4 7 OTG_TEST_PATTERN_VRES 8 11 OTG_TEST_PATTERN_HRES 12 15 OTG_TEST_PATTERN_RAMP0_OFFSET 16 31 mmOTG0_OTG_TEST_PATTERN_COLOR 0 0x1b5e 2 0 2 OTG_TEST_PATTERN_DATA 0 15 OTG_TEST_PATTERN_MASK 16 21 mmOTG0_OTG_MASTER_EN 0 0x1b5f 1 0 2 OTG_MASTER_EN 0 0 mmOTG0_OTG_BLANK_DATA_COLOR 0 0x1b61 3 0 2 OTG_BLANK_DATA_COLOR_BLUE_CB 0 9 OTG_BLANK_DATA_COLOR_GREEN_Y 10 19 OTG_BLANK_DATA_COLOR_RED_CR 20 29 mmOTG0_OTG_BLANK_DATA_COLOR_EXT 0 0x1b62 3 0 2 OTG_BLANK_DATA_COLOR_BLUE_CB_EXT 0 5 OTG_BLANK_DATA_COLOR_GREEN_Y_EXT 8 13 OTG_BLANK_DATA_COLOR_RED_CR_EXT 16 21 mmOTG0_OTG_BLACK_COLOR 0 0x1b63 3 0 2 OTG_BLACK_COLOR_B_CB 0 9 OTG_BLACK_COLOR_G_Y 10 19 OTG_BLACK_COLOR_R_CR 20 29 mmOTG0_OTG_BLACK_COLOR_EXT 0 0x1b64 3 0 2 OTG_BLACK_COLOR_B_CB_EXT 0 5 OTG_BLACK_COLOR_G_Y_EXT 8 13 OTG_BLACK_COLOR_R_CR_EXT 16 21 mmOTG0_OTG_VERTICAL_INTERRUPT0_POSITION 0 0x1b65 2 0 2 OTG_VERTICAL_INTERRUPT0_LINE_START 0 14 OTG_VERTICAL_INTERRUPT0_LINE_END 16 30 mmOTG0_OTG_VERTICAL_INTERRUPT0_CONTROL 0 0x1b66 6 0 2 OTG_VERTICAL_INTERRUPT0_OUTPUT_POLARITY 4 4 OTG_VERTICAL_INTERRUPT0_INT_ENABLE 8 8 OTG_VERTICAL_INTERRUPT0_STATUS 12 12 OTG_VERTICAL_INTERRUPT0_INT_STATUS 16 16 OTG_VERTICAL_INTERRUPT0_CLEAR 20 20 OTG_VERTICAL_INTERRUPT0_INT_TYPE 24 24 mmOTG0_OTG_VERTICAL_INTERRUPT1_POSITION 0 0x1b67 1 0 2 OTG_VERTICAL_INTERRUPT1_LINE_START 0 14 mmOTG0_OTG_VERTICAL_INTERRUPT1_CONTROL 0 0x1b68 5 0 2 OTG_VERTICAL_INTERRUPT1_INT_ENABLE 8 8 OTG_VERTICAL_INTERRUPT1_STATUS 12 12 OTG_VERTICAL_INTERRUPT1_INT_STATUS 16 16 OTG_VERTICAL_INTERRUPT1_CLEAR 20 20 OTG_VERTICAL_INTERRUPT1_INT_TYPE 24 24 mmOTG0_OTG_VERTICAL_INTERRUPT2_POSITION 0 0x1b69 1 0 2 OTG_VERTICAL_INTERRUPT2_LINE_START 0 14 mmOTG0_OTG_VERTICAL_INTERRUPT2_CONTROL 0 0x1b6a 5 0 2 OTG_VERTICAL_INTERRUPT2_INT_ENABLE 8 8 OTG_VERTICAL_INTERRUPT2_STATUS 12 12 OTG_VERTICAL_INTERRUPT2_INT_STATUS 16 16 OTG_VERTICAL_INTERRUPT2_CLEAR 20 20 OTG_VERTICAL_INTERRUPT2_INT_TYPE 24 24 mmOTG0_OTG_CRC_CNTL 0 0x1b6b 16 0 2 OTG_CRC_EN 0 0 OTG_CRC_DUAL_LINK_EN 1 1 OTG_CRC_DUAL_LINK_MODE 2 2 OTG_CRC_BLANK_ONLY 3 3 OTG_CRC_CONT_EN 4 4 OTG_CRC_CAPTURE_START_SEL 5 6 OTG_CRC_STEREO_MODE 8 9 OTG_CRC_INTERLACE_MODE 12 13 OTG_CRC_MULTI_STREAM_MODE 16 18 OTG_CRC_USE_NEW_AND_REPEATED_PIXELS 19 19 OTG_CRC0_SELECT 20 22 OTG_CRC1_SELECT 24 26 OTG_ONE_SHOT_CRC0_PENDING 28 28 OTG_ONE_SHOT_CRC1_PENDING 29 29 OTG_ONE_SHOT_CRC2_PENDING 30 30 OTG_ONE_SHOT_CRC3_PENDING 31 31 mmOTG0_OTG_CRC0_WINDOWA_X_CONTROL 0 0x1b6c 2 0 2 OTG_CRC0_WINDOWA_X_START 0 14 OTG_CRC0_WINDOWA_X_END 16 30 mmOTG0_OTG_CRC0_WINDOWA_Y_CONTROL 0 0x1b6d 2 0 2 OTG_CRC0_WINDOWA_Y_START 0 14 OTG_CRC0_WINDOWA_Y_END 16 30 mmOTG0_OTG_CRC0_WINDOWB_X_CONTROL 0 0x1b6e 2 0 2 OTG_CRC0_WINDOWB_X_START 0 14 OTG_CRC0_WINDOWB_X_END 16 30 mmOTG0_OTG_CRC0_WINDOWB_Y_CONTROL 0 0x1b6f 2 0 2 OTG_CRC0_WINDOWB_Y_START 0 14 OTG_CRC0_WINDOWB_Y_END 16 30 mmOTG0_OTG_CRC0_DATA_RG 0 0x1b70 2 0 2 CRC0_R_CR 0 15 CRC0_G_Y 16 31 mmOTG0_OTG_CRC0_DATA_B 0 0x1b71 2 0 2 CRC0_B_CB 0 15 CRC0_C 16 31 mmOTG0_OTG_CRC1_WINDOWA_X_CONTROL 0 0x1b72 2 0 2 OTG_CRC1_WINDOWA_X_START 0 14 OTG_CRC1_WINDOWA_X_END 16 30 mmOTG0_OTG_CRC1_WINDOWA_Y_CONTROL 0 0x1b73 2 0 2 OTG_CRC1_WINDOWA_Y_START 0 14 OTG_CRC1_WINDOWA_Y_END 16 30 mmOTG0_OTG_CRC1_WINDOWB_X_CONTROL 0 0x1b74 2 0 2 OTG_CRC1_WINDOWB_X_START 0 14 OTG_CRC1_WINDOWB_X_END 16 30 mmOTG0_OTG_CRC1_WINDOWB_Y_CONTROL 0 0x1b75 2 0 2 OTG_CRC1_WINDOWB_Y_START 0 14 OTG_CRC1_WINDOWB_Y_END 16 30 mmOTG0_OTG_CRC1_DATA_RG 0 0x1b76 2 0 2 CRC1_R_CR 0 15 CRC1_G_Y 16 31 mmOTG0_OTG_CRC1_DATA_B 0 0x1b77 2 0 2 CRC1_B_CB 0 15 CRC1_C 16 31 mmOTG0_OTG_CRC2_DATA_RG 0 0x1b78 2 0 2 CRC2_R_CR 0 15 CRC2_G_Y 16 31 mmOTG0_OTG_CRC2_DATA_B 0 0x1b79 2 0 2 CRC2_B_CB 0 15 CRC2_C 16 31 mmOTG0_OTG_CRC3_DATA_RG 0 0x1b7a 2 0 2 CRC3_R_CR 0 15 CRC3_G_Y 16 31 mmOTG0_OTG_CRC3_DATA_B 0 0x1b7b 2 0 2 CRC3_B_CB 0 15 CRC3_C 16 31 mmOTG0_OTG_CRC_SIG_RED_GREEN_MASK 0 0x1b7c 2 0 2 OTG_CRC_SIG_RED_MASK 0 15 OTG_CRC_SIG_GREEN_MASK 16 31 mmOTG0_OTG_CRC_SIG_BLUE_CONTROL_MASK 0 0x1b7d 2 0 2 OTG_CRC_SIG_BLUE_MASK 0 15 OTG_CRC_SIG_CONTROL_MASK 16 31 mmOTG0_OTG_STATIC_SCREEN_CONTROL 0 0x1b84 9 0 2 OTG_STATIC_SCREEN_EVENT_MASK 0 15 OTG_STATIC_SCREEN_FRAME_COUNT 16 23 OTG_CPU_SS_INT_ENABLE 24 24 OTG_SS_STATUS 25 25 OTG_CPU_SS_INT_STATUS 26 26 OTG_CPU_SS_INT_CLEAR 27 27 OTG_CPU_SS_INT_TYPE 28 28 OTG_STATIC_SCREEN_OVERRIDE 30 30 OTG_STATIC_SCREEN_OVERRIDE_VALUE 31 31 mmOTG0_OTG_3D_STRUCTURE_CONTROL 0 0x1b85 6 0 2 OTG_3D_STRUCTURE_EN 0 0 OTG_3D_STRUCTURE_V_UPDATE_MODE 8 9 OTG_3D_STRUCTURE_STEREO_SEL_OVR 12 12 OTG_3D_STRUCTURE_F_COUNT_RESET 16 16 OTG_3D_STRUCTURE_F_COUNT_RESET_PENDING 17 17 OTG_3D_STRUCTURE_F_COUNT 18 19 mmOTG0_OTG_GSL_VSYNC_GAP 0 0x1b86 8 0 2 OTG_GSL_VSYNC_GAP_LIMIT 0 7 OTG_GSL_VSYNC_GAP_DELAY 8 15 OTG_GSL_VSYNC_GAP_SOURCE_SEL 16 16 OTG_GSL_VSYNC_GAP_MODE 17 18 OTG_GSL_VSYNC_GAP_CLEAR 19 19 OTG_GSL_VSYNC_GAP_OCCURRED 20 20 OTG_GSL_VSYNC_GAP_MASTER_FASTER 23 23 OTG_GSL_VSYNC_GAP 24 31 mmOTG0_OTG_MASTER_UPDATE_MODE 0 0x1b87 1 0 2 MASTER_UPDATE_INTERLACED_MODE 0 1 mmOTG0_OTG_CLOCK_CONTROL 0 0x1b88 5 0 2 OTG_CLOCK_EN 0 0 OTG_CLOCK_GATE_DIS 1 1 OTG_SOFT_RESET 4 4 OTG_CLOCK_ON 8 8 OTG_BUSY 16 16 mmOTG0_OTG_VSTARTUP_PARAM 0 0x1b89 1 0 2 VSTARTUP_START 0 9 mmOTG0_OTG_VUPDATE_PARAM 0 0x1b8a 2 0 2 VUPDATE_OFFSET 0 15 VUPDATE_WIDTH 16 25 mmOTG0_OTG_VREADY_PARAM 0 0x1b8b 1 0 2 VREADY_OFFSET 0 15 mmOTG0_OTG_GLOBAL_SYNC_STATUS 0 0x1b8c 25 0 2 VSTARTUP_INT_EN 0 0 VSTARTUP_INT_TYPE 1 1 VSTARTUP_EVENT_OCCURRED 2 2 VSTARTUP_INT_STATUS 3 3 VSTARTUP_EVENT_CLEAR 4 4 VUPDATE_INT_EN 5 5 VUPDATE_INT_TYPE 6 6 VUPDATE_INT_POSITION_SEL 7 7 VUPDATE_EVENT_OCCURRED 8 8 VUPDATE_INT_STATUS 9 9 VUPDATE_EVENT_CLEAR 10 10 VUPDATE_STATUS 11 11 VUPDATE_NO_LOCK_INT_EN 12 12 VUPDATE_NO_LOCK_INT_TYPE 13 13 VUPDATE_NO_LOCK_EVENT_OCCURRED 14 14 VUPDATE_NO_LOCK_INT_STATUS 15 15 VUPDATE_NO_LOCK_EVENT_CLEAR 16 16 VUPDATE_NO_LOCK_STATUS 17 17 VREADY_INT_EN 18 18 VREADY_INT_TYPE 19 19 VREADY_EVENT_OCCURRED 20 20 VREADY_INT_STATUS 21 21 VREADY_EVENT_CLEAR 22 22 STEREO_SELECT_STATUS 24 24 FIELD_NUMBER_STATUS 25 25 mmOTG0_OTG_MASTER_UPDATE_LOCK 0 0x1b8d 2 0 2 OTG_MASTER_UPDATE_LOCK 0 0 UPDATE_LOCK_STATUS 8 8 mmOTG0_OTG_GSL_CONTROL 0 0x1b8e 6 0 2 OTG_GSL0_EN 0 0 OTG_GSL1_EN 1 1 OTG_GSL2_EN 2 2 OTG_GSL_MASTER_EN 3 3 OTG_GSL_FORCE_DELAY 16 20 OTG_GSL_CHECK_ALL_FIELDS 28 28 mmOTG0_OTG_GSL_WINDOW_X 0 0x1b8f 2 0 2 OTG_GSL_WINDOW_START_X 0 14 OTG_GSL_WINDOW_END_X 16 30 mmOTG0_OTG_GSL_WINDOW_Y 0 0x1b90 2 0 2 OTG_GSL_WINDOW_START_Y 0 14 OTG_GSL_WINDOW_END_Y 16 30 mmOTG0_OTG_VUPDATE_KEEPOUT 0 0x1b91 3 0 2 MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_START_OFFSET 0 15 MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_END_OFFSET 16 25 OTG_MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_EN 31 31 mmOTG0_OTG_GLOBAL_CONTROL0 0 0x1b92 3 0 2 OTG_MASTER_UPDATE_LOCK_HTOTAL_KEEPOUT 0 7 OTG_MASTER_UPDATE_LOCK_HTOTAL_KEEPOUT_EN 8 8 OTG_MASTER_UPDATE_LOCK_SEL 25 27 mmOTG0_OTG_GLOBAL_CONTROL1 0 0x1b93 3 0 2 MASTER_UPDATE_LOCK_DB_X 0 14 MASTER_UPDATE_LOCK_DB_Y 16 30 MASTER_UPDATE_LOCK_DB_EN 31 31 mmOTG0_OTG_GLOBAL_CONTROL2 0 0x1b94 4 0 2 DIG_UPDATE_LOCATION 0 9 GLOBAL_UPDATE_LOCK_EN 10 10 MANUAL_FLOW_CONTROL_SEL 16 18 DCCG_VUPDATE_MODE 31 31 mmOTG0_OTG_GLOBAL_CONTROL3 0 0x1b95 3 0 2 MASTER_UPDATE_LOCK_DB_FIELD 0 1 MASTER_UPDATE_LOCK_DB_STEREO_SEL 4 5 MASTER_UPDATE_LOCK_DB_FIELD_STEREO_FLAG_SEL 8 8 mmOTG0_OTG_TRIG_MANUAL_CONTROL 0 0x1b96 1 0 2 TRIG_MANUAL_CONTROL 0 0 mmOTG0_OTG_MANUAL_FLOW_CONTROL 0 0x1b97 1 0 2 MANUAL_FLOW_CONTROL 0 0 mmOTG0_OTG_RANGE_TIMING_INT_STATUS 0 0x1b98 5 0 2 OTG_RANGE_TIMING_UPDATE_OCCURRED 0 0 OTG_RANGE_TIMING_UPDATE_OCCURRED_INT 4 4 OTG_RANGE_TIMING_UPDATE_OCCURRED_CLEAR 8 8 OTG_RANGE_TIMING_UPDATE_OCCURRED_INT_MSK 12 12 OTG_RANGE_TIMING_UPDATE_OCCURRED_INT_TYPE 16 16 mmOTG0_OTG_DRR_CONTROL 0 0x1b99 2 0 2 OTG_DRR_AVERAGE_FRAME 0 2 OTG_V_TOTAL_LAST_USED_BY_DRR 16 30 mmOTG0_OTG_REQUEST_CONTROL 0 0x1b9a 1 0 2 OTG_REQUEST_MODE_FOR_H_DUPLICATE 0 0 mmOTG0_OTG_SPARE_REGISTER 0 0x1b9b 1 0 2 OTG_SPARE_REG 0 31 mmOTG1_OTG_H_TOTAL 0 0x1baa 1 0 2 OTG_H_TOTAL 0 14 mmOTG1_OTG_H_BLANK_START_END 0 0x1bab 2 0 2 OTG_H_BLANK_START 0 14 OTG_H_BLANK_END 16 30 mmOTG1_OTG_H_SYNC_A 0 0x1bac 2 0 2 OTG_H_SYNC_A_START 0 14 OTG_H_SYNC_A_END 16 30 mmOTG1_OTG_H_SYNC_A_CNTL 0 0x1bad 3 0 2 OTG_H_SYNC_A_POL 0 0 OTG_COMP_SYNC_A_EN 16 16 OTG_H_SYNC_A_CUTOFF 17 17 mmOTG1_OTG_H_TIMING_CNTL 0 0x1bae 2 0 2 OTG_H_TIMING_DIV_BY2 0 0 OTG_H_TIMING_DIV_BY2_UPDATE_MODE 8 8 mmOTG1_OTG_V_TOTAL 0 0x1baf 1 0 2 OTG_V_TOTAL 0 14 mmOTG1_OTG_V_TOTAL_MIN 0 0x1bb0 1 0 2 OTG_V_TOTAL_MIN 0 14 mmOTG1_OTG_V_TOTAL_MAX 0 0x1bb1 1 0 2 OTG_V_TOTAL_MAX 0 14 mmOTG1_OTG_V_TOTAL_MID 0 0x1bb2 1 0 2 OTG_V_TOTAL_MID 0 14 mmOTG1_OTG_V_TOTAL_CONTROL 0 0x1bb3 8 0 2 OTG_V_TOTAL_MIN_SEL 0 0 OTG_V_TOTAL_MAX_SEL 1 1 OTG_VTOTAL_MID_REPLACING_MAX_EN 2 2 OTG_VTOTAL_MID_REPLACING_MIN_EN 3 3 OTG_FORCE_LOCK_ON_EVENT 4 4 OTG_SET_V_TOTAL_MIN_MASK_EN 7 7 OTG_VTOTAL_MID_FRAME_NUM 8 15 OTG_SET_V_TOTAL_MIN_MASK 16 31 mmOTG1_OTG_V_TOTAL_INT_STATUS 0 0x1bb4 4 0 2 OTG_SET_V_TOTAL_MIN_EVENT_OCCURED 0 0 OTG_SET_V_TOTAL_MIN_EVENT_OCCURED_INT 4 4 OTG_SET_V_TOTAL_MIN_EVENT_OCCURED_ACK 8 8 OTG_SET_V_TOTAL_MIN_EVENT_OCCURED_MSK 12 12 mmOTG1_OTG_VSYNC_NOM_INT_STATUS 0 0x1bb5 2 0 2 OTG_VSYNC_NOM 0 0 OTG_VSYNC_NOM_INT_CLEAR 4 4 mmOTG1_OTG_V_BLANK_START_END 0 0x1bb6 2 0 2 OTG_V_BLANK_START 0 14 OTG_V_BLANK_END 16 30 mmOTG1_OTG_V_SYNC_A 0 0x1bb7 2 0 2 OTG_V_SYNC_A_START 0 14 OTG_V_SYNC_A_END 16 30 mmOTG1_OTG_V_SYNC_A_CNTL 0 0x1bb8 1 0 2 OTG_V_SYNC_A_POL 0 0 mmOTG1_OTG_TRIGA_CNTL 0 0x1bb9 12 0 2 OTG_TRIGA_SOURCE_SELECT 0 4 OTG_TRIGA_SOURCE_PIPE_SELECT 5 7 OTG_TRIGA_POLARITY_SELECT 8 10 OTG_TRIGA_RESYNC_BYPASS_EN 11 11 OTG_TRIGA_INPUT_STATUS 12 12 OTG_TRIGA_POLARITY_STATUS 13 13 OTG_TRIGA_OCCURRED 14 14 OTG_TRIGA_RISING_EDGE_DETECT_CNTL 16 17 OTG_TRIGA_FALLING_EDGE_DETECT_CNTL 18 19 OTG_TRIGA_FREQUENCY_SELECT 20 21 OTG_TRIGA_DELAY 24 28 OTG_TRIGA_CLEAR 31 31 mmOTG1_OTG_TRIGA_MANUAL_TRIG 0 0x1bba 1 0 2 OTG_TRIGA_MANUAL_TRIG 0 0 mmOTG1_OTG_TRIGB_CNTL 0 0x1bbb 12 0 2 OTG_TRIGB_SOURCE_SELECT 0 4 OTG_TRIGB_SOURCE_PIPE_SELECT 5 7 OTG_TRIGB_POLARITY_SELECT 8 10 OTG_TRIGB_RESYNC_BYPASS_EN 11 11 OTG_TRIGB_INPUT_STATUS 12 12 OTG_TRIGB_POLARITY_STATUS 13 13 OTG_TRIGB_OCCURRED 14 14 OTG_TRIGB_RISING_EDGE_DETECT_CNTL 16 17 OTG_TRIGB_FALLING_EDGE_DETECT_CNTL 18 19 OTG_TRIGB_FREQUENCY_SELECT 20 21 OTG_TRIGB_DELAY 24 28 OTG_TRIGB_CLEAR 31 31 mmOTG1_OTG_TRIGB_MANUAL_TRIG 0 0x1bbc 1 0 2 OTG_TRIGB_MANUAL_TRIG 0 0 mmOTG1_OTG_FORCE_COUNT_NOW_CNTL 0 0x1bbd 5 0 2 OTG_FORCE_COUNT_NOW_MODE 0 1 OTG_FORCE_COUNT_NOW_CHECK 4 4 OTG_FORCE_COUNT_NOW_TRIG_SEL 8 8 OTG_FORCE_COUNT_NOW_OCCURRED 16 16 OTG_FORCE_COUNT_NOW_CLEAR 24 24 mmOTG1_OTG_FLOW_CONTROL 0 0x1bbe 4 0 2 OTG_FLOW_CONTROL_SOURCE_SELECT 0 4 OTG_FLOW_CONTROL_POLARITY 8 8 OTG_FLOW_CONTROL_GRANULARITY 16 16 OTG_FLOW_CONTROL_INPUT_STATUS 24 24 mmOTG1_OTG_STEREO_FORCE_NEXT_EYE 0 0x1bbf 3 0 2 OTG_STEREO_FORCE_NEXT_EYE 0 1 OTG_AVSYNC_FRAME_COUNTER 8 15 OTG_AVSYNC_LINE_COUNTER 16 28 mmOTG1_OTG_AVSYNC_COUNTER 0 0x1bc0 1 0 2 OTG_AVSYNC_COUNTER 0 31 mmOTG1_OTG_CONTROL 0 0x1bc1 6 0 2 OTG_MASTER_EN 0 0 OTG_DISABLE_POINT_CNTL 8 9 OTG_START_POINT_CNTL 12 12 OTG_FIELD_NUMBER_CNTL 13 13 OTG_FIELD_NUMBER_POLARITY 14 14 OTG_CURRENT_MASTER_EN_STATE 16 16 mmOTG1_OTG_BLANK_CONTROL 0 0x1bc2 3 0 2 OTG_CURRENT_BLANK_STATE 0 0 OTG_BLANK_DATA_EN 8 8 OTG_BLANK_DE_MODE 16 16 mmOTG1_OTG_PIPE_ABORT_CONTROL 0 0x1bc3 2 0 2 OTG_PIPE_ABORT 0 0 OTG_PIPE_ABORT_DONE 8 8 mmOTG1_OTG_INTERLACE_CONTROL 0 0x1bc4 2 0 2 OTG_INTERLACE_ENABLE 0 0 OTG_INTERLACE_FORCE_NEXT_FIELD 16 17 mmOTG1_OTG_INTERLACE_STATUS 0 0x1bc5 2 0 2 OTG_INTERLACE_CURRENT_FIELD 0 0 OTG_INTERLACE_NEXT_FIELD 1 1 mmOTG1_OTG_FIELD_INDICATION_CONTROL 0 0x1bc6 2 0 2 OTG_FIELD_INDICATION_OUTPUT_POLARITY 0 0 OTG_FIELD_ALIGNMENT 1 1 mmOTG1_OTG_PIXEL_DATA_READBACK0 0 0x1bc7 2 0 2 OTG_PIXEL_DATA_BLUE_CB 0 15 OTG_PIXEL_DATA_GREEN_Y 16 31 mmOTG1_OTG_PIXEL_DATA_READBACK1 0 0x1bc8 1 0 2 OTG_PIXEL_DATA_RED_CR 0 15 mmOTG1_OTG_STATUS 0 0x1bc9 8 0 2 OTG_V_BLANK 0 0 OTG_V_ACTIVE_DISP 1 1 OTG_V_SYNC_A 2 2 OTG_V_UPDATE 3 3 OTG_V_BLANK_3D_STRUCTURE 5 5 OTG_H_BLANK 16 16 OTG_H_ACTIVE_DISP 17 17 OTG_H_SYNC_A 18 18 mmOTG1_OTG_STATUS_POSITION 0 0x1bca 2 0 2 OTG_VERT_COUNT 0 14 OTG_HORZ_COUNT 16 30 mmOTG1_OTG_NOM_VERT_POSITION 0 0x1bcb 1 0 2 OTG_VERT_COUNT_NOM 0 14 mmOTG1_OTG_STATUS_FRAME_COUNT 0 0x1bcc 1 0 2 OTG_FRAME_COUNT 0 23 mmOTG1_OTG_STATUS_VF_COUNT 0 0x1bcd 1 0 2 OTG_VF_COUNT 0 30 mmOTG1_OTG_STATUS_HV_COUNT 0 0x1bce 1 0 2 OTG_HV_COUNT 0 30 mmOTG1_OTG_COUNT_CONTROL 0 0x1bcf 2 0 2 OTG_HORZ_COUNT_BY2_EN 0 0 OTG_HORZ_REPETITION_COUNT 1 4 mmOTG1_OTG_COUNT_RESET 0 0x1bd0 1 0 2 OTG_RESET_FRAME_COUNT 0 0 mmOTG1_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE 0 0x1bd1 1 0 2 OTG_MANUAL_FORCE_VSYNC_NEXT_LINE 0 0 mmOTG1_OTG_VERT_SYNC_CONTROL 0 0x1bd2 3 0 2 OTG_FORCE_VSYNC_NEXT_LINE_OCCURRED 0 0 OTG_FORCE_VSYNC_NEXT_LINE_CLEAR 8 8 OTG_AUTO_FORCE_VSYNC_MODE 16 17 mmOTG1_OTG_STEREO_STATUS 0 0x1bd3 7 0 2 OTG_STEREO_CURRENT_EYE 0 0 OTG_STEREO_SYNC_OUTPUT 8 8 OTG_STEREO_SYNC_SELECT 16 16 OTG_STEREO_EYE_FLAG 20 20 OTG_STEREO_FORCE_NEXT_EYE_PENDING 24 25 OTG_CURRENT_3D_STRUCTURE_STATE 30 30 OTG_CURRENT_STEREOSYNC_EN_STATE 31 31 mmOTG1_OTG_STEREO_CONTROL 0 0x1bd4 7 0 2 OTG_STEREO_SYNC_OUTPUT_LINE_NUM 0 14 OTG_STEREO_SYNC_OUTPUT_POLARITY 15 15 OTG_STEREO_EYE_FLAG_POLARITY 17 17 OTG_DISABLE_STEREOSYNC_OUTPUT_FOR_DP 18 18 OTG_DISABLE_FIELD_NUM 19 19 OTG_DISABLE_V_BLANK_FOR_DP_FIX 20 20 OTG_STEREO_EN 24 24 mmOTG1_OTG_SNAPSHOT_STATUS 0 0x1bd5 3 0 2 OTG_SNAPSHOT_OCCURRED 0 0 OTG_SNAPSHOT_CLEAR 1 1 OTG_SNAPSHOT_MANUAL_TRIGGER 2 2 mmOTG1_OTG_SNAPSHOT_CONTROL 0 0x1bd6 1 0 2 OTG_AUTO_SNAPSHOT_TRIG_SEL 0 1 mmOTG1_OTG_SNAPSHOT_POSITION 0 0x1bd7 2 0 2 OTG_SNAPSHOT_VERT_COUNT 0 14 OTG_SNAPSHOT_HORZ_COUNT 16 30 mmOTG1_OTG_SNAPSHOT_FRAME 0 0x1bd8 1 0 2 OTG_SNAPSHOT_FRAME_COUNT 0 23 mmOTG1_OTG_INTERRUPT_CONTROL 0 0x1bd9 14 0 2 OTG_SNAPSHOT_INT_MSK 0 0 OTG_SNAPSHOT_INT_TYPE 1 1 OTG_FORCE_COUNT_NOW_INT_MSK 8 8 OTG_FORCE_COUNT_NOW_INT_TYPE 9 9 OTG_FORCE_VSYNC_NEXT_LINE_INT_MSK 16 16 OTG_FORCE_VSYNC_NEXT_LINE_INT_TYPE 17 17 OTG_TRIGA_INT_MSK 24 24 OTG_TRIGB_INT_MSK 25 25 OTG_TRIGA_INT_TYPE 26 26 OTG_TRIGB_INT_TYPE 27 27 OTG_VSYNC_NOM_INT_MSK 28 28 OTG_VSYNC_NOM_INT_TYPE 29 29 OTG_GSL_VSYNC_GAP_INT_MSK 30 30 OTG_GSL_VSYNC_GAP_INT_TYPE 31 31 mmOTG1_OTG_UPDATE_LOCK 0 0x1bda 1 0 2 OTG_UPDATE_LOCK 0 0 mmOTG1_OTG_DOUBLE_BUFFER_CONTROL 0 0x1bdb 10 0 2 OTG_UPDATE_PENDING 0 0 OTG_H_TIMING_DIV_BY2_DB_UPDATE_PENDING 2 2 OTG_BLANK_DATA_EN_UPDATE_PENDING 3 3 OTG_RANGE_TIMING_DBUF_UPDATE_PENDING 4 4 OTG_TIMING_DB_UPDATE_PENDING 5 5 OTG_3D_CTRL_DB_UPDATE_PENDING 6 6 OTG_3D_STRUCTURE_EN_DB_UPDATE_PENDING 7 7 OTG_UPDATE_INSTANTLY 8 8 OTG_BLANK_DATA_DOUBLE_BUFFER_EN 16 16 OTG_RANGE_TIMING_DBUF_UPDATE_MODE 24 25 mmOTG1_OTG_TEST_PATTERN_CONTROL 0 0x1bdc 4 0 2 OTG_TEST_PATTERN_EN 0 0 OTG_TEST_PATTERN_MODE 8 10 OTG_TEST_PATTERN_DYNAMIC_RANGE 16 16 OTG_TEST_PATTERN_COLOR_FORMAT 24 31 mmOTG1_OTG_TEST_PATTERN_PARAMETERS 0 0x1bdd 5 0 2 OTG_TEST_PATTERN_INC0 0 3 OTG_TEST_PATTERN_INC1 4 7 OTG_TEST_PATTERN_VRES 8 11 OTG_TEST_PATTERN_HRES 12 15 OTG_TEST_PATTERN_RAMP0_OFFSET 16 31 mmOTG1_OTG_TEST_PATTERN_COLOR 0 0x1bde 2 0 2 OTG_TEST_PATTERN_DATA 0 15 OTG_TEST_PATTERN_MASK 16 21 mmOTG1_OTG_MASTER_EN 0 0x1bdf 1 0 2 OTG_MASTER_EN 0 0 mmOTG1_OTG_BLANK_DATA_COLOR 0 0x1be1 3 0 2 OTG_BLANK_DATA_COLOR_BLUE_CB 0 9 OTG_BLANK_DATA_COLOR_GREEN_Y 10 19 OTG_BLANK_DATA_COLOR_RED_CR 20 29 mmOTG1_OTG_BLANK_DATA_COLOR_EXT 0 0x1be2 3 0 2 OTG_BLANK_DATA_COLOR_BLUE_CB_EXT 0 5 OTG_BLANK_DATA_COLOR_GREEN_Y_EXT 8 13 OTG_BLANK_DATA_COLOR_RED_CR_EXT 16 21 mmOTG1_OTG_BLACK_COLOR 0 0x1be3 3 0 2 OTG_BLACK_COLOR_B_CB 0 9 OTG_BLACK_COLOR_G_Y 10 19 OTG_BLACK_COLOR_R_CR 20 29 mmOTG1_OTG_BLACK_COLOR_EXT 0 0x1be4 3 0 2 OTG_BLACK_COLOR_B_CB_EXT 0 5 OTG_BLACK_COLOR_G_Y_EXT 8 13 OTG_BLACK_COLOR_R_CR_EXT 16 21 mmOTG1_OTG_VERTICAL_INTERRUPT0_POSITION 0 0x1be5 2 0 2 OTG_VERTICAL_INTERRUPT0_LINE_START 0 14 OTG_VERTICAL_INTERRUPT0_LINE_END 16 30 mmOTG1_OTG_VERTICAL_INTERRUPT0_CONTROL 0 0x1be6 6 0 2 OTG_VERTICAL_INTERRUPT0_OUTPUT_POLARITY 4 4 OTG_VERTICAL_INTERRUPT0_INT_ENABLE 8 8 OTG_VERTICAL_INTERRUPT0_STATUS 12 12 OTG_VERTICAL_INTERRUPT0_INT_STATUS 16 16 OTG_VERTICAL_INTERRUPT0_CLEAR 20 20 OTG_VERTICAL_INTERRUPT0_INT_TYPE 24 24 mmOTG1_OTG_VERTICAL_INTERRUPT1_POSITION 0 0x1be7 1 0 2 OTG_VERTICAL_INTERRUPT1_LINE_START 0 14 mmOTG1_OTG_VERTICAL_INTERRUPT1_CONTROL 0 0x1be8 5 0 2 OTG_VERTICAL_INTERRUPT1_INT_ENABLE 8 8 OTG_VERTICAL_INTERRUPT1_STATUS 12 12 OTG_VERTICAL_INTERRUPT1_INT_STATUS 16 16 OTG_VERTICAL_INTERRUPT1_CLEAR 20 20 OTG_VERTICAL_INTERRUPT1_INT_TYPE 24 24 mmOTG1_OTG_VERTICAL_INTERRUPT2_POSITION 0 0x1be9 1 0 2 OTG_VERTICAL_INTERRUPT2_LINE_START 0 14 mmOTG1_OTG_VERTICAL_INTERRUPT2_CONTROL 0 0x1bea 5 0 2 OTG_VERTICAL_INTERRUPT2_INT_ENABLE 8 8 OTG_VERTICAL_INTERRUPT2_STATUS 12 12 OTG_VERTICAL_INTERRUPT2_INT_STATUS 16 16 OTG_VERTICAL_INTERRUPT2_CLEAR 20 20 OTG_VERTICAL_INTERRUPT2_INT_TYPE 24 24 mmOTG1_OTG_CRC_CNTL 0 0x1beb 16 0 2 OTG_CRC_EN 0 0 OTG_CRC_DUAL_LINK_EN 1 1 OTG_CRC_DUAL_LINK_MODE 2 2 OTG_CRC_BLANK_ONLY 3 3 OTG_CRC_CONT_EN 4 4 OTG_CRC_CAPTURE_START_SEL 5 6 OTG_CRC_STEREO_MODE 8 9 OTG_CRC_INTERLACE_MODE 12 13 OTG_CRC_MULTI_STREAM_MODE 16 18 OTG_CRC_USE_NEW_AND_REPEATED_PIXELS 19 19 OTG_CRC0_SELECT 20 22 OTG_CRC1_SELECT 24 26 OTG_ONE_SHOT_CRC0_PENDING 28 28 OTG_ONE_SHOT_CRC1_PENDING 29 29 OTG_ONE_SHOT_CRC2_PENDING 30 30 OTG_ONE_SHOT_CRC3_PENDING 31 31 mmOTG1_OTG_CRC0_WINDOWA_X_CONTROL 0 0x1bec 2 0 2 OTG_CRC0_WINDOWA_X_START 0 14 OTG_CRC0_WINDOWA_X_END 16 30 mmOTG1_OTG_CRC0_WINDOWA_Y_CONTROL 0 0x1bed 2 0 2 OTG_CRC0_WINDOWA_Y_START 0 14 OTG_CRC0_WINDOWA_Y_END 16 30 mmOTG1_OTG_CRC0_WINDOWB_X_CONTROL 0 0x1bee 2 0 2 OTG_CRC0_WINDOWB_X_START 0 14 OTG_CRC0_WINDOWB_X_END 16 30 mmOTG1_OTG_CRC0_WINDOWB_Y_CONTROL 0 0x1bef 2 0 2 OTG_CRC0_WINDOWB_Y_START 0 14 OTG_CRC0_WINDOWB_Y_END 16 30 mmOTG1_OTG_CRC0_DATA_RG 0 0x1bf0 2 0 2 CRC0_R_CR 0 15 CRC0_G_Y 16 31 mmOTG1_OTG_CRC0_DATA_B 0 0x1bf1 2 0 2 CRC0_B_CB 0 15 CRC0_C 16 31 mmOTG1_OTG_CRC1_WINDOWA_X_CONTROL 0 0x1bf2 2 0 2 OTG_CRC1_WINDOWA_X_START 0 14 OTG_CRC1_WINDOWA_X_END 16 30 mmOTG1_OTG_CRC1_WINDOWA_Y_CONTROL 0 0x1bf3 2 0 2 OTG_CRC1_WINDOWA_Y_START 0 14 OTG_CRC1_WINDOWA_Y_END 16 30 mmOTG1_OTG_CRC1_WINDOWB_X_CONTROL 0 0x1bf4 2 0 2 OTG_CRC1_WINDOWB_X_START 0 14 OTG_CRC1_WINDOWB_X_END 16 30 mmOTG1_OTG_CRC1_WINDOWB_Y_CONTROL 0 0x1bf5 2 0 2 OTG_CRC1_WINDOWB_Y_START 0 14 OTG_CRC1_WINDOWB_Y_END 16 30 mmOTG1_OTG_CRC1_DATA_RG 0 0x1bf6 2 0 2 CRC1_R_CR 0 15 CRC1_G_Y 16 31 mmOTG1_OTG_CRC1_DATA_B 0 0x1bf7 2 0 2 CRC1_B_CB 0 15 CRC1_C 16 31 mmOTG1_OTG_CRC2_DATA_RG 0 0x1bf8 2 0 2 CRC2_R_CR 0 15 CRC2_G_Y 16 31 mmOTG1_OTG_CRC2_DATA_B 0 0x1bf9 2 0 2 CRC2_B_CB 0 15 CRC2_C 16 31 mmOTG1_OTG_CRC3_DATA_RG 0 0x1bfa 2 0 2 CRC3_R_CR 0 15 CRC3_G_Y 16 31 mmOTG1_OTG_CRC3_DATA_B 0 0x1bfb 2 0 2 CRC3_B_CB 0 15 CRC3_C 16 31 mmOTG1_OTG_CRC_SIG_RED_GREEN_MASK 0 0x1bfc 2 0 2 OTG_CRC_SIG_RED_MASK 0 15 OTG_CRC_SIG_GREEN_MASK 16 31 mmOTG1_OTG_CRC_SIG_BLUE_CONTROL_MASK 0 0x1bfd 2 0 2 OTG_CRC_SIG_BLUE_MASK 0 15 OTG_CRC_SIG_CONTROL_MASK 16 31 mmOTG1_OTG_STATIC_SCREEN_CONTROL 0 0x1c04 9 0 2 OTG_STATIC_SCREEN_EVENT_MASK 0 15 OTG_STATIC_SCREEN_FRAME_COUNT 16 23 OTG_CPU_SS_INT_ENABLE 24 24 OTG_SS_STATUS 25 25 OTG_CPU_SS_INT_STATUS 26 26 OTG_CPU_SS_INT_CLEAR 27 27 OTG_CPU_SS_INT_TYPE 28 28 OTG_STATIC_SCREEN_OVERRIDE 30 30 OTG_STATIC_SCREEN_OVERRIDE_VALUE 31 31 mmOTG1_OTG_3D_STRUCTURE_CONTROL 0 0x1c05 6 0 2 OTG_3D_STRUCTURE_EN 0 0 OTG_3D_STRUCTURE_V_UPDATE_MODE 8 9 OTG_3D_STRUCTURE_STEREO_SEL_OVR 12 12 OTG_3D_STRUCTURE_F_COUNT_RESET 16 16 OTG_3D_STRUCTURE_F_COUNT_RESET_PENDING 17 17 OTG_3D_STRUCTURE_F_COUNT 18 19 mmOTG1_OTG_GSL_VSYNC_GAP 0 0x1c06 8 0 2 OTG_GSL_VSYNC_GAP_LIMIT 0 7 OTG_GSL_VSYNC_GAP_DELAY 8 15 OTG_GSL_VSYNC_GAP_SOURCE_SEL 16 16 OTG_GSL_VSYNC_GAP_MODE 17 18 OTG_GSL_VSYNC_GAP_CLEAR 19 19 OTG_GSL_VSYNC_GAP_OCCURRED 20 20 OTG_GSL_VSYNC_GAP_MASTER_FASTER 23 23 OTG_GSL_VSYNC_GAP 24 31 mmOTG1_OTG_MASTER_UPDATE_MODE 0 0x1c07 1 0 2 MASTER_UPDATE_INTERLACED_MODE 0 1 mmOTG1_OTG_CLOCK_CONTROL 0 0x1c08 5 0 2 OTG_CLOCK_EN 0 0 OTG_CLOCK_GATE_DIS 1 1 OTG_SOFT_RESET 4 4 OTG_CLOCK_ON 8 8 OTG_BUSY 16 16 mmOTG1_OTG_VSTARTUP_PARAM 0 0x1c09 1 0 2 VSTARTUP_START 0 9 mmOTG1_OTG_VUPDATE_PARAM 0 0x1c0a 2 0 2 VUPDATE_OFFSET 0 15 VUPDATE_WIDTH 16 25 mmOTG1_OTG_VREADY_PARAM 0 0x1c0b 1 0 2 VREADY_OFFSET 0 15 mmOTG1_OTG_GLOBAL_SYNC_STATUS 0 0x1c0c 25 0 2 VSTARTUP_INT_EN 0 0 VSTARTUP_INT_TYPE 1 1 VSTARTUP_EVENT_OCCURRED 2 2 VSTARTUP_INT_STATUS 3 3 VSTARTUP_EVENT_CLEAR 4 4 VUPDATE_INT_EN 5 5 VUPDATE_INT_TYPE 6 6 VUPDATE_INT_POSITION_SEL 7 7 VUPDATE_EVENT_OCCURRED 8 8 VUPDATE_INT_STATUS 9 9 VUPDATE_EVENT_CLEAR 10 10 VUPDATE_STATUS 11 11 VUPDATE_NO_LOCK_INT_EN 12 12 VUPDATE_NO_LOCK_INT_TYPE 13 13 VUPDATE_NO_LOCK_EVENT_OCCURRED 14 14 VUPDATE_NO_LOCK_INT_STATUS 15 15 VUPDATE_NO_LOCK_EVENT_CLEAR 16 16 VUPDATE_NO_LOCK_STATUS 17 17 VREADY_INT_EN 18 18 VREADY_INT_TYPE 19 19 VREADY_EVENT_OCCURRED 20 20 VREADY_INT_STATUS 21 21 VREADY_EVENT_CLEAR 22 22 STEREO_SELECT_STATUS 24 24 FIELD_NUMBER_STATUS 25 25 mmOTG1_OTG_MASTER_UPDATE_LOCK 0 0x1c0d 2 0 2 OTG_MASTER_UPDATE_LOCK 0 0 UPDATE_LOCK_STATUS 8 8 mmOTG1_OTG_GSL_CONTROL 0 0x1c0e 6 0 2 OTG_GSL0_EN 0 0 OTG_GSL1_EN 1 1 OTG_GSL2_EN 2 2 OTG_GSL_MASTER_EN 3 3 OTG_GSL_FORCE_DELAY 16 20 OTG_GSL_CHECK_ALL_FIELDS 28 28 mmOTG1_OTG_GSL_WINDOW_X 0 0x1c0f 2 0 2 OTG_GSL_WINDOW_START_X 0 14 OTG_GSL_WINDOW_END_X 16 30 mmOTG1_OTG_GSL_WINDOW_Y 0 0x1c10 2 0 2 OTG_GSL_WINDOW_START_Y 0 14 OTG_GSL_WINDOW_END_Y 16 30 mmOTG1_OTG_VUPDATE_KEEPOUT 0 0x1c11 3 0 2 MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_START_OFFSET 0 15 MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_END_OFFSET 16 25 OTG_MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_EN 31 31 mmOTG1_OTG_GLOBAL_CONTROL0 0 0x1c12 3 0 2 OTG_MASTER_UPDATE_LOCK_HTOTAL_KEEPOUT 0 7 OTG_MASTER_UPDATE_LOCK_HTOTAL_KEEPOUT_EN 8 8 OTG_MASTER_UPDATE_LOCK_SEL 25 27 mmOTG1_OTG_GLOBAL_CONTROL1 0 0x1c13 3 0 2 MASTER_UPDATE_LOCK_DB_X 0 14 MASTER_UPDATE_LOCK_DB_Y 16 30 MASTER_UPDATE_LOCK_DB_EN 31 31 mmOTG1_OTG_GLOBAL_CONTROL2 0 0x1c14 4 0 2 DIG_UPDATE_LOCATION 0 9 GLOBAL_UPDATE_LOCK_EN 10 10 MANUAL_FLOW_CONTROL_SEL 16 18 DCCG_VUPDATE_MODE 31 31 mmOTG1_OTG_GLOBAL_CONTROL3 0 0x1c15 3 0 2 MASTER_UPDATE_LOCK_DB_FIELD 0 1 MASTER_UPDATE_LOCK_DB_STEREO_SEL 4 5 MASTER_UPDATE_LOCK_DB_FIELD_STEREO_FLAG_SEL 8 8 mmOTG1_OTG_TRIG_MANUAL_CONTROL 0 0x1c16 1 0 2 TRIG_MANUAL_CONTROL 0 0 mmOTG1_OTG_MANUAL_FLOW_CONTROL 0 0x1c17 1 0 2 MANUAL_FLOW_CONTROL 0 0 mmOTG1_OTG_RANGE_TIMING_INT_STATUS 0 0x1c18 5 0 2 OTG_RANGE_TIMING_UPDATE_OCCURRED 0 0 OTG_RANGE_TIMING_UPDATE_OCCURRED_INT 4 4 OTG_RANGE_TIMING_UPDATE_OCCURRED_CLEAR 8 8 OTG_RANGE_TIMING_UPDATE_OCCURRED_INT_MSK 12 12 OTG_RANGE_TIMING_UPDATE_OCCURRED_INT_TYPE 16 16 mmOTG1_OTG_DRR_CONTROL 0 0x1c19 2 0 2 OTG_DRR_AVERAGE_FRAME 0 2 OTG_V_TOTAL_LAST_USED_BY_DRR 16 30 mmOTG1_OTG_REQUEST_CONTROL 0 0x1c1a 1 0 2 OTG_REQUEST_MODE_FOR_H_DUPLICATE 0 0 mmOTG1_OTG_SPARE_REGISTER 0 0x1c1b 1 0 2 OTG_SPARE_REG 0 31 mmOTG2_OTG_H_TOTAL 0 0x1c2a 1 0 2 OTG_H_TOTAL 0 14 mmOTG2_OTG_H_BLANK_START_END 0 0x1c2b 2 0 2 OTG_H_BLANK_START 0 14 OTG_H_BLANK_END 16 30 mmOTG2_OTG_H_SYNC_A 0 0x1c2c 2 0 2 OTG_H_SYNC_A_START 0 14 OTG_H_SYNC_A_END 16 30 mmOTG2_OTG_H_SYNC_A_CNTL 0 0x1c2d 3 0 2 OTG_H_SYNC_A_POL 0 0 OTG_COMP_SYNC_A_EN 16 16 OTG_H_SYNC_A_CUTOFF 17 17 mmOTG2_OTG_H_TIMING_CNTL 0 0x1c2e 2 0 2 OTG_H_TIMING_DIV_BY2 0 0 OTG_H_TIMING_DIV_BY2_UPDATE_MODE 8 8 mmOTG2_OTG_V_TOTAL 0 0x1c2f 1 0 2 OTG_V_TOTAL 0 14 mmOTG2_OTG_V_TOTAL_MIN 0 0x1c30 1 0 2 OTG_V_TOTAL_MIN 0 14 mmOTG2_OTG_V_TOTAL_MAX 0 0x1c31 1 0 2 OTG_V_TOTAL_MAX 0 14 mmOTG2_OTG_V_TOTAL_MID 0 0x1c32 1 0 2 OTG_V_TOTAL_MID 0 14 mmOTG2_OTG_V_TOTAL_CONTROL 0 0x1c33 8 0 2 OTG_V_TOTAL_MIN_SEL 0 0 OTG_V_TOTAL_MAX_SEL 1 1 OTG_VTOTAL_MID_REPLACING_MAX_EN 2 2 OTG_VTOTAL_MID_REPLACING_MIN_EN 3 3 OTG_FORCE_LOCK_ON_EVENT 4 4 OTG_SET_V_TOTAL_MIN_MASK_EN 7 7 OTG_VTOTAL_MID_FRAME_NUM 8 15 OTG_SET_V_TOTAL_MIN_MASK 16 31 mmOTG2_OTG_V_TOTAL_INT_STATUS 0 0x1c34 4 0 2 OTG_SET_V_TOTAL_MIN_EVENT_OCCURED 0 0 OTG_SET_V_TOTAL_MIN_EVENT_OCCURED_INT 4 4 OTG_SET_V_TOTAL_MIN_EVENT_OCCURED_ACK 8 8 OTG_SET_V_TOTAL_MIN_EVENT_OCCURED_MSK 12 12 mmOTG2_OTG_VSYNC_NOM_INT_STATUS 0 0x1c35 2 0 2 OTG_VSYNC_NOM 0 0 OTG_VSYNC_NOM_INT_CLEAR 4 4 mmOTG2_OTG_V_BLANK_START_END 0 0x1c36 2 0 2 OTG_V_BLANK_START 0 14 OTG_V_BLANK_END 16 30 mmOTG2_OTG_V_SYNC_A 0 0x1c37 2 0 2 OTG_V_SYNC_A_START 0 14 OTG_V_SYNC_A_END 16 30 mmOTG2_OTG_V_SYNC_A_CNTL 0 0x1c38 1 0 2 OTG_V_SYNC_A_POL 0 0 mmOTG2_OTG_TRIGA_CNTL 0 0x1c39 12 0 2 OTG_TRIGA_SOURCE_SELECT 0 4 OTG_TRIGA_SOURCE_PIPE_SELECT 5 7 OTG_TRIGA_POLARITY_SELECT 8 10 OTG_TRIGA_RESYNC_BYPASS_EN 11 11 OTG_TRIGA_INPUT_STATUS 12 12 OTG_TRIGA_POLARITY_STATUS 13 13 OTG_TRIGA_OCCURRED 14 14 OTG_TRIGA_RISING_EDGE_DETECT_CNTL 16 17 OTG_TRIGA_FALLING_EDGE_DETECT_CNTL 18 19 OTG_TRIGA_FREQUENCY_SELECT 20 21 OTG_TRIGA_DELAY 24 28 OTG_TRIGA_CLEAR 31 31 mmOTG2_OTG_TRIGA_MANUAL_TRIG 0 0x1c3a 1 0 2 OTG_TRIGA_MANUAL_TRIG 0 0 mmOTG2_OTG_TRIGB_CNTL 0 0x1c3b 12 0 2 OTG_TRIGB_SOURCE_SELECT 0 4 OTG_TRIGB_SOURCE_PIPE_SELECT 5 7 OTG_TRIGB_POLARITY_SELECT 8 10 OTG_TRIGB_RESYNC_BYPASS_EN 11 11 OTG_TRIGB_INPUT_STATUS 12 12 OTG_TRIGB_POLARITY_STATUS 13 13 OTG_TRIGB_OCCURRED 14 14 OTG_TRIGB_RISING_EDGE_DETECT_CNTL 16 17 OTG_TRIGB_FALLING_EDGE_DETECT_CNTL 18 19 OTG_TRIGB_FREQUENCY_SELECT 20 21 OTG_TRIGB_DELAY 24 28 OTG_TRIGB_CLEAR 31 31 mmOTG2_OTG_TRIGB_MANUAL_TRIG 0 0x1c3c 1 0 2 OTG_TRIGB_MANUAL_TRIG 0 0 mmOTG2_OTG_FORCE_COUNT_NOW_CNTL 0 0x1c3d 5 0 2 OTG_FORCE_COUNT_NOW_MODE 0 1 OTG_FORCE_COUNT_NOW_CHECK 4 4 OTG_FORCE_COUNT_NOW_TRIG_SEL 8 8 OTG_FORCE_COUNT_NOW_OCCURRED 16 16 OTG_FORCE_COUNT_NOW_CLEAR 24 24 mmOTG2_OTG_FLOW_CONTROL 0 0x1c3e 4 0 2 OTG_FLOW_CONTROL_SOURCE_SELECT 0 4 OTG_FLOW_CONTROL_POLARITY 8 8 OTG_FLOW_CONTROL_GRANULARITY 16 16 OTG_FLOW_CONTROL_INPUT_STATUS 24 24 mmOTG2_OTG_STEREO_FORCE_NEXT_EYE 0 0x1c3f 3 0 2 OTG_STEREO_FORCE_NEXT_EYE 0 1 OTG_AVSYNC_FRAME_COUNTER 8 15 OTG_AVSYNC_LINE_COUNTER 16 28 mmOTG2_OTG_AVSYNC_COUNTER 0 0x1c40 1 0 2 OTG_AVSYNC_COUNTER 0 31 mmOTG2_OTG_CONTROL 0 0x1c41 6 0 2 OTG_MASTER_EN 0 0 OTG_DISABLE_POINT_CNTL 8 9 OTG_START_POINT_CNTL 12 12 OTG_FIELD_NUMBER_CNTL 13 13 OTG_FIELD_NUMBER_POLARITY 14 14 OTG_CURRENT_MASTER_EN_STATE 16 16 mmOTG2_OTG_BLANK_CONTROL 0 0x1c42 3 0 2 OTG_CURRENT_BLANK_STATE 0 0 OTG_BLANK_DATA_EN 8 8 OTG_BLANK_DE_MODE 16 16 mmOTG2_OTG_PIPE_ABORT_CONTROL 0 0x1c43 2 0 2 OTG_PIPE_ABORT 0 0 OTG_PIPE_ABORT_DONE 8 8 mmOTG2_OTG_INTERLACE_CONTROL 0 0x1c44 2 0 2 OTG_INTERLACE_ENABLE 0 0 OTG_INTERLACE_FORCE_NEXT_FIELD 16 17 mmOTG2_OTG_INTERLACE_STATUS 0 0x1c45 2 0 2 OTG_INTERLACE_CURRENT_FIELD 0 0 OTG_INTERLACE_NEXT_FIELD 1 1 mmOTG2_OTG_FIELD_INDICATION_CONTROL 0 0x1c46 2 0 2 OTG_FIELD_INDICATION_OUTPUT_POLARITY 0 0 OTG_FIELD_ALIGNMENT 1 1 mmOTG2_OTG_PIXEL_DATA_READBACK0 0 0x1c47 2 0 2 OTG_PIXEL_DATA_BLUE_CB 0 15 OTG_PIXEL_DATA_GREEN_Y 16 31 mmOTG2_OTG_PIXEL_DATA_READBACK1 0 0x1c48 1 0 2 OTG_PIXEL_DATA_RED_CR 0 15 mmOTG2_OTG_STATUS 0 0x1c49 8 0 2 OTG_V_BLANK 0 0 OTG_V_ACTIVE_DISP 1 1 OTG_V_SYNC_A 2 2 OTG_V_UPDATE 3 3 OTG_V_BLANK_3D_STRUCTURE 5 5 OTG_H_BLANK 16 16 OTG_H_ACTIVE_DISP 17 17 OTG_H_SYNC_A 18 18 mmOTG2_OTG_STATUS_POSITION 0 0x1c4a 2 0 2 OTG_VERT_COUNT 0 14 OTG_HORZ_COUNT 16 30 mmOTG2_OTG_NOM_VERT_POSITION 0 0x1c4b 1 0 2 OTG_VERT_COUNT_NOM 0 14 mmOTG2_OTG_STATUS_FRAME_COUNT 0 0x1c4c 1 0 2 OTG_FRAME_COUNT 0 23 mmOTG2_OTG_STATUS_VF_COUNT 0 0x1c4d 1 0 2 OTG_VF_COUNT 0 30 mmOTG2_OTG_STATUS_HV_COUNT 0 0x1c4e 1 0 2 OTG_HV_COUNT 0 30 mmOTG2_OTG_COUNT_CONTROL 0 0x1c4f 2 0 2 OTG_HORZ_COUNT_BY2_EN 0 0 OTG_HORZ_REPETITION_COUNT 1 4 mmOTG2_OTG_COUNT_RESET 0 0x1c50 1 0 2 OTG_RESET_FRAME_COUNT 0 0 mmOTG2_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE 0 0x1c51 1 0 2 OTG_MANUAL_FORCE_VSYNC_NEXT_LINE 0 0 mmOTG2_OTG_VERT_SYNC_CONTROL 0 0x1c52 3 0 2 OTG_FORCE_VSYNC_NEXT_LINE_OCCURRED 0 0 OTG_FORCE_VSYNC_NEXT_LINE_CLEAR 8 8 OTG_AUTO_FORCE_VSYNC_MODE 16 17 mmOTG2_OTG_STEREO_STATUS 0 0x1c53 7 0 2 OTG_STEREO_CURRENT_EYE 0 0 OTG_STEREO_SYNC_OUTPUT 8 8 OTG_STEREO_SYNC_SELECT 16 16 OTG_STEREO_EYE_FLAG 20 20 OTG_STEREO_FORCE_NEXT_EYE_PENDING 24 25 OTG_CURRENT_3D_STRUCTURE_STATE 30 30 OTG_CURRENT_STEREOSYNC_EN_STATE 31 31 mmOTG2_OTG_STEREO_CONTROL 0 0x1c54 7 0 2 OTG_STEREO_SYNC_OUTPUT_LINE_NUM 0 14 OTG_STEREO_SYNC_OUTPUT_POLARITY 15 15 OTG_STEREO_EYE_FLAG_POLARITY 17 17 OTG_DISABLE_STEREOSYNC_OUTPUT_FOR_DP 18 18 OTG_DISABLE_FIELD_NUM 19 19 OTG_DISABLE_V_BLANK_FOR_DP_FIX 20 20 OTG_STEREO_EN 24 24 mmOTG2_OTG_SNAPSHOT_STATUS 0 0x1c55 3 0 2 OTG_SNAPSHOT_OCCURRED 0 0 OTG_SNAPSHOT_CLEAR 1 1 OTG_SNAPSHOT_MANUAL_TRIGGER 2 2 mmOTG2_OTG_SNAPSHOT_CONTROL 0 0x1c56 1 0 2 OTG_AUTO_SNAPSHOT_TRIG_SEL 0 1 mmOTG2_OTG_SNAPSHOT_POSITION 0 0x1c57 2 0 2 OTG_SNAPSHOT_VERT_COUNT 0 14 OTG_SNAPSHOT_HORZ_COUNT 16 30 mmOTG2_OTG_SNAPSHOT_FRAME 0 0x1c58 1 0 2 OTG_SNAPSHOT_FRAME_COUNT 0 23 mmOTG2_OTG_INTERRUPT_CONTROL 0 0x1c59 14 0 2 OTG_SNAPSHOT_INT_MSK 0 0 OTG_SNAPSHOT_INT_TYPE 1 1 OTG_FORCE_COUNT_NOW_INT_MSK 8 8 OTG_FORCE_COUNT_NOW_INT_TYPE 9 9 OTG_FORCE_VSYNC_NEXT_LINE_INT_MSK 16 16 OTG_FORCE_VSYNC_NEXT_LINE_INT_TYPE 17 17 OTG_TRIGA_INT_MSK 24 24 OTG_TRIGB_INT_MSK 25 25 OTG_TRIGA_INT_TYPE 26 26 OTG_TRIGB_INT_TYPE 27 27 OTG_VSYNC_NOM_INT_MSK 28 28 OTG_VSYNC_NOM_INT_TYPE 29 29 OTG_GSL_VSYNC_GAP_INT_MSK 30 30 OTG_GSL_VSYNC_GAP_INT_TYPE 31 31 mmOTG2_OTG_UPDATE_LOCK 0 0x1c5a 1 0 2 OTG_UPDATE_LOCK 0 0 mmOTG2_OTG_DOUBLE_BUFFER_CONTROL 0 0x1c5b 10 0 2 OTG_UPDATE_PENDING 0 0 OTG_H_TIMING_DIV_BY2_DB_UPDATE_PENDING 2 2 OTG_BLANK_DATA_EN_UPDATE_PENDING 3 3 OTG_RANGE_TIMING_DBUF_UPDATE_PENDING 4 4 OTG_TIMING_DB_UPDATE_PENDING 5 5 OTG_3D_CTRL_DB_UPDATE_PENDING 6 6 OTG_3D_STRUCTURE_EN_DB_UPDATE_PENDING 7 7 OTG_UPDATE_INSTANTLY 8 8 OTG_BLANK_DATA_DOUBLE_BUFFER_EN 16 16 OTG_RANGE_TIMING_DBUF_UPDATE_MODE 24 25 mmOTG2_OTG_TEST_PATTERN_CONTROL 0 0x1c5c 4 0 2 OTG_TEST_PATTERN_EN 0 0 OTG_TEST_PATTERN_MODE 8 10 OTG_TEST_PATTERN_DYNAMIC_RANGE 16 16 OTG_TEST_PATTERN_COLOR_FORMAT 24 31 mmOTG2_OTG_TEST_PATTERN_PARAMETERS 0 0x1c5d 5 0 2 OTG_TEST_PATTERN_INC0 0 3 OTG_TEST_PATTERN_INC1 4 7 OTG_TEST_PATTERN_VRES 8 11 OTG_TEST_PATTERN_HRES 12 15 OTG_TEST_PATTERN_RAMP0_OFFSET 16 31 mmOTG2_OTG_TEST_PATTERN_COLOR 0 0x1c5e 2 0 2 OTG_TEST_PATTERN_DATA 0 15 OTG_TEST_PATTERN_MASK 16 21 mmOTG2_OTG_MASTER_EN 0 0x1c5f 1 0 2 OTG_MASTER_EN 0 0 mmOTG2_OTG_BLANK_DATA_COLOR 0 0x1c61 3 0 2 OTG_BLANK_DATA_COLOR_BLUE_CB 0 9 OTG_BLANK_DATA_COLOR_GREEN_Y 10 19 OTG_BLANK_DATA_COLOR_RED_CR 20 29 mmOTG2_OTG_BLANK_DATA_COLOR_EXT 0 0x1c62 3 0 2 OTG_BLANK_DATA_COLOR_BLUE_CB_EXT 0 5 OTG_BLANK_DATA_COLOR_GREEN_Y_EXT 8 13 OTG_BLANK_DATA_COLOR_RED_CR_EXT 16 21 mmOTG2_OTG_BLACK_COLOR 0 0x1c63 3 0 2 OTG_BLACK_COLOR_B_CB 0 9 OTG_BLACK_COLOR_G_Y 10 19 OTG_BLACK_COLOR_R_CR 20 29 mmOTG2_OTG_BLACK_COLOR_EXT 0 0x1c64 3 0 2 OTG_BLACK_COLOR_B_CB_EXT 0 5 OTG_BLACK_COLOR_G_Y_EXT 8 13 OTG_BLACK_COLOR_R_CR_EXT 16 21 mmOTG2_OTG_VERTICAL_INTERRUPT0_POSITION 0 0x1c65 2 0 2 OTG_VERTICAL_INTERRUPT0_LINE_START 0 14 OTG_VERTICAL_INTERRUPT0_LINE_END 16 30 mmOTG2_OTG_VERTICAL_INTERRUPT0_CONTROL 0 0x1c66 6 0 2 OTG_VERTICAL_INTERRUPT0_OUTPUT_POLARITY 4 4 OTG_VERTICAL_INTERRUPT0_INT_ENABLE 8 8 OTG_VERTICAL_INTERRUPT0_STATUS 12 12 OTG_VERTICAL_INTERRUPT0_INT_STATUS 16 16 OTG_VERTICAL_INTERRUPT0_CLEAR 20 20 OTG_VERTICAL_INTERRUPT0_INT_TYPE 24 24 mmOTG2_OTG_VERTICAL_INTERRUPT1_POSITION 0 0x1c67 1 0 2 OTG_VERTICAL_INTERRUPT1_LINE_START 0 14 mmOTG2_OTG_VERTICAL_INTERRUPT1_CONTROL 0 0x1c68 5 0 2 OTG_VERTICAL_INTERRUPT1_INT_ENABLE 8 8 OTG_VERTICAL_INTERRUPT1_STATUS 12 12 OTG_VERTICAL_INTERRUPT1_INT_STATUS 16 16 OTG_VERTICAL_INTERRUPT1_CLEAR 20 20 OTG_VERTICAL_INTERRUPT1_INT_TYPE 24 24 mmOTG2_OTG_VERTICAL_INTERRUPT2_POSITION 0 0x1c69 1 0 2 OTG_VERTICAL_INTERRUPT2_LINE_START 0 14 mmOTG2_OTG_VERTICAL_INTERRUPT2_CONTROL 0 0x1c6a 5 0 2 OTG_VERTICAL_INTERRUPT2_INT_ENABLE 8 8 OTG_VERTICAL_INTERRUPT2_STATUS 12 12 OTG_VERTICAL_INTERRUPT2_INT_STATUS 16 16 OTG_VERTICAL_INTERRUPT2_CLEAR 20 20 OTG_VERTICAL_INTERRUPT2_INT_TYPE 24 24 mmOTG2_OTG_CRC_CNTL 0 0x1c6b 16 0 2 OTG_CRC_EN 0 0 OTG_CRC_DUAL_LINK_EN 1 1 OTG_CRC_DUAL_LINK_MODE 2 2 OTG_CRC_BLANK_ONLY 3 3 OTG_CRC_CONT_EN 4 4 OTG_CRC_CAPTURE_START_SEL 5 6 OTG_CRC_STEREO_MODE 8 9 OTG_CRC_INTERLACE_MODE 12 13 OTG_CRC_MULTI_STREAM_MODE 16 18 OTG_CRC_USE_NEW_AND_REPEATED_PIXELS 19 19 OTG_CRC0_SELECT 20 22 OTG_CRC1_SELECT 24 26 OTG_ONE_SHOT_CRC0_PENDING 28 28 OTG_ONE_SHOT_CRC1_PENDING 29 29 OTG_ONE_SHOT_CRC2_PENDING 30 30 OTG_ONE_SHOT_CRC3_PENDING 31 31 mmOTG2_OTG_CRC0_WINDOWA_X_CONTROL 0 0x1c6c 2 0 2 OTG_CRC0_WINDOWA_X_START 0 14 OTG_CRC0_WINDOWA_X_END 16 30 mmOTG2_OTG_CRC0_WINDOWA_Y_CONTROL 0 0x1c6d 2 0 2 OTG_CRC0_WINDOWA_Y_START 0 14 OTG_CRC0_WINDOWA_Y_END 16 30 mmOTG2_OTG_CRC0_WINDOWB_X_CONTROL 0 0x1c6e 2 0 2 OTG_CRC0_WINDOWB_X_START 0 14 OTG_CRC0_WINDOWB_X_END 16 30 mmOTG2_OTG_CRC0_WINDOWB_Y_CONTROL 0 0x1c6f 2 0 2 OTG_CRC0_WINDOWB_Y_START 0 14 OTG_CRC0_WINDOWB_Y_END 16 30 mmOTG2_OTG_CRC0_DATA_RG 0 0x1c70 2 0 2 CRC0_R_CR 0 15 CRC0_G_Y 16 31 mmOTG2_OTG_CRC0_DATA_B 0 0x1c71 2 0 2 CRC0_B_CB 0 15 CRC0_C 16 31 mmOTG2_OTG_CRC1_WINDOWA_X_CONTROL 0 0x1c72 2 0 2 OTG_CRC1_WINDOWA_X_START 0 14 OTG_CRC1_WINDOWA_X_END 16 30 mmOTG2_OTG_CRC1_WINDOWA_Y_CONTROL 0 0x1c73 2 0 2 OTG_CRC1_WINDOWA_Y_START 0 14 OTG_CRC1_WINDOWA_Y_END 16 30 mmOTG2_OTG_CRC1_WINDOWB_X_CONTROL 0 0x1c74 2 0 2 OTG_CRC1_WINDOWB_X_START 0 14 OTG_CRC1_WINDOWB_X_END 16 30 mmOTG2_OTG_CRC1_WINDOWB_Y_CONTROL 0 0x1c75 2 0 2 OTG_CRC1_WINDOWB_Y_START 0 14 OTG_CRC1_WINDOWB_Y_END 16 30 mmOTG2_OTG_CRC1_DATA_RG 0 0x1c76 2 0 2 CRC1_R_CR 0 15 CRC1_G_Y 16 31 mmOTG2_OTG_CRC1_DATA_B 0 0x1c77 2 0 2 CRC1_B_CB 0 15 CRC1_C 16 31 mmOTG2_OTG_CRC2_DATA_RG 0 0x1c78 2 0 2 CRC2_R_CR 0 15 CRC2_G_Y 16 31 mmOTG2_OTG_CRC2_DATA_B 0 0x1c79 2 0 2 CRC2_B_CB 0 15 CRC2_C 16 31 mmOTG2_OTG_CRC3_DATA_RG 0 0x1c7a 2 0 2 CRC3_R_CR 0 15 CRC3_G_Y 16 31 mmOTG2_OTG_CRC3_DATA_B 0 0x1c7b 2 0 2 CRC3_B_CB 0 15 CRC3_C 16 31 mmOTG2_OTG_CRC_SIG_RED_GREEN_MASK 0 0x1c7c 2 0 2 OTG_CRC_SIG_RED_MASK 0 15 OTG_CRC_SIG_GREEN_MASK 16 31 mmOTG2_OTG_CRC_SIG_BLUE_CONTROL_MASK 0 0x1c7d 2 0 2 OTG_CRC_SIG_BLUE_MASK 0 15 OTG_CRC_SIG_CONTROL_MASK 16 31 mmOTG2_OTG_STATIC_SCREEN_CONTROL 0 0x1c84 9 0 2 OTG_STATIC_SCREEN_EVENT_MASK 0 15 OTG_STATIC_SCREEN_FRAME_COUNT 16 23 OTG_CPU_SS_INT_ENABLE 24 24 OTG_SS_STATUS 25 25 OTG_CPU_SS_INT_STATUS 26 26 OTG_CPU_SS_INT_CLEAR 27 27 OTG_CPU_SS_INT_TYPE 28 28 OTG_STATIC_SCREEN_OVERRIDE 30 30 OTG_STATIC_SCREEN_OVERRIDE_VALUE 31 31 mmOTG2_OTG_3D_STRUCTURE_CONTROL 0 0x1c85 6 0 2 OTG_3D_STRUCTURE_EN 0 0 OTG_3D_STRUCTURE_V_UPDATE_MODE 8 9 OTG_3D_STRUCTURE_STEREO_SEL_OVR 12 12 OTG_3D_STRUCTURE_F_COUNT_RESET 16 16 OTG_3D_STRUCTURE_F_COUNT_RESET_PENDING 17 17 OTG_3D_STRUCTURE_F_COUNT 18 19 mmOTG2_OTG_GSL_VSYNC_GAP 0 0x1c86 8 0 2 OTG_GSL_VSYNC_GAP_LIMIT 0 7 OTG_GSL_VSYNC_GAP_DELAY 8 15 OTG_GSL_VSYNC_GAP_SOURCE_SEL 16 16 OTG_GSL_VSYNC_GAP_MODE 17 18 OTG_GSL_VSYNC_GAP_CLEAR 19 19 OTG_GSL_VSYNC_GAP_OCCURRED 20 20 OTG_GSL_VSYNC_GAP_MASTER_FASTER 23 23 OTG_GSL_VSYNC_GAP 24 31 mmOTG2_OTG_MASTER_UPDATE_MODE 0 0x1c87 1 0 2 MASTER_UPDATE_INTERLACED_MODE 0 1 mmOTG2_OTG_CLOCK_CONTROL 0 0x1c88 5 0 2 OTG_CLOCK_EN 0 0 OTG_CLOCK_GATE_DIS 1 1 OTG_SOFT_RESET 4 4 OTG_CLOCK_ON 8 8 OTG_BUSY 16 16 mmOTG2_OTG_VSTARTUP_PARAM 0 0x1c89 1 0 2 VSTARTUP_START 0 9 mmOTG2_OTG_VUPDATE_PARAM 0 0x1c8a 2 0 2 VUPDATE_OFFSET 0 15 VUPDATE_WIDTH 16 25 mmOTG2_OTG_VREADY_PARAM 0 0x1c8b 1 0 2 VREADY_OFFSET 0 15 mmOTG2_OTG_GLOBAL_SYNC_STATUS 0 0x1c8c 25 0 2 VSTARTUP_INT_EN 0 0 VSTARTUP_INT_TYPE 1 1 VSTARTUP_EVENT_OCCURRED 2 2 VSTARTUP_INT_STATUS 3 3 VSTARTUP_EVENT_CLEAR 4 4 VUPDATE_INT_EN 5 5 VUPDATE_INT_TYPE 6 6 VUPDATE_INT_POSITION_SEL 7 7 VUPDATE_EVENT_OCCURRED 8 8 VUPDATE_INT_STATUS 9 9 VUPDATE_EVENT_CLEAR 10 10 VUPDATE_STATUS 11 11 VUPDATE_NO_LOCK_INT_EN 12 12 VUPDATE_NO_LOCK_INT_TYPE 13 13 VUPDATE_NO_LOCK_EVENT_OCCURRED 14 14 VUPDATE_NO_LOCK_INT_STATUS 15 15 VUPDATE_NO_LOCK_EVENT_CLEAR 16 16 VUPDATE_NO_LOCK_STATUS 17 17 VREADY_INT_EN 18 18 VREADY_INT_TYPE 19 19 VREADY_EVENT_OCCURRED 20 20 VREADY_INT_STATUS 21 21 VREADY_EVENT_CLEAR 22 22 STEREO_SELECT_STATUS 24 24 FIELD_NUMBER_STATUS 25 25 mmOTG2_OTG_MASTER_UPDATE_LOCK 0 0x1c8d 2 0 2 OTG_MASTER_UPDATE_LOCK 0 0 UPDATE_LOCK_STATUS 8 8 mmOTG2_OTG_GSL_CONTROL 0 0x1c8e 6 0 2 OTG_GSL0_EN 0 0 OTG_GSL1_EN 1 1 OTG_GSL2_EN 2 2 OTG_GSL_MASTER_EN 3 3 OTG_GSL_FORCE_DELAY 16 20 OTG_GSL_CHECK_ALL_FIELDS 28 28 mmOTG2_OTG_GSL_WINDOW_X 0 0x1c8f 2 0 2 OTG_GSL_WINDOW_START_X 0 14 OTG_GSL_WINDOW_END_X 16 30 mmOTG2_OTG_GSL_WINDOW_Y 0 0x1c90 2 0 2 OTG_GSL_WINDOW_START_Y 0 14 OTG_GSL_WINDOW_END_Y 16 30 mmOTG2_OTG_VUPDATE_KEEPOUT 0 0x1c91 3 0 2 MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_START_OFFSET 0 15 MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_END_OFFSET 16 25 OTG_MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_EN 31 31 mmOTG2_OTG_GLOBAL_CONTROL0 0 0x1c92 3 0 2 OTG_MASTER_UPDATE_LOCK_HTOTAL_KEEPOUT 0 7 OTG_MASTER_UPDATE_LOCK_HTOTAL_KEEPOUT_EN 8 8 OTG_MASTER_UPDATE_LOCK_SEL 25 27 mmOTG2_OTG_GLOBAL_CONTROL1 0 0x1c93 3 0 2 MASTER_UPDATE_LOCK_DB_X 0 14 MASTER_UPDATE_LOCK_DB_Y 16 30 MASTER_UPDATE_LOCK_DB_EN 31 31 mmOTG2_OTG_GLOBAL_CONTROL2 0 0x1c94 4 0 2 DIG_UPDATE_LOCATION 0 9 GLOBAL_UPDATE_LOCK_EN 10 10 MANUAL_FLOW_CONTROL_SEL 16 18 DCCG_VUPDATE_MODE 31 31 mmOTG2_OTG_GLOBAL_CONTROL3 0 0x1c95 3 0 2 MASTER_UPDATE_LOCK_DB_FIELD 0 1 MASTER_UPDATE_LOCK_DB_STEREO_SEL 4 5 MASTER_UPDATE_LOCK_DB_FIELD_STEREO_FLAG_SEL 8 8 mmOTG2_OTG_TRIG_MANUAL_CONTROL 0 0x1c96 1 0 2 TRIG_MANUAL_CONTROL 0 0 mmOTG2_OTG_MANUAL_FLOW_CONTROL 0 0x1c97 1 0 2 MANUAL_FLOW_CONTROL 0 0 mmOTG2_OTG_RANGE_TIMING_INT_STATUS 0 0x1c98 5 0 2 OTG_RANGE_TIMING_UPDATE_OCCURRED 0 0 OTG_RANGE_TIMING_UPDATE_OCCURRED_INT 4 4 OTG_RANGE_TIMING_UPDATE_OCCURRED_CLEAR 8 8 OTG_RANGE_TIMING_UPDATE_OCCURRED_INT_MSK 12 12 OTG_RANGE_TIMING_UPDATE_OCCURRED_INT_TYPE 16 16 mmOTG2_OTG_DRR_CONTROL 0 0x1c99 2 0 2 OTG_DRR_AVERAGE_FRAME 0 2 OTG_V_TOTAL_LAST_USED_BY_DRR 16 30 mmOTG2_OTG_REQUEST_CONTROL 0 0x1c9a 1 0 2 OTG_REQUEST_MODE_FOR_H_DUPLICATE 0 0 mmOTG2_OTG_SPARE_REGISTER 0 0x1c9b 1 0 2 OTG_SPARE_REG 0 31 mmOTG3_OTG_H_TOTAL 0 0x1caa 1 0 2 OTG_H_TOTAL 0 14 mmOTG3_OTG_H_BLANK_START_END 0 0x1cab 2 0 2 OTG_H_BLANK_START 0 14 OTG_H_BLANK_END 16 30 mmOTG3_OTG_H_SYNC_A 0 0x1cac 2 0 2 OTG_H_SYNC_A_START 0 14 OTG_H_SYNC_A_END 16 30 mmOTG3_OTG_H_SYNC_A_CNTL 0 0x1cad 3 0 2 OTG_H_SYNC_A_POL 0 0 OTG_COMP_SYNC_A_EN 16 16 OTG_H_SYNC_A_CUTOFF 17 17 mmOTG3_OTG_H_TIMING_CNTL 0 0x1cae 2 0 2 OTG_H_TIMING_DIV_BY2 0 0 OTG_H_TIMING_DIV_BY2_UPDATE_MODE 8 8 mmOTG3_OTG_V_TOTAL 0 0x1caf 1 0 2 OTG_V_TOTAL 0 14 mmOTG3_OTG_V_TOTAL_MIN 0 0x1cb0 1 0 2 OTG_V_TOTAL_MIN 0 14 mmOTG3_OTG_V_TOTAL_MAX 0 0x1cb1 1 0 2 OTG_V_TOTAL_MAX 0 14 mmOTG3_OTG_V_TOTAL_MID 0 0x1cb2 1 0 2 OTG_V_TOTAL_MID 0 14 mmOTG3_OTG_V_TOTAL_CONTROL 0 0x1cb3 8 0 2 OTG_V_TOTAL_MIN_SEL 0 0 OTG_V_TOTAL_MAX_SEL 1 1 OTG_VTOTAL_MID_REPLACING_MAX_EN 2 2 OTG_VTOTAL_MID_REPLACING_MIN_EN 3 3 OTG_FORCE_LOCK_ON_EVENT 4 4 OTG_SET_V_TOTAL_MIN_MASK_EN 7 7 OTG_VTOTAL_MID_FRAME_NUM 8 15 OTG_SET_V_TOTAL_MIN_MASK 16 31 mmOTG3_OTG_V_TOTAL_INT_STATUS 0 0x1cb4 4 0 2 OTG_SET_V_TOTAL_MIN_EVENT_OCCURED 0 0 OTG_SET_V_TOTAL_MIN_EVENT_OCCURED_INT 4 4 OTG_SET_V_TOTAL_MIN_EVENT_OCCURED_ACK 8 8 OTG_SET_V_TOTAL_MIN_EVENT_OCCURED_MSK 12 12 mmOTG3_OTG_VSYNC_NOM_INT_STATUS 0 0x1cb5 2 0 2 OTG_VSYNC_NOM 0 0 OTG_VSYNC_NOM_INT_CLEAR 4 4 mmOTG3_OTG_V_BLANK_START_END 0 0x1cb6 2 0 2 OTG_V_BLANK_START 0 14 OTG_V_BLANK_END 16 30 mmOTG3_OTG_V_SYNC_A 0 0x1cb7 2 0 2 OTG_V_SYNC_A_START 0 14 OTG_V_SYNC_A_END 16 30 mmOTG3_OTG_V_SYNC_A_CNTL 0 0x1cb8 1 0 2 OTG_V_SYNC_A_POL 0 0 mmOTG3_OTG_TRIGA_CNTL 0 0x1cb9 12 0 2 OTG_TRIGA_SOURCE_SELECT 0 4 OTG_TRIGA_SOURCE_PIPE_SELECT 5 7 OTG_TRIGA_POLARITY_SELECT 8 10 OTG_TRIGA_RESYNC_BYPASS_EN 11 11 OTG_TRIGA_INPUT_STATUS 12 12 OTG_TRIGA_POLARITY_STATUS 13 13 OTG_TRIGA_OCCURRED 14 14 OTG_TRIGA_RISING_EDGE_DETECT_CNTL 16 17 OTG_TRIGA_FALLING_EDGE_DETECT_CNTL 18 19 OTG_TRIGA_FREQUENCY_SELECT 20 21 OTG_TRIGA_DELAY 24 28 OTG_TRIGA_CLEAR 31 31 mmOTG3_OTG_TRIGA_MANUAL_TRIG 0 0x1cba 1 0 2 OTG_TRIGA_MANUAL_TRIG 0 0 mmOTG3_OTG_TRIGB_CNTL 0 0x1cbb 12 0 2 OTG_TRIGB_SOURCE_SELECT 0 4 OTG_TRIGB_SOURCE_PIPE_SELECT 5 7 OTG_TRIGB_POLARITY_SELECT 8 10 OTG_TRIGB_RESYNC_BYPASS_EN 11 11 OTG_TRIGB_INPUT_STATUS 12 12 OTG_TRIGB_POLARITY_STATUS 13 13 OTG_TRIGB_OCCURRED 14 14 OTG_TRIGB_RISING_EDGE_DETECT_CNTL 16 17 OTG_TRIGB_FALLING_EDGE_DETECT_CNTL 18 19 OTG_TRIGB_FREQUENCY_SELECT 20 21 OTG_TRIGB_DELAY 24 28 OTG_TRIGB_CLEAR 31 31 mmOTG3_OTG_TRIGB_MANUAL_TRIG 0 0x1cbc 1 0 2 OTG_TRIGB_MANUAL_TRIG 0 0 mmOTG3_OTG_FORCE_COUNT_NOW_CNTL 0 0x1cbd 5 0 2 OTG_FORCE_COUNT_NOW_MODE 0 1 OTG_FORCE_COUNT_NOW_CHECK 4 4 OTG_FORCE_COUNT_NOW_TRIG_SEL 8 8 OTG_FORCE_COUNT_NOW_OCCURRED 16 16 OTG_FORCE_COUNT_NOW_CLEAR 24 24 mmOTG3_OTG_FLOW_CONTROL 0 0x1cbe 4 0 2 OTG_FLOW_CONTROL_SOURCE_SELECT 0 4 OTG_FLOW_CONTROL_POLARITY 8 8 OTG_FLOW_CONTROL_GRANULARITY 16 16 OTG_FLOW_CONTROL_INPUT_STATUS 24 24 mmOTG3_OTG_STEREO_FORCE_NEXT_EYE 0 0x1cbf 3 0 2 OTG_STEREO_FORCE_NEXT_EYE 0 1 OTG_AVSYNC_FRAME_COUNTER 8 15 OTG_AVSYNC_LINE_COUNTER 16 28 mmOTG3_OTG_AVSYNC_COUNTER 0 0x1cc0 1 0 2 OTG_AVSYNC_COUNTER 0 31 mmOTG3_OTG_CONTROL 0 0x1cc1 6 0 2 OTG_MASTER_EN 0 0 OTG_DISABLE_POINT_CNTL 8 9 OTG_START_POINT_CNTL 12 12 OTG_FIELD_NUMBER_CNTL 13 13 OTG_FIELD_NUMBER_POLARITY 14 14 OTG_CURRENT_MASTER_EN_STATE 16 16 mmOTG3_OTG_BLANK_CONTROL 0 0x1cc2 3 0 2 OTG_CURRENT_BLANK_STATE 0 0 OTG_BLANK_DATA_EN 8 8 OTG_BLANK_DE_MODE 16 16 mmOTG3_OTG_PIPE_ABORT_CONTROL 0 0x1cc3 2 0 2 OTG_PIPE_ABORT 0 0 OTG_PIPE_ABORT_DONE 8 8 mmOTG3_OTG_INTERLACE_CONTROL 0 0x1cc4 2 0 2 OTG_INTERLACE_ENABLE 0 0 OTG_INTERLACE_FORCE_NEXT_FIELD 16 17 mmOTG3_OTG_INTERLACE_STATUS 0 0x1cc5 2 0 2 OTG_INTERLACE_CURRENT_FIELD 0 0 OTG_INTERLACE_NEXT_FIELD 1 1 mmOTG3_OTG_FIELD_INDICATION_CONTROL 0 0x1cc6 2 0 2 OTG_FIELD_INDICATION_OUTPUT_POLARITY 0 0 OTG_FIELD_ALIGNMENT 1 1 mmOTG3_OTG_PIXEL_DATA_READBACK0 0 0x1cc7 2 0 2 OTG_PIXEL_DATA_BLUE_CB 0 15 OTG_PIXEL_DATA_GREEN_Y 16 31 mmOTG3_OTG_PIXEL_DATA_READBACK1 0 0x1cc8 1 0 2 OTG_PIXEL_DATA_RED_CR 0 15 mmOTG3_OTG_STATUS 0 0x1cc9 8 0 2 OTG_V_BLANK 0 0 OTG_V_ACTIVE_DISP 1 1 OTG_V_SYNC_A 2 2 OTG_V_UPDATE 3 3 OTG_V_BLANK_3D_STRUCTURE 5 5 OTG_H_BLANK 16 16 OTG_H_ACTIVE_DISP 17 17 OTG_H_SYNC_A 18 18 mmOTG3_OTG_STATUS_POSITION 0 0x1cca 2 0 2 OTG_VERT_COUNT 0 14 OTG_HORZ_COUNT 16 30 mmOTG3_OTG_NOM_VERT_POSITION 0 0x1ccb 1 0 2 OTG_VERT_COUNT_NOM 0 14 mmOTG3_OTG_STATUS_FRAME_COUNT 0 0x1ccc 1 0 2 OTG_FRAME_COUNT 0 23 mmOTG3_OTG_STATUS_VF_COUNT 0 0x1ccd 1 0 2 OTG_VF_COUNT 0 30 mmOTG3_OTG_STATUS_HV_COUNT 0 0x1cce 1 0 2 OTG_HV_COUNT 0 30 mmOTG3_OTG_COUNT_CONTROL 0 0x1ccf 2 0 2 OTG_HORZ_COUNT_BY2_EN 0 0 OTG_HORZ_REPETITION_COUNT 1 4 mmOTG3_OTG_COUNT_RESET 0 0x1cd0 1 0 2 OTG_RESET_FRAME_COUNT 0 0 mmOTG3_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE 0 0x1cd1 1 0 2 OTG_MANUAL_FORCE_VSYNC_NEXT_LINE 0 0 mmOTG3_OTG_VERT_SYNC_CONTROL 0 0x1cd2 3 0 2 OTG_FORCE_VSYNC_NEXT_LINE_OCCURRED 0 0 OTG_FORCE_VSYNC_NEXT_LINE_CLEAR 8 8 OTG_AUTO_FORCE_VSYNC_MODE 16 17 mmOTG3_OTG_STEREO_STATUS 0 0x1cd3 7 0 2 OTG_STEREO_CURRENT_EYE 0 0 OTG_STEREO_SYNC_OUTPUT 8 8 OTG_STEREO_SYNC_SELECT 16 16 OTG_STEREO_EYE_FLAG 20 20 OTG_STEREO_FORCE_NEXT_EYE_PENDING 24 25 OTG_CURRENT_3D_STRUCTURE_STATE 30 30 OTG_CURRENT_STEREOSYNC_EN_STATE 31 31 mmOTG3_OTG_STEREO_CONTROL 0 0x1cd4 7 0 2 OTG_STEREO_SYNC_OUTPUT_LINE_NUM 0 14 OTG_STEREO_SYNC_OUTPUT_POLARITY 15 15 OTG_STEREO_EYE_FLAG_POLARITY 17 17 OTG_DISABLE_STEREOSYNC_OUTPUT_FOR_DP 18 18 OTG_DISABLE_FIELD_NUM 19 19 OTG_DISABLE_V_BLANK_FOR_DP_FIX 20 20 OTG_STEREO_EN 24 24 mmOTG3_OTG_SNAPSHOT_STATUS 0 0x1cd5 3 0 2 OTG_SNAPSHOT_OCCURRED 0 0 OTG_SNAPSHOT_CLEAR 1 1 OTG_SNAPSHOT_MANUAL_TRIGGER 2 2 mmOTG3_OTG_SNAPSHOT_CONTROL 0 0x1cd6 1 0 2 OTG_AUTO_SNAPSHOT_TRIG_SEL 0 1 mmOTG3_OTG_SNAPSHOT_POSITION 0 0x1cd7 2 0 2 OTG_SNAPSHOT_VERT_COUNT 0 14 OTG_SNAPSHOT_HORZ_COUNT 16 30 mmOTG3_OTG_SNAPSHOT_FRAME 0 0x1cd8 1 0 2 OTG_SNAPSHOT_FRAME_COUNT 0 23 mmOTG3_OTG_INTERRUPT_CONTROL 0 0x1cd9 14 0 2 OTG_SNAPSHOT_INT_MSK 0 0 OTG_SNAPSHOT_INT_TYPE 1 1 OTG_FORCE_COUNT_NOW_INT_MSK 8 8 OTG_FORCE_COUNT_NOW_INT_TYPE 9 9 OTG_FORCE_VSYNC_NEXT_LINE_INT_MSK 16 16 OTG_FORCE_VSYNC_NEXT_LINE_INT_TYPE 17 17 OTG_TRIGA_INT_MSK 24 24 OTG_TRIGB_INT_MSK 25 25 OTG_TRIGA_INT_TYPE 26 26 OTG_TRIGB_INT_TYPE 27 27 OTG_VSYNC_NOM_INT_MSK 28 28 OTG_VSYNC_NOM_INT_TYPE 29 29 OTG_GSL_VSYNC_GAP_INT_MSK 30 30 OTG_GSL_VSYNC_GAP_INT_TYPE 31 31 mmOTG3_OTG_UPDATE_LOCK 0 0x1cda 1 0 2 OTG_UPDATE_LOCK 0 0 mmOTG3_OTG_DOUBLE_BUFFER_CONTROL 0 0x1cdb 10 0 2 OTG_UPDATE_PENDING 0 0 OTG_H_TIMING_DIV_BY2_DB_UPDATE_PENDING 2 2 OTG_BLANK_DATA_EN_UPDATE_PENDING 3 3 OTG_RANGE_TIMING_DBUF_UPDATE_PENDING 4 4 OTG_TIMING_DB_UPDATE_PENDING 5 5 OTG_3D_CTRL_DB_UPDATE_PENDING 6 6 OTG_3D_STRUCTURE_EN_DB_UPDATE_PENDING 7 7 OTG_UPDATE_INSTANTLY 8 8 OTG_BLANK_DATA_DOUBLE_BUFFER_EN 16 16 OTG_RANGE_TIMING_DBUF_UPDATE_MODE 24 25 mmOTG3_OTG_TEST_PATTERN_CONTROL 0 0x1cdc 4 0 2 OTG_TEST_PATTERN_EN 0 0 OTG_TEST_PATTERN_MODE 8 10 OTG_TEST_PATTERN_DYNAMIC_RANGE 16 16 OTG_TEST_PATTERN_COLOR_FORMAT 24 31 mmOTG3_OTG_TEST_PATTERN_PARAMETERS 0 0x1cdd 5 0 2 OTG_TEST_PATTERN_INC0 0 3 OTG_TEST_PATTERN_INC1 4 7 OTG_TEST_PATTERN_VRES 8 11 OTG_TEST_PATTERN_HRES 12 15 OTG_TEST_PATTERN_RAMP0_OFFSET 16 31 mmOTG3_OTG_TEST_PATTERN_COLOR 0 0x1cde 2 0 2 OTG_TEST_PATTERN_DATA 0 15 OTG_TEST_PATTERN_MASK 16 21 mmOTG3_OTG_MASTER_EN 0 0x1cdf 1 0 2 OTG_MASTER_EN 0 0 mmOTG3_OTG_BLANK_DATA_COLOR 0 0x1ce1 3 0 2 OTG_BLANK_DATA_COLOR_BLUE_CB 0 9 OTG_BLANK_DATA_COLOR_GREEN_Y 10 19 OTG_BLANK_DATA_COLOR_RED_CR 20 29 mmOTG3_OTG_BLANK_DATA_COLOR_EXT 0 0x1ce2 3 0 2 OTG_BLANK_DATA_COLOR_BLUE_CB_EXT 0 5 OTG_BLANK_DATA_COLOR_GREEN_Y_EXT 8 13 OTG_BLANK_DATA_COLOR_RED_CR_EXT 16 21 mmOTG3_OTG_BLACK_COLOR 0 0x1ce3 3 0 2 OTG_BLACK_COLOR_B_CB 0 9 OTG_BLACK_COLOR_G_Y 10 19 OTG_BLACK_COLOR_R_CR 20 29 mmOTG3_OTG_BLACK_COLOR_EXT 0 0x1ce4 3 0 2 OTG_BLACK_COLOR_B_CB_EXT 0 5 OTG_BLACK_COLOR_G_Y_EXT 8 13 OTG_BLACK_COLOR_R_CR_EXT 16 21 mmOTG3_OTG_VERTICAL_INTERRUPT0_POSITION 0 0x1ce5 2 0 2 OTG_VERTICAL_INTERRUPT0_LINE_START 0 14 OTG_VERTICAL_INTERRUPT0_LINE_END 16 30 mmOTG3_OTG_VERTICAL_INTERRUPT0_CONTROL 0 0x1ce6 6 0 2 OTG_VERTICAL_INTERRUPT0_OUTPUT_POLARITY 4 4 OTG_VERTICAL_INTERRUPT0_INT_ENABLE 8 8 OTG_VERTICAL_INTERRUPT0_STATUS 12 12 OTG_VERTICAL_INTERRUPT0_INT_STATUS 16 16 OTG_VERTICAL_INTERRUPT0_CLEAR 20 20 OTG_VERTICAL_INTERRUPT0_INT_TYPE 24 24 mmOTG3_OTG_VERTICAL_INTERRUPT1_POSITION 0 0x1ce7 1 0 2 OTG_VERTICAL_INTERRUPT1_LINE_START 0 14 mmOTG3_OTG_VERTICAL_INTERRUPT1_CONTROL 0 0x1ce8 5 0 2 OTG_VERTICAL_INTERRUPT1_INT_ENABLE 8 8 OTG_VERTICAL_INTERRUPT1_STATUS 12 12 OTG_VERTICAL_INTERRUPT1_INT_STATUS 16 16 OTG_VERTICAL_INTERRUPT1_CLEAR 20 20 OTG_VERTICAL_INTERRUPT1_INT_TYPE 24 24 mmOTG3_OTG_VERTICAL_INTERRUPT2_POSITION 0 0x1ce9 1 0 2 OTG_VERTICAL_INTERRUPT2_LINE_START 0 14 mmOTG3_OTG_VERTICAL_INTERRUPT2_CONTROL 0 0x1cea 5 0 2 OTG_VERTICAL_INTERRUPT2_INT_ENABLE 8 8 OTG_VERTICAL_INTERRUPT2_STATUS 12 12 OTG_VERTICAL_INTERRUPT2_INT_STATUS 16 16 OTG_VERTICAL_INTERRUPT2_CLEAR 20 20 OTG_VERTICAL_INTERRUPT2_INT_TYPE 24 24 mmOTG3_OTG_CRC_CNTL 0 0x1ceb 16 0 2 OTG_CRC_EN 0 0 OTG_CRC_DUAL_LINK_EN 1 1 OTG_CRC_DUAL_LINK_MODE 2 2 OTG_CRC_BLANK_ONLY 3 3 OTG_CRC_CONT_EN 4 4 OTG_CRC_CAPTURE_START_SEL 5 6 OTG_CRC_STEREO_MODE 8 9 OTG_CRC_INTERLACE_MODE 12 13 OTG_CRC_MULTI_STREAM_MODE 16 18 OTG_CRC_USE_NEW_AND_REPEATED_PIXELS 19 19 OTG_CRC0_SELECT 20 22 OTG_CRC1_SELECT 24 26 OTG_ONE_SHOT_CRC0_PENDING 28 28 OTG_ONE_SHOT_CRC1_PENDING 29 29 OTG_ONE_SHOT_CRC2_PENDING 30 30 OTG_ONE_SHOT_CRC3_PENDING 31 31 mmOTG3_OTG_CRC0_WINDOWA_X_CONTROL 0 0x1cec 2 0 2 OTG_CRC0_WINDOWA_X_START 0 14 OTG_CRC0_WINDOWA_X_END 16 30 mmOTG3_OTG_CRC0_WINDOWA_Y_CONTROL 0 0x1ced 2 0 2 OTG_CRC0_WINDOWA_Y_START 0 14 OTG_CRC0_WINDOWA_Y_END 16 30 mmOTG3_OTG_CRC0_WINDOWB_X_CONTROL 0 0x1cee 2 0 2 OTG_CRC0_WINDOWB_X_START 0 14 OTG_CRC0_WINDOWB_X_END 16 30 mmOTG3_OTG_CRC0_WINDOWB_Y_CONTROL 0 0x1cef 2 0 2 OTG_CRC0_WINDOWB_Y_START 0 14 OTG_CRC0_WINDOWB_Y_END 16 30 mmOTG3_OTG_CRC0_DATA_RG 0 0x1cf0 2 0 2 CRC0_R_CR 0 15 CRC0_G_Y 16 31 mmOTG3_OTG_CRC0_DATA_B 0 0x1cf1 2 0 2 CRC0_B_CB 0 15 CRC0_C 16 31 mmOTG3_OTG_CRC1_WINDOWA_X_CONTROL 0 0x1cf2 2 0 2 OTG_CRC1_WINDOWA_X_START 0 14 OTG_CRC1_WINDOWA_X_END 16 30 mmOTG3_OTG_CRC1_WINDOWA_Y_CONTROL 0 0x1cf3 2 0 2 OTG_CRC1_WINDOWA_Y_START 0 14 OTG_CRC1_WINDOWA_Y_END 16 30 mmOTG3_OTG_CRC1_WINDOWB_X_CONTROL 0 0x1cf4 2 0 2 OTG_CRC1_WINDOWB_X_START 0 14 OTG_CRC1_WINDOWB_X_END 16 30 mmOTG3_OTG_CRC1_WINDOWB_Y_CONTROL 0 0x1cf5 2 0 2 OTG_CRC1_WINDOWB_Y_START 0 14 OTG_CRC1_WINDOWB_Y_END 16 30 mmOTG3_OTG_CRC1_DATA_RG 0 0x1cf6 2 0 2 CRC1_R_CR 0 15 CRC1_G_Y 16 31 mmOTG3_OTG_CRC1_DATA_B 0 0x1cf7 2 0 2 CRC1_B_CB 0 15 CRC1_C 16 31 mmOTG3_OTG_CRC2_DATA_RG 0 0x1cf8 2 0 2 CRC2_R_CR 0 15 CRC2_G_Y 16 31 mmOTG3_OTG_CRC2_DATA_B 0 0x1cf9 2 0 2 CRC2_B_CB 0 15 CRC2_C 16 31 mmOTG3_OTG_CRC3_DATA_RG 0 0x1cfa 2 0 2 CRC3_R_CR 0 15 CRC3_G_Y 16 31 mmOTG3_OTG_CRC3_DATA_B 0 0x1cfb 2 0 2 CRC3_B_CB 0 15 CRC3_C 16 31 mmOTG3_OTG_CRC_SIG_RED_GREEN_MASK 0 0x1cfc 2 0 2 OTG_CRC_SIG_RED_MASK 0 15 OTG_CRC_SIG_GREEN_MASK 16 31 mmOTG3_OTG_CRC_SIG_BLUE_CONTROL_MASK 0 0x1cfd 2 0 2 OTG_CRC_SIG_BLUE_MASK 0 15 OTG_CRC_SIG_CONTROL_MASK 16 31 mmOTG3_OTG_STATIC_SCREEN_CONTROL 0 0x1d04 9 0 2 OTG_STATIC_SCREEN_EVENT_MASK 0 15 OTG_STATIC_SCREEN_FRAME_COUNT 16 23 OTG_CPU_SS_INT_ENABLE 24 24 OTG_SS_STATUS 25 25 OTG_CPU_SS_INT_STATUS 26 26 OTG_CPU_SS_INT_CLEAR 27 27 OTG_CPU_SS_INT_TYPE 28 28 OTG_STATIC_SCREEN_OVERRIDE 30 30 OTG_STATIC_SCREEN_OVERRIDE_VALUE 31 31 mmOTG3_OTG_3D_STRUCTURE_CONTROL 0 0x1d05 6 0 2 OTG_3D_STRUCTURE_EN 0 0 OTG_3D_STRUCTURE_V_UPDATE_MODE 8 9 OTG_3D_STRUCTURE_STEREO_SEL_OVR 12 12 OTG_3D_STRUCTURE_F_COUNT_RESET 16 16 OTG_3D_STRUCTURE_F_COUNT_RESET_PENDING 17 17 OTG_3D_STRUCTURE_F_COUNT 18 19 mmOTG3_OTG_GSL_VSYNC_GAP 0 0x1d06 8 0 2 OTG_GSL_VSYNC_GAP_LIMIT 0 7 OTG_GSL_VSYNC_GAP_DELAY 8 15 OTG_GSL_VSYNC_GAP_SOURCE_SEL 16 16 OTG_GSL_VSYNC_GAP_MODE 17 18 OTG_GSL_VSYNC_GAP_CLEAR 19 19 OTG_GSL_VSYNC_GAP_OCCURRED 20 20 OTG_GSL_VSYNC_GAP_MASTER_FASTER 23 23 OTG_GSL_VSYNC_GAP 24 31 mmOTG3_OTG_MASTER_UPDATE_MODE 0 0x1d07 1 0 2 MASTER_UPDATE_INTERLACED_MODE 0 1 mmOTG3_OTG_CLOCK_CONTROL 0 0x1d08 5 0 2 OTG_CLOCK_EN 0 0 OTG_CLOCK_GATE_DIS 1 1 OTG_SOFT_RESET 4 4 OTG_CLOCK_ON 8 8 OTG_BUSY 16 16 mmOTG3_OTG_VSTARTUP_PARAM 0 0x1d09 1 0 2 VSTARTUP_START 0 9 mmOTG3_OTG_VUPDATE_PARAM 0 0x1d0a 2 0 2 VUPDATE_OFFSET 0 15 VUPDATE_WIDTH 16 25 mmOTG3_OTG_VREADY_PARAM 0 0x1d0b 1 0 2 VREADY_OFFSET 0 15 mmOTG3_OTG_GLOBAL_SYNC_STATUS 0 0x1d0c 25 0 2 VSTARTUP_INT_EN 0 0 VSTARTUP_INT_TYPE 1 1 VSTARTUP_EVENT_OCCURRED 2 2 VSTARTUP_INT_STATUS 3 3 VSTARTUP_EVENT_CLEAR 4 4 VUPDATE_INT_EN 5 5 VUPDATE_INT_TYPE 6 6 VUPDATE_INT_POSITION_SEL 7 7 VUPDATE_EVENT_OCCURRED 8 8 VUPDATE_INT_STATUS 9 9 VUPDATE_EVENT_CLEAR 10 10 VUPDATE_STATUS 11 11 VUPDATE_NO_LOCK_INT_EN 12 12 VUPDATE_NO_LOCK_INT_TYPE 13 13 VUPDATE_NO_LOCK_EVENT_OCCURRED 14 14 VUPDATE_NO_LOCK_INT_STATUS 15 15 VUPDATE_NO_LOCK_EVENT_CLEAR 16 16 VUPDATE_NO_LOCK_STATUS 17 17 VREADY_INT_EN 18 18 VREADY_INT_TYPE 19 19 VREADY_EVENT_OCCURRED 20 20 VREADY_INT_STATUS 21 21 VREADY_EVENT_CLEAR 22 22 STEREO_SELECT_STATUS 24 24 FIELD_NUMBER_STATUS 25 25 mmOTG3_OTG_MASTER_UPDATE_LOCK 0 0x1d0d 2 0 2 OTG_MASTER_UPDATE_LOCK 0 0 UPDATE_LOCK_STATUS 8 8 mmOTG3_OTG_GSL_CONTROL 0 0x1d0e 6 0 2 OTG_GSL0_EN 0 0 OTG_GSL1_EN 1 1 OTG_GSL2_EN 2 2 OTG_GSL_MASTER_EN 3 3 OTG_GSL_FORCE_DELAY 16 20 OTG_GSL_CHECK_ALL_FIELDS 28 28 mmOTG3_OTG_GSL_WINDOW_X 0 0x1d0f 2 0 2 OTG_GSL_WINDOW_START_X 0 14 OTG_GSL_WINDOW_END_X 16 30 mmOTG3_OTG_GSL_WINDOW_Y 0 0x1d10 2 0 2 OTG_GSL_WINDOW_START_Y 0 14 OTG_GSL_WINDOW_END_Y 16 30 mmOTG3_OTG_VUPDATE_KEEPOUT 0 0x1d11 3 0 2 MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_START_OFFSET 0 15 MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_END_OFFSET 16 25 OTG_MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_EN 31 31 mmOTG3_OTG_GLOBAL_CONTROL0 0 0x1d12 3 0 2 OTG_MASTER_UPDATE_LOCK_HTOTAL_KEEPOUT 0 7 OTG_MASTER_UPDATE_LOCK_HTOTAL_KEEPOUT_EN 8 8 OTG_MASTER_UPDATE_LOCK_SEL 25 27 mmOTG3_OTG_GLOBAL_CONTROL1 0 0x1d13 3 0 2 MASTER_UPDATE_LOCK_DB_X 0 14 MASTER_UPDATE_LOCK_DB_Y 16 30 MASTER_UPDATE_LOCK_DB_EN 31 31 mmOTG3_OTG_GLOBAL_CONTROL2 0 0x1d14 4 0 2 DIG_UPDATE_LOCATION 0 9 GLOBAL_UPDATE_LOCK_EN 10 10 MANUAL_FLOW_CONTROL_SEL 16 18 DCCG_VUPDATE_MODE 31 31 mmOTG3_OTG_GLOBAL_CONTROL3 0 0x1d15 3 0 2 MASTER_UPDATE_LOCK_DB_FIELD 0 1 MASTER_UPDATE_LOCK_DB_STEREO_SEL 4 5 MASTER_UPDATE_LOCK_DB_FIELD_STEREO_FLAG_SEL 8 8 mmOTG3_OTG_TRIG_MANUAL_CONTROL 0 0x1d16 1 0 2 TRIG_MANUAL_CONTROL 0 0 mmOTG3_OTG_MANUAL_FLOW_CONTROL 0 0x1d17 1 0 2 MANUAL_FLOW_CONTROL 0 0 mmOTG3_OTG_RANGE_TIMING_INT_STATUS 0 0x1d18 5 0 2 OTG_RANGE_TIMING_UPDATE_OCCURRED 0 0 OTG_RANGE_TIMING_UPDATE_OCCURRED_INT 4 4 OTG_RANGE_TIMING_UPDATE_OCCURRED_CLEAR 8 8 OTG_RANGE_TIMING_UPDATE_OCCURRED_INT_MSK 12 12 OTG_RANGE_TIMING_UPDATE_OCCURRED_INT_TYPE 16 16 mmOTG3_OTG_DRR_CONTROL 0 0x1d19 2 0 2 OTG_DRR_AVERAGE_FRAME 0 2 OTG_V_TOTAL_LAST_USED_BY_DRR 16 30 mmOTG3_OTG_REQUEST_CONTROL 0 0x1d1a 1 0 2 OTG_REQUEST_MODE_FOR_H_DUPLICATE 0 0 mmOTG3_OTG_SPARE_REGISTER 0 0x1d1b 1 0 2 OTG_SPARE_REG 0 31 mmOTG4_OTG_H_TOTAL 0 0x1d2a 1 0 2 OTG_H_TOTAL 0 14 mmOTG4_OTG_H_BLANK_START_END 0 0x1d2b 2 0 2 OTG_H_BLANK_START 0 14 OTG_H_BLANK_END 16 30 mmOTG4_OTG_H_SYNC_A 0 0x1d2c 2 0 2 OTG_H_SYNC_A_START 0 14 OTG_H_SYNC_A_END 16 30 mmOTG4_OTG_H_SYNC_A_CNTL 0 0x1d2d 3 0 2 OTG_H_SYNC_A_POL 0 0 OTG_COMP_SYNC_A_EN 16 16 OTG_H_SYNC_A_CUTOFF 17 17 mmOTG4_OTG_H_TIMING_CNTL 0 0x1d2e 2 0 2 OTG_H_TIMING_DIV_BY2 0 0 OTG_H_TIMING_DIV_BY2_UPDATE_MODE 8 8 mmOTG4_OTG_V_TOTAL 0 0x1d2f 1 0 2 OTG_V_TOTAL 0 14 mmOTG4_OTG_V_TOTAL_MIN 0 0x1d30 1 0 2 OTG_V_TOTAL_MIN 0 14 mmOTG4_OTG_V_TOTAL_MAX 0 0x1d31 1 0 2 OTG_V_TOTAL_MAX 0 14 mmOTG4_OTG_V_TOTAL_MID 0 0x1d32 1 0 2 OTG_V_TOTAL_MID 0 14 mmOTG4_OTG_V_TOTAL_CONTROL 0 0x1d33 8 0 2 OTG_V_TOTAL_MIN_SEL 0 0 OTG_V_TOTAL_MAX_SEL 1 1 OTG_VTOTAL_MID_REPLACING_MAX_EN 2 2 OTG_VTOTAL_MID_REPLACING_MIN_EN 3 3 OTG_FORCE_LOCK_ON_EVENT 4 4 OTG_SET_V_TOTAL_MIN_MASK_EN 7 7 OTG_VTOTAL_MID_FRAME_NUM 8 15 OTG_SET_V_TOTAL_MIN_MASK 16 31 mmOTG4_OTG_V_TOTAL_INT_STATUS 0 0x1d34 4 0 2 OTG_SET_V_TOTAL_MIN_EVENT_OCCURED 0 0 OTG_SET_V_TOTAL_MIN_EVENT_OCCURED_INT 4 4 OTG_SET_V_TOTAL_MIN_EVENT_OCCURED_ACK 8 8 OTG_SET_V_TOTAL_MIN_EVENT_OCCURED_MSK 12 12 mmOTG4_OTG_VSYNC_NOM_INT_STATUS 0 0x1d35 2 0 2 OTG_VSYNC_NOM 0 0 OTG_VSYNC_NOM_INT_CLEAR 4 4 mmOTG4_OTG_V_BLANK_START_END 0 0x1d36 2 0 2 OTG_V_BLANK_START 0 14 OTG_V_BLANK_END 16 30 mmOTG4_OTG_V_SYNC_A 0 0x1d37 2 0 2 OTG_V_SYNC_A_START 0 14 OTG_V_SYNC_A_END 16 30 mmOTG4_OTG_V_SYNC_A_CNTL 0 0x1d38 1 0 2 OTG_V_SYNC_A_POL 0 0 mmOTG4_OTG_TRIGA_CNTL 0 0x1d39 12 0 2 OTG_TRIGA_SOURCE_SELECT 0 4 OTG_TRIGA_SOURCE_PIPE_SELECT 5 7 OTG_TRIGA_POLARITY_SELECT 8 10 OTG_TRIGA_RESYNC_BYPASS_EN 11 11 OTG_TRIGA_INPUT_STATUS 12 12 OTG_TRIGA_POLARITY_STATUS 13 13 OTG_TRIGA_OCCURRED 14 14 OTG_TRIGA_RISING_EDGE_DETECT_CNTL 16 17 OTG_TRIGA_FALLING_EDGE_DETECT_CNTL 18 19 OTG_TRIGA_FREQUENCY_SELECT 20 21 OTG_TRIGA_DELAY 24 28 OTG_TRIGA_CLEAR 31 31 mmOTG4_OTG_TRIGA_MANUAL_TRIG 0 0x1d3a 1 0 2 OTG_TRIGA_MANUAL_TRIG 0 0 mmOTG4_OTG_TRIGB_CNTL 0 0x1d3b 12 0 2 OTG_TRIGB_SOURCE_SELECT 0 4 OTG_TRIGB_SOURCE_PIPE_SELECT 5 7 OTG_TRIGB_POLARITY_SELECT 8 10 OTG_TRIGB_RESYNC_BYPASS_EN 11 11 OTG_TRIGB_INPUT_STATUS 12 12 OTG_TRIGB_POLARITY_STATUS 13 13 OTG_TRIGB_OCCURRED 14 14 OTG_TRIGB_RISING_EDGE_DETECT_CNTL 16 17 OTG_TRIGB_FALLING_EDGE_DETECT_CNTL 18 19 OTG_TRIGB_FREQUENCY_SELECT 20 21 OTG_TRIGB_DELAY 24 28 OTG_TRIGB_CLEAR 31 31 mmOTG4_OTG_TRIGB_MANUAL_TRIG 0 0x1d3c 1 0 2 OTG_TRIGB_MANUAL_TRIG 0 0 mmOTG4_OTG_FORCE_COUNT_NOW_CNTL 0 0x1d3d 5 0 2 OTG_FORCE_COUNT_NOW_MODE 0 1 OTG_FORCE_COUNT_NOW_CHECK 4 4 OTG_FORCE_COUNT_NOW_TRIG_SEL 8 8 OTG_FORCE_COUNT_NOW_OCCURRED 16 16 OTG_FORCE_COUNT_NOW_CLEAR 24 24 mmOTG4_OTG_FLOW_CONTROL 0 0x1d3e 4 0 2 OTG_FLOW_CONTROL_SOURCE_SELECT 0 4 OTG_FLOW_CONTROL_POLARITY 8 8 OTG_FLOW_CONTROL_GRANULARITY 16 16 OTG_FLOW_CONTROL_INPUT_STATUS 24 24 mmOTG4_OTG_STEREO_FORCE_NEXT_EYE 0 0x1d3f 3 0 2 OTG_STEREO_FORCE_NEXT_EYE 0 1 OTG_AVSYNC_FRAME_COUNTER 8 15 OTG_AVSYNC_LINE_COUNTER 16 28 mmOTG4_OTG_AVSYNC_COUNTER 0 0x1d40 1 0 2 OTG_AVSYNC_COUNTER 0 31 mmOTG4_OTG_CONTROL 0 0x1d41 6 0 2 OTG_MASTER_EN 0 0 OTG_DISABLE_POINT_CNTL 8 9 OTG_START_POINT_CNTL 12 12 OTG_FIELD_NUMBER_CNTL 13 13 OTG_FIELD_NUMBER_POLARITY 14 14 OTG_CURRENT_MASTER_EN_STATE 16 16 mmOTG4_OTG_BLANK_CONTROL 0 0x1d42 3 0 2 OTG_CURRENT_BLANK_STATE 0 0 OTG_BLANK_DATA_EN 8 8 OTG_BLANK_DE_MODE 16 16 mmOTG4_OTG_PIPE_ABORT_CONTROL 0 0x1d43 2 0 2 OTG_PIPE_ABORT 0 0 OTG_PIPE_ABORT_DONE 8 8 mmOTG4_OTG_INTERLACE_CONTROL 0 0x1d44 2 0 2 OTG_INTERLACE_ENABLE 0 0 OTG_INTERLACE_FORCE_NEXT_FIELD 16 17 mmOTG4_OTG_INTERLACE_STATUS 0 0x1d45 2 0 2 OTG_INTERLACE_CURRENT_FIELD 0 0 OTG_INTERLACE_NEXT_FIELD 1 1 mmOTG4_OTG_FIELD_INDICATION_CONTROL 0 0x1d46 2 0 2 OTG_FIELD_INDICATION_OUTPUT_POLARITY 0 0 OTG_FIELD_ALIGNMENT 1 1 mmOTG4_OTG_PIXEL_DATA_READBACK0 0 0x1d47 2 0 2 OTG_PIXEL_DATA_BLUE_CB 0 15 OTG_PIXEL_DATA_GREEN_Y 16 31 mmOTG4_OTG_PIXEL_DATA_READBACK1 0 0x1d48 1 0 2 OTG_PIXEL_DATA_RED_CR 0 15 mmOTG4_OTG_STATUS 0 0x1d49 8 0 2 OTG_V_BLANK 0 0 OTG_V_ACTIVE_DISP 1 1 OTG_V_SYNC_A 2 2 OTG_V_UPDATE 3 3 OTG_V_BLANK_3D_STRUCTURE 5 5 OTG_H_BLANK 16 16 OTG_H_ACTIVE_DISP 17 17 OTG_H_SYNC_A 18 18 mmOTG4_OTG_STATUS_POSITION 0 0x1d4a 2 0 2 OTG_VERT_COUNT 0 14 OTG_HORZ_COUNT 16 30 mmOTG4_OTG_NOM_VERT_POSITION 0 0x1d4b 1 0 2 OTG_VERT_COUNT_NOM 0 14 mmOTG4_OTG_STATUS_FRAME_COUNT 0 0x1d4c 1 0 2 OTG_FRAME_COUNT 0 23 mmOTG4_OTG_STATUS_VF_COUNT 0 0x1d4d 1 0 2 OTG_VF_COUNT 0 30 mmOTG4_OTG_STATUS_HV_COUNT 0 0x1d4e 1 0 2 OTG_HV_COUNT 0 30 mmOTG4_OTG_COUNT_CONTROL 0 0x1d4f 2 0 2 OTG_HORZ_COUNT_BY2_EN 0 0 OTG_HORZ_REPETITION_COUNT 1 4 mmOTG4_OTG_COUNT_RESET 0 0x1d50 1 0 2 OTG_RESET_FRAME_COUNT 0 0 mmOTG4_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE 0 0x1d51 1 0 2 OTG_MANUAL_FORCE_VSYNC_NEXT_LINE 0 0 mmOTG4_OTG_VERT_SYNC_CONTROL 0 0x1d52 3 0 2 OTG_FORCE_VSYNC_NEXT_LINE_OCCURRED 0 0 OTG_FORCE_VSYNC_NEXT_LINE_CLEAR 8 8 OTG_AUTO_FORCE_VSYNC_MODE 16 17 mmOTG4_OTG_STEREO_STATUS 0 0x1d53 7 0 2 OTG_STEREO_CURRENT_EYE 0 0 OTG_STEREO_SYNC_OUTPUT 8 8 OTG_STEREO_SYNC_SELECT 16 16 OTG_STEREO_EYE_FLAG 20 20 OTG_STEREO_FORCE_NEXT_EYE_PENDING 24 25 OTG_CURRENT_3D_STRUCTURE_STATE 30 30 OTG_CURRENT_STEREOSYNC_EN_STATE 31 31 mmOTG4_OTG_STEREO_CONTROL 0 0x1d54 7 0 2 OTG_STEREO_SYNC_OUTPUT_LINE_NUM 0 14 OTG_STEREO_SYNC_OUTPUT_POLARITY 15 15 OTG_STEREO_EYE_FLAG_POLARITY 17 17 OTG_DISABLE_STEREOSYNC_OUTPUT_FOR_DP 18 18 OTG_DISABLE_FIELD_NUM 19 19 OTG_DISABLE_V_BLANK_FOR_DP_FIX 20 20 OTG_STEREO_EN 24 24 mmOTG4_OTG_SNAPSHOT_STATUS 0 0x1d55 3 0 2 OTG_SNAPSHOT_OCCURRED 0 0 OTG_SNAPSHOT_CLEAR 1 1 OTG_SNAPSHOT_MANUAL_TRIGGER 2 2 mmOTG4_OTG_SNAPSHOT_CONTROL 0 0x1d56 1 0 2 OTG_AUTO_SNAPSHOT_TRIG_SEL 0 1 mmOTG4_OTG_SNAPSHOT_POSITION 0 0x1d57 2 0 2 OTG_SNAPSHOT_VERT_COUNT 0 14 OTG_SNAPSHOT_HORZ_COUNT 16 30 mmOTG4_OTG_SNAPSHOT_FRAME 0 0x1d58 1 0 2 OTG_SNAPSHOT_FRAME_COUNT 0 23 mmOTG4_OTG_INTERRUPT_CONTROL 0 0x1d59 14 0 2 OTG_SNAPSHOT_INT_MSK 0 0 OTG_SNAPSHOT_INT_TYPE 1 1 OTG_FORCE_COUNT_NOW_INT_MSK 8 8 OTG_FORCE_COUNT_NOW_INT_TYPE 9 9 OTG_FORCE_VSYNC_NEXT_LINE_INT_MSK 16 16 OTG_FORCE_VSYNC_NEXT_LINE_INT_TYPE 17 17 OTG_TRIGA_INT_MSK 24 24 OTG_TRIGB_INT_MSK 25 25 OTG_TRIGA_INT_TYPE 26 26 OTG_TRIGB_INT_TYPE 27 27 OTG_VSYNC_NOM_INT_MSK 28 28 OTG_VSYNC_NOM_INT_TYPE 29 29 OTG_GSL_VSYNC_GAP_INT_MSK 30 30 OTG_GSL_VSYNC_GAP_INT_TYPE 31 31 mmOTG4_OTG_UPDATE_LOCK 0 0x1d5a 1 0 2 OTG_UPDATE_LOCK 0 0 mmOTG4_OTG_DOUBLE_BUFFER_CONTROL 0 0x1d5b 10 0 2 OTG_UPDATE_PENDING 0 0 OTG_H_TIMING_DIV_BY2_DB_UPDATE_PENDING 2 2 OTG_BLANK_DATA_EN_UPDATE_PENDING 3 3 OTG_RANGE_TIMING_DBUF_UPDATE_PENDING 4 4 OTG_TIMING_DB_UPDATE_PENDING 5 5 OTG_3D_CTRL_DB_UPDATE_PENDING 6 6 OTG_3D_STRUCTURE_EN_DB_UPDATE_PENDING 7 7 OTG_UPDATE_INSTANTLY 8 8 OTG_BLANK_DATA_DOUBLE_BUFFER_EN 16 16 OTG_RANGE_TIMING_DBUF_UPDATE_MODE 24 25 mmOTG4_OTG_TEST_PATTERN_CONTROL 0 0x1d5c 4 0 2 OTG_TEST_PATTERN_EN 0 0 OTG_TEST_PATTERN_MODE 8 10 OTG_TEST_PATTERN_DYNAMIC_RANGE 16 16 OTG_TEST_PATTERN_COLOR_FORMAT 24 31 mmOTG4_OTG_TEST_PATTERN_PARAMETERS 0 0x1d5d 5 0 2 OTG_TEST_PATTERN_INC0 0 3 OTG_TEST_PATTERN_INC1 4 7 OTG_TEST_PATTERN_VRES 8 11 OTG_TEST_PATTERN_HRES 12 15 OTG_TEST_PATTERN_RAMP0_OFFSET 16 31 mmOTG4_OTG_TEST_PATTERN_COLOR 0 0x1d5e 2 0 2 OTG_TEST_PATTERN_DATA 0 15 OTG_TEST_PATTERN_MASK 16 21 mmOTG4_OTG_MASTER_EN 0 0x1d5f 1 0 2 OTG_MASTER_EN 0 0 mmOTG4_OTG_BLANK_DATA_COLOR 0 0x1d61 3 0 2 OTG_BLANK_DATA_COLOR_BLUE_CB 0 9 OTG_BLANK_DATA_COLOR_GREEN_Y 10 19 OTG_BLANK_DATA_COLOR_RED_CR 20 29 mmOTG4_OTG_BLANK_DATA_COLOR_EXT 0 0x1d62 3 0 2 OTG_BLANK_DATA_COLOR_BLUE_CB_EXT 0 5 OTG_BLANK_DATA_COLOR_GREEN_Y_EXT 8 13 OTG_BLANK_DATA_COLOR_RED_CR_EXT 16 21 mmOTG4_OTG_BLACK_COLOR 0 0x1d63 3 0 2 OTG_BLACK_COLOR_B_CB 0 9 OTG_BLACK_COLOR_G_Y 10 19 OTG_BLACK_COLOR_R_CR 20 29 mmOTG4_OTG_BLACK_COLOR_EXT 0 0x1d64 3 0 2 OTG_BLACK_COLOR_B_CB_EXT 0 5 OTG_BLACK_COLOR_G_Y_EXT 8 13 OTG_BLACK_COLOR_R_CR_EXT 16 21 mmOTG4_OTG_VERTICAL_INTERRUPT0_POSITION 0 0x1d65 2 0 2 OTG_VERTICAL_INTERRUPT0_LINE_START 0 14 OTG_VERTICAL_INTERRUPT0_LINE_END 16 30 mmOTG4_OTG_VERTICAL_INTERRUPT0_CONTROL 0 0x1d66 6 0 2 OTG_VERTICAL_INTERRUPT0_OUTPUT_POLARITY 4 4 OTG_VERTICAL_INTERRUPT0_INT_ENABLE 8 8 OTG_VERTICAL_INTERRUPT0_STATUS 12 12 OTG_VERTICAL_INTERRUPT0_INT_STATUS 16 16 OTG_VERTICAL_INTERRUPT0_CLEAR 20 20 OTG_VERTICAL_INTERRUPT0_INT_TYPE 24 24 mmOTG4_OTG_VERTICAL_INTERRUPT1_POSITION 0 0x1d67 1 0 2 OTG_VERTICAL_INTERRUPT1_LINE_START 0 14 mmOTG4_OTG_VERTICAL_INTERRUPT1_CONTROL 0 0x1d68 5 0 2 OTG_VERTICAL_INTERRUPT1_INT_ENABLE 8 8 OTG_VERTICAL_INTERRUPT1_STATUS 12 12 OTG_VERTICAL_INTERRUPT1_INT_STATUS 16 16 OTG_VERTICAL_INTERRUPT1_CLEAR 20 20 OTG_VERTICAL_INTERRUPT1_INT_TYPE 24 24 mmOTG4_OTG_VERTICAL_INTERRUPT2_POSITION 0 0x1d69 1 0 2 OTG_VERTICAL_INTERRUPT2_LINE_START 0 14 mmOTG4_OTG_VERTICAL_INTERRUPT2_CONTROL 0 0x1d6a 5 0 2 OTG_VERTICAL_INTERRUPT2_INT_ENABLE 8 8 OTG_VERTICAL_INTERRUPT2_STATUS 12 12 OTG_VERTICAL_INTERRUPT2_INT_STATUS 16 16 OTG_VERTICAL_INTERRUPT2_CLEAR 20 20 OTG_VERTICAL_INTERRUPT2_INT_TYPE 24 24 mmOTG4_OTG_CRC_CNTL 0 0x1d6b 16 0 2 OTG_CRC_EN 0 0 OTG_CRC_DUAL_LINK_EN 1 1 OTG_CRC_DUAL_LINK_MODE 2 2 OTG_CRC_BLANK_ONLY 3 3 OTG_CRC_CONT_EN 4 4 OTG_CRC_CAPTURE_START_SEL 5 6 OTG_CRC_STEREO_MODE 8 9 OTG_CRC_INTERLACE_MODE 12 13 OTG_CRC_MULTI_STREAM_MODE 16 18 OTG_CRC_USE_NEW_AND_REPEATED_PIXELS 19 19 OTG_CRC0_SELECT 20 22 OTG_CRC1_SELECT 24 26 OTG_ONE_SHOT_CRC0_PENDING 28 28 OTG_ONE_SHOT_CRC1_PENDING 29 29 OTG_ONE_SHOT_CRC2_PENDING 30 30 OTG_ONE_SHOT_CRC3_PENDING 31 31 mmOTG4_OTG_CRC0_WINDOWA_X_CONTROL 0 0x1d6c 2 0 2 OTG_CRC0_WINDOWA_X_START 0 14 OTG_CRC0_WINDOWA_X_END 16 30 mmOTG4_OTG_CRC0_WINDOWA_Y_CONTROL 0 0x1d6d 2 0 2 OTG_CRC0_WINDOWA_Y_START 0 14 OTG_CRC0_WINDOWA_Y_END 16 30 mmOTG4_OTG_CRC0_WINDOWB_X_CONTROL 0 0x1d6e 2 0 2 OTG_CRC0_WINDOWB_X_START 0 14 OTG_CRC0_WINDOWB_X_END 16 30 mmOTG4_OTG_CRC0_WINDOWB_Y_CONTROL 0 0x1d6f 2 0 2 OTG_CRC0_WINDOWB_Y_START 0 14 OTG_CRC0_WINDOWB_Y_END 16 30 mmOTG4_OTG_CRC0_DATA_RG 0 0x1d70 2 0 2 CRC0_R_CR 0 15 CRC0_G_Y 16 31 mmOTG4_OTG_CRC0_DATA_B 0 0x1d71 2 0 2 CRC0_B_CB 0 15 CRC0_C 16 31 mmOTG4_OTG_CRC1_WINDOWA_X_CONTROL 0 0x1d72 2 0 2 OTG_CRC1_WINDOWA_X_START 0 14 OTG_CRC1_WINDOWA_X_END 16 30 mmOTG4_OTG_CRC1_WINDOWA_Y_CONTROL 0 0x1d73 2 0 2 OTG_CRC1_WINDOWA_Y_START 0 14 OTG_CRC1_WINDOWA_Y_END 16 30 mmOTG4_OTG_CRC1_WINDOWB_X_CONTROL 0 0x1d74 2 0 2 OTG_CRC1_WINDOWB_X_START 0 14 OTG_CRC1_WINDOWB_X_END 16 30 mmOTG4_OTG_CRC1_WINDOWB_Y_CONTROL 0 0x1d75 2 0 2 OTG_CRC1_WINDOWB_Y_START 0 14 OTG_CRC1_WINDOWB_Y_END 16 30 mmOTG4_OTG_CRC1_DATA_RG 0 0x1d76 2 0 2 CRC1_R_CR 0 15 CRC1_G_Y 16 31 mmOTG4_OTG_CRC1_DATA_B 0 0x1d77 2 0 2 CRC1_B_CB 0 15 CRC1_C 16 31 mmOTG4_OTG_CRC2_DATA_RG 0 0x1d78 2 0 2 CRC2_R_CR 0 15 CRC2_G_Y 16 31 mmOTG4_OTG_CRC2_DATA_B 0 0x1d79 2 0 2 CRC2_B_CB 0 15 CRC2_C 16 31 mmOTG4_OTG_CRC3_DATA_RG 0 0x1d7a 2 0 2 CRC3_R_CR 0 15 CRC3_G_Y 16 31 mmOTG4_OTG_CRC3_DATA_B 0 0x1d7b 2 0 2 CRC3_B_CB 0 15 CRC3_C 16 31 mmOTG4_OTG_CRC_SIG_RED_GREEN_MASK 0 0x1d7c 2 0 2 OTG_CRC_SIG_RED_MASK 0 15 OTG_CRC_SIG_GREEN_MASK 16 31 mmOTG4_OTG_CRC_SIG_BLUE_CONTROL_MASK 0 0x1d7d 2 0 2 OTG_CRC_SIG_BLUE_MASK 0 15 OTG_CRC_SIG_CONTROL_MASK 16 31 mmOTG4_OTG_STATIC_SCREEN_CONTROL 0 0x1d84 9 0 2 OTG_STATIC_SCREEN_EVENT_MASK 0 15 OTG_STATIC_SCREEN_FRAME_COUNT 16 23 OTG_CPU_SS_INT_ENABLE 24 24 OTG_SS_STATUS 25 25 OTG_CPU_SS_INT_STATUS 26 26 OTG_CPU_SS_INT_CLEAR 27 27 OTG_CPU_SS_INT_TYPE 28 28 OTG_STATIC_SCREEN_OVERRIDE 30 30 OTG_STATIC_SCREEN_OVERRIDE_VALUE 31 31 mmOTG4_OTG_3D_STRUCTURE_CONTROL 0 0x1d85 6 0 2 OTG_3D_STRUCTURE_EN 0 0 OTG_3D_STRUCTURE_V_UPDATE_MODE 8 9 OTG_3D_STRUCTURE_STEREO_SEL_OVR 12 12 OTG_3D_STRUCTURE_F_COUNT_RESET 16 16 OTG_3D_STRUCTURE_F_COUNT_RESET_PENDING 17 17 OTG_3D_STRUCTURE_F_COUNT 18 19 mmOTG4_OTG_GSL_VSYNC_GAP 0 0x1d86 8 0 2 OTG_GSL_VSYNC_GAP_LIMIT 0 7 OTG_GSL_VSYNC_GAP_DELAY 8 15 OTG_GSL_VSYNC_GAP_SOURCE_SEL 16 16 OTG_GSL_VSYNC_GAP_MODE 17 18 OTG_GSL_VSYNC_GAP_CLEAR 19 19 OTG_GSL_VSYNC_GAP_OCCURRED 20 20 OTG_GSL_VSYNC_GAP_MASTER_FASTER 23 23 OTG_GSL_VSYNC_GAP 24 31 mmOTG4_OTG_MASTER_UPDATE_MODE 0 0x1d87 1 0 2 MASTER_UPDATE_INTERLACED_MODE 0 1 mmOTG4_OTG_CLOCK_CONTROL 0 0x1d88 5 0 2 OTG_CLOCK_EN 0 0 OTG_CLOCK_GATE_DIS 1 1 OTG_SOFT_RESET 4 4 OTG_CLOCK_ON 8 8 OTG_BUSY 16 16 mmOTG4_OTG_VSTARTUP_PARAM 0 0x1d89 1 0 2 VSTARTUP_START 0 9 mmOTG4_OTG_VUPDATE_PARAM 0 0x1d8a 2 0 2 VUPDATE_OFFSET 0 15 VUPDATE_WIDTH 16 25 mmOTG4_OTG_VREADY_PARAM 0 0x1d8b 1 0 2 VREADY_OFFSET 0 15 mmOTG4_OTG_GLOBAL_SYNC_STATUS 0 0x1d8c 25 0 2 VSTARTUP_INT_EN 0 0 VSTARTUP_INT_TYPE 1 1 VSTARTUP_EVENT_OCCURRED 2 2 VSTARTUP_INT_STATUS 3 3 VSTARTUP_EVENT_CLEAR 4 4 VUPDATE_INT_EN 5 5 VUPDATE_INT_TYPE 6 6 VUPDATE_INT_POSITION_SEL 7 7 VUPDATE_EVENT_OCCURRED 8 8 VUPDATE_INT_STATUS 9 9 VUPDATE_EVENT_CLEAR 10 10 VUPDATE_STATUS 11 11 VUPDATE_NO_LOCK_INT_EN 12 12 VUPDATE_NO_LOCK_INT_TYPE 13 13 VUPDATE_NO_LOCK_EVENT_OCCURRED 14 14 VUPDATE_NO_LOCK_INT_STATUS 15 15 VUPDATE_NO_LOCK_EVENT_CLEAR 16 16 VUPDATE_NO_LOCK_STATUS 17 17 VREADY_INT_EN 18 18 VREADY_INT_TYPE 19 19 VREADY_EVENT_OCCURRED 20 20 VREADY_INT_STATUS 21 21 VREADY_EVENT_CLEAR 22 22 STEREO_SELECT_STATUS 24 24 FIELD_NUMBER_STATUS 25 25 mmOTG4_OTG_MASTER_UPDATE_LOCK 0 0x1d8d 2 0 2 OTG_MASTER_UPDATE_LOCK 0 0 UPDATE_LOCK_STATUS 8 8 mmOTG4_OTG_GSL_CONTROL 0 0x1d8e 6 0 2 OTG_GSL0_EN 0 0 OTG_GSL1_EN 1 1 OTG_GSL2_EN 2 2 OTG_GSL_MASTER_EN 3 3 OTG_GSL_FORCE_DELAY 16 20 OTG_GSL_CHECK_ALL_FIELDS 28 28 mmOTG4_OTG_GSL_WINDOW_X 0 0x1d8f 2 0 2 OTG_GSL_WINDOW_START_X 0 14 OTG_GSL_WINDOW_END_X 16 30 mmOTG4_OTG_GSL_WINDOW_Y 0 0x1d90 2 0 2 OTG_GSL_WINDOW_START_Y 0 14 OTG_GSL_WINDOW_END_Y 16 30 mmOTG4_OTG_VUPDATE_KEEPOUT 0 0x1d91 3 0 2 MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_START_OFFSET 0 15 MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_END_OFFSET 16 25 OTG_MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_EN 31 31 mmOTG4_OTG_GLOBAL_CONTROL0 0 0x1d92 3 0 2 OTG_MASTER_UPDATE_LOCK_HTOTAL_KEEPOUT 0 7 OTG_MASTER_UPDATE_LOCK_HTOTAL_KEEPOUT_EN 8 8 OTG_MASTER_UPDATE_LOCK_SEL 25 27 mmOTG4_OTG_GLOBAL_CONTROL1 0 0x1d93 3 0 2 MASTER_UPDATE_LOCK_DB_X 0 14 MASTER_UPDATE_LOCK_DB_Y 16 30 MASTER_UPDATE_LOCK_DB_EN 31 31 mmOTG4_OTG_GLOBAL_CONTROL2 0 0x1d94 4 0 2 DIG_UPDATE_LOCATION 0 9 GLOBAL_UPDATE_LOCK_EN 10 10 MANUAL_FLOW_CONTROL_SEL 16 18 DCCG_VUPDATE_MODE 31 31 mmOTG4_OTG_GLOBAL_CONTROL3 0 0x1d95 3 0 2 MASTER_UPDATE_LOCK_DB_FIELD 0 1 MASTER_UPDATE_LOCK_DB_STEREO_SEL 4 5 MASTER_UPDATE_LOCK_DB_FIELD_STEREO_FLAG_SEL 8 8 mmOTG4_OTG_TRIG_MANUAL_CONTROL 0 0x1d96 1 0 2 TRIG_MANUAL_CONTROL 0 0 mmOTG4_OTG_MANUAL_FLOW_CONTROL 0 0x1d97 1 0 2 MANUAL_FLOW_CONTROL 0 0 mmOTG4_OTG_RANGE_TIMING_INT_STATUS 0 0x1d98 5 0 2 OTG_RANGE_TIMING_UPDATE_OCCURRED 0 0 OTG_RANGE_TIMING_UPDATE_OCCURRED_INT 4 4 OTG_RANGE_TIMING_UPDATE_OCCURRED_CLEAR 8 8 OTG_RANGE_TIMING_UPDATE_OCCURRED_INT_MSK 12 12 OTG_RANGE_TIMING_UPDATE_OCCURRED_INT_TYPE 16 16 mmOTG4_OTG_DRR_CONTROL 0 0x1d99 2 0 2 OTG_DRR_AVERAGE_FRAME 0 2 OTG_V_TOTAL_LAST_USED_BY_DRR 16 30 mmOTG4_OTG_REQUEST_CONTROL 0 0x1d9a 1 0 2 OTG_REQUEST_MODE_FOR_H_DUPLICATE 0 0 mmOTG4_OTG_SPARE_REGISTER 0 0x1d9b 1 0 2 OTG_SPARE_REG 0 31 mmOTG5_OTG_H_TOTAL 0 0x1daa 1 0 2 OTG_H_TOTAL 0 14 mmOTG5_OTG_H_BLANK_START_END 0 0x1dab 2 0 2 OTG_H_BLANK_START 0 14 OTG_H_BLANK_END 16 30 mmOTG5_OTG_H_SYNC_A 0 0x1dac 2 0 2 OTG_H_SYNC_A_START 0 14 OTG_H_SYNC_A_END 16 30 mmOTG5_OTG_H_SYNC_A_CNTL 0 0x1dad 3 0 2 OTG_H_SYNC_A_POL 0 0 OTG_COMP_SYNC_A_EN 16 16 OTG_H_SYNC_A_CUTOFF 17 17 mmOTG5_OTG_H_TIMING_CNTL 0 0x1dae 2 0 2 OTG_H_TIMING_DIV_BY2 0 0 OTG_H_TIMING_DIV_BY2_UPDATE_MODE 8 8 mmOTG5_OTG_V_TOTAL 0 0x1daf 1 0 2 OTG_V_TOTAL 0 14 mmOTG5_OTG_V_TOTAL_MIN 0 0x1db0 1 0 2 OTG_V_TOTAL_MIN 0 14 mmOTG5_OTG_V_TOTAL_MAX 0 0x1db1 1 0 2 OTG_V_TOTAL_MAX 0 14 mmOTG5_OTG_V_TOTAL_MID 0 0x1db2 1 0 2 OTG_V_TOTAL_MID 0 14 mmOTG5_OTG_V_TOTAL_CONTROL 0 0x1db3 8 0 2 OTG_V_TOTAL_MIN_SEL 0 0 OTG_V_TOTAL_MAX_SEL 1 1 OTG_VTOTAL_MID_REPLACING_MAX_EN 2 2 OTG_VTOTAL_MID_REPLACING_MIN_EN 3 3 OTG_FORCE_LOCK_ON_EVENT 4 4 OTG_SET_V_TOTAL_MIN_MASK_EN 7 7 OTG_VTOTAL_MID_FRAME_NUM 8 15 OTG_SET_V_TOTAL_MIN_MASK 16 31 mmOTG5_OTG_V_TOTAL_INT_STATUS 0 0x1db4 4 0 2 OTG_SET_V_TOTAL_MIN_EVENT_OCCURED 0 0 OTG_SET_V_TOTAL_MIN_EVENT_OCCURED_INT 4 4 OTG_SET_V_TOTAL_MIN_EVENT_OCCURED_ACK 8 8 OTG_SET_V_TOTAL_MIN_EVENT_OCCURED_MSK 12 12 mmOTG5_OTG_VSYNC_NOM_INT_STATUS 0 0x1db5 2 0 2 OTG_VSYNC_NOM 0 0 OTG_VSYNC_NOM_INT_CLEAR 4 4 mmOTG5_OTG_V_BLANK_START_END 0 0x1db6 2 0 2 OTG_V_BLANK_START 0 14 OTG_V_BLANK_END 16 30 mmOTG5_OTG_V_SYNC_A 0 0x1db7 2 0 2 OTG_V_SYNC_A_START 0 14 OTG_V_SYNC_A_END 16 30 mmOTG5_OTG_V_SYNC_A_CNTL 0 0x1db8 1 0 2 OTG_V_SYNC_A_POL 0 0 mmOTG5_OTG_TRIGA_CNTL 0 0x1db9 12 0 2 OTG_TRIGA_SOURCE_SELECT 0 4 OTG_TRIGA_SOURCE_PIPE_SELECT 5 7 OTG_TRIGA_POLARITY_SELECT 8 10 OTG_TRIGA_RESYNC_BYPASS_EN 11 11 OTG_TRIGA_INPUT_STATUS 12 12 OTG_TRIGA_POLARITY_STATUS 13 13 OTG_TRIGA_OCCURRED 14 14 OTG_TRIGA_RISING_EDGE_DETECT_CNTL 16 17 OTG_TRIGA_FALLING_EDGE_DETECT_CNTL 18 19 OTG_TRIGA_FREQUENCY_SELECT 20 21 OTG_TRIGA_DELAY 24 28 OTG_TRIGA_CLEAR 31 31 mmOTG5_OTG_TRIGA_MANUAL_TRIG 0 0x1dba 1 0 2 OTG_TRIGA_MANUAL_TRIG 0 0 mmOTG5_OTG_TRIGB_CNTL 0 0x1dbb 12 0 2 OTG_TRIGB_SOURCE_SELECT 0 4 OTG_TRIGB_SOURCE_PIPE_SELECT 5 7 OTG_TRIGB_POLARITY_SELECT 8 10 OTG_TRIGB_RESYNC_BYPASS_EN 11 11 OTG_TRIGB_INPUT_STATUS 12 12 OTG_TRIGB_POLARITY_STATUS 13 13 OTG_TRIGB_OCCURRED 14 14 OTG_TRIGB_RISING_EDGE_DETECT_CNTL 16 17 OTG_TRIGB_FALLING_EDGE_DETECT_CNTL 18 19 OTG_TRIGB_FREQUENCY_SELECT 20 21 OTG_TRIGB_DELAY 24 28 OTG_TRIGB_CLEAR 31 31 mmOTG5_OTG_TRIGB_MANUAL_TRIG 0 0x1dbc 1 0 2 OTG_TRIGB_MANUAL_TRIG 0 0 mmOTG5_OTG_FORCE_COUNT_NOW_CNTL 0 0x1dbd 5 0 2 OTG_FORCE_COUNT_NOW_MODE 0 1 OTG_FORCE_COUNT_NOW_CHECK 4 4 OTG_FORCE_COUNT_NOW_TRIG_SEL 8 8 OTG_FORCE_COUNT_NOW_OCCURRED 16 16 OTG_FORCE_COUNT_NOW_CLEAR 24 24 mmOTG5_OTG_FLOW_CONTROL 0 0x1dbe 4 0 2 OTG_FLOW_CONTROL_SOURCE_SELECT 0 4 OTG_FLOW_CONTROL_POLARITY 8 8 OTG_FLOW_CONTROL_GRANULARITY 16 16 OTG_FLOW_CONTROL_INPUT_STATUS 24 24 mmOTG5_OTG_STEREO_FORCE_NEXT_EYE 0 0x1dbf 3 0 2 OTG_STEREO_FORCE_NEXT_EYE 0 1 OTG_AVSYNC_FRAME_COUNTER 8 15 OTG_AVSYNC_LINE_COUNTER 16 28 mmOTG5_OTG_AVSYNC_COUNTER 0 0x1dc0 1 0 2 OTG_AVSYNC_COUNTER 0 31 mmOTG5_OTG_CONTROL 0 0x1dc1 6 0 2 OTG_MASTER_EN 0 0 OTG_DISABLE_POINT_CNTL 8 9 OTG_START_POINT_CNTL 12 12 OTG_FIELD_NUMBER_CNTL 13 13 OTG_FIELD_NUMBER_POLARITY 14 14 OTG_CURRENT_MASTER_EN_STATE 16 16 mmOTG5_OTG_BLANK_CONTROL 0 0x1dc2 3 0 2 OTG_CURRENT_BLANK_STATE 0 0 OTG_BLANK_DATA_EN 8 8 OTG_BLANK_DE_MODE 16 16 mmOTG5_OTG_PIPE_ABORT_CONTROL 0 0x1dc3 2 0 2 OTG_PIPE_ABORT 0 0 OTG_PIPE_ABORT_DONE 8 8 mmOTG5_OTG_INTERLACE_CONTROL 0 0x1dc4 2 0 2 OTG_INTERLACE_ENABLE 0 0 OTG_INTERLACE_FORCE_NEXT_FIELD 16 17 mmOTG5_OTG_INTERLACE_STATUS 0 0x1dc5 2 0 2 OTG_INTERLACE_CURRENT_FIELD 0 0 OTG_INTERLACE_NEXT_FIELD 1 1 mmOTG5_OTG_FIELD_INDICATION_CONTROL 0 0x1dc6 2 0 2 OTG_FIELD_INDICATION_OUTPUT_POLARITY 0 0 OTG_FIELD_ALIGNMENT 1 1 mmOTG5_OTG_PIXEL_DATA_READBACK0 0 0x1dc7 2 0 2 OTG_PIXEL_DATA_BLUE_CB 0 15 OTG_PIXEL_DATA_GREEN_Y 16 31 mmOTG5_OTG_PIXEL_DATA_READBACK1 0 0x1dc8 1 0 2 OTG_PIXEL_DATA_RED_CR 0 15 mmOTG5_OTG_STATUS 0 0x1dc9 8 0 2 OTG_V_BLANK 0 0 OTG_V_ACTIVE_DISP 1 1 OTG_V_SYNC_A 2 2 OTG_V_UPDATE 3 3 OTG_V_BLANK_3D_STRUCTURE 5 5 OTG_H_BLANK 16 16 OTG_H_ACTIVE_DISP 17 17 OTG_H_SYNC_A 18 18 mmOTG5_OTG_STATUS_POSITION 0 0x1dca 2 0 2 OTG_VERT_COUNT 0 14 OTG_HORZ_COUNT 16 30 mmOTG5_OTG_NOM_VERT_POSITION 0 0x1dcb 1 0 2 OTG_VERT_COUNT_NOM 0 14 mmOTG5_OTG_STATUS_FRAME_COUNT 0 0x1dcc 1 0 2 OTG_FRAME_COUNT 0 23 mmOTG5_OTG_STATUS_VF_COUNT 0 0x1dcd 1 0 2 OTG_VF_COUNT 0 30 mmOTG5_OTG_STATUS_HV_COUNT 0 0x1dce 1 0 2 OTG_HV_COUNT 0 30 mmOTG5_OTG_COUNT_CONTROL 0 0x1dcf 2 0 2 OTG_HORZ_COUNT_BY2_EN 0 0 OTG_HORZ_REPETITION_COUNT 1 4 mmOTG5_OTG_COUNT_RESET 0 0x1dd0 1 0 2 OTG_RESET_FRAME_COUNT 0 0 mmOTG5_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE 0 0x1dd1 1 0 2 OTG_MANUAL_FORCE_VSYNC_NEXT_LINE 0 0 mmOTG5_OTG_VERT_SYNC_CONTROL 0 0x1dd2 3 0 2 OTG_FORCE_VSYNC_NEXT_LINE_OCCURRED 0 0 OTG_FORCE_VSYNC_NEXT_LINE_CLEAR 8 8 OTG_AUTO_FORCE_VSYNC_MODE 16 17 mmOTG5_OTG_STEREO_STATUS 0 0x1dd3 7 0 2 OTG_STEREO_CURRENT_EYE 0 0 OTG_STEREO_SYNC_OUTPUT 8 8 OTG_STEREO_SYNC_SELECT 16 16 OTG_STEREO_EYE_FLAG 20 20 OTG_STEREO_FORCE_NEXT_EYE_PENDING 24 25 OTG_CURRENT_3D_STRUCTURE_STATE 30 30 OTG_CURRENT_STEREOSYNC_EN_STATE 31 31 mmOTG5_OTG_STEREO_CONTROL 0 0x1dd4 7 0 2 OTG_STEREO_SYNC_OUTPUT_LINE_NUM 0 14 OTG_STEREO_SYNC_OUTPUT_POLARITY 15 15 OTG_STEREO_EYE_FLAG_POLARITY 17 17 OTG_DISABLE_STEREOSYNC_OUTPUT_FOR_DP 18 18 OTG_DISABLE_FIELD_NUM 19 19 OTG_DISABLE_V_BLANK_FOR_DP_FIX 20 20 OTG_STEREO_EN 24 24 mmOTG5_OTG_SNAPSHOT_STATUS 0 0x1dd5 3 0 2 OTG_SNAPSHOT_OCCURRED 0 0 OTG_SNAPSHOT_CLEAR 1 1 OTG_SNAPSHOT_MANUAL_TRIGGER 2 2 mmOTG5_OTG_SNAPSHOT_CONTROL 0 0x1dd6 1 0 2 OTG_AUTO_SNAPSHOT_TRIG_SEL 0 1 mmOTG5_OTG_SNAPSHOT_POSITION 0 0x1dd7 2 0 2 OTG_SNAPSHOT_VERT_COUNT 0 14 OTG_SNAPSHOT_HORZ_COUNT 16 30 mmOTG5_OTG_SNAPSHOT_FRAME 0 0x1dd8 1 0 2 OTG_SNAPSHOT_FRAME_COUNT 0 23 mmOTG5_OTG_INTERRUPT_CONTROL 0 0x1dd9 14 0 2 OTG_SNAPSHOT_INT_MSK 0 0 OTG_SNAPSHOT_INT_TYPE 1 1 OTG_FORCE_COUNT_NOW_INT_MSK 8 8 OTG_FORCE_COUNT_NOW_INT_TYPE 9 9 OTG_FORCE_VSYNC_NEXT_LINE_INT_MSK 16 16 OTG_FORCE_VSYNC_NEXT_LINE_INT_TYPE 17 17 OTG_TRIGA_INT_MSK 24 24 OTG_TRIGB_INT_MSK 25 25 OTG_TRIGA_INT_TYPE 26 26 OTG_TRIGB_INT_TYPE 27 27 OTG_VSYNC_NOM_INT_MSK 28 28 OTG_VSYNC_NOM_INT_TYPE 29 29 OTG_GSL_VSYNC_GAP_INT_MSK 30 30 OTG_GSL_VSYNC_GAP_INT_TYPE 31 31 mmOTG5_OTG_UPDATE_LOCK 0 0x1dda 1 0 2 OTG_UPDATE_LOCK 0 0 mmOTG5_OTG_DOUBLE_BUFFER_CONTROL 0 0x1ddb 10 0 2 OTG_UPDATE_PENDING 0 0 OTG_H_TIMING_DIV_BY2_DB_UPDATE_PENDING 2 2 OTG_BLANK_DATA_EN_UPDATE_PENDING 3 3 OTG_RANGE_TIMING_DBUF_UPDATE_PENDING 4 4 OTG_TIMING_DB_UPDATE_PENDING 5 5 OTG_3D_CTRL_DB_UPDATE_PENDING 6 6 OTG_3D_STRUCTURE_EN_DB_UPDATE_PENDING 7 7 OTG_UPDATE_INSTANTLY 8 8 OTG_BLANK_DATA_DOUBLE_BUFFER_EN 16 16 OTG_RANGE_TIMING_DBUF_UPDATE_MODE 24 25 mmOTG5_OTG_TEST_PATTERN_CONTROL 0 0x1ddc 4 0 2 OTG_TEST_PATTERN_EN 0 0 OTG_TEST_PATTERN_MODE 8 10 OTG_TEST_PATTERN_DYNAMIC_RANGE 16 16 OTG_TEST_PATTERN_COLOR_FORMAT 24 31 mmOTG5_OTG_TEST_PATTERN_PARAMETERS 0 0x1ddd 5 0 2 OTG_TEST_PATTERN_INC0 0 3 OTG_TEST_PATTERN_INC1 4 7 OTG_TEST_PATTERN_VRES 8 11 OTG_TEST_PATTERN_HRES 12 15 OTG_TEST_PATTERN_RAMP0_OFFSET 16 31 mmOTG5_OTG_TEST_PATTERN_COLOR 0 0x1dde 2 0 2 OTG_TEST_PATTERN_DATA 0 15 OTG_TEST_PATTERN_MASK 16 21 mmOTG5_OTG_MASTER_EN 0 0x1ddf 1 0 2 OTG_MASTER_EN 0 0 mmOTG5_OTG_BLANK_DATA_COLOR 0 0x1de1 3 0 2 OTG_BLANK_DATA_COLOR_BLUE_CB 0 9 OTG_BLANK_DATA_COLOR_GREEN_Y 10 19 OTG_BLANK_DATA_COLOR_RED_CR 20 29 mmOTG5_OTG_BLANK_DATA_COLOR_EXT 0 0x1de2 3 0 2 OTG_BLANK_DATA_COLOR_BLUE_CB_EXT 0 5 OTG_BLANK_DATA_COLOR_GREEN_Y_EXT 8 13 OTG_BLANK_DATA_COLOR_RED_CR_EXT 16 21 mmOTG5_OTG_BLACK_COLOR 0 0x1de3 3 0 2 OTG_BLACK_COLOR_B_CB 0 9 OTG_BLACK_COLOR_G_Y 10 19 OTG_BLACK_COLOR_R_CR 20 29 mmOTG5_OTG_BLACK_COLOR_EXT 0 0x1de4 3 0 2 OTG_BLACK_COLOR_B_CB_EXT 0 5 OTG_BLACK_COLOR_G_Y_EXT 8 13 OTG_BLACK_COLOR_R_CR_EXT 16 21 mmOTG5_OTG_VERTICAL_INTERRUPT0_POSITION 0 0x1de5 2 0 2 OTG_VERTICAL_INTERRUPT0_LINE_START 0 14 OTG_VERTICAL_INTERRUPT0_LINE_END 16 30 mmOTG5_OTG_VERTICAL_INTERRUPT0_CONTROL 0 0x1de6 6 0 2 OTG_VERTICAL_INTERRUPT0_OUTPUT_POLARITY 4 4 OTG_VERTICAL_INTERRUPT0_INT_ENABLE 8 8 OTG_VERTICAL_INTERRUPT0_STATUS 12 12 OTG_VERTICAL_INTERRUPT0_INT_STATUS 16 16 OTG_VERTICAL_INTERRUPT0_CLEAR 20 20 OTG_VERTICAL_INTERRUPT0_INT_TYPE 24 24 mmOTG5_OTG_VERTICAL_INTERRUPT1_POSITION 0 0x1de7 1 0 2 OTG_VERTICAL_INTERRUPT1_LINE_START 0 14 mmOTG5_OTG_VERTICAL_INTERRUPT1_CONTROL 0 0x1de8 5 0 2 OTG_VERTICAL_INTERRUPT1_INT_ENABLE 8 8 OTG_VERTICAL_INTERRUPT1_STATUS 12 12 OTG_VERTICAL_INTERRUPT1_INT_STATUS 16 16 OTG_VERTICAL_INTERRUPT1_CLEAR 20 20 OTG_VERTICAL_INTERRUPT1_INT_TYPE 24 24 mmOTG5_OTG_VERTICAL_INTERRUPT2_POSITION 0 0x1de9 1 0 2 OTG_VERTICAL_INTERRUPT2_LINE_START 0 14 mmOTG5_OTG_VERTICAL_INTERRUPT2_CONTROL 0 0x1dea 5 0 2 OTG_VERTICAL_INTERRUPT2_INT_ENABLE 8 8 OTG_VERTICAL_INTERRUPT2_STATUS 12 12 OTG_VERTICAL_INTERRUPT2_INT_STATUS 16 16 OTG_VERTICAL_INTERRUPT2_CLEAR 20 20 OTG_VERTICAL_INTERRUPT2_INT_TYPE 24 24 mmOTG5_OTG_CRC_CNTL 0 0x1deb 16 0 2 OTG_CRC_EN 0 0 OTG_CRC_DUAL_LINK_EN 1 1 OTG_CRC_DUAL_LINK_MODE 2 2 OTG_CRC_BLANK_ONLY 3 3 OTG_CRC_CONT_EN 4 4 OTG_CRC_CAPTURE_START_SEL 5 6 OTG_CRC_STEREO_MODE 8 9 OTG_CRC_INTERLACE_MODE 12 13 OTG_CRC_MULTI_STREAM_MODE 16 18 OTG_CRC_USE_NEW_AND_REPEATED_PIXELS 19 19 OTG_CRC0_SELECT 20 22 OTG_CRC1_SELECT 24 26 OTG_ONE_SHOT_CRC0_PENDING 28 28 OTG_ONE_SHOT_CRC1_PENDING 29 29 OTG_ONE_SHOT_CRC2_PENDING 30 30 OTG_ONE_SHOT_CRC3_PENDING 31 31 mmOTG5_OTG_CRC0_WINDOWA_X_CONTROL 0 0x1dec 2 0 2 OTG_CRC0_WINDOWA_X_START 0 14 OTG_CRC0_WINDOWA_X_END 16 30 mmOTG5_OTG_CRC0_WINDOWA_Y_CONTROL 0 0x1ded 2 0 2 OTG_CRC0_WINDOWA_Y_START 0 14 OTG_CRC0_WINDOWA_Y_END 16 30 mmOTG5_OTG_CRC0_WINDOWB_X_CONTROL 0 0x1dee 2 0 2 OTG_CRC0_WINDOWB_X_START 0 14 OTG_CRC0_WINDOWB_X_END 16 30 mmOTG5_OTG_CRC0_WINDOWB_Y_CONTROL 0 0x1def 2 0 2 OTG_CRC0_WINDOWB_Y_START 0 14 OTG_CRC0_WINDOWB_Y_END 16 30 mmOTG5_OTG_CRC0_DATA_RG 0 0x1df0 2 0 2 CRC0_R_CR 0 15 CRC0_G_Y 16 31 mmOTG5_OTG_CRC0_DATA_B 0 0x1df1 2 0 2 CRC0_B_CB 0 15 CRC0_C 16 31 mmOTG5_OTG_CRC1_WINDOWA_X_CONTROL 0 0x1df2 2 0 2 OTG_CRC1_WINDOWA_X_START 0 14 OTG_CRC1_WINDOWA_X_END 16 30 mmOTG5_OTG_CRC1_WINDOWA_Y_CONTROL 0 0x1df3 2 0 2 OTG_CRC1_WINDOWA_Y_START 0 14 OTG_CRC1_WINDOWA_Y_END 16 30 mmOTG5_OTG_CRC1_WINDOWB_X_CONTROL 0 0x1df4 2 0 2 OTG_CRC1_WINDOWB_X_START 0 14 OTG_CRC1_WINDOWB_X_END 16 30 mmOTG5_OTG_CRC1_WINDOWB_Y_CONTROL 0 0x1df5 2 0 2 OTG_CRC1_WINDOWB_Y_START 0 14 OTG_CRC1_WINDOWB_Y_END 16 30 mmOTG5_OTG_CRC1_DATA_RG 0 0x1df6 2 0 2 CRC1_R_CR 0 15 CRC1_G_Y 16 31 mmOTG5_OTG_CRC1_DATA_B 0 0x1df7 2 0 2 CRC1_B_CB 0 15 CRC1_C 16 31 mmOTG5_OTG_CRC2_DATA_RG 0 0x1df8 2 0 2 CRC2_R_CR 0 15 CRC2_G_Y 16 31 mmOTG5_OTG_CRC2_DATA_B 0 0x1df9 2 0 2 CRC2_B_CB 0 15 CRC2_C 16 31 mmOTG5_OTG_CRC3_DATA_RG 0 0x1dfa 2 0 2 CRC3_R_CR 0 15 CRC3_G_Y 16 31 mmOTG5_OTG_CRC3_DATA_B 0 0x1dfb 2 0 2 CRC3_B_CB 0 15 CRC3_C 16 31 mmOTG5_OTG_CRC_SIG_RED_GREEN_MASK 0 0x1dfc 2 0 2 OTG_CRC_SIG_RED_MASK 0 15 OTG_CRC_SIG_GREEN_MASK 16 31 mmOTG5_OTG_CRC_SIG_BLUE_CONTROL_MASK 0 0x1dfd 2 0 2 OTG_CRC_SIG_BLUE_MASK 0 15 OTG_CRC_SIG_CONTROL_MASK 16 31 mmOTG5_OTG_STATIC_SCREEN_CONTROL 0 0x1e04 9 0 2 OTG_STATIC_SCREEN_EVENT_MASK 0 15 OTG_STATIC_SCREEN_FRAME_COUNT 16 23 OTG_CPU_SS_INT_ENABLE 24 24 OTG_SS_STATUS 25 25 OTG_CPU_SS_INT_STATUS 26 26 OTG_CPU_SS_INT_CLEAR 27 27 OTG_CPU_SS_INT_TYPE 28 28 OTG_STATIC_SCREEN_OVERRIDE 30 30 OTG_STATIC_SCREEN_OVERRIDE_VALUE 31 31 mmOTG5_OTG_3D_STRUCTURE_CONTROL 0 0x1e05 6 0 2 OTG_3D_STRUCTURE_EN 0 0 OTG_3D_STRUCTURE_V_UPDATE_MODE 8 9 OTG_3D_STRUCTURE_STEREO_SEL_OVR 12 12 OTG_3D_STRUCTURE_F_COUNT_RESET 16 16 OTG_3D_STRUCTURE_F_COUNT_RESET_PENDING 17 17 OTG_3D_STRUCTURE_F_COUNT 18 19 mmOTG5_OTG_GSL_VSYNC_GAP 0 0x1e06 8 0 2 OTG_GSL_VSYNC_GAP_LIMIT 0 7 OTG_GSL_VSYNC_GAP_DELAY 8 15 OTG_GSL_VSYNC_GAP_SOURCE_SEL 16 16 OTG_GSL_VSYNC_GAP_MODE 17 18 OTG_GSL_VSYNC_GAP_CLEAR 19 19 OTG_GSL_VSYNC_GAP_OCCURRED 20 20 OTG_GSL_VSYNC_GAP_MASTER_FASTER 23 23 OTG_GSL_VSYNC_GAP 24 31 mmOTG5_OTG_MASTER_UPDATE_MODE 0 0x1e07 1 0 2 MASTER_UPDATE_INTERLACED_MODE 0 1 mmOTG5_OTG_CLOCK_CONTROL 0 0x1e08 5 0 2 OTG_CLOCK_EN 0 0 OTG_CLOCK_GATE_DIS 1 1 OTG_SOFT_RESET 4 4 OTG_CLOCK_ON 8 8 OTG_BUSY 16 16 mmOTG5_OTG_VSTARTUP_PARAM 0 0x1e09 1 0 2 VSTARTUP_START 0 9 mmOTG5_OTG_VUPDATE_PARAM 0 0x1e0a 2 0 2 VUPDATE_OFFSET 0 15 VUPDATE_WIDTH 16 25 mmOTG5_OTG_VREADY_PARAM 0 0x1e0b 1 0 2 VREADY_OFFSET 0 15 mmOTG5_OTG_GLOBAL_SYNC_STATUS 0 0x1e0c 25 0 2 VSTARTUP_INT_EN 0 0 VSTARTUP_INT_TYPE 1 1 VSTARTUP_EVENT_OCCURRED 2 2 VSTARTUP_INT_STATUS 3 3 VSTARTUP_EVENT_CLEAR 4 4 VUPDATE_INT_EN 5 5 VUPDATE_INT_TYPE 6 6 VUPDATE_INT_POSITION_SEL 7 7 VUPDATE_EVENT_OCCURRED 8 8 VUPDATE_INT_STATUS 9 9 VUPDATE_EVENT_CLEAR 10 10 VUPDATE_STATUS 11 11 VUPDATE_NO_LOCK_INT_EN 12 12 VUPDATE_NO_LOCK_INT_TYPE 13 13 VUPDATE_NO_LOCK_EVENT_OCCURRED 14 14 VUPDATE_NO_LOCK_INT_STATUS 15 15 VUPDATE_NO_LOCK_EVENT_CLEAR 16 16 VUPDATE_NO_LOCK_STATUS 17 17 VREADY_INT_EN 18 18 VREADY_INT_TYPE 19 19 VREADY_EVENT_OCCURRED 20 20 VREADY_INT_STATUS 21 21 VREADY_EVENT_CLEAR 22 22 STEREO_SELECT_STATUS 24 24 FIELD_NUMBER_STATUS 25 25 mmOTG5_OTG_MASTER_UPDATE_LOCK 0 0x1e0d 2 0 2 OTG_MASTER_UPDATE_LOCK 0 0 UPDATE_LOCK_STATUS 8 8 mmOTG5_OTG_GSL_CONTROL 0 0x1e0e 6 0 2 OTG_GSL0_EN 0 0 OTG_GSL1_EN 1 1 OTG_GSL2_EN 2 2 OTG_GSL_MASTER_EN 3 3 OTG_GSL_FORCE_DELAY 16 20 OTG_GSL_CHECK_ALL_FIELDS 28 28 mmOTG5_OTG_GSL_WINDOW_X 0 0x1e0f 2 0 2 OTG_GSL_WINDOW_START_X 0 14 OTG_GSL_WINDOW_END_X 16 30 mmOTG5_OTG_GSL_WINDOW_Y 0 0x1e10 2 0 2 OTG_GSL_WINDOW_START_Y 0 14 OTG_GSL_WINDOW_END_Y 16 30 mmOTG5_OTG_VUPDATE_KEEPOUT 0 0x1e11 3 0 2 MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_START_OFFSET 0 15 MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_END_OFFSET 16 25 OTG_MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_EN 31 31 mmOTG5_OTG_GLOBAL_CONTROL0 0 0x1e12 3 0 2 OTG_MASTER_UPDATE_LOCK_HTOTAL_KEEPOUT 0 7 OTG_MASTER_UPDATE_LOCK_HTOTAL_KEEPOUT_EN 8 8 OTG_MASTER_UPDATE_LOCK_SEL 25 27 mmOTG5_OTG_GLOBAL_CONTROL1 0 0x1e13 3 0 2 MASTER_UPDATE_LOCK_DB_X 0 14 MASTER_UPDATE_LOCK_DB_Y 16 30 MASTER_UPDATE_LOCK_DB_EN 31 31 mmOTG5_OTG_GLOBAL_CONTROL2 0 0x1e14 4 0 2 DIG_UPDATE_LOCATION 0 9 GLOBAL_UPDATE_LOCK_EN 10 10 MANUAL_FLOW_CONTROL_SEL 16 18 DCCG_VUPDATE_MODE 31 31 mmOTG5_OTG_GLOBAL_CONTROL3 0 0x1e15 3 0 2 MASTER_UPDATE_LOCK_DB_FIELD 0 1 MASTER_UPDATE_LOCK_DB_STEREO_SEL 4 5 MASTER_UPDATE_LOCK_DB_FIELD_STEREO_FLAG_SEL 8 8 mmOTG5_OTG_TRIG_MANUAL_CONTROL 0 0x1e16 1 0 2 TRIG_MANUAL_CONTROL 0 0 mmOTG5_OTG_MANUAL_FLOW_CONTROL 0 0x1e17 1 0 2 MANUAL_FLOW_CONTROL 0 0 mmOTG5_OTG_RANGE_TIMING_INT_STATUS 0 0x1e18 5 0 2 OTG_RANGE_TIMING_UPDATE_OCCURRED 0 0 OTG_RANGE_TIMING_UPDATE_OCCURRED_INT 4 4 OTG_RANGE_TIMING_UPDATE_OCCURRED_CLEAR 8 8 OTG_RANGE_TIMING_UPDATE_OCCURRED_INT_MSK 12 12 OTG_RANGE_TIMING_UPDATE_OCCURRED_INT_TYPE 16 16 mmOTG5_OTG_DRR_CONTROL 0 0x1e19 2 0 2 OTG_DRR_AVERAGE_FRAME 0 2 OTG_V_TOTAL_LAST_USED_BY_DRR 16 30 mmOTG5_OTG_REQUEST_CONTROL 0 0x1e1a 1 0 2 OTG_REQUEST_MODE_FOR_H_DUPLICATE 0 0 mmOTG5_OTG_SPARE_REGISTER 0 0x1e1b 1 0 2 OTG_SPARE_REG 0 31 mmDWB_SOURCE_SELECT 0 0x1e2a 2 0 2 OPTC_DWB0_SOURCE_SELECT 0 2 OPTC_DWB1_SOURCE_SELECT 3 5 mmGSL_SOURCE_SELECT 0 0x1e2b 4 0 2 GSL0_READY_SOURCE_SEL 0 2 GSL1_READY_SOURCE_SEL 4 6 GSL2_READY_SOURCE_SEL 8 10 GSL_TIMING_SYNC_SEL 16 18 mmOPTC_CLOCK_CONTROL 0 0x1e2c 3 0 2 OPTC_DISPCLK_R_GATE_DIS 0 0 OPTC_DISPCLK_R_CLOCK_ON 1 1 OPTC_TEST_CLK_SEL 8 11 mmOPTC_MISC_SPARE_REGISTER 0 0x1e2d 1 0 2 OPTC_MISC_SPARE_REG 0 7 mmDC_PERFMON18_PERFCOUNTER_CNTL 0 0x1e6a 11 0 2 PERFCOUNTER_EVENT_SEL 0 8 PERFCOUNTER_CVALUE_SEL 9 11 PERFCOUNTER_INC_MODE 12 14 PERFCOUNTER_HW_CNTL_SEL 15 15 PERFCOUNTER_RUNEN_MODE 16 16 PERFCOUNTER_CNTOFF_START_DIS 22 22 PERFCOUNTER_RESTART_EN 23 23 PERFCOUNTER_INT_EN 24 24 PERFCOUNTER_OFF_MASK 25 25 PERFCOUNTER_ACTIVE 26 26 PERFCOUNTER_CNTL_SEL 29 31 mmDC_PERFMON18_PERFCOUNTER_CNTL2 0 0x1e6b 5 0 2 PERFCOUNTER_COUNTED_VALUE_TYPE 0 1 PERFCOUNTER_HW_STOP1_SEL 2 2 PERFCOUNTER_HW_STOP2_SEL 3 3 PERFCOUNTER_CNTOFF_SEL 8 13 PERFCOUNTER_CNTL2_SEL 29 31 mmDC_PERFMON18_PERFCOUNTER_STATE 0 0x1e6c 16 0 2 PERFCOUNTER_CNT0_STATE 0 1 PERFCOUNTER_STATE_SEL0 2 2 PERFCOUNTER_CNT1_STATE 4 5 PERFCOUNTER_STATE_SEL1 6 6 PERFCOUNTER_CNT2_STATE 8 9 PERFCOUNTER_STATE_SEL2 10 10 PERFCOUNTER_CNT3_STATE 12 13 PERFCOUNTER_STATE_SEL3 14 14 PERFCOUNTER_CNT4_STATE 16 17 PERFCOUNTER_STATE_SEL4 18 18 PERFCOUNTER_CNT5_STATE 20 21 PERFCOUNTER_STATE_SEL5 22 22 PERFCOUNTER_CNT6_STATE 24 25 PERFCOUNTER_STATE_SEL6 26 26 PERFCOUNTER_CNT7_STATE 28 29 PERFCOUNTER_STATE_SEL7 30 30 mmDC_PERFMON18_PERFMON_CNTL 0 0x1e6d 6 0 2 PERFMON_STATE 0 1 PERFMON_RPT_COUNT 8 27 PERFMON_CNTOFF_AND_OR 28 28 PERFMON_CNTOFF_INT_EN 29 29 PERFMON_CNTOFF_INT_STATUS 30 30 PERFMON_CNTOFF_INT_ACK 31 31 mmDC_PERFMON18_PERFMON_CNTL2 0 0x1e6e 4 0 2 PERFMON_CNTOFF_INT_TYPE 0 0 PERFMON_CLK_ENABLE 1 1 PERFMON_RUN_ENABLE_START_SEL 2 9 PERFMON_RUN_ENABLE_STOP_SEL 10 17 mmDC_PERFMON18_PERFMON_CVALUE_INT_MISC 0 0x1e6f 17 0 2 PERFCOUNTER_INT0_STATUS 0 0 PERFCOUNTER_INT1_STATUS 1 1 PERFCOUNTER_INT2_STATUS 2 2 PERFCOUNTER_INT3_STATUS 3 3 PERFCOUNTER_INT4_STATUS 4 4 PERFCOUNTER_INT5_STATUS 5 5 PERFCOUNTER_INT6_STATUS 6 6 PERFCOUNTER_INT7_STATUS 7 7 PERFCOUNTER_INT0_ACK 8 8 PERFCOUNTER_INT1_ACK 9 9 PERFCOUNTER_INT2_ACK 10 10 PERFCOUNTER_INT3_ACK 11 11 PERFCOUNTER_INT4_ACK 12 12 PERFCOUNTER_INT5_ACK 13 13 PERFCOUNTER_INT6_ACK 14 14 PERFCOUNTER_INT7_ACK 15 15 PERFMON_CVALUE_HI 16 31 mmDC_PERFMON18_PERFMON_CVALUE_LOW 0 0x1e70 1 0 2 PERFMON_CVALUE_LOW 0 31 mmDC_PERFMON18_PERFMON_HI 0 0x1e71 2 0 2 PERFMON_HI 0 15 PERFMON_READ_SEL 29 31 mmDC_PERFMON18_PERFMON_LOW 0 0x1e72 1 0 2 PERFMON_LOW 0 31 mmDAC_ENABLE 0 0x1e76 6 0 2 DAC_ENABLE 0 0 DAC_RESYNC_FIFO_ENABLE 1 1 DAC_RESYNC_FIFO_POINTER_SKEW 2 3 DAC_RESYNC_FIFO_ERROR 4 4 DAC_RESYNC_FIFO_ERROR_ACK 5 5 DAC_RESYNC_FIFO_TVOUT_SIM 8 8 mmDAC_SOURCE_SELECT 0 0x1e77 2 0 2 DAC_SOURCE_SELECT 0 2 DAC_TV_SELECT 3 3 mmDAC_CRC_EN 0 0x1e78 2 0 2 DAC_CRC_EN 0 0 DAC_CRC_CONT_EN 16 16 mmDAC_CRC_CONTROL 0 0x1e79 2 0 2 DAC_CRC_FIELD 0 0 DAC_CRC_ONLY_BLANKB 8 8 mmDAC_CRC_SIG_RGB_MASK 0 0x1e7a 3 0 2 DAC_CRC_SIG_BLUE_MASK 0 9 DAC_CRC_SIG_GREEN_MASK 10 19 DAC_CRC_SIG_RED_MASK 20 29 mmDAC_CRC_SIG_CONTROL_MASK 0 0x1e7b 1 0 2 DAC_CRC_SIG_CONTROL_MASK 0 5 mmDAC_CRC_SIG_RGB 0 0x1e7c 3 0 2 DAC_CRC_SIG_BLUE 0 9 DAC_CRC_SIG_GREEN 10 19 DAC_CRC_SIG_RED 20 29 mmDAC_CRC_SIG_CONTROL 0 0x1e7d 1 0 2 DAC_CRC_SIG_CONTROL 0 5 mmDAC_SYNC_TRISTATE_CONTROL 0 0x1e7e 3 0 2 DAC_HSYNCA_TRISTATE 0 0 DAC_VSYNCA_TRISTATE 8 8 DAC_SYNCA_TRISTATE 16 16 mmDAC_STEREOSYNC_SELECT 0 0x1e7f 1 0 2 DAC_STEREOSYNC_SELECT 0 2 mmDAC_AUTODETECT_CONTROL 0 0x1e80 3 0 2 DAC_AUTODETECT_MODE 0 1 DAC_AUTODETECT_FRAME_TIME_COUNTER 8 15 DAC_AUTODETECT_CHECK_MASK 16 18 mmDAC_AUTODETECT_CONTROL2 0 0x1e81 2 0 2 DAC_AUTODETECT_POWERUP_COUNTER 0 7 DAC_AUTODETECT_TESTMODE 8 8 mmDAC_AUTODETECT_CONTROL3 0 0x1e82 2 0 2 DAC_AUTODET_COMPARATOR_IN_DELAY 0 7 DAC_AUTODET_COMPARATOR_OUT_DELAY 8 15 mmDAC_AUTODETECT_STATUS 0 0x1e83 5 0 2 DAC_AUTODETECT_STATUS 0 0 DAC_AUTODETECT_CONNECT 4 4 DAC_AUTODETECT_RED_SENSE 8 9 DAC_AUTODETECT_GREEN_SENSE 16 17 DAC_AUTODETECT_BLUE_SENSE 24 25 mmDAC_AUTODETECT_INT_CONTROL 0 0x1e84 2 0 2 DAC_AUTODETECT_ACK 0 0 DAC_AUTODETECT_INT_ENABLE 16 16 mmDAC_FORCE_OUTPUT_CNTL 0 0x1e85 3 0 2 DAC_FORCE_DATA_EN 0 0 DAC_FORCE_DATA_SEL 8 10 DAC_FORCE_DATA_ON_BLANKB_ONLY 24 24 mmDAC_FORCE_DATA 0 0x1e86 1 0 2 DAC_FORCE_DATA 0 9 mmDAC_POWERDOWN 0 0x1e87 4 0 2 DAC_POWERDOWN 0 0 DAC_POWERDOWN_BLUE 8 8 DAC_POWERDOWN_GREEN 16 16 DAC_POWERDOWN_RED 24 24 mmDAC_CONTROL 0 0x1e88 3 0 2 DAC_DFORCE_EN 0 0 DAC_TV_ENABLE 8 8 DAC_ZSCALE_SHIFT 16 16 mmDAC_COMPARATOR_ENABLE 0 0x1e89 5 0 2 DAC_COMP_DDET_REF_EN 0 0 DAC_COMP_SDET_REF_EN 8 8 DAC_R_ASYNC_ENABLE 16 16 DAC_G_ASYNC_ENABLE 17 17 DAC_B_ASYNC_ENABLE 18 18 mmDAC_COMPARATOR_OUTPUT 0 0x1e8a 4 0 2 DAC_COMPARATOR_OUTPUT 0 0 DAC_COMPARATOR_OUTPUT_BLUE 1 1 DAC_COMPARATOR_OUTPUT_GREEN 2 2 DAC_COMPARATOR_OUTPUT_RED 3 3 mmDAC_PWR_CNTL 0 0x1e8b 2 0 2 DAC_BG_MODE 0 1 DAC_PWRCNTL 16 17 mmDAC_DFT_CONFIG 0 0x1e8c 1 0 2 DAC_DFT_CONFIG 0 31 mmDAC_FIFO_STATUS 0 0x1e8d 8 0 2 DAC_FIFO_USE_OVERWRITE_LEVEL 1 1 DAC_FIFO_OVERWRITE_LEVEL 2 7 DAC_FIFO_CAL_AVERAGE_LEVEL 10 15 DAC_FIFO_MAXIMUM_LEVEL 16 19 DAC_FIFO_MINIMUM_LEVEL 22 25 DAC_FIFO_CALIBRATED 29 29 DAC_FIFO_FORCE_RECAL_AVERAGE 30 30 DAC_FIFO_FORCE_RECOMP_MINMAX 31 31 mmDC_I2C_CONTROL 0 0x1e98 6 0 2 DC_I2C_GO 0 0 DC_I2C_SOFT_RESET 1 1 DC_I2C_SEND_RESET 2 2 DC_I2C_SW_STATUS_RESET 3 3 DC_I2C_DDC_SELECT 8 10 DC_I2C_TRANSACTION_COUNT 20 21 mmDC_I2C_ARBITRATION 0 0x1e99 9 0 2 DC_I2C_SW_PRIORITY 0 1 DC_I2C_REG_RW_CNTL_STATUS 2 3 DC_I2C_NO_QUEUED_SW_GO 4 4 DC_I2C_ABORT_HW_XFER 8 8 DC_I2C_ABORT_SW_XFER 12 12 DC_I2C_SW_USE_I2C_REG_REQ 20 20 DC_I2C_SW_DONE_USING_I2C_REG 21 21 DC_I2C_DMCU_USE_I2C_REG_REQ 24 24 DC_I2C_DMCU_DONE_USING_I2C_REG 25 25 mmDC_I2C_INTERRUPT_CONTROL 0 0x1e9a 24 0 2 DC_I2C_SW_DONE_INT 0 0 DC_I2C_SW_DONE_ACK 1 1 DC_I2C_SW_DONE_MASK 2 2 DC_I2C_DDC1_HW_DONE_INT 4 4 DC_I2C_DDC1_HW_DONE_ACK 5 5 DC_I2C_DDC1_HW_DONE_MASK 6 6 DC_I2C_DDC2_HW_DONE_INT 8 8 DC_I2C_DDC2_HW_DONE_ACK 9 9 DC_I2C_DDC2_HW_DONE_MASK 10 10 DC_I2C_DDC3_HW_DONE_INT 12 12 DC_I2C_DDC3_HW_DONE_ACK 13 13 DC_I2C_DDC3_HW_DONE_MASK 14 14 DC_I2C_DDC4_HW_DONE_INT 16 16 DC_I2C_DDC4_HW_DONE_ACK 17 17 DC_I2C_DDC4_HW_DONE_MASK 18 18 DC_I2C_DDC5_HW_DONE_INT 20 20 DC_I2C_DDC5_HW_DONE_ACK 21 21 DC_I2C_DDC5_HW_DONE_MASK 22 22 DC_I2C_DDC6_HW_DONE_INT 24 24 DC_I2C_DDC6_HW_DONE_ACK 25 25 DC_I2C_DDC6_HW_DONE_MASK 26 26 DC_I2C_DDCVGA_HW_DONE_INT 27 27 DC_I2C_DDCVGA_HW_DONE_ACK 28 28 DC_I2C_DDCVGA_HW_DONE_MASK 29 29 mmDC_I2C_SW_STATUS 0 0x1e9b 12 0 2 DC_I2C_SW_STATUS 0 1 DC_I2C_SW_DONE 2 2 DC_I2C_SW_ABORTED 4 4 DC_I2C_SW_TIMEOUT 5 5 DC_I2C_SW_INTERRUPTED 6 6 DC_I2C_SW_BUFFER_OVERFLOW 7 7 DC_I2C_SW_STOPPED_ON_NACK 8 8 DC_I2C_SW_NACK0 12 12 DC_I2C_SW_NACK1 13 13 DC_I2C_SW_NACK2 14 14 DC_I2C_SW_NACK3 15 15 DC_I2C_SW_REQ 18 18 mmDC_I2C_DDC1_HW_STATUS 0 0x1e9c 7 0 2 DC_I2C_DDC1_HW_STATUS 0 1 DC_I2C_DDC1_HW_DONE 3 3 DC_I2C_DDC1_HW_REQ 16 16 DC_I2C_DDC1_HW_URG 17 17 DC_I2C_DDC1_EDID_DETECT_STATUS 20 20 DC_I2C_DDC1_EDID_DETECT_NUM_VALID_TRIES 24 27 DC_I2C_DDC1_EDID_DETECT_STATE 28 30 mmDC_I2C_DDC2_HW_STATUS 0 0x1e9d 7 0 2 DC_I2C_DDC2_HW_STATUS 0 1 DC_I2C_DDC2_HW_DONE 3 3 DC_I2C_DDC2_HW_REQ 16 16 DC_I2C_DDC2_HW_URG 17 17 DC_I2C_DDC2_EDID_DETECT_STATUS 20 20 DC_I2C_DDC2_EDID_DETECT_NUM_VALID_TRIES 24 27 DC_I2C_DDC2_EDID_DETECT_STATE 28 30 mmDC_I2C_DDC3_HW_STATUS 0 0x1e9e 7 0 2 DC_I2C_DDC3_HW_STATUS 0 1 DC_I2C_DDC3_HW_DONE 3 3 DC_I2C_DDC3_HW_REQ 16 16 DC_I2C_DDC3_HW_URG 17 17 DC_I2C_DDC3_EDID_DETECT_STATUS 20 20 DC_I2C_DDC3_EDID_DETECT_NUM_VALID_TRIES 24 27 DC_I2C_DDC3_EDID_DETECT_STATE 28 30 mmDC_I2C_DDC4_HW_STATUS 0 0x1e9f 7 0 2 DC_I2C_DDC4_HW_STATUS 0 1 DC_I2C_DDC4_HW_DONE 3 3 DC_I2C_DDC4_HW_REQ 16 16 DC_I2C_DDC4_HW_URG 17 17 DC_I2C_DDC4_EDID_DETECT_STATUS 20 20 DC_I2C_DDC4_EDID_DETECT_NUM_VALID_TRIES 24 27 DC_I2C_DDC4_EDID_DETECT_STATE 28 30 mmDC_I2C_DDC5_HW_STATUS 0 0x1ea0 7 0 2 DC_I2C_DDC5_HW_STATUS 0 1 DC_I2C_DDC5_HW_DONE 3 3 DC_I2C_DDC5_HW_REQ 16 16 DC_I2C_DDC5_HW_URG 17 17 DC_I2C_DDC5_EDID_DETECT_STATUS 20 20 DC_I2C_DDC5_EDID_DETECT_NUM_VALID_TRIES 24 27 DC_I2C_DDC5_EDID_DETECT_STATE 28 30 mmDC_I2C_DDC6_HW_STATUS 0 0x1ea1 7 0 2 DC_I2C_DDC6_HW_STATUS 0 1 DC_I2C_DDC6_HW_DONE 3 3 DC_I2C_DDC6_HW_REQ 16 16 DC_I2C_DDC6_HW_URG 17 17 DC_I2C_DDC6_EDID_DETECT_STATUS 20 20 DC_I2C_DDC6_EDID_DETECT_NUM_VALID_TRIES 24 27 DC_I2C_DDC6_EDID_DETECT_STATE 28 30 mmDC_I2C_DDC1_SPEED 0 0x1ea2 4 0 2 DC_I2C_DDC1_THRESHOLD 0 1 DC_I2C_DDC1_DISABLE_FILTER_DURING_STALL 4 4 DC_I2C_DDC1_START_STOP_TIMING_CNTL 8 9 DC_I2C_DDC1_PRESCALE 16 31 mmDC_I2C_DDC1_SETUP 0 0x1ea3 9 0 2 DC_I2C_DDC1_DATA_DRIVE_EN 0 0 DC_I2C_DDC1_DATA_DRIVE_SEL 1 1 DC_I2C_DDC1_EDID_DETECT_ENABLE 4 4 DC_I2C_DDC1_EDID_DETECT_MODE 5 5 DC_I2C_DDC1_ENABLE 6 6 DC_I2C_DDC1_CLK_DRIVE_EN 7 7 DC_I2C_DDC1_INTRA_BYTE_DELAY 8 15 DC_I2C_DDC1_INTRA_TRANSACTION_DELAY 16 23 DC_I2C_DDC1_TIME_LIMIT 24 31 mmDC_I2C_DDC2_SPEED 0 0x1ea4 4 0 2 DC_I2C_DDC2_THRESHOLD 0 1 DC_I2C_DDC2_DISABLE_FILTER_DURING_STALL 4 4 DC_I2C_DDC2_START_STOP_TIMING_CNTL 8 9 DC_I2C_DDC2_PRESCALE 16 31 mmDC_I2C_DDC2_SETUP 0 0x1ea5 9 0 2 DC_I2C_DDC2_DATA_DRIVE_EN 0 0 DC_I2C_DDC2_DATA_DRIVE_SEL 1 1 DC_I2C_DDC2_EDID_DETECT_ENABLE 4 4 DC_I2C_DDC2_EDID_DETECT_MODE 5 5 DC_I2C_DDC2_ENABLE 6 6 DC_I2C_DDC2_CLK_DRIVE_EN 7 7 DC_I2C_DDC2_INTRA_BYTE_DELAY 8 15 DC_I2C_DDC2_INTRA_TRANSACTION_DELAY 16 23 DC_I2C_DDC2_TIME_LIMIT 24 31 mmDC_I2C_DDC3_SPEED 0 0x1ea6 4 0 2 DC_I2C_DDC3_THRESHOLD 0 1 DC_I2C_DDC3_DISABLE_FILTER_DURING_STALL 4 4 DC_I2C_DDC3_START_STOP_TIMING_CNTL 8 9 DC_I2C_DDC3_PRESCALE 16 31 mmDC_I2C_DDC3_SETUP 0 0x1ea7 9 0 2 DC_I2C_DDC3_DATA_DRIVE_EN 0 0 DC_I2C_DDC3_DATA_DRIVE_SEL 1 1 DC_I2C_DDC3_EDID_DETECT_ENABLE 4 4 DC_I2C_DDC3_EDID_DETECT_MODE 5 5 DC_I2C_DDC3_ENABLE 6 6 DC_I2C_DDC3_CLK_DRIVE_EN 7 7 DC_I2C_DDC3_INTRA_BYTE_DELAY 8 15 DC_I2C_DDC3_INTRA_TRANSACTION_DELAY 16 23 DC_I2C_DDC3_TIME_LIMIT 24 31 mmDC_I2C_DDC4_SPEED 0 0x1ea8 4 0 2 DC_I2C_DDC4_THRESHOLD 0 1 DC_I2C_DDC4_DISABLE_FILTER_DURING_STALL 4 4 DC_I2C_DDC4_START_STOP_TIMING_CNTL 8 9 DC_I2C_DDC4_PRESCALE 16 31 mmDC_I2C_DDC4_SETUP 0 0x1ea9 9 0 2 DC_I2C_DDC4_DATA_DRIVE_EN 0 0 DC_I2C_DDC4_DATA_DRIVE_SEL 1 1 DC_I2C_DDC4_EDID_DETECT_ENABLE 4 4 DC_I2C_DDC4_EDID_DETECT_MODE 5 5 DC_I2C_DDC4_ENABLE 6 6 DC_I2C_DDC4_CLK_DRIVE_EN 7 7 DC_I2C_DDC4_INTRA_BYTE_DELAY 8 15 DC_I2C_DDC4_INTRA_TRANSACTION_DELAY 16 23 DC_I2C_DDC4_TIME_LIMIT 24 31 mmDC_I2C_DDC5_SPEED 0 0x1eaa 4 0 2 DC_I2C_DDC5_THRESHOLD 0 1 DC_I2C_DDC5_DISABLE_FILTER_DURING_STALL 4 4 DC_I2C_DDC5_START_STOP_TIMING_CNTL 8 9 DC_I2C_DDC5_PRESCALE 16 31 mmDC_I2C_DDC5_SETUP 0 0x1eab 9 0 2 DC_I2C_DDC5_DATA_DRIVE_EN 0 0 DC_I2C_DDC5_DATA_DRIVE_SEL 1 1 DC_I2C_DDC5_EDID_DETECT_ENABLE 4 4 DC_I2C_DDC5_EDID_DETECT_MODE 5 5 DC_I2C_DDC5_ENABLE 6 6 DC_I2C_DDC5_CLK_DRIVE_EN 7 7 DC_I2C_DDC5_INTRA_BYTE_DELAY 8 15 DC_I2C_DDC5_INTRA_TRANSACTION_DELAY 16 23 DC_I2C_DDC5_TIME_LIMIT 24 31 mmDC_I2C_DDC6_SPEED 0 0x1eac 4 0 2 DC_I2C_DDC6_THRESHOLD 0 1 DC_I2C_DDC6_DISABLE_FILTER_DURING_STALL 4 4 DC_I2C_DDC6_START_STOP_TIMING_CNTL 8 9 DC_I2C_DDC6_PRESCALE 16 31 mmDC_I2C_DDC6_SETUP 0 0x1ead 9 0 2 DC_I2C_DDC6_DATA_DRIVE_EN 0 0 DC_I2C_DDC6_DATA_DRIVE_SEL 1 1 DC_I2C_DDC6_EDID_DETECT_ENABLE 4 4 DC_I2C_DDC6_EDID_DETECT_MODE 5 5 DC_I2C_DDC6_ENABLE 6 6 DC_I2C_DDC6_CLK_DRIVE_EN 7 7 DC_I2C_DDC6_INTRA_BYTE_DELAY 8 15 DC_I2C_DDC6_INTRA_TRANSACTION_DELAY 16 23 DC_I2C_DDC6_TIME_LIMIT 24 31 mmDC_I2C_TRANSACTION0 0 0x1eae 5 0 2 DC_I2C_RW0 0 0 DC_I2C_STOP_ON_NACK0 8 8 DC_I2C_START0 12 12 DC_I2C_STOP0 13 13 DC_I2C_COUNT0 16 25 mmDC_I2C_TRANSACTION1 0 0x1eaf 5 0 2 DC_I2C_RW1 0 0 DC_I2C_STOP_ON_NACK1 8 8 DC_I2C_START1 12 12 DC_I2C_STOP1 13 13 DC_I2C_COUNT1 16 25 mmDC_I2C_TRANSACTION2 0 0x1eb0 5 0 2 DC_I2C_RW2 0 0 DC_I2C_STOP_ON_NACK2 8 8 DC_I2C_START2 12 12 DC_I2C_STOP2 13 13 DC_I2C_COUNT2 16 25 mmDC_I2C_TRANSACTION3 0 0x1eb1 5 0 2 DC_I2C_RW3 0 0 DC_I2C_STOP_ON_NACK3 8 8 DC_I2C_START3 12 12 DC_I2C_STOP3 13 13 DC_I2C_COUNT3 16 25 mmDC_I2C_DATA 0 0x1eb2 4 0 2 DC_I2C_DATA_RW 0 0 DC_I2C_DATA 8 15 DC_I2C_INDEX 16 25 DC_I2C_INDEX_WRITE 31 31 mmDC_I2C_DDCVGA_HW_STATUS 0 0x1eb3 7 0 2 DC_I2C_DDCVGA_HW_STATUS 0 1 DC_I2C_DDCVGA_HW_DONE 3 3 DC_I2C_DDCVGA_HW_REQ 16 16 DC_I2C_DDCVGA_HW_URG 17 17 DC_I2C_DDCVGA_EDID_DETECT_STATUS 20 20 DC_I2C_DDCVGA_EDID_DETECT_NUM_VALID_TRIES 24 27 DC_I2C_DDCVGA_EDID_DETECT_STATE 28 30 mmDC_I2C_DDCVGA_SPEED 0 0x1eb4 4 0 2 DC_I2C_DDCVGA_THRESHOLD 0 1 DC_I2C_DDCVGA_DISABLE_FILTER_DURING_STALL 4 4 DC_I2C_DDCVGA_START_STOP_TIMING_CNTL 8 9 DC_I2C_DDCVGA_PRESCALE 16 31 mmDC_I2C_DDCVGA_SETUP 0 0x1eb5 9 0 2 DC_I2C_DDCVGA_DATA_DRIVE_EN 0 0 DC_I2C_DDCVGA_DATA_DRIVE_SEL 1 1 DC_I2C_DDCVGA_EDID_DETECT_ENABLE 4 4 DC_I2C_DDCVGA_EDID_DETECT_MODE 5 5 DC_I2C_DDCVGA_ENABLE 6 6 DC_I2C_DDCVGA_CLK_DRIVE_EN 7 7 DC_I2C_DDCVGA_INTRA_BYTE_DELAY 8 15 DC_I2C_DDCVGA_INTRA_TRANSACTION_DELAY 16 23 DC_I2C_DDCVGA_TIME_LIMIT 24 31 mmDC_I2C_EDID_DETECT_CTRL 0 0x1eb6 3 0 2 DC_I2C_EDID_DETECT_WAIT_TIME 0 15 DC_I2C_EDID_DETECT_NUM_TRIES_UNTIL_VALID 20 23 DC_I2C_EDID_DETECT_SEND_RESET 28 28 mmDC_I2C_READ_REQUEST_INTERRUPT 0 0x1eb7 30 0 2 DC_I2C_DDC1_READ_REQUEST_OCCURRED 0 0 DC_I2C_DDC1_READ_REQUEST_INT 1 1 DC_I2C_DDC1_READ_REQUEST_ACK 2 2 DC_I2C_DDC1_READ_REQUEST_MASK 3 3 DC_I2C_DDC2_READ_REQUEST_OCCURRED 4 4 DC_I2C_DDC2_READ_REQUEST_INT 5 5 DC_I2C_DDC2_READ_REQUEST_ACK 6 6 DC_I2C_DDC2_READ_REQUEST_MASK 7 7 DC_I2C_DDC3_READ_REQUEST_OCCURRED 8 8 DC_I2C_DDC3_READ_REQUEST_INT 9 9 DC_I2C_DDC3_READ_REQUEST_ACK 10 10 DC_I2C_DDC3_READ_REQUEST_MASK 11 11 DC_I2C_DDC4_READ_REQUEST_OCCURRED 12 12 DC_I2C_DDC4_READ_REQUEST_INT 13 13 DC_I2C_DDC4_READ_REQUEST_ACK 14 14 DC_I2C_DDC4_READ_REQUEST_MASK 15 15 DC_I2C_DDC5_READ_REQUEST_OCCURRED 16 16 DC_I2C_DDC5_READ_REQUEST_INT 17 17 DC_I2C_DDC5_READ_REQUEST_ACK 18 18 DC_I2C_DDC5_READ_REQUEST_MASK 19 19 DC_I2C_DDC6_READ_REQUEST_OCCURRED 20 20 DC_I2C_DDC6_READ_REQUEST_INT 21 21 DC_I2C_DDC6_READ_REQUEST_ACK 22 22 DC_I2C_DDC6_READ_REQUEST_MASK 23 23 DC_I2C_DDCVGA_READ_REQUEST_OCCURRED 24 24 DC_I2C_DDCVGA_READ_REQUEST_INT 25 25 DC_I2C_DDCVGA_READ_REQUEST_ACK 26 26 DC_I2C_DDCVGA_READ_REQUEST_MASK 27 27 DC_I2C_DDC_READ_REQUEST_ACK_ENABLE 30 30 DC_I2C_DDC_READ_REQUEST_INT_TYPE 31 31 mmGENERIC_I2C_CONTROL 0 0x1eb8 4 0 2 GENERIC_I2C_GO 0 0 GENERIC_I2C_SOFT_RESET 1 1 GENERIC_I2C_SEND_RESET 2 2 GENERIC_I2C_ENABLE 3 3 mmGENERIC_I2C_INTERRUPT_CONTROL 0 0x1eb9 3 0 2 GENERIC_I2C_DONE_INT 0 0 GENERIC_I2C_DONE_ACK 1 1 GENERIC_I2C_DONE_MASK 2 2 mmGENERIC_I2C_STATUS 0 0x1eba 6 0 2 GENERIC_I2C_STATUS 0 3 GENERIC_I2C_DONE 4 4 GENERIC_I2C_ABORTED 5 5 GENERIC_I2C_TIMEOUT 6 6 GENERIC_I2C_STOPPED_ON_NACK 9 9 GENERIC_I2C_NACK 10 10 mmGENERIC_I2C_SPEED 0 0x1ebb 4 0 2 GENERIC_I2C_THRESHOLD 0 1 GENERIC_I2C_DISABLE_FILTER_DURING_STALL 4 4 GENERIC_I2C_START_STOP_TIMING_CNTL 8 9 GENERIC_I2C_PRESCALE 16 31 mmGENERIC_I2C_SETUP 0 0x1ebc 5 0 2 GENERIC_I2C_DATA_DRIVE_EN 0 0 GENERIC_I2C_DATA_DRIVE_SEL 1 1 GENERIC_I2C_CLK_DRIVE_EN 7 7 GENERIC_I2C_INTRA_BYTE_DELAY 8 15 GENERIC_I2C_TIME_LIMIT 24 31 mmGENERIC_I2C_TRANSACTION 0 0x1ebd 6 0 2 GENERIC_I2C_RW 0 0 GENERIC_I2C_STOP_ON_NACK 8 8 GENERIC_I2C_ACK_ON_READ 9 9 GENERIC_I2C_START 12 12 GENERIC_I2C_STOP 13 13 GENERIC_I2C_COUNT 16 19 mmGENERIC_I2C_DATA 0 0x1ebe 4 0 2 GENERIC_I2C_DATA_RW 0 0 GENERIC_I2C_DATA 8 15 GENERIC_I2C_INDEX 16 19 GENERIC_I2C_INDEX_WRITE 31 31 mmGENERIC_I2C_PIN_SELECTION 0 0x1ebf 2 0 2 GENERIC_I2C_SCL_PIN_SEL 0 6 GENERIC_I2C_SDA_PIN_SEL 8 14 mmDIO_SCRATCH0 0 0x1eca 1 0 2 DIO_SCRATCH0 0 31 mmDIO_SCRATCH1 0 0x1ecb 1 0 2 DIO_SCRATCH1 0 31 mmDIO_SCRATCH2 0 0x1ecc 1 0 2 DIO_SCRATCH2 0 31 mmDIO_SCRATCH3 0 0x1ecd 1 0 2 DIO_SCRATCH3 0 31 mmDIO_SCRATCH4 0 0x1ece 1 0 2 DIO_SCRATCH4 0 31 mmDIO_SCRATCH5 0 0x1ecf 1 0 2 DIO_SCRATCH5 0 31 mmDIO_SCRATCH6 0 0x1ed0 1 0 2 DIO_SCRATCH6 0 31 mmDIO_SCRATCH7 0 0x1ed1 1 0 2 DIO_SCRATCH7 0 31 mmDCE_VCE_CONTROL 0 0x1ed2 1 0 2 DC_VCE_AUDIO_STREAM_SELECT 4 6 mmDIO_MEM_PWR_STATUS 0 0x1edd 15 0 2 I2C_MEM_PWR_STATE 0 0 DPA_MEM_PWR_STATE 3 3 DPB_MEM_PWR_STATE 4 4 DPC_MEM_PWR_STATE 5 5 DPD_MEM_PWR_STATE 6 6 DPE_MEM_PWR_STATE 7 7 DPF_MEM_PWR_STATE 8 8 DPG_MEM_PWR_STATE 9 9 HDMI0_MEM_PWR_STATE 10 11 HDMI1_MEM_PWR_STATE 12 13 HDMI2_MEM_PWR_STATE 14 15 HDMI3_MEM_PWR_STATE 16 17 HDMI4_MEM_PWR_STATE 18 19 HDMI5_MEM_PWR_STATE 20 21 HDMI6_MEM_PWR_STATE 22 23 mmDIO_MEM_PWR_CTRL 0 0x1ede 23 0 2 I2C_LIGHT_SLEEP_FORCE 0 0 I2C_LIGHT_SLEEP_DIS 1 1 DPA_LIGHT_SLEEP_DIS 4 4 DPB_LIGHT_SLEEP_DIS 5 5 DPC_LIGHT_SLEEP_DIS 6 6 DPD_LIGHT_SLEEP_DIS 7 7 DPE_LIGHT_SLEEP_DIS 8 8 DPF_LIGHT_SLEEP_DIS 9 9 DPG_LIGHT_SLEEP_DIS 10 10 HDMI0_MEM_PWR_FORCE 11 12 HDMI0_MEM_PWR_DIS 13 13 HDMI1_MEM_PWR_FORCE 14 15 HDMI1_MEM_PWR_DIS 16 16 HDMI2_MEM_PWR_FORCE 17 18 HDMI2_MEM_PWR_DIS 19 19 HDMI3_MEM_PWR_FORCE 20 21 HDMI3_MEM_PWR_DIS 22 22 HDMI4_MEM_PWR_FORCE 23 24 HDMI4_MEM_PWR_DIS 25 25 HDMI5_MEM_PWR_FORCE 26 27 HDMI5_MEM_PWR_DIS 28 28 HDMI6_MEM_PWR_FORCE 29 30 HDMI6_MEM_PWR_DIS 31 31 mmDIO_MEM_PWR_CTRL2 0 0x1edf 20 0 2 HDMI_MEM_PWR_MODE_SEL 0 1 AFMT0_LIGHT_SLEEP_DIS 4 4 AFMT0_LIGHT_SLEEP_FORCE 5 5 AFMT1_LIGHT_SLEEP_DIS 6 6 AFMT1_LIGHT_SLEEP_FORCE 7 7 AFMT2_LIGHT_SLEEP_DIS 8 8 AFMT2_LIGHT_SLEEP_FORCE 9 9 AFMT3_LIGHT_SLEEP_DIS 10 10 AFMT3_LIGHT_SLEEP_FORCE 11 11 AFMT4_LIGHT_SLEEP_DIS 12 12 AFMT4_LIGHT_SLEEP_FORCE 13 13 AFMT5_LIGHT_SLEEP_DIS 14 14 AFMT5_LIGHT_SLEEP_FORCE 15 15 DPA_LIGHT_SLEEP_FORCE 24 24 DPB_LIGHT_SLEEP_FORCE 25 25 DPC_LIGHT_SLEEP_FORCE 26 26 DPD_LIGHT_SLEEP_FORCE 27 27 DPE_LIGHT_SLEEP_FORCE 28 28 DPF_LIGHT_SLEEP_FORCE 29 29 DPG_LIGHT_SLEEP_FORCE 30 30 mmDIO_CLK_CNTL 0 0x1ee0 11 0 2 DISPCLK_R_DIO_GATE_DIS 5 5 DISPCLK_G_DVO_GATE_DIS 7 7 DISPCLK_G_DACA_GATE_DIS 8 8 REFCLK_R_DIO_GATE_DIS 10 10 DISPCLK_G_DIGA_GATE_DIS 24 24 DISPCLK_G_DIGB_GATE_DIS 25 25 DISPCLK_G_DIGC_GATE_DIS 26 26 DISPCLK_G_DIGD_GATE_DIS 27 27 DISPCLK_G_DIGE_GATE_DIS 28 28 DISPCLK_G_DIGF_GATE_DIS 29 29 DISPCLK_G_DIGG_GATE_DIS 30 30 mmDIO_POWER_MANAGEMENT_CNTL 0 0x1ee4 2 0 2 PM_ASSERT_RESET 0 0 PM_ALL_BUSY_OFF 8 8 mmDIO_STEREOSYNC_SEL 0 0x1eea 2 0 2 GENERICA_STEREOSYNC_SEL 0 2 GENERICB_STEREOSYNC_SEL 16 18 mmDIO_SOFT_RESET 0 0x1eed 6 0 2 DACA_SOFT_RESET 0 0 I2S0_SPDIF0_SOFT_RESET 4 4 I2S1_SOFT_RESET 5 5 SPDIF1_SOFT_RESET 6 6 DB_CLK_SOFT_RESET 12 12 DVO_SOFT_RESET 27 27 mmDIG_SOFT_RESET 0 0x1eee 14 0 2 DIGA_FE_SOFT_RESET 0 0 DIGA_BE_SOFT_RESET 1 1 DIGB_FE_SOFT_RESET 4 4 DIGB_BE_SOFT_RESET 5 5 DIGC_FE_SOFT_RESET 8 8 DIGC_BE_SOFT_RESET 9 9 DIGD_FE_SOFT_RESET 12 12 DIGD_BE_SOFT_RESET 13 13 DIGE_FE_SOFT_RESET 16 16 DIGE_BE_SOFT_RESET 17 17 DIGF_FE_SOFT_RESET 20 20 DIGF_BE_SOFT_RESET 21 21 DIGG_FE_SOFT_RESET 24 24 DIGG_BE_SOFT_RESET 25 25 mmDIO_MEM_PWR_STATUS1 0 0x1ef0 6 0 2 AFMT0_MEM_PWR_STATE 0 0 AFMT1_MEM_PWR_STATE 2 2 AFMT2_MEM_PWR_STATE 4 4 AFMT3_MEM_PWR_STATE 6 6 AFMT4_MEM_PWR_STATE 8 8 AFMT5_MEM_PWR_STATE 10 10 mmDIO_CLK_CNTL2 0 0x1ef2 15 0 2 DIO_TEST_CLK_SEL 0 6 SOCCLK_G_AFMTA_GATE_DIS 7 7 SOCCLK_G_AFMTB_GATE_DIS 8 8 SOCCLK_G_AFMTC_GATE_DIS 9 9 SOCCLK_G_AFMTD_GATE_DIS 10 10 SOCCLK_G_AFMTE_GATE_DIS 11 11 SOCCLK_G_AFMTF_GATE_DIS 12 12 SOCCLK_G_AFMTG_GATE_DIS 13 13 SYMCLKA_FE_G_AFMT_GATE_DIS 17 17 SYMCLKB_FE_G_AFMT_GATE_DIS 18 18 SYMCLKC_FE_G_AFMT_GATE_DIS 19 19 SYMCLKD_FE_G_AFMT_GATE_DIS 20 20 SYMCLKE_FE_G_AFMT_GATE_DIS 21 21 SYMCLKF_FE_G_AFMT_GATE_DIS 22 22 SYMCLKG_FE_G_AFMT_GATE_DIS 23 23 mmDIO_CLK_CNTL3 0 0x1ef3 14 0 2 SYMCLKA_FE_G_TMDS_GATE_DIS 0 0 SYMCLKB_FE_G_TMDS_GATE_DIS 1 1 SYMCLKC_FE_G_TMDS_GATE_DIS 2 2 SYMCLKD_FE_G_TMDS_GATE_DIS 3 3 SYMCLKE_FE_G_TMDS_GATE_DIS 4 4 SYMCLKF_FE_G_TMDS_GATE_DIS 5 5 SYMCLKG_FE_G_TMDS_GATE_DIS 6 6 SYMCLKA_G_TMDS_GATE_DIS 10 10 SYMCLKB_G_TMDS_GATE_DIS 11 11 SYMCLKC_G_TMDS_GATE_DIS 12 12 SYMCLKD_G_TMDS_GATE_DIS 13 13 SYMCLKE_G_TMDS_GATE_DIS 14 14 SYMCLKF_G_TMDS_GATE_DIS 15 15 SYMCLKG_G_TMDS_GATE_DIS 16 16 mmDIO_HDMI_RXSTATUS_TIMER_CONTROL 0 0x1eff 5 0 2 DIO_HDMI_RXSTATUS_TIMER_ENABLE 0 0 DIO_HDMI_RXSTATUS_TIMER_TYPE 4 4 DIO_HDMI_RXSTATUS_TIMER_STATUS 8 8 DIO_HDMI_RXSTATUS_TIMER_MASK 12 12 DIO_HDMI_RXSTATUS_TIMER_INTERVAL 16 27 mmDIO_PSP_INTERRUPT_STATUS 0 0x1f00 2 0 2 DIO_PSP_INTERRUPT_STATUS 0 0 DIO_PSP_INTERRUPT_MESSAGE 1 31 mmDIO_PSP_INTERRUPT_CLEAR 0 0x1f01 1 0 2 DIO_PSP_INTERRUPT_CLEAR 0 0 mmDIO_GENERIC_INTERRUPT_MESSAGE 0 0x1f02 2 0 2 DIO_GENERIC_INTERRUPT_STATUS 0 0 DIO_GENERIC_INTERRUPT_MESSAGE 1 31 mmDIO_GENERIC_INTERRUPT_CLEAR 0 0x1f03 1 0 2 DIO_GENERIC_INTERRUPT_CLEAR 0 0 mmHPD0_DC_HPD_INT_STATUS 0 0x1f14 6 0 2 DC_HPD_INT_STATUS 0 0 DC_HPD_SENSE 1 1 DC_HPD_SENSE_DELAYED 4 4 DC_HPD_RX_INT_STATUS 8 8 DC_HPD_TOGGLE_FILT_CON_TIMER_VAL 12 19 DC_HPD_TOGGLE_FILT_DISCON_TIMER_VAL 24 31 mmHPD0_DC_HPD_INT_CONTROL 0 0x1f15 5 0 2 DC_HPD_INT_ACK 0 0 DC_HPD_INT_POLARITY 8 8 DC_HPD_INT_EN 16 16 DC_HPD_RX_INT_ACK 20 20 DC_HPD_RX_INT_EN 24 24 mmHPD0_DC_HPD_CONTROL 0 0x1f16 3 0 2 DC_HPD_CONNECTION_TIMER 0 12 DC_HPD_RX_INT_TIMER 16 25 DC_HPD_EN 28 28 mmHPD0_DC_HPD_FAST_TRAIN_CNTL 0 0x1f17 4 0 2 DC_HPD_CONNECT_AUX_TX_DELAY 0 7 DC_HPD_CONNECT_FAST_TRAIN_DELAY 12 19 DC_HPD_CONNECT_AUX_TX_EN 24 24 DC_HPD_CONNECT_FAST_TRAIN_EN 28 28 mmHPD0_DC_HPD_TOGGLE_FILT_CNTL 0 0x1f18 2 0 2 DC_HPD_CONNECT_INT_DELAY 0 7 DC_HPD_DISCONNECT_INT_DELAY 20 27 mmHPD1_DC_HPD_INT_STATUS 0 0x1f1c 6 0 2 DC_HPD_INT_STATUS 0 0 DC_HPD_SENSE 1 1 DC_HPD_SENSE_DELAYED 4 4 DC_HPD_RX_INT_STATUS 8 8 DC_HPD_TOGGLE_FILT_CON_TIMER_VAL 12 19 DC_HPD_TOGGLE_FILT_DISCON_TIMER_VAL 24 31 mmHPD1_DC_HPD_INT_CONTROL 0 0x1f1d 5 0 2 DC_HPD_INT_ACK 0 0 DC_HPD_INT_POLARITY 8 8 DC_HPD_INT_EN 16 16 DC_HPD_RX_INT_ACK 20 20 DC_HPD_RX_INT_EN 24 24 mmHPD1_DC_HPD_CONTROL 0 0x1f1e 3 0 2 DC_HPD_CONNECTION_TIMER 0 12 DC_HPD_RX_INT_TIMER 16 25 DC_HPD_EN 28 28 mmHPD1_DC_HPD_FAST_TRAIN_CNTL 0 0x1f1f 4 0 2 DC_HPD_CONNECT_AUX_TX_DELAY 0 7 DC_HPD_CONNECT_FAST_TRAIN_DELAY 12 19 DC_HPD_CONNECT_AUX_TX_EN 24 24 DC_HPD_CONNECT_FAST_TRAIN_EN 28 28 mmHPD1_DC_HPD_TOGGLE_FILT_CNTL 0 0x1f20 2 0 2 DC_HPD_CONNECT_INT_DELAY 0 7 DC_HPD_DISCONNECT_INT_DELAY 20 27 mmHPD2_DC_HPD_INT_STATUS 0 0x1f24 6 0 2 DC_HPD_INT_STATUS 0 0 DC_HPD_SENSE 1 1 DC_HPD_SENSE_DELAYED 4 4 DC_HPD_RX_INT_STATUS 8 8 DC_HPD_TOGGLE_FILT_CON_TIMER_VAL 12 19 DC_HPD_TOGGLE_FILT_DISCON_TIMER_VAL 24 31 mmHPD2_DC_HPD_INT_CONTROL 0 0x1f25 5 0 2 DC_HPD_INT_ACK 0 0 DC_HPD_INT_POLARITY 8 8 DC_HPD_INT_EN 16 16 DC_HPD_RX_INT_ACK 20 20 DC_HPD_RX_INT_EN 24 24 mmHPD2_DC_HPD_CONTROL 0 0x1f26 3 0 2 DC_HPD_CONNECTION_TIMER 0 12 DC_HPD_RX_INT_TIMER 16 25 DC_HPD_EN 28 28 mmHPD2_DC_HPD_FAST_TRAIN_CNTL 0 0x1f27 4 0 2 DC_HPD_CONNECT_AUX_TX_DELAY 0 7 DC_HPD_CONNECT_FAST_TRAIN_DELAY 12 19 DC_HPD_CONNECT_AUX_TX_EN 24 24 DC_HPD_CONNECT_FAST_TRAIN_EN 28 28 mmHPD2_DC_HPD_TOGGLE_FILT_CNTL 0 0x1f28 2 0 2 DC_HPD_CONNECT_INT_DELAY 0 7 DC_HPD_DISCONNECT_INT_DELAY 20 27 mmHPD3_DC_HPD_INT_STATUS 0 0x1f2c 6 0 2 DC_HPD_INT_STATUS 0 0 DC_HPD_SENSE 1 1 DC_HPD_SENSE_DELAYED 4 4 DC_HPD_RX_INT_STATUS 8 8 DC_HPD_TOGGLE_FILT_CON_TIMER_VAL 12 19 DC_HPD_TOGGLE_FILT_DISCON_TIMER_VAL 24 31 mmHPD3_DC_HPD_INT_CONTROL 0 0x1f2d 5 0 2 DC_HPD_INT_ACK 0 0 DC_HPD_INT_POLARITY 8 8 DC_HPD_INT_EN 16 16 DC_HPD_RX_INT_ACK 20 20 DC_HPD_RX_INT_EN 24 24 mmHPD3_DC_HPD_CONTROL 0 0x1f2e 3 0 2 DC_HPD_CONNECTION_TIMER 0 12 DC_HPD_RX_INT_TIMER 16 25 DC_HPD_EN 28 28 mmHPD3_DC_HPD_FAST_TRAIN_CNTL 0 0x1f2f 4 0 2 DC_HPD_CONNECT_AUX_TX_DELAY 0 7 DC_HPD_CONNECT_FAST_TRAIN_DELAY 12 19 DC_HPD_CONNECT_AUX_TX_EN 24 24 DC_HPD_CONNECT_FAST_TRAIN_EN 28 28 mmHPD3_DC_HPD_TOGGLE_FILT_CNTL 0 0x1f30 2 0 2 DC_HPD_CONNECT_INT_DELAY 0 7 DC_HPD_DISCONNECT_INT_DELAY 20 27 mmHPD4_DC_HPD_INT_STATUS 0 0x1f34 6 0 2 DC_HPD_INT_STATUS 0 0 DC_HPD_SENSE 1 1 DC_HPD_SENSE_DELAYED 4 4 DC_HPD_RX_INT_STATUS 8 8 DC_HPD_TOGGLE_FILT_CON_TIMER_VAL 12 19 DC_HPD_TOGGLE_FILT_DISCON_TIMER_VAL 24 31 mmHPD4_DC_HPD_INT_CONTROL 0 0x1f35 5 0 2 DC_HPD_INT_ACK 0 0 DC_HPD_INT_POLARITY 8 8 DC_HPD_INT_EN 16 16 DC_HPD_RX_INT_ACK 20 20 DC_HPD_RX_INT_EN 24 24 mmHPD4_DC_HPD_CONTROL 0 0x1f36 3 0 2 DC_HPD_CONNECTION_TIMER 0 12 DC_HPD_RX_INT_TIMER 16 25 DC_HPD_EN 28 28 mmHPD4_DC_HPD_FAST_TRAIN_CNTL 0 0x1f37 4 0 2 DC_HPD_CONNECT_AUX_TX_DELAY 0 7 DC_HPD_CONNECT_FAST_TRAIN_DELAY 12 19 DC_HPD_CONNECT_AUX_TX_EN 24 24 DC_HPD_CONNECT_FAST_TRAIN_EN 28 28 mmHPD4_DC_HPD_TOGGLE_FILT_CNTL 0 0x1f38 2 0 2 DC_HPD_CONNECT_INT_DELAY 0 7 DC_HPD_DISCONNECT_INT_DELAY 20 27 mmHPD5_DC_HPD_INT_STATUS 0 0x1f3c 6 0 2 DC_HPD_INT_STATUS 0 0 DC_HPD_SENSE 1 1 DC_HPD_SENSE_DELAYED 4 4 DC_HPD_RX_INT_STATUS 8 8 DC_HPD_TOGGLE_FILT_CON_TIMER_VAL 12 19 DC_HPD_TOGGLE_FILT_DISCON_TIMER_VAL 24 31 mmHPD5_DC_HPD_INT_CONTROL 0 0x1f3d 5 0 2 DC_HPD_INT_ACK 0 0 DC_HPD_INT_POLARITY 8 8 DC_HPD_INT_EN 16 16 DC_HPD_RX_INT_ACK 20 20 DC_HPD_RX_INT_EN 24 24 mmHPD5_DC_HPD_CONTROL 0 0x1f3e 3 0 2 DC_HPD_CONNECTION_TIMER 0 12 DC_HPD_RX_INT_TIMER 16 25 DC_HPD_EN 28 28 mmHPD5_DC_HPD_FAST_TRAIN_CNTL 0 0x1f3f 4 0 2 DC_HPD_CONNECT_AUX_TX_DELAY 0 7 DC_HPD_CONNECT_FAST_TRAIN_DELAY 12 19 DC_HPD_CONNECT_AUX_TX_EN 24 24 DC_HPD_CONNECT_FAST_TRAIN_EN 28 28 mmHPD5_DC_HPD_TOGGLE_FILT_CNTL 0 0x1f40 2 0 2 DC_HPD_CONNECT_INT_DELAY 0 7 DC_HPD_DISCONNECT_INT_DELAY 20 27 mmDC_PERFMON19_PERFCOUNTER_CNTL 0 0x1f44 11 0 2 PERFCOUNTER_EVENT_SEL 0 8 PERFCOUNTER_CVALUE_SEL 9 11 PERFCOUNTER_INC_MODE 12 14 PERFCOUNTER_HW_CNTL_SEL 15 15 PERFCOUNTER_RUNEN_MODE 16 16 PERFCOUNTER_CNTOFF_START_DIS 22 22 PERFCOUNTER_RESTART_EN 23 23 PERFCOUNTER_INT_EN 24 24 PERFCOUNTER_OFF_MASK 25 25 PERFCOUNTER_ACTIVE 26 26 PERFCOUNTER_CNTL_SEL 29 31 mmDC_PERFMON19_PERFCOUNTER_CNTL2 0 0x1f45 5 0 2 PERFCOUNTER_COUNTED_VALUE_TYPE 0 1 PERFCOUNTER_HW_STOP1_SEL 2 2 PERFCOUNTER_HW_STOP2_SEL 3 3 PERFCOUNTER_CNTOFF_SEL 8 13 PERFCOUNTER_CNTL2_SEL 29 31 mmDC_PERFMON19_PERFCOUNTER_STATE 0 0x1f46 16 0 2 PERFCOUNTER_CNT0_STATE 0 1 PERFCOUNTER_STATE_SEL0 2 2 PERFCOUNTER_CNT1_STATE 4 5 PERFCOUNTER_STATE_SEL1 6 6 PERFCOUNTER_CNT2_STATE 8 9 PERFCOUNTER_STATE_SEL2 10 10 PERFCOUNTER_CNT3_STATE 12 13 PERFCOUNTER_STATE_SEL3 14 14 PERFCOUNTER_CNT4_STATE 16 17 PERFCOUNTER_STATE_SEL4 18 18 PERFCOUNTER_CNT5_STATE 20 21 PERFCOUNTER_STATE_SEL5 22 22 PERFCOUNTER_CNT6_STATE 24 25 PERFCOUNTER_STATE_SEL6 26 26 PERFCOUNTER_CNT7_STATE 28 29 PERFCOUNTER_STATE_SEL7 30 30 mmDC_PERFMON19_PERFMON_CNTL 0 0x1f47 6 0 2 PERFMON_STATE 0 1 PERFMON_RPT_COUNT 8 27 PERFMON_CNTOFF_AND_OR 28 28 PERFMON_CNTOFF_INT_EN 29 29 PERFMON_CNTOFF_INT_STATUS 30 30 PERFMON_CNTOFF_INT_ACK 31 31 mmDC_PERFMON19_PERFMON_CNTL2 0 0x1f48 4 0 2 PERFMON_CNTOFF_INT_TYPE 0 0 PERFMON_CLK_ENABLE 1 1 PERFMON_RUN_ENABLE_START_SEL 2 9 PERFMON_RUN_ENABLE_STOP_SEL 10 17 mmDC_PERFMON19_PERFMON_CVALUE_INT_MISC 0 0x1f49 17 0 2 PERFCOUNTER_INT0_STATUS 0 0 PERFCOUNTER_INT1_STATUS 1 1 PERFCOUNTER_INT2_STATUS 2 2 PERFCOUNTER_INT3_STATUS 3 3 PERFCOUNTER_INT4_STATUS 4 4 PERFCOUNTER_INT5_STATUS 5 5 PERFCOUNTER_INT6_STATUS 6 6 PERFCOUNTER_INT7_STATUS 7 7 PERFCOUNTER_INT0_ACK 8 8 PERFCOUNTER_INT1_ACK 9 9 PERFCOUNTER_INT2_ACK 10 10 PERFCOUNTER_INT3_ACK 11 11 PERFCOUNTER_INT4_ACK 12 12 PERFCOUNTER_INT5_ACK 13 13 PERFCOUNTER_INT6_ACK 14 14 PERFCOUNTER_INT7_ACK 15 15 PERFMON_CVALUE_HI 16 31 mmDC_PERFMON19_PERFMON_CVALUE_LOW 0 0x1f4a 1 0 2 PERFMON_CVALUE_LOW 0 31 mmDC_PERFMON19_PERFMON_HI 0 0x1f4b 2 0 2 PERFMON_HI 0 15 PERFMON_READ_SEL 29 31 mmDC_PERFMON19_PERFMON_LOW 0 0x1f4c 1 0 2 PERFMON_LOW 0 31 mmDP_AUX0_AUX_CONTROL 0 0x1f50 13 0 2 AUX_EN 0 0 AUX_RESET 4 4 AUX_RESET_DONE 5 5 AUX_LS_READ_EN 8 8 AUX_LS_UPDATE_DISABLE 12 12 AUX_IGNORE_HPD_DISCON 16 16 AUX_MODE_DET_EN 18 18 AUX_HPD_SEL 20 22 AUX_IMPCAL_REQ_EN 24 24 AUX_TEST_MODE 28 28 AUX_DEGLITCH_EN 29 29 SPARE_0 30 30 SPARE_1 31 31 mmDP_AUX0_AUX_SW_CONTROL 0 0x1f51 4 0 2 AUX_SW_GO 0 0 AUX_LS_READ_TRIG 2 2 AUX_SW_START_DELAY 4 7 AUX_SW_WR_BYTES 16 20 mmDP_AUX0_AUX_ARB_CONTROL 0 0x1f52 10 0 2 AUX_ARB_PRIORITY 0 1 AUX_REG_RW_CNTL_STATUS 2 3 AUX_NO_QUEUED_SW_GO 8 8 AUX_NO_QUEUED_LS_GO 10 10 AUX_SW_USE_AUX_REG_REQ 16 16 AUX_SW_PENDING_USE_AUX_REG_REQ 16 16 AUX_SW_DONE_USING_AUX_REG 17 17 AUX_DMCU_USE_AUX_REG_REQ 24 24 AUX_DMCU_PENDING_USE_AUX_REG_REQ 24 24 AUX_DMCU_DONE_USING_AUX_REG 25 25 mmDP_AUX0_AUX_INTERRUPT_CONTROL 0 0x1f53 12 0 2 AUX_SW_DONE_INT 0 0 AUX_SW_DONE_ACK 1 1 AUX_SW_DONE_MASK 2 2 AUX_LS_DONE_INT 4 4 AUX_LS_DONE_ACK 5 5 AUX_LS_DONE_MASK 6 6 AUX_GTC_SYNC_LOCK_DONE_INT 8 8 AUX_GTC_SYNC_LOCK_DONE_ACK 9 9 AUX_GTC_SYNC_LOCK_DONE_INT_MASK 10 10 AUX_GTC_SYNC_ERROR_INT 12 12 AUX_GTC_SYNC_ERROR_ACK 13 13 AUX_GTC_SYNC_ERROR_INT_MASK 14 14 mmDP_AUX0_AUX_SW_STATUS 0 0x1f54 18 0 2 AUX_SW_DONE 0 0 AUX_SW_REQ 1 1 AUX_SW_RX_TIMEOUT_STATE 4 6 AUX_SW_RX_TIMEOUT 7 7 AUX_SW_RX_OVERFLOW 8 8 AUX_SW_HPD_DISCON 9 9 AUX_SW_RX_PARTIAL_BYTE 10 10 AUX_SW_NON_AUX_MODE 11 11 AUX_SW_RX_MIN_COUNT_VIOL 12 12 AUX_SW_RX_INVALID_STOP 14 14 AUX_SW_RX_SYNC_INVALID_L 17 17 AUX_SW_RX_SYNC_INVALID_H 18 18 AUX_SW_RX_INVALID_START 19 19 AUX_SW_RX_RECV_NO_DET 20 20 AUX_SW_RX_RECV_INVALID_H 22 22 AUX_SW_RX_RECV_INVALID_L 23 23 AUX_SW_REPLY_BYTE_COUNT 24 28 AUX_ARB_STATUS 30 31 mmDP_AUX0_AUX_LS_STATUS 0 0x1f55 20 0 2 AUX_LS_DONE 0 0 AUX_LS_REQ 1 1 AUX_LS_RX_TIMEOUT_STATE 4 6 AUX_LS_RX_TIMEOUT 7 7 AUX_LS_RX_OVERFLOW 8 8 AUX_LS_HPD_DISCON 9 9 AUX_LS_RX_PARTIAL_BYTE 10 10 AUX_LS_NON_AUX_MODE 11 11 AUX_LS_RX_MIN_COUNT_VIOL 12 12 AUX_LS_RX_INVALID_STOP 14 14 AUX_LS_RX_SYNC_INVALID_L 17 17 AUX_LS_RX_SYNC_INVALID_H 18 18 AUX_LS_RX_INVALID_START 19 19 AUX_LS_RX_RECV_NO_DET 20 20 AUX_LS_RX_RECV_INVALID_H 22 22 AUX_LS_RX_RECV_INVALID_L 23 23 AUX_LS_REPLY_BYTE_COUNT 24 28 AUX_LS_CP_IRQ 29 29 AUX_LS_UPDATED 30 30 AUX_LS_UPDATED_ACK 31 31 mmDP_AUX0_AUX_SW_DATA 0 0x1f56 4 0 2 AUX_SW_DATA_RW 0 0 AUX_SW_DATA 8 15 AUX_SW_INDEX 16 20 AUX_SW_AUTOINCREMENT_DISABLE 31 31 mmDP_AUX0_AUX_LS_DATA 0 0x1f57 2 0 2 AUX_LS_DATA 8 15 AUX_LS_INDEX 16 20 mmDP_AUX0_AUX_DPHY_TX_REF_CONTROL 0 0x1f58 3 0 2 AUX_TX_REF_SEL 0 0 AUX_TX_RATE 4 5 AUX_TX_REF_DIV 16 24 mmDP_AUX0_AUX_DPHY_TX_CONTROL 0 0x1f59 3 0 2 AUX_TX_PRECHARGE_LEN 0 2 AUX_TX_PRECHARGE_SYMBOLS 8 13 AUX_MODE_DET_CHECK_DELAY 16 18 mmDP_AUX0_AUX_DPHY_RX_CONTROL0 0 0x1f5a 10 0 2 AUX_RX_START_WINDOW 4 6 AUX_RX_RECEIVE_WINDOW 8 10 AUX_RX_HALF_SYM_DETECT_LEN 12 13 AUX_RX_TRANSITION_FILTER_EN 16 16 AUX_RX_ALLOW_BELOW_THRESHOLD_PHASE_DETECT 17 17 AUX_RX_ALLOW_BELOW_THRESHOLD_START 18 18 AUX_RX_ALLOW_BELOW_THRESHOLD_STOP 19 19 AUX_RX_PHASE_DETECT_LEN 20 21 AUX_RX_TIMEOUT_LEN 24 26 AUX_RX_DETECTION_THRESHOLD 28 30 mmDP_AUX0_AUX_DPHY_RX_CONTROL1 0 0x1f5b 1 0 2 AUX_RX_PRECHARGE_SKIP 0 7 mmDP_AUX0_AUX_DPHY_TX_STATUS 0 0x1f5c 3 0 2 AUX_TX_ACTIVE 0 0 AUX_TX_STATE 4 6 AUX_TX_HALF_SYM_PERIOD 16 24 mmDP_AUX0_AUX_DPHY_RX_STATUS 0 0x1f5d 4 0 2 AUX_RX_STATE 0 2 AUX_RX_SYNC_VALID_COUNT 8 12 AUX_RX_HALF_SYM_PERIOD_FRACT 16 20 AUX_RX_HALF_SYM_PERIOD 21 29 mmDP_AUX0_AUX_GTC_SYNC_ERROR_CONTROL 0 0x1f5f 4 0 2 AUX_GTC_POTENTIAL_ERROR_THRESHOLD 0 4 AUX_GTC_DEFINITE_ERROR_THRESHOLD 8 12 AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_LEN 16 17 AUX_GTC_SYNC_NUM_RETRY_FOR_LOCK_MAINT 20 21 mmDP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS 0 0x1f60 12 0 2 AUX_GTC_SYNC_LOCK_ACQ_COMPLETE 0 0 AUX_GTC_SYNC_LOCK_LOST 4 4 AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_OCCURRED 8 8 AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_STATE 9 12 AUX_GTC_SYNC_PHASE_ADJUST_TIME_VIOL 16 16 AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED 20 20 AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED_ACK 21 21 AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED 22 22 AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED_ACK 23 23 AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED 24 24 AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED_ACK 25 25 AUX_GTC_SYNC_CTRL_STATE 28 31 mmDP_AUX0_AUX_GTC_SYNC_STATUS 0 0x1f61 19 0 2 AUX_GTC_SYNC_DONE 0 0 AUX_GTC_SYNC_REQ 1 1 AUX_GTC_SYNC_RX_TIMEOUT_STATE 4 6 AUX_GTC_SYNC_TIMEOUT 7 7 AUX_GTC_SYNC_RX_OVERFLOW 8 8 AUX_GTC_SYNC_HPD_DISCON 9 9 AUX_GTC_SYNC_RX_PARTIAL_BYTE 10 10 AUX_GTC_SYNC_NON_AUX_MODE 11 11 AUX_GTC_SYNC_RX_MIN_COUNT_VIOL 12 12 AUX_GTC_SYNC_RX_INVALID_STOP 14 14 AUX_GTC_SYNC_RX_SYNC_INVALID_L 17 17 AUX_GTC_SYNC_RX_SYNC_INVALID_H 18 18 AUX_GTC_SYNC_RX_INVALID_START 19 19 AUX_GTC_SYNC_RX_RECV_NO_DET 20 20 AUX_GTC_SYNC_RX_RECV_INVALID_H 22 22 AUX_GTC_SYNC_RX_RECV_INVALID_L 23 23 AUX_GTC_SYNC_REPLY_BYTE_COUNT 24 28 AUX_GTC_SYNC_NACKED 29 29 AUX_GTC_MASTER_REQ_BY_RX 30 30 mmDP_AUX1_AUX_CONTROL 0 0x1f6c 13 0 2 AUX_EN 0 0 AUX_RESET 4 4 AUX_RESET_DONE 5 5 AUX_LS_READ_EN 8 8 AUX_LS_UPDATE_DISABLE 12 12 AUX_IGNORE_HPD_DISCON 16 16 AUX_MODE_DET_EN 18 18 AUX_HPD_SEL 20 22 AUX_IMPCAL_REQ_EN 24 24 AUX_TEST_MODE 28 28 AUX_DEGLITCH_EN 29 29 SPARE_0 30 30 SPARE_1 31 31 mmDP_AUX1_AUX_SW_CONTROL 0 0x1f6d 4 0 2 AUX_SW_GO 0 0 AUX_LS_READ_TRIG 2 2 AUX_SW_START_DELAY 4 7 AUX_SW_WR_BYTES 16 20 mmDP_AUX1_AUX_ARB_CONTROL 0 0x1f6e 10 0 2 AUX_ARB_PRIORITY 0 1 AUX_REG_RW_CNTL_STATUS 2 3 AUX_NO_QUEUED_SW_GO 8 8 AUX_NO_QUEUED_LS_GO 10 10 AUX_SW_USE_AUX_REG_REQ 16 16 AUX_SW_PENDING_USE_AUX_REG_REQ 16 16 AUX_SW_DONE_USING_AUX_REG 17 17 AUX_DMCU_USE_AUX_REG_REQ 24 24 AUX_DMCU_PENDING_USE_AUX_REG_REQ 24 24 AUX_DMCU_DONE_USING_AUX_REG 25 25 mmDP_AUX1_AUX_INTERRUPT_CONTROL 0 0x1f6f 12 0 2 AUX_SW_DONE_INT 0 0 AUX_SW_DONE_ACK 1 1 AUX_SW_DONE_MASK 2 2 AUX_LS_DONE_INT 4 4 AUX_LS_DONE_ACK 5 5 AUX_LS_DONE_MASK 6 6 AUX_GTC_SYNC_LOCK_DONE_INT 8 8 AUX_GTC_SYNC_LOCK_DONE_ACK 9 9 AUX_GTC_SYNC_LOCK_DONE_INT_MASK 10 10 AUX_GTC_SYNC_ERROR_INT 12 12 AUX_GTC_SYNC_ERROR_ACK 13 13 AUX_GTC_SYNC_ERROR_INT_MASK 14 14 mmDP_AUX1_AUX_SW_STATUS 0 0x1f70 18 0 2 AUX_SW_DONE 0 0 AUX_SW_REQ 1 1 AUX_SW_RX_TIMEOUT_STATE 4 6 AUX_SW_RX_TIMEOUT 7 7 AUX_SW_RX_OVERFLOW 8 8 AUX_SW_HPD_DISCON 9 9 AUX_SW_RX_PARTIAL_BYTE 10 10 AUX_SW_NON_AUX_MODE 11 11 AUX_SW_RX_MIN_COUNT_VIOL 12 12 AUX_SW_RX_INVALID_STOP 14 14 AUX_SW_RX_SYNC_INVALID_L 17 17 AUX_SW_RX_SYNC_INVALID_H 18 18 AUX_SW_RX_INVALID_START 19 19 AUX_SW_RX_RECV_NO_DET 20 20 AUX_SW_RX_RECV_INVALID_H 22 22 AUX_SW_RX_RECV_INVALID_L 23 23 AUX_SW_REPLY_BYTE_COUNT 24 28 AUX_ARB_STATUS 30 31 mmDP_AUX1_AUX_LS_STATUS 0 0x1f71 20 0 2 AUX_LS_DONE 0 0 AUX_LS_REQ 1 1 AUX_LS_RX_TIMEOUT_STATE 4 6 AUX_LS_RX_TIMEOUT 7 7 AUX_LS_RX_OVERFLOW 8 8 AUX_LS_HPD_DISCON 9 9 AUX_LS_RX_PARTIAL_BYTE 10 10 AUX_LS_NON_AUX_MODE 11 11 AUX_LS_RX_MIN_COUNT_VIOL 12 12 AUX_LS_RX_INVALID_STOP 14 14 AUX_LS_RX_SYNC_INVALID_L 17 17 AUX_LS_RX_SYNC_INVALID_H 18 18 AUX_LS_RX_INVALID_START 19 19 AUX_LS_RX_RECV_NO_DET 20 20 AUX_LS_RX_RECV_INVALID_H 22 22 AUX_LS_RX_RECV_INVALID_L 23 23 AUX_LS_REPLY_BYTE_COUNT 24 28 AUX_LS_CP_IRQ 29 29 AUX_LS_UPDATED 30 30 AUX_LS_UPDATED_ACK 31 31 mmDP_AUX1_AUX_SW_DATA 0 0x1f72 4 0 2 AUX_SW_DATA_RW 0 0 AUX_SW_DATA 8 15 AUX_SW_INDEX 16 20 AUX_SW_AUTOINCREMENT_DISABLE 31 31 mmDP_AUX1_AUX_LS_DATA 0 0x1f73 2 0 2 AUX_LS_DATA 8 15 AUX_LS_INDEX 16 20 mmDP_AUX1_AUX_DPHY_TX_REF_CONTROL 0 0x1f74 3 0 2 AUX_TX_REF_SEL 0 0 AUX_TX_RATE 4 5 AUX_TX_REF_DIV 16 24 mmDP_AUX1_AUX_DPHY_TX_CONTROL 0 0x1f75 3 0 2 AUX_TX_PRECHARGE_LEN 0 2 AUX_TX_PRECHARGE_SYMBOLS 8 13 AUX_MODE_DET_CHECK_DELAY 16 18 mmDP_AUX1_AUX_DPHY_RX_CONTROL0 0 0x1f76 10 0 2 AUX_RX_START_WINDOW 4 6 AUX_RX_RECEIVE_WINDOW 8 10 AUX_RX_HALF_SYM_DETECT_LEN 12 13 AUX_RX_TRANSITION_FILTER_EN 16 16 AUX_RX_ALLOW_BELOW_THRESHOLD_PHASE_DETECT 17 17 AUX_RX_ALLOW_BELOW_THRESHOLD_START 18 18 AUX_RX_ALLOW_BELOW_THRESHOLD_STOP 19 19 AUX_RX_PHASE_DETECT_LEN 20 21 AUX_RX_TIMEOUT_LEN 24 26 AUX_RX_DETECTION_THRESHOLD 28 30 mmDP_AUX1_AUX_DPHY_RX_CONTROL1 0 0x1f77 1 0 2 AUX_RX_PRECHARGE_SKIP 0 7 mmDP_AUX1_AUX_DPHY_TX_STATUS 0 0x1f78 3 0 2 AUX_TX_ACTIVE 0 0 AUX_TX_STATE 4 6 AUX_TX_HALF_SYM_PERIOD 16 24 mmDP_AUX1_AUX_DPHY_RX_STATUS 0 0x1f79 4 0 2 AUX_RX_STATE 0 2 AUX_RX_SYNC_VALID_COUNT 8 12 AUX_RX_HALF_SYM_PERIOD_FRACT 16 20 AUX_RX_HALF_SYM_PERIOD 21 29 mmDP_AUX1_AUX_GTC_SYNC_ERROR_CONTROL 0 0x1f7b 4 0 2 AUX_GTC_POTENTIAL_ERROR_THRESHOLD 0 4 AUX_GTC_DEFINITE_ERROR_THRESHOLD 8 12 AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_LEN 16 17 AUX_GTC_SYNC_NUM_RETRY_FOR_LOCK_MAINT 20 21 mmDP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS 0 0x1f7c 12 0 2 AUX_GTC_SYNC_LOCK_ACQ_COMPLETE 0 0 AUX_GTC_SYNC_LOCK_LOST 4 4 AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_OCCURRED 8 8 AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_STATE 9 12 AUX_GTC_SYNC_PHASE_ADJUST_TIME_VIOL 16 16 AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED 20 20 AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED_ACK 21 21 AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED 22 22 AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED_ACK 23 23 AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED 24 24 AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED_ACK 25 25 AUX_GTC_SYNC_CTRL_STATE 28 31 mmDP_AUX1_AUX_GTC_SYNC_STATUS 0 0x1f7d 19 0 2 AUX_GTC_SYNC_DONE 0 0 AUX_GTC_SYNC_REQ 1 1 AUX_GTC_SYNC_RX_TIMEOUT_STATE 4 6 AUX_GTC_SYNC_TIMEOUT 7 7 AUX_GTC_SYNC_RX_OVERFLOW 8 8 AUX_GTC_SYNC_HPD_DISCON 9 9 AUX_GTC_SYNC_RX_PARTIAL_BYTE 10 10 AUX_GTC_SYNC_NON_AUX_MODE 11 11 AUX_GTC_SYNC_RX_MIN_COUNT_VIOL 12 12 AUX_GTC_SYNC_RX_INVALID_STOP 14 14 AUX_GTC_SYNC_RX_SYNC_INVALID_L 17 17 AUX_GTC_SYNC_RX_SYNC_INVALID_H 18 18 AUX_GTC_SYNC_RX_INVALID_START 19 19 AUX_GTC_SYNC_RX_RECV_NO_DET 20 20 AUX_GTC_SYNC_RX_RECV_INVALID_H 22 22 AUX_GTC_SYNC_RX_RECV_INVALID_L 23 23 AUX_GTC_SYNC_REPLY_BYTE_COUNT 24 28 AUX_GTC_SYNC_NACKED 29 29 AUX_GTC_MASTER_REQ_BY_RX 30 30 mmDP_AUX2_AUX_CONTROL 0 0x1f88 13 0 2 AUX_EN 0 0 AUX_RESET 4 4 AUX_RESET_DONE 5 5 AUX_LS_READ_EN 8 8 AUX_LS_UPDATE_DISABLE 12 12 AUX_IGNORE_HPD_DISCON 16 16 AUX_MODE_DET_EN 18 18 AUX_HPD_SEL 20 22 AUX_IMPCAL_REQ_EN 24 24 AUX_TEST_MODE 28 28 AUX_DEGLITCH_EN 29 29 SPARE_0 30 30 SPARE_1 31 31 mmDP_AUX2_AUX_SW_CONTROL 0 0x1f89 4 0 2 AUX_SW_GO 0 0 AUX_LS_READ_TRIG 2 2 AUX_SW_START_DELAY 4 7 AUX_SW_WR_BYTES 16 20 mmDP_AUX2_AUX_ARB_CONTROL 0 0x1f8a 10 0 2 AUX_ARB_PRIORITY 0 1 AUX_REG_RW_CNTL_STATUS 2 3 AUX_NO_QUEUED_SW_GO 8 8 AUX_NO_QUEUED_LS_GO 10 10 AUX_SW_USE_AUX_REG_REQ 16 16 AUX_SW_PENDING_USE_AUX_REG_REQ 16 16 AUX_SW_DONE_USING_AUX_REG 17 17 AUX_DMCU_USE_AUX_REG_REQ 24 24 AUX_DMCU_PENDING_USE_AUX_REG_REQ 24 24 AUX_DMCU_DONE_USING_AUX_REG 25 25 mmDP_AUX2_AUX_INTERRUPT_CONTROL 0 0x1f8b 12 0 2 AUX_SW_DONE_INT 0 0 AUX_SW_DONE_ACK 1 1 AUX_SW_DONE_MASK 2 2 AUX_LS_DONE_INT 4 4 AUX_LS_DONE_ACK 5 5 AUX_LS_DONE_MASK 6 6 AUX_GTC_SYNC_LOCK_DONE_INT 8 8 AUX_GTC_SYNC_LOCK_DONE_ACK 9 9 AUX_GTC_SYNC_LOCK_DONE_INT_MASK 10 10 AUX_GTC_SYNC_ERROR_INT 12 12 AUX_GTC_SYNC_ERROR_ACK 13 13 AUX_GTC_SYNC_ERROR_INT_MASK 14 14 mmDP_AUX2_AUX_SW_STATUS 0 0x1f8c 18 0 2 AUX_SW_DONE 0 0 AUX_SW_REQ 1 1 AUX_SW_RX_TIMEOUT_STATE 4 6 AUX_SW_RX_TIMEOUT 7 7 AUX_SW_RX_OVERFLOW 8 8 AUX_SW_HPD_DISCON 9 9 AUX_SW_RX_PARTIAL_BYTE 10 10 AUX_SW_NON_AUX_MODE 11 11 AUX_SW_RX_MIN_COUNT_VIOL 12 12 AUX_SW_RX_INVALID_STOP 14 14 AUX_SW_RX_SYNC_INVALID_L 17 17 AUX_SW_RX_SYNC_INVALID_H 18 18 AUX_SW_RX_INVALID_START 19 19 AUX_SW_RX_RECV_NO_DET 20 20 AUX_SW_RX_RECV_INVALID_H 22 22 AUX_SW_RX_RECV_INVALID_L 23 23 AUX_SW_REPLY_BYTE_COUNT 24 28 AUX_ARB_STATUS 30 31 mmDP_AUX2_AUX_LS_STATUS 0 0x1f8d 20 0 2 AUX_LS_DONE 0 0 AUX_LS_REQ 1 1 AUX_LS_RX_TIMEOUT_STATE 4 6 AUX_LS_RX_TIMEOUT 7 7 AUX_LS_RX_OVERFLOW 8 8 AUX_LS_HPD_DISCON 9 9 AUX_LS_RX_PARTIAL_BYTE 10 10 AUX_LS_NON_AUX_MODE 11 11 AUX_LS_RX_MIN_COUNT_VIOL 12 12 AUX_LS_RX_INVALID_STOP 14 14 AUX_LS_RX_SYNC_INVALID_L 17 17 AUX_LS_RX_SYNC_INVALID_H 18 18 AUX_LS_RX_INVALID_START 19 19 AUX_LS_RX_RECV_NO_DET 20 20 AUX_LS_RX_RECV_INVALID_H 22 22 AUX_LS_RX_RECV_INVALID_L 23 23 AUX_LS_REPLY_BYTE_COUNT 24 28 AUX_LS_CP_IRQ 29 29 AUX_LS_UPDATED 30 30 AUX_LS_UPDATED_ACK 31 31 mmDP_AUX2_AUX_SW_DATA 0 0x1f8e 4 0 2 AUX_SW_DATA_RW 0 0 AUX_SW_DATA 8 15 AUX_SW_INDEX 16 20 AUX_SW_AUTOINCREMENT_DISABLE 31 31 mmDP_AUX2_AUX_LS_DATA 0 0x1f8f 2 0 2 AUX_LS_DATA 8 15 AUX_LS_INDEX 16 20 mmDP_AUX2_AUX_DPHY_TX_REF_CONTROL 0 0x1f90 3 0 2 AUX_TX_REF_SEL 0 0 AUX_TX_RATE 4 5 AUX_TX_REF_DIV 16 24 mmDP_AUX2_AUX_DPHY_TX_CONTROL 0 0x1f91 3 0 2 AUX_TX_PRECHARGE_LEN 0 2 AUX_TX_PRECHARGE_SYMBOLS 8 13 AUX_MODE_DET_CHECK_DELAY 16 18 mmDP_AUX2_AUX_DPHY_RX_CONTROL0 0 0x1f92 10 0 2 AUX_RX_START_WINDOW 4 6 AUX_RX_RECEIVE_WINDOW 8 10 AUX_RX_HALF_SYM_DETECT_LEN 12 13 AUX_RX_TRANSITION_FILTER_EN 16 16 AUX_RX_ALLOW_BELOW_THRESHOLD_PHASE_DETECT 17 17 AUX_RX_ALLOW_BELOW_THRESHOLD_START 18 18 AUX_RX_ALLOW_BELOW_THRESHOLD_STOP 19 19 AUX_RX_PHASE_DETECT_LEN 20 21 AUX_RX_TIMEOUT_LEN 24 26 AUX_RX_DETECTION_THRESHOLD 28 30 mmDP_AUX2_AUX_DPHY_RX_CONTROL1 0 0x1f93 1 0 2 AUX_RX_PRECHARGE_SKIP 0 7 mmDP_AUX2_AUX_DPHY_TX_STATUS 0 0x1f94 3 0 2 AUX_TX_ACTIVE 0 0 AUX_TX_STATE 4 6 AUX_TX_HALF_SYM_PERIOD 16 24 mmDP_AUX2_AUX_DPHY_RX_STATUS 0 0x1f95 4 0 2 AUX_RX_STATE 0 2 AUX_RX_SYNC_VALID_COUNT 8 12 AUX_RX_HALF_SYM_PERIOD_FRACT 16 20 AUX_RX_HALF_SYM_PERIOD 21 29 mmDP_AUX2_AUX_GTC_SYNC_ERROR_CONTROL 0 0x1f97 4 0 2 AUX_GTC_POTENTIAL_ERROR_THRESHOLD 0 4 AUX_GTC_DEFINITE_ERROR_THRESHOLD 8 12 AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_LEN 16 17 AUX_GTC_SYNC_NUM_RETRY_FOR_LOCK_MAINT 20 21 mmDP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS 0 0x1f98 12 0 2 AUX_GTC_SYNC_LOCK_ACQ_COMPLETE 0 0 AUX_GTC_SYNC_LOCK_LOST 4 4 AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_OCCURRED 8 8 AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_STATE 9 12 AUX_GTC_SYNC_PHASE_ADJUST_TIME_VIOL 16 16 AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED 20 20 AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED_ACK 21 21 AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED 22 22 AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED_ACK 23 23 AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED 24 24 AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED_ACK 25 25 AUX_GTC_SYNC_CTRL_STATE 28 31 mmDP_AUX2_AUX_GTC_SYNC_STATUS 0 0x1f99 19 0 2 AUX_GTC_SYNC_DONE 0 0 AUX_GTC_SYNC_REQ 1 1 AUX_GTC_SYNC_RX_TIMEOUT_STATE 4 6 AUX_GTC_SYNC_TIMEOUT 7 7 AUX_GTC_SYNC_RX_OVERFLOW 8 8 AUX_GTC_SYNC_HPD_DISCON 9 9 AUX_GTC_SYNC_RX_PARTIAL_BYTE 10 10 AUX_GTC_SYNC_NON_AUX_MODE 11 11 AUX_GTC_SYNC_RX_MIN_COUNT_VIOL 12 12 AUX_GTC_SYNC_RX_INVALID_STOP 14 14 AUX_GTC_SYNC_RX_SYNC_INVALID_L 17 17 AUX_GTC_SYNC_RX_SYNC_INVALID_H 18 18 AUX_GTC_SYNC_RX_INVALID_START 19 19 AUX_GTC_SYNC_RX_RECV_NO_DET 20 20 AUX_GTC_SYNC_RX_RECV_INVALID_H 22 22 AUX_GTC_SYNC_RX_RECV_INVALID_L 23 23 AUX_GTC_SYNC_REPLY_BYTE_COUNT 24 28 AUX_GTC_SYNC_NACKED 29 29 AUX_GTC_MASTER_REQ_BY_RX 30 30 mmDP_AUX3_AUX_CONTROL 0 0x1fa4 13 0 2 AUX_EN 0 0 AUX_RESET 4 4 AUX_RESET_DONE 5 5 AUX_LS_READ_EN 8 8 AUX_LS_UPDATE_DISABLE 12 12 AUX_IGNORE_HPD_DISCON 16 16 AUX_MODE_DET_EN 18 18 AUX_HPD_SEL 20 22 AUX_IMPCAL_REQ_EN 24 24 AUX_TEST_MODE 28 28 AUX_DEGLITCH_EN 29 29 SPARE_0 30 30 SPARE_1 31 31 mmDP_AUX3_AUX_SW_CONTROL 0 0x1fa5 4 0 2 AUX_SW_GO 0 0 AUX_LS_READ_TRIG 2 2 AUX_SW_START_DELAY 4 7 AUX_SW_WR_BYTES 16 20 mmDP_AUX3_AUX_ARB_CONTROL 0 0x1fa6 10 0 2 AUX_ARB_PRIORITY 0 1 AUX_REG_RW_CNTL_STATUS 2 3 AUX_NO_QUEUED_SW_GO 8 8 AUX_NO_QUEUED_LS_GO 10 10 AUX_SW_USE_AUX_REG_REQ 16 16 AUX_SW_PENDING_USE_AUX_REG_REQ 16 16 AUX_SW_DONE_USING_AUX_REG 17 17 AUX_DMCU_USE_AUX_REG_REQ 24 24 AUX_DMCU_PENDING_USE_AUX_REG_REQ 24 24 AUX_DMCU_DONE_USING_AUX_REG 25 25 mmDP_AUX3_AUX_INTERRUPT_CONTROL 0 0x1fa7 12 0 2 AUX_SW_DONE_INT 0 0 AUX_SW_DONE_ACK 1 1 AUX_SW_DONE_MASK 2 2 AUX_LS_DONE_INT 4 4 AUX_LS_DONE_ACK 5 5 AUX_LS_DONE_MASK 6 6 AUX_GTC_SYNC_LOCK_DONE_INT 8 8 AUX_GTC_SYNC_LOCK_DONE_ACK 9 9 AUX_GTC_SYNC_LOCK_DONE_INT_MASK 10 10 AUX_GTC_SYNC_ERROR_INT 12 12 AUX_GTC_SYNC_ERROR_ACK 13 13 AUX_GTC_SYNC_ERROR_INT_MASK 14 14 mmDP_AUX3_AUX_SW_STATUS 0 0x1fa8 18 0 2 AUX_SW_DONE 0 0 AUX_SW_REQ 1 1 AUX_SW_RX_TIMEOUT_STATE 4 6 AUX_SW_RX_TIMEOUT 7 7 AUX_SW_RX_OVERFLOW 8 8 AUX_SW_HPD_DISCON 9 9 AUX_SW_RX_PARTIAL_BYTE 10 10 AUX_SW_NON_AUX_MODE 11 11 AUX_SW_RX_MIN_COUNT_VIOL 12 12 AUX_SW_RX_INVALID_STOP 14 14 AUX_SW_RX_SYNC_INVALID_L 17 17 AUX_SW_RX_SYNC_INVALID_H 18 18 AUX_SW_RX_INVALID_START 19 19 AUX_SW_RX_RECV_NO_DET 20 20 AUX_SW_RX_RECV_INVALID_H 22 22 AUX_SW_RX_RECV_INVALID_L 23 23 AUX_SW_REPLY_BYTE_COUNT 24 28 AUX_ARB_STATUS 30 31 mmDP_AUX3_AUX_LS_STATUS 0 0x1fa9 20 0 2 AUX_LS_DONE 0 0 AUX_LS_REQ 1 1 AUX_LS_RX_TIMEOUT_STATE 4 6 AUX_LS_RX_TIMEOUT 7 7 AUX_LS_RX_OVERFLOW 8 8 AUX_LS_HPD_DISCON 9 9 AUX_LS_RX_PARTIAL_BYTE 10 10 AUX_LS_NON_AUX_MODE 11 11 AUX_LS_RX_MIN_COUNT_VIOL 12 12 AUX_LS_RX_INVALID_STOP 14 14 AUX_LS_RX_SYNC_INVALID_L 17 17 AUX_LS_RX_SYNC_INVALID_H 18 18 AUX_LS_RX_INVALID_START 19 19 AUX_LS_RX_RECV_NO_DET 20 20 AUX_LS_RX_RECV_INVALID_H 22 22 AUX_LS_RX_RECV_INVALID_L 23 23 AUX_LS_REPLY_BYTE_COUNT 24 28 AUX_LS_CP_IRQ 29 29 AUX_LS_UPDATED 30 30 AUX_LS_UPDATED_ACK 31 31 mmDP_AUX3_AUX_SW_DATA 0 0x1faa 4 0 2 AUX_SW_DATA_RW 0 0 AUX_SW_DATA 8 15 AUX_SW_INDEX 16 20 AUX_SW_AUTOINCREMENT_DISABLE 31 31 mmDP_AUX3_AUX_LS_DATA 0 0x1fab 2 0 2 AUX_LS_DATA 8 15 AUX_LS_INDEX 16 20 mmDP_AUX3_AUX_DPHY_TX_REF_CONTROL 0 0x1fac 3 0 2 AUX_TX_REF_SEL 0 0 AUX_TX_RATE 4 5 AUX_TX_REF_DIV 16 24 mmDP_AUX3_AUX_DPHY_TX_CONTROL 0 0x1fad 3 0 2 AUX_TX_PRECHARGE_LEN 0 2 AUX_TX_PRECHARGE_SYMBOLS 8 13 AUX_MODE_DET_CHECK_DELAY 16 18 mmDP_AUX3_AUX_DPHY_RX_CONTROL0 0 0x1fae 10 0 2 AUX_RX_START_WINDOW 4 6 AUX_RX_RECEIVE_WINDOW 8 10 AUX_RX_HALF_SYM_DETECT_LEN 12 13 AUX_RX_TRANSITION_FILTER_EN 16 16 AUX_RX_ALLOW_BELOW_THRESHOLD_PHASE_DETECT 17 17 AUX_RX_ALLOW_BELOW_THRESHOLD_START 18 18 AUX_RX_ALLOW_BELOW_THRESHOLD_STOP 19 19 AUX_RX_PHASE_DETECT_LEN 20 21 AUX_RX_TIMEOUT_LEN 24 26 AUX_RX_DETECTION_THRESHOLD 28 30 mmDP_AUX3_AUX_DPHY_RX_CONTROL1 0 0x1faf 1 0 2 AUX_RX_PRECHARGE_SKIP 0 7 mmDP_AUX3_AUX_DPHY_TX_STATUS 0 0x1fb0 3 0 2 AUX_TX_ACTIVE 0 0 AUX_TX_STATE 4 6 AUX_TX_HALF_SYM_PERIOD 16 24 mmDP_AUX3_AUX_DPHY_RX_STATUS 0 0x1fb1 4 0 2 AUX_RX_STATE 0 2 AUX_RX_SYNC_VALID_COUNT 8 12 AUX_RX_HALF_SYM_PERIOD_FRACT 16 20 AUX_RX_HALF_SYM_PERIOD 21 29 mmDP_AUX3_AUX_GTC_SYNC_ERROR_CONTROL 0 0x1fb3 4 0 2 AUX_GTC_POTENTIAL_ERROR_THRESHOLD 0 4 AUX_GTC_DEFINITE_ERROR_THRESHOLD 8 12 AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_LEN 16 17 AUX_GTC_SYNC_NUM_RETRY_FOR_LOCK_MAINT 20 21 mmDP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS 0 0x1fb4 12 0 2 AUX_GTC_SYNC_LOCK_ACQ_COMPLETE 0 0 AUX_GTC_SYNC_LOCK_LOST 4 4 AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_OCCURRED 8 8 AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_STATE 9 12 AUX_GTC_SYNC_PHASE_ADJUST_TIME_VIOL 16 16 AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED 20 20 AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED_ACK 21 21 AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED 22 22 AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED_ACK 23 23 AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED 24 24 AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED_ACK 25 25 AUX_GTC_SYNC_CTRL_STATE 28 31 mmDP_AUX3_AUX_GTC_SYNC_STATUS 0 0x1fb5 19 0 2 AUX_GTC_SYNC_DONE 0 0 AUX_GTC_SYNC_REQ 1 1 AUX_GTC_SYNC_RX_TIMEOUT_STATE 4 6 AUX_GTC_SYNC_TIMEOUT 7 7 AUX_GTC_SYNC_RX_OVERFLOW 8 8 AUX_GTC_SYNC_HPD_DISCON 9 9 AUX_GTC_SYNC_RX_PARTIAL_BYTE 10 10 AUX_GTC_SYNC_NON_AUX_MODE 11 11 AUX_GTC_SYNC_RX_MIN_COUNT_VIOL 12 12 AUX_GTC_SYNC_RX_INVALID_STOP 14 14 AUX_GTC_SYNC_RX_SYNC_INVALID_L 17 17 AUX_GTC_SYNC_RX_SYNC_INVALID_H 18 18 AUX_GTC_SYNC_RX_INVALID_START 19 19 AUX_GTC_SYNC_RX_RECV_NO_DET 20 20 AUX_GTC_SYNC_RX_RECV_INVALID_H 22 22 AUX_GTC_SYNC_RX_RECV_INVALID_L 23 23 AUX_GTC_SYNC_REPLY_BYTE_COUNT 24 28 AUX_GTC_SYNC_NACKED 29 29 AUX_GTC_MASTER_REQ_BY_RX 30 30 mmDP_AUX4_AUX_CONTROL 0 0x1fc0 13 0 2 AUX_EN 0 0 AUX_RESET 4 4 AUX_RESET_DONE 5 5 AUX_LS_READ_EN 8 8 AUX_LS_UPDATE_DISABLE 12 12 AUX_IGNORE_HPD_DISCON 16 16 AUX_MODE_DET_EN 18 18 AUX_HPD_SEL 20 22 AUX_IMPCAL_REQ_EN 24 24 AUX_TEST_MODE 28 28 AUX_DEGLITCH_EN 29 29 SPARE_0 30 30 SPARE_1 31 31 mmDP_AUX4_AUX_SW_CONTROL 0 0x1fc1 4 0 2 AUX_SW_GO 0 0 AUX_LS_READ_TRIG 2 2 AUX_SW_START_DELAY 4 7 AUX_SW_WR_BYTES 16 20 mmDP_AUX4_AUX_ARB_CONTROL 0 0x1fc2 10 0 2 AUX_ARB_PRIORITY 0 1 AUX_REG_RW_CNTL_STATUS 2 3 AUX_NO_QUEUED_SW_GO 8 8 AUX_NO_QUEUED_LS_GO 10 10 AUX_SW_USE_AUX_REG_REQ 16 16 AUX_SW_PENDING_USE_AUX_REG_REQ 16 16 AUX_SW_DONE_USING_AUX_REG 17 17 AUX_DMCU_USE_AUX_REG_REQ 24 24 AUX_DMCU_PENDING_USE_AUX_REG_REQ 24 24 AUX_DMCU_DONE_USING_AUX_REG 25 25 mmDP_AUX4_AUX_INTERRUPT_CONTROL 0 0x1fc3 12 0 2 AUX_SW_DONE_INT 0 0 AUX_SW_DONE_ACK 1 1 AUX_SW_DONE_MASK 2 2 AUX_LS_DONE_INT 4 4 AUX_LS_DONE_ACK 5 5 AUX_LS_DONE_MASK 6 6 AUX_GTC_SYNC_LOCK_DONE_INT 8 8 AUX_GTC_SYNC_LOCK_DONE_ACK 9 9 AUX_GTC_SYNC_LOCK_DONE_INT_MASK 10 10 AUX_GTC_SYNC_ERROR_INT 12 12 AUX_GTC_SYNC_ERROR_ACK 13 13 AUX_GTC_SYNC_ERROR_INT_MASK 14 14 mmDP_AUX4_AUX_SW_STATUS 0 0x1fc4 18 0 2 AUX_SW_DONE 0 0 AUX_SW_REQ 1 1 AUX_SW_RX_TIMEOUT_STATE 4 6 AUX_SW_RX_TIMEOUT 7 7 AUX_SW_RX_OVERFLOW 8 8 AUX_SW_HPD_DISCON 9 9 AUX_SW_RX_PARTIAL_BYTE 10 10 AUX_SW_NON_AUX_MODE 11 11 AUX_SW_RX_MIN_COUNT_VIOL 12 12 AUX_SW_RX_INVALID_STOP 14 14 AUX_SW_RX_SYNC_INVALID_L 17 17 AUX_SW_RX_SYNC_INVALID_H 18 18 AUX_SW_RX_INVALID_START 19 19 AUX_SW_RX_RECV_NO_DET 20 20 AUX_SW_RX_RECV_INVALID_H 22 22 AUX_SW_RX_RECV_INVALID_L 23 23 AUX_SW_REPLY_BYTE_COUNT 24 28 AUX_ARB_STATUS 30 31 mmDP_AUX4_AUX_LS_STATUS 0 0x1fc5 20 0 2 AUX_LS_DONE 0 0 AUX_LS_REQ 1 1 AUX_LS_RX_TIMEOUT_STATE 4 6 AUX_LS_RX_TIMEOUT 7 7 AUX_LS_RX_OVERFLOW 8 8 AUX_LS_HPD_DISCON 9 9 AUX_LS_RX_PARTIAL_BYTE 10 10 AUX_LS_NON_AUX_MODE 11 11 AUX_LS_RX_MIN_COUNT_VIOL 12 12 AUX_LS_RX_INVALID_STOP 14 14 AUX_LS_RX_SYNC_INVALID_L 17 17 AUX_LS_RX_SYNC_INVALID_H 18 18 AUX_LS_RX_INVALID_START 19 19 AUX_LS_RX_RECV_NO_DET 20 20 AUX_LS_RX_RECV_INVALID_H 22 22 AUX_LS_RX_RECV_INVALID_L 23 23 AUX_LS_REPLY_BYTE_COUNT 24 28 AUX_LS_CP_IRQ 29 29 AUX_LS_UPDATED 30 30 AUX_LS_UPDATED_ACK 31 31 mmDP_AUX4_AUX_SW_DATA 0 0x1fc6 4 0 2 AUX_SW_DATA_RW 0 0 AUX_SW_DATA 8 15 AUX_SW_INDEX 16 20 AUX_SW_AUTOINCREMENT_DISABLE 31 31 mmDP_AUX4_AUX_LS_DATA 0 0x1fc7 2 0 2 AUX_LS_DATA 8 15 AUX_LS_INDEX 16 20 mmDP_AUX4_AUX_DPHY_TX_REF_CONTROL 0 0x1fc8 3 0 2 AUX_TX_REF_SEL 0 0 AUX_TX_RATE 4 5 AUX_TX_REF_DIV 16 24 mmDP_AUX4_AUX_DPHY_TX_CONTROL 0 0x1fc9 3 0 2 AUX_TX_PRECHARGE_LEN 0 2 AUX_TX_PRECHARGE_SYMBOLS 8 13 AUX_MODE_DET_CHECK_DELAY 16 18 mmDP_AUX4_AUX_DPHY_RX_CONTROL0 0 0x1fca 10 0 2 AUX_RX_START_WINDOW 4 6 AUX_RX_RECEIVE_WINDOW 8 10 AUX_RX_HALF_SYM_DETECT_LEN 12 13 AUX_RX_TRANSITION_FILTER_EN 16 16 AUX_RX_ALLOW_BELOW_THRESHOLD_PHASE_DETECT 17 17 AUX_RX_ALLOW_BELOW_THRESHOLD_START 18 18 AUX_RX_ALLOW_BELOW_THRESHOLD_STOP 19 19 AUX_RX_PHASE_DETECT_LEN 20 21 AUX_RX_TIMEOUT_LEN 24 26 AUX_RX_DETECTION_THRESHOLD 28 30 mmDP_AUX4_AUX_DPHY_RX_CONTROL1 0 0x1fcb 1 0 2 AUX_RX_PRECHARGE_SKIP 0 7 mmDP_AUX4_AUX_DPHY_TX_STATUS 0 0x1fcc 3 0 2 AUX_TX_ACTIVE 0 0 AUX_TX_STATE 4 6 AUX_TX_HALF_SYM_PERIOD 16 24 mmDP_AUX4_AUX_DPHY_RX_STATUS 0 0x1fcd 4 0 2 AUX_RX_STATE 0 2 AUX_RX_SYNC_VALID_COUNT 8 12 AUX_RX_HALF_SYM_PERIOD_FRACT 16 20 AUX_RX_HALF_SYM_PERIOD 21 29 mmDP_AUX4_AUX_GTC_SYNC_ERROR_CONTROL 0 0x1fcf 4 0 2 AUX_GTC_POTENTIAL_ERROR_THRESHOLD 0 4 AUX_GTC_DEFINITE_ERROR_THRESHOLD 8 12 AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_LEN 16 17 AUX_GTC_SYNC_NUM_RETRY_FOR_LOCK_MAINT 20 21 mmDP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS 0 0x1fd0 12 0 2 AUX_GTC_SYNC_LOCK_ACQ_COMPLETE 0 0 AUX_GTC_SYNC_LOCK_LOST 4 4 AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_OCCURRED 8 8 AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_STATE 9 12 AUX_GTC_SYNC_PHASE_ADJUST_TIME_VIOL 16 16 AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED 20 20 AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED_ACK 21 21 AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED 22 22 AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED_ACK 23 23 AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED 24 24 AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED_ACK 25 25 AUX_GTC_SYNC_CTRL_STATE 28 31 mmDP_AUX4_AUX_GTC_SYNC_STATUS 0 0x1fd1 19 0 2 AUX_GTC_SYNC_DONE 0 0 AUX_GTC_SYNC_REQ 1 1 AUX_GTC_SYNC_RX_TIMEOUT_STATE 4 6 AUX_GTC_SYNC_TIMEOUT 7 7 AUX_GTC_SYNC_RX_OVERFLOW 8 8 AUX_GTC_SYNC_HPD_DISCON 9 9 AUX_GTC_SYNC_RX_PARTIAL_BYTE 10 10 AUX_GTC_SYNC_NON_AUX_MODE 11 11 AUX_GTC_SYNC_RX_MIN_COUNT_VIOL 12 12 AUX_GTC_SYNC_RX_INVALID_STOP 14 14 AUX_GTC_SYNC_RX_SYNC_INVALID_L 17 17 AUX_GTC_SYNC_RX_SYNC_INVALID_H 18 18 AUX_GTC_SYNC_RX_INVALID_START 19 19 AUX_GTC_SYNC_RX_RECV_NO_DET 20 20 AUX_GTC_SYNC_RX_RECV_INVALID_H 22 22 AUX_GTC_SYNC_RX_RECV_INVALID_L 23 23 AUX_GTC_SYNC_REPLY_BYTE_COUNT 24 28 AUX_GTC_SYNC_NACKED 29 29 AUX_GTC_MASTER_REQ_BY_RX 30 30 mmDP_AUX5_AUX_CONTROL 0 0x1fdc 13 0 2 AUX_EN 0 0 AUX_RESET 4 4 AUX_RESET_DONE 5 5 AUX_LS_READ_EN 8 8 AUX_LS_UPDATE_DISABLE 12 12 AUX_IGNORE_HPD_DISCON 16 16 AUX_MODE_DET_EN 18 18 AUX_HPD_SEL 20 22 AUX_IMPCAL_REQ_EN 24 24 AUX_TEST_MODE 28 28 AUX_DEGLITCH_EN 29 29 SPARE_0 30 30 SPARE_1 31 31 mmDP_AUX5_AUX_SW_CONTROL 0 0x1fdd 4 0 2 AUX_SW_GO 0 0 AUX_LS_READ_TRIG 2 2 AUX_SW_START_DELAY 4 7 AUX_SW_WR_BYTES 16 20 mmDP_AUX5_AUX_ARB_CONTROL 0 0x1fde 10 0 2 AUX_ARB_PRIORITY 0 1 AUX_REG_RW_CNTL_STATUS 2 3 AUX_NO_QUEUED_SW_GO 8 8 AUX_NO_QUEUED_LS_GO 10 10 AUX_SW_USE_AUX_REG_REQ 16 16 AUX_SW_PENDING_USE_AUX_REG_REQ 16 16 AUX_SW_DONE_USING_AUX_REG 17 17 AUX_DMCU_USE_AUX_REG_REQ 24 24 AUX_DMCU_PENDING_USE_AUX_REG_REQ 24 24 AUX_DMCU_DONE_USING_AUX_REG 25 25 mmDP_AUX5_AUX_INTERRUPT_CONTROL 0 0x1fdf 12 0 2 AUX_SW_DONE_INT 0 0 AUX_SW_DONE_ACK 1 1 AUX_SW_DONE_MASK 2 2 AUX_LS_DONE_INT 4 4 AUX_LS_DONE_ACK 5 5 AUX_LS_DONE_MASK 6 6 AUX_GTC_SYNC_LOCK_DONE_INT 8 8 AUX_GTC_SYNC_LOCK_DONE_ACK 9 9 AUX_GTC_SYNC_LOCK_DONE_INT_MASK 10 10 AUX_GTC_SYNC_ERROR_INT 12 12 AUX_GTC_SYNC_ERROR_ACK 13 13 AUX_GTC_SYNC_ERROR_INT_MASK 14 14 mmDP_AUX5_AUX_SW_STATUS 0 0x1fe0 18 0 2 AUX_SW_DONE 0 0 AUX_SW_REQ 1 1 AUX_SW_RX_TIMEOUT_STATE 4 6 AUX_SW_RX_TIMEOUT 7 7 AUX_SW_RX_OVERFLOW 8 8 AUX_SW_HPD_DISCON 9 9 AUX_SW_RX_PARTIAL_BYTE 10 10 AUX_SW_NON_AUX_MODE 11 11 AUX_SW_RX_MIN_COUNT_VIOL 12 12 AUX_SW_RX_INVALID_STOP 14 14 AUX_SW_RX_SYNC_INVALID_L 17 17 AUX_SW_RX_SYNC_INVALID_H 18 18 AUX_SW_RX_INVALID_START 19 19 AUX_SW_RX_RECV_NO_DET 20 20 AUX_SW_RX_RECV_INVALID_H 22 22 AUX_SW_RX_RECV_INVALID_L 23 23 AUX_SW_REPLY_BYTE_COUNT 24 28 AUX_ARB_STATUS 30 31 mmDP_AUX5_AUX_LS_STATUS 0 0x1fe1 20 0 2 AUX_LS_DONE 0 0 AUX_LS_REQ 1 1 AUX_LS_RX_TIMEOUT_STATE 4 6 AUX_LS_RX_TIMEOUT 7 7 AUX_LS_RX_OVERFLOW 8 8 AUX_LS_HPD_DISCON 9 9 AUX_LS_RX_PARTIAL_BYTE 10 10 AUX_LS_NON_AUX_MODE 11 11 AUX_LS_RX_MIN_COUNT_VIOL 12 12 AUX_LS_RX_INVALID_STOP 14 14 AUX_LS_RX_SYNC_INVALID_L 17 17 AUX_LS_RX_SYNC_INVALID_H 18 18 AUX_LS_RX_INVALID_START 19 19 AUX_LS_RX_RECV_NO_DET 20 20 AUX_LS_RX_RECV_INVALID_H 22 22 AUX_LS_RX_RECV_INVALID_L 23 23 AUX_LS_REPLY_BYTE_COUNT 24 28 AUX_LS_CP_IRQ 29 29 AUX_LS_UPDATED 30 30 AUX_LS_UPDATED_ACK 31 31 mmDP_AUX5_AUX_SW_DATA 0 0x1fe2 4 0 2 AUX_SW_DATA_RW 0 0 AUX_SW_DATA 8 15 AUX_SW_INDEX 16 20 AUX_SW_AUTOINCREMENT_DISABLE 31 31 mmDP_AUX5_AUX_LS_DATA 0 0x1fe3 2 0 2 AUX_LS_DATA 8 15 AUX_LS_INDEX 16 20 mmDP_AUX5_AUX_DPHY_TX_REF_CONTROL 0 0x1fe4 3 0 2 AUX_TX_REF_SEL 0 0 AUX_TX_RATE 4 5 AUX_TX_REF_DIV 16 24 mmDP_AUX5_AUX_DPHY_TX_CONTROL 0 0x1fe5 3 0 2 AUX_TX_PRECHARGE_LEN 0 2 AUX_TX_PRECHARGE_SYMBOLS 8 13 AUX_MODE_DET_CHECK_DELAY 16 18 mmDP_AUX5_AUX_DPHY_RX_CONTROL0 0 0x1fe6 10 0 2 AUX_RX_START_WINDOW 4 6 AUX_RX_RECEIVE_WINDOW 8 10 AUX_RX_HALF_SYM_DETECT_LEN 12 13 AUX_RX_TRANSITION_FILTER_EN 16 16 AUX_RX_ALLOW_BELOW_THRESHOLD_PHASE_DETECT 17 17 AUX_RX_ALLOW_BELOW_THRESHOLD_START 18 18 AUX_RX_ALLOW_BELOW_THRESHOLD_STOP 19 19 AUX_RX_PHASE_DETECT_LEN 20 21 AUX_RX_TIMEOUT_LEN 24 26 AUX_RX_DETECTION_THRESHOLD 28 30 mmDP_AUX5_AUX_DPHY_RX_CONTROL1 0 0x1fe7 1 0 2 AUX_RX_PRECHARGE_SKIP 0 7 mmDP_AUX5_AUX_DPHY_TX_STATUS 0 0x1fe8 3 0 2 AUX_TX_ACTIVE 0 0 AUX_TX_STATE 4 6 AUX_TX_HALF_SYM_PERIOD 16 24 mmDP_AUX5_AUX_DPHY_RX_STATUS 0 0x1fe9 4 0 2 AUX_RX_STATE 0 2 AUX_RX_SYNC_VALID_COUNT 8 12 AUX_RX_HALF_SYM_PERIOD_FRACT 16 20 AUX_RX_HALF_SYM_PERIOD 21 29 mmDP_AUX5_AUX_GTC_SYNC_ERROR_CONTROL 0 0x1feb 4 0 2 AUX_GTC_POTENTIAL_ERROR_THRESHOLD 0 4 AUX_GTC_DEFINITE_ERROR_THRESHOLD 8 12 AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_LEN 16 17 AUX_GTC_SYNC_NUM_RETRY_FOR_LOCK_MAINT 20 21 mmDP_AUX5_AUX_GTC_SYNC_CONTROLLER_STATUS 0 0x1fec 12 0 2 AUX_GTC_SYNC_LOCK_ACQ_COMPLETE 0 0 AUX_GTC_SYNC_LOCK_LOST 4 4 AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_OCCURRED 8 8 AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_STATE 9 12 AUX_GTC_SYNC_PHASE_ADJUST_TIME_VIOL 16 16 AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED 20 20 AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED_ACK 21 21 AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED 22 22 AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED_ACK 23 23 AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED 24 24 AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED_ACK 25 25 AUX_GTC_SYNC_CTRL_STATE 28 31 mmDP_AUX5_AUX_GTC_SYNC_STATUS 0 0x1fed 19 0 2 AUX_GTC_SYNC_DONE 0 0 AUX_GTC_SYNC_REQ 1 1 AUX_GTC_SYNC_RX_TIMEOUT_STATE 4 6 AUX_GTC_SYNC_TIMEOUT 7 7 AUX_GTC_SYNC_RX_OVERFLOW 8 8 AUX_GTC_SYNC_HPD_DISCON 9 9 AUX_GTC_SYNC_RX_PARTIAL_BYTE 10 10 AUX_GTC_SYNC_NON_AUX_MODE 11 11 AUX_GTC_SYNC_RX_MIN_COUNT_VIOL 12 12 AUX_GTC_SYNC_RX_INVALID_STOP 14 14 AUX_GTC_SYNC_RX_SYNC_INVALID_L 17 17 AUX_GTC_SYNC_RX_SYNC_INVALID_H 18 18 AUX_GTC_SYNC_RX_INVALID_START 19 19 AUX_GTC_SYNC_RX_RECV_NO_DET 20 20 AUX_GTC_SYNC_RX_RECV_INVALID_H 22 22 AUX_GTC_SYNC_RX_RECV_INVALID_L 23 23 AUX_GTC_SYNC_REPLY_BYTE_COUNT 24 28 AUX_GTC_SYNC_NACKED 29 29 AUX_GTC_MASTER_REQ_BY_RX 30 30 mmDP_AUX6_AUX_CONTROL 0 0x1ff8 13 0 2 AUX_EN 0 0 AUX_RESET 4 4 AUX_RESET_DONE 5 5 AUX_LS_READ_EN 8 8 AUX_LS_UPDATE_DISABLE 12 12 AUX_IGNORE_HPD_DISCON 16 16 AUX_MODE_DET_EN 18 18 AUX_HPD_SEL 20 22 AUX_IMPCAL_REQ_EN 24 24 AUX_TEST_MODE 28 28 AUX_DEGLITCH_EN 29 29 SPARE_0 30 30 SPARE_1 31 31 mmDP_AUX6_AUX_SW_CONTROL 0 0x1ff9 4 0 2 AUX_SW_GO 0 0 AUX_LS_READ_TRIG 2 2 AUX_SW_START_DELAY 4 7 AUX_SW_WR_BYTES 16 20 mmDP_AUX6_AUX_ARB_CONTROL 0 0x1ffa 10 0 2 AUX_ARB_PRIORITY 0 1 AUX_REG_RW_CNTL_STATUS 2 3 AUX_NO_QUEUED_SW_GO 8 8 AUX_NO_QUEUED_LS_GO 10 10 AUX_SW_USE_AUX_REG_REQ 16 16 AUX_SW_PENDING_USE_AUX_REG_REQ 16 16 AUX_SW_DONE_USING_AUX_REG 17 17 AUX_DMCU_USE_AUX_REG_REQ 24 24 AUX_DMCU_PENDING_USE_AUX_REG_REQ 24 24 AUX_DMCU_DONE_USING_AUX_REG 25 25 mmDP_AUX6_AUX_INTERRUPT_CONTROL 0 0x1ffb 12 0 2 AUX_SW_DONE_INT 0 0 AUX_SW_DONE_ACK 1 1 AUX_SW_DONE_MASK 2 2 AUX_LS_DONE_INT 4 4 AUX_LS_DONE_ACK 5 5 AUX_LS_DONE_MASK 6 6 AUX_GTC_SYNC_LOCK_DONE_INT 8 8 AUX_GTC_SYNC_LOCK_DONE_ACK 9 9 AUX_GTC_SYNC_LOCK_DONE_INT_MASK 10 10 AUX_GTC_SYNC_ERROR_INT 12 12 AUX_GTC_SYNC_ERROR_ACK 13 13 AUX_GTC_SYNC_ERROR_INT_MASK 14 14 mmDP_AUX6_AUX_SW_STATUS 0 0x1ffc 18 0 2 AUX_SW_DONE 0 0 AUX_SW_REQ 1 1 AUX_SW_RX_TIMEOUT_STATE 4 6 AUX_SW_RX_TIMEOUT 7 7 AUX_SW_RX_OVERFLOW 8 8 AUX_SW_HPD_DISCON 9 9 AUX_SW_RX_PARTIAL_BYTE 10 10 AUX_SW_NON_AUX_MODE 11 11 AUX_SW_RX_MIN_COUNT_VIOL 12 12 AUX_SW_RX_INVALID_STOP 14 14 AUX_SW_RX_SYNC_INVALID_L 17 17 AUX_SW_RX_SYNC_INVALID_H 18 18 AUX_SW_RX_INVALID_START 19 19 AUX_SW_RX_RECV_NO_DET 20 20 AUX_SW_RX_RECV_INVALID_H 22 22 AUX_SW_RX_RECV_INVALID_L 23 23 AUX_SW_REPLY_BYTE_COUNT 24 28 AUX_ARB_STATUS 30 31 mmDP_AUX6_AUX_LS_STATUS 0 0x1ffd 20 0 2 AUX_LS_DONE 0 0 AUX_LS_REQ 1 1 AUX_LS_RX_TIMEOUT_STATE 4 6 AUX_LS_RX_TIMEOUT 7 7 AUX_LS_RX_OVERFLOW 8 8 AUX_LS_HPD_DISCON 9 9 AUX_LS_RX_PARTIAL_BYTE 10 10 AUX_LS_NON_AUX_MODE 11 11 AUX_LS_RX_MIN_COUNT_VIOL 12 12 AUX_LS_RX_INVALID_STOP 14 14 AUX_LS_RX_SYNC_INVALID_L 17 17 AUX_LS_RX_SYNC_INVALID_H 18 18 AUX_LS_RX_INVALID_START 19 19 AUX_LS_RX_RECV_NO_DET 20 20 AUX_LS_RX_RECV_INVALID_H 22 22 AUX_LS_RX_RECV_INVALID_L 23 23 AUX_LS_REPLY_BYTE_COUNT 24 28 AUX_LS_CP_IRQ 29 29 AUX_LS_UPDATED 30 30 AUX_LS_UPDATED_ACK 31 31 mmDP_AUX6_AUX_SW_DATA 0 0x1ffe 4 0 2 AUX_SW_DATA_RW 0 0 AUX_SW_DATA 8 15 AUX_SW_INDEX 16 20 AUX_SW_AUTOINCREMENT_DISABLE 31 31 mmDP_AUX6_AUX_LS_DATA 0 0x1fff 2 0 2 AUX_LS_DATA 8 15 AUX_LS_INDEX 16 20 mmDP_AUX6_AUX_DPHY_TX_REF_CONTROL 0 0x2000 3 0 2 AUX_TX_REF_SEL 0 0 AUX_TX_RATE 4 5 AUX_TX_REF_DIV 16 24 mmDP_AUX6_AUX_DPHY_TX_CONTROL 0 0x2001 3 0 2 AUX_TX_PRECHARGE_LEN 0 2 AUX_TX_PRECHARGE_SYMBOLS 8 13 AUX_MODE_DET_CHECK_DELAY 16 18 mmDP_AUX6_AUX_DPHY_RX_CONTROL0 0 0x2002 10 0 2 AUX_RX_START_WINDOW 4 6 AUX_RX_RECEIVE_WINDOW 8 10 AUX_RX_HALF_SYM_DETECT_LEN 12 13 AUX_RX_TRANSITION_FILTER_EN 16 16 AUX_RX_ALLOW_BELOW_THRESHOLD_PHASE_DETECT 17 17 AUX_RX_ALLOW_BELOW_THRESHOLD_START 18 18 AUX_RX_ALLOW_BELOW_THRESHOLD_STOP 19 19 AUX_RX_PHASE_DETECT_LEN 20 21 AUX_RX_TIMEOUT_LEN 24 26 AUX_RX_DETECTION_THRESHOLD 28 30 mmDP_AUX6_AUX_DPHY_RX_CONTROL1 0 0x2003 1 0 2 AUX_RX_PRECHARGE_SKIP 0 7 mmDP_AUX6_AUX_DPHY_TX_STATUS 0 0x2004 3 0 2 AUX_TX_ACTIVE 0 0 AUX_TX_STATE 4 6 AUX_TX_HALF_SYM_PERIOD 16 24 mmDP_AUX6_AUX_DPHY_RX_STATUS 0 0x2005 4 0 2 AUX_RX_STATE 0 2 AUX_RX_SYNC_VALID_COUNT 8 12 AUX_RX_HALF_SYM_PERIOD_FRACT 16 20 AUX_RX_HALF_SYM_PERIOD 21 29 mmDP_AUX6_AUX_GTC_SYNC_ERROR_CONTROL 0 0x2007 4 0 2 AUX_GTC_POTENTIAL_ERROR_THRESHOLD 0 4 AUX_GTC_DEFINITE_ERROR_THRESHOLD 8 12 AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_LEN 16 17 AUX_GTC_SYNC_NUM_RETRY_FOR_LOCK_MAINT 20 21 mmDP_AUX6_AUX_GTC_SYNC_CONTROLLER_STATUS 0 0x2008 12 0 2 AUX_GTC_SYNC_LOCK_ACQ_COMPLETE 0 0 AUX_GTC_SYNC_LOCK_LOST 4 4 AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_OCCURRED 8 8 AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_STATE 9 12 AUX_GTC_SYNC_PHASE_ADJUST_TIME_VIOL 16 16 AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED 20 20 AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED_ACK 21 21 AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED 22 22 AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED_ACK 23 23 AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED 24 24 AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED_ACK 25 25 AUX_GTC_SYNC_CTRL_STATE 28 31 mmDP_AUX6_AUX_GTC_SYNC_STATUS 0 0x2009 19 0 2 AUX_GTC_SYNC_DONE 0 0 AUX_GTC_SYNC_REQ 1 1 AUX_GTC_SYNC_RX_TIMEOUT_STATE 4 6 AUX_GTC_SYNC_TIMEOUT 7 7 AUX_GTC_SYNC_RX_OVERFLOW 8 8 AUX_GTC_SYNC_HPD_DISCON 9 9 AUX_GTC_SYNC_RX_PARTIAL_BYTE 10 10 AUX_GTC_SYNC_NON_AUX_MODE 11 11 AUX_GTC_SYNC_RX_MIN_COUNT_VIOL 12 12 AUX_GTC_SYNC_RX_INVALID_STOP 14 14 AUX_GTC_SYNC_RX_SYNC_INVALID_L 17 17 AUX_GTC_SYNC_RX_SYNC_INVALID_H 18 18 AUX_GTC_SYNC_RX_INVALID_START 19 19 AUX_GTC_SYNC_RX_RECV_NO_DET 20 20 AUX_GTC_SYNC_RX_RECV_INVALID_H 22 22 AUX_GTC_SYNC_RX_RECV_INVALID_L 23 23 AUX_GTC_SYNC_REPLY_BYTE_COUNT 24 28 AUX_GTC_SYNC_NACKED 29 29 AUX_GTC_MASTER_REQ_BY_RX 30 30 mmDIG0_DIG_FE_CNTL 0 0x2068 8 0 2 DIG_SOURCE_SELECT 0 2 DIG_STEREOSYNC_SELECT 4 6 DIG_STEREOSYNC_GATE_EN 8 8 DIG_START 10 10 DIG_DIGITAL_BYPASS_SELECT 12 14 DIG_SYMCLK_FE_ON 24 24 TMDS_PIXEL_ENCODING 28 28 TMDS_COLOR_FORMAT 30 31 mmDIG0_DIG_OUTPUT_CRC_CNTL 0 0x2069 3 0 2 DIG_OUTPUT_CRC_EN 0 0 DIG_OUTPUT_CRC_LINK_SEL 4 4 DIG_OUTPUT_CRC_DATA_SEL 8 9 mmDIG0_DIG_OUTPUT_CRC_RESULT 0 0x206a 1 0 2 DIG_OUTPUT_CRC_RESULT 0 29 mmDIG0_DIG_CLOCK_PATTERN 0 0x206b 1 0 2 DIG_CLOCK_PATTERN 0 9 mmDIG0_DIG_TEST_PATTERN 0 0x206c 6 0 2 DIG_TEST_PATTERN_OUT_EN 0 0 DIG_HALF_CLOCK_PATTERN_SEL 1 1 DIG_RANDOM_PATTERN_OUT_EN 4 4 DIG_RANDOM_PATTERN_RESET 5 5 DIG_TEST_PATTERN_EXTERNAL_RESET_EN 6 6 DIG_STATIC_TEST_PATTERN 16 25 mmDIG0_DIG_RANDOM_PATTERN_SEED 0 0x206d 2 0 2 DIG_RANDOM_PATTERN_SEED 0 23 DIG_RAN_PAT_DURING_DE_ONLY 24 24 mmDIG0_DIG_FIFO_STATUS 0 0x206e 11 0 2 DIG_FIFO_LEVEL_ERROR 0 0 DIG_FIFO_USE_OVERWRITE_LEVEL 1 1 DIG_FIFO_OVERWRITE_LEVEL 2 7 DIG_FIFO_ERROR_ACK 8 8 DIG_FIFO_CAL_AVERAGE_LEVEL 10 15 DIG_FIFO_MAXIMUM_LEVEL 16 20 DIG_FIFO_MINIMUM_LEVEL 22 25 DIG_FIFO_READ_CLOCK_SRC 26 26 DIG_FIFO_CALIBRATED 29 29 DIG_FIFO_FORCE_RECAL_AVERAGE 30 30 DIG_FIFO_FORCE_RECOMP_MINMAX 31 31 mmDIG0_HDMI_CONTROL 0 0x2071 9 0 2 HDMI_KEEPOUT_MODE 0 0 HDMI_DATA_SCRAMBLE_EN 1 1 HDMI_CLOCK_CHANNEL_RATE 2 2 HDMI_NO_EXTRA_NULL_PACKET_FILLED 3 3 HDMI_PACKET_GEN_VERSION 4 4 HDMI_ERROR_ACK 8 8 HDMI_ERROR_MASK 9 9 HDMI_DEEP_COLOR_ENABLE 24 24 HDMI_DEEP_COLOR_DEPTH 28 29 mmDIG0_HDMI_STATUS 0 0x2072 4 0 2 HDMI_ACTIVE_AVMUTE 0 0 HDMI_AUDIO_PACKET_ERROR 16 16 HDMI_VBI_PACKET_ERROR 20 20 HDMI_ERROR_INT 27 27 mmDIG0_HDMI_AUDIO_PACKET_CONTROL 0 0x2073 2 0 2 HDMI_AUDIO_DELAY_EN 4 5 HDMI_AUDIO_PACKETS_PER_LINE 16 20 mmDIG0_HDMI_ACR_PACKET_CONTROL 0 0x2074 7 0 2 HDMI_ACR_SEND 0 0 HDMI_ACR_CONT 1 1 HDMI_ACR_SELECT 4 5 HDMI_ACR_SOURCE 8 8 HDMI_ACR_AUTO_SEND 12 12 HDMI_ACR_N_MULTIPLE 16 18 HDMI_ACR_AUDIO_PRIORITY 31 31 mmDIG0_HDMI_VBI_PACKET_CONTROL 0 0x2075 6 0 2 HDMI_NULL_SEND 0 0 HDMI_GC_SEND 4 4 HDMI_GC_CONT 5 5 HDMI_ISRC_SEND 8 8 HDMI_ISRC_CONT 9 9 HDMI_ISRC_LINE 16 21 mmDIG0_HDMI_INFOFRAME_CONTROL0 0 0x2076 4 0 2 HDMI_AUDIO_INFO_SEND 4 4 HDMI_AUDIO_INFO_CONT 5 5 HDMI_MPEG_INFO_SEND 8 8 HDMI_MPEG_INFO_CONT 9 9 mmDIG0_HDMI_INFOFRAME_CONTROL1 0 0x2077 2 0 2 HDMI_AUDIO_INFO_LINE 8 13 HDMI_MPEG_INFO_LINE 16 21 mmDIG0_HDMI_GENERIC_PACKET_CONTROL0 0 0x2078 6 0 2 HDMI_GENERIC0_SEND 0 0 HDMI_GENERIC0_CONT 1 1 HDMI_GENERIC1_SEND 4 4 HDMI_GENERIC1_CONT 5 5 HDMI_GENERIC0_LINE 16 21 HDMI_GENERIC1_LINE 24 29 mmDIG0_AFMT_INTERRUPT_STATUS 0 0x2079 0 0 2 mmDIG0_HDMI_GC 0 0x207b 5 0 2 HDMI_GC_AVMUTE 0 0 HDMI_GC_AVMUTE_CONT 2 2 HDMI_DEFAULT_PHASE 4 4 HDMI_PACKING_PHASE 8 11 HDMI_PACKING_PHASE_OVERRIDE 12 12 mmDIG0_AFMT_AUDIO_PACKET_CONTROL2 0 0x207c 6 0 2 AFMT_AUDIO_LAYOUT_OVRD 0 0 AFMT_AUDIO_LAYOUT_SELECT 1 1 AFMT_AUDIO_CHANNEL_ENABLE 8 15 AFMT_DP_AUDIO_STREAM_ID 16 23 AFMT_HBR_ENABLE_OVRD 24 24 AFMT_60958_OSF_OVRD 28 28 mmDIG0_AFMT_ISRC1_0 0 0x207d 3 0 2 AFMT_ISRC_STATUS 0 2 AFMT_ISRC_CONTINUE 6 6 AFMT_ISRC_VALID 7 7 mmDIG0_AFMT_ISRC1_1 0 0x207e 4 0 2 AFMT_UPC_EAN_ISRC0 0 7 AFMT_UPC_EAN_ISRC1 8 15 AFMT_UPC_EAN_ISRC2 16 23 AFMT_UPC_EAN_ISRC3 24 31 mmDIG0_AFMT_ISRC1_2 0 0x207f 4 0 2 AFMT_UPC_EAN_ISRC4 0 7 AFMT_UPC_EAN_ISRC5 8 15 AFMT_UPC_EAN_ISRC6 16 23 AFMT_UPC_EAN_ISRC7 24 31 mmDIG0_AFMT_ISRC1_3 0 0x2080 4 0 2 AFMT_UPC_EAN_ISRC8 0 7 AFMT_UPC_EAN_ISRC9 8 15 AFMT_UPC_EAN_ISRC10 16 23 AFMT_UPC_EAN_ISRC11 24 31 mmDIG0_AFMT_ISRC1_4 0 0x2081 4 0 2 AFMT_UPC_EAN_ISRC12 0 7 AFMT_UPC_EAN_ISRC13 8 15 AFMT_UPC_EAN_ISRC14 16 23 AFMT_UPC_EAN_ISRC15 24 31 mmDIG0_AFMT_ISRC2_0 0 0x2082 4 0 2 AFMT_UPC_EAN_ISRC16 0 7 AFMT_UPC_EAN_ISRC17 8 15 AFMT_UPC_EAN_ISRC18 16 23 AFMT_UPC_EAN_ISRC19 24 31 mmDIG0_AFMT_ISRC2_1 0 0x2083 4 0 2 AFMT_UPC_EAN_ISRC20 0 7 AFMT_UPC_EAN_ISRC21 8 15 AFMT_UPC_EAN_ISRC22 16 23 AFMT_UPC_EAN_ISRC23 24 31 mmDIG0_AFMT_ISRC2_2 0 0x2084 4 0 2 AFMT_UPC_EAN_ISRC24 0 7 AFMT_UPC_EAN_ISRC25 8 15 AFMT_UPC_EAN_ISRC26 16 23 AFMT_UPC_EAN_ISRC27 24 31 mmDIG0_AFMT_ISRC2_3 0 0x2085 4 0 2 AFMT_UPC_EAN_ISRC28 0 7 AFMT_UPC_EAN_ISRC29 8 15 AFMT_UPC_EAN_ISRC30 16 23 AFMT_UPC_EAN_ISRC31 24 31 mmDIG0_HDMI_GENERIC_PACKET_CONTROL2 0 0x2086 6 0 2 HDMI_GENERIC4_SEND 0 0 HDMI_GENERIC4_CONT 1 1 HDMI_GENERIC5_SEND 4 4 HDMI_GENERIC5_CONT 5 5 HDMI_GENERIC4_LINE 16 21 HDMI_GENERIC5_LINE 24 29 mmDIG0_HDMI_GENERIC_PACKET_CONTROL3 0 0x2087 6 0 2 HDMI_GENERIC6_SEND 0 0 HDMI_GENERIC6_CONT 1 1 HDMI_GENERIC7_SEND 4 4 HDMI_GENERIC7_CONT 5 5 HDMI_GENERIC6_LINE 16 21 HDMI_GENERIC7_LINE 24 29 mmDIG0_HDMI_DB_CONTROL 0 0x2088 5 0 2 HDMI_DB_PENDING 0 0 HDMI_DB_TAKEN 4 4 HDMI_DB_TAKEN_CLR 5 5 HDMI_DB_LOCK 8 8 HDMI_DB_DISABLE 12 12 mmDIG0_AFMT_MPEG_INFO0 0 0x208a 4 0 2 AFMT_MPEG_INFO_CHECKSUM 0 7 AFMT_MPEG_INFO_MB0 8 15 AFMT_MPEG_INFO_MB1 16 23 AFMT_MPEG_INFO_MB2 24 31 mmDIG0_AFMT_MPEG_INFO1 0 0x208b 3 0 2 AFMT_MPEG_INFO_MB3 0 7 AFMT_MPEG_INFO_MF 8 9 AFMT_MPEG_INFO_FR 12 12 mmDIG0_AFMT_GENERIC_HDR 0 0x208c 4 0 2 AFMT_GENERIC_HB0 0 7 AFMT_GENERIC_HB1 8 15 AFMT_GENERIC_HB2 16 23 AFMT_GENERIC_HB3 24 31 mmDIG0_AFMT_GENERIC_0 0 0x208d 4 0 2 AFMT_GENERIC_BYTE0 0 7 AFMT_GENERIC_BYTE1 8 15 AFMT_GENERIC_BYTE2 16 23 AFMT_GENERIC_BYTE3 24 31 mmDIG0_AFMT_GENERIC_1 0 0x208e 4 0 2 AFMT_GENERIC_BYTE4 0 7 AFMT_GENERIC_BYTE5 8 15 AFMT_GENERIC_BYTE6 16 23 AFMT_GENERIC_BYTE7 24 31 mmDIG0_AFMT_GENERIC_2 0 0x208f 4 0 2 AFMT_GENERIC_BYTE8 0 7 AFMT_GENERIC_BYTE9 8 15 AFMT_GENERIC_BYTE10 16 23 AFMT_GENERIC_BYTE11 24 31 mmDIG0_AFMT_GENERIC_3 0 0x2090 4 0 2 AFMT_GENERIC_BYTE12 0 7 AFMT_GENERIC_BYTE13 8 15 AFMT_GENERIC_BYTE14 16 23 AFMT_GENERIC_BYTE15 24 31 mmDIG0_AFMT_GENERIC_4 0 0x2091 4 0 2 AFMT_GENERIC_BYTE16 0 7 AFMT_GENERIC_BYTE17 8 15 AFMT_GENERIC_BYTE18 16 23 AFMT_GENERIC_BYTE19 24 31 mmDIG0_AFMT_GENERIC_5 0 0x2092 4 0 2 AFMT_GENERIC_BYTE20 0 7 AFMT_GENERIC_BYTE21 8 15 AFMT_GENERIC_BYTE22 16 23 AFMT_GENERIC_BYTE23 24 31 mmDIG0_AFMT_GENERIC_6 0 0x2093 4 0 2 AFMT_GENERIC_BYTE24 0 7 AFMT_GENERIC_BYTE25 8 15 AFMT_GENERIC_BYTE26 16 23 AFMT_GENERIC_BYTE27 24 31 mmDIG0_AFMT_GENERIC_7 0 0x2094 4 0 2 AFMT_GENERIC_BYTE28 0 7 AFMT_GENERIC_BYTE29 8 15 AFMT_GENERIC_BYTE30 16 23 AFMT_GENERIC_BYTE31 24 31 mmDIG0_HDMI_GENERIC_PACKET_CONTROL1 0 0x2095 6 0 2 HDMI_GENERIC2_SEND 0 0 HDMI_GENERIC2_CONT 1 1 HDMI_GENERIC3_SEND 4 4 HDMI_GENERIC3_CONT 5 5 HDMI_GENERIC2_LINE 16 21 HDMI_GENERIC3_LINE 24 29 mmDIG0_HDMI_ACR_32_0 0 0x2096 1 0 2 HDMI_ACR_CTS_32 12 31 mmDIG0_HDMI_ACR_32_1 0 0x2097 1 0 2 HDMI_ACR_N_32 0 19 mmDIG0_HDMI_ACR_44_0 0 0x2098 1 0 2 HDMI_ACR_CTS_44 12 31 mmDIG0_HDMI_ACR_44_1 0 0x2099 1 0 2 HDMI_ACR_N_44 0 19 mmDIG0_HDMI_ACR_48_0 0 0x209a 1 0 2 HDMI_ACR_CTS_48 12 31 mmDIG0_HDMI_ACR_48_1 0 0x209b 1 0 2 HDMI_ACR_N_48 0 19 mmDIG0_HDMI_ACR_STATUS_0 0 0x209c 1 0 2 HDMI_ACR_CTS 12 31 mmDIG0_HDMI_ACR_STATUS_1 0 0x209d 1 0 2 HDMI_ACR_N 0 19 mmDIG0_AFMT_AUDIO_INFO0 0 0x209e 5 0 2 AFMT_AUDIO_INFO_CHECKSUM 0 7 AFMT_AUDIO_INFO_CC 8 10 AFMT_AUDIO_INFO_CT 11 14 AFMT_AUDIO_INFO_CHECKSUM_OFFSET 16 23 AFMT_AUDIO_INFO_CXT 24 28 mmDIG0_AFMT_AUDIO_INFO1 0 0x209f 4 0 2 AFMT_AUDIO_INFO_CA 0 7 AFMT_AUDIO_INFO_LSV 11 14 AFMT_AUDIO_INFO_DM_INH 15 15 AFMT_AUDIO_INFO_LFEPBL 16 17 mmDIG0_AFMT_60958_0 0 0x20a0 10 0 2 AFMT_60958_CS_A 0 0 AFMT_60958_CS_B 1 1 AFMT_60958_CS_C 2 2 AFMT_60958_CS_D 3 5 AFMT_60958_CS_MODE 6 7 AFMT_60958_CS_CATEGORY_CODE 8 15 AFMT_60958_CS_SOURCE_NUMBER 16 19 AFMT_60958_CS_CHANNEL_NUMBER_L 20 23 AFMT_60958_CS_SAMPLING_FREQUENCY 24 27 AFMT_60958_CS_CLOCK_ACCURACY 28 29 mmDIG0_AFMT_60958_1 0 0x20a1 5 0 2 AFMT_60958_CS_WORD_LENGTH 0 3 AFMT_60958_CS_ORIGINAL_SAMPLING_FREQUENCY 4 7 AFMT_60958_VALID_L 16 16 AFMT_60958_VALID_R 18 18 AFMT_60958_CS_CHANNEL_NUMBER_R 20 23 mmDIG0_AFMT_AUDIO_CRC_CONTROL 0 0x20a2 5 0 2 AFMT_AUDIO_CRC_EN 0 0 AFMT_AUDIO_CRC_CONT 4 4 AFMT_AUDIO_CRC_SOURCE 8 8 AFMT_AUDIO_CRC_CH_SEL 12 15 AFMT_AUDIO_CRC_COUNT 16 31 mmDIG0_AFMT_RAMP_CONTROL0 0 0x20a3 2 0 2 AFMT_RAMP_MAX_COUNT 0 23 AFMT_RAMP_DATA_SIGN 31 31 mmDIG0_AFMT_RAMP_CONTROL1 0 0x20a4 2 0 2 AFMT_RAMP_MIN_COUNT 0 23 AFMT_AUDIO_TEST_CH_DISABLE 24 31 mmDIG0_AFMT_RAMP_CONTROL2 0 0x20a5 1 0 2 AFMT_RAMP_INC_COUNT 0 23 mmDIG0_AFMT_RAMP_CONTROL3 0 0x20a6 1 0 2 AFMT_RAMP_DEC_COUNT 0 23 mmDIG0_AFMT_60958_2 0 0x20a7 6 0 2 AFMT_60958_CS_CHANNEL_NUMBER_2 0 3 AFMT_60958_CS_CHANNEL_NUMBER_3 4 7 AFMT_60958_CS_CHANNEL_NUMBER_4 8 11 AFMT_60958_CS_CHANNEL_NUMBER_5 12 15 AFMT_60958_CS_CHANNEL_NUMBER_6 16 19 AFMT_60958_CS_CHANNEL_NUMBER_7 20 23 mmDIG0_AFMT_AUDIO_CRC_RESULT 0 0x20a8 2 0 2 AFMT_AUDIO_CRC_DONE 0 0 AFMT_AUDIO_CRC 8 31 mmDIG0_AFMT_STATUS 0 0x20a9 4 0 2 AFMT_AUDIO_ENABLE 4 4 AFMT_AZ_HBR_ENABLE 8 8 AFMT_AUDIO_FIFO_OVERFLOW 24 24 AFMT_AZ_AUDIO_ENABLE_CHG 30 30 mmDIG0_AFMT_AUDIO_PACKET_CONTROL 0 0x20aa 8 0 2 AFMT_AUDIO_SAMPLE_SEND 0 0 AFMT_RESET_FIFO_WHEN_AUDIO_DIS 11 11 AFMT_AUDIO_TEST_EN 12 12 AFMT_AUDIO_TEST_MODE 14 14 AFMT_AUDIO_FIFO_OVERFLOW_ACK 23 23 AFMT_AUDIO_CHANNEL_SWAP 24 24 AFMT_60958_CS_UPDATE 26 26 AFMT_AZ_AUDIO_ENABLE_CHG_ACK 30 30 mmDIG0_AFMT_VBI_PACKET_CONTROL 0 0x20ab 4 0 2 AFMT_GENERIC_LOCK_STATUS 8 8 AFMT_GENERIC_CONFLICT 16 16 AFMT_GENERIC_CONFLICT_CLR 17 17 AFMT_GENERIC_INDEX 28 31 mmDIG0_AFMT_INFOFRAME_CONTROL0 0 0x20ac 3 0 2 AFMT_AUDIO_INFO_SOURCE 6 6 AFMT_AUDIO_INFO_UPDATE 7 7 AFMT_MPEG_INFO_UPDATE 10 10 mmDIG0_AFMT_AUDIO_SRC_CONTROL 0 0x20ad 1 0 2 AFMT_AUDIO_SRC_SELECT 0 2 mmDIG0_DIG_BE_CNTL 0 0x20af 5 0 2 DIG_DUAL_LINK_ENABLE 0 0 DIG_SWAP 1 1 DIG_FE_SOURCE_SELECT 8 14 DIG_MODE 16 18 DIG_HPD_SELECT 28 30 mmDIG0_DIG_BE_EN_CNTL 0 0x20b0 2 0 2 DIG_ENABLE 0 0 DIG_SYMCLK_BE_ON 8 8 mmDIG0_TMDS_CNTL 0 0x20d3 1 0 2 TMDS_SYNC_PHASE 0 0 mmDIG0_TMDS_CONTROL_CHAR 0 0x20d4 4 0 2 TMDS_CONTROL_CHAR0_OUT_EN 0 0 TMDS_CONTROL_CHAR1_OUT_EN 1 1 TMDS_CONTROL_CHAR2_OUT_EN 2 2 TMDS_CONTROL_CHAR3_OUT_EN 3 3 mmDIG0_TMDS_CONTROL0_FEEDBACK 0 0x20d5 2 0 2 TMDS_CONTROL0_FEEDBACK_SELECT 0 1 TMDS_CONTROL0_FEEDBACK_DELAY 8 9 mmDIG0_TMDS_STEREOSYNC_CTL_SEL 0 0x20d6 1 0 2 TMDS_STEREOSYNC_CTL_SEL 0 1 mmDIG0_TMDS_SYNC_CHAR_PATTERN_0_1 0 0x20d7 2 0 2 TMDS_SYNC_CHAR_PATTERN0 0 9 TMDS_SYNC_CHAR_PATTERN1 16 25 mmDIG0_TMDS_SYNC_CHAR_PATTERN_2_3 0 0x20d8 2 0 2 TMDS_SYNC_CHAR_PATTERN2 0 9 TMDS_SYNC_CHAR_PATTERN3 16 25 mmDIG0_TMDS_CTL_BITS 0 0x20da 4 0 2 TMDS_CTL0 0 0 TMDS_CTL1 8 8 TMDS_CTL2 16 16 TMDS_CTL3 24 24 mmDIG0_TMDS_DCBALANCER_CONTROL 0 0x20db 4 0 2 TMDS_DCBALANCER_EN 0 0 TMDS_DCBALANCER_TEST_EN 8 8 TMDS_DCBALANCER_TEST_IN 16 19 TMDS_DCBALANCER_FORCE 24 24 mmDIG0_TMDS_CTL0_1_GEN_CNTL 0 0x20dd 15 0 2 TMDS_CTL0_DATA_SEL 0 3 TMDS_CTL0_DATA_DELAY 4 6 TMDS_CTL0_DATA_INVERT 7 7 TMDS_CTL0_DATA_MODULATION 8 9 TMDS_CTL0_USE_FEEDBACK_PATH 10 10 TMDS_CTL0_FB_SYNC_CONT 11 11 TMDS_CTL0_PATTERN_OUT_EN 12 12 TMDS_CTL1_DATA_SEL 16 19 TMDS_CTL1_DATA_DELAY 20 22 TMDS_CTL1_DATA_INVERT 23 23 TMDS_CTL1_DATA_MODULATION 24 25 TMDS_CTL1_USE_FEEDBACK_PATH 26 26 TMDS_CTL1_FB_SYNC_CONT 27 27 TMDS_CTL1_PATTERN_OUT_EN 28 28 TMDS_2BIT_COUNTER_EN 31 31 mmDIG0_TMDS_CTL2_3_GEN_CNTL 0 0x20de 14 0 2 TMDS_CTL2_DATA_SEL 0 3 TMDS_CTL2_DATA_DELAY 4 6 TMDS_CTL2_DATA_INVERT 7 7 TMDS_CTL2_DATA_MODULATION 8 9 TMDS_CTL2_USE_FEEDBACK_PATH 10 10 TMDS_CTL2_FB_SYNC_CONT 11 11 TMDS_CTL2_PATTERN_OUT_EN 12 12 TMDS_CTL3_DATA_SEL 16 19 TMDS_CTL3_DATA_DELAY 20 22 TMDS_CTL3_DATA_INVERT 23 23 TMDS_CTL3_DATA_MODULATION 24 25 TMDS_CTL3_USE_FEEDBACK_PATH 26 26 TMDS_CTL3_FB_SYNC_CONT 27 27 TMDS_CTL3_PATTERN_OUT_EN 28 28 mmDIG0_DIG_VERSION 0 0x20e0 1 0 2 DIG_TYPE 0 0 mmDIG0_DIG_LANE_ENABLE 0 0x20e1 5 0 2 DIG_LANE0EN 0 0 DIG_LANE1EN 1 1 DIG_LANE2EN 2 2 DIG_LANE3EN 3 3 DIG_CLK_EN 8 8 mmDIG0_AFMT_CNTL 0 0x20e6 2 0 2 AFMT_AUDIO_CLOCK_EN 0 0 AFMT_AUDIO_CLOCK_ON 8 8 mmDIG0_AFMT_VBI_PACKET_CONTROL1 0 0x20e7 32 0 2 AFMT_GENERIC0_FRAME_UPDATE 0 0 AFMT_GENERIC0_FRAME_UPDATE_PENDING 1 1 AFMT_GENERIC0_IMMEDIATE_UPDATE 2 2 AFMT_GENERIC0_IMMEDIATE_UPDATE_PENDING 3 3 AFMT_GENERIC1_FRAME_UPDATE 4 4 AFMT_GENERIC1_FRAME_UPDATE_PENDING 5 5 AFMT_GENERIC1_IMMEDIATE_UPDATE 6 6 AFMT_GENERIC1_IMMEDIATE_UPDATE_PENDING 7 7 AFMT_GENERIC2_FRAME_UPDATE 8 8 AFMT_GENERIC2_FRAME_UPDATE_PENDING 9 9 AFMT_GENERIC2_IMMEDIATE_UPDATE 10 10 AFMT_GENERIC2_IMMEDIATE_UPDATE_PENDING 11 11 AFMT_GENERIC3_FRAME_UPDATE 12 12 AFMT_GENERIC3_FRAME_UPDATE_PENDING 13 13 AFMT_GENERIC3_IMMEDIATE_UPDATE 14 14 AFMT_GENERIC3_IMMEDIATE_UPDATE_PENDING 15 15 AFMT_GENERIC4_FRAME_UPDATE 16 16 AFMT_GENERIC4_FRAME_UPDATE_PENDING 17 17 AFMT_GENERIC4_IMMEDIATE_UPDATE 18 18 AFMT_GENERIC4_IMMEDIATE_UPDATE_PENDING 19 19 AFMT_GENERIC5_FRAME_UPDATE 20 20 AFMT_GENERIC5_FRAME_UPDATE_PENDING 21 21 AFMT_GENERIC5_IMMEDIATE_UPDATE 22 22 AFMT_GENERIC5_IMMEDIATE_UPDATE_PENDING 23 23 AFMT_GENERIC6_FRAME_UPDATE 24 24 AFMT_GENERIC6_FRAME_UPDATE_PENDING 25 25 AFMT_GENERIC6_IMMEDIATE_UPDATE 26 26 AFMT_GENERIC6_IMMEDIATE_UPDATE_PENDING 27 27 AFMT_GENERIC7_FRAME_UPDATE 28 28 AFMT_GENERIC7_FRAME_UPDATE_PENDING 29 29 AFMT_GENERIC7_IMMEDIATE_UPDATE 30 30 AFMT_GENERIC7_IMMEDIATE_UPDATE_PENDING 31 31 mmDP0_DP_LINK_CNTL 0 0x2108 3 0 2 DP_LINK_TRAINING_COMPLETE 4 4 DP_LINK_STATUS 8 8 DP_EMBEDDED_PANEL_MODE 17 17 mmDP0_DP_PIXEL_FORMAT 0 0x2109 3 0 2 DP_PIXEL_ENCODING 0 2 DP_COMPONENT_DEPTH 24 26 DP_PIXEL_COMBINE 28 29 mmDP0_DP_MSA_COLORIMETRY 0 0x210a 1 0 2 DP_MSA_MISC0 24 31 mmDP0_DP_CONFIG 0 0x210b 1 0 2 DP_UDI_LANES 0 1 mmDP0_DP_VID_STREAM_CNTL 0 0x210c 4 0 2 DP_VID_STREAM_ENABLE 0 0 DP_VID_STREAM_DIS_DEFER 8 9 DP_VID_STREAM_STATUS 16 16 DP_VID_STREAM_CHANGE_KEEPOUT 20 20 mmDP0_DP_STEER_FIFO 0 0x210d 7 0 2 DP_STEER_FIFO_RESET 0 0 DP_STEER_OVERFLOW_FLAG 4 4 DP_STEER_OVERFLOW_INT 5 5 DP_STEER_OVERFLOW_ACK 6 6 DP_STEER_OVERFLOW_MASK 7 7 DP_TU_OVERFLOW_FLAG 8 8 DP_TU_OVERFLOW_ACK 12 12 mmDP0_DP_MSA_MISC 0 0x210e 4 0 2 DP_MSA_MISC1 0 7 DP_MSA_MISC2 8 15 DP_MSA_MISC3 16 23 DP_MSA_MISC4 24 31 mmDP0_DP_VID_TIMING 0 0x2110 5 0 2 DP_VID_M_N_DOUBLE_BUFFER_MODE 4 4 DP_VID_M_N_GEN_EN 8 8 DP_VID_N_MUL 10 11 DP_VID_M_DIV 12 13 DP_VID_N_DIV 24 31 mmDP0_DP_VID_N 0 0x2111 1 0 2 DP_VID_N 0 23 mmDP0_DP_VID_M 0 0x2112 1 0 2 DP_VID_M 0 23 mmDP0_DP_LINK_FRAMING_CNTL 0 0x2113 3 0 2 DP_IDLE_BS_INTERVAL 0 17 DP_VBID_DISABLE 24 24 DP_VID_ENHANCED_FRAME_MODE 28 28 mmDP0_DP_HBR2_EYE_PATTERN 0 0x2114 1 0 2 DP_HBR2_EYE_PATTERN_ENABLE 0 0 mmDP0_DP_VID_MSA_VBID 0 0x2115 2 0 2 DP_VID_MSA_LOCATION 0 11 DP_VID_VBID_FIELD_POL 24 24 mmDP0_DP_VID_INTERRUPT_CNTL 0 0x2116 3 0 2 DP_VID_STREAM_DISABLE_INT 0 0 DP_VID_STREAM_DISABLE_ACK 1 1 DP_VID_STREAM_DISABLE_MASK 2 2 mmDP0_DP_DPHY_CNTL 0 0x2117 6 0 2 DPHY_ATEST_SEL_LANE0 0 0 DPHY_ATEST_SEL_LANE1 1 1 DPHY_ATEST_SEL_LANE2 2 2 DPHY_ATEST_SEL_LANE3 3 3 DPHY_BYPASS 16 16 DPHY_SKEW_BYPASS 24 24 mmDP0_DP_DPHY_TRAINING_PATTERN_SEL 0 0x2118 1 0 2 DPHY_TRAINING_PATTERN_SEL 0 1 mmDP0_DP_DPHY_SYM0 0 0x2119 3 0 2 DPHY_SYM1 0 9 DPHY_SYM2 10 19 DPHY_SYM3 20 29 mmDP0_DP_DPHY_SYM1 0 0x211a 3 0 2 DPHY_SYM4 0 9 DPHY_SYM5 10 19 DPHY_SYM6 20 29 mmDP0_DP_DPHY_SYM2 0 0x211b 2 0 2 DPHY_SYM7 0 9 DPHY_SYM8 10 19 mmDP0_DP_DPHY_8B10B_CNTL 0 0x211c 3 0 2 DPHY_8B10B_RESET 8 8 DPHY_8B10B_EXT_DISP 16 16 DPHY_8B10B_CUR_DISP 24 24 mmDP0_DP_DPHY_PRBS_CNTL 0 0x211d 3 0 2 DPHY_PRBS_EN 0 0 DPHY_PRBS_SEL 4 5 DPHY_PRBS_SEED 8 30 mmDP0_DP_DPHY_SCRAM_CNTL 0 0x211e 4 0 2 DPHY_SCRAMBLER_DIS 0 0 DPHY_SCRAMBLER_ADVANCE 4 4 DPHY_SCRAMBLER_BS_COUNT 8 17 DPHY_SCRAMBLER_KCODE 24 24 mmDP0_DP_DPHY_CRC_EN 0 0x211f 3 0 2 DPHY_CRC_EN 0 0 DPHY_CRC_CONT_EN 4 4 DPHY_CRC_RESULT_VALID 8 8 mmDP0_DP_DPHY_CRC_CNTL 0 0x2120 3 0 2 DPHY_CRC_FIELD 0 0 DPHY_CRC_SEL 4 5 DPHY_CRC_MASK 16 23 mmDP0_DP_DPHY_CRC_RESULT 0 0x2121 4 0 2 DPHY_CRC_RESULT 0 7 DPHY_CRC_RESULT1 8 15 DPHY_CRC_RESULT2 16 23 DPHY_CRC_RESULT3 24 31 mmDP0_DP_DPHY_CRC_MST_CNTL 0 0x2122 2 0 2 DPHY_CRC_MST_FIRST_SLOT 0 5 DPHY_CRC_MST_LAST_SLOT 8 13 mmDP0_DP_DPHY_CRC_MST_STATUS 0 0x2123 3 0 2 DPHY_CRC_MST_PHASE_LOCK 0 0 DPHY_CRC_MST_PHASE_ERROR 8 8 DPHY_CRC_MST_PHASE_ERROR_ACK 16 16 mmDP0_DP_DPHY_FAST_TRAINING 0 0x2124 5 0 2 DPHY_RX_FAST_TRAINING_CAPABLE 0 0 DPHY_SW_FAST_TRAINING_START 1 1 DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN 2 2 DPHY_FAST_TRAINING_TP1_TIME 8 19 DPHY_FAST_TRAINING_TP2_TIME 20 31 mmDP0_DP_DPHY_FAST_TRAINING_STATUS 0 0x2125 4 0 2 DPHY_FAST_TRAINING_STATE 0 2 DPHY_FAST_TRAINING_COMPLETE_OCCURRED 4 4 DPHY_FAST_TRAINING_COMPLETE_MASK 8 8 DPHY_FAST_TRAINING_COMPLETE_ACK 12 12 mmDP0_DP_SEC_CNTL 0 0x212b 14 0 2 DP_SEC_STREAM_ENABLE 0 0 DP_SEC_ASP_ENABLE 4 4 DP_SEC_ATP_ENABLE 8 8 DP_SEC_AIP_ENABLE 12 12 DP_SEC_ACM_ENABLE 16 16 DP_SEC_GSP0_ENABLE 20 20 DP_SEC_GSP1_ENABLE 21 21 DP_SEC_GSP2_ENABLE 22 22 DP_SEC_GSP3_ENABLE 23 23 DP_SEC_GSP4_ENABLE 24 24 DP_SEC_GSP5_ENABLE 25 25 DP_SEC_GSP6_ENABLE 26 26 DP_SEC_GSP7_ENABLE 27 27 DP_SEC_MPG_ENABLE 28 28 mmDP0_DP_SEC_CNTL1 0 0x212c 7 0 2 DP_SEC_ISRC_ENABLE 0 0 DP_SEC_GSP0_PRIORITY 4 4 DP_SEC_GSP0_SEND 5 5 DP_SEC_GSP0_SEND_PENDING 6 6 DP_SEC_GSP0_SEND_DEADLINE_MISSED 7 7 DP_SEC_GSP0_SEND_ANY_LINE 8 8 DP_SEC_GSP0_LINE_NUM 16 31 mmDP0_DP_SEC_FRAMING1 0 0x212d 2 0 2 DP_SEC_FRAME_START_LOCATION 0 11 DP_SEC_VBLANK_TRANSMIT_WIDTH 16 31 mmDP0_DP_SEC_FRAMING2 0 0x212e 2 0 2 DP_SEC_START_POSITION 0 15 DP_SEC_HBLANK_TRANSMIT_WIDTH 16 31 mmDP0_DP_SEC_FRAMING3 0 0x212f 2 0 2 DP_SEC_IDLE_FRAME_SIZE 0 13 DP_SEC_IDLE_TRANSMIT_WIDTH 16 31 mmDP0_DP_SEC_FRAMING4 0 0x2130 4 0 2 DP_SEC_COLLISION_STATUS 20 20 DP_SEC_COLLISION_ACK 24 24 DP_SEC_AUDIO_MUTE 28 28 DP_SEC_AUDIO_MUTE_STATUS 29 29 mmDP0_DP_SEC_AUD_N 0 0x2131 1 0 2 DP_SEC_AUD_N 0 23 mmDP0_DP_SEC_AUD_N_READBACK 0 0x2132 1 0 2 DP_SEC_AUD_N_READBACK 0 23 mmDP0_DP_SEC_AUD_M 0 0x2133 1 0 2 DP_SEC_AUD_M 0 23 mmDP0_DP_SEC_AUD_M_READBACK 0 0x2134 1 0 2 DP_SEC_AUD_M_READBACK 0 23 mmDP0_DP_SEC_TIMESTAMP 0 0x2135 1 0 2 DP_SEC_TIMESTAMP_MODE 0 0 mmDP0_DP_SEC_PACKET_CNTL 0 0x2136 4 0 2 DP_SEC_ASP_CODING_TYPE 1 3 DP_SEC_ASP_PRIORITY 4 4 DP_SEC_VERSION 8 13 DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE 16 16 mmDP0_DP_MSE_RATE_CNTL 0 0x2137 2 0 2 DP_MSE_RATE_Y 0 25 DP_MSE_RATE_X 26 31 mmDP0_DP_MSE_RATE_UPDATE 0 0x2139 1 0 2 DP_MSE_RATE_UPDATE_PENDING 0 0 mmDP0_DP_MSE_SAT0 0 0x213a 4 0 2 DP_MSE_SAT_SRC0 0 2 DP_MSE_SAT_SLOT_COUNT0 8 13 DP_MSE_SAT_SRC1 16 18 DP_MSE_SAT_SLOT_COUNT1 24 29 mmDP0_DP_MSE_SAT1 0 0x213b 4 0 2 DP_MSE_SAT_SRC2 0 2 DP_MSE_SAT_SLOT_COUNT2 8 13 DP_MSE_SAT_SRC3 16 18 DP_MSE_SAT_SLOT_COUNT3 24 29 mmDP0_DP_MSE_SAT2 0 0x213c 4 0 2 DP_MSE_SAT_SRC4 0 2 DP_MSE_SAT_SLOT_COUNT4 8 13 DP_MSE_SAT_SRC5 16 18 DP_MSE_SAT_SLOT_COUNT5 24 29 mmDP0_DP_MSE_SAT_UPDATE 0 0x213d 2 0 2 DP_MSE_SAT_UPDATE 0 1 DP_MSE_16_MTP_KEEPOUT 8 8 mmDP0_DP_MSE_LINK_TIMING 0 0x213e 2 0 2 DP_MSE_LINK_FRAME 0 9 DP_MSE_LINK_LINE 16 17 mmDP0_DP_MSE_MISC_CNTL 0 0x213f 3 0 2 DP_MSE_BLANK_CODE 0 0 DP_MSE_TIMESTAMP_MODE 4 4 DP_MSE_ZERO_ENCODER 8 8 mmDP0_DP_DPHY_BS_SR_SWAP_CNTL 0 0x2144 3 0 2 DPHY_LOAD_BS_COUNT 0 9 DPHY_BS_SR_SWAP_DONE 15 15 DPHY_LOAD_BS_COUNT_START 16 16 mmDP0_DP_DPHY_HBR2_PATTERN_CONTROL 0 0x2145 1 0 2 DP_DPHY_HBR2_PATTERN_CONTROL 0 2 mmDP0_DP_MSE_SAT0_STATUS 0 0x2147 4 0 2 DP_MSE_SAT_SRC0_STATUS 0 2 DP_MSE_SAT_SLOT_COUNT0_STATUS 8 13 DP_MSE_SAT_SRC1_STATUS 16 18 DP_MSE_SAT_SLOT_COUNT1_STATUS 24 29 mmDP0_DP_MSE_SAT1_STATUS 0 0x2148 4 0 2 DP_MSE_SAT_SRC2_STATUS 0 2 DP_MSE_SAT_SLOT_COUNT2_STATUS 8 13 DP_MSE_SAT_SRC3_STATUS 16 18 DP_MSE_SAT_SLOT_COUNT3_STATUS 24 29 mmDP0_DP_MSE_SAT2_STATUS 0 0x2149 4 0 2 DP_MSE_SAT_SRC4_STATUS 0 2 DP_MSE_SAT_SLOT_COUNT4_STATUS 8 13 DP_MSE_SAT_SRC5_STATUS 16 18 DP_MSE_SAT_SLOT_COUNT5_STATUS 24 29 mmDP0_DP_MSA_TIMING_PARAM1 0 0x214c 2 0 2 DP_MSA_VTOTAL 0 15 DP_MSA_HTOTAL 16 31 mmDP0_DP_MSA_TIMING_PARAM2 0 0x214d 2 0 2 DP_MSA_VSTART 0 15 DP_MSA_HSTART 16 31 mmDP0_DP_MSA_TIMING_PARAM3 0 0x214e 4 0 2 DP_MSA_VSYNCWIDTH 0 14 DP_MSA_VSYNCPOLARITY 15 15 DP_MSA_HSYNCWIDTH 16 30 DP_MSA_HSYNCPOLARITY 31 31 mmDP0_DP_MSA_TIMING_PARAM4 0 0x214f 2 0 2 DP_MSA_VHEIGHT 0 15 DP_MSA_HWIDTH 16 31 mmDP0_DP_MSO_CNTL 0 0x2150 8 0 2 DP_MSO_NUM_OF_SSTLINK 0 1 DP_MSO_SEC_STREAM_ENABLE 4 7 DP_MSO_SEC_ASP_ENABLE 8 11 DP_MSO_SEC_ATP_ENABLE 12 15 DP_MSO_SEC_AIP_ENABLE 16 19 DP_MSO_SEC_ACM_ENABLE 20 23 DP_MSO_SEC_GSP0_ENABLE 24 27 DP_MSO_SEC_GSP1_ENABLE 28 31 mmDP0_DP_MSO_CNTL1 0 0x2151 8 0 2 DP_MSO_SEC_GSP2_ENABLE 0 3 DP_MSO_SEC_GSP3_ENABLE 4 7 DP_MSO_SEC_GSP4_ENABLE 8 11 DP_MSO_SEC_GSP5_ENABLE 12 15 DP_MSO_SEC_GSP6_ENABLE 16 19 DP_MSO_SEC_GSP7_ENABLE 20 23 DP_MSO_SEC_MPG_ENABLE 24 27 DP_MSO_SEC_ISRC_ENABLE 28 31 mmDP0_DP_DSC_CNTL 0 0x2152 1 0 2 DP_DSC_EN 0 0 mmDP0_DP_SEC_CNTL2 0 0x2153 29 0 2 DP_SEC_GSP1_SEND 0 0 DP_SEC_GSP1_SEND_PENDING 1 1 DP_SEC_GSP1_SEND_DEADLINE_MISSED 2 2 DP_SEC_GSP1_SEND_ANY_LINE 3 3 DP_SEC_GSP2_SEND 4 4 DP_SEC_GSP2_SEND_PENDING 5 5 DP_SEC_GSP2_SEND_DEADLINE_MISSED 6 6 DP_SEC_GSP2_SEND_ANY_LINE 7 7 DP_SEC_GSP3_SEND 8 8 DP_SEC_GSP3_SEND_PENDING 9 9 DP_SEC_GSP3_SEND_DEADLINE_MISSED 10 10 DP_SEC_GSP3_SEND_ANY_LINE 11 11 DP_SEC_GSP4_SEND 12 12 DP_SEC_GSP4_SEND_PENDING 13 13 DP_SEC_GSP4_SEND_DEADLINE_MISSED 14 14 DP_SEC_GSP4_SEND_ANY_LINE 15 15 DP_SEC_GSP5_SEND 16 16 DP_SEC_GSP5_SEND_PENDING 17 17 DP_SEC_GSP5_SEND_DEADLINE_MISSED 18 18 DP_SEC_GSP5_SEND_ANY_LINE 19 19 DP_SEC_GSP6_SEND 20 20 DP_SEC_GSP6_SEND_PENDING 21 21 DP_SEC_GSP6_SEND_DEADLINE_MISSED 22 22 DP_SEC_GSP6_SEND_ANY_LINE 23 23 DP_SEC_GSP7_SEND 24 24 DP_SEC_GSP7_SEND_PENDING 25 25 DP_SEC_GSP7_SEND_DEADLINE_MISSED 26 26 DP_SEC_GSP7_SEND_ANY_LINE 27 27 DP_SEC_GSP7_PPS 28 28 mmDP0_DP_SEC_CNTL3 0 0x2154 2 0 2 DP_SEC_GSP1_LINE_NUM 0 15 DP_SEC_GSP2_LINE_NUM 16 31 mmDP0_DP_SEC_CNTL4 0 0x2155 2 0 2 DP_SEC_GSP3_LINE_NUM 0 15 DP_SEC_GSP4_LINE_NUM 16 31 mmDP0_DP_SEC_CNTL5 0 0x2156 2 0 2 DP_SEC_GSP5_LINE_NUM 0 15 DP_SEC_GSP6_LINE_NUM 16 31 mmDP0_DP_SEC_CNTL6 0 0x2157 1 0 2 DP_SEC_GSP7_LINE_NUM 0 15 mmDP0_DP_SEC_CNTL7 0 0x2158 8 0 2 DP_SEC_GSP0_SEND_ACTIVE 0 0 DP_SEC_GSP1_SEND_ACTIVE 4 4 DP_SEC_GSP2_SEND_ACTIVE 8 8 DP_SEC_GSP3_SEND_ACTIVE 12 12 DP_SEC_GSP4_SEND_ACTIVE 16 16 DP_SEC_GSP5_SEND_ACTIVE 20 20 DP_SEC_GSP6_SEND_ACTIVE 24 24 DP_SEC_GSP7_SEND_ACTIVE 28 28 mmDP0_DP_DB_CNTL 0 0x2159 5 0 2 DP_DB_PENDING 0 0 DP_DB_TAKEN 4 4 DP_DB_TAKEN_CLR 5 5 DP_DB_LOCK 8 8 DP_DB_DISABLE 12 12 mmDP0_DP_MSA_VBID_MISC 0 0x215a 6 0 2 DP_MSA_MISC1_STEREOSYNC_OVERRIDE 0 1 DP_MSA_MISC1_STEREOSYNC_OVERRIDE_EN 4 4 DP_VBID1_OVERRIDE 8 8 DP_VBID2_OVERRIDE 9 9 DP_VBID1_OVERRIDE_EN 12 12 DP_VBID2_OVERRIDE_EN 13 13 mmDIG1_DIG_FE_CNTL 0 0x2168 8 0 2 DIG_SOURCE_SELECT 0 2 DIG_STEREOSYNC_SELECT 4 6 DIG_STEREOSYNC_GATE_EN 8 8 DIG_START 10 10 DIG_DIGITAL_BYPASS_SELECT 12 14 DIG_SYMCLK_FE_ON 24 24 TMDS_PIXEL_ENCODING 28 28 TMDS_COLOR_FORMAT 30 31 mmDIG1_DIG_OUTPUT_CRC_CNTL 0 0x2169 3 0 2 DIG_OUTPUT_CRC_EN 0 0 DIG_OUTPUT_CRC_LINK_SEL 4 4 DIG_OUTPUT_CRC_DATA_SEL 8 9 mmDIG1_DIG_OUTPUT_CRC_RESULT 0 0x216a 1 0 2 DIG_OUTPUT_CRC_RESULT 0 29 mmDIG1_DIG_CLOCK_PATTERN 0 0x216b 1 0 2 DIG_CLOCK_PATTERN 0 9 mmDIG1_DIG_TEST_PATTERN 0 0x216c 6 0 2 DIG_TEST_PATTERN_OUT_EN 0 0 DIG_HALF_CLOCK_PATTERN_SEL 1 1 DIG_RANDOM_PATTERN_OUT_EN 4 4 DIG_RANDOM_PATTERN_RESET 5 5 DIG_TEST_PATTERN_EXTERNAL_RESET_EN 6 6 DIG_STATIC_TEST_PATTERN 16 25 mmDIG1_DIG_RANDOM_PATTERN_SEED 0 0x216d 2 0 2 DIG_RANDOM_PATTERN_SEED 0 23 DIG_RAN_PAT_DURING_DE_ONLY 24 24 mmDIG1_DIG_FIFO_STATUS 0 0x216e 11 0 2 DIG_FIFO_LEVEL_ERROR 0 0 DIG_FIFO_USE_OVERWRITE_LEVEL 1 1 DIG_FIFO_OVERWRITE_LEVEL 2 7 DIG_FIFO_ERROR_ACK 8 8 DIG_FIFO_CAL_AVERAGE_LEVEL 10 15 DIG_FIFO_MAXIMUM_LEVEL 16 20 DIG_FIFO_MINIMUM_LEVEL 22 25 DIG_FIFO_READ_CLOCK_SRC 26 26 DIG_FIFO_CALIBRATED 29 29 DIG_FIFO_FORCE_RECAL_AVERAGE 30 30 DIG_FIFO_FORCE_RECOMP_MINMAX 31 31 mmDIG1_HDMI_CONTROL 0 0x2171 9 0 2 HDMI_KEEPOUT_MODE 0 0 HDMI_DATA_SCRAMBLE_EN 1 1 HDMI_CLOCK_CHANNEL_RATE 2 2 HDMI_NO_EXTRA_NULL_PACKET_FILLED 3 3 HDMI_PACKET_GEN_VERSION 4 4 HDMI_ERROR_ACK 8 8 HDMI_ERROR_MASK 9 9 HDMI_DEEP_COLOR_ENABLE 24 24 HDMI_DEEP_COLOR_DEPTH 28 29 mmDIG1_HDMI_STATUS 0 0x2172 4 0 2 HDMI_ACTIVE_AVMUTE 0 0 HDMI_AUDIO_PACKET_ERROR 16 16 HDMI_VBI_PACKET_ERROR 20 20 HDMI_ERROR_INT 27 27 mmDIG1_HDMI_AUDIO_PACKET_CONTROL 0 0x2173 2 0 2 HDMI_AUDIO_DELAY_EN 4 5 HDMI_AUDIO_PACKETS_PER_LINE 16 20 mmDIG1_HDMI_ACR_PACKET_CONTROL 0 0x2174 7 0 2 HDMI_ACR_SEND 0 0 HDMI_ACR_CONT 1 1 HDMI_ACR_SELECT 4 5 HDMI_ACR_SOURCE 8 8 HDMI_ACR_AUTO_SEND 12 12 HDMI_ACR_N_MULTIPLE 16 18 HDMI_ACR_AUDIO_PRIORITY 31 31 mmDIG1_HDMI_VBI_PACKET_CONTROL 0 0x2175 6 0 2 HDMI_NULL_SEND 0 0 HDMI_GC_SEND 4 4 HDMI_GC_CONT 5 5 HDMI_ISRC_SEND 8 8 HDMI_ISRC_CONT 9 9 HDMI_ISRC_LINE 16 21 mmDIG1_HDMI_INFOFRAME_CONTROL0 0 0x2176 4 0 2 HDMI_AUDIO_INFO_SEND 4 4 HDMI_AUDIO_INFO_CONT 5 5 HDMI_MPEG_INFO_SEND 8 8 HDMI_MPEG_INFO_CONT 9 9 mmDIG1_HDMI_INFOFRAME_CONTROL1 0 0x2177 2 0 2 HDMI_AUDIO_INFO_LINE 8 13 HDMI_MPEG_INFO_LINE 16 21 mmDIG1_HDMI_GENERIC_PACKET_CONTROL0 0 0x2178 6 0 2 HDMI_GENERIC0_SEND 0 0 HDMI_GENERIC0_CONT 1 1 HDMI_GENERIC1_SEND 4 4 HDMI_GENERIC1_CONT 5 5 HDMI_GENERIC0_LINE 16 21 HDMI_GENERIC1_LINE 24 29 mmDIG1_AFMT_INTERRUPT_STATUS 0 0x2179 0 0 2 mmDIG1_HDMI_GC 0 0x217b 5 0 2 HDMI_GC_AVMUTE 0 0 HDMI_GC_AVMUTE_CONT 2 2 HDMI_DEFAULT_PHASE 4 4 HDMI_PACKING_PHASE 8 11 HDMI_PACKING_PHASE_OVERRIDE 12 12 mmDIG1_AFMT_AUDIO_PACKET_CONTROL2 0 0x217c 6 0 2 AFMT_AUDIO_LAYOUT_OVRD 0 0 AFMT_AUDIO_LAYOUT_SELECT 1 1 AFMT_AUDIO_CHANNEL_ENABLE 8 15 AFMT_DP_AUDIO_STREAM_ID 16 23 AFMT_HBR_ENABLE_OVRD 24 24 AFMT_60958_OSF_OVRD 28 28 mmDIG1_AFMT_ISRC1_0 0 0x217d 3 0 2 AFMT_ISRC_STATUS 0 2 AFMT_ISRC_CONTINUE 6 6 AFMT_ISRC_VALID 7 7 mmDIG1_AFMT_ISRC1_1 0 0x217e 4 0 2 AFMT_UPC_EAN_ISRC0 0 7 AFMT_UPC_EAN_ISRC1 8 15 AFMT_UPC_EAN_ISRC2 16 23 AFMT_UPC_EAN_ISRC3 24 31 mmDIG1_AFMT_ISRC1_2 0 0x217f 4 0 2 AFMT_UPC_EAN_ISRC4 0 7 AFMT_UPC_EAN_ISRC5 8 15 AFMT_UPC_EAN_ISRC6 16 23 AFMT_UPC_EAN_ISRC7 24 31 mmDIG1_AFMT_ISRC1_3 0 0x2180 4 0 2 AFMT_UPC_EAN_ISRC8 0 7 AFMT_UPC_EAN_ISRC9 8 15 AFMT_UPC_EAN_ISRC10 16 23 AFMT_UPC_EAN_ISRC11 24 31 mmDIG1_AFMT_ISRC1_4 0 0x2181 4 0 2 AFMT_UPC_EAN_ISRC12 0 7 AFMT_UPC_EAN_ISRC13 8 15 AFMT_UPC_EAN_ISRC14 16 23 AFMT_UPC_EAN_ISRC15 24 31 mmDIG1_AFMT_ISRC2_0 0 0x2182 4 0 2 AFMT_UPC_EAN_ISRC16 0 7 AFMT_UPC_EAN_ISRC17 8 15 AFMT_UPC_EAN_ISRC18 16 23 AFMT_UPC_EAN_ISRC19 24 31 mmDIG1_AFMT_ISRC2_1 0 0x2183 4 0 2 AFMT_UPC_EAN_ISRC20 0 7 AFMT_UPC_EAN_ISRC21 8 15 AFMT_UPC_EAN_ISRC22 16 23 AFMT_UPC_EAN_ISRC23 24 31 mmDIG1_AFMT_ISRC2_2 0 0x2184 4 0 2 AFMT_UPC_EAN_ISRC24 0 7 AFMT_UPC_EAN_ISRC25 8 15 AFMT_UPC_EAN_ISRC26 16 23 AFMT_UPC_EAN_ISRC27 24 31 mmDIG1_AFMT_ISRC2_3 0 0x2185 4 0 2 AFMT_UPC_EAN_ISRC28 0 7 AFMT_UPC_EAN_ISRC29 8 15 AFMT_UPC_EAN_ISRC30 16 23 AFMT_UPC_EAN_ISRC31 24 31 mmDIG1_HDMI_GENERIC_PACKET_CONTROL2 0 0x2186 6 0 2 HDMI_GENERIC4_SEND 0 0 HDMI_GENERIC4_CONT 1 1 HDMI_GENERIC5_SEND 4 4 HDMI_GENERIC5_CONT 5 5 HDMI_GENERIC4_LINE 16 21 HDMI_GENERIC5_LINE 24 29 mmDIG1_HDMI_GENERIC_PACKET_CONTROL3 0 0x2187 6 0 2 HDMI_GENERIC6_SEND 0 0 HDMI_GENERIC6_CONT 1 1 HDMI_GENERIC7_SEND 4 4 HDMI_GENERIC7_CONT 5 5 HDMI_GENERIC6_LINE 16 21 HDMI_GENERIC7_LINE 24 29 mmDIG1_HDMI_DB_CONTROL 0 0x2188 5 0 2 HDMI_DB_PENDING 0 0 HDMI_DB_TAKEN 4 4 HDMI_DB_TAKEN_CLR 5 5 HDMI_DB_LOCK 8 8 HDMI_DB_DISABLE 12 12 mmDIG1_AFMT_MPEG_INFO0 0 0x218a 4 0 2 AFMT_MPEG_INFO_CHECKSUM 0 7 AFMT_MPEG_INFO_MB0 8 15 AFMT_MPEG_INFO_MB1 16 23 AFMT_MPEG_INFO_MB2 24 31 mmDIG1_AFMT_MPEG_INFO1 0 0x218b 3 0 2 AFMT_MPEG_INFO_MB3 0 7 AFMT_MPEG_INFO_MF 8 9 AFMT_MPEG_INFO_FR 12 12 mmDIG1_AFMT_GENERIC_HDR 0 0x218c 4 0 2 AFMT_GENERIC_HB0 0 7 AFMT_GENERIC_HB1 8 15 AFMT_GENERIC_HB2 16 23 AFMT_GENERIC_HB3 24 31 mmDIG1_AFMT_GENERIC_0 0 0x218d 4 0 2 AFMT_GENERIC_BYTE0 0 7 AFMT_GENERIC_BYTE1 8 15 AFMT_GENERIC_BYTE2 16 23 AFMT_GENERIC_BYTE3 24 31 mmDIG1_AFMT_GENERIC_1 0 0x218e 4 0 2 AFMT_GENERIC_BYTE4 0 7 AFMT_GENERIC_BYTE5 8 15 AFMT_GENERIC_BYTE6 16 23 AFMT_GENERIC_BYTE7 24 31 mmDIG1_AFMT_GENERIC_2 0 0x218f 4 0 2 AFMT_GENERIC_BYTE8 0 7 AFMT_GENERIC_BYTE9 8 15 AFMT_GENERIC_BYTE10 16 23 AFMT_GENERIC_BYTE11 24 31 mmDIG1_AFMT_GENERIC_3 0 0x2190 4 0 2 AFMT_GENERIC_BYTE12 0 7 AFMT_GENERIC_BYTE13 8 15 AFMT_GENERIC_BYTE14 16 23 AFMT_GENERIC_BYTE15 24 31 mmDIG1_AFMT_GENERIC_4 0 0x2191 4 0 2 AFMT_GENERIC_BYTE16 0 7 AFMT_GENERIC_BYTE17 8 15 AFMT_GENERIC_BYTE18 16 23 AFMT_GENERIC_BYTE19 24 31 mmDIG1_AFMT_GENERIC_5 0 0x2192 4 0 2 AFMT_GENERIC_BYTE20 0 7 AFMT_GENERIC_BYTE21 8 15 AFMT_GENERIC_BYTE22 16 23 AFMT_GENERIC_BYTE23 24 31 mmDIG1_AFMT_GENERIC_6 0 0x2193 4 0 2 AFMT_GENERIC_BYTE24 0 7 AFMT_GENERIC_BYTE25 8 15 AFMT_GENERIC_BYTE26 16 23 AFMT_GENERIC_BYTE27 24 31 mmDIG1_AFMT_GENERIC_7 0 0x2194 4 0 2 AFMT_GENERIC_BYTE28 0 7 AFMT_GENERIC_BYTE29 8 15 AFMT_GENERIC_BYTE30 16 23 AFMT_GENERIC_BYTE31 24 31 mmDIG1_HDMI_GENERIC_PACKET_CONTROL1 0 0x2195 6 0 2 HDMI_GENERIC2_SEND 0 0 HDMI_GENERIC2_CONT 1 1 HDMI_GENERIC3_SEND 4 4 HDMI_GENERIC3_CONT 5 5 HDMI_GENERIC2_LINE 16 21 HDMI_GENERIC3_LINE 24 29 mmDIG1_HDMI_ACR_32_0 0 0x2196 1 0 2 HDMI_ACR_CTS_32 12 31 mmDIG1_HDMI_ACR_32_1 0 0x2197 1 0 2 HDMI_ACR_N_32 0 19 mmDIG1_HDMI_ACR_44_0 0 0x2198 1 0 2 HDMI_ACR_CTS_44 12 31 mmDIG1_HDMI_ACR_44_1 0 0x2199 1 0 2 HDMI_ACR_N_44 0 19 mmDIG1_HDMI_ACR_48_0 0 0x219a 1 0 2 HDMI_ACR_CTS_48 12 31 mmDIG1_HDMI_ACR_48_1 0 0x219b 1 0 2 HDMI_ACR_N_48 0 19 mmDIG1_HDMI_ACR_STATUS_0 0 0x219c 1 0 2 HDMI_ACR_CTS 12 31 mmDIG1_HDMI_ACR_STATUS_1 0 0x219d 1 0 2 HDMI_ACR_N 0 19 mmDIG1_AFMT_AUDIO_INFO0 0 0x219e 5 0 2 AFMT_AUDIO_INFO_CHECKSUM 0 7 AFMT_AUDIO_INFO_CC 8 10 AFMT_AUDIO_INFO_CT 11 14 AFMT_AUDIO_INFO_CHECKSUM_OFFSET 16 23 AFMT_AUDIO_INFO_CXT 24 28 mmDIG1_AFMT_AUDIO_INFO1 0 0x219f 4 0 2 AFMT_AUDIO_INFO_CA 0 7 AFMT_AUDIO_INFO_LSV 11 14 AFMT_AUDIO_INFO_DM_INH 15 15 AFMT_AUDIO_INFO_LFEPBL 16 17 mmDIG1_AFMT_60958_0 0 0x21a0 10 0 2 AFMT_60958_CS_A 0 0 AFMT_60958_CS_B 1 1 AFMT_60958_CS_C 2 2 AFMT_60958_CS_D 3 5 AFMT_60958_CS_MODE 6 7 AFMT_60958_CS_CATEGORY_CODE 8 15 AFMT_60958_CS_SOURCE_NUMBER 16 19 AFMT_60958_CS_CHANNEL_NUMBER_L 20 23 AFMT_60958_CS_SAMPLING_FREQUENCY 24 27 AFMT_60958_CS_CLOCK_ACCURACY 28 29 mmDIG1_AFMT_60958_1 0 0x21a1 5 0 2 AFMT_60958_CS_WORD_LENGTH 0 3 AFMT_60958_CS_ORIGINAL_SAMPLING_FREQUENCY 4 7 AFMT_60958_VALID_L 16 16 AFMT_60958_VALID_R 18 18 AFMT_60958_CS_CHANNEL_NUMBER_R 20 23 mmDIG1_AFMT_AUDIO_CRC_CONTROL 0 0x21a2 5 0 2 AFMT_AUDIO_CRC_EN 0 0 AFMT_AUDIO_CRC_CONT 4 4 AFMT_AUDIO_CRC_SOURCE 8 8 AFMT_AUDIO_CRC_CH_SEL 12 15 AFMT_AUDIO_CRC_COUNT 16 31 mmDIG1_AFMT_RAMP_CONTROL0 0 0x21a3 2 0 2 AFMT_RAMP_MAX_COUNT 0 23 AFMT_RAMP_DATA_SIGN 31 31 mmDIG1_AFMT_RAMP_CONTROL1 0 0x21a4 2 0 2 AFMT_RAMP_MIN_COUNT 0 23 AFMT_AUDIO_TEST_CH_DISABLE 24 31 mmDIG1_AFMT_RAMP_CONTROL2 0 0x21a5 1 0 2 AFMT_RAMP_INC_COUNT 0 23 mmDIG1_AFMT_RAMP_CONTROL3 0 0x21a6 1 0 2 AFMT_RAMP_DEC_COUNT 0 23 mmDIG1_AFMT_60958_2 0 0x21a7 6 0 2 AFMT_60958_CS_CHANNEL_NUMBER_2 0 3 AFMT_60958_CS_CHANNEL_NUMBER_3 4 7 AFMT_60958_CS_CHANNEL_NUMBER_4 8 11 AFMT_60958_CS_CHANNEL_NUMBER_5 12 15 AFMT_60958_CS_CHANNEL_NUMBER_6 16 19 AFMT_60958_CS_CHANNEL_NUMBER_7 20 23 mmDIG1_AFMT_AUDIO_CRC_RESULT 0 0x21a8 2 0 2 AFMT_AUDIO_CRC_DONE 0 0 AFMT_AUDIO_CRC 8 31 mmDIG1_AFMT_STATUS 0 0x21a9 4 0 2 AFMT_AUDIO_ENABLE 4 4 AFMT_AZ_HBR_ENABLE 8 8 AFMT_AUDIO_FIFO_OVERFLOW 24 24 AFMT_AZ_AUDIO_ENABLE_CHG 30 30 mmDIG1_AFMT_AUDIO_PACKET_CONTROL 0 0x21aa 8 0 2 AFMT_AUDIO_SAMPLE_SEND 0 0 AFMT_RESET_FIFO_WHEN_AUDIO_DIS 11 11 AFMT_AUDIO_TEST_EN 12 12 AFMT_AUDIO_TEST_MODE 14 14 AFMT_AUDIO_FIFO_OVERFLOW_ACK 23 23 AFMT_AUDIO_CHANNEL_SWAP 24 24 AFMT_60958_CS_UPDATE 26 26 AFMT_AZ_AUDIO_ENABLE_CHG_ACK 30 30 mmDIG1_AFMT_VBI_PACKET_CONTROL 0 0x21ab 4 0 2 AFMT_GENERIC_LOCK_STATUS 8 8 AFMT_GENERIC_CONFLICT 16 16 AFMT_GENERIC_CONFLICT_CLR 17 17 AFMT_GENERIC_INDEX 28 31 mmDIG1_AFMT_INFOFRAME_CONTROL0 0 0x21ac 3 0 2 AFMT_AUDIO_INFO_SOURCE 6 6 AFMT_AUDIO_INFO_UPDATE 7 7 AFMT_MPEG_INFO_UPDATE 10 10 mmDIG1_AFMT_AUDIO_SRC_CONTROL 0 0x21ad 1 0 2 AFMT_AUDIO_SRC_SELECT 0 2 mmDIG1_DIG_BE_CNTL 0 0x21af 5 0 2 DIG_DUAL_LINK_ENABLE 0 0 DIG_SWAP 1 1 DIG_FE_SOURCE_SELECT 8 14 DIG_MODE 16 18 DIG_HPD_SELECT 28 30 mmDIG1_DIG_BE_EN_CNTL 0 0x21b0 2 0 2 DIG_ENABLE 0 0 DIG_SYMCLK_BE_ON 8 8 mmDIG1_TMDS_CNTL 0 0x21d3 1 0 2 TMDS_SYNC_PHASE 0 0 mmDIG1_TMDS_CONTROL_CHAR 0 0x21d4 4 0 2 TMDS_CONTROL_CHAR0_OUT_EN 0 0 TMDS_CONTROL_CHAR1_OUT_EN 1 1 TMDS_CONTROL_CHAR2_OUT_EN 2 2 TMDS_CONTROL_CHAR3_OUT_EN 3 3 mmDIG1_TMDS_CONTROL0_FEEDBACK 0 0x21d5 2 0 2 TMDS_CONTROL0_FEEDBACK_SELECT 0 1 TMDS_CONTROL0_FEEDBACK_DELAY 8 9 mmDIG1_TMDS_STEREOSYNC_CTL_SEL 0 0x21d6 1 0 2 TMDS_STEREOSYNC_CTL_SEL 0 1 mmDIG1_TMDS_SYNC_CHAR_PATTERN_0_1 0 0x21d7 2 0 2 TMDS_SYNC_CHAR_PATTERN0 0 9 TMDS_SYNC_CHAR_PATTERN1 16 25 mmDIG1_TMDS_SYNC_CHAR_PATTERN_2_3 0 0x21d8 2 0 2 TMDS_SYNC_CHAR_PATTERN2 0 9 TMDS_SYNC_CHAR_PATTERN3 16 25 mmDIG1_TMDS_CTL_BITS 0 0x21da 4 0 2 TMDS_CTL0 0 0 TMDS_CTL1 8 8 TMDS_CTL2 16 16 TMDS_CTL3 24 24 mmDIG1_TMDS_DCBALANCER_CONTROL 0 0x21db 4 0 2 TMDS_DCBALANCER_EN 0 0 TMDS_DCBALANCER_TEST_EN 8 8 TMDS_DCBALANCER_TEST_IN 16 19 TMDS_DCBALANCER_FORCE 24 24 mmDIG1_TMDS_CTL0_1_GEN_CNTL 0 0x21dd 15 0 2 TMDS_CTL0_DATA_SEL 0 3 TMDS_CTL0_DATA_DELAY 4 6 TMDS_CTL0_DATA_INVERT 7 7 TMDS_CTL0_DATA_MODULATION 8 9 TMDS_CTL0_USE_FEEDBACK_PATH 10 10 TMDS_CTL0_FB_SYNC_CONT 11 11 TMDS_CTL0_PATTERN_OUT_EN 12 12 TMDS_CTL1_DATA_SEL 16 19 TMDS_CTL1_DATA_DELAY 20 22 TMDS_CTL1_DATA_INVERT 23 23 TMDS_CTL1_DATA_MODULATION 24 25 TMDS_CTL1_USE_FEEDBACK_PATH 26 26 TMDS_CTL1_FB_SYNC_CONT 27 27 TMDS_CTL1_PATTERN_OUT_EN 28 28 TMDS_2BIT_COUNTER_EN 31 31 mmDIG1_TMDS_CTL2_3_GEN_CNTL 0 0x21de 14 0 2 TMDS_CTL2_DATA_SEL 0 3 TMDS_CTL2_DATA_DELAY 4 6 TMDS_CTL2_DATA_INVERT 7 7 TMDS_CTL2_DATA_MODULATION 8 9 TMDS_CTL2_USE_FEEDBACK_PATH 10 10 TMDS_CTL2_FB_SYNC_CONT 11 11 TMDS_CTL2_PATTERN_OUT_EN 12 12 TMDS_CTL3_DATA_SEL 16 19 TMDS_CTL3_DATA_DELAY 20 22 TMDS_CTL3_DATA_INVERT 23 23 TMDS_CTL3_DATA_MODULATION 24 25 TMDS_CTL3_USE_FEEDBACK_PATH 26 26 TMDS_CTL3_FB_SYNC_CONT 27 27 TMDS_CTL3_PATTERN_OUT_EN 28 28 mmDIG1_DIG_VERSION 0 0x21e0 1 0 2 DIG_TYPE 0 0 mmDIG1_DIG_LANE_ENABLE 0 0x21e1 5 0 2 DIG_LANE0EN 0 0 DIG_LANE1EN 1 1 DIG_LANE2EN 2 2 DIG_LANE3EN 3 3 DIG_CLK_EN 8 8 mmDIG1_AFMT_CNTL 0 0x21e6 2 0 2 AFMT_AUDIO_CLOCK_EN 0 0 AFMT_AUDIO_CLOCK_ON 8 8 mmDIG1_AFMT_VBI_PACKET_CONTROL1 0 0x21e7 32 0 2 AFMT_GENERIC0_FRAME_UPDATE 0 0 AFMT_GENERIC0_FRAME_UPDATE_PENDING 1 1 AFMT_GENERIC0_IMMEDIATE_UPDATE 2 2 AFMT_GENERIC0_IMMEDIATE_UPDATE_PENDING 3 3 AFMT_GENERIC1_FRAME_UPDATE 4 4 AFMT_GENERIC1_FRAME_UPDATE_PENDING 5 5 AFMT_GENERIC1_IMMEDIATE_UPDATE 6 6 AFMT_GENERIC1_IMMEDIATE_UPDATE_PENDING 7 7 AFMT_GENERIC2_FRAME_UPDATE 8 8 AFMT_GENERIC2_FRAME_UPDATE_PENDING 9 9 AFMT_GENERIC2_IMMEDIATE_UPDATE 10 10 AFMT_GENERIC2_IMMEDIATE_UPDATE_PENDING 11 11 AFMT_GENERIC3_FRAME_UPDATE 12 12 AFMT_GENERIC3_FRAME_UPDATE_PENDING 13 13 AFMT_GENERIC3_IMMEDIATE_UPDATE 14 14 AFMT_GENERIC3_IMMEDIATE_UPDATE_PENDING 15 15 AFMT_GENERIC4_FRAME_UPDATE 16 16 AFMT_GENERIC4_FRAME_UPDATE_PENDING 17 17 AFMT_GENERIC4_IMMEDIATE_UPDATE 18 18 AFMT_GENERIC4_IMMEDIATE_UPDATE_PENDING 19 19 AFMT_GENERIC5_FRAME_UPDATE 20 20 AFMT_GENERIC5_FRAME_UPDATE_PENDING 21 21 AFMT_GENERIC5_IMMEDIATE_UPDATE 22 22 AFMT_GENERIC5_IMMEDIATE_UPDATE_PENDING 23 23 AFMT_GENERIC6_FRAME_UPDATE 24 24 AFMT_GENERIC6_FRAME_UPDATE_PENDING 25 25 AFMT_GENERIC6_IMMEDIATE_UPDATE 26 26 AFMT_GENERIC6_IMMEDIATE_UPDATE_PENDING 27 27 AFMT_GENERIC7_FRAME_UPDATE 28 28 AFMT_GENERIC7_FRAME_UPDATE_PENDING 29 29 AFMT_GENERIC7_IMMEDIATE_UPDATE 30 30 AFMT_GENERIC7_IMMEDIATE_UPDATE_PENDING 31 31 mmDP1_DP_LINK_CNTL 0 0x2208 3 0 2 DP_LINK_TRAINING_COMPLETE 4 4 DP_LINK_STATUS 8 8 DP_EMBEDDED_PANEL_MODE 17 17 mmDP1_DP_PIXEL_FORMAT 0 0x2209 3 0 2 DP_PIXEL_ENCODING 0 2 DP_COMPONENT_DEPTH 24 26 DP_PIXEL_COMBINE 28 29 mmDP1_DP_MSA_COLORIMETRY 0 0x220a 1 0 2 DP_MSA_MISC0 24 31 mmDP1_DP_CONFIG 0 0x220b 1 0 2 DP_UDI_LANES 0 1 mmDP1_DP_VID_STREAM_CNTL 0 0x220c 4 0 2 DP_VID_STREAM_ENABLE 0 0 DP_VID_STREAM_DIS_DEFER 8 9 DP_VID_STREAM_STATUS 16 16 DP_VID_STREAM_CHANGE_KEEPOUT 20 20 mmDP1_DP_STEER_FIFO 0 0x220d 7 0 2 DP_STEER_FIFO_RESET 0 0 DP_STEER_OVERFLOW_FLAG 4 4 DP_STEER_OVERFLOW_INT 5 5 DP_STEER_OVERFLOW_ACK 6 6 DP_STEER_OVERFLOW_MASK 7 7 DP_TU_OVERFLOW_FLAG 8 8 DP_TU_OVERFLOW_ACK 12 12 mmDP1_DP_MSA_MISC 0 0x220e 4 0 2 DP_MSA_MISC1 0 7 DP_MSA_MISC2 8 15 DP_MSA_MISC3 16 23 DP_MSA_MISC4 24 31 mmDP1_DP_VID_TIMING 0 0x2210 5 0 2 DP_VID_M_N_DOUBLE_BUFFER_MODE 4 4 DP_VID_M_N_GEN_EN 8 8 DP_VID_N_MUL 10 11 DP_VID_M_DIV 12 13 DP_VID_N_DIV 24 31 mmDP1_DP_VID_N 0 0x2211 1 0 2 DP_VID_N 0 23 mmDP1_DP_VID_M 0 0x2212 1 0 2 DP_VID_M 0 23 mmDP1_DP_LINK_FRAMING_CNTL 0 0x2213 3 0 2 DP_IDLE_BS_INTERVAL 0 17 DP_VBID_DISABLE 24 24 DP_VID_ENHANCED_FRAME_MODE 28 28 mmDP1_DP_HBR2_EYE_PATTERN 0 0x2214 1 0 2 DP_HBR2_EYE_PATTERN_ENABLE 0 0 mmDP1_DP_VID_MSA_VBID 0 0x2215 2 0 2 DP_VID_MSA_LOCATION 0 11 DP_VID_VBID_FIELD_POL 24 24 mmDP1_DP_VID_INTERRUPT_CNTL 0 0x2216 3 0 2 DP_VID_STREAM_DISABLE_INT 0 0 DP_VID_STREAM_DISABLE_ACK 1 1 DP_VID_STREAM_DISABLE_MASK 2 2 mmDP1_DP_DPHY_CNTL 0 0x2217 6 0 2 DPHY_ATEST_SEL_LANE0 0 0 DPHY_ATEST_SEL_LANE1 1 1 DPHY_ATEST_SEL_LANE2 2 2 DPHY_ATEST_SEL_LANE3 3 3 DPHY_BYPASS 16 16 DPHY_SKEW_BYPASS 24 24 mmDP1_DP_DPHY_TRAINING_PATTERN_SEL 0 0x2218 1 0 2 DPHY_TRAINING_PATTERN_SEL 0 1 mmDP1_DP_DPHY_SYM0 0 0x2219 3 0 2 DPHY_SYM1 0 9 DPHY_SYM2 10 19 DPHY_SYM3 20 29 mmDP1_DP_DPHY_SYM1 0 0x221a 3 0 2 DPHY_SYM4 0 9 DPHY_SYM5 10 19 DPHY_SYM6 20 29 mmDP1_DP_DPHY_SYM2 0 0x221b 2 0 2 DPHY_SYM7 0 9 DPHY_SYM8 10 19 mmDP1_DP_DPHY_8B10B_CNTL 0 0x221c 3 0 2 DPHY_8B10B_RESET 8 8 DPHY_8B10B_EXT_DISP 16 16 DPHY_8B10B_CUR_DISP 24 24 mmDP1_DP_DPHY_PRBS_CNTL 0 0x221d 3 0 2 DPHY_PRBS_EN 0 0 DPHY_PRBS_SEL 4 5 DPHY_PRBS_SEED 8 30 mmDP1_DP_DPHY_SCRAM_CNTL 0 0x221e 4 0 2 DPHY_SCRAMBLER_DIS 0 0 DPHY_SCRAMBLER_ADVANCE 4 4 DPHY_SCRAMBLER_BS_COUNT 8 17 DPHY_SCRAMBLER_KCODE 24 24 mmDP1_DP_DPHY_CRC_EN 0 0x221f 3 0 2 DPHY_CRC_EN 0 0 DPHY_CRC_CONT_EN 4 4 DPHY_CRC_RESULT_VALID 8 8 mmDP1_DP_DPHY_CRC_CNTL 0 0x2220 3 0 2 DPHY_CRC_FIELD 0 0 DPHY_CRC_SEL 4 5 DPHY_CRC_MASK 16 23 mmDP1_DP_DPHY_CRC_RESULT 0 0x2221 4 0 2 DPHY_CRC_RESULT 0 7 DPHY_CRC_RESULT1 8 15 DPHY_CRC_RESULT2 16 23 DPHY_CRC_RESULT3 24 31 mmDP1_DP_DPHY_CRC_MST_CNTL 0 0x2222 2 0 2 DPHY_CRC_MST_FIRST_SLOT 0 5 DPHY_CRC_MST_LAST_SLOT 8 13 mmDP1_DP_DPHY_CRC_MST_STATUS 0 0x2223 3 0 2 DPHY_CRC_MST_PHASE_LOCK 0 0 DPHY_CRC_MST_PHASE_ERROR 8 8 DPHY_CRC_MST_PHASE_ERROR_ACK 16 16 mmDP1_DP_DPHY_FAST_TRAINING 0 0x2224 5 0 2 DPHY_RX_FAST_TRAINING_CAPABLE 0 0 DPHY_SW_FAST_TRAINING_START 1 1 DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN 2 2 DPHY_FAST_TRAINING_TP1_TIME 8 19 DPHY_FAST_TRAINING_TP2_TIME 20 31 mmDP1_DP_DPHY_FAST_TRAINING_STATUS 0 0x2225 4 0 2 DPHY_FAST_TRAINING_STATE 0 2 DPHY_FAST_TRAINING_COMPLETE_OCCURRED 4 4 DPHY_FAST_TRAINING_COMPLETE_MASK 8 8 DPHY_FAST_TRAINING_COMPLETE_ACK 12 12 mmDP1_DP_SEC_CNTL 0 0x222b 14 0 2 DP_SEC_STREAM_ENABLE 0 0 DP_SEC_ASP_ENABLE 4 4 DP_SEC_ATP_ENABLE 8 8 DP_SEC_AIP_ENABLE 12 12 DP_SEC_ACM_ENABLE 16 16 DP_SEC_GSP0_ENABLE 20 20 DP_SEC_GSP1_ENABLE 21 21 DP_SEC_GSP2_ENABLE 22 22 DP_SEC_GSP3_ENABLE 23 23 DP_SEC_GSP4_ENABLE 24 24 DP_SEC_GSP5_ENABLE 25 25 DP_SEC_GSP6_ENABLE 26 26 DP_SEC_GSP7_ENABLE 27 27 DP_SEC_MPG_ENABLE 28 28 mmDP1_DP_SEC_CNTL1 0 0x222c 7 0 2 DP_SEC_ISRC_ENABLE 0 0 DP_SEC_GSP0_PRIORITY 4 4 DP_SEC_GSP0_SEND 5 5 DP_SEC_GSP0_SEND_PENDING 6 6 DP_SEC_GSP0_SEND_DEADLINE_MISSED 7 7 DP_SEC_GSP0_SEND_ANY_LINE 8 8 DP_SEC_GSP0_LINE_NUM 16 31 mmDP1_DP_SEC_FRAMING1 0 0x222d 2 0 2 DP_SEC_FRAME_START_LOCATION 0 11 DP_SEC_VBLANK_TRANSMIT_WIDTH 16 31 mmDP1_DP_SEC_FRAMING2 0 0x222e 2 0 2 DP_SEC_START_POSITION 0 15 DP_SEC_HBLANK_TRANSMIT_WIDTH 16 31 mmDP1_DP_SEC_FRAMING3 0 0x222f 2 0 2 DP_SEC_IDLE_FRAME_SIZE 0 13 DP_SEC_IDLE_TRANSMIT_WIDTH 16 31 mmDP1_DP_SEC_FRAMING4 0 0x2230 4 0 2 DP_SEC_COLLISION_STATUS 20 20 DP_SEC_COLLISION_ACK 24 24 DP_SEC_AUDIO_MUTE 28 28 DP_SEC_AUDIO_MUTE_STATUS 29 29 mmDP1_DP_SEC_AUD_N 0 0x2231 1 0 2 DP_SEC_AUD_N 0 23 mmDP1_DP_SEC_AUD_N_READBACK 0 0x2232 1 0 2 DP_SEC_AUD_N_READBACK 0 23 mmDP1_DP_SEC_AUD_M 0 0x2233 1 0 2 DP_SEC_AUD_M 0 23 mmDP1_DP_SEC_AUD_M_READBACK 0 0x2234 1 0 2 DP_SEC_AUD_M_READBACK 0 23 mmDP1_DP_SEC_TIMESTAMP 0 0x2235 1 0 2 DP_SEC_TIMESTAMP_MODE 0 0 mmDP1_DP_SEC_PACKET_CNTL 0 0x2236 4 0 2 DP_SEC_ASP_CODING_TYPE 1 3 DP_SEC_ASP_PRIORITY 4 4 DP_SEC_VERSION 8 13 DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE 16 16 mmDP1_DP_MSE_RATE_CNTL 0 0x2237 2 0 2 DP_MSE_RATE_Y 0 25 DP_MSE_RATE_X 26 31 mmDP1_DP_MSE_RATE_UPDATE 0 0x2239 1 0 2 DP_MSE_RATE_UPDATE_PENDING 0 0 mmDP1_DP_MSE_SAT0 0 0x223a 4 0 2 DP_MSE_SAT_SRC0 0 2 DP_MSE_SAT_SLOT_COUNT0 8 13 DP_MSE_SAT_SRC1 16 18 DP_MSE_SAT_SLOT_COUNT1 24 29 mmDP1_DP_MSE_SAT1 0 0x223b 4 0 2 DP_MSE_SAT_SRC2 0 2 DP_MSE_SAT_SLOT_COUNT2 8 13 DP_MSE_SAT_SRC3 16 18 DP_MSE_SAT_SLOT_COUNT3 24 29 mmDP1_DP_MSE_SAT2 0 0x223c 4 0 2 DP_MSE_SAT_SRC4 0 2 DP_MSE_SAT_SLOT_COUNT4 8 13 DP_MSE_SAT_SRC5 16 18 DP_MSE_SAT_SLOT_COUNT5 24 29 mmDP1_DP_MSE_SAT_UPDATE 0 0x223d 2 0 2 DP_MSE_SAT_UPDATE 0 1 DP_MSE_16_MTP_KEEPOUT 8 8 mmDP1_DP_MSE_LINK_TIMING 0 0x223e 2 0 2 DP_MSE_LINK_FRAME 0 9 DP_MSE_LINK_LINE 16 17 mmDP1_DP_MSE_MISC_CNTL 0 0x223f 3 0 2 DP_MSE_BLANK_CODE 0 0 DP_MSE_TIMESTAMP_MODE 4 4 DP_MSE_ZERO_ENCODER 8 8 mmDP1_DP_DPHY_BS_SR_SWAP_CNTL 0 0x2244 3 0 2 DPHY_LOAD_BS_COUNT 0 9 DPHY_BS_SR_SWAP_DONE 15 15 DPHY_LOAD_BS_COUNT_START 16 16 mmDP1_DP_DPHY_HBR2_PATTERN_CONTROL 0 0x2245 1 0 2 DP_DPHY_HBR2_PATTERN_CONTROL 0 2 mmDP1_DP_MSE_SAT0_STATUS 0 0x2247 4 0 2 DP_MSE_SAT_SRC0_STATUS 0 2 DP_MSE_SAT_SLOT_COUNT0_STATUS 8 13 DP_MSE_SAT_SRC1_STATUS 16 18 DP_MSE_SAT_SLOT_COUNT1_STATUS 24 29 mmDP1_DP_MSE_SAT1_STATUS 0 0x2248 4 0 2 DP_MSE_SAT_SRC2_STATUS 0 2 DP_MSE_SAT_SLOT_COUNT2_STATUS 8 13 DP_MSE_SAT_SRC3_STATUS 16 18 DP_MSE_SAT_SLOT_COUNT3_STATUS 24 29 mmDP1_DP_MSE_SAT2_STATUS 0 0x2249 4 0 2 DP_MSE_SAT_SRC4_STATUS 0 2 DP_MSE_SAT_SLOT_COUNT4_STATUS 8 13 DP_MSE_SAT_SRC5_STATUS 16 18 DP_MSE_SAT_SLOT_COUNT5_STATUS 24 29 mmDP1_DP_MSA_TIMING_PARAM1 0 0x224c 2 0 2 DP_MSA_VTOTAL 0 15 DP_MSA_HTOTAL 16 31 mmDP1_DP_MSA_TIMING_PARAM2 0 0x224d 2 0 2 DP_MSA_VSTART 0 15 DP_MSA_HSTART 16 31 mmDP1_DP_MSA_TIMING_PARAM3 0 0x224e 4 0 2 DP_MSA_VSYNCWIDTH 0 14 DP_MSA_VSYNCPOLARITY 15 15 DP_MSA_HSYNCWIDTH 16 30 DP_MSA_HSYNCPOLARITY 31 31 mmDP1_DP_MSA_TIMING_PARAM4 0 0x224f 2 0 2 DP_MSA_VHEIGHT 0 15 DP_MSA_HWIDTH 16 31 mmDP1_DP_MSO_CNTL 0 0x2250 8 0 2 DP_MSO_NUM_OF_SSTLINK 0 1 DP_MSO_SEC_STREAM_ENABLE 4 7 DP_MSO_SEC_ASP_ENABLE 8 11 DP_MSO_SEC_ATP_ENABLE 12 15 DP_MSO_SEC_AIP_ENABLE 16 19 DP_MSO_SEC_ACM_ENABLE 20 23 DP_MSO_SEC_GSP0_ENABLE 24 27 DP_MSO_SEC_GSP1_ENABLE 28 31 mmDP1_DP_MSO_CNTL1 0 0x2251 8 0 2 DP_MSO_SEC_GSP2_ENABLE 0 3 DP_MSO_SEC_GSP3_ENABLE 4 7 DP_MSO_SEC_GSP4_ENABLE 8 11 DP_MSO_SEC_GSP5_ENABLE 12 15 DP_MSO_SEC_GSP6_ENABLE 16 19 DP_MSO_SEC_GSP7_ENABLE 20 23 DP_MSO_SEC_MPG_ENABLE 24 27 DP_MSO_SEC_ISRC_ENABLE 28 31 mmDP1_DP_DSC_CNTL 0 0x2252 1 0 2 DP_DSC_EN 0 0 mmDP1_DP_SEC_CNTL2 0 0x2253 29 0 2 DP_SEC_GSP1_SEND 0 0 DP_SEC_GSP1_SEND_PENDING 1 1 DP_SEC_GSP1_SEND_DEADLINE_MISSED 2 2 DP_SEC_GSP1_SEND_ANY_LINE 3 3 DP_SEC_GSP2_SEND 4 4 DP_SEC_GSP2_SEND_PENDING 5 5 DP_SEC_GSP2_SEND_DEADLINE_MISSED 6 6 DP_SEC_GSP2_SEND_ANY_LINE 7 7 DP_SEC_GSP3_SEND 8 8 DP_SEC_GSP3_SEND_PENDING 9 9 DP_SEC_GSP3_SEND_DEADLINE_MISSED 10 10 DP_SEC_GSP3_SEND_ANY_LINE 11 11 DP_SEC_GSP4_SEND 12 12 DP_SEC_GSP4_SEND_PENDING 13 13 DP_SEC_GSP4_SEND_DEADLINE_MISSED 14 14 DP_SEC_GSP4_SEND_ANY_LINE 15 15 DP_SEC_GSP5_SEND 16 16 DP_SEC_GSP5_SEND_PENDING 17 17 DP_SEC_GSP5_SEND_DEADLINE_MISSED 18 18 DP_SEC_GSP5_SEND_ANY_LINE 19 19 DP_SEC_GSP6_SEND 20 20 DP_SEC_GSP6_SEND_PENDING 21 21 DP_SEC_GSP6_SEND_DEADLINE_MISSED 22 22 DP_SEC_GSP6_SEND_ANY_LINE 23 23 DP_SEC_GSP7_SEND 24 24 DP_SEC_GSP7_SEND_PENDING 25 25 DP_SEC_GSP7_SEND_DEADLINE_MISSED 26 26 DP_SEC_GSP7_SEND_ANY_LINE 27 27 DP_SEC_GSP7_PPS 28 28 mmDP1_DP_SEC_CNTL3 0 0x2254 2 0 2 DP_SEC_GSP1_LINE_NUM 0 15 DP_SEC_GSP2_LINE_NUM 16 31 mmDP1_DP_SEC_CNTL4 0 0x2255 2 0 2 DP_SEC_GSP3_LINE_NUM 0 15 DP_SEC_GSP4_LINE_NUM 16 31 mmDP1_DP_SEC_CNTL5 0 0x2256 2 0 2 DP_SEC_GSP5_LINE_NUM 0 15 DP_SEC_GSP6_LINE_NUM 16 31 mmDP1_DP_SEC_CNTL6 0 0x2257 1 0 2 DP_SEC_GSP7_LINE_NUM 0 15 mmDP1_DP_SEC_CNTL7 0 0x2258 8 0 2 DP_SEC_GSP0_SEND_ACTIVE 0 0 DP_SEC_GSP1_SEND_ACTIVE 4 4 DP_SEC_GSP2_SEND_ACTIVE 8 8 DP_SEC_GSP3_SEND_ACTIVE 12 12 DP_SEC_GSP4_SEND_ACTIVE 16 16 DP_SEC_GSP5_SEND_ACTIVE 20 20 DP_SEC_GSP6_SEND_ACTIVE 24 24 DP_SEC_GSP7_SEND_ACTIVE 28 28 mmDP1_DP_DB_CNTL 0 0x2259 5 0 2 DP_DB_PENDING 0 0 DP_DB_TAKEN 4 4 DP_DB_TAKEN_CLR 5 5 DP_DB_LOCK 8 8 DP_DB_DISABLE 12 12 mmDP1_DP_MSA_VBID_MISC 0 0x225a 6 0 2 DP_MSA_MISC1_STEREOSYNC_OVERRIDE 0 1 DP_MSA_MISC1_STEREOSYNC_OVERRIDE_EN 4 4 DP_VBID1_OVERRIDE 8 8 DP_VBID2_OVERRIDE 9 9 DP_VBID1_OVERRIDE_EN 12 12 DP_VBID2_OVERRIDE_EN 13 13 mmDIG2_DIG_FE_CNTL 0 0x2268 8 0 2 DIG_SOURCE_SELECT 0 2 DIG_STEREOSYNC_SELECT 4 6 DIG_STEREOSYNC_GATE_EN 8 8 DIG_START 10 10 DIG_DIGITAL_BYPASS_SELECT 12 14 DIG_SYMCLK_FE_ON 24 24 TMDS_PIXEL_ENCODING 28 28 TMDS_COLOR_FORMAT 30 31 mmDIG2_DIG_OUTPUT_CRC_CNTL 0 0x2269 3 0 2 DIG_OUTPUT_CRC_EN 0 0 DIG_OUTPUT_CRC_LINK_SEL 4 4 DIG_OUTPUT_CRC_DATA_SEL 8 9 mmDIG2_DIG_OUTPUT_CRC_RESULT 0 0x226a 1 0 2 DIG_OUTPUT_CRC_RESULT 0 29 mmDIG2_DIG_CLOCK_PATTERN 0 0x226b 1 0 2 DIG_CLOCK_PATTERN 0 9 mmDIG2_DIG_TEST_PATTERN 0 0x226c 6 0 2 DIG_TEST_PATTERN_OUT_EN 0 0 DIG_HALF_CLOCK_PATTERN_SEL 1 1 DIG_RANDOM_PATTERN_OUT_EN 4 4 DIG_RANDOM_PATTERN_RESET 5 5 DIG_TEST_PATTERN_EXTERNAL_RESET_EN 6 6 DIG_STATIC_TEST_PATTERN 16 25 mmDIG2_DIG_RANDOM_PATTERN_SEED 0 0x226d 2 0 2 DIG_RANDOM_PATTERN_SEED 0 23 DIG_RAN_PAT_DURING_DE_ONLY 24 24 mmDIG2_DIG_FIFO_STATUS 0 0x226e 11 0 2 DIG_FIFO_LEVEL_ERROR 0 0 DIG_FIFO_USE_OVERWRITE_LEVEL 1 1 DIG_FIFO_OVERWRITE_LEVEL 2 7 DIG_FIFO_ERROR_ACK 8 8 DIG_FIFO_CAL_AVERAGE_LEVEL 10 15 DIG_FIFO_MAXIMUM_LEVEL 16 20 DIG_FIFO_MINIMUM_LEVEL 22 25 DIG_FIFO_READ_CLOCK_SRC 26 26 DIG_FIFO_CALIBRATED 29 29 DIG_FIFO_FORCE_RECAL_AVERAGE 30 30 DIG_FIFO_FORCE_RECOMP_MINMAX 31 31 mmDIG2_HDMI_CONTROL 0 0x2271 9 0 2 HDMI_KEEPOUT_MODE 0 0 HDMI_DATA_SCRAMBLE_EN 1 1 HDMI_CLOCK_CHANNEL_RATE 2 2 HDMI_NO_EXTRA_NULL_PACKET_FILLED 3 3 HDMI_PACKET_GEN_VERSION 4 4 HDMI_ERROR_ACK 8 8 HDMI_ERROR_MASK 9 9 HDMI_DEEP_COLOR_ENABLE 24 24 HDMI_DEEP_COLOR_DEPTH 28 29 mmDIG2_HDMI_STATUS 0 0x2272 4 0 2 HDMI_ACTIVE_AVMUTE 0 0 HDMI_AUDIO_PACKET_ERROR 16 16 HDMI_VBI_PACKET_ERROR 20 20 HDMI_ERROR_INT 27 27 mmDIG2_HDMI_AUDIO_PACKET_CONTROL 0 0x2273 2 0 2 HDMI_AUDIO_DELAY_EN 4 5 HDMI_AUDIO_PACKETS_PER_LINE 16 20 mmDIG2_HDMI_ACR_PACKET_CONTROL 0 0x2274 7 0 2 HDMI_ACR_SEND 0 0 HDMI_ACR_CONT 1 1 HDMI_ACR_SELECT 4 5 HDMI_ACR_SOURCE 8 8 HDMI_ACR_AUTO_SEND 12 12 HDMI_ACR_N_MULTIPLE 16 18 HDMI_ACR_AUDIO_PRIORITY 31 31 mmDIG2_HDMI_VBI_PACKET_CONTROL 0 0x2275 6 0 2 HDMI_NULL_SEND 0 0 HDMI_GC_SEND 4 4 HDMI_GC_CONT 5 5 HDMI_ISRC_SEND 8 8 HDMI_ISRC_CONT 9 9 HDMI_ISRC_LINE 16 21 mmDIG2_HDMI_INFOFRAME_CONTROL0 0 0x2276 4 0 2 HDMI_AUDIO_INFO_SEND 4 4 HDMI_AUDIO_INFO_CONT 5 5 HDMI_MPEG_INFO_SEND 8 8 HDMI_MPEG_INFO_CONT 9 9 mmDIG2_HDMI_INFOFRAME_CONTROL1 0 0x2277 2 0 2 HDMI_AUDIO_INFO_LINE 8 13 HDMI_MPEG_INFO_LINE 16 21 mmDIG2_HDMI_GENERIC_PACKET_CONTROL0 0 0x2278 6 0 2 HDMI_GENERIC0_SEND 0 0 HDMI_GENERIC0_CONT 1 1 HDMI_GENERIC1_SEND 4 4 HDMI_GENERIC1_CONT 5 5 HDMI_GENERIC0_LINE 16 21 HDMI_GENERIC1_LINE 24 29 mmDIG2_AFMT_INTERRUPT_STATUS 0 0x2279 0 0 2 mmDIG2_HDMI_GC 0 0x227b 5 0 2 HDMI_GC_AVMUTE 0 0 HDMI_GC_AVMUTE_CONT 2 2 HDMI_DEFAULT_PHASE 4 4 HDMI_PACKING_PHASE 8 11 HDMI_PACKING_PHASE_OVERRIDE 12 12 mmDIG2_AFMT_AUDIO_PACKET_CONTROL2 0 0x227c 6 0 2 AFMT_AUDIO_LAYOUT_OVRD 0 0 AFMT_AUDIO_LAYOUT_SELECT 1 1 AFMT_AUDIO_CHANNEL_ENABLE 8 15 AFMT_DP_AUDIO_STREAM_ID 16 23 AFMT_HBR_ENABLE_OVRD 24 24 AFMT_60958_OSF_OVRD 28 28 mmDIG2_AFMT_ISRC1_0 0 0x227d 3 0 2 AFMT_ISRC_STATUS 0 2 AFMT_ISRC_CONTINUE 6 6 AFMT_ISRC_VALID 7 7 mmDIG2_AFMT_ISRC1_1 0 0x227e 4 0 2 AFMT_UPC_EAN_ISRC0 0 7 AFMT_UPC_EAN_ISRC1 8 15 AFMT_UPC_EAN_ISRC2 16 23 AFMT_UPC_EAN_ISRC3 24 31 mmDIG2_AFMT_ISRC1_2 0 0x227f 4 0 2 AFMT_UPC_EAN_ISRC4 0 7 AFMT_UPC_EAN_ISRC5 8 15 AFMT_UPC_EAN_ISRC6 16 23 AFMT_UPC_EAN_ISRC7 24 31 mmDIG2_AFMT_ISRC1_3 0 0x2280 4 0 2 AFMT_UPC_EAN_ISRC8 0 7 AFMT_UPC_EAN_ISRC9 8 15 AFMT_UPC_EAN_ISRC10 16 23 AFMT_UPC_EAN_ISRC11 24 31 mmDIG2_AFMT_ISRC1_4 0 0x2281 4 0 2 AFMT_UPC_EAN_ISRC12 0 7 AFMT_UPC_EAN_ISRC13 8 15 AFMT_UPC_EAN_ISRC14 16 23 AFMT_UPC_EAN_ISRC15 24 31 mmDIG2_AFMT_ISRC2_0 0 0x2282 4 0 2 AFMT_UPC_EAN_ISRC16 0 7 AFMT_UPC_EAN_ISRC17 8 15 AFMT_UPC_EAN_ISRC18 16 23 AFMT_UPC_EAN_ISRC19 24 31 mmDIG2_AFMT_ISRC2_1 0 0x2283 4 0 2 AFMT_UPC_EAN_ISRC20 0 7 AFMT_UPC_EAN_ISRC21 8 15 AFMT_UPC_EAN_ISRC22 16 23 AFMT_UPC_EAN_ISRC23 24 31 mmDIG2_AFMT_ISRC2_2 0 0x2284 4 0 2 AFMT_UPC_EAN_ISRC24 0 7 AFMT_UPC_EAN_ISRC25 8 15 AFMT_UPC_EAN_ISRC26 16 23 AFMT_UPC_EAN_ISRC27 24 31 mmDIG2_AFMT_ISRC2_3 0 0x2285 4 0 2 AFMT_UPC_EAN_ISRC28 0 7 AFMT_UPC_EAN_ISRC29 8 15 AFMT_UPC_EAN_ISRC30 16 23 AFMT_UPC_EAN_ISRC31 24 31 mmDIG2_HDMI_GENERIC_PACKET_CONTROL2 0 0x2286 6 0 2 HDMI_GENERIC4_SEND 0 0 HDMI_GENERIC4_CONT 1 1 HDMI_GENERIC5_SEND 4 4 HDMI_GENERIC5_CONT 5 5 HDMI_GENERIC4_LINE 16 21 HDMI_GENERIC5_LINE 24 29 mmDIG2_HDMI_GENERIC_PACKET_CONTROL3 0 0x2287 6 0 2 HDMI_GENERIC6_SEND 0 0 HDMI_GENERIC6_CONT 1 1 HDMI_GENERIC7_SEND 4 4 HDMI_GENERIC7_CONT 5 5 HDMI_GENERIC6_LINE 16 21 HDMI_GENERIC7_LINE 24 29 mmDIG2_HDMI_DB_CONTROL 0 0x2288 5 0 2 HDMI_DB_PENDING 0 0 HDMI_DB_TAKEN 4 4 HDMI_DB_TAKEN_CLR 5 5 HDMI_DB_LOCK 8 8 HDMI_DB_DISABLE 12 12 mmDIG2_AFMT_MPEG_INFO0 0 0x228a 4 0 2 AFMT_MPEG_INFO_CHECKSUM 0 7 AFMT_MPEG_INFO_MB0 8 15 AFMT_MPEG_INFO_MB1 16 23 AFMT_MPEG_INFO_MB2 24 31 mmDIG2_AFMT_MPEG_INFO1 0 0x228b 3 0 2 AFMT_MPEG_INFO_MB3 0 7 AFMT_MPEG_INFO_MF 8 9 AFMT_MPEG_INFO_FR 12 12 mmDIG2_AFMT_GENERIC_HDR 0 0x228c 4 0 2 AFMT_GENERIC_HB0 0 7 AFMT_GENERIC_HB1 8 15 AFMT_GENERIC_HB2 16 23 AFMT_GENERIC_HB3 24 31 mmDIG2_AFMT_GENERIC_0 0 0x228d 4 0 2 AFMT_GENERIC_BYTE0 0 7 AFMT_GENERIC_BYTE1 8 15 AFMT_GENERIC_BYTE2 16 23 AFMT_GENERIC_BYTE3 24 31 mmDIG2_AFMT_GENERIC_1 0 0x228e 4 0 2 AFMT_GENERIC_BYTE4 0 7 AFMT_GENERIC_BYTE5 8 15 AFMT_GENERIC_BYTE6 16 23 AFMT_GENERIC_BYTE7 24 31 mmDIG2_AFMT_GENERIC_2 0 0x228f 4 0 2 AFMT_GENERIC_BYTE8 0 7 AFMT_GENERIC_BYTE9 8 15 AFMT_GENERIC_BYTE10 16 23 AFMT_GENERIC_BYTE11 24 31 mmDIG2_AFMT_GENERIC_3 0 0x2290 4 0 2 AFMT_GENERIC_BYTE12 0 7 AFMT_GENERIC_BYTE13 8 15 AFMT_GENERIC_BYTE14 16 23 AFMT_GENERIC_BYTE15 24 31 mmDIG2_AFMT_GENERIC_4 0 0x2291 4 0 2 AFMT_GENERIC_BYTE16 0 7 AFMT_GENERIC_BYTE17 8 15 AFMT_GENERIC_BYTE18 16 23 AFMT_GENERIC_BYTE19 24 31 mmDIG2_AFMT_GENERIC_5 0 0x2292 4 0 2 AFMT_GENERIC_BYTE20 0 7 AFMT_GENERIC_BYTE21 8 15 AFMT_GENERIC_BYTE22 16 23 AFMT_GENERIC_BYTE23 24 31 mmDIG2_AFMT_GENERIC_6 0 0x2293 4 0 2 AFMT_GENERIC_BYTE24 0 7 AFMT_GENERIC_BYTE25 8 15 AFMT_GENERIC_BYTE26 16 23 AFMT_GENERIC_BYTE27 24 31 mmDIG2_AFMT_GENERIC_7 0 0x2294 4 0 2 AFMT_GENERIC_BYTE28 0 7 AFMT_GENERIC_BYTE29 8 15 AFMT_GENERIC_BYTE30 16 23 AFMT_GENERIC_BYTE31 24 31 mmDIG2_HDMI_GENERIC_PACKET_CONTROL1 0 0x2295 6 0 2 HDMI_GENERIC2_SEND 0 0 HDMI_GENERIC2_CONT 1 1 HDMI_GENERIC3_SEND 4 4 HDMI_GENERIC3_CONT 5 5 HDMI_GENERIC2_LINE 16 21 HDMI_GENERIC3_LINE 24 29 mmDIG2_HDMI_ACR_32_0 0 0x2296 1 0 2 HDMI_ACR_CTS_32 12 31 mmDIG2_HDMI_ACR_32_1 0 0x2297 1 0 2 HDMI_ACR_N_32 0 19 mmDIG2_HDMI_ACR_44_0 0 0x2298 1 0 2 HDMI_ACR_CTS_44 12 31 mmDIG2_HDMI_ACR_44_1 0 0x2299 1 0 2 HDMI_ACR_N_44 0 19 mmDIG2_HDMI_ACR_48_0 0 0x229a 1 0 2 HDMI_ACR_CTS_48 12 31 mmDIG2_HDMI_ACR_48_1 0 0x229b 1 0 2 HDMI_ACR_N_48 0 19 mmDIG2_HDMI_ACR_STATUS_0 0 0x229c 1 0 2 HDMI_ACR_CTS 12 31 mmDIG2_HDMI_ACR_STATUS_1 0 0x229d 1 0 2 HDMI_ACR_N 0 19 mmDIG2_AFMT_AUDIO_INFO0 0 0x229e 5 0 2 AFMT_AUDIO_INFO_CHECKSUM 0 7 AFMT_AUDIO_INFO_CC 8 10 AFMT_AUDIO_INFO_CT 11 14 AFMT_AUDIO_INFO_CHECKSUM_OFFSET 16 23 AFMT_AUDIO_INFO_CXT 24 28 mmDIG2_AFMT_AUDIO_INFO1 0 0x229f 4 0 2 AFMT_AUDIO_INFO_CA 0 7 AFMT_AUDIO_INFO_LSV 11 14 AFMT_AUDIO_INFO_DM_INH 15 15 AFMT_AUDIO_INFO_LFEPBL 16 17 mmDIG2_AFMT_60958_0 0 0x22a0 10 0 2 AFMT_60958_CS_A 0 0 AFMT_60958_CS_B 1 1 AFMT_60958_CS_C 2 2 AFMT_60958_CS_D 3 5 AFMT_60958_CS_MODE 6 7 AFMT_60958_CS_CATEGORY_CODE 8 15 AFMT_60958_CS_SOURCE_NUMBER 16 19 AFMT_60958_CS_CHANNEL_NUMBER_L 20 23 AFMT_60958_CS_SAMPLING_FREQUENCY 24 27 AFMT_60958_CS_CLOCK_ACCURACY 28 29 mmDIG2_AFMT_60958_1 0 0x22a1 5 0 2 AFMT_60958_CS_WORD_LENGTH 0 3 AFMT_60958_CS_ORIGINAL_SAMPLING_FREQUENCY 4 7 AFMT_60958_VALID_L 16 16 AFMT_60958_VALID_R 18 18 AFMT_60958_CS_CHANNEL_NUMBER_R 20 23 mmDIG2_AFMT_AUDIO_CRC_CONTROL 0 0x22a2 5 0 2 AFMT_AUDIO_CRC_EN 0 0 AFMT_AUDIO_CRC_CONT 4 4 AFMT_AUDIO_CRC_SOURCE 8 8 AFMT_AUDIO_CRC_CH_SEL 12 15 AFMT_AUDIO_CRC_COUNT 16 31 mmDIG2_AFMT_RAMP_CONTROL0 0 0x22a3 2 0 2 AFMT_RAMP_MAX_COUNT 0 23 AFMT_RAMP_DATA_SIGN 31 31 mmDIG2_AFMT_RAMP_CONTROL1 0 0x22a4 2 0 2 AFMT_RAMP_MIN_COUNT 0 23 AFMT_AUDIO_TEST_CH_DISABLE 24 31 mmDIG2_AFMT_RAMP_CONTROL2 0 0x22a5 1 0 2 AFMT_RAMP_INC_COUNT 0 23 mmDIG2_AFMT_RAMP_CONTROL3 0 0x22a6 1 0 2 AFMT_RAMP_DEC_COUNT 0 23 mmDIG2_AFMT_60958_2 0 0x22a7 6 0 2 AFMT_60958_CS_CHANNEL_NUMBER_2 0 3 AFMT_60958_CS_CHANNEL_NUMBER_3 4 7 AFMT_60958_CS_CHANNEL_NUMBER_4 8 11 AFMT_60958_CS_CHANNEL_NUMBER_5 12 15 AFMT_60958_CS_CHANNEL_NUMBER_6 16 19 AFMT_60958_CS_CHANNEL_NUMBER_7 20 23 mmDIG2_AFMT_AUDIO_CRC_RESULT 0 0x22a8 2 0 2 AFMT_AUDIO_CRC_DONE 0 0 AFMT_AUDIO_CRC 8 31 mmDIG2_AFMT_STATUS 0 0x22a9 4 0 2 AFMT_AUDIO_ENABLE 4 4 AFMT_AZ_HBR_ENABLE 8 8 AFMT_AUDIO_FIFO_OVERFLOW 24 24 AFMT_AZ_AUDIO_ENABLE_CHG 30 30 mmDIG2_AFMT_AUDIO_PACKET_CONTROL 0 0x22aa 8 0 2 AFMT_AUDIO_SAMPLE_SEND 0 0 AFMT_RESET_FIFO_WHEN_AUDIO_DIS 11 11 AFMT_AUDIO_TEST_EN 12 12 AFMT_AUDIO_TEST_MODE 14 14 AFMT_AUDIO_FIFO_OVERFLOW_ACK 23 23 AFMT_AUDIO_CHANNEL_SWAP 24 24 AFMT_60958_CS_UPDATE 26 26 AFMT_AZ_AUDIO_ENABLE_CHG_ACK 30 30 mmDIG2_AFMT_VBI_PACKET_CONTROL 0 0x22ab 4 0 2 AFMT_GENERIC_LOCK_STATUS 8 8 AFMT_GENERIC_CONFLICT 16 16 AFMT_GENERIC_CONFLICT_CLR 17 17 AFMT_GENERIC_INDEX 28 31 mmDIG2_AFMT_INFOFRAME_CONTROL0 0 0x22ac 3 0 2 AFMT_AUDIO_INFO_SOURCE 6 6 AFMT_AUDIO_INFO_UPDATE 7 7 AFMT_MPEG_INFO_UPDATE 10 10 mmDIG2_AFMT_AUDIO_SRC_CONTROL 0 0x22ad 1 0 2 AFMT_AUDIO_SRC_SELECT 0 2 mmDIG2_DIG_BE_CNTL 0 0x22af 5 0 2 DIG_DUAL_LINK_ENABLE 0 0 DIG_SWAP 1 1 DIG_FE_SOURCE_SELECT 8 14 DIG_MODE 16 18 DIG_HPD_SELECT 28 30 mmDIG2_DIG_BE_EN_CNTL 0 0x22b0 2 0 2 DIG_ENABLE 0 0 DIG_SYMCLK_BE_ON 8 8 mmDIG2_TMDS_CNTL 0 0x22d3 1 0 2 TMDS_SYNC_PHASE 0 0 mmDIG2_TMDS_CONTROL_CHAR 0 0x22d4 4 0 2 TMDS_CONTROL_CHAR0_OUT_EN 0 0 TMDS_CONTROL_CHAR1_OUT_EN 1 1 TMDS_CONTROL_CHAR2_OUT_EN 2 2 TMDS_CONTROL_CHAR3_OUT_EN 3 3 mmDIG2_TMDS_CONTROL0_FEEDBACK 0 0x22d5 2 0 2 TMDS_CONTROL0_FEEDBACK_SELECT 0 1 TMDS_CONTROL0_FEEDBACK_DELAY 8 9 mmDIG2_TMDS_STEREOSYNC_CTL_SEL 0 0x22d6 1 0 2 TMDS_STEREOSYNC_CTL_SEL 0 1 mmDIG2_TMDS_SYNC_CHAR_PATTERN_0_1 0 0x22d7 2 0 2 TMDS_SYNC_CHAR_PATTERN0 0 9 TMDS_SYNC_CHAR_PATTERN1 16 25 mmDIG2_TMDS_SYNC_CHAR_PATTERN_2_3 0 0x22d8 2 0 2 TMDS_SYNC_CHAR_PATTERN2 0 9 TMDS_SYNC_CHAR_PATTERN3 16 25 mmDIG2_TMDS_CTL_BITS 0 0x22da 4 0 2 TMDS_CTL0 0 0 TMDS_CTL1 8 8 TMDS_CTL2 16 16 TMDS_CTL3 24 24 mmDIG2_TMDS_DCBALANCER_CONTROL 0 0x22db 4 0 2 TMDS_DCBALANCER_EN 0 0 TMDS_DCBALANCER_TEST_EN 8 8 TMDS_DCBALANCER_TEST_IN 16 19 TMDS_DCBALANCER_FORCE 24 24 mmDIG2_TMDS_CTL0_1_GEN_CNTL 0 0x22dd 15 0 2 TMDS_CTL0_DATA_SEL 0 3 TMDS_CTL0_DATA_DELAY 4 6 TMDS_CTL0_DATA_INVERT 7 7 TMDS_CTL0_DATA_MODULATION 8 9 TMDS_CTL0_USE_FEEDBACK_PATH 10 10 TMDS_CTL0_FB_SYNC_CONT 11 11 TMDS_CTL0_PATTERN_OUT_EN 12 12 TMDS_CTL1_DATA_SEL 16 19 TMDS_CTL1_DATA_DELAY 20 22 TMDS_CTL1_DATA_INVERT 23 23 TMDS_CTL1_DATA_MODULATION 24 25 TMDS_CTL1_USE_FEEDBACK_PATH 26 26 TMDS_CTL1_FB_SYNC_CONT 27 27 TMDS_CTL1_PATTERN_OUT_EN 28 28 TMDS_2BIT_COUNTER_EN 31 31 mmDIG2_TMDS_CTL2_3_GEN_CNTL 0 0x22de 14 0 2 TMDS_CTL2_DATA_SEL 0 3 TMDS_CTL2_DATA_DELAY 4 6 TMDS_CTL2_DATA_INVERT 7 7 TMDS_CTL2_DATA_MODULATION 8 9 TMDS_CTL2_USE_FEEDBACK_PATH 10 10 TMDS_CTL2_FB_SYNC_CONT 11 11 TMDS_CTL2_PATTERN_OUT_EN 12 12 TMDS_CTL3_DATA_SEL 16 19 TMDS_CTL3_DATA_DELAY 20 22 TMDS_CTL3_DATA_INVERT 23 23 TMDS_CTL3_DATA_MODULATION 24 25 TMDS_CTL3_USE_FEEDBACK_PATH 26 26 TMDS_CTL3_FB_SYNC_CONT 27 27 TMDS_CTL3_PATTERN_OUT_EN 28 28 mmDIG2_DIG_VERSION 0 0x22e0 1 0 2 DIG_TYPE 0 0 mmDIG2_DIG_LANE_ENABLE 0 0x22e1 5 0 2 DIG_LANE0EN 0 0 DIG_LANE1EN 1 1 DIG_LANE2EN 2 2 DIG_LANE3EN 3 3 DIG_CLK_EN 8 8 mmDIG2_AFMT_CNTL 0 0x22e6 2 0 2 AFMT_AUDIO_CLOCK_EN 0 0 AFMT_AUDIO_CLOCK_ON 8 8 mmDIG2_AFMT_VBI_PACKET_CONTROL1 0 0x22e7 32 0 2 AFMT_GENERIC0_FRAME_UPDATE 0 0 AFMT_GENERIC0_FRAME_UPDATE_PENDING 1 1 AFMT_GENERIC0_IMMEDIATE_UPDATE 2 2 AFMT_GENERIC0_IMMEDIATE_UPDATE_PENDING 3 3 AFMT_GENERIC1_FRAME_UPDATE 4 4 AFMT_GENERIC1_FRAME_UPDATE_PENDING 5 5 AFMT_GENERIC1_IMMEDIATE_UPDATE 6 6 AFMT_GENERIC1_IMMEDIATE_UPDATE_PENDING 7 7 AFMT_GENERIC2_FRAME_UPDATE 8 8 AFMT_GENERIC2_FRAME_UPDATE_PENDING 9 9 AFMT_GENERIC2_IMMEDIATE_UPDATE 10 10 AFMT_GENERIC2_IMMEDIATE_UPDATE_PENDING 11 11 AFMT_GENERIC3_FRAME_UPDATE 12 12 AFMT_GENERIC3_FRAME_UPDATE_PENDING 13 13 AFMT_GENERIC3_IMMEDIATE_UPDATE 14 14 AFMT_GENERIC3_IMMEDIATE_UPDATE_PENDING 15 15 AFMT_GENERIC4_FRAME_UPDATE 16 16 AFMT_GENERIC4_FRAME_UPDATE_PENDING 17 17 AFMT_GENERIC4_IMMEDIATE_UPDATE 18 18 AFMT_GENERIC4_IMMEDIATE_UPDATE_PENDING 19 19 AFMT_GENERIC5_FRAME_UPDATE 20 20 AFMT_GENERIC5_FRAME_UPDATE_PENDING 21 21 AFMT_GENERIC5_IMMEDIATE_UPDATE 22 22 AFMT_GENERIC5_IMMEDIATE_UPDATE_PENDING 23 23 AFMT_GENERIC6_FRAME_UPDATE 24 24 AFMT_GENERIC6_FRAME_UPDATE_PENDING 25 25 AFMT_GENERIC6_IMMEDIATE_UPDATE 26 26 AFMT_GENERIC6_IMMEDIATE_UPDATE_PENDING 27 27 AFMT_GENERIC7_FRAME_UPDATE 28 28 AFMT_GENERIC7_FRAME_UPDATE_PENDING 29 29 AFMT_GENERIC7_IMMEDIATE_UPDATE 30 30 AFMT_GENERIC7_IMMEDIATE_UPDATE_PENDING 31 31 mmDP2_DP_LINK_CNTL 0 0x2308 3 0 2 DP_LINK_TRAINING_COMPLETE 4 4 DP_LINK_STATUS 8 8 DP_EMBEDDED_PANEL_MODE 17 17 mmDP2_DP_PIXEL_FORMAT 0 0x2309 3 0 2 DP_PIXEL_ENCODING 0 2 DP_COMPONENT_DEPTH 24 26 DP_PIXEL_COMBINE 28 29 mmDP2_DP_MSA_COLORIMETRY 0 0x230a 1 0 2 DP_MSA_MISC0 24 31 mmDP2_DP_CONFIG 0 0x230b 1 0 2 DP_UDI_LANES 0 1 mmDP2_DP_VID_STREAM_CNTL 0 0x230c 4 0 2 DP_VID_STREAM_ENABLE 0 0 DP_VID_STREAM_DIS_DEFER 8 9 DP_VID_STREAM_STATUS 16 16 DP_VID_STREAM_CHANGE_KEEPOUT 20 20 mmDP2_DP_STEER_FIFO 0 0x230d 7 0 2 DP_STEER_FIFO_RESET 0 0 DP_STEER_OVERFLOW_FLAG 4 4 DP_STEER_OVERFLOW_INT 5 5 DP_STEER_OVERFLOW_ACK 6 6 DP_STEER_OVERFLOW_MASK 7 7 DP_TU_OVERFLOW_FLAG 8 8 DP_TU_OVERFLOW_ACK 12 12 mmDP2_DP_MSA_MISC 0 0x230e 4 0 2 DP_MSA_MISC1 0 7 DP_MSA_MISC2 8 15 DP_MSA_MISC3 16 23 DP_MSA_MISC4 24 31 mmDP2_DP_VID_TIMING 0 0x2310 5 0 2 DP_VID_M_N_DOUBLE_BUFFER_MODE 4 4 DP_VID_M_N_GEN_EN 8 8 DP_VID_N_MUL 10 11 DP_VID_M_DIV 12 13 DP_VID_N_DIV 24 31 mmDP2_DP_VID_N 0 0x2311 1 0 2 DP_VID_N 0 23 mmDP2_DP_VID_M 0 0x2312 1 0 2 DP_VID_M 0 23 mmDP2_DP_LINK_FRAMING_CNTL 0 0x2313 3 0 2 DP_IDLE_BS_INTERVAL 0 17 DP_VBID_DISABLE 24 24 DP_VID_ENHANCED_FRAME_MODE 28 28 mmDP2_DP_HBR2_EYE_PATTERN 0 0x2314 1 0 2 DP_HBR2_EYE_PATTERN_ENABLE 0 0 mmDP2_DP_VID_MSA_VBID 0 0x2315 2 0 2 DP_VID_MSA_LOCATION 0 11 DP_VID_VBID_FIELD_POL 24 24 mmDP2_DP_VID_INTERRUPT_CNTL 0 0x2316 3 0 2 DP_VID_STREAM_DISABLE_INT 0 0 DP_VID_STREAM_DISABLE_ACK 1 1 DP_VID_STREAM_DISABLE_MASK 2 2 mmDP2_DP_DPHY_CNTL 0 0x2317 6 0 2 DPHY_ATEST_SEL_LANE0 0 0 DPHY_ATEST_SEL_LANE1 1 1 DPHY_ATEST_SEL_LANE2 2 2 DPHY_ATEST_SEL_LANE3 3 3 DPHY_BYPASS 16 16 DPHY_SKEW_BYPASS 24 24 mmDP2_DP_DPHY_TRAINING_PATTERN_SEL 0 0x2318 1 0 2 DPHY_TRAINING_PATTERN_SEL 0 1 mmDP2_DP_DPHY_SYM0 0 0x2319 3 0 2 DPHY_SYM1 0 9 DPHY_SYM2 10 19 DPHY_SYM3 20 29 mmDP2_DP_DPHY_SYM1 0 0x231a 3 0 2 DPHY_SYM4 0 9 DPHY_SYM5 10 19 DPHY_SYM6 20 29 mmDP2_DP_DPHY_SYM2 0 0x231b 2 0 2 DPHY_SYM7 0 9 DPHY_SYM8 10 19 mmDP2_DP_DPHY_8B10B_CNTL 0 0x231c 3 0 2 DPHY_8B10B_RESET 8 8 DPHY_8B10B_EXT_DISP 16 16 DPHY_8B10B_CUR_DISP 24 24 mmDP2_DP_DPHY_PRBS_CNTL 0 0x231d 3 0 2 DPHY_PRBS_EN 0 0 DPHY_PRBS_SEL 4 5 DPHY_PRBS_SEED 8 30 mmDP2_DP_DPHY_SCRAM_CNTL 0 0x231e 4 0 2 DPHY_SCRAMBLER_DIS 0 0 DPHY_SCRAMBLER_ADVANCE 4 4 DPHY_SCRAMBLER_BS_COUNT 8 17 DPHY_SCRAMBLER_KCODE 24 24 mmDP2_DP_DPHY_CRC_EN 0 0x231f 3 0 2 DPHY_CRC_EN 0 0 DPHY_CRC_CONT_EN 4 4 DPHY_CRC_RESULT_VALID 8 8 mmDP2_DP_DPHY_CRC_CNTL 0 0x2320 3 0 2 DPHY_CRC_FIELD 0 0 DPHY_CRC_SEL 4 5 DPHY_CRC_MASK 16 23 mmDP2_DP_DPHY_CRC_RESULT 0 0x2321 4 0 2 DPHY_CRC_RESULT 0 7 DPHY_CRC_RESULT1 8 15 DPHY_CRC_RESULT2 16 23 DPHY_CRC_RESULT3 24 31 mmDP2_DP_DPHY_CRC_MST_CNTL 0 0x2322 2 0 2 DPHY_CRC_MST_FIRST_SLOT 0 5 DPHY_CRC_MST_LAST_SLOT 8 13 mmDP2_DP_DPHY_CRC_MST_STATUS 0 0x2323 3 0 2 DPHY_CRC_MST_PHASE_LOCK 0 0 DPHY_CRC_MST_PHASE_ERROR 8 8 DPHY_CRC_MST_PHASE_ERROR_ACK 16 16 mmDP2_DP_DPHY_FAST_TRAINING 0 0x2324 5 0 2 DPHY_RX_FAST_TRAINING_CAPABLE 0 0 DPHY_SW_FAST_TRAINING_START 1 1 DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN 2 2 DPHY_FAST_TRAINING_TP1_TIME 8 19 DPHY_FAST_TRAINING_TP2_TIME 20 31 mmDP2_DP_DPHY_FAST_TRAINING_STATUS 0 0x2325 4 0 2 DPHY_FAST_TRAINING_STATE 0 2 DPHY_FAST_TRAINING_COMPLETE_OCCURRED 4 4 DPHY_FAST_TRAINING_COMPLETE_MASK 8 8 DPHY_FAST_TRAINING_COMPLETE_ACK 12 12 mmDP2_DP_SEC_CNTL 0 0x232b 14 0 2 DP_SEC_STREAM_ENABLE 0 0 DP_SEC_ASP_ENABLE 4 4 DP_SEC_ATP_ENABLE 8 8 DP_SEC_AIP_ENABLE 12 12 DP_SEC_ACM_ENABLE 16 16 DP_SEC_GSP0_ENABLE 20 20 DP_SEC_GSP1_ENABLE 21 21 DP_SEC_GSP2_ENABLE 22 22 DP_SEC_GSP3_ENABLE 23 23 DP_SEC_GSP4_ENABLE 24 24 DP_SEC_GSP5_ENABLE 25 25 DP_SEC_GSP6_ENABLE 26 26 DP_SEC_GSP7_ENABLE 27 27 DP_SEC_MPG_ENABLE 28 28 mmDP2_DP_SEC_CNTL1 0 0x232c 7 0 2 DP_SEC_ISRC_ENABLE 0 0 DP_SEC_GSP0_PRIORITY 4 4 DP_SEC_GSP0_SEND 5 5 DP_SEC_GSP0_SEND_PENDING 6 6 DP_SEC_GSP0_SEND_DEADLINE_MISSED 7 7 DP_SEC_GSP0_SEND_ANY_LINE 8 8 DP_SEC_GSP0_LINE_NUM 16 31 mmDP2_DP_SEC_FRAMING1 0 0x232d 2 0 2 DP_SEC_FRAME_START_LOCATION 0 11 DP_SEC_VBLANK_TRANSMIT_WIDTH 16 31 mmDP2_DP_SEC_FRAMING2 0 0x232e 2 0 2 DP_SEC_START_POSITION 0 15 DP_SEC_HBLANK_TRANSMIT_WIDTH 16 31 mmDP2_DP_SEC_FRAMING3 0 0x232f 2 0 2 DP_SEC_IDLE_FRAME_SIZE 0 13 DP_SEC_IDLE_TRANSMIT_WIDTH 16 31 mmDP2_DP_SEC_FRAMING4 0 0x2330 4 0 2 DP_SEC_COLLISION_STATUS 20 20 DP_SEC_COLLISION_ACK 24 24 DP_SEC_AUDIO_MUTE 28 28 DP_SEC_AUDIO_MUTE_STATUS 29 29 mmDP2_DP_SEC_AUD_N 0 0x2331 1 0 2 DP_SEC_AUD_N 0 23 mmDP2_DP_SEC_AUD_N_READBACK 0 0x2332 1 0 2 DP_SEC_AUD_N_READBACK 0 23 mmDP2_DP_SEC_AUD_M 0 0x2333 1 0 2 DP_SEC_AUD_M 0 23 mmDP2_DP_SEC_AUD_M_READBACK 0 0x2334 1 0 2 DP_SEC_AUD_M_READBACK 0 23 mmDP2_DP_SEC_TIMESTAMP 0 0x2335 1 0 2 DP_SEC_TIMESTAMP_MODE 0 0 mmDP2_DP_SEC_PACKET_CNTL 0 0x2336 4 0 2 DP_SEC_ASP_CODING_TYPE 1 3 DP_SEC_ASP_PRIORITY 4 4 DP_SEC_VERSION 8 13 DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE 16 16 mmDP2_DP_MSE_RATE_CNTL 0 0x2337 2 0 2 DP_MSE_RATE_Y 0 25 DP_MSE_RATE_X 26 31 mmDP2_DP_MSE_RATE_UPDATE 0 0x2339 1 0 2 DP_MSE_RATE_UPDATE_PENDING 0 0 mmDP2_DP_MSE_SAT0 0 0x233a 4 0 2 DP_MSE_SAT_SRC0 0 2 DP_MSE_SAT_SLOT_COUNT0 8 13 DP_MSE_SAT_SRC1 16 18 DP_MSE_SAT_SLOT_COUNT1 24 29 mmDP2_DP_MSE_SAT1 0 0x233b 4 0 2 DP_MSE_SAT_SRC2 0 2 DP_MSE_SAT_SLOT_COUNT2 8 13 DP_MSE_SAT_SRC3 16 18 DP_MSE_SAT_SLOT_COUNT3 24 29 mmDP2_DP_MSE_SAT2 0 0x233c 4 0 2 DP_MSE_SAT_SRC4 0 2 DP_MSE_SAT_SLOT_COUNT4 8 13 DP_MSE_SAT_SRC5 16 18 DP_MSE_SAT_SLOT_COUNT5 24 29 mmDP2_DP_MSE_SAT_UPDATE 0 0x233d 2 0 2 DP_MSE_SAT_UPDATE 0 1 DP_MSE_16_MTP_KEEPOUT 8 8 mmDP2_DP_MSE_LINK_TIMING 0 0x233e 2 0 2 DP_MSE_LINK_FRAME 0 9 DP_MSE_LINK_LINE 16 17 mmDP2_DP_MSE_MISC_CNTL 0 0x233f 3 0 2 DP_MSE_BLANK_CODE 0 0 DP_MSE_TIMESTAMP_MODE 4 4 DP_MSE_ZERO_ENCODER 8 8 mmDP2_DP_DPHY_BS_SR_SWAP_CNTL 0 0x2344 3 0 2 DPHY_LOAD_BS_COUNT 0 9 DPHY_BS_SR_SWAP_DONE 15 15 DPHY_LOAD_BS_COUNT_START 16 16 mmDP2_DP_DPHY_HBR2_PATTERN_CONTROL 0 0x2345 1 0 2 DP_DPHY_HBR2_PATTERN_CONTROL 0 2 mmDP2_DP_MSE_SAT0_STATUS 0 0x2347 4 0 2 DP_MSE_SAT_SRC0_STATUS 0 2 DP_MSE_SAT_SLOT_COUNT0_STATUS 8 13 DP_MSE_SAT_SRC1_STATUS 16 18 DP_MSE_SAT_SLOT_COUNT1_STATUS 24 29 mmDP2_DP_MSE_SAT1_STATUS 0 0x2348 4 0 2 DP_MSE_SAT_SRC2_STATUS 0 2 DP_MSE_SAT_SLOT_COUNT2_STATUS 8 13 DP_MSE_SAT_SRC3_STATUS 16 18 DP_MSE_SAT_SLOT_COUNT3_STATUS 24 29 mmDP2_DP_MSE_SAT2_STATUS 0 0x2349 4 0 2 DP_MSE_SAT_SRC4_STATUS 0 2 DP_MSE_SAT_SLOT_COUNT4_STATUS 8 13 DP_MSE_SAT_SRC5_STATUS 16 18 DP_MSE_SAT_SLOT_COUNT5_STATUS 24 29 mmDP2_DP_MSA_TIMING_PARAM1 0 0x234c 2 0 2 DP_MSA_VTOTAL 0 15 DP_MSA_HTOTAL 16 31 mmDP2_DP_MSA_TIMING_PARAM2 0 0x234d 2 0 2 DP_MSA_VSTART 0 15 DP_MSA_HSTART 16 31 mmDP2_DP_MSA_TIMING_PARAM3 0 0x234e 4 0 2 DP_MSA_VSYNCWIDTH 0 14 DP_MSA_VSYNCPOLARITY 15 15 DP_MSA_HSYNCWIDTH 16 30 DP_MSA_HSYNCPOLARITY 31 31 mmDP2_DP_MSA_TIMING_PARAM4 0 0x234f 2 0 2 DP_MSA_VHEIGHT 0 15 DP_MSA_HWIDTH 16 31 mmDP2_DP_MSO_CNTL 0 0x2350 8 0 2 DP_MSO_NUM_OF_SSTLINK 0 1 DP_MSO_SEC_STREAM_ENABLE 4 7 DP_MSO_SEC_ASP_ENABLE 8 11 DP_MSO_SEC_ATP_ENABLE 12 15 DP_MSO_SEC_AIP_ENABLE 16 19 DP_MSO_SEC_ACM_ENABLE 20 23 DP_MSO_SEC_GSP0_ENABLE 24 27 DP_MSO_SEC_GSP1_ENABLE 28 31 mmDP2_DP_MSO_CNTL1 0 0x2351 8 0 2 DP_MSO_SEC_GSP2_ENABLE 0 3 DP_MSO_SEC_GSP3_ENABLE 4 7 DP_MSO_SEC_GSP4_ENABLE 8 11 DP_MSO_SEC_GSP5_ENABLE 12 15 DP_MSO_SEC_GSP6_ENABLE 16 19 DP_MSO_SEC_GSP7_ENABLE 20 23 DP_MSO_SEC_MPG_ENABLE 24 27 DP_MSO_SEC_ISRC_ENABLE 28 31 mmDP2_DP_DSC_CNTL 0 0x2352 1 0 2 DP_DSC_EN 0 0 mmDP2_DP_SEC_CNTL2 0 0x2353 29 0 2 DP_SEC_GSP1_SEND 0 0 DP_SEC_GSP1_SEND_PENDING 1 1 DP_SEC_GSP1_SEND_DEADLINE_MISSED 2 2 DP_SEC_GSP1_SEND_ANY_LINE 3 3 DP_SEC_GSP2_SEND 4 4 DP_SEC_GSP2_SEND_PENDING 5 5 DP_SEC_GSP2_SEND_DEADLINE_MISSED 6 6 DP_SEC_GSP2_SEND_ANY_LINE 7 7 DP_SEC_GSP3_SEND 8 8 DP_SEC_GSP3_SEND_PENDING 9 9 DP_SEC_GSP3_SEND_DEADLINE_MISSED 10 10 DP_SEC_GSP3_SEND_ANY_LINE 11 11 DP_SEC_GSP4_SEND 12 12 DP_SEC_GSP4_SEND_PENDING 13 13 DP_SEC_GSP4_SEND_DEADLINE_MISSED 14 14 DP_SEC_GSP4_SEND_ANY_LINE 15 15 DP_SEC_GSP5_SEND 16 16 DP_SEC_GSP5_SEND_PENDING 17 17 DP_SEC_GSP5_SEND_DEADLINE_MISSED 18 18 DP_SEC_GSP5_SEND_ANY_LINE 19 19 DP_SEC_GSP6_SEND 20 20 DP_SEC_GSP6_SEND_PENDING 21 21 DP_SEC_GSP6_SEND_DEADLINE_MISSED 22 22 DP_SEC_GSP6_SEND_ANY_LINE 23 23 DP_SEC_GSP7_SEND 24 24 DP_SEC_GSP7_SEND_PENDING 25 25 DP_SEC_GSP7_SEND_DEADLINE_MISSED 26 26 DP_SEC_GSP7_SEND_ANY_LINE 27 27 DP_SEC_GSP7_PPS 28 28 mmDP2_DP_SEC_CNTL3 0 0x2354 2 0 2 DP_SEC_GSP1_LINE_NUM 0 15 DP_SEC_GSP2_LINE_NUM 16 31 mmDP2_DP_SEC_CNTL4 0 0x2355 2 0 2 DP_SEC_GSP3_LINE_NUM 0 15 DP_SEC_GSP4_LINE_NUM 16 31 mmDP2_DP_SEC_CNTL5 0 0x2356 2 0 2 DP_SEC_GSP5_LINE_NUM 0 15 DP_SEC_GSP6_LINE_NUM 16 31 mmDP2_DP_SEC_CNTL6 0 0x2357 1 0 2 DP_SEC_GSP7_LINE_NUM 0 15 mmDP2_DP_SEC_CNTL7 0 0x2358 8 0 2 DP_SEC_GSP0_SEND_ACTIVE 0 0 DP_SEC_GSP1_SEND_ACTIVE 4 4 DP_SEC_GSP2_SEND_ACTIVE 8 8 DP_SEC_GSP3_SEND_ACTIVE 12 12 DP_SEC_GSP4_SEND_ACTIVE 16 16 DP_SEC_GSP5_SEND_ACTIVE 20 20 DP_SEC_GSP6_SEND_ACTIVE 24 24 DP_SEC_GSP7_SEND_ACTIVE 28 28 mmDP2_DP_DB_CNTL 0 0x2359 5 0 2 DP_DB_PENDING 0 0 DP_DB_TAKEN 4 4 DP_DB_TAKEN_CLR 5 5 DP_DB_LOCK 8 8 DP_DB_DISABLE 12 12 mmDP2_DP_MSA_VBID_MISC 0 0x235a 6 0 2 DP_MSA_MISC1_STEREOSYNC_OVERRIDE 0 1 DP_MSA_MISC1_STEREOSYNC_OVERRIDE_EN 4 4 DP_VBID1_OVERRIDE 8 8 DP_VBID2_OVERRIDE 9 9 DP_VBID1_OVERRIDE_EN 12 12 DP_VBID2_OVERRIDE_EN 13 13 mmDIG3_DIG_FE_CNTL 0 0x2368 8 0 2 DIG_SOURCE_SELECT 0 2 DIG_STEREOSYNC_SELECT 4 6 DIG_STEREOSYNC_GATE_EN 8 8 DIG_START 10 10 DIG_DIGITAL_BYPASS_SELECT 12 14 DIG_SYMCLK_FE_ON 24 24 TMDS_PIXEL_ENCODING 28 28 TMDS_COLOR_FORMAT 30 31 mmDIG3_DIG_OUTPUT_CRC_CNTL 0 0x2369 3 0 2 DIG_OUTPUT_CRC_EN 0 0 DIG_OUTPUT_CRC_LINK_SEL 4 4 DIG_OUTPUT_CRC_DATA_SEL 8 9 mmDIG3_DIG_OUTPUT_CRC_RESULT 0 0x236a 1 0 2 DIG_OUTPUT_CRC_RESULT 0 29 mmDIG3_DIG_CLOCK_PATTERN 0 0x236b 1 0 2 DIG_CLOCK_PATTERN 0 9 mmDIG3_DIG_TEST_PATTERN 0 0x236c 6 0 2 DIG_TEST_PATTERN_OUT_EN 0 0 DIG_HALF_CLOCK_PATTERN_SEL 1 1 DIG_RANDOM_PATTERN_OUT_EN 4 4 DIG_RANDOM_PATTERN_RESET 5 5 DIG_TEST_PATTERN_EXTERNAL_RESET_EN 6 6 DIG_STATIC_TEST_PATTERN 16 25 mmDIG3_DIG_RANDOM_PATTERN_SEED 0 0x236d 2 0 2 DIG_RANDOM_PATTERN_SEED 0 23 DIG_RAN_PAT_DURING_DE_ONLY 24 24 mmDIG3_DIG_FIFO_STATUS 0 0x236e 11 0 2 DIG_FIFO_LEVEL_ERROR 0 0 DIG_FIFO_USE_OVERWRITE_LEVEL 1 1 DIG_FIFO_OVERWRITE_LEVEL 2 7 DIG_FIFO_ERROR_ACK 8 8 DIG_FIFO_CAL_AVERAGE_LEVEL 10 15 DIG_FIFO_MAXIMUM_LEVEL 16 20 DIG_FIFO_MINIMUM_LEVEL 22 25 DIG_FIFO_READ_CLOCK_SRC 26 26 DIG_FIFO_CALIBRATED 29 29 DIG_FIFO_FORCE_RECAL_AVERAGE 30 30 DIG_FIFO_FORCE_RECOMP_MINMAX 31 31 mmDIG3_HDMI_CONTROL 0 0x2371 9 0 2 HDMI_KEEPOUT_MODE 0 0 HDMI_DATA_SCRAMBLE_EN 1 1 HDMI_CLOCK_CHANNEL_RATE 2 2 HDMI_NO_EXTRA_NULL_PACKET_FILLED 3 3 HDMI_PACKET_GEN_VERSION 4 4 HDMI_ERROR_ACK 8 8 HDMI_ERROR_MASK 9 9 HDMI_DEEP_COLOR_ENABLE 24 24 HDMI_DEEP_COLOR_DEPTH 28 29 mmDIG3_HDMI_STATUS 0 0x2372 4 0 2 HDMI_ACTIVE_AVMUTE 0 0 HDMI_AUDIO_PACKET_ERROR 16 16 HDMI_VBI_PACKET_ERROR 20 20 HDMI_ERROR_INT 27 27 mmDIG3_HDMI_AUDIO_PACKET_CONTROL 0 0x2373 2 0 2 HDMI_AUDIO_DELAY_EN 4 5 HDMI_AUDIO_PACKETS_PER_LINE 16 20 mmDIG3_HDMI_ACR_PACKET_CONTROL 0 0x2374 7 0 2 HDMI_ACR_SEND 0 0 HDMI_ACR_CONT 1 1 HDMI_ACR_SELECT 4 5 HDMI_ACR_SOURCE 8 8 HDMI_ACR_AUTO_SEND 12 12 HDMI_ACR_N_MULTIPLE 16 18 HDMI_ACR_AUDIO_PRIORITY 31 31 mmDIG3_HDMI_VBI_PACKET_CONTROL 0 0x2375 6 0 2 HDMI_NULL_SEND 0 0 HDMI_GC_SEND 4 4 HDMI_GC_CONT 5 5 HDMI_ISRC_SEND 8 8 HDMI_ISRC_CONT 9 9 HDMI_ISRC_LINE 16 21 mmDIG3_HDMI_INFOFRAME_CONTROL0 0 0x2376 4 0 2 HDMI_AUDIO_INFO_SEND 4 4 HDMI_AUDIO_INFO_CONT 5 5 HDMI_MPEG_INFO_SEND 8 8 HDMI_MPEG_INFO_CONT 9 9 mmDIG3_HDMI_INFOFRAME_CONTROL1 0 0x2377 2 0 2 HDMI_AUDIO_INFO_LINE 8 13 HDMI_MPEG_INFO_LINE 16 21 mmDIG3_HDMI_GENERIC_PACKET_CONTROL0 0 0x2378 6 0 2 HDMI_GENERIC0_SEND 0 0 HDMI_GENERIC0_CONT 1 1 HDMI_GENERIC1_SEND 4 4 HDMI_GENERIC1_CONT 5 5 HDMI_GENERIC0_LINE 16 21 HDMI_GENERIC1_LINE 24 29 mmDIG3_AFMT_INTERRUPT_STATUS 0 0x2379 0 0 2 mmDIG3_HDMI_GC 0 0x237b 5 0 2 HDMI_GC_AVMUTE 0 0 HDMI_GC_AVMUTE_CONT 2 2 HDMI_DEFAULT_PHASE 4 4 HDMI_PACKING_PHASE 8 11 HDMI_PACKING_PHASE_OVERRIDE 12 12 mmDIG3_AFMT_AUDIO_PACKET_CONTROL2 0 0x237c 6 0 2 AFMT_AUDIO_LAYOUT_OVRD 0 0 AFMT_AUDIO_LAYOUT_SELECT 1 1 AFMT_AUDIO_CHANNEL_ENABLE 8 15 AFMT_DP_AUDIO_STREAM_ID 16 23 AFMT_HBR_ENABLE_OVRD 24 24 AFMT_60958_OSF_OVRD 28 28 mmDIG3_AFMT_ISRC1_0 0 0x237d 3 0 2 AFMT_ISRC_STATUS 0 2 AFMT_ISRC_CONTINUE 6 6 AFMT_ISRC_VALID 7 7 mmDIG3_AFMT_ISRC1_1 0 0x237e 4 0 2 AFMT_UPC_EAN_ISRC0 0 7 AFMT_UPC_EAN_ISRC1 8 15 AFMT_UPC_EAN_ISRC2 16 23 AFMT_UPC_EAN_ISRC3 24 31 mmDIG3_AFMT_ISRC1_2 0 0x237f 4 0 2 AFMT_UPC_EAN_ISRC4 0 7 AFMT_UPC_EAN_ISRC5 8 15 AFMT_UPC_EAN_ISRC6 16 23 AFMT_UPC_EAN_ISRC7 24 31 mmDIG3_AFMT_ISRC1_3 0 0x2380 4 0 2 AFMT_UPC_EAN_ISRC8 0 7 AFMT_UPC_EAN_ISRC9 8 15 AFMT_UPC_EAN_ISRC10 16 23 AFMT_UPC_EAN_ISRC11 24 31 mmDIG3_AFMT_ISRC1_4 0 0x2381 4 0 2 AFMT_UPC_EAN_ISRC12 0 7 AFMT_UPC_EAN_ISRC13 8 15 AFMT_UPC_EAN_ISRC14 16 23 AFMT_UPC_EAN_ISRC15 24 31 mmDIG3_AFMT_ISRC2_0 0 0x2382 4 0 2 AFMT_UPC_EAN_ISRC16 0 7 AFMT_UPC_EAN_ISRC17 8 15 AFMT_UPC_EAN_ISRC18 16 23 AFMT_UPC_EAN_ISRC19 24 31 mmDIG3_AFMT_ISRC2_1 0 0x2383 4 0 2 AFMT_UPC_EAN_ISRC20 0 7 AFMT_UPC_EAN_ISRC21 8 15 AFMT_UPC_EAN_ISRC22 16 23 AFMT_UPC_EAN_ISRC23 24 31 mmDIG3_AFMT_ISRC2_2 0 0x2384 4 0 2 AFMT_UPC_EAN_ISRC24 0 7 AFMT_UPC_EAN_ISRC25 8 15 AFMT_UPC_EAN_ISRC26 16 23 AFMT_UPC_EAN_ISRC27 24 31 mmDIG3_AFMT_ISRC2_3 0 0x2385 4 0 2 AFMT_UPC_EAN_ISRC28 0 7 AFMT_UPC_EAN_ISRC29 8 15 AFMT_UPC_EAN_ISRC30 16 23 AFMT_UPC_EAN_ISRC31 24 31 mmDIG3_HDMI_GENERIC_PACKET_CONTROL2 0 0x2386 6 0 2 HDMI_GENERIC4_SEND 0 0 HDMI_GENERIC4_CONT 1 1 HDMI_GENERIC5_SEND 4 4 HDMI_GENERIC5_CONT 5 5 HDMI_GENERIC4_LINE 16 21 HDMI_GENERIC5_LINE 24 29 mmDIG3_HDMI_GENERIC_PACKET_CONTROL3 0 0x2387 6 0 2 HDMI_GENERIC6_SEND 0 0 HDMI_GENERIC6_CONT 1 1 HDMI_GENERIC7_SEND 4 4 HDMI_GENERIC7_CONT 5 5 HDMI_GENERIC6_LINE 16 21 HDMI_GENERIC7_LINE 24 29 mmDIG3_HDMI_DB_CONTROL 0 0x2388 5 0 2 HDMI_DB_PENDING 0 0 HDMI_DB_TAKEN 4 4 HDMI_DB_TAKEN_CLR 5 5 HDMI_DB_LOCK 8 8 HDMI_DB_DISABLE 12 12 mmDIG3_AFMT_MPEG_INFO0 0 0x238a 4 0 2 AFMT_MPEG_INFO_CHECKSUM 0 7 AFMT_MPEG_INFO_MB0 8 15 AFMT_MPEG_INFO_MB1 16 23 AFMT_MPEG_INFO_MB2 24 31 mmDIG3_AFMT_MPEG_INFO1 0 0x238b 3 0 2 AFMT_MPEG_INFO_MB3 0 7 AFMT_MPEG_INFO_MF 8 9 AFMT_MPEG_INFO_FR 12 12 mmDIG3_AFMT_GENERIC_HDR 0 0x238c 4 0 2 AFMT_GENERIC_HB0 0 7 AFMT_GENERIC_HB1 8 15 AFMT_GENERIC_HB2 16 23 AFMT_GENERIC_HB3 24 31 mmDIG3_AFMT_GENERIC_0 0 0x238d 4 0 2 AFMT_GENERIC_BYTE0 0 7 AFMT_GENERIC_BYTE1 8 15 AFMT_GENERIC_BYTE2 16 23 AFMT_GENERIC_BYTE3 24 31 mmDIG3_AFMT_GENERIC_1 0 0x238e 4 0 2 AFMT_GENERIC_BYTE4 0 7 AFMT_GENERIC_BYTE5 8 15 AFMT_GENERIC_BYTE6 16 23 AFMT_GENERIC_BYTE7 24 31 mmDIG3_AFMT_GENERIC_2 0 0x238f 4 0 2 AFMT_GENERIC_BYTE8 0 7 AFMT_GENERIC_BYTE9 8 15 AFMT_GENERIC_BYTE10 16 23 AFMT_GENERIC_BYTE11 24 31 mmDIG3_AFMT_GENERIC_3 0 0x2390 4 0 2 AFMT_GENERIC_BYTE12 0 7 AFMT_GENERIC_BYTE13 8 15 AFMT_GENERIC_BYTE14 16 23 AFMT_GENERIC_BYTE15 24 31 mmDIG3_AFMT_GENERIC_4 0 0x2391 4 0 2 AFMT_GENERIC_BYTE16 0 7 AFMT_GENERIC_BYTE17 8 15 AFMT_GENERIC_BYTE18 16 23 AFMT_GENERIC_BYTE19 24 31 mmDIG3_AFMT_GENERIC_5 0 0x2392 4 0 2 AFMT_GENERIC_BYTE20 0 7 AFMT_GENERIC_BYTE21 8 15 AFMT_GENERIC_BYTE22 16 23 AFMT_GENERIC_BYTE23 24 31 mmDIG3_AFMT_GENERIC_6 0 0x2393 4 0 2 AFMT_GENERIC_BYTE24 0 7 AFMT_GENERIC_BYTE25 8 15 AFMT_GENERIC_BYTE26 16 23 AFMT_GENERIC_BYTE27 24 31 mmDIG3_AFMT_GENERIC_7 0 0x2394 4 0 2 AFMT_GENERIC_BYTE28 0 7 AFMT_GENERIC_BYTE29 8 15 AFMT_GENERIC_BYTE30 16 23 AFMT_GENERIC_BYTE31 24 31 mmDIG3_HDMI_GENERIC_PACKET_CONTROL1 0 0x2395 6 0 2 HDMI_GENERIC2_SEND 0 0 HDMI_GENERIC2_CONT 1 1 HDMI_GENERIC3_SEND 4 4 HDMI_GENERIC3_CONT 5 5 HDMI_GENERIC2_LINE 16 21 HDMI_GENERIC3_LINE 24 29 mmDIG3_HDMI_ACR_32_0 0 0x2396 1 0 2 HDMI_ACR_CTS_32 12 31 mmDIG3_HDMI_ACR_32_1 0 0x2397 1 0 2 HDMI_ACR_N_32 0 19 mmDIG3_HDMI_ACR_44_0 0 0x2398 1 0 2 HDMI_ACR_CTS_44 12 31 mmDIG3_HDMI_ACR_44_1 0 0x2399 1 0 2 HDMI_ACR_N_44 0 19 mmDIG3_HDMI_ACR_48_0 0 0x239a 1 0 2 HDMI_ACR_CTS_48 12 31 mmDIG3_HDMI_ACR_48_1 0 0x239b 1 0 2 HDMI_ACR_N_48 0 19 mmDIG3_HDMI_ACR_STATUS_0 0 0x239c 1 0 2 HDMI_ACR_CTS 12 31 mmDIG3_HDMI_ACR_STATUS_1 0 0x239d 1 0 2 HDMI_ACR_N 0 19 mmDIG3_AFMT_AUDIO_INFO0 0 0x239e 5 0 2 AFMT_AUDIO_INFO_CHECKSUM 0 7 AFMT_AUDIO_INFO_CC 8 10 AFMT_AUDIO_INFO_CT 11 14 AFMT_AUDIO_INFO_CHECKSUM_OFFSET 16 23 AFMT_AUDIO_INFO_CXT 24 28 mmDIG3_AFMT_AUDIO_INFO1 0 0x239f 4 0 2 AFMT_AUDIO_INFO_CA 0 7 AFMT_AUDIO_INFO_LSV 11 14 AFMT_AUDIO_INFO_DM_INH 15 15 AFMT_AUDIO_INFO_LFEPBL 16 17 mmDIG3_AFMT_60958_0 0 0x23a0 10 0 2 AFMT_60958_CS_A 0 0 AFMT_60958_CS_B 1 1 AFMT_60958_CS_C 2 2 AFMT_60958_CS_D 3 5 AFMT_60958_CS_MODE 6 7 AFMT_60958_CS_CATEGORY_CODE 8 15 AFMT_60958_CS_SOURCE_NUMBER 16 19 AFMT_60958_CS_CHANNEL_NUMBER_L 20 23 AFMT_60958_CS_SAMPLING_FREQUENCY 24 27 AFMT_60958_CS_CLOCK_ACCURACY 28 29 mmDIG3_AFMT_60958_1 0 0x23a1 5 0 2 AFMT_60958_CS_WORD_LENGTH 0 3 AFMT_60958_CS_ORIGINAL_SAMPLING_FREQUENCY 4 7 AFMT_60958_VALID_L 16 16 AFMT_60958_VALID_R 18 18 AFMT_60958_CS_CHANNEL_NUMBER_R 20 23 mmDIG3_AFMT_AUDIO_CRC_CONTROL 0 0x23a2 5 0 2 AFMT_AUDIO_CRC_EN 0 0 AFMT_AUDIO_CRC_CONT 4 4 AFMT_AUDIO_CRC_SOURCE 8 8 AFMT_AUDIO_CRC_CH_SEL 12 15 AFMT_AUDIO_CRC_COUNT 16 31 mmDIG3_AFMT_RAMP_CONTROL0 0 0x23a3 2 0 2 AFMT_RAMP_MAX_COUNT 0 23 AFMT_RAMP_DATA_SIGN 31 31 mmDIG3_AFMT_RAMP_CONTROL1 0 0x23a4 2 0 2 AFMT_RAMP_MIN_COUNT 0 23 AFMT_AUDIO_TEST_CH_DISABLE 24 31 mmDIG3_AFMT_RAMP_CONTROL2 0 0x23a5 1 0 2 AFMT_RAMP_INC_COUNT 0 23 mmDIG3_AFMT_RAMP_CONTROL3 0 0x23a6 1 0 2 AFMT_RAMP_DEC_COUNT 0 23 mmDIG3_AFMT_60958_2 0 0x23a7 6 0 2 AFMT_60958_CS_CHANNEL_NUMBER_2 0 3 AFMT_60958_CS_CHANNEL_NUMBER_3 4 7 AFMT_60958_CS_CHANNEL_NUMBER_4 8 11 AFMT_60958_CS_CHANNEL_NUMBER_5 12 15 AFMT_60958_CS_CHANNEL_NUMBER_6 16 19 AFMT_60958_CS_CHANNEL_NUMBER_7 20 23 mmDIG3_AFMT_AUDIO_CRC_RESULT 0 0x23a8 2 0 2 AFMT_AUDIO_CRC_DONE 0 0 AFMT_AUDIO_CRC 8 31 mmDIG3_AFMT_STATUS 0 0x23a9 4 0 2 AFMT_AUDIO_ENABLE 4 4 AFMT_AZ_HBR_ENABLE 8 8 AFMT_AUDIO_FIFO_OVERFLOW 24 24 AFMT_AZ_AUDIO_ENABLE_CHG 30 30 mmDIG3_AFMT_AUDIO_PACKET_CONTROL 0 0x23aa 8 0 2 AFMT_AUDIO_SAMPLE_SEND 0 0 AFMT_RESET_FIFO_WHEN_AUDIO_DIS 11 11 AFMT_AUDIO_TEST_EN 12 12 AFMT_AUDIO_TEST_MODE 14 14 AFMT_AUDIO_FIFO_OVERFLOW_ACK 23 23 AFMT_AUDIO_CHANNEL_SWAP 24 24 AFMT_60958_CS_UPDATE 26 26 AFMT_AZ_AUDIO_ENABLE_CHG_ACK 30 30 mmDIG3_AFMT_VBI_PACKET_CONTROL 0 0x23ab 4 0 2 AFMT_GENERIC_LOCK_STATUS 8 8 AFMT_GENERIC_CONFLICT 16 16 AFMT_GENERIC_CONFLICT_CLR 17 17 AFMT_GENERIC_INDEX 28 31 mmDIG3_AFMT_INFOFRAME_CONTROL0 0 0x23ac 3 0 2 AFMT_AUDIO_INFO_SOURCE 6 6 AFMT_AUDIO_INFO_UPDATE 7 7 AFMT_MPEG_INFO_UPDATE 10 10 mmDIG3_AFMT_AUDIO_SRC_CONTROL 0 0x23ad 1 0 2 AFMT_AUDIO_SRC_SELECT 0 2 mmDIG3_DIG_BE_CNTL 0 0x23af 5 0 2 DIG_DUAL_LINK_ENABLE 0 0 DIG_SWAP 1 1 DIG_FE_SOURCE_SELECT 8 14 DIG_MODE 16 18 DIG_HPD_SELECT 28 30 mmDIG3_DIG_BE_EN_CNTL 0 0x23b0 2 0 2 DIG_ENABLE 0 0 DIG_SYMCLK_BE_ON 8 8 mmDIG3_TMDS_CNTL 0 0x23d3 1 0 2 TMDS_SYNC_PHASE 0 0 mmDIG3_TMDS_CONTROL_CHAR 0 0x23d4 4 0 2 TMDS_CONTROL_CHAR0_OUT_EN 0 0 TMDS_CONTROL_CHAR1_OUT_EN 1 1 TMDS_CONTROL_CHAR2_OUT_EN 2 2 TMDS_CONTROL_CHAR3_OUT_EN 3 3 mmDIG3_TMDS_CONTROL0_FEEDBACK 0 0x23d5 2 0 2 TMDS_CONTROL0_FEEDBACK_SELECT 0 1 TMDS_CONTROL0_FEEDBACK_DELAY 8 9 mmDIG3_TMDS_STEREOSYNC_CTL_SEL 0 0x23d6 1 0 2 TMDS_STEREOSYNC_CTL_SEL 0 1 mmDIG3_TMDS_SYNC_CHAR_PATTERN_0_1 0 0x23d7 2 0 2 TMDS_SYNC_CHAR_PATTERN0 0 9 TMDS_SYNC_CHAR_PATTERN1 16 25 mmDIG3_TMDS_SYNC_CHAR_PATTERN_2_3 0 0x23d8 2 0 2 TMDS_SYNC_CHAR_PATTERN2 0 9 TMDS_SYNC_CHAR_PATTERN3 16 25 mmDIG3_TMDS_CTL_BITS 0 0x23da 4 0 2 TMDS_CTL0 0 0 TMDS_CTL1 8 8 TMDS_CTL2 16 16 TMDS_CTL3 24 24 mmDIG3_TMDS_DCBALANCER_CONTROL 0 0x23db 4 0 2 TMDS_DCBALANCER_EN 0 0 TMDS_DCBALANCER_TEST_EN 8 8 TMDS_DCBALANCER_TEST_IN 16 19 TMDS_DCBALANCER_FORCE 24 24 mmDIG3_TMDS_CTL0_1_GEN_CNTL 0 0x23dd 15 0 2 TMDS_CTL0_DATA_SEL 0 3 TMDS_CTL0_DATA_DELAY 4 6 TMDS_CTL0_DATA_INVERT 7 7 TMDS_CTL0_DATA_MODULATION 8 9 TMDS_CTL0_USE_FEEDBACK_PATH 10 10 TMDS_CTL0_FB_SYNC_CONT 11 11 TMDS_CTL0_PATTERN_OUT_EN 12 12 TMDS_CTL1_DATA_SEL 16 19 TMDS_CTL1_DATA_DELAY 20 22 TMDS_CTL1_DATA_INVERT 23 23 TMDS_CTL1_DATA_MODULATION 24 25 TMDS_CTL1_USE_FEEDBACK_PATH 26 26 TMDS_CTL1_FB_SYNC_CONT 27 27 TMDS_CTL1_PATTERN_OUT_EN 28 28 TMDS_2BIT_COUNTER_EN 31 31 mmDIG3_TMDS_CTL2_3_GEN_CNTL 0 0x23de 14 0 2 TMDS_CTL2_DATA_SEL 0 3 TMDS_CTL2_DATA_DELAY 4 6 TMDS_CTL2_DATA_INVERT 7 7 TMDS_CTL2_DATA_MODULATION 8 9 TMDS_CTL2_USE_FEEDBACK_PATH 10 10 TMDS_CTL2_FB_SYNC_CONT 11 11 TMDS_CTL2_PATTERN_OUT_EN 12 12 TMDS_CTL3_DATA_SEL 16 19 TMDS_CTL3_DATA_DELAY 20 22 TMDS_CTL3_DATA_INVERT 23 23 TMDS_CTL3_DATA_MODULATION 24 25 TMDS_CTL3_USE_FEEDBACK_PATH 26 26 TMDS_CTL3_FB_SYNC_CONT 27 27 TMDS_CTL3_PATTERN_OUT_EN 28 28 mmDIG3_DIG_VERSION 0 0x23e0 1 0 2 DIG_TYPE 0 0 mmDIG3_DIG_LANE_ENABLE 0 0x23e1 5 0 2 DIG_LANE0EN 0 0 DIG_LANE1EN 1 1 DIG_LANE2EN 2 2 DIG_LANE3EN 3 3 DIG_CLK_EN 8 8 mmDIG3_AFMT_CNTL 0 0x23e6 2 0 2 AFMT_AUDIO_CLOCK_EN 0 0 AFMT_AUDIO_CLOCK_ON 8 8 mmDIG3_AFMT_VBI_PACKET_CONTROL1 0 0x23e7 32 0 2 AFMT_GENERIC0_FRAME_UPDATE 0 0 AFMT_GENERIC0_FRAME_UPDATE_PENDING 1 1 AFMT_GENERIC0_IMMEDIATE_UPDATE 2 2 AFMT_GENERIC0_IMMEDIATE_UPDATE_PENDING 3 3 AFMT_GENERIC1_FRAME_UPDATE 4 4 AFMT_GENERIC1_FRAME_UPDATE_PENDING 5 5 AFMT_GENERIC1_IMMEDIATE_UPDATE 6 6 AFMT_GENERIC1_IMMEDIATE_UPDATE_PENDING 7 7 AFMT_GENERIC2_FRAME_UPDATE 8 8 AFMT_GENERIC2_FRAME_UPDATE_PENDING 9 9 AFMT_GENERIC2_IMMEDIATE_UPDATE 10 10 AFMT_GENERIC2_IMMEDIATE_UPDATE_PENDING 11 11 AFMT_GENERIC3_FRAME_UPDATE 12 12 AFMT_GENERIC3_FRAME_UPDATE_PENDING 13 13 AFMT_GENERIC3_IMMEDIATE_UPDATE 14 14 AFMT_GENERIC3_IMMEDIATE_UPDATE_PENDING 15 15 AFMT_GENERIC4_FRAME_UPDATE 16 16 AFMT_GENERIC4_FRAME_UPDATE_PENDING 17 17 AFMT_GENERIC4_IMMEDIATE_UPDATE 18 18 AFMT_GENERIC4_IMMEDIATE_UPDATE_PENDING 19 19 AFMT_GENERIC5_FRAME_UPDATE 20 20 AFMT_GENERIC5_FRAME_UPDATE_PENDING 21 21 AFMT_GENERIC5_IMMEDIATE_UPDATE 22 22 AFMT_GENERIC5_IMMEDIATE_UPDATE_PENDING 23 23 AFMT_GENERIC6_FRAME_UPDATE 24 24 AFMT_GENERIC6_FRAME_UPDATE_PENDING 25 25 AFMT_GENERIC6_IMMEDIATE_UPDATE 26 26 AFMT_GENERIC6_IMMEDIATE_UPDATE_PENDING 27 27 AFMT_GENERIC7_FRAME_UPDATE 28 28 AFMT_GENERIC7_FRAME_UPDATE_PENDING 29 29 AFMT_GENERIC7_IMMEDIATE_UPDATE 30 30 AFMT_GENERIC7_IMMEDIATE_UPDATE_PENDING 31 31 mmDP3_DP_LINK_CNTL 0 0x2408 3 0 2 DP_LINK_TRAINING_COMPLETE 4 4 DP_LINK_STATUS 8 8 DP_EMBEDDED_PANEL_MODE 17 17 mmDP3_DP_PIXEL_FORMAT 0 0x2409 3 0 2 DP_PIXEL_ENCODING 0 2 DP_COMPONENT_DEPTH 24 26 DP_PIXEL_COMBINE 28 29 mmDP3_DP_MSA_COLORIMETRY 0 0x240a 1 0 2 DP_MSA_MISC0 24 31 mmDP3_DP_CONFIG 0 0x240b 1 0 2 DP_UDI_LANES 0 1 mmDP3_DP_VID_STREAM_CNTL 0 0x240c 4 0 2 DP_VID_STREAM_ENABLE 0 0 DP_VID_STREAM_DIS_DEFER 8 9 DP_VID_STREAM_STATUS 16 16 DP_VID_STREAM_CHANGE_KEEPOUT 20 20 mmDP3_DP_STEER_FIFO 0 0x240d 7 0 2 DP_STEER_FIFO_RESET 0 0 DP_STEER_OVERFLOW_FLAG 4 4 DP_STEER_OVERFLOW_INT 5 5 DP_STEER_OVERFLOW_ACK 6 6 DP_STEER_OVERFLOW_MASK 7 7 DP_TU_OVERFLOW_FLAG 8 8 DP_TU_OVERFLOW_ACK 12 12 mmDP3_DP_MSA_MISC 0 0x240e 4 0 2 DP_MSA_MISC1 0 7 DP_MSA_MISC2 8 15 DP_MSA_MISC3 16 23 DP_MSA_MISC4 24 31 mmDP3_DP_VID_TIMING 0 0x2410 5 0 2 DP_VID_M_N_DOUBLE_BUFFER_MODE 4 4 DP_VID_M_N_GEN_EN 8 8 DP_VID_N_MUL 10 11 DP_VID_M_DIV 12 13 DP_VID_N_DIV 24 31 mmDP3_DP_VID_N 0 0x2411 1 0 2 DP_VID_N 0 23 mmDP3_DP_VID_M 0 0x2412 1 0 2 DP_VID_M 0 23 mmDP3_DP_LINK_FRAMING_CNTL 0 0x2413 3 0 2 DP_IDLE_BS_INTERVAL 0 17 DP_VBID_DISABLE 24 24 DP_VID_ENHANCED_FRAME_MODE 28 28 mmDP3_DP_HBR2_EYE_PATTERN 0 0x2414 1 0 2 DP_HBR2_EYE_PATTERN_ENABLE 0 0 mmDP3_DP_VID_MSA_VBID 0 0x2415 2 0 2 DP_VID_MSA_LOCATION 0 11 DP_VID_VBID_FIELD_POL 24 24 mmDP3_DP_VID_INTERRUPT_CNTL 0 0x2416 3 0 2 DP_VID_STREAM_DISABLE_INT 0 0 DP_VID_STREAM_DISABLE_ACK 1 1 DP_VID_STREAM_DISABLE_MASK 2 2 mmDP3_DP_DPHY_CNTL 0 0x2417 6 0 2 DPHY_ATEST_SEL_LANE0 0 0 DPHY_ATEST_SEL_LANE1 1 1 DPHY_ATEST_SEL_LANE2 2 2 DPHY_ATEST_SEL_LANE3 3 3 DPHY_BYPASS 16 16 DPHY_SKEW_BYPASS 24 24 mmDP3_DP_DPHY_TRAINING_PATTERN_SEL 0 0x2418 1 0 2 DPHY_TRAINING_PATTERN_SEL 0 1 mmDP3_DP_DPHY_SYM0 0 0x2419 3 0 2 DPHY_SYM1 0 9 DPHY_SYM2 10 19 DPHY_SYM3 20 29 mmDP3_DP_DPHY_SYM1 0 0x241a 3 0 2 DPHY_SYM4 0 9 DPHY_SYM5 10 19 DPHY_SYM6 20 29 mmDP3_DP_DPHY_SYM2 0 0x241b 2 0 2 DPHY_SYM7 0 9 DPHY_SYM8 10 19 mmDP3_DP_DPHY_8B10B_CNTL 0 0x241c 3 0 2 DPHY_8B10B_RESET 8 8 DPHY_8B10B_EXT_DISP 16 16 DPHY_8B10B_CUR_DISP 24 24 mmDP3_DP_DPHY_PRBS_CNTL 0 0x241d 3 0 2 DPHY_PRBS_EN 0 0 DPHY_PRBS_SEL 4 5 DPHY_PRBS_SEED 8 30 mmDP3_DP_DPHY_SCRAM_CNTL 0 0x241e 4 0 2 DPHY_SCRAMBLER_DIS 0 0 DPHY_SCRAMBLER_ADVANCE 4 4 DPHY_SCRAMBLER_BS_COUNT 8 17 DPHY_SCRAMBLER_KCODE 24 24 mmDP3_DP_DPHY_CRC_EN 0 0x241f 3 0 2 DPHY_CRC_EN 0 0 DPHY_CRC_CONT_EN 4 4 DPHY_CRC_RESULT_VALID 8 8 mmDP3_DP_DPHY_CRC_CNTL 0 0x2420 3 0 2 DPHY_CRC_FIELD 0 0 DPHY_CRC_SEL 4 5 DPHY_CRC_MASK 16 23 mmDP3_DP_DPHY_CRC_RESULT 0 0x2421 4 0 2 DPHY_CRC_RESULT 0 7 DPHY_CRC_RESULT1 8 15 DPHY_CRC_RESULT2 16 23 DPHY_CRC_RESULT3 24 31 mmDP3_DP_DPHY_CRC_MST_CNTL 0 0x2422 2 0 2 DPHY_CRC_MST_FIRST_SLOT 0 5 DPHY_CRC_MST_LAST_SLOT 8 13 mmDP3_DP_DPHY_CRC_MST_STATUS 0 0x2423 3 0 2 DPHY_CRC_MST_PHASE_LOCK 0 0 DPHY_CRC_MST_PHASE_ERROR 8 8 DPHY_CRC_MST_PHASE_ERROR_ACK 16 16 mmDP3_DP_DPHY_FAST_TRAINING 0 0x2424 5 0 2 DPHY_RX_FAST_TRAINING_CAPABLE 0 0 DPHY_SW_FAST_TRAINING_START 1 1 DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN 2 2 DPHY_FAST_TRAINING_TP1_TIME 8 19 DPHY_FAST_TRAINING_TP2_TIME 20 31 mmDP3_DP_DPHY_FAST_TRAINING_STATUS 0 0x2425 4 0 2 DPHY_FAST_TRAINING_STATE 0 2 DPHY_FAST_TRAINING_COMPLETE_OCCURRED 4 4 DPHY_FAST_TRAINING_COMPLETE_MASK 8 8 DPHY_FAST_TRAINING_COMPLETE_ACK 12 12 mmDP3_DP_SEC_CNTL 0 0x242b 14 0 2 DP_SEC_STREAM_ENABLE 0 0 DP_SEC_ASP_ENABLE 4 4 DP_SEC_ATP_ENABLE 8 8 DP_SEC_AIP_ENABLE 12 12 DP_SEC_ACM_ENABLE 16 16 DP_SEC_GSP0_ENABLE 20 20 DP_SEC_GSP1_ENABLE 21 21 DP_SEC_GSP2_ENABLE 22 22 DP_SEC_GSP3_ENABLE 23 23 DP_SEC_GSP4_ENABLE 24 24 DP_SEC_GSP5_ENABLE 25 25 DP_SEC_GSP6_ENABLE 26 26 DP_SEC_GSP7_ENABLE 27 27 DP_SEC_MPG_ENABLE 28 28 mmDP3_DP_SEC_CNTL1 0 0x242c 7 0 2 DP_SEC_ISRC_ENABLE 0 0 DP_SEC_GSP0_PRIORITY 4 4 DP_SEC_GSP0_SEND 5 5 DP_SEC_GSP0_SEND_PENDING 6 6 DP_SEC_GSP0_SEND_DEADLINE_MISSED 7 7 DP_SEC_GSP0_SEND_ANY_LINE 8 8 DP_SEC_GSP0_LINE_NUM 16 31 mmDP3_DP_SEC_FRAMING1 0 0x242d 2 0 2 DP_SEC_FRAME_START_LOCATION 0 11 DP_SEC_VBLANK_TRANSMIT_WIDTH 16 31 mmDP3_DP_SEC_FRAMING2 0 0x242e 2 0 2 DP_SEC_START_POSITION 0 15 DP_SEC_HBLANK_TRANSMIT_WIDTH 16 31 mmDP3_DP_SEC_FRAMING3 0 0x242f 2 0 2 DP_SEC_IDLE_FRAME_SIZE 0 13 DP_SEC_IDLE_TRANSMIT_WIDTH 16 31 mmDP3_DP_SEC_FRAMING4 0 0x2430 4 0 2 DP_SEC_COLLISION_STATUS 20 20 DP_SEC_COLLISION_ACK 24 24 DP_SEC_AUDIO_MUTE 28 28 DP_SEC_AUDIO_MUTE_STATUS 29 29 mmDP3_DP_SEC_AUD_N 0 0x2431 1 0 2 DP_SEC_AUD_N 0 23 mmDP3_DP_SEC_AUD_N_READBACK 0 0x2432 1 0 2 DP_SEC_AUD_N_READBACK 0 23 mmDP3_DP_SEC_AUD_M 0 0x2433 1 0 2 DP_SEC_AUD_M 0 23 mmDP3_DP_SEC_AUD_M_READBACK 0 0x2434 1 0 2 DP_SEC_AUD_M_READBACK 0 23 mmDP3_DP_SEC_TIMESTAMP 0 0x2435 1 0 2 DP_SEC_TIMESTAMP_MODE 0 0 mmDP3_DP_SEC_PACKET_CNTL 0 0x2436 4 0 2 DP_SEC_ASP_CODING_TYPE 1 3 DP_SEC_ASP_PRIORITY 4 4 DP_SEC_VERSION 8 13 DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE 16 16 mmDP3_DP_MSE_RATE_CNTL 0 0x2437 2 0 2 DP_MSE_RATE_Y 0 25 DP_MSE_RATE_X 26 31 mmDP3_DP_MSE_RATE_UPDATE 0 0x2439 1 0 2 DP_MSE_RATE_UPDATE_PENDING 0 0 mmDP3_DP_MSE_SAT0 0 0x243a 4 0 2 DP_MSE_SAT_SRC0 0 2 DP_MSE_SAT_SLOT_COUNT0 8 13 DP_MSE_SAT_SRC1 16 18 DP_MSE_SAT_SLOT_COUNT1 24 29 mmDP3_DP_MSE_SAT1 0 0x243b 4 0 2 DP_MSE_SAT_SRC2 0 2 DP_MSE_SAT_SLOT_COUNT2 8 13 DP_MSE_SAT_SRC3 16 18 DP_MSE_SAT_SLOT_COUNT3 24 29 mmDP3_DP_MSE_SAT2 0 0x243c 4 0 2 DP_MSE_SAT_SRC4 0 2 DP_MSE_SAT_SLOT_COUNT4 8 13 DP_MSE_SAT_SRC5 16 18 DP_MSE_SAT_SLOT_COUNT5 24 29 mmDP3_DP_MSE_SAT_UPDATE 0 0x243d 2 0 2 DP_MSE_SAT_UPDATE 0 1 DP_MSE_16_MTP_KEEPOUT 8 8 mmDP3_DP_MSE_LINK_TIMING 0 0x243e 2 0 2 DP_MSE_LINK_FRAME 0 9 DP_MSE_LINK_LINE 16 17 mmDP3_DP_MSE_MISC_CNTL 0 0x243f 3 0 2 DP_MSE_BLANK_CODE 0 0 DP_MSE_TIMESTAMP_MODE 4 4 DP_MSE_ZERO_ENCODER 8 8 mmDP3_DP_DPHY_BS_SR_SWAP_CNTL 0 0x2444 3 0 2 DPHY_LOAD_BS_COUNT 0 9 DPHY_BS_SR_SWAP_DONE 15 15 DPHY_LOAD_BS_COUNT_START 16 16 mmDP3_DP_DPHY_HBR2_PATTERN_CONTROL 0 0x2445 1 0 2 DP_DPHY_HBR2_PATTERN_CONTROL 0 2 mmDP3_DP_MSE_SAT0_STATUS 0 0x2447 4 0 2 DP_MSE_SAT_SRC0_STATUS 0 2 DP_MSE_SAT_SLOT_COUNT0_STATUS 8 13 DP_MSE_SAT_SRC1_STATUS 16 18 DP_MSE_SAT_SLOT_COUNT1_STATUS 24 29 mmDP3_DP_MSE_SAT1_STATUS 0 0x2448 4 0 2 DP_MSE_SAT_SRC2_STATUS 0 2 DP_MSE_SAT_SLOT_COUNT2_STATUS 8 13 DP_MSE_SAT_SRC3_STATUS 16 18 DP_MSE_SAT_SLOT_COUNT3_STATUS 24 29 mmDP3_DP_MSE_SAT2_STATUS 0 0x2449 4 0 2 DP_MSE_SAT_SRC4_STATUS 0 2 DP_MSE_SAT_SLOT_COUNT4_STATUS 8 13 DP_MSE_SAT_SRC5_STATUS 16 18 DP_MSE_SAT_SLOT_COUNT5_STATUS 24 29 mmDP3_DP_MSA_TIMING_PARAM1 0 0x244c 2 0 2 DP_MSA_VTOTAL 0 15 DP_MSA_HTOTAL 16 31 mmDP3_DP_MSA_TIMING_PARAM2 0 0x244d 2 0 2 DP_MSA_VSTART 0 15 DP_MSA_HSTART 16 31 mmDP3_DP_MSA_TIMING_PARAM3 0 0x244e 4 0 2 DP_MSA_VSYNCWIDTH 0 14 DP_MSA_VSYNCPOLARITY 15 15 DP_MSA_HSYNCWIDTH 16 30 DP_MSA_HSYNCPOLARITY 31 31 mmDP3_DP_MSA_TIMING_PARAM4 0 0x244f 2 0 2 DP_MSA_VHEIGHT 0 15 DP_MSA_HWIDTH 16 31 mmDP3_DP_MSO_CNTL 0 0x2450 8 0 2 DP_MSO_NUM_OF_SSTLINK 0 1 DP_MSO_SEC_STREAM_ENABLE 4 7 DP_MSO_SEC_ASP_ENABLE 8 11 DP_MSO_SEC_ATP_ENABLE 12 15 DP_MSO_SEC_AIP_ENABLE 16 19 DP_MSO_SEC_ACM_ENABLE 20 23 DP_MSO_SEC_GSP0_ENABLE 24 27 DP_MSO_SEC_GSP1_ENABLE 28 31 mmDP3_DP_MSO_CNTL1 0 0x2451 8 0 2 DP_MSO_SEC_GSP2_ENABLE 0 3 DP_MSO_SEC_GSP3_ENABLE 4 7 DP_MSO_SEC_GSP4_ENABLE 8 11 DP_MSO_SEC_GSP5_ENABLE 12 15 DP_MSO_SEC_GSP6_ENABLE 16 19 DP_MSO_SEC_GSP7_ENABLE 20 23 DP_MSO_SEC_MPG_ENABLE 24 27 DP_MSO_SEC_ISRC_ENABLE 28 31 mmDP3_DP_DSC_CNTL 0 0x2452 1 0 2 DP_DSC_EN 0 0 mmDP3_DP_SEC_CNTL2 0 0x2453 29 0 2 DP_SEC_GSP1_SEND 0 0 DP_SEC_GSP1_SEND_PENDING 1 1 DP_SEC_GSP1_SEND_DEADLINE_MISSED 2 2 DP_SEC_GSP1_SEND_ANY_LINE 3 3 DP_SEC_GSP2_SEND 4 4 DP_SEC_GSP2_SEND_PENDING 5 5 DP_SEC_GSP2_SEND_DEADLINE_MISSED 6 6 DP_SEC_GSP2_SEND_ANY_LINE 7 7 DP_SEC_GSP3_SEND 8 8 DP_SEC_GSP3_SEND_PENDING 9 9 DP_SEC_GSP3_SEND_DEADLINE_MISSED 10 10 DP_SEC_GSP3_SEND_ANY_LINE 11 11 DP_SEC_GSP4_SEND 12 12 DP_SEC_GSP4_SEND_PENDING 13 13 DP_SEC_GSP4_SEND_DEADLINE_MISSED 14 14 DP_SEC_GSP4_SEND_ANY_LINE 15 15 DP_SEC_GSP5_SEND 16 16 DP_SEC_GSP5_SEND_PENDING 17 17 DP_SEC_GSP5_SEND_DEADLINE_MISSED 18 18 DP_SEC_GSP5_SEND_ANY_LINE 19 19 DP_SEC_GSP6_SEND 20 20 DP_SEC_GSP6_SEND_PENDING 21 21 DP_SEC_GSP6_SEND_DEADLINE_MISSED 22 22 DP_SEC_GSP6_SEND_ANY_LINE 23 23 DP_SEC_GSP7_SEND 24 24 DP_SEC_GSP7_SEND_PENDING 25 25 DP_SEC_GSP7_SEND_DEADLINE_MISSED 26 26 DP_SEC_GSP7_SEND_ANY_LINE 27 27 DP_SEC_GSP7_PPS 28 28 mmDP3_DP_SEC_CNTL3 0 0x2454 2 0 2 DP_SEC_GSP1_LINE_NUM 0 15 DP_SEC_GSP2_LINE_NUM 16 31 mmDP3_DP_SEC_CNTL4 0 0x2455 2 0 2 DP_SEC_GSP3_LINE_NUM 0 15 DP_SEC_GSP4_LINE_NUM 16 31 mmDP3_DP_SEC_CNTL5 0 0x2456 2 0 2 DP_SEC_GSP5_LINE_NUM 0 15 DP_SEC_GSP6_LINE_NUM 16 31 mmDP3_DP_SEC_CNTL6 0 0x2457 1 0 2 DP_SEC_GSP7_LINE_NUM 0 15 mmDP3_DP_SEC_CNTL7 0 0x2458 8 0 2 DP_SEC_GSP0_SEND_ACTIVE 0 0 DP_SEC_GSP1_SEND_ACTIVE 4 4 DP_SEC_GSP2_SEND_ACTIVE 8 8 DP_SEC_GSP3_SEND_ACTIVE 12 12 DP_SEC_GSP4_SEND_ACTIVE 16 16 DP_SEC_GSP5_SEND_ACTIVE 20 20 DP_SEC_GSP6_SEND_ACTIVE 24 24 DP_SEC_GSP7_SEND_ACTIVE 28 28 mmDP3_DP_DB_CNTL 0 0x2459 5 0 2 DP_DB_PENDING 0 0 DP_DB_TAKEN 4 4 DP_DB_TAKEN_CLR 5 5 DP_DB_LOCK 8 8 DP_DB_DISABLE 12 12 mmDP3_DP_MSA_VBID_MISC 0 0x245a 6 0 2 DP_MSA_MISC1_STEREOSYNC_OVERRIDE 0 1 DP_MSA_MISC1_STEREOSYNC_OVERRIDE_EN 4 4 DP_VBID1_OVERRIDE 8 8 DP_VBID2_OVERRIDE 9 9 DP_VBID1_OVERRIDE_EN 12 12 DP_VBID2_OVERRIDE_EN 13 13 mmDIG4_DIG_FE_CNTL 0 0x2468 8 0 2 DIG_SOURCE_SELECT 0 2 DIG_STEREOSYNC_SELECT 4 6 DIG_STEREOSYNC_GATE_EN 8 8 DIG_START 10 10 DIG_DIGITAL_BYPASS_SELECT 12 14 DIG_SYMCLK_FE_ON 24 24 TMDS_PIXEL_ENCODING 28 28 TMDS_COLOR_FORMAT 30 31 mmDIG4_DIG_OUTPUT_CRC_CNTL 0 0x2469 3 0 2 DIG_OUTPUT_CRC_EN 0 0 DIG_OUTPUT_CRC_LINK_SEL 4 4 DIG_OUTPUT_CRC_DATA_SEL 8 9 mmDIG4_DIG_OUTPUT_CRC_RESULT 0 0x246a 1 0 2 DIG_OUTPUT_CRC_RESULT 0 29 mmDIG4_DIG_CLOCK_PATTERN 0 0x246b 1 0 2 DIG_CLOCK_PATTERN 0 9 mmDIG4_DIG_TEST_PATTERN 0 0x246c 6 0 2 DIG_TEST_PATTERN_OUT_EN 0 0 DIG_HALF_CLOCK_PATTERN_SEL 1 1 DIG_RANDOM_PATTERN_OUT_EN 4 4 DIG_RANDOM_PATTERN_RESET 5 5 DIG_TEST_PATTERN_EXTERNAL_RESET_EN 6 6 DIG_STATIC_TEST_PATTERN 16 25 mmDIG4_DIG_RANDOM_PATTERN_SEED 0 0x246d 2 0 2 DIG_RANDOM_PATTERN_SEED 0 23 DIG_RAN_PAT_DURING_DE_ONLY 24 24 mmDIG4_DIG_FIFO_STATUS 0 0x246e 11 0 2 DIG_FIFO_LEVEL_ERROR 0 0 DIG_FIFO_USE_OVERWRITE_LEVEL 1 1 DIG_FIFO_OVERWRITE_LEVEL 2 7 DIG_FIFO_ERROR_ACK 8 8 DIG_FIFO_CAL_AVERAGE_LEVEL 10 15 DIG_FIFO_MAXIMUM_LEVEL 16 20 DIG_FIFO_MINIMUM_LEVEL 22 25 DIG_FIFO_READ_CLOCK_SRC 26 26 DIG_FIFO_CALIBRATED 29 29 DIG_FIFO_FORCE_RECAL_AVERAGE 30 30 DIG_FIFO_FORCE_RECOMP_MINMAX 31 31 mmDIG4_HDMI_CONTROL 0 0x2471 9 0 2 HDMI_KEEPOUT_MODE 0 0 HDMI_DATA_SCRAMBLE_EN 1 1 HDMI_CLOCK_CHANNEL_RATE 2 2 HDMI_NO_EXTRA_NULL_PACKET_FILLED 3 3 HDMI_PACKET_GEN_VERSION 4 4 HDMI_ERROR_ACK 8 8 HDMI_ERROR_MASK 9 9 HDMI_DEEP_COLOR_ENABLE 24 24 HDMI_DEEP_COLOR_DEPTH 28 29 mmDIG4_HDMI_STATUS 0 0x2472 4 0 2 HDMI_ACTIVE_AVMUTE 0 0 HDMI_AUDIO_PACKET_ERROR 16 16 HDMI_VBI_PACKET_ERROR 20 20 HDMI_ERROR_INT 27 27 mmDIG4_HDMI_AUDIO_PACKET_CONTROL 0 0x2473 2 0 2 HDMI_AUDIO_DELAY_EN 4 5 HDMI_AUDIO_PACKETS_PER_LINE 16 20 mmDIG4_HDMI_ACR_PACKET_CONTROL 0 0x2474 7 0 2 HDMI_ACR_SEND 0 0 HDMI_ACR_CONT 1 1 HDMI_ACR_SELECT 4 5 HDMI_ACR_SOURCE 8 8 HDMI_ACR_AUTO_SEND 12 12 HDMI_ACR_N_MULTIPLE 16 18 HDMI_ACR_AUDIO_PRIORITY 31 31 mmDIG4_HDMI_VBI_PACKET_CONTROL 0 0x2475 6 0 2 HDMI_NULL_SEND 0 0 HDMI_GC_SEND 4 4 HDMI_GC_CONT 5 5 HDMI_ISRC_SEND 8 8 HDMI_ISRC_CONT 9 9 HDMI_ISRC_LINE 16 21 mmDIG4_HDMI_INFOFRAME_CONTROL0 0 0x2476 4 0 2 HDMI_AUDIO_INFO_SEND 4 4 HDMI_AUDIO_INFO_CONT 5 5 HDMI_MPEG_INFO_SEND 8 8 HDMI_MPEG_INFO_CONT 9 9 mmDIG4_HDMI_INFOFRAME_CONTROL1 0 0x2477 2 0 2 HDMI_AUDIO_INFO_LINE 8 13 HDMI_MPEG_INFO_LINE 16 21 mmDIG4_HDMI_GENERIC_PACKET_CONTROL0 0 0x2478 6 0 2 HDMI_GENERIC0_SEND 0 0 HDMI_GENERIC0_CONT 1 1 HDMI_GENERIC1_SEND 4 4 HDMI_GENERIC1_CONT 5 5 HDMI_GENERIC0_LINE 16 21 HDMI_GENERIC1_LINE 24 29 mmDIG4_AFMT_INTERRUPT_STATUS 0 0x2479 0 0 2 mmDIG4_HDMI_GC 0 0x247b 5 0 2 HDMI_GC_AVMUTE 0 0 HDMI_GC_AVMUTE_CONT 2 2 HDMI_DEFAULT_PHASE 4 4 HDMI_PACKING_PHASE 8 11 HDMI_PACKING_PHASE_OVERRIDE 12 12 mmDIG4_AFMT_AUDIO_PACKET_CONTROL2 0 0x247c 6 0 2 AFMT_AUDIO_LAYOUT_OVRD 0 0 AFMT_AUDIO_LAYOUT_SELECT 1 1 AFMT_AUDIO_CHANNEL_ENABLE 8 15 AFMT_DP_AUDIO_STREAM_ID 16 23 AFMT_HBR_ENABLE_OVRD 24 24 AFMT_60958_OSF_OVRD 28 28 mmDIG4_AFMT_ISRC1_0 0 0x247d 3 0 2 AFMT_ISRC_STATUS 0 2 AFMT_ISRC_CONTINUE 6 6 AFMT_ISRC_VALID 7 7 mmDIG4_AFMT_ISRC1_1 0 0x247e 4 0 2 AFMT_UPC_EAN_ISRC0 0 7 AFMT_UPC_EAN_ISRC1 8 15 AFMT_UPC_EAN_ISRC2 16 23 AFMT_UPC_EAN_ISRC3 24 31 mmDIG4_AFMT_ISRC1_2 0 0x247f 4 0 2 AFMT_UPC_EAN_ISRC4 0 7 AFMT_UPC_EAN_ISRC5 8 15 AFMT_UPC_EAN_ISRC6 16 23 AFMT_UPC_EAN_ISRC7 24 31 mmDIG4_AFMT_ISRC1_3 0 0x2480 4 0 2 AFMT_UPC_EAN_ISRC8 0 7 AFMT_UPC_EAN_ISRC9 8 15 AFMT_UPC_EAN_ISRC10 16 23 AFMT_UPC_EAN_ISRC11 24 31 mmDIG4_AFMT_ISRC1_4 0 0x2481 4 0 2 AFMT_UPC_EAN_ISRC12 0 7 AFMT_UPC_EAN_ISRC13 8 15 AFMT_UPC_EAN_ISRC14 16 23 AFMT_UPC_EAN_ISRC15 24 31 mmDIG4_AFMT_ISRC2_0 0 0x2482 4 0 2 AFMT_UPC_EAN_ISRC16 0 7 AFMT_UPC_EAN_ISRC17 8 15 AFMT_UPC_EAN_ISRC18 16 23 AFMT_UPC_EAN_ISRC19 24 31 mmDIG4_AFMT_ISRC2_1 0 0x2483 4 0 2 AFMT_UPC_EAN_ISRC20 0 7 AFMT_UPC_EAN_ISRC21 8 15 AFMT_UPC_EAN_ISRC22 16 23 AFMT_UPC_EAN_ISRC23 24 31 mmDIG4_AFMT_ISRC2_2 0 0x2484 4 0 2 AFMT_UPC_EAN_ISRC24 0 7 AFMT_UPC_EAN_ISRC25 8 15 AFMT_UPC_EAN_ISRC26 16 23 AFMT_UPC_EAN_ISRC27 24 31 mmDIG4_AFMT_ISRC2_3 0 0x2485 4 0 2 AFMT_UPC_EAN_ISRC28 0 7 AFMT_UPC_EAN_ISRC29 8 15 AFMT_UPC_EAN_ISRC30 16 23 AFMT_UPC_EAN_ISRC31 24 31 mmDIG4_HDMI_GENERIC_PACKET_CONTROL2 0 0x2486 6 0 2 HDMI_GENERIC4_SEND 0 0 HDMI_GENERIC4_CONT 1 1 HDMI_GENERIC5_SEND 4 4 HDMI_GENERIC5_CONT 5 5 HDMI_GENERIC4_LINE 16 21 HDMI_GENERIC5_LINE 24 29 mmDIG4_HDMI_GENERIC_PACKET_CONTROL3 0 0x2487 6 0 2 HDMI_GENERIC6_SEND 0 0 HDMI_GENERIC6_CONT 1 1 HDMI_GENERIC7_SEND 4 4 HDMI_GENERIC7_CONT 5 5 HDMI_GENERIC6_LINE 16 21 HDMI_GENERIC7_LINE 24 29 mmDIG4_HDMI_DB_CONTROL 0 0x2488 5 0 2 HDMI_DB_PENDING 0 0 HDMI_DB_TAKEN 4 4 HDMI_DB_TAKEN_CLR 5 5 HDMI_DB_LOCK 8 8 HDMI_DB_DISABLE 12 12 mmDIG4_AFMT_MPEG_INFO0 0 0x248a 4 0 2 AFMT_MPEG_INFO_CHECKSUM 0 7 AFMT_MPEG_INFO_MB0 8 15 AFMT_MPEG_INFO_MB1 16 23 AFMT_MPEG_INFO_MB2 24 31 mmDIG4_AFMT_MPEG_INFO1 0 0x248b 3 0 2 AFMT_MPEG_INFO_MB3 0 7 AFMT_MPEG_INFO_MF 8 9 AFMT_MPEG_INFO_FR 12 12 mmDIG4_AFMT_GENERIC_HDR 0 0x248c 4 0 2 AFMT_GENERIC_HB0 0 7 AFMT_GENERIC_HB1 8 15 AFMT_GENERIC_HB2 16 23 AFMT_GENERIC_HB3 24 31 mmDIG4_AFMT_GENERIC_0 0 0x248d 4 0 2 AFMT_GENERIC_BYTE0 0 7 AFMT_GENERIC_BYTE1 8 15 AFMT_GENERIC_BYTE2 16 23 AFMT_GENERIC_BYTE3 24 31 mmDIG4_AFMT_GENERIC_1 0 0x248e 4 0 2 AFMT_GENERIC_BYTE4 0 7 AFMT_GENERIC_BYTE5 8 15 AFMT_GENERIC_BYTE6 16 23 AFMT_GENERIC_BYTE7 24 31 mmDIG4_AFMT_GENERIC_2 0 0x248f 4 0 2 AFMT_GENERIC_BYTE8 0 7 AFMT_GENERIC_BYTE9 8 15 AFMT_GENERIC_BYTE10 16 23 AFMT_GENERIC_BYTE11 24 31 mmDIG4_AFMT_GENERIC_3 0 0x2490 4 0 2 AFMT_GENERIC_BYTE12 0 7 AFMT_GENERIC_BYTE13 8 15 AFMT_GENERIC_BYTE14 16 23 AFMT_GENERIC_BYTE15 24 31 mmDIG4_AFMT_GENERIC_4 0 0x2491 4 0 2 AFMT_GENERIC_BYTE16 0 7 AFMT_GENERIC_BYTE17 8 15 AFMT_GENERIC_BYTE18 16 23 AFMT_GENERIC_BYTE19 24 31 mmDIG4_AFMT_GENERIC_5 0 0x2492 4 0 2 AFMT_GENERIC_BYTE20 0 7 AFMT_GENERIC_BYTE21 8 15 AFMT_GENERIC_BYTE22 16 23 AFMT_GENERIC_BYTE23 24 31 mmDIG4_AFMT_GENERIC_6 0 0x2493 4 0 2 AFMT_GENERIC_BYTE24 0 7 AFMT_GENERIC_BYTE25 8 15 AFMT_GENERIC_BYTE26 16 23 AFMT_GENERIC_BYTE27 24 31 mmDIG4_AFMT_GENERIC_7 0 0x2494 4 0 2 AFMT_GENERIC_BYTE28 0 7 AFMT_GENERIC_BYTE29 8 15 AFMT_GENERIC_BYTE30 16 23 AFMT_GENERIC_BYTE31 24 31 mmDIG4_HDMI_GENERIC_PACKET_CONTROL1 0 0x2495 6 0 2 HDMI_GENERIC2_SEND 0 0 HDMI_GENERIC2_CONT 1 1 HDMI_GENERIC3_SEND 4 4 HDMI_GENERIC3_CONT 5 5 HDMI_GENERIC2_LINE 16 21 HDMI_GENERIC3_LINE 24 29 mmDIG4_HDMI_ACR_32_0 0 0x2496 1 0 2 HDMI_ACR_CTS_32 12 31 mmDIG4_HDMI_ACR_32_1 0 0x2497 1 0 2 HDMI_ACR_N_32 0 19 mmDIG4_HDMI_ACR_44_0 0 0x2498 1 0 2 HDMI_ACR_CTS_44 12 31 mmDIG4_HDMI_ACR_44_1 0 0x2499 1 0 2 HDMI_ACR_N_44 0 19 mmDIG4_HDMI_ACR_48_0 0 0x249a 1 0 2 HDMI_ACR_CTS_48 12 31 mmDIG4_HDMI_ACR_48_1 0 0x249b 1 0 2 HDMI_ACR_N_48 0 19 mmDIG4_HDMI_ACR_STATUS_0 0 0x249c 1 0 2 HDMI_ACR_CTS 12 31 mmDIG4_HDMI_ACR_STATUS_1 0 0x249d 1 0 2 HDMI_ACR_N 0 19 mmDIG4_AFMT_AUDIO_INFO0 0 0x249e 5 0 2 AFMT_AUDIO_INFO_CHECKSUM 0 7 AFMT_AUDIO_INFO_CC 8 10 AFMT_AUDIO_INFO_CT 11 14 AFMT_AUDIO_INFO_CHECKSUM_OFFSET 16 23 AFMT_AUDIO_INFO_CXT 24 28 mmDIG4_AFMT_AUDIO_INFO1 0 0x249f 4 0 2 AFMT_AUDIO_INFO_CA 0 7 AFMT_AUDIO_INFO_LSV 11 14 AFMT_AUDIO_INFO_DM_INH 15 15 AFMT_AUDIO_INFO_LFEPBL 16 17 mmDIG4_AFMT_60958_0 0 0x24a0 10 0 2 AFMT_60958_CS_A 0 0 AFMT_60958_CS_B 1 1 AFMT_60958_CS_C 2 2 AFMT_60958_CS_D 3 5 AFMT_60958_CS_MODE 6 7 AFMT_60958_CS_CATEGORY_CODE 8 15 AFMT_60958_CS_SOURCE_NUMBER 16 19 AFMT_60958_CS_CHANNEL_NUMBER_L 20 23 AFMT_60958_CS_SAMPLING_FREQUENCY 24 27 AFMT_60958_CS_CLOCK_ACCURACY 28 29 mmDIG4_AFMT_60958_1 0 0x24a1 5 0 2 AFMT_60958_CS_WORD_LENGTH 0 3 AFMT_60958_CS_ORIGINAL_SAMPLING_FREQUENCY 4 7 AFMT_60958_VALID_L 16 16 AFMT_60958_VALID_R 18 18 AFMT_60958_CS_CHANNEL_NUMBER_R 20 23 mmDIG4_AFMT_AUDIO_CRC_CONTROL 0 0x24a2 5 0 2 AFMT_AUDIO_CRC_EN 0 0 AFMT_AUDIO_CRC_CONT 4 4 AFMT_AUDIO_CRC_SOURCE 8 8 AFMT_AUDIO_CRC_CH_SEL 12 15 AFMT_AUDIO_CRC_COUNT 16 31 mmDIG4_AFMT_RAMP_CONTROL0 0 0x24a3 2 0 2 AFMT_RAMP_MAX_COUNT 0 23 AFMT_RAMP_DATA_SIGN 31 31 mmDIG4_AFMT_RAMP_CONTROL1 0 0x24a4 2 0 2 AFMT_RAMP_MIN_COUNT 0 23 AFMT_AUDIO_TEST_CH_DISABLE 24 31 mmDIG4_AFMT_RAMP_CONTROL2 0 0x24a5 1 0 2 AFMT_RAMP_INC_COUNT 0 23 mmDIG4_AFMT_RAMP_CONTROL3 0 0x24a6 1 0 2 AFMT_RAMP_DEC_COUNT 0 23 mmDIG4_AFMT_60958_2 0 0x24a7 6 0 2 AFMT_60958_CS_CHANNEL_NUMBER_2 0 3 AFMT_60958_CS_CHANNEL_NUMBER_3 4 7 AFMT_60958_CS_CHANNEL_NUMBER_4 8 11 AFMT_60958_CS_CHANNEL_NUMBER_5 12 15 AFMT_60958_CS_CHANNEL_NUMBER_6 16 19 AFMT_60958_CS_CHANNEL_NUMBER_7 20 23 mmDIG4_AFMT_AUDIO_CRC_RESULT 0 0x24a8 2 0 2 AFMT_AUDIO_CRC_DONE 0 0 AFMT_AUDIO_CRC 8 31 mmDIG4_AFMT_STATUS 0 0x24a9 4 0 2 AFMT_AUDIO_ENABLE 4 4 AFMT_AZ_HBR_ENABLE 8 8 AFMT_AUDIO_FIFO_OVERFLOW 24 24 AFMT_AZ_AUDIO_ENABLE_CHG 30 30 mmDIG4_AFMT_AUDIO_PACKET_CONTROL 0 0x24aa 8 0 2 AFMT_AUDIO_SAMPLE_SEND 0 0 AFMT_RESET_FIFO_WHEN_AUDIO_DIS 11 11 AFMT_AUDIO_TEST_EN 12 12 AFMT_AUDIO_TEST_MODE 14 14 AFMT_AUDIO_FIFO_OVERFLOW_ACK 23 23 AFMT_AUDIO_CHANNEL_SWAP 24 24 AFMT_60958_CS_UPDATE 26 26 AFMT_AZ_AUDIO_ENABLE_CHG_ACK 30 30 mmDIG4_AFMT_VBI_PACKET_CONTROL 0 0x24ab 4 0 2 AFMT_GENERIC_LOCK_STATUS 8 8 AFMT_GENERIC_CONFLICT 16 16 AFMT_GENERIC_CONFLICT_CLR 17 17 AFMT_GENERIC_INDEX 28 31 mmDIG4_AFMT_INFOFRAME_CONTROL0 0 0x24ac 3 0 2 AFMT_AUDIO_INFO_SOURCE 6 6 AFMT_AUDIO_INFO_UPDATE 7 7 AFMT_MPEG_INFO_UPDATE 10 10 mmDIG4_AFMT_AUDIO_SRC_CONTROL 0 0x24ad 1 0 2 AFMT_AUDIO_SRC_SELECT 0 2 mmDIG4_DIG_BE_CNTL 0 0x24af 5 0 2 DIG_DUAL_LINK_ENABLE 0 0 DIG_SWAP 1 1 DIG_FE_SOURCE_SELECT 8 14 DIG_MODE 16 18 DIG_HPD_SELECT 28 30 mmDIG4_DIG_BE_EN_CNTL 0 0x24b0 2 0 2 DIG_ENABLE 0 0 DIG_SYMCLK_BE_ON 8 8 mmDIG4_TMDS_CNTL 0 0x24d3 1 0 2 TMDS_SYNC_PHASE 0 0 mmDIG4_TMDS_CONTROL_CHAR 0 0x24d4 4 0 2 TMDS_CONTROL_CHAR0_OUT_EN 0 0 TMDS_CONTROL_CHAR1_OUT_EN 1 1 TMDS_CONTROL_CHAR2_OUT_EN 2 2 TMDS_CONTROL_CHAR3_OUT_EN 3 3 mmDIG4_TMDS_CONTROL0_FEEDBACK 0 0x24d5 2 0 2 TMDS_CONTROL0_FEEDBACK_SELECT 0 1 TMDS_CONTROL0_FEEDBACK_DELAY 8 9 mmDIG4_TMDS_STEREOSYNC_CTL_SEL 0 0x24d6 1 0 2 TMDS_STEREOSYNC_CTL_SEL 0 1 mmDIG4_TMDS_SYNC_CHAR_PATTERN_0_1 0 0x24d7 2 0 2 TMDS_SYNC_CHAR_PATTERN0 0 9 TMDS_SYNC_CHAR_PATTERN1 16 25 mmDIG4_TMDS_SYNC_CHAR_PATTERN_2_3 0 0x24d8 2 0 2 TMDS_SYNC_CHAR_PATTERN2 0 9 TMDS_SYNC_CHAR_PATTERN3 16 25 mmDIG4_TMDS_CTL_BITS 0 0x24da 4 0 2 TMDS_CTL0 0 0 TMDS_CTL1 8 8 TMDS_CTL2 16 16 TMDS_CTL3 24 24 mmDIG4_TMDS_DCBALANCER_CONTROL 0 0x24db 4 0 2 TMDS_DCBALANCER_EN 0 0 TMDS_DCBALANCER_TEST_EN 8 8 TMDS_DCBALANCER_TEST_IN 16 19 TMDS_DCBALANCER_FORCE 24 24 mmDIG4_TMDS_CTL0_1_GEN_CNTL 0 0x24dd 15 0 2 TMDS_CTL0_DATA_SEL 0 3 TMDS_CTL0_DATA_DELAY 4 6 TMDS_CTL0_DATA_INVERT 7 7 TMDS_CTL0_DATA_MODULATION 8 9 TMDS_CTL0_USE_FEEDBACK_PATH 10 10 TMDS_CTL0_FB_SYNC_CONT 11 11 TMDS_CTL0_PATTERN_OUT_EN 12 12 TMDS_CTL1_DATA_SEL 16 19 TMDS_CTL1_DATA_DELAY 20 22 TMDS_CTL1_DATA_INVERT 23 23 TMDS_CTL1_DATA_MODULATION 24 25 TMDS_CTL1_USE_FEEDBACK_PATH 26 26 TMDS_CTL1_FB_SYNC_CONT 27 27 TMDS_CTL1_PATTERN_OUT_EN 28 28 TMDS_2BIT_COUNTER_EN 31 31 mmDIG4_TMDS_CTL2_3_GEN_CNTL 0 0x24de 14 0 2 TMDS_CTL2_DATA_SEL 0 3 TMDS_CTL2_DATA_DELAY 4 6 TMDS_CTL2_DATA_INVERT 7 7 TMDS_CTL2_DATA_MODULATION 8 9 TMDS_CTL2_USE_FEEDBACK_PATH 10 10 TMDS_CTL2_FB_SYNC_CONT 11 11 TMDS_CTL2_PATTERN_OUT_EN 12 12 TMDS_CTL3_DATA_SEL 16 19 TMDS_CTL3_DATA_DELAY 20 22 TMDS_CTL3_DATA_INVERT 23 23 TMDS_CTL3_DATA_MODULATION 24 25 TMDS_CTL3_USE_FEEDBACK_PATH 26 26 TMDS_CTL3_FB_SYNC_CONT 27 27 TMDS_CTL3_PATTERN_OUT_EN 28 28 mmDIG4_DIG_VERSION 0 0x24e0 1 0 2 DIG_TYPE 0 0 mmDIG4_DIG_LANE_ENABLE 0 0x24e1 5 0 2 DIG_LANE0EN 0 0 DIG_LANE1EN 1 1 DIG_LANE2EN 2 2 DIG_LANE3EN 3 3 DIG_CLK_EN 8 8 mmDIG4_AFMT_CNTL 0 0x24e6 2 0 2 AFMT_AUDIO_CLOCK_EN 0 0 AFMT_AUDIO_CLOCK_ON 8 8 mmDIG4_AFMT_VBI_PACKET_CONTROL1 0 0x24e7 32 0 2 AFMT_GENERIC0_FRAME_UPDATE 0 0 AFMT_GENERIC0_FRAME_UPDATE_PENDING 1 1 AFMT_GENERIC0_IMMEDIATE_UPDATE 2 2 AFMT_GENERIC0_IMMEDIATE_UPDATE_PENDING 3 3 AFMT_GENERIC1_FRAME_UPDATE 4 4 AFMT_GENERIC1_FRAME_UPDATE_PENDING 5 5 AFMT_GENERIC1_IMMEDIATE_UPDATE 6 6 AFMT_GENERIC1_IMMEDIATE_UPDATE_PENDING 7 7 AFMT_GENERIC2_FRAME_UPDATE 8 8 AFMT_GENERIC2_FRAME_UPDATE_PENDING 9 9 AFMT_GENERIC2_IMMEDIATE_UPDATE 10 10 AFMT_GENERIC2_IMMEDIATE_UPDATE_PENDING 11 11 AFMT_GENERIC3_FRAME_UPDATE 12 12 AFMT_GENERIC3_FRAME_UPDATE_PENDING 13 13 AFMT_GENERIC3_IMMEDIATE_UPDATE 14 14 AFMT_GENERIC3_IMMEDIATE_UPDATE_PENDING 15 15 AFMT_GENERIC4_FRAME_UPDATE 16 16 AFMT_GENERIC4_FRAME_UPDATE_PENDING 17 17 AFMT_GENERIC4_IMMEDIATE_UPDATE 18 18 AFMT_GENERIC4_IMMEDIATE_UPDATE_PENDING 19 19 AFMT_GENERIC5_FRAME_UPDATE 20 20 AFMT_GENERIC5_FRAME_UPDATE_PENDING 21 21 AFMT_GENERIC5_IMMEDIATE_UPDATE 22 22 AFMT_GENERIC5_IMMEDIATE_UPDATE_PENDING 23 23 AFMT_GENERIC6_FRAME_UPDATE 24 24 AFMT_GENERIC6_FRAME_UPDATE_PENDING 25 25 AFMT_GENERIC6_IMMEDIATE_UPDATE 26 26 AFMT_GENERIC6_IMMEDIATE_UPDATE_PENDING 27 27 AFMT_GENERIC7_FRAME_UPDATE 28 28 AFMT_GENERIC7_FRAME_UPDATE_PENDING 29 29 AFMT_GENERIC7_IMMEDIATE_UPDATE 30 30 AFMT_GENERIC7_IMMEDIATE_UPDATE_PENDING 31 31 mmDP4_DP_LINK_CNTL 0 0x2508 3 0 2 DP_LINK_TRAINING_COMPLETE 4 4 DP_LINK_STATUS 8 8 DP_EMBEDDED_PANEL_MODE 17 17 mmDP4_DP_PIXEL_FORMAT 0 0x2509 3 0 2 DP_PIXEL_ENCODING 0 2 DP_COMPONENT_DEPTH 24 26 DP_PIXEL_COMBINE 28 29 mmDP4_DP_MSA_COLORIMETRY 0 0x250a 1 0 2 DP_MSA_MISC0 24 31 mmDP4_DP_CONFIG 0 0x250b 1 0 2 DP_UDI_LANES 0 1 mmDP4_DP_VID_STREAM_CNTL 0 0x250c 4 0 2 DP_VID_STREAM_ENABLE 0 0 DP_VID_STREAM_DIS_DEFER 8 9 DP_VID_STREAM_STATUS 16 16 DP_VID_STREAM_CHANGE_KEEPOUT 20 20 mmDP4_DP_STEER_FIFO 0 0x250d 7 0 2 DP_STEER_FIFO_RESET 0 0 DP_STEER_OVERFLOW_FLAG 4 4 DP_STEER_OVERFLOW_INT 5 5 DP_STEER_OVERFLOW_ACK 6 6 DP_STEER_OVERFLOW_MASK 7 7 DP_TU_OVERFLOW_FLAG 8 8 DP_TU_OVERFLOW_ACK 12 12 mmDP4_DP_MSA_MISC 0 0x250e 4 0 2 DP_MSA_MISC1 0 7 DP_MSA_MISC2 8 15 DP_MSA_MISC3 16 23 DP_MSA_MISC4 24 31 mmDP4_DP_VID_TIMING 0 0x2510 5 0 2 DP_VID_M_N_DOUBLE_BUFFER_MODE 4 4 DP_VID_M_N_GEN_EN 8 8 DP_VID_N_MUL 10 11 DP_VID_M_DIV 12 13 DP_VID_N_DIV 24 31 mmDP4_DP_VID_N 0 0x2511 1 0 2 DP_VID_N 0 23 mmDP4_DP_VID_M 0 0x2512 1 0 2 DP_VID_M 0 23 mmDP4_DP_LINK_FRAMING_CNTL 0 0x2513 3 0 2 DP_IDLE_BS_INTERVAL 0 17 DP_VBID_DISABLE 24 24 DP_VID_ENHANCED_FRAME_MODE 28 28 mmDP4_DP_HBR2_EYE_PATTERN 0 0x2514 1 0 2 DP_HBR2_EYE_PATTERN_ENABLE 0 0 mmDP4_DP_VID_MSA_VBID 0 0x2515 2 0 2 DP_VID_MSA_LOCATION 0 11 DP_VID_VBID_FIELD_POL 24 24 mmDP4_DP_VID_INTERRUPT_CNTL 0 0x2516 3 0 2 DP_VID_STREAM_DISABLE_INT 0 0 DP_VID_STREAM_DISABLE_ACK 1 1 DP_VID_STREAM_DISABLE_MASK 2 2 mmDP4_DP_DPHY_CNTL 0 0x2517 6 0 2 DPHY_ATEST_SEL_LANE0 0 0 DPHY_ATEST_SEL_LANE1 1 1 DPHY_ATEST_SEL_LANE2 2 2 DPHY_ATEST_SEL_LANE3 3 3 DPHY_BYPASS 16 16 DPHY_SKEW_BYPASS 24 24 mmDP4_DP_DPHY_TRAINING_PATTERN_SEL 0 0x2518 1 0 2 DPHY_TRAINING_PATTERN_SEL 0 1 mmDP4_DP_DPHY_SYM0 0 0x2519 3 0 2 DPHY_SYM1 0 9 DPHY_SYM2 10 19 DPHY_SYM3 20 29 mmDP4_DP_DPHY_SYM1 0 0x251a 3 0 2 DPHY_SYM4 0 9 DPHY_SYM5 10 19 DPHY_SYM6 20 29 mmDP4_DP_DPHY_SYM2 0 0x251b 2 0 2 DPHY_SYM7 0 9 DPHY_SYM8 10 19 mmDP4_DP_DPHY_8B10B_CNTL 0 0x251c 3 0 2 DPHY_8B10B_RESET 8 8 DPHY_8B10B_EXT_DISP 16 16 DPHY_8B10B_CUR_DISP 24 24 mmDP4_DP_DPHY_PRBS_CNTL 0 0x251d 3 0 2 DPHY_PRBS_EN 0 0 DPHY_PRBS_SEL 4 5 DPHY_PRBS_SEED 8 30 mmDP4_DP_DPHY_SCRAM_CNTL 0 0x251e 4 0 2 DPHY_SCRAMBLER_DIS 0 0 DPHY_SCRAMBLER_ADVANCE 4 4 DPHY_SCRAMBLER_BS_COUNT 8 17 DPHY_SCRAMBLER_KCODE 24 24 mmDP4_DP_DPHY_CRC_EN 0 0x251f 3 0 2 DPHY_CRC_EN 0 0 DPHY_CRC_CONT_EN 4 4 DPHY_CRC_RESULT_VALID 8 8 mmDP4_DP_DPHY_CRC_CNTL 0 0x2520 3 0 2 DPHY_CRC_FIELD 0 0 DPHY_CRC_SEL 4 5 DPHY_CRC_MASK 16 23 mmDP4_DP_DPHY_CRC_RESULT 0 0x2521 4 0 2 DPHY_CRC_RESULT 0 7 DPHY_CRC_RESULT1 8 15 DPHY_CRC_RESULT2 16 23 DPHY_CRC_RESULT3 24 31 mmDP4_DP_DPHY_CRC_MST_CNTL 0 0x2522 2 0 2 DPHY_CRC_MST_FIRST_SLOT 0 5 DPHY_CRC_MST_LAST_SLOT 8 13 mmDP4_DP_DPHY_CRC_MST_STATUS 0 0x2523 3 0 2 DPHY_CRC_MST_PHASE_LOCK 0 0 DPHY_CRC_MST_PHASE_ERROR 8 8 DPHY_CRC_MST_PHASE_ERROR_ACK 16 16 mmDP4_DP_DPHY_FAST_TRAINING 0 0x2524 5 0 2 DPHY_RX_FAST_TRAINING_CAPABLE 0 0 DPHY_SW_FAST_TRAINING_START 1 1 DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN 2 2 DPHY_FAST_TRAINING_TP1_TIME 8 19 DPHY_FAST_TRAINING_TP2_TIME 20 31 mmDP4_DP_DPHY_FAST_TRAINING_STATUS 0 0x2525 4 0 2 DPHY_FAST_TRAINING_STATE 0 2 DPHY_FAST_TRAINING_COMPLETE_OCCURRED 4 4 DPHY_FAST_TRAINING_COMPLETE_MASK 8 8 DPHY_FAST_TRAINING_COMPLETE_ACK 12 12 mmDP4_DP_SEC_CNTL 0 0x252b 14 0 2 DP_SEC_STREAM_ENABLE 0 0 DP_SEC_ASP_ENABLE 4 4 DP_SEC_ATP_ENABLE 8 8 DP_SEC_AIP_ENABLE 12 12 DP_SEC_ACM_ENABLE 16 16 DP_SEC_GSP0_ENABLE 20 20 DP_SEC_GSP1_ENABLE 21 21 DP_SEC_GSP2_ENABLE 22 22 DP_SEC_GSP3_ENABLE 23 23 DP_SEC_GSP4_ENABLE 24 24 DP_SEC_GSP5_ENABLE 25 25 DP_SEC_GSP6_ENABLE 26 26 DP_SEC_GSP7_ENABLE 27 27 DP_SEC_MPG_ENABLE 28 28 mmDP4_DP_SEC_CNTL1 0 0x252c 7 0 2 DP_SEC_ISRC_ENABLE 0 0 DP_SEC_GSP0_PRIORITY 4 4 DP_SEC_GSP0_SEND 5 5 DP_SEC_GSP0_SEND_PENDING 6 6 DP_SEC_GSP0_SEND_DEADLINE_MISSED 7 7 DP_SEC_GSP0_SEND_ANY_LINE 8 8 DP_SEC_GSP0_LINE_NUM 16 31 mmDP4_DP_SEC_FRAMING1 0 0x252d 2 0 2 DP_SEC_FRAME_START_LOCATION 0 11 DP_SEC_VBLANK_TRANSMIT_WIDTH 16 31 mmDP4_DP_SEC_FRAMING2 0 0x252e 2 0 2 DP_SEC_START_POSITION 0 15 DP_SEC_HBLANK_TRANSMIT_WIDTH 16 31 mmDP4_DP_SEC_FRAMING3 0 0x252f 2 0 2 DP_SEC_IDLE_FRAME_SIZE 0 13 DP_SEC_IDLE_TRANSMIT_WIDTH 16 31 mmDP4_DP_SEC_FRAMING4 0 0x2530 4 0 2 DP_SEC_COLLISION_STATUS 20 20 DP_SEC_COLLISION_ACK 24 24 DP_SEC_AUDIO_MUTE 28 28 DP_SEC_AUDIO_MUTE_STATUS 29 29 mmDP4_DP_SEC_AUD_N 0 0x2531 1 0 2 DP_SEC_AUD_N 0 23 mmDP4_DP_SEC_AUD_N_READBACK 0 0x2532 1 0 2 DP_SEC_AUD_N_READBACK 0 23 mmDP4_DP_SEC_AUD_M 0 0x2533 1 0 2 DP_SEC_AUD_M 0 23 mmDP4_DP_SEC_AUD_M_READBACK 0 0x2534 1 0 2 DP_SEC_AUD_M_READBACK 0 23 mmDP4_DP_SEC_TIMESTAMP 0 0x2535 1 0 2 DP_SEC_TIMESTAMP_MODE 0 0 mmDP4_DP_SEC_PACKET_CNTL 0 0x2536 4 0 2 DP_SEC_ASP_CODING_TYPE 1 3 DP_SEC_ASP_PRIORITY 4 4 DP_SEC_VERSION 8 13 DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE 16 16 mmDP4_DP_MSE_RATE_CNTL 0 0x2537 2 0 2 DP_MSE_RATE_Y 0 25 DP_MSE_RATE_X 26 31 mmDP4_DP_MSE_RATE_UPDATE 0 0x2539 1 0 2 DP_MSE_RATE_UPDATE_PENDING 0 0 mmDP4_DP_MSE_SAT0 0 0x253a 4 0 2 DP_MSE_SAT_SRC0 0 2 DP_MSE_SAT_SLOT_COUNT0 8 13 DP_MSE_SAT_SRC1 16 18 DP_MSE_SAT_SLOT_COUNT1 24 29 mmDP4_DP_MSE_SAT1 0 0x253b 4 0 2 DP_MSE_SAT_SRC2 0 2 DP_MSE_SAT_SLOT_COUNT2 8 13 DP_MSE_SAT_SRC3 16 18 DP_MSE_SAT_SLOT_COUNT3 24 29 mmDP4_DP_MSE_SAT2 0 0x253c 4 0 2 DP_MSE_SAT_SRC4 0 2 DP_MSE_SAT_SLOT_COUNT4 8 13 DP_MSE_SAT_SRC5 16 18 DP_MSE_SAT_SLOT_COUNT5 24 29 mmDP4_DP_MSE_SAT_UPDATE 0 0x253d 2 0 2 DP_MSE_SAT_UPDATE 0 1 DP_MSE_16_MTP_KEEPOUT 8 8 mmDP4_DP_MSE_LINK_TIMING 0 0x253e 2 0 2 DP_MSE_LINK_FRAME 0 9 DP_MSE_LINK_LINE 16 17 mmDP4_DP_MSE_MISC_CNTL 0 0x253f 3 0 2 DP_MSE_BLANK_CODE 0 0 DP_MSE_TIMESTAMP_MODE 4 4 DP_MSE_ZERO_ENCODER 8 8 mmDP4_DP_DPHY_BS_SR_SWAP_CNTL 0 0x2544 3 0 2 DPHY_LOAD_BS_COUNT 0 9 DPHY_BS_SR_SWAP_DONE 15 15 DPHY_LOAD_BS_COUNT_START 16 16 mmDP4_DP_DPHY_HBR2_PATTERN_CONTROL 0 0x2545 1 0 2 DP_DPHY_HBR2_PATTERN_CONTROL 0 2 mmDP4_DP_MSE_SAT0_STATUS 0 0x2547 4 0 2 DP_MSE_SAT_SRC0_STATUS 0 2 DP_MSE_SAT_SLOT_COUNT0_STATUS 8 13 DP_MSE_SAT_SRC1_STATUS 16 18 DP_MSE_SAT_SLOT_COUNT1_STATUS 24 29 mmDP4_DP_MSE_SAT1_STATUS 0 0x2548 4 0 2 DP_MSE_SAT_SRC2_STATUS 0 2 DP_MSE_SAT_SLOT_COUNT2_STATUS 8 13 DP_MSE_SAT_SRC3_STATUS 16 18 DP_MSE_SAT_SLOT_COUNT3_STATUS 24 29 mmDP4_DP_MSE_SAT2_STATUS 0 0x2549 4 0 2 DP_MSE_SAT_SRC4_STATUS 0 2 DP_MSE_SAT_SLOT_COUNT4_STATUS 8 13 DP_MSE_SAT_SRC5_STATUS 16 18 DP_MSE_SAT_SLOT_COUNT5_STATUS 24 29 mmDP4_DP_MSA_TIMING_PARAM1 0 0x254c 2 0 2 DP_MSA_VTOTAL 0 15 DP_MSA_HTOTAL 16 31 mmDP4_DP_MSA_TIMING_PARAM2 0 0x254d 2 0 2 DP_MSA_VSTART 0 15 DP_MSA_HSTART 16 31 mmDP4_DP_MSA_TIMING_PARAM3 0 0x254e 4 0 2 DP_MSA_VSYNCWIDTH 0 14 DP_MSA_VSYNCPOLARITY 15 15 DP_MSA_HSYNCWIDTH 16 30 DP_MSA_HSYNCPOLARITY 31 31 mmDP4_DP_MSA_TIMING_PARAM4 0 0x254f 2 0 2 DP_MSA_VHEIGHT 0 15 DP_MSA_HWIDTH 16 31 mmDP4_DP_MSO_CNTL 0 0x2550 8 0 2 DP_MSO_NUM_OF_SSTLINK 0 1 DP_MSO_SEC_STREAM_ENABLE 4 7 DP_MSO_SEC_ASP_ENABLE 8 11 DP_MSO_SEC_ATP_ENABLE 12 15 DP_MSO_SEC_AIP_ENABLE 16 19 DP_MSO_SEC_ACM_ENABLE 20 23 DP_MSO_SEC_GSP0_ENABLE 24 27 DP_MSO_SEC_GSP1_ENABLE 28 31 mmDP4_DP_MSO_CNTL1 0 0x2551 8 0 2 DP_MSO_SEC_GSP2_ENABLE 0 3 DP_MSO_SEC_GSP3_ENABLE 4 7 DP_MSO_SEC_GSP4_ENABLE 8 11 DP_MSO_SEC_GSP5_ENABLE 12 15 DP_MSO_SEC_GSP6_ENABLE 16 19 DP_MSO_SEC_GSP7_ENABLE 20 23 DP_MSO_SEC_MPG_ENABLE 24 27 DP_MSO_SEC_ISRC_ENABLE 28 31 mmDP4_DP_DSC_CNTL 0 0x2552 1 0 2 DP_DSC_EN 0 0 mmDP4_DP_SEC_CNTL2 0 0x2553 29 0 2 DP_SEC_GSP1_SEND 0 0 DP_SEC_GSP1_SEND_PENDING 1 1 DP_SEC_GSP1_SEND_DEADLINE_MISSED 2 2 DP_SEC_GSP1_SEND_ANY_LINE 3 3 DP_SEC_GSP2_SEND 4 4 DP_SEC_GSP2_SEND_PENDING 5 5 DP_SEC_GSP2_SEND_DEADLINE_MISSED 6 6 DP_SEC_GSP2_SEND_ANY_LINE 7 7 DP_SEC_GSP3_SEND 8 8 DP_SEC_GSP3_SEND_PENDING 9 9 DP_SEC_GSP3_SEND_DEADLINE_MISSED 10 10 DP_SEC_GSP3_SEND_ANY_LINE 11 11 DP_SEC_GSP4_SEND 12 12 DP_SEC_GSP4_SEND_PENDING 13 13 DP_SEC_GSP4_SEND_DEADLINE_MISSED 14 14 DP_SEC_GSP4_SEND_ANY_LINE 15 15 DP_SEC_GSP5_SEND 16 16 DP_SEC_GSP5_SEND_PENDING 17 17 DP_SEC_GSP5_SEND_DEADLINE_MISSED 18 18 DP_SEC_GSP5_SEND_ANY_LINE 19 19 DP_SEC_GSP6_SEND 20 20 DP_SEC_GSP6_SEND_PENDING 21 21 DP_SEC_GSP6_SEND_DEADLINE_MISSED 22 22 DP_SEC_GSP6_SEND_ANY_LINE 23 23 DP_SEC_GSP7_SEND 24 24 DP_SEC_GSP7_SEND_PENDING 25 25 DP_SEC_GSP7_SEND_DEADLINE_MISSED 26 26 DP_SEC_GSP7_SEND_ANY_LINE 27 27 DP_SEC_GSP7_PPS 28 28 mmDP4_DP_SEC_CNTL3 0 0x2554 2 0 2 DP_SEC_GSP1_LINE_NUM 0 15 DP_SEC_GSP2_LINE_NUM 16 31 mmDP4_DP_SEC_CNTL4 0 0x2555 2 0 2 DP_SEC_GSP3_LINE_NUM 0 15 DP_SEC_GSP4_LINE_NUM 16 31 mmDP4_DP_SEC_CNTL5 0 0x2556 2 0 2 DP_SEC_GSP5_LINE_NUM 0 15 DP_SEC_GSP6_LINE_NUM 16 31 mmDP4_DP_SEC_CNTL6 0 0x2557 1 0 2 DP_SEC_GSP7_LINE_NUM 0 15 mmDP4_DP_SEC_CNTL7 0 0x2558 8 0 2 DP_SEC_GSP0_SEND_ACTIVE 0 0 DP_SEC_GSP1_SEND_ACTIVE 4 4 DP_SEC_GSP2_SEND_ACTIVE 8 8 DP_SEC_GSP3_SEND_ACTIVE 12 12 DP_SEC_GSP4_SEND_ACTIVE 16 16 DP_SEC_GSP5_SEND_ACTIVE 20 20 DP_SEC_GSP6_SEND_ACTIVE 24 24 DP_SEC_GSP7_SEND_ACTIVE 28 28 mmDP4_DP_DB_CNTL 0 0x2559 5 0 2 DP_DB_PENDING 0 0 DP_DB_TAKEN 4 4 DP_DB_TAKEN_CLR 5 5 DP_DB_LOCK 8 8 DP_DB_DISABLE 12 12 mmDP4_DP_MSA_VBID_MISC 0 0x255a 6 0 2 DP_MSA_MISC1_STEREOSYNC_OVERRIDE 0 1 DP_MSA_MISC1_STEREOSYNC_OVERRIDE_EN 4 4 DP_VBID1_OVERRIDE 8 8 DP_VBID2_OVERRIDE 9 9 DP_VBID1_OVERRIDE_EN 12 12 DP_VBID2_OVERRIDE_EN 13 13 mmDIG5_DIG_FE_CNTL 0 0x2568 8 0 2 DIG_SOURCE_SELECT 0 2 DIG_STEREOSYNC_SELECT 4 6 DIG_STEREOSYNC_GATE_EN 8 8 DIG_START 10 10 DIG_DIGITAL_BYPASS_SELECT 12 14 DIG_SYMCLK_FE_ON 24 24 TMDS_PIXEL_ENCODING 28 28 TMDS_COLOR_FORMAT 30 31 mmDIG5_DIG_OUTPUT_CRC_CNTL 0 0x2569 3 0 2 DIG_OUTPUT_CRC_EN 0 0 DIG_OUTPUT_CRC_LINK_SEL 4 4 DIG_OUTPUT_CRC_DATA_SEL 8 9 mmDIG5_DIG_OUTPUT_CRC_RESULT 0 0x256a 1 0 2 DIG_OUTPUT_CRC_RESULT 0 29 mmDIG5_DIG_CLOCK_PATTERN 0 0x256b 1 0 2 DIG_CLOCK_PATTERN 0 9 mmDIG5_DIG_TEST_PATTERN 0 0x256c 6 0 2 DIG_TEST_PATTERN_OUT_EN 0 0 DIG_HALF_CLOCK_PATTERN_SEL 1 1 DIG_RANDOM_PATTERN_OUT_EN 4 4 DIG_RANDOM_PATTERN_RESET 5 5 DIG_TEST_PATTERN_EXTERNAL_RESET_EN 6 6 DIG_STATIC_TEST_PATTERN 16 25 mmDIG5_DIG_RANDOM_PATTERN_SEED 0 0x256d 2 0 2 DIG_RANDOM_PATTERN_SEED 0 23 DIG_RAN_PAT_DURING_DE_ONLY 24 24 mmDIG5_DIG_FIFO_STATUS 0 0x256e 11 0 2 DIG_FIFO_LEVEL_ERROR 0 0 DIG_FIFO_USE_OVERWRITE_LEVEL 1 1 DIG_FIFO_OVERWRITE_LEVEL 2 7 DIG_FIFO_ERROR_ACK 8 8 DIG_FIFO_CAL_AVERAGE_LEVEL 10 15 DIG_FIFO_MAXIMUM_LEVEL 16 20 DIG_FIFO_MINIMUM_LEVEL 22 25 DIG_FIFO_READ_CLOCK_SRC 26 26 DIG_FIFO_CALIBRATED 29 29 DIG_FIFO_FORCE_RECAL_AVERAGE 30 30 DIG_FIFO_FORCE_RECOMP_MINMAX 31 31 mmDIG5_HDMI_CONTROL 0 0x2571 9 0 2 HDMI_KEEPOUT_MODE 0 0 HDMI_DATA_SCRAMBLE_EN 1 1 HDMI_CLOCK_CHANNEL_RATE 2 2 HDMI_NO_EXTRA_NULL_PACKET_FILLED 3 3 HDMI_PACKET_GEN_VERSION 4 4 HDMI_ERROR_ACK 8 8 HDMI_ERROR_MASK 9 9 HDMI_DEEP_COLOR_ENABLE 24 24 HDMI_DEEP_COLOR_DEPTH 28 29 mmDIG5_HDMI_STATUS 0 0x2572 4 0 2 HDMI_ACTIVE_AVMUTE 0 0 HDMI_AUDIO_PACKET_ERROR 16 16 HDMI_VBI_PACKET_ERROR 20 20 HDMI_ERROR_INT 27 27 mmDIG5_HDMI_AUDIO_PACKET_CONTROL 0 0x2573 2 0 2 HDMI_AUDIO_DELAY_EN 4 5 HDMI_AUDIO_PACKETS_PER_LINE 16 20 mmDIG5_HDMI_ACR_PACKET_CONTROL 0 0x2574 7 0 2 HDMI_ACR_SEND 0 0 HDMI_ACR_CONT 1 1 HDMI_ACR_SELECT 4 5 HDMI_ACR_SOURCE 8 8 HDMI_ACR_AUTO_SEND 12 12 HDMI_ACR_N_MULTIPLE 16 18 HDMI_ACR_AUDIO_PRIORITY 31 31 mmDIG5_HDMI_VBI_PACKET_CONTROL 0 0x2575 6 0 2 HDMI_NULL_SEND 0 0 HDMI_GC_SEND 4 4 HDMI_GC_CONT 5 5 HDMI_ISRC_SEND 8 8 HDMI_ISRC_CONT 9 9 HDMI_ISRC_LINE 16 21 mmDIG5_HDMI_INFOFRAME_CONTROL0 0 0x2576 4 0 2 HDMI_AUDIO_INFO_SEND 4 4 HDMI_AUDIO_INFO_CONT 5 5 HDMI_MPEG_INFO_SEND 8 8 HDMI_MPEG_INFO_CONT 9 9 mmDIG5_HDMI_INFOFRAME_CONTROL1 0 0x2577 2 0 2 HDMI_AUDIO_INFO_LINE 8 13 HDMI_MPEG_INFO_LINE 16 21 mmDIG5_HDMI_GENERIC_PACKET_CONTROL0 0 0x2578 6 0 2 HDMI_GENERIC0_SEND 0 0 HDMI_GENERIC0_CONT 1 1 HDMI_GENERIC1_SEND 4 4 HDMI_GENERIC1_CONT 5 5 HDMI_GENERIC0_LINE 16 21 HDMI_GENERIC1_LINE 24 29 mmDIG5_AFMT_INTERRUPT_STATUS 0 0x2579 0 0 2 mmDIG5_HDMI_GC 0 0x257b 5 0 2 HDMI_GC_AVMUTE 0 0 HDMI_GC_AVMUTE_CONT 2 2 HDMI_DEFAULT_PHASE 4 4 HDMI_PACKING_PHASE 8 11 HDMI_PACKING_PHASE_OVERRIDE 12 12 mmDIG5_AFMT_AUDIO_PACKET_CONTROL2 0 0x257c 6 0 2 AFMT_AUDIO_LAYOUT_OVRD 0 0 AFMT_AUDIO_LAYOUT_SELECT 1 1 AFMT_AUDIO_CHANNEL_ENABLE 8 15 AFMT_DP_AUDIO_STREAM_ID 16 23 AFMT_HBR_ENABLE_OVRD 24 24 AFMT_60958_OSF_OVRD 28 28 mmDIG5_AFMT_ISRC1_0 0 0x257d 3 0 2 AFMT_ISRC_STATUS 0 2 AFMT_ISRC_CONTINUE 6 6 AFMT_ISRC_VALID 7 7 mmDIG5_AFMT_ISRC1_1 0 0x257e 4 0 2 AFMT_UPC_EAN_ISRC0 0 7 AFMT_UPC_EAN_ISRC1 8 15 AFMT_UPC_EAN_ISRC2 16 23 AFMT_UPC_EAN_ISRC3 24 31 mmDIG5_AFMT_ISRC1_2 0 0x257f 4 0 2 AFMT_UPC_EAN_ISRC4 0 7 AFMT_UPC_EAN_ISRC5 8 15 AFMT_UPC_EAN_ISRC6 16 23 AFMT_UPC_EAN_ISRC7 24 31 mmDIG5_AFMT_ISRC1_3 0 0x2580 4 0 2 AFMT_UPC_EAN_ISRC8 0 7 AFMT_UPC_EAN_ISRC9 8 15 AFMT_UPC_EAN_ISRC10 16 23 AFMT_UPC_EAN_ISRC11 24 31 mmDIG5_AFMT_ISRC1_4 0 0x2581 4 0 2 AFMT_UPC_EAN_ISRC12 0 7 AFMT_UPC_EAN_ISRC13 8 15 AFMT_UPC_EAN_ISRC14 16 23 AFMT_UPC_EAN_ISRC15 24 31 mmDIG5_AFMT_ISRC2_0 0 0x2582 4 0 2 AFMT_UPC_EAN_ISRC16 0 7 AFMT_UPC_EAN_ISRC17 8 15 AFMT_UPC_EAN_ISRC18 16 23 AFMT_UPC_EAN_ISRC19 24 31 mmDIG5_AFMT_ISRC2_1 0 0x2583 4 0 2 AFMT_UPC_EAN_ISRC20 0 7 AFMT_UPC_EAN_ISRC21 8 15 AFMT_UPC_EAN_ISRC22 16 23 AFMT_UPC_EAN_ISRC23 24 31 mmDIG5_AFMT_ISRC2_2 0 0x2584 4 0 2 AFMT_UPC_EAN_ISRC24 0 7 AFMT_UPC_EAN_ISRC25 8 15 AFMT_UPC_EAN_ISRC26 16 23 AFMT_UPC_EAN_ISRC27 24 31 mmDIG5_AFMT_ISRC2_3 0 0x2585 4 0 2 AFMT_UPC_EAN_ISRC28 0 7 AFMT_UPC_EAN_ISRC29 8 15 AFMT_UPC_EAN_ISRC30 16 23 AFMT_UPC_EAN_ISRC31 24 31 mmDIG5_HDMI_GENERIC_PACKET_CONTROL2 0 0x2586 6 0 2 HDMI_GENERIC4_SEND 0 0 HDMI_GENERIC4_CONT 1 1 HDMI_GENERIC5_SEND 4 4 HDMI_GENERIC5_CONT 5 5 HDMI_GENERIC4_LINE 16 21 HDMI_GENERIC5_LINE 24 29 mmDIG5_HDMI_GENERIC_PACKET_CONTROL3 0 0x2587 6 0 2 HDMI_GENERIC6_SEND 0 0 HDMI_GENERIC6_CONT 1 1 HDMI_GENERIC7_SEND 4 4 HDMI_GENERIC7_CONT 5 5 HDMI_GENERIC6_LINE 16 21 HDMI_GENERIC7_LINE 24 29 mmDIG5_HDMI_DB_CONTROL 0 0x2588 5 0 2 HDMI_DB_PENDING 0 0 HDMI_DB_TAKEN 4 4 HDMI_DB_TAKEN_CLR 5 5 HDMI_DB_LOCK 8 8 HDMI_DB_DISABLE 12 12 mmDIG5_AFMT_MPEG_INFO0 0 0x258a 4 0 2 AFMT_MPEG_INFO_CHECKSUM 0 7 AFMT_MPEG_INFO_MB0 8 15 AFMT_MPEG_INFO_MB1 16 23 AFMT_MPEG_INFO_MB2 24 31 mmDIG5_AFMT_MPEG_INFO1 0 0x258b 3 0 2 AFMT_MPEG_INFO_MB3 0 7 AFMT_MPEG_INFO_MF 8 9 AFMT_MPEG_INFO_FR 12 12 mmDIG5_AFMT_GENERIC_HDR 0 0x258c 4 0 2 AFMT_GENERIC_HB0 0 7 AFMT_GENERIC_HB1 8 15 AFMT_GENERIC_HB2 16 23 AFMT_GENERIC_HB3 24 31 mmDIG5_AFMT_GENERIC_0 0 0x258d 4 0 2 AFMT_GENERIC_BYTE0 0 7 AFMT_GENERIC_BYTE1 8 15 AFMT_GENERIC_BYTE2 16 23 AFMT_GENERIC_BYTE3 24 31 mmDIG5_AFMT_GENERIC_1 0 0x258e 4 0 2 AFMT_GENERIC_BYTE4 0 7 AFMT_GENERIC_BYTE5 8 15 AFMT_GENERIC_BYTE6 16 23 AFMT_GENERIC_BYTE7 24 31 mmDIG5_AFMT_GENERIC_2 0 0x258f 4 0 2 AFMT_GENERIC_BYTE8 0 7 AFMT_GENERIC_BYTE9 8 15 AFMT_GENERIC_BYTE10 16 23 AFMT_GENERIC_BYTE11 24 31 mmDIG5_AFMT_GENERIC_3 0 0x2590 4 0 2 AFMT_GENERIC_BYTE12 0 7 AFMT_GENERIC_BYTE13 8 15 AFMT_GENERIC_BYTE14 16 23 AFMT_GENERIC_BYTE15 24 31 mmDIG5_AFMT_GENERIC_4 0 0x2591 4 0 2 AFMT_GENERIC_BYTE16 0 7 AFMT_GENERIC_BYTE17 8 15 AFMT_GENERIC_BYTE18 16 23 AFMT_GENERIC_BYTE19 24 31 mmDIG5_AFMT_GENERIC_5 0 0x2592 4 0 2 AFMT_GENERIC_BYTE20 0 7 AFMT_GENERIC_BYTE21 8 15 AFMT_GENERIC_BYTE22 16 23 AFMT_GENERIC_BYTE23 24 31 mmDIG5_AFMT_GENERIC_6 0 0x2593 4 0 2 AFMT_GENERIC_BYTE24 0 7 AFMT_GENERIC_BYTE25 8 15 AFMT_GENERIC_BYTE26 16 23 AFMT_GENERIC_BYTE27 24 31 mmDIG5_AFMT_GENERIC_7 0 0x2594 4 0 2 AFMT_GENERIC_BYTE28 0 7 AFMT_GENERIC_BYTE29 8 15 AFMT_GENERIC_BYTE30 16 23 AFMT_GENERIC_BYTE31 24 31 mmDIG5_HDMI_GENERIC_PACKET_CONTROL1 0 0x2595 6 0 2 HDMI_GENERIC2_SEND 0 0 HDMI_GENERIC2_CONT 1 1 HDMI_GENERIC3_SEND 4 4 HDMI_GENERIC3_CONT 5 5 HDMI_GENERIC2_LINE 16 21 HDMI_GENERIC3_LINE 24 29 mmDIG5_HDMI_ACR_32_0 0 0x2596 1 0 2 HDMI_ACR_CTS_32 12 31 mmDIG5_HDMI_ACR_32_1 0 0x2597 1 0 2 HDMI_ACR_N_32 0 19 mmDIG5_HDMI_ACR_44_0 0 0x2598 1 0 2 HDMI_ACR_CTS_44 12 31 mmDIG5_HDMI_ACR_44_1 0 0x2599 1 0 2 HDMI_ACR_N_44 0 19 mmDIG5_HDMI_ACR_48_0 0 0x259a 1 0 2 HDMI_ACR_CTS_48 12 31 mmDIG5_HDMI_ACR_48_1 0 0x259b 1 0 2 HDMI_ACR_N_48 0 19 mmDIG5_HDMI_ACR_STATUS_0 0 0x259c 1 0 2 HDMI_ACR_CTS 12 31 mmDIG5_HDMI_ACR_STATUS_1 0 0x259d 1 0 2 HDMI_ACR_N 0 19 mmDIG5_AFMT_AUDIO_INFO0 0 0x259e 5 0 2 AFMT_AUDIO_INFO_CHECKSUM 0 7 AFMT_AUDIO_INFO_CC 8 10 AFMT_AUDIO_INFO_CT 11 14 AFMT_AUDIO_INFO_CHECKSUM_OFFSET 16 23 AFMT_AUDIO_INFO_CXT 24 28 mmDIG5_AFMT_AUDIO_INFO1 0 0x259f 4 0 2 AFMT_AUDIO_INFO_CA 0 7 AFMT_AUDIO_INFO_LSV 11 14 AFMT_AUDIO_INFO_DM_INH 15 15 AFMT_AUDIO_INFO_LFEPBL 16 17 mmDIG5_AFMT_60958_0 0 0x25a0 10 0 2 AFMT_60958_CS_A 0 0 AFMT_60958_CS_B 1 1 AFMT_60958_CS_C 2 2 AFMT_60958_CS_D 3 5 AFMT_60958_CS_MODE 6 7 AFMT_60958_CS_CATEGORY_CODE 8 15 AFMT_60958_CS_SOURCE_NUMBER 16 19 AFMT_60958_CS_CHANNEL_NUMBER_L 20 23 AFMT_60958_CS_SAMPLING_FREQUENCY 24 27 AFMT_60958_CS_CLOCK_ACCURACY 28 29 mmDIG5_AFMT_60958_1 0 0x25a1 5 0 2 AFMT_60958_CS_WORD_LENGTH 0 3 AFMT_60958_CS_ORIGINAL_SAMPLING_FREQUENCY 4 7 AFMT_60958_VALID_L 16 16 AFMT_60958_VALID_R 18 18 AFMT_60958_CS_CHANNEL_NUMBER_R 20 23 mmDIG5_AFMT_AUDIO_CRC_CONTROL 0 0x25a2 5 0 2 AFMT_AUDIO_CRC_EN 0 0 AFMT_AUDIO_CRC_CONT 4 4 AFMT_AUDIO_CRC_SOURCE 8 8 AFMT_AUDIO_CRC_CH_SEL 12 15 AFMT_AUDIO_CRC_COUNT 16 31 mmDIG5_AFMT_RAMP_CONTROL0 0 0x25a3 2 0 2 AFMT_RAMP_MAX_COUNT 0 23 AFMT_RAMP_DATA_SIGN 31 31 mmDIG5_AFMT_RAMP_CONTROL1 0 0x25a4 2 0 2 AFMT_RAMP_MIN_COUNT 0 23 AFMT_AUDIO_TEST_CH_DISABLE 24 31 mmDIG5_AFMT_RAMP_CONTROL2 0 0x25a5 1 0 2 AFMT_RAMP_INC_COUNT 0 23 mmDIG5_AFMT_RAMP_CONTROL3 0 0x25a6 1 0 2 AFMT_RAMP_DEC_COUNT 0 23 mmDIG5_AFMT_60958_2 0 0x25a7 6 0 2 AFMT_60958_CS_CHANNEL_NUMBER_2 0 3 AFMT_60958_CS_CHANNEL_NUMBER_3 4 7 AFMT_60958_CS_CHANNEL_NUMBER_4 8 11 AFMT_60958_CS_CHANNEL_NUMBER_5 12 15 AFMT_60958_CS_CHANNEL_NUMBER_6 16 19 AFMT_60958_CS_CHANNEL_NUMBER_7 20 23 mmDIG5_AFMT_AUDIO_CRC_RESULT 0 0x25a8 2 0 2 AFMT_AUDIO_CRC_DONE 0 0 AFMT_AUDIO_CRC 8 31 mmDIG5_AFMT_STATUS 0 0x25a9 4 0 2 AFMT_AUDIO_ENABLE 4 4 AFMT_AZ_HBR_ENABLE 8 8 AFMT_AUDIO_FIFO_OVERFLOW 24 24 AFMT_AZ_AUDIO_ENABLE_CHG 30 30 mmDIG5_AFMT_AUDIO_PACKET_CONTROL 0 0x25aa 8 0 2 AFMT_AUDIO_SAMPLE_SEND 0 0 AFMT_RESET_FIFO_WHEN_AUDIO_DIS 11 11 AFMT_AUDIO_TEST_EN 12 12 AFMT_AUDIO_TEST_MODE 14 14 AFMT_AUDIO_FIFO_OVERFLOW_ACK 23 23 AFMT_AUDIO_CHANNEL_SWAP 24 24 AFMT_60958_CS_UPDATE 26 26 AFMT_AZ_AUDIO_ENABLE_CHG_ACK 30 30 mmDIG5_AFMT_VBI_PACKET_CONTROL 0 0x25ab 4 0 2 AFMT_GENERIC_LOCK_STATUS 8 8 AFMT_GENERIC_CONFLICT 16 16 AFMT_GENERIC_CONFLICT_CLR 17 17 AFMT_GENERIC_INDEX 28 31 mmDIG5_AFMT_INFOFRAME_CONTROL0 0 0x25ac 3 0 2 AFMT_AUDIO_INFO_SOURCE 6 6 AFMT_AUDIO_INFO_UPDATE 7 7 AFMT_MPEG_INFO_UPDATE 10 10 mmDIG5_AFMT_AUDIO_SRC_CONTROL 0 0x25ad 1 0 2 AFMT_AUDIO_SRC_SELECT 0 2 mmDIG5_DIG_BE_CNTL 0 0x25af 5 0 2 DIG_DUAL_LINK_ENABLE 0 0 DIG_SWAP 1 1 DIG_FE_SOURCE_SELECT 8 14 DIG_MODE 16 18 DIG_HPD_SELECT 28 30 mmDIG5_DIG_BE_EN_CNTL 0 0x25b0 2 0 2 DIG_ENABLE 0 0 DIG_SYMCLK_BE_ON 8 8 mmDIG5_TMDS_CNTL 0 0x25d3 1 0 2 TMDS_SYNC_PHASE 0 0 mmDIG5_TMDS_CONTROL_CHAR 0 0x25d4 4 0 2 TMDS_CONTROL_CHAR0_OUT_EN 0 0 TMDS_CONTROL_CHAR1_OUT_EN 1 1 TMDS_CONTROL_CHAR2_OUT_EN 2 2 TMDS_CONTROL_CHAR3_OUT_EN 3 3 mmDIG5_TMDS_CONTROL0_FEEDBACK 0 0x25d5 2 0 2 TMDS_CONTROL0_FEEDBACK_SELECT 0 1 TMDS_CONTROL0_FEEDBACK_DELAY 8 9 mmDIG5_TMDS_STEREOSYNC_CTL_SEL 0 0x25d6 1 0 2 TMDS_STEREOSYNC_CTL_SEL 0 1 mmDIG5_TMDS_SYNC_CHAR_PATTERN_0_1 0 0x25d7 2 0 2 TMDS_SYNC_CHAR_PATTERN0 0 9 TMDS_SYNC_CHAR_PATTERN1 16 25 mmDIG5_TMDS_SYNC_CHAR_PATTERN_2_3 0 0x25d8 2 0 2 TMDS_SYNC_CHAR_PATTERN2 0 9 TMDS_SYNC_CHAR_PATTERN3 16 25 mmDIG5_TMDS_CTL_BITS 0 0x25da 4 0 2 TMDS_CTL0 0 0 TMDS_CTL1 8 8 TMDS_CTL2 16 16 TMDS_CTL3 24 24 mmDIG5_TMDS_DCBALANCER_CONTROL 0 0x25db 4 0 2 TMDS_DCBALANCER_EN 0 0 TMDS_DCBALANCER_TEST_EN 8 8 TMDS_DCBALANCER_TEST_IN 16 19 TMDS_DCBALANCER_FORCE 24 24 mmDIG5_TMDS_CTL0_1_GEN_CNTL 0 0x25dd 15 0 2 TMDS_CTL0_DATA_SEL 0 3 TMDS_CTL0_DATA_DELAY 4 6 TMDS_CTL0_DATA_INVERT 7 7 TMDS_CTL0_DATA_MODULATION 8 9 TMDS_CTL0_USE_FEEDBACK_PATH 10 10 TMDS_CTL0_FB_SYNC_CONT 11 11 TMDS_CTL0_PATTERN_OUT_EN 12 12 TMDS_CTL1_DATA_SEL 16 19 TMDS_CTL1_DATA_DELAY 20 22 TMDS_CTL1_DATA_INVERT 23 23 TMDS_CTL1_DATA_MODULATION 24 25 TMDS_CTL1_USE_FEEDBACK_PATH 26 26 TMDS_CTL1_FB_SYNC_CONT 27 27 TMDS_CTL1_PATTERN_OUT_EN 28 28 TMDS_2BIT_COUNTER_EN 31 31 mmDIG5_TMDS_CTL2_3_GEN_CNTL 0 0x25de 14 0 2 TMDS_CTL2_DATA_SEL 0 3 TMDS_CTL2_DATA_DELAY 4 6 TMDS_CTL2_DATA_INVERT 7 7 TMDS_CTL2_DATA_MODULATION 8 9 TMDS_CTL2_USE_FEEDBACK_PATH 10 10 TMDS_CTL2_FB_SYNC_CONT 11 11 TMDS_CTL2_PATTERN_OUT_EN 12 12 TMDS_CTL3_DATA_SEL 16 19 TMDS_CTL3_DATA_DELAY 20 22 TMDS_CTL3_DATA_INVERT 23 23 TMDS_CTL3_DATA_MODULATION 24 25 TMDS_CTL3_USE_FEEDBACK_PATH 26 26 TMDS_CTL3_FB_SYNC_CONT 27 27 TMDS_CTL3_PATTERN_OUT_EN 28 28 mmDIG5_DIG_VERSION 0 0x25e0 1 0 2 DIG_TYPE 0 0 mmDIG5_DIG_LANE_ENABLE 0 0x25e1 5 0 2 DIG_LANE0EN 0 0 DIG_LANE1EN 1 1 DIG_LANE2EN 2 2 DIG_LANE3EN 3 3 DIG_CLK_EN 8 8 mmDIG5_AFMT_CNTL 0 0x25e6 2 0 2 AFMT_AUDIO_CLOCK_EN 0 0 AFMT_AUDIO_CLOCK_ON 8 8 mmDIG5_AFMT_VBI_PACKET_CONTROL1 0 0x25e7 32 0 2 AFMT_GENERIC0_FRAME_UPDATE 0 0 AFMT_GENERIC0_FRAME_UPDATE_PENDING 1 1 AFMT_GENERIC0_IMMEDIATE_UPDATE 2 2 AFMT_GENERIC0_IMMEDIATE_UPDATE_PENDING 3 3 AFMT_GENERIC1_FRAME_UPDATE 4 4 AFMT_GENERIC1_FRAME_UPDATE_PENDING 5 5 AFMT_GENERIC1_IMMEDIATE_UPDATE 6 6 AFMT_GENERIC1_IMMEDIATE_UPDATE_PENDING 7 7 AFMT_GENERIC2_FRAME_UPDATE 8 8 AFMT_GENERIC2_FRAME_UPDATE_PENDING 9 9 AFMT_GENERIC2_IMMEDIATE_UPDATE 10 10 AFMT_GENERIC2_IMMEDIATE_UPDATE_PENDING 11 11 AFMT_GENERIC3_FRAME_UPDATE 12 12 AFMT_GENERIC3_FRAME_UPDATE_PENDING 13 13 AFMT_GENERIC3_IMMEDIATE_UPDATE 14 14 AFMT_GENERIC3_IMMEDIATE_UPDATE_PENDING 15 15 AFMT_GENERIC4_FRAME_UPDATE 16 16 AFMT_GENERIC4_FRAME_UPDATE_PENDING 17 17 AFMT_GENERIC4_IMMEDIATE_UPDATE 18 18 AFMT_GENERIC4_IMMEDIATE_UPDATE_PENDING 19 19 AFMT_GENERIC5_FRAME_UPDATE 20 20 AFMT_GENERIC5_FRAME_UPDATE_PENDING 21 21 AFMT_GENERIC5_IMMEDIATE_UPDATE 22 22 AFMT_GENERIC5_IMMEDIATE_UPDATE_PENDING 23 23 AFMT_GENERIC6_FRAME_UPDATE 24 24 AFMT_GENERIC6_FRAME_UPDATE_PENDING 25 25 AFMT_GENERIC6_IMMEDIATE_UPDATE 26 26 AFMT_GENERIC6_IMMEDIATE_UPDATE_PENDING 27 27 AFMT_GENERIC7_FRAME_UPDATE 28 28 AFMT_GENERIC7_FRAME_UPDATE_PENDING 29 29 AFMT_GENERIC7_IMMEDIATE_UPDATE 30 30 AFMT_GENERIC7_IMMEDIATE_UPDATE_PENDING 31 31 mmDP5_DP_LINK_CNTL 0 0x2608 3 0 2 DP_LINK_TRAINING_COMPLETE 4 4 DP_LINK_STATUS 8 8 DP_EMBEDDED_PANEL_MODE 17 17 mmDP5_DP_PIXEL_FORMAT 0 0x2609 3 0 2 DP_PIXEL_ENCODING 0 2 DP_COMPONENT_DEPTH 24 26 DP_PIXEL_COMBINE 28 29 mmDP5_DP_MSA_COLORIMETRY 0 0x260a 1 0 2 DP_MSA_MISC0 24 31 mmDP5_DP_CONFIG 0 0x260b 1 0 2 DP_UDI_LANES 0 1 mmDP5_DP_VID_STREAM_CNTL 0 0x260c 4 0 2 DP_VID_STREAM_ENABLE 0 0 DP_VID_STREAM_DIS_DEFER 8 9 DP_VID_STREAM_STATUS 16 16 DP_VID_STREAM_CHANGE_KEEPOUT 20 20 mmDP5_DP_STEER_FIFO 0 0x260d 7 0 2 DP_STEER_FIFO_RESET 0 0 DP_STEER_OVERFLOW_FLAG 4 4 DP_STEER_OVERFLOW_INT 5 5 DP_STEER_OVERFLOW_ACK 6 6 DP_STEER_OVERFLOW_MASK 7 7 DP_TU_OVERFLOW_FLAG 8 8 DP_TU_OVERFLOW_ACK 12 12 mmDP5_DP_MSA_MISC 0 0x260e 4 0 2 DP_MSA_MISC1 0 7 DP_MSA_MISC2 8 15 DP_MSA_MISC3 16 23 DP_MSA_MISC4 24 31 mmDP5_DP_VID_TIMING 0 0x2610 5 0 2 DP_VID_M_N_DOUBLE_BUFFER_MODE 4 4 DP_VID_M_N_GEN_EN 8 8 DP_VID_N_MUL 10 11 DP_VID_M_DIV 12 13 DP_VID_N_DIV 24 31 mmDP5_DP_VID_N 0 0x2611 1 0 2 DP_VID_N 0 23 mmDP5_DP_VID_M 0 0x2612 1 0 2 DP_VID_M 0 23 mmDP5_DP_LINK_FRAMING_CNTL 0 0x2613 3 0 2 DP_IDLE_BS_INTERVAL 0 17 DP_VBID_DISABLE 24 24 DP_VID_ENHANCED_FRAME_MODE 28 28 mmDP5_DP_HBR2_EYE_PATTERN 0 0x2614 1 0 2 DP_HBR2_EYE_PATTERN_ENABLE 0 0 mmDP5_DP_VID_MSA_VBID 0 0x2615 2 0 2 DP_VID_MSA_LOCATION 0 11 DP_VID_VBID_FIELD_POL 24 24 mmDP5_DP_VID_INTERRUPT_CNTL 0 0x2616 3 0 2 DP_VID_STREAM_DISABLE_INT 0 0 DP_VID_STREAM_DISABLE_ACK 1 1 DP_VID_STREAM_DISABLE_MASK 2 2 mmDP5_DP_DPHY_CNTL 0 0x2617 6 0 2 DPHY_ATEST_SEL_LANE0 0 0 DPHY_ATEST_SEL_LANE1 1 1 DPHY_ATEST_SEL_LANE2 2 2 DPHY_ATEST_SEL_LANE3 3 3 DPHY_BYPASS 16 16 DPHY_SKEW_BYPASS 24 24 mmDP5_DP_DPHY_TRAINING_PATTERN_SEL 0 0x2618 1 0 2 DPHY_TRAINING_PATTERN_SEL 0 1 mmDP5_DP_DPHY_SYM0 0 0x2619 3 0 2 DPHY_SYM1 0 9 DPHY_SYM2 10 19 DPHY_SYM3 20 29 mmDP5_DP_DPHY_SYM1 0 0x261a 3 0 2 DPHY_SYM4 0 9 DPHY_SYM5 10 19 DPHY_SYM6 20 29 mmDP5_DP_DPHY_SYM2 0 0x261b 2 0 2 DPHY_SYM7 0 9 DPHY_SYM8 10 19 mmDP5_DP_DPHY_8B10B_CNTL 0 0x261c 3 0 2 DPHY_8B10B_RESET 8 8 DPHY_8B10B_EXT_DISP 16 16 DPHY_8B10B_CUR_DISP 24 24 mmDP5_DP_DPHY_PRBS_CNTL 0 0x261d 3 0 2 DPHY_PRBS_EN 0 0 DPHY_PRBS_SEL 4 5 DPHY_PRBS_SEED 8 30 mmDP5_DP_DPHY_SCRAM_CNTL 0 0x261e 4 0 2 DPHY_SCRAMBLER_DIS 0 0 DPHY_SCRAMBLER_ADVANCE 4 4 DPHY_SCRAMBLER_BS_COUNT 8 17 DPHY_SCRAMBLER_KCODE 24 24 mmDP5_DP_DPHY_CRC_EN 0 0x261f 3 0 2 DPHY_CRC_EN 0 0 DPHY_CRC_CONT_EN 4 4 DPHY_CRC_RESULT_VALID 8 8 mmDP5_DP_DPHY_CRC_CNTL 0 0x2620 3 0 2 DPHY_CRC_FIELD 0 0 DPHY_CRC_SEL 4 5 DPHY_CRC_MASK 16 23 mmDP5_DP_DPHY_CRC_RESULT 0 0x2621 4 0 2 DPHY_CRC_RESULT 0 7 DPHY_CRC_RESULT1 8 15 DPHY_CRC_RESULT2 16 23 DPHY_CRC_RESULT3 24 31 mmDP5_DP_DPHY_CRC_MST_CNTL 0 0x2622 2 0 2 DPHY_CRC_MST_FIRST_SLOT 0 5 DPHY_CRC_MST_LAST_SLOT 8 13 mmDP5_DP_DPHY_CRC_MST_STATUS 0 0x2623 3 0 2 DPHY_CRC_MST_PHASE_LOCK 0 0 DPHY_CRC_MST_PHASE_ERROR 8 8 DPHY_CRC_MST_PHASE_ERROR_ACK 16 16 mmDP5_DP_DPHY_FAST_TRAINING 0 0x2624 5 0 2 DPHY_RX_FAST_TRAINING_CAPABLE 0 0 DPHY_SW_FAST_TRAINING_START 1 1 DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN 2 2 DPHY_FAST_TRAINING_TP1_TIME 8 19 DPHY_FAST_TRAINING_TP2_TIME 20 31 mmDP5_DP_DPHY_FAST_TRAINING_STATUS 0 0x2625 4 0 2 DPHY_FAST_TRAINING_STATE 0 2 DPHY_FAST_TRAINING_COMPLETE_OCCURRED 4 4 DPHY_FAST_TRAINING_COMPLETE_MASK 8 8 DPHY_FAST_TRAINING_COMPLETE_ACK 12 12 mmDP5_DP_SEC_CNTL 0 0x262b 14 0 2 DP_SEC_STREAM_ENABLE 0 0 DP_SEC_ASP_ENABLE 4 4 DP_SEC_ATP_ENABLE 8 8 DP_SEC_AIP_ENABLE 12 12 DP_SEC_ACM_ENABLE 16 16 DP_SEC_GSP0_ENABLE 20 20 DP_SEC_GSP1_ENABLE 21 21 DP_SEC_GSP2_ENABLE 22 22 DP_SEC_GSP3_ENABLE 23 23 DP_SEC_GSP4_ENABLE 24 24 DP_SEC_GSP5_ENABLE 25 25 DP_SEC_GSP6_ENABLE 26 26 DP_SEC_GSP7_ENABLE 27 27 DP_SEC_MPG_ENABLE 28 28 mmDP5_DP_SEC_CNTL1 0 0x262c 7 0 2 DP_SEC_ISRC_ENABLE 0 0 DP_SEC_GSP0_PRIORITY 4 4 DP_SEC_GSP0_SEND 5 5 DP_SEC_GSP0_SEND_PENDING 6 6 DP_SEC_GSP0_SEND_DEADLINE_MISSED 7 7 DP_SEC_GSP0_SEND_ANY_LINE 8 8 DP_SEC_GSP0_LINE_NUM 16 31 mmDP5_DP_SEC_FRAMING1 0 0x262d 2 0 2 DP_SEC_FRAME_START_LOCATION 0 11 DP_SEC_VBLANK_TRANSMIT_WIDTH 16 31 mmDP5_DP_SEC_FRAMING2 0 0x262e 2 0 2 DP_SEC_START_POSITION 0 15 DP_SEC_HBLANK_TRANSMIT_WIDTH 16 31 mmDP5_DP_SEC_FRAMING3 0 0x262f 2 0 2 DP_SEC_IDLE_FRAME_SIZE 0 13 DP_SEC_IDLE_TRANSMIT_WIDTH 16 31 mmDP5_DP_SEC_FRAMING4 0 0x2630 4 0 2 DP_SEC_COLLISION_STATUS 20 20 DP_SEC_COLLISION_ACK 24 24 DP_SEC_AUDIO_MUTE 28 28 DP_SEC_AUDIO_MUTE_STATUS 29 29 mmDP5_DP_SEC_AUD_N 0 0x2631 1 0 2 DP_SEC_AUD_N 0 23 mmDP5_DP_SEC_AUD_N_READBACK 0 0x2632 1 0 2 DP_SEC_AUD_N_READBACK 0 23 mmDP5_DP_SEC_AUD_M 0 0x2633 1 0 2 DP_SEC_AUD_M 0 23 mmDP5_DP_SEC_AUD_M_READBACK 0 0x2634 1 0 2 DP_SEC_AUD_M_READBACK 0 23 mmDP5_DP_SEC_TIMESTAMP 0 0x2635 1 0 2 DP_SEC_TIMESTAMP_MODE 0 0 mmDP5_DP_SEC_PACKET_CNTL 0 0x2636 4 0 2 DP_SEC_ASP_CODING_TYPE 1 3 DP_SEC_ASP_PRIORITY 4 4 DP_SEC_VERSION 8 13 DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE 16 16 mmDP5_DP_MSE_RATE_CNTL 0 0x2637 2 0 2 DP_MSE_RATE_Y 0 25 DP_MSE_RATE_X 26 31 mmDP5_DP_MSE_RATE_UPDATE 0 0x2639 1 0 2 DP_MSE_RATE_UPDATE_PENDING 0 0 mmDP5_DP_MSE_SAT0 0 0x263a 4 0 2 DP_MSE_SAT_SRC0 0 2 DP_MSE_SAT_SLOT_COUNT0 8 13 DP_MSE_SAT_SRC1 16 18 DP_MSE_SAT_SLOT_COUNT1 24 29 mmDP5_DP_MSE_SAT1 0 0x263b 4 0 2 DP_MSE_SAT_SRC2 0 2 DP_MSE_SAT_SLOT_COUNT2 8 13 DP_MSE_SAT_SRC3 16 18 DP_MSE_SAT_SLOT_COUNT3 24 29 mmDP5_DP_MSE_SAT2 0 0x263c 4 0 2 DP_MSE_SAT_SRC4 0 2 DP_MSE_SAT_SLOT_COUNT4 8 13 DP_MSE_SAT_SRC5 16 18 DP_MSE_SAT_SLOT_COUNT5 24 29 mmDP5_DP_MSE_SAT_UPDATE 0 0x263d 2 0 2 DP_MSE_SAT_UPDATE 0 1 DP_MSE_16_MTP_KEEPOUT 8 8 mmDP5_DP_MSE_LINK_TIMING 0 0x263e 2 0 2 DP_MSE_LINK_FRAME 0 9 DP_MSE_LINK_LINE 16 17 mmDP5_DP_MSE_MISC_CNTL 0 0x263f 3 0 2 DP_MSE_BLANK_CODE 0 0 DP_MSE_TIMESTAMP_MODE 4 4 DP_MSE_ZERO_ENCODER 8 8 mmDP5_DP_DPHY_BS_SR_SWAP_CNTL 0 0x2644 3 0 2 DPHY_LOAD_BS_COUNT 0 9 DPHY_BS_SR_SWAP_DONE 15 15 DPHY_LOAD_BS_COUNT_START 16 16 mmDP5_DP_DPHY_HBR2_PATTERN_CONTROL 0 0x2645 1 0 2 DP_DPHY_HBR2_PATTERN_CONTROL 0 2 mmDP5_DP_MSE_SAT0_STATUS 0 0x2647 4 0 2 DP_MSE_SAT_SRC0_STATUS 0 2 DP_MSE_SAT_SLOT_COUNT0_STATUS 8 13 DP_MSE_SAT_SRC1_STATUS 16 18 DP_MSE_SAT_SLOT_COUNT1_STATUS 24 29 mmDP5_DP_MSE_SAT1_STATUS 0 0x2648 4 0 2 DP_MSE_SAT_SRC2_STATUS 0 2 DP_MSE_SAT_SLOT_COUNT2_STATUS 8 13 DP_MSE_SAT_SRC3_STATUS 16 18 DP_MSE_SAT_SLOT_COUNT3_STATUS 24 29 mmDP5_DP_MSE_SAT2_STATUS 0 0x2649 4 0 2 DP_MSE_SAT_SRC4_STATUS 0 2 DP_MSE_SAT_SLOT_COUNT4_STATUS 8 13 DP_MSE_SAT_SRC5_STATUS 16 18 DP_MSE_SAT_SLOT_COUNT5_STATUS 24 29 mmDP5_DP_MSA_TIMING_PARAM1 0 0x264c 2 0 2 DP_MSA_VTOTAL 0 15 DP_MSA_HTOTAL 16 31 mmDP5_DP_MSA_TIMING_PARAM2 0 0x264d 2 0 2 DP_MSA_VSTART 0 15 DP_MSA_HSTART 16 31 mmDP5_DP_MSA_TIMING_PARAM3 0 0x264e 4 0 2 DP_MSA_VSYNCWIDTH 0 14 DP_MSA_VSYNCPOLARITY 15 15 DP_MSA_HSYNCWIDTH 16 30 DP_MSA_HSYNCPOLARITY 31 31 mmDP5_DP_MSA_TIMING_PARAM4 0 0x264f 2 0 2 DP_MSA_VHEIGHT 0 15 DP_MSA_HWIDTH 16 31 mmDP5_DP_MSO_CNTL 0 0x2650 8 0 2 DP_MSO_NUM_OF_SSTLINK 0 1 DP_MSO_SEC_STREAM_ENABLE 4 7 DP_MSO_SEC_ASP_ENABLE 8 11 DP_MSO_SEC_ATP_ENABLE 12 15 DP_MSO_SEC_AIP_ENABLE 16 19 DP_MSO_SEC_ACM_ENABLE 20 23 DP_MSO_SEC_GSP0_ENABLE 24 27 DP_MSO_SEC_GSP1_ENABLE 28 31 mmDP5_DP_MSO_CNTL1 0 0x2651 8 0 2 DP_MSO_SEC_GSP2_ENABLE 0 3 DP_MSO_SEC_GSP3_ENABLE 4 7 DP_MSO_SEC_GSP4_ENABLE 8 11 DP_MSO_SEC_GSP5_ENABLE 12 15 DP_MSO_SEC_GSP6_ENABLE 16 19 DP_MSO_SEC_GSP7_ENABLE 20 23 DP_MSO_SEC_MPG_ENABLE 24 27 DP_MSO_SEC_ISRC_ENABLE 28 31 mmDP5_DP_DSC_CNTL 0 0x2652 1 0 2 DP_DSC_EN 0 0 mmDP5_DP_SEC_CNTL2 0 0x2653 29 0 2 DP_SEC_GSP1_SEND 0 0 DP_SEC_GSP1_SEND_PENDING 1 1 DP_SEC_GSP1_SEND_DEADLINE_MISSED 2 2 DP_SEC_GSP1_SEND_ANY_LINE 3 3 DP_SEC_GSP2_SEND 4 4 DP_SEC_GSP2_SEND_PENDING 5 5 DP_SEC_GSP2_SEND_DEADLINE_MISSED 6 6 DP_SEC_GSP2_SEND_ANY_LINE 7 7 DP_SEC_GSP3_SEND 8 8 DP_SEC_GSP3_SEND_PENDING 9 9 DP_SEC_GSP3_SEND_DEADLINE_MISSED 10 10 DP_SEC_GSP3_SEND_ANY_LINE 11 11 DP_SEC_GSP4_SEND 12 12 DP_SEC_GSP4_SEND_PENDING 13 13 DP_SEC_GSP4_SEND_DEADLINE_MISSED 14 14 DP_SEC_GSP4_SEND_ANY_LINE 15 15 DP_SEC_GSP5_SEND 16 16 DP_SEC_GSP5_SEND_PENDING 17 17 DP_SEC_GSP5_SEND_DEADLINE_MISSED 18 18 DP_SEC_GSP5_SEND_ANY_LINE 19 19 DP_SEC_GSP6_SEND 20 20 DP_SEC_GSP6_SEND_PENDING 21 21 DP_SEC_GSP6_SEND_DEADLINE_MISSED 22 22 DP_SEC_GSP6_SEND_ANY_LINE 23 23 DP_SEC_GSP7_SEND 24 24 DP_SEC_GSP7_SEND_PENDING 25 25 DP_SEC_GSP7_SEND_DEADLINE_MISSED 26 26 DP_SEC_GSP7_SEND_ANY_LINE 27 27 DP_SEC_GSP7_PPS 28 28 mmDP5_DP_SEC_CNTL3 0 0x2654 2 0 2 DP_SEC_GSP1_LINE_NUM 0 15 DP_SEC_GSP2_LINE_NUM 16 31 mmDP5_DP_SEC_CNTL4 0 0x2655 2 0 2 DP_SEC_GSP3_LINE_NUM 0 15 DP_SEC_GSP4_LINE_NUM 16 31 mmDP5_DP_SEC_CNTL5 0 0x2656 2 0 2 DP_SEC_GSP5_LINE_NUM 0 15 DP_SEC_GSP6_LINE_NUM 16 31 mmDP5_DP_SEC_CNTL6 0 0x2657 1 0 2 DP_SEC_GSP7_LINE_NUM 0 15 mmDP5_DP_SEC_CNTL7 0 0x2658 8 0 2 DP_SEC_GSP0_SEND_ACTIVE 0 0 DP_SEC_GSP1_SEND_ACTIVE 4 4 DP_SEC_GSP2_SEND_ACTIVE 8 8 DP_SEC_GSP3_SEND_ACTIVE 12 12 DP_SEC_GSP4_SEND_ACTIVE 16 16 DP_SEC_GSP5_SEND_ACTIVE 20 20 DP_SEC_GSP6_SEND_ACTIVE 24 24 DP_SEC_GSP7_SEND_ACTIVE 28 28 mmDP5_DP_DB_CNTL 0 0x2659 5 0 2 DP_DB_PENDING 0 0 DP_DB_TAKEN 4 4 DP_DB_TAKEN_CLR 5 5 DP_DB_LOCK 8 8 DP_DB_DISABLE 12 12 mmDP5_DP_MSA_VBID_MISC 0 0x265a 6 0 2 DP_MSA_MISC1_STEREOSYNC_OVERRIDE 0 1 DP_MSA_MISC1_STEREOSYNC_OVERRIDE_EN 4 4 DP_VBID1_OVERRIDE 8 8 DP_VBID2_OVERRIDE 9 9 DP_VBID1_OVERRIDE_EN 12 12 DP_VBID2_OVERRIDE_EN 13 13 mmDIG6_DIG_FE_CNTL 0 0x2668 8 0 2 DIG_SOURCE_SELECT 0 2 DIG_STEREOSYNC_SELECT 4 6 DIG_STEREOSYNC_GATE_EN 8 8 DIG_START 10 10 DIG_DIGITAL_BYPASS_SELECT 12 14 DIG_SYMCLK_FE_ON 24 24 TMDS_PIXEL_ENCODING 28 28 TMDS_COLOR_FORMAT 30 31 mmDIG6_DIG_OUTPUT_CRC_CNTL 0 0x2669 3 0 2 DIG_OUTPUT_CRC_EN 0 0 DIG_OUTPUT_CRC_LINK_SEL 4 4 DIG_OUTPUT_CRC_DATA_SEL 8 9 mmDIG6_DIG_OUTPUT_CRC_RESULT 0 0x266a 1 0 2 DIG_OUTPUT_CRC_RESULT 0 29 mmDIG6_DIG_CLOCK_PATTERN 0 0x266b 1 0 2 DIG_CLOCK_PATTERN 0 9 mmDIG6_DIG_TEST_PATTERN 0 0x266c 6 0 2 DIG_TEST_PATTERN_OUT_EN 0 0 DIG_HALF_CLOCK_PATTERN_SEL 1 1 DIG_RANDOM_PATTERN_OUT_EN 4 4 DIG_RANDOM_PATTERN_RESET 5 5 DIG_TEST_PATTERN_EXTERNAL_RESET_EN 6 6 DIG_STATIC_TEST_PATTERN 16 25 mmDIG6_DIG_RANDOM_PATTERN_SEED 0 0x266d 2 0 2 DIG_RANDOM_PATTERN_SEED 0 23 DIG_RAN_PAT_DURING_DE_ONLY 24 24 mmDIG6_DIG_FIFO_STATUS 0 0x266e 11 0 2 DIG_FIFO_LEVEL_ERROR 0 0 DIG_FIFO_USE_OVERWRITE_LEVEL 1 1 DIG_FIFO_OVERWRITE_LEVEL 2 7 DIG_FIFO_ERROR_ACK 8 8 DIG_FIFO_CAL_AVERAGE_LEVEL 10 15 DIG_FIFO_MAXIMUM_LEVEL 16 20 DIG_FIFO_MINIMUM_LEVEL 22 25 DIG_FIFO_READ_CLOCK_SRC 26 26 DIG_FIFO_CALIBRATED 29 29 DIG_FIFO_FORCE_RECAL_AVERAGE 30 30 DIG_FIFO_FORCE_RECOMP_MINMAX 31 31 mmDIG6_HDMI_CONTROL 0 0x2671 9 0 2 HDMI_KEEPOUT_MODE 0 0 HDMI_DATA_SCRAMBLE_EN 1 1 HDMI_CLOCK_CHANNEL_RATE 2 2 HDMI_NO_EXTRA_NULL_PACKET_FILLED 3 3 HDMI_PACKET_GEN_VERSION 4 4 HDMI_ERROR_ACK 8 8 HDMI_ERROR_MASK 9 9 HDMI_DEEP_COLOR_ENABLE 24 24 HDMI_DEEP_COLOR_DEPTH 28 29 mmDIG6_HDMI_STATUS 0 0x2672 4 0 2 HDMI_ACTIVE_AVMUTE 0 0 HDMI_AUDIO_PACKET_ERROR 16 16 HDMI_VBI_PACKET_ERROR 20 20 HDMI_ERROR_INT 27 27 mmDIG6_HDMI_AUDIO_PACKET_CONTROL 0 0x2673 2 0 2 HDMI_AUDIO_DELAY_EN 4 5 HDMI_AUDIO_PACKETS_PER_LINE 16 20 mmDIG6_HDMI_ACR_PACKET_CONTROL 0 0x2674 7 0 2 HDMI_ACR_SEND 0 0 HDMI_ACR_CONT 1 1 HDMI_ACR_SELECT 4 5 HDMI_ACR_SOURCE 8 8 HDMI_ACR_AUTO_SEND 12 12 HDMI_ACR_N_MULTIPLE 16 18 HDMI_ACR_AUDIO_PRIORITY 31 31 mmDIG6_HDMI_VBI_PACKET_CONTROL 0 0x2675 6 0 2 HDMI_NULL_SEND 0 0 HDMI_GC_SEND 4 4 HDMI_GC_CONT 5 5 HDMI_ISRC_SEND 8 8 HDMI_ISRC_CONT 9 9 HDMI_ISRC_LINE 16 21 mmDIG6_HDMI_INFOFRAME_CONTROL0 0 0x2676 4 0 2 HDMI_AUDIO_INFO_SEND 4 4 HDMI_AUDIO_INFO_CONT 5 5 HDMI_MPEG_INFO_SEND 8 8 HDMI_MPEG_INFO_CONT 9 9 mmDIG6_HDMI_INFOFRAME_CONTROL1 0 0x2677 2 0 2 HDMI_AUDIO_INFO_LINE 8 13 HDMI_MPEG_INFO_LINE 16 21 mmDIG6_HDMI_GENERIC_PACKET_CONTROL0 0 0x2678 6 0 2 HDMI_GENERIC0_SEND 0 0 HDMI_GENERIC0_CONT 1 1 HDMI_GENERIC1_SEND 4 4 HDMI_GENERIC1_CONT 5 5 HDMI_GENERIC0_LINE 16 21 HDMI_GENERIC1_LINE 24 29 mmDIG6_AFMT_INTERRUPT_STATUS 0 0x2679 0 0 2 mmDIG6_HDMI_GC 0 0x267b 5 0 2 HDMI_GC_AVMUTE 0 0 HDMI_GC_AVMUTE_CONT 2 2 HDMI_DEFAULT_PHASE 4 4 HDMI_PACKING_PHASE 8 11 HDMI_PACKING_PHASE_OVERRIDE 12 12 mmDIG6_AFMT_AUDIO_PACKET_CONTROL2 0 0x267c 6 0 2 AFMT_AUDIO_LAYOUT_OVRD 0 0 AFMT_AUDIO_LAYOUT_SELECT 1 1 AFMT_AUDIO_CHANNEL_ENABLE 8 15 AFMT_DP_AUDIO_STREAM_ID 16 23 AFMT_HBR_ENABLE_OVRD 24 24 AFMT_60958_OSF_OVRD 28 28 mmDIG6_AFMT_ISRC1_0 0 0x267d 3 0 2 AFMT_ISRC_STATUS 0 2 AFMT_ISRC_CONTINUE 6 6 AFMT_ISRC_VALID 7 7 mmDIG6_AFMT_ISRC1_1 0 0x267e 4 0 2 AFMT_UPC_EAN_ISRC0 0 7 AFMT_UPC_EAN_ISRC1 8 15 AFMT_UPC_EAN_ISRC2 16 23 AFMT_UPC_EAN_ISRC3 24 31 mmDIG6_AFMT_ISRC1_2 0 0x267f 4 0 2 AFMT_UPC_EAN_ISRC4 0 7 AFMT_UPC_EAN_ISRC5 8 15 AFMT_UPC_EAN_ISRC6 16 23 AFMT_UPC_EAN_ISRC7 24 31 mmDIG6_AFMT_ISRC1_3 0 0x2680 4 0 2 AFMT_UPC_EAN_ISRC8 0 7 AFMT_UPC_EAN_ISRC9 8 15 AFMT_UPC_EAN_ISRC10 16 23 AFMT_UPC_EAN_ISRC11 24 31 mmDIG6_AFMT_ISRC1_4 0 0x2681 4 0 2 AFMT_UPC_EAN_ISRC12 0 7 AFMT_UPC_EAN_ISRC13 8 15 AFMT_UPC_EAN_ISRC14 16 23 AFMT_UPC_EAN_ISRC15 24 31 mmDIG6_AFMT_ISRC2_0 0 0x2682 4 0 2 AFMT_UPC_EAN_ISRC16 0 7 AFMT_UPC_EAN_ISRC17 8 15 AFMT_UPC_EAN_ISRC18 16 23 AFMT_UPC_EAN_ISRC19 24 31 mmDIG6_AFMT_ISRC2_1 0 0x2683 4 0 2 AFMT_UPC_EAN_ISRC20 0 7 AFMT_UPC_EAN_ISRC21 8 15 AFMT_UPC_EAN_ISRC22 16 23 AFMT_UPC_EAN_ISRC23 24 31 mmDIG6_AFMT_ISRC2_2 0 0x2684 4 0 2 AFMT_UPC_EAN_ISRC24 0 7 AFMT_UPC_EAN_ISRC25 8 15 AFMT_UPC_EAN_ISRC26 16 23 AFMT_UPC_EAN_ISRC27 24 31 mmDIG6_AFMT_ISRC2_3 0 0x2685 4 0 2 AFMT_UPC_EAN_ISRC28 0 7 AFMT_UPC_EAN_ISRC29 8 15 AFMT_UPC_EAN_ISRC30 16 23 AFMT_UPC_EAN_ISRC31 24 31 mmDIG6_HDMI_GENERIC_PACKET_CONTROL2 0 0x2686 6 0 2 HDMI_GENERIC4_SEND 0 0 HDMI_GENERIC4_CONT 1 1 HDMI_GENERIC5_SEND 4 4 HDMI_GENERIC5_CONT 5 5 HDMI_GENERIC4_LINE 16 21 HDMI_GENERIC5_LINE 24 29 mmDIG6_HDMI_GENERIC_PACKET_CONTROL3 0 0x2687 6 0 2 HDMI_GENERIC6_SEND 0 0 HDMI_GENERIC6_CONT 1 1 HDMI_GENERIC7_SEND 4 4 HDMI_GENERIC7_CONT 5 5 HDMI_GENERIC6_LINE 16 21 HDMI_GENERIC7_LINE 24 29 mmDIG6_HDMI_DB_CONTROL 0 0x2688 5 0 2 HDMI_DB_PENDING 0 0 HDMI_DB_TAKEN 4 4 HDMI_DB_TAKEN_CLR 5 5 HDMI_DB_LOCK 8 8 HDMI_DB_DISABLE 12 12 mmDIG6_AFMT_MPEG_INFO0 0 0x268a 4 0 2 AFMT_MPEG_INFO_CHECKSUM 0 7 AFMT_MPEG_INFO_MB0 8 15 AFMT_MPEG_INFO_MB1 16 23 AFMT_MPEG_INFO_MB2 24 31 mmDIG6_AFMT_MPEG_INFO1 0 0x268b 3 0 2 AFMT_MPEG_INFO_MB3 0 7 AFMT_MPEG_INFO_MF 8 9 AFMT_MPEG_INFO_FR 12 12 mmDIG6_AFMT_GENERIC_HDR 0 0x268c 4 0 2 AFMT_GENERIC_HB0 0 7 AFMT_GENERIC_HB1 8 15 AFMT_GENERIC_HB2 16 23 AFMT_GENERIC_HB3 24 31 mmDIG6_AFMT_GENERIC_0 0 0x268d 4 0 2 AFMT_GENERIC_BYTE0 0 7 AFMT_GENERIC_BYTE1 8 15 AFMT_GENERIC_BYTE2 16 23 AFMT_GENERIC_BYTE3 24 31 mmDIG6_AFMT_GENERIC_1 0 0x268e 4 0 2 AFMT_GENERIC_BYTE4 0 7 AFMT_GENERIC_BYTE5 8 15 AFMT_GENERIC_BYTE6 16 23 AFMT_GENERIC_BYTE7 24 31 mmDIG6_AFMT_GENERIC_2 0 0x268f 4 0 2 AFMT_GENERIC_BYTE8 0 7 AFMT_GENERIC_BYTE9 8 15 AFMT_GENERIC_BYTE10 16 23 AFMT_GENERIC_BYTE11 24 31 mmDIG6_AFMT_GENERIC_3 0 0x2690 4 0 2 AFMT_GENERIC_BYTE12 0 7 AFMT_GENERIC_BYTE13 8 15 AFMT_GENERIC_BYTE14 16 23 AFMT_GENERIC_BYTE15 24 31 mmDIG6_AFMT_GENERIC_4 0 0x2691 4 0 2 AFMT_GENERIC_BYTE16 0 7 AFMT_GENERIC_BYTE17 8 15 AFMT_GENERIC_BYTE18 16 23 AFMT_GENERIC_BYTE19 24 31 mmDIG6_AFMT_GENERIC_5 0 0x2692 4 0 2 AFMT_GENERIC_BYTE20 0 7 AFMT_GENERIC_BYTE21 8 15 AFMT_GENERIC_BYTE22 16 23 AFMT_GENERIC_BYTE23 24 31 mmDIG6_AFMT_GENERIC_6 0 0x2693 4 0 2 AFMT_GENERIC_BYTE24 0 7 AFMT_GENERIC_BYTE25 8 15 AFMT_GENERIC_BYTE26 16 23 AFMT_GENERIC_BYTE27 24 31 mmDIG6_AFMT_GENERIC_7 0 0x2694 4 0 2 AFMT_GENERIC_BYTE28 0 7 AFMT_GENERIC_BYTE29 8 15 AFMT_GENERIC_BYTE30 16 23 AFMT_GENERIC_BYTE31 24 31 mmDIG6_HDMI_GENERIC_PACKET_CONTROL1 0 0x2695 6 0 2 HDMI_GENERIC2_SEND 0 0 HDMI_GENERIC2_CONT 1 1 HDMI_GENERIC3_SEND 4 4 HDMI_GENERIC3_CONT 5 5 HDMI_GENERIC2_LINE 16 21 HDMI_GENERIC3_LINE 24 29 mmDIG6_HDMI_ACR_32_0 0 0x2696 1 0 2 HDMI_ACR_CTS_32 12 31 mmDIG6_HDMI_ACR_32_1 0 0x2697 1 0 2 HDMI_ACR_N_32 0 19 mmDIG6_HDMI_ACR_44_0 0 0x2698 1 0 2 HDMI_ACR_CTS_44 12 31 mmDIG6_HDMI_ACR_44_1 0 0x2699 1 0 2 HDMI_ACR_N_44 0 19 mmDIG6_HDMI_ACR_48_0 0 0x269a 1 0 2 HDMI_ACR_CTS_48 12 31 mmDIG6_HDMI_ACR_48_1 0 0x269b 1 0 2 HDMI_ACR_N_48 0 19 mmDIG6_HDMI_ACR_STATUS_0 0 0x269c 1 0 2 HDMI_ACR_CTS 12 31 mmDIG6_HDMI_ACR_STATUS_1 0 0x269d 1 0 2 HDMI_ACR_N 0 19 mmDIG6_AFMT_AUDIO_INFO0 0 0x269e 5 0 2 AFMT_AUDIO_INFO_CHECKSUM 0 7 AFMT_AUDIO_INFO_CC 8 10 AFMT_AUDIO_INFO_CT 11 14 AFMT_AUDIO_INFO_CHECKSUM_OFFSET 16 23 AFMT_AUDIO_INFO_CXT 24 28 mmDIG6_AFMT_AUDIO_INFO1 0 0x269f 4 0 2 AFMT_AUDIO_INFO_CA 0 7 AFMT_AUDIO_INFO_LSV 11 14 AFMT_AUDIO_INFO_DM_INH 15 15 AFMT_AUDIO_INFO_LFEPBL 16 17 mmDIG6_AFMT_60958_0 0 0x26a0 10 0 2 AFMT_60958_CS_A 0 0 AFMT_60958_CS_B 1 1 AFMT_60958_CS_C 2 2 AFMT_60958_CS_D 3 5 AFMT_60958_CS_MODE 6 7 AFMT_60958_CS_CATEGORY_CODE 8 15 AFMT_60958_CS_SOURCE_NUMBER 16 19 AFMT_60958_CS_CHANNEL_NUMBER_L 20 23 AFMT_60958_CS_SAMPLING_FREQUENCY 24 27 AFMT_60958_CS_CLOCK_ACCURACY 28 29 mmDIG6_AFMT_60958_1 0 0x26a1 5 0 2 AFMT_60958_CS_WORD_LENGTH 0 3 AFMT_60958_CS_ORIGINAL_SAMPLING_FREQUENCY 4 7 AFMT_60958_VALID_L 16 16 AFMT_60958_VALID_R 18 18 AFMT_60958_CS_CHANNEL_NUMBER_R 20 23 mmDIG6_AFMT_AUDIO_CRC_CONTROL 0 0x26a2 5 0 2 AFMT_AUDIO_CRC_EN 0 0 AFMT_AUDIO_CRC_CONT 4 4 AFMT_AUDIO_CRC_SOURCE 8 8 AFMT_AUDIO_CRC_CH_SEL 12 15 AFMT_AUDIO_CRC_COUNT 16 31 mmDIG6_AFMT_RAMP_CONTROL0 0 0x26a3 2 0 2 AFMT_RAMP_MAX_COUNT 0 23 AFMT_RAMP_DATA_SIGN 31 31 mmDIG6_AFMT_RAMP_CONTROL1 0 0x26a4 2 0 2 AFMT_RAMP_MIN_COUNT 0 23 AFMT_AUDIO_TEST_CH_DISABLE 24 31 mmDIG6_AFMT_RAMP_CONTROL2 0 0x26a5 1 0 2 AFMT_RAMP_INC_COUNT 0 23 mmDIG6_AFMT_RAMP_CONTROL3 0 0x26a6 1 0 2 AFMT_RAMP_DEC_COUNT 0 23 mmDIG6_AFMT_60958_2 0 0x26a7 6 0 2 AFMT_60958_CS_CHANNEL_NUMBER_2 0 3 AFMT_60958_CS_CHANNEL_NUMBER_3 4 7 AFMT_60958_CS_CHANNEL_NUMBER_4 8 11 AFMT_60958_CS_CHANNEL_NUMBER_5 12 15 AFMT_60958_CS_CHANNEL_NUMBER_6 16 19 AFMT_60958_CS_CHANNEL_NUMBER_7 20 23 mmDIG6_AFMT_AUDIO_CRC_RESULT 0 0x26a8 2 0 2 AFMT_AUDIO_CRC_DONE 0 0 AFMT_AUDIO_CRC 8 31 mmDIG6_AFMT_STATUS 0 0x26a9 4 0 2 AFMT_AUDIO_ENABLE 4 4 AFMT_AZ_HBR_ENABLE 8 8 AFMT_AUDIO_FIFO_OVERFLOW 24 24 AFMT_AZ_AUDIO_ENABLE_CHG 30 30 mmDIG6_AFMT_AUDIO_PACKET_CONTROL 0 0x26aa 8 0 2 AFMT_AUDIO_SAMPLE_SEND 0 0 AFMT_RESET_FIFO_WHEN_AUDIO_DIS 11 11 AFMT_AUDIO_TEST_EN 12 12 AFMT_AUDIO_TEST_MODE 14 14 AFMT_AUDIO_FIFO_OVERFLOW_ACK 23 23 AFMT_AUDIO_CHANNEL_SWAP 24 24 AFMT_60958_CS_UPDATE 26 26 AFMT_AZ_AUDIO_ENABLE_CHG_ACK 30 30 mmDIG6_AFMT_VBI_PACKET_CONTROL 0 0x26ab 4 0 2 AFMT_GENERIC_LOCK_STATUS 8 8 AFMT_GENERIC_CONFLICT 16 16 AFMT_GENERIC_CONFLICT_CLR 17 17 AFMT_GENERIC_INDEX 28 31 mmDIG6_AFMT_INFOFRAME_CONTROL0 0 0x26ac 3 0 2 AFMT_AUDIO_INFO_SOURCE 6 6 AFMT_AUDIO_INFO_UPDATE 7 7 AFMT_MPEG_INFO_UPDATE 10 10 mmDIG6_AFMT_AUDIO_SRC_CONTROL 0 0x26ad 1 0 2 AFMT_AUDIO_SRC_SELECT 0 2 mmDIG6_DIG_BE_CNTL 0 0x26af 5 0 2 DIG_DUAL_LINK_ENABLE 0 0 DIG_SWAP 1 1 DIG_FE_SOURCE_SELECT 8 14 DIG_MODE 16 18 DIG_HPD_SELECT 28 30 mmDIG6_DIG_BE_EN_CNTL 0 0x26b0 2 0 2 DIG_ENABLE 0 0 DIG_SYMCLK_BE_ON 8 8 mmDIG6_TMDS_CNTL 0 0x26d3 1 0 2 TMDS_SYNC_PHASE 0 0 mmDIG6_TMDS_CONTROL_CHAR 0 0x26d4 4 0 2 TMDS_CONTROL_CHAR0_OUT_EN 0 0 TMDS_CONTROL_CHAR1_OUT_EN 1 1 TMDS_CONTROL_CHAR2_OUT_EN 2 2 TMDS_CONTROL_CHAR3_OUT_EN 3 3 mmDIG6_TMDS_CONTROL0_FEEDBACK 0 0x26d5 2 0 2 TMDS_CONTROL0_FEEDBACK_SELECT 0 1 TMDS_CONTROL0_FEEDBACK_DELAY 8 9 mmDIG6_TMDS_STEREOSYNC_CTL_SEL 0 0x26d6 1 0 2 TMDS_STEREOSYNC_CTL_SEL 0 1 mmDIG6_TMDS_SYNC_CHAR_PATTERN_0_1 0 0x26d7 2 0 2 TMDS_SYNC_CHAR_PATTERN0 0 9 TMDS_SYNC_CHAR_PATTERN1 16 25 mmDIG6_TMDS_SYNC_CHAR_PATTERN_2_3 0 0x26d8 2 0 2 TMDS_SYNC_CHAR_PATTERN2 0 9 TMDS_SYNC_CHAR_PATTERN3 16 25 mmDIG6_TMDS_CTL_BITS 0 0x26da 4 0 2 TMDS_CTL0 0 0 TMDS_CTL1 8 8 TMDS_CTL2 16 16 TMDS_CTL3 24 24 mmDIG6_TMDS_DCBALANCER_CONTROL 0 0x26db 4 0 2 TMDS_DCBALANCER_EN 0 0 TMDS_DCBALANCER_TEST_EN 8 8 TMDS_DCBALANCER_TEST_IN 16 19 TMDS_DCBALANCER_FORCE 24 24 mmDIG6_TMDS_CTL0_1_GEN_CNTL 0 0x26dd 15 0 2 TMDS_CTL0_DATA_SEL 0 3 TMDS_CTL0_DATA_DELAY 4 6 TMDS_CTL0_DATA_INVERT 7 7 TMDS_CTL0_DATA_MODULATION 8 9 TMDS_CTL0_USE_FEEDBACK_PATH 10 10 TMDS_CTL0_FB_SYNC_CONT 11 11 TMDS_CTL0_PATTERN_OUT_EN 12 12 TMDS_CTL1_DATA_SEL 16 19 TMDS_CTL1_DATA_DELAY 20 22 TMDS_CTL1_DATA_INVERT 23 23 TMDS_CTL1_DATA_MODULATION 24 25 TMDS_CTL1_USE_FEEDBACK_PATH 26 26 TMDS_CTL1_FB_SYNC_CONT 27 27 TMDS_CTL1_PATTERN_OUT_EN 28 28 TMDS_2BIT_COUNTER_EN 31 31 mmDIG6_TMDS_CTL2_3_GEN_CNTL 0 0x26de 14 0 2 TMDS_CTL2_DATA_SEL 0 3 TMDS_CTL2_DATA_DELAY 4 6 TMDS_CTL2_DATA_INVERT 7 7 TMDS_CTL2_DATA_MODULATION 8 9 TMDS_CTL2_USE_FEEDBACK_PATH 10 10 TMDS_CTL2_FB_SYNC_CONT 11 11 TMDS_CTL2_PATTERN_OUT_EN 12 12 TMDS_CTL3_DATA_SEL 16 19 TMDS_CTL3_DATA_DELAY 20 22 TMDS_CTL3_DATA_INVERT 23 23 TMDS_CTL3_DATA_MODULATION 24 25 TMDS_CTL3_USE_FEEDBACK_PATH 26 26 TMDS_CTL3_FB_SYNC_CONT 27 27 TMDS_CTL3_PATTERN_OUT_EN 28 28 mmDIG6_DIG_VERSION 0 0x26e0 1 0 2 DIG_TYPE 0 0 mmDIG6_DIG_LANE_ENABLE 0 0x26e1 5 0 2 DIG_LANE0EN 0 0 DIG_LANE1EN 1 1 DIG_LANE2EN 2 2 DIG_LANE3EN 3 3 DIG_CLK_EN 8 8 mmDIG6_AFMT_CNTL 0 0x26e6 2 0 2 AFMT_AUDIO_CLOCK_EN 0 0 AFMT_AUDIO_CLOCK_ON 8 8 mmDIG6_AFMT_VBI_PACKET_CONTROL1 0 0x26e7 32 0 2 AFMT_GENERIC0_FRAME_UPDATE 0 0 AFMT_GENERIC0_FRAME_UPDATE_PENDING 1 1 AFMT_GENERIC0_IMMEDIATE_UPDATE 2 2 AFMT_GENERIC0_IMMEDIATE_UPDATE_PENDING 3 3 AFMT_GENERIC1_FRAME_UPDATE 4 4 AFMT_GENERIC1_FRAME_UPDATE_PENDING 5 5 AFMT_GENERIC1_IMMEDIATE_UPDATE 6 6 AFMT_GENERIC1_IMMEDIATE_UPDATE_PENDING 7 7 AFMT_GENERIC2_FRAME_UPDATE 8 8 AFMT_GENERIC2_FRAME_UPDATE_PENDING 9 9 AFMT_GENERIC2_IMMEDIATE_UPDATE 10 10 AFMT_GENERIC2_IMMEDIATE_UPDATE_PENDING 11 11 AFMT_GENERIC3_FRAME_UPDATE 12 12 AFMT_GENERIC3_FRAME_UPDATE_PENDING 13 13 AFMT_GENERIC3_IMMEDIATE_UPDATE 14 14 AFMT_GENERIC3_IMMEDIATE_UPDATE_PENDING 15 15 AFMT_GENERIC4_FRAME_UPDATE 16 16 AFMT_GENERIC4_FRAME_UPDATE_PENDING 17 17 AFMT_GENERIC4_IMMEDIATE_UPDATE 18 18 AFMT_GENERIC4_IMMEDIATE_UPDATE_PENDING 19 19 AFMT_GENERIC5_FRAME_UPDATE 20 20 AFMT_GENERIC5_FRAME_UPDATE_PENDING 21 21 AFMT_GENERIC5_IMMEDIATE_UPDATE 22 22 AFMT_GENERIC5_IMMEDIATE_UPDATE_PENDING 23 23 AFMT_GENERIC6_FRAME_UPDATE 24 24 AFMT_GENERIC6_FRAME_UPDATE_PENDING 25 25 AFMT_GENERIC6_IMMEDIATE_UPDATE 26 26 AFMT_GENERIC6_IMMEDIATE_UPDATE_PENDING 27 27 AFMT_GENERIC7_FRAME_UPDATE 28 28 AFMT_GENERIC7_FRAME_UPDATE_PENDING 29 29 AFMT_GENERIC7_IMMEDIATE_UPDATE 30 30 AFMT_GENERIC7_IMMEDIATE_UPDATE_PENDING 31 31 mmDP6_DP_LINK_CNTL 0 0x2708 3 0 2 DP_LINK_TRAINING_COMPLETE 4 4 DP_LINK_STATUS 8 8 DP_EMBEDDED_PANEL_MODE 17 17 mmDP6_DP_PIXEL_FORMAT 0 0x2709 3 0 2 DP_PIXEL_ENCODING 0 2 DP_COMPONENT_DEPTH 24 26 DP_PIXEL_COMBINE 28 29 mmDP6_DP_MSA_COLORIMETRY 0 0x270a 1 0 2 DP_MSA_MISC0 24 31 mmDP6_DP_CONFIG 0 0x270b 1 0 2 DP_UDI_LANES 0 1 mmDP6_DP_VID_STREAM_CNTL 0 0x270c 4 0 2 DP_VID_STREAM_ENABLE 0 0 DP_VID_STREAM_DIS_DEFER 8 9 DP_VID_STREAM_STATUS 16 16 DP_VID_STREAM_CHANGE_KEEPOUT 20 20 mmDP6_DP_STEER_FIFO 0 0x270d 7 0 2 DP_STEER_FIFO_RESET 0 0 DP_STEER_OVERFLOW_FLAG 4 4 DP_STEER_OVERFLOW_INT 5 5 DP_STEER_OVERFLOW_ACK 6 6 DP_STEER_OVERFLOW_MASK 7 7 DP_TU_OVERFLOW_FLAG 8 8 DP_TU_OVERFLOW_ACK 12 12 mmDP6_DP_MSA_MISC 0 0x270e 4 0 2 DP_MSA_MISC1 0 7 DP_MSA_MISC2 8 15 DP_MSA_MISC3 16 23 DP_MSA_MISC4 24 31 mmDP6_DP_VID_TIMING 0 0x2710 5 0 2 DP_VID_M_N_DOUBLE_BUFFER_MODE 4 4 DP_VID_M_N_GEN_EN 8 8 DP_VID_N_MUL 10 11 DP_VID_M_DIV 12 13 DP_VID_N_DIV 24 31 mmDP6_DP_VID_N 0 0x2711 1 0 2 DP_VID_N 0 23 mmDP6_DP_VID_M 0 0x2712 1 0 2 DP_VID_M 0 23 mmDP6_DP_LINK_FRAMING_CNTL 0 0x2713 3 0 2 DP_IDLE_BS_INTERVAL 0 17 DP_VBID_DISABLE 24 24 DP_VID_ENHANCED_FRAME_MODE 28 28 mmDP6_DP_HBR2_EYE_PATTERN 0 0x2714 1 0 2 DP_HBR2_EYE_PATTERN_ENABLE 0 0 mmDP6_DP_VID_MSA_VBID 0 0x2715 2 0 2 DP_VID_MSA_LOCATION 0 11 DP_VID_VBID_FIELD_POL 24 24 mmDP6_DP_VID_INTERRUPT_CNTL 0 0x2716 3 0 2 DP_VID_STREAM_DISABLE_INT 0 0 DP_VID_STREAM_DISABLE_ACK 1 1 DP_VID_STREAM_DISABLE_MASK 2 2 mmDP6_DP_DPHY_CNTL 0 0x2717 6 0 2 DPHY_ATEST_SEL_LANE0 0 0 DPHY_ATEST_SEL_LANE1 1 1 DPHY_ATEST_SEL_LANE2 2 2 DPHY_ATEST_SEL_LANE3 3 3 DPHY_BYPASS 16 16 DPHY_SKEW_BYPASS 24 24 mmDP6_DP_DPHY_TRAINING_PATTERN_SEL 0 0x2718 1 0 2 DPHY_TRAINING_PATTERN_SEL 0 1 mmDP6_DP_DPHY_SYM0 0 0x2719 3 0 2 DPHY_SYM1 0 9 DPHY_SYM2 10 19 DPHY_SYM3 20 29 mmDP6_DP_DPHY_SYM1 0 0x271a 3 0 2 DPHY_SYM4 0 9 DPHY_SYM5 10 19 DPHY_SYM6 20 29 mmDP6_DP_DPHY_SYM2 0 0x271b 2 0 2 DPHY_SYM7 0 9 DPHY_SYM8 10 19 mmDP6_DP_DPHY_8B10B_CNTL 0 0x271c 3 0 2 DPHY_8B10B_RESET 8 8 DPHY_8B10B_EXT_DISP 16 16 DPHY_8B10B_CUR_DISP 24 24 mmDP6_DP_DPHY_PRBS_CNTL 0 0x271d 3 0 2 DPHY_PRBS_EN 0 0 DPHY_PRBS_SEL 4 5 DPHY_PRBS_SEED 8 30 mmDP6_DP_DPHY_SCRAM_CNTL 0 0x271e 4 0 2 DPHY_SCRAMBLER_DIS 0 0 DPHY_SCRAMBLER_ADVANCE 4 4 DPHY_SCRAMBLER_BS_COUNT 8 17 DPHY_SCRAMBLER_KCODE 24 24 mmDP6_DP_DPHY_CRC_EN 0 0x271f 3 0 2 DPHY_CRC_EN 0 0 DPHY_CRC_CONT_EN 4 4 DPHY_CRC_RESULT_VALID 8 8 mmDP6_DP_DPHY_CRC_CNTL 0 0x2720 3 0 2 DPHY_CRC_FIELD 0 0 DPHY_CRC_SEL 4 5 DPHY_CRC_MASK 16 23 mmDP6_DP_DPHY_CRC_RESULT 0 0x2721 4 0 2 DPHY_CRC_RESULT 0 7 DPHY_CRC_RESULT1 8 15 DPHY_CRC_RESULT2 16 23 DPHY_CRC_RESULT3 24 31 mmDP6_DP_DPHY_CRC_MST_CNTL 0 0x2722 2 0 2 DPHY_CRC_MST_FIRST_SLOT 0 5 DPHY_CRC_MST_LAST_SLOT 8 13 mmDP6_DP_DPHY_CRC_MST_STATUS 0 0x2723 3 0 2 DPHY_CRC_MST_PHASE_LOCK 0 0 DPHY_CRC_MST_PHASE_ERROR 8 8 DPHY_CRC_MST_PHASE_ERROR_ACK 16 16 mmDP6_DP_DPHY_FAST_TRAINING 0 0x2724 5 0 2 DPHY_RX_FAST_TRAINING_CAPABLE 0 0 DPHY_SW_FAST_TRAINING_START 1 1 DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN 2 2 DPHY_FAST_TRAINING_TP1_TIME 8 19 DPHY_FAST_TRAINING_TP2_TIME 20 31 mmDP6_DP_DPHY_FAST_TRAINING_STATUS 0 0x2725 4 0 2 DPHY_FAST_TRAINING_STATE 0 2 DPHY_FAST_TRAINING_COMPLETE_OCCURRED 4 4 DPHY_FAST_TRAINING_COMPLETE_MASK 8 8 DPHY_FAST_TRAINING_COMPLETE_ACK 12 12 mmDP6_DP_SEC_CNTL 0 0x272b 14 0 2 DP_SEC_STREAM_ENABLE 0 0 DP_SEC_ASP_ENABLE 4 4 DP_SEC_ATP_ENABLE 8 8 DP_SEC_AIP_ENABLE 12 12 DP_SEC_ACM_ENABLE 16 16 DP_SEC_GSP0_ENABLE 20 20 DP_SEC_GSP1_ENABLE 21 21 DP_SEC_GSP2_ENABLE 22 22 DP_SEC_GSP3_ENABLE 23 23 DP_SEC_GSP4_ENABLE 24 24 DP_SEC_GSP5_ENABLE 25 25 DP_SEC_GSP6_ENABLE 26 26 DP_SEC_GSP7_ENABLE 27 27 DP_SEC_MPG_ENABLE 28 28 mmDP6_DP_SEC_CNTL1 0 0x272c 7 0 2 DP_SEC_ISRC_ENABLE 0 0 DP_SEC_GSP0_PRIORITY 4 4 DP_SEC_GSP0_SEND 5 5 DP_SEC_GSP0_SEND_PENDING 6 6 DP_SEC_GSP0_SEND_DEADLINE_MISSED 7 7 DP_SEC_GSP0_SEND_ANY_LINE 8 8 DP_SEC_GSP0_LINE_NUM 16 31 mmDP6_DP_SEC_FRAMING1 0 0x272d 2 0 2 DP_SEC_FRAME_START_LOCATION 0 11 DP_SEC_VBLANK_TRANSMIT_WIDTH 16 31 mmDP6_DP_SEC_FRAMING2 0 0x272e 2 0 2 DP_SEC_START_POSITION 0 15 DP_SEC_HBLANK_TRANSMIT_WIDTH 16 31 mmDP6_DP_SEC_FRAMING3 0 0x272f 2 0 2 DP_SEC_IDLE_FRAME_SIZE 0 13 DP_SEC_IDLE_TRANSMIT_WIDTH 16 31 mmDP6_DP_SEC_FRAMING4 0 0x2730 4 0 2 DP_SEC_COLLISION_STATUS 20 20 DP_SEC_COLLISION_ACK 24 24 DP_SEC_AUDIO_MUTE 28 28 DP_SEC_AUDIO_MUTE_STATUS 29 29 mmDP6_DP_SEC_AUD_N 0 0x2731 1 0 2 DP_SEC_AUD_N 0 23 mmDP6_DP_SEC_AUD_N_READBACK 0 0x2732 1 0 2 DP_SEC_AUD_N_READBACK 0 23 mmDP6_DP_SEC_AUD_M 0 0x2733 1 0 2 DP_SEC_AUD_M 0 23 mmDP6_DP_SEC_AUD_M_READBACK 0 0x2734 1 0 2 DP_SEC_AUD_M_READBACK 0 23 mmDP6_DP_SEC_TIMESTAMP 0 0x2735 1 0 2 DP_SEC_TIMESTAMP_MODE 0 0 mmDP6_DP_SEC_PACKET_CNTL 0 0x2736 4 0 2 DP_SEC_ASP_CODING_TYPE 1 3 DP_SEC_ASP_PRIORITY 4 4 DP_SEC_VERSION 8 13 DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE 16 16 mmDP6_DP_MSE_RATE_CNTL 0 0x2737 2 0 2 DP_MSE_RATE_Y 0 25 DP_MSE_RATE_X 26 31 mmDP6_DP_MSE_RATE_UPDATE 0 0x2739 1 0 2 DP_MSE_RATE_UPDATE_PENDING 0 0 mmDP6_DP_MSE_SAT0 0 0x273a 4 0 2 DP_MSE_SAT_SRC0 0 2 DP_MSE_SAT_SLOT_COUNT0 8 13 DP_MSE_SAT_SRC1 16 18 DP_MSE_SAT_SLOT_COUNT1 24 29 mmDP6_DP_MSE_SAT1 0 0x273b 4 0 2 DP_MSE_SAT_SRC2 0 2 DP_MSE_SAT_SLOT_COUNT2 8 13 DP_MSE_SAT_SRC3 16 18 DP_MSE_SAT_SLOT_COUNT3 24 29 mmDP6_DP_MSE_SAT2 0 0x273c 4 0 2 DP_MSE_SAT_SRC4 0 2 DP_MSE_SAT_SLOT_COUNT4 8 13 DP_MSE_SAT_SRC5 16 18 DP_MSE_SAT_SLOT_COUNT5 24 29 mmDP6_DP_MSE_SAT_UPDATE 0 0x273d 2 0 2 DP_MSE_SAT_UPDATE 0 1 DP_MSE_16_MTP_KEEPOUT 8 8 mmDP6_DP_MSE_LINK_TIMING 0 0x273e 2 0 2 DP_MSE_LINK_FRAME 0 9 DP_MSE_LINK_LINE 16 17 mmDP6_DP_MSE_MISC_CNTL 0 0x273f 3 0 2 DP_MSE_BLANK_CODE 0 0 DP_MSE_TIMESTAMP_MODE 4 4 DP_MSE_ZERO_ENCODER 8 8 mmDP6_DP_DPHY_BS_SR_SWAP_CNTL 0 0x2744 3 0 2 DPHY_LOAD_BS_COUNT 0 9 DPHY_BS_SR_SWAP_DONE 15 15 DPHY_LOAD_BS_COUNT_START 16 16 mmDP6_DP_DPHY_HBR2_PATTERN_CONTROL 0 0x2745 1 0 2 DP_DPHY_HBR2_PATTERN_CONTROL 0 2 mmDP6_DP_MSE_SAT0_STATUS 0 0x2747 4 0 2 DP_MSE_SAT_SRC0_STATUS 0 2 DP_MSE_SAT_SLOT_COUNT0_STATUS 8 13 DP_MSE_SAT_SRC1_STATUS 16 18 DP_MSE_SAT_SLOT_COUNT1_STATUS 24 29 mmDP6_DP_MSE_SAT1_STATUS 0 0x2748 4 0 2 DP_MSE_SAT_SRC2_STATUS 0 2 DP_MSE_SAT_SLOT_COUNT2_STATUS 8 13 DP_MSE_SAT_SRC3_STATUS 16 18 DP_MSE_SAT_SLOT_COUNT3_STATUS 24 29 mmDP6_DP_MSE_SAT2_STATUS 0 0x2749 4 0 2 DP_MSE_SAT_SRC4_STATUS 0 2 DP_MSE_SAT_SLOT_COUNT4_STATUS 8 13 DP_MSE_SAT_SRC5_STATUS 16 18 DP_MSE_SAT_SLOT_COUNT5_STATUS 24 29 mmDP6_DP_MSA_TIMING_PARAM1 0 0x274c 2 0 2 DP_MSA_VTOTAL 0 15 DP_MSA_HTOTAL 16 31 mmDP6_DP_MSA_TIMING_PARAM2 0 0x274d 2 0 2 DP_MSA_VSTART 0 15 DP_MSA_HSTART 16 31 mmDP6_DP_MSA_TIMING_PARAM3 0 0x274e 4 0 2 DP_MSA_VSYNCWIDTH 0 14 DP_MSA_VSYNCPOLARITY 15 15 DP_MSA_HSYNCWIDTH 16 30 DP_MSA_HSYNCPOLARITY 31 31 mmDP6_DP_MSA_TIMING_PARAM4 0 0x274f 2 0 2 DP_MSA_VHEIGHT 0 15 DP_MSA_HWIDTH 16 31 mmDP6_DP_MSO_CNTL 0 0x2750 8 0 2 DP_MSO_NUM_OF_SSTLINK 0 1 DP_MSO_SEC_STREAM_ENABLE 4 7 DP_MSO_SEC_ASP_ENABLE 8 11 DP_MSO_SEC_ATP_ENABLE 12 15 DP_MSO_SEC_AIP_ENABLE 16 19 DP_MSO_SEC_ACM_ENABLE 20 23 DP_MSO_SEC_GSP0_ENABLE 24 27 DP_MSO_SEC_GSP1_ENABLE 28 31 mmDP6_DP_MSO_CNTL1 0 0x2751 8 0 2 DP_MSO_SEC_GSP2_ENABLE 0 3 DP_MSO_SEC_GSP3_ENABLE 4 7 DP_MSO_SEC_GSP4_ENABLE 8 11 DP_MSO_SEC_GSP5_ENABLE 12 15 DP_MSO_SEC_GSP6_ENABLE 16 19 DP_MSO_SEC_GSP7_ENABLE 20 23 DP_MSO_SEC_MPG_ENABLE 24 27 DP_MSO_SEC_ISRC_ENABLE 28 31 mmDP6_DP_DSC_CNTL 0 0x2752 1 0 2 DP_DSC_EN 0 0 mmDP6_DP_SEC_CNTL2 0 0x2753 29 0 2 DP_SEC_GSP1_SEND 0 0 DP_SEC_GSP1_SEND_PENDING 1 1 DP_SEC_GSP1_SEND_DEADLINE_MISSED 2 2 DP_SEC_GSP1_SEND_ANY_LINE 3 3 DP_SEC_GSP2_SEND 4 4 DP_SEC_GSP2_SEND_PENDING 5 5 DP_SEC_GSP2_SEND_DEADLINE_MISSED 6 6 DP_SEC_GSP2_SEND_ANY_LINE 7 7 DP_SEC_GSP3_SEND 8 8 DP_SEC_GSP3_SEND_PENDING 9 9 DP_SEC_GSP3_SEND_DEADLINE_MISSED 10 10 DP_SEC_GSP3_SEND_ANY_LINE 11 11 DP_SEC_GSP4_SEND 12 12 DP_SEC_GSP4_SEND_PENDING 13 13 DP_SEC_GSP4_SEND_DEADLINE_MISSED 14 14 DP_SEC_GSP4_SEND_ANY_LINE 15 15 DP_SEC_GSP5_SEND 16 16 DP_SEC_GSP5_SEND_PENDING 17 17 DP_SEC_GSP5_SEND_DEADLINE_MISSED 18 18 DP_SEC_GSP5_SEND_ANY_LINE 19 19 DP_SEC_GSP6_SEND 20 20 DP_SEC_GSP6_SEND_PENDING 21 21 DP_SEC_GSP6_SEND_DEADLINE_MISSED 22 22 DP_SEC_GSP6_SEND_ANY_LINE 23 23 DP_SEC_GSP7_SEND 24 24 DP_SEC_GSP7_SEND_PENDING 25 25 DP_SEC_GSP7_SEND_DEADLINE_MISSED 26 26 DP_SEC_GSP7_SEND_ANY_LINE 27 27 DP_SEC_GSP7_PPS 28 28 mmDP6_DP_SEC_CNTL3 0 0x2754 2 0 2 DP_SEC_GSP1_LINE_NUM 0 15 DP_SEC_GSP2_LINE_NUM 16 31 mmDP6_DP_SEC_CNTL4 0 0x2755 2 0 2 DP_SEC_GSP3_LINE_NUM 0 15 DP_SEC_GSP4_LINE_NUM 16 31 mmDP6_DP_SEC_CNTL5 0 0x2756 2 0 2 DP_SEC_GSP5_LINE_NUM 0 15 DP_SEC_GSP6_LINE_NUM 16 31 mmDP6_DP_SEC_CNTL6 0 0x2757 1 0 2 DP_SEC_GSP7_LINE_NUM 0 15 mmDP6_DP_SEC_CNTL7 0 0x2758 8 0 2 DP_SEC_GSP0_SEND_ACTIVE 0 0 DP_SEC_GSP1_SEND_ACTIVE 4 4 DP_SEC_GSP2_SEND_ACTIVE 8 8 DP_SEC_GSP3_SEND_ACTIVE 12 12 DP_SEC_GSP4_SEND_ACTIVE 16 16 DP_SEC_GSP5_SEND_ACTIVE 20 20 DP_SEC_GSP6_SEND_ACTIVE 24 24 DP_SEC_GSP7_SEND_ACTIVE 28 28 mmDP6_DP_DB_CNTL 0 0x2759 5 0 2 DP_DB_PENDING 0 0 DP_DB_TAKEN 4 4 DP_DB_TAKEN_CLR 5 5 DP_DB_LOCK 8 8 DP_DB_DISABLE 12 12 mmDP6_DP_MSA_VBID_MISC 0 0x275a 6 0 2 DP_MSA_MISC1_STEREOSYNC_OVERRIDE 0 1 DP_MSA_MISC1_STEREOSYNC_OVERRIDE_EN 4 4 DP_VBID1_OVERRIDE 8 8 DP_VBID2_OVERRIDE 9 9 DP_VBID1_OVERRIDE_EN 12 12 DP_VBID2_OVERRIDE_EN 13 13 mmDC_GENERICA 0 0x2868 6 0 2 GENERICA_EN 0 0 GENERICA_SEL 7 11 GENERICA_UNIPHY_REFDIV_CLK_SEL 12 15 GENERICA_UNIPHY_FBDIV_CLK_SEL 16 19 GENERICA_UNIPHY_FBDIV_SSC_CLK_SEL 20 23 GENERICA_UNIPHY_FBDIV_CLK_DIV2_SEL 24 27 mmDC_GENERICB 0 0x2869 6 0 2 GENERICB_EN 0 0 GENERICB_SEL 8 11 GENERICB_UNIPHY_REFDIV_CLK_SEL 12 15 GENERICB_UNIPHY_FBDIV_CLK_SEL 16 19 GENERICB_UNIPHY_FBDIV_SSC_CLK_SEL 20 23 GENERICB_UNIPHY_FBDIV_CLK_DIV2_SEL 24 27 mmDC_REF_CLK_CNTL 0 0x286b 2 0 2 HSYNCA_OUTPUT_SEL 0 1 GENLK_CLK_OUTPUT_SEL 8 9 mmDC_GPIO_DEBUG 0 0x286c 5 0 2 DC_GPIO_VIP_DEBUG 0 0 DC_GPIO_MACRO_DEBUG 8 9 DC_GPIO_CHIP_DEBUG_OUT_PIN_SEL 16 16 DC_GPIO_DEBUG_BUS_FLOP_EN 17 17 DPRX_LOOPBACK_ENABLE 31 31 mmUNIPHYA_LINK_CNTL 0 0x286d 9 0 2 UNIPHY_PFREQCHG 0 0 UNIPHY_PIXVLD_RESET 4 4 UNIPHY_MINIMUM_PIXVLD_LOW_DURATION 8 10 UNIPHY_CHANNEL0_INVERT 12 12 UNIPHY_CHANNEL1_INVERT 13 13 UNIPHY_CHANNEL2_INVERT 14 14 UNIPHY_CHANNEL3_INVERT 15 15 UNIPHY_LANE_STAGGER_DELAY 20 22 UNIPHY_LINK_ENABLE_HPD_MASK 24 25 mmUNIPHYA_CHANNEL_XBAR_CNTL 0 0x286e 5 0 2 UNIPHY_CHANNEL0_XBAR_SOURCE 0 1 UNIPHY_CHANNEL1_XBAR_SOURCE 8 9 UNIPHY_CHANNEL2_XBAR_SOURCE 16 17 UNIPHY_CHANNEL3_XBAR_SOURCE 24 25 UNIPHY_LINK_ENABLE 28 28 mmUNIPHYB_LINK_CNTL 0 0x286f 9 0 2 UNIPHY_PFREQCHG 0 0 UNIPHY_PIXVLD_RESET 4 4 UNIPHY_MINIMUM_PIXVLD_LOW_DURATION 8 10 UNIPHY_CHANNEL0_INVERT 12 12 UNIPHY_CHANNEL1_INVERT 13 13 UNIPHY_CHANNEL2_INVERT 14 14 UNIPHY_CHANNEL3_INVERT 15 15 UNIPHY_LANE_STAGGER_DELAY 20 22 UNIPHY_LINK_ENABLE_HPD_MASK 24 25 mmUNIPHYB_CHANNEL_XBAR_CNTL 0 0x2870 5 0 2 UNIPHY_CHANNEL0_XBAR_SOURCE 0 1 UNIPHY_CHANNEL1_XBAR_SOURCE 8 9 UNIPHY_CHANNEL2_XBAR_SOURCE 16 17 UNIPHY_CHANNEL3_XBAR_SOURCE 24 25 UNIPHY_LINK_ENABLE 28 28 mmUNIPHYC_LINK_CNTL 0 0x2871 9 0 2 UNIPHY_PFREQCHG 0 0 UNIPHY_PIXVLD_RESET 4 4 UNIPHY_MINIMUM_PIXVLD_LOW_DURATION 8 10 UNIPHY_CHANNEL0_INVERT 12 12 UNIPHY_CHANNEL1_INVERT 13 13 UNIPHY_CHANNEL2_INVERT 14 14 UNIPHY_CHANNEL3_INVERT 15 15 UNIPHY_LANE_STAGGER_DELAY 20 22 UNIPHY_LINK_ENABLE_HPD_MASK 24 25 mmUNIPHYC_CHANNEL_XBAR_CNTL 0 0x2872 5 0 2 UNIPHY_CHANNEL0_XBAR_SOURCE 0 1 UNIPHY_CHANNEL1_XBAR_SOURCE 8 9 UNIPHY_CHANNEL2_XBAR_SOURCE 16 17 UNIPHY_CHANNEL3_XBAR_SOURCE 24 25 UNIPHY_LINK_ENABLE 28 28 mmUNIPHYD_LINK_CNTL 0 0x2873 9 0 2 UNIPHY_PFREQCHG 0 0 UNIPHY_PIXVLD_RESET 4 4 UNIPHY_MINIMUM_PIXVLD_LOW_DURATION 8 10 UNIPHY_CHANNEL0_INVERT 12 12 UNIPHY_CHANNEL1_INVERT 13 13 UNIPHY_CHANNEL2_INVERT 14 14 UNIPHY_CHANNEL3_INVERT 15 15 UNIPHY_LANE_STAGGER_DELAY 20 22 UNIPHY_LINK_ENABLE_HPD_MASK 24 25 mmUNIPHYD_CHANNEL_XBAR_CNTL 0 0x2874 5 0 2 UNIPHY_CHANNEL0_XBAR_SOURCE 0 1 UNIPHY_CHANNEL1_XBAR_SOURCE 8 9 UNIPHY_CHANNEL2_XBAR_SOURCE 16 17 UNIPHY_CHANNEL3_XBAR_SOURCE 24 25 UNIPHY_LINK_ENABLE 28 28 mmUNIPHYE_LINK_CNTL 0 0x2875 9 0 2 UNIPHY_PFREQCHG 0 0 UNIPHY_PIXVLD_RESET 4 4 UNIPHY_MINIMUM_PIXVLD_LOW_DURATION 8 10 UNIPHY_CHANNEL0_INVERT 12 12 UNIPHY_CHANNEL1_INVERT 13 13 UNIPHY_CHANNEL2_INVERT 14 14 UNIPHY_CHANNEL3_INVERT 15 15 UNIPHY_LANE_STAGGER_DELAY 20 22 UNIPHY_LINK_ENABLE_HPD_MASK 24 25 mmUNIPHYE_CHANNEL_XBAR_CNTL 0 0x2876 5 0 2 UNIPHY_CHANNEL0_XBAR_SOURCE 0 1 UNIPHY_CHANNEL1_XBAR_SOURCE 8 9 UNIPHY_CHANNEL2_XBAR_SOURCE 16 17 UNIPHY_CHANNEL3_XBAR_SOURCE 24 25 UNIPHY_LINK_ENABLE 28 28 mmUNIPHYF_LINK_CNTL 0 0x2877 9 0 2 UNIPHY_PFREQCHG 0 0 UNIPHY_PIXVLD_RESET 4 4 UNIPHY_MINIMUM_PIXVLD_LOW_DURATION 8 10 UNIPHY_CHANNEL0_INVERT 12 12 UNIPHY_CHANNEL1_INVERT 13 13 UNIPHY_CHANNEL2_INVERT 14 14 UNIPHY_CHANNEL3_INVERT 15 15 UNIPHY_LANE_STAGGER_DELAY 20 22 UNIPHY_LINK_ENABLE_HPD_MASK 24 25 mmUNIPHYF_CHANNEL_XBAR_CNTL 0 0x2878 5 0 2 UNIPHY_CHANNEL0_XBAR_SOURCE 0 1 UNIPHY_CHANNEL1_XBAR_SOURCE 8 9 UNIPHY_CHANNEL2_XBAR_SOURCE 16 17 UNIPHY_CHANNEL3_XBAR_SOURCE 24 25 UNIPHY_LINK_ENABLE 28 28 mmUNIPHYG_LINK_CNTL 0 0x2879 9 0 2 UNIPHY_PFREQCHG 0 0 UNIPHY_PIXVLD_RESET 4 4 UNIPHY_MINIMUM_PIXVLD_LOW_DURATION 8 10 UNIPHY_CHANNEL0_INVERT 12 12 UNIPHY_CHANNEL1_INVERT 13 13 UNIPHY_CHANNEL2_INVERT 14 14 UNIPHY_CHANNEL3_INVERT 15 15 UNIPHY_LANE_STAGGER_DELAY 20 22 UNIPHY_LINK_ENABLE_HPD_MASK 24 25 mmUNIPHYG_CHANNEL_XBAR_CNTL 0 0x287a 5 0 2 UNIPHY_CHANNEL0_XBAR_SOURCE 0 1 UNIPHY_CHANNEL1_XBAR_SOURCE 8 9 UNIPHY_CHANNEL2_XBAR_SOURCE 16 17 UNIPHY_CHANNEL3_XBAR_SOURCE 24 25 UNIPHY_LINK_ENABLE 28 28 mmDCIO_WRCMD_DELAY 0 0x287e 5 0 2 UNIPHY_DELAY 0 3 DAC_DELAY 4 7 DPHY_DELAY 8 11 DCRXPHY_DELAY 12 15 ZCAL_DELAY 16 19 mmDC_PINSTRAPS 0 0x2880 1 0 2 DC_PINSTRAPS_AUDIO 14 15 mmDC_DVODATA_CONFIG 0 0x2882 3 0 2 VIP_MUX_EN 19 19 VIP_ALTER_MAPPING_EN 20 20 DVO_ALTER_MAPPING_EN 21 21 mmLVTMA_PWRSEQ_CNTL 0 0x2883 12 0 2 LVTMA_PWRSEQ_EN 0 0 LVTMA_PWRSEQ_DISABLE_SYNCEN_CONTROL_OF_TX_EN 1 1 LVTMA_PWRSEQ_TARGET_STATE 4 4 LVTMA_SYNCEN 8 8 LVTMA_SYNCEN_OVRD 9 9 LVTMA_SYNCEN_POL 10 10 LVTMA_DIGON 16 16 LVTMA_DIGON_OVRD 17 17 LVTMA_DIGON_POL 18 18 LVTMA_BLON 24 24 LVTMA_BLON_OVRD 25 25 LVTMA_BLON_POL 26 26 mmLVTMA_PWRSEQ_STATE 0 0x2884 6 0 2 LVTMA_PWRSEQ_TARGET_STATE_R 0 0 LVTMA_PWRSEQ_DIGON 1 1 LVTMA_PWRSEQ_SYNCEN 2 2 LVTMA_PWRSEQ_BLON 3 3 LVTMA_PWRSEQ_DONE 4 4 LVTMA_PWRSEQ_STATE 8 11 mmLVTMA_PWRSEQ_REF_DIV 0 0x2885 2 0 2 LVTMA_PWRSEQ_REF_DIV 0 11 BL_PWM_REF_DIV 16 31 mmLVTMA_PWRSEQ_DELAY1 0 0x2886 4 0 2 LVTMA_PWRUP_DELAY1 0 7 LVTMA_PWRUP_DELAY2 8 15 LVTMA_PWRDN_DELAY1 16 23 LVTMA_PWRDN_DELAY2 24 31 mmLVTMA_PWRSEQ_DELAY2 0 0x2887 4 0 2 LVTMA_PWRDN_MIN_LENGTH 0 7 LVTMA_PWRUP_DELAY3 8 15 LVTMA_PWRDN_DELAY3 16 23 LVTMA_VARY_BL_OVERRIDE_EN 24 24 mmBL_PWM_CNTL 0 0x2888 3 0 2 BL_ACTIVE_INT_FRAC_CNT 0 15 BL_PWM_FRACTIONAL_EN 30 30 BL_PWM_EN 31 31 mmBL_PWM_CNTL2 0 0x2889 3 0 2 BL_PWM_POST_FRAME_START_DELAY_BEFORE_UPDATE 0 15 BL_PWM_OVERRIDE_BL_OUT_ENABLE 30 30 BL_PWM_OVERRIDE_LVTMA_PWRSEQ_EN 31 31 mmBL_PWM_PERIOD_CNTL 0 0x288a 2 0 2 BL_PWM_PERIOD 0 15 BL_PWM_PERIOD_BITCNT 16 19 mmBL_PWM_GRP1_REG_LOCK 0 0x288b 6 0 2 BL_PWM_GRP1_REG_LOCK 0 0 BL_PWM_GRP1_REG_UPDATE_PENDING 8 8 BL_PWM_GRP1_UPDATE_AT_FRAME_START 16 16 BL_PWM_GRP1_FRAME_START_DISP_SEL 17 19 BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN 24 24 BL_PWM_GRP1_IGNORE_MASTER_LOCK_EN 31 31 mmDCIO_GSL_GENLK_PAD_CNTL 0 0x288c 4 0 2 DCIO_GENLK_CLK_GSL_FLIP_READY_SEL 4 5 DCIO_GENLK_CLK_GSL_MASK 8 9 DCIO_GENLK_VSYNC_GSL_FLIP_READY_SEL 20 21 DCIO_GENLK_VSYNC_GSL_MASK 24 25 mmDCIO_GSL_SWAPLOCK_PAD_CNTL 0 0x288d 4 0 2 DCIO_SWAPLOCK_A_GSL_FLIP_READY_SEL 4 5 DCIO_SWAPLOCK_A_GSL_MASK 8 9 DCIO_SWAPLOCK_B_GSL_FLIP_READY_SEL 20 21 DCIO_SWAPLOCK_B_GSL_MASK 24 25 mmDCIO_CLOCK_CNTL 0 0x2895 2 0 2 DCIO_TEST_CLK_SEL 0 4 DISPCLK_R_DCIO_GATE_DIS 5 5 mmDIO_OTG_EXT_VSYNC_CNTL 0 0x2898 8 0 2 DIO_OTG0_EXT_VSYNC_MUX 0 2 DIO_OTG1_EXT_VSYNC_MUX 4 6 DIO_OTG2_EXT_VSYNC_MUX 8 10 DIO_OTG3_EXT_VSYNC_MUX 12 14 DIO_OTG4_EXT_VSYNC_MUX 16 18 DIO_OTG5_EXT_VSYNC_MUX 20 22 DIO_SWAPLOCKB_EXT_VSYNC_MASK 24 26 DIO_GENERICB_EXT_VSYNC_MASK 28 30 mmDCIO_SOFT_RESET 0 0x289e 18 0 2 UNIPHYA_SOFT_RESET 0 0 DSYNCA_SOFT_RESET 1 1 UNIPHYB_SOFT_RESET 2 2 DSYNCB_SOFT_RESET 3 3 UNIPHYC_SOFT_RESET 4 4 DSYNCC_SOFT_RESET 5 5 UNIPHYD_SOFT_RESET 6 6 DSYNCD_SOFT_RESET 7 7 UNIPHYE_SOFT_RESET 8 8 DSYNCE_SOFT_RESET 9 9 UNIPHYF_SOFT_RESET 10 10 DSYNCF_SOFT_RESET 11 11 UNIPHYG_SOFT_RESET 12 12 DSYNCG_SOFT_RESET 13 13 DACA_SOFT_RESET 16 16 DCRXPHY_SOFT_RESET 20 20 DPHY_SOFT_RESET 24 24 ZCAL_SOFT_RESET 26 26 mmDCIO_DPHY_SEL 0 0x289f 4 0 2 DPHY_LANE0_SEL 0 1 DPHY_LANE1_SEL 2 3 DPHY_LANE2_SEL 4 5 DPHY_LANE3_SEL 6 7 mmUNIPHY_IMPCAL_LINKA 0 0x28a0 9 0 2 UNIPHY_IMPCAL_ENABLE_LINKA 0 0 UNIPHY_IMPCAL_CALOUT_LINKA 8 8 UNIPHY_CALOUT_ERROR_LINKA 9 9 UNIPHY_CALOUT_ERROR_LINKA_AK 10 10 UNIPHY_IMPCAL_VALUE_LINKA 16 19 UNIPHY_IMPCAL_STEP_DELAY_LINKA 20 23 UNIPHY_IMPCAL_OVERRIDE_LINKA 24 27 UNIPHY_IMPCAL_OVERRIDE_ENABLE_LINKA 28 28 UNIPHY_IMPCAL_SEL_LINKA 30 30 mmUNIPHY_IMPCAL_LINKB 0 0x28a1 9 0 2 UNIPHY_IMPCAL_ENABLE_LINKB 0 0 UNIPHY_IMPCAL_CALOUT_LINKB 8 8 UNIPHY_CALOUT_ERROR_LINKB 9 9 UNIPHY_CALOUT_ERROR_LINKB_AK 10 10 UNIPHY_IMPCAL_VALUE_LINKB 16 19 UNIPHY_IMPCAL_STEP_DELAY_LINKB 20 23 UNIPHY_IMPCAL_OVERRIDE_LINKB 24 27 UNIPHY_IMPCAL_OVERRIDE_ENABLE_LINKB 28 28 UNIPHY_IMPCAL_SEL_LINKB 30 30 mmUNIPHY_IMPCAL_PERIOD 0 0x28a2 1 0 2 UNIPHY_IMPCAL_PERIOD 0 31 mmAUXP_IMPCAL 0 0x28a3 8 0 2 AUXP_IMPCAL_ENABLE 0 0 AUXP_IMPCAL_CALOUT 8 8 AUXP_CALOUT_ERROR 9 9 AUXP_CALOUT_ERROR_AK 10 10 AUXP_IMPCAL_VALUE 16 19 AUXP_IMPCAL_STEP_DELAY 20 23 AUXP_IMPCAL_OVERRIDE 24 27 AUXP_IMPCAL_OVERRIDE_ENABLE 28 28 mmAUXN_IMPCAL 0 0x28a4 8 0 2 AUXN_IMPCAL_ENABLE 0 0 AUXN_IMPCAL_CALOUT 8 8 AUXN_CALOUT_ERROR 9 9 AUXN_CALOUT_ERROR_AK 10 10 AUXN_IMPCAL_VALUE 16 19 AUXN_IMPCAL_STEP_DELAY 20 23 AUXN_IMPCAL_OVERRIDE 24 27 AUXN_IMPCAL_OVERRIDE_ENABLE 28 28 mmDCIO_IMPCAL_CNTL 0 0x28a5 5 0 2 CALR_CNTL_OVERRIDE 0 3 IMPCAL_SOFT_RESET 5 5 IMPCAL_STATUS 8 9 IMPCAL_ARB_STATE 12 14 AUX_IMPCAL_INTERVAL 15 18 mmUNIPHY_IMPCAL_PSW_AB 0 0x28a6 2 0 2 UNIPHY_IMPCAL_PSW_LINKA 0 14 UNIPHY_IMPCAL_PSW_LINKB 16 30 mmUNIPHY_IMPCAL_LINKC 0 0x28a7 9 0 2 UNIPHY_IMPCAL_ENABLE_LINKC 0 0 UNIPHY_IMPCAL_CALOUT_LINKC 8 8 UNIPHY_CALOUT_ERROR_LINKC 9 9 UNIPHY_CALOUT_ERROR_LINKC_AK 10 10 UNIPHY_IMPCAL_VALUE_LINKC 16 19 UNIPHY_IMPCAL_STEP_DELAY_LINKC 20 23 UNIPHY_IMPCAL_OVERRIDE_LINKC 24 27 UNIPHY_IMPCAL_OVERRIDE_ENABLE_LINKC 28 28 UNIPHY_IMPCAL_SEL_LINKC 30 30 mmUNIPHY_IMPCAL_LINKD 0 0x28a8 9 0 2 UNIPHY_IMPCAL_ENABLE_LINKD 0 0 UNIPHY_IMPCAL_CALOUT_LINKD 8 8 UNIPHY_CALOUT_ERROR_LINKD 9 9 UNIPHY_CALOUT_ERROR_LINKD_AK 10 10 UNIPHY_IMPCAL_VALUE_LINKD 16 19 UNIPHY_IMPCAL_STEP_DELAY_LINKD 20 23 UNIPHY_IMPCAL_OVERRIDE_LINKD 24 27 UNIPHY_IMPCAL_OVERRIDE_ENABLE_LINKD 28 28 UNIPHY_IMPCAL_SEL_LINKD 30 30 mmDCIO_IMPCAL_CNTL_CD 0 0x28a9 4 0 2 CALR_CNTL_OVERRIDE 0 3 IMPCAL_SOFT_RESET 5 5 IMPCAL_STATUS 8 9 IMPCAL_ARB_STATE 12 14 mmUNIPHY_IMPCAL_PSW_CD 0 0x28aa 2 0 2 UNIPHY_IMPCAL_PSW_LINKC 0 14 UNIPHY_IMPCAL_PSW_LINKD 16 30 mmUNIPHY_IMPCAL_LINKE 0 0x28ab 9 0 2 UNIPHY_IMPCAL_ENABLE_LINKE 0 0 UNIPHY_IMPCAL_CALOUT_LINKE 8 8 UNIPHY_CALOUT_ERROR_LINKE 9 9 UNIPHY_CALOUT_ERROR_LINKE_AK 10 10 UNIPHY_IMPCAL_VALUE_LINKE 16 19 UNIPHY_IMPCAL_STEP_DELAY_LINKE 20 23 UNIPHY_IMPCAL_OVERRIDE_LINKE 24 27 UNIPHY_IMPCAL_OVERRIDE_ENABLE_LINKE 28 28 UNIPHY_IMPCAL_SEL_LINKE 30 30 mmUNIPHY_IMPCAL_LINKF 0 0x28ac 9 0 2 UNIPHY_IMPCAL_ENABLE_LINKF 0 0 UNIPHY_IMPCAL_CALOUT_LINKF 8 8 UNIPHY_CALOUT_ERROR_LINKF 9 9 UNIPHY_CALOUT_ERROR_LINKF_AK 10 10 UNIPHY_IMPCAL_VALUE_LINKF 16 19 UNIPHY_IMPCAL_STEP_DELAY_LINKF 20 23 UNIPHY_IMPCAL_OVERRIDE_LINKF 24 27 UNIPHY_IMPCAL_OVERRIDE_ENABLE_LINKF 28 28 UNIPHY_IMPCAL_SEL_LINKF 30 30 mmDCIO_IMPCAL_CNTL_EF 0 0x28ad 4 0 2 CALR_CNTL_OVERRIDE 0 3 IMPCAL_SOFT_RESET 5 5 IMPCAL_STATUS 8 9 IMPCAL_ARB_STATE 12 14 mmUNIPHY_IMPCAL_PSW_EF 0 0x28ae 2 0 2 UNIPHY_IMPCAL_PSW_LINKE 0 14 UNIPHY_IMPCAL_PSW_LINKF 16 30 mmDCIO_DPCS_TX_INTERRUPT 0 0x28b3 21 0 2 DCIO_DPCS_TXA_INT_TYPE 0 0 DCIO_DPCS_TXA_INT_MASK 1 1 DCIO_DPCS_TXA_INT_OCCUR 2 2 DCIO_DPCS_TXB_INT_TYPE 3 3 DCIO_DPCS_TXB_INT_MASK 4 4 DCIO_DPCS_TXB_INT_OCCUR 5 5 DCIO_DPCS_TXC_INT_TYPE 6 6 DCIO_DPCS_TXC_INT_MASK 7 7 DCIO_DPCS_TXC_INT_OCCUR 8 8 DCIO_DPCS_TXD_INT_TYPE 9 9 DCIO_DPCS_TXD_INT_MASK 10 10 DCIO_DPCS_TXD_INT_OCCUR 11 11 DCIO_DPCS_TXE_INT_TYPE 12 12 DCIO_DPCS_TXE_INT_MASK 13 13 DCIO_DPCS_TXE_INT_OCCUR 14 14 DCIO_DPCS_TXF_INT_TYPE 15 15 DCIO_DPCS_TXF_INT_MASK 16 16 DCIO_DPCS_TXF_INT_OCCUR 17 17 DCIO_DPCS_TXG_INT_TYPE 18 18 DCIO_DPCS_TXG_INT_MASK 19 19 DCIO_DPCS_TXG_INT_OCCUR 20 20 mmDCIO_DPCS_RX_INTERRUPT 0 0x28b4 3 0 2 DCIO_DPCS_RXA_INT_TYPE 0 0 DCIO_DPCS_RXA_INT_MASK 1 1 DCIO_DPCS_RXA_INT_OCCUR 2 2 mmDCIO_SEMAPHORE0 0 0x28b5 2 0 2 DCIO_SEMAPHORE0_REQ 0 15 DCIO_SEMAPHORE0_GNT 16 31 mmDCIO_SEMAPHORE1 0 0x28b6 2 0 2 DCIO_SEMAPHORE1_REQ 0 15 DCIO_SEMAPHORE1_GNT 16 31 mmDCIO_SEMAPHORE2 0 0x28b7 2 0 2 DCIO_SEMAPHORE2_REQ 0 15 DCIO_SEMAPHORE2_GNT 16 31 mmDCIO_SEMAPHORE3 0 0x28b8 2 0 2 DCIO_SEMAPHORE3_REQ 0 15 DCIO_SEMAPHORE3_GNT 16 31 mmDCIO_SEMAPHORE4 0 0x28b9 2 0 2 DCIO_SEMAPHORE4_REQ 0 15 DCIO_SEMAPHORE4_GNT 16 31 mmDCIO_SEMAPHORE5 0 0x28ba 2 0 2 DCIO_SEMAPHORE5_REQ 0 15 DCIO_SEMAPHORE5_GNT 16 31 mmDCIO_SEMAPHORE6 0 0x28bb 2 0 2 DCIO_SEMAPHORE6_REQ 0 15 DCIO_SEMAPHORE6_GNT 16 31 mmDCIO_SEMAPHORE7 0 0x28bc 2 0 2 DCIO_SEMAPHORE7_REQ 0 15 DCIO_SEMAPHORE7_GNT 16 31 mmDCIO_USBC_FLIP_EN_SEL 0 0x28bd 12 0 2 DCIO_UNIPHYA_USBC_FLIP_EN_SEL 0 2 DCIO_UNIPHYB_USBC_FLIP_EN_SEL 4 6 DCIO_UNIPHYC_USBC_FLIP_EN_SEL 8 10 DCIO_UNIPHYD_USBC_FLIP_EN_SEL 12 14 DCIO_UNIPHYE_USBC_FLIP_EN_SEL 16 18 DCIO_UNIPHYF_USBC_FLIP_EN_SEL 20 22 DCIO_FCH_DC_LINKA_USBC_DP_FLIP_EN 24 24 DCIO_FCH_DC_LINKB_USBC_DP_FLIP_EN 25 25 DCIO_FCH_DC_LINKC_USBC_DP_FLIP_EN 26 26 DCIO_FCH_DC_LINKD_USBC_DP_FLIP_EN 27 27 DCIO_FCH_DC_LINKE_USBC_DP_FLIP_EN 28 28 DCIO_FCH_DC_LINKF_USBC_DP_FLIP_EN 29 29 mmDC_GPIO_GENERIC_MASK 0 0x28c8 21 0 2 DC_GPIO_GENERICA_MASK 0 0 DC_GPIO_GENERICA_PD_DIS 1 1 DC_GPIO_GENERICA_RECV 2 3 DC_GPIO_GENERICB_MASK 4 4 DC_GPIO_GENERICB_PD_DIS 5 5 DC_GPIO_GENERICB_RECV 6 7 DC_GPIO_GENERICC_MASK 8 8 DC_GPIO_GENERICC_PD_DIS 9 9 DC_GPIO_GENERICC_RECV 10 11 DC_GPIO_GENERICD_MASK 12 12 DC_GPIO_GENERICD_PD_DIS 13 13 DC_GPIO_GENERICD_RECV 14 15 DC_GPIO_GENERICE_MASK 16 16 DC_GPIO_GENERICE_PD_DIS 17 17 DC_GPIO_GENERICE_RECV 18 19 DC_GPIO_GENERICF_MASK 20 20 DC_GPIO_GENERICF_PD_DIS 21 21 DC_GPIO_GENERICF_RECV 22 23 DC_GPIO_GENERICG_MASK 24 24 DC_GPIO_GENERICG_PD_DIS 25 25 DC_GPIO_GENERICG_RECV 26 27 mmDC_GPIO_GENERIC_A 0 0x28c9 7 0 2 DC_GPIO_GENERICA_A 0 0 DC_GPIO_GENERICB_A 8 8 DC_GPIO_GENERICC_A 16 16 DC_GPIO_GENERICD_A 20 20 DC_GPIO_GENERICE_A 21 21 DC_GPIO_GENERICF_A 22 22 DC_GPIO_GENERICG_A 23 23 mmDC_GPIO_GENERIC_EN 0 0x28ca 7 0 2 DC_GPIO_GENERICA_EN 0 0 DC_GPIO_GENERICB_EN 8 8 DC_GPIO_GENERICC_EN 16 16 DC_GPIO_GENERICD_EN 20 20 DC_GPIO_GENERICE_EN 21 21 DC_GPIO_GENERICF_EN 22 22 DC_GPIO_GENERICG_EN 23 23 mmDC_GPIO_GENERIC_Y 0 0x28cb 7 0 2 DC_GPIO_GENERICA_Y 0 0 DC_GPIO_GENERICB_Y 8 8 DC_GPIO_GENERICC_Y 16 16 DC_GPIO_GENERICD_Y 20 20 DC_GPIO_GENERICE_Y 21 21 DC_GPIO_GENERICF_Y 22 22 DC_GPIO_GENERICG_Y 23 23 mmDC_GPIO_DVODATA_MASK 0 0x28cc 3 0 2 DC_GPIO_DVODATA_MASK 0 23 DC_GPIO_DVOCNTL_MASK 24 28 DC_GPIO_DVOCLK_MASK 29 29 mmDC_GPIO_DVODATA_A 0 0x28cd 3 0 2 DC_GPIO_DVODATA_A 0 23 DC_GPIO_DVOCNTL_A 24 28 DC_GPIO_DVOCLK_A 29 29 mmDC_GPIO_DVODATA_EN 0 0x28ce 3 0 2 DC_GPIO_DVODATA_EN 0 23 DC_GPIO_DVOCNTL_EN 24 28 DC_GPIO_DVOCLK_EN 29 29 mmDC_GPIO_DVODATA_Y 0 0x28cf 3 0 2 DC_GPIO_DVODATA_Y 0 23 DC_GPIO_DVOCNTL_Y 24 28 DC_GPIO_DVOCLK_Y 29 29 mmDC_GPIO_DDC1_MASK 0 0x28d0 11 0 2 DC_GPIO_DDC1CLK_MASK 0 0 DC_GPIO_DDC1CLK_PD_EN 4 4 DC_GPIO_DDC1CLK_RECV 6 6 DC_GPIO_DDC1DATA_MASK 8 8 DC_GPIO_DDC1DATA_PD_EN 12 12 DC_GPIO_DDC1DATA_RECV 14 14 AUX_PAD1_MODE 16 16 AUX1_POL 20 20 ALLOW_HW_DDC1_PD_EN 22 22 DC_GPIO_DDC1CLK_STR 24 27 DC_GPIO_DDC1DATA_STR 28 31 mmDC_GPIO_DDC1_A 0 0x28d1 2 0 2 DC_GPIO_DDC1CLK_A 0 0 DC_GPIO_DDC1DATA_A 8 8 mmDC_GPIO_DDC1_EN 0 0x28d2 2 0 2 DC_GPIO_DDC1CLK_EN 0 0 DC_GPIO_DDC1DATA_EN 8 8 mmDC_GPIO_DDC1_Y 0 0x28d3 2 0 2 DC_GPIO_DDC1CLK_Y 0 0 DC_GPIO_DDC1DATA_Y 8 8 mmDC_GPIO_DDC2_MASK 0 0x28d4 11 0 2 DC_GPIO_DDC2CLK_MASK 0 0 DC_GPIO_DDC2CLK_PD_EN 4 4 DC_GPIO_DDC2CLK_RECV 6 6 DC_GPIO_DDC2DATA_MASK 8 8 DC_GPIO_DDC2DATA_PD_EN 12 12 DC_GPIO_DDC2DATA_RECV 14 14 AUX_PAD2_MODE 16 16 AUX2_POL 20 20 ALLOW_HW_DDC2_PD_EN 22 22 DC_GPIO_DDC2CLK_STR 24 27 DC_GPIO_DDC2DATA_STR 28 31 mmDC_GPIO_DDC2_A 0 0x28d5 2 0 2 DC_GPIO_DDC2CLK_A 0 0 DC_GPIO_DDC2DATA_A 8 8 mmDC_GPIO_DDC2_EN 0 0x28d6 2 0 2 DC_GPIO_DDC2CLK_EN 0 0 DC_GPIO_DDC2DATA_EN 8 8 mmDC_GPIO_DDC2_Y 0 0x28d7 2 0 2 DC_GPIO_DDC2CLK_Y 0 0 DC_GPIO_DDC2DATA_Y 8 8 mmDC_GPIO_DDC3_MASK 0 0x28d8 11 0 2 DC_GPIO_DDC3CLK_MASK 0 0 DC_GPIO_DDC3CLK_PD_EN 4 4 DC_GPIO_DDC3CLK_RECV 6 6 DC_GPIO_DDC3DATA_MASK 8 8 DC_GPIO_DDC3DATA_PD_EN 12 12 DC_GPIO_DDC3DATA_RECV 14 14 AUX_PAD3_MODE 16 16 AUX3_POL 20 20 ALLOW_HW_DDC3_PD_EN 22 22 DC_GPIO_DDC3CLK_STR 24 27 DC_GPIO_DDC3DATA_STR 28 31 mmDC_GPIO_DDC3_A 0 0x28d9 2 0 2 DC_GPIO_DDC3CLK_A 0 0 DC_GPIO_DDC3DATA_A 8 8 mmDC_GPIO_DDC3_EN 0 0x28da 2 0 2 DC_GPIO_DDC3CLK_EN 0 0 DC_GPIO_DDC3DATA_EN 8 8 mmDC_GPIO_DDC3_Y 0 0x28db 2 0 2 DC_GPIO_DDC3CLK_Y 0 0 DC_GPIO_DDC3DATA_Y 8 8 mmDC_GPIO_DDC4_MASK 0 0x28dc 11 0 2 DC_GPIO_DDC4CLK_MASK 0 0 DC_GPIO_DDC4CLK_PD_EN 4 4 DC_GPIO_DDC4CLK_RECV 6 6 DC_GPIO_DDC4DATA_MASK 8 8 DC_GPIO_DDC4DATA_PD_EN 12 12 DC_GPIO_DDC4DATA_RECV 14 14 AUX_PAD4_MODE 16 16 AUX4_POL 20 20 ALLOW_HW_DDC4_PD_EN 22 22 DC_GPIO_DDC4CLK_STR 24 27 DC_GPIO_DDC4DATA_STR 28 31 mmDC_GPIO_DDC4_A 0 0x28dd 2 0 2 DC_GPIO_DDC4CLK_A 0 0 DC_GPIO_DDC4DATA_A 8 8 mmDC_GPIO_DDC4_EN 0 0x28de 2 0 2 DC_GPIO_DDC4CLK_EN 0 0 DC_GPIO_DDC4DATA_EN 8 8 mmDC_GPIO_DDC4_Y 0 0x28df 2 0 2 DC_GPIO_DDC4CLK_Y 0 0 DC_GPIO_DDC4DATA_Y 8 8 mmDC_GPIO_DDC5_MASK 0 0x28e0 11 0 2 DC_GPIO_DDC5CLK_MASK 0 0 DC_GPIO_DDC5CLK_PD_EN 4 4 DC_GPIO_DDC5CLK_RECV 6 6 DC_GPIO_DDC5DATA_MASK 8 8 DC_GPIO_DDC5DATA_PD_EN 12 12 DC_GPIO_DDC5DATA_RECV 14 14 AUX_PAD5_MODE 16 16 AUX5_POL 20 20 ALLOW_HW_DDC5_PD_EN 22 22 DC_GPIO_DDC5CLK_STR 24 27 DC_GPIO_DDC5DATA_STR 28 31 mmDC_GPIO_DDC5_A 0 0x28e1 2 0 2 DC_GPIO_DDC5CLK_A 0 0 DC_GPIO_DDC5DATA_A 8 8 mmDC_GPIO_DDC5_EN 0 0x28e2 2 0 2 DC_GPIO_DDC5CLK_EN 0 0 DC_GPIO_DDC5DATA_EN 8 8 mmDC_GPIO_DDC5_Y 0 0x28e3 2 0 2 DC_GPIO_DDC5CLK_Y 0 0 DC_GPIO_DDC5DATA_Y 8 8 mmDC_GPIO_DDC6_MASK 0 0x28e4 11 0 2 DC_GPIO_DDC6CLK_MASK 0 0 DC_GPIO_DDC6CLK_PD_EN 4 4 DC_GPIO_DDC6CLK_RECV 6 6 DC_GPIO_DDC6DATA_MASK 8 8 DC_GPIO_DDC6DATA_PD_EN 12 12 DC_GPIO_DDC6DATA_RECV 14 14 AUX_PAD6_MODE 16 16 AUX6_POL 20 20 ALLOW_HW_DDC6_PD_EN 22 22 DC_GPIO_DDC6CLK_STR 24 27 DC_GPIO_DDC6DATA_STR 28 31 mmDC_GPIO_DDC6_A 0 0x28e5 2 0 2 DC_GPIO_DDC6CLK_A 0 0 DC_GPIO_DDC6DATA_A 8 8 mmDC_GPIO_DDC6_EN 0 0x28e6 2 0 2 DC_GPIO_DDC6CLK_EN 0 0 DC_GPIO_DDC6DATA_EN 8 8 mmDC_GPIO_DDC6_Y 0 0x28e7 2 0 2 DC_GPIO_DDC6CLK_Y 0 0 DC_GPIO_DDC6DATA_Y 8 8 mmDC_GPIO_DDCVGA_MASK 0 0x28e8 10 0 2 DC_GPIO_DDCVGACLK_MASK 0 0 DC_GPIO_DDCVGACLK_RECV 6 6 DC_GPIO_DDCVGADATA_MASK 8 8 DC_GPIO_DDCVGADATA_PD_EN 12 12 DC_GPIO_DDCVGADATA_RECV 14 14 AUX_PADVGA_MODE 16 16 AUXVGA_POL 20 20 ALLOW_HW_DDCVGA_PD_EN 22 22 DC_GPIO_DDCVGACLK_STR 24 27 DC_GPIO_DDCVGADATA_STR 28 31 mmDC_GPIO_DDCVGA_A 0 0x28e9 2 0 2 DC_GPIO_DDCVGACLK_A 0 0 DC_GPIO_DDCVGADATA_A 8 8 mmDC_GPIO_DDCVGA_EN 0 0x28ea 2 0 2 DC_GPIO_DDCVGACLK_EN 0 0 DC_GPIO_DDCVGADATA_EN 8 8 mmDC_GPIO_DDCVGA_Y 0 0x28eb 2 0 2 DC_GPIO_DDCVGACLK_Y 0 0 DC_GPIO_DDCVGADATA_Y 8 8 mmDC_GPIO_SYNCA_MASK 0 0x28ec 8 0 2 DC_GPIO_HSYNCA_MASK 0 0 DC_GPIO_HSYNCA_PD_DIS 4 4 DC_GPIO_HSYNCA_RECV 6 7 DC_GPIO_VSYNCA_MASK 8 8 DC_GPIO_VSYNCA_PD_DIS 12 12 DC_GPIO_VSYNCA_RECV 14 15 DC_GPIO_HSYNCA_OPTC_HSYNC_MASK 24 26 DC_GPIO_VSYNCA_OPTC_VSYNC_MASK 28 30 mmDC_GPIO_SYNCA_A 0 0x28ed 2 0 2 DC_GPIO_HSYNCA_A 0 0 DC_GPIO_VSYNCA_A 8 8 mmDC_GPIO_SYNCA_EN 0 0x28ee 2 0 2 DC_GPIO_HSYNCA_EN 0 0 DC_GPIO_VSYNCA_EN 8 8 mmDC_GPIO_SYNCA_Y 0 0x28ef 2 0 2 DC_GPIO_HSYNCA_Y 0 0 DC_GPIO_VSYNCA_Y 8 8 mmDC_GPIO_GENLK_MASK 0 0x28f0 16 0 2 DC_GPIO_GENLK_CLK_MASK 0 0 DC_GPIO_GENLK_CLK_PD_DIS 1 1 DC_GPIO_GENLK_CLK_PU_EN 3 3 DC_GPIO_GENLK_CLK_RECV 4 5 DC_GPIO_GENLK_VSYNC_MASK 8 8 DC_GPIO_GENLK_VSYNC_PD_DIS 9 9 DC_GPIO_GENLK_VSYNC_PU_EN 11 11 DC_GPIO_GENLK_VSYNC_RECV 12 13 DC_GPIO_SWAPLOCK_A_MASK 16 16 DC_GPIO_SWAPLOCK_A_PD_DIS 17 17 DC_GPIO_SWAPLOCK_A_PU_EN 19 19 DC_GPIO_SWAPLOCK_A_RECV 20 21 DC_GPIO_SWAPLOCK_B_MASK 24 24 DC_GPIO_SWAPLOCK_B_PD_DIS 25 25 DC_GPIO_SWAPLOCK_B_PU_EN 27 27 DC_GPIO_SWAPLOCK_B_RECV 28 29 mmDC_GPIO_GENLK_A 0 0x28f1 4 0 2 DC_GPIO_GENLK_CLK_A 0 0 DC_GPIO_GENLK_VSYNC_A 8 8 DC_GPIO_SWAPLOCK_A_A 16 16 DC_GPIO_SWAPLOCK_B_A 24 24 mmDC_GPIO_GENLK_EN 0 0x28f2 4 0 2 DC_GPIO_GENLK_CLK_EN 0 0 DC_GPIO_GENLK_VSYNC_EN 8 8 DC_GPIO_SWAPLOCK_A_EN 16 16 DC_GPIO_SWAPLOCK_B_EN 24 24 mmDC_GPIO_GENLK_Y 0 0x28f3 4 0 2 DC_GPIO_GENLK_CLK_Y 0 0 DC_GPIO_GENLK_VSYNC_Y 8 8 DC_GPIO_SWAPLOCK_A_Y 16 16 DC_GPIO_SWAPLOCK_B_Y 24 24 mmDC_GPIO_HPD_MASK 0 0x28f4 21 0 2 DC_GPIO_HPD1_MASK 0 0 DC_GPIO_RX_HPD_MASK 1 1 DC_GPIO_RX_HPD_PD_DIS 2 2 DC_GPIO_RX_HPD_RX_SEL 3 3 DC_GPIO_HPD1_PD_DIS 4 4 DC_GPIO_HPD1_RECV 6 7 DC_GPIO_HPD2_MASK 8 8 DC_GPIO_HPD2_PD_DIS 9 9 DC_GPIO_HPD2_RECV 10 11 DC_GPIO_HPD3_MASK 16 16 DC_GPIO_HPD3_PD_DIS 17 17 DC_GPIO_HPD3_RECV 18 19 DC_GPIO_HPD4_MASK 20 20 DC_GPIO_HPD4_PD_DIS 21 21 DC_GPIO_HPD4_RECV 22 23 DC_GPIO_HPD5_MASK 24 24 DC_GPIO_HPD5_PD_DIS 25 25 DC_GPIO_HPD5_RECV 26 27 DC_GPIO_HPD6_MASK 28 28 DC_GPIO_HPD6_PD_DIS 29 29 DC_GPIO_HPD6_RECV 30 31 mmDC_GPIO_HPD_A 0 0x28f5 6 0 2 DC_GPIO_HPD1_A 0 0 DC_GPIO_HPD2_A 8 8 DC_GPIO_HPD3_A 16 16 DC_GPIO_HPD4_A 24 24 DC_GPIO_HPD5_A 26 26 DC_GPIO_HPD6_A 28 28 mmDC_GPIO_HPD_EN 0 0x28f6 23 0 2 DC_GPIO_HPD1_EN 0 0 HPD1_SCHMEN_PI 1 1 HPD1_SLEWNCORE 2 2 RX_HPD_SCHMEN_PI 3 3 RX_HPD_SLEWNCORE 4 4 HPD12_SPARE0 5 5 HPD1_SEL0 6 6 RX_HPD_SEL0 7 7 DC_GPIO_HPD2_EN 8 8 HPD2_SCHMEN_PI 9 9 HPD12_SPARE1 10 10 DC_GPIO_HPD3_EN 16 16 HPD3_SCHMEN_PI 17 17 HPD34_SPARE0 18 18 DC_GPIO_HPD4_EN 20 20 HPD4_SCHMEN_PI 21 21 HPD34_SPARE1 22 22 DC_GPIO_HPD5_EN 24 24 HPD5_SCHMEN_PI 25 25 HPD56_SPARE0 26 26 DC_GPIO_HPD6_EN 28 28 HPD6_SCHMEN_PI 29 29 HPD56_SPARE1 30 30 mmDC_GPIO_HPD_Y 0 0x28f7 6 0 2 DC_GPIO_HPD1_Y 0 0 DC_GPIO_HPD2_Y 8 8 DC_GPIO_HPD3_Y 16 16 DC_GPIO_HPD4_Y 24 24 DC_GPIO_HPD5_Y 26 26 DC_GPIO_HPD6_Y 28 28 mmDC_GPIO_PWRSEQ_MASK 0 0x28f8 15 0 2 DC_GPIO_BLON_MASK 0 0 DC_GPIO_BLON_PD_DIS 4 4 DC_GPIO_BLON_RECV 6 7 DC_GPIO_DIGON_MASK 8 8 DC_GPIO_DIGON_PD_DIS 12 12 DC_GPIO_DIGON_RECV 14 15 DC_GPIO_ENA_BL_MASK 16 16 DC_GPIO_ENA_BL_PD_DIS 20 20 DC_GPIO_ENA_BL_RECV 22 23 DC_GPIO_VSYNC_IN_MASK 24 24 DC_GPIO_VSYNC_IN_PD_DIS 25 25 DC_GPIO_VSYNC_IN_RECV 26 26 DC_GPIO_HSYNC_IN_MASK 28 28 DC_GPIO_HSYNC_IN_PD_DIS 29 29 DC_GPIO_HSYNC_IN_RECV 30 30 mmDC_GPIO_PWRSEQ_A 0 0x28f9 5 0 2 DC_GPIO_BLON_A 0 0 DC_GPIO_DIGON_A 8 8 DC_GPIO_ENA_BL_A 16 16 DC_GPIO_VSYNC_IN_A 24 24 DC_GPIO_HSYNC_IN_A 31 31 mmDC_GPIO_PWRSEQ_EN 0 0x28fa 6 0 2 DC_GPIO_BLON_EN 0 0 DC_GPIO_VARY_BL_GENERICA_EN 1 1 DC_GPIO_DIGON_EN 8 8 DC_GPIO_ENA_BL_EN 16 16 DC_GPIO_VSYNC_IN_EN 24 24 DC_GPIO_HSYNC_IN_EN 31 31 mmDC_GPIO_PWRSEQ_Y 0 0x28fb 5 0 2 DC_GPIO_BLON_Y 0 0 DC_GPIO_DIGON_Y 8 8 DC_GPIO_ENA_BL_Y 16 16 DC_GPIO_VSYNC_IN 24 24 DC_GPIO_HSYNC_IN 31 31 mmDC_GPIO_PAD_STRENGTH_1 0 0x28fc 8 0 2 GENLK_STRENGTH_SN 0 3 GENLK_STRENGTH_SP 4 7 RX_HPD_STRENGTH_SN 8 11 RX_HPD_STRENGTH_SP 12 15 TX_HPD_STRENGTH_SN 16 19 TX_HPD_STRENGTH_SP 20 23 SYNC_STRENGTH_SN 24 27 SYNC_STRENGTH_SP 28 31 mmDC_GPIO_PAD_STRENGTH_2 0 0x28fd 7 0 2 STRENGTH_SN 0 3 STRENGTH_SP 4 7 EXT_RESET_DRVSTRENGTH 8 10 REF_27_DRVSTRENGTH 12 14 PWRSEQ_STRENGTH_SN 16 19 PWRSEQ_STRENGTH_SP 20 23 REF_27_SRC_SEL 30 31 mmPHY_AUX_CNTL 0 0x28ff 15 0 2 AUXSLAVE_PAD_SLEWN 0 0 AUXSLAVE_PAD_WAKE 1 1 AUXSLAVE_PAD_RXSEL 2 2 AUXSLAVE_PAD_MODE 3 3 DDCSLAVE_DATA_PD_EN 4 4 DDCSLAVE_DATA_EN 5 5 DDCSLAVE_CLK_PD_EN 6 6 DDCSLAVE_CLK_EN 7 7 AUX_PAD_SLEWN 12 12 AUXSLAVE_CLK_PD_EN 13 13 AUX_PAD_WAKE 14 14 AUX_PAD_RXSEL 16 17 AUX_CAL_BIASENTST 20 22 AUX_CAL_RESBIASEN 23 23 AUX_CAL_SPARE 24 25 mmDC_GPIO_I2CPAD_MASK 0 0x2900 6 0 2 DC_GPIO_SCL_MASK 0 0 DC_GPIO_SCL_PD_DIS 1 1 DC_GPIO_SCL_RECV 2 2 DC_GPIO_SDA_MASK 4 4 DC_GPIO_SDA_PD_DIS 5 5 DC_GPIO_SDA_RECV 6 6 mmDC_GPIO_I2CPAD_A 0 0x2901 2 0 2 DC_GPIO_SCL_A 0 0 DC_GPIO_SDA_A 1 1 mmDC_GPIO_I2CPAD_EN 0 0x2902 2 0 2 DC_GPIO_SCL_EN 0 0 DC_GPIO_SDA_EN 1 1 mmDC_GPIO_I2CPAD_Y 0 0x2903 2 0 2 DC_GPIO_SCL_Y 0 0 DC_GPIO_SDA_Y 1 1 mmDC_GPIO_I2CPAD_STRENGTH 0 0x2904 2 0 2 I2C_STRENGTH_SN 0 3 I2C_STRENGTH_SP 4 7 mmDVO_STRENGTH_CONTROL 0 0x2905 9 0 2 DVO_SP 0 3 DVO_SN 4 7 DVOCLK_SP 8 11 DVOCLK_SN 12 15 DVO_DRVSTRENGTH 16 18 DVOCLK_DRVSTRENGTH 20 22 FLDO_VITNE_DRVSTRENGTH 24 26 DVO_LSB_VMODE 28 28 DVO_MSB_VMODE 29 29 mmDVO_VREF_CONTROL 0 0x2906 3 0 2 DVO_VREFPON 0 0 DVO_VREFSEL 1 1 DVO_VREFCAL 4 7 mmDVO_SKEW_ADJUST 0 0x2907 1 0 2 DVO_SKEW_ADJUST 0 31 mmDC_GPIO_I2S_SPDIF_MASK 0 0x2910 10 0 2 DC_GPIO_I2SDATA0_MASK 0 3 DC_GPIO_MCLK0_MASK 4 4 DC_GPIO_BCLK0_MASK 5 5 DC_GPIO_LRCK0_MASK 6 6 DC_GPIO_SPDIF0_MASK 7 7 DC_GPIO_I2SDATA1_MASK 8 8 DC_GPIO_MCLK1_MASK 9 9 DC_GPIO_BCLK1_MASK 10 10 DC_GPIO_LRCK1_MASK 11 11 DC_GPIO_SPDIF1_MASK 12 12 mmDC_GPIO_I2S_SPDIF_A 0 0x2911 10 0 2 DC_GPIO_I2SDATA0_A 0 3 DC_GPIO_MCLK0_A 4 4 DC_GPIO_BCLK0_A 5 5 DC_GPIO_LRCK0_A 6 6 DC_GPIO_SPDIF0_A 7 7 DC_GPIO_I2SDATA1_A 8 8 DC_GPIO_MCLK1_A 9 9 DC_GPIO_BCLK1_A 10 10 DC_GPIO_LRCK1_A 11 11 DC_GPIO_SPDIF1_A 12 12 mmDC_GPIO_I2S_SPDIF_EN 0 0x2912 16 0 2 DC_GPIO_I2SDATA0_EN 0 3 DC_GPIO_MCLK0_EN 4 4 DC_GPIO_BCLK0_EN 5 5 DC_GPIO_LRCK0_EN 6 6 DC_GPIO_SPDIF0_EN 7 7 DC_GPIO_I2SDATA1_EN 8 8 DC_GPIO_MCLK1_EN 9 9 DC_GPIO_BCLK1_EN 10 10 DC_GPIO_LRCK1_EN 11 11 DC_GPIO_SPDIF1_EN 12 12 SPDIF1_APORT 13 13 SPDIF1_PU 14 14 SPDIF1_RXSEL 15 15 SPDIF1_SCHMEN 16 16 SPDIF1_SMODE_EN 17 17 SPDIF1_IMODE 18 18 mmDC_GPIO_I2S_SPDIF_Y 0 0x2913 10 0 2 DC_GPIO_I2SDATA0_Y 0 3 DC_GPIO_MCLK0_Y 4 4 DC_GPIO_BCLK0_Y 5 5 DC_GPIO_LRCK0_Y 6 6 DC_GPIO_SPDIF0_Y 7 7 DC_GPIO_I2SDATA1_Y 8 8 DC_GPIO_MCLK1_Y 9 9 DC_GPIO_BCLK1_Y 10 10 DC_GPIO_LRCK1_Y 11 11 DC_GPIO_SPDIF1_Y 12 12 mmDC_GPIO_I2S_SPDIF_STRENGTH 0 0x2914 6 0 2 I2S0_DRVSTRENGTH 0 2 SPDIF0_DRVSTRENGTH_SN 8 10 SPDIF0_DRVSTRENGTH_SP 11 13 I2S1_DRVSTRENGTH 16 18 SPDIF1_DRVSTRENGTH_SN 24 26 SPDIF1_DRVSTRENGTH_SP 27 29 mmDC_GPIO_TX12_EN 0 0x2915 10 0 2 DC_GPIO_BLON_TX12_EN 0 0 DC_GPIO_DIGON_TX12_EN 1 1 DC_GPIO_ENA_BL_TX12_EN 2 2 DC_GPIO_GENERICA_TX12_EN 3 3 DC_GPIO_GENERICB_TX12_EN 4 4 DC_GPIO_GENERICC_TX12_EN 5 5 DC_GPIO_GENERICD_TX12_EN 6 6 DC_GPIO_GENERICE_TX12_EN 7 7 DC_GPIO_GENERICF_TX12_EN 8 8 DC_GPIO_GENERICG_TX12_EN 9 9 mmDC_GPIO_AUX_CTRL_0 0 0x2916 24 0 2 DC_GPIO_AUX1_FALLSLEWSEL 0 1 DC_GPIO_AUX2_FALLSLEWSEL 2 3 DC_GPIO_AUX3_FALLSLEWSEL 4 5 DC_GPIO_AUX4_FALLSLEWSEL 6 7 DC_GPIO_AUX5_FALLSLEWSEL 8 9 DC_GPIO_AUX6_FALLSLEWSEL 10 11 DC_GPIO_DDCVGA_FALLSLEWSEL 12 13 DC_GPIO_GENI2C_FALLSLEWSEL 14 15 DC_GPIO_AUX1_SPIKERCEN 16 16 DC_GPIO_AUX2_SPIKERCEN 17 17 DC_GPIO_AUX3_SPIKERCEN 18 18 DC_GPIO_AUX4_SPIKERCEN 19 19 DC_GPIO_AUX5_SPIKERCEN 20 20 DC_GPIO_AUX6_SPIKERCEN 21 21 DC_GPIO_DDCVGA_SPIKERCEN 22 22 DC_GPIO_GENI2C_SPIKERCEN 23 23 DC_GPIO_AUX1_SPIKERCSEL 24 24 DC_GPIO_AUX2_SPIKERCSEL 25 25 DC_GPIO_AUX3_SPIKERCSEL 26 26 DC_GPIO_AUX4_SPIKERCSEL 27 27 DC_GPIO_AUX5_SPIKERCSEL 28 28 DC_GPIO_AUX6_SPIKERCSEL 29 29 DC_GPIO_DDCVGA_SPIKERCSEL 30 30 DC_GPIO_GENI2C_SPIKERCSEL 31 31 mmDC_GPIO_AUX_CTRL_1 0 0x2917 27 0 2 DC_GPIO_AUX_CSEL_0P9 0 0 DC_GPIO_AUX_CSEL_1P1 1 1 DC_GPIO_AUX_RSEL_0P9 2 2 DC_GPIO_AUX_RSEL_1P1 3 3 DC_GPIO_I2C_CSEL_0P9 4 4 DC_GPIO_I2C_CSEL_1P1 5 5 DC_GPIO_I2C_RSEL_0P9 6 6 DC_GPIO_I2C_RSEL_1P1 7 7 DC_GPIO_AUX_BIASCRTEN 8 8 DC_GPIO_I2C_BIASCRTEN 9 9 DC_GPIO_AUX_RESBIASEN 10 10 DC_GPIO_I2C_RESBIASEN 11 11 DC_GPIO_AUX1_COMPSEL 12 12 DC_GPIO_GENI2C_COMPSEL 13 13 DC_GPIO_DDCVGA_SPARE 14 15 DC_GPIO_GENI2C_SPARE 16 17 DC_GPIO_DDCVGA_SLEWN 18 18 DC_GPIO_GENI2C_SLEWN 19 19 DC_GPIO_DDCVGA_RXSEL 20 21 DC_GPIO_GENI2C_RXSEL 22 23 DC_GPIO_GENI2C_PDEN 24 24 DC_GPIO_AUX2_COMPSEL 25 25 DC_GPIO_AUX3_COMPSEL 26 26 DC_GPIO_AUX4_COMPSEL 27 27 DC_GPIO_AUX5_COMPSEL 28 28 DC_GPIO_AUX6_COMPSEL 29 29 DC_GPIO_DDCVGA_COMPSEL 30 30 mmDC_GPIO_AUX_CTRL_2 0 0x2918 21 0 2 DC_GPIO_HPD12_FALLSLEWSEL 0 1 DC_GPIO_HPD34_FALLSLEWSEL 2 3 DC_GPIO_HPD56_FALLSLEWSEL 4 5 DC_GPIO_HPD12_SPIKERCEN 8 8 DC_GPIO_HPD34_SPIKERCEN 9 9 DC_GPIO_HPD56_SPIKERCEN 10 10 DC_GPIO_HPD12_SPIKERCSEL 12 12 DC_GPIO_HPD34_SPIKERCSEL 13 13 DC_GPIO_HPD56_SPIKERCSEL 14 14 DC_GPIO_HPD_CSEL_0P9 16 16 DC_GPIO_HPD_CSEL_1P1 17 17 DC_GPIO_HPD_RSEL_0P9 18 18 DC_GPIO_HPD_RSEL_1P1 19 19 DC_GPIO_HPD_BIASCRTEN 20 20 DC_GPIO_HPD12_SLEWN 24 24 DC_GPIO_HPD34_SLEWN 25 25 DC_GPIO_HPD56_SLEWN 26 26 DC_GPIO_HPD_RESBIASEN 27 27 DC_GPIO_HPD12_COMPSEL 28 28 DC_GPIO_HPD34_COMPSEL 29 29 DC_GPIO_HPD56_COMPSEL 30 30 mmDC_GPIO_RXEN 0 0x2919 22 0 2 DC_GPIO_GENERICA_RXEN 0 0 DC_GPIO_GENERICB_RXEN 1 1 DC_GPIO_GENERICC_RXEN 2 2 DC_GPIO_GENERICD_RXEN 3 3 DC_GPIO_GENERICE_RXEN 4 4 DC_GPIO_GENERICF_RXEN 5 5 DC_GPIO_GENERICG_RXEN 6 6 DC_GPIO_HSYNCA_RXEN 8 8 DC_GPIO_VSYNCA_RXEN 9 9 DC_GPIO_GENLK_CLK_RXEN 10 10 DC_GPIO_GENLK_VSYNC_RXEN 11 11 DC_GPIO_SWAPLOCK_A_RXEN 12 12 DC_GPIO_SWAPLOCK_B_RXEN 13 13 DC_GPIO_HPD1_RXEN 14 14 DC_GPIO_HPD2_RXEN 15 15 DC_GPIO_HPD3_RXEN 16 16 DC_GPIO_HPD4_RXEN 17 17 DC_GPIO_HPD5_RXEN 18 18 DC_GPIO_HPD6_RXEN 19 19 DC_GPIO_BLON_RXEN 20 20 DC_GPIO_DIGON_RXEN 21 21 DC_GPIO_ENA_BL_RXEN 22 22 mmDC_GPIO_PULLUPEN 0 0x291a 13 0 2 DC_GPIO_GENERICA_PU_EN 0 0 DC_GPIO_GENERICB_PU_EN 1 1 DC_GPIO_GENERICC_PU_EN 2 2 DC_GPIO_GENERICD_PU_EN 3 3 DC_GPIO_GENERICE_PU_EN 4 4 DC_GPIO_GENERICF_PU_EN 5 5 DC_GPIO_GENERICG_PU_EN 6 6 DC_GPIO_HSYNCA_PU_EN 8 8 DC_GPIO_VSYNCA_PU_EN 9 9 DC_GPIO_HPD1_PU_EN 14 14 DC_GPIO_BLON_PU_EN 20 20 DC_GPIO_DIGON_PU_EN 21 21 DC_GPIO_ENA_BL_PU_EN 22 22 mmDAC_MACRO_CNTL_RESERVED0 0 0x2920 1 0 2 DAC_MACRO_CNTL_RESERVED 0 31 mmDAC_MACRO_CNTL_RESERVED1 0 0x2921 1 0 2 DAC_MACRO_CNTL_RESERVED 0 31 mmDAC_MACRO_CNTL_RESERVED2 0 0x2922 1 0 2 DAC_MACRO_CNTL_RESERVED 0 31 mmDAC_MACRO_CNTL_RESERVED3 0 0x2923 1 0 2 DAC_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED0 0 0x2928 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED1 0 0x2929 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED2 0 0x292a 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED3 0 0x292b 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED4 0 0x292c 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED5 0 0x292d 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED6 0 0x292e 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED7 0 0x292f 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED8 0 0x2930 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED9 0 0x2931 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED10 0 0x2932 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED11 0 0x2933 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED12 0 0x2934 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED13 0 0x2935 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED14 0 0x2936 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED15 0 0x2937 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED16 0 0x2938 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED17 0 0x2939 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED18 0 0x293a 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED19 0 0x293b 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED20 0 0x293c 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED21 0 0x293d 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED22 0 0x293e 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED23 0 0x293f 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED24 0 0x2940 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED25 0 0x2941 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED26 0 0x2942 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED27 0 0x2943 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED28 0 0x2944 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED29 0 0x2945 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED30 0 0x2946 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED31 0 0x2947 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED32 0 0x2948 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED33 0 0x2949 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED34 0 0x294a 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED35 0 0x294b 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED36 0 0x294c 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED37 0 0x294d 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED38 0 0x294e 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED39 0 0x294f 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED40 0 0x2950 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED41 0 0x2951 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED42 0 0x2952 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED43 0 0x2953 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED44 0 0x2954 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED45 0 0x2955 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED46 0 0x2956 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED47 0 0x2957 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED48 0 0x2958 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED49 0 0x2959 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED50 0 0x295a 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED51 0 0x295b 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED52 0 0x295c 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED53 0 0x295d 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED54 0 0x295e 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED55 0 0x295f 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED56 0 0x2960 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED57 0 0x2961 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED58 0 0x2962 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED59 0 0x2963 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED60 0 0x2964 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED61 0 0x2965 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED62 0 0x2966 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED63 0 0x2967 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED64 0 0x2968 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED65 0 0x2969 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED66 0 0x296a 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED67 0 0x296b 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED68 0 0x296c 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED69 0 0x296d 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED70 0 0x296e 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED71 0 0x296f 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED72 0 0x2970 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED73 0 0x2971 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED74 0 0x2972 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED75 0 0x2973 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED76 0 0x2974 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED77 0 0x2975 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED78 0 0x2976 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED79 0 0x2977 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED80 0 0x2978 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED81 0 0x2979 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED82 0 0x297a 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED83 0 0x297b 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED84 0 0x297c 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED85 0 0x297d 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED86 0 0x297e 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED87 0 0x297f 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED88 0 0x2980 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED89 0 0x2981 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED90 0 0x2982 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED91 0 0x2983 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED92 0 0x2984 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED93 0 0x2985 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED94 0 0x2986 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED95 0 0x2987 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED96 0 0x2988 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED97 0 0x2989 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED98 0 0x298a 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED99 0 0x298b 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED100 0 0x298c 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED101 0 0x298d 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED102 0 0x298e 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED103 0 0x298f 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED104 0 0x2990 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED105 0 0x2991 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED106 0 0x2992 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED107 0 0x2993 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED108 0 0x2994 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED109 0 0x2995 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED110 0 0x2996 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED111 0 0x2997 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED112 0 0x2998 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED113 0 0x2999 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED114 0 0x299a 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED115 0 0x299b 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED116 0 0x299c 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED117 0 0x299d 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED118 0 0x299e 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED119 0 0x299f 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED120 0 0x29a0 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED121 0 0x29a1 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED122 0 0x29a2 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED123 0 0x29a3 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED124 0 0x29a4 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED125 0 0x29a5 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED126 0 0x29a6 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED127 0 0x29a7 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED128 0 0x29a8 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED129 0 0x29a9 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED130 0 0x29aa 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED131 0 0x29ab 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED132 0 0x29ac 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED133 0 0x29ad 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED134 0 0x29ae 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED135 0 0x29af 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED136 0 0x29b0 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED137 0 0x29b1 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED138 0 0x29b2 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED139 0 0x29b3 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED140 0 0x29b4 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED141 0 0x29b5 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED142 0 0x29b6 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED143 0 0x29b7 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED144 0 0x29b8 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED145 0 0x29b9 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED146 0 0x29ba 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED147 0 0x29bb 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED148 0 0x29bc 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED149 0 0x29bd 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED150 0 0x29be 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED151 0 0x29bf 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED152 0 0x29c0 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED153 0 0x29c1 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED154 0 0x29c2 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED155 0 0x29c3 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED156 0 0x29c4 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED157 0 0x29c5 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED158 0 0x29c6 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED159 0 0x29c7 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDC_COMBOPHYCMREGS0_COMMON_FUSE1 0 0x2928 11 0 2 fuse1_valid 0 0 fuse1_unpopulated0 1 2 fuse1_ron_override_val 3 8 fuse1_unpopulated1 9 9 fuse1_ron_ctl 10 11 fuse1_unpopulated2 12 12 fuse1_rtt_override_val 13 18 fuse1_unpopulated3 19 19 fuse1_rtt_ctl 20 21 fuse1_refresh_cal_en 22 22 fuse1_spare 23 31 mmDC_COMBOPHYCMREGS0_COMMON_FUSE2 0 0x2929 4 0 2 fuse2_valid 0 0 fuse2_unpopulated 1 8 fuse2_tx_fifo_ptr 9 13 fuse2_spare 14 31 mmDC_COMBOPHYCMREGS0_COMMON_FUSE3 0 0x292a 11 0 2 fuse3_valid 0 0 fuse3_unpopulated 1 9 fuse3_ei_det_thresh_sel 10 12 cdr_dac_safeval_sel 13 15 cdr_freq_lock_timer 16 17 cdr_cal_dac_stpsz 18 19 cdr_byp_init_val 20 20 cdr_icostart_sel 21 21 cdr_bbweight 22 25 cdr_cur_mirr_ratio 26 28 fuse3_spare 29 31 mmDC_COMBOPHYCMREGS0_COMMON_MAR_DEEMPH_NOM 0 0x292b 4 0 2 tx_margin_nom 0 7 deemph_gen1_nom 8 15 deemph35_gen2_nom 16 23 deemph60_gen2_nom 24 31 mmDC_COMBOPHYCMREGS0_COMMON_LANE_PWRMGMT 0 0x292c 3 0 2 pgdelay 0 3 pgmask 4 9 vprot_en 11 11 mmDC_COMBOPHYCMREGS0_COMMON_TXCNTRL 0 0x292d 5 0 2 rdptr_rst_val_gen3 0 4 clkgate_dis 5 5 slew_rate_ctl_gen1 6 8 slew_rate_ctl_gen2 9 11 slew_rate_ctl_gen3 12 14 mmDC_COMBOPHYCMREGS0_COMMON_TMDP 0 0x292e 1 0 2 tmdp_spare 0 31 mmDC_COMBOPHYCMREGS0_COMMON_LANE_RESETS 0 0x292f 8 0 2 lane_0_reset_l 0 0 lane_1_reset_l 1 1 lane_2_reset_l 2 2 lane_3_reset_l 3 3 lane_4_reset_l 4 4 lane_5_reset_l 5 5 lane_6_reset_l 6 6 lane_7_reset_l 7 7 mmDC_COMBOPHYCMREGS0_COMMON_ZCALCODE_CTRL 0 0x2930 4 0 2 zcalcode_override 0 0 tx_binary_code_override_val 1 5 rx_therm_code_override_val 6 20 tx_driver_fifty_ohms 21 21 mmDC_COMBOPHYCMREGS0_COMMON_DISP_RFU1 0 0x2931 1 0 2 rfu_value1 0 31 mmDC_COMBOPHYCMREGS0_COMMON_DISP_RFU2 0 0x2932 1 0 2 rfu_value2 0 31 mmDC_COMBOPHYCMREGS0_COMMON_DISP_RFU3 0 0x2933 1 0 2 rfu_value3 0 31 mmDC_COMBOPHYCMREGS0_COMMON_DISP_RFU4 0 0x2934 1 0 2 rfu_value4 0 31 mmDC_COMBOPHYCMREGS0_COMMON_DISP_RFU5 0 0x2935 1 0 2 rfu_value5 0 31 mmDC_COMBOPHYCMREGS0_COMMON_DISP_RFU6 0 0x2936 1 0 2 rfu_value6 0 31 mmDC_COMBOPHYCMREGS0_COMMON_DISP_RFU7 0 0x2937 1 0 2 rfu_value7 0 31 mmDC_COMBOPHYTXREGS0_CMD_BUS_TX_CONTROL_LANE0 0 0x2948 3 0 2 tx_pwr 0 2 tx_pg_en 3 4 tx_rdy 8 8 mmDC_COMBOPHYTXREGS0_MARGIN_DEEMPH_LANE0 0 0x2949 3 0 2 txmarg_sel 0 2 deemph_sel 3 4 tx_margin_en 5 5 mmDC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE0 0 0x294a 12 0 2 twosym_en 1 2 link_speed 3 4 gang_mode 5 7 max_linkrate 8 9 pcs_freq 10 11 pcs_clken 12 12 pcs_clkdone 13 13 pll1_always_on 14 14 rdclk_div2_en 15 15 tx_boost_adj 16 19 tx_boost_en 20 20 tx_binary_ron_code_offset 22 23 mmDC_COMBOPHYTXREGS0_TX_DISP_RFU0_LANE0 0 0x294b 1 0 2 rfu_value0 0 31 mmDC_COMBOPHYTXREGS0_TX_DISP_RFU1_LANE0 0 0x294c 1 0 2 rfu_value1 0 31 mmDC_COMBOPHYTXREGS0_TX_DISP_RFU2_LANE0 0 0x294d 1 0 2 rfu_value2 0 31 mmDC_COMBOPHYTXREGS0_TX_DISP_RFU3_LANE0 0 0x294e 1 0 2 rfu_value3 0 31 mmDC_COMBOPHYTXREGS0_TX_DISP_RFU4_LANE0 0 0x294f 1 0 2 rfu_value4 0 31 mmDC_COMBOPHYTXREGS0_TX_DISP_RFU5_LANE0 0 0x2950 1 0 2 rfu_value5 0 31 mmDC_COMBOPHYTXREGS0_TX_DISP_RFU6_LANE0 0 0x2951 1 0 2 rfu_value6 0 31 mmDC_COMBOPHYTXREGS0_TX_DISP_RFU7_LANE0 0 0x2952 1 0 2 rfu_value7 0 31 mmDC_COMBOPHYTXREGS0_TX_DISP_RFU8_LANE0 0 0x2953 1 0 2 rfu_value8 0 31 mmDC_COMBOPHYTXREGS0_TX_DISP_RFU9_LANE0 0 0x2954 1 0 2 rfu_value9 0 31 mmDC_COMBOPHYTXREGS0_TX_DISP_RFU10_LANE0 0 0x2955 1 0 2 rfu_value10 0 31 mmDC_COMBOPHYTXREGS0_TX_DISP_RFU11_LANE0 0 0x2956 1 0 2 rfu_value11 0 31 mmDC_COMBOPHYTXREGS0_TX_DISP_RFU12_LANE0 0 0x2957 1 0 2 rfu_value12 0 31 mmDC_COMBOPHYTXREGS0_CMD_BUS_TX_CONTROL_LANE1 0 0x2958 3 0 2 tx_pwr 0 2 tx_pg_en 3 4 tx_rdy 8 8 mmDC_COMBOPHYTXREGS0_MARGIN_DEEMPH_LANE1 0 0x2959 3 0 2 txmarg_sel 0 2 deemph_sel 3 4 tx_margin_en 5 5 mmDC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE1 0 0x295a 12 0 2 twosym_en 1 2 link_speed 3 4 gang_mode 5 7 max_linkrate 8 9 pcs_freq 10 11 pcs_clken 12 12 pcs_clkdone 13 13 pll1_always_on 14 14 rdclk_div2_en 15 15 tx_boost_adj 16 19 tx_boost_en 20 20 tx_binary_ron_code_offset 22 23 mmDC_COMBOPHYTXREGS0_TX_DISP_RFU0_LANE1 0 0x295b 1 0 2 rfu_value0 0 31 mmDC_COMBOPHYTXREGS0_TX_DISP_RFU1_LANE1 0 0x295c 1 0 2 rfu_value1 0 31 mmDC_COMBOPHYTXREGS0_TX_DISP_RFU2_LANE1 0 0x295d 1 0 2 rfu_value2 0 31 mmDC_COMBOPHYTXREGS0_TX_DISP_RFU3_LANE1 0 0x295e 1 0 2 rfu_value3 0 31 mmDC_COMBOPHYTXREGS0_TX_DISP_RFU4_LANE1 0 0x295f 1 0 2 rfu_value4 0 31 mmDC_COMBOPHYTXREGS0_TX_DISP_RFU5_LANE1 0 0x2960 1 0 2 rfu_value5 0 31 mmDC_COMBOPHYTXREGS0_TX_DISP_RFU6_LANE1 0 0x2961 1 0 2 rfu_value6 0 31 mmDC_COMBOPHYTXREGS0_TX_DISP_RFU7_LANE1 0 0x2962 1 0 2 rfu_value7 0 31 mmDC_COMBOPHYTXREGS0_TX_DISP_RFU8_LANE1 0 0x2963 1 0 2 rfu_value8 0 31 mmDC_COMBOPHYTXREGS0_TX_DISP_RFU9_LANE1 0 0x2964 1 0 2 rfu_value9 0 31 mmDC_COMBOPHYTXREGS0_TX_DISP_RFU10_LANE1 0 0x2965 1 0 2 rfu_value10 0 31 mmDC_COMBOPHYTXREGS0_TX_DISP_RFU11_LANE1 0 0x2966 1 0 2 rfu_value11 0 31 mmDC_COMBOPHYTXREGS0_TX_DISP_RFU12_LANE1 0 0x2967 1 0 2 rfu_value12 0 31 mmDC_COMBOPHYTXREGS0_CMD_BUS_TX_CONTROL_LANE2 0 0x2968 3 0 2 tx_pwr 0 2 tx_pg_en 3 4 tx_rdy 8 8 mmDC_COMBOPHYTXREGS0_MARGIN_DEEMPH_LANE2 0 0x2969 3 0 2 txmarg_sel 0 2 deemph_sel 3 4 tx_margin_en 5 5 mmDC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE2 0 0x296a 12 0 2 twosym_en 1 2 link_speed 3 4 gang_mode 5 7 max_linkrate 8 9 pcs_freq 10 11 pcs_clken 12 12 pcs_clkdone 13 13 pll1_always_on 14 14 rdclk_div2_en 15 15 tx_boost_adj 16 19 tx_boost_en 20 20 tx_binary_ron_code_offset 22 23 mmDC_COMBOPHYTXREGS0_TX_DISP_RFU0_LANE2 0 0x296b 1 0 2 rfu_value0 0 31 mmDC_COMBOPHYTXREGS0_TX_DISP_RFU1_LANE2 0 0x296c 1 0 2 rfu_value1 0 31 mmDC_COMBOPHYTXREGS0_TX_DISP_RFU2_LANE2 0 0x296d 1 0 2 rfu_value2 0 31 mmDC_COMBOPHYTXREGS0_TX_DISP_RFU3_LANE2 0 0x296e 1 0 2 rfu_value3 0 31 mmDC_COMBOPHYTXREGS0_TX_DISP_RFU4_LANE2 0 0x296f 1 0 2 rfu_value4 0 31 mmDC_COMBOPHYTXREGS0_TX_DISP_RFU5_LANE2 0 0x2970 1 0 2 rfu_value5 0 31 mmDC_COMBOPHYTXREGS0_TX_DISP_RFU6_LANE2 0 0x2971 1 0 2 rfu_value6 0 31 mmDC_COMBOPHYTXREGS0_TX_DISP_RFU7_LANE2 0 0x2972 1 0 2 rfu_value7 0 31 mmDC_COMBOPHYTXREGS0_TX_DISP_RFU8_LANE2 0 0x2973 1 0 2 rfu_value8 0 31 mmDC_COMBOPHYTXREGS0_TX_DISP_RFU9_LANE2 0 0x2974 1 0 2 rfu_value9 0 31 mmDC_COMBOPHYTXREGS0_TX_DISP_RFU10_LANE2 0 0x2975 1 0 2 rfu_value10 0 31 mmDC_COMBOPHYTXREGS0_TX_DISP_RFU11_LANE2 0 0x2976 1 0 2 rfu_value11 0 31 mmDC_COMBOPHYTXREGS0_TX_DISP_RFU12_LANE2 0 0x2977 1 0 2 rfu_value12 0 31 mmDC_COMBOPHYTXREGS0_CMD_BUS_TX_CONTROL_LANE3 0 0x2978 3 0 2 tx_pwr 0 2 tx_pg_en 3 4 tx_rdy 8 8 mmDC_COMBOPHYTXREGS0_MARGIN_DEEMPH_LANE3 0 0x2979 3 0 2 txmarg_sel 0 2 deemph_sel 3 4 tx_margin_en 5 5 mmDC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE3 0 0x297a 12 0 2 twosym_en 1 2 link_speed 3 4 gang_mode 5 7 max_linkrate 8 9 pcs_freq 10 11 pcs_clken 12 12 pcs_clkdone 13 13 pll1_always_on 14 14 rdclk_div2_en 15 15 tx_boost_adj 16 19 tx_boost_en 20 20 tx_binary_ron_code_offset 22 23 mmDC_COMBOPHYTXREGS0_TX_DISP_RFU0_LANE3 0 0x297b 1 0 2 rfu_value0 0 31 mmDC_COMBOPHYTXREGS0_TX_DISP_RFU1_LANE3 0 0x297c 1 0 2 rfu_value1 0 31 mmDC_COMBOPHYTXREGS0_TX_DISP_RFU2_LANE3 0 0x297d 1 0 2 rfu_value2 0 31 mmDC_COMBOPHYTXREGS0_TX_DISP_RFU3_LANE3 0 0x297e 1 0 2 rfu_value3 0 31 mmDC_COMBOPHYTXREGS0_TX_DISP_RFU4_LANE3 0 0x297f 1 0 2 rfu_value4 0 31 mmDC_COMBOPHYTXREGS0_TX_DISP_RFU5_LANE3 0 0x2980 1 0 2 rfu_value5 0 31 mmDC_COMBOPHYTXREGS0_TX_DISP_RFU6_LANE3 0 0x2981 1 0 2 rfu_value6 0 31 mmDC_COMBOPHYTXREGS0_TX_DISP_RFU7_LANE3 0 0x2982 1 0 2 rfu_value7 0 31 mmDC_COMBOPHYTXREGS0_TX_DISP_RFU8_LANE3 0 0x2983 1 0 2 rfu_value8 0 31 mmDC_COMBOPHYTXREGS0_TX_DISP_RFU9_LANE3 0 0x2984 1 0 2 rfu_value9 0 31 mmDC_COMBOPHYTXREGS0_TX_DISP_RFU10_LANE3 0 0x2985 1 0 2 rfu_value10 0 31 mmDC_COMBOPHYTXREGS0_TX_DISP_RFU11_LANE3 0 0x2986 1 0 2 rfu_value11 0 31 mmDC_COMBOPHYTXREGS0_TX_DISP_RFU12_LANE3 0 0x2987 1 0 2 rfu_value12 0 31 mmDC_COMBOPHYPLLREGS0_FREQ_CTRL0 0 0x2988 2 0 2 fcw0_frac 0 15 fcw0_int 16 24 mmDC_COMBOPHYPLLREGS0_FREQ_CTRL1 0 0x2989 2 0 2 fcw1_frac 0 15 fcw1_int 16 24 mmDC_COMBOPHYPLLREGS0_FREQ_CTRL2 0 0x298a 2 0 2 fcw_denom 0 15 fcw_slew_frac 16 31 mmDC_COMBOPHYPLLREGS0_FREQ_CTRL3 0 0x298b 8 0 2 refclk_div 0 1 vco_pre_div 3 4 fracn_en 6 6 ssc_en 8 8 fcw_sel 10 10 freq_jump_en 12 12 tdc_resolution 16 23 dpll_cfg_1 24 31 mmDC_COMBOPHYPLLREGS0_BW_CTRL_COARSE 0 0x298c 6 0 2 gi_coarse_mant 0 1 gi_coarse_exp 2 5 gp_coarse_mant 7 10 gp_coarse_exp 12 15 nctl_coarse_res 17 22 nctl_coarse_frac_res 24 25 mmDC_COMBOPHYPLLREGS0_BW_CTRL_FINE 0 0x298d 1 0 2 dpll_cfg_3 0 9 mmDC_COMBOPHYPLLREGS0_CAL_CTRL 0 0x298e 9 0 2 bypass_freq_lock 0 0 tdc_cal_en 1 1 tdc_cal_ctrl 3 8 meas_win_sel 9 10 kdco_cal_dis 11 11 kdco_ratio 13 20 kdco_incr_cal_dis 22 22 nctl_adj_dis 23 23 refclk_rate 24 31 mmDC_COMBOPHYPLLREGS0_LOOP_CTRL 0 0x298f 10 0 2 fbdiv_mask_en 0 0 fb_slip_dis 2 2 clk_tdc_sel 4 5 clk_nctl_sel 7 8 sig_del_patt_sel 10 10 nctl_sig_del_dis 12 12 fbclk_track_refclk 14 14 prbs_en 16 16 tdc_clk_gate_en 18 18 phase_offset 20 26 mmDC_COMBOPHYPLLREGS0_VREG_CFG 0 0x2991 14 0 2 bleeder_ac 0 0 bleeder_en 1 1 is_1p2 2 2 reg_obs_sel 3 4 reg_on_mode 5 6 rlad_tap_sel 7 10 reg_off_hi 11 11 reg_off_lo 12 12 scale_driver 13 14 sel_bump 15 15 sel_rladder_x 16 16 short_rc_filt_x 17 17 vref_pwr_on 18 18 dpll_cfg_2 20 27 mmDC_COMBOPHYPLLREGS0_OBSERVE0 0 0x2992 5 0 2 lock_det_tdc_steps 0 4 clear_sticky_lock 6 6 lock_det_dis 8 8 dco_cfg 10 17 anaobs_sel 21 23 mmDC_COMBOPHYPLLREGS0_OBSERVE1 0 0x2993 5 0 2 digobs_sel 0 3 digobs_trig_sel 5 8 digobs_div 10 11 digobs_trig_div 13 14 lock_timer 16 29 mmDC_COMBOPHYPLLREGS0_DFT_OUT 0 0x2994 1 0 2 dft_data 0 31 mmDC_COMBOPHYPLLREGS0_PLL_WRAP_CNTRL1 0 0x29c6 1 0 2 wrap_cfg_sel_clk 0 1 mmDC_COMBOPHYPLLREGS0_PLL_WRAP_CNTRL 0 0x29c7 11 0 2 wrap_cfg_pll_freq_programming_ovveride 0 0 wrap_cfg_pll_pwr_state_ovrride 1 1 wrap_cfg_pll_pwr_state 2 3 wrap_cfg_tx_pdiv_val 5 7 wrap_cfg_tx_pixdiv_val 8 8 wrap_cfg_cml_cmos_sel 10 10 wrap_cfg_pll_rdy 13 13 wrap_cfg_pll_update 14 14 wrap_cfg_ref_values_chg 15 15 wrap_cfg_clk_gate_w_rdy 16 16 wrap_cfg_pll_dsm_sel 17 19 mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED0 0 0x2a00 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED1 0 0x2a01 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED2 0 0x2a02 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED3 0 0x2a03 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED4 0 0x2a04 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED5 0 0x2a05 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED6 0 0x2a06 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED7 0 0x2a07 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED8 0 0x2a08 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED9 0 0x2a09 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED10 0 0x2a0a 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED11 0 0x2a0b 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED12 0 0x2a0c 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED13 0 0x2a0d 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED14 0 0x2a0e 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED15 0 0x2a0f 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED16 0 0x2a10 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED17 0 0x2a11 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED18 0 0x2a12 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED19 0 0x2a13 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED20 0 0x2a14 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED21 0 0x2a15 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED22 0 0x2a16 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED23 0 0x2a17 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED24 0 0x2a18 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED25 0 0x2a19 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED26 0 0x2a1a 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED27 0 0x2a1b 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED28 0 0x2a1c 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED29 0 0x2a1d 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED30 0 0x2a1e 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED31 0 0x2a1f 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED32 0 0x2a20 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED33 0 0x2a21 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED34 0 0x2a22 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED35 0 0x2a23 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED36 0 0x2a24 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED37 0 0x2a25 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED38 0 0x2a26 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED39 0 0x2a27 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED40 0 0x2a28 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED41 0 0x2a29 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED42 0 0x2a2a 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED43 0 0x2a2b 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED44 0 0x2a2c 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED45 0 0x2a2d 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED46 0 0x2a2e 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED47 0 0x2a2f 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED48 0 0x2a30 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED49 0 0x2a31 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED50 0 0x2a32 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED51 0 0x2a33 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED52 0 0x2a34 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED53 0 0x2a35 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED54 0 0x2a36 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED55 0 0x2a37 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED56 0 0x2a38 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED57 0 0x2a39 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED58 0 0x2a3a 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED59 0 0x2a3b 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED60 0 0x2a3c 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED61 0 0x2a3d 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED62 0 0x2a3e 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED63 0 0x2a3f 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED64 0 0x2a40 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED65 0 0x2a41 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED66 0 0x2a42 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED67 0 0x2a43 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED68 0 0x2a44 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED69 0 0x2a45 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED70 0 0x2a46 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED71 0 0x2a47 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED72 0 0x2a48 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED73 0 0x2a49 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED74 0 0x2a4a 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED75 0 0x2a4b 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED76 0 0x2a4c 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED77 0 0x2a4d 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED78 0 0x2a4e 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED79 0 0x2a4f 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED80 0 0x2a50 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED81 0 0x2a51 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED82 0 0x2a52 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED83 0 0x2a53 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED84 0 0x2a54 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED85 0 0x2a55 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED86 0 0x2a56 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED87 0 0x2a57 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED88 0 0x2a58 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED89 0 0x2a59 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED90 0 0x2a5a 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED91 0 0x2a5b 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED92 0 0x2a5c 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED93 0 0x2a5d 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED94 0 0x2a5e 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED95 0 0x2a5f 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED96 0 0x2a60 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED97 0 0x2a61 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED98 0 0x2a62 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED99 0 0x2a63 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED100 0 0x2a64 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED101 0 0x2a65 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED102 0 0x2a66 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED103 0 0x2a67 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED104 0 0x2a68 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED105 0 0x2a69 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED106 0 0x2a6a 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED107 0 0x2a6b 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED108 0 0x2a6c 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED109 0 0x2a6d 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED110 0 0x2a6e 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED111 0 0x2a6f 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED112 0 0x2a70 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED113 0 0x2a71 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED114 0 0x2a72 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED115 0 0x2a73 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED116 0 0x2a74 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED117 0 0x2a75 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED118 0 0x2a76 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED119 0 0x2a77 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED120 0 0x2a78 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED121 0 0x2a79 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED122 0 0x2a7a 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED123 0 0x2a7b 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED124 0 0x2a7c 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED125 0 0x2a7d 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED126 0 0x2a7e 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED127 0 0x2a7f 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED128 0 0x2a80 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED129 0 0x2a81 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED130 0 0x2a82 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED131 0 0x2a83 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED132 0 0x2a84 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED133 0 0x2a85 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED134 0 0x2a86 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED135 0 0x2a87 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED136 0 0x2a88 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED137 0 0x2a89 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED138 0 0x2a8a 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED139 0 0x2a8b 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED140 0 0x2a8c 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED141 0 0x2a8d 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED142 0 0x2a8e 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED143 0 0x2a8f 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED144 0 0x2a90 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED145 0 0x2a91 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED146 0 0x2a92 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED147 0 0x2a93 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED148 0 0x2a94 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED149 0 0x2a95 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED150 0 0x2a96 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED151 0 0x2a97 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED152 0 0x2a98 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED153 0 0x2a99 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED154 0 0x2a9a 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED155 0 0x2a9b 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED156 0 0x2a9c 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED157 0 0x2a9d 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED158 0 0x2a9e 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED159 0 0x2a9f 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDC_COMBOPHYCMREGS1_COMMON_FUSE1 0 0x2a00 11 0 2 fuse1_valid 0 0 fuse1_unpopulated0 1 2 fuse1_ron_override_val 3 8 fuse1_unpopulated1 9 9 fuse1_ron_ctl 10 11 fuse1_unpopulated2 12 12 fuse1_rtt_override_val 13 18 fuse1_unpopulated3 19 19 fuse1_rtt_ctl 20 21 fuse1_refresh_cal_en 22 22 fuse1_spare 23 31 mmDC_COMBOPHYCMREGS1_COMMON_FUSE2 0 0x2a01 4 0 2 fuse2_valid 0 0 fuse2_unpopulated 1 8 fuse2_tx_fifo_ptr 9 13 fuse2_spare 14 31 mmDC_COMBOPHYCMREGS1_COMMON_FUSE3 0 0x2a02 11 0 2 fuse3_valid 0 0 fuse3_unpopulated 1 9 fuse3_ei_det_thresh_sel 10 12 cdr_dac_safeval_sel 13 15 cdr_freq_lock_timer 16 17 cdr_cal_dac_stpsz 18 19 cdr_byp_init_val 20 20 cdr_icostart_sel 21 21 cdr_bbweight 22 25 cdr_cur_mirr_ratio 26 28 fuse3_spare 29 31 mmDC_COMBOPHYCMREGS1_COMMON_MAR_DEEMPH_NOM 0 0x2a03 4 0 2 tx_margin_nom 0 7 deemph_gen1_nom 8 15 deemph35_gen2_nom 16 23 deemph60_gen2_nom 24 31 mmDC_COMBOPHYCMREGS1_COMMON_LANE_PWRMGMT 0 0x2a04 3 0 2 pgdelay 0 3 pgmask 4 9 vprot_en 11 11 mmDC_COMBOPHYCMREGS1_COMMON_TXCNTRL 0 0x2a05 5 0 2 rdptr_rst_val_gen3 0 4 clkgate_dis 5 5 slew_rate_ctl_gen1 6 8 slew_rate_ctl_gen2 9 11 slew_rate_ctl_gen3 12 14 mmDC_COMBOPHYCMREGS1_COMMON_TMDP 0 0x2a06 1 0 2 tmdp_spare 0 31 mmDC_COMBOPHYCMREGS1_COMMON_LANE_RESETS 0 0x2a07 8 0 2 lane_0_reset_l 0 0 lane_1_reset_l 1 1 lane_2_reset_l 2 2 lane_3_reset_l 3 3 lane_4_reset_l 4 4 lane_5_reset_l 5 5 lane_6_reset_l 6 6 lane_7_reset_l 7 7 mmDC_COMBOPHYCMREGS1_COMMON_ZCALCODE_CTRL 0 0x2a08 4 0 2 zcalcode_override 0 0 tx_binary_code_override_val 1 5 rx_therm_code_override_val 6 20 tx_driver_fifty_ohms 21 21 mmDC_COMBOPHYCMREGS1_COMMON_DISP_RFU1 0 0x2a09 1 0 2 rfu_value1 0 31 mmDC_COMBOPHYCMREGS1_COMMON_DISP_RFU2 0 0x2a0a 1 0 2 rfu_value2 0 31 mmDC_COMBOPHYCMREGS1_COMMON_DISP_RFU3 0 0x2a0b 1 0 2 rfu_value3 0 31 mmDC_COMBOPHYCMREGS1_COMMON_DISP_RFU4 0 0x2a0c 1 0 2 rfu_value4 0 31 mmDC_COMBOPHYCMREGS1_COMMON_DISP_RFU5 0 0x2a0d 1 0 2 rfu_value5 0 31 mmDC_COMBOPHYCMREGS1_COMMON_DISP_RFU6 0 0x2a0e 1 0 2 rfu_value6 0 31 mmDC_COMBOPHYCMREGS1_COMMON_DISP_RFU7 0 0x2a0f 1 0 2 rfu_value7 0 31 mmDC_COMBOPHYTXREGS1_CMD_BUS_TX_CONTROL_LANE0 0 0x2a20 3 0 2 tx_pwr 0 2 tx_pg_en 3 4 tx_rdy 8 8 mmDC_COMBOPHYTXREGS1_MARGIN_DEEMPH_LANE0 0 0x2a21 3 0 2 txmarg_sel 0 2 deemph_sel 3 4 tx_margin_en 5 5 mmDC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE0 0 0x2a22 12 0 2 twosym_en 1 2 link_speed 3 4 gang_mode 5 7 max_linkrate 8 9 pcs_freq 10 11 pcs_clken 12 12 pcs_clkdone 13 13 pll1_always_on 14 14 rdclk_div2_en 15 15 tx_boost_adj 16 19 tx_boost_en 20 20 tx_binary_ron_code_offset 22 23 mmDC_COMBOPHYTXREGS1_TX_DISP_RFU0_LANE0 0 0x2a23 1 0 2 rfu_value0 0 31 mmDC_COMBOPHYTXREGS1_TX_DISP_RFU1_LANE0 0 0x2a24 1 0 2 rfu_value1 0 31 mmDC_COMBOPHYTXREGS1_TX_DISP_RFU2_LANE0 0 0x2a25 1 0 2 rfu_value2 0 31 mmDC_COMBOPHYTXREGS1_TX_DISP_RFU3_LANE0 0 0x2a26 1 0 2 rfu_value3 0 31 mmDC_COMBOPHYTXREGS1_TX_DISP_RFU4_LANE0 0 0x2a27 1 0 2 rfu_value4 0 31 mmDC_COMBOPHYTXREGS1_TX_DISP_RFU5_LANE0 0 0x2a28 1 0 2 rfu_value5 0 31 mmDC_COMBOPHYTXREGS1_TX_DISP_RFU6_LANE0 0 0x2a29 1 0 2 rfu_value6 0 31 mmDC_COMBOPHYTXREGS1_TX_DISP_RFU7_LANE0 0 0x2a2a 1 0 2 rfu_value7 0 31 mmDC_COMBOPHYTXREGS1_TX_DISP_RFU8_LANE0 0 0x2a2b 1 0 2 rfu_value8 0 31 mmDC_COMBOPHYTXREGS1_TX_DISP_RFU9_LANE0 0 0x2a2c 1 0 2 rfu_value9 0 31 mmDC_COMBOPHYTXREGS1_TX_DISP_RFU10_LANE0 0 0x2a2d 1 0 2 rfu_value10 0 31 mmDC_COMBOPHYTXREGS1_TX_DISP_RFU11_LANE0 0 0x2a2e 1 0 2 rfu_value11 0 31 mmDC_COMBOPHYTXREGS1_TX_DISP_RFU12_LANE0 0 0x2a2f 1 0 2 rfu_value12 0 31 mmDC_COMBOPHYTXREGS1_CMD_BUS_TX_CONTROL_LANE1 0 0x2a30 3 0 2 tx_pwr 0 2 tx_pg_en 3 4 tx_rdy 8 8 mmDC_COMBOPHYTXREGS1_MARGIN_DEEMPH_LANE1 0 0x2a31 3 0 2 txmarg_sel 0 2 deemph_sel 3 4 tx_margin_en 5 5 mmDC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE1 0 0x2a32 12 0 2 twosym_en 1 2 link_speed 3 4 gang_mode 5 7 max_linkrate 8 9 pcs_freq 10 11 pcs_clken 12 12 pcs_clkdone 13 13 pll1_always_on 14 14 rdclk_div2_en 15 15 tx_boost_adj 16 19 tx_boost_en 20 20 tx_binary_ron_code_offset 22 23 mmDC_COMBOPHYTXREGS1_TX_DISP_RFU0_LANE1 0 0x2a33 1 0 2 rfu_value0 0 31 mmDC_COMBOPHYTXREGS1_TX_DISP_RFU1_LANE1 0 0x2a34 1 0 2 rfu_value1 0 31 mmDC_COMBOPHYTXREGS1_TX_DISP_RFU2_LANE1 0 0x2a35 1 0 2 rfu_value2 0 31 mmDC_COMBOPHYTXREGS1_TX_DISP_RFU3_LANE1 0 0x2a36 1 0 2 rfu_value3 0 31 mmDC_COMBOPHYTXREGS1_TX_DISP_RFU4_LANE1 0 0x2a37 1 0 2 rfu_value4 0 31 mmDC_COMBOPHYTXREGS1_TX_DISP_RFU5_LANE1 0 0x2a38 1 0 2 rfu_value5 0 31 mmDC_COMBOPHYTXREGS1_TX_DISP_RFU6_LANE1 0 0x2a39 1 0 2 rfu_value6 0 31 mmDC_COMBOPHYTXREGS1_TX_DISP_RFU7_LANE1 0 0x2a3a 1 0 2 rfu_value7 0 31 mmDC_COMBOPHYTXREGS1_TX_DISP_RFU8_LANE1 0 0x2a3b 1 0 2 rfu_value8 0 31 mmDC_COMBOPHYTXREGS1_TX_DISP_RFU9_LANE1 0 0x2a3c 1 0 2 rfu_value9 0 31 mmDC_COMBOPHYTXREGS1_TX_DISP_RFU10_LANE1 0 0x2a3d 1 0 2 rfu_value10 0 31 mmDC_COMBOPHYTXREGS1_TX_DISP_RFU11_LANE1 0 0x2a3e 1 0 2 rfu_value11 0 31 mmDC_COMBOPHYTXREGS1_TX_DISP_RFU12_LANE1 0 0x2a3f 1 0 2 rfu_value12 0 31 mmDC_COMBOPHYTXREGS1_CMD_BUS_TX_CONTROL_LANE2 0 0x2a40 3 0 2 tx_pwr 0 2 tx_pg_en 3 4 tx_rdy 8 8 mmDC_COMBOPHYTXREGS1_MARGIN_DEEMPH_LANE2 0 0x2a41 3 0 2 txmarg_sel 0 2 deemph_sel 3 4 tx_margin_en 5 5 mmDC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE2 0 0x2a42 12 0 2 twosym_en 1 2 link_speed 3 4 gang_mode 5 7 max_linkrate 8 9 pcs_freq 10 11 pcs_clken 12 12 pcs_clkdone 13 13 pll1_always_on 14 14 rdclk_div2_en 15 15 tx_boost_adj 16 19 tx_boost_en 20 20 tx_binary_ron_code_offset 22 23 mmDC_COMBOPHYTXREGS1_TX_DISP_RFU0_LANE2 0 0x2a43 1 0 2 rfu_value0 0 31 mmDC_COMBOPHYTXREGS1_TX_DISP_RFU1_LANE2 0 0x2a44 1 0 2 rfu_value1 0 31 mmDC_COMBOPHYTXREGS1_TX_DISP_RFU2_LANE2 0 0x2a45 1 0 2 rfu_value2 0 31 mmDC_COMBOPHYTXREGS1_TX_DISP_RFU3_LANE2 0 0x2a46 1 0 2 rfu_value3 0 31 mmDC_COMBOPHYTXREGS1_TX_DISP_RFU4_LANE2 0 0x2a47 1 0 2 rfu_value4 0 31 mmDC_COMBOPHYTXREGS1_TX_DISP_RFU5_LANE2 0 0x2a48 1 0 2 rfu_value5 0 31 mmDC_COMBOPHYTXREGS1_TX_DISP_RFU6_LANE2 0 0x2a49 1 0 2 rfu_value6 0 31 mmDC_COMBOPHYTXREGS1_TX_DISP_RFU7_LANE2 0 0x2a4a 1 0 2 rfu_value7 0 31 mmDC_COMBOPHYTXREGS1_TX_DISP_RFU8_LANE2 0 0x2a4b 1 0 2 rfu_value8 0 31 mmDC_COMBOPHYTXREGS1_TX_DISP_RFU9_LANE2 0 0x2a4c 1 0 2 rfu_value9 0 31 mmDC_COMBOPHYTXREGS1_TX_DISP_RFU10_LANE2 0 0x2a4d 1 0 2 rfu_value10 0 31 mmDC_COMBOPHYTXREGS1_TX_DISP_RFU11_LANE2 0 0x2a4e 1 0 2 rfu_value11 0 31 mmDC_COMBOPHYTXREGS1_TX_DISP_RFU12_LANE2 0 0x2a4f 1 0 2 rfu_value12 0 31 mmDC_COMBOPHYTXREGS1_CMD_BUS_TX_CONTROL_LANE3 0 0x2a50 3 0 2 tx_pwr 0 2 tx_pg_en 3 4 tx_rdy 8 8 mmDC_COMBOPHYTXREGS1_MARGIN_DEEMPH_LANE3 0 0x2a51 3 0 2 txmarg_sel 0 2 deemph_sel 3 4 tx_margin_en 5 5 mmDC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE3 0 0x2a52 12 0 2 twosym_en 1 2 link_speed 3 4 gang_mode 5 7 max_linkrate 8 9 pcs_freq 10 11 pcs_clken 12 12 pcs_clkdone 13 13 pll1_always_on 14 14 rdclk_div2_en 15 15 tx_boost_adj 16 19 tx_boost_en 20 20 tx_binary_ron_code_offset 22 23 mmDC_COMBOPHYTXREGS1_TX_DISP_RFU0_LANE3 0 0x2a53 1 0 2 rfu_value0 0 31 mmDC_COMBOPHYTXREGS1_TX_DISP_RFU1_LANE3 0 0x2a54 1 0 2 rfu_value1 0 31 mmDC_COMBOPHYTXREGS1_TX_DISP_RFU2_LANE3 0 0x2a55 1 0 2 rfu_value2 0 31 mmDC_COMBOPHYTXREGS1_TX_DISP_RFU3_LANE3 0 0x2a56 1 0 2 rfu_value3 0 31 mmDC_COMBOPHYTXREGS1_TX_DISP_RFU4_LANE3 0 0x2a57 1 0 2 rfu_value4 0 31 mmDC_COMBOPHYTXREGS1_TX_DISP_RFU5_LANE3 0 0x2a58 1 0 2 rfu_value5 0 31 mmDC_COMBOPHYTXREGS1_TX_DISP_RFU6_LANE3 0 0x2a59 1 0 2 rfu_value6 0 31 mmDC_COMBOPHYTXREGS1_TX_DISP_RFU7_LANE3 0 0x2a5a 1 0 2 rfu_value7 0 31 mmDC_COMBOPHYTXREGS1_TX_DISP_RFU8_LANE3 0 0x2a5b 1 0 2 rfu_value8 0 31 mmDC_COMBOPHYTXREGS1_TX_DISP_RFU9_LANE3 0 0x2a5c 1 0 2 rfu_value9 0 31 mmDC_COMBOPHYTXREGS1_TX_DISP_RFU10_LANE3 0 0x2a5d 1 0 2 rfu_value10 0 31 mmDC_COMBOPHYTXREGS1_TX_DISP_RFU11_LANE3 0 0x2a5e 1 0 2 rfu_value11 0 31 mmDC_COMBOPHYTXREGS1_TX_DISP_RFU12_LANE3 0 0x2a5f 1 0 2 rfu_value12 0 31 mmDC_COMBOPHYPLLREGS1_FREQ_CTRL0 0 0x2a60 2 0 2 fcw0_frac 0 15 fcw0_int 16 24 mmDC_COMBOPHYPLLREGS1_FREQ_CTRL1 0 0x2a61 2 0 2 fcw1_frac 0 15 fcw1_int 16 24 mmDC_COMBOPHYPLLREGS1_FREQ_CTRL2 0 0x2a62 2 0 2 fcw_denom 0 15 fcw_slew_frac 16 31 mmDC_COMBOPHYPLLREGS1_FREQ_CTRL3 0 0x2a63 8 0 2 refclk_div 0 1 vco_pre_div 3 4 fracn_en 6 6 ssc_en 8 8 fcw_sel 10 10 freq_jump_en 12 12 tdc_resolution 16 23 dpll_cfg_1 24 31 mmDC_COMBOPHYPLLREGS1_BW_CTRL_COARSE 0 0x2a64 6 0 2 gi_coarse_mant 0 1 gi_coarse_exp 2 5 gp_coarse_mant 7 10 gp_coarse_exp 12 15 nctl_coarse_res 17 22 nctl_coarse_frac_res 24 25 mmDC_COMBOPHYPLLREGS1_BW_CTRL_FINE 0 0x2a65 1 0 2 dpll_cfg_3 0 9 mmDC_COMBOPHYPLLREGS1_CAL_CTRL 0 0x2a66 9 0 2 bypass_freq_lock 0 0 tdc_cal_en 1 1 tdc_cal_ctrl 3 8 meas_win_sel 9 10 kdco_cal_dis 11 11 kdco_ratio 13 20 kdco_incr_cal_dis 22 22 nctl_adj_dis 23 23 refclk_rate 24 31 mmDC_COMBOPHYPLLREGS1_LOOP_CTRL 0 0x2a67 10 0 2 fbdiv_mask_en 0 0 fb_slip_dis 2 2 clk_tdc_sel 4 5 clk_nctl_sel 7 8 sig_del_patt_sel 10 10 nctl_sig_del_dis 12 12 fbclk_track_refclk 14 14 prbs_en 16 16 tdc_clk_gate_en 18 18 phase_offset 20 26 mmDC_COMBOPHYPLLREGS1_VREG_CFG 0 0x2a69 14 0 2 bleeder_ac 0 0 bleeder_en 1 1 is_1p2 2 2 reg_obs_sel 3 4 reg_on_mode 5 6 rlad_tap_sel 7 10 reg_off_hi 11 11 reg_off_lo 12 12 scale_driver 13 14 sel_bump 15 15 sel_rladder_x 16 16 short_rc_filt_x 17 17 vref_pwr_on 18 18 dpll_cfg_2 20 27 mmDC_COMBOPHYPLLREGS1_OBSERVE0 0 0x2a6a 5 0 2 lock_det_tdc_steps 0 4 clear_sticky_lock 6 6 lock_det_dis 8 8 dco_cfg 10 17 anaobs_sel 21 23 mmDC_COMBOPHYPLLREGS1_OBSERVE1 0 0x2a6b 5 0 2 digobs_sel 0 3 digobs_trig_sel 5 8 digobs_div 10 11 digobs_trig_div 13 14 lock_timer 16 29 mmDC_COMBOPHYPLLREGS1_DFT_OUT 0 0x2a6c 1 0 2 dft_data 0 31 mmDC_COMBOPHYPLLREGS1_PLL_WRAP_CNTRL1 0 0x2a9e 1 0 2 wrap_cfg_sel_clk 0 1 mmDC_COMBOPHYPLLREGS1_PLL_WRAP_CNTRL 0 0x2a9f 11 0 2 wrap_cfg_pll_freq_programming_ovveride 0 0 wrap_cfg_pll_pwr_state_ovrride 1 1 wrap_cfg_pll_pwr_state 2 3 wrap_cfg_tx_pdiv_val 5 7 wrap_cfg_tx_pixdiv_val 8 8 wrap_cfg_cml_cmos_sel 10 10 wrap_cfg_pll_rdy 13 13 wrap_cfg_pll_update 14 14 wrap_cfg_ref_values_chg 15 15 wrap_cfg_clk_gate_w_rdy 16 16 wrap_cfg_pll_dsm_sel 17 19 mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED0 0 0x2ad8 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED1 0 0x2ad9 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED2 0 0x2ada 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED3 0 0x2adb 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED4 0 0x2adc 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED5 0 0x2add 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED6 0 0x2ade 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED7 0 0x2adf 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED8 0 0x2ae0 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED9 0 0x2ae1 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED10 0 0x2ae2 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED11 0 0x2ae3 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED12 0 0x2ae4 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED13 0 0x2ae5 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED14 0 0x2ae6 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED15 0 0x2ae7 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED16 0 0x2ae8 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED17 0 0x2ae9 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED18 0 0x2aea 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED19 0 0x2aeb 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED20 0 0x2aec 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED21 0 0x2aed 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED22 0 0x2aee 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED23 0 0x2aef 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED24 0 0x2af0 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED25 0 0x2af1 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED26 0 0x2af2 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED27 0 0x2af3 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED28 0 0x2af4 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED29 0 0x2af5 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED30 0 0x2af6 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED31 0 0x2af7 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED32 0 0x2af8 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED33 0 0x2af9 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED34 0 0x2afa 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED35 0 0x2afb 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED36 0 0x2afc 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED37 0 0x2afd 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED38 0 0x2afe 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED39 0 0x2aff 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED40 0 0x2b00 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED41 0 0x2b01 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED42 0 0x2b02 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED43 0 0x2b03 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED44 0 0x2b04 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED45 0 0x2b05 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED46 0 0x2b06 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED47 0 0x2b07 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED48 0 0x2b08 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED49 0 0x2b09 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED50 0 0x2b0a 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED51 0 0x2b0b 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED52 0 0x2b0c 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED53 0 0x2b0d 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED54 0 0x2b0e 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED55 0 0x2b0f 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED56 0 0x2b10 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED57 0 0x2b11 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED58 0 0x2b12 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED59 0 0x2b13 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED60 0 0x2b14 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED61 0 0x2b15 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED62 0 0x2b16 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED63 0 0x2b17 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED64 0 0x2b18 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED65 0 0x2b19 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED66 0 0x2b1a 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED67 0 0x2b1b 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED68 0 0x2b1c 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED69 0 0x2b1d 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED70 0 0x2b1e 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED71 0 0x2b1f 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED72 0 0x2b20 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED73 0 0x2b21 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED74 0 0x2b22 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED75 0 0x2b23 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED76 0 0x2b24 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED77 0 0x2b25 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED78 0 0x2b26 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED79 0 0x2b27 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED80 0 0x2b28 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED81 0 0x2b29 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED82 0 0x2b2a 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED83 0 0x2b2b 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED84 0 0x2b2c 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED85 0 0x2b2d 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED86 0 0x2b2e 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED87 0 0x2b2f 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED88 0 0x2b30 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED89 0 0x2b31 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED90 0 0x2b32 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED91 0 0x2b33 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED92 0 0x2b34 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED93 0 0x2b35 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED94 0 0x2b36 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED95 0 0x2b37 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED96 0 0x2b38 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED97 0 0x2b39 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED98 0 0x2b3a 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED99 0 0x2b3b 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED100 0 0x2b3c 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED101 0 0x2b3d 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED102 0 0x2b3e 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED103 0 0x2b3f 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED104 0 0x2b40 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED105 0 0x2b41 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED106 0 0x2b42 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED107 0 0x2b43 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED108 0 0x2b44 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED109 0 0x2b45 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED110 0 0x2b46 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED111 0 0x2b47 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED112 0 0x2b48 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED113 0 0x2b49 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED114 0 0x2b4a 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED115 0 0x2b4b 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED116 0 0x2b4c 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED117 0 0x2b4d 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED118 0 0x2b4e 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED119 0 0x2b4f 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED120 0 0x2b50 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED121 0 0x2b51 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED122 0 0x2b52 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED123 0 0x2b53 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED124 0 0x2b54 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED125 0 0x2b55 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED126 0 0x2b56 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED127 0 0x2b57 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED128 0 0x2b58 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED129 0 0x2b59 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED130 0 0x2b5a 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED131 0 0x2b5b 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED132 0 0x2b5c 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED133 0 0x2b5d 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED134 0 0x2b5e 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED135 0 0x2b5f 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED136 0 0x2b60 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED137 0 0x2b61 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED138 0 0x2b62 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED139 0 0x2b63 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED140 0 0x2b64 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED141 0 0x2b65 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED142 0 0x2b66 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED143 0 0x2b67 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED144 0 0x2b68 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED145 0 0x2b69 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED146 0 0x2b6a 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED147 0 0x2b6b 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED148 0 0x2b6c 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED149 0 0x2b6d 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED150 0 0x2b6e 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED151 0 0x2b6f 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED152 0 0x2b70 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED153 0 0x2b71 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED154 0 0x2b72 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED155 0 0x2b73 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED156 0 0x2b74 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED157 0 0x2b75 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED158 0 0x2b76 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED159 0 0x2b77 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDC_COMBOPHYCMREGS2_COMMON_FUSE1 0 0x2ad8 11 0 2 fuse1_valid 0 0 fuse1_unpopulated0 1 2 fuse1_ron_override_val 3 8 fuse1_unpopulated1 9 9 fuse1_ron_ctl 10 11 fuse1_unpopulated2 12 12 fuse1_rtt_override_val 13 18 fuse1_unpopulated3 19 19 fuse1_rtt_ctl 20 21 fuse1_refresh_cal_en 22 22 fuse1_spare 23 31 mmDC_COMBOPHYCMREGS2_COMMON_FUSE2 0 0x2ad9 4 0 2 fuse2_valid 0 0 fuse2_unpopulated 1 8 fuse2_tx_fifo_ptr 9 13 fuse2_spare 14 31 mmDC_COMBOPHYCMREGS2_COMMON_FUSE3 0 0x2ada 11 0 2 fuse3_valid 0 0 fuse3_unpopulated 1 9 fuse3_ei_det_thresh_sel 10 12 cdr_dac_safeval_sel 13 15 cdr_freq_lock_timer 16 17 cdr_cal_dac_stpsz 18 19 cdr_byp_init_val 20 20 cdr_icostart_sel 21 21 cdr_bbweight 22 25 cdr_cur_mirr_ratio 26 28 fuse3_spare 29 31 mmDC_COMBOPHYCMREGS2_COMMON_MAR_DEEMPH_NOM 0 0x2adb 4 0 2 tx_margin_nom 0 7 deemph_gen1_nom 8 15 deemph35_gen2_nom 16 23 deemph60_gen2_nom 24 31 mmDC_COMBOPHYCMREGS2_COMMON_LANE_PWRMGMT 0 0x2adc 3 0 2 pgdelay 0 3 pgmask 4 9 vprot_en 11 11 mmDC_COMBOPHYCMREGS2_COMMON_TXCNTRL 0 0x2add 5 0 2 rdptr_rst_val_gen3 0 4 clkgate_dis 5 5 slew_rate_ctl_gen1 6 8 slew_rate_ctl_gen2 9 11 slew_rate_ctl_gen3 12 14 mmDC_COMBOPHYCMREGS2_COMMON_TMDP 0 0x2ade 1 0 2 tmdp_spare 0 31 mmDC_COMBOPHYCMREGS2_COMMON_LANE_RESETS 0 0x2adf 8 0 2 lane_0_reset_l 0 0 lane_1_reset_l 1 1 lane_2_reset_l 2 2 lane_3_reset_l 3 3 lane_4_reset_l 4 4 lane_5_reset_l 5 5 lane_6_reset_l 6 6 lane_7_reset_l 7 7 mmDC_COMBOPHYCMREGS2_COMMON_ZCALCODE_CTRL 0 0x2ae0 4 0 2 zcalcode_override 0 0 tx_binary_code_override_val 1 5 rx_therm_code_override_val 6 20 tx_driver_fifty_ohms 21 21 mmDC_COMBOPHYCMREGS2_COMMON_DISP_RFU1 0 0x2ae1 1 0 2 rfu_value1 0 31 mmDC_COMBOPHYCMREGS2_COMMON_DISP_RFU2 0 0x2ae2 1 0 2 rfu_value2 0 31 mmDC_COMBOPHYCMREGS2_COMMON_DISP_RFU3 0 0x2ae3 1 0 2 rfu_value3 0 31 mmDC_COMBOPHYCMREGS2_COMMON_DISP_RFU4 0 0x2ae4 1 0 2 rfu_value4 0 31 mmDC_COMBOPHYCMREGS2_COMMON_DISP_RFU5 0 0x2ae5 1 0 2 rfu_value5 0 31 mmDC_COMBOPHYCMREGS2_COMMON_DISP_RFU6 0 0x2ae6 1 0 2 rfu_value6 0 31 mmDC_COMBOPHYCMREGS2_COMMON_DISP_RFU7 0 0x2ae7 1 0 2 rfu_value7 0 31 mmDC_COMBOPHYTXREGS2_CMD_BUS_TX_CONTROL_LANE0 0 0x2af8 3 0 2 tx_pwr 0 2 tx_pg_en 3 4 tx_rdy 8 8 mmDC_COMBOPHYTXREGS2_MARGIN_DEEMPH_LANE0 0 0x2af9 3 0 2 txmarg_sel 0 2 deemph_sel 3 4 tx_margin_en 5 5 mmDC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE0 0 0x2afa 12 0 2 twosym_en 1 2 link_speed 3 4 gang_mode 5 7 max_linkrate 8 9 pcs_freq 10 11 pcs_clken 12 12 pcs_clkdone 13 13 pll1_always_on 14 14 rdclk_div2_en 15 15 tx_boost_adj 16 19 tx_boost_en 20 20 tx_binary_ron_code_offset 22 23 mmDC_COMBOPHYTXREGS2_TX_DISP_RFU0_LANE0 0 0x2afb 1 0 2 rfu_value0 0 31 mmDC_COMBOPHYTXREGS2_TX_DISP_RFU1_LANE0 0 0x2afc 1 0 2 rfu_value1 0 31 mmDC_COMBOPHYTXREGS2_TX_DISP_RFU2_LANE0 0 0x2afd 1 0 2 rfu_value2 0 31 mmDC_COMBOPHYTXREGS2_TX_DISP_RFU3_LANE0 0 0x2afe 1 0 2 rfu_value3 0 31 mmDC_COMBOPHYTXREGS2_TX_DISP_RFU4_LANE0 0 0x2aff 1 0 2 rfu_value4 0 31 mmDC_COMBOPHYTXREGS2_TX_DISP_RFU5_LANE0 0 0x2b00 1 0 2 rfu_value5 0 31 mmDC_COMBOPHYTXREGS2_TX_DISP_RFU6_LANE0 0 0x2b01 1 0 2 rfu_value6 0 31 mmDC_COMBOPHYTXREGS2_TX_DISP_RFU7_LANE0 0 0x2b02 1 0 2 rfu_value7 0 31 mmDC_COMBOPHYTXREGS2_TX_DISP_RFU8_LANE0 0 0x2b03 1 0 2 rfu_value8 0 31 mmDC_COMBOPHYTXREGS2_TX_DISP_RFU9_LANE0 0 0x2b04 1 0 2 rfu_value9 0 31 mmDC_COMBOPHYTXREGS2_TX_DISP_RFU10_LANE0 0 0x2b05 1 0 2 rfu_value10 0 31 mmDC_COMBOPHYTXREGS2_TX_DISP_RFU11_LANE0 0 0x2b06 1 0 2 rfu_value11 0 31 mmDC_COMBOPHYTXREGS2_TX_DISP_RFU12_LANE0 0 0x2b07 1 0 2 rfu_value12 0 31 mmDC_COMBOPHYTXREGS2_CMD_BUS_TX_CONTROL_LANE1 0 0x2b08 3 0 2 tx_pwr 0 2 tx_pg_en 3 4 tx_rdy 8 8 mmDC_COMBOPHYTXREGS2_MARGIN_DEEMPH_LANE1 0 0x2b09 3 0 2 txmarg_sel 0 2 deemph_sel 3 4 tx_margin_en 5 5 mmDC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE1 0 0x2b0a 12 0 2 twosym_en 1 2 link_speed 3 4 gang_mode 5 7 max_linkrate 8 9 pcs_freq 10 11 pcs_clken 12 12 pcs_clkdone 13 13 pll1_always_on 14 14 rdclk_div2_en 15 15 tx_boost_adj 16 19 tx_boost_en 20 20 tx_binary_ron_code_offset 22 23 mmDC_COMBOPHYTXREGS2_TX_DISP_RFU0_LANE1 0 0x2b0b 1 0 2 rfu_value0 0 31 mmDC_COMBOPHYTXREGS2_TX_DISP_RFU1_LANE1 0 0x2b0c 1 0 2 rfu_value1 0 31 mmDC_COMBOPHYTXREGS2_TX_DISP_RFU2_LANE1 0 0x2b0d 1 0 2 rfu_value2 0 31 mmDC_COMBOPHYTXREGS2_TX_DISP_RFU3_LANE1 0 0x2b0e 1 0 2 rfu_value3 0 31 mmDC_COMBOPHYTXREGS2_TX_DISP_RFU4_LANE1 0 0x2b0f 1 0 2 rfu_value4 0 31 mmDC_COMBOPHYTXREGS2_TX_DISP_RFU5_LANE1 0 0x2b10 1 0 2 rfu_value5 0 31 mmDC_COMBOPHYTXREGS2_TX_DISP_RFU6_LANE1 0 0x2b11 1 0 2 rfu_value6 0 31 mmDC_COMBOPHYTXREGS2_TX_DISP_RFU7_LANE1 0 0x2b12 1 0 2 rfu_value7 0 31 mmDC_COMBOPHYTXREGS2_TX_DISP_RFU8_LANE1 0 0x2b13 1 0 2 rfu_value8 0 31 mmDC_COMBOPHYTXREGS2_TX_DISP_RFU9_LANE1 0 0x2b14 1 0 2 rfu_value9 0 31 mmDC_COMBOPHYTXREGS2_TX_DISP_RFU10_LANE1 0 0x2b15 1 0 2 rfu_value10 0 31 mmDC_COMBOPHYTXREGS2_TX_DISP_RFU11_LANE1 0 0x2b16 1 0 2 rfu_value11 0 31 mmDC_COMBOPHYTXREGS2_TX_DISP_RFU12_LANE1 0 0x2b17 1 0 2 rfu_value12 0 31 mmDC_COMBOPHYTXREGS2_CMD_BUS_TX_CONTROL_LANE2 0 0x2b18 3 0 2 tx_pwr 0 2 tx_pg_en 3 4 tx_rdy 8 8 mmDC_COMBOPHYTXREGS2_MARGIN_DEEMPH_LANE2 0 0x2b19 3 0 2 txmarg_sel 0 2 deemph_sel 3 4 tx_margin_en 5 5 mmDC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE2 0 0x2b1a 12 0 2 twosym_en 1 2 link_speed 3 4 gang_mode 5 7 max_linkrate 8 9 pcs_freq 10 11 pcs_clken 12 12 pcs_clkdone 13 13 pll1_always_on 14 14 rdclk_div2_en 15 15 tx_boost_adj 16 19 tx_boost_en 20 20 tx_binary_ron_code_offset 22 23 mmDC_COMBOPHYTXREGS2_TX_DISP_RFU0_LANE2 0 0x2b1b 1 0 2 rfu_value0 0 31 mmDC_COMBOPHYTXREGS2_TX_DISP_RFU1_LANE2 0 0x2b1c 1 0 2 rfu_value1 0 31 mmDC_COMBOPHYTXREGS2_TX_DISP_RFU2_LANE2 0 0x2b1d 1 0 2 rfu_value2 0 31 mmDC_COMBOPHYTXREGS2_TX_DISP_RFU3_LANE2 0 0x2b1e 1 0 2 rfu_value3 0 31 mmDC_COMBOPHYTXREGS2_TX_DISP_RFU4_LANE2 0 0x2b1f 1 0 2 rfu_value4 0 31 mmDC_COMBOPHYTXREGS2_TX_DISP_RFU5_LANE2 0 0x2b20 1 0 2 rfu_value5 0 31 mmDC_COMBOPHYTXREGS2_TX_DISP_RFU6_LANE2 0 0x2b21 1 0 2 rfu_value6 0 31 mmDC_COMBOPHYTXREGS2_TX_DISP_RFU7_LANE2 0 0x2b22 1 0 2 rfu_value7 0 31 mmDC_COMBOPHYTXREGS2_TX_DISP_RFU8_LANE2 0 0x2b23 1 0 2 rfu_value8 0 31 mmDC_COMBOPHYTXREGS2_TX_DISP_RFU9_LANE2 0 0x2b24 1 0 2 rfu_value9 0 31 mmDC_COMBOPHYTXREGS2_TX_DISP_RFU10_LANE2 0 0x2b25 1 0 2 rfu_value10 0 31 mmDC_COMBOPHYTXREGS2_TX_DISP_RFU11_LANE2 0 0x2b26 1 0 2 rfu_value11 0 31 mmDC_COMBOPHYTXREGS2_TX_DISP_RFU12_LANE2 0 0x2b27 1 0 2 rfu_value12 0 31 mmDC_COMBOPHYTXREGS2_CMD_BUS_TX_CONTROL_LANE3 0 0x2b28 3 0 2 tx_pwr 0 2 tx_pg_en 3 4 tx_rdy 8 8 mmDC_COMBOPHYTXREGS2_MARGIN_DEEMPH_LANE3 0 0x2b29 3 0 2 txmarg_sel 0 2 deemph_sel 3 4 tx_margin_en 5 5 mmDC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE3 0 0x2b2a 12 0 2 twosym_en 1 2 link_speed 3 4 gang_mode 5 7 max_linkrate 8 9 pcs_freq 10 11 pcs_clken 12 12 pcs_clkdone 13 13 pll1_always_on 14 14 rdclk_div2_en 15 15 tx_boost_adj 16 19 tx_boost_en 20 20 tx_binary_ron_code_offset 22 23 mmDC_COMBOPHYTXREGS2_TX_DISP_RFU0_LANE3 0 0x2b2b 1 0 2 rfu_value0 0 31 mmDC_COMBOPHYTXREGS2_TX_DISP_RFU1_LANE3 0 0x2b2c 1 0 2 rfu_value1 0 31 mmDC_COMBOPHYTXREGS2_TX_DISP_RFU2_LANE3 0 0x2b2d 1 0 2 rfu_value2 0 31 mmDC_COMBOPHYTXREGS2_TX_DISP_RFU3_LANE3 0 0x2b2e 1 0 2 rfu_value3 0 31 mmDC_COMBOPHYTXREGS2_TX_DISP_RFU4_LANE3 0 0x2b2f 1 0 2 rfu_value4 0 31 mmDC_COMBOPHYTXREGS2_TX_DISP_RFU5_LANE3 0 0x2b30 1 0 2 rfu_value5 0 31 mmDC_COMBOPHYTXREGS2_TX_DISP_RFU6_LANE3 0 0x2b31 1 0 2 rfu_value6 0 31 mmDC_COMBOPHYTXREGS2_TX_DISP_RFU7_LANE3 0 0x2b32 1 0 2 rfu_value7 0 31 mmDC_COMBOPHYTXREGS2_TX_DISP_RFU8_LANE3 0 0x2b33 1 0 2 rfu_value8 0 31 mmDC_COMBOPHYTXREGS2_TX_DISP_RFU9_LANE3 0 0x2b34 1 0 2 rfu_value9 0 31 mmDC_COMBOPHYTXREGS2_TX_DISP_RFU10_LANE3 0 0x2b35 1 0 2 rfu_value10 0 31 mmDC_COMBOPHYTXREGS2_TX_DISP_RFU11_LANE3 0 0x2b36 1 0 2 rfu_value11 0 31 mmDC_COMBOPHYTXREGS2_TX_DISP_RFU12_LANE3 0 0x2b37 1 0 2 rfu_value12 0 31 mmDC_COMBOPHYPLLREGS2_FREQ_CTRL0 0 0x2b38 2 0 2 fcw0_frac 0 15 fcw0_int 16 24 mmDC_COMBOPHYPLLREGS2_FREQ_CTRL1 0 0x2b39 2 0 2 fcw1_frac 0 15 fcw1_int 16 24 mmDC_COMBOPHYPLLREGS2_FREQ_CTRL2 0 0x2b3a 2 0 2 fcw_denom 0 15 fcw_slew_frac 16 31 mmDC_COMBOPHYPLLREGS2_FREQ_CTRL3 0 0x2b3b 8 0 2 refclk_div 0 1 vco_pre_div 3 4 fracn_en 6 6 ssc_en 8 8 fcw_sel 10 10 freq_jump_en 12 12 tdc_resolution 16 23 dpll_cfg_1 24 31 mmDC_COMBOPHYPLLREGS2_BW_CTRL_COARSE 0 0x2b3c 6 0 2 gi_coarse_mant 0 1 gi_coarse_exp 2 5 gp_coarse_mant 7 10 gp_coarse_exp 12 15 nctl_coarse_res 17 22 nctl_coarse_frac_res 24 25 mmDC_COMBOPHYPLLREGS2_BW_CTRL_FINE 0 0x2b3d 1 0 2 dpll_cfg_3 0 9 mmDC_COMBOPHYPLLREGS2_CAL_CTRL 0 0x2b3e 9 0 2 bypass_freq_lock 0 0 tdc_cal_en 1 1 tdc_cal_ctrl 3 8 meas_win_sel 9 10 kdco_cal_dis 11 11 kdco_ratio 13 20 kdco_incr_cal_dis 22 22 nctl_adj_dis 23 23 refclk_rate 24 31 mmDC_COMBOPHYPLLREGS2_LOOP_CTRL 0 0x2b3f 10 0 2 fbdiv_mask_en 0 0 fb_slip_dis 2 2 clk_tdc_sel 4 5 clk_nctl_sel 7 8 sig_del_patt_sel 10 10 nctl_sig_del_dis 12 12 fbclk_track_refclk 14 14 prbs_en 16 16 tdc_clk_gate_en 18 18 phase_offset 20 26 mmDC_COMBOPHYPLLREGS2_VREG_CFG 0 0x2b41 14 0 2 bleeder_ac 0 0 bleeder_en 1 1 is_1p2 2 2 reg_obs_sel 3 4 reg_on_mode 5 6 rlad_tap_sel 7 10 reg_off_hi 11 11 reg_off_lo 12 12 scale_driver 13 14 sel_bump 15 15 sel_rladder_x 16 16 short_rc_filt_x 17 17 vref_pwr_on 18 18 dpll_cfg_2 20 27 mmDC_COMBOPHYPLLREGS2_OBSERVE0 0 0x2b42 5 0 2 lock_det_tdc_steps 0 4 clear_sticky_lock 6 6 lock_det_dis 8 8 dco_cfg 10 17 anaobs_sel 21 23 mmDC_COMBOPHYPLLREGS2_OBSERVE1 0 0x2b43 5 0 2 digobs_sel 0 3 digobs_trig_sel 5 8 digobs_div 10 11 digobs_trig_div 13 14 lock_timer 16 29 mmDC_COMBOPHYPLLREGS2_DFT_OUT 0 0x2b44 1 0 2 dft_data 0 31 mmDC_COMBOPHYPLLREGS2_PLL_WRAP_CNTRL1 0 0x2b76 1 0 2 wrap_cfg_sel_clk 0 1 mmDC_COMBOPHYPLLREGS2_PLL_WRAP_CNTRL 0 0x2b77 11 0 2 wrap_cfg_pll_freq_programming_ovveride 0 0 wrap_cfg_pll_pwr_state_ovrride 1 1 wrap_cfg_pll_pwr_state 2 3 wrap_cfg_tx_pdiv_val 5 7 wrap_cfg_tx_pixdiv_val 8 8 wrap_cfg_cml_cmos_sel 10 10 wrap_cfg_pll_rdy 13 13 wrap_cfg_pll_update 14 14 wrap_cfg_ref_values_chg 15 15 wrap_cfg_clk_gate_w_rdy 16 16 wrap_cfg_pll_dsm_sel 17 19 mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED0 0 0x2bb0 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED1 0 0x2bb1 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED2 0 0x2bb2 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED3 0 0x2bb3 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED4 0 0x2bb4 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED5 0 0x2bb5 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED6 0 0x2bb6 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED7 0 0x2bb7 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED8 0 0x2bb8 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED9 0 0x2bb9 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED10 0 0x2bba 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED11 0 0x2bbb 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED12 0 0x2bbc 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED13 0 0x2bbd 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED14 0 0x2bbe 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED15 0 0x2bbf 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED16 0 0x2bc0 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED17 0 0x2bc1 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED18 0 0x2bc2 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED19 0 0x2bc3 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED20 0 0x2bc4 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED21 0 0x2bc5 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED22 0 0x2bc6 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED23 0 0x2bc7 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED24 0 0x2bc8 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED25 0 0x2bc9 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED26 0 0x2bca 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED27 0 0x2bcb 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED28 0 0x2bcc 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED29 0 0x2bcd 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED30 0 0x2bce 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED31 0 0x2bcf 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED32 0 0x2bd0 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED33 0 0x2bd1 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED34 0 0x2bd2 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED35 0 0x2bd3 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED36 0 0x2bd4 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED37 0 0x2bd5 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED38 0 0x2bd6 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED39 0 0x2bd7 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED40 0 0x2bd8 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED41 0 0x2bd9 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED42 0 0x2bda 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED43 0 0x2bdb 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED44 0 0x2bdc 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED45 0 0x2bdd 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED46 0 0x2bde 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED47 0 0x2bdf 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED48 0 0x2be0 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED49 0 0x2be1 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED50 0 0x2be2 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED51 0 0x2be3 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED52 0 0x2be4 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED53 0 0x2be5 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED54 0 0x2be6 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED55 0 0x2be7 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED56 0 0x2be8 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED57 0 0x2be9 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED58 0 0x2bea 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED59 0 0x2beb 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED60 0 0x2bec 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED61 0 0x2bed 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED62 0 0x2bee 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED63 0 0x2bef 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED64 0 0x2bf0 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED65 0 0x2bf1 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED66 0 0x2bf2 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED67 0 0x2bf3 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED68 0 0x2bf4 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED69 0 0x2bf5 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED70 0 0x2bf6 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED71 0 0x2bf7 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED72 0 0x2bf8 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED73 0 0x2bf9 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED74 0 0x2bfa 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED75 0 0x2bfb 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED76 0 0x2bfc 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED77 0 0x2bfd 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED78 0 0x2bfe 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED79 0 0x2bff 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED80 0 0x2c00 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED81 0 0x2c01 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED82 0 0x2c02 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED83 0 0x2c03 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED84 0 0x2c04 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED85 0 0x2c05 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED86 0 0x2c06 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED87 0 0x2c07 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED88 0 0x2c08 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED89 0 0x2c09 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED90 0 0x2c0a 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED91 0 0x2c0b 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED92 0 0x2c0c 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED93 0 0x2c0d 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED94 0 0x2c0e 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED95 0 0x2c0f 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED96 0 0x2c10 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED97 0 0x2c11 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED98 0 0x2c12 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED99 0 0x2c13 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED100 0 0x2c14 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED101 0 0x2c15 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED102 0 0x2c16 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED103 0 0x2c17 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED104 0 0x2c18 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED105 0 0x2c19 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED106 0 0x2c1a 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED107 0 0x2c1b 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED108 0 0x2c1c 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED109 0 0x2c1d 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED110 0 0x2c1e 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED111 0 0x2c1f 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED112 0 0x2c20 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED113 0 0x2c21 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED114 0 0x2c22 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED115 0 0x2c23 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED116 0 0x2c24 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED117 0 0x2c25 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED118 0 0x2c26 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED119 0 0x2c27 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED120 0 0x2c28 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED121 0 0x2c29 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED122 0 0x2c2a 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED123 0 0x2c2b 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED124 0 0x2c2c 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED125 0 0x2c2d 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED126 0 0x2c2e 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED127 0 0x2c2f 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED128 0 0x2c30 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED129 0 0x2c31 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED130 0 0x2c32 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED131 0 0x2c33 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED132 0 0x2c34 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED133 0 0x2c35 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED134 0 0x2c36 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED135 0 0x2c37 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED136 0 0x2c38 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED137 0 0x2c39 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED138 0 0x2c3a 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED139 0 0x2c3b 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED140 0 0x2c3c 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED141 0 0x2c3d 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED142 0 0x2c3e 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED143 0 0x2c3f 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED144 0 0x2c40 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED145 0 0x2c41 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED146 0 0x2c42 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED147 0 0x2c43 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED148 0 0x2c44 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED149 0 0x2c45 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED150 0 0x2c46 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED151 0 0x2c47 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED152 0 0x2c48 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED153 0 0x2c49 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED154 0 0x2c4a 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED155 0 0x2c4b 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED156 0 0x2c4c 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED157 0 0x2c4d 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED158 0 0x2c4e 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED159 0 0x2c4f 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 mmDC_COMBOPHYCMREGS3_COMMON_FUSE1 0 0x2bb0 11 0 2 fuse1_valid 0 0 fuse1_unpopulated0 1 2 fuse1_ron_override_val 3 8 fuse1_unpopulated1 9 9 fuse1_ron_ctl 10 11 fuse1_unpopulated2 12 12 fuse1_rtt_override_val 13 18 fuse1_unpopulated3 19 19 fuse1_rtt_ctl 20 21 fuse1_refresh_cal_en 22 22 fuse1_spare 23 31 mmDC_COMBOPHYCMREGS3_COMMON_FUSE2 0 0x2bb1 4 0 2 fuse2_valid 0 0 fuse2_unpopulated 1 8 fuse2_tx_fifo_ptr 9 13 fuse2_spare 14 31 mmDC_COMBOPHYCMREGS3_COMMON_FUSE3 0 0x2bb2 11 0 2 fuse3_valid 0 0 fuse3_unpopulated 1 9 fuse3_ei_det_thresh_sel 10 12 cdr_dac_safeval_sel 13 15 cdr_freq_lock_timer 16 17 cdr_cal_dac_stpsz 18 19 cdr_byp_init_val 20 20 cdr_icostart_sel 21 21 cdr_bbweight 22 25 cdr_cur_mirr_ratio 26 28 fuse3_spare 29 31 mmDC_COMBOPHYCMREGS3_COMMON_MAR_DEEMPH_NOM 0 0x2bb3 4 0 2 tx_margin_nom 0 7 deemph_gen1_nom 8 15 deemph35_gen2_nom 16 23 deemph60_gen2_nom 24 31 mmDC_COMBOPHYCMREGS3_COMMON_LANE_PWRMGMT 0 0x2bb4 3 0 2 pgdelay 0 3 pgmask 4 9 vprot_en 11 11 mmDC_COMBOPHYCMREGS3_COMMON_TXCNTRL 0 0x2bb5 5 0 2 rdptr_rst_val_gen3 0 4 clkgate_dis 5 5 slew_rate_ctl_gen1 6 8 slew_rate_ctl_gen2 9 11 slew_rate_ctl_gen3 12 14 mmDC_COMBOPHYCMREGS3_COMMON_TMDP 0 0x2bb6 1 0 2 tmdp_spare 0 31 mmDC_COMBOPHYCMREGS3_COMMON_LANE_RESETS 0 0x2bb7 8 0 2 lane_0_reset_l 0 0 lane_1_reset_l 1 1 lane_2_reset_l 2 2 lane_3_reset_l 3 3 lane_4_reset_l 4 4 lane_5_reset_l 5 5 lane_6_reset_l 6 6 lane_7_reset_l 7 7 mmDC_COMBOPHYCMREGS3_COMMON_ZCALCODE_CTRL 0 0x2bb8 4 0 2 zcalcode_override 0 0 tx_binary_code_override_val 1 5 rx_therm_code_override_val 6 20 tx_driver_fifty_ohms 21 21 mmDC_COMBOPHYCMREGS3_COMMON_DISP_RFU1 0 0x2bb9 1 0 2 rfu_value1 0 31 mmDC_COMBOPHYCMREGS3_COMMON_DISP_RFU2 0 0x2bba 1 0 2 rfu_value2 0 31 mmDC_COMBOPHYCMREGS3_COMMON_DISP_RFU3 0 0x2bbb 1 0 2 rfu_value3 0 31 mmDC_COMBOPHYCMREGS3_COMMON_DISP_RFU4 0 0x2bbc 1 0 2 rfu_value4 0 31 mmDC_COMBOPHYCMREGS3_COMMON_DISP_RFU5 0 0x2bbd 1 0 2 rfu_value5 0 31 mmDC_COMBOPHYCMREGS3_COMMON_DISP_RFU6 0 0x2bbe 1 0 2 rfu_value6 0 31 mmDC_COMBOPHYCMREGS3_COMMON_DISP_RFU7 0 0x2bbf 1 0 2 rfu_value7 0 31 mmDC_COMBOPHYTXREGS3_CMD_BUS_TX_CONTROL_LANE0 0 0x2bd0 3 0 2 tx_pwr 0 2 tx_pg_en 3 4 tx_rdy 8 8 mmDC_COMBOPHYTXREGS3_MARGIN_DEEMPH_LANE0 0 0x2bd1 3 0 2 txmarg_sel 0 2 deemph_sel 3 4 tx_margin_en 5 5 mmDC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE0 0 0x2bd2 12 0 2 twosym_en 1 2 link_speed 3 4 gang_mode 5 7 max_linkrate 8 9 pcs_freq 10 11 pcs_clken 12 12 pcs_clkdone 13 13 pll1_always_on 14 14 rdclk_div2_en 15 15 tx_boost_adj 16 19 tx_boost_en 20 20 tx_binary_ron_code_offset 22 23 mmDC_COMBOPHYTXREGS3_TX_DISP_RFU0_LANE0 0 0x2bd3 1 0 2 rfu_value0 0 31 mmDC_COMBOPHYTXREGS3_TX_DISP_RFU1_LANE0 0 0x2bd4 1 0 2 rfu_value1 0 31 mmDC_COMBOPHYTXREGS3_TX_DISP_RFU2_LANE0 0 0x2bd5 1 0 2 rfu_value2 0 31 mmDC_COMBOPHYTXREGS3_TX_DISP_RFU3_LANE0 0 0x2bd6 1 0 2 rfu_value3 0 31 mmDC_COMBOPHYTXREGS3_TX_DISP_RFU4_LANE0 0 0x2bd7 1 0 2 rfu_value4 0 31 mmDC_COMBOPHYTXREGS3_TX_DISP_RFU5_LANE0 0 0x2bd8 1 0 2 rfu_value5 0 31 mmDC_COMBOPHYTXREGS3_TX_DISP_RFU6_LANE0 0 0x2bd9 1 0 2 rfu_value6 0 31 mmDC_COMBOPHYTXREGS3_TX_DISP_RFU7_LANE0 0 0x2bda 1 0 2 rfu_value7 0 31 mmDC_COMBOPHYTXREGS3_TX_DISP_RFU8_LANE0 0 0x2bdb 1 0 2 rfu_value8 0 31 mmDC_COMBOPHYTXREGS3_TX_DISP_RFU9_LANE0 0 0x2bdc 1 0 2 rfu_value9 0 31 mmDC_COMBOPHYTXREGS3_TX_DISP_RFU10_LANE0 0 0x2bdd 1 0 2 rfu_value10 0 31 mmDC_COMBOPHYTXREGS3_TX_DISP_RFU11_LANE0 0 0x2bde 1 0 2 rfu_value11 0 31 mmDC_COMBOPHYTXREGS3_TX_DISP_RFU12_LANE0 0 0x2bdf 1 0 2 rfu_value12 0 31 mmDC_COMBOPHYTXREGS3_CMD_BUS_TX_CONTROL_LANE1 0 0x2be0 3 0 2 tx_pwr 0 2 tx_pg_en 3 4 tx_rdy 8 8 mmDC_COMBOPHYTXREGS3_MARGIN_DEEMPH_LANE1 0 0x2be1 3 0 2 txmarg_sel 0 2 deemph_sel 3 4 tx_margin_en 5 5 mmDC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE1 0 0x2be2 12 0 2 twosym_en 1 2 link_speed 3 4 gang_mode 5 7 max_linkrate 8 9 pcs_freq 10 11 pcs_clken 12 12 pcs_clkdone 13 13 pll1_always_on 14 14 rdclk_div2_en 15 15 tx_boost_adj 16 19 tx_boost_en 20 20 tx_binary_ron_code_offset 22 23 mmDC_COMBOPHYTXREGS3_TX_DISP_RFU0_LANE1 0 0x2be3 1 0 2 rfu_value0 0 31 mmDC_COMBOPHYTXREGS3_TX_DISP_RFU1_LANE1 0 0x2be4 1 0 2 rfu_value1 0 31 mmDC_COMBOPHYTXREGS3_TX_DISP_RFU2_LANE1 0 0x2be5 1 0 2 rfu_value2 0 31 mmDC_COMBOPHYTXREGS3_TX_DISP_RFU3_LANE1 0 0x2be6 1 0 2 rfu_value3 0 31 mmDC_COMBOPHYTXREGS3_TX_DISP_RFU4_LANE1 0 0x2be7 1 0 2 rfu_value4 0 31 mmDC_COMBOPHYTXREGS3_TX_DISP_RFU5_LANE1 0 0x2be8 1 0 2 rfu_value5 0 31 mmDC_COMBOPHYTXREGS3_TX_DISP_RFU6_LANE1 0 0x2be9 1 0 2 rfu_value6 0 31 mmDC_COMBOPHYTXREGS3_TX_DISP_RFU7_LANE1 0 0x2bea 1 0 2 rfu_value7 0 31 mmDC_COMBOPHYTXREGS3_TX_DISP_RFU8_LANE1 0 0x2beb 1 0 2 rfu_value8 0 31 mmDC_COMBOPHYTXREGS3_TX_DISP_RFU9_LANE1 0 0x2bec 1 0 2 rfu_value9 0 31 mmDC_COMBOPHYTXREGS3_TX_DISP_RFU10_LANE1 0 0x2bed 1 0 2 rfu_value10 0 31 mmDC_COMBOPHYTXREGS3_TX_DISP_RFU11_LANE1 0 0x2bee 1 0 2 rfu_value11 0 31 mmDC_COMBOPHYTXREGS3_TX_DISP_RFU12_LANE1 0 0x2bef 1 0 2 rfu_value12 0 31 mmDC_COMBOPHYTXREGS3_CMD_BUS_TX_CONTROL_LANE2 0 0x2bf0 3 0 2 tx_pwr 0 2 tx_pg_en 3 4 tx_rdy 8 8 mmDC_COMBOPHYTXREGS3_MARGIN_DEEMPH_LANE2 0 0x2bf1 3 0 2 txmarg_sel 0 2 deemph_sel 3 4 tx_margin_en 5 5 mmDC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE2 0 0x2bf2 12 0 2 twosym_en 1 2 link_speed 3 4 gang_mode 5 7 max_linkrate 8 9 pcs_freq 10 11 pcs_clken 12 12 pcs_clkdone 13 13 pll1_always_on 14 14 rdclk_div2_en 15 15 tx_boost_adj 16 19 tx_boost_en 20 20 tx_binary_ron_code_offset 22 23 mmDC_COMBOPHYTXREGS3_TX_DISP_RFU0_LANE2 0 0x2bf3 1 0 2 rfu_value0 0 31 mmDC_COMBOPHYTXREGS3_TX_DISP_RFU1_LANE2 0 0x2bf4 1 0 2 rfu_value1 0 31 mmDC_COMBOPHYTXREGS3_TX_DISP_RFU2_LANE2 0 0x2bf5 1 0 2 rfu_value2 0 31 mmDC_COMBOPHYTXREGS3_TX_DISP_RFU3_LANE2 0 0x2bf6 1 0 2 rfu_value3 0 31 mmDC_COMBOPHYTXREGS3_TX_DISP_RFU4_LANE2 0 0x2bf7 1 0 2 rfu_value4 0 31 mmDC_COMBOPHYTXREGS3_TX_DISP_RFU5_LANE2 0 0x2bf8 1 0 2 rfu_value5 0 31 mmDC_COMBOPHYTXREGS3_TX_DISP_RFU6_LANE2 0 0x2bf9 1 0 2 rfu_value6 0 31 mmDC_COMBOPHYTXREGS3_TX_DISP_RFU7_LANE2 0 0x2bfa 1 0 2 rfu_value7 0 31 mmDC_COMBOPHYTXREGS3_TX_DISP_RFU8_LANE2 0 0x2bfb 1 0 2 rfu_value8 0 31 mmDC_COMBOPHYTXREGS3_TX_DISP_RFU9_LANE2 0 0x2bfc 1 0 2 rfu_value9 0 31 mmDC_COMBOPHYTXREGS3_TX_DISP_RFU10_LANE2 0 0x2bfd 1 0 2 rfu_value10 0 31 mmDC_COMBOPHYTXREGS3_TX_DISP_RFU11_LANE2 0 0x2bfe 1 0 2 rfu_value11 0 31 mmDC_COMBOPHYTXREGS3_TX_DISP_RFU12_LANE2 0 0x2bff 1 0 2 rfu_value12 0 31 mmDC_COMBOPHYTXREGS3_CMD_BUS_TX_CONTROL_LANE3 0 0x2c00 3 0 2 tx_pwr 0 2 tx_pg_en 3 4 tx_rdy 8 8 mmDC_COMBOPHYTXREGS3_MARGIN_DEEMPH_LANE3 0 0x2c01 3 0 2 txmarg_sel 0 2 deemph_sel 3 4 tx_margin_en 5 5 mmDC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE3 0 0x2c02 12 0 2 twosym_en 1 2 link_speed 3 4 gang_mode 5 7 max_linkrate 8 9 pcs_freq 10 11 pcs_clken 12 12 pcs_clkdone 13 13 pll1_always_on 14 14 rdclk_div2_en 15 15 tx_boost_adj 16 19 tx_boost_en 20 20 tx_binary_ron_code_offset 22 23 mmDC_COMBOPHYTXREGS3_TX_DISP_RFU0_LANE3 0 0x2c03 1 0 2 rfu_value0 0 31 mmDC_COMBOPHYTXREGS3_TX_DISP_RFU1_LANE3 0 0x2c04 1 0 2 rfu_value1 0 31 mmDC_COMBOPHYTXREGS3_TX_DISP_RFU2_LANE3 0 0x2c05 1 0 2 rfu_value2 0 31 mmDC_COMBOPHYTXREGS3_TX_DISP_RFU3_LANE3 0 0x2c06 1 0 2 rfu_value3 0 31 mmDC_COMBOPHYTXREGS3_TX_DISP_RFU4_LANE3 0 0x2c07 1 0 2 rfu_value4 0 31 mmDC_COMBOPHYTXREGS3_TX_DISP_RFU5_LANE3 0 0x2c08 1 0 2 rfu_value5 0 31 mmDC_COMBOPHYTXREGS3_TX_DISP_RFU6_LANE3 0 0x2c09 1 0 2 rfu_value6 0 31 mmDC_COMBOPHYTXREGS3_TX_DISP_RFU7_LANE3 0 0x2c0a 1 0 2 rfu_value7 0 31 mmDC_COMBOPHYTXREGS3_TX_DISP_RFU8_LANE3 0 0x2c0b 1 0 2 rfu_value8 0 31 mmDC_COMBOPHYTXREGS3_TX_DISP_RFU9_LANE3 0 0x2c0c 1 0 2 rfu_value9 0 31 mmDC_COMBOPHYTXREGS3_TX_DISP_RFU10_LANE3 0 0x2c0d 1 0 2 rfu_value10 0 31 mmDC_COMBOPHYTXREGS3_TX_DISP_RFU11_LANE3 0 0x2c0e 1 0 2 rfu_value11 0 31 mmDC_COMBOPHYTXREGS3_TX_DISP_RFU12_LANE3 0 0x2c0f 1 0 2 rfu_value12 0 31 mmDC_COMBOPHYPLLREGS3_FREQ_CTRL0 0 0x2c10 2 0 2 fcw0_frac 0 15 fcw0_int 16 24 mmDC_COMBOPHYPLLREGS3_FREQ_CTRL1 0 0x2c11 2 0 2 fcw1_frac 0 15 fcw1_int 16 24 mmDC_COMBOPHYPLLREGS3_FREQ_CTRL2 0 0x2c12 2 0 2 fcw_denom 0 15 fcw_slew_frac 16 31 mmDC_COMBOPHYPLLREGS3_FREQ_CTRL3 0 0x2c13 8 0 2 refclk_div 0 1 vco_pre_div 3 4 fracn_en 6 6 ssc_en 8 8 fcw_sel 10 10 freq_jump_en 12 12 tdc_resolution 16 23 dpll_cfg_1 24 31 mmDC_COMBOPHYPLLREGS3_BW_CTRL_COARSE 0 0x2c14 6 0 2 gi_coarse_mant 0 1 gi_coarse_exp 2 5 gp_coarse_mant 7 10 gp_coarse_exp 12 15 nctl_coarse_res 17 22 nctl_coarse_frac_res 24 25 mmDC_COMBOPHYPLLREGS3_BW_CTRL_FINE 0 0x2c15 1 0 2 dpll_cfg_3 0 9 mmDC_COMBOPHYPLLREGS3_CAL_CTRL 0 0x2c16 9 0 2 bypass_freq_lock 0 0 tdc_cal_en 1 1 tdc_cal_ctrl 3 8 meas_win_sel 9 10 kdco_cal_dis 11 11 kdco_ratio 13 20 kdco_incr_cal_dis 22 22 nctl_adj_dis 23 23 refclk_rate 24 31 mmDC_COMBOPHYPLLREGS3_LOOP_CTRL 0 0x2c17 10 0 2 fbdiv_mask_en 0 0 fb_slip_dis 2 2 clk_tdc_sel 4 5 clk_nctl_sel 7 8 sig_del_patt_sel 10 10 nctl_sig_del_dis 12 12 fbclk_track_refclk 14 14 prbs_en 16 16 tdc_clk_gate_en 18 18 phase_offset 20 26 mmDC_COMBOPHYPLLREGS3_VREG_CFG 0 0x2c19 14 0 2 bleeder_ac 0 0 bleeder_en 1 1 is_1p2 2 2 reg_obs_sel 3 4 reg_on_mode 5 6 rlad_tap_sel 7 10 reg_off_hi 11 11 reg_off_lo 12 12 scale_driver 13 14 sel_bump 15 15 sel_rladder_x 16 16 short_rc_filt_x 17 17 vref_pwr_on 18 18 dpll_cfg_2 20 27 mmDC_COMBOPHYPLLREGS3_OBSERVE0 0 0x2c1a 5 0 2 lock_det_tdc_steps 0 4 clear_sticky_lock 6 6 lock_det_dis 8 8 dco_cfg 10 17 anaobs_sel 21 23 mmDC_COMBOPHYPLLREGS3_OBSERVE1 0 0x2c1b 5 0 2 digobs_sel 0 3 digobs_trig_sel 5 8 digobs_div 10 11 digobs_trig_div 13 14 lock_timer 16 29 mmDC_COMBOPHYPLLREGS3_DFT_OUT 0 0x2c1c 1 0 2 dft_data 0 31 mmDC_COMBOPHYPLLREGS3_PLL_WRAP_CNTRL1 0 0x2c4e 1 0 2 wrap_cfg_sel_clk 0 1 mmDC_COMBOPHYPLLREGS3_PLL_WRAP_CNTRL 0 0x2c4f 11 0 2 wrap_cfg_pll_freq_programming_ovveride 0 0 wrap_cfg_pll_pwr_state_ovrride 1 1 wrap_cfg_pll_pwr_state 2 3 wrap_cfg_tx_pdiv_val 5 7 wrap_cfg_tx_pixdiv_val 8 8 wrap_cfg_cml_cmos_sel 10 10 wrap_cfg_pll_rdy 13 13 wrap_cfg_pll_update 14 14 wrap_cfg_ref_values_chg 15 15 wrap_cfg_clk_gate_w_rdy 16 16 wrap_cfg_pll_dsm_sel 17 19 mmZCAL_MACRO_CNTL_RESERVED0 0 0x2fe8 1 0 2 ZCAL_MACRO_CNTL_RESERVED 0 31 mmZCAL_MACRO_CNTL_RESERVED1 0 0x2fe9 1 0 2 ZCAL_MACRO_CNTL_RESERVED 0 31 mmZCAL_MACRO_CNTL_RESERVED2 0 0x2fea 1 0 2 ZCAL_MACRO_CNTL_RESERVED 0 31 mmZCAL_MACRO_CNTL_RESERVED3 0 0x2feb 1 0 2 ZCAL_MACRO_CNTL_RESERVED 0 31 mmZCAL_MACRO_CNTL_RESERVED4 0 0x2fec 1 0 2 ZCAL_MACRO_CNTL_RESERVED 0 31 mmCOMP_EN_CTL 0 0x2fe8 12 0 2 comp_en 0 0 comp_en_override 2 2 comp_done 4 4 zcal_code_override 6 6 zcal_cal_rtt 7 7 zcal_base_en 8 8 zcal_ht_rtt_sel 9 9 zcal_code 10 14 zcal_ron_cal_mode 16 16 zcal_ana_dbg_sel 17 18 cfg_cml_cmos_sel 19 19 dsm_sel 20 23 mmCOMP_EN_DFX 0 0x2fe9 6 0 2 autocal_ron_code 0 4 autocal_rtt_code 5 9 pre_fused_ron_code 11 15 pre_fused_rtt_code 16 20 broadcast_ron_code 22 26 broadcast_rtt_code 27 31 mmZCAL_FUSES 0 0x2fea 7 0 2 fuse_valid 0 0 fuse_ron_override_val 3 8 fuse_ron_ctl 10 11 fuse_rtt_override_val 13 18 fuse_rtt_ctl 20 21 fuse_refresh_cal_en 22 22 fuse_spare 23 31 ixSEQ00 2 0x0 2 0 4294967295 SEQ_RST0B 0 0 SEQ_RST1B 1 1 ixSEQ01 2 0x1 5 0 4294967295 SEQ_DOT8 0 0 SEQ_SHIFT2 2 2 SEQ_PCLKBY2 3 3 SEQ_SHIFT4 4 4 SEQ_MAXBW 5 5 ixSEQ02 2 0x2 4 0 4294967295 SEQ_MAP0_EN 0 0 SEQ_MAP1_EN 1 1 SEQ_MAP2_EN 2 2 SEQ_MAP3_EN 3 3 ixSEQ03 2 0x3 6 0 4294967295 SEQ_FONT_B1 0 0 SEQ_FONT_B2 1 1 SEQ_FONT_A1 2 2 SEQ_FONT_A2 3 3 SEQ_FONT_B0 4 4 SEQ_FONT_A0 5 5 ixSEQ04 2 0x4 3 0 4294967295 SEQ_256K 1 1 SEQ_ODDEVEN 2 2 SEQ_CHAIN 3 3 ixCRT00 2 0x0 1 0 4294967295 H_TOTAL 0 7 ixCRT01 2 0x1 1 0 4294967295 H_DISP_END 0 7 ixCRT02 2 0x2 1 0 4294967295 H_BLANK_START 0 7 ixCRT03 2 0x3 3 0 4294967295 H_BLANK_END 0 4 H_DE_SKEW 5 6 CR10CR11_R_DIS_B 7 7 ixCRT04 2 0x4 1 0 4294967295 H_SYNC_START 0 7 ixCRT05 2 0x5 3 0 4294967295 H_SYNC_END 0 4 H_SYNC_SKEW 5 6 H_BLANK_END_B5 7 7 ixCRT06 2 0x6 1 0 4294967295 V_TOTAL 0 7 ixCRT07 2 0x7 8 0 4294967295 V_TOTAL_B8 0 0 V_DISP_END_B8 1 1 V_SYNC_START_B8 2 2 V_BLANK_START_B8 3 3 LINE_CMP_B8 4 4 V_TOTAL_B9 5 5 V_DISP_END_B9 6 6 V_SYNC_START_B9 7 7 ixCRT08 2 0x8 2 0 4294967295 ROW_SCAN_START 0 4 BYTE_PAN 5 6 ixCRT09 2 0x9 4 0 4294967295 MAX_ROW_SCAN 0 4 V_BLANK_START_B9 5 5 LINE_CMP_B9 6 6 DOUBLE_CHAR_HEIGHT 7 7 ixCRT0A 2 0xa 2 0 4294967295 CURSOR_START 0 4 CURSOR_DISABLE 5 5 ixCRT0B 2 0xb 2 0 4294967295 CURSOR_END 0 4 CURSOR_SKEW 5 6 ixCRT0C 2 0xc 1 0 4294967295 DISP_START 0 7 ixCRT0D 2 0xd 1 0 4294967295 DISP_START 0 7 ixCRT0E 2 0xe 1 0 4294967295 CURSOR_LOC_HI 0 7 ixCRT0F 2 0xf 1 0 4294967295 CURSOR_LOC_LO 0 7 ixCRT10 2 0x10 1 0 4294967295 V_SYNC_START 0 7 ixCRT11 2 0x11 5 0 4294967295 V_SYNC_END 0 3 V_INTR_CLR 4 4 V_INTR_EN 5 5 SEL5_REFRESH_CYC 6 6 C0T7_WR_ONLY 7 7 ixCRT12 2 0x12 1 0 4294967295 V_DISP_END 0 7 ixCRT13 2 0x13 1 0 4294967295 DISP_PITCH 0 7 ixCRT14 2 0x14 3 0 4294967295 UNDRLN_LOC 0 4 ADDR_CNT_BY4 5 5 DOUBLE_WORD 6 6 ixCRT15 2 0x15 1 0 4294967295 V_BLANK_START 0 7 ixCRT16 2 0x16 1 0 4294967295 V_BLANK_END 0 7 ixCRT17 2 0x17 7 0 4294967295 RA0_AS_A13B 0 0 RA1_AS_A14B 1 1 VCOUNT_BY2 2 2 ADDR_CNT_BY2 3 3 WRAP_A15TOA0 5 5 BYTE_MODE 6 6 CRTC_SYNC_EN 7 7 ixCRT18 2 0x18 1 0 4294967295 LINE_CMP 0 7 ixCRT1E 2 0x1e 1 0 4294967295 GRPH_DEC_RD1 1 1 ixCRT1F 2 0x1f 1 0 4294967295 GRPH_DEC_RD0 0 7 ixCRT22 2 0x22 1 0 4294967295 GRPH_LATCH_DATA 0 7 ixGRA00 2 0x0 4 0 4294967295 GRPH_SET_RESET0 0 0 GRPH_SET_RESET1 1 1 GRPH_SET_RESET2 2 2 GRPH_SET_RESET3 3 3 ixGRA01 2 0x1 4 0 4294967295 GRPH_SET_RESET_ENA0 0 0 GRPH_SET_RESET_ENA1 1 1 GRPH_SET_RESET_ENA2 2 2 GRPH_SET_RESET_ENA3 3 3 ixGRA02 2 0x2 1 0 4294967295 GRPH_CCOMP 0 3 ixGRA03 2 0x3 2 0 4294967295 GRPH_ROTATE 0 2 GRPH_FN_SEL 3 4 ixGRA04 2 0x4 1 0 4294967295 GRPH_RMAP 0 1 ixGRA05 2 0x5 5 0 4294967295 GRPH_WRITE_MODE 0 1 GRPH_READ1 3 3 CGA_ODDEVEN 4 4 GRPH_OES 5 5 GRPH_PACK 6 6 ixGRA06 2 0x6 3 0 4294967295 GRPH_GRAPHICS 0 0 GRPH_ODDEVEN 1 1 GRPH_ADRSEL 2 3 ixGRA07 2 0x7 4 0 4294967295 GRPH_XCARE0 0 0 GRPH_XCARE1 1 1 GRPH_XCARE2 2 2 GRPH_XCARE3 3 3 ixGRA08 2 0x8 1 0 4294967295 GRPH_BMSK 0 7 ixATTR00 2 0x0 1 0 4294967295 ATTR_PAL 0 5 ixATTR01 2 0x1 1 0 4294967295 ATTR_PAL 0 5 ixATTR02 2 0x2 1 0 4294967295 ATTR_PAL 0 5 ixATTR03 2 0x3 1 0 4294967295 ATTR_PAL 0 5 ixATTR04 2 0x4 1 0 4294967295 ATTR_PAL 0 5 ixATTR05 2 0x5 1 0 4294967295 ATTR_PAL 0 5 ixATTR06 2 0x6 1 0 4294967295 ATTR_PAL 0 5 ixATTR07 2 0x7 1 0 4294967295 ATTR_PAL 0 5 ixATTR08 2 0x8 1 0 4294967295 ATTR_PAL 0 5 ixATTR09 2 0x9 1 0 4294967295 ATTR_PAL 0 5 ixATTR0A 2 0xa 1 0 4294967295 ATTR_PAL 0 5 ixATTR0B 2 0xb 1 0 4294967295 ATTR_PAL 0 5 ixATTR0C 2 0xc 1 0 4294967295 ATTR_PAL 0 5 ixATTR0D 2 0xd 1 0 4294967295 ATTR_PAL 0 5 ixATTR0E 2 0xe 1 0 4294967295 ATTR_PAL 0 5 ixATTR0F 2 0xf 1 0 4294967295 ATTR_PAL 0 5 ixATTR10 2 0x10 7 0 4294967295 ATTR_GRPH_MODE 0 0 ATTR_MONO_EN 1 1 ATTR_LGRPH_EN 2 2 ATTR_BLINK_EN 3 3 ATTR_PANTOPONLY 5 5 ATTR_PCLKBY2 6 6 ATTR_CSEL_EN 7 7 ixATTR11 2 0x11 1 0 4294967295 ATTR_OVSC 0 7 ixATTR12 2 0x12 2 0 4294967295 ATTR_MAP_EN 0 3 ATTR_VSMUX 4 5 ixATTR13 2 0x13 1 0 4294967295 ATTR_PPAN 0 3 ixATTR14 2 0x14 2 0 4294967295 ATTR_CSEL1 0 1 ATTR_CSEL2 2 3 ixAZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT 2 0x2200 7 0 4294967295 NUMBER_OF_CHANNELS 0 3 BITS_PER_SAMPLE 4 6 SAMPLE_BASE_DIVISOR 8 10 SAMPLE_BASE_MULTIPLE 11 13 SAMPLE_BASE_RATE 14 14 STREAM_TYPE 15 15 STREAM_TYPE_R 15 15 ixAZALIA_F2_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID 2 0x2706 2 0 4294967295 CHANNEL_ID 0 3 STREAM_ID 4 7 ixAZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER 2 0x270d 10 0 4294967295 DIGEN 0 0 V 1 1 VCFG 2 2 PRE 3 3 COPY 4 4 NON_AUDIO 5 5 PRO 6 6 L 7 7 CC 8 14 KEEPALIVE 23 23 ixAZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_2 2 0x270e 1 0 4294967295 CC 0 6 ixAZALIA_F2_CODEC_CONVERTER_STRIPE_CONTROL 2 0x2724 2 0 4294967295 STRIPE_CONTROL 0 1 STRIPE_CAPABILITY 20 22 ixAZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3 2 0x273e 1 0 4294967295 KEEPALIVE 7 7 ixAZALIA_F2_CODEC_CONVERTER_CONTROL_RAMP_RATE 2 0x2770 1 0 4294967295 RAMP_RATE 0 7 ixAZALIA_F2_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING 2 0x2771 3 0 4294967295 PRESENTATION_TIME_EMBEDDING_ENABLE 0 0 PRESENTATION_TIME_OFFSET_CHANGED 1 1 PRESENTATION_TIME_EMBEDDING_GROUP 4 6 ixAZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 2 0x2f09 14 0 4294967295 AUDIO_CHANNEL_CAPABILITIES 0 0 INPUT_AMPLIFIER_PRESENT 1 1 OUTPUT_AMPLIFIER_PRESENT 2 2 AMPLIFIER_PARAMETER_OVERRIDE 3 3 FORMAT_OVERRIDE 4 4 STRIPE 5 5 PROCESSING_WIDGET 6 6 UNSOLICITED_RESPONSE_CAPABILITY 7 7 CONNECTION_LIST 8 8 DIGITAL 9 9 POWER_CONTROL 10 10 LR_SWAP 11 11 AUDIO_WIDGET_CAPABILITIES_DELAY 16 19 TYPE 20 23 ixAZALIA_F2_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 2 0x2f0a 2 0 4294967295 AUDIO_RATE_CAPABILITIES 0 11 AUDIO_BIT_CAPABILITIES 16 20 ixAZALIA_F2_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS 2 0x2f0b 1 0 4294967295 STREAM_FORMATS 0 31 ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONNECTION_LIST_ENTRY 2 0x3702 1 0 4294967295 CONNECTION_LIST_ENTRY 0 31 ixAZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL 2 0x3707 1 0 4294967295 OUT_ENABLE 6 6 ixAZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE 2 0x3708 2 0 4294967295 TAG 0 5 ENABLE 7 7 ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE 2 0x3709 2 0 4294967295 IMPEDANCE_SENSE 0 30 PRESENCE_DETECT 31 31 ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 2 0x371c 8 0 4294967295 SEQUENCE 0 3 DEFAULT_ASSOCIATION 4 7 MISC 8 11 COLOR 12 15 CONNECTION_TYPE 16 19 DEFAULT_DEVICE 20 23 LOCATION 24 29 PORT_CONNECTIVITY 30 31 ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2 2 0x371d 2 0 4294967295 MISC 0 3 COLOR 4 7 ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3 2 0x371e 2 0 4294967295 CONNECTION_TYPE 0 3 DEFAULT_DEVICE 4 7 ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4 2 0x371f 2 0 4294967295 LOCATION 0 5 PORT_CONNECTIVITY 6 7 ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION 2 0x3770 4 0 4294967295 SPEAKER_ALLOCATION 0 6 HDMI_CONNECTION 8 8 DP_CONNECTION 9 9 EXTRA_CONNECTION_INFO 10 15 ixAZALIA_F2_CODEC_PIN_CONTROL_CHANNEL_ALLOCATION 2 0x3771 1 0 4294967295 CHANNEL_ALLOCATION 0 7 ixAZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO 2 0x3772 3 0 4294967295 LFE_PLAYBACK_LEVEL 0 1 LEVEL_SHIFT 3 6 DOWN_MIX_INHIBIT 7 7 ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR 2 0x3776 5 0 4294967295 MAX_CHANNELS 0 2 FORMAT_CODE 3 6 SUPPORTED_FREQUENCIES 8 15 DESCRIPTOR_BYTE_2 16 23 SUPPORTED_FREQUENCIES_STEREO 24 31 ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_DATA 2 0x3776 1 0 4294967295 DESCRIPTOR 0 31 ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE 2 0x3777 3 0 4294967295 MULTICHANNEL01_ENABLE 0 0 MULTICHANNEL01_MUTE 1 1 MULTICHANNEL01_CHANNEL_ID 4 7 ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE 2 0x3778 3 0 4294967295 MULTICHANNEL23_ENABLE 0 0 MULTICHANNEL23_MUTE 1 1 MULTICHANNEL23_CHANNEL_ID 4 7 ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE 2 0x3779 3 0 4294967295 MULTICHANNEL45_ENABLE 0 0 MULTICHANNEL45_MUTE 1 1 MULTICHANNEL45_CHANNEL_ID 4 7 ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE 2 0x377a 3 0 4294967295 MULTICHANNEL67_ENABLE 0 0 MULTICHANNEL67_MUTE 1 1 MULTICHANNEL67_CHANNEL_ID 4 7 ixAZALIA_F2_CODEC_PIN_CONTROL_LIPSYNC 2 0x377b 2 0 4294967295 VIDEO_LIPSYNC 0 7 AUDIO_LIPSYNC 8 15 ixAZALIA_F2_CODEC_PIN_CONTROL_HBR 2 0x377c 2 0 4294967295 HBR_CAPABLE 0 0 HBR_ENABLE 4 4 ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_INDEX 2 0x3780 1 0 4294967295 SINK_INFO_INDEX 0 7 ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_DATA 2 0x3781 1 0 4294967295 SINK_DATA 0 31 ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE 2 0x3785 3 0 4294967295 MULTICHANNEL1_ENABLE 0 0 MULTICHANNEL1_MUTE 1 1 MULTICHANNEL1_CHANNEL_ID 4 7 ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE 2 0x3786 3 0 4294967295 MULTICHANNEL3_ENABLE 0 0 MULTICHANNEL3_MUTE 1 1 MULTICHANNEL3_CHANNEL_ID 4 7 ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE 2 0x3787 3 0 4294967295 MULTICHANNEL5_ENABLE 0 0 MULTICHANNEL5_MUTE 1 1 MULTICHANNEL5_CHANNEL_ID 4 7 ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE 2 0x3788 3 0 4294967295 MULTICHANNEL7_ENABLE 0 0 MULTICHANNEL7_MUTE 1 1 MULTICHANNEL7_CHANNEL_ID 4 7 ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE 2 0x3789 1 0 4294967295 MULTICHANNEL_MODE 0 0 ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_0 2 0x378a 2 0 4294967295 IEC_60958_CS_MODE 0 1 IEC_60958_CS_SOURCE_NUMBER 2 5 ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1 2 0x378b 4 0 4294967295 IEC_60958_CS_CLOCK_ACCURACY 0 1 IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN 2 2 IEC_60958_CS_WORD_LENGTH 3 6 IEC_60958_CS_WORD_LENGTH_OVRRD_EN 7 7 ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_2 2 0x378c 2 0 4294967295 IEC_60958_CS_SAMPLING_FREQUENCY 0 5 IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN 6 6 ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_3 2 0x378d 2 0 4294967295 IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY 0 3 IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN 4 4 ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4 2 0x378e 4 0 4294967295 IEC_60958_CS_SAMPLING_FREQUENCY_COEFF 0 3 IEC_60958_CS_MPEG_SURROUND_INFO 4 4 IEC_60958_CS_CGMS_A 5 6 IEC_60958_CS_CGMS_A_VALID 7 7 ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_5 2 0x378f 2 0 4294967295 IEC_60958_CS_CHANNEL_NUMBER_L 0 3 IEC_60958_CS_CHANNEL_NUMBER_R 4 7 ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_6 2 0x3790 2 0 4294967295 IEC_60958_CS_CHANNEL_NUMBER_2 0 3 IEC_60958_CS_CHANNEL_NUMBER_3 4 7 ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_7 2 0x3791 2 0 4294967295 IEC_60958_CS_CHANNEL_NUMBER_4 0 3 IEC_60958_CS_CHANNEL_NUMBER_5 4 7 ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_8 2 0x3792 2 0 4294967295 IEC_60958_CS_CHANNEL_NUMBER_6 0 3 IEC_60958_CS_CHANNEL_NUMBER_7 4 7 ixAZALIA_F2_CODEC_PIN_ASSOCIATION_INFO 2 0x3793 1 0 4294967295 ASSOCIATION_INFO 0 31 ixAZALIA_F2_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS 2 0x3797 1 0 4294967295 OUTPUT_ACTIVE 0 0 ixAZALIA_F2_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 2 0x3798 2 0 4294967295 LPIB_SNAPSHOT_LOCK 0 0 CYCLIC_BUFFER_WRAP_COUNT 8 15 ixAZALIA_F2_CODEC_PIN_CONTROL_LPIB 2 0x3799 1 0 4294967295 LPIB 0 31 ixAZALIA_F2_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 2 0x379a 1 0 4294967295 LPIB_TIMER_SNAPSHOT 0 31 ixAZALIA_F2_CODEC_PIN_CONTROL_CODING_TYPE 2 0x379b 1 0 4294967295 CODING_TYPE 0 7 ixAZALIA_F2_CODEC_PIN_CONTROL_FORMAT_CHANGED 2 0x379c 4 0 4294967295 FORMAT_CHANGED 0 0 FORMAT_CHANGED_ACK_UR_ENABLE 1 1 FORMAT_CHANGE_REASON 8 15 FORMAT_CHANGE_RESPONSE 16 23 ixAZALIA_F2_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION 2 0x379d 1 0 4294967295 WIRELESS_DISPLAY_IDENTIFICATION 0 1 ixAZALIA_F2_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE 2 0x379e 2 0 4294967295 REMOTE_KEEP_ALIVE_ENABLE 0 0 REMOTE_KEEP_ALIVE_CAPABILITY 4 4 ixAZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 2 0x3f09 13 0 4294967295 AUDIO_CHANNEL_CAPABILITIES 0 0 INPUT_AMPLIFIER_PRESENT 1 1 OUTPUT_AMPLIFIER_PRESENT 2 2 AMPLIFIER_PARAMETER_OVERRIDE 3 3 STRIPE 5 5 PROCESSING_WIDGET 6 6 UNSOLICITED_RESPONSE_CAPABILITY 7 7 CONNECTION_LIST 8 8 DIGITAL 9 9 POWER_CONTROL 10 10 LR_SWAP 11 11 AUDIO_WIDGET_CAPABILITIES_DELAY 16 19 TYPE 20 23 ixAZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES 2 0x3f0c 11 0 4294967295 IMPEDANCE_SENSE_CAPABLE 0 0 TRIGGER_REQUIRED 1 1 JACK_DETECTION_CAPABILITY 2 2 HEADPHONE_DRIVE_CAPABLE 3 3 OUTPUT_CAPABLE 4 4 INPUT_CAPABLE 5 5 BALANCED_I_O_PINS 6 6 HDMI 7 7 VREF_CONTROL 8 15 EAPD_CAPABLE 16 16 DP 24 24 ixAZALIA_F2_CODEC_PIN_PARAMETER_CONNECTION_LIST_LENGTH 2 0x3f0e 1 0 4294967295 CONNECTION_LIST_LENGTH 0 31 ixAUDIO_DESCRIPTOR0 2 0x1 4 0 4294967295 MAX_CHANNELS 0 2 SUPPORTED_FREQUENCIES 8 15 DESCRIPTOR_BYTE_2 16 23 SUPPORTED_FREQUENCIES_STEREO 24 31 ixAUDIO_DESCRIPTOR1 2 0x2 4 0 4294967295 MAX_CHANNELS 0 2 SUPPORTED_FREQUENCIES 8 15 DESCRIPTOR_BYTE_2 16 23 SUPPORTED_FREQUENCIES_STEREO 24 31 ixAUDIO_DESCRIPTOR2 2 0x3 4 0 4294967295 MAX_CHANNELS 0 2 SUPPORTED_FREQUENCIES 8 15 DESCRIPTOR_BYTE_2 16 23 SUPPORTED_FREQUENCIES_STEREO 24 31 ixAUDIO_DESCRIPTOR3 2 0x4 4 0 4294967295 MAX_CHANNELS 0 2 SUPPORTED_FREQUENCIES 8 15 DESCRIPTOR_BYTE_2 16 23 SUPPORTED_FREQUENCIES_STEREO 24 31 ixAUDIO_DESCRIPTOR4 2 0x5 4 0 4294967295 MAX_CHANNELS 0 2 SUPPORTED_FREQUENCIES 8 15 DESCRIPTOR_BYTE_2 16 23 SUPPORTED_FREQUENCIES_STEREO 24 31 ixAUDIO_DESCRIPTOR5 2 0x6 4 0 4294967295 MAX_CHANNELS 0 2 SUPPORTED_FREQUENCIES 8 15 DESCRIPTOR_BYTE_2 16 23 SUPPORTED_FREQUENCIES_STEREO 24 31 ixAUDIO_DESCRIPTOR6 2 0x7 4 0 4294967295 MAX_CHANNELS 0 2 SUPPORTED_FREQUENCIES 8 15 DESCRIPTOR_BYTE_2 16 23 SUPPORTED_FREQUENCIES_STEREO 24 31 ixAUDIO_DESCRIPTOR7 2 0x8 4 0 4294967295 MAX_CHANNELS 0 2 SUPPORTED_FREQUENCIES 8 15 DESCRIPTOR_BYTE_2 16 23 SUPPORTED_FREQUENCIES_STEREO 24 31 ixAUDIO_DESCRIPTOR8 2 0x9 4 0 4294967295 MAX_CHANNELS 0 2 SUPPORTED_FREQUENCIES 8 15 DESCRIPTOR_BYTE_2 16 23 SUPPORTED_FREQUENCIES_STEREO 24 31 ixAUDIO_DESCRIPTOR9 2 0xa 4 0 4294967295 MAX_CHANNELS 0 2 SUPPORTED_FREQUENCIES 8 15 DESCRIPTOR_BYTE_2 16 23 SUPPORTED_FREQUENCIES_STEREO 24 31 ixAUDIO_DESCRIPTOR10 2 0xb 4 0 4294967295 MAX_CHANNELS 0 2 SUPPORTED_FREQUENCIES 8 15 DESCRIPTOR_BYTE_2 16 23 SUPPORTED_FREQUENCIES_STEREO 24 31 ixAUDIO_DESCRIPTOR11 2 0xc 4 0 4294967295 MAX_CHANNELS 0 2 SUPPORTED_FREQUENCIES 8 15 DESCRIPTOR_BYTE_2 16 23 SUPPORTED_FREQUENCIES_STEREO 24 31 ixAUDIO_DESCRIPTOR12 2 0xd 4 0 4294967295 MAX_CHANNELS 0 2 SUPPORTED_FREQUENCIES 8 15 DESCRIPTOR_BYTE_2 16 23 SUPPORTED_FREQUENCIES_STEREO 24 31 ixAUDIO_DESCRIPTOR13 2 0xe 4 0 4294967295 MAX_CHANNELS 0 2 SUPPORTED_FREQUENCIES 8 15 DESCRIPTOR_BYTE_2 16 23 SUPPORTED_FREQUENCIES_STEREO 24 31 ixAZALIA_F2_CODEC_PIN_CONTROL_MANUFACTURER_ID 2 0x0 1 0 4294967295 MANUFACTURER_ID 0 15 ixAZALIA_F2_CODEC_PIN_CONTROL_PRODUCT_ID 2 0x1 1 0 4294967295 PRODUCT_ID 0 15 ixAZALIA_F2_CODEC_PIN_CONTROL_SINK_DESCRIPTION_LEN 2 0x2 1 0 4294967295 SINK_DESCRIPTION_LEN 0 7 ixAZALIA_F2_CODEC_PIN_CONTROL_PORTID0 2 0x3 1 0 4294967295 PORTID 0 31 ixAZALIA_F2_CODEC_PIN_CONTROL_PORTID1 2 0x4 1 0 4294967295 PORTID 0 31 ixSINK_DESCRIPTION0 2 0x5 1 0 4294967295 DESCRIPTION 0 7 ixSINK_DESCRIPTION1 2 0x6 1 0 4294967295 DESCRIPTION 0 7 ixSINK_DESCRIPTION2 2 0x7 1 0 4294967295 DESCRIPTION 0 7 ixSINK_DESCRIPTION3 2 0x8 1 0 4294967295 DESCRIPTION 0 7 ixSINK_DESCRIPTION4 2 0x9 1 0 4294967295 DESCRIPTION 0 7 ixSINK_DESCRIPTION5 2 0xa 1 0 4294967295 DESCRIPTION 0 7 ixSINK_DESCRIPTION6 2 0xb 1 0 4294967295 DESCRIPTION 0 7 ixSINK_DESCRIPTION7 2 0xc 1 0 4294967295 DESCRIPTION 0 7 ixSINK_DESCRIPTION8 2 0xd 1 0 4294967295 DESCRIPTION 0 7 ixSINK_DESCRIPTION9 2 0xe 1 0 4294967295 DESCRIPTION 0 7 ixSINK_DESCRIPTION10 2 0xf 1 0 4294967295 DESCRIPTION 0 7 ixSINK_DESCRIPTION11 2 0x10 1 0 4294967295 DESCRIPTION 0 7 ixSINK_DESCRIPTION12 2 0x11 1 0 4294967295 DESCRIPTION 0 7 ixSINK_DESCRIPTION13 2 0x12 1 0 4294967295 DESCRIPTION 0 7 ixSINK_DESCRIPTION14 2 0x13 1 0 4294967295 DESCRIPTION 0 7 ixSINK_DESCRIPTION15 2 0x14 1 0 4294967295 DESCRIPTION 0 7 ixSINK_DESCRIPTION16 2 0x15 1 0 4294967295 DESCRIPTION 0 7 ixSINK_DESCRIPTION17 2 0x16 1 0 4294967295 DESCRIPTION 0 7 ixAZALIA_INPUT_CRC0_CHANNEL0 2 0x0 1 0 4294967295 INPUT_CRC_CHANNEL0 0 31 ixAZALIA_INPUT_CRC0_CHANNEL1 2 0x1 1 0 4294967295 INPUT_CRC_CHANNEL1 0 31 ixAZALIA_INPUT_CRC0_CHANNEL2 2 0x2 1 0 4294967295 INPUT_CRC_CHANNEL2 0 31 ixAZALIA_INPUT_CRC0_CHANNEL3 2 0x3 1 0 4294967295 INPUT_CRC_CHANNEL3 0 31 ixAZALIA_INPUT_CRC0_CHANNEL4 2 0x4 1 0 4294967295 INPUT_CRC_CHANNEL4 0 31 ixAZALIA_INPUT_CRC0_CHANNEL5 2 0x5 1 0 4294967295 INPUT_CRC_CHANNEL5 0 31 ixAZALIA_INPUT_CRC0_CHANNEL6 2 0x6 1 0 4294967295 INPUT_CRC_CHANNEL6 0 31 ixAZALIA_INPUT_CRC0_CHANNEL7 2 0x7 1 0 4294967295 INPUT_CRC_CHANNEL7 0 31 ixAZALIA_INPUT_CRC1_CHANNEL0 2 0x0 1 0 4294967295 INPUT_CRC_CHANNEL0 0 31 ixAZALIA_INPUT_CRC1_CHANNEL1 2 0x1 1 0 4294967295 INPUT_CRC_CHANNEL1 0 31 ixAZALIA_INPUT_CRC1_CHANNEL2 2 0x2 1 0 4294967295 INPUT_CRC_CHANNEL2 0 31 ixAZALIA_INPUT_CRC1_CHANNEL3 2 0x3 1 0 4294967295 INPUT_CRC_CHANNEL3 0 31 ixAZALIA_INPUT_CRC1_CHANNEL4 2 0x4 1 0 4294967295 INPUT_CRC_CHANNEL4 0 31 ixAZALIA_INPUT_CRC1_CHANNEL5 2 0x5 1 0 4294967295 INPUT_CRC_CHANNEL5 0 31 ixAZALIA_INPUT_CRC1_CHANNEL6 2 0x6 1 0 4294967295 INPUT_CRC_CHANNEL6 0 31 ixAZALIA_INPUT_CRC1_CHANNEL7 2 0x7 1 0 4294967295 INPUT_CRC_CHANNEL7 0 31 ixAZALIA_CRC0_CHANNEL0 2 0x0 1 0 4294967295 CRC_CHANNEL0 0 31 ixAZALIA_CRC0_CHANNEL1 2 0x1 1 0 4294967295 CRC_CHANNEL1 0 31 ixAZALIA_CRC0_CHANNEL2 2 0x2 1 0 4294967295 CRC_CHANNEL2 0 31 ixAZALIA_CRC0_CHANNEL3 2 0x3 1 0 4294967295 CRC_CHANNEL3 0 31 ixAZALIA_CRC0_CHANNEL4 2 0x4 1 0 4294967295 CRC_CHANNEL4 0 31 ixAZALIA_CRC0_CHANNEL5 2 0x5 1 0 4294967295 CRC_CHANNEL5 0 31 ixAZALIA_CRC0_CHANNEL6 2 0x6 1 0 4294967295 CRC_CHANNEL6 0 31 ixAZALIA_CRC0_CHANNEL7 2 0x7 1 0 4294967295 CRC_CHANNEL7 0 31 ixAZALIA_CRC1_CHANNEL0 2 0x0 1 0 4294967295 CRC_CHANNEL0 0 31 ixAZALIA_CRC1_CHANNEL1 2 0x1 1 0 4294967295 CRC_CHANNEL1 0 31 ixAZALIA_CRC1_CHANNEL2 2 0x2 1 0 4294967295 CRC_CHANNEL2 0 31 ixAZALIA_CRC1_CHANNEL3 2 0x3 1 0 4294967295 CRC_CHANNEL3 0 31 ixAZALIA_CRC1_CHANNEL4 2 0x4 1 0 4294967295 CRC_CHANNEL4 0 31 ixAZALIA_CRC1_CHANNEL5 2 0x5 1 0 4294967295 CRC_CHANNEL5 0 31 ixAZALIA_CRC1_CHANNEL6 2 0x6 1 0 4294967295 CRC_CHANNEL6 0 31 ixAZALIA_CRC1_CHANNEL7 2 0x7 1 0 4294967295 CRC_CHANNEL7 0 31 ixAZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT 2 0x6200 6 0 4294967295 NUMBER_OF_CHANNELS 0 3 BITS_PER_SAMPLE 4 6 SAMPLE_BASE_DIVISOR 8 10 SAMPLE_BASE_MULTIPLE 11 13 SAMPLE_BASE_RATE 14 14 STREAM_TYPE 15 15 ixAZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID 2 0x6706 2 0 4294967295 CHANNEL_ID 0 3 STREAM_ID 4 7 ixAZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER 2 0x670d 10 0 4294967295 DIGEN 0 0 V 1 1 VCFG 2 2 PRE 3 3 COPY 4 4 NON_AUDIO 5 5 PRO 6 6 L 7 7 CC 8 14 KEEPALIVE 23 23 ixAZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 2 0x6f09 14 0 4294967295 AUDIO_CHANNEL_CAPABILITIES 0 0 INPUT_AMPLIFIER_PRESENT 1 1 OUTPUT_AMPLIFIER_PRESENT 2 2 AMPLIFIER_PARAMETER_OVERRIDE 3 3 FORMAT_OVERRIDE 4 4 STRIPE 5 5 PROCESSING_WIDGET 6 6 UNSOLICITED_RESPONSE_CAPABILITY 7 7 CONNECTION_LIST 8 8 DIGITAL 9 9 POWER_CONTROL 10 10 LR_SWAP 11 11 AUDIO_WIDGET_CAPABILITIES_DELAY 16 19 TYPE 20 23 ixAZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 2 0x6f0a 2 0 4294967295 AUDIO_RATE_CAPABILITIES 0 11 AUDIO_BIT_CAPABILITIES 16 20 ixAZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS 2 0x6f0b 1 0 4294967295 STREAM_FORMATS 0 31 ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL 2 0x7707 1 0 4294967295 IN_ENABLE 5 5 ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE 2 0x7708 2 0 4294967295 TAG 0 5 ENABLE 7 7 ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_PIN_SENSE 2 0x7709 2 0 4294967295 IMPEDANCE_SENSE 0 30 PRESENCE_DETECT 31 31 ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 2 0x771c 8 0 4294967295 SEQUENCE 0 3 DEFAULT_ASSOCIATION 4 7 MISC 8 11 COLOR 12 15 CONNECTION_TYPE 16 19 DEFAULT_DEVICE 20 23 LOCATION 24 29 PORT_CONNECTIVITY 30 31 ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2 2 0x771d 2 0 4294967295 MISC 0 3 COLOR 4 7 ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3 2 0x771e 2 0 4294967295 CONNECTION_TYPE 0 3 DEFAULT_DEVICE 4 7 ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4 2 0x771f 2 0 4294967295 LOCATION 0 5 PORT_CONNECTIVITY 6 7 ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION 2 0x7771 1 0 4294967295 CHANNEL_ALLOCATION 0 7 ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE 2 0x7777 3 0 4294967295 MULTICHANNEL0_ENABLE 0 0 MULTICHANNEL0_MUTE 1 1 MULTICHANNEL0_CHANNEL_ID 4 7 ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE 2 0x7778 3 0 4294967295 MULTICHANNEL2_ENABLE 0 0 MULTICHANNEL2_MUTE 1 1 MULTICHANNEL2_CHANNEL_ID 4 7 ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE 2 0x7779 3 0 4294967295 MULTICHANNEL4_ENABLE 0 0 MULTICHANNEL4_MUTE 1 1 MULTICHANNEL4_CHANNEL_ID 4 7 ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE 2 0x777a 3 0 4294967295 MULTICHANNEL6_ENABLE 0 0 MULTICHANNEL6_MUTE 1 1 MULTICHANNEL6_CHANNEL_ID 4 7 ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_HBR 2 0x777c 2 0 4294967295 HBR_CAPABLE 0 0 HBR_ENABLE 4 4 ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE 2 0x7785 3 0 4294967295 MULTICHANNEL1_ENABLE 0 0 MULTICHANNEL1_MUTE 1 1 MULTICHANNEL1_CHANNEL_ID 4 7 ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE 2 0x7786 3 0 4294967295 MULTICHANNEL3_ENABLE 0 0 MULTICHANNEL3_MUTE 1 1 MULTICHANNEL3_CHANNEL_ID 4 7 ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE 2 0x7787 3 0 4294967295 MULTICHANNEL5_ENABLE 0 0 MULTICHANNEL5_MUTE 1 1 MULTICHANNEL5_CHANNEL_ID 4 7 ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE 2 0x7788 3 0 4294967295 MULTICHANNEL7_ENABLE 0 0 MULTICHANNEL7_MUTE 1 1 MULTICHANNEL7_CHANNEL_ID 4 7 ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 2 0x7798 2 0 4294967295 LPIB_SNAPSHOT_LOCK 0 0 CYCLIC_BUFFER_WRAP_COUNT 8 15 ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB 2 0x7799 1 0 4294967295 LPIB 0 31 ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 2 0x779a 1 0 4294967295 LPIB_TIMER_SNAPSHOT 0 31 ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL 2 0x779b 4 0 4294967295 INPUT_ACTIVITY 0 0 CHANNEL_LAYOUT 1 2 INPUT_ACTIVITY_UR_ENABLE 4 4 INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE 5 5 ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_INFOFRAME 2 0x779c 4 0 4294967295 CHANNEL_COUNT 0 2 CHANNEL_ALLOCATION 8 15 INFOFRAME_BYTE_5 16 23 INFOFRAME_VALID 31 31 ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_STATUS_L 2 0x779d 1 0 4294967295 CHANNEL_STATUS_L 0 31 ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_STATUS_H 2 0x779e 1 0 4294967295 CHANNEL_STATUS_H 0 31 ixAZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 2 0x7f09 13 0 4294967295 AUDIO_CHANNEL_CAPABILITIES 0 0 INPUT_AMPLIFIER_PRESENT 1 1 OUTPUT_AMPLIFIER_PRESENT 2 2 AMPLIFIER_PARAMETER_OVERRIDE 3 3 STRIPE 5 5 PROCESSING_WIDGET 6 6 UNSOLICITED_RESPONSE_CAPABILITY 7 7 CONNECTION_LIST 8 8 DIGITAL 9 9 POWER_CONTROL 10 10 LR_SWAP 11 11 AUDIO_WIDGET_CAPABILITIES_DELAY 16 19 TYPE 20 23 ixAZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES 2 0x7f0c 11 0 4294967295 IMPEDANCE_SENSE_CAPABLE 0 0 TRIGGER_REQUIRED 1 1 JACK_DETECTION_CAPABILITY 2 2 HEADPHONE_DRIVE_CAPABLE 3 3 OUTPUT_CAPABLE 4 4 INPUT_CAPABLE 5 5 BALANCED_I_O_PINS 6 6 HDMI 7 7 VREF_CONTROL 8 15 EAPD_CAPABLE 16 16 DP 24 24 ixAZALIA_F2_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID 2 0xf00 1 0 4294967295 AZALIA_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID 0 31 ixAZALIA_F2_CODEC_ROOT_PARAMETER_REVISION_ID 2 0xf02 1 0 4294967295 AZALIA_CODEC_ROOT_PARAMETER_REVISION_ID 0 31 ixAZALIA_F2_CODEC_ROOT_PARAMETER_SUBORDINATE_NODE_COUNT 2 0xf04 1 0 4294967295 AZALIA_CODEC_ROOT_PARAMETER_SUBORDINATE_NODE_COUNT 0 31 ixAZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE 2 0x1705 4 0 4294967295 POWER_STATE_SET 0 3 POWER_STATE_ACT 4 7 CLKSTOPOK 9 9 POWER_STATE_SETTINGS_RESET 10 10 ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID 2 0x1720 4 0 4294967295 SUBSYSTEM_ID_BYTE0 0 7 SUBSYSTEM_ID_BYTE1 8 15 SUBSYSTEM_ID_BYTE2 16 23 SUBSYSTEM_ID_BYTE3 24 31 ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_2 2 0x1721 1 0 4294967295 SUBSYSTEM_ID_BYTE1 0 7 ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_3 2 0x1722 1 0 4294967295 SUBSYSTEM_ID_BYTE2 0 7 ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_4 2 0x1723 1 0 4294967295 SUBSYSTEM_ID_BYTE3 0 7 ixAZALIA_F2_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION 2 0x1770 1 0 4294967295 CONVERTER_SYNCHRONIZATION 0 7 ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESET 2 0x17ff 1 0 4294967295 CODEC_RESET 0 0 ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_SUBORDINATE_NODE_COUNT 2 0x1f04 1 0 4294967295 AZALIA_CODEC_FUNCTION_PARAMETER_SUBORDINATE_NODE_COUNT 0 31 ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_GROUP_TYPE 2 0x1f05 1 0 4294967295 AZALIA_CODEC_FUNCTION_PARAMETER_GROUP_TYPE 0 31 ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES 2 0x1f0a 2 0 4294967295 AUDIO_RATE_CAPABILITIES 0 11 AUDIO_BIT_CAPABILITIES 16 20 ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS 2 0x1f0b 1 0 4294967295 AZALIA_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS 0 31 ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES 2 0x1f0f 3 0 4294967295 AZALIA_CODEC_FUNCTION_PARAMETER_POWER_STATES 0 29 CLKSTOP 30 30 EPSS 31 31 ixAZF0STREAM0_AZALIA_FIFO_SIZE_CONTROL 2 0x0 3 0 4294967295 MIN_FIFO_SIZE 0 6 MAX_FIFO_SIZE 8 14 MAX_LATENCY_SUPPORT 16 23 ixAZF0STREAM0_AZALIA_LATENCY_COUNTER_CONTROL 2 0x1 1 0 4294967295 AZALIA_LATENCY_COUNTER_RESET 0 0 ixAZF0STREAM0_AZALIA_WORSTCASE_LATENCY_COUNT 2 0x2 1 0 4294967295 AZALIA_WORSTCASE_LATENCY_COUNT 0 31 ixAZF0STREAM0_AZALIA_CUMULATIVE_LATENCY_COUNT 2 0x3 1 0 4294967295 AZALIA_CUMULATIVE_LATENCY_COUNT 0 31 ixAZF0STREAM0_AZALIA_CUMULATIVE_REQUEST_COUNT 2 0x4 1 0 4294967295 AZALIA_CUMULATIVE_REQUEST_COUNT 0 31 ixAZF0STREAM1_AZALIA_FIFO_SIZE_CONTROL 2 0x0 3 0 4294967295 MIN_FIFO_SIZE 0 6 MAX_FIFO_SIZE 8 14 MAX_LATENCY_SUPPORT 16 23 ixAZF0STREAM1_AZALIA_LATENCY_COUNTER_CONTROL 2 0x1 1 0 4294967295 AZALIA_LATENCY_COUNTER_RESET 0 0 ixAZF0STREAM1_AZALIA_WORSTCASE_LATENCY_COUNT 2 0x2 1 0 4294967295 AZALIA_WORSTCASE_LATENCY_COUNT 0 31 ixAZF0STREAM1_AZALIA_CUMULATIVE_LATENCY_COUNT 2 0x3 1 0 4294967295 AZALIA_CUMULATIVE_LATENCY_COUNT 0 31 ixAZF0STREAM1_AZALIA_CUMULATIVE_REQUEST_COUNT 2 0x4 1 0 4294967295 AZALIA_CUMULATIVE_REQUEST_COUNT 0 31 ixAZF0STREAM2_AZALIA_FIFO_SIZE_CONTROL 2 0x0 3 0 4294967295 MIN_FIFO_SIZE 0 6 MAX_FIFO_SIZE 8 14 MAX_LATENCY_SUPPORT 16 23 ixAZF0STREAM2_AZALIA_LATENCY_COUNTER_CONTROL 2 0x1 1 0 4294967295 AZALIA_LATENCY_COUNTER_RESET 0 0 ixAZF0STREAM2_AZALIA_WORSTCASE_LATENCY_COUNT 2 0x2 1 0 4294967295 AZALIA_WORSTCASE_LATENCY_COUNT 0 31 ixAZF0STREAM2_AZALIA_CUMULATIVE_LATENCY_COUNT 2 0x3 1 0 4294967295 AZALIA_CUMULATIVE_LATENCY_COUNT 0 31 ixAZF0STREAM2_AZALIA_CUMULATIVE_REQUEST_COUNT 2 0x4 1 0 4294967295 AZALIA_CUMULATIVE_REQUEST_COUNT 0 31 ixAZF0STREAM3_AZALIA_FIFO_SIZE_CONTROL 2 0x0 3 0 4294967295 MIN_FIFO_SIZE 0 6 MAX_FIFO_SIZE 8 14 MAX_LATENCY_SUPPORT 16 23 ixAZF0STREAM3_AZALIA_LATENCY_COUNTER_CONTROL 2 0x1 1 0 4294967295 AZALIA_LATENCY_COUNTER_RESET 0 0 ixAZF0STREAM3_AZALIA_WORSTCASE_LATENCY_COUNT 2 0x2 1 0 4294967295 AZALIA_WORSTCASE_LATENCY_COUNT 0 31 ixAZF0STREAM3_AZALIA_CUMULATIVE_LATENCY_COUNT 2 0x3 1 0 4294967295 AZALIA_CUMULATIVE_LATENCY_COUNT 0 31 ixAZF0STREAM3_AZALIA_CUMULATIVE_REQUEST_COUNT 2 0x4 1 0 4294967295 AZALIA_CUMULATIVE_REQUEST_COUNT 0 31 ixAZF0STREAM4_AZALIA_FIFO_SIZE_CONTROL 2 0x0 3 0 4294967295 MIN_FIFO_SIZE 0 6 MAX_FIFO_SIZE 8 14 MAX_LATENCY_SUPPORT 16 23 ixAZF0STREAM4_AZALIA_LATENCY_COUNTER_CONTROL 2 0x1 1 0 4294967295 AZALIA_LATENCY_COUNTER_RESET 0 0 ixAZF0STREAM4_AZALIA_WORSTCASE_LATENCY_COUNT 2 0x2 1 0 4294967295 AZALIA_WORSTCASE_LATENCY_COUNT 0 31 ixAZF0STREAM4_AZALIA_CUMULATIVE_LATENCY_COUNT 2 0x3 1 0 4294967295 AZALIA_CUMULATIVE_LATENCY_COUNT 0 31 ixAZF0STREAM4_AZALIA_CUMULATIVE_REQUEST_COUNT 2 0x4 1 0 4294967295 AZALIA_CUMULATIVE_REQUEST_COUNT 0 31 ixAZF0STREAM5_AZALIA_FIFO_SIZE_CONTROL 2 0x0 3 0 4294967295 MIN_FIFO_SIZE 0 6 MAX_FIFO_SIZE 8 14 MAX_LATENCY_SUPPORT 16 23 ixAZF0STREAM5_AZALIA_LATENCY_COUNTER_CONTROL 2 0x1 1 0 4294967295 AZALIA_LATENCY_COUNTER_RESET 0 0 ixAZF0STREAM5_AZALIA_WORSTCASE_LATENCY_COUNT 2 0x2 1 0 4294967295 AZALIA_WORSTCASE_LATENCY_COUNT 0 31 ixAZF0STREAM5_AZALIA_CUMULATIVE_LATENCY_COUNT 2 0x3 1 0 4294967295 AZALIA_CUMULATIVE_LATENCY_COUNT 0 31 ixAZF0STREAM5_AZALIA_CUMULATIVE_REQUEST_COUNT 2 0x4 1 0 4294967295 AZALIA_CUMULATIVE_REQUEST_COUNT 0 31 ixAZF0STREAM6_AZALIA_FIFO_SIZE_CONTROL 2 0x0 3 0 4294967295 MIN_FIFO_SIZE 0 6 MAX_FIFO_SIZE 8 14 MAX_LATENCY_SUPPORT 16 23 ixAZF0STREAM6_AZALIA_LATENCY_COUNTER_CONTROL 2 0x1 1 0 4294967295 AZALIA_LATENCY_COUNTER_RESET 0 0 ixAZF0STREAM6_AZALIA_WORSTCASE_LATENCY_COUNT 2 0x2 1 0 4294967295 AZALIA_WORSTCASE_LATENCY_COUNT 0 31 ixAZF0STREAM6_AZALIA_CUMULATIVE_LATENCY_COUNT 2 0x3 1 0 4294967295 AZALIA_CUMULATIVE_LATENCY_COUNT 0 31 ixAZF0STREAM6_AZALIA_CUMULATIVE_REQUEST_COUNT 2 0x4 1 0 4294967295 AZALIA_CUMULATIVE_REQUEST_COUNT 0 31 ixAZF0STREAM7_AZALIA_FIFO_SIZE_CONTROL 2 0x0 3 0 4294967295 MIN_FIFO_SIZE 0 6 MAX_FIFO_SIZE 8 14 MAX_LATENCY_SUPPORT 16 23 ixAZF0STREAM7_AZALIA_LATENCY_COUNTER_CONTROL 2 0x1 1 0 4294967295 AZALIA_LATENCY_COUNTER_RESET 0 0 ixAZF0STREAM7_AZALIA_WORSTCASE_LATENCY_COUNT 2 0x2 1 0 4294967295 AZALIA_WORSTCASE_LATENCY_COUNT 0 31 ixAZF0STREAM7_AZALIA_CUMULATIVE_LATENCY_COUNT 2 0x3 1 0 4294967295 AZALIA_CUMULATIVE_LATENCY_COUNT 0 31 ixAZF0STREAM7_AZALIA_CUMULATIVE_REQUEST_COUNT 2 0x4 1 0 4294967295 AZALIA_CUMULATIVE_REQUEST_COUNT 0 31 ixAZF0STREAM8_AZALIA_FIFO_SIZE_CONTROL 2 0x0 3 0 4294967295 MIN_FIFO_SIZE 0 6 MAX_FIFO_SIZE 8 14 MAX_LATENCY_SUPPORT 16 23 ixAZF0STREAM8_AZALIA_LATENCY_COUNTER_CONTROL 2 0x1 1 0 4294967295 AZALIA_LATENCY_COUNTER_RESET 0 0 ixAZF0STREAM8_AZALIA_WORSTCASE_LATENCY_COUNT 2 0x2 1 0 4294967295 AZALIA_WORSTCASE_LATENCY_COUNT 0 31 ixAZF0STREAM8_AZALIA_CUMULATIVE_LATENCY_COUNT 2 0x3 1 0 4294967295 AZALIA_CUMULATIVE_LATENCY_COUNT 0 31 ixAZF0STREAM8_AZALIA_CUMULATIVE_REQUEST_COUNT 2 0x4 1 0 4294967295 AZALIA_CUMULATIVE_REQUEST_COUNT 0 31 ixAZF0STREAM9_AZALIA_FIFO_SIZE_CONTROL 2 0x0 3 0 4294967295 MIN_FIFO_SIZE 0 6 MAX_FIFO_SIZE 8 14 MAX_LATENCY_SUPPORT 16 23 ixAZF0STREAM9_AZALIA_LATENCY_COUNTER_CONTROL 2 0x1 1 0 4294967295 AZALIA_LATENCY_COUNTER_RESET 0 0 ixAZF0STREAM9_AZALIA_WORSTCASE_LATENCY_COUNT 2 0x2 1 0 4294967295 AZALIA_WORSTCASE_LATENCY_COUNT 0 31 ixAZF0STREAM9_AZALIA_CUMULATIVE_LATENCY_COUNT 2 0x3 1 0 4294967295 AZALIA_CUMULATIVE_LATENCY_COUNT 0 31 ixAZF0STREAM9_AZALIA_CUMULATIVE_REQUEST_COUNT 2 0x4 1 0 4294967295 AZALIA_CUMULATIVE_REQUEST_COUNT 0 31 ixAZF0STREAM10_AZALIA_FIFO_SIZE_CONTROL 2 0x0 3 0 4294967295 MIN_FIFO_SIZE 0 6 MAX_FIFO_SIZE 8 14 MAX_LATENCY_SUPPORT 16 23 ixAZF0STREAM10_AZALIA_LATENCY_COUNTER_CONTROL 2 0x1 1 0 4294967295 AZALIA_LATENCY_COUNTER_RESET 0 0 ixAZF0STREAM10_AZALIA_WORSTCASE_LATENCY_COUNT 2 0x2 1 0 4294967295 AZALIA_WORSTCASE_LATENCY_COUNT 0 31 ixAZF0STREAM10_AZALIA_CUMULATIVE_LATENCY_COUNT 2 0x3 1 0 4294967295 AZALIA_CUMULATIVE_LATENCY_COUNT 0 31 ixAZF0STREAM10_AZALIA_CUMULATIVE_REQUEST_COUNT 2 0x4 1 0 4294967295 AZALIA_CUMULATIVE_REQUEST_COUNT 0 31 ixAZF0STREAM11_AZALIA_FIFO_SIZE_CONTROL 2 0x0 3 0 4294967295 MIN_FIFO_SIZE 0 6 MAX_FIFO_SIZE 8 14 MAX_LATENCY_SUPPORT 16 23 ixAZF0STREAM11_AZALIA_LATENCY_COUNTER_CONTROL 2 0x1 1 0 4294967295 AZALIA_LATENCY_COUNTER_RESET 0 0 ixAZF0STREAM11_AZALIA_WORSTCASE_LATENCY_COUNT 2 0x2 1 0 4294967295 AZALIA_WORSTCASE_LATENCY_COUNT 0 31 ixAZF0STREAM11_AZALIA_CUMULATIVE_LATENCY_COUNT 2 0x3 1 0 4294967295 AZALIA_CUMULATIVE_LATENCY_COUNT 0 31 ixAZF0STREAM11_AZALIA_CUMULATIVE_REQUEST_COUNT 2 0x4 1 0 4294967295 AZALIA_CUMULATIVE_REQUEST_COUNT 0 31 ixAZF0STREAM12_AZALIA_FIFO_SIZE_CONTROL 2 0x0 3 0 4294967295 MIN_FIFO_SIZE 0 6 MAX_FIFO_SIZE 8 14 MAX_LATENCY_SUPPORT 16 23 ixAZF0STREAM12_AZALIA_LATENCY_COUNTER_CONTROL 2 0x1 1 0 4294967295 AZALIA_LATENCY_COUNTER_RESET 0 0 ixAZF0STREAM12_AZALIA_WORSTCASE_LATENCY_COUNT 2 0x2 1 0 4294967295 AZALIA_WORSTCASE_LATENCY_COUNT 0 31 ixAZF0STREAM12_AZALIA_CUMULATIVE_LATENCY_COUNT 2 0x3 1 0 4294967295 AZALIA_CUMULATIVE_LATENCY_COUNT 0 31 ixAZF0STREAM12_AZALIA_CUMULATIVE_REQUEST_COUNT 2 0x4 1 0 4294967295 AZALIA_CUMULATIVE_REQUEST_COUNT 0 31 ixAZF0STREAM13_AZALIA_FIFO_SIZE_CONTROL 2 0x0 3 0 4294967295 MIN_FIFO_SIZE 0 6 MAX_FIFO_SIZE 8 14 MAX_LATENCY_SUPPORT 16 23 ixAZF0STREAM13_AZALIA_LATENCY_COUNTER_CONTROL 2 0x1 1 0 4294967295 AZALIA_LATENCY_COUNTER_RESET 0 0 ixAZF0STREAM13_AZALIA_WORSTCASE_LATENCY_COUNT 2 0x2 1 0 4294967295 AZALIA_WORSTCASE_LATENCY_COUNT 0 31 ixAZF0STREAM13_AZALIA_CUMULATIVE_LATENCY_COUNT 2 0x3 1 0 4294967295 AZALIA_CUMULATIVE_LATENCY_COUNT 0 31 ixAZF0STREAM13_AZALIA_CUMULATIVE_REQUEST_COUNT 2 0x4 1 0 4294967295 AZALIA_CUMULATIVE_REQUEST_COUNT 0 31 ixAZF0STREAM14_AZALIA_FIFO_SIZE_CONTROL 2 0x0 3 0 4294967295 MIN_FIFO_SIZE 0 6 MAX_FIFO_SIZE 8 14 MAX_LATENCY_SUPPORT 16 23 ixAZF0STREAM14_AZALIA_LATENCY_COUNTER_CONTROL 2 0x1 1 0 4294967295 AZALIA_LATENCY_COUNTER_RESET 0 0 ixAZF0STREAM14_AZALIA_WORSTCASE_LATENCY_COUNT 2 0x2 1 0 4294967295 AZALIA_WORSTCASE_LATENCY_COUNT 0 31 ixAZF0STREAM14_AZALIA_CUMULATIVE_LATENCY_COUNT 2 0x3 1 0 4294967295 AZALIA_CUMULATIVE_LATENCY_COUNT 0 31 ixAZF0STREAM14_AZALIA_CUMULATIVE_REQUEST_COUNT 2 0x4 1 0 4294967295 AZALIA_CUMULATIVE_REQUEST_COUNT 0 31 ixAZF0STREAM15_AZALIA_FIFO_SIZE_CONTROL 2 0x0 3 0 4294967295 MIN_FIFO_SIZE 0 6 MAX_FIFO_SIZE 8 14 MAX_LATENCY_SUPPORT 16 23 ixAZF0STREAM15_AZALIA_LATENCY_COUNTER_CONTROL 2 0x1 1 0 4294967295 AZALIA_LATENCY_COUNTER_RESET 0 0 ixAZF0STREAM15_AZALIA_WORSTCASE_LATENCY_COUNT 2 0x2 1 0 4294967295 AZALIA_WORSTCASE_LATENCY_COUNT 0 31 ixAZF0STREAM15_AZALIA_CUMULATIVE_LATENCY_COUNT 2 0x3 1 0 4294967295 AZALIA_CUMULATIVE_LATENCY_COUNT 0 31 ixAZF0STREAM15_AZALIA_CUMULATIVE_REQUEST_COUNT 2 0x4 1 0 4294967295 AZALIA_CUMULATIVE_REQUEST_COUNT 0 31 ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 2 0x1 14 0 4294967295 AUDIO_CHANNEL_CAPABILITIES 0 0 INPUT_AMPLIFIER_PRESENT 1 1 OUTPUT_AMPLIFIER_PRESENT 2 2 AMPLIFIER_PARAMETER_OVERRIDE 3 3 FORMAT_OVERRIDE 4 4 STRIPE 5 5 PROCESSING_WIDGET 6 6 UNSOLICITED_RESPONSE_CAPABILITY 7 7 CONNECTION_LIST 8 8 DIGITAL 9 9 POWER_CONTROL 10 10 LR_SWAP 11 11 AUDIO_WIDGET_CAPABILITIES_DELAY 16 19 TYPE 20 23 ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT 2 0x2 6 0 4294967295 NUMBER_OF_CHANNELS 0 3 BITS_PER_SAMPLE 4 6 SAMPLE_BASE_DIVISOR 8 10 SAMPLE_BASE_MULTIPLE 11 13 SAMPLE_BASE_RATE 14 14 STREAM_TYPE 15 15 ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID 2 0x3 2 0 4294967295 CHANNEL_ID 0 3 STREAM_ID 4 7 ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER 2 0x4 10 0 4294967295 DIGEN 0 0 V 1 1 VCFG 2 2 PRE 3 3 COPY 4 4 NON_AUDIO 5 5 PRO 6 6 L 7 7 CC 8 14 KEEPALIVE 23 23 ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS 2 0x5 1 0 4294967295 STREAM_FORMATS 0 31 ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 2 0x6 2 0 4294967295 AUDIO_RATE_CAPABILITIES 0 11 AUDIO_BIT_CAPABILITIES 16 20 ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL 2 0x7 2 0 4294967295 STRIPE_CONTROL 0 1 STRIPE_CAPABILITY 20 22 ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE 2 0x8 1 0 4294967295 RAMP_RATE 0 7 ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING 2 0x9 4 0 4294967295 PRESENTATION_TIME_EMBEDDING_ENABLE 0 0 PRESENTATION_TIME_OFFSET_CHANGED 1 1 CLEAR_GTC_COUNTER_MIN_MAX_DELTA 2 2 PRESENTATION_TIME_EMBEDDING_GROUP 4 6 ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA 2 0xc 1 0 4294967295 GTC_COUNTER_DELTA 0 31 ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN 2 0xd 1 0 4294967295 GTC_COUNTER_DELTA_MIN 0 31 ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX 2 0xe 1 0 4294967295 GTC_COUNTER_DELTA_MAX 0 31 ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 2 0x20 13 0 4294967295 AUDIO_CHANNEL_CAPABILITIES 0 0 INPUT_AMPLIFIER_PRESENT 1 1 OUTPUT_AMPLIFIER_PRESENT 2 2 AMPLIFIER_PARAMETER_OVERRIDE 3 3 STRIPE 5 5 PROCESSING_WIDGET 6 6 UNSOLICITED_RESPONSE_CAPABILITY 7 7 CONNECTION_LIST 8 8 DIGITAL 9 9 POWER_CONTROL 10 10 LR_SWAP 11 11 AUDIO_WIDGET_CAPABILITIES_DELAY 16 19 TYPE 20 23 ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES 2 0x21 11 0 4294967295 IMPEDANCE_SENSE_CAPABLE 0 0 TRIGGER_REQUIRED 1 1 JACK_DETECTION_CAPABILITY 2 2 HEADPHONE_DRIVE_CAPABLE 3 3 OUTPUT_CAPABLE 4 4 INPUT_CAPABLE 5 5 BALANCED_I_O_PINS 6 6 HDMI 7 7 VREF_CONTROL 8 15 EAPD_CAPABLE 16 16 DP 24 24 ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE 2 0x22 2 0 4294967295 TAG 0 5 ENABLE 7 7 ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE 2 0x23 1 0 4294967295 IMPEDANCE_SENSE 0 30 ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL 2 0x24 1 0 4294967295 OUT_ENABLE 6 6 ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER 2 0x25 8 0 4294967295 SPEAKER_ALLOCATION 0 6 CHANNEL_ALLOCATION 8 15 HDMI_CONNECTION 16 16 DP_CONNECTION 17 17 EXTRA_CONNECTION_INFO 18 23 LFE_PLAYBACK_LEVEL 24 25 LEVEL_SHIFT 27 30 DOWN_MIX_INHIBIT 31 31 ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 2 0x28 4 0 4294967295 MAX_CHANNELS 0 2 SUPPORTED_FREQUENCIES 8 15 DESCRIPTOR_BYTE_2 16 23 SUPPORTED_FREQUENCIES_STEREO 24 31 ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 2 0x29 3 0 4294967295 MAX_CHANNELS 0 2 SUPPORTED_FREQUENCIES 8 15 DESCRIPTOR_BYTE_2 16 23 ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 2 0x2a 3 0 4294967295 MAX_CHANNELS 0 2 SUPPORTED_FREQUENCIES 8 15 DESCRIPTOR_BYTE_2 16 23 ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 2 0x2b 3 0 4294967295 MAX_CHANNELS 0 2 SUPPORTED_FREQUENCIES 8 15 DESCRIPTOR_BYTE_2 16 23 ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 2 0x2c 3 0 4294967295 MAX_CHANNELS 0 2 SUPPORTED_FREQUENCIES 8 15 DESCRIPTOR_BYTE_2 16 23 ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 2 0x2d 3 0 4294967295 MAX_CHANNELS 0 2 SUPPORTED_FREQUENCIES 8 15 DESCRIPTOR_BYTE_2 16 23 ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 2 0x2e 3 0 4294967295 MAX_CHANNELS 0 2 SUPPORTED_FREQUENCIES 8 15 DESCRIPTOR_BYTE_2 16 23 ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 2 0x2f 3 0 4294967295 MAX_CHANNELS 0 2 SUPPORTED_FREQUENCIES 8 15 DESCRIPTOR_BYTE_2 16 23 ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 2 0x30 3 0 4294967295 MAX_CHANNELS 0 2 SUPPORTED_FREQUENCIES 8 15 DESCRIPTOR_BYTE_2 16 23 ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 2 0x31 3 0 4294967295 MAX_CHANNELS 0 2 SUPPORTED_FREQUENCIES 8 15 DESCRIPTOR_BYTE_2 16 23 ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 2 0x32 3 0 4294967295 MAX_CHANNELS 0 2 SUPPORTED_FREQUENCIES 8 15 DESCRIPTOR_BYTE_2 16 23 ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 2 0x33 3 0 4294967295 MAX_CHANNELS 0 2 SUPPORTED_FREQUENCIES 8 15 DESCRIPTOR_BYTE_2 16 23 ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 2 0x34 3 0 4294967295 MAX_CHANNELS 0 2 SUPPORTED_FREQUENCIES 8 15 DESCRIPTOR_BYTE_2 16 23 ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 2 0x35 3 0 4294967295 MAX_CHANNELS 0 2 SUPPORTED_FREQUENCIES 8 15 DESCRIPTOR_BYTE_2 16 23 ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE 2 0x36 12 0 4294967295 MULTICHANNEL01_ENABLE 0 0 MULTICHANNEL01_MUTE 1 1 MULTICHANNEL01_CHANNEL_ID 4 7 MULTICHANNEL23_ENABLE 8 8 MULTICHANNEL23_MUTE 9 9 MULTICHANNEL23_CHANNEL_ID 12 15 MULTICHANNEL45_ENABLE 16 16 MULTICHANNEL45_MUTE 17 17 MULTICHANNEL45_CHANNEL_ID 20 23 MULTICHANNEL67_ENABLE 24 24 MULTICHANNEL67_MUTE 25 25 MULTICHANNEL67_CHANNEL_ID 28 31 ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC 2 0x37 2 0 4294967295 VIDEO_LIPSYNC 0 7 AUDIO_LIPSYNC 8 15 ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR 2 0x38 2 0 4294967295 HBR_CAPABLE 0 0 HBR_ENABLE 4 4 ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0 2 0x3a 2 0 4294967295 MANUFACTURER_ID 0 15 PRODUCT_ID 16 31 ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1 2 0x3b 1 0 4294967295 SINK_DESCRIPTION_LEN 0 7 ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2 2 0x3c 1 0 4294967295 PORT_ID0 0 31 ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3 2 0x3d 1 0 4294967295 PORT_ID1 0 31 ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4 2 0x3e 4 0 4294967295 DESCRIPTION0 0 7 DESCRIPTION1 8 15 DESCRIPTION2 16 23 DESCRIPTION3 24 31 ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5 2 0x3f 4 0 4294967295 DESCRIPTION4 0 7 DESCRIPTION5 8 15 DESCRIPTION6 16 23 DESCRIPTION7 24 31 ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6 2 0x40 4 0 4294967295 DESCRIPTION8 0 7 DESCRIPTION9 8 15 DESCRIPTION10 16 23 DESCRIPTION11 24 31 ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7 2 0x41 4 0 4294967295 DESCRIPTION12 0 7 DESCRIPTION13 8 15 DESCRIPTION14 16 23 DESCRIPTION15 24 31 ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8 2 0x42 2 0 4294967295 DESCRIPTION16 0 7 DESCRIPTION17 8 15 ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL 2 0x54 3 0 4294967295 CLOCK_GATING_DISABLE 0 0 CLOCK_ON_STATE 4 4 AUDIO_ENABLED 31 31 ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 2 0x55 2 0 4294967295 UNSOLICITED_RESPONSE_PAYLOAD 0 25 UNSOLICITED_RESPONSE_FORCE 28 28 ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 2 0x56 8 0 4294967295 SEQUENCE 0 3 DEFAULT_ASSOCIATION 4 7 MISC 8 11 COLOR 12 15 CONNECTION_TYPE 16 19 DEFAULT_DEVICE 20 23 LOCATION 24 29 PORT_CONNECTIVITY 30 31 ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2 2 0x57 12 0 4294967295 MULTICHANNEL1_ENABLE 0 0 MULTICHANNEL1_MUTE 1 1 MULTICHANNEL1_CHANNEL_ID 4 7 MULTICHANNEL3_ENABLE 8 8 MULTICHANNEL3_MUTE 9 9 MULTICHANNEL3_CHANNEL_ID 12 15 MULTICHANNEL5_ENABLE 16 16 MULTICHANNEL5_MUTE 17 17 MULTICHANNEL5_CHANNEL_ID 20 23 MULTICHANNEL7_ENABLE 24 24 MULTICHANNEL7_MUTE 25 25 MULTICHANNEL7_CHANNEL_ID 28 31 ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE 2 0x58 1 0 4294967295 MULTICHANNEL_MODE 0 0 ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0 2 0x59 2 0 4294967295 IEC_60958_CS_MODE 0 1 IEC_60958_CS_SOURCE_NUMBER 2 5 ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1 2 0x5a 4 0 4294967295 IEC_60958_CS_CLOCK_ACCURACY 0 1 IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN 2 2 IEC_60958_CS_WORD_LENGTH 3 6 IEC_60958_CS_WORD_LENGTH_OVRRD_EN 7 7 ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2 2 0x5b 2 0 4294967295 IEC_60958_CS_SAMPLING_FREQUENCY 0 5 IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN 6 6 ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3 2 0x5c 2 0 4294967295 IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY 0 3 IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN 4 4 ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4 2 0x5d 4 0 4294967295 IEC_60958_CS_SAMPLING_FREQUENCY_COEFF 0 3 IEC_60958_CS_MPEG_SURROUND_INFO 4 4 IEC_60958_CS_CGMS_A 5 6 IEC_60958_CS_CGMS_A_VALID 7 7 ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5 2 0x5e 2 0 4294967295 IEC_60958_CS_CHANNEL_NUMBER_L 0 3 IEC_60958_CS_CHANNEL_NUMBER_R 4 7 ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6 2 0x5f 2 0 4294967295 IEC_60958_CS_CHANNEL_NUMBER_2 0 3 IEC_60958_CS_CHANNEL_NUMBER_3 4 7 ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7 2 0x60 2 0 4294967295 IEC_60958_CS_CHANNEL_NUMBER_4 0 3 IEC_60958_CS_CHANNEL_NUMBER_5 4 7 ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8 2 0x61 2 0 4294967295 IEC_60958_CS_CHANNEL_NUMBER_6 0 3 IEC_60958_CS_CHANNEL_NUMBER_7 4 7 ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO 2 0x62 1 0 4294967295 ASSOCIATION_INFO 0 31 ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS 2 0x63 1 0 4294967295 OUTPUT_ACTIVE 0 0 ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 2 0x64 2 0 4294967295 LPIB_SNAPSHOT_LOCK 0 0 CYCLIC_BUFFER_WRAP_COUNT 8 15 ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB 2 0x65 1 0 4294967295 LPIB 0 31 ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 2 0x66 1 0 4294967295 LPIB_TIMER_SNAPSHOT 0 31 ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE 2 0x67 1 0 4294967295 CODING_TYPE 0 7 ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED 2 0x68 4 0 4294967295 FORMAT_CHANGED 0 0 FORMAT_CHANGED_ACK_UR_ENABLE 1 1 FORMAT_CHANGE_REASON 8 15 FORMAT_CHANGE_RESPONSE 16 23 ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION 2 0x69 1 0 4294967295 WIRELESS_DISPLAY_IDENTIFICATION 0 1 ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE 2 0x6a 2 0 4294967295 REMOTE_KEEP_ALIVE_ENABLE 0 0 REMOTE_KEEP_ALIVE_CAPABILITY 4 4 ixAZF0ENDPOINT0_AZALIA_F0_AUDIO_ENABLE_STATUS 2 0x6b 1 0 4294967295 AUDIO_ENABLE_STATUS 0 0 ixAZF0ENDPOINT0_AZALIA_F0_AUDIO_ENABLED_INT_STATUS 2 0x6c 3 0 4294967295 AUDIO_ENABLED_FLAG 0 0 AUDIO_ENABLED_MASK 4 4 AUDIO_ENABLED_TYPE 8 8 ixAZF0ENDPOINT0_AZALIA_F0_AUDIO_DISABLED_INT_STATUS 2 0x6d 3 0 4294967295 AUDIO_DISABLED_FLAG 0 0 AUDIO_DISABLED_MASK 4 4 AUDIO_DISABLED_TYPE 8 8 ixAZF0ENDPOINT0_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS 2 0x6e 3 0 4294967295 AUDIO_FORMAT_CHANGED_FLAG 0 0 AUDIO_FORMAT_CHANGED_MASK 4 4 AUDIO_FORMAT_CHANGED_TYPE 8 8 ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 2 0x1 14 0 4294967295 AUDIO_CHANNEL_CAPABILITIES 0 0 INPUT_AMPLIFIER_PRESENT 1 1 OUTPUT_AMPLIFIER_PRESENT 2 2 AMPLIFIER_PARAMETER_OVERRIDE 3 3 FORMAT_OVERRIDE 4 4 STRIPE 5 5 PROCESSING_WIDGET 6 6 UNSOLICITED_RESPONSE_CAPABILITY 7 7 CONNECTION_LIST 8 8 DIGITAL 9 9 POWER_CONTROL 10 10 LR_SWAP 11 11 AUDIO_WIDGET_CAPABILITIES_DELAY 16 19 TYPE 20 23 ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT 2 0x2 6 0 4294967295 NUMBER_OF_CHANNELS 0 3 BITS_PER_SAMPLE 4 6 SAMPLE_BASE_DIVISOR 8 10 SAMPLE_BASE_MULTIPLE 11 13 SAMPLE_BASE_RATE 14 14 STREAM_TYPE 15 15 ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID 2 0x3 2 0 4294967295 CHANNEL_ID 0 3 STREAM_ID 4 7 ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER 2 0x4 10 0 4294967295 DIGEN 0 0 V 1 1 VCFG 2 2 PRE 3 3 COPY 4 4 NON_AUDIO 5 5 PRO 6 6 L 7 7 CC 8 14 KEEPALIVE 23 23 ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS 2 0x5 1 0 4294967295 STREAM_FORMATS 0 31 ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 2 0x6 2 0 4294967295 AUDIO_RATE_CAPABILITIES 0 11 AUDIO_BIT_CAPABILITIES 16 20 ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL 2 0x7 2 0 4294967295 STRIPE_CONTROL 0 1 STRIPE_CAPABILITY 20 22 ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE 2 0x8 1 0 4294967295 RAMP_RATE 0 7 ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING 2 0x9 4 0 4294967295 PRESENTATION_TIME_EMBEDDING_ENABLE 0 0 PRESENTATION_TIME_OFFSET_CHANGED 1 1 CLEAR_GTC_COUNTER_MIN_MAX_DELTA 2 2 PRESENTATION_TIME_EMBEDDING_GROUP 4 6 ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA 2 0xc 1 0 4294967295 GTC_COUNTER_DELTA 0 31 ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN 2 0xd 1 0 4294967295 GTC_COUNTER_DELTA_MIN 0 31 ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX 2 0xe 1 0 4294967295 GTC_COUNTER_DELTA_MAX 0 31 ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 2 0x20 13 0 4294967295 AUDIO_CHANNEL_CAPABILITIES 0 0 INPUT_AMPLIFIER_PRESENT 1 1 OUTPUT_AMPLIFIER_PRESENT 2 2 AMPLIFIER_PARAMETER_OVERRIDE 3 3 STRIPE 5 5 PROCESSING_WIDGET 6 6 UNSOLICITED_RESPONSE_CAPABILITY 7 7 CONNECTION_LIST 8 8 DIGITAL 9 9 POWER_CONTROL 10 10 LR_SWAP 11 11 AUDIO_WIDGET_CAPABILITIES_DELAY 16 19 TYPE 20 23 ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES 2 0x21 11 0 4294967295 IMPEDANCE_SENSE_CAPABLE 0 0 TRIGGER_REQUIRED 1 1 JACK_DETECTION_CAPABILITY 2 2 HEADPHONE_DRIVE_CAPABLE 3 3 OUTPUT_CAPABLE 4 4 INPUT_CAPABLE 5 5 BALANCED_I_O_PINS 6 6 HDMI 7 7 VREF_CONTROL 8 15 EAPD_CAPABLE 16 16 DP 24 24 ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE 2 0x22 2 0 4294967295 TAG 0 5 ENABLE 7 7 ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE 2 0x23 1 0 4294967295 IMPEDANCE_SENSE 0 30 ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL 2 0x24 1 0 4294967295 OUT_ENABLE 6 6 ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER 2 0x25 8 0 4294967295 SPEAKER_ALLOCATION 0 6 CHANNEL_ALLOCATION 8 15 HDMI_CONNECTION 16 16 DP_CONNECTION 17 17 EXTRA_CONNECTION_INFO 18 23 LFE_PLAYBACK_LEVEL 24 25 LEVEL_SHIFT 27 30 DOWN_MIX_INHIBIT 31 31 ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 2 0x28 4 0 4294967295 MAX_CHANNELS 0 2 SUPPORTED_FREQUENCIES 8 15 DESCRIPTOR_BYTE_2 16 23 SUPPORTED_FREQUENCIES_STEREO 24 31 ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 2 0x29 3 0 4294967295 MAX_CHANNELS 0 2 SUPPORTED_FREQUENCIES 8 15 DESCRIPTOR_BYTE_2 16 23 ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 2 0x2a 3 0 4294967295 MAX_CHANNELS 0 2 SUPPORTED_FREQUENCIES 8 15 DESCRIPTOR_BYTE_2 16 23 ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 2 0x2b 3 0 4294967295 MAX_CHANNELS 0 2 SUPPORTED_FREQUENCIES 8 15 DESCRIPTOR_BYTE_2 16 23 ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 2 0x2c 3 0 4294967295 MAX_CHANNELS 0 2 SUPPORTED_FREQUENCIES 8 15 DESCRIPTOR_BYTE_2 16 23 ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 2 0x2d 3 0 4294967295 MAX_CHANNELS 0 2 SUPPORTED_FREQUENCIES 8 15 DESCRIPTOR_BYTE_2 16 23 ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 2 0x2e 3 0 4294967295 MAX_CHANNELS 0 2 SUPPORTED_FREQUENCIES 8 15 DESCRIPTOR_BYTE_2 16 23 ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 2 0x2f 3 0 4294967295 MAX_CHANNELS 0 2 SUPPORTED_FREQUENCIES 8 15 DESCRIPTOR_BYTE_2 16 23 ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 2 0x30 3 0 4294967295 MAX_CHANNELS 0 2 SUPPORTED_FREQUENCIES 8 15 DESCRIPTOR_BYTE_2 16 23 ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 2 0x31 3 0 4294967295 MAX_CHANNELS 0 2 SUPPORTED_FREQUENCIES 8 15 DESCRIPTOR_BYTE_2 16 23 ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 2 0x32 3 0 4294967295 MAX_CHANNELS 0 2 SUPPORTED_FREQUENCIES 8 15 DESCRIPTOR_BYTE_2 16 23 ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 2 0x33 3 0 4294967295 MAX_CHANNELS 0 2 SUPPORTED_FREQUENCIES 8 15 DESCRIPTOR_BYTE_2 16 23 ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 2 0x34 3 0 4294967295 MAX_CHANNELS 0 2 SUPPORTED_FREQUENCIES 8 15 DESCRIPTOR_BYTE_2 16 23 ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 2 0x35 3 0 4294967295 MAX_CHANNELS 0 2 SUPPORTED_FREQUENCIES 8 15 DESCRIPTOR_BYTE_2 16 23 ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE 2 0x36 12 0 4294967295 MULTICHANNEL01_ENABLE 0 0 MULTICHANNEL01_MUTE 1 1 MULTICHANNEL01_CHANNEL_ID 4 7 MULTICHANNEL23_ENABLE 8 8 MULTICHANNEL23_MUTE 9 9 MULTICHANNEL23_CHANNEL_ID 12 15 MULTICHANNEL45_ENABLE 16 16 MULTICHANNEL45_MUTE 17 17 MULTICHANNEL45_CHANNEL_ID 20 23 MULTICHANNEL67_ENABLE 24 24 MULTICHANNEL67_MUTE 25 25 MULTICHANNEL67_CHANNEL_ID 28 31 ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC 2 0x37 2 0 4294967295 VIDEO_LIPSYNC 0 7 AUDIO_LIPSYNC 8 15 ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR 2 0x38 2 0 4294967295 HBR_CAPABLE 0 0 HBR_ENABLE 4 4 ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0 2 0x3a 2 0 4294967295 MANUFACTURER_ID 0 15 PRODUCT_ID 16 31 ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1 2 0x3b 1 0 4294967295 SINK_DESCRIPTION_LEN 0 7 ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2 2 0x3c 1 0 4294967295 PORT_ID0 0 31 ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3 2 0x3d 1 0 4294967295 PORT_ID1 0 31 ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4 2 0x3e 4 0 4294967295 DESCRIPTION0 0 7 DESCRIPTION1 8 15 DESCRIPTION2 16 23 DESCRIPTION3 24 31 ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5 2 0x3f 4 0 4294967295 DESCRIPTION4 0 7 DESCRIPTION5 8 15 DESCRIPTION6 16 23 DESCRIPTION7 24 31 ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6 2 0x40 4 0 4294967295 DESCRIPTION8 0 7 DESCRIPTION9 8 15 DESCRIPTION10 16 23 DESCRIPTION11 24 31 ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7 2 0x41 4 0 4294967295 DESCRIPTION12 0 7 DESCRIPTION13 8 15 DESCRIPTION14 16 23 DESCRIPTION15 24 31 ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8 2 0x42 2 0 4294967295 DESCRIPTION16 0 7 DESCRIPTION17 8 15 ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL 2 0x54 3 0 4294967295 CLOCK_GATING_DISABLE 0 0 CLOCK_ON_STATE 4 4 AUDIO_ENABLED 31 31 ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 2 0x55 2 0 4294967295 UNSOLICITED_RESPONSE_PAYLOAD 0 25 UNSOLICITED_RESPONSE_FORCE 28 28 ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 2 0x56 8 0 4294967295 SEQUENCE 0 3 DEFAULT_ASSOCIATION 4 7 MISC 8 11 COLOR 12 15 CONNECTION_TYPE 16 19 DEFAULT_DEVICE 20 23 LOCATION 24 29 PORT_CONNECTIVITY 30 31 ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2 2 0x57 12 0 4294967295 MULTICHANNEL1_ENABLE 0 0 MULTICHANNEL1_MUTE 1 1 MULTICHANNEL1_CHANNEL_ID 4 7 MULTICHANNEL3_ENABLE 8 8 MULTICHANNEL3_MUTE 9 9 MULTICHANNEL3_CHANNEL_ID 12 15 MULTICHANNEL5_ENABLE 16 16 MULTICHANNEL5_MUTE 17 17 MULTICHANNEL5_CHANNEL_ID 20 23 MULTICHANNEL7_ENABLE 24 24 MULTICHANNEL7_MUTE 25 25 MULTICHANNEL7_CHANNEL_ID 28 31 ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE 2 0x58 1 0 4294967295 MULTICHANNEL_MODE 0 0 ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0 2 0x59 2 0 4294967295 IEC_60958_CS_MODE 0 1 IEC_60958_CS_SOURCE_NUMBER 2 5 ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1 2 0x5a 4 0 4294967295 IEC_60958_CS_CLOCK_ACCURACY 0 1 IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN 2 2 IEC_60958_CS_WORD_LENGTH 3 6 IEC_60958_CS_WORD_LENGTH_OVRRD_EN 7 7 ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2 2 0x5b 2 0 4294967295 IEC_60958_CS_SAMPLING_FREQUENCY 0 5 IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN 6 6 ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3 2 0x5c 2 0 4294967295 IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY 0 3 IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN 4 4 ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4 2 0x5d 4 0 4294967295 IEC_60958_CS_SAMPLING_FREQUENCY_COEFF 0 3 IEC_60958_CS_MPEG_SURROUND_INFO 4 4 IEC_60958_CS_CGMS_A 5 6 IEC_60958_CS_CGMS_A_VALID 7 7 ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5 2 0x5e 2 0 4294967295 IEC_60958_CS_CHANNEL_NUMBER_L 0 3 IEC_60958_CS_CHANNEL_NUMBER_R 4 7 ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6 2 0x5f 2 0 4294967295 IEC_60958_CS_CHANNEL_NUMBER_2 0 3 IEC_60958_CS_CHANNEL_NUMBER_3 4 7 ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7 2 0x60 2 0 4294967295 IEC_60958_CS_CHANNEL_NUMBER_4 0 3 IEC_60958_CS_CHANNEL_NUMBER_5 4 7 ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8 2 0x61 2 0 4294967295 IEC_60958_CS_CHANNEL_NUMBER_6 0 3 IEC_60958_CS_CHANNEL_NUMBER_7 4 7 ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO 2 0x62 1 0 4294967295 ASSOCIATION_INFO 0 31 ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS 2 0x63 1 0 4294967295 OUTPUT_ACTIVE 0 0 ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 2 0x64 2 0 4294967295 LPIB_SNAPSHOT_LOCK 0 0 CYCLIC_BUFFER_WRAP_COUNT 8 15 ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB 2 0x65 1 0 4294967295 LPIB 0 31 ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 2 0x66 1 0 4294967295 LPIB_TIMER_SNAPSHOT 0 31 ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE 2 0x67 1 0 4294967295 CODING_TYPE 0 7 ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED 2 0x68 4 0 4294967295 FORMAT_CHANGED 0 0 FORMAT_CHANGED_ACK_UR_ENABLE 1 1 FORMAT_CHANGE_REASON 8 15 FORMAT_CHANGE_RESPONSE 16 23 ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION 2 0x69 1 0 4294967295 WIRELESS_DISPLAY_IDENTIFICATION 0 1 ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE 2 0x6a 2 0 4294967295 REMOTE_KEEP_ALIVE_ENABLE 0 0 REMOTE_KEEP_ALIVE_CAPABILITY 4 4 ixAZF0ENDPOINT1_AZALIA_F0_AUDIO_ENABLE_STATUS 2 0x6b 1 0 4294967295 AUDIO_ENABLE_STATUS 0 0 ixAZF0ENDPOINT1_AZALIA_F0_AUDIO_ENABLED_INT_STATUS 2 0x6c 3 0 4294967295 AUDIO_ENABLED_FLAG 0 0 AUDIO_ENABLED_MASK 4 4 AUDIO_ENABLED_TYPE 8 8 ixAZF0ENDPOINT1_AZALIA_F0_AUDIO_DISABLED_INT_STATUS 2 0x6d 3 0 4294967295 AUDIO_DISABLED_FLAG 0 0 AUDIO_DISABLED_MASK 4 4 AUDIO_DISABLED_TYPE 8 8 ixAZF0ENDPOINT1_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS 2 0x6e 3 0 4294967295 AUDIO_FORMAT_CHANGED_FLAG 0 0 AUDIO_FORMAT_CHANGED_MASK 4 4 AUDIO_FORMAT_CHANGED_TYPE 8 8 ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 2 0x1 14 0 4294967295 AUDIO_CHANNEL_CAPABILITIES 0 0 INPUT_AMPLIFIER_PRESENT 1 1 OUTPUT_AMPLIFIER_PRESENT 2 2 AMPLIFIER_PARAMETER_OVERRIDE 3 3 FORMAT_OVERRIDE 4 4 STRIPE 5 5 PROCESSING_WIDGET 6 6 UNSOLICITED_RESPONSE_CAPABILITY 7 7 CONNECTION_LIST 8 8 DIGITAL 9 9 POWER_CONTROL 10 10 LR_SWAP 11 11 AUDIO_WIDGET_CAPABILITIES_DELAY 16 19 TYPE 20 23 ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT 2 0x2 6 0 4294967295 NUMBER_OF_CHANNELS 0 3 BITS_PER_SAMPLE 4 6 SAMPLE_BASE_DIVISOR 8 10 SAMPLE_BASE_MULTIPLE 11 13 SAMPLE_BASE_RATE 14 14 STREAM_TYPE 15 15 ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID 2 0x3 2 0 4294967295 CHANNEL_ID 0 3 STREAM_ID 4 7 ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER 2 0x4 10 0 4294967295 DIGEN 0 0 V 1 1 VCFG 2 2 PRE 3 3 COPY 4 4 NON_AUDIO 5 5 PRO 6 6 L 7 7 CC 8 14 KEEPALIVE 23 23 ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS 2 0x5 1 0 4294967295 STREAM_FORMATS 0 31 ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 2 0x6 2 0 4294967295 AUDIO_RATE_CAPABILITIES 0 11 AUDIO_BIT_CAPABILITIES 16 20 ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL 2 0x7 2 0 4294967295 STRIPE_CONTROL 0 1 STRIPE_CAPABILITY 20 22 ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE 2 0x8 1 0 4294967295 RAMP_RATE 0 7 ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING 2 0x9 4 0 4294967295 PRESENTATION_TIME_EMBEDDING_ENABLE 0 0 PRESENTATION_TIME_OFFSET_CHANGED 1 1 CLEAR_GTC_COUNTER_MIN_MAX_DELTA 2 2 PRESENTATION_TIME_EMBEDDING_GROUP 4 6 ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA 2 0xc 1 0 4294967295 GTC_COUNTER_DELTA 0 31 ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN 2 0xd 1 0 4294967295 GTC_COUNTER_DELTA_MIN 0 31 ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX 2 0xe 1 0 4294967295 GTC_COUNTER_DELTA_MAX 0 31 ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 2 0x20 13 0 4294967295 AUDIO_CHANNEL_CAPABILITIES 0 0 INPUT_AMPLIFIER_PRESENT 1 1 OUTPUT_AMPLIFIER_PRESENT 2 2 AMPLIFIER_PARAMETER_OVERRIDE 3 3 STRIPE 5 5 PROCESSING_WIDGET 6 6 UNSOLICITED_RESPONSE_CAPABILITY 7 7 CONNECTION_LIST 8 8 DIGITAL 9 9 POWER_CONTROL 10 10 LR_SWAP 11 11 AUDIO_WIDGET_CAPABILITIES_DELAY 16 19 TYPE 20 23 ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES 2 0x21 11 0 4294967295 IMPEDANCE_SENSE_CAPABLE 0 0 TRIGGER_REQUIRED 1 1 JACK_DETECTION_CAPABILITY 2 2 HEADPHONE_DRIVE_CAPABLE 3 3 OUTPUT_CAPABLE 4 4 INPUT_CAPABLE 5 5 BALANCED_I_O_PINS 6 6 HDMI 7 7 VREF_CONTROL 8 15 EAPD_CAPABLE 16 16 DP 24 24 ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE 2 0x22 2 0 4294967295 TAG 0 5 ENABLE 7 7 ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE 2 0x23 1 0 4294967295 IMPEDANCE_SENSE 0 30 ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL 2 0x24 1 0 4294967295 OUT_ENABLE 6 6 ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER 2 0x25 8 0 4294967295 SPEAKER_ALLOCATION 0 6 CHANNEL_ALLOCATION 8 15 HDMI_CONNECTION 16 16 DP_CONNECTION 17 17 EXTRA_CONNECTION_INFO 18 23 LFE_PLAYBACK_LEVEL 24 25 LEVEL_SHIFT 27 30 DOWN_MIX_INHIBIT 31 31 ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 2 0x28 4 0 4294967295 MAX_CHANNELS 0 2 SUPPORTED_FREQUENCIES 8 15 DESCRIPTOR_BYTE_2 16 23 SUPPORTED_FREQUENCIES_STEREO 24 31 ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 2 0x29 3 0 4294967295 MAX_CHANNELS 0 2 SUPPORTED_FREQUENCIES 8 15 DESCRIPTOR_BYTE_2 16 23 ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 2 0x2a 3 0 4294967295 MAX_CHANNELS 0 2 SUPPORTED_FREQUENCIES 8 15 DESCRIPTOR_BYTE_2 16 23 ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 2 0x2b 3 0 4294967295 MAX_CHANNELS 0 2 SUPPORTED_FREQUENCIES 8 15 DESCRIPTOR_BYTE_2 16 23 ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 2 0x2c 3 0 4294967295 MAX_CHANNELS 0 2 SUPPORTED_FREQUENCIES 8 15 DESCRIPTOR_BYTE_2 16 23 ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 2 0x2d 3 0 4294967295 MAX_CHANNELS 0 2 SUPPORTED_FREQUENCIES 8 15 DESCRIPTOR_BYTE_2 16 23 ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 2 0x2e 3 0 4294967295 MAX_CHANNELS 0 2 SUPPORTED_FREQUENCIES 8 15 DESCRIPTOR_BYTE_2 16 23 ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 2 0x2f 3 0 4294967295 MAX_CHANNELS 0 2 SUPPORTED_FREQUENCIES 8 15 DESCRIPTOR_BYTE_2 16 23 ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 2 0x30 3 0 4294967295 MAX_CHANNELS 0 2 SUPPORTED_FREQUENCIES 8 15 DESCRIPTOR_BYTE_2 16 23 ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 2 0x31 3 0 4294967295 MAX_CHANNELS 0 2 SUPPORTED_FREQUENCIES 8 15 DESCRIPTOR_BYTE_2 16 23 ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 2 0x32 3 0 4294967295 MAX_CHANNELS 0 2 SUPPORTED_FREQUENCIES 8 15 DESCRIPTOR_BYTE_2 16 23 ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 2 0x33 3 0 4294967295 MAX_CHANNELS 0 2 SUPPORTED_FREQUENCIES 8 15 DESCRIPTOR_BYTE_2 16 23 ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 2 0x34 3 0 4294967295 MAX_CHANNELS 0 2 SUPPORTED_FREQUENCIES 8 15 DESCRIPTOR_BYTE_2 16 23 ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 2 0x35 3 0 4294967295 MAX_CHANNELS 0 2 SUPPORTED_FREQUENCIES 8 15 DESCRIPTOR_BYTE_2 16 23 ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE 2 0x36 12 0 4294967295 MULTICHANNEL01_ENABLE 0 0 MULTICHANNEL01_MUTE 1 1 MULTICHANNEL01_CHANNEL_ID 4 7 MULTICHANNEL23_ENABLE 8 8 MULTICHANNEL23_MUTE 9 9 MULTICHANNEL23_CHANNEL_ID 12 15 MULTICHANNEL45_ENABLE 16 16 MULTICHANNEL45_MUTE 17 17 MULTICHANNEL45_CHANNEL_ID 20 23 MULTICHANNEL67_ENABLE 24 24 MULTICHANNEL67_MUTE 25 25 MULTICHANNEL67_CHANNEL_ID 28 31 ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC 2 0x37 2 0 4294967295 VIDEO_LIPSYNC 0 7 AUDIO_LIPSYNC 8 15 ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR 2 0x38 2 0 4294967295 HBR_CAPABLE 0 0 HBR_ENABLE 4 4 ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0 2 0x3a 2 0 4294967295 MANUFACTURER_ID 0 15 PRODUCT_ID 16 31 ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1 2 0x3b 1 0 4294967295 SINK_DESCRIPTION_LEN 0 7 ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2 2 0x3c 1 0 4294967295 PORT_ID0 0 31 ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3 2 0x3d 1 0 4294967295 PORT_ID1 0 31 ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4 2 0x3e 4 0 4294967295 DESCRIPTION0 0 7 DESCRIPTION1 8 15 DESCRIPTION2 16 23 DESCRIPTION3 24 31 ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5 2 0x3f 4 0 4294967295 DESCRIPTION4 0 7 DESCRIPTION5 8 15 DESCRIPTION6 16 23 DESCRIPTION7 24 31 ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6 2 0x40 4 0 4294967295 DESCRIPTION8 0 7 DESCRIPTION9 8 15 DESCRIPTION10 16 23 DESCRIPTION11 24 31 ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7 2 0x41 4 0 4294967295 DESCRIPTION12 0 7 DESCRIPTION13 8 15 DESCRIPTION14 16 23 DESCRIPTION15 24 31 ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8 2 0x42 2 0 4294967295 DESCRIPTION16 0 7 DESCRIPTION17 8 15 ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL 2 0x54 3 0 4294967295 CLOCK_GATING_DISABLE 0 0 CLOCK_ON_STATE 4 4 AUDIO_ENABLED 31 31 ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 2 0x55 2 0 4294967295 UNSOLICITED_RESPONSE_PAYLOAD 0 25 UNSOLICITED_RESPONSE_FORCE 28 28 ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 2 0x56 8 0 4294967295 SEQUENCE 0 3 DEFAULT_ASSOCIATION 4 7 MISC 8 11 COLOR 12 15 CONNECTION_TYPE 16 19 DEFAULT_DEVICE 20 23 LOCATION 24 29 PORT_CONNECTIVITY 30 31 ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2 2 0x57 12 0 4294967295 MULTICHANNEL1_ENABLE 0 0 MULTICHANNEL1_MUTE 1 1 MULTICHANNEL1_CHANNEL_ID 4 7 MULTICHANNEL3_ENABLE 8 8 MULTICHANNEL3_MUTE 9 9 MULTICHANNEL3_CHANNEL_ID 12 15 MULTICHANNEL5_ENABLE 16 16 MULTICHANNEL5_MUTE 17 17 MULTICHANNEL5_CHANNEL_ID 20 23 MULTICHANNEL7_ENABLE 24 24 MULTICHANNEL7_MUTE 25 25 MULTICHANNEL7_CHANNEL_ID 28 31 ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE 2 0x58 1 0 4294967295 MULTICHANNEL_MODE 0 0 ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0 2 0x59 2 0 4294967295 IEC_60958_CS_MODE 0 1 IEC_60958_CS_SOURCE_NUMBER 2 5 ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1 2 0x5a 4 0 4294967295 IEC_60958_CS_CLOCK_ACCURACY 0 1 IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN 2 2 IEC_60958_CS_WORD_LENGTH 3 6 IEC_60958_CS_WORD_LENGTH_OVRRD_EN 7 7 ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2 2 0x5b 2 0 4294967295 IEC_60958_CS_SAMPLING_FREQUENCY 0 5 IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN 6 6 ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3 2 0x5c 2 0 4294967295 IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY 0 3 IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN 4 4 ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4 2 0x5d 4 0 4294967295 IEC_60958_CS_SAMPLING_FREQUENCY_COEFF 0 3 IEC_60958_CS_MPEG_SURROUND_INFO 4 4 IEC_60958_CS_CGMS_A 5 6 IEC_60958_CS_CGMS_A_VALID 7 7 ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5 2 0x5e 2 0 4294967295 IEC_60958_CS_CHANNEL_NUMBER_L 0 3 IEC_60958_CS_CHANNEL_NUMBER_R 4 7 ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6 2 0x5f 2 0 4294967295 IEC_60958_CS_CHANNEL_NUMBER_2 0 3 IEC_60958_CS_CHANNEL_NUMBER_3 4 7 ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7 2 0x60 2 0 4294967295 IEC_60958_CS_CHANNEL_NUMBER_4 0 3 IEC_60958_CS_CHANNEL_NUMBER_5 4 7 ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8 2 0x61 2 0 4294967295 IEC_60958_CS_CHANNEL_NUMBER_6 0 3 IEC_60958_CS_CHANNEL_NUMBER_7 4 7 ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO 2 0x62 1 0 4294967295 ASSOCIATION_INFO 0 31 ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS 2 0x63 1 0 4294967295 OUTPUT_ACTIVE 0 0 ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 2 0x64 2 0 4294967295 LPIB_SNAPSHOT_LOCK 0 0 CYCLIC_BUFFER_WRAP_COUNT 8 15 ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB 2 0x65 1 0 4294967295 LPIB 0 31 ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 2 0x66 1 0 4294967295 LPIB_TIMER_SNAPSHOT 0 31 ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE 2 0x67 1 0 4294967295 CODING_TYPE 0 7 ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED 2 0x68 4 0 4294967295 FORMAT_CHANGED 0 0 FORMAT_CHANGED_ACK_UR_ENABLE 1 1 FORMAT_CHANGE_REASON 8 15 FORMAT_CHANGE_RESPONSE 16 23 ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION 2 0x69 1 0 4294967295 WIRELESS_DISPLAY_IDENTIFICATION 0 1 ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE 2 0x6a 2 0 4294967295 REMOTE_KEEP_ALIVE_ENABLE 0 0 REMOTE_KEEP_ALIVE_CAPABILITY 4 4 ixAZF0ENDPOINT2_AZALIA_F0_AUDIO_ENABLE_STATUS 2 0x6b 1 0 4294967295 AUDIO_ENABLE_STATUS 0 0 ixAZF0ENDPOINT2_AZALIA_F0_AUDIO_ENABLED_INT_STATUS 2 0x6c 3 0 4294967295 AUDIO_ENABLED_FLAG 0 0 AUDIO_ENABLED_MASK 4 4 AUDIO_ENABLED_TYPE 8 8 ixAZF0ENDPOINT2_AZALIA_F0_AUDIO_DISABLED_INT_STATUS 2 0x6d 3 0 4294967295 AUDIO_DISABLED_FLAG 0 0 AUDIO_DISABLED_MASK 4 4 AUDIO_DISABLED_TYPE 8 8 ixAZF0ENDPOINT2_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS 2 0x6e 3 0 4294967295 AUDIO_FORMAT_CHANGED_FLAG 0 0 AUDIO_FORMAT_CHANGED_MASK 4 4 AUDIO_FORMAT_CHANGED_TYPE 8 8 ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 2 0x1 14 0 4294967295 AUDIO_CHANNEL_CAPABILITIES 0 0 INPUT_AMPLIFIER_PRESENT 1 1 OUTPUT_AMPLIFIER_PRESENT 2 2 AMPLIFIER_PARAMETER_OVERRIDE 3 3 FORMAT_OVERRIDE 4 4 STRIPE 5 5 PROCESSING_WIDGET 6 6 UNSOLICITED_RESPONSE_CAPABILITY 7 7 CONNECTION_LIST 8 8 DIGITAL 9 9 POWER_CONTROL 10 10 LR_SWAP 11 11 AUDIO_WIDGET_CAPABILITIES_DELAY 16 19 TYPE 20 23 ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT 2 0x2 6 0 4294967295 NUMBER_OF_CHANNELS 0 3 BITS_PER_SAMPLE 4 6 SAMPLE_BASE_DIVISOR 8 10 SAMPLE_BASE_MULTIPLE 11 13 SAMPLE_BASE_RATE 14 14 STREAM_TYPE 15 15 ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID 2 0x3 2 0 4294967295 CHANNEL_ID 0 3 STREAM_ID 4 7 ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER 2 0x4 10 0 4294967295 DIGEN 0 0 V 1 1 VCFG 2 2 PRE 3 3 COPY 4 4 NON_AUDIO 5 5 PRO 6 6 L 7 7 CC 8 14 KEEPALIVE 23 23 ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS 2 0x5 1 0 4294967295 STREAM_FORMATS 0 31 ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 2 0x6 2 0 4294967295 AUDIO_RATE_CAPABILITIES 0 11 AUDIO_BIT_CAPABILITIES 16 20 ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL 2 0x7 2 0 4294967295 STRIPE_CONTROL 0 1 STRIPE_CAPABILITY 20 22 ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE 2 0x8 1 0 4294967295 RAMP_RATE 0 7 ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING 2 0x9 4 0 4294967295 PRESENTATION_TIME_EMBEDDING_ENABLE 0 0 PRESENTATION_TIME_OFFSET_CHANGED 1 1 CLEAR_GTC_COUNTER_MIN_MAX_DELTA 2 2 PRESENTATION_TIME_EMBEDDING_GROUP 4 6 ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA 2 0xc 1 0 4294967295 GTC_COUNTER_DELTA 0 31 ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN 2 0xd 1 0 4294967295 GTC_COUNTER_DELTA_MIN 0 31 ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX 2 0xe 1 0 4294967295 GTC_COUNTER_DELTA_MAX 0 31 ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 2 0x20 13 0 4294967295 AUDIO_CHANNEL_CAPABILITIES 0 0 INPUT_AMPLIFIER_PRESENT 1 1 OUTPUT_AMPLIFIER_PRESENT 2 2 AMPLIFIER_PARAMETER_OVERRIDE 3 3 STRIPE 5 5 PROCESSING_WIDGET 6 6 UNSOLICITED_RESPONSE_CAPABILITY 7 7 CONNECTION_LIST 8 8 DIGITAL 9 9 POWER_CONTROL 10 10 LR_SWAP 11 11 AUDIO_WIDGET_CAPABILITIES_DELAY 16 19 TYPE 20 23 ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES 2 0x21 11 0 4294967295 IMPEDANCE_SENSE_CAPABLE 0 0 TRIGGER_REQUIRED 1 1 JACK_DETECTION_CAPABILITY 2 2 HEADPHONE_DRIVE_CAPABLE 3 3 OUTPUT_CAPABLE 4 4 INPUT_CAPABLE 5 5 BALANCED_I_O_PINS 6 6 HDMI 7 7 VREF_CONTROL 8 15 EAPD_CAPABLE 16 16 DP 24 24 ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE 2 0x22 2 0 4294967295 TAG 0 5 ENABLE 7 7 ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE 2 0x23 1 0 4294967295 IMPEDANCE_SENSE 0 30 ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL 2 0x24 1 0 4294967295 OUT_ENABLE 6 6 ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER 2 0x25 8 0 4294967295 SPEAKER_ALLOCATION 0 6 CHANNEL_ALLOCATION 8 15 HDMI_CONNECTION 16 16 DP_CONNECTION 17 17 EXTRA_CONNECTION_INFO 18 23 LFE_PLAYBACK_LEVEL 24 25 LEVEL_SHIFT 27 30 DOWN_MIX_INHIBIT 31 31 ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 2 0x28 4 0 4294967295 MAX_CHANNELS 0 2 SUPPORTED_FREQUENCIES 8 15 DESCRIPTOR_BYTE_2 16 23 SUPPORTED_FREQUENCIES_STEREO 24 31 ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 2 0x29 3 0 4294967295 MAX_CHANNELS 0 2 SUPPORTED_FREQUENCIES 8 15 DESCRIPTOR_BYTE_2 16 23 ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 2 0x2a 3 0 4294967295 MAX_CHANNELS 0 2 SUPPORTED_FREQUENCIES 8 15 DESCRIPTOR_BYTE_2 16 23 ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 2 0x2b 3 0 4294967295 MAX_CHANNELS 0 2 SUPPORTED_FREQUENCIES 8 15 DESCRIPTOR_BYTE_2 16 23 ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 2 0x2c 3 0 4294967295 MAX_CHANNELS 0 2 SUPPORTED_FREQUENCIES 8 15 DESCRIPTOR_BYTE_2 16 23 ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 2 0x2d 3 0 4294967295 MAX_CHANNELS 0 2 SUPPORTED_FREQUENCIES 8 15 DESCRIPTOR_BYTE_2 16 23 ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 2 0x2e 3 0 4294967295 MAX_CHANNELS 0 2 SUPPORTED_FREQUENCIES 8 15 DESCRIPTOR_BYTE_2 16 23 ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 2 0x2f 3 0 4294967295 MAX_CHANNELS 0 2 SUPPORTED_FREQUENCIES 8 15 DESCRIPTOR_BYTE_2 16 23 ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 2 0x30 3 0 4294967295 MAX_CHANNELS 0 2 SUPPORTED_FREQUENCIES 8 15 DESCRIPTOR_BYTE_2 16 23 ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 2 0x31 3 0 4294967295 MAX_CHANNELS 0 2 SUPPORTED_FREQUENCIES 8 15 DESCRIPTOR_BYTE_2 16 23 ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 2 0x32 3 0 4294967295 MAX_CHANNELS 0 2 SUPPORTED_FREQUENCIES 8 15 DESCRIPTOR_BYTE_2 16 23 ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 2 0x33 3 0 4294967295 MAX_CHANNELS 0 2 SUPPORTED_FREQUENCIES 8 15 DESCRIPTOR_BYTE_2 16 23 ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 2 0x34 3 0 4294967295 MAX_CHANNELS 0 2 SUPPORTED_FREQUENCIES 8 15 DESCRIPTOR_BYTE_2 16 23 ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 2 0x35 3 0 4294967295 MAX_CHANNELS 0 2 SUPPORTED_FREQUENCIES 8 15 DESCRIPTOR_BYTE_2 16 23 ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE 2 0x36 12 0 4294967295 MULTICHANNEL01_ENABLE 0 0 MULTICHANNEL01_MUTE 1 1 MULTICHANNEL01_CHANNEL_ID 4 7 MULTICHANNEL23_ENABLE 8 8 MULTICHANNEL23_MUTE 9 9 MULTICHANNEL23_CHANNEL_ID 12 15 MULTICHANNEL45_ENABLE 16 16 MULTICHANNEL45_MUTE 17 17 MULTICHANNEL45_CHANNEL_ID 20 23 MULTICHANNEL67_ENABLE 24 24 MULTICHANNEL67_MUTE 25 25 MULTICHANNEL67_CHANNEL_ID 28 31 ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC 2 0x37 2 0 4294967295 VIDEO_LIPSYNC 0 7 AUDIO_LIPSYNC 8 15 ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR 2 0x38 2 0 4294967295 HBR_CAPABLE 0 0 HBR_ENABLE 4 4 ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0 2 0x3a 2 0 4294967295 MANUFACTURER_ID 0 15 PRODUCT_ID 16 31 ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1 2 0x3b 1 0 4294967295 SINK_DESCRIPTION_LEN 0 7 ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2 2 0x3c 1 0 4294967295 PORT_ID0 0 31 ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3 2 0x3d 1 0 4294967295 PORT_ID1 0 31 ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4 2 0x3e 4 0 4294967295 DESCRIPTION0 0 7 DESCRIPTION1 8 15 DESCRIPTION2 16 23 DESCRIPTION3 24 31 ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5 2 0x3f 4 0 4294967295 DESCRIPTION4 0 7 DESCRIPTION5 8 15 DESCRIPTION6 16 23 DESCRIPTION7 24 31 ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6 2 0x40 4 0 4294967295 DESCRIPTION8 0 7 DESCRIPTION9 8 15 DESCRIPTION10 16 23 DESCRIPTION11 24 31 ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7 2 0x41 4 0 4294967295 DESCRIPTION12 0 7 DESCRIPTION13 8 15 DESCRIPTION14 16 23 DESCRIPTION15 24 31 ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8 2 0x42 2 0 4294967295 DESCRIPTION16 0 7 DESCRIPTION17 8 15 ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL 2 0x54 3 0 4294967295 CLOCK_GATING_DISABLE 0 0 CLOCK_ON_STATE 4 4 AUDIO_ENABLED 31 31 ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 2 0x55 2 0 4294967295 UNSOLICITED_RESPONSE_PAYLOAD 0 25 UNSOLICITED_RESPONSE_FORCE 28 28 ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 2 0x56 8 0 4294967295 SEQUENCE 0 3 DEFAULT_ASSOCIATION 4 7 MISC 8 11 COLOR 12 15 CONNECTION_TYPE 16 19 DEFAULT_DEVICE 20 23 LOCATION 24 29 PORT_CONNECTIVITY 30 31 ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2 2 0x57 12 0 4294967295 MULTICHANNEL1_ENABLE 0 0 MULTICHANNEL1_MUTE 1 1 MULTICHANNEL1_CHANNEL_ID 4 7 MULTICHANNEL3_ENABLE 8 8 MULTICHANNEL3_MUTE 9 9 MULTICHANNEL3_CHANNEL_ID 12 15 MULTICHANNEL5_ENABLE 16 16 MULTICHANNEL5_MUTE 17 17 MULTICHANNEL5_CHANNEL_ID 20 23 MULTICHANNEL7_ENABLE 24 24 MULTICHANNEL7_MUTE 25 25 MULTICHANNEL7_CHANNEL_ID 28 31 ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE 2 0x58 1 0 4294967295 MULTICHANNEL_MODE 0 0 ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0 2 0x59 2 0 4294967295 IEC_60958_CS_MODE 0 1 IEC_60958_CS_SOURCE_NUMBER 2 5 ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1 2 0x5a 4 0 4294967295 IEC_60958_CS_CLOCK_ACCURACY 0 1 IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN 2 2 IEC_60958_CS_WORD_LENGTH 3 6 IEC_60958_CS_WORD_LENGTH_OVRRD_EN 7 7 ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2 2 0x5b 2 0 4294967295 IEC_60958_CS_SAMPLING_FREQUENCY 0 5 IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN 6 6 ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3 2 0x5c 2 0 4294967295 IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY 0 3 IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN 4 4 ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4 2 0x5d 4 0 4294967295 IEC_60958_CS_SAMPLING_FREQUENCY_COEFF 0 3 IEC_60958_CS_MPEG_SURROUND_INFO 4 4 IEC_60958_CS_CGMS_A 5 6 IEC_60958_CS_CGMS_A_VALID 7 7 ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5 2 0x5e 2 0 4294967295 IEC_60958_CS_CHANNEL_NUMBER_L 0 3 IEC_60958_CS_CHANNEL_NUMBER_R 4 7 ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6 2 0x5f 2 0 4294967295 IEC_60958_CS_CHANNEL_NUMBER_2 0 3 IEC_60958_CS_CHANNEL_NUMBER_3 4 7 ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7 2 0x60 2 0 4294967295 IEC_60958_CS_CHANNEL_NUMBER_4 0 3 IEC_60958_CS_CHANNEL_NUMBER_5 4 7 ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8 2 0x61 2 0 4294967295 IEC_60958_CS_CHANNEL_NUMBER_6 0 3 IEC_60958_CS_CHANNEL_NUMBER_7 4 7 ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO 2 0x62 1 0 4294967295 ASSOCIATION_INFO 0 31 ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS 2 0x63 1 0 4294967295 OUTPUT_ACTIVE 0 0 ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 2 0x64 2 0 4294967295 LPIB_SNAPSHOT_LOCK 0 0 CYCLIC_BUFFER_WRAP_COUNT 8 15 ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB 2 0x65 1 0 4294967295 LPIB 0 31 ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 2 0x66 1 0 4294967295 LPIB_TIMER_SNAPSHOT 0 31 ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE 2 0x67 1 0 4294967295 CODING_TYPE 0 7 ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED 2 0x68 4 0 4294967295 FORMAT_CHANGED 0 0 FORMAT_CHANGED_ACK_UR_ENABLE 1 1 FORMAT_CHANGE_REASON 8 15 FORMAT_CHANGE_RESPONSE 16 23 ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION 2 0x69 1 0 4294967295 WIRELESS_DISPLAY_IDENTIFICATION 0 1 ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE 2 0x6a 2 0 4294967295 REMOTE_KEEP_ALIVE_ENABLE 0 0 REMOTE_KEEP_ALIVE_CAPABILITY 4 4 ixAZF0ENDPOINT3_AZALIA_F0_AUDIO_ENABLE_STATUS 2 0x6b 1 0 4294967295 AUDIO_ENABLE_STATUS 0 0 ixAZF0ENDPOINT3_AZALIA_F0_AUDIO_ENABLED_INT_STATUS 2 0x6c 3 0 4294967295 AUDIO_ENABLED_FLAG 0 0 AUDIO_ENABLED_MASK 4 4 AUDIO_ENABLED_TYPE 8 8 ixAZF0ENDPOINT3_AZALIA_F0_AUDIO_DISABLED_INT_STATUS 2 0x6d 3 0 4294967295 AUDIO_DISABLED_FLAG 0 0 AUDIO_DISABLED_MASK 4 4 AUDIO_DISABLED_TYPE 8 8 ixAZF0ENDPOINT3_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS 2 0x6e 3 0 4294967295 AUDIO_FORMAT_CHANGED_FLAG 0 0 AUDIO_FORMAT_CHANGED_MASK 4 4 AUDIO_FORMAT_CHANGED_TYPE 8 8 ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 2 0x1 14 0 4294967295 AUDIO_CHANNEL_CAPABILITIES 0 0 INPUT_AMPLIFIER_PRESENT 1 1 OUTPUT_AMPLIFIER_PRESENT 2 2 AMPLIFIER_PARAMETER_OVERRIDE 3 3 FORMAT_OVERRIDE 4 4 STRIPE 5 5 PROCESSING_WIDGET 6 6 UNSOLICITED_RESPONSE_CAPABILITY 7 7 CONNECTION_LIST 8 8 DIGITAL 9 9 POWER_CONTROL 10 10 LR_SWAP 11 11 AUDIO_WIDGET_CAPABILITIES_DELAY 16 19 TYPE 20 23 ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT 2 0x2 6 0 4294967295 NUMBER_OF_CHANNELS 0 3 BITS_PER_SAMPLE 4 6 SAMPLE_BASE_DIVISOR 8 10 SAMPLE_BASE_MULTIPLE 11 13 SAMPLE_BASE_RATE 14 14 STREAM_TYPE 15 15 ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID 2 0x3 2 0 4294967295 CHANNEL_ID 0 3 STREAM_ID 4 7 ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER 2 0x4 10 0 4294967295 DIGEN 0 0 V 1 1 VCFG 2 2 PRE 3 3 COPY 4 4 NON_AUDIO 5 5 PRO 6 6 L 7 7 CC 8 14 KEEPALIVE 23 23 ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS 2 0x5 1 0 4294967295 STREAM_FORMATS 0 31 ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 2 0x6 2 0 4294967295 AUDIO_RATE_CAPABILITIES 0 11 AUDIO_BIT_CAPABILITIES 16 20 ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL 2 0x7 2 0 4294967295 STRIPE_CONTROL 0 1 STRIPE_CAPABILITY 20 22 ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE 2 0x8 1 0 4294967295 RAMP_RATE 0 7 ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING 2 0x9 4 0 4294967295 PRESENTATION_TIME_EMBEDDING_ENABLE 0 0 PRESENTATION_TIME_OFFSET_CHANGED 1 1 CLEAR_GTC_COUNTER_MIN_MAX_DELTA 2 2 PRESENTATION_TIME_EMBEDDING_GROUP 4 6 ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA 2 0xc 1 0 4294967295 GTC_COUNTER_DELTA 0 31 ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN 2 0xd 1 0 4294967295 GTC_COUNTER_DELTA_MIN 0 31 ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX 2 0xe 1 0 4294967295 GTC_COUNTER_DELTA_MAX 0 31 ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 2 0x20 13 0 4294967295 AUDIO_CHANNEL_CAPABILITIES 0 0 INPUT_AMPLIFIER_PRESENT 1 1 OUTPUT_AMPLIFIER_PRESENT 2 2 AMPLIFIER_PARAMETER_OVERRIDE 3 3 STRIPE 5 5 PROCESSING_WIDGET 6 6 UNSOLICITED_RESPONSE_CAPABILITY 7 7 CONNECTION_LIST 8 8 DIGITAL 9 9 POWER_CONTROL 10 10 LR_SWAP 11 11 AUDIO_WIDGET_CAPABILITIES_DELAY 16 19 TYPE 20 23 ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES 2 0x21 11 0 4294967295 IMPEDANCE_SENSE_CAPABLE 0 0 TRIGGER_REQUIRED 1 1 JACK_DETECTION_CAPABILITY 2 2 HEADPHONE_DRIVE_CAPABLE 3 3 OUTPUT_CAPABLE 4 4 INPUT_CAPABLE 5 5 BALANCED_I_O_PINS 6 6 HDMI 7 7 VREF_CONTROL 8 15 EAPD_CAPABLE 16 16 DP 24 24 ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE 2 0x22 2 0 4294967295 TAG 0 5 ENABLE 7 7 ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE 2 0x23 1 0 4294967295 IMPEDANCE_SENSE 0 30 ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL 2 0x24 1 0 4294967295 OUT_ENABLE 6 6 ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER 2 0x25 8 0 4294967295 SPEAKER_ALLOCATION 0 6 CHANNEL_ALLOCATION 8 15 HDMI_CONNECTION 16 16 DP_CONNECTION 17 17 EXTRA_CONNECTION_INFO 18 23 LFE_PLAYBACK_LEVEL 24 25 LEVEL_SHIFT 27 30 DOWN_MIX_INHIBIT 31 31 ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 2 0x28 4 0 4294967295 MAX_CHANNELS 0 2 SUPPORTED_FREQUENCIES 8 15 DESCRIPTOR_BYTE_2 16 23 SUPPORTED_FREQUENCIES_STEREO 24 31 ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 2 0x29 3 0 4294967295 MAX_CHANNELS 0 2 SUPPORTED_FREQUENCIES 8 15 DESCRIPTOR_BYTE_2 16 23 ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 2 0x2a 3 0 4294967295 MAX_CHANNELS 0 2 SUPPORTED_FREQUENCIES 8 15 DESCRIPTOR_BYTE_2 16 23 ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 2 0x2b 3 0 4294967295 MAX_CHANNELS 0 2 SUPPORTED_FREQUENCIES 8 15 DESCRIPTOR_BYTE_2 16 23 ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 2 0x2c 3 0 4294967295 MAX_CHANNELS 0 2 SUPPORTED_FREQUENCIES 8 15 DESCRIPTOR_BYTE_2 16 23 ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 2 0x2d 3 0 4294967295 MAX_CHANNELS 0 2 SUPPORTED_FREQUENCIES 8 15 DESCRIPTOR_BYTE_2 16 23 ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 2 0x2e 3 0 4294967295 MAX_CHANNELS 0 2 SUPPORTED_FREQUENCIES 8 15 DESCRIPTOR_BYTE_2 16 23 ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 2 0x2f 3 0 4294967295 MAX_CHANNELS 0 2 SUPPORTED_FREQUENCIES 8 15 DESCRIPTOR_BYTE_2 16 23 ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 2 0x30 3 0 4294967295 MAX_CHANNELS 0 2 SUPPORTED_FREQUENCIES 8 15 DESCRIPTOR_BYTE_2 16 23 ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 2 0x31 3 0 4294967295 MAX_CHANNELS 0 2 SUPPORTED_FREQUENCIES 8 15 DESCRIPTOR_BYTE_2 16 23 ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 2 0x32 3 0 4294967295 MAX_CHANNELS 0 2 SUPPORTED_FREQUENCIES 8 15 DESCRIPTOR_BYTE_2 16 23 ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 2 0x33 3 0 4294967295 MAX_CHANNELS 0 2 SUPPORTED_FREQUENCIES 8 15 DESCRIPTOR_BYTE_2 16 23 ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 2 0x34 3 0 4294967295 MAX_CHANNELS 0 2 SUPPORTED_FREQUENCIES 8 15 DESCRIPTOR_BYTE_2 16 23 ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 2 0x35 3 0 4294967295 MAX_CHANNELS 0 2 SUPPORTED_FREQUENCIES 8 15 DESCRIPTOR_BYTE_2 16 23 ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE 2 0x36 12 0 4294967295 MULTICHANNEL01_ENABLE 0 0 MULTICHANNEL01_MUTE 1 1 MULTICHANNEL01_CHANNEL_ID 4 7 MULTICHANNEL23_ENABLE 8 8 MULTICHANNEL23_MUTE 9 9 MULTICHANNEL23_CHANNEL_ID 12 15 MULTICHANNEL45_ENABLE 16 16 MULTICHANNEL45_MUTE 17 17 MULTICHANNEL45_CHANNEL_ID 20 23 MULTICHANNEL67_ENABLE 24 24 MULTICHANNEL67_MUTE 25 25 MULTICHANNEL67_CHANNEL_ID 28 31 ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC 2 0x37 2 0 4294967295 VIDEO_LIPSYNC 0 7 AUDIO_LIPSYNC 8 15 ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR 2 0x38 2 0 4294967295 HBR_CAPABLE 0 0 HBR_ENABLE 4 4 ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0 2 0x3a 2 0 4294967295 MANUFACTURER_ID 0 15 PRODUCT_ID 16 31 ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1 2 0x3b 1 0 4294967295 SINK_DESCRIPTION_LEN 0 7 ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2 2 0x3c 1 0 4294967295 PORT_ID0 0 31 ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3 2 0x3d 1 0 4294967295 PORT_ID1 0 31 ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4 2 0x3e 4 0 4294967295 DESCRIPTION0 0 7 DESCRIPTION1 8 15 DESCRIPTION2 16 23 DESCRIPTION3 24 31 ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5 2 0x3f 4 0 4294967295 DESCRIPTION4 0 7 DESCRIPTION5 8 15 DESCRIPTION6 16 23 DESCRIPTION7 24 31 ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6 2 0x40 4 0 4294967295 DESCRIPTION8 0 7 DESCRIPTION9 8 15 DESCRIPTION10 16 23 DESCRIPTION11 24 31 ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7 2 0x41 4 0 4294967295 DESCRIPTION12 0 7 DESCRIPTION13 8 15 DESCRIPTION14 16 23 DESCRIPTION15 24 31 ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8 2 0x42 2 0 4294967295 DESCRIPTION16 0 7 DESCRIPTION17 8 15 ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL 2 0x54 3 0 4294967295 CLOCK_GATING_DISABLE 0 0 CLOCK_ON_STATE 4 4 AUDIO_ENABLED 31 31 ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 2 0x55 2 0 4294967295 UNSOLICITED_RESPONSE_PAYLOAD 0 25 UNSOLICITED_RESPONSE_FORCE 28 28 ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 2 0x56 8 0 4294967295 SEQUENCE 0 3 DEFAULT_ASSOCIATION 4 7 MISC 8 11 COLOR 12 15 CONNECTION_TYPE 16 19 DEFAULT_DEVICE 20 23 LOCATION 24 29 PORT_CONNECTIVITY 30 31 ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2 2 0x57 12 0 4294967295 MULTICHANNEL1_ENABLE 0 0 MULTICHANNEL1_MUTE 1 1 MULTICHANNEL1_CHANNEL_ID 4 7 MULTICHANNEL3_ENABLE 8 8 MULTICHANNEL3_MUTE 9 9 MULTICHANNEL3_CHANNEL_ID 12 15 MULTICHANNEL5_ENABLE 16 16 MULTICHANNEL5_MUTE 17 17 MULTICHANNEL5_CHANNEL_ID 20 23 MULTICHANNEL7_ENABLE 24 24 MULTICHANNEL7_MUTE 25 25 MULTICHANNEL7_CHANNEL_ID 28 31 ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE 2 0x58 1 0 4294967295 MULTICHANNEL_MODE 0 0 ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0 2 0x59 2 0 4294967295 IEC_60958_CS_MODE 0 1 IEC_60958_CS_SOURCE_NUMBER 2 5 ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1 2 0x5a 4 0 4294967295 IEC_60958_CS_CLOCK_ACCURACY 0 1 IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN 2 2 IEC_60958_CS_WORD_LENGTH 3 6 IEC_60958_CS_WORD_LENGTH_OVRRD_EN 7 7 ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2 2 0x5b 2 0 4294967295 IEC_60958_CS_SAMPLING_FREQUENCY 0 5 IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN 6 6 ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3 2 0x5c 2 0 4294967295 IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY 0 3 IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN 4 4 ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4 2 0x5d 4 0 4294967295 IEC_60958_CS_SAMPLING_FREQUENCY_COEFF 0 3 IEC_60958_CS_MPEG_SURROUND_INFO 4 4 IEC_60958_CS_CGMS_A 5 6 IEC_60958_CS_CGMS_A_VALID 7 7 ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5 2 0x5e 2 0 4294967295 IEC_60958_CS_CHANNEL_NUMBER_L 0 3 IEC_60958_CS_CHANNEL_NUMBER_R 4 7 ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6 2 0x5f 2 0 4294967295 IEC_60958_CS_CHANNEL_NUMBER_2 0 3 IEC_60958_CS_CHANNEL_NUMBER_3 4 7 ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7 2 0x60 2 0 4294967295 IEC_60958_CS_CHANNEL_NUMBER_4 0 3 IEC_60958_CS_CHANNEL_NUMBER_5 4 7 ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8 2 0x61 2 0 4294967295 IEC_60958_CS_CHANNEL_NUMBER_6 0 3 IEC_60958_CS_CHANNEL_NUMBER_7 4 7 ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO 2 0x62 1 0 4294967295 ASSOCIATION_INFO 0 31 ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS 2 0x63 1 0 4294967295 OUTPUT_ACTIVE 0 0 ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 2 0x64 2 0 4294967295 LPIB_SNAPSHOT_LOCK 0 0 CYCLIC_BUFFER_WRAP_COUNT 8 15 ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB 2 0x65 1 0 4294967295 LPIB 0 31 ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 2 0x66 1 0 4294967295 LPIB_TIMER_SNAPSHOT 0 31 ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE 2 0x67 1 0 4294967295 CODING_TYPE 0 7 ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED 2 0x68 4 0 4294967295 FORMAT_CHANGED 0 0 FORMAT_CHANGED_ACK_UR_ENABLE 1 1 FORMAT_CHANGE_REASON 8 15 FORMAT_CHANGE_RESPONSE 16 23 ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION 2 0x69 1 0 4294967295 WIRELESS_DISPLAY_IDENTIFICATION 0 1 ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE 2 0x6a 2 0 4294967295 REMOTE_KEEP_ALIVE_ENABLE 0 0 REMOTE_KEEP_ALIVE_CAPABILITY 4 4 ixAZF0ENDPOINT4_AZALIA_F0_AUDIO_ENABLE_STATUS 2 0x6b 1 0 4294967295 AUDIO_ENABLE_STATUS 0 0 ixAZF0ENDPOINT4_AZALIA_F0_AUDIO_ENABLED_INT_STATUS 2 0x6c 3 0 4294967295 AUDIO_ENABLED_FLAG 0 0 AUDIO_ENABLED_MASK 4 4 AUDIO_ENABLED_TYPE 8 8 ixAZF0ENDPOINT4_AZALIA_F0_AUDIO_DISABLED_INT_STATUS 2 0x6d 3 0 4294967295 AUDIO_DISABLED_FLAG 0 0 AUDIO_DISABLED_MASK 4 4 AUDIO_DISABLED_TYPE 8 8 ixAZF0ENDPOINT4_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS 2 0x6e 3 0 4294967295 AUDIO_FORMAT_CHANGED_FLAG 0 0 AUDIO_FORMAT_CHANGED_MASK 4 4 AUDIO_FORMAT_CHANGED_TYPE 8 8 ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 2 0x1 14 0 4294967295 AUDIO_CHANNEL_CAPABILITIES 0 0 INPUT_AMPLIFIER_PRESENT 1 1 OUTPUT_AMPLIFIER_PRESENT 2 2 AMPLIFIER_PARAMETER_OVERRIDE 3 3 FORMAT_OVERRIDE 4 4 STRIPE 5 5 PROCESSING_WIDGET 6 6 UNSOLICITED_RESPONSE_CAPABILITY 7 7 CONNECTION_LIST 8 8 DIGITAL 9 9 POWER_CONTROL 10 10 LR_SWAP 11 11 AUDIO_WIDGET_CAPABILITIES_DELAY 16 19 TYPE 20 23 ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT 2 0x2 6 0 4294967295 NUMBER_OF_CHANNELS 0 3 BITS_PER_SAMPLE 4 6 SAMPLE_BASE_DIVISOR 8 10 SAMPLE_BASE_MULTIPLE 11 13 SAMPLE_BASE_RATE 14 14 STREAM_TYPE 15 15 ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID 2 0x3 2 0 4294967295 CHANNEL_ID 0 3 STREAM_ID 4 7 ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER 2 0x4 10 0 4294967295 DIGEN 0 0 V 1 1 VCFG 2 2 PRE 3 3 COPY 4 4 NON_AUDIO 5 5 PRO 6 6 L 7 7 CC 8 14 KEEPALIVE 23 23 ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS 2 0x5 1 0 4294967295 STREAM_FORMATS 0 31 ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 2 0x6 2 0 4294967295 AUDIO_RATE_CAPABILITIES 0 11 AUDIO_BIT_CAPABILITIES 16 20 ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL 2 0x7 2 0 4294967295 STRIPE_CONTROL 0 1 STRIPE_CAPABILITY 20 22 ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE 2 0x8 1 0 4294967295 RAMP_RATE 0 7 ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING 2 0x9 4 0 4294967295 PRESENTATION_TIME_EMBEDDING_ENABLE 0 0 PRESENTATION_TIME_OFFSET_CHANGED 1 1 CLEAR_GTC_COUNTER_MIN_MAX_DELTA 2 2 PRESENTATION_TIME_EMBEDDING_GROUP 4 6 ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA 2 0xc 1 0 4294967295 GTC_COUNTER_DELTA 0 31 ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN 2 0xd 1 0 4294967295 GTC_COUNTER_DELTA_MIN 0 31 ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX 2 0xe 1 0 4294967295 GTC_COUNTER_DELTA_MAX 0 31 ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 2 0x20 13 0 4294967295 AUDIO_CHANNEL_CAPABILITIES 0 0 INPUT_AMPLIFIER_PRESENT 1 1 OUTPUT_AMPLIFIER_PRESENT 2 2 AMPLIFIER_PARAMETER_OVERRIDE 3 3 STRIPE 5 5 PROCESSING_WIDGET 6 6 UNSOLICITED_RESPONSE_CAPABILITY 7 7 CONNECTION_LIST 8 8 DIGITAL 9 9 POWER_CONTROL 10 10 LR_SWAP 11 11 AUDIO_WIDGET_CAPABILITIES_DELAY 16 19 TYPE 20 23 ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES 2 0x21 11 0 4294967295 IMPEDANCE_SENSE_CAPABLE 0 0 TRIGGER_REQUIRED 1 1 JACK_DETECTION_CAPABILITY 2 2 HEADPHONE_DRIVE_CAPABLE 3 3 OUTPUT_CAPABLE 4 4 INPUT_CAPABLE 5 5 BALANCED_I_O_PINS 6 6 HDMI 7 7 VREF_CONTROL 8 15 EAPD_CAPABLE 16 16 DP 24 24 ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE 2 0x22 2 0 4294967295 TAG 0 5 ENABLE 7 7 ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE 2 0x23 1 0 4294967295 IMPEDANCE_SENSE 0 30 ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL 2 0x24 1 0 4294967295 OUT_ENABLE 6 6 ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER 2 0x25 8 0 4294967295 SPEAKER_ALLOCATION 0 6 CHANNEL_ALLOCATION 8 15 HDMI_CONNECTION 16 16 DP_CONNECTION 17 17 EXTRA_CONNECTION_INFO 18 23 LFE_PLAYBACK_LEVEL 24 25 LEVEL_SHIFT 27 30 DOWN_MIX_INHIBIT 31 31 ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 2 0x28 4 0 4294967295 MAX_CHANNELS 0 2 SUPPORTED_FREQUENCIES 8 15 DESCRIPTOR_BYTE_2 16 23 SUPPORTED_FREQUENCIES_STEREO 24 31 ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 2 0x29 3 0 4294967295 MAX_CHANNELS 0 2 SUPPORTED_FREQUENCIES 8 15 DESCRIPTOR_BYTE_2 16 23 ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 2 0x2a 3 0 4294967295 MAX_CHANNELS 0 2 SUPPORTED_FREQUENCIES 8 15 DESCRIPTOR_BYTE_2 16 23 ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 2 0x2b 3 0 4294967295 MAX_CHANNELS 0 2 SUPPORTED_FREQUENCIES 8 15 DESCRIPTOR_BYTE_2 16 23 ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 2 0x2c 3 0 4294967295 MAX_CHANNELS 0 2 SUPPORTED_FREQUENCIES 8 15 DESCRIPTOR_BYTE_2 16 23 ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 2 0x2d 3 0 4294967295 MAX_CHANNELS 0 2 SUPPORTED_FREQUENCIES 8 15 DESCRIPTOR_BYTE_2 16 23 ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 2 0x2e 3 0 4294967295 MAX_CHANNELS 0 2 SUPPORTED_FREQUENCIES 8 15 DESCRIPTOR_BYTE_2 16 23 ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 2 0x2f 3 0 4294967295 MAX_CHANNELS 0 2 SUPPORTED_FREQUENCIES 8 15 DESCRIPTOR_BYTE_2 16 23 ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 2 0x30 3 0 4294967295 MAX_CHANNELS 0 2 SUPPORTED_FREQUENCIES 8 15 DESCRIPTOR_BYTE_2 16 23 ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 2 0x31 3 0 4294967295 MAX_CHANNELS 0 2 SUPPORTED_FREQUENCIES 8 15 DESCRIPTOR_BYTE_2 16 23 ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 2 0x32 3 0 4294967295 MAX_CHANNELS 0 2 SUPPORTED_FREQUENCIES 8 15 DESCRIPTOR_BYTE_2 16 23 ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 2 0x33 3 0 4294967295 MAX_CHANNELS 0 2 SUPPORTED_FREQUENCIES 8 15 DESCRIPTOR_BYTE_2 16 23 ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 2 0x34 3 0 4294967295 MAX_CHANNELS 0 2 SUPPORTED_FREQUENCIES 8 15 DESCRIPTOR_BYTE_2 16 23 ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 2 0x35 3 0 4294967295 MAX_CHANNELS 0 2 SUPPORTED_FREQUENCIES 8 15 DESCRIPTOR_BYTE_2 16 23 ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE 2 0x36 12 0 4294967295 MULTICHANNEL01_ENABLE 0 0 MULTICHANNEL01_MUTE 1 1 MULTICHANNEL01_CHANNEL_ID 4 7 MULTICHANNEL23_ENABLE 8 8 MULTICHANNEL23_MUTE 9 9 MULTICHANNEL23_CHANNEL_ID 12 15 MULTICHANNEL45_ENABLE 16 16 MULTICHANNEL45_MUTE 17 17 MULTICHANNEL45_CHANNEL_ID 20 23 MULTICHANNEL67_ENABLE 24 24 MULTICHANNEL67_MUTE 25 25 MULTICHANNEL67_CHANNEL_ID 28 31 ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC 2 0x37 2 0 4294967295 VIDEO_LIPSYNC 0 7 AUDIO_LIPSYNC 8 15 ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR 2 0x38 2 0 4294967295 HBR_CAPABLE 0 0 HBR_ENABLE 4 4 ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0 2 0x3a 2 0 4294967295 MANUFACTURER_ID 0 15 PRODUCT_ID 16 31 ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1 2 0x3b 1 0 4294967295 SINK_DESCRIPTION_LEN 0 7 ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2 2 0x3c 1 0 4294967295 PORT_ID0 0 31 ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3 2 0x3d 1 0 4294967295 PORT_ID1 0 31 ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4 2 0x3e 4 0 4294967295 DESCRIPTION0 0 7 DESCRIPTION1 8 15 DESCRIPTION2 16 23 DESCRIPTION3 24 31 ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5 2 0x3f 4 0 4294967295 DESCRIPTION4 0 7 DESCRIPTION5 8 15 DESCRIPTION6 16 23 DESCRIPTION7 24 31 ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6 2 0x40 4 0 4294967295 DESCRIPTION8 0 7 DESCRIPTION9 8 15 DESCRIPTION10 16 23 DESCRIPTION11 24 31 ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7 2 0x41 4 0 4294967295 DESCRIPTION12 0 7 DESCRIPTION13 8 15 DESCRIPTION14 16 23 DESCRIPTION15 24 31 ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8 2 0x42 2 0 4294967295 DESCRIPTION16 0 7 DESCRIPTION17 8 15 ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL 2 0x54 3 0 4294967295 CLOCK_GATING_DISABLE 0 0 CLOCK_ON_STATE 4 4 AUDIO_ENABLED 31 31 ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 2 0x55 2 0 4294967295 UNSOLICITED_RESPONSE_PAYLOAD 0 25 UNSOLICITED_RESPONSE_FORCE 28 28 ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 2 0x56 8 0 4294967295 SEQUENCE 0 3 DEFAULT_ASSOCIATION 4 7 MISC 8 11 COLOR 12 15 CONNECTION_TYPE 16 19 DEFAULT_DEVICE 20 23 LOCATION 24 29 PORT_CONNECTIVITY 30 31 ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2 2 0x57 12 0 4294967295 MULTICHANNEL1_ENABLE 0 0 MULTICHANNEL1_MUTE 1 1 MULTICHANNEL1_CHANNEL_ID 4 7 MULTICHANNEL3_ENABLE 8 8 MULTICHANNEL3_MUTE 9 9 MULTICHANNEL3_CHANNEL_ID 12 15 MULTICHANNEL5_ENABLE 16 16 MULTICHANNEL5_MUTE 17 17 MULTICHANNEL5_CHANNEL_ID 20 23 MULTICHANNEL7_ENABLE 24 24 MULTICHANNEL7_MUTE 25 25 MULTICHANNEL7_CHANNEL_ID 28 31 ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE 2 0x58 1 0 4294967295 MULTICHANNEL_MODE 0 0 ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0 2 0x59 2 0 4294967295 IEC_60958_CS_MODE 0 1 IEC_60958_CS_SOURCE_NUMBER 2 5 ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1 2 0x5a 4 0 4294967295 IEC_60958_CS_CLOCK_ACCURACY 0 1 IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN 2 2 IEC_60958_CS_WORD_LENGTH 3 6 IEC_60958_CS_WORD_LENGTH_OVRRD_EN 7 7 ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2 2 0x5b 2 0 4294967295 IEC_60958_CS_SAMPLING_FREQUENCY 0 5 IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN 6 6 ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3 2 0x5c 2 0 4294967295 IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY 0 3 IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN 4 4 ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4 2 0x5d 4 0 4294967295 IEC_60958_CS_SAMPLING_FREQUENCY_COEFF 0 3 IEC_60958_CS_MPEG_SURROUND_INFO 4 4 IEC_60958_CS_CGMS_A 5 6 IEC_60958_CS_CGMS_A_VALID 7 7 ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5 2 0x5e 2 0 4294967295 IEC_60958_CS_CHANNEL_NUMBER_L 0 3 IEC_60958_CS_CHANNEL_NUMBER_R 4 7 ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6 2 0x5f 2 0 4294967295 IEC_60958_CS_CHANNEL_NUMBER_2 0 3 IEC_60958_CS_CHANNEL_NUMBER_3 4 7 ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7 2 0x60 2 0 4294967295 IEC_60958_CS_CHANNEL_NUMBER_4 0 3 IEC_60958_CS_CHANNEL_NUMBER_5 4 7 ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8 2 0x61 2 0 4294967295 IEC_60958_CS_CHANNEL_NUMBER_6 0 3 IEC_60958_CS_CHANNEL_NUMBER_7 4 7 ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO 2 0x62 1 0 4294967295 ASSOCIATION_INFO 0 31 ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS 2 0x63 1 0 4294967295 OUTPUT_ACTIVE 0 0 ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 2 0x64 2 0 4294967295 LPIB_SNAPSHOT_LOCK 0 0 CYCLIC_BUFFER_WRAP_COUNT 8 15 ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB 2 0x65 1 0 4294967295 LPIB 0 31 ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 2 0x66 1 0 4294967295 LPIB_TIMER_SNAPSHOT 0 31 ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE 2 0x67 1 0 4294967295 CODING_TYPE 0 7 ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED 2 0x68 4 0 4294967295 FORMAT_CHANGED 0 0 FORMAT_CHANGED_ACK_UR_ENABLE 1 1 FORMAT_CHANGE_REASON 8 15 FORMAT_CHANGE_RESPONSE 16 23 ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION 2 0x69 1 0 4294967295 WIRELESS_DISPLAY_IDENTIFICATION 0 1 ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE 2 0x6a 2 0 4294967295 REMOTE_KEEP_ALIVE_ENABLE 0 0 REMOTE_KEEP_ALIVE_CAPABILITY 4 4 ixAZF0ENDPOINT5_AZALIA_F0_AUDIO_ENABLE_STATUS 2 0x6b 1 0 4294967295 AUDIO_ENABLE_STATUS 0 0 ixAZF0ENDPOINT5_AZALIA_F0_AUDIO_ENABLED_INT_STATUS 2 0x6c 3 0 4294967295 AUDIO_ENABLED_FLAG 0 0 AUDIO_ENABLED_MASK 4 4 AUDIO_ENABLED_TYPE 8 8 ixAZF0ENDPOINT5_AZALIA_F0_AUDIO_DISABLED_INT_STATUS 2 0x6d 3 0 4294967295 AUDIO_DISABLED_FLAG 0 0 AUDIO_DISABLED_MASK 4 4 AUDIO_DISABLED_TYPE 8 8 ixAZF0ENDPOINT5_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS 2 0x6e 3 0 4294967295 AUDIO_FORMAT_CHANGED_FLAG 0 0 AUDIO_FORMAT_CHANGED_MASK 4 4 AUDIO_FORMAT_CHANGED_TYPE 8 8 ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 2 0x1 14 0 4294967295 AUDIO_CHANNEL_CAPABILITIES 0 0 INPUT_AMPLIFIER_PRESENT 1 1 OUTPUT_AMPLIFIER_PRESENT 2 2 AMPLIFIER_PARAMETER_OVERRIDE 3 3 FORMAT_OVERRIDE 4 4 STRIPE 5 5 PROCESSING_WIDGET 6 6 UNSOLICITED_RESPONSE_CAPABILITY 7 7 CONNECTION_LIST 8 8 DIGITAL 9 9 POWER_CONTROL 10 10 LR_SWAP 11 11 AUDIO_WIDGET_CAPABILITIES_DELAY 16 19 TYPE 20 23 ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT 2 0x2 6 0 4294967295 NUMBER_OF_CHANNELS 0 3 BITS_PER_SAMPLE 4 6 SAMPLE_BASE_DIVISOR 8 10 SAMPLE_BASE_MULTIPLE 11 13 SAMPLE_BASE_RATE 14 14 STREAM_TYPE 15 15 ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID 2 0x3 2 0 4294967295 CHANNEL_ID 0 3 STREAM_ID 4 7 ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER 2 0x4 10 0 4294967295 DIGEN 0 0 V 1 1 VCFG 2 2 PRE 3 3 COPY 4 4 NON_AUDIO 5 5 PRO 6 6 L 7 7 CC 8 14 KEEPALIVE 23 23 ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS 2 0x5 1 0 4294967295 STREAM_FORMATS 0 31 ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 2 0x6 2 0 4294967295 AUDIO_RATE_CAPABILITIES 0 11 AUDIO_BIT_CAPABILITIES 16 20 ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL 2 0x7 2 0 4294967295 STRIPE_CONTROL 0 1 STRIPE_CAPABILITY 20 22 ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE 2 0x8 1 0 4294967295 RAMP_RATE 0 7 ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING 2 0x9 4 0 4294967295 PRESENTATION_TIME_EMBEDDING_ENABLE 0 0 PRESENTATION_TIME_OFFSET_CHANGED 1 1 CLEAR_GTC_COUNTER_MIN_MAX_DELTA 2 2 PRESENTATION_TIME_EMBEDDING_GROUP 4 6 ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA 2 0xc 1 0 4294967295 GTC_COUNTER_DELTA 0 31 ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN 2 0xd 1 0 4294967295 GTC_COUNTER_DELTA_MIN 0 31 ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX 2 0xe 1 0 4294967295 GTC_COUNTER_DELTA_MAX 0 31 ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 2 0x20 13 0 4294967295 AUDIO_CHANNEL_CAPABILITIES 0 0 INPUT_AMPLIFIER_PRESENT 1 1 OUTPUT_AMPLIFIER_PRESENT 2 2 AMPLIFIER_PARAMETER_OVERRIDE 3 3 STRIPE 5 5 PROCESSING_WIDGET 6 6 UNSOLICITED_RESPONSE_CAPABILITY 7 7 CONNECTION_LIST 8 8 DIGITAL 9 9 POWER_CONTROL 10 10 LR_SWAP 11 11 AUDIO_WIDGET_CAPABILITIES_DELAY 16 19 TYPE 20 23 ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES 2 0x21 11 0 4294967295 IMPEDANCE_SENSE_CAPABLE 0 0 TRIGGER_REQUIRED 1 1 JACK_DETECTION_CAPABILITY 2 2 HEADPHONE_DRIVE_CAPABLE 3 3 OUTPUT_CAPABLE 4 4 INPUT_CAPABLE 5 5 BALANCED_I_O_PINS 6 6 HDMI 7 7 VREF_CONTROL 8 15 EAPD_CAPABLE 16 16 DP 24 24 ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE 2 0x22 2 0 4294967295 TAG 0 5 ENABLE 7 7 ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE 2 0x23 1 0 4294967295 IMPEDANCE_SENSE 0 30 ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL 2 0x24 1 0 4294967295 OUT_ENABLE 6 6 ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER 2 0x25 8 0 4294967295 SPEAKER_ALLOCATION 0 6 CHANNEL_ALLOCATION 8 15 HDMI_CONNECTION 16 16 DP_CONNECTION 17 17 EXTRA_CONNECTION_INFO 18 23 LFE_PLAYBACK_LEVEL 24 25 LEVEL_SHIFT 27 30 DOWN_MIX_INHIBIT 31 31 ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 2 0x28 4 0 4294967295 MAX_CHANNELS 0 2 SUPPORTED_FREQUENCIES 8 15 DESCRIPTOR_BYTE_2 16 23 SUPPORTED_FREQUENCIES_STEREO 24 31 ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 2 0x29 3 0 4294967295 MAX_CHANNELS 0 2 SUPPORTED_FREQUENCIES 8 15 DESCRIPTOR_BYTE_2 16 23 ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 2 0x2a 3 0 4294967295 MAX_CHANNELS 0 2 SUPPORTED_FREQUENCIES 8 15 DESCRIPTOR_BYTE_2 16 23 ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 2 0x2b 3 0 4294967295 MAX_CHANNELS 0 2 SUPPORTED_FREQUENCIES 8 15 DESCRIPTOR_BYTE_2 16 23 ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 2 0x2c 3 0 4294967295 MAX_CHANNELS 0 2 SUPPORTED_FREQUENCIES 8 15 DESCRIPTOR_BYTE_2 16 23 ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 2 0x2d 3 0 4294967295 MAX_CHANNELS 0 2 SUPPORTED_FREQUENCIES 8 15 DESCRIPTOR_BYTE_2 16 23 ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 2 0x2e 3 0 4294967295 MAX_CHANNELS 0 2 SUPPORTED_FREQUENCIES 8 15 DESCRIPTOR_BYTE_2 16 23 ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 2 0x2f 3 0 4294967295 MAX_CHANNELS 0 2 SUPPORTED_FREQUENCIES 8 15 DESCRIPTOR_BYTE_2 16 23 ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 2 0x30 3 0 4294967295 MAX_CHANNELS 0 2 SUPPORTED_FREQUENCIES 8 15 DESCRIPTOR_BYTE_2 16 23 ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 2 0x31 3 0 4294967295 MAX_CHANNELS 0 2 SUPPORTED_FREQUENCIES 8 15 DESCRIPTOR_BYTE_2 16 23 ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 2 0x32 3 0 4294967295 MAX_CHANNELS 0 2 SUPPORTED_FREQUENCIES 8 15 DESCRIPTOR_BYTE_2 16 23 ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 2 0x33 3 0 4294967295 MAX_CHANNELS 0 2 SUPPORTED_FREQUENCIES 8 15 DESCRIPTOR_BYTE_2 16 23 ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 2 0x34 3 0 4294967295 MAX_CHANNELS 0 2 SUPPORTED_FREQUENCIES 8 15 DESCRIPTOR_BYTE_2 16 23 ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 2 0x35 3 0 4294967295 MAX_CHANNELS 0 2 SUPPORTED_FREQUENCIES 8 15 DESCRIPTOR_BYTE_2 16 23 ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE 2 0x36 12 0 4294967295 MULTICHANNEL01_ENABLE 0 0 MULTICHANNEL01_MUTE 1 1 MULTICHANNEL01_CHANNEL_ID 4 7 MULTICHANNEL23_ENABLE 8 8 MULTICHANNEL23_MUTE 9 9 MULTICHANNEL23_CHANNEL_ID 12 15 MULTICHANNEL45_ENABLE 16 16 MULTICHANNEL45_MUTE 17 17 MULTICHANNEL45_CHANNEL_ID 20 23 MULTICHANNEL67_ENABLE 24 24 MULTICHANNEL67_MUTE 25 25 MULTICHANNEL67_CHANNEL_ID 28 31 ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC 2 0x37 2 0 4294967295 VIDEO_LIPSYNC 0 7 AUDIO_LIPSYNC 8 15 ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR 2 0x38 2 0 4294967295 HBR_CAPABLE 0 0 HBR_ENABLE 4 4 ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0 2 0x3a 2 0 4294967295 MANUFACTURER_ID 0 15 PRODUCT_ID 16 31 ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1 2 0x3b 1 0 4294967295 SINK_DESCRIPTION_LEN 0 7 ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2 2 0x3c 1 0 4294967295 PORT_ID0 0 31 ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3 2 0x3d 1 0 4294967295 PORT_ID1 0 31 ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4 2 0x3e 4 0 4294967295 DESCRIPTION0 0 7 DESCRIPTION1 8 15 DESCRIPTION2 16 23 DESCRIPTION3 24 31 ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5 2 0x3f 4 0 4294967295 DESCRIPTION4 0 7 DESCRIPTION5 8 15 DESCRIPTION6 16 23 DESCRIPTION7 24 31 ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6 2 0x40 4 0 4294967295 DESCRIPTION8 0 7 DESCRIPTION9 8 15 DESCRIPTION10 16 23 DESCRIPTION11 24 31 ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7 2 0x41 4 0 4294967295 DESCRIPTION12 0 7 DESCRIPTION13 8 15 DESCRIPTION14 16 23 DESCRIPTION15 24 31 ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8 2 0x42 2 0 4294967295 DESCRIPTION16 0 7 DESCRIPTION17 8 15 ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL 2 0x54 3 0 4294967295 CLOCK_GATING_DISABLE 0 0 CLOCK_ON_STATE 4 4 AUDIO_ENABLED 31 31 ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 2 0x55 2 0 4294967295 UNSOLICITED_RESPONSE_PAYLOAD 0 25 UNSOLICITED_RESPONSE_FORCE 28 28 ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 2 0x56 8 0 4294967295 SEQUENCE 0 3 DEFAULT_ASSOCIATION 4 7 MISC 8 11 COLOR 12 15 CONNECTION_TYPE 16 19 DEFAULT_DEVICE 20 23 LOCATION 24 29 PORT_CONNECTIVITY 30 31 ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2 2 0x57 12 0 4294967295 MULTICHANNEL1_ENABLE 0 0 MULTICHANNEL1_MUTE 1 1 MULTICHANNEL1_CHANNEL_ID 4 7 MULTICHANNEL3_ENABLE 8 8 MULTICHANNEL3_MUTE 9 9 MULTICHANNEL3_CHANNEL_ID 12 15 MULTICHANNEL5_ENABLE 16 16 MULTICHANNEL5_MUTE 17 17 MULTICHANNEL5_CHANNEL_ID 20 23 MULTICHANNEL7_ENABLE 24 24 MULTICHANNEL7_MUTE 25 25 MULTICHANNEL7_CHANNEL_ID 28 31 ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE 2 0x58 1 0 4294967295 MULTICHANNEL_MODE 0 0 ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0 2 0x59 2 0 4294967295 IEC_60958_CS_MODE 0 1 IEC_60958_CS_SOURCE_NUMBER 2 5 ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1 2 0x5a 4 0 4294967295 IEC_60958_CS_CLOCK_ACCURACY 0 1 IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN 2 2 IEC_60958_CS_WORD_LENGTH 3 6 IEC_60958_CS_WORD_LENGTH_OVRRD_EN 7 7 ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2 2 0x5b 2 0 4294967295 IEC_60958_CS_SAMPLING_FREQUENCY 0 5 IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN 6 6 ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3 2 0x5c 2 0 4294967295 IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY 0 3 IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN 4 4 ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4 2 0x5d 4 0 4294967295 IEC_60958_CS_SAMPLING_FREQUENCY_COEFF 0 3 IEC_60958_CS_MPEG_SURROUND_INFO 4 4 IEC_60958_CS_CGMS_A 5 6 IEC_60958_CS_CGMS_A_VALID 7 7 ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5 2 0x5e 2 0 4294967295 IEC_60958_CS_CHANNEL_NUMBER_L 0 3 IEC_60958_CS_CHANNEL_NUMBER_R 4 7 ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6 2 0x5f 2 0 4294967295 IEC_60958_CS_CHANNEL_NUMBER_2 0 3 IEC_60958_CS_CHANNEL_NUMBER_3 4 7 ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7 2 0x60 2 0 4294967295 IEC_60958_CS_CHANNEL_NUMBER_4 0 3 IEC_60958_CS_CHANNEL_NUMBER_5 4 7 ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8 2 0x61 2 0 4294967295 IEC_60958_CS_CHANNEL_NUMBER_6 0 3 IEC_60958_CS_CHANNEL_NUMBER_7 4 7 ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO 2 0x62 1 0 4294967295 ASSOCIATION_INFO 0 31 ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS 2 0x63 1 0 4294967295 OUTPUT_ACTIVE 0 0 ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 2 0x64 2 0 4294967295 LPIB_SNAPSHOT_LOCK 0 0 CYCLIC_BUFFER_WRAP_COUNT 8 15 ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB 2 0x65 1 0 4294967295 LPIB 0 31 ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 2 0x66 1 0 4294967295 LPIB_TIMER_SNAPSHOT 0 31 ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE 2 0x67 1 0 4294967295 CODING_TYPE 0 7 ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED 2 0x68 4 0 4294967295 FORMAT_CHANGED 0 0 FORMAT_CHANGED_ACK_UR_ENABLE 1 1 FORMAT_CHANGE_REASON 8 15 FORMAT_CHANGE_RESPONSE 16 23 ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION 2 0x69 1 0 4294967295 WIRELESS_DISPLAY_IDENTIFICATION 0 1 ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE 2 0x6a 2 0 4294967295 REMOTE_KEEP_ALIVE_ENABLE 0 0 REMOTE_KEEP_ALIVE_CAPABILITY 4 4 ixAZF0ENDPOINT6_AZALIA_F0_AUDIO_ENABLE_STATUS 2 0x6b 1 0 4294967295 AUDIO_ENABLE_STATUS 0 0 ixAZF0ENDPOINT6_AZALIA_F0_AUDIO_ENABLED_INT_STATUS 2 0x6c 3 0 4294967295 AUDIO_ENABLED_FLAG 0 0 AUDIO_ENABLED_MASK 4 4 AUDIO_ENABLED_TYPE 8 8 ixAZF0ENDPOINT6_AZALIA_F0_AUDIO_DISABLED_INT_STATUS 2 0x6d 3 0 4294967295 AUDIO_DISABLED_FLAG 0 0 AUDIO_DISABLED_MASK 4 4 AUDIO_DISABLED_TYPE 8 8 ixAZF0ENDPOINT6_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS 2 0x6e 3 0 4294967295 AUDIO_FORMAT_CHANGED_FLAG 0 0 AUDIO_FORMAT_CHANGED_MASK 4 4 AUDIO_FORMAT_CHANGED_TYPE 8 8 ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 2 0x1 14 0 4294967295 AUDIO_CHANNEL_CAPABILITIES 0 0 INPUT_AMPLIFIER_PRESENT 1 1 OUTPUT_AMPLIFIER_PRESENT 2 2 AMPLIFIER_PARAMETER_OVERRIDE 3 3 FORMAT_OVERRIDE 4 4 STRIPE 5 5 PROCESSING_WIDGET 6 6 UNSOLICITED_RESPONSE_CAPABILITY 7 7 CONNECTION_LIST 8 8 DIGITAL 9 9 POWER_CONTROL 10 10 LR_SWAP 11 11 AUDIO_WIDGET_CAPABILITIES_DELAY 16 19 TYPE 20 23 ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT 2 0x2 6 0 4294967295 NUMBER_OF_CHANNELS 0 3 BITS_PER_SAMPLE 4 6 SAMPLE_BASE_DIVISOR 8 10 SAMPLE_BASE_MULTIPLE 11 13 SAMPLE_BASE_RATE 14 14 STREAM_TYPE 15 15 ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID 2 0x3 2 0 4294967295 CHANNEL_ID 0 3 STREAM_ID 4 7 ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER 2 0x4 10 0 4294967295 DIGEN 0 0 V 1 1 VCFG 2 2 PRE 3 3 COPY 4 4 NON_AUDIO 5 5 PRO 6 6 L 7 7 CC 8 14 KEEPALIVE 23 23 ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS 2 0x5 1 0 4294967295 STREAM_FORMATS 0 31 ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 2 0x6 2 0 4294967295 AUDIO_RATE_CAPABILITIES 0 11 AUDIO_BIT_CAPABILITIES 16 20 ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL 2 0x7 2 0 4294967295 STRIPE_CONTROL 0 1 STRIPE_CAPABILITY 20 22 ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE 2 0x8 1 0 4294967295 RAMP_RATE 0 7 ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING 2 0x9 4 0 4294967295 PRESENTATION_TIME_EMBEDDING_ENABLE 0 0 PRESENTATION_TIME_OFFSET_CHANGED 1 1 CLEAR_GTC_COUNTER_MIN_MAX_DELTA 2 2 PRESENTATION_TIME_EMBEDDING_GROUP 4 6 ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA 2 0xc 1 0 4294967295 GTC_COUNTER_DELTA 0 31 ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN 2 0xd 1 0 4294967295 GTC_COUNTER_DELTA_MIN 0 31 ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX 2 0xe 1 0 4294967295 GTC_COUNTER_DELTA_MAX 0 31 ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 2 0x20 13 0 4294967295 AUDIO_CHANNEL_CAPABILITIES 0 0 INPUT_AMPLIFIER_PRESENT 1 1 OUTPUT_AMPLIFIER_PRESENT 2 2 AMPLIFIER_PARAMETER_OVERRIDE 3 3 STRIPE 5 5 PROCESSING_WIDGET 6 6 UNSOLICITED_RESPONSE_CAPABILITY 7 7 CONNECTION_LIST 8 8 DIGITAL 9 9 POWER_CONTROL 10 10 LR_SWAP 11 11 AUDIO_WIDGET_CAPABILITIES_DELAY 16 19 TYPE 20 23 ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES 2 0x21 11 0 4294967295 IMPEDANCE_SENSE_CAPABLE 0 0 TRIGGER_REQUIRED 1 1 JACK_DETECTION_CAPABILITY 2 2 HEADPHONE_DRIVE_CAPABLE 3 3 OUTPUT_CAPABLE 4 4 INPUT_CAPABLE 5 5 BALANCED_I_O_PINS 6 6 HDMI 7 7 VREF_CONTROL 8 15 EAPD_CAPABLE 16 16 DP 24 24 ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE 2 0x22 2 0 4294967295 TAG 0 5 ENABLE 7 7 ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE 2 0x23 1 0 4294967295 IMPEDANCE_SENSE 0 30 ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL 2 0x24 1 0 4294967295 OUT_ENABLE 6 6 ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER 2 0x25 8 0 4294967295 SPEAKER_ALLOCATION 0 6 CHANNEL_ALLOCATION 8 15 HDMI_CONNECTION 16 16 DP_CONNECTION 17 17 EXTRA_CONNECTION_INFO 18 23 LFE_PLAYBACK_LEVEL 24 25 LEVEL_SHIFT 27 30 DOWN_MIX_INHIBIT 31 31 ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 2 0x28 4 0 4294967295 MAX_CHANNELS 0 2 SUPPORTED_FREQUENCIES 8 15 DESCRIPTOR_BYTE_2 16 23 SUPPORTED_FREQUENCIES_STEREO 24 31 ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 2 0x29 3 0 4294967295 MAX_CHANNELS 0 2 SUPPORTED_FREQUENCIES 8 15 DESCRIPTOR_BYTE_2 16 23 ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 2 0x2a 3 0 4294967295 MAX_CHANNELS 0 2 SUPPORTED_FREQUENCIES 8 15 DESCRIPTOR_BYTE_2 16 23 ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 2 0x2b 3 0 4294967295 MAX_CHANNELS 0 2 SUPPORTED_FREQUENCIES 8 15 DESCRIPTOR_BYTE_2 16 23 ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 2 0x2c 3 0 4294967295 MAX_CHANNELS 0 2 SUPPORTED_FREQUENCIES 8 15 DESCRIPTOR_BYTE_2 16 23 ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 2 0x2d 3 0 4294967295 MAX_CHANNELS 0 2 SUPPORTED_FREQUENCIES 8 15 DESCRIPTOR_BYTE_2 16 23 ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 2 0x2e 3 0 4294967295 MAX_CHANNELS 0 2 SUPPORTED_FREQUENCIES 8 15 DESCRIPTOR_BYTE_2 16 23 ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 2 0x2f 3 0 4294967295 MAX_CHANNELS 0 2 SUPPORTED_FREQUENCIES 8 15 DESCRIPTOR_BYTE_2 16 23 ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 2 0x30 3 0 4294967295 MAX_CHANNELS 0 2 SUPPORTED_FREQUENCIES 8 15 DESCRIPTOR_BYTE_2 16 23 ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 2 0x31 3 0 4294967295 MAX_CHANNELS 0 2 SUPPORTED_FREQUENCIES 8 15 DESCRIPTOR_BYTE_2 16 23 ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 2 0x32 3 0 4294967295 MAX_CHANNELS 0 2 SUPPORTED_FREQUENCIES 8 15 DESCRIPTOR_BYTE_2 16 23 ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 2 0x33 3 0 4294967295 MAX_CHANNELS 0 2 SUPPORTED_FREQUENCIES 8 15 DESCRIPTOR_BYTE_2 16 23 ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 2 0x34 3 0 4294967295 MAX_CHANNELS 0 2 SUPPORTED_FREQUENCIES 8 15 DESCRIPTOR_BYTE_2 16 23 ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 2 0x35 3 0 4294967295 MAX_CHANNELS 0 2 SUPPORTED_FREQUENCIES 8 15 DESCRIPTOR_BYTE_2 16 23 ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE 2 0x36 12 0 4294967295 MULTICHANNEL01_ENABLE 0 0 MULTICHANNEL01_MUTE 1 1 MULTICHANNEL01_CHANNEL_ID 4 7 MULTICHANNEL23_ENABLE 8 8 MULTICHANNEL23_MUTE 9 9 MULTICHANNEL23_CHANNEL_ID 12 15 MULTICHANNEL45_ENABLE 16 16 MULTICHANNEL45_MUTE 17 17 MULTICHANNEL45_CHANNEL_ID 20 23 MULTICHANNEL67_ENABLE 24 24 MULTICHANNEL67_MUTE 25 25 MULTICHANNEL67_CHANNEL_ID 28 31 ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC 2 0x37 2 0 4294967295 VIDEO_LIPSYNC 0 7 AUDIO_LIPSYNC 8 15 ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR 2 0x38 2 0 4294967295 HBR_CAPABLE 0 0 HBR_ENABLE 4 4 ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0 2 0x3a 2 0 4294967295 MANUFACTURER_ID 0 15 PRODUCT_ID 16 31 ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1 2 0x3b 1 0 4294967295 SINK_DESCRIPTION_LEN 0 7 ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2 2 0x3c 1 0 4294967295 PORT_ID0 0 31 ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3 2 0x3d 1 0 4294967295 PORT_ID1 0 31 ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4 2 0x3e 4 0 4294967295 DESCRIPTION0 0 7 DESCRIPTION1 8 15 DESCRIPTION2 16 23 DESCRIPTION3 24 31 ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5 2 0x3f 4 0 4294967295 DESCRIPTION4 0 7 DESCRIPTION5 8 15 DESCRIPTION6 16 23 DESCRIPTION7 24 31 ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6 2 0x40 4 0 4294967295 DESCRIPTION8 0 7 DESCRIPTION9 8 15 DESCRIPTION10 16 23 DESCRIPTION11 24 31 ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7 2 0x41 4 0 4294967295 DESCRIPTION12 0 7 DESCRIPTION13 8 15 DESCRIPTION14 16 23 DESCRIPTION15 24 31 ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8 2 0x42 2 0 4294967295 DESCRIPTION16 0 7 DESCRIPTION17 8 15 ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL 2 0x54 3 0 4294967295 CLOCK_GATING_DISABLE 0 0 CLOCK_ON_STATE 4 4 AUDIO_ENABLED 31 31 ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 2 0x55 2 0 4294967295 UNSOLICITED_RESPONSE_PAYLOAD 0 25 UNSOLICITED_RESPONSE_FORCE 28 28 ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 2 0x56 8 0 4294967295 SEQUENCE 0 3 DEFAULT_ASSOCIATION 4 7 MISC 8 11 COLOR 12 15 CONNECTION_TYPE 16 19 DEFAULT_DEVICE 20 23 LOCATION 24 29 PORT_CONNECTIVITY 30 31 ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2 2 0x57 12 0 4294967295 MULTICHANNEL1_ENABLE 0 0 MULTICHANNEL1_MUTE 1 1 MULTICHANNEL1_CHANNEL_ID 4 7 MULTICHANNEL3_ENABLE 8 8 MULTICHANNEL3_MUTE 9 9 MULTICHANNEL3_CHANNEL_ID 12 15 MULTICHANNEL5_ENABLE 16 16 MULTICHANNEL5_MUTE 17 17 MULTICHANNEL5_CHANNEL_ID 20 23 MULTICHANNEL7_ENABLE 24 24 MULTICHANNEL7_MUTE 25 25 MULTICHANNEL7_CHANNEL_ID 28 31 ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE 2 0x58 1 0 4294967295 MULTICHANNEL_MODE 0 0 ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0 2 0x59 2 0 4294967295 IEC_60958_CS_MODE 0 1 IEC_60958_CS_SOURCE_NUMBER 2 5 ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1 2 0x5a 4 0 4294967295 IEC_60958_CS_CLOCK_ACCURACY 0 1 IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN 2 2 IEC_60958_CS_WORD_LENGTH 3 6 IEC_60958_CS_WORD_LENGTH_OVRRD_EN 7 7 ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2 2 0x5b 2 0 4294967295 IEC_60958_CS_SAMPLING_FREQUENCY 0 5 IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN 6 6 ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3 2 0x5c 2 0 4294967295 IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY 0 3 IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN 4 4 ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4 2 0x5d 4 0 4294967295 IEC_60958_CS_SAMPLING_FREQUENCY_COEFF 0 3 IEC_60958_CS_MPEG_SURROUND_INFO 4 4 IEC_60958_CS_CGMS_A 5 6 IEC_60958_CS_CGMS_A_VALID 7 7 ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5 2 0x5e 2 0 4294967295 IEC_60958_CS_CHANNEL_NUMBER_L 0 3 IEC_60958_CS_CHANNEL_NUMBER_R 4 7 ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6 2 0x5f 2 0 4294967295 IEC_60958_CS_CHANNEL_NUMBER_2 0 3 IEC_60958_CS_CHANNEL_NUMBER_3 4 7 ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7 2 0x60 2 0 4294967295 IEC_60958_CS_CHANNEL_NUMBER_4 0 3 IEC_60958_CS_CHANNEL_NUMBER_5 4 7 ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8 2 0x61 2 0 4294967295 IEC_60958_CS_CHANNEL_NUMBER_6 0 3 IEC_60958_CS_CHANNEL_NUMBER_7 4 7 ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO 2 0x62 1 0 4294967295 ASSOCIATION_INFO 0 31 ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS 2 0x63 1 0 4294967295 OUTPUT_ACTIVE 0 0 ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 2 0x64 2 0 4294967295 LPIB_SNAPSHOT_LOCK 0 0 CYCLIC_BUFFER_WRAP_COUNT 8 15 ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB 2 0x65 1 0 4294967295 LPIB 0 31 ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 2 0x66 1 0 4294967295 LPIB_TIMER_SNAPSHOT 0 31 ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE 2 0x67 1 0 4294967295 CODING_TYPE 0 7 ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED 2 0x68 4 0 4294967295 FORMAT_CHANGED 0 0 FORMAT_CHANGED_ACK_UR_ENABLE 1 1 FORMAT_CHANGE_REASON 8 15 FORMAT_CHANGE_RESPONSE 16 23 ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION 2 0x69 1 0 4294967295 WIRELESS_DISPLAY_IDENTIFICATION 0 1 ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE 2 0x6a 2 0 4294967295 REMOTE_KEEP_ALIVE_ENABLE 0 0 REMOTE_KEEP_ALIVE_CAPABILITY 4 4 ixAZF0ENDPOINT7_AZALIA_F0_AUDIO_ENABLE_STATUS 2 0x6b 1 0 4294967295 AUDIO_ENABLE_STATUS 0 0 ixAZF0ENDPOINT7_AZALIA_F0_AUDIO_ENABLED_INT_STATUS 2 0x6c 3 0 4294967295 AUDIO_ENABLED_FLAG 0 0 AUDIO_ENABLED_MASK 4 4 AUDIO_ENABLED_TYPE 8 8 ixAZF0ENDPOINT7_AZALIA_F0_AUDIO_DISABLED_INT_STATUS 2 0x6d 3 0 4294967295 AUDIO_DISABLED_FLAG 0 0 AUDIO_DISABLED_MASK 4 4 AUDIO_DISABLED_TYPE 8 8 ixAZF0ENDPOINT7_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS 2 0x6e 3 0 4294967295 AUDIO_FORMAT_CHANGED_FLAG 0 0 AUDIO_FORMAT_CHANGED_MASK 4 4 AUDIO_FORMAT_CHANGED_TYPE 8 8 ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 2 0x1 14 0 4294967295 AUDIO_CHANNEL_CAPABILITIES 0 0 INPUT_AMPLIFIER_PRESENT 1 1 OUTPUT_AMPLIFIER_PRESENT 2 2 AMPLIFIER_PARAMETER_OVERRIDE 3 3 FORMAT_OVERRIDE 4 4 STRIPE 5 5 PROCESSING_WIDGET 6 6 UNSOLICITED_RESPONSE_CAPABILITY 7 7 CONNECTION_LIST 8 8 DIGITAL 9 9 POWER_CONTROL 10 10 LR_SWAP 11 11 AUDIO_WIDGET_CAPABILITIES_DELAY 16 19 TYPE 20 23 ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT 2 0x2 6 0 4294967295 NUMBER_OF_CHANNELS 0 3 BITS_PER_SAMPLE 4 6 SAMPLE_BASE_DIVISOR 8 10 SAMPLE_BASE_MULTIPLE 11 13 SAMPLE_BASE_RATE 14 14 STREAM_TYPE 15 15 ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID 2 0x3 2 0 4294967295 CHANNEL_ID 0 3 STREAM_ID 4 7 ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER 2 0x4 10 0 4294967295 DIGEN 0 0 V 1 1 VCFG 2 2 PRE 3 3 COPY 4 4 NON_AUDIO 5 5 PRO 6 6 L 7 7 CC 8 14 KEEPALIVE 23 23 ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS 2 0x5 1 0 4294967295 STREAM_FORMATS 0 31 ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 2 0x6 2 0 4294967295 AUDIO_RATE_CAPABILITIES 0 11 AUDIO_BIT_CAPABILITIES 16 20 ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 2 0x20 13 0 4294967295 AUDIO_CHANNEL_CAPABILITIES 0 0 INPUT_AMPLIFIER_PRESENT 1 1 OUTPUT_AMPLIFIER_PRESENT 2 2 AMPLIFIER_PARAMETER_OVERRIDE 3 3 STRIPE 5 5 PROCESSING_WIDGET 6 6 UNSOLICITED_RESPONSE_CAPABILITY 7 7 CONNECTION_LIST 8 8 DIGITAL 9 9 POWER_CONTROL 10 10 LR_SWAP 11 11 AUDIO_WIDGET_CAPABILITIES_DELAY 16 19 TYPE 20 23 ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES 2 0x21 11 0 4294967295 IMPEDANCE_SENSE_CAPABLE 0 0 TRIGGER_REQUIRED 1 1 JACK_DETECTION_CAPABILITY 2 2 HEADPHONE_DRIVE_CAPABLE 3 3 OUTPUT_CAPABLE 4 4 INPUT_CAPABLE 5 5 BALANCED_I_O_PINS 6 6 HDMI 7 7 VREF_CONTROL 8 15 EAPD_CAPABLE 16 16 DP 24 24 ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE 2 0x22 2 0 4294967295 TAG 0 5 ENABLE 7 7 ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE 2 0x23 2 0 4294967295 IMPEDANCE_SENSE 0 30 PRESENCE_DETECT 31 31 ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL 2 0x24 1 0 4294967295 IN_ENABLE 5 5 ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE 2 0x36 12 0 4294967295 MULTICHANNEL0_ENABLE 0 0 MULTICHANNEL0_MUTE 1 1 MULTICHANNEL0_CHANNEL_ID 4 7 MULTICHANNEL1_ENABLE 8 8 MULTICHANNEL1_MUTE 9 9 MULTICHANNEL1_CHANNEL_ID 12 15 MULTICHANNEL2_ENABLE 16 16 MULTICHANNEL2_MUTE 17 17 MULTICHANNEL2_CHANNEL_ID 20 23 MULTICHANNEL3_ENABLE 24 24 MULTICHANNEL3_MUTE 25 25 MULTICHANNEL3_CHANNEL_ID 28 31 ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2 2 0x37 12 0 4294967295 MULTICHANNEL4_ENABLE 0 0 MULTICHANNEL4_MUTE 1 1 MULTICHANNEL4_CHANNEL_ID 4 7 MULTICHANNEL5_ENABLE 8 8 MULTICHANNEL5_MUTE 9 9 MULTICHANNEL5_CHANNEL_ID 12 15 MULTICHANNEL6_ENABLE 16 16 MULTICHANNEL6_MUTE 17 17 MULTICHANNEL6_CHANNEL_ID 20 23 MULTICHANNEL7_ENABLE 24 24 MULTICHANNEL7_MUTE 25 25 MULTICHANNEL7_CHANNEL_ID 28 31 ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR 2 0x38 2 0 4294967295 HBR_CAPABLE 0 0 HBR_ENABLE 4 4 ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION 2 0x53 1 0 4294967295 CHANNEL_ALLOCATION 0 7 ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL 2 0x54 3 0 4294967295 CLOCK_GATING_DISABLE 0 0 CLOCK_ON_STATE 4 4 AUDIO_ENABLED 31 31 ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 2 0x55 2 0 4294967295 UNSOLICITED_RESPONSE_PAYLOAD 0 25 UNSOLICITED_RESPONSE_FORCE 28 28 ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 2 0x56 8 0 4294967295 SEQUENCE 0 3 DEFAULT_ASSOCIATION 4 7 MISC 8 11 COLOR 12 15 CONNECTION_TYPE 16 19 DEFAULT_DEVICE 20 23 LOCATION 24 29 PORT_CONNECTIVITY 30 31 ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 2 0x64 2 0 4294967295 LPIB_SNAPSHOT_LOCK 0 0 CYCLIC_BUFFER_WRAP_COUNT 8 15 ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB 2 0x65 1 0 4294967295 LPIB 0 31 ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 2 0x66 1 0 4294967295 LPIB_TIMER_SNAPSHOT 0 31 ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL 2 0x67 4 0 4294967295 INPUT_ACTIVITY 0 0 CHANNEL_LAYOUT 1 2 INPUT_ACTIVITY_UR_ENABLE 4 4 INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE 5 5 ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME 2 0x68 4 0 4294967295 CHANNEL_COUNT 0 2 CHANNEL_ALLOCATION 8 15 INFOFRAME_BYTE_5 16 23 INFOFRAME_VALID 31 31 ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 2 0x1 14 0 4294967295 AUDIO_CHANNEL_CAPABILITIES 0 0 INPUT_AMPLIFIER_PRESENT 1 1 OUTPUT_AMPLIFIER_PRESENT 2 2 AMPLIFIER_PARAMETER_OVERRIDE 3 3 FORMAT_OVERRIDE 4 4 STRIPE 5 5 PROCESSING_WIDGET 6 6 UNSOLICITED_RESPONSE_CAPABILITY 7 7 CONNECTION_LIST 8 8 DIGITAL 9 9 POWER_CONTROL 10 10 LR_SWAP 11 11 AUDIO_WIDGET_CAPABILITIES_DELAY 16 19 TYPE 20 23 ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT 2 0x2 6 0 4294967295 NUMBER_OF_CHANNELS 0 3 BITS_PER_SAMPLE 4 6 SAMPLE_BASE_DIVISOR 8 10 SAMPLE_BASE_MULTIPLE 11 13 SAMPLE_BASE_RATE 14 14 STREAM_TYPE 15 15 ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID 2 0x3 2 0 4294967295 CHANNEL_ID 0 3 STREAM_ID 4 7 ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER 2 0x4 10 0 4294967295 DIGEN 0 0 V 1 1 VCFG 2 2 PRE 3 3 COPY 4 4 NON_AUDIO 5 5 PRO 6 6 L 7 7 CC 8 14 KEEPALIVE 23 23 ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS 2 0x5 1 0 4294967295 STREAM_FORMATS 0 31 ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 2 0x6 2 0 4294967295 AUDIO_RATE_CAPABILITIES 0 11 AUDIO_BIT_CAPABILITIES 16 20 ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 2 0x20 13 0 4294967295 AUDIO_CHANNEL_CAPABILITIES 0 0 INPUT_AMPLIFIER_PRESENT 1 1 OUTPUT_AMPLIFIER_PRESENT 2 2 AMPLIFIER_PARAMETER_OVERRIDE 3 3 STRIPE 5 5 PROCESSING_WIDGET 6 6 UNSOLICITED_RESPONSE_CAPABILITY 7 7 CONNECTION_LIST 8 8 DIGITAL 9 9 POWER_CONTROL 10 10 LR_SWAP 11 11 AUDIO_WIDGET_CAPABILITIES_DELAY 16 19 TYPE 20 23 ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES 2 0x21 11 0 4294967295 IMPEDANCE_SENSE_CAPABLE 0 0 TRIGGER_REQUIRED 1 1 JACK_DETECTION_CAPABILITY 2 2 HEADPHONE_DRIVE_CAPABLE 3 3 OUTPUT_CAPABLE 4 4 INPUT_CAPABLE 5 5 BALANCED_I_O_PINS 6 6 HDMI 7 7 VREF_CONTROL 8 15 EAPD_CAPABLE 16 16 DP 24 24 ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE 2 0x22 2 0 4294967295 TAG 0 5 ENABLE 7 7 ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE 2 0x23 2 0 4294967295 IMPEDANCE_SENSE 0 30 PRESENCE_DETECT 31 31 ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL 2 0x24 1 0 4294967295 IN_ENABLE 5 5 ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE 2 0x36 12 0 4294967295 MULTICHANNEL0_ENABLE 0 0 MULTICHANNEL0_MUTE 1 1 MULTICHANNEL0_CHANNEL_ID 4 7 MULTICHANNEL1_ENABLE 8 8 MULTICHANNEL1_MUTE 9 9 MULTICHANNEL1_CHANNEL_ID 12 15 MULTICHANNEL2_ENABLE 16 16 MULTICHANNEL2_MUTE 17 17 MULTICHANNEL2_CHANNEL_ID 20 23 MULTICHANNEL3_ENABLE 24 24 MULTICHANNEL3_MUTE 25 25 MULTICHANNEL3_CHANNEL_ID 28 31 ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2 2 0x37 12 0 4294967295 MULTICHANNEL4_ENABLE 0 0 MULTICHANNEL4_MUTE 1 1 MULTICHANNEL4_CHANNEL_ID 4 7 MULTICHANNEL5_ENABLE 8 8 MULTICHANNEL5_MUTE 9 9 MULTICHANNEL5_CHANNEL_ID 12 15 MULTICHANNEL6_ENABLE 16 16 MULTICHANNEL6_MUTE 17 17 MULTICHANNEL6_CHANNEL_ID 20 23 MULTICHANNEL7_ENABLE 24 24 MULTICHANNEL7_MUTE 25 25 MULTICHANNEL7_CHANNEL_ID 28 31 ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR 2 0x38 2 0 4294967295 HBR_CAPABLE 0 0 HBR_ENABLE 4 4 ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION 2 0x53 1 0 4294967295 CHANNEL_ALLOCATION 0 7 ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL 2 0x54 3 0 4294967295 CLOCK_GATING_DISABLE 0 0 CLOCK_ON_STATE 4 4 AUDIO_ENABLED 31 31 ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 2 0x55 2 0 4294967295 UNSOLICITED_RESPONSE_PAYLOAD 0 25 UNSOLICITED_RESPONSE_FORCE 28 28 ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 2 0x56 8 0 4294967295 SEQUENCE 0 3 DEFAULT_ASSOCIATION 4 7 MISC 8 11 COLOR 12 15 CONNECTION_TYPE 16 19 DEFAULT_DEVICE 20 23 LOCATION 24 29 PORT_CONNECTIVITY 30 31 ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 2 0x64 2 0 4294967295 LPIB_SNAPSHOT_LOCK 0 0 CYCLIC_BUFFER_WRAP_COUNT 8 15 ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB 2 0x65 1 0 4294967295 LPIB 0 31 ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 2 0x66 1 0 4294967295 LPIB_TIMER_SNAPSHOT 0 31 ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL 2 0x67 4 0 4294967295 INPUT_ACTIVITY 0 0 CHANNEL_LAYOUT 1 2 INPUT_ACTIVITY_UR_ENABLE 4 4 INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE 5 5 ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME 2 0x68 4 0 4294967295 CHANNEL_COUNT 0 2 CHANNEL_ALLOCATION 8 15 INFOFRAME_BYTE_5 16 23 INFOFRAME_VALID 31 31 ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 2 0x1 14 0 4294967295 AUDIO_CHANNEL_CAPABILITIES 0 0 INPUT_AMPLIFIER_PRESENT 1 1 OUTPUT_AMPLIFIER_PRESENT 2 2 AMPLIFIER_PARAMETER_OVERRIDE 3 3 FORMAT_OVERRIDE 4 4 STRIPE 5 5 PROCESSING_WIDGET 6 6 UNSOLICITED_RESPONSE_CAPABILITY 7 7 CONNECTION_LIST 8 8 DIGITAL 9 9 POWER_CONTROL 10 10 LR_SWAP 11 11 AUDIO_WIDGET_CAPABILITIES_DELAY 16 19 TYPE 20 23 ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT 2 0x2 6 0 4294967295 NUMBER_OF_CHANNELS 0 3 BITS_PER_SAMPLE 4 6 SAMPLE_BASE_DIVISOR 8 10 SAMPLE_BASE_MULTIPLE 11 13 SAMPLE_BASE_RATE 14 14 STREAM_TYPE 15 15 ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID 2 0x3 2 0 4294967295 CHANNEL_ID 0 3 STREAM_ID 4 7 ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER 2 0x4 10 0 4294967295 DIGEN 0 0 V 1 1 VCFG 2 2 PRE 3 3 COPY 4 4 NON_AUDIO 5 5 PRO 6 6 L 7 7 CC 8 14 KEEPALIVE 23 23 ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS 2 0x5 1 0 4294967295 STREAM_FORMATS 0 31 ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 2 0x6 2 0 4294967295 AUDIO_RATE_CAPABILITIES 0 11 AUDIO_BIT_CAPABILITIES 16 20 ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 2 0x20 13 0 4294967295 AUDIO_CHANNEL_CAPABILITIES 0 0 INPUT_AMPLIFIER_PRESENT 1 1 OUTPUT_AMPLIFIER_PRESENT 2 2 AMPLIFIER_PARAMETER_OVERRIDE 3 3 STRIPE 5 5 PROCESSING_WIDGET 6 6 UNSOLICITED_RESPONSE_CAPABILITY 7 7 CONNECTION_LIST 8 8 DIGITAL 9 9 POWER_CONTROL 10 10 LR_SWAP 11 11 AUDIO_WIDGET_CAPABILITIES_DELAY 16 19 TYPE 20 23 ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES 2 0x21 11 0 4294967295 IMPEDANCE_SENSE_CAPABLE 0 0 TRIGGER_REQUIRED 1 1 JACK_DETECTION_CAPABILITY 2 2 HEADPHONE_DRIVE_CAPABLE 3 3 OUTPUT_CAPABLE 4 4 INPUT_CAPABLE 5 5 BALANCED_I_O_PINS 6 6 HDMI 7 7 VREF_CONTROL 8 15 EAPD_CAPABLE 16 16 DP 24 24 ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE 2 0x22 2 0 4294967295 TAG 0 5 ENABLE 7 7 ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE 2 0x23 2 0 4294967295 IMPEDANCE_SENSE 0 30 PRESENCE_DETECT 31 31 ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL 2 0x24 1 0 4294967295 IN_ENABLE 5 5 ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE 2 0x36 12 0 4294967295 MULTICHANNEL0_ENABLE 0 0 MULTICHANNEL0_MUTE 1 1 MULTICHANNEL0_CHANNEL_ID 4 7 MULTICHANNEL1_ENABLE 8 8 MULTICHANNEL1_MUTE 9 9 MULTICHANNEL1_CHANNEL_ID 12 15 MULTICHANNEL2_ENABLE 16 16 MULTICHANNEL2_MUTE 17 17 MULTICHANNEL2_CHANNEL_ID 20 23 MULTICHANNEL3_ENABLE 24 24 MULTICHANNEL3_MUTE 25 25 MULTICHANNEL3_CHANNEL_ID 28 31 ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2 2 0x37 12 0 4294967295 MULTICHANNEL4_ENABLE 0 0 MULTICHANNEL4_MUTE 1 1 MULTICHANNEL4_CHANNEL_ID 4 7 MULTICHANNEL5_ENABLE 8 8 MULTICHANNEL5_MUTE 9 9 MULTICHANNEL5_CHANNEL_ID 12 15 MULTICHANNEL6_ENABLE 16 16 MULTICHANNEL6_MUTE 17 17 MULTICHANNEL6_CHANNEL_ID 20 23 MULTICHANNEL7_ENABLE 24 24 MULTICHANNEL7_MUTE 25 25 MULTICHANNEL7_CHANNEL_ID 28 31 ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR 2 0x38 2 0 4294967295 HBR_CAPABLE 0 0 HBR_ENABLE 4 4 ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION 2 0x53 1 0 4294967295 CHANNEL_ALLOCATION 0 7 ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL 2 0x54 3 0 4294967295 CLOCK_GATING_DISABLE 0 0 CLOCK_ON_STATE 4 4 AUDIO_ENABLED 31 31 ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 2 0x55 2 0 4294967295 UNSOLICITED_RESPONSE_PAYLOAD 0 25 UNSOLICITED_RESPONSE_FORCE 28 28 ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 2 0x56 8 0 4294967295 SEQUENCE 0 3 DEFAULT_ASSOCIATION 4 7 MISC 8 11 COLOR 12 15 CONNECTION_TYPE 16 19 DEFAULT_DEVICE 20 23 LOCATION 24 29 PORT_CONNECTIVITY 30 31 ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 2 0x64 2 0 4294967295 LPIB_SNAPSHOT_LOCK 0 0 CYCLIC_BUFFER_WRAP_COUNT 8 15 ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB 2 0x65 1 0 4294967295 LPIB 0 31 ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 2 0x66 1 0 4294967295 LPIB_TIMER_SNAPSHOT 0 31 ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL 2 0x67 4 0 4294967295 INPUT_ACTIVITY 0 0 CHANNEL_LAYOUT 1 2 INPUT_ACTIVITY_UR_ENABLE 4 4 INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE 5 5 ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME 2 0x68 4 0 4294967295 CHANNEL_COUNT 0 2 CHANNEL_ALLOCATION 8 15 INFOFRAME_BYTE_5 16 23 INFOFRAME_VALID 31 31 ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 2 0x1 14 0 4294967295 AUDIO_CHANNEL_CAPABILITIES 0 0 INPUT_AMPLIFIER_PRESENT 1 1 OUTPUT_AMPLIFIER_PRESENT 2 2 AMPLIFIER_PARAMETER_OVERRIDE 3 3 FORMAT_OVERRIDE 4 4 STRIPE 5 5 PROCESSING_WIDGET 6 6 UNSOLICITED_RESPONSE_CAPABILITY 7 7 CONNECTION_LIST 8 8 DIGITAL 9 9 POWER_CONTROL 10 10 LR_SWAP 11 11 AUDIO_WIDGET_CAPABILITIES_DELAY 16 19 TYPE 20 23 ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT 2 0x2 6 0 4294967295 NUMBER_OF_CHANNELS 0 3 BITS_PER_SAMPLE 4 6 SAMPLE_BASE_DIVISOR 8 10 SAMPLE_BASE_MULTIPLE 11 13 SAMPLE_BASE_RATE 14 14 STREAM_TYPE 15 15 ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID 2 0x3 2 0 4294967295 CHANNEL_ID 0 3 STREAM_ID 4 7 ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER 2 0x4 10 0 4294967295 DIGEN 0 0 V 1 1 VCFG 2 2 PRE 3 3 COPY 4 4 NON_AUDIO 5 5 PRO 6 6 L 7 7 CC 8 14 KEEPALIVE 23 23 ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS 2 0x5 1 0 4294967295 STREAM_FORMATS 0 31 ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 2 0x6 2 0 4294967295 AUDIO_RATE_CAPABILITIES 0 11 AUDIO_BIT_CAPABILITIES 16 20 ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 2 0x20 13 0 4294967295 AUDIO_CHANNEL_CAPABILITIES 0 0 INPUT_AMPLIFIER_PRESENT 1 1 OUTPUT_AMPLIFIER_PRESENT 2 2 AMPLIFIER_PARAMETER_OVERRIDE 3 3 STRIPE 5 5 PROCESSING_WIDGET 6 6 UNSOLICITED_RESPONSE_CAPABILITY 7 7 CONNECTION_LIST 8 8 DIGITAL 9 9 POWER_CONTROL 10 10 LR_SWAP 11 11 AUDIO_WIDGET_CAPABILITIES_DELAY 16 19 TYPE 20 23 ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES 2 0x21 11 0 4294967295 IMPEDANCE_SENSE_CAPABLE 0 0 TRIGGER_REQUIRED 1 1 JACK_DETECTION_CAPABILITY 2 2 HEADPHONE_DRIVE_CAPABLE 3 3 OUTPUT_CAPABLE 4 4 INPUT_CAPABLE 5 5 BALANCED_I_O_PINS 6 6 HDMI 7 7 VREF_CONTROL 8 15 EAPD_CAPABLE 16 16 DP 24 24 ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE 2 0x22 2 0 4294967295 TAG 0 5 ENABLE 7 7 ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE 2 0x23 2 0 4294967295 IMPEDANCE_SENSE 0 30 PRESENCE_DETECT 31 31 ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL 2 0x24 1 0 4294967295 IN_ENABLE 5 5 ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE 2 0x36 12 0 4294967295 MULTICHANNEL0_ENABLE 0 0 MULTICHANNEL0_MUTE 1 1 MULTICHANNEL0_CHANNEL_ID 4 7 MULTICHANNEL1_ENABLE 8 8 MULTICHANNEL1_MUTE 9 9 MULTICHANNEL1_CHANNEL_ID 12 15 MULTICHANNEL2_ENABLE 16 16 MULTICHANNEL2_MUTE 17 17 MULTICHANNEL2_CHANNEL_ID 20 23 MULTICHANNEL3_ENABLE 24 24 MULTICHANNEL3_MUTE 25 25 MULTICHANNEL3_CHANNEL_ID 28 31 ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2 2 0x37 12 0 4294967295 MULTICHANNEL4_ENABLE 0 0 MULTICHANNEL4_MUTE 1 1 MULTICHANNEL4_CHANNEL_ID 4 7 MULTICHANNEL5_ENABLE 8 8 MULTICHANNEL5_MUTE 9 9 MULTICHANNEL5_CHANNEL_ID 12 15 MULTICHANNEL6_ENABLE 16 16 MULTICHANNEL6_MUTE 17 17 MULTICHANNEL6_CHANNEL_ID 20 23 MULTICHANNEL7_ENABLE 24 24 MULTICHANNEL7_MUTE 25 25 MULTICHANNEL7_CHANNEL_ID 28 31 ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR 2 0x38 2 0 4294967295 HBR_CAPABLE 0 0 HBR_ENABLE 4 4 ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION 2 0x53 1 0 4294967295 CHANNEL_ALLOCATION 0 7 ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL 2 0x54 3 0 4294967295 CLOCK_GATING_DISABLE 0 0 CLOCK_ON_STATE 4 4 AUDIO_ENABLED 31 31 ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 2 0x55 2 0 4294967295 UNSOLICITED_RESPONSE_PAYLOAD 0 25 UNSOLICITED_RESPONSE_FORCE 28 28 ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 2 0x56 8 0 4294967295 SEQUENCE 0 3 DEFAULT_ASSOCIATION 4 7 MISC 8 11 COLOR 12 15 CONNECTION_TYPE 16 19 DEFAULT_DEVICE 20 23 LOCATION 24 29 PORT_CONNECTIVITY 30 31 ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 2 0x64 2 0 4294967295 LPIB_SNAPSHOT_LOCK 0 0 CYCLIC_BUFFER_WRAP_COUNT 8 15 ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB 2 0x65 1 0 4294967295 LPIB 0 31 ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 2 0x66 1 0 4294967295 LPIB_TIMER_SNAPSHOT 0 31 ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL 2 0x67 4 0 4294967295 INPUT_ACTIVITY 0 0 CHANNEL_LAYOUT 1 2 INPUT_ACTIVITY_UR_ENABLE 4 4 INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE 5 5 ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME 2 0x68 4 0 4294967295 CHANNEL_COUNT 0 2 CHANNEL_ALLOCATION 8 15 INFOFRAME_BYTE_5 16 23 INFOFRAME_VALID 31 31 ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 2 0x1 14 0 4294967295 AUDIO_CHANNEL_CAPABILITIES 0 0 INPUT_AMPLIFIER_PRESENT 1 1 OUTPUT_AMPLIFIER_PRESENT 2 2 AMPLIFIER_PARAMETER_OVERRIDE 3 3 FORMAT_OVERRIDE 4 4 STRIPE 5 5 PROCESSING_WIDGET 6 6 UNSOLICITED_RESPONSE_CAPABILITY 7 7 CONNECTION_LIST 8 8 DIGITAL 9 9 POWER_CONTROL 10 10 LR_SWAP 11 11 AUDIO_WIDGET_CAPABILITIES_DELAY 16 19 TYPE 20 23 ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT 2 0x2 6 0 4294967295 NUMBER_OF_CHANNELS 0 3 BITS_PER_SAMPLE 4 6 SAMPLE_BASE_DIVISOR 8 10 SAMPLE_BASE_MULTIPLE 11 13 SAMPLE_BASE_RATE 14 14 STREAM_TYPE 15 15 ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID 2 0x3 2 0 4294967295 CHANNEL_ID 0 3 STREAM_ID 4 7 ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER 2 0x4 10 0 4294967295 DIGEN 0 0 V 1 1 VCFG 2 2 PRE 3 3 COPY 4 4 NON_AUDIO 5 5 PRO 6 6 L 7 7 CC 8 14 KEEPALIVE 23 23 ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS 2 0x5 1 0 4294967295 STREAM_FORMATS 0 31 ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 2 0x6 2 0 4294967295 AUDIO_RATE_CAPABILITIES 0 11 AUDIO_BIT_CAPABILITIES 16 20 ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 2 0x20 13 0 4294967295 AUDIO_CHANNEL_CAPABILITIES 0 0 INPUT_AMPLIFIER_PRESENT 1 1 OUTPUT_AMPLIFIER_PRESENT 2 2 AMPLIFIER_PARAMETER_OVERRIDE 3 3 STRIPE 5 5 PROCESSING_WIDGET 6 6 UNSOLICITED_RESPONSE_CAPABILITY 7 7 CONNECTION_LIST 8 8 DIGITAL 9 9 POWER_CONTROL 10 10 LR_SWAP 11 11 AUDIO_WIDGET_CAPABILITIES_DELAY 16 19 TYPE 20 23 ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES 2 0x21 11 0 4294967295 IMPEDANCE_SENSE_CAPABLE 0 0 TRIGGER_REQUIRED 1 1 JACK_DETECTION_CAPABILITY 2 2 HEADPHONE_DRIVE_CAPABLE 3 3 OUTPUT_CAPABLE 4 4 INPUT_CAPABLE 5 5 BALANCED_I_O_PINS 6 6 HDMI 7 7 VREF_CONTROL 8 15 EAPD_CAPABLE 16 16 DP 24 24 ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE 2 0x22 2 0 4294967295 TAG 0 5 ENABLE 7 7 ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE 2 0x23 2 0 4294967295 IMPEDANCE_SENSE 0 30 PRESENCE_DETECT 31 31 ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL 2 0x24 1 0 4294967295 IN_ENABLE 5 5 ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE 2 0x36 12 0 4294967295 MULTICHANNEL0_ENABLE 0 0 MULTICHANNEL0_MUTE 1 1 MULTICHANNEL0_CHANNEL_ID 4 7 MULTICHANNEL1_ENABLE 8 8 MULTICHANNEL1_MUTE 9 9 MULTICHANNEL1_CHANNEL_ID 12 15 MULTICHANNEL2_ENABLE 16 16 MULTICHANNEL2_MUTE 17 17 MULTICHANNEL2_CHANNEL_ID 20 23 MULTICHANNEL3_ENABLE 24 24 MULTICHANNEL3_MUTE 25 25 MULTICHANNEL3_CHANNEL_ID 28 31 ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2 2 0x37 12 0 4294967295 MULTICHANNEL4_ENABLE 0 0 MULTICHANNEL4_MUTE 1 1 MULTICHANNEL4_CHANNEL_ID 4 7 MULTICHANNEL5_ENABLE 8 8 MULTICHANNEL5_MUTE 9 9 MULTICHANNEL5_CHANNEL_ID 12 15 MULTICHANNEL6_ENABLE 16 16 MULTICHANNEL6_MUTE 17 17 MULTICHANNEL6_CHANNEL_ID 20 23 MULTICHANNEL7_ENABLE 24 24 MULTICHANNEL7_MUTE 25 25 MULTICHANNEL7_CHANNEL_ID 28 31 ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR 2 0x38 2 0 4294967295 HBR_CAPABLE 0 0 HBR_ENABLE 4 4 ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION 2 0x53 1 0 4294967295 CHANNEL_ALLOCATION 0 7 ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL 2 0x54 3 0 4294967295 CLOCK_GATING_DISABLE 0 0 CLOCK_ON_STATE 4 4 AUDIO_ENABLED 31 31 ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 2 0x55 2 0 4294967295 UNSOLICITED_RESPONSE_PAYLOAD 0 25 UNSOLICITED_RESPONSE_FORCE 28 28 ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 2 0x56 8 0 4294967295 SEQUENCE 0 3 DEFAULT_ASSOCIATION 4 7 MISC 8 11 COLOR 12 15 CONNECTION_TYPE 16 19 DEFAULT_DEVICE 20 23 LOCATION 24 29 PORT_CONNECTIVITY 30 31 ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 2 0x64 2 0 4294967295 LPIB_SNAPSHOT_LOCK 0 0 CYCLIC_BUFFER_WRAP_COUNT 8 15 ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB 2 0x65 1 0 4294967295 LPIB 0 31 ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 2 0x66 1 0 4294967295 LPIB_TIMER_SNAPSHOT 0 31 ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL 2 0x67 4 0 4294967295 INPUT_ACTIVITY 0 0 CHANNEL_LAYOUT 1 2 INPUT_ACTIVITY_UR_ENABLE 4 4 INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE 5 5 ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME 2 0x68 4 0 4294967295 CHANNEL_COUNT 0 2 CHANNEL_ALLOCATION 8 15 INFOFRAME_BYTE_5 16 23 INFOFRAME_VALID 31 31 ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 2 0x1 14 0 4294967295 AUDIO_CHANNEL_CAPABILITIES 0 0 INPUT_AMPLIFIER_PRESENT 1 1 OUTPUT_AMPLIFIER_PRESENT 2 2 AMPLIFIER_PARAMETER_OVERRIDE 3 3 FORMAT_OVERRIDE 4 4 STRIPE 5 5 PROCESSING_WIDGET 6 6 UNSOLICITED_RESPONSE_CAPABILITY 7 7 CONNECTION_LIST 8 8 DIGITAL 9 9 POWER_CONTROL 10 10 LR_SWAP 11 11 AUDIO_WIDGET_CAPABILITIES_DELAY 16 19 TYPE 20 23 ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT 2 0x2 6 0 4294967295 NUMBER_OF_CHANNELS 0 3 BITS_PER_SAMPLE 4 6 SAMPLE_BASE_DIVISOR 8 10 SAMPLE_BASE_MULTIPLE 11 13 SAMPLE_BASE_RATE 14 14 STREAM_TYPE 15 15 ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID 2 0x3 2 0 4294967295 CHANNEL_ID 0 3 STREAM_ID 4 7 ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER 2 0x4 10 0 4294967295 DIGEN 0 0 V 1 1 VCFG 2 2 PRE 3 3 COPY 4 4 NON_AUDIO 5 5 PRO 6 6 L 7 7 CC 8 14 KEEPALIVE 23 23 ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS 2 0x5 1 0 4294967295 STREAM_FORMATS 0 31 ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 2 0x6 2 0 4294967295 AUDIO_RATE_CAPABILITIES 0 11 AUDIO_BIT_CAPABILITIES 16 20 ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 2 0x20 13 0 4294967295 AUDIO_CHANNEL_CAPABILITIES 0 0 INPUT_AMPLIFIER_PRESENT 1 1 OUTPUT_AMPLIFIER_PRESENT 2 2 AMPLIFIER_PARAMETER_OVERRIDE 3 3 STRIPE 5 5 PROCESSING_WIDGET 6 6 UNSOLICITED_RESPONSE_CAPABILITY 7 7 CONNECTION_LIST 8 8 DIGITAL 9 9 POWER_CONTROL 10 10 LR_SWAP 11 11 AUDIO_WIDGET_CAPABILITIES_DELAY 16 19 TYPE 20 23 ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES 2 0x21 11 0 4294967295 IMPEDANCE_SENSE_CAPABLE 0 0 TRIGGER_REQUIRED 1 1 JACK_DETECTION_CAPABILITY 2 2 HEADPHONE_DRIVE_CAPABLE 3 3 OUTPUT_CAPABLE 4 4 INPUT_CAPABLE 5 5 BALANCED_I_O_PINS 6 6 HDMI 7 7 VREF_CONTROL 8 15 EAPD_CAPABLE 16 16 DP 24 24 ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE 2 0x22 2 0 4294967295 TAG 0 5 ENABLE 7 7 ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE 2 0x23 2 0 4294967295 IMPEDANCE_SENSE 0 30 PRESENCE_DETECT 31 31 ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL 2 0x24 1 0 4294967295 IN_ENABLE 5 5 ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE 2 0x36 12 0 4294967295 MULTICHANNEL0_ENABLE 0 0 MULTICHANNEL0_MUTE 1 1 MULTICHANNEL0_CHANNEL_ID 4 7 MULTICHANNEL1_ENABLE 8 8 MULTICHANNEL1_MUTE 9 9 MULTICHANNEL1_CHANNEL_ID 12 15 MULTICHANNEL2_ENABLE 16 16 MULTICHANNEL2_MUTE 17 17 MULTICHANNEL2_CHANNEL_ID 20 23 MULTICHANNEL3_ENABLE 24 24 MULTICHANNEL3_MUTE 25 25 MULTICHANNEL3_CHANNEL_ID 28 31 ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2 2 0x37 12 0 4294967295 MULTICHANNEL4_ENABLE 0 0 MULTICHANNEL4_MUTE 1 1 MULTICHANNEL4_CHANNEL_ID 4 7 MULTICHANNEL5_ENABLE 8 8 MULTICHANNEL5_MUTE 9 9 MULTICHANNEL5_CHANNEL_ID 12 15 MULTICHANNEL6_ENABLE 16 16 MULTICHANNEL6_MUTE 17 17 MULTICHANNEL6_CHANNEL_ID 20 23 MULTICHANNEL7_ENABLE 24 24 MULTICHANNEL7_MUTE 25 25 MULTICHANNEL7_CHANNEL_ID 28 31 ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR 2 0x38 2 0 4294967295 HBR_CAPABLE 0 0 HBR_ENABLE 4 4 ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION 2 0x53 1 0 4294967295 CHANNEL_ALLOCATION 0 7 ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL 2 0x54 3 0 4294967295 CLOCK_GATING_DISABLE 0 0 CLOCK_ON_STATE 4 4 AUDIO_ENABLED 31 31 ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 2 0x55 2 0 4294967295 UNSOLICITED_RESPONSE_PAYLOAD 0 25 UNSOLICITED_RESPONSE_FORCE 28 28 ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 2 0x56 8 0 4294967295 SEQUENCE 0 3 DEFAULT_ASSOCIATION 4 7 MISC 8 11 COLOR 12 15 CONNECTION_TYPE 16 19 DEFAULT_DEVICE 20 23 LOCATION 24 29 PORT_CONNECTIVITY 30 31 ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 2 0x64 2 0 4294967295 LPIB_SNAPSHOT_LOCK 0 0 CYCLIC_BUFFER_WRAP_COUNT 8 15 ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB 2 0x65 1 0 4294967295 LPIB 0 31 ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 2 0x66 1 0 4294967295 LPIB_TIMER_SNAPSHOT 0 31 ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL 2 0x67 4 0 4294967295 INPUT_ACTIVITY 0 0 CHANNEL_LAYOUT 1 2 INPUT_ACTIVITY_UR_ENABLE 4 4 INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE 5 5 ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME 2 0x68 4 0 4294967295 CHANNEL_COUNT 0 2 CHANNEL_ALLOCATION 8 15 INFOFRAME_BYTE_5 16 23 INFOFRAME_VALID 31 31 ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 2 0x1 14 0 4294967295 AUDIO_CHANNEL_CAPABILITIES 0 0 INPUT_AMPLIFIER_PRESENT 1 1 OUTPUT_AMPLIFIER_PRESENT 2 2 AMPLIFIER_PARAMETER_OVERRIDE 3 3 FORMAT_OVERRIDE 4 4 STRIPE 5 5 PROCESSING_WIDGET 6 6 UNSOLICITED_RESPONSE_CAPABILITY 7 7 CONNECTION_LIST 8 8 DIGITAL 9 9 POWER_CONTROL 10 10 LR_SWAP 11 11 AUDIO_WIDGET_CAPABILITIES_DELAY 16 19 TYPE 20 23 ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT 2 0x2 6 0 4294967295 NUMBER_OF_CHANNELS 0 3 BITS_PER_SAMPLE 4 6 SAMPLE_BASE_DIVISOR 8 10 SAMPLE_BASE_MULTIPLE 11 13 SAMPLE_BASE_RATE 14 14 STREAM_TYPE 15 15 ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID 2 0x3 2 0 4294967295 CHANNEL_ID 0 3 STREAM_ID 4 7 ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER 2 0x4 10 0 4294967295 DIGEN 0 0 V 1 1 VCFG 2 2 PRE 3 3 COPY 4 4 NON_AUDIO 5 5 PRO 6 6 L 7 7 CC 8 14 KEEPALIVE 23 23 ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS 2 0x5 1 0 4294967295 STREAM_FORMATS 0 31 ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 2 0x6 2 0 4294967295 AUDIO_RATE_CAPABILITIES 0 11 AUDIO_BIT_CAPABILITIES 16 20 ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 2 0x20 13 0 4294967295 AUDIO_CHANNEL_CAPABILITIES 0 0 INPUT_AMPLIFIER_PRESENT 1 1 OUTPUT_AMPLIFIER_PRESENT 2 2 AMPLIFIER_PARAMETER_OVERRIDE 3 3 STRIPE 5 5 PROCESSING_WIDGET 6 6 UNSOLICITED_RESPONSE_CAPABILITY 7 7 CONNECTION_LIST 8 8 DIGITAL 9 9 POWER_CONTROL 10 10 LR_SWAP 11 11 AUDIO_WIDGET_CAPABILITIES_DELAY 16 19 TYPE 20 23 ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES 2 0x21 11 0 4294967295 IMPEDANCE_SENSE_CAPABLE 0 0 TRIGGER_REQUIRED 1 1 JACK_DETECTION_CAPABILITY 2 2 HEADPHONE_DRIVE_CAPABLE 3 3 OUTPUT_CAPABLE 4 4 INPUT_CAPABLE 5 5 BALANCED_I_O_PINS 6 6 HDMI 7 7 VREF_CONTROL 8 15 EAPD_CAPABLE 16 16 DP 24 24 ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE 2 0x22 2 0 4294967295 TAG 0 5 ENABLE 7 7 ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE 2 0x23 2 0 4294967295 IMPEDANCE_SENSE 0 30 PRESENCE_DETECT 31 31 ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL 2 0x24 1 0 4294967295 IN_ENABLE 5 5 ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE 2 0x36 12 0 4294967295 MULTICHANNEL0_ENABLE 0 0 MULTICHANNEL0_MUTE 1 1 MULTICHANNEL0_CHANNEL_ID 4 7 MULTICHANNEL1_ENABLE 8 8 MULTICHANNEL1_MUTE 9 9 MULTICHANNEL1_CHANNEL_ID 12 15 MULTICHANNEL2_ENABLE 16 16 MULTICHANNEL2_MUTE 17 17 MULTICHANNEL2_CHANNEL_ID 20 23 MULTICHANNEL3_ENABLE 24 24 MULTICHANNEL3_MUTE 25 25 MULTICHANNEL3_CHANNEL_ID 28 31 ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2 2 0x37 12 0 4294967295 MULTICHANNEL4_ENABLE 0 0 MULTICHANNEL4_MUTE 1 1 MULTICHANNEL4_CHANNEL_ID 4 7 MULTICHANNEL5_ENABLE 8 8 MULTICHANNEL5_MUTE 9 9 MULTICHANNEL5_CHANNEL_ID 12 15 MULTICHANNEL6_ENABLE 16 16 MULTICHANNEL6_MUTE 17 17 MULTICHANNEL6_CHANNEL_ID 20 23 MULTICHANNEL7_ENABLE 24 24 MULTICHANNEL7_MUTE 25 25 MULTICHANNEL7_CHANNEL_ID 28 31 ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR 2 0x38 2 0 4294967295 HBR_CAPABLE 0 0 HBR_ENABLE 4 4 ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION 2 0x53 1 0 4294967295 CHANNEL_ALLOCATION 0 7 ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL 2 0x54 3 0 4294967295 CLOCK_GATING_DISABLE 0 0 CLOCK_ON_STATE 4 4 AUDIO_ENABLED 31 31 ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 2 0x55 2 0 4294967295 UNSOLICITED_RESPONSE_PAYLOAD 0 25 UNSOLICITED_RESPONSE_FORCE 28 28 ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 2 0x56 8 0 4294967295 SEQUENCE 0 3 DEFAULT_ASSOCIATION 4 7 MISC 8 11 COLOR 12 15 CONNECTION_TYPE 16 19 DEFAULT_DEVICE 20 23 LOCATION 24 29 PORT_CONNECTIVITY 30 31 ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 2 0x64 2 0 4294967295 LPIB_SNAPSHOT_LOCK 0 0 CYCLIC_BUFFER_WRAP_COUNT 8 15 ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB 2 0x65 1 0 4294967295 LPIB 0 31 ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 2 0x66 1 0 4294967295 LPIB_TIMER_SNAPSHOT 0 31 ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL 2 0x67 4 0 4294967295 INPUT_ACTIVITY 0 0 CHANNEL_LAYOUT 1 2 INPUT_ACTIVITY_UR_ENABLE 4 4 INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE 5 5 ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME 2 0x68 4 0 4294967295 CHANNEL_COUNT 0 2 CHANNEL_ALLOCATION 8 15 INFOFRAME_BYTE_5 16 23 INFOFRAME_VALID 31 31 ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 2 0x1 14 0 4294967295 AUDIO_CHANNEL_CAPABILITIES 0 0 INPUT_AMPLIFIER_PRESENT 1 1 OUTPUT_AMPLIFIER_PRESENT 2 2 AMPLIFIER_PARAMETER_OVERRIDE 3 3 FORMAT_OVERRIDE 4 4 STRIPE 5 5 PROCESSING_WIDGET 6 6 UNSOLICITED_RESPONSE_CAPABILITY 7 7 CONNECTION_LIST 8 8 DIGITAL 9 9 POWER_CONTROL 10 10 LR_SWAP 11 11 AUDIO_WIDGET_CAPABILITIES_DELAY 16 19 TYPE 20 23 ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT 2 0x2 6 0 4294967295 NUMBER_OF_CHANNELS 0 3 BITS_PER_SAMPLE 4 6 SAMPLE_BASE_DIVISOR 8 10 SAMPLE_BASE_MULTIPLE 11 13 SAMPLE_BASE_RATE 14 14 STREAM_TYPE 15 15 ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID 2 0x3 2 0 4294967295 CHANNEL_ID 0 3 STREAM_ID 4 7 ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER 2 0x4 10 0 4294967295 DIGEN 0 0 V 1 1 VCFG 2 2 PRE 3 3 COPY 4 4 NON_AUDIO 5 5 PRO 6 6 L 7 7 CC 8 14 KEEPALIVE 23 23 ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS 2 0x5 1 0 4294967295 STREAM_FORMATS 0 31 ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 2 0x6 2 0 4294967295 AUDIO_RATE_CAPABILITIES 0 11 AUDIO_BIT_CAPABILITIES 16 20 ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 2 0x20 13 0 4294967295 AUDIO_CHANNEL_CAPABILITIES 0 0 INPUT_AMPLIFIER_PRESENT 1 1 OUTPUT_AMPLIFIER_PRESENT 2 2 AMPLIFIER_PARAMETER_OVERRIDE 3 3 STRIPE 5 5 PROCESSING_WIDGET 6 6 UNSOLICITED_RESPONSE_CAPABILITY 7 7 CONNECTION_LIST 8 8 DIGITAL 9 9 POWER_CONTROL 10 10 LR_SWAP 11 11 AUDIO_WIDGET_CAPABILITIES_DELAY 16 19 TYPE 20 23 ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES 2 0x21 11 0 4294967295 IMPEDANCE_SENSE_CAPABLE 0 0 TRIGGER_REQUIRED 1 1 JACK_DETECTION_CAPABILITY 2 2 HEADPHONE_DRIVE_CAPABLE 3 3 OUTPUT_CAPABLE 4 4 INPUT_CAPABLE 5 5 BALANCED_I_O_PINS 6 6 HDMI 7 7 VREF_CONTROL 8 15 EAPD_CAPABLE 16 16 DP 24 24 ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE 2 0x22 2 0 4294967295 TAG 0 5 ENABLE 7 7 ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE 2 0x23 2 0 4294967295 IMPEDANCE_SENSE 0 30 PRESENCE_DETECT 31 31 ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL 2 0x24 1 0 4294967295 IN_ENABLE 5 5 ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE 2 0x36 12 0 4294967295 MULTICHANNEL0_ENABLE 0 0 MULTICHANNEL0_MUTE 1 1 MULTICHANNEL0_CHANNEL_ID 4 7 MULTICHANNEL1_ENABLE 8 8 MULTICHANNEL1_MUTE 9 9 MULTICHANNEL1_CHANNEL_ID 12 15 MULTICHANNEL2_ENABLE 16 16 MULTICHANNEL2_MUTE 17 17 MULTICHANNEL2_CHANNEL_ID 20 23 MULTICHANNEL3_ENABLE 24 24 MULTICHANNEL3_MUTE 25 25 MULTICHANNEL3_CHANNEL_ID 28 31 ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2 2 0x37 12 0 4294967295 MULTICHANNEL4_ENABLE 0 0 MULTICHANNEL4_MUTE 1 1 MULTICHANNEL4_CHANNEL_ID 4 7 MULTICHANNEL5_ENABLE 8 8 MULTICHANNEL5_MUTE 9 9 MULTICHANNEL5_CHANNEL_ID 12 15 MULTICHANNEL6_ENABLE 16 16 MULTICHANNEL6_MUTE 17 17 MULTICHANNEL6_CHANNEL_ID 20 23 MULTICHANNEL7_ENABLE 24 24 MULTICHANNEL7_MUTE 25 25 MULTICHANNEL7_CHANNEL_ID 28 31 ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR 2 0x38 2 0 4294967295 HBR_CAPABLE 0 0 HBR_ENABLE 4 4 ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION 2 0x53 1 0 4294967295 CHANNEL_ALLOCATION 0 7 ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL 2 0x54 3 0 4294967295 CLOCK_GATING_DISABLE 0 0 CLOCK_ON_STATE 4 4 AUDIO_ENABLED 31 31 ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 2 0x55 2 0 4294967295 UNSOLICITED_RESPONSE_PAYLOAD 0 25 UNSOLICITED_RESPONSE_FORCE 28 28 ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 2 0x56 8 0 4294967295 SEQUENCE 0 3 DEFAULT_ASSOCIATION 4 7 MISC 8 11 COLOR 12 15 CONNECTION_TYPE 16 19 DEFAULT_DEVICE 20 23 LOCATION 24 29 PORT_CONNECTIVITY 30 31 ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 2 0x64 2 0 4294967295 LPIB_SNAPSHOT_LOCK 0 0 CYCLIC_BUFFER_WRAP_COUNT 8 15 ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB 2 0x65 1 0 4294967295 LPIB 0 31 ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 2 0x66 1 0 4294967295 LPIB_TIMER_SNAPSHOT 0 31 ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL 2 0x67 4 0 4294967295 INPUT_ACTIVITY 0 0 CHANNEL_LAYOUT 1 2 INPUT_ACTIVITY_UR_ENABLE 4 4 INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE 5 5 ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME 2 0x68 4 0 4294967295 CHANNEL_COUNT 0 2 CHANNEL_ALLOCATION 8 15 INFOFRAME_BYTE_5 16 23 INFOFRAME_VALID 31 31