7511 regDENTIST_DISPCLK_CNTL 0 0x64 10 0 1 DENTIST_DISPCLK_WDIVIDER 0 6 DENTIST_DISPCLK_RDIVIDER 8 14 DENTIST_DISPCLK_CHG_MODE 15 16 DENTIST_DISPCLK_CHGTOG 17 17 DENTIST_DISPCLK_DONETOG 18 18 DENTIST_DISPCLK_CHG_DONE 19 19 DENTIST_DPPCLK_CHG_DONE 20 20 DENTIST_DPPCLK_CHGTOG 21 21 DENTIST_DPPCLK_DONETOG 22 22 DENTIST_DPPCLK_WDIVIDER 24 30 regPHYPLLA_PIXCLK_RESYNC_CNTL 0 0x40 5 0 1 PHYPLLA_PIXCLK_RESYNC_ENABLE 0 0 PHYPLLA_DEEP_COLOR_DTO_ENABLE_STATUS 1 1 PHYPLLA_DCCG_DEEP_COLOR_CNTL 4 5 PHYPLLA_PIXCLK_ENABLE 8 8 PHYPLLA_PIXCLK_DOUBLE_RATE_ENABLE 9 9 regPHYPLLB_PIXCLK_RESYNC_CNTL 0 0x41 5 0 1 PHYPLLB_PIXCLK_RESYNC_ENABLE 0 0 PHYPLLB_DEEP_COLOR_DTO_ENABLE_STATUS 1 1 PHYPLLB_DCCG_DEEP_COLOR_CNTL 4 5 PHYPLLB_PIXCLK_ENABLE 8 8 PHYPLLB_PIXCLK_DOUBLE_RATE_ENABLE 9 9 regPHYPLLC_PIXCLK_RESYNC_CNTL 0 0x42 5 0 1 PHYPLLC_PIXCLK_RESYNC_ENABLE 0 0 PHYPLLC_DEEP_COLOR_DTO_ENABLE_STATUS 1 1 PHYPLLC_DCCG_DEEP_COLOR_CNTL 4 5 PHYPLLC_PIXCLK_ENABLE 8 8 PHYPLLC_PIXCLK_DOUBLE_RATE_ENABLE 9 9 regPHYPLLD_PIXCLK_RESYNC_CNTL 0 0x43 5 0 1 PHYPLLD_PIXCLK_RESYNC_ENABLE 0 0 PHYPLLD_DEEP_COLOR_DTO_ENABLE_STATUS 1 1 PHYPLLD_DCCG_DEEP_COLOR_CNTL 4 5 PHYPLLD_PIXCLK_ENABLE 8 8 PHYPLLD_PIXCLK_DOUBLE_RATE_ENABLE 9 9 regDP_DTO_DBUF_EN 0 0x44 8 0 1 DP_DTO0_DBUF_EN 0 0 DP_DTO1_DBUF_EN 1 1 DP_DTO2_DBUF_EN 2 2 DP_DTO3_DBUF_EN 3 3 DP_DTO4_DBUF_EN 4 4 DP_DTO5_DBUF_EN 5 5 DP_DTO6_DBUF_EN 6 6 DP_DTO7_DBUF_EN 7 7 regDPREFCLK_CGTT_BLK_CTRL_REG 0 0x48 2 0 1 DPREFCLK_TURN_ON_DELAY 0 3 DPREFCLK_TURN_OFF_DELAY 4 11 regDCCG_GATE_DISABLE_CNTL4 0 0x49 6 0 1 PHYA_REFCLK_ROOT_GATE_DISABLE 0 0 PHYB_REFCLK_ROOT_GATE_DISABLE 1 1 PHYC_REFCLK_ROOT_GATE_DISABLE 2 2 PHYD_REFCLK_ROOT_GATE_DISABLE 3 3 PHYE_REFCLK_ROOT_GATE_DISABLE 4 4 HDMICHARCLK0_ROOT_GATE_DISABLE 17 17 regDPSTREAMCLK_CNTL 0 0x4a 4 0 1 DPSTREAMCLK_PIPE0_EN 1 1 DPSTREAMCLK_PIPE1_EN 2 2 DPSTREAMCLK_PIPE2_EN 3 3 DPSTREAMCLK_PIPE3_EN 4 4 regREFCLK_CGTT_BLK_CTRL_REG 0 0x4b 2 0 1 REFCLK_TURN_ON_DELAY 0 3 REFCLK_TURN_OFF_DELAY 4 11 regPHYPLLE_PIXCLK_RESYNC_CNTL 0 0x4c 5 0 1 PHYPLLE_PIXCLK_RESYNC_ENABLE 0 0 PHYPLLE_DEEP_COLOR_DTO_ENABLE_STATUS 1 1 PHYPLLE_DCCG_DEEP_COLOR_CNTL 4 5 PHYPLLE_PIXCLK_ENABLE 8 8 PHYPLLE_PIXCLK_DOUBLE_RATE_ENABLE 9 9 regDCCG_PERFMON_CNTL2 0 0x4e 10 0 1 DCCG_PERF_DSICLK_ENABLE 0 0 DCCG_PERF_REFCLK_ENABLE 1 1 DCCG_PERF_PIXCLK1_ENABLE 2 2 DCCG_PERF_PIXCLK2_ENABLE 3 3 DCCG_PERF_UNIPHYC_PIXCLK_ENABLE 4 4 DCCG_PERF_UNIPHYD_PIXCLK_ENABLE 5 5 DCCG_PERF_UNIPHYE_PIXCLK_ENABLE 6 6 DCCG_PERF_UNIPHYF_PIXCLK_ENABLE 7 7 DCCG_PERF_UNIPHYG_PIXCLK_ENABLE 8 8 DCCG_PERF_DTBCLK0_ENABLE 9 9 regDCCG_DS_DTO_INCR 0 0x53 1 0 1 DCCG_DS_DTO_INCR 0 31 regDCCG_DS_DTO_MODULO 0 0x54 1 0 1 DCCG_DS_DTO_MODULO 0 31 regDCCG_DS_CNTL 0 0x55 7 0 1 DCCG_DS_ENABLE 0 0 DCCG_DS_REF_SRC 4 5 DCCG_DS_HW_CAL_ENABLE 8 8 DCCG_DS_ENABLED_STATUS 9 9 DCCG_DS_XTALIN_RATE_DIV 16 17 DCCG_DS_JITTER_REMOVE_DIS 24 24 DCCG_DS_DELAY_XTAL_SEL 25 25 regDCCG_DS_HW_CAL_INTERVAL 0 0x56 1 0 1 DCCG_DS_HW_CAL_INTERVAL 0 31 regDPREFCLK_CNTL 0 0x58 1 0 1 DPREFCLK_SRC_SEL 0 2 regDCE_VERSION 0 0x5e 0 0 1 regDCCG_GTC_CNTL 0 0x60 1 0 1 DCCG_GTC_ENABLE 0 0 regDCCG_GTC_DTO_INCR 0 0x61 1 0 1 DCCG_GTC_DTO_INCR 0 31 regDCCG_GTC_DTO_MODULO 0 0x62 1 0 1 DCCG_GTC_DTO_MODULO 0 31 regDCCG_GTC_CURRENT 0 0x63 1 0 1 DCCG_GTC_CURRENT 0 31 regSYMCLK32_SE_CNTL 0 0x65 8 0 1 SYMCLK32_SE0_SRC_SEL 0 2 SYMCLK32_SE0_EN 3 3 SYMCLK32_SE1_SRC_SEL 4 6 SYMCLK32_SE1_EN 7 7 SYMCLK32_SE2_SRC_SEL 8 10 SYMCLK32_SE2_EN 11 11 SYMCLK32_SE3_SRC_SEL 12 14 SYMCLK32_SE3_EN 15 15 regSYMCLK32_LE_CNTL 0 0x66 4 0 1 SYMCLK32_LE0_SRC_SEL 0 2 SYMCLK32_LE0_EN 3 3 SYMCLK32_LE1_SRC_SEL 4 6 SYMCLK32_LE1_EN 7 7 regDSCCLK0_DTO_PARAM 0 0x6c 2 0 1 DSCCLK0_DTO_PHASE 0 7 DSCCLK0_DTO_MODULO 16 23 regDSCCLK1_DTO_PARAM 0 0x6d 2 0 1 DSCCLK1_DTO_PHASE 0 7 DSCCLK1_DTO_MODULO 16 23 regDSCCLK2_DTO_PARAM 0 0x6e 2 0 1 DSCCLK2_DTO_PHASE 0 7 DSCCLK2_DTO_MODULO 16 23 regMILLISECOND_TIME_BASE_DIV 0 0x70 2 0 1 MILLISECOND_TIME_BASE_DIV 0 16 MILLISECOND_TIME_BASE_CLOCK_SOURCE_SEL 20 20 regDISPCLK_FREQ_CHANGE_CNTL 0 0x71 8 0 1 DISPCLK_STEP_DELAY 0 13 DISPCLK_STEP_SIZE 16 19 DISPCLK_FREQ_RAMP_DONE 20 20 DISPCLK_MAX_ERRDET_CYCLES 25 27 DCCG_FIFO_ERRDET_RESET 28 28 DCCG_FIFO_ERRDET_STATE 29 29 DCCG_FIFO_ERRDET_OVR_EN 30 30 DISPCLK_CHG_FWD_CORR_DISABLE 31 31 regDC_MEM_GLOBAL_PWR_REQ_CNTL 0 0x72 1 0 1 DC_MEM_GLOBAL_PWR_REQ_DIS 0 0 regDCCG_PERFMON_CNTL 0 0x73 10 0 1 DCCG_PERF_DISPCLK_ENABLE 0 0 DCCG_PERF_DPREFCLK_ENABLE 1 1 DCCG_PERF_UNIPHYA_PIXCLK_ENABLE 2 2 DCCG_PERF_UNIPHYB_PIXCLK_ENABLE 3 3 DCCG_PERF_PIXCLK0_ENABLE 4 4 DCCG_PERF_RUN 5 5 DCCG_PERF_MODE_VSYNC 6 6 DCCG_PERF_MODE_HSYNC 7 7 DCCG_PERF_OTG_SEL 8 10 DCCG_PERF_XTALIN_PULSE_DIV 11 31 regDCCG_GATE_DISABLE_CNTL 0 0x74 20 0 1 DISPCLK_DCCG_GATE_DISABLE 0 0 DISPCLK_R_DCCG_GATE_DISABLE 1 1 SOCCLK_GATE_DISABLE 2 2 DPREFCLK_GATE_DISABLE 3 3 DACACLK_GATE_DISABLE 4 4 DVOACLK_GATE_DISABLE 6 6 DPREFCLK_R_DCCG_GATE_DISABLE 8 8 DPPCLK_GATE_DISABLE 9 9 DPPCLK_R_DCCG_GATE_DISABLE 10 10 DSCCLK_GATE_DISABLE 11 11 DMCUBCLK_GATE_DISABLE 12 12 AOMCLK0_GATE_DISABLE 17 17 AOMCLK1_GATE_DISABLE 18 18 AOMCLK2_GATE_DISABLE 19 19 DPREFCLK_GTC_GATE_DISABLE 22 22 REFCLK_GATE_DISABLE 26 26 REFCLK_R_DIG_GATE_DISABLE 27 27 DSICLK_GATE_DISABLE 28 28 BYTECLK_GATE_DISABLE 29 29 ESCCLK_GATE_DISABLE 30 30 regDISPCLK_CGTT_BLK_CTRL_REG 0 0x75 2 0 1 DISPCLK_TURN_ON_DELAY 0 3 DISPCLK_TURN_OFF_DELAY 4 11 regSOCCLK_CGTT_BLK_CTRL_REG 0 0x76 2 0 1 SOCCLK_TURN_ON_DELAY 0 3 SOCCLK_TURN_OFF_DELAY 4 11 regDCCG_CAC_STATUS 0 0x77 1 0 1 CAC_STATUS_RDDATA 0 31 regMICROSECOND_TIME_BASE_DIV 0 0x7b 5 0 1 MICROSECOND_TIME_BASE_DIV 0 6 XTAL_REF_DIV 8 14 XTAL_REF_SEL 16 16 XTAL_REF_CLOCK_SOURCE_SEL 17 17 MICROSECOND_TIME_BASE_CLOCK_SOURCE_SEL 20 20 regDCCG_GATE_DISABLE_CNTL2 0 0x7c 26 0 1 SYMCLKA_FE_GATE_DISABLE 0 0 SYMCLKB_FE_GATE_DISABLE 1 1 SYMCLKC_FE_GATE_DISABLE 2 2 SYMCLKD_FE_GATE_DISABLE 3 3 SYMCLKE_FE_GATE_DISABLE 4 4 SYMCLKF_FE_GATE_DISABLE 5 5 SYMCLKG_FE_GATE_DISABLE 6 6 HDMICHARCLK0_GATE_DISABLE 8 8 HDMICHARCLK1_GATE_DISABLE 9 9 HDMICHARCLK2_GATE_DISABLE 10 10 HDMICHARCLK3_GATE_DISABLE 11 11 HDMICHARCLK4_GATE_DISABLE 12 12 HDMICHARCLK5_GATE_DISABLE 13 13 SYMCLKA_GATE_DISABLE 16 16 SYMCLKB_GATE_DISABLE 17 17 SYMCLKC_GATE_DISABLE 18 18 SYMCLKD_GATE_DISABLE 19 19 SYMCLKE_GATE_DISABLE 20 20 SYMCLKF_GATE_DISABLE 21 21 SYMCLKG_GATE_DISABLE 22 22 PHYASYMCLK_GATE_DISABLE 24 24 PHYBSYMCLK_GATE_DISABLE 25 25 PHYCSYMCLK_GATE_DISABLE 26 26 PHYDSYMCLK_GATE_DISABLE 27 27 PHYESYMCLK_GATE_DISABLE 28 28 PHYFSYMCLK_GATE_DISABLE 29 29 regSYMCLK_CGTT_BLK_CTRL_REG 0 0x7d 2 0 1 SYMCLK_TURN_ON_DELAY 0 3 SYMCLK_TURN_OFF_DELAY 4 11 regDCCG_DISP_CNTL_REG 0 0x7f 1 0 1 ALLOW_SR_ON_TRANS_REQ 8 8 regOTG0_PIXEL_RATE_CNTL 0 0x80 13 0 1 OTG0_PIXEL_RATE_SOURCE 0 1 DTBCLK_DTO0_ENABLE 3 3 DP_DTO0_ENABLE 4 4 DP_DTO0_DS_DISABLE 5 5 DTBCLKDTO0_ENABLE_STATUS 6 6 DPDTO0_ENABLE_STATUS 7 7 OTG0_ADD_PIXEL 8 8 OTG0_DROP_PIXEL 9 9 OTG0_DISPOUT_HALF_RATE_EN 11 11 PIPE0_DTO_SRC_SEL 12 12 OTG0_DIO_FIFO_ERROR 14 15 OTG0_DIO_ERROR_COUNT 16 27 DTBCLK_DTO0_DIV 28 31 regDP_DTO0_PHASE 0 0x81 1 0 1 DP_DTO0_PHASE 0 31 regDP_DTO0_MODULO 0 0x82 1 0 1 DP_DTO0_MODULO 0 31 regOTG0_PHYPLL_PIXEL_RATE_CNTL 0 0x83 2 0 1 OTG0_PHYPLL_PIXEL_RATE_SOURCE 0 2 OTG0_PIXEL_RATE_PLL_SOURCE 4 4 regOTG1_PIXEL_RATE_CNTL 0 0x84 13 0 1 OTG1_PIXEL_RATE_SOURCE 0 1 DTBCLK_DTO1_ENABLE 3 3 DP_DTO1_ENABLE 4 4 DP_DTO1_DS_DISABLE 5 5 DTBCLKDTO1_ENABLE_STATUS 6 6 DPDTO1_ENABLE_STATUS 7 7 OTG1_ADD_PIXEL 8 8 OTG1_DROP_PIXEL 9 9 OTG1_DISPOUT_HALF_RATE_EN 11 11 PIPE1_DTO_SRC_SEL 12 12 OTG1_DIO_FIFO_ERROR 14 15 OTG1_DIO_ERROR_COUNT 16 27 DTBCLK_DTO1_DIV 28 31 regDP_DTO1_PHASE 0 0x85 1 0 1 DP_DTO1_PHASE 0 31 regDP_DTO1_MODULO 0 0x86 1 0 1 DP_DTO1_MODULO 0 31 regOTG1_PHYPLL_PIXEL_RATE_CNTL 0 0x87 2 0 1 OTG1_PHYPLL_PIXEL_RATE_SOURCE 0 2 OTG1_PIXEL_RATE_PLL_SOURCE 4 4 regOTG2_PIXEL_RATE_CNTL 0 0x88 13 0 1 OTG2_PIXEL_RATE_SOURCE 0 1 DTBCLK_DTO2_ENABLE 3 3 DP_DTO2_ENABLE 4 4 DP_DTO2_DS_DISABLE 5 5 DTBCLKDTO2_ENABLE_STATUS 6 6 DPDTO2_ENABLE_STATUS 7 7 OTG2_ADD_PIXEL 8 8 OTG2_DROP_PIXEL 9 9 OTG2_DISPOUT_HALF_RATE_EN 11 11 PIPE2_DTO_SRC_SEL 12 12 OTG2_DIO_FIFO_ERROR 14 15 OTG2_DIO_ERROR_COUNT 16 27 DTBCLK_DTO2_DIV 28 31 regDP_DTO2_PHASE 0 0x89 1 0 1 DP_DTO2_PHASE 0 31 regDP_DTO2_MODULO 0 0x8a 1 0 1 DP_DTO2_MODULO 0 31 regOTG2_PHYPLL_PIXEL_RATE_CNTL 0 0x8b 2 0 1 OTG2_PHYPLL_PIXEL_RATE_SOURCE 0 2 OTG2_PIXEL_RATE_PLL_SOURCE 4 4 regOTG3_PIXEL_RATE_CNTL 0 0x8c 13 0 1 OTG3_PIXEL_RATE_SOURCE 0 1 DTBCLK_DTO3_ENABLE 3 3 DP_DTO3_ENABLE 4 4 DP_DTO3_DS_DISABLE 5 5 DTBCLKDTO3_ENABLE_STATUS 6 6 DPDTO3_ENABLE_STATUS 7 7 OTG3_ADD_PIXEL 8 8 OTG3_DROP_PIXEL 9 9 OTG3_DISPOUT_HALF_RATE_EN 11 11 PIPE3_DTO_SRC_SEL 12 12 OTG3_DIO_FIFO_ERROR 14 15 OTG3_DIO_ERROR_COUNT 16 27 DTBCLK_DTO3_DIV 28 31 regDP_DTO3_PHASE 0 0x8d 1 0 1 DP_DTO3_PHASE 0 31 regDP_DTO3_MODULO 0 0x8e 1 0 1 DP_DTO3_MODULO 0 31 regOTG3_PHYPLL_PIXEL_RATE_CNTL 0 0x8f 2 0 1 OTG3_PHYPLL_PIXEL_RATE_SOURCE 0 2 OTG3_PIXEL_RATE_PLL_SOURCE 4 4 regDPPCLK_CGTT_BLK_CTRL_REG 0 0x98 2 0 1 DPPCLK_TURN_ON_DELAY 0 3 DPPCLK_TURN_OFF_DELAY 4 11 regDPPCLK0_DTO_PARAM 0 0x99 2 0 1 DPPCLK0_DTO_PHASE 0 7 DPPCLK0_DTO_MODULO 16 23 regDPPCLK1_DTO_PARAM 0 0x9a 2 0 1 DPPCLK1_DTO_PHASE 0 7 DPPCLK1_DTO_MODULO 16 23 regDPPCLK2_DTO_PARAM 0 0x9b 2 0 1 DPPCLK2_DTO_PHASE 0 7 DPPCLK2_DTO_MODULO 16 23 regDPPCLK3_DTO_PARAM 0 0x9c 2 0 1 DPPCLK3_DTO_PHASE 0 7 DPPCLK3_DTO_MODULO 16 23 regDCCG_CAC_STATUS2 0 0x9f 1 0 1 CAC_STATUS_RDDATA2 0 18 regSYMCLKA_CLOCK_ENABLE 0 0xa0 3 0 1 SYMCLKA_CLOCK_ENABLE 0 0 SYMCLKA_FE_FORCE_EN 4 4 SYMCLKA_FE_FORCE_SRC 8 10 regSYMCLKB_CLOCK_ENABLE 0 0xa1 3 0 1 SYMCLKB_CLOCK_ENABLE 0 0 SYMCLKB_FE_FORCE_EN 4 4 SYMCLKB_FE_FORCE_SRC 8 10 regSYMCLKC_CLOCK_ENABLE 0 0xa2 3 0 1 SYMCLKC_CLOCK_ENABLE 0 0 SYMCLKC_FE_FORCE_EN 4 4 SYMCLKC_FE_FORCE_SRC 8 10 regSYMCLKD_CLOCK_ENABLE 0 0xa3 3 0 1 SYMCLKD_CLOCK_ENABLE 0 0 SYMCLKD_FE_FORCE_EN 4 4 SYMCLKD_FE_FORCE_SRC 8 10 regSYMCLKE_CLOCK_ENABLE 0 0xa4 3 0 1 SYMCLKE_CLOCK_ENABLE 0 0 SYMCLKE_FE_FORCE_EN 4 4 SYMCLKE_FE_FORCE_SRC 8 10 regDCCG_SOFT_RESET 0 0xa6 15 0 1 REFCLK_SOFT_RESET 0 0 SOFT_RESET_DVO 2 2 DVO_ENABLE_RST 3 3 AUDIO_DTO2_CLK_SOFT_RESET 4 4 DPREFCLK_SOFT_RESET 8 8 AMCLK0_SOFT_RESET 12 12 AMCLK1_SOFT_RESET 13 13 P0PLL_CFG_IF_SOFT_RESET 14 14 P1PLL_CFG_IF_SOFT_RESET 15 15 P2PLL_CFG_IF_SOFT_RESET 16 16 A0PLL_CFG_IF_SOFT_RESET 17 17 A1PLL_CFG_IF_SOFT_RESET 18 18 C0PLL_CFG_IF_SOFT_RESET 19 19 C1PLL_CFG_IF_SOFT_RESET 20 20 C2PLL_CFG_IF_SOFT_RESET 21 21 regDSCCLK_DTO_CTRL 0 0xa7 12 0 1 DSCCLK0_DTO_ENABLE 0 0 DSCCLK1_DTO_ENABLE 1 1 DSCCLK2_DTO_ENABLE 2 2 DSCCLK3_DTO_ENABLE 3 3 DSCCLK4_DTO_ENABLE 4 4 DSCCLK5_DTO_ENABLE 5 5 DSCCLK0_DTO_DB_EN 8 8 DSCCLK1_DTO_DB_EN 9 9 DSCCLK2_DTO_DB_EN 10 10 DSCCLK3_DTO_DB_EN 11 11 DSCCLK4_DTO_DB_EN 12 12 DSCCLK5_DTO_DB_EN 13 13 regDCCG_AUDIO_DTO_SOURCE 0 0xab 6 0 1 DCCG_AUDIO_DTO0_SOURCE_SEL 0 2 DCCG_AUDIO_DTO_SEL 4 6 DCCG_AUDIO_DTO2_USE_512FBR_DTO 20 20 DCCG_AUDIO_DTO0_USE_512FBR_DTO 24 24 DCCG_AUDIO_DTO1_USE_512FBR_DTO 28 28 DCCG_AUDIO_DTBCLK_DTO_USE_512FBR_DTO 29 29 regDCCG_AUDIO_DTO0_PHASE 0 0xac 1 0 1 DCCG_AUDIO_DTO0_PHASE 0 31 regDCCG_AUDIO_DTO0_MODULE 0 0xad 1 0 1 DCCG_AUDIO_DTO0_MODULE 0 31 regDCCG_AUDIO_DTO1_PHASE 0 0xae 1 0 1 DCCG_AUDIO_DTO1_PHASE 0 31 regDCCG_AUDIO_DTO1_MODULE 0 0xaf 1 0 1 DCCG_AUDIO_DTO1_MODULE 0 31 regDCCG_VSYNC_OTG0_LATCH_VALUE 0 0xb0 1 0 1 DCCG_VSYNC_CNT_OTG0_LATCH_VALUE 0 31 regDCCG_VSYNC_OTG1_LATCH_VALUE 0 0xb1 1 0 1 DCCG_VSYNC_CNT_OTG1_LATCH_VALUE 0 31 regDCCG_VSYNC_OTG2_LATCH_VALUE 0 0xb2 1 0 1 DCCG_VSYNC_CNT_OTG2_LATCH_VALUE 0 31 regDCCG_VSYNC_OTG3_LATCH_VALUE 0 0xb3 1 0 1 DCCG_VSYNC_CNT_OTG3_LATCH_VALUE 0 31 regDCCG_VSYNC_OTG4_LATCH_VALUE 0 0xb4 1 0 1 DCCG_VSYNC_CNT_OTG4_LATCH_VALUE 0 31 regDCCG_VSYNC_OTG5_LATCH_VALUE 0 0xb5 1 0 1 DCCG_VSYNC_CNT_OTG5_LATCH_VALUE 0 31 regDPPCLK_DTO_CTRL 0 0xb6 12 0 1 DPPCLK0_DTO_ENABLE 0 0 DPPCLK0_DTO_DB_EN 1 1 DPPCLK1_DTO_ENABLE 4 4 DPPCLK1_DTO_DB_EN 5 5 DPPCLK2_DTO_ENABLE 8 8 DPPCLK2_DTO_DB_EN 9 9 DPPCLK3_DTO_ENABLE 12 12 DPPCLK3_DTO_DB_EN 13 13 DPPCLK4_DTO_ENABLE 16 16 DPPCLK4_DTO_DB_EN 17 17 DPPCLK5_DTO_ENABLE 20 20 DPPCLK5_DTO_DB_EN 21 21 regDCCG_VSYNC_CNT_CTRL 0 0xb8 17 0 1 DCCG_VSYNC_CNT_ENABLE 0 0 DCCG_VSYNC_CNT_SW_RESET 2 2 DCCG_VSYNC_CNT_RESET_SEL 3 3 DCCG_VSYNC_CNT_EXT_TRIG_SEL 4 7 DCCG_VSYNC_CNT_FRAME_CNT 8 11 DCCG_VSYNC_OTG0_LATCH_EN 16 16 DCCG_VSYNC_OTG1_LATCH_EN 17 17 DCCG_VSYNC_OTG2_LATCH_EN 18 18 DCCG_VSYNC_OTG3_LATCH_EN 19 19 DCCG_VSYNC_OTG4_LATCH_EN 20 20 DCCG_VSYNC_OTG5_LATCH_EN 21 21 DCCG_VSYNC_OTG0_VSYNC_TRIG_SEL 24 24 DCCG_VSYNC_OTG1_VSYNC_TRIG_SEL 25 25 DCCG_VSYNC_OTG2_VSYNC_TRIG_SEL 26 26 DCCG_VSYNC_OTG3_VSYNC_TRIG_SEL 27 27 DCCG_VSYNC_OTG4_VSYNC_TRIG_SEL 28 28 DCCG_VSYNC_OTG5_VSYNC_TRIG_SEL 29 29 regDCCG_VSYNC_CNT_INT_CTRL 0 0xb9 18 0 1 DCCG_VSYNC_CNT_OTG0_LATCH_INTERRUPT 0 0 DCCG_VSYNC_CNT_OTG0_LATCH_INTERRUPT_CLEAR 0 0 DCCG_VSYNC_CNT_OTG1_LATCH_INTERRUPT 1 1 DCCG_VSYNC_CNT_OTG1_LATCH_INTERRUPT_CLEAR 1 1 DCCG_VSYNC_CNT_OTG2_LATCH_INTERRUPT 2 2 DCCG_VSYNC_CNT_OTG2_LATCH_INTERRUPT_CLEAR 2 2 DCCG_VSYNC_CNT_OTG3_LATCH_INTERRUPT 3 3 DCCG_VSYNC_CNT_OTG3_LATCH_INTERRUPT_CLEAR 3 3 DCCG_VSYNC_CNT_OTG4_LATCH_INTERRUPT 4 4 DCCG_VSYNC_CNT_OTG4_LATCH_INTERRUPT_CLEAR 4 4 DCCG_VSYNC_CNT_OTG5_LATCH_INTERRUPT 5 5 DCCG_VSYNC_CNT_OTG5_LATCH_INTERRUPT_CLEAR 5 5 DCCG_VSYNC_CNT_OTG0_LATCH_MASK 8 8 DCCG_VSYNC_CNT_OTG1_LATCH_MASK 9 9 DCCG_VSYNC_CNT_OTG2_LATCH_MASK 10 10 DCCG_VSYNC_CNT_OTG3_LATCH_MASK 11 11 DCCG_VSYNC_CNT_OTG4_LATCH_MASK 12 12 DCCG_VSYNC_CNT_OTG5_LATCH_MASK 13 13 regFORCE_SYMCLK_DISABLE 0 0xba 7 0 1 FORCE_SYMCLKA_DISABLE 0 0 FORCE_SYMCLKB_DISABLE 1 1 FORCE_SYMCLKC_DISABLE 2 2 FORCE_SYMCLKD_DISABLE 3 3 FORCE_SYMCLKE_DISABLE 4 4 FORCE_SYMCLKF_DISABLE 5 5 FORCE_SYMCLKG_DISABLE 6 6 regDCCG_TEST_CLK_SEL 0 0xbe 5 0 1 DCCG_TEST_CLK_GENERICA_SEL 0 8 DCCG_TEST_CLK_GENERICA_INV 12 12 DCCG_TEST_CLK_GENERICA_DIV_SEL 14 15 DCCG_TEST_CLK_GENERICB_SEL 16 24 DCCG_TEST_CLK_GENERICB_INV 28 28 regDTBCLK_DTO0_PHASE 0 0x18 1 0 2 DTBCLK_DTO0_PHASE 0 31 regDTBCLK_DTO1_PHASE 0 0x19 1 0 2 DTBCLK_DTO1_PHASE 0 31 regDTBCLK_DTO2_PHASE 0 0x1a 1 0 2 DTBCLK_DTO2_PHASE 0 31 regDTBCLK_DTO3_PHASE 0 0x1b 1 0 2 DTBCLK_DTO3_PHASE 0 31 regDTBCLK_DTO0_MODULO 0 0x1f 1 0 2 DTBCLK_DTO0_MODULO 0 31 regDTBCLK_DTO1_MODULO 0 0x20 1 0 2 DTBCLK_DTO1_MODULO 0 31 regDTBCLK_DTO2_MODULO 0 0x21 1 0 2 DTBCLK_DTO2_MODULO 0 31 regDTBCLK_DTO3_MODULO 0 0x22 1 0 2 DTBCLK_DTO3_MODULO 0 31 regPHYASYMCLK_CLOCK_CNTL 0 0x52 2 0 2 PHYASYMCLK_FORCE_EN 0 0 PHYASYMCLK_FORCE_SRC_SEL 4 5 regPHYBSYMCLK_CLOCK_CNTL 0 0x53 2 0 2 PHYBSYMCLK_FORCE_EN 0 0 PHYBSYMCLK_FORCE_SRC_SEL 4 5 regPHYCSYMCLK_CLOCK_CNTL 0 0x54 2 0 2 PHYCSYMCLK_FORCE_EN 0 0 PHYCSYMCLK_FORCE_SRC_SEL 4 5 regPHYDSYMCLK_CLOCK_CNTL 0 0x55 2 0 2 PHYDSYMCLK_FORCE_EN 0 0 PHYDSYMCLK_FORCE_SRC_SEL 4 5 regPHYESYMCLK_CLOCK_CNTL 0 0x56 2 0 2 PHYESYMCLK_FORCE_EN 0 0 PHYESYMCLK_FORCE_SRC_SEL 4 5 regDCCG_GATE_DISABLE_CNTL3 0 0x5a 20 0 2 HDMISTREAMCLK0_GATE_DISABLE 0 0 HDMISTREAMCLK1_GATE_DISABLE 1 1 HDMISTREAMCLK2_GATE_DISABLE 2 2 HDMISTREAMCLK3_GATE_DISABLE 3 3 HDMISTREAMCLK4_GATE_DISABLE 4 4 HDMISTREAMCLK5_GATE_DISABLE 5 5 DPSTREAMCLK_ROOT_GATE_DISABLE 6 6 DPSTREAMCLK_GATE_DISABLE 7 7 SYMCLK32_ROOT_SE0_GATE_DISABLE 8 8 SYMCLK32_SE0_GATE_DISABLE 9 9 SYMCLK32_ROOT_SE1_GATE_DISABLE 10 10 SYMCLK32_SE1_GATE_DISABLE 11 11 SYMCLK32_ROOT_SE2_GATE_DISABLE 12 12 SYMCLK32_SE2_GATE_DISABLE 13 13 SYMCLK32_ROOT_SE3_GATE_DISABLE 14 14 SYMCLK32_SE3_GATE_DISABLE 15 15 SYMCLK32_ROOT_LE0_GATE_DISABLE 20 20 SYMCLK32_LE0_GATE_DISABLE 21 21 SYMCLK32_ROOT_LE1_GATE_DISABLE 22 22 SYMCLK32_LE1_GATE_DISABLE 23 23 regHDMISTREAMCLK0_DTO_PARAM 0 0x5b 2 0 2 HDMISTREAMCLK0_DTO_PHASE 0 7 HDMISTREAMCLK0_DTO_MODULO 16 23 regDCCG_AUDIO_DTBCLK_DTO_PHASE 0 0x61 1 0 2 DCCG_AUDIO_DTBCLK_DTO_PHASE 0 31 regDCCG_AUDIO_DTBCLK_DTO_MODULO 0 0x62 1 0 2 DCCG_AUDIO_DTBCLK_DTO_MODULO 0 31 regDTBCLK_DTO_DBUF_EN 0 0x63 4 0 2 DTBCLK_DTO0_DBUF_EN 0 0 DTBCLK_DTO1_DBUF_EN 1 1 DTBCLK_DTO2_DBUF_EN 2 2 DTBCLK_DTO3_DBUF_EN 3 3 regDC_PERFMON0_PERFCOUNTER_CNTL 0 0x0 11 0 2 PERFCOUNTER_EVENT_SEL 0 8 PERFCOUNTER_CVALUE_SEL 9 11 PERFCOUNTER_INC_MODE 12 14 PERFCOUNTER_HW_CNTL_SEL 15 15 PERFCOUNTER_RUNEN_MODE 16 16 PERFCOUNTER_CNTOFF_START_DIS 22 22 PERFCOUNTER_RESTART_EN 23 23 PERFCOUNTER_INT_EN 24 24 PERFCOUNTER_OFF_MASK 25 25 PERFCOUNTER_ACTIVE 26 26 PERFCOUNTER_CNTL_SEL 29 31 regDC_PERFMON0_PERFCOUNTER_CNTL2 0 0x1 5 0 2 PERFCOUNTER_COUNTED_VALUE_TYPE 0 1 PERFCOUNTER_HW_STOP1_SEL 2 2 PERFCOUNTER_HW_STOP2_SEL 3 3 PERFCOUNTER_CNTOFF_SEL 8 13 PERFCOUNTER_CNTL2_SEL 29 31 regDC_PERFMON0_PERFCOUNTER_STATE 0 0x2 16 0 2 PERFCOUNTER_CNT0_STATE 0 1 PERFCOUNTER_STATE_SEL0 2 2 PERFCOUNTER_CNT1_STATE 4 5 PERFCOUNTER_STATE_SEL1 6 6 PERFCOUNTER_CNT2_STATE 8 9 PERFCOUNTER_STATE_SEL2 10 10 PERFCOUNTER_CNT3_STATE 12 13 PERFCOUNTER_STATE_SEL3 14 14 PERFCOUNTER_CNT4_STATE 16 17 PERFCOUNTER_STATE_SEL4 18 18 PERFCOUNTER_CNT5_STATE 20 21 PERFCOUNTER_STATE_SEL5 22 22 PERFCOUNTER_CNT6_STATE 24 25 PERFCOUNTER_STATE_SEL6 26 26 PERFCOUNTER_CNT7_STATE 28 29 PERFCOUNTER_STATE_SEL7 30 30 regDC_PERFMON0_PERFMON_CNTL 0 0x3 6 0 2 PERFMON_STATE 0 1 PERFMON_RPT_COUNT 8 27 PERFMON_CNTOFF_AND_OR 28 28 PERFMON_CNTOFF_INT_EN 29 29 PERFMON_CNTOFF_INT_STATUS 30 30 PERFMON_CNTOFF_INT_ACK 31 31 regDC_PERFMON0_PERFMON_CNTL2 0 0x4 4 0 2 PERFMON_CNTOFF_INT_TYPE 0 0 PERFMON_CLK_ENABLE 1 1 PERFMON_RUN_ENABLE_START_SEL 2 9 PERFMON_RUN_ENABLE_STOP_SEL 10 17 regDC_PERFMON0_PERFMON_CVALUE_INT_MISC 0 0x5 17 0 2 PERFCOUNTER_INT0_STATUS 0 0 PERFCOUNTER_INT1_STATUS 1 1 PERFCOUNTER_INT2_STATUS 2 2 PERFCOUNTER_INT3_STATUS 3 3 PERFCOUNTER_INT4_STATUS 4 4 PERFCOUNTER_INT5_STATUS 5 5 PERFCOUNTER_INT6_STATUS 6 6 PERFCOUNTER_INT7_STATUS 7 7 PERFCOUNTER_INT0_ACK 8 8 PERFCOUNTER_INT1_ACK 9 9 PERFCOUNTER_INT2_ACK 10 10 PERFCOUNTER_INT3_ACK 11 11 PERFCOUNTER_INT4_ACK 12 12 PERFCOUNTER_INT5_ACK 13 13 PERFCOUNTER_INT6_ACK 14 14 PERFCOUNTER_INT7_ACK 15 15 PERFMON_CVALUE_HI 16 31 regDC_PERFMON0_PERFMON_CVALUE_LOW 0 0x6 1 0 2 PERFMON_CVALUE_LOW 0 31 regDC_PERFMON0_PERFMON_HI 0 0x7 2 0 2 PERFMON_HI 0 15 PERFMON_READ_SEL 29 31 regDC_PERFMON0_PERFMON_LOW 0 0x8 1 0 2 PERFMON_LOW 0 31 regDC_PERFMON1_PERFCOUNTER_CNTL 0 0xc 11 0 2 PERFCOUNTER_EVENT_SEL 0 8 PERFCOUNTER_CVALUE_SEL 9 11 PERFCOUNTER_INC_MODE 12 14 PERFCOUNTER_HW_CNTL_SEL 15 15 PERFCOUNTER_RUNEN_MODE 16 16 PERFCOUNTER_CNTOFF_START_DIS 22 22 PERFCOUNTER_RESTART_EN 23 23 PERFCOUNTER_INT_EN 24 24 PERFCOUNTER_OFF_MASK 25 25 PERFCOUNTER_ACTIVE 26 26 PERFCOUNTER_CNTL_SEL 29 31 regDC_PERFMON1_PERFCOUNTER_CNTL2 0 0xd 5 0 2 PERFCOUNTER_COUNTED_VALUE_TYPE 0 1 PERFCOUNTER_HW_STOP1_SEL 2 2 PERFCOUNTER_HW_STOP2_SEL 3 3 PERFCOUNTER_CNTOFF_SEL 8 13 PERFCOUNTER_CNTL2_SEL 29 31 regDC_PERFMON1_PERFCOUNTER_STATE 0 0xe 16 0 2 PERFCOUNTER_CNT0_STATE 0 1 PERFCOUNTER_STATE_SEL0 2 2 PERFCOUNTER_CNT1_STATE 4 5 PERFCOUNTER_STATE_SEL1 6 6 PERFCOUNTER_CNT2_STATE 8 9 PERFCOUNTER_STATE_SEL2 10 10 PERFCOUNTER_CNT3_STATE 12 13 PERFCOUNTER_STATE_SEL3 14 14 PERFCOUNTER_CNT4_STATE 16 17 PERFCOUNTER_STATE_SEL4 18 18 PERFCOUNTER_CNT5_STATE 20 21 PERFCOUNTER_STATE_SEL5 22 22 PERFCOUNTER_CNT6_STATE 24 25 PERFCOUNTER_STATE_SEL6 26 26 PERFCOUNTER_CNT7_STATE 28 29 PERFCOUNTER_STATE_SEL7 30 30 regDC_PERFMON1_PERFMON_CNTL 0 0xf 6 0 2 PERFMON_STATE 0 1 PERFMON_RPT_COUNT 8 27 PERFMON_CNTOFF_AND_OR 28 28 PERFMON_CNTOFF_INT_EN 29 29 PERFMON_CNTOFF_INT_STATUS 30 30 PERFMON_CNTOFF_INT_ACK 31 31 regDC_PERFMON1_PERFMON_CNTL2 0 0x10 4 0 2 PERFMON_CNTOFF_INT_TYPE 0 0 PERFMON_CLK_ENABLE 1 1 PERFMON_RUN_ENABLE_START_SEL 2 9 PERFMON_RUN_ENABLE_STOP_SEL 10 17 regDC_PERFMON1_PERFMON_CVALUE_INT_MISC 0 0x11 17 0 2 PERFCOUNTER_INT0_STATUS 0 0 PERFCOUNTER_INT1_STATUS 1 1 PERFCOUNTER_INT2_STATUS 2 2 PERFCOUNTER_INT3_STATUS 3 3 PERFCOUNTER_INT4_STATUS 4 4 PERFCOUNTER_INT5_STATUS 5 5 PERFCOUNTER_INT6_STATUS 6 6 PERFCOUNTER_INT7_STATUS 7 7 PERFCOUNTER_INT0_ACK 8 8 PERFCOUNTER_INT1_ACK 9 9 PERFCOUNTER_INT2_ACK 10 10 PERFCOUNTER_INT3_ACK 11 11 PERFCOUNTER_INT4_ACK 12 12 PERFCOUNTER_INT5_ACK 13 13 PERFCOUNTER_INT6_ACK 14 14 PERFCOUNTER_INT7_ACK 15 15 PERFMON_CVALUE_HI 16 31 regDC_PERFMON1_PERFMON_CVALUE_LOW 0 0x12 1 0 2 PERFMON_CVALUE_LOW 0 31 regDC_PERFMON1_PERFMON_HI 0 0x13 2 0 2 PERFMON_HI 0 15 PERFMON_READ_SEL 29 31 regDC_PERFMON1_PERFMON_LOW 0 0x14 1 0 2 PERFMON_LOW 0 31 regDMCU_CTRL 0 0xda 7 0 2 RESET_UC 0 0 IGNORE_PWRMGT 1 1 DISABLE_IRQ_TO_UC 2 2 DISABLE_XIRQ_TO_UC 3 3 DMCU_ENABLE 4 4 DMCU_DYN_CLK_GATING_EN 8 8 UC_REG_RD_TIMEOUT 16 31 regDMCU_STATUS 0 0xdb 3 0 2 UC_IN_RESET 0 0 UC_IN_WAIT_MODE 1 1 UC_IN_STOP_MODE 2 2 regDMCU_PC_START_ADDR 0 0xdc 2 0 2 PC_START_ADDR_LSB 0 7 PC_START_ADDR_MSB 8 15 regDMCU_FW_START_ADDR 0 0xdd 2 0 2 FW_START_ADDR_LSB 0 7 FW_START_ADDR_MSB 8 15 regDMCU_FW_END_ADDR 0 0xde 2 0 2 FW_END_ADDR_LSB 0 7 FW_END_ADDR_MSB 8 15 regDMCU_FW_ISR_START_ADDR 0 0xdf 2 0 2 FW_ISR_START_ADDR_LSB 0 7 FW_ISR_START_ADDR_MSB 8 15 regDMCU_FW_CS_HI 0 0xe0 1 0 2 FW_CHECKSUM_HI 0 31 regDMCU_FW_CS_LO 0 0xe1 1 0 2 FW_CHECKSUM_LO 0 31 regDMCU_RAM_ACCESS_CTRL 0 0xe2 6 0 2 ERAM_WR_ADDR_AUTO_INC 0 0 ERAM_RD_ADDR_AUTO_INC 1 1 IRAM_WR_ADDR_AUTO_INC 2 2 IRAM_RD_ADDR_AUTO_INC 3 3 ERAM_HOST_ACCESS_EN 4 4 IRAM_HOST_ACCESS_EN 5 5 regDMCU_ERAM_WR_CTRL 0 0xe3 3 0 2 ERAM_WR_ADDR 0 15 ERAM_WR_BE 16 19 ERAM_WR_BYTE_MODE 20 20 regDMCU_ERAM_WR_DATA 0 0xe4 1 0 2 ERAM_WR_DATA 0 31 regDMCU_ERAM_RD_CTRL 0 0xe5 3 0 2 ERAM_RD_ADDR 0 15 ERAM_RD_BE 16 19 ERAM_RD_BYTE_MODE 20 20 regDMCU_ERAM_RD_DATA 0 0xe6 1 0 2 ERAM_RD_DATA 0 31 regDMCU_IRAM_WR_CTRL 0 0xe7 1 0 2 IRAM_WR_ADDR 0 9 regDMCU_IRAM_WR_DATA 0 0xe8 1 0 2 IRAM_WR_DATA 0 7 regDMCU_IRAM_RD_CTRL 0 0xe9 1 0 2 IRAM_RD_ADDR 0 9 regDMCU_IRAM_RD_DATA 0 0xea 1 0 2 IRAM_RD_DATA 0 7 regDMCU_EVENT_TRIGGER 0 0xeb 3 0 2 GEN_SW_INT_TO_UC 0 0 UC_INTERNAL_INT_CODE 16 22 GEN_UC_INTERNAL_INT_TO_HOST 23 23 regDMCU_UC_INTERNAL_INT_STATUS 0 0xec 16 0 2 UC_INT_IRQ_N_PIN 0 0 UC_INT_XIRQ_N_PIN 1 1 UC_INT_SOFTWARE_INTERRUPT 2 2 UC_INT_ILLEGAL_OPCODE_TRAP 3 3 UC_INT_TIMER_OUTPUT_COMPARE_4 4 4 UC_INT_TIMER_OUTPUT_COMPARE_3 5 5 UC_INT_TIMER_OUTPUT_COMPARE_2 6 6 UC_INT_TIMER_OUTPUT_COMPARE_1 7 7 UC_INT_TIMER_OVERFLOW 8 8 UC_INT_REAL_TIME_INTERRUPT 9 9 UC_INT_TIMER_INPUT_CAPTURE_4_OUTPUT_COMPARE_5 10 10 UC_INT_TIMER_INPUT_CAPTURE_3 11 11 UC_INT_TIMER_INPUT_CAPTURE_2 12 12 UC_INT_TIMER_INPUT_CAPTURE_1 13 13 UC_INT_PULSE_ACCUMULATOR_INPUT_EDGE 14 14 UC_INT_PULSE_ACCUMULATOR_OVERFLOW 15 15 regDMCU_SS_INTERRUPT_CNTL_STATUS 0 0xed 18 0 2 STATIC_SCREEN1_INT_STATUS 13 13 STATIC_SCREEN1_INT_OCCURRED 14 14 STATIC_SCREEN1_INT_CLEAR 14 14 STATIC_SCREEN2_INT_STATUS 15 15 STATIC_SCREEN2_INT_OCCURRED 16 16 STATIC_SCREEN2_INT_CLEAR 16 16 STATIC_SCREEN3_INT_STATUS 17 17 STATIC_SCREEN3_INT_OCCURRED 18 18 STATIC_SCREEN3_INT_CLEAR 18 18 STATIC_SCREEN4_INT_STATUS 19 19 STATIC_SCREEN4_INT_OCCURRED 20 20 STATIC_SCREEN4_INT_CLEAR 20 20 STATIC_SCREEN5_INT_STATUS 21 21 STATIC_SCREEN5_INT_OCCURRED 22 22 STATIC_SCREEN5_INT_CLEAR 22 22 STATIC_SCREEN6_INT_STATUS 23 23 STATIC_SCREEN6_INT_OCCURRED 24 24 STATIC_SCREEN6_INT_CLEAR 24 24 regDMCU_INTERRUPT_TO_HOST_EN_MASK 0 0xf0 15 0 2 ABM0_HG_READY_INT_MASK 0 0 ABM0_LS_READY_INT_MASK 1 1 ABM0_BL_UPDATE_INT_MASK 2 2 ABM1_HG_READY_INT_MASK 3 3 ABM1_LS_READY_INT_MASK 4 4 ABM1_BL_UPDATE_INT_MASK 5 5 SCP_INT_MASK 9 9 UC_INTERNAL_INT_MASK 10 10 UC_REG_RD_TIMEOUT_INT_MASK 11 11 ABM2_HG_READY_INT_MASK 12 12 ABM2_LS_READY_INT_MASK 13 13 ABM2_BL_UPDATE_INT_MASK 14 14 ABM3_HG_READY_INT_MASK 15 15 ABM3_LS_READY_INT_MASK 16 16 ABM3_BL_UPDATE_INT_MASK 17 17 regDMCU_INTERRUPT_TO_UC_EN_MASK 0 0xf1 29 0 2 ABM1_HG_READY_INT_TO_UC_EN 0 0 ABM1_LS_READY_INT_TO_UC_EN 1 1 ABM1_BL_UPDATE_INT_TO_UC_EN 2 2 MCP_INT_TO_UC_EN 3 3 STATIC_SCREEN1_INT_TO_UC_EN 6 6 STATIC_SCREEN2_INT_TO_UC_EN 7 7 EXTERNAL_SW_INT_TO_UC_EN 8 8 STATIC_SCREEN3_INT_TO_UC_EN 9 9 STATIC_SCREEN4_INT_TO_UC_EN 10 10 STATIC_SCREEN5_INT_TO_UC_EN 11 11 DCPG_IHC_DOMAIN0_POWER_UP_INT_TO_UC_EN 12 12 DCPG_IHC_DOMAIN1_POWER_UP_INT_TO_UC_EN 13 13 DCPG_IHC_DOMAIN2_POWER_UP_INT_TO_UC_EN 14 14 DCPG_IHC_DOMAIN3_POWER_UP_INT_TO_UC_EN 15 15 DCPG_IHC_DOMAIN4_POWER_UP_INT_TO_UC_EN 16 16 DCPG_IHC_DOMAIN5_POWER_UP_INT_TO_UC_EN 17 17 DCPG_IHC_DOMAIN0_POWER_DOWN_INT_TO_UC_EN 18 18 DCPG_IHC_DOMAIN1_POWER_DOWN_INT_TO_UC_EN 19 19 DCPG_IHC_DOMAIN2_POWER_DOWN_INT_TO_UC_EN 20 20 DCPG_IHC_DOMAIN3_POWER_DOWN_INT_TO_UC_EN 21 21 DCPG_IHC_DOMAIN4_POWER_DOWN_INT_TO_UC_EN 22 22 DCPG_IHC_DOMAIN5_POWER_DOWN_INT_TO_UC_EN 23 23 VBLANK1_INT_TO_UC_EN 24 24 VBLANK2_INT_TO_UC_EN 25 25 VBLANK3_INT_TO_UC_EN 26 26 VBLANK4_INT_TO_UC_EN 27 27 VBLANK5_INT_TO_UC_EN 28 28 VBLANK6_INT_TO_UC_EN 29 29 STATIC_SCREEN6_INT_TO_UC_EN 30 30 regDMCU_INTERRUPT_TO_UC_EN_MASK_1 0 0xf2 13 0 2 OTG0_RANGE_TIMING_UPDATE_INT_TO_UC_EN 6 6 OTG1_RANGE_TIMING_UPDATE_INT_TO_UC_EN 7 7 OTG2_RANGE_TIMING_UPDATE_INT_TO_UC_EN 8 8 OTG3_RANGE_TIMING_UPDATE_INT_TO_UC_EN 9 9 OTG4_RANGE_TIMING_UPDATE_INT_TO_UC_EN 10 10 OTG5_RANGE_TIMING_UPDATE_INT_TO_UC_EN 11 11 DMCU_GENERIC_INT_TO_UC_EN 13 13 ABM2_HG_READY_INT_TO_UC_EN 14 14 ABM2_LS_READY_INT_TO_UC_EN 15 15 ABM2_BL_UPDATE_INT_TO_UC_EN 16 16 ABM3_HG_READY_INT_TO_UC_EN 17 17 ABM3_LS_READY_INT_TO_UC_EN 18 18 ABM3_BL_UPDATE_INT_TO_UC_EN 19 19 regDMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL 0 0xf3 29 0 2 ABM1_HG_READY_INT_XIRQ_IRQ_SEL 0 0 ABM1_LS_READY_INT_XIRQ_IRQ_SEL 1 1 ABM1_BL_UPDATE_INT_XIRQ_IRQ_SEL 2 2 MCP_INT_XIRQ_IRQ_SEL 3 3 STATIC_SCREEN1_INT_XIRQ_IRQ_SEL 6 6 STATIC_SCREEN2_INT_XIRQ_IRQ_SEL 7 7 EXTERNAL_SW_INT_XIRQ_IRQ_SEL 8 8 STATIC_SCREEN3_INT_XIRQ_IRQ_SEL 9 9 STATIC_SCREEN4_INT_XIRQ_IRQ_SEL 10 10 STATIC_SCREEN5_INT_XIRQ_IRQ_SEL 11 11 DCPG_IHC_DOMAIN0_POWER_UP_INT_XIRQ_IRQ_SEL 12 12 DCPG_IHC_DOMAIN1_POWER_UP_INT_XIRQ_IRQ_SEL 13 13 DCPG_IHC_DOMAIN2_POWER_UP_INT_XIRQ_IRQ_SEL 14 14 DCPG_IHC_DOMAIN3_POWER_UP_INT_XIRQ_IRQ_SEL 15 15 DCPG_IHC_DOMAIN4_POWER_UP_INT_XIRQ_IRQ_SEL 16 16 DCPG_IHC_DOMAIN5_POWER_UP_INT_XIRQ_IRQ_SEL 17 17 DCPG_IHC_DOMAIN0_POWER_DOWN_INT_XIRQ_IRQ_SEL 18 18 DCPG_IHC_DOMAIN1_POWER_DOWN_INT_XIRQ_IRQ_SEL 19 19 DCPG_IHC_DOMAIN2_POWER_DOWN_INT_XIRQ_IRQ_SEL 20 20 DCPG_IHC_DOMAIN3_POWER_DOWN_INT_XIRQ_IRQ_SEL 21 21 DCPG_IHC_DOMAIN4_POWER_DOWN_INT_XIRQ_IRQ_SEL 22 22 DCPG_IHC_DOMAIN5_POWER_DOWN_INT_XIRQ_IRQ_SEL 23 23 VBLANK1_INT_XIRQ_IRQ_SEL 24 24 VBLANK2_INT_XIRQ_IRQ_SEL 25 25 VBLANK3_INT_XIRQ_IRQ_SEL 26 26 VBLANK4_INT_XIRQ_IRQ_SEL 27 27 VBLANK5_INT_XIRQ_IRQ_SEL 28 28 VBLANK6_INT_XIRQ_IRQ_SEL 29 29 STATIC_SCREEN6_INT_XIRQ_IRQ_SEL 30 30 regDMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1 0 0xf4 13 0 2 OTG0_RANGE_TIMING_UPDATE_INT_XIRQ_IRQ_SEL 6 6 OTG1_RANGE_TIMING_UPDATE_INT_XIRQ_IRQ_SEL 7 7 OTG2_RANGE_TIMING_UPDATE_INT_XIRQ_IRQ_SEL 8 8 OTG3_RANGE_TIMING_UPDATE_INT_XIRQ_IRQ_SEL 9 9 OTG4_RANGE_TIMING_UPDATE_INT_XIRQ_IRQ_SEL 10 10 OTG5_RANGE_TIMING_UPDATE_INT_XIRQ_IRQ_SEL 11 11 DMCU_GENERIC_INT_XIRQ_IRQ_SEL 13 13 ABM2_HG_READY_INT_XIRQ_IRQ_SEL 14 14 ABM2_LS_READY_INT_XIRQ_IRQ_SEL 15 15 ABM2_BL_UPDATE_INT_XIRQ_IRQ_SEL 16 16 ABM3_HG_READY_INT_XIRQ_IRQ_SEL 17 17 ABM3_LS_READY_INT_XIRQ_IRQ_SEL 18 18 ABM3_BL_UPDATE_INT_XIRQ_IRQ_SEL 19 19 regDC_DMCU_SCRATCH 0 0xf5 1 0 2 DMCU_SCRATCH 0 31 regDMCU_INT_CNT 0 0xf6 3 0 2 DMCU_ABM1_HG_READY_INT_CNT 0 7 DMCU_ABM1_LS_READY_INT_CNT 8 15 DMCU_ABM1_BL_UPDATE_INT_CNT 16 23 regDMCU_FW_CHECKSUM_SMPL_BYTE_POS 0 0xf7 2 0 2 DMCU_FW_CHECKSUM_LO_SMPL_BYTE_POS 0 1 DMCU_FW_CHECKSUM_HI_SMPL_BYTE_POS 2 3 regDMCU_UC_CLK_GATING_CNTL 0 0xf8 3 0 2 UC_IRAM_RD_DELAY 0 2 UC_ERAM_RD_DELAY 8 10 UC_RBBM_RD_CLK_GATING_EN 16 16 regMASTER_COMM_DATA_REG1 0 0xf9 4 0 2 MASTER_COMM_DATA_REG1_BYTE0 0 7 MASTER_COMM_DATA_REG1_BYTE1 8 15 MASTER_COMM_DATA_REG1_BYTE2 16 23 MASTER_COMM_DATA_REG1_BYTE3 24 31 regMASTER_COMM_DATA_REG2 0 0xfa 4 0 2 MASTER_COMM_DATA_REG2_BYTE0 0 7 MASTER_COMM_DATA_REG2_BYTE1 8 15 MASTER_COMM_DATA_REG2_BYTE2 16 23 MASTER_COMM_DATA_REG2_BYTE3 24 31 regMASTER_COMM_DATA_REG3 0 0xfb 4 0 2 MASTER_COMM_DATA_REG3_BYTE0 0 7 MASTER_COMM_DATA_REG3_BYTE1 8 15 MASTER_COMM_DATA_REG3_BYTE2 16 23 MASTER_COMM_DATA_REG3_BYTE3 24 31 regMASTER_COMM_CMD_REG 0 0xfc 4 0 2 MASTER_COMM_CMD_REG_BYTE0 0 7 MASTER_COMM_CMD_REG_BYTE1 8 15 MASTER_COMM_CMD_REG_BYTE2 16 23 MASTER_COMM_CMD_REG_BYTE3 24 31 regMASTER_COMM_CNTL_REG 0 0xfd 1 0 2 MASTER_COMM_INTERRUPT 0 0 regSLAVE_COMM_DATA_REG1 0 0xfe 4 0 2 SLAVE_COMM_DATA_REG1_BYTE0 0 7 SLAVE_COMM_DATA_REG1_BYTE1 8 15 SLAVE_COMM_DATA_REG1_BYTE2 16 23 SLAVE_COMM_DATA_REG1_BYTE3 24 31 regSLAVE_COMM_DATA_REG2 0 0xff 4 0 2 SLAVE_COMM_DATA_REG2_BYTE0 0 7 SLAVE_COMM_DATA_REG2_BYTE1 8 15 SLAVE_COMM_DATA_REG2_BYTE2 16 23 SLAVE_COMM_DATA_REG2_BYTE3 24 31 regSLAVE_COMM_DATA_REG3 0 0x100 4 0 2 SLAVE_COMM_DATA_REG3_BYTE0 0 7 SLAVE_COMM_DATA_REG3_BYTE1 8 15 SLAVE_COMM_DATA_REG3_BYTE2 16 23 SLAVE_COMM_DATA_REG3_BYTE3 24 31 regSLAVE_COMM_CMD_REG 0 0x101 4 0 2 SLAVE_COMM_CMD_REG_BYTE0 0 7 SLAVE_COMM_CMD_REG_BYTE1 8 15 SLAVE_COMM_CMD_REG_BYTE2 16 23 SLAVE_COMM_CMD_REG_BYTE3 24 31 regSLAVE_COMM_CNTL_REG 0 0x102 2 0 2 SLAVE_COMM_INTERRUPT 0 0 COMM_PORT_MSG_TO_HOST_IN_PROGRESS 8 8 regDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1 0 0x10a 4 0 2 DMU_PERFMON_COUNTER_INT_TO_UC_EN 0 0 DIO_PERFMON_COUNTER_INT_TO_UC_EN 1 1 DCCG_PERFMON_COUNTER_INT_TO_UC_EN 2 2 HPO_PERFMON_COUNTER_INT_TO_UC_EN 3 3 regDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2 0 0x10b 9 0 2 HUBP0_PERFMON_COUNTER_INT_TO_UC_EN 0 0 HUBP1_PERFMON_COUNTER_INT_TO_UC_EN 1 1 HUBP2_PERFMON_COUNTER_INT_TO_UC_EN 2 2 HUBP3_PERFMON_COUNTER_INT_TO_UC_EN 3 3 HUBP4_PERFMON_COUNTER_INT_TO_UC_EN 4 4 HUBP5_PERFMON_COUNTER_INT_TO_UC_EN 5 5 HUBP6_PERFMON_COUNTER_INT_TO_UC_EN 6 6 HUBP7_PERFMON_COUNTER_INT_TO_UC_EN 7 7 HUBBUB_PERFMON_COUNTER_INT_TO_UC_EN 8 8 regDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3 0 0x10c 8 0 2 DPP0_PERFMON_COUNTER_INT_TO_UC_EN 0 0 DPP1_PERFMON_COUNTER_INT_TO_UC_EN 1 1 DPP2_PERFMON_COUNTER_INT_TO_UC_EN 2 2 DPP3_PERFMON_COUNTER_INT_TO_UC_EN 3 3 DPP4_PERFMON_COUNTER_INT_TO_UC_EN 4 4 DPP5_PERFMON_COUNTER_INT_TO_UC_EN 5 5 DPP6_PERFMON_COUNTER_INT_TO_UC_EN 6 6 DPP7_PERFMON_COUNTER_INT_TO_UC_EN 7 7 regDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4 0 0x10d 5 0 2 WB0_PERFMON_COUNTER_INT_TO_UC_EN 0 0 WB1_PERFMON_COUNTER_INT_TO_UC_EN 1 1 DCCG_PERFMON2_COUNTER_INT_TO_UC_EN 2 2 MMHUBBUB_PERFMON_COUNTER_INT_TO_UC_EN 3 3 WB2_PERFMON_COUNTER_INT_TO_UC_EN 4 4 regDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5 0 0x10e 10 0 2 MPC_PERFMON_COUNTER_INT_TO_UC_EN 0 0 OPP_PERFMON_COUNTER_INT_TO_UC_EN 1 1 OPTC_PERFMON_COUNTER_INT_TO_UC_EN 2 2 HDA_PERFMON_COUNTER_INT_TO_UC_EN 3 3 DSC0_PERFMON_COUNTER_INT_TO_UC_EN 4 4 DSC1_PERFMON_COUNTER_INT_TO_UC_EN 5 5 DSC2_PERFMON_COUNTER_INT_TO_UC_EN 6 6 DSC3_PERFMON_COUNTER_INT_TO_UC_EN 7 7 DSC4_PERFMON_COUNTER_INT_TO_UC_EN 8 8 DSC5_PERFMON_COUNTER_INT_TO_UC_EN 9 9 regDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1 0 0x10f 4 0 2 DMU_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL 0 0 DIO_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL 1 1 DCCG_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL 2 2 HPO_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL 3 3 regDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2 0 0x110 9 0 2 HUBP0_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL 0 0 HUBP1_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL 1 1 HUBP2_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL 2 2 HUBP3_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL 3 3 HUBP4_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL 4 4 HUBP5_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL 5 5 HUBP6_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL 6 6 HUBP7_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL 7 7 HUBBUB_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL 8 8 regDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3 0 0x111 8 0 2 DPP0_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL 0 0 DPP1_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL 1 1 DPP2_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL 2 2 DPP3_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL 3 3 DPP4_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL 4 4 DPP5_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL 5 5 DPP6_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL 6 6 DPP7_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL 7 7 regDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4 0 0x112 5 0 2 WB0_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL 0 0 WB1_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL 1 1 DCCG_PERFMON2_COUNTER_INT_XIRQ_IRQ_SEL 2 2 MMHUBBUB_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL 3 3 WB2_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL 4 4 regDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5 0 0x113 10 0 2 MPC_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL 0 0 OPTC_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL 1 1 OPP_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL 2 2 HDA_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL 3 3 DSC0_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL 4 4 DSC1_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL 5 5 DSC2_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL 6 6 DSC3_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL 7 7 DSC4_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL 8 8 DSC5_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL 9 9 regDMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1 0 0x115 29 0 2 DPRX_SD0P0_MSA_RECEIVED_INT_TO_UC_EN 0 0 DPRX_SD0P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_TO_UC_EN 1 1 DPRX_SD0P0_VERTICAL_INT0_TO_UC_EN 2 2 DPRX_SD0P0_VERTICAL_INT1_TO_UC_EN 3 3 DPRX_SD0P0_SDP_RECEIVED_INT_TO_UC_EN 4 4 DPRX_SD1P0_MSA_RECEIVED_INT_TO_UC_EN 5 5 DPRX_SD1P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_TO_UC_EN 6 6 DPRX_SD1P0_VERTICAL_INT0_TO_UC_EN 7 7 DPRX_SD1P0_VERTICAL_INT1_TO_UC_EN 8 8 DPRX_SD1P0_SDP_RECEIVED_INT_TO_UC_EN 9 9 DPRX_DPHY_P0_BS_INTERVAL_ERROR_THRESH_EXCEEDED_INT_TO_UC_EN 10 10 DPRX_DPHY_P0_SR_INTERVAL_ERROR_THRESH_EXCEEDED_INT_TO_UC_EN 11 11 DPRX_DPHY_P0_SYMBOL_ERROR_THRESH_EXCEEDED_INT_TO_UC_EN 12 12 DPRX_DPHY_P0_DISPARITY_ERROR_THRESH_EXCEEDED_INT_TO_UC_EN 13 13 DPRX_DPHY_P0_TRAINING_ERROR_THRESH_EXCEEDED_INT_TO_UC_EN 14 14 DPRX_DPHY_P0_TEST_PATTERN_ERROR_THRESH_EXCEEDED_INT_TO_UC_EN 15 15 DPRX_DPHY_P0_ECF_ERROR_THRESH_EXCEEDED_INT_TO_UC_EN 16 16 DPRX_DPHY_P0_DETECT_SR_LOCK_INT_TO_UC_EN 17 17 DPRX_DPHY_P0_LOSS_OF_ALIGN_INT_TO_UC_EN 18 18 DPRX_DPHY_P0_LOSS_OF_DESKEW_INT_TO_UC_EN 19 19 DPRX_DPHY_P0_EXCESSIVE_ERROR_INT_TO_UC_EN 20 20 DPRX_DPHY_P0_DESKEW_FIFO_OVERFLOW_INT_TO_UC_EN 21 21 DPRX_AUX_P0_AUX_INT_TO_UC_EN 22 22 DPRX_AUX_P0_I2C_INT_TO_UC_EN 23 23 DPRX_AUX_P0_CPU_INT_TO_UC_EN 24 24 DPRX_AUX_P0_MSG1_TIMEOUT_INT_TO_UC_EN 25 25 DPRX_AUX_P0_MSG2_TIMEOUT_INT_TO_UC_EN 26 26 DPRX_AUX_P0_MSG3_TIMEOUT_INT_TO_UC_EN 27 27 DPRX_AUX_P0_MSG4_TIMEOUT_INT_TO_UC_EN 28 28 regDMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1 0 0x116 29 0 2 DPRX_SD0P0_MSA_RECEIVED_INT_XIRQ_IRQ_SEL 0 0 DPRX_SD0P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_XIRQ_IRQ_SEL 1 1 DPRX_SD0P0_VERTICAL_INT0_XIRQ_IRQ_SEL 2 2 DPRX_SD0P0_VERTICAL_INT1_XIRQ_IRQ_SEL 3 3 DPRX_SD0P0_SDP_RECEIVED_INT_XIRQ_IRQ_SEL 4 4 DPRX_SD1P0_MSA_RECEIVED_INT_XIRQ_IRQ_SEL 5 5 DPRX_SD1P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_XIRQ_IRQ_SEL 6 6 DPRX_SD1P0_VERTICAL_INT0_XIRQ_IRQ_SEL 7 7 DPRX_SD1P0_VERTICAL_INT1_XIRQ_IRQ_SEL 8 8 DPRX_SD1P0_SDP_RECEIVED_INT_XIRQ_IRQ_SEL 9 9 DPRX_DPHY_P0_BS_INTERVAL_ERROR_THRESH_EXCEEDED_INT_XIRQ_IRQ_SEL 10 10 DPRX_DPHY_P0_SR_INTERVAL_ERROR_THRESH_EXCEEDED_INT_XIRQ_IRQ_SEL 11 11 DPRX_DPHY_P0_SYMBOL_ERROR_THRESH_EXCEEDED_INT_XIRQ_IRQ_SEL 12 12 DPRX_DPHY_P0_DISPARITY_ERROR_THRESH_EXCEEDED_INT_XIRQ_IRQ_SEL 13 13 DPRX_DPHY_P0_TRAINING_ERROR_THRESH_EXCEEDED_INT_XIRQ_IRQ_SEL 14 14 DPRX_DPHY_P0_TEST_PATTERN_ERROR_THRESH_EXCEEDED_INT_XIRQ_IRQ_SEL 15 15 DPRX_DPHY_P0_ECF_ERROR_THRESH_EXCEEDED_INT_XIRQ_IRQ_SEL 16 16 DPRX_DPHY_P0_DETECT_SR_LOCK_INT_XIRQ_IRQ_SEL 17 17 DPRX_DPHY_P0_LOSS_OF_ALIGN_INT_XIRQ_IRQ_SEL 18 18 DPRX_DPHY_P0_LOSS_OF_DESKEW_INT_XIRQ_IRQ_SEL 19 19 DPRX_DPHY_P0_EXCESSIVE_ERROR_INT_XIRQ_IRQ_SEL 20 20 DPRX_DPHY_P0_DESKEW_FIFO_OVERFLOW_INT_XIRQ_IRQ_SEL 21 21 DPRX_AUX_P0_AUX_INT_XIRQ_IRQ_SEL 22 22 DPRX_AUX_P0_I2C_INT_XIRQ_IRQ_SEL 23 23 DPRX_AUX_P0_CPU_INT_XIRQ_IRQ_SEL 24 24 DPRX_AUX_P0_MSG1_TIMEOUT_INT_XIRQ_IRQ_SEL 25 25 DPRX_AUX_P0_MSG2_TIMEOUT_INT_XIRQ_IRQ_SEL 26 26 DPRX_AUX_P0_MSG3_TIMEOUT_INT_XIRQ_IRQ_SEL 27 27 DPRX_AUX_P0_MSG4_TIMEOUT_INT_XIRQ_IRQ_SEL 28 28 regDMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE 0 0x11a 29 0 2 DCPG_IHC_DOMAIN6_POWER_UP_INT_TO_UC_EN 0 0 DCPG_IHC_DOMAIN7_POWER_UP_INT_TO_UC_EN 1 1 DCPG_IHC_DOMAIN8_POWER_UP_INT_TO_UC_EN 2 2 DCPG_IHC_DOMAIN9_POWER_UP_INT_TO_UC_EN 3 3 DCPG_IHC_DOMAIN10_POWER_UP_INT_TO_UC_EN 4 4 DCPG_IHC_DOMAIN11_POWER_UP_INT_TO_UC_EN 5 5 DCPG_IHC_DOMAIN12_POWER_UP_INT_TO_UC_EN 6 6 DCPG_IHC_DOMAIN13_POWER_UP_INT_TO_UC_EN 7 7 DCPG_IHC_DOMAIN14_POWER_UP_INT_TO_UC_EN 8 8 DCPG_IHC_DOMAIN15_POWER_UP_INT_TO_UC_EN 9 9 DCPG_IHC_DOMAIN6_POWER_DOWN_INT_TO_UC_EN 10 10 DCPG_IHC_DOMAIN7_POWER_DOWN_INT_TO_UC_EN 11 11 DCPG_IHC_DOMAIN8_POWER_DOWN_INT_TO_UC_EN 12 12 DCPG_IHC_DOMAIN9_POWER_DOWN_INT_TO_UC_EN 13 13 DCPG_IHC_DOMAIN10_POWER_DOWN_INT_TO_UC_EN 14 14 DCPG_IHC_DOMAIN11_POWER_DOWN_INT_TO_UC_EN 15 15 DCPG_IHC_DOMAIN12_POWER_DOWN_INT_TO_UC_EN 16 16 DCPG_IHC_DOMAIN13_POWER_DOWN_INT_TO_UC_EN 17 17 DCPG_IHC_DOMAIN14_POWER_DOWN_INT_TO_UC_EN 18 18 DCPG_IHC_DOMAIN15_POWER_DOWN_INT_TO_UC_EN 19 19 DCCG_DMCU_INT_VSYNC_CNT_OTG0_TO_UC_EN 20 20 DCCG_DMCU_INT_VSYNC_CNT_OTG1_TO_UC_EN 21 21 DCCG_DMCU_INT_VSYNC_CNT_OTG2_TO_UC_EN 22 22 DCCG_DMCU_INT_VSYNC_CNT_OTG3_TO_UC_EN 23 23 DCCG_DMCU_INT_VSYNC_CNT_OTG4_TO_UC_EN 24 24 DCCG_DMCU_INT_VSYNC_CNT_OTG5_TO_UC_EN 25 25 ABM0_HG_READY_INT_TO_UC_EN 26 26 ABM0_LS_READY_INT_TO_UC_EN 27 27 ABM0_BL_UPDATE_INT_TO_UC_EN 28 28 regDMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE 0 0x11b 29 0 2 DCPG_IHC_DOMAIN6_POWER_UP_INT_XIRQ_IRQ_SEL 0 0 DCPG_IHC_DOMAIN7_POWER_UP_INT_XIRQ_IRQ_SEL 1 1 DCPG_IHC_DOMAIN8_POWER_UP_INT_XIRQ_IRQ_SEL 2 2 DCPG_IHC_DOMAIN9_POWER_UP_INT_XIRQ_IRQ_SEL 3 3 DCPG_IHC_DOMAIN10_POWER_UP_INT_XIRQ_IRQ_SEL 4 4 DCPG_IHC_DOMAIN11_POWER_UP_INT_XIRQ_IRQ_SEL 5 5 DCPG_IHC_DOMAIN12_POWER_UP_INT_XIRQ_IRQ_SEL 6 6 DCPG_IHC_DOMAIN13_POWER_UP_INT_XIRQ_IRQ_SEL 7 7 DCPG_IHC_DOMAIN14_POWER_UP_INT_XIRQ_IRQ_SEL 8 8 DCPG_IHC_DOMAIN15_POWER_UP_INT_XIRQ_IRQ_SEL 9 9 DCPG_IHC_DOMAIN6_POWER_DOWN_INT_XIRQ_IRQ_SEL 10 10 DCPG_IHC_DOMAIN7_POWER_DOWN_INT_XIRQ_IRQ_SEL 11 11 DCPG_IHC_DOMAIN8_POWER_DOWN_INT_XIRQ_IRQ_SEL 12 12 DCPG_IHC_DOMAIN9_POWER_DOWN_INT_XIRQ_IRQ_SEL 13 13 DCPG_IHC_DOMAIN10_POWER_DOWN_INT_XIRQ_IRQ_SEL 14 14 DCPG_IHC_DOMAIN11_POWER_DOWN_INT_XIRQ_IRQ_SEL 15 15 DCPG_IHC_DOMAIN12_POWER_DOWN_INT_XIRQ_IRQ_SEL 16 16 DCPG_IHC_DOMAIN13_POWER_DOWN_INT_XIRQ_IRQ_SEL 17 17 DCPG_IHC_DOMAIN14_POWER_DOWN_INT_XIRQ_IRQ_SEL 18 18 DCPG_IHC_DOMAIN15_POWER_DOWN_INT_XIRQ_IRQ_SEL 19 19 DCCG_DMCU_INT_VSYNC_CNT_OTG0_XIRQ_IRQ_SEL 20 20 DCCG_DMCU_INT_VSYNC_CNT_OTG1_XIRQ_IRQ_SEL 21 21 DCCG_DMCU_INT_VSYNC_CNT_OTG2_XIRQ_IRQ_SEL 22 22 DCCG_DMCU_INT_VSYNC_CNT_OTG3_XIRQ_IRQ_SEL 23 23 DCCG_DMCU_INT_VSYNC_CNT_OTG4_XIRQ_IRQ_SEL 24 24 DCCG_DMCU_INT_VSYNC_CNT_OTG5_XIRQ_IRQ_SEL 25 25 ABM0_HG_READY_INT_XIRQ_IRQ_SEL 26 26 ABM0_LS_READY_INT_XIRQ_IRQ_SEL 27 27 ABM0_BL_UPDATE_INT_XIRQ_IRQ_SEL 28 28 regDMCU_INT_CNT_CONTINUE 0 0x11c 3 0 2 DMCU_ABM0_HG_READY_INT_CNT 0 7 DMCU_ABM0_LS_READY_INT_CNT 8 15 DMCU_ABM0_BL_UPDATE_INT_CNT 16 23 regDMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONT2 0 0x11d 19 0 2 DCPG_IHC_DOMAIN16_POWER_UP_INT_XIRQ_IRQ_SEL 0 0 DCPG_IHC_DOMAIN17_POWER_UP_INT_XIRQ_IRQ_SEL 1 1 DCPG_IHC_DOMAIN18_POWER_UP_INT_XIRQ_IRQ_SEL 2 2 DCPG_IHC_DOMAIN19_POWER_UP_INT_XIRQ_IRQ_SEL 3 3 DCPG_IHC_DOMAIN20_POWER_UP_INT_XIRQ_IRQ_SEL 4 4 DCPG_IHC_DOMAIN21_POWER_UP_INT_XIRQ_IRQ_SEL 5 5 DCPG_IHC_DOMAIN16_POWER_DOWN_INT_XIRQ_IRQ_SEL 6 6 DCPG_IHC_DOMAIN17_POWER_DOWN_INT_XIRQ_IRQ_SEL 7 7 DCPG_IHC_DOMAIN18_POWER_DOWN_INT_XIRQ_IRQ_SEL 8 8 DCPG_IHC_DOMAIN19_POWER_DOWN_INT_XIRQ_IRQ_SEL 9 9 DCPG_IHC_DOMAIN20_POWER_DOWN_INT_XIRQ_IRQ_SEL 10 10 DCPG_IHC_DOMAIN21_POWER_DOWN_INT_XIRQ_IRQ_SEL 11 11 DCIO_DPCS_TXA_INT_XIRQ_IRQ_SEL 16 16 DCIO_DPCS_TXB_INT_XIRQ_IRQ_SEL 17 17 DCIO_DPCS_TXC_INT_XIRQ_IRQ_SEL 18 18 DCIO_DPCS_TXD_INT_XIRQ_IRQ_SEL 19 19 DCIO_DPCS_TXE_INT_XIRQ_IRQ_SEL 20 20 DCIO_DPCS_TXF_INT_XIRQ_IRQ_SEL 21 21 DCIO_DPCS_TXG_INT_XIRQ_IRQ_SEL 22 22 regDMCU_INTERRUPT_TO_UC_EN_MASK_2 0 0x11f 19 0 2 DCPG_IHC_DOMAIN16_POWER_UP_INT_TO_UC_EN 0 0 DCPG_IHC_DOMAIN17_POWER_UP_INT_TO_UC_EN 1 1 DCPG_IHC_DOMAIN18_POWER_UP_INT_TO_UC_EN 2 2 DCPG_IHC_DOMAIN19_POWER_UP_INT_TO_UC_EN 3 3 DCPG_IHC_DOMAIN20_POWER_UP_INT_TO_UC_EN 4 4 DCPG_IHC_DOMAIN21_POWER_UP_INT_TO_UC_EN 5 5 DCPG_IHC_DOMAIN16_POWER_DOWN_INT_TO_UC_EN 6 6 DCPG_IHC_DOMAIN17_POWER_DOWN_INT_TO_UC_EN 7 7 DCPG_IHC_DOMAIN18_POWER_DOWN_INT_TO_UC_EN 8 8 DCPG_IHC_DOMAIN19_POWER_DOWN_INT_TO_UC_EN 9 9 DCPG_IHC_DOMAIN20_POWER_DOWN_INT_TO_UC_EN 10 10 DCPG_IHC_DOMAIN21_POWER_DOWN_INT_TO_UC_EN 11 11 DCIO_DPCS_TXA_INT_TO_UC_EN 16 16 DCIO_DPCS_TXB_INT_TO_UC_EN 17 17 DCIO_DPCS_TXC_INT_TO_UC_EN 18 18 DCIO_DPCS_TXD_INT_TO_UC_EN 19 19 DCIO_DPCS_TXE_INT_TO_UC_EN 20 20 DCIO_DPCS_TXF_INT_TO_UC_EN 21 21 DCIO_DPCS_TXG_INT_TO_UC_EN 22 22 regDMCU_INT_CNT_CONT2 0 0x120 3 0 2 DMCU_ABM2_HG_READY_INT_CNT 0 7 DMCU_ABM2_LS_READY_INT_CNT 8 15 DMCU_ABM2_BL_UPDATE_INT_CNT 16 23 regDMCU_INT_CNT_CONT3 0 0x121 3 0 2 DMCU_ABM3_HG_READY_INT_CNT 0 7 DMCU_ABM3_LS_READY_INT_CNT 8 15 DMCU_ABM3_BL_UPDATE_INT_CNT 16 23 regDMCUB_RBBMIF_SEC_CNTL 0 0x17a 3 0 2 DMCUB_RBBMIF_SEC_LVL 0 2 DMCUB_RBBMIF_TRUST_LVL 4 6 DMCUB_RBBMIF_SOURCE_ID 8 24 regRBBMIF_TIMEOUT 0 0x17f 2 0 2 RBBMIF_TIMEOUT_DELAY 0 19 RBBMIF_TIMEOUT_TO_REQ_HOLD 20 31 regRBBMIF_STATUS 0 0x180 1 0 2 RBBMIF_TIMEOUT_CLIENTS_DEC 0 31 regRBBMIF_STATUS_2 0 0x181 1 0 2 RBBMIF_TIMEOUT_CLIENTS_DEC_2 0 6 regRBBMIF_INT_STATUS 0 0x182 5 0 2 RBBMIF_TIMEOUT_ADDR 2 17 RBBMIF_TIMEOUT_OP 28 28 RBBMIF_TIMEOUT_RDWR_STATUS 29 29 RBBMIF_TIMEOUT_ACK 30 30 RBBMIF_TIMEOUT_MASK 31 31 regRBBMIF_TIMEOUT_DIS 0 0x183 32 0 2 CLIENT0_TIMEOUT_DIS 0 0 CLIENT1_TIMEOUT_DIS 1 1 CLIENT2_TIMEOUT_DIS 2 2 CLIENT3_TIMEOUT_DIS 3 3 CLIENT4_TIMEOUT_DIS 4 4 CLIENT5_TIMEOUT_DIS 5 5 CLIENT6_TIMEOUT_DIS 6 6 CLIENT7_TIMEOUT_DIS 7 7 CLIENT8_TIMEOUT_DIS 8 8 CLIENT9_TIMEOUT_DIS 9 9 CLIENT10_TIMEOUT_DIS 10 10 CLIENT11_TIMEOUT_DIS 11 11 CLIENT12_TIMEOUT_DIS 12 12 CLIENT13_TIMEOUT_DIS 13 13 CLIENT14_TIMEOUT_DIS 14 14 CLIENT15_TIMEOUT_DIS 15 15 CLIENT16_TIMEOUT_DIS 16 16 CLIENT17_TIMEOUT_DIS 17 17 CLIENT18_TIMEOUT_DIS 18 18 CLIENT19_TIMEOUT_DIS 19 19 CLIENT20_TIMEOUT_DIS 20 20 CLIENT21_TIMEOUT_DIS 21 21 CLIENT22_TIMEOUT_DIS 22 22 CLIENT23_TIMEOUT_DIS 23 23 CLIENT24_TIMEOUT_DIS 24 24 CLIENT25_TIMEOUT_DIS 25 25 CLIENT26_TIMEOUT_DIS 26 26 CLIENT27_TIMEOUT_DIS 27 27 CLIENT28_TIMEOUT_DIS 28 28 CLIENT29_TIMEOUT_DIS 29 29 CLIENT30_TIMEOUT_DIS 30 30 CLIENT31_TIMEOUT_DIS 31 31 regRBBMIF_TIMEOUT_DIS_2 0 0x184 7 0 2 CLIENT32_TIMEOUT_DIS 0 0 CLIENT33_TIMEOUT_DIS 1 1 CLIENT34_TIMEOUT_DIS 2 2 CLIENT35_TIMEOUT_DIS 3 3 CLIENT36_TIMEOUT_DIS 4 4 CLIENT37_TIMEOUT_DIS 5 5 CLIENT38_TIMEOUT_DIS 6 6 regRBBMIF_STATUS_FLAG 0 0x185 7 0 2 RBBMIF_STATE 0 1 RBBMIF_READ_TIMEOUT 4 4 RBBMIF_FIFO_EMPTY 5 5 RBBMIF_FIFO_FULL 6 6 RBBMIF_INVALID_ACCESS_FLAG 8 8 RBBMIF_INVALID_ACCESS_TYPE 9 11 RBBMIF_INVALID_ACCESS_ADDR 16 31 regDC_PERFMON2_PERFCOUNTER_CNTL 0 0xbe 11 0 2 PERFCOUNTER_EVENT_SEL 0 8 PERFCOUNTER_CVALUE_SEL 9 11 PERFCOUNTER_INC_MODE 12 14 PERFCOUNTER_HW_CNTL_SEL 15 15 PERFCOUNTER_RUNEN_MODE 16 16 PERFCOUNTER_CNTOFF_START_DIS 22 22 PERFCOUNTER_RESTART_EN 23 23 PERFCOUNTER_INT_EN 24 24 PERFCOUNTER_OFF_MASK 25 25 PERFCOUNTER_ACTIVE 26 26 PERFCOUNTER_CNTL_SEL 29 31 regDC_PERFMON2_PERFCOUNTER_CNTL2 0 0xbf 5 0 2 PERFCOUNTER_COUNTED_VALUE_TYPE 0 1 PERFCOUNTER_HW_STOP1_SEL 2 2 PERFCOUNTER_HW_STOP2_SEL 3 3 PERFCOUNTER_CNTOFF_SEL 8 13 PERFCOUNTER_CNTL2_SEL 29 31 regDC_PERFMON2_PERFCOUNTER_STATE 0 0xc0 16 0 2 PERFCOUNTER_CNT0_STATE 0 1 PERFCOUNTER_STATE_SEL0 2 2 PERFCOUNTER_CNT1_STATE 4 5 PERFCOUNTER_STATE_SEL1 6 6 PERFCOUNTER_CNT2_STATE 8 9 PERFCOUNTER_STATE_SEL2 10 10 PERFCOUNTER_CNT3_STATE 12 13 PERFCOUNTER_STATE_SEL3 14 14 PERFCOUNTER_CNT4_STATE 16 17 PERFCOUNTER_STATE_SEL4 18 18 PERFCOUNTER_CNT5_STATE 20 21 PERFCOUNTER_STATE_SEL5 22 22 PERFCOUNTER_CNT6_STATE 24 25 PERFCOUNTER_STATE_SEL6 26 26 PERFCOUNTER_CNT7_STATE 28 29 PERFCOUNTER_STATE_SEL7 30 30 regDC_PERFMON2_PERFMON_CNTL 0 0xc1 6 0 2 PERFMON_STATE 0 1 PERFMON_RPT_COUNT 8 27 PERFMON_CNTOFF_AND_OR 28 28 PERFMON_CNTOFF_INT_EN 29 29 PERFMON_CNTOFF_INT_STATUS 30 30 PERFMON_CNTOFF_INT_ACK 31 31 regDC_PERFMON2_PERFMON_CNTL2 0 0xc2 4 0 2 PERFMON_CNTOFF_INT_TYPE 0 0 PERFMON_CLK_ENABLE 1 1 PERFMON_RUN_ENABLE_START_SEL 2 9 PERFMON_RUN_ENABLE_STOP_SEL 10 17 regDC_PERFMON2_PERFMON_CVALUE_INT_MISC 0 0xc3 17 0 2 PERFCOUNTER_INT0_STATUS 0 0 PERFCOUNTER_INT1_STATUS 1 1 PERFCOUNTER_INT2_STATUS 2 2 PERFCOUNTER_INT3_STATUS 3 3 PERFCOUNTER_INT4_STATUS 4 4 PERFCOUNTER_INT5_STATUS 5 5 PERFCOUNTER_INT6_STATUS 6 6 PERFCOUNTER_INT7_STATUS 7 7 PERFCOUNTER_INT0_ACK 8 8 PERFCOUNTER_INT1_ACK 9 9 PERFCOUNTER_INT2_ACK 10 10 PERFCOUNTER_INT3_ACK 11 11 PERFCOUNTER_INT4_ACK 12 12 PERFCOUNTER_INT5_ACK 13 13 PERFCOUNTER_INT6_ACK 14 14 PERFCOUNTER_INT7_ACK 15 15 PERFMON_CVALUE_HI 16 31 regDC_PERFMON2_PERFMON_CVALUE_LOW 0 0xc4 1 0 2 PERFMON_CVALUE_LOW 0 31 regDC_PERFMON2_PERFMON_HI 0 0xc5 2 0 2 PERFMON_HI 0 15 PERFMON_READ_SEL 29 31 regDC_PERFMON2_PERFMON_LOW 0 0xc6 1 0 2 PERFMON_LOW 0 31 regDC_GPU_TIMER_START_POSITION_V_UPDATE 0 0x126 6 0 2 DC_GPU_TIMER_START_POSITION_D1_V_UPDATE 0 2 DC_GPU_TIMER_START_POSITION_D2_V_UPDATE 4 6 DC_GPU_TIMER_START_POSITION_D3_V_UPDATE 8 10 DC_GPU_TIMER_START_POSITION_D4_V_UPDATE 12 14 DC_GPU_TIMER_START_POSITION_D5_V_UPDATE 16 18 DC_GPU_TIMER_START_POSITION_D6_V_UPDATE 20 22 regDC_GPU_TIMER_START_POSITION_VSTARTUP 0 0x127 6 0 2 DC_GPU_TIMER_START_POSITION_D1_VSTARTUP 0 2 DC_GPU_TIMER_START_POSITION_D2_VSTARTUP 4 6 DC_GPU_TIMER_START_POSITION_D3_VSTARTUP 8 10 DC_GPU_TIMER_START_POSITION_D4_VSTARTUP 12 14 DC_GPU_TIMER_START_POSITION_D5_VSTARTUP 16 18 DC_GPU_TIMER_START_POSITION_D6_VSTARTUP 20 22 regDC_GPU_TIMER_READ 0 0x128 1 0 2 DC_GPU_TIMER_READ 0 31 regDC_GPU_TIMER_READ_CNTL 0 0x129 7 0 2 DC_GPU_TIMER_READ_SELECT 0 6 DC_GPU_TIMER_START_POSITION_D1_VSYNC_NOM 8 10 DC_GPU_TIMER_START_POSITION_D2_VSYNC_NOM 11 13 DC_GPU_TIMER_START_POSITION_D3_VSYNC_NOM 14 16 DC_GPU_TIMER_START_POSITION_D4_VSYNC_NOM 17 19 DC_GPU_TIMER_START_POSITION_D5_VSYNC_NOM 20 22 DC_GPU_TIMER_START_POSITION_D6_VSYNC_NOM 23 25 regDC_GPU_TIMER_START_POSITION_VREADY 0 0x141 6 0 2 DC_GPU_TIMER_START_POSITION_D1_VREADY 0 2 DC_GPU_TIMER_START_POSITION_D2_VREADY 4 6 DC_GPU_TIMER_START_POSITION_D3_VREADY 8 10 DC_GPU_TIMER_START_POSITION_D4_VREADY 12 14 DC_GPU_TIMER_START_POSITION_D5_VREADY 16 18 DC_GPU_TIMER_START_POSITION_D6_VREADY 20 22 regDC_GPU_TIMER_START_POSITION_FLIP 0 0x142 8 0 2 DC_GPU_TIMER_START_POSITION_D1_FLIP 0 2 DC_GPU_TIMER_START_POSITION_D2_FLIP 4 6 DC_GPU_TIMER_START_POSITION_D3_FLIP 8 10 DC_GPU_TIMER_START_POSITION_D4_FLIP 12 14 DC_GPU_TIMER_START_POSITION_D5_FLIP 16 18 DC_GPU_TIMER_START_POSITION_D6_FLIP 20 22 DC_GPU_TIMER_START_POSITION_D7_FLIP 24 26 DC_GPU_TIMER_START_POSITION_D8_FLIP 28 30 regDC_GPU_TIMER_START_POSITION_V_UPDATE_NO_LOCK 0 0x143 6 0 2 DC_GPU_TIMER_START_POSITION_D1_V_UPDATE_NO_LOCK 0 2 DC_GPU_TIMER_START_POSITION_D2_V_UPDATE_NO_LOCK 4 6 DC_GPU_TIMER_START_POSITION_D3_V_UPDATE_NO_LOCK 8 10 DC_GPU_TIMER_START_POSITION_D4_V_UPDATE_NO_LOCK 12 14 DC_GPU_TIMER_START_POSITION_D5_V_UPDATE_NO_LOCK 16 18 DC_GPU_TIMER_START_POSITION_D6_V_UPDATE_NO_LOCK 20 22 regDC_GPU_TIMER_START_POSITION_FLIP_AWAY 0 0x144 8 0 2 DC_GPU_TIMER_START_POSITION_D1_FLIP_AWAY 0 2 DC_GPU_TIMER_START_POSITION_D2_FLIP_AWAY 4 6 DC_GPU_TIMER_START_POSITION_D3_FLIP_AWAY 8 10 DC_GPU_TIMER_START_POSITION_D4_FLIP_AWAY 12 14 DC_GPU_TIMER_START_POSITION_D5_FLIP_AWAY 16 18 DC_GPU_TIMER_START_POSITION_D6_FLIP_AWAY 20 22 DC_GPU_TIMER_START_POSITION_D7_FLIP_AWAY 24 26 DC_GPU_TIMER_START_POSITION_D8_FLIP_AWAY 28 30 regDCCG_INTERRUPT_DEST 0 0x148 10 0 2 DCCG_IHC_VSYNC_OTG0_LATCH_INT_DEST 0 0 DCCG_IHC_VSYNC_OTG1_LATCH_INT_DEST 1 1 DCCG_IHC_VSYNC_OTG2_LATCH_INT_DEST 2 2 DCCG_IHC_VSYNC_OTG3_LATCH_INT_DEST 3 3 DCCG_IHC_VSYNC_OTG4_LATCH_INT_DEST 4 4 DCCG_IHC_VSYNC_OTG5_LATCH_INT_DEST 5 5 DCCG_IHC_PERFMON_COUNTER0_INTERRUPT_DEST 12 12 DCCG_IHC_PERFMON_COUNTER1_INTERRUPT_DEST 13 13 DCCG_IHC_PERFMON2_COUNTER0_INTERRUPT_DEST 14 14 DCCG_IHC_PERFMON2_COUNTER1_INTERRUPT_DEST 15 15 regDMU_INTERRUPT_DEST 0 0x149 25 0 2 DMCUB_IHC_TIMER0_INT_DEST 0 0 DMCUB_IHC_TIMER1_INT_DEST 1 1 DMCUB_IHC_GPINT0_INT_DEST 2 2 DMCUB_IHC_GPINT1_INT_DEST 3 3 DMCUB_IHC_INBOX0_READY_INT_DEST 4 4 DMCUB_IHC_INBOX0_DONE_INT_DEST 5 5 DMCUB_IHC_INBOX1_READY_INT_DEST 6 6 DMCUB_IHC_INBOX1_DONE_INT_DEST 7 7 DMCUB_IHC_OUTBOX0_READY_INT_DEST 8 8 DMCUB_IHC_OUTBOX0_DONE_INT_DEST 9 9 DMCUB_IHC_OUTBOX1_READY_INT_DEST 10 10 DMCUB_IHC_OUTBOX1_DONE_INT_DEST 11 11 DMU_IHC_PERFMON_COUNTER0_INTERRUPT_DEST 12 12 DMU_IHC_PERFMON_COUNTER1_INTERRUPT_DEST 13 13 DMCU_IHC_ABM0_HG_READY_INTERRUPT_DEST 14 14 DMCU_IHC_ABM0_LS_READY_INTERRUPT_DEST 15 15 DMCU_IHC_ABM0_BL_UPDATE_INTERRUPT_DEST 16 16 DMCU_IHC_ABM1_HG_READY_INTERRUPT_DEST 17 17 DMCU_IHC_ABM1_LS_READY_INTERRUPT_DEST 18 18 DMCU_IHC_ABM1_BL_UPDATE_INTERRUPT_DEST 19 19 DMCUB_IHC_GPINT2_INT_DEST 24 24 DMCUB_IHC_UNDEFINED_ADDRESS_FAULT_INT_DEST 25 25 RBBMIF_IHC_TIMEOUT_INTERRUPT_DEST 26 26 DMCU_IHC_DMCU_INTERNAL_INTERRUPT_DEST 27 27 DMCU_IHC_SCP_INTERRUPT_DEST 28 28 regDMU_INTERRUPT_DEST2 0 0x14a 12 0 2 DMCU_IHC_ABM2_HG_READY_INTERRUPT_DEST 0 0 DMCU_IHC_ABM2_LS_READY_INTERRUPT_DEST 1 1 DMCU_IHC_ABM2_BL_UPDATE_INTERRUPT_DEST 2 2 DMCU_IHC_ABM3_HG_READY_INTERRUPT_DEST 3 3 DMCU_IHC_ABM3_LS_READY_INTERRUPT_DEST 4 4 DMCU_IHC_ABM3_BL_UPDATE_INTERRUPT_DEST 5 5 DMCU_IHC_ABM4_HG_READY_INTERRUPT_DEST 6 6 DMCU_IHC_ABM4_LS_READY_INTERRUPT_DEST 7 7 DMCU_IHC_ABM4_BL_UPDATE_INTERRUPT_DEST 8 8 DMCU_IHC_ABM5_HG_READY_INTERRUPT_DEST 9 9 DMCU_IHC_ABM5_LS_READY_INTERRUPT_DEST 10 10 DMCU_IHC_ABM5_BL_UPDATE_INTERRUPT_DEST 11 11 regDCPG_INTERRUPT_DEST 0 0x14b 16 0 2 DCPG_IHC_DOMAIN0_POWER_UP_INTERRUPT_DEST 0 0 DCPG_IHC_DOMAIN1_POWER_UP_INTERRUPT_DEST 1 1 DCPG_IHC_DOMAIN2_POWER_UP_INTERRUPT_DEST 2 2 DCPG_IHC_DOMAIN3_POWER_UP_INTERRUPT_DEST 3 3 DCPG_IHC_DOMAIN4_POWER_UP_INTERRUPT_DEST 4 4 DCPG_IHC_DOMAIN5_POWER_UP_INTERRUPT_DEST 5 5 DCPG_IHC_DOMAIN6_POWER_UP_INTERRUPT_DEST 6 6 DCPG_IHC_DOMAIN7_POWER_UP_INTERRUPT_DEST 7 7 DCPG_IHC_DOMAIN0_POWER_DOWN_INTERRUPT_DEST 16 16 DCPG_IHC_DOMAIN1_POWER_DOWN_INTERRUPT_DEST 17 17 DCPG_IHC_DOMAIN2_POWER_DOWN_INTERRUPT_DEST 18 18 DCPG_IHC_DOMAIN3_POWER_DOWN_INTERRUPT_DEST 19 19 DCPG_IHC_DOMAIN4_POWER_DOWN_INTERRUPT_DEST 20 20 DCPG_IHC_DOMAIN5_POWER_DOWN_INTERRUPT_DEST 21 21 DCPG_IHC_DOMAIN6_POWER_DOWN_INTERRUPT_DEST 22 22 DCPG_IHC_DOMAIN7_POWER_DOWN_INTERRUPT_DEST 23 23 regDCPG_INTERRUPT_DEST2 0 0x14c 12 0 2 DCPG_IHC_DOMAIN16_POWER_UP_INTERRUPT_DEST 0 0 DCPG_IHC_DOMAIN17_POWER_UP_INTERRUPT_DEST 1 1 DCPG_IHC_DOMAIN18_POWER_UP_INTERRUPT_DEST 2 2 DCPG_IHC_DOMAIN19_POWER_UP_INTERRUPT_DEST 3 3 DCPG_IHC_DOMAIN20_POWER_UP_INTERRUPT_DEST 4 4 DCPG_IHC_DOMAIN21_POWER_UP_INTERRUPT_DEST 5 5 DCPG_IHC_DOMAIN16_POWER_DOWN_INTERRUPT_DEST 6 6 DCPG_IHC_DOMAIN17_POWER_DOWN_INTERRUPT_DEST 7 7 DCPG_IHC_DOMAIN18_POWER_DOWN_INTERRUPT_DEST 8 8 DCPG_IHC_DOMAIN19_POWER_DOWN_INTERRUPT_DEST 9 9 DCPG_IHC_DOMAIN20_POWER_DOWN_INTERRUPT_DEST 10 10 DCPG_IHC_DOMAIN21_POWER_DOWN_INTERRUPT_DEST 11 11 regMMHUBBUB_INTERRUPT_DEST 0 0x14d 9 0 2 VGA_IHC_VGA_CRT_INTERRUPT_DEST 0 0 BUFMGR_CWB0_IHIF_INTERRUPT_DEST 1 1 BUFMGR_CWB1_IHIF_INTERRUPT_DEST 2 2 BUFMGR_DWB0_IHIF_INTERRUPT_DEST 3 3 BUFMGR_DWB1_IHIF_INTERRUPT_DEST 4 4 BUFMGR_DWB2_IHIF_INTERRUPT_DEST 5 5 MMHUBBUB_IHC_WARMUP_INTERRUPT_DEST 8 8 MMHUBBUB_IHC_PERFMON_COUNTER0_INTERRUPT_DEST 12 12 MMHUBBUB_IHC_PERFMON_COUNTER1_INTERRUPT_DEST 13 13 regWB_INTERRUPT_DEST 0 0x14e 9 0 2 WBSCL0_IHIF_DATA_OVERFLOW_INTERRUPT_DEST 1 1 WBSCL1_IHIF_DATA_OVERFLOW_INTERRUPT_DEST 9 9 WBSCL2_IHIF_DATA_OVERFLOW_INTERRUPT_DEST 11 11 WB0_IHC_PERFMON_COUNTER0_INTERRUPT_DEST 12 12 WB0_IHC_PERFMON_COUNTER1_INTERRUPT_DEST 13 13 WB1_IHC_PERFMON_COUNTER0_INTERRUPT_DEST 14 14 WB1_IHC_PERFMON_COUNTER1_INTERRUPT_DEST 15 15 WB2_IHC_PERFMON_COUNTER0_INTERRUPT_DEST 16 16 WB2_IHC_PERFMON_COUNTER1_INTERRUPT_DEST 17 17 regDCHUB_INTERRUPT_DEST 0 0x14f 32 0 2 HUBP0_IHC_VBLANK_INTERRUPT_DEST 0 0 HUBP0_IHC_VLINE_INTERRUPT_DEST 1 1 HUBP0_IHC_VLINE2_INTERRUPT_DEST 2 2 HUBP0_IHC_TIMEOUT_INTERRUPT_DEST 3 3 HUBP1_IHC_VBLANK_INTERRUPT_DEST 4 4 HUBP1_IHC_VLINE_INTERRUPT_DEST 5 5 HUBP1_IHC_VLINE2_INTERRUPT_DEST 6 6 HUBP1_IHC_TIMEOUT_INTERRUPT_DEST 7 7 HUBP2_IHC_VBLANK_INTERRUPT_DEST 8 8 HUBP2_IHC_VLINE_INTERRUPT_DEST 9 9 HUBP2_IHC_VLINE2_INTERRUPT_DEST 10 10 HUBP2_IHC_TIMEOUT_INTERRUPT_DEST 11 11 HUBP3_IHC_VBLANK_INTERRUPT_DEST 12 12 HUBP3_IHC_VLINE_INTERRUPT_DEST 13 13 HUBP3_IHC_VLINE2_INTERRUPT_DEST 14 14 HUBP3_IHC_TIMEOUT_INTERRUPT_DEST 15 15 HUBP4_IHC_VBLANK_INTERRUPT_DEST 16 16 HUBP4_IHC_VLINE_INTERRUPT_DEST 17 17 HUBP4_IHC_VLINE2_INTERRUPT_DEST 18 18 HUBP4_IHC_TIMEOUT_INTERRUPT_DEST 19 19 HUBP5_IHC_VBLANK_INTERRUPT_DEST 20 20 HUBP5_IHC_VLINE_INTERRUPT_DEST 21 21 HUBP5_IHC_VLINE2_INTERRUPT_DEST 22 22 HUBP5_IHC_TIMEOUT_INTERRUPT_DEST 23 23 HUBP6_IHC_VBLANK_INTERRUPT_DEST 24 24 HUBP6_IHC_VLINE_INTERRUPT_DEST 25 25 HUBP6_IHC_VLINE2_INTERRUPT_DEST 26 26 HUBP6_IHC_TIMEOUT_INTERRUPT_DEST 27 27 HUBP7_IHC_VBLANK_INTERRUPT_DEST 28 28 HUBP7_IHC_VLINE_INTERRUPT_DEST 29 29 HUBP7_IHC_VLINE2_INTERRUPT_DEST 30 30 HUBP7_IHC_TIMEOUT_INTERRUPT_DEST 31 31 regDCHUB_PERFCOUNTER_INTERRUPT_DEST 0 0x150 18 0 2 HUBBUB_IHC_PERFMON_COUNTER0_INTERRUPT_DEST 12 12 HUBBUB_IHC_PERFMON_COUNTER1_INTERRUPT_DEST 13 13 HUBP0_IHC_PERFMON_COUNTER0_INTERRUPT_DEST 14 14 HUBP0_IHC_PERFMON_COUNTER1_INTERRUPT_DEST 15 15 HUBP1_IHC_PERFMON_COUNTER0_INTERRUPT_DEST 16 16 HUBP1_IHC_PERFMON_COUNTER1_INTERRUPT_DEST 17 17 HUBP2_IHC_PERFMON_COUNTER0_INTERRUPT_DEST 18 18 HUBP2_IHC_PERFMON_COUNTER1_INTERRUPT_DEST 19 19 HUBP3_IHC_PERFMON_COUNTER0_INTERRUPT_DEST 20 20 HUBP3_IHC_PERFMON_COUNTER1_INTERRUPT_DEST 21 21 HUBP4_IHC_PERFMON_COUNTER0_INTERRUPT_DEST 22 22 HUBP4_IHC_PERFMON_COUNTER1_INTERRUPT_DEST 23 23 HUBP5_IHC_PERFMON_COUNTER0_INTERRUPT_DEST 24 24 HUBP5_IHC_PERFMON_COUNTER1_INTERRUPT_DEST 25 25 HUBP6_IHC_PERFMON_COUNTER0_INTERRUPT_DEST 26 26 HUBP6_IHC_PERFMON_COUNTER1_INTERRUPT_DEST 27 27 HUBP7_IHC_PERFMON_COUNTER0_INTERRUPT_DEST 28 28 HUBP7_IHC_PERFMON_COUNTER1_INTERRUPT_DEST 29 29 regDCHUB_INTERRUPT_DEST2 0 0x151 19 0 2 HUBP0_IHC_FLIP_INTERRUPT_DEST 0 0 HUBP0_IHC_FLIP_AWAY_INTERRUPT_DEST 1 1 HUBP1_IHC_FLIP_INTERRUPT_DEST 2 2 HUBP1_IHC_FLIP_AWAY_INTERRUPT_DEST 3 3 HUBP2_IHC_FLIP_INTERRUPT_DEST 4 4 HUBP2_IHC_FLIP_AWAY_INTERRUPT_DEST 5 5 HUBP3_IHC_FLIP_INTERRUPT_DEST 6 6 HUBP3_IHC_FLIP_AWAY_INTERRUPT_DEST 7 7 HUBP4_IHC_FLIP_INTERRUPT_DEST 8 8 HUBP4_IHC_FLIP_AWAY_INTERRUPT_DEST 9 9 HUBP5_IHC_FLIP_INTERRUPT_DEST 10 10 HUBP5_IHC_FLIP_AWAY_INTERRUPT_DEST 11 11 HUBP6_IHC_FLIP_INTERRUPT_DEST 12 12 HUBP6_IHC_FLIP_AWAY_INTERRUPT_DEST 13 13 HUBP7_IHC_FLIP_INTERRUPT_DEST 14 14 HUBP7_IHC_FLIP_AWAY_INTERRUPT_DEST 15 15 HUBBUB_IHC_VM_FAULT_INTERRUPT_DEST 24 24 HUBBUB_IHC_TIMEOUT_INTERRUPT_DEST 25 25 HUBBUB_IHC_COMPBUF_SIZE_CHANGE_INTERRUPT_DEST 26 26 regDPP_PERFCOUNTER_INTERRUPT_DEST 0 0x152 16 0 2 DPP0_IHC_PERFMON_COUNTER0_INTERRUPT_DEST 12 12 DPP0_IHC_PERFMON_COUNTER1_INTERRUPT_DEST 13 13 DPP1_IHC_PERFMON_COUNTER0_INTERRUPT_DEST 14 14 DPP1_IHC_PERFMON_COUNTER1_INTERRUPT_DEST 15 15 DPP2_IHC_PERFMON_COUNTER0_INTERRUPT_DEST 16 16 DPP2_IHC_PERFMON_COUNTER1_INTERRUPT_DEST 17 17 DPP3_IHC_PERFMON_COUNTER0_INTERRUPT_DEST 18 18 DPP3_IHC_PERFMON_COUNTER1_INTERRUPT_DEST 19 19 DPP4_IHC_PERFMON_COUNTER0_INTERRUPT_DEST 20 20 DPP4_IHC_PERFMON_COUNTER1_INTERRUPT_DEST 21 21 DPP5_IHC_PERFMON_COUNTER0_INTERRUPT_DEST 22 22 DPP5_IHC_PERFMON_COUNTER1_INTERRUPT_DEST 23 23 DPP6_IHC_PERFMON_COUNTER0_INTERRUPT_DEST 24 24 DPP6_IHC_PERFMON_COUNTER1_INTERRUPT_DEST 25 25 DPP7_IHC_PERFMON_COUNTER0_INTERRUPT_DEST 26 26 DPP7_IHC_PERFMON_COUNTER1_INTERRUPT_DEST 27 27 regMPC_INTERRUPT_DEST 0 0x153 10 0 2 MPCC0_STALL_INTERRUPT_DEST 0 0 MPCC1_STALL_INTERRUPT_DEST 1 1 MPCC2_STALL_INTERRUPT_DEST 2 2 MPCC3_STALL_INTERRUPT_DEST 3 3 MPCC4_STALL_INTERRUPT_DEST 4 4 MPCC5_STALL_INTERRUPT_DEST 5 5 MPCC6_STALL_INTERRUPT_DEST 6 6 MPCC7_STALL_INTERRUPT_DEST 7 7 MPC_IHC_PERFMON_COUNTER0_INTERRUPT_DEST 12 12 MPC_IHC_PERFMON_COUNTER1_INTERRUPT_DEST 13 13 regOPP_INTERRUPT_DEST 0 0x154 2 0 2 OPP_IHC_PERFMON_COUNTER0_INTERRUPT_DEST 12 12 OPP_IHC_PERFMON_COUNTER1_INTERRUPT_DEST 13 13 regOPTC_INTERRUPT_DEST 0 0x155 8 0 2 OPTC_IHC_PERFMON_COUNTER0_INTERRUPT_DEST 12 12 OPTC_IHC_PERFMON_COUNTER1_INTERRUPT_DEST 13 13 OPTC0_IHC_DATA_UNDERFLOW_INTERRUPT_DEST 24 24 OPTC1_IHC_DATA_UNDERFLOW_INTERRUPT_DEST 25 25 OPTC2_IHC_DATA_UNDERFLOW_INTERRUPT_DEST 26 26 OPTC3_IHC_DATA_UNDERFLOW_INTERRUPT_DEST 27 27 OPTC4_IHC_DATA_UNDERFLOW_INTERRUPT_DEST 28 28 OPTC5_IHC_DATA_UNDERFLOW_INTERRUPT_DEST 29 29 regOTG0_INTERRUPT_DEST 0 0x156 18 0 2 OTG0_IHC_CPU_SS_INTERRUPT_DEST 0 0 OTG0_IHC_DRR_TIMING_INTERRUPT_DEST 1 1 OTG0_IHC_V_UPDATE_INTERRUPT_DEST 2 2 OTG0_IHC_SNAPSHOT_INTERRUPT_DEST 3 3 OTG0_IHC_OTG_FORCE_COUNT_NOW_INTERRUPT_DEST 4 4 OTG0_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT_DEST 5 5 OTG0_IHC_OTG_TRIGA_INTERRUPT_DEST 6 6 OTG0_IHC_OTG_TRIGB_INTERRUPT_DEST 7 7 OTG0_IHC_GSL_VSYNC_GAP_INTERRUPT_DEST 8 8 OTG0_IHC_OTG_VERTICAL_INTERRUPT0_DEST 9 9 OTG0_IHC_OTG_VERTICAL_INTERRUPT1_DEST 10 10 OTG0_IHC_OTG_VERTICAL_INTERRUPT2_DEST 11 11 OTG0_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INTERRUPT_DEST 15 15 OTG0_IHC_VSTARTUP_INTERRUPT_DEST 16 16 OTG0_IHC_VREADY_INTERRUPT_DEST 17 17 OTG0_IHC_VSYNC_NOM_INTERRUPT_DEST 18 18 OTG0_IHC_V_UPDATE_NO_LOCK_INTERRUPT_DEST 19 19 OTG0_DRR_V_TOTAL_REACH_INTERRUPT_DEST 20 20 regOTG1_INTERRUPT_DEST 0 0x157 18 0 2 OTG1_IHC_CPU_SS_INTERRUPT_DEST 0 0 OTG1_IHC_DRR_TIMING_INTERRUPT_DEST 1 1 OTG1_IHC_V_UPDATE_INTERRUPT_DEST 2 2 OTG1_IHC_SNAPSHOT_INTERRUPT_DEST 3 3 OTG1_IHC_OTG_FORCE_COUNT_NOW_INTERRUPT_DEST 4 4 OTG1_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT_DEST 5 5 OTG1_IHC_OTG_TRIGA_INTERRUPT_DEST 6 6 OTG1_IHC_OTG_TRIGB_INTERRUPT_DEST 7 7 OTG1_IHC_GSL_VSYNC_GAP_INTERRUPT_DEST 8 8 OTG1_IHC_OTG_VERTICAL_INTERRUPT0_DEST 9 9 OTG1_IHC_OTG_VERTICAL_INTERRUPT1_DEST 10 10 OTG1_IHC_OTG_VERTICAL_INTERRUPT2_DEST 11 11 OTG1_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INTERRUPT_DEST 15 15 OTG1_IHC_VSTARTUP_INTERRUPT_DEST 16 16 OTG1_IHC_VREADY_INTERRUPT_DEST 17 17 OTG1_IHC_VSYNC_NOM_INTERRUPT_DEST 18 18 OTG1_IHC_V_UPDATE_NO_LOCK_INTERRUPT_DEST 19 19 OTG1_DRR_V_TOTAL_REACH_INTERRUPT_DEST 20 20 regOTG2_INTERRUPT_DEST 0 0x158 18 0 2 OTG2_IHC_CPU_SS_INTERRUPT_DEST 0 0 OTG2_IHC_DRR_TIMING_INTERRUPT_DEST 1 1 OTG2_IHC_V_UPDATE_INTERRUPT_DEST 2 2 OTG2_IHC_SNAPSHOT_INTERRUPT_DEST 3 3 OTG2_IHC_OTG_FORCE_COUNT_NOW_INTERRUPT_DEST 4 4 OTG2_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT_DEST 5 5 OTG2_IHC_OTG_TRIGA_INTERRUPT_DEST 6 6 OTG2_IHC_OTG_TRIGB_INTERRUPT_DEST 7 7 OTG2_IHC_GSL_VSYNC_GAP_INTERRUPT_DEST 8 8 OTG2_IHC_OTG_VERTICAL_INTERRUPT0_DEST 9 9 OTG2_IHC_OTG_VERTICAL_INTERRUPT1_DEST 10 10 OTG2_IHC_OTG_VERTICAL_INTERRUPT2_DEST 11 11 OTG2_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INTERRUPT_DEST 15 15 OTG2_IHC_VSTARTUP_INTERRUPT_DEST 16 16 OTG2_IHC_VREADY_INTERRUPT_DEST 17 17 OTG2_IHC_VSYNC_NOM_INTERRUPT_DEST 18 18 OTG2_IHC_V_UPDATE_NO_LOCK_INTERRUPT_DEST 19 19 OTG2_DRR_V_TOTAL_REACH_INTERRUPT_DEST 20 20 regOTG3_INTERRUPT_DEST 0 0x159 18 0 2 OTG3_IHC_CPU_SS_INTERRUPT_DEST 0 0 OTG3_IHC_DRR_TIMING_INTERRUPT_DEST 1 1 OTG3_IHC_V_UPDATE_INTERRUPT_DEST 2 2 OTG3_IHC_SNAPSHOT_INTERRUPT_DEST 3 3 OTG3_IHC_OTG_FORCE_COUNT_NOW_INTERRUPT_DEST 4 4 OTG3_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT_DEST 5 5 OTG3_IHC_OTG_TRIGA_INTERRUPT_DEST 6 6 OTG3_IHC_OTG_TRIGB_INTERRUPT_DEST 7 7 OTG3_IHC_GSL_VSYNC_GAP_INTERRUPT_DEST 8 8 OTG3_IHC_OTG_VERTICAL_INTERRUPT0_DEST 9 9 OTG3_IHC_OTG_VERTICAL_INTERRUPT1_DEST 10 10 OTG3_IHC_OTG_VERTICAL_INTERRUPT2_DEST 11 11 OTG3_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INTERRUPT_DEST 15 15 OTG3_IHC_VSTARTUP_INTERRUPT_DEST 16 16 OTG3_IHC_VREADY_INTERRUPT_DEST 17 17 OTG3_IHC_VSYNC_NOM_INTERRUPT_DEST 18 18 OTG3_IHC_V_UPDATE_NO_LOCK_INTERRUPT_DEST 19 19 OTG3_DRR_V_TOTAL_REACH_INTERRUPT_DEST 20 20 regOTG4_INTERRUPT_DEST 0 0x15a 18 0 2 OTG4_IHC_CPU_SS_INTERRUPT_DEST 0 0 OTG4_IHC_DRR_TIMING_INTERRUPT_DEST 1 1 OTG4_IHC_V_UPDATE_INTERRUPT_DEST 2 2 OTG4_IHC_SNAPSHOT_INTERRUPT_DEST 3 3 OTG4_IHC_OTG_FORCE_COUNT_NOW_INTERRUPT_DEST 4 4 OTG4_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT_DEST 5 5 OTG4_IHC_OTG_TRIGA_INTERRUPT_DEST 6 6 OTG4_IHC_OTG_TRIGB_INTERRUPT_DEST 7 7 OTG4_IHC_GSL_VSYNC_GAP_INTERRUPT_DEST 8 8 OTG4_IHC_OTG_VERTICAL_INTERRUPT0_DEST 9 9 OTG4_IHC_OTG_VERTICAL_INTERRUPT1_DEST 10 10 OTG4_IHC_OTG_VERTICAL_INTERRUPT2_DEST 11 11 OTG4_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INTERRUPT_DEST 15 15 OTG4_IHC_VSTARTUP_INTERRUPT_DEST 16 16 OTG4_IHC_VREADY_INTERRUPT_DEST 17 17 OTG4_IHC_VSYNC_NOM_INTERRUPT_DEST 18 18 OTG4_IHC_V_UPDATE_NO_LOCK_INTERRUPT_DEST 19 19 OTG4_DRR_V_TOTAL_REACH_INTERRUPT_DEST 20 20 regOTG5_INTERRUPT_DEST 0 0x15b 18 0 2 OTG5_IHC_CPU_SS_INTERRUPT_DEST 0 0 OTG5_IHC_DRR_TIMING_INTERRUPT_DEST 1 1 OTG5_IHC_V_UPDATE_INTERRUPT_DEST 2 2 OTG5_IHC_SNAPSHOT_INTERRUPT_DEST 3 3 OTG5_IHC_OTG_FORCE_COUNT_NOW_INTERRUPT_DEST 4 4 OTG5_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT_DEST 5 5 OTG5_IHC_OTG_TRIGA_INTERRUPT_DEST 6 6 OTG5_IHC_OTG_TRIGB_INTERRUPT_DEST 7 7 OTG5_IHC_GSL_VSYNC_GAP_INTERRUPT_DEST 8 8 OTG5_IHC_OTG_VERTICAL_INTERRUPT0_DEST 9 9 OTG5_IHC_OTG_VERTICAL_INTERRUPT1_DEST 10 10 OTG5_IHC_OTG_VERTICAL_INTERRUPT2_DEST 11 11 OTG5_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INTERRUPT_DEST 15 15 OTG5_IHC_VSTARTUP_INTERRUPT_DEST 16 16 OTG5_IHC_VREADY_INTERRUPT_DEST 17 17 OTG5_IHC_VSYNC_NOM_INTERRUPT_DEST 18 18 OTG5_IHC_V_UPDATE_NO_LOCK_INTERRUPT_DEST 19 19 OTG5_DRR_V_TOTAL_REACH_INTERRUPT_DEST 20 20 regDIG_INTERRUPT_DEST 0 0x15c 16 0 2 DOUT_IHC_DIGA_VID_STREAM_DISABLE_INTERRUPT_DEST 0 0 DOUT_IHC_DIGB_VID_STREAM_DISABLE_INTERRUPT_DEST 1 1 DOUT_IHC_DIGC_VID_STREAM_DISABLE_INTERRUPT_DEST 2 2 DOUT_IHC_DIGD_VID_STREAM_DISABLE_INTERRUPT_DEST 3 3 DOUT_IHC_DIGE_VID_STREAM_DISABLE_INTERRUPT_DEST 4 4 DOUT_IHC_DIGF_VID_STREAM_DISABLE_INTERRUPT_DEST 5 5 DOUT_IHC_DIGG_VID_STREAM_DISABLE_INTERRUPT_DEST 6 6 DOUT_IHC_DIGH_VID_STREAM_DISABLE_INTERRUPT_DEST 7 7 DOUT_IHC_DIGA_FAST_TRAINING_COMPLETE_INTERRUPT_DEST 8 8 DOUT_IHC_DIGB_FAST_TRAINING_COMPLETE_INTERRUPT_DEST 9 9 DOUT_IHC_DIGC_FAST_TRAINING_COMPLETE_INTERRUPT_DEST 10 10 DOUT_IHC_DIGD_FAST_TRAINING_COMPLETE_INTERRUPT_DEST 11 11 DOUT_IHC_DIGE_FAST_TRAINING_COMPLETE_INTERRUPT_DEST 12 12 DOUT_IHC_DIGF_FAST_TRAINING_COMPLETE_INTERRUPT_DEST 13 13 DOUT_IHC_DIGG_FAST_TRAINING_COMPLETE_INTERRUPT_DEST 14 14 DOUT_IHC_DIGH_FAST_TRAINING_COMPLETE_INTERRUPT_DEST 15 15 regI2C_DDC_HPD_INTERRUPT_DEST 0 0x15d 15 0 2 DOUT_IHC_I2C_SW_DONE_INTERRUPT_DEST 0 0 DOUT_IHC_I2C_DDC1_HW_DONE_INTERRUPT_DEST 1 1 DOUT_IHC_I2C_DDC2_HW_DONE_INTERRUPT_DEST 2 2 DOUT_IHC_I2C_DDC3_HW_DONE_INTERRUPT_DEST 3 3 DOUT_IHC_I2C_DDC4_HW_DONE_INTERRUPT_DEST 4 4 DOUT_IHC_I2C_DDC5_HW_DONE_INTERRUPT_DEST 5 5 DOUT_IHC_I2C_DDC6_HW_DONE_INTERRUPT_DEST 6 6 DOUT_IHC_I2C_DDCVGA_HW_DONE_INTERRUPT_DEST 7 7 DC_I2C_DDC1_READ_REQUEST_INTERRUPT_DEST 16 16 DC_I2C_DDC2_READ_REQUEST_INTERRUPT_DEST 17 17 DC_I2C_DDC3_READ_REQUEST_INTERRUPT_DEST 18 18 DC_I2C_DDC4_READ_REQUEST_INTERRUPT_DEST 19 19 DC_I2C_DDC5_READ_REQUEST_INTERRUPT_DEST 20 20 DC_I2C_DDC6_READ_REQUEST_INTERRUPT_DEST 21 21 DC_I2C_DDCVGA_READ_REQUEST_INTERRPUT_DEST 22 22 regDIO_INTERRUPT_DEST 0 0x15f 2 0 2 DIO_IHC_PERFMON_COUNTER0_INTERRUPT_DEST 12 12 DIO_IHC_PERFMON_COUNTER1_INTERRUPT_DEST 13 13 regDCIO_INTERRUPT_DEST 0 0x160 8 0 2 DCIO_DPCS_TXA_IHC_ERROR_INTERRUPT_DEST 0 0 DCIO_DPCS_TXB_IHC_ERROR_INTERRUPT_DEST 1 1 DCIO_DPCS_TXC_IHC_ERROR_INTERRUPT_DEST 2 2 DCIO_DPCS_TXD_IHC_ERROR_INTERRUPT_DEST 3 3 DCIO_DPCS_TXE_IHC_ERROR_INTERRUPT_DEST 4 4 DCIO_DPCS_TXF_IHC_ERROR_INTERRUPT_DEST 5 5 DCIO_DPCS_TXG_IHC_ERROR_INTERRUPT_DEST 6 6 DCIO_DPCS_RXA_IHC_ERROR_INTERRUPT_DEST 16 16 regHPD_INTERRUPT_DEST 0 0x161 12 0 2 DOUT_IHC_HPD1_INTERRUPT_DEST 0 0 DOUT_IHC_HPD2_INTERRUPT_DEST 1 1 DOUT_IHC_HPD3_INTERRUPT_DEST 2 2 DOUT_IHC_HPD4_INTERRUPT_DEST 3 3 DOUT_IHC_HPD5_INTERRUPT_DEST 4 4 DOUT_IHC_HPD6_INTERRUPT_DEST 5 5 DOUT_IHC_HPD1_RX_INTERRUPT_DEST 8 8 DOUT_IHC_HPD2_RX_INTERRUPT_DEST 9 9 DOUT_IHC_HPD3_RX_INTERRUPT_DEST 10 10 DOUT_IHC_HPD4_RX_INTERRUPT_DEST 11 11 DOUT_IHC_HPD5_RX_INTERRUPT_DEST 12 12 DOUT_IHC_HPD6_RX_INTERRUPT_DEST 13 13 regAZ_INTERRUPT_DEST 0 0x162 26 0 2 AZ_IHC_ENDPOINT0_AUDIO_FORMAT_CHANGED_INT_DEST 0 0 AZ_IHC_ENDPOINT1_AUDIO_FORMAT_CHANGED_INT_DEST 1 1 AZ_IHC_ENDPOINT2_AUDIO_FORMAT_CHANGED_INT_DEST 2 2 AZ_IHC_ENDPOINT3_AUDIO_FORMAT_CHANGED_INT_DEST 3 3 AZ_IHC_ENDPOINT4_AUDIO_FORMAT_CHANGED_INT_DEST 4 4 AZ_IHC_ENDPOINT5_AUDIO_FORMAT_CHANGED_INT_DEST 5 5 AZ_IHC_ENDPOINT6_AUDIO_FORMAT_CHANGED_INT_DEST 6 6 AZ_IHC_ENDPOINT7_AUDIO_FORMAT_CHANGED_INT_DEST 7 7 AZ_IHC_ENDPOINT0_AUDIO_ENABLED_INT_DEST 8 8 AZ_IHC_ENDPOINT1_AUDIO_ENABLED_INT_DEST 9 9 AZ_IHC_ENDPOINT2_AUDIO_ENABLED_INT_DEST 10 10 AZ_IHC_ENDPOINT3_AUDIO_ENABLED_INT_DEST 11 11 AZ_IHC_ENDPOINT4_AUDIO_ENABLED_INT_DEST 12 12 AZ_IHC_ENDPOINT5_AUDIO_ENABLED_INT_DEST 13 13 AZ_IHC_ENDPOINT6_AUDIO_ENABLED_INT_DEST 14 14 AZ_IHC_ENDPOINT7_AUDIO_ENABLED_INT_DEST 15 15 AZ_IHC_ENDPOINT0_AUDIO_DISABLED_INT_DEST 16 16 AZ_IHC_ENDPOINT1_AUDIO_DISABLED_INT_DEST 17 17 AZ_IHC_ENDPOINT2_AUDIO_DISABLED_INT_DEST 18 18 AZ_IHC_ENDPOINT3_AUDIO_DISABLED_INT_DEST 19 19 AZ_IHC_ENDPOINT4_AUDIO_DISABLED_INT_DEST 20 20 AZ_IHC_ENDPOINT5_AUDIO_DISABLED_INT_DEST 21 21 AZ_IHC_ENDPOINT6_AUDIO_DISABLED_INT_DEST 22 22 AZ_IHC_ENDPOINT7_AUDIO_DISABLED_INT_DEST 23 23 AZ_IHC_PERFMON_COUNTER0_INTERRUPT_DEST 30 30 AZ_IHC_PERFMON_COUNTER1_INTERRUPT_DEST 31 31 regAUX_INTERRUPT_DEST 0 0x163 24 0 2 DOUT_IHC_AUX1_SW_DONE_INTERRUPT_DEST 0 0 DOUT_IHC_AUX1_LS_DONE_INTERRUPT_DEST 1 1 DOUT_IHC_AUX2_SW_DONE_INTERRUPT_DEST 2 2 DOUT_IHC_AUX2_LS_DONE_INTERRUPT_DEST 3 3 DOUT_IHC_AUX3_SW_DONE_INTERRUPT_DEST 4 4 DOUT_IHC_AUX3_LS_DONE_INTERRUPT_DEST 5 5 DOUT_IHC_AUX4_SW_DONE_INTERRUPT_DEST 6 6 DOUT_IHC_AUX4_LS_DONE_INTERRUPT_DEST 7 7 DOUT_IHC_AUX5_SW_DONE_INTERRUPT_DEST 8 8 DOUT_IHC_AUX5_LS_DONE_INTERRUPT_DEST 9 9 DOUT_IHC_AUX6_SW_DONE_INTERRUPT_DEST 10 10 DOUT_IHC_AUX6_LS_DONE_INTERRUPT_DEST 11 11 DOUT_IHC_AUX1_GTC_SYNC_LOCK_DONE_INTERRUPT_DEST 16 16 DOUT_IHC_AUX1_GTC_SYNC_ERROR_INTERRUPT_DEST 17 17 DOUT_IHC_AUX2_GTC_SYNC_LOCK_DONE_INTERRUPT_DEST 18 18 DOUT_IHC_AUX2_GTC_SYNC_ERROR_INTERRUPT_DEST 19 19 DOUT_IHC_AUX3_GTC_SYNC_LOCK_DONE_INTERRUPT_DEST 20 20 DOUT_IHC_AUX3_GTC_SYNC_ERROR_INTERRUPT_DEST 21 21 DOUT_IHC_AUX4_GTC_SYNC_LOCK_DONE_INTERRUPT_DEST 22 22 DOUT_IHC_AUX4_GTC_SYNC_ERROR_INTERRUPT_DEST 23 23 DOUT_IHC_AUX5_GTC_SYNC_LOCK_DONE_INTERRUPT_DEST 24 24 DOUT_IHC_AUX5_GTC_SYNC_ERROR_INTERRUPT_DEST 25 25 DOUT_IHC_AUX6_GTC_SYNC_LOCK_DONE_INTERRUPT_DEST 26 26 DOUT_IHC_AUX6_GTC_SYNC_ERROR_INTERRUPT_DEST 27 27 regDSC_INTERRUPT_DEST 0 0x164 24 0 2 DSC0_IHC_INPUT_UNDERFLOW_INTERRUPT_DEST 0 0 DSC0_IHC_CORE_ERROR_INTERRUPT_DEST 1 1 DSC0_IHC_PERFMON_COUNTER0_INTERRUPT_DEST 2 2 DSC0_IHC_PERFMON_COUNTER1_INTERRUPT_DEST 3 3 DSC1_IHC_INPUT_UNDERFLOW_INTERRUPT_DEST 4 4 DSC1_IHC_CORE_ERROR_INTERRUPT_DEST 5 5 DSC1_IHC_PERFMON_COUNTER0_INTERRUPT_DEST 6 6 DSC1_IHC_PERFMON_COUNTER1_INTERRUPT_DEST 7 7 DSC2_IHC_INPUT_UNDERFLOW_INTERRUPT_DEST 8 8 DSC2_IHC_CORE_ERROR_INTERRUPT_DEST 9 9 DSC2_IHC_PERFMON_COUNTER0_INTERRUPT_DEST 10 10 DSC2_IHC_PERFMON_COUNTER1_INTERRUPT_DEST 11 11 DSC3_IHC_INPUT_UNDERFLOW_INTERRUPT_DEST 12 12 DSC3_IHC_CORE_ERROR_INTERRUPT_DEST 13 13 DSC3_IHC_PERFMON_COUNTER0_INTERRUPT_DEST 14 14 DSC3_IHC_PERFMON_COUNTER1_INTERRUPT_DEST 15 15 DSC4_IHC_INPUT_UNDERFLOW_INTERRUPT_DEST 16 16 DSC4_IHC_CORE_ERROR_INTERRUPT_DEST 17 17 DSC4_IHC_PERFMON_COUNTER0_INTERRUPT_DEST 18 18 DSC4_IHC_PERFMON_COUNTER1_INTERRUPT_DEST 19 19 DSC5_IHC_INPUT_UNDERFLOW_INTERRUPT_DEST 20 20 DSC5_IHC_CORE_ERROR_INTERRUPT_DEST 21 21 DSC5_IHC_PERFMON_COUNTER0_INTERRUPT_DEST 22 22 DSC5_IHC_PERFMON_COUNTER1_INTERRUPT_DEST 23 23 regHPO_INTERRUPT_DEST 0 0x165 2 0 2 HPO_IHC_PERFMON_COUNTER0_INTERRUPT_DEST 2 2 HPO_IHC_PERFMON_COUNTER1_INTERRUPT_DEST 3 3 regCC_DC_PIPE_DIS 0 0xca 2 0 2 DC_PIPE_DIS 0 7 DC_DMCUB_ENABLE 16 16 regDMU_CLK_CNTL 0 0xcb 7 0 2 DMU_TEST_CLK_SEL 0 3 DISPCLK_R_DMU_GATE_DIS 4 4 DISPCLK_G_DMCU_GATE_DIS 5 5 DISPCLK_G_RBBMIF_GATE_DIS 6 6 DISPCLK_R_CLOCK_ON 8 8 DISPCLK_G_DMCU_CLOCK_ON 9 9 DISPCLK_G_RBBMIF_CLOCK_ON 10 10 regDMU_MEM_PWR_CNTL 0 0xcc 7 0 2 DMCU_ERAM_MEM_PWR_MODE_SEL 0 0 DMCU_ERAM_MEM_PWR_FORCE 1 2 DMCU_ERAM_MEM_PWR_DIS 3 3 DMCU_ERAM_MEM_PWR_STATE 4 5 DMCU_IRAM_MEM_PWR_FORCE 8 8 DMCU_IRAM_MEM_PWR_DIS 9 9 DMCU_IRAM_MEM_PWR_STATE 10 10 regDMCU_SMU_INTERRUPT_CNTL 0 0xcd 2 0 2 DMCU_SMU_MSG_INT 0 0 DMCU_SMU_MSG 16 31 regZSC_CNTL 0 0xcf 1 0 2 FORCE_SOC_ACCESS 0 1 regZSC_CNTL2 0 0xd0 1 0 2 ALLOW_Z10 0 0 regDMU_MISC_ALLOW_DS_FORCE 0 0xd6 2 0 2 DMU_MISC_ALLOW_DS_FORCE_EN 0 0 DMU_MISC_ALLOW_DS_FORCE_VALUE 4 4 regZSC_STATUS 0 0xd7 5 0 2 SOC_ACCESS_TRIGGER_STATUS 0 1 SOC_ACCESS_STICKY_TRIGGER_STATUS 4 5 FENCE_REQ_STATUS 8 8 FENCE_ACK_STATUS 9 9 FENCE_STATUS 10 11 regDOMAIN0_PG_CONFIG 0 0x80 2 0 2 DOMAIN_POWER_FORCEON 0 0 DOMAIN_POWER_GATE 8 8 regDOMAIN0_PG_STATUS 0 0x81 2 0 2 DOMAIN_DESIRED_PWR_STATE 28 28 DOMAIN_PGFSM_PWR_STATUS 30 31 regDOMAIN1_PG_CONFIG 0 0x82 2 0 2 DOMAIN_POWER_FORCEON 0 0 DOMAIN_POWER_GATE 8 8 regDOMAIN1_PG_STATUS 0 0x83 2 0 2 DOMAIN_DESIRED_PWR_STATE 28 28 DOMAIN_PGFSM_PWR_STATUS 30 31 regDOMAIN2_PG_CONFIG 0 0x84 2 0 2 DOMAIN_POWER_FORCEON 0 0 DOMAIN_POWER_GATE 8 8 regDOMAIN2_PG_STATUS 0 0x85 2 0 2 DOMAIN_DESIRED_PWR_STATE 28 28 DOMAIN_PGFSM_PWR_STATUS 30 31 regDOMAIN3_PG_CONFIG 0 0x86 2 0 2 DOMAIN_POWER_FORCEON 0 0 DOMAIN_POWER_GATE 8 8 regDOMAIN3_PG_STATUS 0 0x87 2 0 2 DOMAIN_DESIRED_PWR_STATE 28 28 DOMAIN_PGFSM_PWR_STATUS 30 31 regDOMAIN16_PG_CONFIG 0 0x89 2 0 2 DOMAIN_POWER_FORCEON 0 0 DOMAIN_POWER_GATE 8 8 regDOMAIN16_PG_STATUS 0 0x8a 2 0 2 DOMAIN_DESIRED_PWR_STATE 28 28 DOMAIN_PGFSM_PWR_STATUS 30 31 regDOMAIN17_PG_CONFIG 0 0x8b 2 0 2 DOMAIN_POWER_FORCEON 0 0 DOMAIN_POWER_GATE 8 8 regDOMAIN17_PG_STATUS 0 0x8c 2 0 2 DOMAIN_DESIRED_PWR_STATE 28 28 DOMAIN_PGFSM_PWR_STATUS 30 31 regDOMAIN18_PG_CONFIG 0 0x8d 2 0 2 DOMAIN_POWER_FORCEON 0 0 DOMAIN_POWER_GATE 8 8 regDOMAIN18_PG_STATUS 0 0x8e 2 0 2 DOMAIN_DESIRED_PWR_STATE 28 28 DOMAIN_PGFSM_PWR_STATUS 30 31 regDC_IP_REQUEST_CNTL 0 0x93 1 0 2 IP_REQUEST_EN 0 0 regDMCUB_REGION0_OFFSET 0 0x18e 1 0 2 DMCUB_REGION0_OFFSET 8 31 regDMCUB_REGION0_OFFSET_HIGH 0 0x18f 1 0 2 DMCUB_REGION0_OFFSET_HIGH 0 15 regDMCUB_REGION1_OFFSET 0 0x190 1 0 2 DMCUB_REGION1_OFFSET 8 31 regDMCUB_REGION1_OFFSET_HIGH 0 0x191 1 0 2 DMCUB_REGION1_OFFSET_HIGH 0 15 regDMCUB_REGION2_OFFSET 0 0x192 1 0 2 DMCUB_REGION2_OFFSET 8 31 regDMCUB_REGION2_OFFSET_HIGH 0 0x193 1 0 2 DMCUB_REGION2_OFFSET_HIGH 0 15 regDMCUB_REGION4_OFFSET 0 0x196 1 0 2 DMCUB_REGION4_OFFSET 8 31 regDMCUB_REGION4_OFFSET_HIGH 0 0x197 1 0 2 DMCUB_REGION4_OFFSET_HIGH 0 15 regDMCUB_REGION5_OFFSET 0 0x198 1 0 2 DMCUB_REGION5_OFFSET 8 31 regDMCUB_REGION5_OFFSET_HIGH 0 0x199 1 0 2 DMCUB_REGION5_OFFSET_HIGH 0 15 regDMCUB_REGION6_OFFSET 0 0x19a 1 0 2 DMCUB_REGION6_OFFSET 8 31 regDMCUB_REGION6_OFFSET_HIGH 0 0x19b 1 0 2 DMCUB_REGION6_OFFSET_HIGH 0 15 regDMCUB_REGION7_OFFSET 0 0x19c 1 0 2 DMCUB_REGION7_OFFSET 8 31 regDMCUB_REGION7_OFFSET_HIGH 0 0x19d 1 0 2 DMCUB_REGION7_OFFSET_HIGH 0 15 regDMCUB_REGION0_TOP_ADDRESS 0 0x19e 2 0 2 DMCUB_REGION0_TOP_ADDRESS 0 28 DMCUB_REGION0_ENABLE 31 31 regDMCUB_REGION1_TOP_ADDRESS 0 0x19f 2 0 2 DMCUB_REGION1_TOP_ADDRESS 0 28 DMCUB_REGION1_ENABLE 31 31 regDMCUB_REGION2_TOP_ADDRESS 0 0x1a0 2 0 2 DMCUB_REGION2_TOP_ADDRESS 0 28 DMCUB_REGION2_ENABLE 31 31 regDMCUB_REGION4_TOP_ADDRESS 0 0x1a1 2 0 2 DMCUB_REGION4_TOP_ADDRESS 0 28 DMCUB_REGION4_ENABLE 31 31 regDMCUB_REGION5_TOP_ADDRESS 0 0x1a2 2 0 2 DMCUB_REGION5_TOP_ADDRESS 0 28 DMCUB_REGION5_ENABLE 31 31 regDMCUB_REGION6_TOP_ADDRESS 0 0x1a3 2 0 2 DMCUB_REGION6_TOP_ADDRESS 0 28 DMCUB_REGION6_ENABLE 31 31 regDMCUB_REGION7_TOP_ADDRESS 0 0x1a4 2 0 2 DMCUB_REGION7_TOP_ADDRESS 0 28 DMCUB_REGION7_ENABLE 31 31 regDMCUB_REGION3_CW0_BASE_ADDRESS 0 0x1a5 1 0 2 DMCUB_REGION3_CW0_BASE_ADDRESS 0 28 regDMCUB_REGION3_CW1_BASE_ADDRESS 0 0x1a6 1 0 2 DMCUB_REGION3_CW1_BASE_ADDRESS 0 28 regDMCUB_REGION3_CW2_BASE_ADDRESS 0 0x1a7 1 0 2 DMCUB_REGION3_CW2_BASE_ADDRESS 0 28 regDMCUB_REGION3_CW3_BASE_ADDRESS 0 0x1a8 1 0 2 DMCUB_REGION3_CW3_BASE_ADDRESS 0 28 regDMCUB_REGION3_CW4_BASE_ADDRESS 0 0x1a9 1 0 2 DMCUB_REGION3_CW4_BASE_ADDRESS 0 28 regDMCUB_REGION3_CW5_BASE_ADDRESS 0 0x1aa 1 0 2 DMCUB_REGION3_CW5_BASE_ADDRESS 0 28 regDMCUB_REGION3_CW6_BASE_ADDRESS 0 0x1ab 1 0 2 DMCUB_REGION3_CW6_BASE_ADDRESS 0 28 regDMCUB_REGION3_CW7_BASE_ADDRESS 0 0x1ac 1 0 2 DMCUB_REGION3_CW7_BASE_ADDRESS 0 28 regDMCUB_REGION3_CW0_TOP_ADDRESS 0 0x1ad 2 0 2 DMCUB_REGION3_CW0_TOP_ADDRESS 0 28 DMCUB_REGION3_CW0_ENABLE 31 31 regDMCUB_REGION3_CW1_TOP_ADDRESS 0 0x1ae 2 0 2 DMCUB_REGION3_CW1_TOP_ADDRESS 0 28 DMCUB_REGION3_CW1_ENABLE 31 31 regDMCUB_REGION3_CW2_TOP_ADDRESS 0 0x1af 2 0 2 DMCUB_REGION3_CW2_TOP_ADDRESS 0 28 DMCUB_REGION3_CW2_ENABLE 31 31 regDMCUB_REGION3_CW3_TOP_ADDRESS 0 0x1b0 2 0 2 DMCUB_REGION3_CW3_TOP_ADDRESS 0 28 DMCUB_REGION3_CW3_ENABLE 31 31 regDMCUB_REGION3_CW4_TOP_ADDRESS 0 0x1b1 2 0 2 DMCUB_REGION3_CW4_TOP_ADDRESS 0 28 DMCUB_REGION3_CW4_ENABLE 31 31 regDMCUB_REGION3_CW5_TOP_ADDRESS 0 0x1b2 2 0 2 DMCUB_REGION3_CW5_TOP_ADDRESS 0 28 DMCUB_REGION3_CW5_ENABLE 31 31 regDMCUB_REGION3_CW6_TOP_ADDRESS 0 0x1b3 2 0 2 DMCUB_REGION3_CW6_TOP_ADDRESS 0 28 DMCUB_REGION3_CW6_ENABLE 31 31 regDMCUB_REGION3_CW7_TOP_ADDRESS 0 0x1b4 2 0 2 DMCUB_REGION3_CW7_TOP_ADDRESS 0 28 DMCUB_REGION3_CW7_ENABLE 31 31 regDMCUB_REGION3_CW0_OFFSET 0 0x1b5 1 0 2 DMCUB_REGION3_CW0_OFFSET 8 31 regDMCUB_REGION3_CW0_OFFSET_HIGH 0 0x1b6 1 0 2 DMCUB_REGION3_CW0_OFFSET_HIGH 0 15 regDMCUB_REGION3_CW1_OFFSET 0 0x1b7 1 0 2 DMCUB_REGION3_CW1_OFFSET 8 31 regDMCUB_REGION3_CW1_OFFSET_HIGH 0 0x1b8 1 0 2 DMCUB_REGION3_CW1_OFFSET_HIGH 0 15 regDMCUB_REGION3_CW2_OFFSET 0 0x1b9 1 0 2 DMCUB_REGION3_CW2_OFFSET 8 31 regDMCUB_REGION3_CW2_OFFSET_HIGH 0 0x1ba 1 0 2 DMCUB_REGION3_CW2_OFFSET_HIGH 0 15 regDMCUB_REGION3_CW3_OFFSET 0 0x1bb 1 0 2 DMCUB_REGION3_CW3_OFFSET 8 31 regDMCUB_REGION3_CW3_OFFSET_HIGH 0 0x1bc 1 0 2 DMCUB_REGION3_CW3_OFFSET_HIGH 0 15 regDMCUB_REGION3_CW4_OFFSET 0 0x1bd 1 0 2 DMCUB_REGION3_CW4_OFFSET 8 31 regDMCUB_REGION3_CW4_OFFSET_HIGH 0 0x1be 1 0 2 DMCUB_REGION3_CW4_OFFSET_HIGH 0 15 regDMCUB_REGION3_CW5_OFFSET 0 0x1bf 1 0 2 DMCUB_REGION3_CW5_OFFSET 8 31 regDMCUB_REGION3_CW5_OFFSET_HIGH 0 0x1c0 1 0 2 DMCUB_REGION3_CW5_OFFSET_HIGH 0 15 regDMCUB_REGION3_CW6_OFFSET 0 0x1c1 1 0 2 DMCUB_REGION3_CW6_OFFSET 8 31 regDMCUB_REGION3_CW6_OFFSET_HIGH 0 0x1c2 1 0 2 DMCUB_REGION3_CW6_OFFSET_HIGH 0 15 regDMCUB_REGION3_CW7_OFFSET 0 0x1c3 1 0 2 DMCUB_REGION3_CW7_OFFSET 8 31 regDMCUB_REGION3_CW7_OFFSET_HIGH 0 0x1c4 1 0 2 DMCUB_REGION3_CW7_OFFSET_HIGH 0 15 regDMCUB_INTERRUPT_ENABLE 0 0x1c5 14 0 2 DMCUB_TIMER0_INT_EN 0 0 DMCUB_TIMER1_INT_EN 1 1 DMCUB_INBOX0_READY_INT_EN 2 2 DMCUB_INBOX0_DONE_INT_EN 3 3 DMCUB_INBOX1_READY_INT_EN 4 4 DMCUB_INBOX1_DONE_INT_EN 5 5 DMCUB_OUTBOX0_READY_INT_EN 6 6 DMCUB_OUTBOX0_DONE_INT_EN 7 7 DMCUB_OUTBOX1_READY_INT_EN 8 8 DMCUB_OUTBOX1_DONE_INT_EN 9 9 DMCUB_GPINT0_INT_EN 10 10 DMCUB_GPINT1_INT_EN 11 11 DMCUB_GPINT2_INT_EN 12 12 DMCUB_UNDEFINED_ADDRESS_FAULT_INT_EN 13 13 regDMCUB_INTERRUPT_ACK 0 0x1c6 14 0 2 DMCUB_TIMER0_INT_ACK 0 0 DMCUB_TIMER1_INT_ACK 1 1 DMCUB_INBOX0_READY_INT_ACK 2 2 DMCUB_INBOX0_DONE_INT_ACK 3 3 DMCUB_INBOX1_READY_INT_ACK 4 4 DMCUB_INBOX1_DONE_INT_ACK 5 5 DMCUB_OUTBOX0_READY_INT_ACK 6 6 DMCUB_OUTBOX0_DONE_INT_ACK 7 7 DMCUB_OUTBOX1_READY_INT_ACK 8 8 DMCUB_OUTBOX1_DONE_INT_ACK 9 9 DMCUB_GPINT0_INT_ACK 10 10 DMCUB_GPINT1_INT_ACK 11 11 DMCUB_GPINT2_INT_ACK 12 12 DMCUB_UNDEFINED_ADDRESS_FAULT_ACK 13 13 regDMCUB_INTERRUPT_TYPE 0 0x1c8 14 0 2 DMCUB_TIMER0_INT_TYPE 0 0 DMCUB_TIMER1_INT_TYPE 1 1 DMCUB_INBOX0_READY_INT_TYPE 2 2 DMCUB_INBOX0_DONE_INT_TYPE 3 3 DMCUB_INBOX1_READY_INT_TYPE 4 4 DMCUB_INBOX1_DONE_INT_TYPE 5 5 DMCUB_OUTBOX0_READY_INT_TYPE 6 6 DMCUB_OUTBOX0_DONE_INT_TYPE 7 7 DMCUB_OUTBOX1_READY_INT_TYPE 8 8 DMCUB_OUTBOX1_DONE_INT_TYPE 9 9 DMCUB_GPINT0_INT_TYPE 10 10 DMCUB_GPINT1_INT_TYPE 11 11 DMCUB_GPINT2_INT_TYPE 12 12 DMCUB_UNDEFINED_ADDRESS_FAULT_INT_TYPE 13 13 regDMCUB_EXT_INTERRUPT_CTXID 0 0x1ca 1 0 2 DMCUB_EXT_INTERRUPT_CTXID 0 27 regDMCUB_EXT_INTERRUPT_ACK 0 0x1cb 1 0 2 DMCUB_EXT_INTERRUPT_ACK 0 0 regDMCUB_INST_FETCH_FAULT_ADDR 0 0x1cc 1 0 2 DMCUB_INST_FETCH_FAULT_ADDR 0 31 regDMCUB_DATA_WRITE_FAULT_ADDR 0 0x1cd 1 0 2 DMCUB_DATA_WRITE_FAULT_ADDR 0 31 regDMCUB_SEC_CNTL 0 0x1ce 8 0 2 DMCUB_MEM_SEC_LVL 0 3 DMCUB_MEM_UNIT_ID 8 13 DMCUB_SEC_RESET 16 16 DMCUB_DATA_FAULT_INT_DISABLE 17 17 DMCUB_AUTO_RESET_STATUS 20 20 DMCUB_SEC_RESET_STATUS 21 21 DMCUB_INST_FETCH_FAULT_CLEAR 24 24 DMCUB_DATA_WRITE_FAULT_CLEAR 25 25 regDMCUB_MEM_CNTL 0 0x1cf 2 0 2 DMCUB_MEM_WRITE_QOS 0 3 DMCUB_MEM_READ_QOS 4 7 regDMCUB_INBOX0_BASE_ADDRESS 0 0x1d0 1 0 2 DMCUB_INBOX0_BASE_ADDRESS 0 31 regDMCUB_INBOX0_SIZE 0 0x1d1 1 0 2 DMCUB_INBOX0_SIZE 0 31 regDMCUB_INBOX0_WPTR 0 0x1d2 1 0 2 DMCUB_INBOX0_WPTR 0 31 regDMCUB_INBOX0_RPTR 0 0x1d3 1 0 2 DMCUB_INBOX0_RPTR 0 31 regDMCUB_INBOX1_BASE_ADDRESS 0 0x1d4 1 0 2 DMCUB_INBOX1_BASE_ADDRESS 0 31 regDMCUB_INBOX1_SIZE 0 0x1d5 1 0 2 DMCUB_INBOX1_SIZE 0 31 regDMCUB_INBOX1_WPTR 0 0x1d6 1 0 2 DMCUB_INBOX1_WPTR 0 31 regDMCUB_INBOX1_RPTR 0 0x1d7 1 0 2 DMCUB_INBOX1_RPTR 0 31 regDMCUB_OUTBOX0_BASE_ADDRESS 0 0x1d8 1 0 2 DMCUB_OUTBOX0_BASE_ADDRESS 0 31 regDMCUB_OUTBOX0_SIZE 0 0x1d9 1 0 2 DMCUB_OUTBOX0_SIZE 0 31 regDMCUB_OUTBOX0_WPTR 0 0x1da 1 0 2 DMCUB_OUTBOX0_WPTR 0 31 regDMCUB_OUTBOX0_RPTR 0 0x1db 1 0 2 DMCUB_OUTBOX0_RPTR 0 31 regDMCUB_OUTBOX1_BASE_ADDRESS 0 0x1dc 1 0 2 DMCUB_OUTBOX1_BASE_ADDRESS 0 31 regDMCUB_OUTBOX1_SIZE 0 0x1dd 1 0 2 DMCUB_OUTBOX1_SIZE 0 31 regDMCUB_OUTBOX1_WPTR 0 0x1de 1 0 2 DMCUB_OUTBOX1_WPTR 0 31 regDMCUB_OUTBOX1_RPTR 0 0x1df 1 0 2 DMCUB_OUTBOX1_RPTR 0 31 regDMCUB_TIMER_TRIGGER0 0 0x1e0 1 0 2 DMCUB_TIMER_TRIGGER0 0 31 regDMCUB_TIMER_TRIGGER1 0 0x1e1 1 0 2 DMCUB_TIMER_TRIGGER1 0 31 regDMCUB_TIMER_WINDOW 0 0x1e2 1 0 2 DMCUB_TIMER_WINDOW 0 2 regDMCUB_SCRATCH0 0 0x1e3 1 0 2 DMCUB_SCRATCH0 0 31 regDMCUB_SCRATCH1 0 0x1e4 1 0 2 DMCUB_SCRATCH1 0 31 regDMCUB_SCRATCH2 0 0x1e5 1 0 2 DMCUB_SCRATCH2 0 31 regDMCUB_SCRATCH3 0 0x1e6 1 0 2 DMCUB_SCRATCH3 0 31 regDMCUB_SCRATCH4 0 0x1e7 1 0 2 DMCUB_SCRATCH4 0 31 regDMCUB_SCRATCH5 0 0x1e8 1 0 2 DMCUB_SCRATCH5 0 31 regDMCUB_SCRATCH6 0 0x1e9 1 0 2 DMCUB_SCRATCH6 0 31 regDMCUB_SCRATCH7 0 0x1ea 1 0 2 DMCUB_SCRATCH7 0 31 regDMCUB_SCRATCH8 0 0x1eb 1 0 2 DMCUB_SCRATCH8 0 31 regDMCUB_SCRATCH9 0 0x1ec 1 0 2 DMCUB_SCRATCH9 0 31 regDMCUB_SCRATCH10 0 0x1ed 1 0 2 DMCUB_SCRATCH10 0 31 regDMCUB_SCRATCH11 0 0x1ee 1 0 2 DMCUB_SCRATCH11 0 31 regDMCUB_SCRATCH12 0 0x1ef 1 0 2 DMCUB_SCRATCH12 0 31 regDMCUB_SCRATCH13 0 0x1f0 1 0 2 DMCUB_SCRATCH13 0 31 regDMCUB_SCRATCH14 0 0x1f1 1 0 2 DMCUB_SCRATCH14 0 31 regDMCUB_SCRATCH15 0 0x1f2 1 0 2 DMCUB_SCRATCH15 0 31 regDMCUB_CNTL 0 0x1f6 6 0 2 DMCUB_LS_WAKE_DELAY 0 7 DMCUB_DMCUBCLK_R_GATE_DIS 8 8 DMCUB_ENABLE 16 16 DMCUB_MEM_LIGHT_SLEEP_DISABLE 18 18 DMCUB_TRACEPORT_EN 19 19 DMCUB_PWAIT_MODE_STATUS 20 20 regDMCUB_GPINT_DATAIN0 0 0x1f7 1 0 2 DMCUB_GPINT_DATAIN0 0 31 regDMCUB_GPINT_DATAIN1 0 0x1f8 1 0 2 DMCUB_GPINT_DATAIN1 0 31 regDMCUB_GPINT_DATAOUT 0 0x1f9 1 0 2 DMCUB_GPINT_DATAOUT 0 31 regDMCUB_UNDEFINED_ADDRESS_FAULT_ADDR 0 0x1fa 1 0 2 DMCUB_UNDEFINED_ADDRESS_FAULT_ADDR 0 31 regDMCUB_LS_WAKE_INT_ENABLE 0 0x1fb 1 0 2 DMCUB_LS_WAKE_INT_ENABLE 0 31 regDMCUB_MEM_PWR_CNTL 0 0x1fc 3 0 2 DMCUB_MEM_PWR_FORCE 1 2 DMCUB_MEM_PWR_DIS 3 3 DMCUB_MEM_PWR_STATE 4 5 regDMCUB_TIMER_CURRENT 0 0x1fd 1 0 2 DMCUB_TIMER_CURRENT 0 31 regDMCUB_PROC_ID 0 0x1ff 1 0 2 DMCUB_PROC_ID 0 15 regDMCUB_CNTL2 0 0x200 1 0 2 DMCUB_SOFT_RESET 0 0 regDWB_ENABLE_CLK_CTRL 0 0x3228 4 0 2 DWB_ENABLE 0 0 DISPCLK_R_DWB_GATE_DIS 4 4 DISPCLK_G_DWB_GATE_DIS 8 8 DWB_TEST_CLK_SEL 12 13 regDWB_MEM_PWR_CTRL 0 0x3229 6 0 2 DWB_OUT_FIFO_MEM_PWR_FORCE 8 9 DWB_OUT_FIFO_MEM_PWR_DIS 10 10 DWB_OUT_FIFO_MEM_PWR_STATE 12 13 DWB_OGAM_LUT_MEM_PWR_FORCE 16 17 DWB_OGAM_LUT_MEM_PWR_DIS 18 18 DWB_OGAM_LUT_MEM_PWR_STATE 20 21 regFC_MODE_CTRL 0 0x322a 7 0 2 FC_FRAME_CAPTURE_EN 0 0 FC_FRAME_CAPTURE_RATE 4 5 FC_WINDOW_CROP_EN 8 8 FC_EYE_SELECTION 12 13 FC_STEREO_EYE_POLARITY 16 16 FC_NEW_CONTENT 20 20 FC_FRAME_CAPTURE_EN_CURRENT 31 31 regFC_FLOW_CTRL 0 0x322b 1 0 2 FC_FIRST_PIXEL_DELAY_COUNT 0 11 regFC_WINDOW_START 0 0x322c 2 0 2 FC_WINDOW_START_X 0 12 FC_WINDOW_START_Y 16 28 regFC_WINDOW_SIZE 0 0x322d 2 0 2 FC_WINDOW_WIDTH 0 11 FC_WINDOW_HEIGHT 16 27 regFC_SOURCE_SIZE 0 0x322e 2 0 2 FC_SOURCE_WIDTH 0 14 FC_SOURCE_HEIGHT 16 30 regDWB_UPDATE_CTRL 0 0x322f 2 0 2 DWB_UPDATE_LOCK 0 0 DWB_UPDATE_PENDING 4 4 regDWB_CRC_CTRL 0 0x3230 3 0 2 DWB_CRC_EN 0 0 DWB_CRC_CONT_EN 4 4 DWB_CRC_SRC_SEL 8 9 regDWB_CRC_MASK_R_G 0 0x3231 2 0 2 DWB_CRC_RED_MASK 0 15 DWB_CRC_GREEN_MASK 16 31 regDWB_CRC_MASK_B_A 0 0x3232 2 0 2 DWB_CRC_BLUE_MASK 0 15 DWB_CRC_A_MASK 16 31 regDWB_CRC_VAL_R_G 0 0x3233 2 0 2 DWB_CRC_SIG_RED 0 15 DWB_CRC_SIG_GREEN 16 31 regDWB_CRC_VAL_B_A 0 0x3234 2 0 2 DWB_CRC_SIG_BLUE 0 15 DWB_CRC_SIG_A 16 31 regDWB_OUT_CTRL 0 0x3235 4 0 2 OUT_FORMAT 0 1 OUT_DENORM 4 5 OUT_MAX 8 17 OUT_MIN 20 29 regDWB_MMHUBBUB_BACKPRESSURE_CNT_EN 0 0x3236 1 0 2 DWB_MMHUBBUB_BACKPRESSURE_CNT_EN 0 0 regDWB_MMHUBBUB_BACKPRESSURE_CNT 0 0x3237 1 0 2 DWB_MMHUBBUB_MAX_BACKPRESSURE 0 15 regDWB_HOST_READ_CONTROL 0 0x3238 1 0 2 DWB_HOST_READ_RATE_CONTROL 0 7 regDWB_OVERFLOW_STATUS 0 0x3239 5 0 2 DWB_DATA_OVERFLOW_FLAG 0 0 DWB_DATA_OVERFLOW_ACK 8 8 DWB_DATA_OVERFLOW_MASK 12 12 DWB_DATA_OVERFLOW_INT_STATUS 16 16 DWB_DATA_OVERFLOW_INT_TYPE 20 20 regDWB_OVERFLOW_COUNTER 0 0x323a 3 0 2 DWB_DATA_OVERFLOW_TYPE 0 1 DWB_DATA_OVERFLOW_OUT_X_CNT 4 15 DWB_DATA_OVERFLOW_OUT_Y_CNT 16 27 regDWB_SOFT_RESET 0 0x323b 1 0 2 DWB_SOFT_RESET 0 0 regDWB_DEBUG_CTRL 0 0x323c 2 0 2 DWB_DEBUG_EN 0 0 DWB_DEBUG_SEL 6 7 regDWB_HDR_MULT_COEF 0 0x3294 1 0 2 DWB_HDR_MULT_COEF 0 18 regDWB_GAMUT_REMAP_MODE 0 0x3295 2 0 2 DWB_GAMUT_REMAP_MODE 0 1 DWB_GAMUT_REMAP_MODE_CURRENT 24 25 regDWB_GAMUT_REMAP_COEF_FORMAT 0 0x3296 1 0 2 DWB_GAMUT_REMAP_COEF_FORMAT 0 0 regDWB_GAMUT_REMAPA_C11_C12 0 0x3297 2 0 2 DWB_GAMUT_REMAPA_C11 0 15 DWB_GAMUT_REMAPA_C12 16 31 regDWB_GAMUT_REMAPA_C13_C14 0 0x3298 2 0 2 DWB_GAMUT_REMAPA_C13 0 15 DWB_GAMUT_REMAPA_C14 16 31 regDWB_GAMUT_REMAPA_C21_C22 0 0x3299 2 0 2 DWB_GAMUT_REMAPA_C21 0 15 DWB_GAMUT_REMAPA_C22 16 31 regDWB_GAMUT_REMAPA_C23_C24 0 0x329a 2 0 2 DWB_GAMUT_REMAPA_C23 0 15 DWB_GAMUT_REMAPA_C24 16 31 regDWB_GAMUT_REMAPA_C31_C32 0 0x329b 2 0 2 DWB_GAMUT_REMAPA_C31 0 15 DWB_GAMUT_REMAPA_C32 16 31 regDWB_GAMUT_REMAPA_C33_C34 0 0x329c 2 0 2 DWB_GAMUT_REMAPA_C33 0 15 DWB_GAMUT_REMAPA_C34 16 31 regDWB_GAMUT_REMAPB_C11_C12 0 0x329d 2 0 2 DWB_GAMUT_REMAPB_C11 0 15 DWB_GAMUT_REMAPB_C12 16 31 regDWB_GAMUT_REMAPB_C13_C14 0 0x329e 2 0 2 DWB_GAMUT_REMAPB_C13 0 15 DWB_GAMUT_REMAPB_C14 16 31 regDWB_GAMUT_REMAPB_C21_C22 0 0x329f 2 0 2 DWB_GAMUT_REMAPB_C21 0 15 DWB_GAMUT_REMAPB_C22 16 31 regDWB_GAMUT_REMAPB_C23_C24 0 0x32a0 2 0 2 DWB_GAMUT_REMAPB_C23 0 15 DWB_GAMUT_REMAPB_C24 16 31 regDWB_GAMUT_REMAPB_C31_C32 0 0x32a1 2 0 2 DWB_GAMUT_REMAPB_C31 0 15 DWB_GAMUT_REMAPB_C32 16 31 regDWB_GAMUT_REMAPB_C33_C34 0 0x32a2 2 0 2 DWB_GAMUT_REMAPB_C33 0 15 DWB_GAMUT_REMAPB_C34 16 31 regDWB_OGAM_CONTROL 0 0x32a3 5 0 2 DWB_OGAM_MODE 0 1 DWB_OGAM_SELECT 4 4 DWB_OGAM_PWL_DISABLE 8 8 DWB_OGAM_MODE_CURRENT 24 25 DWB_OGAM_SELECT_CURRENT 28 28 regDWB_OGAM_LUT_INDEX 0 0x32a4 1 0 2 DWB_OGAM_LUT_INDEX 0 8 regDWB_OGAM_LUT_DATA 0 0x32a5 1 0 2 DWB_OGAM_LUT_DATA 0 17 regDWB_OGAM_LUT_CONTROL 0 0x32a6 5 0 2 DWB_OGAM_LUT_WRITE_COLOR_MASK 0 2 DWB_OGAM_LUT_READ_COLOR_SEL 4 5 DWB_OGAM_LUT_READ_DBG 8 8 DWB_OGAM_LUT_HOST_SEL 12 12 DWB_OGAM_LUT_CONFIG_MODE 16 16 regDWB_OGAM_RAMA_START_CNTL_B 0 0x32a7 2 0 2 DWB_OGAM_RAMA_EXP_REGION_START_B 0 17 DWB_OGAM_RAMA_EXP_REGION_START_SEGMENT_B 20 26 regDWB_OGAM_RAMA_START_CNTL_G 0 0x32a8 2 0 2 DWB_OGAM_RAMA_EXP_REGION_START_G 0 17 DWB_OGAM_RAMA_EXP_REGION_START_SEGMENT_G 20 26 regDWB_OGAM_RAMA_START_CNTL_R 0 0x32a9 2 0 2 DWB_OGAM_RAMA_EXP_REGION_START_R 0 17 DWB_OGAM_RAMA_EXP_REGION_START_SEGMENT_R 20 26 regDWB_OGAM_RAMA_START_BASE_CNTL_B 0 0x32aa 1 0 2 DWB_OGAM_RAMA_EXP_REGION_START_BASE_B 0 17 regDWB_OGAM_RAMA_START_SLOPE_CNTL_B 0 0x32ab 1 0 2 DWB_OGAM_RAMA_EXP_REGION_START_SLOPE_B 0 17 regDWB_OGAM_RAMA_START_BASE_CNTL_G 0 0x32ac 1 0 2 DWB_OGAM_RAMA_EXP_REGION_START_BASE_G 0 17 regDWB_OGAM_RAMA_START_SLOPE_CNTL_G 0 0x32ad 1 0 2 DWB_OGAM_RAMA_EXP_REGION_START_SLOPE_G 0 17 regDWB_OGAM_RAMA_START_BASE_CNTL_R 0 0x32ae 1 0 2 DWB_OGAM_RAMA_EXP_REGION_START_BASE_R 0 17 regDWB_OGAM_RAMA_START_SLOPE_CNTL_R 0 0x32af 1 0 2 DWB_OGAM_RAMA_EXP_REGION_START_SLOPE_R 0 17 regDWB_OGAM_RAMA_END_CNTL1_B 0 0x32b0 1 0 2 DWB_OGAM_RAMA_EXP_REGION_END_BASE_B 0 17 regDWB_OGAM_RAMA_END_CNTL2_B 0 0x32b1 2 0 2 DWB_OGAM_RAMA_EXP_REGION_END_B 0 15 DWB_OGAM_RAMA_EXP_REGION_END_SLOPE_B 16 31 regDWB_OGAM_RAMA_END_CNTL1_G 0 0x32b2 1 0 2 DWB_OGAM_RAMA_EXP_REGION_END_BASE_G 0 17 regDWB_OGAM_RAMA_END_CNTL2_G 0 0x32b3 2 0 2 DWB_OGAM_RAMA_EXP_REGION_END_G 0 15 DWB_OGAM_RAMA_EXP_REGION_END_SLOPE_G 16 31 regDWB_OGAM_RAMA_END_CNTL1_R 0 0x32b4 1 0 2 DWB_OGAM_RAMA_EXP_REGION_END_BASE_R 0 17 regDWB_OGAM_RAMA_END_CNTL2_R 0 0x32b5 2 0 2 DWB_OGAM_RAMA_EXP_REGION_END_R 0 15 DWB_OGAM_RAMA_EXP_REGION_END_SLOPE_R 16 31 regDWB_OGAM_RAMA_OFFSET_B 0 0x32b6 1 0 2 DWB_OGAM_RAMA_OFFSET_B 0 18 regDWB_OGAM_RAMA_OFFSET_G 0 0x32b7 1 0 2 DWB_OGAM_RAMA_OFFSET_G 0 18 regDWB_OGAM_RAMA_OFFSET_R 0 0x32b8 1 0 2 DWB_OGAM_RAMA_OFFSET_R 0 18 regDWB_OGAM_RAMA_REGION_0_1 0 0x32b9 4 0 2 DWB_OGAM_RAMA_EXP_REGION0_LUT_OFFSET 0 8 DWB_OGAM_RAMA_EXP_REGION0_NUM_SEGMENTS 12 14 DWB_OGAM_RAMA_EXP_REGION1_LUT_OFFSET 16 24 DWB_OGAM_RAMA_EXP_REGION1_NUM_SEGMENTS 28 30 regDWB_OGAM_RAMA_REGION_2_3 0 0x32ba 4 0 2 DWB_OGAM_RAMA_EXP_REGION2_LUT_OFFSET 0 8 DWB_OGAM_RAMA_EXP_REGION2_NUM_SEGMENTS 12 14 DWB_OGAM_RAMA_EXP_REGION3_LUT_OFFSET 16 24 DWB_OGAM_RAMA_EXP_REGION3_NUM_SEGMENTS 28 30 regDWB_OGAM_RAMA_REGION_4_5 0 0x32bb 4 0 2 DWB_OGAM_RAMA_EXP_REGION4_LUT_OFFSET 0 8 DWB_OGAM_RAMA_EXP_REGION4_NUM_SEGMENTS 12 14 DWB_OGAM_RAMA_EXP_REGION5_LUT_OFFSET 16 24 DWB_OGAM_RAMA_EXP_REGION5_NUM_SEGMENTS 28 30 regDWB_OGAM_RAMA_REGION_6_7 0 0x32bc 4 0 2 DWB_OGAM_RAMA_EXP_REGION6_LUT_OFFSET 0 8 DWB_OGAM_RAMA_EXP_REGION6_NUM_SEGMENTS 12 14 DWB_OGAM_RAMA_EXP_REGION7_LUT_OFFSET 16 24 DWB_OGAM_RAMA_EXP_REGION7_NUM_SEGMENTS 28 30 regDWB_OGAM_RAMA_REGION_8_9 0 0x32bd 4 0 2 DWB_OGAM_RAMA_EXP_REGION8_LUT_OFFSET 0 8 DWB_OGAM_RAMA_EXP_REGION8_NUM_SEGMENTS 12 14 DWB_OGAM_RAMA_EXP_REGION9_LUT_OFFSET 16 24 DWB_OGAM_RAMA_EXP_REGION9_NUM_SEGMENTS 28 30 regDWB_OGAM_RAMA_REGION_10_11 0 0x32be 4 0 2 DWB_OGAM_RAMA_EXP_REGION10_LUT_OFFSET 0 8 DWB_OGAM_RAMA_EXP_REGION10_NUM_SEGMENTS 12 14 DWB_OGAM_RAMA_EXP_REGION11_LUT_OFFSET 16 24 DWB_OGAM_RAMA_EXP_REGION11_NUM_SEGMENTS 28 30 regDWB_OGAM_RAMA_REGION_12_13 0 0x32bf 4 0 2 DWB_OGAM_RAMA_EXP_REGION12_LUT_OFFSET 0 8 DWB_OGAM_RAMA_EXP_REGION12_NUM_SEGMENTS 12 14 DWB_OGAM_RAMA_EXP_REGION13_LUT_OFFSET 16 24 DWB_OGAM_RAMA_EXP_REGION13_NUM_SEGMENTS 28 30 regDWB_OGAM_RAMA_REGION_14_15 0 0x32c0 4 0 2 DWB_OGAM_RAMA_EXP_REGION14_LUT_OFFSET 0 8 DWB_OGAM_RAMA_EXP_REGION14_NUM_SEGMENTS 12 14 DWB_OGAM_RAMA_EXP_REGION15_LUT_OFFSET 16 24 DWB_OGAM_RAMA_EXP_REGION15_NUM_SEGMENTS 28 30 regDWB_OGAM_RAMA_REGION_16_17 0 0x32c1 4 0 2 DWB_OGAM_RAMA_EXP_REGION16_LUT_OFFSET 0 8 DWB_OGAM_RAMA_EXP_REGION16_NUM_SEGMENTS 12 14 DWB_OGAM_RAMA_EXP_REGION17_LUT_OFFSET 16 24 DWB_OGAM_RAMA_EXP_REGION17_NUM_SEGMENTS 28 30 regDWB_OGAM_RAMA_REGION_18_19 0 0x32c2 4 0 2 DWB_OGAM_RAMA_EXP_REGION18_LUT_OFFSET 0 8 DWB_OGAM_RAMA_EXP_REGION18_NUM_SEGMENTS 12 14 DWB_OGAM_RAMA_EXP_REGION19_LUT_OFFSET 16 24 DWB_OGAM_RAMA_EXP_REGION19_NUM_SEGMENTS 28 30 regDWB_OGAM_RAMA_REGION_20_21 0 0x32c3 4 0 2 DWB_OGAM_RAMA_EXP_REGION20_LUT_OFFSET 0 8 DWB_OGAM_RAMA_EXP_REGION20_NUM_SEGMENTS 12 14 DWB_OGAM_RAMA_EXP_REGION21_LUT_OFFSET 16 24 DWB_OGAM_RAMA_EXP_REGION21_NUM_SEGMENTS 28 30 regDWB_OGAM_RAMA_REGION_22_23 0 0x32c4 4 0 2 DWB_OGAM_RAMA_EXP_REGION22_LUT_OFFSET 0 8 DWB_OGAM_RAMA_EXP_REGION22_NUM_SEGMENTS 12 14 DWB_OGAM_RAMA_EXP_REGION23_LUT_OFFSET 16 24 DWB_OGAM_RAMA_EXP_REGION23_NUM_SEGMENTS 28 30 regDWB_OGAM_RAMA_REGION_24_25 0 0x32c5 4 0 2 DWB_OGAM_RAMA_EXP_REGION24_LUT_OFFSET 0 8 DWB_OGAM_RAMA_EXP_REGION24_NUM_SEGMENTS 12 14 DWB_OGAM_RAMA_EXP_REGION25_LUT_OFFSET 16 24 DWB_OGAM_RAMA_EXP_REGION25_NUM_SEGMENTS 28 30 regDWB_OGAM_RAMA_REGION_26_27 0 0x32c6 4 0 2 DWB_OGAM_RAMA_EXP_REGION26_LUT_OFFSET 0 8 DWB_OGAM_RAMA_EXP_REGION26_NUM_SEGMENTS 12 14 DWB_OGAM_RAMA_EXP_REGION27_LUT_OFFSET 16 24 DWB_OGAM_RAMA_EXP_REGION27_NUM_SEGMENTS 28 30 regDWB_OGAM_RAMA_REGION_28_29 0 0x32c7 4 0 2 DWB_OGAM_RAMA_EXP_REGION28_LUT_OFFSET 0 8 DWB_OGAM_RAMA_EXP_REGION28_NUM_SEGMENTS 12 14 DWB_OGAM_RAMA_EXP_REGION29_LUT_OFFSET 16 24 DWB_OGAM_RAMA_EXP_REGION29_NUM_SEGMENTS 28 30 regDWB_OGAM_RAMA_REGION_30_31 0 0x32c8 4 0 2 DWB_OGAM_RAMA_EXP_REGION30_LUT_OFFSET 0 8 DWB_OGAM_RAMA_EXP_REGION30_NUM_SEGMENTS 12 14 DWB_OGAM_RAMA_EXP_REGION31_LUT_OFFSET 16 24 DWB_OGAM_RAMA_EXP_REGION31_NUM_SEGMENTS 28 30 regDWB_OGAM_RAMA_REGION_32_33 0 0x32c9 4 0 2 DWB_OGAM_RAMA_EXP_REGION32_LUT_OFFSET 0 8 DWB_OGAM_RAMA_EXP_REGION32_NUM_SEGMENTS 12 14 DWB_OGAM_RAMA_EXP_REGION33_LUT_OFFSET 16 24 DWB_OGAM_RAMA_EXP_REGION33_NUM_SEGMENTS 28 30 regDWB_OGAM_RAMB_START_CNTL_B 0 0x32ca 2 0 2 DWB_OGAM_RAMB_EXP_REGION_START_B 0 17 DWB_OGAM_RAMB_EXP_REGION_START_SEGMENT_B 20 26 regDWB_OGAM_RAMB_START_CNTL_G 0 0x32cb 2 0 2 DWB_OGAM_RAMB_EXP_REGION_START_G 0 17 DWB_OGAM_RAMB_EXP_REGION_START_SEGMENT_G 20 26 regDWB_OGAM_RAMB_START_CNTL_R 0 0x32cc 2 0 2 DWB_OGAM_RAMB_EXP_REGION_START_R 0 17 DWB_OGAM_RAMB_EXP_REGION_START_SEGMENT_R 20 26 regDWB_OGAM_RAMB_START_BASE_CNTL_B 0 0x32cd 1 0 2 DWB_OGAM_RAMB_EXP_REGION_START_BASE_B 0 17 regDWB_OGAM_RAMB_START_SLOPE_CNTL_B 0 0x32ce 1 0 2 DWB_OGAM_RAMB_EXP_REGION_START_SLOPE_B 0 17 regDWB_OGAM_RAMB_START_BASE_CNTL_G 0 0x32cf 1 0 2 DWB_OGAM_RAMB_EXP_REGION_START_BASE_G 0 17 regDWB_OGAM_RAMB_START_SLOPE_CNTL_G 0 0x32d0 1 0 2 DWB_OGAM_RAMB_EXP_REGION_START_SLOPE_G 0 17 regDWB_OGAM_RAMB_START_BASE_CNTL_R 0 0x32d1 1 0 2 DWB_OGAM_RAMB_EXP_REGION_START_BASE_R 0 17 regDWB_OGAM_RAMB_START_SLOPE_CNTL_R 0 0x32d2 1 0 2 DWB_OGAM_RAMB_EXP_REGION_START_SLOPE_R 0 17 regDWB_OGAM_RAMB_END_CNTL1_B 0 0x32d3 1 0 2 DWB_OGAM_RAMB_EXP_REGION_END_BASE_B 0 17 regDWB_OGAM_RAMB_END_CNTL2_B 0 0x32d4 2 0 2 DWB_OGAM_RAMB_EXP_REGION_END_B 0 15 DWB_OGAM_RAMB_EXP_REGION_END_SLOPE_B 16 31 regDWB_OGAM_RAMB_END_CNTL1_G 0 0x32d5 1 0 2 DWB_OGAM_RAMB_EXP_REGION_END_BASE_G 0 17 regDWB_OGAM_RAMB_END_CNTL2_G 0 0x32d6 2 0 2 DWB_OGAM_RAMB_EXP_REGION_END_G 0 15 DWB_OGAM_RAMB_EXP_REGION_END_SLOPE_G 16 31 regDWB_OGAM_RAMB_END_CNTL1_R 0 0x32d7 1 0 2 DWB_OGAM_RAMB_EXP_REGION_END_BASE_R 0 17 regDWB_OGAM_RAMB_END_CNTL2_R 0 0x32d8 2 0 2 DWB_OGAM_RAMB_EXP_REGION_END_R 0 15 DWB_OGAM_RAMB_EXP_REGION_END_SLOPE_R 16 31 regDWB_OGAM_RAMB_OFFSET_B 0 0x32d9 1 0 2 DWB_OGAM_RAMB_OFFSET_B 0 18 regDWB_OGAM_RAMB_OFFSET_G 0 0x32da 1 0 2 DWB_OGAM_RAMB_OFFSET_G 0 18 regDWB_OGAM_RAMB_OFFSET_R 0 0x32db 1 0 2 DWB_OGAM_RAMB_OFFSET_R 0 18 regDWB_OGAM_RAMB_REGION_0_1 0 0x32dc 4 0 2 DWB_OGAM_RAMB_EXP_REGION0_LUT_OFFSET 0 8 DWB_OGAM_RAMB_EXP_REGION0_NUM_SEGMENTS 12 14 DWB_OGAM_RAMB_EXP_REGION1_LUT_OFFSET 16 24 DWB_OGAM_RAMB_EXP_REGION1_NUM_SEGMENTS 28 30 regDWB_OGAM_RAMB_REGION_2_3 0 0x32dd 4 0 2 DWB_OGAM_RAMB_EXP_REGION2_LUT_OFFSET 0 8 DWB_OGAM_RAMB_EXP_REGION2_NUM_SEGMENTS 12 14 DWB_OGAM_RAMB_EXP_REGION3_LUT_OFFSET 16 24 DWB_OGAM_RAMB_EXP_REGION3_NUM_SEGMENTS 28 30 regDWB_OGAM_RAMB_REGION_4_5 0 0x32de 4 0 2 DWB_OGAM_RAMB_EXP_REGION4_LUT_OFFSET 0 8 DWB_OGAM_RAMB_EXP_REGION4_NUM_SEGMENTS 12 14 DWB_OGAM_RAMB_EXP_REGION5_LUT_OFFSET 16 24 DWB_OGAM_RAMB_EXP_REGION5_NUM_SEGMENTS 28 30 regDWB_OGAM_RAMB_REGION_6_7 0 0x32df 4 0 2 DWB_OGAM_RAMB_EXP_REGION6_LUT_OFFSET 0 8 DWB_OGAM_RAMB_EXP_REGION6_NUM_SEGMENTS 12 14 DWB_OGAM_RAMB_EXP_REGION7_LUT_OFFSET 16 24 DWB_OGAM_RAMB_EXP_REGION7_NUM_SEGMENTS 28 30 regDWB_OGAM_RAMB_REGION_8_9 0 0x32e0 4 0 2 DWB_OGAM_RAMB_EXP_REGION8_LUT_OFFSET 0 8 DWB_OGAM_RAMB_EXP_REGION8_NUM_SEGMENTS 12 14 DWB_OGAM_RAMB_EXP_REGION9_LUT_OFFSET 16 24 DWB_OGAM_RAMB_EXP_REGION9_NUM_SEGMENTS 28 30 regDWB_OGAM_RAMB_REGION_10_11 0 0x32e1 4 0 2 DWB_OGAM_RAMB_EXP_REGION10_LUT_OFFSET 0 8 DWB_OGAM_RAMB_EXP_REGION10_NUM_SEGMENTS 12 14 DWB_OGAM_RAMB_EXP_REGION11_LUT_OFFSET 16 24 DWB_OGAM_RAMB_EXP_REGION11_NUM_SEGMENTS 28 30 regDWB_OGAM_RAMB_REGION_12_13 0 0x32e2 4 0 2 DWB_OGAM_RAMB_EXP_REGION12_LUT_OFFSET 0 8 DWB_OGAM_RAMB_EXP_REGION12_NUM_SEGMENTS 12 14 DWB_OGAM_RAMB_EXP_REGION13_LUT_OFFSET 16 24 DWB_OGAM_RAMB_EXP_REGION13_NUM_SEGMENTS 28 30 regDWB_OGAM_RAMB_REGION_14_15 0 0x32e3 4 0 2 DWB_OGAM_RAMB_EXP_REGION14_LUT_OFFSET 0 8 DWB_OGAM_RAMB_EXP_REGION14_NUM_SEGMENTS 12 14 DWB_OGAM_RAMB_EXP_REGION15_LUT_OFFSET 16 24 DWB_OGAM_RAMB_EXP_REGION15_NUM_SEGMENTS 28 30 regDWB_OGAM_RAMB_REGION_16_17 0 0x32e4 4 0 2 DWB_OGAM_RAMB_EXP_REGION16_LUT_OFFSET 0 8 DWB_OGAM_RAMB_EXP_REGION16_NUM_SEGMENTS 12 14 DWB_OGAM_RAMB_EXP_REGION17_LUT_OFFSET 16 24 DWB_OGAM_RAMB_EXP_REGION17_NUM_SEGMENTS 28 30 regDWB_OGAM_RAMB_REGION_18_19 0 0x32e5 4 0 2 DWB_OGAM_RAMB_EXP_REGION18_LUT_OFFSET 0 8 DWB_OGAM_RAMB_EXP_REGION18_NUM_SEGMENTS 12 14 DWB_OGAM_RAMB_EXP_REGION19_LUT_OFFSET 16 24 DWB_OGAM_RAMB_EXP_REGION19_NUM_SEGMENTS 28 30 regDWB_OGAM_RAMB_REGION_20_21 0 0x32e6 4 0 2 DWB_OGAM_RAMB_EXP_REGION20_LUT_OFFSET 0 8 DWB_OGAM_RAMB_EXP_REGION20_NUM_SEGMENTS 12 14 DWB_OGAM_RAMB_EXP_REGION21_LUT_OFFSET 16 24 DWB_OGAM_RAMB_EXP_REGION21_NUM_SEGMENTS 28 30 regDWB_OGAM_RAMB_REGION_22_23 0 0x32e7 4 0 2 DWB_OGAM_RAMB_EXP_REGION22_LUT_OFFSET 0 8 DWB_OGAM_RAMB_EXP_REGION22_NUM_SEGMENTS 12 14 DWB_OGAM_RAMB_EXP_REGION23_LUT_OFFSET 16 24 DWB_OGAM_RAMB_EXP_REGION23_NUM_SEGMENTS 28 30 regDWB_OGAM_RAMB_REGION_24_25 0 0x32e8 4 0 2 DWB_OGAM_RAMB_EXP_REGION24_LUT_OFFSET 0 8 DWB_OGAM_RAMB_EXP_REGION24_NUM_SEGMENTS 12 14 DWB_OGAM_RAMB_EXP_REGION25_LUT_OFFSET 16 24 DWB_OGAM_RAMB_EXP_REGION25_NUM_SEGMENTS 28 30 regDWB_OGAM_RAMB_REGION_26_27 0 0x32e9 4 0 2 DWB_OGAM_RAMB_EXP_REGION26_LUT_OFFSET 0 8 DWB_OGAM_RAMB_EXP_REGION26_NUM_SEGMENTS 12 14 DWB_OGAM_RAMB_EXP_REGION27_LUT_OFFSET 16 24 DWB_OGAM_RAMB_EXP_REGION27_NUM_SEGMENTS 28 30 regDWB_OGAM_RAMB_REGION_28_29 0 0x32ea 4 0 2 DWB_OGAM_RAMB_EXP_REGION28_LUT_OFFSET 0 8 DWB_OGAM_RAMB_EXP_REGION28_NUM_SEGMENTS 12 14 DWB_OGAM_RAMB_EXP_REGION29_LUT_OFFSET 16 24 DWB_OGAM_RAMB_EXP_REGION29_NUM_SEGMENTS 28 30 regDWB_OGAM_RAMB_REGION_30_31 0 0x32eb 4 0 2 DWB_OGAM_RAMB_EXP_REGION30_LUT_OFFSET 0 8 DWB_OGAM_RAMB_EXP_REGION30_NUM_SEGMENTS 12 14 DWB_OGAM_RAMB_EXP_REGION31_LUT_OFFSET 16 24 DWB_OGAM_RAMB_EXP_REGION31_NUM_SEGMENTS 28 30 regDWB_OGAM_RAMB_REGION_32_33 0 0x32ec 4 0 2 DWB_OGAM_RAMB_EXP_REGION32_LUT_OFFSET 0 8 DWB_OGAM_RAMB_EXP_REGION32_NUM_SEGMENTS 12 14 DWB_OGAM_RAMB_EXP_REGION33_LUT_OFFSET 16 24 DWB_OGAM_RAMB_EXP_REGION33_NUM_SEGMENTS 28 30 regDC_PERFMON3_PERFCOUNTER_CNTL 0 0x3288 11 0 2 PERFCOUNTER_EVENT_SEL 0 8 PERFCOUNTER_CVALUE_SEL 9 11 PERFCOUNTER_INC_MODE 12 14 PERFCOUNTER_HW_CNTL_SEL 15 15 PERFCOUNTER_RUNEN_MODE 16 16 PERFCOUNTER_CNTOFF_START_DIS 22 22 PERFCOUNTER_RESTART_EN 23 23 PERFCOUNTER_INT_EN 24 24 PERFCOUNTER_OFF_MASK 25 25 PERFCOUNTER_ACTIVE 26 26 PERFCOUNTER_CNTL_SEL 29 31 regDC_PERFMON3_PERFCOUNTER_CNTL2 0 0x3289 5 0 2 PERFCOUNTER_COUNTED_VALUE_TYPE 0 1 PERFCOUNTER_HW_STOP1_SEL 2 2 PERFCOUNTER_HW_STOP2_SEL 3 3 PERFCOUNTER_CNTOFF_SEL 8 13 PERFCOUNTER_CNTL2_SEL 29 31 regDC_PERFMON3_PERFCOUNTER_STATE 0 0x328a 16 0 2 PERFCOUNTER_CNT0_STATE 0 1 PERFCOUNTER_STATE_SEL0 2 2 PERFCOUNTER_CNT1_STATE 4 5 PERFCOUNTER_STATE_SEL1 6 6 PERFCOUNTER_CNT2_STATE 8 9 PERFCOUNTER_STATE_SEL2 10 10 PERFCOUNTER_CNT3_STATE 12 13 PERFCOUNTER_STATE_SEL3 14 14 PERFCOUNTER_CNT4_STATE 16 17 PERFCOUNTER_STATE_SEL4 18 18 PERFCOUNTER_CNT5_STATE 20 21 PERFCOUNTER_STATE_SEL5 22 22 PERFCOUNTER_CNT6_STATE 24 25 PERFCOUNTER_STATE_SEL6 26 26 PERFCOUNTER_CNT7_STATE 28 29 PERFCOUNTER_STATE_SEL7 30 30 regDC_PERFMON3_PERFMON_CNTL 0 0x328b 6 0 2 PERFMON_STATE 0 1 PERFMON_RPT_COUNT 8 27 PERFMON_CNTOFF_AND_OR 28 28 PERFMON_CNTOFF_INT_EN 29 29 PERFMON_CNTOFF_INT_STATUS 30 30 PERFMON_CNTOFF_INT_ACK 31 31 regDC_PERFMON3_PERFMON_CNTL2 0 0x328c 4 0 2 PERFMON_CNTOFF_INT_TYPE 0 0 PERFMON_CLK_ENABLE 1 1 PERFMON_RUN_ENABLE_START_SEL 2 9 PERFMON_RUN_ENABLE_STOP_SEL 10 17 regDC_PERFMON3_PERFMON_CVALUE_INT_MISC 0 0x328d 17 0 2 PERFCOUNTER_INT0_STATUS 0 0 PERFCOUNTER_INT1_STATUS 1 1 PERFCOUNTER_INT2_STATUS 2 2 PERFCOUNTER_INT3_STATUS 3 3 PERFCOUNTER_INT4_STATUS 4 4 PERFCOUNTER_INT5_STATUS 5 5 PERFCOUNTER_INT6_STATUS 6 6 PERFCOUNTER_INT7_STATUS 7 7 PERFCOUNTER_INT0_ACK 8 8 PERFCOUNTER_INT1_ACK 9 9 PERFCOUNTER_INT2_ACK 10 10 PERFCOUNTER_INT3_ACK 11 11 PERFCOUNTER_INT4_ACK 12 12 PERFCOUNTER_INT5_ACK 13 13 PERFCOUNTER_INT6_ACK 14 14 PERFCOUNTER_INT7_ACK 15 15 PERFMON_CVALUE_HI 16 31 regDC_PERFMON3_PERFMON_CVALUE_LOW 0 0x328e 1 0 2 PERFMON_CVALUE_LOW 0 31 regDC_PERFMON3_PERFMON_HI 0 0x328f 2 0 2 PERFMON_HI 0 15 PERFMON_READ_SEL 29 31 regDC_PERFMON3_PERFMON_LOW 0 0x3290 1 0 2 PERFMON_LOW 0 31 regVGA_MEM_WRITE_PAGE_ADDR 0 0x0 2 0 0 VGA_MEM_WRITE_PAGE0_ADDR 0 9 VGA_MEM_WRITE_PAGE1_ADDR 16 25 regVGA_MEM_READ_PAGE_ADDR 0 0x1 2 0 0 VGA_MEM_READ_PAGE0_ADDR 0 9 VGA_MEM_READ_PAGE1_ADDR 16 25 regVGA_RENDER_CONTROL 0 0x0 7 0 1 VGA_BLINK_RATE 0 4 VGA_BLINK_MODE 5 6 VGA_CURSOR_BLINK_INVERT 7 7 VGA_EXTD_ADDR_COUNT_ENABLE 8 8 VGA_VSTATUS_CNTL 16 17 VGA_LOCK_8DOT 24 24 VGAREG_LINECMP_COMPATIBILITY_SEL 25 25 regVGA_SEQUENCER_RESET_CONTROL 0 0x1 15 0 1 D1_BLANK_DISPLAY_WHEN_SEQUENCER_RESET 0 0 D2_BLANK_DISPLAY_WHEN_SEQUENCER_RESET 1 1 D3_BLANK_DISPLAY_WHEN_SEQUENCER_RESET 2 2 D4_BLANK_DISPLAY_WHEN_SEQUENCER_RESET 3 3 D5_BLANK_DISPLAY_WHEN_SEQUENCER_RESET 4 4 D6_BLANK_DISPLAY_WHEN_SEQUENCER_RESET 5 5 D1_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET 8 8 D2_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET 9 9 D3_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET 10 10 D4_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET 11 11 D5_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET 12 12 D6_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET 13 13 VGA_MODE_AUTO_TRIGGER_ENABLE 16 16 VGA_MODE_AUTO_TRIGGER_REGISTER_SELECT 17 17 VGA_MODE_AUTO_TRIGGER_INDEX_SELECT 18 23 regVGA_MODE_CONTROL 0 0x2 5 0 1 VGA_ATI_LINEAR 0 0 VGA_LUT_PALETTE_UPDATE_MODE 4 5 VGA_128K_APERTURE_PAGING 8 8 VGA_TEXT_132_COLUMNS_EN 16 16 VGA_DEEP_SLEEP_FORCE_EXIT 24 24 regVGA_SURFACE_PITCH_SELECT 0 0x3 2 0 1 VGA_SURFACE_PITCH_SELECT 0 1 VGA_SURFACE_HEIGHT_SELECT 8 9 regVGA_MEMORY_BASE_ADDRESS 0 0x4 1 0 1 VGA_MEMORY_BASE_ADDRESS 0 31 regVGA_TEST_DEBUG_INDEX 0 0x5 2 0 1 VGA_TEST_DEBUG_INDEX 0 7 VGA_TEST_DEBUG_WRITE_EN 8 8 regVGA_DISPBUF1_SURFACE_ADDR 0 0x6 1 0 1 VGA_DISPBUF1_SURFACE_ADDR 0 24 regVGA_TEST_DEBUG_DATA 0 0x7 1 0 1 VGA_TEST_DEBUG_DATA 0 31 regVGA_DISPBUF2_SURFACE_ADDR 0 0x8 1 0 1 VGA_DISPBUF2_SURFACE_ADDR 0 24 regVGA_MEMORY_BASE_ADDRESS_HIGH 0 0x9 1 0 1 VGA_MEMORY_BASE_ADDRESS_HIGH 0 15 regVGA_HDP_CONTROL 0 0xa 5 0 1 VGA_MEM_PAGE_SELECT_EN 0 0 VGA_MEMORY_DISABLE 4 4 VGA_RBBM_LOCK_DISABLE 8 8 VGA_SOFT_RESET 16 16 VGA_TEST_RESET_CONTROL 24 24 regVGA_CACHE_CONTROL 0 0xb 5 0 1 VGA_WRITE_THROUGH_CACHE_DIS 0 0 VGA_READ_CACHE_DISABLE 8 8 VGA_READ_BUFFER_INVALIDATE 16 16 VGA_DCCIF_W256ONLY 20 20 VGA_DCCIF_WC_TIMEOUT 24 29 regD1VGA_CONTROL 0 0xc 5 0 1 D1VGA_MODE_ENABLE 0 0 D1VGA_TIMING_SELECT 8 8 D1VGA_SYNC_POLARITY_SELECT 9 9 D1VGA_OVERSCAN_COLOR_EN 16 16 D1VGA_ROTATE 24 25 regVGA_SECURITY_LEVEL 0 0xd 1 0 1 VGA_SECURITY_LEVEL 0 3 regD2VGA_CONTROL 0 0xe 5 0 1 D2VGA_MODE_ENABLE 0 0 D2VGA_TIMING_SELECT 8 8 D2VGA_SYNC_POLARITY_SELECT 9 9 D2VGA_OVERSCAN_COLOR_EN 16 16 D2VGA_ROTATE 24 25 regVGA_HW_DEBUG 0 0xf 1 0 1 VGA_HW_DEBUG 0 31 regVGA_STATUS 0 0x10 4 0 1 VGA_MEM_ACCESS_STATUS 0 0 VGA_REG_ACCESS_STATUS 1 1 VGA_DISPLAY_SWITCH_STATUS 2 2 VGA_MODE_AUTO_TRIGGER_STATUS 3 3 regVGA_STATUS_CLEAR 0 0x12 4 0 1 VGA_MEM_ACCESS_INT_CLEAR 0 0 VGA_REG_ACCESS_INT_CLEAR 8 8 VGA_DISPLAY_SWITCH_INT_CLEAR 16 16 VGA_MODE_AUTO_TRIGGER_INT_CLEAR 24 24 regVGA_MAIN_CONTROL 0 0x14 10 0 1 VGA_CRTC_TIMEOUT 0 1 VGA_RENDER_TIMEOUT_COUNT 3 4 VGA_VIRTUAL_VERTICAL_RETRACE_DURATION 5 7 VGA_READBACK_VGA_VSTATUS_SOURCE_SELECT 8 9 VGA_MC_WRITE_CLEAN_WAIT_DELAY 12 15 VGA_READBACK_NO_DISPLAY_SOURCE_SELECT 16 17 VGA_READBACK_CRT_INTR_SOURCE_SELECT 24 25 VGA_READBACK_SENSE_SWITCH_SELECT 26 26 VGA_EXTERNAL_DAC_SENSE 29 29 VGA_MAIN_TEST_VSTATUS_NO_DISPLAY_CRTC_TIMEOUT 31 31 regVGA_TEST_CONTROL 0 0x15 4 0 1 VGA_TEST_ENABLE 0 0 VGA_TEST_RENDER_START 8 8 VGA_TEST_RENDER_DONE 16 16 VGA_TEST_RENDER_DISPBUF_SELECT 24 24 regVGA_DEBUG_READBACK_INDEX 0 0x16 1 0 1 VGA_DEBUG_READBACK_INDEX 0 7 regVGA_DEBUG_READBACK_DATA 0 0x17 1 0 1 VGA_DEBUG_READBACK_DATA 0 31 regVGA_QOS_CTRL 0 0x18 2 0 1 VGA_READ_QOS 0 3 VGA_WRITE_QOS 4 7 regCRTC8_IDX 0 0x2d 1 0 1 VCRTC_IDX 0 5 regCRTC8_DATA 0 0x2d 1 0 1 VCRTC_DATA 0 7 regGENFC_WT 0 0x2e 1 0 1 VSYNC_SEL_W 3 3 regGENS1 0 0x2e 3 0 1 NO_DISPLAY 0 0 VGA_VSTATUS 3 3 PIXEL_READ_BACK 4 5 regATTRDW 0 0x30 1 0 1 ATTR_DATA 0 7 regATTRX 0 0x30 2 0 1 ATTR_IDX 0 4 ATTR_PAL_RW_ENB 5 5 regATTRDR 0 0x30 1 0 1 ATTR_DATA 0 7 regGENMO_WT 0 0x30 6 0 1 GENMO_MONO_ADDRESS_B 0 0 VGA_RAM_EN 1 1 VGA_CKSEL 2 3 ODD_EVEN_MD_PGSEL 5 5 VGA_HSYNC_POL 6 6 VGA_VSYNC_POL 7 7 regGENS0 0 0x30 2 0 1 SENSE_SWITCH 4 4 CRT_INTR 7 7 regGENENB 0 0x30 1 0 1 BLK_IO_BASE 0 7 regSEQ8_IDX 0 0x31 1 0 1 SEQ_IDX 0 2 regSEQ8_DATA 0 0x31 1 0 1 SEQ_DATA 0 7 regDAC_MASK 0 0x31 1 0 1 DAC_MASK 0 7 regDAC_R_INDEX 0 0x31 1 0 1 DAC_R_INDEX 0 7 regDAC_W_INDEX 0 0x32 1 0 1 DAC_W_INDEX 0 7 regDAC_DATA 0 0x32 1 0 1 DAC_DATA 0 5 regGENFC_RD 0 0x32 1 0 1 VSYNC_SEL_R 3 3 regGENMO_RD 0 0x33 6 0 1 GENMO_MONO_ADDRESS_B 0 0 VGA_RAM_EN 1 1 VGA_CKSEL 2 3 ODD_EVEN_MD_PGSEL 5 5 VGA_HSYNC_POL 6 6 VGA_VSYNC_POL 7 7 regGRPH8_IDX 0 0x33 1 0 1 GRPH_IDX 0 3 regGRPH8_DATA 0 0x33 1 0 1 GRPH_DATA 0 7 regCRTC8_IDX_1 0 0x35 1 0 1 VCRTC_IDX 0 5 regCRTC8_DATA_1 0 0x35 1 0 1 VCRTC_DATA 0 7 regGENFC_WT_1 0 0x36 1 0 1 VSYNC_SEL_W 3 3 regGENS1_1 0 0x36 3 0 1 NO_DISPLAY 0 0 VGA_VSTATUS 3 3 PIXEL_READ_BACK 4 5 regD3VGA_CONTROL 0 0x38 5 0 1 D3VGA_MODE_ENABLE 0 0 D3VGA_TIMING_SELECT 8 8 D3VGA_SYNC_POLARITY_SELECT 9 9 D3VGA_OVERSCAN_COLOR_EN 16 16 D3VGA_ROTATE 24 25 regD4VGA_CONTROL 0 0x39 5 0 1 D4VGA_MODE_ENABLE 0 0 D4VGA_TIMING_SELECT 8 8 D4VGA_SYNC_POLARITY_SELECT 9 9 D4VGA_OVERSCAN_COLOR_EN 16 16 D4VGA_ROTATE 24 25 regD5VGA_CONTROL 0 0x3a 5 0 1 D5VGA_MODE_ENABLE 0 0 D5VGA_TIMING_SELECT 8 8 D5VGA_SYNC_POLARITY_SELECT 9 9 D5VGA_OVERSCAN_COLOR_EN 16 16 D5VGA_ROTATE 24 25 regD6VGA_CONTROL 0 0x3b 5 0 1 D6VGA_MODE_ENABLE 0 0 D6VGA_TIMING_SELECT 8 8 D6VGA_SYNC_POLARITY_SELECT 9 9 D6VGA_OVERSCAN_COLOR_EN 16 16 D6VGA_ROTATE 24 25 regVGA_SOURCE_SELECT 0 0x3c 2 0 1 VGA_SOURCE_SEL_A 0 2 VGA_SOURCE_SEL_B 8 10 regMCIF_CONTROL 0 0x34a 2 0 2 MCIF_MC_LATENCY_COUNTER_ENABLE 30 30 MCIF_MC_LATENCY_COUNTER_URGENT_ONLY 31 31 regMCIF_WRITE_COMBINE_CONTROL 0 0x34b 1 0 2 MCIF_WRITE_COMBINE_TIMEOUT 0 9 regMCIF_PHASE0_OUTSTANDING_COUNTER 0 0x34e 1 0 2 MCIF_PHASE0_OUTSTANDING_COUNTER 0 26 regMCIF_PHASE1_OUTSTANDING_COUNTER 0 0x34f 1 0 2 MCIF_PHASE1_OUTSTANDING_COUNTER 0 26 regMCIF_PHASE2_OUTSTANDING_COUNTER 0 0x350 1 0 2 MCIF_PHASE2_OUTSTANDING_COUNTER 0 26 regMCIF_WB_BUFMGR_SW_CONTROL 0 0x272 7 0 2 MCIF_WB_BUFMGR_ENABLE 0 0 MCIF_WB_BUFMGR_SW_INT_EN 4 4 MCIF_WB_BUFMGR_SW_INT_ACK 5 5 MCIF_WB_BUFMGR_SW_SLICE_INT_EN 6 6 MCIF_WB_BUFMGR_SW_OVERRUN_INT_EN 7 7 MCIF_WB_BUFMGR_SW_LOCK 8 11 MCIF_WB_BUF_ADDR_FENCE_EN 24 24 regMCIF_WB_BUFMGR_STATUS 0 0x274 8 0 2 MCIF_WB_BUFMGR_VCE_INT_STATUS 0 0 MCIF_WB_BUFMGR_SW_INT_STATUS 1 1 MCIF_WB_BUFMGR_SW_OVERRUN_INT_STATUS 2 2 MCIF_WB_BUFMGR_CUR_BUF 4 6 MCIF_WB_BUF_DUALSIZE_STATUS 7 7 MCIF_WB_BUFMGR_BUFTAG 8 11 MCIF_WB_BUFMGR_CUR_LINE_L 12 24 MCIF_WB_BUFMGR_NEXT_BUF 28 30 regMCIF_WB_BUF_PITCH 0 0x275 2 0 2 MCIF_WB_BUF_LUMA_PITCH 8 15 MCIF_WB_BUF_CHROMA_PITCH 24 31 regMCIF_WB_BUF_1_STATUS 0 0x276 9 0 2 MCIF_WB_BUF_1_ACTIVE 0 0 MCIF_WB_BUF_1_SW_LOCKED 1 1 MCIF_WB_BUF_1_VCE_LOCKED 2 2 MCIF_WB_BUF_1_OVERFLOW 3 3 MCIF_WB_BUF_1_DISABLE 4 4 MCIF_WB_BUF_1_MODE 5 7 MCIF_WB_BUF_1_BUFTAG 8 11 MCIF_WB_BUF_1_NXT_BUF 12 14 MCIF_WB_BUF_1_CUR_LINE_L 16 28 regMCIF_WB_BUF_1_STATUS2 0 0x277 7 0 2 MCIF_WB_BUF_1_NEW_CONTENT 13 13 MCIF_WB_BUF_1_COLOR_DEPTH 14 14 MCIF_WB_BUF_1_TMZ_BLACK_PIXEL 15 15 MCIF_WB_BUF_1_TMZ 16 16 MCIF_WB_BUF_1_Y_OVERRUN 17 17 MCIF_WB_BUF_1_C_OVERRUN 18 18 MCIF_WB_BUF_1_EYE_FLAG 19 19 regMCIF_WB_BUF_2_STATUS 0 0x278 9 0 2 MCIF_WB_BUF_2_ACTIVE 0 0 MCIF_WB_BUF_2_SW_LOCKED 1 1 MCIF_WB_BUF_2_VCE_LOCKED 2 2 MCIF_WB_BUF_2_OVERFLOW 3 3 MCIF_WB_BUF_2_DISABLE 4 4 MCIF_WB_BUF_2_MODE 5 7 MCIF_WB_BUF_2_BUFTAG 8 11 MCIF_WB_BUF_2_NXT_BUF 12 14 MCIF_WB_BUF_2_CUR_LINE_L 16 28 regMCIF_WB_BUF_2_STATUS2 0 0x279 7 0 2 MCIF_WB_BUF_2_NEW_CONTENT 13 13 MCIF_WB_BUF_2_COLOR_DEPTH 14 14 MCIF_WB_BUF_2_TMZ_BLACK_PIXEL 15 15 MCIF_WB_BUF_2_TMZ 16 16 MCIF_WB_BUF_2_Y_OVERRUN 17 17 MCIF_WB_BUF_2_C_OVERRUN 18 18 MCIF_WB_BUF_2_EYE_FLAG 19 19 regMCIF_WB_BUF_3_STATUS 0 0x27a 9 0 2 MCIF_WB_BUF_3_ACTIVE 0 0 MCIF_WB_BUF_3_SW_LOCKED 1 1 MCIF_WB_BUF_3_VCE_LOCKED 2 2 MCIF_WB_BUF_3_OVERFLOW 3 3 MCIF_WB_BUF_3_DISABLE 4 4 MCIF_WB_BUF_3_MODE 5 7 MCIF_WB_BUF_3_BUFTAG 8 11 MCIF_WB_BUF_3_NXT_BUF 12 14 MCIF_WB_BUF_3_CUR_LINE_L 16 28 regMCIF_WB_BUF_3_STATUS2 0 0x27b 7 0 2 MCIF_WB_BUF_3_NEW_CONTENT 13 13 MCIF_WB_BUF_3_COLOR_DEPTH 14 14 MCIF_WB_BUF_3_TMZ_BLACK_PIXEL 15 15 MCIF_WB_BUF_3_TMZ 16 16 MCIF_WB_BUF_3_Y_OVERRUN 17 17 MCIF_WB_BUF_3_C_OVERRUN 18 18 MCIF_WB_BUF_3_EYE_FLAG 19 19 regMCIF_WB_BUF_4_STATUS 0 0x27c 9 0 2 MCIF_WB_BUF_4_ACTIVE 0 0 MCIF_WB_BUF_4_SW_LOCKED 1 1 MCIF_WB_BUF_4_VCE_LOCKED 2 2 MCIF_WB_BUF_4_OVERFLOW 3 3 MCIF_WB_BUF_4_DISABLE 4 4 MCIF_WB_BUF_4_MODE 5 7 MCIF_WB_BUF_4_BUFTAG 8 11 MCIF_WB_BUF_4_NXT_BUF 12 14 MCIF_WB_BUF_4_CUR_LINE_L 16 28 regMCIF_WB_BUF_4_STATUS2 0 0x27d 7 0 2 MCIF_WB_BUF_4_NEW_CONTENT 13 13 MCIF_WB_BUF_4_COLOR_DEPTH 14 14 MCIF_WB_BUF_4_TMZ_BLACK_PIXEL 15 15 MCIF_WB_BUF_4_TMZ 16 16 MCIF_WB_BUF_4_Y_OVERRUN 17 17 MCIF_WB_BUF_4_C_OVERRUN 18 18 MCIF_WB_BUF_4_EYE_FLAG 19 19 regMCIF_WB_ARBITRATION_CONTROL 0 0x27e 2 0 2 MCIF_WB_CLIENT_ARBITRATION_SLICE 0 1 MCIF_WB_TIME_PER_PIXEL 20 31 regMCIF_WB_SCLK_CHANGE 0 0x27f 1 0 2 WM_CHANGE_ACK_FORCE_ON 0 0 regMCIF_WB_TEST_DEBUG_INDEX 0 0x280 2 0 2 MCIF_WB_TEST_DEBUG_INDEX 0 7 MCIF_WB_TEST_DEBUG_WRITE_EN 8 8 regMCIF_WB_TEST_DEBUG_DATA 0 0x281 1 0 2 MCIF_WB_TEST_DEBUG_DATA 0 31 regMCIF_WB_BUF_1_ADDR_Y 0 0x282 1 0 2 MCIF_WB_BUF_1_ADDR_Y 0 31 regMCIF_WB_BUF_1_ADDR_C 0 0x284 1 0 2 MCIF_WB_BUF_1_ADDR_C 0 31 regMCIF_WB_BUF_2_ADDR_Y 0 0x286 1 0 2 MCIF_WB_BUF_2_ADDR_Y 0 31 regMCIF_WB_BUF_2_ADDR_C 0 0x288 1 0 2 MCIF_WB_BUF_2_ADDR_C 0 31 regMCIF_WB_BUF_3_ADDR_Y 0 0x28a 1 0 2 MCIF_WB_BUF_3_ADDR_Y 0 31 regMCIF_WB_BUF_3_ADDR_C 0 0x28c 1 0 2 MCIF_WB_BUF_3_ADDR_C 0 31 regMCIF_WB_BUF_4_ADDR_Y 0 0x28e 1 0 2 MCIF_WB_BUF_4_ADDR_Y 0 31 regMCIF_WB_BUF_4_ADDR_C 0 0x290 1 0 2 MCIF_WB_BUF_4_ADDR_C 0 31 regMCIF_WB_BUFMGR_VCE_CONTROL 0 0x292 6 0 2 MCIF_WB_BUFMGR_VCE_LOCK_IGNORE 0 0 MCIF_WB_BUFMGR_VCE_INT_EN 4 4 MCIF_WB_BUFMGR_VCE_INT_ACK 5 5 MCIF_WB_BUFMGR_VCE_SLICE_INT_EN 6 6 MCIF_WB_BUFMGR_VCE_LOCK 8 11 MCIF_WB_BUFMGR_SLICE_SIZE 16 28 regMCIF_WB_NB_PSTATE_CONTROL 0 0x293 3 0 2 NB_PSTATE_CHANGE_URGENT_DURING_REQUEST 0 0 NB_PSTATE_CHANGE_FORCE_ON 1 1 NB_PSTATE_ALLOW_FOR_URGENT 2 2 regMCIF_WB_CLOCK_GATER_CONTROL 0 0x294 1 0 2 MCIF_WB_CLI_CLOCK_GATER_OVERRIDE 0 0 regMCIF_WB_SELF_REFRESH_CONTROL 0 0x296 2 0 2 DIS_REFRESH_UNDER_NBPREQ 0 0 PERFRAME_SELF_REFRESH 1 1 regMULTI_LEVEL_QOS_CTRL 0 0x297 1 0 2 MAX_SCALED_TIME_TO_URGENT 0 21 regMCIF_WB_BUF_LUMA_SIZE 0 0x299 1 0 2 MCIF_WB_BUF_LUMA_SIZE 0 19 regMCIF_WB_BUF_CHROMA_SIZE 0 0x29a 1 0 2 MCIF_WB_BUF_CHROMA_SIZE 0 19 regMCIF_WB_BUF_1_ADDR_Y_HIGH 0 0x29b 1 0 2 MCIF_WB_BUF_1_ADDR_Y_HIGH 0 7 regMCIF_WB_BUF_1_ADDR_C_HIGH 0 0x29c 1 0 2 MCIF_WB_BUF_1_ADDR_C_HIGH 0 7 regMCIF_WB_BUF_2_ADDR_Y_HIGH 0 0x29d 1 0 2 MCIF_WB_BUF_2_ADDR_Y_HIGH 0 7 regMCIF_WB_BUF_2_ADDR_C_HIGH 0 0x29e 1 0 2 MCIF_WB_BUF_2_ADDR_C_HIGH 0 7 regMCIF_WB_BUF_3_ADDR_Y_HIGH 0 0x29f 1 0 2 MCIF_WB_BUF_3_ADDR_Y_HIGH 0 7 regMCIF_WB_BUF_3_ADDR_C_HIGH 0 0x2a0 1 0 2 MCIF_WB_BUF_3_ADDR_C_HIGH 0 7 regMCIF_WB_BUF_4_ADDR_Y_HIGH 0 0x2a1 1 0 2 MCIF_WB_BUF_4_ADDR_Y_HIGH 0 7 regMCIF_WB_BUF_4_ADDR_C_HIGH 0 0x2a2 1 0 2 MCIF_WB_BUF_4_ADDR_C_HIGH 0 7 regMCIF_WB_BUF_1_RESOLUTION 0 0x2a3 2 0 2 MCIF_WB_BUF_1_RESOLUTION_WIDTH 0 12 MCIF_WB_BUF_1_RESOLUTION_HEIGHT 16 28 regMCIF_WB_BUF_2_RESOLUTION 0 0x2a4 2 0 2 MCIF_WB_BUF_2_RESOLUTION_WIDTH 0 12 MCIF_WB_BUF_2_RESOLUTION_HEIGHT 16 28 regMCIF_WB_BUF_3_RESOLUTION 0 0x2a5 2 0 2 MCIF_WB_BUF_3_RESOLUTION_WIDTH 0 12 MCIF_WB_BUF_3_RESOLUTION_HEIGHT 16 28 regMCIF_WB_BUF_4_RESOLUTION 0 0x2a6 2 0 2 MCIF_WB_BUF_4_RESOLUTION_WIDTH 0 12 MCIF_WB_BUF_4_RESOLUTION_HEIGHT 16 28 regMCIF_WB_DRAM_SPEED_CHANGE_DURATION_VBI 0 0x2a7 1 0 2 MCIF_WB_DRAM_SPEED_CHANGE_DURATION_VBI 0 15 regMCIF_WB_VMID_CONTROL 0 0x2a8 1 0 2 MCIF_WB_P_VMID 0 3 regMCIF_WB_MIN_TTO 0 0x2a9 1 0 2 MCIF_WB_MIN_TTO 0 18 regDC_PERFMON4_PERFCOUNTER_CNTL 0 0x352 11 0 2 PERFCOUNTER_EVENT_SEL 0 8 PERFCOUNTER_CVALUE_SEL 9 11 PERFCOUNTER_INC_MODE 12 14 PERFCOUNTER_HW_CNTL_SEL 15 15 PERFCOUNTER_RUNEN_MODE 16 16 PERFCOUNTER_CNTOFF_START_DIS 22 22 PERFCOUNTER_RESTART_EN 23 23 PERFCOUNTER_INT_EN 24 24 PERFCOUNTER_OFF_MASK 25 25 PERFCOUNTER_ACTIVE 26 26 PERFCOUNTER_CNTL_SEL 29 31 regDC_PERFMON4_PERFCOUNTER_CNTL2 0 0x353 5 0 2 PERFCOUNTER_COUNTED_VALUE_TYPE 0 1 PERFCOUNTER_HW_STOP1_SEL 2 2 PERFCOUNTER_HW_STOP2_SEL 3 3 PERFCOUNTER_CNTOFF_SEL 8 13 PERFCOUNTER_CNTL2_SEL 29 31 regDC_PERFMON4_PERFCOUNTER_STATE 0 0x354 16 0 2 PERFCOUNTER_CNT0_STATE 0 1 PERFCOUNTER_STATE_SEL0 2 2 PERFCOUNTER_CNT1_STATE 4 5 PERFCOUNTER_STATE_SEL1 6 6 PERFCOUNTER_CNT2_STATE 8 9 PERFCOUNTER_STATE_SEL2 10 10 PERFCOUNTER_CNT3_STATE 12 13 PERFCOUNTER_STATE_SEL3 14 14 PERFCOUNTER_CNT4_STATE 16 17 PERFCOUNTER_STATE_SEL4 18 18 PERFCOUNTER_CNT5_STATE 20 21 PERFCOUNTER_STATE_SEL5 22 22 PERFCOUNTER_CNT6_STATE 24 25 PERFCOUNTER_STATE_SEL6 26 26 PERFCOUNTER_CNT7_STATE 28 29 PERFCOUNTER_STATE_SEL7 30 30 regDC_PERFMON4_PERFMON_CNTL 0 0x355 6 0 2 PERFMON_STATE 0 1 PERFMON_RPT_COUNT 8 27 PERFMON_CNTOFF_AND_OR 28 28 PERFMON_CNTOFF_INT_EN 29 29 PERFMON_CNTOFF_INT_STATUS 30 30 PERFMON_CNTOFF_INT_ACK 31 31 regDC_PERFMON4_PERFMON_CNTL2 0 0x356 4 0 2 PERFMON_CNTOFF_INT_TYPE 0 0 PERFMON_CLK_ENABLE 1 1 PERFMON_RUN_ENABLE_START_SEL 2 9 PERFMON_RUN_ENABLE_STOP_SEL 10 17 regDC_PERFMON4_PERFMON_CVALUE_INT_MISC 0 0x357 17 0 2 PERFCOUNTER_INT0_STATUS 0 0 PERFCOUNTER_INT1_STATUS 1 1 PERFCOUNTER_INT2_STATUS 2 2 PERFCOUNTER_INT3_STATUS 3 3 PERFCOUNTER_INT4_STATUS 4 4 PERFCOUNTER_INT5_STATUS 5 5 PERFCOUNTER_INT6_STATUS 6 6 PERFCOUNTER_INT7_STATUS 7 7 PERFCOUNTER_INT0_ACK 8 8 PERFCOUNTER_INT1_ACK 9 9 PERFCOUNTER_INT2_ACK 10 10 PERFCOUNTER_INT3_ACK 11 11 PERFCOUNTER_INT4_ACK 12 12 PERFCOUNTER_INT5_ACK 13 13 PERFCOUNTER_INT6_ACK 14 14 PERFCOUNTER_INT7_ACK 15 15 PERFMON_CVALUE_HI 16 31 regDC_PERFMON4_PERFMON_CVALUE_LOW 0 0x358 1 0 2 PERFMON_CVALUE_LOW 0 31 regDC_PERFMON4_PERFMON_HI 0 0x359 2 0 2 PERFMON_HI 0 15 PERFMON_READ_SEL 29 31 regDC_PERFMON4_PERFMON_LOW 0 0x35a 1 0 2 PERFMON_LOW 0 31 regMCIF_WB_NB_PSTATE_LATENCY_WATERMARK 0 0x2aa 2 0 2 NB_PSTATE_CHANGE_REFRESH_WATERMARK 0 20 NB_PSTATE_CHANGE_WATERMARK_MASK 24 26 regMCIF_WB_WATERMARK 0 0x2ab 2 0 2 MCIF_WB_CLI_WATERMARK 0 20 MCIF_WB_CLI_WATERMARK_MASK 24 26 regMMHUBBUB_WARMUP_CONFIG 0 0x2ac 2 0 2 MMHUBBUB_WARMUP_QOS 16 19 MMHUBBUB_WARMUP_AWID 20 23 regMMHUBBUB_WARMUP_CONTROL_STATUS 0 0x2ad 5 0 2 MMHUBBUB_WARMUP_EN 0 0 MMHUBBUB_WARMUP_SW_INT_EN 4 4 MMHUBBUB_WARMUP_SW_INT_STATUS 5 5 MMHUBBUB_WARMUP_SW_INT_ACK 6 6 MMHUBBUB_WARMUP_INC_ADDR 8 25 regMMHUBBUB_WARMUP_BASE_ADDR_LOW 0 0x2ae 1 0 2 MMHUBBUB_WARMUP_BASE_ADDR_LOW 0 31 regMMHUBBUB_WARMUP_BASE_ADDR_HIGH 0 0x2af 1 0 2 MMHUBBUB_WARMUP_BASE_ADDR_HIGH 0 10 regMMHUBBUB_WARMUP_ADDR_REGION 0 0x2b0 1 0 2 MMHUBBUB_WARMUP_ADDR_REGION 0 26 regMMHUBBUB_MIN_TTO 0 0x2b1 1 0 2 MMHUBBUB_MIN_TTO 0 18 regMMHUBBUB_CTRL 0 0x333 1 0 2 MMHUB_SOCCLK_DS_MODE 0 1 regWBIF_SMU_WM_CONTROL 0 0x334 2 0 2 MCIF_WB_WM_CHG_SEL 20 21 MCIF_WB_WM_CHG_REQ 22 22 regWBIF0_MISC_CTRL 0 0x335 4 0 2 MCIFWB0_WR_COMBINE_TIMEOUT_THRESH 0 9 MCIF_WB0_SOCCLK_DS_ENABLE 16 16 MCIF_WB0_WM_CHG_ACK_INT_DIS 24 24 MCIF_WB0_WM_CHG_ACK_INT_STATUS 25 25 regWBIF0_PHASE0_OUTSTANDING_COUNTER 0 0x336 1 0 2 MCIF_WB0_PHASE0_OUTSTANDING_COUNTER 0 26 regWBIF0_PHASE1_OUTSTANDING_COUNTER 0 0x337 1 0 2 MCIF_WB0_PHASE1_OUTSTANDING_COUNTER 0 26 regVGA_SRC_SPLIT_CNTL 0 0x33e 1 0 2 VGA_SPLIT_SEL 0 1 regMMHUBBUB_MEM_PWR_STATUS 0 0x33f 5 0 2 MCIF_DWB0_LUMA_MEM0_PWR_STATE 0 1 MCIF_DWB0_LUMA_MEM1_PWR_STATE 2 3 MCIF_DWB0_CHROMA_MEM0_PWR_STATE 4 5 MCIF_DWB0_CHROMA_MEM1_PWR_STATE 6 7 VGA_MEM_PWR_STATE 31 31 regMMHUBBUB_MEM_PWR_CNTL 0 0x340 7 0 2 VGA_MEM_PWR_FORCE 0 0 VGA_MEM_PWR_DIS 1 1 MCIF_DWB0_MEM_PWR_FORCE 2 3 MCIF_DWB0_MEM_PWR_DIS 4 4 MCIF_DWB0_MEM_PWR_MODE_SEL 5 6 MCIF_DWB0_LUMA_MEM_EN_NUM 7 7 MCIF_DWB0_CHROMA_MEM_EN_NUM 8 8 regMMHUBBUB_CLOCK_CNTL 0 0x341 7 0 2 MMHUBBUB_TEST_CLK_SEL 0 4 DISPCLK_R_MMHUBBUB_GATE_DIS 5 5 DISPCLK_G_VGAIF_GATE_DIS 6 6 SOCCLK_G_VGAIF_GATE_DIS 7 7 DISPCLK_G_VGA_GATE_DIS 8 8 DISPCLK_G_WBIF0_GATE_DIS 9 9 SOCCLK_G_WBIF0_GATE_DIS 10 10 regMMHUBBUB_SOFT_RESET 0 0x342 4 0 2 VGA_SOFT_RESET 0 0 VGAIF_SOFT_RESET 1 1 WBIF0_SOFT_RESET 2 2 DMUIF_SOFT_RESET 8 8 regDMU_IF_ERR_STATUS 0 0x346 2 0 2 DMU_RD_OUTSTANDING_ERR 0 0 DMU_RD_OUTSTANDING_ERR_CLR 4 4 regMMHUBBUB_CLIENT_UNIT_ID 0 0x347 2 0 2 VGA_UNIT_ID 0 5 WBIF0_UNIT_ID 8 13 regMMHUBBUB_WARMUP_VMID_CONTROL 0 0x349 1 0 2 MMHUBBUB_WARMUP_P_VMID 0 3 regAZALIA_CONTROLLER_CLOCK_GATING 0 0x3c2 2 0 2 ENABLE_CLOCK_GATING 0 0 CLOCK_ON_STATE 4 4 regAZALIA_AUDIO_DTO 0 0x3c3 2 0 2 AZALIA_AUDIO_DTO_PHASE 0 15 AZALIA_AUDIO_DTO_MODULE 16 31 regAZALIA_AUDIO_DTO_CONTROL 0 0x3c4 1 0 2 AZALIA_AUDIO_FORCE_DTO 8 9 regAZALIA_SOCCLK_CONTROL 0 0x3c5 2 0 2 DRM_SOCCLK_DEEP_SLEEP_EXIT_EN 0 0 AUDIO_STREAM_SOCCLK_DEEP_SLEEP_EXIT_EN 1 1 regAZALIA_UNDERFLOW_FILLER_SAMPLE 0 0x3c6 1 0 2 AZALIA_UNDERFLOW_FILLER_SAMPLE 0 31 regAZALIA_DATA_DMA_CONTROL 0 0x3c7 6 0 2 DATA_DMA_NON_SNOOP 0 1 INPUT_DATA_DMA_NON_SNOOP 2 3 DATA_DMA_ISOCHRONOUS 4 5 INPUT_DATA_DMA_ISOCHRONOUS 6 7 AZALIA_IOC_GENERATION_METHOD 16 16 AZALIA_UNDERFLOW_CONTROL 17 17 regAZALIA_BDL_DMA_CONTROL 0 0x3c8 4 0 2 BDL_DMA_NON_SNOOP 0 1 INPUT_BDL_DMA_NON_SNOOP 2 3 BDL_DMA_ISOCHRONOUS 4 5 INPUT_BDL_DMA_ISOCHRONOUS 6 7 regAZALIA_RIRB_AND_DP_CONTROL 0 0x3c9 3 0 2 RIRB_NON_SNOOP 0 0 DP_DMA_NON_SNOOP 4 4 DP_UPDATE_FREQ_DIVIDER 5 8 regAZALIA_CORB_DMA_CONTROL 0 0x3ca 2 0 2 CORB_DMA_NON_SNOOP 0 0 CORB_DMA_ISOCHRONOUS 4 4 regAZALIA_APPLICATION_POSITION_IN_CYCLIC_BUFFER 0 0x3d1 1 0 2 APPLICATION_POSITION_IN_CYCLIC_BUFFER 0 31 regAZALIA_CYCLIC_BUFFER_SYNC 0 0x3d2 1 0 2 CYCLIC_BUFFER_SYNC_ENABLE 0 0 regAZALIA_OUTPUT_STREAM_ARBITER_CONTROL 0 0x3d5 3 0 2 LATENCY_HIDING_LEVEL 0 7 SYS_MEM_ACTIVE_ENABLE 8 8 INPUT_LATENCY_HIDING_LEVEL 16 23 regAZALIA_INPUT_CRC0_CONTROL0 0 0x3d9 3 0 2 INPUT_CRC_EN 0 0 INPUT_CRC_BLOCK_MODE 4 4 INPUT_CRC_INSTANCE_SEL 8 10 regAZALIA_INPUT_CRC0_CONTROL1 0 0x3da 1 0 2 INPUT_CRC_BLOCK_SIZE 0 31 regAZALIA_INPUT_CRC0_CONTROL2 0 0x3db 1 0 2 INPUT_CRC_BLOCK_ITERATION 0 15 regAZALIA_INPUT_CRC0_CONTROL3 0 0x3dc 3 0 2 INPUT_CRC_COMPLETE 0 0 INPUT_CRC_BLOCK_COMPLETE_PHASE 4 4 INPUT_CRC_CHANNEL_RESULT_SEL 8 10 regAZALIA_INPUT_CRC0_RESULT 0 0x3dd 1 0 2 INPUT_CRC_RESULT 0 31 regAZALIA_INPUT_CRC1_CONTROL0 0 0x3de 3 0 2 INPUT_CRC_EN 0 0 INPUT_CRC_BLOCK_MODE 4 4 INPUT_CRC_INSTANCE_SEL 8 10 regAZALIA_INPUT_CRC1_CONTROL1 0 0x3df 1 0 2 INPUT_CRC_BLOCK_SIZE 0 31 regAZALIA_INPUT_CRC1_CONTROL2 0 0x3e0 1 0 2 INPUT_CRC_BLOCK_ITERATION 0 15 regAZALIA_INPUT_CRC1_CONTROL3 0 0x3e1 3 0 2 INPUT_CRC_COMPLETE 0 0 INPUT_CRC_BLOCK_COMPLETE_PHASE 4 4 INPUT_CRC_CHANNEL_RESULT_SEL 8 10 regAZALIA_INPUT_CRC1_RESULT 0 0x3e2 1 0 2 INPUT_CRC_RESULT 0 31 regAZALIA_CRC0_CONTROL0 0 0x3e3 4 0 2 CRC_EN 0 0 CRC_BLOCK_MODE 4 4 CRC_INSTANCE_SEL 8 10 CRC_SOURCE_SEL 12 12 regAZALIA_CRC0_CONTROL1 0 0x3e4 1 0 2 CRC_BLOCK_SIZE 0 31 regAZALIA_CRC0_CONTROL2 0 0x3e5 1 0 2 CRC_BLOCK_ITERATION 0 15 regAZALIA_CRC0_CONTROL3 0 0x3e6 3 0 2 CRC_COMPLETE 0 0 CRC_BLOCK_COMPLETE_PHASE 4 4 CRC_CHANNEL_RESULT_SEL 8 10 regAZALIA_CRC0_RESULT 0 0x3e7 1 0 2 CRC_RESULT 0 31 regAZALIA_CRC1_CONTROL0 0 0x3e8 4 0 2 CRC_EN 0 0 CRC_BLOCK_MODE 4 4 CRC_INSTANCE_SEL 8 10 CRC_SOURCE_SEL 12 12 regAZALIA_CRC1_CONTROL1 0 0x3e9 1 0 2 CRC_BLOCK_SIZE 0 31 regAZALIA_CRC1_CONTROL2 0 0x3ea 1 0 2 CRC_BLOCK_ITERATION 0 15 regAZALIA_CRC1_CONTROL3 0 0x3eb 3 0 2 CRC_COMPLETE 0 0 CRC_BLOCK_COMPLETE_PHASE 4 4 CRC_CHANNEL_RESULT_SEL 8 10 regAZALIA_CRC1_RESULT 0 0x3ec 1 0 2 CRC_RESULT 0 31 regAZALIA_MEM_PWR_CTRL 0 0x3ee 15 0 2 AZ_MEM_PWR_FORCE 0 1 AZ_MEM_PWR_DIS 2 2 AZ_INPUT_STREAM0_MEM_PWR_FORCE 3 4 AZ_INPUT_STREAM0_MEM_PWR_DIS 5 5 AZ_INPUT_STREAM1_MEM_PWR_FORCE 6 7 AZ_INPUT_STREAM1_MEM_PWR_DIS 8 8 AZ_INPUT_STREAM2_MEM_PWR_FORCE 9 10 AZ_INPUT_STREAM2_MEM_PWR_DIS 11 11 AZ_INPUT_STREAM3_MEM_PWR_FORCE 12 13 AZ_INPUT_STREAM3_MEM_PWR_DIS 14 14 AZ_INPUT_STREAM4_MEM_PWR_FORCE 15 16 AZ_INPUT_STREAM4_MEM_PWR_DIS 17 17 AZ_INPUT_STREAM5_MEM_PWR_FORCE 18 19 AZ_INPUT_STREAM5_MEM_PWR_DIS 20 20 AZ_MEM_PWR_MODE_SEL 28 29 regAZALIA_MEM_PWR_STATUS 0 0x3ef 7 0 2 AZ_MEM_PWR_STATE 0 1 AZ_INPUT_STREAM0_MEM_PWR_STATE 2 3 AZ_INPUT_STREAM1_MEM_PWR_STATE 4 5 AZ_INPUT_STREAM2_MEM_PWR_STATE 6 7 AZ_INPUT_STREAM3_MEM_PWR_STATE 8 9 AZ_INPUT_STREAM4_MEM_PWR_STATE 10 11 AZ_INPUT_STREAM5_MEM_PWR_STATE 12 13 regAZALIA_F0_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID 0 0x406 1 0 2 AZALIA_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID 0 31 regAZALIA_F0_CODEC_ROOT_PARAMETER_REVISION_ID 0 0x407 1 0 2 AZALIA_CODEC_ROOT_PARAMETER_REVISION_ID 0 31 regAZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL 0 0x408 2 0 2 HBR_CHANNEL_COUNT 0 2 COMPRESSED_CHANNEL_COUNT 4 6 regAZALIA_F0_CODEC_RESYNC_FIFO_CONTROL 0 0x409 1 0 2 RESYNC_FIFO_STARTUP_KEEPOUT_WINDOW 0 5 regAZALIA_F0_CODEC_FUNCTION_PARAMETER_GROUP_TYPE 0 0x40a 1 0 2 AZALIA_CODEC_FUNCTION_PARAMETER_GROUP_TYPE 0 31 regAZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES 0 0x40b 2 0 2 AUDIO_RATE_CAPABILITIES 0 11 AUDIO_BIT_CAPABILITIES 16 20 regAZALIA_F0_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS 0 0x40c 1 0 2 AZALIA_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS 0 31 regAZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES 0 0x40d 3 0 2 AZALIA_CODEC_FUNCTION_PARAMETER_POWER_STATES 0 29 CLKSTOP 30 30 EPSS 31 31 regAZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE 0 0x40e 4 0 2 POWER_STATE_SET 0 3 POWER_STATE_ACT 4 7 CLKSTOPOK 9 9 POWER_STATE_SETTINGS_RESET 10 10 regAZALIA_F0_CODEC_FUNCTION_CONTROL_RESET 0 0x40f 1 0 2 CODEC_RESET 0 0 regAZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID 0 0x410 4 0 2 SUBSYSTEM_ID_BYTE0 0 7 SUBSYSTEM_ID_BYTE1 8 15 SUBSYSTEM_ID_BYTE2 16 23 SUBSYSTEM_ID_BYTE3 24 31 regAZALIA_F0_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION 0 0x411 1 0 2 CONVERTER_SYNCHRONIZATION 0 7 regCC_RCU_DC_AUDIO_PORT_CONNECTIVITY 0 0x412 2 0 2 PORT_CONNECTIVITY 0 2 PORT_CONNECTIVITY_OVERRIDE_ENABLE 4 4 regCC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY 0 0x413 2 0 2 INPUT_PORT_CONNECTIVITY 0 2 INPUT_PORT_CONNECTIVITY_OVERRIDE_ENABLE 4 4 regAZALIA_F0_GTC_GROUP_OFFSET0 0 0x415 1 0 2 GTC_GROUP_OFFSET0 0 31 regAZALIA_F0_GTC_GROUP_OFFSET1 0 0x416 1 0 2 GTC_GROUP_OFFSET1 0 31 regAZALIA_F0_GTC_GROUP_OFFSET2 0 0x417 1 0 2 GTC_GROUP_OFFSET2 0 31 regAZALIA_F0_GTC_GROUP_OFFSET3 0 0x418 1 0 2 GTC_GROUP_OFFSET3 0 31 regAZALIA_F0_GTC_GROUP_OFFSET4 0 0x419 1 0 2 GTC_GROUP_OFFSET4 0 31 regAZALIA_F0_GTC_GROUP_OFFSET5 0 0x41a 1 0 2 GTC_GROUP_OFFSET5 0 31 regAZALIA_F0_GTC_GROUP_OFFSET6 0 0x41b 1 0 2 GTC_GROUP_OFFSET6 0 31 regREG_DC_AUDIO_PORT_CONNECTIVITY 0 0x41c 2 0 2 REG_PORT_CONNECTIVITY 0 2 REG_PORT_CONNECTIVITY_OVERRIDE_ENABLE 4 4 regREG_DC_AUDIO_INPUT_PORT_CONNECTIVITY 0 0x41d 2 0 2 REG_INPUT_PORT_CONNECTIVITY 0 2 REG_INPUT_PORT_CONNECTIVITY_OVERRIDE_ENABLE 4 4 regAZ_CLOCK_CNTL 0 0x372 4 0 2 SCLK_G_STREAM_AZ_GATE_DIS 0 0 SCLK_R_AZ_GATE_DIS 8 8 SCLK_G_CNTL_AZ_GATE_DIS 16 16 DCIPG_TEST_CLK_SEL 24 28 regDC_PERFMON5_PERFCOUNTER_CNTL 0 0x37a 11 0 2 PERFCOUNTER_EVENT_SEL 0 8 PERFCOUNTER_CVALUE_SEL 9 11 PERFCOUNTER_INC_MODE 12 14 PERFCOUNTER_HW_CNTL_SEL 15 15 PERFCOUNTER_RUNEN_MODE 16 16 PERFCOUNTER_CNTOFF_START_DIS 22 22 PERFCOUNTER_RESTART_EN 23 23 PERFCOUNTER_INT_EN 24 24 PERFCOUNTER_OFF_MASK 25 25 PERFCOUNTER_ACTIVE 26 26 PERFCOUNTER_CNTL_SEL 29 31 regDC_PERFMON5_PERFCOUNTER_CNTL2 0 0x37b 5 0 2 PERFCOUNTER_COUNTED_VALUE_TYPE 0 1 PERFCOUNTER_HW_STOP1_SEL 2 2 PERFCOUNTER_HW_STOP2_SEL 3 3 PERFCOUNTER_CNTOFF_SEL 8 13 PERFCOUNTER_CNTL2_SEL 29 31 regDC_PERFMON5_PERFCOUNTER_STATE 0 0x37c 16 0 2 PERFCOUNTER_CNT0_STATE 0 1 PERFCOUNTER_STATE_SEL0 2 2 PERFCOUNTER_CNT1_STATE 4 5 PERFCOUNTER_STATE_SEL1 6 6 PERFCOUNTER_CNT2_STATE 8 9 PERFCOUNTER_STATE_SEL2 10 10 PERFCOUNTER_CNT3_STATE 12 13 PERFCOUNTER_STATE_SEL3 14 14 PERFCOUNTER_CNT4_STATE 16 17 PERFCOUNTER_STATE_SEL4 18 18 PERFCOUNTER_CNT5_STATE 20 21 PERFCOUNTER_STATE_SEL5 22 22 PERFCOUNTER_CNT6_STATE 24 25 PERFCOUNTER_STATE_SEL6 26 26 PERFCOUNTER_CNT7_STATE 28 29 PERFCOUNTER_STATE_SEL7 30 30 regDC_PERFMON5_PERFMON_CNTL 0 0x37d 6 0 2 PERFMON_STATE 0 1 PERFMON_RPT_COUNT 8 27 PERFMON_CNTOFF_AND_OR 28 28 PERFMON_CNTOFF_INT_EN 29 29 PERFMON_CNTOFF_INT_STATUS 30 30 PERFMON_CNTOFF_INT_ACK 31 31 regDC_PERFMON5_PERFMON_CNTL2 0 0x37e 4 0 2 PERFMON_CNTOFF_INT_TYPE 0 0 PERFMON_CLK_ENABLE 1 1 PERFMON_RUN_ENABLE_START_SEL 2 9 PERFMON_RUN_ENABLE_STOP_SEL 10 17 regDC_PERFMON5_PERFMON_CVALUE_INT_MISC 0 0x37f 17 0 2 PERFCOUNTER_INT0_STATUS 0 0 PERFCOUNTER_INT1_STATUS 1 1 PERFCOUNTER_INT2_STATUS 2 2 PERFCOUNTER_INT3_STATUS 3 3 PERFCOUNTER_INT4_STATUS 4 4 PERFCOUNTER_INT5_STATUS 5 5 PERFCOUNTER_INT6_STATUS 6 6 PERFCOUNTER_INT7_STATUS 7 7 PERFCOUNTER_INT0_ACK 8 8 PERFCOUNTER_INT1_ACK 9 9 PERFCOUNTER_INT2_ACK 10 10 PERFCOUNTER_INT3_ACK 11 11 PERFCOUNTER_INT4_ACK 12 12 PERFCOUNTER_INT5_ACK 13 13 PERFCOUNTER_INT6_ACK 14 14 PERFCOUNTER_INT7_ACK 15 15 PERFMON_CVALUE_HI 16 31 regDC_PERFMON5_PERFMON_CVALUE_LOW 0 0x380 1 0 2 PERFMON_CVALUE_LOW 0 31 regDC_PERFMON5_PERFMON_HI 0 0x381 2 0 2 PERFMON_HI 0 15 PERFMON_READ_SEL 29 31 regDC_PERFMON5_PERFMON_LOW 0 0x382 1 0 2 PERFMON_LOW 0 31 regAZF0STREAM0_AZALIA_STREAM_INDEX 0 0x35e 2 0 2 AZALIA_STREAM_REG_INDEX 0 7 AZALIA_STREAM_REG_WRITE_EN 8 8 regAZF0STREAM0_AZALIA_STREAM_DATA 0 0x35f 1 0 2 AZALIA_STREAM_REG_DATA 0 31 regAZF0STREAM1_AZALIA_STREAM_INDEX 0 0x360 2 0 2 AZALIA_STREAM_REG_INDEX 0 7 AZALIA_STREAM_REG_WRITE_EN 8 8 regAZF0STREAM1_AZALIA_STREAM_DATA 0 0x361 1 0 2 AZALIA_STREAM_REG_DATA 0 31 regAZF0STREAM2_AZALIA_STREAM_INDEX 0 0x362 2 0 2 AZALIA_STREAM_REG_INDEX 0 7 AZALIA_STREAM_REG_WRITE_EN 8 8 regAZF0STREAM2_AZALIA_STREAM_DATA 0 0x363 1 0 2 AZALIA_STREAM_REG_DATA 0 31 regAZF0STREAM3_AZALIA_STREAM_INDEX 0 0x364 2 0 2 AZALIA_STREAM_REG_INDEX 0 7 AZALIA_STREAM_REG_WRITE_EN 8 8 regAZF0STREAM3_AZALIA_STREAM_DATA 0 0x365 1 0 2 AZALIA_STREAM_REG_DATA 0 31 regAZF0STREAM4_AZALIA_STREAM_INDEX 0 0x366 2 0 2 AZALIA_STREAM_REG_INDEX 0 7 AZALIA_STREAM_REG_WRITE_EN 8 8 regAZF0STREAM4_AZALIA_STREAM_DATA 0 0x367 1 0 2 AZALIA_STREAM_REG_DATA 0 31 regAZF0STREAM5_AZALIA_STREAM_INDEX 0 0x368 2 0 2 AZALIA_STREAM_REG_INDEX 0 7 AZALIA_STREAM_REG_WRITE_EN 8 8 regAZF0STREAM5_AZALIA_STREAM_DATA 0 0x369 1 0 2 AZALIA_STREAM_REG_DATA 0 31 regAZF0STREAM6_AZALIA_STREAM_INDEX 0 0x36a 2 0 2 AZALIA_STREAM_REG_INDEX 0 7 AZALIA_STREAM_REG_WRITE_EN 8 8 regAZF0STREAM6_AZALIA_STREAM_DATA 0 0x36b 1 0 2 AZALIA_STREAM_REG_DATA 0 31 regAZF0STREAM7_AZALIA_STREAM_INDEX 0 0x36c 2 0 2 AZALIA_STREAM_REG_INDEX 0 7 AZALIA_STREAM_REG_WRITE_EN 8 8 regAZF0STREAM7_AZALIA_STREAM_DATA 0 0x36d 1 0 2 AZALIA_STREAM_REG_DATA 0 31 regAZF0STREAM8_AZALIA_STREAM_INDEX 0 0x426 2 0 2 AZALIA_STREAM_REG_INDEX 0 7 AZALIA_STREAM_REG_WRITE_EN 8 8 regAZF0STREAM8_AZALIA_STREAM_DATA 0 0x427 1 0 2 AZALIA_STREAM_REG_DATA 0 31 regAZF0STREAM9_AZALIA_STREAM_INDEX 0 0x428 2 0 2 AZALIA_STREAM_REG_INDEX 0 7 AZALIA_STREAM_REG_WRITE_EN 8 8 regAZF0STREAM9_AZALIA_STREAM_DATA 0 0x429 1 0 2 AZALIA_STREAM_REG_DATA 0 31 regAZF0STREAM10_AZALIA_STREAM_INDEX 0 0x42a 2 0 2 AZALIA_STREAM_REG_INDEX 0 7 AZALIA_STREAM_REG_WRITE_EN 8 8 regAZF0STREAM10_AZALIA_STREAM_DATA 0 0x42b 1 0 2 AZALIA_STREAM_REG_DATA 0 31 regAZF0STREAM11_AZALIA_STREAM_INDEX 0 0x42c 2 0 2 AZALIA_STREAM_REG_INDEX 0 7 AZALIA_STREAM_REG_WRITE_EN 8 8 regAZF0STREAM11_AZALIA_STREAM_DATA 0 0x42d 1 0 2 AZALIA_STREAM_REG_DATA 0 31 regAZF0STREAM12_AZALIA_STREAM_INDEX 0 0x42e 2 0 2 AZALIA_STREAM_REG_INDEX 0 7 AZALIA_STREAM_REG_WRITE_EN 8 8 regAZF0STREAM12_AZALIA_STREAM_DATA 0 0x42f 1 0 2 AZALIA_STREAM_REG_DATA 0 31 regAZF0STREAM13_AZALIA_STREAM_INDEX 0 0x430 2 0 2 AZALIA_STREAM_REG_INDEX 0 7 AZALIA_STREAM_REG_WRITE_EN 8 8 regAZF0STREAM13_AZALIA_STREAM_DATA 0 0x431 1 0 2 AZALIA_STREAM_REG_DATA 0 31 regAZF0STREAM14_AZALIA_STREAM_INDEX 0 0x432 2 0 2 AZALIA_STREAM_REG_INDEX 0 7 AZALIA_STREAM_REG_WRITE_EN 8 8 regAZF0STREAM14_AZALIA_STREAM_DATA 0 0x433 1 0 2 AZALIA_STREAM_REG_DATA 0 31 regAZF0STREAM15_AZALIA_STREAM_INDEX 0 0x434 2 0 2 AZALIA_STREAM_REG_INDEX 0 7 AZALIA_STREAM_REG_WRITE_EN 8 8 regAZF0STREAM15_AZALIA_STREAM_DATA 0 0x435 1 0 2 AZALIA_STREAM_REG_DATA 0 31 regAZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX 0 0x386 1 0 2 AZALIA_ENDPOINT_REG_INDEX 0 13 regAZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA 0 0x387 1 0 2 AZALIA_ENDPOINT_REG_DATA 0 31 regAZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_INDEX 0 0x38c 1 0 2 AZALIA_ENDPOINT_REG_INDEX 0 13 regAZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_DATA 0 0x38d 1 0 2 AZALIA_ENDPOINT_REG_DATA 0 31 regAZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_INDEX 0 0x392 1 0 2 AZALIA_ENDPOINT_REG_INDEX 0 13 regAZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_DATA 0 0x393 1 0 2 AZALIA_ENDPOINT_REG_DATA 0 31 regAZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_INDEX 0 0x398 1 0 2 AZALIA_ENDPOINT_REG_INDEX 0 13 regAZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_DATA 0 0x399 1 0 2 AZALIA_ENDPOINT_REG_DATA 0 31 regAZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_INDEX 0 0x39e 1 0 2 AZALIA_ENDPOINT_REG_INDEX 0 13 regAZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_DATA 0 0x39f 1 0 2 AZALIA_ENDPOINT_REG_DATA 0 31 regAZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_INDEX 0 0x3a4 1 0 2 AZALIA_ENDPOINT_REG_INDEX 0 13 regAZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_DATA 0 0x3a5 1 0 2 AZALIA_ENDPOINT_REG_DATA 0 31 regAZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_INDEX 0 0x3aa 1 0 2 AZALIA_ENDPOINT_REG_INDEX 0 13 regAZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_DATA 0 0x3ab 1 0 2 AZALIA_ENDPOINT_REG_DATA 0 31 regAZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_INDEX 0 0x3b0 1 0 2 AZALIA_ENDPOINT_REG_INDEX 0 13 regAZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_DATA 0 0x3b1 1 0 2 AZALIA_ENDPOINT_REG_DATA 0 31 regAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0 0x43a 1 0 2 AZALIA_INPUT_ENDPOINT_REG_INDEX 0 13 regAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0 0x43b 1 0 2 AZALIA_INPUT_ENDPOINT_REG_DATA 0 31 regAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0 0x43e 1 0 2 AZALIA_INPUT_ENDPOINT_REG_INDEX 0 13 regAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0 0x43f 1 0 2 AZALIA_INPUT_ENDPOINT_REG_DATA 0 31 regAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0 0x442 1 0 2 AZALIA_INPUT_ENDPOINT_REG_INDEX 0 13 regAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0 0x443 1 0 2 AZALIA_INPUT_ENDPOINT_REG_DATA 0 31 regAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0 0x446 1 0 2 AZALIA_INPUT_ENDPOINT_REG_INDEX 0 13 regAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0 0x447 1 0 2 AZALIA_INPUT_ENDPOINT_REG_DATA 0 31 regAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0 0x44a 1 0 2 AZALIA_INPUT_ENDPOINT_REG_INDEX 0 13 regAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0 0x44b 1 0 2 AZALIA_INPUT_ENDPOINT_REG_DATA 0 31 regAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0 0x44e 1 0 2 AZALIA_INPUT_ENDPOINT_REG_INDEX 0 13 regAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0 0x44f 1 0 2 AZALIA_INPUT_ENDPOINT_REG_DATA 0 31 regAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0 0x452 1 0 2 AZALIA_INPUT_ENDPOINT_REG_INDEX 0 13 regAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0 0x453 1 0 2 AZALIA_INPUT_ENDPOINT_REG_DATA 0 31 regAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0 0x456 1 0 2 AZALIA_INPUT_ENDPOINT_REG_INDEX 0 13 regAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0 0x457 1 0 2 AZALIA_INPUT_ENDPOINT_REG_DATA 0 31 regDCHUBBUB_ARB_DF_REQ_OUTSTAND 0 0x4f9 3 0 2 DCHUBBUB_ARB_MAX_REQ_OUTSTAND 0 8 DCHUBBUB_ARB_MIN_REQ_OUTSTAND 12 20 DCHUBBUB_ARB_MIN_REQ_OUTSTAND_COMMIT_THRESHOLD 23 31 regDCHUBBUB_ARB_SAT_LEVEL 0 0x4fa 1 0 2 DCHUBBUB_ARB_SAT_LEVEL 0 31 regDCHUBBUB_ARB_QOS_FORCE 0 0x4fb 3 0 2 DCHUBBUB_ARB_QOS_FORCE_VALUE 0 3 DCHUBBUB_ARB_QOS_FORCE_ENABLE 8 8 DCHUBBUB_ARB_HOSTVM_STALL_QOS 12 15 regDCHUBBUB_ARB_DRAM_STATE_CNTL 0 0x4fc 7 0 2 DCHUBBUB_ARB_ALLOW_SELF_REFRESH_FORCE_VALUE 0 0 DCHUBBUB_ARB_ALLOW_SELF_REFRESH_FORCE_ENABLE 1 1 DCHUBBUB_ARB_ALLOW_PSTATE_CHANGE_FORCE_VALUE 4 4 DCHUBBUB_ARB_ALLOW_PSTATE_CHANGE_FORCE_ENABLE 5 5 DCHUBBUB_ARB_DO_NOT_FORCE_URGENCY_AND_SELF_REFRESH_DURING_DRAM_CLOCK_NBPSTATE_CHANGE_REQUEST 8 8 DCHUBBUB_ARB_FORCE_URGENCY_DURING_DRAM_CLOCK_NBPSTATE_CHANGE_REQUEST_REGARDLESS_OF_ALLOW_SIGNAL 9 9 DCHUBBUB_ARB_CSTATE_MAX_CAP_MODE 12 12 regDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A 0 0x4fd 1 0 2 DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A 0 13 regDCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_A 0 0x4fe 1 0 2 DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_A 0 13 regDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A 0 0x4ff 1 0 2 DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A 0 15 regDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_A 0 0x500 1 0 2 DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_A 0 19 regDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A 0 0x501 1 0 2 DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A 0 15 regDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_A 0 0x502 1 0 2 DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_A 0 19 regDCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A 0 0x503 1 0 2 DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A 0 15 regDCHUBBUB_ARB_FRAC_URG_BW_NOM_A 0 0x504 1 0 2 DCHUBBUB_ARB_FRAC_URG_BW_NOM_A 0 9 regDCHUBBUB_ARB_FRAC_URG_BW_FLIP_A 0 0x505 1 0 2 DCHUBBUB_ARB_FRAC_URG_BW_FLIP_A 0 9 regDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B 0 0x506 1 0 2 DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B 0 13 regDCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_B 0 0x507 1 0 2 DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_B 0 13 regDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B 0 0x508 1 0 2 DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B 0 15 regDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_B 0 0x509 1 0 2 DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_B 0 19 regDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B 0 0x50a 1 0 2 DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B 0 15 regDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_B 0 0x50b 1 0 2 DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_B 0 19 regDCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B 0 0x50c 1 0 2 DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B 0 15 regDCHUBBUB_ARB_FRAC_URG_BW_NOM_B 0 0x50d 1 0 2 DCHUBBUB_ARB_FRAC_URG_BW_NOM_B 0 9 regDCHUBBUB_ARB_FRAC_URG_BW_FLIP_B 0 0x50e 1 0 2 DCHUBBUB_ARB_FRAC_URG_BW_FLIP_B 0 9 regDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C 0 0x50f 1 0 2 DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C 0 13 regDCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_C 0 0x510 1 0 2 DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_C 0 13 regDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C 0 0x511 1 0 2 DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C 0 15 regDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_C 0 0x512 1 0 2 DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_C 0 19 regDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C 0 0x513 1 0 2 DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C 0 15 regDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_C 0 0x514 1 0 2 DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_C 0 19 regDCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_C 0 0x515 1 0 2 DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_C 0 15 regDCHUBBUB_ARB_FRAC_URG_BW_NOM_C 0 0x516 1 0 2 DCHUBBUB_ARB_FRAC_URG_BW_NOM_C 0 9 regDCHUBBUB_ARB_FRAC_URG_BW_FLIP_C 0 0x517 1 0 2 DCHUBBUB_ARB_FRAC_URG_BW_FLIP_C 0 9 regDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D 0 0x518 1 0 2 DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D 0 13 regDCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_D 0 0x519 1 0 2 DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_D 0 13 regDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D 0 0x51a 1 0 2 DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D 0 15 regDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_D 0 0x51b 1 0 2 DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_D 0 19 regDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D 0 0x51c 1 0 2 DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D 0 15 regDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_D 0 0x51d 1 0 2 DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_D 0 19 regDCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D 0 0x51e 1 0 2 DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D 0 15 regDCHUBBUB_ARB_FRAC_URG_BW_NOM_D 0 0x51f 1 0 2 DCHUBBUB_ARB_FRAC_URG_BW_NOM_D 0 9 regDCHUBBUB_ARB_FRAC_URG_BW_FLIP_D 0 0x520 1 0 2 DCHUBBUB_ARB_FRAC_URG_BW_FLIP_D 0 9 regDCHUBBUB_ARB_HOSTVM_CNTL 0 0x521 11 0 2 DISABLE_HOSTVM_FORCE_CSTATE 0 0 DISABLE_HOSTVM_FORCE_ALLOW_PSTATE 1 1 PRQ_SLACK_MASK 2 2 PRQ_SPACE_OK_STATUS 3 3 PRQ_GID_FREE_STATUS 4 4 DCHVM_RET_FIFO_FREE_STATUS 5 5 NON_PRQ_CLIENT_WINNER_STATUS 6 6 HOSTVM_MAX_ALLOCATED_GROUPS 8 13 HOSTVM_MAX_RD_FIFO_ENTRIES 16 23 HOSTVM_QOS 24 27 DCHUBBUB_ARB_MAX_QOS_COMMIT_THRESHOLD 28 31 regDCHUBBUB_ARB_WATERMARK_CHANGE_CNTL 0 0x522 4 0 2 DCHUBBUB_ARB_WATERMARK_CHANGE_SELECT 0 1 DCHUBBUB_ARB_WATERMARK_CHANGE_DONE_INTERRUPT_DISABLE 4 4 DCHUBBUB_ARB_WATERMARK_CHANGE_REQUEST 8 8 DCHUBBUB_ARB_WATERMARK_CHANGE_SELECT_Z8 16 16 regDCHUBBUB_ARB_TIMEOUT_ENABLE 0 0x523 1 0 2 DCHUBBUB_ARB_TIMEOUT_ENABLE 0 0 regDCHUBBUB_GLOBAL_TIMER_CNTL 0 0x524 3 0 2 DCHUBBUB_GLOBAL_TIMER_REFDIV 0 3 DCHUBBUB_GLOBAL_TIMER_ENABLE 12 12 DCHUBBUB_GLOBAL_TIMER_INIT 16 31 regSURFACE_CHECK0_ADDRESS_LSB 0 0x525 1 0 2 SURFACE_CHECK0_ADDRESS_LSB 0 31 regSURFACE_CHECK0_ADDRESS_MSB 0 0x526 2 0 2 SURFACE_CHECK0_ADDRESS_MSB 0 15 CHECKER0_SURFACE_INUSE 31 31 regSURFACE_CHECK1_ADDRESS_LSB 0 0x527 1 0 2 SURFACE_CHECK1_ADDRESS_LSB 0 31 regSURFACE_CHECK1_ADDRESS_MSB 0 0x528 2 0 2 SURFACE_CHECK1_ADDRESS_MSB 0 15 CHECKER1_SURFACE_INUSE 31 31 regSURFACE_CHECK2_ADDRESS_LSB 0 0x529 1 0 2 SURFACE_CHECK2_ADDRESS_LSB 0 31 regSURFACE_CHECK2_ADDRESS_MSB 0 0x52a 2 0 2 SURFACE_CHECK2_ADDRESS_MSB 0 15 CHECKER2_SURFACE_INUSE 31 31 regSURFACE_CHECK3_ADDRESS_LSB 0 0x52b 1 0 2 SURFACE_CHECK3_ADDRESS_LSB 0 31 regSURFACE_CHECK3_ADDRESS_MSB 0 0x52c 2 0 2 SURFACE_CHECK3_ADDRESS_MSB 0 15 CHECKER3_SURFACE_INUSE 31 31 regVTG0_CONTROL 0 0x52d 3 0 2 VTG0_FP2 0 14 VTG0_VCOUNT_INIT 16 30 VTG0_ENABLE 31 31 regVTG1_CONTROL 0 0x52e 3 0 2 VTG1_FP2 0 14 VTG1_VCOUNT_INIT 16 30 VTG1_ENABLE 31 31 regVTG2_CONTROL 0 0x52f 3 0 2 VTG2_FP2 0 14 VTG2_VCOUNT_INIT 16 30 VTG2_ENABLE 31 31 regVTG3_CONTROL 0 0x530 3 0 2 VTG3_FP2 0 14 VTG3_VCOUNT_INIT 16 30 VTG3_ENABLE 31 31 regDCHUBBUB_SOFT_RESET 0 0x531 3 0 2 DCHUBBUB_GLOBAL_SOFT_RESET 0 0 ALLOW_CSTATE_SOFT_RESET 1 1 GLBFLIP_SOFT_RESET 4 4 regDCHUBBUB_CLOCK_CNTL 0 0x532 3 0 2 DCHUBBUB_TEST_CLK_SEL 0 4 DISPCLK_R_DCHUBBUB_GATE_DIS 5 5 DCFCLK_R_DCHUBBUB_GATE_DIS 6 6 regDCFCLK_CNTL 0 0x533 3 0 2 DCFCLK_TURN_ON_DELAY 0 3 DCFCLK_TURN_OFF_DELAY 4 11 DCFCLK_GATE_DIS 31 31 regDCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL 0 0x534 7 0 2 DCHUBBUB_LATENCY_CNT_EN 0 0 DCHUBBUB_LATENCY_EVENT_SHORT_PULSE_FILTER_EN 1 1 DCHUBBUB_DF_REQ_CMD_LATENCY_SEL 2 2 ARB_LATENCY_PIPE_SEL 3 6 ARB_LATENCY_REQ_TYPE_SEL 7 9 DF_LATENCY_URGENT_ONLY 10 10 ROB_FIFO_LEVEL 11 21 regDCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL2 0 0x535 7 0 2 DCHUBBUB_LATENCY_FRAME_WIN_EN 0 0 DCHUBBUB_LATENCY_FRAME_WIN_SRC_SEL 1 3 DCHUBBUB_LATENCY_FRAME_WIN_DUR 4 11 LATENCY_SOURCE_SEL 12 14 LATENCY_DEBUG_SEL 15 15 ROB_MAX_FIFO_LEVEL 19 29 ROB_MAX_FIFO_LEVEL_RESET 31 31 regDCHUBBUB_VLINE_SNAPSHOT 0 0x536 1 0 2 DCHUBBUB_VLINE_SNAPSHOT 0 0 regDCHUBBUB_CTRL_STATUS 0 0x537 5 0 2 URGENT_ZERO_SIZE_REQ_EN 0 0 ROB_OVERFLOW_STATUS 2 2 ROB_OVERFLOW_CLEAR 3 3 DCHUBBUB_HW_DEBUG 4 30 CSTATE_SWATH_CHK_GOOD_MODE 31 31 regDCHUBBUB_TIMEOUT_DETECTION_CTRL1 0 0x53d 2 0 2 DCHUBBUB_TIMEOUT_ERROR_STATUS 0 5 DCHUBBUB_TIMEOUT_REQ_STALL_THRESHOLD 6 31 regDCHUBBUB_TIMEOUT_DETECTION_CTRL2 0 0x53e 3 0 2 DCHUBBUB_TIMEOUT_PSTATE_STALL_THRESHOLD 0 26 DCHUBBUB_TIMEOUT_DETECTION_EN 27 27 DCHUBBUB_TIMEOUT_TIMER_RESET 28 28 regFMON_CTRL 0 0x540 12 0 2 FMON_START 0 0 FMON_MODE 1 2 FMON_PSTATE_IGNORE 4 4 FMON_STATUS_IGNORE 5 5 FMON_URG_MODE_GREATER 6 6 FMON_FILTER_UID_EN 7 8 FMON_STATE 9 10 FMON_URG_FILTER 12 12 FMON_URG_THRESHOLD 13 16 FMON_FILTER_UID_1 17 21 FMON_FILTER_UID_2 22 26 FMON_SOF_SEL 27 29 regDCHUBBUB_TEST_DEBUG_INDEX 0 0x541 1 0 2 DCHUBBUB_TEST_DEBUG_INDEX 0 7 regDCHUBBUB_TEST_DEBUG_DATA 0 0x542 1 0 2 DCHUBBUB_TEST_DEBUG_DATA 0 31 regDCHUBBUB_SDPIF_CFG0 0 0x46f 11 0 2 SDPIF_NO_OUTSTANDING_REQ 0 0 SDPIF_PORT_STATUS 1 2 SDPIF_DATA_RESPONSE_STATUS 3 5 SDPIF_RESPONSE_STATUS 6 9 SDPIF_REQ_CREDIT_ERROR 10 10 SDPIF_RESPONSE_STATUS_CLEAR 11 11 SDPIF_REQ_CREDIT_ERROR_CLEAR 12 12 SDPIF_FLUSH_REQ_CREDIT_EN 13 13 SDPIF_REQ_CREDIT_EN 14 14 SDPIF_PORT_CONTROL 15 15 SDPIF_CREDIT_DISCONNECT_DELAY 25 30 regDCHUBBUB_SDPIF_CFG1 0 0x470 4 0 2 SDPIF_PRQ_ERROR_DETECT_EN 0 0 SDPIF_PRQ_ERROR_STATUS 1 1 SDPIF_PRQ_ERROR_STATUS_CLEAR 2 2 SDPIF_FORCE_SNOOP 8 8 regDCHUBBUB_SDPIF_CFG2 0 0x471 3 0 2 dGPU_ADDR_PRESENT 0 0 SDPIF_HOSTVM_SEC_LVL 8 11 SDPIF_UNIT_ID_BITMASK 16 24 regVM_REQUEST_PHYSICAL 0 0x472 2 0 2 PDE_REQUEST_PHYSICAL 0 0 PTE_REQUEST_PHYSICAL 3 3 regDCHUBBUB_FORCE_IO_STATUS_0 0 0x473 6 0 2 SDPIF_FORCE_IO_STATUS 0 0 SDPIF_FORCE_IO_STATUS_STICKY 1 1 SDPIF_FORCE_IO_STATUS_CLEAR 2 2 SDPIF_FORCE_IO_STATUS_PIPE_ID 3 6 SDPIF_FORCE_IO_STATUS_REQUEST_TYPE 7 9 SDPIF_FORCE_IO_STATUS_ADDR_LO 10 31 regDCHUBBUB_FORCE_IO_STATUS_1 0 0x474 1 0 2 SDPIF_FORCE_IO_STATUS_ADDR_HI 0 20 regDCN_VM_FB_LOCATION_BASE 0 0x475 1 0 2 FB_BASE 0 23 regDCN_VM_FB_LOCATION_TOP 0 0x476 1 0 2 FB_TOP 0 23 regDCN_VM_FB_OFFSET 0 0x477 1 0 2 FB_OFFSET 0 23 regDCN_VM_AGP_BOT 0 0x478 1 0 2 AGP_BOT 0 23 regDCN_VM_AGP_TOP 0 0x479 1 0 2 AGP_TOP 0 23 regDCN_VM_AGP_BASE 0 0x47a 1 0 2 AGP_BASE 0 23 regDCN_VM_LOCAL_HBM_ADDRESS_START 0 0x47b 1 0 2 ADDRESS_START 0 19 regDCN_VM_LOCAL_HBM_ADDRESS_END 0 0x47c 1 0 2 ADDRESS_END 0 19 regDCN_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL 0 0x47d 1 0 2 LOCK 0 0 regDCHUBBUB_SDPIF_PIPE_SEC_LVL 0 0x47e 4 0 2 SDPIF_PIPE0_SEC_LVL 0 3 SDPIF_PIPE1_SEC_LVL 4 7 SDPIF_PIPE2_SEC_LVL 8 11 SDPIF_PIPE3_SEC_LVL 12 15 regDCHUBBUB_SDPIF_PIPE_DMDATA_SEC_LVL 0 0x47f 4 0 2 SDPIF_PIPE0_DMDATA_SEC_LVL 0 3 SDPIF_PIPE1_DMDATA_SEC_LVL 4 7 SDPIF_PIPE2_DMDATA_SEC_LVL 8 11 SDPIF_PIPE3_DMDATA_SEC_LVL 12 15 regDCHUBBUB_SDPIF_MEM_PWR_CTRL 0 0x483 2 0 2 DCHUBBUB_SDPIF_MEM_PWR_FORCE 0 1 DCHUBBUB_SDPIF_MEM_PWR_DIS 2 2 regDCHUBBUB_SDPIF_MEM_PWR_STATUS 0 0x484 1 0 2 DCHUBBUB_SDPIF_MEM_PWR_STATE 0 1 regDCHUBBUB_RET_PATH_DCC_CFG 0 0x4af 1 0 2 DCC_VIDEO_FORMAT_EN 0 0 regDCHUBBUB_RET_PATH_DCC_CFG0_0 0 0x4b0 1 0 2 DCC_CFG0_CONSTANT_0 0 31 regDCHUBBUB_RET_PATH_DCC_CFG0_1 0 0x4b1 1 0 2 DCC_CFG0_CONSTANT_1 0 31 regDCHUBBUB_RET_PATH_DCC_CFG1_0 0 0x4b2 1 0 2 DCC_CFG1_CONSTANT_0 0 31 regDCHUBBUB_RET_PATH_DCC_CFG1_1 0 0x4b3 1 0 2 DCC_CFG1_CONSTANT_1 0 31 regDCHUBBUB_RET_PATH_DCC_CFG2_0 0 0x4b4 1 0 2 DCC_CFG2_CONSTANT_0 0 31 regDCHUBBUB_RET_PATH_DCC_CFG2_1 0 0x4b5 1 0 2 DCC_CFG2_CONSTANT_1 0 31 regDCHUBBUB_RET_PATH_DCC_CFG3_0 0 0x4b6 1 0 2 DCC_CFG3_CONSTANT_0 0 31 regDCHUBBUB_RET_PATH_DCC_CFG3_1 0 0x4b7 1 0 2 DCC_CFG3_CONSTANT_1 0 31 regDCHUBBUB_RET_PATH_DCC_CFG4_0 0 0x4b8 1 0 2 DCC_CFG4_CONSTANT_0 0 31 regDCHUBBUB_RET_PATH_DCC_CFG4_1 0 0x4b9 1 0 2 DCC_CFG4_CONSTANT_1 0 31 regDCHUBBUB_RET_PATH_DCC_CFG5_0 0 0x4ba 1 0 2 DCC_CFG5_CONSTANT_0 0 31 regDCHUBBUB_RET_PATH_DCC_CFG5_1 0 0x4bb 1 0 2 DCC_CFG5_CONSTANT_1 0 31 regDCHUBBUB_RET_PATH_DCC_CFG6_0 0 0x4bc 1 0 2 DCC_CFG6_CONSTANT_0 0 31 regDCHUBBUB_RET_PATH_DCC_CFG6_1 0 0x4bd 1 0 2 DCC_CFG6_CONSTANT_1 0 31 regDCHUBBUB_RET_PATH_DCC_CFG7_0 0 0x4be 1 0 2 DCC_CFG7_CONSTANT_0 0 31 regDCHUBBUB_RET_PATH_DCC_CFG7_1 0 0x4bf 1 0 2 DCC_CFG7_CONSTANT_1 0 31 regDCHUBBUB_RET_PATH_MEM_PWR_CTRL 0 0x4c0 2 0 2 DCHUBBUB_RET_PATH_MEM_PWR_FORCE 0 1 DCHUBBUB_RET_PATH_MEM_PWR_DIS 2 2 regDCHUBBUB_RET_PATH_MEM_PWR_STATUS 0 0x4c1 1 0 2 DCHUBBUB_RET_PATH_MEM_PWR_STATE 0 1 regDCHUBBUB_CRC_CTRL 0 0x4c2 9 0 2 DCHUBBUB_CRC_EN 0 0 DCHUBBUB_CRC_CONT_EN 1 1 DCHUBBUB_CRC0_ONE_SHOT_PENDING 2 2 DCHUBBUB_CRC1_ONE_SHOT_PENDING 3 3 DCHUBBUB_CRC0_SRC_SEL 4 5 DCHUBBUB_CRC1_SRC_SEL 6 7 DCHUBBUB_CRC_PIPE_SEL 8 11 DCHUBBUB_CRC_SURF_SEL 12 12 DCHUBBUB_CRC_DATA_SRC_SEL 20 20 regDCHUBBUB_CRC0_VAL_R_G 0 0x4c3 2 0 2 DCHUBBUB_CRC0_R_CR 0 15 DCHUBBUB_CRC0_G_Y 16 31 regDCHUBBUB_CRC0_VAL_B_A 0 0x4c4 2 0 2 DCHUBBUB_CRC0_B_CB 0 15 DCHUBBUB_CRC0_ALPHA 16 31 regDCHUBBUB_CRC1_VAL_R_G 0 0x4c5 2 0 2 DCHUBBUB_CRC1_R_CR 0 15 DCHUBBUB_CRC1_G_Y 16 31 regDCHUBBUB_CRC1_VAL_B_A 0 0x4c6 2 0 2 DCHUBBUB_CRC1_B_CB 0 15 DCHUBBUB_CRC1_ALPHA 16 31 regDCHUBBUB_DCC_STAT_CNTL 0 0x4c7 5 0 2 DCHUBBUB_DCC_STAT_MODE 0 0 DCHUBBUB_DCC_STAT_EN 1 1 DCHUBBUB_DCC_STAT_DONE 2 2 DCHUBBUB_DCC_STAT_PIPE_SEL 4 7 DCHUBBUB_DCC_STAT_FRAME_CNT 16 31 regDCHUBBUB_DCC_STAT0 0 0x4c8 1 0 2 DCHUBBUB_DCC_STAT_TOTAL_REQ 0 31 regDCHUBBUB_DCC_STAT1 0 0x4c9 1 0 2 DCHUBBUB_DCC_STAT_ZS_REQ 0 31 regDCHUBBUB_DCC_STAT2 0 0x4ca 1 0 2 DCHUBBUB_DCC_STAT_DCC_REQ 0 31 regDCHUBBUB_COMPBUF_CTRL 0 0x4cb 6 0 2 COMPBUF_SIZE 0 4 COMPBUF_SIZE_CURRENT 8 12 COMPBUF_SIZE_CHANGE_DONE_INT_ENABLE 16 16 COMPBUF_SIZE_CHANGE_DONE_INT_STATUS 18 18 COMPBUF_SIZE_CHANGE_DONE_INT_CLEAR 19 19 CONFIG_ERROR 31 31 regDCHUBBUB_DET0_CTRL 0 0x4cc 2 0 2 DET0_SIZE 0 2 DET0_SIZE_CURRENT 8 10 regDCHUBBUB_DET1_CTRL 0 0x4cd 2 0 2 DET1_SIZE 0 2 DET1_SIZE_CURRENT 8 10 regDCHUBBUB_DET2_CTRL 0 0x4ce 2 0 2 DET2_SIZE 0 2 DET2_SIZE_CURRENT 8 10 regDCHUBBUB_DET3_CTRL 0 0x4cf 2 0 2 DET3_SIZE 0 2 DET3_SIZE_CURRENT 8 10 regDCHUBBUB_MEM_PWR_MODE_CTRL 0 0x4d1 12 0 2 COMPBUF_ACCESS_MEM_PWR_MODE 0 1 COMPBUF_ACTIVE_MEM_PWR_MODE 2 3 COMPBUF_IDLE_MEM_PWR_MODE 4 5 METAFIFO_MEM_PWR_FORCE 6 7 DCC_SKID_MEM_PWR_FORCE 8 9 UNALLOCATED_MEM_PWR_MODE 10 11 DET_MEM_PWR_FORCE 16 17 DET_IDLE_MEM_PWR_MODE 18 19 DET_MEM_PWR_LS_MODE 20 21 SEGMENT_MEM_PWR_DIS 24 24 METAFIFO_MEM_PWR_DIS 25 25 DCC_SKID_MEM_PWR_DIS 26 26 regCOMPBUF_MEM_PWR_CTRL_1 0 0x4d2 4 0 2 COMPBUF_ACTIVE_WAKE_LATENCY 0 7 COMPBUF_ACTIVE_SLEEP_LATENCY 8 15 COMPBUF_IDLE_WAKE_LATENCY 16 23 COMPBUF_IDLE_SLEEP_LATENCY 24 31 regCOMPBUF_MEM_PWR_CTRL_2 0 0x4d3 1 0 2 COMPBUF_UNALLOCATED_WAKE_LATENCY 0 7 regDCHUBBUB_MEM_PWR_STATUS 0 0x4d4 8 0 2 COMPBUF_MEM_PWR_STATE 0 1 METAFIFO_MEM_PWR_STATE 2 3 UNALLOCATED_MEM_PWR_STATE 4 5 DCC_SKID_MEM_PWR_STATE 6 7 DET0_MEM_PWR_STATE 8 9 DET1_MEM_PWR_STATE 10 11 DET2_MEM_PWR_STATE 12 13 DET3_MEM_PWR_STATE 14 15 regCOMPBUF_RESERVED_SPACE 0 0x4d5 2 0 2 COMPBUF_RESERVED_SPACE_64B 0 11 COMPBUF_RESERVED_SPACE_ZS 16 27 regDCN_VM_CONTEXT0_CNTL 0 0x559 2 0 2 VM_CONTEXT0_PAGE_TABLE_DEPTH 1 2 VM_CONTEXT0_PAGE_TABLE_BLOCK_SIZE 3 6 regDCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32 0 0x55a 1 0 2 VM_CONTEXT0_PAGE_DIRECTORY_ENTRY_HI32 0 31 regDCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32 0 0x55b 1 0 2 VM_CONTEXT0_PAGE_DIRECTORY_ENTRY_LO32 0 31 regDCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32 0 0x55c 1 0 2 VM_CONTEXT0_START_LOGICAL_PAGE_NUMBER_HI4 0 3 regDCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32 0 0x55d 1 0 2 VM_CONTEXT0_START_LOGICAL_PAGE_NUMBER_LO32 0 31 regDCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32 0 0x55e 1 0 2 VM_CONTEXT0_END_LOGICAL_PAGE_NUMBER_HI4 0 3 regDCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32 0 0x55f 1 0 2 VM_CONTEXT0_END_LOGICAL_PAGE_NUMBER_LO32 0 31 regDCN_VM_CONTEXT1_CNTL 0 0x560 2 0 2 VM_CONTEXT1_PAGE_TABLE_DEPTH 1 2 VM_CONTEXT1_PAGE_TABLE_BLOCK_SIZE 3 6 regDCN_VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32 0 0x561 1 0 2 VM_CONTEXT1_PAGE_DIRECTORY_ENTRY_HI32 0 31 regDCN_VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32 0 0x562 1 0 2 VM_CONTEXT1_PAGE_DIRECTORY_ENTRY_LO32 0 31 regDCN_VM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32 0 0x563 1 0 2 VM_CONTEXT1_START_LOGICAL_PAGE_NUMBER_HI4 0 3 regDCN_VM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32 0 0x564 1 0 2 VM_CONTEXT1_START_LOGICAL_PAGE_NUMBER_LO32 0 31 regDCN_VM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32 0 0x565 1 0 2 VM_CONTEXT1_END_LOGICAL_PAGE_NUMBER_HI4 0 3 regDCN_VM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32 0 0x566 1 0 2 VM_CONTEXT1_END_LOGICAL_PAGE_NUMBER_LO32 0 31 regDCN_VM_CONTEXT2_CNTL 0 0x567 2 0 2 VM_CONTEXT2_PAGE_TABLE_DEPTH 1 2 VM_CONTEXT2_PAGE_TABLE_BLOCK_SIZE 3 6 regDCN_VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32 0 0x568 1 0 2 VM_CONTEXT2_PAGE_DIRECTORY_ENTRY_HI32 0 31 regDCN_VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32 0 0x569 1 0 2 VM_CONTEXT2_PAGE_DIRECTORY_ENTRY_LO32 0 31 regDCN_VM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32 0 0x56a 1 0 2 VM_CONTEXT2_START_LOGICAL_PAGE_NUMBER_HI4 0 3 regDCN_VM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32 0 0x56b 1 0 2 VM_CONTEXT2_START_LOGICAL_PAGE_NUMBER_LO32 0 31 regDCN_VM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32 0 0x56c 1 0 2 VM_CONTEXT2_END_LOGICAL_PAGE_NUMBER_HI4 0 3 regDCN_VM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32 0 0x56d 1 0 2 VM_CONTEXT2_END_LOGICAL_PAGE_NUMBER_LO32 0 31 regDCN_VM_CONTEXT3_CNTL 0 0x56e 2 0 2 VM_CONTEXT3_PAGE_TABLE_DEPTH 1 2 VM_CONTEXT3_PAGE_TABLE_BLOCK_SIZE 3 6 regDCN_VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32 0 0x56f 1 0 2 VM_CONTEXT3_PAGE_DIRECTORY_ENTRY_HI32 0 31 regDCN_VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32 0 0x570 1 0 2 VM_CONTEXT3_PAGE_DIRECTORY_ENTRY_LO32 0 31 regDCN_VM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32 0 0x571 1 0 2 VM_CONTEXT3_START_LOGICAL_PAGE_NUMBER_HI4 0 3 regDCN_VM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32 0 0x572 1 0 2 VM_CONTEXT3_START_LOGICAL_PAGE_NUMBER_LO32 0 31 regDCN_VM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32 0 0x573 1 0 2 VM_CONTEXT3_END_LOGICAL_PAGE_NUMBER_HI4 0 3 regDCN_VM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32 0 0x574 1 0 2 VM_CONTEXT3_END_LOGICAL_PAGE_NUMBER_LO32 0 31 regDCN_VM_CONTEXT4_CNTL 0 0x575 2 0 2 VM_CONTEXT4_PAGE_TABLE_DEPTH 1 2 VM_CONTEXT4_PAGE_TABLE_BLOCK_SIZE 3 6 regDCN_VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32 0 0x576 1 0 2 VM_CONTEXT4_PAGE_DIRECTORY_ENTRY_HI32 0 31 regDCN_VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32 0 0x577 1 0 2 VM_CONTEXT4_PAGE_DIRECTORY_ENTRY_LO32 0 31 regDCN_VM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32 0 0x578 1 0 2 VM_CONTEXT4_START_LOGICAL_PAGE_NUMBER_HI4 0 3 regDCN_VM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32 0 0x579 1 0 2 VM_CONTEXT4_START_LOGICAL_PAGE_NUMBER_LO32 0 31 regDCN_VM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32 0 0x57a 1 0 2 VM_CONTEXT4_END_LOGICAL_PAGE_NUMBER_HI4 0 3 regDCN_VM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32 0 0x57b 1 0 2 VM_CONTEXT4_END_LOGICAL_PAGE_NUMBER_LO32 0 31 regDCN_VM_CONTEXT5_CNTL 0 0x57c 2 0 2 VM_CONTEXT5_PAGE_TABLE_DEPTH 1 2 VM_CONTEXT5_PAGE_TABLE_BLOCK_SIZE 3 6 regDCN_VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32 0 0x57d 1 0 2 VM_CONTEXT5_PAGE_DIRECTORY_ENTRY_HI32 0 31 regDCN_VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32 0 0x57e 1 0 2 VM_CONTEXT5_PAGE_DIRECTORY_ENTRY_LO32 0 31 regDCN_VM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32 0 0x57f 1 0 2 VM_CONTEXT5_START_LOGICAL_PAGE_NUMBER_HI4 0 3 regDCN_VM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32 0 0x580 1 0 2 VM_CONTEXT5_START_LOGICAL_PAGE_NUMBER_LO32 0 31 regDCN_VM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32 0 0x581 1 0 2 VM_CONTEXT5_END_LOGICAL_PAGE_NUMBER_HI4 0 3 regDCN_VM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32 0 0x582 1 0 2 VM_CONTEXT5_END_LOGICAL_PAGE_NUMBER_LO32 0 31 regDCN_VM_CONTEXT6_CNTL 0 0x583 2 0 2 VM_CONTEXT6_PAGE_TABLE_DEPTH 1 2 VM_CONTEXT6_PAGE_TABLE_BLOCK_SIZE 3 6 regDCN_VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32 0 0x584 1 0 2 VM_CONTEXT6_PAGE_DIRECTORY_ENTRY_HI32 0 31 regDCN_VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32 0 0x585 1 0 2 VM_CONTEXT6_PAGE_DIRECTORY_ENTRY_LO32 0 31 regDCN_VM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32 0 0x586 1 0 2 VM_CONTEXT6_START_LOGICAL_PAGE_NUMBER_HI4 0 3 regDCN_VM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32 0 0x587 1 0 2 VM_CONTEXT6_START_LOGICAL_PAGE_NUMBER_LO32 0 31 regDCN_VM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32 0 0x588 1 0 2 VM_CONTEXT6_END_LOGICAL_PAGE_NUMBER_HI4 0 3 regDCN_VM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32 0 0x589 1 0 2 VM_CONTEXT6_END_LOGICAL_PAGE_NUMBER_LO32 0 31 regDCN_VM_CONTEXT7_CNTL 0 0x58a 2 0 2 VM_CONTEXT7_PAGE_TABLE_DEPTH 1 2 VM_CONTEXT7_PAGE_TABLE_BLOCK_SIZE 3 6 regDCN_VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32 0 0x58b 1 0 2 VM_CONTEXT7_PAGE_DIRECTORY_ENTRY_HI32 0 31 regDCN_VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32 0 0x58c 1 0 2 VM_CONTEXT7_PAGE_DIRECTORY_ENTRY_LO32 0 31 regDCN_VM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32 0 0x58d 1 0 2 VM_CONTEXT7_START_LOGICAL_PAGE_NUMBER_HI4 0 3 regDCN_VM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32 0 0x58e 1 0 2 VM_CONTEXT7_START_LOGICAL_PAGE_NUMBER_LO32 0 31 regDCN_VM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32 0 0x58f 1 0 2 VM_CONTEXT7_END_LOGICAL_PAGE_NUMBER_HI4 0 3 regDCN_VM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32 0 0x590 1 0 2 VM_CONTEXT7_END_LOGICAL_PAGE_NUMBER_LO32 0 31 regDCN_VM_CONTEXT8_CNTL 0 0x591 2 0 2 VM_CONTEXT8_PAGE_TABLE_DEPTH 1 2 VM_CONTEXT8_PAGE_TABLE_BLOCK_SIZE 3 6 regDCN_VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32 0 0x592 1 0 2 VM_CONTEXT8_PAGE_DIRECTORY_ENTRY_HI32 0 31 regDCN_VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32 0 0x593 1 0 2 VM_CONTEXT8_PAGE_DIRECTORY_ENTRY_LO32 0 31 regDCN_VM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32 0 0x594 1 0 2 VM_CONTEXT8_START_LOGICAL_PAGE_NUMBER_HI4 0 3 regDCN_VM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32 0 0x595 1 0 2 VM_CONTEXT8_START_LOGICAL_PAGE_NUMBER_LO32 0 31 regDCN_VM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32 0 0x596 1 0 2 VM_CONTEXT8_END_LOGICAL_PAGE_NUMBER_HI4 0 3 regDCN_VM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32 0 0x597 1 0 2 VM_CONTEXT8_END_LOGICAL_PAGE_NUMBER_LO32 0 31 regDCN_VM_CONTEXT9_CNTL 0 0x598 2 0 2 VM_CONTEXT9_PAGE_TABLE_DEPTH 1 2 VM_CONTEXT9_PAGE_TABLE_BLOCK_SIZE 3 6 regDCN_VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32 0 0x599 1 0 2 VM_CONTEXT9_PAGE_DIRECTORY_ENTRY_HI32 0 31 regDCN_VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32 0 0x59a 1 0 2 VM_CONTEXT9_PAGE_DIRECTORY_ENTRY_LO32 0 31 regDCN_VM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32 0 0x59b 1 0 2 VM_CONTEXT9_START_LOGICAL_PAGE_NUMBER_HI4 0 3 regDCN_VM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32 0 0x59c 1 0 2 VM_CONTEXT9_START_LOGICAL_PAGE_NUMBER_LO32 0 31 regDCN_VM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32 0 0x59d 1 0 2 VM_CONTEXT9_END_LOGICAL_PAGE_NUMBER_HI4 0 3 regDCN_VM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32 0 0x59e 1 0 2 VM_CONTEXT9_END_LOGICAL_PAGE_NUMBER_LO32 0 31 regDCN_VM_CONTEXT10_CNTL 0 0x59f 2 0 2 VM_CONTEXT10_PAGE_TABLE_DEPTH 1 2 VM_CONTEXT10_PAGE_TABLE_BLOCK_SIZE 3 6 regDCN_VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32 0 0x5a0 1 0 2 VM_CONTEXT10_PAGE_DIRECTORY_ENTRY_HI32 0 31 regDCN_VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32 0 0x5a1 1 0 2 VM_CONTEXT10_PAGE_DIRECTORY_ENTRY_LO32 0 31 regDCN_VM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32 0 0x5a2 1 0 2 VM_CONTEXT10_START_LOGICAL_PAGE_NUMBER_HI4 0 3 regDCN_VM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32 0 0x5a3 1 0 2 VM_CONTEXT10_START_LOGICAL_PAGE_NUMBER_LO32 0 31 regDCN_VM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32 0 0x5a4 1 0 2 VM_CONTEXT10_END_LOGICAL_PAGE_NUMBER_HI4 0 3 regDCN_VM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32 0 0x5a5 1 0 2 VM_CONTEXT10_END_LOGICAL_PAGE_NUMBER_LO32 0 31 regDCN_VM_CONTEXT11_CNTL 0 0x5a6 2 0 2 VM_CONTEXT11_PAGE_TABLE_DEPTH 1 2 VM_CONTEXT11_PAGE_TABLE_BLOCK_SIZE 3 6 regDCN_VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32 0 0x5a7 1 0 2 VM_CONTEXT11_PAGE_DIRECTORY_ENTRY_HI32 0 31 regDCN_VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32 0 0x5a8 1 0 2 VM_CONTEXT11_PAGE_DIRECTORY_ENTRY_LO32 0 31 regDCN_VM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32 0 0x5a9 1 0 2 VM_CONTEXT11_START_LOGICAL_PAGE_NUMBER_HI4 0 3 regDCN_VM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32 0 0x5aa 1 0 2 VM_CONTEXT11_START_LOGICAL_PAGE_NUMBER_LO32 0 31 regDCN_VM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32 0 0x5ab 1 0 2 VM_CONTEXT11_END_LOGICAL_PAGE_NUMBER_HI4 0 3 regDCN_VM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32 0 0x5ac 1 0 2 VM_CONTEXT11_END_LOGICAL_PAGE_NUMBER_LO32 0 31 regDCN_VM_CONTEXT12_CNTL 0 0x5ad 2 0 2 VM_CONTEXT12_PAGE_TABLE_DEPTH 1 2 VM_CONTEXT12_PAGE_TABLE_BLOCK_SIZE 3 6 regDCN_VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32 0 0x5ae 1 0 2 VM_CONTEXT12_PAGE_DIRECTORY_ENTRY_HI32 0 31 regDCN_VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32 0 0x5af 1 0 2 VM_CONTEXT12_PAGE_DIRECTORY_ENTRY_LO32 0 31 regDCN_VM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32 0 0x5b0 1 0 2 VM_CONTEXT12_START_LOGICAL_PAGE_NUMBER_HI4 0 3 regDCN_VM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32 0 0x5b1 1 0 2 VM_CONTEXT12_START_LOGICAL_PAGE_NUMBER_LO32 0 31 regDCN_VM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32 0 0x5b2 1 0 2 VM_CONTEXT12_END_LOGICAL_PAGE_NUMBER_HI4 0 3 regDCN_VM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32 0 0x5b3 1 0 2 VM_CONTEXT12_END_LOGICAL_PAGE_NUMBER_LO32 0 31 regDCN_VM_CONTEXT13_CNTL 0 0x5b4 2 0 2 VM_CONTEXT13_PAGE_TABLE_DEPTH 1 2 VM_CONTEXT13_PAGE_TABLE_BLOCK_SIZE 3 6 regDCN_VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32 0 0x5b5 1 0 2 VM_CONTEXT13_PAGE_DIRECTORY_ENTRY_HI32 0 31 regDCN_VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32 0 0x5b6 1 0 2 VM_CONTEXT13_PAGE_DIRECTORY_ENTRY_LO32 0 31 regDCN_VM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32 0 0x5b7 1 0 2 VM_CONTEXT13_START_LOGICAL_PAGE_NUMBER_HI4 0 3 regDCN_VM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32 0 0x5b8 1 0 2 VM_CONTEXT13_START_LOGICAL_PAGE_NUMBER_LO32 0 31 regDCN_VM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32 0 0x5b9 1 0 2 VM_CONTEXT13_END_LOGICAL_PAGE_NUMBER_HI4 0 3 regDCN_VM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32 0 0x5ba 1 0 2 VM_CONTEXT13_END_LOGICAL_PAGE_NUMBER_LO32 0 31 regDCN_VM_CONTEXT14_CNTL 0 0x5bb 2 0 2 VM_CONTEXT14_PAGE_TABLE_DEPTH 1 2 VM_CONTEXT14_PAGE_TABLE_BLOCK_SIZE 3 6 regDCN_VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32 0 0x5bc 1 0 2 VM_CONTEXT14_PAGE_DIRECTORY_ENTRY_HI32 0 31 regDCN_VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32 0 0x5bd 1 0 2 VM_CONTEXT14_PAGE_DIRECTORY_ENTRY_LO32 0 31 regDCN_VM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32 0 0x5be 1 0 2 VM_CONTEXT14_START_LOGICAL_PAGE_NUMBER_HI4 0 3 regDCN_VM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32 0 0x5bf 1 0 2 VM_CONTEXT14_START_LOGICAL_PAGE_NUMBER_LO32 0 31 regDCN_VM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32 0 0x5c0 1 0 2 VM_CONTEXT14_END_LOGICAL_PAGE_NUMBER_HI4 0 3 regDCN_VM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32 0 0x5c1 1 0 2 VM_CONTEXT14_END_LOGICAL_PAGE_NUMBER_LO32 0 31 regDCN_VM_CONTEXT15_CNTL 0 0x5c2 2 0 2 VM_CONTEXT15_PAGE_TABLE_DEPTH 1 2 VM_CONTEXT15_PAGE_TABLE_BLOCK_SIZE 3 6 regDCN_VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32 0 0x5c3 1 0 2 VM_CONTEXT15_PAGE_DIRECTORY_ENTRY_HI32 0 31 regDCN_VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32 0 0x5c4 1 0 2 VM_CONTEXT15_PAGE_DIRECTORY_ENTRY_LO32 0 31 regDCN_VM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32 0 0x5c5 1 0 2 VM_CONTEXT15_START_LOGICAL_PAGE_NUMBER_HI4 0 3 regDCN_VM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32 0 0x5c6 1 0 2 VM_CONTEXT15_START_LOGICAL_PAGE_NUMBER_LO32 0 31 regDCN_VM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32 0 0x5c7 1 0 2 VM_CONTEXT15_END_LOGICAL_PAGE_NUMBER_HI4 0 3 regDCN_VM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32 0 0x5c8 1 0 2 VM_CONTEXT15_END_LOGICAL_PAGE_NUMBER_LO32 0 31 regDCN_VM_DEFAULT_ADDR_MSB 0 0x5c9 3 0 2 DCN_VM_DEFAULT_ADDR_MSB 0 3 DCN_VM_DEFAULT_SPA 28 28 DCN_VM_DEFAULT_SNOOP 29 29 regDCN_VM_DEFAULT_ADDR_LSB 0 0x5ca 1 0 2 DCN_VM_DEFAULT_ADDR_LSB 0 31 regDCN_VM_FAULT_CNTL 0 0x5cb 5 0 2 DCN_VM_ERROR_STATUS_CLEAR 0 0 DCN_VM_ERROR_STATUS_MODE 1 1 DCN_VM_ERROR_INTERRUPT_ENABLE 2 2 DCN_VM_RANGE_FAULT_DISABLE 8 8 DCN_VM_PRQ_FAULT_DISABLE 9 9 regDCN_VM_FAULT_STATUS 0 0x5cc 6 0 2 DCN_VM_ERROR_STATUS 0 15 DCN_VM_ERROR_VMID 16 19 DCN_VM_TR_RESP_ERROR_VMID 20 23 DCN_VM_ERROR_TABLE_LEVEL 24 25 DCN_VM_ERROR_PIPE 26 29 DCN_VM_ERROR_INTERRUPT_STATUS 31 31 regDCN_VM_FAULT_ADDR_MSB 0 0x5cd 1 0 2 DCN_VM_FAULT_ADDR_MSB 0 3 regDCN_VM_FAULT_ADDR_LSB 0 0x5ce 1 0 2 DCN_VM_FAULT_ADDR_LSB 0 31 regDC_PERFMON6_PERFCOUNTER_CNTL 0 0x54d 11 0 2 PERFCOUNTER_EVENT_SEL 0 8 PERFCOUNTER_CVALUE_SEL 9 11 PERFCOUNTER_INC_MODE 12 14 PERFCOUNTER_HW_CNTL_SEL 15 15 PERFCOUNTER_RUNEN_MODE 16 16 PERFCOUNTER_CNTOFF_START_DIS 22 22 PERFCOUNTER_RESTART_EN 23 23 PERFCOUNTER_INT_EN 24 24 PERFCOUNTER_OFF_MASK 25 25 PERFCOUNTER_ACTIVE 26 26 PERFCOUNTER_CNTL_SEL 29 31 regDC_PERFMON6_PERFCOUNTER_CNTL2 0 0x54e 5 0 2 PERFCOUNTER_COUNTED_VALUE_TYPE 0 1 PERFCOUNTER_HW_STOP1_SEL 2 2 PERFCOUNTER_HW_STOP2_SEL 3 3 PERFCOUNTER_CNTOFF_SEL 8 13 PERFCOUNTER_CNTL2_SEL 29 31 regDC_PERFMON6_PERFCOUNTER_STATE 0 0x54f 16 0 2 PERFCOUNTER_CNT0_STATE 0 1 PERFCOUNTER_STATE_SEL0 2 2 PERFCOUNTER_CNT1_STATE 4 5 PERFCOUNTER_STATE_SEL1 6 6 PERFCOUNTER_CNT2_STATE 8 9 PERFCOUNTER_STATE_SEL2 10 10 PERFCOUNTER_CNT3_STATE 12 13 PERFCOUNTER_STATE_SEL3 14 14 PERFCOUNTER_CNT4_STATE 16 17 PERFCOUNTER_STATE_SEL4 18 18 PERFCOUNTER_CNT5_STATE 20 21 PERFCOUNTER_STATE_SEL5 22 22 PERFCOUNTER_CNT6_STATE 24 25 PERFCOUNTER_STATE_SEL6 26 26 PERFCOUNTER_CNT7_STATE 28 29 PERFCOUNTER_STATE_SEL7 30 30 regDC_PERFMON6_PERFMON_CNTL 0 0x550 6 0 2 PERFMON_STATE 0 1 PERFMON_RPT_COUNT 8 27 PERFMON_CNTOFF_AND_OR 28 28 PERFMON_CNTOFF_INT_EN 29 29 PERFMON_CNTOFF_INT_STATUS 30 30 PERFMON_CNTOFF_INT_ACK 31 31 regDC_PERFMON6_PERFMON_CNTL2 0 0x551 4 0 2 PERFMON_CNTOFF_INT_TYPE 0 0 PERFMON_CLK_ENABLE 1 1 PERFMON_RUN_ENABLE_START_SEL 2 9 PERFMON_RUN_ENABLE_STOP_SEL 10 17 regDC_PERFMON6_PERFMON_CVALUE_INT_MISC 0 0x552 17 0 2 PERFCOUNTER_INT0_STATUS 0 0 PERFCOUNTER_INT1_STATUS 1 1 PERFCOUNTER_INT2_STATUS 2 2 PERFCOUNTER_INT3_STATUS 3 3 PERFCOUNTER_INT4_STATUS 4 4 PERFCOUNTER_INT5_STATUS 5 5 PERFCOUNTER_INT6_STATUS 6 6 PERFCOUNTER_INT7_STATUS 7 7 PERFCOUNTER_INT0_ACK 8 8 PERFCOUNTER_INT1_ACK 9 9 PERFCOUNTER_INT2_ACK 10 10 PERFCOUNTER_INT3_ACK 11 11 PERFCOUNTER_INT4_ACK 12 12 PERFCOUNTER_INT5_ACK 13 13 PERFCOUNTER_INT6_ACK 14 14 PERFCOUNTER_INT7_ACK 15 15 PERFMON_CVALUE_HI 16 31 regDC_PERFMON6_PERFMON_CVALUE_LOW 0 0x553 1 0 2 PERFMON_CVALUE_LOW 0 31 regDC_PERFMON6_PERFMON_HI 0 0x554 2 0 2 PERFMON_HI 0 15 PERFMON_READ_SEL 29 31 regDC_PERFMON6_PERFMON_LOW 0 0x555 1 0 2 PERFMON_LOW 0 31 regHUBP0_DCSURF_SURFACE_CONFIG 0 0x5e5 4 0 2 SURFACE_PIXEL_FORMAT 0 6 ROTATION_ANGLE 8 9 H_MIRROR_EN 10 10 ALPHA_PLANE_EN 11 11 regHUBP0_DCSURF_ADDR_CONFIG 0 0x5e6 4 0 2 NUM_PIPES 0 2 PIPE_INTERLEAVE 6 7 MAX_COMPRESSED_FRAGS 12 13 NUM_PKRS 16 18 regHUBP0_DCSURF_TILING_CONFIG 0 0x5e7 4 0 2 SW_MODE 0 4 DIM_TYPE 7 8 META_LINEAR 9 9 PIPE_ALIGNED 11 11 regHUBP0_DCSURF_PRI_VIEWPORT_START 0 0x5e9 2 0 2 PRI_VIEWPORT_X_START 0 13 PRI_VIEWPORT_Y_START 16 29 regHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION 0 0x5ea 2 0 2 PRI_VIEWPORT_WIDTH 0 13 PRI_VIEWPORT_HEIGHT 16 29 regHUBP0_DCSURF_PRI_VIEWPORT_START_C 0 0x5eb 2 0 2 PRI_VIEWPORT_X_START_C 0 13 PRI_VIEWPORT_Y_START_C 16 29 regHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_C 0 0x5ec 2 0 2 PRI_VIEWPORT_WIDTH_C 0 13 PRI_VIEWPORT_HEIGHT_C 16 29 regHUBP0_DCSURF_SEC_VIEWPORT_START 0 0x5ed 2 0 2 SEC_VIEWPORT_X_START 0 13 SEC_VIEWPORT_Y_START 16 29 regHUBP0_DCSURF_SEC_VIEWPORT_DIMENSION 0 0x5ee 2 0 2 SEC_VIEWPORT_WIDTH 0 13 SEC_VIEWPORT_HEIGHT 16 29 regHUBP0_DCSURF_SEC_VIEWPORT_START_C 0 0x5ef 2 0 2 SEC_VIEWPORT_X_START_C 0 13 SEC_VIEWPORT_Y_START_C 16 29 regHUBP0_DCSURF_SEC_VIEWPORT_DIMENSION_C 0 0x5f0 2 0 2 SEC_VIEWPORT_WIDTH_C 0 13 SEC_VIEWPORT_HEIGHT_C 16 29 regHUBP0_DCHUBP_REQ_SIZE_CONFIG 0 0x5f1 8 0 2 SWATH_HEIGHT 0 2 PTE_ROW_HEIGHT_LINEAR 4 6 CHUNK_SIZE 8 10 MIN_CHUNK_SIZE 11 12 META_CHUNK_SIZE 16 17 MIN_META_CHUNK_SIZE 18 19 DPTE_GROUP_SIZE 20 22 VM_GROUP_SIZE 24 26 regHUBP0_DCHUBP_REQ_SIZE_CONFIG_C 0 0x5f2 7 0 2 SWATH_HEIGHT_C 0 2 PTE_ROW_HEIGHT_LINEAR_C 4 6 CHUNK_SIZE_C 8 10 MIN_CHUNK_SIZE_C 11 12 META_CHUNK_SIZE_C 16 17 MIN_META_CHUNK_SIZE_C 18 19 DPTE_GROUP_SIZE_C 20 22 regHUBP0_DCHUBP_CNTL 0 0x5f3 18 0 2 HUBP_BLANK_EN 0 0 HUBP_NO_OUTSTANDING_REQ 1 1 HUBP_SOFT_RESET 2 2 HUBP_IN_BLANK 3 3 HUBP_VTG_SEL 4 7 HUBP_VREADY_AT_OR_AFTER_VSYNC 8 8 HUBP_DISABLE_STOP_DATA_DURING_VM 9 9 HUBP_UNBOUNDED_REQ_MODE 10 10 HUBP_SEG_ALLOC_ERR_STATUS 11 11 HUBP_TTU_DISABLE 12 12 HUBP_TTU_MODE 13 15 HUBP_XRQ_NO_OUTSTANDING_REQ 16 19 HUBP_TIMEOUT_STATUS 20 23 HUBP_TIMEOUT_THRESHOLD 24 25 HUBP_TIMEOUT_STATUS_CLEAR 26 26 HUBP_TIMEOUT_INTERRUPT_EN 27 27 HUBP_UNDERFLOW_STATUS 28 30 HUBP_UNDERFLOW_CLEAR 31 31 regHUBP0_HUBP_CLK_CNTL 0 0x5f4 10 0 2 HUBP_CLOCK_ENABLE 0 0 HUBP_DISPCLK_R_GATE_DIS 4 4 HUBP_DPPCLK_G_GATE_DIS 8 8 HUBP_DCFCLK_R_GATE_DIS 12 12 HUBP_DCFCLK_G_GATE_DIS 16 16 HUBP_DISPCLK_R_CLOCK_ON 20 20 HUBP_DPPCLK_G_CLOCK_ON 21 21 HUBP_DCFCLK_R_CLOCK_ON 22 22 HUBP_DCFCLK_G_CLOCK_ON 23 23 HUBP_TEST_CLK_SEL 28 31 regHUBP0_DCHUBP_VMPG_CONFIG 0 0x5f5 1 0 2 VMPG_SIZE 0 0 regHUBP0_HUBPREQ_DEBUG_DB 0 0x5f6 1 0 2 HUBPREQ_DEBUG 0 31 regHUBP0_HUBPREQ_DEBUG 0 0x5f7 1 0 2 HUBPREQ_DEBUG 0 31 regHUBP0_HUBP_MEASURE_WIN_CTRL_DCFCLK 0 0x5fb 5 0 2 HUBP_MEASURE_WIN_EN_DCFCLK 0 0 HUBP_MEASURE_WIN_PERIOD_M1_DCFCLK 4 11 HUBP_PERFMON_START_SEL_DCFCLK 12 16 HUBP_PERFMON_STOP_SEL_DCFCLK 20 24 HUBP_MEASURE_WIN_MODE_DCFCLK 28 29 regHUBP0_HUBP_MEASURE_WIN_CTRL_DPPCLK 0 0x5fc 5 0 2 HUBP_MEASURE_WIN_EN_DPPCLK 0 0 HUBP_MEASURE_WIN_SRC_SEL_DPPCLK 1 1 HUBP_MEASURE_WIN_PERIOD_M1_DPPCLK 4 11 HUBP_PERFMON_START_SEL_DPPCLK 12 16 HUBP_PERFMON_STOP_SEL_DPPCLK 20 24 regHUBPREQ0_DCSURF_SURFACE_PITCH 0 0x607 2 0 2 PITCH 0 13 META_PITCH 16 29 regHUBPREQ0_DCSURF_SURFACE_PITCH_C 0 0x608 2 0 2 PITCH_C 0 13 META_PITCH_C 16 29 regHUBPREQ0_VMID_SETTINGS_0 0 0x609 1 0 2 VMID 0 3 regHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS 0 0x60a 1 0 2 PRIMARY_SURFACE_ADDRESS 0 31 regHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH 0 0x60b 1 0 2 PRIMARY_SURFACE_ADDRESS_HIGH 0 15 regHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_C 0 0x60c 1 0 2 PRIMARY_SURFACE_ADDRESS_C 0 31 regHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C 0 0x60d 1 0 2 PRIMARY_SURFACE_ADDRESS_HIGH_C 0 15 regHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS 0 0x60e 1 0 2 SECONDARY_SURFACE_ADDRESS 0 31 regHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH 0 0x60f 1 0 2 SECONDARY_SURFACE_ADDRESS_HIGH 0 15 regHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_C 0 0x610 1 0 2 SECONDARY_SURFACE_ADDRESS_C 0 31 regHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C 0 0x611 1 0 2 SECONDARY_SURFACE_ADDRESS_HIGH_C 0 15 regHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS 0 0x612 1 0 2 PRIMARY_META_SURFACE_ADDRESS 0 31 regHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH 0 0x613 1 0 2 PRIMARY_META_SURFACE_ADDRESS_HIGH 0 15 regHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C 0 0x614 1 0 2 PRIMARY_META_SURFACE_ADDRESS_C 0 31 regHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C 0 0x615 1 0 2 PRIMARY_META_SURFACE_ADDRESS_HIGH_C 0 15 regHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS 0 0x616 1 0 2 SECONDARY_META_SURFACE_ADDRESS 0 31 regHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH 0 0x617 1 0 2 SECONDARY_META_SURFACE_ADDRESS_HIGH 0 15 regHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C 0 0x618 1 0 2 SECONDARY_META_SURFACE_ADDRESS_C 0 31 regHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C 0 0x619 1 0 2 SECONDARY_META_SURFACE_ADDRESS_HIGH_C 0 15 regHUBPREQ0_DCSURF_SURFACE_CONTROL 0 0x61a 14 0 2 PRIMARY_SURFACE_TMZ 0 0 PRIMARY_SURFACE_DCC_EN 1 1 PRIMARY_SURFACE_DCC_IND_BLK 2 3 PRIMARY_SURFACE_TMZ_C 4 4 PRIMARY_SURFACE_DCC_IND_BLK_C 5 6 SECONDARY_SURFACE_TMZ 8 8 SECONDARY_SURFACE_DCC_EN 9 9 SECONDARY_SURFACE_DCC_IND_BLK 10 11 SECONDARY_SURFACE_TMZ_C 12 12 SECONDARY_SURFACE_DCC_IND_BLK_C 13 14 PRIMARY_META_SURFACE_TMZ 16 16 PRIMARY_META_SURFACE_TMZ_C 17 17 SECONDARY_META_SURFACE_TMZ 18 18 SECONDARY_META_SURFACE_TMZ_C 19 19 regHUBPREQ0_DCSURF_FLIP_CONTROL 0 0x61b 10 0 2 SURFACE_UPDATE_LOCK 0 0 SURFACE_FLIP_TYPE 1 1 SURFACE_FLIP_VUPDATE_SKIP_NUM 4 7 SURFACE_FLIP_PENDING 8 8 HUBPREQ_MASTER_UPDATE_LOCK_STATUS 9 9 SURFACE_FLIP_MODE_FOR_STEREOSYNC 12 13 SURFACE_FLIP_IN_STEREOSYNC 16 16 SURFACE_FLIP_STEREO_SELECT_DISABLE 17 17 SURFACE_FLIP_STEREO_SELECT_POLARITY 18 18 SURFACE_FLIP_PENDING_DELAY 20 29 regHUBPREQ0_DCSURF_FLIP_CONTROL2 0 0x61c 6 0 2 SURFACE_FLIP_PENDING_MIN_TIME 0 7 SURFACE_GSL_ENABLE 8 8 SURFACE_GSL_MASK 9 9 SURFACE_TRIPLE_BUFFER_ENABLE 10 10 SURFACE_INUSE_RAED_NO_LATCH 12 12 SURFACE_FLIP_EXEC_DEBUG_MODE 31 31 regHUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT 0 0x620 10 0 2 SURFACE_FLIP_INT_MASK 0 0 SURFACE_FLIP_INT_TYPE 1 1 SURFACE_FLIP_AWAY_INT_MASK 2 2 SURFACE_FLIP_AWAY_INT_TYPE 3 3 SURFACE_FLIP_CLEAR 8 8 SURFACE_FLIP_AWAY_CLEAR 9 9 SURFACE_FLIP_OCCURRED 16 16 SURFACE_FLIP_INT_STATUS 17 17 SURFACE_FLIP_AWAY_OCCURRED 18 18 SURFACE_FLIP_AWAY_INT_STATUS 19 19 regHUBPREQ0_DCSURF_SURFACE_INUSE 0 0x621 1 0 2 SURFACE_INUSE_ADDRESS 0 31 regHUBPREQ0_DCSURF_SURFACE_INUSE_HIGH 0 0x622 2 0 2 SURFACE_INUSE_ADDRESS_HIGH 0 15 SURFACE_INUSE_VMID 28 31 regHUBPREQ0_DCSURF_SURFACE_INUSE_C 0 0x623 1 0 2 SURFACE_INUSE_ADDRESS_C 0 31 regHUBPREQ0_DCSURF_SURFACE_INUSE_HIGH_C 0 0x624 2 0 2 SURFACE_INUSE_ADDRESS_HIGH_C 0 15 SURFACE_INUSE_VMID_C 28 31 regHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE 0 0x625 1 0 2 SURFACE_EARLIEST_INUSE_ADDRESS 0 31 regHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH 0 0x626 2 0 2 SURFACE_EARLIEST_INUSE_ADDRESS_HIGH 0 15 SURFACE_EARLIEST_INUSE_VMID 28 31 regHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_C 0 0x627 1 0 2 SURFACE_EARLIEST_INUSE_ADDRESS_C 0 31 regHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C 0 0x628 2 0 2 SURFACE_EARLIEST_INUSE_ADDRESS_HIGH_C 0 15 SURFACE_EARLIEST_INUSE_VMID_C 28 31 regHUBPREQ0_DCN_EXPANSION_MODE 0 0x629 4 0 2 DRQ_EXPANSION_MODE 0 1 CRQ_EXPANSION_MODE 2 3 MRQ_EXPANSION_MODE 4 5 PRQ_EXPANSION_MODE 6 7 regHUBPREQ0_DCN_TTU_QOS_WM 0 0x62a 2 0 2 QoS_LEVEL_LOW_WM 0 13 QoS_LEVEL_HIGH_WM 16 29 regHUBPREQ0_DCN_GLOBAL_TTU_CNTL 0 0x62b 5 0 2 MIN_TTU_VBLANK 0 23 PIPE_IN_FLUSH_URGENT 24 24 PRQ_MRQ_FLUSH_URGENT 25 25 ROW_TTU_MODE 27 27 QoS_LEVEL_FLIP 28 31 regHUBPREQ0_DCN_SURF0_TTU_CNTL0 0 0x62c 3 0 2 REFCYC_PER_REQ_DELIVERY 0 22 QoS_LEVEL_FIXED 24 27 QoS_RAMP_DISABLE 28 28 regHUBPREQ0_DCN_SURF0_TTU_CNTL1 0 0x62d 1 0 2 REFCYC_PER_REQ_DELIVERY_PRE 0 22 regHUBPREQ0_DCN_SURF1_TTU_CNTL0 0 0x62e 3 0 2 REFCYC_PER_REQ_DELIVERY 0 22 QoS_LEVEL_FIXED 24 27 QoS_RAMP_DISABLE 28 28 regHUBPREQ0_DCN_SURF1_TTU_CNTL1 0 0x62f 1 0 2 REFCYC_PER_REQ_DELIVERY_PRE 0 22 regHUBPREQ0_DCN_CUR0_TTU_CNTL0 0 0x630 3 0 2 REFCYC_PER_REQ_DELIVERY 0 22 QoS_LEVEL_FIXED 24 27 QoS_RAMP_DISABLE 28 28 regHUBPREQ0_DCN_CUR0_TTU_CNTL1 0 0x631 1 0 2 REFCYC_PER_REQ_DELIVERY_PRE 0 22 regHUBPREQ0_DCN_CUR1_TTU_CNTL0 0 0x632 3 0 2 REFCYC_PER_REQ_DELIVERY 0 22 QoS_LEVEL_FIXED 24 27 QoS_RAMP_DISABLE 28 28 regHUBPREQ0_DCN_CUR1_TTU_CNTL1 0 0x633 1 0 2 REFCYC_PER_REQ_DELIVERY_PRE 0 22 regHUBPREQ0_DCN_DMDATA_VM_CNTL 0 0x634 7 0 2 REFCYC_PER_VM_DMDATA 0 15 DMDATA_VM_FAULT_STATUS 16 19 DMDATA_VM_FAULT_STATUS_CLEAR 20 20 DMDATA_VM_UNDERFLOW_STATUS 24 24 DMDATA_VM_LATE_STATUS 25 25 DMDATA_VM_UNDERFLOW_STATUS_CLEAR 26 26 DMDATA_VM_DONE 31 31 regHUBPREQ0_DCN_VM_SYSTEM_APERTURE_LOW_ADDR 0 0x635 1 0 2 MC_VM_SYSTEM_APERTURE_LOW_ADDR 0 29 regHUBPREQ0_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR 0 0x636 1 0 2 MC_VM_SYSTEM_APERTURE_HIGH_ADDR 0 29 regHUBPREQ0_DCN_VM_MX_L1_TLB_CNTL 0 0x643 4 0 2 ENABLE_L1_TLB 0 0 SYSTEM_ACCESS_MODE 3 4 SYSTEM_APERTURE_UNMAPPED_ACCESS 5 5 ENABLE_ADVANCED_DRIVER_MODEL 6 6 regHUBPREQ0_BLANK_OFFSET_0 0 0x644 2 0 2 REFCYC_H_BLANK_END 0 12 DLG_V_BLANK_END 16 30 regHUBPREQ0_BLANK_OFFSET_1 0 0x645 1 0 2 MIN_DST_Y_NEXT_START 0 17 regHUBPREQ0_DST_DIMENSIONS 0 0x646 1 0 2 REFCYC_PER_HTOTAL 0 20 regHUBPREQ0_DST_AFTER_SCALER 0 0x647 2 0 2 REFCYC_X_AFTER_SCALER 0 12 DST_Y_AFTER_SCALER 16 18 regHUBPREQ0_PREFETCH_SETTINGS 0 0x648 2 0 2 VRATIO_PREFETCH 0 21 DST_Y_PREFETCH 24 31 regHUBPREQ0_PREFETCH_SETTINGS_C 0 0x649 1 0 2 VRATIO_PREFETCH_C 0 21 regHUBPREQ0_VBLANK_PARAMETERS_0 0 0x64a 2 0 2 DST_Y_PER_VM_VBLANK 0 6 DST_Y_PER_ROW_VBLANK 8 13 regHUBPREQ0_VBLANK_PARAMETERS_1 0 0x64b 1 0 2 REFCYC_PER_PTE_GROUP_VBLANK_L 0 22 regHUBPREQ0_VBLANK_PARAMETERS_2 0 0x64c 1 0 2 REFCYC_PER_PTE_GROUP_VBLANK_C 0 22 regHUBPREQ0_VBLANK_PARAMETERS_3 0 0x64d 1 0 2 REFCYC_PER_META_CHUNK_VBLANK_L 0 22 regHUBPREQ0_VBLANK_PARAMETERS_4 0 0x64e 1 0 2 REFCYC_PER_META_CHUNK_VBLANK_C 0 22 regHUBPREQ0_FLIP_PARAMETERS_0 0 0x64f 2 0 2 DST_Y_PER_VM_FLIP 0 6 DST_Y_PER_ROW_FLIP 8 13 regHUBPREQ0_FLIP_PARAMETERS_1 0 0x650 1 0 2 REFCYC_PER_PTE_GROUP_FLIP_L 0 22 regHUBPREQ0_FLIP_PARAMETERS_2 0 0x651 1 0 2 REFCYC_PER_META_CHUNK_FLIP_L 0 22 regHUBPREQ0_NOM_PARAMETERS_0 0 0x652 1 0 2 DST_Y_PER_PTE_ROW_NOM_L 0 16 regHUBPREQ0_NOM_PARAMETERS_1 0 0x653 1 0 2 REFCYC_PER_PTE_GROUP_NOM_L 0 22 regHUBPREQ0_NOM_PARAMETERS_2 0 0x654 1 0 2 DST_Y_PER_PTE_ROW_NOM_C 0 16 regHUBPREQ0_NOM_PARAMETERS_3 0 0x655 1 0 2 REFCYC_PER_PTE_GROUP_NOM_C 0 22 regHUBPREQ0_NOM_PARAMETERS_4 0 0x656 1 0 2 DST_Y_PER_META_ROW_NOM_L 0 16 regHUBPREQ0_NOM_PARAMETERS_5 0 0x657 1 0 2 REFCYC_PER_META_CHUNK_NOM_L 0 22 regHUBPREQ0_NOM_PARAMETERS_6 0 0x658 1 0 2 DST_Y_PER_META_ROW_NOM_C 0 16 regHUBPREQ0_NOM_PARAMETERS_7 0 0x659 1 0 2 REFCYC_PER_META_CHUNK_NOM_C 0 22 regHUBPREQ0_PER_LINE_DELIVERY_PRE 0 0x65a 2 0 2 REFCYC_PER_LINE_DELIVERY_PRE_L 0 12 REFCYC_PER_LINE_DELIVERY_PRE_C 16 28 regHUBPREQ0_PER_LINE_DELIVERY 0 0x65b 2 0 2 REFCYC_PER_LINE_DELIVERY_L 0 12 REFCYC_PER_LINE_DELIVERY_C 16 28 regHUBPREQ0_CURSOR_SETTINGS 0 0x65c 4 0 2 CURSOR0_DST_Y_OFFSET 0 7 CURSOR0_CHUNK_HDL_ADJUST 8 9 CURSOR1_DST_Y_OFFSET 16 23 CURSOR1_CHUNK_HDL_ADJUST 24 25 regHUBPREQ0_REF_FREQ_TO_PIX_FREQ 0 0x65d 1 0 2 REF_FREQ_TO_PIX_FREQ 0 20 regHUBPREQ0_DST_Y_DELTA_DRQ_LIMIT 0 0x65e 1 0 2 DST_Y_DELTA_DRQ_LIMIT 0 14 regHUBPREQ0_HUBPREQ_MEM_PWR_CTRL 0 0x65f 8 0 2 REQ_DPTE_MEM_PWR_FORCE 0 1 REQ_DPTE_MEM_PWR_DIS 2 2 REQ_MPTE_MEM_PWR_FORCE 4 5 REQ_MPTE_MEM_PWR_DIS 6 6 REQ_META_MEM_PWR_FORCE 8 9 REQ_META_MEM_PWR_DIS 10 10 REQ_PDE_MEM_PWR_FORCE 12 13 REQ_PDE_MEM_PWR_DIS 14 14 regHUBPREQ0_HUBPREQ_MEM_PWR_STATUS 0 0x660 4 0 2 REQ_DPTE_MEM_PWR_STATE 0 1 REQ_MPTE_MEM_PWR_STATE 2 3 REQ_META_MEM_PWR_STATE 4 5 REQ_PDE_MEM_PWR_STATE 6 7 regHUBPREQ0_VBLANK_PARAMETERS_5 0 0x663 1 0 2 REFCYC_PER_VM_GROUP_VBLANK 0 22 regHUBPREQ0_VBLANK_PARAMETERS_6 0 0x664 1 0 2 REFCYC_PER_VM_REQ_VBLANK 0 22 regHUBPREQ0_FLIP_PARAMETERS_3 0 0x665 1 0 2 REFCYC_PER_VM_GROUP_FLIP 0 22 regHUBPREQ0_FLIP_PARAMETERS_4 0 0x666 1 0 2 REFCYC_PER_VM_REQ_FLIP 0 22 regHUBPREQ0_FLIP_PARAMETERS_5 0 0x667 1 0 2 REFCYC_PER_PTE_GROUP_FLIP_C 0 22 regHUBPREQ0_FLIP_PARAMETERS_6 0 0x668 1 0 2 REFCYC_PER_META_CHUNK_FLIP_C 0 22 regHUBPRET0_HUBPRET_CONTROL 0 0x66c 7 0 2 DET_BUF_PLANE1_BASE_ADDRESS 4 12 PACK_3TO2_ELEMENT_DISABLE 15 15 CROSSBAR_SRC_ALPHA 16 17 CROSSBAR_SRC_Y_G 18 19 CROSSBAR_SRC_CB_B 20 21 CROSSBAR_SRC_CR_R 22 23 HUBPRET_CONTROL_SPARE 24 31 regHUBPRET0_HUBPRET_MEM_PWR_CTRL 0 0x66d 5 0 2 DMROB_MEM_PWR_FORCE 8 9 DMROB_MEM_PWR_DIS 10 10 PIXCDC_MEM_PWR_FORCE 16 17 PIXCDC_MEM_PWR_DIS 18 18 PIXCDC_MEM_PWR_LS_MODE 20 21 regHUBPRET0_HUBPRET_MEM_PWR_STATUS 0 0x66e 2 0 2 DMROB_MEM_PWR_STATE 2 3 PIXCDC_MEM_PWR_STATE 4 5 regHUBPRET0_HUBPRET_READ_LINE_CTRL0 0 0x66f 2 0 2 PIPE_READ_LINE_INTERVAL_IN_NONACTIVE 0 15 PIPE_READ_LINE_VBLANK_MAXIMUM 16 29 regHUBPRET0_HUBPRET_READ_LINE_CTRL1 0 0x670 2 0 2 PIPE_READ_LINE_REPORTED_WHEN_REQ_DISABLED 0 13 HUBPRET_READ_LINE_CTRL1_SPARE 16 31 regHUBPRET0_HUBPRET_READ_LINE0 0 0x671 2 0 2 PIPE_READ_LINE0_START 0 13 PIPE_READ_LINE0_END 16 29 regHUBPRET0_HUBPRET_READ_LINE1 0 0x672 2 0 2 PIPE_READ_LINE1_START 0 13 PIPE_READ_LINE1_END 16 29 regHUBPRET0_HUBPRET_INTERRUPT 0 0x673 15 0 2 PIPE_VBLANK_INT_MASK 0 0 PIPE_READ_LINE0_INT_MASK 1 1 PIPE_READ_LINE1_INT_MASK 2 2 PIPE_VBLANK_INT_TYPE 4 4 PIPE_READ_LINE0_INT_TYPE 5 5 PIPE_READ_LINE1_INT_TYPE 6 6 PIPE_VBLANK_INT_CLEAR 8 8 PIPE_READ_LINE0_INT_CLEAR 9 9 PIPE_READ_LINE1_INT_CLEAR 10 10 PIPE_VBLANK_STATUS 12 12 PIPE_READ_LINE0_STATUS 13 13 PIPE_READ_LINE1_STATUS 14 14 PIPE_VBLANK_INT_STATUS 16 16 PIPE_READ_LINE0_INT_STATUS 17 17 PIPE_READ_LINE1_INT_STATUS 18 18 regHUBPRET0_HUBPRET_READ_LINE_VALUE 0 0x674 2 0 2 PIPE_READ_LINE 0 13 PIPE_READ_LINE_SNAPSHOT 16 29 regHUBPRET0_HUBPRET_READ_LINE_STATUS 0 0x675 5 0 2 PIPE_READ_VBLANK 0 0 PIPE_READ_LINE0_INSIDE 4 4 PIPE_READ_LINE0_OUTSIDE 5 5 PIPE_READ_LINE1_INSIDE 8 8 PIPE_READ_LINE1_OUTSIDE 10 10 regCURSOR0_0_CURSOR_CONTROL 0 0x678 10 0 2 CURSOR_ENABLE 0 0 CURSOR_REQ_MODE 2 2 CURSOR_2X_MAGNIFY 4 4 CURSOR_MODE 8 10 CURSOR_TMZ 12 12 CURSOR_PITCH 16 17 CURSOR_XY_POSITION_ROTATION_AND_MIRRORING_BYPASS 20 20 CURSOR_LINES_PER_CHUNK 24 28 CURSOR_PERFMON_LATENCY_MEASURE_EN 30 30 CURSOR_PERFMON_LATENCY_MEASURE_SEL 31 31 regCURSOR0_0_CURSOR_SURFACE_ADDRESS 0 0x679 1 0 2 CURSOR_SURFACE_ADDRESS 0 31 regCURSOR0_0_CURSOR_SURFACE_ADDRESS_HIGH 0 0x67a 1 0 2 CURSOR_SURFACE_ADDRESS_HIGH 0 15 regCURSOR0_0_CURSOR_SIZE 0 0x67b 2 0 2 CURSOR_HEIGHT 0 8 CURSOR_WIDTH 16 24 regCURSOR0_0_CURSOR_POSITION 0 0x67c 2 0 2 CURSOR_Y_POSITION 0 13 CURSOR_X_POSITION 16 29 regCURSOR0_0_CURSOR_HOT_SPOT 0 0x67d 2 0 2 CURSOR_HOT_SPOT_Y 0 7 CURSOR_HOT_SPOT_X 16 23 regCURSOR0_0_CURSOR_STEREO_CONTROL 0 0x67e 3 0 2 CURSOR_STEREO_EN 0 0 CURSOR_PRIMARY_OFFSET 4 17 CURSOR_SECONDARY_OFFSET 18 31 regCURSOR0_0_CURSOR_DST_OFFSET 0 0x67f 1 0 2 CURSOR_DST_X_OFFSET 0 12 regCURSOR0_0_CURSOR_MEM_PWR_CTRL 0 0x680 3 0 2 CROB_MEM_PWR_FORCE 0 1 CROB_MEM_PWR_DIS 2 2 CROB_MEM_PWR_LS_MODE 4 5 regCURSOR0_0_CURSOR_MEM_PWR_STATUS 0 0x681 1 0 2 CROB_MEM_PWR_STATE 0 1 regCURSOR0_0_DMDATA_ADDRESS_HIGH 0 0x682 2 0 2 DMDATA_ADDRESS_HIGH 0 15 DMDATA_TMZ 30 30 regCURSOR0_0_DMDATA_ADDRESS_LOW 0 0x683 1 0 2 DMDATA_ADDRESS_LOW 0 31 regCURSOR0_0_DMDATA_CNTL 0 0x684 4 0 2 DMDATA_UPDATED 0 0 DMDATA_REPEAT 1 1 DMDATA_MODE 2 2 DMDATA_SIZE 16 27 regCURSOR0_0_DMDATA_QOS_CNTL 0 0x685 3 0 2 DMDATA_QOS_MODE 0 0 DMDATA_QOS_LEVEL 4 7 DMDATA_DL_DELTA 16 31 regCURSOR0_0_DMDATA_STATUS 0 0x686 3 0 2 DMDATA_DONE 0 0 DMDATA_UNDERFLOW 2 2 DMDATA_UNDERFLOW_CLEAR 4 4 regCURSOR0_0_DMDATA_SW_CNTL 0 0x687 3 0 2 DMDATA_SW_UPDATED 0 0 DMDATA_SW_REPEAT 1 1 DMDATA_SW_SIZE 16 27 regCURSOR0_0_DMDATA_SW_DATA 0 0x688 1 0 2 DMDATA_SW_DATA 0 31 regDC_PERFMON7_PERFCOUNTER_CNTL 0 0x69d 11 0 2 PERFCOUNTER_EVENT_SEL 0 8 PERFCOUNTER_CVALUE_SEL 9 11 PERFCOUNTER_INC_MODE 12 14 PERFCOUNTER_HW_CNTL_SEL 15 15 PERFCOUNTER_RUNEN_MODE 16 16 PERFCOUNTER_CNTOFF_START_DIS 22 22 PERFCOUNTER_RESTART_EN 23 23 PERFCOUNTER_INT_EN 24 24 PERFCOUNTER_OFF_MASK 25 25 PERFCOUNTER_ACTIVE 26 26 PERFCOUNTER_CNTL_SEL 29 31 regDC_PERFMON7_PERFCOUNTER_CNTL2 0 0x69e 5 0 2 PERFCOUNTER_COUNTED_VALUE_TYPE 0 1 PERFCOUNTER_HW_STOP1_SEL 2 2 PERFCOUNTER_HW_STOP2_SEL 3 3 PERFCOUNTER_CNTOFF_SEL 8 13 PERFCOUNTER_CNTL2_SEL 29 31 regDC_PERFMON7_PERFCOUNTER_STATE 0 0x69f 16 0 2 PERFCOUNTER_CNT0_STATE 0 1 PERFCOUNTER_STATE_SEL0 2 2 PERFCOUNTER_CNT1_STATE 4 5 PERFCOUNTER_STATE_SEL1 6 6 PERFCOUNTER_CNT2_STATE 8 9 PERFCOUNTER_STATE_SEL2 10 10 PERFCOUNTER_CNT3_STATE 12 13 PERFCOUNTER_STATE_SEL3 14 14 PERFCOUNTER_CNT4_STATE 16 17 PERFCOUNTER_STATE_SEL4 18 18 PERFCOUNTER_CNT5_STATE 20 21 PERFCOUNTER_STATE_SEL5 22 22 PERFCOUNTER_CNT6_STATE 24 25 PERFCOUNTER_STATE_SEL6 26 26 PERFCOUNTER_CNT7_STATE 28 29 PERFCOUNTER_STATE_SEL7 30 30 regDC_PERFMON7_PERFMON_CNTL 0 0x6a0 6 0 2 PERFMON_STATE 0 1 PERFMON_RPT_COUNT 8 27 PERFMON_CNTOFF_AND_OR 28 28 PERFMON_CNTOFF_INT_EN 29 29 PERFMON_CNTOFF_INT_STATUS 30 30 PERFMON_CNTOFF_INT_ACK 31 31 regDC_PERFMON7_PERFMON_CNTL2 0 0x6a1 4 0 2 PERFMON_CNTOFF_INT_TYPE 0 0 PERFMON_CLK_ENABLE 1 1 PERFMON_RUN_ENABLE_START_SEL 2 9 PERFMON_RUN_ENABLE_STOP_SEL 10 17 regDC_PERFMON7_PERFMON_CVALUE_INT_MISC 0 0x6a2 17 0 2 PERFCOUNTER_INT0_STATUS 0 0 PERFCOUNTER_INT1_STATUS 1 1 PERFCOUNTER_INT2_STATUS 2 2 PERFCOUNTER_INT3_STATUS 3 3 PERFCOUNTER_INT4_STATUS 4 4 PERFCOUNTER_INT5_STATUS 5 5 PERFCOUNTER_INT6_STATUS 6 6 PERFCOUNTER_INT7_STATUS 7 7 PERFCOUNTER_INT0_ACK 8 8 PERFCOUNTER_INT1_ACK 9 9 PERFCOUNTER_INT2_ACK 10 10 PERFCOUNTER_INT3_ACK 11 11 PERFCOUNTER_INT4_ACK 12 12 PERFCOUNTER_INT5_ACK 13 13 PERFCOUNTER_INT6_ACK 14 14 PERFCOUNTER_INT7_ACK 15 15 PERFMON_CVALUE_HI 16 31 regDC_PERFMON7_PERFMON_CVALUE_LOW 0 0x6a3 1 0 2 PERFMON_CVALUE_LOW 0 31 regDC_PERFMON7_PERFMON_HI 0 0x6a4 2 0 2 PERFMON_HI 0 15 PERFMON_READ_SEL 29 31 regDC_PERFMON7_PERFMON_LOW 0 0x6a5 1 0 2 PERFMON_LOW 0 31 regHUBP1_DCSURF_SURFACE_CONFIG 0 0x6c1 4 0 2 SURFACE_PIXEL_FORMAT 0 6 ROTATION_ANGLE 8 9 H_MIRROR_EN 10 10 ALPHA_PLANE_EN 11 11 regHUBP1_DCSURF_ADDR_CONFIG 0 0x6c2 4 0 2 NUM_PIPES 0 2 PIPE_INTERLEAVE 6 7 MAX_COMPRESSED_FRAGS 12 13 NUM_PKRS 16 18 regHUBP1_DCSURF_TILING_CONFIG 0 0x6c3 4 0 2 SW_MODE 0 4 DIM_TYPE 7 8 META_LINEAR 9 9 PIPE_ALIGNED 11 11 regHUBP1_DCSURF_PRI_VIEWPORT_START 0 0x6c5 2 0 2 PRI_VIEWPORT_X_START 0 13 PRI_VIEWPORT_Y_START 16 29 regHUBP1_DCSURF_PRI_VIEWPORT_DIMENSION 0 0x6c6 2 0 2 PRI_VIEWPORT_WIDTH 0 13 PRI_VIEWPORT_HEIGHT 16 29 regHUBP1_DCSURF_PRI_VIEWPORT_START_C 0 0x6c7 2 0 2 PRI_VIEWPORT_X_START_C 0 13 PRI_VIEWPORT_Y_START_C 16 29 regHUBP1_DCSURF_PRI_VIEWPORT_DIMENSION_C 0 0x6c8 2 0 2 PRI_VIEWPORT_WIDTH_C 0 13 PRI_VIEWPORT_HEIGHT_C 16 29 regHUBP1_DCSURF_SEC_VIEWPORT_START 0 0x6c9 2 0 2 SEC_VIEWPORT_X_START 0 13 SEC_VIEWPORT_Y_START 16 29 regHUBP1_DCSURF_SEC_VIEWPORT_DIMENSION 0 0x6ca 2 0 2 SEC_VIEWPORT_WIDTH 0 13 SEC_VIEWPORT_HEIGHT 16 29 regHUBP1_DCSURF_SEC_VIEWPORT_START_C 0 0x6cb 2 0 2 SEC_VIEWPORT_X_START_C 0 13 SEC_VIEWPORT_Y_START_C 16 29 regHUBP1_DCSURF_SEC_VIEWPORT_DIMENSION_C 0 0x6cc 2 0 2 SEC_VIEWPORT_WIDTH_C 0 13 SEC_VIEWPORT_HEIGHT_C 16 29 regHUBP1_DCHUBP_REQ_SIZE_CONFIG 0 0x6cd 8 0 2 SWATH_HEIGHT 0 2 PTE_ROW_HEIGHT_LINEAR 4 6 CHUNK_SIZE 8 10 MIN_CHUNK_SIZE 11 12 META_CHUNK_SIZE 16 17 MIN_META_CHUNK_SIZE 18 19 DPTE_GROUP_SIZE 20 22 VM_GROUP_SIZE 24 26 regHUBP1_DCHUBP_REQ_SIZE_CONFIG_C 0 0x6ce 7 0 2 SWATH_HEIGHT_C 0 2 PTE_ROW_HEIGHT_LINEAR_C 4 6 CHUNK_SIZE_C 8 10 MIN_CHUNK_SIZE_C 11 12 META_CHUNK_SIZE_C 16 17 MIN_META_CHUNK_SIZE_C 18 19 DPTE_GROUP_SIZE_C 20 22 regHUBP1_DCHUBP_CNTL 0 0x6cf 18 0 2 HUBP_BLANK_EN 0 0 HUBP_NO_OUTSTANDING_REQ 1 1 HUBP_SOFT_RESET 2 2 HUBP_IN_BLANK 3 3 HUBP_VTG_SEL 4 7 HUBP_VREADY_AT_OR_AFTER_VSYNC 8 8 HUBP_DISABLE_STOP_DATA_DURING_VM 9 9 HUBP_UNBOUNDED_REQ_MODE 10 10 HUBP_SEG_ALLOC_ERR_STATUS 11 11 HUBP_TTU_DISABLE 12 12 HUBP_TTU_MODE 13 15 HUBP_XRQ_NO_OUTSTANDING_REQ 16 19 HUBP_TIMEOUT_STATUS 20 23 HUBP_TIMEOUT_THRESHOLD 24 25 HUBP_TIMEOUT_STATUS_CLEAR 26 26 HUBP_TIMEOUT_INTERRUPT_EN 27 27 HUBP_UNDERFLOW_STATUS 28 30 HUBP_UNDERFLOW_CLEAR 31 31 regHUBP1_HUBP_CLK_CNTL 0 0x6d0 10 0 2 HUBP_CLOCK_ENABLE 0 0 HUBP_DISPCLK_R_GATE_DIS 4 4 HUBP_DPPCLK_G_GATE_DIS 8 8 HUBP_DCFCLK_R_GATE_DIS 12 12 HUBP_DCFCLK_G_GATE_DIS 16 16 HUBP_DISPCLK_R_CLOCK_ON 20 20 HUBP_DPPCLK_G_CLOCK_ON 21 21 HUBP_DCFCLK_R_CLOCK_ON 22 22 HUBP_DCFCLK_G_CLOCK_ON 23 23 HUBP_TEST_CLK_SEL 28 31 regHUBP1_DCHUBP_VMPG_CONFIG 0 0x6d1 1 0 2 VMPG_SIZE 0 0 regHUBP1_HUBPREQ_DEBUG_DB 0 0x6d2 1 0 2 HUBPREQ_DEBUG 0 31 regHUBP1_HUBPREQ_DEBUG 0 0x6d3 1 0 2 HUBPREQ_DEBUG 0 31 regHUBP1_HUBP_MEASURE_WIN_CTRL_DCFCLK 0 0x6d7 5 0 2 HUBP_MEASURE_WIN_EN_DCFCLK 0 0 HUBP_MEASURE_WIN_PERIOD_M1_DCFCLK 4 11 HUBP_PERFMON_START_SEL_DCFCLK 12 16 HUBP_PERFMON_STOP_SEL_DCFCLK 20 24 HUBP_MEASURE_WIN_MODE_DCFCLK 28 29 regHUBP1_HUBP_MEASURE_WIN_CTRL_DPPCLK 0 0x6d8 5 0 2 HUBP_MEASURE_WIN_EN_DPPCLK 0 0 HUBP_MEASURE_WIN_SRC_SEL_DPPCLK 1 1 HUBP_MEASURE_WIN_PERIOD_M1_DPPCLK 4 11 HUBP_PERFMON_START_SEL_DPPCLK 12 16 HUBP_PERFMON_STOP_SEL_DPPCLK 20 24 regHUBPREQ1_DCSURF_SURFACE_PITCH 0 0x6e3 2 0 2 PITCH 0 13 META_PITCH 16 29 regHUBPREQ1_DCSURF_SURFACE_PITCH_C 0 0x6e4 2 0 2 PITCH_C 0 13 META_PITCH_C 16 29 regHUBPREQ1_VMID_SETTINGS_0 0 0x6e5 1 0 2 VMID 0 3 regHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS 0 0x6e6 1 0 2 PRIMARY_SURFACE_ADDRESS 0 31 regHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH 0 0x6e7 1 0 2 PRIMARY_SURFACE_ADDRESS_HIGH 0 15 regHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_C 0 0x6e8 1 0 2 PRIMARY_SURFACE_ADDRESS_C 0 31 regHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C 0 0x6e9 1 0 2 PRIMARY_SURFACE_ADDRESS_HIGH_C 0 15 regHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS 0 0x6ea 1 0 2 SECONDARY_SURFACE_ADDRESS 0 31 regHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH 0 0x6eb 1 0 2 SECONDARY_SURFACE_ADDRESS_HIGH 0 15 regHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_C 0 0x6ec 1 0 2 SECONDARY_SURFACE_ADDRESS_C 0 31 regHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C 0 0x6ed 1 0 2 SECONDARY_SURFACE_ADDRESS_HIGH_C 0 15 regHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS 0 0x6ee 1 0 2 PRIMARY_META_SURFACE_ADDRESS 0 31 regHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH 0 0x6ef 1 0 2 PRIMARY_META_SURFACE_ADDRESS_HIGH 0 15 regHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C 0 0x6f0 1 0 2 PRIMARY_META_SURFACE_ADDRESS_C 0 31 regHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C 0 0x6f1 1 0 2 PRIMARY_META_SURFACE_ADDRESS_HIGH_C 0 15 regHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS 0 0x6f2 1 0 2 SECONDARY_META_SURFACE_ADDRESS 0 31 regHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH 0 0x6f3 1 0 2 SECONDARY_META_SURFACE_ADDRESS_HIGH 0 15 regHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C 0 0x6f4 1 0 2 SECONDARY_META_SURFACE_ADDRESS_C 0 31 regHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C 0 0x6f5 1 0 2 SECONDARY_META_SURFACE_ADDRESS_HIGH_C 0 15 regHUBPREQ1_DCSURF_SURFACE_CONTROL 0 0x6f6 14 0 2 PRIMARY_SURFACE_TMZ 0 0 PRIMARY_SURFACE_DCC_EN 1 1 PRIMARY_SURFACE_DCC_IND_BLK 2 3 PRIMARY_SURFACE_TMZ_C 4 4 PRIMARY_SURFACE_DCC_IND_BLK_C 5 6 SECONDARY_SURFACE_TMZ 8 8 SECONDARY_SURFACE_DCC_EN 9 9 SECONDARY_SURFACE_DCC_IND_BLK 10 11 SECONDARY_SURFACE_TMZ_C 12 12 SECONDARY_SURFACE_DCC_IND_BLK_C 13 14 PRIMARY_META_SURFACE_TMZ 16 16 PRIMARY_META_SURFACE_TMZ_C 17 17 SECONDARY_META_SURFACE_TMZ 18 18 SECONDARY_META_SURFACE_TMZ_C 19 19 regHUBPREQ1_DCSURF_FLIP_CONTROL 0 0x6f7 10 0 2 SURFACE_UPDATE_LOCK 0 0 SURFACE_FLIP_TYPE 1 1 SURFACE_FLIP_VUPDATE_SKIP_NUM 4 7 SURFACE_FLIP_PENDING 8 8 HUBPREQ_MASTER_UPDATE_LOCK_STATUS 9 9 SURFACE_FLIP_MODE_FOR_STEREOSYNC 12 13 SURFACE_FLIP_IN_STEREOSYNC 16 16 SURFACE_FLIP_STEREO_SELECT_DISABLE 17 17 SURFACE_FLIP_STEREO_SELECT_POLARITY 18 18 SURFACE_FLIP_PENDING_DELAY 20 29 regHUBPREQ1_DCSURF_FLIP_CONTROL2 0 0x6f8 6 0 2 SURFACE_FLIP_PENDING_MIN_TIME 0 7 SURFACE_GSL_ENABLE 8 8 SURFACE_GSL_MASK 9 9 SURFACE_TRIPLE_BUFFER_ENABLE 10 10 SURFACE_INUSE_RAED_NO_LATCH 12 12 SURFACE_FLIP_EXEC_DEBUG_MODE 31 31 regHUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT 0 0x6fc 10 0 2 SURFACE_FLIP_INT_MASK 0 0 SURFACE_FLIP_INT_TYPE 1 1 SURFACE_FLIP_AWAY_INT_MASK 2 2 SURFACE_FLIP_AWAY_INT_TYPE 3 3 SURFACE_FLIP_CLEAR 8 8 SURFACE_FLIP_AWAY_CLEAR 9 9 SURFACE_FLIP_OCCURRED 16 16 SURFACE_FLIP_INT_STATUS 17 17 SURFACE_FLIP_AWAY_OCCURRED 18 18 SURFACE_FLIP_AWAY_INT_STATUS 19 19 regHUBPREQ1_DCSURF_SURFACE_INUSE 0 0x6fd 1 0 2 SURFACE_INUSE_ADDRESS 0 31 regHUBPREQ1_DCSURF_SURFACE_INUSE_HIGH 0 0x6fe 2 0 2 SURFACE_INUSE_ADDRESS_HIGH 0 15 SURFACE_INUSE_VMID 28 31 regHUBPREQ1_DCSURF_SURFACE_INUSE_C 0 0x6ff 1 0 2 SURFACE_INUSE_ADDRESS_C 0 31 regHUBPREQ1_DCSURF_SURFACE_INUSE_HIGH_C 0 0x700 2 0 2 SURFACE_INUSE_ADDRESS_HIGH_C 0 15 SURFACE_INUSE_VMID_C 28 31 regHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE 0 0x701 1 0 2 SURFACE_EARLIEST_INUSE_ADDRESS 0 31 regHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_HIGH 0 0x702 2 0 2 SURFACE_EARLIEST_INUSE_ADDRESS_HIGH 0 15 SURFACE_EARLIEST_INUSE_VMID 28 31 regHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_C 0 0x703 1 0 2 SURFACE_EARLIEST_INUSE_ADDRESS_C 0 31 regHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C 0 0x704 2 0 2 SURFACE_EARLIEST_INUSE_ADDRESS_HIGH_C 0 15 SURFACE_EARLIEST_INUSE_VMID_C 28 31 regHUBPREQ1_DCN_EXPANSION_MODE 0 0x705 4 0 2 DRQ_EXPANSION_MODE 0 1 CRQ_EXPANSION_MODE 2 3 MRQ_EXPANSION_MODE 4 5 PRQ_EXPANSION_MODE 6 7 regHUBPREQ1_DCN_TTU_QOS_WM 0 0x706 2 0 2 QoS_LEVEL_LOW_WM 0 13 QoS_LEVEL_HIGH_WM 16 29 regHUBPREQ1_DCN_GLOBAL_TTU_CNTL 0 0x707 5 0 2 MIN_TTU_VBLANK 0 23 PIPE_IN_FLUSH_URGENT 24 24 PRQ_MRQ_FLUSH_URGENT 25 25 ROW_TTU_MODE 27 27 QoS_LEVEL_FLIP 28 31 regHUBPREQ1_DCN_SURF0_TTU_CNTL0 0 0x708 3 0 2 REFCYC_PER_REQ_DELIVERY 0 22 QoS_LEVEL_FIXED 24 27 QoS_RAMP_DISABLE 28 28 regHUBPREQ1_DCN_SURF0_TTU_CNTL1 0 0x709 1 0 2 REFCYC_PER_REQ_DELIVERY_PRE 0 22 regHUBPREQ1_DCN_SURF1_TTU_CNTL0 0 0x70a 3 0 2 REFCYC_PER_REQ_DELIVERY 0 22 QoS_LEVEL_FIXED 24 27 QoS_RAMP_DISABLE 28 28 regHUBPREQ1_DCN_SURF1_TTU_CNTL1 0 0x70b 1 0 2 REFCYC_PER_REQ_DELIVERY_PRE 0 22 regHUBPREQ1_DCN_CUR0_TTU_CNTL0 0 0x70c 3 0 2 REFCYC_PER_REQ_DELIVERY 0 22 QoS_LEVEL_FIXED 24 27 QoS_RAMP_DISABLE 28 28 regHUBPREQ1_DCN_CUR0_TTU_CNTL1 0 0x70d 1 0 2 REFCYC_PER_REQ_DELIVERY_PRE 0 22 regHUBPREQ1_DCN_CUR1_TTU_CNTL0 0 0x70e 3 0 2 REFCYC_PER_REQ_DELIVERY 0 22 QoS_LEVEL_FIXED 24 27 QoS_RAMP_DISABLE 28 28 regHUBPREQ1_DCN_CUR1_TTU_CNTL1 0 0x70f 1 0 2 REFCYC_PER_REQ_DELIVERY_PRE 0 22 regHUBPREQ1_DCN_DMDATA_VM_CNTL 0 0x710 7 0 2 REFCYC_PER_VM_DMDATA 0 15 DMDATA_VM_FAULT_STATUS 16 19 DMDATA_VM_FAULT_STATUS_CLEAR 20 20 DMDATA_VM_UNDERFLOW_STATUS 24 24 DMDATA_VM_LATE_STATUS 25 25 DMDATA_VM_UNDERFLOW_STATUS_CLEAR 26 26 DMDATA_VM_DONE 31 31 regHUBPREQ1_DCN_VM_SYSTEM_APERTURE_LOW_ADDR 0 0x711 1 0 2 MC_VM_SYSTEM_APERTURE_LOW_ADDR 0 29 regHUBPREQ1_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR 0 0x712 1 0 2 MC_VM_SYSTEM_APERTURE_HIGH_ADDR 0 29 regHUBPREQ1_DCN_VM_MX_L1_TLB_CNTL 0 0x71f 4 0 2 ENABLE_L1_TLB 0 0 SYSTEM_ACCESS_MODE 3 4 SYSTEM_APERTURE_UNMAPPED_ACCESS 5 5 ENABLE_ADVANCED_DRIVER_MODEL 6 6 regHUBPREQ1_BLANK_OFFSET_0 0 0x720 2 0 2 REFCYC_H_BLANK_END 0 12 DLG_V_BLANK_END 16 30 regHUBPREQ1_BLANK_OFFSET_1 0 0x721 1 0 2 MIN_DST_Y_NEXT_START 0 17 regHUBPREQ1_DST_DIMENSIONS 0 0x722 1 0 2 REFCYC_PER_HTOTAL 0 20 regHUBPREQ1_DST_AFTER_SCALER 0 0x723 2 0 2 REFCYC_X_AFTER_SCALER 0 12 DST_Y_AFTER_SCALER 16 18 regHUBPREQ1_PREFETCH_SETTINGS 0 0x724 2 0 2 VRATIO_PREFETCH 0 21 DST_Y_PREFETCH 24 31 regHUBPREQ1_PREFETCH_SETTINGS_C 0 0x725 1 0 2 VRATIO_PREFETCH_C 0 21 regHUBPREQ1_VBLANK_PARAMETERS_0 0 0x726 2 0 2 DST_Y_PER_VM_VBLANK 0 6 DST_Y_PER_ROW_VBLANK 8 13 regHUBPREQ1_VBLANK_PARAMETERS_1 0 0x727 1 0 2 REFCYC_PER_PTE_GROUP_VBLANK_L 0 22 regHUBPREQ1_VBLANK_PARAMETERS_2 0 0x728 1 0 2 REFCYC_PER_PTE_GROUP_VBLANK_C 0 22 regHUBPREQ1_VBLANK_PARAMETERS_3 0 0x729 1 0 2 REFCYC_PER_META_CHUNK_VBLANK_L 0 22 regHUBPREQ1_VBLANK_PARAMETERS_4 0 0x72a 1 0 2 REFCYC_PER_META_CHUNK_VBLANK_C 0 22 regHUBPREQ1_FLIP_PARAMETERS_0 0 0x72b 2 0 2 DST_Y_PER_VM_FLIP 0 6 DST_Y_PER_ROW_FLIP 8 13 regHUBPREQ1_FLIP_PARAMETERS_1 0 0x72c 1 0 2 REFCYC_PER_PTE_GROUP_FLIP_L 0 22 regHUBPREQ1_FLIP_PARAMETERS_2 0 0x72d 1 0 2 REFCYC_PER_META_CHUNK_FLIP_L 0 22 regHUBPREQ1_NOM_PARAMETERS_0 0 0x72e 1 0 2 DST_Y_PER_PTE_ROW_NOM_L 0 16 regHUBPREQ1_NOM_PARAMETERS_1 0 0x72f 1 0 2 REFCYC_PER_PTE_GROUP_NOM_L 0 22 regHUBPREQ1_NOM_PARAMETERS_2 0 0x730 1 0 2 DST_Y_PER_PTE_ROW_NOM_C 0 16 regHUBPREQ1_NOM_PARAMETERS_3 0 0x731 1 0 2 REFCYC_PER_PTE_GROUP_NOM_C 0 22 regHUBPREQ1_NOM_PARAMETERS_4 0 0x732 1 0 2 DST_Y_PER_META_ROW_NOM_L 0 16 regHUBPREQ1_NOM_PARAMETERS_5 0 0x733 1 0 2 REFCYC_PER_META_CHUNK_NOM_L 0 22 regHUBPREQ1_NOM_PARAMETERS_6 0 0x734 1 0 2 DST_Y_PER_META_ROW_NOM_C 0 16 regHUBPREQ1_NOM_PARAMETERS_7 0 0x735 1 0 2 REFCYC_PER_META_CHUNK_NOM_C 0 22 regHUBPREQ1_PER_LINE_DELIVERY_PRE 0 0x736 2 0 2 REFCYC_PER_LINE_DELIVERY_PRE_L 0 12 REFCYC_PER_LINE_DELIVERY_PRE_C 16 28 regHUBPREQ1_PER_LINE_DELIVERY 0 0x737 2 0 2 REFCYC_PER_LINE_DELIVERY_L 0 12 REFCYC_PER_LINE_DELIVERY_C 16 28 regHUBPREQ1_CURSOR_SETTINGS 0 0x738 4 0 2 CURSOR0_DST_Y_OFFSET 0 7 CURSOR0_CHUNK_HDL_ADJUST 8 9 CURSOR1_DST_Y_OFFSET 16 23 CURSOR1_CHUNK_HDL_ADJUST 24 25 regHUBPREQ1_REF_FREQ_TO_PIX_FREQ 0 0x739 1 0 2 REF_FREQ_TO_PIX_FREQ 0 20 regHUBPREQ1_DST_Y_DELTA_DRQ_LIMIT 0 0x73a 1 0 2 DST_Y_DELTA_DRQ_LIMIT 0 14 regHUBPREQ1_HUBPREQ_MEM_PWR_CTRL 0 0x73b 8 0 2 REQ_DPTE_MEM_PWR_FORCE 0 1 REQ_DPTE_MEM_PWR_DIS 2 2 REQ_MPTE_MEM_PWR_FORCE 4 5 REQ_MPTE_MEM_PWR_DIS 6 6 REQ_META_MEM_PWR_FORCE 8 9 REQ_META_MEM_PWR_DIS 10 10 REQ_PDE_MEM_PWR_FORCE 12 13 REQ_PDE_MEM_PWR_DIS 14 14 regHUBPREQ1_HUBPREQ_MEM_PWR_STATUS 0 0x73c 4 0 2 REQ_DPTE_MEM_PWR_STATE 0 1 REQ_MPTE_MEM_PWR_STATE 2 3 REQ_META_MEM_PWR_STATE 4 5 REQ_PDE_MEM_PWR_STATE 6 7 regHUBPREQ1_VBLANK_PARAMETERS_5 0 0x73f 1 0 2 REFCYC_PER_VM_GROUP_VBLANK 0 22 regHUBPREQ1_VBLANK_PARAMETERS_6 0 0x740 1 0 2 REFCYC_PER_VM_REQ_VBLANK 0 22 regHUBPREQ1_FLIP_PARAMETERS_3 0 0x741 1 0 2 REFCYC_PER_VM_GROUP_FLIP 0 22 regHUBPREQ1_FLIP_PARAMETERS_4 0 0x742 1 0 2 REFCYC_PER_VM_REQ_FLIP 0 22 regHUBPREQ1_FLIP_PARAMETERS_5 0 0x743 1 0 2 REFCYC_PER_PTE_GROUP_FLIP_C 0 22 regHUBPREQ1_FLIP_PARAMETERS_6 0 0x744 1 0 2 REFCYC_PER_META_CHUNK_FLIP_C 0 22 regHUBPRET1_HUBPRET_CONTROL 0 0x748 7 0 2 DET_BUF_PLANE1_BASE_ADDRESS 4 12 PACK_3TO2_ELEMENT_DISABLE 15 15 CROSSBAR_SRC_ALPHA 16 17 CROSSBAR_SRC_Y_G 18 19 CROSSBAR_SRC_CB_B 20 21 CROSSBAR_SRC_CR_R 22 23 HUBPRET_CONTROL_SPARE 24 31 regHUBPRET1_HUBPRET_MEM_PWR_CTRL 0 0x749 5 0 2 DMROB_MEM_PWR_FORCE 8 9 DMROB_MEM_PWR_DIS 10 10 PIXCDC_MEM_PWR_FORCE 16 17 PIXCDC_MEM_PWR_DIS 18 18 PIXCDC_MEM_PWR_LS_MODE 20 21 regHUBPRET1_HUBPRET_MEM_PWR_STATUS 0 0x74a 2 0 2 DMROB_MEM_PWR_STATE 2 3 PIXCDC_MEM_PWR_STATE 4 5 regHUBPRET1_HUBPRET_READ_LINE_CTRL0 0 0x74b 2 0 2 PIPE_READ_LINE_INTERVAL_IN_NONACTIVE 0 15 PIPE_READ_LINE_VBLANK_MAXIMUM 16 29 regHUBPRET1_HUBPRET_READ_LINE_CTRL1 0 0x74c 2 0 2 PIPE_READ_LINE_REPORTED_WHEN_REQ_DISABLED 0 13 HUBPRET_READ_LINE_CTRL1_SPARE 16 31 regHUBPRET1_HUBPRET_READ_LINE0 0 0x74d 2 0 2 PIPE_READ_LINE0_START 0 13 PIPE_READ_LINE0_END 16 29 regHUBPRET1_HUBPRET_READ_LINE1 0 0x74e 2 0 2 PIPE_READ_LINE1_START 0 13 PIPE_READ_LINE1_END 16 29 regHUBPRET1_HUBPRET_INTERRUPT 0 0x74f 15 0 2 PIPE_VBLANK_INT_MASK 0 0 PIPE_READ_LINE0_INT_MASK 1 1 PIPE_READ_LINE1_INT_MASK 2 2 PIPE_VBLANK_INT_TYPE 4 4 PIPE_READ_LINE0_INT_TYPE 5 5 PIPE_READ_LINE1_INT_TYPE 6 6 PIPE_VBLANK_INT_CLEAR 8 8 PIPE_READ_LINE0_INT_CLEAR 9 9 PIPE_READ_LINE1_INT_CLEAR 10 10 PIPE_VBLANK_STATUS 12 12 PIPE_READ_LINE0_STATUS 13 13 PIPE_READ_LINE1_STATUS 14 14 PIPE_VBLANK_INT_STATUS 16 16 PIPE_READ_LINE0_INT_STATUS 17 17 PIPE_READ_LINE1_INT_STATUS 18 18 regHUBPRET1_HUBPRET_READ_LINE_VALUE 0 0x750 2 0 2 PIPE_READ_LINE 0 13 PIPE_READ_LINE_SNAPSHOT 16 29 regHUBPRET1_HUBPRET_READ_LINE_STATUS 0 0x751 5 0 2 PIPE_READ_VBLANK 0 0 PIPE_READ_LINE0_INSIDE 4 4 PIPE_READ_LINE0_OUTSIDE 5 5 PIPE_READ_LINE1_INSIDE 8 8 PIPE_READ_LINE1_OUTSIDE 10 10 regCURSOR0_1_CURSOR_CONTROL 0 0x754 10 0 2 CURSOR_ENABLE 0 0 CURSOR_REQ_MODE 2 2 CURSOR_2X_MAGNIFY 4 4 CURSOR_MODE 8 10 CURSOR_TMZ 12 12 CURSOR_PITCH 16 17 CURSOR_XY_POSITION_ROTATION_AND_MIRRORING_BYPASS 20 20 CURSOR_LINES_PER_CHUNK 24 28 CURSOR_PERFMON_LATENCY_MEASURE_EN 30 30 CURSOR_PERFMON_LATENCY_MEASURE_SEL 31 31 regCURSOR0_1_CURSOR_SURFACE_ADDRESS 0 0x755 1 0 2 CURSOR_SURFACE_ADDRESS 0 31 regCURSOR0_1_CURSOR_SURFACE_ADDRESS_HIGH 0 0x756 1 0 2 CURSOR_SURFACE_ADDRESS_HIGH 0 15 regCURSOR0_1_CURSOR_SIZE 0 0x757 2 0 2 CURSOR_HEIGHT 0 8 CURSOR_WIDTH 16 24 regCURSOR0_1_CURSOR_POSITION 0 0x758 2 0 2 CURSOR_Y_POSITION 0 13 CURSOR_X_POSITION 16 29 regCURSOR0_1_CURSOR_HOT_SPOT 0 0x759 2 0 2 CURSOR_HOT_SPOT_Y 0 7 CURSOR_HOT_SPOT_X 16 23 regCURSOR0_1_CURSOR_STEREO_CONTROL 0 0x75a 3 0 2 CURSOR_STEREO_EN 0 0 CURSOR_PRIMARY_OFFSET 4 17 CURSOR_SECONDARY_OFFSET 18 31 regCURSOR0_1_CURSOR_DST_OFFSET 0 0x75b 1 0 2 CURSOR_DST_X_OFFSET 0 12 regCURSOR0_1_CURSOR_MEM_PWR_CTRL 0 0x75c 3 0 2 CROB_MEM_PWR_FORCE 0 1 CROB_MEM_PWR_DIS 2 2 CROB_MEM_PWR_LS_MODE 4 5 regCURSOR0_1_CURSOR_MEM_PWR_STATUS 0 0x75d 1 0 2 CROB_MEM_PWR_STATE 0 1 regCURSOR0_1_DMDATA_ADDRESS_HIGH 0 0x75e 2 0 2 DMDATA_ADDRESS_HIGH 0 15 DMDATA_TMZ 30 30 regCURSOR0_1_DMDATA_ADDRESS_LOW 0 0x75f 1 0 2 DMDATA_ADDRESS_LOW 0 31 regCURSOR0_1_DMDATA_CNTL 0 0x760 4 0 2 DMDATA_UPDATED 0 0 DMDATA_REPEAT 1 1 DMDATA_MODE 2 2 DMDATA_SIZE 16 27 regCURSOR0_1_DMDATA_QOS_CNTL 0 0x761 3 0 2 DMDATA_QOS_MODE 0 0 DMDATA_QOS_LEVEL 4 7 DMDATA_DL_DELTA 16 31 regCURSOR0_1_DMDATA_STATUS 0 0x762 3 0 2 DMDATA_DONE 0 0 DMDATA_UNDERFLOW 2 2 DMDATA_UNDERFLOW_CLEAR 4 4 regCURSOR0_1_DMDATA_SW_CNTL 0 0x763 3 0 2 DMDATA_SW_UPDATED 0 0 DMDATA_SW_REPEAT 1 1 DMDATA_SW_SIZE 16 27 regCURSOR0_1_DMDATA_SW_DATA 0 0x764 1 0 2 DMDATA_SW_DATA 0 31 regDC_PERFMON8_PERFCOUNTER_CNTL 0 0x779 11 0 2 PERFCOUNTER_EVENT_SEL 0 8 PERFCOUNTER_CVALUE_SEL 9 11 PERFCOUNTER_INC_MODE 12 14 PERFCOUNTER_HW_CNTL_SEL 15 15 PERFCOUNTER_RUNEN_MODE 16 16 PERFCOUNTER_CNTOFF_START_DIS 22 22 PERFCOUNTER_RESTART_EN 23 23 PERFCOUNTER_INT_EN 24 24 PERFCOUNTER_OFF_MASK 25 25 PERFCOUNTER_ACTIVE 26 26 PERFCOUNTER_CNTL_SEL 29 31 regDC_PERFMON8_PERFCOUNTER_CNTL2 0 0x77a 5 0 2 PERFCOUNTER_COUNTED_VALUE_TYPE 0 1 PERFCOUNTER_HW_STOP1_SEL 2 2 PERFCOUNTER_HW_STOP2_SEL 3 3 PERFCOUNTER_CNTOFF_SEL 8 13 PERFCOUNTER_CNTL2_SEL 29 31 regDC_PERFMON8_PERFCOUNTER_STATE 0 0x77b 16 0 2 PERFCOUNTER_CNT0_STATE 0 1 PERFCOUNTER_STATE_SEL0 2 2 PERFCOUNTER_CNT1_STATE 4 5 PERFCOUNTER_STATE_SEL1 6 6 PERFCOUNTER_CNT2_STATE 8 9 PERFCOUNTER_STATE_SEL2 10 10 PERFCOUNTER_CNT3_STATE 12 13 PERFCOUNTER_STATE_SEL3 14 14 PERFCOUNTER_CNT4_STATE 16 17 PERFCOUNTER_STATE_SEL4 18 18 PERFCOUNTER_CNT5_STATE 20 21 PERFCOUNTER_STATE_SEL5 22 22 PERFCOUNTER_CNT6_STATE 24 25 PERFCOUNTER_STATE_SEL6 26 26 PERFCOUNTER_CNT7_STATE 28 29 PERFCOUNTER_STATE_SEL7 30 30 regDC_PERFMON8_PERFMON_CNTL 0 0x77c 6 0 2 PERFMON_STATE 0 1 PERFMON_RPT_COUNT 8 27 PERFMON_CNTOFF_AND_OR 28 28 PERFMON_CNTOFF_INT_EN 29 29 PERFMON_CNTOFF_INT_STATUS 30 30 PERFMON_CNTOFF_INT_ACK 31 31 regDC_PERFMON8_PERFMON_CNTL2 0 0x77d 4 0 2 PERFMON_CNTOFF_INT_TYPE 0 0 PERFMON_CLK_ENABLE 1 1 PERFMON_RUN_ENABLE_START_SEL 2 9 PERFMON_RUN_ENABLE_STOP_SEL 10 17 regDC_PERFMON8_PERFMON_CVALUE_INT_MISC 0 0x77e 17 0 2 PERFCOUNTER_INT0_STATUS 0 0 PERFCOUNTER_INT1_STATUS 1 1 PERFCOUNTER_INT2_STATUS 2 2 PERFCOUNTER_INT3_STATUS 3 3 PERFCOUNTER_INT4_STATUS 4 4 PERFCOUNTER_INT5_STATUS 5 5 PERFCOUNTER_INT6_STATUS 6 6 PERFCOUNTER_INT7_STATUS 7 7 PERFCOUNTER_INT0_ACK 8 8 PERFCOUNTER_INT1_ACK 9 9 PERFCOUNTER_INT2_ACK 10 10 PERFCOUNTER_INT3_ACK 11 11 PERFCOUNTER_INT4_ACK 12 12 PERFCOUNTER_INT5_ACK 13 13 PERFCOUNTER_INT6_ACK 14 14 PERFCOUNTER_INT7_ACK 15 15 PERFMON_CVALUE_HI 16 31 regDC_PERFMON8_PERFMON_CVALUE_LOW 0 0x77f 1 0 2 PERFMON_CVALUE_LOW 0 31 regDC_PERFMON8_PERFMON_HI 0 0x780 2 0 2 PERFMON_HI 0 15 PERFMON_READ_SEL 29 31 regDC_PERFMON8_PERFMON_LOW 0 0x781 1 0 2 PERFMON_LOW 0 31 regHUBP2_DCSURF_SURFACE_CONFIG 0 0x79d 4 0 2 SURFACE_PIXEL_FORMAT 0 6 ROTATION_ANGLE 8 9 H_MIRROR_EN 10 10 ALPHA_PLANE_EN 11 11 regHUBP2_DCSURF_ADDR_CONFIG 0 0x79e 4 0 2 NUM_PIPES 0 2 PIPE_INTERLEAVE 6 7 MAX_COMPRESSED_FRAGS 12 13 NUM_PKRS 16 18 regHUBP2_DCSURF_TILING_CONFIG 0 0x79f 4 0 2 SW_MODE 0 4 DIM_TYPE 7 8 META_LINEAR 9 9 PIPE_ALIGNED 11 11 regHUBP2_DCSURF_PRI_VIEWPORT_START 0 0x7a1 2 0 2 PRI_VIEWPORT_X_START 0 13 PRI_VIEWPORT_Y_START 16 29 regHUBP2_DCSURF_PRI_VIEWPORT_DIMENSION 0 0x7a2 2 0 2 PRI_VIEWPORT_WIDTH 0 13 PRI_VIEWPORT_HEIGHT 16 29 regHUBP2_DCSURF_PRI_VIEWPORT_START_C 0 0x7a3 2 0 2 PRI_VIEWPORT_X_START_C 0 13 PRI_VIEWPORT_Y_START_C 16 29 regHUBP2_DCSURF_PRI_VIEWPORT_DIMENSION_C 0 0x7a4 2 0 2 PRI_VIEWPORT_WIDTH_C 0 13 PRI_VIEWPORT_HEIGHT_C 16 29 regHUBP2_DCSURF_SEC_VIEWPORT_START 0 0x7a5 2 0 2 SEC_VIEWPORT_X_START 0 13 SEC_VIEWPORT_Y_START 16 29 regHUBP2_DCSURF_SEC_VIEWPORT_DIMENSION 0 0x7a6 2 0 2 SEC_VIEWPORT_WIDTH 0 13 SEC_VIEWPORT_HEIGHT 16 29 regHUBP2_DCSURF_SEC_VIEWPORT_START_C 0 0x7a7 2 0 2 SEC_VIEWPORT_X_START_C 0 13 SEC_VIEWPORT_Y_START_C 16 29 regHUBP2_DCSURF_SEC_VIEWPORT_DIMENSION_C 0 0x7a8 2 0 2 SEC_VIEWPORT_WIDTH_C 0 13 SEC_VIEWPORT_HEIGHT_C 16 29 regHUBP2_DCHUBP_REQ_SIZE_CONFIG 0 0x7a9 8 0 2 SWATH_HEIGHT 0 2 PTE_ROW_HEIGHT_LINEAR 4 6 CHUNK_SIZE 8 10 MIN_CHUNK_SIZE 11 12 META_CHUNK_SIZE 16 17 MIN_META_CHUNK_SIZE 18 19 DPTE_GROUP_SIZE 20 22 VM_GROUP_SIZE 24 26 regHUBP2_DCHUBP_REQ_SIZE_CONFIG_C 0 0x7aa 7 0 2 SWATH_HEIGHT_C 0 2 PTE_ROW_HEIGHT_LINEAR_C 4 6 CHUNK_SIZE_C 8 10 MIN_CHUNK_SIZE_C 11 12 META_CHUNK_SIZE_C 16 17 MIN_META_CHUNK_SIZE_C 18 19 DPTE_GROUP_SIZE_C 20 22 regHUBP2_DCHUBP_CNTL 0 0x7ab 18 0 2 HUBP_BLANK_EN 0 0 HUBP_NO_OUTSTANDING_REQ 1 1 HUBP_SOFT_RESET 2 2 HUBP_IN_BLANK 3 3 HUBP_VTG_SEL 4 7 HUBP_VREADY_AT_OR_AFTER_VSYNC 8 8 HUBP_DISABLE_STOP_DATA_DURING_VM 9 9 HUBP_UNBOUNDED_REQ_MODE 10 10 HUBP_SEG_ALLOC_ERR_STATUS 11 11 HUBP_TTU_DISABLE 12 12 HUBP_TTU_MODE 13 15 HUBP_XRQ_NO_OUTSTANDING_REQ 16 19 HUBP_TIMEOUT_STATUS 20 23 HUBP_TIMEOUT_THRESHOLD 24 25 HUBP_TIMEOUT_STATUS_CLEAR 26 26 HUBP_TIMEOUT_INTERRUPT_EN 27 27 HUBP_UNDERFLOW_STATUS 28 30 HUBP_UNDERFLOW_CLEAR 31 31 regHUBP2_HUBP_CLK_CNTL 0 0x7ac 10 0 2 HUBP_CLOCK_ENABLE 0 0 HUBP_DISPCLK_R_GATE_DIS 4 4 HUBP_DPPCLK_G_GATE_DIS 8 8 HUBP_DCFCLK_R_GATE_DIS 12 12 HUBP_DCFCLK_G_GATE_DIS 16 16 HUBP_DISPCLK_R_CLOCK_ON 20 20 HUBP_DPPCLK_G_CLOCK_ON 21 21 HUBP_DCFCLK_R_CLOCK_ON 22 22 HUBP_DCFCLK_G_CLOCK_ON 23 23 HUBP_TEST_CLK_SEL 28 31 regHUBP2_DCHUBP_VMPG_CONFIG 0 0x7ad 1 0 2 VMPG_SIZE 0 0 regHUBP2_HUBPREQ_DEBUG_DB 0 0x7ae 1 0 2 HUBPREQ_DEBUG 0 31 regHUBP2_HUBPREQ_DEBUG 0 0x7af 1 0 2 HUBPREQ_DEBUG 0 31 regHUBP2_HUBP_MEASURE_WIN_CTRL_DCFCLK 0 0x7b3 5 0 2 HUBP_MEASURE_WIN_EN_DCFCLK 0 0 HUBP_MEASURE_WIN_PERIOD_M1_DCFCLK 4 11 HUBP_PERFMON_START_SEL_DCFCLK 12 16 HUBP_PERFMON_STOP_SEL_DCFCLK 20 24 HUBP_MEASURE_WIN_MODE_DCFCLK 28 29 regHUBP2_HUBP_MEASURE_WIN_CTRL_DPPCLK 0 0x7b4 5 0 2 HUBP_MEASURE_WIN_EN_DPPCLK 0 0 HUBP_MEASURE_WIN_SRC_SEL_DPPCLK 1 1 HUBP_MEASURE_WIN_PERIOD_M1_DPPCLK 4 11 HUBP_PERFMON_START_SEL_DPPCLK 12 16 HUBP_PERFMON_STOP_SEL_DPPCLK 20 24 regHUBPREQ2_DCSURF_SURFACE_PITCH 0 0x7bf 2 0 2 PITCH 0 13 META_PITCH 16 29 regHUBPREQ2_DCSURF_SURFACE_PITCH_C 0 0x7c0 2 0 2 PITCH_C 0 13 META_PITCH_C 16 29 regHUBPREQ2_VMID_SETTINGS_0 0 0x7c1 1 0 2 VMID 0 3 regHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS 0 0x7c2 1 0 2 PRIMARY_SURFACE_ADDRESS 0 31 regHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH 0 0x7c3 1 0 2 PRIMARY_SURFACE_ADDRESS_HIGH 0 15 regHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_C 0 0x7c4 1 0 2 PRIMARY_SURFACE_ADDRESS_C 0 31 regHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C 0 0x7c5 1 0 2 PRIMARY_SURFACE_ADDRESS_HIGH_C 0 15 regHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS 0 0x7c6 1 0 2 SECONDARY_SURFACE_ADDRESS 0 31 regHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH 0 0x7c7 1 0 2 SECONDARY_SURFACE_ADDRESS_HIGH 0 15 regHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_C 0 0x7c8 1 0 2 SECONDARY_SURFACE_ADDRESS_C 0 31 regHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C 0 0x7c9 1 0 2 SECONDARY_SURFACE_ADDRESS_HIGH_C 0 15 regHUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS 0 0x7ca 1 0 2 PRIMARY_META_SURFACE_ADDRESS 0 31 regHUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH 0 0x7cb 1 0 2 PRIMARY_META_SURFACE_ADDRESS_HIGH 0 15 regHUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C 0 0x7cc 1 0 2 PRIMARY_META_SURFACE_ADDRESS_C 0 31 regHUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C 0 0x7cd 1 0 2 PRIMARY_META_SURFACE_ADDRESS_HIGH_C 0 15 regHUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS 0 0x7ce 1 0 2 SECONDARY_META_SURFACE_ADDRESS 0 31 regHUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH 0 0x7cf 1 0 2 SECONDARY_META_SURFACE_ADDRESS_HIGH 0 15 regHUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C 0 0x7d0 1 0 2 SECONDARY_META_SURFACE_ADDRESS_C 0 31 regHUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C 0 0x7d1 1 0 2 SECONDARY_META_SURFACE_ADDRESS_HIGH_C 0 15 regHUBPREQ2_DCSURF_SURFACE_CONTROL 0 0x7d2 14 0 2 PRIMARY_SURFACE_TMZ 0 0 PRIMARY_SURFACE_DCC_EN 1 1 PRIMARY_SURFACE_DCC_IND_BLK 2 3 PRIMARY_SURFACE_TMZ_C 4 4 PRIMARY_SURFACE_DCC_IND_BLK_C 5 6 SECONDARY_SURFACE_TMZ 8 8 SECONDARY_SURFACE_DCC_EN 9 9 SECONDARY_SURFACE_DCC_IND_BLK 10 11 SECONDARY_SURFACE_TMZ_C 12 12 SECONDARY_SURFACE_DCC_IND_BLK_C 13 14 PRIMARY_META_SURFACE_TMZ 16 16 PRIMARY_META_SURFACE_TMZ_C 17 17 SECONDARY_META_SURFACE_TMZ 18 18 SECONDARY_META_SURFACE_TMZ_C 19 19 regHUBPREQ2_DCSURF_FLIP_CONTROL 0 0x7d3 10 0 2 SURFACE_UPDATE_LOCK 0 0 SURFACE_FLIP_TYPE 1 1 SURFACE_FLIP_VUPDATE_SKIP_NUM 4 7 SURFACE_FLIP_PENDING 8 8 HUBPREQ_MASTER_UPDATE_LOCK_STATUS 9 9 SURFACE_FLIP_MODE_FOR_STEREOSYNC 12 13 SURFACE_FLIP_IN_STEREOSYNC 16 16 SURFACE_FLIP_STEREO_SELECT_DISABLE 17 17 SURFACE_FLIP_STEREO_SELECT_POLARITY 18 18 SURFACE_FLIP_PENDING_DELAY 20 29 regHUBPREQ2_DCSURF_FLIP_CONTROL2 0 0x7d4 6 0 2 SURFACE_FLIP_PENDING_MIN_TIME 0 7 SURFACE_GSL_ENABLE 8 8 SURFACE_GSL_MASK 9 9 SURFACE_TRIPLE_BUFFER_ENABLE 10 10 SURFACE_INUSE_RAED_NO_LATCH 12 12 SURFACE_FLIP_EXEC_DEBUG_MODE 31 31 regHUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT 0 0x7d8 10 0 2 SURFACE_FLIP_INT_MASK 0 0 SURFACE_FLIP_INT_TYPE 1 1 SURFACE_FLIP_AWAY_INT_MASK 2 2 SURFACE_FLIP_AWAY_INT_TYPE 3 3 SURFACE_FLIP_CLEAR 8 8 SURFACE_FLIP_AWAY_CLEAR 9 9 SURFACE_FLIP_OCCURRED 16 16 SURFACE_FLIP_INT_STATUS 17 17 SURFACE_FLIP_AWAY_OCCURRED 18 18 SURFACE_FLIP_AWAY_INT_STATUS 19 19 regHUBPREQ2_DCSURF_SURFACE_INUSE 0 0x7d9 1 0 2 SURFACE_INUSE_ADDRESS 0 31 regHUBPREQ2_DCSURF_SURFACE_INUSE_HIGH 0 0x7da 2 0 2 SURFACE_INUSE_ADDRESS_HIGH 0 15 SURFACE_INUSE_VMID 28 31 regHUBPREQ2_DCSURF_SURFACE_INUSE_C 0 0x7db 1 0 2 SURFACE_INUSE_ADDRESS_C 0 31 regHUBPREQ2_DCSURF_SURFACE_INUSE_HIGH_C 0 0x7dc 2 0 2 SURFACE_INUSE_ADDRESS_HIGH_C 0 15 SURFACE_INUSE_VMID_C 28 31 regHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE 0 0x7dd 1 0 2 SURFACE_EARLIEST_INUSE_ADDRESS 0 31 regHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_HIGH 0 0x7de 2 0 2 SURFACE_EARLIEST_INUSE_ADDRESS_HIGH 0 15 SURFACE_EARLIEST_INUSE_VMID 28 31 regHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_C 0 0x7df 1 0 2 SURFACE_EARLIEST_INUSE_ADDRESS_C 0 31 regHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C 0 0x7e0 2 0 2 SURFACE_EARLIEST_INUSE_ADDRESS_HIGH_C 0 15 SURFACE_EARLIEST_INUSE_VMID_C 28 31 regHUBPREQ2_DCN_EXPANSION_MODE 0 0x7e1 4 0 2 DRQ_EXPANSION_MODE 0 1 CRQ_EXPANSION_MODE 2 3 MRQ_EXPANSION_MODE 4 5 PRQ_EXPANSION_MODE 6 7 regHUBPREQ2_DCN_TTU_QOS_WM 0 0x7e2 2 0 2 QoS_LEVEL_LOW_WM 0 13 QoS_LEVEL_HIGH_WM 16 29 regHUBPREQ2_DCN_GLOBAL_TTU_CNTL 0 0x7e3 5 0 2 MIN_TTU_VBLANK 0 23 PIPE_IN_FLUSH_URGENT 24 24 PRQ_MRQ_FLUSH_URGENT 25 25 ROW_TTU_MODE 27 27 QoS_LEVEL_FLIP 28 31 regHUBPREQ2_DCN_SURF0_TTU_CNTL0 0 0x7e4 3 0 2 REFCYC_PER_REQ_DELIVERY 0 22 QoS_LEVEL_FIXED 24 27 QoS_RAMP_DISABLE 28 28 regHUBPREQ2_DCN_SURF0_TTU_CNTL1 0 0x7e5 1 0 2 REFCYC_PER_REQ_DELIVERY_PRE 0 22 regHUBPREQ2_DCN_SURF1_TTU_CNTL0 0 0x7e6 3 0 2 REFCYC_PER_REQ_DELIVERY 0 22 QoS_LEVEL_FIXED 24 27 QoS_RAMP_DISABLE 28 28 regHUBPREQ2_DCN_SURF1_TTU_CNTL1 0 0x7e7 1 0 2 REFCYC_PER_REQ_DELIVERY_PRE 0 22 regHUBPREQ2_DCN_CUR0_TTU_CNTL0 0 0x7e8 3 0 2 REFCYC_PER_REQ_DELIVERY 0 22 QoS_LEVEL_FIXED 24 27 QoS_RAMP_DISABLE 28 28 regHUBPREQ2_DCN_CUR0_TTU_CNTL1 0 0x7e9 1 0 2 REFCYC_PER_REQ_DELIVERY_PRE 0 22 regHUBPREQ2_DCN_CUR1_TTU_CNTL0 0 0x7ea 3 0 2 REFCYC_PER_REQ_DELIVERY 0 22 QoS_LEVEL_FIXED 24 27 QoS_RAMP_DISABLE 28 28 regHUBPREQ2_DCN_CUR1_TTU_CNTL1 0 0x7eb 1 0 2 REFCYC_PER_REQ_DELIVERY_PRE 0 22 regHUBPREQ2_DCN_DMDATA_VM_CNTL 0 0x7ec 7 0 2 REFCYC_PER_VM_DMDATA 0 15 DMDATA_VM_FAULT_STATUS 16 19 DMDATA_VM_FAULT_STATUS_CLEAR 20 20 DMDATA_VM_UNDERFLOW_STATUS 24 24 DMDATA_VM_LATE_STATUS 25 25 DMDATA_VM_UNDERFLOW_STATUS_CLEAR 26 26 DMDATA_VM_DONE 31 31 regHUBPREQ2_DCN_VM_SYSTEM_APERTURE_LOW_ADDR 0 0x7ed 1 0 2 MC_VM_SYSTEM_APERTURE_LOW_ADDR 0 29 regHUBPREQ2_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR 0 0x7ee 1 0 2 MC_VM_SYSTEM_APERTURE_HIGH_ADDR 0 29 regHUBPREQ2_DCN_VM_MX_L1_TLB_CNTL 0 0x7fb 4 0 2 ENABLE_L1_TLB 0 0 SYSTEM_ACCESS_MODE 3 4 SYSTEM_APERTURE_UNMAPPED_ACCESS 5 5 ENABLE_ADVANCED_DRIVER_MODEL 6 6 regHUBPREQ2_BLANK_OFFSET_0 0 0x7fc 2 0 2 REFCYC_H_BLANK_END 0 12 DLG_V_BLANK_END 16 30 regHUBPREQ2_BLANK_OFFSET_1 0 0x7fd 1 0 2 MIN_DST_Y_NEXT_START 0 17 regHUBPREQ2_DST_DIMENSIONS 0 0x7fe 1 0 2 REFCYC_PER_HTOTAL 0 20 regHUBPREQ2_DST_AFTER_SCALER 0 0x7ff 2 0 2 REFCYC_X_AFTER_SCALER 0 12 DST_Y_AFTER_SCALER 16 18 regHUBPREQ2_PREFETCH_SETTINGS 0 0x800 2 0 2 VRATIO_PREFETCH 0 21 DST_Y_PREFETCH 24 31 regHUBPREQ2_PREFETCH_SETTINGS_C 0 0x801 1 0 2 VRATIO_PREFETCH_C 0 21 regHUBPREQ2_VBLANK_PARAMETERS_0 0 0x802 2 0 2 DST_Y_PER_VM_VBLANK 0 6 DST_Y_PER_ROW_VBLANK 8 13 regHUBPREQ2_VBLANK_PARAMETERS_1 0 0x803 1 0 2 REFCYC_PER_PTE_GROUP_VBLANK_L 0 22 regHUBPREQ2_VBLANK_PARAMETERS_2 0 0x804 1 0 2 REFCYC_PER_PTE_GROUP_VBLANK_C 0 22 regHUBPREQ2_VBLANK_PARAMETERS_3 0 0x805 1 0 2 REFCYC_PER_META_CHUNK_VBLANK_L 0 22 regHUBPREQ2_VBLANK_PARAMETERS_4 0 0x806 1 0 2 REFCYC_PER_META_CHUNK_VBLANK_C 0 22 regHUBPREQ2_FLIP_PARAMETERS_0 0 0x807 2 0 2 DST_Y_PER_VM_FLIP 0 6 DST_Y_PER_ROW_FLIP 8 13 regHUBPREQ2_FLIP_PARAMETERS_1 0 0x808 1 0 2 REFCYC_PER_PTE_GROUP_FLIP_L 0 22 regHUBPREQ2_FLIP_PARAMETERS_2 0 0x809 1 0 2 REFCYC_PER_META_CHUNK_FLIP_L 0 22 regHUBPREQ2_NOM_PARAMETERS_0 0 0x80a 1 0 2 DST_Y_PER_PTE_ROW_NOM_L 0 16 regHUBPREQ2_NOM_PARAMETERS_1 0 0x80b 1 0 2 REFCYC_PER_PTE_GROUP_NOM_L 0 22 regHUBPREQ2_NOM_PARAMETERS_2 0 0x80c 1 0 2 DST_Y_PER_PTE_ROW_NOM_C 0 16 regHUBPREQ2_NOM_PARAMETERS_3 0 0x80d 1 0 2 REFCYC_PER_PTE_GROUP_NOM_C 0 22 regHUBPREQ2_NOM_PARAMETERS_4 0 0x80e 1 0 2 DST_Y_PER_META_ROW_NOM_L 0 16 regHUBPREQ2_NOM_PARAMETERS_5 0 0x80f 1 0 2 REFCYC_PER_META_CHUNK_NOM_L 0 22 regHUBPREQ2_NOM_PARAMETERS_6 0 0x810 1 0 2 DST_Y_PER_META_ROW_NOM_C 0 16 regHUBPREQ2_NOM_PARAMETERS_7 0 0x811 1 0 2 REFCYC_PER_META_CHUNK_NOM_C 0 22 regHUBPREQ2_PER_LINE_DELIVERY_PRE 0 0x812 2 0 2 REFCYC_PER_LINE_DELIVERY_PRE_L 0 12 REFCYC_PER_LINE_DELIVERY_PRE_C 16 28 regHUBPREQ2_PER_LINE_DELIVERY 0 0x813 2 0 2 REFCYC_PER_LINE_DELIVERY_L 0 12 REFCYC_PER_LINE_DELIVERY_C 16 28 regHUBPREQ2_CURSOR_SETTINGS 0 0x814 4 0 2 CURSOR0_DST_Y_OFFSET 0 7 CURSOR0_CHUNK_HDL_ADJUST 8 9 CURSOR1_DST_Y_OFFSET 16 23 CURSOR1_CHUNK_HDL_ADJUST 24 25 regHUBPREQ2_REF_FREQ_TO_PIX_FREQ 0 0x815 1 0 2 REF_FREQ_TO_PIX_FREQ 0 20 regHUBPREQ2_DST_Y_DELTA_DRQ_LIMIT 0 0x816 1 0 2 DST_Y_DELTA_DRQ_LIMIT 0 14 regHUBPREQ2_HUBPREQ_MEM_PWR_CTRL 0 0x817 8 0 2 REQ_DPTE_MEM_PWR_FORCE 0 1 REQ_DPTE_MEM_PWR_DIS 2 2 REQ_MPTE_MEM_PWR_FORCE 4 5 REQ_MPTE_MEM_PWR_DIS 6 6 REQ_META_MEM_PWR_FORCE 8 9 REQ_META_MEM_PWR_DIS 10 10 REQ_PDE_MEM_PWR_FORCE 12 13 REQ_PDE_MEM_PWR_DIS 14 14 regHUBPREQ2_HUBPREQ_MEM_PWR_STATUS 0 0x818 4 0 2 REQ_DPTE_MEM_PWR_STATE 0 1 REQ_MPTE_MEM_PWR_STATE 2 3 REQ_META_MEM_PWR_STATE 4 5 REQ_PDE_MEM_PWR_STATE 6 7 regHUBPREQ2_VBLANK_PARAMETERS_5 0 0x81b 1 0 2 REFCYC_PER_VM_GROUP_VBLANK 0 22 regHUBPREQ2_VBLANK_PARAMETERS_6 0 0x81c 1 0 2 REFCYC_PER_VM_REQ_VBLANK 0 22 regHUBPREQ2_FLIP_PARAMETERS_3 0 0x81d 1 0 2 REFCYC_PER_VM_GROUP_FLIP 0 22 regHUBPREQ2_FLIP_PARAMETERS_4 0 0x81e 1 0 2 REFCYC_PER_VM_REQ_FLIP 0 22 regHUBPREQ2_FLIP_PARAMETERS_5 0 0x81f 1 0 2 REFCYC_PER_PTE_GROUP_FLIP_C 0 22 regHUBPREQ2_FLIP_PARAMETERS_6 0 0x820 1 0 2 REFCYC_PER_META_CHUNK_FLIP_C 0 22 regHUBPRET2_HUBPRET_CONTROL 0 0x824 7 0 2 DET_BUF_PLANE1_BASE_ADDRESS 4 12 PACK_3TO2_ELEMENT_DISABLE 15 15 CROSSBAR_SRC_ALPHA 16 17 CROSSBAR_SRC_Y_G 18 19 CROSSBAR_SRC_CB_B 20 21 CROSSBAR_SRC_CR_R 22 23 HUBPRET_CONTROL_SPARE 24 31 regHUBPRET2_HUBPRET_MEM_PWR_CTRL 0 0x825 5 0 2 DMROB_MEM_PWR_FORCE 8 9 DMROB_MEM_PWR_DIS 10 10 PIXCDC_MEM_PWR_FORCE 16 17 PIXCDC_MEM_PWR_DIS 18 18 PIXCDC_MEM_PWR_LS_MODE 20 21 regHUBPRET2_HUBPRET_MEM_PWR_STATUS 0 0x826 2 0 2 DMROB_MEM_PWR_STATE 2 3 PIXCDC_MEM_PWR_STATE 4 5 regHUBPRET2_HUBPRET_READ_LINE_CTRL0 0 0x827 2 0 2 PIPE_READ_LINE_INTERVAL_IN_NONACTIVE 0 15 PIPE_READ_LINE_VBLANK_MAXIMUM 16 29 regHUBPRET2_HUBPRET_READ_LINE_CTRL1 0 0x828 2 0 2 PIPE_READ_LINE_REPORTED_WHEN_REQ_DISABLED 0 13 HUBPRET_READ_LINE_CTRL1_SPARE 16 31 regHUBPRET2_HUBPRET_READ_LINE0 0 0x829 2 0 2 PIPE_READ_LINE0_START 0 13 PIPE_READ_LINE0_END 16 29 regHUBPRET2_HUBPRET_READ_LINE1 0 0x82a 2 0 2 PIPE_READ_LINE1_START 0 13 PIPE_READ_LINE1_END 16 29 regHUBPRET2_HUBPRET_INTERRUPT 0 0x82b 15 0 2 PIPE_VBLANK_INT_MASK 0 0 PIPE_READ_LINE0_INT_MASK 1 1 PIPE_READ_LINE1_INT_MASK 2 2 PIPE_VBLANK_INT_TYPE 4 4 PIPE_READ_LINE0_INT_TYPE 5 5 PIPE_READ_LINE1_INT_TYPE 6 6 PIPE_VBLANK_INT_CLEAR 8 8 PIPE_READ_LINE0_INT_CLEAR 9 9 PIPE_READ_LINE1_INT_CLEAR 10 10 PIPE_VBLANK_STATUS 12 12 PIPE_READ_LINE0_STATUS 13 13 PIPE_READ_LINE1_STATUS 14 14 PIPE_VBLANK_INT_STATUS 16 16 PIPE_READ_LINE0_INT_STATUS 17 17 PIPE_READ_LINE1_INT_STATUS 18 18 regHUBPRET2_HUBPRET_READ_LINE_VALUE 0 0x82c 2 0 2 PIPE_READ_LINE 0 13 PIPE_READ_LINE_SNAPSHOT 16 29 regHUBPRET2_HUBPRET_READ_LINE_STATUS 0 0x82d 5 0 2 PIPE_READ_VBLANK 0 0 PIPE_READ_LINE0_INSIDE 4 4 PIPE_READ_LINE0_OUTSIDE 5 5 PIPE_READ_LINE1_INSIDE 8 8 PIPE_READ_LINE1_OUTSIDE 10 10 regCURSOR0_2_CURSOR_CONTROL 0 0x830 10 0 2 CURSOR_ENABLE 0 0 CURSOR_REQ_MODE 2 2 CURSOR_2X_MAGNIFY 4 4 CURSOR_MODE 8 10 CURSOR_TMZ 12 12 CURSOR_PITCH 16 17 CURSOR_XY_POSITION_ROTATION_AND_MIRRORING_BYPASS 20 20 CURSOR_LINES_PER_CHUNK 24 28 CURSOR_PERFMON_LATENCY_MEASURE_EN 30 30 CURSOR_PERFMON_LATENCY_MEASURE_SEL 31 31 regCURSOR0_2_CURSOR_SURFACE_ADDRESS 0 0x831 1 0 2 CURSOR_SURFACE_ADDRESS 0 31 regCURSOR0_2_CURSOR_SURFACE_ADDRESS_HIGH 0 0x832 1 0 2 CURSOR_SURFACE_ADDRESS_HIGH 0 15 regCURSOR0_2_CURSOR_SIZE 0 0x833 2 0 2 CURSOR_HEIGHT 0 8 CURSOR_WIDTH 16 24 regCURSOR0_2_CURSOR_POSITION 0 0x834 2 0 2 CURSOR_Y_POSITION 0 13 CURSOR_X_POSITION 16 29 regCURSOR0_2_CURSOR_HOT_SPOT 0 0x835 2 0 2 CURSOR_HOT_SPOT_Y 0 7 CURSOR_HOT_SPOT_X 16 23 regCURSOR0_2_CURSOR_STEREO_CONTROL 0 0x836 3 0 2 CURSOR_STEREO_EN 0 0 CURSOR_PRIMARY_OFFSET 4 17 CURSOR_SECONDARY_OFFSET 18 31 regCURSOR0_2_CURSOR_DST_OFFSET 0 0x837 1 0 2 CURSOR_DST_X_OFFSET 0 12 regCURSOR0_2_CURSOR_MEM_PWR_CTRL 0 0x838 3 0 2 CROB_MEM_PWR_FORCE 0 1 CROB_MEM_PWR_DIS 2 2 CROB_MEM_PWR_LS_MODE 4 5 regCURSOR0_2_CURSOR_MEM_PWR_STATUS 0 0x839 1 0 2 CROB_MEM_PWR_STATE 0 1 regCURSOR0_2_DMDATA_ADDRESS_HIGH 0 0x83a 2 0 2 DMDATA_ADDRESS_HIGH 0 15 DMDATA_TMZ 30 30 regCURSOR0_2_DMDATA_ADDRESS_LOW 0 0x83b 1 0 2 DMDATA_ADDRESS_LOW 0 31 regCURSOR0_2_DMDATA_CNTL 0 0x83c 4 0 2 DMDATA_UPDATED 0 0 DMDATA_REPEAT 1 1 DMDATA_MODE 2 2 DMDATA_SIZE 16 27 regCURSOR0_2_DMDATA_QOS_CNTL 0 0x83d 3 0 2 DMDATA_QOS_MODE 0 0 DMDATA_QOS_LEVEL 4 7 DMDATA_DL_DELTA 16 31 regCURSOR0_2_DMDATA_STATUS 0 0x83e 3 0 2 DMDATA_DONE 0 0 DMDATA_UNDERFLOW 2 2 DMDATA_UNDERFLOW_CLEAR 4 4 regCURSOR0_2_DMDATA_SW_CNTL 0 0x83f 3 0 2 DMDATA_SW_UPDATED 0 0 DMDATA_SW_REPEAT 1 1 DMDATA_SW_SIZE 16 27 regCURSOR0_2_DMDATA_SW_DATA 0 0x840 1 0 2 DMDATA_SW_DATA 0 31 regDC_PERFMON9_PERFCOUNTER_CNTL 0 0x855 11 0 2 PERFCOUNTER_EVENT_SEL 0 8 PERFCOUNTER_CVALUE_SEL 9 11 PERFCOUNTER_INC_MODE 12 14 PERFCOUNTER_HW_CNTL_SEL 15 15 PERFCOUNTER_RUNEN_MODE 16 16 PERFCOUNTER_CNTOFF_START_DIS 22 22 PERFCOUNTER_RESTART_EN 23 23 PERFCOUNTER_INT_EN 24 24 PERFCOUNTER_OFF_MASK 25 25 PERFCOUNTER_ACTIVE 26 26 PERFCOUNTER_CNTL_SEL 29 31 regDC_PERFMON9_PERFCOUNTER_CNTL2 0 0x856 5 0 2 PERFCOUNTER_COUNTED_VALUE_TYPE 0 1 PERFCOUNTER_HW_STOP1_SEL 2 2 PERFCOUNTER_HW_STOP2_SEL 3 3 PERFCOUNTER_CNTOFF_SEL 8 13 PERFCOUNTER_CNTL2_SEL 29 31 regDC_PERFMON9_PERFCOUNTER_STATE 0 0x857 16 0 2 PERFCOUNTER_CNT0_STATE 0 1 PERFCOUNTER_STATE_SEL0 2 2 PERFCOUNTER_CNT1_STATE 4 5 PERFCOUNTER_STATE_SEL1 6 6 PERFCOUNTER_CNT2_STATE 8 9 PERFCOUNTER_STATE_SEL2 10 10 PERFCOUNTER_CNT3_STATE 12 13 PERFCOUNTER_STATE_SEL3 14 14 PERFCOUNTER_CNT4_STATE 16 17 PERFCOUNTER_STATE_SEL4 18 18 PERFCOUNTER_CNT5_STATE 20 21 PERFCOUNTER_STATE_SEL5 22 22 PERFCOUNTER_CNT6_STATE 24 25 PERFCOUNTER_STATE_SEL6 26 26 PERFCOUNTER_CNT7_STATE 28 29 PERFCOUNTER_STATE_SEL7 30 30 regDC_PERFMON9_PERFMON_CNTL 0 0x858 6 0 2 PERFMON_STATE 0 1 PERFMON_RPT_COUNT 8 27 PERFMON_CNTOFF_AND_OR 28 28 PERFMON_CNTOFF_INT_EN 29 29 PERFMON_CNTOFF_INT_STATUS 30 30 PERFMON_CNTOFF_INT_ACK 31 31 regDC_PERFMON9_PERFMON_CNTL2 0 0x859 4 0 2 PERFMON_CNTOFF_INT_TYPE 0 0 PERFMON_CLK_ENABLE 1 1 PERFMON_RUN_ENABLE_START_SEL 2 9 PERFMON_RUN_ENABLE_STOP_SEL 10 17 regDC_PERFMON9_PERFMON_CVALUE_INT_MISC 0 0x85a 17 0 2 PERFCOUNTER_INT0_STATUS 0 0 PERFCOUNTER_INT1_STATUS 1 1 PERFCOUNTER_INT2_STATUS 2 2 PERFCOUNTER_INT3_STATUS 3 3 PERFCOUNTER_INT4_STATUS 4 4 PERFCOUNTER_INT5_STATUS 5 5 PERFCOUNTER_INT6_STATUS 6 6 PERFCOUNTER_INT7_STATUS 7 7 PERFCOUNTER_INT0_ACK 8 8 PERFCOUNTER_INT1_ACK 9 9 PERFCOUNTER_INT2_ACK 10 10 PERFCOUNTER_INT3_ACK 11 11 PERFCOUNTER_INT4_ACK 12 12 PERFCOUNTER_INT5_ACK 13 13 PERFCOUNTER_INT6_ACK 14 14 PERFCOUNTER_INT7_ACK 15 15 PERFMON_CVALUE_HI 16 31 regDC_PERFMON9_PERFMON_CVALUE_LOW 0 0x85b 1 0 2 PERFMON_CVALUE_LOW 0 31 regDC_PERFMON9_PERFMON_HI 0 0x85c 2 0 2 PERFMON_HI 0 15 PERFMON_READ_SEL 29 31 regDC_PERFMON9_PERFMON_LOW 0 0x85d 1 0 2 PERFMON_LOW 0 31 regHUBP3_DCSURF_SURFACE_CONFIG 0 0x879 4 0 2 SURFACE_PIXEL_FORMAT 0 6 ROTATION_ANGLE 8 9 H_MIRROR_EN 10 10 ALPHA_PLANE_EN 11 11 regHUBP3_DCSURF_ADDR_CONFIG 0 0x87a 4 0 2 NUM_PIPES 0 2 PIPE_INTERLEAVE 6 7 MAX_COMPRESSED_FRAGS 12 13 NUM_PKRS 16 18 regHUBP3_DCSURF_TILING_CONFIG 0 0x87b 4 0 2 SW_MODE 0 4 DIM_TYPE 7 8 META_LINEAR 9 9 PIPE_ALIGNED 11 11 regHUBP3_DCSURF_PRI_VIEWPORT_START 0 0x87d 2 0 2 PRI_VIEWPORT_X_START 0 13 PRI_VIEWPORT_Y_START 16 29 regHUBP3_DCSURF_PRI_VIEWPORT_DIMENSION 0 0x87e 2 0 2 PRI_VIEWPORT_WIDTH 0 13 PRI_VIEWPORT_HEIGHT 16 29 regHUBP3_DCSURF_PRI_VIEWPORT_START_C 0 0x87f 2 0 2 PRI_VIEWPORT_X_START_C 0 13 PRI_VIEWPORT_Y_START_C 16 29 regHUBP3_DCSURF_PRI_VIEWPORT_DIMENSION_C 0 0x880 2 0 2 PRI_VIEWPORT_WIDTH_C 0 13 PRI_VIEWPORT_HEIGHT_C 16 29 regHUBP3_DCSURF_SEC_VIEWPORT_START 0 0x881 2 0 2 SEC_VIEWPORT_X_START 0 13 SEC_VIEWPORT_Y_START 16 29 regHUBP3_DCSURF_SEC_VIEWPORT_DIMENSION 0 0x882 2 0 2 SEC_VIEWPORT_WIDTH 0 13 SEC_VIEWPORT_HEIGHT 16 29 regHUBP3_DCSURF_SEC_VIEWPORT_START_C 0 0x883 2 0 2 SEC_VIEWPORT_X_START_C 0 13 SEC_VIEWPORT_Y_START_C 16 29 regHUBP3_DCSURF_SEC_VIEWPORT_DIMENSION_C 0 0x884 2 0 2 SEC_VIEWPORT_WIDTH_C 0 13 SEC_VIEWPORT_HEIGHT_C 16 29 regHUBP3_DCHUBP_REQ_SIZE_CONFIG 0 0x885 8 0 2 SWATH_HEIGHT 0 2 PTE_ROW_HEIGHT_LINEAR 4 6 CHUNK_SIZE 8 10 MIN_CHUNK_SIZE 11 12 META_CHUNK_SIZE 16 17 MIN_META_CHUNK_SIZE 18 19 DPTE_GROUP_SIZE 20 22 VM_GROUP_SIZE 24 26 regHUBP3_DCHUBP_REQ_SIZE_CONFIG_C 0 0x886 7 0 2 SWATH_HEIGHT_C 0 2 PTE_ROW_HEIGHT_LINEAR_C 4 6 CHUNK_SIZE_C 8 10 MIN_CHUNK_SIZE_C 11 12 META_CHUNK_SIZE_C 16 17 MIN_META_CHUNK_SIZE_C 18 19 DPTE_GROUP_SIZE_C 20 22 regHUBP3_DCHUBP_CNTL 0 0x887 18 0 2 HUBP_BLANK_EN 0 0 HUBP_NO_OUTSTANDING_REQ 1 1 HUBP_SOFT_RESET 2 2 HUBP_IN_BLANK 3 3 HUBP_VTG_SEL 4 7 HUBP_VREADY_AT_OR_AFTER_VSYNC 8 8 HUBP_DISABLE_STOP_DATA_DURING_VM 9 9 HUBP_UNBOUNDED_REQ_MODE 10 10 HUBP_SEG_ALLOC_ERR_STATUS 11 11 HUBP_TTU_DISABLE 12 12 HUBP_TTU_MODE 13 15 HUBP_XRQ_NO_OUTSTANDING_REQ 16 19 HUBP_TIMEOUT_STATUS 20 23 HUBP_TIMEOUT_THRESHOLD 24 25 HUBP_TIMEOUT_STATUS_CLEAR 26 26 HUBP_TIMEOUT_INTERRUPT_EN 27 27 HUBP_UNDERFLOW_STATUS 28 30 HUBP_UNDERFLOW_CLEAR 31 31 regHUBP3_HUBP_CLK_CNTL 0 0x888 10 0 2 HUBP_CLOCK_ENABLE 0 0 HUBP_DISPCLK_R_GATE_DIS 4 4 HUBP_DPPCLK_G_GATE_DIS 8 8 HUBP_DCFCLK_R_GATE_DIS 12 12 HUBP_DCFCLK_G_GATE_DIS 16 16 HUBP_DISPCLK_R_CLOCK_ON 20 20 HUBP_DPPCLK_G_CLOCK_ON 21 21 HUBP_DCFCLK_R_CLOCK_ON 22 22 HUBP_DCFCLK_G_CLOCK_ON 23 23 HUBP_TEST_CLK_SEL 28 31 regHUBP3_DCHUBP_VMPG_CONFIG 0 0x889 1 0 2 VMPG_SIZE 0 0 regHUBP3_HUBPREQ_DEBUG_DB 0 0x88a 1 0 2 HUBPREQ_DEBUG 0 31 regHUBP3_HUBPREQ_DEBUG 0 0x88b 1 0 2 HUBPREQ_DEBUG 0 31 regHUBP3_HUBP_MEASURE_WIN_CTRL_DCFCLK 0 0x88f 5 0 2 HUBP_MEASURE_WIN_EN_DCFCLK 0 0 HUBP_MEASURE_WIN_PERIOD_M1_DCFCLK 4 11 HUBP_PERFMON_START_SEL_DCFCLK 12 16 HUBP_PERFMON_STOP_SEL_DCFCLK 20 24 HUBP_MEASURE_WIN_MODE_DCFCLK 28 29 regHUBP3_HUBP_MEASURE_WIN_CTRL_DPPCLK 0 0x890 5 0 2 HUBP_MEASURE_WIN_EN_DPPCLK 0 0 HUBP_MEASURE_WIN_SRC_SEL_DPPCLK 1 1 HUBP_MEASURE_WIN_PERIOD_M1_DPPCLK 4 11 HUBP_PERFMON_START_SEL_DPPCLK 12 16 HUBP_PERFMON_STOP_SEL_DPPCLK 20 24 regHUBPREQ3_DCSURF_SURFACE_PITCH 0 0x89b 2 0 2 PITCH 0 13 META_PITCH 16 29 regHUBPREQ3_DCSURF_SURFACE_PITCH_C 0 0x89c 2 0 2 PITCH_C 0 13 META_PITCH_C 16 29 regHUBPREQ3_VMID_SETTINGS_0 0 0x89d 1 0 2 VMID 0 3 regHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS 0 0x89e 1 0 2 PRIMARY_SURFACE_ADDRESS 0 31 regHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH 0 0x89f 1 0 2 PRIMARY_SURFACE_ADDRESS_HIGH 0 15 regHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_C 0 0x8a0 1 0 2 PRIMARY_SURFACE_ADDRESS_C 0 31 regHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C 0 0x8a1 1 0 2 PRIMARY_SURFACE_ADDRESS_HIGH_C 0 15 regHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS 0 0x8a2 1 0 2 SECONDARY_SURFACE_ADDRESS 0 31 regHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH 0 0x8a3 1 0 2 SECONDARY_SURFACE_ADDRESS_HIGH 0 15 regHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_C 0 0x8a4 1 0 2 SECONDARY_SURFACE_ADDRESS_C 0 31 regHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C 0 0x8a5 1 0 2 SECONDARY_SURFACE_ADDRESS_HIGH_C 0 15 regHUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS 0 0x8a6 1 0 2 PRIMARY_META_SURFACE_ADDRESS 0 31 regHUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH 0 0x8a7 1 0 2 PRIMARY_META_SURFACE_ADDRESS_HIGH 0 15 regHUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C 0 0x8a8 1 0 2 PRIMARY_META_SURFACE_ADDRESS_C 0 31 regHUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C 0 0x8a9 1 0 2 PRIMARY_META_SURFACE_ADDRESS_HIGH_C 0 15 regHUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS 0 0x8aa 1 0 2 SECONDARY_META_SURFACE_ADDRESS 0 31 regHUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH 0 0x8ab 1 0 2 SECONDARY_META_SURFACE_ADDRESS_HIGH 0 15 regHUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C 0 0x8ac 1 0 2 SECONDARY_META_SURFACE_ADDRESS_C 0 31 regHUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C 0 0x8ad 1 0 2 SECONDARY_META_SURFACE_ADDRESS_HIGH_C 0 15 regHUBPREQ3_DCSURF_SURFACE_CONTROL 0 0x8ae 14 0 2 PRIMARY_SURFACE_TMZ 0 0 PRIMARY_SURFACE_DCC_EN 1 1 PRIMARY_SURFACE_DCC_IND_BLK 2 3 PRIMARY_SURFACE_TMZ_C 4 4 PRIMARY_SURFACE_DCC_IND_BLK_C 5 6 SECONDARY_SURFACE_TMZ 8 8 SECONDARY_SURFACE_DCC_EN 9 9 SECONDARY_SURFACE_DCC_IND_BLK 10 11 SECONDARY_SURFACE_TMZ_C 12 12 SECONDARY_SURFACE_DCC_IND_BLK_C 13 14 PRIMARY_META_SURFACE_TMZ 16 16 PRIMARY_META_SURFACE_TMZ_C 17 17 SECONDARY_META_SURFACE_TMZ 18 18 SECONDARY_META_SURFACE_TMZ_C 19 19 regHUBPREQ3_DCSURF_FLIP_CONTROL 0 0x8af 10 0 2 SURFACE_UPDATE_LOCK 0 0 SURFACE_FLIP_TYPE 1 1 SURFACE_FLIP_VUPDATE_SKIP_NUM 4 7 SURFACE_FLIP_PENDING 8 8 HUBPREQ_MASTER_UPDATE_LOCK_STATUS 9 9 SURFACE_FLIP_MODE_FOR_STEREOSYNC 12 13 SURFACE_FLIP_IN_STEREOSYNC 16 16 SURFACE_FLIP_STEREO_SELECT_DISABLE 17 17 SURFACE_FLIP_STEREO_SELECT_POLARITY 18 18 SURFACE_FLIP_PENDING_DELAY 20 29 regHUBPREQ3_DCSURF_FLIP_CONTROL2 0 0x8b0 6 0 2 SURFACE_FLIP_PENDING_MIN_TIME 0 7 SURFACE_GSL_ENABLE 8 8 SURFACE_GSL_MASK 9 9 SURFACE_TRIPLE_BUFFER_ENABLE 10 10 SURFACE_INUSE_RAED_NO_LATCH 12 12 SURFACE_FLIP_EXEC_DEBUG_MODE 31 31 regHUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT 0 0x8b4 10 0 2 SURFACE_FLIP_INT_MASK 0 0 SURFACE_FLIP_INT_TYPE 1 1 SURFACE_FLIP_AWAY_INT_MASK 2 2 SURFACE_FLIP_AWAY_INT_TYPE 3 3 SURFACE_FLIP_CLEAR 8 8 SURFACE_FLIP_AWAY_CLEAR 9 9 SURFACE_FLIP_OCCURRED 16 16 SURFACE_FLIP_INT_STATUS 17 17 SURFACE_FLIP_AWAY_OCCURRED 18 18 SURFACE_FLIP_AWAY_INT_STATUS 19 19 regHUBPREQ3_DCSURF_SURFACE_INUSE 0 0x8b5 1 0 2 SURFACE_INUSE_ADDRESS 0 31 regHUBPREQ3_DCSURF_SURFACE_INUSE_HIGH 0 0x8b6 2 0 2 SURFACE_INUSE_ADDRESS_HIGH 0 15 SURFACE_INUSE_VMID 28 31 regHUBPREQ3_DCSURF_SURFACE_INUSE_C 0 0x8b7 1 0 2 SURFACE_INUSE_ADDRESS_C 0 31 regHUBPREQ3_DCSURF_SURFACE_INUSE_HIGH_C 0 0x8b8 2 0 2 SURFACE_INUSE_ADDRESS_HIGH_C 0 15 SURFACE_INUSE_VMID_C 28 31 regHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE 0 0x8b9 1 0 2 SURFACE_EARLIEST_INUSE_ADDRESS 0 31 regHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_HIGH 0 0x8ba 2 0 2 SURFACE_EARLIEST_INUSE_ADDRESS_HIGH 0 15 SURFACE_EARLIEST_INUSE_VMID 28 31 regHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_C 0 0x8bb 1 0 2 SURFACE_EARLIEST_INUSE_ADDRESS_C 0 31 regHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C 0 0x8bc 2 0 2 SURFACE_EARLIEST_INUSE_ADDRESS_HIGH_C 0 15 SURFACE_EARLIEST_INUSE_VMID_C 28 31 regHUBPREQ3_DCN_EXPANSION_MODE 0 0x8bd 4 0 2 DRQ_EXPANSION_MODE 0 1 CRQ_EXPANSION_MODE 2 3 MRQ_EXPANSION_MODE 4 5 PRQ_EXPANSION_MODE 6 7 regHUBPREQ3_DCN_TTU_QOS_WM 0 0x8be 2 0 2 QoS_LEVEL_LOW_WM 0 13 QoS_LEVEL_HIGH_WM 16 29 regHUBPREQ3_DCN_GLOBAL_TTU_CNTL 0 0x8bf 5 0 2 MIN_TTU_VBLANK 0 23 PIPE_IN_FLUSH_URGENT 24 24 PRQ_MRQ_FLUSH_URGENT 25 25 ROW_TTU_MODE 27 27 QoS_LEVEL_FLIP 28 31 regHUBPREQ3_DCN_SURF0_TTU_CNTL0 0 0x8c0 3 0 2 REFCYC_PER_REQ_DELIVERY 0 22 QoS_LEVEL_FIXED 24 27 QoS_RAMP_DISABLE 28 28 regHUBPREQ3_DCN_SURF0_TTU_CNTL1 0 0x8c1 1 0 2 REFCYC_PER_REQ_DELIVERY_PRE 0 22 regHUBPREQ3_DCN_SURF1_TTU_CNTL0 0 0x8c2 3 0 2 REFCYC_PER_REQ_DELIVERY 0 22 QoS_LEVEL_FIXED 24 27 QoS_RAMP_DISABLE 28 28 regHUBPREQ3_DCN_SURF1_TTU_CNTL1 0 0x8c3 1 0 2 REFCYC_PER_REQ_DELIVERY_PRE 0 22 regHUBPREQ3_DCN_CUR0_TTU_CNTL0 0 0x8c4 3 0 2 REFCYC_PER_REQ_DELIVERY 0 22 QoS_LEVEL_FIXED 24 27 QoS_RAMP_DISABLE 28 28 regHUBPREQ3_DCN_CUR0_TTU_CNTL1 0 0x8c5 1 0 2 REFCYC_PER_REQ_DELIVERY_PRE 0 22 regHUBPREQ3_DCN_CUR1_TTU_CNTL0 0 0x8c6 3 0 2 REFCYC_PER_REQ_DELIVERY 0 22 QoS_LEVEL_FIXED 24 27 QoS_RAMP_DISABLE 28 28 regHUBPREQ3_DCN_CUR1_TTU_CNTL1 0 0x8c7 1 0 2 REFCYC_PER_REQ_DELIVERY_PRE 0 22 regHUBPREQ3_DCN_DMDATA_VM_CNTL 0 0x8c8 7 0 2 REFCYC_PER_VM_DMDATA 0 15 DMDATA_VM_FAULT_STATUS 16 19 DMDATA_VM_FAULT_STATUS_CLEAR 20 20 DMDATA_VM_UNDERFLOW_STATUS 24 24 DMDATA_VM_LATE_STATUS 25 25 DMDATA_VM_UNDERFLOW_STATUS_CLEAR 26 26 DMDATA_VM_DONE 31 31 regHUBPREQ3_DCN_VM_SYSTEM_APERTURE_LOW_ADDR 0 0x8c9 1 0 2 MC_VM_SYSTEM_APERTURE_LOW_ADDR 0 29 regHUBPREQ3_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR 0 0x8ca 1 0 2 MC_VM_SYSTEM_APERTURE_HIGH_ADDR 0 29 regHUBPREQ3_DCN_VM_MX_L1_TLB_CNTL 0 0x8d7 4 0 2 ENABLE_L1_TLB 0 0 SYSTEM_ACCESS_MODE 3 4 SYSTEM_APERTURE_UNMAPPED_ACCESS 5 5 ENABLE_ADVANCED_DRIVER_MODEL 6 6 regHUBPREQ3_BLANK_OFFSET_0 0 0x8d8 2 0 2 REFCYC_H_BLANK_END 0 12 DLG_V_BLANK_END 16 30 regHUBPREQ3_BLANK_OFFSET_1 0 0x8d9 1 0 2 MIN_DST_Y_NEXT_START 0 17 regHUBPREQ3_DST_DIMENSIONS 0 0x8da 1 0 2 REFCYC_PER_HTOTAL 0 20 regHUBPREQ3_DST_AFTER_SCALER 0 0x8db 2 0 2 REFCYC_X_AFTER_SCALER 0 12 DST_Y_AFTER_SCALER 16 18 regHUBPREQ3_PREFETCH_SETTINGS 0 0x8dc 2 0 2 VRATIO_PREFETCH 0 21 DST_Y_PREFETCH 24 31 regHUBPREQ3_PREFETCH_SETTINGS_C 0 0x8dd 1 0 2 VRATIO_PREFETCH_C 0 21 regHUBPREQ3_VBLANK_PARAMETERS_0 0 0x8de 2 0 2 DST_Y_PER_VM_VBLANK 0 6 DST_Y_PER_ROW_VBLANK 8 13 regHUBPREQ3_VBLANK_PARAMETERS_1 0 0x8df 1 0 2 REFCYC_PER_PTE_GROUP_VBLANK_L 0 22 regHUBPREQ3_VBLANK_PARAMETERS_2 0 0x8e0 1 0 2 REFCYC_PER_PTE_GROUP_VBLANK_C 0 22 regHUBPREQ3_VBLANK_PARAMETERS_3 0 0x8e1 1 0 2 REFCYC_PER_META_CHUNK_VBLANK_L 0 22 regHUBPREQ3_VBLANK_PARAMETERS_4 0 0x8e2 1 0 2 REFCYC_PER_META_CHUNK_VBLANK_C 0 22 regHUBPREQ3_FLIP_PARAMETERS_0 0 0x8e3 2 0 2 DST_Y_PER_VM_FLIP 0 6 DST_Y_PER_ROW_FLIP 8 13 regHUBPREQ3_FLIP_PARAMETERS_1 0 0x8e4 1 0 2 REFCYC_PER_PTE_GROUP_FLIP_L 0 22 regHUBPREQ3_FLIP_PARAMETERS_2 0 0x8e5 1 0 2 REFCYC_PER_META_CHUNK_FLIP_L 0 22 regHUBPREQ3_NOM_PARAMETERS_0 0 0x8e6 1 0 2 DST_Y_PER_PTE_ROW_NOM_L 0 16 regHUBPREQ3_NOM_PARAMETERS_1 0 0x8e7 1 0 2 REFCYC_PER_PTE_GROUP_NOM_L 0 22 regHUBPREQ3_NOM_PARAMETERS_2 0 0x8e8 1 0 2 DST_Y_PER_PTE_ROW_NOM_C 0 16 regHUBPREQ3_NOM_PARAMETERS_3 0 0x8e9 1 0 2 REFCYC_PER_PTE_GROUP_NOM_C 0 22 regHUBPREQ3_NOM_PARAMETERS_4 0 0x8ea 1 0 2 DST_Y_PER_META_ROW_NOM_L 0 16 regHUBPREQ3_NOM_PARAMETERS_5 0 0x8eb 1 0 2 REFCYC_PER_META_CHUNK_NOM_L 0 22 regHUBPREQ3_NOM_PARAMETERS_6 0 0x8ec 1 0 2 DST_Y_PER_META_ROW_NOM_C 0 16 regHUBPREQ3_NOM_PARAMETERS_7 0 0x8ed 1 0 2 REFCYC_PER_META_CHUNK_NOM_C 0 22 regHUBPREQ3_PER_LINE_DELIVERY_PRE 0 0x8ee 2 0 2 REFCYC_PER_LINE_DELIVERY_PRE_L 0 12 REFCYC_PER_LINE_DELIVERY_PRE_C 16 28 regHUBPREQ3_PER_LINE_DELIVERY 0 0x8ef 2 0 2 REFCYC_PER_LINE_DELIVERY_L 0 12 REFCYC_PER_LINE_DELIVERY_C 16 28 regHUBPREQ3_CURSOR_SETTINGS 0 0x8f0 4 0 2 CURSOR0_DST_Y_OFFSET 0 7 CURSOR0_CHUNK_HDL_ADJUST 8 9 CURSOR1_DST_Y_OFFSET 16 23 CURSOR1_CHUNK_HDL_ADJUST 24 25 regHUBPREQ3_REF_FREQ_TO_PIX_FREQ 0 0x8f1 1 0 2 REF_FREQ_TO_PIX_FREQ 0 20 regHUBPREQ3_DST_Y_DELTA_DRQ_LIMIT 0 0x8f2 1 0 2 DST_Y_DELTA_DRQ_LIMIT 0 14 regHUBPREQ3_HUBPREQ_MEM_PWR_CTRL 0 0x8f3 8 0 2 REQ_DPTE_MEM_PWR_FORCE 0 1 REQ_DPTE_MEM_PWR_DIS 2 2 REQ_MPTE_MEM_PWR_FORCE 4 5 REQ_MPTE_MEM_PWR_DIS 6 6 REQ_META_MEM_PWR_FORCE 8 9 REQ_META_MEM_PWR_DIS 10 10 REQ_PDE_MEM_PWR_FORCE 12 13 REQ_PDE_MEM_PWR_DIS 14 14 regHUBPREQ3_HUBPREQ_MEM_PWR_STATUS 0 0x8f4 4 0 2 REQ_DPTE_MEM_PWR_STATE 0 1 REQ_MPTE_MEM_PWR_STATE 2 3 REQ_META_MEM_PWR_STATE 4 5 REQ_PDE_MEM_PWR_STATE 6 7 regHUBPREQ3_VBLANK_PARAMETERS_5 0 0x8f7 1 0 2 REFCYC_PER_VM_GROUP_VBLANK 0 22 regHUBPREQ3_VBLANK_PARAMETERS_6 0 0x8f8 1 0 2 REFCYC_PER_VM_REQ_VBLANK 0 22 regHUBPREQ3_FLIP_PARAMETERS_3 0 0x8f9 1 0 2 REFCYC_PER_VM_GROUP_FLIP 0 22 regHUBPREQ3_FLIP_PARAMETERS_4 0 0x8fa 1 0 2 REFCYC_PER_VM_REQ_FLIP 0 22 regHUBPREQ3_FLIP_PARAMETERS_5 0 0x8fb 1 0 2 REFCYC_PER_PTE_GROUP_FLIP_C 0 22 regHUBPREQ3_FLIP_PARAMETERS_6 0 0x8fc 1 0 2 REFCYC_PER_META_CHUNK_FLIP_C 0 22 regHUBPRET3_HUBPRET_CONTROL 0 0x900 7 0 2 DET_BUF_PLANE1_BASE_ADDRESS 4 12 PACK_3TO2_ELEMENT_DISABLE 15 15 CROSSBAR_SRC_ALPHA 16 17 CROSSBAR_SRC_Y_G 18 19 CROSSBAR_SRC_CB_B 20 21 CROSSBAR_SRC_CR_R 22 23 HUBPRET_CONTROL_SPARE 24 31 regHUBPRET3_HUBPRET_MEM_PWR_CTRL 0 0x901 5 0 2 DMROB_MEM_PWR_FORCE 8 9 DMROB_MEM_PWR_DIS 10 10 PIXCDC_MEM_PWR_FORCE 16 17 PIXCDC_MEM_PWR_DIS 18 18 PIXCDC_MEM_PWR_LS_MODE 20 21 regHUBPRET3_HUBPRET_MEM_PWR_STATUS 0 0x902 2 0 2 DMROB_MEM_PWR_STATE 2 3 PIXCDC_MEM_PWR_STATE 4 5 regHUBPRET3_HUBPRET_READ_LINE_CTRL0 0 0x903 2 0 2 PIPE_READ_LINE_INTERVAL_IN_NONACTIVE 0 15 PIPE_READ_LINE_VBLANK_MAXIMUM 16 29 regHUBPRET3_HUBPRET_READ_LINE_CTRL1 0 0x904 2 0 2 PIPE_READ_LINE_REPORTED_WHEN_REQ_DISABLED 0 13 HUBPRET_READ_LINE_CTRL1_SPARE 16 31 regHUBPRET3_HUBPRET_READ_LINE0 0 0x905 2 0 2 PIPE_READ_LINE0_START 0 13 PIPE_READ_LINE0_END 16 29 regHUBPRET3_HUBPRET_READ_LINE1 0 0x906 2 0 2 PIPE_READ_LINE1_START 0 13 PIPE_READ_LINE1_END 16 29 regHUBPRET3_HUBPRET_INTERRUPT 0 0x907 15 0 2 PIPE_VBLANK_INT_MASK 0 0 PIPE_READ_LINE0_INT_MASK 1 1 PIPE_READ_LINE1_INT_MASK 2 2 PIPE_VBLANK_INT_TYPE 4 4 PIPE_READ_LINE0_INT_TYPE 5 5 PIPE_READ_LINE1_INT_TYPE 6 6 PIPE_VBLANK_INT_CLEAR 8 8 PIPE_READ_LINE0_INT_CLEAR 9 9 PIPE_READ_LINE1_INT_CLEAR 10 10 PIPE_VBLANK_STATUS 12 12 PIPE_READ_LINE0_STATUS 13 13 PIPE_READ_LINE1_STATUS 14 14 PIPE_VBLANK_INT_STATUS 16 16 PIPE_READ_LINE0_INT_STATUS 17 17 PIPE_READ_LINE1_INT_STATUS 18 18 regHUBPRET3_HUBPRET_READ_LINE_VALUE 0 0x908 2 0 2 PIPE_READ_LINE 0 13 PIPE_READ_LINE_SNAPSHOT 16 29 regHUBPRET3_HUBPRET_READ_LINE_STATUS 0 0x909 5 0 2 PIPE_READ_VBLANK 0 0 PIPE_READ_LINE0_INSIDE 4 4 PIPE_READ_LINE0_OUTSIDE 5 5 PIPE_READ_LINE1_INSIDE 8 8 PIPE_READ_LINE1_OUTSIDE 10 10 regCURSOR0_3_CURSOR_CONTROL 0 0x90c 10 0 2 CURSOR_ENABLE 0 0 CURSOR_REQ_MODE 2 2 CURSOR_2X_MAGNIFY 4 4 CURSOR_MODE 8 10 CURSOR_TMZ 12 12 CURSOR_PITCH 16 17 CURSOR_XY_POSITION_ROTATION_AND_MIRRORING_BYPASS 20 20 CURSOR_LINES_PER_CHUNK 24 28 CURSOR_PERFMON_LATENCY_MEASURE_EN 30 30 CURSOR_PERFMON_LATENCY_MEASURE_SEL 31 31 regCURSOR0_3_CURSOR_SURFACE_ADDRESS 0 0x90d 1 0 2 CURSOR_SURFACE_ADDRESS 0 31 regCURSOR0_3_CURSOR_SURFACE_ADDRESS_HIGH 0 0x90e 1 0 2 CURSOR_SURFACE_ADDRESS_HIGH 0 15 regCURSOR0_3_CURSOR_SIZE 0 0x90f 2 0 2 CURSOR_HEIGHT 0 8 CURSOR_WIDTH 16 24 regCURSOR0_3_CURSOR_POSITION 0 0x910 2 0 2 CURSOR_Y_POSITION 0 13 CURSOR_X_POSITION 16 29 regCURSOR0_3_CURSOR_HOT_SPOT 0 0x911 2 0 2 CURSOR_HOT_SPOT_Y 0 7 CURSOR_HOT_SPOT_X 16 23 regCURSOR0_3_CURSOR_STEREO_CONTROL 0 0x912 3 0 2 CURSOR_STEREO_EN 0 0 CURSOR_PRIMARY_OFFSET 4 17 CURSOR_SECONDARY_OFFSET 18 31 regCURSOR0_3_CURSOR_DST_OFFSET 0 0x913 1 0 2 CURSOR_DST_X_OFFSET 0 12 regCURSOR0_3_CURSOR_MEM_PWR_CTRL 0 0x914 3 0 2 CROB_MEM_PWR_FORCE 0 1 CROB_MEM_PWR_DIS 2 2 CROB_MEM_PWR_LS_MODE 4 5 regCURSOR0_3_CURSOR_MEM_PWR_STATUS 0 0x915 1 0 2 CROB_MEM_PWR_STATE 0 1 regCURSOR0_3_DMDATA_ADDRESS_HIGH 0 0x916 2 0 2 DMDATA_ADDRESS_HIGH 0 15 DMDATA_TMZ 30 30 regCURSOR0_3_DMDATA_ADDRESS_LOW 0 0x917 1 0 2 DMDATA_ADDRESS_LOW 0 31 regCURSOR0_3_DMDATA_CNTL 0 0x918 4 0 2 DMDATA_UPDATED 0 0 DMDATA_REPEAT 1 1 DMDATA_MODE 2 2 DMDATA_SIZE 16 27 regCURSOR0_3_DMDATA_QOS_CNTL 0 0x919 3 0 2 DMDATA_QOS_MODE 0 0 DMDATA_QOS_LEVEL 4 7 DMDATA_DL_DELTA 16 31 regCURSOR0_3_DMDATA_STATUS 0 0x91a 3 0 2 DMDATA_DONE 0 0 DMDATA_UNDERFLOW 2 2 DMDATA_UNDERFLOW_CLEAR 4 4 regCURSOR0_3_DMDATA_SW_CNTL 0 0x91b 3 0 2 DMDATA_SW_UPDATED 0 0 DMDATA_SW_REPEAT 1 1 DMDATA_SW_SIZE 16 27 regCURSOR0_3_DMDATA_SW_DATA 0 0x91c 1 0 2 DMDATA_SW_DATA 0 31 regDC_PERFMON10_PERFCOUNTER_CNTL 0 0x931 11 0 2 PERFCOUNTER_EVENT_SEL 0 8 PERFCOUNTER_CVALUE_SEL 9 11 PERFCOUNTER_INC_MODE 12 14 PERFCOUNTER_HW_CNTL_SEL 15 15 PERFCOUNTER_RUNEN_MODE 16 16 PERFCOUNTER_CNTOFF_START_DIS 22 22 PERFCOUNTER_RESTART_EN 23 23 PERFCOUNTER_INT_EN 24 24 PERFCOUNTER_OFF_MASK 25 25 PERFCOUNTER_ACTIVE 26 26 PERFCOUNTER_CNTL_SEL 29 31 regDC_PERFMON10_PERFCOUNTER_CNTL2 0 0x932 5 0 2 PERFCOUNTER_COUNTED_VALUE_TYPE 0 1 PERFCOUNTER_HW_STOP1_SEL 2 2 PERFCOUNTER_HW_STOP2_SEL 3 3 PERFCOUNTER_CNTOFF_SEL 8 13 PERFCOUNTER_CNTL2_SEL 29 31 regDC_PERFMON10_PERFCOUNTER_STATE 0 0x933 16 0 2 PERFCOUNTER_CNT0_STATE 0 1 PERFCOUNTER_STATE_SEL0 2 2 PERFCOUNTER_CNT1_STATE 4 5 PERFCOUNTER_STATE_SEL1 6 6 PERFCOUNTER_CNT2_STATE 8 9 PERFCOUNTER_STATE_SEL2 10 10 PERFCOUNTER_CNT3_STATE 12 13 PERFCOUNTER_STATE_SEL3 14 14 PERFCOUNTER_CNT4_STATE 16 17 PERFCOUNTER_STATE_SEL4 18 18 PERFCOUNTER_CNT5_STATE 20 21 PERFCOUNTER_STATE_SEL5 22 22 PERFCOUNTER_CNT6_STATE 24 25 PERFCOUNTER_STATE_SEL6 26 26 PERFCOUNTER_CNT7_STATE 28 29 PERFCOUNTER_STATE_SEL7 30 30 regDC_PERFMON10_PERFMON_CNTL 0 0x934 6 0 2 PERFMON_STATE 0 1 PERFMON_RPT_COUNT 8 27 PERFMON_CNTOFF_AND_OR 28 28 PERFMON_CNTOFF_INT_EN 29 29 PERFMON_CNTOFF_INT_STATUS 30 30 PERFMON_CNTOFF_INT_ACK 31 31 regDC_PERFMON10_PERFMON_CNTL2 0 0x935 4 0 2 PERFMON_CNTOFF_INT_TYPE 0 0 PERFMON_CLK_ENABLE 1 1 PERFMON_RUN_ENABLE_START_SEL 2 9 PERFMON_RUN_ENABLE_STOP_SEL 10 17 regDC_PERFMON10_PERFMON_CVALUE_INT_MISC 0 0x936 17 0 2 PERFCOUNTER_INT0_STATUS 0 0 PERFCOUNTER_INT1_STATUS 1 1 PERFCOUNTER_INT2_STATUS 2 2 PERFCOUNTER_INT3_STATUS 3 3 PERFCOUNTER_INT4_STATUS 4 4 PERFCOUNTER_INT5_STATUS 5 5 PERFCOUNTER_INT6_STATUS 6 6 PERFCOUNTER_INT7_STATUS 7 7 PERFCOUNTER_INT0_ACK 8 8 PERFCOUNTER_INT1_ACK 9 9 PERFCOUNTER_INT2_ACK 10 10 PERFCOUNTER_INT3_ACK 11 11 PERFCOUNTER_INT4_ACK 12 12 PERFCOUNTER_INT5_ACK 13 13 PERFCOUNTER_INT6_ACK 14 14 PERFCOUNTER_INT7_ACK 15 15 PERFMON_CVALUE_HI 16 31 regDC_PERFMON10_PERFMON_CVALUE_LOW 0 0x937 1 0 2 PERFMON_CVALUE_LOW 0 31 regDC_PERFMON10_PERFMON_HI 0 0x938 2 0 2 PERFMON_HI 0 15 PERFMON_READ_SEL 29 31 regDC_PERFMON10_PERFMON_LOW 0 0x939 1 0 2 PERFMON_LOW 0 31 regCNVC_CFG0_CNVC_SURFACE_PIXEL_FORMAT 0 0xccf 2 0 2 CNVC_SURFACE_PIXEL_FORMAT 0 6 CNVC_ALPHA_PLANE_ENABLE 8 8 regCNVC_CFG0_FORMAT_CONTROL 0 0xcd0 11 0 2 FORMAT_EXPANSION_MODE 0 0 FORMAT_CNV16 4 4 ALPHA_EN 8 8 CNVC_BYPASS 12 12 CNVC_BYPASS_MSB_ALIGN 13 13 CLAMP_POSITIVE 16 16 CLAMP_POSITIVE_C 17 17 CNVC_UPDATE_PENDING 20 20 FORMAT_CROSSBAR_R 24 25 FORMAT_CROSSBAR_G 26 27 FORMAT_CROSSBAR_B 28 29 regCNVC_CFG0_FCNV_FP_BIAS_R 0 0xcd1 1 0 2 FCNV_FP_BIAS_R 0 18 regCNVC_CFG0_FCNV_FP_BIAS_G 0 0xcd2 1 0 2 FCNV_FP_BIAS_G 0 18 regCNVC_CFG0_FCNV_FP_BIAS_B 0 0xcd3 1 0 2 FCNV_FP_BIAS_B 0 18 regCNVC_CFG0_FCNV_FP_SCALE_R 0 0xcd4 1 0 2 FCNV_FP_SCALE_R 0 18 regCNVC_CFG0_FCNV_FP_SCALE_G 0 0xcd5 1 0 2 FCNV_FP_SCALE_G 0 18 regCNVC_CFG0_FCNV_FP_SCALE_B 0 0xcd6 1 0 2 FCNV_FP_SCALE_B 0 18 regCNVC_CFG0_COLOR_KEYER_CONTROL 0 0xcd7 2 0 2 COLOR_KEYER_EN 0 0 COLOR_KEYER_MODE 4 5 regCNVC_CFG0_COLOR_KEYER_ALPHA 0 0xcd8 2 0 2 COLOR_KEYER_ALPHA_LOW 0 15 COLOR_KEYER_ALPHA_HIGH 16 31 regCNVC_CFG0_COLOR_KEYER_RED 0 0xcd9 2 0 2 COLOR_KEYER_RED_LOW 0 15 COLOR_KEYER_RED_HIGH 16 31 regCNVC_CFG0_COLOR_KEYER_GREEN 0 0xcda 2 0 2 COLOR_KEYER_GREEN_LOW 0 15 COLOR_KEYER_GREEN_HIGH 16 31 regCNVC_CFG0_COLOR_KEYER_BLUE 0 0xcdb 2 0 2 COLOR_KEYER_BLUE_LOW 0 15 COLOR_KEYER_BLUE_HIGH 16 31 regCNVC_CFG0_ALPHA_2BIT_LUT 0 0xcdd 4 0 2 ALPHA_2BIT_LUT0 0 7 ALPHA_2BIT_LUT1 8 15 ALPHA_2BIT_LUT2 16 23 ALPHA_2BIT_LUT3 24 31 regCNVC_CFG0_PRE_DEALPHA 0 0xcde 2 0 2 PRE_DEALPHA_EN 0 0 PRE_DEALPHA_ABLND_EN 4 4 regCNVC_CFG0_PRE_CSC_MODE 0 0xcdf 2 0 2 PRE_CSC_MODE 0 1 PRE_CSC_MODE_CURRENT 2 3 regCNVC_CFG0_PRE_CSC_C11_C12 0 0xce0 2 0 2 PRE_CSC_C11 0 15 PRE_CSC_C12 16 31 regCNVC_CFG0_PRE_CSC_C13_C14 0 0xce1 2 0 2 PRE_CSC_C13 0 15 PRE_CSC_C14 16 31 regCNVC_CFG0_PRE_CSC_C21_C22 0 0xce2 2 0 2 PRE_CSC_C21 0 15 PRE_CSC_C22 16 31 regCNVC_CFG0_PRE_CSC_C23_C24 0 0xce3 2 0 2 PRE_CSC_C23 0 15 PRE_CSC_C24 16 31 regCNVC_CFG0_PRE_CSC_C31_C32 0 0xce4 2 0 2 PRE_CSC_C31 0 15 PRE_CSC_C32 16 31 regCNVC_CFG0_PRE_CSC_C33_C34 0 0xce5 2 0 2 PRE_CSC_C33 0 15 PRE_CSC_C34 16 31 regCNVC_CFG0_PRE_CSC_B_C11_C12 0 0xce6 2 0 2 PRE_CSC_B_C11 0 15 PRE_CSC_B_C12 16 31 regCNVC_CFG0_PRE_CSC_B_C13_C14 0 0xce7 2 0 2 PRE_CSC_B_C13 0 15 PRE_CSC_B_C14 16 31 regCNVC_CFG0_PRE_CSC_B_C21_C22 0 0xce8 2 0 2 PRE_CSC_B_C21 0 15 PRE_CSC_B_C22 16 31 regCNVC_CFG0_PRE_CSC_B_C23_C24 0 0xce9 2 0 2 PRE_CSC_B_C23 0 15 PRE_CSC_B_C24 16 31 regCNVC_CFG0_PRE_CSC_B_C31_C32 0 0xcea 2 0 2 PRE_CSC_B_C31 0 15 PRE_CSC_B_C32 16 31 regCNVC_CFG0_PRE_CSC_B_C33_C34 0 0xceb 2 0 2 PRE_CSC_B_C33 0 15 PRE_CSC_B_C34 16 31 regCNVC_CFG0_CNVC_COEF_FORMAT 0 0xcec 1 0 2 PRE_CSC_COEF_FORMAT 0 0 regCNVC_CFG0_PRE_DEGAM 0 0xced 2 0 2 PRE_DEGAM_MODE 0 1 PRE_DEGAM_SELECT 4 6 regCNVC_CFG0_PRE_REALPHA 0 0xcee 2 0 2 PRE_REALPHA_EN 0 0 PRE_REALPHA_ABLND_EN 4 4 regCNVC_CUR0_CURSOR0_CONTROL 0 0xcf1 7 0 2 CUR0_ENABLE 0 0 CUR0_EXPANSION_MODE 1 1 CUR0_PIX_INV_MODE 2 2 CUR0_ROM_EN 3 3 CUR0_MODE 4 6 CUR0_PIXEL_ALPHA_MOD_EN 7 7 CUR0_UPDATE_PENDING 16 16 regCNVC_CUR0_CURSOR0_COLOR0 0 0xcf2 1 0 2 CUR0_COLOR0 0 23 regCNVC_CUR0_CURSOR0_COLOR1 0 0xcf3 1 0 2 CUR0_COLOR1 0 23 regCNVC_CUR0_CURSOR0_FP_SCALE_BIAS 0 0xcf4 2 0 2 CUR0_FP_SCALE 0 15 CUR0_FP_BIAS 16 31 regDSCL0_SCL_COEF_RAM_TAP_SELECT 0 0xcf9 3 0 2 SCL_COEF_RAM_TAP_PAIR_IDX 0 1 SCL_COEF_RAM_PHASE 8 13 SCL_COEF_RAM_FILTER_TYPE 16 18 regDSCL0_SCL_COEF_RAM_TAP_DATA 0 0xcfa 4 0 2 SCL_COEF_RAM_EVEN_TAP_COEF 0 13 SCL_COEF_RAM_EVEN_TAP_COEF_EN 15 15 SCL_COEF_RAM_ODD_TAP_COEF 16 29 SCL_COEF_RAM_ODD_TAP_COEF_EN 31 31 regDSCL0_SCL_MODE 0 0xcfb 6 0 2 DSCL_MODE 0 2 SCL_COEF_RAM_SELECT 8 8 SCL_COEF_RAM_SELECT_CURRENT 12 12 SCL_CHROMA_COEF_MODE 16 16 SCL_ALPHA_COEF_MODE 20 20 SCL_COEF_RAM_SELECT_RD 24 24 regDSCL0_SCL_TAP_CONTROL 0 0xcfc 4 0 2 SCL_V_NUM_TAPS 0 2 SCL_H_NUM_TAPS 4 6 SCL_V_NUM_TAPS_C 8 10 SCL_H_NUM_TAPS_C 12 14 regDSCL0_DSCL_CONTROL 0 0xcfd 1 0 2 SCL_BOUNDARY_MODE 0 0 regDSCL0_DSCL_2TAP_CONTROL 0 0xcfe 6 0 2 SCL_H_2TAP_HARDCODE_COEF_EN 0 0 SCL_H_2TAP_SHARP_EN 4 4 SCL_H_2TAP_SHARP_FACTOR 8 10 SCL_V_2TAP_HARDCODE_COEF_EN 16 16 SCL_V_2TAP_SHARP_EN 20 20 SCL_V_2TAP_SHARP_FACTOR 24 26 regDSCL0_SCL_MANUAL_REPLICATE_CONTROL 0 0xcff 2 0 2 SCL_V_MANUAL_REPLICATE_FACTOR 0 3 SCL_H_MANUAL_REPLICATE_FACTOR 8 11 regDSCL0_SCL_HORZ_FILTER_SCALE_RATIO 0 0xd00 1 0 2 SCL_H_SCALE_RATIO 0 26 regDSCL0_SCL_HORZ_FILTER_INIT 0 0xd01 2 0 2 SCL_H_INIT_FRAC 0 23 SCL_H_INIT_INT 24 27 regDSCL0_SCL_HORZ_FILTER_SCALE_RATIO_C 0 0xd02 1 0 2 SCL_H_SCALE_RATIO_C 0 26 regDSCL0_SCL_HORZ_FILTER_INIT_C 0 0xd03 2 0 2 SCL_H_INIT_FRAC_C 0 23 SCL_H_INIT_INT_C 24 27 regDSCL0_SCL_VERT_FILTER_SCALE_RATIO 0 0xd04 1 0 2 SCL_V_SCALE_RATIO 0 26 regDSCL0_SCL_VERT_FILTER_INIT 0 0xd05 2 0 2 SCL_V_INIT_FRAC 0 23 SCL_V_INIT_INT 24 27 regDSCL0_SCL_VERT_FILTER_INIT_BOT 0 0xd06 2 0 2 SCL_V_INIT_FRAC_BOT 0 23 SCL_V_INIT_INT_BOT 24 27 regDSCL0_SCL_VERT_FILTER_SCALE_RATIO_C 0 0xd07 1 0 2 SCL_V_SCALE_RATIO_C 0 26 regDSCL0_SCL_VERT_FILTER_INIT_C 0 0xd08 2 0 2 SCL_V_INIT_FRAC_C 0 23 SCL_V_INIT_INT_C 24 27 regDSCL0_SCL_VERT_FILTER_INIT_BOT_C 0 0xd09 2 0 2 SCL_V_INIT_FRAC_BOT_C 0 23 SCL_V_INIT_INT_BOT_C 24 27 regDSCL0_SCL_BLACK_COLOR 0 0xd0a 2 0 2 SCL_BLACK_COLOR_RGB_Y 0 15 SCL_BLACK_COLOR_CBCR 16 31 regDSCL0_DSCL_UPDATE 0 0xd0b 1 0 2 SCL_UPDATE_PENDING 0 0 regDSCL0_DSCL_AUTOCAL 0 0xd0c 3 0 2 AUTOCAL_MODE 0 1 AUTOCAL_NUM_PIPE 8 9 AUTOCAL_PIPE_ID 12 13 regDSCL0_DSCL_EXT_OVERSCAN_LEFT_RIGHT 0 0xd0d 2 0 2 EXT_OVERSCAN_RIGHT 0 12 EXT_OVERSCAN_LEFT 16 28 regDSCL0_DSCL_EXT_OVERSCAN_TOP_BOTTOM 0 0xd0e 2 0 2 EXT_OVERSCAN_BOTTOM 0 12 EXT_OVERSCAN_TOP 16 28 regDSCL0_OTG_H_BLANK 0 0xd0f 2 0 2 OTG_H_BLANK_START 0 13 OTG_H_BLANK_END 16 29 regDSCL0_OTG_V_BLANK 0 0xd10 2 0 2 OTG_V_BLANK_START 0 13 OTG_V_BLANK_END 16 29 regDSCL0_RECOUT_START 0 0xd11 2 0 2 RECOUT_START_X 0 12 RECOUT_START_Y 16 28 regDSCL0_RECOUT_SIZE 0 0xd12 2 0 2 RECOUT_WIDTH 0 13 RECOUT_HEIGHT 16 29 regDSCL0_MPC_SIZE 0 0xd13 2 0 2 MPC_WIDTH 0 13 MPC_HEIGHT 16 29 regDSCL0_LB_DATA_FORMAT 0 0xd14 2 0 2 INTERLEAVE_EN 0 0 ALPHA_EN 4 4 regDSCL0_LB_MEMORY_CTRL 0 0xd15 4 0 2 MEMORY_CONFIG 0 1 LB_MAX_PARTITIONS 8 13 LB_NUM_PARTITIONS 16 22 LB_NUM_PARTITIONS_C 24 30 regDSCL0_LB_V_COUNTER 0 0xd16 2 0 2 V_COUNTER 0 12 V_COUNTER_C 16 28 regDSCL0_DSCL_MEM_PWR_CTRL 0 0xd17 15 0 2 LUT_MEM_PWR_FORCE 0 1 LUT_MEM_PWR_DIS 2 2 LB_G1_MEM_PWR_FORCE 4 5 LB_G1_MEM_PWR_DIS 6 6 LB_G2_MEM_PWR_FORCE 8 9 LB_G2_MEM_PWR_DIS 10 10 LB_G3_MEM_PWR_FORCE 12 13 LB_G3_MEM_PWR_DIS 14 14 LB_G4_MEM_PWR_FORCE 16 17 LB_G4_MEM_PWR_DIS 18 18 LB_G5_MEM_PWR_FORCE 20 21 LB_G5_MEM_PWR_DIS 22 22 LB_G6_MEM_PWR_FORCE 24 25 LB_G6_MEM_PWR_DIS 26 26 LB_MEM_PWR_MODE 28 28 regDSCL0_DSCL_MEM_PWR_STATUS 0 0xd18 7 0 2 LUT_MEM_PWR_STATE 0 1 LB_G1_MEM_PWR_STATE 2 3 LB_G2_MEM_PWR_STATE 4 5 LB_G3_MEM_PWR_STATE 6 7 LB_G4_MEM_PWR_STATE 8 9 LB_G5_MEM_PWR_STATE 10 11 LB_G6_MEM_PWR_STATE 12 13 regDSCL0_OBUF_CONTROL 0 0xd19 4 0 2 OBUF_BYPASS 0 0 OBUF_USE_FULL_BUFFER 1 1 OBUF_IS_HALF_RECOUT_WIDTH 2 2 OBUF_OUT_HOLD_CNT 4 7 regDSCL0_OBUF_MEM_PWR_CTRL 0 0xd1a 4 0 2 OBUF_MEM_PWR_FORCE 0 1 OBUF_MEM_PWR_DIS 2 2 OBUF_MEM_PWR_MODE 8 8 OBUF_MEM_PWR_STATE 16 17 regCM0_CM_CONTROL 0 0xd20 2 0 2 CM_BYPASS 0 0 CM_UPDATE_PENDING 8 8 regCM0_CM_POST_CSC_CONTROL 0 0xd21 2 0 2 CM_POST_CSC_MODE 0 1 CM_POST_CSC_MODE_CURRENT 2 3 regCM0_CM_POST_CSC_C11_C12 0 0xd22 2 0 2 CM_POST_CSC_C11 0 15 CM_POST_CSC_C12 16 31 regCM0_CM_POST_CSC_C13_C14 0 0xd23 2 0 2 CM_POST_CSC_C13 0 15 CM_POST_CSC_C14 16 31 regCM0_CM_POST_CSC_C21_C22 0 0xd24 2 0 2 CM_POST_CSC_C21 0 15 CM_POST_CSC_C22 16 31 regCM0_CM_POST_CSC_C23_C24 0 0xd25 2 0 2 CM_POST_CSC_C23 0 15 CM_POST_CSC_C24 16 31 regCM0_CM_POST_CSC_C31_C32 0 0xd26 2 0 2 CM_POST_CSC_C31 0 15 CM_POST_CSC_C32 16 31 regCM0_CM_POST_CSC_C33_C34 0 0xd27 2 0 2 CM_POST_CSC_C33 0 15 CM_POST_CSC_C34 16 31 regCM0_CM_POST_CSC_B_C11_C12 0 0xd28 2 0 2 CM_POST_CSC_B_C11 0 15 CM_POST_CSC_B_C12 16 31 regCM0_CM_POST_CSC_B_C13_C14 0 0xd29 2 0 2 CM_POST_CSC_B_C13 0 15 CM_POST_CSC_B_C14 16 31 regCM0_CM_POST_CSC_B_C21_C22 0 0xd2a 2 0 2 CM_POST_CSC_B_C21 0 15 CM_POST_CSC_B_C22 16 31 regCM0_CM_POST_CSC_B_C23_C24 0 0xd2b 2 0 2 CM_POST_CSC_B_C23 0 15 CM_POST_CSC_B_C24 16 31 regCM0_CM_POST_CSC_B_C31_C32 0 0xd2c 2 0 2 CM_POST_CSC_B_C31 0 15 CM_POST_CSC_B_C32 16 31 regCM0_CM_POST_CSC_B_C33_C34 0 0xd2d 2 0 2 CM_POST_CSC_B_C33 0 15 CM_POST_CSC_B_C34 16 31 regCM0_CM_GAMUT_REMAP_CONTROL 0 0xd2e 2 0 2 CM_GAMUT_REMAP_MODE 0 1 CM_GAMUT_REMAP_MODE_CURRENT 2 3 regCM0_CM_GAMUT_REMAP_C11_C12 0 0xd2f 2 0 2 CM_GAMUT_REMAP_C11 0 15 CM_GAMUT_REMAP_C12 16 31 regCM0_CM_GAMUT_REMAP_C13_C14 0 0xd30 2 0 2 CM_GAMUT_REMAP_C13 0 15 CM_GAMUT_REMAP_C14 16 31 regCM0_CM_GAMUT_REMAP_C21_C22 0 0xd31 2 0 2 CM_GAMUT_REMAP_C21 0 15 CM_GAMUT_REMAP_C22 16 31 regCM0_CM_GAMUT_REMAP_C23_C24 0 0xd32 2 0 2 CM_GAMUT_REMAP_C23 0 15 CM_GAMUT_REMAP_C24 16 31 regCM0_CM_GAMUT_REMAP_C31_C32 0 0xd33 2 0 2 CM_GAMUT_REMAP_C31 0 15 CM_GAMUT_REMAP_C32 16 31 regCM0_CM_GAMUT_REMAP_C33_C34 0 0xd34 2 0 2 CM_GAMUT_REMAP_C33 0 15 CM_GAMUT_REMAP_C34 16 31 regCM0_CM_GAMUT_REMAP_B_C11_C12 0 0xd35 2 0 2 CM_GAMUT_REMAP_B_C11 0 15 CM_GAMUT_REMAP_B_C12 16 31 regCM0_CM_GAMUT_REMAP_B_C13_C14 0 0xd36 2 0 2 CM_GAMUT_REMAP_B_C13 0 15 CM_GAMUT_REMAP_B_C14 16 31 regCM0_CM_GAMUT_REMAP_B_C21_C22 0 0xd37 2 0 2 CM_GAMUT_REMAP_B_C21 0 15 CM_GAMUT_REMAP_B_C22 16 31 regCM0_CM_GAMUT_REMAP_B_C23_C24 0 0xd38 2 0 2 CM_GAMUT_REMAP_B_C23 0 15 CM_GAMUT_REMAP_B_C24 16 31 regCM0_CM_GAMUT_REMAP_B_C31_C32 0 0xd39 2 0 2 CM_GAMUT_REMAP_B_C31 0 15 CM_GAMUT_REMAP_B_C32 16 31 regCM0_CM_GAMUT_REMAP_B_C33_C34 0 0xd3a 2 0 2 CM_GAMUT_REMAP_B_C33 0 15 CM_GAMUT_REMAP_B_C34 16 31 regCM0_CM_BIAS_CR_R 0 0xd3b 1 0 2 CM_BIAS_CR_R 0 15 regCM0_CM_BIAS_Y_G_CB_B 0 0xd3c 2 0 2 CM_BIAS_Y_G 0 15 CM_BIAS_CB_B 16 31 regCM0_CM_GAMCOR_CONTROL 0 0xd3d 5 0 2 CM_GAMCOR_MODE 0 1 CM_GAMCOR_SELECT 2 2 CM_GAMCOR_PWL_DISABLE 3 3 CM_GAMCOR_MODE_CURRENT 4 5 CM_GAMCOR_SELECT_CURRENT 6 6 regCM0_CM_GAMCOR_LUT_INDEX 0 0xd3e 1 0 2 CM_GAMCOR_LUT_INDEX 0 8 regCM0_CM_GAMCOR_LUT_DATA 0 0xd3f 1 0 2 CM_GAMCOR_LUT_DATA 0 17 regCM0_CM_GAMCOR_LUT_CONTROL 0 0xd40 5 0 2 CM_GAMCOR_LUT_WRITE_COLOR_MASK 0 2 CM_GAMCOR_LUT_READ_COLOR_SEL 3 4 CM_GAMCOR_LUT_READ_DBG 5 5 CM_GAMCOR_LUT_HOST_SEL 6 6 CM_GAMCOR_LUT_CONFIG_MODE 7 7 regCM0_CM_GAMCOR_RAMA_START_CNTL_B 0 0xd41 2 0 2 CM_GAMCOR_RAMA_EXP_REGION_START_B 0 17 CM_GAMCOR_RAMA_EXP_REGION_START_SEGMENT_B 20 26 regCM0_CM_GAMCOR_RAMA_START_CNTL_G 0 0xd42 2 0 2 CM_GAMCOR_RAMA_EXP_REGION_START_G 0 17 CM_GAMCOR_RAMA_EXP_REGION_START_SEGMENT_G 20 26 regCM0_CM_GAMCOR_RAMA_START_CNTL_R 0 0xd43 2 0 2 CM_GAMCOR_RAMA_EXP_REGION_START_R 0 17 CM_GAMCOR_RAMA_EXP_REGION_START_SEGMENT_R 20 26 regCM0_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B 0 0xd44 1 0 2 CM_GAMCOR_RAMA_EXP_REGION_START_SLOPE_B 0 17 regCM0_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G 0 0xd45 1 0 2 CM_GAMCOR_RAMA_EXP_REGION_START_SLOPE_G 0 17 regCM0_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R 0 0xd46 1 0 2 CM_GAMCOR_RAMA_EXP_REGION_START_SLOPE_R 0 17 regCM0_CM_GAMCOR_RAMA_START_BASE_CNTL_B 0 0xd47 1 0 2 CM_GAMCOR_RAMA_EXP_REGION_START_BASE_B 0 17 regCM0_CM_GAMCOR_RAMA_START_BASE_CNTL_G 0 0xd48 1 0 2 CM_GAMCOR_RAMA_EXP_REGION_START_BASE_G 0 17 regCM0_CM_GAMCOR_RAMA_START_BASE_CNTL_R 0 0xd49 1 0 2 CM_GAMCOR_RAMA_EXP_REGION_START_BASE_R 0 17 regCM0_CM_GAMCOR_RAMA_END_CNTL1_B 0 0xd4a 1 0 2 CM_GAMCOR_RAMA_EXP_REGION_END_BASE_B 0 17 regCM0_CM_GAMCOR_RAMA_END_CNTL2_B 0 0xd4b 2 0 2 CM_GAMCOR_RAMA_EXP_REGION_END_B 0 15 CM_GAMCOR_RAMA_EXP_REGION_END_SLOPE_B 16 31 regCM0_CM_GAMCOR_RAMA_END_CNTL1_G 0 0xd4c 1 0 2 CM_GAMCOR_RAMA_EXP_REGION_END_BASE_G 0 17 regCM0_CM_GAMCOR_RAMA_END_CNTL2_G 0 0xd4d 2 0 2 CM_GAMCOR_RAMA_EXP_REGION_END_G 0 15 CM_GAMCOR_RAMA_EXP_REGION_END_SLOPE_G 16 31 regCM0_CM_GAMCOR_RAMA_END_CNTL1_R 0 0xd4e 1 0 2 CM_GAMCOR_RAMA_EXP_REGION_END_BASE_R 0 17 regCM0_CM_GAMCOR_RAMA_END_CNTL2_R 0 0xd4f 2 0 2 CM_GAMCOR_RAMA_EXP_REGION_END_R 0 15 CM_GAMCOR_RAMA_EXP_REGION_END_SLOPE_R 16 31 regCM0_CM_GAMCOR_RAMA_OFFSET_B 0 0xd50 1 0 2 CM_GAMCOR_RAMA_OFFSET_B 0 18 regCM0_CM_GAMCOR_RAMA_OFFSET_G 0 0xd51 1 0 2 CM_GAMCOR_RAMA_OFFSET_G 0 18 regCM0_CM_GAMCOR_RAMA_OFFSET_R 0 0xd52 1 0 2 CM_GAMCOR_RAMA_OFFSET_R 0 18 regCM0_CM_GAMCOR_RAMA_REGION_0_1 0 0xd53 4 0 2 CM_GAMCOR_RAMA_EXP_REGION0_LUT_OFFSET 0 8 CM_GAMCOR_RAMA_EXP_REGION0_NUM_SEGMENTS 12 14 CM_GAMCOR_RAMA_EXP_REGION1_LUT_OFFSET 16 24 CM_GAMCOR_RAMA_EXP_REGION1_NUM_SEGMENTS 28 30 regCM0_CM_GAMCOR_RAMA_REGION_2_3 0 0xd54 4 0 2 CM_GAMCOR_RAMA_EXP_REGION2_LUT_OFFSET 0 8 CM_GAMCOR_RAMA_EXP_REGION2_NUM_SEGMENTS 12 14 CM_GAMCOR_RAMA_EXP_REGION3_LUT_OFFSET 16 24 CM_GAMCOR_RAMA_EXP_REGION3_NUM_SEGMENTS 28 30 regCM0_CM_GAMCOR_RAMA_REGION_4_5 0 0xd55 4 0 2 CM_GAMCOR_RAMA_EXP_REGION4_LUT_OFFSET 0 8 CM_GAMCOR_RAMA_EXP_REGION4_NUM_SEGMENTS 12 14 CM_GAMCOR_RAMA_EXP_REGION5_LUT_OFFSET 16 24 CM_GAMCOR_RAMA_EXP_REGION5_NUM_SEGMENTS 28 30 regCM0_CM_GAMCOR_RAMA_REGION_6_7 0 0xd56 4 0 2 CM_GAMCOR_RAMA_EXP_REGION6_LUT_OFFSET 0 8 CM_GAMCOR_RAMA_EXP_REGION6_NUM_SEGMENTS 12 14 CM_GAMCOR_RAMA_EXP_REGION7_LUT_OFFSET 16 24 CM_GAMCOR_RAMA_EXP_REGION7_NUM_SEGMENTS 28 30 regCM0_CM_GAMCOR_RAMA_REGION_8_9 0 0xd57 4 0 2 CM_GAMCOR_RAMA_EXP_REGION8_LUT_OFFSET 0 8 CM_GAMCOR_RAMA_EXP_REGION8_NUM_SEGMENTS 12 14 CM_GAMCOR_RAMA_EXP_REGION9_LUT_OFFSET 16 24 CM_GAMCOR_RAMA_EXP_REGION9_NUM_SEGMENTS 28 30 regCM0_CM_GAMCOR_RAMA_REGION_10_11 0 0xd58 4 0 2 CM_GAMCOR_RAMA_EXP_REGION10_LUT_OFFSET 0 8 CM_GAMCOR_RAMA_EXP_REGION10_NUM_SEGMENTS 12 14 CM_GAMCOR_RAMA_EXP_REGION11_LUT_OFFSET 16 24 CM_GAMCOR_RAMA_EXP_REGION11_NUM_SEGMENTS 28 30 regCM0_CM_GAMCOR_RAMA_REGION_12_13 0 0xd59 4 0 2 CM_GAMCOR_RAMA_EXP_REGION12_LUT_OFFSET 0 8 CM_GAMCOR_RAMA_EXP_REGION12_NUM_SEGMENTS 12 14 CM_GAMCOR_RAMA_EXP_REGION13_LUT_OFFSET 16 24 CM_GAMCOR_RAMA_EXP_REGION13_NUM_SEGMENTS 28 30 regCM0_CM_GAMCOR_RAMA_REGION_14_15 0 0xd5a 4 0 2 CM_GAMCOR_RAMA_EXP_REGION14_LUT_OFFSET 0 8 CM_GAMCOR_RAMA_EXP_REGION14_NUM_SEGMENTS 12 14 CM_GAMCOR_RAMA_EXP_REGION15_LUT_OFFSET 16 24 CM_GAMCOR_RAMA_EXP_REGION15_NUM_SEGMENTS 28 30 regCM0_CM_GAMCOR_RAMA_REGION_16_17 0 0xd5b 4 0 2 CM_GAMCOR_RAMA_EXP_REGION16_LUT_OFFSET 0 8 CM_GAMCOR_RAMA_EXP_REGION16_NUM_SEGMENTS 12 14 CM_GAMCOR_RAMA_EXP_REGION17_LUT_OFFSET 16 24 CM_GAMCOR_RAMA_EXP_REGION17_NUM_SEGMENTS 28 30 regCM0_CM_GAMCOR_RAMA_REGION_18_19 0 0xd5c 4 0 2 CM_GAMCOR_RAMA_EXP_REGION18_LUT_OFFSET 0 8 CM_GAMCOR_RAMA_EXP_REGION18_NUM_SEGMENTS 12 14 CM_GAMCOR_RAMA_EXP_REGION19_LUT_OFFSET 16 24 CM_GAMCOR_RAMA_EXP_REGION19_NUM_SEGMENTS 28 30 regCM0_CM_GAMCOR_RAMA_REGION_20_21 0 0xd5d 4 0 2 CM_GAMCOR_RAMA_EXP_REGION20_LUT_OFFSET 0 8 CM_GAMCOR_RAMA_EXP_REGION20_NUM_SEGMENTS 12 14 CM_GAMCOR_RAMA_EXP_REGION21_LUT_OFFSET 16 24 CM_GAMCOR_RAMA_EXP_REGION21_NUM_SEGMENTS 28 30 regCM0_CM_GAMCOR_RAMA_REGION_22_23 0 0xd5e 4 0 2 CM_GAMCOR_RAMA_EXP_REGION22_LUT_OFFSET 0 8 CM_GAMCOR_RAMA_EXP_REGION22_NUM_SEGMENTS 12 14 CM_GAMCOR_RAMA_EXP_REGION23_LUT_OFFSET 16 24 CM_GAMCOR_RAMA_EXP_REGION23_NUM_SEGMENTS 28 30 regCM0_CM_GAMCOR_RAMA_REGION_24_25 0 0xd5f 4 0 2 CM_GAMCOR_RAMA_EXP_REGION24_LUT_OFFSET 0 8 CM_GAMCOR_RAMA_EXP_REGION24_NUM_SEGMENTS 12 14 CM_GAMCOR_RAMA_EXP_REGION25_LUT_OFFSET 16 24 CM_GAMCOR_RAMA_EXP_REGION25_NUM_SEGMENTS 28 30 regCM0_CM_GAMCOR_RAMA_REGION_26_27 0 0xd60 4 0 2 CM_GAMCOR_RAMA_EXP_REGION26_LUT_OFFSET 0 8 CM_GAMCOR_RAMA_EXP_REGION26_NUM_SEGMENTS 12 14 CM_GAMCOR_RAMA_EXP_REGION27_LUT_OFFSET 16 24 CM_GAMCOR_RAMA_EXP_REGION27_NUM_SEGMENTS 28 30 regCM0_CM_GAMCOR_RAMA_REGION_28_29 0 0xd61 4 0 2 CM_GAMCOR_RAMA_EXP_REGION28_LUT_OFFSET 0 8 CM_GAMCOR_RAMA_EXP_REGION28_NUM_SEGMENTS 12 14 CM_GAMCOR_RAMA_EXP_REGION29_LUT_OFFSET 16 24 CM_GAMCOR_RAMA_EXP_REGION29_NUM_SEGMENTS 28 30 regCM0_CM_GAMCOR_RAMA_REGION_30_31 0 0xd62 4 0 2 CM_GAMCOR_RAMA_EXP_REGION30_LUT_OFFSET 0 8 CM_GAMCOR_RAMA_EXP_REGION30_NUM_SEGMENTS 12 14 CM_GAMCOR_RAMA_EXP_REGION31_LUT_OFFSET 16 24 CM_GAMCOR_RAMA_EXP_REGION31_NUM_SEGMENTS 28 30 regCM0_CM_GAMCOR_RAMA_REGION_32_33 0 0xd63 4 0 2 CM_GAMCOR_RAMA_EXP_REGION32_LUT_OFFSET 0 8 CM_GAMCOR_RAMA_EXP_REGION32_NUM_SEGMENTS 12 14 CM_GAMCOR_RAMA_EXP_REGION33_LUT_OFFSET 16 24 CM_GAMCOR_RAMA_EXP_REGION33_NUM_SEGMENTS 28 30 regCM0_CM_GAMCOR_RAMB_START_CNTL_B 0 0xd64 2 0 2 CM_GAMCOR_RAMB_EXP_REGION_START_B 0 17 CM_GAMCOR_RAMB_EXP_REGION_START_SEGMENT_B 20 26 regCM0_CM_GAMCOR_RAMB_START_CNTL_G 0 0xd65 2 0 2 CM_GAMCOR_RAMB_EXP_REGION_START_G 0 17 CM_GAMCOR_RAMB_EXP_REGION_START_SEGMENT_G 20 26 regCM0_CM_GAMCOR_RAMB_START_CNTL_R 0 0xd66 2 0 2 CM_GAMCOR_RAMB_EXP_REGION_START_R 0 17 CM_GAMCOR_RAMB_EXP_REGION_START_SEGMENT_R 20 26 regCM0_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B 0 0xd67 1 0 2 CM_GAMCOR_RAMB_EXP_REGION_START_SLOPE_B 0 17 regCM0_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G 0 0xd68 1 0 2 CM_GAMCOR_RAMB_EXP_REGION_START_SLOPE_G 0 17 regCM0_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R 0 0xd69 1 0 2 CM_GAMCOR_RAMB_EXP_REGION_START_SLOPE_R 0 17 regCM0_CM_GAMCOR_RAMB_START_BASE_CNTL_B 0 0xd6a 1 0 2 CM_GAMCOR_RAMB_EXP_REGION_START_BASE_B 0 17 regCM0_CM_GAMCOR_RAMB_START_BASE_CNTL_G 0 0xd6b 1 0 2 CM_GAMCOR_RAMB_EXP_REGION_START_BASE_G 0 17 regCM0_CM_GAMCOR_RAMB_START_BASE_CNTL_R 0 0xd6c 1 0 2 CM_GAMCOR_RAMB_EXP_REGION_START_BASE_R 0 17 regCM0_CM_GAMCOR_RAMB_END_CNTL1_B 0 0xd6d 1 0 2 CM_GAMCOR_RAMB_EXP_REGION_END_BASE_B 0 17 regCM0_CM_GAMCOR_RAMB_END_CNTL2_B 0 0xd6e 2 0 2 CM_GAMCOR_RAMB_EXP_REGION_END_B 0 15 CM_GAMCOR_RAMB_EXP_REGION_END_SLOPE_B 16 31 regCM0_CM_GAMCOR_RAMB_END_CNTL1_G 0 0xd6f 1 0 2 CM_GAMCOR_RAMB_EXP_REGION_END_BASE_G 0 17 regCM0_CM_GAMCOR_RAMB_END_CNTL2_G 0 0xd70 2 0 2 CM_GAMCOR_RAMB_EXP_REGION_END_G 0 15 CM_GAMCOR_RAMB_EXP_REGION_END_SLOPE_G 16 31 regCM0_CM_GAMCOR_RAMB_END_CNTL1_R 0 0xd71 1 0 2 CM_GAMCOR_RAMB_EXP_REGION_END_BASE_R 0 17 regCM0_CM_GAMCOR_RAMB_END_CNTL2_R 0 0xd72 2 0 2 CM_GAMCOR_RAMB_EXP_REGION_END_R 0 15 CM_GAMCOR_RAMB_EXP_REGION_END_SLOPE_R 16 31 regCM0_CM_GAMCOR_RAMB_OFFSET_B 0 0xd73 1 0 2 CM_GAMCOR_RAMB_OFFSET_B 0 18 regCM0_CM_GAMCOR_RAMB_OFFSET_G 0 0xd74 1 0 2 CM_GAMCOR_RAMB_OFFSET_G 0 18 regCM0_CM_GAMCOR_RAMB_OFFSET_R 0 0xd75 1 0 2 CM_GAMCOR_RAMB_OFFSET_R 0 18 regCM0_CM_GAMCOR_RAMB_REGION_0_1 0 0xd76 4 0 2 CM_GAMCOR_RAMB_EXP_REGION0_LUT_OFFSET 0 8 CM_GAMCOR_RAMB_EXP_REGION0_NUM_SEGMENTS 12 14 CM_GAMCOR_RAMB_EXP_REGION1_LUT_OFFSET 16 24 CM_GAMCOR_RAMB_EXP_REGION1_NUM_SEGMENTS 28 30 regCM0_CM_GAMCOR_RAMB_REGION_2_3 0 0xd77 4 0 2 CM_GAMCOR_RAMB_EXP_REGION2_LUT_OFFSET 0 8 CM_GAMCOR_RAMB_EXP_REGION2_NUM_SEGMENTS 12 14 CM_GAMCOR_RAMB_EXP_REGION3_LUT_OFFSET 16 24 CM_GAMCOR_RAMB_EXP_REGION3_NUM_SEGMENTS 28 30 regCM0_CM_GAMCOR_RAMB_REGION_4_5 0 0xd78 4 0 2 CM_GAMCOR_RAMB_EXP_REGION4_LUT_OFFSET 0 8 CM_GAMCOR_RAMB_EXP_REGION4_NUM_SEGMENTS 12 14 CM_GAMCOR_RAMB_EXP_REGION5_LUT_OFFSET 16 24 CM_GAMCOR_RAMB_EXP_REGION5_NUM_SEGMENTS 28 30 regCM0_CM_GAMCOR_RAMB_REGION_6_7 0 0xd79 4 0 2 CM_GAMCOR_RAMB_EXP_REGION6_LUT_OFFSET 0 8 CM_GAMCOR_RAMB_EXP_REGION6_NUM_SEGMENTS 12 14 CM_GAMCOR_RAMB_EXP_REGION7_LUT_OFFSET 16 24 CM_GAMCOR_RAMB_EXP_REGION7_NUM_SEGMENTS 28 30 regCM0_CM_GAMCOR_RAMB_REGION_8_9 0 0xd7a 4 0 2 CM_GAMCOR_RAMB_EXP_REGION8_LUT_OFFSET 0 8 CM_GAMCOR_RAMB_EXP_REGION8_NUM_SEGMENTS 12 14 CM_GAMCOR_RAMB_EXP_REGION9_LUT_OFFSET 16 24 CM_GAMCOR_RAMB_EXP_REGION9_NUM_SEGMENTS 28 30 regCM0_CM_GAMCOR_RAMB_REGION_10_11 0 0xd7b 4 0 2 CM_GAMCOR_RAMB_EXP_REGION10_LUT_OFFSET 0 8 CM_GAMCOR_RAMB_EXP_REGION10_NUM_SEGMENTS 12 14 CM_GAMCOR_RAMB_EXP_REGION11_LUT_OFFSET 16 24 CM_GAMCOR_RAMB_EXP_REGION11_NUM_SEGMENTS 28 30 regCM0_CM_GAMCOR_RAMB_REGION_12_13 0 0xd7c 4 0 2 CM_GAMCOR_RAMB_EXP_REGION12_LUT_OFFSET 0 8 CM_GAMCOR_RAMB_EXP_REGION12_NUM_SEGMENTS 12 14 CM_GAMCOR_RAMB_EXP_REGION13_LUT_OFFSET 16 24 CM_GAMCOR_RAMB_EXP_REGION13_NUM_SEGMENTS 28 30 regCM0_CM_GAMCOR_RAMB_REGION_14_15 0 0xd7d 4 0 2 CM_GAMCOR_RAMB_EXP_REGION14_LUT_OFFSET 0 8 CM_GAMCOR_RAMB_EXP_REGION14_NUM_SEGMENTS 12 14 CM_GAMCOR_RAMB_EXP_REGION15_LUT_OFFSET 16 24 CM_GAMCOR_RAMB_EXP_REGION15_NUM_SEGMENTS 28 30 regCM0_CM_GAMCOR_RAMB_REGION_16_17 0 0xd7e 4 0 2 CM_GAMCOR_RAMB_EXP_REGION16_LUT_OFFSET 0 8 CM_GAMCOR_RAMB_EXP_REGION16_NUM_SEGMENTS 12 14 CM_GAMCOR_RAMB_EXP_REGION17_LUT_OFFSET 16 24 CM_GAMCOR_RAMB_EXP_REGION17_NUM_SEGMENTS 28 30 regCM0_CM_GAMCOR_RAMB_REGION_18_19 0 0xd7f 4 0 2 CM_GAMCOR_RAMB_EXP_REGION18_LUT_OFFSET 0 8 CM_GAMCOR_RAMB_EXP_REGION18_NUM_SEGMENTS 12 14 CM_GAMCOR_RAMB_EXP_REGION19_LUT_OFFSET 16 24 CM_GAMCOR_RAMB_EXP_REGION19_NUM_SEGMENTS 28 30 regCM0_CM_GAMCOR_RAMB_REGION_20_21 0 0xd80 4 0 2 CM_GAMCOR_RAMB_EXP_REGION20_LUT_OFFSET 0 8 CM_GAMCOR_RAMB_EXP_REGION20_NUM_SEGMENTS 12 14 CM_GAMCOR_RAMB_EXP_REGION21_LUT_OFFSET 16 24 CM_GAMCOR_RAMB_EXP_REGION21_NUM_SEGMENTS 28 30 regCM0_CM_GAMCOR_RAMB_REGION_22_23 0 0xd81 4 0 2 CM_GAMCOR_RAMB_EXP_REGION22_LUT_OFFSET 0 8 CM_GAMCOR_RAMB_EXP_REGION22_NUM_SEGMENTS 12 14 CM_GAMCOR_RAMB_EXP_REGION23_LUT_OFFSET 16 24 CM_GAMCOR_RAMB_EXP_REGION23_NUM_SEGMENTS 28 30 regCM0_CM_GAMCOR_RAMB_REGION_24_25 0 0xd82 4 0 2 CM_GAMCOR_RAMB_EXP_REGION24_LUT_OFFSET 0 8 CM_GAMCOR_RAMB_EXP_REGION24_NUM_SEGMENTS 12 14 CM_GAMCOR_RAMB_EXP_REGION25_LUT_OFFSET 16 24 CM_GAMCOR_RAMB_EXP_REGION25_NUM_SEGMENTS 28 30 regCM0_CM_GAMCOR_RAMB_REGION_26_27 0 0xd83 4 0 2 CM_GAMCOR_RAMB_EXP_REGION26_LUT_OFFSET 0 8 CM_GAMCOR_RAMB_EXP_REGION26_NUM_SEGMENTS 12 14 CM_GAMCOR_RAMB_EXP_REGION27_LUT_OFFSET 16 24 CM_GAMCOR_RAMB_EXP_REGION27_NUM_SEGMENTS 28 30 regCM0_CM_GAMCOR_RAMB_REGION_28_29 0 0xd84 4 0 2 CM_GAMCOR_RAMB_EXP_REGION28_LUT_OFFSET 0 8 CM_GAMCOR_RAMB_EXP_REGION28_NUM_SEGMENTS 12 14 CM_GAMCOR_RAMB_EXP_REGION29_LUT_OFFSET 16 24 CM_GAMCOR_RAMB_EXP_REGION29_NUM_SEGMENTS 28 30 regCM0_CM_GAMCOR_RAMB_REGION_30_31 0 0xd85 4 0 2 CM_GAMCOR_RAMB_EXP_REGION30_LUT_OFFSET 0 8 CM_GAMCOR_RAMB_EXP_REGION30_NUM_SEGMENTS 12 14 CM_GAMCOR_RAMB_EXP_REGION31_LUT_OFFSET 16 24 CM_GAMCOR_RAMB_EXP_REGION31_NUM_SEGMENTS 28 30 regCM0_CM_GAMCOR_RAMB_REGION_32_33 0 0xd86 4 0 2 CM_GAMCOR_RAMB_EXP_REGION32_LUT_OFFSET 0 8 CM_GAMCOR_RAMB_EXP_REGION32_NUM_SEGMENTS 12 14 CM_GAMCOR_RAMB_EXP_REGION33_LUT_OFFSET 16 24 CM_GAMCOR_RAMB_EXP_REGION33_NUM_SEGMENTS 28 30 regCM0_CM_BLNDGAM_CONTROL 0 0xd87 5 0 2 CM_BLNDGAM_MODE 0 1 CM_BLNDGAM_SELECT 2 2 CM_BLNDGAM_PWL_DISABLE 3 3 CM_BLNDGAM_MODE_CURRENT 4 5 CM_BLNDGAM_SELECT_CURRENT 6 6 regCM0_CM_BLNDGAM_LUT_INDEX 0 0xd88 1 0 2 CM_BLNDGAM_LUT_INDEX 0 8 regCM0_CM_BLNDGAM_LUT_DATA 0 0xd89 1 0 2 CM_BLNDGAM_LUT_DATA 0 17 regCM0_CM_BLNDGAM_LUT_CONTROL 0 0xd8a 5 0 2 CM_BLNDGAM_LUT_WRITE_COLOR_MASK 0 2 CM_BLNDGAM_LUT_READ_COLOR_SEL 3 4 CM_BLNDGAM_LUT_READ_DBG 5 5 CM_BLNDGAM_LUT_HOST_SEL 6 6 CM_BLNDGAM_LUT_CONFIG_MODE 7 7 regCM0_CM_BLNDGAM_RAMA_START_CNTL_B 0 0xd8b 2 0 2 CM_BLNDGAM_RAMA_EXP_REGION_START_B 0 17 CM_BLNDGAM_RAMA_EXP_REGION_START_SEGMENT_B 20 26 regCM0_CM_BLNDGAM_RAMA_START_CNTL_G 0 0xd8c 2 0 2 CM_BLNDGAM_RAMA_EXP_REGION_START_G 0 17 CM_BLNDGAM_RAMA_EXP_REGION_START_SEGMENT_G 20 26 regCM0_CM_BLNDGAM_RAMA_START_CNTL_R 0 0xd8d 2 0 2 CM_BLNDGAM_RAMA_EXP_REGION_START_R 0 17 CM_BLNDGAM_RAMA_EXP_REGION_START_SEGMENT_R 20 26 regCM0_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_B 0 0xd8e 1 0 2 CM_BLNDGAM_RAMA_EXP_REGION_START_SLOPE_B 0 17 regCM0_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_G 0 0xd8f 1 0 2 CM_BLNDGAM_RAMA_EXP_REGION_START_SLOPE_G 0 17 regCM0_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_R 0 0xd90 1 0 2 CM_BLNDGAM_RAMA_EXP_REGION_START_SLOPE_R 0 17 regCM0_CM_BLNDGAM_RAMA_START_BASE_CNTL_B 0 0xd91 1 0 2 CM_BLNDGAM_RAMA_EXP_REGION_START_BASE_B 0 17 regCM0_CM_BLNDGAM_RAMA_START_BASE_CNTL_G 0 0xd92 1 0 2 CM_BLNDGAM_RAMA_EXP_REGION_START_BASE_G 0 17 regCM0_CM_BLNDGAM_RAMA_START_BASE_CNTL_R 0 0xd93 1 0 2 CM_BLNDGAM_RAMA_EXP_REGION_START_BASE_R 0 17 regCM0_CM_BLNDGAM_RAMA_END_CNTL1_B 0 0xd94 1 0 2 CM_BLNDGAM_RAMA_EXP_REGION_END_BASE_B 0 17 regCM0_CM_BLNDGAM_RAMA_END_CNTL2_B 0 0xd95 2 0 2 CM_BLNDGAM_RAMA_EXP_REGION_END_B 0 15 CM_BLNDGAM_RAMA_EXP_REGION_END_SLOPE_B 16 31 regCM0_CM_BLNDGAM_RAMA_END_CNTL1_G 0 0xd96 1 0 2 CM_BLNDGAM_RAMA_EXP_REGION_END_BASE_G 0 17 regCM0_CM_BLNDGAM_RAMA_END_CNTL2_G 0 0xd97 2 0 2 CM_BLNDGAM_RAMA_EXP_REGION_END_G 0 15 CM_BLNDGAM_RAMA_EXP_REGION_END_SLOPE_G 16 31 regCM0_CM_BLNDGAM_RAMA_END_CNTL1_R 0 0xd98 1 0 2 CM_BLNDGAM_RAMA_EXP_REGION_END_BASE_R 0 17 regCM0_CM_BLNDGAM_RAMA_END_CNTL2_R 0 0xd99 2 0 2 CM_BLNDGAM_RAMA_EXP_REGION_END_R 0 15 CM_BLNDGAM_RAMA_EXP_REGION_END_SLOPE_R 16 31 regCM0_CM_BLNDGAM_RAMA_OFFSET_B 0 0xd9a 1 0 2 CM_BLNDGAM_RAMA_OFFSET_B 0 18 regCM0_CM_BLNDGAM_RAMA_OFFSET_G 0 0xd9b 1 0 2 CM_BLNDGAM_RAMA_OFFSET_G 0 18 regCM0_CM_BLNDGAM_RAMA_OFFSET_R 0 0xd9c 1 0 2 CM_BLNDGAM_RAMA_OFFSET_R 0 18 regCM0_CM_BLNDGAM_RAMA_REGION_0_1 0 0xd9d 4 0 2 CM_BLNDGAM_RAMA_EXP_REGION0_LUT_OFFSET 0 8 CM_BLNDGAM_RAMA_EXP_REGION0_NUM_SEGMENTS 12 14 CM_BLNDGAM_RAMA_EXP_REGION1_LUT_OFFSET 16 24 CM_BLNDGAM_RAMA_EXP_REGION1_NUM_SEGMENTS 28 30 regCM0_CM_BLNDGAM_RAMA_REGION_2_3 0 0xd9e 4 0 2 CM_BLNDGAM_RAMA_EXP_REGION2_LUT_OFFSET 0 8 CM_BLNDGAM_RAMA_EXP_REGION2_NUM_SEGMENTS 12 14 CM_BLNDGAM_RAMA_EXP_REGION3_LUT_OFFSET 16 24 CM_BLNDGAM_RAMA_EXP_REGION3_NUM_SEGMENTS 28 30 regCM0_CM_BLNDGAM_RAMA_REGION_4_5 0 0xd9f 4 0 2 CM_BLNDGAM_RAMA_EXP_REGION4_LUT_OFFSET 0 8 CM_BLNDGAM_RAMA_EXP_REGION4_NUM_SEGMENTS 12 14 CM_BLNDGAM_RAMA_EXP_REGION5_LUT_OFFSET 16 24 CM_BLNDGAM_RAMA_EXP_REGION5_NUM_SEGMENTS 28 30 regCM0_CM_BLNDGAM_RAMA_REGION_6_7 0 0xda0 4 0 2 CM_BLNDGAM_RAMA_EXP_REGION6_LUT_OFFSET 0 8 CM_BLNDGAM_RAMA_EXP_REGION6_NUM_SEGMENTS 12 14 CM_BLNDGAM_RAMA_EXP_REGION7_LUT_OFFSET 16 24 CM_BLNDGAM_RAMA_EXP_REGION7_NUM_SEGMENTS 28 30 regCM0_CM_BLNDGAM_RAMA_REGION_8_9 0 0xda1 4 0 2 CM_BLNDGAM_RAMA_EXP_REGION8_LUT_OFFSET 0 8 CM_BLNDGAM_RAMA_EXP_REGION8_NUM_SEGMENTS 12 14 CM_BLNDGAM_RAMA_EXP_REGION9_LUT_OFFSET 16 24 CM_BLNDGAM_RAMA_EXP_REGION9_NUM_SEGMENTS 28 30 regCM0_CM_BLNDGAM_RAMA_REGION_10_11 0 0xda2 4 0 2 CM_BLNDGAM_RAMA_EXP_REGION10_LUT_OFFSET 0 8 CM_BLNDGAM_RAMA_EXP_REGION10_NUM_SEGMENTS 12 14 CM_BLNDGAM_RAMA_EXP_REGION11_LUT_OFFSET 16 24 CM_BLNDGAM_RAMA_EXP_REGION11_NUM_SEGMENTS 28 30 regCM0_CM_BLNDGAM_RAMA_REGION_12_13 0 0xda3 4 0 2 CM_BLNDGAM_RAMA_EXP_REGION12_LUT_OFFSET 0 8 CM_BLNDGAM_RAMA_EXP_REGION12_NUM_SEGMENTS 12 14 CM_BLNDGAM_RAMA_EXP_REGION13_LUT_OFFSET 16 24 CM_BLNDGAM_RAMA_EXP_REGION13_NUM_SEGMENTS 28 30 regCM0_CM_BLNDGAM_RAMA_REGION_14_15 0 0xda4 4 0 2 CM_BLNDGAM_RAMA_EXP_REGION14_LUT_OFFSET 0 8 CM_BLNDGAM_RAMA_EXP_REGION14_NUM_SEGMENTS 12 14 CM_BLNDGAM_RAMA_EXP_REGION15_LUT_OFFSET 16 24 CM_BLNDGAM_RAMA_EXP_REGION15_NUM_SEGMENTS 28 30 regCM0_CM_BLNDGAM_RAMA_REGION_16_17 0 0xda5 4 0 2 CM_BLNDGAM_RAMA_EXP_REGION16_LUT_OFFSET 0 8 CM_BLNDGAM_RAMA_EXP_REGION16_NUM_SEGMENTS 12 14 CM_BLNDGAM_RAMA_EXP_REGION17_LUT_OFFSET 16 24 CM_BLNDGAM_RAMA_EXP_REGION17_NUM_SEGMENTS 28 30 regCM0_CM_BLNDGAM_RAMA_REGION_18_19 0 0xda6 4 0 2 CM_BLNDGAM_RAMA_EXP_REGION18_LUT_OFFSET 0 8 CM_BLNDGAM_RAMA_EXP_REGION18_NUM_SEGMENTS 12 14 CM_BLNDGAM_RAMA_EXP_REGION19_LUT_OFFSET 16 24 CM_BLNDGAM_RAMA_EXP_REGION19_NUM_SEGMENTS 28 30 regCM0_CM_BLNDGAM_RAMA_REGION_20_21 0 0xda7 4 0 2 CM_BLNDGAM_RAMA_EXP_REGION20_LUT_OFFSET 0 8 CM_BLNDGAM_RAMA_EXP_REGION20_NUM_SEGMENTS 12 14 CM_BLNDGAM_RAMA_EXP_REGION21_LUT_OFFSET 16 24 CM_BLNDGAM_RAMA_EXP_REGION21_NUM_SEGMENTS 28 30 regCM0_CM_BLNDGAM_RAMA_REGION_22_23 0 0xda8 4 0 2 CM_BLNDGAM_RAMA_EXP_REGION22_LUT_OFFSET 0 8 CM_BLNDGAM_RAMA_EXP_REGION22_NUM_SEGMENTS 12 14 CM_BLNDGAM_RAMA_EXP_REGION23_LUT_OFFSET 16 24 CM_BLNDGAM_RAMA_EXP_REGION23_NUM_SEGMENTS 28 30 regCM0_CM_BLNDGAM_RAMA_REGION_24_25 0 0xda9 4 0 2 CM_BLNDGAM_RAMA_EXP_REGION24_LUT_OFFSET 0 8 CM_BLNDGAM_RAMA_EXP_REGION24_NUM_SEGMENTS 12 14 CM_BLNDGAM_RAMA_EXP_REGION25_LUT_OFFSET 16 24 CM_BLNDGAM_RAMA_EXP_REGION25_NUM_SEGMENTS 28 30 regCM0_CM_BLNDGAM_RAMA_REGION_26_27 0 0xdaa 4 0 2 CM_BLNDGAM_RAMA_EXP_REGION26_LUT_OFFSET 0 8 CM_BLNDGAM_RAMA_EXP_REGION26_NUM_SEGMENTS 12 14 CM_BLNDGAM_RAMA_EXP_REGION27_LUT_OFFSET 16 24 CM_BLNDGAM_RAMA_EXP_REGION27_NUM_SEGMENTS 28 30 regCM0_CM_BLNDGAM_RAMA_REGION_28_29 0 0xdab 4 0 2 CM_BLNDGAM_RAMA_EXP_REGION28_LUT_OFFSET 0 8 CM_BLNDGAM_RAMA_EXP_REGION28_NUM_SEGMENTS 12 14 CM_BLNDGAM_RAMA_EXP_REGION29_LUT_OFFSET 16 24 CM_BLNDGAM_RAMA_EXP_REGION29_NUM_SEGMENTS 28 30 regCM0_CM_BLNDGAM_RAMA_REGION_30_31 0 0xdac 4 0 2 CM_BLNDGAM_RAMA_EXP_REGION30_LUT_OFFSET 0 8 CM_BLNDGAM_RAMA_EXP_REGION30_NUM_SEGMENTS 12 14 CM_BLNDGAM_RAMA_EXP_REGION31_LUT_OFFSET 16 24 CM_BLNDGAM_RAMA_EXP_REGION31_NUM_SEGMENTS 28 30 regCM0_CM_BLNDGAM_RAMA_REGION_32_33 0 0xdad 4 0 2 CM_BLNDGAM_RAMA_EXP_REGION32_LUT_OFFSET 0 8 CM_BLNDGAM_RAMA_EXP_REGION32_NUM_SEGMENTS 12 14 CM_BLNDGAM_RAMA_EXP_REGION33_LUT_OFFSET 16 24 CM_BLNDGAM_RAMA_EXP_REGION33_NUM_SEGMENTS 28 30 regCM0_CM_BLNDGAM_RAMB_START_CNTL_B 0 0xdae 2 0 2 CM_BLNDGAM_RAMB_EXP_REGION_START_B 0 17 CM_BLNDGAM_RAMB_EXP_REGION_START_SEGMENT_B 20 26 regCM0_CM_BLNDGAM_RAMB_START_CNTL_G 0 0xdaf 2 0 2 CM_BLNDGAM_RAMB_EXP_REGION_START_G 0 17 CM_BLNDGAM_RAMB_EXP_REGION_START_SEGMENT_G 20 26 regCM0_CM_BLNDGAM_RAMB_START_CNTL_R 0 0xdb0 2 0 2 CM_BLNDGAM_RAMB_EXP_REGION_START_R 0 17 CM_BLNDGAM_RAMB_EXP_REGION_START_SEGMENT_R 20 26 regCM0_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_B 0 0xdb1 1 0 2 CM_BLNDGAM_RAMB_EXP_REGION_START_SLOPE_B 0 17 regCM0_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_G 0 0xdb2 1 0 2 CM_BLNDGAM_RAMB_EXP_REGION_START_SLOPE_G 0 17 regCM0_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_R 0 0xdb3 1 0 2 CM_BLNDGAM_RAMB_EXP_REGION_START_SLOPE_R 0 17 regCM0_CM_BLNDGAM_RAMB_START_BASE_CNTL_B 0 0xdb4 1 0 2 CM_BLNDGAM_RAMB_EXP_REGION_START_BASE_B 0 17 regCM0_CM_BLNDGAM_RAMB_START_BASE_CNTL_G 0 0xdb5 1 0 2 CM_BLNDGAM_RAMB_EXP_REGION_START_BASE_G 0 17 regCM0_CM_BLNDGAM_RAMB_START_BASE_CNTL_R 0 0xdb6 1 0 2 CM_BLNDGAM_RAMB_EXP_REGION_START_BASE_R 0 17 regCM0_CM_BLNDGAM_RAMB_END_CNTL1_B 0 0xdb7 1 0 2 CM_BLNDGAM_RAMB_EXP_REGION_END_BASE_B 0 17 regCM0_CM_BLNDGAM_RAMB_END_CNTL2_B 0 0xdb8 2 0 2 CM_BLNDGAM_RAMB_EXP_REGION_END_B 0 15 CM_BLNDGAM_RAMB_EXP_REGION_END_SLOPE_B 16 31 regCM0_CM_BLNDGAM_RAMB_END_CNTL1_G 0 0xdb9 1 0 2 CM_BLNDGAM_RAMB_EXP_REGION_END_BASE_G 0 17 regCM0_CM_BLNDGAM_RAMB_END_CNTL2_G 0 0xdba 2 0 2 CM_BLNDGAM_RAMB_EXP_REGION_END_G 0 15 CM_BLNDGAM_RAMB_EXP_REGION_END_SLOPE_G 16 31 regCM0_CM_BLNDGAM_RAMB_END_CNTL1_R 0 0xdbb 1 0 2 CM_BLNDGAM_RAMB_EXP_REGION_END_BASE_R 0 17 regCM0_CM_BLNDGAM_RAMB_END_CNTL2_R 0 0xdbc 2 0 2 CM_BLNDGAM_RAMB_EXP_REGION_END_R 0 15 CM_BLNDGAM_RAMB_EXP_REGION_END_SLOPE_R 16 31 regCM0_CM_BLNDGAM_RAMB_OFFSET_B 0 0xdbd 1 0 2 CM_BLNDGAM_RAMB_OFFSET_B 0 18 regCM0_CM_BLNDGAM_RAMB_OFFSET_G 0 0xdbe 1 0 2 CM_BLNDGAM_RAMB_OFFSET_G 0 18 regCM0_CM_BLNDGAM_RAMB_OFFSET_R 0 0xdbf 1 0 2 CM_BLNDGAM_RAMB_OFFSET_R 0 18 regCM0_CM_BLNDGAM_RAMB_REGION_0_1 0 0xdc0 4 0 2 CM_BLNDGAM_RAMB_EXP_REGION0_LUT_OFFSET 0 8 CM_BLNDGAM_RAMB_EXP_REGION0_NUM_SEGMENTS 12 14 CM_BLNDGAM_RAMB_EXP_REGION1_LUT_OFFSET 16 24 CM_BLNDGAM_RAMB_EXP_REGION1_NUM_SEGMENTS 28 30 regCM0_CM_BLNDGAM_RAMB_REGION_2_3 0 0xdc1 4 0 2 CM_BLNDGAM_RAMB_EXP_REGION2_LUT_OFFSET 0 8 CM_BLNDGAM_RAMB_EXP_REGION2_NUM_SEGMENTS 12 14 CM_BLNDGAM_RAMB_EXP_REGION3_LUT_OFFSET 16 24 CM_BLNDGAM_RAMB_EXP_REGION3_NUM_SEGMENTS 28 30 regCM0_CM_BLNDGAM_RAMB_REGION_4_5 0 0xdc2 4 0 2 CM_BLNDGAM_RAMB_EXP_REGION4_LUT_OFFSET 0 8 CM_BLNDGAM_RAMB_EXP_REGION4_NUM_SEGMENTS 12 14 CM_BLNDGAM_RAMB_EXP_REGION5_LUT_OFFSET 16 24 CM_BLNDGAM_RAMB_EXP_REGION5_NUM_SEGMENTS 28 30 regCM0_CM_BLNDGAM_RAMB_REGION_6_7 0 0xdc3 4 0 2 CM_BLNDGAM_RAMB_EXP_REGION6_LUT_OFFSET 0 8 CM_BLNDGAM_RAMB_EXP_REGION6_NUM_SEGMENTS 12 14 CM_BLNDGAM_RAMB_EXP_REGION7_LUT_OFFSET 16 24 CM_BLNDGAM_RAMB_EXP_REGION7_NUM_SEGMENTS 28 30 regCM0_CM_BLNDGAM_RAMB_REGION_8_9 0 0xdc4 4 0 2 CM_BLNDGAM_RAMB_EXP_REGION8_LUT_OFFSET 0 8 CM_BLNDGAM_RAMB_EXP_REGION8_NUM_SEGMENTS 12 14 CM_BLNDGAM_RAMB_EXP_REGION9_LUT_OFFSET 16 24 CM_BLNDGAM_RAMB_EXP_REGION9_NUM_SEGMENTS 28 30 regCM0_CM_BLNDGAM_RAMB_REGION_10_11 0 0xdc5 4 0 2 CM_BLNDGAM_RAMB_EXP_REGION10_LUT_OFFSET 0 8 CM_BLNDGAM_RAMB_EXP_REGION10_NUM_SEGMENTS 12 14 CM_BLNDGAM_RAMB_EXP_REGION11_LUT_OFFSET 16 24 CM_BLNDGAM_RAMB_EXP_REGION11_NUM_SEGMENTS 28 30 regCM0_CM_BLNDGAM_RAMB_REGION_12_13 0 0xdc6 4 0 2 CM_BLNDGAM_RAMB_EXP_REGION12_LUT_OFFSET 0 8 CM_BLNDGAM_RAMB_EXP_REGION12_NUM_SEGMENTS 12 14 CM_BLNDGAM_RAMB_EXP_REGION13_LUT_OFFSET 16 24 CM_BLNDGAM_RAMB_EXP_REGION13_NUM_SEGMENTS 28 30 regCM0_CM_BLNDGAM_RAMB_REGION_14_15 0 0xdc7 4 0 2 CM_BLNDGAM_RAMB_EXP_REGION14_LUT_OFFSET 0 8 CM_BLNDGAM_RAMB_EXP_REGION14_NUM_SEGMENTS 12 14 CM_BLNDGAM_RAMB_EXP_REGION15_LUT_OFFSET 16 24 CM_BLNDGAM_RAMB_EXP_REGION15_NUM_SEGMENTS 28 30 regCM0_CM_BLNDGAM_RAMB_REGION_16_17 0 0xdc8 4 0 2 CM_BLNDGAM_RAMB_EXP_REGION16_LUT_OFFSET 0 8 CM_BLNDGAM_RAMB_EXP_REGION16_NUM_SEGMENTS 12 14 CM_BLNDGAM_RAMB_EXP_REGION17_LUT_OFFSET 16 24 CM_BLNDGAM_RAMB_EXP_REGION17_NUM_SEGMENTS 28 30 regCM0_CM_BLNDGAM_RAMB_REGION_18_19 0 0xdc9 4 0 2 CM_BLNDGAM_RAMB_EXP_REGION18_LUT_OFFSET 0 8 CM_BLNDGAM_RAMB_EXP_REGION18_NUM_SEGMENTS 12 14 CM_BLNDGAM_RAMB_EXP_REGION19_LUT_OFFSET 16 24 CM_BLNDGAM_RAMB_EXP_REGION19_NUM_SEGMENTS 28 30 regCM0_CM_BLNDGAM_RAMB_REGION_20_21 0 0xdca 4 0 2 CM_BLNDGAM_RAMB_EXP_REGION20_LUT_OFFSET 0 8 CM_BLNDGAM_RAMB_EXP_REGION20_NUM_SEGMENTS 12 14 CM_BLNDGAM_RAMB_EXP_REGION21_LUT_OFFSET 16 24 CM_BLNDGAM_RAMB_EXP_REGION21_NUM_SEGMENTS 28 30 regCM0_CM_BLNDGAM_RAMB_REGION_22_23 0 0xdcb 4 0 2 CM_BLNDGAM_RAMB_EXP_REGION22_LUT_OFFSET 0 8 CM_BLNDGAM_RAMB_EXP_REGION22_NUM_SEGMENTS 12 14 CM_BLNDGAM_RAMB_EXP_REGION23_LUT_OFFSET 16 24 CM_BLNDGAM_RAMB_EXP_REGION23_NUM_SEGMENTS 28 30 regCM0_CM_BLNDGAM_RAMB_REGION_24_25 0 0xdcc 4 0 2 CM_BLNDGAM_RAMB_EXP_REGION24_LUT_OFFSET 0 8 CM_BLNDGAM_RAMB_EXP_REGION24_NUM_SEGMENTS 12 14 CM_BLNDGAM_RAMB_EXP_REGION25_LUT_OFFSET 16 24 CM_BLNDGAM_RAMB_EXP_REGION25_NUM_SEGMENTS 28 30 regCM0_CM_BLNDGAM_RAMB_REGION_26_27 0 0xdcd 4 0 2 CM_BLNDGAM_RAMB_EXP_REGION26_LUT_OFFSET 0 8 CM_BLNDGAM_RAMB_EXP_REGION26_NUM_SEGMENTS 12 14 CM_BLNDGAM_RAMB_EXP_REGION27_LUT_OFFSET 16 24 CM_BLNDGAM_RAMB_EXP_REGION27_NUM_SEGMENTS 28 30 regCM0_CM_BLNDGAM_RAMB_REGION_28_29 0 0xdce 4 0 2 CM_BLNDGAM_RAMB_EXP_REGION28_LUT_OFFSET 0 8 CM_BLNDGAM_RAMB_EXP_REGION28_NUM_SEGMENTS 12 14 CM_BLNDGAM_RAMB_EXP_REGION29_LUT_OFFSET 16 24 CM_BLNDGAM_RAMB_EXP_REGION29_NUM_SEGMENTS 28 30 regCM0_CM_BLNDGAM_RAMB_REGION_30_31 0 0xdcf 4 0 2 CM_BLNDGAM_RAMB_EXP_REGION30_LUT_OFFSET 0 8 CM_BLNDGAM_RAMB_EXP_REGION30_NUM_SEGMENTS 12 14 CM_BLNDGAM_RAMB_EXP_REGION31_LUT_OFFSET 16 24 CM_BLNDGAM_RAMB_EXP_REGION31_NUM_SEGMENTS 28 30 regCM0_CM_BLNDGAM_RAMB_REGION_32_33 0 0xdd0 4 0 2 CM_BLNDGAM_RAMB_EXP_REGION32_LUT_OFFSET 0 8 CM_BLNDGAM_RAMB_EXP_REGION32_NUM_SEGMENTS 12 14 CM_BLNDGAM_RAMB_EXP_REGION33_LUT_OFFSET 16 24 CM_BLNDGAM_RAMB_EXP_REGION33_NUM_SEGMENTS 28 30 regCM0_CM_HDR_MULT_COEF 0 0xdd1 1 0 2 CM_HDR_MULT_COEF 0 18 regCM0_CM_MEM_PWR_CTRL 0 0xdd2 4 0 2 GAMCOR_MEM_PWR_FORCE 0 1 GAMCOR_MEM_PWR_DIS 2 2 BLNDGAM_MEM_PWR_FORCE 4 5 BLNDGAM_MEM_PWR_DIS 6 6 regCM0_CM_MEM_PWR_STATUS 0 0xdd3 2 0 2 GAMCOR_MEM_PWR_STATE 0 1 BLNDGAM_MEM_PWR_STATE 2 3 regCM0_CM_DEALPHA 0 0xdd5 2 0 2 CM_DEALPHA_EN 0 0 CM_DEALPHA_ABLND 1 1 regCM0_CM_COEF_FORMAT 0 0xdd6 3 0 2 CM_BIAS_FORMAT 0 0 CM_POST_CSC_COEF_FORMAT 4 4 CM_GAMUT_REMAP_COEF_FORMAT 8 8 regCM0_CM_SHAPER_CONTROL 0 0xdd7 2 0 2 CM_SHAPER_LUT_MODE 0 1 CM_SHAPER_MODE_CURRENT 2 3 regCM0_CM_SHAPER_OFFSET_R 0 0xdd8 1 0 2 CM_SHAPER_OFFSET_R 0 18 regCM0_CM_SHAPER_OFFSET_G 0 0xdd9 1 0 2 CM_SHAPER_OFFSET_G 0 18 regCM0_CM_SHAPER_OFFSET_B 0 0xdda 1 0 2 CM_SHAPER_OFFSET_B 0 18 regCM0_CM_SHAPER_SCALE_R 0 0xddb 1 0 2 CM_SHAPER_SCALE_R 0 15 regCM0_CM_SHAPER_SCALE_G_B 0 0xddc 2 0 2 CM_SHAPER_SCALE_G 0 15 CM_SHAPER_SCALE_B 16 31 regCM0_CM_SHAPER_LUT_INDEX 0 0xddd 1 0 2 CM_SHAPER_LUT_INDEX 0 7 regCM0_CM_SHAPER_LUT_DATA 0 0xdde 1 0 2 CM_SHAPER_LUT_DATA 0 23 regCM0_CM_SHAPER_LUT_WRITE_EN_MASK 0 0xddf 2 0 2 CM_SHAPER_LUT_WRITE_EN_MASK 0 2 CM_SHAPER_LUT_WRITE_SEL 4 4 regCM0_CM_SHAPER_RAMA_START_CNTL_B 0 0xde0 2 0 2 CM_SHAPER_RAMA_EXP_REGION_START_B 0 17 CM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_B 20 26 regCM0_CM_SHAPER_RAMA_START_CNTL_G 0 0xde1 2 0 2 CM_SHAPER_RAMA_EXP_REGION_START_G 0 17 CM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_G 20 26 regCM0_CM_SHAPER_RAMA_START_CNTL_R 0 0xde2 2 0 2 CM_SHAPER_RAMA_EXP_REGION_START_R 0 17 CM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_R 20 26 regCM0_CM_SHAPER_RAMA_END_CNTL_B 0 0xde3 2 0 2 CM_SHAPER_RAMA_EXP_REGION_END_B 0 15 CM_SHAPER_RAMA_EXP_REGION_END_BASE_B 16 29 regCM0_CM_SHAPER_RAMA_END_CNTL_G 0 0xde4 2 0 2 CM_SHAPER_RAMA_EXP_REGION_END_G 0 15 CM_SHAPER_RAMA_EXP_REGION_END_BASE_G 16 29 regCM0_CM_SHAPER_RAMA_END_CNTL_R 0 0xde5 2 0 2 CM_SHAPER_RAMA_EXP_REGION_END_R 0 15 CM_SHAPER_RAMA_EXP_REGION_END_BASE_R 16 29 regCM0_CM_SHAPER_RAMA_REGION_0_1 0 0xde6 4 0 2 CM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET 0 8 CM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS 12 14 CM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET 16 24 CM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS 28 30 regCM0_CM_SHAPER_RAMA_REGION_2_3 0 0xde7 4 0 2 CM_SHAPER_RAMA_EXP_REGION2_LUT_OFFSET 0 8 CM_SHAPER_RAMA_EXP_REGION2_NUM_SEGMENTS 12 14 CM_SHAPER_RAMA_EXP_REGION3_LUT_OFFSET 16 24 CM_SHAPER_RAMA_EXP_REGION3_NUM_SEGMENTS 28 30 regCM0_CM_SHAPER_RAMA_REGION_4_5 0 0xde8 4 0 2 CM_SHAPER_RAMA_EXP_REGION4_LUT_OFFSET 0 8 CM_SHAPER_RAMA_EXP_REGION4_NUM_SEGMENTS 12 14 CM_SHAPER_RAMA_EXP_REGION5_LUT_OFFSET 16 24 CM_SHAPER_RAMA_EXP_REGION5_NUM_SEGMENTS 28 30 regCM0_CM_SHAPER_RAMA_REGION_6_7 0 0xde9 4 0 2 CM_SHAPER_RAMA_EXP_REGION6_LUT_OFFSET 0 8 CM_SHAPER_RAMA_EXP_REGION6_NUM_SEGMENTS 12 14 CM_SHAPER_RAMA_EXP_REGION7_LUT_OFFSET 16 24 CM_SHAPER_RAMA_EXP_REGION7_NUM_SEGMENTS 28 30 regCM0_CM_SHAPER_RAMA_REGION_8_9 0 0xdea 4 0 2 CM_SHAPER_RAMA_EXP_REGION8_LUT_OFFSET 0 8 CM_SHAPER_RAMA_EXP_REGION8_NUM_SEGMENTS 12 14 CM_SHAPER_RAMA_EXP_REGION9_LUT_OFFSET 16 24 CM_SHAPER_RAMA_EXP_REGION9_NUM_SEGMENTS 28 30 regCM0_CM_SHAPER_RAMA_REGION_10_11 0 0xdeb 4 0 2 CM_SHAPER_RAMA_EXP_REGION10_LUT_OFFSET 0 8 CM_SHAPER_RAMA_EXP_REGION10_NUM_SEGMENTS 12 14 CM_SHAPER_RAMA_EXP_REGION11_LUT_OFFSET 16 24 CM_SHAPER_RAMA_EXP_REGION11_NUM_SEGMENTS 28 30 regCM0_CM_SHAPER_RAMA_REGION_12_13 0 0xdec 4 0 2 CM_SHAPER_RAMA_EXP_REGION12_LUT_OFFSET 0 8 CM_SHAPER_RAMA_EXP_REGION12_NUM_SEGMENTS 12 14 CM_SHAPER_RAMA_EXP_REGION13_LUT_OFFSET 16 24 CM_SHAPER_RAMA_EXP_REGION13_NUM_SEGMENTS 28 30 regCM0_CM_SHAPER_RAMA_REGION_14_15 0 0xded 4 0 2 CM_SHAPER_RAMA_EXP_REGION14_LUT_OFFSET 0 8 CM_SHAPER_RAMA_EXP_REGION14_NUM_SEGMENTS 12 14 CM_SHAPER_RAMA_EXP_REGION15_LUT_OFFSET 16 24 CM_SHAPER_RAMA_EXP_REGION15_NUM_SEGMENTS 28 30 regCM0_CM_SHAPER_RAMA_REGION_16_17 0 0xdee 4 0 2 CM_SHAPER_RAMA_EXP_REGION16_LUT_OFFSET 0 8 CM_SHAPER_RAMA_EXP_REGION16_NUM_SEGMENTS 12 14 CM_SHAPER_RAMA_EXP_REGION17_LUT_OFFSET 16 24 CM_SHAPER_RAMA_EXP_REGION17_NUM_SEGMENTS 28 30 regCM0_CM_SHAPER_RAMA_REGION_18_19 0 0xdef 4 0 2 CM_SHAPER_RAMA_EXP_REGION18_LUT_OFFSET 0 8 CM_SHAPER_RAMA_EXP_REGION18_NUM_SEGMENTS 12 14 CM_SHAPER_RAMA_EXP_REGION19_LUT_OFFSET 16 24 CM_SHAPER_RAMA_EXP_REGION19_NUM_SEGMENTS 28 30 regCM0_CM_SHAPER_RAMA_REGION_20_21 0 0xdf0 4 0 2 CM_SHAPER_RAMA_EXP_REGION20_LUT_OFFSET 0 8 CM_SHAPER_RAMA_EXP_REGION20_NUM_SEGMENTS 12 14 CM_SHAPER_RAMA_EXP_REGION21_LUT_OFFSET 16 24 CM_SHAPER_RAMA_EXP_REGION21_NUM_SEGMENTS 28 30 regCM0_CM_SHAPER_RAMA_REGION_22_23 0 0xdf1 4 0 2 CM_SHAPER_RAMA_EXP_REGION22_LUT_OFFSET 0 8 CM_SHAPER_RAMA_EXP_REGION22_NUM_SEGMENTS 12 14 CM_SHAPER_RAMA_EXP_REGION23_LUT_OFFSET 16 24 CM_SHAPER_RAMA_EXP_REGION23_NUM_SEGMENTS 28 30 regCM0_CM_SHAPER_RAMA_REGION_24_25 0 0xdf2 4 0 2 CM_SHAPER_RAMA_EXP_REGION24_LUT_OFFSET 0 8 CM_SHAPER_RAMA_EXP_REGION24_NUM_SEGMENTS 12 14 CM_SHAPER_RAMA_EXP_REGION25_LUT_OFFSET 16 24 CM_SHAPER_RAMA_EXP_REGION25_NUM_SEGMENTS 28 30 regCM0_CM_SHAPER_RAMA_REGION_26_27 0 0xdf3 4 0 2 CM_SHAPER_RAMA_EXP_REGION26_LUT_OFFSET 0 8 CM_SHAPER_RAMA_EXP_REGION26_NUM_SEGMENTS 12 14 CM_SHAPER_RAMA_EXP_REGION27_LUT_OFFSET 16 24 CM_SHAPER_RAMA_EXP_REGION27_NUM_SEGMENTS 28 30 regCM0_CM_SHAPER_RAMA_REGION_28_29 0 0xdf4 4 0 2 CM_SHAPER_RAMA_EXP_REGION28_LUT_OFFSET 0 8 CM_SHAPER_RAMA_EXP_REGION28_NUM_SEGMENTS 12 14 CM_SHAPER_RAMA_EXP_REGION29_LUT_OFFSET 16 24 CM_SHAPER_RAMA_EXP_REGION29_NUM_SEGMENTS 28 30 regCM0_CM_SHAPER_RAMA_REGION_30_31 0 0xdf5 4 0 2 CM_SHAPER_RAMA_EXP_REGION30_LUT_OFFSET 0 8 CM_SHAPER_RAMA_EXP_REGION30_NUM_SEGMENTS 12 14 CM_SHAPER_RAMA_EXP_REGION31_LUT_OFFSET 16 24 CM_SHAPER_RAMA_EXP_REGION31_NUM_SEGMENTS 28 30 regCM0_CM_SHAPER_RAMA_REGION_32_33 0 0xdf6 4 0 2 CM_SHAPER_RAMA_EXP_REGION32_LUT_OFFSET 0 8 CM_SHAPER_RAMA_EXP_REGION32_NUM_SEGMENTS 12 14 CM_SHAPER_RAMA_EXP_REGION33_LUT_OFFSET 16 24 CM_SHAPER_RAMA_EXP_REGION33_NUM_SEGMENTS 28 30 regCM0_CM_SHAPER_RAMB_START_CNTL_B 0 0xdf7 2 0 2 CM_SHAPER_RAMB_EXP_REGION_START_B 0 17 CM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_B 20 26 regCM0_CM_SHAPER_RAMB_START_CNTL_G 0 0xdf8 2 0 2 CM_SHAPER_RAMB_EXP_REGION_START_G 0 17 CM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_G 20 26 regCM0_CM_SHAPER_RAMB_START_CNTL_R 0 0xdf9 2 0 2 CM_SHAPER_RAMB_EXP_REGION_START_R 0 17 CM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_R 20 26 regCM0_CM_SHAPER_RAMB_END_CNTL_B 0 0xdfa 2 0 2 CM_SHAPER_RAMB_EXP_REGION_END_B 0 15 CM_SHAPER_RAMB_EXP_REGION_END_BASE_B 16 29 regCM0_CM_SHAPER_RAMB_END_CNTL_G 0 0xdfb 2 0 2 CM_SHAPER_RAMB_EXP_REGION_END_G 0 15 CM_SHAPER_RAMB_EXP_REGION_END_BASE_G 16 29 regCM0_CM_SHAPER_RAMB_END_CNTL_R 0 0xdfc 2 0 2 CM_SHAPER_RAMB_EXP_REGION_END_R 0 15 CM_SHAPER_RAMB_EXP_REGION_END_BASE_R 16 29 regCM0_CM_SHAPER_RAMB_REGION_0_1 0 0xdfd 4 0 2 CM_SHAPER_RAMB_EXP_REGION0_LUT_OFFSET 0 8 CM_SHAPER_RAMB_EXP_REGION0_NUM_SEGMENTS 12 14 CM_SHAPER_RAMB_EXP_REGION1_LUT_OFFSET 16 24 CM_SHAPER_RAMB_EXP_REGION1_NUM_SEGMENTS 28 30 regCM0_CM_SHAPER_RAMB_REGION_2_3 0 0xdfe 4 0 2 CM_SHAPER_RAMB_EXP_REGION2_LUT_OFFSET 0 8 CM_SHAPER_RAMB_EXP_REGION2_NUM_SEGMENTS 12 14 CM_SHAPER_RAMB_EXP_REGION3_LUT_OFFSET 16 24 CM_SHAPER_RAMB_EXP_REGION3_NUM_SEGMENTS 28 30 regCM0_CM_SHAPER_RAMB_REGION_4_5 0 0xdff 4 0 2 CM_SHAPER_RAMB_EXP_REGION4_LUT_OFFSET 0 8 CM_SHAPER_RAMB_EXP_REGION4_NUM_SEGMENTS 12 14 CM_SHAPER_RAMB_EXP_REGION5_LUT_OFFSET 16 24 CM_SHAPER_RAMB_EXP_REGION5_NUM_SEGMENTS 28 30 regCM0_CM_SHAPER_RAMB_REGION_6_7 0 0xe00 4 0 2 CM_SHAPER_RAMB_EXP_REGION6_LUT_OFFSET 0 8 CM_SHAPER_RAMB_EXP_REGION6_NUM_SEGMENTS 12 14 CM_SHAPER_RAMB_EXP_REGION7_LUT_OFFSET 16 24 CM_SHAPER_RAMB_EXP_REGION7_NUM_SEGMENTS 28 30 regCM0_CM_SHAPER_RAMB_REGION_8_9 0 0xe01 4 0 2 CM_SHAPER_RAMB_EXP_REGION8_LUT_OFFSET 0 8 CM_SHAPER_RAMB_EXP_REGION8_NUM_SEGMENTS 12 14 CM_SHAPER_RAMB_EXP_REGION9_LUT_OFFSET 16 24 CM_SHAPER_RAMB_EXP_REGION9_NUM_SEGMENTS 28 30 regCM0_CM_SHAPER_RAMB_REGION_10_11 0 0xe02 4 0 2 CM_SHAPER_RAMB_EXP_REGION10_LUT_OFFSET 0 8 CM_SHAPER_RAMB_EXP_REGION10_NUM_SEGMENTS 12 14 CM_SHAPER_RAMB_EXP_REGION11_LUT_OFFSET 16 24 CM_SHAPER_RAMB_EXP_REGION11_NUM_SEGMENTS 28 30 regCM0_CM_SHAPER_RAMB_REGION_12_13 0 0xe03 4 0 2 CM_SHAPER_RAMB_EXP_REGION12_LUT_OFFSET 0 8 CM_SHAPER_RAMB_EXP_REGION12_NUM_SEGMENTS 12 14 CM_SHAPER_RAMB_EXP_REGION13_LUT_OFFSET 16 24 CM_SHAPER_RAMB_EXP_REGION13_NUM_SEGMENTS 28 30 regCM0_CM_SHAPER_RAMB_REGION_14_15 0 0xe04 4 0 2 CM_SHAPER_RAMB_EXP_REGION14_LUT_OFFSET 0 8 CM_SHAPER_RAMB_EXP_REGION14_NUM_SEGMENTS 12 14 CM_SHAPER_RAMB_EXP_REGION15_LUT_OFFSET 16 24 CM_SHAPER_RAMB_EXP_REGION15_NUM_SEGMENTS 28 30 regCM0_CM_SHAPER_RAMB_REGION_16_17 0 0xe05 4 0 2 CM_SHAPER_RAMB_EXP_REGION16_LUT_OFFSET 0 8 CM_SHAPER_RAMB_EXP_REGION16_NUM_SEGMENTS 12 14 CM_SHAPER_RAMB_EXP_REGION17_LUT_OFFSET 16 24 CM_SHAPER_RAMB_EXP_REGION17_NUM_SEGMENTS 28 30 regCM0_CM_SHAPER_RAMB_REGION_18_19 0 0xe06 4 0 2 CM_SHAPER_RAMB_EXP_REGION18_LUT_OFFSET 0 8 CM_SHAPER_RAMB_EXP_REGION18_NUM_SEGMENTS 12 14 CM_SHAPER_RAMB_EXP_REGION19_LUT_OFFSET 16 24 CM_SHAPER_RAMB_EXP_REGION19_NUM_SEGMENTS 28 30 regCM0_CM_SHAPER_RAMB_REGION_20_21 0 0xe07 4 0 2 CM_SHAPER_RAMB_EXP_REGION20_LUT_OFFSET 0 8 CM_SHAPER_RAMB_EXP_REGION20_NUM_SEGMENTS 12 14 CM_SHAPER_RAMB_EXP_REGION21_LUT_OFFSET 16 24 CM_SHAPER_RAMB_EXP_REGION21_NUM_SEGMENTS 28 30 regCM0_CM_SHAPER_RAMB_REGION_22_23 0 0xe08 4 0 2 CM_SHAPER_RAMB_EXP_REGION22_LUT_OFFSET 0 8 CM_SHAPER_RAMB_EXP_REGION22_NUM_SEGMENTS 12 14 CM_SHAPER_RAMB_EXP_REGION23_LUT_OFFSET 16 24 CM_SHAPER_RAMB_EXP_REGION23_NUM_SEGMENTS 28 30 regCM0_CM_SHAPER_RAMB_REGION_24_25 0 0xe09 4 0 2 CM_SHAPER_RAMB_EXP_REGION24_LUT_OFFSET 0 8 CM_SHAPER_RAMB_EXP_REGION24_NUM_SEGMENTS 12 14 CM_SHAPER_RAMB_EXP_REGION25_LUT_OFFSET 16 24 CM_SHAPER_RAMB_EXP_REGION25_NUM_SEGMENTS 28 30 regCM0_CM_SHAPER_RAMB_REGION_26_27 0 0xe0a 4 0 2 CM_SHAPER_RAMB_EXP_REGION26_LUT_OFFSET 0 8 CM_SHAPER_RAMB_EXP_REGION26_NUM_SEGMENTS 12 14 CM_SHAPER_RAMB_EXP_REGION27_LUT_OFFSET 16 24 CM_SHAPER_RAMB_EXP_REGION27_NUM_SEGMENTS 28 30 regCM0_CM_SHAPER_RAMB_REGION_28_29 0 0xe0b 4 0 2 CM_SHAPER_RAMB_EXP_REGION28_LUT_OFFSET 0 8 CM_SHAPER_RAMB_EXP_REGION28_NUM_SEGMENTS 12 14 CM_SHAPER_RAMB_EXP_REGION29_LUT_OFFSET 16 24 CM_SHAPER_RAMB_EXP_REGION29_NUM_SEGMENTS 28 30 regCM0_CM_SHAPER_RAMB_REGION_30_31 0 0xe0c 4 0 2 CM_SHAPER_RAMB_EXP_REGION30_LUT_OFFSET 0 8 CM_SHAPER_RAMB_EXP_REGION30_NUM_SEGMENTS 12 14 CM_SHAPER_RAMB_EXP_REGION31_LUT_OFFSET 16 24 CM_SHAPER_RAMB_EXP_REGION31_NUM_SEGMENTS 28 30 regCM0_CM_SHAPER_RAMB_REGION_32_33 0 0xe0d 4 0 2 CM_SHAPER_RAMB_EXP_REGION32_LUT_OFFSET 0 8 CM_SHAPER_RAMB_EXP_REGION32_NUM_SEGMENTS 12 14 CM_SHAPER_RAMB_EXP_REGION33_LUT_OFFSET 16 24 CM_SHAPER_RAMB_EXP_REGION33_NUM_SEGMENTS 28 30 regCM0_CM_MEM_PWR_CTRL2 0 0xe0e 4 0 2 SHAPER_MEM_PWR_FORCE 8 9 SHAPER_MEM_PWR_DIS 10 10 HDR3DLUT_MEM_PWR_FORCE 12 13 HDR3DLUT_MEM_PWR_DIS 14 14 regCM0_CM_MEM_PWR_STATUS2 0 0xe0f 2 0 2 SHAPER_MEM_PWR_STATE 4 5 HDR3DLUT_MEM_PWR_STATE 6 7 regCM0_CM_3DLUT_MODE 0 0xe10 3 0 2 CM_3DLUT_MODE 0 1 CM_3DLUT_SIZE 4 4 CM_3DLUT_MODE_CURRENT 8 9 regCM0_CM_3DLUT_INDEX 0 0xe11 1 0 2 CM_3DLUT_INDEX 0 10 regCM0_CM_3DLUT_DATA 0 0xe12 2 0 2 CM_3DLUT_DATA0 0 15 CM_3DLUT_DATA1 16 31 regCM0_CM_3DLUT_DATA_30BIT 0 0xe13 1 0 2 CM_3DLUT_DATA_30BIT 2 31 regCM0_CM_3DLUT_READ_WRITE_CONTROL 0 0xe14 4 0 2 CM_3DLUT_WRITE_EN_MASK 0 3 CM_3DLUT_RAM_SEL 4 4 CM_3DLUT_30BIT_EN 8 8 CM_3DLUT_READ_SEL 16 17 regCM0_CM_3DLUT_OUT_NORM_FACTOR 0 0xe15 1 0 2 CM_3DLUT_OUT_NORM_FACTOR 0 15 regCM0_CM_3DLUT_OUT_OFFSET_R 0 0xe16 2 0 2 CM_3DLUT_OUT_OFFSET_R 0 15 CM_3DLUT_OUT_SCALE_R 16 31 regCM0_CM_3DLUT_OUT_OFFSET_G 0 0xe17 2 0 2 CM_3DLUT_OUT_OFFSET_G 0 15 CM_3DLUT_OUT_SCALE_G 16 31 regCM0_CM_3DLUT_OUT_OFFSET_B 0 0xe18 2 0 2 CM_3DLUT_OUT_OFFSET_B 0 15 CM_3DLUT_OUT_SCALE_B 16 31 regCM0_CM_TEST_DEBUG_INDEX 0 0xe19 2 0 2 CM_TEST_DEBUG_INDEX 0 7 CM_TEST_DEBUG_WRITE_EN 8 8 regCM0_CM_TEST_DEBUG_DATA 0 0xe1a 1 0 2 CM_TEST_DEBUG_DATA 0 31 regDPP_TOP0_DPP_CONTROL 0 0xcc5 8 0 2 DPP_CLOCK_ENABLE 4 4 DPPCLK_G_GATE_DISABLE 8 8 DPPCLK_G_DYN_GATE_DISABLE 10 10 DPPCLK_G_DSCL_GATE_DISABLE 12 12 DPPCLK_R_GATE_DISABLE 14 14 DISPCLK_R_GATE_DISABLE 16 16 DISPCLK_G_GATE_DISABLE 18 18 DPP_TEST_CLK_SEL 28 30 regDPP_TOP0_DPP_SOFT_RESET 0 0xcc6 4 0 2 CNVC_SOFT_RESET 0 0 DSCL_SOFT_RESET 4 4 CM_SOFT_RESET 8 8 OBUF_SOFT_RESET 12 12 regDPP_TOP0_DPP_CRC_VAL_R_G 0 0xcc7 2 0 2 DPP_CRC_R_CR 0 15 DPP_CRC_G_Y 16 31 regDPP_TOP0_DPP_CRC_VAL_B_A 0 0xcc8 2 0 2 DPP_CRC_B_CB 0 15 DPP_CRC_ALPHA 16 31 regDPP_TOP0_DPP_CRC_CTRL 0 0xcc9 11 0 2 DPP_CRC_EN 0 0 DPP_CRC_CONT_EN 1 1 DPP_CRC_ONE_SHOT_PENDING 2 2 DPP_CRC_420_COMP_SEL 3 3 DPP_CRC_SRC_SEL 4 5 DPP_CRC_STEREO_EN 6 6 DPP_CRC_STEREO_MODE 7 8 DPP_CRC_INTERLACE_MODE 9 10 DPP_CRC_PIX_FORMAT_SEL 11 13 DPP_CRC_CURSOR_FORMAT_SEL 14 15 DPP_CRC_MASK 16 31 regDPP_TOP0_HOST_READ_CONTROL 0 0xcca 1 0 2 HOST_READ_RATE_CONTROL 0 7 regDC_PERFMON11_PERFCOUNTER_CNTL 0 0xe24 11 0 2 PERFCOUNTER_EVENT_SEL 0 8 PERFCOUNTER_CVALUE_SEL 9 11 PERFCOUNTER_INC_MODE 12 14 PERFCOUNTER_HW_CNTL_SEL 15 15 PERFCOUNTER_RUNEN_MODE 16 16 PERFCOUNTER_CNTOFF_START_DIS 22 22 PERFCOUNTER_RESTART_EN 23 23 PERFCOUNTER_INT_EN 24 24 PERFCOUNTER_OFF_MASK 25 25 PERFCOUNTER_ACTIVE 26 26 PERFCOUNTER_CNTL_SEL 29 31 regDC_PERFMON11_PERFCOUNTER_CNTL2 0 0xe25 5 0 2 PERFCOUNTER_COUNTED_VALUE_TYPE 0 1 PERFCOUNTER_HW_STOP1_SEL 2 2 PERFCOUNTER_HW_STOP2_SEL 3 3 PERFCOUNTER_CNTOFF_SEL 8 13 PERFCOUNTER_CNTL2_SEL 29 31 regDC_PERFMON11_PERFCOUNTER_STATE 0 0xe26 16 0 2 PERFCOUNTER_CNT0_STATE 0 1 PERFCOUNTER_STATE_SEL0 2 2 PERFCOUNTER_CNT1_STATE 4 5 PERFCOUNTER_STATE_SEL1 6 6 PERFCOUNTER_CNT2_STATE 8 9 PERFCOUNTER_STATE_SEL2 10 10 PERFCOUNTER_CNT3_STATE 12 13 PERFCOUNTER_STATE_SEL3 14 14 PERFCOUNTER_CNT4_STATE 16 17 PERFCOUNTER_STATE_SEL4 18 18 PERFCOUNTER_CNT5_STATE 20 21 PERFCOUNTER_STATE_SEL5 22 22 PERFCOUNTER_CNT6_STATE 24 25 PERFCOUNTER_STATE_SEL6 26 26 PERFCOUNTER_CNT7_STATE 28 29 PERFCOUNTER_STATE_SEL7 30 30 regDC_PERFMON11_PERFMON_CNTL 0 0xe27 6 0 2 PERFMON_STATE 0 1 PERFMON_RPT_COUNT 8 27 PERFMON_CNTOFF_AND_OR 28 28 PERFMON_CNTOFF_INT_EN 29 29 PERFMON_CNTOFF_INT_STATUS 30 30 PERFMON_CNTOFF_INT_ACK 31 31 regDC_PERFMON11_PERFMON_CNTL2 0 0xe28 4 0 2 PERFMON_CNTOFF_INT_TYPE 0 0 PERFMON_CLK_ENABLE 1 1 PERFMON_RUN_ENABLE_START_SEL 2 9 PERFMON_RUN_ENABLE_STOP_SEL 10 17 regDC_PERFMON11_PERFMON_CVALUE_INT_MISC 0 0xe29 17 0 2 PERFCOUNTER_INT0_STATUS 0 0 PERFCOUNTER_INT1_STATUS 1 1 PERFCOUNTER_INT2_STATUS 2 2 PERFCOUNTER_INT3_STATUS 3 3 PERFCOUNTER_INT4_STATUS 4 4 PERFCOUNTER_INT5_STATUS 5 5 PERFCOUNTER_INT6_STATUS 6 6 PERFCOUNTER_INT7_STATUS 7 7 PERFCOUNTER_INT0_ACK 8 8 PERFCOUNTER_INT1_ACK 9 9 PERFCOUNTER_INT2_ACK 10 10 PERFCOUNTER_INT3_ACK 11 11 PERFCOUNTER_INT4_ACK 12 12 PERFCOUNTER_INT5_ACK 13 13 PERFCOUNTER_INT6_ACK 14 14 PERFCOUNTER_INT7_ACK 15 15 PERFMON_CVALUE_HI 16 31 regDC_PERFMON11_PERFMON_CVALUE_LOW 0 0xe2a 1 0 2 PERFMON_CVALUE_LOW 0 31 regDC_PERFMON11_PERFMON_HI 0 0xe2b 2 0 2 PERFMON_HI 0 15 PERFMON_READ_SEL 29 31 regDC_PERFMON11_PERFMON_LOW 0 0xe2c 1 0 2 PERFMON_LOW 0 31 regCNVC_CFG1_CNVC_SURFACE_PIXEL_FORMAT 0 0xe3a 2 0 2 CNVC_SURFACE_PIXEL_FORMAT 0 6 CNVC_ALPHA_PLANE_ENABLE 8 8 regCNVC_CFG1_FORMAT_CONTROL 0 0xe3b 11 0 2 FORMAT_EXPANSION_MODE 0 0 FORMAT_CNV16 4 4 ALPHA_EN 8 8 CNVC_BYPASS 12 12 CNVC_BYPASS_MSB_ALIGN 13 13 CLAMP_POSITIVE 16 16 CLAMP_POSITIVE_C 17 17 CNVC_UPDATE_PENDING 20 20 FORMAT_CROSSBAR_R 24 25 FORMAT_CROSSBAR_G 26 27 FORMAT_CROSSBAR_B 28 29 regCNVC_CFG1_FCNV_FP_BIAS_R 0 0xe3c 1 0 2 FCNV_FP_BIAS_R 0 18 regCNVC_CFG1_FCNV_FP_BIAS_G 0 0xe3d 1 0 2 FCNV_FP_BIAS_G 0 18 regCNVC_CFG1_FCNV_FP_BIAS_B 0 0xe3e 1 0 2 FCNV_FP_BIAS_B 0 18 regCNVC_CFG1_FCNV_FP_SCALE_R 0 0xe3f 1 0 2 FCNV_FP_SCALE_R 0 18 regCNVC_CFG1_FCNV_FP_SCALE_G 0 0xe40 1 0 2 FCNV_FP_SCALE_G 0 18 regCNVC_CFG1_FCNV_FP_SCALE_B 0 0xe41 1 0 2 FCNV_FP_SCALE_B 0 18 regCNVC_CFG1_COLOR_KEYER_CONTROL 0 0xe42 2 0 2 COLOR_KEYER_EN 0 0 COLOR_KEYER_MODE 4 5 regCNVC_CFG1_COLOR_KEYER_ALPHA 0 0xe43 2 0 2 COLOR_KEYER_ALPHA_LOW 0 15 COLOR_KEYER_ALPHA_HIGH 16 31 regCNVC_CFG1_COLOR_KEYER_RED 0 0xe44 2 0 2 COLOR_KEYER_RED_LOW 0 15 COLOR_KEYER_RED_HIGH 16 31 regCNVC_CFG1_COLOR_KEYER_GREEN 0 0xe45 2 0 2 COLOR_KEYER_GREEN_LOW 0 15 COLOR_KEYER_GREEN_HIGH 16 31 regCNVC_CFG1_COLOR_KEYER_BLUE 0 0xe46 2 0 2 COLOR_KEYER_BLUE_LOW 0 15 COLOR_KEYER_BLUE_HIGH 16 31 regCNVC_CFG1_ALPHA_2BIT_LUT 0 0xe48 4 0 2 ALPHA_2BIT_LUT0 0 7 ALPHA_2BIT_LUT1 8 15 ALPHA_2BIT_LUT2 16 23 ALPHA_2BIT_LUT3 24 31 regCNVC_CFG1_PRE_DEALPHA 0 0xe49 2 0 2 PRE_DEALPHA_EN 0 0 PRE_DEALPHA_ABLND_EN 4 4 regCNVC_CFG1_PRE_CSC_MODE 0 0xe4a 2 0 2 PRE_CSC_MODE 0 1 PRE_CSC_MODE_CURRENT 2 3 regCNVC_CFG1_PRE_CSC_C11_C12 0 0xe4b 2 0 2 PRE_CSC_C11 0 15 PRE_CSC_C12 16 31 regCNVC_CFG1_PRE_CSC_C13_C14 0 0xe4c 2 0 2 PRE_CSC_C13 0 15 PRE_CSC_C14 16 31 regCNVC_CFG1_PRE_CSC_C21_C22 0 0xe4d 2 0 2 PRE_CSC_C21 0 15 PRE_CSC_C22 16 31 regCNVC_CFG1_PRE_CSC_C23_C24 0 0xe4e 2 0 2 PRE_CSC_C23 0 15 PRE_CSC_C24 16 31 regCNVC_CFG1_PRE_CSC_C31_C32 0 0xe4f 2 0 2 PRE_CSC_C31 0 15 PRE_CSC_C32 16 31 regCNVC_CFG1_PRE_CSC_C33_C34 0 0xe50 2 0 2 PRE_CSC_C33 0 15 PRE_CSC_C34 16 31 regCNVC_CFG1_PRE_CSC_B_C11_C12 0 0xe51 2 0 2 PRE_CSC_B_C11 0 15 PRE_CSC_B_C12 16 31 regCNVC_CFG1_PRE_CSC_B_C13_C14 0 0xe52 2 0 2 PRE_CSC_B_C13 0 15 PRE_CSC_B_C14 16 31 regCNVC_CFG1_PRE_CSC_B_C21_C22 0 0xe53 2 0 2 PRE_CSC_B_C21 0 15 PRE_CSC_B_C22 16 31 regCNVC_CFG1_PRE_CSC_B_C23_C24 0 0xe54 2 0 2 PRE_CSC_B_C23 0 15 PRE_CSC_B_C24 16 31 regCNVC_CFG1_PRE_CSC_B_C31_C32 0 0xe55 2 0 2 PRE_CSC_B_C31 0 15 PRE_CSC_B_C32 16 31 regCNVC_CFG1_PRE_CSC_B_C33_C34 0 0xe56 2 0 2 PRE_CSC_B_C33 0 15 PRE_CSC_B_C34 16 31 regCNVC_CFG1_CNVC_COEF_FORMAT 0 0xe57 1 0 2 PRE_CSC_COEF_FORMAT 0 0 regCNVC_CFG1_PRE_DEGAM 0 0xe58 2 0 2 PRE_DEGAM_MODE 0 1 PRE_DEGAM_SELECT 4 6 regCNVC_CFG1_PRE_REALPHA 0 0xe59 2 0 2 PRE_REALPHA_EN 0 0 PRE_REALPHA_ABLND_EN 4 4 regCNVC_CUR1_CURSOR0_CONTROL 0 0xe5c 7 0 2 CUR0_ENABLE 0 0 CUR0_EXPANSION_MODE 1 1 CUR0_PIX_INV_MODE 2 2 CUR0_ROM_EN 3 3 CUR0_MODE 4 6 CUR0_PIXEL_ALPHA_MOD_EN 7 7 CUR0_UPDATE_PENDING 16 16 regCNVC_CUR1_CURSOR0_COLOR0 0 0xe5d 1 0 2 CUR0_COLOR0 0 23 regCNVC_CUR1_CURSOR0_COLOR1 0 0xe5e 1 0 2 CUR0_COLOR1 0 23 regCNVC_CUR1_CURSOR0_FP_SCALE_BIAS 0 0xe5f 2 0 2 CUR0_FP_SCALE 0 15 CUR0_FP_BIAS 16 31 regDSCL1_SCL_COEF_RAM_TAP_SELECT 0 0xe64 3 0 2 SCL_COEF_RAM_TAP_PAIR_IDX 0 1 SCL_COEF_RAM_PHASE 8 13 SCL_COEF_RAM_FILTER_TYPE 16 18 regDSCL1_SCL_COEF_RAM_TAP_DATA 0 0xe65 4 0 2 SCL_COEF_RAM_EVEN_TAP_COEF 0 13 SCL_COEF_RAM_EVEN_TAP_COEF_EN 15 15 SCL_COEF_RAM_ODD_TAP_COEF 16 29 SCL_COEF_RAM_ODD_TAP_COEF_EN 31 31 regDSCL1_SCL_MODE 0 0xe66 6 0 2 DSCL_MODE 0 2 SCL_COEF_RAM_SELECT 8 8 SCL_COEF_RAM_SELECT_CURRENT 12 12 SCL_CHROMA_COEF_MODE 16 16 SCL_ALPHA_COEF_MODE 20 20 SCL_COEF_RAM_SELECT_RD 24 24 regDSCL1_SCL_TAP_CONTROL 0 0xe67 4 0 2 SCL_V_NUM_TAPS 0 2 SCL_H_NUM_TAPS 4 6 SCL_V_NUM_TAPS_C 8 10 SCL_H_NUM_TAPS_C 12 14 regDSCL1_DSCL_CONTROL 0 0xe68 1 0 2 SCL_BOUNDARY_MODE 0 0 regDSCL1_DSCL_2TAP_CONTROL 0 0xe69 6 0 2 SCL_H_2TAP_HARDCODE_COEF_EN 0 0 SCL_H_2TAP_SHARP_EN 4 4 SCL_H_2TAP_SHARP_FACTOR 8 10 SCL_V_2TAP_HARDCODE_COEF_EN 16 16 SCL_V_2TAP_SHARP_EN 20 20 SCL_V_2TAP_SHARP_FACTOR 24 26 regDSCL1_SCL_MANUAL_REPLICATE_CONTROL 0 0xe6a 2 0 2 SCL_V_MANUAL_REPLICATE_FACTOR 0 3 SCL_H_MANUAL_REPLICATE_FACTOR 8 11 regDSCL1_SCL_HORZ_FILTER_SCALE_RATIO 0 0xe6b 1 0 2 SCL_H_SCALE_RATIO 0 26 regDSCL1_SCL_HORZ_FILTER_INIT 0 0xe6c 2 0 2 SCL_H_INIT_FRAC 0 23 SCL_H_INIT_INT 24 27 regDSCL1_SCL_HORZ_FILTER_SCALE_RATIO_C 0 0xe6d 1 0 2 SCL_H_SCALE_RATIO_C 0 26 regDSCL1_SCL_HORZ_FILTER_INIT_C 0 0xe6e 2 0 2 SCL_H_INIT_FRAC_C 0 23 SCL_H_INIT_INT_C 24 27 regDSCL1_SCL_VERT_FILTER_SCALE_RATIO 0 0xe6f 1 0 2 SCL_V_SCALE_RATIO 0 26 regDSCL1_SCL_VERT_FILTER_INIT 0 0xe70 2 0 2 SCL_V_INIT_FRAC 0 23 SCL_V_INIT_INT 24 27 regDSCL1_SCL_VERT_FILTER_INIT_BOT 0 0xe71 2 0 2 SCL_V_INIT_FRAC_BOT 0 23 SCL_V_INIT_INT_BOT 24 27 regDSCL1_SCL_VERT_FILTER_SCALE_RATIO_C 0 0xe72 1 0 2 SCL_V_SCALE_RATIO_C 0 26 regDSCL1_SCL_VERT_FILTER_INIT_C 0 0xe73 2 0 2 SCL_V_INIT_FRAC_C 0 23 SCL_V_INIT_INT_C 24 27 regDSCL1_SCL_VERT_FILTER_INIT_BOT_C 0 0xe74 2 0 2 SCL_V_INIT_FRAC_BOT_C 0 23 SCL_V_INIT_INT_BOT_C 24 27 regDSCL1_SCL_BLACK_COLOR 0 0xe75 2 0 2 SCL_BLACK_COLOR_RGB_Y 0 15 SCL_BLACK_COLOR_CBCR 16 31 regDSCL1_DSCL_UPDATE 0 0xe76 1 0 2 SCL_UPDATE_PENDING 0 0 regDSCL1_DSCL_AUTOCAL 0 0xe77 3 0 2 AUTOCAL_MODE 0 1 AUTOCAL_NUM_PIPE 8 9 AUTOCAL_PIPE_ID 12 13 regDSCL1_DSCL_EXT_OVERSCAN_LEFT_RIGHT 0 0xe78 2 0 2 EXT_OVERSCAN_RIGHT 0 12 EXT_OVERSCAN_LEFT 16 28 regDSCL1_DSCL_EXT_OVERSCAN_TOP_BOTTOM 0 0xe79 2 0 2 EXT_OVERSCAN_BOTTOM 0 12 EXT_OVERSCAN_TOP 16 28 regDSCL1_OTG_H_BLANK 0 0xe7a 2 0 2 OTG_H_BLANK_START 0 13 OTG_H_BLANK_END 16 29 regDSCL1_OTG_V_BLANK 0 0xe7b 2 0 2 OTG_V_BLANK_START 0 13 OTG_V_BLANK_END 16 29 regDSCL1_RECOUT_START 0 0xe7c 2 0 2 RECOUT_START_X 0 12 RECOUT_START_Y 16 28 regDSCL1_RECOUT_SIZE 0 0xe7d 2 0 2 RECOUT_WIDTH 0 13 RECOUT_HEIGHT 16 29 regDSCL1_MPC_SIZE 0 0xe7e 2 0 2 MPC_WIDTH 0 13 MPC_HEIGHT 16 29 regDSCL1_LB_DATA_FORMAT 0 0xe7f 2 0 2 INTERLEAVE_EN 0 0 ALPHA_EN 4 4 regDSCL1_LB_MEMORY_CTRL 0 0xe80 4 0 2 MEMORY_CONFIG 0 1 LB_MAX_PARTITIONS 8 13 LB_NUM_PARTITIONS 16 22 LB_NUM_PARTITIONS_C 24 30 regDSCL1_LB_V_COUNTER 0 0xe81 2 0 2 V_COUNTER 0 12 V_COUNTER_C 16 28 regDSCL1_DSCL_MEM_PWR_CTRL 0 0xe82 15 0 2 LUT_MEM_PWR_FORCE 0 1 LUT_MEM_PWR_DIS 2 2 LB_G1_MEM_PWR_FORCE 4 5 LB_G1_MEM_PWR_DIS 6 6 LB_G2_MEM_PWR_FORCE 8 9 LB_G2_MEM_PWR_DIS 10 10 LB_G3_MEM_PWR_FORCE 12 13 LB_G3_MEM_PWR_DIS 14 14 LB_G4_MEM_PWR_FORCE 16 17 LB_G4_MEM_PWR_DIS 18 18 LB_G5_MEM_PWR_FORCE 20 21 LB_G5_MEM_PWR_DIS 22 22 LB_G6_MEM_PWR_FORCE 24 25 LB_G6_MEM_PWR_DIS 26 26 LB_MEM_PWR_MODE 28 28 regDSCL1_DSCL_MEM_PWR_STATUS 0 0xe83 7 0 2 LUT_MEM_PWR_STATE 0 1 LB_G1_MEM_PWR_STATE 2 3 LB_G2_MEM_PWR_STATE 4 5 LB_G3_MEM_PWR_STATE 6 7 LB_G4_MEM_PWR_STATE 8 9 LB_G5_MEM_PWR_STATE 10 11 LB_G6_MEM_PWR_STATE 12 13 regDSCL1_OBUF_CONTROL 0 0xe84 4 0 2 OBUF_BYPASS 0 0 OBUF_USE_FULL_BUFFER 1 1 OBUF_IS_HALF_RECOUT_WIDTH 2 2 OBUF_OUT_HOLD_CNT 4 7 regDSCL1_OBUF_MEM_PWR_CTRL 0 0xe85 4 0 2 OBUF_MEM_PWR_FORCE 0 1 OBUF_MEM_PWR_DIS 2 2 OBUF_MEM_PWR_MODE 8 8 OBUF_MEM_PWR_STATE 16 17 regCM1_CM_CONTROL 0 0xe8b 2 0 2 CM_BYPASS 0 0 CM_UPDATE_PENDING 8 8 regCM1_CM_POST_CSC_CONTROL 0 0xe8c 2 0 2 CM_POST_CSC_MODE 0 1 CM_POST_CSC_MODE_CURRENT 2 3 regCM1_CM_POST_CSC_C11_C12 0 0xe8d 2 0 2 CM_POST_CSC_C11 0 15 CM_POST_CSC_C12 16 31 regCM1_CM_POST_CSC_C13_C14 0 0xe8e 2 0 2 CM_POST_CSC_C13 0 15 CM_POST_CSC_C14 16 31 regCM1_CM_POST_CSC_C21_C22 0 0xe8f 2 0 2 CM_POST_CSC_C21 0 15 CM_POST_CSC_C22 16 31 regCM1_CM_POST_CSC_C23_C24 0 0xe90 2 0 2 CM_POST_CSC_C23 0 15 CM_POST_CSC_C24 16 31 regCM1_CM_POST_CSC_C31_C32 0 0xe91 2 0 2 CM_POST_CSC_C31 0 15 CM_POST_CSC_C32 16 31 regCM1_CM_POST_CSC_C33_C34 0 0xe92 2 0 2 CM_POST_CSC_C33 0 15 CM_POST_CSC_C34 16 31 regCM1_CM_POST_CSC_B_C11_C12 0 0xe93 2 0 2 CM_POST_CSC_B_C11 0 15 CM_POST_CSC_B_C12 16 31 regCM1_CM_POST_CSC_B_C13_C14 0 0xe94 2 0 2 CM_POST_CSC_B_C13 0 15 CM_POST_CSC_B_C14 16 31 regCM1_CM_POST_CSC_B_C21_C22 0 0xe95 2 0 2 CM_POST_CSC_B_C21 0 15 CM_POST_CSC_B_C22 16 31 regCM1_CM_POST_CSC_B_C23_C24 0 0xe96 2 0 2 CM_POST_CSC_B_C23 0 15 CM_POST_CSC_B_C24 16 31 regCM1_CM_POST_CSC_B_C31_C32 0 0xe97 2 0 2 CM_POST_CSC_B_C31 0 15 CM_POST_CSC_B_C32 16 31 regCM1_CM_POST_CSC_B_C33_C34 0 0xe98 2 0 2 CM_POST_CSC_B_C33 0 15 CM_POST_CSC_B_C34 16 31 regCM1_CM_GAMUT_REMAP_CONTROL 0 0xe99 2 0 2 CM_GAMUT_REMAP_MODE 0 1 CM_GAMUT_REMAP_MODE_CURRENT 2 3 regCM1_CM_GAMUT_REMAP_C11_C12 0 0xe9a 2 0 2 CM_GAMUT_REMAP_C11 0 15 CM_GAMUT_REMAP_C12 16 31 regCM1_CM_GAMUT_REMAP_C13_C14 0 0xe9b 2 0 2 CM_GAMUT_REMAP_C13 0 15 CM_GAMUT_REMAP_C14 16 31 regCM1_CM_GAMUT_REMAP_C21_C22 0 0xe9c 2 0 2 CM_GAMUT_REMAP_C21 0 15 CM_GAMUT_REMAP_C22 16 31 regCM1_CM_GAMUT_REMAP_C23_C24 0 0xe9d 2 0 2 CM_GAMUT_REMAP_C23 0 15 CM_GAMUT_REMAP_C24 16 31 regCM1_CM_GAMUT_REMAP_C31_C32 0 0xe9e 2 0 2 CM_GAMUT_REMAP_C31 0 15 CM_GAMUT_REMAP_C32 16 31 regCM1_CM_GAMUT_REMAP_C33_C34 0 0xe9f 2 0 2 CM_GAMUT_REMAP_C33 0 15 CM_GAMUT_REMAP_C34 16 31 regCM1_CM_GAMUT_REMAP_B_C11_C12 0 0xea0 2 0 2 CM_GAMUT_REMAP_B_C11 0 15 CM_GAMUT_REMAP_B_C12 16 31 regCM1_CM_GAMUT_REMAP_B_C13_C14 0 0xea1 2 0 2 CM_GAMUT_REMAP_B_C13 0 15 CM_GAMUT_REMAP_B_C14 16 31 regCM1_CM_GAMUT_REMAP_B_C21_C22 0 0xea2 2 0 2 CM_GAMUT_REMAP_B_C21 0 15 CM_GAMUT_REMAP_B_C22 16 31 regCM1_CM_GAMUT_REMAP_B_C23_C24 0 0xea3 2 0 2 CM_GAMUT_REMAP_B_C23 0 15 CM_GAMUT_REMAP_B_C24 16 31 regCM1_CM_GAMUT_REMAP_B_C31_C32 0 0xea4 2 0 2 CM_GAMUT_REMAP_B_C31 0 15 CM_GAMUT_REMAP_B_C32 16 31 regCM1_CM_GAMUT_REMAP_B_C33_C34 0 0xea5 2 0 2 CM_GAMUT_REMAP_B_C33 0 15 CM_GAMUT_REMAP_B_C34 16 31 regCM1_CM_BIAS_CR_R 0 0xea6 1 0 2 CM_BIAS_CR_R 0 15 regCM1_CM_BIAS_Y_G_CB_B 0 0xea7 2 0 2 CM_BIAS_Y_G 0 15 CM_BIAS_CB_B 16 31 regCM1_CM_GAMCOR_CONTROL 0 0xea8 5 0 2 CM_GAMCOR_MODE 0 1 CM_GAMCOR_SELECT 2 2 CM_GAMCOR_PWL_DISABLE 3 3 CM_GAMCOR_MODE_CURRENT 4 5 CM_GAMCOR_SELECT_CURRENT 6 6 regCM1_CM_GAMCOR_LUT_INDEX 0 0xea9 1 0 2 CM_GAMCOR_LUT_INDEX 0 8 regCM1_CM_GAMCOR_LUT_DATA 0 0xeaa 1 0 2 CM_GAMCOR_LUT_DATA 0 17 regCM1_CM_GAMCOR_LUT_CONTROL 0 0xeab 5 0 2 CM_GAMCOR_LUT_WRITE_COLOR_MASK 0 2 CM_GAMCOR_LUT_READ_COLOR_SEL 3 4 CM_GAMCOR_LUT_READ_DBG 5 5 CM_GAMCOR_LUT_HOST_SEL 6 6 CM_GAMCOR_LUT_CONFIG_MODE 7 7 regCM1_CM_GAMCOR_RAMA_START_CNTL_B 0 0xeac 2 0 2 CM_GAMCOR_RAMA_EXP_REGION_START_B 0 17 CM_GAMCOR_RAMA_EXP_REGION_START_SEGMENT_B 20 26 regCM1_CM_GAMCOR_RAMA_START_CNTL_G 0 0xead 2 0 2 CM_GAMCOR_RAMA_EXP_REGION_START_G 0 17 CM_GAMCOR_RAMA_EXP_REGION_START_SEGMENT_G 20 26 regCM1_CM_GAMCOR_RAMA_START_CNTL_R 0 0xeae 2 0 2 CM_GAMCOR_RAMA_EXP_REGION_START_R 0 17 CM_GAMCOR_RAMA_EXP_REGION_START_SEGMENT_R 20 26 regCM1_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B 0 0xeaf 1 0 2 CM_GAMCOR_RAMA_EXP_REGION_START_SLOPE_B 0 17 regCM1_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G 0 0xeb0 1 0 2 CM_GAMCOR_RAMA_EXP_REGION_START_SLOPE_G 0 17 regCM1_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R 0 0xeb1 1 0 2 CM_GAMCOR_RAMA_EXP_REGION_START_SLOPE_R 0 17 regCM1_CM_GAMCOR_RAMA_START_BASE_CNTL_B 0 0xeb2 1 0 2 CM_GAMCOR_RAMA_EXP_REGION_START_BASE_B 0 17 regCM1_CM_GAMCOR_RAMA_START_BASE_CNTL_G 0 0xeb3 1 0 2 CM_GAMCOR_RAMA_EXP_REGION_START_BASE_G 0 17 regCM1_CM_GAMCOR_RAMA_START_BASE_CNTL_R 0 0xeb4 1 0 2 CM_GAMCOR_RAMA_EXP_REGION_START_BASE_R 0 17 regCM1_CM_GAMCOR_RAMA_END_CNTL1_B 0 0xeb5 1 0 2 CM_GAMCOR_RAMA_EXP_REGION_END_BASE_B 0 17 regCM1_CM_GAMCOR_RAMA_END_CNTL2_B 0 0xeb6 2 0 2 CM_GAMCOR_RAMA_EXP_REGION_END_B 0 15 CM_GAMCOR_RAMA_EXP_REGION_END_SLOPE_B 16 31 regCM1_CM_GAMCOR_RAMA_END_CNTL1_G 0 0xeb7 1 0 2 CM_GAMCOR_RAMA_EXP_REGION_END_BASE_G 0 17 regCM1_CM_GAMCOR_RAMA_END_CNTL2_G 0 0xeb8 2 0 2 CM_GAMCOR_RAMA_EXP_REGION_END_G 0 15 CM_GAMCOR_RAMA_EXP_REGION_END_SLOPE_G 16 31 regCM1_CM_GAMCOR_RAMA_END_CNTL1_R 0 0xeb9 1 0 2 CM_GAMCOR_RAMA_EXP_REGION_END_BASE_R 0 17 regCM1_CM_GAMCOR_RAMA_END_CNTL2_R 0 0xeba 2 0 2 CM_GAMCOR_RAMA_EXP_REGION_END_R 0 15 CM_GAMCOR_RAMA_EXP_REGION_END_SLOPE_R 16 31 regCM1_CM_GAMCOR_RAMA_OFFSET_B 0 0xebb 1 0 2 CM_GAMCOR_RAMA_OFFSET_B 0 18 regCM1_CM_GAMCOR_RAMA_OFFSET_G 0 0xebc 1 0 2 CM_GAMCOR_RAMA_OFFSET_G 0 18 regCM1_CM_GAMCOR_RAMA_OFFSET_R 0 0xebd 1 0 2 CM_GAMCOR_RAMA_OFFSET_R 0 18 regCM1_CM_GAMCOR_RAMA_REGION_0_1 0 0xebe 4 0 2 CM_GAMCOR_RAMA_EXP_REGION0_LUT_OFFSET 0 8 CM_GAMCOR_RAMA_EXP_REGION0_NUM_SEGMENTS 12 14 CM_GAMCOR_RAMA_EXP_REGION1_LUT_OFFSET 16 24 CM_GAMCOR_RAMA_EXP_REGION1_NUM_SEGMENTS 28 30 regCM1_CM_GAMCOR_RAMA_REGION_2_3 0 0xebf 4 0 2 CM_GAMCOR_RAMA_EXP_REGION2_LUT_OFFSET 0 8 CM_GAMCOR_RAMA_EXP_REGION2_NUM_SEGMENTS 12 14 CM_GAMCOR_RAMA_EXP_REGION3_LUT_OFFSET 16 24 CM_GAMCOR_RAMA_EXP_REGION3_NUM_SEGMENTS 28 30 regCM1_CM_GAMCOR_RAMA_REGION_4_5 0 0xec0 4 0 2 CM_GAMCOR_RAMA_EXP_REGION4_LUT_OFFSET 0 8 CM_GAMCOR_RAMA_EXP_REGION4_NUM_SEGMENTS 12 14 CM_GAMCOR_RAMA_EXP_REGION5_LUT_OFFSET 16 24 CM_GAMCOR_RAMA_EXP_REGION5_NUM_SEGMENTS 28 30 regCM1_CM_GAMCOR_RAMA_REGION_6_7 0 0xec1 4 0 2 CM_GAMCOR_RAMA_EXP_REGION6_LUT_OFFSET 0 8 CM_GAMCOR_RAMA_EXP_REGION6_NUM_SEGMENTS 12 14 CM_GAMCOR_RAMA_EXP_REGION7_LUT_OFFSET 16 24 CM_GAMCOR_RAMA_EXP_REGION7_NUM_SEGMENTS 28 30 regCM1_CM_GAMCOR_RAMA_REGION_8_9 0 0xec2 4 0 2 CM_GAMCOR_RAMA_EXP_REGION8_LUT_OFFSET 0 8 CM_GAMCOR_RAMA_EXP_REGION8_NUM_SEGMENTS 12 14 CM_GAMCOR_RAMA_EXP_REGION9_LUT_OFFSET 16 24 CM_GAMCOR_RAMA_EXP_REGION9_NUM_SEGMENTS 28 30 regCM1_CM_GAMCOR_RAMA_REGION_10_11 0 0xec3 4 0 2 CM_GAMCOR_RAMA_EXP_REGION10_LUT_OFFSET 0 8 CM_GAMCOR_RAMA_EXP_REGION10_NUM_SEGMENTS 12 14 CM_GAMCOR_RAMA_EXP_REGION11_LUT_OFFSET 16 24 CM_GAMCOR_RAMA_EXP_REGION11_NUM_SEGMENTS 28 30 regCM1_CM_GAMCOR_RAMA_REGION_12_13 0 0xec4 4 0 2 CM_GAMCOR_RAMA_EXP_REGION12_LUT_OFFSET 0 8 CM_GAMCOR_RAMA_EXP_REGION12_NUM_SEGMENTS 12 14 CM_GAMCOR_RAMA_EXP_REGION13_LUT_OFFSET 16 24 CM_GAMCOR_RAMA_EXP_REGION13_NUM_SEGMENTS 28 30 regCM1_CM_GAMCOR_RAMA_REGION_14_15 0 0xec5 4 0 2 CM_GAMCOR_RAMA_EXP_REGION14_LUT_OFFSET 0 8 CM_GAMCOR_RAMA_EXP_REGION14_NUM_SEGMENTS 12 14 CM_GAMCOR_RAMA_EXP_REGION15_LUT_OFFSET 16 24 CM_GAMCOR_RAMA_EXP_REGION15_NUM_SEGMENTS 28 30 regCM1_CM_GAMCOR_RAMA_REGION_16_17 0 0xec6 4 0 2 CM_GAMCOR_RAMA_EXP_REGION16_LUT_OFFSET 0 8 CM_GAMCOR_RAMA_EXP_REGION16_NUM_SEGMENTS 12 14 CM_GAMCOR_RAMA_EXP_REGION17_LUT_OFFSET 16 24 CM_GAMCOR_RAMA_EXP_REGION17_NUM_SEGMENTS 28 30 regCM1_CM_GAMCOR_RAMA_REGION_18_19 0 0xec7 4 0 2 CM_GAMCOR_RAMA_EXP_REGION18_LUT_OFFSET 0 8 CM_GAMCOR_RAMA_EXP_REGION18_NUM_SEGMENTS 12 14 CM_GAMCOR_RAMA_EXP_REGION19_LUT_OFFSET 16 24 CM_GAMCOR_RAMA_EXP_REGION19_NUM_SEGMENTS 28 30 regCM1_CM_GAMCOR_RAMA_REGION_20_21 0 0xec8 4 0 2 CM_GAMCOR_RAMA_EXP_REGION20_LUT_OFFSET 0 8 CM_GAMCOR_RAMA_EXP_REGION20_NUM_SEGMENTS 12 14 CM_GAMCOR_RAMA_EXP_REGION21_LUT_OFFSET 16 24 CM_GAMCOR_RAMA_EXP_REGION21_NUM_SEGMENTS 28 30 regCM1_CM_GAMCOR_RAMA_REGION_22_23 0 0xec9 4 0 2 CM_GAMCOR_RAMA_EXP_REGION22_LUT_OFFSET 0 8 CM_GAMCOR_RAMA_EXP_REGION22_NUM_SEGMENTS 12 14 CM_GAMCOR_RAMA_EXP_REGION23_LUT_OFFSET 16 24 CM_GAMCOR_RAMA_EXP_REGION23_NUM_SEGMENTS 28 30 regCM1_CM_GAMCOR_RAMA_REGION_24_25 0 0xeca 4 0 2 CM_GAMCOR_RAMA_EXP_REGION24_LUT_OFFSET 0 8 CM_GAMCOR_RAMA_EXP_REGION24_NUM_SEGMENTS 12 14 CM_GAMCOR_RAMA_EXP_REGION25_LUT_OFFSET 16 24 CM_GAMCOR_RAMA_EXP_REGION25_NUM_SEGMENTS 28 30 regCM1_CM_GAMCOR_RAMA_REGION_26_27 0 0xecb 4 0 2 CM_GAMCOR_RAMA_EXP_REGION26_LUT_OFFSET 0 8 CM_GAMCOR_RAMA_EXP_REGION26_NUM_SEGMENTS 12 14 CM_GAMCOR_RAMA_EXP_REGION27_LUT_OFFSET 16 24 CM_GAMCOR_RAMA_EXP_REGION27_NUM_SEGMENTS 28 30 regCM1_CM_GAMCOR_RAMA_REGION_28_29 0 0xecc 4 0 2 CM_GAMCOR_RAMA_EXP_REGION28_LUT_OFFSET 0 8 CM_GAMCOR_RAMA_EXP_REGION28_NUM_SEGMENTS 12 14 CM_GAMCOR_RAMA_EXP_REGION29_LUT_OFFSET 16 24 CM_GAMCOR_RAMA_EXP_REGION29_NUM_SEGMENTS 28 30 regCM1_CM_GAMCOR_RAMA_REGION_30_31 0 0xecd 4 0 2 CM_GAMCOR_RAMA_EXP_REGION30_LUT_OFFSET 0 8 CM_GAMCOR_RAMA_EXP_REGION30_NUM_SEGMENTS 12 14 CM_GAMCOR_RAMA_EXP_REGION31_LUT_OFFSET 16 24 CM_GAMCOR_RAMA_EXP_REGION31_NUM_SEGMENTS 28 30 regCM1_CM_GAMCOR_RAMA_REGION_32_33 0 0xece 4 0 2 CM_GAMCOR_RAMA_EXP_REGION32_LUT_OFFSET 0 8 CM_GAMCOR_RAMA_EXP_REGION32_NUM_SEGMENTS 12 14 CM_GAMCOR_RAMA_EXP_REGION33_LUT_OFFSET 16 24 CM_GAMCOR_RAMA_EXP_REGION33_NUM_SEGMENTS 28 30 regCM1_CM_GAMCOR_RAMB_START_CNTL_B 0 0xecf 2 0 2 CM_GAMCOR_RAMB_EXP_REGION_START_B 0 17 CM_GAMCOR_RAMB_EXP_REGION_START_SEGMENT_B 20 26 regCM1_CM_GAMCOR_RAMB_START_CNTL_G 0 0xed0 2 0 2 CM_GAMCOR_RAMB_EXP_REGION_START_G 0 17 CM_GAMCOR_RAMB_EXP_REGION_START_SEGMENT_G 20 26 regCM1_CM_GAMCOR_RAMB_START_CNTL_R 0 0xed1 2 0 2 CM_GAMCOR_RAMB_EXP_REGION_START_R 0 17 CM_GAMCOR_RAMB_EXP_REGION_START_SEGMENT_R 20 26 regCM1_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B 0 0xed2 1 0 2 CM_GAMCOR_RAMB_EXP_REGION_START_SLOPE_B 0 17 regCM1_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G 0 0xed3 1 0 2 CM_GAMCOR_RAMB_EXP_REGION_START_SLOPE_G 0 17 regCM1_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R 0 0xed4 1 0 2 CM_GAMCOR_RAMB_EXP_REGION_START_SLOPE_R 0 17 regCM1_CM_GAMCOR_RAMB_START_BASE_CNTL_B 0 0xed5 1 0 2 CM_GAMCOR_RAMB_EXP_REGION_START_BASE_B 0 17 regCM1_CM_GAMCOR_RAMB_START_BASE_CNTL_G 0 0xed6 1 0 2 CM_GAMCOR_RAMB_EXP_REGION_START_BASE_G 0 17 regCM1_CM_GAMCOR_RAMB_START_BASE_CNTL_R 0 0xed7 1 0 2 CM_GAMCOR_RAMB_EXP_REGION_START_BASE_R 0 17 regCM1_CM_GAMCOR_RAMB_END_CNTL1_B 0 0xed8 1 0 2 CM_GAMCOR_RAMB_EXP_REGION_END_BASE_B 0 17 regCM1_CM_GAMCOR_RAMB_END_CNTL2_B 0 0xed9 2 0 2 CM_GAMCOR_RAMB_EXP_REGION_END_B 0 15 CM_GAMCOR_RAMB_EXP_REGION_END_SLOPE_B 16 31 regCM1_CM_GAMCOR_RAMB_END_CNTL1_G 0 0xeda 1 0 2 CM_GAMCOR_RAMB_EXP_REGION_END_BASE_G 0 17 regCM1_CM_GAMCOR_RAMB_END_CNTL2_G 0 0xedb 2 0 2 CM_GAMCOR_RAMB_EXP_REGION_END_G 0 15 CM_GAMCOR_RAMB_EXP_REGION_END_SLOPE_G 16 31 regCM1_CM_GAMCOR_RAMB_END_CNTL1_R 0 0xedc 1 0 2 CM_GAMCOR_RAMB_EXP_REGION_END_BASE_R 0 17 regCM1_CM_GAMCOR_RAMB_END_CNTL2_R 0 0xedd 2 0 2 CM_GAMCOR_RAMB_EXP_REGION_END_R 0 15 CM_GAMCOR_RAMB_EXP_REGION_END_SLOPE_R 16 31 regCM1_CM_GAMCOR_RAMB_OFFSET_B 0 0xede 1 0 2 CM_GAMCOR_RAMB_OFFSET_B 0 18 regCM1_CM_GAMCOR_RAMB_OFFSET_G 0 0xedf 1 0 2 CM_GAMCOR_RAMB_OFFSET_G 0 18 regCM1_CM_GAMCOR_RAMB_OFFSET_R 0 0xee0 1 0 2 CM_GAMCOR_RAMB_OFFSET_R 0 18 regCM1_CM_GAMCOR_RAMB_REGION_0_1 0 0xee1 4 0 2 CM_GAMCOR_RAMB_EXP_REGION0_LUT_OFFSET 0 8 CM_GAMCOR_RAMB_EXP_REGION0_NUM_SEGMENTS 12 14 CM_GAMCOR_RAMB_EXP_REGION1_LUT_OFFSET 16 24 CM_GAMCOR_RAMB_EXP_REGION1_NUM_SEGMENTS 28 30 regCM1_CM_GAMCOR_RAMB_REGION_2_3 0 0xee2 4 0 2 CM_GAMCOR_RAMB_EXP_REGION2_LUT_OFFSET 0 8 CM_GAMCOR_RAMB_EXP_REGION2_NUM_SEGMENTS 12 14 CM_GAMCOR_RAMB_EXP_REGION3_LUT_OFFSET 16 24 CM_GAMCOR_RAMB_EXP_REGION3_NUM_SEGMENTS 28 30 regCM1_CM_GAMCOR_RAMB_REGION_4_5 0 0xee3 4 0 2 CM_GAMCOR_RAMB_EXP_REGION4_LUT_OFFSET 0 8 CM_GAMCOR_RAMB_EXP_REGION4_NUM_SEGMENTS 12 14 CM_GAMCOR_RAMB_EXP_REGION5_LUT_OFFSET 16 24 CM_GAMCOR_RAMB_EXP_REGION5_NUM_SEGMENTS 28 30 regCM1_CM_GAMCOR_RAMB_REGION_6_7 0 0xee4 4 0 2 CM_GAMCOR_RAMB_EXP_REGION6_LUT_OFFSET 0 8 CM_GAMCOR_RAMB_EXP_REGION6_NUM_SEGMENTS 12 14 CM_GAMCOR_RAMB_EXP_REGION7_LUT_OFFSET 16 24 CM_GAMCOR_RAMB_EXP_REGION7_NUM_SEGMENTS 28 30 regCM1_CM_GAMCOR_RAMB_REGION_8_9 0 0xee5 4 0 2 CM_GAMCOR_RAMB_EXP_REGION8_LUT_OFFSET 0 8 CM_GAMCOR_RAMB_EXP_REGION8_NUM_SEGMENTS 12 14 CM_GAMCOR_RAMB_EXP_REGION9_LUT_OFFSET 16 24 CM_GAMCOR_RAMB_EXP_REGION9_NUM_SEGMENTS 28 30 regCM1_CM_GAMCOR_RAMB_REGION_10_11 0 0xee6 4 0 2 CM_GAMCOR_RAMB_EXP_REGION10_LUT_OFFSET 0 8 CM_GAMCOR_RAMB_EXP_REGION10_NUM_SEGMENTS 12 14 CM_GAMCOR_RAMB_EXP_REGION11_LUT_OFFSET 16 24 CM_GAMCOR_RAMB_EXP_REGION11_NUM_SEGMENTS 28 30 regCM1_CM_GAMCOR_RAMB_REGION_12_13 0 0xee7 4 0 2 CM_GAMCOR_RAMB_EXP_REGION12_LUT_OFFSET 0 8 CM_GAMCOR_RAMB_EXP_REGION12_NUM_SEGMENTS 12 14 CM_GAMCOR_RAMB_EXP_REGION13_LUT_OFFSET 16 24 CM_GAMCOR_RAMB_EXP_REGION13_NUM_SEGMENTS 28 30 regCM1_CM_GAMCOR_RAMB_REGION_14_15 0 0xee8 4 0 2 CM_GAMCOR_RAMB_EXP_REGION14_LUT_OFFSET 0 8 CM_GAMCOR_RAMB_EXP_REGION14_NUM_SEGMENTS 12 14 CM_GAMCOR_RAMB_EXP_REGION15_LUT_OFFSET 16 24 CM_GAMCOR_RAMB_EXP_REGION15_NUM_SEGMENTS 28 30 regCM1_CM_GAMCOR_RAMB_REGION_16_17 0 0xee9 4 0 2 CM_GAMCOR_RAMB_EXP_REGION16_LUT_OFFSET 0 8 CM_GAMCOR_RAMB_EXP_REGION16_NUM_SEGMENTS 12 14 CM_GAMCOR_RAMB_EXP_REGION17_LUT_OFFSET 16 24 CM_GAMCOR_RAMB_EXP_REGION17_NUM_SEGMENTS 28 30 regCM1_CM_GAMCOR_RAMB_REGION_18_19 0 0xeea 4 0 2 CM_GAMCOR_RAMB_EXP_REGION18_LUT_OFFSET 0 8 CM_GAMCOR_RAMB_EXP_REGION18_NUM_SEGMENTS 12 14 CM_GAMCOR_RAMB_EXP_REGION19_LUT_OFFSET 16 24 CM_GAMCOR_RAMB_EXP_REGION19_NUM_SEGMENTS 28 30 regCM1_CM_GAMCOR_RAMB_REGION_20_21 0 0xeeb 4 0 2 CM_GAMCOR_RAMB_EXP_REGION20_LUT_OFFSET 0 8 CM_GAMCOR_RAMB_EXP_REGION20_NUM_SEGMENTS 12 14 CM_GAMCOR_RAMB_EXP_REGION21_LUT_OFFSET 16 24 CM_GAMCOR_RAMB_EXP_REGION21_NUM_SEGMENTS 28 30 regCM1_CM_GAMCOR_RAMB_REGION_22_23 0 0xeec 4 0 2 CM_GAMCOR_RAMB_EXP_REGION22_LUT_OFFSET 0 8 CM_GAMCOR_RAMB_EXP_REGION22_NUM_SEGMENTS 12 14 CM_GAMCOR_RAMB_EXP_REGION23_LUT_OFFSET 16 24 CM_GAMCOR_RAMB_EXP_REGION23_NUM_SEGMENTS 28 30 regCM1_CM_GAMCOR_RAMB_REGION_24_25 0 0xeed 4 0 2 CM_GAMCOR_RAMB_EXP_REGION24_LUT_OFFSET 0 8 CM_GAMCOR_RAMB_EXP_REGION24_NUM_SEGMENTS 12 14 CM_GAMCOR_RAMB_EXP_REGION25_LUT_OFFSET 16 24 CM_GAMCOR_RAMB_EXP_REGION25_NUM_SEGMENTS 28 30 regCM1_CM_GAMCOR_RAMB_REGION_26_27 0 0xeee 4 0 2 CM_GAMCOR_RAMB_EXP_REGION26_LUT_OFFSET 0 8 CM_GAMCOR_RAMB_EXP_REGION26_NUM_SEGMENTS 12 14 CM_GAMCOR_RAMB_EXP_REGION27_LUT_OFFSET 16 24 CM_GAMCOR_RAMB_EXP_REGION27_NUM_SEGMENTS 28 30 regCM1_CM_GAMCOR_RAMB_REGION_28_29 0 0xeef 4 0 2 CM_GAMCOR_RAMB_EXP_REGION28_LUT_OFFSET 0 8 CM_GAMCOR_RAMB_EXP_REGION28_NUM_SEGMENTS 12 14 CM_GAMCOR_RAMB_EXP_REGION29_LUT_OFFSET 16 24 CM_GAMCOR_RAMB_EXP_REGION29_NUM_SEGMENTS 28 30 regCM1_CM_GAMCOR_RAMB_REGION_30_31 0 0xef0 4 0 2 CM_GAMCOR_RAMB_EXP_REGION30_LUT_OFFSET 0 8 CM_GAMCOR_RAMB_EXP_REGION30_NUM_SEGMENTS 12 14 CM_GAMCOR_RAMB_EXP_REGION31_LUT_OFFSET 16 24 CM_GAMCOR_RAMB_EXP_REGION31_NUM_SEGMENTS 28 30 regCM1_CM_GAMCOR_RAMB_REGION_32_33 0 0xef1 4 0 2 CM_GAMCOR_RAMB_EXP_REGION32_LUT_OFFSET 0 8 CM_GAMCOR_RAMB_EXP_REGION32_NUM_SEGMENTS 12 14 CM_GAMCOR_RAMB_EXP_REGION33_LUT_OFFSET 16 24 CM_GAMCOR_RAMB_EXP_REGION33_NUM_SEGMENTS 28 30 regCM1_CM_BLNDGAM_CONTROL 0 0xef2 5 0 2 CM_BLNDGAM_MODE 0 1 CM_BLNDGAM_SELECT 2 2 CM_BLNDGAM_PWL_DISABLE 3 3 CM_BLNDGAM_MODE_CURRENT 4 5 CM_BLNDGAM_SELECT_CURRENT 6 6 regCM1_CM_BLNDGAM_LUT_INDEX 0 0xef3 1 0 2 CM_BLNDGAM_LUT_INDEX 0 8 regCM1_CM_BLNDGAM_LUT_DATA 0 0xef4 1 0 2 CM_BLNDGAM_LUT_DATA 0 17 regCM1_CM_BLNDGAM_LUT_CONTROL 0 0xef5 5 0 2 CM_BLNDGAM_LUT_WRITE_COLOR_MASK 0 2 CM_BLNDGAM_LUT_READ_COLOR_SEL 3 4 CM_BLNDGAM_LUT_READ_DBG 5 5 CM_BLNDGAM_LUT_HOST_SEL 6 6 CM_BLNDGAM_LUT_CONFIG_MODE 7 7 regCM1_CM_BLNDGAM_RAMA_START_CNTL_B 0 0xef6 2 0 2 CM_BLNDGAM_RAMA_EXP_REGION_START_B 0 17 CM_BLNDGAM_RAMA_EXP_REGION_START_SEGMENT_B 20 26 regCM1_CM_BLNDGAM_RAMA_START_CNTL_G 0 0xef7 2 0 2 CM_BLNDGAM_RAMA_EXP_REGION_START_G 0 17 CM_BLNDGAM_RAMA_EXP_REGION_START_SEGMENT_G 20 26 regCM1_CM_BLNDGAM_RAMA_START_CNTL_R 0 0xef8 2 0 2 CM_BLNDGAM_RAMA_EXP_REGION_START_R 0 17 CM_BLNDGAM_RAMA_EXP_REGION_START_SEGMENT_R 20 26 regCM1_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_B 0 0xef9 1 0 2 CM_BLNDGAM_RAMA_EXP_REGION_START_SLOPE_B 0 17 regCM1_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_G 0 0xefa 1 0 2 CM_BLNDGAM_RAMA_EXP_REGION_START_SLOPE_G 0 17 regCM1_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_R 0 0xefb 1 0 2 CM_BLNDGAM_RAMA_EXP_REGION_START_SLOPE_R 0 17 regCM1_CM_BLNDGAM_RAMA_START_BASE_CNTL_B 0 0xefc 1 0 2 CM_BLNDGAM_RAMA_EXP_REGION_START_BASE_B 0 17 regCM1_CM_BLNDGAM_RAMA_START_BASE_CNTL_G 0 0xefd 1 0 2 CM_BLNDGAM_RAMA_EXP_REGION_START_BASE_G 0 17 regCM1_CM_BLNDGAM_RAMA_START_BASE_CNTL_R 0 0xefe 1 0 2 CM_BLNDGAM_RAMA_EXP_REGION_START_BASE_R 0 17 regCM1_CM_BLNDGAM_RAMA_END_CNTL1_B 0 0xeff 1 0 2 CM_BLNDGAM_RAMA_EXP_REGION_END_BASE_B 0 17 regCM1_CM_BLNDGAM_RAMA_END_CNTL2_B 0 0xf00 2 0 2 CM_BLNDGAM_RAMA_EXP_REGION_END_B 0 15 CM_BLNDGAM_RAMA_EXP_REGION_END_SLOPE_B 16 31 regCM1_CM_BLNDGAM_RAMA_END_CNTL1_G 0 0xf01 1 0 2 CM_BLNDGAM_RAMA_EXP_REGION_END_BASE_G 0 17 regCM1_CM_BLNDGAM_RAMA_END_CNTL2_G 0 0xf02 2 0 2 CM_BLNDGAM_RAMA_EXP_REGION_END_G 0 15 CM_BLNDGAM_RAMA_EXP_REGION_END_SLOPE_G 16 31 regCM1_CM_BLNDGAM_RAMA_END_CNTL1_R 0 0xf03 1 0 2 CM_BLNDGAM_RAMA_EXP_REGION_END_BASE_R 0 17 regCM1_CM_BLNDGAM_RAMA_END_CNTL2_R 0 0xf04 2 0 2 CM_BLNDGAM_RAMA_EXP_REGION_END_R 0 15 CM_BLNDGAM_RAMA_EXP_REGION_END_SLOPE_R 16 31 regCM1_CM_BLNDGAM_RAMA_OFFSET_B 0 0xf05 1 0 2 CM_BLNDGAM_RAMA_OFFSET_B 0 18 regCM1_CM_BLNDGAM_RAMA_OFFSET_G 0 0xf06 1 0 2 CM_BLNDGAM_RAMA_OFFSET_G 0 18 regCM1_CM_BLNDGAM_RAMA_OFFSET_R 0 0xf07 1 0 2 CM_BLNDGAM_RAMA_OFFSET_R 0 18 regCM1_CM_BLNDGAM_RAMA_REGION_0_1 0 0xf08 4 0 2 CM_BLNDGAM_RAMA_EXP_REGION0_LUT_OFFSET 0 8 CM_BLNDGAM_RAMA_EXP_REGION0_NUM_SEGMENTS 12 14 CM_BLNDGAM_RAMA_EXP_REGION1_LUT_OFFSET 16 24 CM_BLNDGAM_RAMA_EXP_REGION1_NUM_SEGMENTS 28 30 regCM1_CM_BLNDGAM_RAMA_REGION_2_3 0 0xf09 4 0 2 CM_BLNDGAM_RAMA_EXP_REGION2_LUT_OFFSET 0 8 CM_BLNDGAM_RAMA_EXP_REGION2_NUM_SEGMENTS 12 14 CM_BLNDGAM_RAMA_EXP_REGION3_LUT_OFFSET 16 24 CM_BLNDGAM_RAMA_EXP_REGION3_NUM_SEGMENTS 28 30 regCM1_CM_BLNDGAM_RAMA_REGION_4_5 0 0xf0a 4 0 2 CM_BLNDGAM_RAMA_EXP_REGION4_LUT_OFFSET 0 8 CM_BLNDGAM_RAMA_EXP_REGION4_NUM_SEGMENTS 12 14 CM_BLNDGAM_RAMA_EXP_REGION5_LUT_OFFSET 16 24 CM_BLNDGAM_RAMA_EXP_REGION5_NUM_SEGMENTS 28 30 regCM1_CM_BLNDGAM_RAMA_REGION_6_7 0 0xf0b 4 0 2 CM_BLNDGAM_RAMA_EXP_REGION6_LUT_OFFSET 0 8 CM_BLNDGAM_RAMA_EXP_REGION6_NUM_SEGMENTS 12 14 CM_BLNDGAM_RAMA_EXP_REGION7_LUT_OFFSET 16 24 CM_BLNDGAM_RAMA_EXP_REGION7_NUM_SEGMENTS 28 30 regCM1_CM_BLNDGAM_RAMA_REGION_8_9 0 0xf0c 4 0 2 CM_BLNDGAM_RAMA_EXP_REGION8_LUT_OFFSET 0 8 CM_BLNDGAM_RAMA_EXP_REGION8_NUM_SEGMENTS 12 14 CM_BLNDGAM_RAMA_EXP_REGION9_LUT_OFFSET 16 24 CM_BLNDGAM_RAMA_EXP_REGION9_NUM_SEGMENTS 28 30 regCM1_CM_BLNDGAM_RAMA_REGION_10_11 0 0xf0d 4 0 2 CM_BLNDGAM_RAMA_EXP_REGION10_LUT_OFFSET 0 8 CM_BLNDGAM_RAMA_EXP_REGION10_NUM_SEGMENTS 12 14 CM_BLNDGAM_RAMA_EXP_REGION11_LUT_OFFSET 16 24 CM_BLNDGAM_RAMA_EXP_REGION11_NUM_SEGMENTS 28 30 regCM1_CM_BLNDGAM_RAMA_REGION_12_13 0 0xf0e 4 0 2 CM_BLNDGAM_RAMA_EXP_REGION12_LUT_OFFSET 0 8 CM_BLNDGAM_RAMA_EXP_REGION12_NUM_SEGMENTS 12 14 CM_BLNDGAM_RAMA_EXP_REGION13_LUT_OFFSET 16 24 CM_BLNDGAM_RAMA_EXP_REGION13_NUM_SEGMENTS 28 30 regCM1_CM_BLNDGAM_RAMA_REGION_14_15 0 0xf0f 4 0 2 CM_BLNDGAM_RAMA_EXP_REGION14_LUT_OFFSET 0 8 CM_BLNDGAM_RAMA_EXP_REGION14_NUM_SEGMENTS 12 14 CM_BLNDGAM_RAMA_EXP_REGION15_LUT_OFFSET 16 24 CM_BLNDGAM_RAMA_EXP_REGION15_NUM_SEGMENTS 28 30 regCM1_CM_BLNDGAM_RAMA_REGION_16_17 0 0xf10 4 0 2 CM_BLNDGAM_RAMA_EXP_REGION16_LUT_OFFSET 0 8 CM_BLNDGAM_RAMA_EXP_REGION16_NUM_SEGMENTS 12 14 CM_BLNDGAM_RAMA_EXP_REGION17_LUT_OFFSET 16 24 CM_BLNDGAM_RAMA_EXP_REGION17_NUM_SEGMENTS 28 30 regCM1_CM_BLNDGAM_RAMA_REGION_18_19 0 0xf11 4 0 2 CM_BLNDGAM_RAMA_EXP_REGION18_LUT_OFFSET 0 8 CM_BLNDGAM_RAMA_EXP_REGION18_NUM_SEGMENTS 12 14 CM_BLNDGAM_RAMA_EXP_REGION19_LUT_OFFSET 16 24 CM_BLNDGAM_RAMA_EXP_REGION19_NUM_SEGMENTS 28 30 regCM1_CM_BLNDGAM_RAMA_REGION_20_21 0 0xf12 4 0 2 CM_BLNDGAM_RAMA_EXP_REGION20_LUT_OFFSET 0 8 CM_BLNDGAM_RAMA_EXP_REGION20_NUM_SEGMENTS 12 14 CM_BLNDGAM_RAMA_EXP_REGION21_LUT_OFFSET 16 24 CM_BLNDGAM_RAMA_EXP_REGION21_NUM_SEGMENTS 28 30 regCM1_CM_BLNDGAM_RAMA_REGION_22_23 0 0xf13 4 0 2 CM_BLNDGAM_RAMA_EXP_REGION22_LUT_OFFSET 0 8 CM_BLNDGAM_RAMA_EXP_REGION22_NUM_SEGMENTS 12 14 CM_BLNDGAM_RAMA_EXP_REGION23_LUT_OFFSET 16 24 CM_BLNDGAM_RAMA_EXP_REGION23_NUM_SEGMENTS 28 30 regCM1_CM_BLNDGAM_RAMA_REGION_24_25 0 0xf14 4 0 2 CM_BLNDGAM_RAMA_EXP_REGION24_LUT_OFFSET 0 8 CM_BLNDGAM_RAMA_EXP_REGION24_NUM_SEGMENTS 12 14 CM_BLNDGAM_RAMA_EXP_REGION25_LUT_OFFSET 16 24 CM_BLNDGAM_RAMA_EXP_REGION25_NUM_SEGMENTS 28 30 regCM1_CM_BLNDGAM_RAMA_REGION_26_27 0 0xf15 4 0 2 CM_BLNDGAM_RAMA_EXP_REGION26_LUT_OFFSET 0 8 CM_BLNDGAM_RAMA_EXP_REGION26_NUM_SEGMENTS 12 14 CM_BLNDGAM_RAMA_EXP_REGION27_LUT_OFFSET 16 24 CM_BLNDGAM_RAMA_EXP_REGION27_NUM_SEGMENTS 28 30 regCM1_CM_BLNDGAM_RAMA_REGION_28_29 0 0xf16 4 0 2 CM_BLNDGAM_RAMA_EXP_REGION28_LUT_OFFSET 0 8 CM_BLNDGAM_RAMA_EXP_REGION28_NUM_SEGMENTS 12 14 CM_BLNDGAM_RAMA_EXP_REGION29_LUT_OFFSET 16 24 CM_BLNDGAM_RAMA_EXP_REGION29_NUM_SEGMENTS 28 30 regCM1_CM_BLNDGAM_RAMA_REGION_30_31 0 0xf17 4 0 2 CM_BLNDGAM_RAMA_EXP_REGION30_LUT_OFFSET 0 8 CM_BLNDGAM_RAMA_EXP_REGION30_NUM_SEGMENTS 12 14 CM_BLNDGAM_RAMA_EXP_REGION31_LUT_OFFSET 16 24 CM_BLNDGAM_RAMA_EXP_REGION31_NUM_SEGMENTS 28 30 regCM1_CM_BLNDGAM_RAMA_REGION_32_33 0 0xf18 4 0 2 CM_BLNDGAM_RAMA_EXP_REGION32_LUT_OFFSET 0 8 CM_BLNDGAM_RAMA_EXP_REGION32_NUM_SEGMENTS 12 14 CM_BLNDGAM_RAMA_EXP_REGION33_LUT_OFFSET 16 24 CM_BLNDGAM_RAMA_EXP_REGION33_NUM_SEGMENTS 28 30 regCM1_CM_BLNDGAM_RAMB_START_CNTL_B 0 0xf19 2 0 2 CM_BLNDGAM_RAMB_EXP_REGION_START_B 0 17 CM_BLNDGAM_RAMB_EXP_REGION_START_SEGMENT_B 20 26 regCM1_CM_BLNDGAM_RAMB_START_CNTL_G 0 0xf1a 2 0 2 CM_BLNDGAM_RAMB_EXP_REGION_START_G 0 17 CM_BLNDGAM_RAMB_EXP_REGION_START_SEGMENT_G 20 26 regCM1_CM_BLNDGAM_RAMB_START_CNTL_R 0 0xf1b 2 0 2 CM_BLNDGAM_RAMB_EXP_REGION_START_R 0 17 CM_BLNDGAM_RAMB_EXP_REGION_START_SEGMENT_R 20 26 regCM1_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_B 0 0xf1c 1 0 2 CM_BLNDGAM_RAMB_EXP_REGION_START_SLOPE_B 0 17 regCM1_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_G 0 0xf1d 1 0 2 CM_BLNDGAM_RAMB_EXP_REGION_START_SLOPE_G 0 17 regCM1_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_R 0 0xf1e 1 0 2 CM_BLNDGAM_RAMB_EXP_REGION_START_SLOPE_R 0 17 regCM1_CM_BLNDGAM_RAMB_START_BASE_CNTL_B 0 0xf1f 1 0 2 CM_BLNDGAM_RAMB_EXP_REGION_START_BASE_B 0 17 regCM1_CM_BLNDGAM_RAMB_START_BASE_CNTL_G 0 0xf20 1 0 2 CM_BLNDGAM_RAMB_EXP_REGION_START_BASE_G 0 17 regCM1_CM_BLNDGAM_RAMB_START_BASE_CNTL_R 0 0xf21 1 0 2 CM_BLNDGAM_RAMB_EXP_REGION_START_BASE_R 0 17 regCM1_CM_BLNDGAM_RAMB_END_CNTL1_B 0 0xf22 1 0 2 CM_BLNDGAM_RAMB_EXP_REGION_END_BASE_B 0 17 regCM1_CM_BLNDGAM_RAMB_END_CNTL2_B 0 0xf23 2 0 2 CM_BLNDGAM_RAMB_EXP_REGION_END_B 0 15 CM_BLNDGAM_RAMB_EXP_REGION_END_SLOPE_B 16 31 regCM1_CM_BLNDGAM_RAMB_END_CNTL1_G 0 0xf24 1 0 2 CM_BLNDGAM_RAMB_EXP_REGION_END_BASE_G 0 17 regCM1_CM_BLNDGAM_RAMB_END_CNTL2_G 0 0xf25 2 0 2 CM_BLNDGAM_RAMB_EXP_REGION_END_G 0 15 CM_BLNDGAM_RAMB_EXP_REGION_END_SLOPE_G 16 31 regCM1_CM_BLNDGAM_RAMB_END_CNTL1_R 0 0xf26 1 0 2 CM_BLNDGAM_RAMB_EXP_REGION_END_BASE_R 0 17 regCM1_CM_BLNDGAM_RAMB_END_CNTL2_R 0 0xf27 2 0 2 CM_BLNDGAM_RAMB_EXP_REGION_END_R 0 15 CM_BLNDGAM_RAMB_EXP_REGION_END_SLOPE_R 16 31 regCM1_CM_BLNDGAM_RAMB_OFFSET_B 0 0xf28 1 0 2 CM_BLNDGAM_RAMB_OFFSET_B 0 18 regCM1_CM_BLNDGAM_RAMB_OFFSET_G 0 0xf29 1 0 2 CM_BLNDGAM_RAMB_OFFSET_G 0 18 regCM1_CM_BLNDGAM_RAMB_OFFSET_R 0 0xf2a 1 0 2 CM_BLNDGAM_RAMB_OFFSET_R 0 18 regCM1_CM_BLNDGAM_RAMB_REGION_0_1 0 0xf2b 4 0 2 CM_BLNDGAM_RAMB_EXP_REGION0_LUT_OFFSET 0 8 CM_BLNDGAM_RAMB_EXP_REGION0_NUM_SEGMENTS 12 14 CM_BLNDGAM_RAMB_EXP_REGION1_LUT_OFFSET 16 24 CM_BLNDGAM_RAMB_EXP_REGION1_NUM_SEGMENTS 28 30 regCM1_CM_BLNDGAM_RAMB_REGION_2_3 0 0xf2c 4 0 2 CM_BLNDGAM_RAMB_EXP_REGION2_LUT_OFFSET 0 8 CM_BLNDGAM_RAMB_EXP_REGION2_NUM_SEGMENTS 12 14 CM_BLNDGAM_RAMB_EXP_REGION3_LUT_OFFSET 16 24 CM_BLNDGAM_RAMB_EXP_REGION3_NUM_SEGMENTS 28 30 regCM1_CM_BLNDGAM_RAMB_REGION_4_5 0 0xf2d 4 0 2 CM_BLNDGAM_RAMB_EXP_REGION4_LUT_OFFSET 0 8 CM_BLNDGAM_RAMB_EXP_REGION4_NUM_SEGMENTS 12 14 CM_BLNDGAM_RAMB_EXP_REGION5_LUT_OFFSET 16 24 CM_BLNDGAM_RAMB_EXP_REGION5_NUM_SEGMENTS 28 30 regCM1_CM_BLNDGAM_RAMB_REGION_6_7 0 0xf2e 4 0 2 CM_BLNDGAM_RAMB_EXP_REGION6_LUT_OFFSET 0 8 CM_BLNDGAM_RAMB_EXP_REGION6_NUM_SEGMENTS 12 14 CM_BLNDGAM_RAMB_EXP_REGION7_LUT_OFFSET 16 24 CM_BLNDGAM_RAMB_EXP_REGION7_NUM_SEGMENTS 28 30 regCM1_CM_BLNDGAM_RAMB_REGION_8_9 0 0xf2f 4 0 2 CM_BLNDGAM_RAMB_EXP_REGION8_LUT_OFFSET 0 8 CM_BLNDGAM_RAMB_EXP_REGION8_NUM_SEGMENTS 12 14 CM_BLNDGAM_RAMB_EXP_REGION9_LUT_OFFSET 16 24 CM_BLNDGAM_RAMB_EXP_REGION9_NUM_SEGMENTS 28 30 regCM1_CM_BLNDGAM_RAMB_REGION_10_11 0 0xf30 4 0 2 CM_BLNDGAM_RAMB_EXP_REGION10_LUT_OFFSET 0 8 CM_BLNDGAM_RAMB_EXP_REGION10_NUM_SEGMENTS 12 14 CM_BLNDGAM_RAMB_EXP_REGION11_LUT_OFFSET 16 24 CM_BLNDGAM_RAMB_EXP_REGION11_NUM_SEGMENTS 28 30 regCM1_CM_BLNDGAM_RAMB_REGION_12_13 0 0xf31 4 0 2 CM_BLNDGAM_RAMB_EXP_REGION12_LUT_OFFSET 0 8 CM_BLNDGAM_RAMB_EXP_REGION12_NUM_SEGMENTS 12 14 CM_BLNDGAM_RAMB_EXP_REGION13_LUT_OFFSET 16 24 CM_BLNDGAM_RAMB_EXP_REGION13_NUM_SEGMENTS 28 30 regCM1_CM_BLNDGAM_RAMB_REGION_14_15 0 0xf32 4 0 2 CM_BLNDGAM_RAMB_EXP_REGION14_LUT_OFFSET 0 8 CM_BLNDGAM_RAMB_EXP_REGION14_NUM_SEGMENTS 12 14 CM_BLNDGAM_RAMB_EXP_REGION15_LUT_OFFSET 16 24 CM_BLNDGAM_RAMB_EXP_REGION15_NUM_SEGMENTS 28 30 regCM1_CM_BLNDGAM_RAMB_REGION_16_17 0 0xf33 4 0 2 CM_BLNDGAM_RAMB_EXP_REGION16_LUT_OFFSET 0 8 CM_BLNDGAM_RAMB_EXP_REGION16_NUM_SEGMENTS 12 14 CM_BLNDGAM_RAMB_EXP_REGION17_LUT_OFFSET 16 24 CM_BLNDGAM_RAMB_EXP_REGION17_NUM_SEGMENTS 28 30 regCM1_CM_BLNDGAM_RAMB_REGION_18_19 0 0xf34 4 0 2 CM_BLNDGAM_RAMB_EXP_REGION18_LUT_OFFSET 0 8 CM_BLNDGAM_RAMB_EXP_REGION18_NUM_SEGMENTS 12 14 CM_BLNDGAM_RAMB_EXP_REGION19_LUT_OFFSET 16 24 CM_BLNDGAM_RAMB_EXP_REGION19_NUM_SEGMENTS 28 30 regCM1_CM_BLNDGAM_RAMB_REGION_20_21 0 0xf35 4 0 2 CM_BLNDGAM_RAMB_EXP_REGION20_LUT_OFFSET 0 8 CM_BLNDGAM_RAMB_EXP_REGION20_NUM_SEGMENTS 12 14 CM_BLNDGAM_RAMB_EXP_REGION21_LUT_OFFSET 16 24 CM_BLNDGAM_RAMB_EXP_REGION21_NUM_SEGMENTS 28 30 regCM1_CM_BLNDGAM_RAMB_REGION_22_23 0 0xf36 4 0 2 CM_BLNDGAM_RAMB_EXP_REGION22_LUT_OFFSET 0 8 CM_BLNDGAM_RAMB_EXP_REGION22_NUM_SEGMENTS 12 14 CM_BLNDGAM_RAMB_EXP_REGION23_LUT_OFFSET 16 24 CM_BLNDGAM_RAMB_EXP_REGION23_NUM_SEGMENTS 28 30 regCM1_CM_BLNDGAM_RAMB_REGION_24_25 0 0xf37 4 0 2 CM_BLNDGAM_RAMB_EXP_REGION24_LUT_OFFSET 0 8 CM_BLNDGAM_RAMB_EXP_REGION24_NUM_SEGMENTS 12 14 CM_BLNDGAM_RAMB_EXP_REGION25_LUT_OFFSET 16 24 CM_BLNDGAM_RAMB_EXP_REGION25_NUM_SEGMENTS 28 30 regCM1_CM_BLNDGAM_RAMB_REGION_26_27 0 0xf38 4 0 2 CM_BLNDGAM_RAMB_EXP_REGION26_LUT_OFFSET 0 8 CM_BLNDGAM_RAMB_EXP_REGION26_NUM_SEGMENTS 12 14 CM_BLNDGAM_RAMB_EXP_REGION27_LUT_OFFSET 16 24 CM_BLNDGAM_RAMB_EXP_REGION27_NUM_SEGMENTS 28 30 regCM1_CM_BLNDGAM_RAMB_REGION_28_29 0 0xf39 4 0 2 CM_BLNDGAM_RAMB_EXP_REGION28_LUT_OFFSET 0 8 CM_BLNDGAM_RAMB_EXP_REGION28_NUM_SEGMENTS 12 14 CM_BLNDGAM_RAMB_EXP_REGION29_LUT_OFFSET 16 24 CM_BLNDGAM_RAMB_EXP_REGION29_NUM_SEGMENTS 28 30 regCM1_CM_BLNDGAM_RAMB_REGION_30_31 0 0xf3a 4 0 2 CM_BLNDGAM_RAMB_EXP_REGION30_LUT_OFFSET 0 8 CM_BLNDGAM_RAMB_EXP_REGION30_NUM_SEGMENTS 12 14 CM_BLNDGAM_RAMB_EXP_REGION31_LUT_OFFSET 16 24 CM_BLNDGAM_RAMB_EXP_REGION31_NUM_SEGMENTS 28 30 regCM1_CM_BLNDGAM_RAMB_REGION_32_33 0 0xf3b 4 0 2 CM_BLNDGAM_RAMB_EXP_REGION32_LUT_OFFSET 0 8 CM_BLNDGAM_RAMB_EXP_REGION32_NUM_SEGMENTS 12 14 CM_BLNDGAM_RAMB_EXP_REGION33_LUT_OFFSET 16 24 CM_BLNDGAM_RAMB_EXP_REGION33_NUM_SEGMENTS 28 30 regCM1_CM_HDR_MULT_COEF 0 0xf3c 1 0 2 CM_HDR_MULT_COEF 0 18 regCM1_CM_MEM_PWR_CTRL 0 0xf3d 4 0 2 GAMCOR_MEM_PWR_FORCE 0 1 GAMCOR_MEM_PWR_DIS 2 2 BLNDGAM_MEM_PWR_FORCE 4 5 BLNDGAM_MEM_PWR_DIS 6 6 regCM1_CM_MEM_PWR_STATUS 0 0xf3e 2 0 2 GAMCOR_MEM_PWR_STATE 0 1 BLNDGAM_MEM_PWR_STATE 2 3 regCM1_CM_DEALPHA 0 0xf40 2 0 2 CM_DEALPHA_EN 0 0 CM_DEALPHA_ABLND 1 1 regCM1_CM_COEF_FORMAT 0 0xf41 3 0 2 CM_BIAS_FORMAT 0 0 CM_POST_CSC_COEF_FORMAT 4 4 CM_GAMUT_REMAP_COEF_FORMAT 8 8 regCM1_CM_SHAPER_CONTROL 0 0xf42 2 0 2 CM_SHAPER_LUT_MODE 0 1 CM_SHAPER_MODE_CURRENT 2 3 regCM1_CM_SHAPER_OFFSET_R 0 0xf43 1 0 2 CM_SHAPER_OFFSET_R 0 18 regCM1_CM_SHAPER_OFFSET_G 0 0xf44 1 0 2 CM_SHAPER_OFFSET_G 0 18 regCM1_CM_SHAPER_OFFSET_B 0 0xf45 1 0 2 CM_SHAPER_OFFSET_B 0 18 regCM1_CM_SHAPER_SCALE_R 0 0xf46 1 0 2 CM_SHAPER_SCALE_R 0 15 regCM1_CM_SHAPER_SCALE_G_B 0 0xf47 2 0 2 CM_SHAPER_SCALE_G 0 15 CM_SHAPER_SCALE_B 16 31 regCM1_CM_SHAPER_LUT_INDEX 0 0xf48 1 0 2 CM_SHAPER_LUT_INDEX 0 7 regCM1_CM_SHAPER_LUT_DATA 0 0xf49 1 0 2 CM_SHAPER_LUT_DATA 0 23 regCM1_CM_SHAPER_LUT_WRITE_EN_MASK 0 0xf4a 2 0 2 CM_SHAPER_LUT_WRITE_EN_MASK 0 2 CM_SHAPER_LUT_WRITE_SEL 4 4 regCM1_CM_SHAPER_RAMA_START_CNTL_B 0 0xf4b 2 0 2 CM_SHAPER_RAMA_EXP_REGION_START_B 0 17 CM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_B 20 26 regCM1_CM_SHAPER_RAMA_START_CNTL_G 0 0xf4c 2 0 2 CM_SHAPER_RAMA_EXP_REGION_START_G 0 17 CM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_G 20 26 regCM1_CM_SHAPER_RAMA_START_CNTL_R 0 0xf4d 2 0 2 CM_SHAPER_RAMA_EXP_REGION_START_R 0 17 CM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_R 20 26 regCM1_CM_SHAPER_RAMA_END_CNTL_B 0 0xf4e 2 0 2 CM_SHAPER_RAMA_EXP_REGION_END_B 0 15 CM_SHAPER_RAMA_EXP_REGION_END_BASE_B 16 29 regCM1_CM_SHAPER_RAMA_END_CNTL_G 0 0xf4f 2 0 2 CM_SHAPER_RAMA_EXP_REGION_END_G 0 15 CM_SHAPER_RAMA_EXP_REGION_END_BASE_G 16 29 regCM1_CM_SHAPER_RAMA_END_CNTL_R 0 0xf50 2 0 2 CM_SHAPER_RAMA_EXP_REGION_END_R 0 15 CM_SHAPER_RAMA_EXP_REGION_END_BASE_R 16 29 regCM1_CM_SHAPER_RAMA_REGION_0_1 0 0xf51 4 0 2 CM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET 0 8 CM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS 12 14 CM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET 16 24 CM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS 28 30 regCM1_CM_SHAPER_RAMA_REGION_2_3 0 0xf52 4 0 2 CM_SHAPER_RAMA_EXP_REGION2_LUT_OFFSET 0 8 CM_SHAPER_RAMA_EXP_REGION2_NUM_SEGMENTS 12 14 CM_SHAPER_RAMA_EXP_REGION3_LUT_OFFSET 16 24 CM_SHAPER_RAMA_EXP_REGION3_NUM_SEGMENTS 28 30 regCM1_CM_SHAPER_RAMA_REGION_4_5 0 0xf53 4 0 2 CM_SHAPER_RAMA_EXP_REGION4_LUT_OFFSET 0 8 CM_SHAPER_RAMA_EXP_REGION4_NUM_SEGMENTS 12 14 CM_SHAPER_RAMA_EXP_REGION5_LUT_OFFSET 16 24 CM_SHAPER_RAMA_EXP_REGION5_NUM_SEGMENTS 28 30 regCM1_CM_SHAPER_RAMA_REGION_6_7 0 0xf54 4 0 2 CM_SHAPER_RAMA_EXP_REGION6_LUT_OFFSET 0 8 CM_SHAPER_RAMA_EXP_REGION6_NUM_SEGMENTS 12 14 CM_SHAPER_RAMA_EXP_REGION7_LUT_OFFSET 16 24 CM_SHAPER_RAMA_EXP_REGION7_NUM_SEGMENTS 28 30 regCM1_CM_SHAPER_RAMA_REGION_8_9 0 0xf55 4 0 2 CM_SHAPER_RAMA_EXP_REGION8_LUT_OFFSET 0 8 CM_SHAPER_RAMA_EXP_REGION8_NUM_SEGMENTS 12 14 CM_SHAPER_RAMA_EXP_REGION9_LUT_OFFSET 16 24 CM_SHAPER_RAMA_EXP_REGION9_NUM_SEGMENTS 28 30 regCM1_CM_SHAPER_RAMA_REGION_10_11 0 0xf56 4 0 2 CM_SHAPER_RAMA_EXP_REGION10_LUT_OFFSET 0 8 CM_SHAPER_RAMA_EXP_REGION10_NUM_SEGMENTS 12 14 CM_SHAPER_RAMA_EXP_REGION11_LUT_OFFSET 16 24 CM_SHAPER_RAMA_EXP_REGION11_NUM_SEGMENTS 28 30 regCM1_CM_SHAPER_RAMA_REGION_12_13 0 0xf57 4 0 2 CM_SHAPER_RAMA_EXP_REGION12_LUT_OFFSET 0 8 CM_SHAPER_RAMA_EXP_REGION12_NUM_SEGMENTS 12 14 CM_SHAPER_RAMA_EXP_REGION13_LUT_OFFSET 16 24 CM_SHAPER_RAMA_EXP_REGION13_NUM_SEGMENTS 28 30 regCM1_CM_SHAPER_RAMA_REGION_14_15 0 0xf58 4 0 2 CM_SHAPER_RAMA_EXP_REGION14_LUT_OFFSET 0 8 CM_SHAPER_RAMA_EXP_REGION14_NUM_SEGMENTS 12 14 CM_SHAPER_RAMA_EXP_REGION15_LUT_OFFSET 16 24 CM_SHAPER_RAMA_EXP_REGION15_NUM_SEGMENTS 28 30 regCM1_CM_SHAPER_RAMA_REGION_16_17 0 0xf59 4 0 2 CM_SHAPER_RAMA_EXP_REGION16_LUT_OFFSET 0 8 CM_SHAPER_RAMA_EXP_REGION16_NUM_SEGMENTS 12 14 CM_SHAPER_RAMA_EXP_REGION17_LUT_OFFSET 16 24 CM_SHAPER_RAMA_EXP_REGION17_NUM_SEGMENTS 28 30 regCM1_CM_SHAPER_RAMA_REGION_18_19 0 0xf5a 4 0 2 CM_SHAPER_RAMA_EXP_REGION18_LUT_OFFSET 0 8 CM_SHAPER_RAMA_EXP_REGION18_NUM_SEGMENTS 12 14 CM_SHAPER_RAMA_EXP_REGION19_LUT_OFFSET 16 24 CM_SHAPER_RAMA_EXP_REGION19_NUM_SEGMENTS 28 30 regCM1_CM_SHAPER_RAMA_REGION_20_21 0 0xf5b 4 0 2 CM_SHAPER_RAMA_EXP_REGION20_LUT_OFFSET 0 8 CM_SHAPER_RAMA_EXP_REGION20_NUM_SEGMENTS 12 14 CM_SHAPER_RAMA_EXP_REGION21_LUT_OFFSET 16 24 CM_SHAPER_RAMA_EXP_REGION21_NUM_SEGMENTS 28 30 regCM1_CM_SHAPER_RAMA_REGION_22_23 0 0xf5c 4 0 2 CM_SHAPER_RAMA_EXP_REGION22_LUT_OFFSET 0 8 CM_SHAPER_RAMA_EXP_REGION22_NUM_SEGMENTS 12 14 CM_SHAPER_RAMA_EXP_REGION23_LUT_OFFSET 16 24 CM_SHAPER_RAMA_EXP_REGION23_NUM_SEGMENTS 28 30 regCM1_CM_SHAPER_RAMA_REGION_24_25 0 0xf5d 4 0 2 CM_SHAPER_RAMA_EXP_REGION24_LUT_OFFSET 0 8 CM_SHAPER_RAMA_EXP_REGION24_NUM_SEGMENTS 12 14 CM_SHAPER_RAMA_EXP_REGION25_LUT_OFFSET 16 24 CM_SHAPER_RAMA_EXP_REGION25_NUM_SEGMENTS 28 30 regCM1_CM_SHAPER_RAMA_REGION_26_27 0 0xf5e 4 0 2 CM_SHAPER_RAMA_EXP_REGION26_LUT_OFFSET 0 8 CM_SHAPER_RAMA_EXP_REGION26_NUM_SEGMENTS 12 14 CM_SHAPER_RAMA_EXP_REGION27_LUT_OFFSET 16 24 CM_SHAPER_RAMA_EXP_REGION27_NUM_SEGMENTS 28 30 regCM1_CM_SHAPER_RAMA_REGION_28_29 0 0xf5f 4 0 2 CM_SHAPER_RAMA_EXP_REGION28_LUT_OFFSET 0 8 CM_SHAPER_RAMA_EXP_REGION28_NUM_SEGMENTS 12 14 CM_SHAPER_RAMA_EXP_REGION29_LUT_OFFSET 16 24 CM_SHAPER_RAMA_EXP_REGION29_NUM_SEGMENTS 28 30 regCM1_CM_SHAPER_RAMA_REGION_30_31 0 0xf60 4 0 2 CM_SHAPER_RAMA_EXP_REGION30_LUT_OFFSET 0 8 CM_SHAPER_RAMA_EXP_REGION30_NUM_SEGMENTS 12 14 CM_SHAPER_RAMA_EXP_REGION31_LUT_OFFSET 16 24 CM_SHAPER_RAMA_EXP_REGION31_NUM_SEGMENTS 28 30 regCM1_CM_SHAPER_RAMA_REGION_32_33 0 0xf61 4 0 2 CM_SHAPER_RAMA_EXP_REGION32_LUT_OFFSET 0 8 CM_SHAPER_RAMA_EXP_REGION32_NUM_SEGMENTS 12 14 CM_SHAPER_RAMA_EXP_REGION33_LUT_OFFSET 16 24 CM_SHAPER_RAMA_EXP_REGION33_NUM_SEGMENTS 28 30 regCM1_CM_SHAPER_RAMB_START_CNTL_B 0 0xf62 2 0 2 CM_SHAPER_RAMB_EXP_REGION_START_B 0 17 CM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_B 20 26 regCM1_CM_SHAPER_RAMB_START_CNTL_G 0 0xf63 2 0 2 CM_SHAPER_RAMB_EXP_REGION_START_G 0 17 CM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_G 20 26 regCM1_CM_SHAPER_RAMB_START_CNTL_R 0 0xf64 2 0 2 CM_SHAPER_RAMB_EXP_REGION_START_R 0 17 CM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_R 20 26 regCM1_CM_SHAPER_RAMB_END_CNTL_B 0 0xf65 2 0 2 CM_SHAPER_RAMB_EXP_REGION_END_B 0 15 CM_SHAPER_RAMB_EXP_REGION_END_BASE_B 16 29 regCM1_CM_SHAPER_RAMB_END_CNTL_G 0 0xf66 2 0 2 CM_SHAPER_RAMB_EXP_REGION_END_G 0 15 CM_SHAPER_RAMB_EXP_REGION_END_BASE_G 16 29 regCM1_CM_SHAPER_RAMB_END_CNTL_R 0 0xf67 2 0 2 CM_SHAPER_RAMB_EXP_REGION_END_R 0 15 CM_SHAPER_RAMB_EXP_REGION_END_BASE_R 16 29 regCM1_CM_SHAPER_RAMB_REGION_0_1 0 0xf68 4 0 2 CM_SHAPER_RAMB_EXP_REGION0_LUT_OFFSET 0 8 CM_SHAPER_RAMB_EXP_REGION0_NUM_SEGMENTS 12 14 CM_SHAPER_RAMB_EXP_REGION1_LUT_OFFSET 16 24 CM_SHAPER_RAMB_EXP_REGION1_NUM_SEGMENTS 28 30 regCM1_CM_SHAPER_RAMB_REGION_2_3 0 0xf69 4 0 2 CM_SHAPER_RAMB_EXP_REGION2_LUT_OFFSET 0 8 CM_SHAPER_RAMB_EXP_REGION2_NUM_SEGMENTS 12 14 CM_SHAPER_RAMB_EXP_REGION3_LUT_OFFSET 16 24 CM_SHAPER_RAMB_EXP_REGION3_NUM_SEGMENTS 28 30 regCM1_CM_SHAPER_RAMB_REGION_4_5 0 0xf6a 4 0 2 CM_SHAPER_RAMB_EXP_REGION4_LUT_OFFSET 0 8 CM_SHAPER_RAMB_EXP_REGION4_NUM_SEGMENTS 12 14 CM_SHAPER_RAMB_EXP_REGION5_LUT_OFFSET 16 24 CM_SHAPER_RAMB_EXP_REGION5_NUM_SEGMENTS 28 30 regCM1_CM_SHAPER_RAMB_REGION_6_7 0 0xf6b 4 0 2 CM_SHAPER_RAMB_EXP_REGION6_LUT_OFFSET 0 8 CM_SHAPER_RAMB_EXP_REGION6_NUM_SEGMENTS 12 14 CM_SHAPER_RAMB_EXP_REGION7_LUT_OFFSET 16 24 CM_SHAPER_RAMB_EXP_REGION7_NUM_SEGMENTS 28 30 regCM1_CM_SHAPER_RAMB_REGION_8_9 0 0xf6c 4 0 2 CM_SHAPER_RAMB_EXP_REGION8_LUT_OFFSET 0 8 CM_SHAPER_RAMB_EXP_REGION8_NUM_SEGMENTS 12 14 CM_SHAPER_RAMB_EXP_REGION9_LUT_OFFSET 16 24 CM_SHAPER_RAMB_EXP_REGION9_NUM_SEGMENTS 28 30 regCM1_CM_SHAPER_RAMB_REGION_10_11 0 0xf6d 4 0 2 CM_SHAPER_RAMB_EXP_REGION10_LUT_OFFSET 0 8 CM_SHAPER_RAMB_EXP_REGION10_NUM_SEGMENTS 12 14 CM_SHAPER_RAMB_EXP_REGION11_LUT_OFFSET 16 24 CM_SHAPER_RAMB_EXP_REGION11_NUM_SEGMENTS 28 30 regCM1_CM_SHAPER_RAMB_REGION_12_13 0 0xf6e 4 0 2 CM_SHAPER_RAMB_EXP_REGION12_LUT_OFFSET 0 8 CM_SHAPER_RAMB_EXP_REGION12_NUM_SEGMENTS 12 14 CM_SHAPER_RAMB_EXP_REGION13_LUT_OFFSET 16 24 CM_SHAPER_RAMB_EXP_REGION13_NUM_SEGMENTS 28 30 regCM1_CM_SHAPER_RAMB_REGION_14_15 0 0xf6f 4 0 2 CM_SHAPER_RAMB_EXP_REGION14_LUT_OFFSET 0 8 CM_SHAPER_RAMB_EXP_REGION14_NUM_SEGMENTS 12 14 CM_SHAPER_RAMB_EXP_REGION15_LUT_OFFSET 16 24 CM_SHAPER_RAMB_EXP_REGION15_NUM_SEGMENTS 28 30 regCM1_CM_SHAPER_RAMB_REGION_16_17 0 0xf70 4 0 2 CM_SHAPER_RAMB_EXP_REGION16_LUT_OFFSET 0 8 CM_SHAPER_RAMB_EXP_REGION16_NUM_SEGMENTS 12 14 CM_SHAPER_RAMB_EXP_REGION17_LUT_OFFSET 16 24 CM_SHAPER_RAMB_EXP_REGION17_NUM_SEGMENTS 28 30 regCM1_CM_SHAPER_RAMB_REGION_18_19 0 0xf71 4 0 2 CM_SHAPER_RAMB_EXP_REGION18_LUT_OFFSET 0 8 CM_SHAPER_RAMB_EXP_REGION18_NUM_SEGMENTS 12 14 CM_SHAPER_RAMB_EXP_REGION19_LUT_OFFSET 16 24 CM_SHAPER_RAMB_EXP_REGION19_NUM_SEGMENTS 28 30 regCM1_CM_SHAPER_RAMB_REGION_20_21 0 0xf72 4 0 2 CM_SHAPER_RAMB_EXP_REGION20_LUT_OFFSET 0 8 CM_SHAPER_RAMB_EXP_REGION20_NUM_SEGMENTS 12 14 CM_SHAPER_RAMB_EXP_REGION21_LUT_OFFSET 16 24 CM_SHAPER_RAMB_EXP_REGION21_NUM_SEGMENTS 28 30 regCM1_CM_SHAPER_RAMB_REGION_22_23 0 0xf73 4 0 2 CM_SHAPER_RAMB_EXP_REGION22_LUT_OFFSET 0 8 CM_SHAPER_RAMB_EXP_REGION22_NUM_SEGMENTS 12 14 CM_SHAPER_RAMB_EXP_REGION23_LUT_OFFSET 16 24 CM_SHAPER_RAMB_EXP_REGION23_NUM_SEGMENTS 28 30 regCM1_CM_SHAPER_RAMB_REGION_24_25 0 0xf74 4 0 2 CM_SHAPER_RAMB_EXP_REGION24_LUT_OFFSET 0 8 CM_SHAPER_RAMB_EXP_REGION24_NUM_SEGMENTS 12 14 CM_SHAPER_RAMB_EXP_REGION25_LUT_OFFSET 16 24 CM_SHAPER_RAMB_EXP_REGION25_NUM_SEGMENTS 28 30 regCM1_CM_SHAPER_RAMB_REGION_26_27 0 0xf75 4 0 2 CM_SHAPER_RAMB_EXP_REGION26_LUT_OFFSET 0 8 CM_SHAPER_RAMB_EXP_REGION26_NUM_SEGMENTS 12 14 CM_SHAPER_RAMB_EXP_REGION27_LUT_OFFSET 16 24 CM_SHAPER_RAMB_EXP_REGION27_NUM_SEGMENTS 28 30 regCM1_CM_SHAPER_RAMB_REGION_28_29 0 0xf76 4 0 2 CM_SHAPER_RAMB_EXP_REGION28_LUT_OFFSET 0 8 CM_SHAPER_RAMB_EXP_REGION28_NUM_SEGMENTS 12 14 CM_SHAPER_RAMB_EXP_REGION29_LUT_OFFSET 16 24 CM_SHAPER_RAMB_EXP_REGION29_NUM_SEGMENTS 28 30 regCM1_CM_SHAPER_RAMB_REGION_30_31 0 0xf77 4 0 2 CM_SHAPER_RAMB_EXP_REGION30_LUT_OFFSET 0 8 CM_SHAPER_RAMB_EXP_REGION30_NUM_SEGMENTS 12 14 CM_SHAPER_RAMB_EXP_REGION31_LUT_OFFSET 16 24 CM_SHAPER_RAMB_EXP_REGION31_NUM_SEGMENTS 28 30 regCM1_CM_SHAPER_RAMB_REGION_32_33 0 0xf78 4 0 2 CM_SHAPER_RAMB_EXP_REGION32_LUT_OFFSET 0 8 CM_SHAPER_RAMB_EXP_REGION32_NUM_SEGMENTS 12 14 CM_SHAPER_RAMB_EXP_REGION33_LUT_OFFSET 16 24 CM_SHAPER_RAMB_EXP_REGION33_NUM_SEGMENTS 28 30 regCM1_CM_MEM_PWR_CTRL2 0 0xf79 4 0 2 SHAPER_MEM_PWR_FORCE 8 9 SHAPER_MEM_PWR_DIS 10 10 HDR3DLUT_MEM_PWR_FORCE 12 13 HDR3DLUT_MEM_PWR_DIS 14 14 regCM1_CM_MEM_PWR_STATUS2 0 0xf7a 2 0 2 SHAPER_MEM_PWR_STATE 4 5 HDR3DLUT_MEM_PWR_STATE 6 7 regCM1_CM_3DLUT_MODE 0 0xf7b 3 0 2 CM_3DLUT_MODE 0 1 CM_3DLUT_SIZE 4 4 CM_3DLUT_MODE_CURRENT 8 9 regCM1_CM_3DLUT_INDEX 0 0xf7c 1 0 2 CM_3DLUT_INDEX 0 10 regCM1_CM_3DLUT_DATA 0 0xf7d 2 0 2 CM_3DLUT_DATA0 0 15 CM_3DLUT_DATA1 16 31 regCM1_CM_3DLUT_DATA_30BIT 0 0xf7e 1 0 2 CM_3DLUT_DATA_30BIT 2 31 regCM1_CM_3DLUT_READ_WRITE_CONTROL 0 0xf7f 4 0 2 CM_3DLUT_WRITE_EN_MASK 0 3 CM_3DLUT_RAM_SEL 4 4 CM_3DLUT_30BIT_EN 8 8 CM_3DLUT_READ_SEL 16 17 regCM1_CM_3DLUT_OUT_NORM_FACTOR 0 0xf80 1 0 2 CM_3DLUT_OUT_NORM_FACTOR 0 15 regCM1_CM_3DLUT_OUT_OFFSET_R 0 0xf81 2 0 2 CM_3DLUT_OUT_OFFSET_R 0 15 CM_3DLUT_OUT_SCALE_R 16 31 regCM1_CM_3DLUT_OUT_OFFSET_G 0 0xf82 2 0 2 CM_3DLUT_OUT_OFFSET_G 0 15 CM_3DLUT_OUT_SCALE_G 16 31 regCM1_CM_3DLUT_OUT_OFFSET_B 0 0xf83 2 0 2 CM_3DLUT_OUT_OFFSET_B 0 15 CM_3DLUT_OUT_SCALE_B 16 31 regCM1_CM_TEST_DEBUG_INDEX 0 0xf84 2 0 2 CM_TEST_DEBUG_INDEX 0 7 CM_TEST_DEBUG_WRITE_EN 8 8 regCM1_CM_TEST_DEBUG_DATA 0 0xf85 1 0 2 CM_TEST_DEBUG_DATA 0 31 regDPP_TOP1_DPP_CONTROL 0 0xe30 8 0 2 DPP_CLOCK_ENABLE 4 4 DPPCLK_G_GATE_DISABLE 8 8 DPPCLK_G_DYN_GATE_DISABLE 10 10 DPPCLK_G_DSCL_GATE_DISABLE 12 12 DPPCLK_R_GATE_DISABLE 14 14 DISPCLK_R_GATE_DISABLE 16 16 DISPCLK_G_GATE_DISABLE 18 18 DPP_TEST_CLK_SEL 28 30 regDPP_TOP1_DPP_SOFT_RESET 0 0xe31 4 0 2 CNVC_SOFT_RESET 0 0 DSCL_SOFT_RESET 4 4 CM_SOFT_RESET 8 8 OBUF_SOFT_RESET 12 12 regDPP_TOP1_DPP_CRC_VAL_R_G 0 0xe32 2 0 2 DPP_CRC_R_CR 0 15 DPP_CRC_G_Y 16 31 regDPP_TOP1_DPP_CRC_VAL_B_A 0 0xe33 2 0 2 DPP_CRC_B_CB 0 15 DPP_CRC_ALPHA 16 31 regDPP_TOP1_DPP_CRC_CTRL 0 0xe34 11 0 2 DPP_CRC_EN 0 0 DPP_CRC_CONT_EN 1 1 DPP_CRC_ONE_SHOT_PENDING 2 2 DPP_CRC_420_COMP_SEL 3 3 DPP_CRC_SRC_SEL 4 5 DPP_CRC_STEREO_EN 6 6 DPP_CRC_STEREO_MODE 7 8 DPP_CRC_INTERLACE_MODE 9 10 DPP_CRC_PIX_FORMAT_SEL 11 13 DPP_CRC_CURSOR_FORMAT_SEL 14 15 DPP_CRC_MASK 16 31 regDPP_TOP1_HOST_READ_CONTROL 0 0xe35 1 0 2 HOST_READ_RATE_CONTROL 0 7 regDC_PERFMON12_PERFCOUNTER_CNTL 0 0xf8f 11 0 2 PERFCOUNTER_EVENT_SEL 0 8 PERFCOUNTER_CVALUE_SEL 9 11 PERFCOUNTER_INC_MODE 12 14 PERFCOUNTER_HW_CNTL_SEL 15 15 PERFCOUNTER_RUNEN_MODE 16 16 PERFCOUNTER_CNTOFF_START_DIS 22 22 PERFCOUNTER_RESTART_EN 23 23 PERFCOUNTER_INT_EN 24 24 PERFCOUNTER_OFF_MASK 25 25 PERFCOUNTER_ACTIVE 26 26 PERFCOUNTER_CNTL_SEL 29 31 regDC_PERFMON12_PERFCOUNTER_CNTL2 0 0xf90 5 0 2 PERFCOUNTER_COUNTED_VALUE_TYPE 0 1 PERFCOUNTER_HW_STOP1_SEL 2 2 PERFCOUNTER_HW_STOP2_SEL 3 3 PERFCOUNTER_CNTOFF_SEL 8 13 PERFCOUNTER_CNTL2_SEL 29 31 regDC_PERFMON12_PERFCOUNTER_STATE 0 0xf91 16 0 2 PERFCOUNTER_CNT0_STATE 0 1 PERFCOUNTER_STATE_SEL0 2 2 PERFCOUNTER_CNT1_STATE 4 5 PERFCOUNTER_STATE_SEL1 6 6 PERFCOUNTER_CNT2_STATE 8 9 PERFCOUNTER_STATE_SEL2 10 10 PERFCOUNTER_CNT3_STATE 12 13 PERFCOUNTER_STATE_SEL3 14 14 PERFCOUNTER_CNT4_STATE 16 17 PERFCOUNTER_STATE_SEL4 18 18 PERFCOUNTER_CNT5_STATE 20 21 PERFCOUNTER_STATE_SEL5 22 22 PERFCOUNTER_CNT6_STATE 24 25 PERFCOUNTER_STATE_SEL6 26 26 PERFCOUNTER_CNT7_STATE 28 29 PERFCOUNTER_STATE_SEL7 30 30 regDC_PERFMON12_PERFMON_CNTL 0 0xf92 6 0 2 PERFMON_STATE 0 1 PERFMON_RPT_COUNT 8 27 PERFMON_CNTOFF_AND_OR 28 28 PERFMON_CNTOFF_INT_EN 29 29 PERFMON_CNTOFF_INT_STATUS 30 30 PERFMON_CNTOFF_INT_ACK 31 31 regDC_PERFMON12_PERFMON_CNTL2 0 0xf93 4 0 2 PERFMON_CNTOFF_INT_TYPE 0 0 PERFMON_CLK_ENABLE 1 1 PERFMON_RUN_ENABLE_START_SEL 2 9 PERFMON_RUN_ENABLE_STOP_SEL 10 17 regDC_PERFMON12_PERFMON_CVALUE_INT_MISC 0 0xf94 17 0 2 PERFCOUNTER_INT0_STATUS 0 0 PERFCOUNTER_INT1_STATUS 1 1 PERFCOUNTER_INT2_STATUS 2 2 PERFCOUNTER_INT3_STATUS 3 3 PERFCOUNTER_INT4_STATUS 4 4 PERFCOUNTER_INT5_STATUS 5 5 PERFCOUNTER_INT6_STATUS 6 6 PERFCOUNTER_INT7_STATUS 7 7 PERFCOUNTER_INT0_ACK 8 8 PERFCOUNTER_INT1_ACK 9 9 PERFCOUNTER_INT2_ACK 10 10 PERFCOUNTER_INT3_ACK 11 11 PERFCOUNTER_INT4_ACK 12 12 PERFCOUNTER_INT5_ACK 13 13 PERFCOUNTER_INT6_ACK 14 14 PERFCOUNTER_INT7_ACK 15 15 PERFMON_CVALUE_HI 16 31 regDC_PERFMON12_PERFMON_CVALUE_LOW 0 0xf95 1 0 2 PERFMON_CVALUE_LOW 0 31 regDC_PERFMON12_PERFMON_HI 0 0xf96 2 0 2 PERFMON_HI 0 15 PERFMON_READ_SEL 29 31 regDC_PERFMON12_PERFMON_LOW 0 0xf97 1 0 2 PERFMON_LOW 0 31 regCNVC_CFG2_CNVC_SURFACE_PIXEL_FORMAT 0 0xfa5 2 0 2 CNVC_SURFACE_PIXEL_FORMAT 0 6 CNVC_ALPHA_PLANE_ENABLE 8 8 regCNVC_CFG2_FORMAT_CONTROL 0 0xfa6 11 0 2 FORMAT_EXPANSION_MODE 0 0 FORMAT_CNV16 4 4 ALPHA_EN 8 8 CNVC_BYPASS 12 12 CNVC_BYPASS_MSB_ALIGN 13 13 CLAMP_POSITIVE 16 16 CLAMP_POSITIVE_C 17 17 CNVC_UPDATE_PENDING 20 20 FORMAT_CROSSBAR_R 24 25 FORMAT_CROSSBAR_G 26 27 FORMAT_CROSSBAR_B 28 29 regCNVC_CFG2_FCNV_FP_BIAS_R 0 0xfa7 1 0 2 FCNV_FP_BIAS_R 0 18 regCNVC_CFG2_FCNV_FP_BIAS_G 0 0xfa8 1 0 2 FCNV_FP_BIAS_G 0 18 regCNVC_CFG2_FCNV_FP_BIAS_B 0 0xfa9 1 0 2 FCNV_FP_BIAS_B 0 18 regCNVC_CFG2_FCNV_FP_SCALE_R 0 0xfaa 1 0 2 FCNV_FP_SCALE_R 0 18 regCNVC_CFG2_FCNV_FP_SCALE_G 0 0xfab 1 0 2 FCNV_FP_SCALE_G 0 18 regCNVC_CFG2_FCNV_FP_SCALE_B 0 0xfac 1 0 2 FCNV_FP_SCALE_B 0 18 regCNVC_CFG2_COLOR_KEYER_CONTROL 0 0xfad 2 0 2 COLOR_KEYER_EN 0 0 COLOR_KEYER_MODE 4 5 regCNVC_CFG2_COLOR_KEYER_ALPHA 0 0xfae 2 0 2 COLOR_KEYER_ALPHA_LOW 0 15 COLOR_KEYER_ALPHA_HIGH 16 31 regCNVC_CFG2_COLOR_KEYER_RED 0 0xfaf 2 0 2 COLOR_KEYER_RED_LOW 0 15 COLOR_KEYER_RED_HIGH 16 31 regCNVC_CFG2_COLOR_KEYER_GREEN 0 0xfb0 2 0 2 COLOR_KEYER_GREEN_LOW 0 15 COLOR_KEYER_GREEN_HIGH 16 31 regCNVC_CFG2_COLOR_KEYER_BLUE 0 0xfb1 2 0 2 COLOR_KEYER_BLUE_LOW 0 15 COLOR_KEYER_BLUE_HIGH 16 31 regCNVC_CFG2_ALPHA_2BIT_LUT 0 0xfb3 4 0 2 ALPHA_2BIT_LUT0 0 7 ALPHA_2BIT_LUT1 8 15 ALPHA_2BIT_LUT2 16 23 ALPHA_2BIT_LUT3 24 31 regCNVC_CFG2_PRE_DEALPHA 0 0xfb4 2 0 2 PRE_DEALPHA_EN 0 0 PRE_DEALPHA_ABLND_EN 4 4 regCNVC_CFG2_PRE_CSC_MODE 0 0xfb5 2 0 2 PRE_CSC_MODE 0 1 PRE_CSC_MODE_CURRENT 2 3 regCNVC_CFG2_PRE_CSC_C11_C12 0 0xfb6 2 0 2 PRE_CSC_C11 0 15 PRE_CSC_C12 16 31 regCNVC_CFG2_PRE_CSC_C13_C14 0 0xfb7 2 0 2 PRE_CSC_C13 0 15 PRE_CSC_C14 16 31 regCNVC_CFG2_PRE_CSC_C21_C22 0 0xfb8 2 0 2 PRE_CSC_C21 0 15 PRE_CSC_C22 16 31 regCNVC_CFG2_PRE_CSC_C23_C24 0 0xfb9 2 0 2 PRE_CSC_C23 0 15 PRE_CSC_C24 16 31 regCNVC_CFG2_PRE_CSC_C31_C32 0 0xfba 2 0 2 PRE_CSC_C31 0 15 PRE_CSC_C32 16 31 regCNVC_CFG2_PRE_CSC_C33_C34 0 0xfbb 2 0 2 PRE_CSC_C33 0 15 PRE_CSC_C34 16 31 regCNVC_CFG2_PRE_CSC_B_C11_C12 0 0xfbc 2 0 2 PRE_CSC_B_C11 0 15 PRE_CSC_B_C12 16 31 regCNVC_CFG2_PRE_CSC_B_C13_C14 0 0xfbd 2 0 2 PRE_CSC_B_C13 0 15 PRE_CSC_B_C14 16 31 regCNVC_CFG2_PRE_CSC_B_C21_C22 0 0xfbe 2 0 2 PRE_CSC_B_C21 0 15 PRE_CSC_B_C22 16 31 regCNVC_CFG2_PRE_CSC_B_C23_C24 0 0xfbf 2 0 2 PRE_CSC_B_C23 0 15 PRE_CSC_B_C24 16 31 regCNVC_CFG2_PRE_CSC_B_C31_C32 0 0xfc0 2 0 2 PRE_CSC_B_C31 0 15 PRE_CSC_B_C32 16 31 regCNVC_CFG2_PRE_CSC_B_C33_C34 0 0xfc1 2 0 2 PRE_CSC_B_C33 0 15 PRE_CSC_B_C34 16 31 regCNVC_CFG2_CNVC_COEF_FORMAT 0 0xfc2 1 0 2 PRE_CSC_COEF_FORMAT 0 0 regCNVC_CFG2_PRE_DEGAM 0 0xfc3 2 0 2 PRE_DEGAM_MODE 0 1 PRE_DEGAM_SELECT 4 6 regCNVC_CFG2_PRE_REALPHA 0 0xfc4 2 0 2 PRE_REALPHA_EN 0 0 PRE_REALPHA_ABLND_EN 4 4 regCNVC_CUR2_CURSOR0_CONTROL 0 0xfc7 7 0 2 CUR0_ENABLE 0 0 CUR0_EXPANSION_MODE 1 1 CUR0_PIX_INV_MODE 2 2 CUR0_ROM_EN 3 3 CUR0_MODE 4 6 CUR0_PIXEL_ALPHA_MOD_EN 7 7 CUR0_UPDATE_PENDING 16 16 regCNVC_CUR2_CURSOR0_COLOR0 0 0xfc8 1 0 2 CUR0_COLOR0 0 23 regCNVC_CUR2_CURSOR0_COLOR1 0 0xfc9 1 0 2 CUR0_COLOR1 0 23 regCNVC_CUR2_CURSOR0_FP_SCALE_BIAS 0 0xfca 2 0 2 CUR0_FP_SCALE 0 15 CUR0_FP_BIAS 16 31 regDSCL2_SCL_COEF_RAM_TAP_SELECT 0 0xfcf 3 0 2 SCL_COEF_RAM_TAP_PAIR_IDX 0 1 SCL_COEF_RAM_PHASE 8 13 SCL_COEF_RAM_FILTER_TYPE 16 18 regDSCL2_SCL_COEF_RAM_TAP_DATA 0 0xfd0 4 0 2 SCL_COEF_RAM_EVEN_TAP_COEF 0 13 SCL_COEF_RAM_EVEN_TAP_COEF_EN 15 15 SCL_COEF_RAM_ODD_TAP_COEF 16 29 SCL_COEF_RAM_ODD_TAP_COEF_EN 31 31 regDSCL2_SCL_MODE 0 0xfd1 6 0 2 DSCL_MODE 0 2 SCL_COEF_RAM_SELECT 8 8 SCL_COEF_RAM_SELECT_CURRENT 12 12 SCL_CHROMA_COEF_MODE 16 16 SCL_ALPHA_COEF_MODE 20 20 SCL_COEF_RAM_SELECT_RD 24 24 regDSCL2_SCL_TAP_CONTROL 0 0xfd2 4 0 2 SCL_V_NUM_TAPS 0 2 SCL_H_NUM_TAPS 4 6 SCL_V_NUM_TAPS_C 8 10 SCL_H_NUM_TAPS_C 12 14 regDSCL2_DSCL_CONTROL 0 0xfd3 1 0 2 SCL_BOUNDARY_MODE 0 0 regDSCL2_DSCL_2TAP_CONTROL 0 0xfd4 6 0 2 SCL_H_2TAP_HARDCODE_COEF_EN 0 0 SCL_H_2TAP_SHARP_EN 4 4 SCL_H_2TAP_SHARP_FACTOR 8 10 SCL_V_2TAP_HARDCODE_COEF_EN 16 16 SCL_V_2TAP_SHARP_EN 20 20 SCL_V_2TAP_SHARP_FACTOR 24 26 regDSCL2_SCL_MANUAL_REPLICATE_CONTROL 0 0xfd5 2 0 2 SCL_V_MANUAL_REPLICATE_FACTOR 0 3 SCL_H_MANUAL_REPLICATE_FACTOR 8 11 regDSCL2_SCL_HORZ_FILTER_SCALE_RATIO 0 0xfd6 1 0 2 SCL_H_SCALE_RATIO 0 26 regDSCL2_SCL_HORZ_FILTER_INIT 0 0xfd7 2 0 2 SCL_H_INIT_FRAC 0 23 SCL_H_INIT_INT 24 27 regDSCL2_SCL_HORZ_FILTER_SCALE_RATIO_C 0 0xfd8 1 0 2 SCL_H_SCALE_RATIO_C 0 26 regDSCL2_SCL_HORZ_FILTER_INIT_C 0 0xfd9 2 0 2 SCL_H_INIT_FRAC_C 0 23 SCL_H_INIT_INT_C 24 27 regDSCL2_SCL_VERT_FILTER_SCALE_RATIO 0 0xfda 1 0 2 SCL_V_SCALE_RATIO 0 26 regDSCL2_SCL_VERT_FILTER_INIT 0 0xfdb 2 0 2 SCL_V_INIT_FRAC 0 23 SCL_V_INIT_INT 24 27 regDSCL2_SCL_VERT_FILTER_INIT_BOT 0 0xfdc 2 0 2 SCL_V_INIT_FRAC_BOT 0 23 SCL_V_INIT_INT_BOT 24 27 regDSCL2_SCL_VERT_FILTER_SCALE_RATIO_C 0 0xfdd 1 0 2 SCL_V_SCALE_RATIO_C 0 26 regDSCL2_SCL_VERT_FILTER_INIT_C 0 0xfde 2 0 2 SCL_V_INIT_FRAC_C 0 23 SCL_V_INIT_INT_C 24 27 regDSCL2_SCL_VERT_FILTER_INIT_BOT_C 0 0xfdf 2 0 2 SCL_V_INIT_FRAC_BOT_C 0 23 SCL_V_INIT_INT_BOT_C 24 27 regDSCL2_SCL_BLACK_COLOR 0 0xfe0 2 0 2 SCL_BLACK_COLOR_RGB_Y 0 15 SCL_BLACK_COLOR_CBCR 16 31 regDSCL2_DSCL_UPDATE 0 0xfe1 1 0 2 SCL_UPDATE_PENDING 0 0 regDSCL2_DSCL_AUTOCAL 0 0xfe2 3 0 2 AUTOCAL_MODE 0 1 AUTOCAL_NUM_PIPE 8 9 AUTOCAL_PIPE_ID 12 13 regDSCL2_DSCL_EXT_OVERSCAN_LEFT_RIGHT 0 0xfe3 2 0 2 EXT_OVERSCAN_RIGHT 0 12 EXT_OVERSCAN_LEFT 16 28 regDSCL2_DSCL_EXT_OVERSCAN_TOP_BOTTOM 0 0xfe4 2 0 2 EXT_OVERSCAN_BOTTOM 0 12 EXT_OVERSCAN_TOP 16 28 regDSCL2_OTG_H_BLANK 0 0xfe5 2 0 2 OTG_H_BLANK_START 0 13 OTG_H_BLANK_END 16 29 regDSCL2_OTG_V_BLANK 0 0xfe6 2 0 2 OTG_V_BLANK_START 0 13 OTG_V_BLANK_END 16 29 regDSCL2_RECOUT_START 0 0xfe7 2 0 2 RECOUT_START_X 0 12 RECOUT_START_Y 16 28 regDSCL2_RECOUT_SIZE 0 0xfe8 2 0 2 RECOUT_WIDTH 0 13 RECOUT_HEIGHT 16 29 regDSCL2_MPC_SIZE 0 0xfe9 2 0 2 MPC_WIDTH 0 13 MPC_HEIGHT 16 29 regDSCL2_LB_DATA_FORMAT 0 0xfea 2 0 2 INTERLEAVE_EN 0 0 ALPHA_EN 4 4 regDSCL2_LB_MEMORY_CTRL 0 0xfeb 4 0 2 MEMORY_CONFIG 0 1 LB_MAX_PARTITIONS 8 13 LB_NUM_PARTITIONS 16 22 LB_NUM_PARTITIONS_C 24 30 regDSCL2_LB_V_COUNTER 0 0xfec 2 0 2 V_COUNTER 0 12 V_COUNTER_C 16 28 regDSCL2_DSCL_MEM_PWR_CTRL 0 0xfed 15 0 2 LUT_MEM_PWR_FORCE 0 1 LUT_MEM_PWR_DIS 2 2 LB_G1_MEM_PWR_FORCE 4 5 LB_G1_MEM_PWR_DIS 6 6 LB_G2_MEM_PWR_FORCE 8 9 LB_G2_MEM_PWR_DIS 10 10 LB_G3_MEM_PWR_FORCE 12 13 LB_G3_MEM_PWR_DIS 14 14 LB_G4_MEM_PWR_FORCE 16 17 LB_G4_MEM_PWR_DIS 18 18 LB_G5_MEM_PWR_FORCE 20 21 LB_G5_MEM_PWR_DIS 22 22 LB_G6_MEM_PWR_FORCE 24 25 LB_G6_MEM_PWR_DIS 26 26 LB_MEM_PWR_MODE 28 28 regDSCL2_DSCL_MEM_PWR_STATUS 0 0xfee 7 0 2 LUT_MEM_PWR_STATE 0 1 LB_G1_MEM_PWR_STATE 2 3 LB_G2_MEM_PWR_STATE 4 5 LB_G3_MEM_PWR_STATE 6 7 LB_G4_MEM_PWR_STATE 8 9 LB_G5_MEM_PWR_STATE 10 11 LB_G6_MEM_PWR_STATE 12 13 regDSCL2_OBUF_CONTROL 0 0xfef 4 0 2 OBUF_BYPASS 0 0 OBUF_USE_FULL_BUFFER 1 1 OBUF_IS_HALF_RECOUT_WIDTH 2 2 OBUF_OUT_HOLD_CNT 4 7 regDSCL2_OBUF_MEM_PWR_CTRL 0 0xff0 4 0 2 OBUF_MEM_PWR_FORCE 0 1 OBUF_MEM_PWR_DIS 2 2 OBUF_MEM_PWR_MODE 8 8 OBUF_MEM_PWR_STATE 16 17 regCM2_CM_CONTROL 0 0xff6 2 0 2 CM_BYPASS 0 0 CM_UPDATE_PENDING 8 8 regCM2_CM_POST_CSC_CONTROL 0 0xff7 2 0 2 CM_POST_CSC_MODE 0 1 CM_POST_CSC_MODE_CURRENT 2 3 regCM2_CM_POST_CSC_C11_C12 0 0xff8 2 0 2 CM_POST_CSC_C11 0 15 CM_POST_CSC_C12 16 31 regCM2_CM_POST_CSC_C13_C14 0 0xff9 2 0 2 CM_POST_CSC_C13 0 15 CM_POST_CSC_C14 16 31 regCM2_CM_POST_CSC_C21_C22 0 0xffa 2 0 2 CM_POST_CSC_C21 0 15 CM_POST_CSC_C22 16 31 regCM2_CM_POST_CSC_C23_C24 0 0xffb 2 0 2 CM_POST_CSC_C23 0 15 CM_POST_CSC_C24 16 31 regCM2_CM_POST_CSC_C31_C32 0 0xffc 2 0 2 CM_POST_CSC_C31 0 15 CM_POST_CSC_C32 16 31 regCM2_CM_POST_CSC_C33_C34 0 0xffd 2 0 2 CM_POST_CSC_C33 0 15 CM_POST_CSC_C34 16 31 regCM2_CM_POST_CSC_B_C11_C12 0 0xffe 2 0 2 CM_POST_CSC_B_C11 0 15 CM_POST_CSC_B_C12 16 31 regCM2_CM_POST_CSC_B_C13_C14 0 0xfff 2 0 2 CM_POST_CSC_B_C13 0 15 CM_POST_CSC_B_C14 16 31 regCM2_CM_POST_CSC_B_C21_C22 0 0x1000 2 0 2 CM_POST_CSC_B_C21 0 15 CM_POST_CSC_B_C22 16 31 regCM2_CM_POST_CSC_B_C23_C24 0 0x1001 2 0 2 CM_POST_CSC_B_C23 0 15 CM_POST_CSC_B_C24 16 31 regCM2_CM_POST_CSC_B_C31_C32 0 0x1002 2 0 2 CM_POST_CSC_B_C31 0 15 CM_POST_CSC_B_C32 16 31 regCM2_CM_POST_CSC_B_C33_C34 0 0x1003 2 0 2 CM_POST_CSC_B_C33 0 15 CM_POST_CSC_B_C34 16 31 regCM2_CM_GAMUT_REMAP_CONTROL 0 0x1004 2 0 2 CM_GAMUT_REMAP_MODE 0 1 CM_GAMUT_REMAP_MODE_CURRENT 2 3 regCM2_CM_GAMUT_REMAP_C11_C12 0 0x1005 2 0 2 CM_GAMUT_REMAP_C11 0 15 CM_GAMUT_REMAP_C12 16 31 regCM2_CM_GAMUT_REMAP_C13_C14 0 0x1006 2 0 2 CM_GAMUT_REMAP_C13 0 15 CM_GAMUT_REMAP_C14 16 31 regCM2_CM_GAMUT_REMAP_C21_C22 0 0x1007 2 0 2 CM_GAMUT_REMAP_C21 0 15 CM_GAMUT_REMAP_C22 16 31 regCM2_CM_GAMUT_REMAP_C23_C24 0 0x1008 2 0 2 CM_GAMUT_REMAP_C23 0 15 CM_GAMUT_REMAP_C24 16 31 regCM2_CM_GAMUT_REMAP_C31_C32 0 0x1009 2 0 2 CM_GAMUT_REMAP_C31 0 15 CM_GAMUT_REMAP_C32 16 31 regCM2_CM_GAMUT_REMAP_C33_C34 0 0x100a 2 0 2 CM_GAMUT_REMAP_C33 0 15 CM_GAMUT_REMAP_C34 16 31 regCM2_CM_GAMUT_REMAP_B_C11_C12 0 0x100b 2 0 2 CM_GAMUT_REMAP_B_C11 0 15 CM_GAMUT_REMAP_B_C12 16 31 regCM2_CM_GAMUT_REMAP_B_C13_C14 0 0x100c 2 0 2 CM_GAMUT_REMAP_B_C13 0 15 CM_GAMUT_REMAP_B_C14 16 31 regCM2_CM_GAMUT_REMAP_B_C21_C22 0 0x100d 2 0 2 CM_GAMUT_REMAP_B_C21 0 15 CM_GAMUT_REMAP_B_C22 16 31 regCM2_CM_GAMUT_REMAP_B_C23_C24 0 0x100e 2 0 2 CM_GAMUT_REMAP_B_C23 0 15 CM_GAMUT_REMAP_B_C24 16 31 regCM2_CM_GAMUT_REMAP_B_C31_C32 0 0x100f 2 0 2 CM_GAMUT_REMAP_B_C31 0 15 CM_GAMUT_REMAP_B_C32 16 31 regCM2_CM_GAMUT_REMAP_B_C33_C34 0 0x1010 2 0 2 CM_GAMUT_REMAP_B_C33 0 15 CM_GAMUT_REMAP_B_C34 16 31 regCM2_CM_BIAS_CR_R 0 0x1011 1 0 2 CM_BIAS_CR_R 0 15 regCM2_CM_BIAS_Y_G_CB_B 0 0x1012 2 0 2 CM_BIAS_Y_G 0 15 CM_BIAS_CB_B 16 31 regCM2_CM_GAMCOR_CONTROL 0 0x1013 5 0 2 CM_GAMCOR_MODE 0 1 CM_GAMCOR_SELECT 2 2 CM_GAMCOR_PWL_DISABLE 3 3 CM_GAMCOR_MODE_CURRENT 4 5 CM_GAMCOR_SELECT_CURRENT 6 6 regCM2_CM_GAMCOR_LUT_INDEX 0 0x1014 1 0 2 CM_GAMCOR_LUT_INDEX 0 8 regCM2_CM_GAMCOR_LUT_DATA 0 0x1015 1 0 2 CM_GAMCOR_LUT_DATA 0 17 regCM2_CM_GAMCOR_LUT_CONTROL 0 0x1016 5 0 2 CM_GAMCOR_LUT_WRITE_COLOR_MASK 0 2 CM_GAMCOR_LUT_READ_COLOR_SEL 3 4 CM_GAMCOR_LUT_READ_DBG 5 5 CM_GAMCOR_LUT_HOST_SEL 6 6 CM_GAMCOR_LUT_CONFIG_MODE 7 7 regCM2_CM_GAMCOR_RAMA_START_CNTL_B 0 0x1017 2 0 2 CM_GAMCOR_RAMA_EXP_REGION_START_B 0 17 CM_GAMCOR_RAMA_EXP_REGION_START_SEGMENT_B 20 26 regCM2_CM_GAMCOR_RAMA_START_CNTL_G 0 0x1018 2 0 2 CM_GAMCOR_RAMA_EXP_REGION_START_G 0 17 CM_GAMCOR_RAMA_EXP_REGION_START_SEGMENT_G 20 26 regCM2_CM_GAMCOR_RAMA_START_CNTL_R 0 0x1019 2 0 2 CM_GAMCOR_RAMA_EXP_REGION_START_R 0 17 CM_GAMCOR_RAMA_EXP_REGION_START_SEGMENT_R 20 26 regCM2_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B 0 0x101a 1 0 2 CM_GAMCOR_RAMA_EXP_REGION_START_SLOPE_B 0 17 regCM2_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G 0 0x101b 1 0 2 CM_GAMCOR_RAMA_EXP_REGION_START_SLOPE_G 0 17 regCM2_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R 0 0x101c 1 0 2 CM_GAMCOR_RAMA_EXP_REGION_START_SLOPE_R 0 17 regCM2_CM_GAMCOR_RAMA_START_BASE_CNTL_B 0 0x101d 1 0 2 CM_GAMCOR_RAMA_EXP_REGION_START_BASE_B 0 17 regCM2_CM_GAMCOR_RAMA_START_BASE_CNTL_G 0 0x101e 1 0 2 CM_GAMCOR_RAMA_EXP_REGION_START_BASE_G 0 17 regCM2_CM_GAMCOR_RAMA_START_BASE_CNTL_R 0 0x101f 1 0 2 CM_GAMCOR_RAMA_EXP_REGION_START_BASE_R 0 17 regCM2_CM_GAMCOR_RAMA_END_CNTL1_B 0 0x1020 1 0 2 CM_GAMCOR_RAMA_EXP_REGION_END_BASE_B 0 17 regCM2_CM_GAMCOR_RAMA_END_CNTL2_B 0 0x1021 2 0 2 CM_GAMCOR_RAMA_EXP_REGION_END_B 0 15 CM_GAMCOR_RAMA_EXP_REGION_END_SLOPE_B 16 31 regCM2_CM_GAMCOR_RAMA_END_CNTL1_G 0 0x1022 1 0 2 CM_GAMCOR_RAMA_EXP_REGION_END_BASE_G 0 17 regCM2_CM_GAMCOR_RAMA_END_CNTL2_G 0 0x1023 2 0 2 CM_GAMCOR_RAMA_EXP_REGION_END_G 0 15 CM_GAMCOR_RAMA_EXP_REGION_END_SLOPE_G 16 31 regCM2_CM_GAMCOR_RAMA_END_CNTL1_R 0 0x1024 1 0 2 CM_GAMCOR_RAMA_EXP_REGION_END_BASE_R 0 17 regCM2_CM_GAMCOR_RAMA_END_CNTL2_R 0 0x1025 2 0 2 CM_GAMCOR_RAMA_EXP_REGION_END_R 0 15 CM_GAMCOR_RAMA_EXP_REGION_END_SLOPE_R 16 31 regCM2_CM_GAMCOR_RAMA_OFFSET_B 0 0x1026 1 0 2 CM_GAMCOR_RAMA_OFFSET_B 0 18 regCM2_CM_GAMCOR_RAMA_OFFSET_G 0 0x1027 1 0 2 CM_GAMCOR_RAMA_OFFSET_G 0 18 regCM2_CM_GAMCOR_RAMA_OFFSET_R 0 0x1028 1 0 2 CM_GAMCOR_RAMA_OFFSET_R 0 18 regCM2_CM_GAMCOR_RAMA_REGION_0_1 0 0x1029 4 0 2 CM_GAMCOR_RAMA_EXP_REGION0_LUT_OFFSET 0 8 CM_GAMCOR_RAMA_EXP_REGION0_NUM_SEGMENTS 12 14 CM_GAMCOR_RAMA_EXP_REGION1_LUT_OFFSET 16 24 CM_GAMCOR_RAMA_EXP_REGION1_NUM_SEGMENTS 28 30 regCM2_CM_GAMCOR_RAMA_REGION_2_3 0 0x102a 4 0 2 CM_GAMCOR_RAMA_EXP_REGION2_LUT_OFFSET 0 8 CM_GAMCOR_RAMA_EXP_REGION2_NUM_SEGMENTS 12 14 CM_GAMCOR_RAMA_EXP_REGION3_LUT_OFFSET 16 24 CM_GAMCOR_RAMA_EXP_REGION3_NUM_SEGMENTS 28 30 regCM2_CM_GAMCOR_RAMA_REGION_4_5 0 0x102b 4 0 2 CM_GAMCOR_RAMA_EXP_REGION4_LUT_OFFSET 0 8 CM_GAMCOR_RAMA_EXP_REGION4_NUM_SEGMENTS 12 14 CM_GAMCOR_RAMA_EXP_REGION5_LUT_OFFSET 16 24 CM_GAMCOR_RAMA_EXP_REGION5_NUM_SEGMENTS 28 30 regCM2_CM_GAMCOR_RAMA_REGION_6_7 0 0x102c 4 0 2 CM_GAMCOR_RAMA_EXP_REGION6_LUT_OFFSET 0 8 CM_GAMCOR_RAMA_EXP_REGION6_NUM_SEGMENTS 12 14 CM_GAMCOR_RAMA_EXP_REGION7_LUT_OFFSET 16 24 CM_GAMCOR_RAMA_EXP_REGION7_NUM_SEGMENTS 28 30 regCM2_CM_GAMCOR_RAMA_REGION_8_9 0 0x102d 4 0 2 CM_GAMCOR_RAMA_EXP_REGION8_LUT_OFFSET 0 8 CM_GAMCOR_RAMA_EXP_REGION8_NUM_SEGMENTS 12 14 CM_GAMCOR_RAMA_EXP_REGION9_LUT_OFFSET 16 24 CM_GAMCOR_RAMA_EXP_REGION9_NUM_SEGMENTS 28 30 regCM2_CM_GAMCOR_RAMA_REGION_10_11 0 0x102e 4 0 2 CM_GAMCOR_RAMA_EXP_REGION10_LUT_OFFSET 0 8 CM_GAMCOR_RAMA_EXP_REGION10_NUM_SEGMENTS 12 14 CM_GAMCOR_RAMA_EXP_REGION11_LUT_OFFSET 16 24 CM_GAMCOR_RAMA_EXP_REGION11_NUM_SEGMENTS 28 30 regCM2_CM_GAMCOR_RAMA_REGION_12_13 0 0x102f 4 0 2 CM_GAMCOR_RAMA_EXP_REGION12_LUT_OFFSET 0 8 CM_GAMCOR_RAMA_EXP_REGION12_NUM_SEGMENTS 12 14 CM_GAMCOR_RAMA_EXP_REGION13_LUT_OFFSET 16 24 CM_GAMCOR_RAMA_EXP_REGION13_NUM_SEGMENTS 28 30 regCM2_CM_GAMCOR_RAMA_REGION_14_15 0 0x1030 4 0 2 CM_GAMCOR_RAMA_EXP_REGION14_LUT_OFFSET 0 8 CM_GAMCOR_RAMA_EXP_REGION14_NUM_SEGMENTS 12 14 CM_GAMCOR_RAMA_EXP_REGION15_LUT_OFFSET 16 24 CM_GAMCOR_RAMA_EXP_REGION15_NUM_SEGMENTS 28 30 regCM2_CM_GAMCOR_RAMA_REGION_16_17 0 0x1031 4 0 2 CM_GAMCOR_RAMA_EXP_REGION16_LUT_OFFSET 0 8 CM_GAMCOR_RAMA_EXP_REGION16_NUM_SEGMENTS 12 14 CM_GAMCOR_RAMA_EXP_REGION17_LUT_OFFSET 16 24 CM_GAMCOR_RAMA_EXP_REGION17_NUM_SEGMENTS 28 30 regCM2_CM_GAMCOR_RAMA_REGION_18_19 0 0x1032 4 0 2 CM_GAMCOR_RAMA_EXP_REGION18_LUT_OFFSET 0 8 CM_GAMCOR_RAMA_EXP_REGION18_NUM_SEGMENTS 12 14 CM_GAMCOR_RAMA_EXP_REGION19_LUT_OFFSET 16 24 CM_GAMCOR_RAMA_EXP_REGION19_NUM_SEGMENTS 28 30 regCM2_CM_GAMCOR_RAMA_REGION_20_21 0 0x1033 4 0 2 CM_GAMCOR_RAMA_EXP_REGION20_LUT_OFFSET 0 8 CM_GAMCOR_RAMA_EXP_REGION20_NUM_SEGMENTS 12 14 CM_GAMCOR_RAMA_EXP_REGION21_LUT_OFFSET 16 24 CM_GAMCOR_RAMA_EXP_REGION21_NUM_SEGMENTS 28 30 regCM2_CM_GAMCOR_RAMA_REGION_22_23 0 0x1034 4 0 2 CM_GAMCOR_RAMA_EXP_REGION22_LUT_OFFSET 0 8 CM_GAMCOR_RAMA_EXP_REGION22_NUM_SEGMENTS 12 14 CM_GAMCOR_RAMA_EXP_REGION23_LUT_OFFSET 16 24 CM_GAMCOR_RAMA_EXP_REGION23_NUM_SEGMENTS 28 30 regCM2_CM_GAMCOR_RAMA_REGION_24_25 0 0x1035 4 0 2 CM_GAMCOR_RAMA_EXP_REGION24_LUT_OFFSET 0 8 CM_GAMCOR_RAMA_EXP_REGION24_NUM_SEGMENTS 12 14 CM_GAMCOR_RAMA_EXP_REGION25_LUT_OFFSET 16 24 CM_GAMCOR_RAMA_EXP_REGION25_NUM_SEGMENTS 28 30 regCM2_CM_GAMCOR_RAMA_REGION_26_27 0 0x1036 4 0 2 CM_GAMCOR_RAMA_EXP_REGION26_LUT_OFFSET 0 8 CM_GAMCOR_RAMA_EXP_REGION26_NUM_SEGMENTS 12 14 CM_GAMCOR_RAMA_EXP_REGION27_LUT_OFFSET 16 24 CM_GAMCOR_RAMA_EXP_REGION27_NUM_SEGMENTS 28 30 regCM2_CM_GAMCOR_RAMA_REGION_28_29 0 0x1037 4 0 2 CM_GAMCOR_RAMA_EXP_REGION28_LUT_OFFSET 0 8 CM_GAMCOR_RAMA_EXP_REGION28_NUM_SEGMENTS 12 14 CM_GAMCOR_RAMA_EXP_REGION29_LUT_OFFSET 16 24 CM_GAMCOR_RAMA_EXP_REGION29_NUM_SEGMENTS 28 30 regCM2_CM_GAMCOR_RAMA_REGION_30_31 0 0x1038 4 0 2 CM_GAMCOR_RAMA_EXP_REGION30_LUT_OFFSET 0 8 CM_GAMCOR_RAMA_EXP_REGION30_NUM_SEGMENTS 12 14 CM_GAMCOR_RAMA_EXP_REGION31_LUT_OFFSET 16 24 CM_GAMCOR_RAMA_EXP_REGION31_NUM_SEGMENTS 28 30 regCM2_CM_GAMCOR_RAMA_REGION_32_33 0 0x1039 4 0 2 CM_GAMCOR_RAMA_EXP_REGION32_LUT_OFFSET 0 8 CM_GAMCOR_RAMA_EXP_REGION32_NUM_SEGMENTS 12 14 CM_GAMCOR_RAMA_EXP_REGION33_LUT_OFFSET 16 24 CM_GAMCOR_RAMA_EXP_REGION33_NUM_SEGMENTS 28 30 regCM2_CM_GAMCOR_RAMB_START_CNTL_B 0 0x103a 2 0 2 CM_GAMCOR_RAMB_EXP_REGION_START_B 0 17 CM_GAMCOR_RAMB_EXP_REGION_START_SEGMENT_B 20 26 regCM2_CM_GAMCOR_RAMB_START_CNTL_G 0 0x103b 2 0 2 CM_GAMCOR_RAMB_EXP_REGION_START_G 0 17 CM_GAMCOR_RAMB_EXP_REGION_START_SEGMENT_G 20 26 regCM2_CM_GAMCOR_RAMB_START_CNTL_R 0 0x103c 2 0 2 CM_GAMCOR_RAMB_EXP_REGION_START_R 0 17 CM_GAMCOR_RAMB_EXP_REGION_START_SEGMENT_R 20 26 regCM2_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B 0 0x103d 1 0 2 CM_GAMCOR_RAMB_EXP_REGION_START_SLOPE_B 0 17 regCM2_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G 0 0x103e 1 0 2 CM_GAMCOR_RAMB_EXP_REGION_START_SLOPE_G 0 17 regCM2_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R 0 0x103f 1 0 2 CM_GAMCOR_RAMB_EXP_REGION_START_SLOPE_R 0 17 regCM2_CM_GAMCOR_RAMB_START_BASE_CNTL_B 0 0x1040 1 0 2 CM_GAMCOR_RAMB_EXP_REGION_START_BASE_B 0 17 regCM2_CM_GAMCOR_RAMB_START_BASE_CNTL_G 0 0x1041 1 0 2 CM_GAMCOR_RAMB_EXP_REGION_START_BASE_G 0 17 regCM2_CM_GAMCOR_RAMB_START_BASE_CNTL_R 0 0x1042 1 0 2 CM_GAMCOR_RAMB_EXP_REGION_START_BASE_R 0 17 regCM2_CM_GAMCOR_RAMB_END_CNTL1_B 0 0x1043 1 0 2 CM_GAMCOR_RAMB_EXP_REGION_END_BASE_B 0 17 regCM2_CM_GAMCOR_RAMB_END_CNTL2_B 0 0x1044 2 0 2 CM_GAMCOR_RAMB_EXP_REGION_END_B 0 15 CM_GAMCOR_RAMB_EXP_REGION_END_SLOPE_B 16 31 regCM2_CM_GAMCOR_RAMB_END_CNTL1_G 0 0x1045 1 0 2 CM_GAMCOR_RAMB_EXP_REGION_END_BASE_G 0 17 regCM2_CM_GAMCOR_RAMB_END_CNTL2_G 0 0x1046 2 0 2 CM_GAMCOR_RAMB_EXP_REGION_END_G 0 15 CM_GAMCOR_RAMB_EXP_REGION_END_SLOPE_G 16 31 regCM2_CM_GAMCOR_RAMB_END_CNTL1_R 0 0x1047 1 0 2 CM_GAMCOR_RAMB_EXP_REGION_END_BASE_R 0 17 regCM2_CM_GAMCOR_RAMB_END_CNTL2_R 0 0x1048 2 0 2 CM_GAMCOR_RAMB_EXP_REGION_END_R 0 15 CM_GAMCOR_RAMB_EXP_REGION_END_SLOPE_R 16 31 regCM2_CM_GAMCOR_RAMB_OFFSET_B 0 0x1049 1 0 2 CM_GAMCOR_RAMB_OFFSET_B 0 18 regCM2_CM_GAMCOR_RAMB_OFFSET_G 0 0x104a 1 0 2 CM_GAMCOR_RAMB_OFFSET_G 0 18 regCM2_CM_GAMCOR_RAMB_OFFSET_R 0 0x104b 1 0 2 CM_GAMCOR_RAMB_OFFSET_R 0 18 regCM2_CM_GAMCOR_RAMB_REGION_0_1 0 0x104c 4 0 2 CM_GAMCOR_RAMB_EXP_REGION0_LUT_OFFSET 0 8 CM_GAMCOR_RAMB_EXP_REGION0_NUM_SEGMENTS 12 14 CM_GAMCOR_RAMB_EXP_REGION1_LUT_OFFSET 16 24 CM_GAMCOR_RAMB_EXP_REGION1_NUM_SEGMENTS 28 30 regCM2_CM_GAMCOR_RAMB_REGION_2_3 0 0x104d 4 0 2 CM_GAMCOR_RAMB_EXP_REGION2_LUT_OFFSET 0 8 CM_GAMCOR_RAMB_EXP_REGION2_NUM_SEGMENTS 12 14 CM_GAMCOR_RAMB_EXP_REGION3_LUT_OFFSET 16 24 CM_GAMCOR_RAMB_EXP_REGION3_NUM_SEGMENTS 28 30 regCM2_CM_GAMCOR_RAMB_REGION_4_5 0 0x104e 4 0 2 CM_GAMCOR_RAMB_EXP_REGION4_LUT_OFFSET 0 8 CM_GAMCOR_RAMB_EXP_REGION4_NUM_SEGMENTS 12 14 CM_GAMCOR_RAMB_EXP_REGION5_LUT_OFFSET 16 24 CM_GAMCOR_RAMB_EXP_REGION5_NUM_SEGMENTS 28 30 regCM2_CM_GAMCOR_RAMB_REGION_6_7 0 0x104f 4 0 2 CM_GAMCOR_RAMB_EXP_REGION6_LUT_OFFSET 0 8 CM_GAMCOR_RAMB_EXP_REGION6_NUM_SEGMENTS 12 14 CM_GAMCOR_RAMB_EXP_REGION7_LUT_OFFSET 16 24 CM_GAMCOR_RAMB_EXP_REGION7_NUM_SEGMENTS 28 30 regCM2_CM_GAMCOR_RAMB_REGION_8_9 0 0x1050 4 0 2 CM_GAMCOR_RAMB_EXP_REGION8_LUT_OFFSET 0 8 CM_GAMCOR_RAMB_EXP_REGION8_NUM_SEGMENTS 12 14 CM_GAMCOR_RAMB_EXP_REGION9_LUT_OFFSET 16 24 CM_GAMCOR_RAMB_EXP_REGION9_NUM_SEGMENTS 28 30 regCM2_CM_GAMCOR_RAMB_REGION_10_11 0 0x1051 4 0 2 CM_GAMCOR_RAMB_EXP_REGION10_LUT_OFFSET 0 8 CM_GAMCOR_RAMB_EXP_REGION10_NUM_SEGMENTS 12 14 CM_GAMCOR_RAMB_EXP_REGION11_LUT_OFFSET 16 24 CM_GAMCOR_RAMB_EXP_REGION11_NUM_SEGMENTS 28 30 regCM2_CM_GAMCOR_RAMB_REGION_12_13 0 0x1052 4 0 2 CM_GAMCOR_RAMB_EXP_REGION12_LUT_OFFSET 0 8 CM_GAMCOR_RAMB_EXP_REGION12_NUM_SEGMENTS 12 14 CM_GAMCOR_RAMB_EXP_REGION13_LUT_OFFSET 16 24 CM_GAMCOR_RAMB_EXP_REGION13_NUM_SEGMENTS 28 30 regCM2_CM_GAMCOR_RAMB_REGION_14_15 0 0x1053 4 0 2 CM_GAMCOR_RAMB_EXP_REGION14_LUT_OFFSET 0 8 CM_GAMCOR_RAMB_EXP_REGION14_NUM_SEGMENTS 12 14 CM_GAMCOR_RAMB_EXP_REGION15_LUT_OFFSET 16 24 CM_GAMCOR_RAMB_EXP_REGION15_NUM_SEGMENTS 28 30 regCM2_CM_GAMCOR_RAMB_REGION_16_17 0 0x1054 4 0 2 CM_GAMCOR_RAMB_EXP_REGION16_LUT_OFFSET 0 8 CM_GAMCOR_RAMB_EXP_REGION16_NUM_SEGMENTS 12 14 CM_GAMCOR_RAMB_EXP_REGION17_LUT_OFFSET 16 24 CM_GAMCOR_RAMB_EXP_REGION17_NUM_SEGMENTS 28 30 regCM2_CM_GAMCOR_RAMB_REGION_18_19 0 0x1055 4 0 2 CM_GAMCOR_RAMB_EXP_REGION18_LUT_OFFSET 0 8 CM_GAMCOR_RAMB_EXP_REGION18_NUM_SEGMENTS 12 14 CM_GAMCOR_RAMB_EXP_REGION19_LUT_OFFSET 16 24 CM_GAMCOR_RAMB_EXP_REGION19_NUM_SEGMENTS 28 30 regCM2_CM_GAMCOR_RAMB_REGION_20_21 0 0x1056 4 0 2 CM_GAMCOR_RAMB_EXP_REGION20_LUT_OFFSET 0 8 CM_GAMCOR_RAMB_EXP_REGION20_NUM_SEGMENTS 12 14 CM_GAMCOR_RAMB_EXP_REGION21_LUT_OFFSET 16 24 CM_GAMCOR_RAMB_EXP_REGION21_NUM_SEGMENTS 28 30 regCM2_CM_GAMCOR_RAMB_REGION_22_23 0 0x1057 4 0 2 CM_GAMCOR_RAMB_EXP_REGION22_LUT_OFFSET 0 8 CM_GAMCOR_RAMB_EXP_REGION22_NUM_SEGMENTS 12 14 CM_GAMCOR_RAMB_EXP_REGION23_LUT_OFFSET 16 24 CM_GAMCOR_RAMB_EXP_REGION23_NUM_SEGMENTS 28 30 regCM2_CM_GAMCOR_RAMB_REGION_24_25 0 0x1058 4 0 2 CM_GAMCOR_RAMB_EXP_REGION24_LUT_OFFSET 0 8 CM_GAMCOR_RAMB_EXP_REGION24_NUM_SEGMENTS 12 14 CM_GAMCOR_RAMB_EXP_REGION25_LUT_OFFSET 16 24 CM_GAMCOR_RAMB_EXP_REGION25_NUM_SEGMENTS 28 30 regCM2_CM_GAMCOR_RAMB_REGION_26_27 0 0x1059 4 0 2 CM_GAMCOR_RAMB_EXP_REGION26_LUT_OFFSET 0 8 CM_GAMCOR_RAMB_EXP_REGION26_NUM_SEGMENTS 12 14 CM_GAMCOR_RAMB_EXP_REGION27_LUT_OFFSET 16 24 CM_GAMCOR_RAMB_EXP_REGION27_NUM_SEGMENTS 28 30 regCM2_CM_GAMCOR_RAMB_REGION_28_29 0 0x105a 4 0 2 CM_GAMCOR_RAMB_EXP_REGION28_LUT_OFFSET 0 8 CM_GAMCOR_RAMB_EXP_REGION28_NUM_SEGMENTS 12 14 CM_GAMCOR_RAMB_EXP_REGION29_LUT_OFFSET 16 24 CM_GAMCOR_RAMB_EXP_REGION29_NUM_SEGMENTS 28 30 regCM2_CM_GAMCOR_RAMB_REGION_30_31 0 0x105b 4 0 2 CM_GAMCOR_RAMB_EXP_REGION30_LUT_OFFSET 0 8 CM_GAMCOR_RAMB_EXP_REGION30_NUM_SEGMENTS 12 14 CM_GAMCOR_RAMB_EXP_REGION31_LUT_OFFSET 16 24 CM_GAMCOR_RAMB_EXP_REGION31_NUM_SEGMENTS 28 30 regCM2_CM_GAMCOR_RAMB_REGION_32_33 0 0x105c 4 0 2 CM_GAMCOR_RAMB_EXP_REGION32_LUT_OFFSET 0 8 CM_GAMCOR_RAMB_EXP_REGION32_NUM_SEGMENTS 12 14 CM_GAMCOR_RAMB_EXP_REGION33_LUT_OFFSET 16 24 CM_GAMCOR_RAMB_EXP_REGION33_NUM_SEGMENTS 28 30 regCM2_CM_BLNDGAM_CONTROL 0 0x105d 5 0 2 CM_BLNDGAM_MODE 0 1 CM_BLNDGAM_SELECT 2 2 CM_BLNDGAM_PWL_DISABLE 3 3 CM_BLNDGAM_MODE_CURRENT 4 5 CM_BLNDGAM_SELECT_CURRENT 6 6 regCM2_CM_BLNDGAM_LUT_INDEX 0 0x105e 1 0 2 CM_BLNDGAM_LUT_INDEX 0 8 regCM2_CM_BLNDGAM_LUT_DATA 0 0x105f 1 0 2 CM_BLNDGAM_LUT_DATA 0 17 regCM2_CM_BLNDGAM_LUT_CONTROL 0 0x1060 5 0 2 CM_BLNDGAM_LUT_WRITE_COLOR_MASK 0 2 CM_BLNDGAM_LUT_READ_COLOR_SEL 3 4 CM_BLNDGAM_LUT_READ_DBG 5 5 CM_BLNDGAM_LUT_HOST_SEL 6 6 CM_BLNDGAM_LUT_CONFIG_MODE 7 7 regCM2_CM_BLNDGAM_RAMA_START_CNTL_B 0 0x1061 2 0 2 CM_BLNDGAM_RAMA_EXP_REGION_START_B 0 17 CM_BLNDGAM_RAMA_EXP_REGION_START_SEGMENT_B 20 26 regCM2_CM_BLNDGAM_RAMA_START_CNTL_G 0 0x1062 2 0 2 CM_BLNDGAM_RAMA_EXP_REGION_START_G 0 17 CM_BLNDGAM_RAMA_EXP_REGION_START_SEGMENT_G 20 26 regCM2_CM_BLNDGAM_RAMA_START_CNTL_R 0 0x1063 2 0 2 CM_BLNDGAM_RAMA_EXP_REGION_START_R 0 17 CM_BLNDGAM_RAMA_EXP_REGION_START_SEGMENT_R 20 26 regCM2_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_B 0 0x1064 1 0 2 CM_BLNDGAM_RAMA_EXP_REGION_START_SLOPE_B 0 17 regCM2_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_G 0 0x1065 1 0 2 CM_BLNDGAM_RAMA_EXP_REGION_START_SLOPE_G 0 17 regCM2_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_R 0 0x1066 1 0 2 CM_BLNDGAM_RAMA_EXP_REGION_START_SLOPE_R 0 17 regCM2_CM_BLNDGAM_RAMA_START_BASE_CNTL_B 0 0x1067 1 0 2 CM_BLNDGAM_RAMA_EXP_REGION_START_BASE_B 0 17 regCM2_CM_BLNDGAM_RAMA_START_BASE_CNTL_G 0 0x1068 1 0 2 CM_BLNDGAM_RAMA_EXP_REGION_START_BASE_G 0 17 regCM2_CM_BLNDGAM_RAMA_START_BASE_CNTL_R 0 0x1069 1 0 2 CM_BLNDGAM_RAMA_EXP_REGION_START_BASE_R 0 17 regCM2_CM_BLNDGAM_RAMA_END_CNTL1_B 0 0x106a 1 0 2 CM_BLNDGAM_RAMA_EXP_REGION_END_BASE_B 0 17 regCM2_CM_BLNDGAM_RAMA_END_CNTL2_B 0 0x106b 2 0 2 CM_BLNDGAM_RAMA_EXP_REGION_END_B 0 15 CM_BLNDGAM_RAMA_EXP_REGION_END_SLOPE_B 16 31 regCM2_CM_BLNDGAM_RAMA_END_CNTL1_G 0 0x106c 1 0 2 CM_BLNDGAM_RAMA_EXP_REGION_END_BASE_G 0 17 regCM2_CM_BLNDGAM_RAMA_END_CNTL2_G 0 0x106d 2 0 2 CM_BLNDGAM_RAMA_EXP_REGION_END_G 0 15 CM_BLNDGAM_RAMA_EXP_REGION_END_SLOPE_G 16 31 regCM2_CM_BLNDGAM_RAMA_END_CNTL1_R 0 0x106e 1 0 2 CM_BLNDGAM_RAMA_EXP_REGION_END_BASE_R 0 17 regCM2_CM_BLNDGAM_RAMA_END_CNTL2_R 0 0x106f 2 0 2 CM_BLNDGAM_RAMA_EXP_REGION_END_R 0 15 CM_BLNDGAM_RAMA_EXP_REGION_END_SLOPE_R 16 31 regCM2_CM_BLNDGAM_RAMA_OFFSET_B 0 0x1070 1 0 2 CM_BLNDGAM_RAMA_OFFSET_B 0 18 regCM2_CM_BLNDGAM_RAMA_OFFSET_G 0 0x1071 1 0 2 CM_BLNDGAM_RAMA_OFFSET_G 0 18 regCM2_CM_BLNDGAM_RAMA_OFFSET_R 0 0x1072 1 0 2 CM_BLNDGAM_RAMA_OFFSET_R 0 18 regCM2_CM_BLNDGAM_RAMA_REGION_0_1 0 0x1073 4 0 2 CM_BLNDGAM_RAMA_EXP_REGION0_LUT_OFFSET 0 8 CM_BLNDGAM_RAMA_EXP_REGION0_NUM_SEGMENTS 12 14 CM_BLNDGAM_RAMA_EXP_REGION1_LUT_OFFSET 16 24 CM_BLNDGAM_RAMA_EXP_REGION1_NUM_SEGMENTS 28 30 regCM2_CM_BLNDGAM_RAMA_REGION_2_3 0 0x1074 4 0 2 CM_BLNDGAM_RAMA_EXP_REGION2_LUT_OFFSET 0 8 CM_BLNDGAM_RAMA_EXP_REGION2_NUM_SEGMENTS 12 14 CM_BLNDGAM_RAMA_EXP_REGION3_LUT_OFFSET 16 24 CM_BLNDGAM_RAMA_EXP_REGION3_NUM_SEGMENTS 28 30 regCM2_CM_BLNDGAM_RAMA_REGION_4_5 0 0x1075 4 0 2 CM_BLNDGAM_RAMA_EXP_REGION4_LUT_OFFSET 0 8 CM_BLNDGAM_RAMA_EXP_REGION4_NUM_SEGMENTS 12 14 CM_BLNDGAM_RAMA_EXP_REGION5_LUT_OFFSET 16 24 CM_BLNDGAM_RAMA_EXP_REGION5_NUM_SEGMENTS 28 30 regCM2_CM_BLNDGAM_RAMA_REGION_6_7 0 0x1076 4 0 2 CM_BLNDGAM_RAMA_EXP_REGION6_LUT_OFFSET 0 8 CM_BLNDGAM_RAMA_EXP_REGION6_NUM_SEGMENTS 12 14 CM_BLNDGAM_RAMA_EXP_REGION7_LUT_OFFSET 16 24 CM_BLNDGAM_RAMA_EXP_REGION7_NUM_SEGMENTS 28 30 regCM2_CM_BLNDGAM_RAMA_REGION_8_9 0 0x1077 4 0 2 CM_BLNDGAM_RAMA_EXP_REGION8_LUT_OFFSET 0 8 CM_BLNDGAM_RAMA_EXP_REGION8_NUM_SEGMENTS 12 14 CM_BLNDGAM_RAMA_EXP_REGION9_LUT_OFFSET 16 24 CM_BLNDGAM_RAMA_EXP_REGION9_NUM_SEGMENTS 28 30 regCM2_CM_BLNDGAM_RAMA_REGION_10_11 0 0x1078 4 0 2 CM_BLNDGAM_RAMA_EXP_REGION10_LUT_OFFSET 0 8 CM_BLNDGAM_RAMA_EXP_REGION10_NUM_SEGMENTS 12 14 CM_BLNDGAM_RAMA_EXP_REGION11_LUT_OFFSET 16 24 CM_BLNDGAM_RAMA_EXP_REGION11_NUM_SEGMENTS 28 30 regCM2_CM_BLNDGAM_RAMA_REGION_12_13 0 0x1079 4 0 2 CM_BLNDGAM_RAMA_EXP_REGION12_LUT_OFFSET 0 8 CM_BLNDGAM_RAMA_EXP_REGION12_NUM_SEGMENTS 12 14 CM_BLNDGAM_RAMA_EXP_REGION13_LUT_OFFSET 16 24 CM_BLNDGAM_RAMA_EXP_REGION13_NUM_SEGMENTS 28 30 regCM2_CM_BLNDGAM_RAMA_REGION_14_15 0 0x107a 4 0 2 CM_BLNDGAM_RAMA_EXP_REGION14_LUT_OFFSET 0 8 CM_BLNDGAM_RAMA_EXP_REGION14_NUM_SEGMENTS 12 14 CM_BLNDGAM_RAMA_EXP_REGION15_LUT_OFFSET 16 24 CM_BLNDGAM_RAMA_EXP_REGION15_NUM_SEGMENTS 28 30 regCM2_CM_BLNDGAM_RAMA_REGION_16_17 0 0x107b 4 0 2 CM_BLNDGAM_RAMA_EXP_REGION16_LUT_OFFSET 0 8 CM_BLNDGAM_RAMA_EXP_REGION16_NUM_SEGMENTS 12 14 CM_BLNDGAM_RAMA_EXP_REGION17_LUT_OFFSET 16 24 CM_BLNDGAM_RAMA_EXP_REGION17_NUM_SEGMENTS 28 30 regCM2_CM_BLNDGAM_RAMA_REGION_18_19 0 0x107c 4 0 2 CM_BLNDGAM_RAMA_EXP_REGION18_LUT_OFFSET 0 8 CM_BLNDGAM_RAMA_EXP_REGION18_NUM_SEGMENTS 12 14 CM_BLNDGAM_RAMA_EXP_REGION19_LUT_OFFSET 16 24 CM_BLNDGAM_RAMA_EXP_REGION19_NUM_SEGMENTS 28 30 regCM2_CM_BLNDGAM_RAMA_REGION_20_21 0 0x107d 4 0 2 CM_BLNDGAM_RAMA_EXP_REGION20_LUT_OFFSET 0 8 CM_BLNDGAM_RAMA_EXP_REGION20_NUM_SEGMENTS 12 14 CM_BLNDGAM_RAMA_EXP_REGION21_LUT_OFFSET 16 24 CM_BLNDGAM_RAMA_EXP_REGION21_NUM_SEGMENTS 28 30 regCM2_CM_BLNDGAM_RAMA_REGION_22_23 0 0x107e 4 0 2 CM_BLNDGAM_RAMA_EXP_REGION22_LUT_OFFSET 0 8 CM_BLNDGAM_RAMA_EXP_REGION22_NUM_SEGMENTS 12 14 CM_BLNDGAM_RAMA_EXP_REGION23_LUT_OFFSET 16 24 CM_BLNDGAM_RAMA_EXP_REGION23_NUM_SEGMENTS 28 30 regCM2_CM_BLNDGAM_RAMA_REGION_24_25 0 0x107f 4 0 2 CM_BLNDGAM_RAMA_EXP_REGION24_LUT_OFFSET 0 8 CM_BLNDGAM_RAMA_EXP_REGION24_NUM_SEGMENTS 12 14 CM_BLNDGAM_RAMA_EXP_REGION25_LUT_OFFSET 16 24 CM_BLNDGAM_RAMA_EXP_REGION25_NUM_SEGMENTS 28 30 regCM2_CM_BLNDGAM_RAMA_REGION_26_27 0 0x1080 4 0 2 CM_BLNDGAM_RAMA_EXP_REGION26_LUT_OFFSET 0 8 CM_BLNDGAM_RAMA_EXP_REGION26_NUM_SEGMENTS 12 14 CM_BLNDGAM_RAMA_EXP_REGION27_LUT_OFFSET 16 24 CM_BLNDGAM_RAMA_EXP_REGION27_NUM_SEGMENTS 28 30 regCM2_CM_BLNDGAM_RAMA_REGION_28_29 0 0x1081 4 0 2 CM_BLNDGAM_RAMA_EXP_REGION28_LUT_OFFSET 0 8 CM_BLNDGAM_RAMA_EXP_REGION28_NUM_SEGMENTS 12 14 CM_BLNDGAM_RAMA_EXP_REGION29_LUT_OFFSET 16 24 CM_BLNDGAM_RAMA_EXP_REGION29_NUM_SEGMENTS 28 30 regCM2_CM_BLNDGAM_RAMA_REGION_30_31 0 0x1082 4 0 2 CM_BLNDGAM_RAMA_EXP_REGION30_LUT_OFFSET 0 8 CM_BLNDGAM_RAMA_EXP_REGION30_NUM_SEGMENTS 12 14 CM_BLNDGAM_RAMA_EXP_REGION31_LUT_OFFSET 16 24 CM_BLNDGAM_RAMA_EXP_REGION31_NUM_SEGMENTS 28 30 regCM2_CM_BLNDGAM_RAMA_REGION_32_33 0 0x1083 4 0 2 CM_BLNDGAM_RAMA_EXP_REGION32_LUT_OFFSET 0 8 CM_BLNDGAM_RAMA_EXP_REGION32_NUM_SEGMENTS 12 14 CM_BLNDGAM_RAMA_EXP_REGION33_LUT_OFFSET 16 24 CM_BLNDGAM_RAMA_EXP_REGION33_NUM_SEGMENTS 28 30 regCM2_CM_BLNDGAM_RAMB_START_CNTL_B 0 0x1084 2 0 2 CM_BLNDGAM_RAMB_EXP_REGION_START_B 0 17 CM_BLNDGAM_RAMB_EXP_REGION_START_SEGMENT_B 20 26 regCM2_CM_BLNDGAM_RAMB_START_CNTL_G 0 0x1085 2 0 2 CM_BLNDGAM_RAMB_EXP_REGION_START_G 0 17 CM_BLNDGAM_RAMB_EXP_REGION_START_SEGMENT_G 20 26 regCM2_CM_BLNDGAM_RAMB_START_CNTL_R 0 0x1086 2 0 2 CM_BLNDGAM_RAMB_EXP_REGION_START_R 0 17 CM_BLNDGAM_RAMB_EXP_REGION_START_SEGMENT_R 20 26 regCM2_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_B 0 0x1087 1 0 2 CM_BLNDGAM_RAMB_EXP_REGION_START_SLOPE_B 0 17 regCM2_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_G 0 0x1088 1 0 2 CM_BLNDGAM_RAMB_EXP_REGION_START_SLOPE_G 0 17 regCM2_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_R 0 0x1089 1 0 2 CM_BLNDGAM_RAMB_EXP_REGION_START_SLOPE_R 0 17 regCM2_CM_BLNDGAM_RAMB_START_BASE_CNTL_B 0 0x108a 1 0 2 CM_BLNDGAM_RAMB_EXP_REGION_START_BASE_B 0 17 regCM2_CM_BLNDGAM_RAMB_START_BASE_CNTL_G 0 0x108b 1 0 2 CM_BLNDGAM_RAMB_EXP_REGION_START_BASE_G 0 17 regCM2_CM_BLNDGAM_RAMB_START_BASE_CNTL_R 0 0x108c 1 0 2 CM_BLNDGAM_RAMB_EXP_REGION_START_BASE_R 0 17 regCM2_CM_BLNDGAM_RAMB_END_CNTL1_B 0 0x108d 1 0 2 CM_BLNDGAM_RAMB_EXP_REGION_END_BASE_B 0 17 regCM2_CM_BLNDGAM_RAMB_END_CNTL2_B 0 0x108e 2 0 2 CM_BLNDGAM_RAMB_EXP_REGION_END_B 0 15 CM_BLNDGAM_RAMB_EXP_REGION_END_SLOPE_B 16 31 regCM2_CM_BLNDGAM_RAMB_END_CNTL1_G 0 0x108f 1 0 2 CM_BLNDGAM_RAMB_EXP_REGION_END_BASE_G 0 17 regCM2_CM_BLNDGAM_RAMB_END_CNTL2_G 0 0x1090 2 0 2 CM_BLNDGAM_RAMB_EXP_REGION_END_G 0 15 CM_BLNDGAM_RAMB_EXP_REGION_END_SLOPE_G 16 31 regCM2_CM_BLNDGAM_RAMB_END_CNTL1_R 0 0x1091 1 0 2 CM_BLNDGAM_RAMB_EXP_REGION_END_BASE_R 0 17 regCM2_CM_BLNDGAM_RAMB_END_CNTL2_R 0 0x1092 2 0 2 CM_BLNDGAM_RAMB_EXP_REGION_END_R 0 15 CM_BLNDGAM_RAMB_EXP_REGION_END_SLOPE_R 16 31 regCM2_CM_BLNDGAM_RAMB_OFFSET_B 0 0x1093 1 0 2 CM_BLNDGAM_RAMB_OFFSET_B 0 18 regCM2_CM_BLNDGAM_RAMB_OFFSET_G 0 0x1094 1 0 2 CM_BLNDGAM_RAMB_OFFSET_G 0 18 regCM2_CM_BLNDGAM_RAMB_OFFSET_R 0 0x1095 1 0 2 CM_BLNDGAM_RAMB_OFFSET_R 0 18 regCM2_CM_BLNDGAM_RAMB_REGION_0_1 0 0x1096 4 0 2 CM_BLNDGAM_RAMB_EXP_REGION0_LUT_OFFSET 0 8 CM_BLNDGAM_RAMB_EXP_REGION0_NUM_SEGMENTS 12 14 CM_BLNDGAM_RAMB_EXP_REGION1_LUT_OFFSET 16 24 CM_BLNDGAM_RAMB_EXP_REGION1_NUM_SEGMENTS 28 30 regCM2_CM_BLNDGAM_RAMB_REGION_2_3 0 0x1097 4 0 2 CM_BLNDGAM_RAMB_EXP_REGION2_LUT_OFFSET 0 8 CM_BLNDGAM_RAMB_EXP_REGION2_NUM_SEGMENTS 12 14 CM_BLNDGAM_RAMB_EXP_REGION3_LUT_OFFSET 16 24 CM_BLNDGAM_RAMB_EXP_REGION3_NUM_SEGMENTS 28 30 regCM2_CM_BLNDGAM_RAMB_REGION_4_5 0 0x1098 4 0 2 CM_BLNDGAM_RAMB_EXP_REGION4_LUT_OFFSET 0 8 CM_BLNDGAM_RAMB_EXP_REGION4_NUM_SEGMENTS 12 14 CM_BLNDGAM_RAMB_EXP_REGION5_LUT_OFFSET 16 24 CM_BLNDGAM_RAMB_EXP_REGION5_NUM_SEGMENTS 28 30 regCM2_CM_BLNDGAM_RAMB_REGION_6_7 0 0x1099 4 0 2 CM_BLNDGAM_RAMB_EXP_REGION6_LUT_OFFSET 0 8 CM_BLNDGAM_RAMB_EXP_REGION6_NUM_SEGMENTS 12 14 CM_BLNDGAM_RAMB_EXP_REGION7_LUT_OFFSET 16 24 CM_BLNDGAM_RAMB_EXP_REGION7_NUM_SEGMENTS 28 30 regCM2_CM_BLNDGAM_RAMB_REGION_8_9 0 0x109a 4 0 2 CM_BLNDGAM_RAMB_EXP_REGION8_LUT_OFFSET 0 8 CM_BLNDGAM_RAMB_EXP_REGION8_NUM_SEGMENTS 12 14 CM_BLNDGAM_RAMB_EXP_REGION9_LUT_OFFSET 16 24 CM_BLNDGAM_RAMB_EXP_REGION9_NUM_SEGMENTS 28 30 regCM2_CM_BLNDGAM_RAMB_REGION_10_11 0 0x109b 4 0 2 CM_BLNDGAM_RAMB_EXP_REGION10_LUT_OFFSET 0 8 CM_BLNDGAM_RAMB_EXP_REGION10_NUM_SEGMENTS 12 14 CM_BLNDGAM_RAMB_EXP_REGION11_LUT_OFFSET 16 24 CM_BLNDGAM_RAMB_EXP_REGION11_NUM_SEGMENTS 28 30 regCM2_CM_BLNDGAM_RAMB_REGION_12_13 0 0x109c 4 0 2 CM_BLNDGAM_RAMB_EXP_REGION12_LUT_OFFSET 0 8 CM_BLNDGAM_RAMB_EXP_REGION12_NUM_SEGMENTS 12 14 CM_BLNDGAM_RAMB_EXP_REGION13_LUT_OFFSET 16 24 CM_BLNDGAM_RAMB_EXP_REGION13_NUM_SEGMENTS 28 30 regCM2_CM_BLNDGAM_RAMB_REGION_14_15 0 0x109d 4 0 2 CM_BLNDGAM_RAMB_EXP_REGION14_LUT_OFFSET 0 8 CM_BLNDGAM_RAMB_EXP_REGION14_NUM_SEGMENTS 12 14 CM_BLNDGAM_RAMB_EXP_REGION15_LUT_OFFSET 16 24 CM_BLNDGAM_RAMB_EXP_REGION15_NUM_SEGMENTS 28 30 regCM2_CM_BLNDGAM_RAMB_REGION_16_17 0 0x109e 4 0 2 CM_BLNDGAM_RAMB_EXP_REGION16_LUT_OFFSET 0 8 CM_BLNDGAM_RAMB_EXP_REGION16_NUM_SEGMENTS 12 14 CM_BLNDGAM_RAMB_EXP_REGION17_LUT_OFFSET 16 24 CM_BLNDGAM_RAMB_EXP_REGION17_NUM_SEGMENTS 28 30 regCM2_CM_BLNDGAM_RAMB_REGION_18_19 0 0x109f 4 0 2 CM_BLNDGAM_RAMB_EXP_REGION18_LUT_OFFSET 0 8 CM_BLNDGAM_RAMB_EXP_REGION18_NUM_SEGMENTS 12 14 CM_BLNDGAM_RAMB_EXP_REGION19_LUT_OFFSET 16 24 CM_BLNDGAM_RAMB_EXP_REGION19_NUM_SEGMENTS 28 30 regCM2_CM_BLNDGAM_RAMB_REGION_20_21 0 0x10a0 4 0 2 CM_BLNDGAM_RAMB_EXP_REGION20_LUT_OFFSET 0 8 CM_BLNDGAM_RAMB_EXP_REGION20_NUM_SEGMENTS 12 14 CM_BLNDGAM_RAMB_EXP_REGION21_LUT_OFFSET 16 24 CM_BLNDGAM_RAMB_EXP_REGION21_NUM_SEGMENTS 28 30 regCM2_CM_BLNDGAM_RAMB_REGION_22_23 0 0x10a1 4 0 2 CM_BLNDGAM_RAMB_EXP_REGION22_LUT_OFFSET 0 8 CM_BLNDGAM_RAMB_EXP_REGION22_NUM_SEGMENTS 12 14 CM_BLNDGAM_RAMB_EXP_REGION23_LUT_OFFSET 16 24 CM_BLNDGAM_RAMB_EXP_REGION23_NUM_SEGMENTS 28 30 regCM2_CM_BLNDGAM_RAMB_REGION_24_25 0 0x10a2 4 0 2 CM_BLNDGAM_RAMB_EXP_REGION24_LUT_OFFSET 0 8 CM_BLNDGAM_RAMB_EXP_REGION24_NUM_SEGMENTS 12 14 CM_BLNDGAM_RAMB_EXP_REGION25_LUT_OFFSET 16 24 CM_BLNDGAM_RAMB_EXP_REGION25_NUM_SEGMENTS 28 30 regCM2_CM_BLNDGAM_RAMB_REGION_26_27 0 0x10a3 4 0 2 CM_BLNDGAM_RAMB_EXP_REGION26_LUT_OFFSET 0 8 CM_BLNDGAM_RAMB_EXP_REGION26_NUM_SEGMENTS 12 14 CM_BLNDGAM_RAMB_EXP_REGION27_LUT_OFFSET 16 24 CM_BLNDGAM_RAMB_EXP_REGION27_NUM_SEGMENTS 28 30 regCM2_CM_BLNDGAM_RAMB_REGION_28_29 0 0x10a4 4 0 2 CM_BLNDGAM_RAMB_EXP_REGION28_LUT_OFFSET 0 8 CM_BLNDGAM_RAMB_EXP_REGION28_NUM_SEGMENTS 12 14 CM_BLNDGAM_RAMB_EXP_REGION29_LUT_OFFSET 16 24 CM_BLNDGAM_RAMB_EXP_REGION29_NUM_SEGMENTS 28 30 regCM2_CM_BLNDGAM_RAMB_REGION_30_31 0 0x10a5 4 0 2 CM_BLNDGAM_RAMB_EXP_REGION30_LUT_OFFSET 0 8 CM_BLNDGAM_RAMB_EXP_REGION30_NUM_SEGMENTS 12 14 CM_BLNDGAM_RAMB_EXP_REGION31_LUT_OFFSET 16 24 CM_BLNDGAM_RAMB_EXP_REGION31_NUM_SEGMENTS 28 30 regCM2_CM_BLNDGAM_RAMB_REGION_32_33 0 0x10a6 4 0 2 CM_BLNDGAM_RAMB_EXP_REGION32_LUT_OFFSET 0 8 CM_BLNDGAM_RAMB_EXP_REGION32_NUM_SEGMENTS 12 14 CM_BLNDGAM_RAMB_EXP_REGION33_LUT_OFFSET 16 24 CM_BLNDGAM_RAMB_EXP_REGION33_NUM_SEGMENTS 28 30 regCM2_CM_HDR_MULT_COEF 0 0x10a7 1 0 2 CM_HDR_MULT_COEF 0 18 regCM2_CM_MEM_PWR_CTRL 0 0x10a8 4 0 2 GAMCOR_MEM_PWR_FORCE 0 1 GAMCOR_MEM_PWR_DIS 2 2 BLNDGAM_MEM_PWR_FORCE 4 5 BLNDGAM_MEM_PWR_DIS 6 6 regCM2_CM_MEM_PWR_STATUS 0 0x10a9 2 0 2 GAMCOR_MEM_PWR_STATE 0 1 BLNDGAM_MEM_PWR_STATE 2 3 regCM2_CM_DEALPHA 0 0x10ab 2 0 2 CM_DEALPHA_EN 0 0 CM_DEALPHA_ABLND 1 1 regCM2_CM_COEF_FORMAT 0 0x10ac 3 0 2 CM_BIAS_FORMAT 0 0 CM_POST_CSC_COEF_FORMAT 4 4 CM_GAMUT_REMAP_COEF_FORMAT 8 8 regCM2_CM_SHAPER_CONTROL 0 0x10ad 2 0 2 CM_SHAPER_LUT_MODE 0 1 CM_SHAPER_MODE_CURRENT 2 3 regCM2_CM_SHAPER_OFFSET_R 0 0x10ae 1 0 2 CM_SHAPER_OFFSET_R 0 18 regCM2_CM_SHAPER_OFFSET_G 0 0x10af 1 0 2 CM_SHAPER_OFFSET_G 0 18 regCM2_CM_SHAPER_OFFSET_B 0 0x10b0 1 0 2 CM_SHAPER_OFFSET_B 0 18 regCM2_CM_SHAPER_SCALE_R 0 0x10b1 1 0 2 CM_SHAPER_SCALE_R 0 15 regCM2_CM_SHAPER_SCALE_G_B 0 0x10b2 2 0 2 CM_SHAPER_SCALE_G 0 15 CM_SHAPER_SCALE_B 16 31 regCM2_CM_SHAPER_LUT_INDEX 0 0x10b3 1 0 2 CM_SHAPER_LUT_INDEX 0 7 regCM2_CM_SHAPER_LUT_DATA 0 0x10b4 1 0 2 CM_SHAPER_LUT_DATA 0 23 regCM2_CM_SHAPER_LUT_WRITE_EN_MASK 0 0x10b5 2 0 2 CM_SHAPER_LUT_WRITE_EN_MASK 0 2 CM_SHAPER_LUT_WRITE_SEL 4 4 regCM2_CM_SHAPER_RAMA_START_CNTL_B 0 0x10b6 2 0 2 CM_SHAPER_RAMA_EXP_REGION_START_B 0 17 CM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_B 20 26 regCM2_CM_SHAPER_RAMA_START_CNTL_G 0 0x10b7 2 0 2 CM_SHAPER_RAMA_EXP_REGION_START_G 0 17 CM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_G 20 26 regCM2_CM_SHAPER_RAMA_START_CNTL_R 0 0x10b8 2 0 2 CM_SHAPER_RAMA_EXP_REGION_START_R 0 17 CM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_R 20 26 regCM2_CM_SHAPER_RAMA_END_CNTL_B 0 0x10b9 2 0 2 CM_SHAPER_RAMA_EXP_REGION_END_B 0 15 CM_SHAPER_RAMA_EXP_REGION_END_BASE_B 16 29 regCM2_CM_SHAPER_RAMA_END_CNTL_G 0 0x10ba 2 0 2 CM_SHAPER_RAMA_EXP_REGION_END_G 0 15 CM_SHAPER_RAMA_EXP_REGION_END_BASE_G 16 29 regCM2_CM_SHAPER_RAMA_END_CNTL_R 0 0x10bb 2 0 2 CM_SHAPER_RAMA_EXP_REGION_END_R 0 15 CM_SHAPER_RAMA_EXP_REGION_END_BASE_R 16 29 regCM2_CM_SHAPER_RAMA_REGION_0_1 0 0x10bc 4 0 2 CM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET 0 8 CM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS 12 14 CM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET 16 24 CM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS 28 30 regCM2_CM_SHAPER_RAMA_REGION_2_3 0 0x10bd 4 0 2 CM_SHAPER_RAMA_EXP_REGION2_LUT_OFFSET 0 8 CM_SHAPER_RAMA_EXP_REGION2_NUM_SEGMENTS 12 14 CM_SHAPER_RAMA_EXP_REGION3_LUT_OFFSET 16 24 CM_SHAPER_RAMA_EXP_REGION3_NUM_SEGMENTS 28 30 regCM2_CM_SHAPER_RAMA_REGION_4_5 0 0x10be 4 0 2 CM_SHAPER_RAMA_EXP_REGION4_LUT_OFFSET 0 8 CM_SHAPER_RAMA_EXP_REGION4_NUM_SEGMENTS 12 14 CM_SHAPER_RAMA_EXP_REGION5_LUT_OFFSET 16 24 CM_SHAPER_RAMA_EXP_REGION5_NUM_SEGMENTS 28 30 regCM2_CM_SHAPER_RAMA_REGION_6_7 0 0x10bf 4 0 2 CM_SHAPER_RAMA_EXP_REGION6_LUT_OFFSET 0 8 CM_SHAPER_RAMA_EXP_REGION6_NUM_SEGMENTS 12 14 CM_SHAPER_RAMA_EXP_REGION7_LUT_OFFSET 16 24 CM_SHAPER_RAMA_EXP_REGION7_NUM_SEGMENTS 28 30 regCM2_CM_SHAPER_RAMA_REGION_8_9 0 0x10c0 4 0 2 CM_SHAPER_RAMA_EXP_REGION8_LUT_OFFSET 0 8 CM_SHAPER_RAMA_EXP_REGION8_NUM_SEGMENTS 12 14 CM_SHAPER_RAMA_EXP_REGION9_LUT_OFFSET 16 24 CM_SHAPER_RAMA_EXP_REGION9_NUM_SEGMENTS 28 30 regCM2_CM_SHAPER_RAMA_REGION_10_11 0 0x10c1 4 0 2 CM_SHAPER_RAMA_EXP_REGION10_LUT_OFFSET 0 8 CM_SHAPER_RAMA_EXP_REGION10_NUM_SEGMENTS 12 14 CM_SHAPER_RAMA_EXP_REGION11_LUT_OFFSET 16 24 CM_SHAPER_RAMA_EXP_REGION11_NUM_SEGMENTS 28 30 regCM2_CM_SHAPER_RAMA_REGION_12_13 0 0x10c2 4 0 2 CM_SHAPER_RAMA_EXP_REGION12_LUT_OFFSET 0 8 CM_SHAPER_RAMA_EXP_REGION12_NUM_SEGMENTS 12 14 CM_SHAPER_RAMA_EXP_REGION13_LUT_OFFSET 16 24 CM_SHAPER_RAMA_EXP_REGION13_NUM_SEGMENTS 28 30 regCM2_CM_SHAPER_RAMA_REGION_14_15 0 0x10c3 4 0 2 CM_SHAPER_RAMA_EXP_REGION14_LUT_OFFSET 0 8 CM_SHAPER_RAMA_EXP_REGION14_NUM_SEGMENTS 12 14 CM_SHAPER_RAMA_EXP_REGION15_LUT_OFFSET 16 24 CM_SHAPER_RAMA_EXP_REGION15_NUM_SEGMENTS 28 30 regCM2_CM_SHAPER_RAMA_REGION_16_17 0 0x10c4 4 0 2 CM_SHAPER_RAMA_EXP_REGION16_LUT_OFFSET 0 8 CM_SHAPER_RAMA_EXP_REGION16_NUM_SEGMENTS 12 14 CM_SHAPER_RAMA_EXP_REGION17_LUT_OFFSET 16 24 CM_SHAPER_RAMA_EXP_REGION17_NUM_SEGMENTS 28 30 regCM2_CM_SHAPER_RAMA_REGION_18_19 0 0x10c5 4 0 2 CM_SHAPER_RAMA_EXP_REGION18_LUT_OFFSET 0 8 CM_SHAPER_RAMA_EXP_REGION18_NUM_SEGMENTS 12 14 CM_SHAPER_RAMA_EXP_REGION19_LUT_OFFSET 16 24 CM_SHAPER_RAMA_EXP_REGION19_NUM_SEGMENTS 28 30 regCM2_CM_SHAPER_RAMA_REGION_20_21 0 0x10c6 4 0 2 CM_SHAPER_RAMA_EXP_REGION20_LUT_OFFSET 0 8 CM_SHAPER_RAMA_EXP_REGION20_NUM_SEGMENTS 12 14 CM_SHAPER_RAMA_EXP_REGION21_LUT_OFFSET 16 24 CM_SHAPER_RAMA_EXP_REGION21_NUM_SEGMENTS 28 30 regCM2_CM_SHAPER_RAMA_REGION_22_23 0 0x10c7 4 0 2 CM_SHAPER_RAMA_EXP_REGION22_LUT_OFFSET 0 8 CM_SHAPER_RAMA_EXP_REGION22_NUM_SEGMENTS 12 14 CM_SHAPER_RAMA_EXP_REGION23_LUT_OFFSET 16 24 CM_SHAPER_RAMA_EXP_REGION23_NUM_SEGMENTS 28 30 regCM2_CM_SHAPER_RAMA_REGION_24_25 0 0x10c8 4 0 2 CM_SHAPER_RAMA_EXP_REGION24_LUT_OFFSET 0 8 CM_SHAPER_RAMA_EXP_REGION24_NUM_SEGMENTS 12 14 CM_SHAPER_RAMA_EXP_REGION25_LUT_OFFSET 16 24 CM_SHAPER_RAMA_EXP_REGION25_NUM_SEGMENTS 28 30 regCM2_CM_SHAPER_RAMA_REGION_26_27 0 0x10c9 4 0 2 CM_SHAPER_RAMA_EXP_REGION26_LUT_OFFSET 0 8 CM_SHAPER_RAMA_EXP_REGION26_NUM_SEGMENTS 12 14 CM_SHAPER_RAMA_EXP_REGION27_LUT_OFFSET 16 24 CM_SHAPER_RAMA_EXP_REGION27_NUM_SEGMENTS 28 30 regCM2_CM_SHAPER_RAMA_REGION_28_29 0 0x10ca 4 0 2 CM_SHAPER_RAMA_EXP_REGION28_LUT_OFFSET 0 8 CM_SHAPER_RAMA_EXP_REGION28_NUM_SEGMENTS 12 14 CM_SHAPER_RAMA_EXP_REGION29_LUT_OFFSET 16 24 CM_SHAPER_RAMA_EXP_REGION29_NUM_SEGMENTS 28 30 regCM2_CM_SHAPER_RAMA_REGION_30_31 0 0x10cb 4 0 2 CM_SHAPER_RAMA_EXP_REGION30_LUT_OFFSET 0 8 CM_SHAPER_RAMA_EXP_REGION30_NUM_SEGMENTS 12 14 CM_SHAPER_RAMA_EXP_REGION31_LUT_OFFSET 16 24 CM_SHAPER_RAMA_EXP_REGION31_NUM_SEGMENTS 28 30 regCM2_CM_SHAPER_RAMA_REGION_32_33 0 0x10cc 4 0 2 CM_SHAPER_RAMA_EXP_REGION32_LUT_OFFSET 0 8 CM_SHAPER_RAMA_EXP_REGION32_NUM_SEGMENTS 12 14 CM_SHAPER_RAMA_EXP_REGION33_LUT_OFFSET 16 24 CM_SHAPER_RAMA_EXP_REGION33_NUM_SEGMENTS 28 30 regCM2_CM_SHAPER_RAMB_START_CNTL_B 0 0x10cd 2 0 2 CM_SHAPER_RAMB_EXP_REGION_START_B 0 17 CM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_B 20 26 regCM2_CM_SHAPER_RAMB_START_CNTL_G 0 0x10ce 2 0 2 CM_SHAPER_RAMB_EXP_REGION_START_G 0 17 CM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_G 20 26 regCM2_CM_SHAPER_RAMB_START_CNTL_R 0 0x10cf 2 0 2 CM_SHAPER_RAMB_EXP_REGION_START_R 0 17 CM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_R 20 26 regCM2_CM_SHAPER_RAMB_END_CNTL_B 0 0x10d0 2 0 2 CM_SHAPER_RAMB_EXP_REGION_END_B 0 15 CM_SHAPER_RAMB_EXP_REGION_END_BASE_B 16 29 regCM2_CM_SHAPER_RAMB_END_CNTL_G 0 0x10d1 2 0 2 CM_SHAPER_RAMB_EXP_REGION_END_G 0 15 CM_SHAPER_RAMB_EXP_REGION_END_BASE_G 16 29 regCM2_CM_SHAPER_RAMB_END_CNTL_R 0 0x10d2 2 0 2 CM_SHAPER_RAMB_EXP_REGION_END_R 0 15 CM_SHAPER_RAMB_EXP_REGION_END_BASE_R 16 29 regCM2_CM_SHAPER_RAMB_REGION_0_1 0 0x10d3 4 0 2 CM_SHAPER_RAMB_EXP_REGION0_LUT_OFFSET 0 8 CM_SHAPER_RAMB_EXP_REGION0_NUM_SEGMENTS 12 14 CM_SHAPER_RAMB_EXP_REGION1_LUT_OFFSET 16 24 CM_SHAPER_RAMB_EXP_REGION1_NUM_SEGMENTS 28 30 regCM2_CM_SHAPER_RAMB_REGION_2_3 0 0x10d4 4 0 2 CM_SHAPER_RAMB_EXP_REGION2_LUT_OFFSET 0 8 CM_SHAPER_RAMB_EXP_REGION2_NUM_SEGMENTS 12 14 CM_SHAPER_RAMB_EXP_REGION3_LUT_OFFSET 16 24 CM_SHAPER_RAMB_EXP_REGION3_NUM_SEGMENTS 28 30 regCM2_CM_SHAPER_RAMB_REGION_4_5 0 0x10d5 4 0 2 CM_SHAPER_RAMB_EXP_REGION4_LUT_OFFSET 0 8 CM_SHAPER_RAMB_EXP_REGION4_NUM_SEGMENTS 12 14 CM_SHAPER_RAMB_EXP_REGION5_LUT_OFFSET 16 24 CM_SHAPER_RAMB_EXP_REGION5_NUM_SEGMENTS 28 30 regCM2_CM_SHAPER_RAMB_REGION_6_7 0 0x10d6 4 0 2 CM_SHAPER_RAMB_EXP_REGION6_LUT_OFFSET 0 8 CM_SHAPER_RAMB_EXP_REGION6_NUM_SEGMENTS 12 14 CM_SHAPER_RAMB_EXP_REGION7_LUT_OFFSET 16 24 CM_SHAPER_RAMB_EXP_REGION7_NUM_SEGMENTS 28 30 regCM2_CM_SHAPER_RAMB_REGION_8_9 0 0x10d7 4 0 2 CM_SHAPER_RAMB_EXP_REGION8_LUT_OFFSET 0 8 CM_SHAPER_RAMB_EXP_REGION8_NUM_SEGMENTS 12 14 CM_SHAPER_RAMB_EXP_REGION9_LUT_OFFSET 16 24 CM_SHAPER_RAMB_EXP_REGION9_NUM_SEGMENTS 28 30 regCM2_CM_SHAPER_RAMB_REGION_10_11 0 0x10d8 4 0 2 CM_SHAPER_RAMB_EXP_REGION10_LUT_OFFSET 0 8 CM_SHAPER_RAMB_EXP_REGION10_NUM_SEGMENTS 12 14 CM_SHAPER_RAMB_EXP_REGION11_LUT_OFFSET 16 24 CM_SHAPER_RAMB_EXP_REGION11_NUM_SEGMENTS 28 30 regCM2_CM_SHAPER_RAMB_REGION_12_13 0 0x10d9 4 0 2 CM_SHAPER_RAMB_EXP_REGION12_LUT_OFFSET 0 8 CM_SHAPER_RAMB_EXP_REGION12_NUM_SEGMENTS 12 14 CM_SHAPER_RAMB_EXP_REGION13_LUT_OFFSET 16 24 CM_SHAPER_RAMB_EXP_REGION13_NUM_SEGMENTS 28 30 regCM2_CM_SHAPER_RAMB_REGION_14_15 0 0x10da 4 0 2 CM_SHAPER_RAMB_EXP_REGION14_LUT_OFFSET 0 8 CM_SHAPER_RAMB_EXP_REGION14_NUM_SEGMENTS 12 14 CM_SHAPER_RAMB_EXP_REGION15_LUT_OFFSET 16 24 CM_SHAPER_RAMB_EXP_REGION15_NUM_SEGMENTS 28 30 regCM2_CM_SHAPER_RAMB_REGION_16_17 0 0x10db 4 0 2 CM_SHAPER_RAMB_EXP_REGION16_LUT_OFFSET 0 8 CM_SHAPER_RAMB_EXP_REGION16_NUM_SEGMENTS 12 14 CM_SHAPER_RAMB_EXP_REGION17_LUT_OFFSET 16 24 CM_SHAPER_RAMB_EXP_REGION17_NUM_SEGMENTS 28 30 regCM2_CM_SHAPER_RAMB_REGION_18_19 0 0x10dc 4 0 2 CM_SHAPER_RAMB_EXP_REGION18_LUT_OFFSET 0 8 CM_SHAPER_RAMB_EXP_REGION18_NUM_SEGMENTS 12 14 CM_SHAPER_RAMB_EXP_REGION19_LUT_OFFSET 16 24 CM_SHAPER_RAMB_EXP_REGION19_NUM_SEGMENTS 28 30 regCM2_CM_SHAPER_RAMB_REGION_20_21 0 0x10dd 4 0 2 CM_SHAPER_RAMB_EXP_REGION20_LUT_OFFSET 0 8 CM_SHAPER_RAMB_EXP_REGION20_NUM_SEGMENTS 12 14 CM_SHAPER_RAMB_EXP_REGION21_LUT_OFFSET 16 24 CM_SHAPER_RAMB_EXP_REGION21_NUM_SEGMENTS 28 30 regCM2_CM_SHAPER_RAMB_REGION_22_23 0 0x10de 4 0 2 CM_SHAPER_RAMB_EXP_REGION22_LUT_OFFSET 0 8 CM_SHAPER_RAMB_EXP_REGION22_NUM_SEGMENTS 12 14 CM_SHAPER_RAMB_EXP_REGION23_LUT_OFFSET 16 24 CM_SHAPER_RAMB_EXP_REGION23_NUM_SEGMENTS 28 30 regCM2_CM_SHAPER_RAMB_REGION_24_25 0 0x10df 4 0 2 CM_SHAPER_RAMB_EXP_REGION24_LUT_OFFSET 0 8 CM_SHAPER_RAMB_EXP_REGION24_NUM_SEGMENTS 12 14 CM_SHAPER_RAMB_EXP_REGION25_LUT_OFFSET 16 24 CM_SHAPER_RAMB_EXP_REGION25_NUM_SEGMENTS 28 30 regCM2_CM_SHAPER_RAMB_REGION_26_27 0 0x10e0 4 0 2 CM_SHAPER_RAMB_EXP_REGION26_LUT_OFFSET 0 8 CM_SHAPER_RAMB_EXP_REGION26_NUM_SEGMENTS 12 14 CM_SHAPER_RAMB_EXP_REGION27_LUT_OFFSET 16 24 CM_SHAPER_RAMB_EXP_REGION27_NUM_SEGMENTS 28 30 regCM2_CM_SHAPER_RAMB_REGION_28_29 0 0x10e1 4 0 2 CM_SHAPER_RAMB_EXP_REGION28_LUT_OFFSET 0 8 CM_SHAPER_RAMB_EXP_REGION28_NUM_SEGMENTS 12 14 CM_SHAPER_RAMB_EXP_REGION29_LUT_OFFSET 16 24 CM_SHAPER_RAMB_EXP_REGION29_NUM_SEGMENTS 28 30 regCM2_CM_SHAPER_RAMB_REGION_30_31 0 0x10e2 4 0 2 CM_SHAPER_RAMB_EXP_REGION30_LUT_OFFSET 0 8 CM_SHAPER_RAMB_EXP_REGION30_NUM_SEGMENTS 12 14 CM_SHAPER_RAMB_EXP_REGION31_LUT_OFFSET 16 24 CM_SHAPER_RAMB_EXP_REGION31_NUM_SEGMENTS 28 30 regCM2_CM_SHAPER_RAMB_REGION_32_33 0 0x10e3 4 0 2 CM_SHAPER_RAMB_EXP_REGION32_LUT_OFFSET 0 8 CM_SHAPER_RAMB_EXP_REGION32_NUM_SEGMENTS 12 14 CM_SHAPER_RAMB_EXP_REGION33_LUT_OFFSET 16 24 CM_SHAPER_RAMB_EXP_REGION33_NUM_SEGMENTS 28 30 regCM2_CM_MEM_PWR_CTRL2 0 0x10e4 4 0 2 SHAPER_MEM_PWR_FORCE 8 9 SHAPER_MEM_PWR_DIS 10 10 HDR3DLUT_MEM_PWR_FORCE 12 13 HDR3DLUT_MEM_PWR_DIS 14 14 regCM2_CM_MEM_PWR_STATUS2 0 0x10e5 2 0 2 SHAPER_MEM_PWR_STATE 4 5 HDR3DLUT_MEM_PWR_STATE 6 7 regCM2_CM_3DLUT_MODE 0 0x10e6 3 0 2 CM_3DLUT_MODE 0 1 CM_3DLUT_SIZE 4 4 CM_3DLUT_MODE_CURRENT 8 9 regCM2_CM_3DLUT_INDEX 0 0x10e7 1 0 2 CM_3DLUT_INDEX 0 10 regCM2_CM_3DLUT_DATA 0 0x10e8 2 0 2 CM_3DLUT_DATA0 0 15 CM_3DLUT_DATA1 16 31 regCM2_CM_3DLUT_DATA_30BIT 0 0x10e9 1 0 2 CM_3DLUT_DATA_30BIT 2 31 regCM2_CM_3DLUT_READ_WRITE_CONTROL 0 0x10ea 4 0 2 CM_3DLUT_WRITE_EN_MASK 0 3 CM_3DLUT_RAM_SEL 4 4 CM_3DLUT_30BIT_EN 8 8 CM_3DLUT_READ_SEL 16 17 regCM2_CM_3DLUT_OUT_NORM_FACTOR 0 0x10eb 1 0 2 CM_3DLUT_OUT_NORM_FACTOR 0 15 regCM2_CM_3DLUT_OUT_OFFSET_R 0 0x10ec 2 0 2 CM_3DLUT_OUT_OFFSET_R 0 15 CM_3DLUT_OUT_SCALE_R 16 31 regCM2_CM_3DLUT_OUT_OFFSET_G 0 0x10ed 2 0 2 CM_3DLUT_OUT_OFFSET_G 0 15 CM_3DLUT_OUT_SCALE_G 16 31 regCM2_CM_3DLUT_OUT_OFFSET_B 0 0x10ee 2 0 2 CM_3DLUT_OUT_OFFSET_B 0 15 CM_3DLUT_OUT_SCALE_B 16 31 regCM2_CM_TEST_DEBUG_INDEX 0 0x10ef 2 0 2 CM_TEST_DEBUG_INDEX 0 7 CM_TEST_DEBUG_WRITE_EN 8 8 regCM2_CM_TEST_DEBUG_DATA 0 0x10f0 1 0 2 CM_TEST_DEBUG_DATA 0 31 regDPP_TOP2_DPP_CONTROL 0 0xf9b 8 0 2 DPP_CLOCK_ENABLE 4 4 DPPCLK_G_GATE_DISABLE 8 8 DPPCLK_G_DYN_GATE_DISABLE 10 10 DPPCLK_G_DSCL_GATE_DISABLE 12 12 DPPCLK_R_GATE_DISABLE 14 14 DISPCLK_R_GATE_DISABLE 16 16 DISPCLK_G_GATE_DISABLE 18 18 DPP_TEST_CLK_SEL 28 30 regDPP_TOP2_DPP_SOFT_RESET 0 0xf9c 4 0 2 CNVC_SOFT_RESET 0 0 DSCL_SOFT_RESET 4 4 CM_SOFT_RESET 8 8 OBUF_SOFT_RESET 12 12 regDPP_TOP2_DPP_CRC_VAL_R_G 0 0xf9d 2 0 2 DPP_CRC_R_CR 0 15 DPP_CRC_G_Y 16 31 regDPP_TOP2_DPP_CRC_VAL_B_A 0 0xf9e 2 0 2 DPP_CRC_B_CB 0 15 DPP_CRC_ALPHA 16 31 regDPP_TOP2_DPP_CRC_CTRL 0 0xf9f 11 0 2 DPP_CRC_EN 0 0 DPP_CRC_CONT_EN 1 1 DPP_CRC_ONE_SHOT_PENDING 2 2 DPP_CRC_420_COMP_SEL 3 3 DPP_CRC_SRC_SEL 4 5 DPP_CRC_STEREO_EN 6 6 DPP_CRC_STEREO_MODE 7 8 DPP_CRC_INTERLACE_MODE 9 10 DPP_CRC_PIX_FORMAT_SEL 11 13 DPP_CRC_CURSOR_FORMAT_SEL 14 15 DPP_CRC_MASK 16 31 regDPP_TOP2_HOST_READ_CONTROL 0 0xfa0 1 0 2 HOST_READ_RATE_CONTROL 0 7 regDC_PERFMON13_PERFCOUNTER_CNTL 0 0x10fa 11 0 2 PERFCOUNTER_EVENT_SEL 0 8 PERFCOUNTER_CVALUE_SEL 9 11 PERFCOUNTER_INC_MODE 12 14 PERFCOUNTER_HW_CNTL_SEL 15 15 PERFCOUNTER_RUNEN_MODE 16 16 PERFCOUNTER_CNTOFF_START_DIS 22 22 PERFCOUNTER_RESTART_EN 23 23 PERFCOUNTER_INT_EN 24 24 PERFCOUNTER_OFF_MASK 25 25 PERFCOUNTER_ACTIVE 26 26 PERFCOUNTER_CNTL_SEL 29 31 regDC_PERFMON13_PERFCOUNTER_CNTL2 0 0x10fb 5 0 2 PERFCOUNTER_COUNTED_VALUE_TYPE 0 1 PERFCOUNTER_HW_STOP1_SEL 2 2 PERFCOUNTER_HW_STOP2_SEL 3 3 PERFCOUNTER_CNTOFF_SEL 8 13 PERFCOUNTER_CNTL2_SEL 29 31 regDC_PERFMON13_PERFCOUNTER_STATE 0 0x10fc 16 0 2 PERFCOUNTER_CNT0_STATE 0 1 PERFCOUNTER_STATE_SEL0 2 2 PERFCOUNTER_CNT1_STATE 4 5 PERFCOUNTER_STATE_SEL1 6 6 PERFCOUNTER_CNT2_STATE 8 9 PERFCOUNTER_STATE_SEL2 10 10 PERFCOUNTER_CNT3_STATE 12 13 PERFCOUNTER_STATE_SEL3 14 14 PERFCOUNTER_CNT4_STATE 16 17 PERFCOUNTER_STATE_SEL4 18 18 PERFCOUNTER_CNT5_STATE 20 21 PERFCOUNTER_STATE_SEL5 22 22 PERFCOUNTER_CNT6_STATE 24 25 PERFCOUNTER_STATE_SEL6 26 26 PERFCOUNTER_CNT7_STATE 28 29 PERFCOUNTER_STATE_SEL7 30 30 regDC_PERFMON13_PERFMON_CNTL 0 0x10fd 6 0 2 PERFMON_STATE 0 1 PERFMON_RPT_COUNT 8 27 PERFMON_CNTOFF_AND_OR 28 28 PERFMON_CNTOFF_INT_EN 29 29 PERFMON_CNTOFF_INT_STATUS 30 30 PERFMON_CNTOFF_INT_ACK 31 31 regDC_PERFMON13_PERFMON_CNTL2 0 0x10fe 4 0 2 PERFMON_CNTOFF_INT_TYPE 0 0 PERFMON_CLK_ENABLE 1 1 PERFMON_RUN_ENABLE_START_SEL 2 9 PERFMON_RUN_ENABLE_STOP_SEL 10 17 regDC_PERFMON13_PERFMON_CVALUE_INT_MISC 0 0x10ff 17 0 2 PERFCOUNTER_INT0_STATUS 0 0 PERFCOUNTER_INT1_STATUS 1 1 PERFCOUNTER_INT2_STATUS 2 2 PERFCOUNTER_INT3_STATUS 3 3 PERFCOUNTER_INT4_STATUS 4 4 PERFCOUNTER_INT5_STATUS 5 5 PERFCOUNTER_INT6_STATUS 6 6 PERFCOUNTER_INT7_STATUS 7 7 PERFCOUNTER_INT0_ACK 8 8 PERFCOUNTER_INT1_ACK 9 9 PERFCOUNTER_INT2_ACK 10 10 PERFCOUNTER_INT3_ACK 11 11 PERFCOUNTER_INT4_ACK 12 12 PERFCOUNTER_INT5_ACK 13 13 PERFCOUNTER_INT6_ACK 14 14 PERFCOUNTER_INT7_ACK 15 15 PERFMON_CVALUE_HI 16 31 regDC_PERFMON13_PERFMON_CVALUE_LOW 0 0x1100 1 0 2 PERFMON_CVALUE_LOW 0 31 regDC_PERFMON13_PERFMON_HI 0 0x1101 2 0 2 PERFMON_HI 0 15 PERFMON_READ_SEL 29 31 regDC_PERFMON13_PERFMON_LOW 0 0x1102 1 0 2 PERFMON_LOW 0 31 regCNVC_CFG3_CNVC_SURFACE_PIXEL_FORMAT 0 0x1110 2 0 2 CNVC_SURFACE_PIXEL_FORMAT 0 6 CNVC_ALPHA_PLANE_ENABLE 8 8 regCNVC_CFG3_FORMAT_CONTROL 0 0x1111 11 0 2 FORMAT_EXPANSION_MODE 0 0 FORMAT_CNV16 4 4 ALPHA_EN 8 8 CNVC_BYPASS 12 12 CNVC_BYPASS_MSB_ALIGN 13 13 CLAMP_POSITIVE 16 16 CLAMP_POSITIVE_C 17 17 CNVC_UPDATE_PENDING 20 20 FORMAT_CROSSBAR_R 24 25 FORMAT_CROSSBAR_G 26 27 FORMAT_CROSSBAR_B 28 29 regCNVC_CFG3_FCNV_FP_BIAS_R 0 0x1112 1 0 2 FCNV_FP_BIAS_R 0 18 regCNVC_CFG3_FCNV_FP_BIAS_G 0 0x1113 1 0 2 FCNV_FP_BIAS_G 0 18 regCNVC_CFG3_FCNV_FP_BIAS_B 0 0x1114 1 0 2 FCNV_FP_BIAS_B 0 18 regCNVC_CFG3_FCNV_FP_SCALE_R 0 0x1115 1 0 2 FCNV_FP_SCALE_R 0 18 regCNVC_CFG3_FCNV_FP_SCALE_G 0 0x1116 1 0 2 FCNV_FP_SCALE_G 0 18 regCNVC_CFG3_FCNV_FP_SCALE_B 0 0x1117 1 0 2 FCNV_FP_SCALE_B 0 18 regCNVC_CFG3_COLOR_KEYER_CONTROL 0 0x1118 2 0 2 COLOR_KEYER_EN 0 0 COLOR_KEYER_MODE 4 5 regCNVC_CFG3_COLOR_KEYER_ALPHA 0 0x1119 2 0 2 COLOR_KEYER_ALPHA_LOW 0 15 COLOR_KEYER_ALPHA_HIGH 16 31 regCNVC_CFG3_COLOR_KEYER_RED 0 0x111a 2 0 2 COLOR_KEYER_RED_LOW 0 15 COLOR_KEYER_RED_HIGH 16 31 regCNVC_CFG3_COLOR_KEYER_GREEN 0 0x111b 2 0 2 COLOR_KEYER_GREEN_LOW 0 15 COLOR_KEYER_GREEN_HIGH 16 31 regCNVC_CFG3_COLOR_KEYER_BLUE 0 0x111c 2 0 2 COLOR_KEYER_BLUE_LOW 0 15 COLOR_KEYER_BLUE_HIGH 16 31 regCNVC_CFG3_ALPHA_2BIT_LUT 0 0x111e 4 0 2 ALPHA_2BIT_LUT0 0 7 ALPHA_2BIT_LUT1 8 15 ALPHA_2BIT_LUT2 16 23 ALPHA_2BIT_LUT3 24 31 regCNVC_CFG3_PRE_DEALPHA 0 0x111f 2 0 2 PRE_DEALPHA_EN 0 0 PRE_DEALPHA_ABLND_EN 4 4 regCNVC_CFG3_PRE_CSC_MODE 0 0x1120 2 0 2 PRE_CSC_MODE 0 1 PRE_CSC_MODE_CURRENT 2 3 regCNVC_CFG3_PRE_CSC_C11_C12 0 0x1121 2 0 2 PRE_CSC_C11 0 15 PRE_CSC_C12 16 31 regCNVC_CFG3_PRE_CSC_C13_C14 0 0x1122 2 0 2 PRE_CSC_C13 0 15 PRE_CSC_C14 16 31 regCNVC_CFG3_PRE_CSC_C21_C22 0 0x1123 2 0 2 PRE_CSC_C21 0 15 PRE_CSC_C22 16 31 regCNVC_CFG3_PRE_CSC_C23_C24 0 0x1124 2 0 2 PRE_CSC_C23 0 15 PRE_CSC_C24 16 31 regCNVC_CFG3_PRE_CSC_C31_C32 0 0x1125 2 0 2 PRE_CSC_C31 0 15 PRE_CSC_C32 16 31 regCNVC_CFG3_PRE_CSC_C33_C34 0 0x1126 2 0 2 PRE_CSC_C33 0 15 PRE_CSC_C34 16 31 regCNVC_CFG3_PRE_CSC_B_C11_C12 0 0x1127 2 0 2 PRE_CSC_B_C11 0 15 PRE_CSC_B_C12 16 31 regCNVC_CFG3_PRE_CSC_B_C13_C14 0 0x1128 2 0 2 PRE_CSC_B_C13 0 15 PRE_CSC_B_C14 16 31 regCNVC_CFG3_PRE_CSC_B_C21_C22 0 0x1129 2 0 2 PRE_CSC_B_C21 0 15 PRE_CSC_B_C22 16 31 regCNVC_CFG3_PRE_CSC_B_C23_C24 0 0x112a 2 0 2 PRE_CSC_B_C23 0 15 PRE_CSC_B_C24 16 31 regCNVC_CFG3_PRE_CSC_B_C31_C32 0 0x112b 2 0 2 PRE_CSC_B_C31 0 15 PRE_CSC_B_C32 16 31 regCNVC_CFG3_PRE_CSC_B_C33_C34 0 0x112c 2 0 2 PRE_CSC_B_C33 0 15 PRE_CSC_B_C34 16 31 regCNVC_CFG3_CNVC_COEF_FORMAT 0 0x112d 1 0 2 PRE_CSC_COEF_FORMAT 0 0 regCNVC_CFG3_PRE_DEGAM 0 0x112e 2 0 2 PRE_DEGAM_MODE 0 1 PRE_DEGAM_SELECT 4 6 regCNVC_CFG3_PRE_REALPHA 0 0x112f 2 0 2 PRE_REALPHA_EN 0 0 PRE_REALPHA_ABLND_EN 4 4 regCNVC_CUR3_CURSOR0_CONTROL 0 0x1132 7 0 2 CUR0_ENABLE 0 0 CUR0_EXPANSION_MODE 1 1 CUR0_PIX_INV_MODE 2 2 CUR0_ROM_EN 3 3 CUR0_MODE 4 6 CUR0_PIXEL_ALPHA_MOD_EN 7 7 CUR0_UPDATE_PENDING 16 16 regCNVC_CUR3_CURSOR0_COLOR0 0 0x1133 1 0 2 CUR0_COLOR0 0 23 regCNVC_CUR3_CURSOR0_COLOR1 0 0x1134 1 0 2 CUR0_COLOR1 0 23 regCNVC_CUR3_CURSOR0_FP_SCALE_BIAS 0 0x1135 2 0 2 CUR0_FP_SCALE 0 15 CUR0_FP_BIAS 16 31 regDSCL3_SCL_COEF_RAM_TAP_SELECT 0 0x113a 3 0 2 SCL_COEF_RAM_TAP_PAIR_IDX 0 1 SCL_COEF_RAM_PHASE 8 13 SCL_COEF_RAM_FILTER_TYPE 16 18 regDSCL3_SCL_COEF_RAM_TAP_DATA 0 0x113b 4 0 2 SCL_COEF_RAM_EVEN_TAP_COEF 0 13 SCL_COEF_RAM_EVEN_TAP_COEF_EN 15 15 SCL_COEF_RAM_ODD_TAP_COEF 16 29 SCL_COEF_RAM_ODD_TAP_COEF_EN 31 31 regDSCL3_SCL_MODE 0 0x113c 6 0 2 DSCL_MODE 0 2 SCL_COEF_RAM_SELECT 8 8 SCL_COEF_RAM_SELECT_CURRENT 12 12 SCL_CHROMA_COEF_MODE 16 16 SCL_ALPHA_COEF_MODE 20 20 SCL_COEF_RAM_SELECT_RD 24 24 regDSCL3_SCL_TAP_CONTROL 0 0x113d 4 0 2 SCL_V_NUM_TAPS 0 2 SCL_H_NUM_TAPS 4 6 SCL_V_NUM_TAPS_C 8 10 SCL_H_NUM_TAPS_C 12 14 regDSCL3_DSCL_CONTROL 0 0x113e 1 0 2 SCL_BOUNDARY_MODE 0 0 regDSCL3_DSCL_2TAP_CONTROL 0 0x113f 6 0 2 SCL_H_2TAP_HARDCODE_COEF_EN 0 0 SCL_H_2TAP_SHARP_EN 4 4 SCL_H_2TAP_SHARP_FACTOR 8 10 SCL_V_2TAP_HARDCODE_COEF_EN 16 16 SCL_V_2TAP_SHARP_EN 20 20 SCL_V_2TAP_SHARP_FACTOR 24 26 regDSCL3_SCL_MANUAL_REPLICATE_CONTROL 0 0x1140 2 0 2 SCL_V_MANUAL_REPLICATE_FACTOR 0 3 SCL_H_MANUAL_REPLICATE_FACTOR 8 11 regDSCL3_SCL_HORZ_FILTER_SCALE_RATIO 0 0x1141 1 0 2 SCL_H_SCALE_RATIO 0 26 regDSCL3_SCL_HORZ_FILTER_INIT 0 0x1142 2 0 2 SCL_H_INIT_FRAC 0 23 SCL_H_INIT_INT 24 27 regDSCL3_SCL_HORZ_FILTER_SCALE_RATIO_C 0 0x1143 1 0 2 SCL_H_SCALE_RATIO_C 0 26 regDSCL3_SCL_HORZ_FILTER_INIT_C 0 0x1144 2 0 2 SCL_H_INIT_FRAC_C 0 23 SCL_H_INIT_INT_C 24 27 regDSCL3_SCL_VERT_FILTER_SCALE_RATIO 0 0x1145 1 0 2 SCL_V_SCALE_RATIO 0 26 regDSCL3_SCL_VERT_FILTER_INIT 0 0x1146 2 0 2 SCL_V_INIT_FRAC 0 23 SCL_V_INIT_INT 24 27 regDSCL3_SCL_VERT_FILTER_INIT_BOT 0 0x1147 2 0 2 SCL_V_INIT_FRAC_BOT 0 23 SCL_V_INIT_INT_BOT 24 27 regDSCL3_SCL_VERT_FILTER_SCALE_RATIO_C 0 0x1148 1 0 2 SCL_V_SCALE_RATIO_C 0 26 regDSCL3_SCL_VERT_FILTER_INIT_C 0 0x1149 2 0 2 SCL_V_INIT_FRAC_C 0 23 SCL_V_INIT_INT_C 24 27 regDSCL3_SCL_VERT_FILTER_INIT_BOT_C 0 0x114a 2 0 2 SCL_V_INIT_FRAC_BOT_C 0 23 SCL_V_INIT_INT_BOT_C 24 27 regDSCL3_SCL_BLACK_COLOR 0 0x114b 2 0 2 SCL_BLACK_COLOR_RGB_Y 0 15 SCL_BLACK_COLOR_CBCR 16 31 regDSCL3_DSCL_UPDATE 0 0x114c 1 0 2 SCL_UPDATE_PENDING 0 0 regDSCL3_DSCL_AUTOCAL 0 0x114d 3 0 2 AUTOCAL_MODE 0 1 AUTOCAL_NUM_PIPE 8 9 AUTOCAL_PIPE_ID 12 13 regDSCL3_DSCL_EXT_OVERSCAN_LEFT_RIGHT 0 0x114e 2 0 2 EXT_OVERSCAN_RIGHT 0 12 EXT_OVERSCAN_LEFT 16 28 regDSCL3_DSCL_EXT_OVERSCAN_TOP_BOTTOM 0 0x114f 2 0 2 EXT_OVERSCAN_BOTTOM 0 12 EXT_OVERSCAN_TOP 16 28 regDSCL3_OTG_H_BLANK 0 0x1150 2 0 2 OTG_H_BLANK_START 0 13 OTG_H_BLANK_END 16 29 regDSCL3_OTG_V_BLANK 0 0x1151 2 0 2 OTG_V_BLANK_START 0 13 OTG_V_BLANK_END 16 29 regDSCL3_RECOUT_START 0 0x1152 2 0 2 RECOUT_START_X 0 12 RECOUT_START_Y 16 28 regDSCL3_RECOUT_SIZE 0 0x1153 2 0 2 RECOUT_WIDTH 0 13 RECOUT_HEIGHT 16 29 regDSCL3_MPC_SIZE 0 0x1154 2 0 2 MPC_WIDTH 0 13 MPC_HEIGHT 16 29 regDSCL3_LB_DATA_FORMAT 0 0x1155 2 0 2 INTERLEAVE_EN 0 0 ALPHA_EN 4 4 regDSCL3_LB_MEMORY_CTRL 0 0x1156 4 0 2 MEMORY_CONFIG 0 1 LB_MAX_PARTITIONS 8 13 LB_NUM_PARTITIONS 16 22 LB_NUM_PARTITIONS_C 24 30 regDSCL3_LB_V_COUNTER 0 0x1157 2 0 2 V_COUNTER 0 12 V_COUNTER_C 16 28 regDSCL3_DSCL_MEM_PWR_CTRL 0 0x1158 15 0 2 LUT_MEM_PWR_FORCE 0 1 LUT_MEM_PWR_DIS 2 2 LB_G1_MEM_PWR_FORCE 4 5 LB_G1_MEM_PWR_DIS 6 6 LB_G2_MEM_PWR_FORCE 8 9 LB_G2_MEM_PWR_DIS 10 10 LB_G3_MEM_PWR_FORCE 12 13 LB_G3_MEM_PWR_DIS 14 14 LB_G4_MEM_PWR_FORCE 16 17 LB_G4_MEM_PWR_DIS 18 18 LB_G5_MEM_PWR_FORCE 20 21 LB_G5_MEM_PWR_DIS 22 22 LB_G6_MEM_PWR_FORCE 24 25 LB_G6_MEM_PWR_DIS 26 26 LB_MEM_PWR_MODE 28 28 regDSCL3_DSCL_MEM_PWR_STATUS 0 0x1159 7 0 2 LUT_MEM_PWR_STATE 0 1 LB_G1_MEM_PWR_STATE 2 3 LB_G2_MEM_PWR_STATE 4 5 LB_G3_MEM_PWR_STATE 6 7 LB_G4_MEM_PWR_STATE 8 9 LB_G5_MEM_PWR_STATE 10 11 LB_G6_MEM_PWR_STATE 12 13 regDSCL3_OBUF_CONTROL 0 0x115a 4 0 2 OBUF_BYPASS 0 0 OBUF_USE_FULL_BUFFER 1 1 OBUF_IS_HALF_RECOUT_WIDTH 2 2 OBUF_OUT_HOLD_CNT 4 7 regDSCL3_OBUF_MEM_PWR_CTRL 0 0x115b 4 0 2 OBUF_MEM_PWR_FORCE 0 1 OBUF_MEM_PWR_DIS 2 2 OBUF_MEM_PWR_MODE 8 8 OBUF_MEM_PWR_STATE 16 17 regCM3_CM_CONTROL 0 0x1161 2 0 2 CM_BYPASS 0 0 CM_UPDATE_PENDING 8 8 regCM3_CM_POST_CSC_CONTROL 0 0x1162 2 0 2 CM_POST_CSC_MODE 0 1 CM_POST_CSC_MODE_CURRENT 2 3 regCM3_CM_POST_CSC_C11_C12 0 0x1163 2 0 2 CM_POST_CSC_C11 0 15 CM_POST_CSC_C12 16 31 regCM3_CM_POST_CSC_C13_C14 0 0x1164 2 0 2 CM_POST_CSC_C13 0 15 CM_POST_CSC_C14 16 31 regCM3_CM_POST_CSC_C21_C22 0 0x1165 2 0 2 CM_POST_CSC_C21 0 15 CM_POST_CSC_C22 16 31 regCM3_CM_POST_CSC_C23_C24 0 0x1166 2 0 2 CM_POST_CSC_C23 0 15 CM_POST_CSC_C24 16 31 regCM3_CM_POST_CSC_C31_C32 0 0x1167 2 0 2 CM_POST_CSC_C31 0 15 CM_POST_CSC_C32 16 31 regCM3_CM_POST_CSC_C33_C34 0 0x1168 2 0 2 CM_POST_CSC_C33 0 15 CM_POST_CSC_C34 16 31 regCM3_CM_POST_CSC_B_C11_C12 0 0x1169 2 0 2 CM_POST_CSC_B_C11 0 15 CM_POST_CSC_B_C12 16 31 regCM3_CM_POST_CSC_B_C13_C14 0 0x116a 2 0 2 CM_POST_CSC_B_C13 0 15 CM_POST_CSC_B_C14 16 31 regCM3_CM_POST_CSC_B_C21_C22 0 0x116b 2 0 2 CM_POST_CSC_B_C21 0 15 CM_POST_CSC_B_C22 16 31 regCM3_CM_POST_CSC_B_C23_C24 0 0x116c 2 0 2 CM_POST_CSC_B_C23 0 15 CM_POST_CSC_B_C24 16 31 regCM3_CM_POST_CSC_B_C31_C32 0 0x116d 2 0 2 CM_POST_CSC_B_C31 0 15 CM_POST_CSC_B_C32 16 31 regCM3_CM_POST_CSC_B_C33_C34 0 0x116e 2 0 2 CM_POST_CSC_B_C33 0 15 CM_POST_CSC_B_C34 16 31 regCM3_CM_GAMUT_REMAP_CONTROL 0 0x116f 2 0 2 CM_GAMUT_REMAP_MODE 0 1 CM_GAMUT_REMAP_MODE_CURRENT 2 3 regCM3_CM_GAMUT_REMAP_C11_C12 0 0x1170 2 0 2 CM_GAMUT_REMAP_C11 0 15 CM_GAMUT_REMAP_C12 16 31 regCM3_CM_GAMUT_REMAP_C13_C14 0 0x1171 2 0 2 CM_GAMUT_REMAP_C13 0 15 CM_GAMUT_REMAP_C14 16 31 regCM3_CM_GAMUT_REMAP_C21_C22 0 0x1172 2 0 2 CM_GAMUT_REMAP_C21 0 15 CM_GAMUT_REMAP_C22 16 31 regCM3_CM_GAMUT_REMAP_C23_C24 0 0x1173 2 0 2 CM_GAMUT_REMAP_C23 0 15 CM_GAMUT_REMAP_C24 16 31 regCM3_CM_GAMUT_REMAP_C31_C32 0 0x1174 2 0 2 CM_GAMUT_REMAP_C31 0 15 CM_GAMUT_REMAP_C32 16 31 regCM3_CM_GAMUT_REMAP_C33_C34 0 0x1175 2 0 2 CM_GAMUT_REMAP_C33 0 15 CM_GAMUT_REMAP_C34 16 31 regCM3_CM_GAMUT_REMAP_B_C11_C12 0 0x1176 2 0 2 CM_GAMUT_REMAP_B_C11 0 15 CM_GAMUT_REMAP_B_C12 16 31 regCM3_CM_GAMUT_REMAP_B_C13_C14 0 0x1177 2 0 2 CM_GAMUT_REMAP_B_C13 0 15 CM_GAMUT_REMAP_B_C14 16 31 regCM3_CM_GAMUT_REMAP_B_C21_C22 0 0x1178 2 0 2 CM_GAMUT_REMAP_B_C21 0 15 CM_GAMUT_REMAP_B_C22 16 31 regCM3_CM_GAMUT_REMAP_B_C23_C24 0 0x1179 2 0 2 CM_GAMUT_REMAP_B_C23 0 15 CM_GAMUT_REMAP_B_C24 16 31 regCM3_CM_GAMUT_REMAP_B_C31_C32 0 0x117a 2 0 2 CM_GAMUT_REMAP_B_C31 0 15 CM_GAMUT_REMAP_B_C32 16 31 regCM3_CM_GAMUT_REMAP_B_C33_C34 0 0x117b 2 0 2 CM_GAMUT_REMAP_B_C33 0 15 CM_GAMUT_REMAP_B_C34 16 31 regCM3_CM_BIAS_CR_R 0 0x117c 1 0 2 CM_BIAS_CR_R 0 15 regCM3_CM_BIAS_Y_G_CB_B 0 0x117d 2 0 2 CM_BIAS_Y_G 0 15 CM_BIAS_CB_B 16 31 regCM3_CM_GAMCOR_CONTROL 0 0x117e 5 0 2 CM_GAMCOR_MODE 0 1 CM_GAMCOR_SELECT 2 2 CM_GAMCOR_PWL_DISABLE 3 3 CM_GAMCOR_MODE_CURRENT 4 5 CM_GAMCOR_SELECT_CURRENT 6 6 regCM3_CM_GAMCOR_LUT_INDEX 0 0x117f 1 0 2 CM_GAMCOR_LUT_INDEX 0 8 regCM3_CM_GAMCOR_LUT_DATA 0 0x1180 1 0 2 CM_GAMCOR_LUT_DATA 0 17 regCM3_CM_GAMCOR_LUT_CONTROL 0 0x1181 5 0 2 CM_GAMCOR_LUT_WRITE_COLOR_MASK 0 2 CM_GAMCOR_LUT_READ_COLOR_SEL 3 4 CM_GAMCOR_LUT_READ_DBG 5 5 CM_GAMCOR_LUT_HOST_SEL 6 6 CM_GAMCOR_LUT_CONFIG_MODE 7 7 regCM3_CM_GAMCOR_RAMA_START_CNTL_B 0 0x1182 2 0 2 CM_GAMCOR_RAMA_EXP_REGION_START_B 0 17 CM_GAMCOR_RAMA_EXP_REGION_START_SEGMENT_B 20 26 regCM3_CM_GAMCOR_RAMA_START_CNTL_G 0 0x1183 2 0 2 CM_GAMCOR_RAMA_EXP_REGION_START_G 0 17 CM_GAMCOR_RAMA_EXP_REGION_START_SEGMENT_G 20 26 regCM3_CM_GAMCOR_RAMA_START_CNTL_R 0 0x1184 2 0 2 CM_GAMCOR_RAMA_EXP_REGION_START_R 0 17 CM_GAMCOR_RAMA_EXP_REGION_START_SEGMENT_R 20 26 regCM3_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B 0 0x1185 1 0 2 CM_GAMCOR_RAMA_EXP_REGION_START_SLOPE_B 0 17 regCM3_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G 0 0x1186 1 0 2 CM_GAMCOR_RAMA_EXP_REGION_START_SLOPE_G 0 17 regCM3_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R 0 0x1187 1 0 2 CM_GAMCOR_RAMA_EXP_REGION_START_SLOPE_R 0 17 regCM3_CM_GAMCOR_RAMA_START_BASE_CNTL_B 0 0x1188 1 0 2 CM_GAMCOR_RAMA_EXP_REGION_START_BASE_B 0 17 regCM3_CM_GAMCOR_RAMA_START_BASE_CNTL_G 0 0x1189 1 0 2 CM_GAMCOR_RAMA_EXP_REGION_START_BASE_G 0 17 regCM3_CM_GAMCOR_RAMA_START_BASE_CNTL_R 0 0x118a 1 0 2 CM_GAMCOR_RAMA_EXP_REGION_START_BASE_R 0 17 regCM3_CM_GAMCOR_RAMA_END_CNTL1_B 0 0x118b 1 0 2 CM_GAMCOR_RAMA_EXP_REGION_END_BASE_B 0 17 regCM3_CM_GAMCOR_RAMA_END_CNTL2_B 0 0x118c 2 0 2 CM_GAMCOR_RAMA_EXP_REGION_END_B 0 15 CM_GAMCOR_RAMA_EXP_REGION_END_SLOPE_B 16 31 regCM3_CM_GAMCOR_RAMA_END_CNTL1_G 0 0x118d 1 0 2 CM_GAMCOR_RAMA_EXP_REGION_END_BASE_G 0 17 regCM3_CM_GAMCOR_RAMA_END_CNTL2_G 0 0x118e 2 0 2 CM_GAMCOR_RAMA_EXP_REGION_END_G 0 15 CM_GAMCOR_RAMA_EXP_REGION_END_SLOPE_G 16 31 regCM3_CM_GAMCOR_RAMA_END_CNTL1_R 0 0x118f 1 0 2 CM_GAMCOR_RAMA_EXP_REGION_END_BASE_R 0 17 regCM3_CM_GAMCOR_RAMA_END_CNTL2_R 0 0x1190 2 0 2 CM_GAMCOR_RAMA_EXP_REGION_END_R 0 15 CM_GAMCOR_RAMA_EXP_REGION_END_SLOPE_R 16 31 regCM3_CM_GAMCOR_RAMA_OFFSET_B 0 0x1191 1 0 2 CM_GAMCOR_RAMA_OFFSET_B 0 18 regCM3_CM_GAMCOR_RAMA_OFFSET_G 0 0x1192 1 0 2 CM_GAMCOR_RAMA_OFFSET_G 0 18 regCM3_CM_GAMCOR_RAMA_OFFSET_R 0 0x1193 1 0 2 CM_GAMCOR_RAMA_OFFSET_R 0 18 regCM3_CM_GAMCOR_RAMA_REGION_0_1 0 0x1194 4 0 2 CM_GAMCOR_RAMA_EXP_REGION0_LUT_OFFSET 0 8 CM_GAMCOR_RAMA_EXP_REGION0_NUM_SEGMENTS 12 14 CM_GAMCOR_RAMA_EXP_REGION1_LUT_OFFSET 16 24 CM_GAMCOR_RAMA_EXP_REGION1_NUM_SEGMENTS 28 30 regCM3_CM_GAMCOR_RAMA_REGION_2_3 0 0x1195 4 0 2 CM_GAMCOR_RAMA_EXP_REGION2_LUT_OFFSET 0 8 CM_GAMCOR_RAMA_EXP_REGION2_NUM_SEGMENTS 12 14 CM_GAMCOR_RAMA_EXP_REGION3_LUT_OFFSET 16 24 CM_GAMCOR_RAMA_EXP_REGION3_NUM_SEGMENTS 28 30 regCM3_CM_GAMCOR_RAMA_REGION_4_5 0 0x1196 4 0 2 CM_GAMCOR_RAMA_EXP_REGION4_LUT_OFFSET 0 8 CM_GAMCOR_RAMA_EXP_REGION4_NUM_SEGMENTS 12 14 CM_GAMCOR_RAMA_EXP_REGION5_LUT_OFFSET 16 24 CM_GAMCOR_RAMA_EXP_REGION5_NUM_SEGMENTS 28 30 regCM3_CM_GAMCOR_RAMA_REGION_6_7 0 0x1197 4 0 2 CM_GAMCOR_RAMA_EXP_REGION6_LUT_OFFSET 0 8 CM_GAMCOR_RAMA_EXP_REGION6_NUM_SEGMENTS 12 14 CM_GAMCOR_RAMA_EXP_REGION7_LUT_OFFSET 16 24 CM_GAMCOR_RAMA_EXP_REGION7_NUM_SEGMENTS 28 30 regCM3_CM_GAMCOR_RAMA_REGION_8_9 0 0x1198 4 0 2 CM_GAMCOR_RAMA_EXP_REGION8_LUT_OFFSET 0 8 CM_GAMCOR_RAMA_EXP_REGION8_NUM_SEGMENTS 12 14 CM_GAMCOR_RAMA_EXP_REGION9_LUT_OFFSET 16 24 CM_GAMCOR_RAMA_EXP_REGION9_NUM_SEGMENTS 28 30 regCM3_CM_GAMCOR_RAMA_REGION_10_11 0 0x1199 4 0 2 CM_GAMCOR_RAMA_EXP_REGION10_LUT_OFFSET 0 8 CM_GAMCOR_RAMA_EXP_REGION10_NUM_SEGMENTS 12 14 CM_GAMCOR_RAMA_EXP_REGION11_LUT_OFFSET 16 24 CM_GAMCOR_RAMA_EXP_REGION11_NUM_SEGMENTS 28 30 regCM3_CM_GAMCOR_RAMA_REGION_12_13 0 0x119a 4 0 2 CM_GAMCOR_RAMA_EXP_REGION12_LUT_OFFSET 0 8 CM_GAMCOR_RAMA_EXP_REGION12_NUM_SEGMENTS 12 14 CM_GAMCOR_RAMA_EXP_REGION13_LUT_OFFSET 16 24 CM_GAMCOR_RAMA_EXP_REGION13_NUM_SEGMENTS 28 30 regCM3_CM_GAMCOR_RAMA_REGION_14_15 0 0x119b 4 0 2 CM_GAMCOR_RAMA_EXP_REGION14_LUT_OFFSET 0 8 CM_GAMCOR_RAMA_EXP_REGION14_NUM_SEGMENTS 12 14 CM_GAMCOR_RAMA_EXP_REGION15_LUT_OFFSET 16 24 CM_GAMCOR_RAMA_EXP_REGION15_NUM_SEGMENTS 28 30 regCM3_CM_GAMCOR_RAMA_REGION_16_17 0 0x119c 4 0 2 CM_GAMCOR_RAMA_EXP_REGION16_LUT_OFFSET 0 8 CM_GAMCOR_RAMA_EXP_REGION16_NUM_SEGMENTS 12 14 CM_GAMCOR_RAMA_EXP_REGION17_LUT_OFFSET 16 24 CM_GAMCOR_RAMA_EXP_REGION17_NUM_SEGMENTS 28 30 regCM3_CM_GAMCOR_RAMA_REGION_18_19 0 0x119d 4 0 2 CM_GAMCOR_RAMA_EXP_REGION18_LUT_OFFSET 0 8 CM_GAMCOR_RAMA_EXP_REGION18_NUM_SEGMENTS 12 14 CM_GAMCOR_RAMA_EXP_REGION19_LUT_OFFSET 16 24 CM_GAMCOR_RAMA_EXP_REGION19_NUM_SEGMENTS 28 30 regCM3_CM_GAMCOR_RAMA_REGION_20_21 0 0x119e 4 0 2 CM_GAMCOR_RAMA_EXP_REGION20_LUT_OFFSET 0 8 CM_GAMCOR_RAMA_EXP_REGION20_NUM_SEGMENTS 12 14 CM_GAMCOR_RAMA_EXP_REGION21_LUT_OFFSET 16 24 CM_GAMCOR_RAMA_EXP_REGION21_NUM_SEGMENTS 28 30 regCM3_CM_GAMCOR_RAMA_REGION_22_23 0 0x119f 4 0 2 CM_GAMCOR_RAMA_EXP_REGION22_LUT_OFFSET 0 8 CM_GAMCOR_RAMA_EXP_REGION22_NUM_SEGMENTS 12 14 CM_GAMCOR_RAMA_EXP_REGION23_LUT_OFFSET 16 24 CM_GAMCOR_RAMA_EXP_REGION23_NUM_SEGMENTS 28 30 regCM3_CM_GAMCOR_RAMA_REGION_24_25 0 0x11a0 4 0 2 CM_GAMCOR_RAMA_EXP_REGION24_LUT_OFFSET 0 8 CM_GAMCOR_RAMA_EXP_REGION24_NUM_SEGMENTS 12 14 CM_GAMCOR_RAMA_EXP_REGION25_LUT_OFFSET 16 24 CM_GAMCOR_RAMA_EXP_REGION25_NUM_SEGMENTS 28 30 regCM3_CM_GAMCOR_RAMA_REGION_26_27 0 0x11a1 4 0 2 CM_GAMCOR_RAMA_EXP_REGION26_LUT_OFFSET 0 8 CM_GAMCOR_RAMA_EXP_REGION26_NUM_SEGMENTS 12 14 CM_GAMCOR_RAMA_EXP_REGION27_LUT_OFFSET 16 24 CM_GAMCOR_RAMA_EXP_REGION27_NUM_SEGMENTS 28 30 regCM3_CM_GAMCOR_RAMA_REGION_28_29 0 0x11a2 4 0 2 CM_GAMCOR_RAMA_EXP_REGION28_LUT_OFFSET 0 8 CM_GAMCOR_RAMA_EXP_REGION28_NUM_SEGMENTS 12 14 CM_GAMCOR_RAMA_EXP_REGION29_LUT_OFFSET 16 24 CM_GAMCOR_RAMA_EXP_REGION29_NUM_SEGMENTS 28 30 regCM3_CM_GAMCOR_RAMA_REGION_30_31 0 0x11a3 4 0 2 CM_GAMCOR_RAMA_EXP_REGION30_LUT_OFFSET 0 8 CM_GAMCOR_RAMA_EXP_REGION30_NUM_SEGMENTS 12 14 CM_GAMCOR_RAMA_EXP_REGION31_LUT_OFFSET 16 24 CM_GAMCOR_RAMA_EXP_REGION31_NUM_SEGMENTS 28 30 regCM3_CM_GAMCOR_RAMA_REGION_32_33 0 0x11a4 4 0 2 CM_GAMCOR_RAMA_EXP_REGION32_LUT_OFFSET 0 8 CM_GAMCOR_RAMA_EXP_REGION32_NUM_SEGMENTS 12 14 CM_GAMCOR_RAMA_EXP_REGION33_LUT_OFFSET 16 24 CM_GAMCOR_RAMA_EXP_REGION33_NUM_SEGMENTS 28 30 regCM3_CM_GAMCOR_RAMB_START_CNTL_B 0 0x11a5 2 0 2 CM_GAMCOR_RAMB_EXP_REGION_START_B 0 17 CM_GAMCOR_RAMB_EXP_REGION_START_SEGMENT_B 20 26 regCM3_CM_GAMCOR_RAMB_START_CNTL_G 0 0x11a6 2 0 2 CM_GAMCOR_RAMB_EXP_REGION_START_G 0 17 CM_GAMCOR_RAMB_EXP_REGION_START_SEGMENT_G 20 26 regCM3_CM_GAMCOR_RAMB_START_CNTL_R 0 0x11a7 2 0 2 CM_GAMCOR_RAMB_EXP_REGION_START_R 0 17 CM_GAMCOR_RAMB_EXP_REGION_START_SEGMENT_R 20 26 regCM3_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B 0 0x11a8 1 0 2 CM_GAMCOR_RAMB_EXP_REGION_START_SLOPE_B 0 17 regCM3_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G 0 0x11a9 1 0 2 CM_GAMCOR_RAMB_EXP_REGION_START_SLOPE_G 0 17 regCM3_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R 0 0x11aa 1 0 2 CM_GAMCOR_RAMB_EXP_REGION_START_SLOPE_R 0 17 regCM3_CM_GAMCOR_RAMB_START_BASE_CNTL_B 0 0x11ab 1 0 2 CM_GAMCOR_RAMB_EXP_REGION_START_BASE_B 0 17 regCM3_CM_GAMCOR_RAMB_START_BASE_CNTL_G 0 0x11ac 1 0 2 CM_GAMCOR_RAMB_EXP_REGION_START_BASE_G 0 17 regCM3_CM_GAMCOR_RAMB_START_BASE_CNTL_R 0 0x11ad 1 0 2 CM_GAMCOR_RAMB_EXP_REGION_START_BASE_R 0 17 regCM3_CM_GAMCOR_RAMB_END_CNTL1_B 0 0x11ae 1 0 2 CM_GAMCOR_RAMB_EXP_REGION_END_BASE_B 0 17 regCM3_CM_GAMCOR_RAMB_END_CNTL2_B 0 0x11af 2 0 2 CM_GAMCOR_RAMB_EXP_REGION_END_B 0 15 CM_GAMCOR_RAMB_EXP_REGION_END_SLOPE_B 16 31 regCM3_CM_GAMCOR_RAMB_END_CNTL1_G 0 0x11b0 1 0 2 CM_GAMCOR_RAMB_EXP_REGION_END_BASE_G 0 17 regCM3_CM_GAMCOR_RAMB_END_CNTL2_G 0 0x11b1 2 0 2 CM_GAMCOR_RAMB_EXP_REGION_END_G 0 15 CM_GAMCOR_RAMB_EXP_REGION_END_SLOPE_G 16 31 regCM3_CM_GAMCOR_RAMB_END_CNTL1_R 0 0x11b2 1 0 2 CM_GAMCOR_RAMB_EXP_REGION_END_BASE_R 0 17 regCM3_CM_GAMCOR_RAMB_END_CNTL2_R 0 0x11b3 2 0 2 CM_GAMCOR_RAMB_EXP_REGION_END_R 0 15 CM_GAMCOR_RAMB_EXP_REGION_END_SLOPE_R 16 31 regCM3_CM_GAMCOR_RAMB_OFFSET_B 0 0x11b4 1 0 2 CM_GAMCOR_RAMB_OFFSET_B 0 18 regCM3_CM_GAMCOR_RAMB_OFFSET_G 0 0x11b5 1 0 2 CM_GAMCOR_RAMB_OFFSET_G 0 18 regCM3_CM_GAMCOR_RAMB_OFFSET_R 0 0x11b6 1 0 2 CM_GAMCOR_RAMB_OFFSET_R 0 18 regCM3_CM_GAMCOR_RAMB_REGION_0_1 0 0x11b7 4 0 2 CM_GAMCOR_RAMB_EXP_REGION0_LUT_OFFSET 0 8 CM_GAMCOR_RAMB_EXP_REGION0_NUM_SEGMENTS 12 14 CM_GAMCOR_RAMB_EXP_REGION1_LUT_OFFSET 16 24 CM_GAMCOR_RAMB_EXP_REGION1_NUM_SEGMENTS 28 30 regCM3_CM_GAMCOR_RAMB_REGION_2_3 0 0x11b8 4 0 2 CM_GAMCOR_RAMB_EXP_REGION2_LUT_OFFSET 0 8 CM_GAMCOR_RAMB_EXP_REGION2_NUM_SEGMENTS 12 14 CM_GAMCOR_RAMB_EXP_REGION3_LUT_OFFSET 16 24 CM_GAMCOR_RAMB_EXP_REGION3_NUM_SEGMENTS 28 30 regCM3_CM_GAMCOR_RAMB_REGION_4_5 0 0x11b9 4 0 2 CM_GAMCOR_RAMB_EXP_REGION4_LUT_OFFSET 0 8 CM_GAMCOR_RAMB_EXP_REGION4_NUM_SEGMENTS 12 14 CM_GAMCOR_RAMB_EXP_REGION5_LUT_OFFSET 16 24 CM_GAMCOR_RAMB_EXP_REGION5_NUM_SEGMENTS 28 30 regCM3_CM_GAMCOR_RAMB_REGION_6_7 0 0x11ba 4 0 2 CM_GAMCOR_RAMB_EXP_REGION6_LUT_OFFSET 0 8 CM_GAMCOR_RAMB_EXP_REGION6_NUM_SEGMENTS 12 14 CM_GAMCOR_RAMB_EXP_REGION7_LUT_OFFSET 16 24 CM_GAMCOR_RAMB_EXP_REGION7_NUM_SEGMENTS 28 30 regCM3_CM_GAMCOR_RAMB_REGION_8_9 0 0x11bb 4 0 2 CM_GAMCOR_RAMB_EXP_REGION8_LUT_OFFSET 0 8 CM_GAMCOR_RAMB_EXP_REGION8_NUM_SEGMENTS 12 14 CM_GAMCOR_RAMB_EXP_REGION9_LUT_OFFSET 16 24 CM_GAMCOR_RAMB_EXP_REGION9_NUM_SEGMENTS 28 30 regCM3_CM_GAMCOR_RAMB_REGION_10_11 0 0x11bc 4 0 2 CM_GAMCOR_RAMB_EXP_REGION10_LUT_OFFSET 0 8 CM_GAMCOR_RAMB_EXP_REGION10_NUM_SEGMENTS 12 14 CM_GAMCOR_RAMB_EXP_REGION11_LUT_OFFSET 16 24 CM_GAMCOR_RAMB_EXP_REGION11_NUM_SEGMENTS 28 30 regCM3_CM_GAMCOR_RAMB_REGION_12_13 0 0x11bd 4 0 2 CM_GAMCOR_RAMB_EXP_REGION12_LUT_OFFSET 0 8 CM_GAMCOR_RAMB_EXP_REGION12_NUM_SEGMENTS 12 14 CM_GAMCOR_RAMB_EXP_REGION13_LUT_OFFSET 16 24 CM_GAMCOR_RAMB_EXP_REGION13_NUM_SEGMENTS 28 30 regCM3_CM_GAMCOR_RAMB_REGION_14_15 0 0x11be 4 0 2 CM_GAMCOR_RAMB_EXP_REGION14_LUT_OFFSET 0 8 CM_GAMCOR_RAMB_EXP_REGION14_NUM_SEGMENTS 12 14 CM_GAMCOR_RAMB_EXP_REGION15_LUT_OFFSET 16 24 CM_GAMCOR_RAMB_EXP_REGION15_NUM_SEGMENTS 28 30 regCM3_CM_GAMCOR_RAMB_REGION_16_17 0 0x11bf 4 0 2 CM_GAMCOR_RAMB_EXP_REGION16_LUT_OFFSET 0 8 CM_GAMCOR_RAMB_EXP_REGION16_NUM_SEGMENTS 12 14 CM_GAMCOR_RAMB_EXP_REGION17_LUT_OFFSET 16 24 CM_GAMCOR_RAMB_EXP_REGION17_NUM_SEGMENTS 28 30 regCM3_CM_GAMCOR_RAMB_REGION_18_19 0 0x11c0 4 0 2 CM_GAMCOR_RAMB_EXP_REGION18_LUT_OFFSET 0 8 CM_GAMCOR_RAMB_EXP_REGION18_NUM_SEGMENTS 12 14 CM_GAMCOR_RAMB_EXP_REGION19_LUT_OFFSET 16 24 CM_GAMCOR_RAMB_EXP_REGION19_NUM_SEGMENTS 28 30 regCM3_CM_GAMCOR_RAMB_REGION_20_21 0 0x11c1 4 0 2 CM_GAMCOR_RAMB_EXP_REGION20_LUT_OFFSET 0 8 CM_GAMCOR_RAMB_EXP_REGION20_NUM_SEGMENTS 12 14 CM_GAMCOR_RAMB_EXP_REGION21_LUT_OFFSET 16 24 CM_GAMCOR_RAMB_EXP_REGION21_NUM_SEGMENTS 28 30 regCM3_CM_GAMCOR_RAMB_REGION_22_23 0 0x11c2 4 0 2 CM_GAMCOR_RAMB_EXP_REGION22_LUT_OFFSET 0 8 CM_GAMCOR_RAMB_EXP_REGION22_NUM_SEGMENTS 12 14 CM_GAMCOR_RAMB_EXP_REGION23_LUT_OFFSET 16 24 CM_GAMCOR_RAMB_EXP_REGION23_NUM_SEGMENTS 28 30 regCM3_CM_GAMCOR_RAMB_REGION_24_25 0 0x11c3 4 0 2 CM_GAMCOR_RAMB_EXP_REGION24_LUT_OFFSET 0 8 CM_GAMCOR_RAMB_EXP_REGION24_NUM_SEGMENTS 12 14 CM_GAMCOR_RAMB_EXP_REGION25_LUT_OFFSET 16 24 CM_GAMCOR_RAMB_EXP_REGION25_NUM_SEGMENTS 28 30 regCM3_CM_GAMCOR_RAMB_REGION_26_27 0 0x11c4 4 0 2 CM_GAMCOR_RAMB_EXP_REGION26_LUT_OFFSET 0 8 CM_GAMCOR_RAMB_EXP_REGION26_NUM_SEGMENTS 12 14 CM_GAMCOR_RAMB_EXP_REGION27_LUT_OFFSET 16 24 CM_GAMCOR_RAMB_EXP_REGION27_NUM_SEGMENTS 28 30 regCM3_CM_GAMCOR_RAMB_REGION_28_29 0 0x11c5 4 0 2 CM_GAMCOR_RAMB_EXP_REGION28_LUT_OFFSET 0 8 CM_GAMCOR_RAMB_EXP_REGION28_NUM_SEGMENTS 12 14 CM_GAMCOR_RAMB_EXP_REGION29_LUT_OFFSET 16 24 CM_GAMCOR_RAMB_EXP_REGION29_NUM_SEGMENTS 28 30 regCM3_CM_GAMCOR_RAMB_REGION_30_31 0 0x11c6 4 0 2 CM_GAMCOR_RAMB_EXP_REGION30_LUT_OFFSET 0 8 CM_GAMCOR_RAMB_EXP_REGION30_NUM_SEGMENTS 12 14 CM_GAMCOR_RAMB_EXP_REGION31_LUT_OFFSET 16 24 CM_GAMCOR_RAMB_EXP_REGION31_NUM_SEGMENTS 28 30 regCM3_CM_GAMCOR_RAMB_REGION_32_33 0 0x11c7 4 0 2 CM_GAMCOR_RAMB_EXP_REGION32_LUT_OFFSET 0 8 CM_GAMCOR_RAMB_EXP_REGION32_NUM_SEGMENTS 12 14 CM_GAMCOR_RAMB_EXP_REGION33_LUT_OFFSET 16 24 CM_GAMCOR_RAMB_EXP_REGION33_NUM_SEGMENTS 28 30 regCM3_CM_BLNDGAM_CONTROL 0 0x11c8 5 0 2 CM_BLNDGAM_MODE 0 1 CM_BLNDGAM_SELECT 2 2 CM_BLNDGAM_PWL_DISABLE 3 3 CM_BLNDGAM_MODE_CURRENT 4 5 CM_BLNDGAM_SELECT_CURRENT 6 6 regCM3_CM_BLNDGAM_LUT_INDEX 0 0x11c9 1 0 2 CM_BLNDGAM_LUT_INDEX 0 8 regCM3_CM_BLNDGAM_LUT_DATA 0 0x11ca 1 0 2 CM_BLNDGAM_LUT_DATA 0 17 regCM3_CM_BLNDGAM_LUT_CONTROL 0 0x11cb 5 0 2 CM_BLNDGAM_LUT_WRITE_COLOR_MASK 0 2 CM_BLNDGAM_LUT_READ_COLOR_SEL 3 4 CM_BLNDGAM_LUT_READ_DBG 5 5 CM_BLNDGAM_LUT_HOST_SEL 6 6 CM_BLNDGAM_LUT_CONFIG_MODE 7 7 regCM3_CM_BLNDGAM_RAMA_START_CNTL_B 0 0x11cc 2 0 2 CM_BLNDGAM_RAMA_EXP_REGION_START_B 0 17 CM_BLNDGAM_RAMA_EXP_REGION_START_SEGMENT_B 20 26 regCM3_CM_BLNDGAM_RAMA_START_CNTL_G 0 0x11cd 2 0 2 CM_BLNDGAM_RAMA_EXP_REGION_START_G 0 17 CM_BLNDGAM_RAMA_EXP_REGION_START_SEGMENT_G 20 26 regCM3_CM_BLNDGAM_RAMA_START_CNTL_R 0 0x11ce 2 0 2 CM_BLNDGAM_RAMA_EXP_REGION_START_R 0 17 CM_BLNDGAM_RAMA_EXP_REGION_START_SEGMENT_R 20 26 regCM3_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_B 0 0x11cf 1 0 2 CM_BLNDGAM_RAMA_EXP_REGION_START_SLOPE_B 0 17 regCM3_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_G 0 0x11d0 1 0 2 CM_BLNDGAM_RAMA_EXP_REGION_START_SLOPE_G 0 17 regCM3_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_R 0 0x11d1 1 0 2 CM_BLNDGAM_RAMA_EXP_REGION_START_SLOPE_R 0 17 regCM3_CM_BLNDGAM_RAMA_START_BASE_CNTL_B 0 0x11d2 1 0 2 CM_BLNDGAM_RAMA_EXP_REGION_START_BASE_B 0 17 regCM3_CM_BLNDGAM_RAMA_START_BASE_CNTL_G 0 0x11d3 1 0 2 CM_BLNDGAM_RAMA_EXP_REGION_START_BASE_G 0 17 regCM3_CM_BLNDGAM_RAMA_START_BASE_CNTL_R 0 0x11d4 1 0 2 CM_BLNDGAM_RAMA_EXP_REGION_START_BASE_R 0 17 regCM3_CM_BLNDGAM_RAMA_END_CNTL1_B 0 0x11d5 1 0 2 CM_BLNDGAM_RAMA_EXP_REGION_END_BASE_B 0 17 regCM3_CM_BLNDGAM_RAMA_END_CNTL2_B 0 0x11d6 2 0 2 CM_BLNDGAM_RAMA_EXP_REGION_END_B 0 15 CM_BLNDGAM_RAMA_EXP_REGION_END_SLOPE_B 16 31 regCM3_CM_BLNDGAM_RAMA_END_CNTL1_G 0 0x11d7 1 0 2 CM_BLNDGAM_RAMA_EXP_REGION_END_BASE_G 0 17 regCM3_CM_BLNDGAM_RAMA_END_CNTL2_G 0 0x11d8 2 0 2 CM_BLNDGAM_RAMA_EXP_REGION_END_G 0 15 CM_BLNDGAM_RAMA_EXP_REGION_END_SLOPE_G 16 31 regCM3_CM_BLNDGAM_RAMA_END_CNTL1_R 0 0x11d9 1 0 2 CM_BLNDGAM_RAMA_EXP_REGION_END_BASE_R 0 17 regCM3_CM_BLNDGAM_RAMA_END_CNTL2_R 0 0x11da 2 0 2 CM_BLNDGAM_RAMA_EXP_REGION_END_R 0 15 CM_BLNDGAM_RAMA_EXP_REGION_END_SLOPE_R 16 31 regCM3_CM_BLNDGAM_RAMA_OFFSET_B 0 0x11db 1 0 2 CM_BLNDGAM_RAMA_OFFSET_B 0 18 regCM3_CM_BLNDGAM_RAMA_OFFSET_G 0 0x11dc 1 0 2 CM_BLNDGAM_RAMA_OFFSET_G 0 18 regCM3_CM_BLNDGAM_RAMA_OFFSET_R 0 0x11dd 1 0 2 CM_BLNDGAM_RAMA_OFFSET_R 0 18 regCM3_CM_BLNDGAM_RAMA_REGION_0_1 0 0x11de 4 0 2 CM_BLNDGAM_RAMA_EXP_REGION0_LUT_OFFSET 0 8 CM_BLNDGAM_RAMA_EXP_REGION0_NUM_SEGMENTS 12 14 CM_BLNDGAM_RAMA_EXP_REGION1_LUT_OFFSET 16 24 CM_BLNDGAM_RAMA_EXP_REGION1_NUM_SEGMENTS 28 30 regCM3_CM_BLNDGAM_RAMA_REGION_2_3 0 0x11df 4 0 2 CM_BLNDGAM_RAMA_EXP_REGION2_LUT_OFFSET 0 8 CM_BLNDGAM_RAMA_EXP_REGION2_NUM_SEGMENTS 12 14 CM_BLNDGAM_RAMA_EXP_REGION3_LUT_OFFSET 16 24 CM_BLNDGAM_RAMA_EXP_REGION3_NUM_SEGMENTS 28 30 regCM3_CM_BLNDGAM_RAMA_REGION_4_5 0 0x11e0 4 0 2 CM_BLNDGAM_RAMA_EXP_REGION4_LUT_OFFSET 0 8 CM_BLNDGAM_RAMA_EXP_REGION4_NUM_SEGMENTS 12 14 CM_BLNDGAM_RAMA_EXP_REGION5_LUT_OFFSET 16 24 CM_BLNDGAM_RAMA_EXP_REGION5_NUM_SEGMENTS 28 30 regCM3_CM_BLNDGAM_RAMA_REGION_6_7 0 0x11e1 4 0 2 CM_BLNDGAM_RAMA_EXP_REGION6_LUT_OFFSET 0 8 CM_BLNDGAM_RAMA_EXP_REGION6_NUM_SEGMENTS 12 14 CM_BLNDGAM_RAMA_EXP_REGION7_LUT_OFFSET 16 24 CM_BLNDGAM_RAMA_EXP_REGION7_NUM_SEGMENTS 28 30 regCM3_CM_BLNDGAM_RAMA_REGION_8_9 0 0x11e2 4 0 2 CM_BLNDGAM_RAMA_EXP_REGION8_LUT_OFFSET 0 8 CM_BLNDGAM_RAMA_EXP_REGION8_NUM_SEGMENTS 12 14 CM_BLNDGAM_RAMA_EXP_REGION9_LUT_OFFSET 16 24 CM_BLNDGAM_RAMA_EXP_REGION9_NUM_SEGMENTS 28 30 regCM3_CM_BLNDGAM_RAMA_REGION_10_11 0 0x11e3 4 0 2 CM_BLNDGAM_RAMA_EXP_REGION10_LUT_OFFSET 0 8 CM_BLNDGAM_RAMA_EXP_REGION10_NUM_SEGMENTS 12 14 CM_BLNDGAM_RAMA_EXP_REGION11_LUT_OFFSET 16 24 CM_BLNDGAM_RAMA_EXP_REGION11_NUM_SEGMENTS 28 30 regCM3_CM_BLNDGAM_RAMA_REGION_12_13 0 0x11e4 4 0 2 CM_BLNDGAM_RAMA_EXP_REGION12_LUT_OFFSET 0 8 CM_BLNDGAM_RAMA_EXP_REGION12_NUM_SEGMENTS 12 14 CM_BLNDGAM_RAMA_EXP_REGION13_LUT_OFFSET 16 24 CM_BLNDGAM_RAMA_EXP_REGION13_NUM_SEGMENTS 28 30 regCM3_CM_BLNDGAM_RAMA_REGION_14_15 0 0x11e5 4 0 2 CM_BLNDGAM_RAMA_EXP_REGION14_LUT_OFFSET 0 8 CM_BLNDGAM_RAMA_EXP_REGION14_NUM_SEGMENTS 12 14 CM_BLNDGAM_RAMA_EXP_REGION15_LUT_OFFSET 16 24 CM_BLNDGAM_RAMA_EXP_REGION15_NUM_SEGMENTS 28 30 regCM3_CM_BLNDGAM_RAMA_REGION_16_17 0 0x11e6 4 0 2 CM_BLNDGAM_RAMA_EXP_REGION16_LUT_OFFSET 0 8 CM_BLNDGAM_RAMA_EXP_REGION16_NUM_SEGMENTS 12 14 CM_BLNDGAM_RAMA_EXP_REGION17_LUT_OFFSET 16 24 CM_BLNDGAM_RAMA_EXP_REGION17_NUM_SEGMENTS 28 30 regCM3_CM_BLNDGAM_RAMA_REGION_18_19 0 0x11e7 4 0 2 CM_BLNDGAM_RAMA_EXP_REGION18_LUT_OFFSET 0 8 CM_BLNDGAM_RAMA_EXP_REGION18_NUM_SEGMENTS 12 14 CM_BLNDGAM_RAMA_EXP_REGION19_LUT_OFFSET 16 24 CM_BLNDGAM_RAMA_EXP_REGION19_NUM_SEGMENTS 28 30 regCM3_CM_BLNDGAM_RAMA_REGION_20_21 0 0x11e8 4 0 2 CM_BLNDGAM_RAMA_EXP_REGION20_LUT_OFFSET 0 8 CM_BLNDGAM_RAMA_EXP_REGION20_NUM_SEGMENTS 12 14 CM_BLNDGAM_RAMA_EXP_REGION21_LUT_OFFSET 16 24 CM_BLNDGAM_RAMA_EXP_REGION21_NUM_SEGMENTS 28 30 regCM3_CM_BLNDGAM_RAMA_REGION_22_23 0 0x11e9 4 0 2 CM_BLNDGAM_RAMA_EXP_REGION22_LUT_OFFSET 0 8 CM_BLNDGAM_RAMA_EXP_REGION22_NUM_SEGMENTS 12 14 CM_BLNDGAM_RAMA_EXP_REGION23_LUT_OFFSET 16 24 CM_BLNDGAM_RAMA_EXP_REGION23_NUM_SEGMENTS 28 30 regCM3_CM_BLNDGAM_RAMA_REGION_24_25 0 0x11ea 4 0 2 CM_BLNDGAM_RAMA_EXP_REGION24_LUT_OFFSET 0 8 CM_BLNDGAM_RAMA_EXP_REGION24_NUM_SEGMENTS 12 14 CM_BLNDGAM_RAMA_EXP_REGION25_LUT_OFFSET 16 24 CM_BLNDGAM_RAMA_EXP_REGION25_NUM_SEGMENTS 28 30 regCM3_CM_BLNDGAM_RAMA_REGION_26_27 0 0x11eb 4 0 2 CM_BLNDGAM_RAMA_EXP_REGION26_LUT_OFFSET 0 8 CM_BLNDGAM_RAMA_EXP_REGION26_NUM_SEGMENTS 12 14 CM_BLNDGAM_RAMA_EXP_REGION27_LUT_OFFSET 16 24 CM_BLNDGAM_RAMA_EXP_REGION27_NUM_SEGMENTS 28 30 regCM3_CM_BLNDGAM_RAMA_REGION_28_29 0 0x11ec 4 0 2 CM_BLNDGAM_RAMA_EXP_REGION28_LUT_OFFSET 0 8 CM_BLNDGAM_RAMA_EXP_REGION28_NUM_SEGMENTS 12 14 CM_BLNDGAM_RAMA_EXP_REGION29_LUT_OFFSET 16 24 CM_BLNDGAM_RAMA_EXP_REGION29_NUM_SEGMENTS 28 30 regCM3_CM_BLNDGAM_RAMA_REGION_30_31 0 0x11ed 4 0 2 CM_BLNDGAM_RAMA_EXP_REGION30_LUT_OFFSET 0 8 CM_BLNDGAM_RAMA_EXP_REGION30_NUM_SEGMENTS 12 14 CM_BLNDGAM_RAMA_EXP_REGION31_LUT_OFFSET 16 24 CM_BLNDGAM_RAMA_EXP_REGION31_NUM_SEGMENTS 28 30 regCM3_CM_BLNDGAM_RAMA_REGION_32_33 0 0x11ee 4 0 2 CM_BLNDGAM_RAMA_EXP_REGION32_LUT_OFFSET 0 8 CM_BLNDGAM_RAMA_EXP_REGION32_NUM_SEGMENTS 12 14 CM_BLNDGAM_RAMA_EXP_REGION33_LUT_OFFSET 16 24 CM_BLNDGAM_RAMA_EXP_REGION33_NUM_SEGMENTS 28 30 regCM3_CM_BLNDGAM_RAMB_START_CNTL_B 0 0x11ef 2 0 2 CM_BLNDGAM_RAMB_EXP_REGION_START_B 0 17 CM_BLNDGAM_RAMB_EXP_REGION_START_SEGMENT_B 20 26 regCM3_CM_BLNDGAM_RAMB_START_CNTL_G 0 0x11f0 2 0 2 CM_BLNDGAM_RAMB_EXP_REGION_START_G 0 17 CM_BLNDGAM_RAMB_EXP_REGION_START_SEGMENT_G 20 26 regCM3_CM_BLNDGAM_RAMB_START_CNTL_R 0 0x11f1 2 0 2 CM_BLNDGAM_RAMB_EXP_REGION_START_R 0 17 CM_BLNDGAM_RAMB_EXP_REGION_START_SEGMENT_R 20 26 regCM3_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_B 0 0x11f2 1 0 2 CM_BLNDGAM_RAMB_EXP_REGION_START_SLOPE_B 0 17 regCM3_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_G 0 0x11f3 1 0 2 CM_BLNDGAM_RAMB_EXP_REGION_START_SLOPE_G 0 17 regCM3_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_R 0 0x11f4 1 0 2 CM_BLNDGAM_RAMB_EXP_REGION_START_SLOPE_R 0 17 regCM3_CM_BLNDGAM_RAMB_START_BASE_CNTL_B 0 0x11f5 1 0 2 CM_BLNDGAM_RAMB_EXP_REGION_START_BASE_B 0 17 regCM3_CM_BLNDGAM_RAMB_START_BASE_CNTL_G 0 0x11f6 1 0 2 CM_BLNDGAM_RAMB_EXP_REGION_START_BASE_G 0 17 regCM3_CM_BLNDGAM_RAMB_START_BASE_CNTL_R 0 0x11f7 1 0 2 CM_BLNDGAM_RAMB_EXP_REGION_START_BASE_R 0 17 regCM3_CM_BLNDGAM_RAMB_END_CNTL1_B 0 0x11f8 1 0 2 CM_BLNDGAM_RAMB_EXP_REGION_END_BASE_B 0 17 regCM3_CM_BLNDGAM_RAMB_END_CNTL2_B 0 0x11f9 2 0 2 CM_BLNDGAM_RAMB_EXP_REGION_END_B 0 15 CM_BLNDGAM_RAMB_EXP_REGION_END_SLOPE_B 16 31 regCM3_CM_BLNDGAM_RAMB_END_CNTL1_G 0 0x11fa 1 0 2 CM_BLNDGAM_RAMB_EXP_REGION_END_BASE_G 0 17 regCM3_CM_BLNDGAM_RAMB_END_CNTL2_G 0 0x11fb 2 0 2 CM_BLNDGAM_RAMB_EXP_REGION_END_G 0 15 CM_BLNDGAM_RAMB_EXP_REGION_END_SLOPE_G 16 31 regCM3_CM_BLNDGAM_RAMB_END_CNTL1_R 0 0x11fc 1 0 2 CM_BLNDGAM_RAMB_EXP_REGION_END_BASE_R 0 17 regCM3_CM_BLNDGAM_RAMB_END_CNTL2_R 0 0x11fd 2 0 2 CM_BLNDGAM_RAMB_EXP_REGION_END_R 0 15 CM_BLNDGAM_RAMB_EXP_REGION_END_SLOPE_R 16 31 regCM3_CM_BLNDGAM_RAMB_OFFSET_B 0 0x11fe 1 0 2 CM_BLNDGAM_RAMB_OFFSET_B 0 18 regCM3_CM_BLNDGAM_RAMB_OFFSET_G 0 0x11ff 1 0 2 CM_BLNDGAM_RAMB_OFFSET_G 0 18 regCM3_CM_BLNDGAM_RAMB_OFFSET_R 0 0x1200 1 0 2 CM_BLNDGAM_RAMB_OFFSET_R 0 18 regCM3_CM_BLNDGAM_RAMB_REGION_0_1 0 0x1201 4 0 2 CM_BLNDGAM_RAMB_EXP_REGION0_LUT_OFFSET 0 8 CM_BLNDGAM_RAMB_EXP_REGION0_NUM_SEGMENTS 12 14 CM_BLNDGAM_RAMB_EXP_REGION1_LUT_OFFSET 16 24 CM_BLNDGAM_RAMB_EXP_REGION1_NUM_SEGMENTS 28 30 regCM3_CM_BLNDGAM_RAMB_REGION_2_3 0 0x1202 4 0 2 CM_BLNDGAM_RAMB_EXP_REGION2_LUT_OFFSET 0 8 CM_BLNDGAM_RAMB_EXP_REGION2_NUM_SEGMENTS 12 14 CM_BLNDGAM_RAMB_EXP_REGION3_LUT_OFFSET 16 24 CM_BLNDGAM_RAMB_EXP_REGION3_NUM_SEGMENTS 28 30 regCM3_CM_BLNDGAM_RAMB_REGION_4_5 0 0x1203 4 0 2 CM_BLNDGAM_RAMB_EXP_REGION4_LUT_OFFSET 0 8 CM_BLNDGAM_RAMB_EXP_REGION4_NUM_SEGMENTS 12 14 CM_BLNDGAM_RAMB_EXP_REGION5_LUT_OFFSET 16 24 CM_BLNDGAM_RAMB_EXP_REGION5_NUM_SEGMENTS 28 30 regCM3_CM_BLNDGAM_RAMB_REGION_6_7 0 0x1204 4 0 2 CM_BLNDGAM_RAMB_EXP_REGION6_LUT_OFFSET 0 8 CM_BLNDGAM_RAMB_EXP_REGION6_NUM_SEGMENTS 12 14 CM_BLNDGAM_RAMB_EXP_REGION7_LUT_OFFSET 16 24 CM_BLNDGAM_RAMB_EXP_REGION7_NUM_SEGMENTS 28 30 regCM3_CM_BLNDGAM_RAMB_REGION_8_9 0 0x1205 4 0 2 CM_BLNDGAM_RAMB_EXP_REGION8_LUT_OFFSET 0 8 CM_BLNDGAM_RAMB_EXP_REGION8_NUM_SEGMENTS 12 14 CM_BLNDGAM_RAMB_EXP_REGION9_LUT_OFFSET 16 24 CM_BLNDGAM_RAMB_EXP_REGION9_NUM_SEGMENTS 28 30 regCM3_CM_BLNDGAM_RAMB_REGION_10_11 0 0x1206 4 0 2 CM_BLNDGAM_RAMB_EXP_REGION10_LUT_OFFSET 0 8 CM_BLNDGAM_RAMB_EXP_REGION10_NUM_SEGMENTS 12 14 CM_BLNDGAM_RAMB_EXP_REGION11_LUT_OFFSET 16 24 CM_BLNDGAM_RAMB_EXP_REGION11_NUM_SEGMENTS 28 30 regCM3_CM_BLNDGAM_RAMB_REGION_12_13 0 0x1207 4 0 2 CM_BLNDGAM_RAMB_EXP_REGION12_LUT_OFFSET 0 8 CM_BLNDGAM_RAMB_EXP_REGION12_NUM_SEGMENTS 12 14 CM_BLNDGAM_RAMB_EXP_REGION13_LUT_OFFSET 16 24 CM_BLNDGAM_RAMB_EXP_REGION13_NUM_SEGMENTS 28 30 regCM3_CM_BLNDGAM_RAMB_REGION_14_15 0 0x1208 4 0 2 CM_BLNDGAM_RAMB_EXP_REGION14_LUT_OFFSET 0 8 CM_BLNDGAM_RAMB_EXP_REGION14_NUM_SEGMENTS 12 14 CM_BLNDGAM_RAMB_EXP_REGION15_LUT_OFFSET 16 24 CM_BLNDGAM_RAMB_EXP_REGION15_NUM_SEGMENTS 28 30 regCM3_CM_BLNDGAM_RAMB_REGION_16_17 0 0x1209 4 0 2 CM_BLNDGAM_RAMB_EXP_REGION16_LUT_OFFSET 0 8 CM_BLNDGAM_RAMB_EXP_REGION16_NUM_SEGMENTS 12 14 CM_BLNDGAM_RAMB_EXP_REGION17_LUT_OFFSET 16 24 CM_BLNDGAM_RAMB_EXP_REGION17_NUM_SEGMENTS 28 30 regCM3_CM_BLNDGAM_RAMB_REGION_18_19 0 0x120a 4 0 2 CM_BLNDGAM_RAMB_EXP_REGION18_LUT_OFFSET 0 8 CM_BLNDGAM_RAMB_EXP_REGION18_NUM_SEGMENTS 12 14 CM_BLNDGAM_RAMB_EXP_REGION19_LUT_OFFSET 16 24 CM_BLNDGAM_RAMB_EXP_REGION19_NUM_SEGMENTS 28 30 regCM3_CM_BLNDGAM_RAMB_REGION_20_21 0 0x120b 4 0 2 CM_BLNDGAM_RAMB_EXP_REGION20_LUT_OFFSET 0 8 CM_BLNDGAM_RAMB_EXP_REGION20_NUM_SEGMENTS 12 14 CM_BLNDGAM_RAMB_EXP_REGION21_LUT_OFFSET 16 24 CM_BLNDGAM_RAMB_EXP_REGION21_NUM_SEGMENTS 28 30 regCM3_CM_BLNDGAM_RAMB_REGION_22_23 0 0x120c 4 0 2 CM_BLNDGAM_RAMB_EXP_REGION22_LUT_OFFSET 0 8 CM_BLNDGAM_RAMB_EXP_REGION22_NUM_SEGMENTS 12 14 CM_BLNDGAM_RAMB_EXP_REGION23_LUT_OFFSET 16 24 CM_BLNDGAM_RAMB_EXP_REGION23_NUM_SEGMENTS 28 30 regCM3_CM_BLNDGAM_RAMB_REGION_24_25 0 0x120d 4 0 2 CM_BLNDGAM_RAMB_EXP_REGION24_LUT_OFFSET 0 8 CM_BLNDGAM_RAMB_EXP_REGION24_NUM_SEGMENTS 12 14 CM_BLNDGAM_RAMB_EXP_REGION25_LUT_OFFSET 16 24 CM_BLNDGAM_RAMB_EXP_REGION25_NUM_SEGMENTS 28 30 regCM3_CM_BLNDGAM_RAMB_REGION_26_27 0 0x120e 4 0 2 CM_BLNDGAM_RAMB_EXP_REGION26_LUT_OFFSET 0 8 CM_BLNDGAM_RAMB_EXP_REGION26_NUM_SEGMENTS 12 14 CM_BLNDGAM_RAMB_EXP_REGION27_LUT_OFFSET 16 24 CM_BLNDGAM_RAMB_EXP_REGION27_NUM_SEGMENTS 28 30 regCM3_CM_BLNDGAM_RAMB_REGION_28_29 0 0x120f 4 0 2 CM_BLNDGAM_RAMB_EXP_REGION28_LUT_OFFSET 0 8 CM_BLNDGAM_RAMB_EXP_REGION28_NUM_SEGMENTS 12 14 CM_BLNDGAM_RAMB_EXP_REGION29_LUT_OFFSET 16 24 CM_BLNDGAM_RAMB_EXP_REGION29_NUM_SEGMENTS 28 30 regCM3_CM_BLNDGAM_RAMB_REGION_30_31 0 0x1210 4 0 2 CM_BLNDGAM_RAMB_EXP_REGION30_LUT_OFFSET 0 8 CM_BLNDGAM_RAMB_EXP_REGION30_NUM_SEGMENTS 12 14 CM_BLNDGAM_RAMB_EXP_REGION31_LUT_OFFSET 16 24 CM_BLNDGAM_RAMB_EXP_REGION31_NUM_SEGMENTS 28 30 regCM3_CM_BLNDGAM_RAMB_REGION_32_33 0 0x1211 4 0 2 CM_BLNDGAM_RAMB_EXP_REGION32_LUT_OFFSET 0 8 CM_BLNDGAM_RAMB_EXP_REGION32_NUM_SEGMENTS 12 14 CM_BLNDGAM_RAMB_EXP_REGION33_LUT_OFFSET 16 24 CM_BLNDGAM_RAMB_EXP_REGION33_NUM_SEGMENTS 28 30 regCM3_CM_HDR_MULT_COEF 0 0x1212 1 0 2 CM_HDR_MULT_COEF 0 18 regCM3_CM_MEM_PWR_CTRL 0 0x1213 4 0 2 GAMCOR_MEM_PWR_FORCE 0 1 GAMCOR_MEM_PWR_DIS 2 2 BLNDGAM_MEM_PWR_FORCE 4 5 BLNDGAM_MEM_PWR_DIS 6 6 regCM3_CM_MEM_PWR_STATUS 0 0x1214 2 0 2 GAMCOR_MEM_PWR_STATE 0 1 BLNDGAM_MEM_PWR_STATE 2 3 regCM3_CM_DEALPHA 0 0x1216 2 0 2 CM_DEALPHA_EN 0 0 CM_DEALPHA_ABLND 1 1 regCM3_CM_COEF_FORMAT 0 0x1217 3 0 2 CM_BIAS_FORMAT 0 0 CM_POST_CSC_COEF_FORMAT 4 4 CM_GAMUT_REMAP_COEF_FORMAT 8 8 regCM3_CM_SHAPER_CONTROL 0 0x1218 2 0 2 CM_SHAPER_LUT_MODE 0 1 CM_SHAPER_MODE_CURRENT 2 3 regCM3_CM_SHAPER_OFFSET_R 0 0x1219 1 0 2 CM_SHAPER_OFFSET_R 0 18 regCM3_CM_SHAPER_OFFSET_G 0 0x121a 1 0 2 CM_SHAPER_OFFSET_G 0 18 regCM3_CM_SHAPER_OFFSET_B 0 0x121b 1 0 2 CM_SHAPER_OFFSET_B 0 18 regCM3_CM_SHAPER_SCALE_R 0 0x121c 1 0 2 CM_SHAPER_SCALE_R 0 15 regCM3_CM_SHAPER_SCALE_G_B 0 0x121d 2 0 2 CM_SHAPER_SCALE_G 0 15 CM_SHAPER_SCALE_B 16 31 regCM3_CM_SHAPER_LUT_INDEX 0 0x121e 1 0 2 CM_SHAPER_LUT_INDEX 0 7 regCM3_CM_SHAPER_LUT_DATA 0 0x121f 1 0 2 CM_SHAPER_LUT_DATA 0 23 regCM3_CM_SHAPER_LUT_WRITE_EN_MASK 0 0x1220 2 0 2 CM_SHAPER_LUT_WRITE_EN_MASK 0 2 CM_SHAPER_LUT_WRITE_SEL 4 4 regCM3_CM_SHAPER_RAMA_START_CNTL_B 0 0x1221 2 0 2 CM_SHAPER_RAMA_EXP_REGION_START_B 0 17 CM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_B 20 26 regCM3_CM_SHAPER_RAMA_START_CNTL_G 0 0x1222 2 0 2 CM_SHAPER_RAMA_EXP_REGION_START_G 0 17 CM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_G 20 26 regCM3_CM_SHAPER_RAMA_START_CNTL_R 0 0x1223 2 0 2 CM_SHAPER_RAMA_EXP_REGION_START_R 0 17 CM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_R 20 26 regCM3_CM_SHAPER_RAMA_END_CNTL_B 0 0x1224 2 0 2 CM_SHAPER_RAMA_EXP_REGION_END_B 0 15 CM_SHAPER_RAMA_EXP_REGION_END_BASE_B 16 29 regCM3_CM_SHAPER_RAMA_END_CNTL_G 0 0x1225 2 0 2 CM_SHAPER_RAMA_EXP_REGION_END_G 0 15 CM_SHAPER_RAMA_EXP_REGION_END_BASE_G 16 29 regCM3_CM_SHAPER_RAMA_END_CNTL_R 0 0x1226 2 0 2 CM_SHAPER_RAMA_EXP_REGION_END_R 0 15 CM_SHAPER_RAMA_EXP_REGION_END_BASE_R 16 29 regCM3_CM_SHAPER_RAMA_REGION_0_1 0 0x1227 4 0 2 CM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET 0 8 CM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS 12 14 CM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET 16 24 CM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS 28 30 regCM3_CM_SHAPER_RAMA_REGION_2_3 0 0x1228 4 0 2 CM_SHAPER_RAMA_EXP_REGION2_LUT_OFFSET 0 8 CM_SHAPER_RAMA_EXP_REGION2_NUM_SEGMENTS 12 14 CM_SHAPER_RAMA_EXP_REGION3_LUT_OFFSET 16 24 CM_SHAPER_RAMA_EXP_REGION3_NUM_SEGMENTS 28 30 regCM3_CM_SHAPER_RAMA_REGION_4_5 0 0x1229 4 0 2 CM_SHAPER_RAMA_EXP_REGION4_LUT_OFFSET 0 8 CM_SHAPER_RAMA_EXP_REGION4_NUM_SEGMENTS 12 14 CM_SHAPER_RAMA_EXP_REGION5_LUT_OFFSET 16 24 CM_SHAPER_RAMA_EXP_REGION5_NUM_SEGMENTS 28 30 regCM3_CM_SHAPER_RAMA_REGION_6_7 0 0x122a 4 0 2 CM_SHAPER_RAMA_EXP_REGION6_LUT_OFFSET 0 8 CM_SHAPER_RAMA_EXP_REGION6_NUM_SEGMENTS 12 14 CM_SHAPER_RAMA_EXP_REGION7_LUT_OFFSET 16 24 CM_SHAPER_RAMA_EXP_REGION7_NUM_SEGMENTS 28 30 regCM3_CM_SHAPER_RAMA_REGION_8_9 0 0x122b 4 0 2 CM_SHAPER_RAMA_EXP_REGION8_LUT_OFFSET 0 8 CM_SHAPER_RAMA_EXP_REGION8_NUM_SEGMENTS 12 14 CM_SHAPER_RAMA_EXP_REGION9_LUT_OFFSET 16 24 CM_SHAPER_RAMA_EXP_REGION9_NUM_SEGMENTS 28 30 regCM3_CM_SHAPER_RAMA_REGION_10_11 0 0x122c 4 0 2 CM_SHAPER_RAMA_EXP_REGION10_LUT_OFFSET 0 8 CM_SHAPER_RAMA_EXP_REGION10_NUM_SEGMENTS 12 14 CM_SHAPER_RAMA_EXP_REGION11_LUT_OFFSET 16 24 CM_SHAPER_RAMA_EXP_REGION11_NUM_SEGMENTS 28 30 regCM3_CM_SHAPER_RAMA_REGION_12_13 0 0x122d 4 0 2 CM_SHAPER_RAMA_EXP_REGION12_LUT_OFFSET 0 8 CM_SHAPER_RAMA_EXP_REGION12_NUM_SEGMENTS 12 14 CM_SHAPER_RAMA_EXP_REGION13_LUT_OFFSET 16 24 CM_SHAPER_RAMA_EXP_REGION13_NUM_SEGMENTS 28 30 regCM3_CM_SHAPER_RAMA_REGION_14_15 0 0x122e 4 0 2 CM_SHAPER_RAMA_EXP_REGION14_LUT_OFFSET 0 8 CM_SHAPER_RAMA_EXP_REGION14_NUM_SEGMENTS 12 14 CM_SHAPER_RAMA_EXP_REGION15_LUT_OFFSET 16 24 CM_SHAPER_RAMA_EXP_REGION15_NUM_SEGMENTS 28 30 regCM3_CM_SHAPER_RAMA_REGION_16_17 0 0x122f 4 0 2 CM_SHAPER_RAMA_EXP_REGION16_LUT_OFFSET 0 8 CM_SHAPER_RAMA_EXP_REGION16_NUM_SEGMENTS 12 14 CM_SHAPER_RAMA_EXP_REGION17_LUT_OFFSET 16 24 CM_SHAPER_RAMA_EXP_REGION17_NUM_SEGMENTS 28 30 regCM3_CM_SHAPER_RAMA_REGION_18_19 0 0x1230 4 0 2 CM_SHAPER_RAMA_EXP_REGION18_LUT_OFFSET 0 8 CM_SHAPER_RAMA_EXP_REGION18_NUM_SEGMENTS 12 14 CM_SHAPER_RAMA_EXP_REGION19_LUT_OFFSET 16 24 CM_SHAPER_RAMA_EXP_REGION19_NUM_SEGMENTS 28 30 regCM3_CM_SHAPER_RAMA_REGION_20_21 0 0x1231 4 0 2 CM_SHAPER_RAMA_EXP_REGION20_LUT_OFFSET 0 8 CM_SHAPER_RAMA_EXP_REGION20_NUM_SEGMENTS 12 14 CM_SHAPER_RAMA_EXP_REGION21_LUT_OFFSET 16 24 CM_SHAPER_RAMA_EXP_REGION21_NUM_SEGMENTS 28 30 regCM3_CM_SHAPER_RAMA_REGION_22_23 0 0x1232 4 0 2 CM_SHAPER_RAMA_EXP_REGION22_LUT_OFFSET 0 8 CM_SHAPER_RAMA_EXP_REGION22_NUM_SEGMENTS 12 14 CM_SHAPER_RAMA_EXP_REGION23_LUT_OFFSET 16 24 CM_SHAPER_RAMA_EXP_REGION23_NUM_SEGMENTS 28 30 regCM3_CM_SHAPER_RAMA_REGION_24_25 0 0x1233 4 0 2 CM_SHAPER_RAMA_EXP_REGION24_LUT_OFFSET 0 8 CM_SHAPER_RAMA_EXP_REGION24_NUM_SEGMENTS 12 14 CM_SHAPER_RAMA_EXP_REGION25_LUT_OFFSET 16 24 CM_SHAPER_RAMA_EXP_REGION25_NUM_SEGMENTS 28 30 regCM3_CM_SHAPER_RAMA_REGION_26_27 0 0x1234 4 0 2 CM_SHAPER_RAMA_EXP_REGION26_LUT_OFFSET 0 8 CM_SHAPER_RAMA_EXP_REGION26_NUM_SEGMENTS 12 14 CM_SHAPER_RAMA_EXP_REGION27_LUT_OFFSET 16 24 CM_SHAPER_RAMA_EXP_REGION27_NUM_SEGMENTS 28 30 regCM3_CM_SHAPER_RAMA_REGION_28_29 0 0x1235 4 0 2 CM_SHAPER_RAMA_EXP_REGION28_LUT_OFFSET 0 8 CM_SHAPER_RAMA_EXP_REGION28_NUM_SEGMENTS 12 14 CM_SHAPER_RAMA_EXP_REGION29_LUT_OFFSET 16 24 CM_SHAPER_RAMA_EXP_REGION29_NUM_SEGMENTS 28 30 regCM3_CM_SHAPER_RAMA_REGION_30_31 0 0x1236 4 0 2 CM_SHAPER_RAMA_EXP_REGION30_LUT_OFFSET 0 8 CM_SHAPER_RAMA_EXP_REGION30_NUM_SEGMENTS 12 14 CM_SHAPER_RAMA_EXP_REGION31_LUT_OFFSET 16 24 CM_SHAPER_RAMA_EXP_REGION31_NUM_SEGMENTS 28 30 regCM3_CM_SHAPER_RAMA_REGION_32_33 0 0x1237 4 0 2 CM_SHAPER_RAMA_EXP_REGION32_LUT_OFFSET 0 8 CM_SHAPER_RAMA_EXP_REGION32_NUM_SEGMENTS 12 14 CM_SHAPER_RAMA_EXP_REGION33_LUT_OFFSET 16 24 CM_SHAPER_RAMA_EXP_REGION33_NUM_SEGMENTS 28 30 regCM3_CM_SHAPER_RAMB_START_CNTL_B 0 0x1238 2 0 2 CM_SHAPER_RAMB_EXP_REGION_START_B 0 17 CM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_B 20 26 regCM3_CM_SHAPER_RAMB_START_CNTL_G 0 0x1239 2 0 2 CM_SHAPER_RAMB_EXP_REGION_START_G 0 17 CM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_G 20 26 regCM3_CM_SHAPER_RAMB_START_CNTL_R 0 0x123a 2 0 2 CM_SHAPER_RAMB_EXP_REGION_START_R 0 17 CM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_R 20 26 regCM3_CM_SHAPER_RAMB_END_CNTL_B 0 0x123b 2 0 2 CM_SHAPER_RAMB_EXP_REGION_END_B 0 15 CM_SHAPER_RAMB_EXP_REGION_END_BASE_B 16 29 regCM3_CM_SHAPER_RAMB_END_CNTL_G 0 0x123c 2 0 2 CM_SHAPER_RAMB_EXP_REGION_END_G 0 15 CM_SHAPER_RAMB_EXP_REGION_END_BASE_G 16 29 regCM3_CM_SHAPER_RAMB_END_CNTL_R 0 0x123d 2 0 2 CM_SHAPER_RAMB_EXP_REGION_END_R 0 15 CM_SHAPER_RAMB_EXP_REGION_END_BASE_R 16 29 regCM3_CM_SHAPER_RAMB_REGION_0_1 0 0x123e 4 0 2 CM_SHAPER_RAMB_EXP_REGION0_LUT_OFFSET 0 8 CM_SHAPER_RAMB_EXP_REGION0_NUM_SEGMENTS 12 14 CM_SHAPER_RAMB_EXP_REGION1_LUT_OFFSET 16 24 CM_SHAPER_RAMB_EXP_REGION1_NUM_SEGMENTS 28 30 regCM3_CM_SHAPER_RAMB_REGION_2_3 0 0x123f 4 0 2 CM_SHAPER_RAMB_EXP_REGION2_LUT_OFFSET 0 8 CM_SHAPER_RAMB_EXP_REGION2_NUM_SEGMENTS 12 14 CM_SHAPER_RAMB_EXP_REGION3_LUT_OFFSET 16 24 CM_SHAPER_RAMB_EXP_REGION3_NUM_SEGMENTS 28 30 regCM3_CM_SHAPER_RAMB_REGION_4_5 0 0x1240 4 0 2 CM_SHAPER_RAMB_EXP_REGION4_LUT_OFFSET 0 8 CM_SHAPER_RAMB_EXP_REGION4_NUM_SEGMENTS 12 14 CM_SHAPER_RAMB_EXP_REGION5_LUT_OFFSET 16 24 CM_SHAPER_RAMB_EXP_REGION5_NUM_SEGMENTS 28 30 regCM3_CM_SHAPER_RAMB_REGION_6_7 0 0x1241 4 0 2 CM_SHAPER_RAMB_EXP_REGION6_LUT_OFFSET 0 8 CM_SHAPER_RAMB_EXP_REGION6_NUM_SEGMENTS 12 14 CM_SHAPER_RAMB_EXP_REGION7_LUT_OFFSET 16 24 CM_SHAPER_RAMB_EXP_REGION7_NUM_SEGMENTS 28 30 regCM3_CM_SHAPER_RAMB_REGION_8_9 0 0x1242 4 0 2 CM_SHAPER_RAMB_EXP_REGION8_LUT_OFFSET 0 8 CM_SHAPER_RAMB_EXP_REGION8_NUM_SEGMENTS 12 14 CM_SHAPER_RAMB_EXP_REGION9_LUT_OFFSET 16 24 CM_SHAPER_RAMB_EXP_REGION9_NUM_SEGMENTS 28 30 regCM3_CM_SHAPER_RAMB_REGION_10_11 0 0x1243 4 0 2 CM_SHAPER_RAMB_EXP_REGION10_LUT_OFFSET 0 8 CM_SHAPER_RAMB_EXP_REGION10_NUM_SEGMENTS 12 14 CM_SHAPER_RAMB_EXP_REGION11_LUT_OFFSET 16 24 CM_SHAPER_RAMB_EXP_REGION11_NUM_SEGMENTS 28 30 regCM3_CM_SHAPER_RAMB_REGION_12_13 0 0x1244 4 0 2 CM_SHAPER_RAMB_EXP_REGION12_LUT_OFFSET 0 8 CM_SHAPER_RAMB_EXP_REGION12_NUM_SEGMENTS 12 14 CM_SHAPER_RAMB_EXP_REGION13_LUT_OFFSET 16 24 CM_SHAPER_RAMB_EXP_REGION13_NUM_SEGMENTS 28 30 regCM3_CM_SHAPER_RAMB_REGION_14_15 0 0x1245 4 0 2 CM_SHAPER_RAMB_EXP_REGION14_LUT_OFFSET 0 8 CM_SHAPER_RAMB_EXP_REGION14_NUM_SEGMENTS 12 14 CM_SHAPER_RAMB_EXP_REGION15_LUT_OFFSET 16 24 CM_SHAPER_RAMB_EXP_REGION15_NUM_SEGMENTS 28 30 regCM3_CM_SHAPER_RAMB_REGION_16_17 0 0x1246 4 0 2 CM_SHAPER_RAMB_EXP_REGION16_LUT_OFFSET 0 8 CM_SHAPER_RAMB_EXP_REGION16_NUM_SEGMENTS 12 14 CM_SHAPER_RAMB_EXP_REGION17_LUT_OFFSET 16 24 CM_SHAPER_RAMB_EXP_REGION17_NUM_SEGMENTS 28 30 regCM3_CM_SHAPER_RAMB_REGION_18_19 0 0x1247 4 0 2 CM_SHAPER_RAMB_EXP_REGION18_LUT_OFFSET 0 8 CM_SHAPER_RAMB_EXP_REGION18_NUM_SEGMENTS 12 14 CM_SHAPER_RAMB_EXP_REGION19_LUT_OFFSET 16 24 CM_SHAPER_RAMB_EXP_REGION19_NUM_SEGMENTS 28 30 regCM3_CM_SHAPER_RAMB_REGION_20_21 0 0x1248 4 0 2 CM_SHAPER_RAMB_EXP_REGION20_LUT_OFFSET 0 8 CM_SHAPER_RAMB_EXP_REGION20_NUM_SEGMENTS 12 14 CM_SHAPER_RAMB_EXP_REGION21_LUT_OFFSET 16 24 CM_SHAPER_RAMB_EXP_REGION21_NUM_SEGMENTS 28 30 regCM3_CM_SHAPER_RAMB_REGION_22_23 0 0x1249 4 0 2 CM_SHAPER_RAMB_EXP_REGION22_LUT_OFFSET 0 8 CM_SHAPER_RAMB_EXP_REGION22_NUM_SEGMENTS 12 14 CM_SHAPER_RAMB_EXP_REGION23_LUT_OFFSET 16 24 CM_SHAPER_RAMB_EXP_REGION23_NUM_SEGMENTS 28 30 regCM3_CM_SHAPER_RAMB_REGION_24_25 0 0x124a 4 0 2 CM_SHAPER_RAMB_EXP_REGION24_LUT_OFFSET 0 8 CM_SHAPER_RAMB_EXP_REGION24_NUM_SEGMENTS 12 14 CM_SHAPER_RAMB_EXP_REGION25_LUT_OFFSET 16 24 CM_SHAPER_RAMB_EXP_REGION25_NUM_SEGMENTS 28 30 regCM3_CM_SHAPER_RAMB_REGION_26_27 0 0x124b 4 0 2 CM_SHAPER_RAMB_EXP_REGION26_LUT_OFFSET 0 8 CM_SHAPER_RAMB_EXP_REGION26_NUM_SEGMENTS 12 14 CM_SHAPER_RAMB_EXP_REGION27_LUT_OFFSET 16 24 CM_SHAPER_RAMB_EXP_REGION27_NUM_SEGMENTS 28 30 regCM3_CM_SHAPER_RAMB_REGION_28_29 0 0x124c 4 0 2 CM_SHAPER_RAMB_EXP_REGION28_LUT_OFFSET 0 8 CM_SHAPER_RAMB_EXP_REGION28_NUM_SEGMENTS 12 14 CM_SHAPER_RAMB_EXP_REGION29_LUT_OFFSET 16 24 CM_SHAPER_RAMB_EXP_REGION29_NUM_SEGMENTS 28 30 regCM3_CM_SHAPER_RAMB_REGION_30_31 0 0x124d 4 0 2 CM_SHAPER_RAMB_EXP_REGION30_LUT_OFFSET 0 8 CM_SHAPER_RAMB_EXP_REGION30_NUM_SEGMENTS 12 14 CM_SHAPER_RAMB_EXP_REGION31_LUT_OFFSET 16 24 CM_SHAPER_RAMB_EXP_REGION31_NUM_SEGMENTS 28 30 regCM3_CM_SHAPER_RAMB_REGION_32_33 0 0x124e 4 0 2 CM_SHAPER_RAMB_EXP_REGION32_LUT_OFFSET 0 8 CM_SHAPER_RAMB_EXP_REGION32_NUM_SEGMENTS 12 14 CM_SHAPER_RAMB_EXP_REGION33_LUT_OFFSET 16 24 CM_SHAPER_RAMB_EXP_REGION33_NUM_SEGMENTS 28 30 regCM3_CM_MEM_PWR_CTRL2 0 0x124f 4 0 2 SHAPER_MEM_PWR_FORCE 8 9 SHAPER_MEM_PWR_DIS 10 10 HDR3DLUT_MEM_PWR_FORCE 12 13 HDR3DLUT_MEM_PWR_DIS 14 14 regCM3_CM_MEM_PWR_STATUS2 0 0x1250 2 0 2 SHAPER_MEM_PWR_STATE 4 5 HDR3DLUT_MEM_PWR_STATE 6 7 regCM3_CM_3DLUT_MODE 0 0x1251 3 0 2 CM_3DLUT_MODE 0 1 CM_3DLUT_SIZE 4 4 CM_3DLUT_MODE_CURRENT 8 9 regCM3_CM_3DLUT_INDEX 0 0x1252 1 0 2 CM_3DLUT_INDEX 0 10 regCM3_CM_3DLUT_DATA 0 0x1253 2 0 2 CM_3DLUT_DATA0 0 15 CM_3DLUT_DATA1 16 31 regCM3_CM_3DLUT_DATA_30BIT 0 0x1254 1 0 2 CM_3DLUT_DATA_30BIT 2 31 regCM3_CM_3DLUT_READ_WRITE_CONTROL 0 0x1255 4 0 2 CM_3DLUT_WRITE_EN_MASK 0 3 CM_3DLUT_RAM_SEL 4 4 CM_3DLUT_30BIT_EN 8 8 CM_3DLUT_READ_SEL 16 17 regCM3_CM_3DLUT_OUT_NORM_FACTOR 0 0x1256 1 0 2 CM_3DLUT_OUT_NORM_FACTOR 0 15 regCM3_CM_3DLUT_OUT_OFFSET_R 0 0x1257 2 0 2 CM_3DLUT_OUT_OFFSET_R 0 15 CM_3DLUT_OUT_SCALE_R 16 31 regCM3_CM_3DLUT_OUT_OFFSET_G 0 0x1258 2 0 2 CM_3DLUT_OUT_OFFSET_G 0 15 CM_3DLUT_OUT_SCALE_G 16 31 regCM3_CM_3DLUT_OUT_OFFSET_B 0 0x1259 2 0 2 CM_3DLUT_OUT_OFFSET_B 0 15 CM_3DLUT_OUT_SCALE_B 16 31 regCM3_CM_TEST_DEBUG_INDEX 0 0x125a 2 0 2 CM_TEST_DEBUG_INDEX 0 7 CM_TEST_DEBUG_WRITE_EN 8 8 regCM3_CM_TEST_DEBUG_DATA 0 0x125b 1 0 2 CM_TEST_DEBUG_DATA 0 31 regDPP_TOP3_DPP_CONTROL 0 0x1106 8 0 2 DPP_CLOCK_ENABLE 4 4 DPPCLK_G_GATE_DISABLE 8 8 DPPCLK_G_DYN_GATE_DISABLE 10 10 DPPCLK_G_DSCL_GATE_DISABLE 12 12 DPPCLK_R_GATE_DISABLE 14 14 DISPCLK_R_GATE_DISABLE 16 16 DISPCLK_G_GATE_DISABLE 18 18 DPP_TEST_CLK_SEL 28 30 regDPP_TOP3_DPP_SOFT_RESET 0 0x1107 4 0 2 CNVC_SOFT_RESET 0 0 DSCL_SOFT_RESET 4 4 CM_SOFT_RESET 8 8 OBUF_SOFT_RESET 12 12 regDPP_TOP3_DPP_CRC_VAL_R_G 0 0x1108 2 0 2 DPP_CRC_R_CR 0 15 DPP_CRC_G_Y 16 31 regDPP_TOP3_DPP_CRC_VAL_B_A 0 0x1109 2 0 2 DPP_CRC_B_CB 0 15 DPP_CRC_ALPHA 16 31 regDPP_TOP3_DPP_CRC_CTRL 0 0x110a 11 0 2 DPP_CRC_EN 0 0 DPP_CRC_CONT_EN 1 1 DPP_CRC_ONE_SHOT_PENDING 2 2 DPP_CRC_420_COMP_SEL 3 3 DPP_CRC_SRC_SEL 4 5 DPP_CRC_STEREO_EN 6 6 DPP_CRC_STEREO_MODE 7 8 DPP_CRC_INTERLACE_MODE 9 10 DPP_CRC_PIX_FORMAT_SEL 11 13 DPP_CRC_CURSOR_FORMAT_SEL 14 15 DPP_CRC_MASK 16 31 regDPP_TOP3_HOST_READ_CONTROL 0 0x110b 1 0 2 HOST_READ_RATE_CONTROL 0 7 regDC_PERFMON14_PERFCOUNTER_CNTL 0 0x1265 11 0 2 PERFCOUNTER_EVENT_SEL 0 8 PERFCOUNTER_CVALUE_SEL 9 11 PERFCOUNTER_INC_MODE 12 14 PERFCOUNTER_HW_CNTL_SEL 15 15 PERFCOUNTER_RUNEN_MODE 16 16 PERFCOUNTER_CNTOFF_START_DIS 22 22 PERFCOUNTER_RESTART_EN 23 23 PERFCOUNTER_INT_EN 24 24 PERFCOUNTER_OFF_MASK 25 25 PERFCOUNTER_ACTIVE 26 26 PERFCOUNTER_CNTL_SEL 29 31 regDC_PERFMON14_PERFCOUNTER_CNTL2 0 0x1266 5 0 2 PERFCOUNTER_COUNTED_VALUE_TYPE 0 1 PERFCOUNTER_HW_STOP1_SEL 2 2 PERFCOUNTER_HW_STOP2_SEL 3 3 PERFCOUNTER_CNTOFF_SEL 8 13 PERFCOUNTER_CNTL2_SEL 29 31 regDC_PERFMON14_PERFCOUNTER_STATE 0 0x1267 16 0 2 PERFCOUNTER_CNT0_STATE 0 1 PERFCOUNTER_STATE_SEL0 2 2 PERFCOUNTER_CNT1_STATE 4 5 PERFCOUNTER_STATE_SEL1 6 6 PERFCOUNTER_CNT2_STATE 8 9 PERFCOUNTER_STATE_SEL2 10 10 PERFCOUNTER_CNT3_STATE 12 13 PERFCOUNTER_STATE_SEL3 14 14 PERFCOUNTER_CNT4_STATE 16 17 PERFCOUNTER_STATE_SEL4 18 18 PERFCOUNTER_CNT5_STATE 20 21 PERFCOUNTER_STATE_SEL5 22 22 PERFCOUNTER_CNT6_STATE 24 25 PERFCOUNTER_STATE_SEL6 26 26 PERFCOUNTER_CNT7_STATE 28 29 PERFCOUNTER_STATE_SEL7 30 30 regDC_PERFMON14_PERFMON_CNTL 0 0x1268 6 0 2 PERFMON_STATE 0 1 PERFMON_RPT_COUNT 8 27 PERFMON_CNTOFF_AND_OR 28 28 PERFMON_CNTOFF_INT_EN 29 29 PERFMON_CNTOFF_INT_STATUS 30 30 PERFMON_CNTOFF_INT_ACK 31 31 regDC_PERFMON14_PERFMON_CNTL2 0 0x1269 4 0 2 PERFMON_CNTOFF_INT_TYPE 0 0 PERFMON_CLK_ENABLE 1 1 PERFMON_RUN_ENABLE_START_SEL 2 9 PERFMON_RUN_ENABLE_STOP_SEL 10 17 regDC_PERFMON14_PERFMON_CVALUE_INT_MISC 0 0x126a 17 0 2 PERFCOUNTER_INT0_STATUS 0 0 PERFCOUNTER_INT1_STATUS 1 1 PERFCOUNTER_INT2_STATUS 2 2 PERFCOUNTER_INT3_STATUS 3 3 PERFCOUNTER_INT4_STATUS 4 4 PERFCOUNTER_INT5_STATUS 5 5 PERFCOUNTER_INT6_STATUS 6 6 PERFCOUNTER_INT7_STATUS 7 7 PERFCOUNTER_INT0_ACK 8 8 PERFCOUNTER_INT1_ACK 9 9 PERFCOUNTER_INT2_ACK 10 10 PERFCOUNTER_INT3_ACK 11 11 PERFCOUNTER_INT4_ACK 12 12 PERFCOUNTER_INT5_ACK 13 13 PERFCOUNTER_INT6_ACK 14 14 PERFCOUNTER_INT7_ACK 15 15 PERFMON_CVALUE_HI 16 31 regDC_PERFMON14_PERFMON_CVALUE_LOW 0 0x126b 1 0 2 PERFMON_CVALUE_LOW 0 31 regDC_PERFMON14_PERFMON_HI 0 0x126c 2 0 2 PERFMON_HI 0 15 PERFMON_READ_SEL 29 31 regDC_PERFMON14_PERFMON_LOW 0 0x126d 1 0 2 PERFMON_LOW 0 31 regMPCC0_MPCC_TOP_SEL 0 0x0 1 0 3 MPCC_TOP_SEL 0 3 regMPCC0_MPCC_BOT_SEL 0 0x1 1 0 3 MPCC_BOT_SEL 0 3 regMPCC0_MPCC_OPP_ID 0 0x2 1 0 3 MPCC_OPP_ID 0 3 regMPCC0_MPCC_CONTROL 0 0x3 8 0 3 MPCC_MODE 0 1 MPCC_ALPHA_BLND_MODE 4 5 MPCC_ALPHA_MULTIPLIED_MODE 6 6 MPCC_BLND_ACTIVE_OVERLAP_ONLY 7 7 MPCC_BG_BPC 8 10 MPCC_BOT_GAIN_MODE 11 11 MPCC_GLOBAL_ALPHA 16 23 MPCC_GLOBAL_GAIN 24 31 regMPCC0_MPCC_SM_CONTROL 0 0x4 7 0 3 MPCC_SM_EN 0 0 MPCC_SM_MODE 1 3 MPCC_SM_FRAME_ALT 4 4 MPCC_SM_FIELD_ALT 5 5 MPCC_SM_FORCE_NEXT_FRAME_POL 8 9 MPCC_SM_FORCE_NEXT_TOP_POL 16 17 MPCC_SM_CURRENT_FRAME_POL 24 24 regMPCC0_MPCC_UPDATE_LOCK_SEL 0 0x5 2 0 3 MPCC_UPDATE_LOCK_SEL 0 3 MPCC_UPDATE_LOCKED_STATUS 4 6 regMPCC0_MPCC_TOP_GAIN 0 0x6 1 0 3 MPCC_TOP_GAIN 0 18 regMPCC0_MPCC_BOT_GAIN_INSIDE 0 0x7 1 0 3 MPCC_BOT_GAIN_INSIDE 0 18 regMPCC0_MPCC_BOT_GAIN_OUTSIDE 0 0x8 1 0 3 MPCC_BOT_GAIN_OUTSIDE 0 18 regMPCC0_MPCC_BG_R_CR 0 0x9 1 0 3 MPCC_BG_R_CR 0 11 regMPCC0_MPCC_BG_G_Y 0 0xa 1 0 3 MPCC_BG_G_Y 0 11 regMPCC0_MPCC_BG_B_CB 0 0xb 1 0 3 MPCC_BG_B_CB 0 11 regMPCC0_MPCC_MEM_PWR_CTRL 0 0xc 4 0 3 MPCC_OGAM_MEM_PWR_FORCE 0 1 MPCC_OGAM_MEM_PWR_DIS 2 2 MPCC_OGAM_MEM_LOW_PWR_MODE 4 5 MPCC_OGAM_MEM_PWR_STATE 8 9 regMPCC0_MPCC_STATUS 0 0xd 3 0 3 MPCC_IDLE 0 0 MPCC_BUSY 1 1 MPCC_DISABLED 2 2 regMPCC1_MPCC_TOP_SEL 0 0x20 1 0 3 MPCC_TOP_SEL 0 3 regMPCC1_MPCC_BOT_SEL 0 0x21 1 0 3 MPCC_BOT_SEL 0 3 regMPCC1_MPCC_OPP_ID 0 0x22 1 0 3 MPCC_OPP_ID 0 3 regMPCC1_MPCC_CONTROL 0 0x23 8 0 3 MPCC_MODE 0 1 MPCC_ALPHA_BLND_MODE 4 5 MPCC_ALPHA_MULTIPLIED_MODE 6 6 MPCC_BLND_ACTIVE_OVERLAP_ONLY 7 7 MPCC_BG_BPC 8 10 MPCC_BOT_GAIN_MODE 11 11 MPCC_GLOBAL_ALPHA 16 23 MPCC_GLOBAL_GAIN 24 31 regMPCC1_MPCC_SM_CONTROL 0 0x24 7 0 3 MPCC_SM_EN 0 0 MPCC_SM_MODE 1 3 MPCC_SM_FRAME_ALT 4 4 MPCC_SM_FIELD_ALT 5 5 MPCC_SM_FORCE_NEXT_FRAME_POL 8 9 MPCC_SM_FORCE_NEXT_TOP_POL 16 17 MPCC_SM_CURRENT_FRAME_POL 24 24 regMPCC1_MPCC_UPDATE_LOCK_SEL 0 0x25 2 0 3 MPCC_UPDATE_LOCK_SEL 0 3 MPCC_UPDATE_LOCKED_STATUS 4 6 regMPCC1_MPCC_TOP_GAIN 0 0x26 1 0 3 MPCC_TOP_GAIN 0 18 regMPCC1_MPCC_BOT_GAIN_INSIDE 0 0x27 1 0 3 MPCC_BOT_GAIN_INSIDE 0 18 regMPCC1_MPCC_BOT_GAIN_OUTSIDE 0 0x28 1 0 3 MPCC_BOT_GAIN_OUTSIDE 0 18 regMPCC1_MPCC_BG_R_CR 0 0x29 1 0 3 MPCC_BG_R_CR 0 11 regMPCC1_MPCC_BG_G_Y 0 0x2a 1 0 3 MPCC_BG_G_Y 0 11 regMPCC1_MPCC_BG_B_CB 0 0x2b 1 0 3 MPCC_BG_B_CB 0 11 regMPCC1_MPCC_MEM_PWR_CTRL 0 0x2c 4 0 3 MPCC_OGAM_MEM_PWR_FORCE 0 1 MPCC_OGAM_MEM_PWR_DIS 2 2 MPCC_OGAM_MEM_LOW_PWR_MODE 4 5 MPCC_OGAM_MEM_PWR_STATE 8 9 regMPCC1_MPCC_STATUS 0 0x2d 3 0 3 MPCC_IDLE 0 0 MPCC_BUSY 1 1 MPCC_DISABLED 2 2 regMPCC2_MPCC_TOP_SEL 0 0x40 1 0 3 MPCC_TOP_SEL 0 3 regMPCC2_MPCC_BOT_SEL 0 0x41 1 0 3 MPCC_BOT_SEL 0 3 regMPCC2_MPCC_OPP_ID 0 0x42 1 0 3 MPCC_OPP_ID 0 3 regMPCC2_MPCC_CONTROL 0 0x43 8 0 3 MPCC_MODE 0 1 MPCC_ALPHA_BLND_MODE 4 5 MPCC_ALPHA_MULTIPLIED_MODE 6 6 MPCC_BLND_ACTIVE_OVERLAP_ONLY 7 7 MPCC_BG_BPC 8 10 MPCC_BOT_GAIN_MODE 11 11 MPCC_GLOBAL_ALPHA 16 23 MPCC_GLOBAL_GAIN 24 31 regMPCC2_MPCC_SM_CONTROL 0 0x44 7 0 3 MPCC_SM_EN 0 0 MPCC_SM_MODE 1 3 MPCC_SM_FRAME_ALT 4 4 MPCC_SM_FIELD_ALT 5 5 MPCC_SM_FORCE_NEXT_FRAME_POL 8 9 MPCC_SM_FORCE_NEXT_TOP_POL 16 17 MPCC_SM_CURRENT_FRAME_POL 24 24 regMPCC2_MPCC_UPDATE_LOCK_SEL 0 0x45 2 0 3 MPCC_UPDATE_LOCK_SEL 0 3 MPCC_UPDATE_LOCKED_STATUS 4 6 regMPCC2_MPCC_TOP_GAIN 0 0x46 1 0 3 MPCC_TOP_GAIN 0 18 regMPCC2_MPCC_BOT_GAIN_INSIDE 0 0x47 1 0 3 MPCC_BOT_GAIN_INSIDE 0 18 regMPCC2_MPCC_BOT_GAIN_OUTSIDE 0 0x48 1 0 3 MPCC_BOT_GAIN_OUTSIDE 0 18 regMPCC2_MPCC_BG_R_CR 0 0x49 1 0 3 MPCC_BG_R_CR 0 11 regMPCC2_MPCC_BG_G_Y 0 0x4a 1 0 3 MPCC_BG_G_Y 0 11 regMPCC2_MPCC_BG_B_CB 0 0x4b 1 0 3 MPCC_BG_B_CB 0 11 regMPCC2_MPCC_MEM_PWR_CTRL 0 0x4c 4 0 3 MPCC_OGAM_MEM_PWR_FORCE 0 1 MPCC_OGAM_MEM_PWR_DIS 2 2 MPCC_OGAM_MEM_LOW_PWR_MODE 4 5 MPCC_OGAM_MEM_PWR_STATE 8 9 regMPCC2_MPCC_STATUS 0 0x4d 3 0 3 MPCC_IDLE 0 0 MPCC_BUSY 1 1 MPCC_DISABLED 2 2 regMPCC3_MPCC_TOP_SEL 0 0x60 1 0 3 MPCC_TOP_SEL 0 3 regMPCC3_MPCC_BOT_SEL 0 0x61 1 0 3 MPCC_BOT_SEL 0 3 regMPCC3_MPCC_OPP_ID 0 0x62 1 0 3 MPCC_OPP_ID 0 3 regMPCC3_MPCC_CONTROL 0 0x63 8 0 3 MPCC_MODE 0 1 MPCC_ALPHA_BLND_MODE 4 5 MPCC_ALPHA_MULTIPLIED_MODE 6 6 MPCC_BLND_ACTIVE_OVERLAP_ONLY 7 7 MPCC_BG_BPC 8 10 MPCC_BOT_GAIN_MODE 11 11 MPCC_GLOBAL_ALPHA 16 23 MPCC_GLOBAL_GAIN 24 31 regMPCC3_MPCC_SM_CONTROL 0 0x64 7 0 3 MPCC_SM_EN 0 0 MPCC_SM_MODE 1 3 MPCC_SM_FRAME_ALT 4 4 MPCC_SM_FIELD_ALT 5 5 MPCC_SM_FORCE_NEXT_FRAME_POL 8 9 MPCC_SM_FORCE_NEXT_TOP_POL 16 17 MPCC_SM_CURRENT_FRAME_POL 24 24 regMPCC3_MPCC_UPDATE_LOCK_SEL 0 0x65 2 0 3 MPCC_UPDATE_LOCK_SEL 0 3 MPCC_UPDATE_LOCKED_STATUS 4 6 regMPCC3_MPCC_TOP_GAIN 0 0x66 1 0 3 MPCC_TOP_GAIN 0 18 regMPCC3_MPCC_BOT_GAIN_INSIDE 0 0x67 1 0 3 MPCC_BOT_GAIN_INSIDE 0 18 regMPCC3_MPCC_BOT_GAIN_OUTSIDE 0 0x68 1 0 3 MPCC_BOT_GAIN_OUTSIDE 0 18 regMPCC3_MPCC_BG_R_CR 0 0x69 1 0 3 MPCC_BG_R_CR 0 11 regMPCC3_MPCC_BG_G_Y 0 0x6a 1 0 3 MPCC_BG_G_Y 0 11 regMPCC3_MPCC_BG_B_CB 0 0x6b 1 0 3 MPCC_BG_B_CB 0 11 regMPCC3_MPCC_MEM_PWR_CTRL 0 0x6c 4 0 3 MPCC_OGAM_MEM_PWR_FORCE 0 1 MPCC_OGAM_MEM_PWR_DIS 2 2 MPCC_OGAM_MEM_LOW_PWR_MODE 4 5 MPCC_OGAM_MEM_PWR_STATE 8 9 regMPCC3_MPCC_STATUS 0 0x6d 3 0 3 MPCC_IDLE 0 0 MPCC_BUSY 1 1 MPCC_DISABLED 2 2 regMPC_CLOCK_CONTROL 0 0x500 2 0 3 DISPCLK_R_GATE_DISABLE 1 1 MPC_TEST_CLK_SEL 4 5 regMPC_SOFT_RESET 0 0x501 13 0 3 MPCC0_SOFT_RESET 0 0 MPCC1_SOFT_RESET 1 1 MPCC2_SOFT_RESET 2 2 MPCC3_SOFT_RESET 3 3 MPC_SFR0_SOFT_RESET 10 10 MPC_SFR1_SOFT_RESET 11 11 MPC_SFR2_SOFT_RESET 12 12 MPC_SFR3_SOFT_RESET 13 13 MPC_SFT0_SOFT_RESET 20 20 MPC_SFT1_SOFT_RESET 21 21 MPC_SFT2_SOFT_RESET 22 22 MPC_SFT3_SOFT_RESET 23 23 MPC_SOFT_RESET 31 31 regMPC_CRC_CTRL 0 0x502 9 0 3 MPC_CRC_EN 0 0 MPC_CRC_CONT_EN 4 4 MPC_CRC_STEREO_MODE 8 9 MPC_CRC_STEREO_EN 10 10 MPC_CRC_INTERLACE_MODE 12 13 MPC_CRC_SRC_SEL 24 25 MPC_CRC_ONE_SHOT_PENDING 28 28 MPC_CRC_UPDATE_ENABLED 30 30 MPC_CRC_UPDATE_LOCK 31 31 regMPC_CRC_SEL_CONTROL 0 0x503 4 0 3 MPC_CRC_DPP_SEL 0 3 MPC_CRC_OPP_SEL 4 7 MPC_CRC_DWB_SEL 8 9 MPC_CRC_MASK 16 31 regMPC_CRC_RESULT_AR 0 0x504 2 0 3 MPC_CRC_RESULT_A 0 15 MPC_CRC_RESULT_R 16 31 regMPC_CRC_RESULT_GB 0 0x505 2 0 3 MPC_CRC_RESULT_G 0 15 MPC_CRC_RESULT_B 16 31 regMPC_CRC_RESULT_C 0 0x506 1 0 3 MPC_CRC_RESULT_C 0 15 regMPC_PERFMON_EVENT_CTRL 0 0x509 1 0 3 MPC_PERFMON_EVENT_EN 0 0 regMPC_BYPASS_BG_AR 0 0x50a 2 0 3 MPC_BYPASS_BG_ALPHA 0 15 MPC_BYPASS_BG_R_CR 16 31 regMPC_BYPASS_BG_GB 0 0x50b 2 0 3 MPC_BYPASS_BG_G_Y 0 15 MPC_BYPASS_BG_B_CB 16 31 regMPC_HOST_READ_CONTROL 0 0x50c 1 0 3 HOST_READ_RATE_CONTROL 0 7 regMPC_DPP_PENDING_STATUS 0 0x50d 12 0 3 IN_DPP0_SURFACE_UPDATE_PENDING 0 0 IN_DPP0_CONFIG_UPDATE_PENDING 1 1 IN_DPP0_CURSOR_UPDATE_PENDING 2 2 IN_DPP1_SURFACE_UPDATE_PENDING 4 4 IN_DPP1_CONFIG_UPDATE_PENDING 5 5 IN_DPP1_CURSOR_UPDATE_PENDING 6 6 IN_DPP2_SURFACE_UPDATE_PENDING 8 8 IN_DPP2_CONFIG_UPDATE_PENDING 9 9 IN_DPP2_CURSOR_UPDATE_PENDING 10 10 IN_DPP3_SURFACE_UPDATE_PENDING 12 12 IN_DPP3_CONFIG_UPDATE_PENDING 13 13 IN_DPP3_CURSOR_UPDATE_PENDING 14 14 regMPC_PENDING_STATUS_MISC 0 0x50e 9 0 3 OUT_OPP0_CONFIG_UPDATE_PENDING 0 0 OUT_OPP1_CONFIG_UPDATE_PENDING 1 1 OUT_OPP2_CONFIG_UPDATE_PENDING 2 2 OUT_OPP3_CONFIG_UPDATE_PENDING 3 3 MPCC0_CONFIG_UPDATE_PENDING 8 8 MPCC1_CONFIG_UPDATE_PENDING 9 9 MPCC2_CONFIG_UPDATE_PENDING 10 10 MPCC3_CONFIG_UPDATE_PENDING 11 11 IN_DWB0_CONFIG_UPDATE_PENDING 16 16 regADR_CFG_CUR_VUPDATE_LOCK_SET0 0 0x50f 1 0 3 ADR_CFG_CUR_VUPDATE_LOCK_SET 0 0 regADR_CFG_VUPDATE_LOCK_SET0 0 0x510 1 0 3 ADR_CFG_VUPDATE_LOCK_SET 0 0 regADR_VUPDATE_LOCK_SET0 0 0x511 1 0 3 ADR_VUPDATE_LOCK_SET 0 0 regCFG_VUPDATE_LOCK_SET0 0 0x512 1 0 3 CFG_VUPDATE_LOCK_SET 0 0 regCUR_VUPDATE_LOCK_SET0 0 0x513 1 0 3 CUR_VUPDATE_LOCK_SET 0 0 regADR_CFG_CUR_VUPDATE_LOCK_SET1 0 0x514 1 0 3 ADR_CFG_CUR_VUPDATE_LOCK_SET 0 0 regADR_CFG_VUPDATE_LOCK_SET1 0 0x515 1 0 3 ADR_CFG_VUPDATE_LOCK_SET 0 0 regADR_VUPDATE_LOCK_SET1 0 0x516 1 0 3 ADR_VUPDATE_LOCK_SET 0 0 regCFG_VUPDATE_LOCK_SET1 0 0x517 1 0 3 CFG_VUPDATE_LOCK_SET 0 0 regCUR_VUPDATE_LOCK_SET1 0 0x518 1 0 3 CUR_VUPDATE_LOCK_SET 0 0 regADR_CFG_CUR_VUPDATE_LOCK_SET2 0 0x519 1 0 3 ADR_CFG_CUR_VUPDATE_LOCK_SET 0 0 regADR_CFG_VUPDATE_LOCK_SET2 0 0x51a 1 0 3 ADR_CFG_VUPDATE_LOCK_SET 0 0 regADR_VUPDATE_LOCK_SET2 0 0x51b 1 0 3 ADR_VUPDATE_LOCK_SET 0 0 regCFG_VUPDATE_LOCK_SET2 0 0x51c 1 0 3 CFG_VUPDATE_LOCK_SET 0 0 regCUR_VUPDATE_LOCK_SET2 0 0x51d 1 0 3 CUR_VUPDATE_LOCK_SET 0 0 regADR_CFG_CUR_VUPDATE_LOCK_SET3 0 0x51e 1 0 3 ADR_CFG_CUR_VUPDATE_LOCK_SET 0 0 regADR_CFG_VUPDATE_LOCK_SET3 0 0x51f 1 0 3 ADR_CFG_VUPDATE_LOCK_SET 0 0 regADR_VUPDATE_LOCK_SET3 0 0x520 1 0 3 ADR_VUPDATE_LOCK_SET 0 0 regCFG_VUPDATE_LOCK_SET3 0 0x521 1 0 3 CFG_VUPDATE_LOCK_SET 0 0 regCUR_VUPDATE_LOCK_SET3 0 0x522 1 0 3 CUR_VUPDATE_LOCK_SET 0 0 regMPC_DWB0_MUX 0 0x55c 2 0 3 MPC_DWB0_MUX 0 3 MPC_DWB0_MUX_STATUS 4 7 regDC_PERFMON15_PERFCOUNTER_CNTL 0 0x8c7 11 0 3 PERFCOUNTER_EVENT_SEL 0 8 PERFCOUNTER_CVALUE_SEL 9 11 PERFCOUNTER_INC_MODE 12 14 PERFCOUNTER_HW_CNTL_SEL 15 15 PERFCOUNTER_RUNEN_MODE 16 16 PERFCOUNTER_CNTOFF_START_DIS 22 22 PERFCOUNTER_RESTART_EN 23 23 PERFCOUNTER_INT_EN 24 24 PERFCOUNTER_OFF_MASK 25 25 PERFCOUNTER_ACTIVE 26 26 PERFCOUNTER_CNTL_SEL 29 31 regDC_PERFMON15_PERFCOUNTER_CNTL2 0 0x8c8 5 0 3 PERFCOUNTER_COUNTED_VALUE_TYPE 0 1 PERFCOUNTER_HW_STOP1_SEL 2 2 PERFCOUNTER_HW_STOP2_SEL 3 3 PERFCOUNTER_CNTOFF_SEL 8 13 PERFCOUNTER_CNTL2_SEL 29 31 regDC_PERFMON15_PERFCOUNTER_STATE 0 0x8c9 16 0 3 PERFCOUNTER_CNT0_STATE 0 1 PERFCOUNTER_STATE_SEL0 2 2 PERFCOUNTER_CNT1_STATE 4 5 PERFCOUNTER_STATE_SEL1 6 6 PERFCOUNTER_CNT2_STATE 8 9 PERFCOUNTER_STATE_SEL2 10 10 PERFCOUNTER_CNT3_STATE 12 13 PERFCOUNTER_STATE_SEL3 14 14 PERFCOUNTER_CNT4_STATE 16 17 PERFCOUNTER_STATE_SEL4 18 18 PERFCOUNTER_CNT5_STATE 20 21 PERFCOUNTER_STATE_SEL5 22 22 PERFCOUNTER_CNT6_STATE 24 25 PERFCOUNTER_STATE_SEL6 26 26 PERFCOUNTER_CNT7_STATE 28 29 PERFCOUNTER_STATE_SEL7 30 30 regDC_PERFMON15_PERFMON_CNTL 0 0x8ca 6 0 3 PERFMON_STATE 0 1 PERFMON_RPT_COUNT 8 27 PERFMON_CNTOFF_AND_OR 28 28 PERFMON_CNTOFF_INT_EN 29 29 PERFMON_CNTOFF_INT_STATUS 30 30 PERFMON_CNTOFF_INT_ACK 31 31 regDC_PERFMON15_PERFMON_CNTL2 0 0x8cb 4 0 3 PERFMON_CNTOFF_INT_TYPE 0 0 PERFMON_CLK_ENABLE 1 1 PERFMON_RUN_ENABLE_START_SEL 2 9 PERFMON_RUN_ENABLE_STOP_SEL 10 17 regDC_PERFMON15_PERFMON_CVALUE_INT_MISC 0 0x8cc 17 0 3 PERFCOUNTER_INT0_STATUS 0 0 PERFCOUNTER_INT1_STATUS 1 1 PERFCOUNTER_INT2_STATUS 2 2 PERFCOUNTER_INT3_STATUS 3 3 PERFCOUNTER_INT4_STATUS 4 4 PERFCOUNTER_INT5_STATUS 5 5 PERFCOUNTER_INT6_STATUS 6 6 PERFCOUNTER_INT7_STATUS 7 7 PERFCOUNTER_INT0_ACK 8 8 PERFCOUNTER_INT1_ACK 9 9 PERFCOUNTER_INT2_ACK 10 10 PERFCOUNTER_INT3_ACK 11 11 PERFCOUNTER_INT4_ACK 12 12 PERFCOUNTER_INT5_ACK 13 13 PERFCOUNTER_INT6_ACK 14 14 PERFCOUNTER_INT7_ACK 15 15 PERFMON_CVALUE_HI 16 31 regDC_PERFMON15_PERFMON_CVALUE_LOW 0 0x8cd 1 0 3 PERFMON_CVALUE_LOW 0 31 regDC_PERFMON15_PERFMON_HI 0 0x8ce 2 0 3 PERFMON_HI 0 15 PERFMON_READ_SEL 29 31 regDC_PERFMON15_PERFMON_LOW 0 0x8cf 1 0 3 PERFMON_LOW 0 31 regMPCC_OGAM0_MPCC_OGAM_CONTROL 0 0x100 5 0 3 MPCC_OGAM_MODE 0 1 MPCC_OGAM_SELECT 2 2 MPCC_OGAM_PWL_DISABLE 3 3 MPCC_OGAM_MODE_CURRENT 7 8 MPCC_OGAM_SELECT_CURRENT 9 9 regMPCC_OGAM0_MPCC_OGAM_LUT_INDEX 0 0x101 1 0 3 MPCC_OGAM_LUT_INDEX 0 8 regMPCC_OGAM0_MPCC_OGAM_LUT_DATA 0 0x102 1 0 3 MPCC_OGAM_LUT_DATA 0 17 regMPCC_OGAM0_MPCC_OGAM_LUT_CONTROL 0 0x103 5 0 3 MPCC_OGAM_LUT_WRITE_COLOR_MASK 0 2 MPCC_OGAM_LUT_READ_COLOR_SEL 3 4 MPCC_OGAM_LUT_READ_DBG 5 5 MPCC_OGAM_LUT_HOST_SEL 6 6 MPCC_OGAM_LUT_CONFIG_MODE 7 7 regMPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_B 0 0x104 2 0 3 MPCC_OGAM_RAMA_EXP_REGION_START_B 0 17 MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_B 20 26 regMPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_G 0 0x105 2 0 3 MPCC_OGAM_RAMA_EXP_REGION_START_G 0 17 MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_G 20 26 regMPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_R 0 0x106 2 0 3 MPCC_OGAM_RAMA_EXP_REGION_START_R 0 17 MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_R 20 26 regMPCC_OGAM0_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B 0 0x107 1 0 3 MPCC_OGAM_RAMA_EXP_REGION_START_SLOPE_B 0 17 regMPCC_OGAM0_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G 0 0x108 1 0 3 MPCC_OGAM_RAMA_EXP_REGION_START_SLOPE_G 0 17 regMPCC_OGAM0_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R 0 0x109 1 0 3 MPCC_OGAM_RAMA_EXP_REGION_START_SLOPE_R 0 17 regMPCC_OGAM0_MPCC_OGAM_RAMA_START_BASE_CNTL_B 0 0x10a 1 0 3 MPCC_OGAM_RAMA_EXP_REGION_START_BASE_B 0 17 regMPCC_OGAM0_MPCC_OGAM_RAMA_START_BASE_CNTL_G 0 0x10b 1 0 3 MPCC_OGAM_RAMA_EXP_REGION_START_BASE_G 0 17 regMPCC_OGAM0_MPCC_OGAM_RAMA_START_BASE_CNTL_R 0 0x10c 1 0 3 MPCC_OGAM_RAMA_EXP_REGION_START_BASE_R 0 17 regMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_B 0 0x10d 1 0 3 MPCC_OGAM_RAMA_EXP_REGION_END_BASE_B 0 17 regMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_B 0 0x10e 2 0 3 MPCC_OGAM_RAMA_EXP_REGION_END_B 0 15 MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_B 16 31 regMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_G 0 0x10f 1 0 3 MPCC_OGAM_RAMA_EXP_REGION_END_BASE_G 0 17 regMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_G 0 0x110 2 0 3 MPCC_OGAM_RAMA_EXP_REGION_END_G 0 15 MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_G 16 31 regMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_R 0 0x111 1 0 3 MPCC_OGAM_RAMA_EXP_REGION_END_BASE_R 0 17 regMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_R 0 0x112 2 0 3 MPCC_OGAM_RAMA_EXP_REGION_END_R 0 15 MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_R 16 31 regMPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_B 0 0x113 1 0 3 MPCC_OGAM_RAMA_OFFSET_B 0 18 regMPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_G 0 0x114 1 0 3 MPCC_OGAM_RAMA_OFFSET_G 0 18 regMPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_R 0 0x115 1 0 3 MPCC_OGAM_RAMA_OFFSET_R 0 18 regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_0_1 0 0x116 4 0 3 MPCC_OGAM_RAMA_EXP_REGION0_LUT_OFFSET 0 8 MPCC_OGAM_RAMA_EXP_REGION0_NUM_SEGMENTS 12 14 MPCC_OGAM_RAMA_EXP_REGION1_LUT_OFFSET 16 24 MPCC_OGAM_RAMA_EXP_REGION1_NUM_SEGMENTS 28 30 regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_2_3 0 0x117 4 0 3 MPCC_OGAM_RAMA_EXP_REGION2_LUT_OFFSET 0 8 MPCC_OGAM_RAMA_EXP_REGION2_NUM_SEGMENTS 12 14 MPCC_OGAM_RAMA_EXP_REGION3_LUT_OFFSET 16 24 MPCC_OGAM_RAMA_EXP_REGION3_NUM_SEGMENTS 28 30 regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_4_5 0 0x118 4 0 3 MPCC_OGAM_RAMA_EXP_REGION4_LUT_OFFSET 0 8 MPCC_OGAM_RAMA_EXP_REGION4_NUM_SEGMENTS 12 14 MPCC_OGAM_RAMA_EXP_REGION5_LUT_OFFSET 16 24 MPCC_OGAM_RAMA_EXP_REGION5_NUM_SEGMENTS 28 30 regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_6_7 0 0x119 4 0 3 MPCC_OGAM_RAMA_EXP_REGION6_LUT_OFFSET 0 8 MPCC_OGAM_RAMA_EXP_REGION6_NUM_SEGMENTS 12 14 MPCC_OGAM_RAMA_EXP_REGION7_LUT_OFFSET 16 24 MPCC_OGAM_RAMA_EXP_REGION7_NUM_SEGMENTS 28 30 regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_8_9 0 0x11a 4 0 3 MPCC_OGAM_RAMA_EXP_REGION8_LUT_OFFSET 0 8 MPCC_OGAM_RAMA_EXP_REGION8_NUM_SEGMENTS 12 14 MPCC_OGAM_RAMA_EXP_REGION9_LUT_OFFSET 16 24 MPCC_OGAM_RAMA_EXP_REGION9_NUM_SEGMENTS 28 30 regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_10_11 0 0x11b 4 0 3 MPCC_OGAM_RAMA_EXP_REGION10_LUT_OFFSET 0 8 MPCC_OGAM_RAMA_EXP_REGION10_NUM_SEGMENTS 12 14 MPCC_OGAM_RAMA_EXP_REGION11_LUT_OFFSET 16 24 MPCC_OGAM_RAMA_EXP_REGION11_NUM_SEGMENTS 28 30 regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_12_13 0 0x11c 4 0 3 MPCC_OGAM_RAMA_EXP_REGION12_LUT_OFFSET 0 8 MPCC_OGAM_RAMA_EXP_REGION12_NUM_SEGMENTS 12 14 MPCC_OGAM_RAMA_EXP_REGION13_LUT_OFFSET 16 24 MPCC_OGAM_RAMA_EXP_REGION13_NUM_SEGMENTS 28 30 regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_14_15 0 0x11d 4 0 3 MPCC_OGAM_RAMA_EXP_REGION14_LUT_OFFSET 0 8 MPCC_OGAM_RAMA_EXP_REGION14_NUM_SEGMENTS 12 14 MPCC_OGAM_RAMA_EXP_REGION15_LUT_OFFSET 16 24 MPCC_OGAM_RAMA_EXP_REGION15_NUM_SEGMENTS 28 30 regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_16_17 0 0x11e 4 0 3 MPCC_OGAM_RAMA_EXP_REGION16_LUT_OFFSET 0 8 MPCC_OGAM_RAMA_EXP_REGION16_NUM_SEGMENTS 12 14 MPCC_OGAM_RAMA_EXP_REGION17_LUT_OFFSET 16 24 MPCC_OGAM_RAMA_EXP_REGION17_NUM_SEGMENTS 28 30 regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_18_19 0 0x11f 4 0 3 MPCC_OGAM_RAMA_EXP_REGION18_LUT_OFFSET 0 8 MPCC_OGAM_RAMA_EXP_REGION18_NUM_SEGMENTS 12 14 MPCC_OGAM_RAMA_EXP_REGION19_LUT_OFFSET 16 24 MPCC_OGAM_RAMA_EXP_REGION19_NUM_SEGMENTS 28 30 regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_20_21 0 0x120 4 0 3 MPCC_OGAM_RAMA_EXP_REGION20_LUT_OFFSET 0 8 MPCC_OGAM_RAMA_EXP_REGION20_NUM_SEGMENTS 12 14 MPCC_OGAM_RAMA_EXP_REGION21_LUT_OFFSET 16 24 MPCC_OGAM_RAMA_EXP_REGION21_NUM_SEGMENTS 28 30 regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_22_23 0 0x121 4 0 3 MPCC_OGAM_RAMA_EXP_REGION22_LUT_OFFSET 0 8 MPCC_OGAM_RAMA_EXP_REGION22_NUM_SEGMENTS 12 14 MPCC_OGAM_RAMA_EXP_REGION23_LUT_OFFSET 16 24 MPCC_OGAM_RAMA_EXP_REGION23_NUM_SEGMENTS 28 30 regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_24_25 0 0x122 4 0 3 MPCC_OGAM_RAMA_EXP_REGION24_LUT_OFFSET 0 8 MPCC_OGAM_RAMA_EXP_REGION24_NUM_SEGMENTS 12 14 MPCC_OGAM_RAMA_EXP_REGION25_LUT_OFFSET 16 24 MPCC_OGAM_RAMA_EXP_REGION25_NUM_SEGMENTS 28 30 regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_26_27 0 0x123 4 0 3 MPCC_OGAM_RAMA_EXP_REGION26_LUT_OFFSET 0 8 MPCC_OGAM_RAMA_EXP_REGION26_NUM_SEGMENTS 12 14 MPCC_OGAM_RAMA_EXP_REGION27_LUT_OFFSET 16 24 MPCC_OGAM_RAMA_EXP_REGION27_NUM_SEGMENTS 28 30 regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_28_29 0 0x124 4 0 3 MPCC_OGAM_RAMA_EXP_REGION28_LUT_OFFSET 0 8 MPCC_OGAM_RAMA_EXP_REGION28_NUM_SEGMENTS 12 14 MPCC_OGAM_RAMA_EXP_REGION29_LUT_OFFSET 16 24 MPCC_OGAM_RAMA_EXP_REGION29_NUM_SEGMENTS 28 30 regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_30_31 0 0x125 4 0 3 MPCC_OGAM_RAMA_EXP_REGION30_LUT_OFFSET 0 8 MPCC_OGAM_RAMA_EXP_REGION30_NUM_SEGMENTS 12 14 MPCC_OGAM_RAMA_EXP_REGION31_LUT_OFFSET 16 24 MPCC_OGAM_RAMA_EXP_REGION31_NUM_SEGMENTS 28 30 regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_32_33 0 0x126 4 0 3 MPCC_OGAM_RAMA_EXP_REGION32_LUT_OFFSET 0 8 MPCC_OGAM_RAMA_EXP_REGION32_NUM_SEGMENTS 12 14 MPCC_OGAM_RAMA_EXP_REGION33_LUT_OFFSET 16 24 MPCC_OGAM_RAMA_EXP_REGION33_NUM_SEGMENTS 28 30 regMPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_B 0 0x127 2 0 3 MPCC_OGAM_RAMB_EXP_REGION_START_B 0 17 MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_B 20 26 regMPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_G 0 0x128 2 0 3 MPCC_OGAM_RAMB_EXP_REGION_START_G 0 17 MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_G 20 26 regMPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_R 0 0x129 2 0 3 MPCC_OGAM_RAMB_EXP_REGION_START_R 0 17 MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_R 20 26 regMPCC_OGAM0_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B 0 0x12a 1 0 3 MPCC_OGAM_RAMB_EXP_REGION_START_SLOPE_B 0 17 regMPCC_OGAM0_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G 0 0x12b 1 0 3 MPCC_OGAM_RAMB_EXP_REGION_START_SLOPE_G 0 17 regMPCC_OGAM0_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R 0 0x12c 1 0 3 MPCC_OGAM_RAMB_EXP_REGION_START_SLOPE_R 0 17 regMPCC_OGAM0_MPCC_OGAM_RAMB_START_BASE_CNTL_B 0 0x12d 1 0 3 MPCC_OGAM_RAMB_EXP_REGION_START_BASE_B 0 17 regMPCC_OGAM0_MPCC_OGAM_RAMB_START_BASE_CNTL_G 0 0x12e 1 0 3 MPCC_OGAM_RAMB_EXP_REGION_START_BASE_G 0 17 regMPCC_OGAM0_MPCC_OGAM_RAMB_START_BASE_CNTL_R 0 0x12f 1 0 3 MPCC_OGAM_RAMB_EXP_REGION_START_BASE_R 0 17 regMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_B 0 0x130 1 0 3 MPCC_OGAM_RAMB_EXP_REGION_END_BASE_B 0 17 regMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_B 0 0x131 2 0 3 MPCC_OGAM_RAMB_EXP_REGION_END_B 0 15 MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_B 16 31 regMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_G 0 0x132 1 0 3 MPCC_OGAM_RAMB_EXP_REGION_END_BASE_G 0 17 regMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_G 0 0x133 2 0 3 MPCC_OGAM_RAMB_EXP_REGION_END_G 0 15 MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_G 16 31 regMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_R 0 0x134 1 0 3 MPCC_OGAM_RAMB_EXP_REGION_END_BASE_R 0 17 regMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_R 0 0x135 2 0 3 MPCC_OGAM_RAMB_EXP_REGION_END_R 0 15 MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_R 16 31 regMPCC_OGAM0_MPCC_OGAM_RAMB_OFFSET_B 0 0x136 1 0 3 MPCC_OGAM_RAMB_OFFSET_B 0 18 regMPCC_OGAM0_MPCC_OGAM_RAMB_OFFSET_G 0 0x137 1 0 3 MPCC_OGAM_RAMB_OFFSET_G 0 18 regMPCC_OGAM0_MPCC_OGAM_RAMB_OFFSET_R 0 0x138 1 0 3 MPCC_OGAM_RAMB_OFFSET_R 0 18 regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_0_1 0 0x139 4 0 3 MPCC_OGAM_RAMB_EXP_REGION0_LUT_OFFSET 0 8 MPCC_OGAM_RAMB_EXP_REGION0_NUM_SEGMENTS 12 14 MPCC_OGAM_RAMB_EXP_REGION1_LUT_OFFSET 16 24 MPCC_OGAM_RAMB_EXP_REGION1_NUM_SEGMENTS 28 30 regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_2_3 0 0x13a 4 0 3 MPCC_OGAM_RAMB_EXP_REGION2_LUT_OFFSET 0 8 MPCC_OGAM_RAMB_EXP_REGION2_NUM_SEGMENTS 12 14 MPCC_OGAM_RAMB_EXP_REGION3_LUT_OFFSET 16 24 MPCC_OGAM_RAMB_EXP_REGION3_NUM_SEGMENTS 28 30 regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_4_5 0 0x13b 4 0 3 MPCC_OGAM_RAMB_EXP_REGION4_LUT_OFFSET 0 8 MPCC_OGAM_RAMB_EXP_REGION4_NUM_SEGMENTS 12 14 MPCC_OGAM_RAMB_EXP_REGION5_LUT_OFFSET 16 24 MPCC_OGAM_RAMB_EXP_REGION5_NUM_SEGMENTS 28 30 regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_6_7 0 0x13c 4 0 3 MPCC_OGAM_RAMB_EXP_REGION6_LUT_OFFSET 0 8 MPCC_OGAM_RAMB_EXP_REGION6_NUM_SEGMENTS 12 14 MPCC_OGAM_RAMB_EXP_REGION7_LUT_OFFSET 16 24 MPCC_OGAM_RAMB_EXP_REGION7_NUM_SEGMENTS 28 30 regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_8_9 0 0x13d 4 0 3 MPCC_OGAM_RAMB_EXP_REGION8_LUT_OFFSET 0 8 MPCC_OGAM_RAMB_EXP_REGION8_NUM_SEGMENTS 12 14 MPCC_OGAM_RAMB_EXP_REGION9_LUT_OFFSET 16 24 MPCC_OGAM_RAMB_EXP_REGION9_NUM_SEGMENTS 28 30 regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_10_11 0 0x13e 4 0 3 MPCC_OGAM_RAMB_EXP_REGION10_LUT_OFFSET 0 8 MPCC_OGAM_RAMB_EXP_REGION10_NUM_SEGMENTS 12 14 MPCC_OGAM_RAMB_EXP_REGION11_LUT_OFFSET 16 24 MPCC_OGAM_RAMB_EXP_REGION11_NUM_SEGMENTS 28 30 regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_12_13 0 0x13f 4 0 3 MPCC_OGAM_RAMB_EXP_REGION12_LUT_OFFSET 0 8 MPCC_OGAM_RAMB_EXP_REGION12_NUM_SEGMENTS 12 14 MPCC_OGAM_RAMB_EXP_REGION13_LUT_OFFSET 16 24 MPCC_OGAM_RAMB_EXP_REGION13_NUM_SEGMENTS 28 30 regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_14_15 0 0x140 4 0 3 MPCC_OGAM_RAMB_EXP_REGION14_LUT_OFFSET 0 8 MPCC_OGAM_RAMB_EXP_REGION14_NUM_SEGMENTS 12 14 MPCC_OGAM_RAMB_EXP_REGION15_LUT_OFFSET 16 24 MPCC_OGAM_RAMB_EXP_REGION15_NUM_SEGMENTS 28 30 regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_16_17 0 0x141 4 0 3 MPCC_OGAM_RAMB_EXP_REGION16_LUT_OFFSET 0 8 MPCC_OGAM_RAMB_EXP_REGION16_NUM_SEGMENTS 12 14 MPCC_OGAM_RAMB_EXP_REGION17_LUT_OFFSET 16 24 MPCC_OGAM_RAMB_EXP_REGION17_NUM_SEGMENTS 28 30 regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_18_19 0 0x142 4 0 3 MPCC_OGAM_RAMB_EXP_REGION18_LUT_OFFSET 0 8 MPCC_OGAM_RAMB_EXP_REGION18_NUM_SEGMENTS 12 14 MPCC_OGAM_RAMB_EXP_REGION19_LUT_OFFSET 16 24 MPCC_OGAM_RAMB_EXP_REGION19_NUM_SEGMENTS 28 30 regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_20_21 0 0x143 4 0 3 MPCC_OGAM_RAMB_EXP_REGION20_LUT_OFFSET 0 8 MPCC_OGAM_RAMB_EXP_REGION20_NUM_SEGMENTS 12 14 MPCC_OGAM_RAMB_EXP_REGION21_LUT_OFFSET 16 24 MPCC_OGAM_RAMB_EXP_REGION21_NUM_SEGMENTS 28 30 regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_22_23 0 0x144 4 0 3 MPCC_OGAM_RAMB_EXP_REGION22_LUT_OFFSET 0 8 MPCC_OGAM_RAMB_EXP_REGION22_NUM_SEGMENTS 12 14 MPCC_OGAM_RAMB_EXP_REGION23_LUT_OFFSET 16 24 MPCC_OGAM_RAMB_EXP_REGION23_NUM_SEGMENTS 28 30 regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_24_25 0 0x145 4 0 3 MPCC_OGAM_RAMB_EXP_REGION24_LUT_OFFSET 0 8 MPCC_OGAM_RAMB_EXP_REGION24_NUM_SEGMENTS 12 14 MPCC_OGAM_RAMB_EXP_REGION25_LUT_OFFSET 16 24 MPCC_OGAM_RAMB_EXP_REGION25_NUM_SEGMENTS 28 30 regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_26_27 0 0x146 4 0 3 MPCC_OGAM_RAMB_EXP_REGION26_LUT_OFFSET 0 8 MPCC_OGAM_RAMB_EXP_REGION26_NUM_SEGMENTS 12 14 MPCC_OGAM_RAMB_EXP_REGION27_LUT_OFFSET 16 24 MPCC_OGAM_RAMB_EXP_REGION27_NUM_SEGMENTS 28 30 regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_28_29 0 0x147 4 0 3 MPCC_OGAM_RAMB_EXP_REGION28_LUT_OFFSET 0 8 MPCC_OGAM_RAMB_EXP_REGION28_NUM_SEGMENTS 12 14 MPCC_OGAM_RAMB_EXP_REGION29_LUT_OFFSET 16 24 MPCC_OGAM_RAMB_EXP_REGION29_NUM_SEGMENTS 28 30 regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_30_31 0 0x148 4 0 3 MPCC_OGAM_RAMB_EXP_REGION30_LUT_OFFSET 0 8 MPCC_OGAM_RAMB_EXP_REGION30_NUM_SEGMENTS 12 14 MPCC_OGAM_RAMB_EXP_REGION31_LUT_OFFSET 16 24 MPCC_OGAM_RAMB_EXP_REGION31_NUM_SEGMENTS 28 30 regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_32_33 0 0x149 4 0 3 MPCC_OGAM_RAMB_EXP_REGION32_LUT_OFFSET 0 8 MPCC_OGAM_RAMB_EXP_REGION32_NUM_SEGMENTS 12 14 MPCC_OGAM_RAMB_EXP_REGION33_LUT_OFFSET 16 24 MPCC_OGAM_RAMB_EXP_REGION33_NUM_SEGMENTS 28 30 regMPCC_OGAM0_MPCC_GAMUT_REMAP_COEF_FORMAT 0 0x14a 1 0 3 MPCC_GAMUT_REMAP_COEF_FORMAT 0 0 regMPCC_OGAM0_MPCC_GAMUT_REMAP_MODE 0 0x14b 2 0 3 MPCC_GAMUT_REMAP_MODE 0 1 MPCC_GAMUT_REMAP_MODE_CURRENT 7 8 regMPCC_OGAM0_MPC_GAMUT_REMAP_C11_C12_A 0 0x14c 2 0 3 MPCC_GAMUT_REMAP_C11_A 0 15 MPCC_GAMUT_REMAP_C12_A 16 31 regMPCC_OGAM0_MPC_GAMUT_REMAP_C13_C14_A 0 0x14d 2 0 3 MPCC_GAMUT_REMAP_C13_A 0 15 MPCC_GAMUT_REMAP_C14_A 16 31 regMPCC_OGAM0_MPC_GAMUT_REMAP_C21_C22_A 0 0x14e 2 0 3 MPCC_GAMUT_REMAP_C21_A 0 15 MPCC_GAMUT_REMAP_C22_A 16 31 regMPCC_OGAM0_MPC_GAMUT_REMAP_C23_C24_A 0 0x14f 2 0 3 MPCC_GAMUT_REMAP_C23_A 0 15 MPCC_GAMUT_REMAP_C24_A 16 31 regMPCC_OGAM0_MPC_GAMUT_REMAP_C31_C32_A 0 0x150 2 0 3 MPCC_GAMUT_REMAP_C31_A 0 15 MPCC_GAMUT_REMAP_C32_A 16 31 regMPCC_OGAM0_MPC_GAMUT_REMAP_C33_C34_A 0 0x151 2 0 3 MPCC_GAMUT_REMAP_C33_A 0 15 MPCC_GAMUT_REMAP_C34_A 16 31 regMPCC_OGAM0_MPC_GAMUT_REMAP_C11_C12_B 0 0x152 2 0 3 MPCC_GAMUT_REMAP_C11_B 0 15 MPCC_GAMUT_REMAP_C12_B 16 31 regMPCC_OGAM0_MPC_GAMUT_REMAP_C13_C14_B 0 0x153 2 0 3 MPCC_GAMUT_REMAP_C13_B 0 15 MPCC_GAMUT_REMAP_C14_B 16 31 regMPCC_OGAM0_MPC_GAMUT_REMAP_C21_C22_B 0 0x154 2 0 3 MPCC_GAMUT_REMAP_C21_B 0 15 MPCC_GAMUT_REMAP_C22_B 16 31 regMPCC_OGAM0_MPC_GAMUT_REMAP_C23_C24_B 0 0x155 2 0 3 MPCC_GAMUT_REMAP_C23_B 0 15 MPCC_GAMUT_REMAP_C24_B 16 31 regMPCC_OGAM0_MPC_GAMUT_REMAP_C31_C32_B 0 0x156 2 0 3 MPCC_GAMUT_REMAP_C31_B 0 15 MPCC_GAMUT_REMAP_C32_B 16 31 regMPCC_OGAM0_MPC_GAMUT_REMAP_C33_C34_B 0 0x157 2 0 3 MPCC_GAMUT_REMAP_C33_B 0 15 MPCC_GAMUT_REMAP_C34_B 16 31 regMPCC_OGAM1_MPCC_OGAM_CONTROL 0 0x180 5 0 3 MPCC_OGAM_MODE 0 1 MPCC_OGAM_SELECT 2 2 MPCC_OGAM_PWL_DISABLE 3 3 MPCC_OGAM_MODE_CURRENT 7 8 MPCC_OGAM_SELECT_CURRENT 9 9 regMPCC_OGAM1_MPCC_OGAM_LUT_INDEX 0 0x181 1 0 3 MPCC_OGAM_LUT_INDEX 0 8 regMPCC_OGAM1_MPCC_OGAM_LUT_DATA 0 0x182 1 0 3 MPCC_OGAM_LUT_DATA 0 17 regMPCC_OGAM1_MPCC_OGAM_LUT_CONTROL 0 0x183 5 0 3 MPCC_OGAM_LUT_WRITE_COLOR_MASK 0 2 MPCC_OGAM_LUT_READ_COLOR_SEL 3 4 MPCC_OGAM_LUT_READ_DBG 5 5 MPCC_OGAM_LUT_HOST_SEL 6 6 MPCC_OGAM_LUT_CONFIG_MODE 7 7 regMPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_B 0 0x184 2 0 3 MPCC_OGAM_RAMA_EXP_REGION_START_B 0 17 MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_B 20 26 regMPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_G 0 0x185 2 0 3 MPCC_OGAM_RAMA_EXP_REGION_START_G 0 17 MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_G 20 26 regMPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_R 0 0x186 2 0 3 MPCC_OGAM_RAMA_EXP_REGION_START_R 0 17 MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_R 20 26 regMPCC_OGAM1_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B 0 0x187 1 0 3 MPCC_OGAM_RAMA_EXP_REGION_START_SLOPE_B 0 17 regMPCC_OGAM1_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G 0 0x188 1 0 3 MPCC_OGAM_RAMA_EXP_REGION_START_SLOPE_G 0 17 regMPCC_OGAM1_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R 0 0x189 1 0 3 MPCC_OGAM_RAMA_EXP_REGION_START_SLOPE_R 0 17 regMPCC_OGAM1_MPCC_OGAM_RAMA_START_BASE_CNTL_B 0 0x18a 1 0 3 MPCC_OGAM_RAMA_EXP_REGION_START_BASE_B 0 17 regMPCC_OGAM1_MPCC_OGAM_RAMA_START_BASE_CNTL_G 0 0x18b 1 0 3 MPCC_OGAM_RAMA_EXP_REGION_START_BASE_G 0 17 regMPCC_OGAM1_MPCC_OGAM_RAMA_START_BASE_CNTL_R 0 0x18c 1 0 3 MPCC_OGAM_RAMA_EXP_REGION_START_BASE_R 0 17 regMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_B 0 0x18d 1 0 3 MPCC_OGAM_RAMA_EXP_REGION_END_BASE_B 0 17 regMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_B 0 0x18e 2 0 3 MPCC_OGAM_RAMA_EXP_REGION_END_B 0 15 MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_B 16 31 regMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_G 0 0x18f 1 0 3 MPCC_OGAM_RAMA_EXP_REGION_END_BASE_G 0 17 regMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_G 0 0x190 2 0 3 MPCC_OGAM_RAMA_EXP_REGION_END_G 0 15 MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_G 16 31 regMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_R 0 0x191 1 0 3 MPCC_OGAM_RAMA_EXP_REGION_END_BASE_R 0 17 regMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_R 0 0x192 2 0 3 MPCC_OGAM_RAMA_EXP_REGION_END_R 0 15 MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_R 16 31 regMPCC_OGAM1_MPCC_OGAM_RAMA_OFFSET_B 0 0x193 1 0 3 MPCC_OGAM_RAMA_OFFSET_B 0 18 regMPCC_OGAM1_MPCC_OGAM_RAMA_OFFSET_G 0 0x194 1 0 3 MPCC_OGAM_RAMA_OFFSET_G 0 18 regMPCC_OGAM1_MPCC_OGAM_RAMA_OFFSET_R 0 0x195 1 0 3 MPCC_OGAM_RAMA_OFFSET_R 0 18 regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_0_1 0 0x196 4 0 3 MPCC_OGAM_RAMA_EXP_REGION0_LUT_OFFSET 0 8 MPCC_OGAM_RAMA_EXP_REGION0_NUM_SEGMENTS 12 14 MPCC_OGAM_RAMA_EXP_REGION1_LUT_OFFSET 16 24 MPCC_OGAM_RAMA_EXP_REGION1_NUM_SEGMENTS 28 30 regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_2_3 0 0x197 4 0 3 MPCC_OGAM_RAMA_EXP_REGION2_LUT_OFFSET 0 8 MPCC_OGAM_RAMA_EXP_REGION2_NUM_SEGMENTS 12 14 MPCC_OGAM_RAMA_EXP_REGION3_LUT_OFFSET 16 24 MPCC_OGAM_RAMA_EXP_REGION3_NUM_SEGMENTS 28 30 regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_4_5 0 0x198 4 0 3 MPCC_OGAM_RAMA_EXP_REGION4_LUT_OFFSET 0 8 MPCC_OGAM_RAMA_EXP_REGION4_NUM_SEGMENTS 12 14 MPCC_OGAM_RAMA_EXP_REGION5_LUT_OFFSET 16 24 MPCC_OGAM_RAMA_EXP_REGION5_NUM_SEGMENTS 28 30 regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_6_7 0 0x199 4 0 3 MPCC_OGAM_RAMA_EXP_REGION6_LUT_OFFSET 0 8 MPCC_OGAM_RAMA_EXP_REGION6_NUM_SEGMENTS 12 14 MPCC_OGAM_RAMA_EXP_REGION7_LUT_OFFSET 16 24 MPCC_OGAM_RAMA_EXP_REGION7_NUM_SEGMENTS 28 30 regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_8_9 0 0x19a 4 0 3 MPCC_OGAM_RAMA_EXP_REGION8_LUT_OFFSET 0 8 MPCC_OGAM_RAMA_EXP_REGION8_NUM_SEGMENTS 12 14 MPCC_OGAM_RAMA_EXP_REGION9_LUT_OFFSET 16 24 MPCC_OGAM_RAMA_EXP_REGION9_NUM_SEGMENTS 28 30 regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_10_11 0 0x19b 4 0 3 MPCC_OGAM_RAMA_EXP_REGION10_LUT_OFFSET 0 8 MPCC_OGAM_RAMA_EXP_REGION10_NUM_SEGMENTS 12 14 MPCC_OGAM_RAMA_EXP_REGION11_LUT_OFFSET 16 24 MPCC_OGAM_RAMA_EXP_REGION11_NUM_SEGMENTS 28 30 regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_12_13 0 0x19c 4 0 3 MPCC_OGAM_RAMA_EXP_REGION12_LUT_OFFSET 0 8 MPCC_OGAM_RAMA_EXP_REGION12_NUM_SEGMENTS 12 14 MPCC_OGAM_RAMA_EXP_REGION13_LUT_OFFSET 16 24 MPCC_OGAM_RAMA_EXP_REGION13_NUM_SEGMENTS 28 30 regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_14_15 0 0x19d 4 0 3 MPCC_OGAM_RAMA_EXP_REGION14_LUT_OFFSET 0 8 MPCC_OGAM_RAMA_EXP_REGION14_NUM_SEGMENTS 12 14 MPCC_OGAM_RAMA_EXP_REGION15_LUT_OFFSET 16 24 MPCC_OGAM_RAMA_EXP_REGION15_NUM_SEGMENTS 28 30 regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_16_17 0 0x19e 4 0 3 MPCC_OGAM_RAMA_EXP_REGION16_LUT_OFFSET 0 8 MPCC_OGAM_RAMA_EXP_REGION16_NUM_SEGMENTS 12 14 MPCC_OGAM_RAMA_EXP_REGION17_LUT_OFFSET 16 24 MPCC_OGAM_RAMA_EXP_REGION17_NUM_SEGMENTS 28 30 regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_18_19 0 0x19f 4 0 3 MPCC_OGAM_RAMA_EXP_REGION18_LUT_OFFSET 0 8 MPCC_OGAM_RAMA_EXP_REGION18_NUM_SEGMENTS 12 14 MPCC_OGAM_RAMA_EXP_REGION19_LUT_OFFSET 16 24 MPCC_OGAM_RAMA_EXP_REGION19_NUM_SEGMENTS 28 30 regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_20_21 0 0x1a0 4 0 3 MPCC_OGAM_RAMA_EXP_REGION20_LUT_OFFSET 0 8 MPCC_OGAM_RAMA_EXP_REGION20_NUM_SEGMENTS 12 14 MPCC_OGAM_RAMA_EXP_REGION21_LUT_OFFSET 16 24 MPCC_OGAM_RAMA_EXP_REGION21_NUM_SEGMENTS 28 30 regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_22_23 0 0x1a1 4 0 3 MPCC_OGAM_RAMA_EXP_REGION22_LUT_OFFSET 0 8 MPCC_OGAM_RAMA_EXP_REGION22_NUM_SEGMENTS 12 14 MPCC_OGAM_RAMA_EXP_REGION23_LUT_OFFSET 16 24 MPCC_OGAM_RAMA_EXP_REGION23_NUM_SEGMENTS 28 30 regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_24_25 0 0x1a2 4 0 3 MPCC_OGAM_RAMA_EXP_REGION24_LUT_OFFSET 0 8 MPCC_OGAM_RAMA_EXP_REGION24_NUM_SEGMENTS 12 14 MPCC_OGAM_RAMA_EXP_REGION25_LUT_OFFSET 16 24 MPCC_OGAM_RAMA_EXP_REGION25_NUM_SEGMENTS 28 30 regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_26_27 0 0x1a3 4 0 3 MPCC_OGAM_RAMA_EXP_REGION26_LUT_OFFSET 0 8 MPCC_OGAM_RAMA_EXP_REGION26_NUM_SEGMENTS 12 14 MPCC_OGAM_RAMA_EXP_REGION27_LUT_OFFSET 16 24 MPCC_OGAM_RAMA_EXP_REGION27_NUM_SEGMENTS 28 30 regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_28_29 0 0x1a4 4 0 3 MPCC_OGAM_RAMA_EXP_REGION28_LUT_OFFSET 0 8 MPCC_OGAM_RAMA_EXP_REGION28_NUM_SEGMENTS 12 14 MPCC_OGAM_RAMA_EXP_REGION29_LUT_OFFSET 16 24 MPCC_OGAM_RAMA_EXP_REGION29_NUM_SEGMENTS 28 30 regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_30_31 0 0x1a5 4 0 3 MPCC_OGAM_RAMA_EXP_REGION30_LUT_OFFSET 0 8 MPCC_OGAM_RAMA_EXP_REGION30_NUM_SEGMENTS 12 14 MPCC_OGAM_RAMA_EXP_REGION31_LUT_OFFSET 16 24 MPCC_OGAM_RAMA_EXP_REGION31_NUM_SEGMENTS 28 30 regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_32_33 0 0x1a6 4 0 3 MPCC_OGAM_RAMA_EXP_REGION32_LUT_OFFSET 0 8 MPCC_OGAM_RAMA_EXP_REGION32_NUM_SEGMENTS 12 14 MPCC_OGAM_RAMA_EXP_REGION33_LUT_OFFSET 16 24 MPCC_OGAM_RAMA_EXP_REGION33_NUM_SEGMENTS 28 30 regMPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_B 0 0x1a7 2 0 3 MPCC_OGAM_RAMB_EXP_REGION_START_B 0 17 MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_B 20 26 regMPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_G 0 0x1a8 2 0 3 MPCC_OGAM_RAMB_EXP_REGION_START_G 0 17 MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_G 20 26 regMPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_R 0 0x1a9 2 0 3 MPCC_OGAM_RAMB_EXP_REGION_START_R 0 17 MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_R 20 26 regMPCC_OGAM1_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B 0 0x1aa 1 0 3 MPCC_OGAM_RAMB_EXP_REGION_START_SLOPE_B 0 17 regMPCC_OGAM1_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G 0 0x1ab 1 0 3 MPCC_OGAM_RAMB_EXP_REGION_START_SLOPE_G 0 17 regMPCC_OGAM1_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R 0 0x1ac 1 0 3 MPCC_OGAM_RAMB_EXP_REGION_START_SLOPE_R 0 17 regMPCC_OGAM1_MPCC_OGAM_RAMB_START_BASE_CNTL_B 0 0x1ad 1 0 3 MPCC_OGAM_RAMB_EXP_REGION_START_BASE_B 0 17 regMPCC_OGAM1_MPCC_OGAM_RAMB_START_BASE_CNTL_G 0 0x1ae 1 0 3 MPCC_OGAM_RAMB_EXP_REGION_START_BASE_G 0 17 regMPCC_OGAM1_MPCC_OGAM_RAMB_START_BASE_CNTL_R 0 0x1af 1 0 3 MPCC_OGAM_RAMB_EXP_REGION_START_BASE_R 0 17 regMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_B 0 0x1b0 1 0 3 MPCC_OGAM_RAMB_EXP_REGION_END_BASE_B 0 17 regMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_B 0 0x1b1 2 0 3 MPCC_OGAM_RAMB_EXP_REGION_END_B 0 15 MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_B 16 31 regMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_G 0 0x1b2 1 0 3 MPCC_OGAM_RAMB_EXP_REGION_END_BASE_G 0 17 regMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_G 0 0x1b3 2 0 3 MPCC_OGAM_RAMB_EXP_REGION_END_G 0 15 MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_G 16 31 regMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_R 0 0x1b4 1 0 3 MPCC_OGAM_RAMB_EXP_REGION_END_BASE_R 0 17 regMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_R 0 0x1b5 2 0 3 MPCC_OGAM_RAMB_EXP_REGION_END_R 0 15 MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_R 16 31 regMPCC_OGAM1_MPCC_OGAM_RAMB_OFFSET_B 0 0x1b6 1 0 3 MPCC_OGAM_RAMB_OFFSET_B 0 18 regMPCC_OGAM1_MPCC_OGAM_RAMB_OFFSET_G 0 0x1b7 1 0 3 MPCC_OGAM_RAMB_OFFSET_G 0 18 regMPCC_OGAM1_MPCC_OGAM_RAMB_OFFSET_R 0 0x1b8 1 0 3 MPCC_OGAM_RAMB_OFFSET_R 0 18 regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_0_1 0 0x1b9 4 0 3 MPCC_OGAM_RAMB_EXP_REGION0_LUT_OFFSET 0 8 MPCC_OGAM_RAMB_EXP_REGION0_NUM_SEGMENTS 12 14 MPCC_OGAM_RAMB_EXP_REGION1_LUT_OFFSET 16 24 MPCC_OGAM_RAMB_EXP_REGION1_NUM_SEGMENTS 28 30 regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_2_3 0 0x1ba 4 0 3 MPCC_OGAM_RAMB_EXP_REGION2_LUT_OFFSET 0 8 MPCC_OGAM_RAMB_EXP_REGION2_NUM_SEGMENTS 12 14 MPCC_OGAM_RAMB_EXP_REGION3_LUT_OFFSET 16 24 MPCC_OGAM_RAMB_EXP_REGION3_NUM_SEGMENTS 28 30 regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_4_5 0 0x1bb 4 0 3 MPCC_OGAM_RAMB_EXP_REGION4_LUT_OFFSET 0 8 MPCC_OGAM_RAMB_EXP_REGION4_NUM_SEGMENTS 12 14 MPCC_OGAM_RAMB_EXP_REGION5_LUT_OFFSET 16 24 MPCC_OGAM_RAMB_EXP_REGION5_NUM_SEGMENTS 28 30 regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_6_7 0 0x1bc 4 0 3 MPCC_OGAM_RAMB_EXP_REGION6_LUT_OFFSET 0 8 MPCC_OGAM_RAMB_EXP_REGION6_NUM_SEGMENTS 12 14 MPCC_OGAM_RAMB_EXP_REGION7_LUT_OFFSET 16 24 MPCC_OGAM_RAMB_EXP_REGION7_NUM_SEGMENTS 28 30 regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_8_9 0 0x1bd 4 0 3 MPCC_OGAM_RAMB_EXP_REGION8_LUT_OFFSET 0 8 MPCC_OGAM_RAMB_EXP_REGION8_NUM_SEGMENTS 12 14 MPCC_OGAM_RAMB_EXP_REGION9_LUT_OFFSET 16 24 MPCC_OGAM_RAMB_EXP_REGION9_NUM_SEGMENTS 28 30 regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_10_11 0 0x1be 4 0 3 MPCC_OGAM_RAMB_EXP_REGION10_LUT_OFFSET 0 8 MPCC_OGAM_RAMB_EXP_REGION10_NUM_SEGMENTS 12 14 MPCC_OGAM_RAMB_EXP_REGION11_LUT_OFFSET 16 24 MPCC_OGAM_RAMB_EXP_REGION11_NUM_SEGMENTS 28 30 regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_12_13 0 0x1bf 4 0 3 MPCC_OGAM_RAMB_EXP_REGION12_LUT_OFFSET 0 8 MPCC_OGAM_RAMB_EXP_REGION12_NUM_SEGMENTS 12 14 MPCC_OGAM_RAMB_EXP_REGION13_LUT_OFFSET 16 24 MPCC_OGAM_RAMB_EXP_REGION13_NUM_SEGMENTS 28 30 regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_14_15 0 0x1c0 4 0 3 MPCC_OGAM_RAMB_EXP_REGION14_LUT_OFFSET 0 8 MPCC_OGAM_RAMB_EXP_REGION14_NUM_SEGMENTS 12 14 MPCC_OGAM_RAMB_EXP_REGION15_LUT_OFFSET 16 24 MPCC_OGAM_RAMB_EXP_REGION15_NUM_SEGMENTS 28 30 regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_16_17 0 0x1c1 4 0 3 MPCC_OGAM_RAMB_EXP_REGION16_LUT_OFFSET 0 8 MPCC_OGAM_RAMB_EXP_REGION16_NUM_SEGMENTS 12 14 MPCC_OGAM_RAMB_EXP_REGION17_LUT_OFFSET 16 24 MPCC_OGAM_RAMB_EXP_REGION17_NUM_SEGMENTS 28 30 regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_18_19 0 0x1c2 4 0 3 MPCC_OGAM_RAMB_EXP_REGION18_LUT_OFFSET 0 8 MPCC_OGAM_RAMB_EXP_REGION18_NUM_SEGMENTS 12 14 MPCC_OGAM_RAMB_EXP_REGION19_LUT_OFFSET 16 24 MPCC_OGAM_RAMB_EXP_REGION19_NUM_SEGMENTS 28 30 regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_20_21 0 0x1c3 4 0 3 MPCC_OGAM_RAMB_EXP_REGION20_LUT_OFFSET 0 8 MPCC_OGAM_RAMB_EXP_REGION20_NUM_SEGMENTS 12 14 MPCC_OGAM_RAMB_EXP_REGION21_LUT_OFFSET 16 24 MPCC_OGAM_RAMB_EXP_REGION21_NUM_SEGMENTS 28 30 regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_22_23 0 0x1c4 4 0 3 MPCC_OGAM_RAMB_EXP_REGION22_LUT_OFFSET 0 8 MPCC_OGAM_RAMB_EXP_REGION22_NUM_SEGMENTS 12 14 MPCC_OGAM_RAMB_EXP_REGION23_LUT_OFFSET 16 24 MPCC_OGAM_RAMB_EXP_REGION23_NUM_SEGMENTS 28 30 regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_24_25 0 0x1c5 4 0 3 MPCC_OGAM_RAMB_EXP_REGION24_LUT_OFFSET 0 8 MPCC_OGAM_RAMB_EXP_REGION24_NUM_SEGMENTS 12 14 MPCC_OGAM_RAMB_EXP_REGION25_LUT_OFFSET 16 24 MPCC_OGAM_RAMB_EXP_REGION25_NUM_SEGMENTS 28 30 regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_26_27 0 0x1c6 4 0 3 MPCC_OGAM_RAMB_EXP_REGION26_LUT_OFFSET 0 8 MPCC_OGAM_RAMB_EXP_REGION26_NUM_SEGMENTS 12 14 MPCC_OGAM_RAMB_EXP_REGION27_LUT_OFFSET 16 24 MPCC_OGAM_RAMB_EXP_REGION27_NUM_SEGMENTS 28 30 regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_28_29 0 0x1c7 4 0 3 MPCC_OGAM_RAMB_EXP_REGION28_LUT_OFFSET 0 8 MPCC_OGAM_RAMB_EXP_REGION28_NUM_SEGMENTS 12 14 MPCC_OGAM_RAMB_EXP_REGION29_LUT_OFFSET 16 24 MPCC_OGAM_RAMB_EXP_REGION29_NUM_SEGMENTS 28 30 regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_30_31 0 0x1c8 4 0 3 MPCC_OGAM_RAMB_EXP_REGION30_LUT_OFFSET 0 8 MPCC_OGAM_RAMB_EXP_REGION30_NUM_SEGMENTS 12 14 MPCC_OGAM_RAMB_EXP_REGION31_LUT_OFFSET 16 24 MPCC_OGAM_RAMB_EXP_REGION31_NUM_SEGMENTS 28 30 regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_32_33 0 0x1c9 4 0 3 MPCC_OGAM_RAMB_EXP_REGION32_LUT_OFFSET 0 8 MPCC_OGAM_RAMB_EXP_REGION32_NUM_SEGMENTS 12 14 MPCC_OGAM_RAMB_EXP_REGION33_LUT_OFFSET 16 24 MPCC_OGAM_RAMB_EXP_REGION33_NUM_SEGMENTS 28 30 regMPCC_OGAM1_MPCC_GAMUT_REMAP_COEF_FORMAT 0 0x1ca 1 0 3 MPCC_GAMUT_REMAP_COEF_FORMAT 0 0 regMPCC_OGAM1_MPCC_GAMUT_REMAP_MODE 0 0x1cb 2 0 3 MPCC_GAMUT_REMAP_MODE 0 1 MPCC_GAMUT_REMAP_MODE_CURRENT 7 8 regMPCC_OGAM1_MPC_GAMUT_REMAP_C11_C12_A 0 0x1cc 2 0 3 MPCC_GAMUT_REMAP_C11_A 0 15 MPCC_GAMUT_REMAP_C12_A 16 31 regMPCC_OGAM1_MPC_GAMUT_REMAP_C13_C14_A 0 0x1cd 2 0 3 MPCC_GAMUT_REMAP_C13_A 0 15 MPCC_GAMUT_REMAP_C14_A 16 31 regMPCC_OGAM1_MPC_GAMUT_REMAP_C21_C22_A 0 0x1ce 2 0 3 MPCC_GAMUT_REMAP_C21_A 0 15 MPCC_GAMUT_REMAP_C22_A 16 31 regMPCC_OGAM1_MPC_GAMUT_REMAP_C23_C24_A 0 0x1cf 2 0 3 MPCC_GAMUT_REMAP_C23_A 0 15 MPCC_GAMUT_REMAP_C24_A 16 31 regMPCC_OGAM1_MPC_GAMUT_REMAP_C31_C32_A 0 0x1d0 2 0 3 MPCC_GAMUT_REMAP_C31_A 0 15 MPCC_GAMUT_REMAP_C32_A 16 31 regMPCC_OGAM1_MPC_GAMUT_REMAP_C33_C34_A 0 0x1d1 2 0 3 MPCC_GAMUT_REMAP_C33_A 0 15 MPCC_GAMUT_REMAP_C34_A 16 31 regMPCC_OGAM1_MPC_GAMUT_REMAP_C11_C12_B 0 0x1d2 2 0 3 MPCC_GAMUT_REMAP_C11_B 0 15 MPCC_GAMUT_REMAP_C12_B 16 31 regMPCC_OGAM1_MPC_GAMUT_REMAP_C13_C14_B 0 0x1d3 2 0 3 MPCC_GAMUT_REMAP_C13_B 0 15 MPCC_GAMUT_REMAP_C14_B 16 31 regMPCC_OGAM1_MPC_GAMUT_REMAP_C21_C22_B 0 0x1d4 2 0 3 MPCC_GAMUT_REMAP_C21_B 0 15 MPCC_GAMUT_REMAP_C22_B 16 31 regMPCC_OGAM1_MPC_GAMUT_REMAP_C23_C24_B 0 0x1d5 2 0 3 MPCC_GAMUT_REMAP_C23_B 0 15 MPCC_GAMUT_REMAP_C24_B 16 31 regMPCC_OGAM1_MPC_GAMUT_REMAP_C31_C32_B 0 0x1d6 2 0 3 MPCC_GAMUT_REMAP_C31_B 0 15 MPCC_GAMUT_REMAP_C32_B 16 31 regMPCC_OGAM1_MPC_GAMUT_REMAP_C33_C34_B 0 0x1d7 2 0 3 MPCC_GAMUT_REMAP_C33_B 0 15 MPCC_GAMUT_REMAP_C34_B 16 31 regMPCC_OGAM2_MPCC_OGAM_CONTROL 0 0x200 5 0 3 MPCC_OGAM_MODE 0 1 MPCC_OGAM_SELECT 2 2 MPCC_OGAM_PWL_DISABLE 3 3 MPCC_OGAM_MODE_CURRENT 7 8 MPCC_OGAM_SELECT_CURRENT 9 9 regMPCC_OGAM2_MPCC_OGAM_LUT_INDEX 0 0x201 1 0 3 MPCC_OGAM_LUT_INDEX 0 8 regMPCC_OGAM2_MPCC_OGAM_LUT_DATA 0 0x202 1 0 3 MPCC_OGAM_LUT_DATA 0 17 regMPCC_OGAM2_MPCC_OGAM_LUT_CONTROL 0 0x203 5 0 3 MPCC_OGAM_LUT_WRITE_COLOR_MASK 0 2 MPCC_OGAM_LUT_READ_COLOR_SEL 3 4 MPCC_OGAM_LUT_READ_DBG 5 5 MPCC_OGAM_LUT_HOST_SEL 6 6 MPCC_OGAM_LUT_CONFIG_MODE 7 7 regMPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_B 0 0x204 2 0 3 MPCC_OGAM_RAMA_EXP_REGION_START_B 0 17 MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_B 20 26 regMPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_G 0 0x205 2 0 3 MPCC_OGAM_RAMA_EXP_REGION_START_G 0 17 MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_G 20 26 regMPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_R 0 0x206 2 0 3 MPCC_OGAM_RAMA_EXP_REGION_START_R 0 17 MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_R 20 26 regMPCC_OGAM2_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B 0 0x207 1 0 3 MPCC_OGAM_RAMA_EXP_REGION_START_SLOPE_B 0 17 regMPCC_OGAM2_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G 0 0x208 1 0 3 MPCC_OGAM_RAMA_EXP_REGION_START_SLOPE_G 0 17 regMPCC_OGAM2_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R 0 0x209 1 0 3 MPCC_OGAM_RAMA_EXP_REGION_START_SLOPE_R 0 17 regMPCC_OGAM2_MPCC_OGAM_RAMA_START_BASE_CNTL_B 0 0x20a 1 0 3 MPCC_OGAM_RAMA_EXP_REGION_START_BASE_B 0 17 regMPCC_OGAM2_MPCC_OGAM_RAMA_START_BASE_CNTL_G 0 0x20b 1 0 3 MPCC_OGAM_RAMA_EXP_REGION_START_BASE_G 0 17 regMPCC_OGAM2_MPCC_OGAM_RAMA_START_BASE_CNTL_R 0 0x20c 1 0 3 MPCC_OGAM_RAMA_EXP_REGION_START_BASE_R 0 17 regMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL1_B 0 0x20d 1 0 3 MPCC_OGAM_RAMA_EXP_REGION_END_BASE_B 0 17 regMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_B 0 0x20e 2 0 3 MPCC_OGAM_RAMA_EXP_REGION_END_B 0 15 MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_B 16 31 regMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL1_G 0 0x20f 1 0 3 MPCC_OGAM_RAMA_EXP_REGION_END_BASE_G 0 17 regMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_G 0 0x210 2 0 3 MPCC_OGAM_RAMA_EXP_REGION_END_G 0 15 MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_G 16 31 regMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL1_R 0 0x211 1 0 3 MPCC_OGAM_RAMA_EXP_REGION_END_BASE_R 0 17 regMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_R 0 0x212 2 0 3 MPCC_OGAM_RAMA_EXP_REGION_END_R 0 15 MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_R 16 31 regMPCC_OGAM2_MPCC_OGAM_RAMA_OFFSET_B 0 0x213 1 0 3 MPCC_OGAM_RAMA_OFFSET_B 0 18 regMPCC_OGAM2_MPCC_OGAM_RAMA_OFFSET_G 0 0x214 1 0 3 MPCC_OGAM_RAMA_OFFSET_G 0 18 regMPCC_OGAM2_MPCC_OGAM_RAMA_OFFSET_R 0 0x215 1 0 3 MPCC_OGAM_RAMA_OFFSET_R 0 18 regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_0_1 0 0x216 4 0 3 MPCC_OGAM_RAMA_EXP_REGION0_LUT_OFFSET 0 8 MPCC_OGAM_RAMA_EXP_REGION0_NUM_SEGMENTS 12 14 MPCC_OGAM_RAMA_EXP_REGION1_LUT_OFFSET 16 24 MPCC_OGAM_RAMA_EXP_REGION1_NUM_SEGMENTS 28 30 regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_2_3 0 0x217 4 0 3 MPCC_OGAM_RAMA_EXP_REGION2_LUT_OFFSET 0 8 MPCC_OGAM_RAMA_EXP_REGION2_NUM_SEGMENTS 12 14 MPCC_OGAM_RAMA_EXP_REGION3_LUT_OFFSET 16 24 MPCC_OGAM_RAMA_EXP_REGION3_NUM_SEGMENTS 28 30 regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_4_5 0 0x218 4 0 3 MPCC_OGAM_RAMA_EXP_REGION4_LUT_OFFSET 0 8 MPCC_OGAM_RAMA_EXP_REGION4_NUM_SEGMENTS 12 14 MPCC_OGAM_RAMA_EXP_REGION5_LUT_OFFSET 16 24 MPCC_OGAM_RAMA_EXP_REGION5_NUM_SEGMENTS 28 30 regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_6_7 0 0x219 4 0 3 MPCC_OGAM_RAMA_EXP_REGION6_LUT_OFFSET 0 8 MPCC_OGAM_RAMA_EXP_REGION6_NUM_SEGMENTS 12 14 MPCC_OGAM_RAMA_EXP_REGION7_LUT_OFFSET 16 24 MPCC_OGAM_RAMA_EXP_REGION7_NUM_SEGMENTS 28 30 regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_8_9 0 0x21a 4 0 3 MPCC_OGAM_RAMA_EXP_REGION8_LUT_OFFSET 0 8 MPCC_OGAM_RAMA_EXP_REGION8_NUM_SEGMENTS 12 14 MPCC_OGAM_RAMA_EXP_REGION9_LUT_OFFSET 16 24 MPCC_OGAM_RAMA_EXP_REGION9_NUM_SEGMENTS 28 30 regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_10_11 0 0x21b 4 0 3 MPCC_OGAM_RAMA_EXP_REGION10_LUT_OFFSET 0 8 MPCC_OGAM_RAMA_EXP_REGION10_NUM_SEGMENTS 12 14 MPCC_OGAM_RAMA_EXP_REGION11_LUT_OFFSET 16 24 MPCC_OGAM_RAMA_EXP_REGION11_NUM_SEGMENTS 28 30 regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_12_13 0 0x21c 4 0 3 MPCC_OGAM_RAMA_EXP_REGION12_LUT_OFFSET 0 8 MPCC_OGAM_RAMA_EXP_REGION12_NUM_SEGMENTS 12 14 MPCC_OGAM_RAMA_EXP_REGION13_LUT_OFFSET 16 24 MPCC_OGAM_RAMA_EXP_REGION13_NUM_SEGMENTS 28 30 regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_14_15 0 0x21d 4 0 3 MPCC_OGAM_RAMA_EXP_REGION14_LUT_OFFSET 0 8 MPCC_OGAM_RAMA_EXP_REGION14_NUM_SEGMENTS 12 14 MPCC_OGAM_RAMA_EXP_REGION15_LUT_OFFSET 16 24 MPCC_OGAM_RAMA_EXP_REGION15_NUM_SEGMENTS 28 30 regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_16_17 0 0x21e 4 0 3 MPCC_OGAM_RAMA_EXP_REGION16_LUT_OFFSET 0 8 MPCC_OGAM_RAMA_EXP_REGION16_NUM_SEGMENTS 12 14 MPCC_OGAM_RAMA_EXP_REGION17_LUT_OFFSET 16 24 MPCC_OGAM_RAMA_EXP_REGION17_NUM_SEGMENTS 28 30 regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_18_19 0 0x21f 4 0 3 MPCC_OGAM_RAMA_EXP_REGION18_LUT_OFFSET 0 8 MPCC_OGAM_RAMA_EXP_REGION18_NUM_SEGMENTS 12 14 MPCC_OGAM_RAMA_EXP_REGION19_LUT_OFFSET 16 24 MPCC_OGAM_RAMA_EXP_REGION19_NUM_SEGMENTS 28 30 regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_20_21 0 0x220 4 0 3 MPCC_OGAM_RAMA_EXP_REGION20_LUT_OFFSET 0 8 MPCC_OGAM_RAMA_EXP_REGION20_NUM_SEGMENTS 12 14 MPCC_OGAM_RAMA_EXP_REGION21_LUT_OFFSET 16 24 MPCC_OGAM_RAMA_EXP_REGION21_NUM_SEGMENTS 28 30 regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_22_23 0 0x221 4 0 3 MPCC_OGAM_RAMA_EXP_REGION22_LUT_OFFSET 0 8 MPCC_OGAM_RAMA_EXP_REGION22_NUM_SEGMENTS 12 14 MPCC_OGAM_RAMA_EXP_REGION23_LUT_OFFSET 16 24 MPCC_OGAM_RAMA_EXP_REGION23_NUM_SEGMENTS 28 30 regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_24_25 0 0x222 4 0 3 MPCC_OGAM_RAMA_EXP_REGION24_LUT_OFFSET 0 8 MPCC_OGAM_RAMA_EXP_REGION24_NUM_SEGMENTS 12 14 MPCC_OGAM_RAMA_EXP_REGION25_LUT_OFFSET 16 24 MPCC_OGAM_RAMA_EXP_REGION25_NUM_SEGMENTS 28 30 regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_26_27 0 0x223 4 0 3 MPCC_OGAM_RAMA_EXP_REGION26_LUT_OFFSET 0 8 MPCC_OGAM_RAMA_EXP_REGION26_NUM_SEGMENTS 12 14 MPCC_OGAM_RAMA_EXP_REGION27_LUT_OFFSET 16 24 MPCC_OGAM_RAMA_EXP_REGION27_NUM_SEGMENTS 28 30 regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_28_29 0 0x224 4 0 3 MPCC_OGAM_RAMA_EXP_REGION28_LUT_OFFSET 0 8 MPCC_OGAM_RAMA_EXP_REGION28_NUM_SEGMENTS 12 14 MPCC_OGAM_RAMA_EXP_REGION29_LUT_OFFSET 16 24 MPCC_OGAM_RAMA_EXP_REGION29_NUM_SEGMENTS 28 30 regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_30_31 0 0x225 4 0 3 MPCC_OGAM_RAMA_EXP_REGION30_LUT_OFFSET 0 8 MPCC_OGAM_RAMA_EXP_REGION30_NUM_SEGMENTS 12 14 MPCC_OGAM_RAMA_EXP_REGION31_LUT_OFFSET 16 24 MPCC_OGAM_RAMA_EXP_REGION31_NUM_SEGMENTS 28 30 regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_32_33 0 0x226 4 0 3 MPCC_OGAM_RAMA_EXP_REGION32_LUT_OFFSET 0 8 MPCC_OGAM_RAMA_EXP_REGION32_NUM_SEGMENTS 12 14 MPCC_OGAM_RAMA_EXP_REGION33_LUT_OFFSET 16 24 MPCC_OGAM_RAMA_EXP_REGION33_NUM_SEGMENTS 28 30 regMPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_B 0 0x227 2 0 3 MPCC_OGAM_RAMB_EXP_REGION_START_B 0 17 MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_B 20 26 regMPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_G 0 0x228 2 0 3 MPCC_OGAM_RAMB_EXP_REGION_START_G 0 17 MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_G 20 26 regMPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_R 0 0x229 2 0 3 MPCC_OGAM_RAMB_EXP_REGION_START_R 0 17 MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_R 20 26 regMPCC_OGAM2_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B 0 0x22a 1 0 3 MPCC_OGAM_RAMB_EXP_REGION_START_SLOPE_B 0 17 regMPCC_OGAM2_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G 0 0x22b 1 0 3 MPCC_OGAM_RAMB_EXP_REGION_START_SLOPE_G 0 17 regMPCC_OGAM2_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R 0 0x22c 1 0 3 MPCC_OGAM_RAMB_EXP_REGION_START_SLOPE_R 0 17 regMPCC_OGAM2_MPCC_OGAM_RAMB_START_BASE_CNTL_B 0 0x22d 1 0 3 MPCC_OGAM_RAMB_EXP_REGION_START_BASE_B 0 17 regMPCC_OGAM2_MPCC_OGAM_RAMB_START_BASE_CNTL_G 0 0x22e 1 0 3 MPCC_OGAM_RAMB_EXP_REGION_START_BASE_G 0 17 regMPCC_OGAM2_MPCC_OGAM_RAMB_START_BASE_CNTL_R 0 0x22f 1 0 3 MPCC_OGAM_RAMB_EXP_REGION_START_BASE_R 0 17 regMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL1_B 0 0x230 1 0 3 MPCC_OGAM_RAMB_EXP_REGION_END_BASE_B 0 17 regMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_B 0 0x231 2 0 3 MPCC_OGAM_RAMB_EXP_REGION_END_B 0 15 MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_B 16 31 regMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL1_G 0 0x232 1 0 3 MPCC_OGAM_RAMB_EXP_REGION_END_BASE_G 0 17 regMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_G 0 0x233 2 0 3 MPCC_OGAM_RAMB_EXP_REGION_END_G 0 15 MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_G 16 31 regMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL1_R 0 0x234 1 0 3 MPCC_OGAM_RAMB_EXP_REGION_END_BASE_R 0 17 regMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_R 0 0x235 2 0 3 MPCC_OGAM_RAMB_EXP_REGION_END_R 0 15 MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_R 16 31 regMPCC_OGAM2_MPCC_OGAM_RAMB_OFFSET_B 0 0x236 1 0 3 MPCC_OGAM_RAMB_OFFSET_B 0 18 regMPCC_OGAM2_MPCC_OGAM_RAMB_OFFSET_G 0 0x237 1 0 3 MPCC_OGAM_RAMB_OFFSET_G 0 18 regMPCC_OGAM2_MPCC_OGAM_RAMB_OFFSET_R 0 0x238 1 0 3 MPCC_OGAM_RAMB_OFFSET_R 0 18 regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_0_1 0 0x239 4 0 3 MPCC_OGAM_RAMB_EXP_REGION0_LUT_OFFSET 0 8 MPCC_OGAM_RAMB_EXP_REGION0_NUM_SEGMENTS 12 14 MPCC_OGAM_RAMB_EXP_REGION1_LUT_OFFSET 16 24 MPCC_OGAM_RAMB_EXP_REGION1_NUM_SEGMENTS 28 30 regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_2_3 0 0x23a 4 0 3 MPCC_OGAM_RAMB_EXP_REGION2_LUT_OFFSET 0 8 MPCC_OGAM_RAMB_EXP_REGION2_NUM_SEGMENTS 12 14 MPCC_OGAM_RAMB_EXP_REGION3_LUT_OFFSET 16 24 MPCC_OGAM_RAMB_EXP_REGION3_NUM_SEGMENTS 28 30 regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_4_5 0 0x23b 4 0 3 MPCC_OGAM_RAMB_EXP_REGION4_LUT_OFFSET 0 8 MPCC_OGAM_RAMB_EXP_REGION4_NUM_SEGMENTS 12 14 MPCC_OGAM_RAMB_EXP_REGION5_LUT_OFFSET 16 24 MPCC_OGAM_RAMB_EXP_REGION5_NUM_SEGMENTS 28 30 regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_6_7 0 0x23c 4 0 3 MPCC_OGAM_RAMB_EXP_REGION6_LUT_OFFSET 0 8 MPCC_OGAM_RAMB_EXP_REGION6_NUM_SEGMENTS 12 14 MPCC_OGAM_RAMB_EXP_REGION7_LUT_OFFSET 16 24 MPCC_OGAM_RAMB_EXP_REGION7_NUM_SEGMENTS 28 30 regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_8_9 0 0x23d 4 0 3 MPCC_OGAM_RAMB_EXP_REGION8_LUT_OFFSET 0 8 MPCC_OGAM_RAMB_EXP_REGION8_NUM_SEGMENTS 12 14 MPCC_OGAM_RAMB_EXP_REGION9_LUT_OFFSET 16 24 MPCC_OGAM_RAMB_EXP_REGION9_NUM_SEGMENTS 28 30 regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_10_11 0 0x23e 4 0 3 MPCC_OGAM_RAMB_EXP_REGION10_LUT_OFFSET 0 8 MPCC_OGAM_RAMB_EXP_REGION10_NUM_SEGMENTS 12 14 MPCC_OGAM_RAMB_EXP_REGION11_LUT_OFFSET 16 24 MPCC_OGAM_RAMB_EXP_REGION11_NUM_SEGMENTS 28 30 regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_12_13 0 0x23f 4 0 3 MPCC_OGAM_RAMB_EXP_REGION12_LUT_OFFSET 0 8 MPCC_OGAM_RAMB_EXP_REGION12_NUM_SEGMENTS 12 14 MPCC_OGAM_RAMB_EXP_REGION13_LUT_OFFSET 16 24 MPCC_OGAM_RAMB_EXP_REGION13_NUM_SEGMENTS 28 30 regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_14_15 0 0x240 4 0 3 MPCC_OGAM_RAMB_EXP_REGION14_LUT_OFFSET 0 8 MPCC_OGAM_RAMB_EXP_REGION14_NUM_SEGMENTS 12 14 MPCC_OGAM_RAMB_EXP_REGION15_LUT_OFFSET 16 24 MPCC_OGAM_RAMB_EXP_REGION15_NUM_SEGMENTS 28 30 regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_16_17 0 0x241 4 0 3 MPCC_OGAM_RAMB_EXP_REGION16_LUT_OFFSET 0 8 MPCC_OGAM_RAMB_EXP_REGION16_NUM_SEGMENTS 12 14 MPCC_OGAM_RAMB_EXP_REGION17_LUT_OFFSET 16 24 MPCC_OGAM_RAMB_EXP_REGION17_NUM_SEGMENTS 28 30 regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_18_19 0 0x242 4 0 3 MPCC_OGAM_RAMB_EXP_REGION18_LUT_OFFSET 0 8 MPCC_OGAM_RAMB_EXP_REGION18_NUM_SEGMENTS 12 14 MPCC_OGAM_RAMB_EXP_REGION19_LUT_OFFSET 16 24 MPCC_OGAM_RAMB_EXP_REGION19_NUM_SEGMENTS 28 30 regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_20_21 0 0x243 4 0 3 MPCC_OGAM_RAMB_EXP_REGION20_LUT_OFFSET 0 8 MPCC_OGAM_RAMB_EXP_REGION20_NUM_SEGMENTS 12 14 MPCC_OGAM_RAMB_EXP_REGION21_LUT_OFFSET 16 24 MPCC_OGAM_RAMB_EXP_REGION21_NUM_SEGMENTS 28 30 regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_22_23 0 0x244 4 0 3 MPCC_OGAM_RAMB_EXP_REGION22_LUT_OFFSET 0 8 MPCC_OGAM_RAMB_EXP_REGION22_NUM_SEGMENTS 12 14 MPCC_OGAM_RAMB_EXP_REGION23_LUT_OFFSET 16 24 MPCC_OGAM_RAMB_EXP_REGION23_NUM_SEGMENTS 28 30 regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_24_25 0 0x245 4 0 3 MPCC_OGAM_RAMB_EXP_REGION24_LUT_OFFSET 0 8 MPCC_OGAM_RAMB_EXP_REGION24_NUM_SEGMENTS 12 14 MPCC_OGAM_RAMB_EXP_REGION25_LUT_OFFSET 16 24 MPCC_OGAM_RAMB_EXP_REGION25_NUM_SEGMENTS 28 30 regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_26_27 0 0x246 4 0 3 MPCC_OGAM_RAMB_EXP_REGION26_LUT_OFFSET 0 8 MPCC_OGAM_RAMB_EXP_REGION26_NUM_SEGMENTS 12 14 MPCC_OGAM_RAMB_EXP_REGION27_LUT_OFFSET 16 24 MPCC_OGAM_RAMB_EXP_REGION27_NUM_SEGMENTS 28 30 regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_28_29 0 0x247 4 0 3 MPCC_OGAM_RAMB_EXP_REGION28_LUT_OFFSET 0 8 MPCC_OGAM_RAMB_EXP_REGION28_NUM_SEGMENTS 12 14 MPCC_OGAM_RAMB_EXP_REGION29_LUT_OFFSET 16 24 MPCC_OGAM_RAMB_EXP_REGION29_NUM_SEGMENTS 28 30 regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_30_31 0 0x248 4 0 3 MPCC_OGAM_RAMB_EXP_REGION30_LUT_OFFSET 0 8 MPCC_OGAM_RAMB_EXP_REGION30_NUM_SEGMENTS 12 14 MPCC_OGAM_RAMB_EXP_REGION31_LUT_OFFSET 16 24 MPCC_OGAM_RAMB_EXP_REGION31_NUM_SEGMENTS 28 30 regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_32_33 0 0x249 4 0 3 MPCC_OGAM_RAMB_EXP_REGION32_LUT_OFFSET 0 8 MPCC_OGAM_RAMB_EXP_REGION32_NUM_SEGMENTS 12 14 MPCC_OGAM_RAMB_EXP_REGION33_LUT_OFFSET 16 24 MPCC_OGAM_RAMB_EXP_REGION33_NUM_SEGMENTS 28 30 regMPCC_OGAM2_MPCC_GAMUT_REMAP_COEF_FORMAT 0 0x24a 1 0 3 MPCC_GAMUT_REMAP_COEF_FORMAT 0 0 regMPCC_OGAM2_MPCC_GAMUT_REMAP_MODE 0 0x24b 2 0 3 MPCC_GAMUT_REMAP_MODE 0 1 MPCC_GAMUT_REMAP_MODE_CURRENT 7 8 regMPCC_OGAM2_MPC_GAMUT_REMAP_C11_C12_A 0 0x24c 2 0 3 MPCC_GAMUT_REMAP_C11_A 0 15 MPCC_GAMUT_REMAP_C12_A 16 31 regMPCC_OGAM2_MPC_GAMUT_REMAP_C13_C14_A 0 0x24d 2 0 3 MPCC_GAMUT_REMAP_C13_A 0 15 MPCC_GAMUT_REMAP_C14_A 16 31 regMPCC_OGAM2_MPC_GAMUT_REMAP_C21_C22_A 0 0x24e 2 0 3 MPCC_GAMUT_REMAP_C21_A 0 15 MPCC_GAMUT_REMAP_C22_A 16 31 regMPCC_OGAM2_MPC_GAMUT_REMAP_C23_C24_A 0 0x24f 2 0 3 MPCC_GAMUT_REMAP_C23_A 0 15 MPCC_GAMUT_REMAP_C24_A 16 31 regMPCC_OGAM2_MPC_GAMUT_REMAP_C31_C32_A 0 0x250 2 0 3 MPCC_GAMUT_REMAP_C31_A 0 15 MPCC_GAMUT_REMAP_C32_A 16 31 regMPCC_OGAM2_MPC_GAMUT_REMAP_C33_C34_A 0 0x251 2 0 3 MPCC_GAMUT_REMAP_C33_A 0 15 MPCC_GAMUT_REMAP_C34_A 16 31 regMPCC_OGAM2_MPC_GAMUT_REMAP_C11_C12_B 0 0x252 2 0 3 MPCC_GAMUT_REMAP_C11_B 0 15 MPCC_GAMUT_REMAP_C12_B 16 31 regMPCC_OGAM2_MPC_GAMUT_REMAP_C13_C14_B 0 0x253 2 0 3 MPCC_GAMUT_REMAP_C13_B 0 15 MPCC_GAMUT_REMAP_C14_B 16 31 regMPCC_OGAM2_MPC_GAMUT_REMAP_C21_C22_B 0 0x254 2 0 3 MPCC_GAMUT_REMAP_C21_B 0 15 MPCC_GAMUT_REMAP_C22_B 16 31 regMPCC_OGAM2_MPC_GAMUT_REMAP_C23_C24_B 0 0x255 2 0 3 MPCC_GAMUT_REMAP_C23_B 0 15 MPCC_GAMUT_REMAP_C24_B 16 31 regMPCC_OGAM2_MPC_GAMUT_REMAP_C31_C32_B 0 0x256 2 0 3 MPCC_GAMUT_REMAP_C31_B 0 15 MPCC_GAMUT_REMAP_C32_B 16 31 regMPCC_OGAM2_MPC_GAMUT_REMAP_C33_C34_B 0 0x257 2 0 3 MPCC_GAMUT_REMAP_C33_B 0 15 MPCC_GAMUT_REMAP_C34_B 16 31 regMPCC_OGAM3_MPCC_OGAM_CONTROL 0 0x280 5 0 3 MPCC_OGAM_MODE 0 1 MPCC_OGAM_SELECT 2 2 MPCC_OGAM_PWL_DISABLE 3 3 MPCC_OGAM_MODE_CURRENT 7 8 MPCC_OGAM_SELECT_CURRENT 9 9 regMPCC_OGAM3_MPCC_OGAM_LUT_INDEX 0 0x281 1 0 3 MPCC_OGAM_LUT_INDEX 0 8 regMPCC_OGAM3_MPCC_OGAM_LUT_DATA 0 0x282 1 0 3 MPCC_OGAM_LUT_DATA 0 17 regMPCC_OGAM3_MPCC_OGAM_LUT_CONTROL 0 0x283 5 0 3 MPCC_OGAM_LUT_WRITE_COLOR_MASK 0 2 MPCC_OGAM_LUT_READ_COLOR_SEL 3 4 MPCC_OGAM_LUT_READ_DBG 5 5 MPCC_OGAM_LUT_HOST_SEL 6 6 MPCC_OGAM_LUT_CONFIG_MODE 7 7 regMPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_B 0 0x284 2 0 3 MPCC_OGAM_RAMA_EXP_REGION_START_B 0 17 MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_B 20 26 regMPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_G 0 0x285 2 0 3 MPCC_OGAM_RAMA_EXP_REGION_START_G 0 17 MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_G 20 26 regMPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_R 0 0x286 2 0 3 MPCC_OGAM_RAMA_EXP_REGION_START_R 0 17 MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_R 20 26 regMPCC_OGAM3_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B 0 0x287 1 0 3 MPCC_OGAM_RAMA_EXP_REGION_START_SLOPE_B 0 17 regMPCC_OGAM3_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G 0 0x288 1 0 3 MPCC_OGAM_RAMA_EXP_REGION_START_SLOPE_G 0 17 regMPCC_OGAM3_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R 0 0x289 1 0 3 MPCC_OGAM_RAMA_EXP_REGION_START_SLOPE_R 0 17 regMPCC_OGAM3_MPCC_OGAM_RAMA_START_BASE_CNTL_B 0 0x28a 1 0 3 MPCC_OGAM_RAMA_EXP_REGION_START_BASE_B 0 17 regMPCC_OGAM3_MPCC_OGAM_RAMA_START_BASE_CNTL_G 0 0x28b 1 0 3 MPCC_OGAM_RAMA_EXP_REGION_START_BASE_G 0 17 regMPCC_OGAM3_MPCC_OGAM_RAMA_START_BASE_CNTL_R 0 0x28c 1 0 3 MPCC_OGAM_RAMA_EXP_REGION_START_BASE_R 0 17 regMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL1_B 0 0x28d 1 0 3 MPCC_OGAM_RAMA_EXP_REGION_END_BASE_B 0 17 regMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_B 0 0x28e 2 0 3 MPCC_OGAM_RAMA_EXP_REGION_END_B 0 15 MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_B 16 31 regMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL1_G 0 0x28f 1 0 3 MPCC_OGAM_RAMA_EXP_REGION_END_BASE_G 0 17 regMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_G 0 0x290 2 0 3 MPCC_OGAM_RAMA_EXP_REGION_END_G 0 15 MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_G 16 31 regMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL1_R 0 0x291 1 0 3 MPCC_OGAM_RAMA_EXP_REGION_END_BASE_R 0 17 regMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_R 0 0x292 2 0 3 MPCC_OGAM_RAMA_EXP_REGION_END_R 0 15 MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_R 16 31 regMPCC_OGAM3_MPCC_OGAM_RAMA_OFFSET_B 0 0x293 1 0 3 MPCC_OGAM_RAMA_OFFSET_B 0 18 regMPCC_OGAM3_MPCC_OGAM_RAMA_OFFSET_G 0 0x294 1 0 3 MPCC_OGAM_RAMA_OFFSET_G 0 18 regMPCC_OGAM3_MPCC_OGAM_RAMA_OFFSET_R 0 0x295 1 0 3 MPCC_OGAM_RAMA_OFFSET_R 0 18 regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_0_1 0 0x296 4 0 3 MPCC_OGAM_RAMA_EXP_REGION0_LUT_OFFSET 0 8 MPCC_OGAM_RAMA_EXP_REGION0_NUM_SEGMENTS 12 14 MPCC_OGAM_RAMA_EXP_REGION1_LUT_OFFSET 16 24 MPCC_OGAM_RAMA_EXP_REGION1_NUM_SEGMENTS 28 30 regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_2_3 0 0x297 4 0 3 MPCC_OGAM_RAMA_EXP_REGION2_LUT_OFFSET 0 8 MPCC_OGAM_RAMA_EXP_REGION2_NUM_SEGMENTS 12 14 MPCC_OGAM_RAMA_EXP_REGION3_LUT_OFFSET 16 24 MPCC_OGAM_RAMA_EXP_REGION3_NUM_SEGMENTS 28 30 regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_4_5 0 0x298 4 0 3 MPCC_OGAM_RAMA_EXP_REGION4_LUT_OFFSET 0 8 MPCC_OGAM_RAMA_EXP_REGION4_NUM_SEGMENTS 12 14 MPCC_OGAM_RAMA_EXP_REGION5_LUT_OFFSET 16 24 MPCC_OGAM_RAMA_EXP_REGION5_NUM_SEGMENTS 28 30 regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_6_7 0 0x299 4 0 3 MPCC_OGAM_RAMA_EXP_REGION6_LUT_OFFSET 0 8 MPCC_OGAM_RAMA_EXP_REGION6_NUM_SEGMENTS 12 14 MPCC_OGAM_RAMA_EXP_REGION7_LUT_OFFSET 16 24 MPCC_OGAM_RAMA_EXP_REGION7_NUM_SEGMENTS 28 30 regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_8_9 0 0x29a 4 0 3 MPCC_OGAM_RAMA_EXP_REGION8_LUT_OFFSET 0 8 MPCC_OGAM_RAMA_EXP_REGION8_NUM_SEGMENTS 12 14 MPCC_OGAM_RAMA_EXP_REGION9_LUT_OFFSET 16 24 MPCC_OGAM_RAMA_EXP_REGION9_NUM_SEGMENTS 28 30 regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_10_11 0 0x29b 4 0 3 MPCC_OGAM_RAMA_EXP_REGION10_LUT_OFFSET 0 8 MPCC_OGAM_RAMA_EXP_REGION10_NUM_SEGMENTS 12 14 MPCC_OGAM_RAMA_EXP_REGION11_LUT_OFFSET 16 24 MPCC_OGAM_RAMA_EXP_REGION11_NUM_SEGMENTS 28 30 regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_12_13 0 0x29c 4 0 3 MPCC_OGAM_RAMA_EXP_REGION12_LUT_OFFSET 0 8 MPCC_OGAM_RAMA_EXP_REGION12_NUM_SEGMENTS 12 14 MPCC_OGAM_RAMA_EXP_REGION13_LUT_OFFSET 16 24 MPCC_OGAM_RAMA_EXP_REGION13_NUM_SEGMENTS 28 30 regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_14_15 0 0x29d 4 0 3 MPCC_OGAM_RAMA_EXP_REGION14_LUT_OFFSET 0 8 MPCC_OGAM_RAMA_EXP_REGION14_NUM_SEGMENTS 12 14 MPCC_OGAM_RAMA_EXP_REGION15_LUT_OFFSET 16 24 MPCC_OGAM_RAMA_EXP_REGION15_NUM_SEGMENTS 28 30 regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_16_17 0 0x29e 4 0 3 MPCC_OGAM_RAMA_EXP_REGION16_LUT_OFFSET 0 8 MPCC_OGAM_RAMA_EXP_REGION16_NUM_SEGMENTS 12 14 MPCC_OGAM_RAMA_EXP_REGION17_LUT_OFFSET 16 24 MPCC_OGAM_RAMA_EXP_REGION17_NUM_SEGMENTS 28 30 regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_18_19 0 0x29f 4 0 3 MPCC_OGAM_RAMA_EXP_REGION18_LUT_OFFSET 0 8 MPCC_OGAM_RAMA_EXP_REGION18_NUM_SEGMENTS 12 14 MPCC_OGAM_RAMA_EXP_REGION19_LUT_OFFSET 16 24 MPCC_OGAM_RAMA_EXP_REGION19_NUM_SEGMENTS 28 30 regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_20_21 0 0x2a0 4 0 3 MPCC_OGAM_RAMA_EXP_REGION20_LUT_OFFSET 0 8 MPCC_OGAM_RAMA_EXP_REGION20_NUM_SEGMENTS 12 14 MPCC_OGAM_RAMA_EXP_REGION21_LUT_OFFSET 16 24 MPCC_OGAM_RAMA_EXP_REGION21_NUM_SEGMENTS 28 30 regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_22_23 0 0x2a1 4 0 3 MPCC_OGAM_RAMA_EXP_REGION22_LUT_OFFSET 0 8 MPCC_OGAM_RAMA_EXP_REGION22_NUM_SEGMENTS 12 14 MPCC_OGAM_RAMA_EXP_REGION23_LUT_OFFSET 16 24 MPCC_OGAM_RAMA_EXP_REGION23_NUM_SEGMENTS 28 30 regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_24_25 0 0x2a2 4 0 3 MPCC_OGAM_RAMA_EXP_REGION24_LUT_OFFSET 0 8 MPCC_OGAM_RAMA_EXP_REGION24_NUM_SEGMENTS 12 14 MPCC_OGAM_RAMA_EXP_REGION25_LUT_OFFSET 16 24 MPCC_OGAM_RAMA_EXP_REGION25_NUM_SEGMENTS 28 30 regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_26_27 0 0x2a3 4 0 3 MPCC_OGAM_RAMA_EXP_REGION26_LUT_OFFSET 0 8 MPCC_OGAM_RAMA_EXP_REGION26_NUM_SEGMENTS 12 14 MPCC_OGAM_RAMA_EXP_REGION27_LUT_OFFSET 16 24 MPCC_OGAM_RAMA_EXP_REGION27_NUM_SEGMENTS 28 30 regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_28_29 0 0x2a4 4 0 3 MPCC_OGAM_RAMA_EXP_REGION28_LUT_OFFSET 0 8 MPCC_OGAM_RAMA_EXP_REGION28_NUM_SEGMENTS 12 14 MPCC_OGAM_RAMA_EXP_REGION29_LUT_OFFSET 16 24 MPCC_OGAM_RAMA_EXP_REGION29_NUM_SEGMENTS 28 30 regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_30_31 0 0x2a5 4 0 3 MPCC_OGAM_RAMA_EXP_REGION30_LUT_OFFSET 0 8 MPCC_OGAM_RAMA_EXP_REGION30_NUM_SEGMENTS 12 14 MPCC_OGAM_RAMA_EXP_REGION31_LUT_OFFSET 16 24 MPCC_OGAM_RAMA_EXP_REGION31_NUM_SEGMENTS 28 30 regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_32_33 0 0x2a6 4 0 3 MPCC_OGAM_RAMA_EXP_REGION32_LUT_OFFSET 0 8 MPCC_OGAM_RAMA_EXP_REGION32_NUM_SEGMENTS 12 14 MPCC_OGAM_RAMA_EXP_REGION33_LUT_OFFSET 16 24 MPCC_OGAM_RAMA_EXP_REGION33_NUM_SEGMENTS 28 30 regMPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_B 0 0x2a7 2 0 3 MPCC_OGAM_RAMB_EXP_REGION_START_B 0 17 MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_B 20 26 regMPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_G 0 0x2a8 2 0 3 MPCC_OGAM_RAMB_EXP_REGION_START_G 0 17 MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_G 20 26 regMPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_R 0 0x2a9 2 0 3 MPCC_OGAM_RAMB_EXP_REGION_START_R 0 17 MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_R 20 26 regMPCC_OGAM3_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B 0 0x2aa 1 0 3 MPCC_OGAM_RAMB_EXP_REGION_START_SLOPE_B 0 17 regMPCC_OGAM3_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G 0 0x2ab 1 0 3 MPCC_OGAM_RAMB_EXP_REGION_START_SLOPE_G 0 17 regMPCC_OGAM3_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R 0 0x2ac 1 0 3 MPCC_OGAM_RAMB_EXP_REGION_START_SLOPE_R 0 17 regMPCC_OGAM3_MPCC_OGAM_RAMB_START_BASE_CNTL_B 0 0x2ad 1 0 3 MPCC_OGAM_RAMB_EXP_REGION_START_BASE_B 0 17 regMPCC_OGAM3_MPCC_OGAM_RAMB_START_BASE_CNTL_G 0 0x2ae 1 0 3 MPCC_OGAM_RAMB_EXP_REGION_START_BASE_G 0 17 regMPCC_OGAM3_MPCC_OGAM_RAMB_START_BASE_CNTL_R 0 0x2af 1 0 3 MPCC_OGAM_RAMB_EXP_REGION_START_BASE_R 0 17 regMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL1_B 0 0x2b0 1 0 3 MPCC_OGAM_RAMB_EXP_REGION_END_BASE_B 0 17 regMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_B 0 0x2b1 2 0 3 MPCC_OGAM_RAMB_EXP_REGION_END_B 0 15 MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_B 16 31 regMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL1_G 0 0x2b2 1 0 3 MPCC_OGAM_RAMB_EXP_REGION_END_BASE_G 0 17 regMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_G 0 0x2b3 2 0 3 MPCC_OGAM_RAMB_EXP_REGION_END_G 0 15 MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_G 16 31 regMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL1_R 0 0x2b4 1 0 3 MPCC_OGAM_RAMB_EXP_REGION_END_BASE_R 0 17 regMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_R 0 0x2b5 2 0 3 MPCC_OGAM_RAMB_EXP_REGION_END_R 0 15 MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_R 16 31 regMPCC_OGAM3_MPCC_OGAM_RAMB_OFFSET_B 0 0x2b6 1 0 3 MPCC_OGAM_RAMB_OFFSET_B 0 18 regMPCC_OGAM3_MPCC_OGAM_RAMB_OFFSET_G 0 0x2b7 1 0 3 MPCC_OGAM_RAMB_OFFSET_G 0 18 regMPCC_OGAM3_MPCC_OGAM_RAMB_OFFSET_R 0 0x2b8 1 0 3 MPCC_OGAM_RAMB_OFFSET_R 0 18 regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_0_1 0 0x2b9 4 0 3 MPCC_OGAM_RAMB_EXP_REGION0_LUT_OFFSET 0 8 MPCC_OGAM_RAMB_EXP_REGION0_NUM_SEGMENTS 12 14 MPCC_OGAM_RAMB_EXP_REGION1_LUT_OFFSET 16 24 MPCC_OGAM_RAMB_EXP_REGION1_NUM_SEGMENTS 28 30 regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_2_3 0 0x2ba 4 0 3 MPCC_OGAM_RAMB_EXP_REGION2_LUT_OFFSET 0 8 MPCC_OGAM_RAMB_EXP_REGION2_NUM_SEGMENTS 12 14 MPCC_OGAM_RAMB_EXP_REGION3_LUT_OFFSET 16 24 MPCC_OGAM_RAMB_EXP_REGION3_NUM_SEGMENTS 28 30 regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_4_5 0 0x2bb 4 0 3 MPCC_OGAM_RAMB_EXP_REGION4_LUT_OFFSET 0 8 MPCC_OGAM_RAMB_EXP_REGION4_NUM_SEGMENTS 12 14 MPCC_OGAM_RAMB_EXP_REGION5_LUT_OFFSET 16 24 MPCC_OGAM_RAMB_EXP_REGION5_NUM_SEGMENTS 28 30 regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_6_7 0 0x2bc 4 0 3 MPCC_OGAM_RAMB_EXP_REGION6_LUT_OFFSET 0 8 MPCC_OGAM_RAMB_EXP_REGION6_NUM_SEGMENTS 12 14 MPCC_OGAM_RAMB_EXP_REGION7_LUT_OFFSET 16 24 MPCC_OGAM_RAMB_EXP_REGION7_NUM_SEGMENTS 28 30 regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_8_9 0 0x2bd 4 0 3 MPCC_OGAM_RAMB_EXP_REGION8_LUT_OFFSET 0 8 MPCC_OGAM_RAMB_EXP_REGION8_NUM_SEGMENTS 12 14 MPCC_OGAM_RAMB_EXP_REGION9_LUT_OFFSET 16 24 MPCC_OGAM_RAMB_EXP_REGION9_NUM_SEGMENTS 28 30 regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_10_11 0 0x2be 4 0 3 MPCC_OGAM_RAMB_EXP_REGION10_LUT_OFFSET 0 8 MPCC_OGAM_RAMB_EXP_REGION10_NUM_SEGMENTS 12 14 MPCC_OGAM_RAMB_EXP_REGION11_LUT_OFFSET 16 24 MPCC_OGAM_RAMB_EXP_REGION11_NUM_SEGMENTS 28 30 regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_12_13 0 0x2bf 4 0 3 MPCC_OGAM_RAMB_EXP_REGION12_LUT_OFFSET 0 8 MPCC_OGAM_RAMB_EXP_REGION12_NUM_SEGMENTS 12 14 MPCC_OGAM_RAMB_EXP_REGION13_LUT_OFFSET 16 24 MPCC_OGAM_RAMB_EXP_REGION13_NUM_SEGMENTS 28 30 regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_14_15 0 0x2c0 4 0 3 MPCC_OGAM_RAMB_EXP_REGION14_LUT_OFFSET 0 8 MPCC_OGAM_RAMB_EXP_REGION14_NUM_SEGMENTS 12 14 MPCC_OGAM_RAMB_EXP_REGION15_LUT_OFFSET 16 24 MPCC_OGAM_RAMB_EXP_REGION15_NUM_SEGMENTS 28 30 regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_16_17 0 0x2c1 4 0 3 MPCC_OGAM_RAMB_EXP_REGION16_LUT_OFFSET 0 8 MPCC_OGAM_RAMB_EXP_REGION16_NUM_SEGMENTS 12 14 MPCC_OGAM_RAMB_EXP_REGION17_LUT_OFFSET 16 24 MPCC_OGAM_RAMB_EXP_REGION17_NUM_SEGMENTS 28 30 regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_18_19 0 0x2c2 4 0 3 MPCC_OGAM_RAMB_EXP_REGION18_LUT_OFFSET 0 8 MPCC_OGAM_RAMB_EXP_REGION18_NUM_SEGMENTS 12 14 MPCC_OGAM_RAMB_EXP_REGION19_LUT_OFFSET 16 24 MPCC_OGAM_RAMB_EXP_REGION19_NUM_SEGMENTS 28 30 regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_20_21 0 0x2c3 4 0 3 MPCC_OGAM_RAMB_EXP_REGION20_LUT_OFFSET 0 8 MPCC_OGAM_RAMB_EXP_REGION20_NUM_SEGMENTS 12 14 MPCC_OGAM_RAMB_EXP_REGION21_LUT_OFFSET 16 24 MPCC_OGAM_RAMB_EXP_REGION21_NUM_SEGMENTS 28 30 regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_22_23 0 0x2c4 4 0 3 MPCC_OGAM_RAMB_EXP_REGION22_LUT_OFFSET 0 8 MPCC_OGAM_RAMB_EXP_REGION22_NUM_SEGMENTS 12 14 MPCC_OGAM_RAMB_EXP_REGION23_LUT_OFFSET 16 24 MPCC_OGAM_RAMB_EXP_REGION23_NUM_SEGMENTS 28 30 regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_24_25 0 0x2c5 4 0 3 MPCC_OGAM_RAMB_EXP_REGION24_LUT_OFFSET 0 8 MPCC_OGAM_RAMB_EXP_REGION24_NUM_SEGMENTS 12 14 MPCC_OGAM_RAMB_EXP_REGION25_LUT_OFFSET 16 24 MPCC_OGAM_RAMB_EXP_REGION25_NUM_SEGMENTS 28 30 regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_26_27 0 0x2c6 4 0 3 MPCC_OGAM_RAMB_EXP_REGION26_LUT_OFFSET 0 8 MPCC_OGAM_RAMB_EXP_REGION26_NUM_SEGMENTS 12 14 MPCC_OGAM_RAMB_EXP_REGION27_LUT_OFFSET 16 24 MPCC_OGAM_RAMB_EXP_REGION27_NUM_SEGMENTS 28 30 regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_28_29 0 0x2c7 4 0 3 MPCC_OGAM_RAMB_EXP_REGION28_LUT_OFFSET 0 8 MPCC_OGAM_RAMB_EXP_REGION28_NUM_SEGMENTS 12 14 MPCC_OGAM_RAMB_EXP_REGION29_LUT_OFFSET 16 24 MPCC_OGAM_RAMB_EXP_REGION29_NUM_SEGMENTS 28 30 regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_30_31 0 0x2c8 4 0 3 MPCC_OGAM_RAMB_EXP_REGION30_LUT_OFFSET 0 8 MPCC_OGAM_RAMB_EXP_REGION30_NUM_SEGMENTS 12 14 MPCC_OGAM_RAMB_EXP_REGION31_LUT_OFFSET 16 24 MPCC_OGAM_RAMB_EXP_REGION31_NUM_SEGMENTS 28 30 regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_32_33 0 0x2c9 4 0 3 MPCC_OGAM_RAMB_EXP_REGION32_LUT_OFFSET 0 8 MPCC_OGAM_RAMB_EXP_REGION32_NUM_SEGMENTS 12 14 MPCC_OGAM_RAMB_EXP_REGION33_LUT_OFFSET 16 24 MPCC_OGAM_RAMB_EXP_REGION33_NUM_SEGMENTS 28 30 regMPCC_OGAM3_MPCC_GAMUT_REMAP_COEF_FORMAT 0 0x2ca 1 0 3 MPCC_GAMUT_REMAP_COEF_FORMAT 0 0 regMPCC_OGAM3_MPCC_GAMUT_REMAP_MODE 0 0x2cb 2 0 3 MPCC_GAMUT_REMAP_MODE 0 1 MPCC_GAMUT_REMAP_MODE_CURRENT 7 8 regMPCC_OGAM3_MPC_GAMUT_REMAP_C11_C12_A 0 0x2cc 2 0 3 MPCC_GAMUT_REMAP_C11_A 0 15 MPCC_GAMUT_REMAP_C12_A 16 31 regMPCC_OGAM3_MPC_GAMUT_REMAP_C13_C14_A 0 0x2cd 2 0 3 MPCC_GAMUT_REMAP_C13_A 0 15 MPCC_GAMUT_REMAP_C14_A 16 31 regMPCC_OGAM3_MPC_GAMUT_REMAP_C21_C22_A 0 0x2ce 2 0 3 MPCC_GAMUT_REMAP_C21_A 0 15 MPCC_GAMUT_REMAP_C22_A 16 31 regMPCC_OGAM3_MPC_GAMUT_REMAP_C23_C24_A 0 0x2cf 2 0 3 MPCC_GAMUT_REMAP_C23_A 0 15 MPCC_GAMUT_REMAP_C24_A 16 31 regMPCC_OGAM3_MPC_GAMUT_REMAP_C31_C32_A 0 0x2d0 2 0 3 MPCC_GAMUT_REMAP_C31_A 0 15 MPCC_GAMUT_REMAP_C32_A 16 31 regMPCC_OGAM3_MPC_GAMUT_REMAP_C33_C34_A 0 0x2d1 2 0 3 MPCC_GAMUT_REMAP_C33_A 0 15 MPCC_GAMUT_REMAP_C34_A 16 31 regMPCC_OGAM3_MPC_GAMUT_REMAP_C11_C12_B 0 0x2d2 2 0 3 MPCC_GAMUT_REMAP_C11_B 0 15 MPCC_GAMUT_REMAP_C12_B 16 31 regMPCC_OGAM3_MPC_GAMUT_REMAP_C13_C14_B 0 0x2d3 2 0 3 MPCC_GAMUT_REMAP_C13_B 0 15 MPCC_GAMUT_REMAP_C14_B 16 31 regMPCC_OGAM3_MPC_GAMUT_REMAP_C21_C22_B 0 0x2d4 2 0 3 MPCC_GAMUT_REMAP_C21_B 0 15 MPCC_GAMUT_REMAP_C22_B 16 31 regMPCC_OGAM3_MPC_GAMUT_REMAP_C23_C24_B 0 0x2d5 2 0 3 MPCC_GAMUT_REMAP_C23_B 0 15 MPCC_GAMUT_REMAP_C24_B 16 31 regMPCC_OGAM3_MPC_GAMUT_REMAP_C31_C32_B 0 0x2d6 2 0 3 MPCC_GAMUT_REMAP_C31_B 0 15 MPCC_GAMUT_REMAP_C32_B 16 31 regMPCC_OGAM3_MPC_GAMUT_REMAP_C33_C34_B 0 0x2d7 2 0 3 MPCC_GAMUT_REMAP_C33_B 0 15 MPCC_GAMUT_REMAP_C34_B 16 31 regMPC_OUT0_MUX 0 0x580 7 0 3 MPC_OUT_MUX 0 3 MPC_OUT_RATE_CONTROL_OVFL_ERROR 5 5 MPC_OUT_RATE_CONTROL_ERROR_ACK 7 7 MPC_OUT_RATE_CONTROL_DISABLE 8 8 MPC_OUT_RATE_CONTROL 9 9 MPC_OUT_FLOW_CONTROL_MODE 10 10 MPC_OUT_FLOW_CONTROL_COUNT 11 22 regMPC_OUT0_DENORM_CONTROL 0 0x581 3 0 3 MPC_OUT_DENORM_CLAMP_MIN_R_CR 0 11 MPC_OUT_DENORM_CLAMP_MAX_R_CR 12 23 MPC_OUT_DENORM_MODE 24 26 regMPC_OUT0_DENORM_CLAMP_G_Y 0 0x582 2 0 3 MPC_OUT_DENORM_CLAMP_MIN_G_Y 0 11 MPC_OUT_DENORM_CLAMP_MAX_G_Y 12 23 regMPC_OUT0_DENORM_CLAMP_B_CB 0 0x583 2 0 3 MPC_OUT_DENORM_CLAMP_MIN_B_CB 0 11 MPC_OUT_DENORM_CLAMP_MAX_B_CB 12 23 regMPC_OUT1_MUX 0 0x584 7 0 3 MPC_OUT_MUX 0 3 MPC_OUT_RATE_CONTROL_OVFL_ERROR 5 5 MPC_OUT_RATE_CONTROL_ERROR_ACK 7 7 MPC_OUT_RATE_CONTROL_DISABLE 8 8 MPC_OUT_RATE_CONTROL 9 9 MPC_OUT_FLOW_CONTROL_MODE 10 10 MPC_OUT_FLOW_CONTROL_COUNT 11 22 regMPC_OUT1_DENORM_CONTROL 0 0x585 3 0 3 MPC_OUT_DENORM_CLAMP_MIN_R_CR 0 11 MPC_OUT_DENORM_CLAMP_MAX_R_CR 12 23 MPC_OUT_DENORM_MODE 24 26 regMPC_OUT1_DENORM_CLAMP_G_Y 0 0x586 2 0 3 MPC_OUT_DENORM_CLAMP_MIN_G_Y 0 11 MPC_OUT_DENORM_CLAMP_MAX_G_Y 12 23 regMPC_OUT1_DENORM_CLAMP_B_CB 0 0x587 2 0 3 MPC_OUT_DENORM_CLAMP_MIN_B_CB 0 11 MPC_OUT_DENORM_CLAMP_MAX_B_CB 12 23 regMPC_OUT2_MUX 0 0x588 7 0 3 MPC_OUT_MUX 0 3 MPC_OUT_RATE_CONTROL_OVFL_ERROR 5 5 MPC_OUT_RATE_CONTROL_ERROR_ACK 7 7 MPC_OUT_RATE_CONTROL_DISABLE 8 8 MPC_OUT_RATE_CONTROL 9 9 MPC_OUT_FLOW_CONTROL_MODE 10 10 MPC_OUT_FLOW_CONTROL_COUNT 11 22 regMPC_OUT2_DENORM_CONTROL 0 0x589 3 0 3 MPC_OUT_DENORM_CLAMP_MIN_R_CR 0 11 MPC_OUT_DENORM_CLAMP_MAX_R_CR 12 23 MPC_OUT_DENORM_MODE 24 26 regMPC_OUT2_DENORM_CLAMP_G_Y 0 0x58a 2 0 3 MPC_OUT_DENORM_CLAMP_MIN_G_Y 0 11 MPC_OUT_DENORM_CLAMP_MAX_G_Y 12 23 regMPC_OUT2_DENORM_CLAMP_B_CB 0 0x58b 2 0 3 MPC_OUT_DENORM_CLAMP_MIN_B_CB 0 11 MPC_OUT_DENORM_CLAMP_MAX_B_CB 12 23 regMPC_OUT3_MUX 0 0x58c 7 0 3 MPC_OUT_MUX 0 3 MPC_OUT_RATE_CONTROL_OVFL_ERROR 5 5 MPC_OUT_RATE_CONTROL_ERROR_ACK 7 7 MPC_OUT_RATE_CONTROL_DISABLE 8 8 MPC_OUT_RATE_CONTROL 9 9 MPC_OUT_FLOW_CONTROL_MODE 10 10 MPC_OUT_FLOW_CONTROL_COUNT 11 22 regMPC_OUT3_DENORM_CONTROL 0 0x58d 3 0 3 MPC_OUT_DENORM_CLAMP_MIN_R_CR 0 11 MPC_OUT_DENORM_CLAMP_MAX_R_CR 12 23 MPC_OUT_DENORM_MODE 24 26 regMPC_OUT3_DENORM_CLAMP_G_Y 0 0x58e 2 0 3 MPC_OUT_DENORM_CLAMP_MIN_G_Y 0 11 MPC_OUT_DENORM_CLAMP_MAX_G_Y 12 23 regMPC_OUT3_DENORM_CLAMP_B_CB 0 0x58f 2 0 3 MPC_OUT_DENORM_CLAMP_MIN_B_CB 0 11 MPC_OUT_DENORM_CLAMP_MAX_B_CB 12 23 regMPC_OUT_CSC_COEF_FORMAT 0 0x5a0 4 0 3 MPC_OCSC0_COEF_FORMAT 0 0 MPC_OCSC1_COEF_FORMAT 1 1 MPC_OCSC2_COEF_FORMAT 2 2 MPC_OCSC3_COEF_FORMAT 3 3 regMPC_OUT0_CSC_MODE 0 0x5a1 2 0 3 MPC_OCSC_MODE 0 1 MPC_OCSC_MODE_CURRENT 7 8 regMPC_OUT0_CSC_C11_C12_A 0 0x5a2 2 0 3 MPC_OCSC_C11_A 0 15 MPC_OCSC_C12_A 16 31 regMPC_OUT0_CSC_C13_C14_A 0 0x5a3 2 0 3 MPC_OCSC_C13_A 0 15 MPC_OCSC_C14_A 16 31 regMPC_OUT0_CSC_C21_C22_A 0 0x5a4 2 0 3 MPC_OCSC_C21_A 0 15 MPC_OCSC_C22_A 16 31 regMPC_OUT0_CSC_C23_C24_A 0 0x5a5 2 0 3 MPC_OCSC_C23_A 0 15 MPC_OCSC_C24_A 16 31 regMPC_OUT0_CSC_C31_C32_A 0 0x5a6 2 0 3 MPC_OCSC_C31_A 0 15 MPC_OCSC_C32_A 16 31 regMPC_OUT0_CSC_C33_C34_A 0 0x5a7 2 0 3 MPC_OCSC_C33_A 0 15 MPC_OCSC_C34_A 16 31 regMPC_OUT0_CSC_C11_C12_B 0 0x5a8 2 0 3 MPC_OCSC_C11_B 0 15 MPC_OCSC_C12_B 16 31 regMPC_OUT0_CSC_C13_C14_B 0 0x5a9 2 0 3 MPC_OCSC_C13_B 0 15 MPC_OCSC_C14_B 16 31 regMPC_OUT0_CSC_C21_C22_B 0 0x5aa 2 0 3 MPC_OCSC_C21_B 0 15 MPC_OCSC_C22_B 16 31 regMPC_OUT0_CSC_C23_C24_B 0 0x5ab 2 0 3 MPC_OCSC_C23_B 0 15 MPC_OCSC_C24_B 16 31 regMPC_OUT0_CSC_C31_C32_B 0 0x5ac 2 0 3 MPC_OCSC_C31_B 0 15 MPC_OCSC_C32_B 16 31 regMPC_OUT0_CSC_C33_C34_B 0 0x5ad 2 0 3 MPC_OCSC_C33_B 0 15 MPC_OCSC_C34_B 16 31 regMPC_OUT1_CSC_MODE 0 0x5ae 2 0 3 MPC_OCSC_MODE 0 1 MPC_OCSC_MODE_CURRENT 7 8 regMPC_OUT1_CSC_C11_C12_A 0 0x5af 2 0 3 MPC_OCSC_C11_A 0 15 MPC_OCSC_C12_A 16 31 regMPC_OUT1_CSC_C13_C14_A 0 0x5b0 2 0 3 MPC_OCSC_C13_A 0 15 MPC_OCSC_C14_A 16 31 regMPC_OUT1_CSC_C21_C22_A 0 0x5b1 2 0 3 MPC_OCSC_C21_A 0 15 MPC_OCSC_C22_A 16 31 regMPC_OUT1_CSC_C23_C24_A 0 0x5b2 2 0 3 MPC_OCSC_C23_A 0 15 MPC_OCSC_C24_A 16 31 regMPC_OUT1_CSC_C31_C32_A 0 0x5b3 2 0 3 MPC_OCSC_C31_A 0 15 MPC_OCSC_C32_A 16 31 regMPC_OUT1_CSC_C33_C34_A 0 0x5b4 2 0 3 MPC_OCSC_C33_A 0 15 MPC_OCSC_C34_A 16 31 regMPC_OUT1_CSC_C11_C12_B 0 0x5b5 2 0 3 MPC_OCSC_C11_B 0 15 MPC_OCSC_C12_B 16 31 regMPC_OUT1_CSC_C13_C14_B 0 0x5b6 2 0 3 MPC_OCSC_C13_B 0 15 MPC_OCSC_C14_B 16 31 regMPC_OUT1_CSC_C21_C22_B 0 0x5b7 2 0 3 MPC_OCSC_C21_B 0 15 MPC_OCSC_C22_B 16 31 regMPC_OUT1_CSC_C23_C24_B 0 0x5b8 2 0 3 MPC_OCSC_C23_B 0 15 MPC_OCSC_C24_B 16 31 regMPC_OUT1_CSC_C31_C32_B 0 0x5b9 2 0 3 MPC_OCSC_C31_B 0 15 MPC_OCSC_C32_B 16 31 regMPC_OUT1_CSC_C33_C34_B 0 0x5ba 2 0 3 MPC_OCSC_C33_B 0 15 MPC_OCSC_C34_B 16 31 regMPC_OUT2_CSC_MODE 0 0x5bb 2 0 3 MPC_OCSC_MODE 0 1 MPC_OCSC_MODE_CURRENT 7 8 regMPC_OUT2_CSC_C11_C12_A 0 0x5bc 2 0 3 MPC_OCSC_C11_A 0 15 MPC_OCSC_C12_A 16 31 regMPC_OUT2_CSC_C13_C14_A 0 0x5bd 2 0 3 MPC_OCSC_C13_A 0 15 MPC_OCSC_C14_A 16 31 regMPC_OUT2_CSC_C21_C22_A 0 0x5be 2 0 3 MPC_OCSC_C21_A 0 15 MPC_OCSC_C22_A 16 31 regMPC_OUT2_CSC_C23_C24_A 0 0x5bf 2 0 3 MPC_OCSC_C23_A 0 15 MPC_OCSC_C24_A 16 31 regMPC_OUT2_CSC_C31_C32_A 0 0x5c0 2 0 3 MPC_OCSC_C31_A 0 15 MPC_OCSC_C32_A 16 31 regMPC_OUT2_CSC_C33_C34_A 0 0x5c1 2 0 3 MPC_OCSC_C33_A 0 15 MPC_OCSC_C34_A 16 31 regMPC_OUT2_CSC_C11_C12_B 0 0x5c2 2 0 3 MPC_OCSC_C11_B 0 15 MPC_OCSC_C12_B 16 31 regMPC_OUT2_CSC_C13_C14_B 0 0x5c3 2 0 3 MPC_OCSC_C13_B 0 15 MPC_OCSC_C14_B 16 31 regMPC_OUT2_CSC_C21_C22_B 0 0x5c4 2 0 3 MPC_OCSC_C21_B 0 15 MPC_OCSC_C22_B 16 31 regMPC_OUT2_CSC_C23_C24_B 0 0x5c5 2 0 3 MPC_OCSC_C23_B 0 15 MPC_OCSC_C24_B 16 31 regMPC_OUT2_CSC_C31_C32_B 0 0x5c6 2 0 3 MPC_OCSC_C31_B 0 15 MPC_OCSC_C32_B 16 31 regMPC_OUT2_CSC_C33_C34_B 0 0x5c7 2 0 3 MPC_OCSC_C33_B 0 15 MPC_OCSC_C34_B 16 31 regMPC_OUT3_CSC_MODE 0 0x5c8 2 0 3 MPC_OCSC_MODE 0 1 MPC_OCSC_MODE_CURRENT 7 8 regMPC_OUT3_CSC_C11_C12_A 0 0x5c9 2 0 3 MPC_OCSC_C11_A 0 15 MPC_OCSC_C12_A 16 31 regMPC_OUT3_CSC_C13_C14_A 0 0x5ca 2 0 3 MPC_OCSC_C13_A 0 15 MPC_OCSC_C14_A 16 31 regMPC_OUT3_CSC_C21_C22_A 0 0x5cb 2 0 3 MPC_OCSC_C21_A 0 15 MPC_OCSC_C22_A 16 31 regMPC_OUT3_CSC_C23_C24_A 0 0x5cc 2 0 3 MPC_OCSC_C23_A 0 15 MPC_OCSC_C24_A 16 31 regMPC_OUT3_CSC_C31_C32_A 0 0x5cd 2 0 3 MPC_OCSC_C31_A 0 15 MPC_OCSC_C32_A 16 31 regMPC_OUT3_CSC_C33_C34_A 0 0x5ce 2 0 3 MPC_OCSC_C33_A 0 15 MPC_OCSC_C34_A 16 31 regMPC_OUT3_CSC_C11_C12_B 0 0x5cf 2 0 3 MPC_OCSC_C11_B 0 15 MPC_OCSC_C12_B 16 31 regMPC_OUT3_CSC_C13_C14_B 0 0x5d0 2 0 3 MPC_OCSC_C13_B 0 15 MPC_OCSC_C14_B 16 31 regMPC_OUT3_CSC_C21_C22_B 0 0x5d1 2 0 3 MPC_OCSC_C21_B 0 15 MPC_OCSC_C22_B 16 31 regMPC_OUT3_CSC_C23_C24_B 0 0x5d2 2 0 3 MPC_OCSC_C23_B 0 15 MPC_OCSC_C24_B 16 31 regMPC_OUT3_CSC_C31_C32_B 0 0x5d3 2 0 3 MPC_OCSC_C31_B 0 15 MPC_OCSC_C32_B 16 31 regMPC_OUT3_CSC_C33_C34_B 0 0x5d4 2 0 3 MPC_OCSC_C33_B 0 15 MPC_OCSC_C34_B 16 31 regMPC_OCSC_TEST_DEBUG_INDEX 0 0x605 2 0 3 MPC_OCSC_TEST_DEBUG_INDEX 0 7 MPC_OCSC_TEST_DEBUG_WRITE_EN 8 8 regMPC_OCSC_TEST_DEBUG_DATA 0 0x606 1 0 3 MPC_OCSC_TEST_DEBUG_DATA 0 31 regMPC_RMU_CONTROL 0 0x680 4 0 3 MPC_RMU0_MUX 0 3 MPC_RMU0_MUX_STATUS 4 7 MPC_RMU1_MUX 8 11 MPC_RMU1_MUX_STATUS 12 15 regMPC_RMU_MEM_PWR_CTRL 0 0x681 10 0 3 MPC_RMU0_MEM_PWR_FORCE 0 1 MPC_RMU0_MEM_PWR_DIS 2 2 MPC_RMU0_SHAPER_MEM_PWR_STATE 4 5 MPC_RMU0_3DLUT_MEM_PWR_STATE 6 7 MPC_RMU0_MEM_LOW_PWR_MODE 8 9 MPC_RMU1_MEM_PWR_FORCE 10 11 MPC_RMU1_MEM_PWR_DIS 12 12 MPC_RMU1_SHAPER_MEM_PWR_STATE 14 15 MPC_RMU1_3DLUT_MEM_PWR_STATE 16 17 MPC_RMU1_MEM_LOW_PWR_MODE 18 19 regMPC_RMU0_SHAPER_CONTROL 0 0x682 2 0 3 MPC_RMU_SHAPER_LUT_MODE 0 1 MPC_RMU_SHAPER_MODE_CURRENT 8 9 regMPC_RMU0_SHAPER_OFFSET_R 0 0x683 1 0 3 MPC_RMU_SHAPER_OFFSET_R 0 18 regMPC_RMU0_SHAPER_OFFSET_G 0 0x684 1 0 3 MPC_RMU_SHAPER_OFFSET_G 0 18 regMPC_RMU0_SHAPER_OFFSET_B 0 0x685 1 0 3 MPC_RMU_SHAPER_OFFSET_B 0 18 regMPC_RMU0_SHAPER_SCALE_R 0 0x686 1 0 3 MPC_RMU_SHAPER_SCALE_R 0 15 regMPC_RMU0_SHAPER_SCALE_G_B 0 0x687 2 0 3 MPC_RMU_SHAPER_SCALE_G 0 15 MPC_RMU_SHAPER_SCALE_B 16 31 regMPC_RMU0_SHAPER_LUT_INDEX 0 0x688 1 0 3 MPC_RMU_SHAPER_LUT_INDEX 0 7 regMPC_RMU0_SHAPER_LUT_DATA 0 0x689 1 0 3 MPC_RMU_SHAPER_LUT_DATA 0 23 regMPC_RMU0_SHAPER_LUT_WRITE_EN_MASK 0 0x68a 2 0 3 MPC_RMU_SHAPER_LUT_WRITE_EN_MASK 0 2 MPC_RMU_SHAPER_LUT_WRITE_SEL 4 4 regMPC_RMU0_SHAPER_RAMA_START_CNTL_B 0 0x68b 2 0 3 MPC_RMU_SHAPER_RAMA_EXP_REGION_START_B 0 17 MPC_RMU_SHAPER_RAMA_EXP_REGION_START_SEGMENT_B 20 26 regMPC_RMU0_SHAPER_RAMA_START_CNTL_G 0 0x68c 2 0 3 MPC_RMU_SHAPER_RAMA_EXP_REGION_START_G 0 17 MPC_RMU_SHAPER_RAMA_EXP_REGION_START_SEGMENT_G 20 26 regMPC_RMU0_SHAPER_RAMA_START_CNTL_R 0 0x68d 2 0 3 MPC_RMU_SHAPER_RAMA_EXP_REGION_START_R 0 17 MPC_RMU_SHAPER_RAMA_EXP_REGION_START_SEGMENT_R 20 26 regMPC_RMU0_SHAPER_RAMA_END_CNTL_B 0 0x68e 2 0 3 MPC_RMU_SHAPER_RAMA_EXP_REGION_END_B 0 15 MPC_RMU_SHAPER_RAMA_EXP_REGION_END_BASE_B 16 29 regMPC_RMU0_SHAPER_RAMA_END_CNTL_G 0 0x68f 2 0 3 MPC_RMU_SHAPER_RAMA_EXP_REGION_END_G 0 15 MPC_RMU_SHAPER_RAMA_EXP_REGION_END_BASE_G 16 29 regMPC_RMU0_SHAPER_RAMA_END_CNTL_R 0 0x690 2 0 3 MPC_RMU_SHAPER_RAMA_EXP_REGION_END_R 0 15 MPC_RMU_SHAPER_RAMA_EXP_REGION_END_BASE_R 16 29 regMPC_RMU0_SHAPER_RAMA_REGION_0_1 0 0x691 4 0 3 MPC_RMU_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET 0 8 MPC_RMU_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS 12 14 MPC_RMU_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET 16 24 MPC_RMU_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS 28 30 regMPC_RMU0_SHAPER_RAMA_REGION_2_3 0 0x692 4 0 3 MPC_RMU_SHAPER_RAMA_EXP_REGION2_LUT_OFFSET 0 8 MPC_RMU_SHAPER_RAMA_EXP_REGION2_NUM_SEGMENTS 12 14 MPC_RMU_SHAPER_RAMA_EXP_REGION3_LUT_OFFSET 16 24 MPC_RMU_SHAPER_RAMA_EXP_REGION3_NUM_SEGMENTS 28 30 regMPC_RMU0_SHAPER_RAMA_REGION_4_5 0 0x693 4 0 3 MPC_RMU_SHAPER_RAMA_EXP_REGION4_LUT_OFFSET 0 8 MPC_RMU_SHAPER_RAMA_EXP_REGION4_NUM_SEGMENTS 12 14 MPC_RMU_SHAPER_RAMA_EXP_REGION5_LUT_OFFSET 16 24 MPC_RMU_SHAPER_RAMA_EXP_REGION5_NUM_SEGMENTS 28 30 regMPC_RMU0_SHAPER_RAMA_REGION_6_7 0 0x694 4 0 3 MPC_RMU_SHAPER_RAMA_EXP_REGION6_LUT_OFFSET 0 8 MPC_RMU_SHAPER_RAMA_EXP_REGION6_NUM_SEGMENTS 12 14 MPC_RMU_SHAPER_RAMA_EXP_REGION7_LUT_OFFSET 16 24 MPC_RMU_SHAPER_RAMA_EXP_REGION7_NUM_SEGMENTS 28 30 regMPC_RMU0_SHAPER_RAMA_REGION_8_9 0 0x695 4 0 3 MPC_RMU_SHAPER_RAMA_EXP_REGION8_LUT_OFFSET 0 8 MPC_RMU_SHAPER_RAMA_EXP_REGION8_NUM_SEGMENTS 12 14 MPC_RMU_SHAPER_RAMA_EXP_REGION9_LUT_OFFSET 16 24 MPC_RMU_SHAPER_RAMA_EXP_REGION9_NUM_SEGMENTS 28 30 regMPC_RMU0_SHAPER_RAMA_REGION_10_11 0 0x696 4 0 3 MPC_RMU_SHAPER_RAMA_EXP_REGION10_LUT_OFFSET 0 8 MPC_RMU_SHAPER_RAMA_EXP_REGION10_NUM_SEGMENTS 12 14 MPC_RMU_SHAPER_RAMA_EXP_REGION11_LUT_OFFSET 16 24 MPC_RMU_SHAPER_RAMA_EXP_REGION11_NUM_SEGMENTS 28 30 regMPC_RMU0_SHAPER_RAMA_REGION_12_13 0 0x697 4 0 3 MPC_RMU_SHAPER_RAMA_EXP_REGION12_LUT_OFFSET 0 8 MPC_RMU_SHAPER_RAMA_EXP_REGION12_NUM_SEGMENTS 12 14 MPC_RMU_SHAPER_RAMA_EXP_REGION13_LUT_OFFSET 16 24 MPC_RMU_SHAPER_RAMA_EXP_REGION13_NUM_SEGMENTS 28 30 regMPC_RMU0_SHAPER_RAMA_REGION_14_15 0 0x698 4 0 3 MPC_RMU_SHAPER_RAMA_EXP_REGION14_LUT_OFFSET 0 8 MPC_RMU_SHAPER_RAMA_EXP_REGION14_NUM_SEGMENTS 12 14 MPC_RMU_SHAPER_RAMA_EXP_REGION15_LUT_OFFSET 16 24 MPC_RMU_SHAPER_RAMA_EXP_REGION15_NUM_SEGMENTS 28 30 regMPC_RMU0_SHAPER_RAMA_REGION_16_17 0 0x699 4 0 3 MPC_RMU_SHAPER_RAMA_EXP_REGION16_LUT_OFFSET 0 8 MPC_RMU_SHAPER_RAMA_EXP_REGION16_NUM_SEGMENTS 12 14 MPC_RMU_SHAPER_RAMA_EXP_REGION17_LUT_OFFSET 16 24 MPC_RMU_SHAPER_RAMA_EXP_REGION17_NUM_SEGMENTS 28 30 regMPC_RMU0_SHAPER_RAMA_REGION_18_19 0 0x69a 4 0 3 MPC_RMU_SHAPER_RAMA_EXP_REGION18_LUT_OFFSET 0 8 MPC_RMU_SHAPER_RAMA_EXP_REGION18_NUM_SEGMENTS 12 14 MPC_RMU_SHAPER_RAMA_EXP_REGION19_LUT_OFFSET 16 24 MPC_RMU_SHAPER_RAMA_EXP_REGION19_NUM_SEGMENTS 28 30 regMPC_RMU0_SHAPER_RAMA_REGION_20_21 0 0x69b 4 0 3 MPC_RMU_SHAPER_RAMA_EXP_REGION20_LUT_OFFSET 0 8 MPC_RMU_SHAPER_RAMA_EXP_REGION20_NUM_SEGMENTS 12 14 MPC_RMU_SHAPER_RAMA_EXP_REGION21_LUT_OFFSET 16 24 MPC_RMU_SHAPER_RAMA_EXP_REGION21_NUM_SEGMENTS 28 30 regMPC_RMU0_SHAPER_RAMA_REGION_22_23 0 0x69c 4 0 3 MPC_RMU_SHAPER_RAMA_EXP_REGION22_LUT_OFFSET 0 8 MPC_RMU_SHAPER_RAMA_EXP_REGION22_NUM_SEGMENTS 12 14 MPC_RMU_SHAPER_RAMA_EXP_REGION23_LUT_OFFSET 16 24 MPC_RMU_SHAPER_RAMA_EXP_REGION23_NUM_SEGMENTS 28 30 regMPC_RMU0_SHAPER_RAMA_REGION_24_25 0 0x69d 4 0 3 MPC_RMU_SHAPER_RAMA_EXP_REGION24_LUT_OFFSET 0 8 MPC_RMU_SHAPER_RAMA_EXP_REGION24_NUM_SEGMENTS 12 14 MPC_RMU_SHAPER_RAMA_EXP_REGION25_LUT_OFFSET 16 24 MPC_RMU_SHAPER_RAMA_EXP_REGION25_NUM_SEGMENTS 28 30 regMPC_RMU0_SHAPER_RAMA_REGION_26_27 0 0x69e 4 0 3 MPC_RMU_SHAPER_RAMA_EXP_REGION26_LUT_OFFSET 0 8 MPC_RMU_SHAPER_RAMA_EXP_REGION26_NUM_SEGMENTS 12 14 MPC_RMU_SHAPER_RAMA_EXP_REGION27_LUT_OFFSET 16 24 MPC_RMU_SHAPER_RAMA_EXP_REGION27_NUM_SEGMENTS 28 30 regMPC_RMU0_SHAPER_RAMA_REGION_28_29 0 0x69f 4 0 3 MPC_RMU_SHAPER_RAMA_EXP_REGION28_LUT_OFFSET 0 8 MPC_RMU_SHAPER_RAMA_EXP_REGION28_NUM_SEGMENTS 12 14 MPC_RMU_SHAPER_RAMA_EXP_REGION29_LUT_OFFSET 16 24 MPC_RMU_SHAPER_RAMA_EXP_REGION29_NUM_SEGMENTS 28 30 regMPC_RMU0_SHAPER_RAMA_REGION_30_31 0 0x6a0 4 0 3 MPC_RMU_SHAPER_RAMA_EXP_REGION30_LUT_OFFSET 0 8 MPC_RMU_SHAPER_RAMA_EXP_REGION30_NUM_SEGMENTS 12 14 MPC_RMU_SHAPER_RAMA_EXP_REGION31_LUT_OFFSET 16 24 MPC_RMU_SHAPER_RAMA_EXP_REGION31_NUM_SEGMENTS 28 30 regMPC_RMU0_SHAPER_RAMA_REGION_32_33 0 0x6a1 4 0 3 MPC_RMU_SHAPER_RAMA_EXP_REGION32_LUT_OFFSET 0 8 MPC_RMU_SHAPER_RAMA_EXP_REGION32_NUM_SEGMENTS 12 14 MPC_RMU_SHAPER_RAMA_EXP_REGION33_LUT_OFFSET 16 24 MPC_RMU_SHAPER_RAMA_EXP_REGION33_NUM_SEGMENTS 28 30 regMPC_RMU0_SHAPER_RAMB_START_CNTL_B 0 0x6a2 2 0 3 MPC_RMU_SHAPER_RAMB_EXP_REGION_START_B 0 17 MPC_RMU_SHAPER_RAMB_EXP_REGION_START_SEGMENT_B 20 26 regMPC_RMU0_SHAPER_RAMB_START_CNTL_G 0 0x6a3 2 0 3 MPC_RMU_SHAPER_RAMB_EXP_REGION_START_G 0 17 MPC_RMU_SHAPER_RAMB_EXP_REGION_START_SEGMENT_G 20 26 regMPC_RMU0_SHAPER_RAMB_START_CNTL_R 0 0x6a4 2 0 3 MPC_RMU_SHAPER_RAMB_EXP_REGION_START_R 0 17 MPC_RMU_SHAPER_RAMB_EXP_REGION_START_SEGMENT_R 20 26 regMPC_RMU0_SHAPER_RAMB_END_CNTL_B 0 0x6a5 2 0 3 MPC_RMU_SHAPER_RAMB_EXP_REGION_END_B 0 15 MPC_RMU_SHAPER_RAMB_EXP_REGION_END_BASE_B 16 29 regMPC_RMU0_SHAPER_RAMB_END_CNTL_G 0 0x6a6 2 0 3 MPC_RMU_SHAPER_RAMB_EXP_REGION_END_G 0 15 MPC_RMU_SHAPER_RAMB_EXP_REGION_END_BASE_G 16 29 regMPC_RMU0_SHAPER_RAMB_END_CNTL_R 0 0x6a7 2 0 3 MPC_RMU_SHAPER_RAMB_EXP_REGION_END_R 0 15 MPC_RMU_SHAPER_RAMB_EXP_REGION_END_BASE_R 16 29 regMPC_RMU0_SHAPER_RAMB_REGION_0_1 0 0x6a8 4 0 3 MPC_RMU_SHAPER_RAMB_EXP_REGION0_LUT_OFFSET 0 8 MPC_RMU_SHAPER_RAMB_EXP_REGION0_NUM_SEGMENTS 12 14 MPC_RMU_SHAPER_RAMB_EXP_REGION1_LUT_OFFSET 16 24 MPC_RMU_SHAPER_RAMB_EXP_REGION1_NUM_SEGMENTS 28 30 regMPC_RMU0_SHAPER_RAMB_REGION_2_3 0 0x6a9 4 0 3 MPC_RMU_SHAPER_RAMB_EXP_REGION2_LUT_OFFSET 0 8 MPC_RMU_SHAPER_RAMB_EXP_REGION2_NUM_SEGMENTS 12 14 MPC_RMU_SHAPER_RAMB_EXP_REGION3_LUT_OFFSET 16 24 MPC_RMU_SHAPER_RAMB_EXP_REGION3_NUM_SEGMENTS 28 30 regMPC_RMU0_SHAPER_RAMB_REGION_4_5 0 0x6aa 4 0 3 MPC_RMU_SHAPER_RAMB_EXP_REGION4_LUT_OFFSET 0 8 MPC_RMU_SHAPER_RAMB_EXP_REGION4_NUM_SEGMENTS 12 14 MPC_RMU_SHAPER_RAMB_EXP_REGION5_LUT_OFFSET 16 24 MPC_RMU_SHAPER_RAMB_EXP_REGION5_NUM_SEGMENTS 28 30 regMPC_RMU0_SHAPER_RAMB_REGION_6_7 0 0x6ab 4 0 3 MPC_RMU_SHAPER_RAMB_EXP_REGION6_LUT_OFFSET 0 8 MPC_RMU_SHAPER_RAMB_EXP_REGION6_NUM_SEGMENTS 12 14 MPC_RMU_SHAPER_RAMB_EXP_REGION7_LUT_OFFSET 16 24 MPC_RMU_SHAPER_RAMB_EXP_REGION7_NUM_SEGMENTS 28 30 regMPC_RMU0_SHAPER_RAMB_REGION_8_9 0 0x6ac 4 0 3 MPC_RMU_SHAPER_RAMB_EXP_REGION8_LUT_OFFSET 0 8 MPC_RMU_SHAPER_RAMB_EXP_REGION8_NUM_SEGMENTS 12 14 MPC_RMU_SHAPER_RAMB_EXP_REGION9_LUT_OFFSET 16 24 MPC_RMU_SHAPER_RAMB_EXP_REGION9_NUM_SEGMENTS 28 30 regMPC_RMU0_SHAPER_RAMB_REGION_10_11 0 0x6ad 4 0 3 MPC_RMU_SHAPER_RAMB_EXP_REGION10_LUT_OFFSET 0 8 MPC_RMU_SHAPER_RAMB_EXP_REGION10_NUM_SEGMENTS 12 14 MPC_RMU_SHAPER_RAMB_EXP_REGION11_LUT_OFFSET 16 24 MPC_RMU_SHAPER_RAMB_EXP_REGION11_NUM_SEGMENTS 28 30 regMPC_RMU0_SHAPER_RAMB_REGION_12_13 0 0x6ae 4 0 3 MPC_RMU_SHAPER_RAMB_EXP_REGION12_LUT_OFFSET 0 8 MPC_RMU_SHAPER_RAMB_EXP_REGION12_NUM_SEGMENTS 12 14 MPC_RMU_SHAPER_RAMB_EXP_REGION13_LUT_OFFSET 16 24 MPC_RMU_SHAPER_RAMB_EXP_REGION13_NUM_SEGMENTS 28 30 regMPC_RMU0_SHAPER_RAMB_REGION_14_15 0 0x6af 4 0 3 MPC_RMU_SHAPER_RAMB_EXP_REGION14_LUT_OFFSET 0 8 MPC_RMU_SHAPER_RAMB_EXP_REGION14_NUM_SEGMENTS 12 14 MPC_RMU_SHAPER_RAMB_EXP_REGION15_LUT_OFFSET 16 24 MPC_RMU_SHAPER_RAMB_EXP_REGION15_NUM_SEGMENTS 28 30 regMPC_RMU0_SHAPER_RAMB_REGION_16_17 0 0x6b0 4 0 3 MPC_RMU_SHAPER_RAMB_EXP_REGION16_LUT_OFFSET 0 8 MPC_RMU_SHAPER_RAMB_EXP_REGION16_NUM_SEGMENTS 12 14 MPC_RMU_SHAPER_RAMB_EXP_REGION17_LUT_OFFSET 16 24 MPC_RMU_SHAPER_RAMB_EXP_REGION17_NUM_SEGMENTS 28 30 regMPC_RMU0_SHAPER_RAMB_REGION_18_19 0 0x6b1 4 0 3 MPC_RMU_SHAPER_RAMB_EXP_REGION18_LUT_OFFSET 0 8 MPC_RMU_SHAPER_RAMB_EXP_REGION18_NUM_SEGMENTS 12 14 MPC_RMU_SHAPER_RAMB_EXP_REGION19_LUT_OFFSET 16 24 MPC_RMU_SHAPER_RAMB_EXP_REGION19_NUM_SEGMENTS 28 30 regMPC_RMU0_SHAPER_RAMB_REGION_20_21 0 0x6b2 4 0 3 MPC_RMU_SHAPER_RAMB_EXP_REGION20_LUT_OFFSET 0 8 MPC_RMU_SHAPER_RAMB_EXP_REGION20_NUM_SEGMENTS 12 14 MPC_RMU_SHAPER_RAMB_EXP_REGION21_LUT_OFFSET 16 24 MPC_RMU_SHAPER_RAMB_EXP_REGION21_NUM_SEGMENTS 28 30 regMPC_RMU0_SHAPER_RAMB_REGION_22_23 0 0x6b3 4 0 3 MPC_RMU_SHAPER_RAMB_EXP_REGION22_LUT_OFFSET 0 8 MPC_RMU_SHAPER_RAMB_EXP_REGION22_NUM_SEGMENTS 12 14 MPC_RMU_SHAPER_RAMB_EXP_REGION23_LUT_OFFSET 16 24 MPC_RMU_SHAPER_RAMB_EXP_REGION23_NUM_SEGMENTS 28 30 regMPC_RMU0_SHAPER_RAMB_REGION_24_25 0 0x6b4 4 0 3 MPC_RMU_SHAPER_RAMB_EXP_REGION24_LUT_OFFSET 0 8 MPC_RMU_SHAPER_RAMB_EXP_REGION24_NUM_SEGMENTS 12 14 MPC_RMU_SHAPER_RAMB_EXP_REGION25_LUT_OFFSET 16 24 MPC_RMU_SHAPER_RAMB_EXP_REGION25_NUM_SEGMENTS 28 30 regMPC_RMU0_SHAPER_RAMB_REGION_26_27 0 0x6b5 4 0 3 MPC_RMU_SHAPER_RAMB_EXP_REGION26_LUT_OFFSET 0 8 MPC_RMU_SHAPER_RAMB_EXP_REGION26_NUM_SEGMENTS 12 14 MPC_RMU_SHAPER_RAMB_EXP_REGION27_LUT_OFFSET 16 24 MPC_RMU_SHAPER_RAMB_EXP_REGION27_NUM_SEGMENTS 28 30 regMPC_RMU0_SHAPER_RAMB_REGION_28_29 0 0x6b6 4 0 3 MPC_RMU_SHAPER_RAMB_EXP_REGION28_LUT_OFFSET 0 8 MPC_RMU_SHAPER_RAMB_EXP_REGION28_NUM_SEGMENTS 12 14 MPC_RMU_SHAPER_RAMB_EXP_REGION29_LUT_OFFSET 16 24 MPC_RMU_SHAPER_RAMB_EXP_REGION29_NUM_SEGMENTS 28 30 regMPC_RMU0_SHAPER_RAMB_REGION_30_31 0 0x6b7 4 0 3 MPC_RMU_SHAPER_RAMB_EXP_REGION30_LUT_OFFSET 0 8 MPC_RMU_SHAPER_RAMB_EXP_REGION30_NUM_SEGMENTS 12 14 MPC_RMU_SHAPER_RAMB_EXP_REGION31_LUT_OFFSET 16 24 MPC_RMU_SHAPER_RAMB_EXP_REGION31_NUM_SEGMENTS 28 30 regMPC_RMU0_SHAPER_RAMB_REGION_32_33 0 0x6b8 4 0 3 MPC_RMU_SHAPER_RAMB_EXP_REGION32_LUT_OFFSET 0 8 MPC_RMU_SHAPER_RAMB_EXP_REGION32_NUM_SEGMENTS 12 14 MPC_RMU_SHAPER_RAMB_EXP_REGION33_LUT_OFFSET 16 24 MPC_RMU_SHAPER_RAMB_EXP_REGION33_NUM_SEGMENTS 28 30 regMPC_RMU0_3DLUT_MODE 0 0x6b9 3 0 3 MPC_RMU_3DLUT_MODE 0 1 MPC_RMU_3DLUT_SIZE 4 4 MPC_RMU_3DLUT_MODE_CURRENT 8 9 regMPC_RMU0_3DLUT_INDEX 0 0x6ba 1 0 3 MPC_RMU_3DLUT_INDEX 0 10 regMPC_RMU0_3DLUT_DATA 0 0x6bb 2 0 3 MPC_RMU_3DLUT_DATA0 0 15 MPC_RMU_3DLUT_DATA1 16 31 regMPC_RMU0_3DLUT_DATA_30BIT 0 0x6bc 1 0 3 MPC_RMU_3DLUT_DATA_30BIT 2 31 regMPC_RMU0_3DLUT_READ_WRITE_CONTROL 0 0x6bd 4 0 3 MPC_RMU_3DLUT_WRITE_EN_MASK 0 3 MPC_RMU_3DLUT_RAM_SEL 4 4 MPC_RMU_3DLUT_30BIT_EN 8 8 MPC_RMU_3DLUT_READ_SEL 16 17 regMPC_RMU0_3DLUT_OUT_NORM_FACTOR 0 0x6be 1 0 3 MPC_RMU_3DLUT_OUT_NORM_FACTOR 0 15 regMPC_RMU0_3DLUT_OUT_OFFSET_R 0 0x6bf 2 0 3 MPC_RMU_3DLUT_OUT_OFFSET_R 0 15 MPC_RMU_3DLUT_OUT_SCALE_R 16 31 regMPC_RMU0_3DLUT_OUT_OFFSET_G 0 0x6c0 2 0 3 MPC_RMU_3DLUT_OUT_OFFSET_G 0 15 MPC_RMU_3DLUT_OUT_SCALE_G 16 31 regMPC_RMU0_3DLUT_OUT_OFFSET_B 0 0x6c1 2 0 3 MPC_RMU_3DLUT_OUT_OFFSET_B 0 15 MPC_RMU_3DLUT_OUT_SCALE_B 16 31 regMPC_RMU1_SHAPER_CONTROL 0 0x6c2 2 0 3 MPC_RMU_SHAPER_LUT_MODE 0 1 MPC_RMU_SHAPER_MODE_CURRENT 8 9 regMPC_RMU1_SHAPER_OFFSET_R 0 0x6c3 1 0 3 MPC_RMU_SHAPER_OFFSET_R 0 18 regMPC_RMU1_SHAPER_OFFSET_G 0 0x6c4 1 0 3 MPC_RMU_SHAPER_OFFSET_G 0 18 regMPC_RMU1_SHAPER_OFFSET_B 0 0x6c5 1 0 3 MPC_RMU_SHAPER_OFFSET_B 0 18 regMPC_RMU1_SHAPER_SCALE_R 0 0x6c6 1 0 3 MPC_RMU_SHAPER_SCALE_R 0 15 regMPC_RMU1_SHAPER_SCALE_G_B 0 0x6c7 2 0 3 MPC_RMU_SHAPER_SCALE_G 0 15 MPC_RMU_SHAPER_SCALE_B 16 31 regMPC_RMU1_SHAPER_LUT_INDEX 0 0x6c8 1 0 3 MPC_RMU_SHAPER_LUT_INDEX 0 7 regMPC_RMU1_SHAPER_LUT_DATA 0 0x6c9 1 0 3 MPC_RMU_SHAPER_LUT_DATA 0 23 regMPC_RMU1_SHAPER_LUT_WRITE_EN_MASK 0 0x6ca 2 0 3 MPC_RMU_SHAPER_LUT_WRITE_EN_MASK 0 2 MPC_RMU_SHAPER_LUT_WRITE_SEL 4 4 regMPC_RMU1_SHAPER_RAMA_START_CNTL_B 0 0x6cb 2 0 3 MPC_RMU_SHAPER_RAMA_EXP_REGION_START_B 0 17 MPC_RMU_SHAPER_RAMA_EXP_REGION_START_SEGMENT_B 20 26 regMPC_RMU1_SHAPER_RAMA_START_CNTL_G 0 0x6cc 2 0 3 MPC_RMU_SHAPER_RAMA_EXP_REGION_START_G 0 17 MPC_RMU_SHAPER_RAMA_EXP_REGION_START_SEGMENT_G 20 26 regMPC_RMU1_SHAPER_RAMA_START_CNTL_R 0 0x6cd 2 0 3 MPC_RMU_SHAPER_RAMA_EXP_REGION_START_R 0 17 MPC_RMU_SHAPER_RAMA_EXP_REGION_START_SEGMENT_R 20 26 regMPC_RMU1_SHAPER_RAMA_END_CNTL_B 0 0x6ce 2 0 3 MPC_RMU_SHAPER_RAMA_EXP_REGION_END_B 0 15 MPC_RMU_SHAPER_RAMA_EXP_REGION_END_BASE_B 16 29 regMPC_RMU1_SHAPER_RAMA_END_CNTL_G 0 0x6cf 2 0 3 MPC_RMU_SHAPER_RAMA_EXP_REGION_END_G 0 15 MPC_RMU_SHAPER_RAMA_EXP_REGION_END_BASE_G 16 29 regMPC_RMU1_SHAPER_RAMA_END_CNTL_R 0 0x6d0 2 0 3 MPC_RMU_SHAPER_RAMA_EXP_REGION_END_R 0 15 MPC_RMU_SHAPER_RAMA_EXP_REGION_END_BASE_R 16 29 regMPC_RMU1_SHAPER_RAMA_REGION_0_1 0 0x6d1 4 0 3 MPC_RMU_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET 0 8 MPC_RMU_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS 12 14 MPC_RMU_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET 16 24 MPC_RMU_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS 28 30 regMPC_RMU1_SHAPER_RAMA_REGION_2_3 0 0x6d2 4 0 3 MPC_RMU_SHAPER_RAMA_EXP_REGION2_LUT_OFFSET 0 8 MPC_RMU_SHAPER_RAMA_EXP_REGION2_NUM_SEGMENTS 12 14 MPC_RMU_SHAPER_RAMA_EXP_REGION3_LUT_OFFSET 16 24 MPC_RMU_SHAPER_RAMA_EXP_REGION3_NUM_SEGMENTS 28 30 regMPC_RMU1_SHAPER_RAMA_REGION_4_5 0 0x6d3 4 0 3 MPC_RMU_SHAPER_RAMA_EXP_REGION4_LUT_OFFSET 0 8 MPC_RMU_SHAPER_RAMA_EXP_REGION4_NUM_SEGMENTS 12 14 MPC_RMU_SHAPER_RAMA_EXP_REGION5_LUT_OFFSET 16 24 MPC_RMU_SHAPER_RAMA_EXP_REGION5_NUM_SEGMENTS 28 30 regMPC_RMU1_SHAPER_RAMA_REGION_6_7 0 0x6d4 4 0 3 MPC_RMU_SHAPER_RAMA_EXP_REGION6_LUT_OFFSET 0 8 MPC_RMU_SHAPER_RAMA_EXP_REGION6_NUM_SEGMENTS 12 14 MPC_RMU_SHAPER_RAMA_EXP_REGION7_LUT_OFFSET 16 24 MPC_RMU_SHAPER_RAMA_EXP_REGION7_NUM_SEGMENTS 28 30 regMPC_RMU1_SHAPER_RAMA_REGION_8_9 0 0x6d5 4 0 3 MPC_RMU_SHAPER_RAMA_EXP_REGION8_LUT_OFFSET 0 8 MPC_RMU_SHAPER_RAMA_EXP_REGION8_NUM_SEGMENTS 12 14 MPC_RMU_SHAPER_RAMA_EXP_REGION9_LUT_OFFSET 16 24 MPC_RMU_SHAPER_RAMA_EXP_REGION9_NUM_SEGMENTS 28 30 regMPC_RMU1_SHAPER_RAMA_REGION_10_11 0 0x6d6 4 0 3 MPC_RMU_SHAPER_RAMA_EXP_REGION10_LUT_OFFSET 0 8 MPC_RMU_SHAPER_RAMA_EXP_REGION10_NUM_SEGMENTS 12 14 MPC_RMU_SHAPER_RAMA_EXP_REGION11_LUT_OFFSET 16 24 MPC_RMU_SHAPER_RAMA_EXP_REGION11_NUM_SEGMENTS 28 30 regMPC_RMU1_SHAPER_RAMA_REGION_12_13 0 0x6d7 4 0 3 MPC_RMU_SHAPER_RAMA_EXP_REGION12_LUT_OFFSET 0 8 MPC_RMU_SHAPER_RAMA_EXP_REGION12_NUM_SEGMENTS 12 14 MPC_RMU_SHAPER_RAMA_EXP_REGION13_LUT_OFFSET 16 24 MPC_RMU_SHAPER_RAMA_EXP_REGION13_NUM_SEGMENTS 28 30 regMPC_RMU1_SHAPER_RAMA_REGION_14_15 0 0x6d8 4 0 3 MPC_RMU_SHAPER_RAMA_EXP_REGION14_LUT_OFFSET 0 8 MPC_RMU_SHAPER_RAMA_EXP_REGION14_NUM_SEGMENTS 12 14 MPC_RMU_SHAPER_RAMA_EXP_REGION15_LUT_OFFSET 16 24 MPC_RMU_SHAPER_RAMA_EXP_REGION15_NUM_SEGMENTS 28 30 regMPC_RMU1_SHAPER_RAMA_REGION_16_17 0 0x6d9 4 0 3 MPC_RMU_SHAPER_RAMA_EXP_REGION16_LUT_OFFSET 0 8 MPC_RMU_SHAPER_RAMA_EXP_REGION16_NUM_SEGMENTS 12 14 MPC_RMU_SHAPER_RAMA_EXP_REGION17_LUT_OFFSET 16 24 MPC_RMU_SHAPER_RAMA_EXP_REGION17_NUM_SEGMENTS 28 30 regMPC_RMU1_SHAPER_RAMA_REGION_18_19 0 0x6da 4 0 3 MPC_RMU_SHAPER_RAMA_EXP_REGION18_LUT_OFFSET 0 8 MPC_RMU_SHAPER_RAMA_EXP_REGION18_NUM_SEGMENTS 12 14 MPC_RMU_SHAPER_RAMA_EXP_REGION19_LUT_OFFSET 16 24 MPC_RMU_SHAPER_RAMA_EXP_REGION19_NUM_SEGMENTS 28 30 regMPC_RMU1_SHAPER_RAMA_REGION_20_21 0 0x6db 4 0 3 MPC_RMU_SHAPER_RAMA_EXP_REGION20_LUT_OFFSET 0 8 MPC_RMU_SHAPER_RAMA_EXP_REGION20_NUM_SEGMENTS 12 14 MPC_RMU_SHAPER_RAMA_EXP_REGION21_LUT_OFFSET 16 24 MPC_RMU_SHAPER_RAMA_EXP_REGION21_NUM_SEGMENTS 28 30 regMPC_RMU1_SHAPER_RAMA_REGION_22_23 0 0x6dc 4 0 3 MPC_RMU_SHAPER_RAMA_EXP_REGION22_LUT_OFFSET 0 8 MPC_RMU_SHAPER_RAMA_EXP_REGION22_NUM_SEGMENTS 12 14 MPC_RMU_SHAPER_RAMA_EXP_REGION23_LUT_OFFSET 16 24 MPC_RMU_SHAPER_RAMA_EXP_REGION23_NUM_SEGMENTS 28 30 regMPC_RMU1_SHAPER_RAMA_REGION_24_25 0 0x6dd 4 0 3 MPC_RMU_SHAPER_RAMA_EXP_REGION24_LUT_OFFSET 0 8 MPC_RMU_SHAPER_RAMA_EXP_REGION24_NUM_SEGMENTS 12 14 MPC_RMU_SHAPER_RAMA_EXP_REGION25_LUT_OFFSET 16 24 MPC_RMU_SHAPER_RAMA_EXP_REGION25_NUM_SEGMENTS 28 30 regMPC_RMU1_SHAPER_RAMA_REGION_26_27 0 0x6de 4 0 3 MPC_RMU_SHAPER_RAMA_EXP_REGION26_LUT_OFFSET 0 8 MPC_RMU_SHAPER_RAMA_EXP_REGION26_NUM_SEGMENTS 12 14 MPC_RMU_SHAPER_RAMA_EXP_REGION27_LUT_OFFSET 16 24 MPC_RMU_SHAPER_RAMA_EXP_REGION27_NUM_SEGMENTS 28 30 regMPC_RMU1_SHAPER_RAMA_REGION_28_29 0 0x6df 4 0 3 MPC_RMU_SHAPER_RAMA_EXP_REGION28_LUT_OFFSET 0 8 MPC_RMU_SHAPER_RAMA_EXP_REGION28_NUM_SEGMENTS 12 14 MPC_RMU_SHAPER_RAMA_EXP_REGION29_LUT_OFFSET 16 24 MPC_RMU_SHAPER_RAMA_EXP_REGION29_NUM_SEGMENTS 28 30 regMPC_RMU1_SHAPER_RAMA_REGION_30_31 0 0x6e0 4 0 3 MPC_RMU_SHAPER_RAMA_EXP_REGION30_LUT_OFFSET 0 8 MPC_RMU_SHAPER_RAMA_EXP_REGION30_NUM_SEGMENTS 12 14 MPC_RMU_SHAPER_RAMA_EXP_REGION31_LUT_OFFSET 16 24 MPC_RMU_SHAPER_RAMA_EXP_REGION31_NUM_SEGMENTS 28 30 regMPC_RMU1_SHAPER_RAMA_REGION_32_33 0 0x6e1 4 0 3 MPC_RMU_SHAPER_RAMA_EXP_REGION32_LUT_OFFSET 0 8 MPC_RMU_SHAPER_RAMA_EXP_REGION32_NUM_SEGMENTS 12 14 MPC_RMU_SHAPER_RAMA_EXP_REGION33_LUT_OFFSET 16 24 MPC_RMU_SHAPER_RAMA_EXP_REGION33_NUM_SEGMENTS 28 30 regMPC_RMU1_SHAPER_RAMB_START_CNTL_B 0 0x6e2 2 0 3 MPC_RMU_SHAPER_RAMB_EXP_REGION_START_B 0 17 MPC_RMU_SHAPER_RAMB_EXP_REGION_START_SEGMENT_B 20 26 regMPC_RMU1_SHAPER_RAMB_START_CNTL_G 0 0x6e3 2 0 3 MPC_RMU_SHAPER_RAMB_EXP_REGION_START_G 0 17 MPC_RMU_SHAPER_RAMB_EXP_REGION_START_SEGMENT_G 20 26 regMPC_RMU1_SHAPER_RAMB_START_CNTL_R 0 0x6e4 2 0 3 MPC_RMU_SHAPER_RAMB_EXP_REGION_START_R 0 17 MPC_RMU_SHAPER_RAMB_EXP_REGION_START_SEGMENT_R 20 26 regMPC_RMU1_SHAPER_RAMB_END_CNTL_B 0 0x6e5 2 0 3 MPC_RMU_SHAPER_RAMB_EXP_REGION_END_B 0 15 MPC_RMU_SHAPER_RAMB_EXP_REGION_END_BASE_B 16 29 regMPC_RMU1_SHAPER_RAMB_END_CNTL_G 0 0x6e6 2 0 3 MPC_RMU_SHAPER_RAMB_EXP_REGION_END_G 0 15 MPC_RMU_SHAPER_RAMB_EXP_REGION_END_BASE_G 16 29 regMPC_RMU1_SHAPER_RAMB_END_CNTL_R 0 0x6e7 2 0 3 MPC_RMU_SHAPER_RAMB_EXP_REGION_END_R 0 15 MPC_RMU_SHAPER_RAMB_EXP_REGION_END_BASE_R 16 29 regMPC_RMU1_SHAPER_RAMB_REGION_0_1 0 0x6e8 4 0 3 MPC_RMU_SHAPER_RAMB_EXP_REGION0_LUT_OFFSET 0 8 MPC_RMU_SHAPER_RAMB_EXP_REGION0_NUM_SEGMENTS 12 14 MPC_RMU_SHAPER_RAMB_EXP_REGION1_LUT_OFFSET 16 24 MPC_RMU_SHAPER_RAMB_EXP_REGION1_NUM_SEGMENTS 28 30 regMPC_RMU1_SHAPER_RAMB_REGION_2_3 0 0x6e9 4 0 3 MPC_RMU_SHAPER_RAMB_EXP_REGION2_LUT_OFFSET 0 8 MPC_RMU_SHAPER_RAMB_EXP_REGION2_NUM_SEGMENTS 12 14 MPC_RMU_SHAPER_RAMB_EXP_REGION3_LUT_OFFSET 16 24 MPC_RMU_SHAPER_RAMB_EXP_REGION3_NUM_SEGMENTS 28 30 regMPC_RMU1_SHAPER_RAMB_REGION_4_5 0 0x6ea 4 0 3 MPC_RMU_SHAPER_RAMB_EXP_REGION4_LUT_OFFSET 0 8 MPC_RMU_SHAPER_RAMB_EXP_REGION4_NUM_SEGMENTS 12 14 MPC_RMU_SHAPER_RAMB_EXP_REGION5_LUT_OFFSET 16 24 MPC_RMU_SHAPER_RAMB_EXP_REGION5_NUM_SEGMENTS 28 30 regMPC_RMU1_SHAPER_RAMB_REGION_6_7 0 0x6eb 4 0 3 MPC_RMU_SHAPER_RAMB_EXP_REGION6_LUT_OFFSET 0 8 MPC_RMU_SHAPER_RAMB_EXP_REGION6_NUM_SEGMENTS 12 14 MPC_RMU_SHAPER_RAMB_EXP_REGION7_LUT_OFFSET 16 24 MPC_RMU_SHAPER_RAMB_EXP_REGION7_NUM_SEGMENTS 28 30 regMPC_RMU1_SHAPER_RAMB_REGION_8_9 0 0x6ec 4 0 3 MPC_RMU_SHAPER_RAMB_EXP_REGION8_LUT_OFFSET 0 8 MPC_RMU_SHAPER_RAMB_EXP_REGION8_NUM_SEGMENTS 12 14 MPC_RMU_SHAPER_RAMB_EXP_REGION9_LUT_OFFSET 16 24 MPC_RMU_SHAPER_RAMB_EXP_REGION9_NUM_SEGMENTS 28 30 regMPC_RMU1_SHAPER_RAMB_REGION_10_11 0 0x6ed 4 0 3 MPC_RMU_SHAPER_RAMB_EXP_REGION10_LUT_OFFSET 0 8 MPC_RMU_SHAPER_RAMB_EXP_REGION10_NUM_SEGMENTS 12 14 MPC_RMU_SHAPER_RAMB_EXP_REGION11_LUT_OFFSET 16 24 MPC_RMU_SHAPER_RAMB_EXP_REGION11_NUM_SEGMENTS 28 30 regMPC_RMU1_SHAPER_RAMB_REGION_12_13 0 0x6ee 4 0 3 MPC_RMU_SHAPER_RAMB_EXP_REGION12_LUT_OFFSET 0 8 MPC_RMU_SHAPER_RAMB_EXP_REGION12_NUM_SEGMENTS 12 14 MPC_RMU_SHAPER_RAMB_EXP_REGION13_LUT_OFFSET 16 24 MPC_RMU_SHAPER_RAMB_EXP_REGION13_NUM_SEGMENTS 28 30 regMPC_RMU1_SHAPER_RAMB_REGION_14_15 0 0x6ef 4 0 3 MPC_RMU_SHAPER_RAMB_EXP_REGION14_LUT_OFFSET 0 8 MPC_RMU_SHAPER_RAMB_EXP_REGION14_NUM_SEGMENTS 12 14 MPC_RMU_SHAPER_RAMB_EXP_REGION15_LUT_OFFSET 16 24 MPC_RMU_SHAPER_RAMB_EXP_REGION15_NUM_SEGMENTS 28 30 regMPC_RMU1_SHAPER_RAMB_REGION_16_17 0 0x6f0 4 0 3 MPC_RMU_SHAPER_RAMB_EXP_REGION16_LUT_OFFSET 0 8 MPC_RMU_SHAPER_RAMB_EXP_REGION16_NUM_SEGMENTS 12 14 MPC_RMU_SHAPER_RAMB_EXP_REGION17_LUT_OFFSET 16 24 MPC_RMU_SHAPER_RAMB_EXP_REGION17_NUM_SEGMENTS 28 30 regMPC_RMU1_SHAPER_RAMB_REGION_18_19 0 0x6f1 4 0 3 MPC_RMU_SHAPER_RAMB_EXP_REGION18_LUT_OFFSET 0 8 MPC_RMU_SHAPER_RAMB_EXP_REGION18_NUM_SEGMENTS 12 14 MPC_RMU_SHAPER_RAMB_EXP_REGION19_LUT_OFFSET 16 24 MPC_RMU_SHAPER_RAMB_EXP_REGION19_NUM_SEGMENTS 28 30 regMPC_RMU1_SHAPER_RAMB_REGION_20_21 0 0x6f2 4 0 3 MPC_RMU_SHAPER_RAMB_EXP_REGION20_LUT_OFFSET 0 8 MPC_RMU_SHAPER_RAMB_EXP_REGION20_NUM_SEGMENTS 12 14 MPC_RMU_SHAPER_RAMB_EXP_REGION21_LUT_OFFSET 16 24 MPC_RMU_SHAPER_RAMB_EXP_REGION21_NUM_SEGMENTS 28 30 regMPC_RMU1_SHAPER_RAMB_REGION_22_23 0 0x6f3 4 0 3 MPC_RMU_SHAPER_RAMB_EXP_REGION22_LUT_OFFSET 0 8 MPC_RMU_SHAPER_RAMB_EXP_REGION22_NUM_SEGMENTS 12 14 MPC_RMU_SHAPER_RAMB_EXP_REGION23_LUT_OFFSET 16 24 MPC_RMU_SHAPER_RAMB_EXP_REGION23_NUM_SEGMENTS 28 30 regMPC_RMU1_SHAPER_RAMB_REGION_24_25 0 0x6f4 4 0 3 MPC_RMU_SHAPER_RAMB_EXP_REGION24_LUT_OFFSET 0 8 MPC_RMU_SHAPER_RAMB_EXP_REGION24_NUM_SEGMENTS 12 14 MPC_RMU_SHAPER_RAMB_EXP_REGION25_LUT_OFFSET 16 24 MPC_RMU_SHAPER_RAMB_EXP_REGION25_NUM_SEGMENTS 28 30 regMPC_RMU1_SHAPER_RAMB_REGION_26_27 0 0x6f5 4 0 3 MPC_RMU_SHAPER_RAMB_EXP_REGION26_LUT_OFFSET 0 8 MPC_RMU_SHAPER_RAMB_EXP_REGION26_NUM_SEGMENTS 12 14 MPC_RMU_SHAPER_RAMB_EXP_REGION27_LUT_OFFSET 16 24 MPC_RMU_SHAPER_RAMB_EXP_REGION27_NUM_SEGMENTS 28 30 regMPC_RMU1_SHAPER_RAMB_REGION_28_29 0 0x6f6 4 0 3 MPC_RMU_SHAPER_RAMB_EXP_REGION28_LUT_OFFSET 0 8 MPC_RMU_SHAPER_RAMB_EXP_REGION28_NUM_SEGMENTS 12 14 MPC_RMU_SHAPER_RAMB_EXP_REGION29_LUT_OFFSET 16 24 MPC_RMU_SHAPER_RAMB_EXP_REGION29_NUM_SEGMENTS 28 30 regMPC_RMU1_SHAPER_RAMB_REGION_30_31 0 0x6f7 4 0 3 MPC_RMU_SHAPER_RAMB_EXP_REGION30_LUT_OFFSET 0 8 MPC_RMU_SHAPER_RAMB_EXP_REGION30_NUM_SEGMENTS 12 14 MPC_RMU_SHAPER_RAMB_EXP_REGION31_LUT_OFFSET 16 24 MPC_RMU_SHAPER_RAMB_EXP_REGION31_NUM_SEGMENTS 28 30 regMPC_RMU1_SHAPER_RAMB_REGION_32_33 0 0x6f8 4 0 3 MPC_RMU_SHAPER_RAMB_EXP_REGION32_LUT_OFFSET 0 8 MPC_RMU_SHAPER_RAMB_EXP_REGION32_NUM_SEGMENTS 12 14 MPC_RMU_SHAPER_RAMB_EXP_REGION33_LUT_OFFSET 16 24 MPC_RMU_SHAPER_RAMB_EXP_REGION33_NUM_SEGMENTS 28 30 regMPC_RMU1_3DLUT_MODE 0 0x6f9 3 0 3 MPC_RMU_3DLUT_MODE 0 1 MPC_RMU_3DLUT_SIZE 4 4 MPC_RMU_3DLUT_MODE_CURRENT 8 9 regMPC_RMU1_3DLUT_INDEX 0 0x6fa 1 0 3 MPC_RMU_3DLUT_INDEX 0 10 regMPC_RMU1_3DLUT_DATA 0 0x6fb 2 0 3 MPC_RMU_3DLUT_DATA0 0 15 MPC_RMU_3DLUT_DATA1 16 31 regMPC_RMU1_3DLUT_DATA_30BIT 0 0x6fc 1 0 3 MPC_RMU_3DLUT_DATA_30BIT 2 31 regMPC_RMU1_3DLUT_READ_WRITE_CONTROL 0 0x6fd 4 0 3 MPC_RMU_3DLUT_WRITE_EN_MASK 0 3 MPC_RMU_3DLUT_RAM_SEL 4 4 MPC_RMU_3DLUT_30BIT_EN 8 8 MPC_RMU_3DLUT_READ_SEL 16 17 regMPC_RMU1_3DLUT_OUT_NORM_FACTOR 0 0x6fe 1 0 3 MPC_RMU_3DLUT_OUT_NORM_FACTOR 0 15 regMPC_RMU1_3DLUT_OUT_OFFSET_R 0 0x6ff 2 0 3 MPC_RMU_3DLUT_OUT_OFFSET_R 0 15 MPC_RMU_3DLUT_OUT_SCALE_R 16 31 regMPC_RMU1_3DLUT_OUT_OFFSET_G 0 0x700 2 0 3 MPC_RMU_3DLUT_OUT_OFFSET_G 0 15 MPC_RMU_3DLUT_OUT_SCALE_G 16 31 regMPC_RMU1_3DLUT_OUT_OFFSET_B 0 0x701 2 0 3 MPC_RMU_3DLUT_OUT_OFFSET_B 0 15 MPC_RMU_3DLUT_OUT_SCALE_B 16 31 regABM0_BL1_PWM_AMBIENT_LIGHT_LEVEL 0 0xe7a 1 0 3 BL1_PWM_AMBIENT_LIGHT_LEVEL 0 16 regABM0_BL1_PWM_USER_LEVEL 0 0xe7b 1 0 3 BL1_PWM_USER_LEVEL 0 16 regABM0_BL1_PWM_TARGET_ABM_LEVEL 0 0xe7c 1 0 3 BL1_PWM_TARGET_ABM_LEVEL 0 16 regABM0_BL1_PWM_CURRENT_ABM_LEVEL 0 0xe7d 1 0 3 BL1_PWM_CURRENT_ABM_LEVEL 0 16 regABM0_BL1_PWM_FINAL_DUTY_CYCLE 0 0xe7e 1 0 3 BL1_PWM_FINAL_DUTY_CYCLE 0 16 regABM0_BL1_PWM_MINIMUM_DUTY_CYCLE 0 0xe7f 1 0 3 BL1_PWM_MINIMUM_DUTY_CYCLE 0 16 regABM0_BL1_PWM_ABM_CNTL 0 0xe80 5 0 3 BL1_PWM_USE_ABM_EN 0 0 BL1_PWM_USE_AMBIENT_LEVEL_EN 1 1 BL1_PWM_AUTO_UPDATE_CURRENT_ABM_LEVEL_EN 2 2 BL1_PWM_AUTO_CALC_FINAL_DUTY_CYCLE_EN 3 3 BL1_PWM_AUTO_UPDATE_CURRENT_ABM_STEP_SIZE 16 31 regABM0_BL1_PWM_BL_UPDATE_SAMPLE_RATE 0 0xe81 5 0 3 BL1_PWM_BL_UPDATE_SAMPLE_RATE_COUNT_EN 0 0 BL1_PWM_BL_UPDATE_RESET_SAMPLE_RATE_FRAME_COUNTER 1 1 BL1_PWM_BL_UPDATE_SAMPLE_RATE_FRAME_COUNT 8 15 BL1_PWM_BL_UPDATE_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET 16 23 ABM1_HGLS_REG_LOCK 31 31 regABM0_BL1_PWM_GRP2_REG_LOCK 0 0xe82 6 0 3 BL1_PWM_GRP2_REG_LOCK 0 0 BL1_PWM_GRP2_REG_UPDATE_PENDING 8 8 BL1_PWM_GRP2_UPDATE_AT_FRAME_START 16 16 BL1_PWM_GRP2_FRAME_START_DISP_SEL 17 19 BL1_PWM_GRP2_READBACK_DB_REG_VALUE_EN 24 24 BL1_PWM_GRP2_IGNORE_MASTER_LOCK_EN 31 31 regABM0_DC_ABM1_CNTL 0 0xe83 2 0 3 ABM1_EN 0 0 ABM1_PROCESSING_BYPASS 4 4 regABM0_DC_ABM1_IPCSC_COEFF_SEL 0 0xe84 4 0 3 ABM1_IPCSC_COEFF_SEL_B 0 3 ABM1_IPCSC_COEFF_SEL_G 8 11 ABM1_IPCSC_COEFF_SEL_R 16 19 ABM1_HGLS_REG_LOCK 31 31 regABM0_DC_ABM1_ACE_OFFSET_SLOPE_0 0 0xe85 3 0 3 ABM1_ACE_SLOPE_0 0 14 ABM1_ACE_OFFSET_0 16 26 ABM1_ACE_LOCK 31 31 regABM0_DC_ABM1_ACE_OFFSET_SLOPE_1 0 0xe86 3 0 3 ABM1_ACE_SLOPE_1 0 14 ABM1_ACE_OFFSET_1 16 26 ABM1_ACE_LOCK 31 31 regABM0_DC_ABM1_ACE_OFFSET_SLOPE_2 0 0xe87 3 0 3 ABM1_ACE_SLOPE_2 0 14 ABM1_ACE_OFFSET_2 16 26 ABM1_ACE_LOCK 31 31 regABM0_DC_ABM1_ACE_OFFSET_SLOPE_3 0 0xe88 3 0 3 ABM1_ACE_SLOPE_3 0 14 ABM1_ACE_OFFSET_3 16 26 ABM1_ACE_LOCK 31 31 regABM0_DC_ABM1_ACE_OFFSET_SLOPE_4 0 0xe89 3 0 3 ABM1_ACE_SLOPE_4 0 14 ABM1_ACE_OFFSET_4 16 26 ABM1_ACE_LOCK 31 31 regABM0_DC_ABM1_ACE_THRES_12 0 0xe8a 3 0 3 ABM1_ACE_THRES_1 0 9 ABM1_ACE_THRES_2 16 25 ABM1_ACE_LOCK 31 31 regABM0_DC_ABM1_ACE_THRES_34 0 0xe8b 6 0 3 ABM1_ACE_THRES_3 0 9 ABM1_ACE_THRES_4 16 25 ABM1_ACE_IGNORE_MASTER_LOCK_EN 28 28 ABM1_ACE_READBACK_DB_REG_VALUE_EN 29 29 ABM1_ACE_DBUF_REG_UPDATE_PENDING 30 30 ABM1_ACE_LOCK 31 31 regABM0_DC_ABM1_ACE_CNTL_MISC 0 0xe8c 2 0 3 ABM1_ACE_REG_WR_MISSED_FRAME 0 0 ABM1_ACE_REG_WR_MISSED_FRAME_CLEAR 8 8 regABM0_DC_ABM1_HGLS_REG_READ_PROGRESS 0 0xe8e 9 0 3 ABM1_HG_REG_READ_IN_PROGRESS 0 0 ABM1_LS_REG_READ_IN_PROGRESS 1 1 ABM1_BL_REG_READ_IN_PROGRESS 2 2 ABM1_HG_REG_READ_MISSED_FRAME 8 8 ABM1_LS_REG_READ_MISSED_FRAME 9 9 ABM1_BL_REG_READ_MISSED_FRAME 10 10 ABM1_HG_REG_READ_MISSED_FRAME_CLEAR 16 16 ABM1_LS_REG_READ_MISSED_FRAME_CLEAR 24 24 ABM1_BL_REG_READ_MISSED_FRAME_CLEAR 31 31 regABM0_DC_ABM1_HG_MISC_CTRL 0 0xe8f 11 0 3 ABM1_HG_NUM_OF_BINS_SEL 0 1 ABM1_HG_VMAX_SEL 8 8 ABM1_HG_FINE_MODE_BIN_SEL 12 12 ABM1_HG_BIN_BITWIDTH_SIZE_SEL 16 17 ABM1_OVR_SCAN_PIXEL_PROCESS_EN 20 20 ABM1_DBUF_HGLS_READBACK_DB_REG_VALUE_EN 23 23 ABM1_DBUF_HGLS_REG_FRAME_START_DISP_SEL 24 26 ABM1_DBUF_HGLS_REG_UPDATE_AT_FRAME_START 28 28 ABM1_HGLS_IGNORE_MASTER_LOCK_EN 29 29 ABM1_DBUF_HGLS_REG_UPDATE_PENDING 30 30 ABM1_HGLS_REG_LOCK 31 31 regABM0_DC_ABM1_LS_SUM_OF_LUMA 0 0xe90 1 0 3 ABM1_LS_SUM_OF_LUMA 0 31 regABM0_DC_ABM1_LS_MIN_MAX_LUMA 0 0xe91 2 0 3 ABM1_LS_MIN_LUMA 0 9 ABM1_LS_MAX_LUMA 16 25 regABM0_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA 0 0xe92 2 0 3 ABM1_LS_FILTERED_MIN_LUMA 0 9 ABM1_LS_FILTERED_MAX_LUMA 16 25 regABM0_DC_ABM1_LS_PIXEL_COUNT 0 0xe93 2 0 3 ABM1_LS_PIXEL_COUNT 0 23 ABM1_LS_SUM_OF_LUMA_MSB 24 31 regABM0_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES 0 0xe94 3 0 3 ABM1_LS_MIN_PIXEL_VALUE_THRES 0 9 ABM1_LS_MAX_PIXEL_VALUE_THRES 16 25 ABM1_HGLS_REG_LOCK 31 31 regABM0_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT 0 0xe95 1 0 3 ABM1_LS_MIN_PIXEL_VALUE_COUNT 0 23 regABM0_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT 0 0xe96 1 0 3 ABM1_LS_MAX_PIXEL_VALUE_COUNT 0 23 regABM0_DC_ABM1_HG_SAMPLE_RATE 0 0xe97 5 0 3 ABM1_HG_SAMPLE_RATE_COUNT_EN 0 0 ABM1_HG_RESET_SAMPLE_RATE_FRAME_COUNTER 1 1 ABM1_HG_SAMPLE_RATE_FRAME_COUNT 8 15 ABM1_HG_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET 16 23 ABM1_HGLS_REG_LOCK 31 31 regABM0_DC_ABM1_LS_SAMPLE_RATE 0 0xe98 5 0 3 ABM1_LS_SAMPLE_RATE_COUNT_EN 0 0 ABM1_LS_RESET_SAMPLE_RATE_FRAME_COUNTER 1 1 ABM1_LS_SAMPLE_RATE_FRAME_COUNT 8 15 ABM1_LS_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET 16 23 ABM1_HGLS_REG_LOCK 31 31 regABM0_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG 0 0xe99 1 0 3 ABM1_HG_BIN_1_32_SHIFT_FLAG 0 31 regABM0_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX 0 0xe9a 1 0 3 ABM1_HG_BIN_1_8_SHIFT_INDEX 0 31 regABM0_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX 0 0xe9b 1 0 3 ABM1_HG_BIN_9_16_SHIFT_INDEX 0 31 regABM0_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX 0 0xe9c 1 0 3 ABM1_HG_BIN_17_24_SHIFT_INDEX 0 31 regABM0_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX 0 0xe9d 1 0 3 ABM1_HG_BIN_25_32_SHIFT_INDEX 0 31 regABM0_DC_ABM1_HG_RESULT_1 0 0xe9e 1 0 3 ABM1_HG_RESULT_1 0 31 regABM0_DC_ABM1_HG_RESULT_2 0 0xe9f 1 0 3 ABM1_HG_RESULT_2 0 31 regABM0_DC_ABM1_HG_RESULT_3 0 0xea0 1 0 3 ABM1_HG_RESULT_3 0 31 regABM0_DC_ABM1_HG_RESULT_4 0 0xea1 1 0 3 ABM1_HG_RESULT_4 0 31 regABM0_DC_ABM1_HG_RESULT_5 0 0xea2 1 0 3 ABM1_HG_RESULT_5 0 31 regABM0_DC_ABM1_HG_RESULT_6 0 0xea3 1 0 3 ABM1_HG_RESULT_6 0 31 regABM0_DC_ABM1_HG_RESULT_7 0 0xea4 1 0 3 ABM1_HG_RESULT_7 0 31 regABM0_DC_ABM1_HG_RESULT_8 0 0xea5 1 0 3 ABM1_HG_RESULT_8 0 31 regABM0_DC_ABM1_HG_RESULT_9 0 0xea6 1 0 3 ABM1_HG_RESULT_9 0 31 regABM0_DC_ABM1_HG_RESULT_10 0 0xea7 1 0 3 ABM1_HG_RESULT_10 0 31 regABM0_DC_ABM1_HG_RESULT_11 0 0xea8 1 0 3 ABM1_HG_RESULT_11 0 31 regABM0_DC_ABM1_HG_RESULT_12 0 0xea9 1 0 3 ABM1_HG_RESULT_12 0 31 regABM0_DC_ABM1_HG_RESULT_13 0 0xeaa 1 0 3 ABM1_HG_RESULT_13 0 31 regABM0_DC_ABM1_HG_RESULT_14 0 0xeab 1 0 3 ABM1_HG_RESULT_14 0 31 regABM0_DC_ABM1_HG_RESULT_15 0 0xeac 1 0 3 ABM1_HG_RESULT_15 0 31 regABM0_DC_ABM1_HG_RESULT_16 0 0xead 1 0 3 ABM1_HG_RESULT_16 0 31 regABM0_DC_ABM1_HG_RESULT_17 0 0xeae 1 0 3 ABM1_HG_RESULT_17 0 31 regABM0_DC_ABM1_HG_RESULT_18 0 0xeaf 1 0 3 ABM1_HG_RESULT_18 0 31 regABM0_DC_ABM1_HG_RESULT_19 0 0xeb0 1 0 3 ABM1_HG_RESULT_19 0 31 regABM0_DC_ABM1_HG_RESULT_20 0 0xeb1 1 0 3 ABM1_HG_RESULT_20 0 31 regABM0_DC_ABM1_HG_RESULT_21 0 0xeb2 1 0 3 ABM1_HG_RESULT_21 0 31 regABM0_DC_ABM1_HG_RESULT_22 0 0xeb3 1 0 3 ABM1_HG_RESULT_22 0 31 regABM0_DC_ABM1_HG_RESULT_23 0 0xeb4 1 0 3 ABM1_HG_RESULT_23 0 31 regABM0_DC_ABM1_HG_RESULT_24 0 0xeb5 1 0 3 ABM1_HG_RESULT_24 0 31 regABM0_DC_ABM1_BL_MASTER_LOCK 0 0xeb6 1 0 3 ABM1_BL_MASTER_LOCK 31 31 regABM1_BL1_PWM_AMBIENT_LIGHT_LEVEL 0 0xebb 1 0 3 BL1_PWM_AMBIENT_LIGHT_LEVEL 0 16 regABM1_BL1_PWM_USER_LEVEL 0 0xebc 1 0 3 BL1_PWM_USER_LEVEL 0 16 regABM1_BL1_PWM_TARGET_ABM_LEVEL 0 0xebd 1 0 3 BL1_PWM_TARGET_ABM_LEVEL 0 16 regABM1_BL1_PWM_CURRENT_ABM_LEVEL 0 0xebe 1 0 3 BL1_PWM_CURRENT_ABM_LEVEL 0 16 regABM1_BL1_PWM_FINAL_DUTY_CYCLE 0 0xebf 1 0 3 BL1_PWM_FINAL_DUTY_CYCLE 0 16 regABM1_BL1_PWM_MINIMUM_DUTY_CYCLE 0 0xec0 1 0 3 BL1_PWM_MINIMUM_DUTY_CYCLE 0 16 regABM1_BL1_PWM_ABM_CNTL 0 0xec1 5 0 3 BL1_PWM_USE_ABM_EN 0 0 BL1_PWM_USE_AMBIENT_LEVEL_EN 1 1 BL1_PWM_AUTO_UPDATE_CURRENT_ABM_LEVEL_EN 2 2 BL1_PWM_AUTO_CALC_FINAL_DUTY_CYCLE_EN 3 3 BL1_PWM_AUTO_UPDATE_CURRENT_ABM_STEP_SIZE 16 31 regABM1_BL1_PWM_BL_UPDATE_SAMPLE_RATE 0 0xec2 5 0 3 BL1_PWM_BL_UPDATE_SAMPLE_RATE_COUNT_EN 0 0 BL1_PWM_BL_UPDATE_RESET_SAMPLE_RATE_FRAME_COUNTER 1 1 BL1_PWM_BL_UPDATE_SAMPLE_RATE_FRAME_COUNT 8 15 BL1_PWM_BL_UPDATE_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET 16 23 ABM1_HGLS_REG_LOCK 31 31 regABM1_BL1_PWM_GRP2_REG_LOCK 0 0xec3 6 0 3 BL1_PWM_GRP2_REG_LOCK 0 0 BL1_PWM_GRP2_REG_UPDATE_PENDING 8 8 BL1_PWM_GRP2_UPDATE_AT_FRAME_START 16 16 BL1_PWM_GRP2_FRAME_START_DISP_SEL 17 19 BL1_PWM_GRP2_READBACK_DB_REG_VALUE_EN 24 24 BL1_PWM_GRP2_IGNORE_MASTER_LOCK_EN 31 31 regABM1_DC_ABM1_CNTL 0 0xec4 2 0 3 ABM1_EN 0 0 ABM1_PROCESSING_BYPASS 4 4 regABM1_DC_ABM1_IPCSC_COEFF_SEL 0 0xec5 4 0 3 ABM1_IPCSC_COEFF_SEL_B 0 3 ABM1_IPCSC_COEFF_SEL_G 8 11 ABM1_IPCSC_COEFF_SEL_R 16 19 ABM1_HGLS_REG_LOCK 31 31 regABM1_DC_ABM1_ACE_OFFSET_SLOPE_0 0 0xec6 3 0 3 ABM1_ACE_SLOPE_0 0 14 ABM1_ACE_OFFSET_0 16 26 ABM1_ACE_LOCK 31 31 regABM1_DC_ABM1_ACE_OFFSET_SLOPE_1 0 0xec7 3 0 3 ABM1_ACE_SLOPE_1 0 14 ABM1_ACE_OFFSET_1 16 26 ABM1_ACE_LOCK 31 31 regABM1_DC_ABM1_ACE_OFFSET_SLOPE_2 0 0xec8 3 0 3 ABM1_ACE_SLOPE_2 0 14 ABM1_ACE_OFFSET_2 16 26 ABM1_ACE_LOCK 31 31 regABM1_DC_ABM1_ACE_OFFSET_SLOPE_3 0 0xec9 3 0 3 ABM1_ACE_SLOPE_3 0 14 ABM1_ACE_OFFSET_3 16 26 ABM1_ACE_LOCK 31 31 regABM1_DC_ABM1_ACE_OFFSET_SLOPE_4 0 0xeca 3 0 3 ABM1_ACE_SLOPE_4 0 14 ABM1_ACE_OFFSET_4 16 26 ABM1_ACE_LOCK 31 31 regABM1_DC_ABM1_ACE_THRES_12 0 0xecb 3 0 3 ABM1_ACE_THRES_1 0 9 ABM1_ACE_THRES_2 16 25 ABM1_ACE_LOCK 31 31 regABM1_DC_ABM1_ACE_THRES_34 0 0xecc 6 0 3 ABM1_ACE_THRES_3 0 9 ABM1_ACE_THRES_4 16 25 ABM1_ACE_IGNORE_MASTER_LOCK_EN 28 28 ABM1_ACE_READBACK_DB_REG_VALUE_EN 29 29 ABM1_ACE_DBUF_REG_UPDATE_PENDING 30 30 ABM1_ACE_LOCK 31 31 regABM1_DC_ABM1_ACE_CNTL_MISC 0 0xecd 2 0 3 ABM1_ACE_REG_WR_MISSED_FRAME 0 0 ABM1_ACE_REG_WR_MISSED_FRAME_CLEAR 8 8 regABM1_DC_ABM1_HGLS_REG_READ_PROGRESS 0 0xecf 9 0 3 ABM1_HG_REG_READ_IN_PROGRESS 0 0 ABM1_LS_REG_READ_IN_PROGRESS 1 1 ABM1_BL_REG_READ_IN_PROGRESS 2 2 ABM1_HG_REG_READ_MISSED_FRAME 8 8 ABM1_LS_REG_READ_MISSED_FRAME 9 9 ABM1_BL_REG_READ_MISSED_FRAME 10 10 ABM1_HG_REG_READ_MISSED_FRAME_CLEAR 16 16 ABM1_LS_REG_READ_MISSED_FRAME_CLEAR 24 24 ABM1_BL_REG_READ_MISSED_FRAME_CLEAR 31 31 regABM1_DC_ABM1_HG_MISC_CTRL 0 0xed0 11 0 3 ABM1_HG_NUM_OF_BINS_SEL 0 1 ABM1_HG_VMAX_SEL 8 8 ABM1_HG_FINE_MODE_BIN_SEL 12 12 ABM1_HG_BIN_BITWIDTH_SIZE_SEL 16 17 ABM1_OVR_SCAN_PIXEL_PROCESS_EN 20 20 ABM1_DBUF_HGLS_READBACK_DB_REG_VALUE_EN 23 23 ABM1_DBUF_HGLS_REG_FRAME_START_DISP_SEL 24 26 ABM1_DBUF_HGLS_REG_UPDATE_AT_FRAME_START 28 28 ABM1_HGLS_IGNORE_MASTER_LOCK_EN 29 29 ABM1_DBUF_HGLS_REG_UPDATE_PENDING 30 30 ABM1_HGLS_REG_LOCK 31 31 regABM1_DC_ABM1_LS_SUM_OF_LUMA 0 0xed1 1 0 3 ABM1_LS_SUM_OF_LUMA 0 31 regABM1_DC_ABM1_LS_MIN_MAX_LUMA 0 0xed2 2 0 3 ABM1_LS_MIN_LUMA 0 9 ABM1_LS_MAX_LUMA 16 25 regABM1_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA 0 0xed3 2 0 3 ABM1_LS_FILTERED_MIN_LUMA 0 9 ABM1_LS_FILTERED_MAX_LUMA 16 25 regABM1_DC_ABM1_LS_PIXEL_COUNT 0 0xed4 2 0 3 ABM1_LS_PIXEL_COUNT 0 23 ABM1_LS_SUM_OF_LUMA_MSB 24 31 regABM1_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES 0 0xed5 3 0 3 ABM1_LS_MIN_PIXEL_VALUE_THRES 0 9 ABM1_LS_MAX_PIXEL_VALUE_THRES 16 25 ABM1_HGLS_REG_LOCK 31 31 regABM1_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT 0 0xed6 1 0 3 ABM1_LS_MIN_PIXEL_VALUE_COUNT 0 23 regABM1_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT 0 0xed7 1 0 3 ABM1_LS_MAX_PIXEL_VALUE_COUNT 0 23 regABM1_DC_ABM1_HG_SAMPLE_RATE 0 0xed8 5 0 3 ABM1_HG_SAMPLE_RATE_COUNT_EN 0 0 ABM1_HG_RESET_SAMPLE_RATE_FRAME_COUNTER 1 1 ABM1_HG_SAMPLE_RATE_FRAME_COUNT 8 15 ABM1_HG_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET 16 23 ABM1_HGLS_REG_LOCK 31 31 regABM1_DC_ABM1_LS_SAMPLE_RATE 0 0xed9 5 0 3 ABM1_LS_SAMPLE_RATE_COUNT_EN 0 0 ABM1_LS_RESET_SAMPLE_RATE_FRAME_COUNTER 1 1 ABM1_LS_SAMPLE_RATE_FRAME_COUNT 8 15 ABM1_LS_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET 16 23 ABM1_HGLS_REG_LOCK 31 31 regABM1_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG 0 0xeda 1 0 3 ABM1_HG_BIN_1_32_SHIFT_FLAG 0 31 regABM1_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX 0 0xedb 1 0 3 ABM1_HG_BIN_1_8_SHIFT_INDEX 0 31 regABM1_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX 0 0xedc 1 0 3 ABM1_HG_BIN_9_16_SHIFT_INDEX 0 31 regABM1_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX 0 0xedd 1 0 3 ABM1_HG_BIN_17_24_SHIFT_INDEX 0 31 regABM1_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX 0 0xede 1 0 3 ABM1_HG_BIN_25_32_SHIFT_INDEX 0 31 regABM1_DC_ABM1_HG_RESULT_1 0 0xedf 1 0 3 ABM1_HG_RESULT_1 0 31 regABM1_DC_ABM1_HG_RESULT_2 0 0xee0 1 0 3 ABM1_HG_RESULT_2 0 31 regABM1_DC_ABM1_HG_RESULT_3 0 0xee1 1 0 3 ABM1_HG_RESULT_3 0 31 regABM1_DC_ABM1_HG_RESULT_4 0 0xee2 1 0 3 ABM1_HG_RESULT_4 0 31 regABM1_DC_ABM1_HG_RESULT_5 0 0xee3 1 0 3 ABM1_HG_RESULT_5 0 31 regABM1_DC_ABM1_HG_RESULT_6 0 0xee4 1 0 3 ABM1_HG_RESULT_6 0 31 regABM1_DC_ABM1_HG_RESULT_7 0 0xee5 1 0 3 ABM1_HG_RESULT_7 0 31 regABM1_DC_ABM1_HG_RESULT_8 0 0xee6 1 0 3 ABM1_HG_RESULT_8 0 31 regABM1_DC_ABM1_HG_RESULT_9 0 0xee7 1 0 3 ABM1_HG_RESULT_9 0 31 regABM1_DC_ABM1_HG_RESULT_10 0 0xee8 1 0 3 ABM1_HG_RESULT_10 0 31 regABM1_DC_ABM1_HG_RESULT_11 0 0xee9 1 0 3 ABM1_HG_RESULT_11 0 31 regABM1_DC_ABM1_HG_RESULT_12 0 0xeea 1 0 3 ABM1_HG_RESULT_12 0 31 regABM1_DC_ABM1_HG_RESULT_13 0 0xeeb 1 0 3 ABM1_HG_RESULT_13 0 31 regABM1_DC_ABM1_HG_RESULT_14 0 0xeec 1 0 3 ABM1_HG_RESULT_14 0 31 regABM1_DC_ABM1_HG_RESULT_15 0 0xeed 1 0 3 ABM1_HG_RESULT_15 0 31 regABM1_DC_ABM1_HG_RESULT_16 0 0xeee 1 0 3 ABM1_HG_RESULT_16 0 31 regABM1_DC_ABM1_HG_RESULT_17 0 0xeef 1 0 3 ABM1_HG_RESULT_17 0 31 regABM1_DC_ABM1_HG_RESULT_18 0 0xef0 1 0 3 ABM1_HG_RESULT_18 0 31 regABM1_DC_ABM1_HG_RESULT_19 0 0xef1 1 0 3 ABM1_HG_RESULT_19 0 31 regABM1_DC_ABM1_HG_RESULT_20 0 0xef2 1 0 3 ABM1_HG_RESULT_20 0 31 regABM1_DC_ABM1_HG_RESULT_21 0 0xef3 1 0 3 ABM1_HG_RESULT_21 0 31 regABM1_DC_ABM1_HG_RESULT_22 0 0xef4 1 0 3 ABM1_HG_RESULT_22 0 31 regABM1_DC_ABM1_HG_RESULT_23 0 0xef5 1 0 3 ABM1_HG_RESULT_23 0 31 regABM1_DC_ABM1_HG_RESULT_24 0 0xef6 1 0 3 ABM1_HG_RESULT_24 0 31 regABM1_DC_ABM1_BL_MASTER_LOCK 0 0xef7 1 0 3 ABM1_BL_MASTER_LOCK 31 31 regABM2_BL1_PWM_AMBIENT_LIGHT_LEVEL 0 0xefc 1 0 3 BL1_PWM_AMBIENT_LIGHT_LEVEL 0 16 regABM2_BL1_PWM_USER_LEVEL 0 0xefd 1 0 3 BL1_PWM_USER_LEVEL 0 16 regABM2_BL1_PWM_TARGET_ABM_LEVEL 0 0xefe 1 0 3 BL1_PWM_TARGET_ABM_LEVEL 0 16 regABM2_BL1_PWM_CURRENT_ABM_LEVEL 0 0xeff 1 0 3 BL1_PWM_CURRENT_ABM_LEVEL 0 16 regABM2_BL1_PWM_FINAL_DUTY_CYCLE 0 0xf00 1 0 3 BL1_PWM_FINAL_DUTY_CYCLE 0 16 regABM2_BL1_PWM_MINIMUM_DUTY_CYCLE 0 0xf01 1 0 3 BL1_PWM_MINIMUM_DUTY_CYCLE 0 16 regABM2_BL1_PWM_ABM_CNTL 0 0xf02 5 0 3 BL1_PWM_USE_ABM_EN 0 0 BL1_PWM_USE_AMBIENT_LEVEL_EN 1 1 BL1_PWM_AUTO_UPDATE_CURRENT_ABM_LEVEL_EN 2 2 BL1_PWM_AUTO_CALC_FINAL_DUTY_CYCLE_EN 3 3 BL1_PWM_AUTO_UPDATE_CURRENT_ABM_STEP_SIZE 16 31 regABM2_BL1_PWM_BL_UPDATE_SAMPLE_RATE 0 0xf03 5 0 3 BL1_PWM_BL_UPDATE_SAMPLE_RATE_COUNT_EN 0 0 BL1_PWM_BL_UPDATE_RESET_SAMPLE_RATE_FRAME_COUNTER 1 1 BL1_PWM_BL_UPDATE_SAMPLE_RATE_FRAME_COUNT 8 15 BL1_PWM_BL_UPDATE_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET 16 23 ABM1_HGLS_REG_LOCK 31 31 regABM2_BL1_PWM_GRP2_REG_LOCK 0 0xf04 6 0 3 BL1_PWM_GRP2_REG_LOCK 0 0 BL1_PWM_GRP2_REG_UPDATE_PENDING 8 8 BL1_PWM_GRP2_UPDATE_AT_FRAME_START 16 16 BL1_PWM_GRP2_FRAME_START_DISP_SEL 17 19 BL1_PWM_GRP2_READBACK_DB_REG_VALUE_EN 24 24 BL1_PWM_GRP2_IGNORE_MASTER_LOCK_EN 31 31 regABM2_DC_ABM1_CNTL 0 0xf05 2 0 3 ABM1_EN 0 0 ABM1_PROCESSING_BYPASS 4 4 regABM2_DC_ABM1_IPCSC_COEFF_SEL 0 0xf06 4 0 3 ABM1_IPCSC_COEFF_SEL_B 0 3 ABM1_IPCSC_COEFF_SEL_G 8 11 ABM1_IPCSC_COEFF_SEL_R 16 19 ABM1_HGLS_REG_LOCK 31 31 regABM2_DC_ABM1_ACE_OFFSET_SLOPE_0 0 0xf07 3 0 3 ABM1_ACE_SLOPE_0 0 14 ABM1_ACE_OFFSET_0 16 26 ABM1_ACE_LOCK 31 31 regABM2_DC_ABM1_ACE_OFFSET_SLOPE_1 0 0xf08 3 0 3 ABM1_ACE_SLOPE_1 0 14 ABM1_ACE_OFFSET_1 16 26 ABM1_ACE_LOCK 31 31 regABM2_DC_ABM1_ACE_OFFSET_SLOPE_2 0 0xf09 3 0 3 ABM1_ACE_SLOPE_2 0 14 ABM1_ACE_OFFSET_2 16 26 ABM1_ACE_LOCK 31 31 regABM2_DC_ABM1_ACE_OFFSET_SLOPE_3 0 0xf0a 3 0 3 ABM1_ACE_SLOPE_3 0 14 ABM1_ACE_OFFSET_3 16 26 ABM1_ACE_LOCK 31 31 regABM2_DC_ABM1_ACE_OFFSET_SLOPE_4 0 0xf0b 3 0 3 ABM1_ACE_SLOPE_4 0 14 ABM1_ACE_OFFSET_4 16 26 ABM1_ACE_LOCK 31 31 regABM2_DC_ABM1_ACE_THRES_12 0 0xf0c 3 0 3 ABM1_ACE_THRES_1 0 9 ABM1_ACE_THRES_2 16 25 ABM1_ACE_LOCK 31 31 regABM2_DC_ABM1_ACE_THRES_34 0 0xf0d 6 0 3 ABM1_ACE_THRES_3 0 9 ABM1_ACE_THRES_4 16 25 ABM1_ACE_IGNORE_MASTER_LOCK_EN 28 28 ABM1_ACE_READBACK_DB_REG_VALUE_EN 29 29 ABM1_ACE_DBUF_REG_UPDATE_PENDING 30 30 ABM1_ACE_LOCK 31 31 regABM2_DC_ABM1_ACE_CNTL_MISC 0 0xf0e 2 0 3 ABM1_ACE_REG_WR_MISSED_FRAME 0 0 ABM1_ACE_REG_WR_MISSED_FRAME_CLEAR 8 8 regABM2_DC_ABM1_HGLS_REG_READ_PROGRESS 0 0xf10 9 0 3 ABM1_HG_REG_READ_IN_PROGRESS 0 0 ABM1_LS_REG_READ_IN_PROGRESS 1 1 ABM1_BL_REG_READ_IN_PROGRESS 2 2 ABM1_HG_REG_READ_MISSED_FRAME 8 8 ABM1_LS_REG_READ_MISSED_FRAME 9 9 ABM1_BL_REG_READ_MISSED_FRAME 10 10 ABM1_HG_REG_READ_MISSED_FRAME_CLEAR 16 16 ABM1_LS_REG_READ_MISSED_FRAME_CLEAR 24 24 ABM1_BL_REG_READ_MISSED_FRAME_CLEAR 31 31 regABM2_DC_ABM1_HG_MISC_CTRL 0 0xf11 11 0 3 ABM1_HG_NUM_OF_BINS_SEL 0 1 ABM1_HG_VMAX_SEL 8 8 ABM1_HG_FINE_MODE_BIN_SEL 12 12 ABM1_HG_BIN_BITWIDTH_SIZE_SEL 16 17 ABM1_OVR_SCAN_PIXEL_PROCESS_EN 20 20 ABM1_DBUF_HGLS_READBACK_DB_REG_VALUE_EN 23 23 ABM1_DBUF_HGLS_REG_FRAME_START_DISP_SEL 24 26 ABM1_DBUF_HGLS_REG_UPDATE_AT_FRAME_START 28 28 ABM1_HGLS_IGNORE_MASTER_LOCK_EN 29 29 ABM1_DBUF_HGLS_REG_UPDATE_PENDING 30 30 ABM1_HGLS_REG_LOCK 31 31 regABM2_DC_ABM1_LS_SUM_OF_LUMA 0 0xf12 1 0 3 ABM1_LS_SUM_OF_LUMA 0 31 regABM2_DC_ABM1_LS_MIN_MAX_LUMA 0 0xf13 2 0 3 ABM1_LS_MIN_LUMA 0 9 ABM1_LS_MAX_LUMA 16 25 regABM2_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA 0 0xf14 2 0 3 ABM1_LS_FILTERED_MIN_LUMA 0 9 ABM1_LS_FILTERED_MAX_LUMA 16 25 regABM2_DC_ABM1_LS_PIXEL_COUNT 0 0xf15 2 0 3 ABM1_LS_PIXEL_COUNT 0 23 ABM1_LS_SUM_OF_LUMA_MSB 24 31 regABM2_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES 0 0xf16 3 0 3 ABM1_LS_MIN_PIXEL_VALUE_THRES 0 9 ABM1_LS_MAX_PIXEL_VALUE_THRES 16 25 ABM1_HGLS_REG_LOCK 31 31 regABM2_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT 0 0xf17 1 0 3 ABM1_LS_MIN_PIXEL_VALUE_COUNT 0 23 regABM2_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT 0 0xf18 1 0 3 ABM1_LS_MAX_PIXEL_VALUE_COUNT 0 23 regABM2_DC_ABM1_HG_SAMPLE_RATE 0 0xf19 5 0 3 ABM1_HG_SAMPLE_RATE_COUNT_EN 0 0 ABM1_HG_RESET_SAMPLE_RATE_FRAME_COUNTER 1 1 ABM1_HG_SAMPLE_RATE_FRAME_COUNT 8 15 ABM1_HG_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET 16 23 ABM1_HGLS_REG_LOCK 31 31 regABM2_DC_ABM1_LS_SAMPLE_RATE 0 0xf1a 5 0 3 ABM1_LS_SAMPLE_RATE_COUNT_EN 0 0 ABM1_LS_RESET_SAMPLE_RATE_FRAME_COUNTER 1 1 ABM1_LS_SAMPLE_RATE_FRAME_COUNT 8 15 ABM1_LS_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET 16 23 ABM1_HGLS_REG_LOCK 31 31 regABM2_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG 0 0xf1b 1 0 3 ABM1_HG_BIN_1_32_SHIFT_FLAG 0 31 regABM2_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX 0 0xf1c 1 0 3 ABM1_HG_BIN_1_8_SHIFT_INDEX 0 31 regABM2_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX 0 0xf1d 1 0 3 ABM1_HG_BIN_9_16_SHIFT_INDEX 0 31 regABM2_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX 0 0xf1e 1 0 3 ABM1_HG_BIN_17_24_SHIFT_INDEX 0 31 regABM2_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX 0 0xf1f 1 0 3 ABM1_HG_BIN_25_32_SHIFT_INDEX 0 31 regABM2_DC_ABM1_HG_RESULT_1 0 0xf20 1 0 3 ABM1_HG_RESULT_1 0 31 regABM2_DC_ABM1_HG_RESULT_2 0 0xf21 1 0 3 ABM1_HG_RESULT_2 0 31 regABM2_DC_ABM1_HG_RESULT_3 0 0xf22 1 0 3 ABM1_HG_RESULT_3 0 31 regABM2_DC_ABM1_HG_RESULT_4 0 0xf23 1 0 3 ABM1_HG_RESULT_4 0 31 regABM2_DC_ABM1_HG_RESULT_5 0 0xf24 1 0 3 ABM1_HG_RESULT_5 0 31 regABM2_DC_ABM1_HG_RESULT_6 0 0xf25 1 0 3 ABM1_HG_RESULT_6 0 31 regABM2_DC_ABM1_HG_RESULT_7 0 0xf26 1 0 3 ABM1_HG_RESULT_7 0 31 regABM2_DC_ABM1_HG_RESULT_8 0 0xf27 1 0 3 ABM1_HG_RESULT_8 0 31 regABM2_DC_ABM1_HG_RESULT_9 0 0xf28 1 0 3 ABM1_HG_RESULT_9 0 31 regABM2_DC_ABM1_HG_RESULT_10 0 0xf29 1 0 3 ABM1_HG_RESULT_10 0 31 regABM2_DC_ABM1_HG_RESULT_11 0 0xf2a 1 0 3 ABM1_HG_RESULT_11 0 31 regABM2_DC_ABM1_HG_RESULT_12 0 0xf2b 1 0 3 ABM1_HG_RESULT_12 0 31 regABM2_DC_ABM1_HG_RESULT_13 0 0xf2c 1 0 3 ABM1_HG_RESULT_13 0 31 regABM2_DC_ABM1_HG_RESULT_14 0 0xf2d 1 0 3 ABM1_HG_RESULT_14 0 31 regABM2_DC_ABM1_HG_RESULT_15 0 0xf2e 1 0 3 ABM1_HG_RESULT_15 0 31 regABM2_DC_ABM1_HG_RESULT_16 0 0xf2f 1 0 3 ABM1_HG_RESULT_16 0 31 regABM2_DC_ABM1_HG_RESULT_17 0 0xf30 1 0 3 ABM1_HG_RESULT_17 0 31 regABM2_DC_ABM1_HG_RESULT_18 0 0xf31 1 0 3 ABM1_HG_RESULT_18 0 31 regABM2_DC_ABM1_HG_RESULT_19 0 0xf32 1 0 3 ABM1_HG_RESULT_19 0 31 regABM2_DC_ABM1_HG_RESULT_20 0 0xf33 1 0 3 ABM1_HG_RESULT_20 0 31 regABM2_DC_ABM1_HG_RESULT_21 0 0xf34 1 0 3 ABM1_HG_RESULT_21 0 31 regABM2_DC_ABM1_HG_RESULT_22 0 0xf35 1 0 3 ABM1_HG_RESULT_22 0 31 regABM2_DC_ABM1_HG_RESULT_23 0 0xf36 1 0 3 ABM1_HG_RESULT_23 0 31 regABM2_DC_ABM1_HG_RESULT_24 0 0xf37 1 0 3 ABM1_HG_RESULT_24 0 31 regABM2_DC_ABM1_BL_MASTER_LOCK 0 0xf38 1 0 3 ABM1_BL_MASTER_LOCK 31 31 regABM3_BL1_PWM_AMBIENT_LIGHT_LEVEL 0 0xf3d 1 0 3 BL1_PWM_AMBIENT_LIGHT_LEVEL 0 16 regABM3_BL1_PWM_USER_LEVEL 0 0xf3e 1 0 3 BL1_PWM_USER_LEVEL 0 16 regABM3_BL1_PWM_TARGET_ABM_LEVEL 0 0xf3f 1 0 3 BL1_PWM_TARGET_ABM_LEVEL 0 16 regABM3_BL1_PWM_CURRENT_ABM_LEVEL 0 0xf40 1 0 3 BL1_PWM_CURRENT_ABM_LEVEL 0 16 regABM3_BL1_PWM_FINAL_DUTY_CYCLE 0 0xf41 1 0 3 BL1_PWM_FINAL_DUTY_CYCLE 0 16 regABM3_BL1_PWM_MINIMUM_DUTY_CYCLE 0 0xf42 1 0 3 BL1_PWM_MINIMUM_DUTY_CYCLE 0 16 regABM3_BL1_PWM_ABM_CNTL 0 0xf43 5 0 3 BL1_PWM_USE_ABM_EN 0 0 BL1_PWM_USE_AMBIENT_LEVEL_EN 1 1 BL1_PWM_AUTO_UPDATE_CURRENT_ABM_LEVEL_EN 2 2 BL1_PWM_AUTO_CALC_FINAL_DUTY_CYCLE_EN 3 3 BL1_PWM_AUTO_UPDATE_CURRENT_ABM_STEP_SIZE 16 31 regABM3_BL1_PWM_BL_UPDATE_SAMPLE_RATE 0 0xf44 5 0 3 BL1_PWM_BL_UPDATE_SAMPLE_RATE_COUNT_EN 0 0 BL1_PWM_BL_UPDATE_RESET_SAMPLE_RATE_FRAME_COUNTER 1 1 BL1_PWM_BL_UPDATE_SAMPLE_RATE_FRAME_COUNT 8 15 BL1_PWM_BL_UPDATE_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET 16 23 ABM1_HGLS_REG_LOCK 31 31 regABM3_BL1_PWM_GRP2_REG_LOCK 0 0xf45 6 0 3 BL1_PWM_GRP2_REG_LOCK 0 0 BL1_PWM_GRP2_REG_UPDATE_PENDING 8 8 BL1_PWM_GRP2_UPDATE_AT_FRAME_START 16 16 BL1_PWM_GRP2_FRAME_START_DISP_SEL 17 19 BL1_PWM_GRP2_READBACK_DB_REG_VALUE_EN 24 24 BL1_PWM_GRP2_IGNORE_MASTER_LOCK_EN 31 31 regABM3_DC_ABM1_CNTL 0 0xf46 2 0 3 ABM1_EN 0 0 ABM1_PROCESSING_BYPASS 4 4 regABM3_DC_ABM1_IPCSC_COEFF_SEL 0 0xf47 4 0 3 ABM1_IPCSC_COEFF_SEL_B 0 3 ABM1_IPCSC_COEFF_SEL_G 8 11 ABM1_IPCSC_COEFF_SEL_R 16 19 ABM1_HGLS_REG_LOCK 31 31 regABM3_DC_ABM1_ACE_OFFSET_SLOPE_0 0 0xf48 3 0 3 ABM1_ACE_SLOPE_0 0 14 ABM1_ACE_OFFSET_0 16 26 ABM1_ACE_LOCK 31 31 regABM3_DC_ABM1_ACE_OFFSET_SLOPE_1 0 0xf49 3 0 3 ABM1_ACE_SLOPE_1 0 14 ABM1_ACE_OFFSET_1 16 26 ABM1_ACE_LOCK 31 31 regABM3_DC_ABM1_ACE_OFFSET_SLOPE_2 0 0xf4a 3 0 3 ABM1_ACE_SLOPE_2 0 14 ABM1_ACE_OFFSET_2 16 26 ABM1_ACE_LOCK 31 31 regABM3_DC_ABM1_ACE_OFFSET_SLOPE_3 0 0xf4b 3 0 3 ABM1_ACE_SLOPE_3 0 14 ABM1_ACE_OFFSET_3 16 26 ABM1_ACE_LOCK 31 31 regABM3_DC_ABM1_ACE_OFFSET_SLOPE_4 0 0xf4c 3 0 3 ABM1_ACE_SLOPE_4 0 14 ABM1_ACE_OFFSET_4 16 26 ABM1_ACE_LOCK 31 31 regABM3_DC_ABM1_ACE_THRES_12 0 0xf4d 3 0 3 ABM1_ACE_THRES_1 0 9 ABM1_ACE_THRES_2 16 25 ABM1_ACE_LOCK 31 31 regABM3_DC_ABM1_ACE_THRES_34 0 0xf4e 6 0 3 ABM1_ACE_THRES_3 0 9 ABM1_ACE_THRES_4 16 25 ABM1_ACE_IGNORE_MASTER_LOCK_EN 28 28 ABM1_ACE_READBACK_DB_REG_VALUE_EN 29 29 ABM1_ACE_DBUF_REG_UPDATE_PENDING 30 30 ABM1_ACE_LOCK 31 31 regABM3_DC_ABM1_ACE_CNTL_MISC 0 0xf4f 2 0 3 ABM1_ACE_REG_WR_MISSED_FRAME 0 0 ABM1_ACE_REG_WR_MISSED_FRAME_CLEAR 8 8 regABM3_DC_ABM1_HGLS_REG_READ_PROGRESS 0 0xf51 9 0 3 ABM1_HG_REG_READ_IN_PROGRESS 0 0 ABM1_LS_REG_READ_IN_PROGRESS 1 1 ABM1_BL_REG_READ_IN_PROGRESS 2 2 ABM1_HG_REG_READ_MISSED_FRAME 8 8 ABM1_LS_REG_READ_MISSED_FRAME 9 9 ABM1_BL_REG_READ_MISSED_FRAME 10 10 ABM1_HG_REG_READ_MISSED_FRAME_CLEAR 16 16 ABM1_LS_REG_READ_MISSED_FRAME_CLEAR 24 24 ABM1_BL_REG_READ_MISSED_FRAME_CLEAR 31 31 regABM3_DC_ABM1_HG_MISC_CTRL 0 0xf52 11 0 3 ABM1_HG_NUM_OF_BINS_SEL 0 1 ABM1_HG_VMAX_SEL 8 8 ABM1_HG_FINE_MODE_BIN_SEL 12 12 ABM1_HG_BIN_BITWIDTH_SIZE_SEL 16 17 ABM1_OVR_SCAN_PIXEL_PROCESS_EN 20 20 ABM1_DBUF_HGLS_READBACK_DB_REG_VALUE_EN 23 23 ABM1_DBUF_HGLS_REG_FRAME_START_DISP_SEL 24 26 ABM1_DBUF_HGLS_REG_UPDATE_AT_FRAME_START 28 28 ABM1_HGLS_IGNORE_MASTER_LOCK_EN 29 29 ABM1_DBUF_HGLS_REG_UPDATE_PENDING 30 30 ABM1_HGLS_REG_LOCK 31 31 regABM3_DC_ABM1_LS_SUM_OF_LUMA 0 0xf53 1 0 3 ABM1_LS_SUM_OF_LUMA 0 31 regABM3_DC_ABM1_LS_MIN_MAX_LUMA 0 0xf54 2 0 3 ABM1_LS_MIN_LUMA 0 9 ABM1_LS_MAX_LUMA 16 25 regABM3_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA 0 0xf55 2 0 3 ABM1_LS_FILTERED_MIN_LUMA 0 9 ABM1_LS_FILTERED_MAX_LUMA 16 25 regABM3_DC_ABM1_LS_PIXEL_COUNT 0 0xf56 2 0 3 ABM1_LS_PIXEL_COUNT 0 23 ABM1_LS_SUM_OF_LUMA_MSB 24 31 regABM3_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES 0 0xf57 3 0 3 ABM1_LS_MIN_PIXEL_VALUE_THRES 0 9 ABM1_LS_MAX_PIXEL_VALUE_THRES 16 25 ABM1_HGLS_REG_LOCK 31 31 regABM3_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT 0 0xf58 1 0 3 ABM1_LS_MIN_PIXEL_VALUE_COUNT 0 23 regABM3_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT 0 0xf59 1 0 3 ABM1_LS_MAX_PIXEL_VALUE_COUNT 0 23 regABM3_DC_ABM1_HG_SAMPLE_RATE 0 0xf5a 5 0 3 ABM1_HG_SAMPLE_RATE_COUNT_EN 0 0 ABM1_HG_RESET_SAMPLE_RATE_FRAME_COUNTER 1 1 ABM1_HG_SAMPLE_RATE_FRAME_COUNT 8 15 ABM1_HG_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET 16 23 ABM1_HGLS_REG_LOCK 31 31 regABM3_DC_ABM1_LS_SAMPLE_RATE 0 0xf5b 5 0 3 ABM1_LS_SAMPLE_RATE_COUNT_EN 0 0 ABM1_LS_RESET_SAMPLE_RATE_FRAME_COUNTER 1 1 ABM1_LS_SAMPLE_RATE_FRAME_COUNT 8 15 ABM1_LS_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET 16 23 ABM1_HGLS_REG_LOCK 31 31 regABM3_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG 0 0xf5c 1 0 3 ABM1_HG_BIN_1_32_SHIFT_FLAG 0 31 regABM3_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX 0 0xf5d 1 0 3 ABM1_HG_BIN_1_8_SHIFT_INDEX 0 31 regABM3_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX 0 0xf5e 1 0 3 ABM1_HG_BIN_9_16_SHIFT_INDEX 0 31 regABM3_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX 0 0xf5f 1 0 3 ABM1_HG_BIN_17_24_SHIFT_INDEX 0 31 regABM3_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX 0 0xf60 1 0 3 ABM1_HG_BIN_25_32_SHIFT_INDEX 0 31 regABM3_DC_ABM1_HG_RESULT_1 0 0xf61 1 0 3 ABM1_HG_RESULT_1 0 31 regABM3_DC_ABM1_HG_RESULT_2 0 0xf62 1 0 3 ABM1_HG_RESULT_2 0 31 regABM3_DC_ABM1_HG_RESULT_3 0 0xf63 1 0 3 ABM1_HG_RESULT_3 0 31 regABM3_DC_ABM1_HG_RESULT_4 0 0xf64 1 0 3 ABM1_HG_RESULT_4 0 31 regABM3_DC_ABM1_HG_RESULT_5 0 0xf65 1 0 3 ABM1_HG_RESULT_5 0 31 regABM3_DC_ABM1_HG_RESULT_6 0 0xf66 1 0 3 ABM1_HG_RESULT_6 0 31 regABM3_DC_ABM1_HG_RESULT_7 0 0xf67 1 0 3 ABM1_HG_RESULT_7 0 31 regABM3_DC_ABM1_HG_RESULT_8 0 0xf68 1 0 3 ABM1_HG_RESULT_8 0 31 regABM3_DC_ABM1_HG_RESULT_9 0 0xf69 1 0 3 ABM1_HG_RESULT_9 0 31 regABM3_DC_ABM1_HG_RESULT_10 0 0xf6a 1 0 3 ABM1_HG_RESULT_10 0 31 regABM3_DC_ABM1_HG_RESULT_11 0 0xf6b 1 0 3 ABM1_HG_RESULT_11 0 31 regABM3_DC_ABM1_HG_RESULT_12 0 0xf6c 1 0 3 ABM1_HG_RESULT_12 0 31 regABM3_DC_ABM1_HG_RESULT_13 0 0xf6d 1 0 3 ABM1_HG_RESULT_13 0 31 regABM3_DC_ABM1_HG_RESULT_14 0 0xf6e 1 0 3 ABM1_HG_RESULT_14 0 31 regABM3_DC_ABM1_HG_RESULT_15 0 0xf6f 1 0 3 ABM1_HG_RESULT_15 0 31 regABM3_DC_ABM1_HG_RESULT_16 0 0xf70 1 0 3 ABM1_HG_RESULT_16 0 31 regABM3_DC_ABM1_HG_RESULT_17 0 0xf71 1 0 3 ABM1_HG_RESULT_17 0 31 regABM3_DC_ABM1_HG_RESULT_18 0 0xf72 1 0 3 ABM1_HG_RESULT_18 0 31 regABM3_DC_ABM1_HG_RESULT_19 0 0xf73 1 0 3 ABM1_HG_RESULT_19 0 31 regABM3_DC_ABM1_HG_RESULT_20 0 0xf74 1 0 3 ABM1_HG_RESULT_20 0 31 regABM3_DC_ABM1_HG_RESULT_21 0 0xf75 1 0 3 ABM1_HG_RESULT_21 0 31 regABM3_DC_ABM1_HG_RESULT_22 0 0xf76 1 0 3 ABM1_HG_RESULT_22 0 31 regABM3_DC_ABM1_HG_RESULT_23 0 0xf77 1 0 3 ABM1_HG_RESULT_23 0 31 regABM3_DC_ABM1_HG_RESULT_24 0 0xf78 1 0 3 ABM1_HG_RESULT_24 0 31 regABM3_DC_ABM1_BL_MASTER_LOCK 0 0xf79 1 0 3 ABM1_BL_MASTER_LOCK 31 31 regDPG0_DPG_CONTROL 0 0x1854 7 0 2 DPG_EN 0 0 DPG_MODE 4 6 DPG_DYNAMIC_RANGE 8 8 DPG_BIT_DEPTH 12 13 DPG_VRES 16 19 DPG_HRES 20 23 DPG_FIELD_POLARITY 24 24 regDPG0_DPG_RAMP_CONTROL 0 0x1855 3 0 2 DPG_RAMP0_OFFSET 0 15 DPG_INC0 24 27 DPG_INC1 28 31 regDPG0_DPG_DIMENSIONS 0 0x1856 2 0 2 DPG_ACTIVE_HEIGHT 0 13 DPG_ACTIVE_WIDTH 16 29 regDPG0_DPG_COLOUR_R_CR 0 0x1857 2 0 2 DPG_COLOUR0_R_CR 0 15 DPG_COLOUR1_R_CR 16 31 regDPG0_DPG_COLOUR_G_Y 0 0x1858 2 0 2 DPG_COLOUR0_G_Y 0 15 DPG_COLOUR1_G_Y 16 31 regDPG0_DPG_COLOUR_B_CB 0 0x1859 2 0 2 DPG_COLOUR0_B_CB 0 15 DPG_COLOUR1_B_CB 16 31 regDPG0_DPG_OFFSET_SEGMENT 0 0x185a 2 0 2 DPG_X_OFFSET 0 13 DPG_SEGMENT_WIDTH 16 29 regDPG0_DPG_STATUS 0 0x185b 1 0 2 DPG_DOUBLE_BUFFER_PENDING 0 0 regFMT0_FMT_CLAMP_COMPONENT_R 0 0x183c 2 0 2 FMT_CLAMP_LOWER_R 0 15 FMT_CLAMP_UPPER_R 16 31 regFMT0_FMT_CLAMP_COMPONENT_G 0 0x183d 2 0 2 FMT_CLAMP_LOWER_G 0 15 FMT_CLAMP_UPPER_G 16 31 regFMT0_FMT_CLAMP_COMPONENT_B 0 0x183e 2 0 2 FMT_CLAMP_LOWER_B 0 15 FMT_CLAMP_UPPER_B 16 31 regFMT0_FMT_DYNAMIC_EXP_CNTL 0 0x183f 2 0 2 FMT_DYNAMIC_EXP_EN 0 0 FMT_DYNAMIC_EXP_MODE 4 4 regFMT0_FMT_CONTROL 0 0x1840 8 0 2 FMT_STEREOSYNC_OVERRIDE 0 0 FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX 8 11 FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP 12 13 FMT_PIXEL_ENCODING 16 17 FMT_SUBSAMPLING_MODE 18 19 FMT_SUBSAMPLING_ORDER 20 20 FMT_CBCR_BIT_REDUCTION_BYPASS 21 21 FMT_DOUBLE_BUFFER_REG_UPDATE_PENDING 24 24 regFMT0_FMT_BIT_DEPTH_CONTROL 0 0x1841 17 0 2 FMT_TRUNCATE_EN 0 0 FMT_TRUNCATE_MODE 1 1 FMT_TRUNCATE_DEPTH 4 5 FMT_SPATIAL_DITHER_EN 8 8 FMT_SPATIAL_DITHER_MODE 9 10 FMT_SPATIAL_DITHER_DEPTH 11 12 FMT_FRAME_RANDOM_ENABLE 13 13 FMT_RGB_RANDOM_ENABLE 14 14 FMT_HIGHPASS_RANDOM_ENABLE 15 15 FMT_TEMPORAL_DITHER_EN 16 16 FMT_TEMPORAL_DITHER_DEPTH 17 18 FMT_TEMPORAL_DITHER_OFFSET 21 22 FMT_TEMPORAL_LEVEL 24 24 FMT_TEMPORAL_DITHER_RESET 25 25 FMT_25FRC_SEL 26 27 FMT_50FRC_SEL 28 29 FMT_75FRC_SEL 30 31 regFMT0_FMT_DITHER_RAND_R_SEED 0 0x1842 2 0 2 FMT_RAND_R_SEED 0 7 FMT_OFFSET_R_CR 16 31 regFMT0_FMT_DITHER_RAND_G_SEED 0 0x1843 2 0 2 FMT_RAND_G_SEED 0 7 FMT_OFFSET_G_Y 16 31 regFMT0_FMT_DITHER_RAND_B_SEED 0 0x1844 2 0 2 FMT_RAND_B_SEED 0 7 FMT_OFFSET_B_CB 16 31 regFMT0_FMT_CLAMP_CNTL 0 0x1845 2 0 2 FMT_CLAMP_DATA_EN 0 0 FMT_CLAMP_COLOR_FORMAT 16 18 regFMT0_FMT_SIDE_BY_SIDE_STEREO_CONTROL 0 0x1846 1 0 2 FMT_SIDE_BY_SIDE_STEREO_ACTIVE_WIDTH 0 12 regFMT0_FMT_MAP420_MEMORY_CONTROL 0 0x1847 4 0 2 FMT_MAP420MEM_PWR_FORCE 0 1 FMT_MAP420MEM_PWR_DIS 4 4 FMT_MAP420MEM_PWR_STATE 8 9 FMT_DEFAULT_MEM_LOW_POWER_STATE 12 13 regFMT0_FMT_422_CONTROL 0 0x1849 1 0 2 FMT_LEFT_EDGE_EXTRA_PIXEL_COUNT 0 0 regOPPBUF0_OPPBUF_CONTROL 0 0x1884 5 0 2 OPPBUF_ACTIVE_WIDTH 0 13 OPPBUF_DISPLAY_SEGMENTATION 16 18 OPPBUF_OVERLAP_PIXEL_NUM 20 23 OPPBUF_PIXEL_REPETITION 24 27 OPPBUF_DOUBLE_BUFFER_PENDING 28 28 regOPPBUF0_OPPBUF_3D_PARAMETERS_0 0 0x1885 3 0 2 OPPBUF_3D_VACT_SPACE1_SIZE 0 9 OPPBUF_3D_VACT_SPACE2_SIZE 10 19 OPPBUF_DUMMY_DATA_R 20 31 regOPPBUF0_OPPBUF_3D_PARAMETERS_1 0 0x1886 2 0 2 OPPBUF_DUMMY_DATA_G 0 11 OPPBUF_DUMMY_DATA_B 16 27 regOPPBUF0_OPPBUF_CONTROL1 0 0x1889 1 0 2 OPPBUF_NUM_SEGMENT_PADDED_PIXELS 0 2 regOPP_PIPE0_OPP_PIPE_CONTROL 0 0x188c 3 0 2 OPP_PIPE_CLOCK_EN 0 0 OPP_PIPE_CLOCK_ON 1 1 OPP_PIPE_DIGITAL_BYPASS_EN 4 4 regOPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL 0 0x1891 9 0 2 OPP_PIPE_CRC_EN 0 0 OPP_PIPE_CRC_CONT_EN 4 4 OPP_PIPE_CRC_STEREO_MODE 8 9 OPP_PIPE_CRC_STEREO_EN 10 10 OPP_PIPE_CRC_INTERLACE_MODE 12 13 OPP_PIPE_CRC_INTERLACE_EN 14 14 OPP_PIPE_CRC_PIXEL_SELECT 20 21 OPP_PIPE_CRC_SOURCE_SELECT 24 24 OPP_PIPE_CRC_ONE_SHOT_PENDING 28 28 regOPP_PIPE_CRC0_OPP_PIPE_CRC_MASK 0 0x1892 1 0 2 OPP_PIPE_CRC_MASK 0 15 regOPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT0 0 0x1893 2 0 2 OPP_PIPE_CRC_RESULT_A 0 15 OPP_PIPE_CRC_RESULT_R 16 31 regOPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT1 0 0x1894 2 0 2 OPP_PIPE_CRC_RESULT_G 0 15 OPP_PIPE_CRC_RESULT_B 16 31 regOPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT2 0 0x1895 1 0 2 OPP_PIPE_CRC_RESULT_C 0 15 regDPG1_DPG_CONTROL 0 0x18ae 7 0 2 DPG_EN 0 0 DPG_MODE 4 6 DPG_DYNAMIC_RANGE 8 8 DPG_BIT_DEPTH 12 13 DPG_VRES 16 19 DPG_HRES 20 23 DPG_FIELD_POLARITY 24 24 regDPG1_DPG_RAMP_CONTROL 0 0x18af 3 0 2 DPG_RAMP0_OFFSET 0 15 DPG_INC0 24 27 DPG_INC1 28 31 regDPG1_DPG_DIMENSIONS 0 0x18b0 2 0 2 DPG_ACTIVE_HEIGHT 0 13 DPG_ACTIVE_WIDTH 16 29 regDPG1_DPG_COLOUR_R_CR 0 0x18b1 2 0 2 DPG_COLOUR0_R_CR 0 15 DPG_COLOUR1_R_CR 16 31 regDPG1_DPG_COLOUR_G_Y 0 0x18b2 2 0 2 DPG_COLOUR0_G_Y 0 15 DPG_COLOUR1_G_Y 16 31 regDPG1_DPG_COLOUR_B_CB 0 0x18b3 2 0 2 DPG_COLOUR0_B_CB 0 15 DPG_COLOUR1_B_CB 16 31 regDPG1_DPG_OFFSET_SEGMENT 0 0x18b4 2 0 2 DPG_X_OFFSET 0 13 DPG_SEGMENT_WIDTH 16 29 regDPG1_DPG_STATUS 0 0x18b5 1 0 2 DPG_DOUBLE_BUFFER_PENDING 0 0 regFMT1_FMT_CLAMP_COMPONENT_R 0 0x1896 2 0 2 FMT_CLAMP_LOWER_R 0 15 FMT_CLAMP_UPPER_R 16 31 regFMT1_FMT_CLAMP_COMPONENT_G 0 0x1897 2 0 2 FMT_CLAMP_LOWER_G 0 15 FMT_CLAMP_UPPER_G 16 31 regFMT1_FMT_CLAMP_COMPONENT_B 0 0x1898 2 0 2 FMT_CLAMP_LOWER_B 0 15 FMT_CLAMP_UPPER_B 16 31 regFMT1_FMT_DYNAMIC_EXP_CNTL 0 0x1899 2 0 2 FMT_DYNAMIC_EXP_EN 0 0 FMT_DYNAMIC_EXP_MODE 4 4 regFMT1_FMT_CONTROL 0 0x189a 8 0 2 FMT_STEREOSYNC_OVERRIDE 0 0 FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX 8 11 FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP 12 13 FMT_PIXEL_ENCODING 16 17 FMT_SUBSAMPLING_MODE 18 19 FMT_SUBSAMPLING_ORDER 20 20 FMT_CBCR_BIT_REDUCTION_BYPASS 21 21 FMT_DOUBLE_BUFFER_REG_UPDATE_PENDING 24 24 regFMT1_FMT_BIT_DEPTH_CONTROL 0 0x189b 17 0 2 FMT_TRUNCATE_EN 0 0 FMT_TRUNCATE_MODE 1 1 FMT_TRUNCATE_DEPTH 4 5 FMT_SPATIAL_DITHER_EN 8 8 FMT_SPATIAL_DITHER_MODE 9 10 FMT_SPATIAL_DITHER_DEPTH 11 12 FMT_FRAME_RANDOM_ENABLE 13 13 FMT_RGB_RANDOM_ENABLE 14 14 FMT_HIGHPASS_RANDOM_ENABLE 15 15 FMT_TEMPORAL_DITHER_EN 16 16 FMT_TEMPORAL_DITHER_DEPTH 17 18 FMT_TEMPORAL_DITHER_OFFSET 21 22 FMT_TEMPORAL_LEVEL 24 24 FMT_TEMPORAL_DITHER_RESET 25 25 FMT_25FRC_SEL 26 27 FMT_50FRC_SEL 28 29 FMT_75FRC_SEL 30 31 regFMT1_FMT_DITHER_RAND_R_SEED 0 0x189c 2 0 2 FMT_RAND_R_SEED 0 7 FMT_OFFSET_R_CR 16 31 regFMT1_FMT_DITHER_RAND_G_SEED 0 0x189d 2 0 2 FMT_RAND_G_SEED 0 7 FMT_OFFSET_G_Y 16 31 regFMT1_FMT_DITHER_RAND_B_SEED 0 0x189e 2 0 2 FMT_RAND_B_SEED 0 7 FMT_OFFSET_B_CB 16 31 regFMT1_FMT_CLAMP_CNTL 0 0x189f 2 0 2 FMT_CLAMP_DATA_EN 0 0 FMT_CLAMP_COLOR_FORMAT 16 18 regFMT1_FMT_SIDE_BY_SIDE_STEREO_CONTROL 0 0x18a0 1 0 2 FMT_SIDE_BY_SIDE_STEREO_ACTIVE_WIDTH 0 12 regFMT1_FMT_MAP420_MEMORY_CONTROL 0 0x18a1 4 0 2 FMT_MAP420MEM_PWR_FORCE 0 1 FMT_MAP420MEM_PWR_DIS 4 4 FMT_MAP420MEM_PWR_STATE 8 9 FMT_DEFAULT_MEM_LOW_POWER_STATE 12 13 regFMT1_FMT_422_CONTROL 0 0x18a3 1 0 2 FMT_LEFT_EDGE_EXTRA_PIXEL_COUNT 0 0 regOPPBUF1_OPPBUF_CONTROL 0 0x18de 5 0 2 OPPBUF_ACTIVE_WIDTH 0 13 OPPBUF_DISPLAY_SEGMENTATION 16 18 OPPBUF_OVERLAP_PIXEL_NUM 20 23 OPPBUF_PIXEL_REPETITION 24 27 OPPBUF_DOUBLE_BUFFER_PENDING 28 28 regOPPBUF1_OPPBUF_3D_PARAMETERS_0 0 0x18df 3 0 2 OPPBUF_3D_VACT_SPACE1_SIZE 0 9 OPPBUF_3D_VACT_SPACE2_SIZE 10 19 OPPBUF_DUMMY_DATA_R 20 31 regOPPBUF1_OPPBUF_3D_PARAMETERS_1 0 0x18e0 2 0 2 OPPBUF_DUMMY_DATA_G 0 11 OPPBUF_DUMMY_DATA_B 16 27 regOPPBUF1_OPPBUF_CONTROL1 0 0x18e3 1 0 2 OPPBUF_NUM_SEGMENT_PADDED_PIXELS 0 2 regOPP_PIPE1_OPP_PIPE_CONTROL 0 0x18e6 3 0 2 OPP_PIPE_CLOCK_EN 0 0 OPP_PIPE_CLOCK_ON 1 1 OPP_PIPE_DIGITAL_BYPASS_EN 4 4 regOPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL 0 0x18eb 9 0 2 OPP_PIPE_CRC_EN 0 0 OPP_PIPE_CRC_CONT_EN 4 4 OPP_PIPE_CRC_STEREO_MODE 8 9 OPP_PIPE_CRC_STEREO_EN 10 10 OPP_PIPE_CRC_INTERLACE_MODE 12 13 OPP_PIPE_CRC_INTERLACE_EN 14 14 OPP_PIPE_CRC_PIXEL_SELECT 20 21 OPP_PIPE_CRC_SOURCE_SELECT 24 24 OPP_PIPE_CRC_ONE_SHOT_PENDING 28 28 regOPP_PIPE_CRC1_OPP_PIPE_CRC_MASK 0 0x18ec 1 0 2 OPP_PIPE_CRC_MASK 0 15 regOPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT0 0 0x18ed 2 0 2 OPP_PIPE_CRC_RESULT_A 0 15 OPP_PIPE_CRC_RESULT_R 16 31 regOPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT1 0 0x18ee 2 0 2 OPP_PIPE_CRC_RESULT_G 0 15 OPP_PIPE_CRC_RESULT_B 16 31 regOPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT2 0 0x18ef 1 0 2 OPP_PIPE_CRC_RESULT_C 0 15 regDPG2_DPG_CONTROL 0 0x1908 7 0 2 DPG_EN 0 0 DPG_MODE 4 6 DPG_DYNAMIC_RANGE 8 8 DPG_BIT_DEPTH 12 13 DPG_VRES 16 19 DPG_HRES 20 23 DPG_FIELD_POLARITY 24 24 regDPG2_DPG_RAMP_CONTROL 0 0x1909 3 0 2 DPG_RAMP0_OFFSET 0 15 DPG_INC0 24 27 DPG_INC1 28 31 regDPG2_DPG_DIMENSIONS 0 0x190a 2 0 2 DPG_ACTIVE_HEIGHT 0 13 DPG_ACTIVE_WIDTH 16 29 regDPG2_DPG_COLOUR_R_CR 0 0x190b 2 0 2 DPG_COLOUR0_R_CR 0 15 DPG_COLOUR1_R_CR 16 31 regDPG2_DPG_COLOUR_G_Y 0 0x190c 2 0 2 DPG_COLOUR0_G_Y 0 15 DPG_COLOUR1_G_Y 16 31 regDPG2_DPG_COLOUR_B_CB 0 0x190d 2 0 2 DPG_COLOUR0_B_CB 0 15 DPG_COLOUR1_B_CB 16 31 regDPG2_DPG_OFFSET_SEGMENT 0 0x190e 2 0 2 DPG_X_OFFSET 0 13 DPG_SEGMENT_WIDTH 16 29 regDPG2_DPG_STATUS 0 0x190f 1 0 2 DPG_DOUBLE_BUFFER_PENDING 0 0 regFMT2_FMT_CLAMP_COMPONENT_R 0 0x18f0 2 0 2 FMT_CLAMP_LOWER_R 0 15 FMT_CLAMP_UPPER_R 16 31 regFMT2_FMT_CLAMP_COMPONENT_G 0 0x18f1 2 0 2 FMT_CLAMP_LOWER_G 0 15 FMT_CLAMP_UPPER_G 16 31 regFMT2_FMT_CLAMP_COMPONENT_B 0 0x18f2 2 0 2 FMT_CLAMP_LOWER_B 0 15 FMT_CLAMP_UPPER_B 16 31 regFMT2_FMT_DYNAMIC_EXP_CNTL 0 0x18f3 2 0 2 FMT_DYNAMIC_EXP_EN 0 0 FMT_DYNAMIC_EXP_MODE 4 4 regFMT2_FMT_CONTROL 0 0x18f4 8 0 2 FMT_STEREOSYNC_OVERRIDE 0 0 FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX 8 11 FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP 12 13 FMT_PIXEL_ENCODING 16 17 FMT_SUBSAMPLING_MODE 18 19 FMT_SUBSAMPLING_ORDER 20 20 FMT_CBCR_BIT_REDUCTION_BYPASS 21 21 FMT_DOUBLE_BUFFER_REG_UPDATE_PENDING 24 24 regFMT2_FMT_BIT_DEPTH_CONTROL 0 0x18f5 17 0 2 FMT_TRUNCATE_EN 0 0 FMT_TRUNCATE_MODE 1 1 FMT_TRUNCATE_DEPTH 4 5 FMT_SPATIAL_DITHER_EN 8 8 FMT_SPATIAL_DITHER_MODE 9 10 FMT_SPATIAL_DITHER_DEPTH 11 12 FMT_FRAME_RANDOM_ENABLE 13 13 FMT_RGB_RANDOM_ENABLE 14 14 FMT_HIGHPASS_RANDOM_ENABLE 15 15 FMT_TEMPORAL_DITHER_EN 16 16 FMT_TEMPORAL_DITHER_DEPTH 17 18 FMT_TEMPORAL_DITHER_OFFSET 21 22 FMT_TEMPORAL_LEVEL 24 24 FMT_TEMPORAL_DITHER_RESET 25 25 FMT_25FRC_SEL 26 27 FMT_50FRC_SEL 28 29 FMT_75FRC_SEL 30 31 regFMT2_FMT_DITHER_RAND_R_SEED 0 0x18f6 2 0 2 FMT_RAND_R_SEED 0 7 FMT_OFFSET_R_CR 16 31 regFMT2_FMT_DITHER_RAND_G_SEED 0 0x18f7 2 0 2 FMT_RAND_G_SEED 0 7 FMT_OFFSET_G_Y 16 31 regFMT2_FMT_DITHER_RAND_B_SEED 0 0x18f8 2 0 2 FMT_RAND_B_SEED 0 7 FMT_OFFSET_B_CB 16 31 regFMT2_FMT_CLAMP_CNTL 0 0x18f9 2 0 2 FMT_CLAMP_DATA_EN 0 0 FMT_CLAMP_COLOR_FORMAT 16 18 regFMT2_FMT_SIDE_BY_SIDE_STEREO_CONTROL 0 0x18fa 1 0 2 FMT_SIDE_BY_SIDE_STEREO_ACTIVE_WIDTH 0 12 regFMT2_FMT_MAP420_MEMORY_CONTROL 0 0x18fb 4 0 2 FMT_MAP420MEM_PWR_FORCE 0 1 FMT_MAP420MEM_PWR_DIS 4 4 FMT_MAP420MEM_PWR_STATE 8 9 FMT_DEFAULT_MEM_LOW_POWER_STATE 12 13 regFMT2_FMT_422_CONTROL 0 0x18fd 1 0 2 FMT_LEFT_EDGE_EXTRA_PIXEL_COUNT 0 0 regOPPBUF2_OPPBUF_CONTROL 0 0x1938 5 0 2 OPPBUF_ACTIVE_WIDTH 0 13 OPPBUF_DISPLAY_SEGMENTATION 16 18 OPPBUF_OVERLAP_PIXEL_NUM 20 23 OPPBUF_PIXEL_REPETITION 24 27 OPPBUF_DOUBLE_BUFFER_PENDING 28 28 regOPPBUF2_OPPBUF_3D_PARAMETERS_0 0 0x1939 3 0 2 OPPBUF_3D_VACT_SPACE1_SIZE 0 9 OPPBUF_3D_VACT_SPACE2_SIZE 10 19 OPPBUF_DUMMY_DATA_R 20 31 regOPPBUF2_OPPBUF_3D_PARAMETERS_1 0 0x193a 2 0 2 OPPBUF_DUMMY_DATA_G 0 11 OPPBUF_DUMMY_DATA_B 16 27 regOPPBUF2_OPPBUF_CONTROL1 0 0x193d 1 0 2 OPPBUF_NUM_SEGMENT_PADDED_PIXELS 0 2 regOPP_PIPE2_OPP_PIPE_CONTROL 0 0x1940 3 0 2 OPP_PIPE_CLOCK_EN 0 0 OPP_PIPE_CLOCK_ON 1 1 OPP_PIPE_DIGITAL_BYPASS_EN 4 4 regOPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL 0 0x1945 9 0 2 OPP_PIPE_CRC_EN 0 0 OPP_PIPE_CRC_CONT_EN 4 4 OPP_PIPE_CRC_STEREO_MODE 8 9 OPP_PIPE_CRC_STEREO_EN 10 10 OPP_PIPE_CRC_INTERLACE_MODE 12 13 OPP_PIPE_CRC_INTERLACE_EN 14 14 OPP_PIPE_CRC_PIXEL_SELECT 20 21 OPP_PIPE_CRC_SOURCE_SELECT 24 24 OPP_PIPE_CRC_ONE_SHOT_PENDING 28 28 regOPP_PIPE_CRC2_OPP_PIPE_CRC_MASK 0 0x1946 1 0 2 OPP_PIPE_CRC_MASK 0 15 regOPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT0 0 0x1947 2 0 2 OPP_PIPE_CRC_RESULT_A 0 15 OPP_PIPE_CRC_RESULT_R 16 31 regOPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT1 0 0x1948 2 0 2 OPP_PIPE_CRC_RESULT_G 0 15 OPP_PIPE_CRC_RESULT_B 16 31 regOPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT2 0 0x1949 1 0 2 OPP_PIPE_CRC_RESULT_C 0 15 regDPG3_DPG_CONTROL 0 0x1962 7 0 2 DPG_EN 0 0 DPG_MODE 4 6 DPG_DYNAMIC_RANGE 8 8 DPG_BIT_DEPTH 12 13 DPG_VRES 16 19 DPG_HRES 20 23 DPG_FIELD_POLARITY 24 24 regDPG3_DPG_RAMP_CONTROL 0 0x1963 3 0 2 DPG_RAMP0_OFFSET 0 15 DPG_INC0 24 27 DPG_INC1 28 31 regDPG3_DPG_DIMENSIONS 0 0x1964 2 0 2 DPG_ACTIVE_HEIGHT 0 13 DPG_ACTIVE_WIDTH 16 29 regDPG3_DPG_COLOUR_R_CR 0 0x1965 2 0 2 DPG_COLOUR0_R_CR 0 15 DPG_COLOUR1_R_CR 16 31 regDPG3_DPG_COLOUR_G_Y 0 0x1966 2 0 2 DPG_COLOUR0_G_Y 0 15 DPG_COLOUR1_G_Y 16 31 regDPG3_DPG_COLOUR_B_CB 0 0x1967 2 0 2 DPG_COLOUR0_B_CB 0 15 DPG_COLOUR1_B_CB 16 31 regDPG3_DPG_OFFSET_SEGMENT 0 0x1968 2 0 2 DPG_X_OFFSET 0 13 DPG_SEGMENT_WIDTH 16 29 regDPG3_DPG_STATUS 0 0x1969 1 0 2 DPG_DOUBLE_BUFFER_PENDING 0 0 regFMT3_FMT_CLAMP_COMPONENT_R 0 0x194a 2 0 2 FMT_CLAMP_LOWER_R 0 15 FMT_CLAMP_UPPER_R 16 31 regFMT3_FMT_CLAMP_COMPONENT_G 0 0x194b 2 0 2 FMT_CLAMP_LOWER_G 0 15 FMT_CLAMP_UPPER_G 16 31 regFMT3_FMT_CLAMP_COMPONENT_B 0 0x194c 2 0 2 FMT_CLAMP_LOWER_B 0 15 FMT_CLAMP_UPPER_B 16 31 regFMT3_FMT_DYNAMIC_EXP_CNTL 0 0x194d 2 0 2 FMT_DYNAMIC_EXP_EN 0 0 FMT_DYNAMIC_EXP_MODE 4 4 regFMT3_FMT_CONTROL 0 0x194e 8 0 2 FMT_STEREOSYNC_OVERRIDE 0 0 FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX 8 11 FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP 12 13 FMT_PIXEL_ENCODING 16 17 FMT_SUBSAMPLING_MODE 18 19 FMT_SUBSAMPLING_ORDER 20 20 FMT_CBCR_BIT_REDUCTION_BYPASS 21 21 FMT_DOUBLE_BUFFER_REG_UPDATE_PENDING 24 24 regFMT3_FMT_BIT_DEPTH_CONTROL 0 0x194f 17 0 2 FMT_TRUNCATE_EN 0 0 FMT_TRUNCATE_MODE 1 1 FMT_TRUNCATE_DEPTH 4 5 FMT_SPATIAL_DITHER_EN 8 8 FMT_SPATIAL_DITHER_MODE 9 10 FMT_SPATIAL_DITHER_DEPTH 11 12 FMT_FRAME_RANDOM_ENABLE 13 13 FMT_RGB_RANDOM_ENABLE 14 14 FMT_HIGHPASS_RANDOM_ENABLE 15 15 FMT_TEMPORAL_DITHER_EN 16 16 FMT_TEMPORAL_DITHER_DEPTH 17 18 FMT_TEMPORAL_DITHER_OFFSET 21 22 FMT_TEMPORAL_LEVEL 24 24 FMT_TEMPORAL_DITHER_RESET 25 25 FMT_25FRC_SEL 26 27 FMT_50FRC_SEL 28 29 FMT_75FRC_SEL 30 31 regFMT3_FMT_DITHER_RAND_R_SEED 0 0x1950 2 0 2 FMT_RAND_R_SEED 0 7 FMT_OFFSET_R_CR 16 31 regFMT3_FMT_DITHER_RAND_G_SEED 0 0x1951 2 0 2 FMT_RAND_G_SEED 0 7 FMT_OFFSET_G_Y 16 31 regFMT3_FMT_DITHER_RAND_B_SEED 0 0x1952 2 0 2 FMT_RAND_B_SEED 0 7 FMT_OFFSET_B_CB 16 31 regFMT3_FMT_CLAMP_CNTL 0 0x1953 2 0 2 FMT_CLAMP_DATA_EN 0 0 FMT_CLAMP_COLOR_FORMAT 16 18 regFMT3_FMT_SIDE_BY_SIDE_STEREO_CONTROL 0 0x1954 1 0 2 FMT_SIDE_BY_SIDE_STEREO_ACTIVE_WIDTH 0 12 regFMT3_FMT_MAP420_MEMORY_CONTROL 0 0x1955 4 0 2 FMT_MAP420MEM_PWR_FORCE 0 1 FMT_MAP420MEM_PWR_DIS 4 4 FMT_MAP420MEM_PWR_STATE 8 9 FMT_DEFAULT_MEM_LOW_POWER_STATE 12 13 regFMT3_FMT_422_CONTROL 0 0x1957 1 0 2 FMT_LEFT_EDGE_EXTRA_PIXEL_COUNT 0 0 regOPPBUF3_OPPBUF_CONTROL 0 0x1992 5 0 2 OPPBUF_ACTIVE_WIDTH 0 13 OPPBUF_DISPLAY_SEGMENTATION 16 18 OPPBUF_OVERLAP_PIXEL_NUM 20 23 OPPBUF_PIXEL_REPETITION 24 27 OPPBUF_DOUBLE_BUFFER_PENDING 28 28 regOPPBUF3_OPPBUF_3D_PARAMETERS_0 0 0x1993 3 0 2 OPPBUF_3D_VACT_SPACE1_SIZE 0 9 OPPBUF_3D_VACT_SPACE2_SIZE 10 19 OPPBUF_DUMMY_DATA_R 20 31 regOPPBUF3_OPPBUF_3D_PARAMETERS_1 0 0x1994 2 0 2 OPPBUF_DUMMY_DATA_G 0 11 OPPBUF_DUMMY_DATA_B 16 27 regOPPBUF3_OPPBUF_CONTROL1 0 0x1997 1 0 2 OPPBUF_NUM_SEGMENT_PADDED_PIXELS 0 2 regOPP_PIPE3_OPP_PIPE_CONTROL 0 0x199a 3 0 2 OPP_PIPE_CLOCK_EN 0 0 OPP_PIPE_CLOCK_ON 1 1 OPP_PIPE_DIGITAL_BYPASS_EN 4 4 regOPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL 0 0x199f 9 0 2 OPP_PIPE_CRC_EN 0 0 OPP_PIPE_CRC_CONT_EN 4 4 OPP_PIPE_CRC_STEREO_MODE 8 9 OPP_PIPE_CRC_STEREO_EN 10 10 OPP_PIPE_CRC_INTERLACE_MODE 12 13 OPP_PIPE_CRC_INTERLACE_EN 14 14 OPP_PIPE_CRC_PIXEL_SELECT 20 21 OPP_PIPE_CRC_SOURCE_SELECT 24 24 OPP_PIPE_CRC_ONE_SHOT_PENDING 28 28 regOPP_PIPE_CRC3_OPP_PIPE_CRC_MASK 0 0x19a0 1 0 2 OPP_PIPE_CRC_MASK 0 15 regOPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT0 0 0x19a1 2 0 2 OPP_PIPE_CRC_RESULT_A 0 15 OPP_PIPE_CRC_RESULT_R 16 31 regOPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT1 0 0x19a2 2 0 2 OPP_PIPE_CRC_RESULT_G 0 15 OPP_PIPE_CRC_RESULT_B 16 31 regOPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT2 0 0x19a3 1 0 2 OPP_PIPE_CRC_RESULT_C 0 15 regDSCRM0_DSCRM_DSC_FORWARD_CONFIG 0 0x1a64 4 0 2 DSCRM_DSC_FORWARD_EN 0 0 DSCRM_DSC_OPP_PIPE_SOURCE 4 6 DSCRM_DSC_DOUBLE_BUFFER_REG_UPDATE_PENDING 8 8 DSCRM_DSC_FORWARD_EN_STATUS 12 12 regDSCRM1_DSCRM_DSC_FORWARD_CONFIG 0 0x1a65 4 0 2 DSCRM_DSC_FORWARD_EN 0 0 DSCRM_DSC_OPP_PIPE_SOURCE 4 6 DSCRM_DSC_DOUBLE_BUFFER_REG_UPDATE_PENDING 8 8 DSCRM_DSC_FORWARD_EN_STATUS 12 12 regDSCRM2_DSCRM_DSC_FORWARD_CONFIG 0 0x1a66 4 0 2 DSCRM_DSC_FORWARD_EN 0 0 DSCRM_DSC_OPP_PIPE_SOURCE 4 6 DSCRM_DSC_DOUBLE_BUFFER_REG_UPDATE_PENDING 8 8 DSCRM_DSC_FORWARD_EN_STATUS 12 12 regOPP_TOP_CLK_CONTROL 0 0x1a5e 7 0 2 OPP_DISPCLK_R_GATE_DIS 0 0 OPP_DISPCLK_G_ABM_GATE_DIS 4 4 OPP_TEST_CLK_SEL 8 11 OPP_ABM0_CLOCK_ON 12 12 OPP_ABM1_CLOCK_ON 13 13 OPP_ABM2_CLOCK_ON 14 14 OPP_ABM3_CLOCK_ON 15 15 regOPP_ABM_CONTROL 0 0x1a60 1 0 2 OPP_ABM_BLPWM_SEL 0 2 regDC_PERFMON16_PERFCOUNTER_CNTL 0 0x1abe 11 0 2 PERFCOUNTER_EVENT_SEL 0 8 PERFCOUNTER_CVALUE_SEL 9 11 PERFCOUNTER_INC_MODE 12 14 PERFCOUNTER_HW_CNTL_SEL 15 15 PERFCOUNTER_RUNEN_MODE 16 16 PERFCOUNTER_CNTOFF_START_DIS 22 22 PERFCOUNTER_RESTART_EN 23 23 PERFCOUNTER_INT_EN 24 24 PERFCOUNTER_OFF_MASK 25 25 PERFCOUNTER_ACTIVE 26 26 PERFCOUNTER_CNTL_SEL 29 31 regDC_PERFMON16_PERFCOUNTER_CNTL2 0 0x1abf 5 0 2 PERFCOUNTER_COUNTED_VALUE_TYPE 0 1 PERFCOUNTER_HW_STOP1_SEL 2 2 PERFCOUNTER_HW_STOP2_SEL 3 3 PERFCOUNTER_CNTOFF_SEL 8 13 PERFCOUNTER_CNTL2_SEL 29 31 regDC_PERFMON16_PERFCOUNTER_STATE 0 0x1ac0 16 0 2 PERFCOUNTER_CNT0_STATE 0 1 PERFCOUNTER_STATE_SEL0 2 2 PERFCOUNTER_CNT1_STATE 4 5 PERFCOUNTER_STATE_SEL1 6 6 PERFCOUNTER_CNT2_STATE 8 9 PERFCOUNTER_STATE_SEL2 10 10 PERFCOUNTER_CNT3_STATE 12 13 PERFCOUNTER_STATE_SEL3 14 14 PERFCOUNTER_CNT4_STATE 16 17 PERFCOUNTER_STATE_SEL4 18 18 PERFCOUNTER_CNT5_STATE 20 21 PERFCOUNTER_STATE_SEL5 22 22 PERFCOUNTER_CNT6_STATE 24 25 PERFCOUNTER_STATE_SEL6 26 26 PERFCOUNTER_CNT7_STATE 28 29 PERFCOUNTER_STATE_SEL7 30 30 regDC_PERFMON16_PERFMON_CNTL 0 0x1ac1 6 0 2 PERFMON_STATE 0 1 PERFMON_RPT_COUNT 8 27 PERFMON_CNTOFF_AND_OR 28 28 PERFMON_CNTOFF_INT_EN 29 29 PERFMON_CNTOFF_INT_STATUS 30 30 PERFMON_CNTOFF_INT_ACK 31 31 regDC_PERFMON16_PERFMON_CNTL2 0 0x1ac2 4 0 2 PERFMON_CNTOFF_INT_TYPE 0 0 PERFMON_CLK_ENABLE 1 1 PERFMON_RUN_ENABLE_START_SEL 2 9 PERFMON_RUN_ENABLE_STOP_SEL 10 17 regDC_PERFMON16_PERFMON_CVALUE_INT_MISC 0 0x1ac3 17 0 2 PERFCOUNTER_INT0_STATUS 0 0 PERFCOUNTER_INT1_STATUS 1 1 PERFCOUNTER_INT2_STATUS 2 2 PERFCOUNTER_INT3_STATUS 3 3 PERFCOUNTER_INT4_STATUS 4 4 PERFCOUNTER_INT5_STATUS 5 5 PERFCOUNTER_INT6_STATUS 6 6 PERFCOUNTER_INT7_STATUS 7 7 PERFCOUNTER_INT0_ACK 8 8 PERFCOUNTER_INT1_ACK 9 9 PERFCOUNTER_INT2_ACK 10 10 PERFCOUNTER_INT3_ACK 11 11 PERFCOUNTER_INT4_ACK 12 12 PERFCOUNTER_INT5_ACK 13 13 PERFCOUNTER_INT6_ACK 14 14 PERFCOUNTER_INT7_ACK 15 15 PERFMON_CVALUE_HI 16 31 regDC_PERFMON16_PERFMON_CVALUE_LOW 0 0x1ac4 1 0 2 PERFMON_CVALUE_LOW 0 31 regDC_PERFMON16_PERFMON_HI 0 0x1ac5 2 0 2 PERFMON_HI 0 15 PERFMON_READ_SEL 29 31 regDC_PERFMON16_PERFMON_LOW 0 0x1ac6 1 0 2 PERFMON_LOW 0 31 regODM0_OPTC_INPUT_GLOBAL_CONTROL 0 0x1aca 8 0 2 OPTC_INPUT_SOFT_RESET 0 0 OPTC_UNDERFLOW_INT_EN 8 8 OPTC_UNDERFLOW_INT_TYPE 9 9 OPTC_UNDERFLOW_OCCURRED_STATUS 10 10 OPTC_UNDERFLOW_INT_STATUS 11 11 OPTC_UNDERFLOW_CLEAR 12 12 OPTC_UNDERFLOW_OCCURRED_CURRENT 13 13 OPTC_DOUBLE_BUFFER_PENDING 31 31 regODM0_OPTC_DATA_SOURCE_SELECT 0 0x1acb 6 0 2 OPTC_NUM_OF_INPUT_SEGMENT 0 1 OPTC_NUM_OF_OUTPUT_SEGMENT 8 9 OPTC_SEG0_SRC_SEL 16 19 OPTC_SEG1_SRC_SEL 20 23 OPTC_SEG2_SRC_SEL 24 27 OPTC_SEG3_SRC_SEL 28 31 regODM0_OPTC_DATA_FORMAT_CONTROL 0 0x1acc 2 0 2 OPTC_DATA_FORMAT 0 1 OPTC_DSC_MODE 4 5 regODM0_OPTC_BYTES_PER_PIXEL 0 0x1acd 1 0 2 OPTC_DSC_BYTES_PER_PIXEL 0 30 regODM0_OPTC_WIDTH_CONTROL 0 0x1ace 2 0 2 OPTC_SEGMENT_WIDTH 0 12 OPTC_DSC_SLICE_WIDTH 16 28 regODM0_OPTC_INPUT_CLOCK_CONTROL 0 0x1acf 3 0 2 OPTC_INPUT_CLK_GATE_DIS 0 0 OPTC_INPUT_CLK_EN 1 1 OPTC_INPUT_CLK_ON 2 2 regODM0_OPTC_MEMORY_CONFIG 0 0x1ad0 2 0 2 OPTC_MEM_SEL 0 15 OPTC_MEM_SEL_STATUS 16 31 regODM0_OPTC_INPUT_SPARE_REGISTER 0 0x1ad1 1 0 2 OPTC_INPUT_SPARE_REG 0 31 regODM1_OPTC_INPUT_GLOBAL_CONTROL 0 0x1ada 8 0 2 OPTC_INPUT_SOFT_RESET 0 0 OPTC_UNDERFLOW_INT_EN 8 8 OPTC_UNDERFLOW_INT_TYPE 9 9 OPTC_UNDERFLOW_OCCURRED_STATUS 10 10 OPTC_UNDERFLOW_INT_STATUS 11 11 OPTC_UNDERFLOW_CLEAR 12 12 OPTC_UNDERFLOW_OCCURRED_CURRENT 13 13 OPTC_DOUBLE_BUFFER_PENDING 31 31 regODM1_OPTC_DATA_SOURCE_SELECT 0 0x1adb 6 0 2 OPTC_NUM_OF_INPUT_SEGMENT 0 1 OPTC_NUM_OF_OUTPUT_SEGMENT 8 9 OPTC_SEG0_SRC_SEL 16 19 OPTC_SEG1_SRC_SEL 20 23 OPTC_SEG2_SRC_SEL 24 27 OPTC_SEG3_SRC_SEL 28 31 regODM1_OPTC_DATA_FORMAT_CONTROL 0 0x1adc 2 0 2 OPTC_DATA_FORMAT 0 1 OPTC_DSC_MODE 4 5 regODM1_OPTC_BYTES_PER_PIXEL 0 0x1add 1 0 2 OPTC_DSC_BYTES_PER_PIXEL 0 30 regODM1_OPTC_WIDTH_CONTROL 0 0x1ade 2 0 2 OPTC_SEGMENT_WIDTH 0 12 OPTC_DSC_SLICE_WIDTH 16 28 regODM1_OPTC_INPUT_CLOCK_CONTROL 0 0x1adf 3 0 2 OPTC_INPUT_CLK_GATE_DIS 0 0 OPTC_INPUT_CLK_EN 1 1 OPTC_INPUT_CLK_ON 2 2 regODM1_OPTC_MEMORY_CONFIG 0 0x1ae0 2 0 2 OPTC_MEM_SEL 0 15 OPTC_MEM_SEL_STATUS 16 31 regODM1_OPTC_INPUT_SPARE_REGISTER 0 0x1ae1 1 0 2 OPTC_INPUT_SPARE_REG 0 31 regODM2_OPTC_INPUT_GLOBAL_CONTROL 0 0x1aea 8 0 2 OPTC_INPUT_SOFT_RESET 0 0 OPTC_UNDERFLOW_INT_EN 8 8 OPTC_UNDERFLOW_INT_TYPE 9 9 OPTC_UNDERFLOW_OCCURRED_STATUS 10 10 OPTC_UNDERFLOW_INT_STATUS 11 11 OPTC_UNDERFLOW_CLEAR 12 12 OPTC_UNDERFLOW_OCCURRED_CURRENT 13 13 OPTC_DOUBLE_BUFFER_PENDING 31 31 regODM2_OPTC_DATA_SOURCE_SELECT 0 0x1aeb 6 0 2 OPTC_NUM_OF_INPUT_SEGMENT 0 1 OPTC_NUM_OF_OUTPUT_SEGMENT 8 9 OPTC_SEG0_SRC_SEL 16 19 OPTC_SEG1_SRC_SEL 20 23 OPTC_SEG2_SRC_SEL 24 27 OPTC_SEG3_SRC_SEL 28 31 regODM2_OPTC_DATA_FORMAT_CONTROL 0 0x1aec 2 0 2 OPTC_DATA_FORMAT 0 1 OPTC_DSC_MODE 4 5 regODM2_OPTC_BYTES_PER_PIXEL 0 0x1aed 1 0 2 OPTC_DSC_BYTES_PER_PIXEL 0 30 regODM2_OPTC_WIDTH_CONTROL 0 0x1aee 2 0 2 OPTC_SEGMENT_WIDTH 0 12 OPTC_DSC_SLICE_WIDTH 16 28 regODM2_OPTC_INPUT_CLOCK_CONTROL 0 0x1aef 3 0 2 OPTC_INPUT_CLK_GATE_DIS 0 0 OPTC_INPUT_CLK_EN 1 1 OPTC_INPUT_CLK_ON 2 2 regODM2_OPTC_MEMORY_CONFIG 0 0x1af0 2 0 2 OPTC_MEM_SEL 0 15 OPTC_MEM_SEL_STATUS 16 31 regODM2_OPTC_INPUT_SPARE_REGISTER 0 0x1af1 1 0 2 OPTC_INPUT_SPARE_REG 0 31 regODM3_OPTC_INPUT_GLOBAL_CONTROL 0 0x1afa 8 0 2 OPTC_INPUT_SOFT_RESET 0 0 OPTC_UNDERFLOW_INT_EN 8 8 OPTC_UNDERFLOW_INT_TYPE 9 9 OPTC_UNDERFLOW_OCCURRED_STATUS 10 10 OPTC_UNDERFLOW_INT_STATUS 11 11 OPTC_UNDERFLOW_CLEAR 12 12 OPTC_UNDERFLOW_OCCURRED_CURRENT 13 13 OPTC_DOUBLE_BUFFER_PENDING 31 31 regODM3_OPTC_DATA_SOURCE_SELECT 0 0x1afb 6 0 2 OPTC_NUM_OF_INPUT_SEGMENT 0 1 OPTC_NUM_OF_OUTPUT_SEGMENT 8 9 OPTC_SEG0_SRC_SEL 16 19 OPTC_SEG1_SRC_SEL 20 23 OPTC_SEG2_SRC_SEL 24 27 OPTC_SEG3_SRC_SEL 28 31 regODM3_OPTC_DATA_FORMAT_CONTROL 0 0x1afc 2 0 2 OPTC_DATA_FORMAT 0 1 OPTC_DSC_MODE 4 5 regODM3_OPTC_BYTES_PER_PIXEL 0 0x1afd 1 0 2 OPTC_DSC_BYTES_PER_PIXEL 0 30 regODM3_OPTC_WIDTH_CONTROL 0 0x1afe 2 0 2 OPTC_SEGMENT_WIDTH 0 12 OPTC_DSC_SLICE_WIDTH 16 28 regODM3_OPTC_INPUT_CLOCK_CONTROL 0 0x1aff 3 0 2 OPTC_INPUT_CLK_GATE_DIS 0 0 OPTC_INPUT_CLK_EN 1 1 OPTC_INPUT_CLK_ON 2 2 regODM3_OPTC_MEMORY_CONFIG 0 0x1b00 2 0 2 OPTC_MEM_SEL 0 15 OPTC_MEM_SEL_STATUS 16 31 regODM3_OPTC_INPUT_SPARE_REGISTER 0 0x1b01 1 0 2 OPTC_INPUT_SPARE_REG 0 31 regOTG0_OTG_H_TOTAL 0 0x1b2a 1 0 2 OTG_H_TOTAL 0 14 regOTG0_OTG_H_BLANK_START_END 0 0x1b2b 2 0 2 OTG_H_BLANK_START 0 14 OTG_H_BLANK_END 16 30 regOTG0_OTG_H_SYNC_A 0 0x1b2c 2 0 2 OTG_H_SYNC_A_START 0 14 OTG_H_SYNC_A_END 16 30 regOTG0_OTG_H_SYNC_A_CNTL 0 0x1b2d 3 0 2 OTG_H_SYNC_A_POL 0 0 OTG_COMP_SYNC_A_EN 16 16 OTG_H_SYNC_A_CUTOFF 17 17 regOTG0_OTG_H_TIMING_CNTL 0 0x1b2e 2 0 2 OTG_H_TIMING_DIV_MODE 0 1 OTG_H_TIMING_DIV_UPDATE_MODE 8 8 regOTG0_OTG_V_TOTAL 0 0x1b2f 1 0 2 OTG_V_TOTAL 0 14 regOTG0_OTG_V_TOTAL_MIN 0 0x1b30 1 0 2 OTG_V_TOTAL_MIN 0 14 regOTG0_OTG_V_TOTAL_MAX 0 0x1b31 1 0 2 OTG_V_TOTAL_MAX 0 14 regOTG0_OTG_V_TOTAL_MID 0 0x1b32 1 0 2 OTG_V_TOTAL_MID 0 14 regOTG0_OTG_V_TOTAL_CONTROL 0 0x1b33 8 0 2 OTG_V_TOTAL_MIN_SEL 0 0 OTG_V_TOTAL_MAX_SEL 1 1 OTG_VTOTAL_MID_REPLACING_MAX_EN 2 2 OTG_VTOTAL_MID_REPLACING_MIN_EN 3 3 OTG_FORCE_LOCK_ON_EVENT 4 4 OTG_DRR_EVENT_ACTIVE_PERIOD 5 5 OTG_VTOTAL_MID_FRAME_NUM 8 15 OTG_SET_V_TOTAL_MIN_MASK 16 31 regOTG0_OTG_V_TOTAL_INT_STATUS 0 0x1b34 4 0 2 OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED 0 0 OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_INT 4 4 OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_ACK 8 8 OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_MSK 12 12 regOTG0_OTG_VSYNC_NOM_INT_STATUS 0 0x1b35 2 0 2 OTG_VSYNC_NOM 0 0 OTG_VSYNC_NOM_INT_CLEAR 4 4 regOTG0_OTG_V_BLANK_START_END 0 0x1b36 2 0 2 OTG_V_BLANK_START 0 14 OTG_V_BLANK_END 16 30 regOTG0_OTG_V_SYNC_A 0 0x1b37 2 0 2 OTG_V_SYNC_A_START 0 14 OTG_V_SYNC_A_END 16 30 regOTG0_OTG_V_SYNC_A_CNTL 0 0x1b38 2 0 2 OTG_V_SYNC_A_POL 0 0 OTG_V_SYNC_MODE 8 8 regOTG0_OTG_TRIGA_CNTL 0 0x1b39 12 0 2 OTG_TRIGA_SOURCE_SELECT 0 4 OTG_TRIGA_SOURCE_PIPE_SELECT 5 7 OTG_TRIGA_POLARITY_SELECT 8 10 OTG_TRIGA_RESYNC_BYPASS_EN 11 11 OTG_TRIGA_INPUT_STATUS 12 12 OTG_TRIGA_POLARITY_STATUS 13 13 OTG_TRIGA_OCCURRED 14 14 OTG_TRIGA_RISING_EDGE_DETECT_CNTL 16 17 OTG_TRIGA_FALLING_EDGE_DETECT_CNTL 18 19 OTG_TRIGA_FREQUENCY_SELECT 20 21 OTG_TRIGA_DELAY 24 28 OTG_TRIGA_CLEAR 31 31 regOTG0_OTG_TRIGA_MANUAL_TRIG 0 0x1b3a 1 0 2 OTG_TRIGA_MANUAL_TRIG 0 0 regOTG0_OTG_TRIGB_CNTL 0 0x1b3b 12 0 2 OTG_TRIGB_SOURCE_SELECT 0 4 OTG_TRIGB_SOURCE_PIPE_SELECT 5 7 OTG_TRIGB_POLARITY_SELECT 8 10 OTG_TRIGB_RESYNC_BYPASS_EN 11 11 OTG_TRIGB_INPUT_STATUS 12 12 OTG_TRIGB_POLARITY_STATUS 13 13 OTG_TRIGB_OCCURRED 14 14 OTG_TRIGB_RISING_EDGE_DETECT_CNTL 16 17 OTG_TRIGB_FALLING_EDGE_DETECT_CNTL 18 19 OTG_TRIGB_FREQUENCY_SELECT 20 21 OTG_TRIGB_DELAY 24 28 OTG_TRIGB_CLEAR 31 31 regOTG0_OTG_TRIGB_MANUAL_TRIG 0 0x1b3c 1 0 2 OTG_TRIGB_MANUAL_TRIG 0 0 regOTG0_OTG_FORCE_COUNT_NOW_CNTL 0 0x1b3d 5 0 2 OTG_FORCE_COUNT_NOW_MODE 0 1 OTG_FORCE_COUNT_NOW_CHECK 4 4 OTG_FORCE_COUNT_NOW_TRIG_SEL 8 8 OTG_FORCE_COUNT_NOW_OCCURRED 16 16 OTG_FORCE_COUNT_NOW_CLEAR 24 24 regOTG0_OTG_FLOW_CONTROL 0 0x1b3e 4 0 2 OTG_FLOW_CONTROL_SOURCE_SELECT 0 4 OTG_FLOW_CONTROL_POLARITY 8 8 OTG_FLOW_CONTROL_GRANULARITY 16 16 OTG_FLOW_CONTROL_INPUT_STATUS 24 24 regOTG0_OTG_STEREO_FORCE_NEXT_EYE 0 0x1b3f 1 0 2 OTG_STEREO_FORCE_NEXT_EYE 0 1 regOTG0_OTG_CONTROL 0 0x1b41 7 0 2 OTG_MASTER_EN 0 0 OTG_DISABLE_POINT_CNTL 8 9 OTG_START_POINT_CNTL 12 12 OTG_FIELD_NUMBER_CNTL 13 13 OTG_FIELD_NUMBER_POLARITY 14 14 OTG_CURRENT_MASTER_EN_STATE 16 16 OTG_OUT_MUX 20 21 regOTG0_OTG_INTERLACE_CONTROL 0 0x1b44 2 0 2 OTG_INTERLACE_ENABLE 0 0 OTG_INTERLACE_FORCE_NEXT_FIELD 16 17 regOTG0_OTG_INTERLACE_STATUS 0 0x1b45 2 0 2 OTG_INTERLACE_CURRENT_FIELD 0 0 OTG_INTERLACE_NEXT_FIELD 1 1 regOTG0_OTG_PIXEL_DATA_READBACK0 0 0x1b47 2 0 2 OTG_PIXEL_DATA_BLUE_CB 0 15 OTG_PIXEL_DATA_GREEN_Y 16 31 regOTG0_OTG_PIXEL_DATA_READBACK1 0 0x1b48 1 0 2 OTG_PIXEL_DATA_RED_CR 0 15 regOTG0_OTG_STATUS 0 0x1b49 8 0 2 OTG_V_BLANK 0 0 OTG_V_ACTIVE_DISP 1 1 OTG_V_SYNC_A 2 2 OTG_V_UPDATE 3 3 OTG_V_BLANK_3D_STRUCTURE 5 5 OTG_H_BLANK 16 16 OTG_H_ACTIVE_DISP 17 17 OTG_H_SYNC_A 18 18 regOTG0_OTG_STATUS_POSITION 0 0x1b4a 2 0 2 OTG_VERT_COUNT 0 14 OTG_HORZ_COUNT 16 30 regOTG0_OTG_NOM_VERT_POSITION 0 0x1b4b 1 0 2 OTG_VERT_COUNT_NOM 0 14 regOTG0_OTG_STATUS_FRAME_COUNT 0 0x1b4c 1 0 2 OTG_FRAME_COUNT 0 23 regOTG0_OTG_STATUS_VF_COUNT 0 0x1b4d 1 0 2 OTG_VF_COUNT 0 30 regOTG0_OTG_STATUS_HV_COUNT 0 0x1b4e 1 0 2 OTG_HV_COUNT 0 30 regOTG0_OTG_COUNT_CONTROL 0 0x1b4f 2 0 2 OTG_HORZ_COUNT_BY2_EN 0 0 OTG_HORZ_REPETITION_COUNT 1 4 regOTG0_OTG_COUNT_RESET 0 0x1b50 1 0 2 OTG_RESET_FRAME_COUNT 0 0 regOTG0_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE 0 0x1b51 1 0 2 OTG_MANUAL_FORCE_VSYNC_NEXT_LINE 0 0 regOTG0_OTG_VERT_SYNC_CONTROL 0 0x1b52 3 0 2 OTG_FORCE_VSYNC_NEXT_LINE_OCCURRED 0 0 OTG_FORCE_VSYNC_NEXT_LINE_CLEAR 8 8 OTG_AUTO_FORCE_VSYNC_MODE 16 17 regOTG0_OTG_STEREO_STATUS 0 0x1b53 7 0 2 OTG_STEREO_CURRENT_EYE 0 0 OTG_STEREO_SYNC_OUTPUT 8 8 OTG_STEREO_SYNC_SELECT 16 16 OTG_STEREO_EYE_FLAG 20 20 OTG_STEREO_FORCE_NEXT_EYE_PENDING 24 25 OTG_CURRENT_3D_STRUCTURE_STATE 30 30 OTG_CURRENT_STEREOSYNC_EN_STATE 31 31 regOTG0_OTG_STEREO_CONTROL 0 0x1b54 8 0 2 OTG_STEREO_SYNC_OUTPUT_LINE_NUM 0 14 OTG_STEREO_SYNC_OUTPUT_POLARITY 15 15 OTG_STEREO_EYE_FLAG_POLARITY 17 17 OTG_DISABLE_STEREOSYNC_OUTPUT_FOR_DP 18 18 OTG_DISABLE_FIELD_NUM 19 19 OTG_DISABLE_V_BLANK_FOR_DP_FIX 20 20 OTG_FIELD_NUM_SEL 21 21 OTG_STEREO_EN 24 24 regOTG0_OTG_SNAPSHOT_STATUS 0 0x1b55 3 0 2 OTG_SNAPSHOT_OCCURRED 0 0 OTG_SNAPSHOT_CLEAR 1 1 OTG_SNAPSHOT_MANUAL_TRIGGER 2 2 regOTG0_OTG_SNAPSHOT_CONTROL 0 0x1b56 1 0 2 OTG_AUTO_SNAPSHOT_TRIG_SEL 0 1 regOTG0_OTG_SNAPSHOT_POSITION 0 0x1b57 2 0 2 OTG_SNAPSHOT_VERT_COUNT 0 14 OTG_SNAPSHOT_HORZ_COUNT 16 30 regOTG0_OTG_SNAPSHOT_FRAME 0 0x1b58 1 0 2 OTG_SNAPSHOT_FRAME_COUNT 0 23 regOTG0_OTG_UPDATE_LOCK 0 0x1b5a 1 0 2 OTG_UPDATE_LOCK 0 0 regOTG0_OTG_DOUBLE_BUFFER_CONTROL 0 0x1b5b 10 0 2 OTG_UPDATE_PENDING 0 0 OTG_H_TIMING_DIV_MODE_DB_UPDATE_PENDING 2 2 OTG_DRR_TIMING_DBUF_UPDATE_PENDING 4 4 OTG_TIMING_DB_UPDATE_PENDING 5 5 OTG_3D_CTRL_DB_UPDATE_PENDING 6 6 OTG_3D_STRUCTURE_EN_DB_UPDATE_PENDING 7 7 OTG_UPDATE_INSTANTLY 8 8 OTG_VSTARTUP_DB_UPDATE_PENDING 9 9 OTG_DSC_POSITION_DB_UPDATE_PENDING 10 10 OTG_DRR_TIMING_DBUF_UPDATE_MODE 24 25 regOTG0_OTG_MASTER_EN 0 0x1b5c 1 0 2 OTG_MASTER_EN 0 0 regOTG0_OTG_VERTICAL_INTERRUPT0_POSITION 0 0x1b62 2 0 2 OTG_VERTICAL_INTERRUPT0_LINE_START 0 14 OTG_VERTICAL_INTERRUPT0_LINE_END 16 30 regOTG0_OTG_VERTICAL_INTERRUPT0_CONTROL 0 0x1b63 7 0 2 OTG_VERTICAL_INTERRUPT0_OUTPUT_POLARITY 4 4 OTG_VERTICAL_INTERRUPT0_INT_ENABLE 8 8 OTG_VERTICAL_INTERRUPT0_STATUS 12 12 OTG_VERTICAL_INTERRUPT0_INT_STATUS 16 16 OTG_VERTICAL_INTERRUPT0_CLEAR 20 20 OTG_VERTICAL_INTERRUPT0_INT_TYPE 24 24 OTG_VINTE_STATUS 28 28 regOTG0_OTG_VERTICAL_INTERRUPT1_POSITION 0 0x1b64 1 0 2 OTG_VERTICAL_INTERRUPT1_LINE_START 0 14 regOTG0_OTG_VERTICAL_INTERRUPT1_CONTROL 0 0x1b65 5 0 2 OTG_VERTICAL_INTERRUPT1_INT_ENABLE 8 8 OTG_VERTICAL_INTERRUPT1_STATUS 12 12 OTG_VERTICAL_INTERRUPT1_INT_STATUS 16 16 OTG_VERTICAL_INTERRUPT1_CLEAR 20 20 OTG_VERTICAL_INTERRUPT1_INT_TYPE 24 24 regOTG0_OTG_VERTICAL_INTERRUPT2_POSITION 0 0x1b66 1 0 2 OTG_VERTICAL_INTERRUPT2_LINE_START 0 14 regOTG0_OTG_VERTICAL_INTERRUPT2_CONTROL 0 0x1b67 5 0 2 OTG_VERTICAL_INTERRUPT2_INT_ENABLE 8 8 OTG_VERTICAL_INTERRUPT2_STATUS 12 12 OTG_VERTICAL_INTERRUPT2_INT_STATUS 16 16 OTG_VERTICAL_INTERRUPT2_CLEAR 20 20 OTG_VERTICAL_INTERRUPT2_INT_TYPE 24 24 regOTG0_OTG_CRC_CNTL 0 0x1b68 16 0 2 OTG_CRC_EN 0 0 OTG_CRC_DUAL_LINK_EN 1 1 OTG_CRC_DUAL_LINK_MODE 2 2 OTG_CRC_BLANK_ONLY 3 3 OTG_CRC_CONT_EN 4 4 OTG_CRC_CAPTURE_START_SEL 5 6 OTG_CRC1_EN 7 7 OTG_CRC_STEREO_MODE 8 9 OTG_CRC_INTERLACE_MODE 12 13 OTG_CRC_USE_NEW_AND_REPEATED_PIXELS 19 19 OTG_CRC0_SELECT 20 22 OTG_CRC1_SELECT 24 26 OTG_ONE_SHOT_CRC0_PENDING 28 28 OTG_ONE_SHOT_CRC1_PENDING 29 29 OTG_ONE_SHOT_CRC2_PENDING 30 30 OTG_ONE_SHOT_CRC3_PENDING 31 31 regOTG0_OTG_CRC_CNTL2 0 0x1b69 4 0 2 OTG_CRC_DSC_MODE 0 0 OTG_CRC_DATA_STREAM_COMBINE_MODE 1 1 OTG_CRC_DATA_STREAM_SPLIT_MODE 4 5 OTG_CRC_DATA_FORMAT 8 9 regOTG0_OTG_CRC0_WINDOWA_X_CONTROL 0 0x1b6a 2 0 2 OTG_CRC0_WINDOWA_X_START 0 14 OTG_CRC0_WINDOWA_X_END 16 30 regOTG0_OTG_CRC0_WINDOWA_Y_CONTROL 0 0x1b6b 2 0 2 OTG_CRC0_WINDOWA_Y_START 0 14 OTG_CRC0_WINDOWA_Y_END 16 30 regOTG0_OTG_CRC0_WINDOWB_X_CONTROL 0 0x1b6c 2 0 2 OTG_CRC0_WINDOWB_X_START 0 14 OTG_CRC0_WINDOWB_X_END 16 30 regOTG0_OTG_CRC0_WINDOWB_Y_CONTROL 0 0x1b6d 2 0 2 OTG_CRC0_WINDOWB_Y_START 0 14 OTG_CRC0_WINDOWB_Y_END 16 30 regOTG0_OTG_CRC0_DATA_RG 0 0x1b6e 2 0 2 CRC0_R_CR 0 15 CRC0_G_Y 16 31 regOTG0_OTG_CRC0_DATA_B 0 0x1b6f 2 0 2 CRC0_B_CB 0 15 CRC0_C 16 31 regOTG0_OTG_CRC1_WINDOWA_X_CONTROL 0 0x1b70 2 0 2 OTG_CRC1_WINDOWA_X_START 0 14 OTG_CRC1_WINDOWA_X_END 16 30 regOTG0_OTG_CRC1_WINDOWA_Y_CONTROL 0 0x1b71 2 0 2 OTG_CRC1_WINDOWA_Y_START 0 14 OTG_CRC1_WINDOWA_Y_END 16 30 regOTG0_OTG_CRC1_WINDOWB_X_CONTROL 0 0x1b72 2 0 2 OTG_CRC1_WINDOWB_X_START 0 14 OTG_CRC1_WINDOWB_X_END 16 30 regOTG0_OTG_CRC1_WINDOWB_Y_CONTROL 0 0x1b73 2 0 2 OTG_CRC1_WINDOWB_Y_START 0 14 OTG_CRC1_WINDOWB_Y_END 16 30 regOTG0_OTG_CRC1_DATA_RG 0 0x1b74 2 0 2 CRC1_R_CR 0 15 CRC1_G_Y 16 31 regOTG0_OTG_CRC1_DATA_B 0 0x1b75 2 0 2 CRC1_B_CB 0 15 CRC1_C 16 31 regOTG0_OTG_CRC2_DATA_RG 0 0x1b76 2 0 2 CRC2_R_CR 0 15 CRC2_G_Y 16 31 regOTG0_OTG_CRC2_DATA_B 0 0x1b77 2 0 2 CRC2_B_CB 0 15 CRC2_C 16 31 regOTG0_OTG_CRC3_DATA_RG 0 0x1b78 2 0 2 CRC3_R_CR 0 15 CRC3_G_Y 16 31 regOTG0_OTG_CRC3_DATA_B 0 0x1b79 2 0 2 CRC3_B_CB 0 15 CRC3_C 16 31 regOTG0_OTG_CRC_SIG_RED_GREEN_MASK 0 0x1b7a 2 0 2 OTG_CRC_SIG_RED_MASK 0 15 OTG_CRC_SIG_GREEN_MASK 16 31 regOTG0_OTG_CRC_SIG_BLUE_CONTROL_MASK 0 0x1b7b 2 0 2 OTG_CRC_SIG_BLUE_MASK 0 15 OTG_CRC_SIG_CONTROL_MASK 16 31 regOTG0_OTG_STATIC_SCREEN_CONTROL 0 0x1b82 9 0 2 OTG_STATIC_SCREEN_EVENT_MASK 0 15 OTG_STATIC_SCREEN_FRAME_COUNT 16 23 OTG_CPU_SS_INT_ENABLE 24 24 OTG_SS_STATUS 25 25 OTG_CPU_SS_INT_STATUS 26 26 OTG_CPU_SS_INT_CLEAR 27 27 OTG_CPU_SS_INT_TYPE 28 28 OTG_STATIC_SCREEN_OVERRIDE 30 30 OTG_STATIC_SCREEN_OVERRIDE_VALUE 31 31 regOTG0_OTG_3D_STRUCTURE_CONTROL 0 0x1b83 6 0 2 OTG_3D_STRUCTURE_EN 0 0 OTG_3D_STRUCTURE_V_UPDATE_MODE 8 9 OTG_3D_STRUCTURE_STEREO_SEL_OVR 12 12 OTG_3D_STRUCTURE_F_COUNT_RESET 16 16 OTG_3D_STRUCTURE_F_COUNT_RESET_PENDING 17 17 OTG_3D_STRUCTURE_F_COUNT 18 19 regOTG0_OTG_GSL_VSYNC_GAP 0 0x1b84 8 0 2 OTG_GSL_VSYNC_GAP_LIMIT 0 7 OTG_GSL_VSYNC_GAP_DELAY 8 15 OTG_GSL_VSYNC_GAP_SOURCE_SEL 16 16 OTG_GSL_VSYNC_GAP_MODE 17 18 OTG_GSL_VSYNC_GAP_CLEAR 19 19 OTG_GSL_VSYNC_GAP_OCCURRED 20 20 OTG_GSL_VSYNC_GAP_MASTER_FASTER 23 23 OTG_GSL_VSYNC_GAP 24 31 regOTG0_OTG_MASTER_UPDATE_MODE 0 0x1b85 1 0 2 MASTER_UPDATE_INTERLACED_MODE 0 1 regOTG0_OTG_CLOCK_CONTROL 0 0x1b86 5 0 2 OTG_CLOCK_EN 0 0 OTG_CLOCK_GATE_DIS 1 1 OTG_SOFT_RESET 4 4 OTG_CLOCK_ON 8 8 OTG_BUSY 16 16 regOTG0_OTG_VSTARTUP_PARAM 0 0x1b87 1 0 2 VSTARTUP_START 0 9 regOTG0_OTG_VUPDATE_PARAM 0 0x1b88 2 0 2 VUPDATE_OFFSET 0 15 VUPDATE_WIDTH 16 25 regOTG0_OTG_VREADY_PARAM 0 0x1b89 1 0 2 VREADY_OFFSET 0 15 regOTG0_OTG_GLOBAL_SYNC_STATUS 0 0x1b8a 25 0 2 VSTARTUP_INT_EN 0 0 VSTARTUP_INT_TYPE 1 1 VSTARTUP_EVENT_OCCURRED 2 2 VSTARTUP_INT_STATUS 3 3 VSTARTUP_EVENT_CLEAR 4 4 VUPDATE_INT_EN 5 5 VUPDATE_INT_TYPE 6 6 VUPDATE_INT_POSITION_SEL 7 7 VUPDATE_EVENT_OCCURRED 8 8 VUPDATE_INT_STATUS 9 9 VUPDATE_EVENT_CLEAR 10 10 VUPDATE_STATUS 11 11 VUPDATE_NO_LOCK_INT_EN 12 12 VUPDATE_NO_LOCK_INT_TYPE 13 13 VUPDATE_NO_LOCK_EVENT_OCCURRED 14 14 VUPDATE_NO_LOCK_INT_STATUS 15 15 VUPDATE_NO_LOCK_EVENT_CLEAR 16 16 VUPDATE_NO_LOCK_STATUS 17 17 VREADY_INT_EN 18 18 VREADY_INT_TYPE 19 19 VREADY_EVENT_OCCURRED 20 20 VREADY_INT_STATUS 21 21 VREADY_EVENT_CLEAR 22 22 STEREO_SELECT_STATUS 24 24 FIELD_NUMBER_STATUS 25 25 regOTG0_OTG_MASTER_UPDATE_LOCK 0 0x1b8b 2 0 2 OTG_MASTER_UPDATE_LOCK 0 0 UPDATE_LOCK_STATUS 8 8 regOTG0_OTG_GSL_CONTROL 0 0x1b8c 9 0 2 OTG_GSL0_EN 0 0 OTG_GSL1_EN 1 1 OTG_GSL2_EN 2 2 OTG_GSL_MASTER_EN 3 3 OTG_GSL_MASTER_MODE 4 5 OTG_GSL_CHECK_DELAY 8 11 OTG_GSL_FORCE_DELAY 16 20 OTG_GSL_CHECK_ALL_FIELDS 28 28 OTG_MASTER_UPDATE_LOCK_GSL_EN 31 31 regOTG0_OTG_GSL_WINDOW_X 0 0x1b8d 2 0 2 OTG_GSL_WINDOW_START_X 0 14 OTG_GSL_WINDOW_END_X 16 30 regOTG0_OTG_GSL_WINDOW_Y 0 0x1b8e 2 0 2 OTG_GSL_WINDOW_START_Y 0 14 OTG_GSL_WINDOW_END_Y 16 30 regOTG0_OTG_VUPDATE_KEEPOUT 0 0x1b8f 3 0 2 MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_START_OFFSET 0 15 MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_END_OFFSET 16 25 OTG_MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_EN 31 31 regOTG0_OTG_GLOBAL_CONTROL0 0 0x1b90 3 0 2 MASTER_UPDATE_LOCK_DB_START_X 0 14 MASTER_UPDATE_LOCK_DB_END_X 16 30 MASTER_UPDATE_LOCK_DB_EN 31 31 regOTG0_OTG_GLOBAL_CONTROL1 0 0x1b91 3 0 2 MASTER_UPDATE_LOCK_DB_START_Y 0 14 MASTER_UPDATE_LOCK_DB_END_Y 16 30 MASTER_UPDATE_LOCK_VCOUNT_MODE 31 31 regOTG0_OTG_GLOBAL_CONTROL2 0 0x1b92 5 0 2 GLOBAL_UPDATE_LOCK_EN 10 10 MANUAL_FLOW_CONTROL_SEL 16 18 OTG_MASTER_UPDATE_LOCK_SEL 25 27 OTG_VUPDATE_BLOCK_DISABLE 30 30 DCCG_VUPDATE_MODE 31 31 regOTG0_OTG_GLOBAL_CONTROL3 0 0x1b93 4 0 2 MASTER_UPDATE_LOCK_DB_FIELD 0 1 MASTER_UPDATE_LOCK_DB_STEREO_SEL 4 5 DIG_UPDATE_FIELD_SEL 16 17 DIG_UPDATE_EYE_SEL 20 21 regOTG0_OTG_GLOBAL_CONTROL4 0 0x1b94 3 0 2 DIG_UPDATE_POSITION_X 0 14 DIG_UPDATE_POSITION_Y 16 30 DIG_UPDATE_VCOUNT_MODE 31 31 regOTG0_OTG_TRIG_MANUAL_CONTROL 0 0x1b95 1 0 2 TRIG_MANUAL_CONTROL 0 0 regOTG0_OTG_MANUAL_FLOW_CONTROL 0 0x1b96 1 0 2 MANUAL_FLOW_CONTROL 0 0 regOTG0_OTG_DRR_TIMING_INT_STATUS 0 0x1b97 10 0 2 OTG_DRR_TIMING_UPDATE_OCCURRED 0 0 OTG_DRR_TIMING_UPDATE_OCCURRED_INT 4 4 OTG_DRR_TIMING_UPDATE_OCCURRED_CLEAR 8 8 OTG_DRR_TIMING_UPDATE_OCCURRED_INT_MSK 12 12 OTG_DRR_TIMING_UPDATE_OCCURRED_INT_TYPE 13 13 OTG_DRR_V_TOTAL_REACH_OCCURRED 16 16 OTG_DRR_V_TOTAL_REACH_OCCURRED_INT 20 20 OTG_DRR_V_TOTAL_REACH_OCCURRED_CLEAR 24 24 OTG_DRR_V_TOTAL_REACH_OCCURRED_INT_MSK 28 28 OTG_DRR_V_TOTAL_REACH_OCCURRED_INT_TYPE 29 29 regOTG0_OTG_DRR_V_TOTAL_REACH_RANGE 0 0x1b98 2 0 2 OTG_DRR_V_TOTAL_REACH_LOWER_RANGE 0 14 OTG_DRR_V_TOTAL_REACH_UPPER_RANGE 16 30 regOTG0_OTG_DRR_V_TOTAL_CHANGE 0 0x1b99 1 0 2 OTG_DRR_V_TOTAL_CHANGE_LIMIT 0 14 regOTG0_OTG_DRR_TRIGGER_WINDOW 0 0x1b9a 2 0 2 OTG_DRR_TRIGGER_WINDOW_START_X 0 14 OTG_DRR_TRIGGER_WINDOW_END_X 16 30 regOTG0_OTG_DRR_CONTROL 0 0x1b9b 2 0 2 OTG_DRR_AVERAGE_FRAME 0 1 OTG_V_TOTAL_LAST_USED_BY_DRR 16 30 regOTG0_OTG_M_CONST_DTO0 0 0x1b9c 1 0 2 OTG_M_CONST_DTO_PHASE 0 31 regOTG0_OTG_M_CONST_DTO1 0 0x1b9d 1 0 2 OTG_M_CONST_DTO_MODULO 0 31 regOTG0_OTG_REQUEST_CONTROL 0 0x1b9e 1 0 2 OTG_REQUEST_MODE_FOR_H_DUPLICATE 0 0 regOTG0_OTG_DSC_START_POSITION 0 0x1b9f 2 0 2 OTG_DSC_START_POSITION_X 0 14 OTG_DSC_START_POSITION_LINE_NUM 16 25 regOTG0_OTG_PIPE_UPDATE_STATUS 0 0x1ba0 4 0 2 OTG_FLIP_PENDING 0 0 OTG_DC_REG_UPDATE_PENDING 4 4 OTG_CURSOR_UPDATE_PENDING 8 8 OTG_VUPDATE_KEEPOUT_STATUS 16 16 regOTG0_OTG_SPARE_REGISTER 0 0x1ba2 1 0 2 OTG_SPARE_REG 0 31 regOTG1_OTG_H_TOTAL 0 0x1baa 1 0 2 OTG_H_TOTAL 0 14 regOTG1_OTG_H_BLANK_START_END 0 0x1bab 2 0 2 OTG_H_BLANK_START 0 14 OTG_H_BLANK_END 16 30 regOTG1_OTG_H_SYNC_A 0 0x1bac 2 0 2 OTG_H_SYNC_A_START 0 14 OTG_H_SYNC_A_END 16 30 regOTG1_OTG_H_SYNC_A_CNTL 0 0x1bad 3 0 2 OTG_H_SYNC_A_POL 0 0 OTG_COMP_SYNC_A_EN 16 16 OTG_H_SYNC_A_CUTOFF 17 17 regOTG1_OTG_H_TIMING_CNTL 0 0x1bae 2 0 2 OTG_H_TIMING_DIV_MODE 0 1 OTG_H_TIMING_DIV_UPDATE_MODE 8 8 regOTG1_OTG_V_TOTAL 0 0x1baf 1 0 2 OTG_V_TOTAL 0 14 regOTG1_OTG_V_TOTAL_MIN 0 0x1bb0 1 0 2 OTG_V_TOTAL_MIN 0 14 regOTG1_OTG_V_TOTAL_MAX 0 0x1bb1 1 0 2 OTG_V_TOTAL_MAX 0 14 regOTG1_OTG_V_TOTAL_MID 0 0x1bb2 1 0 2 OTG_V_TOTAL_MID 0 14 regOTG1_OTG_V_TOTAL_CONTROL 0 0x1bb3 8 0 2 OTG_V_TOTAL_MIN_SEL 0 0 OTG_V_TOTAL_MAX_SEL 1 1 OTG_VTOTAL_MID_REPLACING_MAX_EN 2 2 OTG_VTOTAL_MID_REPLACING_MIN_EN 3 3 OTG_FORCE_LOCK_ON_EVENT 4 4 OTG_DRR_EVENT_ACTIVE_PERIOD 5 5 OTG_VTOTAL_MID_FRAME_NUM 8 15 OTG_SET_V_TOTAL_MIN_MASK 16 31 regOTG1_OTG_V_TOTAL_INT_STATUS 0 0x1bb4 4 0 2 OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED 0 0 OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_INT 4 4 OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_ACK 8 8 OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_MSK 12 12 regOTG1_OTG_VSYNC_NOM_INT_STATUS 0 0x1bb5 2 0 2 OTG_VSYNC_NOM 0 0 OTG_VSYNC_NOM_INT_CLEAR 4 4 regOTG1_OTG_V_BLANK_START_END 0 0x1bb6 2 0 2 OTG_V_BLANK_START 0 14 OTG_V_BLANK_END 16 30 regOTG1_OTG_V_SYNC_A 0 0x1bb7 2 0 2 OTG_V_SYNC_A_START 0 14 OTG_V_SYNC_A_END 16 30 regOTG1_OTG_V_SYNC_A_CNTL 0 0x1bb8 2 0 2 OTG_V_SYNC_A_POL 0 0 OTG_V_SYNC_MODE 8 8 regOTG1_OTG_TRIGA_CNTL 0 0x1bb9 12 0 2 OTG_TRIGA_SOURCE_SELECT 0 4 OTG_TRIGA_SOURCE_PIPE_SELECT 5 7 OTG_TRIGA_POLARITY_SELECT 8 10 OTG_TRIGA_RESYNC_BYPASS_EN 11 11 OTG_TRIGA_INPUT_STATUS 12 12 OTG_TRIGA_POLARITY_STATUS 13 13 OTG_TRIGA_OCCURRED 14 14 OTG_TRIGA_RISING_EDGE_DETECT_CNTL 16 17 OTG_TRIGA_FALLING_EDGE_DETECT_CNTL 18 19 OTG_TRIGA_FREQUENCY_SELECT 20 21 OTG_TRIGA_DELAY 24 28 OTG_TRIGA_CLEAR 31 31 regOTG1_OTG_TRIGA_MANUAL_TRIG 0 0x1bba 1 0 2 OTG_TRIGA_MANUAL_TRIG 0 0 regOTG1_OTG_TRIGB_CNTL 0 0x1bbb 12 0 2 OTG_TRIGB_SOURCE_SELECT 0 4 OTG_TRIGB_SOURCE_PIPE_SELECT 5 7 OTG_TRIGB_POLARITY_SELECT 8 10 OTG_TRIGB_RESYNC_BYPASS_EN 11 11 OTG_TRIGB_INPUT_STATUS 12 12 OTG_TRIGB_POLARITY_STATUS 13 13 OTG_TRIGB_OCCURRED 14 14 OTG_TRIGB_RISING_EDGE_DETECT_CNTL 16 17 OTG_TRIGB_FALLING_EDGE_DETECT_CNTL 18 19 OTG_TRIGB_FREQUENCY_SELECT 20 21 OTG_TRIGB_DELAY 24 28 OTG_TRIGB_CLEAR 31 31 regOTG1_OTG_TRIGB_MANUAL_TRIG 0 0x1bbc 1 0 2 OTG_TRIGB_MANUAL_TRIG 0 0 regOTG1_OTG_FORCE_COUNT_NOW_CNTL 0 0x1bbd 5 0 2 OTG_FORCE_COUNT_NOW_MODE 0 1 OTG_FORCE_COUNT_NOW_CHECK 4 4 OTG_FORCE_COUNT_NOW_TRIG_SEL 8 8 OTG_FORCE_COUNT_NOW_OCCURRED 16 16 OTG_FORCE_COUNT_NOW_CLEAR 24 24 regOTG1_OTG_FLOW_CONTROL 0 0x1bbe 4 0 2 OTG_FLOW_CONTROL_SOURCE_SELECT 0 4 OTG_FLOW_CONTROL_POLARITY 8 8 OTG_FLOW_CONTROL_GRANULARITY 16 16 OTG_FLOW_CONTROL_INPUT_STATUS 24 24 regOTG1_OTG_STEREO_FORCE_NEXT_EYE 0 0x1bbf 1 0 2 OTG_STEREO_FORCE_NEXT_EYE 0 1 regOTG1_OTG_CONTROL 0 0x1bc1 7 0 2 OTG_MASTER_EN 0 0 OTG_DISABLE_POINT_CNTL 8 9 OTG_START_POINT_CNTL 12 12 OTG_FIELD_NUMBER_CNTL 13 13 OTG_FIELD_NUMBER_POLARITY 14 14 OTG_CURRENT_MASTER_EN_STATE 16 16 OTG_OUT_MUX 20 21 regOTG1_OTG_INTERLACE_CONTROL 0 0x1bc4 2 0 2 OTG_INTERLACE_ENABLE 0 0 OTG_INTERLACE_FORCE_NEXT_FIELD 16 17 regOTG1_OTG_INTERLACE_STATUS 0 0x1bc5 2 0 2 OTG_INTERLACE_CURRENT_FIELD 0 0 OTG_INTERLACE_NEXT_FIELD 1 1 regOTG1_OTG_PIXEL_DATA_READBACK0 0 0x1bc7 2 0 2 OTG_PIXEL_DATA_BLUE_CB 0 15 OTG_PIXEL_DATA_GREEN_Y 16 31 regOTG1_OTG_PIXEL_DATA_READBACK1 0 0x1bc8 1 0 2 OTG_PIXEL_DATA_RED_CR 0 15 regOTG1_OTG_STATUS 0 0x1bc9 8 0 2 OTG_V_BLANK 0 0 OTG_V_ACTIVE_DISP 1 1 OTG_V_SYNC_A 2 2 OTG_V_UPDATE 3 3 OTG_V_BLANK_3D_STRUCTURE 5 5 OTG_H_BLANK 16 16 OTG_H_ACTIVE_DISP 17 17 OTG_H_SYNC_A 18 18 regOTG1_OTG_STATUS_POSITION 0 0x1bca 2 0 2 OTG_VERT_COUNT 0 14 OTG_HORZ_COUNT 16 30 regOTG1_OTG_NOM_VERT_POSITION 0 0x1bcb 1 0 2 OTG_VERT_COUNT_NOM 0 14 regOTG1_OTG_STATUS_FRAME_COUNT 0 0x1bcc 1 0 2 OTG_FRAME_COUNT 0 23 regOTG1_OTG_STATUS_VF_COUNT 0 0x1bcd 1 0 2 OTG_VF_COUNT 0 30 regOTG1_OTG_STATUS_HV_COUNT 0 0x1bce 1 0 2 OTG_HV_COUNT 0 30 regOTG1_OTG_COUNT_CONTROL 0 0x1bcf 2 0 2 OTG_HORZ_COUNT_BY2_EN 0 0 OTG_HORZ_REPETITION_COUNT 1 4 regOTG1_OTG_COUNT_RESET 0 0x1bd0 1 0 2 OTG_RESET_FRAME_COUNT 0 0 regOTG1_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE 0 0x1bd1 1 0 2 OTG_MANUAL_FORCE_VSYNC_NEXT_LINE 0 0 regOTG1_OTG_VERT_SYNC_CONTROL 0 0x1bd2 3 0 2 OTG_FORCE_VSYNC_NEXT_LINE_OCCURRED 0 0 OTG_FORCE_VSYNC_NEXT_LINE_CLEAR 8 8 OTG_AUTO_FORCE_VSYNC_MODE 16 17 regOTG1_OTG_STEREO_STATUS 0 0x1bd3 7 0 2 OTG_STEREO_CURRENT_EYE 0 0 OTG_STEREO_SYNC_OUTPUT 8 8 OTG_STEREO_SYNC_SELECT 16 16 OTG_STEREO_EYE_FLAG 20 20 OTG_STEREO_FORCE_NEXT_EYE_PENDING 24 25 OTG_CURRENT_3D_STRUCTURE_STATE 30 30 OTG_CURRENT_STEREOSYNC_EN_STATE 31 31 regOTG1_OTG_STEREO_CONTROL 0 0x1bd4 8 0 2 OTG_STEREO_SYNC_OUTPUT_LINE_NUM 0 14 OTG_STEREO_SYNC_OUTPUT_POLARITY 15 15 OTG_STEREO_EYE_FLAG_POLARITY 17 17 OTG_DISABLE_STEREOSYNC_OUTPUT_FOR_DP 18 18 OTG_DISABLE_FIELD_NUM 19 19 OTG_DISABLE_V_BLANK_FOR_DP_FIX 20 20 OTG_FIELD_NUM_SEL 21 21 OTG_STEREO_EN 24 24 regOTG1_OTG_SNAPSHOT_STATUS 0 0x1bd5 3 0 2 OTG_SNAPSHOT_OCCURRED 0 0 OTG_SNAPSHOT_CLEAR 1 1 OTG_SNAPSHOT_MANUAL_TRIGGER 2 2 regOTG1_OTG_SNAPSHOT_CONTROL 0 0x1bd6 1 0 2 OTG_AUTO_SNAPSHOT_TRIG_SEL 0 1 regOTG1_OTG_SNAPSHOT_POSITION 0 0x1bd7 2 0 2 OTG_SNAPSHOT_VERT_COUNT 0 14 OTG_SNAPSHOT_HORZ_COUNT 16 30 regOTG1_OTG_SNAPSHOT_FRAME 0 0x1bd8 1 0 2 OTG_SNAPSHOT_FRAME_COUNT 0 23 regOTG1_OTG_UPDATE_LOCK 0 0x1bda 1 0 2 OTG_UPDATE_LOCK 0 0 regOTG1_OTG_DOUBLE_BUFFER_CONTROL 0 0x1bdb 10 0 2 OTG_UPDATE_PENDING 0 0 OTG_H_TIMING_DIV_MODE_DB_UPDATE_PENDING 2 2 OTG_DRR_TIMING_DBUF_UPDATE_PENDING 4 4 OTG_TIMING_DB_UPDATE_PENDING 5 5 OTG_3D_CTRL_DB_UPDATE_PENDING 6 6 OTG_3D_STRUCTURE_EN_DB_UPDATE_PENDING 7 7 OTG_UPDATE_INSTANTLY 8 8 OTG_VSTARTUP_DB_UPDATE_PENDING 9 9 OTG_DSC_POSITION_DB_UPDATE_PENDING 10 10 OTG_DRR_TIMING_DBUF_UPDATE_MODE 24 25 regOTG1_OTG_MASTER_EN 0 0x1bdc 1 0 2 OTG_MASTER_EN 0 0 regOTG1_OTG_VERTICAL_INTERRUPT0_POSITION 0 0x1be2 2 0 2 OTG_VERTICAL_INTERRUPT0_LINE_START 0 14 OTG_VERTICAL_INTERRUPT0_LINE_END 16 30 regOTG1_OTG_VERTICAL_INTERRUPT0_CONTROL 0 0x1be3 7 0 2 OTG_VERTICAL_INTERRUPT0_OUTPUT_POLARITY 4 4 OTG_VERTICAL_INTERRUPT0_INT_ENABLE 8 8 OTG_VERTICAL_INTERRUPT0_STATUS 12 12 OTG_VERTICAL_INTERRUPT0_INT_STATUS 16 16 OTG_VERTICAL_INTERRUPT0_CLEAR 20 20 OTG_VERTICAL_INTERRUPT0_INT_TYPE 24 24 OTG_VINTE_STATUS 28 28 regOTG1_OTG_VERTICAL_INTERRUPT1_POSITION 0 0x1be4 1 0 2 OTG_VERTICAL_INTERRUPT1_LINE_START 0 14 regOTG1_OTG_VERTICAL_INTERRUPT1_CONTROL 0 0x1be5 5 0 2 OTG_VERTICAL_INTERRUPT1_INT_ENABLE 8 8 OTG_VERTICAL_INTERRUPT1_STATUS 12 12 OTG_VERTICAL_INTERRUPT1_INT_STATUS 16 16 OTG_VERTICAL_INTERRUPT1_CLEAR 20 20 OTG_VERTICAL_INTERRUPT1_INT_TYPE 24 24 regOTG1_OTG_VERTICAL_INTERRUPT2_POSITION 0 0x1be6 1 0 2 OTG_VERTICAL_INTERRUPT2_LINE_START 0 14 regOTG1_OTG_VERTICAL_INTERRUPT2_CONTROL 0 0x1be7 5 0 2 OTG_VERTICAL_INTERRUPT2_INT_ENABLE 8 8 OTG_VERTICAL_INTERRUPT2_STATUS 12 12 OTG_VERTICAL_INTERRUPT2_INT_STATUS 16 16 OTG_VERTICAL_INTERRUPT2_CLEAR 20 20 OTG_VERTICAL_INTERRUPT2_INT_TYPE 24 24 regOTG1_OTG_CRC_CNTL 0 0x1be8 16 0 2 OTG_CRC_EN 0 0 OTG_CRC_DUAL_LINK_EN 1 1 OTG_CRC_DUAL_LINK_MODE 2 2 OTG_CRC_BLANK_ONLY 3 3 OTG_CRC_CONT_EN 4 4 OTG_CRC_CAPTURE_START_SEL 5 6 OTG_CRC1_EN 7 7 OTG_CRC_STEREO_MODE 8 9 OTG_CRC_INTERLACE_MODE 12 13 OTG_CRC_USE_NEW_AND_REPEATED_PIXELS 19 19 OTG_CRC0_SELECT 20 22 OTG_CRC1_SELECT 24 26 OTG_ONE_SHOT_CRC0_PENDING 28 28 OTG_ONE_SHOT_CRC1_PENDING 29 29 OTG_ONE_SHOT_CRC2_PENDING 30 30 OTG_ONE_SHOT_CRC3_PENDING 31 31 regOTG1_OTG_CRC_CNTL2 0 0x1be9 4 0 2 OTG_CRC_DSC_MODE 0 0 OTG_CRC_DATA_STREAM_COMBINE_MODE 1 1 OTG_CRC_DATA_STREAM_SPLIT_MODE 4 5 OTG_CRC_DATA_FORMAT 8 9 regOTG1_OTG_CRC0_WINDOWA_X_CONTROL 0 0x1bea 2 0 2 OTG_CRC0_WINDOWA_X_START 0 14 OTG_CRC0_WINDOWA_X_END 16 30 regOTG1_OTG_CRC0_WINDOWA_Y_CONTROL 0 0x1beb 2 0 2 OTG_CRC0_WINDOWA_Y_START 0 14 OTG_CRC0_WINDOWA_Y_END 16 30 regOTG1_OTG_CRC0_WINDOWB_X_CONTROL 0 0x1bec 2 0 2 OTG_CRC0_WINDOWB_X_START 0 14 OTG_CRC0_WINDOWB_X_END 16 30 regOTG1_OTG_CRC0_WINDOWB_Y_CONTROL 0 0x1bed 2 0 2 OTG_CRC0_WINDOWB_Y_START 0 14 OTG_CRC0_WINDOWB_Y_END 16 30 regOTG1_OTG_CRC0_DATA_RG 0 0x1bee 2 0 2 CRC0_R_CR 0 15 CRC0_G_Y 16 31 regOTG1_OTG_CRC0_DATA_B 0 0x1bef 2 0 2 CRC0_B_CB 0 15 CRC0_C 16 31 regOTG1_OTG_CRC1_WINDOWA_X_CONTROL 0 0x1bf0 2 0 2 OTG_CRC1_WINDOWA_X_START 0 14 OTG_CRC1_WINDOWA_X_END 16 30 regOTG1_OTG_CRC1_WINDOWA_Y_CONTROL 0 0x1bf1 2 0 2 OTG_CRC1_WINDOWA_Y_START 0 14 OTG_CRC1_WINDOWA_Y_END 16 30 regOTG1_OTG_CRC1_WINDOWB_X_CONTROL 0 0x1bf2 2 0 2 OTG_CRC1_WINDOWB_X_START 0 14 OTG_CRC1_WINDOWB_X_END 16 30 regOTG1_OTG_CRC1_WINDOWB_Y_CONTROL 0 0x1bf3 2 0 2 OTG_CRC1_WINDOWB_Y_START 0 14 OTG_CRC1_WINDOWB_Y_END 16 30 regOTG1_OTG_CRC1_DATA_RG 0 0x1bf4 2 0 2 CRC1_R_CR 0 15 CRC1_G_Y 16 31 regOTG1_OTG_CRC1_DATA_B 0 0x1bf5 2 0 2 CRC1_B_CB 0 15 CRC1_C 16 31 regOTG1_OTG_CRC2_DATA_RG 0 0x1bf6 2 0 2 CRC2_R_CR 0 15 CRC2_G_Y 16 31 regOTG1_OTG_CRC2_DATA_B 0 0x1bf7 2 0 2 CRC2_B_CB 0 15 CRC2_C 16 31 regOTG1_OTG_CRC3_DATA_RG 0 0x1bf8 2 0 2 CRC3_R_CR 0 15 CRC3_G_Y 16 31 regOTG1_OTG_CRC3_DATA_B 0 0x1bf9 2 0 2 CRC3_B_CB 0 15 CRC3_C 16 31 regOTG1_OTG_CRC_SIG_RED_GREEN_MASK 0 0x1bfa 2 0 2 OTG_CRC_SIG_RED_MASK 0 15 OTG_CRC_SIG_GREEN_MASK 16 31 regOTG1_OTG_CRC_SIG_BLUE_CONTROL_MASK 0 0x1bfb 2 0 2 OTG_CRC_SIG_BLUE_MASK 0 15 OTG_CRC_SIG_CONTROL_MASK 16 31 regOTG1_OTG_STATIC_SCREEN_CONTROL 0 0x1c02 9 0 2 OTG_STATIC_SCREEN_EVENT_MASK 0 15 OTG_STATIC_SCREEN_FRAME_COUNT 16 23 OTG_CPU_SS_INT_ENABLE 24 24 OTG_SS_STATUS 25 25 OTG_CPU_SS_INT_STATUS 26 26 OTG_CPU_SS_INT_CLEAR 27 27 OTG_CPU_SS_INT_TYPE 28 28 OTG_STATIC_SCREEN_OVERRIDE 30 30 OTG_STATIC_SCREEN_OVERRIDE_VALUE 31 31 regOTG1_OTG_3D_STRUCTURE_CONTROL 0 0x1c03 6 0 2 OTG_3D_STRUCTURE_EN 0 0 OTG_3D_STRUCTURE_V_UPDATE_MODE 8 9 OTG_3D_STRUCTURE_STEREO_SEL_OVR 12 12 OTG_3D_STRUCTURE_F_COUNT_RESET 16 16 OTG_3D_STRUCTURE_F_COUNT_RESET_PENDING 17 17 OTG_3D_STRUCTURE_F_COUNT 18 19 regOTG1_OTG_GSL_VSYNC_GAP 0 0x1c04 8 0 2 OTG_GSL_VSYNC_GAP_LIMIT 0 7 OTG_GSL_VSYNC_GAP_DELAY 8 15 OTG_GSL_VSYNC_GAP_SOURCE_SEL 16 16 OTG_GSL_VSYNC_GAP_MODE 17 18 OTG_GSL_VSYNC_GAP_CLEAR 19 19 OTG_GSL_VSYNC_GAP_OCCURRED 20 20 OTG_GSL_VSYNC_GAP_MASTER_FASTER 23 23 OTG_GSL_VSYNC_GAP 24 31 regOTG1_OTG_MASTER_UPDATE_MODE 0 0x1c05 1 0 2 MASTER_UPDATE_INTERLACED_MODE 0 1 regOTG1_OTG_CLOCK_CONTROL 0 0x1c06 5 0 2 OTG_CLOCK_EN 0 0 OTG_CLOCK_GATE_DIS 1 1 OTG_SOFT_RESET 4 4 OTG_CLOCK_ON 8 8 OTG_BUSY 16 16 regOTG1_OTG_VSTARTUP_PARAM 0 0x1c07 1 0 2 VSTARTUP_START 0 9 regOTG1_OTG_VUPDATE_PARAM 0 0x1c08 2 0 2 VUPDATE_OFFSET 0 15 VUPDATE_WIDTH 16 25 regOTG1_OTG_VREADY_PARAM 0 0x1c09 1 0 2 VREADY_OFFSET 0 15 regOTG1_OTG_GLOBAL_SYNC_STATUS 0 0x1c0a 25 0 2 VSTARTUP_INT_EN 0 0 VSTARTUP_INT_TYPE 1 1 VSTARTUP_EVENT_OCCURRED 2 2 VSTARTUP_INT_STATUS 3 3 VSTARTUP_EVENT_CLEAR 4 4 VUPDATE_INT_EN 5 5 VUPDATE_INT_TYPE 6 6 VUPDATE_INT_POSITION_SEL 7 7 VUPDATE_EVENT_OCCURRED 8 8 VUPDATE_INT_STATUS 9 9 VUPDATE_EVENT_CLEAR 10 10 VUPDATE_STATUS 11 11 VUPDATE_NO_LOCK_INT_EN 12 12 VUPDATE_NO_LOCK_INT_TYPE 13 13 VUPDATE_NO_LOCK_EVENT_OCCURRED 14 14 VUPDATE_NO_LOCK_INT_STATUS 15 15 VUPDATE_NO_LOCK_EVENT_CLEAR 16 16 VUPDATE_NO_LOCK_STATUS 17 17 VREADY_INT_EN 18 18 VREADY_INT_TYPE 19 19 VREADY_EVENT_OCCURRED 20 20 VREADY_INT_STATUS 21 21 VREADY_EVENT_CLEAR 22 22 STEREO_SELECT_STATUS 24 24 FIELD_NUMBER_STATUS 25 25 regOTG1_OTG_MASTER_UPDATE_LOCK 0 0x1c0b 2 0 2 OTG_MASTER_UPDATE_LOCK 0 0 UPDATE_LOCK_STATUS 8 8 regOTG1_OTG_GSL_CONTROL 0 0x1c0c 9 0 2 OTG_GSL0_EN 0 0 OTG_GSL1_EN 1 1 OTG_GSL2_EN 2 2 OTG_GSL_MASTER_EN 3 3 OTG_GSL_MASTER_MODE 4 5 OTG_GSL_CHECK_DELAY 8 11 OTG_GSL_FORCE_DELAY 16 20 OTG_GSL_CHECK_ALL_FIELDS 28 28 OTG_MASTER_UPDATE_LOCK_GSL_EN 31 31 regOTG1_OTG_GSL_WINDOW_X 0 0x1c0d 2 0 2 OTG_GSL_WINDOW_START_X 0 14 OTG_GSL_WINDOW_END_X 16 30 regOTG1_OTG_GSL_WINDOW_Y 0 0x1c0e 2 0 2 OTG_GSL_WINDOW_START_Y 0 14 OTG_GSL_WINDOW_END_Y 16 30 regOTG1_OTG_VUPDATE_KEEPOUT 0 0x1c0f 3 0 2 MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_START_OFFSET 0 15 MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_END_OFFSET 16 25 OTG_MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_EN 31 31 regOTG1_OTG_GLOBAL_CONTROL0 0 0x1c10 3 0 2 MASTER_UPDATE_LOCK_DB_START_X 0 14 MASTER_UPDATE_LOCK_DB_END_X 16 30 MASTER_UPDATE_LOCK_DB_EN 31 31 regOTG1_OTG_GLOBAL_CONTROL1 0 0x1c11 3 0 2 MASTER_UPDATE_LOCK_DB_START_Y 0 14 MASTER_UPDATE_LOCK_DB_END_Y 16 30 MASTER_UPDATE_LOCK_VCOUNT_MODE 31 31 regOTG1_OTG_GLOBAL_CONTROL2 0 0x1c12 5 0 2 GLOBAL_UPDATE_LOCK_EN 10 10 MANUAL_FLOW_CONTROL_SEL 16 18 OTG_MASTER_UPDATE_LOCK_SEL 25 27 OTG_VUPDATE_BLOCK_DISABLE 30 30 DCCG_VUPDATE_MODE 31 31 regOTG1_OTG_GLOBAL_CONTROL3 0 0x1c13 4 0 2 MASTER_UPDATE_LOCK_DB_FIELD 0 1 MASTER_UPDATE_LOCK_DB_STEREO_SEL 4 5 DIG_UPDATE_FIELD_SEL 16 17 DIG_UPDATE_EYE_SEL 20 21 regOTG1_OTG_GLOBAL_CONTROL4 0 0x1c14 3 0 2 DIG_UPDATE_POSITION_X 0 14 DIG_UPDATE_POSITION_Y 16 30 DIG_UPDATE_VCOUNT_MODE 31 31 regOTG1_OTG_TRIG_MANUAL_CONTROL 0 0x1c15 1 0 2 TRIG_MANUAL_CONTROL 0 0 regOTG1_OTG_MANUAL_FLOW_CONTROL 0 0x1c16 1 0 2 MANUAL_FLOW_CONTROL 0 0 regOTG1_OTG_DRR_TIMING_INT_STATUS 0 0x1c17 10 0 2 OTG_DRR_TIMING_UPDATE_OCCURRED 0 0 OTG_DRR_TIMING_UPDATE_OCCURRED_INT 4 4 OTG_DRR_TIMING_UPDATE_OCCURRED_CLEAR 8 8 OTG_DRR_TIMING_UPDATE_OCCURRED_INT_MSK 12 12 OTG_DRR_TIMING_UPDATE_OCCURRED_INT_TYPE 13 13 OTG_DRR_V_TOTAL_REACH_OCCURRED 16 16 OTG_DRR_V_TOTAL_REACH_OCCURRED_INT 20 20 OTG_DRR_V_TOTAL_REACH_OCCURRED_CLEAR 24 24 OTG_DRR_V_TOTAL_REACH_OCCURRED_INT_MSK 28 28 OTG_DRR_V_TOTAL_REACH_OCCURRED_INT_TYPE 29 29 regOTG1_OTG_DRR_V_TOTAL_REACH_RANGE 0 0x1c18 2 0 2 OTG_DRR_V_TOTAL_REACH_LOWER_RANGE 0 14 OTG_DRR_V_TOTAL_REACH_UPPER_RANGE 16 30 regOTG1_OTG_DRR_V_TOTAL_CHANGE 0 0x1c19 1 0 2 OTG_DRR_V_TOTAL_CHANGE_LIMIT 0 14 regOTG1_OTG_DRR_TRIGGER_WINDOW 0 0x1c1a 2 0 2 OTG_DRR_TRIGGER_WINDOW_START_X 0 14 OTG_DRR_TRIGGER_WINDOW_END_X 16 30 regOTG1_OTG_DRR_CONTROL 0 0x1c1b 2 0 2 OTG_DRR_AVERAGE_FRAME 0 1 OTG_V_TOTAL_LAST_USED_BY_DRR 16 30 regOTG1_OTG_M_CONST_DTO0 0 0x1c1c 1 0 2 OTG_M_CONST_DTO_PHASE 0 31 regOTG1_OTG_M_CONST_DTO1 0 0x1c1d 1 0 2 OTG_M_CONST_DTO_MODULO 0 31 regOTG1_OTG_REQUEST_CONTROL 0 0x1c1e 1 0 2 OTG_REQUEST_MODE_FOR_H_DUPLICATE 0 0 regOTG1_OTG_DSC_START_POSITION 0 0x1c1f 2 0 2 OTG_DSC_START_POSITION_X 0 14 OTG_DSC_START_POSITION_LINE_NUM 16 25 regOTG1_OTG_PIPE_UPDATE_STATUS 0 0x1c20 4 0 2 OTG_FLIP_PENDING 0 0 OTG_DC_REG_UPDATE_PENDING 4 4 OTG_CURSOR_UPDATE_PENDING 8 8 OTG_VUPDATE_KEEPOUT_STATUS 16 16 regOTG1_OTG_SPARE_REGISTER 0 0x1c22 1 0 2 OTG_SPARE_REG 0 31 regOTG2_OTG_H_TOTAL 0 0x1c2a 1 0 2 OTG_H_TOTAL 0 14 regOTG2_OTG_H_BLANK_START_END 0 0x1c2b 2 0 2 OTG_H_BLANK_START 0 14 OTG_H_BLANK_END 16 30 regOTG2_OTG_H_SYNC_A 0 0x1c2c 2 0 2 OTG_H_SYNC_A_START 0 14 OTG_H_SYNC_A_END 16 30 regOTG2_OTG_H_SYNC_A_CNTL 0 0x1c2d 3 0 2 OTG_H_SYNC_A_POL 0 0 OTG_COMP_SYNC_A_EN 16 16 OTG_H_SYNC_A_CUTOFF 17 17 regOTG2_OTG_H_TIMING_CNTL 0 0x1c2e 2 0 2 OTG_H_TIMING_DIV_MODE 0 1 OTG_H_TIMING_DIV_UPDATE_MODE 8 8 regOTG2_OTG_V_TOTAL 0 0x1c2f 1 0 2 OTG_V_TOTAL 0 14 regOTG2_OTG_V_TOTAL_MIN 0 0x1c30 1 0 2 OTG_V_TOTAL_MIN 0 14 regOTG2_OTG_V_TOTAL_MAX 0 0x1c31 1 0 2 OTG_V_TOTAL_MAX 0 14 regOTG2_OTG_V_TOTAL_MID 0 0x1c32 1 0 2 OTG_V_TOTAL_MID 0 14 regOTG2_OTG_V_TOTAL_CONTROL 0 0x1c33 8 0 2 OTG_V_TOTAL_MIN_SEL 0 0 OTG_V_TOTAL_MAX_SEL 1 1 OTG_VTOTAL_MID_REPLACING_MAX_EN 2 2 OTG_VTOTAL_MID_REPLACING_MIN_EN 3 3 OTG_FORCE_LOCK_ON_EVENT 4 4 OTG_DRR_EVENT_ACTIVE_PERIOD 5 5 OTG_VTOTAL_MID_FRAME_NUM 8 15 OTG_SET_V_TOTAL_MIN_MASK 16 31 regOTG2_OTG_V_TOTAL_INT_STATUS 0 0x1c34 4 0 2 OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED 0 0 OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_INT 4 4 OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_ACK 8 8 OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_MSK 12 12 regOTG2_OTG_VSYNC_NOM_INT_STATUS 0 0x1c35 2 0 2 OTG_VSYNC_NOM 0 0 OTG_VSYNC_NOM_INT_CLEAR 4 4 regOTG2_OTG_V_BLANK_START_END 0 0x1c36 2 0 2 OTG_V_BLANK_START 0 14 OTG_V_BLANK_END 16 30 regOTG2_OTG_V_SYNC_A 0 0x1c37 2 0 2 OTG_V_SYNC_A_START 0 14 OTG_V_SYNC_A_END 16 30 regOTG2_OTG_V_SYNC_A_CNTL 0 0x1c38 2 0 2 OTG_V_SYNC_A_POL 0 0 OTG_V_SYNC_MODE 8 8 regOTG2_OTG_TRIGA_CNTL 0 0x1c39 12 0 2 OTG_TRIGA_SOURCE_SELECT 0 4 OTG_TRIGA_SOURCE_PIPE_SELECT 5 7 OTG_TRIGA_POLARITY_SELECT 8 10 OTG_TRIGA_RESYNC_BYPASS_EN 11 11 OTG_TRIGA_INPUT_STATUS 12 12 OTG_TRIGA_POLARITY_STATUS 13 13 OTG_TRIGA_OCCURRED 14 14 OTG_TRIGA_RISING_EDGE_DETECT_CNTL 16 17 OTG_TRIGA_FALLING_EDGE_DETECT_CNTL 18 19 OTG_TRIGA_FREQUENCY_SELECT 20 21 OTG_TRIGA_DELAY 24 28 OTG_TRIGA_CLEAR 31 31 regOTG2_OTG_TRIGA_MANUAL_TRIG 0 0x1c3a 1 0 2 OTG_TRIGA_MANUAL_TRIG 0 0 regOTG2_OTG_TRIGB_CNTL 0 0x1c3b 12 0 2 OTG_TRIGB_SOURCE_SELECT 0 4 OTG_TRIGB_SOURCE_PIPE_SELECT 5 7 OTG_TRIGB_POLARITY_SELECT 8 10 OTG_TRIGB_RESYNC_BYPASS_EN 11 11 OTG_TRIGB_INPUT_STATUS 12 12 OTG_TRIGB_POLARITY_STATUS 13 13 OTG_TRIGB_OCCURRED 14 14 OTG_TRIGB_RISING_EDGE_DETECT_CNTL 16 17 OTG_TRIGB_FALLING_EDGE_DETECT_CNTL 18 19 OTG_TRIGB_FREQUENCY_SELECT 20 21 OTG_TRIGB_DELAY 24 28 OTG_TRIGB_CLEAR 31 31 regOTG2_OTG_TRIGB_MANUAL_TRIG 0 0x1c3c 1 0 2 OTG_TRIGB_MANUAL_TRIG 0 0 regOTG2_OTG_FORCE_COUNT_NOW_CNTL 0 0x1c3d 5 0 2 OTG_FORCE_COUNT_NOW_MODE 0 1 OTG_FORCE_COUNT_NOW_CHECK 4 4 OTG_FORCE_COUNT_NOW_TRIG_SEL 8 8 OTG_FORCE_COUNT_NOW_OCCURRED 16 16 OTG_FORCE_COUNT_NOW_CLEAR 24 24 regOTG2_OTG_FLOW_CONTROL 0 0x1c3e 4 0 2 OTG_FLOW_CONTROL_SOURCE_SELECT 0 4 OTG_FLOW_CONTROL_POLARITY 8 8 OTG_FLOW_CONTROL_GRANULARITY 16 16 OTG_FLOW_CONTROL_INPUT_STATUS 24 24 regOTG2_OTG_STEREO_FORCE_NEXT_EYE 0 0x1c3f 1 0 2 OTG_STEREO_FORCE_NEXT_EYE 0 1 regOTG2_OTG_CONTROL 0 0x1c41 7 0 2 OTG_MASTER_EN 0 0 OTG_DISABLE_POINT_CNTL 8 9 OTG_START_POINT_CNTL 12 12 OTG_FIELD_NUMBER_CNTL 13 13 OTG_FIELD_NUMBER_POLARITY 14 14 OTG_CURRENT_MASTER_EN_STATE 16 16 OTG_OUT_MUX 20 21 regOTG2_OTG_INTERLACE_CONTROL 0 0x1c44 2 0 2 OTG_INTERLACE_ENABLE 0 0 OTG_INTERLACE_FORCE_NEXT_FIELD 16 17 regOTG2_OTG_INTERLACE_STATUS 0 0x1c45 2 0 2 OTG_INTERLACE_CURRENT_FIELD 0 0 OTG_INTERLACE_NEXT_FIELD 1 1 regOTG2_OTG_PIXEL_DATA_READBACK0 0 0x1c47 2 0 2 OTG_PIXEL_DATA_BLUE_CB 0 15 OTG_PIXEL_DATA_GREEN_Y 16 31 regOTG2_OTG_PIXEL_DATA_READBACK1 0 0x1c48 1 0 2 OTG_PIXEL_DATA_RED_CR 0 15 regOTG2_OTG_STATUS 0 0x1c49 8 0 2 OTG_V_BLANK 0 0 OTG_V_ACTIVE_DISP 1 1 OTG_V_SYNC_A 2 2 OTG_V_UPDATE 3 3 OTG_V_BLANK_3D_STRUCTURE 5 5 OTG_H_BLANK 16 16 OTG_H_ACTIVE_DISP 17 17 OTG_H_SYNC_A 18 18 regOTG2_OTG_STATUS_POSITION 0 0x1c4a 2 0 2 OTG_VERT_COUNT 0 14 OTG_HORZ_COUNT 16 30 regOTG2_OTG_NOM_VERT_POSITION 0 0x1c4b 1 0 2 OTG_VERT_COUNT_NOM 0 14 regOTG2_OTG_STATUS_FRAME_COUNT 0 0x1c4c 1 0 2 OTG_FRAME_COUNT 0 23 regOTG2_OTG_STATUS_VF_COUNT 0 0x1c4d 1 0 2 OTG_VF_COUNT 0 30 regOTG2_OTG_STATUS_HV_COUNT 0 0x1c4e 1 0 2 OTG_HV_COUNT 0 30 regOTG2_OTG_COUNT_CONTROL 0 0x1c4f 2 0 2 OTG_HORZ_COUNT_BY2_EN 0 0 OTG_HORZ_REPETITION_COUNT 1 4 regOTG2_OTG_COUNT_RESET 0 0x1c50 1 0 2 OTG_RESET_FRAME_COUNT 0 0 regOTG2_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE 0 0x1c51 1 0 2 OTG_MANUAL_FORCE_VSYNC_NEXT_LINE 0 0 regOTG2_OTG_VERT_SYNC_CONTROL 0 0x1c52 3 0 2 OTG_FORCE_VSYNC_NEXT_LINE_OCCURRED 0 0 OTG_FORCE_VSYNC_NEXT_LINE_CLEAR 8 8 OTG_AUTO_FORCE_VSYNC_MODE 16 17 regOTG2_OTG_STEREO_STATUS 0 0x1c53 7 0 2 OTG_STEREO_CURRENT_EYE 0 0 OTG_STEREO_SYNC_OUTPUT 8 8 OTG_STEREO_SYNC_SELECT 16 16 OTG_STEREO_EYE_FLAG 20 20 OTG_STEREO_FORCE_NEXT_EYE_PENDING 24 25 OTG_CURRENT_3D_STRUCTURE_STATE 30 30 OTG_CURRENT_STEREOSYNC_EN_STATE 31 31 regOTG2_OTG_STEREO_CONTROL 0 0x1c54 8 0 2 OTG_STEREO_SYNC_OUTPUT_LINE_NUM 0 14 OTG_STEREO_SYNC_OUTPUT_POLARITY 15 15 OTG_STEREO_EYE_FLAG_POLARITY 17 17 OTG_DISABLE_STEREOSYNC_OUTPUT_FOR_DP 18 18 OTG_DISABLE_FIELD_NUM 19 19 OTG_DISABLE_V_BLANK_FOR_DP_FIX 20 20 OTG_FIELD_NUM_SEL 21 21 OTG_STEREO_EN 24 24 regOTG2_OTG_SNAPSHOT_STATUS 0 0x1c55 3 0 2 OTG_SNAPSHOT_OCCURRED 0 0 OTG_SNAPSHOT_CLEAR 1 1 OTG_SNAPSHOT_MANUAL_TRIGGER 2 2 regOTG2_OTG_SNAPSHOT_CONTROL 0 0x1c56 1 0 2 OTG_AUTO_SNAPSHOT_TRIG_SEL 0 1 regOTG2_OTG_SNAPSHOT_POSITION 0 0x1c57 2 0 2 OTG_SNAPSHOT_VERT_COUNT 0 14 OTG_SNAPSHOT_HORZ_COUNT 16 30 regOTG2_OTG_SNAPSHOT_FRAME 0 0x1c58 1 0 2 OTG_SNAPSHOT_FRAME_COUNT 0 23 regOTG2_OTG_UPDATE_LOCK 0 0x1c5a 1 0 2 OTG_UPDATE_LOCK 0 0 regOTG2_OTG_DOUBLE_BUFFER_CONTROL 0 0x1c5b 10 0 2 OTG_UPDATE_PENDING 0 0 OTG_H_TIMING_DIV_MODE_DB_UPDATE_PENDING 2 2 OTG_DRR_TIMING_DBUF_UPDATE_PENDING 4 4 OTG_TIMING_DB_UPDATE_PENDING 5 5 OTG_3D_CTRL_DB_UPDATE_PENDING 6 6 OTG_3D_STRUCTURE_EN_DB_UPDATE_PENDING 7 7 OTG_UPDATE_INSTANTLY 8 8 OTG_VSTARTUP_DB_UPDATE_PENDING 9 9 OTG_DSC_POSITION_DB_UPDATE_PENDING 10 10 OTG_DRR_TIMING_DBUF_UPDATE_MODE 24 25 regOTG2_OTG_MASTER_EN 0 0x1c5c 1 0 2 OTG_MASTER_EN 0 0 regOTG2_OTG_VERTICAL_INTERRUPT0_POSITION 0 0x1c62 2 0 2 OTG_VERTICAL_INTERRUPT0_LINE_START 0 14 OTG_VERTICAL_INTERRUPT0_LINE_END 16 30 regOTG2_OTG_VERTICAL_INTERRUPT0_CONTROL 0 0x1c63 7 0 2 OTG_VERTICAL_INTERRUPT0_OUTPUT_POLARITY 4 4 OTG_VERTICAL_INTERRUPT0_INT_ENABLE 8 8 OTG_VERTICAL_INTERRUPT0_STATUS 12 12 OTG_VERTICAL_INTERRUPT0_INT_STATUS 16 16 OTG_VERTICAL_INTERRUPT0_CLEAR 20 20 OTG_VERTICAL_INTERRUPT0_INT_TYPE 24 24 OTG_VINTE_STATUS 28 28 regOTG2_OTG_VERTICAL_INTERRUPT1_POSITION 0 0x1c64 1 0 2 OTG_VERTICAL_INTERRUPT1_LINE_START 0 14 regOTG2_OTG_VERTICAL_INTERRUPT1_CONTROL 0 0x1c65 5 0 2 OTG_VERTICAL_INTERRUPT1_INT_ENABLE 8 8 OTG_VERTICAL_INTERRUPT1_STATUS 12 12 OTG_VERTICAL_INTERRUPT1_INT_STATUS 16 16 OTG_VERTICAL_INTERRUPT1_CLEAR 20 20 OTG_VERTICAL_INTERRUPT1_INT_TYPE 24 24 regOTG2_OTG_VERTICAL_INTERRUPT2_POSITION 0 0x1c66 1 0 2 OTG_VERTICAL_INTERRUPT2_LINE_START 0 14 regOTG2_OTG_VERTICAL_INTERRUPT2_CONTROL 0 0x1c67 5 0 2 OTG_VERTICAL_INTERRUPT2_INT_ENABLE 8 8 OTG_VERTICAL_INTERRUPT2_STATUS 12 12 OTG_VERTICAL_INTERRUPT2_INT_STATUS 16 16 OTG_VERTICAL_INTERRUPT2_CLEAR 20 20 OTG_VERTICAL_INTERRUPT2_INT_TYPE 24 24 regOTG2_OTG_CRC_CNTL 0 0x1c68 16 0 2 OTG_CRC_EN 0 0 OTG_CRC_DUAL_LINK_EN 1 1 OTG_CRC_DUAL_LINK_MODE 2 2 OTG_CRC_BLANK_ONLY 3 3 OTG_CRC_CONT_EN 4 4 OTG_CRC_CAPTURE_START_SEL 5 6 OTG_CRC1_EN 7 7 OTG_CRC_STEREO_MODE 8 9 OTG_CRC_INTERLACE_MODE 12 13 OTG_CRC_USE_NEW_AND_REPEATED_PIXELS 19 19 OTG_CRC0_SELECT 20 22 OTG_CRC1_SELECT 24 26 OTG_ONE_SHOT_CRC0_PENDING 28 28 OTG_ONE_SHOT_CRC1_PENDING 29 29 OTG_ONE_SHOT_CRC2_PENDING 30 30 OTG_ONE_SHOT_CRC3_PENDING 31 31 regOTG2_OTG_CRC_CNTL2 0 0x1c69 4 0 2 OTG_CRC_DSC_MODE 0 0 OTG_CRC_DATA_STREAM_COMBINE_MODE 1 1 OTG_CRC_DATA_STREAM_SPLIT_MODE 4 5 OTG_CRC_DATA_FORMAT 8 9 regOTG2_OTG_CRC0_WINDOWA_X_CONTROL 0 0x1c6a 2 0 2 OTG_CRC0_WINDOWA_X_START 0 14 OTG_CRC0_WINDOWA_X_END 16 30 regOTG2_OTG_CRC0_WINDOWA_Y_CONTROL 0 0x1c6b 2 0 2 OTG_CRC0_WINDOWA_Y_START 0 14 OTG_CRC0_WINDOWA_Y_END 16 30 regOTG2_OTG_CRC0_WINDOWB_X_CONTROL 0 0x1c6c 2 0 2 OTG_CRC0_WINDOWB_X_START 0 14 OTG_CRC0_WINDOWB_X_END 16 30 regOTG2_OTG_CRC0_WINDOWB_Y_CONTROL 0 0x1c6d 2 0 2 OTG_CRC0_WINDOWB_Y_START 0 14 OTG_CRC0_WINDOWB_Y_END 16 30 regOTG2_OTG_CRC0_DATA_RG 0 0x1c6e 2 0 2 CRC0_R_CR 0 15 CRC0_G_Y 16 31 regOTG2_OTG_CRC0_DATA_B 0 0x1c6f 2 0 2 CRC0_B_CB 0 15 CRC0_C 16 31 regOTG2_OTG_CRC1_WINDOWA_X_CONTROL 0 0x1c70 2 0 2 OTG_CRC1_WINDOWA_X_START 0 14 OTG_CRC1_WINDOWA_X_END 16 30 regOTG2_OTG_CRC1_WINDOWA_Y_CONTROL 0 0x1c71 2 0 2 OTG_CRC1_WINDOWA_Y_START 0 14 OTG_CRC1_WINDOWA_Y_END 16 30 regOTG2_OTG_CRC1_WINDOWB_X_CONTROL 0 0x1c72 2 0 2 OTG_CRC1_WINDOWB_X_START 0 14 OTG_CRC1_WINDOWB_X_END 16 30 regOTG2_OTG_CRC1_WINDOWB_Y_CONTROL 0 0x1c73 2 0 2 OTG_CRC1_WINDOWB_Y_START 0 14 OTG_CRC1_WINDOWB_Y_END 16 30 regOTG2_OTG_CRC1_DATA_RG 0 0x1c74 2 0 2 CRC1_R_CR 0 15 CRC1_G_Y 16 31 regOTG2_OTG_CRC1_DATA_B 0 0x1c75 2 0 2 CRC1_B_CB 0 15 CRC1_C 16 31 regOTG2_OTG_CRC2_DATA_RG 0 0x1c76 2 0 2 CRC2_R_CR 0 15 CRC2_G_Y 16 31 regOTG2_OTG_CRC2_DATA_B 0 0x1c77 2 0 2 CRC2_B_CB 0 15 CRC2_C 16 31 regOTG2_OTG_CRC3_DATA_RG 0 0x1c78 2 0 2 CRC3_R_CR 0 15 CRC3_G_Y 16 31 regOTG2_OTG_CRC3_DATA_B 0 0x1c79 2 0 2 CRC3_B_CB 0 15 CRC3_C 16 31 regOTG2_OTG_CRC_SIG_RED_GREEN_MASK 0 0x1c7a 2 0 2 OTG_CRC_SIG_RED_MASK 0 15 OTG_CRC_SIG_GREEN_MASK 16 31 regOTG2_OTG_CRC_SIG_BLUE_CONTROL_MASK 0 0x1c7b 2 0 2 OTG_CRC_SIG_BLUE_MASK 0 15 OTG_CRC_SIG_CONTROL_MASK 16 31 regOTG2_OTG_STATIC_SCREEN_CONTROL 0 0x1c82 9 0 2 OTG_STATIC_SCREEN_EVENT_MASK 0 15 OTG_STATIC_SCREEN_FRAME_COUNT 16 23 OTG_CPU_SS_INT_ENABLE 24 24 OTG_SS_STATUS 25 25 OTG_CPU_SS_INT_STATUS 26 26 OTG_CPU_SS_INT_CLEAR 27 27 OTG_CPU_SS_INT_TYPE 28 28 OTG_STATIC_SCREEN_OVERRIDE 30 30 OTG_STATIC_SCREEN_OVERRIDE_VALUE 31 31 regOTG2_OTG_3D_STRUCTURE_CONTROL 0 0x1c83 6 0 2 OTG_3D_STRUCTURE_EN 0 0 OTG_3D_STRUCTURE_V_UPDATE_MODE 8 9 OTG_3D_STRUCTURE_STEREO_SEL_OVR 12 12 OTG_3D_STRUCTURE_F_COUNT_RESET 16 16 OTG_3D_STRUCTURE_F_COUNT_RESET_PENDING 17 17 OTG_3D_STRUCTURE_F_COUNT 18 19 regOTG2_OTG_GSL_VSYNC_GAP 0 0x1c84 8 0 2 OTG_GSL_VSYNC_GAP_LIMIT 0 7 OTG_GSL_VSYNC_GAP_DELAY 8 15 OTG_GSL_VSYNC_GAP_SOURCE_SEL 16 16 OTG_GSL_VSYNC_GAP_MODE 17 18 OTG_GSL_VSYNC_GAP_CLEAR 19 19 OTG_GSL_VSYNC_GAP_OCCURRED 20 20 OTG_GSL_VSYNC_GAP_MASTER_FASTER 23 23 OTG_GSL_VSYNC_GAP 24 31 regOTG2_OTG_MASTER_UPDATE_MODE 0 0x1c85 1 0 2 MASTER_UPDATE_INTERLACED_MODE 0 1 regOTG2_OTG_CLOCK_CONTROL 0 0x1c86 5 0 2 OTG_CLOCK_EN 0 0 OTG_CLOCK_GATE_DIS 1 1 OTG_SOFT_RESET 4 4 OTG_CLOCK_ON 8 8 OTG_BUSY 16 16 regOTG2_OTG_VSTARTUP_PARAM 0 0x1c87 1 0 2 VSTARTUP_START 0 9 regOTG2_OTG_VUPDATE_PARAM 0 0x1c88 2 0 2 VUPDATE_OFFSET 0 15 VUPDATE_WIDTH 16 25 regOTG2_OTG_VREADY_PARAM 0 0x1c89 1 0 2 VREADY_OFFSET 0 15 regOTG2_OTG_GLOBAL_SYNC_STATUS 0 0x1c8a 25 0 2 VSTARTUP_INT_EN 0 0 VSTARTUP_INT_TYPE 1 1 VSTARTUP_EVENT_OCCURRED 2 2 VSTARTUP_INT_STATUS 3 3 VSTARTUP_EVENT_CLEAR 4 4 VUPDATE_INT_EN 5 5 VUPDATE_INT_TYPE 6 6 VUPDATE_INT_POSITION_SEL 7 7 VUPDATE_EVENT_OCCURRED 8 8 VUPDATE_INT_STATUS 9 9 VUPDATE_EVENT_CLEAR 10 10 VUPDATE_STATUS 11 11 VUPDATE_NO_LOCK_INT_EN 12 12 VUPDATE_NO_LOCK_INT_TYPE 13 13 VUPDATE_NO_LOCK_EVENT_OCCURRED 14 14 VUPDATE_NO_LOCK_INT_STATUS 15 15 VUPDATE_NO_LOCK_EVENT_CLEAR 16 16 VUPDATE_NO_LOCK_STATUS 17 17 VREADY_INT_EN 18 18 VREADY_INT_TYPE 19 19 VREADY_EVENT_OCCURRED 20 20 VREADY_INT_STATUS 21 21 VREADY_EVENT_CLEAR 22 22 STEREO_SELECT_STATUS 24 24 FIELD_NUMBER_STATUS 25 25 regOTG2_OTG_MASTER_UPDATE_LOCK 0 0x1c8b 2 0 2 OTG_MASTER_UPDATE_LOCK 0 0 UPDATE_LOCK_STATUS 8 8 regOTG2_OTG_GSL_CONTROL 0 0x1c8c 9 0 2 OTG_GSL0_EN 0 0 OTG_GSL1_EN 1 1 OTG_GSL2_EN 2 2 OTG_GSL_MASTER_EN 3 3 OTG_GSL_MASTER_MODE 4 5 OTG_GSL_CHECK_DELAY 8 11 OTG_GSL_FORCE_DELAY 16 20 OTG_GSL_CHECK_ALL_FIELDS 28 28 OTG_MASTER_UPDATE_LOCK_GSL_EN 31 31 regOTG2_OTG_GSL_WINDOW_X 0 0x1c8d 2 0 2 OTG_GSL_WINDOW_START_X 0 14 OTG_GSL_WINDOW_END_X 16 30 regOTG2_OTG_GSL_WINDOW_Y 0 0x1c8e 2 0 2 OTG_GSL_WINDOW_START_Y 0 14 OTG_GSL_WINDOW_END_Y 16 30 regOTG2_OTG_VUPDATE_KEEPOUT 0 0x1c8f 3 0 2 MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_START_OFFSET 0 15 MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_END_OFFSET 16 25 OTG_MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_EN 31 31 regOTG2_OTG_GLOBAL_CONTROL0 0 0x1c90 3 0 2 MASTER_UPDATE_LOCK_DB_START_X 0 14 MASTER_UPDATE_LOCK_DB_END_X 16 30 MASTER_UPDATE_LOCK_DB_EN 31 31 regOTG2_OTG_GLOBAL_CONTROL1 0 0x1c91 3 0 2 MASTER_UPDATE_LOCK_DB_START_Y 0 14 MASTER_UPDATE_LOCK_DB_END_Y 16 30 MASTER_UPDATE_LOCK_VCOUNT_MODE 31 31 regOTG2_OTG_GLOBAL_CONTROL2 0 0x1c92 5 0 2 GLOBAL_UPDATE_LOCK_EN 10 10 MANUAL_FLOW_CONTROL_SEL 16 18 OTG_MASTER_UPDATE_LOCK_SEL 25 27 OTG_VUPDATE_BLOCK_DISABLE 30 30 DCCG_VUPDATE_MODE 31 31 regOTG2_OTG_GLOBAL_CONTROL3 0 0x1c93 4 0 2 MASTER_UPDATE_LOCK_DB_FIELD 0 1 MASTER_UPDATE_LOCK_DB_STEREO_SEL 4 5 DIG_UPDATE_FIELD_SEL 16 17 DIG_UPDATE_EYE_SEL 20 21 regOTG2_OTG_GLOBAL_CONTROL4 0 0x1c94 3 0 2 DIG_UPDATE_POSITION_X 0 14 DIG_UPDATE_POSITION_Y 16 30 DIG_UPDATE_VCOUNT_MODE 31 31 regOTG2_OTG_TRIG_MANUAL_CONTROL 0 0x1c95 1 0 2 TRIG_MANUAL_CONTROL 0 0 regOTG2_OTG_MANUAL_FLOW_CONTROL 0 0x1c96 1 0 2 MANUAL_FLOW_CONTROL 0 0 regOTG2_OTG_DRR_TIMING_INT_STATUS 0 0x1c97 10 0 2 OTG_DRR_TIMING_UPDATE_OCCURRED 0 0 OTG_DRR_TIMING_UPDATE_OCCURRED_INT 4 4 OTG_DRR_TIMING_UPDATE_OCCURRED_CLEAR 8 8 OTG_DRR_TIMING_UPDATE_OCCURRED_INT_MSK 12 12 OTG_DRR_TIMING_UPDATE_OCCURRED_INT_TYPE 13 13 OTG_DRR_V_TOTAL_REACH_OCCURRED 16 16 OTG_DRR_V_TOTAL_REACH_OCCURRED_INT 20 20 OTG_DRR_V_TOTAL_REACH_OCCURRED_CLEAR 24 24 OTG_DRR_V_TOTAL_REACH_OCCURRED_INT_MSK 28 28 OTG_DRR_V_TOTAL_REACH_OCCURRED_INT_TYPE 29 29 regOTG2_OTG_DRR_V_TOTAL_REACH_RANGE 0 0x1c98 2 0 2 OTG_DRR_V_TOTAL_REACH_LOWER_RANGE 0 14 OTG_DRR_V_TOTAL_REACH_UPPER_RANGE 16 30 regOTG2_OTG_DRR_V_TOTAL_CHANGE 0 0x1c99 1 0 2 OTG_DRR_V_TOTAL_CHANGE_LIMIT 0 14 regOTG2_OTG_DRR_TRIGGER_WINDOW 0 0x1c9a 2 0 2 OTG_DRR_TRIGGER_WINDOW_START_X 0 14 OTG_DRR_TRIGGER_WINDOW_END_X 16 30 regOTG2_OTG_DRR_CONTROL 0 0x1c9b 2 0 2 OTG_DRR_AVERAGE_FRAME 0 1 OTG_V_TOTAL_LAST_USED_BY_DRR 16 30 regOTG2_OTG_M_CONST_DTO0 0 0x1c9c 1 0 2 OTG_M_CONST_DTO_PHASE 0 31 regOTG2_OTG_M_CONST_DTO1 0 0x1c9d 1 0 2 OTG_M_CONST_DTO_MODULO 0 31 regOTG2_OTG_REQUEST_CONTROL 0 0x1c9e 1 0 2 OTG_REQUEST_MODE_FOR_H_DUPLICATE 0 0 regOTG2_OTG_DSC_START_POSITION 0 0x1c9f 2 0 2 OTG_DSC_START_POSITION_X 0 14 OTG_DSC_START_POSITION_LINE_NUM 16 25 regOTG2_OTG_PIPE_UPDATE_STATUS 0 0x1ca0 4 0 2 OTG_FLIP_PENDING 0 0 OTG_DC_REG_UPDATE_PENDING 4 4 OTG_CURSOR_UPDATE_PENDING 8 8 OTG_VUPDATE_KEEPOUT_STATUS 16 16 regOTG2_OTG_SPARE_REGISTER 0 0x1ca2 1 0 2 OTG_SPARE_REG 0 31 regOTG3_OTG_H_TOTAL 0 0x1caa 1 0 2 OTG_H_TOTAL 0 14 regOTG3_OTG_H_BLANK_START_END 0 0x1cab 2 0 2 OTG_H_BLANK_START 0 14 OTG_H_BLANK_END 16 30 regOTG3_OTG_H_SYNC_A 0 0x1cac 2 0 2 OTG_H_SYNC_A_START 0 14 OTG_H_SYNC_A_END 16 30 regOTG3_OTG_H_SYNC_A_CNTL 0 0x1cad 3 0 2 OTG_H_SYNC_A_POL 0 0 OTG_COMP_SYNC_A_EN 16 16 OTG_H_SYNC_A_CUTOFF 17 17 regOTG3_OTG_H_TIMING_CNTL 0 0x1cae 2 0 2 OTG_H_TIMING_DIV_MODE 0 1 OTG_H_TIMING_DIV_UPDATE_MODE 8 8 regOTG3_OTG_V_TOTAL 0 0x1caf 1 0 2 OTG_V_TOTAL 0 14 regOTG3_OTG_V_TOTAL_MIN 0 0x1cb0 1 0 2 OTG_V_TOTAL_MIN 0 14 regOTG3_OTG_V_TOTAL_MAX 0 0x1cb1 1 0 2 OTG_V_TOTAL_MAX 0 14 regOTG3_OTG_V_TOTAL_MID 0 0x1cb2 1 0 2 OTG_V_TOTAL_MID 0 14 regOTG3_OTG_V_TOTAL_CONTROL 0 0x1cb3 8 0 2 OTG_V_TOTAL_MIN_SEL 0 0 OTG_V_TOTAL_MAX_SEL 1 1 OTG_VTOTAL_MID_REPLACING_MAX_EN 2 2 OTG_VTOTAL_MID_REPLACING_MIN_EN 3 3 OTG_FORCE_LOCK_ON_EVENT 4 4 OTG_DRR_EVENT_ACTIVE_PERIOD 5 5 OTG_VTOTAL_MID_FRAME_NUM 8 15 OTG_SET_V_TOTAL_MIN_MASK 16 31 regOTG3_OTG_V_TOTAL_INT_STATUS 0 0x1cb4 4 0 2 OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED 0 0 OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_INT 4 4 OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_ACK 8 8 OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_MSK 12 12 regOTG3_OTG_VSYNC_NOM_INT_STATUS 0 0x1cb5 2 0 2 OTG_VSYNC_NOM 0 0 OTG_VSYNC_NOM_INT_CLEAR 4 4 regOTG3_OTG_V_BLANK_START_END 0 0x1cb6 2 0 2 OTG_V_BLANK_START 0 14 OTG_V_BLANK_END 16 30 regOTG3_OTG_V_SYNC_A 0 0x1cb7 2 0 2 OTG_V_SYNC_A_START 0 14 OTG_V_SYNC_A_END 16 30 regOTG3_OTG_V_SYNC_A_CNTL 0 0x1cb8 2 0 2 OTG_V_SYNC_A_POL 0 0 OTG_V_SYNC_MODE 8 8 regOTG3_OTG_TRIGA_CNTL 0 0x1cb9 12 0 2 OTG_TRIGA_SOURCE_SELECT 0 4 OTG_TRIGA_SOURCE_PIPE_SELECT 5 7 OTG_TRIGA_POLARITY_SELECT 8 10 OTG_TRIGA_RESYNC_BYPASS_EN 11 11 OTG_TRIGA_INPUT_STATUS 12 12 OTG_TRIGA_POLARITY_STATUS 13 13 OTG_TRIGA_OCCURRED 14 14 OTG_TRIGA_RISING_EDGE_DETECT_CNTL 16 17 OTG_TRIGA_FALLING_EDGE_DETECT_CNTL 18 19 OTG_TRIGA_FREQUENCY_SELECT 20 21 OTG_TRIGA_DELAY 24 28 OTG_TRIGA_CLEAR 31 31 regOTG3_OTG_TRIGA_MANUAL_TRIG 0 0x1cba 1 0 2 OTG_TRIGA_MANUAL_TRIG 0 0 regOTG3_OTG_TRIGB_CNTL 0 0x1cbb 12 0 2 OTG_TRIGB_SOURCE_SELECT 0 4 OTG_TRIGB_SOURCE_PIPE_SELECT 5 7 OTG_TRIGB_POLARITY_SELECT 8 10 OTG_TRIGB_RESYNC_BYPASS_EN 11 11 OTG_TRIGB_INPUT_STATUS 12 12 OTG_TRIGB_POLARITY_STATUS 13 13 OTG_TRIGB_OCCURRED 14 14 OTG_TRIGB_RISING_EDGE_DETECT_CNTL 16 17 OTG_TRIGB_FALLING_EDGE_DETECT_CNTL 18 19 OTG_TRIGB_FREQUENCY_SELECT 20 21 OTG_TRIGB_DELAY 24 28 OTG_TRIGB_CLEAR 31 31 regOTG3_OTG_TRIGB_MANUAL_TRIG 0 0x1cbc 1 0 2 OTG_TRIGB_MANUAL_TRIG 0 0 regOTG3_OTG_FORCE_COUNT_NOW_CNTL 0 0x1cbd 5 0 2 OTG_FORCE_COUNT_NOW_MODE 0 1 OTG_FORCE_COUNT_NOW_CHECK 4 4 OTG_FORCE_COUNT_NOW_TRIG_SEL 8 8 OTG_FORCE_COUNT_NOW_OCCURRED 16 16 OTG_FORCE_COUNT_NOW_CLEAR 24 24 regOTG3_OTG_FLOW_CONTROL 0 0x1cbe 4 0 2 OTG_FLOW_CONTROL_SOURCE_SELECT 0 4 OTG_FLOW_CONTROL_POLARITY 8 8 OTG_FLOW_CONTROL_GRANULARITY 16 16 OTG_FLOW_CONTROL_INPUT_STATUS 24 24 regOTG3_OTG_STEREO_FORCE_NEXT_EYE 0 0x1cbf 1 0 2 OTG_STEREO_FORCE_NEXT_EYE 0 1 regOTG3_OTG_CONTROL 0 0x1cc1 7 0 2 OTG_MASTER_EN 0 0 OTG_DISABLE_POINT_CNTL 8 9 OTG_START_POINT_CNTL 12 12 OTG_FIELD_NUMBER_CNTL 13 13 OTG_FIELD_NUMBER_POLARITY 14 14 OTG_CURRENT_MASTER_EN_STATE 16 16 OTG_OUT_MUX 20 21 regOTG3_OTG_INTERLACE_CONTROL 0 0x1cc4 2 0 2 OTG_INTERLACE_ENABLE 0 0 OTG_INTERLACE_FORCE_NEXT_FIELD 16 17 regOTG3_OTG_INTERLACE_STATUS 0 0x1cc5 2 0 2 OTG_INTERLACE_CURRENT_FIELD 0 0 OTG_INTERLACE_NEXT_FIELD 1 1 regOTG3_OTG_PIXEL_DATA_READBACK0 0 0x1cc7 2 0 2 OTG_PIXEL_DATA_BLUE_CB 0 15 OTG_PIXEL_DATA_GREEN_Y 16 31 regOTG3_OTG_PIXEL_DATA_READBACK1 0 0x1cc8 1 0 2 OTG_PIXEL_DATA_RED_CR 0 15 regOTG3_OTG_STATUS 0 0x1cc9 8 0 2 OTG_V_BLANK 0 0 OTG_V_ACTIVE_DISP 1 1 OTG_V_SYNC_A 2 2 OTG_V_UPDATE 3 3 OTG_V_BLANK_3D_STRUCTURE 5 5 OTG_H_BLANK 16 16 OTG_H_ACTIVE_DISP 17 17 OTG_H_SYNC_A 18 18 regOTG3_OTG_STATUS_POSITION 0 0x1cca 2 0 2 OTG_VERT_COUNT 0 14 OTG_HORZ_COUNT 16 30 regOTG3_OTG_NOM_VERT_POSITION 0 0x1ccb 1 0 2 OTG_VERT_COUNT_NOM 0 14 regOTG3_OTG_STATUS_FRAME_COUNT 0 0x1ccc 1 0 2 OTG_FRAME_COUNT 0 23 regOTG3_OTG_STATUS_VF_COUNT 0 0x1ccd 1 0 2 OTG_VF_COUNT 0 30 regOTG3_OTG_STATUS_HV_COUNT 0 0x1cce 1 0 2 OTG_HV_COUNT 0 30 regOTG3_OTG_COUNT_CONTROL 0 0x1ccf 2 0 2 OTG_HORZ_COUNT_BY2_EN 0 0 OTG_HORZ_REPETITION_COUNT 1 4 regOTG3_OTG_COUNT_RESET 0 0x1cd0 1 0 2 OTG_RESET_FRAME_COUNT 0 0 regOTG3_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE 0 0x1cd1 1 0 2 OTG_MANUAL_FORCE_VSYNC_NEXT_LINE 0 0 regOTG3_OTG_VERT_SYNC_CONTROL 0 0x1cd2 3 0 2 OTG_FORCE_VSYNC_NEXT_LINE_OCCURRED 0 0 OTG_FORCE_VSYNC_NEXT_LINE_CLEAR 8 8 OTG_AUTO_FORCE_VSYNC_MODE 16 17 regOTG3_OTG_STEREO_STATUS 0 0x1cd3 7 0 2 OTG_STEREO_CURRENT_EYE 0 0 OTG_STEREO_SYNC_OUTPUT 8 8 OTG_STEREO_SYNC_SELECT 16 16 OTG_STEREO_EYE_FLAG 20 20 OTG_STEREO_FORCE_NEXT_EYE_PENDING 24 25 OTG_CURRENT_3D_STRUCTURE_STATE 30 30 OTG_CURRENT_STEREOSYNC_EN_STATE 31 31 regOTG3_OTG_STEREO_CONTROL 0 0x1cd4 8 0 2 OTG_STEREO_SYNC_OUTPUT_LINE_NUM 0 14 OTG_STEREO_SYNC_OUTPUT_POLARITY 15 15 OTG_STEREO_EYE_FLAG_POLARITY 17 17 OTG_DISABLE_STEREOSYNC_OUTPUT_FOR_DP 18 18 OTG_DISABLE_FIELD_NUM 19 19 OTG_DISABLE_V_BLANK_FOR_DP_FIX 20 20 OTG_FIELD_NUM_SEL 21 21 OTG_STEREO_EN 24 24 regOTG3_OTG_SNAPSHOT_STATUS 0 0x1cd5 3 0 2 OTG_SNAPSHOT_OCCURRED 0 0 OTG_SNAPSHOT_CLEAR 1 1 OTG_SNAPSHOT_MANUAL_TRIGGER 2 2 regOTG3_OTG_SNAPSHOT_CONTROL 0 0x1cd6 1 0 2 OTG_AUTO_SNAPSHOT_TRIG_SEL 0 1 regOTG3_OTG_SNAPSHOT_POSITION 0 0x1cd7 2 0 2 OTG_SNAPSHOT_VERT_COUNT 0 14 OTG_SNAPSHOT_HORZ_COUNT 16 30 regOTG3_OTG_SNAPSHOT_FRAME 0 0x1cd8 1 0 2 OTG_SNAPSHOT_FRAME_COUNT 0 23 regOTG3_OTG_UPDATE_LOCK 0 0x1cda 1 0 2 OTG_UPDATE_LOCK 0 0 regOTG3_OTG_DOUBLE_BUFFER_CONTROL 0 0x1cdb 10 0 2 OTG_UPDATE_PENDING 0 0 OTG_H_TIMING_DIV_MODE_DB_UPDATE_PENDING 2 2 OTG_DRR_TIMING_DBUF_UPDATE_PENDING 4 4 OTG_TIMING_DB_UPDATE_PENDING 5 5 OTG_3D_CTRL_DB_UPDATE_PENDING 6 6 OTG_3D_STRUCTURE_EN_DB_UPDATE_PENDING 7 7 OTG_UPDATE_INSTANTLY 8 8 OTG_VSTARTUP_DB_UPDATE_PENDING 9 9 OTG_DSC_POSITION_DB_UPDATE_PENDING 10 10 OTG_DRR_TIMING_DBUF_UPDATE_MODE 24 25 regOTG3_OTG_MASTER_EN 0 0x1cdc 1 0 2 OTG_MASTER_EN 0 0 regOTG3_OTG_VERTICAL_INTERRUPT0_POSITION 0 0x1ce2 2 0 2 OTG_VERTICAL_INTERRUPT0_LINE_START 0 14 OTG_VERTICAL_INTERRUPT0_LINE_END 16 30 regOTG3_OTG_VERTICAL_INTERRUPT0_CONTROL 0 0x1ce3 7 0 2 OTG_VERTICAL_INTERRUPT0_OUTPUT_POLARITY 4 4 OTG_VERTICAL_INTERRUPT0_INT_ENABLE 8 8 OTG_VERTICAL_INTERRUPT0_STATUS 12 12 OTG_VERTICAL_INTERRUPT0_INT_STATUS 16 16 OTG_VERTICAL_INTERRUPT0_CLEAR 20 20 OTG_VERTICAL_INTERRUPT0_INT_TYPE 24 24 OTG_VINTE_STATUS 28 28 regOTG3_OTG_VERTICAL_INTERRUPT1_POSITION 0 0x1ce4 1 0 2 OTG_VERTICAL_INTERRUPT1_LINE_START 0 14 regOTG3_OTG_VERTICAL_INTERRUPT1_CONTROL 0 0x1ce5 5 0 2 OTG_VERTICAL_INTERRUPT1_INT_ENABLE 8 8 OTG_VERTICAL_INTERRUPT1_STATUS 12 12 OTG_VERTICAL_INTERRUPT1_INT_STATUS 16 16 OTG_VERTICAL_INTERRUPT1_CLEAR 20 20 OTG_VERTICAL_INTERRUPT1_INT_TYPE 24 24 regOTG3_OTG_VERTICAL_INTERRUPT2_POSITION 0 0x1ce6 1 0 2 OTG_VERTICAL_INTERRUPT2_LINE_START 0 14 regOTG3_OTG_VERTICAL_INTERRUPT2_CONTROL 0 0x1ce7 5 0 2 OTG_VERTICAL_INTERRUPT2_INT_ENABLE 8 8 OTG_VERTICAL_INTERRUPT2_STATUS 12 12 OTG_VERTICAL_INTERRUPT2_INT_STATUS 16 16 OTG_VERTICAL_INTERRUPT2_CLEAR 20 20 OTG_VERTICAL_INTERRUPT2_INT_TYPE 24 24 regOTG3_OTG_CRC_CNTL 0 0x1ce8 16 0 2 OTG_CRC_EN 0 0 OTG_CRC_DUAL_LINK_EN 1 1 OTG_CRC_DUAL_LINK_MODE 2 2 OTG_CRC_BLANK_ONLY 3 3 OTG_CRC_CONT_EN 4 4 OTG_CRC_CAPTURE_START_SEL 5 6 OTG_CRC1_EN 7 7 OTG_CRC_STEREO_MODE 8 9 OTG_CRC_INTERLACE_MODE 12 13 OTG_CRC_USE_NEW_AND_REPEATED_PIXELS 19 19 OTG_CRC0_SELECT 20 22 OTG_CRC1_SELECT 24 26 OTG_ONE_SHOT_CRC0_PENDING 28 28 OTG_ONE_SHOT_CRC1_PENDING 29 29 OTG_ONE_SHOT_CRC2_PENDING 30 30 OTG_ONE_SHOT_CRC3_PENDING 31 31 regOTG3_OTG_CRC_CNTL2 0 0x1ce9 4 0 2 OTG_CRC_DSC_MODE 0 0 OTG_CRC_DATA_STREAM_COMBINE_MODE 1 1 OTG_CRC_DATA_STREAM_SPLIT_MODE 4 5 OTG_CRC_DATA_FORMAT 8 9 regOTG3_OTG_CRC0_WINDOWA_X_CONTROL 0 0x1cea 2 0 2 OTG_CRC0_WINDOWA_X_START 0 14 OTG_CRC0_WINDOWA_X_END 16 30 regOTG3_OTG_CRC0_WINDOWA_Y_CONTROL 0 0x1ceb 2 0 2 OTG_CRC0_WINDOWA_Y_START 0 14 OTG_CRC0_WINDOWA_Y_END 16 30 regOTG3_OTG_CRC0_WINDOWB_X_CONTROL 0 0x1cec 2 0 2 OTG_CRC0_WINDOWB_X_START 0 14 OTG_CRC0_WINDOWB_X_END 16 30 regOTG3_OTG_CRC0_WINDOWB_Y_CONTROL 0 0x1ced 2 0 2 OTG_CRC0_WINDOWB_Y_START 0 14 OTG_CRC0_WINDOWB_Y_END 16 30 regOTG3_OTG_CRC0_DATA_RG 0 0x1cee 2 0 2 CRC0_R_CR 0 15 CRC0_G_Y 16 31 regOTG3_OTG_CRC0_DATA_B 0 0x1cef 2 0 2 CRC0_B_CB 0 15 CRC0_C 16 31 regOTG3_OTG_CRC1_WINDOWA_X_CONTROL 0 0x1cf0 2 0 2 OTG_CRC1_WINDOWA_X_START 0 14 OTG_CRC1_WINDOWA_X_END 16 30 regOTG3_OTG_CRC1_WINDOWA_Y_CONTROL 0 0x1cf1 2 0 2 OTG_CRC1_WINDOWA_Y_START 0 14 OTG_CRC1_WINDOWA_Y_END 16 30 regOTG3_OTG_CRC1_WINDOWB_X_CONTROL 0 0x1cf2 2 0 2 OTG_CRC1_WINDOWB_X_START 0 14 OTG_CRC1_WINDOWB_X_END 16 30 regOTG3_OTG_CRC1_WINDOWB_Y_CONTROL 0 0x1cf3 2 0 2 OTG_CRC1_WINDOWB_Y_START 0 14 OTG_CRC1_WINDOWB_Y_END 16 30 regOTG3_OTG_CRC1_DATA_RG 0 0x1cf4 2 0 2 CRC1_R_CR 0 15 CRC1_G_Y 16 31 regOTG3_OTG_CRC1_DATA_B 0 0x1cf5 2 0 2 CRC1_B_CB 0 15 CRC1_C 16 31 regOTG3_OTG_CRC2_DATA_RG 0 0x1cf6 2 0 2 CRC2_R_CR 0 15 CRC2_G_Y 16 31 regOTG3_OTG_CRC2_DATA_B 0 0x1cf7 2 0 2 CRC2_B_CB 0 15 CRC2_C 16 31 regOTG3_OTG_CRC3_DATA_RG 0 0x1cf8 2 0 2 CRC3_R_CR 0 15 CRC3_G_Y 16 31 regOTG3_OTG_CRC3_DATA_B 0 0x1cf9 2 0 2 CRC3_B_CB 0 15 CRC3_C 16 31 regOTG3_OTG_CRC_SIG_RED_GREEN_MASK 0 0x1cfa 2 0 2 OTG_CRC_SIG_RED_MASK 0 15 OTG_CRC_SIG_GREEN_MASK 16 31 regOTG3_OTG_CRC_SIG_BLUE_CONTROL_MASK 0 0x1cfb 2 0 2 OTG_CRC_SIG_BLUE_MASK 0 15 OTG_CRC_SIG_CONTROL_MASK 16 31 regOTG3_OTG_STATIC_SCREEN_CONTROL 0 0x1d02 9 0 2 OTG_STATIC_SCREEN_EVENT_MASK 0 15 OTG_STATIC_SCREEN_FRAME_COUNT 16 23 OTG_CPU_SS_INT_ENABLE 24 24 OTG_SS_STATUS 25 25 OTG_CPU_SS_INT_STATUS 26 26 OTG_CPU_SS_INT_CLEAR 27 27 OTG_CPU_SS_INT_TYPE 28 28 OTG_STATIC_SCREEN_OVERRIDE 30 30 OTG_STATIC_SCREEN_OVERRIDE_VALUE 31 31 regOTG3_OTG_3D_STRUCTURE_CONTROL 0 0x1d03 6 0 2 OTG_3D_STRUCTURE_EN 0 0 OTG_3D_STRUCTURE_V_UPDATE_MODE 8 9 OTG_3D_STRUCTURE_STEREO_SEL_OVR 12 12 OTG_3D_STRUCTURE_F_COUNT_RESET 16 16 OTG_3D_STRUCTURE_F_COUNT_RESET_PENDING 17 17 OTG_3D_STRUCTURE_F_COUNT 18 19 regOTG3_OTG_GSL_VSYNC_GAP 0 0x1d04 8 0 2 OTG_GSL_VSYNC_GAP_LIMIT 0 7 OTG_GSL_VSYNC_GAP_DELAY 8 15 OTG_GSL_VSYNC_GAP_SOURCE_SEL 16 16 OTG_GSL_VSYNC_GAP_MODE 17 18 OTG_GSL_VSYNC_GAP_CLEAR 19 19 OTG_GSL_VSYNC_GAP_OCCURRED 20 20 OTG_GSL_VSYNC_GAP_MASTER_FASTER 23 23 OTG_GSL_VSYNC_GAP 24 31 regOTG3_OTG_MASTER_UPDATE_MODE 0 0x1d05 1 0 2 MASTER_UPDATE_INTERLACED_MODE 0 1 regOTG3_OTG_CLOCK_CONTROL 0 0x1d06 5 0 2 OTG_CLOCK_EN 0 0 OTG_CLOCK_GATE_DIS 1 1 OTG_SOFT_RESET 4 4 OTG_CLOCK_ON 8 8 OTG_BUSY 16 16 regOTG3_OTG_VSTARTUP_PARAM 0 0x1d07 1 0 2 VSTARTUP_START 0 9 regOTG3_OTG_VUPDATE_PARAM 0 0x1d08 2 0 2 VUPDATE_OFFSET 0 15 VUPDATE_WIDTH 16 25 regOTG3_OTG_VREADY_PARAM 0 0x1d09 1 0 2 VREADY_OFFSET 0 15 regOTG3_OTG_GLOBAL_SYNC_STATUS 0 0x1d0a 25 0 2 VSTARTUP_INT_EN 0 0 VSTARTUP_INT_TYPE 1 1 VSTARTUP_EVENT_OCCURRED 2 2 VSTARTUP_INT_STATUS 3 3 VSTARTUP_EVENT_CLEAR 4 4 VUPDATE_INT_EN 5 5 VUPDATE_INT_TYPE 6 6 VUPDATE_INT_POSITION_SEL 7 7 VUPDATE_EVENT_OCCURRED 8 8 VUPDATE_INT_STATUS 9 9 VUPDATE_EVENT_CLEAR 10 10 VUPDATE_STATUS 11 11 VUPDATE_NO_LOCK_INT_EN 12 12 VUPDATE_NO_LOCK_INT_TYPE 13 13 VUPDATE_NO_LOCK_EVENT_OCCURRED 14 14 VUPDATE_NO_LOCK_INT_STATUS 15 15 VUPDATE_NO_LOCK_EVENT_CLEAR 16 16 VUPDATE_NO_LOCK_STATUS 17 17 VREADY_INT_EN 18 18 VREADY_INT_TYPE 19 19 VREADY_EVENT_OCCURRED 20 20 VREADY_INT_STATUS 21 21 VREADY_EVENT_CLEAR 22 22 STEREO_SELECT_STATUS 24 24 FIELD_NUMBER_STATUS 25 25 regOTG3_OTG_MASTER_UPDATE_LOCK 0 0x1d0b 2 0 2 OTG_MASTER_UPDATE_LOCK 0 0 UPDATE_LOCK_STATUS 8 8 regOTG3_OTG_GSL_CONTROL 0 0x1d0c 9 0 2 OTG_GSL0_EN 0 0 OTG_GSL1_EN 1 1 OTG_GSL2_EN 2 2 OTG_GSL_MASTER_EN 3 3 OTG_GSL_MASTER_MODE 4 5 OTG_GSL_CHECK_DELAY 8 11 OTG_GSL_FORCE_DELAY 16 20 OTG_GSL_CHECK_ALL_FIELDS 28 28 OTG_MASTER_UPDATE_LOCK_GSL_EN 31 31 regOTG3_OTG_GSL_WINDOW_X 0 0x1d0d 2 0 2 OTG_GSL_WINDOW_START_X 0 14 OTG_GSL_WINDOW_END_X 16 30 regOTG3_OTG_GSL_WINDOW_Y 0 0x1d0e 2 0 2 OTG_GSL_WINDOW_START_Y 0 14 OTG_GSL_WINDOW_END_Y 16 30 regOTG3_OTG_VUPDATE_KEEPOUT 0 0x1d0f 3 0 2 MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_START_OFFSET 0 15 MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_END_OFFSET 16 25 OTG_MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_EN 31 31 regOTG3_OTG_GLOBAL_CONTROL0 0 0x1d10 0 0 2 regOTG3_OTG_GLOBAL_CONTROL1 0 0x1d11 0 0 2 regOTG3_OTG_GLOBAL_CONTROL2 0 0x1d12 0 0 2 regOTG3_OTG_GLOBAL_CONTROL3 0 0x1d13 0 0 2 regOTG3_OTG_GLOBAL_CONTROL4 0 0x1d14 0 0 2 regOTG3_OTG_TRIG_MANUAL_CONTROL 0 0x1d15 1 0 2 TRIG_MANUAL_CONTROL 0 0 regOTG3_OTG_MANUAL_FLOW_CONTROL 0 0x1d16 1 0 2 MANUAL_FLOW_CONTROL 0 0 regOTG3_OTG_DRR_TIMING_INT_STATUS 0 0x1d17 10 0 2 OTG_DRR_TIMING_UPDATE_OCCURRED 0 0 OTG_DRR_TIMING_UPDATE_OCCURRED_INT 4 4 OTG_DRR_TIMING_UPDATE_OCCURRED_CLEAR 8 8 OTG_DRR_TIMING_UPDATE_OCCURRED_INT_MSK 12 12 OTG_DRR_TIMING_UPDATE_OCCURRED_INT_TYPE 13 13 OTG_DRR_V_TOTAL_REACH_OCCURRED 16 16 OTG_DRR_V_TOTAL_REACH_OCCURRED_INT 20 20 OTG_DRR_V_TOTAL_REACH_OCCURRED_CLEAR 24 24 OTG_DRR_V_TOTAL_REACH_OCCURRED_INT_MSK 28 28 OTG_DRR_V_TOTAL_REACH_OCCURRED_INT_TYPE 29 29 regOTG3_OTG_DRR_V_TOTAL_REACH_RANGE 0 0x1d18 2 0 2 OTG_DRR_V_TOTAL_REACH_LOWER_RANGE 0 14 OTG_DRR_V_TOTAL_REACH_UPPER_RANGE 16 30 regOTG3_OTG_DRR_V_TOTAL_CHANGE 0 0x1d19 1 0 2 OTG_DRR_V_TOTAL_CHANGE_LIMIT 0 14 regOTG3_OTG_DRR_TRIGGER_WINDOW 0 0x1d1a 2 0 2 OTG_DRR_TRIGGER_WINDOW_START_X 0 14 OTG_DRR_TRIGGER_WINDOW_END_X 16 30 regOTG3_OTG_DRR_CONTROL 0 0x1d1b 2 0 2 OTG_DRR_AVERAGE_FRAME 0 1 OTG_V_TOTAL_LAST_USED_BY_DRR 16 30 regOTG3_OTG_M_CONST_DTO0 0 0x1d1c 1 0 2 OTG_M_CONST_DTO_PHASE 0 31 regOTG3_OTG_M_CONST_DTO1 0 0x1d1d 1 0 2 OTG_M_CONST_DTO_MODULO 0 31 regOTG3_OTG_REQUEST_CONTROL 0 0x1d1e 1 0 2 OTG_REQUEST_MODE_FOR_H_DUPLICATE 0 0 regOTG3_OTG_DSC_START_POSITION 0 0x1d1f 2 0 2 OTG_DSC_START_POSITION_X 0 14 OTG_DSC_START_POSITION_LINE_NUM 16 25 regOTG3_OTG_PIPE_UPDATE_STATUS 0 0x1d20 4 0 2 OTG_FLIP_PENDING 0 0 OTG_DC_REG_UPDATE_PENDING 4 4 OTG_CURSOR_UPDATE_PENDING 8 8 OTG_VUPDATE_KEEPOUT_STATUS 16 16 regOTG3_OTG_SPARE_REGISTER 0 0x1d22 1 0 2 OTG_SPARE_REG 0 31 regDWB_SOURCE_SELECT 0 0x1e2a 3 0 2 OPTC_DWB0_SOURCE_SELECT 0 2 OPTC_DWB1_SOURCE_SELECT 3 5 OPTC_DWB2_SOURCE_SELECT 6 8 regGSL_SOURCE_SELECT 0 0x1e2b 4 0 2 GSL0_READY_SOURCE_SEL 0 2 GSL1_READY_SOURCE_SEL 4 6 GSL2_READY_SOURCE_SEL 8 10 GSL_TIMING_SYNC_SEL 16 18 regOPTC_CLOCK_CONTROL 0 0x1e2c 3 0 2 OPTC_DISPCLK_R_GATE_DIS 0 0 OPTC_DISPCLK_R_CLOCK_ON 1 1 OPTC_TEST_CLK_SEL 8 11 regODM_MEM_PWR_CTRL 0 0x1e2d 16 0 2 ODM_MEM0_PWR_FORCE 0 1 ODM_MEM0_PWR_DIS 2 2 ODM_MEM1_PWR_FORCE 4 5 ODM_MEM1_PWR_DIS 6 6 ODM_MEM2_PWR_FORCE 8 9 ODM_MEM2_PWR_DIS 10 10 ODM_MEM3_PWR_FORCE 12 13 ODM_MEM3_PWR_DIS 14 14 ODM_MEM4_PWR_FORCE 16 17 ODM_MEM4_PWR_DIS 18 18 ODM_MEM5_PWR_FORCE 20 21 ODM_MEM5_PWR_DIS 22 22 ODM_MEM6_PWR_FORCE 24 25 ODM_MEM6_PWR_DIS 26 26 ODM_MEM7_PWR_FORCE 28 29 ODM_MEM7_PWR_DIS 30 30 regODM_MEM_PWR_CTRL3 0 0x1e2f 2 0 2 ODM_MEM_UNASSIGNED_PWR_MODE 0 1 ODM_MEM_VBLANK_PWR_MODE 2 3 regODM_MEM_PWR_STATUS 0 0x1e30 8 0 2 ODM_MEM0_PWR_STATE 0 1 ODM_MEM1_PWR_STATE 2 3 ODM_MEM2_PWR_STATE 4 5 ODM_MEM3_PWR_STATE 6 7 ODM_MEM4_PWR_STATE 8 9 ODM_MEM5_PWR_STATE 10 11 ODM_MEM6_PWR_STATE 12 13 ODM_MEM7_PWR_STATE 14 15 regOPTC_MISC_SPARE_REGISTER 0 0x1e31 1 0 2 OPTC_MISC_SPARE_REG 0 7 regDC_PERFMON17_PERFCOUNTER_CNTL 0 0x1e6a 11 0 2 PERFCOUNTER_EVENT_SEL 0 8 PERFCOUNTER_CVALUE_SEL 9 11 PERFCOUNTER_INC_MODE 12 14 PERFCOUNTER_HW_CNTL_SEL 15 15 PERFCOUNTER_RUNEN_MODE 16 16 PERFCOUNTER_CNTOFF_START_DIS 22 22 PERFCOUNTER_RESTART_EN 23 23 PERFCOUNTER_INT_EN 24 24 PERFCOUNTER_OFF_MASK 25 25 PERFCOUNTER_ACTIVE 26 26 PERFCOUNTER_CNTL_SEL 29 31 regDC_PERFMON17_PERFCOUNTER_CNTL2 0 0x1e6b 5 0 2 PERFCOUNTER_COUNTED_VALUE_TYPE 0 1 PERFCOUNTER_HW_STOP1_SEL 2 2 PERFCOUNTER_HW_STOP2_SEL 3 3 PERFCOUNTER_CNTOFF_SEL 8 13 PERFCOUNTER_CNTL2_SEL 29 31 regDC_PERFMON17_PERFCOUNTER_STATE 0 0x1e6c 16 0 2 PERFCOUNTER_CNT0_STATE 0 1 PERFCOUNTER_STATE_SEL0 2 2 PERFCOUNTER_CNT1_STATE 4 5 PERFCOUNTER_STATE_SEL1 6 6 PERFCOUNTER_CNT2_STATE 8 9 PERFCOUNTER_STATE_SEL2 10 10 PERFCOUNTER_CNT3_STATE 12 13 PERFCOUNTER_STATE_SEL3 14 14 PERFCOUNTER_CNT4_STATE 16 17 PERFCOUNTER_STATE_SEL4 18 18 PERFCOUNTER_CNT5_STATE 20 21 PERFCOUNTER_STATE_SEL5 22 22 PERFCOUNTER_CNT6_STATE 24 25 PERFCOUNTER_STATE_SEL6 26 26 PERFCOUNTER_CNT7_STATE 28 29 PERFCOUNTER_STATE_SEL7 30 30 regDC_PERFMON17_PERFMON_CNTL 0 0x1e6d 6 0 2 PERFMON_STATE 0 1 PERFMON_RPT_COUNT 8 27 PERFMON_CNTOFF_AND_OR 28 28 PERFMON_CNTOFF_INT_EN 29 29 PERFMON_CNTOFF_INT_STATUS 30 30 PERFMON_CNTOFF_INT_ACK 31 31 regDC_PERFMON17_PERFMON_CNTL2 0 0x1e6e 4 0 2 PERFMON_CNTOFF_INT_TYPE 0 0 PERFMON_CLK_ENABLE 1 1 PERFMON_RUN_ENABLE_START_SEL 2 9 PERFMON_RUN_ENABLE_STOP_SEL 10 17 regDC_PERFMON17_PERFMON_CVALUE_INT_MISC 0 0x1e6f 17 0 2 PERFCOUNTER_INT0_STATUS 0 0 PERFCOUNTER_INT1_STATUS 1 1 PERFCOUNTER_INT2_STATUS 2 2 PERFCOUNTER_INT3_STATUS 3 3 PERFCOUNTER_INT4_STATUS 4 4 PERFCOUNTER_INT5_STATUS 5 5 PERFCOUNTER_INT6_STATUS 6 6 PERFCOUNTER_INT7_STATUS 7 7 PERFCOUNTER_INT0_ACK 8 8 PERFCOUNTER_INT1_ACK 9 9 PERFCOUNTER_INT2_ACK 10 10 PERFCOUNTER_INT3_ACK 11 11 PERFCOUNTER_INT4_ACK 12 12 PERFCOUNTER_INT5_ACK 13 13 PERFCOUNTER_INT6_ACK 14 14 PERFCOUNTER_INT7_ACK 15 15 PERFMON_CVALUE_HI 16 31 regDC_PERFMON17_PERFMON_CVALUE_LOW 0 0x1e70 1 0 2 PERFMON_CVALUE_LOW 0 31 regDC_PERFMON17_PERFMON_HI 0 0x1e71 2 0 2 PERFMON_HI 0 15 PERFMON_READ_SEL 29 31 regDC_PERFMON17_PERFMON_LOW 0 0x1e72 1 0 2 PERFMON_LOW 0 31 regHPD0_DC_HPD_INT_STATUS 0 0x1f14 6 0 2 DC_HPD_INT_STATUS 0 0 DC_HPD_SENSE 1 1 DC_HPD_SENSE_DELAYED 4 4 DC_HPD_RX_INT_STATUS 8 8 DC_HPD_TOGGLE_FILT_CON_TIMER_VAL 12 19 DC_HPD_TOGGLE_FILT_DISCON_TIMER_VAL 24 31 regHPD0_DC_HPD_INT_CONTROL 0 0x1f15 5 0 2 DC_HPD_INT_ACK 0 0 DC_HPD_INT_POLARITY 8 8 DC_HPD_INT_EN 16 16 DC_HPD_RX_INT_ACK 20 20 DC_HPD_RX_INT_EN 24 24 regHPD0_DC_HPD_CONTROL 0 0x1f16 3 0 2 DC_HPD_CONNECTION_TIMER 0 12 DC_HPD_RX_INT_TIMER 16 25 DC_HPD_EN 28 28 regHPD0_DC_HPD_FAST_TRAIN_CNTL 0 0x1f17 4 0 2 DC_HPD_CONNECT_AUX_TX_DELAY 0 7 DC_HPD_CONNECT_FAST_TRAIN_DELAY 12 19 DC_HPD_CONNECT_AUX_TX_EN 24 24 DC_HPD_CONNECT_FAST_TRAIN_EN 28 28 regHPD0_DC_HPD_TOGGLE_FILT_CNTL 0 0x1f18 2 0 2 DC_HPD_CONNECT_INT_DELAY 0 7 DC_HPD_DISCONNECT_INT_DELAY 20 27 regHPD1_DC_HPD_INT_STATUS 0 0x1f1c 6 0 2 DC_HPD_INT_STATUS 0 0 DC_HPD_SENSE 1 1 DC_HPD_SENSE_DELAYED 4 4 DC_HPD_RX_INT_STATUS 8 8 DC_HPD_TOGGLE_FILT_CON_TIMER_VAL 12 19 DC_HPD_TOGGLE_FILT_DISCON_TIMER_VAL 24 31 regHPD1_DC_HPD_INT_CONTROL 0 0x1f1d 5 0 2 DC_HPD_INT_ACK 0 0 DC_HPD_INT_POLARITY 8 8 DC_HPD_INT_EN 16 16 DC_HPD_RX_INT_ACK 20 20 DC_HPD_RX_INT_EN 24 24 regHPD1_DC_HPD_CONTROL 0 0x1f1e 3 0 2 DC_HPD_CONNECTION_TIMER 0 12 DC_HPD_RX_INT_TIMER 16 25 DC_HPD_EN 28 28 regHPD1_DC_HPD_FAST_TRAIN_CNTL 0 0x1f1f 4 0 2 DC_HPD_CONNECT_AUX_TX_DELAY 0 7 DC_HPD_CONNECT_FAST_TRAIN_DELAY 12 19 DC_HPD_CONNECT_AUX_TX_EN 24 24 DC_HPD_CONNECT_FAST_TRAIN_EN 28 28 regHPD1_DC_HPD_TOGGLE_FILT_CNTL 0 0x1f20 2 0 2 DC_HPD_CONNECT_INT_DELAY 0 7 DC_HPD_DISCONNECT_INT_DELAY 20 27 regHPD2_DC_HPD_INT_STATUS 0 0x1f24 6 0 2 DC_HPD_INT_STATUS 0 0 DC_HPD_SENSE 1 1 DC_HPD_SENSE_DELAYED 4 4 DC_HPD_RX_INT_STATUS 8 8 DC_HPD_TOGGLE_FILT_CON_TIMER_VAL 12 19 DC_HPD_TOGGLE_FILT_DISCON_TIMER_VAL 24 31 regHPD2_DC_HPD_INT_CONTROL 0 0x1f25 5 0 2 DC_HPD_INT_ACK 0 0 DC_HPD_INT_POLARITY 8 8 DC_HPD_INT_EN 16 16 DC_HPD_RX_INT_ACK 20 20 DC_HPD_RX_INT_EN 24 24 regHPD2_DC_HPD_CONTROL 0 0x1f26 3 0 2 DC_HPD_CONNECTION_TIMER 0 12 DC_HPD_RX_INT_TIMER 16 25 DC_HPD_EN 28 28 regHPD2_DC_HPD_FAST_TRAIN_CNTL 0 0x1f27 4 0 2 DC_HPD_CONNECT_AUX_TX_DELAY 0 7 DC_HPD_CONNECT_FAST_TRAIN_DELAY 12 19 DC_HPD_CONNECT_AUX_TX_EN 24 24 DC_HPD_CONNECT_FAST_TRAIN_EN 28 28 regHPD2_DC_HPD_TOGGLE_FILT_CNTL 0 0x1f28 2 0 2 DC_HPD_CONNECT_INT_DELAY 0 7 DC_HPD_DISCONNECT_INT_DELAY 20 27 regHPD3_DC_HPD_INT_STATUS 0 0x1f2c 6 0 2 DC_HPD_INT_STATUS 0 0 DC_HPD_SENSE 1 1 DC_HPD_SENSE_DELAYED 4 4 DC_HPD_RX_INT_STATUS 8 8 DC_HPD_TOGGLE_FILT_CON_TIMER_VAL 12 19 DC_HPD_TOGGLE_FILT_DISCON_TIMER_VAL 24 31 regHPD3_DC_HPD_INT_CONTROL 0 0x1f2d 5 0 2 DC_HPD_INT_ACK 0 0 DC_HPD_INT_POLARITY 8 8 DC_HPD_INT_EN 16 16 DC_HPD_RX_INT_ACK 20 20 DC_HPD_RX_INT_EN 24 24 regHPD3_DC_HPD_CONTROL 0 0x1f2e 3 0 2 DC_HPD_CONNECTION_TIMER 0 12 DC_HPD_RX_INT_TIMER 16 25 DC_HPD_EN 28 28 regHPD3_DC_HPD_FAST_TRAIN_CNTL 0 0x1f2f 4 0 2 DC_HPD_CONNECT_AUX_TX_DELAY 0 7 DC_HPD_CONNECT_FAST_TRAIN_DELAY 12 19 DC_HPD_CONNECT_AUX_TX_EN 24 24 DC_HPD_CONNECT_FAST_TRAIN_EN 28 28 regHPD3_DC_HPD_TOGGLE_FILT_CNTL 0 0x1f30 2 0 2 DC_HPD_CONNECT_INT_DELAY 0 7 DC_HPD_DISCONNECT_INT_DELAY 20 27 regHPD4_DC_HPD_INT_STATUS 0 0x1f34 6 0 2 DC_HPD_INT_STATUS 0 0 DC_HPD_SENSE 1 1 DC_HPD_SENSE_DELAYED 4 4 DC_HPD_RX_INT_STATUS 8 8 DC_HPD_TOGGLE_FILT_CON_TIMER_VAL 12 19 DC_HPD_TOGGLE_FILT_DISCON_TIMER_VAL 24 31 regHPD4_DC_HPD_INT_CONTROL 0 0x1f35 5 0 2 DC_HPD_INT_ACK 0 0 DC_HPD_INT_POLARITY 8 8 DC_HPD_INT_EN 16 16 DC_HPD_RX_INT_ACK 20 20 DC_HPD_RX_INT_EN 24 24 regHPD4_DC_HPD_CONTROL 0 0x1f36 3 0 2 DC_HPD_CONNECTION_TIMER 0 12 DC_HPD_RX_INT_TIMER 16 25 DC_HPD_EN 28 28 regHPD4_DC_HPD_FAST_TRAIN_CNTL 0 0x1f37 4 0 2 DC_HPD_CONNECT_AUX_TX_DELAY 0 7 DC_HPD_CONNECT_FAST_TRAIN_DELAY 12 19 DC_HPD_CONNECT_AUX_TX_EN 24 24 DC_HPD_CONNECT_FAST_TRAIN_EN 28 28 regHPD4_DC_HPD_TOGGLE_FILT_CNTL 0 0x1f38 2 0 2 DC_HPD_CONNECT_INT_DELAY 0 7 DC_HPD_DISCONNECT_INT_DELAY 20 27 regDP0_DP_LINK_CNTL 0 0x2108 3 0 2 DP_LINK_TRAINING_COMPLETE 4 4 DP_LINK_STATUS 8 8 DP_EMBEDDED_PANEL_MODE 17 17 regDP0_DP_PIXEL_FORMAT 0 0x2109 3 0 2 DP_PIXEL_ENCODING 0 2 DP_COMPONENT_DEPTH 24 26 DP_PIXEL_COMBINE 28 29 regDP0_DP_MSA_COLORIMETRY 0 0x210a 1 0 2 DP_MSA_MISC0 24 31 regDP0_DP_CONFIG 0 0x210b 1 0 2 DP_UDI_LANES 0 1 regDP0_DP_VID_STREAM_CNTL 0 0x210c 4 0 2 DP_VID_STREAM_ENABLE 0 0 DP_VID_STREAM_DIS_DEFER 8 9 DP_VID_STREAM_STATUS 16 16 DP_VID_STREAM_CHANGE_KEEPOUT 20 20 regDP0_DP_STEER_FIFO 0 0x210d 7 0 2 DP_STEER_FIFO_RESET 0 0 DP_STEER_OVERFLOW_FLAG 4 4 DP_STEER_OVERFLOW_INT 5 5 DP_STEER_OVERFLOW_ACK 6 6 DP_STEER_OVERFLOW_MASK 7 7 DP_TU_OVERFLOW_FLAG 8 8 DP_TU_OVERFLOW_ACK 12 12 regDP0_DP_MSA_MISC 0 0x210e 4 0 2 DP_MSA_MISC1 0 7 DP_MSA_MISC2 8 15 DP_MSA_MISC3 16 23 DP_MSA_MISC4 24 31 regDP0_DP_DPHY_INTERNAL_CTRL 0 0x210f 2 0 2 DPHY_ALT_SCRAMBLER_RESET_EN 0 0 DPHY_ALT_SCRAMBLER_RESET_SEL 4 4 regDP0_DP_VID_TIMING 0 0x2110 5 0 2 DP_VID_M_N_DOUBLE_BUFFER_MODE 4 4 DP_VID_M_N_GEN_EN 8 8 DP_VID_N_MUL 10 11 DP_VID_M_DIV 12 13 DP_VID_N_DIV 24 31 regDP0_DP_VID_N 0 0x2111 1 0 2 DP_VID_N 0 23 regDP0_DP_VID_M 0 0x2112 1 0 2 DP_VID_M 0 23 regDP0_DP_LINK_FRAMING_CNTL 0 0x2113 3 0 2 DP_IDLE_BS_INTERVAL 0 17 DP_VBID_DISABLE 24 24 DP_VID_ENHANCED_FRAME_MODE 28 28 regDP0_DP_HBR2_EYE_PATTERN 0 0x2114 1 0 2 DP_HBR2_EYE_PATTERN_ENABLE 0 0 regDP0_DP_VID_MSA_VBID 0 0x2115 2 0 2 DP_VID_MSA_LOCATION 0 11 DP_VID_VBID_FIELD_POL 24 24 regDP0_DP_VID_INTERRUPT_CNTL 0 0x2116 3 0 2 DP_VID_STREAM_DISABLE_INT 0 0 DP_VID_STREAM_DISABLE_ACK 1 1 DP_VID_STREAM_DISABLE_MASK 2 2 regDP0_DP_DPHY_CNTL 0 0x2117 10 0 2 DPHY_ATEST_SEL_LANE0 0 0 DPHY_ATEST_SEL_LANE1 1 1 DPHY_ATEST_SEL_LANE2 2 2 DPHY_ATEST_SEL_LANE3 3 3 DPHY_FEC_EN 4 4 DPHY_FEC_READY_SHADOW 5 5 DPHY_FEC_ACTIVE_STATUS 6 6 DPHY_SCRAMBLER_SEL 8 8 DPHY_BYPASS 16 16 DPHY_SKEW_BYPASS 24 24 regDP0_DP_DPHY_TRAINING_PATTERN_SEL 0 0x2118 1 0 2 DPHY_TRAINING_PATTERN_SEL 0 1 regDP0_DP_DPHY_SYM0 0 0x2119 3 0 2 DPHY_SYM1 0 9 DPHY_SYM2 10 19 DPHY_SYM3 20 29 regDP0_DP_DPHY_SYM1 0 0x211a 3 0 2 DPHY_SYM4 0 9 DPHY_SYM5 10 19 DPHY_SYM6 20 29 regDP0_DP_DPHY_SYM2 0 0x211b 2 0 2 DPHY_SYM7 0 9 DPHY_SYM8 10 19 regDP0_DP_DPHY_8B10B_CNTL 0 0x211c 3 0 2 DPHY_8B10B_RESET 8 8 DPHY_8B10B_EXT_DISP 16 16 DPHY_8B10B_CUR_DISP 24 24 regDP0_DP_DPHY_PRBS_CNTL 0 0x211d 3 0 2 DPHY_PRBS_EN 0 0 DPHY_PRBS_SEL 4 5 DPHY_PRBS_SEED 8 30 regDP0_DP_DPHY_SCRAM_CNTL 0 0x211e 4 0 2 DPHY_SCRAMBLER_DIS 0 0 DPHY_SCRAMBLER_ADVANCE 4 4 DPHY_SCRAMBLER_BS_COUNT 8 17 DPHY_SCRAMBLER_KCODE 24 24 regDP0_DP_DPHY_CRC_EN 0 0x211f 3 0 2 DPHY_CRC_EN 0 0 DPHY_CRC_CONT_EN 4 4 DPHY_CRC_RESULT_VALID 8 8 regDP0_DP_DPHY_CRC_CNTL 0 0x2120 3 0 2 DPHY_CRC_FIELD 0 0 DPHY_CRC_SEL 4 5 DPHY_CRC_MASK 16 23 regDP0_DP_DPHY_CRC_RESULT 0 0x2121 4 0 2 DPHY_CRC_RESULT 0 7 DPHY_CRC_RESULT1 8 15 DPHY_CRC_RESULT2 16 23 DPHY_CRC_RESULT3 24 31 regDP0_DP_DPHY_CRC_MST_CNTL 0 0x2122 2 0 2 DPHY_CRC_MST_FIRST_SLOT 0 5 DPHY_CRC_MST_LAST_SLOT 8 13 regDP0_DP_DPHY_CRC_MST_STATUS 0 0x2123 3 0 2 DPHY_CRC_MST_PHASE_LOCK 0 0 DPHY_CRC_MST_PHASE_ERROR 8 8 DPHY_CRC_MST_PHASE_ERROR_ACK 16 16 regDP0_DP_DPHY_FAST_TRAINING 0 0x2124 6 0 2 DPHY_RX_FAST_TRAINING_CAPABLE 0 0 DPHY_SW_FAST_TRAINING_START 1 1 DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN 2 2 DPHY_STREAM_RESET_DURING_FAST_TRAINING 4 4 DPHY_FAST_TRAINING_TP1_TIME 8 19 DPHY_FAST_TRAINING_TP2_TIME 20 31 regDP0_DP_DPHY_FAST_TRAINING_STATUS 0 0x2125 4 0 2 DPHY_FAST_TRAINING_STATE 0 2 DPHY_FAST_TRAINING_COMPLETE_OCCURRED 4 4 DPHY_FAST_TRAINING_COMPLETE_MASK 8 8 DPHY_FAST_TRAINING_COMPLETE_ACK 12 12 regDP0_DP_SEC_CNTL 0 0x212b 14 0 2 DP_SEC_STREAM_ENABLE 0 0 DP_SEC_ASP_ENABLE 4 4 DP_SEC_ATP_ENABLE 8 8 DP_SEC_AIP_ENABLE 12 12 DP_SEC_ACM_ENABLE 16 16 DP_SEC_GSP0_ENABLE 20 20 DP_SEC_GSP1_ENABLE 21 21 DP_SEC_GSP2_ENABLE 22 22 DP_SEC_GSP3_ENABLE 23 23 DP_SEC_GSP4_ENABLE 24 24 DP_SEC_GSP5_ENABLE 25 25 DP_SEC_GSP6_ENABLE 26 26 DP_SEC_GSP7_ENABLE 27 27 DP_SEC_MPG_ENABLE 28 28 regDP0_DP_SEC_CNTL1 0 0x212c 15 0 2 DP_SEC_ISRC_ENABLE 0 0 DP_SEC_GSP0_LINE_REFERENCE 1 1 DP_SEC_GSP0_PRIORITY 4 4 DP_SEC_GSP0_SEND 5 5 DP_SEC_GSP0_SEND_PENDING 6 6 DP_SEC_GSP0_SEND_DEADLINE_MISSED 7 7 DP_SEC_GSP0_SEND_ANY_LINE 8 8 DP_SEC_GSP1_LINE_REFERENCE 9 9 DP_SEC_GSP2_LINE_REFERENCE 10 10 DP_SEC_GSP3_LINE_REFERENCE 11 11 DP_SEC_GSP4_LINE_REFERENCE 12 12 DP_SEC_GSP5_LINE_REFERENCE 13 13 DP_SEC_GSP6_LINE_REFERENCE 14 14 DP_SEC_GSP7_LINE_REFERENCE 15 15 DP_SEC_GSP0_LINE_NUM 16 31 regDP0_DP_SEC_FRAMING1 0 0x212d 2 0 2 DP_SEC_FRAME_START_LOCATION 0 11 DP_SEC_VBLANK_TRANSMIT_WIDTH 16 31 regDP0_DP_SEC_FRAMING2 0 0x212e 2 0 2 DP_SEC_START_POSITION 0 15 DP_SEC_HBLANK_TRANSMIT_WIDTH 16 31 regDP0_DP_SEC_FRAMING3 0 0x212f 2 0 2 DP_SEC_IDLE_FRAME_SIZE 0 13 DP_SEC_IDLE_TRANSMIT_WIDTH 16 31 regDP0_DP_SEC_FRAMING4 0 0x2130 5 0 2 DP_SST_SDP_SPLITTING 0 0 DP_SEC_COLLISION_STATUS 20 20 DP_SEC_COLLISION_ACK 24 24 DP_SEC_AUDIO_MUTE 28 28 DP_SEC_AUDIO_MUTE_STATUS 29 29 regDP0_DP_SEC_AUD_N 0 0x2131 1 0 2 DP_SEC_AUD_N 0 23 regDP0_DP_SEC_AUD_N_READBACK 0 0x2132 1 0 2 DP_SEC_AUD_N_READBACK 0 23 regDP0_DP_SEC_AUD_M 0 0x2133 1 0 2 DP_SEC_AUD_M 0 23 regDP0_DP_SEC_AUD_M_READBACK 0 0x2134 1 0 2 DP_SEC_AUD_M_READBACK 0 23 regDP0_DP_SEC_TIMESTAMP 0 0x2135 1 0 2 DP_SEC_TIMESTAMP_MODE 0 0 regDP0_DP_SEC_PACKET_CNTL 0 0x2136 4 0 2 DP_SEC_ASP_CODING_TYPE 1 3 DP_SEC_ASP_PRIORITY 4 4 DP_SEC_VERSION 8 13 DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE 16 16 regDP0_DP_MSE_RATE_CNTL 0 0x2137 2 0 2 DP_MSE_RATE_Y 0 25 DP_MSE_RATE_X 26 31 regDP0_DP_MSE_RATE_UPDATE 0 0x2139 1 0 2 DP_MSE_RATE_UPDATE_PENDING 0 0 regDP0_DP_MSE_SAT0 0 0x213a 8 0 2 DP_MSE_SAT_SRC0 0 2 DP_MSE_SAT_ENCRYPT0 4 4 DP_MSE_SAT_ENCRYPTION_TYPE0 5 5 DP_MSE_SAT_SLOT_COUNT0 8 13 DP_MSE_SAT_SRC1 16 18 DP_MSE_SAT_ENCRYPT1 20 20 DP_MSE_SAT_ENCRYPTION_TYPE1 21 21 DP_MSE_SAT_SLOT_COUNT1 24 29 regDP0_DP_MSE_SAT1 0 0x213b 8 0 2 DP_MSE_SAT_SRC2 0 2 DP_MSE_SAT_ENCRYPT2 4 4 DP_MSE_SAT_ENCRYPTION_TYPE2 5 5 DP_MSE_SAT_SLOT_COUNT2 8 13 DP_MSE_SAT_SRC3 16 18 DP_MSE_SAT_ENCRYPT3 20 20 DP_MSE_SAT_ENCRYPTION_TYPE3 21 21 DP_MSE_SAT_SLOT_COUNT3 24 29 regDP0_DP_MSE_SAT2 0 0x213c 8 0 2 DP_MSE_SAT_SRC4 0 2 DP_MSE_SAT_ENCRYPT4 4 4 DP_MSE_SAT_ENCRYPTION_TYPE4 5 5 DP_MSE_SAT_SLOT_COUNT4 8 13 DP_MSE_SAT_SRC5 16 18 DP_MSE_SAT_ENCRYPT5 20 20 DP_MSE_SAT_ENCRYPTION_TYPE5 21 21 DP_MSE_SAT_SLOT_COUNT5 24 29 regDP0_DP_MSE_SAT_UPDATE 0 0x213d 2 0 2 DP_MSE_SAT_UPDATE 0 1 DP_MSE_16_MTP_KEEPOUT 8 8 regDP0_DP_MSE_LINK_TIMING 0 0x213e 2 0 2 DP_MSE_LINK_FRAME 0 9 DP_MSE_LINK_LINE 16 17 regDP0_DP_MSE_MISC_CNTL 0 0x213f 3 0 2 DP_MSE_BLANK_CODE 0 0 DP_MSE_TIMESTAMP_MODE 4 4 DP_MSE_ZERO_ENCODER 8 8 regDP0_DP_DPHY_BS_SR_SWAP_CNTL 0 0x2144 3 0 2 DPHY_LOAD_BS_COUNT 0 9 DPHY_BS_SR_SWAP_DONE 15 15 DPHY_LOAD_BS_COUNT_START 16 16 regDP0_DP_DPHY_HBR2_PATTERN_CONTROL 0 0x2145 1 0 2 DP_DPHY_HBR2_PATTERN_CONTROL 0 2 regDP0_DP_MSE_SAT0_STATUS 0 0x2147 8 0 2 DP_MSE_SAT_SRC0_STATUS 0 2 DP_MSE_SAT_ENCRYPT0_STATUS 4 4 DP_MSE_SAT_ENCRYPTION_TYPE0_STATUS 5 5 DP_MSE_SAT_SLOT_COUNT0_STATUS 8 13 DP_MSE_SAT_SRC1_STATUS 16 18 DP_MSE_SAT_ENCRYPT1_STATUS 20 20 DP_MSE_SAT_ENCRYPTION_TYPE1_STATUS 21 21 DP_MSE_SAT_SLOT_COUNT1_STATUS 24 29 regDP0_DP_MSE_SAT1_STATUS 0 0x2148 8 0 2 DP_MSE_SAT_SRC2_STATUS 0 2 DP_MSE_SAT_ENCRYPT2_STATUS 4 4 DP_MSE_SAT_ENCRYPTION_TYPE2_STATUS 5 5 DP_MSE_SAT_SLOT_COUNT2_STATUS 8 13 DP_MSE_SAT_SRC3_STATUS 16 18 DP_MSE_SAT_ENCRYPT3_STATUS 20 20 DP_MSE_SAT_ENCRYPTION_TYPE3_STATUS 21 21 DP_MSE_SAT_SLOT_COUNT3_STATUS 24 29 regDP0_DP_MSE_SAT2_STATUS 0 0x2149 8 0 2 DP_MSE_SAT_SRC4_STATUS 0 2 DP_MSE_SAT_ENCRYPT4_STATUS 4 4 DP_MSE_SAT_ENCRYPTION_TYPE4_STATUS 5 5 DP_MSE_SAT_SLOT_COUNT4_STATUS 8 13 DP_MSE_SAT_SRC5_STATUS 16 18 DP_MSE_SAT_ENCRYPT5_STATUS 20 20 DP_MSE_SAT_ENCRYPTION_TYPE5_STATUS 21 21 DP_MSE_SAT_SLOT_COUNT5_STATUS 24 29 regDP0_DP_MSA_TIMING_PARAM1 0 0x214c 2 0 2 DP_MSA_VTOTAL 0 15 DP_MSA_HTOTAL 16 31 regDP0_DP_MSA_TIMING_PARAM2 0 0x214d 2 0 2 DP_MSA_VSTART 0 15 DP_MSA_HSTART 16 31 regDP0_DP_MSA_TIMING_PARAM3 0 0x214e 4 0 2 DP_MSA_VSYNCWIDTH 0 14 DP_MSA_VSYNCPOLARITY 15 15 DP_MSA_HSYNCWIDTH 16 30 DP_MSA_HSYNCPOLARITY 31 31 regDP0_DP_MSA_TIMING_PARAM4 0 0x214f 2 0 2 DP_MSA_VHEIGHT 0 15 DP_MSA_HWIDTH 16 31 regDP0_DP_MSO_CNTL 0 0x2150 8 0 2 DP_MSO_NUM_OF_SSTLINK 0 1 DP_MSO_SEC_STREAM_ENABLE 4 7 DP_MSO_SEC_ASP_ENABLE 8 11 DP_MSO_SEC_ATP_ENABLE 12 15 DP_MSO_SEC_AIP_ENABLE 16 19 DP_MSO_SEC_ACM_ENABLE 20 23 DP_MSO_SEC_GSP0_ENABLE 24 27 DP_MSO_SEC_GSP1_ENABLE 28 31 regDP0_DP_MSO_CNTL1 0 0x2151 8 0 2 DP_MSO_SEC_GSP2_ENABLE 0 3 DP_MSO_SEC_GSP3_ENABLE 4 7 DP_MSO_SEC_GSP4_ENABLE 8 11 DP_MSO_SEC_GSP5_ENABLE 12 15 DP_MSO_SEC_GSP6_ENABLE 16 19 DP_MSO_SEC_GSP7_ENABLE 20 23 DP_MSO_SEC_MPG_ENABLE 24 27 DP_MSO_SEC_ISRC_ENABLE 28 31 regDP0_DP_DSC_CNTL 0 0x2152 2 0 2 DP_DSC_MODE 0 1 DP_DSC_SLICE_WIDTH 16 28 regDP0_DP_SEC_CNTL2 0 0x2153 29 0 2 DP_SEC_GSP1_SEND 0 0 DP_SEC_GSP1_SEND_PENDING 1 1 DP_SEC_GSP1_SEND_DEADLINE_MISSED 2 2 DP_SEC_GSP1_SEND_ANY_LINE 3 3 DP_SEC_GSP2_SEND 4 4 DP_SEC_GSP2_SEND_PENDING 5 5 DP_SEC_GSP2_SEND_DEADLINE_MISSED 6 6 DP_SEC_GSP2_SEND_ANY_LINE 7 7 DP_SEC_GSP3_SEND 8 8 DP_SEC_GSP3_SEND_PENDING 9 9 DP_SEC_GSP3_SEND_DEADLINE_MISSED 10 10 DP_SEC_GSP3_SEND_ANY_LINE 11 11 DP_SEC_GSP4_SEND 12 12 DP_SEC_GSP4_SEND_PENDING 13 13 DP_SEC_GSP4_SEND_DEADLINE_MISSED 14 14 DP_SEC_GSP4_SEND_ANY_LINE 15 15 DP_SEC_GSP5_SEND 16 16 DP_SEC_GSP5_SEND_PENDING 17 17 DP_SEC_GSP5_SEND_DEADLINE_MISSED 18 18 DP_SEC_GSP5_SEND_ANY_LINE 19 19 DP_SEC_GSP6_SEND 20 20 DP_SEC_GSP6_SEND_PENDING 21 21 DP_SEC_GSP6_SEND_DEADLINE_MISSED 22 22 DP_SEC_GSP6_SEND_ANY_LINE 23 23 DP_SEC_GSP7_SEND 24 24 DP_SEC_GSP7_SEND_PENDING 25 25 DP_SEC_GSP7_SEND_DEADLINE_MISSED 26 26 DP_SEC_GSP7_SEND_ANY_LINE 27 27 DP_SEC_GSP11_PPS 28 28 regDP0_DP_SEC_CNTL3 0 0x2154 2 0 2 DP_SEC_GSP1_LINE_NUM 0 15 DP_SEC_GSP2_LINE_NUM 16 31 regDP0_DP_SEC_CNTL4 0 0x2155 2 0 2 DP_SEC_GSP3_LINE_NUM 0 15 DP_SEC_GSP4_LINE_NUM 16 31 regDP0_DP_SEC_CNTL5 0 0x2156 2 0 2 DP_SEC_GSP5_LINE_NUM 0 15 DP_SEC_GSP6_LINE_NUM 16 31 regDP0_DP_SEC_CNTL6 0 0x2157 13 0 2 DP_SEC_GSP7_LINE_NUM 0 15 DP_SEC_GSP0_EN_DB_DISABLE 16 16 DP_SEC_GSP1_EN_DB_DISABLE 17 17 DP_SEC_GSP2_EN_DB_DISABLE 18 18 DP_SEC_GSP3_EN_DB_DISABLE 19 19 DP_SEC_GSP4_EN_DB_DISABLE 20 20 DP_SEC_GSP5_EN_DB_DISABLE 21 21 DP_SEC_GSP6_EN_DB_DISABLE 22 22 DP_SEC_GSP7_EN_DB_DISABLE 23 23 DP_SEC_GSP8_EN_DB_DISABLE 24 24 DP_SEC_GSP9_EN_DB_DISABLE 25 25 DP_SEC_GSP10_EN_DB_DISABLE 26 26 DP_SEC_GSP11_EN_DB_DISABLE 27 27 regDP0_DP_SEC_CNTL7 0 0x2158 16 0 2 DP_SEC_GSP0_SEND_ACTIVE 0 0 DP_SEC_GSP0_SEND_IN_IDLE 1 1 DP_SEC_GSP1_SEND_ACTIVE 4 4 DP_SEC_GSP1_SEND_IN_IDLE 5 5 DP_SEC_GSP2_SEND_ACTIVE 8 8 DP_SEC_GSP2_SEND_IN_IDLE 9 9 DP_SEC_GSP3_SEND_ACTIVE 12 12 DP_SEC_GSP3_SEND_IN_IDLE 13 13 DP_SEC_GSP4_SEND_ACTIVE 16 16 DP_SEC_GSP4_SEND_IN_IDLE 17 17 DP_SEC_GSP5_SEND_ACTIVE 20 20 DP_SEC_GSP5_SEND_IN_IDLE 21 21 DP_SEC_GSP6_SEND_ACTIVE 24 24 DP_SEC_GSP6_SEND_IN_IDLE 25 25 DP_SEC_GSP7_SEND_ACTIVE 28 28 DP_SEC_GSP7_SEND_IN_IDLE 29 29 regDP0_DP_DB_CNTL 0 0x2159 8 0 2 DP_DB_PENDING 0 0 DP_DB_TAKEN 4 4 DP_DB_TAKEN_CLR 5 5 DP_DB_LOCK 8 8 DP_DB_DISABLE 12 12 DP_VUPDATE_DB_PENDING 15 15 DP_VUPDATE_DB_TAKEN 16 16 DP_VUPDATE_DB_TAKEN_CLR 17 17 regDP0_DP_MSA_VBID_MISC 0 0x215a 8 0 2 DP_MSA_MISC1_STEREOSYNC_OVERRIDE 0 1 DP_MSA_MISC1_STEREOSYNC_OVERRIDE_EN 4 4 DP_VBID1_OVERRIDE 8 8 DP_VBID2_OVERRIDE 9 9 DP_VBID1_OVERRIDE_EN 12 12 DP_VBID2_OVERRIDE_EN 13 13 DP_VBID6_LINE_REFERENCE 15 15 DP_VBID6_LINE_NUM 16 31 regDP0_DP_SEC_METADATA_TRANSMISSION 0 0x215b 4 0 2 DP_SEC_METADATA_PACKET_ENABLE 0 0 DP_SEC_METADATA_PACKET_LINE_REFERENCE 1 1 DP_SEC_MSO_METADATA_PACKET_ENABLE 4 7 DP_SEC_METADATA_PACKET_LINE 16 31 regDP0_DP_DSC_BYTES_PER_PIXEL 0 0x215c 1 0 2 DP_DSC_BYTES_PER_PIXEL 0 30 regDP0_DP_ALPM_CNTL 0 0x215d 7 0 2 DP_ML_PHY_SLEEP_SEND 0 0 DP_ML_PHY_SLEEP_PENDING 1 1 DP_ML_PHY_STANDBY_SEND 2 2 DP_ML_PHY_STANDBY_PENDING 3 3 DP_ML_PHY_SLEEP_STANDBY_IMMEDIATE 4 4 DP_LINK_TRAINING_SWITCH_BETWEEN_VIDEO 5 5 DP_ML_PHY_SLEEP_STANDBY_LINE_NUM 16 31 regDP0_DP_GSP8_CNTL 0 0x215e 10 0 2 DP_MSO_SEC_GSP8_ENABLE 0 3 DP_SEC_GSP8_ENABLE 4 4 DP_SEC_GSP8_LINE_REFERENCE 5 5 DP_SEC_GSP8_SEND_IN_IDLE 6 6 DP_SEC_GSP8_SEND 7 7 DP_SEC_GSP8_SEND_ANY_LINE 8 8 DP_SEC_GSP8_SEND_PENDING 12 12 DP_SEC_GSP8_SEND_ACTIVE 13 13 DP_SEC_GSP8_SEND_DEADLINE_MISSED 14 14 DP_SEC_GSP8_LINE_NUM 16 31 regDP0_DP_GSP9_CNTL 0 0x215f 10 0 2 DP_MSO_SEC_GSP9_ENABLE 0 3 DP_SEC_GSP9_ENABLE 4 4 DP_SEC_GSP9_LINE_REFERENCE 5 5 DP_SEC_GSP9_SEND_IN_IDLE 6 6 DP_SEC_GSP9_SEND 7 7 DP_SEC_GSP9_SEND_ANY_LINE 8 8 DP_SEC_GSP9_SEND_PENDING 12 12 DP_SEC_GSP9_SEND_ACTIVE 13 13 DP_SEC_GSP9_SEND_DEADLINE_MISSED 14 14 DP_SEC_GSP9_LINE_NUM 16 31 regDP0_DP_GSP10_CNTL 0 0x2160 10 0 2 DP_MSO_SEC_GSP10_ENABLE 0 3 DP_SEC_GSP10_ENABLE 4 4 DP_SEC_GSP10_LINE_REFERENCE 5 5 DP_SEC_GSP10_SEND_IN_IDLE 6 6 DP_SEC_GSP10_SEND 7 7 DP_SEC_GSP10_SEND_ANY_LINE 8 8 DP_SEC_GSP10_SEND_PENDING 12 12 DP_SEC_GSP10_SEND_ACTIVE 13 13 DP_SEC_GSP10_SEND_DEADLINE_MISSED 14 14 DP_SEC_GSP10_LINE_NUM 16 31 regDP0_DP_GSP11_CNTL 0 0x2161 10 0 2 DP_MSO_SEC_GSP11_ENABLE 0 3 DP_SEC_GSP11_ENABLE 4 4 DP_SEC_GSP11_LINE_REFERENCE 5 5 DP_SEC_GSP11_SEND_IN_IDLE 6 6 DP_SEC_GSP11_SEND 7 7 DP_SEC_GSP11_SEND_ANY_LINE 8 8 DP_SEC_GSP11_SEND_PENDING 12 12 DP_SEC_GSP11_SEND_ACTIVE 13 13 DP_SEC_GSP11_SEND_DEADLINE_MISSED 14 14 DP_SEC_GSP11_LINE_NUM 16 31 regDP0_DP_GSP_EN_DB_STATUS 0 0x2162 12 0 2 DP_SEC_GSP0_EN_DB_PENDING 0 0 DP_SEC_GSP1_EN_DB_PENDING 1 1 DP_SEC_GSP2_EN_DB_PENDING 2 2 DP_SEC_GSP3_EN_DB_PENDING 3 3 DP_SEC_GSP4_EN_DB_PENDING 4 4 DP_SEC_GSP5_EN_DB_PENDING 5 5 DP_SEC_GSP6_EN_DB_PENDING 6 6 DP_SEC_GSP7_EN_DB_PENDING 7 7 DP_SEC_GSP8_EN_DB_PENDING 8 8 DP_SEC_GSP9_EN_DB_PENDING 9 9 DP_SEC_GSP10_EN_DB_PENDING 10 10 DP_SEC_GSP11_EN_DB_PENDING 11 11 regDIG0_DIG_FE_CNTL 0 0x208b 11 0 2 DIG_SOURCE_SELECT 0 2 DIG_STEREOSYNC_SELECT 4 6 DIG_STEREOSYNC_GATE_EN 8 8 DIG_START 10 10 DIG_DIGITAL_BYPASS_SELECT 12 14 DIG_INPUT_PIXEL_SELECT 16 17 DOLBY_VISION_EN 18 18 DOLBY_VISION_METADATA_PACKET_MISSED 19 19 DIG_SYMCLK_FE_ON 24 24 TMDS_PIXEL_ENCODING 28 28 TMDS_COLOR_FORMAT 30 31 regDIG0_DIG_OUTPUT_CRC_CNTL 0 0x208c 3 0 2 DIG_OUTPUT_CRC_EN 0 0 DIG_OUTPUT_CRC_LINK_SEL 4 4 DIG_OUTPUT_CRC_DATA_SEL 8 9 regDIG0_DIG_OUTPUT_CRC_RESULT 0 0x208d 1 0 2 DIG_OUTPUT_CRC_RESULT 0 29 regDIG0_DIG_CLOCK_PATTERN 0 0x208e 1 0 2 DIG_CLOCK_PATTERN 0 9 regDIG0_DIG_TEST_PATTERN 0 0x208f 6 0 2 DIG_TEST_PATTERN_OUT_EN 0 0 DIG_HALF_CLOCK_PATTERN_SEL 1 1 DIG_RANDOM_PATTERN_OUT_EN 4 4 DIG_RANDOM_PATTERN_RESET 5 5 DIG_TEST_PATTERN_EXTERNAL_RESET_EN 6 6 DIG_STATIC_TEST_PATTERN 16 25 regDIG0_DIG_RANDOM_PATTERN_SEED 0 0x2090 2 0 2 DIG_RANDOM_PATTERN_SEED 0 23 DIG_RAN_PAT_DURING_DE_ONLY 24 24 regDIG0_DIG_FIFO_STATUS 0 0x2091 11 0 2 DIG_FIFO_LEVEL_ERROR 0 0 DIG_FIFO_USE_OVERWRITE_LEVEL 1 1 DIG_FIFO_OVERWRITE_LEVEL 2 7 DIG_FIFO_ERROR_ACK 8 8 DIG_FIFO_CAL_AVERAGE_LEVEL 10 15 DIG_FIFO_MAXIMUM_LEVEL 16 20 DIG_FIFO_MINIMUM_LEVEL 22 25 DIG_FIFO_READ_CLOCK_SRC 26 26 DIG_FIFO_CALIBRATED 29 29 DIG_FIFO_FORCE_RECAL_AVERAGE 30 30 DIG_FIFO_FORCE_RECOMP_MINMAX 31 31 regDIG0_HDMI_METADATA_PACKET_CONTROL 0 0x2092 4 0 2 HDMI_METADATA_PACKET_ENABLE 0 0 HDMI_METADATA_PACKET_LINE_REFERENCE 4 4 HDMI_METADATA_PACKET_MISSED 8 8 HDMI_METADATA_PACKET_LINE 16 31 regDIG0_HDMI_CONTROL 0 0x2093 10 0 2 HDMI_KEEPOUT_MODE 0 0 HDMI_DATA_SCRAMBLE_EN 1 1 HDMI_CLOCK_CHANNEL_RATE 2 2 HDMI_NO_EXTRA_NULL_PACKET_FILLED 3 3 HDMI_PACKET_GEN_VERSION 4 4 HDMI_ERROR_ACK 8 8 HDMI_ERROR_MASK 9 9 HDMI_UNSCRAMBLED_CONTROL_LINE_NUM 16 21 HDMI_DEEP_COLOR_ENABLE 24 24 HDMI_DEEP_COLOR_DEPTH 28 29 regDIG0_HDMI_STATUS 0 0x2094 4 0 2 HDMI_ACTIVE_AVMUTE 0 0 HDMI_AUDIO_PACKET_ERROR 16 16 HDMI_VBI_PACKET_ERROR 20 20 HDMI_ERROR_INT 27 27 regDIG0_HDMI_AUDIO_PACKET_CONTROL 0 0x2095 1 0 2 HDMI_AUDIO_DELAY_EN 4 5 regDIG0_HDMI_ACR_PACKET_CONTROL 0 0x2096 7 0 2 HDMI_ACR_SEND 0 0 HDMI_ACR_CONT 1 1 HDMI_ACR_SELECT 4 5 HDMI_ACR_SOURCE 8 8 HDMI_ACR_AUTO_SEND 12 12 HDMI_ACR_N_MULTIPLE 16 18 HDMI_ACR_AUDIO_PRIORITY 31 31 regDIG0_HDMI_VBI_PACKET_CONTROL 0 0x2097 8 0 2 HDMI_NULL_SEND 0 0 HDMI_GC_SEND 4 4 HDMI_GC_CONT 5 5 HDMI_ISRC_SEND 8 8 HDMI_ISRC_CONT 9 9 HDMI_ACP_SEND 12 12 HDMI_ISRC_LINE 16 21 HDMI_ACP_LINE 24 29 regDIG0_HDMI_INFOFRAME_CONTROL0 0 0x2098 4 0 2 HDMI_AUDIO_INFO_SEND 4 4 HDMI_AUDIO_INFO_CONT 5 5 HDMI_MPEG_INFO_SEND 8 8 HDMI_MPEG_INFO_CONT 9 9 regDIG0_HDMI_INFOFRAME_CONTROL1 0 0x2099 2 0 2 HDMI_AUDIO_INFO_LINE 8 13 HDMI_MPEG_INFO_LINE 16 21 regDIG0_HDMI_GENERIC_PACKET_CONTROL0 0 0x209a 32 0 2 HDMI_GENERIC0_SEND 0 0 HDMI_GENERIC0_CONT 1 1 HDMI_GENERIC0_LINE_REFERENCE 2 2 HDMI_GENERIC0_UPDATE_LOCK_DISABLE 3 3 HDMI_GENERIC1_SEND 4 4 HDMI_GENERIC1_CONT 5 5 HDMI_GENERIC1_LINE_REFERENCE 6 6 HDMI_GENERIC1_UPDATE_LOCK_DISABLE 7 7 HDMI_GENERIC2_SEND 8 8 HDMI_GENERIC2_CONT 9 9 HDMI_GENERIC2_LINE_REFERENCE 10 10 HDMI_GENERIC2_UPDATE_LOCK_DISABLE 11 11 HDMI_GENERIC3_SEND 12 12 HDMI_GENERIC3_CONT 13 13 HDMI_GENERIC3_LINE_REFERENCE 14 14 HDMI_GENERIC3_UPDATE_LOCK_DISABLE 15 15 HDMI_GENERIC4_SEND 16 16 HDMI_GENERIC4_CONT 17 17 HDMI_GENERIC4_LINE_REFERENCE 18 18 HDMI_GENERIC4_UPDATE_LOCK_DISABLE 19 19 HDMI_GENERIC5_SEND 20 20 HDMI_GENERIC5_CONT 21 21 HDMI_GENERIC5_LINE_REFERENCE 22 22 HDMI_GENERIC5_UPDATE_LOCK_DISABLE 23 23 HDMI_GENERIC6_SEND 24 24 HDMI_GENERIC6_CONT 25 25 HDMI_GENERIC6_LINE_REFERENCE 26 26 HDMI_GENERIC6_UPDATE_LOCK_DISABLE 27 27 HDMI_GENERIC7_SEND 28 28 HDMI_GENERIC7_CONT 29 29 HDMI_GENERIC7_LINE_REFERENCE 30 30 HDMI_GENERIC7_UPDATE_LOCK_DISABLE 31 31 regDIG0_HDMI_GENERIC_PACKET_CONTROL6 0 0x209b 28 0 2 HDMI_GENERIC8_SEND 0 0 HDMI_GENERIC8_CONT 1 1 HDMI_GENERIC8_LINE_REFERENCE 2 2 HDMI_GENERIC8_UPDATE_LOCK_DISABLE 3 3 HDMI_GENERIC9_SEND 4 4 HDMI_GENERIC9_CONT 5 5 HDMI_GENERIC9_LINE_REFERENCE 6 6 HDMI_GENERIC9_UPDATE_LOCK_DISABLE 7 7 HDMI_GENERIC10_SEND 8 8 HDMI_GENERIC10_CONT 9 9 HDMI_GENERIC10_LINE_REFERENCE 10 10 HDMI_GENERIC10_UPDATE_LOCK_DISABLE 11 11 HDMI_GENERIC11_SEND 12 12 HDMI_GENERIC11_CONT 13 13 HDMI_GENERIC11_LINE_REFERENCE 14 14 HDMI_GENERIC11_UPDATE_LOCK_DISABLE 15 15 HDMI_GENERIC12_SEND 16 16 HDMI_GENERIC12_CONT 17 17 HDMI_GENERIC12_LINE_REFERENCE 18 18 HDMI_GENERIC12_UPDATE_LOCK_DISABLE 19 19 HDMI_GENERIC13_SEND 20 20 HDMI_GENERIC13_CONT 21 21 HDMI_GENERIC13_LINE_REFERENCE 22 22 HDMI_GENERIC13_UPDATE_LOCK_DISABLE 23 23 HDMI_GENERIC14_SEND 24 24 HDMI_GENERIC14_CONT 25 25 HDMI_GENERIC14_LINE_REFERENCE 26 26 HDMI_GENERIC14_UPDATE_LOCK_DISABLE 27 27 regDIG0_HDMI_GENERIC_PACKET_CONTROL5 0 0x209c 30 0 2 HDMI_GENERIC0_IMMEDIATE_SEND 0 0 HDMI_GENERIC0_IMMEDIATE_SEND_PENDING 1 1 HDMI_GENERIC1_IMMEDIATE_SEND 2 2 HDMI_GENERIC1_IMMEDIATE_SEND_PENDING 3 3 HDMI_GENERIC2_IMMEDIATE_SEND 4 4 HDMI_GENERIC2_IMMEDIATE_SEND_PENDING 5 5 HDMI_GENERIC3_IMMEDIATE_SEND 6 6 HDMI_GENERIC3_IMMEDIATE_SEND_PENDING 7 7 HDMI_GENERIC4_IMMEDIATE_SEND 8 8 HDMI_GENERIC4_IMMEDIATE_SEND_PENDING 9 9 HDMI_GENERIC5_IMMEDIATE_SEND 10 10 HDMI_GENERIC5_IMMEDIATE_SEND_PENDING 11 11 HDMI_GENERIC6_IMMEDIATE_SEND 12 12 HDMI_GENERIC6_IMMEDIATE_SEND_PENDING 13 13 HDMI_GENERIC7_IMMEDIATE_SEND 14 14 HDMI_GENERIC7_IMMEDIATE_SEND_PENDING 15 15 HDMI_GENERIC8_IMMEDIATE_SEND 16 16 HDMI_GENERIC8_IMMEDIATE_SEND_PENDING 17 17 HDMI_GENERIC9_IMMEDIATE_SEND 18 18 HDMI_GENERIC9_IMMEDIATE_SEND_PENDING 19 19 HDMI_GENERIC10_IMMEDIATE_SEND 20 20 HDMI_GENERIC10_IMMEDIATE_SEND_PENDING 21 21 HDMI_GENERIC11_IMMEDIATE_SEND 22 22 HDMI_GENERIC11_IMMEDIATE_SEND_PENDING 23 23 HDMI_GENERIC12_IMMEDIATE_SEND 24 24 HDMI_GENERIC12_IMMEDIATE_SEND_PENDING 25 25 HDMI_GENERIC13_IMMEDIATE_SEND 26 26 HDMI_GENERIC13_IMMEDIATE_SEND_PENDING 27 27 HDMI_GENERIC14_IMMEDIATE_SEND 28 28 HDMI_GENERIC14_IMMEDIATE_SEND_PENDING 29 29 regDIG0_HDMI_GC 0 0x209d 5 0 2 HDMI_GC_AVMUTE 0 0 HDMI_GC_AVMUTE_CONT 2 2 HDMI_DEFAULT_PHASE 4 4 HDMI_PACKING_PHASE 8 11 HDMI_PACKING_PHASE_OVERRIDE 12 12 regDIG0_HDMI_GENERIC_PACKET_CONTROL1 0 0x209e 2 0 2 HDMI_GENERIC0_LINE 0 15 HDMI_GENERIC1_LINE 16 31 regDIG0_HDMI_GENERIC_PACKET_CONTROL2 0 0x209f 2 0 2 HDMI_GENERIC2_LINE 0 15 HDMI_GENERIC3_LINE 16 31 regDIG0_HDMI_GENERIC_PACKET_CONTROL3 0 0x20a0 2 0 2 HDMI_GENERIC4_LINE 0 15 HDMI_GENERIC5_LINE 16 31 regDIG0_HDMI_GENERIC_PACKET_CONTROL4 0 0x20a1 2 0 2 HDMI_GENERIC6_LINE 0 15 HDMI_GENERIC7_LINE 16 31 regDIG0_HDMI_GENERIC_PACKET_CONTROL7 0 0x20a2 2 0 2 HDMI_GENERIC8_LINE 0 15 HDMI_GENERIC9_LINE 16 31 regDIG0_HDMI_GENERIC_PACKET_CONTROL8 0 0x20a3 2 0 2 HDMI_GENERIC10_LINE 0 15 HDMI_GENERIC11_LINE 16 31 regDIG0_HDMI_GENERIC_PACKET_CONTROL9 0 0x20a4 2 0 2 HDMI_GENERIC12_LINE 0 15 HDMI_GENERIC13_LINE 16 31 regDIG0_HDMI_GENERIC_PACKET_CONTROL10 0 0x20a5 16 0 2 HDMI_GENERIC14_LINE 0 15 HDMI_GENERIC0_EN_DB_PENDING 16 16 HDMI_GENERIC1_EN_DB_PENDING 17 17 HDMI_GENERIC2_EN_DB_PENDING 18 18 HDMI_GENERIC3_EN_DB_PENDING 19 19 HDMI_GENERIC4_EN_DB_PENDING 20 20 HDMI_GENERIC5_EN_DB_PENDING 21 21 HDMI_GENERIC6_EN_DB_PENDING 22 22 HDMI_GENERIC7_EN_DB_PENDING 23 23 HDMI_GENERIC8_EN_DB_PENDING 24 24 HDMI_GENERIC9_EN_DB_PENDING 25 25 HDMI_GENERIC10_EN_DB_PENDING 26 26 HDMI_GENERIC11_EN_DB_PENDING 27 27 HDMI_GENERIC12_EN_DB_PENDING 28 28 HDMI_GENERIC13_EN_DB_PENDING 29 29 HDMI_GENERIC14_EN_DB_PENDING 30 30 regDIG0_HDMI_DB_CONTROL 0 0x20a6 8 0 2 HDMI_DB_PENDING 0 0 HDMI_DB_TAKEN 4 4 HDMI_DB_TAKEN_CLR 5 5 HDMI_DB_LOCK 8 8 HDMI_DB_DISABLE 12 12 VUPDATE_DB_PENDING 15 15 VUPDATE_DB_TAKEN 16 16 VUPDATE_DB_TAKEN_CLR 17 17 regDIG0_HDMI_ACR_32_0 0 0x20a7 1 0 2 HDMI_ACR_CTS_32 12 31 regDIG0_HDMI_ACR_32_1 0 0x20a8 1 0 2 HDMI_ACR_N_32 0 19 regDIG0_HDMI_ACR_44_0 0 0x20a9 1 0 2 HDMI_ACR_CTS_44 12 31 regDIG0_HDMI_ACR_44_1 0 0x20aa 1 0 2 HDMI_ACR_N_44 0 19 regDIG0_HDMI_ACR_48_0 0 0x20ab 1 0 2 HDMI_ACR_CTS_48 12 31 regDIG0_HDMI_ACR_48_1 0 0x20ac 1 0 2 HDMI_ACR_N_48 0 19 regDIG0_HDMI_ACR_STATUS_0 0 0x20ad 1 0 2 HDMI_ACR_CTS 12 31 regDIG0_HDMI_ACR_STATUS_1 0 0x20ae 1 0 2 HDMI_ACR_N 0 19 regDIG0_AFMT_CNTL 0 0x20af 2 0 2 AFMT_AUDIO_CLOCK_EN 0 0 AFMT_AUDIO_CLOCK_ON 8 8 regDIG0_DIG_BE_CNTL 0 0x20b0 6 0 2 DIG_DUAL_LINK_ENABLE 0 0 DIG_SWAP 1 1 DIG_RB_SWITCH_EN 2 2 DIG_FE_SOURCE_SELECT 8 14 DIG_MODE 16 18 DIG_HPD_SELECT 28 30 regDIG0_DIG_BE_EN_CNTL 0 0x20b1 2 0 2 DIG_ENABLE 0 0 DIG_SYMCLK_BE_ON 8 8 regDIG0_TMDS_CNTL 0 0x20d7 1 0 2 TMDS_SYNC_PHASE 0 0 regDIG0_TMDS_CONTROL_CHAR 0 0x20d8 4 0 2 TMDS_CONTROL_CHAR0_OUT_EN 0 0 TMDS_CONTROL_CHAR1_OUT_EN 1 1 TMDS_CONTROL_CHAR2_OUT_EN 2 2 TMDS_CONTROL_CHAR3_OUT_EN 3 3 regDIG0_TMDS_CONTROL0_FEEDBACK 0 0x20d9 2 0 2 TMDS_CONTROL0_FEEDBACK_SELECT 0 1 TMDS_CONTROL0_FEEDBACK_DELAY 8 9 regDIG0_TMDS_STEREOSYNC_CTL_SEL 0 0x20da 1 0 2 TMDS_STEREOSYNC_CTL_SEL 0 1 regDIG0_TMDS_SYNC_CHAR_PATTERN_0_1 0 0x20db 2 0 2 TMDS_SYNC_CHAR_PATTERN0 0 9 TMDS_SYNC_CHAR_PATTERN1 16 25 regDIG0_TMDS_SYNC_CHAR_PATTERN_2_3 0 0x20dc 2 0 2 TMDS_SYNC_CHAR_PATTERN2 0 9 TMDS_SYNC_CHAR_PATTERN3 16 25 regDIG0_TMDS_CTL_BITS 0 0x20de 4 0 2 TMDS_CTL0 0 0 TMDS_CTL1 8 8 TMDS_CTL2 16 16 TMDS_CTL3 24 24 regDIG0_TMDS_DCBALANCER_CONTROL 0 0x20df 5 0 2 TMDS_DCBALANCER_EN 0 0 TMDS_SYNC_DCBAL_EN 4 6 TMDS_DCBALANCER_TEST_EN 8 8 TMDS_DCBALANCER_TEST_IN 16 19 TMDS_DCBALANCER_FORCE 24 24 regDIG0_TMDS_SYNC_DCBALANCE_CHAR 0 0x20e0 2 0 2 TMDS_SYNC_DCBAL_CHAR01 0 9 TMDS_SYNC_DCBAL_CHAR11 16 25 regDIG0_TMDS_CTL0_1_GEN_CNTL 0 0x20e1 15 0 2 TMDS_CTL0_DATA_SEL 0 3 TMDS_CTL0_DATA_DELAY 4 6 TMDS_CTL0_DATA_INVERT 7 7 TMDS_CTL0_DATA_MODULATION 8 9 TMDS_CTL0_USE_FEEDBACK_PATH 10 10 TMDS_CTL0_FB_SYNC_CONT 11 11 TMDS_CTL0_PATTERN_OUT_EN 12 12 TMDS_CTL1_DATA_SEL 16 19 TMDS_CTL1_DATA_DELAY 20 22 TMDS_CTL1_DATA_INVERT 23 23 TMDS_CTL1_DATA_MODULATION 24 25 TMDS_CTL1_USE_FEEDBACK_PATH 26 26 TMDS_CTL1_FB_SYNC_CONT 27 27 TMDS_CTL1_PATTERN_OUT_EN 28 28 TMDS_2BIT_COUNTER_EN 31 31 regDIG0_TMDS_CTL2_3_GEN_CNTL 0 0x20e2 14 0 2 TMDS_CTL2_DATA_SEL 0 3 TMDS_CTL2_DATA_DELAY 4 6 TMDS_CTL2_DATA_INVERT 7 7 TMDS_CTL2_DATA_MODULATION 8 9 TMDS_CTL2_USE_FEEDBACK_PATH 10 10 TMDS_CTL2_FB_SYNC_CONT 11 11 TMDS_CTL2_PATTERN_OUT_EN 12 12 TMDS_CTL3_DATA_SEL 16 19 TMDS_CTL3_DATA_DELAY 20 22 TMDS_CTL3_DATA_INVERT 23 23 TMDS_CTL3_DATA_MODULATION 24 25 TMDS_CTL3_USE_FEEDBACK_PATH 26 26 TMDS_CTL3_FB_SYNC_CONT 27 27 TMDS_CTL3_PATTERN_OUT_EN 28 28 regDIG0_DIG_VERSION 0 0x20e4 1 0 2 DIG_TYPE 0 0 regDIG0_FORCE_DIG_DISABLE 0 0x20e5 1 0 2 FORCE_DIG_DISABLE 0 0 regDP1_DP_LINK_CNTL 0 0x2208 3 0 2 DP_LINK_TRAINING_COMPLETE 4 4 DP_LINK_STATUS 8 8 DP_EMBEDDED_PANEL_MODE 17 17 regDP1_DP_PIXEL_FORMAT 0 0x2209 3 0 2 DP_PIXEL_ENCODING 0 2 DP_COMPONENT_DEPTH 24 26 DP_PIXEL_COMBINE 28 29 regDP1_DP_MSA_COLORIMETRY 0 0x220a 1 0 2 DP_MSA_MISC0 24 31 regDP1_DP_CONFIG 0 0x220b 1 0 2 DP_UDI_LANES 0 1 regDP1_DP_VID_STREAM_CNTL 0 0x220c 4 0 2 DP_VID_STREAM_ENABLE 0 0 DP_VID_STREAM_DIS_DEFER 8 9 DP_VID_STREAM_STATUS 16 16 DP_VID_STREAM_CHANGE_KEEPOUT 20 20 regDP1_DP_STEER_FIFO 0 0x220d 7 0 2 DP_STEER_FIFO_RESET 0 0 DP_STEER_OVERFLOW_FLAG 4 4 DP_STEER_OVERFLOW_INT 5 5 DP_STEER_OVERFLOW_ACK 6 6 DP_STEER_OVERFLOW_MASK 7 7 DP_TU_OVERFLOW_FLAG 8 8 DP_TU_OVERFLOW_ACK 12 12 regDP1_DP_MSA_MISC 0 0x220e 4 0 2 DP_MSA_MISC1 0 7 DP_MSA_MISC2 8 15 DP_MSA_MISC3 16 23 DP_MSA_MISC4 24 31 regDP1_DP_DPHY_INTERNAL_CTRL 0 0x220f 2 0 2 DPHY_ALT_SCRAMBLER_RESET_EN 0 0 DPHY_ALT_SCRAMBLER_RESET_SEL 4 4 regDP1_DP_VID_TIMING 0 0x2210 5 0 2 DP_VID_M_N_DOUBLE_BUFFER_MODE 4 4 DP_VID_M_N_GEN_EN 8 8 DP_VID_N_MUL 10 11 DP_VID_M_DIV 12 13 DP_VID_N_DIV 24 31 regDP1_DP_VID_N 0 0x2211 1 0 2 DP_VID_N 0 23 regDP1_DP_VID_M 0 0x2212 1 0 2 DP_VID_M 0 23 regDP1_DP_LINK_FRAMING_CNTL 0 0x2213 3 0 2 DP_IDLE_BS_INTERVAL 0 17 DP_VBID_DISABLE 24 24 DP_VID_ENHANCED_FRAME_MODE 28 28 regDP1_DP_HBR2_EYE_PATTERN 0 0x2214 1 0 2 DP_HBR2_EYE_PATTERN_ENABLE 0 0 regDP1_DP_VID_MSA_VBID 0 0x2215 2 0 2 DP_VID_MSA_LOCATION 0 11 DP_VID_VBID_FIELD_POL 24 24 regDP1_DP_VID_INTERRUPT_CNTL 0 0x2216 3 0 2 DP_VID_STREAM_DISABLE_INT 0 0 DP_VID_STREAM_DISABLE_ACK 1 1 DP_VID_STREAM_DISABLE_MASK 2 2 regDP1_DP_DPHY_CNTL 0 0x2217 10 0 2 DPHY_ATEST_SEL_LANE0 0 0 DPHY_ATEST_SEL_LANE1 1 1 DPHY_ATEST_SEL_LANE2 2 2 DPHY_ATEST_SEL_LANE3 3 3 DPHY_FEC_EN 4 4 DPHY_FEC_READY_SHADOW 5 5 DPHY_FEC_ACTIVE_STATUS 6 6 DPHY_SCRAMBLER_SEL 8 8 DPHY_BYPASS 16 16 DPHY_SKEW_BYPASS 24 24 regDP1_DP_DPHY_TRAINING_PATTERN_SEL 0 0x2218 1 0 2 DPHY_TRAINING_PATTERN_SEL 0 1 regDP1_DP_DPHY_SYM0 0 0x2219 3 0 2 DPHY_SYM1 0 9 DPHY_SYM2 10 19 DPHY_SYM3 20 29 regDP1_DP_DPHY_SYM1 0 0x221a 3 0 2 DPHY_SYM4 0 9 DPHY_SYM5 10 19 DPHY_SYM6 20 29 regDP1_DP_DPHY_SYM2 0 0x221b 2 0 2 DPHY_SYM7 0 9 DPHY_SYM8 10 19 regDP1_DP_DPHY_8B10B_CNTL 0 0x221c 3 0 2 DPHY_8B10B_RESET 8 8 DPHY_8B10B_EXT_DISP 16 16 DPHY_8B10B_CUR_DISP 24 24 regDP1_DP_DPHY_PRBS_CNTL 0 0x221d 3 0 2 DPHY_PRBS_EN 0 0 DPHY_PRBS_SEL 4 5 DPHY_PRBS_SEED 8 30 regDP1_DP_DPHY_SCRAM_CNTL 0 0x221e 4 0 2 DPHY_SCRAMBLER_DIS 0 0 DPHY_SCRAMBLER_ADVANCE 4 4 DPHY_SCRAMBLER_BS_COUNT 8 17 DPHY_SCRAMBLER_KCODE 24 24 regDP1_DP_DPHY_CRC_EN 0 0x221f 3 0 2 DPHY_CRC_EN 0 0 DPHY_CRC_CONT_EN 4 4 DPHY_CRC_RESULT_VALID 8 8 regDP1_DP_DPHY_CRC_CNTL 0 0x2220 3 0 2 DPHY_CRC_FIELD 0 0 DPHY_CRC_SEL 4 5 DPHY_CRC_MASK 16 23 regDP1_DP_DPHY_CRC_RESULT 0 0x2221 4 0 2 DPHY_CRC_RESULT 0 7 DPHY_CRC_RESULT1 8 15 DPHY_CRC_RESULT2 16 23 DPHY_CRC_RESULT3 24 31 regDP1_DP_DPHY_CRC_MST_CNTL 0 0x2222 2 0 2 DPHY_CRC_MST_FIRST_SLOT 0 5 DPHY_CRC_MST_LAST_SLOT 8 13 regDP1_DP_DPHY_CRC_MST_STATUS 0 0x2223 3 0 2 DPHY_CRC_MST_PHASE_LOCK 0 0 DPHY_CRC_MST_PHASE_ERROR 8 8 DPHY_CRC_MST_PHASE_ERROR_ACK 16 16 regDP1_DP_DPHY_FAST_TRAINING 0 0x2224 6 0 2 DPHY_RX_FAST_TRAINING_CAPABLE 0 0 DPHY_SW_FAST_TRAINING_START 1 1 DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN 2 2 DPHY_STREAM_RESET_DURING_FAST_TRAINING 4 4 DPHY_FAST_TRAINING_TP1_TIME 8 19 DPHY_FAST_TRAINING_TP2_TIME 20 31 regDP1_DP_DPHY_FAST_TRAINING_STATUS 0 0x2225 4 0 2 DPHY_FAST_TRAINING_STATE 0 2 DPHY_FAST_TRAINING_COMPLETE_OCCURRED 4 4 DPHY_FAST_TRAINING_COMPLETE_MASK 8 8 DPHY_FAST_TRAINING_COMPLETE_ACK 12 12 regDP1_DP_SEC_CNTL 0 0x222b 14 0 2 DP_SEC_STREAM_ENABLE 0 0 DP_SEC_ASP_ENABLE 4 4 DP_SEC_ATP_ENABLE 8 8 DP_SEC_AIP_ENABLE 12 12 DP_SEC_ACM_ENABLE 16 16 DP_SEC_GSP0_ENABLE 20 20 DP_SEC_GSP1_ENABLE 21 21 DP_SEC_GSP2_ENABLE 22 22 DP_SEC_GSP3_ENABLE 23 23 DP_SEC_GSP4_ENABLE 24 24 DP_SEC_GSP5_ENABLE 25 25 DP_SEC_GSP6_ENABLE 26 26 DP_SEC_GSP7_ENABLE 27 27 DP_SEC_MPG_ENABLE 28 28 regDP1_DP_SEC_CNTL1 0 0x222c 15 0 2 DP_SEC_ISRC_ENABLE 0 0 DP_SEC_GSP0_LINE_REFERENCE 1 1 DP_SEC_GSP0_PRIORITY 4 4 DP_SEC_GSP0_SEND 5 5 DP_SEC_GSP0_SEND_PENDING 6 6 DP_SEC_GSP0_SEND_DEADLINE_MISSED 7 7 DP_SEC_GSP0_SEND_ANY_LINE 8 8 DP_SEC_GSP1_LINE_REFERENCE 9 9 DP_SEC_GSP2_LINE_REFERENCE 10 10 DP_SEC_GSP3_LINE_REFERENCE 11 11 DP_SEC_GSP4_LINE_REFERENCE 12 12 DP_SEC_GSP5_LINE_REFERENCE 13 13 DP_SEC_GSP6_LINE_REFERENCE 14 14 DP_SEC_GSP7_LINE_REFERENCE 15 15 DP_SEC_GSP0_LINE_NUM 16 31 regDP1_DP_SEC_FRAMING1 0 0x222d 2 0 2 DP_SEC_FRAME_START_LOCATION 0 11 DP_SEC_VBLANK_TRANSMIT_WIDTH 16 31 regDP1_DP_SEC_FRAMING2 0 0x222e 2 0 2 DP_SEC_START_POSITION 0 15 DP_SEC_HBLANK_TRANSMIT_WIDTH 16 31 regDP1_DP_SEC_FRAMING3 0 0x222f 2 0 2 DP_SEC_IDLE_FRAME_SIZE 0 13 DP_SEC_IDLE_TRANSMIT_WIDTH 16 31 regDP1_DP_SEC_FRAMING4 0 0x2230 5 0 2 DP_SST_SDP_SPLITTING 0 0 DP_SEC_COLLISION_STATUS 20 20 DP_SEC_COLLISION_ACK 24 24 DP_SEC_AUDIO_MUTE 28 28 DP_SEC_AUDIO_MUTE_STATUS 29 29 regDP1_DP_SEC_AUD_N 0 0x2231 1 0 2 DP_SEC_AUD_N 0 23 regDP1_DP_SEC_AUD_N_READBACK 0 0x2232 1 0 2 DP_SEC_AUD_N_READBACK 0 23 regDP1_DP_SEC_AUD_M 0 0x2233 1 0 2 DP_SEC_AUD_M 0 23 regDP1_DP_SEC_AUD_M_READBACK 0 0x2234 1 0 2 DP_SEC_AUD_M_READBACK 0 23 regDP1_DP_SEC_TIMESTAMP 0 0x2235 1 0 2 DP_SEC_TIMESTAMP_MODE 0 0 regDP1_DP_SEC_PACKET_CNTL 0 0x2236 4 0 2 DP_SEC_ASP_CODING_TYPE 1 3 DP_SEC_ASP_PRIORITY 4 4 DP_SEC_VERSION 8 13 DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE 16 16 regDP1_DP_MSE_RATE_CNTL 0 0x2237 2 0 2 DP_MSE_RATE_Y 0 25 DP_MSE_RATE_X 26 31 regDP1_DP_MSE_RATE_UPDATE 0 0x2239 1 0 2 DP_MSE_RATE_UPDATE_PENDING 0 0 regDP1_DP_MSE_SAT0 0 0x223a 8 0 2 DP_MSE_SAT_SRC0 0 2 DP_MSE_SAT_ENCRYPT0 4 4 DP_MSE_SAT_ENCRYPTION_TYPE0 5 5 DP_MSE_SAT_SLOT_COUNT0 8 13 DP_MSE_SAT_SRC1 16 18 DP_MSE_SAT_ENCRYPT1 20 20 DP_MSE_SAT_ENCRYPTION_TYPE1 21 21 DP_MSE_SAT_SLOT_COUNT1 24 29 regDP1_DP_MSE_SAT1 0 0x223b 8 0 2 DP_MSE_SAT_SRC2 0 2 DP_MSE_SAT_ENCRYPT2 4 4 DP_MSE_SAT_ENCRYPTION_TYPE2 5 5 DP_MSE_SAT_SLOT_COUNT2 8 13 DP_MSE_SAT_SRC3 16 18 DP_MSE_SAT_ENCRYPT3 20 20 DP_MSE_SAT_ENCRYPTION_TYPE3 21 21 DP_MSE_SAT_SLOT_COUNT3 24 29 regDP1_DP_MSE_SAT2 0 0x223c 8 0 2 DP_MSE_SAT_SRC4 0 2 DP_MSE_SAT_ENCRYPT4 4 4 DP_MSE_SAT_ENCRYPTION_TYPE4 5 5 DP_MSE_SAT_SLOT_COUNT4 8 13 DP_MSE_SAT_SRC5 16 18 DP_MSE_SAT_ENCRYPT5 20 20 DP_MSE_SAT_ENCRYPTION_TYPE5 21 21 DP_MSE_SAT_SLOT_COUNT5 24 29 regDP1_DP_MSE_SAT_UPDATE 0 0x223d 2 0 2 DP_MSE_SAT_UPDATE 0 1 DP_MSE_16_MTP_KEEPOUT 8 8 regDP1_DP_MSE_LINK_TIMING 0 0x223e 2 0 2 DP_MSE_LINK_FRAME 0 9 DP_MSE_LINK_LINE 16 17 regDP1_DP_MSE_MISC_CNTL 0 0x223f 3 0 2 DP_MSE_BLANK_CODE 0 0 DP_MSE_TIMESTAMP_MODE 4 4 DP_MSE_ZERO_ENCODER 8 8 regDP1_DP_DPHY_BS_SR_SWAP_CNTL 0 0x2244 3 0 2 DPHY_LOAD_BS_COUNT 0 9 DPHY_BS_SR_SWAP_DONE 15 15 DPHY_LOAD_BS_COUNT_START 16 16 regDP1_DP_DPHY_HBR2_PATTERN_CONTROL 0 0x2245 1 0 2 DP_DPHY_HBR2_PATTERN_CONTROL 0 2 regDP1_DP_MSE_SAT0_STATUS 0 0x2247 8 0 2 DP_MSE_SAT_SRC0_STATUS 0 2 DP_MSE_SAT_ENCRYPT0_STATUS 4 4 DP_MSE_SAT_ENCRYPTION_TYPE0_STATUS 5 5 DP_MSE_SAT_SLOT_COUNT0_STATUS 8 13 DP_MSE_SAT_SRC1_STATUS 16 18 DP_MSE_SAT_ENCRYPT1_STATUS 20 20 DP_MSE_SAT_ENCRYPTION_TYPE1_STATUS 21 21 DP_MSE_SAT_SLOT_COUNT1_STATUS 24 29 regDP1_DP_MSE_SAT1_STATUS 0 0x2248 8 0 2 DP_MSE_SAT_SRC2_STATUS 0 2 DP_MSE_SAT_ENCRYPT2_STATUS 4 4 DP_MSE_SAT_ENCRYPTION_TYPE2_STATUS 5 5 DP_MSE_SAT_SLOT_COUNT2_STATUS 8 13 DP_MSE_SAT_SRC3_STATUS 16 18 DP_MSE_SAT_ENCRYPT3_STATUS 20 20 DP_MSE_SAT_ENCRYPTION_TYPE3_STATUS 21 21 DP_MSE_SAT_SLOT_COUNT3_STATUS 24 29 regDP1_DP_MSE_SAT2_STATUS 0 0x2249 8 0 2 DP_MSE_SAT_SRC4_STATUS 0 2 DP_MSE_SAT_ENCRYPT4_STATUS 4 4 DP_MSE_SAT_ENCRYPTION_TYPE4_STATUS 5 5 DP_MSE_SAT_SLOT_COUNT4_STATUS 8 13 DP_MSE_SAT_SRC5_STATUS 16 18 DP_MSE_SAT_ENCRYPT5_STATUS 20 20 DP_MSE_SAT_ENCRYPTION_TYPE5_STATUS 21 21 DP_MSE_SAT_SLOT_COUNT5_STATUS 24 29 regDP1_DP_MSA_TIMING_PARAM1 0 0x224c 2 0 2 DP_MSA_VTOTAL 0 15 DP_MSA_HTOTAL 16 31 regDP1_DP_MSA_TIMING_PARAM2 0 0x224d 2 0 2 DP_MSA_VSTART 0 15 DP_MSA_HSTART 16 31 regDP1_DP_MSA_TIMING_PARAM3 0 0x224e 4 0 2 DP_MSA_VSYNCWIDTH 0 14 DP_MSA_VSYNCPOLARITY 15 15 DP_MSA_HSYNCWIDTH 16 30 DP_MSA_HSYNCPOLARITY 31 31 regDP1_DP_MSA_TIMING_PARAM4 0 0x224f 2 0 2 DP_MSA_VHEIGHT 0 15 DP_MSA_HWIDTH 16 31 regDP1_DP_MSO_CNTL 0 0x2250 8 0 2 DP_MSO_NUM_OF_SSTLINK 0 1 DP_MSO_SEC_STREAM_ENABLE 4 7 DP_MSO_SEC_ASP_ENABLE 8 11 DP_MSO_SEC_ATP_ENABLE 12 15 DP_MSO_SEC_AIP_ENABLE 16 19 DP_MSO_SEC_ACM_ENABLE 20 23 DP_MSO_SEC_GSP0_ENABLE 24 27 DP_MSO_SEC_GSP1_ENABLE 28 31 regDP1_DP_MSO_CNTL1 0 0x2251 8 0 2 DP_MSO_SEC_GSP2_ENABLE 0 3 DP_MSO_SEC_GSP3_ENABLE 4 7 DP_MSO_SEC_GSP4_ENABLE 8 11 DP_MSO_SEC_GSP5_ENABLE 12 15 DP_MSO_SEC_GSP6_ENABLE 16 19 DP_MSO_SEC_GSP7_ENABLE 20 23 DP_MSO_SEC_MPG_ENABLE 24 27 DP_MSO_SEC_ISRC_ENABLE 28 31 regDP1_DP_DSC_CNTL 0 0x2252 2 0 2 DP_DSC_MODE 0 1 DP_DSC_SLICE_WIDTH 16 28 regDP1_DP_SEC_CNTL2 0 0x2253 29 0 2 DP_SEC_GSP1_SEND 0 0 DP_SEC_GSP1_SEND_PENDING 1 1 DP_SEC_GSP1_SEND_DEADLINE_MISSED 2 2 DP_SEC_GSP1_SEND_ANY_LINE 3 3 DP_SEC_GSP2_SEND 4 4 DP_SEC_GSP2_SEND_PENDING 5 5 DP_SEC_GSP2_SEND_DEADLINE_MISSED 6 6 DP_SEC_GSP2_SEND_ANY_LINE 7 7 DP_SEC_GSP3_SEND 8 8 DP_SEC_GSP3_SEND_PENDING 9 9 DP_SEC_GSP3_SEND_DEADLINE_MISSED 10 10 DP_SEC_GSP3_SEND_ANY_LINE 11 11 DP_SEC_GSP4_SEND 12 12 DP_SEC_GSP4_SEND_PENDING 13 13 DP_SEC_GSP4_SEND_DEADLINE_MISSED 14 14 DP_SEC_GSP4_SEND_ANY_LINE 15 15 DP_SEC_GSP5_SEND 16 16 DP_SEC_GSP5_SEND_PENDING 17 17 DP_SEC_GSP5_SEND_DEADLINE_MISSED 18 18 DP_SEC_GSP5_SEND_ANY_LINE 19 19 DP_SEC_GSP6_SEND 20 20 DP_SEC_GSP6_SEND_PENDING 21 21 DP_SEC_GSP6_SEND_DEADLINE_MISSED 22 22 DP_SEC_GSP6_SEND_ANY_LINE 23 23 DP_SEC_GSP7_SEND 24 24 DP_SEC_GSP7_SEND_PENDING 25 25 DP_SEC_GSP7_SEND_DEADLINE_MISSED 26 26 DP_SEC_GSP7_SEND_ANY_LINE 27 27 DP_SEC_GSP11_PPS 28 28 regDP1_DP_SEC_CNTL3 0 0x2254 2 0 2 DP_SEC_GSP1_LINE_NUM 0 15 DP_SEC_GSP2_LINE_NUM 16 31 regDP1_DP_SEC_CNTL4 0 0x2255 2 0 2 DP_SEC_GSP3_LINE_NUM 0 15 DP_SEC_GSP4_LINE_NUM 16 31 regDP1_DP_SEC_CNTL5 0 0x2256 2 0 2 DP_SEC_GSP5_LINE_NUM 0 15 DP_SEC_GSP6_LINE_NUM 16 31 regDP1_DP_SEC_CNTL6 0 0x2257 13 0 2 DP_SEC_GSP7_LINE_NUM 0 15 DP_SEC_GSP0_EN_DB_DISABLE 16 16 DP_SEC_GSP1_EN_DB_DISABLE 17 17 DP_SEC_GSP2_EN_DB_DISABLE 18 18 DP_SEC_GSP3_EN_DB_DISABLE 19 19 DP_SEC_GSP4_EN_DB_DISABLE 20 20 DP_SEC_GSP5_EN_DB_DISABLE 21 21 DP_SEC_GSP6_EN_DB_DISABLE 22 22 DP_SEC_GSP7_EN_DB_DISABLE 23 23 DP_SEC_GSP8_EN_DB_DISABLE 24 24 DP_SEC_GSP9_EN_DB_DISABLE 25 25 DP_SEC_GSP10_EN_DB_DISABLE 26 26 DP_SEC_GSP11_EN_DB_DISABLE 27 27 regDP1_DP_SEC_CNTL7 0 0x2258 16 0 2 DP_SEC_GSP0_SEND_ACTIVE 0 0 DP_SEC_GSP0_SEND_IN_IDLE 1 1 DP_SEC_GSP1_SEND_ACTIVE 4 4 DP_SEC_GSP1_SEND_IN_IDLE 5 5 DP_SEC_GSP2_SEND_ACTIVE 8 8 DP_SEC_GSP2_SEND_IN_IDLE 9 9 DP_SEC_GSP3_SEND_ACTIVE 12 12 DP_SEC_GSP3_SEND_IN_IDLE 13 13 DP_SEC_GSP4_SEND_ACTIVE 16 16 DP_SEC_GSP4_SEND_IN_IDLE 17 17 DP_SEC_GSP5_SEND_ACTIVE 20 20 DP_SEC_GSP5_SEND_IN_IDLE 21 21 DP_SEC_GSP6_SEND_ACTIVE 24 24 DP_SEC_GSP6_SEND_IN_IDLE 25 25 DP_SEC_GSP7_SEND_ACTIVE 28 28 DP_SEC_GSP7_SEND_IN_IDLE 29 29 regDP1_DP_DB_CNTL 0 0x2259 8 0 2 DP_DB_PENDING 0 0 DP_DB_TAKEN 4 4 DP_DB_TAKEN_CLR 5 5 DP_DB_LOCK 8 8 DP_DB_DISABLE 12 12 DP_VUPDATE_DB_PENDING 15 15 DP_VUPDATE_DB_TAKEN 16 16 DP_VUPDATE_DB_TAKEN_CLR 17 17 regDP1_DP_MSA_VBID_MISC 0 0x225a 8 0 2 DP_MSA_MISC1_STEREOSYNC_OVERRIDE 0 1 DP_MSA_MISC1_STEREOSYNC_OVERRIDE_EN 4 4 DP_VBID1_OVERRIDE 8 8 DP_VBID2_OVERRIDE 9 9 DP_VBID1_OVERRIDE_EN 12 12 DP_VBID2_OVERRIDE_EN 13 13 DP_VBID6_LINE_REFERENCE 15 15 DP_VBID6_LINE_NUM 16 31 regDP1_DP_SEC_METADATA_TRANSMISSION 0 0x225b 4 0 2 DP_SEC_METADATA_PACKET_ENABLE 0 0 DP_SEC_METADATA_PACKET_LINE_REFERENCE 1 1 DP_SEC_MSO_METADATA_PACKET_ENABLE 4 7 DP_SEC_METADATA_PACKET_LINE 16 31 regDP1_DP_DSC_BYTES_PER_PIXEL 0 0x225c 1 0 2 DP_DSC_BYTES_PER_PIXEL 0 30 regDP1_DP_ALPM_CNTL 0 0x225d 7 0 2 DP_ML_PHY_SLEEP_SEND 0 0 DP_ML_PHY_SLEEP_PENDING 1 1 DP_ML_PHY_STANDBY_SEND 2 2 DP_ML_PHY_STANDBY_PENDING 3 3 DP_ML_PHY_SLEEP_STANDBY_IMMEDIATE 4 4 DP_LINK_TRAINING_SWITCH_BETWEEN_VIDEO 5 5 DP_ML_PHY_SLEEP_STANDBY_LINE_NUM 16 31 regDP1_DP_GSP8_CNTL 0 0x225e 10 0 2 DP_MSO_SEC_GSP8_ENABLE 0 3 DP_SEC_GSP8_ENABLE 4 4 DP_SEC_GSP8_LINE_REFERENCE 5 5 DP_SEC_GSP8_SEND_IN_IDLE 6 6 DP_SEC_GSP8_SEND 7 7 DP_SEC_GSP8_SEND_ANY_LINE 8 8 DP_SEC_GSP8_SEND_PENDING 12 12 DP_SEC_GSP8_SEND_ACTIVE 13 13 DP_SEC_GSP8_SEND_DEADLINE_MISSED 14 14 DP_SEC_GSP8_LINE_NUM 16 31 regDP1_DP_GSP9_CNTL 0 0x225f 10 0 2 DP_MSO_SEC_GSP9_ENABLE 0 3 DP_SEC_GSP9_ENABLE 4 4 DP_SEC_GSP9_LINE_REFERENCE 5 5 DP_SEC_GSP9_SEND_IN_IDLE 6 6 DP_SEC_GSP9_SEND 7 7 DP_SEC_GSP9_SEND_ANY_LINE 8 8 DP_SEC_GSP9_SEND_PENDING 12 12 DP_SEC_GSP9_SEND_ACTIVE 13 13 DP_SEC_GSP9_SEND_DEADLINE_MISSED 14 14 DP_SEC_GSP9_LINE_NUM 16 31 regDP1_DP_GSP10_CNTL 0 0x2260 10 0 2 DP_MSO_SEC_GSP10_ENABLE 0 3 DP_SEC_GSP10_ENABLE 4 4 DP_SEC_GSP10_LINE_REFERENCE 5 5 DP_SEC_GSP10_SEND_IN_IDLE 6 6 DP_SEC_GSP10_SEND 7 7 DP_SEC_GSP10_SEND_ANY_LINE 8 8 DP_SEC_GSP10_SEND_PENDING 12 12 DP_SEC_GSP10_SEND_ACTIVE 13 13 DP_SEC_GSP10_SEND_DEADLINE_MISSED 14 14 DP_SEC_GSP10_LINE_NUM 16 31 regDP1_DP_GSP11_CNTL 0 0x2261 10 0 2 DP_MSO_SEC_GSP11_ENABLE 0 3 DP_SEC_GSP11_ENABLE 4 4 DP_SEC_GSP11_LINE_REFERENCE 5 5 DP_SEC_GSP11_SEND_IN_IDLE 6 6 DP_SEC_GSP11_SEND 7 7 DP_SEC_GSP11_SEND_ANY_LINE 8 8 DP_SEC_GSP11_SEND_PENDING 12 12 DP_SEC_GSP11_SEND_ACTIVE 13 13 DP_SEC_GSP11_SEND_DEADLINE_MISSED 14 14 DP_SEC_GSP11_LINE_NUM 16 31 regDP1_DP_GSP_EN_DB_STATUS 0 0x2262 12 0 2 DP_SEC_GSP0_EN_DB_PENDING 0 0 DP_SEC_GSP1_EN_DB_PENDING 1 1 DP_SEC_GSP2_EN_DB_PENDING 2 2 DP_SEC_GSP3_EN_DB_PENDING 3 3 DP_SEC_GSP4_EN_DB_PENDING 4 4 DP_SEC_GSP5_EN_DB_PENDING 5 5 DP_SEC_GSP6_EN_DB_PENDING 6 6 DP_SEC_GSP7_EN_DB_PENDING 7 7 DP_SEC_GSP8_EN_DB_PENDING 8 8 DP_SEC_GSP9_EN_DB_PENDING 9 9 DP_SEC_GSP10_EN_DB_PENDING 10 10 DP_SEC_GSP11_EN_DB_PENDING 11 11 regDIG1_DIG_FE_CNTL 0 0x218b 11 0 2 DIG_SOURCE_SELECT 0 2 DIG_STEREOSYNC_SELECT 4 6 DIG_STEREOSYNC_GATE_EN 8 8 DIG_START 10 10 DIG_DIGITAL_BYPASS_SELECT 12 14 DIG_INPUT_PIXEL_SELECT 16 17 DOLBY_VISION_EN 18 18 DOLBY_VISION_METADATA_PACKET_MISSED 19 19 DIG_SYMCLK_FE_ON 24 24 TMDS_PIXEL_ENCODING 28 28 TMDS_COLOR_FORMAT 30 31 regDIG1_DIG_OUTPUT_CRC_CNTL 0 0x218c 3 0 2 DIG_OUTPUT_CRC_EN 0 0 DIG_OUTPUT_CRC_LINK_SEL 4 4 DIG_OUTPUT_CRC_DATA_SEL 8 9 regDIG1_DIG_OUTPUT_CRC_RESULT 0 0x218d 1 0 2 DIG_OUTPUT_CRC_RESULT 0 29 regDIG1_DIG_CLOCK_PATTERN 0 0x218e 1 0 2 DIG_CLOCK_PATTERN 0 9 regDIG1_DIG_TEST_PATTERN 0 0x218f 6 0 2 DIG_TEST_PATTERN_OUT_EN 0 0 DIG_HALF_CLOCK_PATTERN_SEL 1 1 DIG_RANDOM_PATTERN_OUT_EN 4 4 DIG_RANDOM_PATTERN_RESET 5 5 DIG_TEST_PATTERN_EXTERNAL_RESET_EN 6 6 DIG_STATIC_TEST_PATTERN 16 25 regDIG1_DIG_RANDOM_PATTERN_SEED 0 0x2190 2 0 2 DIG_RANDOM_PATTERN_SEED 0 23 DIG_RAN_PAT_DURING_DE_ONLY 24 24 regDIG1_DIG_FIFO_STATUS 0 0x2191 11 0 2 DIG_FIFO_LEVEL_ERROR 0 0 DIG_FIFO_USE_OVERWRITE_LEVEL 1 1 DIG_FIFO_OVERWRITE_LEVEL 2 7 DIG_FIFO_ERROR_ACK 8 8 DIG_FIFO_CAL_AVERAGE_LEVEL 10 15 DIG_FIFO_MAXIMUM_LEVEL 16 20 DIG_FIFO_MINIMUM_LEVEL 22 25 DIG_FIFO_READ_CLOCK_SRC 26 26 DIG_FIFO_CALIBRATED 29 29 DIG_FIFO_FORCE_RECAL_AVERAGE 30 30 DIG_FIFO_FORCE_RECOMP_MINMAX 31 31 regDIG1_HDMI_METADATA_PACKET_CONTROL 0 0x2192 4 0 2 HDMI_METADATA_PACKET_ENABLE 0 0 HDMI_METADATA_PACKET_LINE_REFERENCE 4 4 HDMI_METADATA_PACKET_MISSED 8 8 HDMI_METADATA_PACKET_LINE 16 31 regDIG1_HDMI_CONTROL 0 0x2193 10 0 2 HDMI_KEEPOUT_MODE 0 0 HDMI_DATA_SCRAMBLE_EN 1 1 HDMI_CLOCK_CHANNEL_RATE 2 2 HDMI_NO_EXTRA_NULL_PACKET_FILLED 3 3 HDMI_PACKET_GEN_VERSION 4 4 HDMI_ERROR_ACK 8 8 HDMI_ERROR_MASK 9 9 HDMI_UNSCRAMBLED_CONTROL_LINE_NUM 16 21 HDMI_DEEP_COLOR_ENABLE 24 24 HDMI_DEEP_COLOR_DEPTH 28 29 regDIG1_HDMI_STATUS 0 0x2194 4 0 2 HDMI_ACTIVE_AVMUTE 0 0 HDMI_AUDIO_PACKET_ERROR 16 16 HDMI_VBI_PACKET_ERROR 20 20 HDMI_ERROR_INT 27 27 regDIG1_HDMI_AUDIO_PACKET_CONTROL 0 0x2195 1 0 2 HDMI_AUDIO_DELAY_EN 4 5 regDIG1_HDMI_ACR_PACKET_CONTROL 0 0x2196 7 0 2 HDMI_ACR_SEND 0 0 HDMI_ACR_CONT 1 1 HDMI_ACR_SELECT 4 5 HDMI_ACR_SOURCE 8 8 HDMI_ACR_AUTO_SEND 12 12 HDMI_ACR_N_MULTIPLE 16 18 HDMI_ACR_AUDIO_PRIORITY 31 31 regDIG1_HDMI_VBI_PACKET_CONTROL 0 0x2197 8 0 2 HDMI_NULL_SEND 0 0 HDMI_GC_SEND 4 4 HDMI_GC_CONT 5 5 HDMI_ISRC_SEND 8 8 HDMI_ISRC_CONT 9 9 HDMI_ACP_SEND 12 12 HDMI_ISRC_LINE 16 21 HDMI_ACP_LINE 24 29 regDIG1_HDMI_INFOFRAME_CONTROL0 0 0x2198 4 0 2 HDMI_AUDIO_INFO_SEND 4 4 HDMI_AUDIO_INFO_CONT 5 5 HDMI_MPEG_INFO_SEND 8 8 HDMI_MPEG_INFO_CONT 9 9 regDIG1_HDMI_INFOFRAME_CONTROL1 0 0x2199 2 0 2 HDMI_AUDIO_INFO_LINE 8 13 HDMI_MPEG_INFO_LINE 16 21 regDIG1_HDMI_GENERIC_PACKET_CONTROL0 0 0x219a 32 0 2 HDMI_GENERIC0_SEND 0 0 HDMI_GENERIC0_CONT 1 1 HDMI_GENERIC0_LINE_REFERENCE 2 2 HDMI_GENERIC0_UPDATE_LOCK_DISABLE 3 3 HDMI_GENERIC1_SEND 4 4 HDMI_GENERIC1_CONT 5 5 HDMI_GENERIC1_LINE_REFERENCE 6 6 HDMI_GENERIC1_UPDATE_LOCK_DISABLE 7 7 HDMI_GENERIC2_SEND 8 8 HDMI_GENERIC2_CONT 9 9 HDMI_GENERIC2_LINE_REFERENCE 10 10 HDMI_GENERIC2_UPDATE_LOCK_DISABLE 11 11 HDMI_GENERIC3_SEND 12 12 HDMI_GENERIC3_CONT 13 13 HDMI_GENERIC3_LINE_REFERENCE 14 14 HDMI_GENERIC3_UPDATE_LOCK_DISABLE 15 15 HDMI_GENERIC4_SEND 16 16 HDMI_GENERIC4_CONT 17 17 HDMI_GENERIC4_LINE_REFERENCE 18 18 HDMI_GENERIC4_UPDATE_LOCK_DISABLE 19 19 HDMI_GENERIC5_SEND 20 20 HDMI_GENERIC5_CONT 21 21 HDMI_GENERIC5_LINE_REFERENCE 22 22 HDMI_GENERIC5_UPDATE_LOCK_DISABLE 23 23 HDMI_GENERIC6_SEND 24 24 HDMI_GENERIC6_CONT 25 25 HDMI_GENERIC6_LINE_REFERENCE 26 26 HDMI_GENERIC6_UPDATE_LOCK_DISABLE 27 27 HDMI_GENERIC7_SEND 28 28 HDMI_GENERIC7_CONT 29 29 HDMI_GENERIC7_LINE_REFERENCE 30 30 HDMI_GENERIC7_UPDATE_LOCK_DISABLE 31 31 regDIG1_HDMI_GENERIC_PACKET_CONTROL6 0 0x219b 28 0 2 HDMI_GENERIC8_SEND 0 0 HDMI_GENERIC8_CONT 1 1 HDMI_GENERIC8_LINE_REFERENCE 2 2 HDMI_GENERIC8_UPDATE_LOCK_DISABLE 3 3 HDMI_GENERIC9_SEND 4 4 HDMI_GENERIC9_CONT 5 5 HDMI_GENERIC9_LINE_REFERENCE 6 6 HDMI_GENERIC9_UPDATE_LOCK_DISABLE 7 7 HDMI_GENERIC10_SEND 8 8 HDMI_GENERIC10_CONT 9 9 HDMI_GENERIC10_LINE_REFERENCE 10 10 HDMI_GENERIC10_UPDATE_LOCK_DISABLE 11 11 HDMI_GENERIC11_SEND 12 12 HDMI_GENERIC11_CONT 13 13 HDMI_GENERIC11_LINE_REFERENCE 14 14 HDMI_GENERIC11_UPDATE_LOCK_DISABLE 15 15 HDMI_GENERIC12_SEND 16 16 HDMI_GENERIC12_CONT 17 17 HDMI_GENERIC12_LINE_REFERENCE 18 18 HDMI_GENERIC12_UPDATE_LOCK_DISABLE 19 19 HDMI_GENERIC13_SEND 20 20 HDMI_GENERIC13_CONT 21 21 HDMI_GENERIC13_LINE_REFERENCE 22 22 HDMI_GENERIC13_UPDATE_LOCK_DISABLE 23 23 HDMI_GENERIC14_SEND 24 24 HDMI_GENERIC14_CONT 25 25 HDMI_GENERIC14_LINE_REFERENCE 26 26 HDMI_GENERIC14_UPDATE_LOCK_DISABLE 27 27 regDIG1_HDMI_GENERIC_PACKET_CONTROL5 0 0x219c 30 0 2 HDMI_GENERIC0_IMMEDIATE_SEND 0 0 HDMI_GENERIC0_IMMEDIATE_SEND_PENDING 1 1 HDMI_GENERIC1_IMMEDIATE_SEND 2 2 HDMI_GENERIC1_IMMEDIATE_SEND_PENDING 3 3 HDMI_GENERIC2_IMMEDIATE_SEND 4 4 HDMI_GENERIC2_IMMEDIATE_SEND_PENDING 5 5 HDMI_GENERIC3_IMMEDIATE_SEND 6 6 HDMI_GENERIC3_IMMEDIATE_SEND_PENDING 7 7 HDMI_GENERIC4_IMMEDIATE_SEND 8 8 HDMI_GENERIC4_IMMEDIATE_SEND_PENDING 9 9 HDMI_GENERIC5_IMMEDIATE_SEND 10 10 HDMI_GENERIC5_IMMEDIATE_SEND_PENDING 11 11 HDMI_GENERIC6_IMMEDIATE_SEND 12 12 HDMI_GENERIC6_IMMEDIATE_SEND_PENDING 13 13 HDMI_GENERIC7_IMMEDIATE_SEND 14 14 HDMI_GENERIC7_IMMEDIATE_SEND_PENDING 15 15 HDMI_GENERIC8_IMMEDIATE_SEND 16 16 HDMI_GENERIC8_IMMEDIATE_SEND_PENDING 17 17 HDMI_GENERIC9_IMMEDIATE_SEND 18 18 HDMI_GENERIC9_IMMEDIATE_SEND_PENDING 19 19 HDMI_GENERIC10_IMMEDIATE_SEND 20 20 HDMI_GENERIC10_IMMEDIATE_SEND_PENDING 21 21 HDMI_GENERIC11_IMMEDIATE_SEND 22 22 HDMI_GENERIC11_IMMEDIATE_SEND_PENDING 23 23 HDMI_GENERIC12_IMMEDIATE_SEND 24 24 HDMI_GENERIC12_IMMEDIATE_SEND_PENDING 25 25 HDMI_GENERIC13_IMMEDIATE_SEND 26 26 HDMI_GENERIC13_IMMEDIATE_SEND_PENDING 27 27 HDMI_GENERIC14_IMMEDIATE_SEND 28 28 HDMI_GENERIC14_IMMEDIATE_SEND_PENDING 29 29 regDIG1_HDMI_GC 0 0x219d 5 0 2 HDMI_GC_AVMUTE 0 0 HDMI_GC_AVMUTE_CONT 2 2 HDMI_DEFAULT_PHASE 4 4 HDMI_PACKING_PHASE 8 11 HDMI_PACKING_PHASE_OVERRIDE 12 12 regDIG1_HDMI_GENERIC_PACKET_CONTROL1 0 0x219e 2 0 2 HDMI_GENERIC0_LINE 0 15 HDMI_GENERIC1_LINE 16 31 regDIG1_HDMI_GENERIC_PACKET_CONTROL2 0 0x219f 2 0 2 HDMI_GENERIC2_LINE 0 15 HDMI_GENERIC3_LINE 16 31 regDIG1_HDMI_GENERIC_PACKET_CONTROL3 0 0x21a0 2 0 2 HDMI_GENERIC4_LINE 0 15 HDMI_GENERIC5_LINE 16 31 regDIG1_HDMI_GENERIC_PACKET_CONTROL4 0 0x21a1 2 0 2 HDMI_GENERIC6_LINE 0 15 HDMI_GENERIC7_LINE 16 31 regDIG1_HDMI_GENERIC_PACKET_CONTROL7 0 0x21a2 2 0 2 HDMI_GENERIC8_LINE 0 15 HDMI_GENERIC9_LINE 16 31 regDIG1_HDMI_GENERIC_PACKET_CONTROL8 0 0x21a3 2 0 2 HDMI_GENERIC10_LINE 0 15 HDMI_GENERIC11_LINE 16 31 regDIG1_HDMI_GENERIC_PACKET_CONTROL9 0 0x21a4 2 0 2 HDMI_GENERIC12_LINE 0 15 HDMI_GENERIC13_LINE 16 31 regDIG1_HDMI_GENERIC_PACKET_CONTROL10 0 0x21a5 16 0 2 HDMI_GENERIC14_LINE 0 15 HDMI_GENERIC0_EN_DB_PENDING 16 16 HDMI_GENERIC1_EN_DB_PENDING 17 17 HDMI_GENERIC2_EN_DB_PENDING 18 18 HDMI_GENERIC3_EN_DB_PENDING 19 19 HDMI_GENERIC4_EN_DB_PENDING 20 20 HDMI_GENERIC5_EN_DB_PENDING 21 21 HDMI_GENERIC6_EN_DB_PENDING 22 22 HDMI_GENERIC7_EN_DB_PENDING 23 23 HDMI_GENERIC8_EN_DB_PENDING 24 24 HDMI_GENERIC9_EN_DB_PENDING 25 25 HDMI_GENERIC10_EN_DB_PENDING 26 26 HDMI_GENERIC11_EN_DB_PENDING 27 27 HDMI_GENERIC12_EN_DB_PENDING 28 28 HDMI_GENERIC13_EN_DB_PENDING 29 29 HDMI_GENERIC14_EN_DB_PENDING 30 30 regDIG1_HDMI_DB_CONTROL 0 0x21a6 8 0 2 HDMI_DB_PENDING 0 0 HDMI_DB_TAKEN 4 4 HDMI_DB_TAKEN_CLR 5 5 HDMI_DB_LOCK 8 8 HDMI_DB_DISABLE 12 12 VUPDATE_DB_PENDING 15 15 VUPDATE_DB_TAKEN 16 16 VUPDATE_DB_TAKEN_CLR 17 17 regDIG1_HDMI_ACR_32_0 0 0x21a7 1 0 2 HDMI_ACR_CTS_32 12 31 regDIG1_HDMI_ACR_32_1 0 0x21a8 1 0 2 HDMI_ACR_N_32 0 19 regDIG1_HDMI_ACR_44_0 0 0x21a9 1 0 2 HDMI_ACR_CTS_44 12 31 regDIG1_HDMI_ACR_44_1 0 0x21aa 1 0 2 HDMI_ACR_N_44 0 19 regDIG1_HDMI_ACR_48_0 0 0x21ab 1 0 2 HDMI_ACR_CTS_48 12 31 regDIG1_HDMI_ACR_48_1 0 0x21ac 1 0 2 HDMI_ACR_N_48 0 19 regDIG1_HDMI_ACR_STATUS_0 0 0x21ad 1 0 2 HDMI_ACR_CTS 12 31 regDIG1_HDMI_ACR_STATUS_1 0 0x21ae 1 0 2 HDMI_ACR_N 0 19 regDIG1_AFMT_CNTL 0 0x21af 2 0 2 AFMT_AUDIO_CLOCK_EN 0 0 AFMT_AUDIO_CLOCK_ON 8 8 regDIG1_DIG_BE_CNTL 0 0x21b0 6 0 2 DIG_DUAL_LINK_ENABLE 0 0 DIG_SWAP 1 1 DIG_RB_SWITCH_EN 2 2 DIG_FE_SOURCE_SELECT 8 14 DIG_MODE 16 18 DIG_HPD_SELECT 28 30 regDIG1_DIG_BE_EN_CNTL 0 0x21b1 2 0 2 DIG_ENABLE 0 0 DIG_SYMCLK_BE_ON 8 8 regDIG1_TMDS_CNTL 0 0x21d7 1 0 2 TMDS_SYNC_PHASE 0 0 regDIG1_TMDS_CONTROL_CHAR 0 0x21d8 4 0 2 TMDS_CONTROL_CHAR0_OUT_EN 0 0 TMDS_CONTROL_CHAR1_OUT_EN 1 1 TMDS_CONTROL_CHAR2_OUT_EN 2 2 TMDS_CONTROL_CHAR3_OUT_EN 3 3 regDIG1_TMDS_CONTROL0_FEEDBACK 0 0x21d9 2 0 2 TMDS_CONTROL0_FEEDBACK_SELECT 0 1 TMDS_CONTROL0_FEEDBACK_DELAY 8 9 regDIG1_TMDS_STEREOSYNC_CTL_SEL 0 0x21da 1 0 2 TMDS_STEREOSYNC_CTL_SEL 0 1 regDIG1_TMDS_SYNC_CHAR_PATTERN_0_1 0 0x21db 2 0 2 TMDS_SYNC_CHAR_PATTERN0 0 9 TMDS_SYNC_CHAR_PATTERN1 16 25 regDIG1_TMDS_SYNC_CHAR_PATTERN_2_3 0 0x21dc 2 0 2 TMDS_SYNC_CHAR_PATTERN2 0 9 TMDS_SYNC_CHAR_PATTERN3 16 25 regDIG1_TMDS_CTL_BITS 0 0x21de 4 0 2 TMDS_CTL0 0 0 TMDS_CTL1 8 8 TMDS_CTL2 16 16 TMDS_CTL3 24 24 regDIG1_TMDS_DCBALANCER_CONTROL 0 0x21df 5 0 2 TMDS_DCBALANCER_EN 0 0 TMDS_SYNC_DCBAL_EN 4 6 TMDS_DCBALANCER_TEST_EN 8 8 TMDS_DCBALANCER_TEST_IN 16 19 TMDS_DCBALANCER_FORCE 24 24 regDIG1_TMDS_SYNC_DCBALANCE_CHAR 0 0x21e0 2 0 2 TMDS_SYNC_DCBAL_CHAR01 0 9 TMDS_SYNC_DCBAL_CHAR11 16 25 regDIG1_TMDS_CTL0_1_GEN_CNTL 0 0x21e1 15 0 2 TMDS_CTL0_DATA_SEL 0 3 TMDS_CTL0_DATA_DELAY 4 6 TMDS_CTL0_DATA_INVERT 7 7 TMDS_CTL0_DATA_MODULATION 8 9 TMDS_CTL0_USE_FEEDBACK_PATH 10 10 TMDS_CTL0_FB_SYNC_CONT 11 11 TMDS_CTL0_PATTERN_OUT_EN 12 12 TMDS_CTL1_DATA_SEL 16 19 TMDS_CTL1_DATA_DELAY 20 22 TMDS_CTL1_DATA_INVERT 23 23 TMDS_CTL1_DATA_MODULATION 24 25 TMDS_CTL1_USE_FEEDBACK_PATH 26 26 TMDS_CTL1_FB_SYNC_CONT 27 27 TMDS_CTL1_PATTERN_OUT_EN 28 28 TMDS_2BIT_COUNTER_EN 31 31 regDIG1_TMDS_CTL2_3_GEN_CNTL 0 0x21e2 14 0 2 TMDS_CTL2_DATA_SEL 0 3 TMDS_CTL2_DATA_DELAY 4 6 TMDS_CTL2_DATA_INVERT 7 7 TMDS_CTL2_DATA_MODULATION 8 9 TMDS_CTL2_USE_FEEDBACK_PATH 10 10 TMDS_CTL2_FB_SYNC_CONT 11 11 TMDS_CTL2_PATTERN_OUT_EN 12 12 TMDS_CTL3_DATA_SEL 16 19 TMDS_CTL3_DATA_DELAY 20 22 TMDS_CTL3_DATA_INVERT 23 23 TMDS_CTL3_DATA_MODULATION 24 25 TMDS_CTL3_USE_FEEDBACK_PATH 26 26 TMDS_CTL3_FB_SYNC_CONT 27 27 TMDS_CTL3_PATTERN_OUT_EN 28 28 regDIG1_DIG_VERSION 0 0x21e4 1 0 2 DIG_TYPE 0 0 regDIG1_FORCE_DIG_DISABLE 0 0x21e5 1 0 2 FORCE_DIG_DISABLE 0 0 regDP2_DP_LINK_CNTL 0 0x2308 3 0 2 DP_LINK_TRAINING_COMPLETE 4 4 DP_LINK_STATUS 8 8 DP_EMBEDDED_PANEL_MODE 17 17 regDP2_DP_PIXEL_FORMAT 0 0x2309 3 0 2 DP_PIXEL_ENCODING 0 2 DP_COMPONENT_DEPTH 24 26 DP_PIXEL_COMBINE 28 29 regDP2_DP_MSA_COLORIMETRY 0 0x230a 1 0 2 DP_MSA_MISC0 24 31 regDP2_DP_CONFIG 0 0x230b 1 0 2 DP_UDI_LANES 0 1 regDP2_DP_VID_STREAM_CNTL 0 0x230c 4 0 2 DP_VID_STREAM_ENABLE 0 0 DP_VID_STREAM_DIS_DEFER 8 9 DP_VID_STREAM_STATUS 16 16 DP_VID_STREAM_CHANGE_KEEPOUT 20 20 regDP2_DP_STEER_FIFO 0 0x230d 7 0 2 DP_STEER_FIFO_RESET 0 0 DP_STEER_OVERFLOW_FLAG 4 4 DP_STEER_OVERFLOW_INT 5 5 DP_STEER_OVERFLOW_ACK 6 6 DP_STEER_OVERFLOW_MASK 7 7 DP_TU_OVERFLOW_FLAG 8 8 DP_TU_OVERFLOW_ACK 12 12 regDP2_DP_MSA_MISC 0 0x230e 4 0 2 DP_MSA_MISC1 0 7 DP_MSA_MISC2 8 15 DP_MSA_MISC3 16 23 DP_MSA_MISC4 24 31 regDP2_DP_DPHY_INTERNAL_CTRL 0 0x230f 2 0 2 DPHY_ALT_SCRAMBLER_RESET_EN 0 0 DPHY_ALT_SCRAMBLER_RESET_SEL 4 4 regDP2_DP_VID_TIMING 0 0x2310 5 0 2 DP_VID_M_N_DOUBLE_BUFFER_MODE 4 4 DP_VID_M_N_GEN_EN 8 8 DP_VID_N_MUL 10 11 DP_VID_M_DIV 12 13 DP_VID_N_DIV 24 31 regDP2_DP_VID_N 0 0x2311 1 0 2 DP_VID_N 0 23 regDP2_DP_VID_M 0 0x2312 1 0 2 DP_VID_M 0 23 regDP2_DP_LINK_FRAMING_CNTL 0 0x2313 3 0 2 DP_IDLE_BS_INTERVAL 0 17 DP_VBID_DISABLE 24 24 DP_VID_ENHANCED_FRAME_MODE 28 28 regDP2_DP_HBR2_EYE_PATTERN 0 0x2314 1 0 2 DP_HBR2_EYE_PATTERN_ENABLE 0 0 regDP2_DP_VID_MSA_VBID 0 0x2315 2 0 2 DP_VID_MSA_LOCATION 0 11 DP_VID_VBID_FIELD_POL 24 24 regDP2_DP_VID_INTERRUPT_CNTL 0 0x2316 3 0 2 DP_VID_STREAM_DISABLE_INT 0 0 DP_VID_STREAM_DISABLE_ACK 1 1 DP_VID_STREAM_DISABLE_MASK 2 2 regDP2_DP_DPHY_CNTL 0 0x2317 10 0 2 DPHY_ATEST_SEL_LANE0 0 0 DPHY_ATEST_SEL_LANE1 1 1 DPHY_ATEST_SEL_LANE2 2 2 DPHY_ATEST_SEL_LANE3 3 3 DPHY_FEC_EN 4 4 DPHY_FEC_READY_SHADOW 5 5 DPHY_FEC_ACTIVE_STATUS 6 6 DPHY_SCRAMBLER_SEL 8 8 DPHY_BYPASS 16 16 DPHY_SKEW_BYPASS 24 24 regDP2_DP_DPHY_TRAINING_PATTERN_SEL 0 0x2318 1 0 2 DPHY_TRAINING_PATTERN_SEL 0 1 regDP2_DP_DPHY_SYM0 0 0x2319 3 0 2 DPHY_SYM1 0 9 DPHY_SYM2 10 19 DPHY_SYM3 20 29 regDP2_DP_DPHY_SYM1 0 0x231a 3 0 2 DPHY_SYM4 0 9 DPHY_SYM5 10 19 DPHY_SYM6 20 29 regDP2_DP_DPHY_SYM2 0 0x231b 2 0 2 DPHY_SYM7 0 9 DPHY_SYM8 10 19 regDP2_DP_DPHY_8B10B_CNTL 0 0x231c 3 0 2 DPHY_8B10B_RESET 8 8 DPHY_8B10B_EXT_DISP 16 16 DPHY_8B10B_CUR_DISP 24 24 regDP2_DP_DPHY_PRBS_CNTL 0 0x231d 3 0 2 DPHY_PRBS_EN 0 0 DPHY_PRBS_SEL 4 5 DPHY_PRBS_SEED 8 30 regDP2_DP_DPHY_SCRAM_CNTL 0 0x231e 4 0 2 DPHY_SCRAMBLER_DIS 0 0 DPHY_SCRAMBLER_ADVANCE 4 4 DPHY_SCRAMBLER_BS_COUNT 8 17 DPHY_SCRAMBLER_KCODE 24 24 regDP2_DP_DPHY_CRC_EN 0 0x231f 3 0 2 DPHY_CRC_EN 0 0 DPHY_CRC_CONT_EN 4 4 DPHY_CRC_RESULT_VALID 8 8 regDP2_DP_DPHY_CRC_CNTL 0 0x2320 3 0 2 DPHY_CRC_FIELD 0 0 DPHY_CRC_SEL 4 5 DPHY_CRC_MASK 16 23 regDP2_DP_DPHY_CRC_RESULT 0 0x2321 4 0 2 DPHY_CRC_RESULT 0 7 DPHY_CRC_RESULT1 8 15 DPHY_CRC_RESULT2 16 23 DPHY_CRC_RESULT3 24 31 regDP2_DP_DPHY_CRC_MST_CNTL 0 0x2322 2 0 2 DPHY_CRC_MST_FIRST_SLOT 0 5 DPHY_CRC_MST_LAST_SLOT 8 13 regDP2_DP_DPHY_CRC_MST_STATUS 0 0x2323 3 0 2 DPHY_CRC_MST_PHASE_LOCK 0 0 DPHY_CRC_MST_PHASE_ERROR 8 8 DPHY_CRC_MST_PHASE_ERROR_ACK 16 16 regDP2_DP_DPHY_FAST_TRAINING 0 0x2324 6 0 2 DPHY_RX_FAST_TRAINING_CAPABLE 0 0 DPHY_SW_FAST_TRAINING_START 1 1 DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN 2 2 DPHY_STREAM_RESET_DURING_FAST_TRAINING 4 4 DPHY_FAST_TRAINING_TP1_TIME 8 19 DPHY_FAST_TRAINING_TP2_TIME 20 31 regDP2_DP_DPHY_FAST_TRAINING_STATUS 0 0x2325 4 0 2 DPHY_FAST_TRAINING_STATE 0 2 DPHY_FAST_TRAINING_COMPLETE_OCCURRED 4 4 DPHY_FAST_TRAINING_COMPLETE_MASK 8 8 DPHY_FAST_TRAINING_COMPLETE_ACK 12 12 regDP2_DP_SEC_CNTL 0 0x232b 14 0 2 DP_SEC_STREAM_ENABLE 0 0 DP_SEC_ASP_ENABLE 4 4 DP_SEC_ATP_ENABLE 8 8 DP_SEC_AIP_ENABLE 12 12 DP_SEC_ACM_ENABLE 16 16 DP_SEC_GSP0_ENABLE 20 20 DP_SEC_GSP1_ENABLE 21 21 DP_SEC_GSP2_ENABLE 22 22 DP_SEC_GSP3_ENABLE 23 23 DP_SEC_GSP4_ENABLE 24 24 DP_SEC_GSP5_ENABLE 25 25 DP_SEC_GSP6_ENABLE 26 26 DP_SEC_GSP7_ENABLE 27 27 DP_SEC_MPG_ENABLE 28 28 regDP2_DP_SEC_CNTL1 0 0x232c 15 0 2 DP_SEC_ISRC_ENABLE 0 0 DP_SEC_GSP0_LINE_REFERENCE 1 1 DP_SEC_GSP0_PRIORITY 4 4 DP_SEC_GSP0_SEND 5 5 DP_SEC_GSP0_SEND_PENDING 6 6 DP_SEC_GSP0_SEND_DEADLINE_MISSED 7 7 DP_SEC_GSP0_SEND_ANY_LINE 8 8 DP_SEC_GSP1_LINE_REFERENCE 9 9 DP_SEC_GSP2_LINE_REFERENCE 10 10 DP_SEC_GSP3_LINE_REFERENCE 11 11 DP_SEC_GSP4_LINE_REFERENCE 12 12 DP_SEC_GSP5_LINE_REFERENCE 13 13 DP_SEC_GSP6_LINE_REFERENCE 14 14 DP_SEC_GSP7_LINE_REFERENCE 15 15 DP_SEC_GSP0_LINE_NUM 16 31 regDP2_DP_SEC_FRAMING1 0 0x232d 2 0 2 DP_SEC_FRAME_START_LOCATION 0 11 DP_SEC_VBLANK_TRANSMIT_WIDTH 16 31 regDP2_DP_SEC_FRAMING2 0 0x232e 2 0 2 DP_SEC_START_POSITION 0 15 DP_SEC_HBLANK_TRANSMIT_WIDTH 16 31 regDP2_DP_SEC_FRAMING3 0 0x232f 2 0 2 DP_SEC_IDLE_FRAME_SIZE 0 13 DP_SEC_IDLE_TRANSMIT_WIDTH 16 31 regDP2_DP_SEC_FRAMING4 0 0x2330 5 0 2 DP_SST_SDP_SPLITTING 0 0 DP_SEC_COLLISION_STATUS 20 20 DP_SEC_COLLISION_ACK 24 24 DP_SEC_AUDIO_MUTE 28 28 DP_SEC_AUDIO_MUTE_STATUS 29 29 regDP2_DP_SEC_AUD_N 0 0x2331 1 0 2 DP_SEC_AUD_N 0 23 regDP2_DP_SEC_AUD_N_READBACK 0 0x2332 1 0 2 DP_SEC_AUD_N_READBACK 0 23 regDP2_DP_SEC_AUD_M 0 0x2333 1 0 2 DP_SEC_AUD_M 0 23 regDP2_DP_SEC_AUD_M_READBACK 0 0x2334 1 0 2 DP_SEC_AUD_M_READBACK 0 23 regDP2_DP_SEC_TIMESTAMP 0 0x2335 1 0 2 DP_SEC_TIMESTAMP_MODE 0 0 regDP2_DP_SEC_PACKET_CNTL 0 0x2336 4 0 2 DP_SEC_ASP_CODING_TYPE 1 3 DP_SEC_ASP_PRIORITY 4 4 DP_SEC_VERSION 8 13 DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE 16 16 regDP2_DP_MSE_RATE_CNTL 0 0x2337 2 0 2 DP_MSE_RATE_Y 0 25 DP_MSE_RATE_X 26 31 regDP2_DP_MSE_RATE_UPDATE 0 0x2339 1 0 2 DP_MSE_RATE_UPDATE_PENDING 0 0 regDP2_DP_MSE_SAT0 0 0x233a 8 0 2 DP_MSE_SAT_SRC0 0 2 DP_MSE_SAT_ENCRYPT0 4 4 DP_MSE_SAT_ENCRYPTION_TYPE0 5 5 DP_MSE_SAT_SLOT_COUNT0 8 13 DP_MSE_SAT_SRC1 16 18 DP_MSE_SAT_ENCRYPT1 20 20 DP_MSE_SAT_ENCRYPTION_TYPE1 21 21 DP_MSE_SAT_SLOT_COUNT1 24 29 regDP2_DP_MSE_SAT1 0 0x233b 8 0 2 DP_MSE_SAT_SRC2 0 2 DP_MSE_SAT_ENCRYPT2 4 4 DP_MSE_SAT_ENCRYPTION_TYPE2 5 5 DP_MSE_SAT_SLOT_COUNT2 8 13 DP_MSE_SAT_SRC3 16 18 DP_MSE_SAT_ENCRYPT3 20 20 DP_MSE_SAT_ENCRYPTION_TYPE3 21 21 DP_MSE_SAT_SLOT_COUNT3 24 29 regDP2_DP_MSE_SAT2 0 0x233c 8 0 2 DP_MSE_SAT_SRC4 0 2 DP_MSE_SAT_ENCRYPT4 4 4 DP_MSE_SAT_ENCRYPTION_TYPE4 5 5 DP_MSE_SAT_SLOT_COUNT4 8 13 DP_MSE_SAT_SRC5 16 18 DP_MSE_SAT_ENCRYPT5 20 20 DP_MSE_SAT_ENCRYPTION_TYPE5 21 21 DP_MSE_SAT_SLOT_COUNT5 24 29 regDP2_DP_MSE_SAT_UPDATE 0 0x233d 2 0 2 DP_MSE_SAT_UPDATE 0 1 DP_MSE_16_MTP_KEEPOUT 8 8 regDP2_DP_MSE_LINK_TIMING 0 0x233e 2 0 2 DP_MSE_LINK_FRAME 0 9 DP_MSE_LINK_LINE 16 17 regDP2_DP_MSE_MISC_CNTL 0 0x233f 3 0 2 DP_MSE_BLANK_CODE 0 0 DP_MSE_TIMESTAMP_MODE 4 4 DP_MSE_ZERO_ENCODER 8 8 regDP2_DP_DPHY_BS_SR_SWAP_CNTL 0 0x2344 3 0 2 DPHY_LOAD_BS_COUNT 0 9 DPHY_BS_SR_SWAP_DONE 15 15 DPHY_LOAD_BS_COUNT_START 16 16 regDP2_DP_DPHY_HBR2_PATTERN_CONTROL 0 0x2345 1 0 2 DP_DPHY_HBR2_PATTERN_CONTROL 0 2 regDP2_DP_MSE_SAT0_STATUS 0 0x2347 8 0 2 DP_MSE_SAT_SRC0_STATUS 0 2 DP_MSE_SAT_ENCRYPT0_STATUS 4 4 DP_MSE_SAT_ENCRYPTION_TYPE0_STATUS 5 5 DP_MSE_SAT_SLOT_COUNT0_STATUS 8 13 DP_MSE_SAT_SRC1_STATUS 16 18 DP_MSE_SAT_ENCRYPT1_STATUS 20 20 DP_MSE_SAT_ENCRYPTION_TYPE1_STATUS 21 21 DP_MSE_SAT_SLOT_COUNT1_STATUS 24 29 regDP2_DP_MSE_SAT1_STATUS 0 0x2348 8 0 2 DP_MSE_SAT_SRC2_STATUS 0 2 DP_MSE_SAT_ENCRYPT2_STATUS 4 4 DP_MSE_SAT_ENCRYPTION_TYPE2_STATUS 5 5 DP_MSE_SAT_SLOT_COUNT2_STATUS 8 13 DP_MSE_SAT_SRC3_STATUS 16 18 DP_MSE_SAT_ENCRYPT3_STATUS 20 20 DP_MSE_SAT_ENCRYPTION_TYPE3_STATUS 21 21 DP_MSE_SAT_SLOT_COUNT3_STATUS 24 29 regDP2_DP_MSE_SAT2_STATUS 0 0x2349 8 0 2 DP_MSE_SAT_SRC4_STATUS 0 2 DP_MSE_SAT_ENCRYPT4_STATUS 4 4 DP_MSE_SAT_ENCRYPTION_TYPE4_STATUS 5 5 DP_MSE_SAT_SLOT_COUNT4_STATUS 8 13 DP_MSE_SAT_SRC5_STATUS 16 18 DP_MSE_SAT_ENCRYPT5_STATUS 20 20 DP_MSE_SAT_ENCRYPTION_TYPE5_STATUS 21 21 DP_MSE_SAT_SLOT_COUNT5_STATUS 24 29 regDP2_DP_MSA_TIMING_PARAM1 0 0x234c 2 0 2 DP_MSA_VTOTAL 0 15 DP_MSA_HTOTAL 16 31 regDP2_DP_MSA_TIMING_PARAM2 0 0x234d 2 0 2 DP_MSA_VSTART 0 15 DP_MSA_HSTART 16 31 regDP2_DP_MSA_TIMING_PARAM3 0 0x234e 4 0 2 DP_MSA_VSYNCWIDTH 0 14 DP_MSA_VSYNCPOLARITY 15 15 DP_MSA_HSYNCWIDTH 16 30 DP_MSA_HSYNCPOLARITY 31 31 regDP2_DP_MSA_TIMING_PARAM4 0 0x234f 2 0 2 DP_MSA_VHEIGHT 0 15 DP_MSA_HWIDTH 16 31 regDP2_DP_MSO_CNTL 0 0x2350 8 0 2 DP_MSO_NUM_OF_SSTLINK 0 1 DP_MSO_SEC_STREAM_ENABLE 4 7 DP_MSO_SEC_ASP_ENABLE 8 11 DP_MSO_SEC_ATP_ENABLE 12 15 DP_MSO_SEC_AIP_ENABLE 16 19 DP_MSO_SEC_ACM_ENABLE 20 23 DP_MSO_SEC_GSP0_ENABLE 24 27 DP_MSO_SEC_GSP1_ENABLE 28 31 regDP2_DP_MSO_CNTL1 0 0x2351 8 0 2 DP_MSO_SEC_GSP2_ENABLE 0 3 DP_MSO_SEC_GSP3_ENABLE 4 7 DP_MSO_SEC_GSP4_ENABLE 8 11 DP_MSO_SEC_GSP5_ENABLE 12 15 DP_MSO_SEC_GSP6_ENABLE 16 19 DP_MSO_SEC_GSP7_ENABLE 20 23 DP_MSO_SEC_MPG_ENABLE 24 27 DP_MSO_SEC_ISRC_ENABLE 28 31 regDP2_DP_DSC_CNTL 0 0x2352 2 0 2 DP_DSC_MODE 0 1 DP_DSC_SLICE_WIDTH 16 28 regDP2_DP_SEC_CNTL2 0 0x2353 29 0 2 DP_SEC_GSP1_SEND 0 0 DP_SEC_GSP1_SEND_PENDING 1 1 DP_SEC_GSP1_SEND_DEADLINE_MISSED 2 2 DP_SEC_GSP1_SEND_ANY_LINE 3 3 DP_SEC_GSP2_SEND 4 4 DP_SEC_GSP2_SEND_PENDING 5 5 DP_SEC_GSP2_SEND_DEADLINE_MISSED 6 6 DP_SEC_GSP2_SEND_ANY_LINE 7 7 DP_SEC_GSP3_SEND 8 8 DP_SEC_GSP3_SEND_PENDING 9 9 DP_SEC_GSP3_SEND_DEADLINE_MISSED 10 10 DP_SEC_GSP3_SEND_ANY_LINE 11 11 DP_SEC_GSP4_SEND 12 12 DP_SEC_GSP4_SEND_PENDING 13 13 DP_SEC_GSP4_SEND_DEADLINE_MISSED 14 14 DP_SEC_GSP4_SEND_ANY_LINE 15 15 DP_SEC_GSP5_SEND 16 16 DP_SEC_GSP5_SEND_PENDING 17 17 DP_SEC_GSP5_SEND_DEADLINE_MISSED 18 18 DP_SEC_GSP5_SEND_ANY_LINE 19 19 DP_SEC_GSP6_SEND 20 20 DP_SEC_GSP6_SEND_PENDING 21 21 DP_SEC_GSP6_SEND_DEADLINE_MISSED 22 22 DP_SEC_GSP6_SEND_ANY_LINE 23 23 DP_SEC_GSP7_SEND 24 24 DP_SEC_GSP7_SEND_PENDING 25 25 DP_SEC_GSP7_SEND_DEADLINE_MISSED 26 26 DP_SEC_GSP7_SEND_ANY_LINE 27 27 DP_SEC_GSP11_PPS 28 28 regDP2_DP_SEC_CNTL3 0 0x2354 2 0 2 DP_SEC_GSP1_LINE_NUM 0 15 DP_SEC_GSP2_LINE_NUM 16 31 regDP2_DP_SEC_CNTL4 0 0x2355 2 0 2 DP_SEC_GSP3_LINE_NUM 0 15 DP_SEC_GSP4_LINE_NUM 16 31 regDP2_DP_SEC_CNTL5 0 0x2356 2 0 2 DP_SEC_GSP5_LINE_NUM 0 15 DP_SEC_GSP6_LINE_NUM 16 31 regDP2_DP_SEC_CNTL6 0 0x2357 13 0 2 DP_SEC_GSP7_LINE_NUM 0 15 DP_SEC_GSP0_EN_DB_DISABLE 16 16 DP_SEC_GSP1_EN_DB_DISABLE 17 17 DP_SEC_GSP2_EN_DB_DISABLE 18 18 DP_SEC_GSP3_EN_DB_DISABLE 19 19 DP_SEC_GSP4_EN_DB_DISABLE 20 20 DP_SEC_GSP5_EN_DB_DISABLE 21 21 DP_SEC_GSP6_EN_DB_DISABLE 22 22 DP_SEC_GSP7_EN_DB_DISABLE 23 23 DP_SEC_GSP8_EN_DB_DISABLE 24 24 DP_SEC_GSP9_EN_DB_DISABLE 25 25 DP_SEC_GSP10_EN_DB_DISABLE 26 26 DP_SEC_GSP11_EN_DB_DISABLE 27 27 regDP2_DP_SEC_CNTL7 0 0x2358 16 0 2 DP_SEC_GSP0_SEND_ACTIVE 0 0 DP_SEC_GSP0_SEND_IN_IDLE 1 1 DP_SEC_GSP1_SEND_ACTIVE 4 4 DP_SEC_GSP1_SEND_IN_IDLE 5 5 DP_SEC_GSP2_SEND_ACTIVE 8 8 DP_SEC_GSP2_SEND_IN_IDLE 9 9 DP_SEC_GSP3_SEND_ACTIVE 12 12 DP_SEC_GSP3_SEND_IN_IDLE 13 13 DP_SEC_GSP4_SEND_ACTIVE 16 16 DP_SEC_GSP4_SEND_IN_IDLE 17 17 DP_SEC_GSP5_SEND_ACTIVE 20 20 DP_SEC_GSP5_SEND_IN_IDLE 21 21 DP_SEC_GSP6_SEND_ACTIVE 24 24 DP_SEC_GSP6_SEND_IN_IDLE 25 25 DP_SEC_GSP7_SEND_ACTIVE 28 28 DP_SEC_GSP7_SEND_IN_IDLE 29 29 regDP2_DP_DB_CNTL 0 0x2359 8 0 2 DP_DB_PENDING 0 0 DP_DB_TAKEN 4 4 DP_DB_TAKEN_CLR 5 5 DP_DB_LOCK 8 8 DP_DB_DISABLE 12 12 DP_VUPDATE_DB_PENDING 15 15 DP_VUPDATE_DB_TAKEN 16 16 DP_VUPDATE_DB_TAKEN_CLR 17 17 regDP2_DP_MSA_VBID_MISC 0 0x235a 8 0 2 DP_MSA_MISC1_STEREOSYNC_OVERRIDE 0 1 DP_MSA_MISC1_STEREOSYNC_OVERRIDE_EN 4 4 DP_VBID1_OVERRIDE 8 8 DP_VBID2_OVERRIDE 9 9 DP_VBID1_OVERRIDE_EN 12 12 DP_VBID2_OVERRIDE_EN 13 13 DP_VBID6_LINE_REFERENCE 15 15 DP_VBID6_LINE_NUM 16 31 regDP2_DP_SEC_METADATA_TRANSMISSION 0 0x235b 4 0 2 DP_SEC_METADATA_PACKET_ENABLE 0 0 DP_SEC_METADATA_PACKET_LINE_REFERENCE 1 1 DP_SEC_MSO_METADATA_PACKET_ENABLE 4 7 DP_SEC_METADATA_PACKET_LINE 16 31 regDP2_DP_DSC_BYTES_PER_PIXEL 0 0x235c 1 0 2 DP_DSC_BYTES_PER_PIXEL 0 30 regDP2_DP_ALPM_CNTL 0 0x235d 7 0 2 DP_ML_PHY_SLEEP_SEND 0 0 DP_ML_PHY_SLEEP_PENDING 1 1 DP_ML_PHY_STANDBY_SEND 2 2 DP_ML_PHY_STANDBY_PENDING 3 3 DP_ML_PHY_SLEEP_STANDBY_IMMEDIATE 4 4 DP_LINK_TRAINING_SWITCH_BETWEEN_VIDEO 5 5 DP_ML_PHY_SLEEP_STANDBY_LINE_NUM 16 31 regDP2_DP_GSP8_CNTL 0 0x235e 10 0 2 DP_MSO_SEC_GSP8_ENABLE 0 3 DP_SEC_GSP8_ENABLE 4 4 DP_SEC_GSP8_LINE_REFERENCE 5 5 DP_SEC_GSP8_SEND_IN_IDLE 6 6 DP_SEC_GSP8_SEND 7 7 DP_SEC_GSP8_SEND_ANY_LINE 8 8 DP_SEC_GSP8_SEND_PENDING 12 12 DP_SEC_GSP8_SEND_ACTIVE 13 13 DP_SEC_GSP8_SEND_DEADLINE_MISSED 14 14 DP_SEC_GSP8_LINE_NUM 16 31 regDP2_DP_GSP9_CNTL 0 0x235f 10 0 2 DP_MSO_SEC_GSP9_ENABLE 0 3 DP_SEC_GSP9_ENABLE 4 4 DP_SEC_GSP9_LINE_REFERENCE 5 5 DP_SEC_GSP9_SEND_IN_IDLE 6 6 DP_SEC_GSP9_SEND 7 7 DP_SEC_GSP9_SEND_ANY_LINE 8 8 DP_SEC_GSP9_SEND_PENDING 12 12 DP_SEC_GSP9_SEND_ACTIVE 13 13 DP_SEC_GSP9_SEND_DEADLINE_MISSED 14 14 DP_SEC_GSP9_LINE_NUM 16 31 regDP2_DP_GSP10_CNTL 0 0x2360 10 0 2 DP_MSO_SEC_GSP10_ENABLE 0 3 DP_SEC_GSP10_ENABLE 4 4 DP_SEC_GSP10_LINE_REFERENCE 5 5 DP_SEC_GSP10_SEND_IN_IDLE 6 6 DP_SEC_GSP10_SEND 7 7 DP_SEC_GSP10_SEND_ANY_LINE 8 8 DP_SEC_GSP10_SEND_PENDING 12 12 DP_SEC_GSP10_SEND_ACTIVE 13 13 DP_SEC_GSP10_SEND_DEADLINE_MISSED 14 14 DP_SEC_GSP10_LINE_NUM 16 31 regDP2_DP_GSP11_CNTL 0 0x2361 10 0 2 DP_MSO_SEC_GSP11_ENABLE 0 3 DP_SEC_GSP11_ENABLE 4 4 DP_SEC_GSP11_LINE_REFERENCE 5 5 DP_SEC_GSP11_SEND_IN_IDLE 6 6 DP_SEC_GSP11_SEND 7 7 DP_SEC_GSP11_SEND_ANY_LINE 8 8 DP_SEC_GSP11_SEND_PENDING 12 12 DP_SEC_GSP11_SEND_ACTIVE 13 13 DP_SEC_GSP11_SEND_DEADLINE_MISSED 14 14 DP_SEC_GSP11_LINE_NUM 16 31 regDP2_DP_GSP_EN_DB_STATUS 0 0x2362 12 0 2 DP_SEC_GSP0_EN_DB_PENDING 0 0 DP_SEC_GSP1_EN_DB_PENDING 1 1 DP_SEC_GSP2_EN_DB_PENDING 2 2 DP_SEC_GSP3_EN_DB_PENDING 3 3 DP_SEC_GSP4_EN_DB_PENDING 4 4 DP_SEC_GSP5_EN_DB_PENDING 5 5 DP_SEC_GSP6_EN_DB_PENDING 6 6 DP_SEC_GSP7_EN_DB_PENDING 7 7 DP_SEC_GSP8_EN_DB_PENDING 8 8 DP_SEC_GSP9_EN_DB_PENDING 9 9 DP_SEC_GSP10_EN_DB_PENDING 10 10 DP_SEC_GSP11_EN_DB_PENDING 11 11 regDIG2_DIG_FE_CNTL 0 0x228b 11 0 2 DIG_SOURCE_SELECT 0 2 DIG_STEREOSYNC_SELECT 4 6 DIG_STEREOSYNC_GATE_EN 8 8 DIG_START 10 10 DIG_DIGITAL_BYPASS_SELECT 12 14 DIG_INPUT_PIXEL_SELECT 16 17 DOLBY_VISION_EN 18 18 DOLBY_VISION_METADATA_PACKET_MISSED 19 19 DIG_SYMCLK_FE_ON 24 24 TMDS_PIXEL_ENCODING 28 28 TMDS_COLOR_FORMAT 30 31 regDIG2_DIG_OUTPUT_CRC_CNTL 0 0x228c 3 0 2 DIG_OUTPUT_CRC_EN 0 0 DIG_OUTPUT_CRC_LINK_SEL 4 4 DIG_OUTPUT_CRC_DATA_SEL 8 9 regDIG2_DIG_OUTPUT_CRC_RESULT 0 0x228d 1 0 2 DIG_OUTPUT_CRC_RESULT 0 29 regDIG2_DIG_CLOCK_PATTERN 0 0x228e 1 0 2 DIG_CLOCK_PATTERN 0 9 regDIG2_DIG_TEST_PATTERN 0 0x228f 6 0 2 DIG_TEST_PATTERN_OUT_EN 0 0 DIG_HALF_CLOCK_PATTERN_SEL 1 1 DIG_RANDOM_PATTERN_OUT_EN 4 4 DIG_RANDOM_PATTERN_RESET 5 5 DIG_TEST_PATTERN_EXTERNAL_RESET_EN 6 6 DIG_STATIC_TEST_PATTERN 16 25 regDIG2_DIG_RANDOM_PATTERN_SEED 0 0x2290 2 0 2 DIG_RANDOM_PATTERN_SEED 0 23 DIG_RAN_PAT_DURING_DE_ONLY 24 24 regDIG2_DIG_FIFO_STATUS 0 0x2291 11 0 2 DIG_FIFO_LEVEL_ERROR 0 0 DIG_FIFO_USE_OVERWRITE_LEVEL 1 1 DIG_FIFO_OVERWRITE_LEVEL 2 7 DIG_FIFO_ERROR_ACK 8 8 DIG_FIFO_CAL_AVERAGE_LEVEL 10 15 DIG_FIFO_MAXIMUM_LEVEL 16 20 DIG_FIFO_MINIMUM_LEVEL 22 25 DIG_FIFO_READ_CLOCK_SRC 26 26 DIG_FIFO_CALIBRATED 29 29 DIG_FIFO_FORCE_RECAL_AVERAGE 30 30 DIG_FIFO_FORCE_RECOMP_MINMAX 31 31 regDIG2_HDMI_METADATA_PACKET_CONTROL 0 0x2292 4 0 2 HDMI_METADATA_PACKET_ENABLE 0 0 HDMI_METADATA_PACKET_LINE_REFERENCE 4 4 HDMI_METADATA_PACKET_MISSED 8 8 HDMI_METADATA_PACKET_LINE 16 31 regDIG2_HDMI_CONTROL 0 0x2293 10 0 2 HDMI_KEEPOUT_MODE 0 0 HDMI_DATA_SCRAMBLE_EN 1 1 HDMI_CLOCK_CHANNEL_RATE 2 2 HDMI_NO_EXTRA_NULL_PACKET_FILLED 3 3 HDMI_PACKET_GEN_VERSION 4 4 HDMI_ERROR_ACK 8 8 HDMI_ERROR_MASK 9 9 HDMI_UNSCRAMBLED_CONTROL_LINE_NUM 16 21 HDMI_DEEP_COLOR_ENABLE 24 24 HDMI_DEEP_COLOR_DEPTH 28 29 regDIG2_HDMI_STATUS 0 0x2294 4 0 2 HDMI_ACTIVE_AVMUTE 0 0 HDMI_AUDIO_PACKET_ERROR 16 16 HDMI_VBI_PACKET_ERROR 20 20 HDMI_ERROR_INT 27 27 regDIG2_HDMI_AUDIO_PACKET_CONTROL 0 0x2295 1 0 2 HDMI_AUDIO_DELAY_EN 4 5 regDIG2_HDMI_ACR_PACKET_CONTROL 0 0x2296 7 0 2 HDMI_ACR_SEND 0 0 HDMI_ACR_CONT 1 1 HDMI_ACR_SELECT 4 5 HDMI_ACR_SOURCE 8 8 HDMI_ACR_AUTO_SEND 12 12 HDMI_ACR_N_MULTIPLE 16 18 HDMI_ACR_AUDIO_PRIORITY 31 31 regDIG2_HDMI_VBI_PACKET_CONTROL 0 0x2297 8 0 2 HDMI_NULL_SEND 0 0 HDMI_GC_SEND 4 4 HDMI_GC_CONT 5 5 HDMI_ISRC_SEND 8 8 HDMI_ISRC_CONT 9 9 HDMI_ACP_SEND 12 12 HDMI_ISRC_LINE 16 21 HDMI_ACP_LINE 24 29 regDIG2_HDMI_INFOFRAME_CONTROL0 0 0x2298 4 0 2 HDMI_AUDIO_INFO_SEND 4 4 HDMI_AUDIO_INFO_CONT 5 5 HDMI_MPEG_INFO_SEND 8 8 HDMI_MPEG_INFO_CONT 9 9 regDIG2_HDMI_INFOFRAME_CONTROL1 0 0x2299 2 0 2 HDMI_AUDIO_INFO_LINE 8 13 HDMI_MPEG_INFO_LINE 16 21 regDIG2_HDMI_GENERIC_PACKET_CONTROL0 0 0x229a 32 0 2 HDMI_GENERIC0_SEND 0 0 HDMI_GENERIC0_CONT 1 1 HDMI_GENERIC0_LINE_REFERENCE 2 2 HDMI_GENERIC0_UPDATE_LOCK_DISABLE 3 3 HDMI_GENERIC1_SEND 4 4 HDMI_GENERIC1_CONT 5 5 HDMI_GENERIC1_LINE_REFERENCE 6 6 HDMI_GENERIC1_UPDATE_LOCK_DISABLE 7 7 HDMI_GENERIC2_SEND 8 8 HDMI_GENERIC2_CONT 9 9 HDMI_GENERIC2_LINE_REFERENCE 10 10 HDMI_GENERIC2_UPDATE_LOCK_DISABLE 11 11 HDMI_GENERIC3_SEND 12 12 HDMI_GENERIC3_CONT 13 13 HDMI_GENERIC3_LINE_REFERENCE 14 14 HDMI_GENERIC3_UPDATE_LOCK_DISABLE 15 15 HDMI_GENERIC4_SEND 16 16 HDMI_GENERIC4_CONT 17 17 HDMI_GENERIC4_LINE_REFERENCE 18 18 HDMI_GENERIC4_UPDATE_LOCK_DISABLE 19 19 HDMI_GENERIC5_SEND 20 20 HDMI_GENERIC5_CONT 21 21 HDMI_GENERIC5_LINE_REFERENCE 22 22 HDMI_GENERIC5_UPDATE_LOCK_DISABLE 23 23 HDMI_GENERIC6_SEND 24 24 HDMI_GENERIC6_CONT 25 25 HDMI_GENERIC6_LINE_REFERENCE 26 26 HDMI_GENERIC6_UPDATE_LOCK_DISABLE 27 27 HDMI_GENERIC7_SEND 28 28 HDMI_GENERIC7_CONT 29 29 HDMI_GENERIC7_LINE_REFERENCE 30 30 HDMI_GENERIC7_UPDATE_LOCK_DISABLE 31 31 regDIG2_HDMI_GENERIC_PACKET_CONTROL6 0 0x229b 28 0 2 HDMI_GENERIC8_SEND 0 0 HDMI_GENERIC8_CONT 1 1 HDMI_GENERIC8_LINE_REFERENCE 2 2 HDMI_GENERIC8_UPDATE_LOCK_DISABLE 3 3 HDMI_GENERIC9_SEND 4 4 HDMI_GENERIC9_CONT 5 5 HDMI_GENERIC9_LINE_REFERENCE 6 6 HDMI_GENERIC9_UPDATE_LOCK_DISABLE 7 7 HDMI_GENERIC10_SEND 8 8 HDMI_GENERIC10_CONT 9 9 HDMI_GENERIC10_LINE_REFERENCE 10 10 HDMI_GENERIC10_UPDATE_LOCK_DISABLE 11 11 HDMI_GENERIC11_SEND 12 12 HDMI_GENERIC11_CONT 13 13 HDMI_GENERIC11_LINE_REFERENCE 14 14 HDMI_GENERIC11_UPDATE_LOCK_DISABLE 15 15 HDMI_GENERIC12_SEND 16 16 HDMI_GENERIC12_CONT 17 17 HDMI_GENERIC12_LINE_REFERENCE 18 18 HDMI_GENERIC12_UPDATE_LOCK_DISABLE 19 19 HDMI_GENERIC13_SEND 20 20 HDMI_GENERIC13_CONT 21 21 HDMI_GENERIC13_LINE_REFERENCE 22 22 HDMI_GENERIC13_UPDATE_LOCK_DISABLE 23 23 HDMI_GENERIC14_SEND 24 24 HDMI_GENERIC14_CONT 25 25 HDMI_GENERIC14_LINE_REFERENCE 26 26 HDMI_GENERIC14_UPDATE_LOCK_DISABLE 27 27 regDIG2_HDMI_GENERIC_PACKET_CONTROL5 0 0x229c 30 0 2 HDMI_GENERIC0_IMMEDIATE_SEND 0 0 HDMI_GENERIC0_IMMEDIATE_SEND_PENDING 1 1 HDMI_GENERIC1_IMMEDIATE_SEND 2 2 HDMI_GENERIC1_IMMEDIATE_SEND_PENDING 3 3 HDMI_GENERIC2_IMMEDIATE_SEND 4 4 HDMI_GENERIC2_IMMEDIATE_SEND_PENDING 5 5 HDMI_GENERIC3_IMMEDIATE_SEND 6 6 HDMI_GENERIC3_IMMEDIATE_SEND_PENDING 7 7 HDMI_GENERIC4_IMMEDIATE_SEND 8 8 HDMI_GENERIC4_IMMEDIATE_SEND_PENDING 9 9 HDMI_GENERIC5_IMMEDIATE_SEND 10 10 HDMI_GENERIC5_IMMEDIATE_SEND_PENDING 11 11 HDMI_GENERIC6_IMMEDIATE_SEND 12 12 HDMI_GENERIC6_IMMEDIATE_SEND_PENDING 13 13 HDMI_GENERIC7_IMMEDIATE_SEND 14 14 HDMI_GENERIC7_IMMEDIATE_SEND_PENDING 15 15 HDMI_GENERIC8_IMMEDIATE_SEND 16 16 HDMI_GENERIC8_IMMEDIATE_SEND_PENDING 17 17 HDMI_GENERIC9_IMMEDIATE_SEND 18 18 HDMI_GENERIC9_IMMEDIATE_SEND_PENDING 19 19 HDMI_GENERIC10_IMMEDIATE_SEND 20 20 HDMI_GENERIC10_IMMEDIATE_SEND_PENDING 21 21 HDMI_GENERIC11_IMMEDIATE_SEND 22 22 HDMI_GENERIC11_IMMEDIATE_SEND_PENDING 23 23 HDMI_GENERIC12_IMMEDIATE_SEND 24 24 HDMI_GENERIC12_IMMEDIATE_SEND_PENDING 25 25 HDMI_GENERIC13_IMMEDIATE_SEND 26 26 HDMI_GENERIC13_IMMEDIATE_SEND_PENDING 27 27 HDMI_GENERIC14_IMMEDIATE_SEND 28 28 HDMI_GENERIC14_IMMEDIATE_SEND_PENDING 29 29 regDIG2_HDMI_GC 0 0x229d 5 0 2 HDMI_GC_AVMUTE 0 0 HDMI_GC_AVMUTE_CONT 2 2 HDMI_DEFAULT_PHASE 4 4 HDMI_PACKING_PHASE 8 11 HDMI_PACKING_PHASE_OVERRIDE 12 12 regDIG2_HDMI_GENERIC_PACKET_CONTROL1 0 0x229e 2 0 2 HDMI_GENERIC0_LINE 0 15 HDMI_GENERIC1_LINE 16 31 regDIG2_HDMI_GENERIC_PACKET_CONTROL2 0 0x229f 2 0 2 HDMI_GENERIC2_LINE 0 15 HDMI_GENERIC3_LINE 16 31 regDIG2_HDMI_GENERIC_PACKET_CONTROL3 0 0x22a0 2 0 2 HDMI_GENERIC4_LINE 0 15 HDMI_GENERIC5_LINE 16 31 regDIG2_HDMI_GENERIC_PACKET_CONTROL4 0 0x22a1 2 0 2 HDMI_GENERIC6_LINE 0 15 HDMI_GENERIC7_LINE 16 31 regDIG2_HDMI_GENERIC_PACKET_CONTROL7 0 0x22a2 2 0 2 HDMI_GENERIC8_LINE 0 15 HDMI_GENERIC9_LINE 16 31 regDIG2_HDMI_GENERIC_PACKET_CONTROL8 0 0x22a3 2 0 2 HDMI_GENERIC10_LINE 0 15 HDMI_GENERIC11_LINE 16 31 regDIG2_HDMI_GENERIC_PACKET_CONTROL9 0 0x22a4 2 0 2 HDMI_GENERIC12_LINE 0 15 HDMI_GENERIC13_LINE 16 31 regDIG2_HDMI_GENERIC_PACKET_CONTROL10 0 0x22a5 16 0 2 HDMI_GENERIC14_LINE 0 15 HDMI_GENERIC0_EN_DB_PENDING 16 16 HDMI_GENERIC1_EN_DB_PENDING 17 17 HDMI_GENERIC2_EN_DB_PENDING 18 18 HDMI_GENERIC3_EN_DB_PENDING 19 19 HDMI_GENERIC4_EN_DB_PENDING 20 20 HDMI_GENERIC5_EN_DB_PENDING 21 21 HDMI_GENERIC6_EN_DB_PENDING 22 22 HDMI_GENERIC7_EN_DB_PENDING 23 23 HDMI_GENERIC8_EN_DB_PENDING 24 24 HDMI_GENERIC9_EN_DB_PENDING 25 25 HDMI_GENERIC10_EN_DB_PENDING 26 26 HDMI_GENERIC11_EN_DB_PENDING 27 27 HDMI_GENERIC12_EN_DB_PENDING 28 28 HDMI_GENERIC13_EN_DB_PENDING 29 29 HDMI_GENERIC14_EN_DB_PENDING 30 30 regDIG2_HDMI_DB_CONTROL 0 0x22a6 8 0 2 HDMI_DB_PENDING 0 0 HDMI_DB_TAKEN 4 4 HDMI_DB_TAKEN_CLR 5 5 HDMI_DB_LOCK 8 8 HDMI_DB_DISABLE 12 12 VUPDATE_DB_PENDING 15 15 VUPDATE_DB_TAKEN 16 16 VUPDATE_DB_TAKEN_CLR 17 17 regDIG2_HDMI_ACR_32_0 0 0x22a7 1 0 2 HDMI_ACR_CTS_32 12 31 regDIG2_HDMI_ACR_32_1 0 0x22a8 1 0 2 HDMI_ACR_N_32 0 19 regDIG2_HDMI_ACR_44_0 0 0x22a9 1 0 2 HDMI_ACR_CTS_44 12 31 regDIG2_HDMI_ACR_44_1 0 0x22aa 1 0 2 HDMI_ACR_N_44 0 19 regDIG2_HDMI_ACR_48_0 0 0x22ab 1 0 2 HDMI_ACR_CTS_48 12 31 regDIG2_HDMI_ACR_48_1 0 0x22ac 1 0 2 HDMI_ACR_N_48 0 19 regDIG2_HDMI_ACR_STATUS_0 0 0x22ad 1 0 2 HDMI_ACR_CTS 12 31 regDIG2_HDMI_ACR_STATUS_1 0 0x22ae 1 0 2 HDMI_ACR_N 0 19 regDIG2_AFMT_CNTL 0 0x22af 2 0 2 AFMT_AUDIO_CLOCK_EN 0 0 AFMT_AUDIO_CLOCK_ON 8 8 regDIG2_DIG_BE_CNTL 0 0x22b0 6 0 2 DIG_DUAL_LINK_ENABLE 0 0 DIG_SWAP 1 1 DIG_RB_SWITCH_EN 2 2 DIG_FE_SOURCE_SELECT 8 14 DIG_MODE 16 18 DIG_HPD_SELECT 28 30 regDIG2_DIG_BE_EN_CNTL 0 0x22b1 2 0 2 DIG_ENABLE 0 0 DIG_SYMCLK_BE_ON 8 8 regDIG2_TMDS_CNTL 0 0x22d7 1 0 2 TMDS_SYNC_PHASE 0 0 regDIG2_TMDS_CONTROL_CHAR 0 0x22d8 4 0 2 TMDS_CONTROL_CHAR0_OUT_EN 0 0 TMDS_CONTROL_CHAR1_OUT_EN 1 1 TMDS_CONTROL_CHAR2_OUT_EN 2 2 TMDS_CONTROL_CHAR3_OUT_EN 3 3 regDIG2_TMDS_CONTROL0_FEEDBACK 0 0x22d9 2 0 2 TMDS_CONTROL0_FEEDBACK_SELECT 0 1 TMDS_CONTROL0_FEEDBACK_DELAY 8 9 regDIG2_TMDS_STEREOSYNC_CTL_SEL 0 0x22da 1 0 2 TMDS_STEREOSYNC_CTL_SEL 0 1 regDIG2_TMDS_SYNC_CHAR_PATTERN_0_1 0 0x22db 2 0 2 TMDS_SYNC_CHAR_PATTERN0 0 9 TMDS_SYNC_CHAR_PATTERN1 16 25 regDIG2_TMDS_SYNC_CHAR_PATTERN_2_3 0 0x22dc 2 0 2 TMDS_SYNC_CHAR_PATTERN2 0 9 TMDS_SYNC_CHAR_PATTERN3 16 25 regDIG2_TMDS_CTL_BITS 0 0x22de 4 0 2 TMDS_CTL0 0 0 TMDS_CTL1 8 8 TMDS_CTL2 16 16 TMDS_CTL3 24 24 regDIG2_TMDS_DCBALANCER_CONTROL 0 0x22df 5 0 2 TMDS_DCBALANCER_EN 0 0 TMDS_SYNC_DCBAL_EN 4 6 TMDS_DCBALANCER_TEST_EN 8 8 TMDS_DCBALANCER_TEST_IN 16 19 TMDS_DCBALANCER_FORCE 24 24 regDIG2_TMDS_SYNC_DCBALANCE_CHAR 0 0x22e0 2 0 2 TMDS_SYNC_DCBAL_CHAR01 0 9 TMDS_SYNC_DCBAL_CHAR11 16 25 regDIG2_TMDS_CTL0_1_GEN_CNTL 0 0x22e1 15 0 2 TMDS_CTL0_DATA_SEL 0 3 TMDS_CTL0_DATA_DELAY 4 6 TMDS_CTL0_DATA_INVERT 7 7 TMDS_CTL0_DATA_MODULATION 8 9 TMDS_CTL0_USE_FEEDBACK_PATH 10 10 TMDS_CTL0_FB_SYNC_CONT 11 11 TMDS_CTL0_PATTERN_OUT_EN 12 12 TMDS_CTL1_DATA_SEL 16 19 TMDS_CTL1_DATA_DELAY 20 22 TMDS_CTL1_DATA_INVERT 23 23 TMDS_CTL1_DATA_MODULATION 24 25 TMDS_CTL1_USE_FEEDBACK_PATH 26 26 TMDS_CTL1_FB_SYNC_CONT 27 27 TMDS_CTL1_PATTERN_OUT_EN 28 28 TMDS_2BIT_COUNTER_EN 31 31 regDIG2_TMDS_CTL2_3_GEN_CNTL 0 0x22e2 14 0 2 TMDS_CTL2_DATA_SEL 0 3 TMDS_CTL2_DATA_DELAY 4 6 TMDS_CTL2_DATA_INVERT 7 7 TMDS_CTL2_DATA_MODULATION 8 9 TMDS_CTL2_USE_FEEDBACK_PATH 10 10 TMDS_CTL2_FB_SYNC_CONT 11 11 TMDS_CTL2_PATTERN_OUT_EN 12 12 TMDS_CTL3_DATA_SEL 16 19 TMDS_CTL3_DATA_DELAY 20 22 TMDS_CTL3_DATA_INVERT 23 23 TMDS_CTL3_DATA_MODULATION 24 25 TMDS_CTL3_USE_FEEDBACK_PATH 26 26 TMDS_CTL3_FB_SYNC_CONT 27 27 TMDS_CTL3_PATTERN_OUT_EN 28 28 regDIG2_DIG_VERSION 0 0x22e4 1 0 2 DIG_TYPE 0 0 regDIG2_FORCE_DIG_DISABLE 0 0x22e5 1 0 2 FORCE_DIG_DISABLE 0 0 regDP3_DP_LINK_CNTL 0 0x2408 3 0 2 DP_LINK_TRAINING_COMPLETE 4 4 DP_LINK_STATUS 8 8 DP_EMBEDDED_PANEL_MODE 17 17 regDP3_DP_PIXEL_FORMAT 0 0x2409 3 0 2 DP_PIXEL_ENCODING 0 2 DP_COMPONENT_DEPTH 24 26 DP_PIXEL_COMBINE 28 29 regDP3_DP_MSA_COLORIMETRY 0 0x240a 1 0 2 DP_MSA_MISC0 24 31 regDP3_DP_CONFIG 0 0x240b 1 0 2 DP_UDI_LANES 0 1 regDP3_DP_VID_STREAM_CNTL 0 0x240c 4 0 2 DP_VID_STREAM_ENABLE 0 0 DP_VID_STREAM_DIS_DEFER 8 9 DP_VID_STREAM_STATUS 16 16 DP_VID_STREAM_CHANGE_KEEPOUT 20 20 regDP3_DP_STEER_FIFO 0 0x240d 7 0 2 DP_STEER_FIFO_RESET 0 0 DP_STEER_OVERFLOW_FLAG 4 4 DP_STEER_OVERFLOW_INT 5 5 DP_STEER_OVERFLOW_ACK 6 6 DP_STEER_OVERFLOW_MASK 7 7 DP_TU_OVERFLOW_FLAG 8 8 DP_TU_OVERFLOW_ACK 12 12 regDP3_DP_MSA_MISC 0 0x240e 4 0 2 DP_MSA_MISC1 0 7 DP_MSA_MISC2 8 15 DP_MSA_MISC3 16 23 DP_MSA_MISC4 24 31 regDP3_DP_DPHY_INTERNAL_CTRL 0 0x240f 2 0 2 DPHY_ALT_SCRAMBLER_RESET_EN 0 0 DPHY_ALT_SCRAMBLER_RESET_SEL 4 4 regDP3_DP_VID_TIMING 0 0x2410 5 0 2 DP_VID_M_N_DOUBLE_BUFFER_MODE 4 4 DP_VID_M_N_GEN_EN 8 8 DP_VID_N_MUL 10 11 DP_VID_M_DIV 12 13 DP_VID_N_DIV 24 31 regDP3_DP_VID_N 0 0x2411 1 0 2 DP_VID_N 0 23 regDP3_DP_VID_M 0 0x2412 1 0 2 DP_VID_M 0 23 regDP3_DP_LINK_FRAMING_CNTL 0 0x2413 3 0 2 DP_IDLE_BS_INTERVAL 0 17 DP_VBID_DISABLE 24 24 DP_VID_ENHANCED_FRAME_MODE 28 28 regDP3_DP_HBR2_EYE_PATTERN 0 0x2414 1 0 2 DP_HBR2_EYE_PATTERN_ENABLE 0 0 regDP3_DP_VID_MSA_VBID 0 0x2415 2 0 2 DP_VID_MSA_LOCATION 0 11 DP_VID_VBID_FIELD_POL 24 24 regDP3_DP_VID_INTERRUPT_CNTL 0 0x2416 3 0 2 DP_VID_STREAM_DISABLE_INT 0 0 DP_VID_STREAM_DISABLE_ACK 1 1 DP_VID_STREAM_DISABLE_MASK 2 2 regDP3_DP_DPHY_CNTL 0 0x2417 10 0 2 DPHY_ATEST_SEL_LANE0 0 0 DPHY_ATEST_SEL_LANE1 1 1 DPHY_ATEST_SEL_LANE2 2 2 DPHY_ATEST_SEL_LANE3 3 3 DPHY_FEC_EN 4 4 DPHY_FEC_READY_SHADOW 5 5 DPHY_FEC_ACTIVE_STATUS 6 6 DPHY_SCRAMBLER_SEL 8 8 DPHY_BYPASS 16 16 DPHY_SKEW_BYPASS 24 24 regDP3_DP_DPHY_TRAINING_PATTERN_SEL 0 0x2418 1 0 2 DPHY_TRAINING_PATTERN_SEL 0 1 regDP3_DP_DPHY_SYM0 0 0x2419 3 0 2 DPHY_SYM1 0 9 DPHY_SYM2 10 19 DPHY_SYM3 20 29 regDP3_DP_DPHY_SYM1 0 0x241a 3 0 2 DPHY_SYM4 0 9 DPHY_SYM5 10 19 DPHY_SYM6 20 29 regDP3_DP_DPHY_SYM2 0 0x241b 2 0 2 DPHY_SYM7 0 9 DPHY_SYM8 10 19 regDP3_DP_DPHY_8B10B_CNTL 0 0x241c 3 0 2 DPHY_8B10B_RESET 8 8 DPHY_8B10B_EXT_DISP 16 16 DPHY_8B10B_CUR_DISP 24 24 regDP3_DP_DPHY_PRBS_CNTL 0 0x241d 3 0 2 DPHY_PRBS_EN 0 0 DPHY_PRBS_SEL 4 5 DPHY_PRBS_SEED 8 30 regDP3_DP_DPHY_SCRAM_CNTL 0 0x241e 4 0 2 DPHY_SCRAMBLER_DIS 0 0 DPHY_SCRAMBLER_ADVANCE 4 4 DPHY_SCRAMBLER_BS_COUNT 8 17 DPHY_SCRAMBLER_KCODE 24 24 regDP3_DP_DPHY_CRC_EN 0 0x241f 3 0 2 DPHY_CRC_EN 0 0 DPHY_CRC_CONT_EN 4 4 DPHY_CRC_RESULT_VALID 8 8 regDP3_DP_DPHY_CRC_CNTL 0 0x2420 3 0 2 DPHY_CRC_FIELD 0 0 DPHY_CRC_SEL 4 5 DPHY_CRC_MASK 16 23 regDP3_DP_DPHY_CRC_RESULT 0 0x2421 4 0 2 DPHY_CRC_RESULT 0 7 DPHY_CRC_RESULT1 8 15 DPHY_CRC_RESULT2 16 23 DPHY_CRC_RESULT3 24 31 regDP3_DP_DPHY_CRC_MST_CNTL 0 0x2422 2 0 2 DPHY_CRC_MST_FIRST_SLOT 0 5 DPHY_CRC_MST_LAST_SLOT 8 13 regDP3_DP_DPHY_CRC_MST_STATUS 0 0x2423 3 0 2 DPHY_CRC_MST_PHASE_LOCK 0 0 DPHY_CRC_MST_PHASE_ERROR 8 8 DPHY_CRC_MST_PHASE_ERROR_ACK 16 16 regDP3_DP_DPHY_FAST_TRAINING 0 0x2424 6 0 2 DPHY_RX_FAST_TRAINING_CAPABLE 0 0 DPHY_SW_FAST_TRAINING_START 1 1 DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN 2 2 DPHY_STREAM_RESET_DURING_FAST_TRAINING 4 4 DPHY_FAST_TRAINING_TP1_TIME 8 19 DPHY_FAST_TRAINING_TP2_TIME 20 31 regDP3_DP_DPHY_FAST_TRAINING_STATUS 0 0x2425 4 0 2 DPHY_FAST_TRAINING_STATE 0 2 DPHY_FAST_TRAINING_COMPLETE_OCCURRED 4 4 DPHY_FAST_TRAINING_COMPLETE_MASK 8 8 DPHY_FAST_TRAINING_COMPLETE_ACK 12 12 regDP3_DP_SEC_CNTL 0 0x242b 14 0 2 DP_SEC_STREAM_ENABLE 0 0 DP_SEC_ASP_ENABLE 4 4 DP_SEC_ATP_ENABLE 8 8 DP_SEC_AIP_ENABLE 12 12 DP_SEC_ACM_ENABLE 16 16 DP_SEC_GSP0_ENABLE 20 20 DP_SEC_GSP1_ENABLE 21 21 DP_SEC_GSP2_ENABLE 22 22 DP_SEC_GSP3_ENABLE 23 23 DP_SEC_GSP4_ENABLE 24 24 DP_SEC_GSP5_ENABLE 25 25 DP_SEC_GSP6_ENABLE 26 26 DP_SEC_GSP7_ENABLE 27 27 DP_SEC_MPG_ENABLE 28 28 regDP3_DP_SEC_CNTL1 0 0x242c 15 0 2 DP_SEC_ISRC_ENABLE 0 0 DP_SEC_GSP0_LINE_REFERENCE 1 1 DP_SEC_GSP0_PRIORITY 4 4 DP_SEC_GSP0_SEND 5 5 DP_SEC_GSP0_SEND_PENDING 6 6 DP_SEC_GSP0_SEND_DEADLINE_MISSED 7 7 DP_SEC_GSP0_SEND_ANY_LINE 8 8 DP_SEC_GSP1_LINE_REFERENCE 9 9 DP_SEC_GSP2_LINE_REFERENCE 10 10 DP_SEC_GSP3_LINE_REFERENCE 11 11 DP_SEC_GSP4_LINE_REFERENCE 12 12 DP_SEC_GSP5_LINE_REFERENCE 13 13 DP_SEC_GSP6_LINE_REFERENCE 14 14 DP_SEC_GSP7_LINE_REFERENCE 15 15 DP_SEC_GSP0_LINE_NUM 16 31 regDP3_DP_SEC_FRAMING1 0 0x242d 2 0 2 DP_SEC_FRAME_START_LOCATION 0 11 DP_SEC_VBLANK_TRANSMIT_WIDTH 16 31 regDP3_DP_SEC_FRAMING2 0 0x242e 2 0 2 DP_SEC_START_POSITION 0 15 DP_SEC_HBLANK_TRANSMIT_WIDTH 16 31 regDP3_DP_SEC_FRAMING3 0 0x242f 2 0 2 DP_SEC_IDLE_FRAME_SIZE 0 13 DP_SEC_IDLE_TRANSMIT_WIDTH 16 31 regDP3_DP_SEC_FRAMING4 0 0x2430 5 0 2 DP_SST_SDP_SPLITTING 0 0 DP_SEC_COLLISION_STATUS 20 20 DP_SEC_COLLISION_ACK 24 24 DP_SEC_AUDIO_MUTE 28 28 DP_SEC_AUDIO_MUTE_STATUS 29 29 regDP3_DP_SEC_AUD_N 0 0x2431 1 0 2 DP_SEC_AUD_N 0 23 regDP3_DP_SEC_AUD_N_READBACK 0 0x2432 1 0 2 DP_SEC_AUD_N_READBACK 0 23 regDP3_DP_SEC_AUD_M 0 0x2433 1 0 2 DP_SEC_AUD_M 0 23 regDP3_DP_SEC_AUD_M_READBACK 0 0x2434 1 0 2 DP_SEC_AUD_M_READBACK 0 23 regDP3_DP_SEC_TIMESTAMP 0 0x2435 1 0 2 DP_SEC_TIMESTAMP_MODE 0 0 regDP3_DP_SEC_PACKET_CNTL 0 0x2436 4 0 2 DP_SEC_ASP_CODING_TYPE 1 3 DP_SEC_ASP_PRIORITY 4 4 DP_SEC_VERSION 8 13 DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE 16 16 regDP3_DP_MSE_RATE_CNTL 0 0x2437 2 0 2 DP_MSE_RATE_Y 0 25 DP_MSE_RATE_X 26 31 regDP3_DP_MSE_RATE_UPDATE 0 0x2439 1 0 2 DP_MSE_RATE_UPDATE_PENDING 0 0 regDP3_DP_MSE_SAT0 0 0x243a 8 0 2 DP_MSE_SAT_SRC0 0 2 DP_MSE_SAT_ENCRYPT0 4 4 DP_MSE_SAT_ENCRYPTION_TYPE0 5 5 DP_MSE_SAT_SLOT_COUNT0 8 13 DP_MSE_SAT_SRC1 16 18 DP_MSE_SAT_ENCRYPT1 20 20 DP_MSE_SAT_ENCRYPTION_TYPE1 21 21 DP_MSE_SAT_SLOT_COUNT1 24 29 regDP3_DP_MSE_SAT1 0 0x243b 8 0 2 DP_MSE_SAT_SRC2 0 2 DP_MSE_SAT_ENCRYPT2 4 4 DP_MSE_SAT_ENCRYPTION_TYPE2 5 5 DP_MSE_SAT_SLOT_COUNT2 8 13 DP_MSE_SAT_SRC3 16 18 DP_MSE_SAT_ENCRYPT3 20 20 DP_MSE_SAT_ENCRYPTION_TYPE3 21 21 DP_MSE_SAT_SLOT_COUNT3 24 29 regDP3_DP_MSE_SAT2 0 0x243c 8 0 2 DP_MSE_SAT_SRC4 0 2 DP_MSE_SAT_ENCRYPT4 4 4 DP_MSE_SAT_ENCRYPTION_TYPE4 5 5 DP_MSE_SAT_SLOT_COUNT4 8 13 DP_MSE_SAT_SRC5 16 18 DP_MSE_SAT_ENCRYPT5 20 20 DP_MSE_SAT_ENCRYPTION_TYPE5 21 21 DP_MSE_SAT_SLOT_COUNT5 24 29 regDP3_DP_MSE_SAT_UPDATE 0 0x243d 2 0 2 DP_MSE_SAT_UPDATE 0 1 DP_MSE_16_MTP_KEEPOUT 8 8 regDP3_DP_MSE_LINK_TIMING 0 0x243e 2 0 2 DP_MSE_LINK_FRAME 0 9 DP_MSE_LINK_LINE 16 17 regDP3_DP_MSE_MISC_CNTL 0 0x243f 3 0 2 DP_MSE_BLANK_CODE 0 0 DP_MSE_TIMESTAMP_MODE 4 4 DP_MSE_ZERO_ENCODER 8 8 regDP3_DP_DPHY_BS_SR_SWAP_CNTL 0 0x2444 3 0 2 DPHY_LOAD_BS_COUNT 0 9 DPHY_BS_SR_SWAP_DONE 15 15 DPHY_LOAD_BS_COUNT_START 16 16 regDP3_DP_DPHY_HBR2_PATTERN_CONTROL 0 0x2445 1 0 2 DP_DPHY_HBR2_PATTERN_CONTROL 0 2 regDP3_DP_MSE_SAT0_STATUS 0 0x2447 8 0 2 DP_MSE_SAT_SRC0_STATUS 0 2 DP_MSE_SAT_ENCRYPT0_STATUS 4 4 DP_MSE_SAT_ENCRYPTION_TYPE0_STATUS 5 5 DP_MSE_SAT_SLOT_COUNT0_STATUS 8 13 DP_MSE_SAT_SRC1_STATUS 16 18 DP_MSE_SAT_ENCRYPT1_STATUS 20 20 DP_MSE_SAT_ENCRYPTION_TYPE1_STATUS 21 21 DP_MSE_SAT_SLOT_COUNT1_STATUS 24 29 regDP3_DP_MSE_SAT1_STATUS 0 0x2448 8 0 2 DP_MSE_SAT_SRC2_STATUS 0 2 DP_MSE_SAT_ENCRYPT2_STATUS 4 4 DP_MSE_SAT_ENCRYPTION_TYPE2_STATUS 5 5 DP_MSE_SAT_SLOT_COUNT2_STATUS 8 13 DP_MSE_SAT_SRC3_STATUS 16 18 DP_MSE_SAT_ENCRYPT3_STATUS 20 20 DP_MSE_SAT_ENCRYPTION_TYPE3_STATUS 21 21 DP_MSE_SAT_SLOT_COUNT3_STATUS 24 29 regDP3_DP_MSE_SAT2_STATUS 0 0x2449 8 0 2 DP_MSE_SAT_SRC4_STATUS 0 2 DP_MSE_SAT_ENCRYPT4_STATUS 4 4 DP_MSE_SAT_ENCRYPTION_TYPE4_STATUS 5 5 DP_MSE_SAT_SLOT_COUNT4_STATUS 8 13 DP_MSE_SAT_SRC5_STATUS 16 18 DP_MSE_SAT_ENCRYPT5_STATUS 20 20 DP_MSE_SAT_ENCRYPTION_TYPE5_STATUS 21 21 DP_MSE_SAT_SLOT_COUNT5_STATUS 24 29 regDP3_DP_MSA_TIMING_PARAM1 0 0x244c 2 0 2 DP_MSA_VTOTAL 0 15 DP_MSA_HTOTAL 16 31 regDP3_DP_MSA_TIMING_PARAM2 0 0x244d 2 0 2 DP_MSA_VSTART 0 15 DP_MSA_HSTART 16 31 regDP3_DP_MSA_TIMING_PARAM3 0 0x244e 4 0 2 DP_MSA_VSYNCWIDTH 0 14 DP_MSA_VSYNCPOLARITY 15 15 DP_MSA_HSYNCWIDTH 16 30 DP_MSA_HSYNCPOLARITY 31 31 regDP3_DP_MSA_TIMING_PARAM4 0 0x244f 2 0 2 DP_MSA_VHEIGHT 0 15 DP_MSA_HWIDTH 16 31 regDP3_DP_MSO_CNTL 0 0x2450 8 0 2 DP_MSO_NUM_OF_SSTLINK 0 1 DP_MSO_SEC_STREAM_ENABLE 4 7 DP_MSO_SEC_ASP_ENABLE 8 11 DP_MSO_SEC_ATP_ENABLE 12 15 DP_MSO_SEC_AIP_ENABLE 16 19 DP_MSO_SEC_ACM_ENABLE 20 23 DP_MSO_SEC_GSP0_ENABLE 24 27 DP_MSO_SEC_GSP1_ENABLE 28 31 regDP3_DP_MSO_CNTL1 0 0x2451 8 0 2 DP_MSO_SEC_GSP2_ENABLE 0 3 DP_MSO_SEC_GSP3_ENABLE 4 7 DP_MSO_SEC_GSP4_ENABLE 8 11 DP_MSO_SEC_GSP5_ENABLE 12 15 DP_MSO_SEC_GSP6_ENABLE 16 19 DP_MSO_SEC_GSP7_ENABLE 20 23 DP_MSO_SEC_MPG_ENABLE 24 27 DP_MSO_SEC_ISRC_ENABLE 28 31 regDP3_DP_DSC_CNTL 0 0x2452 2 0 2 DP_DSC_MODE 0 1 DP_DSC_SLICE_WIDTH 16 28 regDP3_DP_SEC_CNTL2 0 0x2453 29 0 2 DP_SEC_GSP1_SEND 0 0 DP_SEC_GSP1_SEND_PENDING 1 1 DP_SEC_GSP1_SEND_DEADLINE_MISSED 2 2 DP_SEC_GSP1_SEND_ANY_LINE 3 3 DP_SEC_GSP2_SEND 4 4 DP_SEC_GSP2_SEND_PENDING 5 5 DP_SEC_GSP2_SEND_DEADLINE_MISSED 6 6 DP_SEC_GSP2_SEND_ANY_LINE 7 7 DP_SEC_GSP3_SEND 8 8 DP_SEC_GSP3_SEND_PENDING 9 9 DP_SEC_GSP3_SEND_DEADLINE_MISSED 10 10 DP_SEC_GSP3_SEND_ANY_LINE 11 11 DP_SEC_GSP4_SEND 12 12 DP_SEC_GSP4_SEND_PENDING 13 13 DP_SEC_GSP4_SEND_DEADLINE_MISSED 14 14 DP_SEC_GSP4_SEND_ANY_LINE 15 15 DP_SEC_GSP5_SEND 16 16 DP_SEC_GSP5_SEND_PENDING 17 17 DP_SEC_GSP5_SEND_DEADLINE_MISSED 18 18 DP_SEC_GSP5_SEND_ANY_LINE 19 19 DP_SEC_GSP6_SEND 20 20 DP_SEC_GSP6_SEND_PENDING 21 21 DP_SEC_GSP6_SEND_DEADLINE_MISSED 22 22 DP_SEC_GSP6_SEND_ANY_LINE 23 23 DP_SEC_GSP7_SEND 24 24 DP_SEC_GSP7_SEND_PENDING 25 25 DP_SEC_GSP7_SEND_DEADLINE_MISSED 26 26 DP_SEC_GSP7_SEND_ANY_LINE 27 27 DP_SEC_GSP11_PPS 28 28 regDP3_DP_SEC_CNTL3 0 0x2454 2 0 2 DP_SEC_GSP1_LINE_NUM 0 15 DP_SEC_GSP2_LINE_NUM 16 31 regDP3_DP_SEC_CNTL4 0 0x2455 2 0 2 DP_SEC_GSP3_LINE_NUM 0 15 DP_SEC_GSP4_LINE_NUM 16 31 regDP3_DP_SEC_CNTL5 0 0x2456 2 0 2 DP_SEC_GSP5_LINE_NUM 0 15 DP_SEC_GSP6_LINE_NUM 16 31 regDP3_DP_SEC_CNTL6 0 0x2457 13 0 2 DP_SEC_GSP7_LINE_NUM 0 15 DP_SEC_GSP0_EN_DB_DISABLE 16 16 DP_SEC_GSP1_EN_DB_DISABLE 17 17 DP_SEC_GSP2_EN_DB_DISABLE 18 18 DP_SEC_GSP3_EN_DB_DISABLE 19 19 DP_SEC_GSP4_EN_DB_DISABLE 20 20 DP_SEC_GSP5_EN_DB_DISABLE 21 21 DP_SEC_GSP6_EN_DB_DISABLE 22 22 DP_SEC_GSP7_EN_DB_DISABLE 23 23 DP_SEC_GSP8_EN_DB_DISABLE 24 24 DP_SEC_GSP9_EN_DB_DISABLE 25 25 DP_SEC_GSP10_EN_DB_DISABLE 26 26 DP_SEC_GSP11_EN_DB_DISABLE 27 27 regDP3_DP_SEC_CNTL7 0 0x2458 16 0 2 DP_SEC_GSP0_SEND_ACTIVE 0 0 DP_SEC_GSP0_SEND_IN_IDLE 1 1 DP_SEC_GSP1_SEND_ACTIVE 4 4 DP_SEC_GSP1_SEND_IN_IDLE 5 5 DP_SEC_GSP2_SEND_ACTIVE 8 8 DP_SEC_GSP2_SEND_IN_IDLE 9 9 DP_SEC_GSP3_SEND_ACTIVE 12 12 DP_SEC_GSP3_SEND_IN_IDLE 13 13 DP_SEC_GSP4_SEND_ACTIVE 16 16 DP_SEC_GSP4_SEND_IN_IDLE 17 17 DP_SEC_GSP5_SEND_ACTIVE 20 20 DP_SEC_GSP5_SEND_IN_IDLE 21 21 DP_SEC_GSP6_SEND_ACTIVE 24 24 DP_SEC_GSP6_SEND_IN_IDLE 25 25 DP_SEC_GSP7_SEND_ACTIVE 28 28 DP_SEC_GSP7_SEND_IN_IDLE 29 29 regDP3_DP_DB_CNTL 0 0x2459 8 0 2 DP_DB_PENDING 0 0 DP_DB_TAKEN 4 4 DP_DB_TAKEN_CLR 5 5 DP_DB_LOCK 8 8 DP_DB_DISABLE 12 12 DP_VUPDATE_DB_PENDING 15 15 DP_VUPDATE_DB_TAKEN 16 16 DP_VUPDATE_DB_TAKEN_CLR 17 17 regDP3_DP_MSA_VBID_MISC 0 0x245a 8 0 2 DP_MSA_MISC1_STEREOSYNC_OVERRIDE 0 1 DP_MSA_MISC1_STEREOSYNC_OVERRIDE_EN 4 4 DP_VBID1_OVERRIDE 8 8 DP_VBID2_OVERRIDE 9 9 DP_VBID1_OVERRIDE_EN 12 12 DP_VBID2_OVERRIDE_EN 13 13 DP_VBID6_LINE_REFERENCE 15 15 DP_VBID6_LINE_NUM 16 31 regDP3_DP_SEC_METADATA_TRANSMISSION 0 0x245b 4 0 2 DP_SEC_METADATA_PACKET_ENABLE 0 0 DP_SEC_METADATA_PACKET_LINE_REFERENCE 1 1 DP_SEC_MSO_METADATA_PACKET_ENABLE 4 7 DP_SEC_METADATA_PACKET_LINE 16 31 regDP3_DP_DSC_BYTES_PER_PIXEL 0 0x245c 1 0 2 DP_DSC_BYTES_PER_PIXEL 0 30 regDP3_DP_ALPM_CNTL 0 0x245d 7 0 2 DP_ML_PHY_SLEEP_SEND 0 0 DP_ML_PHY_SLEEP_PENDING 1 1 DP_ML_PHY_STANDBY_SEND 2 2 DP_ML_PHY_STANDBY_PENDING 3 3 DP_ML_PHY_SLEEP_STANDBY_IMMEDIATE 4 4 DP_LINK_TRAINING_SWITCH_BETWEEN_VIDEO 5 5 DP_ML_PHY_SLEEP_STANDBY_LINE_NUM 16 31 regDP3_DP_GSP8_CNTL 0 0x245e 10 0 2 DP_MSO_SEC_GSP8_ENABLE 0 3 DP_SEC_GSP8_ENABLE 4 4 DP_SEC_GSP8_LINE_REFERENCE 5 5 DP_SEC_GSP8_SEND_IN_IDLE 6 6 DP_SEC_GSP8_SEND 7 7 DP_SEC_GSP8_SEND_ANY_LINE 8 8 DP_SEC_GSP8_SEND_PENDING 12 12 DP_SEC_GSP8_SEND_ACTIVE 13 13 DP_SEC_GSP8_SEND_DEADLINE_MISSED 14 14 DP_SEC_GSP8_LINE_NUM 16 31 regDP3_DP_GSP9_CNTL 0 0x245f 10 0 2 DP_MSO_SEC_GSP9_ENABLE 0 3 DP_SEC_GSP9_ENABLE 4 4 DP_SEC_GSP9_LINE_REFERENCE 5 5 DP_SEC_GSP9_SEND_IN_IDLE 6 6 DP_SEC_GSP9_SEND 7 7 DP_SEC_GSP9_SEND_ANY_LINE 8 8 DP_SEC_GSP9_SEND_PENDING 12 12 DP_SEC_GSP9_SEND_ACTIVE 13 13 DP_SEC_GSP9_SEND_DEADLINE_MISSED 14 14 DP_SEC_GSP9_LINE_NUM 16 31 regDP3_DP_GSP10_CNTL 0 0x2460 10 0 2 DP_MSO_SEC_GSP10_ENABLE 0 3 DP_SEC_GSP10_ENABLE 4 4 DP_SEC_GSP10_LINE_REFERENCE 5 5 DP_SEC_GSP10_SEND_IN_IDLE 6 6 DP_SEC_GSP10_SEND 7 7 DP_SEC_GSP10_SEND_ANY_LINE 8 8 DP_SEC_GSP10_SEND_PENDING 12 12 DP_SEC_GSP10_SEND_ACTIVE 13 13 DP_SEC_GSP10_SEND_DEADLINE_MISSED 14 14 DP_SEC_GSP10_LINE_NUM 16 31 regDP3_DP_GSP11_CNTL 0 0x2461 10 0 2 DP_MSO_SEC_GSP11_ENABLE 0 3 DP_SEC_GSP11_ENABLE 4 4 DP_SEC_GSP11_LINE_REFERENCE 5 5 DP_SEC_GSP11_SEND_IN_IDLE 6 6 DP_SEC_GSP11_SEND 7 7 DP_SEC_GSP11_SEND_ANY_LINE 8 8 DP_SEC_GSP11_SEND_PENDING 12 12 DP_SEC_GSP11_SEND_ACTIVE 13 13 DP_SEC_GSP11_SEND_DEADLINE_MISSED 14 14 DP_SEC_GSP11_LINE_NUM 16 31 regDP3_DP_GSP_EN_DB_STATUS 0 0x2462 12 0 2 DP_SEC_GSP0_EN_DB_PENDING 0 0 DP_SEC_GSP1_EN_DB_PENDING 1 1 DP_SEC_GSP2_EN_DB_PENDING 2 2 DP_SEC_GSP3_EN_DB_PENDING 3 3 DP_SEC_GSP4_EN_DB_PENDING 4 4 DP_SEC_GSP5_EN_DB_PENDING 5 5 DP_SEC_GSP6_EN_DB_PENDING 6 6 DP_SEC_GSP7_EN_DB_PENDING 7 7 DP_SEC_GSP8_EN_DB_PENDING 8 8 DP_SEC_GSP9_EN_DB_PENDING 9 9 DP_SEC_GSP10_EN_DB_PENDING 10 10 DP_SEC_GSP11_EN_DB_PENDING 11 11 regDIG3_DIG_FE_CNTL 0 0x238b 11 0 2 DIG_SOURCE_SELECT 0 2 DIG_STEREOSYNC_SELECT 4 6 DIG_STEREOSYNC_GATE_EN 8 8 DIG_START 10 10 DIG_DIGITAL_BYPASS_SELECT 12 14 DIG_INPUT_PIXEL_SELECT 16 17 DOLBY_VISION_EN 18 18 DOLBY_VISION_METADATA_PACKET_MISSED 19 19 DIG_SYMCLK_FE_ON 24 24 TMDS_PIXEL_ENCODING 28 28 TMDS_COLOR_FORMAT 30 31 regDIG3_DIG_OUTPUT_CRC_CNTL 0 0x238c 3 0 2 DIG_OUTPUT_CRC_EN 0 0 DIG_OUTPUT_CRC_LINK_SEL 4 4 DIG_OUTPUT_CRC_DATA_SEL 8 9 regDIG3_DIG_OUTPUT_CRC_RESULT 0 0x238d 1 0 2 DIG_OUTPUT_CRC_RESULT 0 29 regDIG3_DIG_CLOCK_PATTERN 0 0x238e 1 0 2 DIG_CLOCK_PATTERN 0 9 regDIG3_DIG_TEST_PATTERN 0 0x238f 6 0 2 DIG_TEST_PATTERN_OUT_EN 0 0 DIG_HALF_CLOCK_PATTERN_SEL 1 1 DIG_RANDOM_PATTERN_OUT_EN 4 4 DIG_RANDOM_PATTERN_RESET 5 5 DIG_TEST_PATTERN_EXTERNAL_RESET_EN 6 6 DIG_STATIC_TEST_PATTERN 16 25 regDIG3_DIG_RANDOM_PATTERN_SEED 0 0x2390 2 0 2 DIG_RANDOM_PATTERN_SEED 0 23 DIG_RAN_PAT_DURING_DE_ONLY 24 24 regDIG3_DIG_FIFO_STATUS 0 0x2391 11 0 2 DIG_FIFO_LEVEL_ERROR 0 0 DIG_FIFO_USE_OVERWRITE_LEVEL 1 1 DIG_FIFO_OVERWRITE_LEVEL 2 7 DIG_FIFO_ERROR_ACK 8 8 DIG_FIFO_CAL_AVERAGE_LEVEL 10 15 DIG_FIFO_MAXIMUM_LEVEL 16 20 DIG_FIFO_MINIMUM_LEVEL 22 25 DIG_FIFO_READ_CLOCK_SRC 26 26 DIG_FIFO_CALIBRATED 29 29 DIG_FIFO_FORCE_RECAL_AVERAGE 30 30 DIG_FIFO_FORCE_RECOMP_MINMAX 31 31 regDIG3_HDMI_METADATA_PACKET_CONTROL 0 0x2392 4 0 2 HDMI_METADATA_PACKET_ENABLE 0 0 HDMI_METADATA_PACKET_LINE_REFERENCE 4 4 HDMI_METADATA_PACKET_MISSED 8 8 HDMI_METADATA_PACKET_LINE 16 31 regDIG3_HDMI_CONTROL 0 0x2393 10 0 2 HDMI_KEEPOUT_MODE 0 0 HDMI_DATA_SCRAMBLE_EN 1 1 HDMI_CLOCK_CHANNEL_RATE 2 2 HDMI_NO_EXTRA_NULL_PACKET_FILLED 3 3 HDMI_PACKET_GEN_VERSION 4 4 HDMI_ERROR_ACK 8 8 HDMI_ERROR_MASK 9 9 HDMI_UNSCRAMBLED_CONTROL_LINE_NUM 16 21 HDMI_DEEP_COLOR_ENABLE 24 24 HDMI_DEEP_COLOR_DEPTH 28 29 regDIG3_HDMI_STATUS 0 0x2394 4 0 2 HDMI_ACTIVE_AVMUTE 0 0 HDMI_AUDIO_PACKET_ERROR 16 16 HDMI_VBI_PACKET_ERROR 20 20 HDMI_ERROR_INT 27 27 regDIG3_HDMI_AUDIO_PACKET_CONTROL 0 0x2395 1 0 2 HDMI_AUDIO_DELAY_EN 4 5 regDIG3_HDMI_ACR_PACKET_CONTROL 0 0x2396 7 0 2 HDMI_ACR_SEND 0 0 HDMI_ACR_CONT 1 1 HDMI_ACR_SELECT 4 5 HDMI_ACR_SOURCE 8 8 HDMI_ACR_AUTO_SEND 12 12 HDMI_ACR_N_MULTIPLE 16 18 HDMI_ACR_AUDIO_PRIORITY 31 31 regDIG3_HDMI_VBI_PACKET_CONTROL 0 0x2397 8 0 2 HDMI_NULL_SEND 0 0 HDMI_GC_SEND 4 4 HDMI_GC_CONT 5 5 HDMI_ISRC_SEND 8 8 HDMI_ISRC_CONT 9 9 HDMI_ACP_SEND 12 12 HDMI_ISRC_LINE 16 21 HDMI_ACP_LINE 24 29 regDIG3_HDMI_INFOFRAME_CONTROL0 0 0x2398 4 0 2 HDMI_AUDIO_INFO_SEND 4 4 HDMI_AUDIO_INFO_CONT 5 5 HDMI_MPEG_INFO_SEND 8 8 HDMI_MPEG_INFO_CONT 9 9 regDIG3_HDMI_INFOFRAME_CONTROL1 0 0x2399 2 0 2 HDMI_AUDIO_INFO_LINE 8 13 HDMI_MPEG_INFO_LINE 16 21 regDIG3_HDMI_GENERIC_PACKET_CONTROL0 0 0x239a 32 0 2 HDMI_GENERIC0_SEND 0 0 HDMI_GENERIC0_CONT 1 1 HDMI_GENERIC0_LINE_REFERENCE 2 2 HDMI_GENERIC0_UPDATE_LOCK_DISABLE 3 3 HDMI_GENERIC1_SEND 4 4 HDMI_GENERIC1_CONT 5 5 HDMI_GENERIC1_LINE_REFERENCE 6 6 HDMI_GENERIC1_UPDATE_LOCK_DISABLE 7 7 HDMI_GENERIC2_SEND 8 8 HDMI_GENERIC2_CONT 9 9 HDMI_GENERIC2_LINE_REFERENCE 10 10 HDMI_GENERIC2_UPDATE_LOCK_DISABLE 11 11 HDMI_GENERIC3_SEND 12 12 HDMI_GENERIC3_CONT 13 13 HDMI_GENERIC3_LINE_REFERENCE 14 14 HDMI_GENERIC3_UPDATE_LOCK_DISABLE 15 15 HDMI_GENERIC4_SEND 16 16 HDMI_GENERIC4_CONT 17 17 HDMI_GENERIC4_LINE_REFERENCE 18 18 HDMI_GENERIC4_UPDATE_LOCK_DISABLE 19 19 HDMI_GENERIC5_SEND 20 20 HDMI_GENERIC5_CONT 21 21 HDMI_GENERIC5_LINE_REFERENCE 22 22 HDMI_GENERIC5_UPDATE_LOCK_DISABLE 23 23 HDMI_GENERIC6_SEND 24 24 HDMI_GENERIC6_CONT 25 25 HDMI_GENERIC6_LINE_REFERENCE 26 26 HDMI_GENERIC6_UPDATE_LOCK_DISABLE 27 27 HDMI_GENERIC7_SEND 28 28 HDMI_GENERIC7_CONT 29 29 HDMI_GENERIC7_LINE_REFERENCE 30 30 HDMI_GENERIC7_UPDATE_LOCK_DISABLE 31 31 regDIG3_HDMI_GENERIC_PACKET_CONTROL6 0 0x239b 28 0 2 HDMI_GENERIC8_SEND 0 0 HDMI_GENERIC8_CONT 1 1 HDMI_GENERIC8_LINE_REFERENCE 2 2 HDMI_GENERIC8_UPDATE_LOCK_DISABLE 3 3 HDMI_GENERIC9_SEND 4 4 HDMI_GENERIC9_CONT 5 5 HDMI_GENERIC9_LINE_REFERENCE 6 6 HDMI_GENERIC9_UPDATE_LOCK_DISABLE 7 7 HDMI_GENERIC10_SEND 8 8 HDMI_GENERIC10_CONT 9 9 HDMI_GENERIC10_LINE_REFERENCE 10 10 HDMI_GENERIC10_UPDATE_LOCK_DISABLE 11 11 HDMI_GENERIC11_SEND 12 12 HDMI_GENERIC11_CONT 13 13 HDMI_GENERIC11_LINE_REFERENCE 14 14 HDMI_GENERIC11_UPDATE_LOCK_DISABLE 15 15 HDMI_GENERIC12_SEND 16 16 HDMI_GENERIC12_CONT 17 17 HDMI_GENERIC12_LINE_REFERENCE 18 18 HDMI_GENERIC12_UPDATE_LOCK_DISABLE 19 19 HDMI_GENERIC13_SEND 20 20 HDMI_GENERIC13_CONT 21 21 HDMI_GENERIC13_LINE_REFERENCE 22 22 HDMI_GENERIC13_UPDATE_LOCK_DISABLE 23 23 HDMI_GENERIC14_SEND 24 24 HDMI_GENERIC14_CONT 25 25 HDMI_GENERIC14_LINE_REFERENCE 26 26 HDMI_GENERIC14_UPDATE_LOCK_DISABLE 27 27 regDIG3_HDMI_GENERIC_PACKET_CONTROL5 0 0x239c 30 0 2 HDMI_GENERIC0_IMMEDIATE_SEND 0 0 HDMI_GENERIC0_IMMEDIATE_SEND_PENDING 1 1 HDMI_GENERIC1_IMMEDIATE_SEND 2 2 HDMI_GENERIC1_IMMEDIATE_SEND_PENDING 3 3 HDMI_GENERIC2_IMMEDIATE_SEND 4 4 HDMI_GENERIC2_IMMEDIATE_SEND_PENDING 5 5 HDMI_GENERIC3_IMMEDIATE_SEND 6 6 HDMI_GENERIC3_IMMEDIATE_SEND_PENDING 7 7 HDMI_GENERIC4_IMMEDIATE_SEND 8 8 HDMI_GENERIC4_IMMEDIATE_SEND_PENDING 9 9 HDMI_GENERIC5_IMMEDIATE_SEND 10 10 HDMI_GENERIC5_IMMEDIATE_SEND_PENDING 11 11 HDMI_GENERIC6_IMMEDIATE_SEND 12 12 HDMI_GENERIC6_IMMEDIATE_SEND_PENDING 13 13 HDMI_GENERIC7_IMMEDIATE_SEND 14 14 HDMI_GENERIC7_IMMEDIATE_SEND_PENDING 15 15 HDMI_GENERIC8_IMMEDIATE_SEND 16 16 HDMI_GENERIC8_IMMEDIATE_SEND_PENDING 17 17 HDMI_GENERIC9_IMMEDIATE_SEND 18 18 HDMI_GENERIC9_IMMEDIATE_SEND_PENDING 19 19 HDMI_GENERIC10_IMMEDIATE_SEND 20 20 HDMI_GENERIC10_IMMEDIATE_SEND_PENDING 21 21 HDMI_GENERIC11_IMMEDIATE_SEND 22 22 HDMI_GENERIC11_IMMEDIATE_SEND_PENDING 23 23 HDMI_GENERIC12_IMMEDIATE_SEND 24 24 HDMI_GENERIC12_IMMEDIATE_SEND_PENDING 25 25 HDMI_GENERIC13_IMMEDIATE_SEND 26 26 HDMI_GENERIC13_IMMEDIATE_SEND_PENDING 27 27 HDMI_GENERIC14_IMMEDIATE_SEND 28 28 HDMI_GENERIC14_IMMEDIATE_SEND_PENDING 29 29 regDIG3_HDMI_GC 0 0x239d 5 0 2 HDMI_GC_AVMUTE 0 0 HDMI_GC_AVMUTE_CONT 2 2 HDMI_DEFAULT_PHASE 4 4 HDMI_PACKING_PHASE 8 11 HDMI_PACKING_PHASE_OVERRIDE 12 12 regDIG3_HDMI_GENERIC_PACKET_CONTROL1 0 0x239e 2 0 2 HDMI_GENERIC0_LINE 0 15 HDMI_GENERIC1_LINE 16 31 regDIG3_HDMI_GENERIC_PACKET_CONTROL2 0 0x239f 2 0 2 HDMI_GENERIC2_LINE 0 15 HDMI_GENERIC3_LINE 16 31 regDIG3_HDMI_GENERIC_PACKET_CONTROL3 0 0x23a0 2 0 2 HDMI_GENERIC4_LINE 0 15 HDMI_GENERIC5_LINE 16 31 regDIG3_HDMI_GENERIC_PACKET_CONTROL4 0 0x23a1 2 0 2 HDMI_GENERIC6_LINE 0 15 HDMI_GENERIC7_LINE 16 31 regDIG3_HDMI_GENERIC_PACKET_CONTROL7 0 0x23a2 2 0 2 HDMI_GENERIC8_LINE 0 15 HDMI_GENERIC9_LINE 16 31 regDIG3_HDMI_GENERIC_PACKET_CONTROL8 0 0x23a3 2 0 2 HDMI_GENERIC10_LINE 0 15 HDMI_GENERIC11_LINE 16 31 regDIG3_HDMI_GENERIC_PACKET_CONTROL9 0 0x23a4 2 0 2 HDMI_GENERIC12_LINE 0 15 HDMI_GENERIC13_LINE 16 31 regDIG3_HDMI_GENERIC_PACKET_CONTROL10 0 0x23a5 16 0 2 HDMI_GENERIC14_LINE 0 15 HDMI_GENERIC0_EN_DB_PENDING 16 16 HDMI_GENERIC1_EN_DB_PENDING 17 17 HDMI_GENERIC2_EN_DB_PENDING 18 18 HDMI_GENERIC3_EN_DB_PENDING 19 19 HDMI_GENERIC4_EN_DB_PENDING 20 20 HDMI_GENERIC5_EN_DB_PENDING 21 21 HDMI_GENERIC6_EN_DB_PENDING 22 22 HDMI_GENERIC7_EN_DB_PENDING 23 23 HDMI_GENERIC8_EN_DB_PENDING 24 24 HDMI_GENERIC9_EN_DB_PENDING 25 25 HDMI_GENERIC10_EN_DB_PENDING 26 26 HDMI_GENERIC11_EN_DB_PENDING 27 27 HDMI_GENERIC12_EN_DB_PENDING 28 28 HDMI_GENERIC13_EN_DB_PENDING 29 29 HDMI_GENERIC14_EN_DB_PENDING 30 30 regDIG3_HDMI_DB_CONTROL 0 0x23a6 8 0 2 HDMI_DB_PENDING 0 0 HDMI_DB_TAKEN 4 4 HDMI_DB_TAKEN_CLR 5 5 HDMI_DB_LOCK 8 8 HDMI_DB_DISABLE 12 12 VUPDATE_DB_PENDING 15 15 VUPDATE_DB_TAKEN 16 16 VUPDATE_DB_TAKEN_CLR 17 17 regDIG3_HDMI_ACR_32_0 0 0x23a7 1 0 2 HDMI_ACR_CTS_32 12 31 regDIG3_HDMI_ACR_32_1 0 0x23a8 1 0 2 HDMI_ACR_N_32 0 19 regDIG3_HDMI_ACR_44_0 0 0x23a9 1 0 2 HDMI_ACR_CTS_44 12 31 regDIG3_HDMI_ACR_44_1 0 0x23aa 1 0 2 HDMI_ACR_N_44 0 19 regDIG3_HDMI_ACR_48_0 0 0x23ab 1 0 2 HDMI_ACR_CTS_48 12 31 regDIG3_HDMI_ACR_48_1 0 0x23ac 1 0 2 HDMI_ACR_N_48 0 19 regDIG3_HDMI_ACR_STATUS_0 0 0x23ad 1 0 2 HDMI_ACR_CTS 12 31 regDIG3_HDMI_ACR_STATUS_1 0 0x23ae 1 0 2 HDMI_ACR_N 0 19 regDIG3_AFMT_CNTL 0 0x23af 2 0 2 AFMT_AUDIO_CLOCK_EN 0 0 AFMT_AUDIO_CLOCK_ON 8 8 regDIG3_DIG_BE_CNTL 0 0x23b0 6 0 2 DIG_DUAL_LINK_ENABLE 0 0 DIG_SWAP 1 1 DIG_RB_SWITCH_EN 2 2 DIG_FE_SOURCE_SELECT 8 14 DIG_MODE 16 18 DIG_HPD_SELECT 28 30 regDIG3_DIG_BE_EN_CNTL 0 0x23b1 2 0 2 DIG_ENABLE 0 0 DIG_SYMCLK_BE_ON 8 8 regDIG3_TMDS_CNTL 0 0x23d7 1 0 2 TMDS_SYNC_PHASE 0 0 regDIG3_TMDS_CONTROL_CHAR 0 0x23d8 4 0 2 TMDS_CONTROL_CHAR0_OUT_EN 0 0 TMDS_CONTROL_CHAR1_OUT_EN 1 1 TMDS_CONTROL_CHAR2_OUT_EN 2 2 TMDS_CONTROL_CHAR3_OUT_EN 3 3 regDIG3_TMDS_CONTROL0_FEEDBACK 0 0x23d9 2 0 2 TMDS_CONTROL0_FEEDBACK_SELECT 0 1 TMDS_CONTROL0_FEEDBACK_DELAY 8 9 regDIG3_TMDS_STEREOSYNC_CTL_SEL 0 0x23da 1 0 2 TMDS_STEREOSYNC_CTL_SEL 0 1 regDIG3_TMDS_SYNC_CHAR_PATTERN_0_1 0 0x23db 2 0 2 TMDS_SYNC_CHAR_PATTERN0 0 9 TMDS_SYNC_CHAR_PATTERN1 16 25 regDIG3_TMDS_SYNC_CHAR_PATTERN_2_3 0 0x23dc 2 0 2 TMDS_SYNC_CHAR_PATTERN2 0 9 TMDS_SYNC_CHAR_PATTERN3 16 25 regDIG3_TMDS_CTL_BITS 0 0x23de 4 0 2 TMDS_CTL0 0 0 TMDS_CTL1 8 8 TMDS_CTL2 16 16 TMDS_CTL3 24 24 regDIG3_TMDS_DCBALANCER_CONTROL 0 0x23df 5 0 2 TMDS_DCBALANCER_EN 0 0 TMDS_SYNC_DCBAL_EN 4 6 TMDS_DCBALANCER_TEST_EN 8 8 TMDS_DCBALANCER_TEST_IN 16 19 TMDS_DCBALANCER_FORCE 24 24 regDIG3_TMDS_SYNC_DCBALANCE_CHAR 0 0x23e0 2 0 2 TMDS_SYNC_DCBAL_CHAR01 0 9 TMDS_SYNC_DCBAL_CHAR11 16 25 regDIG3_TMDS_CTL0_1_GEN_CNTL 0 0x23e1 15 0 2 TMDS_CTL0_DATA_SEL 0 3 TMDS_CTL0_DATA_DELAY 4 6 TMDS_CTL0_DATA_INVERT 7 7 TMDS_CTL0_DATA_MODULATION 8 9 TMDS_CTL0_USE_FEEDBACK_PATH 10 10 TMDS_CTL0_FB_SYNC_CONT 11 11 TMDS_CTL0_PATTERN_OUT_EN 12 12 TMDS_CTL1_DATA_SEL 16 19 TMDS_CTL1_DATA_DELAY 20 22 TMDS_CTL1_DATA_INVERT 23 23 TMDS_CTL1_DATA_MODULATION 24 25 TMDS_CTL1_USE_FEEDBACK_PATH 26 26 TMDS_CTL1_FB_SYNC_CONT 27 27 TMDS_CTL1_PATTERN_OUT_EN 28 28 TMDS_2BIT_COUNTER_EN 31 31 regDIG3_TMDS_CTL2_3_GEN_CNTL 0 0x23e2 14 0 2 TMDS_CTL2_DATA_SEL 0 3 TMDS_CTL2_DATA_DELAY 4 6 TMDS_CTL2_DATA_INVERT 7 7 TMDS_CTL2_DATA_MODULATION 8 9 TMDS_CTL2_USE_FEEDBACK_PATH 10 10 TMDS_CTL2_FB_SYNC_CONT 11 11 TMDS_CTL2_PATTERN_OUT_EN 12 12 TMDS_CTL3_DATA_SEL 16 19 TMDS_CTL3_DATA_DELAY 20 22 TMDS_CTL3_DATA_INVERT 23 23 TMDS_CTL3_DATA_MODULATION 24 25 TMDS_CTL3_USE_FEEDBACK_PATH 26 26 TMDS_CTL3_FB_SYNC_CONT 27 27 TMDS_CTL3_PATTERN_OUT_EN 28 28 regDIG3_DIG_VERSION 0 0x23e4 1 0 2 DIG_TYPE 0 0 regDIG3_FORCE_DIG_DISABLE 0 0x23e5 1 0 2 FORCE_DIG_DISABLE 0 0 regDP4_DP_LINK_CNTL 0 0x2508 3 0 2 DP_LINK_TRAINING_COMPLETE 4 4 DP_LINK_STATUS 8 8 DP_EMBEDDED_PANEL_MODE 17 17 regDP4_DP_PIXEL_FORMAT 0 0x2509 3 0 2 DP_PIXEL_ENCODING 0 2 DP_COMPONENT_DEPTH 24 26 DP_PIXEL_COMBINE 28 29 regDP4_DP_MSA_COLORIMETRY 0 0x250a 1 0 2 DP_MSA_MISC0 24 31 regDP4_DP_CONFIG 0 0x250b 1 0 2 DP_UDI_LANES 0 1 regDP4_DP_VID_STREAM_CNTL 0 0x250c 4 0 2 DP_VID_STREAM_ENABLE 0 0 DP_VID_STREAM_DIS_DEFER 8 9 DP_VID_STREAM_STATUS 16 16 DP_VID_STREAM_CHANGE_KEEPOUT 20 20 regDP4_DP_STEER_FIFO 0 0x250d 7 0 2 DP_STEER_FIFO_RESET 0 0 DP_STEER_OVERFLOW_FLAG 4 4 DP_STEER_OVERFLOW_INT 5 5 DP_STEER_OVERFLOW_ACK 6 6 DP_STEER_OVERFLOW_MASK 7 7 DP_TU_OVERFLOW_FLAG 8 8 DP_TU_OVERFLOW_ACK 12 12 regDP4_DP_MSA_MISC 0 0x250e 4 0 2 DP_MSA_MISC1 0 7 DP_MSA_MISC2 8 15 DP_MSA_MISC3 16 23 DP_MSA_MISC4 24 31 regDP4_DP_DPHY_INTERNAL_CTRL 0 0x250f 2 0 2 DPHY_ALT_SCRAMBLER_RESET_EN 0 0 DPHY_ALT_SCRAMBLER_RESET_SEL 4 4 regDP4_DP_VID_TIMING 0 0x2510 5 0 2 DP_VID_M_N_DOUBLE_BUFFER_MODE 4 4 DP_VID_M_N_GEN_EN 8 8 DP_VID_N_MUL 10 11 DP_VID_M_DIV 12 13 DP_VID_N_DIV 24 31 regDP4_DP_VID_N 0 0x2511 1 0 2 DP_VID_N 0 23 regDP4_DP_VID_M 0 0x2512 1 0 2 DP_VID_M 0 23 regDP4_DP_LINK_FRAMING_CNTL 0 0x2513 3 0 2 DP_IDLE_BS_INTERVAL 0 17 DP_VBID_DISABLE 24 24 DP_VID_ENHANCED_FRAME_MODE 28 28 regDP4_DP_HBR2_EYE_PATTERN 0 0x2514 1 0 2 DP_HBR2_EYE_PATTERN_ENABLE 0 0 regDP4_DP_VID_MSA_VBID 0 0x2515 2 0 2 DP_VID_MSA_LOCATION 0 11 DP_VID_VBID_FIELD_POL 24 24 regDP4_DP_VID_INTERRUPT_CNTL 0 0x2516 3 0 2 DP_VID_STREAM_DISABLE_INT 0 0 DP_VID_STREAM_DISABLE_ACK 1 1 DP_VID_STREAM_DISABLE_MASK 2 2 regDP4_DP_DPHY_CNTL 0 0x2517 10 0 2 DPHY_ATEST_SEL_LANE0 0 0 DPHY_ATEST_SEL_LANE1 1 1 DPHY_ATEST_SEL_LANE2 2 2 DPHY_ATEST_SEL_LANE3 3 3 DPHY_FEC_EN 4 4 DPHY_FEC_READY_SHADOW 5 5 DPHY_FEC_ACTIVE_STATUS 6 6 DPHY_SCRAMBLER_SEL 8 8 DPHY_BYPASS 16 16 DPHY_SKEW_BYPASS 24 24 regDP4_DP_DPHY_TRAINING_PATTERN_SEL 0 0x2518 1 0 2 DPHY_TRAINING_PATTERN_SEL 0 1 regDP4_DP_DPHY_SYM0 0 0x2519 3 0 2 DPHY_SYM1 0 9 DPHY_SYM2 10 19 DPHY_SYM3 20 29 regDP4_DP_DPHY_SYM1 0 0x251a 3 0 2 DPHY_SYM4 0 9 DPHY_SYM5 10 19 DPHY_SYM6 20 29 regDP4_DP_DPHY_SYM2 0 0x251b 2 0 2 DPHY_SYM7 0 9 DPHY_SYM8 10 19 regDP4_DP_DPHY_8B10B_CNTL 0 0x251c 3 0 2 DPHY_8B10B_RESET 8 8 DPHY_8B10B_EXT_DISP 16 16 DPHY_8B10B_CUR_DISP 24 24 regDP4_DP_DPHY_PRBS_CNTL 0 0x251d 3 0 2 DPHY_PRBS_EN 0 0 DPHY_PRBS_SEL 4 5 DPHY_PRBS_SEED 8 30 regDP4_DP_DPHY_SCRAM_CNTL 0 0x251e 4 0 2 DPHY_SCRAMBLER_DIS 0 0 DPHY_SCRAMBLER_ADVANCE 4 4 DPHY_SCRAMBLER_BS_COUNT 8 17 DPHY_SCRAMBLER_KCODE 24 24 regDP4_DP_DPHY_CRC_EN 0 0x251f 3 0 2 DPHY_CRC_EN 0 0 DPHY_CRC_CONT_EN 4 4 DPHY_CRC_RESULT_VALID 8 8 regDP4_DP_DPHY_CRC_CNTL 0 0x2520 3 0 2 DPHY_CRC_FIELD 0 0 DPHY_CRC_SEL 4 5 DPHY_CRC_MASK 16 23 regDP4_DP_DPHY_CRC_RESULT 0 0x2521 4 0 2 DPHY_CRC_RESULT 0 7 DPHY_CRC_RESULT1 8 15 DPHY_CRC_RESULT2 16 23 DPHY_CRC_RESULT3 24 31 regDP4_DP_DPHY_CRC_MST_CNTL 0 0x2522 2 0 2 DPHY_CRC_MST_FIRST_SLOT 0 5 DPHY_CRC_MST_LAST_SLOT 8 13 regDP4_DP_DPHY_CRC_MST_STATUS 0 0x2523 3 0 2 DPHY_CRC_MST_PHASE_LOCK 0 0 DPHY_CRC_MST_PHASE_ERROR 8 8 DPHY_CRC_MST_PHASE_ERROR_ACK 16 16 regDP4_DP_DPHY_FAST_TRAINING 0 0x2524 6 0 2 DPHY_RX_FAST_TRAINING_CAPABLE 0 0 DPHY_SW_FAST_TRAINING_START 1 1 DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN 2 2 DPHY_STREAM_RESET_DURING_FAST_TRAINING 4 4 DPHY_FAST_TRAINING_TP1_TIME 8 19 DPHY_FAST_TRAINING_TP2_TIME 20 31 regDP4_DP_DPHY_FAST_TRAINING_STATUS 0 0x2525 4 0 2 DPHY_FAST_TRAINING_STATE 0 2 DPHY_FAST_TRAINING_COMPLETE_OCCURRED 4 4 DPHY_FAST_TRAINING_COMPLETE_MASK 8 8 DPHY_FAST_TRAINING_COMPLETE_ACK 12 12 regDP4_DP_SEC_CNTL 0 0x252b 14 0 2 DP_SEC_STREAM_ENABLE 0 0 DP_SEC_ASP_ENABLE 4 4 DP_SEC_ATP_ENABLE 8 8 DP_SEC_AIP_ENABLE 12 12 DP_SEC_ACM_ENABLE 16 16 DP_SEC_GSP0_ENABLE 20 20 DP_SEC_GSP1_ENABLE 21 21 DP_SEC_GSP2_ENABLE 22 22 DP_SEC_GSP3_ENABLE 23 23 DP_SEC_GSP4_ENABLE 24 24 DP_SEC_GSP5_ENABLE 25 25 DP_SEC_GSP6_ENABLE 26 26 DP_SEC_GSP7_ENABLE 27 27 DP_SEC_MPG_ENABLE 28 28 regDP4_DP_SEC_CNTL1 0 0x252c 15 0 2 DP_SEC_ISRC_ENABLE 0 0 DP_SEC_GSP0_LINE_REFERENCE 1 1 DP_SEC_GSP0_PRIORITY 4 4 DP_SEC_GSP0_SEND 5 5 DP_SEC_GSP0_SEND_PENDING 6 6 DP_SEC_GSP0_SEND_DEADLINE_MISSED 7 7 DP_SEC_GSP0_SEND_ANY_LINE 8 8 DP_SEC_GSP1_LINE_REFERENCE 9 9 DP_SEC_GSP2_LINE_REFERENCE 10 10 DP_SEC_GSP3_LINE_REFERENCE 11 11 DP_SEC_GSP4_LINE_REFERENCE 12 12 DP_SEC_GSP5_LINE_REFERENCE 13 13 DP_SEC_GSP6_LINE_REFERENCE 14 14 DP_SEC_GSP7_LINE_REFERENCE 15 15 DP_SEC_GSP0_LINE_NUM 16 31 regDP4_DP_SEC_FRAMING1 0 0x252d 2 0 2 DP_SEC_FRAME_START_LOCATION 0 11 DP_SEC_VBLANK_TRANSMIT_WIDTH 16 31 regDP4_DP_SEC_FRAMING2 0 0x252e 2 0 2 DP_SEC_START_POSITION 0 15 DP_SEC_HBLANK_TRANSMIT_WIDTH 16 31 regDP4_DP_SEC_FRAMING3 0 0x252f 2 0 2 DP_SEC_IDLE_FRAME_SIZE 0 13 DP_SEC_IDLE_TRANSMIT_WIDTH 16 31 regDP4_DP_SEC_FRAMING4 0 0x2530 5 0 2 DP_SST_SDP_SPLITTING 0 0 DP_SEC_COLLISION_STATUS 20 20 DP_SEC_COLLISION_ACK 24 24 DP_SEC_AUDIO_MUTE 28 28 DP_SEC_AUDIO_MUTE_STATUS 29 29 regDP4_DP_SEC_AUD_N 0 0x2531 1 0 2 DP_SEC_AUD_N 0 23 regDP4_DP_SEC_AUD_N_READBACK 0 0x2532 1 0 2 DP_SEC_AUD_N_READBACK 0 23 regDP4_DP_SEC_AUD_M 0 0x2533 1 0 2 DP_SEC_AUD_M 0 23 regDP4_DP_SEC_AUD_M_READBACK 0 0x2534 1 0 2 DP_SEC_AUD_M_READBACK 0 23 regDP4_DP_SEC_TIMESTAMP 0 0x2535 1 0 2 DP_SEC_TIMESTAMP_MODE 0 0 regDP4_DP_SEC_PACKET_CNTL 0 0x2536 4 0 2 DP_SEC_ASP_CODING_TYPE 1 3 DP_SEC_ASP_PRIORITY 4 4 DP_SEC_VERSION 8 13 DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE 16 16 regDP4_DP_MSE_RATE_CNTL 0 0x2537 2 0 2 DP_MSE_RATE_Y 0 25 DP_MSE_RATE_X 26 31 regDP4_DP_MSE_RATE_UPDATE 0 0x2539 1 0 2 DP_MSE_RATE_UPDATE_PENDING 0 0 regDP4_DP_MSE_SAT0 0 0x253a 8 0 2 DP_MSE_SAT_SRC0 0 2 DP_MSE_SAT_ENCRYPT0 4 4 DP_MSE_SAT_ENCRYPTION_TYPE0 5 5 DP_MSE_SAT_SLOT_COUNT0 8 13 DP_MSE_SAT_SRC1 16 18 DP_MSE_SAT_ENCRYPT1 20 20 DP_MSE_SAT_ENCRYPTION_TYPE1 21 21 DP_MSE_SAT_SLOT_COUNT1 24 29 regDP4_DP_MSE_SAT1 0 0x253b 8 0 2 DP_MSE_SAT_SRC2 0 2 DP_MSE_SAT_ENCRYPT2 4 4 DP_MSE_SAT_ENCRYPTION_TYPE2 5 5 DP_MSE_SAT_SLOT_COUNT2 8 13 DP_MSE_SAT_SRC3 16 18 DP_MSE_SAT_ENCRYPT3 20 20 DP_MSE_SAT_ENCRYPTION_TYPE3 21 21 DP_MSE_SAT_SLOT_COUNT3 24 29 regDP4_DP_MSE_SAT2 0 0x253c 8 0 2 DP_MSE_SAT_SRC4 0 2 DP_MSE_SAT_ENCRYPT4 4 4 DP_MSE_SAT_ENCRYPTION_TYPE4 5 5 DP_MSE_SAT_SLOT_COUNT4 8 13 DP_MSE_SAT_SRC5 16 18 DP_MSE_SAT_ENCRYPT5 20 20 DP_MSE_SAT_ENCRYPTION_TYPE5 21 21 DP_MSE_SAT_SLOT_COUNT5 24 29 regDP4_DP_MSE_SAT_UPDATE 0 0x253d 2 0 2 DP_MSE_SAT_UPDATE 0 1 DP_MSE_16_MTP_KEEPOUT 8 8 regDP4_DP_MSE_LINK_TIMING 0 0x253e 2 0 2 DP_MSE_LINK_FRAME 0 9 DP_MSE_LINK_LINE 16 17 regDP4_DP_MSE_MISC_CNTL 0 0x253f 3 0 2 DP_MSE_BLANK_CODE 0 0 DP_MSE_TIMESTAMP_MODE 4 4 DP_MSE_ZERO_ENCODER 8 8 regDP4_DP_DPHY_BS_SR_SWAP_CNTL 0 0x2544 3 0 2 DPHY_LOAD_BS_COUNT 0 9 DPHY_BS_SR_SWAP_DONE 15 15 DPHY_LOAD_BS_COUNT_START 16 16 regDP4_DP_DPHY_HBR2_PATTERN_CONTROL 0 0x2545 1 0 2 DP_DPHY_HBR2_PATTERN_CONTROL 0 2 regDP4_DP_MSE_SAT0_STATUS 0 0x2547 8 0 2 DP_MSE_SAT_SRC0_STATUS 0 2 DP_MSE_SAT_ENCRYPT0_STATUS 4 4 DP_MSE_SAT_ENCRYPTION_TYPE0_STATUS 5 5 DP_MSE_SAT_SLOT_COUNT0_STATUS 8 13 DP_MSE_SAT_SRC1_STATUS 16 18 DP_MSE_SAT_ENCRYPT1_STATUS 20 20 DP_MSE_SAT_ENCRYPTION_TYPE1_STATUS 21 21 DP_MSE_SAT_SLOT_COUNT1_STATUS 24 29 regDP4_DP_MSE_SAT1_STATUS 0 0x2548 8 0 2 DP_MSE_SAT_SRC2_STATUS 0 2 DP_MSE_SAT_ENCRYPT2_STATUS 4 4 DP_MSE_SAT_ENCRYPTION_TYPE2_STATUS 5 5 DP_MSE_SAT_SLOT_COUNT2_STATUS 8 13 DP_MSE_SAT_SRC3_STATUS 16 18 DP_MSE_SAT_ENCRYPT3_STATUS 20 20 DP_MSE_SAT_ENCRYPTION_TYPE3_STATUS 21 21 DP_MSE_SAT_SLOT_COUNT3_STATUS 24 29 regDP4_DP_MSE_SAT2_STATUS 0 0x2549 8 0 2 DP_MSE_SAT_SRC4_STATUS 0 2 DP_MSE_SAT_ENCRYPT4_STATUS 4 4 DP_MSE_SAT_ENCRYPTION_TYPE4_STATUS 5 5 DP_MSE_SAT_SLOT_COUNT4_STATUS 8 13 DP_MSE_SAT_SRC5_STATUS 16 18 DP_MSE_SAT_ENCRYPT5_STATUS 20 20 DP_MSE_SAT_ENCRYPTION_TYPE5_STATUS 21 21 DP_MSE_SAT_SLOT_COUNT5_STATUS 24 29 regDP4_DP_MSA_TIMING_PARAM1 0 0x254c 2 0 2 DP_MSA_VTOTAL 0 15 DP_MSA_HTOTAL 16 31 regDP4_DP_MSA_TIMING_PARAM2 0 0x254d 2 0 2 DP_MSA_VSTART 0 15 DP_MSA_HSTART 16 31 regDP4_DP_MSA_TIMING_PARAM3 0 0x254e 4 0 2 DP_MSA_VSYNCWIDTH 0 14 DP_MSA_VSYNCPOLARITY 15 15 DP_MSA_HSYNCWIDTH 16 30 DP_MSA_HSYNCPOLARITY 31 31 regDP4_DP_MSA_TIMING_PARAM4 0 0x254f 2 0 2 DP_MSA_VHEIGHT 0 15 DP_MSA_HWIDTH 16 31 regDP4_DP_MSO_CNTL 0 0x2550 8 0 2 DP_MSO_NUM_OF_SSTLINK 0 1 DP_MSO_SEC_STREAM_ENABLE 4 7 DP_MSO_SEC_ASP_ENABLE 8 11 DP_MSO_SEC_ATP_ENABLE 12 15 DP_MSO_SEC_AIP_ENABLE 16 19 DP_MSO_SEC_ACM_ENABLE 20 23 DP_MSO_SEC_GSP0_ENABLE 24 27 DP_MSO_SEC_GSP1_ENABLE 28 31 regDP4_DP_MSO_CNTL1 0 0x2551 8 0 2 DP_MSO_SEC_GSP2_ENABLE 0 3 DP_MSO_SEC_GSP3_ENABLE 4 7 DP_MSO_SEC_GSP4_ENABLE 8 11 DP_MSO_SEC_GSP5_ENABLE 12 15 DP_MSO_SEC_GSP6_ENABLE 16 19 DP_MSO_SEC_GSP7_ENABLE 20 23 DP_MSO_SEC_MPG_ENABLE 24 27 DP_MSO_SEC_ISRC_ENABLE 28 31 regDP4_DP_DSC_CNTL 0 0x2552 2 0 2 DP_DSC_MODE 0 1 DP_DSC_SLICE_WIDTH 16 28 regDP4_DP_SEC_CNTL2 0 0x2553 29 0 2 DP_SEC_GSP1_SEND 0 0 DP_SEC_GSP1_SEND_PENDING 1 1 DP_SEC_GSP1_SEND_DEADLINE_MISSED 2 2 DP_SEC_GSP1_SEND_ANY_LINE 3 3 DP_SEC_GSP2_SEND 4 4 DP_SEC_GSP2_SEND_PENDING 5 5 DP_SEC_GSP2_SEND_DEADLINE_MISSED 6 6 DP_SEC_GSP2_SEND_ANY_LINE 7 7 DP_SEC_GSP3_SEND 8 8 DP_SEC_GSP3_SEND_PENDING 9 9 DP_SEC_GSP3_SEND_DEADLINE_MISSED 10 10 DP_SEC_GSP3_SEND_ANY_LINE 11 11 DP_SEC_GSP4_SEND 12 12 DP_SEC_GSP4_SEND_PENDING 13 13 DP_SEC_GSP4_SEND_DEADLINE_MISSED 14 14 DP_SEC_GSP4_SEND_ANY_LINE 15 15 DP_SEC_GSP5_SEND 16 16 DP_SEC_GSP5_SEND_PENDING 17 17 DP_SEC_GSP5_SEND_DEADLINE_MISSED 18 18 DP_SEC_GSP5_SEND_ANY_LINE 19 19 DP_SEC_GSP6_SEND 20 20 DP_SEC_GSP6_SEND_PENDING 21 21 DP_SEC_GSP6_SEND_DEADLINE_MISSED 22 22 DP_SEC_GSP6_SEND_ANY_LINE 23 23 DP_SEC_GSP7_SEND 24 24 DP_SEC_GSP7_SEND_PENDING 25 25 DP_SEC_GSP7_SEND_DEADLINE_MISSED 26 26 DP_SEC_GSP7_SEND_ANY_LINE 27 27 DP_SEC_GSP11_PPS 28 28 regDP4_DP_SEC_CNTL3 0 0x2554 2 0 2 DP_SEC_GSP1_LINE_NUM 0 15 DP_SEC_GSP2_LINE_NUM 16 31 regDP4_DP_SEC_CNTL4 0 0x2555 2 0 2 DP_SEC_GSP3_LINE_NUM 0 15 DP_SEC_GSP4_LINE_NUM 16 31 regDP4_DP_SEC_CNTL5 0 0x2556 2 0 2 DP_SEC_GSP5_LINE_NUM 0 15 DP_SEC_GSP6_LINE_NUM 16 31 regDP4_DP_SEC_CNTL6 0 0x2557 13 0 2 DP_SEC_GSP7_LINE_NUM 0 15 DP_SEC_GSP0_EN_DB_DISABLE 16 16 DP_SEC_GSP1_EN_DB_DISABLE 17 17 DP_SEC_GSP2_EN_DB_DISABLE 18 18 DP_SEC_GSP3_EN_DB_DISABLE 19 19 DP_SEC_GSP4_EN_DB_DISABLE 20 20 DP_SEC_GSP5_EN_DB_DISABLE 21 21 DP_SEC_GSP6_EN_DB_DISABLE 22 22 DP_SEC_GSP7_EN_DB_DISABLE 23 23 DP_SEC_GSP8_EN_DB_DISABLE 24 24 DP_SEC_GSP9_EN_DB_DISABLE 25 25 DP_SEC_GSP10_EN_DB_DISABLE 26 26 DP_SEC_GSP11_EN_DB_DISABLE 27 27 regDP4_DP_SEC_CNTL7 0 0x2558 16 0 2 DP_SEC_GSP0_SEND_ACTIVE 0 0 DP_SEC_GSP0_SEND_IN_IDLE 1 1 DP_SEC_GSP1_SEND_ACTIVE 4 4 DP_SEC_GSP1_SEND_IN_IDLE 5 5 DP_SEC_GSP2_SEND_ACTIVE 8 8 DP_SEC_GSP2_SEND_IN_IDLE 9 9 DP_SEC_GSP3_SEND_ACTIVE 12 12 DP_SEC_GSP3_SEND_IN_IDLE 13 13 DP_SEC_GSP4_SEND_ACTIVE 16 16 DP_SEC_GSP4_SEND_IN_IDLE 17 17 DP_SEC_GSP5_SEND_ACTIVE 20 20 DP_SEC_GSP5_SEND_IN_IDLE 21 21 DP_SEC_GSP6_SEND_ACTIVE 24 24 DP_SEC_GSP6_SEND_IN_IDLE 25 25 DP_SEC_GSP7_SEND_ACTIVE 28 28 DP_SEC_GSP7_SEND_IN_IDLE 29 29 regDP4_DP_DB_CNTL 0 0x2559 8 0 2 DP_DB_PENDING 0 0 DP_DB_TAKEN 4 4 DP_DB_TAKEN_CLR 5 5 DP_DB_LOCK 8 8 DP_DB_DISABLE 12 12 DP_VUPDATE_DB_PENDING 15 15 DP_VUPDATE_DB_TAKEN 16 16 DP_VUPDATE_DB_TAKEN_CLR 17 17 regDP4_DP_MSA_VBID_MISC 0 0x255a 8 0 2 DP_MSA_MISC1_STEREOSYNC_OVERRIDE 0 1 DP_MSA_MISC1_STEREOSYNC_OVERRIDE_EN 4 4 DP_VBID1_OVERRIDE 8 8 DP_VBID2_OVERRIDE 9 9 DP_VBID1_OVERRIDE_EN 12 12 DP_VBID2_OVERRIDE_EN 13 13 DP_VBID6_LINE_REFERENCE 15 15 DP_VBID6_LINE_NUM 16 31 regDP4_DP_SEC_METADATA_TRANSMISSION 0 0x255b 4 0 2 DP_SEC_METADATA_PACKET_ENABLE 0 0 DP_SEC_METADATA_PACKET_LINE_REFERENCE 1 1 DP_SEC_MSO_METADATA_PACKET_ENABLE 4 7 DP_SEC_METADATA_PACKET_LINE 16 31 regDP4_DP_DSC_BYTES_PER_PIXEL 0 0x255c 1 0 2 DP_DSC_BYTES_PER_PIXEL 0 30 regDP4_DP_ALPM_CNTL 0 0x255d 7 0 2 DP_ML_PHY_SLEEP_SEND 0 0 DP_ML_PHY_SLEEP_PENDING 1 1 DP_ML_PHY_STANDBY_SEND 2 2 DP_ML_PHY_STANDBY_PENDING 3 3 DP_ML_PHY_SLEEP_STANDBY_IMMEDIATE 4 4 DP_LINK_TRAINING_SWITCH_BETWEEN_VIDEO 5 5 DP_ML_PHY_SLEEP_STANDBY_LINE_NUM 16 31 regDP4_DP_GSP8_CNTL 0 0x255e 10 0 2 DP_MSO_SEC_GSP8_ENABLE 0 3 DP_SEC_GSP8_ENABLE 4 4 DP_SEC_GSP8_LINE_REFERENCE 5 5 DP_SEC_GSP8_SEND_IN_IDLE 6 6 DP_SEC_GSP8_SEND 7 7 DP_SEC_GSP8_SEND_ANY_LINE 8 8 DP_SEC_GSP8_SEND_PENDING 12 12 DP_SEC_GSP8_SEND_ACTIVE 13 13 DP_SEC_GSP8_SEND_DEADLINE_MISSED 14 14 DP_SEC_GSP8_LINE_NUM 16 31 regDP4_DP_GSP9_CNTL 0 0x255f 10 0 2 DP_MSO_SEC_GSP9_ENABLE 0 3 DP_SEC_GSP9_ENABLE 4 4 DP_SEC_GSP9_LINE_REFERENCE 5 5 DP_SEC_GSP9_SEND_IN_IDLE 6 6 DP_SEC_GSP9_SEND 7 7 DP_SEC_GSP9_SEND_ANY_LINE 8 8 DP_SEC_GSP9_SEND_PENDING 12 12 DP_SEC_GSP9_SEND_ACTIVE 13 13 DP_SEC_GSP9_SEND_DEADLINE_MISSED 14 14 DP_SEC_GSP9_LINE_NUM 16 31 regDP4_DP_GSP10_CNTL 0 0x2560 10 0 2 DP_MSO_SEC_GSP10_ENABLE 0 3 DP_SEC_GSP10_ENABLE 4 4 DP_SEC_GSP10_LINE_REFERENCE 5 5 DP_SEC_GSP10_SEND_IN_IDLE 6 6 DP_SEC_GSP10_SEND 7 7 DP_SEC_GSP10_SEND_ANY_LINE 8 8 DP_SEC_GSP10_SEND_PENDING 12 12 DP_SEC_GSP10_SEND_ACTIVE 13 13 DP_SEC_GSP10_SEND_DEADLINE_MISSED 14 14 DP_SEC_GSP10_LINE_NUM 16 31 regDP4_DP_GSP11_CNTL 0 0x2561 10 0 2 DP_MSO_SEC_GSP11_ENABLE 0 3 DP_SEC_GSP11_ENABLE 4 4 DP_SEC_GSP11_LINE_REFERENCE 5 5 DP_SEC_GSP11_SEND_IN_IDLE 6 6 DP_SEC_GSP11_SEND 7 7 DP_SEC_GSP11_SEND_ANY_LINE 8 8 DP_SEC_GSP11_SEND_PENDING 12 12 DP_SEC_GSP11_SEND_ACTIVE 13 13 DP_SEC_GSP11_SEND_DEADLINE_MISSED 14 14 DP_SEC_GSP11_LINE_NUM 16 31 regDP4_DP_GSP_EN_DB_STATUS 0 0x2562 12 0 2 DP_SEC_GSP0_EN_DB_PENDING 0 0 DP_SEC_GSP1_EN_DB_PENDING 1 1 DP_SEC_GSP2_EN_DB_PENDING 2 2 DP_SEC_GSP3_EN_DB_PENDING 3 3 DP_SEC_GSP4_EN_DB_PENDING 4 4 DP_SEC_GSP5_EN_DB_PENDING 5 5 DP_SEC_GSP6_EN_DB_PENDING 6 6 DP_SEC_GSP7_EN_DB_PENDING 7 7 DP_SEC_GSP8_EN_DB_PENDING 8 8 DP_SEC_GSP9_EN_DB_PENDING 9 9 DP_SEC_GSP10_EN_DB_PENDING 10 10 DP_SEC_GSP11_EN_DB_PENDING 11 11 regDIG4_DIG_FE_CNTL 0 0x248b 11 0 2 DIG_SOURCE_SELECT 0 2 DIG_STEREOSYNC_SELECT 4 6 DIG_STEREOSYNC_GATE_EN 8 8 DIG_START 10 10 DIG_DIGITAL_BYPASS_SELECT 12 14 DIG_INPUT_PIXEL_SELECT 16 17 DOLBY_VISION_EN 18 18 DOLBY_VISION_METADATA_PACKET_MISSED 19 19 DIG_SYMCLK_FE_ON 24 24 TMDS_PIXEL_ENCODING 28 28 TMDS_COLOR_FORMAT 30 31 regDIG4_DIG_OUTPUT_CRC_CNTL 0 0x248c 3 0 2 DIG_OUTPUT_CRC_EN 0 0 DIG_OUTPUT_CRC_LINK_SEL 4 4 DIG_OUTPUT_CRC_DATA_SEL 8 9 regDIG4_DIG_OUTPUT_CRC_RESULT 0 0x248d 1 0 2 DIG_OUTPUT_CRC_RESULT 0 29 regDIG4_DIG_CLOCK_PATTERN 0 0x248e 1 0 2 DIG_CLOCK_PATTERN 0 9 regDIG4_DIG_TEST_PATTERN 0 0x248f 6 0 2 DIG_TEST_PATTERN_OUT_EN 0 0 DIG_HALF_CLOCK_PATTERN_SEL 1 1 DIG_RANDOM_PATTERN_OUT_EN 4 4 DIG_RANDOM_PATTERN_RESET 5 5 DIG_TEST_PATTERN_EXTERNAL_RESET_EN 6 6 DIG_STATIC_TEST_PATTERN 16 25 regDIG4_DIG_RANDOM_PATTERN_SEED 0 0x2490 2 0 2 DIG_RANDOM_PATTERN_SEED 0 23 DIG_RAN_PAT_DURING_DE_ONLY 24 24 regDIG4_DIG_FIFO_STATUS 0 0x2491 11 0 2 DIG_FIFO_LEVEL_ERROR 0 0 DIG_FIFO_USE_OVERWRITE_LEVEL 1 1 DIG_FIFO_OVERWRITE_LEVEL 2 7 DIG_FIFO_ERROR_ACK 8 8 DIG_FIFO_CAL_AVERAGE_LEVEL 10 15 DIG_FIFO_MAXIMUM_LEVEL 16 20 DIG_FIFO_MINIMUM_LEVEL 22 25 DIG_FIFO_READ_CLOCK_SRC 26 26 DIG_FIFO_CALIBRATED 29 29 DIG_FIFO_FORCE_RECAL_AVERAGE 30 30 DIG_FIFO_FORCE_RECOMP_MINMAX 31 31 regDIG4_HDMI_METADATA_PACKET_CONTROL 0 0x2492 4 0 2 HDMI_METADATA_PACKET_ENABLE 0 0 HDMI_METADATA_PACKET_LINE_REFERENCE 4 4 HDMI_METADATA_PACKET_MISSED 8 8 HDMI_METADATA_PACKET_LINE 16 31 regDIG4_HDMI_CONTROL 0 0x2493 10 0 2 HDMI_KEEPOUT_MODE 0 0 HDMI_DATA_SCRAMBLE_EN 1 1 HDMI_CLOCK_CHANNEL_RATE 2 2 HDMI_NO_EXTRA_NULL_PACKET_FILLED 3 3 HDMI_PACKET_GEN_VERSION 4 4 HDMI_ERROR_ACK 8 8 HDMI_ERROR_MASK 9 9 HDMI_UNSCRAMBLED_CONTROL_LINE_NUM 16 21 HDMI_DEEP_COLOR_ENABLE 24 24 HDMI_DEEP_COLOR_DEPTH 28 29 regDIG4_HDMI_STATUS 0 0x2494 4 0 2 HDMI_ACTIVE_AVMUTE 0 0 HDMI_AUDIO_PACKET_ERROR 16 16 HDMI_VBI_PACKET_ERROR 20 20 HDMI_ERROR_INT 27 27 regDIG4_HDMI_AUDIO_PACKET_CONTROL 0 0x2495 1 0 2 HDMI_AUDIO_DELAY_EN 4 5 regDIG4_HDMI_ACR_PACKET_CONTROL 0 0x2496 7 0 2 HDMI_ACR_SEND 0 0 HDMI_ACR_CONT 1 1 HDMI_ACR_SELECT 4 5 HDMI_ACR_SOURCE 8 8 HDMI_ACR_AUTO_SEND 12 12 HDMI_ACR_N_MULTIPLE 16 18 HDMI_ACR_AUDIO_PRIORITY 31 31 regDIG4_HDMI_VBI_PACKET_CONTROL 0 0x2497 8 0 2 HDMI_NULL_SEND 0 0 HDMI_GC_SEND 4 4 HDMI_GC_CONT 5 5 HDMI_ISRC_SEND 8 8 HDMI_ISRC_CONT 9 9 HDMI_ACP_SEND 12 12 HDMI_ISRC_LINE 16 21 HDMI_ACP_LINE 24 29 regDIG4_HDMI_INFOFRAME_CONTROL0 0 0x2498 4 0 2 HDMI_AUDIO_INFO_SEND 4 4 HDMI_AUDIO_INFO_CONT 5 5 HDMI_MPEG_INFO_SEND 8 8 HDMI_MPEG_INFO_CONT 9 9 regDIG4_HDMI_INFOFRAME_CONTROL1 0 0x2499 2 0 2 HDMI_AUDIO_INFO_LINE 8 13 HDMI_MPEG_INFO_LINE 16 21 regDIG4_HDMI_GENERIC_PACKET_CONTROL0 0 0x249a 32 0 2 HDMI_GENERIC0_SEND 0 0 HDMI_GENERIC0_CONT 1 1 HDMI_GENERIC0_LINE_REFERENCE 2 2 HDMI_GENERIC0_UPDATE_LOCK_DISABLE 3 3 HDMI_GENERIC1_SEND 4 4 HDMI_GENERIC1_CONT 5 5 HDMI_GENERIC1_LINE_REFERENCE 6 6 HDMI_GENERIC1_UPDATE_LOCK_DISABLE 7 7 HDMI_GENERIC2_SEND 8 8 HDMI_GENERIC2_CONT 9 9 HDMI_GENERIC2_LINE_REFERENCE 10 10 HDMI_GENERIC2_UPDATE_LOCK_DISABLE 11 11 HDMI_GENERIC3_SEND 12 12 HDMI_GENERIC3_CONT 13 13 HDMI_GENERIC3_LINE_REFERENCE 14 14 HDMI_GENERIC3_UPDATE_LOCK_DISABLE 15 15 HDMI_GENERIC4_SEND 16 16 HDMI_GENERIC4_CONT 17 17 HDMI_GENERIC4_LINE_REFERENCE 18 18 HDMI_GENERIC4_UPDATE_LOCK_DISABLE 19 19 HDMI_GENERIC5_SEND 20 20 HDMI_GENERIC5_CONT 21 21 HDMI_GENERIC5_LINE_REFERENCE 22 22 HDMI_GENERIC5_UPDATE_LOCK_DISABLE 23 23 HDMI_GENERIC6_SEND 24 24 HDMI_GENERIC6_CONT 25 25 HDMI_GENERIC6_LINE_REFERENCE 26 26 HDMI_GENERIC6_UPDATE_LOCK_DISABLE 27 27 HDMI_GENERIC7_SEND 28 28 HDMI_GENERIC7_CONT 29 29 HDMI_GENERIC7_LINE_REFERENCE 30 30 HDMI_GENERIC7_UPDATE_LOCK_DISABLE 31 31 regDIG4_HDMI_GENERIC_PACKET_CONTROL6 0 0x249b 28 0 2 HDMI_GENERIC8_SEND 0 0 HDMI_GENERIC8_CONT 1 1 HDMI_GENERIC8_LINE_REFERENCE 2 2 HDMI_GENERIC8_UPDATE_LOCK_DISABLE 3 3 HDMI_GENERIC9_SEND 4 4 HDMI_GENERIC9_CONT 5 5 HDMI_GENERIC9_LINE_REFERENCE 6 6 HDMI_GENERIC9_UPDATE_LOCK_DISABLE 7 7 HDMI_GENERIC10_SEND 8 8 HDMI_GENERIC10_CONT 9 9 HDMI_GENERIC10_LINE_REFERENCE 10 10 HDMI_GENERIC10_UPDATE_LOCK_DISABLE 11 11 HDMI_GENERIC11_SEND 12 12 HDMI_GENERIC11_CONT 13 13 HDMI_GENERIC11_LINE_REFERENCE 14 14 HDMI_GENERIC11_UPDATE_LOCK_DISABLE 15 15 HDMI_GENERIC12_SEND 16 16 HDMI_GENERIC12_CONT 17 17 HDMI_GENERIC12_LINE_REFERENCE 18 18 HDMI_GENERIC12_UPDATE_LOCK_DISABLE 19 19 HDMI_GENERIC13_SEND 20 20 HDMI_GENERIC13_CONT 21 21 HDMI_GENERIC13_LINE_REFERENCE 22 22 HDMI_GENERIC13_UPDATE_LOCK_DISABLE 23 23 HDMI_GENERIC14_SEND 24 24 HDMI_GENERIC14_CONT 25 25 HDMI_GENERIC14_LINE_REFERENCE 26 26 HDMI_GENERIC14_UPDATE_LOCK_DISABLE 27 27 regDIG4_HDMI_GENERIC_PACKET_CONTROL5 0 0x249c 30 0 2 HDMI_GENERIC0_IMMEDIATE_SEND 0 0 HDMI_GENERIC0_IMMEDIATE_SEND_PENDING 1 1 HDMI_GENERIC1_IMMEDIATE_SEND 2 2 HDMI_GENERIC1_IMMEDIATE_SEND_PENDING 3 3 HDMI_GENERIC2_IMMEDIATE_SEND 4 4 HDMI_GENERIC2_IMMEDIATE_SEND_PENDING 5 5 HDMI_GENERIC3_IMMEDIATE_SEND 6 6 HDMI_GENERIC3_IMMEDIATE_SEND_PENDING 7 7 HDMI_GENERIC4_IMMEDIATE_SEND 8 8 HDMI_GENERIC4_IMMEDIATE_SEND_PENDING 9 9 HDMI_GENERIC5_IMMEDIATE_SEND 10 10 HDMI_GENERIC5_IMMEDIATE_SEND_PENDING 11 11 HDMI_GENERIC6_IMMEDIATE_SEND 12 12 HDMI_GENERIC6_IMMEDIATE_SEND_PENDING 13 13 HDMI_GENERIC7_IMMEDIATE_SEND 14 14 HDMI_GENERIC7_IMMEDIATE_SEND_PENDING 15 15 HDMI_GENERIC8_IMMEDIATE_SEND 16 16 HDMI_GENERIC8_IMMEDIATE_SEND_PENDING 17 17 HDMI_GENERIC9_IMMEDIATE_SEND 18 18 HDMI_GENERIC9_IMMEDIATE_SEND_PENDING 19 19 HDMI_GENERIC10_IMMEDIATE_SEND 20 20 HDMI_GENERIC10_IMMEDIATE_SEND_PENDING 21 21 HDMI_GENERIC11_IMMEDIATE_SEND 22 22 HDMI_GENERIC11_IMMEDIATE_SEND_PENDING 23 23 HDMI_GENERIC12_IMMEDIATE_SEND 24 24 HDMI_GENERIC12_IMMEDIATE_SEND_PENDING 25 25 HDMI_GENERIC13_IMMEDIATE_SEND 26 26 HDMI_GENERIC13_IMMEDIATE_SEND_PENDING 27 27 HDMI_GENERIC14_IMMEDIATE_SEND 28 28 HDMI_GENERIC14_IMMEDIATE_SEND_PENDING 29 29 regDIG4_HDMI_GC 0 0x249d 5 0 2 HDMI_GC_AVMUTE 0 0 HDMI_GC_AVMUTE_CONT 2 2 HDMI_DEFAULT_PHASE 4 4 HDMI_PACKING_PHASE 8 11 HDMI_PACKING_PHASE_OVERRIDE 12 12 regDIG4_HDMI_GENERIC_PACKET_CONTROL1 0 0x249e 2 0 2 HDMI_GENERIC0_LINE 0 15 HDMI_GENERIC1_LINE 16 31 regDIG4_HDMI_GENERIC_PACKET_CONTROL2 0 0x249f 2 0 2 HDMI_GENERIC2_LINE 0 15 HDMI_GENERIC3_LINE 16 31 regDIG4_HDMI_GENERIC_PACKET_CONTROL3 0 0x24a0 2 0 2 HDMI_GENERIC4_LINE 0 15 HDMI_GENERIC5_LINE 16 31 regDIG4_HDMI_GENERIC_PACKET_CONTROL4 0 0x24a1 2 0 2 HDMI_GENERIC6_LINE 0 15 HDMI_GENERIC7_LINE 16 31 regDIG4_HDMI_GENERIC_PACKET_CONTROL7 0 0x24a2 2 0 2 HDMI_GENERIC8_LINE 0 15 HDMI_GENERIC9_LINE 16 31 regDIG4_HDMI_GENERIC_PACKET_CONTROL8 0 0x24a3 2 0 2 HDMI_GENERIC10_LINE 0 15 HDMI_GENERIC11_LINE 16 31 regDIG4_HDMI_GENERIC_PACKET_CONTROL9 0 0x24a4 2 0 2 HDMI_GENERIC12_LINE 0 15 HDMI_GENERIC13_LINE 16 31 regDIG4_HDMI_GENERIC_PACKET_CONTROL10 0 0x24a5 16 0 2 HDMI_GENERIC14_LINE 0 15 HDMI_GENERIC0_EN_DB_PENDING 16 16 HDMI_GENERIC1_EN_DB_PENDING 17 17 HDMI_GENERIC2_EN_DB_PENDING 18 18 HDMI_GENERIC3_EN_DB_PENDING 19 19 HDMI_GENERIC4_EN_DB_PENDING 20 20 HDMI_GENERIC5_EN_DB_PENDING 21 21 HDMI_GENERIC6_EN_DB_PENDING 22 22 HDMI_GENERIC7_EN_DB_PENDING 23 23 HDMI_GENERIC8_EN_DB_PENDING 24 24 HDMI_GENERIC9_EN_DB_PENDING 25 25 HDMI_GENERIC10_EN_DB_PENDING 26 26 HDMI_GENERIC11_EN_DB_PENDING 27 27 HDMI_GENERIC12_EN_DB_PENDING 28 28 HDMI_GENERIC13_EN_DB_PENDING 29 29 HDMI_GENERIC14_EN_DB_PENDING 30 30 regDIG4_HDMI_DB_CONTROL 0 0x24a6 8 0 2 HDMI_DB_PENDING 0 0 HDMI_DB_TAKEN 4 4 HDMI_DB_TAKEN_CLR 5 5 HDMI_DB_LOCK 8 8 HDMI_DB_DISABLE 12 12 VUPDATE_DB_PENDING 15 15 VUPDATE_DB_TAKEN 16 16 VUPDATE_DB_TAKEN_CLR 17 17 regDIG4_HDMI_ACR_32_0 0 0x24a7 1 0 2 HDMI_ACR_CTS_32 12 31 regDIG4_HDMI_ACR_32_1 0 0x24a8 1 0 2 HDMI_ACR_N_32 0 19 regDIG4_HDMI_ACR_44_0 0 0x24a9 1 0 2 HDMI_ACR_CTS_44 12 31 regDIG4_HDMI_ACR_44_1 0 0x24aa 1 0 2 HDMI_ACR_N_44 0 19 regDIG4_HDMI_ACR_48_0 0 0x24ab 1 0 2 HDMI_ACR_CTS_48 12 31 regDIG4_HDMI_ACR_48_1 0 0x24ac 1 0 2 HDMI_ACR_N_48 0 19 regDIG4_HDMI_ACR_STATUS_0 0 0x24ad 1 0 2 HDMI_ACR_CTS 12 31 regDIG4_HDMI_ACR_STATUS_1 0 0x24ae 1 0 2 HDMI_ACR_N 0 19 regDIG4_AFMT_CNTL 0 0x24af 2 0 2 AFMT_AUDIO_CLOCK_EN 0 0 AFMT_AUDIO_CLOCK_ON 8 8 regDIG4_DIG_BE_CNTL 0 0x24b0 6 0 2 DIG_DUAL_LINK_ENABLE 0 0 DIG_SWAP 1 1 DIG_RB_SWITCH_EN 2 2 DIG_FE_SOURCE_SELECT 8 14 DIG_MODE 16 18 DIG_HPD_SELECT 28 30 regDIG4_DIG_BE_EN_CNTL 0 0x24b1 2 0 2 DIG_ENABLE 0 0 DIG_SYMCLK_BE_ON 8 8 regDIG4_TMDS_CNTL 0 0x24d7 1 0 2 TMDS_SYNC_PHASE 0 0 regDIG4_TMDS_CONTROL_CHAR 0 0x24d8 4 0 2 TMDS_CONTROL_CHAR0_OUT_EN 0 0 TMDS_CONTROL_CHAR1_OUT_EN 1 1 TMDS_CONTROL_CHAR2_OUT_EN 2 2 TMDS_CONTROL_CHAR3_OUT_EN 3 3 regDIG4_TMDS_CONTROL0_FEEDBACK 0 0x24d9 2 0 2 TMDS_CONTROL0_FEEDBACK_SELECT 0 1 TMDS_CONTROL0_FEEDBACK_DELAY 8 9 regDIG4_TMDS_STEREOSYNC_CTL_SEL 0 0x24da 1 0 2 TMDS_STEREOSYNC_CTL_SEL 0 1 regDIG4_TMDS_SYNC_CHAR_PATTERN_0_1 0 0x24db 2 0 2 TMDS_SYNC_CHAR_PATTERN0 0 9 TMDS_SYNC_CHAR_PATTERN1 16 25 regDIG4_TMDS_SYNC_CHAR_PATTERN_2_3 0 0x24dc 2 0 2 TMDS_SYNC_CHAR_PATTERN2 0 9 TMDS_SYNC_CHAR_PATTERN3 16 25 regDIG4_TMDS_CTL_BITS 0 0x24de 4 0 2 TMDS_CTL0 0 0 TMDS_CTL1 8 8 TMDS_CTL2 16 16 TMDS_CTL3 24 24 regDIG4_TMDS_DCBALANCER_CONTROL 0 0x24df 5 0 2 TMDS_DCBALANCER_EN 0 0 TMDS_SYNC_DCBAL_EN 4 6 TMDS_DCBALANCER_TEST_EN 8 8 TMDS_DCBALANCER_TEST_IN 16 19 TMDS_DCBALANCER_FORCE 24 24 regDIG4_TMDS_SYNC_DCBALANCE_CHAR 0 0x24e0 2 0 2 TMDS_SYNC_DCBAL_CHAR01 0 9 TMDS_SYNC_DCBAL_CHAR11 16 25 regDIG4_TMDS_CTL0_1_GEN_CNTL 0 0x24e1 15 0 2 TMDS_CTL0_DATA_SEL 0 3 TMDS_CTL0_DATA_DELAY 4 6 TMDS_CTL0_DATA_INVERT 7 7 TMDS_CTL0_DATA_MODULATION 8 9 TMDS_CTL0_USE_FEEDBACK_PATH 10 10 TMDS_CTL0_FB_SYNC_CONT 11 11 TMDS_CTL0_PATTERN_OUT_EN 12 12 TMDS_CTL1_DATA_SEL 16 19 TMDS_CTL1_DATA_DELAY 20 22 TMDS_CTL1_DATA_INVERT 23 23 TMDS_CTL1_DATA_MODULATION 24 25 TMDS_CTL1_USE_FEEDBACK_PATH 26 26 TMDS_CTL1_FB_SYNC_CONT 27 27 TMDS_CTL1_PATTERN_OUT_EN 28 28 TMDS_2BIT_COUNTER_EN 31 31 regDIG4_TMDS_CTL2_3_GEN_CNTL 0 0x24e2 14 0 2 TMDS_CTL2_DATA_SEL 0 3 TMDS_CTL2_DATA_DELAY 4 6 TMDS_CTL2_DATA_INVERT 7 7 TMDS_CTL2_DATA_MODULATION 8 9 TMDS_CTL2_USE_FEEDBACK_PATH 10 10 TMDS_CTL2_FB_SYNC_CONT 11 11 TMDS_CTL2_PATTERN_OUT_EN 12 12 TMDS_CTL3_DATA_SEL 16 19 TMDS_CTL3_DATA_DELAY 20 22 TMDS_CTL3_DATA_INVERT 23 23 TMDS_CTL3_DATA_MODULATION 24 25 TMDS_CTL3_USE_FEEDBACK_PATH 26 26 TMDS_CTL3_FB_SYNC_CONT 27 27 TMDS_CTL3_PATTERN_OUT_EN 28 28 regDIG4_DIG_VERSION 0 0x24e4 1 0 2 DIG_TYPE 0 0 regDIG4_FORCE_DIG_DISABLE 0 0x24e5 1 0 2 FORCE_DIG_DISABLE 0 0 regAFMT0_AFMT_VBI_PACKET_CONTROL 0 0x2074 3 0 2 AFMT_ACP_SOURCE 13 13 AFMT_HDMI_AUDIO_PACKETS_PER_LINE 16 20 AFMT_HDMI_AUDIO_SEND_MAX_PACKETS 24 24 regAFMT0_AFMT_AUDIO_PACKET_CONTROL2 0 0x2075 6 0 2 AFMT_AUDIO_LAYOUT_OVRD 0 0 AFMT_AUDIO_LAYOUT_SELECT 1 1 AFMT_AUDIO_CHANNEL_ENABLE 8 15 AFMT_DP_AUDIO_STREAM_ID 16 23 AFMT_HBR_ENABLE_OVRD 24 24 AFMT_60958_OSF_OVRD 28 28 regAFMT0_AFMT_AUDIO_INFO0 0 0x2076 5 0 2 AFMT_AUDIO_INFO_CHECKSUM 0 7 AFMT_AUDIO_INFO_CC 8 10 AFMT_AUDIO_INFO_CT 11 14 AFMT_AUDIO_INFO_CHECKSUM_OFFSET 16 23 AFMT_AUDIO_INFO_CXT 24 28 regAFMT0_AFMT_AUDIO_INFO1 0 0x2077 4 0 2 AFMT_AUDIO_INFO_CA 0 7 AFMT_AUDIO_INFO_LSV 11 14 AFMT_AUDIO_INFO_DM_INH 15 15 AFMT_AUDIO_INFO_LFEPBL 16 17 regAFMT0_AFMT_60958_0 0 0x2078 10 0 2 AFMT_60958_CS_A 0 0 AFMT_60958_CS_B 1 1 AFMT_60958_CS_C 2 2 AFMT_60958_CS_D 3 5 AFMT_60958_CS_MODE 6 7 AFMT_60958_CS_CATEGORY_CODE 8 15 AFMT_60958_CS_SOURCE_NUMBER 16 19 AFMT_60958_CS_CHANNEL_NUMBER_L 20 23 AFMT_60958_CS_SAMPLING_FREQUENCY 24 27 AFMT_60958_CS_CLOCK_ACCURACY 28 29 regAFMT0_AFMT_60958_1 0 0x2079 5 0 2 AFMT_60958_CS_WORD_LENGTH 0 3 AFMT_60958_CS_ORIGINAL_SAMPLING_FREQUENCY 4 7 AFMT_60958_VALID_L 16 16 AFMT_60958_VALID_R 18 18 AFMT_60958_CS_CHANNEL_NUMBER_R 20 23 regAFMT0_AFMT_AUDIO_CRC_CONTROL 0 0x207a 5 0 2 AFMT_AUDIO_CRC_EN 0 0 AFMT_AUDIO_CRC_CONT 4 4 AFMT_AUDIO_CRC_SOURCE 8 8 AFMT_AUDIO_CRC_CH_SEL 12 15 AFMT_AUDIO_CRC_COUNT 16 31 regAFMT0_AFMT_RAMP_CONTROL0 0 0x207b 2 0 2 AFMT_RAMP_MAX_COUNT 0 23 AFMT_RAMP_DATA_SIGN 31 31 regAFMT0_AFMT_RAMP_CONTROL1 0 0x207c 2 0 2 AFMT_RAMP_MIN_COUNT 0 23 AFMT_AUDIO_TEST_CH_DISABLE 24 31 regAFMT0_AFMT_RAMP_CONTROL2 0 0x207d 1 0 2 AFMT_RAMP_INC_COUNT 0 23 regAFMT0_AFMT_RAMP_CONTROL3 0 0x207e 1 0 2 AFMT_RAMP_DEC_COUNT 0 23 regAFMT0_AFMT_60958_2 0 0x207f 6 0 2 AFMT_60958_CS_CHANNEL_NUMBER_2 0 3 AFMT_60958_CS_CHANNEL_NUMBER_3 4 7 AFMT_60958_CS_CHANNEL_NUMBER_4 8 11 AFMT_60958_CS_CHANNEL_NUMBER_5 12 15 AFMT_60958_CS_CHANNEL_NUMBER_6 16 19 AFMT_60958_CS_CHANNEL_NUMBER_7 20 23 regAFMT0_AFMT_AUDIO_CRC_RESULT 0 0x2080 2 0 2 AFMT_AUDIO_CRC_DONE 0 0 AFMT_AUDIO_CRC 8 31 regAFMT0_AFMT_STATUS 0 0x2081 4 0 2 AFMT_AUDIO_ENABLE 4 4 AFMT_AZ_HBR_ENABLE 8 8 AFMT_AUDIO_FIFO_OVERFLOW 24 24 AFMT_AZ_AUDIO_ENABLE_CHG 30 30 regAFMT0_AFMT_AUDIO_PACKET_CONTROL 0 0x2082 10 0 2 AFMT_AUDIO_SAMPLE_SEND 0 0 AFMT_AUDIO_SAMPLE_SEND_DOUBLE_BUFFER_ENABLE 4 4 AFMT_RESET_FIFO_WHEN_AUDIO_DIS 11 11 AFMT_AUDIO_TEST_EN 12 12 AFMT_AUDIO_TEST_MODE 14 14 AFMT_AUDIO_FIFO_OVERFLOW_ACK 23 23 AFMT_AUDIO_CHANNEL_SWAP 24 24 AFMT_60958_CS_UPDATE 26 26 AFMT_AZ_AUDIO_ENABLE_CHG_ACK 30 30 AFMT_BLANK_TEST_DATA_ON_ENC_ENB 31 31 regAFMT0_AFMT_INFOFRAME_CONTROL0 0 0x2083 2 0 2 AFMT_AUDIO_INFO_SOURCE 6 6 AFMT_AUDIO_INFO_UPDATE 7 7 regAFMT0_AFMT_AUDIO_SRC_CONTROL 0 0x2085 1 0 2 AFMT_AUDIO_SRC_SELECT 0 2 regAFMT0_AFMT_MEM_PWR 0 0x2087 3 0 2 AFMT_MEM_PWR_DIS 0 0 AFMT_MEM_PWR_FORCE 4 5 AFMT_MEM_PWR_STATE 8 9 regAFMT1_AFMT_VBI_PACKET_CONTROL 0 0x2174 3 0 2 AFMT_ACP_SOURCE 13 13 AFMT_HDMI_AUDIO_PACKETS_PER_LINE 16 20 AFMT_HDMI_AUDIO_SEND_MAX_PACKETS 24 24 regAFMT1_AFMT_AUDIO_PACKET_CONTROL2 0 0x2175 6 0 2 AFMT_AUDIO_LAYOUT_OVRD 0 0 AFMT_AUDIO_LAYOUT_SELECT 1 1 AFMT_AUDIO_CHANNEL_ENABLE 8 15 AFMT_DP_AUDIO_STREAM_ID 16 23 AFMT_HBR_ENABLE_OVRD 24 24 AFMT_60958_OSF_OVRD 28 28 regAFMT1_AFMT_AUDIO_INFO0 0 0x2176 5 0 2 AFMT_AUDIO_INFO_CHECKSUM 0 7 AFMT_AUDIO_INFO_CC 8 10 AFMT_AUDIO_INFO_CT 11 14 AFMT_AUDIO_INFO_CHECKSUM_OFFSET 16 23 AFMT_AUDIO_INFO_CXT 24 28 regAFMT1_AFMT_AUDIO_INFO1 0 0x2177 4 0 2 AFMT_AUDIO_INFO_CA 0 7 AFMT_AUDIO_INFO_LSV 11 14 AFMT_AUDIO_INFO_DM_INH 15 15 AFMT_AUDIO_INFO_LFEPBL 16 17 regAFMT1_AFMT_60958_0 0 0x2178 10 0 2 AFMT_60958_CS_A 0 0 AFMT_60958_CS_B 1 1 AFMT_60958_CS_C 2 2 AFMT_60958_CS_D 3 5 AFMT_60958_CS_MODE 6 7 AFMT_60958_CS_CATEGORY_CODE 8 15 AFMT_60958_CS_SOURCE_NUMBER 16 19 AFMT_60958_CS_CHANNEL_NUMBER_L 20 23 AFMT_60958_CS_SAMPLING_FREQUENCY 24 27 AFMT_60958_CS_CLOCK_ACCURACY 28 29 regAFMT1_AFMT_60958_1 0 0x2179 5 0 2 AFMT_60958_CS_WORD_LENGTH 0 3 AFMT_60958_CS_ORIGINAL_SAMPLING_FREQUENCY 4 7 AFMT_60958_VALID_L 16 16 AFMT_60958_VALID_R 18 18 AFMT_60958_CS_CHANNEL_NUMBER_R 20 23 regAFMT1_AFMT_AUDIO_CRC_CONTROL 0 0x217a 5 0 2 AFMT_AUDIO_CRC_EN 0 0 AFMT_AUDIO_CRC_CONT 4 4 AFMT_AUDIO_CRC_SOURCE 8 8 AFMT_AUDIO_CRC_CH_SEL 12 15 AFMT_AUDIO_CRC_COUNT 16 31 regAFMT1_AFMT_RAMP_CONTROL0 0 0x217b 2 0 2 AFMT_RAMP_MAX_COUNT 0 23 AFMT_RAMP_DATA_SIGN 31 31 regAFMT1_AFMT_RAMP_CONTROL1 0 0x217c 2 0 2 AFMT_RAMP_MIN_COUNT 0 23 AFMT_AUDIO_TEST_CH_DISABLE 24 31 regAFMT1_AFMT_RAMP_CONTROL2 0 0x217d 1 0 2 AFMT_RAMP_INC_COUNT 0 23 regAFMT1_AFMT_RAMP_CONTROL3 0 0x217e 1 0 2 AFMT_RAMP_DEC_COUNT 0 23 regAFMT1_AFMT_60958_2 0 0x217f 6 0 2 AFMT_60958_CS_CHANNEL_NUMBER_2 0 3 AFMT_60958_CS_CHANNEL_NUMBER_3 4 7 AFMT_60958_CS_CHANNEL_NUMBER_4 8 11 AFMT_60958_CS_CHANNEL_NUMBER_5 12 15 AFMT_60958_CS_CHANNEL_NUMBER_6 16 19 AFMT_60958_CS_CHANNEL_NUMBER_7 20 23 regAFMT1_AFMT_AUDIO_CRC_RESULT 0 0x2180 2 0 2 AFMT_AUDIO_CRC_DONE 0 0 AFMT_AUDIO_CRC 8 31 regAFMT1_AFMT_STATUS 0 0x2181 4 0 2 AFMT_AUDIO_ENABLE 4 4 AFMT_AZ_HBR_ENABLE 8 8 AFMT_AUDIO_FIFO_OVERFLOW 24 24 AFMT_AZ_AUDIO_ENABLE_CHG 30 30 regAFMT1_AFMT_AUDIO_PACKET_CONTROL 0 0x2182 10 0 2 AFMT_AUDIO_SAMPLE_SEND 0 0 AFMT_AUDIO_SAMPLE_SEND_DOUBLE_BUFFER_ENABLE 4 4 AFMT_RESET_FIFO_WHEN_AUDIO_DIS 11 11 AFMT_AUDIO_TEST_EN 12 12 AFMT_AUDIO_TEST_MODE 14 14 AFMT_AUDIO_FIFO_OVERFLOW_ACK 23 23 AFMT_AUDIO_CHANNEL_SWAP 24 24 AFMT_60958_CS_UPDATE 26 26 AFMT_AZ_AUDIO_ENABLE_CHG_ACK 30 30 AFMT_BLANK_TEST_DATA_ON_ENC_ENB 31 31 regAFMT1_AFMT_INFOFRAME_CONTROL0 0 0x2183 2 0 2 AFMT_AUDIO_INFO_SOURCE 6 6 AFMT_AUDIO_INFO_UPDATE 7 7 regAFMT1_AFMT_AUDIO_SRC_CONTROL 0 0x2185 1 0 2 AFMT_AUDIO_SRC_SELECT 0 2 regAFMT1_AFMT_MEM_PWR 0 0x2187 3 0 2 AFMT_MEM_PWR_DIS 0 0 AFMT_MEM_PWR_FORCE 4 5 AFMT_MEM_PWR_STATE 8 9 regAFMT2_AFMT_VBI_PACKET_CONTROL 0 0x2274 3 0 2 AFMT_ACP_SOURCE 13 13 AFMT_HDMI_AUDIO_PACKETS_PER_LINE 16 20 AFMT_HDMI_AUDIO_SEND_MAX_PACKETS 24 24 regAFMT2_AFMT_AUDIO_PACKET_CONTROL2 0 0x2275 6 0 2 AFMT_AUDIO_LAYOUT_OVRD 0 0 AFMT_AUDIO_LAYOUT_SELECT 1 1 AFMT_AUDIO_CHANNEL_ENABLE 8 15 AFMT_DP_AUDIO_STREAM_ID 16 23 AFMT_HBR_ENABLE_OVRD 24 24 AFMT_60958_OSF_OVRD 28 28 regAFMT2_AFMT_AUDIO_INFO0 0 0x2276 5 0 2 AFMT_AUDIO_INFO_CHECKSUM 0 7 AFMT_AUDIO_INFO_CC 8 10 AFMT_AUDIO_INFO_CT 11 14 AFMT_AUDIO_INFO_CHECKSUM_OFFSET 16 23 AFMT_AUDIO_INFO_CXT 24 28 regAFMT2_AFMT_AUDIO_INFO1 0 0x2277 4 0 2 AFMT_AUDIO_INFO_CA 0 7 AFMT_AUDIO_INFO_LSV 11 14 AFMT_AUDIO_INFO_DM_INH 15 15 AFMT_AUDIO_INFO_LFEPBL 16 17 regAFMT2_AFMT_60958_0 0 0x2278 10 0 2 AFMT_60958_CS_A 0 0 AFMT_60958_CS_B 1 1 AFMT_60958_CS_C 2 2 AFMT_60958_CS_D 3 5 AFMT_60958_CS_MODE 6 7 AFMT_60958_CS_CATEGORY_CODE 8 15 AFMT_60958_CS_SOURCE_NUMBER 16 19 AFMT_60958_CS_CHANNEL_NUMBER_L 20 23 AFMT_60958_CS_SAMPLING_FREQUENCY 24 27 AFMT_60958_CS_CLOCK_ACCURACY 28 29 regAFMT2_AFMT_60958_1 0 0x2279 5 0 2 AFMT_60958_CS_WORD_LENGTH 0 3 AFMT_60958_CS_ORIGINAL_SAMPLING_FREQUENCY 4 7 AFMT_60958_VALID_L 16 16 AFMT_60958_VALID_R 18 18 AFMT_60958_CS_CHANNEL_NUMBER_R 20 23 regAFMT2_AFMT_AUDIO_CRC_CONTROL 0 0x227a 5 0 2 AFMT_AUDIO_CRC_EN 0 0 AFMT_AUDIO_CRC_CONT 4 4 AFMT_AUDIO_CRC_SOURCE 8 8 AFMT_AUDIO_CRC_CH_SEL 12 15 AFMT_AUDIO_CRC_COUNT 16 31 regAFMT2_AFMT_RAMP_CONTROL0 0 0x227b 2 0 2 AFMT_RAMP_MAX_COUNT 0 23 AFMT_RAMP_DATA_SIGN 31 31 regAFMT2_AFMT_RAMP_CONTROL1 0 0x227c 2 0 2 AFMT_RAMP_MIN_COUNT 0 23 AFMT_AUDIO_TEST_CH_DISABLE 24 31 regAFMT2_AFMT_RAMP_CONTROL2 0 0x227d 1 0 2 AFMT_RAMP_INC_COUNT 0 23 regAFMT2_AFMT_RAMP_CONTROL3 0 0x227e 1 0 2 AFMT_RAMP_DEC_COUNT 0 23 regAFMT2_AFMT_60958_2 0 0x227f 6 0 2 AFMT_60958_CS_CHANNEL_NUMBER_2 0 3 AFMT_60958_CS_CHANNEL_NUMBER_3 4 7 AFMT_60958_CS_CHANNEL_NUMBER_4 8 11 AFMT_60958_CS_CHANNEL_NUMBER_5 12 15 AFMT_60958_CS_CHANNEL_NUMBER_6 16 19 AFMT_60958_CS_CHANNEL_NUMBER_7 20 23 regAFMT2_AFMT_AUDIO_CRC_RESULT 0 0x2280 2 0 2 AFMT_AUDIO_CRC_DONE 0 0 AFMT_AUDIO_CRC 8 31 regAFMT2_AFMT_STATUS 0 0x2281 4 0 2 AFMT_AUDIO_ENABLE 4 4 AFMT_AZ_HBR_ENABLE 8 8 AFMT_AUDIO_FIFO_OVERFLOW 24 24 AFMT_AZ_AUDIO_ENABLE_CHG 30 30 regAFMT2_AFMT_AUDIO_PACKET_CONTROL 0 0x2282 10 0 2 AFMT_AUDIO_SAMPLE_SEND 0 0 AFMT_AUDIO_SAMPLE_SEND_DOUBLE_BUFFER_ENABLE 4 4 AFMT_RESET_FIFO_WHEN_AUDIO_DIS 11 11 AFMT_AUDIO_TEST_EN 12 12 AFMT_AUDIO_TEST_MODE 14 14 AFMT_AUDIO_FIFO_OVERFLOW_ACK 23 23 AFMT_AUDIO_CHANNEL_SWAP 24 24 AFMT_60958_CS_UPDATE 26 26 AFMT_AZ_AUDIO_ENABLE_CHG_ACK 30 30 AFMT_BLANK_TEST_DATA_ON_ENC_ENB 31 31 regAFMT2_AFMT_INFOFRAME_CONTROL0 0 0x2283 2 0 2 AFMT_AUDIO_INFO_SOURCE 6 6 AFMT_AUDIO_INFO_UPDATE 7 7 regAFMT2_AFMT_AUDIO_SRC_CONTROL 0 0x2285 1 0 2 AFMT_AUDIO_SRC_SELECT 0 2 regAFMT2_AFMT_MEM_PWR 0 0x2287 3 0 2 AFMT_MEM_PWR_DIS 0 0 AFMT_MEM_PWR_FORCE 4 5 AFMT_MEM_PWR_STATE 8 9 regAFMT3_AFMT_VBI_PACKET_CONTROL 0 0x2374 3 0 2 AFMT_ACP_SOURCE 13 13 AFMT_HDMI_AUDIO_PACKETS_PER_LINE 16 20 AFMT_HDMI_AUDIO_SEND_MAX_PACKETS 24 24 regAFMT3_AFMT_AUDIO_PACKET_CONTROL2 0 0x2375 6 0 2 AFMT_AUDIO_LAYOUT_OVRD 0 0 AFMT_AUDIO_LAYOUT_SELECT 1 1 AFMT_AUDIO_CHANNEL_ENABLE 8 15 AFMT_DP_AUDIO_STREAM_ID 16 23 AFMT_HBR_ENABLE_OVRD 24 24 AFMT_60958_OSF_OVRD 28 28 regAFMT3_AFMT_AUDIO_INFO0 0 0x2376 5 0 2 AFMT_AUDIO_INFO_CHECKSUM 0 7 AFMT_AUDIO_INFO_CC 8 10 AFMT_AUDIO_INFO_CT 11 14 AFMT_AUDIO_INFO_CHECKSUM_OFFSET 16 23 AFMT_AUDIO_INFO_CXT 24 28 regAFMT3_AFMT_AUDIO_INFO1 0 0x2377 4 0 2 AFMT_AUDIO_INFO_CA 0 7 AFMT_AUDIO_INFO_LSV 11 14 AFMT_AUDIO_INFO_DM_INH 15 15 AFMT_AUDIO_INFO_LFEPBL 16 17 regAFMT3_AFMT_60958_0 0 0x2378 10 0 2 AFMT_60958_CS_A 0 0 AFMT_60958_CS_B 1 1 AFMT_60958_CS_C 2 2 AFMT_60958_CS_D 3 5 AFMT_60958_CS_MODE 6 7 AFMT_60958_CS_CATEGORY_CODE 8 15 AFMT_60958_CS_SOURCE_NUMBER 16 19 AFMT_60958_CS_CHANNEL_NUMBER_L 20 23 AFMT_60958_CS_SAMPLING_FREQUENCY 24 27 AFMT_60958_CS_CLOCK_ACCURACY 28 29 regAFMT3_AFMT_60958_1 0 0x2379 5 0 2 AFMT_60958_CS_WORD_LENGTH 0 3 AFMT_60958_CS_ORIGINAL_SAMPLING_FREQUENCY 4 7 AFMT_60958_VALID_L 16 16 AFMT_60958_VALID_R 18 18 AFMT_60958_CS_CHANNEL_NUMBER_R 20 23 regAFMT3_AFMT_AUDIO_CRC_CONTROL 0 0x237a 5 0 2 AFMT_AUDIO_CRC_EN 0 0 AFMT_AUDIO_CRC_CONT 4 4 AFMT_AUDIO_CRC_SOURCE 8 8 AFMT_AUDIO_CRC_CH_SEL 12 15 AFMT_AUDIO_CRC_COUNT 16 31 regAFMT3_AFMT_RAMP_CONTROL0 0 0x237b 2 0 2 AFMT_RAMP_MAX_COUNT 0 23 AFMT_RAMP_DATA_SIGN 31 31 regAFMT3_AFMT_RAMP_CONTROL1 0 0x237c 2 0 2 AFMT_RAMP_MIN_COUNT 0 23 AFMT_AUDIO_TEST_CH_DISABLE 24 31 regAFMT3_AFMT_RAMP_CONTROL2 0 0x237d 1 0 2 AFMT_RAMP_INC_COUNT 0 23 regAFMT3_AFMT_RAMP_CONTROL3 0 0x237e 1 0 2 AFMT_RAMP_DEC_COUNT 0 23 regAFMT3_AFMT_60958_2 0 0x237f 6 0 2 AFMT_60958_CS_CHANNEL_NUMBER_2 0 3 AFMT_60958_CS_CHANNEL_NUMBER_3 4 7 AFMT_60958_CS_CHANNEL_NUMBER_4 8 11 AFMT_60958_CS_CHANNEL_NUMBER_5 12 15 AFMT_60958_CS_CHANNEL_NUMBER_6 16 19 AFMT_60958_CS_CHANNEL_NUMBER_7 20 23 regAFMT3_AFMT_AUDIO_CRC_RESULT 0 0x2380 2 0 2 AFMT_AUDIO_CRC_DONE 0 0 AFMT_AUDIO_CRC 8 31 regAFMT3_AFMT_STATUS 0 0x2381 4 0 2 AFMT_AUDIO_ENABLE 4 4 AFMT_AZ_HBR_ENABLE 8 8 AFMT_AUDIO_FIFO_OVERFLOW 24 24 AFMT_AZ_AUDIO_ENABLE_CHG 30 30 regAFMT3_AFMT_AUDIO_PACKET_CONTROL 0 0x2382 10 0 2 AFMT_AUDIO_SAMPLE_SEND 0 0 AFMT_AUDIO_SAMPLE_SEND_DOUBLE_BUFFER_ENABLE 4 4 AFMT_RESET_FIFO_WHEN_AUDIO_DIS 11 11 AFMT_AUDIO_TEST_EN 12 12 AFMT_AUDIO_TEST_MODE 14 14 AFMT_AUDIO_FIFO_OVERFLOW_ACK 23 23 AFMT_AUDIO_CHANNEL_SWAP 24 24 AFMT_60958_CS_UPDATE 26 26 AFMT_AZ_AUDIO_ENABLE_CHG_ACK 30 30 AFMT_BLANK_TEST_DATA_ON_ENC_ENB 31 31 regAFMT3_AFMT_INFOFRAME_CONTROL0 0 0x2383 2 0 2 AFMT_AUDIO_INFO_SOURCE 6 6 AFMT_AUDIO_INFO_UPDATE 7 7 regAFMT3_AFMT_AUDIO_SRC_CONTROL 0 0x2385 1 0 2 AFMT_AUDIO_SRC_SELECT 0 2 regAFMT3_AFMT_MEM_PWR 0 0x2387 3 0 2 AFMT_MEM_PWR_DIS 0 0 AFMT_MEM_PWR_FORCE 4 5 AFMT_MEM_PWR_STATE 8 9 regAFMT4_AFMT_VBI_PACKET_CONTROL 0 0x2474 3 0 2 AFMT_ACP_SOURCE 13 13 AFMT_HDMI_AUDIO_PACKETS_PER_LINE 16 20 AFMT_HDMI_AUDIO_SEND_MAX_PACKETS 24 24 regAFMT4_AFMT_AUDIO_PACKET_CONTROL2 0 0x2475 6 0 2 AFMT_AUDIO_LAYOUT_OVRD 0 0 AFMT_AUDIO_LAYOUT_SELECT 1 1 AFMT_AUDIO_CHANNEL_ENABLE 8 15 AFMT_DP_AUDIO_STREAM_ID 16 23 AFMT_HBR_ENABLE_OVRD 24 24 AFMT_60958_OSF_OVRD 28 28 regAFMT4_AFMT_AUDIO_INFO0 0 0x2476 5 0 2 AFMT_AUDIO_INFO_CHECKSUM 0 7 AFMT_AUDIO_INFO_CC 8 10 AFMT_AUDIO_INFO_CT 11 14 AFMT_AUDIO_INFO_CHECKSUM_OFFSET 16 23 AFMT_AUDIO_INFO_CXT 24 28 regAFMT4_AFMT_AUDIO_INFO1 0 0x2477 4 0 2 AFMT_AUDIO_INFO_CA 0 7 AFMT_AUDIO_INFO_LSV 11 14 AFMT_AUDIO_INFO_DM_INH 15 15 AFMT_AUDIO_INFO_LFEPBL 16 17 regAFMT4_AFMT_60958_0 0 0x2478 10 0 2 AFMT_60958_CS_A 0 0 AFMT_60958_CS_B 1 1 AFMT_60958_CS_C 2 2 AFMT_60958_CS_D 3 5 AFMT_60958_CS_MODE 6 7 AFMT_60958_CS_CATEGORY_CODE 8 15 AFMT_60958_CS_SOURCE_NUMBER 16 19 AFMT_60958_CS_CHANNEL_NUMBER_L 20 23 AFMT_60958_CS_SAMPLING_FREQUENCY 24 27 AFMT_60958_CS_CLOCK_ACCURACY 28 29 regAFMT4_AFMT_60958_1 0 0x2479 5 0 2 AFMT_60958_CS_WORD_LENGTH 0 3 AFMT_60958_CS_ORIGINAL_SAMPLING_FREQUENCY 4 7 AFMT_60958_VALID_L 16 16 AFMT_60958_VALID_R 18 18 AFMT_60958_CS_CHANNEL_NUMBER_R 20 23 regAFMT4_AFMT_AUDIO_CRC_CONTROL 0 0x247a 5 0 2 AFMT_AUDIO_CRC_EN 0 0 AFMT_AUDIO_CRC_CONT 4 4 AFMT_AUDIO_CRC_SOURCE 8 8 AFMT_AUDIO_CRC_CH_SEL 12 15 AFMT_AUDIO_CRC_COUNT 16 31 regAFMT4_AFMT_RAMP_CONTROL0 0 0x247b 2 0 2 AFMT_RAMP_MAX_COUNT 0 23 AFMT_RAMP_DATA_SIGN 31 31 regAFMT4_AFMT_RAMP_CONTROL1 0 0x247c 2 0 2 AFMT_RAMP_MIN_COUNT 0 23 AFMT_AUDIO_TEST_CH_DISABLE 24 31 regAFMT4_AFMT_RAMP_CONTROL2 0 0x247d 1 0 2 AFMT_RAMP_INC_COUNT 0 23 regAFMT4_AFMT_RAMP_CONTROL3 0 0x247e 1 0 2 AFMT_RAMP_DEC_COUNT 0 23 regAFMT4_AFMT_60958_2 0 0x247f 6 0 2 AFMT_60958_CS_CHANNEL_NUMBER_2 0 3 AFMT_60958_CS_CHANNEL_NUMBER_3 4 7 AFMT_60958_CS_CHANNEL_NUMBER_4 8 11 AFMT_60958_CS_CHANNEL_NUMBER_5 12 15 AFMT_60958_CS_CHANNEL_NUMBER_6 16 19 AFMT_60958_CS_CHANNEL_NUMBER_7 20 23 regAFMT4_AFMT_AUDIO_CRC_RESULT 0 0x2480 2 0 2 AFMT_AUDIO_CRC_DONE 0 0 AFMT_AUDIO_CRC 8 31 regAFMT4_AFMT_STATUS 0 0x2481 4 0 2 AFMT_AUDIO_ENABLE 4 4 AFMT_AZ_HBR_ENABLE 8 8 AFMT_AUDIO_FIFO_OVERFLOW 24 24 AFMT_AZ_AUDIO_ENABLE_CHG 30 30 regAFMT4_AFMT_AUDIO_PACKET_CONTROL 0 0x2482 10 0 2 AFMT_AUDIO_SAMPLE_SEND 0 0 AFMT_AUDIO_SAMPLE_SEND_DOUBLE_BUFFER_ENABLE 4 4 AFMT_RESET_FIFO_WHEN_AUDIO_DIS 11 11 AFMT_AUDIO_TEST_EN 12 12 AFMT_AUDIO_TEST_MODE 14 14 AFMT_AUDIO_FIFO_OVERFLOW_ACK 23 23 AFMT_AUDIO_CHANNEL_SWAP 24 24 AFMT_60958_CS_UPDATE 26 26 AFMT_AZ_AUDIO_ENABLE_CHG_ACK 30 30 AFMT_BLANK_TEST_DATA_ON_ENC_ENB 31 31 regAFMT4_AFMT_INFOFRAME_CONTROL0 0 0x2483 2 0 2 AFMT_AUDIO_INFO_SOURCE 6 6 AFMT_AUDIO_INFO_UPDATE 7 7 regAFMT4_AFMT_AUDIO_SRC_CONTROL 0 0x2485 1 0 2 AFMT_AUDIO_SRC_SELECT 0 2 regAFMT4_AFMT_MEM_PWR 0 0x2487 3 0 2 AFMT_MEM_PWR_DIS 0 0 AFMT_MEM_PWR_FORCE 4 5 AFMT_MEM_PWR_STATE 8 9 regDME0_DME_CONTROL 0 0x2089 9 0 2 METADATA_HUBP_REQUESTOR_ID 0 2 METADATA_ENGINE_EN 4 4 METADATA_STREAM_TYPE 8 8 METADATA_DB_PENDING 12 12 METADATA_DB_TAKEN 13 13 METADATA_DB_TAKEN_CLR 16 16 METADATA_DB_DISABLE 20 20 METADATA_TRANSMISSION_MISSED 24 24 METADATA_TRANSMISSION_MISSED_CLR 25 25 regDME0_DME_MEMORY_CONTROL 0 0x208a 4 0 2 DME_MEM_PWR_FORCE 0 1 DME_MEM_PWR_DIS 4 4 DME_MEM_PWR_STATE 8 9 DME_MEM_DEFAULT_MEM_LOW_POWER_STATE 12 13 regVPG0_VPG_GENERIC_PACKET_ACCESS_CTRL 0 0x2068 1 0 2 VPG_GENERIC_DATA_INDEX 0 7 regVPG0_VPG_GENERIC_PACKET_DATA 0 0x2069 4 0 2 VPG_GENERIC_DATA_BYTE0 0 7 VPG_GENERIC_DATA_BYTE1 8 15 VPG_GENERIC_DATA_BYTE2 16 23 VPG_GENERIC_DATA_BYTE3 24 31 regVPG0_VPG_GSP_FRAME_UPDATE_CTRL 0 0x206a 30 0 2 VPG_GENERIC0_FRAME_UPDATE 0 0 VPG_GENERIC1_FRAME_UPDATE 1 1 VPG_GENERIC2_FRAME_UPDATE 2 2 VPG_GENERIC3_FRAME_UPDATE 3 3 VPG_GENERIC4_FRAME_UPDATE 4 4 VPG_GENERIC5_FRAME_UPDATE 5 5 VPG_GENERIC6_FRAME_UPDATE 6 6 VPG_GENERIC7_FRAME_UPDATE 7 7 VPG_GENERIC8_FRAME_UPDATE 8 8 VPG_GENERIC9_FRAME_UPDATE 9 9 VPG_GENERIC10_FRAME_UPDATE 10 10 VPG_GENERIC11_FRAME_UPDATE 11 11 VPG_GENERIC12_FRAME_UPDATE 12 12 VPG_GENERIC13_FRAME_UPDATE 13 13 VPG_GENERIC14_FRAME_UPDATE 14 14 VPG_GENERIC0_FRAME_UPDATE_PENDING 16 16 VPG_GENERIC1_FRAME_UPDATE_PENDING 17 17 VPG_GENERIC2_FRAME_UPDATE_PENDING 18 18 VPG_GENERIC3_FRAME_UPDATE_PENDING 19 19 VPG_GENERIC4_FRAME_UPDATE_PENDING 20 20 VPG_GENERIC5_FRAME_UPDATE_PENDING 21 21 VPG_GENERIC6_FRAME_UPDATE_PENDING 22 22 VPG_GENERIC7_FRAME_UPDATE_PENDING 23 23 VPG_GENERIC8_FRAME_UPDATE_PENDING 24 24 VPG_GENERIC9_FRAME_UPDATE_PENDING 25 25 VPG_GENERIC10_FRAME_UPDATE_PENDING 26 26 VPG_GENERIC11_FRAME_UPDATE_PENDING 27 27 VPG_GENERIC12_FRAME_UPDATE_PENDING 28 28 VPG_GENERIC13_FRAME_UPDATE_PENDING 29 29 VPG_GENERIC14_FRAME_UPDATE_PENDING 30 30 regVPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL 0 0x206b 30 0 2 VPG_GENERIC0_IMMEDIATE_UPDATE 0 0 VPG_GENERIC1_IMMEDIATE_UPDATE 1 1 VPG_GENERIC2_IMMEDIATE_UPDATE 2 2 VPG_GENERIC3_IMMEDIATE_UPDATE 3 3 VPG_GENERIC4_IMMEDIATE_UPDATE 4 4 VPG_GENERIC5_IMMEDIATE_UPDATE 5 5 VPG_GENERIC6_IMMEDIATE_UPDATE 6 6 VPG_GENERIC7_IMMEDIATE_UPDATE 7 7 VPG_GENERIC8_IMMEDIATE_UPDATE 8 8 VPG_GENERIC9_IMMEDIATE_UPDATE 9 9 VPG_GENERIC10_IMMEDIATE_UPDATE 10 10 VPG_GENERIC11_IMMEDIATE_UPDATE 11 11 VPG_GENERIC12_IMMEDIATE_UPDATE 12 12 VPG_GENERIC13_IMMEDIATE_UPDATE 13 13 VPG_GENERIC14_IMMEDIATE_UPDATE 14 14 VPG_GENERIC0_IMMEDIATE_UPDATE_PENDING 16 16 VPG_GENERIC1_IMMEDIATE_UPDATE_PENDING 17 17 VPG_GENERIC2_IMMEDIATE_UPDATE_PENDING 18 18 VPG_GENERIC3_IMMEDIATE_UPDATE_PENDING 19 19 VPG_GENERIC4_IMMEDIATE_UPDATE_PENDING 20 20 VPG_GENERIC5_IMMEDIATE_UPDATE_PENDING 21 21 VPG_GENERIC6_IMMEDIATE_UPDATE_PENDING 22 22 VPG_GENERIC7_IMMEDIATE_UPDATE_PENDING 23 23 VPG_GENERIC8_IMMEDIATE_UPDATE_PENDING 24 24 VPG_GENERIC9_IMMEDIATE_UPDATE_PENDING 25 25 VPG_GENERIC10_IMMEDIATE_UPDATE_PENDING 26 26 VPG_GENERIC11_IMMEDIATE_UPDATE_PENDING 27 27 VPG_GENERIC12_IMMEDIATE_UPDATE_PENDING 28 28 VPG_GENERIC13_IMMEDIATE_UPDATE_PENDING 29 29 VPG_GENERIC14_IMMEDIATE_UPDATE_PENDING 30 30 regVPG0_VPG_GENERIC_STATUS 0 0x206c 3 0 2 VPG_GENERIC_LOCK_STATUS 0 0 VPG_GENERIC_CONFLICT_OCCURED 1 1 VPG_GENERIC_CONFLICT_CLR 4 4 regVPG0_VPG_MEM_PWR 0 0x206d 3 0 2 VPG_GSP_MEM_LIGHT_SLEEP_DIS 0 0 VPG_GSP_LIGHT_SLEEP_FORCE 4 4 VPG_GSP_MEM_PWR_STATE 8 8 regVPG0_VPG_ISRC1_2_ACCESS_CTRL 0 0x206e 1 0 2 VPG_ISRC1_2_DATA_INDEX 0 3 regVPG0_VPG_ISRC1_2_DATA 0 0x206f 4 0 2 VPG_ISRC_DATA_BYTE0 0 7 VPG_ISRC_DATA_BYTE1 8 15 VPG_ISRC_DATA_BYTE2 16 23 VPG_ISRC_DATA_BYTE3 24 31 regVPG0_VPG_MPEG_INFO0 0 0x2070 4 0 2 VPG_MPEG_INFO_CHECKSUM 0 7 VPG_MPEG_INFO_MB0 8 15 VPG_MPEG_INFO_MB1 16 23 VPG_MPEG_INFO_MB2 24 31 regVPG0_VPG_MPEG_INFO1 0 0x2071 4 0 2 VPG_MPEG_INFO_MB3 0 7 VPG_MPEG_INFO_MF 8 9 VPG_MPEG_INFO_FR 12 12 VPG_MPEG_INFO_UPDATE 16 16 regDME1_DME_CONTROL 0 0x2189 9 0 2 METADATA_HUBP_REQUESTOR_ID 0 2 METADATA_ENGINE_EN 4 4 METADATA_STREAM_TYPE 8 8 METADATA_DB_PENDING 12 12 METADATA_DB_TAKEN 13 13 METADATA_DB_TAKEN_CLR 16 16 METADATA_DB_DISABLE 20 20 METADATA_TRANSMISSION_MISSED 24 24 METADATA_TRANSMISSION_MISSED_CLR 25 25 regDME1_DME_MEMORY_CONTROL 0 0x218a 4 0 2 DME_MEM_PWR_FORCE 0 1 DME_MEM_PWR_DIS 4 4 DME_MEM_PWR_STATE 8 9 DME_MEM_DEFAULT_MEM_LOW_POWER_STATE 12 13 regVPG1_VPG_GENERIC_PACKET_ACCESS_CTRL 0 0x2168 1 0 2 VPG_GENERIC_DATA_INDEX 0 7 regVPG1_VPG_GENERIC_PACKET_DATA 0 0x2169 4 0 2 VPG_GENERIC_DATA_BYTE0 0 7 VPG_GENERIC_DATA_BYTE1 8 15 VPG_GENERIC_DATA_BYTE2 16 23 VPG_GENERIC_DATA_BYTE3 24 31 regVPG1_VPG_GSP_FRAME_UPDATE_CTRL 0 0x216a 30 0 2 VPG_GENERIC0_FRAME_UPDATE 0 0 VPG_GENERIC1_FRAME_UPDATE 1 1 VPG_GENERIC2_FRAME_UPDATE 2 2 VPG_GENERIC3_FRAME_UPDATE 3 3 VPG_GENERIC4_FRAME_UPDATE 4 4 VPG_GENERIC5_FRAME_UPDATE 5 5 VPG_GENERIC6_FRAME_UPDATE 6 6 VPG_GENERIC7_FRAME_UPDATE 7 7 VPG_GENERIC8_FRAME_UPDATE 8 8 VPG_GENERIC9_FRAME_UPDATE 9 9 VPG_GENERIC10_FRAME_UPDATE 10 10 VPG_GENERIC11_FRAME_UPDATE 11 11 VPG_GENERIC12_FRAME_UPDATE 12 12 VPG_GENERIC13_FRAME_UPDATE 13 13 VPG_GENERIC14_FRAME_UPDATE 14 14 VPG_GENERIC0_FRAME_UPDATE_PENDING 16 16 VPG_GENERIC1_FRAME_UPDATE_PENDING 17 17 VPG_GENERIC2_FRAME_UPDATE_PENDING 18 18 VPG_GENERIC3_FRAME_UPDATE_PENDING 19 19 VPG_GENERIC4_FRAME_UPDATE_PENDING 20 20 VPG_GENERIC5_FRAME_UPDATE_PENDING 21 21 VPG_GENERIC6_FRAME_UPDATE_PENDING 22 22 VPG_GENERIC7_FRAME_UPDATE_PENDING 23 23 VPG_GENERIC8_FRAME_UPDATE_PENDING 24 24 VPG_GENERIC9_FRAME_UPDATE_PENDING 25 25 VPG_GENERIC10_FRAME_UPDATE_PENDING 26 26 VPG_GENERIC11_FRAME_UPDATE_PENDING 27 27 VPG_GENERIC12_FRAME_UPDATE_PENDING 28 28 VPG_GENERIC13_FRAME_UPDATE_PENDING 29 29 VPG_GENERIC14_FRAME_UPDATE_PENDING 30 30 regVPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL 0 0x216b 30 0 2 VPG_GENERIC0_IMMEDIATE_UPDATE 0 0 VPG_GENERIC1_IMMEDIATE_UPDATE 1 1 VPG_GENERIC2_IMMEDIATE_UPDATE 2 2 VPG_GENERIC3_IMMEDIATE_UPDATE 3 3 VPG_GENERIC4_IMMEDIATE_UPDATE 4 4 VPG_GENERIC5_IMMEDIATE_UPDATE 5 5 VPG_GENERIC6_IMMEDIATE_UPDATE 6 6 VPG_GENERIC7_IMMEDIATE_UPDATE 7 7 VPG_GENERIC8_IMMEDIATE_UPDATE 8 8 VPG_GENERIC9_IMMEDIATE_UPDATE 9 9 VPG_GENERIC10_IMMEDIATE_UPDATE 10 10 VPG_GENERIC11_IMMEDIATE_UPDATE 11 11 VPG_GENERIC12_IMMEDIATE_UPDATE 12 12 VPG_GENERIC13_IMMEDIATE_UPDATE 13 13 VPG_GENERIC14_IMMEDIATE_UPDATE 14 14 VPG_GENERIC0_IMMEDIATE_UPDATE_PENDING 16 16 VPG_GENERIC1_IMMEDIATE_UPDATE_PENDING 17 17 VPG_GENERIC2_IMMEDIATE_UPDATE_PENDING 18 18 VPG_GENERIC3_IMMEDIATE_UPDATE_PENDING 19 19 VPG_GENERIC4_IMMEDIATE_UPDATE_PENDING 20 20 VPG_GENERIC5_IMMEDIATE_UPDATE_PENDING 21 21 VPG_GENERIC6_IMMEDIATE_UPDATE_PENDING 22 22 VPG_GENERIC7_IMMEDIATE_UPDATE_PENDING 23 23 VPG_GENERIC8_IMMEDIATE_UPDATE_PENDING 24 24 VPG_GENERIC9_IMMEDIATE_UPDATE_PENDING 25 25 VPG_GENERIC10_IMMEDIATE_UPDATE_PENDING 26 26 VPG_GENERIC11_IMMEDIATE_UPDATE_PENDING 27 27 VPG_GENERIC12_IMMEDIATE_UPDATE_PENDING 28 28 VPG_GENERIC13_IMMEDIATE_UPDATE_PENDING 29 29 VPG_GENERIC14_IMMEDIATE_UPDATE_PENDING 30 30 regVPG1_VPG_GENERIC_STATUS 0 0x216c 3 0 2 VPG_GENERIC_LOCK_STATUS 0 0 VPG_GENERIC_CONFLICT_OCCURED 1 1 VPG_GENERIC_CONFLICT_CLR 4 4 regVPG1_VPG_MEM_PWR 0 0x216d 3 0 2 VPG_GSP_MEM_LIGHT_SLEEP_DIS 0 0 VPG_GSP_LIGHT_SLEEP_FORCE 4 4 VPG_GSP_MEM_PWR_STATE 8 8 regVPG1_VPG_ISRC1_2_ACCESS_CTRL 0 0x216e 1 0 2 VPG_ISRC1_2_DATA_INDEX 0 3 regVPG1_VPG_ISRC1_2_DATA 0 0x216f 4 0 2 VPG_ISRC_DATA_BYTE0 0 7 VPG_ISRC_DATA_BYTE1 8 15 VPG_ISRC_DATA_BYTE2 16 23 VPG_ISRC_DATA_BYTE3 24 31 regVPG1_VPG_MPEG_INFO0 0 0x2170 4 0 2 VPG_MPEG_INFO_CHECKSUM 0 7 VPG_MPEG_INFO_MB0 8 15 VPG_MPEG_INFO_MB1 16 23 VPG_MPEG_INFO_MB2 24 31 regVPG1_VPG_MPEG_INFO1 0 0x2171 4 0 2 VPG_MPEG_INFO_MB3 0 7 VPG_MPEG_INFO_MF 8 9 VPG_MPEG_INFO_FR 12 12 VPG_MPEG_INFO_UPDATE 16 16 regDME2_DME_CONTROL 0 0x2289 9 0 2 METADATA_HUBP_REQUESTOR_ID 0 2 METADATA_ENGINE_EN 4 4 METADATA_STREAM_TYPE 8 8 METADATA_DB_PENDING 12 12 METADATA_DB_TAKEN 13 13 METADATA_DB_TAKEN_CLR 16 16 METADATA_DB_DISABLE 20 20 METADATA_TRANSMISSION_MISSED 24 24 METADATA_TRANSMISSION_MISSED_CLR 25 25 regDME2_DME_MEMORY_CONTROL 0 0x228a 4 0 2 DME_MEM_PWR_FORCE 0 1 DME_MEM_PWR_DIS 4 4 DME_MEM_PWR_STATE 8 9 DME_MEM_DEFAULT_MEM_LOW_POWER_STATE 12 13 regVPG2_VPG_GENERIC_PACKET_ACCESS_CTRL 0 0x2268 1 0 2 VPG_GENERIC_DATA_INDEX 0 7 regVPG2_VPG_GENERIC_PACKET_DATA 0 0x2269 4 0 2 VPG_GENERIC_DATA_BYTE0 0 7 VPG_GENERIC_DATA_BYTE1 8 15 VPG_GENERIC_DATA_BYTE2 16 23 VPG_GENERIC_DATA_BYTE3 24 31 regVPG2_VPG_GSP_FRAME_UPDATE_CTRL 0 0x226a 30 0 2 VPG_GENERIC0_FRAME_UPDATE 0 0 VPG_GENERIC1_FRAME_UPDATE 1 1 VPG_GENERIC2_FRAME_UPDATE 2 2 VPG_GENERIC3_FRAME_UPDATE 3 3 VPG_GENERIC4_FRAME_UPDATE 4 4 VPG_GENERIC5_FRAME_UPDATE 5 5 VPG_GENERIC6_FRAME_UPDATE 6 6 VPG_GENERIC7_FRAME_UPDATE 7 7 VPG_GENERIC8_FRAME_UPDATE 8 8 VPG_GENERIC9_FRAME_UPDATE 9 9 VPG_GENERIC10_FRAME_UPDATE 10 10 VPG_GENERIC11_FRAME_UPDATE 11 11 VPG_GENERIC12_FRAME_UPDATE 12 12 VPG_GENERIC13_FRAME_UPDATE 13 13 VPG_GENERIC14_FRAME_UPDATE 14 14 VPG_GENERIC0_FRAME_UPDATE_PENDING 16 16 VPG_GENERIC1_FRAME_UPDATE_PENDING 17 17 VPG_GENERIC2_FRAME_UPDATE_PENDING 18 18 VPG_GENERIC3_FRAME_UPDATE_PENDING 19 19 VPG_GENERIC4_FRAME_UPDATE_PENDING 20 20 VPG_GENERIC5_FRAME_UPDATE_PENDING 21 21 VPG_GENERIC6_FRAME_UPDATE_PENDING 22 22 VPG_GENERIC7_FRAME_UPDATE_PENDING 23 23 VPG_GENERIC8_FRAME_UPDATE_PENDING 24 24 VPG_GENERIC9_FRAME_UPDATE_PENDING 25 25 VPG_GENERIC10_FRAME_UPDATE_PENDING 26 26 VPG_GENERIC11_FRAME_UPDATE_PENDING 27 27 VPG_GENERIC12_FRAME_UPDATE_PENDING 28 28 VPG_GENERIC13_FRAME_UPDATE_PENDING 29 29 VPG_GENERIC14_FRAME_UPDATE_PENDING 30 30 regVPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL 0 0x226b 30 0 2 VPG_GENERIC0_IMMEDIATE_UPDATE 0 0 VPG_GENERIC1_IMMEDIATE_UPDATE 1 1 VPG_GENERIC2_IMMEDIATE_UPDATE 2 2 VPG_GENERIC3_IMMEDIATE_UPDATE 3 3 VPG_GENERIC4_IMMEDIATE_UPDATE 4 4 VPG_GENERIC5_IMMEDIATE_UPDATE 5 5 VPG_GENERIC6_IMMEDIATE_UPDATE 6 6 VPG_GENERIC7_IMMEDIATE_UPDATE 7 7 VPG_GENERIC8_IMMEDIATE_UPDATE 8 8 VPG_GENERIC9_IMMEDIATE_UPDATE 9 9 VPG_GENERIC10_IMMEDIATE_UPDATE 10 10 VPG_GENERIC11_IMMEDIATE_UPDATE 11 11 VPG_GENERIC12_IMMEDIATE_UPDATE 12 12 VPG_GENERIC13_IMMEDIATE_UPDATE 13 13 VPG_GENERIC14_IMMEDIATE_UPDATE 14 14 VPG_GENERIC0_IMMEDIATE_UPDATE_PENDING 16 16 VPG_GENERIC1_IMMEDIATE_UPDATE_PENDING 17 17 VPG_GENERIC2_IMMEDIATE_UPDATE_PENDING 18 18 VPG_GENERIC3_IMMEDIATE_UPDATE_PENDING 19 19 VPG_GENERIC4_IMMEDIATE_UPDATE_PENDING 20 20 VPG_GENERIC5_IMMEDIATE_UPDATE_PENDING 21 21 VPG_GENERIC6_IMMEDIATE_UPDATE_PENDING 22 22 VPG_GENERIC7_IMMEDIATE_UPDATE_PENDING 23 23 VPG_GENERIC8_IMMEDIATE_UPDATE_PENDING 24 24 VPG_GENERIC9_IMMEDIATE_UPDATE_PENDING 25 25 VPG_GENERIC10_IMMEDIATE_UPDATE_PENDING 26 26 VPG_GENERIC11_IMMEDIATE_UPDATE_PENDING 27 27 VPG_GENERIC12_IMMEDIATE_UPDATE_PENDING 28 28 VPG_GENERIC13_IMMEDIATE_UPDATE_PENDING 29 29 VPG_GENERIC14_IMMEDIATE_UPDATE_PENDING 30 30 regVPG2_VPG_GENERIC_STATUS 0 0x226c 3 0 2 VPG_GENERIC_LOCK_STATUS 0 0 VPG_GENERIC_CONFLICT_OCCURED 1 1 VPG_GENERIC_CONFLICT_CLR 4 4 regVPG2_VPG_MEM_PWR 0 0x226d 3 0 2 VPG_GSP_MEM_LIGHT_SLEEP_DIS 0 0 VPG_GSP_LIGHT_SLEEP_FORCE 4 4 VPG_GSP_MEM_PWR_STATE 8 8 regVPG2_VPG_ISRC1_2_ACCESS_CTRL 0 0x226e 1 0 2 VPG_ISRC1_2_DATA_INDEX 0 3 regVPG2_VPG_ISRC1_2_DATA 0 0x226f 4 0 2 VPG_ISRC_DATA_BYTE0 0 7 VPG_ISRC_DATA_BYTE1 8 15 VPG_ISRC_DATA_BYTE2 16 23 VPG_ISRC_DATA_BYTE3 24 31 regVPG2_VPG_MPEG_INFO0 0 0x2270 4 0 2 VPG_MPEG_INFO_CHECKSUM 0 7 VPG_MPEG_INFO_MB0 8 15 VPG_MPEG_INFO_MB1 16 23 VPG_MPEG_INFO_MB2 24 31 regVPG2_VPG_MPEG_INFO1 0 0x2271 4 0 2 VPG_MPEG_INFO_MB3 0 7 VPG_MPEG_INFO_MF 8 9 VPG_MPEG_INFO_FR 12 12 VPG_MPEG_INFO_UPDATE 16 16 regDME3_DME_CONTROL 0 0x2389 9 0 2 METADATA_HUBP_REQUESTOR_ID 0 2 METADATA_ENGINE_EN 4 4 METADATA_STREAM_TYPE 8 8 METADATA_DB_PENDING 12 12 METADATA_DB_TAKEN 13 13 METADATA_DB_TAKEN_CLR 16 16 METADATA_DB_DISABLE 20 20 METADATA_TRANSMISSION_MISSED 24 24 METADATA_TRANSMISSION_MISSED_CLR 25 25 regDME3_DME_MEMORY_CONTROL 0 0x238a 4 0 2 DME_MEM_PWR_FORCE 0 1 DME_MEM_PWR_DIS 4 4 DME_MEM_PWR_STATE 8 9 DME_MEM_DEFAULT_MEM_LOW_POWER_STATE 12 13 regVPG3_VPG_GENERIC_PACKET_ACCESS_CTRL 0 0x2368 1 0 2 VPG_GENERIC_DATA_INDEX 0 7 regVPG3_VPG_GENERIC_PACKET_DATA 0 0x2369 4 0 2 VPG_GENERIC_DATA_BYTE0 0 7 VPG_GENERIC_DATA_BYTE1 8 15 VPG_GENERIC_DATA_BYTE2 16 23 VPG_GENERIC_DATA_BYTE3 24 31 regVPG3_VPG_GSP_FRAME_UPDATE_CTRL 0 0x236a 30 0 2 VPG_GENERIC0_FRAME_UPDATE 0 0 VPG_GENERIC1_FRAME_UPDATE 1 1 VPG_GENERIC2_FRAME_UPDATE 2 2 VPG_GENERIC3_FRAME_UPDATE 3 3 VPG_GENERIC4_FRAME_UPDATE 4 4 VPG_GENERIC5_FRAME_UPDATE 5 5 VPG_GENERIC6_FRAME_UPDATE 6 6 VPG_GENERIC7_FRAME_UPDATE 7 7 VPG_GENERIC8_FRAME_UPDATE 8 8 VPG_GENERIC9_FRAME_UPDATE 9 9 VPG_GENERIC10_FRAME_UPDATE 10 10 VPG_GENERIC11_FRAME_UPDATE 11 11 VPG_GENERIC12_FRAME_UPDATE 12 12 VPG_GENERIC13_FRAME_UPDATE 13 13 VPG_GENERIC14_FRAME_UPDATE 14 14 VPG_GENERIC0_FRAME_UPDATE_PENDING 16 16 VPG_GENERIC1_FRAME_UPDATE_PENDING 17 17 VPG_GENERIC2_FRAME_UPDATE_PENDING 18 18 VPG_GENERIC3_FRAME_UPDATE_PENDING 19 19 VPG_GENERIC4_FRAME_UPDATE_PENDING 20 20 VPG_GENERIC5_FRAME_UPDATE_PENDING 21 21 VPG_GENERIC6_FRAME_UPDATE_PENDING 22 22 VPG_GENERIC7_FRAME_UPDATE_PENDING 23 23 VPG_GENERIC8_FRAME_UPDATE_PENDING 24 24 VPG_GENERIC9_FRAME_UPDATE_PENDING 25 25 VPG_GENERIC10_FRAME_UPDATE_PENDING 26 26 VPG_GENERIC11_FRAME_UPDATE_PENDING 27 27 VPG_GENERIC12_FRAME_UPDATE_PENDING 28 28 VPG_GENERIC13_FRAME_UPDATE_PENDING 29 29 VPG_GENERIC14_FRAME_UPDATE_PENDING 30 30 regVPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL 0 0x236b 30 0 2 VPG_GENERIC0_IMMEDIATE_UPDATE 0 0 VPG_GENERIC1_IMMEDIATE_UPDATE 1 1 VPG_GENERIC2_IMMEDIATE_UPDATE 2 2 VPG_GENERIC3_IMMEDIATE_UPDATE 3 3 VPG_GENERIC4_IMMEDIATE_UPDATE 4 4 VPG_GENERIC5_IMMEDIATE_UPDATE 5 5 VPG_GENERIC6_IMMEDIATE_UPDATE 6 6 VPG_GENERIC7_IMMEDIATE_UPDATE 7 7 VPG_GENERIC8_IMMEDIATE_UPDATE 8 8 VPG_GENERIC9_IMMEDIATE_UPDATE 9 9 VPG_GENERIC10_IMMEDIATE_UPDATE 10 10 VPG_GENERIC11_IMMEDIATE_UPDATE 11 11 VPG_GENERIC12_IMMEDIATE_UPDATE 12 12 VPG_GENERIC13_IMMEDIATE_UPDATE 13 13 VPG_GENERIC14_IMMEDIATE_UPDATE 14 14 VPG_GENERIC0_IMMEDIATE_UPDATE_PENDING 16 16 VPG_GENERIC1_IMMEDIATE_UPDATE_PENDING 17 17 VPG_GENERIC2_IMMEDIATE_UPDATE_PENDING 18 18 VPG_GENERIC3_IMMEDIATE_UPDATE_PENDING 19 19 VPG_GENERIC4_IMMEDIATE_UPDATE_PENDING 20 20 VPG_GENERIC5_IMMEDIATE_UPDATE_PENDING 21 21 VPG_GENERIC6_IMMEDIATE_UPDATE_PENDING 22 22 VPG_GENERIC7_IMMEDIATE_UPDATE_PENDING 23 23 VPG_GENERIC8_IMMEDIATE_UPDATE_PENDING 24 24 VPG_GENERIC9_IMMEDIATE_UPDATE_PENDING 25 25 VPG_GENERIC10_IMMEDIATE_UPDATE_PENDING 26 26 VPG_GENERIC11_IMMEDIATE_UPDATE_PENDING 27 27 VPG_GENERIC12_IMMEDIATE_UPDATE_PENDING 28 28 VPG_GENERIC13_IMMEDIATE_UPDATE_PENDING 29 29 VPG_GENERIC14_IMMEDIATE_UPDATE_PENDING 30 30 regVPG3_VPG_GENERIC_STATUS 0 0x236c 3 0 2 VPG_GENERIC_LOCK_STATUS 0 0 VPG_GENERIC_CONFLICT_OCCURED 1 1 VPG_GENERIC_CONFLICT_CLR 4 4 regVPG3_VPG_MEM_PWR 0 0x236d 3 0 2 VPG_GSP_MEM_LIGHT_SLEEP_DIS 0 0 VPG_GSP_LIGHT_SLEEP_FORCE 4 4 VPG_GSP_MEM_PWR_STATE 8 8 regVPG3_VPG_ISRC1_2_ACCESS_CTRL 0 0x236e 1 0 2 VPG_ISRC1_2_DATA_INDEX 0 3 regVPG3_VPG_ISRC1_2_DATA 0 0x236f 4 0 2 VPG_ISRC_DATA_BYTE0 0 7 VPG_ISRC_DATA_BYTE1 8 15 VPG_ISRC_DATA_BYTE2 16 23 VPG_ISRC_DATA_BYTE3 24 31 regVPG3_VPG_MPEG_INFO0 0 0x2370 4 0 2 VPG_MPEG_INFO_CHECKSUM 0 7 VPG_MPEG_INFO_MB0 8 15 VPG_MPEG_INFO_MB1 16 23 VPG_MPEG_INFO_MB2 24 31 regVPG3_VPG_MPEG_INFO1 0 0x2371 4 0 2 VPG_MPEG_INFO_MB3 0 7 VPG_MPEG_INFO_MF 8 9 VPG_MPEG_INFO_FR 12 12 VPG_MPEG_INFO_UPDATE 16 16 regDME4_DME_CONTROL 0 0x2489 9 0 2 METADATA_HUBP_REQUESTOR_ID 0 2 METADATA_ENGINE_EN 4 4 METADATA_STREAM_TYPE 8 8 METADATA_DB_PENDING 12 12 METADATA_DB_TAKEN 13 13 METADATA_DB_TAKEN_CLR 16 16 METADATA_DB_DISABLE 20 20 METADATA_TRANSMISSION_MISSED 24 24 METADATA_TRANSMISSION_MISSED_CLR 25 25 regDME4_DME_MEMORY_CONTROL 0 0x248a 4 0 2 DME_MEM_PWR_FORCE 0 1 DME_MEM_PWR_DIS 4 4 DME_MEM_PWR_STATE 8 9 DME_MEM_DEFAULT_MEM_LOW_POWER_STATE 12 13 regVPG4_VPG_GENERIC_PACKET_ACCESS_CTRL 0 0x2468 1 0 2 VPG_GENERIC_DATA_INDEX 0 7 regVPG4_VPG_GENERIC_PACKET_DATA 0 0x2469 4 0 2 VPG_GENERIC_DATA_BYTE0 0 7 VPG_GENERIC_DATA_BYTE1 8 15 VPG_GENERIC_DATA_BYTE2 16 23 VPG_GENERIC_DATA_BYTE3 24 31 regVPG4_VPG_GSP_FRAME_UPDATE_CTRL 0 0x246a 30 0 2 VPG_GENERIC0_FRAME_UPDATE 0 0 VPG_GENERIC1_FRAME_UPDATE 1 1 VPG_GENERIC2_FRAME_UPDATE 2 2 VPG_GENERIC3_FRAME_UPDATE 3 3 VPG_GENERIC4_FRAME_UPDATE 4 4 VPG_GENERIC5_FRAME_UPDATE 5 5 VPG_GENERIC6_FRAME_UPDATE 6 6 VPG_GENERIC7_FRAME_UPDATE 7 7 VPG_GENERIC8_FRAME_UPDATE 8 8 VPG_GENERIC9_FRAME_UPDATE 9 9 VPG_GENERIC10_FRAME_UPDATE 10 10 VPG_GENERIC11_FRAME_UPDATE 11 11 VPG_GENERIC12_FRAME_UPDATE 12 12 VPG_GENERIC13_FRAME_UPDATE 13 13 VPG_GENERIC14_FRAME_UPDATE 14 14 VPG_GENERIC0_FRAME_UPDATE_PENDING 16 16 VPG_GENERIC1_FRAME_UPDATE_PENDING 17 17 VPG_GENERIC2_FRAME_UPDATE_PENDING 18 18 VPG_GENERIC3_FRAME_UPDATE_PENDING 19 19 VPG_GENERIC4_FRAME_UPDATE_PENDING 20 20 VPG_GENERIC5_FRAME_UPDATE_PENDING 21 21 VPG_GENERIC6_FRAME_UPDATE_PENDING 22 22 VPG_GENERIC7_FRAME_UPDATE_PENDING 23 23 VPG_GENERIC8_FRAME_UPDATE_PENDING 24 24 VPG_GENERIC9_FRAME_UPDATE_PENDING 25 25 VPG_GENERIC10_FRAME_UPDATE_PENDING 26 26 VPG_GENERIC11_FRAME_UPDATE_PENDING 27 27 VPG_GENERIC12_FRAME_UPDATE_PENDING 28 28 VPG_GENERIC13_FRAME_UPDATE_PENDING 29 29 VPG_GENERIC14_FRAME_UPDATE_PENDING 30 30 regVPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL 0 0x246b 30 0 2 VPG_GENERIC0_IMMEDIATE_UPDATE 0 0 VPG_GENERIC1_IMMEDIATE_UPDATE 1 1 VPG_GENERIC2_IMMEDIATE_UPDATE 2 2 VPG_GENERIC3_IMMEDIATE_UPDATE 3 3 VPG_GENERIC4_IMMEDIATE_UPDATE 4 4 VPG_GENERIC5_IMMEDIATE_UPDATE 5 5 VPG_GENERIC6_IMMEDIATE_UPDATE 6 6 VPG_GENERIC7_IMMEDIATE_UPDATE 7 7 VPG_GENERIC8_IMMEDIATE_UPDATE 8 8 VPG_GENERIC9_IMMEDIATE_UPDATE 9 9 VPG_GENERIC10_IMMEDIATE_UPDATE 10 10 VPG_GENERIC11_IMMEDIATE_UPDATE 11 11 VPG_GENERIC12_IMMEDIATE_UPDATE 12 12 VPG_GENERIC13_IMMEDIATE_UPDATE 13 13 VPG_GENERIC14_IMMEDIATE_UPDATE 14 14 VPG_GENERIC0_IMMEDIATE_UPDATE_PENDING 16 16 VPG_GENERIC1_IMMEDIATE_UPDATE_PENDING 17 17 VPG_GENERIC2_IMMEDIATE_UPDATE_PENDING 18 18 VPG_GENERIC3_IMMEDIATE_UPDATE_PENDING 19 19 VPG_GENERIC4_IMMEDIATE_UPDATE_PENDING 20 20 VPG_GENERIC5_IMMEDIATE_UPDATE_PENDING 21 21 VPG_GENERIC6_IMMEDIATE_UPDATE_PENDING 22 22 VPG_GENERIC7_IMMEDIATE_UPDATE_PENDING 23 23 VPG_GENERIC8_IMMEDIATE_UPDATE_PENDING 24 24 VPG_GENERIC9_IMMEDIATE_UPDATE_PENDING 25 25 VPG_GENERIC10_IMMEDIATE_UPDATE_PENDING 26 26 VPG_GENERIC11_IMMEDIATE_UPDATE_PENDING 27 27 VPG_GENERIC12_IMMEDIATE_UPDATE_PENDING 28 28 VPG_GENERIC13_IMMEDIATE_UPDATE_PENDING 29 29 VPG_GENERIC14_IMMEDIATE_UPDATE_PENDING 30 30 regVPG4_VPG_GENERIC_STATUS 0 0x246c 3 0 2 VPG_GENERIC_LOCK_STATUS 0 0 VPG_GENERIC_CONFLICT_OCCURED 1 1 VPG_GENERIC_CONFLICT_CLR 4 4 regVPG4_VPG_MEM_PWR 0 0x246d 3 0 2 VPG_GSP_MEM_LIGHT_SLEEP_DIS 0 0 VPG_GSP_LIGHT_SLEEP_FORCE 4 4 VPG_GSP_MEM_PWR_STATE 8 8 regVPG4_VPG_ISRC1_2_ACCESS_CTRL 0 0x246e 1 0 2 VPG_ISRC1_2_DATA_INDEX 0 3 regVPG4_VPG_ISRC1_2_DATA 0 0x246f 4 0 2 VPG_ISRC_DATA_BYTE0 0 7 VPG_ISRC_DATA_BYTE1 8 15 VPG_ISRC_DATA_BYTE2 16 23 VPG_ISRC_DATA_BYTE3 24 31 regVPG4_VPG_MPEG_INFO0 0 0x2470 4 0 2 VPG_MPEG_INFO_CHECKSUM 0 7 VPG_MPEG_INFO_MB0 8 15 VPG_MPEG_INFO_MB1 16 23 VPG_MPEG_INFO_MB2 24 31 regVPG4_VPG_MPEG_INFO1 0 0x2471 4 0 2 VPG_MPEG_INFO_MB3 0 7 VPG_MPEG_INFO_MF 8 9 VPG_MPEG_INFO_FR 12 12 VPG_MPEG_INFO_UPDATE 16 16 regDP_AUX0_AUX_CONTROL 0 0x1f50 13 0 2 AUX_EN 0 0 AUX_RESET 4 4 AUX_RESET_DONE 5 5 AUX_LS_READ_EN 8 8 AUX_LS_UPDATE_DISABLE 12 12 AUX_IGNORE_HPD_DISCON 16 16 AUX_MODE_DET_EN 18 18 AUX_HPD_SEL 20 22 AUX_IMPCAL_REQ_EN 24 24 AUX_TEST_MODE 28 28 AUX_DEGLITCH_EN 29 29 SPARE_0 30 30 SPARE_1 31 31 regDP_AUX0_AUX_SW_CONTROL 0 0x1f51 4 0 2 AUX_SW_GO 0 0 AUX_LS_READ_TRIG 2 2 AUX_SW_START_DELAY 4 7 AUX_SW_WR_BYTES 16 20 regDP_AUX0_AUX_ARB_CONTROL 0 0x1f52 10 0 2 AUX_ARB_PRIORITY 0 1 AUX_REG_RW_CNTL_STATUS 2 3 AUX_NO_QUEUED_SW_GO 8 8 AUX_NO_QUEUED_LS_GO 10 10 AUX_SW_USE_AUX_REG_REQ 16 16 AUX_SW_PENDING_USE_AUX_REG_REQ 16 16 AUX_SW_DONE_USING_AUX_REG 17 17 AUX_DMCU_USE_AUX_REG_REQ 24 24 AUX_DMCU_PENDING_USE_AUX_REG_REQ 24 24 AUX_DMCU_DONE_USING_AUX_REG 25 25 regDP_AUX0_AUX_INTERRUPT_CONTROL 0 0x1f53 12 0 2 AUX_SW_DONE_INT 0 0 AUX_SW_DONE_ACK 1 1 AUX_SW_DONE_MASK 2 2 AUX_LS_DONE_INT 4 4 AUX_LS_DONE_ACK 5 5 AUX_LS_DONE_MASK 6 6 AUX_GTC_SYNC_LOCK_DONE_INT 8 8 AUX_GTC_SYNC_LOCK_DONE_ACK 9 9 AUX_GTC_SYNC_LOCK_DONE_INT_MASK 10 10 AUX_GTC_SYNC_ERROR_INT 12 12 AUX_GTC_SYNC_ERROR_ACK 13 13 AUX_GTC_SYNC_ERROR_INT_MASK 14 14 regDP_AUX0_AUX_SW_STATUS 0 0x1f54 18 0 2 AUX_SW_DONE 0 0 AUX_SW_REQ 1 1 AUX_SW_RX_TIMEOUT_STATE 4 6 AUX_SW_RX_TIMEOUT 7 7 AUX_SW_RX_OVERFLOW 8 8 AUX_SW_HPD_DISCON 9 9 AUX_SW_RX_PARTIAL_BYTE 10 10 AUX_SW_NON_AUX_MODE 11 11 AUX_SW_RX_MIN_COUNT_VIOL 12 12 AUX_SW_RX_INVALID_STOP 14 14 AUX_SW_RX_SYNC_INVALID_L 17 17 AUX_SW_RX_SYNC_INVALID_H 18 18 AUX_SW_RX_INVALID_START 19 19 AUX_SW_RX_RECV_NO_DET 20 20 AUX_SW_RX_RECV_INVALID_H 22 22 AUX_SW_RX_RECV_INVALID_L 23 23 AUX_SW_REPLY_BYTE_COUNT 24 28 AUX_ARB_STATUS 29 31 regDP_AUX0_AUX_LS_STATUS 0 0x1f55 20 0 2 AUX_LS_DONE 0 0 AUX_LS_REQ 1 1 AUX_LS_RX_TIMEOUT_STATE 4 6 AUX_LS_RX_TIMEOUT 7 7 AUX_LS_RX_OVERFLOW 8 8 AUX_LS_HPD_DISCON 9 9 AUX_LS_RX_PARTIAL_BYTE 10 10 AUX_LS_NON_AUX_MODE 11 11 AUX_LS_RX_MIN_COUNT_VIOL 12 12 AUX_LS_RX_INVALID_STOP 14 14 AUX_LS_RX_SYNC_INVALID_L 17 17 AUX_LS_RX_SYNC_INVALID_H 18 18 AUX_LS_RX_INVALID_START 19 19 AUX_LS_RX_RECV_NO_DET 20 20 AUX_LS_RX_RECV_INVALID_H 22 22 AUX_LS_RX_RECV_INVALID_L 23 23 AUX_LS_REPLY_BYTE_COUNT 24 28 AUX_LS_CP_IRQ 29 29 AUX_LS_UPDATED 30 30 AUX_LS_UPDATED_ACK 31 31 regDP_AUX0_AUX_SW_DATA 0 0x1f56 4 0 2 AUX_SW_DATA_RW 0 0 AUX_SW_DATA 8 15 AUX_SW_INDEX 16 20 AUX_SW_AUTOINCREMENT_DISABLE 31 31 regDP_AUX0_AUX_LS_DATA 0 0x1f57 2 0 2 AUX_LS_DATA 8 15 AUX_LS_INDEX 16 20 regDP_AUX0_AUX_DPHY_TX_REF_CONTROL 0 0x1f58 3 0 2 AUX_TX_REF_SEL 0 0 AUX_TX_RATE 4 5 AUX_TX_REF_DIV 16 24 regDP_AUX0_AUX_DPHY_TX_CONTROL 0 0x1f59 5 0 2 AUX_TX_PRECHARGE_LEN 0 3 AUX_TX_PRECHARGE_LEN_MUL 4 5 AUX_TX_OE_ASSERT_TIME 6 6 AUX_TX_PRECHARGE_SYMBOLS 8 13 AUX_MODE_DET_CHECK_DELAY 16 18 regDP_AUX0_AUX_DPHY_RX_CONTROL0 0 0x1f5a 9 0 2 AUX_RX_START_WINDOW 4 6 AUX_RX_RECEIVE_WINDOW 8 10 AUX_RX_HALF_SYM_DETECT_LEN 12 13 AUX_RX_TRANSITION_FILTER_EN 16 16 AUX_RX_ALLOW_BELOW_THRESHOLD_PHASE_DETECT 17 17 AUX_RX_ALLOW_BELOW_THRESHOLD_START 18 18 AUX_RX_ALLOW_BELOW_THRESHOLD_STOP 19 19 AUX_RX_PHASE_DETECT_LEN 20 21 AUX_RX_DETECTION_THRESHOLD 28 30 regDP_AUX0_AUX_DPHY_RX_CONTROL1 0 0x1f5b 3 0 2 AUX_RX_PRECHARGE_SKIP 0 7 AUX_RX_TIMEOUT_LEN 8 14 AUX_RX_TIMEOUT_LEN_MUL 15 16 regDP_AUX0_AUX_DPHY_TX_STATUS 0 0x1f5c 3 0 2 AUX_TX_ACTIVE 0 0 AUX_TX_STATE 4 6 AUX_TX_HALF_SYM_PERIOD 16 24 regDP_AUX0_AUX_DPHY_RX_STATUS 0 0x1f5d 4 0 2 AUX_RX_STATE 0 2 AUX_RX_SYNC_VALID_COUNT 8 12 AUX_RX_HALF_SYM_PERIOD_FRACT 16 20 AUX_RX_HALF_SYM_PERIOD 21 29 regDP_AUX0_AUX_GTC_SYNC_CONTROL 0 0x1f5e 9 0 2 AUX_GTC_SYNC_EN 0 0 AUX_GTC_SYNC_IMPCAL_EN 4 4 AUX_GTC_SYNC_IMPCAL_INTERVAL 8 11 AUX_GTC_SYNC_LOCK_ACQ_PERIOD 12 15 AUX_GTC_SYNC_LOCK_MAINT_PERIOD 16 18 AUX_GTC_SYNC_BLOCK_REQ 20 20 AUX_GTC_SYNC_INTERVAL_RESET_WINDOW 22 23 AUX_GTC_SYNC_OFFSET_CALC_MAX_ATTEMPT 24 25 AUX_GTC_SYNC_LOCK_ACQ_MAX_ATTEMPT 28 31 regDP_AUX0_AUX_GTC_SYNC_ERROR_CONTROL 0 0x1f5f 4 0 2 AUX_GTC_POTENTIAL_ERROR_THRESHOLD 0 4 AUX_GTC_DEFINITE_ERROR_THRESHOLD 8 12 AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_LEN 16 17 AUX_GTC_SYNC_NUM_RETRY_FOR_LOCK_MAINT 20 21 regDP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS 0 0x1f60 12 0 2 AUX_GTC_SYNC_LOCK_ACQ_COMPLETE 0 0 AUX_GTC_SYNC_LOCK_LOST 4 4 AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_OCCURRED 8 8 AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_STATE 9 12 AUX_GTC_SYNC_PHASE_ADJUST_TIME_VIOL 16 16 AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED 20 20 AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED_ACK 21 21 AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED 22 22 AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED_ACK 23 23 AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED 24 24 AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED_ACK 25 25 AUX_GTC_SYNC_CTRL_STATE 28 31 regDP_AUX0_AUX_GTC_SYNC_STATUS 0 0x1f61 19 0 2 AUX_GTC_SYNC_DONE 0 0 AUX_GTC_SYNC_REQ 1 1 AUX_GTC_SYNC_RX_TIMEOUT_STATE 4 6 AUX_GTC_SYNC_TIMEOUT 7 7 AUX_GTC_SYNC_RX_OVERFLOW 8 8 AUX_GTC_SYNC_HPD_DISCON 9 9 AUX_GTC_SYNC_RX_PARTIAL_BYTE 10 10 AUX_GTC_SYNC_NON_AUX_MODE 11 11 AUX_GTC_SYNC_RX_MIN_COUNT_VIOL 12 12 AUX_GTC_SYNC_RX_INVALID_STOP 14 14 AUX_GTC_SYNC_RX_SYNC_INVALID_L 17 17 AUX_GTC_SYNC_RX_SYNC_INVALID_H 18 18 AUX_GTC_SYNC_RX_INVALID_START 19 19 AUX_GTC_SYNC_RX_RECV_NO_DET 20 20 AUX_GTC_SYNC_RX_RECV_INVALID_H 22 22 AUX_GTC_SYNC_RX_RECV_INVALID_L 23 23 AUX_GTC_SYNC_REPLY_BYTE_COUNT 24 28 AUX_GTC_SYNC_NACKED 29 29 AUX_GTC_MASTER_REQ_BY_RX 30 30 regDP_AUX0_AUX_PHY_WAKE_CNTL 0 0x1f66 4 0 2 DP_AUX_PHY_WAKE_GO 0 0 DP_AUX_PHY_WAKE_PENDING 1 1 DP_AUX_PHY_WAKE_PRIORITY 2 2 DP_AUX_PHY_WAKE_ACK 3 3 regDP_AUX1_AUX_CONTROL 0 0x1f6c 13 0 2 AUX_EN 0 0 AUX_RESET 4 4 AUX_RESET_DONE 5 5 AUX_LS_READ_EN 8 8 AUX_LS_UPDATE_DISABLE 12 12 AUX_IGNORE_HPD_DISCON 16 16 AUX_MODE_DET_EN 18 18 AUX_HPD_SEL 20 22 AUX_IMPCAL_REQ_EN 24 24 AUX_TEST_MODE 28 28 AUX_DEGLITCH_EN 29 29 SPARE_0 30 30 SPARE_1 31 31 regDP_AUX1_AUX_SW_CONTROL 0 0x1f6d 4 0 2 AUX_SW_GO 0 0 AUX_LS_READ_TRIG 2 2 AUX_SW_START_DELAY 4 7 AUX_SW_WR_BYTES 16 20 regDP_AUX1_AUX_ARB_CONTROL 0 0x1f6e 10 0 2 AUX_ARB_PRIORITY 0 1 AUX_REG_RW_CNTL_STATUS 2 3 AUX_NO_QUEUED_SW_GO 8 8 AUX_NO_QUEUED_LS_GO 10 10 AUX_SW_USE_AUX_REG_REQ 16 16 AUX_SW_PENDING_USE_AUX_REG_REQ 16 16 AUX_SW_DONE_USING_AUX_REG 17 17 AUX_DMCU_USE_AUX_REG_REQ 24 24 AUX_DMCU_PENDING_USE_AUX_REG_REQ 24 24 AUX_DMCU_DONE_USING_AUX_REG 25 25 regDP_AUX1_AUX_INTERRUPT_CONTROL 0 0x1f6f 12 0 2 AUX_SW_DONE_INT 0 0 AUX_SW_DONE_ACK 1 1 AUX_SW_DONE_MASK 2 2 AUX_LS_DONE_INT 4 4 AUX_LS_DONE_ACK 5 5 AUX_LS_DONE_MASK 6 6 AUX_GTC_SYNC_LOCK_DONE_INT 8 8 AUX_GTC_SYNC_LOCK_DONE_ACK 9 9 AUX_GTC_SYNC_LOCK_DONE_INT_MASK 10 10 AUX_GTC_SYNC_ERROR_INT 12 12 AUX_GTC_SYNC_ERROR_ACK 13 13 AUX_GTC_SYNC_ERROR_INT_MASK 14 14 regDP_AUX1_AUX_SW_STATUS 0 0x1f70 18 0 2 AUX_SW_DONE 0 0 AUX_SW_REQ 1 1 AUX_SW_RX_TIMEOUT_STATE 4 6 AUX_SW_RX_TIMEOUT 7 7 AUX_SW_RX_OVERFLOW 8 8 AUX_SW_HPD_DISCON 9 9 AUX_SW_RX_PARTIAL_BYTE 10 10 AUX_SW_NON_AUX_MODE 11 11 AUX_SW_RX_MIN_COUNT_VIOL 12 12 AUX_SW_RX_INVALID_STOP 14 14 AUX_SW_RX_SYNC_INVALID_L 17 17 AUX_SW_RX_SYNC_INVALID_H 18 18 AUX_SW_RX_INVALID_START 19 19 AUX_SW_RX_RECV_NO_DET 20 20 AUX_SW_RX_RECV_INVALID_H 22 22 AUX_SW_RX_RECV_INVALID_L 23 23 AUX_SW_REPLY_BYTE_COUNT 24 28 AUX_ARB_STATUS 29 31 regDP_AUX1_AUX_LS_STATUS 0 0x1f71 20 0 2 AUX_LS_DONE 0 0 AUX_LS_REQ 1 1 AUX_LS_RX_TIMEOUT_STATE 4 6 AUX_LS_RX_TIMEOUT 7 7 AUX_LS_RX_OVERFLOW 8 8 AUX_LS_HPD_DISCON 9 9 AUX_LS_RX_PARTIAL_BYTE 10 10 AUX_LS_NON_AUX_MODE 11 11 AUX_LS_RX_MIN_COUNT_VIOL 12 12 AUX_LS_RX_INVALID_STOP 14 14 AUX_LS_RX_SYNC_INVALID_L 17 17 AUX_LS_RX_SYNC_INVALID_H 18 18 AUX_LS_RX_INVALID_START 19 19 AUX_LS_RX_RECV_NO_DET 20 20 AUX_LS_RX_RECV_INVALID_H 22 22 AUX_LS_RX_RECV_INVALID_L 23 23 AUX_LS_REPLY_BYTE_COUNT 24 28 AUX_LS_CP_IRQ 29 29 AUX_LS_UPDATED 30 30 AUX_LS_UPDATED_ACK 31 31 regDP_AUX1_AUX_SW_DATA 0 0x1f72 4 0 2 AUX_SW_DATA_RW 0 0 AUX_SW_DATA 8 15 AUX_SW_INDEX 16 20 AUX_SW_AUTOINCREMENT_DISABLE 31 31 regDP_AUX1_AUX_LS_DATA 0 0x1f73 2 0 2 AUX_LS_DATA 8 15 AUX_LS_INDEX 16 20 regDP_AUX1_AUX_DPHY_TX_REF_CONTROL 0 0x1f74 3 0 2 AUX_TX_REF_SEL 0 0 AUX_TX_RATE 4 5 AUX_TX_REF_DIV 16 24 regDP_AUX1_AUX_DPHY_TX_CONTROL 0 0x1f75 5 0 2 AUX_TX_PRECHARGE_LEN 0 3 AUX_TX_PRECHARGE_LEN_MUL 4 5 AUX_TX_OE_ASSERT_TIME 6 6 AUX_TX_PRECHARGE_SYMBOLS 8 13 AUX_MODE_DET_CHECK_DELAY 16 18 regDP_AUX1_AUX_DPHY_RX_CONTROL0 0 0x1f76 9 0 2 AUX_RX_START_WINDOW 4 6 AUX_RX_RECEIVE_WINDOW 8 10 AUX_RX_HALF_SYM_DETECT_LEN 12 13 AUX_RX_TRANSITION_FILTER_EN 16 16 AUX_RX_ALLOW_BELOW_THRESHOLD_PHASE_DETECT 17 17 AUX_RX_ALLOW_BELOW_THRESHOLD_START 18 18 AUX_RX_ALLOW_BELOW_THRESHOLD_STOP 19 19 AUX_RX_PHASE_DETECT_LEN 20 21 AUX_RX_DETECTION_THRESHOLD 28 30 regDP_AUX1_AUX_DPHY_RX_CONTROL1 0 0x1f77 3 0 2 AUX_RX_PRECHARGE_SKIP 0 7 AUX_RX_TIMEOUT_LEN 8 14 AUX_RX_TIMEOUT_LEN_MUL 15 16 regDP_AUX1_AUX_DPHY_TX_STATUS 0 0x1f78 3 0 2 AUX_TX_ACTIVE 0 0 AUX_TX_STATE 4 6 AUX_TX_HALF_SYM_PERIOD 16 24 regDP_AUX1_AUX_DPHY_RX_STATUS 0 0x1f79 4 0 2 AUX_RX_STATE 0 2 AUX_RX_SYNC_VALID_COUNT 8 12 AUX_RX_HALF_SYM_PERIOD_FRACT 16 20 AUX_RX_HALF_SYM_PERIOD 21 29 regDP_AUX1_AUX_GTC_SYNC_CONTROL 0 0x1f7a 9 0 2 AUX_GTC_SYNC_EN 0 0 AUX_GTC_SYNC_IMPCAL_EN 4 4 AUX_GTC_SYNC_IMPCAL_INTERVAL 8 11 AUX_GTC_SYNC_LOCK_ACQ_PERIOD 12 15 AUX_GTC_SYNC_LOCK_MAINT_PERIOD 16 18 AUX_GTC_SYNC_BLOCK_REQ 20 20 AUX_GTC_SYNC_INTERVAL_RESET_WINDOW 22 23 AUX_GTC_SYNC_OFFSET_CALC_MAX_ATTEMPT 24 25 AUX_GTC_SYNC_LOCK_ACQ_MAX_ATTEMPT 28 31 regDP_AUX1_AUX_GTC_SYNC_ERROR_CONTROL 0 0x1f7b 4 0 2 AUX_GTC_POTENTIAL_ERROR_THRESHOLD 0 4 AUX_GTC_DEFINITE_ERROR_THRESHOLD 8 12 AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_LEN 16 17 AUX_GTC_SYNC_NUM_RETRY_FOR_LOCK_MAINT 20 21 regDP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS 0 0x1f7c 12 0 2 AUX_GTC_SYNC_LOCK_ACQ_COMPLETE 0 0 AUX_GTC_SYNC_LOCK_LOST 4 4 AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_OCCURRED 8 8 AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_STATE 9 12 AUX_GTC_SYNC_PHASE_ADJUST_TIME_VIOL 16 16 AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED 20 20 AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED_ACK 21 21 AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED 22 22 AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED_ACK 23 23 AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED 24 24 AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED_ACK 25 25 AUX_GTC_SYNC_CTRL_STATE 28 31 regDP_AUX1_AUX_GTC_SYNC_STATUS 0 0x1f7d 19 0 2 AUX_GTC_SYNC_DONE 0 0 AUX_GTC_SYNC_REQ 1 1 AUX_GTC_SYNC_RX_TIMEOUT_STATE 4 6 AUX_GTC_SYNC_TIMEOUT 7 7 AUX_GTC_SYNC_RX_OVERFLOW 8 8 AUX_GTC_SYNC_HPD_DISCON 9 9 AUX_GTC_SYNC_RX_PARTIAL_BYTE 10 10 AUX_GTC_SYNC_NON_AUX_MODE 11 11 AUX_GTC_SYNC_RX_MIN_COUNT_VIOL 12 12 AUX_GTC_SYNC_RX_INVALID_STOP 14 14 AUX_GTC_SYNC_RX_SYNC_INVALID_L 17 17 AUX_GTC_SYNC_RX_SYNC_INVALID_H 18 18 AUX_GTC_SYNC_RX_INVALID_START 19 19 AUX_GTC_SYNC_RX_RECV_NO_DET 20 20 AUX_GTC_SYNC_RX_RECV_INVALID_H 22 22 AUX_GTC_SYNC_RX_RECV_INVALID_L 23 23 AUX_GTC_SYNC_REPLY_BYTE_COUNT 24 28 AUX_GTC_SYNC_NACKED 29 29 AUX_GTC_MASTER_REQ_BY_RX 30 30 regDP_AUX1_AUX_PHY_WAKE_CNTL 0 0x1f82 4 0 2 DP_AUX_PHY_WAKE_GO 0 0 DP_AUX_PHY_WAKE_PENDING 1 1 DP_AUX_PHY_WAKE_PRIORITY 2 2 DP_AUX_PHY_WAKE_ACK 3 3 regDP_AUX2_AUX_CONTROL 0 0x1f88 13 0 2 AUX_EN 0 0 AUX_RESET 4 4 AUX_RESET_DONE 5 5 AUX_LS_READ_EN 8 8 AUX_LS_UPDATE_DISABLE 12 12 AUX_IGNORE_HPD_DISCON 16 16 AUX_MODE_DET_EN 18 18 AUX_HPD_SEL 20 22 AUX_IMPCAL_REQ_EN 24 24 AUX_TEST_MODE 28 28 AUX_DEGLITCH_EN 29 29 SPARE_0 30 30 SPARE_1 31 31 regDP_AUX2_AUX_SW_CONTROL 0 0x1f89 4 0 2 AUX_SW_GO 0 0 AUX_LS_READ_TRIG 2 2 AUX_SW_START_DELAY 4 7 AUX_SW_WR_BYTES 16 20 regDP_AUX2_AUX_ARB_CONTROL 0 0x1f8a 10 0 2 AUX_ARB_PRIORITY 0 1 AUX_REG_RW_CNTL_STATUS 2 3 AUX_NO_QUEUED_SW_GO 8 8 AUX_NO_QUEUED_LS_GO 10 10 AUX_SW_USE_AUX_REG_REQ 16 16 AUX_SW_PENDING_USE_AUX_REG_REQ 16 16 AUX_SW_DONE_USING_AUX_REG 17 17 AUX_DMCU_USE_AUX_REG_REQ 24 24 AUX_DMCU_PENDING_USE_AUX_REG_REQ 24 24 AUX_DMCU_DONE_USING_AUX_REG 25 25 regDP_AUX2_AUX_INTERRUPT_CONTROL 0 0x1f8b 12 0 2 AUX_SW_DONE_INT 0 0 AUX_SW_DONE_ACK 1 1 AUX_SW_DONE_MASK 2 2 AUX_LS_DONE_INT 4 4 AUX_LS_DONE_ACK 5 5 AUX_LS_DONE_MASK 6 6 AUX_GTC_SYNC_LOCK_DONE_INT 8 8 AUX_GTC_SYNC_LOCK_DONE_ACK 9 9 AUX_GTC_SYNC_LOCK_DONE_INT_MASK 10 10 AUX_GTC_SYNC_ERROR_INT 12 12 AUX_GTC_SYNC_ERROR_ACK 13 13 AUX_GTC_SYNC_ERROR_INT_MASK 14 14 regDP_AUX2_AUX_SW_STATUS 0 0x1f8c 18 0 2 AUX_SW_DONE 0 0 AUX_SW_REQ 1 1 AUX_SW_RX_TIMEOUT_STATE 4 6 AUX_SW_RX_TIMEOUT 7 7 AUX_SW_RX_OVERFLOW 8 8 AUX_SW_HPD_DISCON 9 9 AUX_SW_RX_PARTIAL_BYTE 10 10 AUX_SW_NON_AUX_MODE 11 11 AUX_SW_RX_MIN_COUNT_VIOL 12 12 AUX_SW_RX_INVALID_STOP 14 14 AUX_SW_RX_SYNC_INVALID_L 17 17 AUX_SW_RX_SYNC_INVALID_H 18 18 AUX_SW_RX_INVALID_START 19 19 AUX_SW_RX_RECV_NO_DET 20 20 AUX_SW_RX_RECV_INVALID_H 22 22 AUX_SW_RX_RECV_INVALID_L 23 23 AUX_SW_REPLY_BYTE_COUNT 24 28 AUX_ARB_STATUS 29 31 regDP_AUX2_AUX_LS_STATUS 0 0x1f8d 20 0 2 AUX_LS_DONE 0 0 AUX_LS_REQ 1 1 AUX_LS_RX_TIMEOUT_STATE 4 6 AUX_LS_RX_TIMEOUT 7 7 AUX_LS_RX_OVERFLOW 8 8 AUX_LS_HPD_DISCON 9 9 AUX_LS_RX_PARTIAL_BYTE 10 10 AUX_LS_NON_AUX_MODE 11 11 AUX_LS_RX_MIN_COUNT_VIOL 12 12 AUX_LS_RX_INVALID_STOP 14 14 AUX_LS_RX_SYNC_INVALID_L 17 17 AUX_LS_RX_SYNC_INVALID_H 18 18 AUX_LS_RX_INVALID_START 19 19 AUX_LS_RX_RECV_NO_DET 20 20 AUX_LS_RX_RECV_INVALID_H 22 22 AUX_LS_RX_RECV_INVALID_L 23 23 AUX_LS_REPLY_BYTE_COUNT 24 28 AUX_LS_CP_IRQ 29 29 AUX_LS_UPDATED 30 30 AUX_LS_UPDATED_ACK 31 31 regDP_AUX2_AUX_SW_DATA 0 0x1f8e 4 0 2 AUX_SW_DATA_RW 0 0 AUX_SW_DATA 8 15 AUX_SW_INDEX 16 20 AUX_SW_AUTOINCREMENT_DISABLE 31 31 regDP_AUX2_AUX_LS_DATA 0 0x1f8f 2 0 2 AUX_LS_DATA 8 15 AUX_LS_INDEX 16 20 regDP_AUX2_AUX_DPHY_TX_REF_CONTROL 0 0x1f90 3 0 2 AUX_TX_REF_SEL 0 0 AUX_TX_RATE 4 5 AUX_TX_REF_DIV 16 24 regDP_AUX2_AUX_DPHY_TX_CONTROL 0 0x1f91 5 0 2 AUX_TX_PRECHARGE_LEN 0 3 AUX_TX_PRECHARGE_LEN_MUL 4 5 AUX_TX_OE_ASSERT_TIME 6 6 AUX_TX_PRECHARGE_SYMBOLS 8 13 AUX_MODE_DET_CHECK_DELAY 16 18 regDP_AUX2_AUX_DPHY_RX_CONTROL0 0 0x1f92 9 0 2 AUX_RX_START_WINDOW 4 6 AUX_RX_RECEIVE_WINDOW 8 10 AUX_RX_HALF_SYM_DETECT_LEN 12 13 AUX_RX_TRANSITION_FILTER_EN 16 16 AUX_RX_ALLOW_BELOW_THRESHOLD_PHASE_DETECT 17 17 AUX_RX_ALLOW_BELOW_THRESHOLD_START 18 18 AUX_RX_ALLOW_BELOW_THRESHOLD_STOP 19 19 AUX_RX_PHASE_DETECT_LEN 20 21 AUX_RX_DETECTION_THRESHOLD 28 30 regDP_AUX2_AUX_DPHY_RX_CONTROL1 0 0x1f93 3 0 2 AUX_RX_PRECHARGE_SKIP 0 7 AUX_RX_TIMEOUT_LEN 8 14 AUX_RX_TIMEOUT_LEN_MUL 15 16 regDP_AUX2_AUX_DPHY_TX_STATUS 0 0x1f94 3 0 2 AUX_TX_ACTIVE 0 0 AUX_TX_STATE 4 6 AUX_TX_HALF_SYM_PERIOD 16 24 regDP_AUX2_AUX_DPHY_RX_STATUS 0 0x1f95 4 0 2 AUX_RX_STATE 0 2 AUX_RX_SYNC_VALID_COUNT 8 12 AUX_RX_HALF_SYM_PERIOD_FRACT 16 20 AUX_RX_HALF_SYM_PERIOD 21 29 regDP_AUX2_AUX_GTC_SYNC_CONTROL 0 0x1f96 9 0 2 AUX_GTC_SYNC_EN 0 0 AUX_GTC_SYNC_IMPCAL_EN 4 4 AUX_GTC_SYNC_IMPCAL_INTERVAL 8 11 AUX_GTC_SYNC_LOCK_ACQ_PERIOD 12 15 AUX_GTC_SYNC_LOCK_MAINT_PERIOD 16 18 AUX_GTC_SYNC_BLOCK_REQ 20 20 AUX_GTC_SYNC_INTERVAL_RESET_WINDOW 22 23 AUX_GTC_SYNC_OFFSET_CALC_MAX_ATTEMPT 24 25 AUX_GTC_SYNC_LOCK_ACQ_MAX_ATTEMPT 28 31 regDP_AUX2_AUX_GTC_SYNC_ERROR_CONTROL 0 0x1f97 4 0 2 AUX_GTC_POTENTIAL_ERROR_THRESHOLD 0 4 AUX_GTC_DEFINITE_ERROR_THRESHOLD 8 12 AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_LEN 16 17 AUX_GTC_SYNC_NUM_RETRY_FOR_LOCK_MAINT 20 21 regDP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS 0 0x1f98 12 0 2 AUX_GTC_SYNC_LOCK_ACQ_COMPLETE 0 0 AUX_GTC_SYNC_LOCK_LOST 4 4 AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_OCCURRED 8 8 AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_STATE 9 12 AUX_GTC_SYNC_PHASE_ADJUST_TIME_VIOL 16 16 AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED 20 20 AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED_ACK 21 21 AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED 22 22 AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED_ACK 23 23 AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED 24 24 AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED_ACK 25 25 AUX_GTC_SYNC_CTRL_STATE 28 31 regDP_AUX2_AUX_GTC_SYNC_STATUS 0 0x1f99 19 0 2 AUX_GTC_SYNC_DONE 0 0 AUX_GTC_SYNC_REQ 1 1 AUX_GTC_SYNC_RX_TIMEOUT_STATE 4 6 AUX_GTC_SYNC_TIMEOUT 7 7 AUX_GTC_SYNC_RX_OVERFLOW 8 8 AUX_GTC_SYNC_HPD_DISCON 9 9 AUX_GTC_SYNC_RX_PARTIAL_BYTE 10 10 AUX_GTC_SYNC_NON_AUX_MODE 11 11 AUX_GTC_SYNC_RX_MIN_COUNT_VIOL 12 12 AUX_GTC_SYNC_RX_INVALID_STOP 14 14 AUX_GTC_SYNC_RX_SYNC_INVALID_L 17 17 AUX_GTC_SYNC_RX_SYNC_INVALID_H 18 18 AUX_GTC_SYNC_RX_INVALID_START 19 19 AUX_GTC_SYNC_RX_RECV_NO_DET 20 20 AUX_GTC_SYNC_RX_RECV_INVALID_H 22 22 AUX_GTC_SYNC_RX_RECV_INVALID_L 23 23 AUX_GTC_SYNC_REPLY_BYTE_COUNT 24 28 AUX_GTC_SYNC_NACKED 29 29 AUX_GTC_MASTER_REQ_BY_RX 30 30 regDP_AUX2_AUX_PHY_WAKE_CNTL 0 0x1f9e 4 0 2 DP_AUX_PHY_WAKE_GO 0 0 DP_AUX_PHY_WAKE_PENDING 1 1 DP_AUX_PHY_WAKE_PRIORITY 2 2 DP_AUX_PHY_WAKE_ACK 3 3 regDP_AUX3_AUX_CONTROL 0 0x1fa4 13 0 2 AUX_EN 0 0 AUX_RESET 4 4 AUX_RESET_DONE 5 5 AUX_LS_READ_EN 8 8 AUX_LS_UPDATE_DISABLE 12 12 AUX_IGNORE_HPD_DISCON 16 16 AUX_MODE_DET_EN 18 18 AUX_HPD_SEL 20 22 AUX_IMPCAL_REQ_EN 24 24 AUX_TEST_MODE 28 28 AUX_DEGLITCH_EN 29 29 SPARE_0 30 30 SPARE_1 31 31 regDP_AUX3_AUX_SW_CONTROL 0 0x1fa5 4 0 2 AUX_SW_GO 0 0 AUX_LS_READ_TRIG 2 2 AUX_SW_START_DELAY 4 7 AUX_SW_WR_BYTES 16 20 regDP_AUX3_AUX_ARB_CONTROL 0 0x1fa6 10 0 2 AUX_ARB_PRIORITY 0 1 AUX_REG_RW_CNTL_STATUS 2 3 AUX_NO_QUEUED_SW_GO 8 8 AUX_NO_QUEUED_LS_GO 10 10 AUX_SW_USE_AUX_REG_REQ 16 16 AUX_SW_PENDING_USE_AUX_REG_REQ 16 16 AUX_SW_DONE_USING_AUX_REG 17 17 AUX_DMCU_USE_AUX_REG_REQ 24 24 AUX_DMCU_PENDING_USE_AUX_REG_REQ 24 24 AUX_DMCU_DONE_USING_AUX_REG 25 25 regDP_AUX3_AUX_INTERRUPT_CONTROL 0 0x1fa7 12 0 2 AUX_SW_DONE_INT 0 0 AUX_SW_DONE_ACK 1 1 AUX_SW_DONE_MASK 2 2 AUX_LS_DONE_INT 4 4 AUX_LS_DONE_ACK 5 5 AUX_LS_DONE_MASK 6 6 AUX_GTC_SYNC_LOCK_DONE_INT 8 8 AUX_GTC_SYNC_LOCK_DONE_ACK 9 9 AUX_GTC_SYNC_LOCK_DONE_INT_MASK 10 10 AUX_GTC_SYNC_ERROR_INT 12 12 AUX_GTC_SYNC_ERROR_ACK 13 13 AUX_GTC_SYNC_ERROR_INT_MASK 14 14 regDP_AUX3_AUX_SW_STATUS 0 0x1fa8 18 0 2 AUX_SW_DONE 0 0 AUX_SW_REQ 1 1 AUX_SW_RX_TIMEOUT_STATE 4 6 AUX_SW_RX_TIMEOUT 7 7 AUX_SW_RX_OVERFLOW 8 8 AUX_SW_HPD_DISCON 9 9 AUX_SW_RX_PARTIAL_BYTE 10 10 AUX_SW_NON_AUX_MODE 11 11 AUX_SW_RX_MIN_COUNT_VIOL 12 12 AUX_SW_RX_INVALID_STOP 14 14 AUX_SW_RX_SYNC_INVALID_L 17 17 AUX_SW_RX_SYNC_INVALID_H 18 18 AUX_SW_RX_INVALID_START 19 19 AUX_SW_RX_RECV_NO_DET 20 20 AUX_SW_RX_RECV_INVALID_H 22 22 AUX_SW_RX_RECV_INVALID_L 23 23 AUX_SW_REPLY_BYTE_COUNT 24 28 AUX_ARB_STATUS 29 31 regDP_AUX3_AUX_LS_STATUS 0 0x1fa9 20 0 2 AUX_LS_DONE 0 0 AUX_LS_REQ 1 1 AUX_LS_RX_TIMEOUT_STATE 4 6 AUX_LS_RX_TIMEOUT 7 7 AUX_LS_RX_OVERFLOW 8 8 AUX_LS_HPD_DISCON 9 9 AUX_LS_RX_PARTIAL_BYTE 10 10 AUX_LS_NON_AUX_MODE 11 11 AUX_LS_RX_MIN_COUNT_VIOL 12 12 AUX_LS_RX_INVALID_STOP 14 14 AUX_LS_RX_SYNC_INVALID_L 17 17 AUX_LS_RX_SYNC_INVALID_H 18 18 AUX_LS_RX_INVALID_START 19 19 AUX_LS_RX_RECV_NO_DET 20 20 AUX_LS_RX_RECV_INVALID_H 22 22 AUX_LS_RX_RECV_INVALID_L 23 23 AUX_LS_REPLY_BYTE_COUNT 24 28 AUX_LS_CP_IRQ 29 29 AUX_LS_UPDATED 30 30 AUX_LS_UPDATED_ACK 31 31 regDP_AUX3_AUX_SW_DATA 0 0x1faa 4 0 2 AUX_SW_DATA_RW 0 0 AUX_SW_DATA 8 15 AUX_SW_INDEX 16 20 AUX_SW_AUTOINCREMENT_DISABLE 31 31 regDP_AUX3_AUX_LS_DATA 0 0x1fab 2 0 2 AUX_LS_DATA 8 15 AUX_LS_INDEX 16 20 regDP_AUX3_AUX_DPHY_TX_REF_CONTROL 0 0x1fac 3 0 2 AUX_TX_REF_SEL 0 0 AUX_TX_RATE 4 5 AUX_TX_REF_DIV 16 24 regDP_AUX3_AUX_DPHY_TX_CONTROL 0 0x1fad 5 0 2 AUX_TX_PRECHARGE_LEN 0 3 AUX_TX_PRECHARGE_LEN_MUL 4 5 AUX_TX_OE_ASSERT_TIME 6 6 AUX_TX_PRECHARGE_SYMBOLS 8 13 AUX_MODE_DET_CHECK_DELAY 16 18 regDP_AUX3_AUX_DPHY_RX_CONTROL0 0 0x1fae 9 0 2 AUX_RX_START_WINDOW 4 6 AUX_RX_RECEIVE_WINDOW 8 10 AUX_RX_HALF_SYM_DETECT_LEN 12 13 AUX_RX_TRANSITION_FILTER_EN 16 16 AUX_RX_ALLOW_BELOW_THRESHOLD_PHASE_DETECT 17 17 AUX_RX_ALLOW_BELOW_THRESHOLD_START 18 18 AUX_RX_ALLOW_BELOW_THRESHOLD_STOP 19 19 AUX_RX_PHASE_DETECT_LEN 20 21 AUX_RX_DETECTION_THRESHOLD 28 30 regDP_AUX3_AUX_DPHY_RX_CONTROL1 0 0x1faf 3 0 2 AUX_RX_PRECHARGE_SKIP 0 7 AUX_RX_TIMEOUT_LEN 8 14 AUX_RX_TIMEOUT_LEN_MUL 15 16 regDP_AUX3_AUX_DPHY_TX_STATUS 0 0x1fb0 3 0 2 AUX_TX_ACTIVE 0 0 AUX_TX_STATE 4 6 AUX_TX_HALF_SYM_PERIOD 16 24 regDP_AUX3_AUX_DPHY_RX_STATUS 0 0x1fb1 4 0 2 AUX_RX_STATE 0 2 AUX_RX_SYNC_VALID_COUNT 8 12 AUX_RX_HALF_SYM_PERIOD_FRACT 16 20 AUX_RX_HALF_SYM_PERIOD 21 29 regDP_AUX3_AUX_GTC_SYNC_CONTROL 0 0x1fb2 9 0 2 AUX_GTC_SYNC_EN 0 0 AUX_GTC_SYNC_IMPCAL_EN 4 4 AUX_GTC_SYNC_IMPCAL_INTERVAL 8 11 AUX_GTC_SYNC_LOCK_ACQ_PERIOD 12 15 AUX_GTC_SYNC_LOCK_MAINT_PERIOD 16 18 AUX_GTC_SYNC_BLOCK_REQ 20 20 AUX_GTC_SYNC_INTERVAL_RESET_WINDOW 22 23 AUX_GTC_SYNC_OFFSET_CALC_MAX_ATTEMPT 24 25 AUX_GTC_SYNC_LOCK_ACQ_MAX_ATTEMPT 28 31 regDP_AUX3_AUX_GTC_SYNC_ERROR_CONTROL 0 0x1fb3 4 0 2 AUX_GTC_POTENTIAL_ERROR_THRESHOLD 0 4 AUX_GTC_DEFINITE_ERROR_THRESHOLD 8 12 AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_LEN 16 17 AUX_GTC_SYNC_NUM_RETRY_FOR_LOCK_MAINT 20 21 regDP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS 0 0x1fb4 12 0 2 AUX_GTC_SYNC_LOCK_ACQ_COMPLETE 0 0 AUX_GTC_SYNC_LOCK_LOST 4 4 AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_OCCURRED 8 8 AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_STATE 9 12 AUX_GTC_SYNC_PHASE_ADJUST_TIME_VIOL 16 16 AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED 20 20 AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED_ACK 21 21 AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED 22 22 AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED_ACK 23 23 AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED 24 24 AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED_ACK 25 25 AUX_GTC_SYNC_CTRL_STATE 28 31 regDP_AUX3_AUX_GTC_SYNC_STATUS 0 0x1fb5 19 0 2 AUX_GTC_SYNC_DONE 0 0 AUX_GTC_SYNC_REQ 1 1 AUX_GTC_SYNC_RX_TIMEOUT_STATE 4 6 AUX_GTC_SYNC_TIMEOUT 7 7 AUX_GTC_SYNC_RX_OVERFLOW 8 8 AUX_GTC_SYNC_HPD_DISCON 9 9 AUX_GTC_SYNC_RX_PARTIAL_BYTE 10 10 AUX_GTC_SYNC_NON_AUX_MODE 11 11 AUX_GTC_SYNC_RX_MIN_COUNT_VIOL 12 12 AUX_GTC_SYNC_RX_INVALID_STOP 14 14 AUX_GTC_SYNC_RX_SYNC_INVALID_L 17 17 AUX_GTC_SYNC_RX_SYNC_INVALID_H 18 18 AUX_GTC_SYNC_RX_INVALID_START 19 19 AUX_GTC_SYNC_RX_RECV_NO_DET 20 20 AUX_GTC_SYNC_RX_RECV_INVALID_H 22 22 AUX_GTC_SYNC_RX_RECV_INVALID_L 23 23 AUX_GTC_SYNC_REPLY_BYTE_COUNT 24 28 AUX_GTC_SYNC_NACKED 29 29 AUX_GTC_MASTER_REQ_BY_RX 30 30 regDP_AUX3_AUX_PHY_WAKE_CNTL 0 0x1fba 4 0 2 DP_AUX_PHY_WAKE_GO 0 0 DP_AUX_PHY_WAKE_PENDING 1 1 DP_AUX_PHY_WAKE_PRIORITY 2 2 DP_AUX_PHY_WAKE_ACK 3 3 regDP_AUX4_AUX_CONTROL 0 0x1fc0 13 0 2 AUX_EN 0 0 AUX_RESET 4 4 AUX_RESET_DONE 5 5 AUX_LS_READ_EN 8 8 AUX_LS_UPDATE_DISABLE 12 12 AUX_IGNORE_HPD_DISCON 16 16 AUX_MODE_DET_EN 18 18 AUX_HPD_SEL 20 22 AUX_IMPCAL_REQ_EN 24 24 AUX_TEST_MODE 28 28 AUX_DEGLITCH_EN 29 29 SPARE_0 30 30 SPARE_1 31 31 regDP_AUX4_AUX_SW_CONTROL 0 0x1fc1 4 0 2 AUX_SW_GO 0 0 AUX_LS_READ_TRIG 2 2 AUX_SW_START_DELAY 4 7 AUX_SW_WR_BYTES 16 20 regDP_AUX4_AUX_ARB_CONTROL 0 0x1fc2 10 0 2 AUX_ARB_PRIORITY 0 1 AUX_REG_RW_CNTL_STATUS 2 3 AUX_NO_QUEUED_SW_GO 8 8 AUX_NO_QUEUED_LS_GO 10 10 AUX_SW_USE_AUX_REG_REQ 16 16 AUX_SW_PENDING_USE_AUX_REG_REQ 16 16 AUX_SW_DONE_USING_AUX_REG 17 17 AUX_DMCU_USE_AUX_REG_REQ 24 24 AUX_DMCU_PENDING_USE_AUX_REG_REQ 24 24 AUX_DMCU_DONE_USING_AUX_REG 25 25 regDP_AUX4_AUX_INTERRUPT_CONTROL 0 0x1fc3 12 0 2 AUX_SW_DONE_INT 0 0 AUX_SW_DONE_ACK 1 1 AUX_SW_DONE_MASK 2 2 AUX_LS_DONE_INT 4 4 AUX_LS_DONE_ACK 5 5 AUX_LS_DONE_MASK 6 6 AUX_GTC_SYNC_LOCK_DONE_INT 8 8 AUX_GTC_SYNC_LOCK_DONE_ACK 9 9 AUX_GTC_SYNC_LOCK_DONE_INT_MASK 10 10 AUX_GTC_SYNC_ERROR_INT 12 12 AUX_GTC_SYNC_ERROR_ACK 13 13 AUX_GTC_SYNC_ERROR_INT_MASK 14 14 regDP_AUX4_AUX_SW_STATUS 0 0x1fc4 18 0 2 AUX_SW_DONE 0 0 AUX_SW_REQ 1 1 AUX_SW_RX_TIMEOUT_STATE 4 6 AUX_SW_RX_TIMEOUT 7 7 AUX_SW_RX_OVERFLOW 8 8 AUX_SW_HPD_DISCON 9 9 AUX_SW_RX_PARTIAL_BYTE 10 10 AUX_SW_NON_AUX_MODE 11 11 AUX_SW_RX_MIN_COUNT_VIOL 12 12 AUX_SW_RX_INVALID_STOP 14 14 AUX_SW_RX_SYNC_INVALID_L 17 17 AUX_SW_RX_SYNC_INVALID_H 18 18 AUX_SW_RX_INVALID_START 19 19 AUX_SW_RX_RECV_NO_DET 20 20 AUX_SW_RX_RECV_INVALID_H 22 22 AUX_SW_RX_RECV_INVALID_L 23 23 AUX_SW_REPLY_BYTE_COUNT 24 28 AUX_ARB_STATUS 29 31 regDP_AUX4_AUX_LS_STATUS 0 0x1fc5 20 0 2 AUX_LS_DONE 0 0 AUX_LS_REQ 1 1 AUX_LS_RX_TIMEOUT_STATE 4 6 AUX_LS_RX_TIMEOUT 7 7 AUX_LS_RX_OVERFLOW 8 8 AUX_LS_HPD_DISCON 9 9 AUX_LS_RX_PARTIAL_BYTE 10 10 AUX_LS_NON_AUX_MODE 11 11 AUX_LS_RX_MIN_COUNT_VIOL 12 12 AUX_LS_RX_INVALID_STOP 14 14 AUX_LS_RX_SYNC_INVALID_L 17 17 AUX_LS_RX_SYNC_INVALID_H 18 18 AUX_LS_RX_INVALID_START 19 19 AUX_LS_RX_RECV_NO_DET 20 20 AUX_LS_RX_RECV_INVALID_H 22 22 AUX_LS_RX_RECV_INVALID_L 23 23 AUX_LS_REPLY_BYTE_COUNT 24 28 AUX_LS_CP_IRQ 29 29 AUX_LS_UPDATED 30 30 AUX_LS_UPDATED_ACK 31 31 regDP_AUX4_AUX_SW_DATA 0 0x1fc6 4 0 2 AUX_SW_DATA_RW 0 0 AUX_SW_DATA 8 15 AUX_SW_INDEX 16 20 AUX_SW_AUTOINCREMENT_DISABLE 31 31 regDP_AUX4_AUX_LS_DATA 0 0x1fc7 2 0 2 AUX_LS_DATA 8 15 AUX_LS_INDEX 16 20 regDP_AUX4_AUX_DPHY_TX_REF_CONTROL 0 0x1fc8 3 0 2 AUX_TX_REF_SEL 0 0 AUX_TX_RATE 4 5 AUX_TX_REF_DIV 16 24 regDP_AUX4_AUX_DPHY_TX_CONTROL 0 0x1fc9 5 0 2 AUX_TX_PRECHARGE_LEN 0 3 AUX_TX_PRECHARGE_LEN_MUL 4 5 AUX_TX_OE_ASSERT_TIME 6 6 AUX_TX_PRECHARGE_SYMBOLS 8 13 AUX_MODE_DET_CHECK_DELAY 16 18 regDP_AUX4_AUX_DPHY_RX_CONTROL0 0 0x1fca 9 0 2 AUX_RX_START_WINDOW 4 6 AUX_RX_RECEIVE_WINDOW 8 10 AUX_RX_HALF_SYM_DETECT_LEN 12 13 AUX_RX_TRANSITION_FILTER_EN 16 16 AUX_RX_ALLOW_BELOW_THRESHOLD_PHASE_DETECT 17 17 AUX_RX_ALLOW_BELOW_THRESHOLD_START 18 18 AUX_RX_ALLOW_BELOW_THRESHOLD_STOP 19 19 AUX_RX_PHASE_DETECT_LEN 20 21 AUX_RX_DETECTION_THRESHOLD 28 30 regDP_AUX4_AUX_DPHY_RX_CONTROL1 0 0x1fcb 3 0 2 AUX_RX_PRECHARGE_SKIP 0 7 AUX_RX_TIMEOUT_LEN 8 14 AUX_RX_TIMEOUT_LEN_MUL 15 16 regDP_AUX4_AUX_DPHY_TX_STATUS 0 0x1fcc 3 0 2 AUX_TX_ACTIVE 0 0 AUX_TX_STATE 4 6 AUX_TX_HALF_SYM_PERIOD 16 24 regDP_AUX4_AUX_DPHY_RX_STATUS 0 0x1fcd 4 0 2 AUX_RX_STATE 0 2 AUX_RX_SYNC_VALID_COUNT 8 12 AUX_RX_HALF_SYM_PERIOD_FRACT 16 20 AUX_RX_HALF_SYM_PERIOD 21 29 regDP_AUX4_AUX_GTC_SYNC_CONTROL 0 0x1fce 9 0 2 AUX_GTC_SYNC_EN 0 0 AUX_GTC_SYNC_IMPCAL_EN 4 4 AUX_GTC_SYNC_IMPCAL_INTERVAL 8 11 AUX_GTC_SYNC_LOCK_ACQ_PERIOD 12 15 AUX_GTC_SYNC_LOCK_MAINT_PERIOD 16 18 AUX_GTC_SYNC_BLOCK_REQ 20 20 AUX_GTC_SYNC_INTERVAL_RESET_WINDOW 22 23 AUX_GTC_SYNC_OFFSET_CALC_MAX_ATTEMPT 24 25 AUX_GTC_SYNC_LOCK_ACQ_MAX_ATTEMPT 28 31 regDP_AUX4_AUX_GTC_SYNC_ERROR_CONTROL 0 0x1fcf 4 0 2 AUX_GTC_POTENTIAL_ERROR_THRESHOLD 0 4 AUX_GTC_DEFINITE_ERROR_THRESHOLD 8 12 AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_LEN 16 17 AUX_GTC_SYNC_NUM_RETRY_FOR_LOCK_MAINT 20 21 regDP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS 0 0x1fd0 12 0 2 AUX_GTC_SYNC_LOCK_ACQ_COMPLETE 0 0 AUX_GTC_SYNC_LOCK_LOST 4 4 AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_OCCURRED 8 8 AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_STATE 9 12 AUX_GTC_SYNC_PHASE_ADJUST_TIME_VIOL 16 16 AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED 20 20 AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED_ACK 21 21 AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED 22 22 AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED_ACK 23 23 AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED 24 24 AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED_ACK 25 25 AUX_GTC_SYNC_CTRL_STATE 28 31 regDP_AUX4_AUX_GTC_SYNC_STATUS 0 0x1fd1 19 0 2 AUX_GTC_SYNC_DONE 0 0 AUX_GTC_SYNC_REQ 1 1 AUX_GTC_SYNC_RX_TIMEOUT_STATE 4 6 AUX_GTC_SYNC_TIMEOUT 7 7 AUX_GTC_SYNC_RX_OVERFLOW 8 8 AUX_GTC_SYNC_HPD_DISCON 9 9 AUX_GTC_SYNC_RX_PARTIAL_BYTE 10 10 AUX_GTC_SYNC_NON_AUX_MODE 11 11 AUX_GTC_SYNC_RX_MIN_COUNT_VIOL 12 12 AUX_GTC_SYNC_RX_INVALID_STOP 14 14 AUX_GTC_SYNC_RX_SYNC_INVALID_L 17 17 AUX_GTC_SYNC_RX_SYNC_INVALID_H 18 18 AUX_GTC_SYNC_RX_INVALID_START 19 19 AUX_GTC_SYNC_RX_RECV_NO_DET 20 20 AUX_GTC_SYNC_RX_RECV_INVALID_H 22 22 AUX_GTC_SYNC_RX_RECV_INVALID_L 23 23 AUX_GTC_SYNC_REPLY_BYTE_COUNT 24 28 AUX_GTC_SYNC_NACKED 29 29 AUX_GTC_MASTER_REQ_BY_RX 30 30 regDP_AUX4_AUX_PHY_WAKE_CNTL 0 0x1fd6 4 0 2 DP_AUX_PHY_WAKE_GO 0 0 DP_AUX_PHY_WAKE_PENDING 1 1 DP_AUX_PHY_WAKE_PRIORITY 2 2 DP_AUX_PHY_WAKE_ACK 3 3 regDC_I2C_CONTROL 0 0x1e98 7 0 2 DC_I2C_GO 0 0 DC_I2C_SOFT_RESET 1 1 DC_I2C_SEND_RESET 2 2 DC_I2C_SW_STATUS_RESET 3 3 DC_I2C_DDC_SELECT 8 10 DC_I2C_TRANSACTION_COUNT 20 21 DC_I2C_DBG_REF_SEL 31 31 regDC_I2C_ARBITRATION 0 0x1e99 9 0 2 DC_I2C_SW_PRIORITY 0 1 DC_I2C_REG_RW_CNTL_STATUS 2 3 DC_I2C_NO_QUEUED_SW_GO 4 4 DC_I2C_ABORT_HW_XFER 8 8 DC_I2C_ABORT_SW_XFER 12 12 DC_I2C_SW_USE_I2C_REG_REQ 20 20 DC_I2C_SW_DONE_USING_I2C_REG 21 21 DC_I2C_DMCU_USE_I2C_REG_REQ 24 24 DC_I2C_DMCU_DONE_USING_I2C_REG 25 25 regDC_I2C_SW_STATUS 0 0x1e9b 12 0 2 DC_I2C_SW_STATUS 0 1 DC_I2C_SW_DONE 2 2 DC_I2C_SW_ABORTED 4 4 DC_I2C_SW_TIMEOUT 5 5 DC_I2C_SW_INTERRUPTED 6 6 DC_I2C_SW_BUFFER_OVERFLOW 7 7 DC_I2C_SW_STOPPED_ON_NACK 8 8 DC_I2C_SW_NACK0 12 12 DC_I2C_SW_NACK1 13 13 DC_I2C_SW_NACK2 14 14 DC_I2C_SW_NACK3 15 15 DC_I2C_SW_REQ 18 18 regDC_I2C_DDC1_HW_STATUS 0 0x1e9c 7 0 2 DC_I2C_DDC1_HW_STATUS 0 1 DC_I2C_DDC1_HW_DONE 3 3 DC_I2C_DDC1_HW_REQ 16 16 DC_I2C_DDC1_HW_URG 17 17 DC_I2C_DDC1_EDID_DETECT_STATUS 20 20 DC_I2C_DDC1_EDID_DETECT_NUM_VALID_TRIES 24 27 DC_I2C_DDC1_EDID_DETECT_STATE 28 30 regDC_I2C_DDC2_HW_STATUS 0 0x1e9d 7 0 2 DC_I2C_DDC2_HW_STATUS 0 1 DC_I2C_DDC2_HW_DONE 3 3 DC_I2C_DDC2_HW_REQ 16 16 DC_I2C_DDC2_HW_URG 17 17 DC_I2C_DDC2_EDID_DETECT_STATUS 20 20 DC_I2C_DDC2_EDID_DETECT_NUM_VALID_TRIES 24 27 DC_I2C_DDC2_EDID_DETECT_STATE 28 30 regDC_I2C_DDC3_HW_STATUS 0 0x1e9e 7 0 2 DC_I2C_DDC3_HW_STATUS 0 1 DC_I2C_DDC3_HW_DONE 3 3 DC_I2C_DDC3_HW_REQ 16 16 DC_I2C_DDC3_HW_URG 17 17 DC_I2C_DDC3_EDID_DETECT_STATUS 20 20 DC_I2C_DDC3_EDID_DETECT_NUM_VALID_TRIES 24 27 DC_I2C_DDC3_EDID_DETECT_STATE 28 30 regDC_I2C_DDC4_HW_STATUS 0 0x1e9f 7 0 2 DC_I2C_DDC4_HW_STATUS 0 1 DC_I2C_DDC4_HW_DONE 3 3 DC_I2C_DDC4_HW_REQ 16 16 DC_I2C_DDC4_HW_URG 17 17 DC_I2C_DDC4_EDID_DETECT_STATUS 20 20 DC_I2C_DDC4_EDID_DETECT_NUM_VALID_TRIES 24 27 DC_I2C_DDC4_EDID_DETECT_STATE 28 30 regDC_I2C_DDC5_HW_STATUS 0 0x1ea0 7 0 2 DC_I2C_DDC5_HW_STATUS 0 1 DC_I2C_DDC5_HW_DONE 3 3 DC_I2C_DDC5_HW_REQ 16 16 DC_I2C_DDC5_HW_URG 17 17 DC_I2C_DDC5_EDID_DETECT_STATUS 20 20 DC_I2C_DDC5_EDID_DETECT_NUM_VALID_TRIES 24 27 DC_I2C_DDC5_EDID_DETECT_STATE 28 30 regDC_I2C_DDC1_SPEED 0 0x1ea2 4 0 2 DC_I2C_DDC1_THRESHOLD 0 1 DC_I2C_DDC1_DISABLE_FILTER_DURING_STALL 4 4 DC_I2C_DDC1_START_STOP_TIMING_CNTL 8 9 DC_I2C_DDC1_PRESCALE 16 31 regDC_I2C_DDC1_SETUP 0 0x1ea3 10 0 2 DC_I2C_DDC1_DATA_DRIVE_EN 0 0 DC_I2C_DDC1_DATA_DRIVE_SEL 1 1 DC_I2C_DDC1_SEND_RESET_LENGTH 2 2 DC_I2C_DDC1_EDID_DETECT_ENABLE 4 4 DC_I2C_DDC1_EDID_DETECT_MODE 5 5 DC_I2C_DDC1_ENABLE 6 6 DC_I2C_DDC1_CLK_DRIVE_EN 7 7 DC_I2C_DDC1_INTRA_BYTE_DELAY 8 15 DC_I2C_DDC1_INTRA_TRANSACTION_DELAY 16 23 DC_I2C_DDC1_TIME_LIMIT 24 31 regDC_I2C_DDC2_SPEED 0 0x1ea4 4 0 2 DC_I2C_DDC2_THRESHOLD 0 1 DC_I2C_DDC2_DISABLE_FILTER_DURING_STALL 4 4 DC_I2C_DDC2_START_STOP_TIMING_CNTL 8 9 DC_I2C_DDC2_PRESCALE 16 31 regDC_I2C_DDC2_SETUP 0 0x1ea5 10 0 2 DC_I2C_DDC2_DATA_DRIVE_EN 0 0 DC_I2C_DDC2_DATA_DRIVE_SEL 1 1 DC_I2C_DDC2_SEND_RESET_LENGTH 2 2 DC_I2C_DDC2_EDID_DETECT_ENABLE 4 4 DC_I2C_DDC2_EDID_DETECT_MODE 5 5 DC_I2C_DDC2_ENABLE 6 6 DC_I2C_DDC2_CLK_DRIVE_EN 7 7 DC_I2C_DDC2_INTRA_BYTE_DELAY 8 15 DC_I2C_DDC2_INTRA_TRANSACTION_DELAY 16 23 DC_I2C_DDC2_TIME_LIMIT 24 31 regDC_I2C_DDC3_SPEED 0 0x1ea6 4 0 2 DC_I2C_DDC3_THRESHOLD 0 1 DC_I2C_DDC3_DISABLE_FILTER_DURING_STALL 4 4 DC_I2C_DDC3_START_STOP_TIMING_CNTL 8 9 DC_I2C_DDC3_PRESCALE 16 31 regDC_I2C_DDC3_SETUP 0 0x1ea7 10 0 2 DC_I2C_DDC3_DATA_DRIVE_EN 0 0 DC_I2C_DDC3_DATA_DRIVE_SEL 1 1 DC_I2C_DDC3_SEND_RESET_LENGTH 2 2 DC_I2C_DDC3_EDID_DETECT_ENABLE 4 4 DC_I2C_DDC3_EDID_DETECT_MODE 5 5 DC_I2C_DDC3_ENABLE 6 6 DC_I2C_DDC3_CLK_DRIVE_EN 7 7 DC_I2C_DDC3_INTRA_BYTE_DELAY 8 15 DC_I2C_DDC3_INTRA_TRANSACTION_DELAY 16 23 DC_I2C_DDC3_TIME_LIMIT 24 31 regDC_I2C_DDC4_SPEED 0 0x1ea8 4 0 2 DC_I2C_DDC4_THRESHOLD 0 1 DC_I2C_DDC4_DISABLE_FILTER_DURING_STALL 4 4 DC_I2C_DDC4_START_STOP_TIMING_CNTL 8 9 DC_I2C_DDC4_PRESCALE 16 31 regDC_I2C_DDC4_SETUP 0 0x1ea9 10 0 2 DC_I2C_DDC4_DATA_DRIVE_EN 0 0 DC_I2C_DDC4_DATA_DRIVE_SEL 1 1 DC_I2C_DDC4_SEND_RESET_LENGTH 2 2 DC_I2C_DDC4_EDID_DETECT_ENABLE 4 4 DC_I2C_DDC4_EDID_DETECT_MODE 5 5 DC_I2C_DDC4_ENABLE 6 6 DC_I2C_DDC4_CLK_DRIVE_EN 7 7 DC_I2C_DDC4_INTRA_BYTE_DELAY 8 15 DC_I2C_DDC4_INTRA_TRANSACTION_DELAY 16 23 DC_I2C_DDC4_TIME_LIMIT 24 31 regDC_I2C_DDC5_SPEED 0 0x1eaa 4 0 2 DC_I2C_DDC5_THRESHOLD 0 1 DC_I2C_DDC5_DISABLE_FILTER_DURING_STALL 4 4 DC_I2C_DDC5_START_STOP_TIMING_CNTL 8 9 DC_I2C_DDC5_PRESCALE 16 31 regDC_I2C_DDC5_SETUP 0 0x1eab 10 0 2 DC_I2C_DDC5_DATA_DRIVE_EN 0 0 DC_I2C_DDC5_DATA_DRIVE_SEL 1 1 DC_I2C_DDC5_SEND_RESET_LENGTH 2 2 DC_I2C_DDC5_EDID_DETECT_ENABLE 4 4 DC_I2C_DDC5_EDID_DETECT_MODE 5 5 DC_I2C_DDC5_ENABLE 6 6 DC_I2C_DDC5_CLK_DRIVE_EN 7 7 DC_I2C_DDC5_INTRA_BYTE_DELAY 8 15 DC_I2C_DDC5_INTRA_TRANSACTION_DELAY 16 23 DC_I2C_DDC5_TIME_LIMIT 24 31 regDC_I2C_TRANSACTION0 0 0x1eae 5 0 2 DC_I2C_RW0 0 0 DC_I2C_STOP_ON_NACK0 8 8 DC_I2C_START0 12 12 DC_I2C_STOP0 13 13 DC_I2C_COUNT0 16 25 regDC_I2C_TRANSACTION1 0 0x1eaf 5 0 2 DC_I2C_RW1 0 0 DC_I2C_STOP_ON_NACK1 8 8 DC_I2C_START1 12 12 DC_I2C_STOP1 13 13 DC_I2C_COUNT1 16 25 regDC_I2C_TRANSACTION2 0 0x1eb0 5 0 2 DC_I2C_RW2 0 0 DC_I2C_STOP_ON_NACK2 8 8 DC_I2C_START2 12 12 DC_I2C_STOP2 13 13 DC_I2C_COUNT2 16 25 regDC_I2C_TRANSACTION3 0 0x1eb1 5 0 2 DC_I2C_RW3 0 0 DC_I2C_STOP_ON_NACK3 8 8 DC_I2C_START3 12 12 DC_I2C_STOP3 13 13 DC_I2C_COUNT3 16 25 regDC_I2C_DATA 0 0x1eb2 4 0 2 DC_I2C_DATA_RW 0 0 DC_I2C_DATA 8 15 DC_I2C_INDEX 16 25 DC_I2C_INDEX_WRITE 31 31 regDC_I2C_EDID_DETECT_CTRL 0 0x1eb6 3 0 2 DC_I2C_EDID_DETECT_WAIT_TIME 0 15 DC_I2C_EDID_DETECT_NUM_TRIES_UNTIL_VALID 20 23 DC_I2C_EDID_DETECT_SEND_RESET 28 28 regDC_I2C_READ_REQUEST_INTERRUPT 0 0x1eb7 30 0 2 DC_I2C_DDC1_READ_REQUEST_OCCURRED 0 0 DC_I2C_DDC1_READ_REQUEST_INT 1 1 DC_I2C_DDC1_READ_REQUEST_ACK 2 2 DC_I2C_DDC1_READ_REQUEST_MASK 3 3 DC_I2C_DDC2_READ_REQUEST_OCCURRED 4 4 DC_I2C_DDC2_READ_REQUEST_INT 5 5 DC_I2C_DDC2_READ_REQUEST_ACK 6 6 DC_I2C_DDC2_READ_REQUEST_MASK 7 7 DC_I2C_DDC3_READ_REQUEST_OCCURRED 8 8 DC_I2C_DDC3_READ_REQUEST_INT 9 9 DC_I2C_DDC3_READ_REQUEST_ACK 10 10 DC_I2C_DDC3_READ_REQUEST_MASK 11 11 DC_I2C_DDC4_READ_REQUEST_OCCURRED 12 12 DC_I2C_DDC4_READ_REQUEST_INT 13 13 DC_I2C_DDC4_READ_REQUEST_ACK 14 14 DC_I2C_DDC4_READ_REQUEST_MASK 15 15 DC_I2C_DDC5_READ_REQUEST_OCCURRED 16 16 DC_I2C_DDC5_READ_REQUEST_INT 17 17 DC_I2C_DDC5_READ_REQUEST_ACK 18 18 DC_I2C_DDC5_READ_REQUEST_MASK 19 19 DC_I2C_DDC6_READ_REQUEST_OCCURRED 20 20 DC_I2C_DDC6_READ_REQUEST_INT 21 21 DC_I2C_DDC6_READ_REQUEST_ACK 22 22 DC_I2C_DDC6_READ_REQUEST_MASK 23 23 DC_I2C_DDCVGA_READ_REQUEST_OCCURRED 24 24 DC_I2C_DDCVGA_READ_REQUEST_INT 25 25 DC_I2C_DDCVGA_READ_REQUEST_ACK 26 26 DC_I2C_DDCVGA_READ_REQUEST_MASK 27 27 DC_I2C_DDC_READ_REQUEST_ACK_ENABLE 30 30 DC_I2C_DDC_READ_REQUEST_INT_TYPE 31 31 regDIO_SCRATCH0 0 0x1eca 1 0 2 DIO_SCRATCH0 0 31 regDIO_SCRATCH1 0 0x1ecb 1 0 2 DIO_SCRATCH1 0 31 regDIO_SCRATCH2 0 0x1ecc 1 0 2 DIO_SCRATCH2 0 31 regDIO_SCRATCH3 0 0x1ecd 1 0 2 DIO_SCRATCH3 0 31 regDIO_SCRATCH4 0 0x1ece 1 0 2 DIO_SCRATCH4 0 31 regDIO_SCRATCH5 0 0x1ecf 1 0 2 DIO_SCRATCH5 0 31 regDIO_SCRATCH6 0 0x1ed0 1 0 2 DIO_SCRATCH6 0 31 regDIO_SCRATCH7 0 0x1ed1 1 0 2 DIO_SCRATCH7 0 31 regDIO_MEM_PWR_STATUS 0 0x1edd 8 0 2 I2C_MEM_PWR_STATE 0 0 DPA_MEM_PWR_STATE 3 3 DPB_MEM_PWR_STATE 4 4 DPC_MEM_PWR_STATE 5 5 DPD_MEM_PWR_STATE 6 6 DPE_MEM_PWR_STATE 7 7 DPF_MEM_PWR_STATE 8 8 DPG_MEM_PWR_STATE 9 9 regDIO_MEM_PWR_CTRL 0 0x1ede 9 0 2 I2C_LIGHT_SLEEP_FORCE 0 0 I2C_LIGHT_SLEEP_DIS 1 1 DPA_LIGHT_SLEEP_DIS 4 4 DPB_LIGHT_SLEEP_DIS 5 5 DPC_LIGHT_SLEEP_DIS 6 6 DPD_LIGHT_SLEEP_DIS 7 7 DPE_LIGHT_SLEEP_DIS 8 8 DPF_LIGHT_SLEEP_DIS 9 9 DPG_LIGHT_SLEEP_DIS 10 10 regDIO_MEM_PWR_CTRL2 0 0x1edf 7 0 2 DPA_LIGHT_SLEEP_FORCE 24 24 DPB_LIGHT_SLEEP_FORCE 25 25 DPC_LIGHT_SLEEP_FORCE 26 26 DPD_LIGHT_SLEEP_FORCE 27 27 DPE_LIGHT_SLEEP_FORCE 28 28 DPF_LIGHT_SLEEP_FORCE 29 29 DPG_LIGHT_SLEEP_FORCE 30 30 regDIO_CLK_CNTL 0 0x1ee0 9 0 2 DISPCLK_R_DIO_GATE_DIS 5 5 REFCLK_R_DIO_GATE_DIS 10 10 DISPCLK_G_DIGA_GATE_DIS 24 24 DISPCLK_G_DIGB_GATE_DIS 25 25 DISPCLK_G_DIGC_GATE_DIS 26 26 DISPCLK_G_DIGD_GATE_DIS 27 27 DISPCLK_G_DIGE_GATE_DIS 28 28 DISPCLK_G_DIGF_GATE_DIS 29 29 DISPCLK_G_DIGG_GATE_DIS 30 30 regDIO_POWER_MANAGEMENT_CNTL 0 0x1ee4 2 0 2 PM_ASSERT_RESET 0 0 PM_ALL_BUSY_OFF 8 8 regDIG_SOFT_RESET 0 0x1eee 14 0 2 DIGA_FE_SOFT_RESET 0 0 DIGA_BE_SOFT_RESET 1 1 DIGB_FE_SOFT_RESET 4 4 DIGB_BE_SOFT_RESET 5 5 DIGC_FE_SOFT_RESET 8 8 DIGC_BE_SOFT_RESET 9 9 DIGD_FE_SOFT_RESET 12 12 DIGD_BE_SOFT_RESET 13 13 DIGE_FE_SOFT_RESET 16 16 DIGE_BE_SOFT_RESET 17 17 DIGF_FE_SOFT_RESET 20 20 DIGF_BE_SOFT_RESET 21 21 DIGG_FE_SOFT_RESET 24 24 DIGG_BE_SOFT_RESET 25 25 regDIO_CLK_CNTL2 0 0x1ef2 22 0 2 DIO_TEST_CLK_SEL 0 6 SOCCLK_G_AFMTA_GATE_DIS 7 7 SOCCLK_G_AFMTB_GATE_DIS 8 8 SOCCLK_G_AFMTC_GATE_DIS 9 9 SOCCLK_G_AFMTD_GATE_DIS 10 10 SOCCLK_G_AFMTE_GATE_DIS 11 11 SOCCLK_G_AFMTF_GATE_DIS 12 12 SOCCLK_G_AFMTG_GATE_DIS 13 13 SYMCLKA_FE_G_AFMT_GATE_DIS 17 17 SYMCLKB_FE_G_AFMT_GATE_DIS 18 18 SYMCLKC_FE_G_AFMT_GATE_DIS 19 19 SYMCLKD_FE_G_AFMT_GATE_DIS 20 20 SYMCLKE_FE_G_AFMT_GATE_DIS 21 21 SYMCLKF_FE_G_AFMT_GATE_DIS 22 22 SYMCLKG_FE_G_AFMT_GATE_DIS 23 23 SYMCLKA_FE_R_GATE_DIS 24 24 SYMCLKB_FE_R_GATE_DIS 25 25 SYMCLKC_FE_R_GATE_DIS 26 26 SYMCLKD_FE_R_GATE_DIS 27 27 SYMCLKE_FE_R_GATE_DIS 28 28 SYMCLKF_FE_R_GATE_DIS 29 29 SYMCLKG_FE_R_GATE_DIS 30 30 regDIO_CLK_CNTL3 0 0x1ef3 14 0 2 SYMCLKA_FE_G_TMDS_GATE_DIS 0 0 SYMCLKB_FE_G_TMDS_GATE_DIS 1 1 SYMCLKC_FE_G_TMDS_GATE_DIS 2 2 SYMCLKD_FE_G_TMDS_GATE_DIS 3 3 SYMCLKE_FE_G_TMDS_GATE_DIS 4 4 SYMCLKF_FE_G_TMDS_GATE_DIS 5 5 SYMCLKG_FE_G_TMDS_GATE_DIS 6 6 SYMCLKA_G_TMDS_GATE_DIS 10 10 SYMCLKB_G_TMDS_GATE_DIS 11 11 SYMCLKC_G_TMDS_GATE_DIS 12 12 SYMCLKD_G_TMDS_GATE_DIS 13 13 SYMCLKE_G_TMDS_GATE_DIS 14 14 SYMCLKF_G_TMDS_GATE_DIS 15 15 SYMCLKG_G_TMDS_GATE_DIS 16 16 regDIO_HDMI_RXSTATUS_TIMER_CONTROL 0 0x1eff 5 0 2 DIO_HDMI_RXSTATUS_TIMER_ENABLE 0 0 DIO_HDMI_RXSTATUS_TIMER_TYPE 4 4 DIO_HDMI_RXSTATUS_TIMER_STATUS 8 8 DIO_HDMI_RXSTATUS_TIMER_MASK 12 12 DIO_HDMI_RXSTATUS_TIMER_INTERVAL 16 27 regDIO_PSP_INTERRUPT_CLEAR 0 0x1f01 1 0 2 DIO_PSP_INTERRUPT_CLEAR 0 0 regDIO_GENERIC_INTERRUPT_MESSAGE 0 0x1f02 1 0 2 DIO_GENERIC_INTERRUPT_MESSAGE 1 31 regDIO_GENERIC_INTERRUPT_CLEAR 0 0x1f03 1 0 2 DIO_GENERIC_INTERRUPT_CLEAR 0 0 regDIO_LINKA_CNTL 0 0x1f04 3 0 2 ENC_TYPE_SEL 0 1 HPO_HDMI_ENC_SEL 4 6 HPO_DP_ENC_SEL 8 10 regDIO_LINKB_CNTL 0 0x1f05 3 0 2 ENC_TYPE_SEL 0 1 HPO_HDMI_ENC_SEL 4 6 HPO_DP_ENC_SEL 8 10 regDIO_LINKC_CNTL 0 0x1f06 3 0 2 ENC_TYPE_SEL 0 1 HPO_HDMI_ENC_SEL 4 6 HPO_DP_ENC_SEL 8 10 regDIO_LINKD_CNTL 0 0x1f07 3 0 2 ENC_TYPE_SEL 0 1 HPO_HDMI_ENC_SEL 4 6 HPO_DP_ENC_SEL 8 10 regDIO_LINKE_CNTL 0 0x1f08 3 0 2 ENC_TYPE_SEL 0 1 HPO_HDMI_ENC_SEL 4 6 HPO_DP_ENC_SEL 8 10 regDIO_LINKF_CNTL 0 0x1f09 3 0 2 ENC_TYPE_SEL 0 1 HPO_HDMI_ENC_SEL 4 6 HPO_DP_ENC_SEL 8 10 regDC_PERFMON18_PERFCOUNTER_CNTL 0 0x1f44 11 0 2 PERFCOUNTER_EVENT_SEL 0 8 PERFCOUNTER_CVALUE_SEL 9 11 PERFCOUNTER_INC_MODE 12 14 PERFCOUNTER_HW_CNTL_SEL 15 15 PERFCOUNTER_RUNEN_MODE 16 16 PERFCOUNTER_CNTOFF_START_DIS 22 22 PERFCOUNTER_RESTART_EN 23 23 PERFCOUNTER_INT_EN 24 24 PERFCOUNTER_OFF_MASK 25 25 PERFCOUNTER_ACTIVE 26 26 PERFCOUNTER_CNTL_SEL 29 31 regDC_PERFMON18_PERFCOUNTER_CNTL2 0 0x1f45 5 0 2 PERFCOUNTER_COUNTED_VALUE_TYPE 0 1 PERFCOUNTER_HW_STOP1_SEL 2 2 PERFCOUNTER_HW_STOP2_SEL 3 3 PERFCOUNTER_CNTOFF_SEL 8 13 PERFCOUNTER_CNTL2_SEL 29 31 regDC_PERFMON18_PERFCOUNTER_STATE 0 0x1f46 16 0 2 PERFCOUNTER_CNT0_STATE 0 1 PERFCOUNTER_STATE_SEL0 2 2 PERFCOUNTER_CNT1_STATE 4 5 PERFCOUNTER_STATE_SEL1 6 6 PERFCOUNTER_CNT2_STATE 8 9 PERFCOUNTER_STATE_SEL2 10 10 PERFCOUNTER_CNT3_STATE 12 13 PERFCOUNTER_STATE_SEL3 14 14 PERFCOUNTER_CNT4_STATE 16 17 PERFCOUNTER_STATE_SEL4 18 18 PERFCOUNTER_CNT5_STATE 20 21 PERFCOUNTER_STATE_SEL5 22 22 PERFCOUNTER_CNT6_STATE 24 25 PERFCOUNTER_STATE_SEL6 26 26 PERFCOUNTER_CNT7_STATE 28 29 PERFCOUNTER_STATE_SEL7 30 30 regDC_PERFMON18_PERFMON_CNTL 0 0x1f47 6 0 2 PERFMON_STATE 0 1 PERFMON_RPT_COUNT 8 27 PERFMON_CNTOFF_AND_OR 28 28 PERFMON_CNTOFF_INT_EN 29 29 PERFMON_CNTOFF_INT_STATUS 30 30 PERFMON_CNTOFF_INT_ACK 31 31 regDC_PERFMON18_PERFMON_CNTL2 0 0x1f48 4 0 2 PERFMON_CNTOFF_INT_TYPE 0 0 PERFMON_CLK_ENABLE 1 1 PERFMON_RUN_ENABLE_START_SEL 2 9 PERFMON_RUN_ENABLE_STOP_SEL 10 17 regDC_PERFMON18_PERFMON_CVALUE_INT_MISC 0 0x1f49 17 0 2 PERFCOUNTER_INT0_STATUS 0 0 PERFCOUNTER_INT1_STATUS 1 1 PERFCOUNTER_INT2_STATUS 2 2 PERFCOUNTER_INT3_STATUS 3 3 PERFCOUNTER_INT4_STATUS 4 4 PERFCOUNTER_INT5_STATUS 5 5 PERFCOUNTER_INT6_STATUS 6 6 PERFCOUNTER_INT7_STATUS 7 7 PERFCOUNTER_INT0_ACK 8 8 PERFCOUNTER_INT1_ACK 9 9 PERFCOUNTER_INT2_ACK 10 10 PERFCOUNTER_INT3_ACK 11 11 PERFCOUNTER_INT4_ACK 12 12 PERFCOUNTER_INT5_ACK 13 13 PERFCOUNTER_INT6_ACK 14 14 PERFCOUNTER_INT7_ACK 15 15 PERFMON_CVALUE_HI 16 31 regDC_PERFMON18_PERFMON_CVALUE_LOW 0 0x1f4a 1 0 2 PERFMON_CVALUE_LOW 0 31 regDC_PERFMON18_PERFMON_HI 0 0x1f4b 2 0 2 PERFMON_HI 0 15 PERFMON_READ_SEL 29 31 regDC_PERFMON18_PERFMON_LOW 0 0x1f4c 1 0 2 PERFMON_LOW 0 31 regDC_GENERICA 0 0x2868 6 0 2 GENERICA_EN 0 0 GENERICA_SEL 7 11 GENERICA_UNIPHY_REFDIV_CLK_SEL 12 15 GENERICA_UNIPHY_FBDIV_CLK_SEL 16 19 GENERICA_UNIPHY_FBDIV_SSC_CLK_SEL 20 23 GENERICA_UNIPHY_FBDIV_CLK_DIV2_SEL 24 27 regDC_GENERICB 0 0x2869 6 0 2 GENERICB_EN 0 0 GENERICB_SEL 8 11 GENERICB_UNIPHY_REFDIV_CLK_SEL 12 15 GENERICB_UNIPHY_FBDIV_CLK_SEL 16 19 GENERICB_UNIPHY_FBDIV_SSC_CLK_SEL 20 23 GENERICB_UNIPHY_FBDIV_CLK_DIV2_SEL 24 27 regDCIO_CLOCK_CNTL 0 0x286a 2 0 2 DCIO_TEST_CLK_SEL 0 4 DISPCLK_R_DCIO_GATE_DIS 5 5 regDC_REF_CLK_CNTL 0 0x286b 2 0 2 HSYNCA_OUTPUT_SEL 0 1 GENLK_CLK_OUTPUT_SEL 8 9 regUNIPHYA_LINK_CNTL 0 0x286d 5 0 2 UNIPHY_CHANNEL0_INVERT 12 12 UNIPHY_CHANNEL1_INVERT 13 13 UNIPHY_CHANNEL2_INVERT 14 14 UNIPHY_CHANNEL3_INVERT 15 15 UNIPHY_LINK_PWRSEQ_SEL 16 16 regUNIPHYA_CHANNEL_XBAR_CNTL 0 0x286e 4 0 2 UNIPHY_CHANNEL0_XBAR_SOURCE 0 1 UNIPHY_CHANNEL1_XBAR_SOURCE 8 9 UNIPHY_CHANNEL2_XBAR_SOURCE 16 17 UNIPHY_CHANNEL3_XBAR_SOURCE 24 25 regUNIPHYB_LINK_CNTL 0 0x286f 5 0 2 UNIPHY_CHANNEL0_INVERT 12 12 UNIPHY_CHANNEL1_INVERT 13 13 UNIPHY_CHANNEL2_INVERT 14 14 UNIPHY_CHANNEL3_INVERT 15 15 UNIPHY_LINK_PWRSEQ_SEL 16 16 regUNIPHYB_CHANNEL_XBAR_CNTL 0 0x2870 4 0 2 UNIPHY_CHANNEL0_XBAR_SOURCE 0 1 UNIPHY_CHANNEL1_XBAR_SOURCE 8 9 UNIPHY_CHANNEL2_XBAR_SOURCE 16 17 UNIPHY_CHANNEL3_XBAR_SOURCE 24 25 regUNIPHYC_LINK_CNTL 0 0x2871 5 0 2 UNIPHY_CHANNEL0_INVERT 12 12 UNIPHY_CHANNEL1_INVERT 13 13 UNIPHY_CHANNEL2_INVERT 14 14 UNIPHY_CHANNEL3_INVERT 15 15 UNIPHY_LINK_PWRSEQ_SEL 16 16 regUNIPHYC_CHANNEL_XBAR_CNTL 0 0x2872 4 0 2 UNIPHY_CHANNEL0_XBAR_SOURCE 0 1 UNIPHY_CHANNEL1_XBAR_SOURCE 8 9 UNIPHY_CHANNEL2_XBAR_SOURCE 16 17 UNIPHY_CHANNEL3_XBAR_SOURCE 24 25 regUNIPHYD_LINK_CNTL 0 0x2873 5 0 2 UNIPHY_CHANNEL0_INVERT 12 12 UNIPHY_CHANNEL1_INVERT 13 13 UNIPHY_CHANNEL2_INVERT 14 14 UNIPHY_CHANNEL3_INVERT 15 15 UNIPHY_LINK_PWRSEQ_SEL 16 16 regUNIPHYD_CHANNEL_XBAR_CNTL 0 0x2874 4 0 2 UNIPHY_CHANNEL0_XBAR_SOURCE 0 1 UNIPHY_CHANNEL1_XBAR_SOURCE 8 9 UNIPHY_CHANNEL2_XBAR_SOURCE 16 17 UNIPHY_CHANNEL3_XBAR_SOURCE 24 25 regUNIPHYE_LINK_CNTL 0 0x2875 5 0 2 UNIPHY_CHANNEL0_INVERT 12 12 UNIPHY_CHANNEL1_INVERT 13 13 UNIPHY_CHANNEL2_INVERT 14 14 UNIPHY_CHANNEL3_INVERT 15 15 UNIPHY_LINK_PWRSEQ_SEL 16 16 regUNIPHYE_CHANNEL_XBAR_CNTL 0 0x2876 4 0 2 UNIPHY_CHANNEL0_XBAR_SOURCE 0 1 UNIPHY_CHANNEL1_XBAR_SOURCE 8 9 UNIPHY_CHANNEL2_XBAR_SOURCE 16 17 UNIPHY_CHANNEL3_XBAR_SOURCE 24 25 regDCIO_WRCMD_DELAY 0 0x287e 1 0 2 UNIPHY_DELAY 24 31 regDC_PINSTRAPS 0 0x2880 4 0 2 DC_PINSTRAPS_SMS_EN_HARD 13 13 DC_PINSTRAPS_AUDIO 14 15 DC_PINSTRAPS_CCBYPASS 16 16 DC_PINSTRAPS_CONNECTIVITY 17 19 regINTERCEPT_STATE 0 0x2884 8 0 2 PWRSEQ0_INTERCEPTB_STATE 0 0 PWRSEQ1_INTERCEPTB_STATE 1 1 RDPCS_TX_DC0_INTERCEPTB_STATE 4 4 RDPCS_TX_DC1_INTERCEPTB_STATE 5 5 RDPCS_TX_DC2_INTERCEPTB_STATE 6 6 RDPCS_TX_DC3_INTERCEPTB_STATE 7 7 RDPCS_TX_DC4_INTERCEPTB_STATE 8 8 RDPCS_TX_DC5_INTERCEPTB_STATE 9 9 regDCIO_BL_PWM_FRAME_START_DISP_SEL 0 0x288b 2 0 2 BL_PWM0_GRP1_FRAME_START_DISP_SEL 0 2 BL_PWM1_GRP1_FRAME_START_DISP_SEL 4 6 regDCIO_GSL_GENLK_PAD_CNTL 0 0x288c 4 0 2 DCIO_GENLK_CLK_GSL_FLIP_READY_SEL 4 5 DCIO_GENLK_CLK_GSL_MASK 8 9 DCIO_GENLK_VSYNC_GSL_FLIP_READY_SEL 20 21 DCIO_GENLK_VSYNC_GSL_MASK 24 25 regDCIO_GSL_SWAPLOCK_PAD_CNTL 0 0x288d 4 0 2 DCIO_SWAPLOCK_A_GSL_FLIP_READY_SEL 4 5 DCIO_SWAPLOCK_A_GSL_MASK 8 9 DCIO_SWAPLOCK_B_GSL_FLIP_READY_SEL 20 21 DCIO_SWAPLOCK_B_GSL_MASK 24 25 regDCIO_SOFT_RESET 0 0x289e 16 0 2 UNIPHYA_SOFT_RESET 0 0 DSYNCA_SOFT_RESET 1 1 UNIPHYB_SOFT_RESET 2 2 DSYNCB_SOFT_RESET 3 3 UNIPHYC_SOFT_RESET 4 4 DSYNCC_SOFT_RESET 5 5 UNIPHYD_SOFT_RESET 6 6 DSYNCD_SOFT_RESET 7 7 UNIPHYE_SOFT_RESET 8 8 DSYNCE_SOFT_RESET 9 9 UNIPHYF_SOFT_RESET 10 10 DSYNCF_SOFT_RESET 11 11 UNIPHYG_SOFT_RESET 12 12 DSYNCG_SOFT_RESET 13 13 PWRSEQ0_SOFT_RESET 16 16 PWRSEQ1_SOFT_RESET 17 17 regDC_GPIO_GENERIC_MASK 0 0x28c8 22 0 2 DC_GPIO_GENERICA_MASK 0 0 DC_GPIO_GENERICA_PD_DIS 1 1 DC_GPIO_GENERICA_RECV 2 3 DC_GPIO_GENERICB_MASK 4 4 DC_GPIO_GENERICB_PD_DIS 5 5 DC_GPIO_GENERICB_RECV 6 7 DC_GPIO_GENERICC_MASK 8 8 DC_GPIO_GENERICC_PD_DIS 9 9 DC_GPIO_GENERICC_RECV 10 11 DC_GPIO_GENERICD_MASK 12 12 DC_GPIO_GENERICD_PD_DIS 13 13 DC_GPIO_GENERICD_RECV 14 15 DC_GPIO_GENERICE_MASK 16 16 DC_GPIO_GENERICE_PD_DIS 17 17 DC_GPIO_GENERICE_RECV 18 19 DC_GPIO_GENERICF_MASK 20 20 DC_GPIO_GENERICF_PD_DIS 21 21 DC_GPIO_GENERICF_RECV 22 23 DC_GPIO_GENERICG_MASK 24 24 DC_GPIO_GENERICG_PD_DIS 25 25 DC_GPIO_GENERICG_RECV 26 27 DC_GPIO_GENERICB_STRENGTH_SN 28 31 regDC_GPIO_GENERIC_A 0 0x28c9 7 0 2 DC_GPIO_GENERICA_A 0 0 DC_GPIO_GENERICB_A 8 8 DC_GPIO_GENERICC_A 16 16 DC_GPIO_GENERICD_A 20 20 DC_GPIO_GENERICE_A 21 21 DC_GPIO_GENERICF_A 22 22 DC_GPIO_GENERICG_A 23 23 regDC_GPIO_GENERIC_EN 0 0x28ca 7 0 2 DC_GPIO_GENERICA_EN 0 0 DC_GPIO_GENERICB_EN 8 8 DC_GPIO_GENERICC_EN 16 16 DC_GPIO_GENERICD_EN 20 20 DC_GPIO_GENERICE_EN 21 21 DC_GPIO_GENERICF_EN 22 22 DC_GPIO_GENERICG_EN 23 23 regDC_GPIO_GENERIC_Y 0 0x28cb 7 0 2 DC_GPIO_GENERICA_Y 0 0 DC_GPIO_GENERICB_Y 8 8 DC_GPIO_GENERICC_Y 16 16 DC_GPIO_GENERICD_Y 20 20 DC_GPIO_GENERICE_Y 21 21 DC_GPIO_GENERICF_Y 22 22 DC_GPIO_GENERICG_Y 23 23 regDC_GPIO_DDC1_MASK 0 0x28d0 11 0 2 DC_GPIO_DDC1CLK_MASK 0 0 DC_GPIO_DDC1CLK_PD_EN 4 4 DC_GPIO_DDC1CLK_RECV 6 6 DC_GPIO_DDC1DATA_MASK 8 8 DC_GPIO_DDC1DATA_PD_EN 12 12 DC_GPIO_DDC1DATA_RECV 14 14 AUX_PAD1_MODE 16 16 AUX1_POL 20 20 ALLOW_HW_DDC1_PD_EN 22 22 DC_GPIO_DDC1CLK_STR 24 27 DC_GPIO_DDC1DATA_STR 28 31 regDC_GPIO_DDC1_A 0 0x28d1 2 0 2 DC_GPIO_DDC1CLK_A 0 0 DC_GPIO_DDC1DATA_A 8 8 regDC_GPIO_DDC1_EN 0 0x28d2 2 0 2 DC_GPIO_DDC1CLK_EN 0 0 DC_GPIO_DDC1DATA_EN 8 8 regDC_GPIO_DDC1_Y 0 0x28d3 2 0 2 DC_GPIO_DDC1CLK_Y 0 0 DC_GPIO_DDC1DATA_Y 8 8 regDC_GPIO_DDC2_MASK 0 0x28d4 11 0 2 DC_GPIO_DDC2CLK_MASK 0 0 DC_GPIO_DDC2CLK_PD_EN 4 4 DC_GPIO_DDC2CLK_RECV 6 6 DC_GPIO_DDC2DATA_MASK 8 8 DC_GPIO_DDC2DATA_PD_EN 12 12 DC_GPIO_DDC2DATA_RECV 14 14 AUX_PAD2_MODE 16 16 AUX2_POL 20 20 ALLOW_HW_DDC2_PD_EN 22 22 DC_GPIO_DDC2CLK_STR 24 27 DC_GPIO_DDC2DATA_STR 28 31 regDC_GPIO_DDC2_A 0 0x28d5 2 0 2 DC_GPIO_DDC2CLK_A 0 0 DC_GPIO_DDC2DATA_A 8 8 regDC_GPIO_DDC2_EN 0 0x28d6 2 0 2 DC_GPIO_DDC2CLK_EN 0 0 DC_GPIO_DDC2DATA_EN 8 8 regDC_GPIO_DDC2_Y 0 0x28d7 2 0 2 DC_GPIO_DDC2CLK_Y 0 0 DC_GPIO_DDC2DATA_Y 8 8 regDC_GPIO_DDC3_MASK 0 0x28d8 11 0 2 DC_GPIO_DDC3CLK_MASK 0 0 DC_GPIO_DDC3CLK_PD_EN 4 4 DC_GPIO_DDC3CLK_RECV 6 6 DC_GPIO_DDC3DATA_MASK 8 8 DC_GPIO_DDC3DATA_PD_EN 12 12 DC_GPIO_DDC3DATA_RECV 14 14 AUX_PAD3_MODE 16 16 AUX3_POL 20 20 ALLOW_HW_DDC3_PD_EN 22 22 DC_GPIO_DDC3CLK_STR 24 27 DC_GPIO_DDC3DATA_STR 28 31 regDC_GPIO_DDC3_A 0 0x28d9 2 0 2 DC_GPIO_DDC3CLK_A 0 0 DC_GPIO_DDC3DATA_A 8 8 regDC_GPIO_DDC3_EN 0 0x28da 2 0 2 DC_GPIO_DDC3CLK_EN 0 0 DC_GPIO_DDC3DATA_EN 8 8 regDC_GPIO_DDC3_Y 0 0x28db 2 0 2 DC_GPIO_DDC3CLK_Y 0 0 DC_GPIO_DDC3DATA_Y 8 8 regDC_GPIO_DDC4_MASK 0 0x28dc 11 0 2 DC_GPIO_DDC4CLK_MASK 0 0 DC_GPIO_DDC4CLK_PD_EN 4 4 DC_GPIO_DDC4CLK_RECV 6 6 DC_GPIO_DDC4DATA_MASK 8 8 DC_GPIO_DDC4DATA_PD_EN 12 12 DC_GPIO_DDC4DATA_RECV 14 14 AUX_PAD4_MODE 16 16 AUX4_POL 20 20 ALLOW_HW_DDC4_PD_EN 22 22 DC_GPIO_DDC4CLK_STR 24 27 DC_GPIO_DDC4DATA_STR 28 31 regDC_GPIO_DDC4_A 0 0x28dd 2 0 2 DC_GPIO_DDC4CLK_A 0 0 DC_GPIO_DDC4DATA_A 8 8 regDC_GPIO_DDC4_EN 0 0x28de 2 0 2 DC_GPIO_DDC4CLK_EN 0 0 DC_GPIO_DDC4DATA_EN 8 8 regDC_GPIO_DDC4_Y 0 0x28df 2 0 2 DC_GPIO_DDC4CLK_Y 0 0 DC_GPIO_DDC4DATA_Y 8 8 regDC_GPIO_DDC5_MASK 0 0x28e0 11 0 2 DC_GPIO_DDC5CLK_MASK 0 0 DC_GPIO_DDC5CLK_PD_EN 4 4 DC_GPIO_DDC5CLK_RECV 6 6 DC_GPIO_DDC5DATA_MASK 8 8 DC_GPIO_DDC5DATA_PD_EN 12 12 DC_GPIO_DDC5DATA_RECV 14 14 AUX_PAD5_MODE 16 16 AUX5_POL 20 20 ALLOW_HW_DDC5_PD_EN 22 22 DC_GPIO_DDC5CLK_STR 24 27 DC_GPIO_DDC5DATA_STR 28 31 regDC_GPIO_DDC5_A 0 0x28e1 2 0 2 DC_GPIO_DDC5CLK_A 0 0 DC_GPIO_DDC5DATA_A 8 8 regDC_GPIO_DDC5_EN 0 0x28e2 2 0 2 DC_GPIO_DDC5CLK_EN 0 0 DC_GPIO_DDC5DATA_EN 8 8 regDC_GPIO_DDC5_Y 0 0x28e3 2 0 2 DC_GPIO_DDC5CLK_Y 0 0 DC_GPIO_DDC5DATA_Y 8 8 regDC_GPIO_DDCVGA_MASK 0 0x28e8 10 0 2 DC_GPIO_DDCVGACLK_MASK 0 0 DC_GPIO_DDCVGACLK_RECV 6 6 DC_GPIO_DDCVGADATA_MASK 8 8 DC_GPIO_DDCVGADATA_PD_EN 12 12 DC_GPIO_DDCVGADATA_RECV 14 14 AUX_PADVGA_MODE 16 16 AUXVGA_POL 20 20 ALLOW_HW_DDCVGA_PD_EN 22 22 DC_GPIO_DDCVGACLK_STR 24 27 DC_GPIO_DDCVGADATA_STR 28 31 regDC_GPIO_DDCVGA_A 0 0x28e9 2 0 2 DC_GPIO_DDCVGACLK_A 0 0 DC_GPIO_DDCVGADATA_A 8 8 regDC_GPIO_DDCVGA_EN 0 0x28ea 2 0 2 DC_GPIO_DDCVGACLK_EN 0 0 DC_GPIO_DDCVGADATA_EN 8 8 regDC_GPIO_DDCVGA_Y 0 0x28eb 2 0 2 DC_GPIO_DDCVGACLK_Y 0 0 DC_GPIO_DDCVGADATA_Y 8 8 regDC_GPIO_GENLK_MASK 0 0x28f0 16 0 2 DC_GPIO_GENLK_CLK_MASK 0 0 DC_GPIO_GENLK_CLK_PD_DIS 1 1 DC_GPIO_GENLK_CLK_PU_EN 3 3 DC_GPIO_GENLK_CLK_RECV 4 5 DC_GPIO_GENLK_VSYNC_MASK 8 8 DC_GPIO_GENLK_VSYNC_PD_DIS 9 9 DC_GPIO_GENLK_VSYNC_PU_EN 11 11 DC_GPIO_GENLK_VSYNC_RECV 12 13 DC_GPIO_SWAPLOCK_A_MASK 16 16 DC_GPIO_SWAPLOCK_A_PD_DIS 17 17 DC_GPIO_SWAPLOCK_A_PU_EN 19 19 DC_GPIO_SWAPLOCK_A_RECV 20 21 DC_GPIO_SWAPLOCK_B_MASK 24 24 DC_GPIO_SWAPLOCK_B_PD_DIS 25 25 DC_GPIO_SWAPLOCK_B_PU_EN 27 27 DC_GPIO_SWAPLOCK_B_RECV 28 29 regDC_GPIO_GENLK_A 0 0x28f1 4 0 2 DC_GPIO_GENLK_CLK_A 0 0 DC_GPIO_GENLK_VSYNC_A 8 8 DC_GPIO_SWAPLOCK_A_A 16 16 DC_GPIO_SWAPLOCK_B_A 24 24 regDC_GPIO_GENLK_EN 0 0x28f2 4 0 2 DC_GPIO_GENLK_CLK_EN 0 0 DC_GPIO_GENLK_VSYNC_EN 8 8 DC_GPIO_SWAPLOCK_A_EN 16 16 DC_GPIO_SWAPLOCK_B_EN 24 24 regDC_GPIO_GENLK_Y 0 0x28f3 4 0 2 DC_GPIO_GENLK_CLK_Y 0 0 DC_GPIO_GENLK_VSYNC_Y 8 8 DC_GPIO_SWAPLOCK_A_Y 16 16 DC_GPIO_SWAPLOCK_B_Y 24 24 regDC_GPIO_HPD_MASK 0 0x28f4 18 0 2 DC_GPIO_HPD1_MASK 0 0 DC_GPIO_HPD1_PD_DIS 4 4 DC_GPIO_HPD1_RECV 6 7 DC_GPIO_HPD2_MASK 8 8 DC_GPIO_HPD2_PD_DIS 9 9 DC_GPIO_HPD2_RECV 10 11 DC_GPIO_HPD3_MASK 16 16 DC_GPIO_HPD3_PD_DIS 17 17 DC_GPIO_HPD3_RECV 18 19 DC_GPIO_HPD4_MASK 20 20 DC_GPIO_HPD4_PD_DIS 21 21 DC_GPIO_HPD4_RECV 22 23 DC_GPIO_HPD5_MASK 24 24 DC_GPIO_HPD5_PD_DIS 25 25 DC_GPIO_HPD5_RECV 26 27 DC_GPIO_HPD6_MASK 28 28 DC_GPIO_HPD6_PD_DIS 29 29 DC_GPIO_HPD6_RECV 30 31 regDC_GPIO_HPD_A 0 0x28f5 6 0 2 DC_GPIO_HPD1_A 0 0 DC_GPIO_HPD2_A 8 8 DC_GPIO_HPD3_A 16 16 DC_GPIO_HPD4_A 24 24 DC_GPIO_HPD5_A 26 26 DC_GPIO_HPD6_A 28 28 regDC_GPIO_HPD_EN 0 0x28f6 20 0 2 DC_GPIO_HPD1_EN 0 0 HPD1_SCHMEN_PI 1 1 HPD1_SLEWNCORE 2 2 HPD12_SPARE0 5 5 HPD1_SEL0 6 6 DC_GPIO_HPD2_EN 8 8 HPD2_SCHMEN_PI 9 9 HPD12_SPARE1 10 10 DC_GPIO_HPD3_EN 16 16 HPD3_SCHMEN_PI 17 17 HPD34_SPARE0 18 18 DC_GPIO_HPD4_EN 20 20 HPD4_SCHMEN_PI 21 21 HPD34_SPARE1 22 22 DC_GPIO_HPD5_EN 24 24 HPD5_SCHMEN_PI 25 25 HPD56_SPARE0 26 26 DC_GPIO_HPD6_EN 28 28 HPD6_SCHMEN_PI 29 29 HPD56_SPARE1 30 30 regDC_GPIO_HPD_Y 0 0x28f7 6 0 2 DC_GPIO_HPD1_Y 0 0 DC_GPIO_HPD2_Y 8 8 DC_GPIO_HPD3_Y 16 16 DC_GPIO_HPD4_Y 24 24 DC_GPIO_HPD5_Y 26 26 DC_GPIO_HPD6_Y 28 28 regDC_GPIO_PWRSEQ0_EN 0 0x28fa 5 0 2 DC_GPIO_VARY_BL_OTG_VSYNC_EN 20 20 DC_GPIO_VARY_BL_OTG_VSYNC_SEL 21 23 DC_GPIO_BLON_OTG_VSYNC_EN 25 25 DC_GPIO_BLON_OTG_VSYNC_SEL 26 28 DC_GPIO_VARY_BL_GENERICA_EN 29 29 regDC_GPIO_PAD_STRENGTH_1 0 0x28fc 6 0 2 GENLK_STRENGTH_SN 0 3 GENLK_STRENGTH_SP 4 7 TX_HPD_STRENGTH_SN 16 19 TX_HPD_STRENGTH_SP 20 23 SYNC_STRENGTH_SN 24 27 SYNC_STRENGTH_SP 28 31 regDC_GPIO_PAD_STRENGTH_2 0 0x28fd 5 0 2 STRENGTH_SN 0 3 STRENGTH_SP 4 7 EXT_RESET_DRVSTRENGTH 8 10 REF_27_DRVSTRENGTH 12 14 REF_27_SRC_SEL 30 31 regPHY_AUX_CNTL 0 0x28ff 7 0 2 AUX_PAD_WAKE 9 9 AUX1_PAD_RXSEL 10 11 AUX2_PAD_RXSEL 12 13 AUX3_PAD_RXSEL 14 15 AUX4_PAD_RXSEL 16 17 AUX5_PAD_RXSEL 18 19 AUX6_PAD_RXSEL 20 21 regDC_GPIO_PWRSEQ1_EN 0 0x2902 5 0 2 DC_GPIO_VARY_BL_OTG_VSYNC_EN 20 20 DC_GPIO_VARY_BL_OTG_VSYNC_SEL 21 23 DC_GPIO_BLON_OTG_VSYNC_EN 25 25 DC_GPIO_BLON_OTG_VSYNC_SEL 26 28 DC_GPIO_VARY_BL_GENERICA_EN 29 29 regDC_GPIO_TX12_EN 0 0x2915 7 0 2 DC_GPIO_GENERICA_TX12_EN 3 3 DC_GPIO_GENERICB_TX12_EN 4 4 DC_GPIO_GENERICC_TX12_EN 5 5 DC_GPIO_GENERICD_TX12_EN 6 6 DC_GPIO_GENERICE_TX12_EN 7 7 DC_GPIO_GENERICF_TX12_EN 8 8 DC_GPIO_GENERICG_TX12_EN 9 9 regDC_GPIO_AUX_CTRL_0 0 0x2916 21 0 2 DC_GPIO_AUX1_FALLSLEWSEL 0 1 DC_GPIO_AUX2_FALLSLEWSEL 2 3 DC_GPIO_AUX3_FALLSLEWSEL 4 5 DC_GPIO_AUX4_FALLSLEWSEL 6 7 DC_GPIO_AUX5_FALLSLEWSEL 8 9 DC_GPIO_AUX6_FALLSLEWSEL 10 11 DC_GPIO_DDCVGA_FALLSLEWSEL 12 13 DC_GPIO_AUX1_SPIKERCEN 16 16 DC_GPIO_AUX2_SPIKERCEN 17 17 DC_GPIO_AUX3_SPIKERCEN 18 18 DC_GPIO_AUX4_SPIKERCEN 19 19 DC_GPIO_AUX5_SPIKERCEN 20 20 DC_GPIO_AUX6_SPIKERCEN 21 21 DC_GPIO_DDCVGA_SPIKERCEN 22 22 DC_GPIO_AUX1_SPIKERCSEL 24 24 DC_GPIO_AUX2_SPIKERCSEL 25 25 DC_GPIO_AUX3_SPIKERCSEL 26 26 DC_GPIO_AUX4_SPIKERCSEL 27 27 DC_GPIO_AUX5_SPIKERCSEL 28 28 DC_GPIO_AUX6_SPIKERCSEL 29 29 DC_GPIO_DDCVGA_SPIKERCSEL 30 30 regDC_GPIO_AUX_CTRL_1 0 0x2917 22 0 2 DC_GPIO_AUX_CSEL_0P9 0 0 DC_GPIO_AUX_CSEL_1P1 1 1 DC_GPIO_AUX_RSEL_0P9 2 2 DC_GPIO_AUX_RSEL_1P1 3 3 DC_GPIO_I2C_CSEL_0P9 4 4 DC_GPIO_I2C_CSEL_1P1 5 5 DC_GPIO_I2C_RSEL_0P9 6 6 DC_GPIO_I2C_RSEL_1P1 7 7 DC_GPIO_AUX_BIASCRTEN 8 8 DC_GPIO_I2C_BIASCRTEN 9 9 DC_GPIO_AUX_RESBIASEN 10 10 DC_GPIO_I2C_RESBIASEN 11 11 DC_GPIO_AUX1_COMPSEL 12 12 DC_GPIO_DDCVGA_SPARE 14 15 DC_GPIO_DDCVGA_SLEWN 18 18 DC_GPIO_DDCVGA_RXSEL 20 21 DC_GPIO_AUX2_COMPSEL 25 25 DC_GPIO_AUX3_COMPSEL 26 26 DC_GPIO_AUX4_COMPSEL 27 27 DC_GPIO_AUX5_COMPSEL 28 28 DC_GPIO_AUX6_COMPSEL 29 29 DC_GPIO_DDCVGA_COMPSEL 30 30 regDC_GPIO_AUX_CTRL_2 0 0x2918 21 0 2 DC_GPIO_HPD12_FALLSLEWSEL 0 1 DC_GPIO_HPD34_FALLSLEWSEL 2 3 DC_GPIO_HPD56_FALLSLEWSEL 4 5 DC_GPIO_HPD12_SPIKERCEN 8 8 DC_GPIO_HPD34_SPIKERCEN 9 9 DC_GPIO_HPD56_SPIKERCEN 10 10 DC_GPIO_HPD12_SPIKERCSEL 12 12 DC_GPIO_HPD34_SPIKERCSEL 13 13 DC_GPIO_HPD56_SPIKERCSEL 14 14 DC_GPIO_HPD_CSEL_0P9 16 16 DC_GPIO_HPD_CSEL_1P1 17 17 DC_GPIO_HPD_RSEL_0P9 18 18 DC_GPIO_HPD_RSEL_1P1 19 19 DC_GPIO_HPD_BIASCRTEN 20 20 DC_GPIO_HPD12_SLEWN 24 24 DC_GPIO_HPD34_SLEWN 25 25 DC_GPIO_HPD56_SLEWN 26 26 DC_GPIO_HPD_RESBIASEN 27 27 DC_GPIO_HPD12_COMPSEL 28 28 DC_GPIO_HPD34_COMPSEL 29 29 DC_GPIO_HPD56_COMPSEL 30 30 regDC_GPIO_RXEN 0 0x2919 19 0 2 DC_GPIO_GENERICA_RXEN 0 0 DC_GPIO_GENERICB_RXEN 1 1 DC_GPIO_GENERICC_RXEN 2 2 DC_GPIO_GENERICD_RXEN 3 3 DC_GPIO_GENERICE_RXEN 4 4 DC_GPIO_GENERICF_RXEN 5 5 DC_GPIO_GENERICG_RXEN 6 6 DC_GPIO_HSYNCA_RXEN 8 8 DC_GPIO_VSYNCA_RXEN 9 9 DC_GPIO_GENLK_CLK_RXEN 10 10 DC_GPIO_GENLK_VSYNC_RXEN 11 11 DC_GPIO_SWAPLOCK_A_RXEN 12 12 DC_GPIO_SWAPLOCK_B_RXEN 13 13 DC_GPIO_HPD1_RXEN 14 14 DC_GPIO_HPD2_RXEN 15 15 DC_GPIO_HPD3_RXEN 16 16 DC_GPIO_HPD4_RXEN 17 17 DC_GPIO_HPD5_RXEN 18 18 DC_GPIO_HPD6_RXEN 19 19 regDC_GPIO_PULLUPEN 0 0x291a 15 0 2 DC_GPIO_GENERICA_PU_EN 0 0 DC_GPIO_GENERICB_PU_EN 1 1 DC_GPIO_GENERICC_PU_EN 2 2 DC_GPIO_GENERICD_PU_EN 3 3 DC_GPIO_GENERICE_PU_EN 4 4 DC_GPIO_GENERICF_PU_EN 5 5 DC_GPIO_GENERICG_PU_EN 6 6 DC_GPIO_HSYNCA_PU_EN 8 8 DC_GPIO_VSYNCA_PU_EN 9 9 DC_GPIO_HPD1_PU_EN 14 14 DC_GPIO_HPD2_PU_EN 15 15 DC_GPIO_HPD3_PU_EN 16 16 DC_GPIO_HPD4_PU_EN 17 17 DC_GPIO_HPD5_PU_EN 18 18 DC_GPIO_HPD6_PU_EN 19 19 regDC_GPIO_AUX_CTRL_3 0 0x291b 18 0 2 AUX1_NEN_RTERM 0 0 AUX2_NEN_RTERM 1 1 AUX3_NEN_RTERM 2 2 AUX4_NEN_RTERM 3 3 AUX5_NEN_RTERM 4 4 AUX6_NEN_RTERM 5 5 AUX1_DP_DN_SWAP 8 8 AUX2_DP_DN_SWAP 9 9 AUX3_DP_DN_SWAP 10 10 AUX4_DP_DN_SWAP 11 11 AUX5_DP_DN_SWAP 12 12 AUX6_DP_DN_SWAP 13 13 AUX1_HYS_TUNE 16 17 AUX2_HYS_TUNE 18 19 AUX3_HYS_TUNE 20 21 AUX4_HYS_TUNE 22 23 AUX5_HYS_TUNE 24 25 AUX6_HYS_TUNE 26 27 regDC_GPIO_AUX_CTRL_4 0 0x291c 6 0 2 AUX1_AUX_CTRL 0 3 AUX2_AUX_CTRL 4 7 AUX3_AUX_CTRL 8 11 AUX4_AUX_CTRL 12 15 AUX5_AUX_CTRL 16 19 AUX6_AUX_CTRL 20 23 regDC_GPIO_AUX_CTRL_5 0 0x291d 24 0 2 AUX1_VOD_TUNE 0 1 AUX2_VOD_TUNE 2 3 AUX3_VOD_TUNE 4 5 AUX4_VOD_TUNE 6 7 AUX5_VOD_TUNE 8 9 AUX6_VOD_TUNE 10 11 DDC_PAD1_I2CMODE 12 12 DDC_PAD2_I2CMODE 13 13 DDC_PAD3_I2CMODE 14 14 DDC_PAD4_I2CMODE 15 15 DDC_PAD5_I2CMODE 16 16 DDC_PAD6_I2CMODE 17 17 DDC1_I2C_VPH_1V2_EN 18 18 DDC2_I2C_VPH_1V2_EN 19 19 DDC3_I2C_VPH_1V2_EN 20 20 DDC4_I2C_VPH_1V2_EN 21 21 DDC5_I2C_VPH_1V2_EN 22 22 DDC6_I2C_VPH_1V2_EN 23 23 DDC1_PAD_I2C_CTRL 24 24 DDC2_PAD_I2C_CTRL 25 25 DDC3_PAD_I2C_CTRL 26 26 DDC4_PAD_I2C_CTRL 27 27 DDC5_PAD_I2C_CTRL 28 28 DDC6_PAD_I2C_CTRL 29 29 regAUXI2C_PAD_ALL_PWR_OK 0 0x291e 6 0 2 AUXI2C_PHY1_ALL_PWR_OK 0 0 AUXI2C_PHY2_ALL_PWR_OK 1 1 AUXI2C_PHY3_ALL_PWR_OK 2 2 AUXI2C_PHY4_ALL_PWR_OK 3 3 AUXI2C_PHY5_ALL_PWR_OK 4 4 AUXI2C_PHY6_ALL_PWR_OK 5 5 regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED0 0 0x2928 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED1 0 0x2929 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED2 0 0x292a 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED3 0 0x292b 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED4 0 0x292c 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED5 0 0x292d 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED6 0 0x292e 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED7 0 0x292f 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED8 0 0x2930 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED9 0 0x2931 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED10 0 0x2932 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED11 0 0x2933 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED12 0 0x2934 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED13 0 0x2935 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED14 0 0x2936 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED15 0 0x2937 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED16 0 0x2938 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED17 0 0x2939 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED18 0 0x293a 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED19 0 0x293b 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED20 0 0x293c 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED21 0 0x293d 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED22 0 0x293e 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED23 0 0x293f 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED24 0 0x2940 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED25 0 0x2941 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED26 0 0x2942 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED27 0 0x2943 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED28 0 0x2944 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED29 0 0x2945 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED30 0 0x2946 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED31 0 0x2947 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED32 0 0x2948 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED33 0 0x2949 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED34 0 0x294a 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED35 0 0x294b 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED36 0 0x294c 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED37 0 0x294d 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED38 0 0x294e 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED39 0 0x294f 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED40 0 0x2950 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED41 0 0x2951 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED42 0 0x2952 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED43 0 0x2953 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED44 0 0x2954 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED45 0 0x2955 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED46 0 0x2956 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED47 0 0x2957 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED48 0 0x2958 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED49 0 0x2959 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED50 0 0x295a 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED51 0 0x295b 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED52 0 0x295c 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED53 0 0x295d 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED54 0 0x295e 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED55 0 0x295f 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED56 0 0x2960 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED57 0 0x2961 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED0 0 0x2a00 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED1 0 0x2a01 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED2 0 0x2a02 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED3 0 0x2a03 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED4 0 0x2a04 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED5 0 0x2a05 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED6 0 0x2a06 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED7 0 0x2a07 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED8 0 0x2a08 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED9 0 0x2a09 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED10 0 0x2a0a 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED11 0 0x2a0b 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED12 0 0x2a0c 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED13 0 0x2a0d 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED14 0 0x2a0e 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED15 0 0x2a0f 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED16 0 0x2a10 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED17 0 0x2a11 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED18 0 0x2a12 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED19 0 0x2a13 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED20 0 0x2a14 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED21 0 0x2a15 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED22 0 0x2a16 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED23 0 0x2a17 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED24 0 0x2a18 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED25 0 0x2a19 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED26 0 0x2a1a 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED27 0 0x2a1b 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED28 0 0x2a1c 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED29 0 0x2a1d 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED30 0 0x2a1e 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED31 0 0x2a1f 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED32 0 0x2a20 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED33 0 0x2a21 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED34 0 0x2a22 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED35 0 0x2a23 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED36 0 0x2a24 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED37 0 0x2a25 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED38 0 0x2a26 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED39 0 0x2a27 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED40 0 0x2a28 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED41 0 0x2a29 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED42 0 0x2a2a 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED43 0 0x2a2b 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED44 0 0x2a2c 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED45 0 0x2a2d 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED46 0 0x2a2e 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED47 0 0x2a2f 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED48 0 0x2a30 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED49 0 0x2a31 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED50 0 0x2a32 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED51 0 0x2a33 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED52 0 0x2a34 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED53 0 0x2a35 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED54 0 0x2a36 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED55 0 0x2a37 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED56 0 0x2a38 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED57 0 0x2a39 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED0 0 0x2ad8 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED1 0 0x2ad9 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED2 0 0x2ada 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED3 0 0x2adb 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED4 0 0x2adc 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED5 0 0x2add 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED6 0 0x2ade 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED7 0 0x2adf 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED8 0 0x2ae0 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED9 0 0x2ae1 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED10 0 0x2ae2 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED11 0 0x2ae3 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED12 0 0x2ae4 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED13 0 0x2ae5 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED14 0 0x2ae6 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED15 0 0x2ae7 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED16 0 0x2ae8 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED17 0 0x2ae9 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED18 0 0x2aea 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED19 0 0x2aeb 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED20 0 0x2aec 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED21 0 0x2aed 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED22 0 0x2aee 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED23 0 0x2aef 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED24 0 0x2af0 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED25 0 0x2af1 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED26 0 0x2af2 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED27 0 0x2af3 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED28 0 0x2af4 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED29 0 0x2af5 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED30 0 0x2af6 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED31 0 0x2af7 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED32 0 0x2af8 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED33 0 0x2af9 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED34 0 0x2afa 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED35 0 0x2afb 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED36 0 0x2afc 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED37 0 0x2afd 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED38 0 0x2afe 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED39 0 0x2aff 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED40 0 0x2b00 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED41 0 0x2b01 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED42 0 0x2b02 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED43 0 0x2b03 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED44 0 0x2b04 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED45 0 0x2b05 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED46 0 0x2b06 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED47 0 0x2b07 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED48 0 0x2b08 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED49 0 0x2b09 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED50 0 0x2b0a 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED51 0 0x2b0b 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED52 0 0x2b0c 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED53 0 0x2b0d 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED54 0 0x2b0e 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED55 0 0x2b0f 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED56 0 0x2b10 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED57 0 0x2b11 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED0 0 0x2bb0 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED1 0 0x2bb1 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED2 0 0x2bb2 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED3 0 0x2bb3 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED4 0 0x2bb4 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED5 0 0x2bb5 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED6 0 0x2bb6 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED7 0 0x2bb7 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED8 0 0x2bb8 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED9 0 0x2bb9 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED10 0 0x2bba 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED11 0 0x2bbb 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED12 0 0x2bbc 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED13 0 0x2bbd 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED14 0 0x2bbe 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED15 0 0x2bbf 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED16 0 0x2bc0 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED17 0 0x2bc1 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED18 0 0x2bc2 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED19 0 0x2bc3 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED20 0 0x2bc4 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED21 0 0x2bc5 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED22 0 0x2bc6 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED23 0 0x2bc7 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED24 0 0x2bc8 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED25 0 0x2bc9 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED26 0 0x2bca 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED27 0 0x2bcb 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED28 0 0x2bcc 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED29 0 0x2bcd 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED30 0 0x2bce 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED31 0 0x2bcf 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED32 0 0x2bd0 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED33 0 0x2bd1 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED34 0 0x2bd2 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED35 0 0x2bd3 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED36 0 0x2bd4 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED37 0 0x2bd5 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED38 0 0x2bd6 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED39 0 0x2bd7 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED40 0 0x2bd8 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED41 0 0x2bd9 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED42 0 0x2bda 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED43 0 0x2bdb 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED44 0 0x2bdc 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED45 0 0x2bdd 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED46 0 0x2bde 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED47 0 0x2bdf 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED48 0 0x2be0 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED49 0 0x2be1 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED50 0 0x2be2 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED51 0 0x2be3 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED52 0 0x2be4 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED53 0 0x2be5 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED54 0 0x2be6 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED55 0 0x2be7 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED56 0 0x2be8 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED57 0 0x2be9 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED0 0 0x2c88 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED1 0 0x2c89 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED2 0 0x2c8a 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED3 0 0x2c8b 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED4 0 0x2c8c 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED5 0 0x2c8d 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED6 0 0x2c8e 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED7 0 0x2c8f 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED8 0 0x2c90 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED9 0 0x2c91 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED10 0 0x2c92 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED11 0 0x2c93 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED12 0 0x2c94 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED13 0 0x2c95 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED14 0 0x2c96 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED15 0 0x2c97 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED16 0 0x2c98 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED17 0 0x2c99 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED18 0 0x2c9a 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED19 0 0x2c9b 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED20 0 0x2c9c 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED21 0 0x2c9d 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED22 0 0x2c9e 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED23 0 0x2c9f 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED24 0 0x2ca0 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED25 0 0x2ca1 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED26 0 0x2ca2 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED27 0 0x2ca3 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED28 0 0x2ca4 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED29 0 0x2ca5 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED30 0 0x2ca6 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED31 0 0x2ca7 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED32 0 0x2ca8 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED33 0 0x2ca9 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED34 0 0x2caa 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED35 0 0x2cab 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED36 0 0x2cac 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED37 0 0x2cad 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED38 0 0x2cae 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED39 0 0x2caf 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED40 0 0x2cb0 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED41 0 0x2cb1 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED42 0 0x2cb2 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED43 0 0x2cb3 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED44 0 0x2cb4 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED45 0 0x2cb5 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED46 0 0x2cb6 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED47 0 0x2cb7 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED48 0 0x2cb8 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED49 0 0x2cb9 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED50 0 0x2cba 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED51 0 0x2cbb 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED52 0 0x2cbc 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED53 0 0x2cbd 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED54 0 0x2cbe 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED55 0 0x2cbf 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED56 0 0x2cc0 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED57 0 0x2cc1 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regPWRSEQ0_DC_GPIO_PWRSEQ_EN 0 0x2f10 3 0 2 DC_GPIO_VARY_BL_EN 0 0 DC_GPIO_DIGON_EN 8 8 DC_GPIO_BLON_EN 16 16 regPWRSEQ0_DC_GPIO_PWRSEQ_CTRL 0 0x2f11 11 0 2 DC_GPIO_VARY_BL_TX12_EN 0 0 DC_GPIO_DIGON_TX12_EN 1 1 DC_GPIO_BLON_TX12_EN 2 2 DC_GPIO_VARY_BL_RXEN 3 3 DC_GPIO_DIGON_RXEN 4 4 DC_GPIO_BLON_RXEN 5 5 DC_GPIO_VARY_BL_PU_EN 6 6 DC_GPIO_DIGON_PU_EN 7 7 DC_GPIO_BLON_PU_EN 8 8 PWRSEQ_STRENGTH_SN 16 19 PWRSEQ_STRENGTH_SP 20 23 regPWRSEQ0_DC_GPIO_PWRSEQ_MASK 0 0x2f12 9 0 2 DC_GPIO_VARY_BL_MASK 0 0 DC_GPIO_VARY_BL_PD_DIS 4 4 DC_GPIO_VARY_BL_RECV 6 7 DC_GPIO_DIGON_MASK 8 8 DC_GPIO_DIGON_PD_DIS 12 12 DC_GPIO_DIGON_RECV 14 15 DC_GPIO_BLON_MASK 16 16 DC_GPIO_BLON_PD_DIS 20 20 DC_GPIO_BLON_RECV 22 23 regPWRSEQ0_DC_GPIO_PWRSEQ_A_Y 0 0x2f13 6 0 2 DC_GPIO_VARY_BL_A 0 0 DC_GPIO_VARY_BL_Y 1 1 DC_GPIO_DIGON_A 8 8 DC_GPIO_DIGON_Y 9 9 DC_GPIO_BLON_A 16 16 DC_GPIO_BLON_Y 17 17 regPWRSEQ0_PANEL_PWRSEQ_CNTL 0 0x2f14 11 0 2 PANEL_PWRSEQ_EN 0 0 PANEL_PWRSEQ_TARGET_STATE 4 4 PANEL_SYNCEN 8 8 PANEL_SYNCEN_OVRD 9 9 PANEL_SYNCEN_POL 10 10 PANEL_DIGON 16 16 PANEL_DIGON_OVRD 17 17 PANEL_DIGON_POL 18 18 PANEL_BLON 24 24 PANEL_BLON_OVRD 25 25 PANEL_BLON_POL 26 26 regPWRSEQ0_PANEL_PWRSEQ_STATE 0 0x2f15 6 0 2 PANEL_PWRSEQ_TARGET_STATE_R 0 0 PANEL_PWRSEQ_DIGON 1 1 PANEL_PWRSEQ_SYNCEN 2 2 PANEL_PWRSEQ_BLON 3 3 PANEL_PWRSEQ_DONE 4 4 PANEL_PWRSEQ_STATE 8 11 regPWRSEQ0_PANEL_PWRSEQ_DELAY1 0 0x2f16 4 0 2 PANEL_PWRUP_DELAY1 0 7 PANEL_PWRUP_DELAY2 8 15 PANEL_PWRDN_DELAY1 16 23 PANEL_PWRDN_DELAY2 24 31 regPWRSEQ0_PANEL_PWRSEQ_DELAY2 0 0x2f17 4 0 2 PANEL_PWRDN_MIN_LENGTH 0 7 PANEL_PWRUP_DELAY3 8 15 PANEL_PWRDN_DELAY3 16 23 PANEL_VARY_BL_OVERRIDE_EN 24 24 regPWRSEQ0_PANEL_PWRSEQ_REF_DIV1 0 0x2f18 2 0 2 PANEL_PWRSEQ_REF_DIV 0 11 BL_PWM_REF_DIV 16 31 regPWRSEQ0_BL_PWM_CNTL 0 0x2f19 6 0 2 BL_ACTIVE_INT_FRAC_CNT 0 15 BL_PWM_EN_EQ_ZERO 19 19 FRAME_START_EVENT_RECOGNIZED 20 20 RECOGNIZE_POST_FRAME_START_DELAY_BEFORE_UPDATE 21 21 BL_PWM_FRACTIONAL_EN 30 30 BL_PWM_EN 31 31 regPWRSEQ0_BL_PWM_CNTL2 0 0x2f1a 4 0 2 BL_PWM_POST_FRAME_START_DELAY_BEFORE_UPDATE 0 15 DBG_BL_PWM_INPUT_REFCLK_SELECT 28 29 BL_PWM_OVERRIDE_BL_OUT_ENABLE 30 30 BL_PWM_OVERRIDE_PANEL_PWRSEQ_EN 31 31 regPWRSEQ0_BL_PWM_PERIOD_CNTL 0 0x2f1b 2 0 2 BL_PWM_PERIOD 0 15 BL_PWM_PERIOD_BITCNT 16 19 regPWRSEQ0_BL_PWM_GRP1_REG_LOCK 0 0x2f1c 5 0 2 BL_PWM_GRP1_REG_LOCK 0 0 BL_PWM_GRP1_REG_UPDATE_PENDING 8 8 BL_PWM_GRP1_UPDATE_AT_FRAME_START 16 16 BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN 24 24 BL_PWM_GRP1_IGNORE_MASTER_LOCK_EN 31 31 regPWRSEQ0_PANEL_PWRSEQ_REF_DIV2 0 0x2f1d 3 0 2 XTAL_REF_DIV 0 6 MICROSECOND_TIME_BASE_DIV 8 14 XTAL_REF_START_ON_VARY_BL_ACTIVE 16 16 regPWRSEQ0_PWRSEQ_SPARE 0 0x2f21 1 0 2 PWRSEQ_SPARE 0 31 regPWRSEQ1_DC_GPIO_PWRSEQ_EN 0 0x2f7c 3 0 2 DC_GPIO_VARY_BL_EN 0 0 DC_GPIO_DIGON_EN 8 8 DC_GPIO_BLON_EN 16 16 regPWRSEQ1_DC_GPIO_PWRSEQ_CTRL 0 0x2f7d 11 0 2 DC_GPIO_VARY_BL_TX12_EN 0 0 DC_GPIO_DIGON_TX12_EN 1 1 DC_GPIO_BLON_TX12_EN 2 2 DC_GPIO_VARY_BL_RXEN 3 3 DC_GPIO_DIGON_RXEN 4 4 DC_GPIO_BLON_RXEN 5 5 DC_GPIO_VARY_BL_PU_EN 6 6 DC_GPIO_DIGON_PU_EN 7 7 DC_GPIO_BLON_PU_EN 8 8 PWRSEQ_STRENGTH_SN 16 19 PWRSEQ_STRENGTH_SP 20 23 regPWRSEQ1_DC_GPIO_PWRSEQ_MASK 0 0x2f7e 9 0 2 DC_GPIO_VARY_BL_MASK 0 0 DC_GPIO_VARY_BL_PD_DIS 4 4 DC_GPIO_VARY_BL_RECV 6 7 DC_GPIO_DIGON_MASK 8 8 DC_GPIO_DIGON_PD_DIS 12 12 DC_GPIO_DIGON_RECV 14 15 DC_GPIO_BLON_MASK 16 16 DC_GPIO_BLON_PD_DIS 20 20 DC_GPIO_BLON_RECV 22 23 regPWRSEQ1_DC_GPIO_PWRSEQ_A_Y 0 0x2f7f 6 0 2 DC_GPIO_VARY_BL_A 0 0 DC_GPIO_VARY_BL_Y 1 1 DC_GPIO_DIGON_A 8 8 DC_GPIO_DIGON_Y 9 9 DC_GPIO_BLON_A 16 16 DC_GPIO_BLON_Y 17 17 regPWRSEQ1_PANEL_PWRSEQ_CNTL 0 0x2f80 11 0 2 PANEL_PWRSEQ_EN 0 0 PANEL_PWRSEQ_TARGET_STATE 4 4 PANEL_SYNCEN 8 8 PANEL_SYNCEN_OVRD 9 9 PANEL_SYNCEN_POL 10 10 PANEL_DIGON 16 16 PANEL_DIGON_OVRD 17 17 PANEL_DIGON_POL 18 18 PANEL_BLON 24 24 PANEL_BLON_OVRD 25 25 PANEL_BLON_POL 26 26 regPWRSEQ1_PANEL_PWRSEQ_STATE 0 0x2f81 6 0 2 PANEL_PWRSEQ_TARGET_STATE_R 0 0 PANEL_PWRSEQ_DIGON 1 1 PANEL_PWRSEQ_SYNCEN 2 2 PANEL_PWRSEQ_BLON 3 3 PANEL_PWRSEQ_DONE 4 4 PANEL_PWRSEQ_STATE 8 11 regPWRSEQ1_PANEL_PWRSEQ_DELAY1 0 0x2f82 4 0 2 PANEL_PWRUP_DELAY1 0 7 PANEL_PWRUP_DELAY2 8 15 PANEL_PWRDN_DELAY1 16 23 PANEL_PWRDN_DELAY2 24 31 regPWRSEQ1_PANEL_PWRSEQ_DELAY2 0 0x2f83 4 0 2 PANEL_PWRDN_MIN_LENGTH 0 7 PANEL_PWRUP_DELAY3 8 15 PANEL_PWRDN_DELAY3 16 23 PANEL_VARY_BL_OVERRIDE_EN 24 24 regPWRSEQ1_PANEL_PWRSEQ_REF_DIV1 0 0x2f84 2 0 2 PANEL_PWRSEQ_REF_DIV 0 11 BL_PWM_REF_DIV 16 31 regPWRSEQ1_BL_PWM_CNTL 0 0x2f85 6 0 2 BL_ACTIVE_INT_FRAC_CNT 0 15 BL_PWM_EN_EQ_ZERO 19 19 FRAME_START_EVENT_RECOGNIZED 20 20 RECOGNIZE_POST_FRAME_START_DELAY_BEFORE_UPDATE 21 21 BL_PWM_FRACTIONAL_EN 30 30 BL_PWM_EN 31 31 regPWRSEQ1_BL_PWM_CNTL2 0 0x2f86 4 0 2 BL_PWM_POST_FRAME_START_DELAY_BEFORE_UPDATE 0 15 DBG_BL_PWM_INPUT_REFCLK_SELECT 28 29 BL_PWM_OVERRIDE_BL_OUT_ENABLE 30 30 BL_PWM_OVERRIDE_PANEL_PWRSEQ_EN 31 31 regPWRSEQ1_BL_PWM_PERIOD_CNTL 0 0x2f87 2 0 2 BL_PWM_PERIOD 0 15 BL_PWM_PERIOD_BITCNT 16 19 regPWRSEQ1_BL_PWM_GRP1_REG_LOCK 0 0x2f88 5 0 2 BL_PWM_GRP1_REG_LOCK 0 0 BL_PWM_GRP1_REG_UPDATE_PENDING 8 8 BL_PWM_GRP1_UPDATE_AT_FRAME_START 16 16 BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN 24 24 BL_PWM_GRP1_IGNORE_MASTER_LOCK_EN 31 31 regPWRSEQ1_PANEL_PWRSEQ_REF_DIV2 0 0x2f89 3 0 2 XTAL_REF_DIV 0 6 MICROSECOND_TIME_BASE_DIV 8 14 XTAL_REF_START_ON_VARY_BL_ACTIVE 16 16 regPWRSEQ1_PWRSEQ_SPARE 0 0x2f8d 1 0 2 PWRSEQ_SPARE 0 31 regDSCC0_DSCC_CONFIG0 0 0x300a 4 0 2 ICH_RESET_AT_END_OF_LINE 0 3 NUMBER_OF_SLICES_PER_LINE 4 5 ALTERNATE_ICH_ENCODING_EN 8 8 NUMBER_OF_SLICES_IN_VERTICAL_DIRECTION 16 31 regDSCC0_DSCC_CONFIG1 0 0x300b 1 0 2 DSCC_RATE_CONTROL_BUFFER_MODEL_SIZE 0 17 regDSCC0_DSCC_STATUS 0 0x300c 1 0 2 DSCC_DOUBLE_BUFFER_REG_UPDATE_PENDING 0 0 regDSCC0_DSCC_INTERRUPT_CONTROL_STATUS 0 0x300d 24 0 2 DSCC_RATE_BUFFER0_OVERFLOW_OCCURRED 0 0 DSCC_RATE_BUFFER1_OVERFLOW_OCCURRED 1 1 DSCC_RATE_BUFFER2_OVERFLOW_OCCURRED 2 2 DSCC_RATE_BUFFER3_OVERFLOW_OCCURRED 3 3 DSCC_RATE_BUFFER0_UNDERFLOW_OCCURRED 4 4 DSCC_RATE_BUFFER1_UNDERFLOW_OCCURRED 5 5 DSCC_RATE_BUFFER2_UNDERFLOW_OCCURRED 6 6 DSCC_RATE_BUFFER3_UNDERFLOW_OCCURRED 7 7 DSCC_RATE_CONTROL_BUFFER_MODEL0_OVERFLOW_OCCURRED 8 8 DSCC_RATE_CONTROL_BUFFER_MODEL1_OVERFLOW_OCCURRED 9 9 DSCC_RATE_CONTROL_BUFFER_MODEL2_OVERFLOW_OCCURRED 10 10 DSCC_RATE_CONTROL_BUFFER_MODEL3_OVERFLOW_OCCURRED 11 11 DSCC_RATE_BUFFER0_OVERFLOW_OCCURRED_INT_EN 16 16 DSCC_RATE_BUFFER1_OVERFLOW_OCCURRED_INT_EN 17 17 DSCC_RATE_BUFFER2_OVERFLOW_OCCURRED_INT_EN 18 18 DSCC_RATE_BUFFER3_OVERFLOW_OCCURRED_INT_EN 19 19 DSCC_RATE_BUFFER0_UNDERFLOW_OCCURRED_INT_EN 20 20 DSCC_RATE_BUFFER1_UNDERFLOW_OCCURRED_INT_EN 21 21 DSCC_RATE_BUFFER2_UNDERFLOW_OCCURRED_INT_EN 22 22 DSCC_RATE_BUFFER3_UNDERFLOW_OCCURRED_INT_EN 23 23 DSCC_RATE_CONTROL_BUFFER_MODEL0_OVERFLOW_OCCURRED_INT_EN 24 24 DSCC_RATE_CONTROL_BUFFER_MODEL1_OVERFLOW_OCCURRED_INT_EN 25 25 DSCC_RATE_CONTROL_BUFFER_MODEL2_OVERFLOW_OCCURRED_INT_EN 26 26 DSCC_RATE_CONTROL_BUFFER_MODEL3_OVERFLOW_OCCURRED_INT_EN 27 27 regDSCC0_DSCC_PPS_CONFIG0 0 0x300e 5 0 2 DSC_VERSION_MINOR 0 3 DSC_VERSION_MAJOR 4 7 PPS_IDENTIFIER 8 15 LINEBUF_DEPTH 24 27 BITS_PER_COMPONENT 28 31 regDSCC0_DSCC_PPS_CONFIG1 0 0x300f 8 0 2 BITS_PER_PIXEL 0 9 VBR_ENABLE 10 10 SIMPLE_422 11 11 CONVERT_RGB 12 12 BLOCK_PRED_ENABLE 13 13 NATIVE_422 14 14 NATIVE_420 15 15 CHUNK_SIZE 16 31 regDSCC0_DSCC_PPS_CONFIG2 0 0x3010 2 0 2 PIC_WIDTH 0 15 PIC_HEIGHT 16 31 regDSCC0_DSCC_PPS_CONFIG3 0 0x3011 2 0 2 SLICE_WIDTH 0 15 SLICE_HEIGHT 16 31 regDSCC0_DSCC_PPS_CONFIG4 0 0x3012 2 0 2 INITIAL_XMIT_DELAY 0 9 INITIAL_DEC_DELAY 16 31 regDSCC0_DSCC_PPS_CONFIG5 0 0x3013 2 0 2 INITIAL_SCALE_VALUE 0 5 SCALE_INCREMENT_INTERVAL 16 31 regDSCC0_DSCC_PPS_CONFIG6 0 0x3014 3 0 2 SCALE_DECREMENT_INTERVAL 0 11 FIRST_LINE_BPG_OFFSET 16 20 SECOND_LINE_BPG_OFFSET 24 28 regDSCC0_DSCC_PPS_CONFIG7 0 0x3015 2 0 2 NFL_BPG_OFFSET 0 15 SLICE_BPG_OFFSET 16 31 regDSCC0_DSCC_PPS_CONFIG8 0 0x3016 2 0 2 NSL_BPG_OFFSET 0 15 SECOND_LINE_OFFSET_ADJ 16 31 regDSCC0_DSCC_PPS_CONFIG9 0 0x3017 2 0 2 INITIAL_OFFSET 0 15 FINAL_OFFSET 16 31 regDSCC0_DSCC_PPS_CONFIG10 0 0x3018 3 0 2 FLATNESS_MIN_QP 0 4 FLATNESS_MAX_QP 8 12 RC_MODEL_SIZE 16 31 regDSCC0_DSCC_PPS_CONFIG11 0 0x3019 5 0 2 RC_EDGE_FACTOR 0 3 RC_QUANT_INCR_LIMIT0 8 12 RC_QUANT_INCR_LIMIT1 16 20 RC_TGT_OFFSET_LO 24 27 RC_TGT_OFFSET_HI 28 31 regDSCC0_DSCC_PPS_CONFIG12 0 0x301a 4 0 2 RC_BUF_THRESH0 0 7 RC_BUF_THRESH1 8 15 RC_BUF_THRESH2 16 23 RC_BUF_THRESH3 24 31 regDSCC0_DSCC_PPS_CONFIG13 0 0x301b 4 0 2 RC_BUF_THRESH4 0 7 RC_BUF_THRESH5 8 15 RC_BUF_THRESH6 16 23 RC_BUF_THRESH7 24 31 regDSCC0_DSCC_PPS_CONFIG14 0 0x301c 4 0 2 RC_BUF_THRESH8 0 7 RC_BUF_THRESH9 8 15 RC_BUF_THRESH10 16 23 RC_BUF_THRESH11 24 31 regDSCC0_DSCC_PPS_CONFIG15 0 0x301d 5 0 2 RC_BUF_THRESH12 0 7 RC_BUF_THRESH13 8 15 RANGE_MIN_QP0 16 20 RANGE_MAX_QP0 21 25 RANGE_BPG_OFFSET0 26 31 regDSCC0_DSCC_PPS_CONFIG16 0 0x301e 6 0 2 RANGE_MIN_QP1 0 4 RANGE_MAX_QP1 5 9 RANGE_BPG_OFFSET1 10 15 RANGE_MIN_QP2 16 20 RANGE_MAX_QP2 21 25 RANGE_BPG_OFFSET2 26 31 regDSCC0_DSCC_PPS_CONFIG17 0 0x301f 6 0 2 RANGE_MIN_QP3 0 4 RANGE_MAX_QP3 5 9 RANGE_BPG_OFFSET3 10 15 RANGE_MIN_QP4 16 20 RANGE_MAX_QP4 21 25 RANGE_BPG_OFFSET4 26 31 regDSCC0_DSCC_PPS_CONFIG18 0 0x3020 6 0 2 RANGE_MIN_QP5 0 4 RANGE_MAX_QP5 5 9 RANGE_BPG_OFFSET5 10 15 RANGE_MIN_QP6 16 20 RANGE_MAX_QP6 21 25 RANGE_BPG_OFFSET6 26 31 regDSCC0_DSCC_PPS_CONFIG19 0 0x3021 6 0 2 RANGE_MIN_QP7 0 4 RANGE_MAX_QP7 5 9 RANGE_BPG_OFFSET7 10 15 RANGE_MIN_QP8 16 20 RANGE_MAX_QP8 21 25 RANGE_BPG_OFFSET8 26 31 regDSCC0_DSCC_PPS_CONFIG20 0 0x3022 6 0 2 RANGE_MIN_QP9 0 4 RANGE_MAX_QP9 5 9 RANGE_BPG_OFFSET9 10 15 RANGE_MIN_QP10 16 20 RANGE_MAX_QP10 21 25 RANGE_BPG_OFFSET10 26 31 regDSCC0_DSCC_PPS_CONFIG21 0 0x3023 6 0 2 RANGE_MIN_QP11 0 4 RANGE_MAX_QP11 5 9 RANGE_BPG_OFFSET11 10 15 RANGE_MIN_QP12 16 20 RANGE_MAX_QP12 21 25 RANGE_BPG_OFFSET12 26 31 regDSCC0_DSCC_PPS_CONFIG22 0 0x3024 6 0 2 RANGE_MIN_QP13 0 4 RANGE_MAX_QP13 5 9 RANGE_BPG_OFFSET13 10 15 RANGE_MIN_QP14 16 20 RANGE_MAX_QP14 21 25 RANGE_BPG_OFFSET14 26 31 regDSCC0_DSCC_MEM_POWER_CONTROL 0 0x3025 7 0 2 DSCC_DEFAULT_MEM_LOW_POWER_STATE 0 1 DSCC_MEM_PWR_FORCE 4 5 DSCC_MEM_PWR_DIS 8 8 DSCC_MEM_PWR_STATE 16 17 DSCC_NATIVE_422_MEM_PWR_FORCE 20 21 DSCC_NATIVE_422_MEM_PWR_DIS 24 24 DSCC_NATIVE_422_MEM_PWR_STATE 28 29 regDSCC0_DSCC_R_Y_SQUARED_ERROR_LOWER 0 0x3026 1 0 2 DSCC_R_Y_SQUARED_ERROR_LOWER 0 31 regDSCC0_DSCC_R_Y_SQUARED_ERROR_UPPER 0 0x3027 1 0 2 DSCC_R_Y_SQUARED_ERROR_UPPER 0 31 regDSCC0_DSCC_G_CB_SQUARED_ERROR_LOWER 0 0x3028 1 0 2 DSCC_G_CB_SQUARED_ERROR_LOWER 0 31 regDSCC0_DSCC_G_CB_SQUARED_ERROR_UPPER 0 0x3029 1 0 2 DSCC_G_CB_SQUARED_ERROR_UPPER 0 31 regDSCC0_DSCC_B_CR_SQUARED_ERROR_LOWER 0 0x302a 1 0 2 DSCC_B_CR_SQUARED_ERROR_LOWER 0 31 regDSCC0_DSCC_B_CR_SQUARED_ERROR_UPPER 0 0x302b 1 0 2 DSCC_B_CR_SQUARED_ERROR_UPPER 0 31 regDSCC0_DSCC_MAX_ABS_ERROR0 0 0x302c 2 0 2 DSCC_R_Y_MAX_ABS_ERROR 0 15 DSCC_G_CB_MAX_ABS_ERROR 16 31 regDSCC0_DSCC_MAX_ABS_ERROR1 0 0x302d 1 0 2 DSCC_B_CR_MAX_ABS_ERROR 0 15 regDSCC0_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL 0 0x302e 1 0 2 DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL 0 17 regDSCC0_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL 0 0x302f 1 0 2 DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL 0 17 regDSCC0_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL 0 0x3030 1 0 2 DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL 0 17 regDSCC0_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL 0 0x3031 1 0 2 DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL 0 17 regDSCC0_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL 0 0x3032 1 0 2 DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL 0 17 regDSCC0_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL 0 0x3033 1 0 2 DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL 0 17 regDSCC0_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL 0 0x3034 1 0 2 DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL 0 17 regDSCC0_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL 0 0x3035 1 0 2 DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL 0 17 regDSCC0_DSCC_TEST_DEBUG_BUS_ROTATE 0 0x303a 4 0 2 DSCC_TEST_DEBUG_BUS0_ROTATE 0 4 DSCC_TEST_DEBUG_BUS1_ROTATE 8 12 DSCC_TEST_DEBUG_BUS2_ROTATE 16 20 DSCC_TEST_DEBUG_BUS3_ROTATE 24 28 regDSCCIF0_DSCCIF_CONFIG0 0 0x3005 6 0 2 INPUT_INTERFACE_UNDERFLOW_RECOVERY_EN 0 0 INPUT_INTERFACE_UNDERFLOW_OCCURRED_INT_EN 4 4 INPUT_INTERFACE_UNDERFLOW_OCCURRED_STATUS 8 8 INPUT_PIXEL_FORMAT 12 14 BITS_PER_COMPONENT 16 19 DOUBLE_BUFFER_REG_UPDATE_PENDING 24 24 regDSCCIF0_DSCCIF_CONFIG1 0 0x3006 2 0 2 PIC_WIDTH 0 15 PIC_HEIGHT 16 31 regDSC_TOP0_DSC_TOP_CONTROL 0 0x3000 3 0 2 DSC_CLOCK_EN 0 0 DSC_DISPCLK_R_GATE_DIS 4 4 DSC_DSCCLK_R_GATE_DIS 8 8 regDSC_TOP0_DSC_DEBUG_CONTROL 0 0x3001 2 0 2 DSC_DBG_EN 0 0 DSC_TEST_CLOCK_MUX_SEL 4 6 regDC_PERFMON19_PERFCOUNTER_CNTL 0 0x3050 11 0 2 PERFCOUNTER_EVENT_SEL 0 8 PERFCOUNTER_CVALUE_SEL 9 11 PERFCOUNTER_INC_MODE 12 14 PERFCOUNTER_HW_CNTL_SEL 15 15 PERFCOUNTER_RUNEN_MODE 16 16 PERFCOUNTER_CNTOFF_START_DIS 22 22 PERFCOUNTER_RESTART_EN 23 23 PERFCOUNTER_INT_EN 24 24 PERFCOUNTER_OFF_MASK 25 25 PERFCOUNTER_ACTIVE 26 26 PERFCOUNTER_CNTL_SEL 29 31 regDC_PERFMON19_PERFCOUNTER_CNTL2 0 0x3051 5 0 2 PERFCOUNTER_COUNTED_VALUE_TYPE 0 1 PERFCOUNTER_HW_STOP1_SEL 2 2 PERFCOUNTER_HW_STOP2_SEL 3 3 PERFCOUNTER_CNTOFF_SEL 8 13 PERFCOUNTER_CNTL2_SEL 29 31 regDC_PERFMON19_PERFCOUNTER_STATE 0 0x3052 16 0 2 PERFCOUNTER_CNT0_STATE 0 1 PERFCOUNTER_STATE_SEL0 2 2 PERFCOUNTER_CNT1_STATE 4 5 PERFCOUNTER_STATE_SEL1 6 6 PERFCOUNTER_CNT2_STATE 8 9 PERFCOUNTER_STATE_SEL2 10 10 PERFCOUNTER_CNT3_STATE 12 13 PERFCOUNTER_STATE_SEL3 14 14 PERFCOUNTER_CNT4_STATE 16 17 PERFCOUNTER_STATE_SEL4 18 18 PERFCOUNTER_CNT5_STATE 20 21 PERFCOUNTER_STATE_SEL5 22 22 PERFCOUNTER_CNT6_STATE 24 25 PERFCOUNTER_STATE_SEL6 26 26 PERFCOUNTER_CNT7_STATE 28 29 PERFCOUNTER_STATE_SEL7 30 30 regDC_PERFMON19_PERFMON_CNTL 0 0x3053 6 0 2 PERFMON_STATE 0 1 PERFMON_RPT_COUNT 8 27 PERFMON_CNTOFF_AND_OR 28 28 PERFMON_CNTOFF_INT_EN 29 29 PERFMON_CNTOFF_INT_STATUS 30 30 PERFMON_CNTOFF_INT_ACK 31 31 regDC_PERFMON19_PERFMON_CNTL2 0 0x3054 4 0 2 PERFMON_CNTOFF_INT_TYPE 0 0 PERFMON_CLK_ENABLE 1 1 PERFMON_RUN_ENABLE_START_SEL 2 9 PERFMON_RUN_ENABLE_STOP_SEL 10 17 regDC_PERFMON19_PERFMON_CVALUE_INT_MISC 0 0x3055 17 0 2 PERFCOUNTER_INT0_STATUS 0 0 PERFCOUNTER_INT1_STATUS 1 1 PERFCOUNTER_INT2_STATUS 2 2 PERFCOUNTER_INT3_STATUS 3 3 PERFCOUNTER_INT4_STATUS 4 4 PERFCOUNTER_INT5_STATUS 5 5 PERFCOUNTER_INT6_STATUS 6 6 PERFCOUNTER_INT7_STATUS 7 7 PERFCOUNTER_INT0_ACK 8 8 PERFCOUNTER_INT1_ACK 9 9 PERFCOUNTER_INT2_ACK 10 10 PERFCOUNTER_INT3_ACK 11 11 PERFCOUNTER_INT4_ACK 12 12 PERFCOUNTER_INT5_ACK 13 13 PERFCOUNTER_INT6_ACK 14 14 PERFCOUNTER_INT7_ACK 15 15 PERFMON_CVALUE_HI 16 31 regDC_PERFMON19_PERFMON_CVALUE_LOW 0 0x3056 1 0 2 PERFMON_CVALUE_LOW 0 31 regDC_PERFMON19_PERFMON_HI 0 0x3057 2 0 2 PERFMON_HI 0 15 PERFMON_READ_SEL 29 31 regDC_PERFMON19_PERFMON_LOW 0 0x3058 1 0 2 PERFMON_LOW 0 31 regDSCC1_DSCC_CONFIG0 0 0x3066 3 0 2 NUMBER_OF_SLICES_PER_LINE 4 5 ALTERNATE_ICH_ENCODING_EN 8 8 NUMBER_OF_SLICES_IN_VERTICAL_DIRECTION 16 31 regDSCC1_DSCC_CONFIG1 0 0x3067 1 0 2 DSCC_RATE_CONTROL_BUFFER_MODEL_SIZE 0 17 regDSCC1_DSCC_STATUS 0 0x3068 1 0 2 DSCC_DOUBLE_BUFFER_REG_UPDATE_PENDING 0 0 regDSCC1_DSCC_INTERRUPT_CONTROL_STATUS 0 0x3069 24 0 2 DSCC_RATE_BUFFER0_OVERFLOW_OCCURRED 0 0 DSCC_RATE_BUFFER1_OVERFLOW_OCCURRED 1 1 DSCC_RATE_BUFFER2_OVERFLOW_OCCURRED 2 2 DSCC_RATE_BUFFER3_OVERFLOW_OCCURRED 3 3 DSCC_RATE_BUFFER0_UNDERFLOW_OCCURRED 4 4 DSCC_RATE_BUFFER1_UNDERFLOW_OCCURRED 5 5 DSCC_RATE_BUFFER2_UNDERFLOW_OCCURRED 6 6 DSCC_RATE_BUFFER3_UNDERFLOW_OCCURRED 7 7 DSCC_RATE_CONTROL_BUFFER_MODEL0_OVERFLOW_OCCURRED 8 8 DSCC_RATE_CONTROL_BUFFER_MODEL1_OVERFLOW_OCCURRED 9 9 DSCC_RATE_CONTROL_BUFFER_MODEL2_OVERFLOW_OCCURRED 10 10 DSCC_RATE_CONTROL_BUFFER_MODEL3_OVERFLOW_OCCURRED 11 11 DSCC_RATE_BUFFER0_OVERFLOW_OCCURRED_INT_EN 16 16 DSCC_RATE_BUFFER1_OVERFLOW_OCCURRED_INT_EN 17 17 DSCC_RATE_BUFFER2_OVERFLOW_OCCURRED_INT_EN 18 18 DSCC_RATE_BUFFER3_OVERFLOW_OCCURRED_INT_EN 19 19 DSCC_RATE_BUFFER0_UNDERFLOW_OCCURRED_INT_EN 20 20 DSCC_RATE_BUFFER1_UNDERFLOW_OCCURRED_INT_EN 21 21 DSCC_RATE_BUFFER2_UNDERFLOW_OCCURRED_INT_EN 22 22 DSCC_RATE_BUFFER3_UNDERFLOW_OCCURRED_INT_EN 23 23 DSCC_RATE_CONTROL_BUFFER_MODEL0_OVERFLOW_OCCURRED_INT_EN 24 24 DSCC_RATE_CONTROL_BUFFER_MODEL1_OVERFLOW_OCCURRED_INT_EN 25 25 DSCC_RATE_CONTROL_BUFFER_MODEL2_OVERFLOW_OCCURRED_INT_EN 26 26 DSCC_RATE_CONTROL_BUFFER_MODEL3_OVERFLOW_OCCURRED_INT_EN 27 27 regDSCC1_DSCC_PPS_CONFIG0 0 0x306a 5 0 2 DSC_VERSION_MINOR 0 3 DSC_VERSION_MAJOR 4 7 PPS_IDENTIFIER 8 15 LINEBUF_DEPTH 24 27 BITS_PER_COMPONENT 28 31 regDSCC1_DSCC_PPS_CONFIG1 0 0x306b 8 0 2 BITS_PER_PIXEL 0 9 VBR_ENABLE 10 10 SIMPLE_422 11 11 CONVERT_RGB 12 12 BLOCK_PRED_ENABLE 13 13 NATIVE_422 14 14 NATIVE_420 15 15 CHUNK_SIZE 16 31 regDSCC1_DSCC_PPS_CONFIG2 0 0x306c 2 0 2 PIC_WIDTH 0 15 PIC_HEIGHT 16 31 regDSCC1_DSCC_PPS_CONFIG3 0 0x306d 2 0 2 SLICE_WIDTH 0 15 SLICE_HEIGHT 16 31 regDSCC1_DSCC_PPS_CONFIG4 0 0x306e 2 0 2 INITIAL_XMIT_DELAY 0 9 INITIAL_DEC_DELAY 16 31 regDSCC1_DSCC_PPS_CONFIG5 0 0x306f 2 0 2 INITIAL_SCALE_VALUE 0 5 SCALE_INCREMENT_INTERVAL 16 31 regDSCC1_DSCC_PPS_CONFIG6 0 0x3070 3 0 2 SCALE_DECREMENT_INTERVAL 0 11 FIRST_LINE_BPG_OFFSET 16 20 SECOND_LINE_BPG_OFFSET 24 28 regDSCC1_DSCC_PPS_CONFIG7 0 0x3071 2 0 2 NFL_BPG_OFFSET 0 15 SLICE_BPG_OFFSET 16 31 regDSCC1_DSCC_PPS_CONFIG8 0 0x3072 2 0 2 NSL_BPG_OFFSET 0 15 SECOND_LINE_OFFSET_ADJ 16 31 regDSCC1_DSCC_PPS_CONFIG9 0 0x3073 2 0 2 INITIAL_OFFSET 0 15 FINAL_OFFSET 16 31 regDSCC1_DSCC_PPS_CONFIG10 0 0x3074 3 0 2 FLATNESS_MIN_QP 0 4 FLATNESS_MAX_QP 8 12 RC_MODEL_SIZE 16 31 regDSCC1_DSCC_PPS_CONFIG11 0 0x3075 5 0 2 RC_EDGE_FACTOR 0 3 RC_QUANT_INCR_LIMIT0 8 12 RC_QUANT_INCR_LIMIT1 16 20 RC_TGT_OFFSET_LO 24 27 RC_TGT_OFFSET_HI 28 31 regDSCC1_DSCC_PPS_CONFIG12 0 0x3076 4 0 2 RC_BUF_THRESH0 0 7 RC_BUF_THRESH1 8 15 RC_BUF_THRESH2 16 23 RC_BUF_THRESH3 24 31 regDSCC1_DSCC_PPS_CONFIG13 0 0x3077 4 0 2 RC_BUF_THRESH4 0 7 RC_BUF_THRESH5 8 15 RC_BUF_THRESH6 16 23 RC_BUF_THRESH7 24 31 regDSCC1_DSCC_PPS_CONFIG14 0 0x3078 4 0 2 RC_BUF_THRESH8 0 7 RC_BUF_THRESH9 8 15 RC_BUF_THRESH10 16 23 RC_BUF_THRESH11 24 31 regDSCC1_DSCC_PPS_CONFIG15 0 0x3079 5 0 2 RC_BUF_THRESH12 0 7 RC_BUF_THRESH13 8 15 RANGE_MIN_QP0 16 20 RANGE_MAX_QP0 21 25 RANGE_BPG_OFFSET0 26 31 regDSCC1_DSCC_PPS_CONFIG16 0 0x307a 6 0 2 RANGE_MIN_QP1 0 4 RANGE_MAX_QP1 5 9 RANGE_BPG_OFFSET1 10 15 RANGE_MIN_QP2 16 20 RANGE_MAX_QP2 21 25 RANGE_BPG_OFFSET2 26 31 regDSCC1_DSCC_PPS_CONFIG17 0 0x307b 6 0 2 RANGE_MIN_QP3 0 4 RANGE_MAX_QP3 5 9 RANGE_BPG_OFFSET3 10 15 RANGE_MIN_QP4 16 20 RANGE_MAX_QP4 21 25 RANGE_BPG_OFFSET4 26 31 regDSCC1_DSCC_PPS_CONFIG18 0 0x307c 6 0 2 RANGE_MIN_QP5 0 4 RANGE_MAX_QP5 5 9 RANGE_BPG_OFFSET5 10 15 RANGE_MIN_QP6 16 20 RANGE_MAX_QP6 21 25 RANGE_BPG_OFFSET6 26 31 regDSCC1_DSCC_PPS_CONFIG19 0 0x307d 6 0 2 RANGE_MIN_QP7 0 4 RANGE_MAX_QP7 5 9 RANGE_BPG_OFFSET7 10 15 RANGE_MIN_QP8 16 20 RANGE_MAX_QP8 21 25 RANGE_BPG_OFFSET8 26 31 regDSCC1_DSCC_PPS_CONFIG20 0 0x307e 6 0 2 RANGE_MIN_QP9 0 4 RANGE_MAX_QP9 5 9 RANGE_BPG_OFFSET9 10 15 RANGE_MIN_QP10 16 20 RANGE_MAX_QP10 21 25 RANGE_BPG_OFFSET10 26 31 regDSCC1_DSCC_PPS_CONFIG21 0 0x307f 6 0 2 RANGE_MIN_QP11 0 4 RANGE_MAX_QP11 5 9 RANGE_BPG_OFFSET11 10 15 RANGE_MIN_QP12 16 20 RANGE_MAX_QP12 21 25 RANGE_BPG_OFFSET12 26 31 regDSCC1_DSCC_PPS_CONFIG22 0 0x3080 6 0 2 RANGE_MIN_QP13 0 4 RANGE_MAX_QP13 5 9 RANGE_BPG_OFFSET13 10 15 RANGE_MIN_QP14 16 20 RANGE_MAX_QP14 21 25 RANGE_BPG_OFFSET14 26 31 regDSCC1_DSCC_MEM_POWER_CONTROL 0 0x3081 7 0 2 DSCC_DEFAULT_MEM_LOW_POWER_STATE 0 1 DSCC_MEM_PWR_FORCE 4 5 DSCC_MEM_PWR_DIS 8 8 DSCC_MEM_PWR_STATE 16 17 DSCC_NATIVE_422_MEM_PWR_FORCE 20 21 DSCC_NATIVE_422_MEM_PWR_DIS 24 24 DSCC_NATIVE_422_MEM_PWR_STATE 28 29 regDSCC1_DSCC_R_Y_SQUARED_ERROR_LOWER 0 0x3082 1 0 2 DSCC_R_Y_SQUARED_ERROR_LOWER 0 31 regDSCC1_DSCC_R_Y_SQUARED_ERROR_UPPER 0 0x3083 1 0 2 DSCC_R_Y_SQUARED_ERROR_UPPER 0 31 regDSCC1_DSCC_G_CB_SQUARED_ERROR_LOWER 0 0x3084 1 0 2 DSCC_G_CB_SQUARED_ERROR_LOWER 0 31 regDSCC1_DSCC_G_CB_SQUARED_ERROR_UPPER 0 0x3085 1 0 2 DSCC_G_CB_SQUARED_ERROR_UPPER 0 31 regDSCC1_DSCC_B_CR_SQUARED_ERROR_LOWER 0 0x3086 1 0 2 DSCC_B_CR_SQUARED_ERROR_LOWER 0 31 regDSCC1_DSCC_B_CR_SQUARED_ERROR_UPPER 0 0x3087 1 0 2 DSCC_B_CR_SQUARED_ERROR_UPPER 0 31 regDSCC1_DSCC_MAX_ABS_ERROR0 0 0x3088 2 0 2 DSCC_R_Y_MAX_ABS_ERROR 0 15 DSCC_G_CB_MAX_ABS_ERROR 16 31 regDSCC1_DSCC_MAX_ABS_ERROR1 0 0x3089 1 0 2 DSCC_B_CR_MAX_ABS_ERROR 0 15 regDSCC1_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL 0 0x308a 1 0 2 DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL 0 17 regDSCC1_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL 0 0x308b 1 0 2 DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL 0 17 regDSCC1_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL 0 0x308c 1 0 2 DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL 0 17 regDSCC1_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL 0 0x308d 1 0 2 DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL 0 17 regDSCC1_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL 0 0x308e 1 0 2 DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL 0 17 regDSCC1_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL 0 0x308f 1 0 2 DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL 0 17 regDSCC1_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL 0 0x3090 1 0 2 DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL 0 17 regDSCC1_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL 0 0x3091 1 0 2 DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL 0 17 regDSCC1_DSCC_TEST_DEBUG_BUS_ROTATE 0 0x3096 4 0 2 DSCC_TEST_DEBUG_BUS0_ROTATE 0 4 DSCC_TEST_DEBUG_BUS1_ROTATE 8 12 DSCC_TEST_DEBUG_BUS2_ROTATE 16 20 DSCC_TEST_DEBUG_BUS3_ROTATE 24 28 regDSCCIF1_DSCCIF_CONFIG0 0 0x3061 6 0 2 INPUT_INTERFACE_UNDERFLOW_RECOVERY_EN 0 0 INPUT_INTERFACE_UNDERFLOW_OCCURRED_INT_EN 4 4 INPUT_INTERFACE_UNDERFLOW_OCCURRED_STATUS 8 8 INPUT_PIXEL_FORMAT 12 14 BITS_PER_COMPONENT 16 19 DOUBLE_BUFFER_REG_UPDATE_PENDING 24 24 regDSCCIF1_DSCCIF_CONFIG1 0 0x3062 2 0 2 PIC_WIDTH 0 15 PIC_HEIGHT 16 31 regDSC_TOP1_DSC_TOP_CONTROL 0 0x305c 3 0 2 DSC_CLOCK_EN 0 0 DSC_DISPCLK_R_GATE_DIS 4 4 DSC_DSCCLK_R_GATE_DIS 8 8 regDSC_TOP1_DSC_DEBUG_CONTROL 0 0x305d 2 0 2 DSC_DBG_EN 0 0 DSC_TEST_CLOCK_MUX_SEL 4 6 regDC_PERFMON20_PERFCOUNTER_CNTL 0 0x30ac 11 0 2 PERFCOUNTER_EVENT_SEL 0 8 PERFCOUNTER_CVALUE_SEL 9 11 PERFCOUNTER_INC_MODE 12 14 PERFCOUNTER_HW_CNTL_SEL 15 15 PERFCOUNTER_RUNEN_MODE 16 16 PERFCOUNTER_CNTOFF_START_DIS 22 22 PERFCOUNTER_RESTART_EN 23 23 PERFCOUNTER_INT_EN 24 24 PERFCOUNTER_OFF_MASK 25 25 PERFCOUNTER_ACTIVE 26 26 PERFCOUNTER_CNTL_SEL 29 31 regDC_PERFMON20_PERFCOUNTER_CNTL2 0 0x30ad 5 0 2 PERFCOUNTER_COUNTED_VALUE_TYPE 0 1 PERFCOUNTER_HW_STOP1_SEL 2 2 PERFCOUNTER_HW_STOP2_SEL 3 3 PERFCOUNTER_CNTOFF_SEL 8 13 PERFCOUNTER_CNTL2_SEL 29 31 regDC_PERFMON20_PERFCOUNTER_STATE 0 0x30ae 16 0 2 PERFCOUNTER_CNT0_STATE 0 1 PERFCOUNTER_STATE_SEL0 2 2 PERFCOUNTER_CNT1_STATE 4 5 PERFCOUNTER_STATE_SEL1 6 6 PERFCOUNTER_CNT2_STATE 8 9 PERFCOUNTER_STATE_SEL2 10 10 PERFCOUNTER_CNT3_STATE 12 13 PERFCOUNTER_STATE_SEL3 14 14 PERFCOUNTER_CNT4_STATE 16 17 PERFCOUNTER_STATE_SEL4 18 18 PERFCOUNTER_CNT5_STATE 20 21 PERFCOUNTER_STATE_SEL5 22 22 PERFCOUNTER_CNT6_STATE 24 25 PERFCOUNTER_STATE_SEL6 26 26 PERFCOUNTER_CNT7_STATE 28 29 PERFCOUNTER_STATE_SEL7 30 30 regDC_PERFMON20_PERFMON_CNTL 0 0x30af 6 0 2 PERFMON_STATE 0 1 PERFMON_RPT_COUNT 8 27 PERFMON_CNTOFF_AND_OR 28 28 PERFMON_CNTOFF_INT_EN 29 29 PERFMON_CNTOFF_INT_STATUS 30 30 PERFMON_CNTOFF_INT_ACK 31 31 regDC_PERFMON20_PERFMON_CNTL2 0 0x30b0 4 0 2 PERFMON_CNTOFF_INT_TYPE 0 0 PERFMON_CLK_ENABLE 1 1 PERFMON_RUN_ENABLE_START_SEL 2 9 PERFMON_RUN_ENABLE_STOP_SEL 10 17 regDC_PERFMON20_PERFMON_CVALUE_INT_MISC 0 0x30b1 17 0 2 PERFCOUNTER_INT0_STATUS 0 0 PERFCOUNTER_INT1_STATUS 1 1 PERFCOUNTER_INT2_STATUS 2 2 PERFCOUNTER_INT3_STATUS 3 3 PERFCOUNTER_INT4_STATUS 4 4 PERFCOUNTER_INT5_STATUS 5 5 PERFCOUNTER_INT6_STATUS 6 6 PERFCOUNTER_INT7_STATUS 7 7 PERFCOUNTER_INT0_ACK 8 8 PERFCOUNTER_INT1_ACK 9 9 PERFCOUNTER_INT2_ACK 10 10 PERFCOUNTER_INT3_ACK 11 11 PERFCOUNTER_INT4_ACK 12 12 PERFCOUNTER_INT5_ACK 13 13 PERFCOUNTER_INT6_ACK 14 14 PERFCOUNTER_INT7_ACK 15 15 PERFMON_CVALUE_HI 16 31 regDC_PERFMON20_PERFMON_CVALUE_LOW 0 0x30b2 1 0 2 PERFMON_CVALUE_LOW 0 31 regDC_PERFMON20_PERFMON_HI 0 0x30b3 2 0 2 PERFMON_HI 0 15 PERFMON_READ_SEL 29 31 regDC_PERFMON20_PERFMON_LOW 0 0x30b4 1 0 2 PERFMON_LOW 0 31 regDSCC2_DSCC_CONFIG0 0 0x30c2 3 0 2 NUMBER_OF_SLICES_PER_LINE 4 5 ALTERNATE_ICH_ENCODING_EN 8 8 NUMBER_OF_SLICES_IN_VERTICAL_DIRECTION 16 31 regDSCC2_DSCC_CONFIG1 0 0x30c3 1 0 2 DSCC_RATE_CONTROL_BUFFER_MODEL_SIZE 0 17 regDSCC2_DSCC_STATUS 0 0x30c4 1 0 2 DSCC_DOUBLE_BUFFER_REG_UPDATE_PENDING 0 0 regDSCC2_DSCC_INTERRUPT_CONTROL_STATUS 0 0x30c5 24 0 2 DSCC_RATE_BUFFER0_OVERFLOW_OCCURRED 0 0 DSCC_RATE_BUFFER1_OVERFLOW_OCCURRED 1 1 DSCC_RATE_BUFFER2_OVERFLOW_OCCURRED 2 2 DSCC_RATE_BUFFER3_OVERFLOW_OCCURRED 3 3 DSCC_RATE_BUFFER0_UNDERFLOW_OCCURRED 4 4 DSCC_RATE_BUFFER1_UNDERFLOW_OCCURRED 5 5 DSCC_RATE_BUFFER2_UNDERFLOW_OCCURRED 6 6 DSCC_RATE_BUFFER3_UNDERFLOW_OCCURRED 7 7 DSCC_RATE_CONTROL_BUFFER_MODEL0_OVERFLOW_OCCURRED 8 8 DSCC_RATE_CONTROL_BUFFER_MODEL1_OVERFLOW_OCCURRED 9 9 DSCC_RATE_CONTROL_BUFFER_MODEL2_OVERFLOW_OCCURRED 10 10 DSCC_RATE_CONTROL_BUFFER_MODEL3_OVERFLOW_OCCURRED 11 11 DSCC_RATE_BUFFER0_OVERFLOW_OCCURRED_INT_EN 16 16 DSCC_RATE_BUFFER1_OVERFLOW_OCCURRED_INT_EN 17 17 DSCC_RATE_BUFFER2_OVERFLOW_OCCURRED_INT_EN 18 18 DSCC_RATE_BUFFER3_OVERFLOW_OCCURRED_INT_EN 19 19 DSCC_RATE_BUFFER0_UNDERFLOW_OCCURRED_INT_EN 20 20 DSCC_RATE_BUFFER1_UNDERFLOW_OCCURRED_INT_EN 21 21 DSCC_RATE_BUFFER2_UNDERFLOW_OCCURRED_INT_EN 22 22 DSCC_RATE_BUFFER3_UNDERFLOW_OCCURRED_INT_EN 23 23 DSCC_RATE_CONTROL_BUFFER_MODEL0_OVERFLOW_OCCURRED_INT_EN 24 24 DSCC_RATE_CONTROL_BUFFER_MODEL1_OVERFLOW_OCCURRED_INT_EN 25 25 DSCC_RATE_CONTROL_BUFFER_MODEL2_OVERFLOW_OCCURRED_INT_EN 26 26 DSCC_RATE_CONTROL_BUFFER_MODEL3_OVERFLOW_OCCURRED_INT_EN 27 27 regDSCC2_DSCC_PPS_CONFIG0 0 0x30c6 5 0 2 DSC_VERSION_MINOR 0 3 DSC_VERSION_MAJOR 4 7 PPS_IDENTIFIER 8 15 LINEBUF_DEPTH 24 27 BITS_PER_COMPONENT 28 31 regDSCC2_DSCC_PPS_CONFIG1 0 0x30c7 8 0 2 BITS_PER_PIXEL 0 9 VBR_ENABLE 10 10 SIMPLE_422 11 11 CONVERT_RGB 12 12 BLOCK_PRED_ENABLE 13 13 NATIVE_422 14 14 NATIVE_420 15 15 CHUNK_SIZE 16 31 regDSCC2_DSCC_PPS_CONFIG2 0 0x30c8 2 0 2 PIC_WIDTH 0 15 PIC_HEIGHT 16 31 regDSCC2_DSCC_PPS_CONFIG3 0 0x30c9 2 0 2 SLICE_WIDTH 0 15 SLICE_HEIGHT 16 31 regDSCC2_DSCC_PPS_CONFIG4 0 0x30ca 2 0 2 INITIAL_XMIT_DELAY 0 9 INITIAL_DEC_DELAY 16 31 regDSCC2_DSCC_PPS_CONFIG5 0 0x30cb 2 0 2 INITIAL_SCALE_VALUE 0 5 SCALE_INCREMENT_INTERVAL 16 31 regDSCC2_DSCC_PPS_CONFIG6 0 0x30cc 3 0 2 SCALE_DECREMENT_INTERVAL 0 11 FIRST_LINE_BPG_OFFSET 16 20 SECOND_LINE_BPG_OFFSET 24 28 regDSCC2_DSCC_PPS_CONFIG7 0 0x30cd 2 0 2 NFL_BPG_OFFSET 0 15 SLICE_BPG_OFFSET 16 31 regDSCC2_DSCC_PPS_CONFIG8 0 0x30ce 2 0 2 NSL_BPG_OFFSET 0 15 SECOND_LINE_OFFSET_ADJ 16 31 regDSCC2_DSCC_PPS_CONFIG9 0 0x30cf 2 0 2 INITIAL_OFFSET 0 15 FINAL_OFFSET 16 31 regDSCC2_DSCC_PPS_CONFIG10 0 0x30d0 3 0 2 FLATNESS_MIN_QP 0 4 FLATNESS_MAX_QP 8 12 RC_MODEL_SIZE 16 31 regDSCC2_DSCC_PPS_CONFIG11 0 0x30d1 5 0 2 RC_EDGE_FACTOR 0 3 RC_QUANT_INCR_LIMIT0 8 12 RC_QUANT_INCR_LIMIT1 16 20 RC_TGT_OFFSET_LO 24 27 RC_TGT_OFFSET_HI 28 31 regDSCC2_DSCC_PPS_CONFIG12 0 0x30d2 4 0 2 RC_BUF_THRESH0 0 7 RC_BUF_THRESH1 8 15 RC_BUF_THRESH2 16 23 RC_BUF_THRESH3 24 31 regDSCC2_DSCC_PPS_CONFIG13 0 0x30d3 4 0 2 RC_BUF_THRESH4 0 7 RC_BUF_THRESH5 8 15 RC_BUF_THRESH6 16 23 RC_BUF_THRESH7 24 31 regDSCC2_DSCC_PPS_CONFIG14 0 0x30d4 4 0 2 RC_BUF_THRESH8 0 7 RC_BUF_THRESH9 8 15 RC_BUF_THRESH10 16 23 RC_BUF_THRESH11 24 31 regDSCC2_DSCC_PPS_CONFIG15 0 0x30d5 5 0 2 RC_BUF_THRESH12 0 7 RC_BUF_THRESH13 8 15 RANGE_MIN_QP0 16 20 RANGE_MAX_QP0 21 25 RANGE_BPG_OFFSET0 26 31 regDSCC2_DSCC_PPS_CONFIG16 0 0x30d6 6 0 2 RANGE_MIN_QP1 0 4 RANGE_MAX_QP1 5 9 RANGE_BPG_OFFSET1 10 15 RANGE_MIN_QP2 16 20 RANGE_MAX_QP2 21 25 RANGE_BPG_OFFSET2 26 31 regDSCC2_DSCC_PPS_CONFIG17 0 0x30d7 6 0 2 RANGE_MIN_QP3 0 4 RANGE_MAX_QP3 5 9 RANGE_BPG_OFFSET3 10 15 RANGE_MIN_QP4 16 20 RANGE_MAX_QP4 21 25 RANGE_BPG_OFFSET4 26 31 regDSCC2_DSCC_PPS_CONFIG18 0 0x30d8 6 0 2 RANGE_MIN_QP5 0 4 RANGE_MAX_QP5 5 9 RANGE_BPG_OFFSET5 10 15 RANGE_MIN_QP6 16 20 RANGE_MAX_QP6 21 25 RANGE_BPG_OFFSET6 26 31 regDSCC2_DSCC_PPS_CONFIG19 0 0x30d9 6 0 2 RANGE_MIN_QP7 0 4 RANGE_MAX_QP7 5 9 RANGE_BPG_OFFSET7 10 15 RANGE_MIN_QP8 16 20 RANGE_MAX_QP8 21 25 RANGE_BPG_OFFSET8 26 31 regDSCC2_DSCC_PPS_CONFIG20 0 0x30da 6 0 2 RANGE_MIN_QP9 0 4 RANGE_MAX_QP9 5 9 RANGE_BPG_OFFSET9 10 15 RANGE_MIN_QP10 16 20 RANGE_MAX_QP10 21 25 RANGE_BPG_OFFSET10 26 31 regDSCC2_DSCC_PPS_CONFIG21 0 0x30db 6 0 2 RANGE_MIN_QP11 0 4 RANGE_MAX_QP11 5 9 RANGE_BPG_OFFSET11 10 15 RANGE_MIN_QP12 16 20 RANGE_MAX_QP12 21 25 RANGE_BPG_OFFSET12 26 31 regDSCC2_DSCC_PPS_CONFIG22 0 0x30dc 6 0 2 RANGE_MIN_QP13 0 4 RANGE_MAX_QP13 5 9 RANGE_BPG_OFFSET13 10 15 RANGE_MIN_QP14 16 20 RANGE_MAX_QP14 21 25 RANGE_BPG_OFFSET14 26 31 regDSCC2_DSCC_MEM_POWER_CONTROL 0 0x30dd 7 0 2 DSCC_DEFAULT_MEM_LOW_POWER_STATE 0 1 DSCC_MEM_PWR_FORCE 4 5 DSCC_MEM_PWR_DIS 8 8 DSCC_MEM_PWR_STATE 16 17 DSCC_NATIVE_422_MEM_PWR_FORCE 20 21 DSCC_NATIVE_422_MEM_PWR_DIS 24 24 DSCC_NATIVE_422_MEM_PWR_STATE 28 29 regDSCC2_DSCC_R_Y_SQUARED_ERROR_LOWER 0 0x30de 1 0 2 DSCC_R_Y_SQUARED_ERROR_LOWER 0 31 regDSCC2_DSCC_R_Y_SQUARED_ERROR_UPPER 0 0x30df 1 0 2 DSCC_R_Y_SQUARED_ERROR_UPPER 0 31 regDSCC2_DSCC_G_CB_SQUARED_ERROR_LOWER 0 0x30e0 1 0 2 DSCC_G_CB_SQUARED_ERROR_LOWER 0 31 regDSCC2_DSCC_G_CB_SQUARED_ERROR_UPPER 0 0x30e1 1 0 2 DSCC_G_CB_SQUARED_ERROR_UPPER 0 31 regDSCC2_DSCC_B_CR_SQUARED_ERROR_LOWER 0 0x30e2 1 0 2 DSCC_B_CR_SQUARED_ERROR_LOWER 0 31 regDSCC2_DSCC_B_CR_SQUARED_ERROR_UPPER 0 0x30e3 1 0 2 DSCC_B_CR_SQUARED_ERROR_UPPER 0 31 regDSCC2_DSCC_MAX_ABS_ERROR0 0 0x30e4 2 0 2 DSCC_R_Y_MAX_ABS_ERROR 0 15 DSCC_G_CB_MAX_ABS_ERROR 16 31 regDSCC2_DSCC_MAX_ABS_ERROR1 0 0x30e5 1 0 2 DSCC_B_CR_MAX_ABS_ERROR 0 15 regDSCC2_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL 0 0x30e6 1 0 2 DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL 0 17 regDSCC2_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL 0 0x30e7 1 0 2 DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL 0 17 regDSCC2_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL 0 0x30e8 1 0 2 DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL 0 17 regDSCC2_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL 0 0x30e9 1 0 2 DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL 0 17 regDSCC2_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL 0 0x30ea 1 0 2 DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL 0 17 regDSCC2_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL 0 0x30eb 1 0 2 DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL 0 17 regDSCC2_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL 0 0x30ec 1 0 2 DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL 0 17 regDSCC2_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL 0 0x30ed 1 0 2 DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL 0 17 regDSCC2_DSCC_TEST_DEBUG_BUS_ROTATE 0 0x30f2 4 0 2 DSCC_TEST_DEBUG_BUS0_ROTATE 0 4 DSCC_TEST_DEBUG_BUS1_ROTATE 8 12 DSCC_TEST_DEBUG_BUS2_ROTATE 16 20 DSCC_TEST_DEBUG_BUS3_ROTATE 24 28 regDSCCIF2_DSCCIF_CONFIG0 0 0x30bd 6 0 2 INPUT_INTERFACE_UNDERFLOW_RECOVERY_EN 0 0 INPUT_INTERFACE_UNDERFLOW_OCCURRED_INT_EN 4 4 INPUT_INTERFACE_UNDERFLOW_OCCURRED_STATUS 8 8 INPUT_PIXEL_FORMAT 12 14 BITS_PER_COMPONENT 16 19 DOUBLE_BUFFER_REG_UPDATE_PENDING 24 24 regDSCCIF2_DSCCIF_CONFIG1 0 0x30be 2 0 2 PIC_WIDTH 0 15 PIC_HEIGHT 16 31 regDSC_TOP2_DSC_TOP_CONTROL 0 0x30b8 3 0 2 DSC_CLOCK_EN 0 0 DSC_DISPCLK_R_GATE_DIS 4 4 DSC_DSCCLK_R_GATE_DIS 8 8 regDSC_TOP2_DSC_DEBUG_CONTROL 0 0x30b9 2 0 2 DSC_DBG_EN 0 0 DSC_TEST_CLOCK_MUX_SEL 4 6 regDC_PERFMON21_PERFCOUNTER_CNTL 0 0x3108 11 0 2 PERFCOUNTER_EVENT_SEL 0 8 PERFCOUNTER_CVALUE_SEL 9 11 PERFCOUNTER_INC_MODE 12 14 PERFCOUNTER_HW_CNTL_SEL 15 15 PERFCOUNTER_RUNEN_MODE 16 16 PERFCOUNTER_CNTOFF_START_DIS 22 22 PERFCOUNTER_RESTART_EN 23 23 PERFCOUNTER_INT_EN 24 24 PERFCOUNTER_OFF_MASK 25 25 PERFCOUNTER_ACTIVE 26 26 PERFCOUNTER_CNTL_SEL 29 31 regDC_PERFMON21_PERFCOUNTER_CNTL2 0 0x3109 5 0 2 PERFCOUNTER_COUNTED_VALUE_TYPE 0 1 PERFCOUNTER_HW_STOP1_SEL 2 2 PERFCOUNTER_HW_STOP2_SEL 3 3 PERFCOUNTER_CNTOFF_SEL 8 13 PERFCOUNTER_CNTL2_SEL 29 31 regDC_PERFMON21_PERFCOUNTER_STATE 0 0x310a 16 0 2 PERFCOUNTER_CNT0_STATE 0 1 PERFCOUNTER_STATE_SEL0 2 2 PERFCOUNTER_CNT1_STATE 4 5 PERFCOUNTER_STATE_SEL1 6 6 PERFCOUNTER_CNT2_STATE 8 9 PERFCOUNTER_STATE_SEL2 10 10 PERFCOUNTER_CNT3_STATE 12 13 PERFCOUNTER_STATE_SEL3 14 14 PERFCOUNTER_CNT4_STATE 16 17 PERFCOUNTER_STATE_SEL4 18 18 PERFCOUNTER_CNT5_STATE 20 21 PERFCOUNTER_STATE_SEL5 22 22 PERFCOUNTER_CNT6_STATE 24 25 PERFCOUNTER_STATE_SEL6 26 26 PERFCOUNTER_CNT7_STATE 28 29 PERFCOUNTER_STATE_SEL7 30 30 regDC_PERFMON21_PERFMON_CNTL 0 0x310b 6 0 2 PERFMON_STATE 0 1 PERFMON_RPT_COUNT 8 27 PERFMON_CNTOFF_AND_OR 28 28 PERFMON_CNTOFF_INT_EN 29 29 PERFMON_CNTOFF_INT_STATUS 30 30 PERFMON_CNTOFF_INT_ACK 31 31 regDC_PERFMON21_PERFMON_CNTL2 0 0x310c 4 0 2 PERFMON_CNTOFF_INT_TYPE 0 0 PERFMON_CLK_ENABLE 1 1 PERFMON_RUN_ENABLE_START_SEL 2 9 PERFMON_RUN_ENABLE_STOP_SEL 10 17 regDC_PERFMON21_PERFMON_CVALUE_INT_MISC 0 0x310d 17 0 2 PERFCOUNTER_INT0_STATUS 0 0 PERFCOUNTER_INT1_STATUS 1 1 PERFCOUNTER_INT2_STATUS 2 2 PERFCOUNTER_INT3_STATUS 3 3 PERFCOUNTER_INT4_STATUS 4 4 PERFCOUNTER_INT5_STATUS 5 5 PERFCOUNTER_INT6_STATUS 6 6 PERFCOUNTER_INT7_STATUS 7 7 PERFCOUNTER_INT0_ACK 8 8 PERFCOUNTER_INT1_ACK 9 9 PERFCOUNTER_INT2_ACK 10 10 PERFCOUNTER_INT3_ACK 11 11 PERFCOUNTER_INT4_ACK 12 12 PERFCOUNTER_INT5_ACK 13 13 PERFCOUNTER_INT6_ACK 14 14 PERFCOUNTER_INT7_ACK 15 15 PERFMON_CVALUE_HI 16 31 regDC_PERFMON21_PERFMON_CVALUE_LOW 0 0x310e 1 0 2 PERFMON_CVALUE_LOW 0 31 regDC_PERFMON21_PERFMON_HI 0 0x310f 2 0 2 PERFMON_HI 0 15 PERFMON_READ_SEL 29 31 regDC_PERFMON21_PERFMON_LOW 0 0x3110 1 0 2 PERFMON_LOW 0 31 regHPO_TOP_CLOCK_CONTROL 0 0xe43 15 0 3 HPO_DISPCLK_R_GATE_DIS 0 0 HPO_DISPCLK_GATE_DIS 1 1 HPO_SOCCLK_R_GATE_DIS 4 4 HPO_SOCCLK_GATE_DIS 5 5 HPO_HDMISTREAMCLK_R_GATE_DIS 8 8 HPO_HDMISTREAMCLK_G_GATE_DIS 9 9 HPO_HDMICHARCLK_R_GATE_DIS 12 12 HPO_HDMICHARCLK_G_GATE_DIS 13 13 HPO_DPSTREAMCLK_R_GATE_DIS 16 16 HPO_DPSTREAMCLK_G_GATE_DIS 17 17 HPO_SYMCLK32_SE_R_GATE_DIS 18 18 HPO_SYMCLK32_SE_G_GATE_DIS 19 19 HPO_SYMCLK32_LE_R_GATE_DIS 20 20 HPO_SYMCLK32_LE_G_GATE_DIS 21 21 HPO_TEST_CLK_SEL 24 30 regHPO_TOP_HW_CONTROL 0 0xe4a 1 0 3 HPO_IO_EN 0 0 regDP_STREAM_MAPPER_CONTROL0 0 0xe56 1 0 3 DP_STREAM_LINK_TARGET 0 2 regDP_STREAM_MAPPER_CONTROL1 0 0xe57 1 0 3 DP_STREAM_LINK_TARGET 0 2 regDP_STREAM_MAPPER_CONTROL2 0 0xe58 1 0 3 DP_STREAM_LINK_TARGET 0 2 regDP_STREAM_MAPPER_CONTROL3 0 0xe59 1 0 3 DP_STREAM_LINK_TARGET 0 2 regDC_PERFMON22_PERFCOUNTER_CNTL 0 0xe66 11 0 3 PERFCOUNTER_EVENT_SEL 0 8 PERFCOUNTER_CVALUE_SEL 9 11 PERFCOUNTER_INC_MODE 12 14 PERFCOUNTER_HW_CNTL_SEL 15 15 PERFCOUNTER_RUNEN_MODE 16 16 PERFCOUNTER_CNTOFF_START_DIS 22 22 PERFCOUNTER_RESTART_EN 23 23 PERFCOUNTER_INT_EN 24 24 PERFCOUNTER_OFF_MASK 25 25 PERFCOUNTER_ACTIVE 26 26 PERFCOUNTER_CNTL_SEL 29 31 regDC_PERFMON22_PERFCOUNTER_CNTL2 0 0xe67 5 0 3 PERFCOUNTER_COUNTED_VALUE_TYPE 0 1 PERFCOUNTER_HW_STOP1_SEL 2 2 PERFCOUNTER_HW_STOP2_SEL 3 3 PERFCOUNTER_CNTOFF_SEL 8 13 PERFCOUNTER_CNTL2_SEL 29 31 regDC_PERFMON22_PERFCOUNTER_STATE 0 0xe68 16 0 3 PERFCOUNTER_CNT0_STATE 0 1 PERFCOUNTER_STATE_SEL0 2 2 PERFCOUNTER_CNT1_STATE 4 5 PERFCOUNTER_STATE_SEL1 6 6 PERFCOUNTER_CNT2_STATE 8 9 PERFCOUNTER_STATE_SEL2 10 10 PERFCOUNTER_CNT3_STATE 12 13 PERFCOUNTER_STATE_SEL3 14 14 PERFCOUNTER_CNT4_STATE 16 17 PERFCOUNTER_STATE_SEL4 18 18 PERFCOUNTER_CNT5_STATE 20 21 PERFCOUNTER_STATE_SEL5 22 22 PERFCOUNTER_CNT6_STATE 24 25 PERFCOUNTER_STATE_SEL6 26 26 PERFCOUNTER_CNT7_STATE 28 29 PERFCOUNTER_STATE_SEL7 30 30 regDC_PERFMON22_PERFMON_CNTL 0 0xe69 6 0 3 PERFMON_STATE 0 1 PERFMON_RPT_COUNT 8 27 PERFMON_CNTOFF_AND_OR 28 28 PERFMON_CNTOFF_INT_EN 29 29 PERFMON_CNTOFF_INT_STATUS 30 30 PERFMON_CNTOFF_INT_ACK 31 31 regDC_PERFMON22_PERFMON_CNTL2 0 0xe6a 4 0 3 PERFMON_CNTOFF_INT_TYPE 0 0 PERFMON_CLK_ENABLE 1 1 PERFMON_RUN_ENABLE_START_SEL 2 9 PERFMON_RUN_ENABLE_STOP_SEL 10 17 regDC_PERFMON22_PERFMON_CVALUE_INT_MISC 0 0xe6b 17 0 3 PERFCOUNTER_INT0_STATUS 0 0 PERFCOUNTER_INT1_STATUS 1 1 PERFCOUNTER_INT2_STATUS 2 2 PERFCOUNTER_INT3_STATUS 3 3 PERFCOUNTER_INT4_STATUS 4 4 PERFCOUNTER_INT5_STATUS 5 5 PERFCOUNTER_INT6_STATUS 6 6 PERFCOUNTER_INT7_STATUS 7 7 PERFCOUNTER_INT0_ACK 8 8 PERFCOUNTER_INT1_ACK 9 9 PERFCOUNTER_INT2_ACK 10 10 PERFCOUNTER_INT3_ACK 11 11 PERFCOUNTER_INT4_ACK 12 12 PERFCOUNTER_INT5_ACK 13 13 PERFCOUNTER_INT6_ACK 14 14 PERFCOUNTER_INT7_ACK 15 15 PERFMON_CVALUE_HI 16 31 regDC_PERFMON22_PERFMON_CVALUE_LOW 0 0xe6c 1 0 3 PERFMON_CVALUE_LOW 0 31 regDC_PERFMON22_PERFMON_HI 0 0xe6d 2 0 3 PERFMON_HI 0 15 PERFMON_READ_SEL 29 31 regDC_PERFMON22_PERFMON_LOW 0 0xe6e 1 0 3 PERFMON_LOW 0 31 regAFMT5_AFMT_VBI_PACKET_CONTROL 0 0x91c 3 0 3 AFMT_ACP_SOURCE 13 13 AFMT_HDMI_AUDIO_PACKETS_PER_LINE 16 20 AFMT_HDMI_AUDIO_SEND_MAX_PACKETS 24 24 regAFMT5_AFMT_AUDIO_PACKET_CONTROL2 0 0x91d 6 0 3 AFMT_AUDIO_LAYOUT_OVRD 0 0 AFMT_AUDIO_LAYOUT_SELECT 1 1 AFMT_AUDIO_CHANNEL_ENABLE 8 15 AFMT_DP_AUDIO_STREAM_ID 16 23 AFMT_HBR_ENABLE_OVRD 24 24 AFMT_60958_OSF_OVRD 28 28 regAFMT5_AFMT_AUDIO_INFO0 0 0x91e 5 0 3 AFMT_AUDIO_INFO_CHECKSUM 0 7 AFMT_AUDIO_INFO_CC 8 10 AFMT_AUDIO_INFO_CT 11 14 AFMT_AUDIO_INFO_CHECKSUM_OFFSET 16 23 AFMT_AUDIO_INFO_CXT 24 28 regAFMT5_AFMT_AUDIO_INFO1 0 0x91f 4 0 3 AFMT_AUDIO_INFO_CA 0 7 AFMT_AUDIO_INFO_LSV 11 14 AFMT_AUDIO_INFO_DM_INH 15 15 AFMT_AUDIO_INFO_LFEPBL 16 17 regAFMT5_AFMT_60958_0 0 0x920 10 0 3 AFMT_60958_CS_A 0 0 AFMT_60958_CS_B 1 1 AFMT_60958_CS_C 2 2 AFMT_60958_CS_D 3 5 AFMT_60958_CS_MODE 6 7 AFMT_60958_CS_CATEGORY_CODE 8 15 AFMT_60958_CS_SOURCE_NUMBER 16 19 AFMT_60958_CS_CHANNEL_NUMBER_L 20 23 AFMT_60958_CS_SAMPLING_FREQUENCY 24 27 AFMT_60958_CS_CLOCK_ACCURACY 28 29 regAFMT5_AFMT_60958_1 0 0x921 5 0 3 AFMT_60958_CS_WORD_LENGTH 0 3 AFMT_60958_CS_ORIGINAL_SAMPLING_FREQUENCY 4 7 AFMT_60958_VALID_L 16 16 AFMT_60958_VALID_R 18 18 AFMT_60958_CS_CHANNEL_NUMBER_R 20 23 regAFMT5_AFMT_AUDIO_CRC_CONTROL 0 0x922 5 0 3 AFMT_AUDIO_CRC_EN 0 0 AFMT_AUDIO_CRC_CONT 4 4 AFMT_AUDIO_CRC_SOURCE 8 8 AFMT_AUDIO_CRC_CH_SEL 12 15 AFMT_AUDIO_CRC_COUNT 16 31 regAFMT5_AFMT_RAMP_CONTROL0 0 0x923 2 0 3 AFMT_RAMP_MAX_COUNT 0 23 AFMT_RAMP_DATA_SIGN 31 31 regAFMT5_AFMT_RAMP_CONTROL1 0 0x924 2 0 3 AFMT_RAMP_MIN_COUNT 0 23 AFMT_AUDIO_TEST_CH_DISABLE 24 31 regAFMT5_AFMT_RAMP_CONTROL2 0 0x925 1 0 3 AFMT_RAMP_INC_COUNT 0 23 regAFMT5_AFMT_RAMP_CONTROL3 0 0x926 1 0 3 AFMT_RAMP_DEC_COUNT 0 23 regAFMT5_AFMT_60958_2 0 0x927 6 0 3 AFMT_60958_CS_CHANNEL_NUMBER_2 0 3 AFMT_60958_CS_CHANNEL_NUMBER_3 4 7 AFMT_60958_CS_CHANNEL_NUMBER_4 8 11 AFMT_60958_CS_CHANNEL_NUMBER_5 12 15 AFMT_60958_CS_CHANNEL_NUMBER_6 16 19 AFMT_60958_CS_CHANNEL_NUMBER_7 20 23 regAFMT5_AFMT_AUDIO_CRC_RESULT 0 0x928 2 0 3 AFMT_AUDIO_CRC_DONE 0 0 AFMT_AUDIO_CRC 8 31 regAFMT5_AFMT_STATUS 0 0x929 4 0 3 AFMT_AUDIO_ENABLE 4 4 AFMT_AZ_HBR_ENABLE 8 8 AFMT_AUDIO_FIFO_OVERFLOW 24 24 AFMT_AZ_AUDIO_ENABLE_CHG 30 30 regAFMT5_AFMT_AUDIO_PACKET_CONTROL 0 0x92a 10 0 3 AFMT_AUDIO_SAMPLE_SEND 0 0 AFMT_AUDIO_SAMPLE_SEND_DOUBLE_BUFFER_ENABLE 4 4 AFMT_RESET_FIFO_WHEN_AUDIO_DIS 11 11 AFMT_AUDIO_TEST_EN 12 12 AFMT_AUDIO_TEST_MODE 14 14 AFMT_AUDIO_FIFO_OVERFLOW_ACK 23 23 AFMT_AUDIO_CHANNEL_SWAP 24 24 AFMT_60958_CS_UPDATE 26 26 AFMT_AZ_AUDIO_ENABLE_CHG_ACK 30 30 AFMT_BLANK_TEST_DATA_ON_ENC_ENB 31 31 regAFMT5_AFMT_INFOFRAME_CONTROL0 0 0x92b 2 0 3 AFMT_AUDIO_INFO_SOURCE 6 6 AFMT_AUDIO_INFO_UPDATE 7 7 regAFMT5_AFMT_AUDIO_SRC_CONTROL 0 0x92d 1 0 3 AFMT_AUDIO_SRC_SELECT 0 2 regAFMT5_AFMT_MEM_PWR 0 0x92f 3 0 3 AFMT_MEM_PWR_DIS 0 0 AFMT_MEM_PWR_FORCE 4 5 AFMT_MEM_PWR_STATE 8 9 regDME5_DME_CONTROL 0 0x93c 9 0 3 METADATA_HUBP_REQUESTOR_ID 0 2 METADATA_ENGINE_EN 4 4 METADATA_STREAM_TYPE 8 8 METADATA_DB_PENDING 12 12 METADATA_DB_TAKEN 13 13 METADATA_DB_TAKEN_CLR 16 16 METADATA_DB_DISABLE 20 20 METADATA_TRANSMISSION_MISSED 24 24 METADATA_TRANSMISSION_MISSED_CLR 25 25 regDME5_DME_MEMORY_CONTROL 0 0x93d 4 0 3 DME_MEM_PWR_FORCE 0 1 DME_MEM_PWR_DIS 4 4 DME_MEM_PWR_STATE 8 9 DME_MEM_DEFAULT_MEM_LOW_POWER_STATE 12 13 regVPG5_VPG_GENERIC_PACKET_ACCESS_CTRL 0 0x931 1 0 3 VPG_GENERIC_DATA_INDEX 0 7 regVPG5_VPG_GENERIC_PACKET_DATA 0 0x932 4 0 3 VPG_GENERIC_DATA_BYTE0 0 7 VPG_GENERIC_DATA_BYTE1 8 15 VPG_GENERIC_DATA_BYTE2 16 23 VPG_GENERIC_DATA_BYTE3 24 31 regVPG5_VPG_GSP_FRAME_UPDATE_CTRL 0 0x933 30 0 3 VPG_GENERIC0_FRAME_UPDATE 0 0 VPG_GENERIC1_FRAME_UPDATE 1 1 VPG_GENERIC2_FRAME_UPDATE 2 2 VPG_GENERIC3_FRAME_UPDATE 3 3 VPG_GENERIC4_FRAME_UPDATE 4 4 VPG_GENERIC5_FRAME_UPDATE 5 5 VPG_GENERIC6_FRAME_UPDATE 6 6 VPG_GENERIC7_FRAME_UPDATE 7 7 VPG_GENERIC8_FRAME_UPDATE 8 8 VPG_GENERIC9_FRAME_UPDATE 9 9 VPG_GENERIC10_FRAME_UPDATE 10 10 VPG_GENERIC11_FRAME_UPDATE 11 11 VPG_GENERIC12_FRAME_UPDATE 12 12 VPG_GENERIC13_FRAME_UPDATE 13 13 VPG_GENERIC14_FRAME_UPDATE 14 14 VPG_GENERIC0_FRAME_UPDATE_PENDING 16 16 VPG_GENERIC1_FRAME_UPDATE_PENDING 17 17 VPG_GENERIC2_FRAME_UPDATE_PENDING 18 18 VPG_GENERIC3_FRAME_UPDATE_PENDING 19 19 VPG_GENERIC4_FRAME_UPDATE_PENDING 20 20 VPG_GENERIC5_FRAME_UPDATE_PENDING 21 21 VPG_GENERIC6_FRAME_UPDATE_PENDING 22 22 VPG_GENERIC7_FRAME_UPDATE_PENDING 23 23 VPG_GENERIC8_FRAME_UPDATE_PENDING 24 24 VPG_GENERIC9_FRAME_UPDATE_PENDING 25 25 VPG_GENERIC10_FRAME_UPDATE_PENDING 26 26 VPG_GENERIC11_FRAME_UPDATE_PENDING 27 27 VPG_GENERIC12_FRAME_UPDATE_PENDING 28 28 VPG_GENERIC13_FRAME_UPDATE_PENDING 29 29 VPG_GENERIC14_FRAME_UPDATE_PENDING 30 30 regVPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL 0 0x934 30 0 3 VPG_GENERIC0_IMMEDIATE_UPDATE 0 0 VPG_GENERIC1_IMMEDIATE_UPDATE 1 1 VPG_GENERIC2_IMMEDIATE_UPDATE 2 2 VPG_GENERIC3_IMMEDIATE_UPDATE 3 3 VPG_GENERIC4_IMMEDIATE_UPDATE 4 4 VPG_GENERIC5_IMMEDIATE_UPDATE 5 5 VPG_GENERIC6_IMMEDIATE_UPDATE 6 6 VPG_GENERIC7_IMMEDIATE_UPDATE 7 7 VPG_GENERIC8_IMMEDIATE_UPDATE 8 8 VPG_GENERIC9_IMMEDIATE_UPDATE 9 9 VPG_GENERIC10_IMMEDIATE_UPDATE 10 10 VPG_GENERIC11_IMMEDIATE_UPDATE 11 11 VPG_GENERIC12_IMMEDIATE_UPDATE 12 12 VPG_GENERIC13_IMMEDIATE_UPDATE 13 13 VPG_GENERIC14_IMMEDIATE_UPDATE 14 14 VPG_GENERIC0_IMMEDIATE_UPDATE_PENDING 16 16 VPG_GENERIC1_IMMEDIATE_UPDATE_PENDING 17 17 VPG_GENERIC2_IMMEDIATE_UPDATE_PENDING 18 18 VPG_GENERIC3_IMMEDIATE_UPDATE_PENDING 19 19 VPG_GENERIC4_IMMEDIATE_UPDATE_PENDING 20 20 VPG_GENERIC5_IMMEDIATE_UPDATE_PENDING 21 21 VPG_GENERIC6_IMMEDIATE_UPDATE_PENDING 22 22 VPG_GENERIC7_IMMEDIATE_UPDATE_PENDING 23 23 VPG_GENERIC8_IMMEDIATE_UPDATE_PENDING 24 24 VPG_GENERIC9_IMMEDIATE_UPDATE_PENDING 25 25 VPG_GENERIC10_IMMEDIATE_UPDATE_PENDING 26 26 VPG_GENERIC11_IMMEDIATE_UPDATE_PENDING 27 27 VPG_GENERIC12_IMMEDIATE_UPDATE_PENDING 28 28 VPG_GENERIC13_IMMEDIATE_UPDATE_PENDING 29 29 VPG_GENERIC14_IMMEDIATE_UPDATE_PENDING 30 30 regVPG5_VPG_GENERIC_STATUS 0 0x935 3 0 3 VPG_GENERIC_LOCK_STATUS 0 0 VPG_GENERIC_CONFLICT_OCCURED 1 1 VPG_GENERIC_CONFLICT_CLR 4 4 regVPG5_VPG_MEM_PWR 0 0x936 3 0 3 VPG_GSP_MEM_LIGHT_SLEEP_DIS 0 0 VPG_GSP_LIGHT_SLEEP_FORCE 4 4 VPG_GSP_MEM_PWR_STATE 8 8 regVPG5_VPG_ISRC1_2_ACCESS_CTRL 0 0x937 1 0 3 VPG_ISRC1_2_DATA_INDEX 0 3 regVPG5_VPG_ISRC1_2_DATA 0 0x938 4 0 3 VPG_ISRC_DATA_BYTE0 0 7 VPG_ISRC_DATA_BYTE1 8 15 VPG_ISRC_DATA_BYTE2 16 23 VPG_ISRC_DATA_BYTE3 24 31 regVPG5_VPG_MPEG_INFO0 0 0x939 4 0 3 VPG_MPEG_INFO_CHECKSUM 0 7 VPG_MPEG_INFO_MB0 8 15 VPG_MPEG_INFO_MB1 16 23 VPG_MPEG_INFO_MB2 24 31 regVPG5_VPG_MPEG_INFO1 0 0x93a 4 0 3 VPG_MPEG_INFO_MB3 0 7 VPG_MPEG_INFO_MF 8 9 VPG_MPEG_INFO_FR 12 12 VPG_MPEG_INFO_UPDATE 16 16 regDP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_CONTROL 0 0x3623 5 0 2 DP_STREAM_ENC_CLOCK_EN 0 0 DP_STREAM_ENC_CLOCK_ON_DISPCLK 4 4 DP_STREAM_ENC_CLOCK_ON_SOCCLK 8 8 DP_STREAM_ENC_CLOCK_ON_DPSTREAMCLK 12 12 DP_STREAM_ENC_CLOCK_ON_SYMCLK32 16 16 regDP_STREAM_ENC0_DP_STREAM_ENC_INPUT_MUX_CONTROL 0 0x3624 1 0 2 DP_STREAM_ENC_INPUT_MUX_PIXEL_STREAM_SOURCE_SEL 0 2 regDP_STREAM_ENC0_DP_STREAM_ENC_AUDIO_CONTROL 0 0x3625 1 0 2 DP_STREAM_ENC_INPUT_MUX_AUDIO_STREAM_SOURCE_SEL 0 2 regDP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0 0 0x3626 7 0 2 FIFO_ENABLE 0 0 FIFO_RESET 4 4 FIFO_READ_START_LEVEL 8 12 FIFO_READ_CLOCK_SRC 16 16 FIFO_RESET_DONE 20 20 FIFO_VIDEO_STREAM_ACTIVE 24 24 FIFO_ERROR 28 29 regDP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1 0 0x3627 8 0 2 FIFO_USE_OVERWRITE_LEVEL 0 0 FIFO_FORCE_RECAL_AVERAGE 1 1 FIFO_FORCE_RECOMP_MINMAX 2 2 FIFO_OVERWRITE_LEVEL 4 9 FIFO_MINIMUM_LEVEL 12 15 FIFO_MAXIMUM_LEVEL 16 20 FIFO_CAL_AVERAGE_LEVEL 24 29 FIFO_CALIBRATED 31 31 regDP_STREAM_ENC0_DP_STREAM_ENC_SPARE 0 0x3628 1 0 2 DP_STREAM_ENC_SPARE 0 31 regAPG0_APG_CONTROL 0 0x3630 2 0 2 APG_RESET 1 1 APG_RESET_DONE 2 2 regAPG0_APG_CONTROL2 0 0x3631 3 0 2 APG_ENABLE 0 0 APG_DP_AUDIO_STREAM_ID 8 15 APG_DP_ASP_CHANNEL_COUNT_OVERRIDE 24 24 regAPG0_APG_DBG_GEN_CONTROL 0 0x3632 4 0 2 APG_DBG_GEN_ENABLE 0 0 APG_DBG_GEN_RESET 1 1 APG_DBG_AUDIO_CHANNEL_ENABLE 8 15 APG_DBG_AUDIO_TEST_CH_DISABLE 24 31 regAPG0_APG_PACKET_CONTROL 0 0x3633 3 0 2 APG_DBG_MUX_SEL 0 0 APG_ACP_SOURCE 1 1 APG_AUDIO_INFO_SOURCE 2 2 regAPG0_APG_AUDIO_CRC_CONTROL 0 0x363a 4 0 2 APG_AUDIO_CRC_EN 0 0 APG_AUDIO_CRC_CONT 4 4 APG_AUDIO_CRC_CH_SEL 13 15 APG_AUDIO_CRC_COUNT 16 31 regAPG0_APG_AUDIO_CRC_CONTROL2 0 0x363b 1 0 2 APG_AUDIO_CRC_COUNT_FORCE_DEFAULT 0 15 regAPG0_APG_AUDIO_CRC_RESULT 0 0x363c 3 0 2 APG_AUDIO_CRC_DONE 0 0 APG_AUDIO_CRC_DONE_CLEAR 8 8 APG_AUDIO_CRC 16 31 regAPG0_APG_STATUS 0 0x3641 4 0 2 APG_AUDIO_ENABLE 4 4 APG_HBR_ENABLE 8 8 APG_AUDIO_FIFO_OVERFLOW_STATUS 24 24 APG_AUDIO_FIFO_OVERFLOW_STATUS_CLEAR 25 25 regAPG0_APG_STATUS2 0 0x3642 1 0 2 APG_OUTPUT_ACTIVE 0 0 regAPG0_APG_MEM_PWR 0 0x3644 4 0 2 APG_MEM_PWR_DIS 0 0 APG_MEM_PWR_FORCE 4 5 APG_MEM_PWR_STATE 8 9 APG_MEM_DEFAULT_LOW_POWER_STATE 12 13 regAPG0_APG_SPARE 0 0x3646 1 0 2 APG_SPARE 0 31 regDME6_DME_CONTROL 0 0x364e 9 0 2 METADATA_HUBP_REQUESTOR_ID 0 2 METADATA_ENGINE_EN 4 4 METADATA_STREAM_TYPE 8 8 METADATA_DB_PENDING 12 12 METADATA_DB_TAKEN 13 13 METADATA_DB_TAKEN_CLR 16 16 METADATA_DB_DISABLE 20 20 METADATA_TRANSMISSION_MISSED 24 24 METADATA_TRANSMISSION_MISSED_CLR 25 25 regDME6_DME_MEMORY_CONTROL 0 0x364f 4 0 2 DME_MEM_PWR_FORCE 0 1 DME_MEM_PWR_DIS 4 4 DME_MEM_PWR_STATE 8 9 DME_MEM_DEFAULT_MEM_LOW_POWER_STATE 12 13 regVPG6_VPG_GENERIC_PACKET_ACCESS_CTRL 0 0x3651 1 0 2 VPG_GENERIC_DATA_INDEX 0 7 regVPG6_VPG_GENERIC_PACKET_DATA 0 0x3652 4 0 2 VPG_GENERIC_DATA_BYTE0 0 7 VPG_GENERIC_DATA_BYTE1 8 15 VPG_GENERIC_DATA_BYTE2 16 23 VPG_GENERIC_DATA_BYTE3 24 31 regVPG6_VPG_GSP_FRAME_UPDATE_CTRL 0 0x3653 30 0 2 VPG_GENERIC0_FRAME_UPDATE 0 0 VPG_GENERIC1_FRAME_UPDATE 1 1 VPG_GENERIC2_FRAME_UPDATE 2 2 VPG_GENERIC3_FRAME_UPDATE 3 3 VPG_GENERIC4_FRAME_UPDATE 4 4 VPG_GENERIC5_FRAME_UPDATE 5 5 VPG_GENERIC6_FRAME_UPDATE 6 6 VPG_GENERIC7_FRAME_UPDATE 7 7 VPG_GENERIC8_FRAME_UPDATE 8 8 VPG_GENERIC9_FRAME_UPDATE 9 9 VPG_GENERIC10_FRAME_UPDATE 10 10 VPG_GENERIC11_FRAME_UPDATE 11 11 VPG_GENERIC12_FRAME_UPDATE 12 12 VPG_GENERIC13_FRAME_UPDATE 13 13 VPG_GENERIC14_FRAME_UPDATE 14 14 VPG_GENERIC0_FRAME_UPDATE_PENDING 16 16 VPG_GENERIC1_FRAME_UPDATE_PENDING 17 17 VPG_GENERIC2_FRAME_UPDATE_PENDING 18 18 VPG_GENERIC3_FRAME_UPDATE_PENDING 19 19 VPG_GENERIC4_FRAME_UPDATE_PENDING 20 20 VPG_GENERIC5_FRAME_UPDATE_PENDING 21 21 VPG_GENERIC6_FRAME_UPDATE_PENDING 22 22 VPG_GENERIC7_FRAME_UPDATE_PENDING 23 23 VPG_GENERIC8_FRAME_UPDATE_PENDING 24 24 VPG_GENERIC9_FRAME_UPDATE_PENDING 25 25 VPG_GENERIC10_FRAME_UPDATE_PENDING 26 26 VPG_GENERIC11_FRAME_UPDATE_PENDING 27 27 VPG_GENERIC12_FRAME_UPDATE_PENDING 28 28 VPG_GENERIC13_FRAME_UPDATE_PENDING 29 29 VPG_GENERIC14_FRAME_UPDATE_PENDING 30 30 regVPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL 0 0x3654 30 0 2 VPG_GENERIC0_IMMEDIATE_UPDATE 0 0 VPG_GENERIC1_IMMEDIATE_UPDATE 1 1 VPG_GENERIC2_IMMEDIATE_UPDATE 2 2 VPG_GENERIC3_IMMEDIATE_UPDATE 3 3 VPG_GENERIC4_IMMEDIATE_UPDATE 4 4 VPG_GENERIC5_IMMEDIATE_UPDATE 5 5 VPG_GENERIC6_IMMEDIATE_UPDATE 6 6 VPG_GENERIC7_IMMEDIATE_UPDATE 7 7 VPG_GENERIC8_IMMEDIATE_UPDATE 8 8 VPG_GENERIC9_IMMEDIATE_UPDATE 9 9 VPG_GENERIC10_IMMEDIATE_UPDATE 10 10 VPG_GENERIC11_IMMEDIATE_UPDATE 11 11 VPG_GENERIC12_IMMEDIATE_UPDATE 12 12 VPG_GENERIC13_IMMEDIATE_UPDATE 13 13 VPG_GENERIC14_IMMEDIATE_UPDATE 14 14 VPG_GENERIC0_IMMEDIATE_UPDATE_PENDING 16 16 VPG_GENERIC1_IMMEDIATE_UPDATE_PENDING 17 17 VPG_GENERIC2_IMMEDIATE_UPDATE_PENDING 18 18 VPG_GENERIC3_IMMEDIATE_UPDATE_PENDING 19 19 VPG_GENERIC4_IMMEDIATE_UPDATE_PENDING 20 20 VPG_GENERIC5_IMMEDIATE_UPDATE_PENDING 21 21 VPG_GENERIC6_IMMEDIATE_UPDATE_PENDING 22 22 VPG_GENERIC7_IMMEDIATE_UPDATE_PENDING 23 23 VPG_GENERIC8_IMMEDIATE_UPDATE_PENDING 24 24 VPG_GENERIC9_IMMEDIATE_UPDATE_PENDING 25 25 VPG_GENERIC10_IMMEDIATE_UPDATE_PENDING 26 26 VPG_GENERIC11_IMMEDIATE_UPDATE_PENDING 27 27 VPG_GENERIC12_IMMEDIATE_UPDATE_PENDING 28 28 VPG_GENERIC13_IMMEDIATE_UPDATE_PENDING 29 29 VPG_GENERIC14_IMMEDIATE_UPDATE_PENDING 30 30 regVPG6_VPG_GENERIC_STATUS 0 0x3655 3 0 2 VPG_GENERIC_LOCK_STATUS 0 0 VPG_GENERIC_CONFLICT_OCCURED 1 1 VPG_GENERIC_CONFLICT_CLR 4 4 regVPG6_VPG_MEM_PWR 0 0x3656 3 0 2 VPG_GSP_MEM_LIGHT_SLEEP_DIS 0 0 VPG_GSP_LIGHT_SLEEP_FORCE 4 4 VPG_GSP_MEM_PWR_STATE 8 8 regVPG6_VPG_ISRC1_2_ACCESS_CTRL 0 0x3657 1 0 2 VPG_ISRC1_2_DATA_INDEX 0 3 regVPG6_VPG_ISRC1_2_DATA 0 0x3658 4 0 2 VPG_ISRC_DATA_BYTE0 0 7 VPG_ISRC_DATA_BYTE1 8 15 VPG_ISRC_DATA_BYTE2 16 23 VPG_ISRC_DATA_BYTE3 24 31 regVPG6_VPG_MPEG_INFO0 0 0x3659 4 0 2 VPG_MPEG_INFO_CHECKSUM 0 7 VPG_MPEG_INFO_MB0 8 15 VPG_MPEG_INFO_MB1 16 23 VPG_MPEG_INFO_MB2 24 31 regVPG6_VPG_MPEG_INFO1 0 0x365a 4 0 2 VPG_MPEG_INFO_MB3 0 7 VPG_MPEG_INFO_MF 8 9 VPG_MPEG_INFO_FR 12 12 VPG_MPEG_INFO_UPDATE 16 16 regDP_SYM32_ENC0_DP_SYM32_ENC_CONTROL 0 0x365d 3 0 2 DP_SYM32_ENC_ENABLE 0 0 DP_SYM32_ENC_RESET 4 4 DP_SYM32_ENC_RESET_DONE 8 8 regDP_SYM32_ENC0_DP_SYM32_ENC_VID_FIFO_CONTROL 0 0x365e 4 0 2 PIXEL_TO_SYMBOL_FIFO_ENABLE 0 0 PIXEL_TO_SYMBOL_FIFO_RESET 4 4 PIXEL_TO_SYMBOL_FIFO_RESET_DONE 8 8 PIXEL_TO_SYMBOL_FIFO_OVERFLOW_STATUS 12 12 regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL 0 0x365f 2 0 2 MSA_DOUBLE_BUFFER_ENABLE 0 0 MSA_DOUBLE_BUFFER_PENDING 4 4 regDP_SYM32_ENC0_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL 0 0x3660 2 0 2 PIXEL_FORMAT_DOUBLE_BUFFER_ENABLE 0 0 PIXEL_FORMAT_DOUBLE_BUFFER_PENDING 4 4 regDP_SYM32_ENC0_DP_SYM32_ENC_VID_PIXEL_FORMAT 0 0x3661 3 0 2 PIXEL_ENCODING_TYPE 0 0 UNCOMPRESSED_PIXEL_ENCODING 4 5 UNCOMPRESSED_COMPONENT_DEPTH 8 9 regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA0 0 0x3662 1 0 2 MSA_DATA 0 31 regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA1 0 0x3663 1 0 2 MSA_DATA 0 31 regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA2 0 0x3664 1 0 2 MSA_DATA 0 31 regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA3 0 0x3665 1 0 2 MSA_DATA 0 31 regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA4 0 0x3666 1 0 2 MSA_DATA 0 31 regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA5 0 0x3667 1 0 2 MSA_DATA 0 31 regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA6 0 0x3668 1 0 2 MSA_DATA 0 31 regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA7 0 0x3669 1 0 2 MSA_DATA 0 31 regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA8 0 0x366a 1 0 2 MSA_DATA 0 31 regDP_SYM32_ENC0_DP_SYM32_ENC_HBLANK_CONTROL 0 0x366b 1 0 2 HBLANK_MINIMUM_SYMBOL_WIDTH 0 15 regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL0 0 0x366c 11 0 2 GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE 0 0 GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE 1 1 GSP_TRIGGER_ONE_SHOT_SEND 2 2 GSP_TRIGGER_ONE_SHOT_POSITION 3 3 GSP_DOUBLE_BUFFER_ENABLE 4 4 GSP_PAYLOAD_SIZE 5 6 GSP_SOF_REFERENCE 7 7 GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED 8 8 GSP_TRIGGER_TRANSMISSION_PENDING 9 9 GSP_DOUBLE_BUFFER_PENDING 10 10 GSP_TRANSMISSION_LINE_NUMBER 16 31 regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL1 0 0x366d 11 0 2 GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE 0 0 GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE 1 1 GSP_TRIGGER_ONE_SHOT_SEND 2 2 GSP_TRIGGER_ONE_SHOT_POSITION 3 3 GSP_DOUBLE_BUFFER_ENABLE 4 4 GSP_PAYLOAD_SIZE 5 6 GSP_SOF_REFERENCE 7 7 GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED 8 8 GSP_TRIGGER_TRANSMISSION_PENDING 9 9 GSP_DOUBLE_BUFFER_PENDING 10 10 GSP_TRANSMISSION_LINE_NUMBER 16 31 regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL2 0 0x366e 11 0 2 GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE 0 0 GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE 1 1 GSP_TRIGGER_ONE_SHOT_SEND 2 2 GSP_TRIGGER_ONE_SHOT_POSITION 3 3 GSP_DOUBLE_BUFFER_ENABLE 4 4 GSP_PAYLOAD_SIZE 5 6 GSP_SOF_REFERENCE 7 7 GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED 8 8 GSP_TRIGGER_TRANSMISSION_PENDING 9 9 GSP_DOUBLE_BUFFER_PENDING 10 10 GSP_TRANSMISSION_LINE_NUMBER 16 31 regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL3 0 0x366f 11 0 2 GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE 0 0 GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE 1 1 GSP_TRIGGER_ONE_SHOT_SEND 2 2 GSP_TRIGGER_ONE_SHOT_POSITION 3 3 GSP_DOUBLE_BUFFER_ENABLE 4 4 GSP_PAYLOAD_SIZE 5 6 GSP_SOF_REFERENCE 7 7 GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED 8 8 GSP_TRIGGER_TRANSMISSION_PENDING 9 9 GSP_DOUBLE_BUFFER_PENDING 10 10 GSP_TRANSMISSION_LINE_NUMBER 16 31 regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL4 0 0x3670 11 0 2 GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE 0 0 GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE 1 1 GSP_TRIGGER_ONE_SHOT_SEND 2 2 GSP_TRIGGER_ONE_SHOT_POSITION 3 3 GSP_DOUBLE_BUFFER_ENABLE 4 4 GSP_PAYLOAD_SIZE 5 6 GSP_SOF_REFERENCE 7 7 GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED 8 8 GSP_TRIGGER_TRANSMISSION_PENDING 9 9 GSP_DOUBLE_BUFFER_PENDING 10 10 GSP_TRANSMISSION_LINE_NUMBER 16 31 regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL5 0 0x3671 11 0 2 GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE 0 0 GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE 1 1 GSP_TRIGGER_ONE_SHOT_SEND 2 2 GSP_TRIGGER_ONE_SHOT_POSITION 3 3 GSP_DOUBLE_BUFFER_ENABLE 4 4 GSP_PAYLOAD_SIZE 5 6 GSP_SOF_REFERENCE 7 7 GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED 8 8 GSP_TRIGGER_TRANSMISSION_PENDING 9 9 GSP_DOUBLE_BUFFER_PENDING 10 10 GSP_TRANSMISSION_LINE_NUMBER 16 31 regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL6 0 0x3672 11 0 2 GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE 0 0 GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE 1 1 GSP_TRIGGER_ONE_SHOT_SEND 2 2 GSP_TRIGGER_ONE_SHOT_POSITION 3 3 GSP_DOUBLE_BUFFER_ENABLE 4 4 GSP_PAYLOAD_SIZE 5 6 GSP_SOF_REFERENCE 7 7 GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED 8 8 GSP_TRIGGER_TRANSMISSION_PENDING 9 9 GSP_DOUBLE_BUFFER_PENDING 10 10 GSP_TRANSMISSION_LINE_NUMBER 16 31 regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL7 0 0x3673 11 0 2 GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE 0 0 GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE 1 1 GSP_TRIGGER_ONE_SHOT_SEND 2 2 GSP_TRIGGER_ONE_SHOT_POSITION 3 3 GSP_DOUBLE_BUFFER_ENABLE 4 4 GSP_PAYLOAD_SIZE 5 6 GSP_SOF_REFERENCE 7 7 GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED 8 8 GSP_TRIGGER_TRANSMISSION_PENDING 9 9 GSP_DOUBLE_BUFFER_PENDING 10 10 GSP_TRANSMISSION_LINE_NUMBER 16 31 regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL8 0 0x3674 11 0 2 GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE 0 0 GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE 1 1 GSP_TRIGGER_ONE_SHOT_SEND 2 2 GSP_TRIGGER_ONE_SHOT_POSITION 3 3 GSP_DOUBLE_BUFFER_ENABLE 4 4 GSP_PAYLOAD_SIZE 5 6 GSP_SOF_REFERENCE 7 7 GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED 8 8 GSP_TRIGGER_TRANSMISSION_PENDING 9 9 GSP_DOUBLE_BUFFER_PENDING 10 10 GSP_TRANSMISSION_LINE_NUMBER 16 31 regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL9 0 0x3675 11 0 2 GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE 0 0 GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE 1 1 GSP_TRIGGER_ONE_SHOT_SEND 2 2 GSP_TRIGGER_ONE_SHOT_POSITION 3 3 GSP_DOUBLE_BUFFER_ENABLE 4 4 GSP_PAYLOAD_SIZE 5 6 GSP_SOF_REFERENCE 7 7 GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED 8 8 GSP_TRIGGER_TRANSMISSION_PENDING 9 9 GSP_DOUBLE_BUFFER_PENDING 10 10 GSP_TRANSMISSION_LINE_NUMBER 16 31 regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL10 0 0x3676 11 0 2 GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE 0 0 GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE 1 1 GSP_TRIGGER_ONE_SHOT_SEND 2 2 GSP_TRIGGER_ONE_SHOT_POSITION 3 3 GSP_DOUBLE_BUFFER_ENABLE 4 4 GSP_PAYLOAD_SIZE 5 6 GSP_SOF_REFERENCE 7 7 GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED 8 8 GSP_TRIGGER_TRANSMISSION_PENDING 9 9 GSP_DOUBLE_BUFFER_PENDING 10 10 GSP_TRANSMISSION_LINE_NUMBER 16 31 regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL11 0 0x3677 11 0 2 GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE 0 0 GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE 1 1 GSP_TRIGGER_ONE_SHOT_SEND 2 2 GSP_TRIGGER_ONE_SHOT_POSITION 3 3 GSP_DOUBLE_BUFFER_ENABLE 4 4 GSP_PAYLOAD_SIZE 5 6 GSP_SOF_REFERENCE 7 7 GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED 8 8 GSP_TRIGGER_TRANSMISSION_PENDING 9 9 GSP_DOUBLE_BUFFER_PENDING 10 10 GSP_TRANSMISSION_LINE_NUMBER 16 31 regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL12 0 0x3678 11 0 2 GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE 0 0 GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE 1 1 GSP_TRIGGER_ONE_SHOT_SEND 2 2 GSP_TRIGGER_ONE_SHOT_POSITION 3 3 GSP_DOUBLE_BUFFER_ENABLE 4 4 GSP_PAYLOAD_SIZE 5 6 GSP_SOF_REFERENCE 7 7 GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED 8 8 GSP_TRIGGER_TRANSMISSION_PENDING 9 9 GSP_DOUBLE_BUFFER_PENDING 10 10 GSP_TRANSMISSION_LINE_NUMBER 16 31 regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL13 0 0x3679 11 0 2 GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE 0 0 GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE 1 1 GSP_TRIGGER_ONE_SHOT_SEND 2 2 GSP_TRIGGER_ONE_SHOT_POSITION 3 3 GSP_DOUBLE_BUFFER_ENABLE 4 4 GSP_PAYLOAD_SIZE 5 6 GSP_SOF_REFERENCE 7 7 GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED 8 8 GSP_TRIGGER_TRANSMISSION_PENDING 9 9 GSP_DOUBLE_BUFFER_PENDING 10 10 GSP_TRANSMISSION_LINE_NUMBER 16 31 regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL14 0 0x367a 11 0 2 GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE 0 0 GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE 1 1 GSP_TRIGGER_ONE_SHOT_SEND 2 2 GSP_TRIGGER_ONE_SHOT_POSITION 3 3 GSP_DOUBLE_BUFFER_ENABLE 4 4 GSP_PAYLOAD_SIZE 5 6 GSP_SOF_REFERENCE 7 7 GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED 8 8 GSP_TRIGGER_TRANSMISSION_PENDING 9 9 GSP_DOUBLE_BUFFER_PENDING 10 10 GSP_TRANSMISSION_LINE_NUMBER 16 31 regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_CONTROL 0 0x367b 3 0 2 SDP_STREAM_ENABLE 0 0 GSP0_PRIORITY 4 4 SDP_CRC16_ENABLE 8 8 regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL0 0 0x367c 9 0 2 ASP_ENABLE 0 0 ATP_ENABLE 1 1 AIP_ENABLE 2 2 ACM_ENABLE 3 3 ISRC_ENABLE 4 4 ASP_PRIORITY 5 5 ATP_VERSION_NUMBER 8 13 AUDIO_MUTE 28 28 AUDIO_MUTE_STATUS 29 29 regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL1 0 0x367d 4 0 2 ASP_CONCATENATION_ENABLE 0 0 ASP_CONCATENATION_2_CHANNEL_LAYOUT_MAX_SAMPLE_COUNT 4 9 ASP_CONCATENATION_8_CHANNEL_LAYOUT_MAX_SAMPLE_COUNT 12 17 ASP_CONCATENATION_HBR_LAYOUT_MAX_SAMPLE_COUNT 20 25 regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL 0 0x367e 5 0 2 METADATA_PACKET_ENABLE 0 0 METADATA_DOUBLE_BUFFER_ENABLE 4 4 METADATA_PACKET_SOF_REFERENCE 8 8 METADATA_PACKET_DOUBLE_BUFFER_PENDING 12 12 METADATA_PACKET_TRANSMISSION_LINE_NUMBER 16 31 regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA_CONTROL 0 0x3683 2 0 2 MSA_MISC1_STEREOSYNC_OVERRIDE_EN 0 0 MSA_TRANSMISSION_LINE_NUMBER 16 31 regDP_SYM32_ENC0_DP_SYM32_ENC_VID_VBID_CONTROL 0 0x3684 2 0 2 VBID_6_COMPRESSEDSTREAM_FLAG_SOF_REFERENCE 0 0 VBID_6_COMPRESSEDSTREAM_FLAG_LINE_NUMBER 16 31 regDP_SYM32_ENC0_DP_SYM32_ENC_VID_STREAM_CONTROL 0 0x3685 3 0 2 VID_STREAM_ENABLE 0 0 VID_STREAM_DISABLE_DEFER 4 5 VID_STREAM_STATUS 8 8 regDP_SYM32_ENC0_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL 0 0x3686 2 0 2 PANEL_REPLAY_TUNNELING_OPTIMIZATION_ENABLE 0 0 PANEL_REPLAY_TUNNELING_OPTIMIZATION_DOUBLE_BUFFER_ENABLE 4 4 regDP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_CONTROL 0 0x3687 2 0 2 CRC_ENABLE 0 0 CRC_CONT_MODE_ENABLE 4 4 regDP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_RESULT0 0 0x3688 2 0 2 CRC_RESULT0 0 15 CRC_RESULT1 16 31 regDP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_RESULT1 0 0x3689 2 0 2 CRC_RESULT2 0 15 CRC_RESULT3 16 31 regDP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_STATUS 0 0x368a 1 0 2 CRC_VALID 0 0 regDP_SYM32_ENC0_DP_SYM32_ENC_MEM_POWER_CONTROL 0 0x368b 4 0 2 MEM_DEFAULT_LOW_POWER_STATE 0 1 MEM_PWR_FORCE 4 5 MEM_PWR_DIS 8 8 MEM_PWR_STATE 12 13 regDP_SYM32_ENC0_DP_SYM32_ENC_SPARE 0 0x368c 1 0 2 DP_SYM32_ENC_SPARE 0 31 regDP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_CONTROL 0 0x36f7 5 0 2 DP_STREAM_ENC_CLOCK_EN 0 0 DP_STREAM_ENC_CLOCK_ON_DISPCLK 4 4 DP_STREAM_ENC_CLOCK_ON_SOCCLK 8 8 DP_STREAM_ENC_CLOCK_ON_DPSTREAMCLK 12 12 DP_STREAM_ENC_CLOCK_ON_SYMCLK32 16 16 regDP_STREAM_ENC1_DP_STREAM_ENC_INPUT_MUX_CONTROL 0 0x36f8 1 0 2 DP_STREAM_ENC_INPUT_MUX_PIXEL_STREAM_SOURCE_SEL 0 2 regDP_STREAM_ENC1_DP_STREAM_ENC_AUDIO_CONTROL 0 0x36f9 1 0 2 DP_STREAM_ENC_INPUT_MUX_AUDIO_STREAM_SOURCE_SEL 0 2 regDP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0 0 0x36fa 7 0 2 FIFO_ENABLE 0 0 FIFO_RESET 4 4 FIFO_READ_START_LEVEL 8 12 FIFO_READ_CLOCK_SRC 16 16 FIFO_RESET_DONE 20 20 FIFO_VIDEO_STREAM_ACTIVE 24 24 FIFO_ERROR 28 29 regDP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1 0 0x36fb 8 0 2 FIFO_USE_OVERWRITE_LEVEL 0 0 FIFO_FORCE_RECAL_AVERAGE 1 1 FIFO_FORCE_RECOMP_MINMAX 2 2 FIFO_OVERWRITE_LEVEL 4 9 FIFO_MINIMUM_LEVEL 12 15 FIFO_MAXIMUM_LEVEL 16 20 FIFO_CAL_AVERAGE_LEVEL 24 29 FIFO_CALIBRATED 31 31 regDP_STREAM_ENC1_DP_STREAM_ENC_SPARE 0 0x36fc 1 0 2 DP_STREAM_ENC_SPARE 0 31 regAPG1_APG_CONTROL 0 0x3704 2 0 2 APG_RESET 1 1 APG_RESET_DONE 2 2 regAPG1_APG_CONTROL2 0 0x3705 3 0 2 APG_ENABLE 0 0 APG_DP_AUDIO_STREAM_ID 8 15 APG_DP_ASP_CHANNEL_COUNT_OVERRIDE 24 24 regAPG1_APG_DBG_GEN_CONTROL 0 0x3706 4 0 2 APG_DBG_GEN_ENABLE 0 0 APG_DBG_GEN_RESET 1 1 APG_DBG_AUDIO_CHANNEL_ENABLE 8 15 APG_DBG_AUDIO_TEST_CH_DISABLE 24 31 regAPG1_APG_PACKET_CONTROL 0 0x3707 3 0 2 APG_DBG_MUX_SEL 0 0 APG_ACP_SOURCE 1 1 APG_AUDIO_INFO_SOURCE 2 2 regAPG1_APG_AUDIO_CRC_CONTROL 0 0x370e 4 0 2 APG_AUDIO_CRC_EN 0 0 APG_AUDIO_CRC_CONT 4 4 APG_AUDIO_CRC_CH_SEL 13 15 APG_AUDIO_CRC_COUNT 16 31 regAPG1_APG_AUDIO_CRC_CONTROL2 0 0x370f 1 0 2 APG_AUDIO_CRC_COUNT_FORCE_DEFAULT 0 15 regAPG1_APG_AUDIO_CRC_RESULT 0 0x3710 3 0 2 APG_AUDIO_CRC_DONE 0 0 APG_AUDIO_CRC_DONE_CLEAR 8 8 APG_AUDIO_CRC 16 31 regAPG1_APG_STATUS 0 0x3715 4 0 2 APG_AUDIO_ENABLE 4 4 APG_HBR_ENABLE 8 8 APG_AUDIO_FIFO_OVERFLOW_STATUS 24 24 APG_AUDIO_FIFO_OVERFLOW_STATUS_CLEAR 25 25 regAPG1_APG_STATUS2 0 0x3716 1 0 2 APG_OUTPUT_ACTIVE 0 0 regAPG1_APG_MEM_PWR 0 0x3718 4 0 2 APG_MEM_PWR_DIS 0 0 APG_MEM_PWR_FORCE 4 5 APG_MEM_PWR_STATE 8 9 APG_MEM_DEFAULT_LOW_POWER_STATE 12 13 regAPG1_APG_SPARE 0 0x371a 1 0 2 APG_SPARE 0 31 regDME7_DME_CONTROL 0 0x3722 9 0 2 METADATA_HUBP_REQUESTOR_ID 0 2 METADATA_ENGINE_EN 4 4 METADATA_STREAM_TYPE 8 8 METADATA_DB_PENDING 12 12 METADATA_DB_TAKEN 13 13 METADATA_DB_TAKEN_CLR 16 16 METADATA_DB_DISABLE 20 20 METADATA_TRANSMISSION_MISSED 24 24 METADATA_TRANSMISSION_MISSED_CLR 25 25 regDME7_DME_MEMORY_CONTROL 0 0x3723 4 0 2 DME_MEM_PWR_FORCE 0 1 DME_MEM_PWR_DIS 4 4 DME_MEM_PWR_STATE 8 9 DME_MEM_DEFAULT_MEM_LOW_POWER_STATE 12 13 regVPG7_VPG_GENERIC_PACKET_ACCESS_CTRL 0 0x3725 1 0 2 VPG_GENERIC_DATA_INDEX 0 7 regVPG7_VPG_GENERIC_PACKET_DATA 0 0x3726 4 0 2 VPG_GENERIC_DATA_BYTE0 0 7 VPG_GENERIC_DATA_BYTE1 8 15 VPG_GENERIC_DATA_BYTE2 16 23 VPG_GENERIC_DATA_BYTE3 24 31 regVPG7_VPG_GSP_FRAME_UPDATE_CTRL 0 0x3727 30 0 2 VPG_GENERIC0_FRAME_UPDATE 0 0 VPG_GENERIC1_FRAME_UPDATE 1 1 VPG_GENERIC2_FRAME_UPDATE 2 2 VPG_GENERIC3_FRAME_UPDATE 3 3 VPG_GENERIC4_FRAME_UPDATE 4 4 VPG_GENERIC5_FRAME_UPDATE 5 5 VPG_GENERIC6_FRAME_UPDATE 6 6 VPG_GENERIC7_FRAME_UPDATE 7 7 VPG_GENERIC8_FRAME_UPDATE 8 8 VPG_GENERIC9_FRAME_UPDATE 9 9 VPG_GENERIC10_FRAME_UPDATE 10 10 VPG_GENERIC11_FRAME_UPDATE 11 11 VPG_GENERIC12_FRAME_UPDATE 12 12 VPG_GENERIC13_FRAME_UPDATE 13 13 VPG_GENERIC14_FRAME_UPDATE 14 14 VPG_GENERIC0_FRAME_UPDATE_PENDING 16 16 VPG_GENERIC1_FRAME_UPDATE_PENDING 17 17 VPG_GENERIC2_FRAME_UPDATE_PENDING 18 18 VPG_GENERIC3_FRAME_UPDATE_PENDING 19 19 VPG_GENERIC4_FRAME_UPDATE_PENDING 20 20 VPG_GENERIC5_FRAME_UPDATE_PENDING 21 21 VPG_GENERIC6_FRAME_UPDATE_PENDING 22 22 VPG_GENERIC7_FRAME_UPDATE_PENDING 23 23 VPG_GENERIC8_FRAME_UPDATE_PENDING 24 24 VPG_GENERIC9_FRAME_UPDATE_PENDING 25 25 VPG_GENERIC10_FRAME_UPDATE_PENDING 26 26 VPG_GENERIC11_FRAME_UPDATE_PENDING 27 27 VPG_GENERIC12_FRAME_UPDATE_PENDING 28 28 VPG_GENERIC13_FRAME_UPDATE_PENDING 29 29 VPG_GENERIC14_FRAME_UPDATE_PENDING 30 30 regVPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL 0 0x3728 30 0 2 VPG_GENERIC0_IMMEDIATE_UPDATE 0 0 VPG_GENERIC1_IMMEDIATE_UPDATE 1 1 VPG_GENERIC2_IMMEDIATE_UPDATE 2 2 VPG_GENERIC3_IMMEDIATE_UPDATE 3 3 VPG_GENERIC4_IMMEDIATE_UPDATE 4 4 VPG_GENERIC5_IMMEDIATE_UPDATE 5 5 VPG_GENERIC6_IMMEDIATE_UPDATE 6 6 VPG_GENERIC7_IMMEDIATE_UPDATE 7 7 VPG_GENERIC8_IMMEDIATE_UPDATE 8 8 VPG_GENERIC9_IMMEDIATE_UPDATE 9 9 VPG_GENERIC10_IMMEDIATE_UPDATE 10 10 VPG_GENERIC11_IMMEDIATE_UPDATE 11 11 VPG_GENERIC12_IMMEDIATE_UPDATE 12 12 VPG_GENERIC13_IMMEDIATE_UPDATE 13 13 VPG_GENERIC14_IMMEDIATE_UPDATE 14 14 VPG_GENERIC0_IMMEDIATE_UPDATE_PENDING 16 16 VPG_GENERIC1_IMMEDIATE_UPDATE_PENDING 17 17 VPG_GENERIC2_IMMEDIATE_UPDATE_PENDING 18 18 VPG_GENERIC3_IMMEDIATE_UPDATE_PENDING 19 19 VPG_GENERIC4_IMMEDIATE_UPDATE_PENDING 20 20 VPG_GENERIC5_IMMEDIATE_UPDATE_PENDING 21 21 VPG_GENERIC6_IMMEDIATE_UPDATE_PENDING 22 22 VPG_GENERIC7_IMMEDIATE_UPDATE_PENDING 23 23 VPG_GENERIC8_IMMEDIATE_UPDATE_PENDING 24 24 VPG_GENERIC9_IMMEDIATE_UPDATE_PENDING 25 25 VPG_GENERIC10_IMMEDIATE_UPDATE_PENDING 26 26 VPG_GENERIC11_IMMEDIATE_UPDATE_PENDING 27 27 VPG_GENERIC12_IMMEDIATE_UPDATE_PENDING 28 28 VPG_GENERIC13_IMMEDIATE_UPDATE_PENDING 29 29 VPG_GENERIC14_IMMEDIATE_UPDATE_PENDING 30 30 regVPG7_VPG_GENERIC_STATUS 0 0x3729 3 0 2 VPG_GENERIC_LOCK_STATUS 0 0 VPG_GENERIC_CONFLICT_OCCURED 1 1 VPG_GENERIC_CONFLICT_CLR 4 4 regVPG7_VPG_MEM_PWR 0 0x372a 3 0 2 VPG_GSP_MEM_LIGHT_SLEEP_DIS 0 0 VPG_GSP_LIGHT_SLEEP_FORCE 4 4 VPG_GSP_MEM_PWR_STATE 8 8 regVPG7_VPG_ISRC1_2_ACCESS_CTRL 0 0x372b 1 0 2 VPG_ISRC1_2_DATA_INDEX 0 3 regVPG7_VPG_ISRC1_2_DATA 0 0x372c 4 0 2 VPG_ISRC_DATA_BYTE0 0 7 VPG_ISRC_DATA_BYTE1 8 15 VPG_ISRC_DATA_BYTE2 16 23 VPG_ISRC_DATA_BYTE3 24 31 regVPG7_VPG_MPEG_INFO0 0 0x372d 4 0 2 VPG_MPEG_INFO_CHECKSUM 0 7 VPG_MPEG_INFO_MB0 8 15 VPG_MPEG_INFO_MB1 16 23 VPG_MPEG_INFO_MB2 24 31 regVPG7_VPG_MPEG_INFO1 0 0x372e 4 0 2 VPG_MPEG_INFO_MB3 0 7 VPG_MPEG_INFO_MF 8 9 VPG_MPEG_INFO_FR 12 12 VPG_MPEG_INFO_UPDATE 16 16 regDP_SYM32_ENC1_DP_SYM32_ENC_CONTROL 0 0x3731 3 0 2 DP_SYM32_ENC_ENABLE 0 0 DP_SYM32_ENC_RESET 4 4 DP_SYM32_ENC_RESET_DONE 8 8 regDP_SYM32_ENC1_DP_SYM32_ENC_VID_FIFO_CONTROL 0 0x3732 4 0 2 PIXEL_TO_SYMBOL_FIFO_ENABLE 0 0 PIXEL_TO_SYMBOL_FIFO_RESET 4 4 PIXEL_TO_SYMBOL_FIFO_RESET_DONE 8 8 PIXEL_TO_SYMBOL_FIFO_OVERFLOW_STATUS 12 12 regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL 0 0x3733 2 0 2 MSA_DOUBLE_BUFFER_ENABLE 0 0 MSA_DOUBLE_BUFFER_PENDING 4 4 regDP_SYM32_ENC1_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL 0 0x3734 2 0 2 PIXEL_FORMAT_DOUBLE_BUFFER_ENABLE 0 0 PIXEL_FORMAT_DOUBLE_BUFFER_PENDING 4 4 regDP_SYM32_ENC1_DP_SYM32_ENC_VID_PIXEL_FORMAT 0 0x3735 3 0 2 PIXEL_ENCODING_TYPE 0 0 UNCOMPRESSED_PIXEL_ENCODING 4 5 UNCOMPRESSED_COMPONENT_DEPTH 8 9 regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA0 0 0x3736 1 0 2 MSA_DATA 0 31 regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA1 0 0x3737 1 0 2 MSA_DATA 0 31 regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA2 0 0x3738 1 0 2 MSA_DATA 0 31 regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA3 0 0x3739 1 0 2 MSA_DATA 0 31 regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA4 0 0x373a 1 0 2 MSA_DATA 0 31 regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA5 0 0x373b 1 0 2 MSA_DATA 0 31 regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA6 0 0x373c 1 0 2 MSA_DATA 0 31 regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA7 0 0x373d 1 0 2 MSA_DATA 0 31 regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA8 0 0x373e 1 0 2 MSA_DATA 0 31 regDP_SYM32_ENC1_DP_SYM32_ENC_HBLANK_CONTROL 0 0x373f 1 0 2 HBLANK_MINIMUM_SYMBOL_WIDTH 0 15 regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL0 0 0x3740 11 0 2 GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE 0 0 GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE 1 1 GSP_TRIGGER_ONE_SHOT_SEND 2 2 GSP_TRIGGER_ONE_SHOT_POSITION 3 3 GSP_DOUBLE_BUFFER_ENABLE 4 4 GSP_PAYLOAD_SIZE 5 6 GSP_SOF_REFERENCE 7 7 GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED 8 8 GSP_TRIGGER_TRANSMISSION_PENDING 9 9 GSP_DOUBLE_BUFFER_PENDING 10 10 GSP_TRANSMISSION_LINE_NUMBER 16 31 regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL1 0 0x3741 11 0 2 GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE 0 0 GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE 1 1 GSP_TRIGGER_ONE_SHOT_SEND 2 2 GSP_TRIGGER_ONE_SHOT_POSITION 3 3 GSP_DOUBLE_BUFFER_ENABLE 4 4 GSP_PAYLOAD_SIZE 5 6 GSP_SOF_REFERENCE 7 7 GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED 8 8 GSP_TRIGGER_TRANSMISSION_PENDING 9 9 GSP_DOUBLE_BUFFER_PENDING 10 10 GSP_TRANSMISSION_LINE_NUMBER 16 31 regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL2 0 0x3742 11 0 2 GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE 0 0 GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE 1 1 GSP_TRIGGER_ONE_SHOT_SEND 2 2 GSP_TRIGGER_ONE_SHOT_POSITION 3 3 GSP_DOUBLE_BUFFER_ENABLE 4 4 GSP_PAYLOAD_SIZE 5 6 GSP_SOF_REFERENCE 7 7 GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED 8 8 GSP_TRIGGER_TRANSMISSION_PENDING 9 9 GSP_DOUBLE_BUFFER_PENDING 10 10 GSP_TRANSMISSION_LINE_NUMBER 16 31 regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL3 0 0x3743 11 0 2 GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE 0 0 GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE 1 1 GSP_TRIGGER_ONE_SHOT_SEND 2 2 GSP_TRIGGER_ONE_SHOT_POSITION 3 3 GSP_DOUBLE_BUFFER_ENABLE 4 4 GSP_PAYLOAD_SIZE 5 6 GSP_SOF_REFERENCE 7 7 GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED 8 8 GSP_TRIGGER_TRANSMISSION_PENDING 9 9 GSP_DOUBLE_BUFFER_PENDING 10 10 GSP_TRANSMISSION_LINE_NUMBER 16 31 regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL4 0 0x3744 11 0 2 GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE 0 0 GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE 1 1 GSP_TRIGGER_ONE_SHOT_SEND 2 2 GSP_TRIGGER_ONE_SHOT_POSITION 3 3 GSP_DOUBLE_BUFFER_ENABLE 4 4 GSP_PAYLOAD_SIZE 5 6 GSP_SOF_REFERENCE 7 7 GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED 8 8 GSP_TRIGGER_TRANSMISSION_PENDING 9 9 GSP_DOUBLE_BUFFER_PENDING 10 10 GSP_TRANSMISSION_LINE_NUMBER 16 31 regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL5 0 0x3745 11 0 2 GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE 0 0 GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE 1 1 GSP_TRIGGER_ONE_SHOT_SEND 2 2 GSP_TRIGGER_ONE_SHOT_POSITION 3 3 GSP_DOUBLE_BUFFER_ENABLE 4 4 GSP_PAYLOAD_SIZE 5 6 GSP_SOF_REFERENCE 7 7 GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED 8 8 GSP_TRIGGER_TRANSMISSION_PENDING 9 9 GSP_DOUBLE_BUFFER_PENDING 10 10 GSP_TRANSMISSION_LINE_NUMBER 16 31 regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL6 0 0x3746 11 0 2 GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE 0 0 GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE 1 1 GSP_TRIGGER_ONE_SHOT_SEND 2 2 GSP_TRIGGER_ONE_SHOT_POSITION 3 3 GSP_DOUBLE_BUFFER_ENABLE 4 4 GSP_PAYLOAD_SIZE 5 6 GSP_SOF_REFERENCE 7 7 GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED 8 8 GSP_TRIGGER_TRANSMISSION_PENDING 9 9 GSP_DOUBLE_BUFFER_PENDING 10 10 GSP_TRANSMISSION_LINE_NUMBER 16 31 regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL7 0 0x3747 11 0 2 GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE 0 0 GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE 1 1 GSP_TRIGGER_ONE_SHOT_SEND 2 2 GSP_TRIGGER_ONE_SHOT_POSITION 3 3 GSP_DOUBLE_BUFFER_ENABLE 4 4 GSP_PAYLOAD_SIZE 5 6 GSP_SOF_REFERENCE 7 7 GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED 8 8 GSP_TRIGGER_TRANSMISSION_PENDING 9 9 GSP_DOUBLE_BUFFER_PENDING 10 10 GSP_TRANSMISSION_LINE_NUMBER 16 31 regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL8 0 0x3748 11 0 2 GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE 0 0 GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE 1 1 GSP_TRIGGER_ONE_SHOT_SEND 2 2 GSP_TRIGGER_ONE_SHOT_POSITION 3 3 GSP_DOUBLE_BUFFER_ENABLE 4 4 GSP_PAYLOAD_SIZE 5 6 GSP_SOF_REFERENCE 7 7 GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED 8 8 GSP_TRIGGER_TRANSMISSION_PENDING 9 9 GSP_DOUBLE_BUFFER_PENDING 10 10 GSP_TRANSMISSION_LINE_NUMBER 16 31 regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL9 0 0x3749 11 0 2 GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE 0 0 GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE 1 1 GSP_TRIGGER_ONE_SHOT_SEND 2 2 GSP_TRIGGER_ONE_SHOT_POSITION 3 3 GSP_DOUBLE_BUFFER_ENABLE 4 4 GSP_PAYLOAD_SIZE 5 6 GSP_SOF_REFERENCE 7 7 GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED 8 8 GSP_TRIGGER_TRANSMISSION_PENDING 9 9 GSP_DOUBLE_BUFFER_PENDING 10 10 GSP_TRANSMISSION_LINE_NUMBER 16 31 regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL10 0 0x374a 11 0 2 GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE 0 0 GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE 1 1 GSP_TRIGGER_ONE_SHOT_SEND 2 2 GSP_TRIGGER_ONE_SHOT_POSITION 3 3 GSP_DOUBLE_BUFFER_ENABLE 4 4 GSP_PAYLOAD_SIZE 5 6 GSP_SOF_REFERENCE 7 7 GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED 8 8 GSP_TRIGGER_TRANSMISSION_PENDING 9 9 GSP_DOUBLE_BUFFER_PENDING 10 10 GSP_TRANSMISSION_LINE_NUMBER 16 31 regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL11 0 0x374b 11 0 2 GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE 0 0 GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE 1 1 GSP_TRIGGER_ONE_SHOT_SEND 2 2 GSP_TRIGGER_ONE_SHOT_POSITION 3 3 GSP_DOUBLE_BUFFER_ENABLE 4 4 GSP_PAYLOAD_SIZE 5 6 GSP_SOF_REFERENCE 7 7 GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED 8 8 GSP_TRIGGER_TRANSMISSION_PENDING 9 9 GSP_DOUBLE_BUFFER_PENDING 10 10 GSP_TRANSMISSION_LINE_NUMBER 16 31 regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL12 0 0x374c 11 0 2 GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE 0 0 GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE 1 1 GSP_TRIGGER_ONE_SHOT_SEND 2 2 GSP_TRIGGER_ONE_SHOT_POSITION 3 3 GSP_DOUBLE_BUFFER_ENABLE 4 4 GSP_PAYLOAD_SIZE 5 6 GSP_SOF_REFERENCE 7 7 GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED 8 8 GSP_TRIGGER_TRANSMISSION_PENDING 9 9 GSP_DOUBLE_BUFFER_PENDING 10 10 GSP_TRANSMISSION_LINE_NUMBER 16 31 regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL13 0 0x374d 11 0 2 GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE 0 0 GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE 1 1 GSP_TRIGGER_ONE_SHOT_SEND 2 2 GSP_TRIGGER_ONE_SHOT_POSITION 3 3 GSP_DOUBLE_BUFFER_ENABLE 4 4 GSP_PAYLOAD_SIZE 5 6 GSP_SOF_REFERENCE 7 7 GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED 8 8 GSP_TRIGGER_TRANSMISSION_PENDING 9 9 GSP_DOUBLE_BUFFER_PENDING 10 10 GSP_TRANSMISSION_LINE_NUMBER 16 31 regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL14 0 0x374e 11 0 2 GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE 0 0 GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE 1 1 GSP_TRIGGER_ONE_SHOT_SEND 2 2 GSP_TRIGGER_ONE_SHOT_POSITION 3 3 GSP_DOUBLE_BUFFER_ENABLE 4 4 GSP_PAYLOAD_SIZE 5 6 GSP_SOF_REFERENCE 7 7 GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED 8 8 GSP_TRIGGER_TRANSMISSION_PENDING 9 9 GSP_DOUBLE_BUFFER_PENDING 10 10 GSP_TRANSMISSION_LINE_NUMBER 16 31 regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_CONTROL 0 0x374f 3 0 2 SDP_STREAM_ENABLE 0 0 GSP0_PRIORITY 4 4 SDP_CRC16_ENABLE 8 8 regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_AUDIO_CONTROL0 0 0x3750 9 0 2 ASP_ENABLE 0 0 ATP_ENABLE 1 1 AIP_ENABLE 2 2 ACM_ENABLE 3 3 ISRC_ENABLE 4 4 ASP_PRIORITY 5 5 ATP_VERSION_NUMBER 8 13 AUDIO_MUTE 28 28 AUDIO_MUTE_STATUS 29 29 regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_AUDIO_CONTROL1 0 0x3751 4 0 2 ASP_CONCATENATION_ENABLE 0 0 ASP_CONCATENATION_2_CHANNEL_LAYOUT_MAX_SAMPLE_COUNT 4 9 ASP_CONCATENATION_8_CHANNEL_LAYOUT_MAX_SAMPLE_COUNT 12 17 ASP_CONCATENATION_HBR_LAYOUT_MAX_SAMPLE_COUNT 20 25 regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL 0 0x3752 5 0 2 METADATA_PACKET_ENABLE 0 0 METADATA_DOUBLE_BUFFER_ENABLE 4 4 METADATA_PACKET_SOF_REFERENCE 8 8 METADATA_PACKET_DOUBLE_BUFFER_PENDING 12 12 METADATA_PACKET_TRANSMISSION_LINE_NUMBER 16 31 regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA_CONTROL 0 0x3757 2 0 2 MSA_MISC1_STEREOSYNC_OVERRIDE_EN 0 0 MSA_TRANSMISSION_LINE_NUMBER 16 31 regDP_SYM32_ENC1_DP_SYM32_ENC_VID_VBID_CONTROL 0 0x3758 2 0 2 VBID_6_COMPRESSEDSTREAM_FLAG_SOF_REFERENCE 0 0 VBID_6_COMPRESSEDSTREAM_FLAG_LINE_NUMBER 16 31 regDP_SYM32_ENC1_DP_SYM32_ENC_VID_STREAM_CONTROL 0 0x3759 3 0 2 VID_STREAM_ENABLE 0 0 VID_STREAM_DISABLE_DEFER 4 5 VID_STREAM_STATUS 8 8 regDP_SYM32_ENC1_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL 0 0x375a 2 0 2 PANEL_REPLAY_TUNNELING_OPTIMIZATION_ENABLE 0 0 PANEL_REPLAY_TUNNELING_OPTIMIZATION_DOUBLE_BUFFER_ENABLE 4 4 regDP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_CONTROL 0 0x375b 2 0 2 CRC_ENABLE 0 0 CRC_CONT_MODE_ENABLE 4 4 regDP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_RESULT0 0 0x375c 2 0 2 CRC_RESULT0 0 15 CRC_RESULT1 16 31 regDP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_RESULT1 0 0x375d 2 0 2 CRC_RESULT2 0 15 CRC_RESULT3 16 31 regDP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_STATUS 0 0x375e 1 0 2 CRC_VALID 0 0 regDP_SYM32_ENC1_DP_SYM32_ENC_MEM_POWER_CONTROL 0 0x375f 4 0 2 MEM_DEFAULT_LOW_POWER_STATE 0 1 MEM_PWR_FORCE 4 5 MEM_PWR_DIS 8 8 MEM_PWR_STATE 12 13 regDP_SYM32_ENC1_DP_SYM32_ENC_SPARE 0 0x3760 1 0 2 DP_SYM32_ENC_SPARE 0 31 regDP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_CONTROL 0 0x37cb 5 0 2 DP_STREAM_ENC_CLOCK_EN 0 0 DP_STREAM_ENC_CLOCK_ON_DISPCLK 4 4 DP_STREAM_ENC_CLOCK_ON_SOCCLK 8 8 DP_STREAM_ENC_CLOCK_ON_DPSTREAMCLK 12 12 DP_STREAM_ENC_CLOCK_ON_SYMCLK32 16 16 regDP_STREAM_ENC2_DP_STREAM_ENC_INPUT_MUX_CONTROL 0 0x37cc 1 0 2 DP_STREAM_ENC_INPUT_MUX_PIXEL_STREAM_SOURCE_SEL 0 2 regDP_STREAM_ENC2_DP_STREAM_ENC_AUDIO_CONTROL 0 0x37cd 1 0 2 DP_STREAM_ENC_INPUT_MUX_AUDIO_STREAM_SOURCE_SEL 0 2 regDP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0 0 0x37ce 7 0 2 FIFO_ENABLE 0 0 FIFO_RESET 4 4 FIFO_READ_START_LEVEL 8 12 FIFO_READ_CLOCK_SRC 16 16 FIFO_RESET_DONE 20 20 FIFO_VIDEO_STREAM_ACTIVE 24 24 FIFO_ERROR 28 29 regDP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1 0 0x37cf 8 0 2 FIFO_USE_OVERWRITE_LEVEL 0 0 FIFO_FORCE_RECAL_AVERAGE 1 1 FIFO_FORCE_RECOMP_MINMAX 2 2 FIFO_OVERWRITE_LEVEL 4 9 FIFO_MINIMUM_LEVEL 12 15 FIFO_MAXIMUM_LEVEL 16 20 FIFO_CAL_AVERAGE_LEVEL 24 29 FIFO_CALIBRATED 31 31 regDP_STREAM_ENC2_DP_STREAM_ENC_SPARE 0 0x37d0 1 0 2 DP_STREAM_ENC_SPARE 0 31 regAPG2_APG_CONTROL 0 0x37d8 2 0 2 APG_RESET 1 1 APG_RESET_DONE 2 2 regAPG2_APG_CONTROL2 0 0x37d9 3 0 2 APG_ENABLE 0 0 APG_DP_AUDIO_STREAM_ID 8 15 APG_DP_ASP_CHANNEL_COUNT_OVERRIDE 24 24 regAPG2_APG_DBG_GEN_CONTROL 0 0x37da 4 0 2 APG_DBG_GEN_ENABLE 0 0 APG_DBG_GEN_RESET 1 1 APG_DBG_AUDIO_CHANNEL_ENABLE 8 15 APG_DBG_AUDIO_TEST_CH_DISABLE 24 31 regAPG2_APG_PACKET_CONTROL 0 0x37db 3 0 2 APG_DBG_MUX_SEL 0 0 APG_ACP_SOURCE 1 1 APG_AUDIO_INFO_SOURCE 2 2 regAPG2_APG_AUDIO_CRC_CONTROL 0 0x37e2 4 0 2 APG_AUDIO_CRC_EN 0 0 APG_AUDIO_CRC_CONT 4 4 APG_AUDIO_CRC_CH_SEL 13 15 APG_AUDIO_CRC_COUNT 16 31 regAPG2_APG_AUDIO_CRC_CONTROL2 0 0x37e3 1 0 2 APG_AUDIO_CRC_COUNT_FORCE_DEFAULT 0 15 regAPG2_APG_AUDIO_CRC_RESULT 0 0x37e4 3 0 2 APG_AUDIO_CRC_DONE 0 0 APG_AUDIO_CRC_DONE_CLEAR 8 8 APG_AUDIO_CRC 16 31 regAPG2_APG_STATUS 0 0x37e9 4 0 2 APG_AUDIO_ENABLE 4 4 APG_HBR_ENABLE 8 8 APG_AUDIO_FIFO_OVERFLOW_STATUS 24 24 APG_AUDIO_FIFO_OVERFLOW_STATUS_CLEAR 25 25 regAPG2_APG_STATUS2 0 0x37ea 1 0 2 APG_OUTPUT_ACTIVE 0 0 regAPG2_APG_MEM_PWR 0 0x37ec 4 0 2 APG_MEM_PWR_DIS 0 0 APG_MEM_PWR_FORCE 4 5 APG_MEM_PWR_STATE 8 9 APG_MEM_DEFAULT_LOW_POWER_STATE 12 13 regAPG2_APG_SPARE 0 0x37ee 1 0 2 APG_SPARE 0 31 regDME8_DME_CONTROL 0 0x37f6 9 0 2 METADATA_HUBP_REQUESTOR_ID 0 2 METADATA_ENGINE_EN 4 4 METADATA_STREAM_TYPE 8 8 METADATA_DB_PENDING 12 12 METADATA_DB_TAKEN 13 13 METADATA_DB_TAKEN_CLR 16 16 METADATA_DB_DISABLE 20 20 METADATA_TRANSMISSION_MISSED 24 24 METADATA_TRANSMISSION_MISSED_CLR 25 25 regDME8_DME_MEMORY_CONTROL 0 0x37f7 4 0 2 DME_MEM_PWR_FORCE 0 1 DME_MEM_PWR_DIS 4 4 DME_MEM_PWR_STATE 8 9 DME_MEM_DEFAULT_MEM_LOW_POWER_STATE 12 13 regVPG8_VPG_GENERIC_PACKET_ACCESS_CTRL 0 0x37f9 1 0 2 VPG_GENERIC_DATA_INDEX 0 7 regVPG8_VPG_GENERIC_PACKET_DATA 0 0x37fa 4 0 2 VPG_GENERIC_DATA_BYTE0 0 7 VPG_GENERIC_DATA_BYTE1 8 15 VPG_GENERIC_DATA_BYTE2 16 23 VPG_GENERIC_DATA_BYTE3 24 31 regVPG8_VPG_GSP_FRAME_UPDATE_CTRL 0 0x37fb 30 0 2 VPG_GENERIC0_FRAME_UPDATE 0 0 VPG_GENERIC1_FRAME_UPDATE 1 1 VPG_GENERIC2_FRAME_UPDATE 2 2 VPG_GENERIC3_FRAME_UPDATE 3 3 VPG_GENERIC4_FRAME_UPDATE 4 4 VPG_GENERIC5_FRAME_UPDATE 5 5 VPG_GENERIC6_FRAME_UPDATE 6 6 VPG_GENERIC7_FRAME_UPDATE 7 7 VPG_GENERIC8_FRAME_UPDATE 8 8 VPG_GENERIC9_FRAME_UPDATE 9 9 VPG_GENERIC10_FRAME_UPDATE 10 10 VPG_GENERIC11_FRAME_UPDATE 11 11 VPG_GENERIC12_FRAME_UPDATE 12 12 VPG_GENERIC13_FRAME_UPDATE 13 13 VPG_GENERIC14_FRAME_UPDATE 14 14 VPG_GENERIC0_FRAME_UPDATE_PENDING 16 16 VPG_GENERIC1_FRAME_UPDATE_PENDING 17 17 VPG_GENERIC2_FRAME_UPDATE_PENDING 18 18 VPG_GENERIC3_FRAME_UPDATE_PENDING 19 19 VPG_GENERIC4_FRAME_UPDATE_PENDING 20 20 VPG_GENERIC5_FRAME_UPDATE_PENDING 21 21 VPG_GENERIC6_FRAME_UPDATE_PENDING 22 22 VPG_GENERIC7_FRAME_UPDATE_PENDING 23 23 VPG_GENERIC8_FRAME_UPDATE_PENDING 24 24 VPG_GENERIC9_FRAME_UPDATE_PENDING 25 25 VPG_GENERIC10_FRAME_UPDATE_PENDING 26 26 VPG_GENERIC11_FRAME_UPDATE_PENDING 27 27 VPG_GENERIC12_FRAME_UPDATE_PENDING 28 28 VPG_GENERIC13_FRAME_UPDATE_PENDING 29 29 VPG_GENERIC14_FRAME_UPDATE_PENDING 30 30 regVPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL 0 0x37fc 30 0 2 VPG_GENERIC0_IMMEDIATE_UPDATE 0 0 VPG_GENERIC1_IMMEDIATE_UPDATE 1 1 VPG_GENERIC2_IMMEDIATE_UPDATE 2 2 VPG_GENERIC3_IMMEDIATE_UPDATE 3 3 VPG_GENERIC4_IMMEDIATE_UPDATE 4 4 VPG_GENERIC5_IMMEDIATE_UPDATE 5 5 VPG_GENERIC6_IMMEDIATE_UPDATE 6 6 VPG_GENERIC7_IMMEDIATE_UPDATE 7 7 VPG_GENERIC8_IMMEDIATE_UPDATE 8 8 VPG_GENERIC9_IMMEDIATE_UPDATE 9 9 VPG_GENERIC10_IMMEDIATE_UPDATE 10 10 VPG_GENERIC11_IMMEDIATE_UPDATE 11 11 VPG_GENERIC12_IMMEDIATE_UPDATE 12 12 VPG_GENERIC13_IMMEDIATE_UPDATE 13 13 VPG_GENERIC14_IMMEDIATE_UPDATE 14 14 VPG_GENERIC0_IMMEDIATE_UPDATE_PENDING 16 16 VPG_GENERIC1_IMMEDIATE_UPDATE_PENDING 17 17 VPG_GENERIC2_IMMEDIATE_UPDATE_PENDING 18 18 VPG_GENERIC3_IMMEDIATE_UPDATE_PENDING 19 19 VPG_GENERIC4_IMMEDIATE_UPDATE_PENDING 20 20 VPG_GENERIC5_IMMEDIATE_UPDATE_PENDING 21 21 VPG_GENERIC6_IMMEDIATE_UPDATE_PENDING 22 22 VPG_GENERIC7_IMMEDIATE_UPDATE_PENDING 23 23 VPG_GENERIC8_IMMEDIATE_UPDATE_PENDING 24 24 VPG_GENERIC9_IMMEDIATE_UPDATE_PENDING 25 25 VPG_GENERIC10_IMMEDIATE_UPDATE_PENDING 26 26 VPG_GENERIC11_IMMEDIATE_UPDATE_PENDING 27 27 VPG_GENERIC12_IMMEDIATE_UPDATE_PENDING 28 28 VPG_GENERIC13_IMMEDIATE_UPDATE_PENDING 29 29 VPG_GENERIC14_IMMEDIATE_UPDATE_PENDING 30 30 regVPG8_VPG_GENERIC_STATUS 0 0x37fd 3 0 2 VPG_GENERIC_LOCK_STATUS 0 0 VPG_GENERIC_CONFLICT_OCCURED 1 1 VPG_GENERIC_CONFLICT_CLR 4 4 regVPG8_VPG_MEM_PWR 0 0x37fe 3 0 2 VPG_GSP_MEM_LIGHT_SLEEP_DIS 0 0 VPG_GSP_LIGHT_SLEEP_FORCE 4 4 VPG_GSP_MEM_PWR_STATE 8 8 regVPG8_VPG_ISRC1_2_ACCESS_CTRL 0 0x37ff 1 0 2 VPG_ISRC1_2_DATA_INDEX 0 3 regVPG8_VPG_ISRC1_2_DATA 0 0x3800 4 0 2 VPG_ISRC_DATA_BYTE0 0 7 VPG_ISRC_DATA_BYTE1 8 15 VPG_ISRC_DATA_BYTE2 16 23 VPG_ISRC_DATA_BYTE3 24 31 regVPG8_VPG_MPEG_INFO0 0 0x3801 4 0 2 VPG_MPEG_INFO_CHECKSUM 0 7 VPG_MPEG_INFO_MB0 8 15 VPG_MPEG_INFO_MB1 16 23 VPG_MPEG_INFO_MB2 24 31 regVPG8_VPG_MPEG_INFO1 0 0x3802 4 0 2 VPG_MPEG_INFO_MB3 0 7 VPG_MPEG_INFO_MF 8 9 VPG_MPEG_INFO_FR 12 12 VPG_MPEG_INFO_UPDATE 16 16 regDP_SYM32_ENC2_DP_SYM32_ENC_CONTROL 0 0x3805 3 0 2 DP_SYM32_ENC_ENABLE 0 0 DP_SYM32_ENC_RESET 4 4 DP_SYM32_ENC_RESET_DONE 8 8 regDP_SYM32_ENC2_DP_SYM32_ENC_VID_FIFO_CONTROL 0 0x3806 4 0 2 PIXEL_TO_SYMBOL_FIFO_ENABLE 0 0 PIXEL_TO_SYMBOL_FIFO_RESET 4 4 PIXEL_TO_SYMBOL_FIFO_RESET_DONE 8 8 PIXEL_TO_SYMBOL_FIFO_OVERFLOW_STATUS 12 12 regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL 0 0x3807 2 0 2 MSA_DOUBLE_BUFFER_ENABLE 0 0 MSA_DOUBLE_BUFFER_PENDING 4 4 regDP_SYM32_ENC2_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL 0 0x3808 2 0 2 PIXEL_FORMAT_DOUBLE_BUFFER_ENABLE 0 0 PIXEL_FORMAT_DOUBLE_BUFFER_PENDING 4 4 regDP_SYM32_ENC2_DP_SYM32_ENC_VID_PIXEL_FORMAT 0 0x3809 3 0 2 PIXEL_ENCODING_TYPE 0 0 UNCOMPRESSED_PIXEL_ENCODING 4 5 UNCOMPRESSED_COMPONENT_DEPTH 8 9 regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA0 0 0x380a 1 0 2 MSA_DATA 0 31 regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA1 0 0x380b 1 0 2 MSA_DATA 0 31 regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA2 0 0x380c 1 0 2 MSA_DATA 0 31 regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA3 0 0x380d 1 0 2 MSA_DATA 0 31 regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA4 0 0x380e 1 0 2 MSA_DATA 0 31 regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA5 0 0x380f 1 0 2 MSA_DATA 0 31 regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA6 0 0x3810 1 0 2 MSA_DATA 0 31 regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA7 0 0x3811 1 0 2 MSA_DATA 0 31 regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA8 0 0x3812 1 0 2 MSA_DATA 0 31 regDP_SYM32_ENC2_DP_SYM32_ENC_HBLANK_CONTROL 0 0x3813 1 0 2 HBLANK_MINIMUM_SYMBOL_WIDTH 0 15 regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL0 0 0x3814 11 0 2 GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE 0 0 GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE 1 1 GSP_TRIGGER_ONE_SHOT_SEND 2 2 GSP_TRIGGER_ONE_SHOT_POSITION 3 3 GSP_DOUBLE_BUFFER_ENABLE 4 4 GSP_PAYLOAD_SIZE 5 6 GSP_SOF_REFERENCE 7 7 GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED 8 8 GSP_TRIGGER_TRANSMISSION_PENDING 9 9 GSP_DOUBLE_BUFFER_PENDING 10 10 GSP_TRANSMISSION_LINE_NUMBER 16 31 regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL1 0 0x3815 11 0 2 GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE 0 0 GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE 1 1 GSP_TRIGGER_ONE_SHOT_SEND 2 2 GSP_TRIGGER_ONE_SHOT_POSITION 3 3 GSP_DOUBLE_BUFFER_ENABLE 4 4 GSP_PAYLOAD_SIZE 5 6 GSP_SOF_REFERENCE 7 7 GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED 8 8 GSP_TRIGGER_TRANSMISSION_PENDING 9 9 GSP_DOUBLE_BUFFER_PENDING 10 10 GSP_TRANSMISSION_LINE_NUMBER 16 31 regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL2 0 0x3816 11 0 2 GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE 0 0 GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE 1 1 GSP_TRIGGER_ONE_SHOT_SEND 2 2 GSP_TRIGGER_ONE_SHOT_POSITION 3 3 GSP_DOUBLE_BUFFER_ENABLE 4 4 GSP_PAYLOAD_SIZE 5 6 GSP_SOF_REFERENCE 7 7 GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED 8 8 GSP_TRIGGER_TRANSMISSION_PENDING 9 9 GSP_DOUBLE_BUFFER_PENDING 10 10 GSP_TRANSMISSION_LINE_NUMBER 16 31 regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL3 0 0x3817 11 0 2 GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE 0 0 GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE 1 1 GSP_TRIGGER_ONE_SHOT_SEND 2 2 GSP_TRIGGER_ONE_SHOT_POSITION 3 3 GSP_DOUBLE_BUFFER_ENABLE 4 4 GSP_PAYLOAD_SIZE 5 6 GSP_SOF_REFERENCE 7 7 GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED 8 8 GSP_TRIGGER_TRANSMISSION_PENDING 9 9 GSP_DOUBLE_BUFFER_PENDING 10 10 GSP_TRANSMISSION_LINE_NUMBER 16 31 regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL4 0 0x3818 11 0 2 GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE 0 0 GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE 1 1 GSP_TRIGGER_ONE_SHOT_SEND 2 2 GSP_TRIGGER_ONE_SHOT_POSITION 3 3 GSP_DOUBLE_BUFFER_ENABLE 4 4 GSP_PAYLOAD_SIZE 5 6 GSP_SOF_REFERENCE 7 7 GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED 8 8 GSP_TRIGGER_TRANSMISSION_PENDING 9 9 GSP_DOUBLE_BUFFER_PENDING 10 10 GSP_TRANSMISSION_LINE_NUMBER 16 31 regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL5 0 0x3819 11 0 2 GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE 0 0 GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE 1 1 GSP_TRIGGER_ONE_SHOT_SEND 2 2 GSP_TRIGGER_ONE_SHOT_POSITION 3 3 GSP_DOUBLE_BUFFER_ENABLE 4 4 GSP_PAYLOAD_SIZE 5 6 GSP_SOF_REFERENCE 7 7 GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED 8 8 GSP_TRIGGER_TRANSMISSION_PENDING 9 9 GSP_DOUBLE_BUFFER_PENDING 10 10 GSP_TRANSMISSION_LINE_NUMBER 16 31 regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL6 0 0x381a 11 0 2 GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE 0 0 GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE 1 1 GSP_TRIGGER_ONE_SHOT_SEND 2 2 GSP_TRIGGER_ONE_SHOT_POSITION 3 3 GSP_DOUBLE_BUFFER_ENABLE 4 4 GSP_PAYLOAD_SIZE 5 6 GSP_SOF_REFERENCE 7 7 GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED 8 8 GSP_TRIGGER_TRANSMISSION_PENDING 9 9 GSP_DOUBLE_BUFFER_PENDING 10 10 GSP_TRANSMISSION_LINE_NUMBER 16 31 regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL7 0 0x381b 11 0 2 GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE 0 0 GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE 1 1 GSP_TRIGGER_ONE_SHOT_SEND 2 2 GSP_TRIGGER_ONE_SHOT_POSITION 3 3 GSP_DOUBLE_BUFFER_ENABLE 4 4 GSP_PAYLOAD_SIZE 5 6 GSP_SOF_REFERENCE 7 7 GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED 8 8 GSP_TRIGGER_TRANSMISSION_PENDING 9 9 GSP_DOUBLE_BUFFER_PENDING 10 10 GSP_TRANSMISSION_LINE_NUMBER 16 31 regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL8 0 0x381c 11 0 2 GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE 0 0 GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE 1 1 GSP_TRIGGER_ONE_SHOT_SEND 2 2 GSP_TRIGGER_ONE_SHOT_POSITION 3 3 GSP_DOUBLE_BUFFER_ENABLE 4 4 GSP_PAYLOAD_SIZE 5 6 GSP_SOF_REFERENCE 7 7 GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED 8 8 GSP_TRIGGER_TRANSMISSION_PENDING 9 9 GSP_DOUBLE_BUFFER_PENDING 10 10 GSP_TRANSMISSION_LINE_NUMBER 16 31 regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL9 0 0x381d 11 0 2 GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE 0 0 GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE 1 1 GSP_TRIGGER_ONE_SHOT_SEND 2 2 GSP_TRIGGER_ONE_SHOT_POSITION 3 3 GSP_DOUBLE_BUFFER_ENABLE 4 4 GSP_PAYLOAD_SIZE 5 6 GSP_SOF_REFERENCE 7 7 GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED 8 8 GSP_TRIGGER_TRANSMISSION_PENDING 9 9 GSP_DOUBLE_BUFFER_PENDING 10 10 GSP_TRANSMISSION_LINE_NUMBER 16 31 regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL10 0 0x381e 11 0 2 GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE 0 0 GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE 1 1 GSP_TRIGGER_ONE_SHOT_SEND 2 2 GSP_TRIGGER_ONE_SHOT_POSITION 3 3 GSP_DOUBLE_BUFFER_ENABLE 4 4 GSP_PAYLOAD_SIZE 5 6 GSP_SOF_REFERENCE 7 7 GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED 8 8 GSP_TRIGGER_TRANSMISSION_PENDING 9 9 GSP_DOUBLE_BUFFER_PENDING 10 10 GSP_TRANSMISSION_LINE_NUMBER 16 31 regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL11 0 0x381f 11 0 2 GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE 0 0 GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE 1 1 GSP_TRIGGER_ONE_SHOT_SEND 2 2 GSP_TRIGGER_ONE_SHOT_POSITION 3 3 GSP_DOUBLE_BUFFER_ENABLE 4 4 GSP_PAYLOAD_SIZE 5 6 GSP_SOF_REFERENCE 7 7 GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED 8 8 GSP_TRIGGER_TRANSMISSION_PENDING 9 9 GSP_DOUBLE_BUFFER_PENDING 10 10 GSP_TRANSMISSION_LINE_NUMBER 16 31 regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL12 0 0x3820 11 0 2 GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE 0 0 GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE 1 1 GSP_TRIGGER_ONE_SHOT_SEND 2 2 GSP_TRIGGER_ONE_SHOT_POSITION 3 3 GSP_DOUBLE_BUFFER_ENABLE 4 4 GSP_PAYLOAD_SIZE 5 6 GSP_SOF_REFERENCE 7 7 GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED 8 8 GSP_TRIGGER_TRANSMISSION_PENDING 9 9 GSP_DOUBLE_BUFFER_PENDING 10 10 GSP_TRANSMISSION_LINE_NUMBER 16 31 regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL13 0 0x3821 11 0 2 GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE 0 0 GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE 1 1 GSP_TRIGGER_ONE_SHOT_SEND 2 2 GSP_TRIGGER_ONE_SHOT_POSITION 3 3 GSP_DOUBLE_BUFFER_ENABLE 4 4 GSP_PAYLOAD_SIZE 5 6 GSP_SOF_REFERENCE 7 7 GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED 8 8 GSP_TRIGGER_TRANSMISSION_PENDING 9 9 GSP_DOUBLE_BUFFER_PENDING 10 10 GSP_TRANSMISSION_LINE_NUMBER 16 31 regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL14 0 0x3822 11 0 2 GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE 0 0 GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE 1 1 GSP_TRIGGER_ONE_SHOT_SEND 2 2 GSP_TRIGGER_ONE_SHOT_POSITION 3 3 GSP_DOUBLE_BUFFER_ENABLE 4 4 GSP_PAYLOAD_SIZE 5 6 GSP_SOF_REFERENCE 7 7 GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED 8 8 GSP_TRIGGER_TRANSMISSION_PENDING 9 9 GSP_DOUBLE_BUFFER_PENDING 10 10 GSP_TRANSMISSION_LINE_NUMBER 16 31 regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_CONTROL 0 0x3823 3 0 2 SDP_STREAM_ENABLE 0 0 GSP0_PRIORITY 4 4 SDP_CRC16_ENABLE 8 8 regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_AUDIO_CONTROL0 0 0x3824 9 0 2 ASP_ENABLE 0 0 ATP_ENABLE 1 1 AIP_ENABLE 2 2 ACM_ENABLE 3 3 ISRC_ENABLE 4 4 ASP_PRIORITY 5 5 ATP_VERSION_NUMBER 8 13 AUDIO_MUTE 28 28 AUDIO_MUTE_STATUS 29 29 regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_AUDIO_CONTROL1 0 0x3825 4 0 2 ASP_CONCATENATION_ENABLE 0 0 ASP_CONCATENATION_2_CHANNEL_LAYOUT_MAX_SAMPLE_COUNT 4 9 ASP_CONCATENATION_8_CHANNEL_LAYOUT_MAX_SAMPLE_COUNT 12 17 ASP_CONCATENATION_HBR_LAYOUT_MAX_SAMPLE_COUNT 20 25 regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL 0 0x3826 5 0 2 METADATA_PACKET_ENABLE 0 0 METADATA_DOUBLE_BUFFER_ENABLE 4 4 METADATA_PACKET_SOF_REFERENCE 8 8 METADATA_PACKET_DOUBLE_BUFFER_PENDING 12 12 METADATA_PACKET_TRANSMISSION_LINE_NUMBER 16 31 regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA_CONTROL 0 0x382b 2 0 2 MSA_MISC1_STEREOSYNC_OVERRIDE_EN 0 0 MSA_TRANSMISSION_LINE_NUMBER 16 31 regDP_SYM32_ENC2_DP_SYM32_ENC_VID_VBID_CONTROL 0 0x382c 2 0 2 VBID_6_COMPRESSEDSTREAM_FLAG_SOF_REFERENCE 0 0 VBID_6_COMPRESSEDSTREAM_FLAG_LINE_NUMBER 16 31 regDP_SYM32_ENC2_DP_SYM32_ENC_VID_STREAM_CONTROL 0 0x382d 3 0 2 VID_STREAM_ENABLE 0 0 VID_STREAM_DISABLE_DEFER 4 5 VID_STREAM_STATUS 8 8 regDP_SYM32_ENC2_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL 0 0x382e 2 0 2 PANEL_REPLAY_TUNNELING_OPTIMIZATION_ENABLE 0 0 PANEL_REPLAY_TUNNELING_OPTIMIZATION_DOUBLE_BUFFER_ENABLE 4 4 regDP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_CONTROL 0 0x382f 2 0 2 CRC_ENABLE 0 0 CRC_CONT_MODE_ENABLE 4 4 regDP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_RESULT0 0 0x3830 2 0 2 CRC_RESULT0 0 15 CRC_RESULT1 16 31 regDP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_RESULT1 0 0x3831 2 0 2 CRC_RESULT2 0 15 CRC_RESULT3 16 31 regDP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_STATUS 0 0x3832 1 0 2 CRC_VALID 0 0 regDP_SYM32_ENC2_DP_SYM32_ENC_MEM_POWER_CONTROL 0 0x3833 4 0 2 MEM_DEFAULT_LOW_POWER_STATE 0 1 MEM_PWR_FORCE 4 5 MEM_PWR_DIS 8 8 MEM_PWR_STATE 12 13 regDP_SYM32_ENC2_DP_SYM32_ENC_SPARE 0 0x3834 1 0 2 DP_SYM32_ENC_SPARE 0 31 regDP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_CONTROL 0 0x389f 5 0 2 DP_STREAM_ENC_CLOCK_EN 0 0 DP_STREAM_ENC_CLOCK_ON_DISPCLK 4 4 DP_STREAM_ENC_CLOCK_ON_SOCCLK 8 8 DP_STREAM_ENC_CLOCK_ON_DPSTREAMCLK 12 12 DP_STREAM_ENC_CLOCK_ON_SYMCLK32 16 16 regDP_STREAM_ENC3_DP_STREAM_ENC_INPUT_MUX_CONTROL 0 0x38a0 1 0 2 DP_STREAM_ENC_INPUT_MUX_PIXEL_STREAM_SOURCE_SEL 0 2 regDP_STREAM_ENC3_DP_STREAM_ENC_AUDIO_CONTROL 0 0x38a1 1 0 2 DP_STREAM_ENC_INPUT_MUX_AUDIO_STREAM_SOURCE_SEL 0 2 regDP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0 0 0x38a2 7 0 2 FIFO_ENABLE 0 0 FIFO_RESET 4 4 FIFO_READ_START_LEVEL 8 12 FIFO_READ_CLOCK_SRC 16 16 FIFO_RESET_DONE 20 20 FIFO_VIDEO_STREAM_ACTIVE 24 24 FIFO_ERROR 28 29 regDP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1 0 0x38a3 8 0 2 FIFO_USE_OVERWRITE_LEVEL 0 0 FIFO_FORCE_RECAL_AVERAGE 1 1 FIFO_FORCE_RECOMP_MINMAX 2 2 FIFO_OVERWRITE_LEVEL 4 9 FIFO_MINIMUM_LEVEL 12 15 FIFO_MAXIMUM_LEVEL 16 20 FIFO_CAL_AVERAGE_LEVEL 24 29 FIFO_CALIBRATED 31 31 regDP_STREAM_ENC3_DP_STREAM_ENC_SPARE 0 0x38a4 1 0 2 DP_STREAM_ENC_SPARE 0 31 regAPG3_APG_CONTROL 0 0x38ac 2 0 2 APG_RESET 1 1 APG_RESET_DONE 2 2 regAPG3_APG_CONTROL2 0 0x38ad 3 0 2 APG_ENABLE 0 0 APG_DP_AUDIO_STREAM_ID 8 15 APG_DP_ASP_CHANNEL_COUNT_OVERRIDE 24 24 regAPG3_APG_DBG_GEN_CONTROL 0 0x38ae 4 0 2 APG_DBG_GEN_ENABLE 0 0 APG_DBG_GEN_RESET 1 1 APG_DBG_AUDIO_CHANNEL_ENABLE 8 15 APG_DBG_AUDIO_TEST_CH_DISABLE 24 31 regAPG3_APG_PACKET_CONTROL 0 0x38af 3 0 2 APG_DBG_MUX_SEL 0 0 APG_ACP_SOURCE 1 1 APG_AUDIO_INFO_SOURCE 2 2 regAPG3_APG_AUDIO_CRC_CONTROL 0 0x38b6 4 0 2 APG_AUDIO_CRC_EN 0 0 APG_AUDIO_CRC_CONT 4 4 APG_AUDIO_CRC_CH_SEL 13 15 APG_AUDIO_CRC_COUNT 16 31 regAPG3_APG_AUDIO_CRC_CONTROL2 0 0x38b7 1 0 2 APG_AUDIO_CRC_COUNT_FORCE_DEFAULT 0 15 regAPG3_APG_AUDIO_CRC_RESULT 0 0x38b8 3 0 2 APG_AUDIO_CRC_DONE 0 0 APG_AUDIO_CRC_DONE_CLEAR 8 8 APG_AUDIO_CRC 16 31 regAPG3_APG_STATUS 0 0x38bd 4 0 2 APG_AUDIO_ENABLE 4 4 APG_HBR_ENABLE 8 8 APG_AUDIO_FIFO_OVERFLOW_STATUS 24 24 APG_AUDIO_FIFO_OVERFLOW_STATUS_CLEAR 25 25 regAPG3_APG_STATUS2 0 0x38be 1 0 2 APG_OUTPUT_ACTIVE 0 0 regAPG3_APG_MEM_PWR 0 0x38c0 4 0 2 APG_MEM_PWR_DIS 0 0 APG_MEM_PWR_FORCE 4 5 APG_MEM_PWR_STATE 8 9 APG_MEM_DEFAULT_LOW_POWER_STATE 12 13 regAPG3_APG_SPARE 0 0x38c2 1 0 2 APG_SPARE 0 31 regDME9_DME_CONTROL 0 0x38ca 9 0 2 METADATA_HUBP_REQUESTOR_ID 0 2 METADATA_ENGINE_EN 4 4 METADATA_STREAM_TYPE 8 8 METADATA_DB_PENDING 12 12 METADATA_DB_TAKEN 13 13 METADATA_DB_TAKEN_CLR 16 16 METADATA_DB_DISABLE 20 20 METADATA_TRANSMISSION_MISSED 24 24 METADATA_TRANSMISSION_MISSED_CLR 25 25 regDME9_DME_MEMORY_CONTROL 0 0x38cb 4 0 2 DME_MEM_PWR_FORCE 0 1 DME_MEM_PWR_DIS 4 4 DME_MEM_PWR_STATE 8 9 DME_MEM_DEFAULT_MEM_LOW_POWER_STATE 12 13 regVPG9_VPG_GENERIC_PACKET_ACCESS_CTRL 0 0x38cd 1 0 2 VPG_GENERIC_DATA_INDEX 0 7 regVPG9_VPG_GENERIC_PACKET_DATA 0 0x38ce 4 0 2 VPG_GENERIC_DATA_BYTE0 0 7 VPG_GENERIC_DATA_BYTE1 8 15 VPG_GENERIC_DATA_BYTE2 16 23 VPG_GENERIC_DATA_BYTE3 24 31 regVPG9_VPG_GSP_FRAME_UPDATE_CTRL 0 0x38cf 30 0 2 VPG_GENERIC0_FRAME_UPDATE 0 0 VPG_GENERIC1_FRAME_UPDATE 1 1 VPG_GENERIC2_FRAME_UPDATE 2 2 VPG_GENERIC3_FRAME_UPDATE 3 3 VPG_GENERIC4_FRAME_UPDATE 4 4 VPG_GENERIC5_FRAME_UPDATE 5 5 VPG_GENERIC6_FRAME_UPDATE 6 6 VPG_GENERIC7_FRAME_UPDATE 7 7 VPG_GENERIC8_FRAME_UPDATE 8 8 VPG_GENERIC9_FRAME_UPDATE 9 9 VPG_GENERIC10_FRAME_UPDATE 10 10 VPG_GENERIC11_FRAME_UPDATE 11 11 VPG_GENERIC12_FRAME_UPDATE 12 12 VPG_GENERIC13_FRAME_UPDATE 13 13 VPG_GENERIC14_FRAME_UPDATE 14 14 VPG_GENERIC0_FRAME_UPDATE_PENDING 16 16 VPG_GENERIC1_FRAME_UPDATE_PENDING 17 17 VPG_GENERIC2_FRAME_UPDATE_PENDING 18 18 VPG_GENERIC3_FRAME_UPDATE_PENDING 19 19 VPG_GENERIC4_FRAME_UPDATE_PENDING 20 20 VPG_GENERIC5_FRAME_UPDATE_PENDING 21 21 VPG_GENERIC6_FRAME_UPDATE_PENDING 22 22 VPG_GENERIC7_FRAME_UPDATE_PENDING 23 23 VPG_GENERIC8_FRAME_UPDATE_PENDING 24 24 VPG_GENERIC9_FRAME_UPDATE_PENDING 25 25 VPG_GENERIC10_FRAME_UPDATE_PENDING 26 26 VPG_GENERIC11_FRAME_UPDATE_PENDING 27 27 VPG_GENERIC12_FRAME_UPDATE_PENDING 28 28 VPG_GENERIC13_FRAME_UPDATE_PENDING 29 29 VPG_GENERIC14_FRAME_UPDATE_PENDING 30 30 regVPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL 0 0x38d0 30 0 2 VPG_GENERIC0_IMMEDIATE_UPDATE 0 0 VPG_GENERIC1_IMMEDIATE_UPDATE 1 1 VPG_GENERIC2_IMMEDIATE_UPDATE 2 2 VPG_GENERIC3_IMMEDIATE_UPDATE 3 3 VPG_GENERIC4_IMMEDIATE_UPDATE 4 4 VPG_GENERIC5_IMMEDIATE_UPDATE 5 5 VPG_GENERIC6_IMMEDIATE_UPDATE 6 6 VPG_GENERIC7_IMMEDIATE_UPDATE 7 7 VPG_GENERIC8_IMMEDIATE_UPDATE 8 8 VPG_GENERIC9_IMMEDIATE_UPDATE 9 9 VPG_GENERIC10_IMMEDIATE_UPDATE 10 10 VPG_GENERIC11_IMMEDIATE_UPDATE 11 11 VPG_GENERIC12_IMMEDIATE_UPDATE 12 12 VPG_GENERIC13_IMMEDIATE_UPDATE 13 13 VPG_GENERIC14_IMMEDIATE_UPDATE 14 14 VPG_GENERIC0_IMMEDIATE_UPDATE_PENDING 16 16 VPG_GENERIC1_IMMEDIATE_UPDATE_PENDING 17 17 VPG_GENERIC2_IMMEDIATE_UPDATE_PENDING 18 18 VPG_GENERIC3_IMMEDIATE_UPDATE_PENDING 19 19 VPG_GENERIC4_IMMEDIATE_UPDATE_PENDING 20 20 VPG_GENERIC5_IMMEDIATE_UPDATE_PENDING 21 21 VPG_GENERIC6_IMMEDIATE_UPDATE_PENDING 22 22 VPG_GENERIC7_IMMEDIATE_UPDATE_PENDING 23 23 VPG_GENERIC8_IMMEDIATE_UPDATE_PENDING 24 24 VPG_GENERIC9_IMMEDIATE_UPDATE_PENDING 25 25 VPG_GENERIC10_IMMEDIATE_UPDATE_PENDING 26 26 VPG_GENERIC11_IMMEDIATE_UPDATE_PENDING 27 27 VPG_GENERIC12_IMMEDIATE_UPDATE_PENDING 28 28 VPG_GENERIC13_IMMEDIATE_UPDATE_PENDING 29 29 VPG_GENERIC14_IMMEDIATE_UPDATE_PENDING 30 30 regVPG9_VPG_GENERIC_STATUS 0 0x38d1 3 0 2 VPG_GENERIC_LOCK_STATUS 0 0 VPG_GENERIC_CONFLICT_OCCURED 1 1 VPG_GENERIC_CONFLICT_CLR 4 4 regVPG9_VPG_MEM_PWR 0 0x38d2 3 0 2 VPG_GSP_MEM_LIGHT_SLEEP_DIS 0 0 VPG_GSP_LIGHT_SLEEP_FORCE 4 4 VPG_GSP_MEM_PWR_STATE 8 8 regVPG9_VPG_ISRC1_2_ACCESS_CTRL 0 0x38d3 1 0 2 VPG_ISRC1_2_DATA_INDEX 0 3 regVPG9_VPG_ISRC1_2_DATA 0 0x38d4 4 0 2 VPG_ISRC_DATA_BYTE0 0 7 VPG_ISRC_DATA_BYTE1 8 15 VPG_ISRC_DATA_BYTE2 16 23 VPG_ISRC_DATA_BYTE3 24 31 regVPG9_VPG_MPEG_INFO0 0 0x38d5 4 0 2 VPG_MPEG_INFO_CHECKSUM 0 7 VPG_MPEG_INFO_MB0 8 15 VPG_MPEG_INFO_MB1 16 23 VPG_MPEG_INFO_MB2 24 31 regVPG9_VPG_MPEG_INFO1 0 0x38d6 4 0 2 VPG_MPEG_INFO_MB3 0 7 VPG_MPEG_INFO_MF 8 9 VPG_MPEG_INFO_FR 12 12 VPG_MPEG_INFO_UPDATE 16 16 regDP_SYM32_ENC3_DP_SYM32_ENC_CONTROL 0 0x38d9 3 0 2 DP_SYM32_ENC_ENABLE 0 0 DP_SYM32_ENC_RESET 4 4 DP_SYM32_ENC_RESET_DONE 8 8 regDP_SYM32_ENC3_DP_SYM32_ENC_VID_FIFO_CONTROL 0 0x38da 4 0 2 PIXEL_TO_SYMBOL_FIFO_ENABLE 0 0 PIXEL_TO_SYMBOL_FIFO_RESET 4 4 PIXEL_TO_SYMBOL_FIFO_RESET_DONE 8 8 PIXEL_TO_SYMBOL_FIFO_OVERFLOW_STATUS 12 12 regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL 0 0x38db 2 0 2 MSA_DOUBLE_BUFFER_ENABLE 0 0 MSA_DOUBLE_BUFFER_PENDING 4 4 regDP_SYM32_ENC3_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL 0 0x38dc 2 0 2 PIXEL_FORMAT_DOUBLE_BUFFER_ENABLE 0 0 PIXEL_FORMAT_DOUBLE_BUFFER_PENDING 4 4 regDP_SYM32_ENC3_DP_SYM32_ENC_VID_PIXEL_FORMAT 0 0x38dd 3 0 2 PIXEL_ENCODING_TYPE 0 0 UNCOMPRESSED_PIXEL_ENCODING 4 5 UNCOMPRESSED_COMPONENT_DEPTH 8 9 regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA0 0 0x38de 1 0 2 MSA_DATA 0 31 regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA1 0 0x38df 1 0 2 MSA_DATA 0 31 regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA2 0 0x38e0 1 0 2 MSA_DATA 0 31 regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA3 0 0x38e1 1 0 2 MSA_DATA 0 31 regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA4 0 0x38e2 1 0 2 MSA_DATA 0 31 regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA5 0 0x38e3 1 0 2 MSA_DATA 0 31 regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA6 0 0x38e4 1 0 2 MSA_DATA 0 31 regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA7 0 0x38e5 1 0 2 MSA_DATA 0 31 regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA8 0 0x38e6 1 0 2 MSA_DATA 0 31 regDP_SYM32_ENC3_DP_SYM32_ENC_HBLANK_CONTROL 0 0x38e7 1 0 2 HBLANK_MINIMUM_SYMBOL_WIDTH 0 15 regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL0 0 0x38e8 11 0 2 GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE 0 0 GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE 1 1 GSP_TRIGGER_ONE_SHOT_SEND 2 2 GSP_TRIGGER_ONE_SHOT_POSITION 3 3 GSP_DOUBLE_BUFFER_ENABLE 4 4 GSP_PAYLOAD_SIZE 5 6 GSP_SOF_REFERENCE 7 7 GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED 8 8 GSP_TRIGGER_TRANSMISSION_PENDING 9 9 GSP_DOUBLE_BUFFER_PENDING 10 10 GSP_TRANSMISSION_LINE_NUMBER 16 31 regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL1 0 0x38e9 11 0 2 GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE 0 0 GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE 1 1 GSP_TRIGGER_ONE_SHOT_SEND 2 2 GSP_TRIGGER_ONE_SHOT_POSITION 3 3 GSP_DOUBLE_BUFFER_ENABLE 4 4 GSP_PAYLOAD_SIZE 5 6 GSP_SOF_REFERENCE 7 7 GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED 8 8 GSP_TRIGGER_TRANSMISSION_PENDING 9 9 GSP_DOUBLE_BUFFER_PENDING 10 10 GSP_TRANSMISSION_LINE_NUMBER 16 31 regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL2 0 0x38ea 11 0 2 GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE 0 0 GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE 1 1 GSP_TRIGGER_ONE_SHOT_SEND 2 2 GSP_TRIGGER_ONE_SHOT_POSITION 3 3 GSP_DOUBLE_BUFFER_ENABLE 4 4 GSP_PAYLOAD_SIZE 5 6 GSP_SOF_REFERENCE 7 7 GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED 8 8 GSP_TRIGGER_TRANSMISSION_PENDING 9 9 GSP_DOUBLE_BUFFER_PENDING 10 10 GSP_TRANSMISSION_LINE_NUMBER 16 31 regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL3 0 0x38eb 11 0 2 GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE 0 0 GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE 1 1 GSP_TRIGGER_ONE_SHOT_SEND 2 2 GSP_TRIGGER_ONE_SHOT_POSITION 3 3 GSP_DOUBLE_BUFFER_ENABLE 4 4 GSP_PAYLOAD_SIZE 5 6 GSP_SOF_REFERENCE 7 7 GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED 8 8 GSP_TRIGGER_TRANSMISSION_PENDING 9 9 GSP_DOUBLE_BUFFER_PENDING 10 10 GSP_TRANSMISSION_LINE_NUMBER 16 31 regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL4 0 0x38ec 11 0 2 GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE 0 0 GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE 1 1 GSP_TRIGGER_ONE_SHOT_SEND 2 2 GSP_TRIGGER_ONE_SHOT_POSITION 3 3 GSP_DOUBLE_BUFFER_ENABLE 4 4 GSP_PAYLOAD_SIZE 5 6 GSP_SOF_REFERENCE 7 7 GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED 8 8 GSP_TRIGGER_TRANSMISSION_PENDING 9 9 GSP_DOUBLE_BUFFER_PENDING 10 10 GSP_TRANSMISSION_LINE_NUMBER 16 31 regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL5 0 0x38ed 11 0 2 GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE 0 0 GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE 1 1 GSP_TRIGGER_ONE_SHOT_SEND 2 2 GSP_TRIGGER_ONE_SHOT_POSITION 3 3 GSP_DOUBLE_BUFFER_ENABLE 4 4 GSP_PAYLOAD_SIZE 5 6 GSP_SOF_REFERENCE 7 7 GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED 8 8 GSP_TRIGGER_TRANSMISSION_PENDING 9 9 GSP_DOUBLE_BUFFER_PENDING 10 10 GSP_TRANSMISSION_LINE_NUMBER 16 31 regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL6 0 0x38ee 11 0 2 GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE 0 0 GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE 1 1 GSP_TRIGGER_ONE_SHOT_SEND 2 2 GSP_TRIGGER_ONE_SHOT_POSITION 3 3 GSP_DOUBLE_BUFFER_ENABLE 4 4 GSP_PAYLOAD_SIZE 5 6 GSP_SOF_REFERENCE 7 7 GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED 8 8 GSP_TRIGGER_TRANSMISSION_PENDING 9 9 GSP_DOUBLE_BUFFER_PENDING 10 10 GSP_TRANSMISSION_LINE_NUMBER 16 31 regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL7 0 0x38ef 11 0 2 GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE 0 0 GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE 1 1 GSP_TRIGGER_ONE_SHOT_SEND 2 2 GSP_TRIGGER_ONE_SHOT_POSITION 3 3 GSP_DOUBLE_BUFFER_ENABLE 4 4 GSP_PAYLOAD_SIZE 5 6 GSP_SOF_REFERENCE 7 7 GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED 8 8 GSP_TRIGGER_TRANSMISSION_PENDING 9 9 GSP_DOUBLE_BUFFER_PENDING 10 10 GSP_TRANSMISSION_LINE_NUMBER 16 31 regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL8 0 0x38f0 11 0 2 GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE 0 0 GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE 1 1 GSP_TRIGGER_ONE_SHOT_SEND 2 2 GSP_TRIGGER_ONE_SHOT_POSITION 3 3 GSP_DOUBLE_BUFFER_ENABLE 4 4 GSP_PAYLOAD_SIZE 5 6 GSP_SOF_REFERENCE 7 7 GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED 8 8 GSP_TRIGGER_TRANSMISSION_PENDING 9 9 GSP_DOUBLE_BUFFER_PENDING 10 10 GSP_TRANSMISSION_LINE_NUMBER 16 31 regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL9 0 0x38f1 11 0 2 GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE 0 0 GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE 1 1 GSP_TRIGGER_ONE_SHOT_SEND 2 2 GSP_TRIGGER_ONE_SHOT_POSITION 3 3 GSP_DOUBLE_BUFFER_ENABLE 4 4 GSP_PAYLOAD_SIZE 5 6 GSP_SOF_REFERENCE 7 7 GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED 8 8 GSP_TRIGGER_TRANSMISSION_PENDING 9 9 GSP_DOUBLE_BUFFER_PENDING 10 10 GSP_TRANSMISSION_LINE_NUMBER 16 31 regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL10 0 0x38f2 11 0 2 GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE 0 0 GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE 1 1 GSP_TRIGGER_ONE_SHOT_SEND 2 2 GSP_TRIGGER_ONE_SHOT_POSITION 3 3 GSP_DOUBLE_BUFFER_ENABLE 4 4 GSP_PAYLOAD_SIZE 5 6 GSP_SOF_REFERENCE 7 7 GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED 8 8 GSP_TRIGGER_TRANSMISSION_PENDING 9 9 GSP_DOUBLE_BUFFER_PENDING 10 10 GSP_TRANSMISSION_LINE_NUMBER 16 31 regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL11 0 0x38f3 11 0 2 GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE 0 0 GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE 1 1 GSP_TRIGGER_ONE_SHOT_SEND 2 2 GSP_TRIGGER_ONE_SHOT_POSITION 3 3 GSP_DOUBLE_BUFFER_ENABLE 4 4 GSP_PAYLOAD_SIZE 5 6 GSP_SOF_REFERENCE 7 7 GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED 8 8 GSP_TRIGGER_TRANSMISSION_PENDING 9 9 GSP_DOUBLE_BUFFER_PENDING 10 10 GSP_TRANSMISSION_LINE_NUMBER 16 31 regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL12 0 0x38f4 11 0 2 GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE 0 0 GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE 1 1 GSP_TRIGGER_ONE_SHOT_SEND 2 2 GSP_TRIGGER_ONE_SHOT_POSITION 3 3 GSP_DOUBLE_BUFFER_ENABLE 4 4 GSP_PAYLOAD_SIZE 5 6 GSP_SOF_REFERENCE 7 7 GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED 8 8 GSP_TRIGGER_TRANSMISSION_PENDING 9 9 GSP_DOUBLE_BUFFER_PENDING 10 10 GSP_TRANSMISSION_LINE_NUMBER 16 31 regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL13 0 0x38f5 11 0 2 GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE 0 0 GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE 1 1 GSP_TRIGGER_ONE_SHOT_SEND 2 2 GSP_TRIGGER_ONE_SHOT_POSITION 3 3 GSP_DOUBLE_BUFFER_ENABLE 4 4 GSP_PAYLOAD_SIZE 5 6 GSP_SOF_REFERENCE 7 7 GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED 8 8 GSP_TRIGGER_TRANSMISSION_PENDING 9 9 GSP_DOUBLE_BUFFER_PENDING 10 10 GSP_TRANSMISSION_LINE_NUMBER 16 31 regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL14 0 0x38f6 11 0 2 GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE 0 0 GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE 1 1 GSP_TRIGGER_ONE_SHOT_SEND 2 2 GSP_TRIGGER_ONE_SHOT_POSITION 3 3 GSP_DOUBLE_BUFFER_ENABLE 4 4 GSP_PAYLOAD_SIZE 5 6 GSP_SOF_REFERENCE 7 7 GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED 8 8 GSP_TRIGGER_TRANSMISSION_PENDING 9 9 GSP_DOUBLE_BUFFER_PENDING 10 10 GSP_TRANSMISSION_LINE_NUMBER 16 31 regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_CONTROL 0 0x38f7 3 0 2 SDP_STREAM_ENABLE 0 0 GSP0_PRIORITY 4 4 SDP_CRC16_ENABLE 8 8 regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_AUDIO_CONTROL0 0 0x38f8 9 0 2 ASP_ENABLE 0 0 ATP_ENABLE 1 1 AIP_ENABLE 2 2 ACM_ENABLE 3 3 ISRC_ENABLE 4 4 ASP_PRIORITY 5 5 ATP_VERSION_NUMBER 8 13 AUDIO_MUTE 28 28 AUDIO_MUTE_STATUS 29 29 regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_AUDIO_CONTROL1 0 0x38f9 4 0 2 ASP_CONCATENATION_ENABLE 0 0 ASP_CONCATENATION_2_CHANNEL_LAYOUT_MAX_SAMPLE_COUNT 4 9 ASP_CONCATENATION_8_CHANNEL_LAYOUT_MAX_SAMPLE_COUNT 12 17 ASP_CONCATENATION_HBR_LAYOUT_MAX_SAMPLE_COUNT 20 25 regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL 0 0x38fa 5 0 2 METADATA_PACKET_ENABLE 0 0 METADATA_DOUBLE_BUFFER_ENABLE 4 4 METADATA_PACKET_SOF_REFERENCE 8 8 METADATA_PACKET_DOUBLE_BUFFER_PENDING 12 12 METADATA_PACKET_TRANSMISSION_LINE_NUMBER 16 31 regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA_CONTROL 0 0x38ff 2 0 2 MSA_MISC1_STEREOSYNC_OVERRIDE_EN 0 0 MSA_TRANSMISSION_LINE_NUMBER 16 31 regDP_SYM32_ENC3_DP_SYM32_ENC_VID_VBID_CONTROL 0 0x3900 2 0 2 VBID_6_COMPRESSEDSTREAM_FLAG_SOF_REFERENCE 0 0 VBID_6_COMPRESSEDSTREAM_FLAG_LINE_NUMBER 16 31 regDP_SYM32_ENC3_DP_SYM32_ENC_VID_STREAM_CONTROL 0 0x3901 3 0 2 VID_STREAM_ENABLE 0 0 VID_STREAM_DISABLE_DEFER 4 5 VID_STREAM_STATUS 8 8 regDP_SYM32_ENC3_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL 0 0x3902 2 0 2 PANEL_REPLAY_TUNNELING_OPTIMIZATION_ENABLE 0 0 PANEL_REPLAY_TUNNELING_OPTIMIZATION_DOUBLE_BUFFER_ENABLE 4 4 regDP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_CONTROL 0 0x3903 2 0 2 CRC_ENABLE 0 0 CRC_CONT_MODE_ENABLE 4 4 regDP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_RESULT0 0 0x3904 2 0 2 CRC_RESULT0 0 15 CRC_RESULT1 16 31 regDP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_RESULT1 0 0x3905 2 0 2 CRC_RESULT2 0 15 CRC_RESULT3 16 31 regDP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_STATUS 0 0x3906 1 0 2 CRC_VALID 0 0 regDP_SYM32_ENC3_DP_SYM32_ENC_MEM_POWER_CONTROL 0 0x3907 4 0 2 MEM_DEFAULT_LOW_POWER_STATE 0 1 MEM_PWR_FORCE 4 5 MEM_PWR_DIS 8 8 MEM_PWR_STATE 12 13 regDP_SYM32_ENC3_DP_SYM32_ENC_SPARE 0 0x3908 1 0 2 DP_SYM32_ENC_SPARE 0 31 regDP_LINK_ENC0_DP_LINK_ENC_CLOCK_CONTROL 0 0x3697 2 0 2 DP_LINK_ENC_CLOCK_EN 0 0 DP_LINK_ENC_CLOCK_ON_SYMCLK32 4 4 regDP_LINK_ENC0_DP_LINK_ENC_SPARE 0 0x3698 1 0 2 DP_LINK_ENC_SPARE 0 31 regDP_DPHY_SYM320_DP_DPHY_SYM32_CONTROL 0 0x36c0 5 0 2 DPHY_ENABLE 0 0 DPHY_RESET 1 1 PRECODER_ENABLE 2 2 MODE 4 5 NUM_LANES 8 9 regDP_DPHY_SYM320_DP_DPHY_SYM32_STATUS 0 0x36c1 6 0 2 STATUS 0 0 RESET_STATUS 1 1 CURRENT_MODE 4 5 ENCRYPTION_ENABLED 8 8 RATE_UPDATE_PENDING 12 12 SAT_UPDATE_PENDING 16 17 regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_UPDATE 0 0x36c4 1 0 2 SAT_UPDATE 0 1 regDP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL0 0 0x36c5 2 0 2 STREAM_VC_RATE_Y 0 24 STREAM_VC_RATE_X 25 31 regDP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL1 0 0x36c6 2 0 2 STREAM_VC_RATE_Y 0 24 STREAM_VC_RATE_X 25 31 regDP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL2 0 0x36c7 2 0 2 STREAM_VC_RATE_Y 0 24 STREAM_VC_RATE_X 25 31 regDP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL3 0 0x36c8 2 0 2 STREAM_VC_RATE_Y 0 24 STREAM_VC_RATE_X 25 31 regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC0 0 0x36cb 4 0 2 SAT_STREAM_SOURCE 0 2 SAT_ENCRYPTION_ENABLE 4 4 SAT_ENCRYPTION_TYPE 5 5 SAT_SLOT_COUNT 8 14 regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC1 0 0x36cc 4 0 2 SAT_STREAM_SOURCE 0 2 SAT_ENCRYPTION_ENABLE 4 4 SAT_ENCRYPTION_TYPE 5 5 SAT_SLOT_COUNT 8 14 regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC2 0 0x36cd 4 0 2 SAT_STREAM_SOURCE 0 2 SAT_ENCRYPTION_ENABLE 4 4 SAT_ENCRYPTION_TYPE 5 5 SAT_SLOT_COUNT 8 14 regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC3 0 0x36ce 4 0 2 SAT_STREAM_SOURCE 0 2 SAT_ENCRYPTION_ENABLE 4 4 SAT_ENCRYPTION_TYPE 5 5 SAT_SLOT_COUNT 8 14 regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS0 0 0x36d1 4 0 2 SAT_STREAM_SOURCE 0 2 SAT_ENCRYPTION_ENABLE 4 4 SAT_ENCRYPTION_TYPE 5 5 SAT_SLOT_COUNT 8 14 regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS1 0 0x36d2 4 0 2 SAT_STREAM_SOURCE 0 2 SAT_ENCRYPTION_ENABLE 4 4 SAT_ENCRYPTION_TYPE 5 5 SAT_SLOT_COUNT 8 14 regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS2 0 0x36d3 4 0 2 SAT_STREAM_SOURCE 0 2 SAT_ENCRYPTION_ENABLE 4 4 SAT_ENCRYPTION_TYPE 5 5 SAT_SLOT_COUNT 8 14 regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS3 0 0x36d4 4 0 2 SAT_STREAM_SOURCE 0 2 SAT_ENCRYPTION_ENABLE 4 4 SAT_ENCRYPTION_TYPE 5 5 SAT_SLOT_COUNT 8 14 regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CONFIG 0 0x36d7 8 0 2 TP_SELECT0 0 2 TP_PRBS_SEL0 4 6 TP_SELECT1 8 10 TP_PRBS_SEL1 12 14 TP_SELECT2 16 18 TP_PRBS_SEL2 20 22 TP_SELECT3 24 26 TP_PRBS_SEL3 28 30 regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_PRBS_SEED0 0 0x36d8 1 0 2 TP_PRBS_SEED 0 30 regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_PRBS_SEED1 0 0x36d9 1 0 2 TP_PRBS_SEED 0 30 regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_PRBS_SEED2 0 0x36da 1 0 2 TP_PRBS_SEED 0 30 regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_PRBS_SEED3 0 0x36db 1 0 2 TP_PRBS_SEED 0 30 regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_SQ_PULSE 0 0x36dc 1 0 2 TP_SQ_PULSE_WIDTH 0 7 regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM0 0 0x36dd 1 0 2 TP_CUSTOM 0 23 regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM1 0 0x36de 1 0 2 TP_CUSTOM 0 23 regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM2 0 0x36df 1 0 2 TP_CUSTOM 0 23 regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM3 0 0x36e0 1 0 2 TP_CUSTOM 0 23 regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM4 0 0x36e1 1 0 2 TP_CUSTOM 0 23 regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM5 0 0x36e2 1 0 2 TP_CUSTOM 0 23 regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM6 0 0x36e3 1 0 2 TP_CUSTOM 0 23 regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM7 0 0x36e4 1 0 2 TP_CUSTOM 0 23 regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM8 0 0x36e5 1 0 2 TP_CUSTOM 0 23 regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM9 0 0x36e6 1 0 2 TP_CUSTOM 0 23 regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM10 0 0x36e7 1 0 2 TP_CUSTOM 0 23 regDP_DPHY_SYM320_DP_DPHY_SYM32_ERROR_STATUS 0 0x36e8 9 0 2 TOTAL_SLOT_COUNT_ERROR 0 0 RATE_ERROR 1 1 VC_SAME_STREAM_SOURCE 2 2 NO_ACT_ERROR 3 3 UNEXPECT_MODE_TRANSITION 4 4 ILLEGAL_STREAM_SYMBOL 5 5 RATE_COUNTER_SATURATION 6 6 COUNTER_OVERFLOW 7 7 CIPHER_ERROR 8 8 regDP_DPHY_SYM320_DP_DPHY_SYM32_SYMBOL_OVERRIDE 0 0x36ea 12 0 2 STREAM0_OVR_ENABLE 0 1 STREAM0_OVR_TYPE 2 2 STREAM0_OVR_SYMBOL 4 7 STREAM1_OVR_ENABLE 8 9 STREAM1_OVR_TYPE 10 10 STREAM1_OVR_SYMBOL 12 15 STREAM2_OVR_ENABLE 16 17 STREAM2_OVR_TYPE 18 18 STREAM2_OVR_SYMBOL 20 23 STREAM3_OVR_ENABLE 24 25 STREAM3_OVR_TYPE 26 26 STREAM3_OVR_SYMBOL 28 31 regDP_DPHY_SYM320_DP_DPHY_SYM32_CRC_CONFIG0 0 0x36eb 9 0 2 CRC_ENABLE 0 0 CRC_RESET 1 1 CRC_LANE_SOURCE 4 5 CRC_TAP_SOURCE 6 7 CRC_SCHEDULER_SOURCE 8 13 CRC_IGNORE_VCPF 16 16 CRC_START_EVENT 17 19 CRC_USE_NUM_SYMBOLS 20 20 CRC_END_EVENT 21 22 regDP_DPHY_SYM320_DP_DPHY_SYM32_CRC_CONFIG1 0 0x36ec 1 0 2 CRC_NUM_SYMBOLS 0 31 regDP_DPHY_SYM320_DP_DPHY_SYM32_CRC_STATUS 0 0x36ed 2 0 2 CRC_DONE 0 0 CRC_VALUE 8 23 regDP_DPHY_SYM320_DP_DPHY_SYM32_CRC_COUNT 0 0x36ee 1 0 2 CRC_SYMBOL_COUNT 0 31 regDP_LINK_ENC1_DP_LINK_ENC_CLOCK_CONTROL 0 0x376b 2 0 2 DP_LINK_ENC_CLOCK_EN 0 0 DP_LINK_ENC_CLOCK_ON_SYMCLK32 4 4 regDP_LINK_ENC1_DP_LINK_ENC_SPARE 0 0x376c 1 0 2 DP_LINK_ENC_SPARE 0 31 regDP_DPHY_SYM321_DP_DPHY_SYM32_CONTROL 0 0x3794 5 0 2 DPHY_ENABLE 0 0 DPHY_RESET 1 1 PRECODER_ENABLE 2 2 MODE 4 5 NUM_LANES 8 9 regDP_DPHY_SYM321_DP_DPHY_SYM32_STATUS 0 0x3795 6 0 2 STATUS 0 0 RESET_STATUS 1 1 CURRENT_MODE 4 5 ENCRYPTION_ENABLED 8 8 RATE_UPDATE_PENDING 12 12 SAT_UPDATE_PENDING 16 17 regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_UPDATE 0 0x3798 1 0 2 SAT_UPDATE 0 1 regDP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL0 0 0x3799 2 0 2 STREAM_VC_RATE_Y 0 24 STREAM_VC_RATE_X 25 31 regDP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL1 0 0x379a 2 0 2 STREAM_VC_RATE_Y 0 24 STREAM_VC_RATE_X 25 31 regDP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL2 0 0x379b 2 0 2 STREAM_VC_RATE_Y 0 24 STREAM_VC_RATE_X 25 31 regDP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL3 0 0x379c 2 0 2 STREAM_VC_RATE_Y 0 24 STREAM_VC_RATE_X 25 31 regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC0 0 0x379f 4 0 2 SAT_STREAM_SOURCE 0 2 SAT_ENCRYPTION_ENABLE 4 4 SAT_ENCRYPTION_TYPE 5 5 SAT_SLOT_COUNT 8 14 regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC1 0 0x37a0 4 0 2 SAT_STREAM_SOURCE 0 2 SAT_ENCRYPTION_ENABLE 4 4 SAT_ENCRYPTION_TYPE 5 5 SAT_SLOT_COUNT 8 14 regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC2 0 0x37a1 4 0 2 SAT_STREAM_SOURCE 0 2 SAT_ENCRYPTION_ENABLE 4 4 SAT_ENCRYPTION_TYPE 5 5 SAT_SLOT_COUNT 8 14 regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC3 0 0x37a2 4 0 2 SAT_STREAM_SOURCE 0 2 SAT_ENCRYPTION_ENABLE 4 4 SAT_ENCRYPTION_TYPE 5 5 SAT_SLOT_COUNT 8 14 regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS0 0 0x37a5 4 0 2 SAT_STREAM_SOURCE 0 2 SAT_ENCRYPTION_ENABLE 4 4 SAT_ENCRYPTION_TYPE 5 5 SAT_SLOT_COUNT 8 14 regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS1 0 0x37a6 4 0 2 SAT_STREAM_SOURCE 0 2 SAT_ENCRYPTION_ENABLE 4 4 SAT_ENCRYPTION_TYPE 5 5 SAT_SLOT_COUNT 8 14 regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS2 0 0x37a7 4 0 2 SAT_STREAM_SOURCE 0 2 SAT_ENCRYPTION_ENABLE 4 4 SAT_ENCRYPTION_TYPE 5 5 SAT_SLOT_COUNT 8 14 regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS3 0 0x37a8 4 0 2 SAT_STREAM_SOURCE 0 2 SAT_ENCRYPTION_ENABLE 4 4 SAT_ENCRYPTION_TYPE 5 5 SAT_SLOT_COUNT 8 14 regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CONFIG 0 0x37ab 8 0 2 TP_SELECT0 0 2 TP_PRBS_SEL0 4 6 TP_SELECT1 8 10 TP_PRBS_SEL1 12 14 TP_SELECT2 16 18 TP_PRBS_SEL2 20 22 TP_SELECT3 24 26 TP_PRBS_SEL3 28 30 regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_PRBS_SEED0 0 0x37ac 1 0 2 TP_PRBS_SEED 0 30 regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_PRBS_SEED1 0 0x37ad 1 0 2 TP_PRBS_SEED 0 30 regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_PRBS_SEED2 0 0x37ae 1 0 2 TP_PRBS_SEED 0 30 regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_PRBS_SEED3 0 0x37af 1 0 2 TP_PRBS_SEED 0 30 regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_SQ_PULSE 0 0x37b0 1 0 2 TP_SQ_PULSE_WIDTH 0 7 regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM0 0 0x37b1 1 0 2 TP_CUSTOM 0 23 regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM1 0 0x37b2 1 0 2 TP_CUSTOM 0 23 regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM2 0 0x37b3 1 0 2 TP_CUSTOM 0 23 regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM3 0 0x37b4 1 0 2 TP_CUSTOM 0 23 regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM4 0 0x37b5 1 0 2 TP_CUSTOM 0 23 regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM5 0 0x37b6 1 0 2 TP_CUSTOM 0 23 regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM6 0 0x37b7 1 0 2 TP_CUSTOM 0 23 regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM7 0 0x37b8 1 0 2 TP_CUSTOM 0 23 regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM8 0 0x37b9 1 0 2 TP_CUSTOM 0 23 regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM9 0 0x37ba 1 0 2 TP_CUSTOM 0 23 regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM10 0 0x37bb 1 0 2 TP_CUSTOM 0 23 regDP_DPHY_SYM321_DP_DPHY_SYM32_ERROR_STATUS 0 0x37bc 9 0 2 TOTAL_SLOT_COUNT_ERROR 0 0 RATE_ERROR 1 1 VC_SAME_STREAM_SOURCE 2 2 NO_ACT_ERROR 3 3 UNEXPECT_MODE_TRANSITION 4 4 ILLEGAL_STREAM_SYMBOL 5 5 RATE_COUNTER_SATURATION 6 6 COUNTER_OVERFLOW 7 7 CIPHER_ERROR 8 8 regDP_DPHY_SYM321_DP_DPHY_SYM32_SYMBOL_OVERRIDE 0 0x37be 12 0 2 STREAM0_OVR_ENABLE 0 1 STREAM0_OVR_TYPE 2 2 STREAM0_OVR_SYMBOL 4 7 STREAM1_OVR_ENABLE 8 9 STREAM1_OVR_TYPE 10 10 STREAM1_OVR_SYMBOL 12 15 STREAM2_OVR_ENABLE 16 17 STREAM2_OVR_TYPE 18 18 STREAM2_OVR_SYMBOL 20 23 STREAM3_OVR_ENABLE 24 25 STREAM3_OVR_TYPE 26 26 STREAM3_OVR_SYMBOL 28 31 regDP_DPHY_SYM321_DP_DPHY_SYM32_CRC_CONFIG0 0 0x37bf 9 0 2 CRC_ENABLE 0 0 CRC_RESET 1 1 CRC_LANE_SOURCE 4 5 CRC_TAP_SOURCE 6 7 CRC_SCHEDULER_SOURCE 8 13 CRC_IGNORE_VCPF 16 16 CRC_START_EVENT 17 19 CRC_USE_NUM_SYMBOLS 20 20 CRC_END_EVENT 21 22 regDP_DPHY_SYM321_DP_DPHY_SYM32_CRC_CONFIG1 0 0x37c0 1 0 2 CRC_NUM_SYMBOLS 0 31 regDP_DPHY_SYM321_DP_DPHY_SYM32_CRC_STATUS 0 0x37c1 2 0 2 CRC_DONE 0 0 CRC_VALUE 8 23 regDP_DPHY_SYM321_DP_DPHY_SYM32_CRC_COUNT 0 0x37c2 1 0 2 CRC_SYMBOL_COUNT 0 31 regDCHVM_CTRL0 0 0x3603 1 0 2 HOSTVM_INIT_REQ 0 0 regDCHVM_CTRL1 0 0x3604 1 0 2 DUMMY1 0 31 regDCHVM_CLK_CTRL 0 0x3605 6 0 2 HVM_DISPCLK_R_GATE_DIS 0 0 HVM_DISPCLK_G_GATE_DIS 1 1 HVM_DCFCLK_R_GATE_DIS 4 4 HVM_DCFCLK_G_GATE_DIS 5 5 TR_REQ_REQCLKREQ_MODE 8 9 TW_RSP_COMPCLKREQ_MODE 10 11 regDCHVM_MEM_CTRL 0 0x3606 3 0 2 HVM_GPUVMRET_PWR_REQ_DIS 0 0 HVM_GPUVMRET_FORCE_REQ 2 3 HVM_GPUVMRET_POWER_STATUS 4 5 regDCHVM_RIOMMU_CTRL0 0 0x3607 2 0 2 HOSTVM_PREFETCH_REQ 0 0 HOSTVM_POWERSTATUS 1 1 regDCHVM_RIOMMU_STAT0 0 0x3608 2 0 2 RIOMMU_ACTIVE 0 0 HOSTVM_PREFETCH_DONE 1 1 regCORB_WRITE_POINTER 0 0x4b7012 1 0 3 CORB_WRITE_POINTER 0 7 regCORB_READ_POINTER 0 0x4b7012 2 0 3 CORB_READ_POINTER 0 7 CORB_READ_POINTER_RESET 15 15 regCORB_CONTROL 0 0x4b7013 2 0 3 CORB_MEMORY_ERROR_INTERRUPT_ENABLE 0 0 ENABLE_CORB_DMA_ENGINE 1 1 regCORB_STATUS 0 0x4b7013 1 0 3 CORB_MEMORY_ERROR_INDICATION 0 0 regCORB_SIZE 0 0x4b7013 2 0 3 CORB_SIZE 0 1 CORB_SIZE_CAPABILITY 4 7 regRIRB_LOWER_BASE_ADDRESS 0 0x4b7014 2 0 3 RIRB_LOWER_BASE_UNIMPLEMENTED_BITS 0 6 RIRB_LOWER_BASE_ADDRESS 7 31 regRIRB_UPPER_BASE_ADDRESS 0 0x4b7015 1 0 3 RIRB_UPPER_BASE_ADDRESS 0 31 regRIRB_WRITE_POINTER 0 0x4b7016 2 0 3 RIRB_WRITE_POINTER 0 7 RIRB_WRITE_POINTER_RESET 15 15 regRESPONSE_INTERRUPT_COUNT 0 0x4b7016 1 0 3 N_RESPONSE_INTERRUPT_COUNT 0 7 regRIRB_CONTROL 0 0x4b7017 1 0 3 RIRB_DMA_ENABLE 1 1 regRIRB_STATUS 0 0x4b7017 1 0 3 RESPONSE_INTERRUPT 0 0 regRIRB_SIZE 0 0x4b7017 2 0 3 RIRB_SIZE 0 1 RIRB_SIZE_CAPABILITY 4 7 regIMMEDIATE_COMMAND_OUTPUT_INTERFACE 0 0x4b7018 2 0 3 IMMEDIATE_COMMAND_WRITE_VERB_AND_PAYLOAD 0 27 IMMEDIATE_COMMAND_WRITE_CODEC_ADDRESS 28 31 regIMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA 0 0x4b7018 1 0 3 IMMEDIATE_COMMAND_WRITE 0 31 regIMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX 0 0x4b7018 1 0 3 IMMEDIATE_COMMAND_WRITE 0 15 regIMMEDIATE_RESPONSE_INPUT_INTERFACE 0 0x4b7019 1 0 3 IMMEDIATE_RESPONSE_READ 0 31 regIMMEDIATE_COMMAND_STATUS 0 0x4b701a 2 0 3 IMMEDIATE_COMMAND_BUSY 0 0 IMMEDIATE_RESULT_VALID 1 1 regDMA_POSITION_LOWER_BASE_ADDRESS 0 0x4b701c 3 0 3 DMA_POSITION_BUFFER_ENABLE 0 0 DMA_POSITION_LOWER_BASE_UNIMPLEMENTED_BITS 1 6 DMA_POSITION_LOWER_BASE_ADDRESS 7 31 regDMA_POSITION_UPPER_BASE_ADDRESS 0 0x4b701d 1 0 3 DMA_POSITION_UPPER_BASE_ADDRESS 0 31 regAZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA 0 0x4b7018 1 0 3 IMMEDIATE_COMMAND_WRITE 0 31 regAZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX 0 0x4b7018 1 0 3 IMMEDIATE_COMMAND_WRITE 0 16 regAZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_DATA 0 0x4b7018 1 0 3 IMMEDIATE_COMMAND_WRITE 0 31 regAZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_INDEX 0 0x4b7018 1 0 3 IMMEDIATE_COMMAND_WRITE 0 16 regAZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA 0 0x4b7018 1 0 3 IMMEDIATE_COMMAND_WRITE 0 31 regAZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX 0 0x4b7018 1 0 3 IMMEDIATE_COMMAND_WRITE 0 16 regAZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS 0 0x4b7020 11 0 3 STREAM_RESET 0 0 STREAM_RUN 1 1 INTERRUPT_ON_COMPLETION_ENABLE 2 2 FIFO_ERROR_INTERRUPT_ENABLE 3 3 DESCRIPTOR_ERROR_INTERRUPT_ENABLE 4 4 STRIPE_CONTROL 16 17 TRAFFIC_PRIORITY 18 18 STREAM_NUMBER 20 23 FIFO_ERROR 27 27 DESCRIPTOR_ERROR 28 28 FIFO_READY 29 29 regAZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER 0 0x4b7021 1 0 3 LINK_POSITION_IN_BUFFER 0 31 regAZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH 0 0x4b7022 1 0 3 CYCLIC_BUFFER_LENGTH 0 31 regAZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX 0 0x4b7023 1 0 3 LAST_VALID_INDEX 0 7 regAZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE 0 0x4b7024 1 0 3 FIFO_SIZE 0 15 regAZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_FORMAT 0 0x4b7024 5 0 3 NUMBER_OF_CHANNELS 0 3 BITS_PER_SAMPLE 4 6 SAMPLE_BASE_DIVISOR 8 10 SAMPLE_BASE_MULTIPLE 11 13 SAMPLE_BASE_RATE 14 14 regAZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS 0 0x4b7026 2 0 3 BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_UNIMPLEMENTED_BITS 0 6 BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS 7 31 regAZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS 0 0x4b7027 1 0 3 BUFFER_DESCRIPTOR_LIST_UPPER_BASE_ADDRESS 0 31 regAZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS 0 0x4b7821 1 0 3 LINK_POSITION_IN_BUFFER_ALIAS 0 31 regAZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS 0 0x4b7028 11 0 3 STREAM_RESET 0 0 STREAM_RUN 1 1 INTERRUPT_ON_COMPLETION_ENABLE 2 2 FIFO_ERROR_INTERRUPT_ENABLE 3 3 DESCRIPTOR_ERROR_INTERRUPT_ENABLE 4 4 STRIPE_CONTROL 16 17 TRAFFIC_PRIORITY 18 18 STREAM_NUMBER 20 23 FIFO_ERROR 27 27 DESCRIPTOR_ERROR 28 28 FIFO_READY 29 29 regAZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER 0 0x4b7029 1 0 3 LINK_POSITION_IN_BUFFER 0 31 regAZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH 0 0x4b702a 1 0 3 CYCLIC_BUFFER_LENGTH 0 31 regAZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX 0 0x4b702b 1 0 3 LAST_VALID_INDEX 0 7 regAZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE 0 0x4b702c 1 0 3 FIFO_SIZE 0 15 regAZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_FORMAT 0 0x4b702c 5 0 3 NUMBER_OF_CHANNELS 0 3 BITS_PER_SAMPLE 4 6 SAMPLE_BASE_DIVISOR 8 10 SAMPLE_BASE_MULTIPLE 11 13 SAMPLE_BASE_RATE 14 14 regAZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS 0 0x4b702e 2 0 3 BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_UNIMPLEMENTED_BITS 0 6 BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS 7 31 regAZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS 0 0x4b702f 1 0 3 BUFFER_DESCRIPTOR_LIST_UPPER_BASE_ADDRESS 0 31 regAZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS 0 0x4b7829 1 0 3 LINK_POSITION_IN_BUFFER_ALIAS 0 31 regAZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS 0 0x4b7030 11 0 3 STREAM_RESET 0 0 STREAM_RUN 1 1 INTERRUPT_ON_COMPLETION_ENABLE 2 2 FIFO_ERROR_INTERRUPT_ENABLE 3 3 DESCRIPTOR_ERROR_INTERRUPT_ENABLE 4 4 STRIPE_CONTROL 16 17 TRAFFIC_PRIORITY 18 18 STREAM_NUMBER 20 23 FIFO_ERROR 27 27 DESCRIPTOR_ERROR 28 28 FIFO_READY 29 29 regAZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER 0 0x4b7031 1 0 3 LINK_POSITION_IN_BUFFER 0 31 regAZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH 0 0x4b7032 1 0 3 CYCLIC_BUFFER_LENGTH 0 31 regAZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX 0 0x4b7033 1 0 3 LAST_VALID_INDEX 0 7 regAZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE 0 0x4b7034 1 0 3 FIFO_SIZE 0 15 regAZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_FORMAT 0 0x4b7034 5 0 3 NUMBER_OF_CHANNELS 0 3 BITS_PER_SAMPLE 4 6 SAMPLE_BASE_DIVISOR 8 10 SAMPLE_BASE_MULTIPLE 11 13 SAMPLE_BASE_RATE 14 14 regAZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS 0 0x4b7036 2 0 3 BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_UNIMPLEMENTED_BITS 0 6 BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS 7 31 regAZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS 0 0x4b7037 1 0 3 BUFFER_DESCRIPTOR_LIST_UPPER_BASE_ADDRESS 0 31 regAZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS 0 0x4b7831 1 0 3 LINK_POSITION_IN_BUFFER_ALIAS 0 31 regAZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS 0 0x4b7038 11 0 3 STREAM_RESET 0 0 STREAM_RUN 1 1 INTERRUPT_ON_COMPLETION_ENABLE 2 2 FIFO_ERROR_INTERRUPT_ENABLE 3 3 DESCRIPTOR_ERROR_INTERRUPT_ENABLE 4 4 STRIPE_CONTROL 16 17 TRAFFIC_PRIORITY 18 18 STREAM_NUMBER 20 23 FIFO_ERROR 27 27 DESCRIPTOR_ERROR 28 28 FIFO_READY 29 29 regAZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER 0 0x4b7039 1 0 3 LINK_POSITION_IN_BUFFER 0 31 regAZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH 0 0x4b703a 1 0 3 CYCLIC_BUFFER_LENGTH 0 31 regAZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX 0 0x4b703b 1 0 3 LAST_VALID_INDEX 0 7 regAZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE 0 0x4b703c 1 0 3 FIFO_SIZE 0 15 regAZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_FORMAT 0 0x4b703c 5 0 3 NUMBER_OF_CHANNELS 0 3 BITS_PER_SAMPLE 4 6 SAMPLE_BASE_DIVISOR 8 10 SAMPLE_BASE_MULTIPLE 11 13 SAMPLE_BASE_RATE 14 14 regAZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS 0 0x4b703e 2 0 3 BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_UNIMPLEMENTED_BITS 0 6 BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS 7 31 regAZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS 0 0x4b703f 1 0 3 BUFFER_DESCRIPTOR_LIST_UPPER_BASE_ADDRESS 0 31 regAZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS 0 0x4b7839 1 0 3 LINK_POSITION_IN_BUFFER_ALIAS 0 31 regAZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS 0 0x4b7040 11 0 3 STREAM_RESET 0 0 STREAM_RUN 1 1 INTERRUPT_ON_COMPLETION_ENABLE 2 2 FIFO_ERROR_INTERRUPT_ENABLE 3 3 DESCRIPTOR_ERROR_INTERRUPT_ENABLE 4 4 STRIPE_CONTROL 16 17 TRAFFIC_PRIORITY 18 18 STREAM_NUMBER 20 23 FIFO_ERROR 27 27 DESCRIPTOR_ERROR 28 28 FIFO_READY 29 29 regAZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER 0 0x4b7041 1 0 3 LINK_POSITION_IN_BUFFER 0 31 regAZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH 0 0x4b7042 1 0 3 CYCLIC_BUFFER_LENGTH 0 31 regAZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX 0 0x4b7043 1 0 3 LAST_VALID_INDEX 0 7 regAZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE 0 0x4b7044 1 0 3 FIFO_SIZE 0 15 regAZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_FORMAT 0 0x4b7044 5 0 3 NUMBER_OF_CHANNELS 0 3 BITS_PER_SAMPLE 4 6 SAMPLE_BASE_DIVISOR 8 10 SAMPLE_BASE_MULTIPLE 11 13 SAMPLE_BASE_RATE 14 14 regAZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS 0 0x4b7046 2 0 3 BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_UNIMPLEMENTED_BITS 0 6 BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS 7 31 regAZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS 0 0x4b7047 1 0 3 BUFFER_DESCRIPTOR_LIST_UPPER_BASE_ADDRESS 0 31 regAZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS 0 0x4b7841 1 0 3 LINK_POSITION_IN_BUFFER_ALIAS 0 31 regAZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS 0 0x4b7048 11 0 3 STREAM_RESET 0 0 STREAM_RUN 1 1 INTERRUPT_ON_COMPLETION_ENABLE 2 2 FIFO_ERROR_INTERRUPT_ENABLE 3 3 DESCRIPTOR_ERROR_INTERRUPT_ENABLE 4 4 STRIPE_CONTROL 16 17 TRAFFIC_PRIORITY 18 18 STREAM_NUMBER 20 23 FIFO_ERROR 27 27 DESCRIPTOR_ERROR 28 28 FIFO_READY 29 29 regAZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER 0 0x4b7049 1 0 3 LINK_POSITION_IN_BUFFER 0 31 regAZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH 0 0x4b704a 1 0 3 CYCLIC_BUFFER_LENGTH 0 31 regAZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX 0 0x4b704b 1 0 3 LAST_VALID_INDEX 0 7 regAZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE 0 0x4b704c 1 0 3 FIFO_SIZE 0 15 regAZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_FORMAT 0 0x4b704c 5 0 3 NUMBER_OF_CHANNELS 0 3 BITS_PER_SAMPLE 4 6 SAMPLE_BASE_DIVISOR 8 10 SAMPLE_BASE_MULTIPLE 11 13 SAMPLE_BASE_RATE 14 14 regAZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS 0 0x4b704e 2 0 3 BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_UNIMPLEMENTED_BITS 0 6 BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS 7 31 regAZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS 0 0x4b704f 1 0 3 BUFFER_DESCRIPTOR_LIST_UPPER_BASE_ADDRESS 0 31 regAZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS 0 0x4b7849 1 0 3 LINK_POSITION_IN_BUFFER_ALIAS 0 31 regAZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS 0 0x4b7050 11 0 3 STREAM_RESET 0 0 STREAM_RUN 1 1 INTERRUPT_ON_COMPLETION_ENABLE 2 2 FIFO_ERROR_INTERRUPT_ENABLE 3 3 DESCRIPTOR_ERROR_INTERRUPT_ENABLE 4 4 STRIPE_CONTROL 16 17 TRAFFIC_PRIORITY 18 18 STREAM_NUMBER 20 23 FIFO_ERROR 27 27 DESCRIPTOR_ERROR 28 28 FIFO_READY 29 29 regAZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER 0 0x4b7051 1 0 3 LINK_POSITION_IN_BUFFER 0 31 regAZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH 0 0x4b7052 1 0 3 CYCLIC_BUFFER_LENGTH 0 31 regAZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX 0 0x4b7053 1 0 3 LAST_VALID_INDEX 0 7 regAZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE 0 0x4b7054 1 0 3 FIFO_SIZE 0 15 regAZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_FORMAT 0 0x4b7054 5 0 3 NUMBER_OF_CHANNELS 0 3 BITS_PER_SAMPLE 4 6 SAMPLE_BASE_DIVISOR 8 10 SAMPLE_BASE_MULTIPLE 11 13 SAMPLE_BASE_RATE 14 14 regAZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS 0 0x4b7056 2 0 3 BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_UNIMPLEMENTED_BITS 0 6 BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS 7 31 regAZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS 0 0x4b7057 1 0 3 BUFFER_DESCRIPTOR_LIST_UPPER_BASE_ADDRESS 0 31 regAZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS 0 0x4b7851 1 0 3 LINK_POSITION_IN_BUFFER_ALIAS 0 31 regAZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS 0 0x4b7058 11 0 3 STREAM_RESET 0 0 STREAM_RUN 1 1 INTERRUPT_ON_COMPLETION_ENABLE 2 2 FIFO_ERROR_INTERRUPT_ENABLE 3 3 DESCRIPTOR_ERROR_INTERRUPT_ENABLE 4 4 STRIPE_CONTROL 16 17 TRAFFIC_PRIORITY 18 18 STREAM_NUMBER 20 23 FIFO_ERROR 27 27 DESCRIPTOR_ERROR 28 28 FIFO_READY 29 29 regAZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER 0 0x4b7059 1 0 3 LINK_POSITION_IN_BUFFER 0 31 regAZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH 0 0x4b705a 1 0 3 CYCLIC_BUFFER_LENGTH 0 31 regAZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX 0 0x4b705b 1 0 3 LAST_VALID_INDEX 0 7 regAZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE 0 0x4b705c 1 0 3 FIFO_SIZE 0 15 regAZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_FORMAT 0 0x4b705c 5 0 3 NUMBER_OF_CHANNELS 0 3 BITS_PER_SAMPLE 4 6 SAMPLE_BASE_DIVISOR 8 10 SAMPLE_BASE_MULTIPLE 11 13 SAMPLE_BASE_RATE 14 14 regAZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS 0 0x4b705e 2 0 3 BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_UNIMPLEMENTED_BITS 0 6 BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS 7 31 regAZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS 0 0x4b705f 1 0 3 BUFFER_DESCRIPTOR_LIST_UPPER_BASE_ADDRESS 0 31 regAZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS 0 0x4b7859 1 0 3 LINK_POSITION_IN_BUFFER_ALIAS 0 31 ixSEQ00 2 0x0 2 0 4294967295 SEQ_RST0B 0 0 SEQ_RST1B 1 1 ixSEQ01 2 0x1 5 0 4294967295 SEQ_DOT8 0 0 SEQ_SHIFT2 2 2 SEQ_PCLKBY2 3 3 SEQ_SHIFT4 4 4 SEQ_MAXBW 5 5 ixSEQ02 2 0x2 4 0 4294967295 SEQ_MAP0_EN 0 0 SEQ_MAP1_EN 1 1 SEQ_MAP2_EN 2 2 SEQ_MAP3_EN 3 3 ixSEQ03 2 0x3 6 0 4294967295 SEQ_FONT_B1 0 0 SEQ_FONT_B2 1 1 SEQ_FONT_A1 2 2 SEQ_FONT_A2 3 3 SEQ_FONT_B0 4 4 SEQ_FONT_A0 5 5 ixSEQ04 2 0x4 3 0 4294967295 SEQ_256K 1 1 SEQ_ODDEVEN 2 2 SEQ_CHAIN 3 3 ixCRT00 2 0x0 1 0 4294967295 H_TOTAL 0 7 ixCRT01 2 0x1 1 0 4294967295 H_DISP_END 0 7 ixCRT02 2 0x2 1 0 4294967295 H_BLANK_START 0 7 ixCRT03 2 0x3 3 0 4294967295 H_BLANK_END 0 4 H_DE_SKEW 5 6 CR10CR11_R_DIS_B 7 7 ixCRT04 2 0x4 1 0 4294967295 H_SYNC_START 0 7 ixCRT05 2 0x5 3 0 4294967295 H_SYNC_END 0 4 H_SYNC_SKEW 5 6 H_BLANK_END_B5 7 7 ixCRT06 2 0x6 1 0 4294967295 V_TOTAL 0 7 ixCRT07 2 0x7 8 0 4294967295 V_TOTAL_B8 0 0 V_DISP_END_B8 1 1 V_SYNC_START_B8 2 2 V_BLANK_START_B8 3 3 LINE_CMP_B8 4 4 V_TOTAL_B9 5 5 V_DISP_END_B9 6 6 V_SYNC_START_B9 7 7 ixCRT08 2 0x8 2 0 4294967295 ROW_SCAN_START 0 4 BYTE_PAN 5 6 ixCRT09 2 0x9 4 0 4294967295 MAX_ROW_SCAN 0 4 V_BLANK_START_B9 5 5 LINE_CMP_B9 6 6 DOUBLE_CHAR_HEIGHT 7 7 ixCRT0A 2 0xa 2 0 4294967295 CURSOR_START 0 4 CURSOR_DISABLE 5 5 ixCRT0B 2 0xb 2 0 4294967295 CURSOR_END 0 4 CURSOR_SKEW 5 6 ixCRT0C 2 0xc 1 0 4294967295 DISP_START 0 7 ixCRT0D 2 0xd 1 0 4294967295 DISP_START 0 7 ixCRT0E 2 0xe 1 0 4294967295 CURSOR_LOC_HI 0 7 ixCRT0F 2 0xf 1 0 4294967295 CURSOR_LOC_LO 0 7 ixCRT10 2 0x10 1 0 4294967295 V_SYNC_START 0 7 ixCRT11 2 0x11 5 0 4294967295 V_SYNC_END 0 3 V_INTR_CLR 4 4 V_INTR_EN 5 5 SEL5_REFRESH_CYC 6 6 C0T7_WR_ONLY 7 7 ixCRT12 2 0x12 1 0 4294967295 V_DISP_END 0 7 ixCRT13 2 0x13 1 0 4294967295 DISP_PITCH 0 7 ixCRT14 2 0x14 3 0 4294967295 UNDRLN_LOC 0 4 ADDR_CNT_BY4 5 5 DOUBLE_WORD 6 6 ixCRT15 2 0x15 1 0 4294967295 V_BLANK_START 0 7 ixCRT16 2 0x16 1 0 4294967295 V_BLANK_END 0 7 ixCRT17 2 0x17 7 0 4294967295 RA0_AS_A13B 0 0 RA1_AS_A14B 1 1 VCOUNT_BY2 2 2 ADDR_CNT_BY2 3 3 WRAP_A15TOA0 5 5 BYTE_MODE 6 6 CRTC_SYNC_EN 7 7 ixCRT18 2 0x18 1 0 4294967295 LINE_CMP 0 7 ixCRT1E 2 0x1e 1 0 4294967295 GRPH_DEC_RD1 1 1 ixCRT1F 2 0x1f 1 0 4294967295 GRPH_DEC_RD0 0 7 ixCRT22 2 0x22 1 0 4294967295 GRPH_LATCH_DATA 0 7 ixGRA00 2 0x0 4 0 4294967295 GRPH_SET_RESET0 0 0 GRPH_SET_RESET1 1 1 GRPH_SET_RESET2 2 2 GRPH_SET_RESET3 3 3 ixGRA01 2 0x1 4 0 4294967295 GRPH_SET_RESET_ENA0 0 0 GRPH_SET_RESET_ENA1 1 1 GRPH_SET_RESET_ENA2 2 2 GRPH_SET_RESET_ENA3 3 3 ixGRA02 2 0x2 1 0 4294967295 GRPH_CCOMP 0 3 ixGRA03 2 0x3 2 0 4294967295 GRPH_ROTATE 0 2 GRPH_FN_SEL 3 4 ixGRA04 2 0x4 1 0 4294967295 GRPH_RMAP 0 1 ixGRA05 2 0x5 5 0 4294967295 GRPH_WRITE_MODE 0 1 GRPH_READ1 3 3 CGA_ODDEVEN 4 4 GRPH_OES 5 5 GRPH_PACK 6 6 ixGRA06 2 0x6 3 0 4294967295 GRPH_GRAPHICS 0 0 GRPH_ODDEVEN 1 1 GRPH_ADRSEL 2 3 ixGRA07 2 0x7 4 0 4294967295 GRPH_XCARE0 0 0 GRPH_XCARE1 1 1 GRPH_XCARE2 2 2 GRPH_XCARE3 3 3 ixGRA08 2 0x8 1 0 4294967295 GRPH_BMSK 0 7 ixATTR00 2 0x0 1 0 4294967295 ATTR_PAL 0 5 ixATTR01 2 0x1 1 0 4294967295 ATTR_PAL 0 5 ixATTR02 2 0x2 1 0 4294967295 ATTR_PAL 0 5 ixATTR03 2 0x3 1 0 4294967295 ATTR_PAL 0 5 ixATTR04 2 0x4 1 0 4294967295 ATTR_PAL 0 5 ixATTR05 2 0x5 1 0 4294967295 ATTR_PAL 0 5 ixATTR06 2 0x6 1 0 4294967295 ATTR_PAL 0 5 ixATTR07 2 0x7 1 0 4294967295 ATTR_PAL 0 5 ixATTR08 2 0x8 1 0 4294967295 ATTR_PAL 0 5 ixATTR09 2 0x9 1 0 4294967295 ATTR_PAL 0 5 ixATTR0A 2 0xa 1 0 4294967295 ATTR_PAL 0 5 ixATTR0B 2 0xb 1 0 4294967295 ATTR_PAL 0 5 ixATTR0C 2 0xc 1 0 4294967295 ATTR_PAL 0 5 ixATTR0D 2 0xd 1 0 4294967295 ATTR_PAL 0 5 ixATTR0E 2 0xe 1 0 4294967295 ATTR_PAL 0 5 ixATTR0F 2 0xf 1 0 4294967295 ATTR_PAL 0 5 ixATTR10 2 0x10 7 0 4294967295 ATTR_GRPH_MODE 0 0 ATTR_MONO_EN 1 1 ATTR_LGRPH_EN 2 2 ATTR_BLINK_EN 3 3 ATTR_PANTOPONLY 5 5 ATTR_PCLKBY2 6 6 ATTR_CSEL_EN 7 7 ixATTR11 2 0x11 1 0 4294967295 ATTR_OVSC 0 7 ixATTR12 2 0x12 2 0 4294967295 ATTR_MAP_EN 0 3 ATTR_VSMUX 4 5 ixATTR13 2 0x13 1 0 4294967295 ATTR_PPAN 0 3 ixATTR14 2 0x14 2 0 4294967295 ATTR_CSEL1 0 1 ATTR_CSEL2 2 3 ixAZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT 2 0x2200 7 0 4294967295 NUMBER_OF_CHANNELS 0 3 BITS_PER_SAMPLE 4 6 SAMPLE_BASE_DIVISOR 8 10 SAMPLE_BASE_MULTIPLE 11 13 SAMPLE_BASE_RATE 14 14 STREAM_TYPE 15 15 STREAM_TYPE_R 15 15 ixAZALIA_F2_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID 2 0x2706 2 0 4294967295 CHANNEL_ID 0 3 STREAM_ID 4 7 ixAZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER 2 0x270d 10 0 4294967295 DIGEN 0 0 V 1 1 VCFG 2 2 PRE 3 3 COPY 4 4 NON_AUDIO 5 5 PRO 6 6 L 7 7 CC 8 14 KEEPALIVE 23 23 ixAZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_2 2 0x270e 1 0 4294967295 CC 0 6 ixAZALIA_F2_CODEC_CONVERTER_STRIPE_CONTROL 2 0x2724 2 0 4294967295 STRIPE_CONTROL 0 1 STRIPE_CAPABILITY 20 22 ixAZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3 2 0x273e 1 0 4294967295 KEEPALIVE 7 7 ixAZALIA_F2_CODEC_CONVERTER_CONTROL_RAMP_RATE 2 0x2770 1 0 4294967295 RAMP_RATE 0 7 ixAZALIA_F2_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING 2 0x2771 3 0 4294967295 PRESENTATION_TIME_EMBEDDING_ENABLE 0 0 PRESENTATION_TIME_OFFSET_CHANGED 1 1 PRESENTATION_TIME_EMBEDDING_GROUP 4 6 ixAZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 2 0x2f09 14 0 4294967295 AUDIO_CHANNEL_CAPABILITIES 0 0 INPUT_AMPLIFIER_PRESENT 1 1 OUTPUT_AMPLIFIER_PRESENT 2 2 AMPLIFIER_PARAMETER_OVERRIDE 3 3 FORMAT_OVERRIDE 4 4 STRIPE 5 5 PROCESSING_WIDGET 6 6 UNSOLICITED_RESPONSE_CAPABILITY 7 7 CONNECTION_LIST 8 8 DIGITAL 9 9 POWER_CONTROL 10 10 LR_SWAP 11 11 AUDIO_WIDGET_CAPABILITIES_DELAY 16 19 TYPE 20 23 ixAZALIA_F2_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 2 0x2f0a 2 0 4294967295 AUDIO_RATE_CAPABILITIES 0 11 AUDIO_BIT_CAPABILITIES 16 20 ixAZALIA_F2_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS 2 0x2f0b 1 0 4294967295 STREAM_FORMATS 0 31 ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONNECTION_LIST_ENTRY 2 0x3702 1 0 4294967295 CONNECTION_LIST_ENTRY 0 31 ixAZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL 2 0x3707 1 0 4294967295 OUT_ENABLE 6 6 ixAZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE 2 0x3708 2 0 4294967295 TAG 0 5 ENABLE 7 7 ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE 2 0x3709 2 0 4294967295 IMPEDANCE_SENSE 0 30 PRESENCE_DETECT 31 31 ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 2 0x371c 8 0 4294967295 SEQUENCE 0 3 DEFAULT_ASSOCIATION 4 7 MISC 8 11 COLOR 12 15 CONNECTION_TYPE 16 19 DEFAULT_DEVICE 20 23 LOCATION 24 29 PORT_CONNECTIVITY 30 31 ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2 2 0x371d 2 0 4294967295 MISC 0 3 COLOR 4 7 ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3 2 0x371e 2 0 4294967295 CONNECTION_TYPE 0 3 DEFAULT_DEVICE 4 7 ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4 2 0x371f 2 0 4294967295 LOCATION 0 5 PORT_CONNECTIVITY 6 7 ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION 2 0x3770 4 0 4294967295 SPEAKER_ALLOCATION 0 6 HDMI_CONNECTION 8 8 DP_CONNECTION 9 9 EXTRA_CONNECTION_INFO 10 15 ixAZALIA_F2_CODEC_PIN_CONTROL_CHANNEL_ALLOCATION 2 0x3771 1 0 4294967295 CHANNEL_ALLOCATION 0 7 ixAZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO 2 0x3772 3 0 4294967295 LFE_PLAYBACK_LEVEL 0 1 LEVEL_SHIFT 3 6 DOWN_MIX_INHIBIT 7 7 ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR 2 0x3776 5 0 4294967295 MAX_CHANNELS 0 2 FORMAT_CODE 3 6 SUPPORTED_FREQUENCIES 8 15 DESCRIPTOR_BYTE_2 16 23 SUPPORTED_FREQUENCIES_STEREO 24 31 ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_DATA 2 0x3776 1 0 4294967295 DESCRIPTOR 0 31 ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE 2 0x3777 3 0 4294967295 MULTICHANNEL01_ENABLE 0 0 MULTICHANNEL01_MUTE 1 1 MULTICHANNEL01_CHANNEL_ID 4 7 ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE 2 0x3778 3 0 4294967295 MULTICHANNEL23_ENABLE 0 0 MULTICHANNEL23_MUTE 1 1 MULTICHANNEL23_CHANNEL_ID 4 7 ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE 2 0x3779 3 0 4294967295 MULTICHANNEL45_ENABLE 0 0 MULTICHANNEL45_MUTE 1 1 MULTICHANNEL45_CHANNEL_ID 4 7 ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE 2 0x377a 3 0 4294967295 MULTICHANNEL67_ENABLE 0 0 MULTICHANNEL67_MUTE 1 1 MULTICHANNEL67_CHANNEL_ID 4 7 ixAZALIA_F2_CODEC_PIN_CONTROL_LIPSYNC 2 0x377b 2 0 4294967295 VIDEO_LIPSYNC 0 7 AUDIO_LIPSYNC 8 15 ixAZALIA_F2_CODEC_PIN_CONTROL_HBR 2 0x377c 2 0 4294967295 HBR_CAPABLE 0 0 HBR_ENABLE 4 4 ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_INDEX 2 0x3780 1 0 4294967295 SINK_INFO_INDEX 0 7 ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_DATA 2 0x3781 1 0 4294967295 SINK_DATA 0 31 ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE 2 0x3785 3 0 4294967295 MULTICHANNEL1_ENABLE 0 0 MULTICHANNEL1_MUTE 1 1 MULTICHANNEL1_CHANNEL_ID 4 7 ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE 2 0x3786 3 0 4294967295 MULTICHANNEL3_ENABLE 0 0 MULTICHANNEL3_MUTE 1 1 MULTICHANNEL3_CHANNEL_ID 4 7 ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE 2 0x3787 3 0 4294967295 MULTICHANNEL5_ENABLE 0 0 MULTICHANNEL5_MUTE 1 1 MULTICHANNEL5_CHANNEL_ID 4 7 ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE 2 0x3788 3 0 4294967295 MULTICHANNEL7_ENABLE 0 0 MULTICHANNEL7_MUTE 1 1 MULTICHANNEL7_CHANNEL_ID 4 7 ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE 2 0x3789 1 0 4294967295 MULTICHANNEL_MODE 0 0 ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_0 2 0x378a 2 0 4294967295 IEC_60958_CS_MODE 0 1 IEC_60958_CS_SOURCE_NUMBER 2 5 ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1 2 0x378b 4 0 4294967295 IEC_60958_CS_CLOCK_ACCURACY 0 1 IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN 2 2 IEC_60958_CS_WORD_LENGTH 3 6 IEC_60958_CS_WORD_LENGTH_OVRRD_EN 7 7 ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_2 2 0x378c 2 0 4294967295 IEC_60958_CS_SAMPLING_FREQUENCY 0 5 IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN 6 6 ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_3 2 0x378d 2 0 4294967295 IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY 0 3 IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN 4 4 ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4 2 0x378e 4 0 4294967295 IEC_60958_CS_SAMPLING_FREQUENCY_COEFF 0 3 IEC_60958_CS_MPEG_SURROUND_INFO 4 4 IEC_60958_CS_CGMS_A 5 6 IEC_60958_CS_CGMS_A_VALID 7 7 ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_5 2 0x378f 2 0 4294967295 IEC_60958_CS_CHANNEL_NUMBER_L 0 3 IEC_60958_CS_CHANNEL_NUMBER_R 4 7 ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_6 2 0x3790 2 0 4294967295 IEC_60958_CS_CHANNEL_NUMBER_2 0 3 IEC_60958_CS_CHANNEL_NUMBER_3 4 7 ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_7 2 0x3791 2 0 4294967295 IEC_60958_CS_CHANNEL_NUMBER_4 0 3 IEC_60958_CS_CHANNEL_NUMBER_5 4 7 ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_8 2 0x3792 2 0 4294967295 IEC_60958_CS_CHANNEL_NUMBER_6 0 3 IEC_60958_CS_CHANNEL_NUMBER_7 4 7 ixAZALIA_F2_CODEC_PIN_ASSOCIATION_INFO 2 0x3793 1 0 4294967295 ASSOCIATION_INFO 0 31 ixAZALIA_F2_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS 2 0x3797 1 0 4294967295 OUTPUT_ACTIVE 0 0 ixAZALIA_F2_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 2 0x3798 2 0 4294967295 LPIB_SNAPSHOT_LOCK 0 0 CYCLIC_BUFFER_WRAP_COUNT 8 15 ixAZALIA_F2_CODEC_PIN_CONTROL_LPIB 2 0x3799 1 0 4294967295 LPIB 0 31 ixAZALIA_F2_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 2 0x379a 1 0 4294967295 LPIB_TIMER_SNAPSHOT 0 31 ixAZALIA_F2_CODEC_PIN_CONTROL_CODING_TYPE 2 0x379b 1 0 4294967295 CODING_TYPE 0 7 ixAZALIA_F2_CODEC_PIN_CONTROL_FORMAT_CHANGED 2 0x379c 4 0 4294967295 FORMAT_CHANGED 0 0 FORMAT_CHANGED_ACK_UR_ENABLE 1 1 FORMAT_CHANGE_REASON 8 15 FORMAT_CHANGE_RESPONSE 16 23 ixAZALIA_F2_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION 2 0x379d 1 0 4294967295 WIRELESS_DISPLAY_IDENTIFICATION 0 1 ixAZALIA_F2_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE 2 0x379e 2 0 4294967295 REMOTE_KEEP_ALIVE_ENABLE 0 0 REMOTE_KEEP_ALIVE_CAPABILITY 4 4 ixAZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 2 0x3f09 13 0 4294967295 AUDIO_CHANNEL_CAPABILITIES 0 0 INPUT_AMPLIFIER_PRESENT 1 1 OUTPUT_AMPLIFIER_PRESENT 2 2 AMPLIFIER_PARAMETER_OVERRIDE 3 3 STRIPE 5 5 PROCESSING_WIDGET 6 6 UNSOLICITED_RESPONSE_CAPABILITY 7 7 CONNECTION_LIST 8 8 DIGITAL 9 9 POWER_CONTROL 10 10 LR_SWAP 11 11 AUDIO_WIDGET_CAPABILITIES_DELAY 16 19 TYPE 20 23 ixAZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES 2 0x3f0c 11 0 4294967295 IMPEDANCE_SENSE_CAPABLE 0 0 TRIGGER_REQUIRED 1 1 JACK_DETECTION_CAPABILITY 2 2 HEADPHONE_DRIVE_CAPABLE 3 3 OUTPUT_CAPABLE 4 4 INPUT_CAPABLE 5 5 BALANCED_I_O_PINS 6 6 HDMI 7 7 VREF_CONTROL 8 15 EAPD_CAPABLE 16 16 DP 24 24 ixAZALIA_F2_CODEC_PIN_PARAMETER_CONNECTION_LIST_LENGTH 2 0x3f0e 1 0 4294967295 CONNECTION_LIST_LENGTH 0 31 ixAUDIO_DESCRIPTOR0 2 0x1 4 0 4294967295 MAX_CHANNELS 0 2 SUPPORTED_FREQUENCIES 8 15 DESCRIPTOR_BYTE_2 16 23 SUPPORTED_FREQUENCIES_STEREO 24 31 ixAUDIO_DESCRIPTOR1 2 0x2 4 0 4294967295 MAX_CHANNELS 0 2 SUPPORTED_FREQUENCIES 8 15 DESCRIPTOR_BYTE_2 16 23 SUPPORTED_FREQUENCIES_STEREO 24 31 ixAUDIO_DESCRIPTOR2 2 0x3 4 0 4294967295 MAX_CHANNELS 0 2 SUPPORTED_FREQUENCIES 8 15 DESCRIPTOR_BYTE_2 16 23 SUPPORTED_FREQUENCIES_STEREO 24 31 ixAUDIO_DESCRIPTOR3 2 0x4 4 0 4294967295 MAX_CHANNELS 0 2 SUPPORTED_FREQUENCIES 8 15 DESCRIPTOR_BYTE_2 16 23 SUPPORTED_FREQUENCIES_STEREO 24 31 ixAUDIO_DESCRIPTOR4 2 0x5 4 0 4294967295 MAX_CHANNELS 0 2 SUPPORTED_FREQUENCIES 8 15 DESCRIPTOR_BYTE_2 16 23 SUPPORTED_FREQUENCIES_STEREO 24 31 ixAUDIO_DESCRIPTOR5 2 0x6 4 0 4294967295 MAX_CHANNELS 0 2 SUPPORTED_FREQUENCIES 8 15 DESCRIPTOR_BYTE_2 16 23 SUPPORTED_FREQUENCIES_STEREO 24 31 ixAUDIO_DESCRIPTOR6 2 0x7 4 0 4294967295 MAX_CHANNELS 0 2 SUPPORTED_FREQUENCIES 8 15 DESCRIPTOR_BYTE_2 16 23 SUPPORTED_FREQUENCIES_STEREO 24 31 ixAUDIO_DESCRIPTOR7 2 0x8 4 0 4294967295 MAX_CHANNELS 0 2 SUPPORTED_FREQUENCIES 8 15 DESCRIPTOR_BYTE_2 16 23 SUPPORTED_FREQUENCIES_STEREO 24 31 ixAUDIO_DESCRIPTOR8 2 0x9 4 0 4294967295 MAX_CHANNELS 0 2 SUPPORTED_FREQUENCIES 8 15 DESCRIPTOR_BYTE_2 16 23 SUPPORTED_FREQUENCIES_STEREO 24 31 ixAUDIO_DESCRIPTOR9 2 0xa 4 0 4294967295 MAX_CHANNELS 0 2 SUPPORTED_FREQUENCIES 8 15 DESCRIPTOR_BYTE_2 16 23 SUPPORTED_FREQUENCIES_STEREO 24 31 ixAUDIO_DESCRIPTOR10 2 0xb 4 0 4294967295 MAX_CHANNELS 0 2 SUPPORTED_FREQUENCIES 8 15 DESCRIPTOR_BYTE_2 16 23 SUPPORTED_FREQUENCIES_STEREO 24 31 ixAUDIO_DESCRIPTOR11 2 0xc 4 0 4294967295 MAX_CHANNELS 0 2 SUPPORTED_FREQUENCIES 8 15 DESCRIPTOR_BYTE_2 16 23 SUPPORTED_FREQUENCIES_STEREO 24 31 ixAUDIO_DESCRIPTOR12 2 0xd 4 0 4294967295 MAX_CHANNELS 0 2 SUPPORTED_FREQUENCIES 8 15 DESCRIPTOR_BYTE_2 16 23 SUPPORTED_FREQUENCIES_STEREO 24 31 ixAUDIO_DESCRIPTOR13 2 0xe 4 0 4294967295 MAX_CHANNELS 0 2 SUPPORTED_FREQUENCIES 8 15 DESCRIPTOR_BYTE_2 16 23 SUPPORTED_FREQUENCIES_STEREO 24 31 ixAZALIA_F2_CODEC_PIN_CONTROL_MANUFACTURER_ID 2 0x0 1 0 4294967295 MANUFACTURER_ID 0 15 ixAZALIA_F2_CODEC_PIN_CONTROL_PRODUCT_ID 2 0x1 1 0 4294967295 PRODUCT_ID 0 15 ixAZALIA_F2_CODEC_PIN_CONTROL_SINK_DESCRIPTION_LEN 2 0x2 1 0 4294967295 SINK_DESCRIPTION_LEN 0 7 ixAZALIA_F2_CODEC_PIN_CONTROL_PORTID0 2 0x3 1 0 4294967295 PORTID 0 31 ixAZALIA_F2_CODEC_PIN_CONTROL_PORTID1 2 0x4 1 0 4294967295 PORTID 0 31 ixSINK_DESCRIPTION0 2 0x5 1 0 4294967295 DESCRIPTION 0 7 ixSINK_DESCRIPTION1 2 0x6 1 0 4294967295 DESCRIPTION 0 7 ixSINK_DESCRIPTION2 2 0x7 1 0 4294967295 DESCRIPTION 0 7 ixSINK_DESCRIPTION3 2 0x8 1 0 4294967295 DESCRIPTION 0 7 ixSINK_DESCRIPTION4 2 0x9 1 0 4294967295 DESCRIPTION 0 7 ixSINK_DESCRIPTION5 2 0xa 1 0 4294967295 DESCRIPTION 0 7 ixSINK_DESCRIPTION6 2 0xb 1 0 4294967295 DESCRIPTION 0 7 ixSINK_DESCRIPTION7 2 0xc 1 0 4294967295 DESCRIPTION 0 7 ixSINK_DESCRIPTION8 2 0xd 1 0 4294967295 DESCRIPTION 0 7 ixSINK_DESCRIPTION9 2 0xe 1 0 4294967295 DESCRIPTION 0 7 ixSINK_DESCRIPTION10 2 0xf 1 0 4294967295 DESCRIPTION 0 7 ixSINK_DESCRIPTION11 2 0x10 1 0 4294967295 DESCRIPTION 0 7 ixSINK_DESCRIPTION12 2 0x11 1 0 4294967295 DESCRIPTION 0 7 ixSINK_DESCRIPTION13 2 0x12 1 0 4294967295 DESCRIPTION 0 7 ixSINK_DESCRIPTION14 2 0x13 1 0 4294967295 DESCRIPTION 0 7 ixSINK_DESCRIPTION15 2 0x14 1 0 4294967295 DESCRIPTION 0 7 ixSINK_DESCRIPTION16 2 0x15 1 0 4294967295 DESCRIPTION 0 7 ixSINK_DESCRIPTION17 2 0x16 1 0 4294967295 DESCRIPTION 0 7 ixAZALIA_INPUT_CRC0_CHANNEL0 2 0x0 1 0 4294967295 INPUT_CRC_CHANNEL0 0 31 ixAZALIA_INPUT_CRC0_CHANNEL1 2 0x1 1 0 4294967295 INPUT_CRC_CHANNEL1 0 31 ixAZALIA_INPUT_CRC0_CHANNEL2 2 0x2 1 0 4294967295 INPUT_CRC_CHANNEL2 0 31 ixAZALIA_INPUT_CRC0_CHANNEL3 2 0x3 1 0 4294967295 INPUT_CRC_CHANNEL3 0 31 ixAZALIA_INPUT_CRC0_CHANNEL4 2 0x4 1 0 4294967295 INPUT_CRC_CHANNEL4 0 31 ixAZALIA_INPUT_CRC0_CHANNEL5 2 0x5 1 0 4294967295 INPUT_CRC_CHANNEL5 0 31 ixAZALIA_INPUT_CRC0_CHANNEL6 2 0x6 1 0 4294967295 INPUT_CRC_CHANNEL6 0 31 ixAZALIA_INPUT_CRC0_CHANNEL7 2 0x7 1 0 4294967295 INPUT_CRC_CHANNEL7 0 31 ixAZALIA_INPUT_CRC1_CHANNEL0 2 0x0 1 0 4294967295 INPUT_CRC_CHANNEL0 0 31 ixAZALIA_INPUT_CRC1_CHANNEL1 2 0x1 1 0 4294967295 INPUT_CRC_CHANNEL1 0 31 ixAZALIA_INPUT_CRC1_CHANNEL2 2 0x2 1 0 4294967295 INPUT_CRC_CHANNEL2 0 31 ixAZALIA_INPUT_CRC1_CHANNEL3 2 0x3 1 0 4294967295 INPUT_CRC_CHANNEL3 0 31 ixAZALIA_INPUT_CRC1_CHANNEL4 2 0x4 1 0 4294967295 INPUT_CRC_CHANNEL4 0 31 ixAZALIA_INPUT_CRC1_CHANNEL5 2 0x5 1 0 4294967295 INPUT_CRC_CHANNEL5 0 31 ixAZALIA_INPUT_CRC1_CHANNEL6 2 0x6 1 0 4294967295 INPUT_CRC_CHANNEL6 0 31 ixAZALIA_INPUT_CRC1_CHANNEL7 2 0x7 1 0 4294967295 INPUT_CRC_CHANNEL7 0 31 ixAZALIA_CRC0_CHANNEL0 2 0x0 1 0 4294967295 CRC_CHANNEL0 0 31 ixAZALIA_CRC0_CHANNEL1 2 0x1 1 0 4294967295 CRC_CHANNEL1 0 31 ixAZALIA_CRC0_CHANNEL2 2 0x2 1 0 4294967295 CRC_CHANNEL2 0 31 ixAZALIA_CRC0_CHANNEL3 2 0x3 1 0 4294967295 CRC_CHANNEL3 0 31 ixAZALIA_CRC0_CHANNEL4 2 0x4 1 0 4294967295 CRC_CHANNEL4 0 31 ixAZALIA_CRC0_CHANNEL5 2 0x5 1 0 4294967295 CRC_CHANNEL5 0 31 ixAZALIA_CRC0_CHANNEL6 2 0x6 1 0 4294967295 CRC_CHANNEL6 0 31 ixAZALIA_CRC0_CHANNEL7 2 0x7 1 0 4294967295 CRC_CHANNEL7 0 31 ixAZALIA_CRC1_CHANNEL0 2 0x0 1 0 4294967295 CRC_CHANNEL0 0 31 ixAZALIA_CRC1_CHANNEL1 2 0x1 1 0 4294967295 CRC_CHANNEL1 0 31 ixAZALIA_CRC1_CHANNEL2 2 0x2 1 0 4294967295 CRC_CHANNEL2 0 31 ixAZALIA_CRC1_CHANNEL3 2 0x3 1 0 4294967295 CRC_CHANNEL3 0 31 ixAZALIA_CRC1_CHANNEL4 2 0x4 1 0 4294967295 CRC_CHANNEL4 0 31 ixAZALIA_CRC1_CHANNEL5 2 0x5 1 0 4294967295 CRC_CHANNEL5 0 31 ixAZALIA_CRC1_CHANNEL6 2 0x6 1 0 4294967295 CRC_CHANNEL6 0 31 ixAZALIA_CRC1_CHANNEL7 2 0x7 1 0 4294967295 CRC_CHANNEL7 0 31 ixAZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT 2 0x6200 6 0 4294967295 NUMBER_OF_CHANNELS 0 3 BITS_PER_SAMPLE 4 6 SAMPLE_BASE_DIVISOR 8 10 SAMPLE_BASE_MULTIPLE 11 13 SAMPLE_BASE_RATE 14 14 STREAM_TYPE 15 15 ixAZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID 2 0x6706 2 0 4294967295 CHANNEL_ID 0 3 STREAM_ID 4 7 ixAZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER 2 0x670d 10 0 4294967295 DIGEN 0 0 V 1 1 VCFG 2 2 PRE 3 3 COPY 4 4 NON_AUDIO 5 5 PRO 6 6 L 7 7 CC 8 14 KEEPALIVE 23 23 ixAZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 2 0x6f09 14 0 4294967295 AUDIO_CHANNEL_CAPABILITIES 0 0 INPUT_AMPLIFIER_PRESENT 1 1 OUTPUT_AMPLIFIER_PRESENT 2 2 AMPLIFIER_PARAMETER_OVERRIDE 3 3 FORMAT_OVERRIDE 4 4 STRIPE 5 5 PROCESSING_WIDGET 6 6 UNSOLICITED_RESPONSE_CAPABILITY 7 7 CONNECTION_LIST 8 8 DIGITAL 9 9 POWER_CONTROL 10 10 LR_SWAP 11 11 AUDIO_WIDGET_CAPABILITIES_DELAY 16 19 TYPE 20 23 ixAZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 2 0x6f0a 2 0 4294967295 AUDIO_RATE_CAPABILITIES 0 11 AUDIO_BIT_CAPABILITIES 16 20 ixAZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS 2 0x6f0b 1 0 4294967295 STREAM_FORMATS 0 31 ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL 2 0x7707 1 0 4294967295 IN_ENABLE 5 5 ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE 2 0x7708 2 0 4294967295 TAG 0 5 ENABLE 7 7 ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_PIN_SENSE 2 0x7709 2 0 4294967295 IMPEDANCE_SENSE 0 30 PRESENCE_DETECT 31 31 ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 2 0x771c 8 0 4294967295 SEQUENCE 0 3 DEFAULT_ASSOCIATION 4 7 MISC 8 11 COLOR 12 15 CONNECTION_TYPE 16 19 DEFAULT_DEVICE 20 23 LOCATION 24 29 PORT_CONNECTIVITY 30 31 ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2 2 0x771d 2 0 4294967295 MISC 0 3 COLOR 4 7 ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3 2 0x771e 2 0 4294967295 CONNECTION_TYPE 0 3 DEFAULT_DEVICE 4 7 ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4 2 0x771f 2 0 4294967295 LOCATION 0 5 PORT_CONNECTIVITY 6 7 ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION 2 0x7771 1 0 4294967295 CHANNEL_ALLOCATION 0 7 ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE 2 0x7777 3 0 4294967295 MULTICHANNEL0_ENABLE 0 0 MULTICHANNEL0_MUTE 1 1 MULTICHANNEL0_CHANNEL_ID 4 7 ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE 2 0x7778 3 0 4294967295 MULTICHANNEL2_ENABLE 0 0 MULTICHANNEL2_MUTE 1 1 MULTICHANNEL2_CHANNEL_ID 4 7 ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE 2 0x7779 3 0 4294967295 MULTICHANNEL4_ENABLE 0 0 MULTICHANNEL4_MUTE 1 1 MULTICHANNEL4_CHANNEL_ID 4 7 ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE 2 0x777a 3 0 4294967295 MULTICHANNEL6_ENABLE 0 0 MULTICHANNEL6_MUTE 1 1 MULTICHANNEL6_CHANNEL_ID 4 7 ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_HBR 2 0x777c 2 0 4294967295 HBR_CAPABLE 0 0 HBR_ENABLE 4 4 ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE 2 0x7785 3 0 4294967295 MULTICHANNEL1_ENABLE 0 0 MULTICHANNEL1_MUTE 1 1 MULTICHANNEL1_CHANNEL_ID 4 7 ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE 2 0x7786 3 0 4294967295 MULTICHANNEL3_ENABLE 0 0 MULTICHANNEL3_MUTE 1 1 MULTICHANNEL3_CHANNEL_ID 4 7 ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE 2 0x7787 3 0 4294967295 MULTICHANNEL5_ENABLE 0 0 MULTICHANNEL5_MUTE 1 1 MULTICHANNEL5_CHANNEL_ID 4 7 ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE 2 0x7788 3 0 4294967295 MULTICHANNEL7_ENABLE 0 0 MULTICHANNEL7_MUTE 1 1 MULTICHANNEL7_CHANNEL_ID 4 7 ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 2 0x7798 2 0 4294967295 LPIB_SNAPSHOT_LOCK 0 0 CYCLIC_BUFFER_WRAP_COUNT 8 15 ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB 2 0x7799 1 0 4294967295 LPIB 0 31 ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 2 0x779a 1 0 4294967295 LPIB_TIMER_SNAPSHOT 0 31 ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL 2 0x779b 4 0 4294967295 INPUT_ACTIVITY 0 0 CHANNEL_LAYOUT 1 2 INPUT_ACTIVITY_UR_ENABLE 4 4 INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE 5 5 ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_INFOFRAME 2 0x779c 4 0 4294967295 CHANNEL_COUNT 0 2 CHANNEL_ALLOCATION 8 15 INFOFRAME_BYTE_5 16 23 INFOFRAME_VALID 31 31 ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_STATUS_L 2 0x779d 1 0 4294967295 CHANNEL_STATUS_L 0 31 ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_STATUS_H 2 0x779e 1 0 4294967295 CHANNEL_STATUS_H 0 31 ixAZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 2 0x7f09 13 0 4294967295 AUDIO_CHANNEL_CAPABILITIES 0 0 INPUT_AMPLIFIER_PRESENT 1 1 OUTPUT_AMPLIFIER_PRESENT 2 2 AMPLIFIER_PARAMETER_OVERRIDE 3 3 STRIPE 5 5 PROCESSING_WIDGET 6 6 UNSOLICITED_RESPONSE_CAPABILITY 7 7 CONNECTION_LIST 8 8 DIGITAL 9 9 POWER_CONTROL 10 10 LR_SWAP 11 11 AUDIO_WIDGET_CAPABILITIES_DELAY 16 19 TYPE 20 23 ixAZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES 2 0x7f0c 11 0 4294967295 IMPEDANCE_SENSE_CAPABLE 0 0 TRIGGER_REQUIRED 1 1 JACK_DETECTION_CAPABILITY 2 2 HEADPHONE_DRIVE_CAPABLE 3 3 OUTPUT_CAPABLE 4 4 INPUT_CAPABLE 5 5 BALANCED_I_O_PINS 6 6 HDMI 7 7 VREF_CONTROL 8 15 EAPD_CAPABLE 16 16 DP 24 24 ixAZALIA_F2_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID 2 0xf00 1 0 4294967295 AZALIA_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID 0 31 ixAZALIA_F2_CODEC_ROOT_PARAMETER_REVISION_ID 2 0xf02 1 0 4294967295 AZALIA_CODEC_ROOT_PARAMETER_REVISION_ID 0 31 ixAZALIA_F2_CODEC_ROOT_PARAMETER_SUBORDINATE_NODE_COUNT 2 0xf04 1 0 4294967295 AZALIA_CODEC_ROOT_PARAMETER_SUBORDINATE_NODE_COUNT 0 31 ixAZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE 2 0x1705 4 0 4294967295 POWER_STATE_SET 0 3 POWER_STATE_ACT 4 7 CLKSTOPOK 9 9 POWER_STATE_SETTINGS_RESET 10 10 ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID 2 0x1720 4 0 4294967295 SUBSYSTEM_ID_BYTE0 0 7 SUBSYSTEM_ID_BYTE1 8 15 SUBSYSTEM_ID_BYTE2 16 23 SUBSYSTEM_ID_BYTE3 24 31 ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_2 2 0x1721 1 0 4294967295 SUBSYSTEM_ID_BYTE1 0 7 ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_3 2 0x1722 1 0 4294967295 SUBSYSTEM_ID_BYTE2 0 7 ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_4 2 0x1723 1 0 4294967295 SUBSYSTEM_ID_BYTE3 0 7 ixAZALIA_F2_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION 2 0x1770 1 0 4294967295 CONVERTER_SYNCHRONIZATION 0 7 ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESET 2 0x17ff 1 0 4294967295 CODEC_RESET 0 0 ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_SUBORDINATE_NODE_COUNT 2 0x1f04 1 0 4294967295 AZALIA_CODEC_FUNCTION_PARAMETER_SUBORDINATE_NODE_COUNT 0 31 ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_GROUP_TYPE 2 0x1f05 1 0 4294967295 AZALIA_CODEC_FUNCTION_PARAMETER_GROUP_TYPE 0 31 ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES 2 0x1f0a 2 0 4294967295 AUDIO_RATE_CAPABILITIES 0 11 AUDIO_BIT_CAPABILITIES 16 20 ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS 2 0x1f0b 1 0 4294967295 AZALIA_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS 0 31 ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES 2 0x1f0f 3 0 4294967295 AZALIA_CODEC_FUNCTION_PARAMETER_POWER_STATES 0 29 CLKSTOP 30 30 EPSS 31 31 ixAZF0STREAM0_AZALIA_FIFO_SIZE_CONTROL 2 0x0 3 0 4294967295 MIN_FIFO_SIZE 0 6 MAX_FIFO_SIZE 8 14 MAX_LATENCY_SUPPORT 16 23 ixAZF0STREAM0_AZALIA_LATENCY_COUNTER_CONTROL 2 0x1 1 0 4294967295 AZALIA_LATENCY_COUNTER_RESET 0 0 ixAZF0STREAM0_AZALIA_WORSTCASE_LATENCY_COUNT 2 0x2 1 0 4294967295 AZALIA_WORSTCASE_LATENCY_COUNT 0 31 ixAZF0STREAM0_AZALIA_CUMULATIVE_LATENCY_COUNT 2 0x3 1 0 4294967295 AZALIA_CUMULATIVE_LATENCY_COUNT 0 31 ixAZF0STREAM0_AZALIA_CUMULATIVE_REQUEST_COUNT 2 0x4 1 0 4294967295 AZALIA_CUMULATIVE_REQUEST_COUNT 0 31 ixAZF0STREAM1_AZALIA_FIFO_SIZE_CONTROL 2 0x0 3 0 4294967295 MIN_FIFO_SIZE 0 6 MAX_FIFO_SIZE 8 14 MAX_LATENCY_SUPPORT 16 23 ixAZF0STREAM1_AZALIA_LATENCY_COUNTER_CONTROL 2 0x1 1 0 4294967295 AZALIA_LATENCY_COUNTER_RESET 0 0 ixAZF0STREAM1_AZALIA_WORSTCASE_LATENCY_COUNT 2 0x2 1 0 4294967295 AZALIA_WORSTCASE_LATENCY_COUNT 0 31 ixAZF0STREAM1_AZALIA_CUMULATIVE_LATENCY_COUNT 2 0x3 1 0 4294967295 AZALIA_CUMULATIVE_LATENCY_COUNT 0 31 ixAZF0STREAM1_AZALIA_CUMULATIVE_REQUEST_COUNT 2 0x4 1 0 4294967295 AZALIA_CUMULATIVE_REQUEST_COUNT 0 31 ixAZF0STREAM2_AZALIA_FIFO_SIZE_CONTROL 2 0x0 3 0 4294967295 MIN_FIFO_SIZE 0 6 MAX_FIFO_SIZE 8 14 MAX_LATENCY_SUPPORT 16 23 ixAZF0STREAM2_AZALIA_LATENCY_COUNTER_CONTROL 2 0x1 1 0 4294967295 AZALIA_LATENCY_COUNTER_RESET 0 0 ixAZF0STREAM2_AZALIA_WORSTCASE_LATENCY_COUNT 2 0x2 1 0 4294967295 AZALIA_WORSTCASE_LATENCY_COUNT 0 31 ixAZF0STREAM2_AZALIA_CUMULATIVE_LATENCY_COUNT 2 0x3 1 0 4294967295 AZALIA_CUMULATIVE_LATENCY_COUNT 0 31 ixAZF0STREAM2_AZALIA_CUMULATIVE_REQUEST_COUNT 2 0x4 1 0 4294967295 AZALIA_CUMULATIVE_REQUEST_COUNT 0 31 ixAZF0STREAM3_AZALIA_FIFO_SIZE_CONTROL 2 0x0 3 0 4294967295 MIN_FIFO_SIZE 0 6 MAX_FIFO_SIZE 8 14 MAX_LATENCY_SUPPORT 16 23 ixAZF0STREAM3_AZALIA_LATENCY_COUNTER_CONTROL 2 0x1 1 0 4294967295 AZALIA_LATENCY_COUNTER_RESET 0 0 ixAZF0STREAM3_AZALIA_WORSTCASE_LATENCY_COUNT 2 0x2 1 0 4294967295 AZALIA_WORSTCASE_LATENCY_COUNT 0 31 ixAZF0STREAM3_AZALIA_CUMULATIVE_LATENCY_COUNT 2 0x3 1 0 4294967295 AZALIA_CUMULATIVE_LATENCY_COUNT 0 31 ixAZF0STREAM3_AZALIA_CUMULATIVE_REQUEST_COUNT 2 0x4 1 0 4294967295 AZALIA_CUMULATIVE_REQUEST_COUNT 0 31 ixAZF0STREAM4_AZALIA_FIFO_SIZE_CONTROL 2 0x0 3 0 4294967295 MIN_FIFO_SIZE 0 6 MAX_FIFO_SIZE 8 14 MAX_LATENCY_SUPPORT 16 23 ixAZF0STREAM4_AZALIA_LATENCY_COUNTER_CONTROL 2 0x1 1 0 4294967295 AZALIA_LATENCY_COUNTER_RESET 0 0 ixAZF0STREAM4_AZALIA_WORSTCASE_LATENCY_COUNT 2 0x2 1 0 4294967295 AZALIA_WORSTCASE_LATENCY_COUNT 0 31 ixAZF0STREAM4_AZALIA_CUMULATIVE_LATENCY_COUNT 2 0x3 1 0 4294967295 AZALIA_CUMULATIVE_LATENCY_COUNT 0 31 ixAZF0STREAM4_AZALIA_CUMULATIVE_REQUEST_COUNT 2 0x4 1 0 4294967295 AZALIA_CUMULATIVE_REQUEST_COUNT 0 31 ixAZF0STREAM5_AZALIA_FIFO_SIZE_CONTROL 2 0x0 3 0 4294967295 MIN_FIFO_SIZE 0 6 MAX_FIFO_SIZE 8 14 MAX_LATENCY_SUPPORT 16 23 ixAZF0STREAM5_AZALIA_LATENCY_COUNTER_CONTROL 2 0x1 1 0 4294967295 AZALIA_LATENCY_COUNTER_RESET 0 0 ixAZF0STREAM5_AZALIA_WORSTCASE_LATENCY_COUNT 2 0x2 1 0 4294967295 AZALIA_WORSTCASE_LATENCY_COUNT 0 31 ixAZF0STREAM5_AZALIA_CUMULATIVE_LATENCY_COUNT 2 0x3 1 0 4294967295 AZALIA_CUMULATIVE_LATENCY_COUNT 0 31 ixAZF0STREAM5_AZALIA_CUMULATIVE_REQUEST_COUNT 2 0x4 1 0 4294967295 AZALIA_CUMULATIVE_REQUEST_COUNT 0 31 ixAZF0STREAM6_AZALIA_FIFO_SIZE_CONTROL 2 0x0 3 0 4294967295 MIN_FIFO_SIZE 0 6 MAX_FIFO_SIZE 8 14 MAX_LATENCY_SUPPORT 16 23 ixAZF0STREAM6_AZALIA_LATENCY_COUNTER_CONTROL 2 0x1 1 0 4294967295 AZALIA_LATENCY_COUNTER_RESET 0 0 ixAZF0STREAM6_AZALIA_WORSTCASE_LATENCY_COUNT 2 0x2 1 0 4294967295 AZALIA_WORSTCASE_LATENCY_COUNT 0 31 ixAZF0STREAM6_AZALIA_CUMULATIVE_LATENCY_COUNT 2 0x3 1 0 4294967295 AZALIA_CUMULATIVE_LATENCY_COUNT 0 31 ixAZF0STREAM6_AZALIA_CUMULATIVE_REQUEST_COUNT 2 0x4 1 0 4294967295 AZALIA_CUMULATIVE_REQUEST_COUNT 0 31 ixAZF0STREAM7_AZALIA_FIFO_SIZE_CONTROL 2 0x0 3 0 4294967295 MIN_FIFO_SIZE 0 6 MAX_FIFO_SIZE 8 14 MAX_LATENCY_SUPPORT 16 23 ixAZF0STREAM7_AZALIA_LATENCY_COUNTER_CONTROL 2 0x1 1 0 4294967295 AZALIA_LATENCY_COUNTER_RESET 0 0 ixAZF0STREAM7_AZALIA_WORSTCASE_LATENCY_COUNT 2 0x2 1 0 4294967295 AZALIA_WORSTCASE_LATENCY_COUNT 0 31 ixAZF0STREAM7_AZALIA_CUMULATIVE_LATENCY_COUNT 2 0x3 1 0 4294967295 AZALIA_CUMULATIVE_LATENCY_COUNT 0 31 ixAZF0STREAM7_AZALIA_CUMULATIVE_REQUEST_COUNT 2 0x4 1 0 4294967295 AZALIA_CUMULATIVE_REQUEST_COUNT 0 31 ixAZF0STREAM8_AZALIA_FIFO_SIZE_CONTROL 2 0x0 3 0 4294967295 MIN_FIFO_SIZE 0 6 MAX_FIFO_SIZE 8 14 MAX_LATENCY_SUPPORT 16 23 ixAZF0STREAM8_AZALIA_LATENCY_COUNTER_CONTROL 2 0x1 1 0 4294967295 AZALIA_LATENCY_COUNTER_RESET 0 0 ixAZF0STREAM8_AZALIA_WORSTCASE_LATENCY_COUNT 2 0x2 1 0 4294967295 AZALIA_WORSTCASE_LATENCY_COUNT 0 31 ixAZF0STREAM8_AZALIA_CUMULATIVE_LATENCY_COUNT 2 0x3 1 0 4294967295 AZALIA_CUMULATIVE_LATENCY_COUNT 0 31 ixAZF0STREAM8_AZALIA_CUMULATIVE_REQUEST_COUNT 2 0x4 1 0 4294967295 AZALIA_CUMULATIVE_REQUEST_COUNT 0 31 ixAZF0STREAM9_AZALIA_FIFO_SIZE_CONTROL 2 0x0 3 0 4294967295 MIN_FIFO_SIZE 0 6 MAX_FIFO_SIZE 8 14 MAX_LATENCY_SUPPORT 16 23 ixAZF0STREAM9_AZALIA_LATENCY_COUNTER_CONTROL 2 0x1 1 0 4294967295 AZALIA_LATENCY_COUNTER_RESET 0 0 ixAZF0STREAM9_AZALIA_WORSTCASE_LATENCY_COUNT 2 0x2 1 0 4294967295 AZALIA_WORSTCASE_LATENCY_COUNT 0 31 ixAZF0STREAM9_AZALIA_CUMULATIVE_LATENCY_COUNT 2 0x3 1 0 4294967295 AZALIA_CUMULATIVE_LATENCY_COUNT 0 31 ixAZF0STREAM9_AZALIA_CUMULATIVE_REQUEST_COUNT 2 0x4 1 0 4294967295 AZALIA_CUMULATIVE_REQUEST_COUNT 0 31 ixAZF0STREAM10_AZALIA_FIFO_SIZE_CONTROL 2 0x0 3 0 4294967295 MIN_FIFO_SIZE 0 6 MAX_FIFO_SIZE 8 14 MAX_LATENCY_SUPPORT 16 23 ixAZF0STREAM10_AZALIA_LATENCY_COUNTER_CONTROL 2 0x1 1 0 4294967295 AZALIA_LATENCY_COUNTER_RESET 0 0 ixAZF0STREAM10_AZALIA_WORSTCASE_LATENCY_COUNT 2 0x2 1 0 4294967295 AZALIA_WORSTCASE_LATENCY_COUNT 0 31 ixAZF0STREAM10_AZALIA_CUMULATIVE_LATENCY_COUNT 2 0x3 1 0 4294967295 AZALIA_CUMULATIVE_LATENCY_COUNT 0 31 ixAZF0STREAM10_AZALIA_CUMULATIVE_REQUEST_COUNT 2 0x4 1 0 4294967295 AZALIA_CUMULATIVE_REQUEST_COUNT 0 31 ixAZF0STREAM11_AZALIA_FIFO_SIZE_CONTROL 2 0x0 3 0 4294967295 MIN_FIFO_SIZE 0 6 MAX_FIFO_SIZE 8 14 MAX_LATENCY_SUPPORT 16 23 ixAZF0STREAM11_AZALIA_LATENCY_COUNTER_CONTROL 2 0x1 1 0 4294967295 AZALIA_LATENCY_COUNTER_RESET 0 0 ixAZF0STREAM11_AZALIA_WORSTCASE_LATENCY_COUNT 2 0x2 1 0 4294967295 AZALIA_WORSTCASE_LATENCY_COUNT 0 31 ixAZF0STREAM11_AZALIA_CUMULATIVE_LATENCY_COUNT 2 0x3 1 0 4294967295 AZALIA_CUMULATIVE_LATENCY_COUNT 0 31 ixAZF0STREAM11_AZALIA_CUMULATIVE_REQUEST_COUNT 2 0x4 1 0 4294967295 AZALIA_CUMULATIVE_REQUEST_COUNT 0 31 ixAZF0STREAM12_AZALIA_FIFO_SIZE_CONTROL 2 0x0 3 0 4294967295 MIN_FIFO_SIZE 0 6 MAX_FIFO_SIZE 8 14 MAX_LATENCY_SUPPORT 16 23 ixAZF0STREAM12_AZALIA_LATENCY_COUNTER_CONTROL 2 0x1 1 0 4294967295 AZALIA_LATENCY_COUNTER_RESET 0 0 ixAZF0STREAM12_AZALIA_WORSTCASE_LATENCY_COUNT 2 0x2 1 0 4294967295 AZALIA_WORSTCASE_LATENCY_COUNT 0 31 ixAZF0STREAM12_AZALIA_CUMULATIVE_LATENCY_COUNT 2 0x3 1 0 4294967295 AZALIA_CUMULATIVE_LATENCY_COUNT 0 31 ixAZF0STREAM12_AZALIA_CUMULATIVE_REQUEST_COUNT 2 0x4 1 0 4294967295 AZALIA_CUMULATIVE_REQUEST_COUNT 0 31 ixAZF0STREAM13_AZALIA_FIFO_SIZE_CONTROL 2 0x0 3 0 4294967295 MIN_FIFO_SIZE 0 6 MAX_FIFO_SIZE 8 14 MAX_LATENCY_SUPPORT 16 23 ixAZF0STREAM13_AZALIA_LATENCY_COUNTER_CONTROL 2 0x1 1 0 4294967295 AZALIA_LATENCY_COUNTER_RESET 0 0 ixAZF0STREAM13_AZALIA_WORSTCASE_LATENCY_COUNT 2 0x2 1 0 4294967295 AZALIA_WORSTCASE_LATENCY_COUNT 0 31 ixAZF0STREAM13_AZALIA_CUMULATIVE_LATENCY_COUNT 2 0x3 1 0 4294967295 AZALIA_CUMULATIVE_LATENCY_COUNT 0 31 ixAZF0STREAM13_AZALIA_CUMULATIVE_REQUEST_COUNT 2 0x4 1 0 4294967295 AZALIA_CUMULATIVE_REQUEST_COUNT 0 31 ixAZF0STREAM14_AZALIA_FIFO_SIZE_CONTROL 2 0x0 3 0 4294967295 MIN_FIFO_SIZE 0 6 MAX_FIFO_SIZE 8 14 MAX_LATENCY_SUPPORT 16 23 ixAZF0STREAM14_AZALIA_LATENCY_COUNTER_CONTROL 2 0x1 1 0 4294967295 AZALIA_LATENCY_COUNTER_RESET 0 0 ixAZF0STREAM14_AZALIA_WORSTCASE_LATENCY_COUNT 2 0x2 1 0 4294967295 AZALIA_WORSTCASE_LATENCY_COUNT 0 31 ixAZF0STREAM14_AZALIA_CUMULATIVE_LATENCY_COUNT 2 0x3 1 0 4294967295 AZALIA_CUMULATIVE_LATENCY_COUNT 0 31 ixAZF0STREAM14_AZALIA_CUMULATIVE_REQUEST_COUNT 2 0x4 1 0 4294967295 AZALIA_CUMULATIVE_REQUEST_COUNT 0 31 ixAZF0STREAM15_AZALIA_FIFO_SIZE_CONTROL 2 0x0 3 0 4294967295 MIN_FIFO_SIZE 0 6 MAX_FIFO_SIZE 8 14 MAX_LATENCY_SUPPORT 16 23 ixAZF0STREAM15_AZALIA_LATENCY_COUNTER_CONTROL 2 0x1 1 0 4294967295 AZALIA_LATENCY_COUNTER_RESET 0 0 ixAZF0STREAM15_AZALIA_WORSTCASE_LATENCY_COUNT 2 0x2 1 0 4294967295 AZALIA_WORSTCASE_LATENCY_COUNT 0 31 ixAZF0STREAM15_AZALIA_CUMULATIVE_LATENCY_COUNT 2 0x3 1 0 4294967295 AZALIA_CUMULATIVE_LATENCY_COUNT 0 31 ixAZF0STREAM15_AZALIA_CUMULATIVE_REQUEST_COUNT 2 0x4 1 0 4294967295 AZALIA_CUMULATIVE_REQUEST_COUNT 0 31 ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 2 0x1 14 0 4294967295 AUDIO_CHANNEL_CAPABILITIES 0 0 INPUT_AMPLIFIER_PRESENT 1 1 OUTPUT_AMPLIFIER_PRESENT 2 2 AMPLIFIER_PARAMETER_OVERRIDE 3 3 FORMAT_OVERRIDE 4 4 STRIPE 5 5 PROCESSING_WIDGET 6 6 UNSOLICITED_RESPONSE_CAPABILITY 7 7 CONNECTION_LIST 8 8 DIGITAL 9 9 POWER_CONTROL 10 10 LR_SWAP 11 11 AUDIO_WIDGET_CAPABILITIES_DELAY 16 19 TYPE 20 23 ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT 2 0x2 6 0 4294967295 NUMBER_OF_CHANNELS 0 3 BITS_PER_SAMPLE 4 6 SAMPLE_BASE_DIVISOR 8 10 SAMPLE_BASE_MULTIPLE 11 13 SAMPLE_BASE_RATE 14 14 STREAM_TYPE 15 15 ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID 2 0x3 2 0 4294967295 CHANNEL_ID 0 3 STREAM_ID 4 7 ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER 2 0x4 10 0 4294967295 DIGEN 0 0 V 1 1 VCFG 2 2 PRE 3 3 COPY 4 4 NON_AUDIO 5 5 PRO 6 6 L 7 7 CC 8 14 KEEPALIVE 23 23 ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS 2 0x5 1 0 4294967295 STREAM_FORMATS 0 31 ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 2 0x6 2 0 4294967295 AUDIO_RATE_CAPABILITIES 0 11 AUDIO_BIT_CAPABILITIES 16 20 ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL 2 0x7 2 0 4294967295 STRIPE_CONTROL 0 1 STRIPE_CAPABILITY 20 22 ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE 2 0x8 1 0 4294967295 RAMP_RATE 0 7 ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING 2 0x9 4 0 4294967295 PRESENTATION_TIME_EMBEDDING_ENABLE 0 0 PRESENTATION_TIME_OFFSET_CHANGED 1 1 CLEAR_GTC_COUNTER_MIN_MAX_DELTA 2 2 PRESENTATION_TIME_EMBEDDING_GROUP 4 6 ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA 2 0xc 1 0 4294967295 GTC_COUNTER_DELTA 0 31 ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN 2 0xd 1 0 4294967295 GTC_COUNTER_DELTA_MIN 0 31 ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX 2 0xe 1 0 4294967295 GTC_COUNTER_DELTA_MAX 0 31 ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 2 0x20 13 0 4294967295 AUDIO_CHANNEL_CAPABILITIES 0 0 INPUT_AMPLIFIER_PRESENT 1 1 OUTPUT_AMPLIFIER_PRESENT 2 2 AMPLIFIER_PARAMETER_OVERRIDE 3 3 STRIPE 5 5 PROCESSING_WIDGET 6 6 UNSOLICITED_RESPONSE_CAPABILITY 7 7 CONNECTION_LIST 8 8 DIGITAL 9 9 POWER_CONTROL 10 10 LR_SWAP 11 11 AUDIO_WIDGET_CAPABILITIES_DELAY 16 19 TYPE 20 23 ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES 2 0x21 11 0 4294967295 IMPEDANCE_SENSE_CAPABLE 0 0 TRIGGER_REQUIRED 1 1 JACK_DETECTION_CAPABILITY 2 2 HEADPHONE_DRIVE_CAPABLE 3 3 OUTPUT_CAPABLE 4 4 INPUT_CAPABLE 5 5 BALANCED_I_O_PINS 6 6 HDMI 7 7 VREF_CONTROL 8 15 EAPD_CAPABLE 16 16 DP 24 24 ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE 2 0x22 2 0 4294967295 TAG 0 5 ENABLE 7 7 ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE 2 0x23 1 0 4294967295 IMPEDANCE_SENSE 0 30 ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL 2 0x24 1 0 4294967295 OUT_ENABLE 6 6 ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER 2 0x25 8 0 4294967295 SPEAKER_ALLOCATION 0 6 CHANNEL_ALLOCATION 8 15 HDMI_CONNECTION 16 16 DP_CONNECTION 17 17 EXTRA_CONNECTION_INFO 18 23 LFE_PLAYBACK_LEVEL 24 25 LEVEL_SHIFT 27 30 DOWN_MIX_INHIBIT 31 31 ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 2 0x28 4 0 4294967295 MAX_CHANNELS 0 2 SUPPORTED_FREQUENCIES 8 15 DESCRIPTOR_BYTE_2 16 23 SUPPORTED_FREQUENCIES_STEREO 24 31 ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 2 0x29 3 0 4294967295 MAX_CHANNELS 0 2 SUPPORTED_FREQUENCIES 8 15 DESCRIPTOR_BYTE_2 16 23 ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 2 0x2a 3 0 4294967295 MAX_CHANNELS 0 2 SUPPORTED_FREQUENCIES 8 15 DESCRIPTOR_BYTE_2 16 23 ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 2 0x2b 3 0 4294967295 MAX_CHANNELS 0 2 SUPPORTED_FREQUENCIES 8 15 DESCRIPTOR_BYTE_2 16 23 ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 2 0x2c 3 0 4294967295 MAX_CHANNELS 0 2 SUPPORTED_FREQUENCIES 8 15 DESCRIPTOR_BYTE_2 16 23 ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 2 0x2d 3 0 4294967295 MAX_CHANNELS 0 2 SUPPORTED_FREQUENCIES 8 15 DESCRIPTOR_BYTE_2 16 23 ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 2 0x2e 3 0 4294967295 MAX_CHANNELS 0 2 SUPPORTED_FREQUENCIES 8 15 DESCRIPTOR_BYTE_2 16 23 ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 2 0x2f 3 0 4294967295 MAX_CHANNELS 0 2 SUPPORTED_FREQUENCIES 8 15 DESCRIPTOR_BYTE_2 16 23 ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 2 0x30 3 0 4294967295 MAX_CHANNELS 0 2 SUPPORTED_FREQUENCIES 8 15 DESCRIPTOR_BYTE_2 16 23 ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 2 0x31 3 0 4294967295 MAX_CHANNELS 0 2 SUPPORTED_FREQUENCIES 8 15 DESCRIPTOR_BYTE_2 16 23 ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 2 0x32 3 0 4294967295 MAX_CHANNELS 0 2 SUPPORTED_FREQUENCIES 8 15 DESCRIPTOR_BYTE_2 16 23 ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 2 0x33 3 0 4294967295 MAX_CHANNELS 0 2 SUPPORTED_FREQUENCIES 8 15 DESCRIPTOR_BYTE_2 16 23 ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 2 0x34 3 0 4294967295 MAX_CHANNELS 0 2 SUPPORTED_FREQUENCIES 8 15 DESCRIPTOR_BYTE_2 16 23 ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 2 0x35 3 0 4294967295 MAX_CHANNELS 0 2 SUPPORTED_FREQUENCIES 8 15 DESCRIPTOR_BYTE_2 16 23 ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE 2 0x36 12 0 4294967295 MULTICHANNEL01_ENABLE 0 0 MULTICHANNEL01_MUTE 1 1 MULTICHANNEL01_CHANNEL_ID 4 7 MULTICHANNEL23_ENABLE 8 8 MULTICHANNEL23_MUTE 9 9 MULTICHANNEL23_CHANNEL_ID 12 15 MULTICHANNEL45_ENABLE 16 16 MULTICHANNEL45_MUTE 17 17 MULTICHANNEL45_CHANNEL_ID 20 23 MULTICHANNEL67_ENABLE 24 24 MULTICHANNEL67_MUTE 25 25 MULTICHANNEL67_CHANNEL_ID 28 31 ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC 2 0x37 2 0 4294967295 VIDEO_LIPSYNC 0 7 AUDIO_LIPSYNC 8 15 ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR 2 0x38 2 0 4294967295 HBR_CAPABLE 0 0 HBR_ENABLE 4 4 ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0 2 0x3a 2 0 4294967295 MANUFACTURER_ID 0 15 PRODUCT_ID 16 31 ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1 2 0x3b 1 0 4294967295 SINK_DESCRIPTION_LEN 0 7 ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2 2 0x3c 1 0 4294967295 PORT_ID0 0 31 ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3 2 0x3d 1 0 4294967295 PORT_ID1 0 31 ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4 2 0x3e 4 0 4294967295 DESCRIPTION0 0 7 DESCRIPTION1 8 15 DESCRIPTION2 16 23 DESCRIPTION3 24 31 ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5 2 0x3f 4 0 4294967295 DESCRIPTION4 0 7 DESCRIPTION5 8 15 DESCRIPTION6 16 23 DESCRIPTION7 24 31 ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6 2 0x40 4 0 4294967295 DESCRIPTION8 0 7 DESCRIPTION9 8 15 DESCRIPTION10 16 23 DESCRIPTION11 24 31 ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7 2 0x41 4 0 4294967295 DESCRIPTION12 0 7 DESCRIPTION13 8 15 DESCRIPTION14 16 23 DESCRIPTION15 24 31 ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8 2 0x42 2 0 4294967295 DESCRIPTION16 0 7 DESCRIPTION17 8 15 ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL 2 0x54 3 0 4294967295 CLOCK_GATING_DISABLE 0 0 CLOCK_ON_STATE 4 4 AUDIO_ENABLED 31 31 ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 2 0x55 2 0 4294967295 UNSOLICITED_RESPONSE_PAYLOAD 0 25 UNSOLICITED_RESPONSE_FORCE 28 28 ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 2 0x56 8 0 4294967295 SEQUENCE 0 3 DEFAULT_ASSOCIATION 4 7 MISC 8 11 COLOR 12 15 CONNECTION_TYPE 16 19 DEFAULT_DEVICE 20 23 LOCATION 24 29 PORT_CONNECTIVITY 30 31 ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2 2 0x57 12 0 4294967295 MULTICHANNEL1_ENABLE 0 0 MULTICHANNEL1_MUTE 1 1 MULTICHANNEL1_CHANNEL_ID 4 7 MULTICHANNEL3_ENABLE 8 8 MULTICHANNEL3_MUTE 9 9 MULTICHANNEL3_CHANNEL_ID 12 15 MULTICHANNEL5_ENABLE 16 16 MULTICHANNEL5_MUTE 17 17 MULTICHANNEL5_CHANNEL_ID 20 23 MULTICHANNEL7_ENABLE 24 24 MULTICHANNEL7_MUTE 25 25 MULTICHANNEL7_CHANNEL_ID 28 31 ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE 2 0x58 1 0 4294967295 MULTICHANNEL_MODE 0 0 ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0 2 0x59 2 0 4294967295 IEC_60958_CS_MODE 0 1 IEC_60958_CS_SOURCE_NUMBER 2 5 ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1 2 0x5a 4 0 4294967295 IEC_60958_CS_CLOCK_ACCURACY 0 1 IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN 2 2 IEC_60958_CS_WORD_LENGTH 3 6 IEC_60958_CS_WORD_LENGTH_OVRRD_EN 7 7 ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2 2 0x5b 2 0 4294967295 IEC_60958_CS_SAMPLING_FREQUENCY 0 5 IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN 6 6 ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3 2 0x5c 2 0 4294967295 IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY 0 3 IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN 4 4 ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4 2 0x5d 4 0 4294967295 IEC_60958_CS_SAMPLING_FREQUENCY_COEFF 0 3 IEC_60958_CS_MPEG_SURROUND_INFO 4 4 IEC_60958_CS_CGMS_A 5 6 IEC_60958_CS_CGMS_A_VALID 7 7 ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5 2 0x5e 2 0 4294967295 IEC_60958_CS_CHANNEL_NUMBER_L 0 3 IEC_60958_CS_CHANNEL_NUMBER_R 4 7 ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6 2 0x5f 2 0 4294967295 IEC_60958_CS_CHANNEL_NUMBER_2 0 3 IEC_60958_CS_CHANNEL_NUMBER_3 4 7 ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7 2 0x60 2 0 4294967295 IEC_60958_CS_CHANNEL_NUMBER_4 0 3 IEC_60958_CS_CHANNEL_NUMBER_5 4 7 ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8 2 0x61 2 0 4294967295 IEC_60958_CS_CHANNEL_NUMBER_6 0 3 IEC_60958_CS_CHANNEL_NUMBER_7 4 7 ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO 2 0x62 1 0 4294967295 ASSOCIATION_INFO 0 31 ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS 2 0x63 1 0 4294967295 OUTPUT_ACTIVE 0 0 ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 2 0x64 2 0 4294967295 LPIB_SNAPSHOT_LOCK 0 0 CYCLIC_BUFFER_WRAP_COUNT 8 15 ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB 2 0x65 1 0 4294967295 LPIB 0 31 ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 2 0x66 1 0 4294967295 LPIB_TIMER_SNAPSHOT 0 31 ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE 2 0x67 1 0 4294967295 CODING_TYPE 0 7 ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED 2 0x68 4 0 4294967295 FORMAT_CHANGED 0 0 FORMAT_CHANGED_ACK_UR_ENABLE 1 1 FORMAT_CHANGE_REASON 8 15 FORMAT_CHANGE_RESPONSE 16 23 ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION 2 0x69 1 0 4294967295 WIRELESS_DISPLAY_IDENTIFICATION 0 1 ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE 2 0x6a 2 0 4294967295 REMOTE_KEEP_ALIVE_ENABLE 0 0 REMOTE_KEEP_ALIVE_CAPABILITY 4 4 ixAZF0ENDPOINT0_AZALIA_F0_AUDIO_ENABLE_STATUS 2 0x6b 1 0 4294967295 AUDIO_ENABLE_STATUS 0 0 ixAZF0ENDPOINT0_AZALIA_F0_AUDIO_ENABLED_INT_STATUS 2 0x6c 3 0 4294967295 AUDIO_ENABLED_FLAG 0 0 AUDIO_ENABLED_MASK 4 4 AUDIO_ENABLED_TYPE 8 8 ixAZF0ENDPOINT0_AZALIA_F0_AUDIO_DISABLED_INT_STATUS 2 0x6d 3 0 4294967295 AUDIO_DISABLED_FLAG 0 0 AUDIO_DISABLED_MASK 4 4 AUDIO_DISABLED_TYPE 8 8 ixAZF0ENDPOINT0_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS 2 0x6e 3 0 4294967295 AUDIO_FORMAT_CHANGED_FLAG 0 0 AUDIO_FORMAT_CHANGED_MASK 4 4 AUDIO_FORMAT_CHANGED_TYPE 8 8 ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 2 0x1 14 0 4294967295 AUDIO_CHANNEL_CAPABILITIES 0 0 INPUT_AMPLIFIER_PRESENT 1 1 OUTPUT_AMPLIFIER_PRESENT 2 2 AMPLIFIER_PARAMETER_OVERRIDE 3 3 FORMAT_OVERRIDE 4 4 STRIPE 5 5 PROCESSING_WIDGET 6 6 UNSOLICITED_RESPONSE_CAPABILITY 7 7 CONNECTION_LIST 8 8 DIGITAL 9 9 POWER_CONTROL 10 10 LR_SWAP 11 11 AUDIO_WIDGET_CAPABILITIES_DELAY 16 19 TYPE 20 23 ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT 2 0x2 6 0 4294967295 NUMBER_OF_CHANNELS 0 3 BITS_PER_SAMPLE 4 6 SAMPLE_BASE_DIVISOR 8 10 SAMPLE_BASE_MULTIPLE 11 13 SAMPLE_BASE_RATE 14 14 STREAM_TYPE 15 15 ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID 2 0x3 2 0 4294967295 CHANNEL_ID 0 3 STREAM_ID 4 7 ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER 2 0x4 10 0 4294967295 DIGEN 0 0 V 1 1 VCFG 2 2 PRE 3 3 COPY 4 4 NON_AUDIO 5 5 PRO 6 6 L 7 7 CC 8 14 KEEPALIVE 23 23 ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS 2 0x5 1 0 4294967295 STREAM_FORMATS 0 31 ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 2 0x6 2 0 4294967295 AUDIO_RATE_CAPABILITIES 0 11 AUDIO_BIT_CAPABILITIES 16 20 ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL 2 0x7 2 0 4294967295 STRIPE_CONTROL 0 1 STRIPE_CAPABILITY 20 22 ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE 2 0x8 1 0 4294967295 RAMP_RATE 0 7 ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING 2 0x9 4 0 4294967295 PRESENTATION_TIME_EMBEDDING_ENABLE 0 0 PRESENTATION_TIME_OFFSET_CHANGED 1 1 CLEAR_GTC_COUNTER_MIN_MAX_DELTA 2 2 PRESENTATION_TIME_EMBEDDING_GROUP 4 6 ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA 2 0xc 1 0 4294967295 GTC_COUNTER_DELTA 0 31 ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN 2 0xd 1 0 4294967295 GTC_COUNTER_DELTA_MIN 0 31 ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX 2 0xe 1 0 4294967295 GTC_COUNTER_DELTA_MAX 0 31 ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 2 0x20 13 0 4294967295 AUDIO_CHANNEL_CAPABILITIES 0 0 INPUT_AMPLIFIER_PRESENT 1 1 OUTPUT_AMPLIFIER_PRESENT 2 2 AMPLIFIER_PARAMETER_OVERRIDE 3 3 STRIPE 5 5 PROCESSING_WIDGET 6 6 UNSOLICITED_RESPONSE_CAPABILITY 7 7 CONNECTION_LIST 8 8 DIGITAL 9 9 POWER_CONTROL 10 10 LR_SWAP 11 11 AUDIO_WIDGET_CAPABILITIES_DELAY 16 19 TYPE 20 23 ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES 2 0x21 11 0 4294967295 IMPEDANCE_SENSE_CAPABLE 0 0 TRIGGER_REQUIRED 1 1 JACK_DETECTION_CAPABILITY 2 2 HEADPHONE_DRIVE_CAPABLE 3 3 OUTPUT_CAPABLE 4 4 INPUT_CAPABLE 5 5 BALANCED_I_O_PINS 6 6 HDMI 7 7 VREF_CONTROL 8 15 EAPD_CAPABLE 16 16 DP 24 24 ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE 2 0x22 2 0 4294967295 TAG 0 5 ENABLE 7 7 ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE 2 0x23 1 0 4294967295 IMPEDANCE_SENSE 0 30 ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL 2 0x24 1 0 4294967295 OUT_ENABLE 6 6 ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER 2 0x25 8 0 4294967295 SPEAKER_ALLOCATION 0 6 CHANNEL_ALLOCATION 8 15 HDMI_CONNECTION 16 16 DP_CONNECTION 17 17 EXTRA_CONNECTION_INFO 18 23 LFE_PLAYBACK_LEVEL 24 25 LEVEL_SHIFT 27 30 DOWN_MIX_INHIBIT 31 31 ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 2 0x28 4 0 4294967295 MAX_CHANNELS 0 2 SUPPORTED_FREQUENCIES 8 15 DESCRIPTOR_BYTE_2 16 23 SUPPORTED_FREQUENCIES_STEREO 24 31 ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 2 0x29 3 0 4294967295 MAX_CHANNELS 0 2 SUPPORTED_FREQUENCIES 8 15 DESCRIPTOR_BYTE_2 16 23 ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 2 0x2a 3 0 4294967295 MAX_CHANNELS 0 2 SUPPORTED_FREQUENCIES 8 15 DESCRIPTOR_BYTE_2 16 23 ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 2 0x2b 3 0 4294967295 MAX_CHANNELS 0 2 SUPPORTED_FREQUENCIES 8 15 DESCRIPTOR_BYTE_2 16 23 ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 2 0x2c 3 0 4294967295 MAX_CHANNELS 0 2 SUPPORTED_FREQUENCIES 8 15 DESCRIPTOR_BYTE_2 16 23 ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 2 0x2d 3 0 4294967295 MAX_CHANNELS 0 2 SUPPORTED_FREQUENCIES 8 15 DESCRIPTOR_BYTE_2 16 23 ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 2 0x2e 3 0 4294967295 MAX_CHANNELS 0 2 SUPPORTED_FREQUENCIES 8 15 DESCRIPTOR_BYTE_2 16 23 ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 2 0x2f 3 0 4294967295 MAX_CHANNELS 0 2 SUPPORTED_FREQUENCIES 8 15 DESCRIPTOR_BYTE_2 16 23 ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 2 0x30 3 0 4294967295 MAX_CHANNELS 0 2 SUPPORTED_FREQUENCIES 8 15 DESCRIPTOR_BYTE_2 16 23 ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 2 0x31 3 0 4294967295 MAX_CHANNELS 0 2 SUPPORTED_FREQUENCIES 8 15 DESCRIPTOR_BYTE_2 16 23 ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 2 0x32 3 0 4294967295 MAX_CHANNELS 0 2 SUPPORTED_FREQUENCIES 8 15 DESCRIPTOR_BYTE_2 16 23 ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 2 0x33 3 0 4294967295 MAX_CHANNELS 0 2 SUPPORTED_FREQUENCIES 8 15 DESCRIPTOR_BYTE_2 16 23 ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 2 0x34 3 0 4294967295 MAX_CHANNELS 0 2 SUPPORTED_FREQUENCIES 8 15 DESCRIPTOR_BYTE_2 16 23 ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 2 0x35 3 0 4294967295 MAX_CHANNELS 0 2 SUPPORTED_FREQUENCIES 8 15 DESCRIPTOR_BYTE_2 16 23 ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE 2 0x36 12 0 4294967295 MULTICHANNEL01_ENABLE 0 0 MULTICHANNEL01_MUTE 1 1 MULTICHANNEL01_CHANNEL_ID 4 7 MULTICHANNEL23_ENABLE 8 8 MULTICHANNEL23_MUTE 9 9 MULTICHANNEL23_CHANNEL_ID 12 15 MULTICHANNEL45_ENABLE 16 16 MULTICHANNEL45_MUTE 17 17 MULTICHANNEL45_CHANNEL_ID 20 23 MULTICHANNEL67_ENABLE 24 24 MULTICHANNEL67_MUTE 25 25 MULTICHANNEL67_CHANNEL_ID 28 31 ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC 2 0x37 2 0 4294967295 VIDEO_LIPSYNC 0 7 AUDIO_LIPSYNC 8 15 ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR 2 0x38 2 0 4294967295 HBR_CAPABLE 0 0 HBR_ENABLE 4 4 ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0 2 0x3a 2 0 4294967295 MANUFACTURER_ID 0 15 PRODUCT_ID 16 31 ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1 2 0x3b 1 0 4294967295 SINK_DESCRIPTION_LEN 0 7 ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2 2 0x3c 1 0 4294967295 PORT_ID0 0 31 ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3 2 0x3d 1 0 4294967295 PORT_ID1 0 31 ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4 2 0x3e 4 0 4294967295 DESCRIPTION0 0 7 DESCRIPTION1 8 15 DESCRIPTION2 16 23 DESCRIPTION3 24 31 ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5 2 0x3f 4 0 4294967295 DESCRIPTION4 0 7 DESCRIPTION5 8 15 DESCRIPTION6 16 23 DESCRIPTION7 24 31 ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6 2 0x40 4 0 4294967295 DESCRIPTION8 0 7 DESCRIPTION9 8 15 DESCRIPTION10 16 23 DESCRIPTION11 24 31 ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7 2 0x41 4 0 4294967295 DESCRIPTION12 0 7 DESCRIPTION13 8 15 DESCRIPTION14 16 23 DESCRIPTION15 24 31 ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8 2 0x42 2 0 4294967295 DESCRIPTION16 0 7 DESCRIPTION17 8 15 ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL 2 0x54 3 0 4294967295 CLOCK_GATING_DISABLE 0 0 CLOCK_ON_STATE 4 4 AUDIO_ENABLED 31 31 ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 2 0x55 2 0 4294967295 UNSOLICITED_RESPONSE_PAYLOAD 0 25 UNSOLICITED_RESPONSE_FORCE 28 28 ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 2 0x56 8 0 4294967295 SEQUENCE 0 3 DEFAULT_ASSOCIATION 4 7 MISC 8 11 COLOR 12 15 CONNECTION_TYPE 16 19 DEFAULT_DEVICE 20 23 LOCATION 24 29 PORT_CONNECTIVITY 30 31 ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2 2 0x57 12 0 4294967295 MULTICHANNEL1_ENABLE 0 0 MULTICHANNEL1_MUTE 1 1 MULTICHANNEL1_CHANNEL_ID 4 7 MULTICHANNEL3_ENABLE 8 8 MULTICHANNEL3_MUTE 9 9 MULTICHANNEL3_CHANNEL_ID 12 15 MULTICHANNEL5_ENABLE 16 16 MULTICHANNEL5_MUTE 17 17 MULTICHANNEL5_CHANNEL_ID 20 23 MULTICHANNEL7_ENABLE 24 24 MULTICHANNEL7_MUTE 25 25 MULTICHANNEL7_CHANNEL_ID 28 31 ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE 2 0x58 1 0 4294967295 MULTICHANNEL_MODE 0 0 ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0 2 0x59 2 0 4294967295 IEC_60958_CS_MODE 0 1 IEC_60958_CS_SOURCE_NUMBER 2 5 ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1 2 0x5a 4 0 4294967295 IEC_60958_CS_CLOCK_ACCURACY 0 1 IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN 2 2 IEC_60958_CS_WORD_LENGTH 3 6 IEC_60958_CS_WORD_LENGTH_OVRRD_EN 7 7 ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2 2 0x5b 2 0 4294967295 IEC_60958_CS_SAMPLING_FREQUENCY 0 5 IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN 6 6 ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3 2 0x5c 2 0 4294967295 IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY 0 3 IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN 4 4 ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4 2 0x5d 4 0 4294967295 IEC_60958_CS_SAMPLING_FREQUENCY_COEFF 0 3 IEC_60958_CS_MPEG_SURROUND_INFO 4 4 IEC_60958_CS_CGMS_A 5 6 IEC_60958_CS_CGMS_A_VALID 7 7 ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5 2 0x5e 2 0 4294967295 IEC_60958_CS_CHANNEL_NUMBER_L 0 3 IEC_60958_CS_CHANNEL_NUMBER_R 4 7 ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6 2 0x5f 2 0 4294967295 IEC_60958_CS_CHANNEL_NUMBER_2 0 3 IEC_60958_CS_CHANNEL_NUMBER_3 4 7 ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7 2 0x60 2 0 4294967295 IEC_60958_CS_CHANNEL_NUMBER_4 0 3 IEC_60958_CS_CHANNEL_NUMBER_5 4 7 ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8 2 0x61 2 0 4294967295 IEC_60958_CS_CHANNEL_NUMBER_6 0 3 IEC_60958_CS_CHANNEL_NUMBER_7 4 7 ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO 2 0x62 1 0 4294967295 ASSOCIATION_INFO 0 31 ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS 2 0x63 1 0 4294967295 OUTPUT_ACTIVE 0 0 ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 2 0x64 2 0 4294967295 LPIB_SNAPSHOT_LOCK 0 0 CYCLIC_BUFFER_WRAP_COUNT 8 15 ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB 2 0x65 1 0 4294967295 LPIB 0 31 ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 2 0x66 1 0 4294967295 LPIB_TIMER_SNAPSHOT 0 31 ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE 2 0x67 1 0 4294967295 CODING_TYPE 0 7 ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED 2 0x68 4 0 4294967295 FORMAT_CHANGED 0 0 FORMAT_CHANGED_ACK_UR_ENABLE 1 1 FORMAT_CHANGE_REASON 8 15 FORMAT_CHANGE_RESPONSE 16 23 ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION 2 0x69 1 0 4294967295 WIRELESS_DISPLAY_IDENTIFICATION 0 1 ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE 2 0x6a 2 0 4294967295 REMOTE_KEEP_ALIVE_ENABLE 0 0 REMOTE_KEEP_ALIVE_CAPABILITY 4 4 ixAZF0ENDPOINT1_AZALIA_F0_AUDIO_ENABLE_STATUS 2 0x6b 1 0 4294967295 AUDIO_ENABLE_STATUS 0 0 ixAZF0ENDPOINT1_AZALIA_F0_AUDIO_ENABLED_INT_STATUS 2 0x6c 3 0 4294967295 AUDIO_ENABLED_FLAG 0 0 AUDIO_ENABLED_MASK 4 4 AUDIO_ENABLED_TYPE 8 8 ixAZF0ENDPOINT1_AZALIA_F0_AUDIO_DISABLED_INT_STATUS 2 0x6d 3 0 4294967295 AUDIO_DISABLED_FLAG 0 0 AUDIO_DISABLED_MASK 4 4 AUDIO_DISABLED_TYPE 8 8 ixAZF0ENDPOINT1_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS 2 0x6e 3 0 4294967295 AUDIO_FORMAT_CHANGED_FLAG 0 0 AUDIO_FORMAT_CHANGED_MASK 4 4 AUDIO_FORMAT_CHANGED_TYPE 8 8 ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 2 0x1 14 0 4294967295 AUDIO_CHANNEL_CAPABILITIES 0 0 INPUT_AMPLIFIER_PRESENT 1 1 OUTPUT_AMPLIFIER_PRESENT 2 2 AMPLIFIER_PARAMETER_OVERRIDE 3 3 FORMAT_OVERRIDE 4 4 STRIPE 5 5 PROCESSING_WIDGET 6 6 UNSOLICITED_RESPONSE_CAPABILITY 7 7 CONNECTION_LIST 8 8 DIGITAL 9 9 POWER_CONTROL 10 10 LR_SWAP 11 11 AUDIO_WIDGET_CAPABILITIES_DELAY 16 19 TYPE 20 23 ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT 2 0x2 6 0 4294967295 NUMBER_OF_CHANNELS 0 3 BITS_PER_SAMPLE 4 6 SAMPLE_BASE_DIVISOR 8 10 SAMPLE_BASE_MULTIPLE 11 13 SAMPLE_BASE_RATE 14 14 STREAM_TYPE 15 15 ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID 2 0x3 2 0 4294967295 CHANNEL_ID 0 3 STREAM_ID 4 7 ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER 2 0x4 10 0 4294967295 DIGEN 0 0 V 1 1 VCFG 2 2 PRE 3 3 COPY 4 4 NON_AUDIO 5 5 PRO 6 6 L 7 7 CC 8 14 KEEPALIVE 23 23 ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS 2 0x5 1 0 4294967295 STREAM_FORMATS 0 31 ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 2 0x6 2 0 4294967295 AUDIO_RATE_CAPABILITIES 0 11 AUDIO_BIT_CAPABILITIES 16 20 ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL 2 0x7 2 0 4294967295 STRIPE_CONTROL 0 1 STRIPE_CAPABILITY 20 22 ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE 2 0x8 1 0 4294967295 RAMP_RATE 0 7 ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING 2 0x9 4 0 4294967295 PRESENTATION_TIME_EMBEDDING_ENABLE 0 0 PRESENTATION_TIME_OFFSET_CHANGED 1 1 CLEAR_GTC_COUNTER_MIN_MAX_DELTA 2 2 PRESENTATION_TIME_EMBEDDING_GROUP 4 6 ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA 2 0xc 1 0 4294967295 GTC_COUNTER_DELTA 0 31 ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN 2 0xd 1 0 4294967295 GTC_COUNTER_DELTA_MIN 0 31 ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX 2 0xe 1 0 4294967295 GTC_COUNTER_DELTA_MAX 0 31 ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 2 0x20 13 0 4294967295 AUDIO_CHANNEL_CAPABILITIES 0 0 INPUT_AMPLIFIER_PRESENT 1 1 OUTPUT_AMPLIFIER_PRESENT 2 2 AMPLIFIER_PARAMETER_OVERRIDE 3 3 STRIPE 5 5 PROCESSING_WIDGET 6 6 UNSOLICITED_RESPONSE_CAPABILITY 7 7 CONNECTION_LIST 8 8 DIGITAL 9 9 POWER_CONTROL 10 10 LR_SWAP 11 11 AUDIO_WIDGET_CAPABILITIES_DELAY 16 19 TYPE 20 23 ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES 2 0x21 11 0 4294967295 IMPEDANCE_SENSE_CAPABLE 0 0 TRIGGER_REQUIRED 1 1 JACK_DETECTION_CAPABILITY 2 2 HEADPHONE_DRIVE_CAPABLE 3 3 OUTPUT_CAPABLE 4 4 INPUT_CAPABLE 5 5 BALANCED_I_O_PINS 6 6 HDMI 7 7 VREF_CONTROL 8 15 EAPD_CAPABLE 16 16 DP 24 24 ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE 2 0x22 2 0 4294967295 TAG 0 5 ENABLE 7 7 ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE 2 0x23 1 0 4294967295 IMPEDANCE_SENSE 0 30 ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL 2 0x24 1 0 4294967295 OUT_ENABLE 6 6 ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER 2 0x25 8 0 4294967295 SPEAKER_ALLOCATION 0 6 CHANNEL_ALLOCATION 8 15 HDMI_CONNECTION 16 16 DP_CONNECTION 17 17 EXTRA_CONNECTION_INFO 18 23 LFE_PLAYBACK_LEVEL 24 25 LEVEL_SHIFT 27 30 DOWN_MIX_INHIBIT 31 31 ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 2 0x28 4 0 4294967295 MAX_CHANNELS 0 2 SUPPORTED_FREQUENCIES 8 15 DESCRIPTOR_BYTE_2 16 23 SUPPORTED_FREQUENCIES_STEREO 24 31 ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 2 0x29 3 0 4294967295 MAX_CHANNELS 0 2 SUPPORTED_FREQUENCIES 8 15 DESCRIPTOR_BYTE_2 16 23 ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 2 0x2a 3 0 4294967295 MAX_CHANNELS 0 2 SUPPORTED_FREQUENCIES 8 15 DESCRIPTOR_BYTE_2 16 23 ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 2 0x2b 3 0 4294967295 MAX_CHANNELS 0 2 SUPPORTED_FREQUENCIES 8 15 DESCRIPTOR_BYTE_2 16 23 ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 2 0x2c 3 0 4294967295 MAX_CHANNELS 0 2 SUPPORTED_FREQUENCIES 8 15 DESCRIPTOR_BYTE_2 16 23 ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 2 0x2d 3 0 4294967295 MAX_CHANNELS 0 2 SUPPORTED_FREQUENCIES 8 15 DESCRIPTOR_BYTE_2 16 23 ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 2 0x2e 3 0 4294967295 MAX_CHANNELS 0 2 SUPPORTED_FREQUENCIES 8 15 DESCRIPTOR_BYTE_2 16 23 ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 2 0x2f 3 0 4294967295 MAX_CHANNELS 0 2 SUPPORTED_FREQUENCIES 8 15 DESCRIPTOR_BYTE_2 16 23 ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 2 0x30 3 0 4294967295 MAX_CHANNELS 0 2 SUPPORTED_FREQUENCIES 8 15 DESCRIPTOR_BYTE_2 16 23 ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 2 0x31 3 0 4294967295 MAX_CHANNELS 0 2 SUPPORTED_FREQUENCIES 8 15 DESCRIPTOR_BYTE_2 16 23 ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 2 0x32 3 0 4294967295 MAX_CHANNELS 0 2 SUPPORTED_FREQUENCIES 8 15 DESCRIPTOR_BYTE_2 16 23 ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 2 0x33 3 0 4294967295 MAX_CHANNELS 0 2 SUPPORTED_FREQUENCIES 8 15 DESCRIPTOR_BYTE_2 16 23 ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 2 0x34 3 0 4294967295 MAX_CHANNELS 0 2 SUPPORTED_FREQUENCIES 8 15 DESCRIPTOR_BYTE_2 16 23 ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 2 0x35 3 0 4294967295 MAX_CHANNELS 0 2 SUPPORTED_FREQUENCIES 8 15 DESCRIPTOR_BYTE_2 16 23 ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE 2 0x36 12 0 4294967295 MULTICHANNEL01_ENABLE 0 0 MULTICHANNEL01_MUTE 1 1 MULTICHANNEL01_CHANNEL_ID 4 7 MULTICHANNEL23_ENABLE 8 8 MULTICHANNEL23_MUTE 9 9 MULTICHANNEL23_CHANNEL_ID 12 15 MULTICHANNEL45_ENABLE 16 16 MULTICHANNEL45_MUTE 17 17 MULTICHANNEL45_CHANNEL_ID 20 23 MULTICHANNEL67_ENABLE 24 24 MULTICHANNEL67_MUTE 25 25 MULTICHANNEL67_CHANNEL_ID 28 31 ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC 2 0x37 2 0 4294967295 VIDEO_LIPSYNC 0 7 AUDIO_LIPSYNC 8 15 ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR 2 0x38 2 0 4294967295 HBR_CAPABLE 0 0 HBR_ENABLE 4 4 ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0 2 0x3a 2 0 4294967295 MANUFACTURER_ID 0 15 PRODUCT_ID 16 31 ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1 2 0x3b 1 0 4294967295 SINK_DESCRIPTION_LEN 0 7 ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2 2 0x3c 1 0 4294967295 PORT_ID0 0 31 ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3 2 0x3d 1 0 4294967295 PORT_ID1 0 31 ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4 2 0x3e 4 0 4294967295 DESCRIPTION0 0 7 DESCRIPTION1 8 15 DESCRIPTION2 16 23 DESCRIPTION3 24 31 ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5 2 0x3f 4 0 4294967295 DESCRIPTION4 0 7 DESCRIPTION5 8 15 DESCRIPTION6 16 23 DESCRIPTION7 24 31 ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6 2 0x40 4 0 4294967295 DESCRIPTION8 0 7 DESCRIPTION9 8 15 DESCRIPTION10 16 23 DESCRIPTION11 24 31 ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7 2 0x41 4 0 4294967295 DESCRIPTION12 0 7 DESCRIPTION13 8 15 DESCRIPTION14 16 23 DESCRIPTION15 24 31 ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8 2 0x42 2 0 4294967295 DESCRIPTION16 0 7 DESCRIPTION17 8 15 ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL 2 0x54 3 0 4294967295 CLOCK_GATING_DISABLE 0 0 CLOCK_ON_STATE 4 4 AUDIO_ENABLED 31 31 ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 2 0x55 2 0 4294967295 UNSOLICITED_RESPONSE_PAYLOAD 0 25 UNSOLICITED_RESPONSE_FORCE 28 28 ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 2 0x56 8 0 4294967295 SEQUENCE 0 3 DEFAULT_ASSOCIATION 4 7 MISC 8 11 COLOR 12 15 CONNECTION_TYPE 16 19 DEFAULT_DEVICE 20 23 LOCATION 24 29 PORT_CONNECTIVITY 30 31 ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2 2 0x57 12 0 4294967295 MULTICHANNEL1_ENABLE 0 0 MULTICHANNEL1_MUTE 1 1 MULTICHANNEL1_CHANNEL_ID 4 7 MULTICHANNEL3_ENABLE 8 8 MULTICHANNEL3_MUTE 9 9 MULTICHANNEL3_CHANNEL_ID 12 15 MULTICHANNEL5_ENABLE 16 16 MULTICHANNEL5_MUTE 17 17 MULTICHANNEL5_CHANNEL_ID 20 23 MULTICHANNEL7_ENABLE 24 24 MULTICHANNEL7_MUTE 25 25 MULTICHANNEL7_CHANNEL_ID 28 31 ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE 2 0x58 1 0 4294967295 MULTICHANNEL_MODE 0 0 ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0 2 0x59 2 0 4294967295 IEC_60958_CS_MODE 0 1 IEC_60958_CS_SOURCE_NUMBER 2 5 ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1 2 0x5a 4 0 4294967295 IEC_60958_CS_CLOCK_ACCURACY 0 1 IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN 2 2 IEC_60958_CS_WORD_LENGTH 3 6 IEC_60958_CS_WORD_LENGTH_OVRRD_EN 7 7 ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2 2 0x5b 2 0 4294967295 IEC_60958_CS_SAMPLING_FREQUENCY 0 5 IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN 6 6 ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3 2 0x5c 2 0 4294967295 IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY 0 3 IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN 4 4 ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4 2 0x5d 4 0 4294967295 IEC_60958_CS_SAMPLING_FREQUENCY_COEFF 0 3 IEC_60958_CS_MPEG_SURROUND_INFO 4 4 IEC_60958_CS_CGMS_A 5 6 IEC_60958_CS_CGMS_A_VALID 7 7 ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5 2 0x5e 2 0 4294967295 IEC_60958_CS_CHANNEL_NUMBER_L 0 3 IEC_60958_CS_CHANNEL_NUMBER_R 4 7 ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6 2 0x5f 2 0 4294967295 IEC_60958_CS_CHANNEL_NUMBER_2 0 3 IEC_60958_CS_CHANNEL_NUMBER_3 4 7 ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7 2 0x60 2 0 4294967295 IEC_60958_CS_CHANNEL_NUMBER_4 0 3 IEC_60958_CS_CHANNEL_NUMBER_5 4 7 ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8 2 0x61 2 0 4294967295 IEC_60958_CS_CHANNEL_NUMBER_6 0 3 IEC_60958_CS_CHANNEL_NUMBER_7 4 7 ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO 2 0x62 1 0 4294967295 ASSOCIATION_INFO 0 31 ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS 2 0x63 1 0 4294967295 OUTPUT_ACTIVE 0 0 ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 2 0x64 2 0 4294967295 LPIB_SNAPSHOT_LOCK 0 0 CYCLIC_BUFFER_WRAP_COUNT 8 15 ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB 2 0x65 1 0 4294967295 LPIB 0 31 ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 2 0x66 1 0 4294967295 LPIB_TIMER_SNAPSHOT 0 31 ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE 2 0x67 1 0 4294967295 CODING_TYPE 0 7 ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED 2 0x68 4 0 4294967295 FORMAT_CHANGED 0 0 FORMAT_CHANGED_ACK_UR_ENABLE 1 1 FORMAT_CHANGE_REASON 8 15 FORMAT_CHANGE_RESPONSE 16 23 ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION 2 0x69 1 0 4294967295 WIRELESS_DISPLAY_IDENTIFICATION 0 1 ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE 2 0x6a 2 0 4294967295 REMOTE_KEEP_ALIVE_ENABLE 0 0 REMOTE_KEEP_ALIVE_CAPABILITY 4 4 ixAZF0ENDPOINT2_AZALIA_F0_AUDIO_ENABLE_STATUS 2 0x6b 1 0 4294967295 AUDIO_ENABLE_STATUS 0 0 ixAZF0ENDPOINT2_AZALIA_F0_AUDIO_ENABLED_INT_STATUS 2 0x6c 3 0 4294967295 AUDIO_ENABLED_FLAG 0 0 AUDIO_ENABLED_MASK 4 4 AUDIO_ENABLED_TYPE 8 8 ixAZF0ENDPOINT2_AZALIA_F0_AUDIO_DISABLED_INT_STATUS 2 0x6d 3 0 4294967295 AUDIO_DISABLED_FLAG 0 0 AUDIO_DISABLED_MASK 4 4 AUDIO_DISABLED_TYPE 8 8 ixAZF0ENDPOINT2_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS 2 0x6e 3 0 4294967295 AUDIO_FORMAT_CHANGED_FLAG 0 0 AUDIO_FORMAT_CHANGED_MASK 4 4 AUDIO_FORMAT_CHANGED_TYPE 8 8 ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 2 0x1 14 0 4294967295 AUDIO_CHANNEL_CAPABILITIES 0 0 INPUT_AMPLIFIER_PRESENT 1 1 OUTPUT_AMPLIFIER_PRESENT 2 2 AMPLIFIER_PARAMETER_OVERRIDE 3 3 FORMAT_OVERRIDE 4 4 STRIPE 5 5 PROCESSING_WIDGET 6 6 UNSOLICITED_RESPONSE_CAPABILITY 7 7 CONNECTION_LIST 8 8 DIGITAL 9 9 POWER_CONTROL 10 10 LR_SWAP 11 11 AUDIO_WIDGET_CAPABILITIES_DELAY 16 19 TYPE 20 23 ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT 2 0x2 6 0 4294967295 NUMBER_OF_CHANNELS 0 3 BITS_PER_SAMPLE 4 6 SAMPLE_BASE_DIVISOR 8 10 SAMPLE_BASE_MULTIPLE 11 13 SAMPLE_BASE_RATE 14 14 STREAM_TYPE 15 15 ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID 2 0x3 2 0 4294967295 CHANNEL_ID 0 3 STREAM_ID 4 7 ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER 2 0x4 10 0 4294967295 DIGEN 0 0 V 1 1 VCFG 2 2 PRE 3 3 COPY 4 4 NON_AUDIO 5 5 PRO 6 6 L 7 7 CC 8 14 KEEPALIVE 23 23 ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS 2 0x5 1 0 4294967295 STREAM_FORMATS 0 31 ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 2 0x6 2 0 4294967295 AUDIO_RATE_CAPABILITIES 0 11 AUDIO_BIT_CAPABILITIES 16 20 ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL 2 0x7 2 0 4294967295 STRIPE_CONTROL 0 1 STRIPE_CAPABILITY 20 22 ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE 2 0x8 1 0 4294967295 RAMP_RATE 0 7 ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING 2 0x9 4 0 4294967295 PRESENTATION_TIME_EMBEDDING_ENABLE 0 0 PRESENTATION_TIME_OFFSET_CHANGED 1 1 CLEAR_GTC_COUNTER_MIN_MAX_DELTA 2 2 PRESENTATION_TIME_EMBEDDING_GROUP 4 6 ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA 2 0xc 1 0 4294967295 GTC_COUNTER_DELTA 0 31 ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN 2 0xd 1 0 4294967295 GTC_COUNTER_DELTA_MIN 0 31 ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX 2 0xe 1 0 4294967295 GTC_COUNTER_DELTA_MAX 0 31 ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 2 0x20 13 0 4294967295 AUDIO_CHANNEL_CAPABILITIES 0 0 INPUT_AMPLIFIER_PRESENT 1 1 OUTPUT_AMPLIFIER_PRESENT 2 2 AMPLIFIER_PARAMETER_OVERRIDE 3 3 STRIPE 5 5 PROCESSING_WIDGET 6 6 UNSOLICITED_RESPONSE_CAPABILITY 7 7 CONNECTION_LIST 8 8 DIGITAL 9 9 POWER_CONTROL 10 10 LR_SWAP 11 11 AUDIO_WIDGET_CAPABILITIES_DELAY 16 19 TYPE 20 23 ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES 2 0x21 11 0 4294967295 IMPEDANCE_SENSE_CAPABLE 0 0 TRIGGER_REQUIRED 1 1 JACK_DETECTION_CAPABILITY 2 2 HEADPHONE_DRIVE_CAPABLE 3 3 OUTPUT_CAPABLE 4 4 INPUT_CAPABLE 5 5 BALANCED_I_O_PINS 6 6 HDMI 7 7 VREF_CONTROL 8 15 EAPD_CAPABLE 16 16 DP 24 24 ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE 2 0x22 2 0 4294967295 TAG 0 5 ENABLE 7 7 ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE 2 0x23 1 0 4294967295 IMPEDANCE_SENSE 0 30 ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL 2 0x24 1 0 4294967295 OUT_ENABLE 6 6 ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER 2 0x25 8 0 4294967295 SPEAKER_ALLOCATION 0 6 CHANNEL_ALLOCATION 8 15 HDMI_CONNECTION 16 16 DP_CONNECTION 17 17 EXTRA_CONNECTION_INFO 18 23 LFE_PLAYBACK_LEVEL 24 25 LEVEL_SHIFT 27 30 DOWN_MIX_INHIBIT 31 31 ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 2 0x28 4 0 4294967295 MAX_CHANNELS 0 2 SUPPORTED_FREQUENCIES 8 15 DESCRIPTOR_BYTE_2 16 23 SUPPORTED_FREQUENCIES_STEREO 24 31 ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 2 0x29 3 0 4294967295 MAX_CHANNELS 0 2 SUPPORTED_FREQUENCIES 8 15 DESCRIPTOR_BYTE_2 16 23 ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 2 0x2a 3 0 4294967295 MAX_CHANNELS 0 2 SUPPORTED_FREQUENCIES 8 15 DESCRIPTOR_BYTE_2 16 23 ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 2 0x2b 3 0 4294967295 MAX_CHANNELS 0 2 SUPPORTED_FREQUENCIES 8 15 DESCRIPTOR_BYTE_2 16 23 ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 2 0x2c 3 0 4294967295 MAX_CHANNELS 0 2 SUPPORTED_FREQUENCIES 8 15 DESCRIPTOR_BYTE_2 16 23 ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 2 0x2d 3 0 4294967295 MAX_CHANNELS 0 2 SUPPORTED_FREQUENCIES 8 15 DESCRIPTOR_BYTE_2 16 23 ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 2 0x2e 3 0 4294967295 MAX_CHANNELS 0 2 SUPPORTED_FREQUENCIES 8 15 DESCRIPTOR_BYTE_2 16 23 ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 2 0x2f 3 0 4294967295 MAX_CHANNELS 0 2 SUPPORTED_FREQUENCIES 8 15 DESCRIPTOR_BYTE_2 16 23 ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 2 0x30 3 0 4294967295 MAX_CHANNELS 0 2 SUPPORTED_FREQUENCIES 8 15 DESCRIPTOR_BYTE_2 16 23 ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 2 0x31 3 0 4294967295 MAX_CHANNELS 0 2 SUPPORTED_FREQUENCIES 8 15 DESCRIPTOR_BYTE_2 16 23 ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 2 0x32 3 0 4294967295 MAX_CHANNELS 0 2 SUPPORTED_FREQUENCIES 8 15 DESCRIPTOR_BYTE_2 16 23 ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 2 0x33 3 0 4294967295 MAX_CHANNELS 0 2 SUPPORTED_FREQUENCIES 8 15 DESCRIPTOR_BYTE_2 16 23 ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 2 0x34 3 0 4294967295 MAX_CHANNELS 0 2 SUPPORTED_FREQUENCIES 8 15 DESCRIPTOR_BYTE_2 16 23 ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 2 0x35 3 0 4294967295 MAX_CHANNELS 0 2 SUPPORTED_FREQUENCIES 8 15 DESCRIPTOR_BYTE_2 16 23 ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE 2 0x36 12 0 4294967295 MULTICHANNEL01_ENABLE 0 0 MULTICHANNEL01_MUTE 1 1 MULTICHANNEL01_CHANNEL_ID 4 7 MULTICHANNEL23_ENABLE 8 8 MULTICHANNEL23_MUTE 9 9 MULTICHANNEL23_CHANNEL_ID 12 15 MULTICHANNEL45_ENABLE 16 16 MULTICHANNEL45_MUTE 17 17 MULTICHANNEL45_CHANNEL_ID 20 23 MULTICHANNEL67_ENABLE 24 24 MULTICHANNEL67_MUTE 25 25 MULTICHANNEL67_CHANNEL_ID 28 31 ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC 2 0x37 2 0 4294967295 VIDEO_LIPSYNC 0 7 AUDIO_LIPSYNC 8 15 ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR 2 0x38 2 0 4294967295 HBR_CAPABLE 0 0 HBR_ENABLE 4 4 ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0 2 0x3a 2 0 4294967295 MANUFACTURER_ID 0 15 PRODUCT_ID 16 31 ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1 2 0x3b 1 0 4294967295 SINK_DESCRIPTION_LEN 0 7 ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2 2 0x3c 1 0 4294967295 PORT_ID0 0 31 ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3 2 0x3d 1 0 4294967295 PORT_ID1 0 31 ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4 2 0x3e 4 0 4294967295 DESCRIPTION0 0 7 DESCRIPTION1 8 15 DESCRIPTION2 16 23 DESCRIPTION3 24 31 ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5 2 0x3f 4 0 4294967295 DESCRIPTION4 0 7 DESCRIPTION5 8 15 DESCRIPTION6 16 23 DESCRIPTION7 24 31 ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6 2 0x40 4 0 4294967295 DESCRIPTION8 0 7 DESCRIPTION9 8 15 DESCRIPTION10 16 23 DESCRIPTION11 24 31 ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7 2 0x41 4 0 4294967295 DESCRIPTION12 0 7 DESCRIPTION13 8 15 DESCRIPTION14 16 23 DESCRIPTION15 24 31 ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8 2 0x42 2 0 4294967295 DESCRIPTION16 0 7 DESCRIPTION17 8 15 ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL 2 0x54 3 0 4294967295 CLOCK_GATING_DISABLE 0 0 CLOCK_ON_STATE 4 4 AUDIO_ENABLED 31 31 ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 2 0x55 2 0 4294967295 UNSOLICITED_RESPONSE_PAYLOAD 0 25 UNSOLICITED_RESPONSE_FORCE 28 28 ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 2 0x56 8 0 4294967295 SEQUENCE 0 3 DEFAULT_ASSOCIATION 4 7 MISC 8 11 COLOR 12 15 CONNECTION_TYPE 16 19 DEFAULT_DEVICE 20 23 LOCATION 24 29 PORT_CONNECTIVITY 30 31 ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2 2 0x57 12 0 4294967295 MULTICHANNEL1_ENABLE 0 0 MULTICHANNEL1_MUTE 1 1 MULTICHANNEL1_CHANNEL_ID 4 7 MULTICHANNEL3_ENABLE 8 8 MULTICHANNEL3_MUTE 9 9 MULTICHANNEL3_CHANNEL_ID 12 15 MULTICHANNEL5_ENABLE 16 16 MULTICHANNEL5_MUTE 17 17 MULTICHANNEL5_CHANNEL_ID 20 23 MULTICHANNEL7_ENABLE 24 24 MULTICHANNEL7_MUTE 25 25 MULTICHANNEL7_CHANNEL_ID 28 31 ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE 2 0x58 1 0 4294967295 MULTICHANNEL_MODE 0 0 ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0 2 0x59 2 0 4294967295 IEC_60958_CS_MODE 0 1 IEC_60958_CS_SOURCE_NUMBER 2 5 ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1 2 0x5a 4 0 4294967295 IEC_60958_CS_CLOCK_ACCURACY 0 1 IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN 2 2 IEC_60958_CS_WORD_LENGTH 3 6 IEC_60958_CS_WORD_LENGTH_OVRRD_EN 7 7 ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2 2 0x5b 2 0 4294967295 IEC_60958_CS_SAMPLING_FREQUENCY 0 5 IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN 6 6 ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3 2 0x5c 2 0 4294967295 IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY 0 3 IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN 4 4 ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4 2 0x5d 4 0 4294967295 IEC_60958_CS_SAMPLING_FREQUENCY_COEFF 0 3 IEC_60958_CS_MPEG_SURROUND_INFO 4 4 IEC_60958_CS_CGMS_A 5 6 IEC_60958_CS_CGMS_A_VALID 7 7 ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5 2 0x5e 2 0 4294967295 IEC_60958_CS_CHANNEL_NUMBER_L 0 3 IEC_60958_CS_CHANNEL_NUMBER_R 4 7 ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6 2 0x5f 2 0 4294967295 IEC_60958_CS_CHANNEL_NUMBER_2 0 3 IEC_60958_CS_CHANNEL_NUMBER_3 4 7 ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7 2 0x60 2 0 4294967295 IEC_60958_CS_CHANNEL_NUMBER_4 0 3 IEC_60958_CS_CHANNEL_NUMBER_5 4 7 ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8 2 0x61 2 0 4294967295 IEC_60958_CS_CHANNEL_NUMBER_6 0 3 IEC_60958_CS_CHANNEL_NUMBER_7 4 7 ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO 2 0x62 1 0 4294967295 ASSOCIATION_INFO 0 31 ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS 2 0x63 1 0 4294967295 OUTPUT_ACTIVE 0 0 ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 2 0x64 2 0 4294967295 LPIB_SNAPSHOT_LOCK 0 0 CYCLIC_BUFFER_WRAP_COUNT 8 15 ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB 2 0x65 1 0 4294967295 LPIB 0 31 ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 2 0x66 1 0 4294967295 LPIB_TIMER_SNAPSHOT 0 31 ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE 2 0x67 1 0 4294967295 CODING_TYPE 0 7 ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED 2 0x68 4 0 4294967295 FORMAT_CHANGED 0 0 FORMAT_CHANGED_ACK_UR_ENABLE 1 1 FORMAT_CHANGE_REASON 8 15 FORMAT_CHANGE_RESPONSE 16 23 ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION 2 0x69 1 0 4294967295 WIRELESS_DISPLAY_IDENTIFICATION 0 1 ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE 2 0x6a 2 0 4294967295 REMOTE_KEEP_ALIVE_ENABLE 0 0 REMOTE_KEEP_ALIVE_CAPABILITY 4 4 ixAZF0ENDPOINT3_AZALIA_F0_AUDIO_ENABLE_STATUS 2 0x6b 1 0 4294967295 AUDIO_ENABLE_STATUS 0 0 ixAZF0ENDPOINT3_AZALIA_F0_AUDIO_ENABLED_INT_STATUS 2 0x6c 3 0 4294967295 AUDIO_ENABLED_FLAG 0 0 AUDIO_ENABLED_MASK 4 4 AUDIO_ENABLED_TYPE 8 8 ixAZF0ENDPOINT3_AZALIA_F0_AUDIO_DISABLED_INT_STATUS 2 0x6d 3 0 4294967295 AUDIO_DISABLED_FLAG 0 0 AUDIO_DISABLED_MASK 4 4 AUDIO_DISABLED_TYPE 8 8 ixAZF0ENDPOINT3_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS 2 0x6e 3 0 4294967295 AUDIO_FORMAT_CHANGED_FLAG 0 0 AUDIO_FORMAT_CHANGED_MASK 4 4 AUDIO_FORMAT_CHANGED_TYPE 8 8 ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 2 0x1 14 0 4294967295 AUDIO_CHANNEL_CAPABILITIES 0 0 INPUT_AMPLIFIER_PRESENT 1 1 OUTPUT_AMPLIFIER_PRESENT 2 2 AMPLIFIER_PARAMETER_OVERRIDE 3 3 FORMAT_OVERRIDE 4 4 STRIPE 5 5 PROCESSING_WIDGET 6 6 UNSOLICITED_RESPONSE_CAPABILITY 7 7 CONNECTION_LIST 8 8 DIGITAL 9 9 POWER_CONTROL 10 10 LR_SWAP 11 11 AUDIO_WIDGET_CAPABILITIES_DELAY 16 19 TYPE 20 23 ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT 2 0x2 6 0 4294967295 NUMBER_OF_CHANNELS 0 3 BITS_PER_SAMPLE 4 6 SAMPLE_BASE_DIVISOR 8 10 SAMPLE_BASE_MULTIPLE 11 13 SAMPLE_BASE_RATE 14 14 STREAM_TYPE 15 15 ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID 2 0x3 2 0 4294967295 CHANNEL_ID 0 3 STREAM_ID 4 7 ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER 2 0x4 10 0 4294967295 DIGEN 0 0 V 1 1 VCFG 2 2 PRE 3 3 COPY 4 4 NON_AUDIO 5 5 PRO 6 6 L 7 7 CC 8 14 KEEPALIVE 23 23 ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS 2 0x5 1 0 4294967295 STREAM_FORMATS 0 31 ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 2 0x6 2 0 4294967295 AUDIO_RATE_CAPABILITIES 0 11 AUDIO_BIT_CAPABILITIES 16 20 ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL 2 0x7 2 0 4294967295 STRIPE_CONTROL 0 1 STRIPE_CAPABILITY 20 22 ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE 2 0x8 1 0 4294967295 RAMP_RATE 0 7 ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING 2 0x9 4 0 4294967295 PRESENTATION_TIME_EMBEDDING_ENABLE 0 0 PRESENTATION_TIME_OFFSET_CHANGED 1 1 CLEAR_GTC_COUNTER_MIN_MAX_DELTA 2 2 PRESENTATION_TIME_EMBEDDING_GROUP 4 6 ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA 2 0xc 1 0 4294967295 GTC_COUNTER_DELTA 0 31 ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN 2 0xd 1 0 4294967295 GTC_COUNTER_DELTA_MIN 0 31 ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX 2 0xe 1 0 4294967295 GTC_COUNTER_DELTA_MAX 0 31 ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 2 0x20 13 0 4294967295 AUDIO_CHANNEL_CAPABILITIES 0 0 INPUT_AMPLIFIER_PRESENT 1 1 OUTPUT_AMPLIFIER_PRESENT 2 2 AMPLIFIER_PARAMETER_OVERRIDE 3 3 STRIPE 5 5 PROCESSING_WIDGET 6 6 UNSOLICITED_RESPONSE_CAPABILITY 7 7 CONNECTION_LIST 8 8 DIGITAL 9 9 POWER_CONTROL 10 10 LR_SWAP 11 11 AUDIO_WIDGET_CAPABILITIES_DELAY 16 19 TYPE 20 23 ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES 2 0x21 11 0 4294967295 IMPEDANCE_SENSE_CAPABLE 0 0 TRIGGER_REQUIRED 1 1 JACK_DETECTION_CAPABILITY 2 2 HEADPHONE_DRIVE_CAPABLE 3 3 OUTPUT_CAPABLE 4 4 INPUT_CAPABLE 5 5 BALANCED_I_O_PINS 6 6 HDMI 7 7 VREF_CONTROL 8 15 EAPD_CAPABLE 16 16 DP 24 24 ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE 2 0x22 2 0 4294967295 TAG 0 5 ENABLE 7 7 ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE 2 0x23 1 0 4294967295 IMPEDANCE_SENSE 0 30 ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL 2 0x24 1 0 4294967295 OUT_ENABLE 6 6 ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER 2 0x25 8 0 4294967295 SPEAKER_ALLOCATION 0 6 CHANNEL_ALLOCATION 8 15 HDMI_CONNECTION 16 16 DP_CONNECTION 17 17 EXTRA_CONNECTION_INFO 18 23 LFE_PLAYBACK_LEVEL 24 25 LEVEL_SHIFT 27 30 DOWN_MIX_INHIBIT 31 31 ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 2 0x28 4 0 4294967295 MAX_CHANNELS 0 2 SUPPORTED_FREQUENCIES 8 15 DESCRIPTOR_BYTE_2 16 23 SUPPORTED_FREQUENCIES_STEREO 24 31 ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 2 0x29 3 0 4294967295 MAX_CHANNELS 0 2 SUPPORTED_FREQUENCIES 8 15 DESCRIPTOR_BYTE_2 16 23 ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 2 0x2a 3 0 4294967295 MAX_CHANNELS 0 2 SUPPORTED_FREQUENCIES 8 15 DESCRIPTOR_BYTE_2 16 23 ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 2 0x2b 3 0 4294967295 MAX_CHANNELS 0 2 SUPPORTED_FREQUENCIES 8 15 DESCRIPTOR_BYTE_2 16 23 ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 2 0x2c 3 0 4294967295 MAX_CHANNELS 0 2 SUPPORTED_FREQUENCIES 8 15 DESCRIPTOR_BYTE_2 16 23 ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 2 0x2d 3 0 4294967295 MAX_CHANNELS 0 2 SUPPORTED_FREQUENCIES 8 15 DESCRIPTOR_BYTE_2 16 23 ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 2 0x2e 3 0 4294967295 MAX_CHANNELS 0 2 SUPPORTED_FREQUENCIES 8 15 DESCRIPTOR_BYTE_2 16 23 ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 2 0x2f 3 0 4294967295 MAX_CHANNELS 0 2 SUPPORTED_FREQUENCIES 8 15 DESCRIPTOR_BYTE_2 16 23 ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 2 0x30 3 0 4294967295 MAX_CHANNELS 0 2 SUPPORTED_FREQUENCIES 8 15 DESCRIPTOR_BYTE_2 16 23 ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 2 0x31 3 0 4294967295 MAX_CHANNELS 0 2 SUPPORTED_FREQUENCIES 8 15 DESCRIPTOR_BYTE_2 16 23 ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 2 0x32 3 0 4294967295 MAX_CHANNELS 0 2 SUPPORTED_FREQUENCIES 8 15 DESCRIPTOR_BYTE_2 16 23 ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 2 0x33 3 0 4294967295 MAX_CHANNELS 0 2 SUPPORTED_FREQUENCIES 8 15 DESCRIPTOR_BYTE_2 16 23 ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 2 0x34 3 0 4294967295 MAX_CHANNELS 0 2 SUPPORTED_FREQUENCIES 8 15 DESCRIPTOR_BYTE_2 16 23 ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 2 0x35 3 0 4294967295 MAX_CHANNELS 0 2 SUPPORTED_FREQUENCIES 8 15 DESCRIPTOR_BYTE_2 16 23 ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE 2 0x36 12 0 4294967295 MULTICHANNEL01_ENABLE 0 0 MULTICHANNEL01_MUTE 1 1 MULTICHANNEL01_CHANNEL_ID 4 7 MULTICHANNEL23_ENABLE 8 8 MULTICHANNEL23_MUTE 9 9 MULTICHANNEL23_CHANNEL_ID 12 15 MULTICHANNEL45_ENABLE 16 16 MULTICHANNEL45_MUTE 17 17 MULTICHANNEL45_CHANNEL_ID 20 23 MULTICHANNEL67_ENABLE 24 24 MULTICHANNEL67_MUTE 25 25 MULTICHANNEL67_CHANNEL_ID 28 31 ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC 2 0x37 2 0 4294967295 VIDEO_LIPSYNC 0 7 AUDIO_LIPSYNC 8 15 ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR 2 0x38 2 0 4294967295 HBR_CAPABLE 0 0 HBR_ENABLE 4 4 ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0 2 0x3a 2 0 4294967295 MANUFACTURER_ID 0 15 PRODUCT_ID 16 31 ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1 2 0x3b 1 0 4294967295 SINK_DESCRIPTION_LEN 0 7 ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2 2 0x3c 1 0 4294967295 PORT_ID0 0 31 ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3 2 0x3d 1 0 4294967295 PORT_ID1 0 31 ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4 2 0x3e 4 0 4294967295 DESCRIPTION0 0 7 DESCRIPTION1 8 15 DESCRIPTION2 16 23 DESCRIPTION3 24 31 ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5 2 0x3f 4 0 4294967295 DESCRIPTION4 0 7 DESCRIPTION5 8 15 DESCRIPTION6 16 23 DESCRIPTION7 24 31 ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6 2 0x40 4 0 4294967295 DESCRIPTION8 0 7 DESCRIPTION9 8 15 DESCRIPTION10 16 23 DESCRIPTION11 24 31 ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7 2 0x41 4 0 4294967295 DESCRIPTION12 0 7 DESCRIPTION13 8 15 DESCRIPTION14 16 23 DESCRIPTION15 24 31 ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8 2 0x42 2 0 4294967295 DESCRIPTION16 0 7 DESCRIPTION17 8 15 ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL 2 0x54 3 0 4294967295 CLOCK_GATING_DISABLE 0 0 CLOCK_ON_STATE 4 4 AUDIO_ENABLED 31 31 ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 2 0x55 2 0 4294967295 UNSOLICITED_RESPONSE_PAYLOAD 0 25 UNSOLICITED_RESPONSE_FORCE 28 28 ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 2 0x56 8 0 4294967295 SEQUENCE 0 3 DEFAULT_ASSOCIATION 4 7 MISC 8 11 COLOR 12 15 CONNECTION_TYPE 16 19 DEFAULT_DEVICE 20 23 LOCATION 24 29 PORT_CONNECTIVITY 30 31 ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2 2 0x57 12 0 4294967295 MULTICHANNEL1_ENABLE 0 0 MULTICHANNEL1_MUTE 1 1 MULTICHANNEL1_CHANNEL_ID 4 7 MULTICHANNEL3_ENABLE 8 8 MULTICHANNEL3_MUTE 9 9 MULTICHANNEL3_CHANNEL_ID 12 15 MULTICHANNEL5_ENABLE 16 16 MULTICHANNEL5_MUTE 17 17 MULTICHANNEL5_CHANNEL_ID 20 23 MULTICHANNEL7_ENABLE 24 24 MULTICHANNEL7_MUTE 25 25 MULTICHANNEL7_CHANNEL_ID 28 31 ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE 2 0x58 1 0 4294967295 MULTICHANNEL_MODE 0 0 ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0 2 0x59 2 0 4294967295 IEC_60958_CS_MODE 0 1 IEC_60958_CS_SOURCE_NUMBER 2 5 ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1 2 0x5a 4 0 4294967295 IEC_60958_CS_CLOCK_ACCURACY 0 1 IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN 2 2 IEC_60958_CS_WORD_LENGTH 3 6 IEC_60958_CS_WORD_LENGTH_OVRRD_EN 7 7 ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2 2 0x5b 2 0 4294967295 IEC_60958_CS_SAMPLING_FREQUENCY 0 5 IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN 6 6 ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3 2 0x5c 2 0 4294967295 IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY 0 3 IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN 4 4 ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4 2 0x5d 4 0 4294967295 IEC_60958_CS_SAMPLING_FREQUENCY_COEFF 0 3 IEC_60958_CS_MPEG_SURROUND_INFO 4 4 IEC_60958_CS_CGMS_A 5 6 IEC_60958_CS_CGMS_A_VALID 7 7 ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5 2 0x5e 2 0 4294967295 IEC_60958_CS_CHANNEL_NUMBER_L 0 3 IEC_60958_CS_CHANNEL_NUMBER_R 4 7 ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6 2 0x5f 2 0 4294967295 IEC_60958_CS_CHANNEL_NUMBER_2 0 3 IEC_60958_CS_CHANNEL_NUMBER_3 4 7 ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7 2 0x60 2 0 4294967295 IEC_60958_CS_CHANNEL_NUMBER_4 0 3 IEC_60958_CS_CHANNEL_NUMBER_5 4 7 ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8 2 0x61 2 0 4294967295 IEC_60958_CS_CHANNEL_NUMBER_6 0 3 IEC_60958_CS_CHANNEL_NUMBER_7 4 7 ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO 2 0x62 1 0 4294967295 ASSOCIATION_INFO 0 31 ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS 2 0x63 1 0 4294967295 OUTPUT_ACTIVE 0 0 ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 2 0x64 2 0 4294967295 LPIB_SNAPSHOT_LOCK 0 0 CYCLIC_BUFFER_WRAP_COUNT 8 15 ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB 2 0x65 1 0 4294967295 LPIB 0 31 ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 2 0x66 1 0 4294967295 LPIB_TIMER_SNAPSHOT 0 31 ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE 2 0x67 1 0 4294967295 CODING_TYPE 0 7 ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED 2 0x68 4 0 4294967295 FORMAT_CHANGED 0 0 FORMAT_CHANGED_ACK_UR_ENABLE 1 1 FORMAT_CHANGE_REASON 8 15 FORMAT_CHANGE_RESPONSE 16 23 ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION 2 0x69 1 0 4294967295 WIRELESS_DISPLAY_IDENTIFICATION 0 1 ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE 2 0x6a 2 0 4294967295 REMOTE_KEEP_ALIVE_ENABLE 0 0 REMOTE_KEEP_ALIVE_CAPABILITY 4 4 ixAZF0ENDPOINT4_AZALIA_F0_AUDIO_ENABLE_STATUS 2 0x6b 1 0 4294967295 AUDIO_ENABLE_STATUS 0 0 ixAZF0ENDPOINT4_AZALIA_F0_AUDIO_ENABLED_INT_STATUS 2 0x6c 3 0 4294967295 AUDIO_ENABLED_FLAG 0 0 AUDIO_ENABLED_MASK 4 4 AUDIO_ENABLED_TYPE 8 8 ixAZF0ENDPOINT4_AZALIA_F0_AUDIO_DISABLED_INT_STATUS 2 0x6d 3 0 4294967295 AUDIO_DISABLED_FLAG 0 0 AUDIO_DISABLED_MASK 4 4 AUDIO_DISABLED_TYPE 8 8 ixAZF0ENDPOINT4_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS 2 0x6e 3 0 4294967295 AUDIO_FORMAT_CHANGED_FLAG 0 0 AUDIO_FORMAT_CHANGED_MASK 4 4 AUDIO_FORMAT_CHANGED_TYPE 8 8 ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 2 0x1 14 0 4294967295 AUDIO_CHANNEL_CAPABILITIES 0 0 INPUT_AMPLIFIER_PRESENT 1 1 OUTPUT_AMPLIFIER_PRESENT 2 2 AMPLIFIER_PARAMETER_OVERRIDE 3 3 FORMAT_OVERRIDE 4 4 STRIPE 5 5 PROCESSING_WIDGET 6 6 UNSOLICITED_RESPONSE_CAPABILITY 7 7 CONNECTION_LIST 8 8 DIGITAL 9 9 POWER_CONTROL 10 10 LR_SWAP 11 11 AUDIO_WIDGET_CAPABILITIES_DELAY 16 19 TYPE 20 23 ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT 2 0x2 6 0 4294967295 NUMBER_OF_CHANNELS 0 3 BITS_PER_SAMPLE 4 6 SAMPLE_BASE_DIVISOR 8 10 SAMPLE_BASE_MULTIPLE 11 13 SAMPLE_BASE_RATE 14 14 STREAM_TYPE 15 15 ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID 2 0x3 2 0 4294967295 CHANNEL_ID 0 3 STREAM_ID 4 7 ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER 2 0x4 10 0 4294967295 DIGEN 0 0 V 1 1 VCFG 2 2 PRE 3 3 COPY 4 4 NON_AUDIO 5 5 PRO 6 6 L 7 7 CC 8 14 KEEPALIVE 23 23 ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS 2 0x5 1 0 4294967295 STREAM_FORMATS 0 31 ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 2 0x6 2 0 4294967295 AUDIO_RATE_CAPABILITIES 0 11 AUDIO_BIT_CAPABILITIES 16 20 ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL 2 0x7 2 0 4294967295 STRIPE_CONTROL 0 1 STRIPE_CAPABILITY 20 22 ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE 2 0x8 1 0 4294967295 RAMP_RATE 0 7 ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING 2 0x9 4 0 4294967295 PRESENTATION_TIME_EMBEDDING_ENABLE 0 0 PRESENTATION_TIME_OFFSET_CHANGED 1 1 CLEAR_GTC_COUNTER_MIN_MAX_DELTA 2 2 PRESENTATION_TIME_EMBEDDING_GROUP 4 6 ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA 2 0xc 1 0 4294967295 GTC_COUNTER_DELTA 0 31 ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN 2 0xd 1 0 4294967295 GTC_COUNTER_DELTA_MIN 0 31 ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX 2 0xe 1 0 4294967295 GTC_COUNTER_DELTA_MAX 0 31 ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 2 0x20 13 0 4294967295 AUDIO_CHANNEL_CAPABILITIES 0 0 INPUT_AMPLIFIER_PRESENT 1 1 OUTPUT_AMPLIFIER_PRESENT 2 2 AMPLIFIER_PARAMETER_OVERRIDE 3 3 STRIPE 5 5 PROCESSING_WIDGET 6 6 UNSOLICITED_RESPONSE_CAPABILITY 7 7 CONNECTION_LIST 8 8 DIGITAL 9 9 POWER_CONTROL 10 10 LR_SWAP 11 11 AUDIO_WIDGET_CAPABILITIES_DELAY 16 19 TYPE 20 23 ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES 2 0x21 11 0 4294967295 IMPEDANCE_SENSE_CAPABLE 0 0 TRIGGER_REQUIRED 1 1 JACK_DETECTION_CAPABILITY 2 2 HEADPHONE_DRIVE_CAPABLE 3 3 OUTPUT_CAPABLE 4 4 INPUT_CAPABLE 5 5 BALANCED_I_O_PINS 6 6 HDMI 7 7 VREF_CONTROL 8 15 EAPD_CAPABLE 16 16 DP 24 24 ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE 2 0x22 2 0 4294967295 TAG 0 5 ENABLE 7 7 ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE 2 0x23 1 0 4294967295 IMPEDANCE_SENSE 0 30 ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL 2 0x24 1 0 4294967295 OUT_ENABLE 6 6 ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER 2 0x25 8 0 4294967295 SPEAKER_ALLOCATION 0 6 CHANNEL_ALLOCATION 8 15 HDMI_CONNECTION 16 16 DP_CONNECTION 17 17 EXTRA_CONNECTION_INFO 18 23 LFE_PLAYBACK_LEVEL 24 25 LEVEL_SHIFT 27 30 DOWN_MIX_INHIBIT 31 31 ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 2 0x28 4 0 4294967295 MAX_CHANNELS 0 2 SUPPORTED_FREQUENCIES 8 15 DESCRIPTOR_BYTE_2 16 23 SUPPORTED_FREQUENCIES_STEREO 24 31 ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 2 0x29 3 0 4294967295 MAX_CHANNELS 0 2 SUPPORTED_FREQUENCIES 8 15 DESCRIPTOR_BYTE_2 16 23 ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 2 0x2a 3 0 4294967295 MAX_CHANNELS 0 2 SUPPORTED_FREQUENCIES 8 15 DESCRIPTOR_BYTE_2 16 23 ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 2 0x2b 3 0 4294967295 MAX_CHANNELS 0 2 SUPPORTED_FREQUENCIES 8 15 DESCRIPTOR_BYTE_2 16 23 ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 2 0x2c 3 0 4294967295 MAX_CHANNELS 0 2 SUPPORTED_FREQUENCIES 8 15 DESCRIPTOR_BYTE_2 16 23 ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 2 0x2d 3 0 4294967295 MAX_CHANNELS 0 2 SUPPORTED_FREQUENCIES 8 15 DESCRIPTOR_BYTE_2 16 23 ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 2 0x2e 3 0 4294967295 MAX_CHANNELS 0 2 SUPPORTED_FREQUENCIES 8 15 DESCRIPTOR_BYTE_2 16 23 ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 2 0x2f 3 0 4294967295 MAX_CHANNELS 0 2 SUPPORTED_FREQUENCIES 8 15 DESCRIPTOR_BYTE_2 16 23 ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 2 0x30 3 0 4294967295 MAX_CHANNELS 0 2 SUPPORTED_FREQUENCIES 8 15 DESCRIPTOR_BYTE_2 16 23 ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 2 0x31 3 0 4294967295 MAX_CHANNELS 0 2 SUPPORTED_FREQUENCIES 8 15 DESCRIPTOR_BYTE_2 16 23 ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 2 0x32 3 0 4294967295 MAX_CHANNELS 0 2 SUPPORTED_FREQUENCIES 8 15 DESCRIPTOR_BYTE_2 16 23 ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 2 0x33 3 0 4294967295 MAX_CHANNELS 0 2 SUPPORTED_FREQUENCIES 8 15 DESCRIPTOR_BYTE_2 16 23 ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 2 0x34 3 0 4294967295 MAX_CHANNELS 0 2 SUPPORTED_FREQUENCIES 8 15 DESCRIPTOR_BYTE_2 16 23 ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 2 0x35 3 0 4294967295 MAX_CHANNELS 0 2 SUPPORTED_FREQUENCIES 8 15 DESCRIPTOR_BYTE_2 16 23 ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE 2 0x36 12 0 4294967295 MULTICHANNEL01_ENABLE 0 0 MULTICHANNEL01_MUTE 1 1 MULTICHANNEL01_CHANNEL_ID 4 7 MULTICHANNEL23_ENABLE 8 8 MULTICHANNEL23_MUTE 9 9 MULTICHANNEL23_CHANNEL_ID 12 15 MULTICHANNEL45_ENABLE 16 16 MULTICHANNEL45_MUTE 17 17 MULTICHANNEL45_CHANNEL_ID 20 23 MULTICHANNEL67_ENABLE 24 24 MULTICHANNEL67_MUTE 25 25 MULTICHANNEL67_CHANNEL_ID 28 31 ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC 2 0x37 2 0 4294967295 VIDEO_LIPSYNC 0 7 AUDIO_LIPSYNC 8 15 ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR 2 0x38 2 0 4294967295 HBR_CAPABLE 0 0 HBR_ENABLE 4 4 ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0 2 0x3a 2 0 4294967295 MANUFACTURER_ID 0 15 PRODUCT_ID 16 31 ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1 2 0x3b 1 0 4294967295 SINK_DESCRIPTION_LEN 0 7 ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2 2 0x3c 1 0 4294967295 PORT_ID0 0 31 ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3 2 0x3d 1 0 4294967295 PORT_ID1 0 31 ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4 2 0x3e 4 0 4294967295 DESCRIPTION0 0 7 DESCRIPTION1 8 15 DESCRIPTION2 16 23 DESCRIPTION3 24 31 ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5 2 0x3f 4 0 4294967295 DESCRIPTION4 0 7 DESCRIPTION5 8 15 DESCRIPTION6 16 23 DESCRIPTION7 24 31 ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6 2 0x40 4 0 4294967295 DESCRIPTION8 0 7 DESCRIPTION9 8 15 DESCRIPTION10 16 23 DESCRIPTION11 24 31 ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7 2 0x41 4 0 4294967295 DESCRIPTION12 0 7 DESCRIPTION13 8 15 DESCRIPTION14 16 23 DESCRIPTION15 24 31 ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8 2 0x42 2 0 4294967295 DESCRIPTION16 0 7 DESCRIPTION17 8 15 ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL 2 0x54 3 0 4294967295 CLOCK_GATING_DISABLE 0 0 CLOCK_ON_STATE 4 4 AUDIO_ENABLED 31 31 ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 2 0x55 2 0 4294967295 UNSOLICITED_RESPONSE_PAYLOAD 0 25 UNSOLICITED_RESPONSE_FORCE 28 28 ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 2 0x56 8 0 4294967295 SEQUENCE 0 3 DEFAULT_ASSOCIATION 4 7 MISC 8 11 COLOR 12 15 CONNECTION_TYPE 16 19 DEFAULT_DEVICE 20 23 LOCATION 24 29 PORT_CONNECTIVITY 30 31 ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2 2 0x57 12 0 4294967295 MULTICHANNEL1_ENABLE 0 0 MULTICHANNEL1_MUTE 1 1 MULTICHANNEL1_CHANNEL_ID 4 7 MULTICHANNEL3_ENABLE 8 8 MULTICHANNEL3_MUTE 9 9 MULTICHANNEL3_CHANNEL_ID 12 15 MULTICHANNEL5_ENABLE 16 16 MULTICHANNEL5_MUTE 17 17 MULTICHANNEL5_CHANNEL_ID 20 23 MULTICHANNEL7_ENABLE 24 24 MULTICHANNEL7_MUTE 25 25 MULTICHANNEL7_CHANNEL_ID 28 31 ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE 2 0x58 1 0 4294967295 MULTICHANNEL_MODE 0 0 ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0 2 0x59 2 0 4294967295 IEC_60958_CS_MODE 0 1 IEC_60958_CS_SOURCE_NUMBER 2 5 ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1 2 0x5a 4 0 4294967295 IEC_60958_CS_CLOCK_ACCURACY 0 1 IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN 2 2 IEC_60958_CS_WORD_LENGTH 3 6 IEC_60958_CS_WORD_LENGTH_OVRRD_EN 7 7 ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2 2 0x5b 2 0 4294967295 IEC_60958_CS_SAMPLING_FREQUENCY 0 5 IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN 6 6 ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3 2 0x5c 2 0 4294967295 IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY 0 3 IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN 4 4 ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4 2 0x5d 4 0 4294967295 IEC_60958_CS_SAMPLING_FREQUENCY_COEFF 0 3 IEC_60958_CS_MPEG_SURROUND_INFO 4 4 IEC_60958_CS_CGMS_A 5 6 IEC_60958_CS_CGMS_A_VALID 7 7 ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5 2 0x5e 2 0 4294967295 IEC_60958_CS_CHANNEL_NUMBER_L 0 3 IEC_60958_CS_CHANNEL_NUMBER_R 4 7 ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6 2 0x5f 2 0 4294967295 IEC_60958_CS_CHANNEL_NUMBER_2 0 3 IEC_60958_CS_CHANNEL_NUMBER_3 4 7 ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7 2 0x60 2 0 4294967295 IEC_60958_CS_CHANNEL_NUMBER_4 0 3 IEC_60958_CS_CHANNEL_NUMBER_5 4 7 ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8 2 0x61 2 0 4294967295 IEC_60958_CS_CHANNEL_NUMBER_6 0 3 IEC_60958_CS_CHANNEL_NUMBER_7 4 7 ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO 2 0x62 1 0 4294967295 ASSOCIATION_INFO 0 31 ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS 2 0x63 1 0 4294967295 OUTPUT_ACTIVE 0 0 ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 2 0x64 2 0 4294967295 LPIB_SNAPSHOT_LOCK 0 0 CYCLIC_BUFFER_WRAP_COUNT 8 15 ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB 2 0x65 1 0 4294967295 LPIB 0 31 ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 2 0x66 1 0 4294967295 LPIB_TIMER_SNAPSHOT 0 31 ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE 2 0x67 1 0 4294967295 CODING_TYPE 0 7 ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED 2 0x68 4 0 4294967295 FORMAT_CHANGED 0 0 FORMAT_CHANGED_ACK_UR_ENABLE 1 1 FORMAT_CHANGE_REASON 8 15 FORMAT_CHANGE_RESPONSE 16 23 ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION 2 0x69 1 0 4294967295 WIRELESS_DISPLAY_IDENTIFICATION 0 1 ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE 2 0x6a 2 0 4294967295 REMOTE_KEEP_ALIVE_ENABLE 0 0 REMOTE_KEEP_ALIVE_CAPABILITY 4 4 ixAZF0ENDPOINT5_AZALIA_F0_AUDIO_ENABLE_STATUS 2 0x6b 1 0 4294967295 AUDIO_ENABLE_STATUS 0 0 ixAZF0ENDPOINT5_AZALIA_F0_AUDIO_ENABLED_INT_STATUS 2 0x6c 3 0 4294967295 AUDIO_ENABLED_FLAG 0 0 AUDIO_ENABLED_MASK 4 4 AUDIO_ENABLED_TYPE 8 8 ixAZF0ENDPOINT5_AZALIA_F0_AUDIO_DISABLED_INT_STATUS 2 0x6d 3 0 4294967295 AUDIO_DISABLED_FLAG 0 0 AUDIO_DISABLED_MASK 4 4 AUDIO_DISABLED_TYPE 8 8 ixAZF0ENDPOINT5_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS 2 0x6e 3 0 4294967295 AUDIO_FORMAT_CHANGED_FLAG 0 0 AUDIO_FORMAT_CHANGED_MASK 4 4 AUDIO_FORMAT_CHANGED_TYPE 8 8 ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 2 0x1 14 0 4294967295 AUDIO_CHANNEL_CAPABILITIES 0 0 INPUT_AMPLIFIER_PRESENT 1 1 OUTPUT_AMPLIFIER_PRESENT 2 2 AMPLIFIER_PARAMETER_OVERRIDE 3 3 FORMAT_OVERRIDE 4 4 STRIPE 5 5 PROCESSING_WIDGET 6 6 UNSOLICITED_RESPONSE_CAPABILITY 7 7 CONNECTION_LIST 8 8 DIGITAL 9 9 POWER_CONTROL 10 10 LR_SWAP 11 11 AUDIO_WIDGET_CAPABILITIES_DELAY 16 19 TYPE 20 23 ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT 2 0x2 6 0 4294967295 NUMBER_OF_CHANNELS 0 3 BITS_PER_SAMPLE 4 6 SAMPLE_BASE_DIVISOR 8 10 SAMPLE_BASE_MULTIPLE 11 13 SAMPLE_BASE_RATE 14 14 STREAM_TYPE 15 15 ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID 2 0x3 2 0 4294967295 CHANNEL_ID 0 3 STREAM_ID 4 7 ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER 2 0x4 10 0 4294967295 DIGEN 0 0 V 1 1 VCFG 2 2 PRE 3 3 COPY 4 4 NON_AUDIO 5 5 PRO 6 6 L 7 7 CC 8 14 KEEPALIVE 23 23 ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS 2 0x5 1 0 4294967295 STREAM_FORMATS 0 31 ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 2 0x6 2 0 4294967295 AUDIO_RATE_CAPABILITIES 0 11 AUDIO_BIT_CAPABILITIES 16 20 ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL 2 0x7 2 0 4294967295 STRIPE_CONTROL 0 1 STRIPE_CAPABILITY 20 22 ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE 2 0x8 1 0 4294967295 RAMP_RATE 0 7 ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING 2 0x9 4 0 4294967295 PRESENTATION_TIME_EMBEDDING_ENABLE 0 0 PRESENTATION_TIME_OFFSET_CHANGED 1 1 CLEAR_GTC_COUNTER_MIN_MAX_DELTA 2 2 PRESENTATION_TIME_EMBEDDING_GROUP 4 6 ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA 2 0xc 1 0 4294967295 GTC_COUNTER_DELTA 0 31 ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN 2 0xd 1 0 4294967295 GTC_COUNTER_DELTA_MIN 0 31 ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX 2 0xe 1 0 4294967295 GTC_COUNTER_DELTA_MAX 0 31 ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 2 0x20 13 0 4294967295 AUDIO_CHANNEL_CAPABILITIES 0 0 INPUT_AMPLIFIER_PRESENT 1 1 OUTPUT_AMPLIFIER_PRESENT 2 2 AMPLIFIER_PARAMETER_OVERRIDE 3 3 STRIPE 5 5 PROCESSING_WIDGET 6 6 UNSOLICITED_RESPONSE_CAPABILITY 7 7 CONNECTION_LIST 8 8 DIGITAL 9 9 POWER_CONTROL 10 10 LR_SWAP 11 11 AUDIO_WIDGET_CAPABILITIES_DELAY 16 19 TYPE 20 23 ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES 2 0x21 11 0 4294967295 IMPEDANCE_SENSE_CAPABLE 0 0 TRIGGER_REQUIRED 1 1 JACK_DETECTION_CAPABILITY 2 2 HEADPHONE_DRIVE_CAPABLE 3 3 OUTPUT_CAPABLE 4 4 INPUT_CAPABLE 5 5 BALANCED_I_O_PINS 6 6 HDMI 7 7 VREF_CONTROL 8 15 EAPD_CAPABLE 16 16 DP 24 24 ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE 2 0x22 2 0 4294967295 TAG 0 5 ENABLE 7 7 ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE 2 0x23 1 0 4294967295 IMPEDANCE_SENSE 0 30 ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL 2 0x24 1 0 4294967295 OUT_ENABLE 6 6 ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER 2 0x25 8 0 4294967295 SPEAKER_ALLOCATION 0 6 CHANNEL_ALLOCATION 8 15 HDMI_CONNECTION 16 16 DP_CONNECTION 17 17 EXTRA_CONNECTION_INFO 18 23 LFE_PLAYBACK_LEVEL 24 25 LEVEL_SHIFT 27 30 DOWN_MIX_INHIBIT 31 31 ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 2 0x28 4 0 4294967295 MAX_CHANNELS 0 2 SUPPORTED_FREQUENCIES 8 15 DESCRIPTOR_BYTE_2 16 23 SUPPORTED_FREQUENCIES_STEREO 24 31 ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 2 0x29 3 0 4294967295 MAX_CHANNELS 0 2 SUPPORTED_FREQUENCIES 8 15 DESCRIPTOR_BYTE_2 16 23 ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 2 0x2a 3 0 4294967295 MAX_CHANNELS 0 2 SUPPORTED_FREQUENCIES 8 15 DESCRIPTOR_BYTE_2 16 23 ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 2 0x2b 3 0 4294967295 MAX_CHANNELS 0 2 SUPPORTED_FREQUENCIES 8 15 DESCRIPTOR_BYTE_2 16 23 ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 2 0x2c 3 0 4294967295 MAX_CHANNELS 0 2 SUPPORTED_FREQUENCIES 8 15 DESCRIPTOR_BYTE_2 16 23 ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 2 0x2d 3 0 4294967295 MAX_CHANNELS 0 2 SUPPORTED_FREQUENCIES 8 15 DESCRIPTOR_BYTE_2 16 23 ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 2 0x2e 3 0 4294967295 MAX_CHANNELS 0 2 SUPPORTED_FREQUENCIES 8 15 DESCRIPTOR_BYTE_2 16 23 ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 2 0x2f 3 0 4294967295 MAX_CHANNELS 0 2 SUPPORTED_FREQUENCIES 8 15 DESCRIPTOR_BYTE_2 16 23 ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 2 0x30 3 0 4294967295 MAX_CHANNELS 0 2 SUPPORTED_FREQUENCIES 8 15 DESCRIPTOR_BYTE_2 16 23 ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 2 0x31 3 0 4294967295 MAX_CHANNELS 0 2 SUPPORTED_FREQUENCIES 8 15 DESCRIPTOR_BYTE_2 16 23 ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 2 0x32 3 0 4294967295 MAX_CHANNELS 0 2 SUPPORTED_FREQUENCIES 8 15 DESCRIPTOR_BYTE_2 16 23 ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 2 0x33 3 0 4294967295 MAX_CHANNELS 0 2 SUPPORTED_FREQUENCIES 8 15 DESCRIPTOR_BYTE_2 16 23 ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 2 0x34 3 0 4294967295 MAX_CHANNELS 0 2 SUPPORTED_FREQUENCIES 8 15 DESCRIPTOR_BYTE_2 16 23 ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 2 0x35 3 0 4294967295 MAX_CHANNELS 0 2 SUPPORTED_FREQUENCIES 8 15 DESCRIPTOR_BYTE_2 16 23 ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE 2 0x36 12 0 4294967295 MULTICHANNEL01_ENABLE 0 0 MULTICHANNEL01_MUTE 1 1 MULTICHANNEL01_CHANNEL_ID 4 7 MULTICHANNEL23_ENABLE 8 8 MULTICHANNEL23_MUTE 9 9 MULTICHANNEL23_CHANNEL_ID 12 15 MULTICHANNEL45_ENABLE 16 16 MULTICHANNEL45_MUTE 17 17 MULTICHANNEL45_CHANNEL_ID 20 23 MULTICHANNEL67_ENABLE 24 24 MULTICHANNEL67_MUTE 25 25 MULTICHANNEL67_CHANNEL_ID 28 31 ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC 2 0x37 2 0 4294967295 VIDEO_LIPSYNC 0 7 AUDIO_LIPSYNC 8 15 ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR 2 0x38 2 0 4294967295 HBR_CAPABLE 0 0 HBR_ENABLE 4 4 ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0 2 0x3a 2 0 4294967295 MANUFACTURER_ID 0 15 PRODUCT_ID 16 31 ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1 2 0x3b 1 0 4294967295 SINK_DESCRIPTION_LEN 0 7 ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2 2 0x3c 1 0 4294967295 PORT_ID0 0 31 ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3 2 0x3d 1 0 4294967295 PORT_ID1 0 31 ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4 2 0x3e 4 0 4294967295 DESCRIPTION0 0 7 DESCRIPTION1 8 15 DESCRIPTION2 16 23 DESCRIPTION3 24 31 ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5 2 0x3f 4 0 4294967295 DESCRIPTION4 0 7 DESCRIPTION5 8 15 DESCRIPTION6 16 23 DESCRIPTION7 24 31 ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6 2 0x40 4 0 4294967295 DESCRIPTION8 0 7 DESCRIPTION9 8 15 DESCRIPTION10 16 23 DESCRIPTION11 24 31 ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7 2 0x41 4 0 4294967295 DESCRIPTION12 0 7 DESCRIPTION13 8 15 DESCRIPTION14 16 23 DESCRIPTION15 24 31 ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8 2 0x42 2 0 4294967295 DESCRIPTION16 0 7 DESCRIPTION17 8 15 ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL 2 0x54 3 0 4294967295 CLOCK_GATING_DISABLE 0 0 CLOCK_ON_STATE 4 4 AUDIO_ENABLED 31 31 ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 2 0x55 2 0 4294967295 UNSOLICITED_RESPONSE_PAYLOAD 0 25 UNSOLICITED_RESPONSE_FORCE 28 28 ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 2 0x56 8 0 4294967295 SEQUENCE 0 3 DEFAULT_ASSOCIATION 4 7 MISC 8 11 COLOR 12 15 CONNECTION_TYPE 16 19 DEFAULT_DEVICE 20 23 LOCATION 24 29 PORT_CONNECTIVITY 30 31 ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2 2 0x57 12 0 4294967295 MULTICHANNEL1_ENABLE 0 0 MULTICHANNEL1_MUTE 1 1 MULTICHANNEL1_CHANNEL_ID 4 7 MULTICHANNEL3_ENABLE 8 8 MULTICHANNEL3_MUTE 9 9 MULTICHANNEL3_CHANNEL_ID 12 15 MULTICHANNEL5_ENABLE 16 16 MULTICHANNEL5_MUTE 17 17 MULTICHANNEL5_CHANNEL_ID 20 23 MULTICHANNEL7_ENABLE 24 24 MULTICHANNEL7_MUTE 25 25 MULTICHANNEL7_CHANNEL_ID 28 31 ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE 2 0x58 1 0 4294967295 MULTICHANNEL_MODE 0 0 ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0 2 0x59 2 0 4294967295 IEC_60958_CS_MODE 0 1 IEC_60958_CS_SOURCE_NUMBER 2 5 ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1 2 0x5a 4 0 4294967295 IEC_60958_CS_CLOCK_ACCURACY 0 1 IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN 2 2 IEC_60958_CS_WORD_LENGTH 3 6 IEC_60958_CS_WORD_LENGTH_OVRRD_EN 7 7 ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2 2 0x5b 2 0 4294967295 IEC_60958_CS_SAMPLING_FREQUENCY 0 5 IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN 6 6 ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3 2 0x5c 2 0 4294967295 IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY 0 3 IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN 4 4 ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4 2 0x5d 4 0 4294967295 IEC_60958_CS_SAMPLING_FREQUENCY_COEFF 0 3 IEC_60958_CS_MPEG_SURROUND_INFO 4 4 IEC_60958_CS_CGMS_A 5 6 IEC_60958_CS_CGMS_A_VALID 7 7 ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5 2 0x5e 2 0 4294967295 IEC_60958_CS_CHANNEL_NUMBER_L 0 3 IEC_60958_CS_CHANNEL_NUMBER_R 4 7 ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6 2 0x5f 2 0 4294967295 IEC_60958_CS_CHANNEL_NUMBER_2 0 3 IEC_60958_CS_CHANNEL_NUMBER_3 4 7 ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7 2 0x60 2 0 4294967295 IEC_60958_CS_CHANNEL_NUMBER_4 0 3 IEC_60958_CS_CHANNEL_NUMBER_5 4 7 ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8 2 0x61 2 0 4294967295 IEC_60958_CS_CHANNEL_NUMBER_6 0 3 IEC_60958_CS_CHANNEL_NUMBER_7 4 7 ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO 2 0x62 1 0 4294967295 ASSOCIATION_INFO 0 31 ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS 2 0x63 1 0 4294967295 OUTPUT_ACTIVE 0 0 ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 2 0x64 2 0 4294967295 LPIB_SNAPSHOT_LOCK 0 0 CYCLIC_BUFFER_WRAP_COUNT 8 15 ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB 2 0x65 1 0 4294967295 LPIB 0 31 ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 2 0x66 1 0 4294967295 LPIB_TIMER_SNAPSHOT 0 31 ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE 2 0x67 1 0 4294967295 CODING_TYPE 0 7 ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED 2 0x68 4 0 4294967295 FORMAT_CHANGED 0 0 FORMAT_CHANGED_ACK_UR_ENABLE 1 1 FORMAT_CHANGE_REASON 8 15 FORMAT_CHANGE_RESPONSE 16 23 ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION 2 0x69 1 0 4294967295 WIRELESS_DISPLAY_IDENTIFICATION 0 1 ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE 2 0x6a 2 0 4294967295 REMOTE_KEEP_ALIVE_ENABLE 0 0 REMOTE_KEEP_ALIVE_CAPABILITY 4 4 ixAZF0ENDPOINT6_AZALIA_F0_AUDIO_ENABLE_STATUS 2 0x6b 1 0 4294967295 AUDIO_ENABLE_STATUS 0 0 ixAZF0ENDPOINT6_AZALIA_F0_AUDIO_ENABLED_INT_STATUS 2 0x6c 3 0 4294967295 AUDIO_ENABLED_FLAG 0 0 AUDIO_ENABLED_MASK 4 4 AUDIO_ENABLED_TYPE 8 8 ixAZF0ENDPOINT6_AZALIA_F0_AUDIO_DISABLED_INT_STATUS 2 0x6d 3 0 4294967295 AUDIO_DISABLED_FLAG 0 0 AUDIO_DISABLED_MASK 4 4 AUDIO_DISABLED_TYPE 8 8 ixAZF0ENDPOINT6_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS 2 0x6e 3 0 4294967295 AUDIO_FORMAT_CHANGED_FLAG 0 0 AUDIO_FORMAT_CHANGED_MASK 4 4 AUDIO_FORMAT_CHANGED_TYPE 8 8 ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 2 0x1 14 0 4294967295 AUDIO_CHANNEL_CAPABILITIES 0 0 INPUT_AMPLIFIER_PRESENT 1 1 OUTPUT_AMPLIFIER_PRESENT 2 2 AMPLIFIER_PARAMETER_OVERRIDE 3 3 FORMAT_OVERRIDE 4 4 STRIPE 5 5 PROCESSING_WIDGET 6 6 UNSOLICITED_RESPONSE_CAPABILITY 7 7 CONNECTION_LIST 8 8 DIGITAL 9 9 POWER_CONTROL 10 10 LR_SWAP 11 11 AUDIO_WIDGET_CAPABILITIES_DELAY 16 19 TYPE 20 23 ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT 2 0x2 6 0 4294967295 NUMBER_OF_CHANNELS 0 3 BITS_PER_SAMPLE 4 6 SAMPLE_BASE_DIVISOR 8 10 SAMPLE_BASE_MULTIPLE 11 13 SAMPLE_BASE_RATE 14 14 STREAM_TYPE 15 15 ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID 2 0x3 2 0 4294967295 CHANNEL_ID 0 3 STREAM_ID 4 7 ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER 2 0x4 10 0 4294967295 DIGEN 0 0 V 1 1 VCFG 2 2 PRE 3 3 COPY 4 4 NON_AUDIO 5 5 PRO 6 6 L 7 7 CC 8 14 KEEPALIVE 23 23 ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS 2 0x5 1 0 4294967295 STREAM_FORMATS 0 31 ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 2 0x6 2 0 4294967295 AUDIO_RATE_CAPABILITIES 0 11 AUDIO_BIT_CAPABILITIES 16 20 ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL 2 0x7 2 0 4294967295 STRIPE_CONTROL 0 1 STRIPE_CAPABILITY 20 22 ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE 2 0x8 1 0 4294967295 RAMP_RATE 0 7 ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING 2 0x9 4 0 4294967295 PRESENTATION_TIME_EMBEDDING_ENABLE 0 0 PRESENTATION_TIME_OFFSET_CHANGED 1 1 CLEAR_GTC_COUNTER_MIN_MAX_DELTA 2 2 PRESENTATION_TIME_EMBEDDING_GROUP 4 6 ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA 2 0xc 1 0 4294967295 GTC_COUNTER_DELTA 0 31 ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN 2 0xd 1 0 4294967295 GTC_COUNTER_DELTA_MIN 0 31 ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX 2 0xe 1 0 4294967295 GTC_COUNTER_DELTA_MAX 0 31 ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 2 0x20 13 0 4294967295 AUDIO_CHANNEL_CAPABILITIES 0 0 INPUT_AMPLIFIER_PRESENT 1 1 OUTPUT_AMPLIFIER_PRESENT 2 2 AMPLIFIER_PARAMETER_OVERRIDE 3 3 STRIPE 5 5 PROCESSING_WIDGET 6 6 UNSOLICITED_RESPONSE_CAPABILITY 7 7 CONNECTION_LIST 8 8 DIGITAL 9 9 POWER_CONTROL 10 10 LR_SWAP 11 11 AUDIO_WIDGET_CAPABILITIES_DELAY 16 19 TYPE 20 23 ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES 2 0x21 11 0 4294967295 IMPEDANCE_SENSE_CAPABLE 0 0 TRIGGER_REQUIRED 1 1 JACK_DETECTION_CAPABILITY 2 2 HEADPHONE_DRIVE_CAPABLE 3 3 OUTPUT_CAPABLE 4 4 INPUT_CAPABLE 5 5 BALANCED_I_O_PINS 6 6 HDMI 7 7 VREF_CONTROL 8 15 EAPD_CAPABLE 16 16 DP 24 24 ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE 2 0x22 2 0 4294967295 TAG 0 5 ENABLE 7 7 ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE 2 0x23 1 0 4294967295 IMPEDANCE_SENSE 0 30 ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL 2 0x24 1 0 4294967295 OUT_ENABLE 6 6 ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER 2 0x25 8 0 4294967295 SPEAKER_ALLOCATION 0 6 CHANNEL_ALLOCATION 8 15 HDMI_CONNECTION 16 16 DP_CONNECTION 17 17 EXTRA_CONNECTION_INFO 18 23 LFE_PLAYBACK_LEVEL 24 25 LEVEL_SHIFT 27 30 DOWN_MIX_INHIBIT 31 31 ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 2 0x28 4 0 4294967295 MAX_CHANNELS 0 2 SUPPORTED_FREQUENCIES 8 15 DESCRIPTOR_BYTE_2 16 23 SUPPORTED_FREQUENCIES_STEREO 24 31 ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 2 0x29 3 0 4294967295 MAX_CHANNELS 0 2 SUPPORTED_FREQUENCIES 8 15 DESCRIPTOR_BYTE_2 16 23 ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 2 0x2a 3 0 4294967295 MAX_CHANNELS 0 2 SUPPORTED_FREQUENCIES 8 15 DESCRIPTOR_BYTE_2 16 23 ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 2 0x2b 3 0 4294967295 MAX_CHANNELS 0 2 SUPPORTED_FREQUENCIES 8 15 DESCRIPTOR_BYTE_2 16 23 ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 2 0x2c 3 0 4294967295 MAX_CHANNELS 0 2 SUPPORTED_FREQUENCIES 8 15 DESCRIPTOR_BYTE_2 16 23 ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 2 0x2d 3 0 4294967295 MAX_CHANNELS 0 2 SUPPORTED_FREQUENCIES 8 15 DESCRIPTOR_BYTE_2 16 23 ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 2 0x2e 3 0 4294967295 MAX_CHANNELS 0 2 SUPPORTED_FREQUENCIES 8 15 DESCRIPTOR_BYTE_2 16 23 ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 2 0x2f 3 0 4294967295 MAX_CHANNELS 0 2 SUPPORTED_FREQUENCIES 8 15 DESCRIPTOR_BYTE_2 16 23 ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 2 0x30 3 0 4294967295 MAX_CHANNELS 0 2 SUPPORTED_FREQUENCIES 8 15 DESCRIPTOR_BYTE_2 16 23 ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 2 0x31 3 0 4294967295 MAX_CHANNELS 0 2 SUPPORTED_FREQUENCIES 8 15 DESCRIPTOR_BYTE_2 16 23 ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 2 0x32 3 0 4294967295 MAX_CHANNELS 0 2 SUPPORTED_FREQUENCIES 8 15 DESCRIPTOR_BYTE_2 16 23 ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 2 0x33 3 0 4294967295 MAX_CHANNELS 0 2 SUPPORTED_FREQUENCIES 8 15 DESCRIPTOR_BYTE_2 16 23 ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 2 0x34 3 0 4294967295 MAX_CHANNELS 0 2 SUPPORTED_FREQUENCIES 8 15 DESCRIPTOR_BYTE_2 16 23 ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 2 0x35 3 0 4294967295 MAX_CHANNELS 0 2 SUPPORTED_FREQUENCIES 8 15 DESCRIPTOR_BYTE_2 16 23 ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE 2 0x36 12 0 4294967295 MULTICHANNEL01_ENABLE 0 0 MULTICHANNEL01_MUTE 1 1 MULTICHANNEL01_CHANNEL_ID 4 7 MULTICHANNEL23_ENABLE 8 8 MULTICHANNEL23_MUTE 9 9 MULTICHANNEL23_CHANNEL_ID 12 15 MULTICHANNEL45_ENABLE 16 16 MULTICHANNEL45_MUTE 17 17 MULTICHANNEL45_CHANNEL_ID 20 23 MULTICHANNEL67_ENABLE 24 24 MULTICHANNEL67_MUTE 25 25 MULTICHANNEL67_CHANNEL_ID 28 31 ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC 2 0x37 2 0 4294967295 VIDEO_LIPSYNC 0 7 AUDIO_LIPSYNC 8 15 ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR 2 0x38 2 0 4294967295 HBR_CAPABLE 0 0 HBR_ENABLE 4 4 ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0 2 0x3a 2 0 4294967295 MANUFACTURER_ID 0 15 PRODUCT_ID 16 31 ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1 2 0x3b 1 0 4294967295 SINK_DESCRIPTION_LEN 0 7 ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2 2 0x3c 1 0 4294967295 PORT_ID0 0 31 ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3 2 0x3d 1 0 4294967295 PORT_ID1 0 31 ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4 2 0x3e 4 0 4294967295 DESCRIPTION0 0 7 DESCRIPTION1 8 15 DESCRIPTION2 16 23 DESCRIPTION3 24 31 ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5 2 0x3f 4 0 4294967295 DESCRIPTION4 0 7 DESCRIPTION5 8 15 DESCRIPTION6 16 23 DESCRIPTION7 24 31 ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6 2 0x40 4 0 4294967295 DESCRIPTION8 0 7 DESCRIPTION9 8 15 DESCRIPTION10 16 23 DESCRIPTION11 24 31 ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7 2 0x41 4 0 4294967295 DESCRIPTION12 0 7 DESCRIPTION13 8 15 DESCRIPTION14 16 23 DESCRIPTION15 24 31 ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8 2 0x42 2 0 4294967295 DESCRIPTION16 0 7 DESCRIPTION17 8 15 ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL 2 0x54 3 0 4294967295 CLOCK_GATING_DISABLE 0 0 CLOCK_ON_STATE 4 4 AUDIO_ENABLED 31 31 ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 2 0x55 2 0 4294967295 UNSOLICITED_RESPONSE_PAYLOAD 0 25 UNSOLICITED_RESPONSE_FORCE 28 28 ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 2 0x56 8 0 4294967295 SEQUENCE 0 3 DEFAULT_ASSOCIATION 4 7 MISC 8 11 COLOR 12 15 CONNECTION_TYPE 16 19 DEFAULT_DEVICE 20 23 LOCATION 24 29 PORT_CONNECTIVITY 30 31 ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2 2 0x57 12 0 4294967295 MULTICHANNEL1_ENABLE 0 0 MULTICHANNEL1_MUTE 1 1 MULTICHANNEL1_CHANNEL_ID 4 7 MULTICHANNEL3_ENABLE 8 8 MULTICHANNEL3_MUTE 9 9 MULTICHANNEL3_CHANNEL_ID 12 15 MULTICHANNEL5_ENABLE 16 16 MULTICHANNEL5_MUTE 17 17 MULTICHANNEL5_CHANNEL_ID 20 23 MULTICHANNEL7_ENABLE 24 24 MULTICHANNEL7_MUTE 25 25 MULTICHANNEL7_CHANNEL_ID 28 31 ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE 2 0x58 1 0 4294967295 MULTICHANNEL_MODE 0 0 ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0 2 0x59 2 0 4294967295 IEC_60958_CS_MODE 0 1 IEC_60958_CS_SOURCE_NUMBER 2 5 ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1 2 0x5a 4 0 4294967295 IEC_60958_CS_CLOCK_ACCURACY 0 1 IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN 2 2 IEC_60958_CS_WORD_LENGTH 3 6 IEC_60958_CS_WORD_LENGTH_OVRRD_EN 7 7 ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2 2 0x5b 2 0 4294967295 IEC_60958_CS_SAMPLING_FREQUENCY 0 5 IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN 6 6 ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3 2 0x5c 2 0 4294967295 IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY 0 3 IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN 4 4 ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4 2 0x5d 4 0 4294967295 IEC_60958_CS_SAMPLING_FREQUENCY_COEFF 0 3 IEC_60958_CS_MPEG_SURROUND_INFO 4 4 IEC_60958_CS_CGMS_A 5 6 IEC_60958_CS_CGMS_A_VALID 7 7 ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5 2 0x5e 2 0 4294967295 IEC_60958_CS_CHANNEL_NUMBER_L 0 3 IEC_60958_CS_CHANNEL_NUMBER_R 4 7 ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6 2 0x5f 2 0 4294967295 IEC_60958_CS_CHANNEL_NUMBER_2 0 3 IEC_60958_CS_CHANNEL_NUMBER_3 4 7 ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7 2 0x60 2 0 4294967295 IEC_60958_CS_CHANNEL_NUMBER_4 0 3 IEC_60958_CS_CHANNEL_NUMBER_5 4 7 ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8 2 0x61 2 0 4294967295 IEC_60958_CS_CHANNEL_NUMBER_6 0 3 IEC_60958_CS_CHANNEL_NUMBER_7 4 7 ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO 2 0x62 1 0 4294967295 ASSOCIATION_INFO 0 31 ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS 2 0x63 1 0 4294967295 OUTPUT_ACTIVE 0 0 ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 2 0x64 2 0 4294967295 LPIB_SNAPSHOT_LOCK 0 0 CYCLIC_BUFFER_WRAP_COUNT 8 15 ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB 2 0x65 1 0 4294967295 LPIB 0 31 ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 2 0x66 1 0 4294967295 LPIB_TIMER_SNAPSHOT 0 31 ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE 2 0x67 1 0 4294967295 CODING_TYPE 0 7 ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED 2 0x68 4 0 4294967295 FORMAT_CHANGED 0 0 FORMAT_CHANGED_ACK_UR_ENABLE 1 1 FORMAT_CHANGE_REASON 8 15 FORMAT_CHANGE_RESPONSE 16 23 ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION 2 0x69 1 0 4294967295 WIRELESS_DISPLAY_IDENTIFICATION 0 1 ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE 2 0x6a 2 0 4294967295 REMOTE_KEEP_ALIVE_ENABLE 0 0 REMOTE_KEEP_ALIVE_CAPABILITY 4 4 ixAZF0ENDPOINT7_AZALIA_F0_AUDIO_ENABLE_STATUS 2 0x6b 1 0 4294967295 AUDIO_ENABLE_STATUS 0 0 ixAZF0ENDPOINT7_AZALIA_F0_AUDIO_ENABLED_INT_STATUS 2 0x6c 3 0 4294967295 AUDIO_ENABLED_FLAG 0 0 AUDIO_ENABLED_MASK 4 4 AUDIO_ENABLED_TYPE 8 8 ixAZF0ENDPOINT7_AZALIA_F0_AUDIO_DISABLED_INT_STATUS 2 0x6d 3 0 4294967295 AUDIO_DISABLED_FLAG 0 0 AUDIO_DISABLED_MASK 4 4 AUDIO_DISABLED_TYPE 8 8 ixAZF0ENDPOINT7_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS 2 0x6e 3 0 4294967295 AUDIO_FORMAT_CHANGED_FLAG 0 0 AUDIO_FORMAT_CHANGED_MASK 4 4 AUDIO_FORMAT_CHANGED_TYPE 8 8 ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 2 0x1 14 0 4294967295 AUDIO_CHANNEL_CAPABILITIES 0 0 INPUT_AMPLIFIER_PRESENT 1 1 OUTPUT_AMPLIFIER_PRESENT 2 2 AMPLIFIER_PARAMETER_OVERRIDE 3 3 FORMAT_OVERRIDE 4 4 STRIPE 5 5 PROCESSING_WIDGET 6 6 UNSOLICITED_RESPONSE_CAPABILITY 7 7 CONNECTION_LIST 8 8 DIGITAL 9 9 POWER_CONTROL 10 10 LR_SWAP 11 11 AUDIO_WIDGET_CAPABILITIES_DELAY 16 19 TYPE 20 23 ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT 2 0x2 6 0 4294967295 NUMBER_OF_CHANNELS 0 3 BITS_PER_SAMPLE 4 6 SAMPLE_BASE_DIVISOR 8 10 SAMPLE_BASE_MULTIPLE 11 13 SAMPLE_BASE_RATE 14 14 STREAM_TYPE 15 15 ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID 2 0x3 2 0 4294967295 CHANNEL_ID 0 3 STREAM_ID 4 7 ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER 2 0x4 10 0 4294967295 DIGEN 0 0 V 1 1 VCFG 2 2 PRE 3 3 COPY 4 4 NON_AUDIO 5 5 PRO 6 6 L 7 7 CC 8 14 KEEPALIVE 23 23 ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS 2 0x5 1 0 4294967295 STREAM_FORMATS 0 31 ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 2 0x6 2 0 4294967295 AUDIO_RATE_CAPABILITIES 0 11 AUDIO_BIT_CAPABILITIES 16 20 ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 2 0x20 13 0 4294967295 AUDIO_CHANNEL_CAPABILITIES 0 0 INPUT_AMPLIFIER_PRESENT 1 1 OUTPUT_AMPLIFIER_PRESENT 2 2 AMPLIFIER_PARAMETER_OVERRIDE 3 3 STRIPE 5 5 PROCESSING_WIDGET 6 6 UNSOLICITED_RESPONSE_CAPABILITY 7 7 CONNECTION_LIST 8 8 DIGITAL 9 9 POWER_CONTROL 10 10 LR_SWAP 11 11 AUDIO_WIDGET_CAPABILITIES_DELAY 16 19 TYPE 20 23 ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES 2 0x21 11 0 4294967295 IMPEDANCE_SENSE_CAPABLE 0 0 TRIGGER_REQUIRED 1 1 JACK_DETECTION_CAPABILITY 2 2 HEADPHONE_DRIVE_CAPABLE 3 3 OUTPUT_CAPABLE 4 4 INPUT_CAPABLE 5 5 BALANCED_I_O_PINS 6 6 HDMI 7 7 VREF_CONTROL 8 15 EAPD_CAPABLE 16 16 DP 24 24 ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE 2 0x22 2 0 4294967295 TAG 0 5 ENABLE 7 7 ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE 2 0x23 2 0 4294967295 IMPEDANCE_SENSE 0 30 PRESENCE_DETECT 31 31 ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL 2 0x24 1 0 4294967295 IN_ENABLE 5 5 ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE 2 0x36 12 0 4294967295 MULTICHANNEL0_ENABLE 0 0 MULTICHANNEL0_MUTE 1 1 MULTICHANNEL0_CHANNEL_ID 4 7 MULTICHANNEL1_ENABLE 8 8 MULTICHANNEL1_MUTE 9 9 MULTICHANNEL1_CHANNEL_ID 12 15 MULTICHANNEL2_ENABLE 16 16 MULTICHANNEL2_MUTE 17 17 MULTICHANNEL2_CHANNEL_ID 20 23 MULTICHANNEL3_ENABLE 24 24 MULTICHANNEL3_MUTE 25 25 MULTICHANNEL3_CHANNEL_ID 28 31 ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2 2 0x37 12 0 4294967295 MULTICHANNEL4_ENABLE 0 0 MULTICHANNEL4_MUTE 1 1 MULTICHANNEL4_CHANNEL_ID 4 7 MULTICHANNEL5_ENABLE 8 8 MULTICHANNEL5_MUTE 9 9 MULTICHANNEL5_CHANNEL_ID 12 15 MULTICHANNEL6_ENABLE 16 16 MULTICHANNEL6_MUTE 17 17 MULTICHANNEL6_CHANNEL_ID 20 23 MULTICHANNEL7_ENABLE 24 24 MULTICHANNEL7_MUTE 25 25 MULTICHANNEL7_CHANNEL_ID 28 31 ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR 2 0x38 2 0 4294967295 HBR_CAPABLE 0 0 HBR_ENABLE 4 4 ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION 2 0x53 1 0 4294967295 CHANNEL_ALLOCATION 0 7 ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL 2 0x54 3 0 4294967295 CLOCK_GATING_DISABLE 0 0 CLOCK_ON_STATE 4 4 AUDIO_ENABLED 31 31 ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 2 0x55 2 0 4294967295 UNSOLICITED_RESPONSE_PAYLOAD 0 25 UNSOLICITED_RESPONSE_FORCE 28 28 ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 2 0x56 8 0 4294967295 SEQUENCE 0 3 DEFAULT_ASSOCIATION 4 7 MISC 8 11 COLOR 12 15 CONNECTION_TYPE 16 19 DEFAULT_DEVICE 20 23 LOCATION 24 29 PORT_CONNECTIVITY 30 31 ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 2 0x64 2 0 4294967295 LPIB_SNAPSHOT_LOCK 0 0 CYCLIC_BUFFER_WRAP_COUNT 8 15 ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB 2 0x65 1 0 4294967295 LPIB 0 31 ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 2 0x66 1 0 4294967295 LPIB_TIMER_SNAPSHOT 0 31 ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL 2 0x67 4 0 4294967295 INPUT_ACTIVITY 0 0 CHANNEL_LAYOUT 1 2 INPUT_ACTIVITY_UR_ENABLE 4 4 INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE 5 5 ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME 2 0x68 4 0 4294967295 CHANNEL_COUNT 0 2 CHANNEL_ALLOCATION 8 15 INFOFRAME_BYTE_5 16 23 INFOFRAME_VALID 31 31 ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 2 0x1 14 0 4294967295 AUDIO_CHANNEL_CAPABILITIES 0 0 INPUT_AMPLIFIER_PRESENT 1 1 OUTPUT_AMPLIFIER_PRESENT 2 2 AMPLIFIER_PARAMETER_OVERRIDE 3 3 FORMAT_OVERRIDE 4 4 STRIPE 5 5 PROCESSING_WIDGET 6 6 UNSOLICITED_RESPONSE_CAPABILITY 7 7 CONNECTION_LIST 8 8 DIGITAL 9 9 POWER_CONTROL 10 10 LR_SWAP 11 11 AUDIO_WIDGET_CAPABILITIES_DELAY 16 19 TYPE 20 23 ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT 2 0x2 6 0 4294967295 NUMBER_OF_CHANNELS 0 3 BITS_PER_SAMPLE 4 6 SAMPLE_BASE_DIVISOR 8 10 SAMPLE_BASE_MULTIPLE 11 13 SAMPLE_BASE_RATE 14 14 STREAM_TYPE 15 15 ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID 2 0x3 2 0 4294967295 CHANNEL_ID 0 3 STREAM_ID 4 7 ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER 2 0x4 10 0 4294967295 DIGEN 0 0 V 1 1 VCFG 2 2 PRE 3 3 COPY 4 4 NON_AUDIO 5 5 PRO 6 6 L 7 7 CC 8 14 KEEPALIVE 23 23 ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS 2 0x5 1 0 4294967295 STREAM_FORMATS 0 31 ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 2 0x6 2 0 4294967295 AUDIO_RATE_CAPABILITIES 0 11 AUDIO_BIT_CAPABILITIES 16 20 ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 2 0x20 13 0 4294967295 AUDIO_CHANNEL_CAPABILITIES 0 0 INPUT_AMPLIFIER_PRESENT 1 1 OUTPUT_AMPLIFIER_PRESENT 2 2 AMPLIFIER_PARAMETER_OVERRIDE 3 3 STRIPE 5 5 PROCESSING_WIDGET 6 6 UNSOLICITED_RESPONSE_CAPABILITY 7 7 CONNECTION_LIST 8 8 DIGITAL 9 9 POWER_CONTROL 10 10 LR_SWAP 11 11 AUDIO_WIDGET_CAPABILITIES_DELAY 16 19 TYPE 20 23 ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES 2 0x21 11 0 4294967295 IMPEDANCE_SENSE_CAPABLE 0 0 TRIGGER_REQUIRED 1 1 JACK_DETECTION_CAPABILITY 2 2 HEADPHONE_DRIVE_CAPABLE 3 3 OUTPUT_CAPABLE 4 4 INPUT_CAPABLE 5 5 BALANCED_I_O_PINS 6 6 HDMI 7 7 VREF_CONTROL 8 15 EAPD_CAPABLE 16 16 DP 24 24 ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE 2 0x22 2 0 4294967295 TAG 0 5 ENABLE 7 7 ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE 2 0x23 2 0 4294967295 IMPEDANCE_SENSE 0 30 PRESENCE_DETECT 31 31 ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL 2 0x24 1 0 4294967295 IN_ENABLE 5 5 ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE 2 0x36 12 0 4294967295 MULTICHANNEL0_ENABLE 0 0 MULTICHANNEL0_MUTE 1 1 MULTICHANNEL0_CHANNEL_ID 4 7 MULTICHANNEL1_ENABLE 8 8 MULTICHANNEL1_MUTE 9 9 MULTICHANNEL1_CHANNEL_ID 12 15 MULTICHANNEL2_ENABLE 16 16 MULTICHANNEL2_MUTE 17 17 MULTICHANNEL2_CHANNEL_ID 20 23 MULTICHANNEL3_ENABLE 24 24 MULTICHANNEL3_MUTE 25 25 MULTICHANNEL3_CHANNEL_ID 28 31 ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2 2 0x37 12 0 4294967295 MULTICHANNEL4_ENABLE 0 0 MULTICHANNEL4_MUTE 1 1 MULTICHANNEL4_CHANNEL_ID 4 7 MULTICHANNEL5_ENABLE 8 8 MULTICHANNEL5_MUTE 9 9 MULTICHANNEL5_CHANNEL_ID 12 15 MULTICHANNEL6_ENABLE 16 16 MULTICHANNEL6_MUTE 17 17 MULTICHANNEL6_CHANNEL_ID 20 23 MULTICHANNEL7_ENABLE 24 24 MULTICHANNEL7_MUTE 25 25 MULTICHANNEL7_CHANNEL_ID 28 31 ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR 2 0x38 2 0 4294967295 HBR_CAPABLE 0 0 HBR_ENABLE 4 4 ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION 2 0x53 1 0 4294967295 CHANNEL_ALLOCATION 0 7 ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL 2 0x54 3 0 4294967295 CLOCK_GATING_DISABLE 0 0 CLOCK_ON_STATE 4 4 AUDIO_ENABLED 31 31 ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 2 0x55 2 0 4294967295 UNSOLICITED_RESPONSE_PAYLOAD 0 25 UNSOLICITED_RESPONSE_FORCE 28 28 ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 2 0x56 8 0 4294967295 SEQUENCE 0 3 DEFAULT_ASSOCIATION 4 7 MISC 8 11 COLOR 12 15 CONNECTION_TYPE 16 19 DEFAULT_DEVICE 20 23 LOCATION 24 29 PORT_CONNECTIVITY 30 31 ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 2 0x64 2 0 4294967295 LPIB_SNAPSHOT_LOCK 0 0 CYCLIC_BUFFER_WRAP_COUNT 8 15 ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB 2 0x65 1 0 4294967295 LPIB 0 31 ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 2 0x66 1 0 4294967295 LPIB_TIMER_SNAPSHOT 0 31 ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL 2 0x67 4 0 4294967295 INPUT_ACTIVITY 0 0 CHANNEL_LAYOUT 1 2 INPUT_ACTIVITY_UR_ENABLE 4 4 INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE 5 5 ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME 2 0x68 4 0 4294967295 CHANNEL_COUNT 0 2 CHANNEL_ALLOCATION 8 15 INFOFRAME_BYTE_5 16 23 INFOFRAME_VALID 31 31 ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 2 0x1 14 0 4294967295 AUDIO_CHANNEL_CAPABILITIES 0 0 INPUT_AMPLIFIER_PRESENT 1 1 OUTPUT_AMPLIFIER_PRESENT 2 2 AMPLIFIER_PARAMETER_OVERRIDE 3 3 FORMAT_OVERRIDE 4 4 STRIPE 5 5 PROCESSING_WIDGET 6 6 UNSOLICITED_RESPONSE_CAPABILITY 7 7 CONNECTION_LIST 8 8 DIGITAL 9 9 POWER_CONTROL 10 10 LR_SWAP 11 11 AUDIO_WIDGET_CAPABILITIES_DELAY 16 19 TYPE 20 23 ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT 2 0x2 6 0 4294967295 NUMBER_OF_CHANNELS 0 3 BITS_PER_SAMPLE 4 6 SAMPLE_BASE_DIVISOR 8 10 SAMPLE_BASE_MULTIPLE 11 13 SAMPLE_BASE_RATE 14 14 STREAM_TYPE 15 15 ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID 2 0x3 2 0 4294967295 CHANNEL_ID 0 3 STREAM_ID 4 7 ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER 2 0x4 10 0 4294967295 DIGEN 0 0 V 1 1 VCFG 2 2 PRE 3 3 COPY 4 4 NON_AUDIO 5 5 PRO 6 6 L 7 7 CC 8 14 KEEPALIVE 23 23 ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS 2 0x5 1 0 4294967295 STREAM_FORMATS 0 31 ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 2 0x6 2 0 4294967295 AUDIO_RATE_CAPABILITIES 0 11 AUDIO_BIT_CAPABILITIES 16 20 ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 2 0x20 13 0 4294967295 AUDIO_CHANNEL_CAPABILITIES 0 0 INPUT_AMPLIFIER_PRESENT 1 1 OUTPUT_AMPLIFIER_PRESENT 2 2 AMPLIFIER_PARAMETER_OVERRIDE 3 3 STRIPE 5 5 PROCESSING_WIDGET 6 6 UNSOLICITED_RESPONSE_CAPABILITY 7 7 CONNECTION_LIST 8 8 DIGITAL 9 9 POWER_CONTROL 10 10 LR_SWAP 11 11 AUDIO_WIDGET_CAPABILITIES_DELAY 16 19 TYPE 20 23 ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES 2 0x21 11 0 4294967295 IMPEDANCE_SENSE_CAPABLE 0 0 TRIGGER_REQUIRED 1 1 JACK_DETECTION_CAPABILITY 2 2 HEADPHONE_DRIVE_CAPABLE 3 3 OUTPUT_CAPABLE 4 4 INPUT_CAPABLE 5 5 BALANCED_I_O_PINS 6 6 HDMI 7 7 VREF_CONTROL 8 15 EAPD_CAPABLE 16 16 DP 24 24 ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE 2 0x22 2 0 4294967295 TAG 0 5 ENABLE 7 7 ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE 2 0x23 2 0 4294967295 IMPEDANCE_SENSE 0 30 PRESENCE_DETECT 31 31 ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL 2 0x24 1 0 4294967295 IN_ENABLE 5 5 ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE 2 0x36 12 0 4294967295 MULTICHANNEL0_ENABLE 0 0 MULTICHANNEL0_MUTE 1 1 MULTICHANNEL0_CHANNEL_ID 4 7 MULTICHANNEL1_ENABLE 8 8 MULTICHANNEL1_MUTE 9 9 MULTICHANNEL1_CHANNEL_ID 12 15 MULTICHANNEL2_ENABLE 16 16 MULTICHANNEL2_MUTE 17 17 MULTICHANNEL2_CHANNEL_ID 20 23 MULTICHANNEL3_ENABLE 24 24 MULTICHANNEL3_MUTE 25 25 MULTICHANNEL3_CHANNEL_ID 28 31 ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2 2 0x37 12 0 4294967295 MULTICHANNEL4_ENABLE 0 0 MULTICHANNEL4_MUTE 1 1 MULTICHANNEL4_CHANNEL_ID 4 7 MULTICHANNEL5_ENABLE 8 8 MULTICHANNEL5_MUTE 9 9 MULTICHANNEL5_CHANNEL_ID 12 15 MULTICHANNEL6_ENABLE 16 16 MULTICHANNEL6_MUTE 17 17 MULTICHANNEL6_CHANNEL_ID 20 23 MULTICHANNEL7_ENABLE 24 24 MULTICHANNEL7_MUTE 25 25 MULTICHANNEL7_CHANNEL_ID 28 31 ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR 2 0x38 2 0 4294967295 HBR_CAPABLE 0 0 HBR_ENABLE 4 4 ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION 2 0x53 1 0 4294967295 CHANNEL_ALLOCATION 0 7 ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL 2 0x54 3 0 4294967295 CLOCK_GATING_DISABLE 0 0 CLOCK_ON_STATE 4 4 AUDIO_ENABLED 31 31 ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 2 0x55 2 0 4294967295 UNSOLICITED_RESPONSE_PAYLOAD 0 25 UNSOLICITED_RESPONSE_FORCE 28 28 ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 2 0x56 8 0 4294967295 SEQUENCE 0 3 DEFAULT_ASSOCIATION 4 7 MISC 8 11 COLOR 12 15 CONNECTION_TYPE 16 19 DEFAULT_DEVICE 20 23 LOCATION 24 29 PORT_CONNECTIVITY 30 31 ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 2 0x64 2 0 4294967295 LPIB_SNAPSHOT_LOCK 0 0 CYCLIC_BUFFER_WRAP_COUNT 8 15 ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB 2 0x65 1 0 4294967295 LPIB 0 31 ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 2 0x66 1 0 4294967295 LPIB_TIMER_SNAPSHOT 0 31 ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL 2 0x67 4 0 4294967295 INPUT_ACTIVITY 0 0 CHANNEL_LAYOUT 1 2 INPUT_ACTIVITY_UR_ENABLE 4 4 INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE 5 5 ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME 2 0x68 4 0 4294967295 CHANNEL_COUNT 0 2 CHANNEL_ALLOCATION 8 15 INFOFRAME_BYTE_5 16 23 INFOFRAME_VALID 31 31 ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 2 0x1 14 0 4294967295 AUDIO_CHANNEL_CAPABILITIES 0 0 INPUT_AMPLIFIER_PRESENT 1 1 OUTPUT_AMPLIFIER_PRESENT 2 2 AMPLIFIER_PARAMETER_OVERRIDE 3 3 FORMAT_OVERRIDE 4 4 STRIPE 5 5 PROCESSING_WIDGET 6 6 UNSOLICITED_RESPONSE_CAPABILITY 7 7 CONNECTION_LIST 8 8 DIGITAL 9 9 POWER_CONTROL 10 10 LR_SWAP 11 11 AUDIO_WIDGET_CAPABILITIES_DELAY 16 19 TYPE 20 23 ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT 2 0x2 6 0 4294967295 NUMBER_OF_CHANNELS 0 3 BITS_PER_SAMPLE 4 6 SAMPLE_BASE_DIVISOR 8 10 SAMPLE_BASE_MULTIPLE 11 13 SAMPLE_BASE_RATE 14 14 STREAM_TYPE 15 15 ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID 2 0x3 2 0 4294967295 CHANNEL_ID 0 3 STREAM_ID 4 7 ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER 2 0x4 10 0 4294967295 DIGEN 0 0 V 1 1 VCFG 2 2 PRE 3 3 COPY 4 4 NON_AUDIO 5 5 PRO 6 6 L 7 7 CC 8 14 KEEPALIVE 23 23 ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS 2 0x5 1 0 4294967295 STREAM_FORMATS 0 31 ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 2 0x6 2 0 4294967295 AUDIO_RATE_CAPABILITIES 0 11 AUDIO_BIT_CAPABILITIES 16 20 ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 2 0x20 13 0 4294967295 AUDIO_CHANNEL_CAPABILITIES 0 0 INPUT_AMPLIFIER_PRESENT 1 1 OUTPUT_AMPLIFIER_PRESENT 2 2 AMPLIFIER_PARAMETER_OVERRIDE 3 3 STRIPE 5 5 PROCESSING_WIDGET 6 6 UNSOLICITED_RESPONSE_CAPABILITY 7 7 CONNECTION_LIST 8 8 DIGITAL 9 9 POWER_CONTROL 10 10 LR_SWAP 11 11 AUDIO_WIDGET_CAPABILITIES_DELAY 16 19 TYPE 20 23 ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES 2 0x21 11 0 4294967295 IMPEDANCE_SENSE_CAPABLE 0 0 TRIGGER_REQUIRED 1 1 JACK_DETECTION_CAPABILITY 2 2 HEADPHONE_DRIVE_CAPABLE 3 3 OUTPUT_CAPABLE 4 4 INPUT_CAPABLE 5 5 BALANCED_I_O_PINS 6 6 HDMI 7 7 VREF_CONTROL 8 15 EAPD_CAPABLE 16 16 DP 24 24 ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE 2 0x22 2 0 4294967295 TAG 0 5 ENABLE 7 7 ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE 2 0x23 2 0 4294967295 IMPEDANCE_SENSE 0 30 PRESENCE_DETECT 31 31 ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL 2 0x24 1 0 4294967295 IN_ENABLE 5 5 ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE 2 0x36 12 0 4294967295 MULTICHANNEL0_ENABLE 0 0 MULTICHANNEL0_MUTE 1 1 MULTICHANNEL0_CHANNEL_ID 4 7 MULTICHANNEL1_ENABLE 8 8 MULTICHANNEL1_MUTE 9 9 MULTICHANNEL1_CHANNEL_ID 12 15 MULTICHANNEL2_ENABLE 16 16 MULTICHANNEL2_MUTE 17 17 MULTICHANNEL2_CHANNEL_ID 20 23 MULTICHANNEL3_ENABLE 24 24 MULTICHANNEL3_MUTE 25 25 MULTICHANNEL3_CHANNEL_ID 28 31 ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2 2 0x37 12 0 4294967295 MULTICHANNEL4_ENABLE 0 0 MULTICHANNEL4_MUTE 1 1 MULTICHANNEL4_CHANNEL_ID 4 7 MULTICHANNEL5_ENABLE 8 8 MULTICHANNEL5_MUTE 9 9 MULTICHANNEL5_CHANNEL_ID 12 15 MULTICHANNEL6_ENABLE 16 16 MULTICHANNEL6_MUTE 17 17 MULTICHANNEL6_CHANNEL_ID 20 23 MULTICHANNEL7_ENABLE 24 24 MULTICHANNEL7_MUTE 25 25 MULTICHANNEL7_CHANNEL_ID 28 31 ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR 2 0x38 2 0 4294967295 HBR_CAPABLE 0 0 HBR_ENABLE 4 4 ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION 2 0x53 1 0 4294967295 CHANNEL_ALLOCATION 0 7 ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL 2 0x54 3 0 4294967295 CLOCK_GATING_DISABLE 0 0 CLOCK_ON_STATE 4 4 AUDIO_ENABLED 31 31 ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 2 0x55 2 0 4294967295 UNSOLICITED_RESPONSE_PAYLOAD 0 25 UNSOLICITED_RESPONSE_FORCE 28 28 ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 2 0x56 8 0 4294967295 SEQUENCE 0 3 DEFAULT_ASSOCIATION 4 7 MISC 8 11 COLOR 12 15 CONNECTION_TYPE 16 19 DEFAULT_DEVICE 20 23 LOCATION 24 29 PORT_CONNECTIVITY 30 31 ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 2 0x64 2 0 4294967295 LPIB_SNAPSHOT_LOCK 0 0 CYCLIC_BUFFER_WRAP_COUNT 8 15 ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB 2 0x65 1 0 4294967295 LPIB 0 31 ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 2 0x66 1 0 4294967295 LPIB_TIMER_SNAPSHOT 0 31 ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL 2 0x67 4 0 4294967295 INPUT_ACTIVITY 0 0 CHANNEL_LAYOUT 1 2 INPUT_ACTIVITY_UR_ENABLE 4 4 INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE 5 5 ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME 2 0x68 4 0 4294967295 CHANNEL_COUNT 0 2 CHANNEL_ALLOCATION 8 15 INFOFRAME_BYTE_5 16 23 INFOFRAME_VALID 31 31 ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 2 0x1 14 0 4294967295 AUDIO_CHANNEL_CAPABILITIES 0 0 INPUT_AMPLIFIER_PRESENT 1 1 OUTPUT_AMPLIFIER_PRESENT 2 2 AMPLIFIER_PARAMETER_OVERRIDE 3 3 FORMAT_OVERRIDE 4 4 STRIPE 5 5 PROCESSING_WIDGET 6 6 UNSOLICITED_RESPONSE_CAPABILITY 7 7 CONNECTION_LIST 8 8 DIGITAL 9 9 POWER_CONTROL 10 10 LR_SWAP 11 11 AUDIO_WIDGET_CAPABILITIES_DELAY 16 19 TYPE 20 23 ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT 2 0x2 6 0 4294967295 NUMBER_OF_CHANNELS 0 3 BITS_PER_SAMPLE 4 6 SAMPLE_BASE_DIVISOR 8 10 SAMPLE_BASE_MULTIPLE 11 13 SAMPLE_BASE_RATE 14 14 STREAM_TYPE 15 15 ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID 2 0x3 2 0 4294967295 CHANNEL_ID 0 3 STREAM_ID 4 7 ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER 2 0x4 10 0 4294967295 DIGEN 0 0 V 1 1 VCFG 2 2 PRE 3 3 COPY 4 4 NON_AUDIO 5 5 PRO 6 6 L 7 7 CC 8 14 KEEPALIVE 23 23 ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS 2 0x5 1 0 4294967295 STREAM_FORMATS 0 31 ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 2 0x6 2 0 4294967295 AUDIO_RATE_CAPABILITIES 0 11 AUDIO_BIT_CAPABILITIES 16 20 ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 2 0x20 13 0 4294967295 AUDIO_CHANNEL_CAPABILITIES 0 0 INPUT_AMPLIFIER_PRESENT 1 1 OUTPUT_AMPLIFIER_PRESENT 2 2 AMPLIFIER_PARAMETER_OVERRIDE 3 3 STRIPE 5 5 PROCESSING_WIDGET 6 6 UNSOLICITED_RESPONSE_CAPABILITY 7 7 CONNECTION_LIST 8 8 DIGITAL 9 9 POWER_CONTROL 10 10 LR_SWAP 11 11 AUDIO_WIDGET_CAPABILITIES_DELAY 16 19 TYPE 20 23 ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES 2 0x21 11 0 4294967295 IMPEDANCE_SENSE_CAPABLE 0 0 TRIGGER_REQUIRED 1 1 JACK_DETECTION_CAPABILITY 2 2 HEADPHONE_DRIVE_CAPABLE 3 3 OUTPUT_CAPABLE 4 4 INPUT_CAPABLE 5 5 BALANCED_I_O_PINS 6 6 HDMI 7 7 VREF_CONTROL 8 15 EAPD_CAPABLE 16 16 DP 24 24 ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE 2 0x22 2 0 4294967295 TAG 0 5 ENABLE 7 7 ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE 2 0x23 2 0 4294967295 IMPEDANCE_SENSE 0 30 PRESENCE_DETECT 31 31 ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL 2 0x24 1 0 4294967295 IN_ENABLE 5 5 ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE 2 0x36 12 0 4294967295 MULTICHANNEL0_ENABLE 0 0 MULTICHANNEL0_MUTE 1 1 MULTICHANNEL0_CHANNEL_ID 4 7 MULTICHANNEL1_ENABLE 8 8 MULTICHANNEL1_MUTE 9 9 MULTICHANNEL1_CHANNEL_ID 12 15 MULTICHANNEL2_ENABLE 16 16 MULTICHANNEL2_MUTE 17 17 MULTICHANNEL2_CHANNEL_ID 20 23 MULTICHANNEL3_ENABLE 24 24 MULTICHANNEL3_MUTE 25 25 MULTICHANNEL3_CHANNEL_ID 28 31 ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2 2 0x37 12 0 4294967295 MULTICHANNEL4_ENABLE 0 0 MULTICHANNEL4_MUTE 1 1 MULTICHANNEL4_CHANNEL_ID 4 7 MULTICHANNEL5_ENABLE 8 8 MULTICHANNEL5_MUTE 9 9 MULTICHANNEL5_CHANNEL_ID 12 15 MULTICHANNEL6_ENABLE 16 16 MULTICHANNEL6_MUTE 17 17 MULTICHANNEL6_CHANNEL_ID 20 23 MULTICHANNEL7_ENABLE 24 24 MULTICHANNEL7_MUTE 25 25 MULTICHANNEL7_CHANNEL_ID 28 31 ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR 2 0x38 2 0 4294967295 HBR_CAPABLE 0 0 HBR_ENABLE 4 4 ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION 2 0x53 1 0 4294967295 CHANNEL_ALLOCATION 0 7 ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL 2 0x54 3 0 4294967295 CLOCK_GATING_DISABLE 0 0 CLOCK_ON_STATE 4 4 AUDIO_ENABLED 31 31 ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 2 0x55 2 0 4294967295 UNSOLICITED_RESPONSE_PAYLOAD 0 25 UNSOLICITED_RESPONSE_FORCE 28 28 ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 2 0x56 8 0 4294967295 SEQUENCE 0 3 DEFAULT_ASSOCIATION 4 7 MISC 8 11 COLOR 12 15 CONNECTION_TYPE 16 19 DEFAULT_DEVICE 20 23 LOCATION 24 29 PORT_CONNECTIVITY 30 31 ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 2 0x64 2 0 4294967295 LPIB_SNAPSHOT_LOCK 0 0 CYCLIC_BUFFER_WRAP_COUNT 8 15 ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB 2 0x65 1 0 4294967295 LPIB 0 31 ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 2 0x66 1 0 4294967295 LPIB_TIMER_SNAPSHOT 0 31 ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL 2 0x67 4 0 4294967295 INPUT_ACTIVITY 0 0 CHANNEL_LAYOUT 1 2 INPUT_ACTIVITY_UR_ENABLE 4 4 INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE 5 5 ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME 2 0x68 4 0 4294967295 CHANNEL_COUNT 0 2 CHANNEL_ALLOCATION 8 15 INFOFRAME_BYTE_5 16 23 INFOFRAME_VALID 31 31 ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 2 0x1 14 0 4294967295 AUDIO_CHANNEL_CAPABILITIES 0 0 INPUT_AMPLIFIER_PRESENT 1 1 OUTPUT_AMPLIFIER_PRESENT 2 2 AMPLIFIER_PARAMETER_OVERRIDE 3 3 FORMAT_OVERRIDE 4 4 STRIPE 5 5 PROCESSING_WIDGET 6 6 UNSOLICITED_RESPONSE_CAPABILITY 7 7 CONNECTION_LIST 8 8 DIGITAL 9 9 POWER_CONTROL 10 10 LR_SWAP 11 11 AUDIO_WIDGET_CAPABILITIES_DELAY 16 19 TYPE 20 23 ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT 2 0x2 6 0 4294967295 NUMBER_OF_CHANNELS 0 3 BITS_PER_SAMPLE 4 6 SAMPLE_BASE_DIVISOR 8 10 SAMPLE_BASE_MULTIPLE 11 13 SAMPLE_BASE_RATE 14 14 STREAM_TYPE 15 15 ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID 2 0x3 2 0 4294967295 CHANNEL_ID 0 3 STREAM_ID 4 7 ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER 2 0x4 10 0 4294967295 DIGEN 0 0 V 1 1 VCFG 2 2 PRE 3 3 COPY 4 4 NON_AUDIO 5 5 PRO 6 6 L 7 7 CC 8 14 KEEPALIVE 23 23 ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS 2 0x5 1 0 4294967295 STREAM_FORMATS 0 31 ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 2 0x6 2 0 4294967295 AUDIO_RATE_CAPABILITIES 0 11 AUDIO_BIT_CAPABILITIES 16 20 ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 2 0x20 13 0 4294967295 AUDIO_CHANNEL_CAPABILITIES 0 0 INPUT_AMPLIFIER_PRESENT 1 1 OUTPUT_AMPLIFIER_PRESENT 2 2 AMPLIFIER_PARAMETER_OVERRIDE 3 3 STRIPE 5 5 PROCESSING_WIDGET 6 6 UNSOLICITED_RESPONSE_CAPABILITY 7 7 CONNECTION_LIST 8 8 DIGITAL 9 9 POWER_CONTROL 10 10 LR_SWAP 11 11 AUDIO_WIDGET_CAPABILITIES_DELAY 16 19 TYPE 20 23 ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES 2 0x21 11 0 4294967295 IMPEDANCE_SENSE_CAPABLE 0 0 TRIGGER_REQUIRED 1 1 JACK_DETECTION_CAPABILITY 2 2 HEADPHONE_DRIVE_CAPABLE 3 3 OUTPUT_CAPABLE 4 4 INPUT_CAPABLE 5 5 BALANCED_I_O_PINS 6 6 HDMI 7 7 VREF_CONTROL 8 15 EAPD_CAPABLE 16 16 DP 24 24 ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE 2 0x22 2 0 4294967295 TAG 0 5 ENABLE 7 7 ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE 2 0x23 2 0 4294967295 IMPEDANCE_SENSE 0 30 PRESENCE_DETECT 31 31 ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL 2 0x24 1 0 4294967295 IN_ENABLE 5 5 ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE 2 0x36 12 0 4294967295 MULTICHANNEL0_ENABLE 0 0 MULTICHANNEL0_MUTE 1 1 MULTICHANNEL0_CHANNEL_ID 4 7 MULTICHANNEL1_ENABLE 8 8 MULTICHANNEL1_MUTE 9 9 MULTICHANNEL1_CHANNEL_ID 12 15 MULTICHANNEL2_ENABLE 16 16 MULTICHANNEL2_MUTE 17 17 MULTICHANNEL2_CHANNEL_ID 20 23 MULTICHANNEL3_ENABLE 24 24 MULTICHANNEL3_MUTE 25 25 MULTICHANNEL3_CHANNEL_ID 28 31 ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2 2 0x37 12 0 4294967295 MULTICHANNEL4_ENABLE 0 0 MULTICHANNEL4_MUTE 1 1 MULTICHANNEL4_CHANNEL_ID 4 7 MULTICHANNEL5_ENABLE 8 8 MULTICHANNEL5_MUTE 9 9 MULTICHANNEL5_CHANNEL_ID 12 15 MULTICHANNEL6_ENABLE 16 16 MULTICHANNEL6_MUTE 17 17 MULTICHANNEL6_CHANNEL_ID 20 23 MULTICHANNEL7_ENABLE 24 24 MULTICHANNEL7_MUTE 25 25 MULTICHANNEL7_CHANNEL_ID 28 31 ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR 2 0x38 2 0 4294967295 HBR_CAPABLE 0 0 HBR_ENABLE 4 4 ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION 2 0x53 1 0 4294967295 CHANNEL_ALLOCATION 0 7 ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL 2 0x54 3 0 4294967295 CLOCK_GATING_DISABLE 0 0 CLOCK_ON_STATE 4 4 AUDIO_ENABLED 31 31 ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 2 0x55 2 0 4294967295 UNSOLICITED_RESPONSE_PAYLOAD 0 25 UNSOLICITED_RESPONSE_FORCE 28 28 ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 2 0x56 8 0 4294967295 SEQUENCE 0 3 DEFAULT_ASSOCIATION 4 7 MISC 8 11 COLOR 12 15 CONNECTION_TYPE 16 19 DEFAULT_DEVICE 20 23 LOCATION 24 29 PORT_CONNECTIVITY 30 31 ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 2 0x64 2 0 4294967295 LPIB_SNAPSHOT_LOCK 0 0 CYCLIC_BUFFER_WRAP_COUNT 8 15 ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB 2 0x65 1 0 4294967295 LPIB 0 31 ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 2 0x66 1 0 4294967295 LPIB_TIMER_SNAPSHOT 0 31 ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL 2 0x67 4 0 4294967295 INPUT_ACTIVITY 0 0 CHANNEL_LAYOUT 1 2 INPUT_ACTIVITY_UR_ENABLE 4 4 INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE 5 5 ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME 2 0x68 4 0 4294967295 CHANNEL_COUNT 0 2 CHANNEL_ALLOCATION 8 15 INFOFRAME_BYTE_5 16 23 INFOFRAME_VALID 31 31 ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 2 0x1 14 0 4294967295 AUDIO_CHANNEL_CAPABILITIES 0 0 INPUT_AMPLIFIER_PRESENT 1 1 OUTPUT_AMPLIFIER_PRESENT 2 2 AMPLIFIER_PARAMETER_OVERRIDE 3 3 FORMAT_OVERRIDE 4 4 STRIPE 5 5 PROCESSING_WIDGET 6 6 UNSOLICITED_RESPONSE_CAPABILITY 7 7 CONNECTION_LIST 8 8 DIGITAL 9 9 POWER_CONTROL 10 10 LR_SWAP 11 11 AUDIO_WIDGET_CAPABILITIES_DELAY 16 19 TYPE 20 23 ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT 2 0x2 6 0 4294967295 NUMBER_OF_CHANNELS 0 3 BITS_PER_SAMPLE 4 6 SAMPLE_BASE_DIVISOR 8 10 SAMPLE_BASE_MULTIPLE 11 13 SAMPLE_BASE_RATE 14 14 STREAM_TYPE 15 15 ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID 2 0x3 2 0 4294967295 CHANNEL_ID 0 3 STREAM_ID 4 7 ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER 2 0x4 10 0 4294967295 DIGEN 0 0 V 1 1 VCFG 2 2 PRE 3 3 COPY 4 4 NON_AUDIO 5 5 PRO 6 6 L 7 7 CC 8 14 KEEPALIVE 23 23 ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS 2 0x5 1 0 4294967295 STREAM_FORMATS 0 31 ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 2 0x6 2 0 4294967295 AUDIO_RATE_CAPABILITIES 0 11 AUDIO_BIT_CAPABILITIES 16 20 ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 2 0x20 13 0 4294967295 AUDIO_CHANNEL_CAPABILITIES 0 0 INPUT_AMPLIFIER_PRESENT 1 1 OUTPUT_AMPLIFIER_PRESENT 2 2 AMPLIFIER_PARAMETER_OVERRIDE 3 3 STRIPE 5 5 PROCESSING_WIDGET 6 6 UNSOLICITED_RESPONSE_CAPABILITY 7 7 CONNECTION_LIST 8 8 DIGITAL 9 9 POWER_CONTROL 10 10 LR_SWAP 11 11 AUDIO_WIDGET_CAPABILITIES_DELAY 16 19 TYPE 20 23 ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES 2 0x21 11 0 4294967295 IMPEDANCE_SENSE_CAPABLE 0 0 TRIGGER_REQUIRED 1 1 JACK_DETECTION_CAPABILITY 2 2 HEADPHONE_DRIVE_CAPABLE 3 3 OUTPUT_CAPABLE 4 4 INPUT_CAPABLE 5 5 BALANCED_I_O_PINS 6 6 HDMI 7 7 VREF_CONTROL 8 15 EAPD_CAPABLE 16 16 DP 24 24 ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE 2 0x22 2 0 4294967295 TAG 0 5 ENABLE 7 7 ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE 2 0x23 2 0 4294967295 IMPEDANCE_SENSE 0 30 PRESENCE_DETECT 31 31 ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL 2 0x24 1 0 4294967295 IN_ENABLE 5 5 ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE 2 0x36 12 0 4294967295 MULTICHANNEL0_ENABLE 0 0 MULTICHANNEL0_MUTE 1 1 MULTICHANNEL0_CHANNEL_ID 4 7 MULTICHANNEL1_ENABLE 8 8 MULTICHANNEL1_MUTE 9 9 MULTICHANNEL1_CHANNEL_ID 12 15 MULTICHANNEL2_ENABLE 16 16 MULTICHANNEL2_MUTE 17 17 MULTICHANNEL2_CHANNEL_ID 20 23 MULTICHANNEL3_ENABLE 24 24 MULTICHANNEL3_MUTE 25 25 MULTICHANNEL3_CHANNEL_ID 28 31 ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2 2 0x37 12 0 4294967295 MULTICHANNEL4_ENABLE 0 0 MULTICHANNEL4_MUTE 1 1 MULTICHANNEL4_CHANNEL_ID 4 7 MULTICHANNEL5_ENABLE 8 8 MULTICHANNEL5_MUTE 9 9 MULTICHANNEL5_CHANNEL_ID 12 15 MULTICHANNEL6_ENABLE 16 16 MULTICHANNEL6_MUTE 17 17 MULTICHANNEL6_CHANNEL_ID 20 23 MULTICHANNEL7_ENABLE 24 24 MULTICHANNEL7_MUTE 25 25 MULTICHANNEL7_CHANNEL_ID 28 31 ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR 2 0x38 2 0 4294967295 HBR_CAPABLE 0 0 HBR_ENABLE 4 4 ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION 2 0x53 1 0 4294967295 CHANNEL_ALLOCATION 0 7 ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL 2 0x54 3 0 4294967295 CLOCK_GATING_DISABLE 0 0 CLOCK_ON_STATE 4 4 AUDIO_ENABLED 31 31 ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 2 0x55 2 0 4294967295 UNSOLICITED_RESPONSE_PAYLOAD 0 25 UNSOLICITED_RESPONSE_FORCE 28 28 ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 2 0x56 8 0 4294967295 SEQUENCE 0 3 DEFAULT_ASSOCIATION 4 7 MISC 8 11 COLOR 12 15 CONNECTION_TYPE 16 19 DEFAULT_DEVICE 20 23 LOCATION 24 29 PORT_CONNECTIVITY 30 31 ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 2 0x64 2 0 4294967295 LPIB_SNAPSHOT_LOCK 0 0 CYCLIC_BUFFER_WRAP_COUNT 8 15 ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB 2 0x65 1 0 4294967295 LPIB 0 31 ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 2 0x66 1 0 4294967295 LPIB_TIMER_SNAPSHOT 0 31 ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL 2 0x67 4 0 4294967295 INPUT_ACTIVITY 0 0 CHANNEL_LAYOUT 1 2 INPUT_ACTIVITY_UR_ENABLE 4 4 INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE 5 5 ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME 2 0x68 4 0 4294967295 CHANNEL_COUNT 0 2 CHANNEL_ALLOCATION 8 15 INFOFRAME_BYTE_5 16 23 INFOFRAME_VALID 31 31 ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 2 0x1 14 0 4294967295 AUDIO_CHANNEL_CAPABILITIES 0 0 INPUT_AMPLIFIER_PRESENT 1 1 OUTPUT_AMPLIFIER_PRESENT 2 2 AMPLIFIER_PARAMETER_OVERRIDE 3 3 FORMAT_OVERRIDE 4 4 STRIPE 5 5 PROCESSING_WIDGET 6 6 UNSOLICITED_RESPONSE_CAPABILITY 7 7 CONNECTION_LIST 8 8 DIGITAL 9 9 POWER_CONTROL 10 10 LR_SWAP 11 11 AUDIO_WIDGET_CAPABILITIES_DELAY 16 19 TYPE 20 23 ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT 2 0x2 6 0 4294967295 NUMBER_OF_CHANNELS 0 3 BITS_PER_SAMPLE 4 6 SAMPLE_BASE_DIVISOR 8 10 SAMPLE_BASE_MULTIPLE 11 13 SAMPLE_BASE_RATE 14 14 STREAM_TYPE 15 15 ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID 2 0x3 2 0 4294967295 CHANNEL_ID 0 3 STREAM_ID 4 7 ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER 2 0x4 10 0 4294967295 DIGEN 0 0 V 1 1 VCFG 2 2 PRE 3 3 COPY 4 4 NON_AUDIO 5 5 PRO 6 6 L 7 7 CC 8 14 KEEPALIVE 23 23 ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS 2 0x5 1 0 4294967295 STREAM_FORMATS 0 31 ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 2 0x6 2 0 4294967295 AUDIO_RATE_CAPABILITIES 0 11 AUDIO_BIT_CAPABILITIES 16 20 ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 2 0x20 13 0 4294967295 AUDIO_CHANNEL_CAPABILITIES 0 0 INPUT_AMPLIFIER_PRESENT 1 1 OUTPUT_AMPLIFIER_PRESENT 2 2 AMPLIFIER_PARAMETER_OVERRIDE 3 3 STRIPE 5 5 PROCESSING_WIDGET 6 6 UNSOLICITED_RESPONSE_CAPABILITY 7 7 CONNECTION_LIST 8 8 DIGITAL 9 9 POWER_CONTROL 10 10 LR_SWAP 11 11 AUDIO_WIDGET_CAPABILITIES_DELAY 16 19 TYPE 20 23 ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES 2 0x21 11 0 4294967295 IMPEDANCE_SENSE_CAPABLE 0 0 TRIGGER_REQUIRED 1 1 JACK_DETECTION_CAPABILITY 2 2 HEADPHONE_DRIVE_CAPABLE 3 3 OUTPUT_CAPABLE 4 4 INPUT_CAPABLE 5 5 BALANCED_I_O_PINS 6 6 HDMI 7 7 VREF_CONTROL 8 15 EAPD_CAPABLE 16 16 DP 24 24 ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE 2 0x22 2 0 4294967295 TAG 0 5 ENABLE 7 7 ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE 2 0x23 2 0 4294967295 IMPEDANCE_SENSE 0 30 PRESENCE_DETECT 31 31 ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL 2 0x24 1 0 4294967295 IN_ENABLE 5 5 ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE 2 0x36 12 0 4294967295 MULTICHANNEL0_ENABLE 0 0 MULTICHANNEL0_MUTE 1 1 MULTICHANNEL0_CHANNEL_ID 4 7 MULTICHANNEL1_ENABLE 8 8 MULTICHANNEL1_MUTE 9 9 MULTICHANNEL1_CHANNEL_ID 12 15 MULTICHANNEL2_ENABLE 16 16 MULTICHANNEL2_MUTE 17 17 MULTICHANNEL2_CHANNEL_ID 20 23 MULTICHANNEL3_ENABLE 24 24 MULTICHANNEL3_MUTE 25 25 MULTICHANNEL3_CHANNEL_ID 28 31 ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2 2 0x37 12 0 4294967295 MULTICHANNEL4_ENABLE 0 0 MULTICHANNEL4_MUTE 1 1 MULTICHANNEL4_CHANNEL_ID 4 7 MULTICHANNEL5_ENABLE 8 8 MULTICHANNEL5_MUTE 9 9 MULTICHANNEL5_CHANNEL_ID 12 15 MULTICHANNEL6_ENABLE 16 16 MULTICHANNEL6_MUTE 17 17 MULTICHANNEL6_CHANNEL_ID 20 23 MULTICHANNEL7_ENABLE 24 24 MULTICHANNEL7_MUTE 25 25 MULTICHANNEL7_CHANNEL_ID 28 31 ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR 2 0x38 2 0 4294967295 HBR_CAPABLE 0 0 HBR_ENABLE 4 4 ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION 2 0x53 1 0 4294967295 CHANNEL_ALLOCATION 0 7 ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL 2 0x54 3 0 4294967295 CLOCK_GATING_DISABLE 0 0 CLOCK_ON_STATE 4 4 AUDIO_ENABLED 31 31 ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 2 0x55 2 0 4294967295 UNSOLICITED_RESPONSE_PAYLOAD 0 25 UNSOLICITED_RESPONSE_FORCE 28 28 ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 2 0x56 8 0 4294967295 SEQUENCE 0 3 DEFAULT_ASSOCIATION 4 7 MISC 8 11 COLOR 12 15 CONNECTION_TYPE 16 19 DEFAULT_DEVICE 20 23 LOCATION 24 29 PORT_CONNECTIVITY 30 31 ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 2 0x64 2 0 4294967295 LPIB_SNAPSHOT_LOCK 0 0 CYCLIC_BUFFER_WRAP_COUNT 8 15 ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB 2 0x65 1 0 4294967295 LPIB 0 31 ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 2 0x66 1 0 4294967295 LPIB_TIMER_SNAPSHOT 0 31 ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL 2 0x67 4 0 4294967295 INPUT_ACTIVITY 0 0 CHANNEL_LAYOUT 1 2 INPUT_ACTIVITY_UR_ENABLE 4 4 INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE 5 5 ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME 2 0x68 4 0 4294967295 CHANNEL_COUNT 0 2 CHANNEL_ALLOCATION 8 15 INFOFRAME_BYTE_5 16 23 INFOFRAME_VALID 31 31