273 mmDPCSTX0_DPCSTX_TX_CLOCK_CNTL 0 0x2928 4 0 2 DPCS_SYMCLK_GATE_DIS 0 0 DPCS_SYMCLK_EN 1 1 DPCS_SYMCLK_CLOCK_ON 2 2 DPCS_SYMCLK_DIV2_CLOCK_ON 3 3 mmDPCSTX0_DPCSTX_TX_CNTL 0 0x2929 8 0 2 DPCS_TX_PLL_UPDATE_REQ 12 12 DPCS_TX_PLL_UPDATE_PENDING 13 13 DPCS_TX_DATA_SWAP 14 14 DPCS_TX_DATA_ORDER_INVERT 15 15 DPCS_TX_FIFO_EN 16 16 DPCS_TX_FIFO_START 17 17 DPCS_TX_FIFO_RD_START_DELAY 20 23 DPCS_TX_SOFT_RESET 31 31 mmDPCSTX0_DPCSTX_CBUS_CNTL 0 0x292a 2 0 2 DPCS_CBUS_WR_CMD_DELAY 0 7 DPCS_CBUS_SOFT_RESET 31 31 mmDPCSTX0_DPCSTX_INTERRUPT_CNTL 0 0x292b 10 0 2 DPCS_REG_FIFO_OVERFLOW 0 0 DPCS_REG_ERROR_CLR 1 1 DPCS_REG_FIFO_ERROR_MASK 4 4 DPCS_TX0_FIFO_ERROR 8 8 DPCS_TX1_FIFO_ERROR 9 9 DPCS_TX2_FIFO_ERROR 10 10 DPCS_TX3_FIFO_ERROR 11 11 DPCS_TX_ERROR_CLR 12 12 DPCS_TX_FIFO_ERROR_MASK 16 16 DPCS_INTERRUPT_MASK 20 20 mmDPCSTX0_DPCSTX_PLL_UPDATE_ADDR 0 0x292c 1 0 2 DPCS_PLL_UPDATE_ADDR 0 17 mmDPCSTX0_DPCSTX_PLL_UPDATE_DATA 0 0x292d 1 0 2 DPCS_PLL_UPDATE_DATA 0 31 mmDPCSTX0_DPCSTX_DEBUG_CONFIG 0 0x292e 6 0 2 DPCS_DBG_EN 0 0 DPCS_DBG_CFGCLK_SEL 1 3 DPCS_DBG_TX_SYMCLK_SEL 4 6 DPCS_DBG_TX_SYMCLK_DIV2_SEL 8 10 DPCS_DBG_CBUS_DIS 14 14 DPCS_TEST_DEBUG_WRITE_EN 16 16 mmRDPCSTX0_RDPCSTX_CNTL 0 0x2930 13 0 2 RDPCS_CBUS_SOFT_RESET 0 0 RDPCS_SRAM_SOFT_RESET 4 4 RDPCS_TX_FIFO_LANE0_EN 12 12 RDPCS_TX_FIFO_LANE1_EN 13 13 RDPCS_TX_FIFO_LANE2_EN 14 14 RDPCS_TX_FIFO_LANE3_EN 15 15 RDPCS_TX_FIFO_EN 16 16 RDPCS_TX_FIFO_START 17 17 RDPCS_TX_FIFO_RD_START_DELAY 20 23 RDPCS_CR_REGISTER_BLOCK_EN 24 24 RDPCS_NON_DPALT_REGISTER_BLOCK_EN 25 25 RDPCS_DPALT_BLOCK_STATUS 26 26 RDPCS_TX_SOFT_RESET 31 31 mmRDPCSTX0_RDPCSTX_CLOCK_CNTL 0 0x2931 12 0 2 RDPCS_EXT_REFCLK_EN 0 0 RDPCS_SYMCLK_DIV2_TX0_EN 4 4 RDPCS_SYMCLK_DIV2_TX1_EN 5 5 RDPCS_SYMCLK_DIV2_TX2_EN 6 6 RDPCS_SYMCLK_DIV2_TX3_EN 7 7 RDPCS_SYMCLK_DIV2_GATE_DIS 8 8 RDPCS_SYMCLK_DIV2_EN 9 9 RDPCS_SYMCLK_DIV2_CLOCK_ON 10 10 RDPCS_SRAMCLK_GATE_DIS 12 12 RDPCS_SRAMCLK_EN 13 13 RDPCS_SRAMCLK_CLOCK_ON 14 14 RDPCS_SRAMCLK_BYPASS 16 16 mmRDPCSTX0_RDPCSTX_INTERRUPT_CONTROL 0 0x2932 15 0 2 RDPCS_REG_FIFO_OVERFLOW 0 0 RDPCS_DPALT_DISABLE_TOGGLE 1 1 RDPCS_DPALT_4LANE_TOGGLE 2 2 RDPCS_TX0_FIFO_ERROR 4 4 RDPCS_TX1_FIFO_ERROR 5 5 RDPCS_TX2_FIFO_ERROR 6 6 RDPCS_TX3_FIFO_ERROR 7 7 RDPCS_REG_ERROR_CLR 8 8 RDPCS_DPALT_DISABLE_TOGGLE_CLR 9 9 RDPCS_DPALT_4LANE_TOGGLE_CLR 10 10 RDPCS_TX_ERROR_CLR 12 12 RDPCS_REG_FIFO_ERROR_MASK 16 16 RDPCS_DPALT_DISABLE_TOGGLE_MASK 17 17 RDPCS_DPALT_4LANE_TOGGLE_MASK 18 18 RDPCS_TX_FIFO_ERROR_MASK 20 20 mmRDPCSTX0_RDPCSTX_PLL_UPDATE_DATA 0 0x2933 1 0 2 RDPCS_PLL_UPDATE_DATA 0 0 mmRDPCSTX0_RDPCS_TX_CR_ADDR 0 0x2934 1 0 2 RDPCS_TX_CR_ADDR 0 15 mmRDPCSTX0_RDPCS_TX_CR_DATA 0 0x2935 1 0 2 RDPCS_TX_CR_DATA 0 15 mmRDPCSTX0_RDPCS_TX_SRAM_CNTL 0 0x2936 3 0 2 RDPCS_MEM_PWR_DIS 20 20 RDPCS_MEM_PWR_FORCE 24 25 RDPCS_MEM_PWR_PWR_STATE 28 29 mmRDPCSTX0_RDPCSTX_MEM_POWER_CTRL 0 0x2937 7 0 2 RDPCS_FUSE_RM_FUSES 0 11 RDPCS_FUSE_CUSTOM_RM_FUSES 12 25 RDPCS_MEM_POWER_CTRL_PDP_BC1 26 26 RDPCS_MEM_POWER_CTRL_PDP_BC2 27 27 RDPCS_MEM_POWER_CTRL_HD_BC1 28 28 RDPCS_MEM_POWER_CTRL_HD_BC2 29 29 RDPCS_LIVMIN_DIS_SRAM 30 30 mmRDPCSTX0_RDPCSTX_MEM_POWER_CTRL2 0 0x2938 2 0 2 RDPCS_MEM_POWER_CTRL_POFF 0 1 RDPCS_MEM_POWER_CTRL_FISO 2 2 mmRDPCSTX0_RDPCSTX_SCRATCH 0 0x2939 1 0 2 RDPCSTX_SCRATCH 0 31 mmRDPCSTX0_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG 0 0x293c 3 0 2 RDPCS_DMCU_DPALT_DIS_BLOCK_REG 0 0 RDPCS_DMCU_DPALT_FORCE_SYMCLK_DIV2_DIS 4 4 RDPCS_DMCU_DPALT_CONTROL_SPARE 8 15 mmRDPCSTX0_RDPCSTX_DEBUG_CONFIG 0 0x293d 7 0 2 RDPCS_DBG_EN 0 0 RDPCS_DBG_SEL_ASYNC_8BIT 4 6 RDPCS_DBG_SEL_ASYNC_SWAP 7 7 RDPCS_DBG_SEL_TEST_CLK 8 12 RDPCS_DBG_CR_COUNT_EXPIRE 15 15 RDPCS_DBG_CR_COUNT_MAX 16 23 RDPCS_DBG_CR_COUNT 24 31 mmRDPCSTX0_RDPCSTX_PHY_CNTL0 0 0x2940 17 0 2 RDPCS_PHY_RESET 0 0 RDPCS_PHY_TCA_PHY_RESET 1 1 RDPCS_PHY_TCA_APB_RESET_N 2 2 RDPCS_PHY_TEST_POWERDOWN 3 3 RDPCS_PHY_DTB_OUT 4 5 RDPCS_PHY_HDMIMODE_ENABLE 8 8 RDPCS_PHY_REF_RANGE 9 13 RDPCS_PHY_TX_VBOOST_LVL 14 16 RDPCS_PHY_RTUNE_REQ 17 17 RDPCS_PHY_RTUNE_ACK 18 18 RDPCS_PHY_CR_PARA_SEL 20 20 RDPCS_PHY_CR_MUX_SEL 21 21 RDPCS_PHY_REF_CLKDET_EN 24 24 RDPCS_PHY_REF_CLKDET_RESULT 25 25 RDPCS_SRAM_INIT_DONE 28 28 RDPCS_SRAM_EXT_LD_DONE 29 29 RDPCS_SRAM_BYPASS 31 31 mmRDPCSTX0_RDPCSTX_PHY_CNTL1 0 0x2941 8 0 2 RDPCS_PHY_PG_MODE_EN 0 0 RDPCS_PHY_PCS_PWR_EN 1 1 RDPCS_PHY_PCS_PWR_STABLE 2 2 RDPCS_PHY_PMA_PWR_EN 3 3 RDPCS_PHY_PMA_PWR_STABLE 4 4 RDPCS_PHY_DP_PG_RESET 5 5 RDPCS_PHY_ANA_PWR_EN 6 6 RDPCS_PHY_ANA_PWR_STABLE 7 7 mmRDPCSTX0_RDPCSTX_PHY_CNTL2 0 0x2942 9 0 2 RDPCS_PHY_DP4_POR 3 3 RDPCS_PHY_DP_LANE0_RX2TX_PAR_LB_EN 4 4 RDPCS_PHY_DP_LANE1_RX2TX_PAR_LB_EN 5 5 RDPCS_PHY_DP_LANE2_RX2TX_PAR_LB_EN 6 6 RDPCS_PHY_DP_LANE3_RX2TX_PAR_LB_EN 7 7 RDPCS_PHY_DP_LANE0_TX2RX_SER_LB_EN 8 8 RDPCS_PHY_DP_LANE1_TX2RX_SER_LB_EN 9 9 RDPCS_PHY_DP_LANE2_TX2RX_SER_LB_EN 10 10 RDPCS_PHY_DP_LANE3_TX2RX_SER_LB_EN 11 11 mmRDPCSTX0_RDPCSTX_PHY_CNTL3 0 0x2943 24 0 2 RDPCS_PHY_DP_TX0_RESET 0 0 RDPCS_PHY_DP_TX0_DISABLE 1 1 RDPCS_PHY_DP_TX0_CLK_RDY 2 2 RDPCS_PHY_DP_TX0_DATA_EN 3 3 RDPCS_PHY_DP_TX0_REQ 4 4 RDPCS_PHY_DP_TX0_ACK 5 5 RDPCS_PHY_DP_TX1_RESET 8 8 RDPCS_PHY_DP_TX1_DISABLE 9 9 RDPCS_PHY_DP_TX1_CLK_RDY 10 10 RDPCS_PHY_DP_TX1_DATA_EN 11 11 RDPCS_PHY_DP_TX1_REQ 12 12 RDPCS_PHY_DP_TX1_ACK 13 13 RDPCS_PHY_DP_TX2_RESET 16 16 RDPCS_PHY_DP_TX2_DISABLE 17 17 RDPCS_PHY_DP_TX2_CLK_RDY 18 18 RDPCS_PHY_DP_TX2_DATA_EN 19 19 RDPCS_PHY_DP_TX2_REQ 20 20 RDPCS_PHY_DP_TX2_ACK 21 21 RDPCS_PHY_DP_TX3_RESET 24 24 RDPCS_PHY_DP_TX3_DISABLE 25 25 RDPCS_PHY_DP_TX3_CLK_RDY 26 26 RDPCS_PHY_DP_TX3_DATA_EN 27 27 RDPCS_PHY_DP_TX3_REQ 28 28 RDPCS_PHY_DP_TX3_ACK 29 29 mmRDPCSTX0_RDPCSTX_PHY_CNTL4 0 0x2944 16 0 2 RDPCS_PHY_DP_TX0_TERM_CTRL 0 2 RDPCS_PHY_DP_TX0_INVERT 4 4 RDPCS_PHY_DP_TX0_BYPASS_EQ_CALC 6 6 RDPCS_PHY_DP_TX0_HP_PROT_EN 7 7 RDPCS_PHY_DP_TX1_TERM_CTRL 8 10 RDPCS_PHY_DP_TX1_INVERT 12 12 RDPCS_PHY_DP_TX1_BYPASS_EQ_CALC 14 14 RDPCS_PHY_DP_TX1_HP_PROT_EN 15 15 RDPCS_PHY_DP_TX2_TERM_CTRL 16 18 RDPCS_PHY_DP_TX2_INVERT 20 20 RDPCS_PHY_DP_TX2_BYPASS_EQ_CALC 22 22 RDPCS_PHY_DP_TX2_HP_PROT_EN 23 23 RDPCS_PHY_DP_TX3_TERM_CTRL 24 26 RDPCS_PHY_DP_TX3_INVERT 28 28 RDPCS_PHY_DP_TX3_BYPASS_EQ_CALC 30 30 RDPCS_PHY_DP_TX3_HP_PROT_EN 31 31 mmRDPCSTX0_RDPCSTX_PHY_CNTL5 0 0x2945 20 0 2 RDPCS_PHY_DP_TX0_LPD 0 0 RDPCS_PHY_DP_TX0_RATE 1 3 RDPCS_PHY_DP_TX0_WIDTH 4 5 RDPCS_PHY_DP_TX0_DETRX_REQ 6 6 RDPCS_PHY_DP_TX0_DETRX_RESULT 7 7 RDPCS_PHY_DP_TX1_LPD 8 8 RDPCS_PHY_DP_TX1_RATE 9 11 RDPCS_PHY_DP_TX1_WIDTH 12 13 RDPCS_PHY_DP_TX1_DETRX_REQ 14 14 RDPCS_PHY_DP_TX1_DETRX_RESULT 15 15 RDPCS_PHY_DP_TX2_LPD 16 16 RDPCS_PHY_DP_TX2_RATE 17 19 RDPCS_PHY_DP_TX2_WIDTH 20 21 RDPCS_PHY_DP_TX2_DETRX_REQ 22 22 RDPCS_PHY_DP_TX2_DETRX_RESULT 23 23 RDPCS_PHY_DP_TX3_LPD 24 24 RDPCS_PHY_DP_TX3_RATE 25 27 RDPCS_PHY_DP_TX3_WIDTH 28 29 RDPCS_PHY_DP_TX3_DETRX_REQ 30 30 RDPCS_PHY_DP_TX3_DETRX_RESULT 31 31 mmRDPCSTX0_RDPCSTX_PHY_CNTL6 0 0x2946 13 0 2 RDPCS_PHY_DP_TX0_PSTATE 0 1 RDPCS_PHY_DP_TX0_MPLL_EN 2 2 RDPCS_PHY_DP_TX1_PSTATE 4 5 RDPCS_PHY_DP_TX1_MPLL_EN 6 6 RDPCS_PHY_DP_TX2_PSTATE 8 9 RDPCS_PHY_DP_TX2_MPLL_EN 10 10 RDPCS_PHY_DP_TX3_PSTATE 12 13 RDPCS_PHY_DP_TX3_MPLL_EN 14 14 RDPCS_PHY_DPALT_DP4 16 16 RDPCS_PHY_DPALT_DISABLE 17 17 RDPCS_PHY_DPALT_DISABLE_ACK 18 18 RDPCS_PHY_DP_REF_CLK_EN 19 19 RDPCS_PHY_DP_REF_CLK_REQ 20 20 mmRDPCSTX0_RDPCSTX_PHY_CNTL7 0 0x2947 2 0 2 RDPCS_PHY_DP_MPLLB_FRACN_DEN 0 15 RDPCS_PHY_DP_MPLLB_FRACN_QUOT 16 31 mmRDPCSTX0_RDPCSTX_PHY_CNTL8 0 0x2948 1 0 2 RDPCS_PHY_DP_MPLLB_SSC_PEAK 0 19 mmRDPCSTX0_RDPCSTX_PHY_CNTL9 0 0x2949 2 0 2 RDPCS_PHY_DP_MPLLB_SSC_STEPSIZE 0 20 RDPCS_PHY_DP_MPLLB_SSC_UP_SPREAD 24 24 mmRDPCSTX0_RDPCSTX_PHY_CNTL10 0 0x294a 1 0 2 RDPCS_PHY_DP_MPLLB_FRACN_REM 0 15 mmRDPCSTX0_RDPCSTX_PHY_CNTL11 0 0x294b 4 0 2 RDPCS_PHY_DP_MPLLB_MULTIPLIER 4 15 RDPCS_PHY_HDMI_MPLLB_HDMI_DIV 16 18 RDPCS_PHY_DP_REF_CLK_MPLLB_DIV 20 22 RDPCS_PHY_HDMI_MPLLB_HDMI_PIXEL_CLK_DIV 24 25 mmRDPCSTX0_RDPCSTX_PHY_CNTL12 0 0x294c 5 0 2 RDPCS_PHY_DP_MPLLB_DIV5_CLK_EN 0 0 RDPCS_PHY_DP_MPLLB_WORD_DIV2_EN 2 2 RDPCS_PHY_DP_MPLLB_TX_CLK_DIV 4 6 RDPCS_PHY_DP_MPLLB_STATE 7 7 RDPCS_PHY_DP_MPLLB_SSC_EN 8 8 mmRDPCSTX0_RDPCSTX_PHY_CNTL13 0 0x294d 4 0 2 RDPCS_PHY_DP_MPLLB_DIV_MULTIPLIER 20 27 RDPCS_PHY_DP_MPLLB_DIV_CLK_EN 28 28 RDPCS_PHY_DP_MPLLB_FORCE_EN 29 29 RDPCS_PHY_DP_MPLLB_INIT_CAL_DISABLE 30 30 mmRDPCSTX0_RDPCSTX_PHY_CNTL14 0 0x294e 3 0 2 RDPCS_PHY_DP_MPLLB_CAL_FORCE 0 0 RDPCS_PHY_DP_MPLLB_FRACN_EN 24 24 RDPCS_PHY_DP_MPLLB_PMIX_EN 28 28 mmRDPCSTX0_RDPCSTX_PHY_FUSE0 0 0x294f 5 0 2 RDPCS_PHY_DP_TX0_EQ_MAIN 0 5 RDPCS_PHY_DP_TX0_EQ_PRE 6 11 RDPCS_PHY_DP_TX0_EQ_POST 12 17 RDPCS_PHY_DP_MPLLB_V2I 18 19 RDPCS_PHY_DP_MPLLB_FREQ_VCO 20 21 mmRDPCSTX0_RDPCSTX_PHY_FUSE1 0 0x2950 5 0 2 RDPCS_PHY_DP_TX1_EQ_MAIN 0 5 RDPCS_PHY_DP_TX1_EQ_PRE 6 11 RDPCS_PHY_DP_TX1_EQ_POST 12 17 RDPCS_PHY_DP_MPLLB_CP_INT 18 24 RDPCS_PHY_DP_MPLLB_CP_PROP 25 31 mmRDPCSTX0_RDPCSTX_PHY_FUSE2 0 0x2951 3 0 2 RDPCS_PHY_DP_TX2_EQ_MAIN 0 5 RDPCS_PHY_DP_TX2_EQ_PRE 6 11 RDPCS_PHY_DP_TX2_EQ_POST 12 17 mmRDPCSTX0_RDPCSTX_PHY_FUSE3 0 0x2952 5 0 2 RDPCS_PHY_DP_TX3_EQ_MAIN 0 5 RDPCS_PHY_DP_TX3_EQ_PRE 6 11 RDPCS_PHY_DP_TX3_EQ_POST 12 17 RDPCS_PHY_DCO_FINETUNE 18 23 RDPCS_PHY_DCO_RANGE 24 25 mmRDPCSTX0_RDPCSTX_PHY_RX_LD_VAL 0 0x2953 2 0 2 RDPCS_PHY_RX_REF_LD_VAL 0 6 RDPCS_PHY_RX_VCO_LD_VAL 8 20 mmRDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3 0 0x2954 24 0 2 RDPCS_PHY_DP_TX0_RESET_RESERVED 0 0 RDPCS_PHY_DP_TX0_DISABLE_RESERVED 1 1 RDPCS_PHY_DP_TX0_CLK_RDY_RESERVED 2 2 RDPCS_PHY_DP_TX0_DATA_EN_RESERVED 3 3 RDPCS_PHY_DP_TX0_REQ_RESERVED 4 4 RDPCS_PHY_DP_TX0_ACK_RESERVED 5 5 RDPCS_PHY_DP_TX1_RESET_RESERVED 8 8 RDPCS_PHY_DP_TX1_DISABLE_RESERVED 9 9 RDPCS_PHY_DP_TX1_CLK_RDY_RESERVED 10 10 RDPCS_PHY_DP_TX1_DATA_EN_RESERVED 11 11 RDPCS_PHY_DP_TX1_REQ_RESERVED 12 12 RDPCS_PHY_DP_TX1_ACK_RESERVED 13 13 RDPCS_PHY_DP_TX2_RESET_RESERVED 16 16 RDPCS_PHY_DP_TX2_DISABLE_RESERVED 17 17 RDPCS_PHY_DP_TX2_CLK_RDY_RESERVED 18 18 RDPCS_PHY_DP_TX2_DATA_EN_RESERVED 19 19 RDPCS_PHY_DP_TX2_REQ_RESERVED 20 20 RDPCS_PHY_DP_TX2_ACK_RESERVED 21 21 RDPCS_PHY_DP_TX3_RESET_RESERVED 24 24 RDPCS_PHY_DP_TX3_DISABLE_RESERVED 25 25 RDPCS_PHY_DP_TX3_CLK_RDY_RESERVED 26 26 RDPCS_PHY_DP_TX3_DATA_EN_RESERVED 27 27 RDPCS_PHY_DP_TX3_REQ_RESERVED 28 28 RDPCS_PHY_DP_TX3_ACK_RESERVED 29 29 mmRDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL6 0 0x2955 13 0 2 RDPCS_PHY_DP_TX0_PSTATE_RESERVED 0 1 RDPCS_PHY_DP_TX0_MPLL_EN_RESERVED 2 2 RDPCS_PHY_DP_TX1_PSTATE_RESERVED 4 5 RDPCS_PHY_DP_TX1_MPLL_EN_RESERVED 6 6 RDPCS_PHY_DP_TX2_PSTATE_RESERVED 8 9 RDPCS_PHY_DP_TX2_MPLL_EN_RESERVED 10 10 RDPCS_PHY_DP_TX3_PSTATE_RESERVED 12 13 RDPCS_PHY_DP_TX3_MPLL_EN_RESERVED 14 14 RDPCS_PHY_DPALT_DP4_RESERVED 16 16 RDPCS_PHY_DPALT_DISABLE_RESERVED 17 17 RDPCS_PHY_DPALT_DISABLE_ACK_RESERVED 18 18 RDPCS_PHY_DP_REF_CLK_EN_RESERVED 19 19 RDPCS_PHY_DP_REF_CLK_REQ_RESERVED 20 20 mmRDPCSTX0_RDPCSTX_DPALT_CONTROL_REG 0 0x2956 3 0 2 RDPCS_ALLOW_DRIVER_ACCESS 0 0 RDPCS_DRIVER_ACCESS_BLOCKED 4 4 RDPCS_DPALT_CONTROL_SPARE 8 15 mmDPCSSYS_CR0_DPCSSYS_CR_ADDR 0 0x2934 1 0 2 RDPCS_TX_CR_ADDR 0 15 mmDPCSSYS_CR0_DPCSSYS_CR_DATA 0 0x2935 1 0 2 RDPCS_TX_CR_DATA 0 15 mmDPCSTX1_DPCSTX_TX_CLOCK_CNTL 0 0x2a00 4 0 2 DPCS_SYMCLK_GATE_DIS 0 0 DPCS_SYMCLK_EN 1 1 DPCS_SYMCLK_CLOCK_ON 2 2 DPCS_SYMCLK_DIV2_CLOCK_ON 3 3 mmDPCSTX1_DPCSTX_TX_CNTL 0 0x2a01 8 0 2 DPCS_TX_PLL_UPDATE_REQ 12 12 DPCS_TX_PLL_UPDATE_PENDING 13 13 DPCS_TX_DATA_SWAP 14 14 DPCS_TX_DATA_ORDER_INVERT 15 15 DPCS_TX_FIFO_EN 16 16 DPCS_TX_FIFO_START 17 17 DPCS_TX_FIFO_RD_START_DELAY 20 23 DPCS_TX_SOFT_RESET 31 31 mmDPCSTX1_DPCSTX_CBUS_CNTL 0 0x2a02 2 0 2 DPCS_CBUS_WR_CMD_DELAY 0 7 DPCS_CBUS_SOFT_RESET 31 31 mmDPCSTX1_DPCSTX_INTERRUPT_CNTL 0 0x2a03 10 0 2 DPCS_REG_FIFO_OVERFLOW 0 0 DPCS_REG_ERROR_CLR 1 1 DPCS_REG_FIFO_ERROR_MASK 4 4 DPCS_TX0_FIFO_ERROR 8 8 DPCS_TX1_FIFO_ERROR 9 9 DPCS_TX2_FIFO_ERROR 10 10 DPCS_TX3_FIFO_ERROR 11 11 DPCS_TX_ERROR_CLR 12 12 DPCS_TX_FIFO_ERROR_MASK 16 16 DPCS_INTERRUPT_MASK 20 20 mmDPCSTX1_DPCSTX_PLL_UPDATE_ADDR 0 0x2a04 1 0 2 DPCS_PLL_UPDATE_ADDR 0 17 mmDPCSTX1_DPCSTX_PLL_UPDATE_DATA 0 0x2a05 1 0 2 DPCS_PLL_UPDATE_DATA 0 31 mmDPCSTX1_DPCSTX_DEBUG_CONFIG 0 0x2a06 6 0 2 DPCS_DBG_EN 0 0 DPCS_DBG_CFGCLK_SEL 1 3 DPCS_DBG_TX_SYMCLK_SEL 4 6 DPCS_DBG_TX_SYMCLK_DIV2_SEL 8 10 DPCS_DBG_CBUS_DIS 14 14 DPCS_TEST_DEBUG_WRITE_EN 16 16 mmRDPCSTX1_RDPCSTX_CNTL 0 0x2a08 13 0 2 RDPCS_CBUS_SOFT_RESET 0 0 RDPCS_SRAM_SOFT_RESET 4 4 RDPCS_TX_FIFO_LANE0_EN 12 12 RDPCS_TX_FIFO_LANE1_EN 13 13 RDPCS_TX_FIFO_LANE2_EN 14 14 RDPCS_TX_FIFO_LANE3_EN 15 15 RDPCS_TX_FIFO_EN 16 16 RDPCS_TX_FIFO_START 17 17 RDPCS_TX_FIFO_RD_START_DELAY 20 23 RDPCS_CR_REGISTER_BLOCK_EN 24 24 RDPCS_NON_DPALT_REGISTER_BLOCK_EN 25 25 RDPCS_DPALT_BLOCK_STATUS 26 26 RDPCS_TX_SOFT_RESET 31 31 mmRDPCSTX1_RDPCSTX_CLOCK_CNTL 0 0x2a09 12 0 2 RDPCS_EXT_REFCLK_EN 0 0 RDPCS_SYMCLK_DIV2_TX0_EN 4 4 RDPCS_SYMCLK_DIV2_TX1_EN 5 5 RDPCS_SYMCLK_DIV2_TX2_EN 6 6 RDPCS_SYMCLK_DIV2_TX3_EN 7 7 RDPCS_SYMCLK_DIV2_GATE_DIS 8 8 RDPCS_SYMCLK_DIV2_EN 9 9 RDPCS_SYMCLK_DIV2_CLOCK_ON 10 10 RDPCS_SRAMCLK_GATE_DIS 12 12 RDPCS_SRAMCLK_EN 13 13 RDPCS_SRAMCLK_CLOCK_ON 14 14 RDPCS_SRAMCLK_BYPASS 16 16 mmRDPCSTX1_RDPCSTX_INTERRUPT_CONTROL 0 0x2a0a 15 0 2 RDPCS_REG_FIFO_OVERFLOW 0 0 RDPCS_DPALT_DISABLE_TOGGLE 1 1 RDPCS_DPALT_4LANE_TOGGLE 2 2 RDPCS_TX0_FIFO_ERROR 4 4 RDPCS_TX1_FIFO_ERROR 5 5 RDPCS_TX2_FIFO_ERROR 6 6 RDPCS_TX3_FIFO_ERROR 7 7 RDPCS_REG_ERROR_CLR 8 8 RDPCS_DPALT_DISABLE_TOGGLE_CLR 9 9 RDPCS_DPALT_4LANE_TOGGLE_CLR 10 10 RDPCS_TX_ERROR_CLR 12 12 RDPCS_REG_FIFO_ERROR_MASK 16 16 RDPCS_DPALT_DISABLE_TOGGLE_MASK 17 17 RDPCS_DPALT_4LANE_TOGGLE_MASK 18 18 RDPCS_TX_FIFO_ERROR_MASK 20 20 mmRDPCSTX1_RDPCSTX_PLL_UPDATE_DATA 0 0x2a0b 1 0 2 RDPCS_PLL_UPDATE_DATA 0 0 mmRDPCSTX1_RDPCS_TX_CR_ADDR 0 0x2a0c 1 0 2 RDPCS_TX_CR_ADDR 0 15 mmRDPCSTX1_RDPCS_TX_CR_DATA 0 0x2a0d 1 0 2 RDPCS_TX_CR_DATA 0 15 mmRDPCSTX1_RDPCS_TX_SRAM_CNTL 0 0x2a0e 3 0 2 RDPCS_MEM_PWR_DIS 20 20 RDPCS_MEM_PWR_FORCE 24 25 RDPCS_MEM_PWR_PWR_STATE 28 29 mmRDPCSTX1_RDPCSTX_MEM_POWER_CTRL 0 0x2a0f 7 0 2 RDPCS_FUSE_RM_FUSES 0 11 RDPCS_FUSE_CUSTOM_RM_FUSES 12 25 RDPCS_MEM_POWER_CTRL_PDP_BC1 26 26 RDPCS_MEM_POWER_CTRL_PDP_BC2 27 27 RDPCS_MEM_POWER_CTRL_HD_BC1 28 28 RDPCS_MEM_POWER_CTRL_HD_BC2 29 29 RDPCS_LIVMIN_DIS_SRAM 30 30 mmRDPCSTX1_RDPCSTX_MEM_POWER_CTRL2 0 0x2a10 2 0 2 RDPCS_MEM_POWER_CTRL_POFF 0 1 RDPCS_MEM_POWER_CTRL_FISO 2 2 mmRDPCSTX1_RDPCSTX_SCRATCH 0 0x2a11 1 0 2 RDPCSTX_SCRATCH 0 31 mmRDPCSTX1_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG 0 0x2a14 3 0 2 RDPCS_DMCU_DPALT_DIS_BLOCK_REG 0 0 RDPCS_DMCU_DPALT_FORCE_SYMCLK_DIV2_DIS 4 4 RDPCS_DMCU_DPALT_CONTROL_SPARE 8 15 mmRDPCSTX1_RDPCSTX_DEBUG_CONFIG 0 0x2a15 7 0 2 RDPCS_DBG_EN 0 0 RDPCS_DBG_SEL_ASYNC_8BIT 4 6 RDPCS_DBG_SEL_ASYNC_SWAP 7 7 RDPCS_DBG_SEL_TEST_CLK 8 12 RDPCS_DBG_CR_COUNT_EXPIRE 15 15 RDPCS_DBG_CR_COUNT_MAX 16 23 RDPCS_DBG_CR_COUNT 24 31 mmRDPCSTX1_RDPCSTX_PHY_CNTL0 0 0x2a18 17 0 2 RDPCS_PHY_RESET 0 0 RDPCS_PHY_TCA_PHY_RESET 1 1 RDPCS_PHY_TCA_APB_RESET_N 2 2 RDPCS_PHY_TEST_POWERDOWN 3 3 RDPCS_PHY_DTB_OUT 4 5 RDPCS_PHY_HDMIMODE_ENABLE 8 8 RDPCS_PHY_REF_RANGE 9 13 RDPCS_PHY_TX_VBOOST_LVL 14 16 RDPCS_PHY_RTUNE_REQ 17 17 RDPCS_PHY_RTUNE_ACK 18 18 RDPCS_PHY_CR_PARA_SEL 20 20 RDPCS_PHY_CR_MUX_SEL 21 21 RDPCS_PHY_REF_CLKDET_EN 24 24 RDPCS_PHY_REF_CLKDET_RESULT 25 25 RDPCS_SRAM_INIT_DONE 28 28 RDPCS_SRAM_EXT_LD_DONE 29 29 RDPCS_SRAM_BYPASS 31 31 mmRDPCSTX1_RDPCSTX_PHY_CNTL1 0 0x2a19 8 0 2 RDPCS_PHY_PG_MODE_EN 0 0 RDPCS_PHY_PCS_PWR_EN 1 1 RDPCS_PHY_PCS_PWR_STABLE 2 2 RDPCS_PHY_PMA_PWR_EN 3 3 RDPCS_PHY_PMA_PWR_STABLE 4 4 RDPCS_PHY_DP_PG_RESET 5 5 RDPCS_PHY_ANA_PWR_EN 6 6 RDPCS_PHY_ANA_PWR_STABLE 7 7 mmRDPCSTX1_RDPCSTX_PHY_CNTL2 0 0x2a1a 9 0 2 RDPCS_PHY_DP4_POR 3 3 RDPCS_PHY_DP_LANE0_RX2TX_PAR_LB_EN 4 4 RDPCS_PHY_DP_LANE1_RX2TX_PAR_LB_EN 5 5 RDPCS_PHY_DP_LANE2_RX2TX_PAR_LB_EN 6 6 RDPCS_PHY_DP_LANE3_RX2TX_PAR_LB_EN 7 7 RDPCS_PHY_DP_LANE0_TX2RX_SER_LB_EN 8 8 RDPCS_PHY_DP_LANE1_TX2RX_SER_LB_EN 9 9 RDPCS_PHY_DP_LANE2_TX2RX_SER_LB_EN 10 10 RDPCS_PHY_DP_LANE3_TX2RX_SER_LB_EN 11 11 mmRDPCSTX1_RDPCSTX_PHY_CNTL3 0 0x2a1b 24 0 2 RDPCS_PHY_DP_TX0_RESET 0 0 RDPCS_PHY_DP_TX0_DISABLE 1 1 RDPCS_PHY_DP_TX0_CLK_RDY 2 2 RDPCS_PHY_DP_TX0_DATA_EN 3 3 RDPCS_PHY_DP_TX0_REQ 4 4 RDPCS_PHY_DP_TX0_ACK 5 5 RDPCS_PHY_DP_TX1_RESET 8 8 RDPCS_PHY_DP_TX1_DISABLE 9 9 RDPCS_PHY_DP_TX1_CLK_RDY 10 10 RDPCS_PHY_DP_TX1_DATA_EN 11 11 RDPCS_PHY_DP_TX1_REQ 12 12 RDPCS_PHY_DP_TX1_ACK 13 13 RDPCS_PHY_DP_TX2_RESET 16 16 RDPCS_PHY_DP_TX2_DISABLE 17 17 RDPCS_PHY_DP_TX2_CLK_RDY 18 18 RDPCS_PHY_DP_TX2_DATA_EN 19 19 RDPCS_PHY_DP_TX2_REQ 20 20 RDPCS_PHY_DP_TX2_ACK 21 21 RDPCS_PHY_DP_TX3_RESET 24 24 RDPCS_PHY_DP_TX3_DISABLE 25 25 RDPCS_PHY_DP_TX3_CLK_RDY 26 26 RDPCS_PHY_DP_TX3_DATA_EN 27 27 RDPCS_PHY_DP_TX3_REQ 28 28 RDPCS_PHY_DP_TX3_ACK 29 29 mmRDPCSTX1_RDPCSTX_PHY_CNTL4 0 0x2a1c 16 0 2 RDPCS_PHY_DP_TX0_TERM_CTRL 0 2 RDPCS_PHY_DP_TX0_INVERT 4 4 RDPCS_PHY_DP_TX0_BYPASS_EQ_CALC 6 6 RDPCS_PHY_DP_TX0_HP_PROT_EN 7 7 RDPCS_PHY_DP_TX1_TERM_CTRL 8 10 RDPCS_PHY_DP_TX1_INVERT 12 12 RDPCS_PHY_DP_TX1_BYPASS_EQ_CALC 14 14 RDPCS_PHY_DP_TX1_HP_PROT_EN 15 15 RDPCS_PHY_DP_TX2_TERM_CTRL 16 18 RDPCS_PHY_DP_TX2_INVERT 20 20 RDPCS_PHY_DP_TX2_BYPASS_EQ_CALC 22 22 RDPCS_PHY_DP_TX2_HP_PROT_EN 23 23 RDPCS_PHY_DP_TX3_TERM_CTRL 24 26 RDPCS_PHY_DP_TX3_INVERT 28 28 RDPCS_PHY_DP_TX3_BYPASS_EQ_CALC 30 30 RDPCS_PHY_DP_TX3_HP_PROT_EN 31 31 mmRDPCSTX1_RDPCSTX_PHY_CNTL5 0 0x2a1d 20 0 2 RDPCS_PHY_DP_TX0_LPD 0 0 RDPCS_PHY_DP_TX0_RATE 1 3 RDPCS_PHY_DP_TX0_WIDTH 4 5 RDPCS_PHY_DP_TX0_DETRX_REQ 6 6 RDPCS_PHY_DP_TX0_DETRX_RESULT 7 7 RDPCS_PHY_DP_TX1_LPD 8 8 RDPCS_PHY_DP_TX1_RATE 9 11 RDPCS_PHY_DP_TX1_WIDTH 12 13 RDPCS_PHY_DP_TX1_DETRX_REQ 14 14 RDPCS_PHY_DP_TX1_DETRX_RESULT 15 15 RDPCS_PHY_DP_TX2_LPD 16 16 RDPCS_PHY_DP_TX2_RATE 17 19 RDPCS_PHY_DP_TX2_WIDTH 20 21 RDPCS_PHY_DP_TX2_DETRX_REQ 22 22 RDPCS_PHY_DP_TX2_DETRX_RESULT 23 23 RDPCS_PHY_DP_TX3_LPD 24 24 RDPCS_PHY_DP_TX3_RATE 25 27 RDPCS_PHY_DP_TX3_WIDTH 28 29 RDPCS_PHY_DP_TX3_DETRX_REQ 30 30 RDPCS_PHY_DP_TX3_DETRX_RESULT 31 31 mmRDPCSTX1_RDPCSTX_PHY_CNTL6 0 0x2a1e 13 0 2 RDPCS_PHY_DP_TX0_PSTATE 0 1 RDPCS_PHY_DP_TX0_MPLL_EN 2 2 RDPCS_PHY_DP_TX1_PSTATE 4 5 RDPCS_PHY_DP_TX1_MPLL_EN 6 6 RDPCS_PHY_DP_TX2_PSTATE 8 9 RDPCS_PHY_DP_TX2_MPLL_EN 10 10 RDPCS_PHY_DP_TX3_PSTATE 12 13 RDPCS_PHY_DP_TX3_MPLL_EN 14 14 RDPCS_PHY_DPALT_DP4 16 16 RDPCS_PHY_DPALT_DISABLE 17 17 RDPCS_PHY_DPALT_DISABLE_ACK 18 18 RDPCS_PHY_DP_REF_CLK_EN 19 19 RDPCS_PHY_DP_REF_CLK_REQ 20 20 mmRDPCSTX1_RDPCSTX_PHY_CNTL7 0 0x2a1f 2 0 2 RDPCS_PHY_DP_MPLLB_FRACN_DEN 0 15 RDPCS_PHY_DP_MPLLB_FRACN_QUOT 16 31 mmRDPCSTX1_RDPCSTX_PHY_CNTL8 0 0x2a20 1 0 2 RDPCS_PHY_DP_MPLLB_SSC_PEAK 0 19 mmRDPCSTX1_RDPCSTX_PHY_CNTL9 0 0x2a21 2 0 2 RDPCS_PHY_DP_MPLLB_SSC_STEPSIZE 0 20 RDPCS_PHY_DP_MPLLB_SSC_UP_SPREAD 24 24 mmRDPCSTX1_RDPCSTX_PHY_CNTL10 0 0x2a22 1 0 2 RDPCS_PHY_DP_MPLLB_FRACN_REM 0 15 mmRDPCSTX1_RDPCSTX_PHY_CNTL11 0 0x2a23 4 0 2 RDPCS_PHY_DP_MPLLB_MULTIPLIER 4 15 RDPCS_PHY_HDMI_MPLLB_HDMI_DIV 16 18 RDPCS_PHY_DP_REF_CLK_MPLLB_DIV 20 22 RDPCS_PHY_HDMI_MPLLB_HDMI_PIXEL_CLK_DIV 24 25 mmRDPCSTX1_RDPCSTX_PHY_CNTL12 0 0x2a24 5 0 2 RDPCS_PHY_DP_MPLLB_DIV5_CLK_EN 0 0 RDPCS_PHY_DP_MPLLB_WORD_DIV2_EN 2 2 RDPCS_PHY_DP_MPLLB_TX_CLK_DIV 4 6 RDPCS_PHY_DP_MPLLB_STATE 7 7 RDPCS_PHY_DP_MPLLB_SSC_EN 8 8 mmRDPCSTX1_RDPCSTX_PHY_CNTL13 0 0x2a25 4 0 2 RDPCS_PHY_DP_MPLLB_DIV_MULTIPLIER 20 27 RDPCS_PHY_DP_MPLLB_DIV_CLK_EN 28 28 RDPCS_PHY_DP_MPLLB_FORCE_EN 29 29 RDPCS_PHY_DP_MPLLB_INIT_CAL_DISABLE 30 30 mmRDPCSTX1_RDPCSTX_PHY_CNTL14 0 0x2a26 3 0 2 RDPCS_PHY_DP_MPLLB_CAL_FORCE 0 0 RDPCS_PHY_DP_MPLLB_FRACN_EN 24 24 RDPCS_PHY_DP_MPLLB_PMIX_EN 28 28 mmRDPCSTX1_RDPCSTX_PHY_FUSE0 0 0x2a27 5 0 2 RDPCS_PHY_DP_TX0_EQ_MAIN 0 5 RDPCS_PHY_DP_TX0_EQ_PRE 6 11 RDPCS_PHY_DP_TX0_EQ_POST 12 17 RDPCS_PHY_DP_MPLLB_V2I 18 19 RDPCS_PHY_DP_MPLLB_FREQ_VCO 20 21 mmRDPCSTX1_RDPCSTX_PHY_FUSE1 0 0x2a28 5 0 2 RDPCS_PHY_DP_TX1_EQ_MAIN 0 5 RDPCS_PHY_DP_TX1_EQ_PRE 6 11 RDPCS_PHY_DP_TX1_EQ_POST 12 17 RDPCS_PHY_DP_MPLLB_CP_INT 18 24 RDPCS_PHY_DP_MPLLB_CP_PROP 25 31 mmRDPCSTX1_RDPCSTX_PHY_FUSE2 0 0x2a29 3 0 2 RDPCS_PHY_DP_TX2_EQ_MAIN 0 5 RDPCS_PHY_DP_TX2_EQ_PRE 6 11 RDPCS_PHY_DP_TX2_EQ_POST 12 17 mmRDPCSTX1_RDPCSTX_PHY_FUSE3 0 0x2a2a 5 0 2 RDPCS_PHY_DP_TX3_EQ_MAIN 0 5 RDPCS_PHY_DP_TX3_EQ_PRE 6 11 RDPCS_PHY_DP_TX3_EQ_POST 12 17 RDPCS_PHY_DCO_FINETUNE 18 23 RDPCS_PHY_DCO_RANGE 24 25 mmRDPCSTX1_RDPCSTX_PHY_RX_LD_VAL 0 0x2a2b 2 0 2 RDPCS_PHY_RX_REF_LD_VAL 0 6 RDPCS_PHY_RX_VCO_LD_VAL 8 20 mmRDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3 0 0x2a2c 24 0 2 RDPCS_PHY_DP_TX0_RESET_RESERVED 0 0 RDPCS_PHY_DP_TX0_DISABLE_RESERVED 1 1 RDPCS_PHY_DP_TX0_CLK_RDY_RESERVED 2 2 RDPCS_PHY_DP_TX0_DATA_EN_RESERVED 3 3 RDPCS_PHY_DP_TX0_REQ_RESERVED 4 4 RDPCS_PHY_DP_TX0_ACK_RESERVED 5 5 RDPCS_PHY_DP_TX1_RESET_RESERVED 8 8 RDPCS_PHY_DP_TX1_DISABLE_RESERVED 9 9 RDPCS_PHY_DP_TX1_CLK_RDY_RESERVED 10 10 RDPCS_PHY_DP_TX1_DATA_EN_RESERVED 11 11 RDPCS_PHY_DP_TX1_REQ_RESERVED 12 12 RDPCS_PHY_DP_TX1_ACK_RESERVED 13 13 RDPCS_PHY_DP_TX2_RESET_RESERVED 16 16 RDPCS_PHY_DP_TX2_DISABLE_RESERVED 17 17 RDPCS_PHY_DP_TX2_CLK_RDY_RESERVED 18 18 RDPCS_PHY_DP_TX2_DATA_EN_RESERVED 19 19 RDPCS_PHY_DP_TX2_REQ_RESERVED 20 20 RDPCS_PHY_DP_TX2_ACK_RESERVED 21 21 RDPCS_PHY_DP_TX3_RESET_RESERVED 24 24 RDPCS_PHY_DP_TX3_DISABLE_RESERVED 25 25 RDPCS_PHY_DP_TX3_CLK_RDY_RESERVED 26 26 RDPCS_PHY_DP_TX3_DATA_EN_RESERVED 27 27 RDPCS_PHY_DP_TX3_REQ_RESERVED 28 28 RDPCS_PHY_DP_TX3_ACK_RESERVED 29 29 mmRDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL6 0 0x2a2d 13 0 2 RDPCS_PHY_DP_TX0_PSTATE_RESERVED 0 1 RDPCS_PHY_DP_TX0_MPLL_EN_RESERVED 2 2 RDPCS_PHY_DP_TX1_PSTATE_RESERVED 4 5 RDPCS_PHY_DP_TX1_MPLL_EN_RESERVED 6 6 RDPCS_PHY_DP_TX2_PSTATE_RESERVED 8 9 RDPCS_PHY_DP_TX2_MPLL_EN_RESERVED 10 10 RDPCS_PHY_DP_TX3_PSTATE_RESERVED 12 13 RDPCS_PHY_DP_TX3_MPLL_EN_RESERVED 14 14 RDPCS_PHY_DPALT_DP4_RESERVED 16 16 RDPCS_PHY_DPALT_DISABLE_RESERVED 17 17 RDPCS_PHY_DPALT_DISABLE_ACK_RESERVED 18 18 RDPCS_PHY_DP_REF_CLK_EN_RESERVED 19 19 RDPCS_PHY_DP_REF_CLK_REQ_RESERVED 20 20 mmRDPCSTX1_RDPCSTX_DPALT_CONTROL_REG 0 0x2a2e 3 0 2 RDPCS_ALLOW_DRIVER_ACCESS 0 0 RDPCS_DRIVER_ACCESS_BLOCKED 4 4 RDPCS_DPALT_CONTROL_SPARE 8 15 mmDPCSSYS_CR1_DPCSSYS_CR_ADDR 0 0x2a0c 1 0 2 RDPCS_TX_CR_ADDR 0 15 mmDPCSSYS_CR1_DPCSSYS_CR_DATA 0 0x2a0d 1 0 2 RDPCS_TX_CR_DATA 0 15 mmDPCSTX2_DPCSTX_TX_CLOCK_CNTL 0 0x2ad8 4 0 2 DPCS_SYMCLK_GATE_DIS 0 0 DPCS_SYMCLK_EN 1 1 DPCS_SYMCLK_CLOCK_ON 2 2 DPCS_SYMCLK_DIV2_CLOCK_ON 3 3 mmDPCSTX2_DPCSTX_TX_CNTL 0 0x2ad9 8 0 2 DPCS_TX_PLL_UPDATE_REQ 12 12 DPCS_TX_PLL_UPDATE_PENDING 13 13 DPCS_TX_DATA_SWAP 14 14 DPCS_TX_DATA_ORDER_INVERT 15 15 DPCS_TX_FIFO_EN 16 16 DPCS_TX_FIFO_START 17 17 DPCS_TX_FIFO_RD_START_DELAY 20 23 DPCS_TX_SOFT_RESET 31 31 mmDPCSTX2_DPCSTX_CBUS_CNTL 0 0x2ada 2 0 2 DPCS_CBUS_WR_CMD_DELAY 0 7 DPCS_CBUS_SOFT_RESET 31 31 mmDPCSTX2_DPCSTX_INTERRUPT_CNTL 0 0x2adb 10 0 2 DPCS_REG_FIFO_OVERFLOW 0 0 DPCS_REG_ERROR_CLR 1 1 DPCS_REG_FIFO_ERROR_MASK 4 4 DPCS_TX0_FIFO_ERROR 8 8 DPCS_TX1_FIFO_ERROR 9 9 DPCS_TX2_FIFO_ERROR 10 10 DPCS_TX3_FIFO_ERROR 11 11 DPCS_TX_ERROR_CLR 12 12 DPCS_TX_FIFO_ERROR_MASK 16 16 DPCS_INTERRUPT_MASK 20 20 mmDPCSTX2_DPCSTX_PLL_UPDATE_ADDR 0 0x2adc 1 0 2 DPCS_PLL_UPDATE_ADDR 0 17 mmDPCSTX2_DPCSTX_PLL_UPDATE_DATA 0 0x2add 1 0 2 DPCS_PLL_UPDATE_DATA 0 31 mmDPCSTX2_DPCSTX_DEBUG_CONFIG 0 0x2ade 6 0 2 DPCS_DBG_EN 0 0 DPCS_DBG_CFGCLK_SEL 1 3 DPCS_DBG_TX_SYMCLK_SEL 4 6 DPCS_DBG_TX_SYMCLK_DIV2_SEL 8 10 DPCS_DBG_CBUS_DIS 14 14 DPCS_TEST_DEBUG_WRITE_EN 16 16 mmRDPCSTX2_RDPCSTX_CNTL 0 0x2ae0 13 0 2 RDPCS_CBUS_SOFT_RESET 0 0 RDPCS_SRAM_SOFT_RESET 4 4 RDPCS_TX_FIFO_LANE0_EN 12 12 RDPCS_TX_FIFO_LANE1_EN 13 13 RDPCS_TX_FIFO_LANE2_EN 14 14 RDPCS_TX_FIFO_LANE3_EN 15 15 RDPCS_TX_FIFO_EN 16 16 RDPCS_TX_FIFO_START 17 17 RDPCS_TX_FIFO_RD_START_DELAY 20 23 RDPCS_CR_REGISTER_BLOCK_EN 24 24 RDPCS_NON_DPALT_REGISTER_BLOCK_EN 25 25 RDPCS_DPALT_BLOCK_STATUS 26 26 RDPCS_TX_SOFT_RESET 31 31 mmRDPCSTX2_RDPCSTX_CLOCK_CNTL 0 0x2ae1 12 0 2 RDPCS_EXT_REFCLK_EN 0 0 RDPCS_SYMCLK_DIV2_TX0_EN 4 4 RDPCS_SYMCLK_DIV2_TX1_EN 5 5 RDPCS_SYMCLK_DIV2_TX2_EN 6 6 RDPCS_SYMCLK_DIV2_TX3_EN 7 7 RDPCS_SYMCLK_DIV2_GATE_DIS 8 8 RDPCS_SYMCLK_DIV2_EN 9 9 RDPCS_SYMCLK_DIV2_CLOCK_ON 10 10 RDPCS_SRAMCLK_GATE_DIS 12 12 RDPCS_SRAMCLK_EN 13 13 RDPCS_SRAMCLK_CLOCK_ON 14 14 RDPCS_SRAMCLK_BYPASS 16 16 mmRDPCSTX2_RDPCSTX_INTERRUPT_CONTROL 0 0x2ae2 15 0 2 RDPCS_REG_FIFO_OVERFLOW 0 0 RDPCS_DPALT_DISABLE_TOGGLE 1 1 RDPCS_DPALT_4LANE_TOGGLE 2 2 RDPCS_TX0_FIFO_ERROR 4 4 RDPCS_TX1_FIFO_ERROR 5 5 RDPCS_TX2_FIFO_ERROR 6 6 RDPCS_TX3_FIFO_ERROR 7 7 RDPCS_REG_ERROR_CLR 8 8 RDPCS_DPALT_DISABLE_TOGGLE_CLR 9 9 RDPCS_DPALT_4LANE_TOGGLE_CLR 10 10 RDPCS_TX_ERROR_CLR 12 12 RDPCS_REG_FIFO_ERROR_MASK 16 16 RDPCS_DPALT_DISABLE_TOGGLE_MASK 17 17 RDPCS_DPALT_4LANE_TOGGLE_MASK 18 18 RDPCS_TX_FIFO_ERROR_MASK 20 20 mmRDPCSTX2_RDPCSTX_PLL_UPDATE_DATA 0 0x2ae3 1 0 2 RDPCS_PLL_UPDATE_DATA 0 0 mmRDPCSTX2_RDPCS_TX_CR_ADDR 0 0x2ae4 1 0 2 RDPCS_TX_CR_ADDR 0 15 mmRDPCSTX2_RDPCS_TX_CR_DATA 0 0x2ae5 1 0 2 RDPCS_TX_CR_DATA 0 15 mmRDPCSTX2_RDPCS_TX_SRAM_CNTL 0 0x2ae6 3 0 2 RDPCS_MEM_PWR_DIS 20 20 RDPCS_MEM_PWR_FORCE 24 25 RDPCS_MEM_PWR_PWR_STATE 28 29 mmRDPCSTX2_RDPCSTX_MEM_POWER_CTRL 0 0x2ae7 7 0 2 RDPCS_FUSE_RM_FUSES 0 11 RDPCS_FUSE_CUSTOM_RM_FUSES 12 25 RDPCS_MEM_POWER_CTRL_PDP_BC1 26 26 RDPCS_MEM_POWER_CTRL_PDP_BC2 27 27 RDPCS_MEM_POWER_CTRL_HD_BC1 28 28 RDPCS_MEM_POWER_CTRL_HD_BC2 29 29 RDPCS_LIVMIN_DIS_SRAM 30 30 mmRDPCSTX2_RDPCSTX_MEM_POWER_CTRL2 0 0x2ae8 2 0 2 RDPCS_MEM_POWER_CTRL_POFF 0 1 RDPCS_MEM_POWER_CTRL_FISO 2 2 mmRDPCSTX2_RDPCSTX_SCRATCH 0 0x2ae9 1 0 2 RDPCSTX_SCRATCH 0 31 mmRDPCSTX2_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG 0 0x2aec 3 0 2 RDPCS_DMCU_DPALT_DIS_BLOCK_REG 0 0 RDPCS_DMCU_DPALT_FORCE_SYMCLK_DIV2_DIS 4 4 RDPCS_DMCU_DPALT_CONTROL_SPARE 8 15 mmRDPCSTX2_RDPCSTX_DEBUG_CONFIG 0 0x2aed 7 0 2 RDPCS_DBG_EN 0 0 RDPCS_DBG_SEL_ASYNC_8BIT 4 6 RDPCS_DBG_SEL_ASYNC_SWAP 7 7 RDPCS_DBG_SEL_TEST_CLK 8 12 RDPCS_DBG_CR_COUNT_EXPIRE 15 15 RDPCS_DBG_CR_COUNT_MAX 16 23 RDPCS_DBG_CR_COUNT 24 31 mmRDPCSTX2_RDPCSTX_PHY_CNTL0 0 0x2af0 17 0 2 RDPCS_PHY_RESET 0 0 RDPCS_PHY_TCA_PHY_RESET 1 1 RDPCS_PHY_TCA_APB_RESET_N 2 2 RDPCS_PHY_TEST_POWERDOWN 3 3 RDPCS_PHY_DTB_OUT 4 5 RDPCS_PHY_HDMIMODE_ENABLE 8 8 RDPCS_PHY_REF_RANGE 9 13 RDPCS_PHY_TX_VBOOST_LVL 14 16 RDPCS_PHY_RTUNE_REQ 17 17 RDPCS_PHY_RTUNE_ACK 18 18 RDPCS_PHY_CR_PARA_SEL 20 20 RDPCS_PHY_CR_MUX_SEL 21 21 RDPCS_PHY_REF_CLKDET_EN 24 24 RDPCS_PHY_REF_CLKDET_RESULT 25 25 RDPCS_SRAM_INIT_DONE 28 28 RDPCS_SRAM_EXT_LD_DONE 29 29 RDPCS_SRAM_BYPASS 31 31 mmRDPCSTX2_RDPCSTX_PHY_CNTL1 0 0x2af1 8 0 2 RDPCS_PHY_PG_MODE_EN 0 0 RDPCS_PHY_PCS_PWR_EN 1 1 RDPCS_PHY_PCS_PWR_STABLE 2 2 RDPCS_PHY_PMA_PWR_EN 3 3 RDPCS_PHY_PMA_PWR_STABLE 4 4 RDPCS_PHY_DP_PG_RESET 5 5 RDPCS_PHY_ANA_PWR_EN 6 6 RDPCS_PHY_ANA_PWR_STABLE 7 7 mmRDPCSTX2_RDPCSTX_PHY_CNTL2 0 0x2af2 9 0 2 RDPCS_PHY_DP4_POR 3 3 RDPCS_PHY_DP_LANE0_RX2TX_PAR_LB_EN 4 4 RDPCS_PHY_DP_LANE1_RX2TX_PAR_LB_EN 5 5 RDPCS_PHY_DP_LANE2_RX2TX_PAR_LB_EN 6 6 RDPCS_PHY_DP_LANE3_RX2TX_PAR_LB_EN 7 7 RDPCS_PHY_DP_LANE0_TX2RX_SER_LB_EN 8 8 RDPCS_PHY_DP_LANE1_TX2RX_SER_LB_EN 9 9 RDPCS_PHY_DP_LANE2_TX2RX_SER_LB_EN 10 10 RDPCS_PHY_DP_LANE3_TX2RX_SER_LB_EN 11 11 mmRDPCSTX2_RDPCSTX_PHY_CNTL3 0 0x2af3 24 0 2 RDPCS_PHY_DP_TX0_RESET 0 0 RDPCS_PHY_DP_TX0_DISABLE 1 1 RDPCS_PHY_DP_TX0_CLK_RDY 2 2 RDPCS_PHY_DP_TX0_DATA_EN 3 3 RDPCS_PHY_DP_TX0_REQ 4 4 RDPCS_PHY_DP_TX0_ACK 5 5 RDPCS_PHY_DP_TX1_RESET 8 8 RDPCS_PHY_DP_TX1_DISABLE 9 9 RDPCS_PHY_DP_TX1_CLK_RDY 10 10 RDPCS_PHY_DP_TX1_DATA_EN 11 11 RDPCS_PHY_DP_TX1_REQ 12 12 RDPCS_PHY_DP_TX1_ACK 13 13 RDPCS_PHY_DP_TX2_RESET 16 16 RDPCS_PHY_DP_TX2_DISABLE 17 17 RDPCS_PHY_DP_TX2_CLK_RDY 18 18 RDPCS_PHY_DP_TX2_DATA_EN 19 19 RDPCS_PHY_DP_TX2_REQ 20 20 RDPCS_PHY_DP_TX2_ACK 21 21 RDPCS_PHY_DP_TX3_RESET 24 24 RDPCS_PHY_DP_TX3_DISABLE 25 25 RDPCS_PHY_DP_TX3_CLK_RDY 26 26 RDPCS_PHY_DP_TX3_DATA_EN 27 27 RDPCS_PHY_DP_TX3_REQ 28 28 RDPCS_PHY_DP_TX3_ACK 29 29 mmRDPCSTX2_RDPCSTX_PHY_CNTL4 0 0x2af4 16 0 2 RDPCS_PHY_DP_TX0_TERM_CTRL 0 2 RDPCS_PHY_DP_TX0_INVERT 4 4 RDPCS_PHY_DP_TX0_BYPASS_EQ_CALC 6 6 RDPCS_PHY_DP_TX0_HP_PROT_EN 7 7 RDPCS_PHY_DP_TX1_TERM_CTRL 8 10 RDPCS_PHY_DP_TX1_INVERT 12 12 RDPCS_PHY_DP_TX1_BYPASS_EQ_CALC 14 14 RDPCS_PHY_DP_TX1_HP_PROT_EN 15 15 RDPCS_PHY_DP_TX2_TERM_CTRL 16 18 RDPCS_PHY_DP_TX2_INVERT 20 20 RDPCS_PHY_DP_TX2_BYPASS_EQ_CALC 22 22 RDPCS_PHY_DP_TX2_HP_PROT_EN 23 23 RDPCS_PHY_DP_TX3_TERM_CTRL 24 26 RDPCS_PHY_DP_TX3_INVERT 28 28 RDPCS_PHY_DP_TX3_BYPASS_EQ_CALC 30 30 RDPCS_PHY_DP_TX3_HP_PROT_EN 31 31 mmRDPCSTX2_RDPCSTX_PHY_CNTL5 0 0x2af5 20 0 2 RDPCS_PHY_DP_TX0_LPD 0 0 RDPCS_PHY_DP_TX0_RATE 1 3 RDPCS_PHY_DP_TX0_WIDTH 4 5 RDPCS_PHY_DP_TX0_DETRX_REQ 6 6 RDPCS_PHY_DP_TX0_DETRX_RESULT 7 7 RDPCS_PHY_DP_TX1_LPD 8 8 RDPCS_PHY_DP_TX1_RATE 9 11 RDPCS_PHY_DP_TX1_WIDTH 12 13 RDPCS_PHY_DP_TX1_DETRX_REQ 14 14 RDPCS_PHY_DP_TX1_DETRX_RESULT 15 15 RDPCS_PHY_DP_TX2_LPD 16 16 RDPCS_PHY_DP_TX2_RATE 17 19 RDPCS_PHY_DP_TX2_WIDTH 20 21 RDPCS_PHY_DP_TX2_DETRX_REQ 22 22 RDPCS_PHY_DP_TX2_DETRX_RESULT 23 23 RDPCS_PHY_DP_TX3_LPD 24 24 RDPCS_PHY_DP_TX3_RATE 25 27 RDPCS_PHY_DP_TX3_WIDTH 28 29 RDPCS_PHY_DP_TX3_DETRX_REQ 30 30 RDPCS_PHY_DP_TX3_DETRX_RESULT 31 31 mmRDPCSTX2_RDPCSTX_PHY_CNTL6 0 0x2af6 13 0 2 RDPCS_PHY_DP_TX0_PSTATE 0 1 RDPCS_PHY_DP_TX0_MPLL_EN 2 2 RDPCS_PHY_DP_TX1_PSTATE 4 5 RDPCS_PHY_DP_TX1_MPLL_EN 6 6 RDPCS_PHY_DP_TX2_PSTATE 8 9 RDPCS_PHY_DP_TX2_MPLL_EN 10 10 RDPCS_PHY_DP_TX3_PSTATE 12 13 RDPCS_PHY_DP_TX3_MPLL_EN 14 14 RDPCS_PHY_DPALT_DP4 16 16 RDPCS_PHY_DPALT_DISABLE 17 17 RDPCS_PHY_DPALT_DISABLE_ACK 18 18 RDPCS_PHY_DP_REF_CLK_EN 19 19 RDPCS_PHY_DP_REF_CLK_REQ 20 20 mmRDPCSTX2_RDPCSTX_PHY_CNTL7 0 0x2af7 2 0 2 RDPCS_PHY_DP_MPLLB_FRACN_DEN 0 15 RDPCS_PHY_DP_MPLLB_FRACN_QUOT 16 31 mmRDPCSTX2_RDPCSTX_PHY_CNTL8 0 0x2af8 1 0 2 RDPCS_PHY_DP_MPLLB_SSC_PEAK 0 19 mmRDPCSTX2_RDPCSTX_PHY_CNTL9 0 0x2af9 2 0 2 RDPCS_PHY_DP_MPLLB_SSC_STEPSIZE 0 20 RDPCS_PHY_DP_MPLLB_SSC_UP_SPREAD 24 24 mmRDPCSTX2_RDPCSTX_PHY_CNTL10 0 0x2afa 1 0 2 RDPCS_PHY_DP_MPLLB_FRACN_REM 0 15 mmRDPCSTX2_RDPCSTX_PHY_CNTL11 0 0x2afb 4 0 2 RDPCS_PHY_DP_MPLLB_MULTIPLIER 4 15 RDPCS_PHY_HDMI_MPLLB_HDMI_DIV 16 18 RDPCS_PHY_DP_REF_CLK_MPLLB_DIV 20 22 RDPCS_PHY_HDMI_MPLLB_HDMI_PIXEL_CLK_DIV 24 25 mmRDPCSTX2_RDPCSTX_PHY_CNTL12 0 0x2afc 5 0 2 RDPCS_PHY_DP_MPLLB_DIV5_CLK_EN 0 0 RDPCS_PHY_DP_MPLLB_WORD_DIV2_EN 2 2 RDPCS_PHY_DP_MPLLB_TX_CLK_DIV 4 6 RDPCS_PHY_DP_MPLLB_STATE 7 7 RDPCS_PHY_DP_MPLLB_SSC_EN 8 8 mmRDPCSTX2_RDPCSTX_PHY_CNTL13 0 0x2afd 4 0 2 RDPCS_PHY_DP_MPLLB_DIV_MULTIPLIER 20 27 RDPCS_PHY_DP_MPLLB_DIV_CLK_EN 28 28 RDPCS_PHY_DP_MPLLB_FORCE_EN 29 29 RDPCS_PHY_DP_MPLLB_INIT_CAL_DISABLE 30 30 mmRDPCSTX2_RDPCSTX_PHY_CNTL14 0 0x2afe 3 0 2 RDPCS_PHY_DP_MPLLB_CAL_FORCE 0 0 RDPCS_PHY_DP_MPLLB_FRACN_EN 24 24 RDPCS_PHY_DP_MPLLB_PMIX_EN 28 28 mmRDPCSTX2_RDPCSTX_PHY_FUSE0 0 0x2aff 5 0 2 RDPCS_PHY_DP_TX0_EQ_MAIN 0 5 RDPCS_PHY_DP_TX0_EQ_PRE 6 11 RDPCS_PHY_DP_TX0_EQ_POST 12 17 RDPCS_PHY_DP_MPLLB_V2I 18 19 RDPCS_PHY_DP_MPLLB_FREQ_VCO 20 21 mmRDPCSTX2_RDPCSTX_PHY_FUSE1 0 0x2b00 5 0 2 RDPCS_PHY_DP_TX1_EQ_MAIN 0 5 RDPCS_PHY_DP_TX1_EQ_PRE 6 11 RDPCS_PHY_DP_TX1_EQ_POST 12 17 RDPCS_PHY_DP_MPLLB_CP_INT 18 24 RDPCS_PHY_DP_MPLLB_CP_PROP 25 31 mmRDPCSTX2_RDPCSTX_PHY_FUSE2 0 0x2b01 3 0 2 RDPCS_PHY_DP_TX2_EQ_MAIN 0 5 RDPCS_PHY_DP_TX2_EQ_PRE 6 11 RDPCS_PHY_DP_TX2_EQ_POST 12 17 mmRDPCSTX2_RDPCSTX_PHY_FUSE3 0 0x2b02 5 0 2 RDPCS_PHY_DP_TX3_EQ_MAIN 0 5 RDPCS_PHY_DP_TX3_EQ_PRE 6 11 RDPCS_PHY_DP_TX3_EQ_POST 12 17 RDPCS_PHY_DCO_FINETUNE 18 23 RDPCS_PHY_DCO_RANGE 24 25 mmRDPCSTX2_RDPCSTX_PHY_RX_LD_VAL 0 0x2b03 2 0 2 RDPCS_PHY_RX_REF_LD_VAL 0 6 RDPCS_PHY_RX_VCO_LD_VAL 8 20 mmRDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL3 0 0x2b04 24 0 2 RDPCS_PHY_DP_TX0_RESET_RESERVED 0 0 RDPCS_PHY_DP_TX0_DISABLE_RESERVED 1 1 RDPCS_PHY_DP_TX0_CLK_RDY_RESERVED 2 2 RDPCS_PHY_DP_TX0_DATA_EN_RESERVED 3 3 RDPCS_PHY_DP_TX0_REQ_RESERVED 4 4 RDPCS_PHY_DP_TX0_ACK_RESERVED 5 5 RDPCS_PHY_DP_TX1_RESET_RESERVED 8 8 RDPCS_PHY_DP_TX1_DISABLE_RESERVED 9 9 RDPCS_PHY_DP_TX1_CLK_RDY_RESERVED 10 10 RDPCS_PHY_DP_TX1_DATA_EN_RESERVED 11 11 RDPCS_PHY_DP_TX1_REQ_RESERVED 12 12 RDPCS_PHY_DP_TX1_ACK_RESERVED 13 13 RDPCS_PHY_DP_TX2_RESET_RESERVED 16 16 RDPCS_PHY_DP_TX2_DISABLE_RESERVED 17 17 RDPCS_PHY_DP_TX2_CLK_RDY_RESERVED 18 18 RDPCS_PHY_DP_TX2_DATA_EN_RESERVED 19 19 RDPCS_PHY_DP_TX2_REQ_RESERVED 20 20 RDPCS_PHY_DP_TX2_ACK_RESERVED 21 21 RDPCS_PHY_DP_TX3_RESET_RESERVED 24 24 RDPCS_PHY_DP_TX3_DISABLE_RESERVED 25 25 RDPCS_PHY_DP_TX3_CLK_RDY_RESERVED 26 26 RDPCS_PHY_DP_TX3_DATA_EN_RESERVED 27 27 RDPCS_PHY_DP_TX3_REQ_RESERVED 28 28 RDPCS_PHY_DP_TX3_ACK_RESERVED 29 29 mmRDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL6 0 0x2b05 13 0 2 RDPCS_PHY_DP_TX0_PSTATE_RESERVED 0 1 RDPCS_PHY_DP_TX0_MPLL_EN_RESERVED 2 2 RDPCS_PHY_DP_TX1_PSTATE_RESERVED 4 5 RDPCS_PHY_DP_TX1_MPLL_EN_RESERVED 6 6 RDPCS_PHY_DP_TX2_PSTATE_RESERVED 8 9 RDPCS_PHY_DP_TX2_MPLL_EN_RESERVED 10 10 RDPCS_PHY_DP_TX3_PSTATE_RESERVED 12 13 RDPCS_PHY_DP_TX3_MPLL_EN_RESERVED 14 14 RDPCS_PHY_DPALT_DP4_RESERVED 16 16 RDPCS_PHY_DPALT_DISABLE_RESERVED 17 17 RDPCS_PHY_DPALT_DISABLE_ACK_RESERVED 18 18 RDPCS_PHY_DP_REF_CLK_EN_RESERVED 19 19 RDPCS_PHY_DP_REF_CLK_REQ_RESERVED 20 20 mmRDPCSTX2_RDPCSTX_DPALT_CONTROL_REG 0 0x2b06 3 0 2 RDPCS_ALLOW_DRIVER_ACCESS 0 0 RDPCS_DRIVER_ACCESS_BLOCKED 4 4 RDPCS_DPALT_CONTROL_SPARE 8 15 mmDPCSSYS_CR2_DPCSSYS_CR_ADDR 0 0x2ae4 1 0 2 RDPCS_TX_CR_ADDR 0 15 mmDPCSSYS_CR2_DPCSSYS_CR_DATA 0 0x2ae5 1 0 2 RDPCS_TX_CR_DATA 0 15 mmDPCSTX3_DPCSTX_TX_CLOCK_CNTL 0 0x2bb0 4 0 2 DPCS_SYMCLK_GATE_DIS 0 0 DPCS_SYMCLK_EN 1 1 DPCS_SYMCLK_CLOCK_ON 2 2 DPCS_SYMCLK_DIV2_CLOCK_ON 3 3 mmDPCSTX3_DPCSTX_TX_CNTL 0 0x2bb1 8 0 2 DPCS_TX_PLL_UPDATE_REQ 12 12 DPCS_TX_PLL_UPDATE_PENDING 13 13 DPCS_TX_DATA_SWAP 14 14 DPCS_TX_DATA_ORDER_INVERT 15 15 DPCS_TX_FIFO_EN 16 16 DPCS_TX_FIFO_START 17 17 DPCS_TX_FIFO_RD_START_DELAY 20 23 DPCS_TX_SOFT_RESET 31 31 mmDPCSTX3_DPCSTX_CBUS_CNTL 0 0x2bb2 2 0 2 DPCS_CBUS_WR_CMD_DELAY 0 7 DPCS_CBUS_SOFT_RESET 31 31 mmDPCSTX3_DPCSTX_INTERRUPT_CNTL 0 0x2bb3 10 0 2 DPCS_REG_FIFO_OVERFLOW 0 0 DPCS_REG_ERROR_CLR 1 1 DPCS_REG_FIFO_ERROR_MASK 4 4 DPCS_TX0_FIFO_ERROR 8 8 DPCS_TX1_FIFO_ERROR 9 9 DPCS_TX2_FIFO_ERROR 10 10 DPCS_TX3_FIFO_ERROR 11 11 DPCS_TX_ERROR_CLR 12 12 DPCS_TX_FIFO_ERROR_MASK 16 16 DPCS_INTERRUPT_MASK 20 20 mmDPCSTX3_DPCSTX_PLL_UPDATE_ADDR 0 0x2bb4 1 0 2 DPCS_PLL_UPDATE_ADDR 0 17 mmDPCSTX3_DPCSTX_PLL_UPDATE_DATA 0 0x2bb5 1 0 2 DPCS_PLL_UPDATE_DATA 0 31 mmDPCSTX3_DPCSTX_DEBUG_CONFIG 0 0x2bb6 6 0 2 DPCS_DBG_EN 0 0 DPCS_DBG_CFGCLK_SEL 1 3 DPCS_DBG_TX_SYMCLK_SEL 4 6 DPCS_DBG_TX_SYMCLK_DIV2_SEL 8 10 DPCS_DBG_CBUS_DIS 14 14 DPCS_TEST_DEBUG_WRITE_EN 16 16 mmRDPCSTX3_RDPCSTX_CNTL 0 0x2bb8 13 0 2 RDPCS_CBUS_SOFT_RESET 0 0 RDPCS_SRAM_SOFT_RESET 4 4 RDPCS_TX_FIFO_LANE0_EN 12 12 RDPCS_TX_FIFO_LANE1_EN 13 13 RDPCS_TX_FIFO_LANE2_EN 14 14 RDPCS_TX_FIFO_LANE3_EN 15 15 RDPCS_TX_FIFO_EN 16 16 RDPCS_TX_FIFO_START 17 17 RDPCS_TX_FIFO_RD_START_DELAY 20 23 RDPCS_CR_REGISTER_BLOCK_EN 24 24 RDPCS_NON_DPALT_REGISTER_BLOCK_EN 25 25 RDPCS_DPALT_BLOCK_STATUS 26 26 RDPCS_TX_SOFT_RESET 31 31 mmRDPCSTX3_RDPCSTX_CLOCK_CNTL 0 0x2bb9 12 0 2 RDPCS_EXT_REFCLK_EN 0 0 RDPCS_SYMCLK_DIV2_TX0_EN 4 4 RDPCS_SYMCLK_DIV2_TX1_EN 5 5 RDPCS_SYMCLK_DIV2_TX2_EN 6 6 RDPCS_SYMCLK_DIV2_TX3_EN 7 7 RDPCS_SYMCLK_DIV2_GATE_DIS 8 8 RDPCS_SYMCLK_DIV2_EN 9 9 RDPCS_SYMCLK_DIV2_CLOCK_ON 10 10 RDPCS_SRAMCLK_GATE_DIS 12 12 RDPCS_SRAMCLK_EN 13 13 RDPCS_SRAMCLK_CLOCK_ON 14 14 RDPCS_SRAMCLK_BYPASS 16 16 mmRDPCSTX3_RDPCSTX_INTERRUPT_CONTROL 0 0x2bba 15 0 2 RDPCS_REG_FIFO_OVERFLOW 0 0 RDPCS_DPALT_DISABLE_TOGGLE 1 1 RDPCS_DPALT_4LANE_TOGGLE 2 2 RDPCS_TX0_FIFO_ERROR 4 4 RDPCS_TX1_FIFO_ERROR 5 5 RDPCS_TX2_FIFO_ERROR 6 6 RDPCS_TX3_FIFO_ERROR 7 7 RDPCS_REG_ERROR_CLR 8 8 RDPCS_DPALT_DISABLE_TOGGLE_CLR 9 9 RDPCS_DPALT_4LANE_TOGGLE_CLR 10 10 RDPCS_TX_ERROR_CLR 12 12 RDPCS_REG_FIFO_ERROR_MASK 16 16 RDPCS_DPALT_DISABLE_TOGGLE_MASK 17 17 RDPCS_DPALT_4LANE_TOGGLE_MASK 18 18 RDPCS_TX_FIFO_ERROR_MASK 20 20 mmRDPCSTX3_RDPCSTX_PLL_UPDATE_DATA 0 0x2bbb 1 0 2 RDPCS_PLL_UPDATE_DATA 0 0 mmRDPCSTX3_RDPCS_TX_CR_ADDR 0 0x2bbc 1 0 2 RDPCS_TX_CR_ADDR 0 15 mmRDPCSTX3_RDPCS_TX_CR_DATA 0 0x2bbd 1 0 2 RDPCS_TX_CR_DATA 0 15 mmRDPCSTX3_RDPCS_TX_SRAM_CNTL 0 0x2bbe 3 0 2 RDPCS_MEM_PWR_DIS 20 20 RDPCS_MEM_PWR_FORCE 24 25 RDPCS_MEM_PWR_PWR_STATE 28 29 mmRDPCSTX3_RDPCSTX_MEM_POWER_CTRL 0 0x2bbf 7 0 2 RDPCS_FUSE_RM_FUSES 0 11 RDPCS_FUSE_CUSTOM_RM_FUSES 12 25 RDPCS_MEM_POWER_CTRL_PDP_BC1 26 26 RDPCS_MEM_POWER_CTRL_PDP_BC2 27 27 RDPCS_MEM_POWER_CTRL_HD_BC1 28 28 RDPCS_MEM_POWER_CTRL_HD_BC2 29 29 RDPCS_LIVMIN_DIS_SRAM 30 30 mmRDPCSTX3_RDPCSTX_MEM_POWER_CTRL2 0 0x2bc0 2 0 2 RDPCS_MEM_POWER_CTRL_POFF 0 1 RDPCS_MEM_POWER_CTRL_FISO 2 2 mmRDPCSTX3_RDPCSTX_SCRATCH 0 0x2bc1 1 0 2 RDPCSTX_SCRATCH 0 31 mmRDPCSTX3_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG 0 0x2bc4 3 0 2 RDPCS_DMCU_DPALT_DIS_BLOCK_REG 0 0 RDPCS_DMCU_DPALT_FORCE_SYMCLK_DIV2_DIS 4 4 RDPCS_DMCU_DPALT_CONTROL_SPARE 8 15 mmRDPCSTX3_RDPCSTX_DEBUG_CONFIG 0 0x2bc5 7 0 2 RDPCS_DBG_EN 0 0 RDPCS_DBG_SEL_ASYNC_8BIT 4 6 RDPCS_DBG_SEL_ASYNC_SWAP 7 7 RDPCS_DBG_SEL_TEST_CLK 8 12 RDPCS_DBG_CR_COUNT_EXPIRE 15 15 RDPCS_DBG_CR_COUNT_MAX 16 23 RDPCS_DBG_CR_COUNT 24 31 mmRDPCSTX3_RDPCSTX_PHY_CNTL0 0 0x2bc8 17 0 2 RDPCS_PHY_RESET 0 0 RDPCS_PHY_TCA_PHY_RESET 1 1 RDPCS_PHY_TCA_APB_RESET_N 2 2 RDPCS_PHY_TEST_POWERDOWN 3 3 RDPCS_PHY_DTB_OUT 4 5 RDPCS_PHY_HDMIMODE_ENABLE 8 8 RDPCS_PHY_REF_RANGE 9 13 RDPCS_PHY_TX_VBOOST_LVL 14 16 RDPCS_PHY_RTUNE_REQ 17 17 RDPCS_PHY_RTUNE_ACK 18 18 RDPCS_PHY_CR_PARA_SEL 20 20 RDPCS_PHY_CR_MUX_SEL 21 21 RDPCS_PHY_REF_CLKDET_EN 24 24 RDPCS_PHY_REF_CLKDET_RESULT 25 25 RDPCS_SRAM_INIT_DONE 28 28 RDPCS_SRAM_EXT_LD_DONE 29 29 RDPCS_SRAM_BYPASS 31 31 mmRDPCSTX3_RDPCSTX_PHY_CNTL1 0 0x2bc9 8 0 2 RDPCS_PHY_PG_MODE_EN 0 0 RDPCS_PHY_PCS_PWR_EN 1 1 RDPCS_PHY_PCS_PWR_STABLE 2 2 RDPCS_PHY_PMA_PWR_EN 3 3 RDPCS_PHY_PMA_PWR_STABLE 4 4 RDPCS_PHY_DP_PG_RESET 5 5 RDPCS_PHY_ANA_PWR_EN 6 6 RDPCS_PHY_ANA_PWR_STABLE 7 7 mmRDPCSTX3_RDPCSTX_PHY_CNTL2 0 0x2bca 9 0 2 RDPCS_PHY_DP4_POR 3 3 RDPCS_PHY_DP_LANE0_RX2TX_PAR_LB_EN 4 4 RDPCS_PHY_DP_LANE1_RX2TX_PAR_LB_EN 5 5 RDPCS_PHY_DP_LANE2_RX2TX_PAR_LB_EN 6 6 RDPCS_PHY_DP_LANE3_RX2TX_PAR_LB_EN 7 7 RDPCS_PHY_DP_LANE0_TX2RX_SER_LB_EN 8 8 RDPCS_PHY_DP_LANE1_TX2RX_SER_LB_EN 9 9 RDPCS_PHY_DP_LANE2_TX2RX_SER_LB_EN 10 10 RDPCS_PHY_DP_LANE3_TX2RX_SER_LB_EN 11 11 mmRDPCSTX3_RDPCSTX_PHY_CNTL3 0 0x2bcb 24 0 2 RDPCS_PHY_DP_TX0_RESET 0 0 RDPCS_PHY_DP_TX0_DISABLE 1 1 RDPCS_PHY_DP_TX0_CLK_RDY 2 2 RDPCS_PHY_DP_TX0_DATA_EN 3 3 RDPCS_PHY_DP_TX0_REQ 4 4 RDPCS_PHY_DP_TX0_ACK 5 5 RDPCS_PHY_DP_TX1_RESET 8 8 RDPCS_PHY_DP_TX1_DISABLE 9 9 RDPCS_PHY_DP_TX1_CLK_RDY 10 10 RDPCS_PHY_DP_TX1_DATA_EN 11 11 RDPCS_PHY_DP_TX1_REQ 12 12 RDPCS_PHY_DP_TX1_ACK 13 13 RDPCS_PHY_DP_TX2_RESET 16 16 RDPCS_PHY_DP_TX2_DISABLE 17 17 RDPCS_PHY_DP_TX2_CLK_RDY 18 18 RDPCS_PHY_DP_TX2_DATA_EN 19 19 RDPCS_PHY_DP_TX2_REQ 20 20 RDPCS_PHY_DP_TX2_ACK 21 21 RDPCS_PHY_DP_TX3_RESET 24 24 RDPCS_PHY_DP_TX3_DISABLE 25 25 RDPCS_PHY_DP_TX3_CLK_RDY 26 26 RDPCS_PHY_DP_TX3_DATA_EN 27 27 RDPCS_PHY_DP_TX3_REQ 28 28 RDPCS_PHY_DP_TX3_ACK 29 29 mmRDPCSTX3_RDPCSTX_PHY_CNTL4 0 0x2bcc 16 0 2 RDPCS_PHY_DP_TX0_TERM_CTRL 0 2 RDPCS_PHY_DP_TX0_INVERT 4 4 RDPCS_PHY_DP_TX0_BYPASS_EQ_CALC 6 6 RDPCS_PHY_DP_TX0_HP_PROT_EN 7 7 RDPCS_PHY_DP_TX1_TERM_CTRL 8 10 RDPCS_PHY_DP_TX1_INVERT 12 12 RDPCS_PHY_DP_TX1_BYPASS_EQ_CALC 14 14 RDPCS_PHY_DP_TX1_HP_PROT_EN 15 15 RDPCS_PHY_DP_TX2_TERM_CTRL 16 18 RDPCS_PHY_DP_TX2_INVERT 20 20 RDPCS_PHY_DP_TX2_BYPASS_EQ_CALC 22 22 RDPCS_PHY_DP_TX2_HP_PROT_EN 23 23 RDPCS_PHY_DP_TX3_TERM_CTRL 24 26 RDPCS_PHY_DP_TX3_INVERT 28 28 RDPCS_PHY_DP_TX3_BYPASS_EQ_CALC 30 30 RDPCS_PHY_DP_TX3_HP_PROT_EN 31 31 mmRDPCSTX3_RDPCSTX_PHY_CNTL5 0 0x2bcd 20 0 2 RDPCS_PHY_DP_TX0_LPD 0 0 RDPCS_PHY_DP_TX0_RATE 1 3 RDPCS_PHY_DP_TX0_WIDTH 4 5 RDPCS_PHY_DP_TX0_DETRX_REQ 6 6 RDPCS_PHY_DP_TX0_DETRX_RESULT 7 7 RDPCS_PHY_DP_TX1_LPD 8 8 RDPCS_PHY_DP_TX1_RATE 9 11 RDPCS_PHY_DP_TX1_WIDTH 12 13 RDPCS_PHY_DP_TX1_DETRX_REQ 14 14 RDPCS_PHY_DP_TX1_DETRX_RESULT 15 15 RDPCS_PHY_DP_TX2_LPD 16 16 RDPCS_PHY_DP_TX2_RATE 17 19 RDPCS_PHY_DP_TX2_WIDTH 20 21 RDPCS_PHY_DP_TX2_DETRX_REQ 22 22 RDPCS_PHY_DP_TX2_DETRX_RESULT 23 23 RDPCS_PHY_DP_TX3_LPD 24 24 RDPCS_PHY_DP_TX3_RATE 25 27 RDPCS_PHY_DP_TX3_WIDTH 28 29 RDPCS_PHY_DP_TX3_DETRX_REQ 30 30 RDPCS_PHY_DP_TX3_DETRX_RESULT 31 31 mmRDPCSTX3_RDPCSTX_PHY_CNTL6 0 0x2bce 13 0 2 RDPCS_PHY_DP_TX0_PSTATE 0 1 RDPCS_PHY_DP_TX0_MPLL_EN 2 2 RDPCS_PHY_DP_TX1_PSTATE 4 5 RDPCS_PHY_DP_TX1_MPLL_EN 6 6 RDPCS_PHY_DP_TX2_PSTATE 8 9 RDPCS_PHY_DP_TX2_MPLL_EN 10 10 RDPCS_PHY_DP_TX3_PSTATE 12 13 RDPCS_PHY_DP_TX3_MPLL_EN 14 14 RDPCS_PHY_DPALT_DP4 16 16 RDPCS_PHY_DPALT_DISABLE 17 17 RDPCS_PHY_DPALT_DISABLE_ACK 18 18 RDPCS_PHY_DP_REF_CLK_EN 19 19 RDPCS_PHY_DP_REF_CLK_REQ 20 20 mmRDPCSTX3_RDPCSTX_PHY_CNTL7 0 0x2bcf 2 0 2 RDPCS_PHY_DP_MPLLB_FRACN_DEN 0 15 RDPCS_PHY_DP_MPLLB_FRACN_QUOT 16 31 mmRDPCSTX3_RDPCSTX_PHY_CNTL8 0 0x2bd0 1 0 2 RDPCS_PHY_DP_MPLLB_SSC_PEAK 0 19 mmRDPCSTX3_RDPCSTX_PHY_CNTL9 0 0x2bd1 2 0 2 RDPCS_PHY_DP_MPLLB_SSC_STEPSIZE 0 20 RDPCS_PHY_DP_MPLLB_SSC_UP_SPREAD 24 24 mmRDPCSTX3_RDPCSTX_PHY_CNTL10 0 0x2bd2 1 0 2 RDPCS_PHY_DP_MPLLB_FRACN_REM 0 15 mmRDPCSTX3_RDPCSTX_PHY_CNTL11 0 0x2bd3 4 0 2 RDPCS_PHY_DP_MPLLB_MULTIPLIER 4 15 RDPCS_PHY_HDMI_MPLLB_HDMI_DIV 16 18 RDPCS_PHY_DP_REF_CLK_MPLLB_DIV 20 22 RDPCS_PHY_HDMI_MPLLB_HDMI_PIXEL_CLK_DIV 24 25 mmRDPCSTX3_RDPCSTX_PHY_CNTL12 0 0x2bd4 5 0 2 RDPCS_PHY_DP_MPLLB_DIV5_CLK_EN 0 0 RDPCS_PHY_DP_MPLLB_WORD_DIV2_EN 2 2 RDPCS_PHY_DP_MPLLB_TX_CLK_DIV 4 6 RDPCS_PHY_DP_MPLLB_STATE 7 7 RDPCS_PHY_DP_MPLLB_SSC_EN 8 8 mmRDPCSTX3_RDPCSTX_PHY_CNTL13 0 0x2bd5 4 0 2 RDPCS_PHY_DP_MPLLB_DIV_MULTIPLIER 20 27 RDPCS_PHY_DP_MPLLB_DIV_CLK_EN 28 28 RDPCS_PHY_DP_MPLLB_FORCE_EN 29 29 RDPCS_PHY_DP_MPLLB_INIT_CAL_DISABLE 30 30 mmRDPCSTX3_RDPCSTX_PHY_CNTL14 0 0x2bd6 3 0 2 RDPCS_PHY_DP_MPLLB_CAL_FORCE 0 0 RDPCS_PHY_DP_MPLLB_FRACN_EN 24 24 RDPCS_PHY_DP_MPLLB_PMIX_EN 28 28 mmRDPCSTX3_RDPCSTX_PHY_FUSE0 0 0x2bd7 5 0 2 RDPCS_PHY_DP_TX0_EQ_MAIN 0 5 RDPCS_PHY_DP_TX0_EQ_PRE 6 11 RDPCS_PHY_DP_TX0_EQ_POST 12 17 RDPCS_PHY_DP_MPLLB_V2I 18 19 RDPCS_PHY_DP_MPLLB_FREQ_VCO 20 21 mmRDPCSTX3_RDPCSTX_PHY_FUSE1 0 0x2bd8 5 0 2 RDPCS_PHY_DP_TX1_EQ_MAIN 0 5 RDPCS_PHY_DP_TX1_EQ_PRE 6 11 RDPCS_PHY_DP_TX1_EQ_POST 12 17 RDPCS_PHY_DP_MPLLB_CP_INT 18 24 RDPCS_PHY_DP_MPLLB_CP_PROP 25 31 mmRDPCSTX3_RDPCSTX_PHY_FUSE2 0 0x2bd9 3 0 2 RDPCS_PHY_DP_TX2_EQ_MAIN 0 5 RDPCS_PHY_DP_TX2_EQ_PRE 6 11 RDPCS_PHY_DP_TX2_EQ_POST 12 17 mmRDPCSTX3_RDPCSTX_PHY_FUSE3 0 0x2bda 5 0 2 RDPCS_PHY_DP_TX3_EQ_MAIN 0 5 RDPCS_PHY_DP_TX3_EQ_PRE 6 11 RDPCS_PHY_DP_TX3_EQ_POST 12 17 RDPCS_PHY_DCO_FINETUNE 18 23 RDPCS_PHY_DCO_RANGE 24 25 mmRDPCSTX3_RDPCSTX_PHY_RX_LD_VAL 0 0x2bdb 2 0 2 RDPCS_PHY_RX_REF_LD_VAL 0 6 RDPCS_PHY_RX_VCO_LD_VAL 8 20 mmRDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL3 0 0x2bdc 24 0 2 RDPCS_PHY_DP_TX0_RESET_RESERVED 0 0 RDPCS_PHY_DP_TX0_DISABLE_RESERVED 1 1 RDPCS_PHY_DP_TX0_CLK_RDY_RESERVED 2 2 RDPCS_PHY_DP_TX0_DATA_EN_RESERVED 3 3 RDPCS_PHY_DP_TX0_REQ_RESERVED 4 4 RDPCS_PHY_DP_TX0_ACK_RESERVED 5 5 RDPCS_PHY_DP_TX1_RESET_RESERVED 8 8 RDPCS_PHY_DP_TX1_DISABLE_RESERVED 9 9 RDPCS_PHY_DP_TX1_CLK_RDY_RESERVED 10 10 RDPCS_PHY_DP_TX1_DATA_EN_RESERVED 11 11 RDPCS_PHY_DP_TX1_REQ_RESERVED 12 12 RDPCS_PHY_DP_TX1_ACK_RESERVED 13 13 RDPCS_PHY_DP_TX2_RESET_RESERVED 16 16 RDPCS_PHY_DP_TX2_DISABLE_RESERVED 17 17 RDPCS_PHY_DP_TX2_CLK_RDY_RESERVED 18 18 RDPCS_PHY_DP_TX2_DATA_EN_RESERVED 19 19 RDPCS_PHY_DP_TX2_REQ_RESERVED 20 20 RDPCS_PHY_DP_TX2_ACK_RESERVED 21 21 RDPCS_PHY_DP_TX3_RESET_RESERVED 24 24 RDPCS_PHY_DP_TX3_DISABLE_RESERVED 25 25 RDPCS_PHY_DP_TX3_CLK_RDY_RESERVED 26 26 RDPCS_PHY_DP_TX3_DATA_EN_RESERVED 27 27 RDPCS_PHY_DP_TX3_REQ_RESERVED 28 28 RDPCS_PHY_DP_TX3_ACK_RESERVED 29 29 mmRDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL6 0 0x2bdd 13 0 2 RDPCS_PHY_DP_TX0_PSTATE_RESERVED 0 1 RDPCS_PHY_DP_TX0_MPLL_EN_RESERVED 2 2 RDPCS_PHY_DP_TX1_PSTATE_RESERVED 4 5 RDPCS_PHY_DP_TX1_MPLL_EN_RESERVED 6 6 RDPCS_PHY_DP_TX2_PSTATE_RESERVED 8 9 RDPCS_PHY_DP_TX2_MPLL_EN_RESERVED 10 10 RDPCS_PHY_DP_TX3_PSTATE_RESERVED 12 13 RDPCS_PHY_DP_TX3_MPLL_EN_RESERVED 14 14 RDPCS_PHY_DPALT_DP4_RESERVED 16 16 RDPCS_PHY_DPALT_DISABLE_RESERVED 17 17 RDPCS_PHY_DPALT_DISABLE_ACK_RESERVED 18 18 RDPCS_PHY_DP_REF_CLK_EN_RESERVED 19 19 RDPCS_PHY_DP_REF_CLK_REQ_RESERVED 20 20 mmRDPCSTX3_RDPCSTX_DPALT_CONTROL_REG 0 0x2bde 3 0 2 RDPCS_ALLOW_DRIVER_ACCESS 0 0 RDPCS_DRIVER_ACCESS_BLOCKED 4 4 RDPCS_DPALT_CONTROL_SPARE 8 15 mmDPCSSYS_CR3_DPCSSYS_CR_ADDR 0 0x2bbc 1 0 2 RDPCS_TX_CR_ADDR 0 15 mmDPCSSYS_CR3_DPCSSYS_CR_DATA 0 0x2bbd 1 0 2 RDPCS_TX_CR_DATA 0 15 mmDPCSRX_PHY_CNTL 0 0x2c76 1 0 2 DPCS_PHY_RESET 0 0 mmDPCSRX_RX_CLOCK_CNTL 0 0x2c78 16 0 2 DPCS_SYMCLK_RX_GATE_DIS 0 0 DPCS_SYMCLK_RX_EN 1 1 DPCS_SYMCLK_RX_SEL 2 3 DPCS_SYMCLK_RX_CLOCK_ON 4 4 DPCS_SYMCLK_RX0_GATE_DIS 16 16 DPCS_SYMCLK_RX0_EN 17 17 DPCS_SYMCLK_RX0_CLOCK_ON 18 18 DPCS_SYMCLK_RX1_GATE_DIS 20 20 DPCS_SYMCLK_RX1_EN 21 21 DPCS_SYMCLK_RX1_CLOCK_ON 22 22 DPCS_SYMCLK_RX2_GATE_DIS 24 24 DPCS_SYMCLK_RX2_EN 25 25 DPCS_SYMCLK_RX2_CLOCK_ON 26 26 DPCS_SYMCLK_RX3_GATE_DIS 28 28 DPCS_SYMCLK_RX3_EN 29 29 DPCS_SYMCLK_RX3_CLOCK_ON 30 30 mmDPCSRX_RX_CNTL 0 0x2c7a 8 0 2 DPCS_RX_LANE0_EN 0 0 DPCS_RX_LANE1_EN 1 1 DPCS_RX_LANE2_EN 2 2 DPCS_RX_LANE3_EN 3 3 DPCS_RX_FIFO_EN 4 4 DPCS_RX_FIFO_START 5 5 DPCS_RX_FIFO_RD_START_DELAY 8 11 DPCS_RX_SOFT_RESET 31 31 mmDPCSRX_CBUS_CNTL 0 0x2c7b 3 0 2 DPCS_CBUS_WR_CMD_DELAY 0 3 DPCS_PHY_MASTER_REQ_DELAY 8 15 DPCS_CBUS_SOFT_RESET 31 31 mmDPCSRX_REG_ERROR_STATUS 0 0x2c7c 3 0 2 DPCS_REG_FIFO_OVERFLOW 0 0 DPCS_REG_ERROR_CLR 1 1 DPCS_REG_FIFO_ERROR_MASK 4 4 mmDPCSRX_RX_ERROR_STATUS 0 0x2c7d 6 0 2 DPCS_RX0_FIFO_ERROR 0 0 DPCS_RX1_FIFO_ERROR 1 1 DPCS_RX2_FIFO_ERROR 2 2 DPCS_RX3_FIFO_ERROR 3 3 DPCS_RX_ERROR_CLR 8 8 DPCS_RX_FIFO_ERROR_MASK 12 12 mmDPCSRX_INDEX_MODE_ADDR 0 0x2c80 1 0 2 DPCS_INDEX_MODE_ADDR 0 17 mmDPCSRX_INDEX_MODE_DATA 0 0x2c81 1 0 2 DPCS_INDEX_MODE_DATA 0 31 mmDPCSRX_DEBUG_CONFIG 0 0x2c82 6 0 2 DPCS_DBG_EN 0 0 DPCS_DBG_CFGCLK_SEL 1 3 DPCS_DBG_RX_SYMCLK_SEL 6 7 DPCS_DBG_BLOCK_SEL 11 13 DPCS_DBG_CBUS_DIS 14 14 DPCS_TEST_DEBUG_WRITE_EN 16 16 mmDPCSTX4_DPCSTX_TX_CLOCK_CNTL 0 0x2c88 4 0 2 DPCS_SYMCLK_GATE_DIS 0 0 DPCS_SYMCLK_EN 1 1 DPCS_SYMCLK_CLOCK_ON 2 2 DPCS_SYMCLK_DIV2_CLOCK_ON 3 3 mmDPCSTX4_DPCSTX_TX_CNTL 0 0x2c89 8 0 2 DPCS_TX_PLL_UPDATE_REQ 12 12 DPCS_TX_PLL_UPDATE_PENDING 13 13 DPCS_TX_DATA_SWAP 14 14 DPCS_TX_DATA_ORDER_INVERT 15 15 DPCS_TX_FIFO_EN 16 16 DPCS_TX_FIFO_START 17 17 DPCS_TX_FIFO_RD_START_DELAY 20 23 DPCS_TX_SOFT_RESET 31 31 mmDPCSTX4_DPCSTX_CBUS_CNTL 0 0x2c8a 2 0 2 DPCS_CBUS_WR_CMD_DELAY 0 7 DPCS_CBUS_SOFT_RESET 31 31 mmDPCSTX4_DPCSTX_INTERRUPT_CNTL 0 0x2c8b 10 0 2 DPCS_REG_FIFO_OVERFLOW 0 0 DPCS_REG_ERROR_CLR 1 1 DPCS_REG_FIFO_ERROR_MASK 4 4 DPCS_TX0_FIFO_ERROR 8 8 DPCS_TX1_FIFO_ERROR 9 9 DPCS_TX2_FIFO_ERROR 10 10 DPCS_TX3_FIFO_ERROR 11 11 DPCS_TX_ERROR_CLR 12 12 DPCS_TX_FIFO_ERROR_MASK 16 16 DPCS_INTERRUPT_MASK 20 20 mmDPCSTX4_DPCSTX_PLL_UPDATE_ADDR 0 0x2c8c 1 0 2 DPCS_PLL_UPDATE_ADDR 0 17 mmDPCSTX4_DPCSTX_PLL_UPDATE_DATA 0 0x2c8d 1 0 2 DPCS_PLL_UPDATE_DATA 0 31 mmDPCSTX4_DPCSTX_DEBUG_CONFIG 0 0x2c8e 6 0 2 DPCS_DBG_EN 0 0 DPCS_DBG_CFGCLK_SEL 1 3 DPCS_DBG_TX_SYMCLK_SEL 4 6 DPCS_DBG_TX_SYMCLK_DIV2_SEL 8 10 DPCS_DBG_CBUS_DIS 14 14 DPCS_TEST_DEBUG_WRITE_EN 16 16 mmRDPCSTX4_RDPCSTX_CNTL 0 0x2c90 13 0 2 RDPCS_CBUS_SOFT_RESET 0 0 RDPCS_SRAM_SOFT_RESET 4 4 RDPCS_TX_FIFO_LANE0_EN 12 12 RDPCS_TX_FIFO_LANE1_EN 13 13 RDPCS_TX_FIFO_LANE2_EN 14 14 RDPCS_TX_FIFO_LANE3_EN 15 15 RDPCS_TX_FIFO_EN 16 16 RDPCS_TX_FIFO_START 17 17 RDPCS_TX_FIFO_RD_START_DELAY 20 23 RDPCS_CR_REGISTER_BLOCK_EN 24 24 RDPCS_NON_DPALT_REGISTER_BLOCK_EN 25 25 RDPCS_DPALT_BLOCK_STATUS 26 26 RDPCS_TX_SOFT_RESET 31 31 mmRDPCSTX4_RDPCSTX_CLOCK_CNTL 0 0x2c91 12 0 2 RDPCS_EXT_REFCLK_EN 0 0 RDPCS_SYMCLK_DIV2_TX0_EN 4 4 RDPCS_SYMCLK_DIV2_TX1_EN 5 5 RDPCS_SYMCLK_DIV2_TX2_EN 6 6 RDPCS_SYMCLK_DIV2_TX3_EN 7 7 RDPCS_SYMCLK_DIV2_GATE_DIS 8 8 RDPCS_SYMCLK_DIV2_EN 9 9 RDPCS_SYMCLK_DIV2_CLOCK_ON 10 10 RDPCS_SRAMCLK_GATE_DIS 12 12 RDPCS_SRAMCLK_EN 13 13 RDPCS_SRAMCLK_CLOCK_ON 14 14 RDPCS_SRAMCLK_BYPASS 16 16 mmRDPCSTX4_RDPCSTX_INTERRUPT_CONTROL 0 0x2c92 15 0 2 RDPCS_REG_FIFO_OVERFLOW 0 0 RDPCS_DPALT_DISABLE_TOGGLE 1 1 RDPCS_DPALT_4LANE_TOGGLE 2 2 RDPCS_TX0_FIFO_ERROR 4 4 RDPCS_TX1_FIFO_ERROR 5 5 RDPCS_TX2_FIFO_ERROR 6 6 RDPCS_TX3_FIFO_ERROR 7 7 RDPCS_REG_ERROR_CLR 8 8 RDPCS_DPALT_DISABLE_TOGGLE_CLR 9 9 RDPCS_DPALT_4LANE_TOGGLE_CLR 10 10 RDPCS_TX_ERROR_CLR 12 12 RDPCS_REG_FIFO_ERROR_MASK 16 16 RDPCS_DPALT_DISABLE_TOGGLE_MASK 17 17 RDPCS_DPALT_4LANE_TOGGLE_MASK 18 18 RDPCS_TX_FIFO_ERROR_MASK 20 20 mmRDPCSTX4_RDPCSTX_PLL_UPDATE_DATA 0 0x2c93 1 0 2 RDPCS_PLL_UPDATE_DATA 0 0 mmRDPCSTX4_RDPCS_TX_CR_ADDR 0 0x2c94 1 0 2 RDPCS_TX_CR_ADDR 0 15 mmRDPCSTX4_RDPCS_TX_CR_DATA 0 0x2c95 1 0 2 RDPCS_TX_CR_DATA 0 15 mmRDPCSTX4_RDPCS_TX_SRAM_CNTL 0 0x2c96 3 0 2 RDPCS_MEM_PWR_DIS 20 20 RDPCS_MEM_PWR_FORCE 24 25 RDPCS_MEM_PWR_PWR_STATE 28 29 mmRDPCSTX4_RDPCSTX_MEM_POWER_CTRL 0 0x2c97 7 0 2 RDPCS_FUSE_RM_FUSES 0 11 RDPCS_FUSE_CUSTOM_RM_FUSES 12 25 RDPCS_MEM_POWER_CTRL_PDP_BC1 26 26 RDPCS_MEM_POWER_CTRL_PDP_BC2 27 27 RDPCS_MEM_POWER_CTRL_HD_BC1 28 28 RDPCS_MEM_POWER_CTRL_HD_BC2 29 29 RDPCS_LIVMIN_DIS_SRAM 30 30 mmRDPCSTX4_RDPCSTX_MEM_POWER_CTRL2 0 0x2c98 2 0 2 RDPCS_MEM_POWER_CTRL_POFF 0 1 RDPCS_MEM_POWER_CTRL_FISO 2 2 mmRDPCSTX4_RDPCSTX_SCRATCH 0 0x2c99 1 0 2 RDPCSTX_SCRATCH 0 31 mmRDPCSTX4_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG 0 0x2c9c 3 0 2 RDPCS_DMCU_DPALT_DIS_BLOCK_REG 0 0 RDPCS_DMCU_DPALT_FORCE_SYMCLK_DIV2_DIS 4 4 RDPCS_DMCU_DPALT_CONTROL_SPARE 8 15 mmRDPCSTX4_RDPCSTX_DEBUG_CONFIG 0 0x2c9d 7 0 2 RDPCS_DBG_EN 0 0 RDPCS_DBG_SEL_ASYNC_8BIT 4 6 RDPCS_DBG_SEL_ASYNC_SWAP 7 7 RDPCS_DBG_SEL_TEST_CLK 8 12 RDPCS_DBG_CR_COUNT_EXPIRE 15 15 RDPCS_DBG_CR_COUNT_MAX 16 23 RDPCS_DBG_CR_COUNT 24 31 mmRDPCSTX4_RDPCSTX_PHY_CNTL0 0 0x2ca0 17 0 2 RDPCS_PHY_RESET 0 0 RDPCS_PHY_TCA_PHY_RESET 1 1 RDPCS_PHY_TCA_APB_RESET_N 2 2 RDPCS_PHY_TEST_POWERDOWN 3 3 RDPCS_PHY_DTB_OUT 4 5 RDPCS_PHY_HDMIMODE_ENABLE 8 8 RDPCS_PHY_REF_RANGE 9 13 RDPCS_PHY_TX_VBOOST_LVL 14 16 RDPCS_PHY_RTUNE_REQ 17 17 RDPCS_PHY_RTUNE_ACK 18 18 RDPCS_PHY_CR_PARA_SEL 20 20 RDPCS_PHY_CR_MUX_SEL 21 21 RDPCS_PHY_REF_CLKDET_EN 24 24 RDPCS_PHY_REF_CLKDET_RESULT 25 25 RDPCS_SRAM_INIT_DONE 28 28 RDPCS_SRAM_EXT_LD_DONE 29 29 RDPCS_SRAM_BYPASS 31 31 mmRDPCSTX4_RDPCSTX_PHY_CNTL1 0 0x2ca1 8 0 2 RDPCS_PHY_PG_MODE_EN 0 0 RDPCS_PHY_PCS_PWR_EN 1 1 RDPCS_PHY_PCS_PWR_STABLE 2 2 RDPCS_PHY_PMA_PWR_EN 3 3 RDPCS_PHY_PMA_PWR_STABLE 4 4 RDPCS_PHY_DP_PG_RESET 5 5 RDPCS_PHY_ANA_PWR_EN 6 6 RDPCS_PHY_ANA_PWR_STABLE 7 7 mmRDPCSTX4_RDPCSTX_PHY_CNTL2 0 0x2ca2 9 0 2 RDPCS_PHY_DP4_POR 3 3 RDPCS_PHY_DP_LANE0_RX2TX_PAR_LB_EN 4 4 RDPCS_PHY_DP_LANE1_RX2TX_PAR_LB_EN 5 5 RDPCS_PHY_DP_LANE2_RX2TX_PAR_LB_EN 6 6 RDPCS_PHY_DP_LANE3_RX2TX_PAR_LB_EN 7 7 RDPCS_PHY_DP_LANE0_TX2RX_SER_LB_EN 8 8 RDPCS_PHY_DP_LANE1_TX2RX_SER_LB_EN 9 9 RDPCS_PHY_DP_LANE2_TX2RX_SER_LB_EN 10 10 RDPCS_PHY_DP_LANE3_TX2RX_SER_LB_EN 11 11 mmRDPCSTX4_RDPCSTX_PHY_CNTL3 0 0x2ca3 24 0 2 RDPCS_PHY_DP_TX0_RESET 0 0 RDPCS_PHY_DP_TX0_DISABLE 1 1 RDPCS_PHY_DP_TX0_CLK_RDY 2 2 RDPCS_PHY_DP_TX0_DATA_EN 3 3 RDPCS_PHY_DP_TX0_REQ 4 4 RDPCS_PHY_DP_TX0_ACK 5 5 RDPCS_PHY_DP_TX1_RESET 8 8 RDPCS_PHY_DP_TX1_DISABLE 9 9 RDPCS_PHY_DP_TX1_CLK_RDY 10 10 RDPCS_PHY_DP_TX1_DATA_EN 11 11 RDPCS_PHY_DP_TX1_REQ 12 12 RDPCS_PHY_DP_TX1_ACK 13 13 RDPCS_PHY_DP_TX2_RESET 16 16 RDPCS_PHY_DP_TX2_DISABLE 17 17 RDPCS_PHY_DP_TX2_CLK_RDY 18 18 RDPCS_PHY_DP_TX2_DATA_EN 19 19 RDPCS_PHY_DP_TX2_REQ 20 20 RDPCS_PHY_DP_TX2_ACK 21 21 RDPCS_PHY_DP_TX3_RESET 24 24 RDPCS_PHY_DP_TX3_DISABLE 25 25 RDPCS_PHY_DP_TX3_CLK_RDY 26 26 RDPCS_PHY_DP_TX3_DATA_EN 27 27 RDPCS_PHY_DP_TX3_REQ 28 28 RDPCS_PHY_DP_TX3_ACK 29 29 mmRDPCSTX4_RDPCSTX_PHY_CNTL4 0 0x2ca4 16 0 2 RDPCS_PHY_DP_TX0_TERM_CTRL 0 2 RDPCS_PHY_DP_TX0_INVERT 4 4 RDPCS_PHY_DP_TX0_BYPASS_EQ_CALC 6 6 RDPCS_PHY_DP_TX0_HP_PROT_EN 7 7 RDPCS_PHY_DP_TX1_TERM_CTRL 8 10 RDPCS_PHY_DP_TX1_INVERT 12 12 RDPCS_PHY_DP_TX1_BYPASS_EQ_CALC 14 14 RDPCS_PHY_DP_TX1_HP_PROT_EN 15 15 RDPCS_PHY_DP_TX2_TERM_CTRL 16 18 RDPCS_PHY_DP_TX2_INVERT 20 20 RDPCS_PHY_DP_TX2_BYPASS_EQ_CALC 22 22 RDPCS_PHY_DP_TX2_HP_PROT_EN 23 23 RDPCS_PHY_DP_TX3_TERM_CTRL 24 26 RDPCS_PHY_DP_TX3_INVERT 28 28 RDPCS_PHY_DP_TX3_BYPASS_EQ_CALC 30 30 RDPCS_PHY_DP_TX3_HP_PROT_EN 31 31 mmRDPCSTX4_RDPCSTX_PHY_CNTL5 0 0x2ca5 20 0 2 RDPCS_PHY_DP_TX0_LPD 0 0 RDPCS_PHY_DP_TX0_RATE 1 3 RDPCS_PHY_DP_TX0_WIDTH 4 5 RDPCS_PHY_DP_TX0_DETRX_REQ 6 6 RDPCS_PHY_DP_TX0_DETRX_RESULT 7 7 RDPCS_PHY_DP_TX1_LPD 8 8 RDPCS_PHY_DP_TX1_RATE 9 11 RDPCS_PHY_DP_TX1_WIDTH 12 13 RDPCS_PHY_DP_TX1_DETRX_REQ 14 14 RDPCS_PHY_DP_TX1_DETRX_RESULT 15 15 RDPCS_PHY_DP_TX2_LPD 16 16 RDPCS_PHY_DP_TX2_RATE 17 19 RDPCS_PHY_DP_TX2_WIDTH 20 21 RDPCS_PHY_DP_TX2_DETRX_REQ 22 22 RDPCS_PHY_DP_TX2_DETRX_RESULT 23 23 RDPCS_PHY_DP_TX3_LPD 24 24 RDPCS_PHY_DP_TX3_RATE 25 27 RDPCS_PHY_DP_TX3_WIDTH 28 29 RDPCS_PHY_DP_TX3_DETRX_REQ 30 30 RDPCS_PHY_DP_TX3_DETRX_RESULT 31 31 mmRDPCSTX4_RDPCSTX_PHY_CNTL6 0 0x2ca6 13 0 2 RDPCS_PHY_DP_TX0_PSTATE 0 1 RDPCS_PHY_DP_TX0_MPLL_EN 2 2 RDPCS_PHY_DP_TX1_PSTATE 4 5 RDPCS_PHY_DP_TX1_MPLL_EN 6 6 RDPCS_PHY_DP_TX2_PSTATE 8 9 RDPCS_PHY_DP_TX2_MPLL_EN 10 10 RDPCS_PHY_DP_TX3_PSTATE 12 13 RDPCS_PHY_DP_TX3_MPLL_EN 14 14 RDPCS_PHY_DPALT_DP4 16 16 RDPCS_PHY_DPALT_DISABLE 17 17 RDPCS_PHY_DPALT_DISABLE_ACK 18 18 RDPCS_PHY_DP_REF_CLK_EN 19 19 RDPCS_PHY_DP_REF_CLK_REQ 20 20 mmRDPCSTX4_RDPCSTX_PHY_CNTL7 0 0x2ca7 2 0 2 RDPCS_PHY_DP_MPLLB_FRACN_DEN 0 15 RDPCS_PHY_DP_MPLLB_FRACN_QUOT 16 31 mmRDPCSTX4_RDPCSTX_PHY_CNTL8 0 0x2ca8 1 0 2 RDPCS_PHY_DP_MPLLB_SSC_PEAK 0 19 mmRDPCSTX4_RDPCSTX_PHY_CNTL9 0 0x2ca9 2 0 2 RDPCS_PHY_DP_MPLLB_SSC_STEPSIZE 0 20 RDPCS_PHY_DP_MPLLB_SSC_UP_SPREAD 24 24 mmRDPCSTX4_RDPCSTX_PHY_CNTL10 0 0x2caa 1 0 2 RDPCS_PHY_DP_MPLLB_FRACN_REM 0 15 mmRDPCSTX4_RDPCSTX_PHY_CNTL11 0 0x2cab 4 0 2 RDPCS_PHY_DP_MPLLB_MULTIPLIER 4 15 RDPCS_PHY_HDMI_MPLLB_HDMI_DIV 16 18 RDPCS_PHY_DP_REF_CLK_MPLLB_DIV 20 22 RDPCS_PHY_HDMI_MPLLB_HDMI_PIXEL_CLK_DIV 24 25 mmRDPCSTX4_RDPCSTX_PHY_CNTL12 0 0x2cac 5 0 2 RDPCS_PHY_DP_MPLLB_DIV5_CLK_EN 0 0 RDPCS_PHY_DP_MPLLB_WORD_DIV2_EN 2 2 RDPCS_PHY_DP_MPLLB_TX_CLK_DIV 4 6 RDPCS_PHY_DP_MPLLB_STATE 7 7 RDPCS_PHY_DP_MPLLB_SSC_EN 8 8 mmRDPCSTX4_RDPCSTX_PHY_CNTL13 0 0x2cad 4 0 2 RDPCS_PHY_DP_MPLLB_DIV_MULTIPLIER 20 27 RDPCS_PHY_DP_MPLLB_DIV_CLK_EN 28 28 RDPCS_PHY_DP_MPLLB_FORCE_EN 29 29 RDPCS_PHY_DP_MPLLB_INIT_CAL_DISABLE 30 30 mmRDPCSTX4_RDPCSTX_PHY_CNTL14 0 0x2cae 3 0 2 RDPCS_PHY_DP_MPLLB_CAL_FORCE 0 0 RDPCS_PHY_DP_MPLLB_FRACN_EN 24 24 RDPCS_PHY_DP_MPLLB_PMIX_EN 28 28 mmRDPCSTX4_RDPCSTX_PHY_FUSE0 0 0x2caf 5 0 2 RDPCS_PHY_DP_TX0_EQ_MAIN 0 5 RDPCS_PHY_DP_TX0_EQ_PRE 6 11 RDPCS_PHY_DP_TX0_EQ_POST 12 17 RDPCS_PHY_DP_MPLLB_V2I 18 19 RDPCS_PHY_DP_MPLLB_FREQ_VCO 20 21 mmRDPCSTX4_RDPCSTX_PHY_FUSE1 0 0x2cb0 5 0 2 RDPCS_PHY_DP_TX1_EQ_MAIN 0 5 RDPCS_PHY_DP_TX1_EQ_PRE 6 11 RDPCS_PHY_DP_TX1_EQ_POST 12 17 RDPCS_PHY_DP_MPLLB_CP_INT 18 24 RDPCS_PHY_DP_MPLLB_CP_PROP 25 31 mmRDPCSTX4_RDPCSTX_PHY_FUSE2 0 0x2cb1 3 0 2 RDPCS_PHY_DP_TX2_EQ_MAIN 0 5 RDPCS_PHY_DP_TX2_EQ_PRE 6 11 RDPCS_PHY_DP_TX2_EQ_POST 12 17 mmRDPCSTX4_RDPCSTX_PHY_FUSE3 0 0x2cb2 5 0 2 RDPCS_PHY_DP_TX3_EQ_MAIN 0 5 RDPCS_PHY_DP_TX3_EQ_PRE 6 11 RDPCS_PHY_DP_TX3_EQ_POST 12 17 RDPCS_PHY_DCO_FINETUNE 18 23 RDPCS_PHY_DCO_RANGE 24 25 mmRDPCSTX4_RDPCSTX_PHY_RX_LD_VAL 0 0x2cb3 2 0 2 RDPCS_PHY_RX_REF_LD_VAL 0 6 RDPCS_PHY_RX_VCO_LD_VAL 8 20 mmRDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL3 0 0x2cb4 24 0 2 RDPCS_PHY_DP_TX0_RESET_RESERVED 0 0 RDPCS_PHY_DP_TX0_DISABLE_RESERVED 1 1 RDPCS_PHY_DP_TX0_CLK_RDY_RESERVED 2 2 RDPCS_PHY_DP_TX0_DATA_EN_RESERVED 3 3 RDPCS_PHY_DP_TX0_REQ_RESERVED 4 4 RDPCS_PHY_DP_TX0_ACK_RESERVED 5 5 RDPCS_PHY_DP_TX1_RESET_RESERVED 8 8 RDPCS_PHY_DP_TX1_DISABLE_RESERVED 9 9 RDPCS_PHY_DP_TX1_CLK_RDY_RESERVED 10 10 RDPCS_PHY_DP_TX1_DATA_EN_RESERVED 11 11 RDPCS_PHY_DP_TX1_REQ_RESERVED 12 12 RDPCS_PHY_DP_TX1_ACK_RESERVED 13 13 RDPCS_PHY_DP_TX2_RESET_RESERVED 16 16 RDPCS_PHY_DP_TX2_DISABLE_RESERVED 17 17 RDPCS_PHY_DP_TX2_CLK_RDY_RESERVED 18 18 RDPCS_PHY_DP_TX2_DATA_EN_RESERVED 19 19 RDPCS_PHY_DP_TX2_REQ_RESERVED 20 20 RDPCS_PHY_DP_TX2_ACK_RESERVED 21 21 RDPCS_PHY_DP_TX3_RESET_RESERVED 24 24 RDPCS_PHY_DP_TX3_DISABLE_RESERVED 25 25 RDPCS_PHY_DP_TX3_CLK_RDY_RESERVED 26 26 RDPCS_PHY_DP_TX3_DATA_EN_RESERVED 27 27 RDPCS_PHY_DP_TX3_REQ_RESERVED 28 28 RDPCS_PHY_DP_TX3_ACK_RESERVED 29 29 mmRDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL6 0 0x2cb5 13 0 2 RDPCS_PHY_DP_TX0_PSTATE_RESERVED 0 1 RDPCS_PHY_DP_TX0_MPLL_EN_RESERVED 2 2 RDPCS_PHY_DP_TX1_PSTATE_RESERVED 4 5 RDPCS_PHY_DP_TX1_MPLL_EN_RESERVED 6 6 RDPCS_PHY_DP_TX2_PSTATE_RESERVED 8 9 RDPCS_PHY_DP_TX2_MPLL_EN_RESERVED 10 10 RDPCS_PHY_DP_TX3_PSTATE_RESERVED 12 13 RDPCS_PHY_DP_TX3_MPLL_EN_RESERVED 14 14 RDPCS_PHY_DPALT_DP4_RESERVED 16 16 RDPCS_PHY_DPALT_DISABLE_RESERVED 17 17 RDPCS_PHY_DPALT_DISABLE_ACK_RESERVED 18 18 RDPCS_PHY_DP_REF_CLK_EN_RESERVED 19 19 RDPCS_PHY_DP_REF_CLK_REQ_RESERVED 20 20 mmRDPCSTX4_RDPCSTX_DPALT_CONTROL_REG 0 0x2cb6 3 0 2 RDPCS_ALLOW_DRIVER_ACCESS 0 0 RDPCS_DRIVER_ACCESS_BLOCKED 4 4 RDPCS_DPALT_CONTROL_SPARE 8 15 mmDPCSSYS_CR4_DPCSSYS_CR_ADDR 0 0x2c94 1 0 2 RDPCS_TX_CR_ADDR 0 15 mmDPCSSYS_CR4_DPCSSYS_CR_DATA 0 0x2c95 1 0 2 RDPCS_TX_CR_DATA 0 15 mmDPCSTX5_DPCSTX_TX_CLOCK_CNTL 0 0x2d60 4 0 2 DPCS_SYMCLK_GATE_DIS 0 0 DPCS_SYMCLK_EN 1 1 DPCS_SYMCLK_CLOCK_ON 2 2 DPCS_SYMCLK_DIV2_CLOCK_ON 3 3 mmDPCSTX5_DPCSTX_TX_CNTL 0 0x2d61 8 0 2 DPCS_TX_PLL_UPDATE_REQ 12 12 DPCS_TX_PLL_UPDATE_PENDING 13 13 DPCS_TX_DATA_SWAP 14 14 DPCS_TX_DATA_ORDER_INVERT 15 15 DPCS_TX_FIFO_EN 16 16 DPCS_TX_FIFO_START 17 17 DPCS_TX_FIFO_RD_START_DELAY 20 23 DPCS_TX_SOFT_RESET 31 31 mmDPCSTX5_DPCSTX_CBUS_CNTL 0 0x2d62 2 0 2 DPCS_CBUS_WR_CMD_DELAY 0 7 DPCS_CBUS_SOFT_RESET 31 31 mmDPCSTX5_DPCSTX_INTERRUPT_CNTL 0 0x2d63 10 0 2 DPCS_REG_FIFO_OVERFLOW 0 0 DPCS_REG_ERROR_CLR 1 1 DPCS_REG_FIFO_ERROR_MASK 4 4 DPCS_TX0_FIFO_ERROR 8 8 DPCS_TX1_FIFO_ERROR 9 9 DPCS_TX2_FIFO_ERROR 10 10 DPCS_TX3_FIFO_ERROR 11 11 DPCS_TX_ERROR_CLR 12 12 DPCS_TX_FIFO_ERROR_MASK 16 16 DPCS_INTERRUPT_MASK 20 20 mmDPCSTX5_DPCSTX_PLL_UPDATE_ADDR 0 0x2d64 1 0 2 DPCS_PLL_UPDATE_ADDR 0 17 mmDPCSTX5_DPCSTX_PLL_UPDATE_DATA 0 0x2d65 1 0 2 DPCS_PLL_UPDATE_DATA 0 31 mmDPCSTX5_DPCSTX_DEBUG_CONFIG 0 0x2d66 6 0 2 DPCS_DBG_EN 0 0 DPCS_DBG_CFGCLK_SEL 1 3 DPCS_DBG_TX_SYMCLK_SEL 4 6 DPCS_DBG_TX_SYMCLK_DIV2_SEL 8 10 DPCS_DBG_CBUS_DIS 14 14 DPCS_TEST_DEBUG_WRITE_EN 16 16 mmRDPCSTX5_RDPCSTX_CNTL 0 0x2d68 13 0 2 RDPCS_CBUS_SOFT_RESET 0 0 RDPCS_SRAM_SOFT_RESET 4 4 RDPCS_TX_FIFO_LANE0_EN 12 12 RDPCS_TX_FIFO_LANE1_EN 13 13 RDPCS_TX_FIFO_LANE2_EN 14 14 RDPCS_TX_FIFO_LANE3_EN 15 15 RDPCS_TX_FIFO_EN 16 16 RDPCS_TX_FIFO_START 17 17 RDPCS_TX_FIFO_RD_START_DELAY 20 23 RDPCS_CR_REGISTER_BLOCK_EN 24 24 RDPCS_NON_DPALT_REGISTER_BLOCK_EN 25 25 RDPCS_DPALT_BLOCK_STATUS 26 26 RDPCS_TX_SOFT_RESET 31 31 mmRDPCSTX5_RDPCSTX_CLOCK_CNTL 0 0x2d69 12 0 2 RDPCS_EXT_REFCLK_EN 0 0 RDPCS_SYMCLK_DIV2_TX0_EN 4 4 RDPCS_SYMCLK_DIV2_TX1_EN 5 5 RDPCS_SYMCLK_DIV2_TX2_EN 6 6 RDPCS_SYMCLK_DIV2_TX3_EN 7 7 RDPCS_SYMCLK_DIV2_GATE_DIS 8 8 RDPCS_SYMCLK_DIV2_EN 9 9 RDPCS_SYMCLK_DIV2_CLOCK_ON 10 10 RDPCS_SRAMCLK_GATE_DIS 12 12 RDPCS_SRAMCLK_EN 13 13 RDPCS_SRAMCLK_CLOCK_ON 14 14 RDPCS_SRAMCLK_BYPASS 16 16 mmRDPCSTX5_RDPCSTX_INTERRUPT_CONTROL 0 0x2d6a 15 0 2 RDPCS_REG_FIFO_OVERFLOW 0 0 RDPCS_DPALT_DISABLE_TOGGLE 1 1 RDPCS_DPALT_4LANE_TOGGLE 2 2 RDPCS_TX0_FIFO_ERROR 4 4 RDPCS_TX1_FIFO_ERROR 5 5 RDPCS_TX2_FIFO_ERROR 6 6 RDPCS_TX3_FIFO_ERROR 7 7 RDPCS_REG_ERROR_CLR 8 8 RDPCS_DPALT_DISABLE_TOGGLE_CLR 9 9 RDPCS_DPALT_4LANE_TOGGLE_CLR 10 10 RDPCS_TX_ERROR_CLR 12 12 RDPCS_REG_FIFO_ERROR_MASK 16 16 RDPCS_DPALT_DISABLE_TOGGLE_MASK 17 17 RDPCS_DPALT_4LANE_TOGGLE_MASK 18 18 RDPCS_TX_FIFO_ERROR_MASK 20 20 mmRDPCSTX5_RDPCSTX_PLL_UPDATE_DATA 0 0x2d6b 1 0 2 RDPCS_PLL_UPDATE_DATA 0 0 mmRDPCSTX5_RDPCS_TX_CR_ADDR 0 0x2d6c 1 0 2 RDPCS_TX_CR_ADDR 0 15 mmRDPCSTX5_RDPCS_TX_CR_DATA 0 0x2d6d 1 0 2 RDPCS_TX_CR_DATA 0 15 mmRDPCSTX5_RDPCS_TX_SRAM_CNTL 0 0x2d6e 3 0 2 RDPCS_MEM_PWR_DIS 20 20 RDPCS_MEM_PWR_FORCE 24 25 RDPCS_MEM_PWR_PWR_STATE 28 29 mmRDPCSTX5_RDPCSTX_MEM_POWER_CTRL 0 0x2d6f 7 0 2 RDPCS_FUSE_RM_FUSES 0 11 RDPCS_FUSE_CUSTOM_RM_FUSES 12 25 RDPCS_MEM_POWER_CTRL_PDP_BC1 26 26 RDPCS_MEM_POWER_CTRL_PDP_BC2 27 27 RDPCS_MEM_POWER_CTRL_HD_BC1 28 28 RDPCS_MEM_POWER_CTRL_HD_BC2 29 29 RDPCS_LIVMIN_DIS_SRAM 30 30 mmRDPCSTX5_RDPCSTX_MEM_POWER_CTRL2 0 0x2d70 2 0 2 RDPCS_MEM_POWER_CTRL_POFF 0 1 RDPCS_MEM_POWER_CTRL_FISO 2 2 mmRDPCSTX5_RDPCSTX_SCRATCH 0 0x2d71 1 0 2 RDPCSTX_SCRATCH 0 31 mmRDPCSTX5_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG 0 0x2d74 3 0 2 RDPCS_DMCU_DPALT_DIS_BLOCK_REG 0 0 RDPCS_DMCU_DPALT_FORCE_SYMCLK_DIV2_DIS 4 4 RDPCS_DMCU_DPALT_CONTROL_SPARE 8 15 mmRDPCSTX5_RDPCSTX_DEBUG_CONFIG 0 0x2d75 7 0 2 RDPCS_DBG_EN 0 0 RDPCS_DBG_SEL_ASYNC_8BIT 4 6 RDPCS_DBG_SEL_ASYNC_SWAP 7 7 RDPCS_DBG_SEL_TEST_CLK 8 12 RDPCS_DBG_CR_COUNT_EXPIRE 15 15 RDPCS_DBG_CR_COUNT_MAX 16 23 RDPCS_DBG_CR_COUNT 24 31 mmRDPCSTX5_RDPCSTX_PHY_CNTL0 0 0x2d78 17 0 2 RDPCS_PHY_RESET 0 0 RDPCS_PHY_TCA_PHY_RESET 1 1 RDPCS_PHY_TCA_APB_RESET_N 2 2 RDPCS_PHY_TEST_POWERDOWN 3 3 RDPCS_PHY_DTB_OUT 4 5 RDPCS_PHY_HDMIMODE_ENABLE 8 8 RDPCS_PHY_REF_RANGE 9 13 RDPCS_PHY_TX_VBOOST_LVL 14 16 RDPCS_PHY_RTUNE_REQ 17 17 RDPCS_PHY_RTUNE_ACK 18 18 RDPCS_PHY_CR_PARA_SEL 20 20 RDPCS_PHY_CR_MUX_SEL 21 21 RDPCS_PHY_REF_CLKDET_EN 24 24 RDPCS_PHY_REF_CLKDET_RESULT 25 25 RDPCS_SRAM_INIT_DONE 28 28 RDPCS_SRAM_EXT_LD_DONE 29 29 RDPCS_SRAM_BYPASS 31 31 mmRDPCSTX5_RDPCSTX_PHY_CNTL1 0 0x2d79 8 0 2 RDPCS_PHY_PG_MODE_EN 0 0 RDPCS_PHY_PCS_PWR_EN 1 1 RDPCS_PHY_PCS_PWR_STABLE 2 2 RDPCS_PHY_PMA_PWR_EN 3 3 RDPCS_PHY_PMA_PWR_STABLE 4 4 RDPCS_PHY_DP_PG_RESET 5 5 RDPCS_PHY_ANA_PWR_EN 6 6 RDPCS_PHY_ANA_PWR_STABLE 7 7 mmRDPCSTX5_RDPCSTX_PHY_CNTL2 0 0x2d7a 9 0 2 RDPCS_PHY_DP4_POR 3 3 RDPCS_PHY_DP_LANE0_RX2TX_PAR_LB_EN 4 4 RDPCS_PHY_DP_LANE1_RX2TX_PAR_LB_EN 5 5 RDPCS_PHY_DP_LANE2_RX2TX_PAR_LB_EN 6 6 RDPCS_PHY_DP_LANE3_RX2TX_PAR_LB_EN 7 7 RDPCS_PHY_DP_LANE0_TX2RX_SER_LB_EN 8 8 RDPCS_PHY_DP_LANE1_TX2RX_SER_LB_EN 9 9 RDPCS_PHY_DP_LANE2_TX2RX_SER_LB_EN 10 10 RDPCS_PHY_DP_LANE3_TX2RX_SER_LB_EN 11 11 mmRDPCSTX5_RDPCSTX_PHY_CNTL3 0 0x2d7b 24 0 2 RDPCS_PHY_DP_TX0_RESET 0 0 RDPCS_PHY_DP_TX0_DISABLE 1 1 RDPCS_PHY_DP_TX0_CLK_RDY 2 2 RDPCS_PHY_DP_TX0_DATA_EN 3 3 RDPCS_PHY_DP_TX0_REQ 4 4 RDPCS_PHY_DP_TX0_ACK 5 5 RDPCS_PHY_DP_TX1_RESET 8 8 RDPCS_PHY_DP_TX1_DISABLE 9 9 RDPCS_PHY_DP_TX1_CLK_RDY 10 10 RDPCS_PHY_DP_TX1_DATA_EN 11 11 RDPCS_PHY_DP_TX1_REQ 12 12 RDPCS_PHY_DP_TX1_ACK 13 13 RDPCS_PHY_DP_TX2_RESET 16 16 RDPCS_PHY_DP_TX2_DISABLE 17 17 RDPCS_PHY_DP_TX2_CLK_RDY 18 18 RDPCS_PHY_DP_TX2_DATA_EN 19 19 RDPCS_PHY_DP_TX2_REQ 20 20 RDPCS_PHY_DP_TX2_ACK 21 21 RDPCS_PHY_DP_TX3_RESET 24 24 RDPCS_PHY_DP_TX3_DISABLE 25 25 RDPCS_PHY_DP_TX3_CLK_RDY 26 26 RDPCS_PHY_DP_TX3_DATA_EN 27 27 RDPCS_PHY_DP_TX3_REQ 28 28 RDPCS_PHY_DP_TX3_ACK 29 29 mmRDPCSTX5_RDPCSTX_PHY_CNTL4 0 0x2d7c 16 0 2 RDPCS_PHY_DP_TX0_TERM_CTRL 0 2 RDPCS_PHY_DP_TX0_INVERT 4 4 RDPCS_PHY_DP_TX0_BYPASS_EQ_CALC 6 6 RDPCS_PHY_DP_TX0_HP_PROT_EN 7 7 RDPCS_PHY_DP_TX1_TERM_CTRL 8 10 RDPCS_PHY_DP_TX1_INVERT 12 12 RDPCS_PHY_DP_TX1_BYPASS_EQ_CALC 14 14 RDPCS_PHY_DP_TX1_HP_PROT_EN 15 15 RDPCS_PHY_DP_TX2_TERM_CTRL 16 18 RDPCS_PHY_DP_TX2_INVERT 20 20 RDPCS_PHY_DP_TX2_BYPASS_EQ_CALC 22 22 RDPCS_PHY_DP_TX2_HP_PROT_EN 23 23 RDPCS_PHY_DP_TX3_TERM_CTRL 24 26 RDPCS_PHY_DP_TX3_INVERT 28 28 RDPCS_PHY_DP_TX3_BYPASS_EQ_CALC 30 30 RDPCS_PHY_DP_TX3_HP_PROT_EN 31 31 mmRDPCSTX5_RDPCSTX_PHY_CNTL5 0 0x2d7d 20 0 2 RDPCS_PHY_DP_TX0_LPD 0 0 RDPCS_PHY_DP_TX0_RATE 1 3 RDPCS_PHY_DP_TX0_WIDTH 4 5 RDPCS_PHY_DP_TX0_DETRX_REQ 6 6 RDPCS_PHY_DP_TX0_DETRX_RESULT 7 7 RDPCS_PHY_DP_TX1_LPD 8 8 RDPCS_PHY_DP_TX1_RATE 9 11 RDPCS_PHY_DP_TX1_WIDTH 12 13 RDPCS_PHY_DP_TX1_DETRX_REQ 14 14 RDPCS_PHY_DP_TX1_DETRX_RESULT 15 15 RDPCS_PHY_DP_TX2_LPD 16 16 RDPCS_PHY_DP_TX2_RATE 17 19 RDPCS_PHY_DP_TX2_WIDTH 20 21 RDPCS_PHY_DP_TX2_DETRX_REQ 22 22 RDPCS_PHY_DP_TX2_DETRX_RESULT 23 23 RDPCS_PHY_DP_TX3_LPD 24 24 RDPCS_PHY_DP_TX3_RATE 25 27 RDPCS_PHY_DP_TX3_WIDTH 28 29 RDPCS_PHY_DP_TX3_DETRX_REQ 30 30 RDPCS_PHY_DP_TX3_DETRX_RESULT 31 31 mmRDPCSTX5_RDPCSTX_PHY_CNTL6 0 0x2d7e 13 0 2 RDPCS_PHY_DP_TX0_PSTATE 0 1 RDPCS_PHY_DP_TX0_MPLL_EN 2 2 RDPCS_PHY_DP_TX1_PSTATE 4 5 RDPCS_PHY_DP_TX1_MPLL_EN 6 6 RDPCS_PHY_DP_TX2_PSTATE 8 9 RDPCS_PHY_DP_TX2_MPLL_EN 10 10 RDPCS_PHY_DP_TX3_PSTATE 12 13 RDPCS_PHY_DP_TX3_MPLL_EN 14 14 RDPCS_PHY_DPALT_DP4 16 16 RDPCS_PHY_DPALT_DISABLE 17 17 RDPCS_PHY_DPALT_DISABLE_ACK 18 18 RDPCS_PHY_DP_REF_CLK_EN 19 19 RDPCS_PHY_DP_REF_CLK_REQ 20 20 mmRDPCSTX5_RDPCSTX_PHY_CNTL7 0 0x2d7f 2 0 2 RDPCS_PHY_DP_MPLLB_FRACN_DEN 0 15 RDPCS_PHY_DP_MPLLB_FRACN_QUOT 16 31 mmRDPCSTX5_RDPCSTX_PHY_CNTL8 0 0x2d80 1 0 2 RDPCS_PHY_DP_MPLLB_SSC_PEAK 0 19 mmRDPCSTX5_RDPCSTX_PHY_CNTL9 0 0x2d81 2 0 2 RDPCS_PHY_DP_MPLLB_SSC_STEPSIZE 0 20 RDPCS_PHY_DP_MPLLB_SSC_UP_SPREAD 24 24 mmRDPCSTX5_RDPCSTX_PHY_CNTL10 0 0x2d82 1 0 2 RDPCS_PHY_DP_MPLLB_FRACN_REM 0 15 mmRDPCSTX5_RDPCSTX_PHY_CNTL11 0 0x2d83 4 0 2 RDPCS_PHY_DP_MPLLB_MULTIPLIER 4 15 RDPCS_PHY_HDMI_MPLLB_HDMI_DIV 16 18 RDPCS_PHY_DP_REF_CLK_MPLLB_DIV 20 22 RDPCS_PHY_HDMI_MPLLB_HDMI_PIXEL_CLK_DIV 24 25 mmRDPCSTX5_RDPCSTX_PHY_CNTL12 0 0x2d84 5 0 2 RDPCS_PHY_DP_MPLLB_DIV5_CLK_EN 0 0 RDPCS_PHY_DP_MPLLB_WORD_DIV2_EN 2 2 RDPCS_PHY_DP_MPLLB_TX_CLK_DIV 4 6 RDPCS_PHY_DP_MPLLB_STATE 7 7 RDPCS_PHY_DP_MPLLB_SSC_EN 8 8 mmRDPCSTX5_RDPCSTX_PHY_CNTL13 0 0x2d85 4 0 2 RDPCS_PHY_DP_MPLLB_DIV_MULTIPLIER 20 27 RDPCS_PHY_DP_MPLLB_DIV_CLK_EN 28 28 RDPCS_PHY_DP_MPLLB_FORCE_EN 29 29 RDPCS_PHY_DP_MPLLB_INIT_CAL_DISABLE 30 30 mmRDPCSTX5_RDPCSTX_PHY_CNTL14 0 0x2d86 3 0 2 RDPCS_PHY_DP_MPLLB_CAL_FORCE 0 0 RDPCS_PHY_DP_MPLLB_FRACN_EN 24 24 RDPCS_PHY_DP_MPLLB_PMIX_EN 28 28 mmRDPCSTX5_RDPCSTX_PHY_FUSE0 0 0x2d87 5 0 2 RDPCS_PHY_DP_TX0_EQ_MAIN 0 5 RDPCS_PHY_DP_TX0_EQ_PRE 6 11 RDPCS_PHY_DP_TX0_EQ_POST 12 17 RDPCS_PHY_DP_MPLLB_V2I 18 19 RDPCS_PHY_DP_MPLLB_FREQ_VCO 20 21 mmRDPCSTX5_RDPCSTX_PHY_FUSE1 0 0x2d88 5 0 2 RDPCS_PHY_DP_TX1_EQ_MAIN 0 5 RDPCS_PHY_DP_TX1_EQ_PRE 6 11 RDPCS_PHY_DP_TX1_EQ_POST 12 17 RDPCS_PHY_DP_MPLLB_CP_INT 18 24 RDPCS_PHY_DP_MPLLB_CP_PROP 25 31 mmRDPCSTX5_RDPCSTX_PHY_FUSE2 0 0x2d89 3 0 2 RDPCS_PHY_DP_TX2_EQ_MAIN 0 5 RDPCS_PHY_DP_TX2_EQ_PRE 6 11 RDPCS_PHY_DP_TX2_EQ_POST 12 17 mmRDPCSTX5_RDPCSTX_PHY_FUSE3 0 0x2d8a 5 0 2 RDPCS_PHY_DP_TX3_EQ_MAIN 0 5 RDPCS_PHY_DP_TX3_EQ_PRE 6 11 RDPCS_PHY_DP_TX3_EQ_POST 12 17 RDPCS_PHY_DCO_FINETUNE 18 23 RDPCS_PHY_DCO_RANGE 24 25 mmRDPCSTX5_RDPCSTX_PHY_RX_LD_VAL 0 0x2d8b 2 0 2 RDPCS_PHY_RX_REF_LD_VAL 0 6 RDPCS_PHY_RX_VCO_LD_VAL 8 20 mmRDPCSTX5_RDPCSTX_DMCU_DPALT_PHY_CNTL3 0 0x2d8c 24 0 2 RDPCS_PHY_DP_TX0_RESET_RESERVED 0 0 RDPCS_PHY_DP_TX0_DISABLE_RESERVED 1 1 RDPCS_PHY_DP_TX0_CLK_RDY_RESERVED 2 2 RDPCS_PHY_DP_TX0_DATA_EN_RESERVED 3 3 RDPCS_PHY_DP_TX0_REQ_RESERVED 4 4 RDPCS_PHY_DP_TX0_ACK_RESERVED 5 5 RDPCS_PHY_DP_TX1_RESET_RESERVED 8 8 RDPCS_PHY_DP_TX1_DISABLE_RESERVED 9 9 RDPCS_PHY_DP_TX1_CLK_RDY_RESERVED 10 10 RDPCS_PHY_DP_TX1_DATA_EN_RESERVED 11 11 RDPCS_PHY_DP_TX1_REQ_RESERVED 12 12 RDPCS_PHY_DP_TX1_ACK_RESERVED 13 13 RDPCS_PHY_DP_TX2_RESET_RESERVED 16 16 RDPCS_PHY_DP_TX2_DISABLE_RESERVED 17 17 RDPCS_PHY_DP_TX2_CLK_RDY_RESERVED 18 18 RDPCS_PHY_DP_TX2_DATA_EN_RESERVED 19 19 RDPCS_PHY_DP_TX2_REQ_RESERVED 20 20 RDPCS_PHY_DP_TX2_ACK_RESERVED 21 21 RDPCS_PHY_DP_TX3_RESET_RESERVED 24 24 RDPCS_PHY_DP_TX3_DISABLE_RESERVED 25 25 RDPCS_PHY_DP_TX3_CLK_RDY_RESERVED 26 26 RDPCS_PHY_DP_TX3_DATA_EN_RESERVED 27 27 RDPCS_PHY_DP_TX3_REQ_RESERVED 28 28 RDPCS_PHY_DP_TX3_ACK_RESERVED 29 29 mmRDPCSTX5_RDPCSTX_DMCU_DPALT_PHY_CNTL6 0 0x2d8d 13 0 2 RDPCS_PHY_DP_TX0_PSTATE_RESERVED 0 1 RDPCS_PHY_DP_TX0_MPLL_EN_RESERVED 2 2 RDPCS_PHY_DP_TX1_PSTATE_RESERVED 4 5 RDPCS_PHY_DP_TX1_MPLL_EN_RESERVED 6 6 RDPCS_PHY_DP_TX2_PSTATE_RESERVED 8 9 RDPCS_PHY_DP_TX2_MPLL_EN_RESERVED 10 10 RDPCS_PHY_DP_TX3_PSTATE_RESERVED 12 13 RDPCS_PHY_DP_TX3_MPLL_EN_RESERVED 14 14 RDPCS_PHY_DPALT_DP4_RESERVED 16 16 RDPCS_PHY_DPALT_DISABLE_RESERVED 17 17 RDPCS_PHY_DPALT_DISABLE_ACK_RESERVED 18 18 RDPCS_PHY_DP_REF_CLK_EN_RESERVED 19 19 RDPCS_PHY_DP_REF_CLK_REQ_RESERVED 20 20 mmRDPCSTX5_RDPCSTX_DPALT_CONTROL_REG 0 0x2d8e 3 0 2 RDPCS_ALLOW_DRIVER_ACCESS 0 0 RDPCS_DRIVER_ACCESS_BLOCKED 4 4 RDPCS_DPALT_CONTROL_SPARE 8 15 mmDPCSSYS_CR5_DPCSSYS_CR_ADDR 0 0x2d6c 1 0 2 RDPCS_TX_CR_ADDR 0 15 mmDPCSSYS_CR5_DPCSSYS_CR_DATA 0 0x2d6d 1 0 2 RDPCS_TX_CR_DATA 0 15