56 mmDPCSTX0_DPCSTX_TX_CLOCK_CNTL 0 0x2928 4 0 2 DPCS_SYMCLK_GATE_DIS 0 0 DPCS_SYMCLK_EN 1 1 DPCS_SYMCLK_CLOCK_ON 2 2 DPCS_SYMCLK_DIV2_CLOCK_ON 3 3 mmDPCSTX0_DPCSTX_TX_CNTL 0 0x2929 8 0 2 DPCS_TX_PLL_UPDATE_REQ 12 12 DPCS_TX_PLL_UPDATE_PENDING 13 13 DPCS_TX_DATA_SWAP 14 14 DPCS_TX_DATA_ORDER_INVERT 15 15 DPCS_TX_FIFO_EN 16 16 DPCS_TX_FIFO_START 17 17 DPCS_TX_FIFO_RD_START_DELAY 20 23 DPCS_TX_SOFT_RESET 31 31 mmDPCSTX0_DPCSTX_CBUS_CNTL 0 0x292a 2 0 2 DPCS_CBUS_WR_CMD_DELAY 0 7 DPCS_CBUS_SOFT_RESET 31 31 mmDPCSTX0_DPCSTX_INTERRUPT_CNTL 0 0x292b 10 0 2 DPCS_REG_FIFO_OVERFLOW 0 0 DPCS_REG_ERROR_CLR 1 1 DPCS_REG_FIFO_ERROR_MASK 4 4 DPCS_TX0_FIFO_ERROR 8 8 DPCS_TX1_FIFO_ERROR 9 9 DPCS_TX2_FIFO_ERROR 10 10 DPCS_TX3_FIFO_ERROR 11 11 DPCS_TX_ERROR_CLR 12 12 DPCS_TX_FIFO_ERROR_MASK 16 16 DPCS_INTERRUPT_MASK 20 20 mmDPCSTX0_DPCSTX_PLL_UPDATE_ADDR 0 0x292c 1 0 2 DPCS_PLL_UPDATE_ADDR 0 17 mmDPCSTX0_DPCSTX_PLL_UPDATE_DATA 0 0x292d 1 0 2 DPCS_PLL_UPDATE_DATA 0 31 mmRDPCSTX0_RDPCSTX_CNTL 0 0x2930 10 0 2 RDPCS_CBUS_SOFT_RESET 0 0 RDPCS_SRAM_SOFT_RESET 4 4 RDPCS_TX_FIFO_LANE0_EN 12 12 RDPCS_TX_FIFO_LANE1_EN 13 13 RDPCS_TX_FIFO_LANE2_EN 14 14 RDPCS_TX_FIFO_LANE3_EN 15 15 RDPCS_TX_FIFO_EN 16 16 RDPCS_TX_FIFO_START 17 17 RDPCS_TX_FIFO_RD_START_DELAY 20 23 RDPCS_TX_SOFT_RESET 31 31 mmRDPCSTX0_RDPCSTX_CLOCK_CNTL 0 0x2931 12 0 2 RDPCS_EXT_REFCLK_EN 0 0 RDPCS_SYMCLK_DIV2_TX0_EN 4 4 RDPCS_SYMCLK_DIV2_TX1_EN 5 5 RDPCS_SYMCLK_DIV2_TX2_EN 6 6 RDPCS_SYMCLK_DIV2_TX3_EN 7 7 RDPCS_SYMCLK_DIV2_GATE_DIS 8 8 RDPCS_SYMCLK_DIV2_EN 9 9 RDPCS_SYMCLK_DIV2_CLOCK_ON 10 10 RDPCS_SRAMCLK_GATE_DIS 12 12 RDPCS_SRAMCLK_EN 13 13 RDPCS_SRAMCLK_CLOCK_ON 14 14 RDPCS_SRAMCLK_BYPASS 16 16 mmRDPCSTX0_RDPCSTX_INTERRUPT_CONTROL 0 0x2932 15 0 2 RDPCS_REG_FIFO_OVERFLOW 0 0 RDPCS_DPALT_DISABLE_TOGGLE 1 1 RDPCS_DPALT_4LANE_TOGGLE 2 2 RDPCS_TX0_FIFO_ERROR 4 4 RDPCS_TX1_FIFO_ERROR 5 5 RDPCS_TX2_FIFO_ERROR 6 6 RDPCS_TX3_FIFO_ERROR 7 7 RDPCS_REG_ERROR_CLR 8 8 RDPCS_DPALT_DISABLE_TOGGLE_CLR 9 9 RDPCS_DPALT_4LANE_TOGGLE_CLR 10 10 RDPCS_TX_ERROR_CLR 12 12 RDPCS_REG_FIFO_ERROR_MASK 16 16 RDPCS_DPALT_DISABLE_TOGGLE_MASK 17 17 RDPCS_DPALT_4LANE_TOGGLE_MASK 18 18 RDPCS_TX_FIFO_ERROR_MASK 20 20 mmRDPCSTX0_RDPCSTX_PLL_UPDATE_DATA 0 0x2933 1 0 2 RDPCS_PLL_UPDATE_DATA 0 0 mmRDPCSTX0_RDPCS_TX_CR_ADDR 0 0x2934 1 0 2 RDPCS_TX_CR_ADDR 0 15 mmRDPCSTX0_RDPCS_TX_CR_DATA 0 0x2935 1 0 2 RDPCS_TX_CR_DATA 0 15 mmRDPCSTX0_RDPCSTX_SCRATCH 0 0x2939 1 0 2 RDPCSTX_SCRATCH 0 31 mmRDPCSTX0_RDPCSTX_PHY_CNTL0 0 0x2940 17 0 2 RDPCS_PHY_RESET 0 0 RDPCS_PHY_TCA_PHY_RESET 1 1 RDPCS_PHY_TCA_APB_RESET_N 2 2 RDPCS_PHY_TEST_POWERDOWN 3 3 RDPCS_PHY_DTB_OUT 4 5 RDPCS_PHY_HDMIMODE_ENABLE 8 8 RDPCS_PHY_REF_RANGE 9 13 RDPCS_PHY_TX_VBOOST_LVL 14 16 RDPCS_PHY_RTUNE_REQ 17 17 RDPCS_PHY_RTUNE_ACK 18 18 RDPCS_PHY_CR_PARA_SEL 20 20 RDPCS_PHY_CR_MUX_SEL 21 21 RDPCS_PHY_REF_CLKDET_EN 24 24 RDPCS_PHY_REF_CLKDET_RESULT 25 25 RDPCS_SRAM_INIT_DONE 28 28 RDPCS_SRAM_EXT_LD_DONE 29 29 RDPCS_SRAM_BYPASS 31 31 mmRDPCSTX0_RDPCSTX_PHY_CNTL1 0 0x2941 8 0 2 RDPCS_PHY_PG_MODE_EN 0 0 RDPCS_PHY_PCS_PWR_EN 1 1 RDPCS_PHY_PCS_PWR_STABLE 2 2 RDPCS_PHY_PMA_PWR_EN 3 3 RDPCS_PHY_PMA_PWR_STABLE 4 4 RDPCS_PHY_DP_PG_RESET 5 5 RDPCS_PHY_ANA_PWR_EN 6 6 RDPCS_PHY_ANA_PWR_STABLE 7 7 mmRDPCSTX0_RDPCSTX_PHY_CNTL2 0 0x2942 12 0 2 RDPCS_PHY_DPALT_DP4 0 0 RDPCS_PHY_DPALT_DISABLE 1 1 RDPCS_PHY_DPALT_DISABLE_ACK 2 2 RDPCS_PHY_DP4_POR 3 3 RDPCS_PHY_DP_LANE0_RX2TX_PAR_LB_EN 4 4 RDPCS_PHY_DP_LANE1_RX2TX_PAR_LB_EN 5 5 RDPCS_PHY_DP_LANE2_RX2TX_PAR_LB_EN 6 6 RDPCS_PHY_DP_LANE3_RX2TX_PAR_LB_EN 7 7 RDPCS_PHY_DP_LANE0_TX2RX_SER_LB_EN 8 8 RDPCS_PHY_DP_LANE1_TX2RX_SER_LB_EN 9 9 RDPCS_PHY_DP_LANE2_TX2RX_SER_LB_EN 10 10 RDPCS_PHY_DP_LANE3_TX2RX_SER_LB_EN 11 11 mmRDPCSTX0_RDPCSTX_PHY_CNTL3 0 0x2943 24 0 2 RDPCS_PHY_DP_TX0_RESET 0 0 RDPCS_PHY_DP_TX0_DISABLE 1 1 RDPCS_PHY_DP_TX0_CLK_RDY 2 2 RDPCS_PHY_DP_TX0_DATA_EN 3 3 RDPCS_PHY_DP_TX0_REQ 4 4 RDPCS_PHY_DP_TX0_ACK 5 5 RDPCS_PHY_DP_TX1_RESET 8 8 RDPCS_PHY_DP_TX1_DISABLE 9 9 RDPCS_PHY_DP_TX1_CLK_RDY 10 10 RDPCS_PHY_DP_TX1_DATA_EN 11 11 RDPCS_PHY_DP_TX1_REQ 12 12 RDPCS_PHY_DP_TX1_ACK 13 13 RDPCS_PHY_DP_TX2_RESET 16 16 RDPCS_PHY_DP_TX2_DISABLE 17 17 RDPCS_PHY_DP_TX2_CLK_RDY 18 18 RDPCS_PHY_DP_TX2_DATA_EN 19 19 RDPCS_PHY_DP_TX2_REQ 20 20 RDPCS_PHY_DP_TX2_ACK 21 21 RDPCS_PHY_DP_TX3_RESET 24 24 RDPCS_PHY_DP_TX3_DISABLE 25 25 RDPCS_PHY_DP_TX3_CLK_RDY 26 26 RDPCS_PHY_DP_TX3_DATA_EN 27 27 RDPCS_PHY_DP_TX3_REQ 28 28 RDPCS_PHY_DP_TX3_ACK 29 29 mmRDPCSTX0_RDPCSTX_PHY_CNTL4 0 0x2944 16 0 2 RDPCS_PHY_DP_TX0_TERM_CTRL 0 2 RDPCS_PHY_DP_TX0_INVERT 4 4 RDPCS_PHY_DP_TX0_BYPASS_EQ_CALC 6 6 RDPCS_PHY_DP_TX0_HP_PROT_EN 7 7 RDPCS_PHY_DP_TX1_TERM_CTRL 8 10 RDPCS_PHY_DP_TX1_INVERT 12 12 RDPCS_PHY_DP_TX1_BYPASS_EQ_CALC 14 14 RDPCS_PHY_DP_TX1_HP_PROT_EN 15 15 RDPCS_PHY_DP_TX2_TERM_CTRL 16 18 RDPCS_PHY_DP_TX2_INVERT 20 20 RDPCS_PHY_DP_TX2_BYPASS_EQ_CALC 22 22 RDPCS_PHY_DP_TX2_HP_PROT_EN 23 23 RDPCS_PHY_DP_TX3_TERM_CTRL 24 26 RDPCS_PHY_DP_TX3_INVERT 28 28 RDPCS_PHY_DP_TX3_BYPASS_EQ_CALC 30 30 RDPCS_PHY_DP_TX3_HP_PROT_EN 31 31 mmRDPCSTX0_RDPCSTX_PHY_CNTL5 0 0x2945 14 0 2 RDPCS_PHY_DP_TX0_PSTATE 2 3 RDPCS_PHY_DP_TX0_LPD 4 4 RDPCS_PHY_DP_TX0_RATE 5 7 RDPCS_PHY_DP_TX0_WIDTH 8 9 RDPCS_PHY_DP_TX0_MPLL_EN 10 10 RDPCS_PHY_DP_TX0_DETRX_REQ 11 11 RDPCS_PHY_DP_TX0_DETRX_RESULT 12 12 RDPCS_PHY_DP_TX1_PSTATE 18 19 RDPCS_PHY_DP_TX1_LPD 20 20 RDPCS_PHY_DP_TX1_RATE 21 23 RDPCS_PHY_DP_TX1_WIDTH 24 25 RDPCS_PHY_DP_TX1_MPLL_EN 26 26 RDPCS_PHY_DP_TX1_DETRX_REQ 27 27 RDPCS_PHY_DP_TX1_DETRX_RESULT 28 28 mmRDPCSTX0_RDPCSTX_PHY_CNTL6 0 0x2946 14 0 2 RDPCS_PHY_DP_TX2_PSTATE 2 3 RDPCS_PHY_DP_TX2_LPD 4 4 RDPCS_PHY_DP_TX2_RATE 5 7 RDPCS_PHY_DP_TX2_WIDTH 8 9 RDPCS_PHY_DP_TX2_MPLL_EN 10 10 RDPCS_PHY_DP_TX2_DETRX_REQ 11 11 RDPCS_PHY_DP_TX2_DETRX_RESULT 12 12 RDPCS_PHY_DP_TX3_PSTATE 18 19 RDPCS_PHY_DP_TX3_LPD 20 20 RDPCS_PHY_DP_TX3_RATE 21 23 RDPCS_PHY_DP_TX3_WIDTH 24 25 RDPCS_PHY_DP_TX3_MPLL_EN 26 26 RDPCS_PHY_DP_TX3_DETRX_REQ 27 27 RDPCS_PHY_DP_TX3_DETRX_RESULT 28 28 mmRDPCSTX0_RDPCSTX_PHY_CNTL7 0 0x2947 2 0 2 RDPCS_PHY_DP_MPLLB_FRACN_DEN 0 15 RDPCS_PHY_DP_MPLLB_FRACN_QUOT 16 31 mmRDPCSTX0_RDPCSTX_PHY_CNTL8 0 0x2948 1 0 2 RDPCS_PHY_DP_MPLLB_SSC_PEAK 0 19 mmRDPCSTX0_RDPCSTX_PHY_CNTL9 0 0x2949 2 0 2 RDPCS_PHY_DP_MPLLB_SSC_STEPSIZE 0 20 RDPCS_PHY_DP_MPLLB_SSC_UP_SPREAD 24 24 mmRDPCSTX0_RDPCSTX_PHY_CNTL10 0 0x294a 1 0 2 RDPCS_PHY_DP_MPLLB_FRACN_REM 0 15 mmRDPCSTX0_RDPCSTX_PHY_CNTL11 0 0x294b 6 0 2 RDPCS_PHY_DP_REF_CLK_EN 0 0 RDPCS_PHY_DP_REF_CLK_REQ 1 1 RDPCS_PHY_DP_MPLLB_MULTIPLIER 4 15 RDPCS_PHY_HDMI_MPLLB_HDMI_DIV 16 18 RDPCS_PHY_DP_REF_CLK_MPLLB_DIV 20 22 RDPCS_PHY_HDMI_MPLLB_HDMI_PIXEL_CLK_DIV 24 25 mmRDPCSTX0_RDPCSTX_PHY_CNTL12 0 0x294c 5 0 2 RDPCS_PHY_DP_MPLLB_DIV5_CLK_EN 0 0 RDPCS_PHY_DP_MPLLB_WORD_DIV2_EN 2 2 RDPCS_PHY_DP_MPLLB_TX_CLK_DIV 4 6 RDPCS_PHY_DP_MPLLB_STATE 7 7 RDPCS_PHY_DP_MPLLB_SSC_EN 8 8 mmRDPCSTX0_RDPCSTX_PHY_CNTL13 0 0x294d 4 0 2 RDPCS_PHY_DP_MPLLB_DIV_MULTIPLIER 20 27 RDPCS_PHY_DP_MPLLB_DIV_CLK_EN 28 28 RDPCS_PHY_DP_MPLLB_FORCE_EN 29 29 RDPCS_PHY_DP_MPLLB_INIT_CAL_DISABLE 30 30 mmRDPCSTX0_RDPCSTX_PHY_CNTL14 0 0x294e 3 0 2 RDPCS_PHY_DP_MPLLB_CAL_FORCE 0 0 RDPCS_PHY_DP_MPLLB_FRACN_EN 24 24 RDPCS_PHY_DP_MPLLB_PMIX_EN 28 28 mmDPCSTX1_DPCSTX_TX_CLOCK_CNTL 0 0x2a00 4 0 2 DPCS_SYMCLK_GATE_DIS 0 0 DPCS_SYMCLK_EN 1 1 DPCS_SYMCLK_CLOCK_ON 2 2 DPCS_SYMCLK_DIV2_CLOCK_ON 3 3 mmDPCSTX1_DPCSTX_TX_CNTL 0 0x2a01 8 0 2 DPCS_TX_PLL_UPDATE_REQ 12 12 DPCS_TX_PLL_UPDATE_PENDING 13 13 DPCS_TX_DATA_SWAP 14 14 DPCS_TX_DATA_ORDER_INVERT 15 15 DPCS_TX_FIFO_EN 16 16 DPCS_TX_FIFO_START 17 17 DPCS_TX_FIFO_RD_START_DELAY 20 23 DPCS_TX_SOFT_RESET 31 31 mmDPCSTX1_DPCSTX_CBUS_CNTL 0 0x2a02 2 0 2 DPCS_CBUS_WR_CMD_DELAY 0 7 DPCS_CBUS_SOFT_RESET 31 31 mmDPCSTX1_DPCSTX_INTERRUPT_CNTL 0 0x2a03 10 0 2 DPCS_REG_FIFO_OVERFLOW 0 0 DPCS_REG_ERROR_CLR 1 1 DPCS_REG_FIFO_ERROR_MASK 4 4 DPCS_TX0_FIFO_ERROR 8 8 DPCS_TX1_FIFO_ERROR 9 9 DPCS_TX2_FIFO_ERROR 10 10 DPCS_TX3_FIFO_ERROR 11 11 DPCS_TX_ERROR_CLR 12 12 DPCS_TX_FIFO_ERROR_MASK 16 16 DPCS_INTERRUPT_MASK 20 20 mmDPCSTX1_DPCSTX_PLL_UPDATE_ADDR 0 0x2a04 1 0 2 DPCS_PLL_UPDATE_ADDR 0 17 mmDPCSTX1_DPCSTX_PLL_UPDATE_DATA 0 0x2a05 1 0 2 DPCS_PLL_UPDATE_DATA 0 31 mmRDPCSTX1_RDPCSTX_CNTL 0 0x2a08 10 0 2 RDPCS_CBUS_SOFT_RESET 0 0 RDPCS_SRAM_SOFT_RESET 4 4 RDPCS_TX_FIFO_LANE0_EN 12 12 RDPCS_TX_FIFO_LANE1_EN 13 13 RDPCS_TX_FIFO_LANE2_EN 14 14 RDPCS_TX_FIFO_LANE3_EN 15 15 RDPCS_TX_FIFO_EN 16 16 RDPCS_TX_FIFO_START 17 17 RDPCS_TX_FIFO_RD_START_DELAY 20 23 RDPCS_TX_SOFT_RESET 31 31 mmRDPCSTX1_RDPCSTX_CLOCK_CNTL 0 0x2a09 12 0 2 RDPCS_EXT_REFCLK_EN 0 0 RDPCS_SYMCLK_DIV2_TX0_EN 4 4 RDPCS_SYMCLK_DIV2_TX1_EN 5 5 RDPCS_SYMCLK_DIV2_TX2_EN 6 6 RDPCS_SYMCLK_DIV2_TX3_EN 7 7 RDPCS_SYMCLK_DIV2_GATE_DIS 8 8 RDPCS_SYMCLK_DIV2_EN 9 9 RDPCS_SYMCLK_DIV2_CLOCK_ON 10 10 RDPCS_SRAMCLK_GATE_DIS 12 12 RDPCS_SRAMCLK_EN 13 13 RDPCS_SRAMCLK_CLOCK_ON 14 14 RDPCS_SRAMCLK_BYPASS 16 16 mmRDPCSTX1_RDPCSTX_INTERRUPT_CONTROL 0 0x2a0a 15 0 2 RDPCS_REG_FIFO_OVERFLOW 0 0 RDPCS_DPALT_DISABLE_TOGGLE 1 1 RDPCS_DPALT_4LANE_TOGGLE 2 2 RDPCS_TX0_FIFO_ERROR 4 4 RDPCS_TX1_FIFO_ERROR 5 5 RDPCS_TX2_FIFO_ERROR 6 6 RDPCS_TX3_FIFO_ERROR 7 7 RDPCS_REG_ERROR_CLR 8 8 RDPCS_DPALT_DISABLE_TOGGLE_CLR 9 9 RDPCS_DPALT_4LANE_TOGGLE_CLR 10 10 RDPCS_TX_ERROR_CLR 12 12 RDPCS_REG_FIFO_ERROR_MASK 16 16 RDPCS_DPALT_DISABLE_TOGGLE_MASK 17 17 RDPCS_DPALT_4LANE_TOGGLE_MASK 18 18 RDPCS_TX_FIFO_ERROR_MASK 20 20 mmRDPCSTX1_RDPCSTX_PLL_UPDATE_DATA 0 0x2a0b 1 0 2 RDPCS_PLL_UPDATE_DATA 0 0 mmRDPCSTX1_RDPCS_TX_CR_ADDR 0 0x2a0c 1 0 2 RDPCS_TX_CR_ADDR 0 15 mmRDPCSTX1_RDPCS_TX_CR_DATA 0 0x2a0d 1 0 2 RDPCS_TX_CR_DATA 0 15 mmRDPCSTX1_RDPCSTX_SCRATCH 0 0x2a11 1 0 2 RDPCSTX_SCRATCH 0 31 mmRDPCSTX1_RDPCSTX_PHY_CNTL0 0 0x2a18 17 0 2 RDPCS_PHY_RESET 0 0 RDPCS_PHY_TCA_PHY_RESET 1 1 RDPCS_PHY_TCA_APB_RESET_N 2 2 RDPCS_PHY_TEST_POWERDOWN 3 3 RDPCS_PHY_DTB_OUT 4 5 RDPCS_PHY_HDMIMODE_ENABLE 8 8 RDPCS_PHY_REF_RANGE 9 13 RDPCS_PHY_TX_VBOOST_LVL 14 16 RDPCS_PHY_RTUNE_REQ 17 17 RDPCS_PHY_RTUNE_ACK 18 18 RDPCS_PHY_CR_PARA_SEL 20 20 RDPCS_PHY_CR_MUX_SEL 21 21 RDPCS_PHY_REF_CLKDET_EN 24 24 RDPCS_PHY_REF_CLKDET_RESULT 25 25 RDPCS_SRAM_INIT_DONE 28 28 RDPCS_SRAM_EXT_LD_DONE 29 29 RDPCS_SRAM_BYPASS 31 31 mmRDPCSTX1_RDPCSTX_PHY_CNTL1 0 0x2a19 8 0 2 RDPCS_PHY_PG_MODE_EN 0 0 RDPCS_PHY_PCS_PWR_EN 1 1 RDPCS_PHY_PCS_PWR_STABLE 2 2 RDPCS_PHY_PMA_PWR_EN 3 3 RDPCS_PHY_PMA_PWR_STABLE 4 4 RDPCS_PHY_DP_PG_RESET 5 5 RDPCS_PHY_ANA_PWR_EN 6 6 RDPCS_PHY_ANA_PWR_STABLE 7 7 mmRDPCSTX1_RDPCSTX_PHY_CNTL2 0 0x2a1a 12 0 2 RDPCS_PHY_DPALT_DP4 0 0 RDPCS_PHY_DPALT_DISABLE 1 1 RDPCS_PHY_DPALT_DISABLE_ACK 2 2 RDPCS_PHY_DP4_POR 3 3 RDPCS_PHY_DP_LANE0_RX2TX_PAR_LB_EN 4 4 RDPCS_PHY_DP_LANE1_RX2TX_PAR_LB_EN 5 5 RDPCS_PHY_DP_LANE2_RX2TX_PAR_LB_EN 6 6 RDPCS_PHY_DP_LANE3_RX2TX_PAR_LB_EN 7 7 RDPCS_PHY_DP_LANE0_TX2RX_SER_LB_EN 8 8 RDPCS_PHY_DP_LANE1_TX2RX_SER_LB_EN 9 9 RDPCS_PHY_DP_LANE2_TX2RX_SER_LB_EN 10 10 RDPCS_PHY_DP_LANE3_TX2RX_SER_LB_EN 11 11 mmRDPCSTX1_RDPCSTX_PHY_CNTL3 0 0x2a1b 24 0 2 RDPCS_PHY_DP_TX0_RESET 0 0 RDPCS_PHY_DP_TX0_DISABLE 1 1 RDPCS_PHY_DP_TX0_CLK_RDY 2 2 RDPCS_PHY_DP_TX0_DATA_EN 3 3 RDPCS_PHY_DP_TX0_REQ 4 4 RDPCS_PHY_DP_TX0_ACK 5 5 RDPCS_PHY_DP_TX1_RESET 8 8 RDPCS_PHY_DP_TX1_DISABLE 9 9 RDPCS_PHY_DP_TX1_CLK_RDY 10 10 RDPCS_PHY_DP_TX1_DATA_EN 11 11 RDPCS_PHY_DP_TX1_REQ 12 12 RDPCS_PHY_DP_TX1_ACK 13 13 RDPCS_PHY_DP_TX2_RESET 16 16 RDPCS_PHY_DP_TX2_DISABLE 17 17 RDPCS_PHY_DP_TX2_CLK_RDY 18 18 RDPCS_PHY_DP_TX2_DATA_EN 19 19 RDPCS_PHY_DP_TX2_REQ 20 20 RDPCS_PHY_DP_TX2_ACK 21 21 RDPCS_PHY_DP_TX3_RESET 24 24 RDPCS_PHY_DP_TX3_DISABLE 25 25 RDPCS_PHY_DP_TX3_CLK_RDY 26 26 RDPCS_PHY_DP_TX3_DATA_EN 27 27 RDPCS_PHY_DP_TX3_REQ 28 28 RDPCS_PHY_DP_TX3_ACK 29 29 mmRDPCSTX1_RDPCSTX_PHY_CNTL4 0 0x2a1c 16 0 2 RDPCS_PHY_DP_TX0_TERM_CTRL 0 2 RDPCS_PHY_DP_TX0_INVERT 4 4 RDPCS_PHY_DP_TX0_BYPASS_EQ_CALC 6 6 RDPCS_PHY_DP_TX0_HP_PROT_EN 7 7 RDPCS_PHY_DP_TX1_TERM_CTRL 8 10 RDPCS_PHY_DP_TX1_INVERT 12 12 RDPCS_PHY_DP_TX1_BYPASS_EQ_CALC 14 14 RDPCS_PHY_DP_TX1_HP_PROT_EN 15 15 RDPCS_PHY_DP_TX2_TERM_CTRL 16 18 RDPCS_PHY_DP_TX2_INVERT 20 20 RDPCS_PHY_DP_TX2_BYPASS_EQ_CALC 22 22 RDPCS_PHY_DP_TX2_HP_PROT_EN 23 23 RDPCS_PHY_DP_TX3_TERM_CTRL 24 26 RDPCS_PHY_DP_TX3_INVERT 28 28 RDPCS_PHY_DP_TX3_BYPASS_EQ_CALC 30 30 RDPCS_PHY_DP_TX3_HP_PROT_EN 31 31 mmRDPCSTX1_RDPCSTX_PHY_CNTL5 0 0x2a1d 14 0 2 RDPCS_PHY_DP_TX0_PSTATE 2 3 RDPCS_PHY_DP_TX0_LPD 4 4 RDPCS_PHY_DP_TX0_RATE 5 7 RDPCS_PHY_DP_TX0_WIDTH 8 9 RDPCS_PHY_DP_TX0_MPLL_EN 10 10 RDPCS_PHY_DP_TX0_DETRX_REQ 11 11 RDPCS_PHY_DP_TX0_DETRX_RESULT 12 12 RDPCS_PHY_DP_TX1_PSTATE 18 19 RDPCS_PHY_DP_TX1_LPD 20 20 RDPCS_PHY_DP_TX1_RATE 21 23 RDPCS_PHY_DP_TX1_WIDTH 24 25 RDPCS_PHY_DP_TX1_MPLL_EN 26 26 RDPCS_PHY_DP_TX1_DETRX_REQ 27 27 RDPCS_PHY_DP_TX1_DETRX_RESULT 28 28 mmRDPCSTX1_RDPCSTX_PHY_CNTL6 0 0x2a1e 14 0 2 RDPCS_PHY_DP_TX2_PSTATE 2 3 RDPCS_PHY_DP_TX2_LPD 4 4 RDPCS_PHY_DP_TX2_RATE 5 7 RDPCS_PHY_DP_TX2_WIDTH 8 9 RDPCS_PHY_DP_TX2_MPLL_EN 10 10 RDPCS_PHY_DP_TX2_DETRX_REQ 11 11 RDPCS_PHY_DP_TX2_DETRX_RESULT 12 12 RDPCS_PHY_DP_TX3_PSTATE 18 19 RDPCS_PHY_DP_TX3_LPD 20 20 RDPCS_PHY_DP_TX3_RATE 21 23 RDPCS_PHY_DP_TX3_WIDTH 24 25 RDPCS_PHY_DP_TX3_MPLL_EN 26 26 RDPCS_PHY_DP_TX3_DETRX_REQ 27 27 RDPCS_PHY_DP_TX3_DETRX_RESULT 28 28 mmRDPCSTX1_RDPCSTX_PHY_CNTL7 0 0x2a1f 2 0 2 RDPCS_PHY_DP_MPLLB_FRACN_DEN 0 15 RDPCS_PHY_DP_MPLLB_FRACN_QUOT 16 31 mmRDPCSTX1_RDPCSTX_PHY_CNTL8 0 0x2a20 1 0 2 RDPCS_PHY_DP_MPLLB_SSC_PEAK 0 19 mmRDPCSTX1_RDPCSTX_PHY_CNTL9 0 0x2a21 2 0 2 RDPCS_PHY_DP_MPLLB_SSC_STEPSIZE 0 20 RDPCS_PHY_DP_MPLLB_SSC_UP_SPREAD 24 24 mmRDPCSTX1_RDPCSTX_PHY_CNTL10 0 0x2a22 1 0 2 RDPCS_PHY_DP_MPLLB_FRACN_REM 0 15 mmRDPCSTX1_RDPCSTX_PHY_CNTL11 0 0x2a23 6 0 2 RDPCS_PHY_DP_REF_CLK_EN 0 0 RDPCS_PHY_DP_REF_CLK_REQ 1 1 RDPCS_PHY_DP_MPLLB_MULTIPLIER 4 15 RDPCS_PHY_HDMI_MPLLB_HDMI_DIV 16 18 RDPCS_PHY_DP_REF_CLK_MPLLB_DIV 20 22 RDPCS_PHY_HDMI_MPLLB_HDMI_PIXEL_CLK_DIV 24 25 mmRDPCSTX1_RDPCSTX_PHY_CNTL12 0 0x2a24 5 0 2 RDPCS_PHY_DP_MPLLB_DIV5_CLK_EN 0 0 RDPCS_PHY_DP_MPLLB_WORD_DIV2_EN 2 2 RDPCS_PHY_DP_MPLLB_TX_CLK_DIV 4 6 RDPCS_PHY_DP_MPLLB_STATE 7 7 RDPCS_PHY_DP_MPLLB_SSC_EN 8 8 mmRDPCSTX1_RDPCSTX_PHY_CNTL13 0 0x2a25 4 0 2 RDPCS_PHY_DP_MPLLB_DIV_MULTIPLIER 20 27 RDPCS_PHY_DP_MPLLB_DIV_CLK_EN 28 28 RDPCS_PHY_DP_MPLLB_FORCE_EN 29 29 RDPCS_PHY_DP_MPLLB_INIT_CAL_DISABLE 30 30 mmRDPCSTX1_RDPCSTX_PHY_CNTL14 0 0x2a26 3 0 2 RDPCS_PHY_DP_MPLLB_CAL_FORCE 0 0 RDPCS_PHY_DP_MPLLB_FRACN_EN 24 24 RDPCS_PHY_DP_MPLLB_PMIX_EN 28 28