11279 regDPCSSYS_CR0_DPCSSYS_CR_ADDR 0 0x2934 1 0 2 RDPCS_TX_CR_ADDR 0 15 regDPCSSYS_CR0_DPCSSYS_CR_DATA 0 0x2935 1 0 2 RDPCS_TX_CR_DATA 0 15 regDPCSSYS_CR1_DPCSSYS_CR_ADDR 0 0x2a0c 1 0 2 RDPCS_TX_CR_ADDR 0 15 regDPCSSYS_CR1_DPCSSYS_CR_DATA 0 0x2a0d 1 0 2 RDPCS_TX_CR_DATA 0 15 regDPCSSYS_CR2_DPCSSYS_CR_ADDR 0 0x2ae4 1 0 2 RDPCS_TX_CR_ADDR 0 15 regDPCSSYS_CR2_DPCSSYS_CR_DATA 0 0x2ae5 1 0 2 RDPCS_TX_CR_DATA 0 15 regDPCSSYS_CR3_DPCSSYS_CR_ADDR 0 0x2bbc 1 0 2 RDPCS_TX_CR_ADDR 0 15 regDPCSSYS_CR3_DPCSSYS_CR_DATA 0 0x2bbd 1 0 2 RDPCS_TX_CR_DATA 0 15 regDPCSSYS_CR4_DPCSSYS_CR_ADDR 0 0x2c94 1 0 2 RDPCS_TX_CR_ADDR 0 15 regDPCSSYS_CR4_DPCSSYS_CR_DATA 0 0x2c95 1 0 2 RDPCS_TX_CR_DATA 0 15 regPWRSEQ0_DC_GPIO_PWRSEQ_EN 0 0x2f10 3 0 2 DC_GPIO_VARY_BL_EN 0 0 DC_GPIO_DIGON_EN 8 8 DC_GPIO_BLON_EN 16 16 regPWRSEQ0_DC_GPIO_PWRSEQ_CTRL 0 0x2f11 11 0 2 DC_GPIO_VARY_BL_TX12_EN 0 0 DC_GPIO_DIGON_TX12_EN 1 1 DC_GPIO_BLON_TX12_EN 2 2 DC_GPIO_VARY_BL_RXEN 3 3 DC_GPIO_DIGON_RXEN 4 4 DC_GPIO_BLON_RXEN 5 5 DC_GPIO_VARY_BL_PU_EN 6 6 DC_GPIO_DIGON_PU_EN 7 7 DC_GPIO_BLON_PU_EN 8 8 PWRSEQ_STRENGTH_SN 16 19 PWRSEQ_STRENGTH_SP 20 23 regPWRSEQ0_DC_GPIO_PWRSEQ_MASK 0 0x2f12 9 0 2 DC_GPIO_VARY_BL_MASK 0 0 DC_GPIO_VARY_BL_PD_DIS 4 4 DC_GPIO_VARY_BL_RECV 6 7 DC_GPIO_DIGON_MASK 8 8 DC_GPIO_DIGON_PD_DIS 12 12 DC_GPIO_DIGON_RECV 14 15 DC_GPIO_BLON_MASK 16 16 DC_GPIO_BLON_PD_DIS 20 20 DC_GPIO_BLON_RECV 22 23 regPWRSEQ0_DC_GPIO_PWRSEQ_A_Y 0 0x2f13 6 0 2 DC_GPIO_VARY_BL_A 0 0 DC_GPIO_VARY_BL_Y 1 1 DC_GPIO_DIGON_A 8 8 DC_GPIO_DIGON_Y 9 9 DC_GPIO_BLON_A 16 16 DC_GPIO_BLON_Y 17 17 regPWRSEQ0_PANEL_PWRSEQ_CNTL 0 0x2f14 11 0 2 PANEL_PWRSEQ_EN 0 0 PANEL_PWRSEQ_TARGET_STATE 4 4 PANEL_SYNCEN 8 8 PANEL_SYNCEN_OVRD 9 9 PANEL_SYNCEN_POL 10 10 PANEL_DIGON 16 16 PANEL_DIGON_OVRD 17 17 PANEL_DIGON_POL 18 18 PANEL_BLON 24 24 PANEL_BLON_OVRD 25 25 PANEL_BLON_POL 26 26 regPWRSEQ0_PANEL_PWRSEQ_STATE 0 0x2f15 6 0 2 PANEL_PWRSEQ_TARGET_STATE_R 0 0 PANEL_PWRSEQ_DIGON 1 1 PANEL_PWRSEQ_SYNCEN 2 2 PANEL_PWRSEQ_BLON 3 3 PANEL_PWRSEQ_DONE 4 4 PANEL_PWRSEQ_STATE 8 11 regPWRSEQ0_PANEL_PWRSEQ_DELAY1 0 0x2f16 4 0 2 PANEL_PWRUP_DELAY1 0 7 PANEL_PWRUP_DELAY2 8 15 PANEL_PWRDN_DELAY1 16 23 PANEL_PWRDN_DELAY2 24 31 regPWRSEQ0_PANEL_PWRSEQ_DELAY2 0 0x2f17 4 0 2 PANEL_PWRDN_MIN_LENGTH 0 7 PANEL_PWRUP_DELAY3 8 15 PANEL_PWRDN_DELAY3 16 23 PANEL_VARY_BL_OVERRIDE_EN 24 24 regPWRSEQ0_PANEL_PWRSEQ_REF_DIV1 0 0x2f18 2 0 2 PANEL_PWRSEQ_REF_DIV 0 11 BL_PWM_REF_DIV 16 31 regPWRSEQ0_BL_PWM_CNTL 0 0x2f19 6 0 2 BL_ACTIVE_INT_FRAC_CNT 0 15 BL_PWM_EN_EQ_ZERO 19 19 FRAME_START_EVENT_RECOGNIZED 20 20 RECOGNIZE_POST_FRAME_START_DELAY_BEFORE_UPDATE 21 21 BL_PWM_FRACTIONAL_EN 30 30 BL_PWM_EN 31 31 regPWRSEQ0_BL_PWM_CNTL2 0 0x2f1a 4 0 2 BL_PWM_POST_FRAME_START_DELAY_BEFORE_UPDATE 0 15 DBG_BL_PWM_INPUT_REFCLK_SELECT 28 29 BL_PWM_OVERRIDE_BL_OUT_ENABLE 30 30 BL_PWM_OVERRIDE_PANEL_PWRSEQ_EN 31 31 regPWRSEQ0_BL_PWM_PERIOD_CNTL 0 0x2f1b 2 0 2 BL_PWM_PERIOD 0 15 BL_PWM_PERIOD_BITCNT 16 19 regPWRSEQ0_BL_PWM_GRP1_REG_LOCK 0 0x2f1c 5 0 2 BL_PWM_GRP1_REG_LOCK 0 0 BL_PWM_GRP1_REG_UPDATE_PENDING 8 8 BL_PWM_GRP1_UPDATE_AT_FRAME_START 16 16 BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN 24 24 BL_PWM_GRP1_IGNORE_MASTER_LOCK_EN 31 31 regPWRSEQ0_PANEL_PWRSEQ_REF_DIV2 0 0x2f1d 3 0 2 XTAL_REF_DIV 0 6 MICROSECOND_TIME_BASE_DIV 8 14 XTAL_REF_START_ON_VARY_BL_ACTIVE 16 16 regPWRSEQ0_PWRSEQ_SPARE 0 0x2f21 1 0 2 PWRSEQ_SPARE 0 31 regPWRSEQ1_DC_GPIO_PWRSEQ_EN 0 0x2f7c 3 0 2 DC_GPIO_VARY_BL_EN 0 0 DC_GPIO_DIGON_EN 8 8 DC_GPIO_BLON_EN 16 16 regPWRSEQ1_DC_GPIO_PWRSEQ_CTRL 0 0x2f7d 11 0 2 DC_GPIO_VARY_BL_TX12_EN 0 0 DC_GPIO_DIGON_TX12_EN 1 1 DC_GPIO_BLON_TX12_EN 2 2 DC_GPIO_VARY_BL_RXEN 3 3 DC_GPIO_DIGON_RXEN 4 4 DC_GPIO_BLON_RXEN 5 5 DC_GPIO_VARY_BL_PU_EN 6 6 DC_GPIO_DIGON_PU_EN 7 7 DC_GPIO_BLON_PU_EN 8 8 PWRSEQ_STRENGTH_SN 16 19 PWRSEQ_STRENGTH_SP 20 23 regPWRSEQ1_DC_GPIO_PWRSEQ_MASK 0 0x2f7e 9 0 2 DC_GPIO_VARY_BL_MASK 0 0 DC_GPIO_VARY_BL_PD_DIS 4 4 DC_GPIO_VARY_BL_RECV 6 7 DC_GPIO_DIGON_MASK 8 8 DC_GPIO_DIGON_PD_DIS 12 12 DC_GPIO_DIGON_RECV 14 15 DC_GPIO_BLON_MASK 16 16 DC_GPIO_BLON_PD_DIS 20 20 DC_GPIO_BLON_RECV 22 23 regPWRSEQ1_DC_GPIO_PWRSEQ_A_Y 0 0x2f7f 6 0 2 DC_GPIO_VARY_BL_A 0 0 DC_GPIO_VARY_BL_Y 1 1 DC_GPIO_DIGON_A 8 8 DC_GPIO_DIGON_Y 9 9 DC_GPIO_BLON_A 16 16 DC_GPIO_BLON_Y 17 17 regPWRSEQ1_PANEL_PWRSEQ_CNTL 0 0x2f80 11 0 2 PANEL_PWRSEQ_EN 0 0 PANEL_PWRSEQ_TARGET_STATE 4 4 PANEL_SYNCEN 8 8 PANEL_SYNCEN_OVRD 9 9 PANEL_SYNCEN_POL 10 10 PANEL_DIGON 16 16 PANEL_DIGON_OVRD 17 17 PANEL_DIGON_POL 18 18 PANEL_BLON 24 24 PANEL_BLON_OVRD 25 25 PANEL_BLON_POL 26 26 regPWRSEQ1_PANEL_PWRSEQ_STATE 0 0x2f81 6 0 2 PANEL_PWRSEQ_TARGET_STATE_R 0 0 PANEL_PWRSEQ_DIGON 1 1 PANEL_PWRSEQ_SYNCEN 2 2 PANEL_PWRSEQ_BLON 3 3 PANEL_PWRSEQ_DONE 4 4 PANEL_PWRSEQ_STATE 8 11 regPWRSEQ1_PANEL_PWRSEQ_DELAY1 0 0x2f82 4 0 2 PANEL_PWRUP_DELAY1 0 7 PANEL_PWRUP_DELAY2 8 15 PANEL_PWRDN_DELAY1 16 23 PANEL_PWRDN_DELAY2 24 31 regPWRSEQ1_PANEL_PWRSEQ_DELAY2 0 0x2f83 4 0 2 PANEL_PWRDN_MIN_LENGTH 0 7 PANEL_PWRUP_DELAY3 8 15 PANEL_PWRDN_DELAY3 16 23 PANEL_VARY_BL_OVERRIDE_EN 24 24 regPWRSEQ1_PANEL_PWRSEQ_REF_DIV1 0 0x2f84 2 0 2 PANEL_PWRSEQ_REF_DIV 0 11 BL_PWM_REF_DIV 16 31 regPWRSEQ1_BL_PWM_CNTL 0 0x2f85 6 0 2 BL_ACTIVE_INT_FRAC_CNT 0 15 BL_PWM_EN_EQ_ZERO 19 19 FRAME_START_EVENT_RECOGNIZED 20 20 RECOGNIZE_POST_FRAME_START_DELAY_BEFORE_UPDATE 21 21 BL_PWM_FRACTIONAL_EN 30 30 BL_PWM_EN 31 31 regPWRSEQ1_BL_PWM_CNTL2 0 0x2f86 4 0 2 BL_PWM_POST_FRAME_START_DELAY_BEFORE_UPDATE 0 15 DBG_BL_PWM_INPUT_REFCLK_SELECT 28 29 BL_PWM_OVERRIDE_BL_OUT_ENABLE 30 30 BL_PWM_OVERRIDE_PANEL_PWRSEQ_EN 31 31 regPWRSEQ1_BL_PWM_PERIOD_CNTL 0 0x2f87 2 0 2 BL_PWM_PERIOD 0 15 BL_PWM_PERIOD_BITCNT 16 19 regPWRSEQ1_BL_PWM_GRP1_REG_LOCK 0 0x2f88 5 0 2 BL_PWM_GRP1_REG_LOCK 0 0 BL_PWM_GRP1_REG_UPDATE_PENDING 8 8 BL_PWM_GRP1_UPDATE_AT_FRAME_START 16 16 BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN 24 24 BL_PWM_GRP1_IGNORE_MASTER_LOCK_EN 31 31 regPWRSEQ1_PANEL_PWRSEQ_REF_DIV2 0 0x2f89 3 0 2 XTAL_REF_DIV 0 6 MICROSECOND_TIME_BASE_DIV 8 14 XTAL_REF_START_ON_VARY_BL_ACTIVE 16 16 regPWRSEQ1_PWRSEQ_SPARE 0 0x2f8d 1 0 2 PWRSEQ_SPARE 0 31 regRDPCSTX0_RDPCSTX_CNTL 0 0x2930 24 0 2 RDPCS_CBUS_SOFT_RESET 0 0 RDPCS_SRAM_SOFT_RESET 1 1 TX_LANE0_BIT_ORDER_REVERSE_BEFORE_PACK 4 4 TX_LANE1_BIT_ORDER_REVERSE_BEFORE_PACK 5 5 TX_LANE2_BIT_ORDER_REVERSE_BEFORE_PACK 6 6 TX_LANE3_BIT_ORDER_REVERSE_BEFORE_PACK 7 7 RDPCS_INTERRUPT_MASK 8 8 RDPCS_TX_PLL_UPDATE_REQ 9 9 RDPCS_TX_PLL_UPDATE_PENDING 10 10 RDPCS_TX_FIFO_LANE0_EN 12 12 RDPCS_TX_FIFO_LANE1_EN 13 13 RDPCS_TX_FIFO_LANE2_EN 14 14 RDPCS_TX_FIFO_LANE3_EN 15 15 TX_LANE0_PACK_FROM_MSB 16 16 TX_LANE1_PACK_FROM_MSB 17 17 TX_LANE2_PACK_FROM_MSB 18 18 TX_LANE3_PACK_FROM_MSB 19 19 RDPCS_TX_FIFO_RD_START_DELAY 20 24 RDPCS_TX_FIFO_EN 25 25 RDPCS_TX_FIFO_START 26 26 RDPCS_CR_REGISTER_BLOCK_EN 28 28 RDPCS_NON_DPALT_REGISTER_BLOCK_EN 29 29 RDPCS_DPALT_BLOCK_STATUS 30 30 RDPCS_TX_SOFT_RESET 31 31 regRDPCSTX0_RDPCSTX_CLOCK_CNTL 0 0x2931 16 0 2 RDPCS_EXT_REFCLK_EN 0 0 RDPCS_TX0_CLK_EN 4 4 RDPCS_TX1_CLK_EN 5 5 RDPCS_TX2_CLK_EN 6 6 RDPCS_TX3_CLK_EN 7 7 RDPCS_TX_CLK_GATE_DIS 8 8 RDPCS_TX_CLK_EN 9 9 RDPCS_TX_CLK_CLOCK_ON 10 10 RDPCS_TX_PHY_REF_ALT_CLK_EN 11 11 RDPCS_SRAMCLK_GATE_DIS 12 12 RDPCS_SRAMCLK_EN 13 13 RDPCS_SRAMCLK_CLOCK_ON 14 14 RDPCS_SRAMCLK_BYPASS 16 16 RDPCS_OCLACLK_GATE_DIS 20 20 RDPCS_OCLACLK_EN 21 21 RDPCS_OCLACLK_CLOCK_ON 22 22 regRDPCSTX0_RDPCSTX_INTERRUPT_CONTROL 0 0x2932 15 0 2 RDPCS_REG_FIFO_OVERFLOW 0 0 RDPCS_DPALT_DISABLE_TOGGLE 1 1 RDPCS_DPALT_4LANE_TOGGLE 2 2 RDPCS_TX0_FIFO_ERROR 4 4 RDPCS_TX1_FIFO_ERROR 5 5 RDPCS_TX2_FIFO_ERROR 6 6 RDPCS_TX3_FIFO_ERROR 7 7 RDPCS_REG_ERROR_CLR 8 8 RDPCS_DPALT_DISABLE_TOGGLE_CLR 9 9 RDPCS_DPALT_4LANE_TOGGLE_CLR 10 10 RDPCS_TX_ERROR_CLR 12 12 RDPCS_REG_FIFO_ERROR_MASK 16 16 RDPCS_DPALT_DISABLE_TOGGLE_MASK 17 17 RDPCS_DPALT_4LANE_TOGGLE_MASK 18 18 RDPCS_TX_FIFO_ERROR_MASK 20 20 regRDPCSTX0_RDPCS_TX_PLL_UPDATE_DATA 0 0x2933 1 0 2 RDPCS_PLL_UPDATE_DATA 0 0 regRDPCSTX0_RDPCS_TX_CR_ADDR 0 0x2934 1 0 2 RDPCS_TX_CR_ADDR 0 15 regRDPCSTX0_RDPCS_TX_CR_DATA 0 0x2935 1 0 2 RDPCS_TX_CR_DATA 0 15 regRDPCSTX0_RDPCS_TX_SRAM_CNTL 0 0x2936 3 0 2 RDPCS_MEM_PWR_DIS 20 20 RDPCS_MEM_PWR_FORCE 24 25 RDPCS_MEM_PWR_PWR_STATE 28 29 regRDPCSTX0_RDPCSTX_SCRATCH 0 0x2937 1 0 2 RDPCSTX_SCRATCH 0 31 regRDPCSTX0_RDPCSTX_SPARE 0 0x2938 1 0 2 RDPCSTX_SPARE 0 31 regRDPCSTX0_RDPCSTX_CNTL2 0 0x2939 3 0 2 RDPCS_CR_CONVERT_FIFO_EMPTY 0 0 RDPCS_CR_CONVERT_FIFO_FULL 1 1 RDPCS_PHY_ENC_TYPE_SEL 2 3 regRDPCSTX0_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG 0 0x293c 3 0 2 RDPCS_DMCU_DPALT_DIS_BLOCK_REG 0 0 RDPCS_DMCU_DPALT_FORCE_TX_CLK_DIS 4 4 RDPCS_DMCU_DPALT_CONTROL_SPARE 8 15 regRDPCSTX0_RDPCSTX_DEBUG_CONFIG 0 0x293d 7 0 2 RDPCS_DBG_EN 0 0 RDPCS_DBG_SEL_ASYNC_8BIT 4 6 RDPCS_DBG_SEL_ASYNC_SWAP 7 7 RDPCS_DBG_SEL_TEST_CLK 8 12 RDPCS_DBG_CR_COUNT_EXPIRE 15 15 RDPCS_DBG_CR_COUNT_MAX 16 23 RDPCS_DBG_CR_COUNT 24 31 regRDPCSTX0_RDPCSTX_PHY_CNTL0 0 0x2940 16 0 2 RDPCS_PHY_RESET 0 0 RDPCS_PHY_TCA_PHY_RESET 1 1 RDPCS_PHY_TCA_APB_RESET_N 2 2 RDPCS_PHY_TEST_POWERDOWN 3 3 RDPCS_PHY_DTB_OUT 4 5 RDPCS_PHY_HDMIMODE_ENABLE 8 8 RDPCS_PHY_REF_RANGE 9 13 RDPCS_PHY_RTUNE_REQ 17 17 RDPCS_PHY_RTUNE_ACK 18 18 RDPCS_PHY_CR_PARA_SEL 20 20 RDPCS_PHY_CR_MUX_SEL 21 21 RDPCS_PHY_REF_CLKDET_EN 24 24 RDPCS_PHY_REF_CLKDET_RESULT 25 25 RDPCS_SRAM_INIT_DONE 28 28 RDPCS_SRAM_EXT_LD_DONE 29 29 RDPCS_SRAM_BYPASS 31 31 regRDPCSTX0_RDPCSTX_PHY_CNTL1 0 0x2941 8 0 2 RDPCS_PHY_PG_MODE_EN 0 0 RDPCS_PHY_PCS_PWR_EN 1 1 RDPCS_PHY_PCS_PWR_STABLE 2 2 RDPCS_PHY_PMA_PWR_EN 3 3 RDPCS_PHY_PMA_PWR_STABLE 4 4 RDPCS_PHY_DP_PG_RESET 5 5 RDPCS_PHY_ANA_PWR_EN 6 6 RDPCS_PHY_ANA_PWR_STABLE 7 7 regRDPCSTX0_RDPCSTX_PHY_CNTL2 0 0x2942 9 0 2 RDPCS_PHY_DP4_POR 3 3 RDPCS_PHY_DP_LANE0_RX2TX_PAR_LB_EN 4 4 RDPCS_PHY_DP_LANE1_RX2TX_PAR_LB_EN 5 5 RDPCS_PHY_DP_LANE2_RX2TX_PAR_LB_EN 6 6 RDPCS_PHY_DP_LANE3_RX2TX_PAR_LB_EN 7 7 RDPCS_PHY_DP_LANE0_TX2RX_SER_LB_EN 8 8 RDPCS_PHY_DP_LANE1_TX2RX_SER_LB_EN 9 9 RDPCS_PHY_DP_LANE2_TX2RX_SER_LB_EN 10 10 RDPCS_PHY_DP_LANE3_TX2RX_SER_LB_EN 11 11 regRDPCSTX0_RDPCSTX_PHY_CNTL3 0 0x2943 24 0 2 RDPCS_PHY_DP_TX0_RESET 0 0 RDPCS_PHY_DP_TX0_DISABLE 1 1 RDPCS_PHY_DP_TX0_CLK_RDY 2 2 RDPCS_PHY_DP_TX0_DATA_EN 3 3 RDPCS_PHY_DP_TX0_REQ 4 4 RDPCS_PHY_DP_TX0_ACK 5 5 RDPCS_PHY_DP_TX1_RESET 8 8 RDPCS_PHY_DP_TX1_DISABLE 9 9 RDPCS_PHY_DP_TX1_CLK_RDY 10 10 RDPCS_PHY_DP_TX1_DATA_EN 11 11 RDPCS_PHY_DP_TX1_REQ 12 12 RDPCS_PHY_DP_TX1_ACK 13 13 RDPCS_PHY_DP_TX2_RESET 16 16 RDPCS_PHY_DP_TX2_DISABLE 17 17 RDPCS_PHY_DP_TX2_CLK_RDY 18 18 RDPCS_PHY_DP_TX2_DATA_EN 19 19 RDPCS_PHY_DP_TX2_REQ 20 20 RDPCS_PHY_DP_TX2_ACK 21 21 RDPCS_PHY_DP_TX3_RESET 24 24 RDPCS_PHY_DP_TX3_DISABLE 25 25 RDPCS_PHY_DP_TX3_CLK_RDY 26 26 RDPCS_PHY_DP_TX3_DATA_EN 27 27 RDPCS_PHY_DP_TX3_REQ 28 28 RDPCS_PHY_DP_TX3_ACK 29 29 regRDPCSTX0_RDPCSTX_PHY_CNTL4 0 0x2944 16 0 2 RDPCS_PHY_DP_TX0_TERM_CTRL 0 2 RDPCS_PHY_DP_TX0_INVERT 4 4 RDPCS_PHY_DP_TX0_BYPASS_EQ_CALC 6 6 RDPCS_PHY_DP_TX0_HP_PROT_EN 7 7 RDPCS_PHY_DP_TX1_TERM_CTRL 8 10 RDPCS_PHY_DP_TX1_INVERT 12 12 RDPCS_PHY_DP_TX1_BYPASS_EQ_CALC 14 14 RDPCS_PHY_DP_TX1_HP_PROT_EN 15 15 RDPCS_PHY_DP_TX2_TERM_CTRL 16 18 RDPCS_PHY_DP_TX2_INVERT 20 20 RDPCS_PHY_DP_TX2_BYPASS_EQ_CALC 22 22 RDPCS_PHY_DP_TX2_HP_PROT_EN 23 23 RDPCS_PHY_DP_TX3_TERM_CTRL 24 26 RDPCS_PHY_DP_TX3_INVERT 28 28 RDPCS_PHY_DP_TX3_BYPASS_EQ_CALC 30 30 RDPCS_PHY_DP_TX3_HP_PROT_EN 31 31 regRDPCSTX0_RDPCSTX_PHY_CNTL5 0 0x2945 20 0 2 RDPCS_PHY_DP_TX0_LPD 0 0 RDPCS_PHY_DP_TX0_RATE 1 3 RDPCS_PHY_DP_TX0_WIDTH 4 5 RDPCS_PHY_DP_TX0_DETRX_REQ 6 6 RDPCS_PHY_DP_TX0_DETRX_RESULT 7 7 RDPCS_PHY_DP_TX1_LPD 8 8 RDPCS_PHY_DP_TX1_RATE 9 11 RDPCS_PHY_DP_TX1_WIDTH 12 13 RDPCS_PHY_DP_TX1_DETRX_REQ 14 14 RDPCS_PHY_DP_TX1_DETRX_RESULT 15 15 RDPCS_PHY_DP_TX2_LPD 16 16 RDPCS_PHY_DP_TX2_RATE 17 19 RDPCS_PHY_DP_TX2_WIDTH 20 21 RDPCS_PHY_DP_TX2_DETRX_REQ 22 22 RDPCS_PHY_DP_TX2_DETRX_RESULT 23 23 RDPCS_PHY_DP_TX3_LPD 24 24 RDPCS_PHY_DP_TX3_RATE 25 27 RDPCS_PHY_DP_TX3_WIDTH 28 29 RDPCS_PHY_DP_TX3_DETRX_REQ 30 30 RDPCS_PHY_DP_TX3_DETRX_RESULT 31 31 regRDPCSTX0_RDPCSTX_PHY_CNTL6 0 0x2946 13 0 2 RDPCS_PHY_DP_TX0_PSTATE 0 1 RDPCS_PHY_DP_TX0_MPLL_EN 2 2 RDPCS_PHY_DP_TX1_PSTATE 4 5 RDPCS_PHY_DP_TX1_MPLL_EN 6 6 RDPCS_PHY_DP_TX2_PSTATE 8 9 RDPCS_PHY_DP_TX2_MPLL_EN 10 10 RDPCS_PHY_DP_TX3_PSTATE 12 13 RDPCS_PHY_DP_TX3_MPLL_EN 14 14 RDPCS_PHY_DPALT_DP4 16 16 RDPCS_PHY_DPALT_DISABLE 17 17 RDPCS_PHY_DPALT_DISABLE_ACK 18 18 RDPCS_PHY_DP_REF_CLK_EN 19 19 RDPCS_PHY_DP_REF_CLK_REQ 20 20 regRDPCSTX0_RDPCSTX_PHY_CNTL7 0 0x2947 2 0 2 RDPCS_PHY_DP_MPLLB_FRACN_DEN 0 15 RDPCS_PHY_DP_MPLLB_FRACN_QUOT 16 31 regRDPCSTX0_RDPCSTX_PHY_CNTL8 0 0x2948 1 0 2 RDPCS_PHY_DP_MPLLB_SSC_PEAK 0 19 regRDPCSTX0_RDPCSTX_PHY_CNTL9 0 0x2949 2 0 2 RDPCS_PHY_DP_MPLLB_SSC_STEPSIZE 0 20 RDPCS_PHY_DP_MPLLB_SSC_UP_SPREAD 24 24 regRDPCSTX0_RDPCSTX_PHY_CNTL10 0 0x294a 1 0 2 RDPCS_PHY_DP_MPLLB_FRACN_REM 0 15 regRDPCSTX0_RDPCSTX_PHY_CNTL11 0 0x294b 4 0 2 RDPCS_PHY_DP_MPLLB_MULTIPLIER 4 15 RDPCS_PHY_HDMI_MPLLB_HDMI_DIV 16 18 RDPCS_PHY_DP_REF_CLK_MPLLB_DIV 20 22 RDPCS_PHY_HDMI_MPLLB_HDMI_PIXEL_CLK_DIV 24 25 regRDPCSTX0_RDPCSTX_PHY_CNTL12 0 0x294c 5 0 2 RDPCS_PHY_DP_MPLLB_DIV5_CLK_EN 0 0 RDPCS_PHY_DP_MPLLB_WORD_DIV2_EN 2 2 RDPCS_PHY_DP_MPLLB_TX_CLK_DIV 4 6 RDPCS_PHY_DP_MPLLB_STATE 7 7 RDPCS_PHY_DP_MPLLB_SSC_EN 8 8 regRDPCSTX0_RDPCSTX_PHY_CNTL13 0 0x294d 4 0 2 RDPCS_PHY_DP_MPLLB_DIV_MULTIPLIER 20 27 RDPCS_PHY_DP_MPLLB_DIV_CLK_EN 28 28 RDPCS_PHY_DP_MPLLB_FORCE_EN 29 29 RDPCS_PHY_DP_MPLLB_INIT_CAL_DISABLE 30 30 regRDPCSTX0_RDPCSTX_PHY_CNTL14 0 0x294e 3 0 2 RDPCS_PHY_DP_MPLLB_CAL_FORCE 0 0 RDPCS_PHY_DP_MPLLB_FRACN_EN 24 24 RDPCS_PHY_DP_MPLLB_PMIX_EN 28 28 regRDPCSTX0_RDPCSTX_PHY_FUSE0 0 0x294f 7 0 2 RDPCS_PHY_DP_TX0_EQ_MAIN 0 5 RDPCS_PHY_DP_TX0_EQ_PRE 6 11 RDPCS_PHY_DP_TX0_EQ_POST 12 17 RDPCS_PHY_DP_MPLLB_V2I 18 19 RDPCS_PHY_DP_MPLLB_FREQ_VCO 20 21 RDPCS_PHY_DP_MPLLB_CP_INT_GS 22 28 RDPCS_PHY_RX_VREF_CTRL 29 31 regRDPCSTX0_RDPCSTX_PHY_FUSE1 0 0x2950 5 0 2 RDPCS_PHY_DP_TX1_EQ_MAIN 0 5 RDPCS_PHY_DP_TX1_EQ_PRE 6 11 RDPCS_PHY_DP_TX1_EQ_POST 12 17 RDPCS_PHY_DP_MPLLB_CP_INT 18 24 RDPCS_PHY_DP_MPLLB_CP_PROP 25 31 regRDPCSTX0_RDPCSTX_PHY_FUSE2 0 0x2951 4 0 2 RDPCS_PHY_DP_TX2_EQ_MAIN 0 5 RDPCS_PHY_DP_TX2_EQ_PRE 6 11 RDPCS_PHY_DP_TX2_EQ_POST 12 17 RDPCS_PHY_DP_MPLLB_CP_PROP_GS 23 29 regRDPCSTX0_RDPCSTX_PHY_FUSE3 0 0x2952 7 0 2 RDPCS_PHY_DP_TX3_EQ_MAIN 0 5 RDPCS_PHY_DP_TX3_EQ_PRE 6 11 RDPCS_PHY_DP_TX3_EQ_POST 12 17 RDPCS_PHY_DCO_FINETUNE 18 23 RDPCS_PHY_DCO_RANGE 24 25 RDPCS_PHY_TX_VBOOST_LVL 26 28 RDPCS_PHY_SUP_RX_VCO_VREF_SEL 29 31 regRDPCSTX0_RDPCSTX_PHY_RX_LD_VAL 0 0x2953 3 0 2 RDPCS_PHY_RX_REF_LD_VAL 0 6 RDPCS_PHY_RX_CDR_VCO_LOWFREQ 7 7 RDPCS_PHY_RX_VCO_LD_VAL 8 20 regRDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3 0 0x2954 24 0 2 RDPCS_PHY_DP_TX0_RESET_RESERVED 0 0 RDPCS_PHY_DP_TX0_DISABLE_RESERVED 1 1 RDPCS_PHY_DP_TX0_CLK_RDY_RESERVED 2 2 RDPCS_PHY_DP_TX0_DATA_EN_RESERVED 3 3 RDPCS_PHY_DP_TX0_REQ_RESERVED 4 4 RDPCS_PHY_DP_TX0_ACK_RESERVED 5 5 RDPCS_PHY_DP_TX1_RESET_RESERVED 8 8 RDPCS_PHY_DP_TX1_DISABLE_RESERVED 9 9 RDPCS_PHY_DP_TX1_CLK_RDY_RESERVED 10 10 RDPCS_PHY_DP_TX1_DATA_EN_RESERVED 11 11 RDPCS_PHY_DP_TX1_REQ_RESERVED 12 12 RDPCS_PHY_DP_TX1_ACK_RESERVED 13 13 RDPCS_PHY_DP_TX2_RESET_RESERVED 16 16 RDPCS_PHY_DP_TX2_DISABLE_RESERVED 17 17 RDPCS_PHY_DP_TX2_CLK_RDY_RESERVED 18 18 RDPCS_PHY_DP_TX2_DATA_EN_RESERVED 19 19 RDPCS_PHY_DP_TX2_REQ_RESERVED 20 20 RDPCS_PHY_DP_TX2_ACK_RESERVED 21 21 RDPCS_PHY_DP_TX3_RESET_RESERVED 24 24 RDPCS_PHY_DP_TX3_DISABLE_RESERVED 25 25 RDPCS_PHY_DP_TX3_CLK_RDY_RESERVED 26 26 RDPCS_PHY_DP_TX3_DATA_EN_RESERVED 27 27 RDPCS_PHY_DP_TX3_REQ_RESERVED 28 28 RDPCS_PHY_DP_TX3_ACK_RESERVED 29 29 regRDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL6 0 0x2955 13 0 2 RDPCS_PHY_DP_TX0_PSTATE_RESERVED 0 1 RDPCS_PHY_DP_TX0_MPLL_EN_RESERVED 2 2 RDPCS_PHY_DP_TX1_PSTATE_RESERVED 4 5 RDPCS_PHY_DP_TX1_MPLL_EN_RESERVED 6 6 RDPCS_PHY_DP_TX2_PSTATE_RESERVED 8 9 RDPCS_PHY_DP_TX2_MPLL_EN_RESERVED 10 10 RDPCS_PHY_DP_TX3_PSTATE_RESERVED 12 13 RDPCS_PHY_DP_TX3_MPLL_EN_RESERVED 14 14 RDPCS_PHY_DPALT_DP4_RESERVED 16 16 RDPCS_PHY_DPALT_DISABLE_RESERVED 17 17 RDPCS_PHY_DPALT_DISABLE_ACK_RESERVED 18 18 RDPCS_PHY_DP_REF_CLK_EN_RESERVED 19 19 RDPCS_PHY_DP_REF_CLK_REQ_RESERVED 20 20 regRDPCSTX0_RDPCSTX_DPALT_CONTROL_REG 0 0x2956 3 0 2 RDPCS_ALLOW_DRIVER_ACCESS 0 0 RDPCS_DRIVER_ACCESS_BLOCKED 4 4 RDPCS_DPALT_CONTROL_SPARE 8 15 regRDPCSTX0_RDPCSTX_PHY_CNTL15 0 0x2958 6 0 2 RDPCS_PHY_SSTX_VREGDRV_BYP 0 0 RDPCS_PHY_DP_TX0_VREGDRV_BYP 16 16 RDPCS_PHY_DP_TX1_VREGDRV_BYP 17 17 RDPCS_PHY_DP_TX2_VREGDRV_BYP 18 18 RDPCS_PHY_DP_TX3_VREGDRV_BYP 19 19 RDPCS_PHY_SUP_PRE_HP 20 20 regRDPCSTX0_RDPCSTX_PHY_CNTL16 0 0x2959 5 0 2 RDPCS_PHY_DP_TX0_OUT_GENERIC_BUS 0 4 RDPCS_PHY_DP_TX1_OUT_GENERIC_BUS 6 10 RDPCS_PHY_DP_TX2_OUT_GENERIC_BUS 12 16 RDPCS_PHY_DP_TX3_OUT_GENERIC_BUS 18 22 RDPCS_PHY_CMN_OUT_GENERIC_BUS 24 28 regRDPCSTX0_RDPCSTX_PHY_CNTL17 0 0x295a 5 0 2 RDPCS_PHY_DP_TX0_IN_GENERIC_BUS 0 4 RDPCS_PHY_DP_TX1_IN_GENERIC_BUS 6 10 RDPCS_PHY_DP_TX2_IN_GENERIC_BUS 12 16 RDPCS_PHY_DP_TX3_IN_GENERIC_BUS 18 22 RDPCS_PHY_CMN_IN_GENERIC_BUS 24 28 regRDPCSTX0_RDPCSTX_DEBUG_CONFIG2 0 0x295b 5 0 2 RDPCS_DBG_OCLA_SRC0 0 2 RDPCS_DBG_OCLA_SRC1 4 6 RDPCS_DBG_OCLA_SRC2 8 10 RDPCS_DBG_OCLA_SRC3 12 14 RDPCS_DBG_OCLA_VALID_REPLACE_MSB 16 16 regRDPCSTX0_RDPCS_CNTL3 0 0x295c 4 0 2 TX_LANE0_BYTE_ORDER_CHANGE 0 7 TX_LANE1_BYTE_ORDER_CHANGE 8 15 TX_LANE2_BYTE_ORDER_CHANGE 16 23 TX_LANE3_BYTE_ORDER_CHANGE 24 31 regRDPCSTX0_RDPCS_TX_PLL_UPDATE_ADDR_OVRRD 0 0x295d 1 0 2 RDPCS_PLL_UPDATE_ADDR_OVRRD 0 17 regRDPCSTX0_RDPCS_TX_PLL_UPDATE_DATA_OVRRD 0 0x295e 1 0 2 RDPCS_PLL_UPDATE_DATA_OVRRD 0 31 regRDPCSTX1_RDPCSTX_CNTL 0 0x2a08 24 0 2 RDPCS_CBUS_SOFT_RESET 0 0 RDPCS_SRAM_SOFT_RESET 1 1 TX_LANE0_BIT_ORDER_REVERSE_BEFORE_PACK 4 4 TX_LANE1_BIT_ORDER_REVERSE_BEFORE_PACK 5 5 TX_LANE2_BIT_ORDER_REVERSE_BEFORE_PACK 6 6 TX_LANE3_BIT_ORDER_REVERSE_BEFORE_PACK 7 7 RDPCS_INTERRUPT_MASK 8 8 RDPCS_TX_PLL_UPDATE_REQ 9 9 RDPCS_TX_PLL_UPDATE_PENDING 10 10 RDPCS_TX_FIFO_LANE0_EN 12 12 RDPCS_TX_FIFO_LANE1_EN 13 13 RDPCS_TX_FIFO_LANE2_EN 14 14 RDPCS_TX_FIFO_LANE3_EN 15 15 TX_LANE0_PACK_FROM_MSB 16 16 TX_LANE1_PACK_FROM_MSB 17 17 TX_LANE2_PACK_FROM_MSB 18 18 TX_LANE3_PACK_FROM_MSB 19 19 RDPCS_TX_FIFO_RD_START_DELAY 20 24 RDPCS_TX_FIFO_EN 25 25 RDPCS_TX_FIFO_START 26 26 RDPCS_CR_REGISTER_BLOCK_EN 28 28 RDPCS_NON_DPALT_REGISTER_BLOCK_EN 29 29 RDPCS_DPALT_BLOCK_STATUS 30 30 RDPCS_TX_SOFT_RESET 31 31 regRDPCSTX1_RDPCSTX_CLOCK_CNTL 0 0x2a09 16 0 2 RDPCS_EXT_REFCLK_EN 0 0 RDPCS_TX0_CLK_EN 4 4 RDPCS_TX1_CLK_EN 5 5 RDPCS_TX2_CLK_EN 6 6 RDPCS_TX3_CLK_EN 7 7 RDPCS_TX_CLK_GATE_DIS 8 8 RDPCS_TX_CLK_EN 9 9 RDPCS_TX_CLK_CLOCK_ON 10 10 RDPCS_TX_PHY_REF_ALT_CLK_EN 11 11 RDPCS_SRAMCLK_GATE_DIS 12 12 RDPCS_SRAMCLK_EN 13 13 RDPCS_SRAMCLK_CLOCK_ON 14 14 RDPCS_SRAMCLK_BYPASS 16 16 RDPCS_OCLACLK_GATE_DIS 20 20 RDPCS_OCLACLK_EN 21 21 RDPCS_OCLACLK_CLOCK_ON 22 22 regRDPCSTX1_RDPCSTX_INTERRUPT_CONTROL 0 0x2a0a 15 0 2 RDPCS_REG_FIFO_OVERFLOW 0 0 RDPCS_DPALT_DISABLE_TOGGLE 1 1 RDPCS_DPALT_4LANE_TOGGLE 2 2 RDPCS_TX0_FIFO_ERROR 4 4 RDPCS_TX1_FIFO_ERROR 5 5 RDPCS_TX2_FIFO_ERROR 6 6 RDPCS_TX3_FIFO_ERROR 7 7 RDPCS_REG_ERROR_CLR 8 8 RDPCS_DPALT_DISABLE_TOGGLE_CLR 9 9 RDPCS_DPALT_4LANE_TOGGLE_CLR 10 10 RDPCS_TX_ERROR_CLR 12 12 RDPCS_REG_FIFO_ERROR_MASK 16 16 RDPCS_DPALT_DISABLE_TOGGLE_MASK 17 17 RDPCS_DPALT_4LANE_TOGGLE_MASK 18 18 RDPCS_TX_FIFO_ERROR_MASK 20 20 regRDPCSTX1_RDPCS_TX_PLL_UPDATE_DATA 0 0x2a0b 1 0 2 RDPCS_PLL_UPDATE_DATA 0 0 regRDPCSTX1_RDPCS_TX_CR_ADDR 0 0x2a0c 1 0 2 RDPCS_TX_CR_ADDR 0 15 regRDPCSTX1_RDPCS_TX_CR_DATA 0 0x2a0d 1 0 2 RDPCS_TX_CR_DATA 0 15 regRDPCSTX1_RDPCS_TX_SRAM_CNTL 0 0x2a0e 3 0 2 RDPCS_MEM_PWR_DIS 20 20 RDPCS_MEM_PWR_FORCE 24 25 RDPCS_MEM_PWR_PWR_STATE 28 29 regRDPCSTX1_RDPCSTX_SCRATCH 0 0x2a0f 1 0 2 RDPCSTX_SCRATCH 0 31 regRDPCSTX1_RDPCSTX_SPARE 0 0x2a10 1 0 2 RDPCSTX_SPARE 0 31 regRDPCSTX1_RDPCSTX_CNTL2 0 0x2a11 3 0 2 RDPCS_CR_CONVERT_FIFO_EMPTY 0 0 RDPCS_CR_CONVERT_FIFO_FULL 1 1 RDPCS_PHY_ENC_TYPE_SEL 2 3 regRDPCSTX1_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG 0 0x2a14 3 0 2 RDPCS_DMCU_DPALT_DIS_BLOCK_REG 0 0 RDPCS_DMCU_DPALT_FORCE_TX_CLK_DIS 4 4 RDPCS_DMCU_DPALT_CONTROL_SPARE 8 15 regRDPCSTX1_RDPCSTX_DEBUG_CONFIG 0 0x2a15 7 0 2 RDPCS_DBG_EN 0 0 RDPCS_DBG_SEL_ASYNC_8BIT 4 6 RDPCS_DBG_SEL_ASYNC_SWAP 7 7 RDPCS_DBG_SEL_TEST_CLK 8 12 RDPCS_DBG_CR_COUNT_EXPIRE 15 15 RDPCS_DBG_CR_COUNT_MAX 16 23 RDPCS_DBG_CR_COUNT 24 31 regRDPCSTX1_RDPCSTX_PHY_CNTL0 0 0x2a18 16 0 2 RDPCS_PHY_RESET 0 0 RDPCS_PHY_TCA_PHY_RESET 1 1 RDPCS_PHY_TCA_APB_RESET_N 2 2 RDPCS_PHY_TEST_POWERDOWN 3 3 RDPCS_PHY_DTB_OUT 4 5 RDPCS_PHY_HDMIMODE_ENABLE 8 8 RDPCS_PHY_REF_RANGE 9 13 RDPCS_PHY_RTUNE_REQ 17 17 RDPCS_PHY_RTUNE_ACK 18 18 RDPCS_PHY_CR_PARA_SEL 20 20 RDPCS_PHY_CR_MUX_SEL 21 21 RDPCS_PHY_REF_CLKDET_EN 24 24 RDPCS_PHY_REF_CLKDET_RESULT 25 25 RDPCS_SRAM_INIT_DONE 28 28 RDPCS_SRAM_EXT_LD_DONE 29 29 RDPCS_SRAM_BYPASS 31 31 regRDPCSTX1_RDPCSTX_PHY_CNTL1 0 0x2a19 8 0 2 RDPCS_PHY_PG_MODE_EN 0 0 RDPCS_PHY_PCS_PWR_EN 1 1 RDPCS_PHY_PCS_PWR_STABLE 2 2 RDPCS_PHY_PMA_PWR_EN 3 3 RDPCS_PHY_PMA_PWR_STABLE 4 4 RDPCS_PHY_DP_PG_RESET 5 5 RDPCS_PHY_ANA_PWR_EN 6 6 RDPCS_PHY_ANA_PWR_STABLE 7 7 regRDPCSTX1_RDPCSTX_PHY_CNTL2 0 0x2a1a 9 0 2 RDPCS_PHY_DP4_POR 3 3 RDPCS_PHY_DP_LANE0_RX2TX_PAR_LB_EN 4 4 RDPCS_PHY_DP_LANE1_RX2TX_PAR_LB_EN 5 5 RDPCS_PHY_DP_LANE2_RX2TX_PAR_LB_EN 6 6 RDPCS_PHY_DP_LANE3_RX2TX_PAR_LB_EN 7 7 RDPCS_PHY_DP_LANE0_TX2RX_SER_LB_EN 8 8 RDPCS_PHY_DP_LANE1_TX2RX_SER_LB_EN 9 9 RDPCS_PHY_DP_LANE2_TX2RX_SER_LB_EN 10 10 RDPCS_PHY_DP_LANE3_TX2RX_SER_LB_EN 11 11 regRDPCSTX1_RDPCSTX_PHY_CNTL3 0 0x2a1b 24 0 2 RDPCS_PHY_DP_TX0_RESET 0 0 RDPCS_PHY_DP_TX0_DISABLE 1 1 RDPCS_PHY_DP_TX0_CLK_RDY 2 2 RDPCS_PHY_DP_TX0_DATA_EN 3 3 RDPCS_PHY_DP_TX0_REQ 4 4 RDPCS_PHY_DP_TX0_ACK 5 5 RDPCS_PHY_DP_TX1_RESET 8 8 RDPCS_PHY_DP_TX1_DISABLE 9 9 RDPCS_PHY_DP_TX1_CLK_RDY 10 10 RDPCS_PHY_DP_TX1_DATA_EN 11 11 RDPCS_PHY_DP_TX1_REQ 12 12 RDPCS_PHY_DP_TX1_ACK 13 13 RDPCS_PHY_DP_TX2_RESET 16 16 RDPCS_PHY_DP_TX2_DISABLE 17 17 RDPCS_PHY_DP_TX2_CLK_RDY 18 18 RDPCS_PHY_DP_TX2_DATA_EN 19 19 RDPCS_PHY_DP_TX2_REQ 20 20 RDPCS_PHY_DP_TX2_ACK 21 21 RDPCS_PHY_DP_TX3_RESET 24 24 RDPCS_PHY_DP_TX3_DISABLE 25 25 RDPCS_PHY_DP_TX3_CLK_RDY 26 26 RDPCS_PHY_DP_TX3_DATA_EN 27 27 RDPCS_PHY_DP_TX3_REQ 28 28 RDPCS_PHY_DP_TX3_ACK 29 29 regRDPCSTX1_RDPCSTX_PHY_CNTL4 0 0x2a1c 16 0 2 RDPCS_PHY_DP_TX0_TERM_CTRL 0 2 RDPCS_PHY_DP_TX0_INVERT 4 4 RDPCS_PHY_DP_TX0_BYPASS_EQ_CALC 6 6 RDPCS_PHY_DP_TX0_HP_PROT_EN 7 7 RDPCS_PHY_DP_TX1_TERM_CTRL 8 10 RDPCS_PHY_DP_TX1_INVERT 12 12 RDPCS_PHY_DP_TX1_BYPASS_EQ_CALC 14 14 RDPCS_PHY_DP_TX1_HP_PROT_EN 15 15 RDPCS_PHY_DP_TX2_TERM_CTRL 16 18 RDPCS_PHY_DP_TX2_INVERT 20 20 RDPCS_PHY_DP_TX2_BYPASS_EQ_CALC 22 22 RDPCS_PHY_DP_TX2_HP_PROT_EN 23 23 RDPCS_PHY_DP_TX3_TERM_CTRL 24 26 RDPCS_PHY_DP_TX3_INVERT 28 28 RDPCS_PHY_DP_TX3_BYPASS_EQ_CALC 30 30 RDPCS_PHY_DP_TX3_HP_PROT_EN 31 31 regRDPCSTX1_RDPCSTX_PHY_CNTL5 0 0x2a1d 20 0 2 RDPCS_PHY_DP_TX0_LPD 0 0 RDPCS_PHY_DP_TX0_RATE 1 3 RDPCS_PHY_DP_TX0_WIDTH 4 5 RDPCS_PHY_DP_TX0_DETRX_REQ 6 6 RDPCS_PHY_DP_TX0_DETRX_RESULT 7 7 RDPCS_PHY_DP_TX1_LPD 8 8 RDPCS_PHY_DP_TX1_RATE 9 11 RDPCS_PHY_DP_TX1_WIDTH 12 13 RDPCS_PHY_DP_TX1_DETRX_REQ 14 14 RDPCS_PHY_DP_TX1_DETRX_RESULT 15 15 RDPCS_PHY_DP_TX2_LPD 16 16 RDPCS_PHY_DP_TX2_RATE 17 19 RDPCS_PHY_DP_TX2_WIDTH 20 21 RDPCS_PHY_DP_TX2_DETRX_REQ 22 22 RDPCS_PHY_DP_TX2_DETRX_RESULT 23 23 RDPCS_PHY_DP_TX3_LPD 24 24 RDPCS_PHY_DP_TX3_RATE 25 27 RDPCS_PHY_DP_TX3_WIDTH 28 29 RDPCS_PHY_DP_TX3_DETRX_REQ 30 30 RDPCS_PHY_DP_TX3_DETRX_RESULT 31 31 regRDPCSTX1_RDPCSTX_PHY_CNTL6 0 0x2a1e 13 0 2 RDPCS_PHY_DP_TX0_PSTATE 0 1 RDPCS_PHY_DP_TX0_MPLL_EN 2 2 RDPCS_PHY_DP_TX1_PSTATE 4 5 RDPCS_PHY_DP_TX1_MPLL_EN 6 6 RDPCS_PHY_DP_TX2_PSTATE 8 9 RDPCS_PHY_DP_TX2_MPLL_EN 10 10 RDPCS_PHY_DP_TX3_PSTATE 12 13 RDPCS_PHY_DP_TX3_MPLL_EN 14 14 RDPCS_PHY_DPALT_DP4 16 16 RDPCS_PHY_DPALT_DISABLE 17 17 RDPCS_PHY_DPALT_DISABLE_ACK 18 18 RDPCS_PHY_DP_REF_CLK_EN 19 19 RDPCS_PHY_DP_REF_CLK_REQ 20 20 regRDPCSTX1_RDPCSTX_PHY_CNTL7 0 0x2a1f 2 0 2 RDPCS_PHY_DP_MPLLB_FRACN_DEN 0 15 RDPCS_PHY_DP_MPLLB_FRACN_QUOT 16 31 regRDPCSTX1_RDPCSTX_PHY_CNTL8 0 0x2a20 1 0 2 RDPCS_PHY_DP_MPLLB_SSC_PEAK 0 19 regRDPCSTX1_RDPCSTX_PHY_CNTL9 0 0x2a21 2 0 2 RDPCS_PHY_DP_MPLLB_SSC_STEPSIZE 0 20 RDPCS_PHY_DP_MPLLB_SSC_UP_SPREAD 24 24 regRDPCSTX1_RDPCSTX_PHY_CNTL10 0 0x2a22 1 0 2 RDPCS_PHY_DP_MPLLB_FRACN_REM 0 15 regRDPCSTX1_RDPCSTX_PHY_CNTL11 0 0x2a23 4 0 2 RDPCS_PHY_DP_MPLLB_MULTIPLIER 4 15 RDPCS_PHY_HDMI_MPLLB_HDMI_DIV 16 18 RDPCS_PHY_DP_REF_CLK_MPLLB_DIV 20 22 RDPCS_PHY_HDMI_MPLLB_HDMI_PIXEL_CLK_DIV 24 25 regRDPCSTX1_RDPCSTX_PHY_CNTL12 0 0x2a24 5 0 2 RDPCS_PHY_DP_MPLLB_DIV5_CLK_EN 0 0 RDPCS_PHY_DP_MPLLB_WORD_DIV2_EN 2 2 RDPCS_PHY_DP_MPLLB_TX_CLK_DIV 4 6 RDPCS_PHY_DP_MPLLB_STATE 7 7 RDPCS_PHY_DP_MPLLB_SSC_EN 8 8 regRDPCSTX1_RDPCSTX_PHY_CNTL13 0 0x2a25 4 0 2 RDPCS_PHY_DP_MPLLB_DIV_MULTIPLIER 20 27 RDPCS_PHY_DP_MPLLB_DIV_CLK_EN 28 28 RDPCS_PHY_DP_MPLLB_FORCE_EN 29 29 RDPCS_PHY_DP_MPLLB_INIT_CAL_DISABLE 30 30 regRDPCSTX1_RDPCSTX_PHY_CNTL14 0 0x2a26 3 0 2 RDPCS_PHY_DP_MPLLB_CAL_FORCE 0 0 RDPCS_PHY_DP_MPLLB_FRACN_EN 24 24 RDPCS_PHY_DP_MPLLB_PMIX_EN 28 28 regRDPCSTX1_RDPCSTX_PHY_FUSE0 0 0x2a27 7 0 2 RDPCS_PHY_DP_TX0_EQ_MAIN 0 5 RDPCS_PHY_DP_TX0_EQ_PRE 6 11 RDPCS_PHY_DP_TX0_EQ_POST 12 17 RDPCS_PHY_DP_MPLLB_V2I 18 19 RDPCS_PHY_DP_MPLLB_FREQ_VCO 20 21 RDPCS_PHY_DP_MPLLB_CP_INT_GS 22 28 RDPCS_PHY_RX_VREF_CTRL 29 31 regRDPCSTX1_RDPCSTX_PHY_FUSE1 0 0x2a28 5 0 2 RDPCS_PHY_DP_TX1_EQ_MAIN 0 5 RDPCS_PHY_DP_TX1_EQ_PRE 6 11 RDPCS_PHY_DP_TX1_EQ_POST 12 17 RDPCS_PHY_DP_MPLLB_CP_INT 18 24 RDPCS_PHY_DP_MPLLB_CP_PROP 25 31 regRDPCSTX1_RDPCSTX_PHY_FUSE2 0 0x2a29 4 0 2 RDPCS_PHY_DP_TX2_EQ_MAIN 0 5 RDPCS_PHY_DP_TX2_EQ_PRE 6 11 RDPCS_PHY_DP_TX2_EQ_POST 12 17 RDPCS_PHY_DP_MPLLB_CP_PROP_GS 23 29 regRDPCSTX1_RDPCSTX_PHY_FUSE3 0 0x2a2a 7 0 2 RDPCS_PHY_DP_TX3_EQ_MAIN 0 5 RDPCS_PHY_DP_TX3_EQ_PRE 6 11 RDPCS_PHY_DP_TX3_EQ_POST 12 17 RDPCS_PHY_DCO_FINETUNE 18 23 RDPCS_PHY_DCO_RANGE 24 25 RDPCS_PHY_TX_VBOOST_LVL 26 28 RDPCS_PHY_SUP_RX_VCO_VREF_SEL 29 31 regRDPCSTX1_RDPCSTX_PHY_RX_LD_VAL 0 0x2a2b 3 0 2 RDPCS_PHY_RX_REF_LD_VAL 0 6 RDPCS_PHY_RX_CDR_VCO_LOWFREQ 7 7 RDPCS_PHY_RX_VCO_LD_VAL 8 20 regRDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3 0 0x2a2c 24 0 2 RDPCS_PHY_DP_TX0_RESET_RESERVED 0 0 RDPCS_PHY_DP_TX0_DISABLE_RESERVED 1 1 RDPCS_PHY_DP_TX0_CLK_RDY_RESERVED 2 2 RDPCS_PHY_DP_TX0_DATA_EN_RESERVED 3 3 RDPCS_PHY_DP_TX0_REQ_RESERVED 4 4 RDPCS_PHY_DP_TX0_ACK_RESERVED 5 5 RDPCS_PHY_DP_TX1_RESET_RESERVED 8 8 RDPCS_PHY_DP_TX1_DISABLE_RESERVED 9 9 RDPCS_PHY_DP_TX1_CLK_RDY_RESERVED 10 10 RDPCS_PHY_DP_TX1_DATA_EN_RESERVED 11 11 RDPCS_PHY_DP_TX1_REQ_RESERVED 12 12 RDPCS_PHY_DP_TX1_ACK_RESERVED 13 13 RDPCS_PHY_DP_TX2_RESET_RESERVED 16 16 RDPCS_PHY_DP_TX2_DISABLE_RESERVED 17 17 RDPCS_PHY_DP_TX2_CLK_RDY_RESERVED 18 18 RDPCS_PHY_DP_TX2_DATA_EN_RESERVED 19 19 RDPCS_PHY_DP_TX2_REQ_RESERVED 20 20 RDPCS_PHY_DP_TX2_ACK_RESERVED 21 21 RDPCS_PHY_DP_TX3_RESET_RESERVED 24 24 RDPCS_PHY_DP_TX3_DISABLE_RESERVED 25 25 RDPCS_PHY_DP_TX3_CLK_RDY_RESERVED 26 26 RDPCS_PHY_DP_TX3_DATA_EN_RESERVED 27 27 RDPCS_PHY_DP_TX3_REQ_RESERVED 28 28 RDPCS_PHY_DP_TX3_ACK_RESERVED 29 29 regRDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL6 0 0x2a2d 13 0 2 RDPCS_PHY_DP_TX0_PSTATE_RESERVED 0 1 RDPCS_PHY_DP_TX0_MPLL_EN_RESERVED 2 2 RDPCS_PHY_DP_TX1_PSTATE_RESERVED 4 5 RDPCS_PHY_DP_TX1_MPLL_EN_RESERVED 6 6 RDPCS_PHY_DP_TX2_PSTATE_RESERVED 8 9 RDPCS_PHY_DP_TX2_MPLL_EN_RESERVED 10 10 RDPCS_PHY_DP_TX3_PSTATE_RESERVED 12 13 RDPCS_PHY_DP_TX3_MPLL_EN_RESERVED 14 14 RDPCS_PHY_DPALT_DP4_RESERVED 16 16 RDPCS_PHY_DPALT_DISABLE_RESERVED 17 17 RDPCS_PHY_DPALT_DISABLE_ACK_RESERVED 18 18 RDPCS_PHY_DP_REF_CLK_EN_RESERVED 19 19 RDPCS_PHY_DP_REF_CLK_REQ_RESERVED 20 20 regRDPCSTX1_RDPCSTX_DPALT_CONTROL_REG 0 0x2a2e 3 0 2 RDPCS_ALLOW_DRIVER_ACCESS 0 0 RDPCS_DRIVER_ACCESS_BLOCKED 4 4 RDPCS_DPALT_CONTROL_SPARE 8 15 regRDPCSTX1_RDPCSTX_PHY_CNTL15 0 0x2a30 6 0 2 RDPCS_PHY_SSTX_VREGDRV_BYP 0 0 RDPCS_PHY_DP_TX0_VREGDRV_BYP 16 16 RDPCS_PHY_DP_TX1_VREGDRV_BYP 17 17 RDPCS_PHY_DP_TX2_VREGDRV_BYP 18 18 RDPCS_PHY_DP_TX3_VREGDRV_BYP 19 19 RDPCS_PHY_SUP_PRE_HP 20 20 regRDPCSTX1_RDPCSTX_PHY_CNTL16 0 0x2a31 5 0 2 RDPCS_PHY_DP_TX0_OUT_GENERIC_BUS 0 4 RDPCS_PHY_DP_TX1_OUT_GENERIC_BUS 6 10 RDPCS_PHY_DP_TX2_OUT_GENERIC_BUS 12 16 RDPCS_PHY_DP_TX3_OUT_GENERIC_BUS 18 22 RDPCS_PHY_CMN_OUT_GENERIC_BUS 24 28 regRDPCSTX1_RDPCSTX_PHY_CNTL17 0 0x2a32 5 0 2 RDPCS_PHY_DP_TX0_IN_GENERIC_BUS 0 4 RDPCS_PHY_DP_TX1_IN_GENERIC_BUS 6 10 RDPCS_PHY_DP_TX2_IN_GENERIC_BUS 12 16 RDPCS_PHY_DP_TX3_IN_GENERIC_BUS 18 22 RDPCS_PHY_CMN_IN_GENERIC_BUS 24 28 regRDPCSTX1_RDPCSTX_DEBUG_CONFIG2 0 0x2a33 5 0 2 RDPCS_DBG_OCLA_SRC0 0 2 RDPCS_DBG_OCLA_SRC1 4 6 RDPCS_DBG_OCLA_SRC2 8 10 RDPCS_DBG_OCLA_SRC3 12 14 RDPCS_DBG_OCLA_VALID_REPLACE_MSB 16 16 regRDPCSTX1_RDPCS_CNTL3 0 0x2a34 4 0 2 TX_LANE0_BYTE_ORDER_CHANGE 0 7 TX_LANE1_BYTE_ORDER_CHANGE 8 15 TX_LANE2_BYTE_ORDER_CHANGE 16 23 TX_LANE3_BYTE_ORDER_CHANGE 24 31 regRDPCSTX1_RDPCS_TX_PLL_UPDATE_ADDR_OVRRD 0 0x2a35 1 0 2 RDPCS_PLL_UPDATE_ADDR_OVRRD 0 17 regRDPCSTX1_RDPCS_TX_PLL_UPDATE_DATA_OVRRD 0 0x2a36 1 0 2 RDPCS_PLL_UPDATE_DATA_OVRRD 0 31 regRDPCSTX2_RDPCSTX_CNTL 0 0x2ae0 24 0 2 RDPCS_CBUS_SOFT_RESET 0 0 RDPCS_SRAM_SOFT_RESET 1 1 TX_LANE0_BIT_ORDER_REVERSE_BEFORE_PACK 4 4 TX_LANE1_BIT_ORDER_REVERSE_BEFORE_PACK 5 5 TX_LANE2_BIT_ORDER_REVERSE_BEFORE_PACK 6 6 TX_LANE3_BIT_ORDER_REVERSE_BEFORE_PACK 7 7 RDPCS_INTERRUPT_MASK 8 8 RDPCS_TX_PLL_UPDATE_REQ 9 9 RDPCS_TX_PLL_UPDATE_PENDING 10 10 RDPCS_TX_FIFO_LANE0_EN 12 12 RDPCS_TX_FIFO_LANE1_EN 13 13 RDPCS_TX_FIFO_LANE2_EN 14 14 RDPCS_TX_FIFO_LANE3_EN 15 15 TX_LANE0_PACK_FROM_MSB 16 16 TX_LANE1_PACK_FROM_MSB 17 17 TX_LANE2_PACK_FROM_MSB 18 18 TX_LANE3_PACK_FROM_MSB 19 19 RDPCS_TX_FIFO_RD_START_DELAY 20 24 RDPCS_TX_FIFO_EN 25 25 RDPCS_TX_FIFO_START 26 26 RDPCS_CR_REGISTER_BLOCK_EN 28 28 RDPCS_NON_DPALT_REGISTER_BLOCK_EN 29 29 RDPCS_DPALT_BLOCK_STATUS 30 30 RDPCS_TX_SOFT_RESET 31 31 regRDPCSTX2_RDPCSTX_CLOCK_CNTL 0 0x2ae1 16 0 2 RDPCS_EXT_REFCLK_EN 0 0 RDPCS_TX0_CLK_EN 4 4 RDPCS_TX1_CLK_EN 5 5 RDPCS_TX2_CLK_EN 6 6 RDPCS_TX3_CLK_EN 7 7 RDPCS_TX_CLK_GATE_DIS 8 8 RDPCS_TX_CLK_EN 9 9 RDPCS_TX_CLK_CLOCK_ON 10 10 RDPCS_TX_PHY_REF_ALT_CLK_EN 11 11 RDPCS_SRAMCLK_GATE_DIS 12 12 RDPCS_SRAMCLK_EN 13 13 RDPCS_SRAMCLK_CLOCK_ON 14 14 RDPCS_SRAMCLK_BYPASS 16 16 RDPCS_OCLACLK_GATE_DIS 20 20 RDPCS_OCLACLK_EN 21 21 RDPCS_OCLACLK_CLOCK_ON 22 22 regRDPCSTX2_RDPCSTX_INTERRUPT_CONTROL 0 0x2ae2 15 0 2 RDPCS_REG_FIFO_OVERFLOW 0 0 RDPCS_DPALT_DISABLE_TOGGLE 1 1 RDPCS_DPALT_4LANE_TOGGLE 2 2 RDPCS_TX0_FIFO_ERROR 4 4 RDPCS_TX1_FIFO_ERROR 5 5 RDPCS_TX2_FIFO_ERROR 6 6 RDPCS_TX3_FIFO_ERROR 7 7 RDPCS_REG_ERROR_CLR 8 8 RDPCS_DPALT_DISABLE_TOGGLE_CLR 9 9 RDPCS_DPALT_4LANE_TOGGLE_CLR 10 10 RDPCS_TX_ERROR_CLR 12 12 RDPCS_REG_FIFO_ERROR_MASK 16 16 RDPCS_DPALT_DISABLE_TOGGLE_MASK 17 17 RDPCS_DPALT_4LANE_TOGGLE_MASK 18 18 RDPCS_TX_FIFO_ERROR_MASK 20 20 regRDPCSTX2_RDPCS_TX_PLL_UPDATE_DATA 0 0x2ae3 1 0 2 RDPCS_PLL_UPDATE_DATA 0 0 regRDPCSTX2_RDPCS_TX_CR_ADDR 0 0x2ae4 1 0 2 RDPCS_TX_CR_ADDR 0 15 regRDPCSTX2_RDPCS_TX_CR_DATA 0 0x2ae5 1 0 2 RDPCS_TX_CR_DATA 0 15 regRDPCSTX2_RDPCS_TX_SRAM_CNTL 0 0x2ae6 3 0 2 RDPCS_MEM_PWR_DIS 20 20 RDPCS_MEM_PWR_FORCE 24 25 RDPCS_MEM_PWR_PWR_STATE 28 29 regRDPCSTX2_RDPCSTX_SCRATCH 0 0x2ae7 1 0 2 RDPCSTX_SCRATCH 0 31 regRDPCSTX2_RDPCSTX_SPARE 0 0x2ae8 1 0 2 RDPCSTX_SPARE 0 31 regRDPCSTX2_RDPCSTX_CNTL2 0 0x2ae9 3 0 2 RDPCS_CR_CONVERT_FIFO_EMPTY 0 0 RDPCS_CR_CONVERT_FIFO_FULL 1 1 RDPCS_PHY_ENC_TYPE_SEL 2 3 regRDPCSTX2_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG 0 0x2aec 3 0 2 RDPCS_DMCU_DPALT_DIS_BLOCK_REG 0 0 RDPCS_DMCU_DPALT_FORCE_TX_CLK_DIS 4 4 RDPCS_DMCU_DPALT_CONTROL_SPARE 8 15 regRDPCSTX2_RDPCSTX_DEBUG_CONFIG 0 0x2aed 7 0 2 RDPCS_DBG_EN 0 0 RDPCS_DBG_SEL_ASYNC_8BIT 4 6 RDPCS_DBG_SEL_ASYNC_SWAP 7 7 RDPCS_DBG_SEL_TEST_CLK 8 12 RDPCS_DBG_CR_COUNT_EXPIRE 15 15 RDPCS_DBG_CR_COUNT_MAX 16 23 RDPCS_DBG_CR_COUNT 24 31 regRDPCSTX2_RDPCSTX_PHY_CNTL0 0 0x2af0 16 0 2 RDPCS_PHY_RESET 0 0 RDPCS_PHY_TCA_PHY_RESET 1 1 RDPCS_PHY_TCA_APB_RESET_N 2 2 RDPCS_PHY_TEST_POWERDOWN 3 3 RDPCS_PHY_DTB_OUT 4 5 RDPCS_PHY_HDMIMODE_ENABLE 8 8 RDPCS_PHY_REF_RANGE 9 13 RDPCS_PHY_RTUNE_REQ 17 17 RDPCS_PHY_RTUNE_ACK 18 18 RDPCS_PHY_CR_PARA_SEL 20 20 RDPCS_PHY_CR_MUX_SEL 21 21 RDPCS_PHY_REF_CLKDET_EN 24 24 RDPCS_PHY_REF_CLKDET_RESULT 25 25 RDPCS_SRAM_INIT_DONE 28 28 RDPCS_SRAM_EXT_LD_DONE 29 29 RDPCS_SRAM_BYPASS 31 31 regRDPCSTX2_RDPCSTX_PHY_CNTL1 0 0x2af1 8 0 2 RDPCS_PHY_PG_MODE_EN 0 0 RDPCS_PHY_PCS_PWR_EN 1 1 RDPCS_PHY_PCS_PWR_STABLE 2 2 RDPCS_PHY_PMA_PWR_EN 3 3 RDPCS_PHY_PMA_PWR_STABLE 4 4 RDPCS_PHY_DP_PG_RESET 5 5 RDPCS_PHY_ANA_PWR_EN 6 6 RDPCS_PHY_ANA_PWR_STABLE 7 7 regRDPCSTX2_RDPCSTX_PHY_CNTL2 0 0x2af2 9 0 2 RDPCS_PHY_DP4_POR 3 3 RDPCS_PHY_DP_LANE0_RX2TX_PAR_LB_EN 4 4 RDPCS_PHY_DP_LANE1_RX2TX_PAR_LB_EN 5 5 RDPCS_PHY_DP_LANE2_RX2TX_PAR_LB_EN 6 6 RDPCS_PHY_DP_LANE3_RX2TX_PAR_LB_EN 7 7 RDPCS_PHY_DP_LANE0_TX2RX_SER_LB_EN 8 8 RDPCS_PHY_DP_LANE1_TX2RX_SER_LB_EN 9 9 RDPCS_PHY_DP_LANE2_TX2RX_SER_LB_EN 10 10 RDPCS_PHY_DP_LANE3_TX2RX_SER_LB_EN 11 11 regRDPCSTX2_RDPCSTX_PHY_CNTL3 0 0x2af3 24 0 2 RDPCS_PHY_DP_TX0_RESET 0 0 RDPCS_PHY_DP_TX0_DISABLE 1 1 RDPCS_PHY_DP_TX0_CLK_RDY 2 2 RDPCS_PHY_DP_TX0_DATA_EN 3 3 RDPCS_PHY_DP_TX0_REQ 4 4 RDPCS_PHY_DP_TX0_ACK 5 5 RDPCS_PHY_DP_TX1_RESET 8 8 RDPCS_PHY_DP_TX1_DISABLE 9 9 RDPCS_PHY_DP_TX1_CLK_RDY 10 10 RDPCS_PHY_DP_TX1_DATA_EN 11 11 RDPCS_PHY_DP_TX1_REQ 12 12 RDPCS_PHY_DP_TX1_ACK 13 13 RDPCS_PHY_DP_TX2_RESET 16 16 RDPCS_PHY_DP_TX2_DISABLE 17 17 RDPCS_PHY_DP_TX2_CLK_RDY 18 18 RDPCS_PHY_DP_TX2_DATA_EN 19 19 RDPCS_PHY_DP_TX2_REQ 20 20 RDPCS_PHY_DP_TX2_ACK 21 21 RDPCS_PHY_DP_TX3_RESET 24 24 RDPCS_PHY_DP_TX3_DISABLE 25 25 RDPCS_PHY_DP_TX3_CLK_RDY 26 26 RDPCS_PHY_DP_TX3_DATA_EN 27 27 RDPCS_PHY_DP_TX3_REQ 28 28 RDPCS_PHY_DP_TX3_ACK 29 29 regRDPCSTX2_RDPCSTX_PHY_CNTL4 0 0x2af4 16 0 2 RDPCS_PHY_DP_TX0_TERM_CTRL 0 2 RDPCS_PHY_DP_TX0_INVERT 4 4 RDPCS_PHY_DP_TX0_BYPASS_EQ_CALC 6 6 RDPCS_PHY_DP_TX0_HP_PROT_EN 7 7 RDPCS_PHY_DP_TX1_TERM_CTRL 8 10 RDPCS_PHY_DP_TX1_INVERT 12 12 RDPCS_PHY_DP_TX1_BYPASS_EQ_CALC 14 14 RDPCS_PHY_DP_TX1_HP_PROT_EN 15 15 RDPCS_PHY_DP_TX2_TERM_CTRL 16 18 RDPCS_PHY_DP_TX2_INVERT 20 20 RDPCS_PHY_DP_TX2_BYPASS_EQ_CALC 22 22 RDPCS_PHY_DP_TX2_HP_PROT_EN 23 23 RDPCS_PHY_DP_TX3_TERM_CTRL 24 26 RDPCS_PHY_DP_TX3_INVERT 28 28 RDPCS_PHY_DP_TX3_BYPASS_EQ_CALC 30 30 RDPCS_PHY_DP_TX3_HP_PROT_EN 31 31 regRDPCSTX2_RDPCSTX_PHY_CNTL5 0 0x2af5 20 0 2 RDPCS_PHY_DP_TX0_LPD 0 0 RDPCS_PHY_DP_TX0_RATE 1 3 RDPCS_PHY_DP_TX0_WIDTH 4 5 RDPCS_PHY_DP_TX0_DETRX_REQ 6 6 RDPCS_PHY_DP_TX0_DETRX_RESULT 7 7 RDPCS_PHY_DP_TX1_LPD 8 8 RDPCS_PHY_DP_TX1_RATE 9 11 RDPCS_PHY_DP_TX1_WIDTH 12 13 RDPCS_PHY_DP_TX1_DETRX_REQ 14 14 RDPCS_PHY_DP_TX1_DETRX_RESULT 15 15 RDPCS_PHY_DP_TX2_LPD 16 16 RDPCS_PHY_DP_TX2_RATE 17 19 RDPCS_PHY_DP_TX2_WIDTH 20 21 RDPCS_PHY_DP_TX2_DETRX_REQ 22 22 RDPCS_PHY_DP_TX2_DETRX_RESULT 23 23 RDPCS_PHY_DP_TX3_LPD 24 24 RDPCS_PHY_DP_TX3_RATE 25 27 RDPCS_PHY_DP_TX3_WIDTH 28 29 RDPCS_PHY_DP_TX3_DETRX_REQ 30 30 RDPCS_PHY_DP_TX3_DETRX_RESULT 31 31 regRDPCSTX2_RDPCSTX_PHY_CNTL6 0 0x2af6 13 0 2 RDPCS_PHY_DP_TX0_PSTATE 0 1 RDPCS_PHY_DP_TX0_MPLL_EN 2 2 RDPCS_PHY_DP_TX1_PSTATE 4 5 RDPCS_PHY_DP_TX1_MPLL_EN 6 6 RDPCS_PHY_DP_TX2_PSTATE 8 9 RDPCS_PHY_DP_TX2_MPLL_EN 10 10 RDPCS_PHY_DP_TX3_PSTATE 12 13 RDPCS_PHY_DP_TX3_MPLL_EN 14 14 RDPCS_PHY_DPALT_DP4 16 16 RDPCS_PHY_DPALT_DISABLE 17 17 RDPCS_PHY_DPALT_DISABLE_ACK 18 18 RDPCS_PHY_DP_REF_CLK_EN 19 19 RDPCS_PHY_DP_REF_CLK_REQ 20 20 regRDPCSTX2_RDPCSTX_PHY_CNTL7 0 0x2af7 2 0 2 RDPCS_PHY_DP_MPLLB_FRACN_DEN 0 15 RDPCS_PHY_DP_MPLLB_FRACN_QUOT 16 31 regRDPCSTX2_RDPCSTX_PHY_CNTL8 0 0x2af8 1 0 2 RDPCS_PHY_DP_MPLLB_SSC_PEAK 0 19 regRDPCSTX2_RDPCSTX_PHY_CNTL9 0 0x2af9 2 0 2 RDPCS_PHY_DP_MPLLB_SSC_STEPSIZE 0 20 RDPCS_PHY_DP_MPLLB_SSC_UP_SPREAD 24 24 regRDPCSTX2_RDPCSTX_PHY_CNTL10 0 0x2afa 1 0 2 RDPCS_PHY_DP_MPLLB_FRACN_REM 0 15 regRDPCSTX2_RDPCSTX_PHY_CNTL11 0 0x2afb 4 0 2 RDPCS_PHY_DP_MPLLB_MULTIPLIER 4 15 RDPCS_PHY_HDMI_MPLLB_HDMI_DIV 16 18 RDPCS_PHY_DP_REF_CLK_MPLLB_DIV 20 22 RDPCS_PHY_HDMI_MPLLB_HDMI_PIXEL_CLK_DIV 24 25 regRDPCSTX2_RDPCSTX_PHY_CNTL12 0 0x2afc 5 0 2 RDPCS_PHY_DP_MPLLB_DIV5_CLK_EN 0 0 RDPCS_PHY_DP_MPLLB_WORD_DIV2_EN 2 2 RDPCS_PHY_DP_MPLLB_TX_CLK_DIV 4 6 RDPCS_PHY_DP_MPLLB_STATE 7 7 RDPCS_PHY_DP_MPLLB_SSC_EN 8 8 regRDPCSTX2_RDPCSTX_PHY_CNTL13 0 0x2afd 4 0 2 RDPCS_PHY_DP_MPLLB_DIV_MULTIPLIER 20 27 RDPCS_PHY_DP_MPLLB_DIV_CLK_EN 28 28 RDPCS_PHY_DP_MPLLB_FORCE_EN 29 29 RDPCS_PHY_DP_MPLLB_INIT_CAL_DISABLE 30 30 regRDPCSTX2_RDPCSTX_PHY_CNTL14 0 0x2afe 3 0 2 RDPCS_PHY_DP_MPLLB_CAL_FORCE 0 0 RDPCS_PHY_DP_MPLLB_FRACN_EN 24 24 RDPCS_PHY_DP_MPLLB_PMIX_EN 28 28 regRDPCSTX2_RDPCSTX_PHY_FUSE0 0 0x2aff 7 0 2 RDPCS_PHY_DP_TX0_EQ_MAIN 0 5 RDPCS_PHY_DP_TX0_EQ_PRE 6 11 RDPCS_PHY_DP_TX0_EQ_POST 12 17 RDPCS_PHY_DP_MPLLB_V2I 18 19 RDPCS_PHY_DP_MPLLB_FREQ_VCO 20 21 RDPCS_PHY_DP_MPLLB_CP_INT_GS 22 28 RDPCS_PHY_RX_VREF_CTRL 29 31 regRDPCSTX2_RDPCSTX_PHY_FUSE1 0 0x2b00 5 0 2 RDPCS_PHY_DP_TX1_EQ_MAIN 0 5 RDPCS_PHY_DP_TX1_EQ_PRE 6 11 RDPCS_PHY_DP_TX1_EQ_POST 12 17 RDPCS_PHY_DP_MPLLB_CP_INT 18 24 RDPCS_PHY_DP_MPLLB_CP_PROP 25 31 regRDPCSTX2_RDPCSTX_PHY_FUSE2 0 0x2b01 4 0 2 RDPCS_PHY_DP_TX2_EQ_MAIN 0 5 RDPCS_PHY_DP_TX2_EQ_PRE 6 11 RDPCS_PHY_DP_TX2_EQ_POST 12 17 RDPCS_PHY_DP_MPLLB_CP_PROP_GS 23 29 regRDPCSTX2_RDPCSTX_PHY_FUSE3 0 0x2b02 7 0 2 RDPCS_PHY_DP_TX3_EQ_MAIN 0 5 RDPCS_PHY_DP_TX3_EQ_PRE 6 11 RDPCS_PHY_DP_TX3_EQ_POST 12 17 RDPCS_PHY_DCO_FINETUNE 18 23 RDPCS_PHY_DCO_RANGE 24 25 RDPCS_PHY_TX_VBOOST_LVL 26 28 RDPCS_PHY_SUP_RX_VCO_VREF_SEL 29 31 regRDPCSTX2_RDPCSTX_PHY_RX_LD_VAL 0 0x2b03 3 0 2 RDPCS_PHY_RX_REF_LD_VAL 0 6 RDPCS_PHY_RX_CDR_VCO_LOWFREQ 7 7 RDPCS_PHY_RX_VCO_LD_VAL 8 20 regRDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL3 0 0x2b04 24 0 2 RDPCS_PHY_DP_TX0_RESET_RESERVED 0 0 RDPCS_PHY_DP_TX0_DISABLE_RESERVED 1 1 RDPCS_PHY_DP_TX0_CLK_RDY_RESERVED 2 2 RDPCS_PHY_DP_TX0_DATA_EN_RESERVED 3 3 RDPCS_PHY_DP_TX0_REQ_RESERVED 4 4 RDPCS_PHY_DP_TX0_ACK_RESERVED 5 5 RDPCS_PHY_DP_TX1_RESET_RESERVED 8 8 RDPCS_PHY_DP_TX1_DISABLE_RESERVED 9 9 RDPCS_PHY_DP_TX1_CLK_RDY_RESERVED 10 10 RDPCS_PHY_DP_TX1_DATA_EN_RESERVED 11 11 RDPCS_PHY_DP_TX1_REQ_RESERVED 12 12 RDPCS_PHY_DP_TX1_ACK_RESERVED 13 13 RDPCS_PHY_DP_TX2_RESET_RESERVED 16 16 RDPCS_PHY_DP_TX2_DISABLE_RESERVED 17 17 RDPCS_PHY_DP_TX2_CLK_RDY_RESERVED 18 18 RDPCS_PHY_DP_TX2_DATA_EN_RESERVED 19 19 RDPCS_PHY_DP_TX2_REQ_RESERVED 20 20 RDPCS_PHY_DP_TX2_ACK_RESERVED 21 21 RDPCS_PHY_DP_TX3_RESET_RESERVED 24 24 RDPCS_PHY_DP_TX3_DISABLE_RESERVED 25 25 RDPCS_PHY_DP_TX3_CLK_RDY_RESERVED 26 26 RDPCS_PHY_DP_TX3_DATA_EN_RESERVED 27 27 RDPCS_PHY_DP_TX3_REQ_RESERVED 28 28 RDPCS_PHY_DP_TX3_ACK_RESERVED 29 29 regRDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL6 0 0x2b05 13 0 2 RDPCS_PHY_DP_TX0_PSTATE_RESERVED 0 1 RDPCS_PHY_DP_TX0_MPLL_EN_RESERVED 2 2 RDPCS_PHY_DP_TX1_PSTATE_RESERVED 4 5 RDPCS_PHY_DP_TX1_MPLL_EN_RESERVED 6 6 RDPCS_PHY_DP_TX2_PSTATE_RESERVED 8 9 RDPCS_PHY_DP_TX2_MPLL_EN_RESERVED 10 10 RDPCS_PHY_DP_TX3_PSTATE_RESERVED 12 13 RDPCS_PHY_DP_TX3_MPLL_EN_RESERVED 14 14 RDPCS_PHY_DPALT_DP4_RESERVED 16 16 RDPCS_PHY_DPALT_DISABLE_RESERVED 17 17 RDPCS_PHY_DPALT_DISABLE_ACK_RESERVED 18 18 RDPCS_PHY_DP_REF_CLK_EN_RESERVED 19 19 RDPCS_PHY_DP_REF_CLK_REQ_RESERVED 20 20 regRDPCSTX2_RDPCSTX_DPALT_CONTROL_REG 0 0x2b06 3 0 2 RDPCS_ALLOW_DRIVER_ACCESS 0 0 RDPCS_DRIVER_ACCESS_BLOCKED 4 4 RDPCS_DPALT_CONTROL_SPARE 8 15 regRDPCSTX2_RDPCSTX_PHY_CNTL15 0 0x2b08 6 0 2 RDPCS_PHY_SSTX_VREGDRV_BYP 0 0 RDPCS_PHY_DP_TX0_VREGDRV_BYP 16 16 RDPCS_PHY_DP_TX1_VREGDRV_BYP 17 17 RDPCS_PHY_DP_TX2_VREGDRV_BYP 18 18 RDPCS_PHY_DP_TX3_VREGDRV_BYP 19 19 RDPCS_PHY_SUP_PRE_HP 20 20 regRDPCSTX2_RDPCSTX_PHY_CNTL16 0 0x2b09 5 0 2 RDPCS_PHY_DP_TX0_OUT_GENERIC_BUS 0 4 RDPCS_PHY_DP_TX1_OUT_GENERIC_BUS 6 10 RDPCS_PHY_DP_TX2_OUT_GENERIC_BUS 12 16 RDPCS_PHY_DP_TX3_OUT_GENERIC_BUS 18 22 RDPCS_PHY_CMN_OUT_GENERIC_BUS 24 28 regRDPCSTX2_RDPCSTX_PHY_CNTL17 0 0x2b0a 5 0 2 RDPCS_PHY_DP_TX0_IN_GENERIC_BUS 0 4 RDPCS_PHY_DP_TX1_IN_GENERIC_BUS 6 10 RDPCS_PHY_DP_TX2_IN_GENERIC_BUS 12 16 RDPCS_PHY_DP_TX3_IN_GENERIC_BUS 18 22 RDPCS_PHY_CMN_IN_GENERIC_BUS 24 28 regRDPCSTX2_RDPCSTX_DEBUG_CONFIG2 0 0x2b0b 5 0 2 RDPCS_DBG_OCLA_SRC0 0 2 RDPCS_DBG_OCLA_SRC1 4 6 RDPCS_DBG_OCLA_SRC2 8 10 RDPCS_DBG_OCLA_SRC3 12 14 RDPCS_DBG_OCLA_VALID_REPLACE_MSB 16 16 regRDPCSTX2_RDPCS_CNTL3 0 0x2b0c 4 0 2 TX_LANE0_BYTE_ORDER_CHANGE 0 7 TX_LANE1_BYTE_ORDER_CHANGE 8 15 TX_LANE2_BYTE_ORDER_CHANGE 16 23 TX_LANE3_BYTE_ORDER_CHANGE 24 31 regRDPCSTX2_RDPCS_TX_PLL_UPDATE_ADDR_OVRRD 0 0x2b0d 1 0 2 RDPCS_PLL_UPDATE_ADDR_OVRRD 0 17 regRDPCSTX2_RDPCS_TX_PLL_UPDATE_DATA_OVRRD 0 0x2b0e 1 0 2 RDPCS_PLL_UPDATE_DATA_OVRRD 0 31 regRDPCSTX3_RDPCSTX_CNTL 0 0x2bb8 24 0 2 RDPCS_CBUS_SOFT_RESET 0 0 RDPCS_SRAM_SOFT_RESET 1 1 TX_LANE0_BIT_ORDER_REVERSE_BEFORE_PACK 4 4 TX_LANE1_BIT_ORDER_REVERSE_BEFORE_PACK 5 5 TX_LANE2_BIT_ORDER_REVERSE_BEFORE_PACK 6 6 TX_LANE3_BIT_ORDER_REVERSE_BEFORE_PACK 7 7 RDPCS_INTERRUPT_MASK 8 8 RDPCS_TX_PLL_UPDATE_REQ 9 9 RDPCS_TX_PLL_UPDATE_PENDING 10 10 RDPCS_TX_FIFO_LANE0_EN 12 12 RDPCS_TX_FIFO_LANE1_EN 13 13 RDPCS_TX_FIFO_LANE2_EN 14 14 RDPCS_TX_FIFO_LANE3_EN 15 15 TX_LANE0_PACK_FROM_MSB 16 16 TX_LANE1_PACK_FROM_MSB 17 17 TX_LANE2_PACK_FROM_MSB 18 18 TX_LANE3_PACK_FROM_MSB 19 19 RDPCS_TX_FIFO_RD_START_DELAY 20 24 RDPCS_TX_FIFO_EN 25 25 RDPCS_TX_FIFO_START 26 26 RDPCS_CR_REGISTER_BLOCK_EN 28 28 RDPCS_NON_DPALT_REGISTER_BLOCK_EN 29 29 RDPCS_DPALT_BLOCK_STATUS 30 30 RDPCS_TX_SOFT_RESET 31 31 regRDPCSTX3_RDPCSTX_CLOCK_CNTL 0 0x2bb9 16 0 2 RDPCS_EXT_REFCLK_EN 0 0 RDPCS_TX0_CLK_EN 4 4 RDPCS_TX1_CLK_EN 5 5 RDPCS_TX2_CLK_EN 6 6 RDPCS_TX3_CLK_EN 7 7 RDPCS_TX_CLK_GATE_DIS 8 8 RDPCS_TX_CLK_EN 9 9 RDPCS_TX_CLK_CLOCK_ON 10 10 RDPCS_TX_PHY_REF_ALT_CLK_EN 11 11 RDPCS_SRAMCLK_GATE_DIS 12 12 RDPCS_SRAMCLK_EN 13 13 RDPCS_SRAMCLK_CLOCK_ON 14 14 RDPCS_SRAMCLK_BYPASS 16 16 RDPCS_OCLACLK_GATE_DIS 20 20 RDPCS_OCLACLK_EN 21 21 RDPCS_OCLACLK_CLOCK_ON 22 22 regRDPCSTX3_RDPCSTX_INTERRUPT_CONTROL 0 0x2bba 15 0 2 RDPCS_REG_FIFO_OVERFLOW 0 0 RDPCS_DPALT_DISABLE_TOGGLE 1 1 RDPCS_DPALT_4LANE_TOGGLE 2 2 RDPCS_TX0_FIFO_ERROR 4 4 RDPCS_TX1_FIFO_ERROR 5 5 RDPCS_TX2_FIFO_ERROR 6 6 RDPCS_TX3_FIFO_ERROR 7 7 RDPCS_REG_ERROR_CLR 8 8 RDPCS_DPALT_DISABLE_TOGGLE_CLR 9 9 RDPCS_DPALT_4LANE_TOGGLE_CLR 10 10 RDPCS_TX_ERROR_CLR 12 12 RDPCS_REG_FIFO_ERROR_MASK 16 16 RDPCS_DPALT_DISABLE_TOGGLE_MASK 17 17 RDPCS_DPALT_4LANE_TOGGLE_MASK 18 18 RDPCS_TX_FIFO_ERROR_MASK 20 20 regRDPCSTX3_RDPCS_TX_PLL_UPDATE_DATA 0 0x2bbb 1 0 2 RDPCS_PLL_UPDATE_DATA 0 0 regRDPCSTX3_RDPCS_TX_CR_ADDR 0 0x2bbc 1 0 2 RDPCS_TX_CR_ADDR 0 15 regRDPCSTX3_RDPCS_TX_CR_DATA 0 0x2bbd 1 0 2 RDPCS_TX_CR_DATA 0 15 regRDPCSTX3_RDPCS_TX_SRAM_CNTL 0 0x2bbe 3 0 2 RDPCS_MEM_PWR_DIS 20 20 RDPCS_MEM_PWR_FORCE 24 25 RDPCS_MEM_PWR_PWR_STATE 28 29 regRDPCSTX3_RDPCSTX_SCRATCH 0 0x2bbf 1 0 2 RDPCSTX_SCRATCH 0 31 regRDPCSTX3_RDPCSTX_SPARE 0 0x2bc0 1 0 2 RDPCSTX_SPARE 0 31 regRDPCSTX3_RDPCSTX_CNTL2 0 0x2bc1 3 0 2 RDPCS_CR_CONVERT_FIFO_EMPTY 0 0 RDPCS_CR_CONVERT_FIFO_FULL 1 1 RDPCS_PHY_ENC_TYPE_SEL 2 3 regRDPCSTX3_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG 0 0x2bc4 3 0 2 RDPCS_DMCU_DPALT_DIS_BLOCK_REG 0 0 RDPCS_DMCU_DPALT_FORCE_TX_CLK_DIS 4 4 RDPCS_DMCU_DPALT_CONTROL_SPARE 8 15 regRDPCSTX3_RDPCSTX_DEBUG_CONFIG 0 0x2bc5 7 0 2 RDPCS_DBG_EN 0 0 RDPCS_DBG_SEL_ASYNC_8BIT 4 6 RDPCS_DBG_SEL_ASYNC_SWAP 7 7 RDPCS_DBG_SEL_TEST_CLK 8 12 RDPCS_DBG_CR_COUNT_EXPIRE 15 15 RDPCS_DBG_CR_COUNT_MAX 16 23 RDPCS_DBG_CR_COUNT 24 31 regRDPCSTX3_RDPCSTX_PHY_CNTL0 0 0x2bc8 16 0 2 RDPCS_PHY_RESET 0 0 RDPCS_PHY_TCA_PHY_RESET 1 1 RDPCS_PHY_TCA_APB_RESET_N 2 2 RDPCS_PHY_TEST_POWERDOWN 3 3 RDPCS_PHY_DTB_OUT 4 5 RDPCS_PHY_HDMIMODE_ENABLE 8 8 RDPCS_PHY_REF_RANGE 9 13 RDPCS_PHY_RTUNE_REQ 17 17 RDPCS_PHY_RTUNE_ACK 18 18 RDPCS_PHY_CR_PARA_SEL 20 20 RDPCS_PHY_CR_MUX_SEL 21 21 RDPCS_PHY_REF_CLKDET_EN 24 24 RDPCS_PHY_REF_CLKDET_RESULT 25 25 RDPCS_SRAM_INIT_DONE 28 28 RDPCS_SRAM_EXT_LD_DONE 29 29 RDPCS_SRAM_BYPASS 31 31 regRDPCSTX3_RDPCSTX_PHY_CNTL1 0 0x2bc9 8 0 2 RDPCS_PHY_PG_MODE_EN 0 0 RDPCS_PHY_PCS_PWR_EN 1 1 RDPCS_PHY_PCS_PWR_STABLE 2 2 RDPCS_PHY_PMA_PWR_EN 3 3 RDPCS_PHY_PMA_PWR_STABLE 4 4 RDPCS_PHY_DP_PG_RESET 5 5 RDPCS_PHY_ANA_PWR_EN 6 6 RDPCS_PHY_ANA_PWR_STABLE 7 7 regRDPCSTX3_RDPCSTX_PHY_CNTL2 0 0x2bca 9 0 2 RDPCS_PHY_DP4_POR 3 3 RDPCS_PHY_DP_LANE0_RX2TX_PAR_LB_EN 4 4 RDPCS_PHY_DP_LANE1_RX2TX_PAR_LB_EN 5 5 RDPCS_PHY_DP_LANE2_RX2TX_PAR_LB_EN 6 6 RDPCS_PHY_DP_LANE3_RX2TX_PAR_LB_EN 7 7 RDPCS_PHY_DP_LANE0_TX2RX_SER_LB_EN 8 8 RDPCS_PHY_DP_LANE1_TX2RX_SER_LB_EN 9 9 RDPCS_PHY_DP_LANE2_TX2RX_SER_LB_EN 10 10 RDPCS_PHY_DP_LANE3_TX2RX_SER_LB_EN 11 11 regRDPCSTX3_RDPCSTX_PHY_CNTL3 0 0x2bcb 24 0 2 RDPCS_PHY_DP_TX0_RESET 0 0 RDPCS_PHY_DP_TX0_DISABLE 1 1 RDPCS_PHY_DP_TX0_CLK_RDY 2 2 RDPCS_PHY_DP_TX0_DATA_EN 3 3 RDPCS_PHY_DP_TX0_REQ 4 4 RDPCS_PHY_DP_TX0_ACK 5 5 RDPCS_PHY_DP_TX1_RESET 8 8 RDPCS_PHY_DP_TX1_DISABLE 9 9 RDPCS_PHY_DP_TX1_CLK_RDY 10 10 RDPCS_PHY_DP_TX1_DATA_EN 11 11 RDPCS_PHY_DP_TX1_REQ 12 12 RDPCS_PHY_DP_TX1_ACK 13 13 RDPCS_PHY_DP_TX2_RESET 16 16 RDPCS_PHY_DP_TX2_DISABLE 17 17 RDPCS_PHY_DP_TX2_CLK_RDY 18 18 RDPCS_PHY_DP_TX2_DATA_EN 19 19 RDPCS_PHY_DP_TX2_REQ 20 20 RDPCS_PHY_DP_TX2_ACK 21 21 RDPCS_PHY_DP_TX3_RESET 24 24 RDPCS_PHY_DP_TX3_DISABLE 25 25 RDPCS_PHY_DP_TX3_CLK_RDY 26 26 RDPCS_PHY_DP_TX3_DATA_EN 27 27 RDPCS_PHY_DP_TX3_REQ 28 28 RDPCS_PHY_DP_TX3_ACK 29 29 regRDPCSTX3_RDPCSTX_PHY_CNTL4 0 0x2bcc 16 0 2 RDPCS_PHY_DP_TX0_TERM_CTRL 0 2 RDPCS_PHY_DP_TX0_INVERT 4 4 RDPCS_PHY_DP_TX0_BYPASS_EQ_CALC 6 6 RDPCS_PHY_DP_TX0_HP_PROT_EN 7 7 RDPCS_PHY_DP_TX1_TERM_CTRL 8 10 RDPCS_PHY_DP_TX1_INVERT 12 12 RDPCS_PHY_DP_TX1_BYPASS_EQ_CALC 14 14 RDPCS_PHY_DP_TX1_HP_PROT_EN 15 15 RDPCS_PHY_DP_TX2_TERM_CTRL 16 18 RDPCS_PHY_DP_TX2_INVERT 20 20 RDPCS_PHY_DP_TX2_BYPASS_EQ_CALC 22 22 RDPCS_PHY_DP_TX2_HP_PROT_EN 23 23 RDPCS_PHY_DP_TX3_TERM_CTRL 24 26 RDPCS_PHY_DP_TX3_INVERT 28 28 RDPCS_PHY_DP_TX3_BYPASS_EQ_CALC 30 30 RDPCS_PHY_DP_TX3_HP_PROT_EN 31 31 regRDPCSTX3_RDPCSTX_PHY_CNTL5 0 0x2bcd 20 0 2 RDPCS_PHY_DP_TX0_LPD 0 0 RDPCS_PHY_DP_TX0_RATE 1 3 RDPCS_PHY_DP_TX0_WIDTH 4 5 RDPCS_PHY_DP_TX0_DETRX_REQ 6 6 RDPCS_PHY_DP_TX0_DETRX_RESULT 7 7 RDPCS_PHY_DP_TX1_LPD 8 8 RDPCS_PHY_DP_TX1_RATE 9 11 RDPCS_PHY_DP_TX1_WIDTH 12 13 RDPCS_PHY_DP_TX1_DETRX_REQ 14 14 RDPCS_PHY_DP_TX1_DETRX_RESULT 15 15 RDPCS_PHY_DP_TX2_LPD 16 16 RDPCS_PHY_DP_TX2_RATE 17 19 RDPCS_PHY_DP_TX2_WIDTH 20 21 RDPCS_PHY_DP_TX2_DETRX_REQ 22 22 RDPCS_PHY_DP_TX2_DETRX_RESULT 23 23 RDPCS_PHY_DP_TX3_LPD 24 24 RDPCS_PHY_DP_TX3_RATE 25 27 RDPCS_PHY_DP_TX3_WIDTH 28 29 RDPCS_PHY_DP_TX3_DETRX_REQ 30 30 RDPCS_PHY_DP_TX3_DETRX_RESULT 31 31 regRDPCSTX3_RDPCSTX_PHY_CNTL6 0 0x2bce 13 0 2 RDPCS_PHY_DP_TX0_PSTATE 0 1 RDPCS_PHY_DP_TX0_MPLL_EN 2 2 RDPCS_PHY_DP_TX1_PSTATE 4 5 RDPCS_PHY_DP_TX1_MPLL_EN 6 6 RDPCS_PHY_DP_TX2_PSTATE 8 9 RDPCS_PHY_DP_TX2_MPLL_EN 10 10 RDPCS_PHY_DP_TX3_PSTATE 12 13 RDPCS_PHY_DP_TX3_MPLL_EN 14 14 RDPCS_PHY_DPALT_DP4 16 16 RDPCS_PHY_DPALT_DISABLE 17 17 RDPCS_PHY_DPALT_DISABLE_ACK 18 18 RDPCS_PHY_DP_REF_CLK_EN 19 19 RDPCS_PHY_DP_REF_CLK_REQ 20 20 regRDPCSTX3_RDPCSTX_PHY_CNTL7 0 0x2bcf 2 0 2 RDPCS_PHY_DP_MPLLB_FRACN_DEN 0 15 RDPCS_PHY_DP_MPLLB_FRACN_QUOT 16 31 regRDPCSTX3_RDPCSTX_PHY_CNTL8 0 0x2bd0 1 0 2 RDPCS_PHY_DP_MPLLB_SSC_PEAK 0 19 regRDPCSTX3_RDPCSTX_PHY_CNTL9 0 0x2bd1 2 0 2 RDPCS_PHY_DP_MPLLB_SSC_STEPSIZE 0 20 RDPCS_PHY_DP_MPLLB_SSC_UP_SPREAD 24 24 regRDPCSTX3_RDPCSTX_PHY_CNTL10 0 0x2bd2 1 0 2 RDPCS_PHY_DP_MPLLB_FRACN_REM 0 15 regRDPCSTX3_RDPCSTX_PHY_CNTL11 0 0x2bd3 4 0 2 RDPCS_PHY_DP_MPLLB_MULTIPLIER 4 15 RDPCS_PHY_HDMI_MPLLB_HDMI_DIV 16 18 RDPCS_PHY_DP_REF_CLK_MPLLB_DIV 20 22 RDPCS_PHY_HDMI_MPLLB_HDMI_PIXEL_CLK_DIV 24 25 regRDPCSTX3_RDPCSTX_PHY_CNTL12 0 0x2bd4 5 0 2 RDPCS_PHY_DP_MPLLB_DIV5_CLK_EN 0 0 RDPCS_PHY_DP_MPLLB_WORD_DIV2_EN 2 2 RDPCS_PHY_DP_MPLLB_TX_CLK_DIV 4 6 RDPCS_PHY_DP_MPLLB_STATE 7 7 RDPCS_PHY_DP_MPLLB_SSC_EN 8 8 regRDPCSTX3_RDPCSTX_PHY_CNTL13 0 0x2bd5 4 0 2 RDPCS_PHY_DP_MPLLB_DIV_MULTIPLIER 20 27 RDPCS_PHY_DP_MPLLB_DIV_CLK_EN 28 28 RDPCS_PHY_DP_MPLLB_FORCE_EN 29 29 RDPCS_PHY_DP_MPLLB_INIT_CAL_DISABLE 30 30 regRDPCSTX3_RDPCSTX_PHY_CNTL14 0 0x2bd6 3 0 2 RDPCS_PHY_DP_MPLLB_CAL_FORCE 0 0 RDPCS_PHY_DP_MPLLB_FRACN_EN 24 24 RDPCS_PHY_DP_MPLLB_PMIX_EN 28 28 regRDPCSTX3_RDPCSTX_PHY_FUSE0 0 0x2bd7 7 0 2 RDPCS_PHY_DP_TX0_EQ_MAIN 0 5 RDPCS_PHY_DP_TX0_EQ_PRE 6 11 RDPCS_PHY_DP_TX0_EQ_POST 12 17 RDPCS_PHY_DP_MPLLB_V2I 18 19 RDPCS_PHY_DP_MPLLB_FREQ_VCO 20 21 RDPCS_PHY_DP_MPLLB_CP_INT_GS 22 28 RDPCS_PHY_RX_VREF_CTRL 29 31 regRDPCSTX3_RDPCSTX_PHY_FUSE1 0 0x2bd8 5 0 2 RDPCS_PHY_DP_TX1_EQ_MAIN 0 5 RDPCS_PHY_DP_TX1_EQ_PRE 6 11 RDPCS_PHY_DP_TX1_EQ_POST 12 17 RDPCS_PHY_DP_MPLLB_CP_INT 18 24 RDPCS_PHY_DP_MPLLB_CP_PROP 25 31 regRDPCSTX3_RDPCSTX_PHY_FUSE2 0 0x2bd9 4 0 2 RDPCS_PHY_DP_TX2_EQ_MAIN 0 5 RDPCS_PHY_DP_TX2_EQ_PRE 6 11 RDPCS_PHY_DP_TX2_EQ_POST 12 17 RDPCS_PHY_DP_MPLLB_CP_PROP_GS 23 29 regRDPCSTX3_RDPCSTX_PHY_FUSE3 0 0x2bda 7 0 2 RDPCS_PHY_DP_TX3_EQ_MAIN 0 5 RDPCS_PHY_DP_TX3_EQ_PRE 6 11 RDPCS_PHY_DP_TX3_EQ_POST 12 17 RDPCS_PHY_DCO_FINETUNE 18 23 RDPCS_PHY_DCO_RANGE 24 25 RDPCS_PHY_TX_VBOOST_LVL 26 28 RDPCS_PHY_SUP_RX_VCO_VREF_SEL 29 31 regRDPCSTX3_RDPCSTX_PHY_RX_LD_VAL 0 0x2bdb 3 0 2 RDPCS_PHY_RX_REF_LD_VAL 0 6 RDPCS_PHY_RX_CDR_VCO_LOWFREQ 7 7 RDPCS_PHY_RX_VCO_LD_VAL 8 20 regRDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL3 0 0x2bdc 24 0 2 RDPCS_PHY_DP_TX0_RESET_RESERVED 0 0 RDPCS_PHY_DP_TX0_DISABLE_RESERVED 1 1 RDPCS_PHY_DP_TX0_CLK_RDY_RESERVED 2 2 RDPCS_PHY_DP_TX0_DATA_EN_RESERVED 3 3 RDPCS_PHY_DP_TX0_REQ_RESERVED 4 4 RDPCS_PHY_DP_TX0_ACK_RESERVED 5 5 RDPCS_PHY_DP_TX1_RESET_RESERVED 8 8 RDPCS_PHY_DP_TX1_DISABLE_RESERVED 9 9 RDPCS_PHY_DP_TX1_CLK_RDY_RESERVED 10 10 RDPCS_PHY_DP_TX1_DATA_EN_RESERVED 11 11 RDPCS_PHY_DP_TX1_REQ_RESERVED 12 12 RDPCS_PHY_DP_TX1_ACK_RESERVED 13 13 RDPCS_PHY_DP_TX2_RESET_RESERVED 16 16 RDPCS_PHY_DP_TX2_DISABLE_RESERVED 17 17 RDPCS_PHY_DP_TX2_CLK_RDY_RESERVED 18 18 RDPCS_PHY_DP_TX2_DATA_EN_RESERVED 19 19 RDPCS_PHY_DP_TX2_REQ_RESERVED 20 20 RDPCS_PHY_DP_TX2_ACK_RESERVED 21 21 RDPCS_PHY_DP_TX3_RESET_RESERVED 24 24 RDPCS_PHY_DP_TX3_DISABLE_RESERVED 25 25 RDPCS_PHY_DP_TX3_CLK_RDY_RESERVED 26 26 RDPCS_PHY_DP_TX3_DATA_EN_RESERVED 27 27 RDPCS_PHY_DP_TX3_REQ_RESERVED 28 28 RDPCS_PHY_DP_TX3_ACK_RESERVED 29 29 regRDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL6 0 0x2bdd 13 0 2 RDPCS_PHY_DP_TX0_PSTATE_RESERVED 0 1 RDPCS_PHY_DP_TX0_MPLL_EN_RESERVED 2 2 RDPCS_PHY_DP_TX1_PSTATE_RESERVED 4 5 RDPCS_PHY_DP_TX1_MPLL_EN_RESERVED 6 6 RDPCS_PHY_DP_TX2_PSTATE_RESERVED 8 9 RDPCS_PHY_DP_TX2_MPLL_EN_RESERVED 10 10 RDPCS_PHY_DP_TX3_PSTATE_RESERVED 12 13 RDPCS_PHY_DP_TX3_MPLL_EN_RESERVED 14 14 RDPCS_PHY_DPALT_DP4_RESERVED 16 16 RDPCS_PHY_DPALT_DISABLE_RESERVED 17 17 RDPCS_PHY_DPALT_DISABLE_ACK_RESERVED 18 18 RDPCS_PHY_DP_REF_CLK_EN_RESERVED 19 19 RDPCS_PHY_DP_REF_CLK_REQ_RESERVED 20 20 regRDPCSTX3_RDPCSTX_DPALT_CONTROL_REG 0 0x2bde 3 0 2 RDPCS_ALLOW_DRIVER_ACCESS 0 0 RDPCS_DRIVER_ACCESS_BLOCKED 4 4 RDPCS_DPALT_CONTROL_SPARE 8 15 regRDPCSTX3_RDPCSTX_PHY_CNTL15 0 0x2be0 6 0 2 RDPCS_PHY_SSTX_VREGDRV_BYP 0 0 RDPCS_PHY_DP_TX0_VREGDRV_BYP 16 16 RDPCS_PHY_DP_TX1_VREGDRV_BYP 17 17 RDPCS_PHY_DP_TX2_VREGDRV_BYP 18 18 RDPCS_PHY_DP_TX3_VREGDRV_BYP 19 19 RDPCS_PHY_SUP_PRE_HP 20 20 regRDPCSTX3_RDPCSTX_PHY_CNTL16 0 0x2be1 5 0 2 RDPCS_PHY_DP_TX0_OUT_GENERIC_BUS 0 4 RDPCS_PHY_DP_TX1_OUT_GENERIC_BUS 6 10 RDPCS_PHY_DP_TX2_OUT_GENERIC_BUS 12 16 RDPCS_PHY_DP_TX3_OUT_GENERIC_BUS 18 22 RDPCS_PHY_CMN_OUT_GENERIC_BUS 24 28 regRDPCSTX3_RDPCSTX_PHY_CNTL17 0 0x2be2 5 0 2 RDPCS_PHY_DP_TX0_IN_GENERIC_BUS 0 4 RDPCS_PHY_DP_TX1_IN_GENERIC_BUS 6 10 RDPCS_PHY_DP_TX2_IN_GENERIC_BUS 12 16 RDPCS_PHY_DP_TX3_IN_GENERIC_BUS 18 22 RDPCS_PHY_CMN_IN_GENERIC_BUS 24 28 regRDPCSTX3_RDPCSTX_DEBUG_CONFIG2 0 0x2be3 5 0 2 RDPCS_DBG_OCLA_SRC0 0 2 RDPCS_DBG_OCLA_SRC1 4 6 RDPCS_DBG_OCLA_SRC2 8 10 RDPCS_DBG_OCLA_SRC3 12 14 RDPCS_DBG_OCLA_VALID_REPLACE_MSB 16 16 regRDPCSTX3_RDPCS_CNTL3 0 0x2be4 4 0 2 TX_LANE0_BYTE_ORDER_CHANGE 0 7 TX_LANE1_BYTE_ORDER_CHANGE 8 15 TX_LANE2_BYTE_ORDER_CHANGE 16 23 TX_LANE3_BYTE_ORDER_CHANGE 24 31 regRDPCSTX3_RDPCS_TX_PLL_UPDATE_ADDR_OVRRD 0 0x2be5 1 0 2 RDPCS_PLL_UPDATE_ADDR_OVRRD 0 17 regRDPCSTX3_RDPCS_TX_PLL_UPDATE_DATA_OVRRD 0 0x2be6 1 0 2 RDPCS_PLL_UPDATE_DATA_OVRRD 0 31 regRDPCSTX4_RDPCSTX_CNTL 0 0x2c90 24 0 2 RDPCS_CBUS_SOFT_RESET 0 0 RDPCS_SRAM_SOFT_RESET 1 1 TX_LANE0_BIT_ORDER_REVERSE_BEFORE_PACK 4 4 TX_LANE1_BIT_ORDER_REVERSE_BEFORE_PACK 5 5 TX_LANE2_BIT_ORDER_REVERSE_BEFORE_PACK 6 6 TX_LANE3_BIT_ORDER_REVERSE_BEFORE_PACK 7 7 RDPCS_INTERRUPT_MASK 8 8 RDPCS_TX_PLL_UPDATE_REQ 9 9 RDPCS_TX_PLL_UPDATE_PENDING 10 10 RDPCS_TX_FIFO_LANE0_EN 12 12 RDPCS_TX_FIFO_LANE1_EN 13 13 RDPCS_TX_FIFO_LANE2_EN 14 14 RDPCS_TX_FIFO_LANE3_EN 15 15 TX_LANE0_PACK_FROM_MSB 16 16 TX_LANE1_PACK_FROM_MSB 17 17 TX_LANE2_PACK_FROM_MSB 18 18 TX_LANE3_PACK_FROM_MSB 19 19 RDPCS_TX_FIFO_RD_START_DELAY 20 24 RDPCS_TX_FIFO_EN 25 25 RDPCS_TX_FIFO_START 26 26 RDPCS_CR_REGISTER_BLOCK_EN 28 28 RDPCS_NON_DPALT_REGISTER_BLOCK_EN 29 29 RDPCS_DPALT_BLOCK_STATUS 30 30 RDPCS_TX_SOFT_RESET 31 31 regRDPCSTX4_RDPCSTX_CLOCK_CNTL 0 0x2c91 16 0 2 RDPCS_EXT_REFCLK_EN 0 0 RDPCS_TX0_CLK_EN 4 4 RDPCS_TX1_CLK_EN 5 5 RDPCS_TX2_CLK_EN 6 6 RDPCS_TX3_CLK_EN 7 7 RDPCS_TX_CLK_GATE_DIS 8 8 RDPCS_TX_CLK_EN 9 9 RDPCS_TX_CLK_CLOCK_ON 10 10 RDPCS_TX_PHY_REF_ALT_CLK_EN 11 11 RDPCS_SRAMCLK_GATE_DIS 12 12 RDPCS_SRAMCLK_EN 13 13 RDPCS_SRAMCLK_CLOCK_ON 14 14 RDPCS_SRAMCLK_BYPASS 16 16 RDPCS_OCLACLK_GATE_DIS 20 20 RDPCS_OCLACLK_EN 21 21 RDPCS_OCLACLK_CLOCK_ON 22 22 regRDPCSTX4_RDPCSTX_INTERRUPT_CONTROL 0 0x2c92 15 0 2 RDPCS_REG_FIFO_OVERFLOW 0 0 RDPCS_DPALT_DISABLE_TOGGLE 1 1 RDPCS_DPALT_4LANE_TOGGLE 2 2 RDPCS_TX0_FIFO_ERROR 4 4 RDPCS_TX1_FIFO_ERROR 5 5 RDPCS_TX2_FIFO_ERROR 6 6 RDPCS_TX3_FIFO_ERROR 7 7 RDPCS_REG_ERROR_CLR 8 8 RDPCS_DPALT_DISABLE_TOGGLE_CLR 9 9 RDPCS_DPALT_4LANE_TOGGLE_CLR 10 10 RDPCS_TX_ERROR_CLR 12 12 RDPCS_REG_FIFO_ERROR_MASK 16 16 RDPCS_DPALT_DISABLE_TOGGLE_MASK 17 17 RDPCS_DPALT_4LANE_TOGGLE_MASK 18 18 RDPCS_TX_FIFO_ERROR_MASK 20 20 regRDPCSTX4_RDPCS_TX_PLL_UPDATE_DATA 0 0x2c93 1 0 2 RDPCS_PLL_UPDATE_DATA 0 0 regRDPCSTX4_RDPCS_TX_CR_ADDR 0 0x2c94 1 0 2 RDPCS_TX_CR_ADDR 0 15 regRDPCSTX4_RDPCS_TX_CR_DATA 0 0x2c95 1 0 2 RDPCS_TX_CR_DATA 0 15 regRDPCSTX4_RDPCS_TX_SRAM_CNTL 0 0x2c96 3 0 2 RDPCS_MEM_PWR_DIS 20 20 RDPCS_MEM_PWR_FORCE 24 25 RDPCS_MEM_PWR_PWR_STATE 28 29 regRDPCSTX4_RDPCSTX_SCRATCH 0 0x2c97 1 0 2 RDPCSTX_SCRATCH 0 31 regRDPCSTX4_RDPCSTX_SPARE 0 0x2c98 1 0 2 RDPCSTX_SPARE 0 31 regRDPCSTX4_RDPCSTX_CNTL2 0 0x2c99 3 0 2 RDPCS_CR_CONVERT_FIFO_EMPTY 0 0 RDPCS_CR_CONVERT_FIFO_FULL 1 1 RDPCS_PHY_ENC_TYPE_SEL 2 3 regRDPCSTX4_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG 0 0x2c9c 3 0 2 RDPCS_DMCU_DPALT_DIS_BLOCK_REG 0 0 RDPCS_DMCU_DPALT_FORCE_TX_CLK_DIS 4 4 RDPCS_DMCU_DPALT_CONTROL_SPARE 8 15 regRDPCSTX4_RDPCSTX_DEBUG_CONFIG 0 0x2c9d 7 0 2 RDPCS_DBG_EN 0 0 RDPCS_DBG_SEL_ASYNC_8BIT 4 6 RDPCS_DBG_SEL_ASYNC_SWAP 7 7 RDPCS_DBG_SEL_TEST_CLK 8 12 RDPCS_DBG_CR_COUNT_EXPIRE 15 15 RDPCS_DBG_CR_COUNT_MAX 16 23 RDPCS_DBG_CR_COUNT 24 31 regRDPCSTX4_RDPCSTX_PHY_CNTL0 0 0x2ca0 16 0 2 RDPCS_PHY_RESET 0 0 RDPCS_PHY_TCA_PHY_RESET 1 1 RDPCS_PHY_TCA_APB_RESET_N 2 2 RDPCS_PHY_TEST_POWERDOWN 3 3 RDPCS_PHY_DTB_OUT 4 5 RDPCS_PHY_HDMIMODE_ENABLE 8 8 RDPCS_PHY_REF_RANGE 9 13 RDPCS_PHY_RTUNE_REQ 17 17 RDPCS_PHY_RTUNE_ACK 18 18 RDPCS_PHY_CR_PARA_SEL 20 20 RDPCS_PHY_CR_MUX_SEL 21 21 RDPCS_PHY_REF_CLKDET_EN 24 24 RDPCS_PHY_REF_CLKDET_RESULT 25 25 RDPCS_SRAM_INIT_DONE 28 28 RDPCS_SRAM_EXT_LD_DONE 29 29 RDPCS_SRAM_BYPASS 31 31 regRDPCSTX4_RDPCSTX_PHY_CNTL1 0 0x2ca1 8 0 2 RDPCS_PHY_PG_MODE_EN 0 0 RDPCS_PHY_PCS_PWR_EN 1 1 RDPCS_PHY_PCS_PWR_STABLE 2 2 RDPCS_PHY_PMA_PWR_EN 3 3 RDPCS_PHY_PMA_PWR_STABLE 4 4 RDPCS_PHY_DP_PG_RESET 5 5 RDPCS_PHY_ANA_PWR_EN 6 6 RDPCS_PHY_ANA_PWR_STABLE 7 7 regRDPCSTX4_RDPCSTX_PHY_CNTL2 0 0x2ca2 9 0 2 RDPCS_PHY_DP4_POR 3 3 RDPCS_PHY_DP_LANE0_RX2TX_PAR_LB_EN 4 4 RDPCS_PHY_DP_LANE1_RX2TX_PAR_LB_EN 5 5 RDPCS_PHY_DP_LANE2_RX2TX_PAR_LB_EN 6 6 RDPCS_PHY_DP_LANE3_RX2TX_PAR_LB_EN 7 7 RDPCS_PHY_DP_LANE0_TX2RX_SER_LB_EN 8 8 RDPCS_PHY_DP_LANE1_TX2RX_SER_LB_EN 9 9 RDPCS_PHY_DP_LANE2_TX2RX_SER_LB_EN 10 10 RDPCS_PHY_DP_LANE3_TX2RX_SER_LB_EN 11 11 regRDPCSTX4_RDPCSTX_PHY_CNTL3 0 0x2ca3 24 0 2 RDPCS_PHY_DP_TX0_RESET 0 0 RDPCS_PHY_DP_TX0_DISABLE 1 1 RDPCS_PHY_DP_TX0_CLK_RDY 2 2 RDPCS_PHY_DP_TX0_DATA_EN 3 3 RDPCS_PHY_DP_TX0_REQ 4 4 RDPCS_PHY_DP_TX0_ACK 5 5 RDPCS_PHY_DP_TX1_RESET 8 8 RDPCS_PHY_DP_TX1_DISABLE 9 9 RDPCS_PHY_DP_TX1_CLK_RDY 10 10 RDPCS_PHY_DP_TX1_DATA_EN 11 11 RDPCS_PHY_DP_TX1_REQ 12 12 RDPCS_PHY_DP_TX1_ACK 13 13 RDPCS_PHY_DP_TX2_RESET 16 16 RDPCS_PHY_DP_TX2_DISABLE 17 17 RDPCS_PHY_DP_TX2_CLK_RDY 18 18 RDPCS_PHY_DP_TX2_DATA_EN 19 19 RDPCS_PHY_DP_TX2_REQ 20 20 RDPCS_PHY_DP_TX2_ACK 21 21 RDPCS_PHY_DP_TX3_RESET 24 24 RDPCS_PHY_DP_TX3_DISABLE 25 25 RDPCS_PHY_DP_TX3_CLK_RDY 26 26 RDPCS_PHY_DP_TX3_DATA_EN 27 27 RDPCS_PHY_DP_TX3_REQ 28 28 RDPCS_PHY_DP_TX3_ACK 29 29 regRDPCSTX4_RDPCSTX_PHY_CNTL4 0 0x2ca4 16 0 2 RDPCS_PHY_DP_TX0_TERM_CTRL 0 2 RDPCS_PHY_DP_TX0_INVERT 4 4 RDPCS_PHY_DP_TX0_BYPASS_EQ_CALC 6 6 RDPCS_PHY_DP_TX0_HP_PROT_EN 7 7 RDPCS_PHY_DP_TX1_TERM_CTRL 8 10 RDPCS_PHY_DP_TX1_INVERT 12 12 RDPCS_PHY_DP_TX1_BYPASS_EQ_CALC 14 14 RDPCS_PHY_DP_TX1_HP_PROT_EN 15 15 RDPCS_PHY_DP_TX2_TERM_CTRL 16 18 RDPCS_PHY_DP_TX2_INVERT 20 20 RDPCS_PHY_DP_TX2_BYPASS_EQ_CALC 22 22 RDPCS_PHY_DP_TX2_HP_PROT_EN 23 23 RDPCS_PHY_DP_TX3_TERM_CTRL 24 26 RDPCS_PHY_DP_TX3_INVERT 28 28 RDPCS_PHY_DP_TX3_BYPASS_EQ_CALC 30 30 RDPCS_PHY_DP_TX3_HP_PROT_EN 31 31 regRDPCSTX4_RDPCSTX_PHY_CNTL5 0 0x2ca5 20 0 2 RDPCS_PHY_DP_TX0_LPD 0 0 RDPCS_PHY_DP_TX0_RATE 1 3 RDPCS_PHY_DP_TX0_WIDTH 4 5 RDPCS_PHY_DP_TX0_DETRX_REQ 6 6 RDPCS_PHY_DP_TX0_DETRX_RESULT 7 7 RDPCS_PHY_DP_TX1_LPD 8 8 RDPCS_PHY_DP_TX1_RATE 9 11 RDPCS_PHY_DP_TX1_WIDTH 12 13 RDPCS_PHY_DP_TX1_DETRX_REQ 14 14 RDPCS_PHY_DP_TX1_DETRX_RESULT 15 15 RDPCS_PHY_DP_TX2_LPD 16 16 RDPCS_PHY_DP_TX2_RATE 17 19 RDPCS_PHY_DP_TX2_WIDTH 20 21 RDPCS_PHY_DP_TX2_DETRX_REQ 22 22 RDPCS_PHY_DP_TX2_DETRX_RESULT 23 23 RDPCS_PHY_DP_TX3_LPD 24 24 RDPCS_PHY_DP_TX3_RATE 25 27 RDPCS_PHY_DP_TX3_WIDTH 28 29 RDPCS_PHY_DP_TX3_DETRX_REQ 30 30 RDPCS_PHY_DP_TX3_DETRX_RESULT 31 31 regRDPCSTX4_RDPCSTX_PHY_CNTL6 0 0x2ca6 13 0 2 RDPCS_PHY_DP_TX0_PSTATE 0 1 RDPCS_PHY_DP_TX0_MPLL_EN 2 2 RDPCS_PHY_DP_TX1_PSTATE 4 5 RDPCS_PHY_DP_TX1_MPLL_EN 6 6 RDPCS_PHY_DP_TX2_PSTATE 8 9 RDPCS_PHY_DP_TX2_MPLL_EN 10 10 RDPCS_PHY_DP_TX3_PSTATE 12 13 RDPCS_PHY_DP_TX3_MPLL_EN 14 14 RDPCS_PHY_DPALT_DP4 16 16 RDPCS_PHY_DPALT_DISABLE 17 17 RDPCS_PHY_DPALT_DISABLE_ACK 18 18 RDPCS_PHY_DP_REF_CLK_EN 19 19 RDPCS_PHY_DP_REF_CLK_REQ 20 20 regRDPCSTX4_RDPCSTX_PHY_CNTL7 0 0x2ca7 2 0 2 RDPCS_PHY_DP_MPLLB_FRACN_DEN 0 15 RDPCS_PHY_DP_MPLLB_FRACN_QUOT 16 31 regRDPCSTX4_RDPCSTX_PHY_CNTL8 0 0x2ca8 1 0 2 RDPCS_PHY_DP_MPLLB_SSC_PEAK 0 19 regRDPCSTX4_RDPCSTX_PHY_CNTL9 0 0x2ca9 2 0 2 RDPCS_PHY_DP_MPLLB_SSC_STEPSIZE 0 20 RDPCS_PHY_DP_MPLLB_SSC_UP_SPREAD 24 24 regRDPCSTX4_RDPCSTX_PHY_CNTL10 0 0x2caa 1 0 2 RDPCS_PHY_DP_MPLLB_FRACN_REM 0 15 regRDPCSTX4_RDPCSTX_PHY_CNTL11 0 0x2cab 4 0 2 RDPCS_PHY_DP_MPLLB_MULTIPLIER 4 15 RDPCS_PHY_HDMI_MPLLB_HDMI_DIV 16 18 RDPCS_PHY_DP_REF_CLK_MPLLB_DIV 20 22 RDPCS_PHY_HDMI_MPLLB_HDMI_PIXEL_CLK_DIV 24 25 regRDPCSTX4_RDPCSTX_PHY_CNTL12 0 0x2cac 5 0 2 RDPCS_PHY_DP_MPLLB_DIV5_CLK_EN 0 0 RDPCS_PHY_DP_MPLLB_WORD_DIV2_EN 2 2 RDPCS_PHY_DP_MPLLB_TX_CLK_DIV 4 6 RDPCS_PHY_DP_MPLLB_STATE 7 7 RDPCS_PHY_DP_MPLLB_SSC_EN 8 8 regRDPCSTX4_RDPCSTX_PHY_CNTL13 0 0x2cad 4 0 2 RDPCS_PHY_DP_MPLLB_DIV_MULTIPLIER 20 27 RDPCS_PHY_DP_MPLLB_DIV_CLK_EN 28 28 RDPCS_PHY_DP_MPLLB_FORCE_EN 29 29 RDPCS_PHY_DP_MPLLB_INIT_CAL_DISABLE 30 30 regRDPCSTX4_RDPCSTX_PHY_CNTL14 0 0x2cae 3 0 2 RDPCS_PHY_DP_MPLLB_CAL_FORCE 0 0 RDPCS_PHY_DP_MPLLB_FRACN_EN 24 24 RDPCS_PHY_DP_MPLLB_PMIX_EN 28 28 regRDPCSTX4_RDPCSTX_PHY_FUSE0 0 0x2caf 7 0 2 RDPCS_PHY_DP_TX0_EQ_MAIN 0 5 RDPCS_PHY_DP_TX0_EQ_PRE 6 11 RDPCS_PHY_DP_TX0_EQ_POST 12 17 RDPCS_PHY_DP_MPLLB_V2I 18 19 RDPCS_PHY_DP_MPLLB_FREQ_VCO 20 21 RDPCS_PHY_DP_MPLLB_CP_INT_GS 22 28 RDPCS_PHY_RX_VREF_CTRL 29 31 regRDPCSTX4_RDPCSTX_PHY_FUSE1 0 0x2cb0 5 0 2 RDPCS_PHY_DP_TX1_EQ_MAIN 0 5 RDPCS_PHY_DP_TX1_EQ_PRE 6 11 RDPCS_PHY_DP_TX1_EQ_POST 12 17 RDPCS_PHY_DP_MPLLB_CP_INT 18 24 RDPCS_PHY_DP_MPLLB_CP_PROP 25 31 regRDPCSTX4_RDPCSTX_PHY_FUSE2 0 0x2cb1 4 0 2 RDPCS_PHY_DP_TX2_EQ_MAIN 0 5 RDPCS_PHY_DP_TX2_EQ_PRE 6 11 RDPCS_PHY_DP_TX2_EQ_POST 12 17 RDPCS_PHY_DP_MPLLB_CP_PROP_GS 23 29 regRDPCSTX4_RDPCSTX_PHY_FUSE3 0 0x2cb2 7 0 2 RDPCS_PHY_DP_TX3_EQ_MAIN 0 5 RDPCS_PHY_DP_TX3_EQ_PRE 6 11 RDPCS_PHY_DP_TX3_EQ_POST 12 17 RDPCS_PHY_DCO_FINETUNE 18 23 RDPCS_PHY_DCO_RANGE 24 25 RDPCS_PHY_TX_VBOOST_LVL 26 28 RDPCS_PHY_SUP_RX_VCO_VREF_SEL 29 31 regRDPCSTX4_RDPCSTX_PHY_RX_LD_VAL 0 0x2cb3 3 0 2 RDPCS_PHY_RX_REF_LD_VAL 0 6 RDPCS_PHY_RX_CDR_VCO_LOWFREQ 7 7 RDPCS_PHY_RX_VCO_LD_VAL 8 20 regRDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL3 0 0x2cb4 24 0 2 RDPCS_PHY_DP_TX0_RESET_RESERVED 0 0 RDPCS_PHY_DP_TX0_DISABLE_RESERVED 1 1 RDPCS_PHY_DP_TX0_CLK_RDY_RESERVED 2 2 RDPCS_PHY_DP_TX0_DATA_EN_RESERVED 3 3 RDPCS_PHY_DP_TX0_REQ_RESERVED 4 4 RDPCS_PHY_DP_TX0_ACK_RESERVED 5 5 RDPCS_PHY_DP_TX1_RESET_RESERVED 8 8 RDPCS_PHY_DP_TX1_DISABLE_RESERVED 9 9 RDPCS_PHY_DP_TX1_CLK_RDY_RESERVED 10 10 RDPCS_PHY_DP_TX1_DATA_EN_RESERVED 11 11 RDPCS_PHY_DP_TX1_REQ_RESERVED 12 12 RDPCS_PHY_DP_TX1_ACK_RESERVED 13 13 RDPCS_PHY_DP_TX2_RESET_RESERVED 16 16 RDPCS_PHY_DP_TX2_DISABLE_RESERVED 17 17 RDPCS_PHY_DP_TX2_CLK_RDY_RESERVED 18 18 RDPCS_PHY_DP_TX2_DATA_EN_RESERVED 19 19 RDPCS_PHY_DP_TX2_REQ_RESERVED 20 20 RDPCS_PHY_DP_TX2_ACK_RESERVED 21 21 RDPCS_PHY_DP_TX3_RESET_RESERVED 24 24 RDPCS_PHY_DP_TX3_DISABLE_RESERVED 25 25 RDPCS_PHY_DP_TX3_CLK_RDY_RESERVED 26 26 RDPCS_PHY_DP_TX3_DATA_EN_RESERVED 27 27 RDPCS_PHY_DP_TX3_REQ_RESERVED 28 28 RDPCS_PHY_DP_TX3_ACK_RESERVED 29 29 regRDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL6 0 0x2cb5 13 0 2 RDPCS_PHY_DP_TX0_PSTATE_RESERVED 0 1 RDPCS_PHY_DP_TX0_MPLL_EN_RESERVED 2 2 RDPCS_PHY_DP_TX1_PSTATE_RESERVED 4 5 RDPCS_PHY_DP_TX1_MPLL_EN_RESERVED 6 6 RDPCS_PHY_DP_TX2_PSTATE_RESERVED 8 9 RDPCS_PHY_DP_TX2_MPLL_EN_RESERVED 10 10 RDPCS_PHY_DP_TX3_PSTATE_RESERVED 12 13 RDPCS_PHY_DP_TX3_MPLL_EN_RESERVED 14 14 RDPCS_PHY_DPALT_DP4_RESERVED 16 16 RDPCS_PHY_DPALT_DISABLE_RESERVED 17 17 RDPCS_PHY_DPALT_DISABLE_ACK_RESERVED 18 18 RDPCS_PHY_DP_REF_CLK_EN_RESERVED 19 19 RDPCS_PHY_DP_REF_CLK_REQ_RESERVED 20 20 regRDPCSTX4_RDPCSTX_DPALT_CONTROL_REG 0 0x2cb6 3 0 2 RDPCS_ALLOW_DRIVER_ACCESS 0 0 RDPCS_DRIVER_ACCESS_BLOCKED 4 4 RDPCS_DPALT_CONTROL_SPARE 8 15 regRDPCSTX4_RDPCSTX_PHY_CNTL15 0 0x2cb8 6 0 2 RDPCS_PHY_SSTX_VREGDRV_BYP 0 0 RDPCS_PHY_DP_TX0_VREGDRV_BYP 16 16 RDPCS_PHY_DP_TX1_VREGDRV_BYP 17 17 RDPCS_PHY_DP_TX2_VREGDRV_BYP 18 18 RDPCS_PHY_DP_TX3_VREGDRV_BYP 19 19 RDPCS_PHY_SUP_PRE_HP 20 20 regRDPCSTX4_RDPCSTX_PHY_CNTL16 0 0x2cb9 5 0 2 RDPCS_PHY_DP_TX0_OUT_GENERIC_BUS 0 4 RDPCS_PHY_DP_TX1_OUT_GENERIC_BUS 6 10 RDPCS_PHY_DP_TX2_OUT_GENERIC_BUS 12 16 RDPCS_PHY_DP_TX3_OUT_GENERIC_BUS 18 22 RDPCS_PHY_CMN_OUT_GENERIC_BUS 24 28 regRDPCSTX4_RDPCSTX_PHY_CNTL17 0 0x2cba 5 0 2 RDPCS_PHY_DP_TX0_IN_GENERIC_BUS 0 4 RDPCS_PHY_DP_TX1_IN_GENERIC_BUS 6 10 RDPCS_PHY_DP_TX2_IN_GENERIC_BUS 12 16 RDPCS_PHY_DP_TX3_IN_GENERIC_BUS 18 22 RDPCS_PHY_CMN_IN_GENERIC_BUS 24 28 regRDPCSTX4_RDPCSTX_DEBUG_CONFIG2 0 0x2cbb 5 0 2 RDPCS_DBG_OCLA_SRC0 0 2 RDPCS_DBG_OCLA_SRC1 4 6 RDPCS_DBG_OCLA_SRC2 8 10 RDPCS_DBG_OCLA_SRC3 12 14 RDPCS_DBG_OCLA_VALID_REPLACE_MSB 16 16 regRDPCSTX4_RDPCS_CNTL3 0 0x2cbc 4 0 2 TX_LANE0_BYTE_ORDER_CHANGE 0 7 TX_LANE1_BYTE_ORDER_CHANGE 8 15 TX_LANE2_BYTE_ORDER_CHANGE 16 23 TX_LANE3_BYTE_ORDER_CHANGE 24 31 regRDPCSTX4_RDPCS_TX_PLL_UPDATE_ADDR_OVRRD 0 0x2cbd 1 0 2 RDPCS_PLL_UPDATE_ADDR_OVRRD 0 17 regRDPCSTX4_RDPCS_TX_PLL_UPDATE_DATA_OVRRD 0 0x2cbe 1 0 2 RDPCS_PLL_UPDATE_DATA_OVRRD 0 31 regRDPCSPIPE0_RDPCSPIPE_PHY_CNTL6 0 0x2d73 3 0 2 RDPCS_PHY_DPALT_DP4 16 16 RDPCS_PHY_DPALT_DISABLE 17 17 RDPCS_PHY_DPALT_DISABLE_ACK 18 18 regRDPCSPIPE1_RDPCSPIPE_PHY_CNTL6 0 0x2e4b 3 0 2 RDPCS_PHY_DPALT_DP4 16 16 RDPCS_PHY_DPALT_DISABLE 17 17 RDPCS_PHY_DPALT_DISABLE_ACK 18 18 regRDPCSPIPE2_RDPCSPIPE_PHY_CNTL6 0 0x2d73 0 0 2 regRDPCSPIPE3_RDPCSPIPE_PHY_CNTL6 0 0x2e4b 0 0 2 regRDPCSPIPE4_RDPCSPIPE_PHY_CNTL6 0 0x2d73 0 0 2 regDC_GENERICA 0 0x2868 6 0 2 GENERICA_EN 0 0 GENERICA_SEL 7 11 GENERICA_UNIPHY_REFDIV_CLK_SEL 12 15 GENERICA_UNIPHY_FBDIV_CLK_SEL 16 19 GENERICA_UNIPHY_FBDIV_SSC_CLK_SEL 20 23 GENERICA_UNIPHY_FBDIV_CLK_DIV2_SEL 24 27 regDC_GENERICB 0 0x2869 6 0 2 GENERICB_EN 0 0 GENERICB_SEL 8 11 GENERICB_UNIPHY_REFDIV_CLK_SEL 12 15 GENERICB_UNIPHY_FBDIV_CLK_SEL 16 19 GENERICB_UNIPHY_FBDIV_SSC_CLK_SEL 20 23 GENERICB_UNIPHY_FBDIV_CLK_DIV2_SEL 24 27 regDCIO_CLOCK_CNTL 0 0x286a 2 0 2 DCIO_TEST_CLK_SEL 0 4 DISPCLK_R_DCIO_GATE_DIS 5 5 regDC_REF_CLK_CNTL 0 0x286b 2 0 2 HSYNCA_OUTPUT_SEL 0 1 GENLK_CLK_OUTPUT_SEL 8 9 regUNIPHYA_LINK_CNTL 0 0x286d 4 0 2 UNIPHY_CHANNEL0_INVERT 12 12 UNIPHY_CHANNEL1_INVERT 13 13 UNIPHY_CHANNEL2_INVERT 14 14 UNIPHY_CHANNEL3_INVERT 15 15 regUNIPHYA_CHANNEL_XBAR_CNTL 0 0x286e 4 0 2 UNIPHY_CHANNEL0_XBAR_SOURCE 0 1 UNIPHY_CHANNEL1_XBAR_SOURCE 8 9 UNIPHY_CHANNEL2_XBAR_SOURCE 16 17 UNIPHY_CHANNEL3_XBAR_SOURCE 24 25 regUNIPHYB_LINK_CNTL 0 0x286f 4 0 2 UNIPHY_CHANNEL0_INVERT 12 12 UNIPHY_CHANNEL1_INVERT 13 13 UNIPHY_CHANNEL2_INVERT 14 14 UNIPHY_CHANNEL3_INVERT 15 15 regUNIPHYB_CHANNEL_XBAR_CNTL 0 0x2870 4 0 2 UNIPHY_CHANNEL0_XBAR_SOURCE 0 1 UNIPHY_CHANNEL1_XBAR_SOURCE 8 9 UNIPHY_CHANNEL2_XBAR_SOURCE 16 17 UNIPHY_CHANNEL3_XBAR_SOURCE 24 25 regUNIPHYC_LINK_CNTL 0 0x2871 4 0 2 UNIPHY_CHANNEL0_INVERT 12 12 UNIPHY_CHANNEL1_INVERT 13 13 UNIPHY_CHANNEL2_INVERT 14 14 UNIPHY_CHANNEL3_INVERT 15 15 regUNIPHYC_CHANNEL_XBAR_CNTL 0 0x2872 4 0 2 UNIPHY_CHANNEL0_XBAR_SOURCE 0 1 UNIPHY_CHANNEL1_XBAR_SOURCE 8 9 UNIPHY_CHANNEL2_XBAR_SOURCE 16 17 UNIPHY_CHANNEL3_XBAR_SOURCE 24 25 regUNIPHYD_LINK_CNTL 0 0x2873 4 0 2 UNIPHY_CHANNEL0_INVERT 12 12 UNIPHY_CHANNEL1_INVERT 13 13 UNIPHY_CHANNEL2_INVERT 14 14 UNIPHY_CHANNEL3_INVERT 15 15 regUNIPHYD_CHANNEL_XBAR_CNTL 0 0x2874 4 0 2 UNIPHY_CHANNEL0_XBAR_SOURCE 0 1 UNIPHY_CHANNEL1_XBAR_SOURCE 8 9 UNIPHY_CHANNEL2_XBAR_SOURCE 16 17 UNIPHY_CHANNEL3_XBAR_SOURCE 24 25 regUNIPHYE_LINK_CNTL 0 0x2875 4 0 2 UNIPHY_CHANNEL0_INVERT 12 12 UNIPHY_CHANNEL1_INVERT 13 13 UNIPHY_CHANNEL2_INVERT 14 14 UNIPHY_CHANNEL3_INVERT 15 15 regUNIPHYE_CHANNEL_XBAR_CNTL 0 0x2876 4 0 2 UNIPHY_CHANNEL0_XBAR_SOURCE 0 1 UNIPHY_CHANNEL1_XBAR_SOURCE 8 9 UNIPHY_CHANNEL2_XBAR_SOURCE 16 17 UNIPHY_CHANNEL3_XBAR_SOURCE 24 25 regDCIO_WRCMD_DELAY 0 0x287e 1 0 2 UNIPHY_DELAY 24 31 regDC_PINSTRAPS 0 0x2880 4 0 2 DC_PINSTRAPS_SMS_EN_HARD 13 13 DC_PINSTRAPS_AUDIO 14 15 DC_PINSTRAPS_CCBYPASS 16 16 DC_PINSTRAPS_CONNECTIVITY 17 19 regINTERCEPT_STATE 0 0x2884 9 0 2 PWRSEQ0_INTERCEPTB_STATE 0 0 PWRSEQ1_INTERCEPTB_STATE 1 1 DPCS0_INTERCEPTB_STATE 4 4 DPCS1_INTERCEPTB_STATE 5 5 DPCS2_INTERCEPTB_STATE 6 6 DPCS3_INTERCEPTB_STATE 7 7 DPCS4_INTERCEPTB_STATE 8 8 DPCS5_INTERCEPTB_STATE 9 9 DPCS6_INTERCEPTB_STATE 10 10 regDCIO_BL_PWM_FRAME_START_DISP_SEL 0 0x288b 2 0 2 BL_PWM0_GRP1_FRAME_START_DISP_SEL 0 2 BL_PWM1_GRP1_FRAME_START_DISP_SEL 4 6 regDCIO_GSL_GENLK_PAD_CNTL 0 0x288c 4 0 2 DCIO_GENLK_CLK_GSL_FLIP_READY_SEL 4 5 DCIO_GENLK_CLK_GSL_MASK 8 9 DCIO_GENLK_VSYNC_GSL_FLIP_READY_SEL 20 21 DCIO_GENLK_VSYNC_GSL_MASK 24 25 regDCIO_GSL_SWAPLOCK_PAD_CNTL 0 0x288d 4 0 2 DCIO_SWAPLOCK_A_GSL_FLIP_READY_SEL 4 5 DCIO_SWAPLOCK_A_GSL_MASK 8 9 DCIO_SWAPLOCK_B_GSL_FLIP_READY_SEL 20 21 DCIO_SWAPLOCK_B_GSL_MASK 24 25 regDCIO_SOFT_RESET 0 0x289e 16 0 2 UNIPHYA_SOFT_RESET 0 0 UNIPHYB_SOFT_RESET 1 1 UNIPHYC_SOFT_RESET 2 2 UNIPHYD_SOFT_RESET 3 3 UNIPHYE_SOFT_RESET 4 4 UNIPHYF_SOFT_RESET 5 5 UNIPHYG_SOFT_RESET 6 6 DSYNCA_SOFT_RESET 8 8 DSYNCB_SOFT_RESET 9 9 DSYNCC_SOFT_RESET 10 10 DSYNCD_SOFT_RESET 11 11 DSYNCE_SOFT_RESET 12 12 DSYNCF_SOFT_RESET 13 13 DSYNCG_SOFT_RESET 14 14 PWRSEQ0_SOFT_RESET 16 16 PWRSEQ1_SOFT_RESET 17 17 regDC_GPIO_GENERIC_MASK 0 0x28c8 22 0 2 DC_GPIO_GENERICA_MASK 0 0 DC_GPIO_GENERICA_PD_DIS 1 1 DC_GPIO_GENERICA_RECV 2 3 DC_GPIO_GENERICB_MASK 4 4 DC_GPIO_GENERICB_PD_DIS 5 5 DC_GPIO_GENERICB_RECV 6 7 DC_GPIO_GENERICC_MASK 8 8 DC_GPIO_GENERICC_PD_DIS 9 9 DC_GPIO_GENERICC_RECV 10 11 DC_GPIO_GENERICD_MASK 12 12 DC_GPIO_GENERICD_PD_DIS 13 13 DC_GPIO_GENERICD_RECV 14 15 DC_GPIO_GENERICE_MASK 16 16 DC_GPIO_GENERICE_PD_DIS 17 17 DC_GPIO_GENERICE_RECV 18 19 DC_GPIO_GENERICF_MASK 20 20 DC_GPIO_GENERICF_PD_DIS 21 21 DC_GPIO_GENERICF_RECV 22 23 DC_GPIO_GENERICG_MASK 24 24 DC_GPIO_GENERICG_PD_DIS 25 25 DC_GPIO_GENERICG_RECV 26 27 DC_GPIO_GENERICB_STRENGTH_SN 28 31 regDC_GPIO_GENERIC_A 0 0x28c9 7 0 2 DC_GPIO_GENERICA_A 0 0 DC_GPIO_GENERICB_A 8 8 DC_GPIO_GENERICC_A 16 16 DC_GPIO_GENERICD_A 20 20 DC_GPIO_GENERICE_A 21 21 DC_GPIO_GENERICF_A 22 22 DC_GPIO_GENERICG_A 23 23 regDC_GPIO_GENERIC_EN 0 0x28ca 7 0 2 DC_GPIO_GENERICA_EN 0 0 DC_GPIO_GENERICB_EN 8 8 DC_GPIO_GENERICC_EN 16 16 DC_GPIO_GENERICD_EN 20 20 DC_GPIO_GENERICE_EN 21 21 DC_GPIO_GENERICF_EN 22 22 DC_GPIO_GENERICG_EN 23 23 regDC_GPIO_GENERIC_Y 0 0x28cb 7 0 2 DC_GPIO_GENERICA_Y 0 0 DC_GPIO_GENERICB_Y 8 8 DC_GPIO_GENERICC_Y 16 16 DC_GPIO_GENERICD_Y 20 20 DC_GPIO_GENERICE_Y 21 21 DC_GPIO_GENERICF_Y 22 22 DC_GPIO_GENERICG_Y 23 23 regDC_GPIO_DDC1_MASK 0 0x28d0 11 0 2 DC_GPIO_DDC1CLK_MASK 0 0 DC_GPIO_DDC1CLK_PD_EN 4 4 DC_GPIO_DDC1CLK_RECV 6 6 DC_GPIO_DDC1DATA_MASK 8 8 DC_GPIO_DDC1DATA_PD_EN 12 12 DC_GPIO_DDC1DATA_RECV 14 14 AUX_PAD1_MODE 16 16 AUX1_POL 20 20 ALLOW_HW_DDC1_PD_EN 22 22 DC_GPIO_DDC1CLK_STR 24 27 DC_GPIO_DDC1DATA_STR 28 31 regDC_GPIO_DDC1_A 0 0x28d1 2 0 2 DC_GPIO_DDC1CLK_A 0 0 DC_GPIO_DDC1DATA_A 8 8 regDC_GPIO_DDC1_EN 0 0x28d2 2 0 2 DC_GPIO_DDC1CLK_EN 0 0 DC_GPIO_DDC1DATA_EN 8 8 regDC_GPIO_DDC1_Y 0 0x28d3 2 0 2 DC_GPIO_DDC1CLK_Y 0 0 DC_GPIO_DDC1DATA_Y 8 8 regDC_GPIO_DDC2_MASK 0 0x28d4 11 0 2 DC_GPIO_DDC2CLK_MASK 0 0 DC_GPIO_DDC2CLK_PD_EN 4 4 DC_GPIO_DDC2CLK_RECV 6 6 DC_GPIO_DDC2DATA_MASK 8 8 DC_GPIO_DDC2DATA_PD_EN 12 12 DC_GPIO_DDC2DATA_RECV 14 14 AUX_PAD2_MODE 16 16 AUX2_POL 20 20 ALLOW_HW_DDC2_PD_EN 22 22 DC_GPIO_DDC2CLK_STR 24 27 DC_GPIO_DDC2DATA_STR 28 31 regDC_GPIO_DDC2_A 0 0x28d5 2 0 2 DC_GPIO_DDC2CLK_A 0 0 DC_GPIO_DDC2DATA_A 8 8 regDC_GPIO_DDC2_EN 0 0x28d6 2 0 2 DC_GPIO_DDC2CLK_EN 0 0 DC_GPIO_DDC2DATA_EN 8 8 regDC_GPIO_DDC2_Y 0 0x28d7 2 0 2 DC_GPIO_DDC2CLK_Y 0 0 DC_GPIO_DDC2DATA_Y 8 8 regDC_GPIO_DDC3_MASK 0 0x28d8 11 0 2 DC_GPIO_DDC3CLK_MASK 0 0 DC_GPIO_DDC3CLK_PD_EN 4 4 DC_GPIO_DDC3CLK_RECV 6 6 DC_GPIO_DDC3DATA_MASK 8 8 DC_GPIO_DDC3DATA_PD_EN 12 12 DC_GPIO_DDC3DATA_RECV 14 14 AUX_PAD3_MODE 16 16 AUX3_POL 20 20 ALLOW_HW_DDC3_PD_EN 22 22 DC_GPIO_DDC3CLK_STR 24 27 DC_GPIO_DDC3DATA_STR 28 31 regDC_GPIO_DDC3_A 0 0x28d9 2 0 2 DC_GPIO_DDC3CLK_A 0 0 DC_GPIO_DDC3DATA_A 8 8 regDC_GPIO_DDC3_EN 0 0x28da 2 0 2 DC_GPIO_DDC3CLK_EN 0 0 DC_GPIO_DDC3DATA_EN 8 8 regDC_GPIO_DDC3_Y 0 0x28db 2 0 2 DC_GPIO_DDC3CLK_Y 0 0 DC_GPIO_DDC3DATA_Y 8 8 regDC_GPIO_DDC4_MASK 0 0x28dc 11 0 2 DC_GPIO_DDC4CLK_MASK 0 0 DC_GPIO_DDC4CLK_PD_EN 4 4 DC_GPIO_DDC4CLK_RECV 6 6 DC_GPIO_DDC4DATA_MASK 8 8 DC_GPIO_DDC4DATA_PD_EN 12 12 DC_GPIO_DDC4DATA_RECV 14 14 AUX_PAD4_MODE 16 16 AUX4_POL 20 20 ALLOW_HW_DDC4_PD_EN 22 22 DC_GPIO_DDC4CLK_STR 24 27 DC_GPIO_DDC4DATA_STR 28 31 regDC_GPIO_DDC4_A 0 0x28dd 2 0 2 DC_GPIO_DDC4CLK_A 0 0 DC_GPIO_DDC4DATA_A 8 8 regDC_GPIO_DDC4_EN 0 0x28de 2 0 2 DC_GPIO_DDC4CLK_EN 0 0 DC_GPIO_DDC4DATA_EN 8 8 regDC_GPIO_DDC4_Y 0 0x28df 2 0 2 DC_GPIO_DDC4CLK_Y 0 0 DC_GPIO_DDC4DATA_Y 8 8 regDC_GPIO_DDC5_MASK 0 0x28e0 11 0 2 DC_GPIO_DDC5CLK_MASK 0 0 DC_GPIO_DDC5CLK_PD_EN 4 4 DC_GPIO_DDC5CLK_RECV 6 6 DC_GPIO_DDC5DATA_MASK 8 8 DC_GPIO_DDC5DATA_PD_EN 12 12 DC_GPIO_DDC5DATA_RECV 14 14 AUX_PAD5_MODE 16 16 AUX5_POL 20 20 ALLOW_HW_DDC5_PD_EN 22 22 DC_GPIO_DDC5CLK_STR 24 27 DC_GPIO_DDC5DATA_STR 28 31 regDC_GPIO_DDC5_A 0 0x28e1 2 0 2 DC_GPIO_DDC5CLK_A 0 0 DC_GPIO_DDC5DATA_A 8 8 regDC_GPIO_DDC5_EN 0 0x28e2 2 0 2 DC_GPIO_DDC5CLK_EN 0 0 DC_GPIO_DDC5DATA_EN 8 8 regDC_GPIO_DDC5_Y 0 0x28e3 2 0 2 DC_GPIO_DDC5CLK_Y 0 0 DC_GPIO_DDC5DATA_Y 8 8 regDC_GPIO_DDCVGA_MASK 0 0x28e8 10 0 2 DC_GPIO_DDCVGACLK_MASK 0 0 DC_GPIO_DDCVGACLK_RECV 6 6 DC_GPIO_DDCVGADATA_MASK 8 8 DC_GPIO_DDCVGADATA_PD_EN 12 12 DC_GPIO_DDCVGADATA_RECV 14 14 AUX_PADVGA_MODE 16 16 AUXVGA_POL 20 20 ALLOW_HW_DDCVGA_PD_EN 22 22 DC_GPIO_DDCVGACLK_STR 24 27 DC_GPIO_DDCVGADATA_STR 28 31 regDC_GPIO_DDCVGA_A 0 0x28e9 2 0 2 DC_GPIO_DDCVGACLK_A 0 0 DC_GPIO_DDCVGADATA_A 8 8 regDC_GPIO_DDCVGA_EN 0 0x28ea 2 0 2 DC_GPIO_DDCVGACLK_EN 0 0 DC_GPIO_DDCVGADATA_EN 8 8 regDC_GPIO_DDCVGA_Y 0 0x28eb 2 0 2 DC_GPIO_DDCVGACLK_Y 0 0 DC_GPIO_DDCVGADATA_Y 8 8 regDC_GPIO_GENLK_MASK 0 0x28f0 16 0 2 DC_GPIO_GENLK_CLK_MASK 0 0 DC_GPIO_GENLK_CLK_PD_DIS 1 1 DC_GPIO_GENLK_CLK_PU_EN 3 3 DC_GPIO_GENLK_CLK_RECV 4 5 DC_GPIO_GENLK_VSYNC_MASK 8 8 DC_GPIO_GENLK_VSYNC_PD_DIS 9 9 DC_GPIO_GENLK_VSYNC_PU_EN 11 11 DC_GPIO_GENLK_VSYNC_RECV 12 13 DC_GPIO_SWAPLOCK_A_MASK 16 16 DC_GPIO_SWAPLOCK_A_PD_DIS 17 17 DC_GPIO_SWAPLOCK_A_PU_EN 19 19 DC_GPIO_SWAPLOCK_A_RECV 20 21 DC_GPIO_SWAPLOCK_B_MASK 24 24 DC_GPIO_SWAPLOCK_B_PD_DIS 25 25 DC_GPIO_SWAPLOCK_B_PU_EN 27 27 DC_GPIO_SWAPLOCK_B_RECV 28 29 regDC_GPIO_GENLK_A 0 0x28f1 4 0 2 DC_GPIO_GENLK_CLK_A 0 0 DC_GPIO_GENLK_VSYNC_A 8 8 DC_GPIO_SWAPLOCK_A_A 16 16 DC_GPIO_SWAPLOCK_B_A 24 24 regDC_GPIO_GENLK_EN 0 0x28f2 4 0 2 DC_GPIO_GENLK_CLK_EN 0 0 DC_GPIO_GENLK_VSYNC_EN 8 8 DC_GPIO_SWAPLOCK_A_EN 16 16 DC_GPIO_SWAPLOCK_B_EN 24 24 regDC_GPIO_GENLK_Y 0 0x28f3 4 0 2 DC_GPIO_GENLK_CLK_Y 0 0 DC_GPIO_GENLK_VSYNC_Y 8 8 DC_GPIO_SWAPLOCK_A_Y 16 16 DC_GPIO_SWAPLOCK_B_Y 24 24 regDC_GPIO_HPD_MASK 0 0x28f4 18 0 2 DC_GPIO_HPD1_MASK 0 0 DC_GPIO_HPD1_PD_DIS 4 4 DC_GPIO_HPD1_RECV 6 7 DC_GPIO_HPD2_MASK 8 8 DC_GPIO_HPD2_PD_DIS 9 9 DC_GPIO_HPD2_RECV 10 11 DC_GPIO_HPD3_MASK 16 16 DC_GPIO_HPD3_PD_DIS 17 17 DC_GPIO_HPD3_RECV 18 19 DC_GPIO_HPD4_MASK 20 20 DC_GPIO_HPD4_PD_DIS 21 21 DC_GPIO_HPD4_RECV 22 23 DC_GPIO_HPD5_MASK 24 24 DC_GPIO_HPD5_PD_DIS 25 25 DC_GPIO_HPD5_RECV 26 27 DC_GPIO_HPD6_MASK 28 28 DC_GPIO_HPD6_PD_DIS 29 29 DC_GPIO_HPD6_RECV 30 31 regDC_GPIO_HPD_A 0 0x28f5 6 0 2 DC_GPIO_HPD1_A 0 0 DC_GPIO_HPD2_A 8 8 DC_GPIO_HPD3_A 16 16 DC_GPIO_HPD4_A 24 24 DC_GPIO_HPD5_A 26 26 DC_GPIO_HPD6_A 28 28 regDC_GPIO_HPD_EN 0 0x28f6 20 0 2 DC_GPIO_HPD1_EN 0 0 HPD1_SCHMEN_PI 1 1 HPD1_SLEWNCORE 2 2 HPD12_SPARE0 5 5 HPD1_SEL0 6 6 DC_GPIO_HPD2_EN 8 8 HPD2_SCHMEN_PI 9 9 HPD12_SPARE1 10 10 DC_GPIO_HPD3_EN 16 16 HPD3_SCHMEN_PI 17 17 HPD34_SPARE0 18 18 DC_GPIO_HPD4_EN 20 20 HPD4_SCHMEN_PI 21 21 HPD34_SPARE1 22 22 DC_GPIO_HPD5_EN 24 24 HPD5_SCHMEN_PI 25 25 HPD56_SPARE0 26 26 DC_GPIO_HPD6_EN 28 28 HPD6_SCHMEN_PI 29 29 HPD56_SPARE1 30 30 regDC_GPIO_HPD_Y 0 0x28f7 6 0 2 DC_GPIO_HPD1_Y 0 0 DC_GPIO_HPD2_Y 8 8 DC_GPIO_HPD3_Y 16 16 DC_GPIO_HPD4_Y 24 24 DC_GPIO_HPD5_Y 26 26 DC_GPIO_HPD6_Y 28 28 regDC_GPIO_PWRSEQ0_EN 0 0x28fa 5 0 2 DC_GPIO_VARY_BL_OTG_VSYNC_EN 20 20 DC_GPIO_VARY_BL_OTG_VSYNC_SEL 21 23 DC_GPIO_BLON_OTG_VSYNC_EN 25 25 DC_GPIO_BLON_OTG_VSYNC_SEL 26 28 DC_GPIO_VARY_BL_GENERICA_EN 29 29 regDC_GPIO_PAD_STRENGTH_1 0 0x28fc 6 0 2 GENLK_STRENGTH_SN 0 3 GENLK_STRENGTH_SP 4 7 TX_HPD_STRENGTH_SN 16 19 TX_HPD_STRENGTH_SP 20 23 SYNC_STRENGTH_SN 24 27 SYNC_STRENGTH_SP 28 31 regDC_GPIO_PAD_STRENGTH_2 0 0x28fd 5 0 2 STRENGTH_SN 0 3 STRENGTH_SP 4 7 EXT_RESET_DRVSTRENGTH 8 10 REF_27_DRVSTRENGTH 12 14 REF_27_SRC_SEL 30 31 regPHY_AUX_CNTL 0 0x28ff 7 0 2 AUX_PAD_WAKE 9 9 AUX1_PAD_RXSEL 10 11 AUX2_PAD_RXSEL 12 13 AUX3_PAD_RXSEL 14 15 AUX4_PAD_RXSEL 16 17 AUX5_PAD_RXSEL 18 19 AUX6_PAD_RXSEL 20 21 regDC_GPIO_PWRSEQ1_EN 0 0x2902 5 0 2 DC_GPIO_VARY_BL_OTG_VSYNC_EN 20 20 DC_GPIO_VARY_BL_OTG_VSYNC_SEL 21 23 DC_GPIO_BLON_OTG_VSYNC_EN 25 25 DC_GPIO_BLON_OTG_VSYNC_SEL 26 28 DC_GPIO_VARY_BL_GENERICA_EN 29 29 regDC_GPIO_TX12_EN 0 0x2915 7 0 2 DC_GPIO_GENERICA_TX12_EN 3 3 DC_GPIO_GENERICB_TX12_EN 4 4 DC_GPIO_GENERICC_TX12_EN 5 5 DC_GPIO_GENERICD_TX12_EN 6 6 DC_GPIO_GENERICE_TX12_EN 7 7 DC_GPIO_GENERICF_TX12_EN 8 8 DC_GPIO_GENERICG_TX12_EN 9 9 regDC_GPIO_AUX_CTRL_0 0 0x2916 21 0 2 DC_GPIO_AUX1_FALLSLEWSEL 0 1 DC_GPIO_AUX2_FALLSLEWSEL 2 3 DC_GPIO_AUX3_FALLSLEWSEL 4 5 DC_GPIO_AUX4_FALLSLEWSEL 6 7 DC_GPIO_AUX5_FALLSLEWSEL 8 9 DC_GPIO_AUX6_FALLSLEWSEL 10 11 DC_GPIO_DDCVGA_FALLSLEWSEL 12 13 DC_GPIO_AUX1_SPIKERCEN 16 16 DC_GPIO_AUX2_SPIKERCEN 17 17 DC_GPIO_AUX3_SPIKERCEN 18 18 DC_GPIO_AUX4_SPIKERCEN 19 19 DC_GPIO_AUX5_SPIKERCEN 20 20 DC_GPIO_AUX6_SPIKERCEN 21 21 DC_GPIO_DDCVGA_SPIKERCEN 22 22 DC_GPIO_AUX1_SPIKERCSEL 24 24 DC_GPIO_AUX2_SPIKERCSEL 25 25 DC_GPIO_AUX3_SPIKERCSEL 26 26 DC_GPIO_AUX4_SPIKERCSEL 27 27 DC_GPIO_AUX5_SPIKERCSEL 28 28 DC_GPIO_AUX6_SPIKERCSEL 29 29 DC_GPIO_DDCVGA_SPIKERCSEL 30 30 regDC_GPIO_AUX_CTRL_1 0 0x2917 22 0 2 DC_GPIO_AUX_CSEL_0P9 0 0 DC_GPIO_AUX_CSEL_1P1 1 1 DC_GPIO_AUX_RSEL_0P9 2 2 DC_GPIO_AUX_RSEL_1P1 3 3 DC_GPIO_I2C_CSEL_0P9 4 4 DC_GPIO_I2C_CSEL_1P1 5 5 DC_GPIO_I2C_RSEL_0P9 6 6 DC_GPIO_I2C_RSEL_1P1 7 7 DC_GPIO_AUX_BIASCRTEN 8 8 DC_GPIO_I2C_BIASCRTEN 9 9 DC_GPIO_AUX_RESBIASEN 10 10 DC_GPIO_I2C_RESBIASEN 11 11 DC_GPIO_AUX1_COMPSEL 12 12 DC_GPIO_DDCVGA_SPARE 14 15 DC_GPIO_DDCVGA_SLEWN 18 18 DC_GPIO_DDCVGA_RXSEL 20 21 DC_GPIO_AUX2_COMPSEL 25 25 DC_GPIO_AUX3_COMPSEL 26 26 DC_GPIO_AUX4_COMPSEL 27 27 DC_GPIO_AUX5_COMPSEL 28 28 DC_GPIO_AUX6_COMPSEL 29 29 DC_GPIO_DDCVGA_COMPSEL 30 30 regDC_GPIO_AUX_CTRL_2 0 0x2918 21 0 2 DC_GPIO_HPD12_FALLSLEWSEL 0 1 DC_GPIO_HPD34_FALLSLEWSEL 2 3 DC_GPIO_HPD56_FALLSLEWSEL 4 5 DC_GPIO_HPD12_SPIKERCEN 8 8 DC_GPIO_HPD34_SPIKERCEN 9 9 DC_GPIO_HPD56_SPIKERCEN 10 10 DC_GPIO_HPD12_SPIKERCSEL 12 12 DC_GPIO_HPD34_SPIKERCSEL 13 13 DC_GPIO_HPD56_SPIKERCSEL 14 14 DC_GPIO_HPD_CSEL_0P9 16 16 DC_GPIO_HPD_CSEL_1P1 17 17 DC_GPIO_HPD_RSEL_0P9 18 18 DC_GPIO_HPD_RSEL_1P1 19 19 DC_GPIO_HPD_BIASCRTEN 20 20 DC_GPIO_HPD12_SLEWN 24 24 DC_GPIO_HPD34_SLEWN 25 25 DC_GPIO_HPD56_SLEWN 26 26 DC_GPIO_HPD_RESBIASEN 27 27 DC_GPIO_HPD12_COMPSEL 28 28 DC_GPIO_HPD34_COMPSEL 29 29 DC_GPIO_HPD56_COMPSEL 30 30 regDC_GPIO_RXEN 0 0x2919 19 0 2 DC_GPIO_GENERICA_RXEN 0 0 DC_GPIO_GENERICB_RXEN 1 1 DC_GPIO_GENERICC_RXEN 2 2 DC_GPIO_GENERICD_RXEN 3 3 DC_GPIO_GENERICE_RXEN 4 4 DC_GPIO_GENERICF_RXEN 5 5 DC_GPIO_GENERICG_RXEN 6 6 DC_GPIO_HSYNCA_RXEN 8 8 DC_GPIO_VSYNCA_RXEN 9 9 DC_GPIO_GENLK_CLK_RXEN 10 10 DC_GPIO_GENLK_VSYNC_RXEN 11 11 DC_GPIO_SWAPLOCK_A_RXEN 12 12 DC_GPIO_SWAPLOCK_B_RXEN 13 13 DC_GPIO_HPD1_RXEN 14 14 DC_GPIO_HPD2_RXEN 15 15 DC_GPIO_HPD3_RXEN 16 16 DC_GPIO_HPD4_RXEN 17 17 DC_GPIO_HPD5_RXEN 18 18 DC_GPIO_HPD6_RXEN 19 19 regDC_GPIO_PULLUPEN 0 0x291a 15 0 2 DC_GPIO_GENERICA_PU_EN 0 0 DC_GPIO_GENERICB_PU_EN 1 1 DC_GPIO_GENERICC_PU_EN 2 2 DC_GPIO_GENERICD_PU_EN 3 3 DC_GPIO_GENERICE_PU_EN 4 4 DC_GPIO_GENERICF_PU_EN 5 5 DC_GPIO_GENERICG_PU_EN 6 6 DC_GPIO_HSYNCA_PU_EN 8 8 DC_GPIO_VSYNCA_PU_EN 9 9 DC_GPIO_HPD1_PU_EN 14 14 DC_GPIO_HPD2_PU_EN 15 15 DC_GPIO_HPD3_PU_EN 16 16 DC_GPIO_HPD4_PU_EN 17 17 DC_GPIO_HPD5_PU_EN 18 18 DC_GPIO_HPD6_PU_EN 19 19 regDC_GPIO_AUX_CTRL_3 0 0x291b 18 0 2 AUX1_NEN_RTERM 0 0 AUX2_NEN_RTERM 1 1 AUX3_NEN_RTERM 2 2 AUX4_NEN_RTERM 3 3 AUX5_NEN_RTERM 4 4 AUX6_NEN_RTERM 5 5 AUX1_DP_DN_SWAP 8 8 AUX2_DP_DN_SWAP 9 9 AUX3_DP_DN_SWAP 10 10 AUX4_DP_DN_SWAP 11 11 AUX5_DP_DN_SWAP 12 12 AUX6_DP_DN_SWAP 13 13 AUX1_HYS_TUNE 16 17 AUX2_HYS_TUNE 18 19 AUX3_HYS_TUNE 20 21 AUX4_HYS_TUNE 22 23 AUX5_HYS_TUNE 24 25 AUX6_HYS_TUNE 26 27 regDC_GPIO_AUX_CTRL_4 0 0x291c 6 0 2 AUX1_AUX_CTRL 0 3 AUX2_AUX_CTRL 4 7 AUX3_AUX_CTRL 8 11 AUX4_AUX_CTRL 12 15 AUX5_AUX_CTRL 16 19 AUX6_AUX_CTRL 20 23 regDC_GPIO_AUX_CTRL_5 0 0x291d 24 0 2 AUX1_VOD_TUNE 0 1 AUX2_VOD_TUNE 2 3 AUX3_VOD_TUNE 4 5 AUX4_VOD_TUNE 6 7 AUX5_VOD_TUNE 8 9 AUX6_VOD_TUNE 10 11 DDC_PAD1_I2CMODE 12 12 DDC_PAD2_I2CMODE 13 13 DDC_PAD3_I2CMODE 14 14 DDC_PAD4_I2CMODE 15 15 DDC_PAD5_I2CMODE 16 16 DDC_PAD6_I2CMODE 17 17 DDC1_I2C_VPH_1V2_EN 18 18 DDC2_I2C_VPH_1V2_EN 19 19 DDC3_I2C_VPH_1V2_EN 20 20 DDC4_I2C_VPH_1V2_EN 21 21 DDC5_I2C_VPH_1V2_EN 22 22 DDC6_I2C_VPH_1V2_EN 23 23 DDC1_PAD_I2C_CTRL 24 24 DDC2_PAD_I2C_CTRL 25 25 DDC3_PAD_I2C_CTRL 26 26 DDC4_PAD_I2C_CTRL 27 27 DDC5_PAD_I2C_CTRL 28 28 DDC6_PAD_I2C_CTRL 29 29 regAUXI2C_PAD_ALL_PWR_OK 0 0x291e 6 0 2 AUXI2C_PHY1_ALL_PWR_OK 0 0 AUXI2C_PHY2_ALL_PWR_OK 1 1 AUXI2C_PHY3_ALL_PWR_OK 2 2 AUXI2C_PHY4_ALL_PWR_OK 3 3 AUXI2C_PHY5_ALL_PWR_OK 4 4 AUXI2C_PHY6_ALL_PWR_OK 5 5 regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED0 0 0x2a00 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED1 0 0x2a01 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED2 0 0x2a02 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED3 0 0x2a03 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED4 0 0x2a04 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED5 0 0x2a05 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED6 0 0x2a06 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED7 0 0x2a07 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED8 0 0x2a08 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED9 0 0x2a09 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED10 0 0x2a0a 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED11 0 0x2a0b 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED12 0 0x2a0c 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED13 0 0x2a0d 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED14 0 0x2a0e 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED15 0 0x2a0f 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED16 0 0x2a10 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED17 0 0x2a11 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED18 0 0x2a12 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED19 0 0x2a13 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED20 0 0x2a14 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED21 0 0x2a15 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED22 0 0x2a16 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED23 0 0x2a17 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED24 0 0x2a18 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED25 0 0x2a19 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED26 0 0x2a1a 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED27 0 0x2a1b 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED28 0 0x2a1c 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED29 0 0x2a1d 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED30 0 0x2a1e 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED31 0 0x2a1f 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED32 0 0x2a20 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED33 0 0x2a21 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED34 0 0x2a22 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED35 0 0x2a23 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED36 0 0x2a24 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED37 0 0x2a25 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED38 0 0x2a26 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED39 0 0x2a27 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED40 0 0x2a28 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED41 0 0x2a29 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED42 0 0x2a2a 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED43 0 0x2a2b 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED44 0 0x2a2c 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED45 0 0x2a2d 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED46 0 0x2a2e 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED47 0 0x2a2f 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED48 0 0x2a30 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED49 0 0x2a31 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED50 0 0x2a32 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED51 0 0x2a33 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED52 0 0x2a34 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED53 0 0x2a35 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED54 0 0x2a36 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED55 0 0x2a37 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED56 0 0x2a38 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED57 0 0x2a39 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED0 0 0x2ad8 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED1 0 0x2ad9 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED2 0 0x2ada 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED3 0 0x2adb 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED4 0 0x2adc 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED5 0 0x2add 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED6 0 0x2ade 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED7 0 0x2adf 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED8 0 0x2ae0 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED9 0 0x2ae1 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED10 0 0x2ae2 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED11 0 0x2ae3 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED12 0 0x2ae4 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED13 0 0x2ae5 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED14 0 0x2ae6 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED15 0 0x2ae7 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED16 0 0x2ae8 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED17 0 0x2ae9 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED18 0 0x2aea 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED19 0 0x2aeb 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED20 0 0x2aec 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED21 0 0x2aed 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED22 0 0x2aee 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED23 0 0x2aef 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED24 0 0x2af0 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED25 0 0x2af1 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED26 0 0x2af2 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED27 0 0x2af3 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED28 0 0x2af4 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED29 0 0x2af5 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED30 0 0x2af6 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED31 0 0x2af7 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED32 0 0x2af8 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED33 0 0x2af9 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED34 0 0x2afa 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED35 0 0x2afb 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED36 0 0x2afc 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED37 0 0x2afd 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED38 0 0x2afe 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED39 0 0x2aff 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED40 0 0x2b00 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED41 0 0x2b01 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED42 0 0x2b02 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED43 0 0x2b03 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED44 0 0x2b04 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED45 0 0x2b05 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED46 0 0x2b06 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED47 0 0x2b07 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED48 0 0x2b08 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED49 0 0x2b09 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED50 0 0x2b0a 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED51 0 0x2b0b 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED52 0 0x2b0c 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED53 0 0x2b0d 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED54 0 0x2b0e 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED55 0 0x2b0f 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED56 0 0x2b10 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED57 0 0x2b11 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED0 0 0x2bb0 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED1 0 0x2bb1 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED2 0 0x2bb2 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED3 0 0x2bb3 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED4 0 0x2bb4 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED5 0 0x2bb5 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED6 0 0x2bb6 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED7 0 0x2bb7 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED8 0 0x2bb8 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED9 0 0x2bb9 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED10 0 0x2bba 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED11 0 0x2bbb 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED12 0 0x2bbc 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED13 0 0x2bbd 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED14 0 0x2bbe 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED15 0 0x2bbf 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED16 0 0x2bc0 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED17 0 0x2bc1 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED18 0 0x2bc2 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED19 0 0x2bc3 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED20 0 0x2bc4 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED21 0 0x2bc5 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED22 0 0x2bc6 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED23 0 0x2bc7 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED24 0 0x2bc8 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED25 0 0x2bc9 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED26 0 0x2bca 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED27 0 0x2bcb 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED28 0 0x2bcc 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED29 0 0x2bcd 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED30 0 0x2bce 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED31 0 0x2bcf 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED32 0 0x2bd0 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED33 0 0x2bd1 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED34 0 0x2bd2 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED35 0 0x2bd3 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED36 0 0x2bd4 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED37 0 0x2bd5 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED38 0 0x2bd6 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED39 0 0x2bd7 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED40 0 0x2bd8 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED41 0 0x2bd9 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED42 0 0x2bda 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED43 0 0x2bdb 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED44 0 0x2bdc 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED45 0 0x2bdd 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED46 0 0x2bde 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED47 0 0x2bdf 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED48 0 0x2be0 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED49 0 0x2be1 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED50 0 0x2be2 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED51 0 0x2be3 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED52 0 0x2be4 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED53 0 0x2be5 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED54 0 0x2be6 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED55 0 0x2be7 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED56 0 0x2be8 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED57 0 0x2be9 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED0 0 0x2c88 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED1 0 0x2c89 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED2 0 0x2c8a 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED3 0 0x2c8b 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED4 0 0x2c8c 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED5 0 0x2c8d 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED6 0 0x2c8e 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED7 0 0x2c8f 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED8 0 0x2c90 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED9 0 0x2c91 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED10 0 0x2c92 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED11 0 0x2c93 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED12 0 0x2c94 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED13 0 0x2c95 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED14 0 0x2c96 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED15 0 0x2c97 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED16 0 0x2c98 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED17 0 0x2c99 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED18 0 0x2c9a 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED19 0 0x2c9b 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED20 0 0x2c9c 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED21 0 0x2c9d 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED22 0 0x2c9e 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED23 0 0x2c9f 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED24 0 0x2ca0 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED25 0 0x2ca1 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED26 0 0x2ca2 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED27 0 0x2ca3 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED28 0 0x2ca4 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED29 0 0x2ca5 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED30 0 0x2ca6 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED31 0 0x2ca7 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED32 0 0x2ca8 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED33 0 0x2ca9 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED34 0 0x2caa 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED35 0 0x2cab 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED36 0 0x2cac 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED37 0 0x2cad 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED38 0 0x2cae 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED39 0 0x2caf 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED40 0 0x2cb0 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED41 0 0x2cb1 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED42 0 0x2cb2 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED43 0 0x2cb3 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED44 0 0x2cb4 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED45 0 0x2cb5 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED46 0 0x2cb6 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED47 0 0x2cb7 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED48 0 0x2cb8 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED49 0 0x2cb9 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED50 0 0x2cba 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED51 0 0x2cbb 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED52 0 0x2cbc 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED53 0 0x2cbd 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED54 0 0x2cbe 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED55 0 0x2cbf 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED56 0 0x2cc0 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED57 0 0x2cc1 1 0 2 UNIPHY_MACRO_CNTL_RESERVED 0 31 ixDPCSSYS_CR0_SUP_DIG_IDCODE_LO 2 0x0 1 0 4294967295 DATA 0 0 ixDPCSSYS_CR0_SUP_DIG_IDCODE_HI 2 0x1 1 0 4294967295 DATA 0 0 ixDPCSSYS_CR0_SUP_DIG_REFCLK_OVRD_IN 2 0x2 12 0 4294967295 REF_CLK_EN 0 0 REF_CLK_EN_OVRD_EN 1 1 REF_USE_PAD 2 2 REF_USE_PAD_OVRD_EN 3 3 REF_CLK_RANGE 4 8 REF_CLK_RANGE_OVRD_EN 9 9 BG_EN 10 10 BG_EN_OVRD_EN 11 11 HDMIMODE_EN 12 12 HDMIMODE_ENABLE_OVRD_EN 13 13 SUP_PRE_HP_OVRD 14 14 SUP_PRE_HP_OVRD_EN 15 15 ixDPCSSYS_CR0_SUP_DIG_MPLLA_DIV_CLK_OVRD_IN 2 0x3 4 0 4294967295 MPLLA_DIV_CLK_EN 0 0 MPLLA_DIV_MULTIPLIER 1 8 MPLLA_DIV_OVRD_EN 9 9 RESERVED_15_10 10 15 ixDPCSSYS_CR0_SUP_DIG_MPLLA_HDMI_CLK_OVRD_IN 2 0x4 4 0 4294967295 MPLLA_HDMI_PIXEL_CLK_DIV 0 1 MPLLA_HDMI_DIV 2 4 MPLLA_HDMI_OVRD_EN 5 5 RESERVED_15_6 6 15 ixDPCSSYS_CR0_SUP_DIG_MPLLB_DIV_CLK_OVRD_IN 2 0x5 4 0 4294967295 MPLLB_DIV_CLK_EN 0 0 MPLLB_DIV_MULTIPLIER 1 8 MPLLB_DIV_OVRD_EN 9 9 RESERVED_15_10 10 15 ixDPCSSYS_CR0_SUP_DIG_MPLLB_HDMI_CLK_OVRD_IN 2 0x6 4 0 4294967295 MPLLB_HDMI_PIXEL_CLK_DIV 0 1 MPLLB_HDMI_DIV 2 4 MPLLB_HDMI_OVRD_EN 5 5 RESERVED_15_6 6 15 ixDPCSSYS_CR0_SUP_DIG_MPLLA_OVRD_IN_0 2 0x7 12 0 4294967295 MPLLA_EN 0 0 MPLLA_DIV5_CLK_EN 1 1 MPLLA_TX_CLK_DIV 2 4 OVRD_EN 5 5 MPLLA_V2I 6 7 MPLLA_STANDBY 8 8 MPLLA_FREQ_VCO 9 10 MPLLA_CAL_FORCE 11 11 MPLL_FRACN_EN 12 12 MPLLA_CLK_SYNC_OVRD 13 13 MPLLA_CLK_SYNC_OVRD_EN 14 14 RESERVED_15_15 15 15 ixDPCSSYS_CR0_SUP_DIG_MPLLA_OVRD_IN_1 2 0x8 2 0 4294967295 MPLLA_MULTIPLIER 0 11 RESERVED_15_12 12 15 ixDPCSSYS_CR0_SUP_DIG_MPLLA_OVRD_IN_2 2 0x9 7 0 4294967295 MPLLA_SSC_EN 0 0 MPLLA_SSC_OVRD_EN 1 1 MPLLA_SSC_UP_SPREAD 2 2 MPLLA_PMIX_EN 3 3 MPLLA_WORD_DIV2_EN 4 4 MPLLA_FRACN_CFG_UPDATE_EN 5 5 RESERVED_15_6 6 15 ixDPCSSYS_CR0_SUP_DIG_MPLLA_SSC_PEAK_1 2 0xa 1 0 4294967295 MPLLA_SSC_PEAK_15_0 0 15 ixDPCSSYS_CR0_SUP_DIG_MPLLA_SSC_PEAK_2 2 0xb 2 0 4294967295 MPLLA_SSC_PEAK_19_16 0 3 RESERVED_15_4 4 15 ixDPCSSYS_CR0_SUP_DIG_MPLLA_SSC_STEPSIZE_1 2 0xc 1 0 4294967295 MPLLA_SSC_STEPSIZE_15_0 0 15 ixDPCSSYS_CR0_SUP_DIG_MPLLA_SSC_STEPSIZE_2 2 0xd 2 0 4294967295 MPLLA_SSC_STEPSIZE_20_16 0 4 RESERVED_15_5 5 15 ixDPCSSYS_CR0_SUP_DIG_MPLLA_OVRD_IN_3 2 0xe 1 0 4294967295 MPLLA_FRACN_QUOT 0 15 ixDPCSSYS_CR0_SUP_DIG_MPLLA_OVRD_IN_4 2 0xf 1 0 4294967295 MPLLA_FRACN_REM 0 15 ixDPCSSYS_CR0_SUP_DIG_MPLLA_OVRD_IN_5 2 0x10 1 0 4294967295 MPLLA_FRACN_DEN 0 15 ixDPCSSYS_CR0_SUP_DIG_MPLLA_CP_OVRD_IN 2 0x11 3 0 4294967295 MPLLA_CP_PROP 0 6 MPLLA_CP_INT 7 13 RESERVED_15_14 14 15 ixDPCSSYS_CR0_SUP_DIG_MPLLA_CP_GS_OVRD_IN 2 0x12 4 0 4294967295 MPLLA_CP_PROP_GS 0 6 MPLLA_CP_PROP_GS_OVR_EN 7 7 MPLLA_CP_INT_GS 8 14 MPLLA_CP_INT_GS_OVR_EN 15 15 ixDPCSSYS_CR0_SUP_DIG_MPLLB_OVRD_IN_0 2 0x13 12 0 4294967295 MPLLB_EN 0 0 MPLLB_DIV5_CLK_EN 1 1 MPLLB_TX_CLK_DIV 2 4 OVRD_EN 5 5 MPLLB_V2I 6 7 MPLLB_STANDBY 8 8 MPLLB_FREQ_VCO 9 10 MPLLB_CAL_FORCE 11 11 MPLL_FRACN_EN 12 12 MPLLB_CLK_SYNC_OVRD 13 13 MPLLB_CLK_SYNC_OVRD_EN 14 14 RESERVED_15_15 15 15 ixDPCSSYS_CR0_SUP_DIG_MPLLB_OVRD_IN_1 2 0x14 2 0 4294967295 MPLLB_MULTIPLIER 0 11 RESERVED_15_12 12 15 ixDPCSSYS_CR0_SUP_DIG_MPLLB_OVRD_IN_2 2 0x15 7 0 4294967295 MPLLB_SSC_EN 0 0 MPLLB_SSC_OVRD_EN 1 1 MPLLB_SSC_UP_SPREAD 2 2 MPLLB_PMIX_EN 3 3 MPLLB_WORD_DIV2_EN 4 4 MPLLB_FRACN_CFG_UPDATE_EN 5 5 RESERVED_15_6 6 15 ixDPCSSYS_CR0_SUP_DIG_MPLLB_SSC_PEAK_1 2 0x16 1 0 4294967295 MPLLB_SSC_PEAK_15_0 0 15 ixDPCSSYS_CR0_SUP_DIG_MPLLB_SSC_PEAK_2 2 0x17 2 0 4294967295 MPLLB_SSC_PEAK_19_16 0 3 RESERVED_15_4 4 15 ixDPCSSYS_CR0_SUP_DIG_MPLLB_SSC_STEPSIZE_1 2 0x18 1 0 4294967295 MPLLB_SSC_STEPSIZE_15_0 0 15 ixDPCSSYS_CR0_SUP_DIG_MPLLB_SSC_STEPSIZE_2 2 0x19 2 0 4294967295 MPLLB_SSC_STEPSIZE_20_16 0 4 RESERVED_15_5 5 15 ixDPCSSYS_CR0_SUP_DIG_MPLLB_OVRD_IN_3 2 0x1a 1 0 4294967295 MPLLB_FRACN_QUOT 0 15 ixDPCSSYS_CR0_SUP_DIG_MPLLB_OVRD_IN_4 2 0x1b 1 0 4294967295 MPLLB_FRACN_REM 0 15 ixDPCSSYS_CR0_SUP_DIG_MPLLB_OVRD_IN_5 2 0x1c 1 0 4294967295 MPLLB_FRACN_DEN 0 15 ixDPCSSYS_CR0_SUP_DIG_MPLLB_CP_OVRD_IN 2 0x1d 3 0 4294967295 MPLLB_CP_PROP 0 6 MPLLB_CP_INT 7 13 RESERVED_15_14 14 15 ixDPCSSYS_CR0_SUP_DIG_MPLLB_CP_GS_OVRD_IN 2 0x1e 4 0 4294967295 MPLLB_CP_PROP_GS 0 6 MPLLB_CP_PROP_GS_OVR_EN 7 7 MPLLB_CP_INT_GS 8 14 MPLLB_CP_INT_GS_OVR_EN 15 15 ixDPCSSYS_CR0_SUP_DIG_SUP_OVRD_IN 2 0x1f 8 0 4294967295 PRESCALER_OVRD_EN 0 0 RTUNE_REQ 1 1 RTUNE_OVRD_EN 2 2 TX_CAL_CODE 3 6 TX_CAL_CODE_EN 7 7 REF_ALT_CLK_LP_SEL_OVRD 8 8 REF_ALT_CLK_LP_SEL_OVRD_EN 9 9 RESERVED_15_10 10 15 ixDPCSSYS_CR0_SUP_DIG_PRESCALER_OVRD_IN 2 0x20 6 0 4294967295 DCO_RANGE 0 1 DCO_FINETUNE 2 7 REF_CLK_MPLLB_DIV 8 10 REF_CLK_MPLLA_DIV 11 13 REF_CLKDET_RESULT 14 14 REF_CLKDET_EN 15 15 ixDPCSSYS_CR0_SUP_DIG_SUP_OVRD_OUT 2 0x21 12 0 4294967295 RTUNE_ACK 0 0 RTUNE_ACK_OVRD_EN 1 1 MPLLA_STATE 2 2 MPLLA_STATE_OVRD_EN 3 3 MPLLB_STATE 4 4 MPLLB_STATE_OVRD_EN 5 5 BG_LANE_STATE 6 6 BG_LANE_STATE_OVRD_EN 7 7 BG_SUP_STATE 8 8 BG_SUP_STATE_OVRD_EN 9 9 REF_CLK_ACK 10 10 RESERVED_15_11 11 15 ixDPCSSYS_CR0_SUP_DIG_LVL_OVRD_IN 2 0x22 7 0 4294967295 RX_VREF_CTRL 0 2 RX_VREF_CTRL_EN 3 3 TX_VBOOST_LVL 4 6 TX_VBOOST_LVL_EN 7 7 SUP_RX_VCO_VREF_SEL_OVR 8 10 SUP_RX_VCO_VREF_SEL_OVR_EN 11 11 RESERVED_15_12 12 15 ixDPCSSYS_CR0_SUP_DIG_MPLLA_ASIC_IN_0 2 0x24 9 0 4294967295 MPLLA_EN 0 0 MPLLA_DIV5_CLK_EN 1 1 MPLLA_TX_CLK_DIV 2 4 MPLLA_V2I 5 6 MPLLA_STANDBY 7 7 MPLLA_FREQ_VCO 8 9 MPLLA_CAL_FORCE 10 10 MPLLA_FRACN_EN 11 11 RESERVED_15_12 12 15 ixDPCSSYS_CR0_SUP_DIG_MPLLA_ASIC_IN_1 2 0x25 2 0 4294967295 MPLLA_MULTIPLIER 0 11 RESERVED_15_12 12 15 ixDPCSSYS_CR0_SUP_DIG_MPLLA_ASIC_IN_2 2 0x26 7 0 4294967295 MPLLA_SSC_EN 0 0 MPLLA_SSC_UP_SPREAD 1 1 MPLLA_PMIX_EN 2 2 MPLLA_WORD_DIV2_EN 3 3 MPLLA_FRACN_CFG_UPDATE_EN 4 4 MPLLA_CLK_SYNC 5 5 RESERVED_15_6 6 15 ixDPCSSYS_CR0_SUP_DIG_MPLLA_ASIC_IN_3 2 0x27 1 0 4294967295 MPLLA_SSC_PEAK_15_0 0 15 ixDPCSSYS_CR0_SUP_DIG_MPLLA_ASIC_IN_4 2 0x28 2 0 4294967295 MPLLA_SSC_PEAK_19_16 0 3 RESERVED_15_4 4 15 ixDPCSSYS_CR0_SUP_DIG_MPLLA_ASIC_IN_5 2 0x29 1 0 4294967295 MPLLA_SSC_STEPSIZE_15_0 0 15 ixDPCSSYS_CR0_SUP_DIG_MPLLA_ASIC_IN_6 2 0x2a 2 0 4294967295 MPLLA_SSC_STEPSIZE_20_16 0 3 RESERVED_15_4 4 15 ixDPCSSYS_CR0_SUP_DIG_MPLLB_ASIC_IN_0 2 0x2b 9 0 4294967295 MPLLB_EN 0 0 MPLLB_DIV5_CLK_EN 1 1 MPLLB_TX_CLK_DIV 2 4 MPLLB_V2I 5 6 MPLLB_STANDBY 7 7 MPLLB_FREQ_VCO 8 9 MPLLB_CAL_FORCE 10 10 MPLLB_FRACN_EN 11 11 RESERVED_15_12 12 15 ixDPCSSYS_CR0_SUP_DIG_MPLLB_ASIC_IN_1 2 0x2c 2 0 4294967295 MPLLB_MULTIPLIER 0 11 RESERVED_15_12 12 15 ixDPCSSYS_CR0_SUP_DIG_MPLLB_ASIC_IN_2 2 0x2d 7 0 4294967295 MPLLB_SSC_EN 0 0 MPLLB_SSC_UP_SPREAD 1 1 MPLLB_PMIX_EN 2 2 MPLLB_WORD_DIV2_EN 3 3 MPLLB_FRACN_CFG_UPDATE_EN 4 4 MPLLB_CLK_SYNC 5 5 RESERVED_15_6 6 15 ixDPCSSYS_CR0_SUP_DIG_MPLLB_ASIC_IN_3 2 0x2e 1 0 4294967295 MPLLB_SSC_PEAK_15_0 0 15 ixDPCSSYS_CR0_SUP_DIG_MPLLB_ASIC_IN_4 2 0x2f 2 0 4294967295 MPLLB_SSC_PEAK_19_16 0 3 RESERVED_15_4 4 15 ixDPCSSYS_CR0_SUP_DIG_MPLLB_ASIC_IN_5 2 0x30 1 0 4294967295 MPLLB_SSC_STEPSIZE_15_0 0 15 ixDPCSSYS_CR0_SUP_DIG_MPLLB_ASIC_IN_6 2 0x31 2 0 4294967295 MPLLB_SSC_STEPSIZE_20_16 0 3 RESERVED_15_4 4 15 ixDPCSSYS_CR0_SUP_DIG_MPLLA_DIV_CLK_ASIC_IN 2 0x32 3 0 4294967295 MPLLA_DIV_CLK_EN 0 0 MPLLA_DIV_MULTIPLIER 1 8 RESERVED_15_9 9 15 ixDPCSSYS_CR0_SUP_DIG_MPLLA_HDMI_CLK_ASIC_IN 2 0x33 3 0 4294967295 MPLLA_HDMI_PIXEL_CLK_DIV 0 1 MPLLA_HDMI_DIV 2 4 RESERVED_15_5 5 15 ixDPCSSYS_CR0_SUP_DIG_MPLLB_DIV_CLK_ASIC_IN 2 0x34 3 0 4294967295 MPLLB_DIV_CLK_EN 0 0 MPLLB_DIV_MULTIPLIER 1 8 RESERVED_15_9 9 15 ixDPCSSYS_CR0_SUP_DIG_MPLLB_HDMI_CLK_ASIC_IN 2 0x35 3 0 4294967295 MPLLB_HDMI_PIXEL_CLK_DIV 0 1 MPLLB_HDMI_DIV 2 4 RESERVED_15_5 5 15 ixDPCSSYS_CR0_SUP_DIG_ASIC_IN 2 0x36 12 0 4294967295 PHY_RESET 0 0 REF_CLK_EN 1 1 REF_USE_PAD 2 2 TEST_BURNIN 3 3 TEST_POWERDOWN 4 4 RTUNE_REQ 5 5 RTUNE_ACK 6 6 MPLLA_STATE 7 7 MPLLB_STATE 8 8 TEST_TX_REF_CLK_EN 9 9 REF_ALT_CLK_LP_SEL 10 10 RESERVED_15_11 11 15 ixDPCSSYS_CR0_SUP_DIG_LVL_ASIC_IN 2 0x37 4 0 4294967295 RX_VREF_CTRL 0 2 TX_VBOOST_LVL 3 5 SUP_RX_VCO_VREF_SEL 6 8 RESERVED_15_9 9 15 ixDPCSSYS_CR0_SUP_DIG_BANDGAP_ASIC_IN 2 0x38 2 0 4294967295 BG_EN 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR0_SUP_DIG_MPLLA_CP_ASIC_IN 2 0x39 3 0 4294967295 MPLLA_CP_PROP 0 6 MPLLA_CP_INT 7 13 RESERVED_15_14 14 15 ixDPCSSYS_CR0_SUP_DIG_MPLLA_CP_GS_ASIC_IN 2 0x3a 3 0 4294967295 MPLLA_CP_PROP_GS 0 6 MPLLA_CP_INT_GS 7 13 RESERVED_15_14 14 15 ixDPCSSYS_CR0_SUP_DIG_MPLLB_CP_ASIC_IN 2 0x3b 3 0 4294967295 MPLLB_CP_PROP 0 6 MPLLB_CP_INT 7 13 RESERVED_15_14 14 15 ixDPCSSYS_CR0_SUP_DIG_MPLLB_CP_GS_ASIC_IN 2 0x3c 3 0 4294967295 MPLLB_CP_PROP_GS 0 6 MPLLB_CP_INT_GS 7 13 RESERVED_15_14 14 15 ixDPCSSYS_CR0_SUP_ANA_PRESCALER_CTRL 2 0x40 7 0 4294967295 PSCALER_ATB_SELECT 0 0 PSCALER_MEAS_VREG 0 0 PSCALER_OVRD_FAST_START 0 0 PSCALER_FAST_START_REG 0 0 PSCALER_VREG_BOOST 0 0 PSCALER_HYST_REF 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR0_SUP_ANA_RTUNE_CTRL 2 0x41 9 0 4294967295 RT_ATB 0 0 RT_SEL_ATBF 0 0 RT_SEL_ATBP 0 0 RT_VP4O8_EN 0 0 RT_DAC_CHOP 0 0 RT_DAC_MODE 0 0 RT_EN_FRCON 0 0 PSCALER_VREG_FB_DIV_CTRL 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR0_SUP_ANA_BG1 2 0x42 6 0 4294967295 SUP_SEL_VBG_VREF 0 0 SUP_SEL_VPHUD_VREF 0 0 NC4 4 4 SUP_SEL_VPLL_REF 0 0 RT_VREF_SEL 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR0_SUP_ANA_BG2 2 0x43 9 0 4294967295 SUP_BYPASS_BG 0 0 SUP_CHOP_EN 0 0 SUP_TEMP_MEAS 0 0 VPHUD_SELREF 0 0 ATB_EXT_MEAS_EN 0 0 RT_TX_OFFSET_EN 0 0 SUP_SEL_TX_SWING_VREF 0 0 PSCALER_VREG_OVERRIDE_RING_CTRL 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR0_SUP_ANA_SWITCH_PWR_MEAS 2 0x44 3 0 4294967295 SUP_ATB_SW 0 0 SUP_TIE 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR0_SUP_ANA_BG3 2 0x45 4 0 4294967295 SUP_SEL_RX_VCO_TC_VREF 0 0 SUP_SEL_RX_CAL_VREF 0 0 NC7_4 4 7 RESERVED_15_8 8 15 ixDPCSSYS_CR0_SUP_ANA_MPLLA_MISC1 2 0x46 7 0 4294967295 OVRD_GEAR_RC_FILT 0 0 OVRD_TEST_RC_FILT 0 0 TEST_VREG_DIV 0 0 VBG_EN 0 0 COUNT_SEL_LOCK 0 0 PHASE_SEL_LOCK 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR0_SUP_ANA_MPLLA_MISC2 2 0x47 8 0 4294967295 OVRD_PR_BYPASS 0 0 PR_BYPASS 0 0 OVRD_GEARSHIFT 0 0 GEARSHIFT_REG 0 0 TEST_LOCK_GEAR 0 0 EN_CAL_SPO 0 0 TEST_BOOST 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR0_SUP_ANA_MPLLA_OVRD 2 0x48 9 0 4294967295 OVRD_ENABLE 0 0 ENABLE_REG 0 0 OVRD_CAL 0 0 CAL_REG 0 0 OVRD_FB_CLK_EN 0 0 FB_CLK_EN_REG 0 0 OVRD_RESET 0 0 RESET_REG 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR0_SUP_ANA_MPLLA_ATB1 2 0x49 3 0 4294967295 MEAS_IV_WRAP 0 0 ATB_SELECT 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR0_SUP_ANA_MPLLA_ATB2 2 0x4a 2 0 4294967295 MEAS_IV_PLL 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR0_SUP_ANA_MPLLA_ATB3 2 0x4b 3 0 4294967295 MEAS_IV_BIAS 0 0 CTR_UPLL_TUNNING 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR0_SUP_ANA_MPLLA_CTR1 2 0x4c 5 0 4294967295 CTR_ICP_INT 0 0 CTR_VREF_EN 0 0 CTR_VREF_VMARG 0 0 CTR_CP_PLL 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR0_SUP_ANA_MPLLA_CTR2 2 0x4d 2 0 4294967295 CTR_REGS_PLL 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR0_SUP_ANA_MPLLA_CTR3 2 0x4e 4 0 4294967295 CTR_REGS_CP_PLL 0 0 CTR_SPO_PLL 0 0 CTR_VINT_CAP 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR0_SUP_ANA_MPLLA_CTR4 2 0x4f 7 0 4294967295 CTR_CP_8X 0 0 CTR_FIL_REG 0 0 CTR_CP_PROP_REF 0 0 CTR_DOUBLER_GAIN 0 0 CTR_TEST_CASC 0 0 CTR_RC_FITER 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR0_SUP_ANA_MPLLA_CTR5 2 0x50 8 0 4294967295 CTR_STANDBY_MODE 0 0 CTR_LEG_SR_CON 0 0 CTR_VREG_RING_OVERRIDE 0 0 CTR_SPO_SPEED_OVERRIDE 0 0 CTR_BYPASS_LOCK_SPO_CAL 0 0 CTR_LOCK_SPO_CAL 0 0 CTR_UPLL_RESERVED 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR0_SUP_ANA_MPLLA_RESERVED1 2 0x51 8 0 4294967295 CTR_REF_FBK_BYPASS 0 0 CTR_BYPASS_TX 0 0 CTR_VREG_CLK_BYPASS 0 0 CTR_VREG_CLK_PMIX_BYPASS 0 0 CTR_VREG_RIGHT_BYPASS 0 0 CTR_VREG_LEFT_BYPASS 0 0 CTR_LEFT_RIGHT_GAIN 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR0_SUP_ANA_MPLLA_RESERVED2 2 0x52 5 0 4294967295 CTR_DLL_MODE_90 0 0 CTR_DLL_RESERVED 0 0 CTR_DIV24_DSQ_ENZ 0 0 CTR_DIV4 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR0_SUP_ANA_MPLLB_MISC1 2 0x53 7 0 4294967295 OVRD_GEAR_RC_FILT 0 0 OVRD_TEST_RC_FILT 0 0 TEST_VREG_DIV 0 0 VBG_EN 0 0 COUNT_SEL_LOCK 0 0 PHASE_SEL_LOCK 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR0_SUP_ANA_MPLLB_MISC2 2 0x54 8 0 4294967295 OVRD_PR_BYPASS 0 0 PR_BYPASS 0 0 OVRD_GEARSHIFT 0 0 GEARSHIFT_REG 0 0 TEST_LOCK_GEAR 0 0 EN_CAL_SPO 0 0 TEST_BOOST 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR0_SUP_ANA_MPLLB_OVRD 2 0x55 9 0 4294967295 OVRD_ENABLE 0 0 ENABLE_REG 0 0 OVRD_CAL 0 0 CAL_REG 0 0 OVRD_FB_CLK_EN 0 0 FB_CLK_EN_REG 0 0 OVRD_RESET 0 0 RESET_REG 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR0_SUP_ANA_MPLLB_ATB1 2 0x56 3 0 4294967295 MEAS_IV_WRAP 0 0 ATB_SELECT 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR0_SUP_ANA_MPLLB_ATB2 2 0x57 2 0 4294967295 MEAS_IV_PLL 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR0_SUP_ANA_MPLLB_ATB3 2 0x58 3 0 4294967295 MEAS_IV_BIAS 0 0 CTR_UPLL_TUNNING 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR0_SUP_ANA_MPLLB_CTR1 2 0x59 5 0 4294967295 CTR_ICP_INT 0 0 CTR_VREF_EN 0 0 CTR_VREF_VMARG 0 0 CTR_CP_PLL 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR0_SUP_ANA_MPLLB_CTR2 2 0x5a 2 0 4294967295 CTR_REGS_PLL 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR0_SUP_ANA_MPLLB_CTR3 2 0x5b 4 0 4294967295 CTR_REGS_CP_PLL 0 0 CTR_SPO_PLL 0 0 CTR_VINT_CAP 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR0_SUP_ANA_MPLLB_CTR4 2 0x5c 7 0 4294967295 CTR_CP_8X 0 0 CTR_FIL_REG 0 0 CTR_CP_PROP_REF 0 0 CTR_DOUBLER_GAIN 0 0 CTR_TEST_CASC 0 0 CTR_RC_FITER 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR0_SUP_ANA_MPLLB_CTR5 2 0x5d 8 0 4294967295 CTR_STANDBY_MODE 0 0 CTR_LEG_SR_CON 0 0 CTR_VREG_RING_OVERRIDE 0 0 CTR_SPO_SPEED_OVERRIDE 0 0 CTR_BYPASS_LOCK_SPO_CAL 0 0 CTR_LOCK_SPO_CAL 0 0 CTR_UPLL_RESERVED 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR0_SUP_ANA_MPLLB_RESERVED1 2 0x5e 8 0 4294967295 CTR_REF_FBK_BYPASS 0 0 CTR_BYPASS_TX 0 0 CTR_VREG_CLK_BYPASS 0 0 CTR_VREG_CLK_PMIX_BYPASS 0 0 CTR_VREG_RIGHT_BYPASS 0 0 CTR_VREG_LEFT_BYPASS 0 0 CTR_LEFT_RIGHT_GAIN 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR0_SUP_ANA_MPLLB_RESERVED2 2 0x5f 5 0 4294967295 CTR_DLL_MODE_90 0 0 CTR_DLL_RESERVED 0 0 CTR_DIV24_DSQ_ENZ 0 0 CTR_DIV4 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD 2 0x61 8 0 4294967295 OVRD_SEL 0 0 MPLL_FBDIGCLK_EN 1 1 MPLL_PCLK_EN 2 2 FAST_MPLL_PWRUP 3 3 FAST_MPLL_LOCK 4 4 DTB_SEL 5 9 DIV10_EN 10 10 RESERVED 11 15 ixDPCSSYS_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT 2 0x62 11 0 4294967295 FSM_STATE 0 3 MPLL_R_LANES 4 4 MPLL_L_LANES 5 5 MPLL_PCLK_EN 6 6 MPLL_OUTPUT_EN 7 7 MPLL_FBCLK_EN 8 8 MPLL_CAL 9 9 MPLL_RST 10 10 MPLL_ANA_EN 11 11 MPLL_LOCK 12 12 RESERVED_15_13 13 15 ixDPCSSYS_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE 2 0x63 3 0 4294967295 MAX_RANGE 0 4 DAC_IN 5 9 RESERVED_15_10 10 15 ixDPCSSYS_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_LOCK 2 0x64 3 0 4294967295 LOCK_TIME 0 7 STABLE_TIME 8 13 RESERVED_15_14 14 15 ixDPCSSYS_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS 2 0x65 2 0 4294967295 GEARSHIFT_TIME 0 7 PRESET_TIME 8 15 ixDPCSSYS_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE 2 0x66 3 0 4294967295 PWRDN_WAIT_TIME 0 5 PCLK_EN_TIME 6 11 RESERVED_15_12 12 15 ixDPCSSYS_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2 2 0x67 3 0 4294967295 PCLK_DIS_TIME 0 5 PWRDN_TIME 6 11 RESERVED_15_12 12 15 ixDPCSSYS_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_CAL 2 0x68 3 0 4294967295 MPLL_CAL 0 0 MPLL_CAL_OVRD_EN 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT 2 0x69 2 0 4294967295 MPLL_ANA_DAC_OUT 0 4 RESERVED_15_5 5 15 ixDPCSSYS_CR0_SUP_DIG_MPLLA_SSC_GEN_SPREAD_TYPE 2 0x6b 3 0 4294967295 SPREAD_TYPE 0 1 OVR_EN 2 2 RESERVED_15_3 3 15 ixDPCSSYS_CR0_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD 2 0x6d 8 0 4294967295 OVRD_SEL 0 0 MPLL_FBDIGCLK_EN 1 1 MPLL_PCLK_EN 2 2 FAST_MPLL_PWRUP 3 3 FAST_MPLL_LOCK 4 4 DTB_SEL 5 9 DIV10_EN 10 10 RESERVED 11 15 ixDPCSSYS_CR0_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT 2 0x6e 11 0 4294967295 FSM_STATE 0 3 MPLL_R_LANES 4 4 MPLL_L_LANES 5 5 MPLL_PCLK_EN 6 6 MPLL_OUTPUT_EN 7 7 MPLL_FBCLK_EN 8 8 MPLL_CAL 9 9 MPLL_RST 10 10 MPLL_ANA_EN 11 11 MPLL_LOCK 12 12 RESERVED_15_13 13 15 ixDPCSSYS_CR0_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE 2 0x6f 3 0 4294967295 MAX_RANGE 0 4 DAC_IN 5 9 RESERVED_15_10 10 15 ixDPCSSYS_CR0_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_LOCK 2 0x70 3 0 4294967295 LOCK_TIME 0 7 STABLE_TIME 8 13 RESERVED_15_14 14 15 ixDPCSSYS_CR0_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS 2 0x71 2 0 4294967295 GEARSHIFT_TIME 0 7 PRESET_TIME 8 15 ixDPCSSYS_CR0_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE 2 0x72 3 0 4294967295 PWRDN_WAIT_TIME 0 5 PCLK_EN_TIME 6 11 RESERVED_15_12 12 15 ixDPCSSYS_CR0_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2 2 0x73 3 0 4294967295 PCLK_DIS_TIME 0 5 PWRDN_TIME 6 11 RESERVED_15_12 12 15 ixDPCSSYS_CR0_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_CAL 2 0x74 3 0 4294967295 MPLL_CAL 0 0 MPLL_CAL_OVRD_EN 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR0_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT 2 0x75 2 0 4294967295 MPLL_ANA_DAC_OUT 0 4 RESERVED_15_5 5 15 ixDPCSSYS_CR0_SUP_DIG_MPLLB_SSC_GEN_SPREAD_TYPE 2 0x77 3 0 4294967295 SPREAD_TYPE 0 1 OVR_EN 2 2 RESERVED_15_3 3 15 ixDPCSSYS_CR0_SUP_DIG_CLK_RST_BG_PWRUP_TIME_0 2 0x78 3 0 4294967295 BG_SUP_EN_TIME 0 8 FAST_BG_WAIT 9 9 RESERVED_15_10 10 15 ixDPCSSYS_CR0_SUP_DIG_CLK_RST_BG_PWRUP_TIME_1 2 0x79 2 0 4294967295 BG_LANE_EN_TIME 0 8 RESERVED_15_9 9 15 ixDPCSSYS_CR0_SUP_DIG_CLK_RST_BG_PWRUP_TIME_2 2 0x7a 3 0 4294967295 BG_KICK_START_EN_TIME 0 7 BG_SUP_STATE_UPD_EN 8 8 RESERVED_15_9 9 15 ixDPCSSYS_CR0_SUP_DIG_CLK_RST_REF_PWRUP_TIME_0 2 0x7b 3 0 4294967295 REF_VREG_FAST_START_TIME 0 4 FAST_REF_WAIT 5 5 RESERVED_15_6 6 15 ixDPCSSYS_CR0_SUP_DIG_CLK_RST_REF_VPHUD 2 0x7c 3 0 4294967295 SUP_ANA_VPHUD_SELVPH_I 0 0 SUP_ANA_VPHUD_EN_I 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR0_SUP_DIG_RTUNE_CONFIG 2 0x81 5 0 4294967295 RX_CAL_EN 0 0 FAST_RTUNE 1 1 TX_CAL_EN 2 2 SUP_ANA_TERM_CTRL 3 5 RESERVED_15_6 6 15 ixDPCSSYS_CR0_SUP_DIG_RTUNE_STAT 2 0x82 3 0 4294967295 STAT 0 9 DTB_RTUNE 10 11 RESERVED_15_12 12 15 ixDPCSSYS_CR0_SUP_DIG_RTUNE_RX_SET_VAL 2 0x83 2 0 4294967295 RX_SET_VAL 0 5 RESERVED_15_6 6 15 ixDPCSSYS_CR0_SUP_DIG_RTUNE_TXDN_SET_VAL 2 0x84 2 0 4294967295 TXDN_SET_VAL 0 9 RESERVED_15_10 10 15 ixDPCSSYS_CR0_SUP_DIG_RTUNE_TXUP_SET_VAL 2 0x85 2 0 4294967295 TXUP_SET_VAL 0 9 RESERVED_15_10 10 15 ixDPCSSYS_CR0_SUP_DIG_RTUNE_RX_STAT 2 0x86 2 0 4294967295 RX_STAT 0 5 RESERVED_15_6 6 15 ixDPCSSYS_CR0_SUP_DIG_RTUNE_TXDN_STAT 2 0x87 2 0 4294967295 TXDN_STAT 0 9 RESERVED_15_10 10 15 ixDPCSSYS_CR0_SUP_DIG_RTUNE_TXUP_STAT 2 0x88 2 0 4294967295 TXUP_STAT 0 9 RESERVED_15_10 10 15 ixDPCSSYS_CR0_SUP_DIG_RTUNE_CONFIG_CNT0 2 0x89 4 0 4294967295 RT_RESULT_TIME 0 3 RT_EVAL_TIME 4 7 RT_RST_TIME 8 11 RT_ACK_TIME 12 15 ixDPCSSYS_CR0_SUP_DIG_RTUNE_CONFIG_CNT1 2 0x8a 3 0 4294967295 RT_TXDN_SETTLE_TIME 0 3 RT_PWRUP_TIME 4 8 RESERVED_15_9 9 15 ixDPCSSYS_CR0_SUP_DIG_RTUNE_TX_CAL_CODE 2 0x8b 2 0 4294967295 VALUE 0 3 RESERVED_15_4 4 15 ixDPCSSYS_CR0_SUP_DIG_ANA_MPLLA_OVRD_OUT_0 2 0x8c 16 0 4294967295 MPLLA_WORD_CLK_EN 0 0 MPLLA_HDMI_CLK_EN 1 1 MPLLA_DIV_CLK_EN 2 2 MPLLA_OUTPUT_EN 3 3 MPLLA_CLK_EN_OVRD_EN 4 4 MPLLA_OUTPUT_L_EN 5 5 MPLLA_OUTPUT_R_EN 6 6 MPLLA_ANA_EN 7 7 MPLLA_RST 8 8 MPLLA_CAL 9 9 MPLLA_DIV5_CLK_EN 10 10 MPLLA_DIV10_CLK_EN 11 11 MPLLA_FBCLK_EN 12 12 MPLLA_GEARSHIFT_EN 13 13 MPLLA_STANDBY 14 14 OVRD_SEL 15 15 ixDPCSSYS_CR0_SUP_DIG_ANA_MPLLA_OVRD_OUT_1 2 0x8d 2 0 4294967295 MPLLA_ANA_INT 0 9 RESERVED_15_10 10 15 ixDPCSSYS_CR0_SUP_DIG_ANA_MPLLA_OVRD_OUT_2 2 0x8e 3 0 4294967295 MPLLA_CP_PROP 0 6 MPLLA_CP_INT 7 13 RESERVED_15_14 14 15 ixDPCSSYS_CR0_SUP_DIG_ANA_MPLLB_OVRD_OUT_0 2 0x8f 16 0 4294967295 MPLLB_WORD_CLK_EN 0 0 MPLLB_HDMI_CLK_EN 1 1 MPLLB_DIV_CLK_EN 2 2 MPLLB_OUTPUT_EN 3 3 MPLLB_CLK_EN_OVRD_EN 4 4 MPLLB_OUTPUT_L_EN 5 5 MPLLB_OUTPUT_R_EN 6 6 MPLLB_ANA_EN 7 7 MPLLB_RST 8 8 MPLLB_CAL 9 9 MPLLB_DIV5_CLK_EN 10 10 MPLLB_DIV10_CLK_EN 11 11 MPLLB_FBCLK_EN 12 12 MPLLB_GEARSHIFT_EN 13 13 MPLLB_STANDBY 14 14 OVRD_SEL 15 15 ixDPCSSYS_CR0_SUP_DIG_ANA_MPLLB_OVRD_OUT_1 2 0x90 2 0 4294967295 MPLLB_ANA_INT 0 9 RESERVED_15_10 10 15 ixDPCSSYS_CR0_SUP_DIG_ANA_MPLLB_OVRD_OUT_2 2 0x91 3 0 4294967295 MPLLB_CP_PROP 0 6 MPLLB_CP_INT 7 13 RESERVED_15_14 14 15 ixDPCSSYS_CR0_SUP_DIG_ANA_RTUNE_OVRD_OUT 2 0x92 6 0 4294967295 RTUNE_COMP_RST 0 0 RTUNE_MODE 1 2 RTUNE_EN 3 3 RTUNE_VALUE 4 13 RTUNE_OVRD_EN 14 14 RESERVED_15_15 15 15 ixDPCSSYS_CR0_SUP_DIG_ANA_STAT 2 0x93 3 0 4294967295 RT_ANA_COMP_RESULT 0 0 REF_ANA_CLKDET_RESULT 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR0_SUP_DIG_ANA_BG_OVRD_OUT 2 0x94 11 0 4294967295 BG_EN 0 0 BG_FAST_START 1 1 BG_KICK_START 2 2 BG_OVRD_EN 3 3 ANA_ASYNC_RST 4 4 ANA_ASYNC_RST_OVRD_EN 5 5 REF_VREG_FAST_START 6 6 REF_VREG_FAST_START_OVRD_EN 7 7 REF_VREG_REF_SEL 8 9 REF_VREG_REF_SEL_OVRD_EN 10 10 RESERVED_15_11 11 15 ixDPCSSYS_CR0_SUP_DIG_ANA_MPLLA_PMIX_OVRD_OUT 2 0x95 5 0 4294967295 MPLLA_PMIX_SEL 0 5 MPLLA_PMIX_EN 6 6 MPLLA_PMIX_SEL_OVRD_EN 7 7 MPLLA_PMIX_EN_OVRD_EN 8 8 RESERVED_15_9 9 15 ixDPCSSYS_CR0_SUP_DIG_ANA_MPLLB_PMIX_OVRD_OUT 2 0x96 5 0 4294967295 MPLLB_PMIX_SEL 0 5 MPLLB_PMIX_EN 6 6 MPLLB_PMIX_SEL_OVRD_EN 7 7 MPLLB_PMIX_EN_OVRD_EN 8 8 RESERVED_15_9 9 15 ixDPCSSYS_CR0_LANE0_DIG_ASIC_LANE_OVRD_IN 2 0x1000 5 0 4294967295 LANE_TX2RX_SER_LB 0 0 LANE_RX2TX_PAR_LB 1 1 EN 2 2 RX_ACJTAG_EN 3 3 RESERVED_15_4 4 15 ixDPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_0 2 0x1001 12 0 4294967295 REQ 0 0 REQ_OVRD_EN 1 1 PSTATE 2 3 PSTATE_OVRD_EN 4 4 RATE 5 7 RATE_OVRD_EN 8 8 WIDTH 9 10 WIDTH_OVRD_EN 11 11 MPLLB_SEL 12 12 MPLLB_SEL_OVRD_EN 13 13 DATA_EN 14 14 DATA_EN_OVRD_EN 15 15 ixDPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_1 2 0x1002 11 0 4294967295 NYQUIST_DATA 0 0 DISABLE 1 1 BEACON_EN 2 2 EN 3 3 TX_MAIN_CURSOR 4 9 MAIN_OVRD_EN 10 10 ASYNC_DRV_EN 11 11 ASYNC_DRV_OVRD_EN 12 12 TX_VREGDRV_BYP_OVRD 13 13 TX_VREGDRV_BYP_OVRD_EN 14 14 RESERVED_15_15 15 15 ixDPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_2 2 0x1003 6 0 4294967295 TX_PRE_CURSOR 0 5 PRE_OVRD_EN 6 6 TX_POST_CURSOR 7 12 POST_OVRD_EN 13 13 HDMIMODE_EN 14 14 HDMIMODE_ENABLE_OVRD_EN 15 15 ixDPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_3 2 0x1004 15 0 4294967295 CLK_RDY 0 0 CLK_RDY_OVRD_EN 1 1 DETECT_RX_REQ 2 2 DETECT_RX_REQ_OVRD_EN 3 3 INVERT 4 4 INVERT_OVRD_EN 5 5 LPD 6 6 LPD_OVRD_EN 7 7 TX_DC_COUP_EN 8 8 TX_DC_COUP_EN_OVRD_EN 9 9 PMA_EXTENDED_FIFO_EN 10 10 PMA_EXTENDED_FIFO_EN_OVRD_EN 11 11 TX_MPHY_MODE_EN 12 12 TX_MPHY_MODE_EN_OVRD_EN 13 13 RESERVED_15_14 14 15 ixDPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_4 2 0x1005 3 0 4294967295 RESET 0 0 RESET_OVRD_EN 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_OUT 2 0x1006 5 0 4294967295 TX_ACK 0 0 EN_TX_ACK 1 1 DETRX_RESULT 2 2 EN_DETRX_RESULT 3 3 RESERVED_15_4 4 15 ixDPCSSYS_CR0_LANE0_DIG_ASIC_RX_OVRD_OUT_0 2 0x100f 9 0 4294967295 ACK 0 0 ACK_OVRD_EN 1 1 ADAPT_STS 2 3 ADAPT_STS_OVRD_EN 4 4 RX_ASYNC_DATA 5 5 RX_ASYNC_DATA_OVRD_EN 6 6 RX_SQ_WEAKKEEP_OUT 7 7 RX_SQ_WEAKKEEP_OUT_OVRD_EN 8 8 RESERVED_15_9 9 15 ixDPCSSYS_CR0_LANE0_DIG_ASIC_LANE_ASIC_IN 2 0x1010 3 0 4294967295 LANE_TX2RX_SER_LB 0 0 LANE_RX2TX_PAR_LB 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR0_LANE0_DIG_ASIC_TX_ASIC_IN_0 2 0x1011 12 0 4294967295 CLK_RDY 0 0 RESET 1 1 INVERT 2 2 DATA_EN 3 3 REQ 4 4 LPD 5 5 PSTATE 6 7 RATE 8 10 WIDTH 11 12 MPLLB_SEL 13 13 DETECT_RX_REQ 14 14 DISABLE 15 15 ixDPCSSYS_CR0_LANE0_DIG_ASIC_TX_ASIC_IN_1 2 0x1012 7 0 4294967295 BEACON_EN 0 0 TX_MAIN_CURSOR 1 6 TX_ASYNC_EN 7 7 TX_ASYNC_DATA 8 8 TX_ASYNC_DRV_EN 9 9 TX_VREGDRV_BYP 10 10 RESERVED_15_11 11 15 ixDPCSSYS_CR0_LANE0_DIG_ASIC_TX_ASIC_IN_2 2 0x1013 3 0 4294967295 TX_PRE_CURSOR 0 5 TX_POST_CURSOR 6 11 RESERVED_15_12 12 15 ixDPCSSYS_CR0_LANE0_DIG_ASIC_TX_ASIC_OUT 2 0x1014 3 0 4294967295 TX_ACK 0 0 DETRX_RESULT 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR0_LANE0_DIG_ASIC_RX_ASIC_OUT_0 2 0x101b 4 0 4294967295 ACK 0 0 VALID 1 1 ADAPT_STS 2 3 RESERVED_15_4 4 15 ixDPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_5 2 0x101d 15 0 4294967295 RPTR_EN_MASTER_LANE 0 0 RPTR_EN_MASTER_LANE_OVRD_EN 1 1 DIG_CLK_EN_OTHER_LANE 2 2 DIG_CLK_EN_OTHER_LANE_OVRD_EN 3 3 DIG_CLK_STATE_MASTER_LANE 4 4 DIG_CLK_STATE_MASTER_LANE_OVRD_EN 5 5 SHIFT_MASTER_LANE 6 6 SHIFT_MASTER_LANE_ORVD_EN 7 7 SHIFT_ACK_OTHER_LANE 8 8 SHIFT_ACK_OTHER_LANE_OVRD_EN 9 9 LANE_MASTER 10 10 LANE_MASTER_OVRD_IN_EN 11 11 TX_DWORD_CLK_SYNC_OVRD 12 12 TX_DWORD_CLK_SYNC_OVRD_EN 13 13 RESERVED_15_14 14 15 ixDPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_OUT_1 2 0x101e 11 0 4294967295 RPTR_EN_OUT 0 0 RPTR_EN_OUT_OVRD_EN 1 1 DIG_CLK_EN_OUT 2 2 DIG_CLK_EN_OUT_OVRD_EN 3 3 DIG_CLK_STATE_OUT 4 4 DIG_CLK_STATE_OUT_OVRD_EN 5 5 SHIFT_OUT 6 6 SHIFT_OUT_OVRD_EN 7 7 SHIFT_ACK_OUT 8 8 SHIFT_ACK_OUT_OVRD_EN 9 9 RESERVED_15_10 10 15 ixDPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0 2 0x1020 11 0 4294967295 TX_P0_ANA_REFGEN_EN 0 0 TX_P0_ANA_VCM_HOLD 1 1 TX_P0_ANA_CLK_EN 2 2 TX_P0_ANA_WORD_CLK_EN 3 3 TX_P0_ANA_RESET 4 4 TX_P0_ANA_SERIAL_EN 5 5 TX_P0_DIG_CLK_EN 6 6 TX_P0_DATA_EN 7 7 TX_P0_ALLOW_RXDET 8 8 TX_P0_ANA_DCC_COMP_CAL_EN 9 9 RESERVED_15_10 10 15 ixDPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S 2 0x1021 11 0 4294967295 TX_P0S_ANA_REFGEN_EN 0 0 TX_P0S_ANA_VCM_HOLD 1 1 TX_P0S_ANA_CLK_EN 2 2 TX_P0S_ANA_WORD_CLK_EN 3 3 TX_P0S_ANA_RESET 4 4 TX_P0S_ANA_SERIAL_EN 5 5 TX_P0S_DIG_CLK_EN 6 6 TX_P0S_DATA_EN 7 7 TX_P0S_ALLOW_RXDET 8 8 TX_P0S_ANA_DCC_COMP_CAL_EN 9 9 RESERVED_15_10 10 15 ixDPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1 2 0x1022 11 0 4294967295 TX_P1_ANA_REFGEN_EN 0 0 TX_P1_ANA_VCM_HOLD 1 1 TX_P1_ANA_CLK_EN 2 2 TX_P1_ANA_WORD_CLK_EN 3 3 TX_P1_ANA_RESET 4 4 TX_P1_ANA_SERIAL_EN 5 5 TX_P1_DIG_CLK_EN 6 6 TX_P1_DATA_EN 7 7 TX_P1_ALLOW_RXDET 8 8 TX_P1_ANA_DCC_COMP_CAL_EN 9 9 RESERVED_15_10 10 15 ixDPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2 2 0x1023 12 0 4294967295 TX_P2_ANA_REFGEN_EN 0 0 TX_P2_ANA_VCM_HOLD 1 1 TX_P2_ANA_CLK_EN 2 2 TX_P2_ANA_WORD_CLK_EN 3 3 TX_P2_ANA_RESET 4 4 TX_P2_ANA_SERIAL_EN 5 5 TX_P2_DIG_CLK_EN 6 6 TX_P2_DATA_EN 7 7 TX_P2_ALLOW_RXDET 8 8 TX_P2_ALLOW_VBOOST 9 9 TX_P2_ANA_DCC_COMP_CAL_EN 10 10 RESERVED_15_11 11 15 ixDPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_0 2 0x1024 2 0 4294967295 TX_REFGEN_EN_TIME 0 7 TX_CLK_EN 8 15 ixDPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_1 2 0x1025 2 0 4294967295 TX_VCM_HOLD_TIME_14_0 0 14 SKIP_TX_VCM_HOLD_WAIT 15 15 ixDPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_2 2 0x1026 2 0 4294967295 TX_VBOOST_DIS_TIME_12_0 0 12 DTB_SEL 13 15 ixDPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_3 2 0x1027 3 0 4294967295 TX_VCM_HOLD_TIME_17_15 0 2 TX_VBOOST_DIS_TIME_13 3 3 RESERVED_15_4 4 15 ixDPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_4 2 0x1028 2 0 4294967295 TX_VCM_HOLD_GS_TIME 0 14 SKIP_TX_VCM_HOLD_GS_PULSE 15 15 ixDPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_5 2 0x1029 5 0 4294967295 TX_RXDET_TIME 0 9 FAST_TX_RXDET 10 10 TX_RESET_TIME 11 12 TX_SERIAL_EN_TIME 13 14 RESERVED_15_15 15 15 ixDPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_DCC_CR_BANK_ADDR 2 0x102a 1 0 4294967295 ADDR 0 15 ixDPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_DCC_CR_BANK_DATA 2 0x102b 1 0 4294967295 DATA 0 15 ixDPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_DCC_DAC_CTRL 2 0x102c 2 0 4294967295 CTRL 0 7 RESERVED_15_8 8 15 ixDPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_DCC_DAC_RANGE 2 0x102d 2 0 4294967295 CTRL 0 1 RESERVED_15_2 2 15 ixDPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_DCC_DAC_SEL 2 0x102e 6 0 4294967295 SEL 0 2 REQ 3 3 CTRL_UPD 4 4 RANGE_UPD 5 5 BIN_HOT 6 6 RESERVED_15_7 7 15 ixDPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_DCC_DAC_ACK 2 0x102f 2 0 4294967295 ACK 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_DCC_DAC_ADDR 2 0x1030 1 0 4294967295 ADDR 0 15 ixDPCSSYS_CR0_LANE0_DIG_TX_CLK_ALIGN_TX_CTL_0 2 0x1031 4 0 4294967295 TX_NUM_2UI_SHIFTS_16B_MODE 0 3 TX_NUM_2UI_SHIFTS_20B_MODE 4 7 TX_FIFO_BYPASS 8 8 RESERVED_15_9 9 15 ixDPCSSYS_CR0_LANE0_DIG_TX_LBERT_CTL 2 0x1032 4 0 4294967295 MODE 0 3 TRIGGER_ERR 4 4 PAT0 5 14 RESERVED_15_15 15 15 ixDPCSSYS_CR0_LANE0_DIG_RX_STAT_LD_VAL_1 2 0x1080 2 0 4294967295 SC1_LD_VAL 0 14 SC1_START 15 15 ixDPCSSYS_CR0_LANE0_DIG_RX_STAT_DATA_MSK 2 0x1081 1 0 4294967295 DATA_MSK_15_0 0 15 ixDPCSSYS_CR0_LANE0_DIG_RX_STAT_MATCH_CTL0 2 0x1082 4 0 4294967295 PTTRN_MSK_CR1A_4_0 0 4 PTTRN_CR1A_4_0 5 9 DATA_MSK_19_16 10 13 SCOPE_DLY 14 15 ixDPCSSYS_CR0_LANE0_DIG_RX_STAT_MATCH_CTL1 2 0x1083 5 0 4294967295 PTTRN_CR1B_EN 0 0 PTTRN_MSK_CR1B_4_0 1 5 PTTRN_CR1B_4_0 6 10 PTTRN_CR1A_ADPT_EN 11 11 RESERVED_15_12 12 15 ixDPCSSYS_CR0_LANE0_DIG_RX_STAT_STAT_CTL0 2 0x1084 10 0 4294967295 RESERVED_0 0 0 CORR_SHFT_SEL_VGA 1 1 CORR_SHFT_SEL 2 2 CORR_SRC_SEL 3 4 CORR_MODE_EN 5 5 STAT_SHFT_SEL 6 9 STAT_SRC_SEL 10 12 STAT_RXCLK_SEL 13 13 SC_TIMER_MODE 14 14 SKIP_EN 15 15 ixDPCSSYS_CR0_LANE0_DIG_RX_STAT_STAT_CTL1 2 0x1085 13 0 4294967295 STAT_CNT_0_EN 0 0 STAT_CNT_1_EN 1 1 STAT_CNT_2_EN 2 2 STAT_CNT_3_EN 3 3 STAT_CNT_4_EN 4 4 STAT_CNT_5_EN 5 5 STAT_CNT_6_EN 6 6 RESERVED_8_7 7 8 SC_PAUSE 9 9 STAT_CLK_EN 10 10 DATA_DLY_SEL 11 12 VLD_LOSS_CLR 13 13 VLD_CTL 14 15 ixDPCSSYS_CR0_LANE0_DIG_RX_STAT_SMPL_CNT1 2 0x1086 2 0 4294967295 SMPL_CNT1 0 14 SMPL_CNT1_DONE 15 15 ixDPCSSYS_CR0_LANE0_DIG_RX_STAT_STAT_CNT_0 2 0x1087 2 0 4294967295 STAT_CNT_0 0 14 SMPL_CNT1_DONE 15 15 ixDPCSSYS_CR0_LANE0_DIG_RX_STAT_STAT_CNT_1 2 0x1088 2 0 4294967295 STAT_CNT_1 0 14 SMPL_CNT1_DONE 15 15 ixDPCSSYS_CR0_LANE0_DIG_RX_STAT_STAT_CNT_2 2 0x1089 2 0 4294967295 STAT_CNT_2 0 14 SMPL_CNT1_DONE 15 15 ixDPCSSYS_CR0_LANE0_DIG_RX_STAT_STAT_CNT_3 2 0x108a 2 0 4294967295 STAT_CNT_3 0 14 SMPL_CNT1_DONE 15 15 ixDPCSSYS_CR0_LANE0_DIG_RX_STAT_STAT_CNT_4 2 0x108b 2 0 4294967295 STAT_CNT_4 0 14 SMPL_CNT1_DONE 15 15 ixDPCSSYS_CR0_LANE0_DIG_RX_STAT_STAT_CNT_5 2 0x108c 2 0 4294967295 STAT_CNT_5 0 14 SMPL_CNT1_DONE 15 15 ixDPCSSYS_CR0_LANE0_DIG_RX_STAT_STAT_CNT_6 2 0x108d 2 0 4294967295 STAT_CNT_6 0 14 SMPL_CNT1_DONE 15 15 ixDPCSSYS_CR0_LANE0_DIG_RX_STAT_CAL_COMP_CLK_CTL 2 0x108e 3 0 4294967295 PRECHRGE_CNT 0 2 REF_DIV_CNT 3 5 RESERVED_15_6 6 15 ixDPCSSYS_CR0_LANE0_DIG_RX_STAT_MATCH_CTL2 2 0x108f 2 0 4294967295 PTTRN_CR1A_19_5 0 14 RESERVED_15_15 15 15 ixDPCSSYS_CR0_LANE0_DIG_RX_STAT_MATCH_CTL3 2 0x1090 2 0 4294967295 PTTRN_MSK_CR1A_19_5 0 14 RESERVED_15_15 15 15 ixDPCSSYS_CR0_LANE0_DIG_RX_STAT_MATCH_CTL4 2 0x1091 2 0 4294967295 PTTRN_CR1B_19_5 0 14 RESERVED_15_15 15 15 ixDPCSSYS_CR0_LANE0_DIG_RX_STAT_MATCH_CTL5 2 0x1092 2 0 4294967295 PTTRN_MSK_CR1B_19_5 0 14 RESERVED_15_15 15 15 ixDPCSSYS_CR0_LANE0_DIG_RX_STAT_STAT_CTL2 2 0x1093 4 0 4294967295 DATA_DLY_SEL_2 0 0 SCOPE_DLY_2 1 1 DISABLE_SAMPLE_COUNT 2 2 RESERVED_15_3 3 15 ixDPCSSYS_CR0_LANE0_DIG_RX_STAT_STAT_STOP 2 0x1094 2 0 4294967295 SC1_STOP 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR0_LANE0_DIG_ANA_TX_OVRD_OUT 2 0x10a0 15 0 4294967295 TX_ANA_CLK_SHIFT 0 0 TX_ANA_DATA_EN 1 1 TX_ANA_REFGEN_EN 2 2 TX_ANA_VCM_HOLD 3 3 TX_ANA_CLK_EN 4 4 TX_ANA_WORD_CLK_EN 5 5 TX_ANA_MPLLA_CLK_EN 6 6 TX_ANA_MPLLB_CLK_EN 7 7 TX_ANA_RESET 8 8 TX_ANA_SERIAL_EN 9 9 TX_ANA_DATA_RATE 10 11 RESERVED 12 12 TX_DIV4_EN 13 13 TX_RXDET_EN 14 14 TX_OVRD_EN 15 15 ixDPCSSYS_CR0_LANE0_DIG_ANA_TX_TERM_CODE_OVRD_OUT 2 0x10a1 5 0 4294967295 TX_TERM_CODE 0 9 TX_TERM_OVRD_EN 10 10 TX_DRV_SRC 11 12 TX_DRV_SRC_OVRD_EN 13 13 RESERVED_15_14 14 15 ixDPCSSYS_CR0_LANE0_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT 2 0x10a2 3 0 4294967295 TX_TERM_DN_CLK 0 0 TX_TERM_CLK_SELF_CLEAR_DISABLE 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR0_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_0 2 0x10a3 3 0 4294967295 TX_ANA_LOAD_CLK 0 0 TX_ANA_CTRL_LEG_PULL_EN_13_0 1 14 TX_EQ_OVRD_EN 15 15 ixDPCSSYS_CR0_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_1 2 0x10a4 2 0 4294967295 TX_ANA_CTRL_LEG_PULL_EN_19_14 0 5 RESERVED_15_6 6 15 ixDPCSSYS_CR0_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_2 2 0x10a5 4 0 4294967295 RESERVED 0 2 TX_ANA_CTRL_EQ_MUX_SEL 3 6 TX_ANA_CTRL_PRE 7 12 RESERVED_15_13 13 15 ixDPCSSYS_CR0_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_3 2 0x10a6 2 0 4294967295 TX_ANA_CTRL_POST 0 8 RESERVED_15_9 9 15 ixDPCSSYS_CR0_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_4 2 0x10a7 1 0 4294967295 TX_ANA_CTRL_LEG_PULL_DIR_19_4 0 15 ixDPCSSYS_CR0_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_5 2 0x10a8 2 0 4294967295 TX_ANA_CTRL_LEG_PULL_DIR_3_0 0 3 RESERVED_15_4 4 15 ixDPCSSYS_CR0_LANE0_DIG_ANA_STATUS_0 2 0x10bb 9 0 4294967295 TX_ANA_CLK_SHIFT_ACK 0 0 TX_ANA_RXDETP_RESULT 1 1 TX_ANA_RXDETM_RESULT 2 2 TX_ANA_LOOPBACK_EN 3 3 TX_ANA_CLK_LB_EN 4 4 RX_ANA_CAL_RESULT 5 5 RX_ANA_SCOPE_DATA 6 6 TX_ANA_DCC_CAL_RESULT 7 7 TX_ANA_CTRL_EQ_MUX 8 15 ixDPCSSYS_CR0_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT 2 0x10c2 8 0 4294967295 TX_ANA_DCC_CAL_RANGE 0 1 TX_ANA_DCC_CAL_RANGE_OVRD_EN 2 2 TX_ANA_DCC_CAL_COMP_EN 3 3 TX_ANA_DCC_CAL_COMP_EN_OVRD_EN 4 4 TX_ANA_DCC_CAL_CTRL 5 12 TX_ANA_DCC_CAL_CTRL_OVRD_EN 13 13 TX_ANA_DCC_CAL_CTRL_EN 14 14 TX_ANA_DCC_CAL_CTRL_EN_OVRD_EN 15 15 ixDPCSSYS_CR0_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2 2 0x10c3 5 0 4294967295 TX_ANA_DCC_CAL_CTRL_SEL 0 2 TX_ANA_DCC_CAL_CTRL_SEL_OVRD_EN 3 3 TX_ANA_DCC_CLK_COMP 4 4 TX_ANA_DCC_CLK_COMP_OVRD_EN 5 5 RESERVED_15_6 6 15 ixDPCSSYS_CR0_LANE0_DIG_ANA_TX_OVRD_OUT_2 2 0x10c4 6 0 4294967295 TX_ANA_FAST_START 0 0 TX_ANA_FAST_START_OVRD_EN 1 1 TX_CLK_LB_EN 2 2 TX_CLK_LB_EN_OVRD_EN 3 3 TX_ACJTAG_EN 4 4 RESERVED_15_5 5 15 ixDPCSSYS_CR0_LANE0_ANA_TX_OVRD_MEAS 2 0x10e0 9 0 4294967295 OVRD_CLK_SHIFT 0 0 CLK_SHIFT_REG 0 0 MEAS_ATB_CAL_MUX 0 0 MEAS_ATB_CAL_COMP 0 0 OVRD_VCM_HOLD 0 0 VCM_HOLD_REG 0 0 PULL_UP_REG 0 0 PULL_DN_REG 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR0_LANE0_ANA_TX_PWR_OVRD 2 0x10e1 9 0 4294967295 OVRD_TX_LOOPBACK 0 0 LOOPBACK_EN_REG 0 0 REFGEN_EN_REG 0 0 CLK_DIV_EN_REG 0 0 DATA_EN_REG_INT 0 0 CLK_EN_REG 0 0 SERIAL_EN_REG 0 0 OVRD_EN 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR0_LANE0_ANA_TX_ALT_BUS 2 0x10e2 6 0 4294967295 DRV_SOURCE_REG 0 0 OVRD_ALT_BUS 0 0 ATB_S_ENABLE 0 0 TX_ALT_RINGO 0 0 JTAG_DATA_REG 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR0_LANE0_ANA_TX_ATB1 2 0x10e3 9 0 4294967295 MEAS_ATB_GD 0 0 MEAS_ATB_VDDH 0 0 OVERRIDE_RXDETREF 0 0 MEAS_ATB_VPTX 0 0 OVERRIDE_REGREF 0 0 MEAS_ATB_VREG_DRV 0 0 MEAS_ATB_VREG 0 0 MEAS_ATB_VPH_HALF 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR0_LANE0_ANA_TX_ATB2 2 0x10e4 9 0 4294967295 MEAS_ATB_VCM 0 0 MEAS_ATB_CAL_VDAC_CM 0 0 MEAS_ATB_CAL_VDAC_DIFF 0 0 MEAS_ATB_TXM 0 0 MEAS_ATB_TXP 0 0 MEAS_ATB_RXDETREF 0 0 LFPS_HIGH_PRIORITY 0 0 OSC_DIV4_EN 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR0_LANE0_ANA_TX_DCC_DAC 2 0x10e5 2 0 4294967295 DCC_DAC_REG 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR0_LANE0_ANA_TX_DCC_CTRL1 2 0x10e6 7 0 4294967295 NC0 0 0 OVRD_DCC_DAC_CTRL_SEL 0 0 DCC_DAC_CTRL_SEL_REG 0 0 OVRD_DCC_DAC_CTRL_EN 0 0 DCC_DAC_CTRL_EN_REG 0 0 OVRD_DCC_DAC_REG 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR0_LANE0_ANA_TX_TERM_CODE 2 0x10e7 2 0 4294967295 TERM_CODE_REG_70 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR0_LANE0_ANA_TX_TERM_CODE_CTRL 2 0x10e8 8 0 4294967295 VREG_BOOST_1 0 0 OVRD_UPDATE_TERM 0 0 UPDATE_TERM_REG 0 0 OVRD_RESET_TERM 0 0 RESET_TERM_REG 0 0 OVRD_TERM_CODE 0 0 TERM_CODE_REG_98 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR0_LANE0_ANA_TX_OVRD_CLK 2 0x10e9 9 0 4294967295 VREG_BOOST_0 0 0 CLK_LB_EN_REG 0 0 OVRD_LB_EN 0 0 MPLLB_CLK_EN_REG 0 0 MPLLA_CLK_EN_REG 0 0 OVRD_MPLLAB_EN 0 0 WORD_CLK_EN_REG 0 0 OVRD_WORD_CLK_EN 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR0_LANE0_ANA_TX_MISC1 2 0x10ea 8 0 4294967295 MEAS_ATB_CAL_CLK_ALIGN 0 0 OVRD_DCC_DAC_CTRL_RANGE 0 0 DCC_DAC_CTRL_RANGE_REG 0 0 OVRD_VREF_SEL 0 0 VREF_SEL_REG 0 0 FORCE_ATB_TXM 0 0 FORCE_ATB_TXP 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR0_LANE0_ANA_TX_MISC2 2 0x10eb 8 0 4294967295 TX_PEAKING_LVL 0 0 VREG_CP_GAIN_CTRL 0 0 TX_SLEW_EN 0 0 EN_INV_POST 0 0 EN_INV_PRE 0 0 TX_VREG_EN_BYP 0 0 TX_VDRIVER_PULLDN_EN 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR0_LANE0_ANA_TX_MISC3 2 0x10ec 4 0 4294967295 TX_VREG_OVRD_RING_CTRL 0 0 TX_DCC_LOWV 0 0 NC7_2 2 7 RESERVED_15_8 8 15 ixDPCSSYS_CR0_LANE0_ANA_TX_RESERVED2 2 0x10ed 2 0 4294967295 NC7_0 0 7 RESERVED_15_8 8 15 ixDPCSSYS_CR0_LANE0_ANA_TX_RESERVED3 2 0x10ee 2 0 4294967295 NC7_0 0 7 RESERVED_15_8 8 15 ixDPCSSYS_CR0_LANE0_ANA_TX_RESERVED4 2 0x10ef 2 0 4294967295 NC7_0 0 7 RESERVED_15_8 8 15 ixDPCSSYS_CR0_LANE1_DIG_ASIC_LANE_OVRD_IN 2 0x1100 5 0 4294967295 LANE_TX2RX_SER_LB 0 0 LANE_RX2TX_PAR_LB 1 1 EN 2 2 RX_ACJTAG_EN 3 3 RESERVED_15_4 4 15 ixDPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_0 2 0x1101 12 0 4294967295 REQ 0 0 REQ_OVRD_EN 1 1 PSTATE 2 3 PSTATE_OVRD_EN 4 4 RATE 5 7 RATE_OVRD_EN 8 8 WIDTH 9 10 WIDTH_OVRD_EN 11 11 MPLLB_SEL 12 12 MPLLB_SEL_OVRD_EN 13 13 DATA_EN 14 14 DATA_EN_OVRD_EN 15 15 ixDPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_1 2 0x1102 11 0 4294967295 NYQUIST_DATA 0 0 DISABLE 1 1 BEACON_EN 2 2 EN 3 3 TX_MAIN_CURSOR 4 9 MAIN_OVRD_EN 10 10 ASYNC_DRV_EN 11 11 ASYNC_DRV_OVRD_EN 12 12 TX_VREGDRV_BYP_OVRD 13 13 TX_VREGDRV_BYP_OVRD_EN 14 14 RESERVED_15_15 15 15 ixDPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_2 2 0x1103 6 0 4294967295 TX_PRE_CURSOR 0 5 PRE_OVRD_EN 6 6 TX_POST_CURSOR 7 12 POST_OVRD_EN 13 13 HDMIMODE_EN 14 14 HDMIMODE_ENABLE_OVRD_EN 15 15 ixDPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_3 2 0x1104 15 0 4294967295 CLK_RDY 0 0 CLK_RDY_OVRD_EN 1 1 DETECT_RX_REQ 2 2 DETECT_RX_REQ_OVRD_EN 3 3 INVERT 4 4 INVERT_OVRD_EN 5 5 LPD 6 6 LPD_OVRD_EN 7 7 TX_DC_COUP_EN 8 8 TX_DC_COUP_EN_OVRD_EN 9 9 PMA_EXTENDED_FIFO_EN 10 10 PMA_EXTENDED_FIFO_EN_OVRD_EN 11 11 TX_MPHY_MODE_EN 12 12 TX_MPHY_MODE_EN_OVRD_EN 13 13 RESERVED_15_14 14 15 ixDPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_4 2 0x1105 3 0 4294967295 RESET 0 0 RESET_OVRD_EN 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_OUT 2 0x1106 5 0 4294967295 TX_ACK 0 0 EN_TX_ACK 1 1 DETRX_RESULT 2 2 EN_DETRX_RESULT 3 3 RESERVED_15_4 4 15 ixDPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_0 2 0x1107 11 0 4294967295 REQ 0 0 REQ_OVRD_EN 1 1 DATA_EN 2 2 DATA_EN_OVRD_EN 3 3 PSTATE 4 5 PSTATE_OVRD_EN 6 6 RATE 7 8 RATE_OVRD_EN 9 9 WIDTH 10 11 WIDTH_OVRD_EN 12 12 RESERVED_15_13 13 15 ixDPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_1 2 0x1108 5 0 4294967295 RX_REF_LD_VAL_5_0 0 5 RX_CDR_VCO_LOWFREQ 6 6 EN 7 7 RX_REF_LD_VAL_6 8 8 RESERVED_15_9 9 15 ixDPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_2 2 0x1109 3 0 4294967295 RX_VCO_LD_VAL 0 12 EN 13 13 RESERVED_15_14 14 15 ixDPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_3 2 0x110a 11 0 4294967295 CDR_TRACK_EN 0 0 CDR_TRACK_EN_OVRD_EN 1 1 CDR_SSC_EN 2 2 CDR_SSC_EN_OVRD_EN 3 3 ALIGN_EN 4 4 ALIGN_EN_OVRD_EN 5 5 CLK_SHIFT 6 6 CLK_SHIFT_OVRD_EN 7 7 DISABLE 8 8 DISABLE_OVRD_EN 9 9 RESERVED_15_10 10 15 ixDPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_4 2 0x110b 11 0 4294967295 LPD 0 0 LPD_OVRD_EN 1 1 INVERT 2 2 INVERT_OVRD_EN 3 3 ADAPT_AFE_EN 4 4 ADAPT_DFE_EN 5 5 ADPT_OVRD_EN 6 6 TERM_EN 7 7 TERM_ACDC 8 8 TERM_OVRD_EN 9 9 RESERVED_15_10 10 15 ixDPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_5 2 0x110c 3 0 4294967295 RESET 0 0 RESET_OVRD_EN 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0 2 0x110d 4 0 4294967295 EQ_ATT_LVL 0 2 EQ_AFE_GAIN 3 6 RESERVED 7 10 EQ_CTLE_BOOST 11 15 ixDPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1 2 0x110e 3 0 4294967295 EQ_DFE_TAP2 0 6 EQ_DFE_TAP1 7 14 EQ_OVRD_EN 15 15 ixDPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_OUT_0 2 0x110f 9 0 4294967295 ACK 0 0 ACK_OVRD_EN 1 1 ADAPT_STS 2 3 ADAPT_STS_OVRD_EN 4 4 RX_ASYNC_DATA 5 5 RX_ASYNC_DATA_OVRD_EN 6 6 RX_SQ_WEAKKEEP_OUT 7 7 RX_SQ_WEAKKEEP_OUT_OVRD_EN 8 8 RESERVED_15_9 9 15 ixDPCSSYS_CR0_LANE1_DIG_ASIC_LANE_ASIC_IN 2 0x1110 3 0 4294967295 LANE_TX2RX_SER_LB 0 0 LANE_RX2TX_PAR_LB 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR0_LANE1_DIG_ASIC_TX_ASIC_IN_0 2 0x1111 12 0 4294967295 CLK_RDY 0 0 RESET 1 1 INVERT 2 2 DATA_EN 3 3 REQ 4 4 LPD 5 5 PSTATE 6 7 RATE 8 10 WIDTH 11 12 MPLLB_SEL 13 13 DETECT_RX_REQ 14 14 DISABLE 15 15 ixDPCSSYS_CR0_LANE1_DIG_ASIC_TX_ASIC_IN_1 2 0x1112 7 0 4294967295 BEACON_EN 0 0 TX_MAIN_CURSOR 1 6 TX_ASYNC_EN 7 7 TX_ASYNC_DATA 8 8 TX_ASYNC_DRV_EN 9 9 TX_VREGDRV_BYP 10 10 RESERVED_15_11 11 15 ixDPCSSYS_CR0_LANE1_DIG_ASIC_TX_ASIC_IN_2 2 0x1113 3 0 4294967295 TX_PRE_CURSOR 0 5 TX_POST_CURSOR 6 11 RESERVED_15_12 12 15 ixDPCSSYS_CR0_LANE1_DIG_ASIC_TX_ASIC_OUT 2 0x1114 3 0 4294967295 TX_ACK 0 0 DETRX_RESULT 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR0_LANE1_DIG_ASIC_RX_ASIC_IN_0 2 0x1115 13 0 4294967295 RESET 0 0 INVERT 1 1 DATA_EN 2 2 REQ 3 3 LPD 4 4 PSTATE 5 6 RATE 7 8 WIDTH 9 10 RESERVED 11 11 ADAPT_AFE_EN 12 12 ADAPT_DFE_EN 13 13 CDR_TRACK_EN 14 14 RESERVED_15_15 15 15 ixDPCSSYS_CR0_LANE1_DIG_ASIC_RX_ASIC_IN_1 2 0x1116 7 0 4294967295 CDR_SSC_EN 0 0 ALIGN_EN 1 1 CLK_SHIFT 2 2 DISABLE 3 3 RX_TERM_EN 4 4 RX_TERM_ACDC 5 5 RESERVED_15_6 6 15 ixDPCSSYS_CR0_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0 2 0x1117 4 0 4294967295 EQ_ATT_LVL 0 2 EQ_AFE_GAIN 3 6 RESERVED 7 10 EQ_CTLE_BOOST 11 15 ixDPCSSYS_CR0_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_1 2 0x1118 3 0 4294967295 EQ_DFE_TAP2 0 6 EQ_DFE_TAP1 7 14 RESERVED_15_15 15 15 ixDPCSSYS_CR0_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0 2 0x1119 3 0 4294967295 RX_CDR_VCO_LOWFREQ 0 0 RX_REF_LD_VAL 1 7 RESERVED_15_8 8 15 ixDPCSSYS_CR0_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1 2 0x111a 2 0 4294967295 RX_VCO_LD_VAL 0 12 RESERVED_15_13 13 15 ixDPCSSYS_CR0_LANE1_DIG_ASIC_RX_ASIC_OUT_0 2 0x111b 4 0 4294967295 ACK 0 0 VALID 1 1 ADAPT_STS 2 3 RESERVED_15_4 4 15 ixDPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_6 2 0x111c 10 0 4294967295 RX_PWM_CLK_SEL 0 1 RX_PWM_CLK_SEL_OVRD_EN 2 2 RX_TERM_LCC_ON 3 3 RX_TERM_LS_ON 4 4 RX_TERM_LS_LCC_ON_OVRD_EN 5 5 RX_TERM_CTL 6 7 RX_TERM_CTL_OVRD_EN 8 8 RX_PWM_EN 9 9 RX_PWM_EN_OVRD_EN 10 10 RESERVED_15_11 11 15 ixDPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_5 2 0x111d 15 0 4294967295 RPTR_EN_MASTER_LANE 0 0 RPTR_EN_MASTER_LANE_OVRD_EN 1 1 DIG_CLK_EN_OTHER_LANE 2 2 DIG_CLK_EN_OTHER_LANE_OVRD_EN 3 3 DIG_CLK_STATE_MASTER_LANE 4 4 DIG_CLK_STATE_MASTER_LANE_OVRD_EN 5 5 SHIFT_MASTER_LANE 6 6 SHIFT_MASTER_LANE_ORVD_EN 7 7 SHIFT_ACK_OTHER_LANE 8 8 SHIFT_ACK_OTHER_LANE_OVRD_EN 9 9 LANE_MASTER 10 10 LANE_MASTER_OVRD_IN_EN 11 11 TX_DWORD_CLK_SYNC_OVRD 12 12 TX_DWORD_CLK_SYNC_OVRD_EN 13 13 RESERVED_15_14 14 15 ixDPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_OUT_1 2 0x111e 11 0 4294967295 RPTR_EN_OUT 0 0 RPTR_EN_OUT_OVRD_EN 1 1 DIG_CLK_EN_OUT 2 2 DIG_CLK_EN_OUT_OVRD_EN 3 3 DIG_CLK_STATE_OUT 4 4 DIG_CLK_STATE_OUT_OVRD_EN 5 5 SHIFT_OUT 6 6 SHIFT_OUT_OVRD_EN 7 7 SHIFT_ACK_OUT 8 8 SHIFT_ACK_OUT_OVRD_EN 9 9 RESERVED_15_10 10 15 ixDPCSSYS_CR0_LANE1_DIG_ASIC_OCLA 2 0x111f 3 0 4294967295 RX_DWORD_OCLA_CLK_EN 0 0 RX_DWORD_OCLA_DATA_EN 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0 2 0x1120 11 0 4294967295 TX_P0_ANA_REFGEN_EN 0 0 TX_P0_ANA_VCM_HOLD 1 1 TX_P0_ANA_CLK_EN 2 2 TX_P0_ANA_WORD_CLK_EN 3 3 TX_P0_ANA_RESET 4 4 TX_P0_ANA_SERIAL_EN 5 5 TX_P0_DIG_CLK_EN 6 6 TX_P0_DATA_EN 7 7 TX_P0_ALLOW_RXDET 8 8 TX_P0_ANA_DCC_COMP_CAL_EN 9 9 RESERVED_15_10 10 15 ixDPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S 2 0x1121 11 0 4294967295 TX_P0S_ANA_REFGEN_EN 0 0 TX_P0S_ANA_VCM_HOLD 1 1 TX_P0S_ANA_CLK_EN 2 2 TX_P0S_ANA_WORD_CLK_EN 3 3 TX_P0S_ANA_RESET 4 4 TX_P0S_ANA_SERIAL_EN 5 5 TX_P0S_DIG_CLK_EN 6 6 TX_P0S_DATA_EN 7 7 TX_P0S_ALLOW_RXDET 8 8 TX_P0S_ANA_DCC_COMP_CAL_EN 9 9 RESERVED_15_10 10 15 ixDPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1 2 0x1122 11 0 4294967295 TX_P1_ANA_REFGEN_EN 0 0 TX_P1_ANA_VCM_HOLD 1 1 TX_P1_ANA_CLK_EN 2 2 TX_P1_ANA_WORD_CLK_EN 3 3 TX_P1_ANA_RESET 4 4 TX_P1_ANA_SERIAL_EN 5 5 TX_P1_DIG_CLK_EN 6 6 TX_P1_DATA_EN 7 7 TX_P1_ALLOW_RXDET 8 8 TX_P1_ANA_DCC_COMP_CAL_EN 9 9 RESERVED_15_10 10 15 ixDPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2 2 0x1123 12 0 4294967295 TX_P2_ANA_REFGEN_EN 0 0 TX_P2_ANA_VCM_HOLD 1 1 TX_P2_ANA_CLK_EN 2 2 TX_P2_ANA_WORD_CLK_EN 3 3 TX_P2_ANA_RESET 4 4 TX_P2_ANA_SERIAL_EN 5 5 TX_P2_DIG_CLK_EN 6 6 TX_P2_DATA_EN 7 7 TX_P2_ALLOW_RXDET 8 8 TX_P2_ALLOW_VBOOST 9 9 TX_P2_ANA_DCC_COMP_CAL_EN 10 10 RESERVED_15_11 11 15 ixDPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_0 2 0x1124 2 0 4294967295 TX_REFGEN_EN_TIME 0 7 TX_CLK_EN 8 15 ixDPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_1 2 0x1125 2 0 4294967295 TX_VCM_HOLD_TIME_14_0 0 14 SKIP_TX_VCM_HOLD_WAIT 15 15 ixDPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_2 2 0x1126 2 0 4294967295 TX_VBOOST_DIS_TIME_12_0 0 12 DTB_SEL 13 15 ixDPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_3 2 0x1127 3 0 4294967295 TX_VCM_HOLD_TIME_17_15 0 2 TX_VBOOST_DIS_TIME_13 3 3 RESERVED_15_4 4 15 ixDPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_4 2 0x1128 2 0 4294967295 TX_VCM_HOLD_GS_TIME 0 14 SKIP_TX_VCM_HOLD_GS_PULSE 15 15 ixDPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_5 2 0x1129 5 0 4294967295 TX_RXDET_TIME 0 9 FAST_TX_RXDET 10 10 TX_RESET_TIME 11 12 TX_SERIAL_EN_TIME 13 14 RESERVED_15_15 15 15 ixDPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_DCC_CR_BANK_ADDR 2 0x112a 1 0 4294967295 ADDR 0 15 ixDPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_DCC_CR_BANK_DATA 2 0x112b 1 0 4294967295 DATA 0 15 ixDPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_DCC_DAC_CTRL 2 0x112c 2 0 4294967295 CTRL 0 7 RESERVED_15_8 8 15 ixDPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_DCC_DAC_RANGE 2 0x112d 2 0 4294967295 CTRL 0 1 RESERVED_15_2 2 15 ixDPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_DCC_DAC_SEL 2 0x112e 6 0 4294967295 SEL 0 2 REQ 3 3 CTRL_UPD 4 4 RANGE_UPD 5 5 BIN_HOT 6 6 RESERVED_15_7 7 15 ixDPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_DCC_DAC_ACK 2 0x112f 2 0 4294967295 ACK 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_DCC_DAC_ADDR 2 0x1130 1 0 4294967295 ADDR 0 15 ixDPCSSYS_CR0_LANE1_DIG_TX_CLK_ALIGN_TX_CTL_0 2 0x1131 4 0 4294967295 TX_NUM_2UI_SHIFTS_16B_MODE 0 3 TX_NUM_2UI_SHIFTS_20B_MODE 4 7 TX_FIFO_BYPASS 8 8 RESERVED_15_9 9 15 ixDPCSSYS_CR0_LANE1_DIG_TX_LBERT_CTL 2 0x1132 4 0 4294967295 MODE 0 3 TRIGGER_ERR 4 4 PAT0 5 14 RESERVED_15_15 15 15 ixDPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0 2 0x1140 12 0 4294967295 RX_P0_ANA_AFE_EN 0 0 RX_P0_ANA_CLK_VREG_EN 1 1 RESERVED_1 2 2 RX_P0_ANA_CLK_EN 3 3 RESERVED_0 4 4 RX_P0_ANA_DESER_EN 5 5 RX_P0_ANA_CDR_EN 6 6 RX_P0_VCO_FREQ_RST 7 7 RX_P0_VCO_CAL_RST 8 8 RX_P0_VCO_CONTCAL_EN 9 9 RX_P0_DIG_CLK_EN 10 10 RESERVED_15_11 11 15 ixDPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S 2 0x1141 12 0 4294967295 RX_P0S_ANA_AFE_EN 0 0 RX_P0S_ANA_CLK_VREG_EN 1 1 RESERVED_2 2 2 RX_P0S_ANA_CLK_EN 3 3 RESERVED_4 4 4 RX_P0S_ANA_DESER_EN 5 5 RX_P0S_ANA_CDR_EN 6 6 RX_P0S_VCO_FREQ_RST 7 7 RX_P0S_VCO_CAL_RST 8 8 RX_P0S_VCO_CONTCAL_EN 9 9 RX_P0S_DIG_CLK_EN 10 10 RESERVED_15_11 11 15 ixDPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1 2 0x1142 12 0 4294967295 RX_P1_ANA_AFE_EN 0 0 RX_P1_ANA_CLK_VREG_EN 1 1 RESERVED_2 2 2 RX_P1_ANA_CLK_EN 3 3 RESERVED_4 4 4 RX_P1_ANA_DESER_EN 5 5 RX_P1_ANA_CDR_EN 6 6 RX_P1_VCO_FREQ_RST 7 7 RX_P1_VCO_CAL_RST 8 8 RX_P1_VCO_CONTCAL_EN 9 9 RX_P1_DIG_CLK_EN 10 10 RESERVED_15_11 11 15 ixDPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2 2 0x1143 12 0 4294967295 RX_P2_ANA_AFE_EN 0 0 RX_P2_ANA_CLK_VREG_EN 1 1 RESERVED_2 2 2 RX_P2_ANA_CLK_EN 3 3 RESERVED_4 4 4 RX_P2_ANA_DESER_EN 5 5 RX_P2_ANA_CDR_EN 6 6 RX_P2_VCO_FREQ_RST 7 7 RX_P2_VCO_CAL_RST 8 8 RX_P2_VCO_CONTCAL_EN 9 9 RX_P2_DIG_CLK_EN 10 10 RESERVED_15_11 11 15 ixDPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1 2 0x1145 5 0 4294967295 RX_AFE_EN_TIME 0 5 FAST_RX_AFE_EN 6 6 RX_VREG_EN_TIME 7 12 FAST_RX_VREG_EN 13 13 RESERVED_15_14 14 15 ixDPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_2 2 0x1146 4 0 4294967295 RX_CLK_EN_TIME 0 5 FAST_RX_CLK_EN 6 6 RX_FAST_START_TIME 7 10 RESERVED_15_11 11 15 ixDPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_3 2 0x1147 5 0 4294967295 RX_RATE_TIME 0 1 RSVD_3_7_2 2 7 RX_CDR_EN_TIME 8 11 RX_DESER_EN_TIME 12 13 RX_DESER_DIS_TIME 14 15 ixDPCSSYS_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0 2 0x1148 8 0 4294967295 INT_GAIN_CAL_FIXED_CNT 0 4 INT_GAIN_CAL_FIXED_CNT_EN 5 5 INT_GAIN_CAL_CNT_SHIFT 6 8 INT_GAIN_CAL_BOUNCE_CNT 9 11 DISABLE_BIN_HOLD 12 12 DISABLE_INT_GAIN_HOLD 13 13 DISABLE_COARSE_CALDONE 14 14 RESERVED_15_15 15 15 ixDPCSSYS_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1 2 0x1149 7 0 4294967295 RX_VCO_OVRD_SEL 0 0 RX_VCO_FREQ_RST 1 1 RX_VCO_CAL_RST 2 2 RX_VCO_CONTCAL_EN 3 3 DISABLE_INT_CAL_MODE 4 4 DPLL_CAL_UG 5 8 DTB_SEL 9 15 ixDPCSSYS_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2 2 0x114a 4 0 4294967295 FREQ_TUNE_START_VAL 0 9 FREQ_TUNE_CAL_STEPS 10 13 SKIP_RX_VCO_FREQ_TUNE_CAL 14 14 SKIP_RX_VCO_CAL 15 15 ixDPCSSYS_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0 2 0x114b 4 0 4294967295 RX_VCO_STARTUP_TIME 0 6 RX_VCO_UPDATE_TIME 7 10 RX_VCO_CNTR_PWRUP_TIME 11 14 FAST_RX_VCO_WAIT 15 15 ixDPCSSYS_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1 2 0x114c 2 0 4294967295 RX_VCO_CNTR_SETTLE_TIME 0 2 RESERVED_15_3 3 15 ixDPCSSYS_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0 2 0x114d 6 0 4294967295 RX_ANA_CDR_FREQ_TUNE 0 9 RX_ANA_VCO_CNTR_PD 10 10 RX_ANA_VCO_CNTR_EN 11 11 RX_ANA_CDR_STARTUP 12 12 RX_ANA_CDR_VCO_EN 13 13 RESERVED_15_14 14 15 ixDPCSSYS_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1 2 0x114e 7 0 4294967295 RX_VCO_FSM_STATE 0 3 RX_VCO_FREQ_RST 4 4 RX_VCO_CAL_RST 5 5 RX_VCO_CONTCAL_EN 6 6 RX_VCO_CAL_DONE 7 7 DPLL_FREQ_RST 8 8 RESERVED_15_9 9 15 ixDPCSSYS_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_2 2 0x114f 4 0 4294967295 VCO_CNTR_FINAL 0 12 VCOCLK_TOO_FAST 13 13 RX_VCO_CORRECT 14 14 RX_VCO_UP 15 15 ixDPCSSYS_CR0_LANE1_DIG_RX_RX_ALIGN_XAUI_COMM_MASK 2 0x1150 2 0 4294967295 XAUI_COMM_MASK 0 9 RESERVED_15_10 10 15 ixDPCSSYS_CR0_LANE1_DIG_RX_LBERT_CTL 2 0x1151 3 0 4294967295 MODE 0 3 SYNC 4 4 RESERVED_15_5 5 15 ixDPCSSYS_CR0_LANE1_DIG_RX_LBERT_ERR 2 0x1152 2 0 4294967295 COUNT 0 14 OV14 15 15 ixDPCSSYS_CR0_LANE1_DIG_RX_CDR_CDR_CTL_0 2 0x1153 7 0 4294967295 PHDET_EN 0 1 PHDET_EDGE 2 3 PHDET_POL 4 4 PHDET_EN_PR_MODE 5 5 ALWAYS_REALIGN 6 6 DTB_SEL 7 10 RESERVED_15_11 11 15 ixDPCSSYS_CR0_LANE1_DIG_RX_CDR_CDR_CTL_1 2 0x1154 2 0 4294967295 SSC_OFF_CNT0 0 9 SSC_OFF_CNT1 10 15 ixDPCSSYS_CR0_LANE1_DIG_RX_CDR_CDR_CTL_2 2 0x1155 2 0 4294967295 SSC_ON_CNT0 0 8 SSC_ON_CNT1 9 15 ixDPCSSYS_CR0_LANE1_DIG_RX_CDR_CDR_CTL_3 2 0x1156 6 0 4294967295 SSC_OFF_PHUG0 0 2 SSC_OFF_PHUG1 3 5 SSC_OFF_FRUG0 6 8 OVRD_DPLL_GAIN 9 9 PHUG_OVRD_VALUE 10 12 FRUG_OVRD_VALUE 13 15 ixDPCSSYS_CR0_LANE1_DIG_RX_CDR_CDR_CTL_4 2 0x1157 6 0 4294967295 SSC_OFF_FRUG1 0 2 SSC_ON_FRUG0 3 5 SSC_ON_FRUG1 6 8 SSC_ON_PHUG0 9 11 SSC_ON_PHUG1 12 14 RESERVED_15_15 15 15 ixDPCSSYS_CR0_LANE1_DIG_RX_CDR_STAT 2 0x1158 3 0 4294967295 PHUG_VALUE 0 2 FRUG_VALUE 3 5 RESERVED_15_6 6 15 ixDPCSSYS_CR0_LANE1_DIG_RX_DPLL_FREQ 2 0x1159 2 0 4294967295 VAL 0 13 RESERVED_15_14 14 15 ixDPCSSYS_CR0_LANE1_DIG_RX_DPLL_FREQ_BOUND_0 2 0x115a 3 0 4294967295 FREQ_BOUND_EN 0 0 UPPER_FREQ_BOUND 1 10 RESERVED_15_11 11 15 ixDPCSSYS_CR0_LANE1_DIG_RX_DPLL_FREQ_BOUND_1 2 0x115b 2 0 4294967295 LOWER_FREQ_BOUND 0 9 RESERVED_15_10 10 15 ixDPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_0 2 0x1160 4 0 4294967295 N_TOP_ASM1 0 9 N_TGG_ASM1 10 13 START_ASM1 14 14 ADPT_CLK_DIV4_EN 15 15 ixDPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1 2 0x1161 5 0 4294967295 N_WAIT_ASM1 0 6 FAST_AFE_DFE_SETTLE 7 7 CTLE_POLE_OVRD_VAL 8 10 CTLE_POLE_OVRD_EN 11 11 RESERVED_15_12 12 15 ixDPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_2 2 0x1162 3 0 4294967295 TGG_PTTRN_0 0 4 TGG_PTTRN_1 5 9 RESERVED_15_10 10 15 ixDPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3 2 0x1163 8 0 4294967295 CTLE_EN 0 4 VGA_EN 5 5 ATT_EN 6 6 DFE_EN 7 11 EYEHE_EN 12 12 EYEHO_EN 13 13 TGG_EN 14 14 ESL_TWICE_DSL 15 15 ixDPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_4 2 0x1164 4 0 4294967295 CTLE_TH 0 3 VGA_TH 4 7 DFE1_TH 8 11 DFE2_TH 12 15 ixDPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_5 2 0x1165 4 0 4294967295 DFE3_TH 0 3 DFE4_TH 4 7 DFE5_TH 8 11 TH_OFFSET 12 15 ixDPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6 2 0x1166 6 0 4294967295 CTLE_MU 0 2 VGA_MU 3 5 ATT_MU 6 8 VGA_SAT_CNT 9 11 VGA_SAT_CNT_STICKY 12 12 ATT_LOW_TH 13 15 ixDPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_7 2 0x1167 4 0 4294967295 VGA_MIN_SAT 0 4 VGA_LEV_HIGH 5 9 VGA_LEV_LOW 10 14 RESERVED_15_15 15 15 ixDPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8 2 0x1168 6 0 4294967295 DFE1_MU 0 2 DFE2_MU 3 5 DFE3_MU 6 8 DFE4_MU 9 11 DFE5_MU 12 14 RESERVED_15_15 15 15 ixDPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_9 2 0x1169 2 0 4294967295 ERR_SLE_ADPT_INIT 0 7 ERR_SLO_ADPT_INIT 8 15 ixDPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG 2 0x116a 6 0 4294967295 RST_ADPT_ATT 0 0 RST_ADPT_VGA 1 1 RST_ADPT_CTLE_BOOST 2 2 RST_ADPT_CTLE_POLE 3 3 RST_ADPT_TAP1 4 4 RESERVED_15_5 5 15 ixDPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ATT_STATUS 2 0x116b 3 0 4294967295 ATT_ADPT_CODE 0 7 ASM1_DON 8 8 RESERVED_15_9 9 15 ixDPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_VGA_STATUS 2 0x116c 3 0 4294967295 VGA_ADPT_CODE 0 9 ASM1_DONE 10 10 RESERVED_15_11 11 15 ixDPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_CTLE_STATUS 2 0x116d 4 0 4294967295 CTLE_BOOST_ADPT_CODE 0 9 CTLE_POLE_ADPT_CODE 10 12 ASM1_DONE 13 13 RESERVED_15_14 14 15 ixDPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_DFE_TAP1_STATUS 2 0x116e 3 0 4294967295 DFE_TAP1_ADPT_CODE 0 12 ASM1_DONE 13 13 RESERVED_15_14 14 15 ixDPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_DFE_TAP2_STATUS 2 0x116f 3 0 4294967295 DFE_TAP2_ADPT_CODE 0 11 ASM1_DONE 12 12 RESERVED_15_13 13 15 ixDPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_DFE_TAP3_STATUS 2 0x1170 3 0 4294967295 DFE_TAP3_ADPT_CODE 0 11 ASM1_DONE 12 12 RESERVED_15_13 13 15 ixDPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_DFE_TAP4_STATUS 2 0x1171 3 0 4294967295 DFE_TAP4_ADPT_CODE 0 11 ASM1_DONE 12 12 RESERVED_15_13 13 15 ixDPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_DFE_TAP5_STATUS 2 0x1172 3 0 4294967295 DFE_TAP5_ADPT_CODE 0 11 ASM1_DONE 12 12 RESERVED_15_13 13 15 ixDPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_DFE_DATA_EVEN_VDAC_OFST 2 0x1173 2 0 4294967295 DFE_DATA_EVEN_VDAC_OFST 0 7 RESERVED_15_8 8 15 ixDPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_DFE_DATA_ODD_VDAC_OFST 2 0x1174 2 0 4294967295 DFE_DATA_ODD_VDAC_OFST 0 7 RESERVED_15_8 8 15 ixDPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN 2 0x1175 2 0 4294967295 RX_ANA_SLICER_CTRL_E 0 3 RESERVED_15_4 4 15 ixDPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD 2 0x1176 2 0 4294967295 RX_ANA_SLICER_CTRL_O 0 3 RESERVED_15_4 4 15 ixDPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST 2 0x1177 2 0 4294967295 DFE_ERROR_EVEN_VDAC_OFST 0 7 RESERVED_15_8 8 15 ixDPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST 2 0x1178 2 0 4294967295 DFE_ERROR_ODD_VDAC_OFST 0 7 RESERVED_15_8 8 15 ixDPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL 2 0x1179 2 0 4294967295 E_SLO_LVL 0 7 E_SLE_LVL 8 15 ixDPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_RESET 2 0x117a 2 0 4294967295 RESET_ASM1 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1 2 0x117b 4 0 4294967295 DFE_T1_IDAC 0 4 DFE_T2_IDAC 5 9 DCC_START_IDAC 10 14 RESERVED_15_15 15 15 ixDPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2 2 0x117c 3 0 4294967295 DFE_DAT_EVEN_VDAC 0 4 DFE_DAT_ODD_VDAC 5 9 RESERVED_15_10 10 15 ixDPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3 2 0x117d 3 0 4294967295 DFE_ERR_EVEN_VDAC 0 4 DFE_ERR_ODD_VDAC 5 9 RESERVED_15_10 10 15 ixDPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_CR_BANK_ADDR 2 0x117e 1 0 4294967295 ADDR 0 15 ixDPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_CR_BANK_DATA 2 0x117f 1 0 4294967295 DATA 0 15 ixDPCSSYS_CR0_LANE1_DIG_RX_STAT_LD_VAL_1 2 0x1180 2 0 4294967295 SC1_LD_VAL 0 14 SC1_START 15 15 ixDPCSSYS_CR0_LANE1_DIG_RX_STAT_DATA_MSK 2 0x1181 1 0 4294967295 DATA_MSK_15_0 0 15 ixDPCSSYS_CR0_LANE1_DIG_RX_STAT_MATCH_CTL0 2 0x1182 4 0 4294967295 PTTRN_MSK_CR1A_4_0 0 4 PTTRN_CR1A_4_0 5 9 DATA_MSK_19_16 10 13 SCOPE_DLY 14 15 ixDPCSSYS_CR0_LANE1_DIG_RX_STAT_MATCH_CTL1 2 0x1183 5 0 4294967295 PTTRN_CR1B_EN 0 0 PTTRN_MSK_CR1B_4_0 1 5 PTTRN_CR1B_4_0 6 10 PTTRN_CR1A_ADPT_EN 11 11 RESERVED_15_12 12 15 ixDPCSSYS_CR0_LANE1_DIG_RX_STAT_STAT_CTL0 2 0x1184 10 0 4294967295 RESERVED_0 0 0 CORR_SHFT_SEL_VGA 1 1 CORR_SHFT_SEL 2 2 CORR_SRC_SEL 3 4 CORR_MODE_EN 5 5 STAT_SHFT_SEL 6 9 STAT_SRC_SEL 10 12 STAT_RXCLK_SEL 13 13 SC_TIMER_MODE 14 14 SKIP_EN 15 15 ixDPCSSYS_CR0_LANE1_DIG_RX_STAT_STAT_CTL1 2 0x1185 13 0 4294967295 STAT_CNT_0_EN 0 0 STAT_CNT_1_EN 1 1 STAT_CNT_2_EN 2 2 STAT_CNT_3_EN 3 3 STAT_CNT_4_EN 4 4 STAT_CNT_5_EN 5 5 STAT_CNT_6_EN 6 6 RESERVED_8_7 7 8 SC_PAUSE 9 9 STAT_CLK_EN 10 10 DATA_DLY_SEL 11 12 VLD_LOSS_CLR 13 13 VLD_CTL 14 15 ixDPCSSYS_CR0_LANE1_DIG_RX_STAT_SMPL_CNT1 2 0x1186 2 0 4294967295 SMPL_CNT1 0 14 SMPL_CNT1_DONE 15 15 ixDPCSSYS_CR0_LANE1_DIG_RX_STAT_STAT_CNT_0 2 0x1187 2 0 4294967295 STAT_CNT_0 0 14 SMPL_CNT1_DONE 15 15 ixDPCSSYS_CR0_LANE1_DIG_RX_STAT_STAT_CNT_1 2 0x1188 2 0 4294967295 STAT_CNT_1 0 14 SMPL_CNT1_DONE 15 15 ixDPCSSYS_CR0_LANE1_DIG_RX_STAT_STAT_CNT_2 2 0x1189 2 0 4294967295 STAT_CNT_2 0 14 SMPL_CNT1_DONE 15 15 ixDPCSSYS_CR0_LANE1_DIG_RX_STAT_STAT_CNT_3 2 0x118a 2 0 4294967295 STAT_CNT_3 0 14 SMPL_CNT1_DONE 15 15 ixDPCSSYS_CR0_LANE1_DIG_RX_STAT_STAT_CNT_4 2 0x118b 2 0 4294967295 STAT_CNT_4 0 14 SMPL_CNT1_DONE 15 15 ixDPCSSYS_CR0_LANE1_DIG_RX_STAT_STAT_CNT_5 2 0x118c 2 0 4294967295 STAT_CNT_5 0 14 SMPL_CNT1_DONE 15 15 ixDPCSSYS_CR0_LANE1_DIG_RX_STAT_STAT_CNT_6 2 0x118d 2 0 4294967295 STAT_CNT_6 0 14 SMPL_CNT1_DONE 15 15 ixDPCSSYS_CR0_LANE1_DIG_RX_STAT_CAL_COMP_CLK_CTL 2 0x118e 3 0 4294967295 PRECHRGE_CNT 0 2 REF_DIV_CNT 3 5 RESERVED_15_6 6 15 ixDPCSSYS_CR0_LANE1_DIG_RX_STAT_MATCH_CTL2 2 0x118f 2 0 4294967295 PTTRN_CR1A_19_5 0 14 RESERVED_15_15 15 15 ixDPCSSYS_CR0_LANE1_DIG_RX_STAT_MATCH_CTL3 2 0x1190 2 0 4294967295 PTTRN_MSK_CR1A_19_5 0 14 RESERVED_15_15 15 15 ixDPCSSYS_CR0_LANE1_DIG_RX_STAT_MATCH_CTL4 2 0x1191 2 0 4294967295 PTTRN_CR1B_19_5 0 14 RESERVED_15_15 15 15 ixDPCSSYS_CR0_LANE1_DIG_RX_STAT_MATCH_CTL5 2 0x1192 2 0 4294967295 PTTRN_MSK_CR1B_19_5 0 14 RESERVED_15_15 15 15 ixDPCSSYS_CR0_LANE1_DIG_RX_STAT_STAT_CTL2 2 0x1193 4 0 4294967295 DATA_DLY_SEL_2 0 0 SCOPE_DLY_2 1 1 DISABLE_SAMPLE_COUNT 2 2 RESERVED_15_3 3 15 ixDPCSSYS_CR0_LANE1_DIG_RX_STAT_STAT_STOP 2 0x1194 2 0 4294967295 SC1_STOP 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR0_LANE1_DIG_MPHY_RX_PWM_CTL 2 0x1195 3 0 4294967295 RX_PWM_POL 0 0 RX_PWM_DATA_POL 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR0_LANE1_DIG_MPHY_RX_TERM_LS_CTL 2 0x1196 2 0 4294967295 RX_TERM_LCC_CNT 0 2 RESERVED_15_3 3 15 ixDPCSSYS_CR0_LANE1_DIG_MPHY_RX_ANA_PWM_CLK_STABLE_CNT 2 0x1197 2 0 4294967295 PWM_CLK_STABLE_CNT 0 3 RESERVED_15_4 4 15 ixDPCSSYS_CR0_LANE1_DIG_ANA_TX_OVRD_OUT 2 0x11a0 15 0 4294967295 TX_ANA_CLK_SHIFT 0 0 TX_ANA_DATA_EN 1 1 TX_ANA_REFGEN_EN 2 2 TX_ANA_VCM_HOLD 3 3 TX_ANA_CLK_EN 4 4 TX_ANA_WORD_CLK_EN 5 5 TX_ANA_MPLLA_CLK_EN 6 6 TX_ANA_MPLLB_CLK_EN 7 7 TX_ANA_RESET 8 8 TX_ANA_SERIAL_EN 9 9 TX_ANA_DATA_RATE 10 11 RESERVED 12 12 TX_DIV4_EN 13 13 TX_RXDET_EN 14 14 TX_OVRD_EN 15 15 ixDPCSSYS_CR0_LANE1_DIG_ANA_TX_TERM_CODE_OVRD_OUT 2 0x11a1 5 0 4294967295 TX_TERM_CODE 0 9 TX_TERM_OVRD_EN 10 10 TX_DRV_SRC 11 12 TX_DRV_SRC_OVRD_EN 13 13 RESERVED_15_14 14 15 ixDPCSSYS_CR0_LANE1_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT 2 0x11a2 3 0 4294967295 TX_TERM_DN_CLK 0 0 TX_TERM_CLK_SELF_CLEAR_DISABLE 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR0_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_0 2 0x11a3 3 0 4294967295 TX_ANA_LOAD_CLK 0 0 TX_ANA_CTRL_LEG_PULL_EN_13_0 1 14 TX_EQ_OVRD_EN 15 15 ixDPCSSYS_CR0_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_1 2 0x11a4 2 0 4294967295 TX_ANA_CTRL_LEG_PULL_EN_19_14 0 5 RESERVED_15_6 6 15 ixDPCSSYS_CR0_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_2 2 0x11a5 4 0 4294967295 RESERVED 0 2 TX_ANA_CTRL_EQ_MUX_SEL 3 6 TX_ANA_CTRL_PRE 7 12 RESERVED_15_13 13 15 ixDPCSSYS_CR0_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_3 2 0x11a6 2 0 4294967295 TX_ANA_CTRL_POST 0 8 RESERVED_15_9 9 15 ixDPCSSYS_CR0_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_4 2 0x11a7 1 0 4294967295 TX_ANA_CTRL_LEG_PULL_DIR_19_4 0 15 ixDPCSSYS_CR0_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_5 2 0x11a8 2 0 4294967295 TX_ANA_CTRL_LEG_PULL_DIR_3_0 0 3 RESERVED_15_4 4 15 ixDPCSSYS_CR0_LANE1_DIG_ANA_RX_CTL_OVRD_OUT 2 0x11a9 9 0 4294967295 RESERVED 0 0 RX_ANA_DATA_RATE 1 2 RX_ANA_WORD_CLK_EN 3 3 RX_ANA_DIV4_EN 4 4 RX_ANA_DFE_TAPS_EN 5 5 RX_ANA_ADAPTATION_EN 6 6 RX_LBK_CLK_EN 7 7 RX_CTL_OVRD_EN 8 8 RESERVED_15_9 9 15 ixDPCSSYS_CR0_LANE1_DIG_ANA_RX_PWR_OVRD_OUT 2 0x11aa 9 0 4294967295 RX_ANA_AFE_EN 0 0 RX_ANA_CLK_VREG_EN 1 1 RX_ANA_CLK_DCC_EN 2 2 RX_ANA_CLK_EN 3 3 RX_ANA_CDR_EN 4 4 RX_ANA_DESERIAL_EN 5 5 RX_PWR_OVRD_EN 6 6 RX_ANA_FAST_START 7 7 RESERVED_15_8 8 15 ixDPCSSYS_CR0_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0 2 0x11ab 7 0 4294967295 RX_ANA_CDR_VCO_EN 0 0 RX_ANA_CDR_STARTUP 1 1 RX_VCO_CDR_OVRD_EN 2 2 RX_ANA_CDR_FREQ_TUNE 3 12 RX_ANA_VCO_CNTR_EN 13 13 RX_ANA_VCO_CNTR_CLK 14 14 RX_CDR_FREQ_TUNE_OVRD_EN 15 15 ixDPCSSYS_CR0_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_1 2 0x11ac 3 0 4294967295 RX_ANA_CDR_VCO_LOWFREQ 0 0 RX_ANA_VCO_CNTR_PD 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR0_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_2 2 0x11ad 3 0 4294967295 RX_ANA_CDR_FREQ_TUNE_CLK 0 0 CDR_FREQ_TUNE_CLK_SELF_CLEAR_DISABLE 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR0_LANE1_DIG_ANA_RX_CAL 2 0x11ae 7 0 4294967295 RX_ANA_CAL_MUXA_SEL 0 4 RX_ANA_CAL_MUXB_SEL 5 9 RX_ANA_CAL_LPFBYP_EN 10 10 RESERVED 11 11 RX_ANA_SLICER_CAL_EN 12 12 RX_ANA_CAL_MODE 13 14 RX_ANA_CAL_COMP_EN 15 15 ixDPCSSYS_CR0_LANE1_DIG_ANA_RX_DAC_CTRL 2 0x11af 2 0 4294967295 RX_ANA_CAL_DAC_CTRL 0 7 RESERVED_15_8 8 15 ixDPCSSYS_CR0_LANE1_DIG_ANA_RX_DAC_CTRL_OVRD 2 0x11b0 2 0 4294967295 RX_CAL_DAC_CTRL_OVRD 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR0_LANE1_DIG_ANA_RX_DAC_CTRL_SEL 2 0x11b1 2 0 4294967295 RX_ANA_CAL_DAC_CTRL_SEL 0 4 RESERVED_15_5 5 15 ixDPCSSYS_CR0_LANE1_DIG_ANA_RX_AFE_ATT_VGA 2 0x11b2 5 0 4294967295 RX_ANA_AFE_ATT_LVL 0 2 RX_ANA_AFE_GAIN 3 6 RESERVED 7 10 RX_AFE_OVRD_EN 11 11 RESERVED_15_12 12 15 ixDPCSSYS_CR0_LANE1_DIG_ANA_RX_AFE_CTLE 2 0x11b3 3 0 4294967295 RESERVED 0 2 RX_ANA_AFE_CTLE_BOOST 3 7 RESERVED_15_8 8 15 ixDPCSSYS_CR0_LANE1_DIG_ANA_RX_SCOPE 2 0x11b4 7 0 4294967295 RX_ANA_SCOPE_EN 0 0 RX_ANA_SCOPE_SEL 1 2 RX_ANA_SCOPE_PH_CLK 3 3 RX_ANA_SCOPE_PHASE 4 11 RX_ANA_SCOPE_CLK_EN 12 12 RX_SCOPE_SELF_CLEAR_DISABLE 13 13 RESERVED_15_14 14 15 ixDPCSSYS_CR0_LANE1_DIG_ANA_RX_SLICER_CTRL 2 0x11b5 4 0 4294967295 RX_ANA_SLICER_CTRL_E 0 3 RX_ANA_SLICER_CTRL_O 4 7 RX_ANA_SLICER_CTRL_OVRD_EN 8 8 RESERVED_15_9 9 15 ixDPCSSYS_CR0_LANE1_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST 2 0x11b6 2 0 4294967295 RX_ANA_IQ_PHASE_ADJUST 0 6 RESERVED_15_7 7 15 ixDPCSSYS_CR0_LANE1_DIG_ANA_RX_ANA_IQ_SENSE_EN 2 0x11b7 2 0 4294967295 RX_ANA_IQ_SENSE_EN 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR0_LANE1_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN 2 0x11b8 3 0 4294967295 RX_ANA_CAL_DAC_CTRL_EN 0 0 DAC_CTRL_SELF_CLEAR_DISABLE 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR0_LANE1_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE 2 0x11b9 3 0 4294967295 RX_ANA_AFE_UPDATE_EN 0 0 AFE_UPDATE_SELF_CLEAR_DISABLE 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR0_LANE1_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK 2 0x11ba 3 0 4294967295 RX_ANA_IQ_PHASE_ADJUST_CLK 0 0 PHASE_ADJUST_SELF_CLEAR_DISABLE 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR0_LANE1_DIG_ANA_STATUS_0 2 0x11bb 9 0 4294967295 TX_ANA_CLK_SHIFT_ACK 0 0 TX_ANA_RXDETP_RESULT 1 1 TX_ANA_RXDETM_RESULT 2 2 TX_ANA_LOOPBACK_EN 3 3 TX_ANA_CLK_LB_EN 4 4 RX_ANA_CAL_RESULT 5 5 RX_ANA_SCOPE_DATA 6 6 TX_ANA_DCC_CAL_RESULT 7 7 TX_ANA_CTRL_EQ_MUX 8 15 ixDPCSSYS_CR0_LANE1_DIG_ANA_STATUS_1 2 0x11bc 2 0 4294967295 RX_ANA_VCO_CNTR 0 12 RESERVED_15_13 13 15 ixDPCSSYS_CR0_LANE1_DIG_ANA_RX_TERM_CODE_OVRD_OUT 2 0x11bd 3 0 4294967295 RX_TERM_CODE 0 5 RX_TERM_OVRD_EN 6 6 RESERVED_15_7 7 15 ixDPCSSYS_CR0_LANE1_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT 2 0x11be 3 0 4294967295 RX_TERM_CLK 0 0 RX_TERM_CLK_SELF_CLEAR_DISABLE 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR0_LANE1_DIG_ANA_MPHY_OVRD_OUT 2 0x11bf 9 0 4294967295 RX_ANA_SQ_CTRL_TRESH 0 2 RX_ANA_SQ_CTRL_TRESH_OVRD_EN 3 3 RX_ANA_SQ_CTRL_RESP 4 5 RX_ANA_SQ_CTRL_RESP_OVRD_EN 6 6 RX_ANA_PWM_EN 7 7 RX_ANA_PWM_EN_OVRD_EN 8 8 RX_ANA_PWM_CLK_SEL 9 10 RX_ANA_PWM_CLK_SEL_OVRD_EN 11 11 RESERVED_15_12 12 15 ixDPCSSYS_CR0_LANE1_DIG_ANA_SIGDET_OVRD_OUT_1 2 0x11c0 7 0 4294967295 RX_ANA_SIGDET_HF_THRESH 0 2 RX_ANA_SIGDET_HF_THRESH_OVRD_EN 3 3 RX_ANA_SIGDET_HF_CAL_TUNE 4 9 RX_ANA_SIGDET_CAL_TUNE_OVRD_EN 10 10 RX_ANA_SIGDET_CAL_EN 11 11 RX_ANA_SIGDET_CAL_EN_OVRD_EN 12 12 RESERVED_15_13 13 15 ixDPCSSYS_CR0_LANE1_DIG_ANA_SIGDET_OVRD_OUT_2 2 0x11c1 7 0 4294967295 RX_ANA_SIGDET_LF_THRESH 0 2 RX_ANA_SIGDET_LF_THRESH_OVRD_EN 3 3 RX_ANA_SIGDET_LF_FILTER_EN 4 4 RX_ANA_SIGDET_LF_FILTER_EN_OVRD_EN 5 5 RX_ANA_SIGDET_CAL_TUNE 6 11 RX_ANA_SIGDET_CAL_TUNE_OVRD_EN 12 12 RESERVED_15_13 13 15 ixDPCSSYS_CR0_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT 2 0x11c2 8 0 4294967295 TX_ANA_DCC_CAL_RANGE 0 1 TX_ANA_DCC_CAL_RANGE_OVRD_EN 2 2 TX_ANA_DCC_CAL_COMP_EN 3 3 TX_ANA_DCC_CAL_COMP_EN_OVRD_EN 4 4 TX_ANA_DCC_CAL_CTRL 5 12 TX_ANA_DCC_CAL_CTRL_OVRD_EN 13 13 TX_ANA_DCC_CAL_CTRL_EN 14 14 TX_ANA_DCC_CAL_CTRL_EN_OVRD_EN 15 15 ixDPCSSYS_CR0_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2 2 0x11c3 5 0 4294967295 TX_ANA_DCC_CAL_CTRL_SEL 0 2 TX_ANA_DCC_CAL_CTRL_SEL_OVRD_EN 3 3 TX_ANA_DCC_CLK_COMP 4 4 TX_ANA_DCC_CLK_COMP_OVRD_EN 5 5 RESERVED_15_6 6 15 ixDPCSSYS_CR0_LANE1_DIG_ANA_TX_OVRD_OUT_2 2 0x11c4 6 0 4294967295 TX_ANA_FAST_START 0 0 TX_ANA_FAST_START_OVRD_EN 1 1 TX_CLK_LB_EN 2 2 TX_CLK_LB_EN_OVRD_EN 3 3 TX_ACJTAG_EN 4 4 RESERVED_15_5 5 15 ixDPCSSYS_CR0_LANE1_ANA_TX_OVRD_MEAS 2 0x11e0 9 0 4294967295 OVRD_CLK_SHIFT 0 0 CLK_SHIFT_REG 0 0 MEAS_ATB_CAL_MUX 0 0 MEAS_ATB_CAL_COMP 0 0 OVRD_VCM_HOLD 0 0 VCM_HOLD_REG 0 0 PULL_UP_REG 0 0 PULL_DN_REG 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR0_LANE1_ANA_TX_PWR_OVRD 2 0x11e1 9 0 4294967295 OVRD_TX_LOOPBACK 0 0 LOOPBACK_EN_REG 0 0 REFGEN_EN_REG 0 0 CLK_DIV_EN_REG 0 0 DATA_EN_REG_INT 0 0 CLK_EN_REG 0 0 SERIAL_EN_REG 0 0 OVRD_EN 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR0_LANE1_ANA_TX_ALT_BUS 2 0x11e2 6 0 4294967295 DRV_SOURCE_REG 0 0 OVRD_ALT_BUS 0 0 ATB_S_ENABLE 0 0 TX_ALT_RINGO 0 0 JTAG_DATA_REG 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR0_LANE1_ANA_TX_ATB1 2 0x11e3 9 0 4294967295 MEAS_ATB_GD 0 0 MEAS_ATB_VDDH 0 0 OVERRIDE_RXDETREF 0 0 MEAS_ATB_VPTX 0 0 OVERRIDE_REGREF 0 0 MEAS_ATB_VREG_DRV 0 0 MEAS_ATB_VREG 0 0 MEAS_ATB_VPH_HALF 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR0_LANE1_ANA_TX_ATB2 2 0x11e4 9 0 4294967295 MEAS_ATB_VCM 0 0 MEAS_ATB_CAL_VDAC_CM 0 0 MEAS_ATB_CAL_VDAC_DIFF 0 0 MEAS_ATB_TXM 0 0 MEAS_ATB_TXP 0 0 MEAS_ATB_RXDETREF 0 0 LFPS_HIGH_PRIORITY 0 0 OSC_DIV4_EN 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR0_LANE1_ANA_TX_DCC_DAC 2 0x11e5 2 0 4294967295 DCC_DAC_REG 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR0_LANE1_ANA_TX_DCC_CTRL1 2 0x11e6 7 0 4294967295 NC0 0 0 OVRD_DCC_DAC_CTRL_SEL 0 0 DCC_DAC_CTRL_SEL_REG 0 0 OVRD_DCC_DAC_CTRL_EN 0 0 DCC_DAC_CTRL_EN_REG 0 0 OVRD_DCC_DAC_REG 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR0_LANE1_ANA_TX_TERM_CODE 2 0x11e7 2 0 4294967295 TERM_CODE_REG_70 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR0_LANE1_ANA_TX_TERM_CODE_CTRL 2 0x11e8 8 0 4294967295 VREG_BOOST_1 0 0 OVRD_UPDATE_TERM 0 0 UPDATE_TERM_REG 0 0 OVRD_RESET_TERM 0 0 RESET_TERM_REG 0 0 OVRD_TERM_CODE 0 0 TERM_CODE_REG_98 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR0_LANE1_ANA_TX_OVRD_CLK 2 0x11e9 9 0 4294967295 VREG_BOOST_0 0 0 CLK_LB_EN_REG 0 0 OVRD_LB_EN 0 0 MPLLB_CLK_EN_REG 0 0 MPLLA_CLK_EN_REG 0 0 OVRD_MPLLAB_EN 0 0 WORD_CLK_EN_REG 0 0 OVRD_WORD_CLK_EN 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR0_LANE1_ANA_TX_MISC1 2 0x11ea 8 0 4294967295 MEAS_ATB_CAL_CLK_ALIGN 0 0 OVRD_DCC_DAC_CTRL_RANGE 0 0 DCC_DAC_CTRL_RANGE_REG 0 0 OVRD_VREF_SEL 0 0 VREF_SEL_REG 0 0 FORCE_ATB_TXM 0 0 FORCE_ATB_TXP 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR0_LANE1_ANA_TX_MISC2 2 0x11eb 8 0 4294967295 TX_PEAKING_LVL 0 0 VREG_CP_GAIN_CTRL 0 0 TX_SLEW_EN 0 0 EN_INV_POST 0 0 EN_INV_PRE 0 0 TX_VREG_EN_BYP 0 0 TX_VDRIVER_PULLDN_EN 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR0_LANE1_ANA_TX_MISC3 2 0x11ec 4 0 4294967295 TX_VREG_OVRD_RING_CTRL 0 0 TX_DCC_LOWV 0 0 NC7_2 2 7 RESERVED_15_8 8 15 ixDPCSSYS_CR0_LANE1_ANA_TX_RESERVED2 2 0x11ed 2 0 4294967295 NC7_0 0 7 RESERVED_15_8 8 15 ixDPCSSYS_CR0_LANE1_ANA_TX_RESERVED3 2 0x11ee 2 0 4294967295 NC7_0 0 7 RESERVED_15_8 8 15 ixDPCSSYS_CR0_LANE1_ANA_TX_RESERVED4 2 0x11ef 2 0 4294967295 NC7_0 0 7 RESERVED_15_8 8 15 ixDPCSSYS_CR0_LANE1_ANA_RX_CLK_1 2 0x11f0 8 0 4294967295 CDR_VCO_STARTUP_CODE 0 0 CDR_VCO_TEMP_COMP_EN 0 0 CDR_VCO_USE_UNCAL_BIAS 0 0 OVERRIDE_CDR_EN 0 0 OVRD_CLK_EN 0 0 CLK_EN_REG 0 0 NC7 7 7 RESERVED_15_8 8 15 ixDPCSSYS_CR0_LANE1_ANA_RX_CLK_2 2 0x11f1 5 0 4294967295 IQ_PHASE_ADJUST_REG 0 0 OVRD_IQ_PHASE_ADJUST 0 0 RX_LOOPBACK_CLK_REG 0 0 OVRD_RX_LOOPBACK_CLK 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR0_LANE1_ANA_RX_CDR_DES 2 0x11f2 7 0 4294967295 OVRD_WORD_CLK_EN 0 0 WORD_CLK_EN_REG 0 0 PHDET_ODD_REG 0 0 PHDET_EVEN_REG 0 0 SIGDET_VREF_EXT_EN 0 0 NC7_5 5 7 RESERVED_15_8 8 15 ixDPCSSYS_CR0_LANE1_ANA_RX_SLC_CTRL 2 0x11f3 3 0 4294967295 RX_SLICER_CTRL_O_REG 0 0 RX_SLICER_CTRL_E_REG 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR0_LANE1_ANA_RX_PWR_CTRL1 2 0x11f4 8 0 4294967295 OVRD_ACJT_EN 0 0 ACJT_EN_REG 0 0 OVRD_AFE_EN 0 0 AFE_EN_REG 0 0 AFE_CM_SEL 0 0 ATT_PULLDN_EN 0 0 NC7_7 7 7 RESERVED_15_8 8 15 ixDPCSSYS_CR0_LANE1_ANA_RX_PWR_CTRL2 2 0x11f5 9 0 4294967295 OVRD_DFE_EN 0 0 DFE_EN_REG 0 0 OVRD_DESERIAL_EN 0 0 DESERIAL_EN_REG 0 0 OVRD_LOOPBACK_EN 0 0 LOOPBACK_EN_REG 0 0 OVRD_FAST_START 0 0 FAST_START_REG 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR0_LANE1_ANA_RX_SQ 2 0x11f6 7 0 4294967295 SQ_CTRL_RESP_REG 0 0 OVRD_SQ_CTRL_RESP 0 0 NC4_3 3 4 SQ_CTRL_TRESH_REG 0 0 OVRD_SQ_CTRL_TRESH 0 0 AFE_LOOPBACK_SEL 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR0_LANE1_ANA_RX_CAL1 2 0x11f7 5 0 4294967295 DFE_TAPS_EN_REG 0 0 OVRD_DFE_TAPS_EN 0 0 CAL_MUXB_SEL_REG 0 0 OVRD_CAL_MUXB_SEL 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR0_LANE1_ANA_RX_CAL2 2 0x11f8 5 0 4294967295 AFE_PD_EQ_OFFSET 0 0 CAL_IDACS_USE_UNCAL 0 0 CAL_MUXA_SEL_REG 0 0 OVRD_CAL_MUXA_SEL 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR0_LANE1_ANA_RX_ATB_REGREF 2 0x11f9 8 0 4294967295 OVERRIDE_REGREF_VCO 0 0 OVERRIDE_REGREF_CLK 0 0 OVERRIDE_REGREF_IQC 0 0 BOOST_REGREF_IQC 0 0 OVRD_RX_SLICER_CTRL 0 0 OVRD_RX_TERM_AC_DCZ 0 0 RX_TERM_AC_DCZ_REG 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR0_LANE1_ANA_RX_ATB_MEAS1 2 0x11fa 9 0 4294967295 MASTER_ATB_EN 0 0 MEAS_ATB_VP 0 0 MEAS_ATB_GD 0 0 MEAS_ATB_VREG_VCO 0 0 MEAS_ATB_VREG_CLK 0 0 MEAS_ATB_VREG_IQC 0 0 REGS_FB_DIV_CTRL 0 0 RX_VREG_CLK_BYPASS 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR0_LANE1_ANA_RX_ATB_MEAS2 2 0x11fb 2 0 4294967295 MEAS_ATB_RX 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR0_LANE1_ANA_RX_ATB_MEAS3 2 0x11fc 7 0 4294967295 MEAS_ATB_CDR_VCO_GD 0 0 MEAS_ATB_CDR_VCO_VIREF_200U 0 0 MEAS_ATB_VIBIAS_CDR_VCO 0 0 MEAS_ATB_CDR_VCO_VOSC 0 0 MEAS_ATB_CAL_MUX 0 0 RX_VREG_OVERRIDE_RING_CTRL 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR0_LANE1_ANA_RX_ATB_MEAS4 2 0x11fd 3 0 4294967295 MEAS_ATB_CAL_VREF 0 0 NC7 7 7 RESERVED_15_8 8 15 ixDPCSSYS_CR0_LANE1_ANA_RX_ATB_FRC 2 0x11fe 2 0 4294967295 FRC_ATB_CAL_VREF 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR0_LANE1_ANA_RX_RESERVED1 2 0x11ff 2 0 4294967295 NC7_0 0 7 RESERVED_15_8 8 15 ixDPCSSYS_CR0_LANE2_DIG_ASIC_LANE_OVRD_IN 2 0x1200 5 0 4294967295 LANE_TX2RX_SER_LB 0 0 LANE_RX2TX_PAR_LB 1 1 EN 2 2 RX_ACJTAG_EN 3 3 RESERVED_15_4 4 15 ixDPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_0 2 0x1201 12 0 4294967295 REQ 0 0 REQ_OVRD_EN 1 1 PSTATE 2 3 PSTATE_OVRD_EN 4 4 RATE 5 7 RATE_OVRD_EN 8 8 WIDTH 9 10 WIDTH_OVRD_EN 11 11 MPLLB_SEL 12 12 MPLLB_SEL_OVRD_EN 13 13 DATA_EN 14 14 DATA_EN_OVRD_EN 15 15 ixDPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_1 2 0x1202 11 0 4294967295 NYQUIST_DATA 0 0 DISABLE 1 1 BEACON_EN 2 2 EN 3 3 TX_MAIN_CURSOR 4 9 MAIN_OVRD_EN 10 10 ASYNC_DRV_EN 11 11 ASYNC_DRV_OVRD_EN 12 12 TX_VREGDRV_BYP_OVRD 13 13 TX_VREGDRV_BYP_OVRD_EN 14 14 RESERVED_15_15 15 15 ixDPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_2 2 0x1203 6 0 4294967295 TX_PRE_CURSOR 0 5 PRE_OVRD_EN 6 6 TX_POST_CURSOR 7 12 POST_OVRD_EN 13 13 HDMIMODE_EN 14 14 HDMIMODE_ENABLE_OVRD_EN 15 15 ixDPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_3 2 0x1204 15 0 4294967295 CLK_RDY 0 0 CLK_RDY_OVRD_EN 1 1 DETECT_RX_REQ 2 2 DETECT_RX_REQ_OVRD_EN 3 3 INVERT 4 4 INVERT_OVRD_EN 5 5 LPD 6 6 LPD_OVRD_EN 7 7 TX_DC_COUP_EN 8 8 TX_DC_COUP_EN_OVRD_EN 9 9 PMA_EXTENDED_FIFO_EN 10 10 PMA_EXTENDED_FIFO_EN_OVRD_EN 11 11 TX_MPHY_MODE_EN 12 12 TX_MPHY_MODE_EN_OVRD_EN 13 13 RESERVED_15_14 14 15 ixDPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_4 2 0x1205 3 0 4294967295 RESET 0 0 RESET_OVRD_EN 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_OUT 2 0x1206 5 0 4294967295 TX_ACK 0 0 EN_TX_ACK 1 1 DETRX_RESULT 2 2 EN_DETRX_RESULT 3 3 RESERVED_15_4 4 15 ixDPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_0 2 0x1207 11 0 4294967295 REQ 0 0 REQ_OVRD_EN 1 1 DATA_EN 2 2 DATA_EN_OVRD_EN 3 3 PSTATE 4 5 PSTATE_OVRD_EN 6 6 RATE 7 8 RATE_OVRD_EN 9 9 WIDTH 10 11 WIDTH_OVRD_EN 12 12 RESERVED_15_13 13 15 ixDPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_1 2 0x1208 5 0 4294967295 RX_REF_LD_VAL_5_0 0 5 RX_CDR_VCO_LOWFREQ 6 6 EN 7 7 RX_REF_LD_VAL_6 8 8 RESERVED_15_9 9 15 ixDPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_2 2 0x1209 3 0 4294967295 RX_VCO_LD_VAL 0 12 EN 13 13 RESERVED_15_14 14 15 ixDPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_3 2 0x120a 11 0 4294967295 CDR_TRACK_EN 0 0 CDR_TRACK_EN_OVRD_EN 1 1 CDR_SSC_EN 2 2 CDR_SSC_EN_OVRD_EN 3 3 ALIGN_EN 4 4 ALIGN_EN_OVRD_EN 5 5 CLK_SHIFT 6 6 CLK_SHIFT_OVRD_EN 7 7 DISABLE 8 8 DISABLE_OVRD_EN 9 9 RESERVED_15_10 10 15 ixDPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_4 2 0x120b 11 0 4294967295 LPD 0 0 LPD_OVRD_EN 1 1 INVERT 2 2 INVERT_OVRD_EN 3 3 ADAPT_AFE_EN 4 4 ADAPT_DFE_EN 5 5 ADPT_OVRD_EN 6 6 TERM_EN 7 7 TERM_ACDC 8 8 TERM_OVRD_EN 9 9 RESERVED_15_10 10 15 ixDPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_5 2 0x120c 3 0 4294967295 RESET 0 0 RESET_OVRD_EN 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0 2 0x120d 4 0 4294967295 EQ_ATT_LVL 0 2 EQ_AFE_GAIN 3 6 RESERVED 7 10 EQ_CTLE_BOOST 11 15 ixDPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1 2 0x120e 3 0 4294967295 EQ_DFE_TAP2 0 6 EQ_DFE_TAP1 7 14 EQ_OVRD_EN 15 15 ixDPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_OUT_0 2 0x120f 9 0 4294967295 ACK 0 0 ACK_OVRD_EN 1 1 ADAPT_STS 2 3 ADAPT_STS_OVRD_EN 4 4 RX_ASYNC_DATA 5 5 RX_ASYNC_DATA_OVRD_EN 6 6 RX_SQ_WEAKKEEP_OUT 7 7 RX_SQ_WEAKKEEP_OUT_OVRD_EN 8 8 RESERVED_15_9 9 15 ixDPCSSYS_CR0_LANE2_DIG_ASIC_LANE_ASIC_IN 2 0x1210 3 0 4294967295 LANE_TX2RX_SER_LB 0 0 LANE_RX2TX_PAR_LB 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR0_LANE2_DIG_ASIC_TX_ASIC_IN_0 2 0x1211 12 0 4294967295 CLK_RDY 0 0 RESET 1 1 INVERT 2 2 DATA_EN 3 3 REQ 4 4 LPD 5 5 PSTATE 6 7 RATE 8 10 WIDTH 11 12 MPLLB_SEL 13 13 DETECT_RX_REQ 14 14 DISABLE 15 15 ixDPCSSYS_CR0_LANE2_DIG_ASIC_TX_ASIC_IN_1 2 0x1212 7 0 4294967295 BEACON_EN 0 0 TX_MAIN_CURSOR 1 6 TX_ASYNC_EN 7 7 TX_ASYNC_DATA 8 8 TX_ASYNC_DRV_EN 9 9 TX_VREGDRV_BYP 10 10 RESERVED_15_11 11 15 ixDPCSSYS_CR0_LANE2_DIG_ASIC_TX_ASIC_IN_2 2 0x1213 3 0 4294967295 TX_PRE_CURSOR 0 5 TX_POST_CURSOR 6 11 RESERVED_15_12 12 15 ixDPCSSYS_CR0_LANE2_DIG_ASIC_TX_ASIC_OUT 2 0x1214 3 0 4294967295 TX_ACK 0 0 DETRX_RESULT 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR0_LANE2_DIG_ASIC_RX_ASIC_IN_0 2 0x1215 13 0 4294967295 RESET 0 0 INVERT 1 1 DATA_EN 2 2 REQ 3 3 LPD 4 4 PSTATE 5 6 RATE 7 8 WIDTH 9 10 RESERVED 11 11 ADAPT_AFE_EN 12 12 ADAPT_DFE_EN 13 13 CDR_TRACK_EN 14 14 RESERVED_15_15 15 15 ixDPCSSYS_CR0_LANE2_DIG_ASIC_RX_ASIC_IN_1 2 0x1216 7 0 4294967295 CDR_SSC_EN 0 0 ALIGN_EN 1 1 CLK_SHIFT 2 2 DISABLE 3 3 RX_TERM_EN 4 4 RX_TERM_ACDC 5 5 RESERVED_15_6 6 15 ixDPCSSYS_CR0_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0 2 0x1217 4 0 4294967295 EQ_ATT_LVL 0 2 EQ_AFE_GAIN 3 6 RESERVED 7 10 EQ_CTLE_BOOST 11 15 ixDPCSSYS_CR0_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_1 2 0x1218 3 0 4294967295 EQ_DFE_TAP2 0 6 EQ_DFE_TAP1 7 14 RESERVED_15_15 15 15 ixDPCSSYS_CR0_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0 2 0x1219 3 0 4294967295 RX_CDR_VCO_LOWFREQ 0 0 RX_REF_LD_VAL 1 7 RESERVED_15_8 8 15 ixDPCSSYS_CR0_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1 2 0x121a 2 0 4294967295 RX_VCO_LD_VAL 0 12 RESERVED_15_13 13 15 ixDPCSSYS_CR0_LANE2_DIG_ASIC_RX_ASIC_OUT_0 2 0x121b 4 0 4294967295 ACK 0 0 VALID 1 1 ADAPT_STS 2 3 RESERVED_15_4 4 15 ixDPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_6 2 0x121c 10 0 4294967295 RX_PWM_CLK_SEL 0 1 RX_PWM_CLK_SEL_OVRD_EN 2 2 RX_TERM_LCC_ON 3 3 RX_TERM_LS_ON 4 4 RX_TERM_LS_LCC_ON_OVRD_EN 5 5 RX_TERM_CTL 6 7 RX_TERM_CTL_OVRD_EN 8 8 RX_PWM_EN 9 9 RX_PWM_EN_OVRD_EN 10 10 RESERVED_15_11 11 15 ixDPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_5 2 0x121d 15 0 4294967295 RPTR_EN_MASTER_LANE 0 0 RPTR_EN_MASTER_LANE_OVRD_EN 1 1 DIG_CLK_EN_OTHER_LANE 2 2 DIG_CLK_EN_OTHER_LANE_OVRD_EN 3 3 DIG_CLK_STATE_MASTER_LANE 4 4 DIG_CLK_STATE_MASTER_LANE_OVRD_EN 5 5 SHIFT_MASTER_LANE 6 6 SHIFT_MASTER_LANE_ORVD_EN 7 7 SHIFT_ACK_OTHER_LANE 8 8 SHIFT_ACK_OTHER_LANE_OVRD_EN 9 9 LANE_MASTER 10 10 LANE_MASTER_OVRD_IN_EN 11 11 TX_DWORD_CLK_SYNC_OVRD 12 12 TX_DWORD_CLK_SYNC_OVRD_EN 13 13 RESERVED_15_14 14 15 ixDPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_OUT_1 2 0x121e 11 0 4294967295 RPTR_EN_OUT 0 0 RPTR_EN_OUT_OVRD_EN 1 1 DIG_CLK_EN_OUT 2 2 DIG_CLK_EN_OUT_OVRD_EN 3 3 DIG_CLK_STATE_OUT 4 4 DIG_CLK_STATE_OUT_OVRD_EN 5 5 SHIFT_OUT 6 6 SHIFT_OUT_OVRD_EN 7 7 SHIFT_ACK_OUT 8 8 SHIFT_ACK_OUT_OVRD_EN 9 9 RESERVED_15_10 10 15 ixDPCSSYS_CR0_LANE2_DIG_ASIC_OCLA 2 0x121f 3 0 4294967295 RX_DWORD_OCLA_CLK_EN 0 0 RX_DWORD_OCLA_DATA_EN 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0 2 0x1220 11 0 4294967295 TX_P0_ANA_REFGEN_EN 0 0 TX_P0_ANA_VCM_HOLD 1 1 TX_P0_ANA_CLK_EN 2 2 TX_P0_ANA_WORD_CLK_EN 3 3 TX_P0_ANA_RESET 4 4 TX_P0_ANA_SERIAL_EN 5 5 TX_P0_DIG_CLK_EN 6 6 TX_P0_DATA_EN 7 7 TX_P0_ALLOW_RXDET 8 8 TX_P0_ANA_DCC_COMP_CAL_EN 9 9 RESERVED_15_10 10 15 ixDPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S 2 0x1221 11 0 4294967295 TX_P0S_ANA_REFGEN_EN 0 0 TX_P0S_ANA_VCM_HOLD 1 1 TX_P0S_ANA_CLK_EN 2 2 TX_P0S_ANA_WORD_CLK_EN 3 3 TX_P0S_ANA_RESET 4 4 TX_P0S_ANA_SERIAL_EN 5 5 TX_P0S_DIG_CLK_EN 6 6 TX_P0S_DATA_EN 7 7 TX_P0S_ALLOW_RXDET 8 8 TX_P0S_ANA_DCC_COMP_CAL_EN 9 9 RESERVED_15_10 10 15 ixDPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1 2 0x1222 11 0 4294967295 TX_P1_ANA_REFGEN_EN 0 0 TX_P1_ANA_VCM_HOLD 1 1 TX_P1_ANA_CLK_EN 2 2 TX_P1_ANA_WORD_CLK_EN 3 3 TX_P1_ANA_RESET 4 4 TX_P1_ANA_SERIAL_EN 5 5 TX_P1_DIG_CLK_EN 6 6 TX_P1_DATA_EN 7 7 TX_P1_ALLOW_RXDET 8 8 TX_P1_ANA_DCC_COMP_CAL_EN 9 9 RESERVED_15_10 10 15 ixDPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2 2 0x1223 12 0 4294967295 TX_P2_ANA_REFGEN_EN 0 0 TX_P2_ANA_VCM_HOLD 1 1 TX_P2_ANA_CLK_EN 2 2 TX_P2_ANA_WORD_CLK_EN 3 3 TX_P2_ANA_RESET 4 4 TX_P2_ANA_SERIAL_EN 5 5 TX_P2_DIG_CLK_EN 6 6 TX_P2_DATA_EN 7 7 TX_P2_ALLOW_RXDET 8 8 TX_P2_ALLOW_VBOOST 9 9 TX_P2_ANA_DCC_COMP_CAL_EN 10 10 RESERVED_15_11 11 15 ixDPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_0 2 0x1224 2 0 4294967295 TX_REFGEN_EN_TIME 0 7 TX_CLK_EN 8 15 ixDPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_1 2 0x1225 2 0 4294967295 TX_VCM_HOLD_TIME_14_0 0 14 SKIP_TX_VCM_HOLD_WAIT 15 15 ixDPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_2 2 0x1226 2 0 4294967295 TX_VBOOST_DIS_TIME_12_0 0 12 DTB_SEL 13 15 ixDPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_3 2 0x1227 3 0 4294967295 TX_VCM_HOLD_TIME_17_15 0 2 TX_VBOOST_DIS_TIME_13 3 3 RESERVED_15_4 4 15 ixDPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_4 2 0x1228 2 0 4294967295 TX_VCM_HOLD_GS_TIME 0 14 SKIP_TX_VCM_HOLD_GS_PULSE 15 15 ixDPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_5 2 0x1229 5 0 4294967295 TX_RXDET_TIME 0 9 FAST_TX_RXDET 10 10 TX_RESET_TIME 11 12 TX_SERIAL_EN_TIME 13 14 RESERVED_15_15 15 15 ixDPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_DCC_CR_BANK_ADDR 2 0x122a 1 0 4294967295 ADDR 0 15 ixDPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_DCC_CR_BANK_DATA 2 0x122b 1 0 4294967295 DATA 0 15 ixDPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_DCC_DAC_CTRL 2 0x122c 2 0 4294967295 CTRL 0 7 RESERVED_15_8 8 15 ixDPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_DCC_DAC_RANGE 2 0x122d 2 0 4294967295 CTRL 0 1 RESERVED_15_2 2 15 ixDPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_DCC_DAC_SEL 2 0x122e 6 0 4294967295 SEL 0 2 REQ 3 3 CTRL_UPD 4 4 RANGE_UPD 5 5 BIN_HOT 6 6 RESERVED_15_7 7 15 ixDPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_DCC_DAC_ACK 2 0x122f 2 0 4294967295 ACK 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_DCC_DAC_ADDR 2 0x1230 1 0 4294967295 ADDR 0 15 ixDPCSSYS_CR0_LANE2_DIG_TX_CLK_ALIGN_TX_CTL_0 2 0x1231 4 0 4294967295 TX_NUM_2UI_SHIFTS_16B_MODE 0 3 TX_NUM_2UI_SHIFTS_20B_MODE 4 7 TX_FIFO_BYPASS 8 8 RESERVED_15_9 9 15 ixDPCSSYS_CR0_LANE2_DIG_TX_LBERT_CTL 2 0x1232 4 0 4294967295 MODE 0 3 TRIGGER_ERR 4 4 PAT0 5 14 RESERVED_15_15 15 15 ixDPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0 2 0x1240 12 0 4294967295 RX_P0_ANA_AFE_EN 0 0 RX_P0_ANA_CLK_VREG_EN 1 1 RESERVED_1 2 2 RX_P0_ANA_CLK_EN 3 3 RESERVED_0 4 4 RX_P0_ANA_DESER_EN 5 5 RX_P0_ANA_CDR_EN 6 6 RX_P0_VCO_FREQ_RST 7 7 RX_P0_VCO_CAL_RST 8 8 RX_P0_VCO_CONTCAL_EN 9 9 RX_P0_DIG_CLK_EN 10 10 RESERVED_15_11 11 15 ixDPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S 2 0x1241 12 0 4294967295 RX_P0S_ANA_AFE_EN 0 0 RX_P0S_ANA_CLK_VREG_EN 1 1 RESERVED_2 2 2 RX_P0S_ANA_CLK_EN 3 3 RESERVED_4 4 4 RX_P0S_ANA_DESER_EN 5 5 RX_P0S_ANA_CDR_EN 6 6 RX_P0S_VCO_FREQ_RST 7 7 RX_P0S_VCO_CAL_RST 8 8 RX_P0S_VCO_CONTCAL_EN 9 9 RX_P0S_DIG_CLK_EN 10 10 RESERVED_15_11 11 15 ixDPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1 2 0x1242 12 0 4294967295 RX_P1_ANA_AFE_EN 0 0 RX_P1_ANA_CLK_VREG_EN 1 1 RESERVED_2 2 2 RX_P1_ANA_CLK_EN 3 3 RESERVED_4 4 4 RX_P1_ANA_DESER_EN 5 5 RX_P1_ANA_CDR_EN 6 6 RX_P1_VCO_FREQ_RST 7 7 RX_P1_VCO_CAL_RST 8 8 RX_P1_VCO_CONTCAL_EN 9 9 RX_P1_DIG_CLK_EN 10 10 RESERVED_15_11 11 15 ixDPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2 2 0x1243 12 0 4294967295 RX_P2_ANA_AFE_EN 0 0 RX_P2_ANA_CLK_VREG_EN 1 1 RESERVED_2 2 2 RX_P2_ANA_CLK_EN 3 3 RESERVED_4 4 4 RX_P2_ANA_DESER_EN 5 5 RX_P2_ANA_CDR_EN 6 6 RX_P2_VCO_FREQ_RST 7 7 RX_P2_VCO_CAL_RST 8 8 RX_P2_VCO_CONTCAL_EN 9 9 RX_P2_DIG_CLK_EN 10 10 RESERVED_15_11 11 15 ixDPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1 2 0x1245 5 0 4294967295 RX_AFE_EN_TIME 0 5 FAST_RX_AFE_EN 6 6 RX_VREG_EN_TIME 7 12 FAST_RX_VREG_EN 13 13 RESERVED_15_14 14 15 ixDPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_2 2 0x1246 4 0 4294967295 RX_CLK_EN_TIME 0 5 FAST_RX_CLK_EN 6 6 RX_FAST_START_TIME 7 10 RESERVED_15_11 11 15 ixDPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_3 2 0x1247 5 0 4294967295 RX_RATE_TIME 0 1 RSVD_3_7_2 2 7 RX_CDR_EN_TIME 8 11 RX_DESER_EN_TIME 12 13 RX_DESER_DIS_TIME 14 15 ixDPCSSYS_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0 2 0x1248 8 0 4294967295 INT_GAIN_CAL_FIXED_CNT 0 4 INT_GAIN_CAL_FIXED_CNT_EN 5 5 INT_GAIN_CAL_CNT_SHIFT 6 8 INT_GAIN_CAL_BOUNCE_CNT 9 11 DISABLE_BIN_HOLD 12 12 DISABLE_INT_GAIN_HOLD 13 13 DISABLE_COARSE_CALDONE 14 14 RESERVED_15_15 15 15 ixDPCSSYS_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1 2 0x1249 7 0 4294967295 RX_VCO_OVRD_SEL 0 0 RX_VCO_FREQ_RST 1 1 RX_VCO_CAL_RST 2 2 RX_VCO_CONTCAL_EN 3 3 DISABLE_INT_CAL_MODE 4 4 DPLL_CAL_UG 5 8 DTB_SEL 9 15 ixDPCSSYS_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2 2 0x124a 4 0 4294967295 FREQ_TUNE_START_VAL 0 9 FREQ_TUNE_CAL_STEPS 10 13 SKIP_RX_VCO_FREQ_TUNE_CAL 14 14 SKIP_RX_VCO_CAL 15 15 ixDPCSSYS_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0 2 0x124b 4 0 4294967295 RX_VCO_STARTUP_TIME 0 6 RX_VCO_UPDATE_TIME 7 10 RX_VCO_CNTR_PWRUP_TIME 11 14 FAST_RX_VCO_WAIT 15 15 ixDPCSSYS_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1 2 0x124c 2 0 4294967295 RX_VCO_CNTR_SETTLE_TIME 0 2 RESERVED_15_3 3 15 ixDPCSSYS_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0 2 0x124d 6 0 4294967295 RX_ANA_CDR_FREQ_TUNE 0 9 RX_ANA_VCO_CNTR_PD 10 10 RX_ANA_VCO_CNTR_EN 11 11 RX_ANA_CDR_STARTUP 12 12 RX_ANA_CDR_VCO_EN 13 13 RESERVED_15_14 14 15 ixDPCSSYS_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1 2 0x124e 7 0 4294967295 RX_VCO_FSM_STATE 0 3 RX_VCO_FREQ_RST 4 4 RX_VCO_CAL_RST 5 5 RX_VCO_CONTCAL_EN 6 6 RX_VCO_CAL_DONE 7 7 DPLL_FREQ_RST 8 8 RESERVED_15_9 9 15 ixDPCSSYS_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_2 2 0x124f 4 0 4294967295 VCO_CNTR_FINAL 0 12 VCOCLK_TOO_FAST 13 13 RX_VCO_CORRECT 14 14 RX_VCO_UP 15 15 ixDPCSSYS_CR0_LANE2_DIG_RX_RX_ALIGN_XAUI_COMM_MASK 2 0x1250 2 0 4294967295 XAUI_COMM_MASK 0 9 RESERVED_15_10 10 15 ixDPCSSYS_CR0_LANE2_DIG_RX_LBERT_CTL 2 0x1251 3 0 4294967295 MODE 0 3 SYNC 4 4 RESERVED_15_5 5 15 ixDPCSSYS_CR0_LANE2_DIG_RX_LBERT_ERR 2 0x1252 2 0 4294967295 COUNT 0 14 OV14 15 15 ixDPCSSYS_CR0_LANE2_DIG_RX_CDR_CDR_CTL_0 2 0x1253 7 0 4294967295 PHDET_EN 0 1 PHDET_EDGE 2 3 PHDET_POL 4 4 PHDET_EN_PR_MODE 5 5 ALWAYS_REALIGN 6 6 DTB_SEL 7 10 RESERVED_15_11 11 15 ixDPCSSYS_CR0_LANE2_DIG_RX_CDR_CDR_CTL_1 2 0x1254 2 0 4294967295 SSC_OFF_CNT0 0 9 SSC_OFF_CNT1 10 15 ixDPCSSYS_CR0_LANE2_DIG_RX_CDR_CDR_CTL_2 2 0x1255 2 0 4294967295 SSC_ON_CNT0 0 8 SSC_ON_CNT1 9 15 ixDPCSSYS_CR0_LANE2_DIG_RX_CDR_CDR_CTL_3 2 0x1256 6 0 4294967295 SSC_OFF_PHUG0 0 2 SSC_OFF_PHUG1 3 5 SSC_OFF_FRUG0 6 8 OVRD_DPLL_GAIN 9 9 PHUG_OVRD_VALUE 10 12 FRUG_OVRD_VALUE 13 15 ixDPCSSYS_CR0_LANE2_DIG_RX_CDR_CDR_CTL_4 2 0x1257 6 0 4294967295 SSC_OFF_FRUG1 0 2 SSC_ON_FRUG0 3 5 SSC_ON_FRUG1 6 8 SSC_ON_PHUG0 9 11 SSC_ON_PHUG1 12 14 RESERVED_15_15 15 15 ixDPCSSYS_CR0_LANE2_DIG_RX_CDR_STAT 2 0x1258 3 0 4294967295 PHUG_VALUE 0 2 FRUG_VALUE 3 5 RESERVED_15_6 6 15 ixDPCSSYS_CR0_LANE2_DIG_RX_DPLL_FREQ 2 0x1259 2 0 4294967295 VAL 0 13 RESERVED_15_14 14 15 ixDPCSSYS_CR0_LANE2_DIG_RX_DPLL_FREQ_BOUND_0 2 0x125a 3 0 4294967295 FREQ_BOUND_EN 0 0 UPPER_FREQ_BOUND 1 10 RESERVED_15_11 11 15 ixDPCSSYS_CR0_LANE2_DIG_RX_DPLL_FREQ_BOUND_1 2 0x125b 2 0 4294967295 LOWER_FREQ_BOUND 0 9 RESERVED_15_10 10 15 ixDPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_0 2 0x1260 4 0 4294967295 N_TOP_ASM1 0 9 N_TGG_ASM1 10 13 START_ASM1 14 14 ADPT_CLK_DIV4_EN 15 15 ixDPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1 2 0x1261 5 0 4294967295 N_WAIT_ASM1 0 6 FAST_AFE_DFE_SETTLE 7 7 CTLE_POLE_OVRD_VAL 8 10 CTLE_POLE_OVRD_EN 11 11 RESERVED_15_12 12 15 ixDPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_2 2 0x1262 3 0 4294967295 TGG_PTTRN_0 0 4 TGG_PTTRN_1 5 9 RESERVED_15_10 10 15 ixDPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3 2 0x1263 8 0 4294967295 CTLE_EN 0 4 VGA_EN 5 5 ATT_EN 6 6 DFE_EN 7 11 EYEHE_EN 12 12 EYEHO_EN 13 13 TGG_EN 14 14 ESL_TWICE_DSL 15 15 ixDPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_4 2 0x1264 4 0 4294967295 CTLE_TH 0 3 VGA_TH 4 7 DFE1_TH 8 11 DFE2_TH 12 15 ixDPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_5 2 0x1265 4 0 4294967295 DFE3_TH 0 3 DFE4_TH 4 7 DFE5_TH 8 11 TH_OFFSET 12 15 ixDPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6 2 0x1266 6 0 4294967295 CTLE_MU 0 2 VGA_MU 3 5 ATT_MU 6 8 VGA_SAT_CNT 9 11 VGA_SAT_CNT_STICKY 12 12 ATT_LOW_TH 13 15 ixDPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_7 2 0x1267 4 0 4294967295 VGA_MIN_SAT 0 4 VGA_LEV_HIGH 5 9 VGA_LEV_LOW 10 14 RESERVED_15_15 15 15 ixDPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8 2 0x1268 6 0 4294967295 DFE1_MU 0 2 DFE2_MU 3 5 DFE3_MU 6 8 DFE4_MU 9 11 DFE5_MU 12 14 RESERVED_15_15 15 15 ixDPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_9 2 0x1269 2 0 4294967295 ERR_SLE_ADPT_INIT 0 7 ERR_SLO_ADPT_INIT 8 15 ixDPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG 2 0x126a 6 0 4294967295 RST_ADPT_ATT 0 0 RST_ADPT_VGA 1 1 RST_ADPT_CTLE_BOOST 2 2 RST_ADPT_CTLE_POLE 3 3 RST_ADPT_TAP1 4 4 RESERVED_15_5 5 15 ixDPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ATT_STATUS 2 0x126b 3 0 4294967295 ATT_ADPT_CODE 0 7 ASM1_DON 8 8 RESERVED_15_9 9 15 ixDPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_VGA_STATUS 2 0x126c 3 0 4294967295 VGA_ADPT_CODE 0 9 ASM1_DONE 10 10 RESERVED_15_11 11 15 ixDPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_CTLE_STATUS 2 0x126d 4 0 4294967295 CTLE_BOOST_ADPT_CODE 0 9 CTLE_POLE_ADPT_CODE 10 12 ASM1_DONE 13 13 RESERVED_15_14 14 15 ixDPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_DFE_TAP1_STATUS 2 0x126e 3 0 4294967295 DFE_TAP1_ADPT_CODE 0 12 ASM1_DONE 13 13 RESERVED_15_14 14 15 ixDPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_DFE_TAP2_STATUS 2 0x126f 3 0 4294967295 DFE_TAP2_ADPT_CODE 0 11 ASM1_DONE 12 12 RESERVED_15_13 13 15 ixDPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_DFE_TAP3_STATUS 2 0x1270 3 0 4294967295 DFE_TAP3_ADPT_CODE 0 11 ASM1_DONE 12 12 RESERVED_15_13 13 15 ixDPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_DFE_TAP4_STATUS 2 0x1271 3 0 4294967295 DFE_TAP4_ADPT_CODE 0 11 ASM1_DONE 12 12 RESERVED_15_13 13 15 ixDPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_DFE_TAP5_STATUS 2 0x1272 3 0 4294967295 DFE_TAP5_ADPT_CODE 0 11 ASM1_DONE 12 12 RESERVED_15_13 13 15 ixDPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_DFE_DATA_EVEN_VDAC_OFST 2 0x1273 2 0 4294967295 DFE_DATA_EVEN_VDAC_OFST 0 7 RESERVED_15_8 8 15 ixDPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_DFE_DATA_ODD_VDAC_OFST 2 0x1274 2 0 4294967295 DFE_DATA_ODD_VDAC_OFST 0 7 RESERVED_15_8 8 15 ixDPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN 2 0x1275 2 0 4294967295 RX_ANA_SLICER_CTRL_E 0 3 RESERVED_15_4 4 15 ixDPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD 2 0x1276 2 0 4294967295 RX_ANA_SLICER_CTRL_O 0 3 RESERVED_15_4 4 15 ixDPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST 2 0x1277 2 0 4294967295 DFE_ERROR_EVEN_VDAC_OFST 0 7 RESERVED_15_8 8 15 ixDPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST 2 0x1278 2 0 4294967295 DFE_ERROR_ODD_VDAC_OFST 0 7 RESERVED_15_8 8 15 ixDPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL 2 0x1279 2 0 4294967295 E_SLO_LVL 0 7 E_SLE_LVL 8 15 ixDPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_RESET 2 0x127a 2 0 4294967295 RESET_ASM1 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1 2 0x127b 4 0 4294967295 DFE_T1_IDAC 0 4 DFE_T2_IDAC 5 9 DCC_START_IDAC 10 14 RESERVED_15_15 15 15 ixDPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2 2 0x127c 3 0 4294967295 DFE_DAT_EVEN_VDAC 0 4 DFE_DAT_ODD_VDAC 5 9 RESERVED_15_10 10 15 ixDPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3 2 0x127d 3 0 4294967295 DFE_ERR_EVEN_VDAC 0 4 DFE_ERR_ODD_VDAC 5 9 RESERVED_15_10 10 15 ixDPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_CR_BANK_ADDR 2 0x127e 1 0 4294967295 ADDR 0 15 ixDPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_CR_BANK_DATA 2 0x127f 1 0 4294967295 DATA 0 15 ixDPCSSYS_CR0_LANE2_DIG_RX_STAT_LD_VAL_1 2 0x1280 2 0 4294967295 SC1_LD_VAL 0 14 SC1_START 15 15 ixDPCSSYS_CR0_LANE2_DIG_RX_STAT_DATA_MSK 2 0x1281 1 0 4294967295 DATA_MSK_15_0 0 15 ixDPCSSYS_CR0_LANE2_DIG_RX_STAT_MATCH_CTL0 2 0x1282 4 0 4294967295 PTTRN_MSK_CR1A_4_0 0 4 PTTRN_CR1A_4_0 5 9 DATA_MSK_19_16 10 13 SCOPE_DLY 14 15 ixDPCSSYS_CR0_LANE2_DIG_RX_STAT_MATCH_CTL1 2 0x1283 5 0 4294967295 PTTRN_CR1B_EN 0 0 PTTRN_MSK_CR1B_4_0 1 5 PTTRN_CR1B_4_0 6 10 PTTRN_CR1A_ADPT_EN 11 11 RESERVED_15_12 12 15 ixDPCSSYS_CR0_LANE2_DIG_RX_STAT_STAT_CTL0 2 0x1284 10 0 4294967295 RESERVED_0 0 0 CORR_SHFT_SEL_VGA 1 1 CORR_SHFT_SEL 2 2 CORR_SRC_SEL 3 4 CORR_MODE_EN 5 5 STAT_SHFT_SEL 6 9 STAT_SRC_SEL 10 12 STAT_RXCLK_SEL 13 13 SC_TIMER_MODE 14 14 SKIP_EN 15 15 ixDPCSSYS_CR0_LANE2_DIG_RX_STAT_STAT_CTL1 2 0x1285 13 0 4294967295 STAT_CNT_0_EN 0 0 STAT_CNT_1_EN 1 1 STAT_CNT_2_EN 2 2 STAT_CNT_3_EN 3 3 STAT_CNT_4_EN 4 4 STAT_CNT_5_EN 5 5 STAT_CNT_6_EN 6 6 RESERVED_8_7 7 8 SC_PAUSE 9 9 STAT_CLK_EN 10 10 DATA_DLY_SEL 11 12 VLD_LOSS_CLR 13 13 VLD_CTL 14 15 ixDPCSSYS_CR0_LANE2_DIG_RX_STAT_SMPL_CNT1 2 0x1286 2 0 4294967295 SMPL_CNT1 0 14 SMPL_CNT1_DONE 15 15 ixDPCSSYS_CR0_LANE2_DIG_RX_STAT_STAT_CNT_0 2 0x1287 2 0 4294967295 STAT_CNT_0 0 14 SMPL_CNT1_DONE 15 15 ixDPCSSYS_CR0_LANE2_DIG_RX_STAT_STAT_CNT_1 2 0x1288 2 0 4294967295 STAT_CNT_1 0 14 SMPL_CNT1_DONE 15 15 ixDPCSSYS_CR0_LANE2_DIG_RX_STAT_STAT_CNT_2 2 0x1289 2 0 4294967295 STAT_CNT_2 0 14 SMPL_CNT1_DONE 15 15 ixDPCSSYS_CR0_LANE2_DIG_RX_STAT_STAT_CNT_3 2 0x128a 2 0 4294967295 STAT_CNT_3 0 14 SMPL_CNT1_DONE 15 15 ixDPCSSYS_CR0_LANE2_DIG_RX_STAT_STAT_CNT_4 2 0x128b 2 0 4294967295 STAT_CNT_4 0 14 SMPL_CNT1_DONE 15 15 ixDPCSSYS_CR0_LANE2_DIG_RX_STAT_STAT_CNT_5 2 0x128c 2 0 4294967295 STAT_CNT_5 0 14 SMPL_CNT1_DONE 15 15 ixDPCSSYS_CR0_LANE2_DIG_RX_STAT_STAT_CNT_6 2 0x128d 2 0 4294967295 STAT_CNT_6 0 14 SMPL_CNT1_DONE 15 15 ixDPCSSYS_CR0_LANE2_DIG_RX_STAT_CAL_COMP_CLK_CTL 2 0x128e 3 0 4294967295 PRECHRGE_CNT 0 2 REF_DIV_CNT 3 5 RESERVED_15_6 6 15 ixDPCSSYS_CR0_LANE2_DIG_RX_STAT_MATCH_CTL2 2 0x128f 2 0 4294967295 PTTRN_CR1A_19_5 0 14 RESERVED_15_15 15 15 ixDPCSSYS_CR0_LANE2_DIG_RX_STAT_MATCH_CTL3 2 0x1290 2 0 4294967295 PTTRN_MSK_CR1A_19_5 0 14 RESERVED_15_15 15 15 ixDPCSSYS_CR0_LANE2_DIG_RX_STAT_MATCH_CTL4 2 0x1291 2 0 4294967295 PTTRN_CR1B_19_5 0 14 RESERVED_15_15 15 15 ixDPCSSYS_CR0_LANE2_DIG_RX_STAT_MATCH_CTL5 2 0x1292 2 0 4294967295 PTTRN_MSK_CR1B_19_5 0 14 RESERVED_15_15 15 15 ixDPCSSYS_CR0_LANE2_DIG_RX_STAT_STAT_CTL2 2 0x1293 4 0 4294967295 DATA_DLY_SEL_2 0 0 SCOPE_DLY_2 1 1 DISABLE_SAMPLE_COUNT 2 2 RESERVED_15_3 3 15 ixDPCSSYS_CR0_LANE2_DIG_RX_STAT_STAT_STOP 2 0x1294 2 0 4294967295 SC1_STOP 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR0_LANE2_DIG_MPHY_RX_PWM_CTL 2 0x1295 3 0 4294967295 RX_PWM_POL 0 0 RX_PWM_DATA_POL 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR0_LANE2_DIG_MPHY_RX_TERM_LS_CTL 2 0x1296 2 0 4294967295 RX_TERM_LCC_CNT 0 2 RESERVED_15_3 3 15 ixDPCSSYS_CR0_LANE2_DIG_MPHY_RX_ANA_PWM_CLK_STABLE_CNT 2 0x1297 2 0 4294967295 PWM_CLK_STABLE_CNT 0 3 RESERVED_15_4 4 15 ixDPCSSYS_CR0_LANE2_DIG_ANA_TX_OVRD_OUT 2 0x12a0 15 0 4294967295 TX_ANA_CLK_SHIFT 0 0 TX_ANA_DATA_EN 1 1 TX_ANA_REFGEN_EN 2 2 TX_ANA_VCM_HOLD 3 3 TX_ANA_CLK_EN 4 4 TX_ANA_WORD_CLK_EN 5 5 TX_ANA_MPLLA_CLK_EN 6 6 TX_ANA_MPLLB_CLK_EN 7 7 TX_ANA_RESET 8 8 TX_ANA_SERIAL_EN 9 9 TX_ANA_DATA_RATE 10 11 RESERVED 12 12 TX_DIV4_EN 13 13 TX_RXDET_EN 14 14 TX_OVRD_EN 15 15 ixDPCSSYS_CR0_LANE2_DIG_ANA_TX_TERM_CODE_OVRD_OUT 2 0x12a1 5 0 4294967295 TX_TERM_CODE 0 9 TX_TERM_OVRD_EN 10 10 TX_DRV_SRC 11 12 TX_DRV_SRC_OVRD_EN 13 13 RESERVED_15_14 14 15 ixDPCSSYS_CR0_LANE2_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT 2 0x12a2 3 0 4294967295 TX_TERM_DN_CLK 0 0 TX_TERM_CLK_SELF_CLEAR_DISABLE 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR0_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_0 2 0x12a3 3 0 4294967295 TX_ANA_LOAD_CLK 0 0 TX_ANA_CTRL_LEG_PULL_EN_13_0 1 14 TX_EQ_OVRD_EN 15 15 ixDPCSSYS_CR0_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_1 2 0x12a4 2 0 4294967295 TX_ANA_CTRL_LEG_PULL_EN_19_14 0 5 RESERVED_15_6 6 15 ixDPCSSYS_CR0_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_2 2 0x12a5 4 0 4294967295 RESERVED 0 2 TX_ANA_CTRL_EQ_MUX_SEL 3 6 TX_ANA_CTRL_PRE 7 12 RESERVED_15_13 13 15 ixDPCSSYS_CR0_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_3 2 0x12a6 2 0 4294967295 TX_ANA_CTRL_POST 0 8 RESERVED_15_9 9 15 ixDPCSSYS_CR0_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_4 2 0x12a7 1 0 4294967295 TX_ANA_CTRL_LEG_PULL_DIR_19_4 0 15 ixDPCSSYS_CR0_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_5 2 0x12a8 2 0 4294967295 TX_ANA_CTRL_LEG_PULL_DIR_3_0 0 3 RESERVED_15_4 4 15 ixDPCSSYS_CR0_LANE2_DIG_ANA_RX_CTL_OVRD_OUT 2 0x12a9 9 0 4294967295 RESERVED 0 0 RX_ANA_DATA_RATE 1 2 RX_ANA_WORD_CLK_EN 3 3 RX_ANA_DIV4_EN 4 4 RX_ANA_DFE_TAPS_EN 5 5 RX_ANA_ADAPTATION_EN 6 6 RX_LBK_CLK_EN 7 7 RX_CTL_OVRD_EN 8 8 RESERVED_15_9 9 15 ixDPCSSYS_CR0_LANE2_DIG_ANA_RX_PWR_OVRD_OUT 2 0x12aa 9 0 4294967295 RX_ANA_AFE_EN 0 0 RX_ANA_CLK_VREG_EN 1 1 RX_ANA_CLK_DCC_EN 2 2 RX_ANA_CLK_EN 3 3 RX_ANA_CDR_EN 4 4 RX_ANA_DESERIAL_EN 5 5 RX_PWR_OVRD_EN 6 6 RX_ANA_FAST_START 7 7 RESERVED_15_8 8 15 ixDPCSSYS_CR0_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0 2 0x12ab 7 0 4294967295 RX_ANA_CDR_VCO_EN 0 0 RX_ANA_CDR_STARTUP 1 1 RX_VCO_CDR_OVRD_EN 2 2 RX_ANA_CDR_FREQ_TUNE 3 12 RX_ANA_VCO_CNTR_EN 13 13 RX_ANA_VCO_CNTR_CLK 14 14 RX_CDR_FREQ_TUNE_OVRD_EN 15 15 ixDPCSSYS_CR0_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_1 2 0x12ac 3 0 4294967295 RX_ANA_CDR_VCO_LOWFREQ 0 0 RX_ANA_VCO_CNTR_PD 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR0_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_2 2 0x12ad 3 0 4294967295 RX_ANA_CDR_FREQ_TUNE_CLK 0 0 CDR_FREQ_TUNE_CLK_SELF_CLEAR_DISABLE 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR0_LANE2_DIG_ANA_RX_CAL 2 0x12ae 7 0 4294967295 RX_ANA_CAL_MUXA_SEL 0 4 RX_ANA_CAL_MUXB_SEL 5 9 RX_ANA_CAL_LPFBYP_EN 10 10 RESERVED 11 11 RX_ANA_SLICER_CAL_EN 12 12 RX_ANA_CAL_MODE 13 14 RX_ANA_CAL_COMP_EN 15 15 ixDPCSSYS_CR0_LANE2_DIG_ANA_RX_DAC_CTRL 2 0x12af 2 0 4294967295 RX_ANA_CAL_DAC_CTRL 0 7 RESERVED_15_8 8 15 ixDPCSSYS_CR0_LANE2_DIG_ANA_RX_DAC_CTRL_OVRD 2 0x12b0 2 0 4294967295 RX_CAL_DAC_CTRL_OVRD 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR0_LANE2_DIG_ANA_RX_DAC_CTRL_SEL 2 0x12b1 2 0 4294967295 RX_ANA_CAL_DAC_CTRL_SEL 0 4 RESERVED_15_5 5 15 ixDPCSSYS_CR0_LANE2_DIG_ANA_RX_AFE_ATT_VGA 2 0x12b2 5 0 4294967295 RX_ANA_AFE_ATT_LVL 0 2 RX_ANA_AFE_GAIN 3 6 RESERVED 7 10 RX_AFE_OVRD_EN 11 11 RESERVED_15_12 12 15 ixDPCSSYS_CR0_LANE2_DIG_ANA_RX_AFE_CTLE 2 0x12b3 3 0 4294967295 RESERVED 0 2 RX_ANA_AFE_CTLE_BOOST 3 7 RESERVED_15_8 8 15 ixDPCSSYS_CR0_LANE2_DIG_ANA_RX_SCOPE 2 0x12b4 7 0 4294967295 RX_ANA_SCOPE_EN 0 0 RX_ANA_SCOPE_SEL 1 2 RX_ANA_SCOPE_PH_CLK 3 3 RX_ANA_SCOPE_PHASE 4 11 RX_ANA_SCOPE_CLK_EN 12 12 RX_SCOPE_SELF_CLEAR_DISABLE 13 13 RESERVED_15_14 14 15 ixDPCSSYS_CR0_LANE2_DIG_ANA_RX_SLICER_CTRL 2 0x12b5 4 0 4294967295 RX_ANA_SLICER_CTRL_E 0 3 RX_ANA_SLICER_CTRL_O 4 7 RX_ANA_SLICER_CTRL_OVRD_EN 8 8 RESERVED_15_9 9 15 ixDPCSSYS_CR0_LANE2_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST 2 0x12b6 2 0 4294967295 RX_ANA_IQ_PHASE_ADJUST 0 6 RESERVED_15_7 7 15 ixDPCSSYS_CR0_LANE2_DIG_ANA_RX_ANA_IQ_SENSE_EN 2 0x12b7 2 0 4294967295 RX_ANA_IQ_SENSE_EN 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR0_LANE2_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN 2 0x12b8 3 0 4294967295 RX_ANA_CAL_DAC_CTRL_EN 0 0 DAC_CTRL_SELF_CLEAR_DISABLE 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR0_LANE2_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE 2 0x12b9 3 0 4294967295 RX_ANA_AFE_UPDATE_EN 0 0 AFE_UPDATE_SELF_CLEAR_DISABLE 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR0_LANE2_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK 2 0x12ba 3 0 4294967295 RX_ANA_IQ_PHASE_ADJUST_CLK 0 0 PHASE_ADJUST_SELF_CLEAR_DISABLE 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR0_LANE2_DIG_ANA_STATUS_0 2 0x12bb 9 0 4294967295 TX_ANA_CLK_SHIFT_ACK 0 0 TX_ANA_RXDETP_RESULT 1 1 TX_ANA_RXDETM_RESULT 2 2 TX_ANA_LOOPBACK_EN 3 3 TX_ANA_CLK_LB_EN 4 4 RX_ANA_CAL_RESULT 5 5 RX_ANA_SCOPE_DATA 6 6 TX_ANA_DCC_CAL_RESULT 7 7 TX_ANA_CTRL_EQ_MUX 8 15 ixDPCSSYS_CR0_LANE2_DIG_ANA_STATUS_1 2 0x12bc 2 0 4294967295 RX_ANA_VCO_CNTR 0 12 RESERVED_15_13 13 15 ixDPCSSYS_CR0_LANE2_DIG_ANA_RX_TERM_CODE_OVRD_OUT 2 0x12bd 3 0 4294967295 RX_TERM_CODE 0 5 RX_TERM_OVRD_EN 6 6 RESERVED_15_7 7 15 ixDPCSSYS_CR0_LANE2_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT 2 0x12be 3 0 4294967295 RX_TERM_CLK 0 0 RX_TERM_CLK_SELF_CLEAR_DISABLE 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR0_LANE2_DIG_ANA_MPHY_OVRD_OUT 2 0x12bf 9 0 4294967295 RX_ANA_SQ_CTRL_TRESH 0 2 RX_ANA_SQ_CTRL_TRESH_OVRD_EN 3 3 RX_ANA_SQ_CTRL_RESP 4 5 RX_ANA_SQ_CTRL_RESP_OVRD_EN 6 6 RX_ANA_PWM_EN 7 7 RX_ANA_PWM_EN_OVRD_EN 8 8 RX_ANA_PWM_CLK_SEL 9 10 RX_ANA_PWM_CLK_SEL_OVRD_EN 11 11 RESERVED_15_12 12 15 ixDPCSSYS_CR0_LANE2_DIG_ANA_SIGDET_OVRD_OUT_1 2 0x12c0 7 0 4294967295 RX_ANA_SIGDET_HF_THRESH 0 2 RX_ANA_SIGDET_HF_THRESH_OVRD_EN 3 3 RX_ANA_SIGDET_HF_CAL_TUNE 4 9 RX_ANA_SIGDET_CAL_TUNE_OVRD_EN 10 10 RX_ANA_SIGDET_CAL_EN 11 11 RX_ANA_SIGDET_CAL_EN_OVRD_EN 12 12 RESERVED_15_13 13 15 ixDPCSSYS_CR0_LANE2_DIG_ANA_SIGDET_OVRD_OUT_2 2 0x12c1 7 0 4294967295 RX_ANA_SIGDET_LF_THRESH 0 2 RX_ANA_SIGDET_LF_THRESH_OVRD_EN 3 3 RX_ANA_SIGDET_LF_FILTER_EN 4 4 RX_ANA_SIGDET_LF_FILTER_EN_OVRD_EN 5 5 RX_ANA_SIGDET_CAL_TUNE 6 11 RX_ANA_SIGDET_CAL_TUNE_OVRD_EN 12 12 RESERVED_15_13 13 15 ixDPCSSYS_CR0_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT 2 0x12c2 8 0 4294967295 TX_ANA_DCC_CAL_RANGE 0 1 TX_ANA_DCC_CAL_RANGE_OVRD_EN 2 2 TX_ANA_DCC_CAL_COMP_EN 3 3 TX_ANA_DCC_CAL_COMP_EN_OVRD_EN 4 4 TX_ANA_DCC_CAL_CTRL 5 12 TX_ANA_DCC_CAL_CTRL_OVRD_EN 13 13 TX_ANA_DCC_CAL_CTRL_EN 14 14 TX_ANA_DCC_CAL_CTRL_EN_OVRD_EN 15 15 ixDPCSSYS_CR0_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2 2 0x12c3 5 0 4294967295 TX_ANA_DCC_CAL_CTRL_SEL 0 2 TX_ANA_DCC_CAL_CTRL_SEL_OVRD_EN 3 3 TX_ANA_DCC_CLK_COMP 4 4 TX_ANA_DCC_CLK_COMP_OVRD_EN 5 5 RESERVED_15_6 6 15 ixDPCSSYS_CR0_LANE2_DIG_ANA_TX_OVRD_OUT_2 2 0x12c4 6 0 4294967295 TX_ANA_FAST_START 0 0 TX_ANA_FAST_START_OVRD_EN 1 1 TX_CLK_LB_EN 2 2 TX_CLK_LB_EN_OVRD_EN 3 3 TX_ACJTAG_EN 4 4 RESERVED_15_5 5 15 ixDPCSSYS_CR0_LANE2_ANA_TX_OVRD_MEAS 2 0x12e0 9 0 4294967295 OVRD_CLK_SHIFT 0 0 CLK_SHIFT_REG 0 0 MEAS_ATB_CAL_MUX 0 0 MEAS_ATB_CAL_COMP 0 0 OVRD_VCM_HOLD 0 0 VCM_HOLD_REG 0 0 PULL_UP_REG 0 0 PULL_DN_REG 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR0_LANE2_ANA_TX_PWR_OVRD 2 0x12e1 9 0 4294967295 OVRD_TX_LOOPBACK 0 0 LOOPBACK_EN_REG 0 0 REFGEN_EN_REG 0 0 CLK_DIV_EN_REG 0 0 DATA_EN_REG_INT 0 0 CLK_EN_REG 0 0 SERIAL_EN_REG 0 0 OVRD_EN 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR0_LANE2_ANA_TX_ALT_BUS 2 0x12e2 6 0 4294967295 DRV_SOURCE_REG 0 0 OVRD_ALT_BUS 0 0 ATB_S_ENABLE 0 0 TX_ALT_RINGO 0 0 JTAG_DATA_REG 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR0_LANE2_ANA_TX_ATB1 2 0x12e3 9 0 4294967295 MEAS_ATB_GD 0 0 MEAS_ATB_VDDH 0 0 OVERRIDE_RXDETREF 0 0 MEAS_ATB_VPTX 0 0 OVERRIDE_REGREF 0 0 MEAS_ATB_VREG_DRV 0 0 MEAS_ATB_VREG 0 0 MEAS_ATB_VPH_HALF 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR0_LANE2_ANA_TX_ATB2 2 0x12e4 9 0 4294967295 MEAS_ATB_VCM 0 0 MEAS_ATB_CAL_VDAC_CM 0 0 MEAS_ATB_CAL_VDAC_DIFF 0 0 MEAS_ATB_TXM 0 0 MEAS_ATB_TXP 0 0 MEAS_ATB_RXDETREF 0 0 LFPS_HIGH_PRIORITY 0 0 OSC_DIV4_EN 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR0_LANE2_ANA_TX_DCC_DAC 2 0x12e5 2 0 4294967295 DCC_DAC_REG 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR0_LANE2_ANA_TX_DCC_CTRL1 2 0x12e6 7 0 4294967295 NC0 0 0 OVRD_DCC_DAC_CTRL_SEL 0 0 DCC_DAC_CTRL_SEL_REG 0 0 OVRD_DCC_DAC_CTRL_EN 0 0 DCC_DAC_CTRL_EN_REG 0 0 OVRD_DCC_DAC_REG 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR0_LANE2_ANA_TX_TERM_CODE 2 0x12e7 2 0 4294967295 TERM_CODE_REG_70 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR0_LANE2_ANA_TX_TERM_CODE_CTRL 2 0x12e8 8 0 4294967295 VREG_BOOST_1 0 0 OVRD_UPDATE_TERM 0 0 UPDATE_TERM_REG 0 0 OVRD_RESET_TERM 0 0 RESET_TERM_REG 0 0 OVRD_TERM_CODE 0 0 TERM_CODE_REG_98 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR0_LANE2_ANA_TX_OVRD_CLK 2 0x12e9 9 0 4294967295 VREG_BOOST_0 0 0 CLK_LB_EN_REG 0 0 OVRD_LB_EN 0 0 MPLLB_CLK_EN_REG 0 0 MPLLA_CLK_EN_REG 0 0 OVRD_MPLLAB_EN 0 0 WORD_CLK_EN_REG 0 0 OVRD_WORD_CLK_EN 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR0_LANE2_ANA_TX_MISC1 2 0x12ea 8 0 4294967295 MEAS_ATB_CAL_CLK_ALIGN 0 0 OVRD_DCC_DAC_CTRL_RANGE 0 0 DCC_DAC_CTRL_RANGE_REG 0 0 OVRD_VREF_SEL 0 0 VREF_SEL_REG 0 0 FORCE_ATB_TXM 0 0 FORCE_ATB_TXP 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR0_LANE2_ANA_TX_MISC2 2 0x12eb 8 0 4294967295 TX_PEAKING_LVL 0 0 VREG_CP_GAIN_CTRL 0 0 TX_SLEW_EN 0 0 EN_INV_POST 0 0 EN_INV_PRE 0 0 TX_VREG_EN_BYP 0 0 TX_VDRIVER_PULLDN_EN 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR0_LANE2_ANA_TX_MISC3 2 0x12ec 4 0 4294967295 TX_VREG_OVRD_RING_CTRL 0 0 TX_DCC_LOWV 0 0 NC7_2 2 7 RESERVED_15_8 8 15 ixDPCSSYS_CR0_LANE2_ANA_TX_RESERVED2 2 0x12ed 2 0 4294967295 NC7_0 0 7 RESERVED_15_8 8 15 ixDPCSSYS_CR0_LANE2_ANA_TX_RESERVED3 2 0x12ee 2 0 4294967295 NC7_0 0 7 RESERVED_15_8 8 15 ixDPCSSYS_CR0_LANE2_ANA_TX_RESERVED4 2 0x12ef 2 0 4294967295 NC7_0 0 7 RESERVED_15_8 8 15 ixDPCSSYS_CR0_LANE2_ANA_RX_CLK_1 2 0x12f0 8 0 4294967295 CDR_VCO_STARTUP_CODE 0 0 CDR_VCO_TEMP_COMP_EN 0 0 CDR_VCO_USE_UNCAL_BIAS 0 0 OVERRIDE_CDR_EN 0 0 OVRD_CLK_EN 0 0 CLK_EN_REG 0 0 NC7 7 7 RESERVED_15_8 8 15 ixDPCSSYS_CR0_LANE2_ANA_RX_CLK_2 2 0x12f1 5 0 4294967295 IQ_PHASE_ADJUST_REG 0 0 OVRD_IQ_PHASE_ADJUST 0 0 RX_LOOPBACK_CLK_REG 0 0 OVRD_RX_LOOPBACK_CLK 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR0_LANE2_ANA_RX_CDR_DES 2 0x12f2 7 0 4294967295 OVRD_WORD_CLK_EN 0 0 WORD_CLK_EN_REG 0 0 PHDET_ODD_REG 0 0 PHDET_EVEN_REG 0 0 SIGDET_VREF_EXT_EN 0 0 NC7_5 5 7 RESERVED_15_8 8 15 ixDPCSSYS_CR0_LANE2_ANA_RX_SLC_CTRL 2 0x12f3 3 0 4294967295 RX_SLICER_CTRL_O_REG 0 0 RX_SLICER_CTRL_E_REG 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR0_LANE2_ANA_RX_PWR_CTRL1 2 0x12f4 8 0 4294967295 OVRD_ACJT_EN 0 0 ACJT_EN_REG 0 0 OVRD_AFE_EN 0 0 AFE_EN_REG 0 0 AFE_CM_SEL 0 0 ATT_PULLDN_EN 0 0 NC7_7 7 7 RESERVED_15_8 8 15 ixDPCSSYS_CR0_LANE2_ANA_RX_PWR_CTRL2 2 0x12f5 9 0 4294967295 OVRD_DFE_EN 0 0 DFE_EN_REG 0 0 OVRD_DESERIAL_EN 0 0 DESERIAL_EN_REG 0 0 OVRD_LOOPBACK_EN 0 0 LOOPBACK_EN_REG 0 0 OVRD_FAST_START 0 0 FAST_START_REG 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR0_LANE2_ANA_RX_SQ 2 0x12f6 7 0 4294967295 SQ_CTRL_RESP_REG 0 0 OVRD_SQ_CTRL_RESP 0 0 NC4_3 3 4 SQ_CTRL_TRESH_REG 0 0 OVRD_SQ_CTRL_TRESH 0 0 AFE_LOOPBACK_SEL 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR0_LANE2_ANA_RX_CAL1 2 0x12f7 5 0 4294967295 DFE_TAPS_EN_REG 0 0 OVRD_DFE_TAPS_EN 0 0 CAL_MUXB_SEL_REG 0 0 OVRD_CAL_MUXB_SEL 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR0_LANE2_ANA_RX_CAL2 2 0x12f8 5 0 4294967295 AFE_PD_EQ_OFFSET 0 0 CAL_IDACS_USE_UNCAL 0 0 CAL_MUXA_SEL_REG 0 0 OVRD_CAL_MUXA_SEL 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR0_LANE2_ANA_RX_ATB_REGREF 2 0x12f9 8 0 4294967295 OVERRIDE_REGREF_VCO 0 0 OVERRIDE_REGREF_CLK 0 0 OVERRIDE_REGREF_IQC 0 0 BOOST_REGREF_IQC 0 0 OVRD_RX_SLICER_CTRL 0 0 OVRD_RX_TERM_AC_DCZ 0 0 RX_TERM_AC_DCZ_REG 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR0_LANE2_ANA_RX_ATB_MEAS1 2 0x12fa 9 0 4294967295 MASTER_ATB_EN 0 0 MEAS_ATB_VP 0 0 MEAS_ATB_GD 0 0 MEAS_ATB_VREG_VCO 0 0 MEAS_ATB_VREG_CLK 0 0 MEAS_ATB_VREG_IQC 0 0 REGS_FB_DIV_CTRL 0 0 RX_VREG_CLK_BYPASS 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR0_LANE2_ANA_RX_ATB_MEAS2 2 0x12fb 2 0 4294967295 MEAS_ATB_RX 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR0_LANE2_ANA_RX_ATB_MEAS3 2 0x12fc 7 0 4294967295 MEAS_ATB_CDR_VCO_GD 0 0 MEAS_ATB_CDR_VCO_VIREF_200U 0 0 MEAS_ATB_VIBIAS_CDR_VCO 0 0 MEAS_ATB_CDR_VCO_VOSC 0 0 MEAS_ATB_CAL_MUX 0 0 RX_VREG_OVERRIDE_RING_CTRL 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR0_LANE2_ANA_RX_ATB_MEAS4 2 0x12fd 3 0 4294967295 MEAS_ATB_CAL_VREF 0 0 NC7 7 7 RESERVED_15_8 8 15 ixDPCSSYS_CR0_LANE2_ANA_RX_ATB_FRC 2 0x12fe 2 0 4294967295 FRC_ATB_CAL_VREF 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR0_LANE2_ANA_RX_RESERVED1 2 0x12ff 2 0 4294967295 NC7_0 0 7 RESERVED_15_8 8 15 ixDPCSSYS_CR0_LANE3_DIG_ASIC_LANE_OVRD_IN 2 0x1300 5 0 4294967295 LANE_TX2RX_SER_LB 0 0 LANE_RX2TX_PAR_LB 1 1 EN 2 2 RX_ACJTAG_EN 3 3 RESERVED_15_4 4 15 ixDPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_0 2 0x1301 12 0 4294967295 REQ 0 0 REQ_OVRD_EN 1 1 PSTATE 2 3 PSTATE_OVRD_EN 4 4 RATE 5 7 RATE_OVRD_EN 8 8 WIDTH 9 10 WIDTH_OVRD_EN 11 11 MPLLB_SEL 12 12 MPLLB_SEL_OVRD_EN 13 13 DATA_EN 14 14 DATA_EN_OVRD_EN 15 15 ixDPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_1 2 0x1302 11 0 4294967295 NYQUIST_DATA 0 0 DISABLE 1 1 BEACON_EN 2 2 EN 3 3 TX_MAIN_CURSOR 4 9 MAIN_OVRD_EN 10 10 ASYNC_DRV_EN 11 11 ASYNC_DRV_OVRD_EN 12 12 TX_VREGDRV_BYP_OVRD 13 13 TX_VREGDRV_BYP_OVRD_EN 14 14 RESERVED_15_15 15 15 ixDPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_2 2 0x1303 6 0 4294967295 TX_PRE_CURSOR 0 5 PRE_OVRD_EN 6 6 TX_POST_CURSOR 7 12 POST_OVRD_EN 13 13 HDMIMODE_EN 14 14 HDMIMODE_ENABLE_OVRD_EN 15 15 ixDPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_3 2 0x1304 15 0 4294967295 CLK_RDY 0 0 CLK_RDY_OVRD_EN 1 1 DETECT_RX_REQ 2 2 DETECT_RX_REQ_OVRD_EN 3 3 INVERT 4 4 INVERT_OVRD_EN 5 5 LPD 6 6 LPD_OVRD_EN 7 7 TX_DC_COUP_EN 8 8 TX_DC_COUP_EN_OVRD_EN 9 9 PMA_EXTENDED_FIFO_EN 10 10 PMA_EXTENDED_FIFO_EN_OVRD_EN 11 11 TX_MPHY_MODE_EN 12 12 TX_MPHY_MODE_EN_OVRD_EN 13 13 RESERVED_15_14 14 15 ixDPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_4 2 0x1305 3 0 4294967295 RESET 0 0 RESET_OVRD_EN 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_OUT 2 0x1306 5 0 4294967295 TX_ACK 0 0 EN_TX_ACK 1 1 DETRX_RESULT 2 2 EN_DETRX_RESULT 3 3 RESERVED_15_4 4 15 ixDPCSSYS_CR0_LANE3_DIG_ASIC_RX_OVRD_OUT_0 2 0x130f 9 0 4294967295 ACK 0 0 ACK_OVRD_EN 1 1 ADAPT_STS 2 3 ADAPT_STS_OVRD_EN 4 4 RX_ASYNC_DATA 5 5 RX_ASYNC_DATA_OVRD_EN 6 6 RX_SQ_WEAKKEEP_OUT 7 7 RX_SQ_WEAKKEEP_OUT_OVRD_EN 8 8 RESERVED_15_9 9 15 ixDPCSSYS_CR0_LANE3_DIG_ASIC_LANE_ASIC_IN 2 0x1310 3 0 4294967295 LANE_TX2RX_SER_LB 0 0 LANE_RX2TX_PAR_LB 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR0_LANE3_DIG_ASIC_TX_ASIC_IN_0 2 0x1311 12 0 4294967295 CLK_RDY 0 0 RESET 1 1 INVERT 2 2 DATA_EN 3 3 REQ 4 4 LPD 5 5 PSTATE 6 7 RATE 8 10 WIDTH 11 12 MPLLB_SEL 13 13 DETECT_RX_REQ 14 14 DISABLE 15 15 ixDPCSSYS_CR0_LANE3_DIG_ASIC_TX_ASIC_IN_1 2 0x1312 7 0 4294967295 BEACON_EN 0 0 TX_MAIN_CURSOR 1 6 TX_ASYNC_EN 7 7 TX_ASYNC_DATA 8 8 TX_ASYNC_DRV_EN 9 9 TX_VREGDRV_BYP 10 10 RESERVED_15_11 11 15 ixDPCSSYS_CR0_LANE3_DIG_ASIC_TX_ASIC_IN_2 2 0x1313 3 0 4294967295 TX_PRE_CURSOR 0 5 TX_POST_CURSOR 6 11 RESERVED_15_12 12 15 ixDPCSSYS_CR0_LANE3_DIG_ASIC_TX_ASIC_OUT 2 0x1314 3 0 4294967295 TX_ACK 0 0 DETRX_RESULT 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR0_LANE3_DIG_ASIC_RX_ASIC_OUT_0 2 0x131b 4 0 4294967295 ACK 0 0 VALID 1 1 ADAPT_STS 2 3 RESERVED_15_4 4 15 ixDPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_5 2 0x131d 15 0 4294967295 RPTR_EN_MASTER_LANE 0 0 RPTR_EN_MASTER_LANE_OVRD_EN 1 1 DIG_CLK_EN_OTHER_LANE 2 2 DIG_CLK_EN_OTHER_LANE_OVRD_EN 3 3 DIG_CLK_STATE_MASTER_LANE 4 4 DIG_CLK_STATE_MASTER_LANE_OVRD_EN 5 5 SHIFT_MASTER_LANE 6 6 SHIFT_MASTER_LANE_ORVD_EN 7 7 SHIFT_ACK_OTHER_LANE 8 8 SHIFT_ACK_OTHER_LANE_OVRD_EN 9 9 LANE_MASTER 10 10 LANE_MASTER_OVRD_IN_EN 11 11 TX_DWORD_CLK_SYNC_OVRD 12 12 TX_DWORD_CLK_SYNC_OVRD_EN 13 13 RESERVED_15_14 14 15 ixDPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_OUT_1 2 0x131e 11 0 4294967295 RPTR_EN_OUT 0 0 RPTR_EN_OUT_OVRD_EN 1 1 DIG_CLK_EN_OUT 2 2 DIG_CLK_EN_OUT_OVRD_EN 3 3 DIG_CLK_STATE_OUT 4 4 DIG_CLK_STATE_OUT_OVRD_EN 5 5 SHIFT_OUT 6 6 SHIFT_OUT_OVRD_EN 7 7 SHIFT_ACK_OUT 8 8 SHIFT_ACK_OUT_OVRD_EN 9 9 RESERVED_15_10 10 15 ixDPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0 2 0x1320 11 0 4294967295 TX_P0_ANA_REFGEN_EN 0 0 TX_P0_ANA_VCM_HOLD 1 1 TX_P0_ANA_CLK_EN 2 2 TX_P0_ANA_WORD_CLK_EN 3 3 TX_P0_ANA_RESET 4 4 TX_P0_ANA_SERIAL_EN 5 5 TX_P0_DIG_CLK_EN 6 6 TX_P0_DATA_EN 7 7 TX_P0_ALLOW_RXDET 8 8 TX_P0_ANA_DCC_COMP_CAL_EN 9 9 RESERVED_15_10 10 15 ixDPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S 2 0x1321 11 0 4294967295 TX_P0S_ANA_REFGEN_EN 0 0 TX_P0S_ANA_VCM_HOLD 1 1 TX_P0S_ANA_CLK_EN 2 2 TX_P0S_ANA_WORD_CLK_EN 3 3 TX_P0S_ANA_RESET 4 4 TX_P0S_ANA_SERIAL_EN 5 5 TX_P0S_DIG_CLK_EN 6 6 TX_P0S_DATA_EN 7 7 TX_P0S_ALLOW_RXDET 8 8 TX_P0S_ANA_DCC_COMP_CAL_EN 9 9 RESERVED_15_10 10 15 ixDPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1 2 0x1322 11 0 4294967295 TX_P1_ANA_REFGEN_EN 0 0 TX_P1_ANA_VCM_HOLD 1 1 TX_P1_ANA_CLK_EN 2 2 TX_P1_ANA_WORD_CLK_EN 3 3 TX_P1_ANA_RESET 4 4 TX_P1_ANA_SERIAL_EN 5 5 TX_P1_DIG_CLK_EN 6 6 TX_P1_DATA_EN 7 7 TX_P1_ALLOW_RXDET 8 8 TX_P1_ANA_DCC_COMP_CAL_EN 9 9 RESERVED_15_10 10 15 ixDPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2 2 0x1323 12 0 4294967295 TX_P2_ANA_REFGEN_EN 0 0 TX_P2_ANA_VCM_HOLD 1 1 TX_P2_ANA_CLK_EN 2 2 TX_P2_ANA_WORD_CLK_EN 3 3 TX_P2_ANA_RESET 4 4 TX_P2_ANA_SERIAL_EN 5 5 TX_P2_DIG_CLK_EN 6 6 TX_P2_DATA_EN 7 7 TX_P2_ALLOW_RXDET 8 8 TX_P2_ALLOW_VBOOST 9 9 TX_P2_ANA_DCC_COMP_CAL_EN 10 10 RESERVED_15_11 11 15 ixDPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_0 2 0x1324 2 0 4294967295 TX_REFGEN_EN_TIME 0 7 TX_CLK_EN 8 15 ixDPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_1 2 0x1325 2 0 4294967295 TX_VCM_HOLD_TIME_14_0 0 14 SKIP_TX_VCM_HOLD_WAIT 15 15 ixDPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_2 2 0x1326 2 0 4294967295 TX_VBOOST_DIS_TIME_12_0 0 12 DTB_SEL 13 15 ixDPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_3 2 0x1327 3 0 4294967295 TX_VCM_HOLD_TIME_17_15 0 2 TX_VBOOST_DIS_TIME_13 3 3 RESERVED_15_4 4 15 ixDPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_4 2 0x1328 2 0 4294967295 TX_VCM_HOLD_GS_TIME 0 14 SKIP_TX_VCM_HOLD_GS_PULSE 15 15 ixDPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_5 2 0x1329 5 0 4294967295 TX_RXDET_TIME 0 9 FAST_TX_RXDET 10 10 TX_RESET_TIME 11 12 TX_SERIAL_EN_TIME 13 14 RESERVED_15_15 15 15 ixDPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_DCC_CR_BANK_ADDR 2 0x132a 1 0 4294967295 ADDR 0 15 ixDPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_DCC_CR_BANK_DATA 2 0x132b 1 0 4294967295 DATA 0 15 ixDPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_DCC_DAC_CTRL 2 0x132c 2 0 4294967295 CTRL 0 7 RESERVED_15_8 8 15 ixDPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_DCC_DAC_RANGE 2 0x132d 2 0 4294967295 CTRL 0 1 RESERVED_15_2 2 15 ixDPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_DCC_DAC_SEL 2 0x132e 6 0 4294967295 SEL 0 2 REQ 3 3 CTRL_UPD 4 4 RANGE_UPD 5 5 BIN_HOT 6 6 RESERVED_15_7 7 15 ixDPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_DCC_DAC_ACK 2 0x132f 2 0 4294967295 ACK 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_DCC_DAC_ADDR 2 0x1330 1 0 4294967295 ADDR 0 15 ixDPCSSYS_CR0_LANE3_DIG_TX_CLK_ALIGN_TX_CTL_0 2 0x1331 4 0 4294967295 TX_NUM_2UI_SHIFTS_16B_MODE 0 3 TX_NUM_2UI_SHIFTS_20B_MODE 4 7 TX_FIFO_BYPASS 8 8 RESERVED_15_9 9 15 ixDPCSSYS_CR0_LANE3_DIG_TX_LBERT_CTL 2 0x1332 4 0 4294967295 MODE 0 3 TRIGGER_ERR 4 4 PAT0 5 14 RESERVED_15_15 15 15 ixDPCSSYS_CR0_LANE3_DIG_RX_STAT_LD_VAL_1 2 0x1380 2 0 4294967295 SC1_LD_VAL 0 14 SC1_START 15 15 ixDPCSSYS_CR0_LANE3_DIG_RX_STAT_DATA_MSK 2 0x1381 1 0 4294967295 DATA_MSK_15_0 0 15 ixDPCSSYS_CR0_LANE3_DIG_RX_STAT_MATCH_CTL0 2 0x1382 4 0 4294967295 PTTRN_MSK_CR1A_4_0 0 4 PTTRN_CR1A_4_0 5 9 DATA_MSK_19_16 10 13 SCOPE_DLY 14 15 ixDPCSSYS_CR0_LANE3_DIG_RX_STAT_MATCH_CTL1 2 0x1383 5 0 4294967295 PTTRN_CR1B_EN 0 0 PTTRN_MSK_CR1B_4_0 1 5 PTTRN_CR1B_4_0 6 10 PTTRN_CR1A_ADPT_EN 11 11 RESERVED_15_12 12 15 ixDPCSSYS_CR0_LANE3_DIG_RX_STAT_STAT_CTL0 2 0x1384 10 0 4294967295 RESERVED_0 0 0 CORR_SHFT_SEL_VGA 1 1 CORR_SHFT_SEL 2 2 CORR_SRC_SEL 3 4 CORR_MODE_EN 5 5 STAT_SHFT_SEL 6 9 STAT_SRC_SEL 10 12 STAT_RXCLK_SEL 13 13 SC_TIMER_MODE 14 14 SKIP_EN 15 15 ixDPCSSYS_CR0_LANE3_DIG_RX_STAT_STAT_CTL1 2 0x1385 13 0 4294967295 STAT_CNT_0_EN 0 0 STAT_CNT_1_EN 1 1 STAT_CNT_2_EN 2 2 STAT_CNT_3_EN 3 3 STAT_CNT_4_EN 4 4 STAT_CNT_5_EN 5 5 STAT_CNT_6_EN 6 6 RESERVED_8_7 7 8 SC_PAUSE 9 9 STAT_CLK_EN 10 10 DATA_DLY_SEL 11 12 VLD_LOSS_CLR 13 13 VLD_CTL 14 15 ixDPCSSYS_CR0_LANE3_DIG_RX_STAT_SMPL_CNT1 2 0x1386 2 0 4294967295 SMPL_CNT1 0 14 SMPL_CNT1_DONE 15 15 ixDPCSSYS_CR0_LANE3_DIG_RX_STAT_STAT_CNT_0 2 0x1387 2 0 4294967295 STAT_CNT_0 0 14 SMPL_CNT1_DONE 15 15 ixDPCSSYS_CR0_LANE3_DIG_RX_STAT_STAT_CNT_1 2 0x1388 2 0 4294967295 STAT_CNT_1 0 14 SMPL_CNT1_DONE 15 15 ixDPCSSYS_CR0_LANE3_DIG_RX_STAT_STAT_CNT_2 2 0x1389 2 0 4294967295 STAT_CNT_2 0 14 SMPL_CNT1_DONE 15 15 ixDPCSSYS_CR0_LANE3_DIG_RX_STAT_STAT_CNT_3 2 0x138a 2 0 4294967295 STAT_CNT_3 0 14 SMPL_CNT1_DONE 15 15 ixDPCSSYS_CR0_LANE3_DIG_RX_STAT_STAT_CNT_4 2 0x138b 2 0 4294967295 STAT_CNT_4 0 14 SMPL_CNT1_DONE 15 15 ixDPCSSYS_CR0_LANE3_DIG_RX_STAT_STAT_CNT_5 2 0x138c 2 0 4294967295 STAT_CNT_5 0 14 SMPL_CNT1_DONE 15 15 ixDPCSSYS_CR0_LANE3_DIG_RX_STAT_STAT_CNT_6 2 0x138d 2 0 4294967295 STAT_CNT_6 0 14 SMPL_CNT1_DONE 15 15 ixDPCSSYS_CR0_LANE3_DIG_RX_STAT_CAL_COMP_CLK_CTL 2 0x138e 3 0 4294967295 PRECHRGE_CNT 0 2 REF_DIV_CNT 3 5 RESERVED_15_6 6 15 ixDPCSSYS_CR0_LANE3_DIG_RX_STAT_MATCH_CTL2 2 0x138f 2 0 4294967295 PTTRN_CR1A_19_5 0 14 RESERVED_15_15 15 15 ixDPCSSYS_CR0_LANE3_DIG_RX_STAT_MATCH_CTL3 2 0x1390 2 0 4294967295 PTTRN_MSK_CR1A_19_5 0 14 RESERVED_15_15 15 15 ixDPCSSYS_CR0_LANE3_DIG_RX_STAT_MATCH_CTL4 2 0x1391 2 0 4294967295 PTTRN_CR1B_19_5 0 14 RESERVED_15_15 15 15 ixDPCSSYS_CR0_LANE3_DIG_RX_STAT_MATCH_CTL5 2 0x1392 2 0 4294967295 PTTRN_MSK_CR1B_19_5 0 14 RESERVED_15_15 15 15 ixDPCSSYS_CR0_LANE3_DIG_RX_STAT_STAT_CTL2 2 0x1393 4 0 4294967295 DATA_DLY_SEL_2 0 0 SCOPE_DLY_2 1 1 DISABLE_SAMPLE_COUNT 2 2 RESERVED_15_3 3 15 ixDPCSSYS_CR0_LANE3_DIG_RX_STAT_STAT_STOP 2 0x1394 2 0 4294967295 SC1_STOP 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR0_LANE3_DIG_ANA_TX_OVRD_OUT 2 0x13a0 15 0 4294967295 TX_ANA_CLK_SHIFT 0 0 TX_ANA_DATA_EN 1 1 TX_ANA_REFGEN_EN 2 2 TX_ANA_VCM_HOLD 3 3 TX_ANA_CLK_EN 4 4 TX_ANA_WORD_CLK_EN 5 5 TX_ANA_MPLLA_CLK_EN 6 6 TX_ANA_MPLLB_CLK_EN 7 7 TX_ANA_RESET 8 8 TX_ANA_SERIAL_EN 9 9 TX_ANA_DATA_RATE 10 11 RESERVED 12 12 TX_DIV4_EN 13 13 TX_RXDET_EN 14 14 TX_OVRD_EN 15 15 ixDPCSSYS_CR0_LANE3_DIG_ANA_TX_TERM_CODE_OVRD_OUT 2 0x13a1 5 0 4294967295 TX_TERM_CODE 0 9 TX_TERM_OVRD_EN 10 10 TX_DRV_SRC 11 12 TX_DRV_SRC_OVRD_EN 13 13 RESERVED_15_14 14 15 ixDPCSSYS_CR0_LANE3_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT 2 0x13a2 3 0 4294967295 TX_TERM_DN_CLK 0 0 TX_TERM_CLK_SELF_CLEAR_DISABLE 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR0_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_0 2 0x13a3 3 0 4294967295 TX_ANA_LOAD_CLK 0 0 TX_ANA_CTRL_LEG_PULL_EN_13_0 1 14 TX_EQ_OVRD_EN 15 15 ixDPCSSYS_CR0_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_1 2 0x13a4 2 0 4294967295 TX_ANA_CTRL_LEG_PULL_EN_19_14 0 5 RESERVED_15_6 6 15 ixDPCSSYS_CR0_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_2 2 0x13a5 4 0 4294967295 RESERVED 0 2 TX_ANA_CTRL_EQ_MUX_SEL 3 6 TX_ANA_CTRL_PRE 7 12 RESERVED_15_13 13 15 ixDPCSSYS_CR0_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_3 2 0x13a6 2 0 4294967295 TX_ANA_CTRL_POST 0 8 RESERVED_15_9 9 15 ixDPCSSYS_CR0_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_4 2 0x13a7 1 0 4294967295 TX_ANA_CTRL_LEG_PULL_DIR_19_4 0 15 ixDPCSSYS_CR0_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_5 2 0x13a8 2 0 4294967295 TX_ANA_CTRL_LEG_PULL_DIR_3_0 0 3 RESERVED_15_4 4 15 ixDPCSSYS_CR0_LANE3_DIG_ANA_STATUS_0 2 0x13bb 9 0 4294967295 TX_ANA_CLK_SHIFT_ACK 0 0 TX_ANA_RXDETP_RESULT 1 1 TX_ANA_RXDETM_RESULT 2 2 TX_ANA_LOOPBACK_EN 3 3 TX_ANA_CLK_LB_EN 4 4 RX_ANA_CAL_RESULT 5 5 RX_ANA_SCOPE_DATA 6 6 TX_ANA_DCC_CAL_RESULT 7 7 TX_ANA_CTRL_EQ_MUX 8 15 ixDPCSSYS_CR0_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT 2 0x13c2 8 0 4294967295 TX_ANA_DCC_CAL_RANGE 0 1 TX_ANA_DCC_CAL_RANGE_OVRD_EN 2 2 TX_ANA_DCC_CAL_COMP_EN 3 3 TX_ANA_DCC_CAL_COMP_EN_OVRD_EN 4 4 TX_ANA_DCC_CAL_CTRL 5 12 TX_ANA_DCC_CAL_CTRL_OVRD_EN 13 13 TX_ANA_DCC_CAL_CTRL_EN 14 14 TX_ANA_DCC_CAL_CTRL_EN_OVRD_EN 15 15 ixDPCSSYS_CR0_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2 2 0x13c3 5 0 4294967295 TX_ANA_DCC_CAL_CTRL_SEL 0 2 TX_ANA_DCC_CAL_CTRL_SEL_OVRD_EN 3 3 TX_ANA_DCC_CLK_COMP 4 4 TX_ANA_DCC_CLK_COMP_OVRD_EN 5 5 RESERVED_15_6 6 15 ixDPCSSYS_CR0_LANE3_DIG_ANA_TX_OVRD_OUT_2 2 0x13c4 6 0 4294967295 TX_ANA_FAST_START 0 0 TX_ANA_FAST_START_OVRD_EN 1 1 TX_CLK_LB_EN 2 2 TX_CLK_LB_EN_OVRD_EN 3 3 TX_ACJTAG_EN 4 4 RESERVED_15_5 5 15 ixDPCSSYS_CR0_LANE3_ANA_TX_OVRD_MEAS 2 0x13e0 9 0 4294967295 OVRD_CLK_SHIFT 0 0 CLK_SHIFT_REG 0 0 MEAS_ATB_CAL_MUX 0 0 MEAS_ATB_CAL_COMP 0 0 OVRD_VCM_HOLD 0 0 VCM_HOLD_REG 0 0 PULL_UP_REG 0 0 PULL_DN_REG 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR0_LANE3_ANA_TX_PWR_OVRD 2 0x13e1 9 0 4294967295 OVRD_TX_LOOPBACK 0 0 LOOPBACK_EN_REG 0 0 REFGEN_EN_REG 0 0 CLK_DIV_EN_REG 0 0 DATA_EN_REG_INT 0 0 CLK_EN_REG 0 0 SERIAL_EN_REG 0 0 OVRD_EN 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR0_LANE3_ANA_TX_ALT_BUS 2 0x13e2 6 0 4294967295 DRV_SOURCE_REG 0 0 OVRD_ALT_BUS 0 0 ATB_S_ENABLE 0 0 TX_ALT_RINGO 0 0 JTAG_DATA_REG 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR0_LANE3_ANA_TX_ATB1 2 0x13e3 9 0 4294967295 MEAS_ATB_GD 0 0 MEAS_ATB_VDDH 0 0 OVERRIDE_RXDETREF 0 0 MEAS_ATB_VPTX 0 0 OVERRIDE_REGREF 0 0 MEAS_ATB_VREG_DRV 0 0 MEAS_ATB_VREG 0 0 MEAS_ATB_VPH_HALF 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR0_LANE3_ANA_TX_ATB2 2 0x13e4 9 0 4294967295 MEAS_ATB_VCM 0 0 MEAS_ATB_CAL_VDAC_CM 0 0 MEAS_ATB_CAL_VDAC_DIFF 0 0 MEAS_ATB_TXM 0 0 MEAS_ATB_TXP 0 0 MEAS_ATB_RXDETREF 0 0 LFPS_HIGH_PRIORITY 0 0 OSC_DIV4_EN 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR0_LANE3_ANA_TX_DCC_DAC 2 0x13e5 2 0 4294967295 DCC_DAC_REG 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR0_LANE3_ANA_TX_DCC_CTRL1 2 0x13e6 7 0 4294967295 NC0 0 0 OVRD_DCC_DAC_CTRL_SEL 0 0 DCC_DAC_CTRL_SEL_REG 0 0 OVRD_DCC_DAC_CTRL_EN 0 0 DCC_DAC_CTRL_EN_REG 0 0 OVRD_DCC_DAC_REG 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR0_LANE3_ANA_TX_TERM_CODE 2 0x13e7 2 0 4294967295 TERM_CODE_REG_70 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR0_LANE3_ANA_TX_TERM_CODE_CTRL 2 0x13e8 8 0 4294967295 VREG_BOOST_1 0 0 OVRD_UPDATE_TERM 0 0 UPDATE_TERM_REG 0 0 OVRD_RESET_TERM 0 0 RESET_TERM_REG 0 0 OVRD_TERM_CODE 0 0 TERM_CODE_REG_98 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR0_LANE3_ANA_TX_OVRD_CLK 2 0x13e9 9 0 4294967295 VREG_BOOST_0 0 0 CLK_LB_EN_REG 0 0 OVRD_LB_EN 0 0 MPLLB_CLK_EN_REG 0 0 MPLLA_CLK_EN_REG 0 0 OVRD_MPLLAB_EN 0 0 WORD_CLK_EN_REG 0 0 OVRD_WORD_CLK_EN 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR0_LANE3_ANA_TX_MISC1 2 0x13ea 8 0 4294967295 MEAS_ATB_CAL_CLK_ALIGN 0 0 OVRD_DCC_DAC_CTRL_RANGE 0 0 DCC_DAC_CTRL_RANGE_REG 0 0 OVRD_VREF_SEL 0 0 VREF_SEL_REG 0 0 FORCE_ATB_TXM 0 0 FORCE_ATB_TXP 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR0_LANE3_ANA_TX_MISC2 2 0x13eb 8 0 4294967295 TX_PEAKING_LVL 0 0 VREG_CP_GAIN_CTRL 0 0 TX_SLEW_EN 0 0 EN_INV_POST 0 0 EN_INV_PRE 0 0 TX_VREG_EN_BYP 0 0 TX_VDRIVER_PULLDN_EN 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR0_LANE3_ANA_TX_MISC3 2 0x13ec 4 0 4294967295 TX_VREG_OVRD_RING_CTRL 0 0 TX_DCC_LOWV 0 0 NC7_2 2 7 RESERVED_15_8 8 15 ixDPCSSYS_CR0_LANE3_ANA_TX_RESERVED2 2 0x13ed 2 0 4294967295 NC7_0 0 7 RESERVED_15_8 8 15 ixDPCSSYS_CR0_LANE3_ANA_TX_RESERVED3 2 0x13ee 2 0 4294967295 NC7_0 0 7 RESERVED_15_8 8 15 ixDPCSSYS_CR0_LANE3_ANA_TX_RESERVED4 2 0x13ef 2 0 4294967295 NC7_0 0 7 RESERVED_15_8 8 15 ixDPCSSYS_CR0_RAWCMN_DIG_CMN_CTL 2 0x2000 2 0 4294967295 PHY_FUNC_RST 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR0_RAWCMN_DIG_MPLLA_OVRD_IN 2 0x2001 10 0 4294967295 MPLLA_WORD_DIV2_EN_OVRD_VAL 0 0 MPLLA_WORD_DIV2_EN_OVRD_EN 1 1 MPLLA_TX_CLK_DIV_OVRD_VAL 2 4 MPLLA_TX_CLK_DIV_OVRD_EN 5 5 MPLLA_DIV10_CLK_EN_OVRD_VAL 6 6 MPLLA_DIV10_CLK_EN_OVRD_EN 7 7 MPLLA_DIV8_CLK_EN_OVRD_VAL 8 8 MPLLA_DIV8_CLK_EN_OVRD_EN 9 9 MPLLA_BW_OVRD_EN 10 10 RESERVED_15_11 11 15 ixDPCSSYS_CR0_RAWCMN_DIG_MPLLA_BW_OVRD_IN 2 0x2002 1 0 4294967295 MPLLA_BW_OVRD_VAL 0 15 ixDPCSSYS_CR0_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_0 2 0x2003 7 0 4294967295 MPLLA_SSC_RANGE_OVRD_VAL 0 2 MPLLA_SSC_RANGE_OVRD_EN 3 3 MPLLA_SSC_CLK_SEL_OVRD_VAL 4 6 MPLLA_SSC_CLK_SEL_OVRD_EN 7 7 MPLLA_SSC_EN_OVRD_VAL 8 8 MPLLA_SSC_EN_OVRD_EN 9 9 RESERVED_15_10 10 15 ixDPCSSYS_CR0_RAWCMN_DIG_MPLLB_OVRD_IN 2 0x2004 10 0 4294967295 MPLLB_WORD_DIV2_EN_OVRD_VAL 0 0 MPLLB_WORD_DIV2_EN_OVRD_EN 1 1 MPLLB_TX_CLK_DIV_OVRD_VAL 2 4 MPLLB_TX_CLK_DIV_OVRD_EN 5 5 MPLLB_DIV10_CLK_EN_OVRD_VAL 6 6 MPLLB_DIV10_CLK_EN_OVRD_EN 7 7 MPLLB_DIV8_CLK_EN_OVRD_VAL 8 8 MPLLB_DIV8_CLK_EN_OVRD_EN 9 9 MPLLB_BW_OVRD_EN 10 10 RESERVED_15_11 11 15 ixDPCSSYS_CR0_RAWCMN_DIG_MPLLB_BW_OVRD_IN 2 0x2005 1 0 4294967295 MPLLB_BW_OVRD_VAL 0 15 ixDPCSSYS_CR0_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_0 2 0x2006 7 0 4294967295 MPLLB_SSC_RANGE_OVRD_VAL 0 2 MPLLB_SSC_RANGE_OVRD_EN 3 3 MPLLB_SSC_CLK_SEL_OVRD_VAL 4 6 MPLLB_SSC_CLK_SEL_OVRD_EN 7 7 MPLLB_SSC_EN_OVRD_VAL 8 8 MPLLB_SSC_EN_OVRD_EN 9 9 RESERVED_15_10 10 15 ixDPCSSYS_CR0_RAWCMN_DIG_LANE_FSM_OP_XTND 2 0x2007 2 0 4294967295 DATA 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR0_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_1 2 0x2008 3 0 4294967295 MPLLA_FRACN_CTRL_OVRD_VAL 0 10 MPLLA_FRACN_CTRL_OVRD_EN 11 11 RESERVED_15_12 12 15 ixDPCSSYS_CR0_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_1 2 0x2009 3 0 4294967295 MPLLB_FRACN_CTRL_OVRD_VAL 0 10 MPLLB_FRACN_CTRL_OVRD_EN 11 11 RESERVED_15_12 12 15 ixDPCSSYS_CR0_RAWCMN_DIG_CMN_CTL_1 2 0x200a 13 0 4294967295 MPLLA_INIT_CAL_DISABLE_OVRD_VAL 0 0 MPLLA_INIT_CAL_DISABLE_OVRD_EN 1 1 MPLLB_INIT_CAL_DISABLE_OVRD_VAL 2 2 MPLLB_INIT_CAL_DISABLE_OVRD_EN 3 3 RTUNE_REQ_OVRD_VAL 4 4 RTUNE_REQ_OVRD_EN 5 5 HDMIMODE_ENABLE_OVRD_VAL 6 6 HDMIMODE_ENABLE_OVRD_EN 7 7 TX_PWM_CLK_SEL_OVRD_VAL 8 9 TX_PWM_CLK_SEL_OVRD_EN 10 10 TX_PWM_CLK_EN_OVRD_VAL 11 11 TX_PWM_CLK_EN_OVRD_EN 12 12 RESERVED_15_13 13 15 ixDPCSSYS_CR0_RAWCMN_DIG_MPLL_STATE_CTL 2 0x200b 8 0 4294967295 MPLL_OFF_TIME 0 5 MPLLA_STATE 6 6 MPLLB_STATE 7 7 MPLL_STATE_OVRD_OUT_EN 8 8 MPLL_FORCE_ON_TIME 9 12 MPLLB_BANK_SEL 13 13 MPLLA_BANK_SEL 14 14 RESERVED_15_15 15 15 ixDPCSSYS_CR0_RAWCMN_DIG_TX_CAL_CODE 2 0x200c 2 0 4294967295 DATA 0 0 RESERVED_15_4 4 15 ixDPCSSYS_CR0_RAWCMN_DIG_SRAM_INIT_DONE 2 0x200d 2 0 4294967295 DATA 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR0_RAWCMN_DIG_OCLA 2 0x200e 3 0 4294967295 DIV2_CLK_EN 0 0 TCA_OCLA_PROBE_SEL 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR0_RAWCMN_DIG_SUP_ANA_OVRD 2 0x200f 7 0 4294967295 REF_ALT_CLK_LP_SEL_OVRD_EN 0 0 REF_ALT_CLK_LP_SEL_OVRD_VAL 1 1 SUP_PRE_HP_OVRD_EN 2 2 SUP_PRE_HP_OVRD_VAL 3 3 SUP_RX_VCO_VREF_SEL_OVRD_EN 4 4 SUP_RX_VCO_VREF_SEL_OVRD_VAL 5 7 RESERVED_15_8 8 15 ixDPCSSYS_CR0_RAWCMN_DIG_PCS_RAW_ID_CODE 2 0x2010 1 0 4294967295 DATA 0 0 ixDPCSSYS_CR0_RAWCMN_DIG_FW_ID_CODE_1 2 0x2011 1 0 4294967295 W_ID_CODE_1 0 15 ixDPCSSYS_CR0_RAWCMN_DIG_FW_ID_CODE_2 2 0x2012 1 0 4294967295 W_ID_CODE_2 0 15 ixDPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_0 2 0x2020 2 0 4294967295 RTUNE_RX_VAL_0 0 5 RESERVED_15_6 6 15 ixDPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_0 2 0x2021 2 0 4294967295 RTUNE_TXDN_VAL_0 0 9 RESERVED_15_10 10 15 ixDPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_0 2 0x2022 2 0 4294967295 RTUNE_TXUP_VAL_0 0 9 RESERVED_15_10 10 15 ixDPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_1 2 0x2023 2 0 4294967295 RTUNE_RX_VAL_1 0 5 RESERVED_15_6 6 15 ixDPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_1 2 0x2024 2 0 4294967295 RTUNE_TXDN_VAL_1 0 9 RESERVED_15_10 10 15 ixDPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_1 2 0x2025 2 0 4294967295 RTUNE_TXUP_VAL_1 0 9 RESERVED_15_10 10 15 ixDPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_2 2 0x2026 2 0 4294967295 RTUNE_RX_VAL_2 0 5 RESERVED_15_6 6 15 ixDPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_2 2 0x2027 2 0 4294967295 RTUNE_TXDN_VAL_2 0 9 RESERVED_15_10 10 15 ixDPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_2 2 0x2028 2 0 4294967295 RTUNE_TXUP_VAL_2 0 9 RESERVED_15_10 10 15 ixDPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_3 2 0x2029 2 0 4294967295 RTUNE_RX_VAL_3 0 5 RESERVED_15_6 6 15 ixDPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_3 2 0x202a 2 0 4294967295 RTUNE_TXDN_VAL_3 0 9 RESERVED_15_10 10 15 ixDPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_3 2 0x202b 2 0 4294967295 RTUNE_TXUP_VAL_3 0 9 RESERVED_15_10 10 15 ixDPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_4 2 0x202c 2 0 4294967295 RTUNE_RX_VAL_4 0 5 RESERVED_15_6 6 15 ixDPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_4 2 0x202d 2 0 4294967295 RTUNE_TXDN_VAL_4 0 9 RESERVED_15_10 10 15 ixDPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_4 2 0x202e 2 0 4294967295 RTUNE_TXUP_VAL_4 0 9 RESERVED_15_10 10 15 ixDPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_5 2 0x202f 2 0 4294967295 RTUNE_RX_VAL_5 0 5 RESERVED_15_6 6 15 ixDPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_5 2 0x2030 2 0 4294967295 RTUNE_TXDN_VAL_5 0 9 RESERVED_15_10 10 15 ixDPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_5 2 0x2031 2 0 4294967295 RTUNE_TXUP_VAL_5 0 9 RESERVED_15_10 10 15 ixDPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_6 2 0x2032 2 0 4294967295 RTUNE_RX_VAL_6 0 5 RESERVED_15_6 6 15 ixDPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_6 2 0x2033 2 0 4294967295 RTUNE_TXDN_VAL_6 0 9 RESERVED_15_10 10 15 ixDPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_6 2 0x2034 2 0 4294967295 RTUNE_TXUP_VAL_6 0 9 RESERVED_15_10 10 15 ixDPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_7 2 0x2035 2 0 4294967295 RTUNE_RX_VAL_7 0 5 RESERVED_15_6 6 15 ixDPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_7 2 0x2036 2 0 4294967295 RTUNE_TXDN_VAL_7 0 9 RESERVED_15_10 10 15 ixDPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_7 2 0x2037 2 0 4294967295 RTUNE_TXUP_VAL_7 0 9 RESERVED_15_10 10 15 ixDPCSSYS_CR0_RAWCMN_DIG_AON_CMN_SRAM_BL_CFG 2 0x2038 5 0 4294967295 SRAM_PGATE_BL_EN 0 0 SRAM_BL_ROM 1 1 SRAM_BL_BYPASS 2 2 SRAM_BL_START 3 3 RESERVED_15_4 4 15 ixDPCSSYS_CR0_RAWCMN_DIG_AON_CMN_PG_OVRD_IN 2 0x2039 7 0 4294967295 PMA_PWR_STABLE_OVRD 0 0 PCS_PWR_STABLE_OVRD 1 1 PG_RESET_OVRD_VAL 2 2 PG_RESET_OVRD_EN 3 3 PG_MODE_EN_OVRD_VAL 4 4 PG_MODE_EN_OVRD_EN 5 5 RESERVED_15_6 6 15 ixDPCSSYS_CR0_RAWCMN_DIG_AON_CMN_PG_OVRD_OUT 2 0x203a 8 0 4294967295 PMA_PWR_EN_OVRD 0 0 PCS_PWR_EN_OVRD 1 1 MON_IN_VALID_OVRD_VAL 2 2 MON_IN_VALID_OVRD_EN 3 3 MON_IN_PULL_DOWN 4 4 ANA_ISOLATION_EN_OVRD_EN 5 5 ANA_ISOLATION_EN_OVRD_VAL 6 6 RESERVED_15_7 7 15 ixDPCSSYS_CR0_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN 2 0x203b 11 0 4294967295 MPLLA_FORCE_EN_OVRD_VAL 0 0 MPLLA_FORCE_EN_OVRD_EN 1 1 MPLLB_FORCE_EN_OVRD_VAL 2 2 MPLLB_FORCE_EN_OVRD_EN 3 3 REF_CLK_EN_OVRD_VAL 4 4 REF_CLK_EN_OVRD_EN 5 5 MPLLA_FORCE_ACK_OVRD_VAL 6 6 MPLLA_FORCE_ACK_OVRD_EN 7 7 MPLLB_FORCE_ACK_OVRD_VAL 8 8 MPLLB_FORCE_ACK_OVRD_EN 9 9 RESERVED_15_10 10 15 ixDPCSSYS_CR0_RAWCMN_DIG_AON_CMN_VREF_STATS 2 0x203c 3 0 4294967295 SUP_ANA_VPHUD_SELVPH 0 0 VREF_CAL_DONE 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RES_OVRD_IN 2 0x203d 8 0 4294967295 RES_REQ_IN 0 0 RES_ACK_IN 1 1 RES_OVRD_EN 2 2 RES_REQ_OUT 3 3 RES_REQ_OUT_OVRD_EN 4 4 RES_ACK_OUT 5 5 RES_ACK_OUT_OVRD_EN 6 6 RESERVED_15_7 7 15 ixDPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RES_ASIC_IN_OUT 2 0x203e 5 0 4294967295 RES_REQ_IN 0 0 RES_REQ_OUT 1 1 RES_ACK_IN 2 2 RES_ACK_OUT 3 3 RESERVED_15_4 4 15 ixDPCSSYS_CR0_RAWCMN_DIG_AON_CMN_REF_RANGE_OVRD 2 0x203f 3 0 4294967295 OVRD_VAL 0 4 OVRD_EN 5 5 RESERVED_15_6 6 15 ixDPCSSYS_CR0_RAWCMN_DIG_AON_CMN_MISC_CONF_IN_1 2 0x2040 2 0 4294967295 MPLL_PWRDN_TIME 0 9 RESERVED_15_10 10 15 ixDPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN 2 0x3000 12 0 4294967295 PSTATE 0 1 LPD 2 2 WIDTH 3 4 RATE 5 7 MPLLB_SEL 8 8 MPLL_EN 9 9 OVRD_EN 10 10 MSTR_MPLLA_STATE 11 11 MSTR_MPLLB_STATE 12 12 MSTR_MPLL_OVRD_EN 13 13 TX_ASYNC_EN_OVR_VAL 14 14 TX_ASYNC_EN_OVR_EN 15 15 ixDPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1 2 0x3001 13 0 4294967295 RESET_OVRD_VAL 0 0 RESET_OVRD_EN 1 1 REQ_OVRD_VAL 2 2 REQ_OVRD_EN 3 3 DETRX_REQ_OVRD_VAL 4 4 DETRX_REQ_OVRD_EN 5 5 VBOOST_EN_OVRD_VAL 6 6 VBOOST_EN_OVRD_EN 7 7 IBOOST_LVL_OVRD_VAL 8 11 IBOOST_LVL_OVRD_EN 12 12 TX_BEACON_EN_OVR_VAL 13 13 TX_BEACON_EN_OVR_EN 14 14 RESERVED_15_15 15 15 ixDPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_PCS_IN 2 0x3002 12 0 4294967295 RESET 0 0 REQ 1 1 PSTATE 2 3 LPD 4 4 WIDTH 5 6 RATE 7 9 MPLLB_SEL 10 10 MPLL_EN 11 11 MSTR_MPLLA_STATE 12 12 MSTR_MPLLB_STATE 13 13 DETRX_REQ 14 14 RESERVED_15_15 15 15 ixDPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_OVRD_OUT 2 0x3003 6 0 4294967295 ACK 0 0 DETRX_RESULT 1 1 EN_CTL 2 2 TX_DWORD_CLK_SYNC_OVRD_VAL 3 3 TX_DWORD_CLK_SYNC_OVRD_EN 4 4 RESERVED_15_5 5 15 ixDPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_PCS_OUT 2 0x3004 2 0 4294967295 ACK 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN 2 0x3005 12 0 4294967295 RATE 0 1 WIDTH 2 3 PSTATE 4 5 LPD 6 6 OVRD_EN 7 7 ADAPT_AFE_EN 8 8 ADAPT_DFE_EN 9 9 LANE_RX2TX_PAR_LB_EN_OVRD_VAL 10 10 LANE_RX2TX_PAR_LB_EN_OVRD_EN 11 11 RX_DATA_EN_OVRD_VAL_R 12 12 RX_DATA_EN_OVRD_EN_R 13 13 RESERVED_15_14 14 15 ixDPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1 2 0x3006 12 0 4294967295 RESET_OVRD_VAL 0 0 RESET_OVRD_EN 1 1 REQ_OVRD_VAL 2 2 REQ_OVRD_EN 3 3 RX_LOS_THRSHLD_OVRD_VAL 4 6 RX_LOS_THRSHLD_OVRD_EN 7 7 ADAPT_REQ 8 8 ADAPT_REQ_OVRD_EN 9 9 ADAPT_CONT 10 10 OFFCAN_CONT 11 11 CONT_OVRD_EN 12 12 RESERVED_15_13 13 15 ixDPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_2 2 0x3007 4 0 4294967295 VCO_LD_VAL_OVRD 0 12 VCO_LD_VAL_OVRD_EN 13 13 VCO_LOWFREQ_VAL_OVRD 14 14 VCO_LOWFREQ_VAL_OVRD_EN 15 15 ixDPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_3 2 0x3008 3 0 4294967295 REF_LD_VAL_OVRD 0 6 REF_LD_VAL_OVRD_EN 7 7 RESERVED_15_8 8 15 ixDPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_PCS_IN 2 0x3009 13 0 4294967295 REQ 0 0 RATE 1 2 WIDTH 3 4 PSTATE 5 6 LPD 7 7 CDR_VCO_LOWFREQ 8 8 ADAPT_AFE_EN 9 9 ADAPT_DFE_EN 10 10 ADAPT_REQ 11 11 ADAPT_CONT 12 12 OFFCAN_CONT 13 13 RESET 14 14 RESERVED_15_15 15 15 ixDPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_1 2 0x300a 2 0 4294967295 REF_LD_VAL 0 6 RESERVED_15_7 7 15 ixDPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_2 2 0x300b 2 0 4294967295 VCO_LD_VAL 0 12 RESERVED_15_13 13 15 ixDPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_3 2 0x300c 4 0 4294967295 EQ_ATT_LVL 0 2 EQ_VGA1_GAIN 3 6 EQ_VGA2_GAIN 7 10 EQ_CTLE_BOOST 11 15 ixDPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_4 2 0x300d 3 0 4294967295 EQ_CTLE_POLE 0 2 EQ_DFE_TAP1 3 10 RESERVED_15_11 11 15 ixDPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT 2 0x300e 3 0 4294967295 ACK 0 0 EN_CTL 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_PCS_OUT 2 0x300f 2 0 4294967295 ACK 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_ADAPT_ACK 2 0x3010 2 0 4294967295 RX_ADAPT_ACK 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_ADAPT_FOM 2 0x3011 2 0 4294967295 RX_ADAPT_FOM 0 7 RESERVED_15_8 8 15 ixDPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_TXPRE_DIR 2 0x3012 2 0 4294967295 RX_TXPRE_DIR 0 1 RESERVED_15_2 2 15 ixDPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_TXMAIN_DIR 2 0x3013 2 0 4294967295 RX_TXMAIN_DIR 0 1 RESERVED_15_2 2 15 ixDPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_TXPOST_DIR 2 0x3014 2 0 4294967295 RX_TXPOST_DIR 0 1 RESERVED_15_2 2 15 ixDPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_LANE_NUMBER 2 0x3015 2 0 4294967295 LANE_NUMBER 0 3 RESERVED_15_4 4 15 ixDPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RESERVED_1 2 0x3016 1 0 4294967295 RESERVED_REG_1 0 15 ixDPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RESERVED_2 2 0x3017 1 0 4294967295 RESERVED_REG_2 0 15 ixDPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN 2 0x3018 16 0 4294967295 RX_RESET_ATE_OVRD_VAL 0 0 RX_RESET_ATE_OVRD_EN 1 1 TX_RESET_ATE_OVRD_VAL 2 2 TX_RESET_ATE_OVRD_EN 3 3 RX_REQ_ATE_OVRD_VAL 4 4 RX_REQ_ATE_OVRD_EN 5 5 TX_REQ_ATE_OVRD_VAL 6 6 TX_REQ_ATE_OVRD_EN 7 7 RX_ADAPT_AFE_EN_OVRD_VAL 8 8 RX_ADAPT_AFE_EN_OVRD_EN 9 9 RX_ADAPT_DFE_EN_OVRD_VAL 10 10 RX_ADAPT_DFE_EN_OVRD_EN 11 11 TX_DATA_EN_ATE_OVRD_VAL 12 12 TX_DATA_EN_ATE_OVRD_EN 13 13 RX_DATA_EN_ATE_OVRD_VAL 14 14 RX_DATA_EN_ATE_OVRD_EN 15 15 ixDPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN 2 0x3019 3 0 4294967295 RX_EQ_DELTA_IQ_OVRD_VAL 0 3 RX_EQ_DELTA_IQ_OVRD_EN 4 4 RESERVED_15_5 5 15 ixDPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN 2 0x301a 5 0 4294967295 RX_TERM_CTRL_OVRD_VAL 0 2 RX_TERM_CTRL_OVRD_EN 3 3 TX_TERM_CTRL_OVRD_VAL 4 6 TX_TERM_CTRL_OVRD_EN 7 7 RESERVED_15_8 8 15 ixDPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TXRX_TERM_CTRL_IN 2 0x301b 3 0 4294967295 RX_TERM_CTRL 0 2 TX_TERM_CTRL 3 5 RESERVED_15_6 6 15 ixDPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT_1 2 0x301c 2 0 4294967295 RX_CLK_EN 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_EQ_OVRD_IN_1 2 0x301d 4 0 4294967295 RX_EQ_AFE_GAIN_OVRD_VAL 0 3 RX_EQ_ATT_LVL_OVRD_VAL 4 6 RX_EQ_OVRD_EN 7 7 RESERVED_15_8 8 15 ixDPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_EQ_OVRD_IN_2 2 0x301e 3 0 4294967295 RX_EQ_DFE_TAP1_OVRD_VAL 0 7 RX_EQ_CTLE_BOOST_OVRD_VAL 8 12 RESERVED_15_13 13 15 ixDPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_PH2_CAL 2 0x301f 4 0 4294967295 PH2_CAL_ACK_VAL 0 0 PH2_CAL_REQ_VAL 1 1 PH2_CAL_REQ_OVRD_VAL 2 2 RESERVED_15_3 3 15 ixDPCSSYS_CR0_RAWLANE0_DIG_FSM_FSM_OVRD_CTL 2 0x3020 5 0 4294967295 FSM_JMP_ADDR 0 11 FSM_JMP_EN 12 12 FSM_CMD_START 13 13 FSM_OVRD_EN 14 14 FSM_BREAK 15 15 ixDPCSSYS_CR0_RAWLANE0_DIG_FSM_MEM_ADDR_MON 2 0x3021 1 0 4294967295 MEM_ADDR 0 15 ixDPCSSYS_CR0_RAWLANE0_DIG_FSM_STATUS_MON 2 0x3022 8 0 4294967295 STATE 0 4 CMD_RDY 5 5 ALU_OVFLW 6 6 ALU_RES_EQ0 7 7 WAIT_CNT_EQ0 8 8 WRMSK_DISABLED 9 9 RDMSK_DISABLED 10 10 RESERVED_15_11 11 15 ixDPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_RX_STARTUP_CAL 2 0x3023 2 0 4294967295 FAST_RX_STARTUP_CAL 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_RX_ADAPT 2 0x3024 2 0 4294967295 FAST_RX_ADAPT 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_RX_AFE_CAL 2 0x3025 2 0 4294967295 FAST_RX_AFE_CAL 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_RX_DFE_CAL 2 0x3026 2 0 4294967295 FAST_RX_DFE_CAL 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_RX_BYPASS_CAL 2 0x3027 2 0 4294967295 FAST_RX_BYPASS_CAL 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_RX_REFLVL_CAL 2 0x3028 2 0 4294967295 FAST_RX_REFLVL_CAL 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_RX_IQ_CAL 2 0x3029 2 0 4294967295 FAST_RX_IQ_CAL 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_RX_AFE_ADAPT 2 0x302a 2 0 4294967295 FAST_RX_AFE_ADAPT 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_RX_DFE_ADAPT 2 0x302b 2 0 4294967295 FAST_RX_DFE_ADAPT 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_SUP 2 0x302c 2 0 4294967295 FAST_SUP 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_TX_CMN_MODE 2 0x302d 2 0 4294967295 FAST_TX_CMN_MODE 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_TX_RXDET 2 0x302e 2 0 4294967295 FAST_TX_RXDET 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_RX_PWRUP 2 0x302f 2 0 4294967295 FAST_RX_PWRUP 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_RX_VCO_WAIT 2 0x3030 2 0 4294967295 FAST_RX_VCO_WAIT 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_RX_VCO_CAL 2 0x3031 2 0 4294967295 FAST_RX_VCO_CAL 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR0_RAWLANE0_DIG_FSM_CMNCAL_MPLL_STATUS 2 0x3032 3 0 4294967295 CMNCAL_MPLL_INIT 0 0 CMNCAL_MPLL_DONE 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_RX_CONT_CAL_ADAPT 2 0x3033 2 0 4294967295 FAST_RX_CONT_CAL_ADAPT 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_RX_CONT_ADAPT 2 0x3034 2 0 4294967295 FAST_RX_CONT_ADAPT 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_RX_CONT_DATA_CAL 2 0x3035 2 0 4294967295 FAST_RX_CONT_DATA_CAL 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_RX_CONT_PHASE_CAL 2 0x3036 2 0 4294967295 FAST_RX_CONT_PHASE_CAL 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_RX_CONT_AFE_CAL 2 0x3037 2 0 4294967295 FAST_RX_CONT_AFE_CAL 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_FLAGS 2 0x3038 12 0 4294967295 TX_FAST_DCC_CAL 0 0 RX_FAST_DCC_CAL 1 1 RX_FAST_VPHUD_CAL 2 2 RX_FAST_VREF_CAL 3 3 RX_FAST_SIGDET_CAL 4 4 RESERVED_2 5 7 TX_FAST_CONT_DCC_CAL 8 8 RX_FAST_CONT_DCC_CAL 9 9 RX_FAST_CONT_VPHUD_CAL 10 10 RX_FAST_CONT_VREF_CAL 11 11 RESERVED_1 12 14 TX_SKIP_SUP_CAL 15 15 ixDPCSSYS_CR0_RAWLANE0_DIG_FSM_CR_LOCK 2 0x3039 3 0 4294967295 CR_REG_LOCK 0 0 CR_MEM_LOCK 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR0_RAWLANE0_DIG_FSM_TX_DCC_FLAGS 2 0x303a 4 0 4294967295 RATE 0 0 DIV 1 1 MPLL 2 2 RESERVED_15_3 3 15 ixDPCSSYS_CR0_RAWLANE0_DIG_FSM_TX_DCC_STATUS 2 0x303b 2 0 4294967295 FLAG 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR0_RAWLANE0_DIG_FSM_OCLA 2 0x303c 4 0 4294967295 PC_EN 0 0 REG_BANK1_EN 1 1 REG_BANK2_EN 2 2 RESERVED_15_3 3 15 ixDPCSSYS_CR0_RAWLANE0_DIG_FSM_TX_EQ_UPDATE_FLAG 2 0x303d 2 0 4294967295 TX_EQ_UPDATE_FLAG 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR0_RAWLANE0_DIG_FSM_CMNCAL_RCAL_STATUS 2 0x303e 3 0 4294967295 CMNCAL_RCAL_INIT 0 0 CMNCAL_RCAL_DONE 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR0_RAWLANE0_DIG_FSM_RX_IQ_PHASE_OFFSET 2 0x303f 2 0 4294967295 RX_IQ_PHASE_OFFSET 0 3 RESERVED_15_4 4 15 ixDPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_RESET_RTN_REQ 2 0x3040 2 0 4294967295 RESET_RTN_REQ 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_RX_RESET_IRQ 2 0x3041 2 0 4294967295 RX_RESET 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_RX_REQ_IRQ 2 0x3042 2 0 4294967295 RX_REQ 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_RX_RATE_IRQ 2 0x3043 2 0 4294967295 RX_RATE_IRQ 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_RX_PSTATE_IRQ 2 0x3044 2 0 4294967295 RX_PSTATE_IRQ 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ 2 0x3045 2 0 4294967295 RX_ADAPT_REQ_IRQ 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ 2 0x3046 2 0 4294967295 RX_ADAPT_DIS_IRQ 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_RX_RESET_IRQ_CLR 2 0x3047 2 0 4294967295 RX_RESET_IRQ_CLR 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_RX_REQ_IRQ_CLR 2 0x3048 2 0 4294967295 RX_REQ_IRQ_CLR 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_RX_RATE_IRQ_CLR 2 0x3049 2 0 4294967295 RX_RATE_IRQ_CLR 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR 2 0x304a 2 0 4294967295 RX_PSTATE_IRQ_CLR 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR 2 0x304b 2 0 4294967295 RX_ADAPT_REQ_IRQ_CLR 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR 2 0x304c 2 0 4294967295 RX_ADAPT_DIS_IRQ_CLR 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK 2 0x304d 12 0 4294967295 RX_REQ_IRQ_MSK 0 0 RX_RATE_IRQ_MSK 1 1 RX_PSTATE_IRQ_MSK 2 2 RX_ADAPT_REQ_IRQ_MSK 3 3 RX_ADAPT_DIS_IRQ_MSK 4 4 RX_RESET_IRQ_MSK 5 5 LANE_XCVR_MODE_IRQ_MSK 6 6 RX_PH2_CAL_REQ_IRQ_MSK 7 7 RX_PH2_CAL_DIS_IRQ_MSK 8 8 LANE_RX2TX_SER_LB_EN_IRQ_MSK 9 9 DCC_ONDMD_IRQ_MSK 10 10 RESERVED_15_11 11 15 ixDPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK_2 2 0x304e 3 0 4294967295 TX_RESET_IRQ_MSK 0 0 TX_REQ_IRQ_MSK 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ 2 0x304f 2 0 4294967295 LANE_XCVR_MODE_IRQ 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR 2 0x3050 2 0 4294967295 LANE_XCVR_MODE_IRQ_CLR 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ 2 0x3051 2 0 4294967295 RX_PH2_CAL_REQ_IRQ 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ 2 0x3052 2 0 4294967295 RX_PH2_CAL_DIS_IRQ 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR 2 0x3053 2 0 4294967295 RX_PH2_CAL_REQ_IRQ_CLR 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR 2 0x3054 2 0 4294967295 RX_PH2_CAL_DIS_IRQ_CLR 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ 2 0x3055 2 0 4294967295 LANE_RX2TX_SER_LB_EN_IRQ 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR 2 0x3056 2 0 4294967295 LANE_RX2TX_SER_LB_EN_IRQ_CLR 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_DCC_ONDMD_IRQ 2 0x3057 2 0 4294967295 IRQ 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_TX_RESET_IRQ 2 0x3058 2 0 4294967295 TX_RESET 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_TX_REQ_IRQ 2 0x3059 2 0 4294967295 TX_REQ 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_TX_RESET_IRQ_CLR 2 0x305a 2 0 4294967295 TX_RESET_IRQ_CLR 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_TX_REQ_IRQ_CLR 2 0x305b 2 0 4294967295 TX_REQ_IRQ_CLR 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_LANE_OVRD_IN 2 0x3060 4 0 4294967295 LANE_MPLLA_EN_IN 0 0 LANE_MPLLB_EN_IN 1 1 LANE_OVRD_EN 2 2 RESERVED_15_3 3 15 ixDPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_LANE_OVRD_OUT 2 0x3061 4 0 4294967295 LANE_MPLLA_EN_OUT 0 0 LANE_MPLLB_EN_OUT 1 1 LANE_OVRD_EN 2 2 RESERVED_15_3 3 15 ixDPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_SUP_OVRD_IN 2 0x3062 4 0 4294967295 MPLLA_STATE 0 0 MPLLB_STATE 1 1 SUP_STATE_OVRD_EN 2 2 RESERVED_15_3 3 15 ixDPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_SUP_PMA_IN 2 0x3063 3 0 4294967295 MPLLA_STATE 0 0 MPLLB_STATE 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT 2 0x3064 16 0 4294967295 TX_REQ_OVRD_VAL 0 0 TX_REQ_OVRD_EN 1 1 TX_RESET_OVRD_VAL 2 2 TX_RESET_OVRD_EN 3 3 TX_BEACON_EN_OVRD_VAL 4 4 TX_BEACON_EN_OVRD_EN 5 5 TX_ASYNC_DRV_EN_OVRD_VAL 6 6 TX_ASYNC_DRV_EN_OVRD_EN 7 7 TX_ASYNC_EN_OVRD_VAL 8 8 TX_ASYNC_EN_OVRD_EN 9 9 TX_DWORD_CLK_SYNC_OVRD_VAL 10 10 TX_DWORD_CLK_SYNC_OVRD_EN 11 11 LANE_TX2RX_SER_LB_EN_OVRD_VAL 12 12 LANE_TX2RX_SER_LB_EN_OVRD_EN 13 13 TX_PMA_DATA_EN_OVRD_VAL_R 14 14 TX_PMA_DATA_EN_OVRD_EN_R 15 15 ixDPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_TX_PMA_IN 2 0x3065 2 0 4294967295 ACK 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT 2 0x3066 9 0 4294967295 RX_REQ_OVRD_VAL 0 0 RX_REQ_OVRD_EN 1 1 RX_RESET_OVRD_VAL 2 2 RX_RESET_OVRD_EN 3 3 LANE_RX2TX_PAR_LB_EN_OVRD_VAL 4 4 LANE_RX2TX_PAR_LB_EN_OVRD_EN 5 5 RX_PMA_DATA_EN_OVRD_VAL_R 6 6 RX_PMA_DATA_EN_OVRD_EN_R 7 7 RESERVED_15_8 8 15 ixDPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_RX_PMA_IN 2 0x3067 2 0 4294967295 ACK 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_LANE_RTUNE_CTL 2 0x3068 2 0 4294967295 LANE_RTUNE_REQ 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_SUP_PMA_IN_1 2 0x3069 2 0 4294967295 RTUNE_ACK 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_IN 2 0x306a 9 0 4294967295 RX_PMA_PWM_WORD_CLK_R 0 0 RX_PMA_PWM_WORD_CLK_OVRD_EN 1 1 RX_PMA_PWM_DATA_R 2 2 RX_PMA_PWM_DATA_OVRD_EN 3 3 RX_PMA_PWM_CLK_R 4 4 RX_PMA_PWM_CLK_OVRD_EN 5 5 RX_PMA_TERM_CTL_R 6 7 RX_PMA_TERM_CTL_OVRD_EN 8 8 RESERVED_15_9 9 15 ixDPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_OUT 2 0x306b 7 0 4294967295 RX_PMA_PWM_EN 0 0 RX_PMA_PWM_EN_OVRD_EN 1 1 RX_PMA_PWM_CLK_SEL 2 3 RX_PMA_PWM_CLK_SEL_OVRD_EN 4 4 RX_PMA_ASYNC_EN 5 5 RX_PMA_ASYNC_EN_OVRD_EN 6 6 RESERVED_15_7 7 15 ixDPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_RX_ADAPT_OVRD_OUT 2 0x306c 3 0 4294967295 RX_PMA_IQ_PHASE_ADJUST_MAP_OVRD_VAL 0 6 RX_PMA_IQ_PHASE_ADJUST_MAP_OVRD_EN 7 7 RESERVED_15_8 8 15 ixDPCSSYS_CR0_RAWLANE0_DIG_TX_CTL_TX_FSM_CTL 2 0x3080 6 0 4294967295 TX_WAIT_MPLL_OFF_TIME 0 6 TX_P2_ALLOW_RXDET 7 7 TX_P1_ALLOW_RXDET 8 8 TX_P0S_ALLOW_RXDET 9 9 TX_P0_ALLOW_RXDET 10 10 RESERVED_15_11 11 15 ixDPCSSYS_CR0_RAWLANE0_DIG_TX_CTL_TX_CLK_CTL 2 0x3081 4 0 4294967295 TX_CLK_EN 0 0 TX_CLK_SEL 1 4 ASYNC_BEACON_WAIT_TIME 5 10 RESERVED_15_11 11 15 ixDPCSSYS_CR0_RAWLANE0_DIG_TX_CTL_TX_DCC_CONT_STATUS 2 0x3082 2 0 4294967295 ENABLE 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR0_RAWLANE0_DIG_TX_CTL_OCLA 2 0x3083 2 0 4294967295 FSM_EN 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR0_RAWLANE0_DIG_TX_CTL_UPCS_OCLA 2 0x3084 3 0 4294967295 DATA_EN 0 1 CLK_EN 2 2 RESERVED_15_3 3 15 ixDPCSSYS_CR0_RAWLANE0_DIG_RX_CTL_RX_FSM_CTL 2 0x30a0 3 0 4294967295 EN_RX_CTL_FSM 0 0 RATE_CHG_IN_P1 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR0_RAWLANE0_DIG_RX_CTL_RX_LOS_MASK_CTL 2 0x30a1 2 0 4294967295 RX_LOS_MASK_CNT 0 8 RESERVED_15_9 9 15 ixDPCSSYS_CR0_RAWLANE0_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL 2 0x30a2 2 0 4294967295 RX_DATA_EN_OVRD_CNT 0 4 INT_REF_TRCK_CNT 5 15 ixDPCSSYS_CR0_RAWLANE0_DIG_RX_CTL_OFFCAN_CONT_STATUS 2 0x30a3 2 0 4294967295 ENABLE 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR0_RAWLANE0_DIG_RX_CTL_ADAPT_CONT_STATUS 2 0x30a4 2 0 4294967295 ENABLE 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR0_RAWLANE0_DIG_RX_CTL_UPCS_OCLA 2 0x30a5 3 0 4294967295 DATA_EN 0 2 CLK_EN 3 3 RESERVED_15_4 4 15 ixDPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN 2 0x30c0 11 0 4294967295 RATE_OVRD_VAL 0 1 RATE_OVRD_EN 2 2 WIDTH_OVRD_VAL 3 4 WIDTH_OVRD_EN 5 5 PSTATE_OVRD_VAL 6 7 PSTATE_OVRD_EN 8 8 LPD_OVRD_VAL 9 9 LPD_OVRD_EN 10 10 LANE_RX2TX_PAR_LB_EN_OVRD_VAL 11 11 LANE_RX2TX_PAR_LB_EN_OVRD_EN 12 12 RESERVED_15_13 13 15 ixDPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN 2 0x30c1 12 0 4294967295 PSTATE 0 1 LPD 2 2 WIDTH 3 4 RATE 5 7 MPLLB_SEL 8 8 MPLL_EN 9 9 OVRD_EN 10 10 MSTR_MPLLA_STATE 11 11 MSTR_MPLLB_STATE 12 12 MSTR_MPLL_OVRD_EN 13 13 TX_ASYNC_EN_OVR_VAL 14 14 TX_ASYNC_EN_OVR_EN 15 15 ixDPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1 2 0x30c2 13 0 4294967295 DETRX_REQ_OVRD_VAL 0 0 DETRX_REQ_OVRD_EN 1 1 VBOOST_EN_OVRD_VAL 2 2 VBOOST_EN_OVRD_EN 3 3 IBOOST_LVL_OVRD_VAL 4 7 IBOOST_LVL_OVRD_EN 8 8 TX_BEACON_EN_OVR_VAL 9 9 TX_BEACON_EN_OVR_EN 10 10 LANE_TX2RX_SER_LB_EN_OVRD_VAL 11 11 LANE_TX2RX_SER_LB_EN_OVRD_EN 12 12 TX_ASYNC_DATA_OVRD_VAL 13 13 TX_ASYNC_DATA_OVRD_EN 14 14 RESERVED_15_15 15 15 ixDPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_MASTER_MPLL_LOOP 2 0x30c3 3 0 4294967295 MPLLB_LOOP_EN 0 0 MPLLA_LOOP_EN 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1 2 0x30c4 11 0 4294967295 RESERVED 0 1 RX_LOS_LFPS_EN_OVRD_VAL 2 2 RX_LOS_LFPS_EN_OVRD_EN 3 3 RX_LOS_THRSHLD_OVRD_VAL 4 6 RX_LOS_THRSHLD_OVRD_EN 7 7 ADAPT_REQ 8 8 ADAPT_REQ_OVRD_EN 9 9 ADAPT_CONT 10 10 OFFCAN_CONT 11 11 CONT_OVRD_EN 12 12 RESERVED_15_13 13 15 ixDPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_2 2 0x30c5 4 0 4294967295 VCO_LD_VAL_OVRD 0 12 VCO_LD_VAL_OVRD_EN 13 13 VCO_LOWFREQ_VAL_OVRD 14 14 VCO_LOWFREQ_VAL_OVRD_EN 15 15 ixDPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_3 2 0x30c6 3 0 4294967295 REF_LD_VAL_OVRD 0 6 REF_LD_VAL_OVRD_EN 7 7 RESERVED_15_8 8 15 ixDPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT_2 2 0x30c7 3 0 4294967295 RX_VALID 0 0 RX_VALID_OVRD_EN 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_2 2 0x30c8 7 0 4294967295 LANE_TX2RX_SER_LB_EN_OVRD_VAL 0 0 LANE_TX2RX_SER_LB_EN_OVRD_EN 1 1 TX_DATA_EN_OVRD_VAL_R 2 2 TX_DATA_EN_OVRD_EN_R 3 3 TX_ASYNC_DATA_OVRD_VAL_R 4 4 TX_ASYNC_DATA_OVRD_EN_R 5 5 RESERVED_15_6 6 15 ixDPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN 2 0x3100 12 0 4294967295 PSTATE 0 1 LPD 2 2 WIDTH 3 4 RATE 5 7 MPLLB_SEL 8 8 MPLL_EN 9 9 OVRD_EN 10 10 MSTR_MPLLA_STATE 11 11 MSTR_MPLLB_STATE 12 12 MSTR_MPLL_OVRD_EN 13 13 TX_ASYNC_EN_OVR_VAL 14 14 TX_ASYNC_EN_OVR_EN 15 15 ixDPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1 2 0x3101 13 0 4294967295 RESET_OVRD_VAL 0 0 RESET_OVRD_EN 1 1 REQ_OVRD_VAL 2 2 REQ_OVRD_EN 3 3 DETRX_REQ_OVRD_VAL 4 4 DETRX_REQ_OVRD_EN 5 5 VBOOST_EN_OVRD_VAL 6 6 VBOOST_EN_OVRD_EN 7 7 IBOOST_LVL_OVRD_VAL 8 11 IBOOST_LVL_OVRD_EN 12 12 TX_BEACON_EN_OVR_VAL 13 13 TX_BEACON_EN_OVR_EN 14 14 RESERVED_15_15 15 15 ixDPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_PCS_IN 2 0x3102 12 0 4294967295 RESET 0 0 REQ 1 1 PSTATE 2 3 LPD 4 4 WIDTH 5 6 RATE 7 9 MPLLB_SEL 10 10 MPLL_EN 11 11 MSTR_MPLLA_STATE 12 12 MSTR_MPLLB_STATE 13 13 DETRX_REQ 14 14 RESERVED_15_15 15 15 ixDPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_OVRD_OUT 2 0x3103 6 0 4294967295 ACK 0 0 DETRX_RESULT 1 1 EN_CTL 2 2 TX_DWORD_CLK_SYNC_OVRD_VAL 3 3 TX_DWORD_CLK_SYNC_OVRD_EN 4 4 RESERVED_15_5 5 15 ixDPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_PCS_OUT 2 0x3104 2 0 4294967295 ACK 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN 2 0x3105 12 0 4294967295 RATE 0 1 WIDTH 2 3 PSTATE 4 5 LPD 6 6 OVRD_EN 7 7 ADAPT_AFE_EN 8 8 ADAPT_DFE_EN 9 9 LANE_RX2TX_PAR_LB_EN_OVRD_VAL 10 10 LANE_RX2TX_PAR_LB_EN_OVRD_EN 11 11 RX_DATA_EN_OVRD_VAL_R 12 12 RX_DATA_EN_OVRD_EN_R 13 13 RESERVED_15_14 14 15 ixDPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1 2 0x3106 12 0 4294967295 RESET_OVRD_VAL 0 0 RESET_OVRD_EN 1 1 REQ_OVRD_VAL 2 2 REQ_OVRD_EN 3 3 RX_LOS_THRSHLD_OVRD_VAL 4 6 RX_LOS_THRSHLD_OVRD_EN 7 7 ADAPT_REQ 8 8 ADAPT_REQ_OVRD_EN 9 9 ADAPT_CONT 10 10 OFFCAN_CONT 11 11 CONT_OVRD_EN 12 12 RESERVED_15_13 13 15 ixDPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_2 2 0x3107 4 0 4294967295 VCO_LD_VAL_OVRD 0 12 VCO_LD_VAL_OVRD_EN 13 13 VCO_LOWFREQ_VAL_OVRD 14 14 VCO_LOWFREQ_VAL_OVRD_EN 15 15 ixDPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_3 2 0x3108 3 0 4294967295 REF_LD_VAL_OVRD 0 6 REF_LD_VAL_OVRD_EN 7 7 RESERVED_15_8 8 15 ixDPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_PCS_IN 2 0x3109 13 0 4294967295 REQ 0 0 RATE 1 2 WIDTH 3 4 PSTATE 5 6 LPD 7 7 CDR_VCO_LOWFREQ 8 8 ADAPT_AFE_EN 9 9 ADAPT_DFE_EN 10 10 ADAPT_REQ 11 11 ADAPT_CONT 12 12 OFFCAN_CONT 13 13 RESET 14 14 RESERVED_15_15 15 15 ixDPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_1 2 0x310a 2 0 4294967295 REF_LD_VAL 0 6 RESERVED_15_7 7 15 ixDPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_2 2 0x310b 2 0 4294967295 VCO_LD_VAL 0 12 RESERVED_15_13 13 15 ixDPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_3 2 0x310c 4 0 4294967295 EQ_ATT_LVL 0 2 EQ_VGA1_GAIN 3 6 EQ_VGA2_GAIN 7 10 EQ_CTLE_BOOST 11 15 ixDPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_4 2 0x310d 3 0 4294967295 EQ_CTLE_POLE 0 2 EQ_DFE_TAP1 3 10 RESERVED_15_11 11 15 ixDPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT 2 0x310e 3 0 4294967295 ACK 0 0 EN_CTL 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_PCS_OUT 2 0x310f 2 0 4294967295 ACK 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_ADAPT_ACK 2 0x3110 2 0 4294967295 RX_ADAPT_ACK 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_ADAPT_FOM 2 0x3111 2 0 4294967295 RX_ADAPT_FOM 0 7 RESERVED_15_8 8 15 ixDPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_TXPRE_DIR 2 0x3112 2 0 4294967295 RX_TXPRE_DIR 0 1 RESERVED_15_2 2 15 ixDPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_TXMAIN_DIR 2 0x3113 2 0 4294967295 RX_TXMAIN_DIR 0 1 RESERVED_15_2 2 15 ixDPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_TXPOST_DIR 2 0x3114 2 0 4294967295 RX_TXPOST_DIR 0 1 RESERVED_15_2 2 15 ixDPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_LANE_NUMBER 2 0x3115 2 0 4294967295 LANE_NUMBER 0 3 RESERVED_15_4 4 15 ixDPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RESERVED_1 2 0x3116 1 0 4294967295 RESERVED_REG_1 0 15 ixDPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RESERVED_2 2 0x3117 1 0 4294967295 RESERVED_REG_2 0 15 ixDPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN 2 0x3118 16 0 4294967295 RX_RESET_ATE_OVRD_VAL 0 0 RX_RESET_ATE_OVRD_EN 1 1 TX_RESET_ATE_OVRD_VAL 2 2 TX_RESET_ATE_OVRD_EN 3 3 RX_REQ_ATE_OVRD_VAL 4 4 RX_REQ_ATE_OVRD_EN 5 5 TX_REQ_ATE_OVRD_VAL 6 6 TX_REQ_ATE_OVRD_EN 7 7 RX_ADAPT_AFE_EN_OVRD_VAL 8 8 RX_ADAPT_AFE_EN_OVRD_EN 9 9 RX_ADAPT_DFE_EN_OVRD_VAL 10 10 RX_ADAPT_DFE_EN_OVRD_EN 11 11 TX_DATA_EN_ATE_OVRD_VAL 12 12 TX_DATA_EN_ATE_OVRD_EN 13 13 RX_DATA_EN_ATE_OVRD_VAL 14 14 RX_DATA_EN_ATE_OVRD_EN 15 15 ixDPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN 2 0x3119 3 0 4294967295 RX_EQ_DELTA_IQ_OVRD_VAL 0 3 RX_EQ_DELTA_IQ_OVRD_EN 4 4 RESERVED_15_5 5 15 ixDPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN 2 0x311a 5 0 4294967295 RX_TERM_CTRL_OVRD_VAL 0 2 RX_TERM_CTRL_OVRD_EN 3 3 TX_TERM_CTRL_OVRD_VAL 4 6 TX_TERM_CTRL_OVRD_EN 7 7 RESERVED_15_8 8 15 ixDPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TXRX_TERM_CTRL_IN 2 0x311b 3 0 4294967295 RX_TERM_CTRL 0 2 TX_TERM_CTRL 3 5 RESERVED_15_6 6 15 ixDPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT_1 2 0x311c 2 0 4294967295 RX_CLK_EN 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_EQ_OVRD_IN_1 2 0x311d 4 0 4294967295 RX_EQ_AFE_GAIN_OVRD_VAL 0 3 RX_EQ_ATT_LVL_OVRD_VAL 4 6 RX_EQ_OVRD_EN 7 7 RESERVED_15_8 8 15 ixDPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_EQ_OVRD_IN_2 2 0x311e 3 0 4294967295 RX_EQ_DFE_TAP1_OVRD_VAL 0 7 RX_EQ_CTLE_BOOST_OVRD_VAL 8 12 RESERVED_15_13 13 15 ixDPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_PH2_CAL 2 0x311f 4 0 4294967295 PH2_CAL_ACK_VAL 0 0 PH2_CAL_REQ_VAL 1 1 PH2_CAL_REQ_OVRD_VAL 2 2 RESERVED_15_3 3 15 ixDPCSSYS_CR0_RAWLANE1_DIG_FSM_FSM_OVRD_CTL 2 0x3120 5 0 4294967295 FSM_JMP_ADDR 0 11 FSM_JMP_EN 12 12 FSM_CMD_START 13 13 FSM_OVRD_EN 14 14 FSM_BREAK 15 15 ixDPCSSYS_CR0_RAWLANE1_DIG_FSM_MEM_ADDR_MON 2 0x3121 1 0 4294967295 MEM_ADDR 0 15 ixDPCSSYS_CR0_RAWLANE1_DIG_FSM_STATUS_MON 2 0x3122 8 0 4294967295 STATE 0 4 CMD_RDY 5 5 ALU_OVFLW 6 6 ALU_RES_EQ0 7 7 WAIT_CNT_EQ0 8 8 WRMSK_DISABLED 9 9 RDMSK_DISABLED 10 10 RESERVED_15_11 11 15 ixDPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_RX_STARTUP_CAL 2 0x3123 2 0 4294967295 FAST_RX_STARTUP_CAL 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_RX_ADAPT 2 0x3124 2 0 4294967295 FAST_RX_ADAPT 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_RX_AFE_CAL 2 0x3125 2 0 4294967295 FAST_RX_AFE_CAL 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_RX_DFE_CAL 2 0x3126 2 0 4294967295 FAST_RX_DFE_CAL 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_RX_BYPASS_CAL 2 0x3127 2 0 4294967295 FAST_RX_BYPASS_CAL 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_RX_REFLVL_CAL 2 0x3128 2 0 4294967295 FAST_RX_REFLVL_CAL 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_RX_IQ_CAL 2 0x3129 2 0 4294967295 FAST_RX_IQ_CAL 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_RX_AFE_ADAPT 2 0x312a 2 0 4294967295 FAST_RX_AFE_ADAPT 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_RX_DFE_ADAPT 2 0x312b 2 0 4294967295 FAST_RX_DFE_ADAPT 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_SUP 2 0x312c 2 0 4294967295 FAST_SUP 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_TX_CMN_MODE 2 0x312d 2 0 4294967295 FAST_TX_CMN_MODE 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_TX_RXDET 2 0x312e 2 0 4294967295 FAST_TX_RXDET 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_RX_PWRUP 2 0x312f 2 0 4294967295 FAST_RX_PWRUP 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_RX_VCO_WAIT 2 0x3130 2 0 4294967295 FAST_RX_VCO_WAIT 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_RX_VCO_CAL 2 0x3131 2 0 4294967295 FAST_RX_VCO_CAL 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR0_RAWLANE1_DIG_FSM_CMNCAL_MPLL_STATUS 2 0x3132 3 0 4294967295 CMNCAL_MPLL_INIT 0 0 CMNCAL_MPLL_DONE 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_RX_CONT_CAL_ADAPT 2 0x3133 2 0 4294967295 FAST_RX_CONT_CAL_ADAPT 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_RX_CONT_ADAPT 2 0x3134 2 0 4294967295 FAST_RX_CONT_ADAPT 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_RX_CONT_DATA_CAL 2 0x3135 2 0 4294967295 FAST_RX_CONT_DATA_CAL 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_RX_CONT_PHASE_CAL 2 0x3136 2 0 4294967295 FAST_RX_CONT_PHASE_CAL 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_RX_CONT_AFE_CAL 2 0x3137 2 0 4294967295 FAST_RX_CONT_AFE_CAL 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_FLAGS 2 0x3138 12 0 4294967295 TX_FAST_DCC_CAL 0 0 RX_FAST_DCC_CAL 1 1 RX_FAST_VPHUD_CAL 2 2 RX_FAST_VREF_CAL 3 3 RX_FAST_SIGDET_CAL 4 4 RESERVED_2 5 7 TX_FAST_CONT_DCC_CAL 8 8 RX_FAST_CONT_DCC_CAL 9 9 RX_FAST_CONT_VPHUD_CAL 10 10 RX_FAST_CONT_VREF_CAL 11 11 RESERVED_1 12 14 TX_SKIP_SUP_CAL 15 15 ixDPCSSYS_CR0_RAWLANE1_DIG_FSM_CR_LOCK 2 0x3139 3 0 4294967295 CR_REG_LOCK 0 0 CR_MEM_LOCK 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR0_RAWLANE1_DIG_FSM_TX_DCC_FLAGS 2 0x313a 4 0 4294967295 RATE 0 0 DIV 1 1 MPLL 2 2 RESERVED_15_3 3 15 ixDPCSSYS_CR0_RAWLANE1_DIG_FSM_TX_DCC_STATUS 2 0x313b 2 0 4294967295 FLAG 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR0_RAWLANE1_DIG_FSM_OCLA 2 0x313c 4 0 4294967295 PC_EN 0 0 REG_BANK1_EN 1 1 REG_BANK2_EN 2 2 RESERVED_15_3 3 15 ixDPCSSYS_CR0_RAWLANE1_DIG_FSM_TX_EQ_UPDATE_FLAG 2 0x313d 2 0 4294967295 TX_EQ_UPDATE_FLAG 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR0_RAWLANE1_DIG_FSM_CMNCAL_RCAL_STATUS 2 0x313e 3 0 4294967295 CMNCAL_RCAL_INIT 0 0 CMNCAL_RCAL_DONE 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR0_RAWLANE1_DIG_FSM_RX_IQ_PHASE_OFFSET 2 0x313f 2 0 4294967295 RX_IQ_PHASE_OFFSET 0 3 RESERVED_15_4 4 15 ixDPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_RESET_RTN_REQ 2 0x3140 2 0 4294967295 RESET_RTN_REQ 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_RX_RESET_IRQ 2 0x3141 2 0 4294967295 RX_RESET 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_RX_REQ_IRQ 2 0x3142 2 0 4294967295 RX_REQ 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_RX_RATE_IRQ 2 0x3143 2 0 4294967295 RX_RATE_IRQ 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_RX_PSTATE_IRQ 2 0x3144 2 0 4294967295 RX_PSTATE_IRQ 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ 2 0x3145 2 0 4294967295 RX_ADAPT_REQ_IRQ 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ 2 0x3146 2 0 4294967295 RX_ADAPT_DIS_IRQ 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_RX_RESET_IRQ_CLR 2 0x3147 2 0 4294967295 RX_RESET_IRQ_CLR 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_RX_REQ_IRQ_CLR 2 0x3148 2 0 4294967295 RX_REQ_IRQ_CLR 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_RX_RATE_IRQ_CLR 2 0x3149 2 0 4294967295 RX_RATE_IRQ_CLR 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR 2 0x314a 2 0 4294967295 RX_PSTATE_IRQ_CLR 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR 2 0x314b 2 0 4294967295 RX_ADAPT_REQ_IRQ_CLR 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR 2 0x314c 2 0 4294967295 RX_ADAPT_DIS_IRQ_CLR 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK 2 0x314d 12 0 4294967295 RX_REQ_IRQ_MSK 0 0 RX_RATE_IRQ_MSK 1 1 RX_PSTATE_IRQ_MSK 2 2 RX_ADAPT_REQ_IRQ_MSK 3 3 RX_ADAPT_DIS_IRQ_MSK 4 4 RX_RESET_IRQ_MSK 5 5 LANE_XCVR_MODE_IRQ_MSK 6 6 RX_PH2_CAL_REQ_IRQ_MSK 7 7 RX_PH2_CAL_DIS_IRQ_MSK 8 8 LANE_RX2TX_SER_LB_EN_IRQ_MSK 9 9 DCC_ONDMD_IRQ_MSK 10 10 RESERVED_15_11 11 15 ixDPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK_2 2 0x314e 3 0 4294967295 TX_RESET_IRQ_MSK 0 0 TX_REQ_IRQ_MSK 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ 2 0x314f 2 0 4294967295 LANE_XCVR_MODE_IRQ 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR 2 0x3150 2 0 4294967295 LANE_XCVR_MODE_IRQ_CLR 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ 2 0x3151 2 0 4294967295 RX_PH2_CAL_REQ_IRQ 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ 2 0x3152 2 0 4294967295 RX_PH2_CAL_DIS_IRQ 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR 2 0x3153 2 0 4294967295 RX_PH2_CAL_REQ_IRQ_CLR 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR 2 0x3154 2 0 4294967295 RX_PH2_CAL_DIS_IRQ_CLR 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ 2 0x3155 2 0 4294967295 LANE_RX2TX_SER_LB_EN_IRQ 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR 2 0x3156 2 0 4294967295 LANE_RX2TX_SER_LB_EN_IRQ_CLR 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_DCC_ONDMD_IRQ 2 0x3157 2 0 4294967295 IRQ 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_TX_RESET_IRQ 2 0x3158 2 0 4294967295 TX_RESET 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_TX_REQ_IRQ 2 0x3159 2 0 4294967295 TX_REQ 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_TX_RESET_IRQ_CLR 2 0x315a 2 0 4294967295 TX_RESET_IRQ_CLR 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_TX_REQ_IRQ_CLR 2 0x315b 2 0 4294967295 TX_REQ_IRQ_CLR 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_LANE_OVRD_IN 2 0x3160 4 0 4294967295 LANE_MPLLA_EN_IN 0 0 LANE_MPLLB_EN_IN 1 1 LANE_OVRD_EN 2 2 RESERVED_15_3 3 15 ixDPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_LANE_OVRD_OUT 2 0x3161 4 0 4294967295 LANE_MPLLA_EN_OUT 0 0 LANE_MPLLB_EN_OUT 1 1 LANE_OVRD_EN 2 2 RESERVED_15_3 3 15 ixDPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_SUP_OVRD_IN 2 0x3162 4 0 4294967295 MPLLA_STATE 0 0 MPLLB_STATE 1 1 SUP_STATE_OVRD_EN 2 2 RESERVED_15_3 3 15 ixDPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_SUP_PMA_IN 2 0x3163 3 0 4294967295 MPLLA_STATE 0 0 MPLLB_STATE 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT 2 0x3164 16 0 4294967295 TX_REQ_OVRD_VAL 0 0 TX_REQ_OVRD_EN 1 1 TX_RESET_OVRD_VAL 2 2 TX_RESET_OVRD_EN 3 3 TX_BEACON_EN_OVRD_VAL 4 4 TX_BEACON_EN_OVRD_EN 5 5 TX_ASYNC_DRV_EN_OVRD_VAL 6 6 TX_ASYNC_DRV_EN_OVRD_EN 7 7 TX_ASYNC_EN_OVRD_VAL 8 8 TX_ASYNC_EN_OVRD_EN 9 9 TX_DWORD_CLK_SYNC_OVRD_VAL 10 10 TX_DWORD_CLK_SYNC_OVRD_EN 11 11 LANE_TX2RX_SER_LB_EN_OVRD_VAL 12 12 LANE_TX2RX_SER_LB_EN_OVRD_EN 13 13 TX_PMA_DATA_EN_OVRD_VAL_R 14 14 TX_PMA_DATA_EN_OVRD_EN_R 15 15 ixDPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_TX_PMA_IN 2 0x3165 2 0 4294967295 ACK 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT 2 0x3166 9 0 4294967295 RX_REQ_OVRD_VAL 0 0 RX_REQ_OVRD_EN 1 1 RX_RESET_OVRD_VAL 2 2 RX_RESET_OVRD_EN 3 3 LANE_RX2TX_PAR_LB_EN_OVRD_VAL 4 4 LANE_RX2TX_PAR_LB_EN_OVRD_EN 5 5 RX_PMA_DATA_EN_OVRD_VAL_R 6 6 RX_PMA_DATA_EN_OVRD_EN_R 7 7 RESERVED_15_8 8 15 ixDPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_RX_PMA_IN 2 0x3167 2 0 4294967295 ACK 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_LANE_RTUNE_CTL 2 0x3168 2 0 4294967295 LANE_RTUNE_REQ 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_SUP_PMA_IN_1 2 0x3169 2 0 4294967295 RTUNE_ACK 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_IN 2 0x316a 9 0 4294967295 RX_PMA_PWM_WORD_CLK_R 0 0 RX_PMA_PWM_WORD_CLK_OVRD_EN 1 1 RX_PMA_PWM_DATA_R 2 2 RX_PMA_PWM_DATA_OVRD_EN 3 3 RX_PMA_PWM_CLK_R 4 4 RX_PMA_PWM_CLK_OVRD_EN 5 5 RX_PMA_TERM_CTL_R 6 7 RX_PMA_TERM_CTL_OVRD_EN 8 8 RESERVED_15_9 9 15 ixDPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_OUT 2 0x316b 7 0 4294967295 RX_PMA_PWM_EN 0 0 RX_PMA_PWM_EN_OVRD_EN 1 1 RX_PMA_PWM_CLK_SEL 2 3 RX_PMA_PWM_CLK_SEL_OVRD_EN 4 4 RX_PMA_ASYNC_EN 5 5 RX_PMA_ASYNC_EN_OVRD_EN 6 6 RESERVED_15_7 7 15 ixDPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_RX_ADAPT_OVRD_OUT 2 0x316c 3 0 4294967295 RX_PMA_IQ_PHASE_ADJUST_MAP_OVRD_VAL 0 6 RX_PMA_IQ_PHASE_ADJUST_MAP_OVRD_EN 7 7 RESERVED_15_8 8 15 ixDPCSSYS_CR0_RAWLANE1_DIG_TX_CTL_TX_FSM_CTL 2 0x3180 6 0 4294967295 TX_WAIT_MPLL_OFF_TIME 0 6 TX_P2_ALLOW_RXDET 7 7 TX_P1_ALLOW_RXDET 8 8 TX_P0S_ALLOW_RXDET 9 9 TX_P0_ALLOW_RXDET 10 10 RESERVED_15_11 11 15 ixDPCSSYS_CR0_RAWLANE1_DIG_TX_CTL_TX_CLK_CTL 2 0x3181 4 0 4294967295 TX_CLK_EN 0 0 TX_CLK_SEL 1 4 ASYNC_BEACON_WAIT_TIME 5 10 RESERVED_15_11 11 15 ixDPCSSYS_CR0_RAWLANE1_DIG_TX_CTL_TX_DCC_CONT_STATUS 2 0x3182 2 0 4294967295 ENABLE 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR0_RAWLANE1_DIG_TX_CTL_OCLA 2 0x3183 2 0 4294967295 FSM_EN 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR0_RAWLANE1_DIG_TX_CTL_UPCS_OCLA 2 0x3184 3 0 4294967295 DATA_EN 0 1 CLK_EN 2 2 RESERVED_15_3 3 15 ixDPCSSYS_CR0_RAWLANE1_DIG_RX_CTL_RX_FSM_CTL 2 0x31a0 3 0 4294967295 EN_RX_CTL_FSM 0 0 RATE_CHG_IN_P1 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR0_RAWLANE1_DIG_RX_CTL_RX_LOS_MASK_CTL 2 0x31a1 2 0 4294967295 RX_LOS_MASK_CNT 0 8 RESERVED_15_9 9 15 ixDPCSSYS_CR0_RAWLANE1_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL 2 0x31a2 2 0 4294967295 RX_DATA_EN_OVRD_CNT 0 4 INT_REF_TRCK_CNT 5 15 ixDPCSSYS_CR0_RAWLANE1_DIG_RX_CTL_OFFCAN_CONT_STATUS 2 0x31a3 2 0 4294967295 ENABLE 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR0_RAWLANE1_DIG_RX_CTL_ADAPT_CONT_STATUS 2 0x31a4 2 0 4294967295 ENABLE 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR0_RAWLANE1_DIG_RX_CTL_UPCS_OCLA 2 0x31a5 3 0 4294967295 DATA_EN 0 2 CLK_EN 3 3 RESERVED_15_4 4 15 ixDPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN 2 0x31c0 11 0 4294967295 RATE_OVRD_VAL 0 1 RATE_OVRD_EN 2 2 WIDTH_OVRD_VAL 3 4 WIDTH_OVRD_EN 5 5 PSTATE_OVRD_VAL 6 7 PSTATE_OVRD_EN 8 8 LPD_OVRD_VAL 9 9 LPD_OVRD_EN 10 10 LANE_RX2TX_PAR_LB_EN_OVRD_VAL 11 11 LANE_RX2TX_PAR_LB_EN_OVRD_EN 12 12 RESERVED_15_13 13 15 ixDPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN 2 0x31c1 12 0 4294967295 PSTATE 0 1 LPD 2 2 WIDTH 3 4 RATE 5 7 MPLLB_SEL 8 8 MPLL_EN 9 9 OVRD_EN 10 10 MSTR_MPLLA_STATE 11 11 MSTR_MPLLB_STATE 12 12 MSTR_MPLL_OVRD_EN 13 13 TX_ASYNC_EN_OVR_VAL 14 14 TX_ASYNC_EN_OVR_EN 15 15 ixDPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1 2 0x31c2 13 0 4294967295 DETRX_REQ_OVRD_VAL 0 0 DETRX_REQ_OVRD_EN 1 1 VBOOST_EN_OVRD_VAL 2 2 VBOOST_EN_OVRD_EN 3 3 IBOOST_LVL_OVRD_VAL 4 7 IBOOST_LVL_OVRD_EN 8 8 TX_BEACON_EN_OVR_VAL 9 9 TX_BEACON_EN_OVR_EN 10 10 LANE_TX2RX_SER_LB_EN_OVRD_VAL 11 11 LANE_TX2RX_SER_LB_EN_OVRD_EN 12 12 TX_ASYNC_DATA_OVRD_VAL 13 13 TX_ASYNC_DATA_OVRD_EN 14 14 RESERVED_15_15 15 15 ixDPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_MASTER_MPLL_LOOP 2 0x31c3 3 0 4294967295 MPLLB_LOOP_EN 0 0 MPLLA_LOOP_EN 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1 2 0x31c4 11 0 4294967295 RESERVED 0 1 RX_LOS_LFPS_EN_OVRD_VAL 2 2 RX_LOS_LFPS_EN_OVRD_EN 3 3 RX_LOS_THRSHLD_OVRD_VAL 4 6 RX_LOS_THRSHLD_OVRD_EN 7 7 ADAPT_REQ 8 8 ADAPT_REQ_OVRD_EN 9 9 ADAPT_CONT 10 10 OFFCAN_CONT 11 11 CONT_OVRD_EN 12 12 RESERVED_15_13 13 15 ixDPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_2 2 0x31c5 4 0 4294967295 VCO_LD_VAL_OVRD 0 12 VCO_LD_VAL_OVRD_EN 13 13 VCO_LOWFREQ_VAL_OVRD 14 14 VCO_LOWFREQ_VAL_OVRD_EN 15 15 ixDPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_3 2 0x31c6 3 0 4294967295 REF_LD_VAL_OVRD 0 6 REF_LD_VAL_OVRD_EN 7 7 RESERVED_15_8 8 15 ixDPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT_2 2 0x31c7 3 0 4294967295 RX_VALID 0 0 RX_VALID_OVRD_EN 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_2 2 0x31c8 7 0 4294967295 LANE_TX2RX_SER_LB_EN_OVRD_VAL 0 0 LANE_TX2RX_SER_LB_EN_OVRD_EN 1 1 TX_DATA_EN_OVRD_VAL_R 2 2 TX_DATA_EN_OVRD_EN_R 3 3 TX_ASYNC_DATA_OVRD_VAL_R 4 4 TX_ASYNC_DATA_OVRD_EN_R 5 5 RESERVED_15_6 6 15 ixDPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN 2 0x3200 12 0 4294967295 PSTATE 0 1 LPD 2 2 WIDTH 3 4 RATE 5 7 MPLLB_SEL 8 8 MPLL_EN 9 9 OVRD_EN 10 10 MSTR_MPLLA_STATE 11 11 MSTR_MPLLB_STATE 12 12 MSTR_MPLL_OVRD_EN 13 13 TX_ASYNC_EN_OVR_VAL 14 14 TX_ASYNC_EN_OVR_EN 15 15 ixDPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1 2 0x3201 13 0 4294967295 RESET_OVRD_VAL 0 0 RESET_OVRD_EN 1 1 REQ_OVRD_VAL 2 2 REQ_OVRD_EN 3 3 DETRX_REQ_OVRD_VAL 4 4 DETRX_REQ_OVRD_EN 5 5 VBOOST_EN_OVRD_VAL 6 6 VBOOST_EN_OVRD_EN 7 7 IBOOST_LVL_OVRD_VAL 8 11 IBOOST_LVL_OVRD_EN 12 12 TX_BEACON_EN_OVR_VAL 13 13 TX_BEACON_EN_OVR_EN 14 14 RESERVED_15_15 15 15 ixDPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_PCS_IN 2 0x3202 12 0 4294967295 RESET 0 0 REQ 1 1 PSTATE 2 3 LPD 4 4 WIDTH 5 6 RATE 7 9 MPLLB_SEL 10 10 MPLL_EN 11 11 MSTR_MPLLA_STATE 12 12 MSTR_MPLLB_STATE 13 13 DETRX_REQ 14 14 RESERVED_15_15 15 15 ixDPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_OVRD_OUT 2 0x3203 6 0 4294967295 ACK 0 0 DETRX_RESULT 1 1 EN_CTL 2 2 TX_DWORD_CLK_SYNC_OVRD_VAL 3 3 TX_DWORD_CLK_SYNC_OVRD_EN 4 4 RESERVED_15_5 5 15 ixDPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_PCS_OUT 2 0x3204 2 0 4294967295 ACK 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN 2 0x3205 12 0 4294967295 RATE 0 1 WIDTH 2 3 PSTATE 4 5 LPD 6 6 OVRD_EN 7 7 ADAPT_AFE_EN 8 8 ADAPT_DFE_EN 9 9 LANE_RX2TX_PAR_LB_EN_OVRD_VAL 10 10 LANE_RX2TX_PAR_LB_EN_OVRD_EN 11 11 RX_DATA_EN_OVRD_VAL_R 12 12 RX_DATA_EN_OVRD_EN_R 13 13 RESERVED_15_14 14 15 ixDPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1 2 0x3206 12 0 4294967295 RESET_OVRD_VAL 0 0 RESET_OVRD_EN 1 1 REQ_OVRD_VAL 2 2 REQ_OVRD_EN 3 3 RX_LOS_THRSHLD_OVRD_VAL 4 6 RX_LOS_THRSHLD_OVRD_EN 7 7 ADAPT_REQ 8 8 ADAPT_REQ_OVRD_EN 9 9 ADAPT_CONT 10 10 OFFCAN_CONT 11 11 CONT_OVRD_EN 12 12 RESERVED_15_13 13 15 ixDPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_2 2 0x3207 4 0 4294967295 VCO_LD_VAL_OVRD 0 12 VCO_LD_VAL_OVRD_EN 13 13 VCO_LOWFREQ_VAL_OVRD 14 14 VCO_LOWFREQ_VAL_OVRD_EN 15 15 ixDPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_3 2 0x3208 3 0 4294967295 REF_LD_VAL_OVRD 0 6 REF_LD_VAL_OVRD_EN 7 7 RESERVED_15_8 8 15 ixDPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_PCS_IN 2 0x3209 13 0 4294967295 REQ 0 0 RATE 1 2 WIDTH 3 4 PSTATE 5 6 LPD 7 7 CDR_VCO_LOWFREQ 8 8 ADAPT_AFE_EN 9 9 ADAPT_DFE_EN 10 10 ADAPT_REQ 11 11 ADAPT_CONT 12 12 OFFCAN_CONT 13 13 RESET 14 14 RESERVED_15_15 15 15 ixDPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_1 2 0x320a 2 0 4294967295 REF_LD_VAL 0 6 RESERVED_15_7 7 15 ixDPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_2 2 0x320b 2 0 4294967295 VCO_LD_VAL 0 12 RESERVED_15_13 13 15 ixDPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_3 2 0x320c 4 0 4294967295 EQ_ATT_LVL 0 2 EQ_VGA1_GAIN 3 6 EQ_VGA2_GAIN 7 10 EQ_CTLE_BOOST 11 15 ixDPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_4 2 0x320d 3 0 4294967295 EQ_CTLE_POLE 0 2 EQ_DFE_TAP1 3 10 RESERVED_15_11 11 15 ixDPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT 2 0x320e 3 0 4294967295 ACK 0 0 EN_CTL 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_PCS_OUT 2 0x320f 2 0 4294967295 ACK 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_ADAPT_ACK 2 0x3210 2 0 4294967295 RX_ADAPT_ACK 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_ADAPT_FOM 2 0x3211 2 0 4294967295 RX_ADAPT_FOM 0 7 RESERVED_15_8 8 15 ixDPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_TXPRE_DIR 2 0x3212 2 0 4294967295 RX_TXPRE_DIR 0 1 RESERVED_15_2 2 15 ixDPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_TXMAIN_DIR 2 0x3213 2 0 4294967295 RX_TXMAIN_DIR 0 1 RESERVED_15_2 2 15 ixDPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_TXPOST_DIR 2 0x3214 2 0 4294967295 RX_TXPOST_DIR 0 1 RESERVED_15_2 2 15 ixDPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_LANE_NUMBER 2 0x3215 2 0 4294967295 LANE_NUMBER 0 3 RESERVED_15_4 4 15 ixDPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RESERVED_1 2 0x3216 1 0 4294967295 RESERVED_REG_1 0 15 ixDPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RESERVED_2 2 0x3217 1 0 4294967295 RESERVED_REG_2 0 15 ixDPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN 2 0x3218 16 0 4294967295 RX_RESET_ATE_OVRD_VAL 0 0 RX_RESET_ATE_OVRD_EN 1 1 TX_RESET_ATE_OVRD_VAL 2 2 TX_RESET_ATE_OVRD_EN 3 3 RX_REQ_ATE_OVRD_VAL 4 4 RX_REQ_ATE_OVRD_EN 5 5 TX_REQ_ATE_OVRD_VAL 6 6 TX_REQ_ATE_OVRD_EN 7 7 RX_ADAPT_AFE_EN_OVRD_VAL 8 8 RX_ADAPT_AFE_EN_OVRD_EN 9 9 RX_ADAPT_DFE_EN_OVRD_VAL 10 10 RX_ADAPT_DFE_EN_OVRD_EN 11 11 TX_DATA_EN_ATE_OVRD_VAL 12 12 TX_DATA_EN_ATE_OVRD_EN 13 13 RX_DATA_EN_ATE_OVRD_VAL 14 14 RX_DATA_EN_ATE_OVRD_EN 15 15 ixDPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN 2 0x3219 3 0 4294967295 RX_EQ_DELTA_IQ_OVRD_VAL 0 3 RX_EQ_DELTA_IQ_OVRD_EN 4 4 RESERVED_15_5 5 15 ixDPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN 2 0x321a 5 0 4294967295 RX_TERM_CTRL_OVRD_VAL 0 2 RX_TERM_CTRL_OVRD_EN 3 3 TX_TERM_CTRL_OVRD_VAL 4 6 TX_TERM_CTRL_OVRD_EN 7 7 RESERVED_15_8 8 15 ixDPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TXRX_TERM_CTRL_IN 2 0x321b 3 0 4294967295 RX_TERM_CTRL 0 2 TX_TERM_CTRL 3 5 RESERVED_15_6 6 15 ixDPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT_1 2 0x321c 2 0 4294967295 RX_CLK_EN 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_EQ_OVRD_IN_1 2 0x321d 4 0 4294967295 RX_EQ_AFE_GAIN_OVRD_VAL 0 3 RX_EQ_ATT_LVL_OVRD_VAL 4 6 RX_EQ_OVRD_EN 7 7 RESERVED_15_8 8 15 ixDPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_EQ_OVRD_IN_2 2 0x321e 3 0 4294967295 RX_EQ_DFE_TAP1_OVRD_VAL 0 7 RX_EQ_CTLE_BOOST_OVRD_VAL 8 12 RESERVED_15_13 13 15 ixDPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_PH2_CAL 2 0x321f 4 0 4294967295 PH2_CAL_ACK_VAL 0 0 PH2_CAL_REQ_VAL 1 1 PH2_CAL_REQ_OVRD_VAL 2 2 RESERVED_15_3 3 15 ixDPCSSYS_CR0_RAWLANE2_DIG_FSM_FSM_OVRD_CTL 2 0x3220 5 0 4294967295 FSM_JMP_ADDR 0 11 FSM_JMP_EN 12 12 FSM_CMD_START 13 13 FSM_OVRD_EN 14 14 FSM_BREAK 15 15 ixDPCSSYS_CR0_RAWLANE2_DIG_FSM_MEM_ADDR_MON 2 0x3221 1 0 4294967295 MEM_ADDR 0 15 ixDPCSSYS_CR0_RAWLANE2_DIG_FSM_STATUS_MON 2 0x3222 8 0 4294967295 STATE 0 4 CMD_RDY 5 5 ALU_OVFLW 6 6 ALU_RES_EQ0 7 7 WAIT_CNT_EQ0 8 8 WRMSK_DISABLED 9 9 RDMSK_DISABLED 10 10 RESERVED_15_11 11 15 ixDPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_RX_STARTUP_CAL 2 0x3223 2 0 4294967295 FAST_RX_STARTUP_CAL 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_RX_ADAPT 2 0x3224 2 0 4294967295 FAST_RX_ADAPT 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_RX_AFE_CAL 2 0x3225 2 0 4294967295 FAST_RX_AFE_CAL 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_RX_DFE_CAL 2 0x3226 2 0 4294967295 FAST_RX_DFE_CAL 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_RX_BYPASS_CAL 2 0x3227 2 0 4294967295 FAST_RX_BYPASS_CAL 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_RX_REFLVL_CAL 2 0x3228 2 0 4294967295 FAST_RX_REFLVL_CAL 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_RX_IQ_CAL 2 0x3229 2 0 4294967295 FAST_RX_IQ_CAL 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_RX_AFE_ADAPT 2 0x322a 2 0 4294967295 FAST_RX_AFE_ADAPT 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_RX_DFE_ADAPT 2 0x322b 2 0 4294967295 FAST_RX_DFE_ADAPT 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_SUP 2 0x322c 2 0 4294967295 FAST_SUP 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_TX_CMN_MODE 2 0x322d 2 0 4294967295 FAST_TX_CMN_MODE 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_TX_RXDET 2 0x322e 2 0 4294967295 FAST_TX_RXDET 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_RX_PWRUP 2 0x322f 2 0 4294967295 FAST_RX_PWRUP 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_RX_VCO_WAIT 2 0x3230 2 0 4294967295 FAST_RX_VCO_WAIT 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_RX_VCO_CAL 2 0x3231 2 0 4294967295 FAST_RX_VCO_CAL 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR0_RAWLANE2_DIG_FSM_CMNCAL_MPLL_STATUS 2 0x3232 3 0 4294967295 CMNCAL_MPLL_INIT 0 0 CMNCAL_MPLL_DONE 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_RX_CONT_CAL_ADAPT 2 0x3233 2 0 4294967295 FAST_RX_CONT_CAL_ADAPT 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_RX_CONT_ADAPT 2 0x3234 2 0 4294967295 FAST_RX_CONT_ADAPT 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_RX_CONT_DATA_CAL 2 0x3235 2 0 4294967295 FAST_RX_CONT_DATA_CAL 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_RX_CONT_PHASE_CAL 2 0x3236 2 0 4294967295 FAST_RX_CONT_PHASE_CAL 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_RX_CONT_AFE_CAL 2 0x3237 2 0 4294967295 FAST_RX_CONT_AFE_CAL 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_FLAGS 2 0x3238 12 0 4294967295 TX_FAST_DCC_CAL 0 0 RX_FAST_DCC_CAL 1 1 RX_FAST_VPHUD_CAL 2 2 RX_FAST_VREF_CAL 3 3 RX_FAST_SIGDET_CAL 4 4 RESERVED_2 5 7 TX_FAST_CONT_DCC_CAL 8 8 RX_FAST_CONT_DCC_CAL 9 9 RX_FAST_CONT_VPHUD_CAL 10 10 RX_FAST_CONT_VREF_CAL 11 11 RESERVED_1 12 14 TX_SKIP_SUP_CAL 15 15 ixDPCSSYS_CR0_RAWLANE2_DIG_FSM_CR_LOCK 2 0x3239 3 0 4294967295 CR_REG_LOCK 0 0 CR_MEM_LOCK 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR0_RAWLANE2_DIG_FSM_TX_DCC_FLAGS 2 0x323a 4 0 4294967295 RATE 0 0 DIV 1 1 MPLL 2 2 RESERVED_15_3 3 15 ixDPCSSYS_CR0_RAWLANE2_DIG_FSM_TX_DCC_STATUS 2 0x323b 2 0 4294967295 FLAG 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR0_RAWLANE2_DIG_FSM_OCLA 2 0x323c 4 0 4294967295 PC_EN 0 0 REG_BANK1_EN 1 1 REG_BANK2_EN 2 2 RESERVED_15_3 3 15 ixDPCSSYS_CR0_RAWLANE2_DIG_FSM_TX_EQ_UPDATE_FLAG 2 0x323d 2 0 4294967295 TX_EQ_UPDATE_FLAG 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR0_RAWLANE2_DIG_FSM_CMNCAL_RCAL_STATUS 2 0x323e 3 0 4294967295 CMNCAL_RCAL_INIT 0 0 CMNCAL_RCAL_DONE 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR0_RAWLANE2_DIG_FSM_RX_IQ_PHASE_OFFSET 2 0x323f 2 0 4294967295 RX_IQ_PHASE_OFFSET 0 3 RESERVED_15_4 4 15 ixDPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_RESET_RTN_REQ 2 0x3240 2 0 4294967295 RESET_RTN_REQ 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_RX_RESET_IRQ 2 0x3241 2 0 4294967295 RX_RESET 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_RX_REQ_IRQ 2 0x3242 2 0 4294967295 RX_REQ 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_RX_RATE_IRQ 2 0x3243 2 0 4294967295 RX_RATE_IRQ 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_RX_PSTATE_IRQ 2 0x3244 2 0 4294967295 RX_PSTATE_IRQ 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ 2 0x3245 2 0 4294967295 RX_ADAPT_REQ_IRQ 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ 2 0x3246 2 0 4294967295 RX_ADAPT_DIS_IRQ 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_RX_RESET_IRQ_CLR 2 0x3247 2 0 4294967295 RX_RESET_IRQ_CLR 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_RX_REQ_IRQ_CLR 2 0x3248 2 0 4294967295 RX_REQ_IRQ_CLR 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_RX_RATE_IRQ_CLR 2 0x3249 2 0 4294967295 RX_RATE_IRQ_CLR 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR 2 0x324a 2 0 4294967295 RX_PSTATE_IRQ_CLR 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR 2 0x324b 2 0 4294967295 RX_ADAPT_REQ_IRQ_CLR 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR 2 0x324c 2 0 4294967295 RX_ADAPT_DIS_IRQ_CLR 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK 2 0x324d 12 0 4294967295 RX_REQ_IRQ_MSK 0 0 RX_RATE_IRQ_MSK 1 1 RX_PSTATE_IRQ_MSK 2 2 RX_ADAPT_REQ_IRQ_MSK 3 3 RX_ADAPT_DIS_IRQ_MSK 4 4 RX_RESET_IRQ_MSK 5 5 LANE_XCVR_MODE_IRQ_MSK 6 6 RX_PH2_CAL_REQ_IRQ_MSK 7 7 RX_PH2_CAL_DIS_IRQ_MSK 8 8 LANE_RX2TX_SER_LB_EN_IRQ_MSK 9 9 DCC_ONDMD_IRQ_MSK 10 10 RESERVED_15_11 11 15 ixDPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK_2 2 0x324e 3 0 4294967295 TX_RESET_IRQ_MSK 0 0 TX_REQ_IRQ_MSK 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ 2 0x324f 2 0 4294967295 LANE_XCVR_MODE_IRQ 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR 2 0x3250 2 0 4294967295 LANE_XCVR_MODE_IRQ_CLR 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ 2 0x3251 2 0 4294967295 RX_PH2_CAL_REQ_IRQ 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ 2 0x3252 2 0 4294967295 RX_PH2_CAL_DIS_IRQ 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR 2 0x3253 2 0 4294967295 RX_PH2_CAL_REQ_IRQ_CLR 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR 2 0x3254 2 0 4294967295 RX_PH2_CAL_DIS_IRQ_CLR 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ 2 0x3255 2 0 4294967295 LANE_RX2TX_SER_LB_EN_IRQ 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR 2 0x3256 2 0 4294967295 LANE_RX2TX_SER_LB_EN_IRQ_CLR 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_DCC_ONDMD_IRQ 2 0x3257 2 0 4294967295 IRQ 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_TX_RESET_IRQ 2 0x3258 2 0 4294967295 TX_RESET 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_TX_REQ_IRQ 2 0x3259 2 0 4294967295 TX_REQ 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_TX_RESET_IRQ_CLR 2 0x325a 2 0 4294967295 TX_RESET_IRQ_CLR 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_TX_REQ_IRQ_CLR 2 0x325b 2 0 4294967295 TX_REQ_IRQ_CLR 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_LANE_OVRD_IN 2 0x3260 4 0 4294967295 LANE_MPLLA_EN_IN 0 0 LANE_MPLLB_EN_IN 1 1 LANE_OVRD_EN 2 2 RESERVED_15_3 3 15 ixDPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_LANE_OVRD_OUT 2 0x3261 4 0 4294967295 LANE_MPLLA_EN_OUT 0 0 LANE_MPLLB_EN_OUT 1 1 LANE_OVRD_EN 2 2 RESERVED_15_3 3 15 ixDPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_SUP_OVRD_IN 2 0x3262 4 0 4294967295 MPLLA_STATE 0 0 MPLLB_STATE 1 1 SUP_STATE_OVRD_EN 2 2 RESERVED_15_3 3 15 ixDPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_SUP_PMA_IN 2 0x3263 3 0 4294967295 MPLLA_STATE 0 0 MPLLB_STATE 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT 2 0x3264 16 0 4294967295 TX_REQ_OVRD_VAL 0 0 TX_REQ_OVRD_EN 1 1 TX_RESET_OVRD_VAL 2 2 TX_RESET_OVRD_EN 3 3 TX_BEACON_EN_OVRD_VAL 4 4 TX_BEACON_EN_OVRD_EN 5 5 TX_ASYNC_DRV_EN_OVRD_VAL 6 6 TX_ASYNC_DRV_EN_OVRD_EN 7 7 TX_ASYNC_EN_OVRD_VAL 8 8 TX_ASYNC_EN_OVRD_EN 9 9 TX_DWORD_CLK_SYNC_OVRD_VAL 10 10 TX_DWORD_CLK_SYNC_OVRD_EN 11 11 LANE_TX2RX_SER_LB_EN_OVRD_VAL 12 12 LANE_TX2RX_SER_LB_EN_OVRD_EN 13 13 TX_PMA_DATA_EN_OVRD_VAL_R 14 14 TX_PMA_DATA_EN_OVRD_EN_R 15 15 ixDPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_TX_PMA_IN 2 0x3265 2 0 4294967295 ACK 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT 2 0x3266 9 0 4294967295 RX_REQ_OVRD_VAL 0 0 RX_REQ_OVRD_EN 1 1 RX_RESET_OVRD_VAL 2 2 RX_RESET_OVRD_EN 3 3 LANE_RX2TX_PAR_LB_EN_OVRD_VAL 4 4 LANE_RX2TX_PAR_LB_EN_OVRD_EN 5 5 RX_PMA_DATA_EN_OVRD_VAL_R 6 6 RX_PMA_DATA_EN_OVRD_EN_R 7 7 RESERVED_15_8 8 15 ixDPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_RX_PMA_IN 2 0x3267 2 0 4294967295 ACK 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_LANE_RTUNE_CTL 2 0x3268 2 0 4294967295 LANE_RTUNE_REQ 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_SUP_PMA_IN_1 2 0x3269 2 0 4294967295 RTUNE_ACK 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_IN 2 0x326a 9 0 4294967295 RX_PMA_PWM_WORD_CLK_R 0 0 RX_PMA_PWM_WORD_CLK_OVRD_EN 1 1 RX_PMA_PWM_DATA_R 2 2 RX_PMA_PWM_DATA_OVRD_EN 3 3 RX_PMA_PWM_CLK_R 4 4 RX_PMA_PWM_CLK_OVRD_EN 5 5 RX_PMA_TERM_CTL_R 6 7 RX_PMA_TERM_CTL_OVRD_EN 8 8 RESERVED_15_9 9 15 ixDPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_OUT 2 0x326b 7 0 4294967295 RX_PMA_PWM_EN 0 0 RX_PMA_PWM_EN_OVRD_EN 1 1 RX_PMA_PWM_CLK_SEL 2 3 RX_PMA_PWM_CLK_SEL_OVRD_EN 4 4 RX_PMA_ASYNC_EN 5 5 RX_PMA_ASYNC_EN_OVRD_EN 6 6 RESERVED_15_7 7 15 ixDPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_RX_ADAPT_OVRD_OUT 2 0x326c 3 0 4294967295 RX_PMA_IQ_PHASE_ADJUST_MAP_OVRD_VAL 0 6 RX_PMA_IQ_PHASE_ADJUST_MAP_OVRD_EN 7 7 RESERVED_15_8 8 15 ixDPCSSYS_CR0_RAWLANE2_DIG_TX_CTL_TX_FSM_CTL 2 0x3280 6 0 4294967295 TX_WAIT_MPLL_OFF_TIME 0 6 TX_P2_ALLOW_RXDET 7 7 TX_P1_ALLOW_RXDET 8 8 TX_P0S_ALLOW_RXDET 9 9 TX_P0_ALLOW_RXDET 10 10 RESERVED_15_11 11 15 ixDPCSSYS_CR0_RAWLANE2_DIG_TX_CTL_TX_CLK_CTL 2 0x3281 4 0 4294967295 TX_CLK_EN 0 0 TX_CLK_SEL 1 4 ASYNC_BEACON_WAIT_TIME 5 10 RESERVED_15_11 11 15 ixDPCSSYS_CR0_RAWLANE2_DIG_TX_CTL_TX_DCC_CONT_STATUS 2 0x3282 2 0 4294967295 ENABLE 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR0_RAWLANE2_DIG_TX_CTL_OCLA 2 0x3283 2 0 4294967295 FSM_EN 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR0_RAWLANE2_DIG_TX_CTL_UPCS_OCLA 2 0x3284 3 0 4294967295 DATA_EN 0 1 CLK_EN 2 2 RESERVED_15_3 3 15 ixDPCSSYS_CR0_RAWLANE2_DIG_RX_CTL_RX_FSM_CTL 2 0x32a0 3 0 4294967295 EN_RX_CTL_FSM 0 0 RATE_CHG_IN_P1 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR0_RAWLANE2_DIG_RX_CTL_RX_LOS_MASK_CTL 2 0x32a1 2 0 4294967295 RX_LOS_MASK_CNT 0 8 RESERVED_15_9 9 15 ixDPCSSYS_CR0_RAWLANE2_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL 2 0x32a2 2 0 4294967295 RX_DATA_EN_OVRD_CNT 0 4 INT_REF_TRCK_CNT 5 15 ixDPCSSYS_CR0_RAWLANE2_DIG_RX_CTL_OFFCAN_CONT_STATUS 2 0x32a3 2 0 4294967295 ENABLE 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR0_RAWLANE2_DIG_RX_CTL_ADAPT_CONT_STATUS 2 0x32a4 2 0 4294967295 ENABLE 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR0_RAWLANE2_DIG_RX_CTL_UPCS_OCLA 2 0x32a5 3 0 4294967295 DATA_EN 0 2 CLK_EN 3 3 RESERVED_15_4 4 15 ixDPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN 2 0x32c0 11 0 4294967295 RATE_OVRD_VAL 0 1 RATE_OVRD_EN 2 2 WIDTH_OVRD_VAL 3 4 WIDTH_OVRD_EN 5 5 PSTATE_OVRD_VAL 6 7 PSTATE_OVRD_EN 8 8 LPD_OVRD_VAL 9 9 LPD_OVRD_EN 10 10 LANE_RX2TX_PAR_LB_EN_OVRD_VAL 11 11 LANE_RX2TX_PAR_LB_EN_OVRD_EN 12 12 RESERVED_15_13 13 15 ixDPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN 2 0x32c1 12 0 4294967295 PSTATE 0 1 LPD 2 2 WIDTH 3 4 RATE 5 7 MPLLB_SEL 8 8 MPLL_EN 9 9 OVRD_EN 10 10 MSTR_MPLLA_STATE 11 11 MSTR_MPLLB_STATE 12 12 MSTR_MPLL_OVRD_EN 13 13 TX_ASYNC_EN_OVR_VAL 14 14 TX_ASYNC_EN_OVR_EN 15 15 ixDPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1 2 0x32c2 13 0 4294967295 DETRX_REQ_OVRD_VAL 0 0 DETRX_REQ_OVRD_EN 1 1 VBOOST_EN_OVRD_VAL 2 2 VBOOST_EN_OVRD_EN 3 3 IBOOST_LVL_OVRD_VAL 4 7 IBOOST_LVL_OVRD_EN 8 8 TX_BEACON_EN_OVR_VAL 9 9 TX_BEACON_EN_OVR_EN 10 10 LANE_TX2RX_SER_LB_EN_OVRD_VAL 11 11 LANE_TX2RX_SER_LB_EN_OVRD_EN 12 12 TX_ASYNC_DATA_OVRD_VAL 13 13 TX_ASYNC_DATA_OVRD_EN 14 14 RESERVED_15_15 15 15 ixDPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_MASTER_MPLL_LOOP 2 0x32c3 3 0 4294967295 MPLLB_LOOP_EN 0 0 MPLLA_LOOP_EN 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1 2 0x32c4 11 0 4294967295 RESERVED 0 1 RX_LOS_LFPS_EN_OVRD_VAL 2 2 RX_LOS_LFPS_EN_OVRD_EN 3 3 RX_LOS_THRSHLD_OVRD_VAL 4 6 RX_LOS_THRSHLD_OVRD_EN 7 7 ADAPT_REQ 8 8 ADAPT_REQ_OVRD_EN 9 9 ADAPT_CONT 10 10 OFFCAN_CONT 11 11 CONT_OVRD_EN 12 12 RESERVED_15_13 13 15 ixDPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_2 2 0x32c5 4 0 4294967295 VCO_LD_VAL_OVRD 0 12 VCO_LD_VAL_OVRD_EN 13 13 VCO_LOWFREQ_VAL_OVRD 14 14 VCO_LOWFREQ_VAL_OVRD_EN 15 15 ixDPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_3 2 0x32c6 3 0 4294967295 REF_LD_VAL_OVRD 0 6 REF_LD_VAL_OVRD_EN 7 7 RESERVED_15_8 8 15 ixDPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT_2 2 0x32c7 3 0 4294967295 RX_VALID 0 0 RX_VALID_OVRD_EN 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_2 2 0x32c8 7 0 4294967295 LANE_TX2RX_SER_LB_EN_OVRD_VAL 0 0 LANE_TX2RX_SER_LB_EN_OVRD_EN 1 1 TX_DATA_EN_OVRD_VAL_R 2 2 TX_DATA_EN_OVRD_EN_R 3 3 TX_ASYNC_DATA_OVRD_VAL_R 4 4 TX_ASYNC_DATA_OVRD_EN_R 5 5 RESERVED_15_6 6 15 ixDPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN 2 0x3300 12 0 4294967295 PSTATE 0 1 LPD 2 2 WIDTH 3 4 RATE 5 7 MPLLB_SEL 8 8 MPLL_EN 9 9 OVRD_EN 10 10 MSTR_MPLLA_STATE 11 11 MSTR_MPLLB_STATE 12 12 MSTR_MPLL_OVRD_EN 13 13 TX_ASYNC_EN_OVR_VAL 14 14 TX_ASYNC_EN_OVR_EN 15 15 ixDPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1 2 0x3301 13 0 4294967295 RESET_OVRD_VAL 0 0 RESET_OVRD_EN 1 1 REQ_OVRD_VAL 2 2 REQ_OVRD_EN 3 3 DETRX_REQ_OVRD_VAL 4 4 DETRX_REQ_OVRD_EN 5 5 VBOOST_EN_OVRD_VAL 6 6 VBOOST_EN_OVRD_EN 7 7 IBOOST_LVL_OVRD_VAL 8 11 IBOOST_LVL_OVRD_EN 12 12 TX_BEACON_EN_OVR_VAL 13 13 TX_BEACON_EN_OVR_EN 14 14 RESERVED_15_15 15 15 ixDPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_PCS_IN 2 0x3302 12 0 4294967295 RESET 0 0 REQ 1 1 PSTATE 2 3 LPD 4 4 WIDTH 5 6 RATE 7 9 MPLLB_SEL 10 10 MPLL_EN 11 11 MSTR_MPLLA_STATE 12 12 MSTR_MPLLB_STATE 13 13 DETRX_REQ 14 14 RESERVED_15_15 15 15 ixDPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_OVRD_OUT 2 0x3303 6 0 4294967295 ACK 0 0 DETRX_RESULT 1 1 EN_CTL 2 2 TX_DWORD_CLK_SYNC_OVRD_VAL 3 3 TX_DWORD_CLK_SYNC_OVRD_EN 4 4 RESERVED_15_5 5 15 ixDPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_PCS_OUT 2 0x3304 2 0 4294967295 ACK 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN 2 0x3305 12 0 4294967295 RATE 0 1 WIDTH 2 3 PSTATE 4 5 LPD 6 6 OVRD_EN 7 7 ADAPT_AFE_EN 8 8 ADAPT_DFE_EN 9 9 LANE_RX2TX_PAR_LB_EN_OVRD_VAL 10 10 LANE_RX2TX_PAR_LB_EN_OVRD_EN 11 11 RX_DATA_EN_OVRD_VAL_R 12 12 RX_DATA_EN_OVRD_EN_R 13 13 RESERVED_15_14 14 15 ixDPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1 2 0x3306 12 0 4294967295 RESET_OVRD_VAL 0 0 RESET_OVRD_EN 1 1 REQ_OVRD_VAL 2 2 REQ_OVRD_EN 3 3 RX_LOS_THRSHLD_OVRD_VAL 4 6 RX_LOS_THRSHLD_OVRD_EN 7 7 ADAPT_REQ 8 8 ADAPT_REQ_OVRD_EN 9 9 ADAPT_CONT 10 10 OFFCAN_CONT 11 11 CONT_OVRD_EN 12 12 RESERVED_15_13 13 15 ixDPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_2 2 0x3307 4 0 4294967295 VCO_LD_VAL_OVRD 0 12 VCO_LD_VAL_OVRD_EN 13 13 VCO_LOWFREQ_VAL_OVRD 14 14 VCO_LOWFREQ_VAL_OVRD_EN 15 15 ixDPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_3 2 0x3308 3 0 4294967295 REF_LD_VAL_OVRD 0 6 REF_LD_VAL_OVRD_EN 7 7 RESERVED_15_8 8 15 ixDPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_PCS_IN 2 0x3309 13 0 4294967295 REQ 0 0 RATE 1 2 WIDTH 3 4 PSTATE 5 6 LPD 7 7 CDR_VCO_LOWFREQ 8 8 ADAPT_AFE_EN 9 9 ADAPT_DFE_EN 10 10 ADAPT_REQ 11 11 ADAPT_CONT 12 12 OFFCAN_CONT 13 13 RESET 14 14 RESERVED_15_15 15 15 ixDPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_1 2 0x330a 2 0 4294967295 REF_LD_VAL 0 6 RESERVED_15_7 7 15 ixDPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_2 2 0x330b 2 0 4294967295 VCO_LD_VAL 0 12 RESERVED_15_13 13 15 ixDPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_3 2 0x330c 4 0 4294967295 EQ_ATT_LVL 0 2 EQ_VGA1_GAIN 3 6 EQ_VGA2_GAIN 7 10 EQ_CTLE_BOOST 11 15 ixDPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_4 2 0x330d 3 0 4294967295 EQ_CTLE_POLE 0 2 EQ_DFE_TAP1 3 10 RESERVED_15_11 11 15 ixDPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT 2 0x330e 3 0 4294967295 ACK 0 0 EN_CTL 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_PCS_OUT 2 0x330f 2 0 4294967295 ACK 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_ADAPT_ACK 2 0x3310 2 0 4294967295 RX_ADAPT_ACK 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_ADAPT_FOM 2 0x3311 2 0 4294967295 RX_ADAPT_FOM 0 7 RESERVED_15_8 8 15 ixDPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_TXPRE_DIR 2 0x3312 2 0 4294967295 RX_TXPRE_DIR 0 1 RESERVED_15_2 2 15 ixDPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_TXMAIN_DIR 2 0x3313 2 0 4294967295 RX_TXMAIN_DIR 0 1 RESERVED_15_2 2 15 ixDPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_TXPOST_DIR 2 0x3314 2 0 4294967295 RX_TXPOST_DIR 0 1 RESERVED_15_2 2 15 ixDPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_LANE_NUMBER 2 0x3315 2 0 4294967295 LANE_NUMBER 0 3 RESERVED_15_4 4 15 ixDPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RESERVED_1 2 0x3316 1 0 4294967295 RESERVED_REG_1 0 15 ixDPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RESERVED_2 2 0x3317 1 0 4294967295 RESERVED_REG_2 0 15 ixDPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN 2 0x3318 16 0 4294967295 RX_RESET_ATE_OVRD_VAL 0 0 RX_RESET_ATE_OVRD_EN 1 1 TX_RESET_ATE_OVRD_VAL 2 2 TX_RESET_ATE_OVRD_EN 3 3 RX_REQ_ATE_OVRD_VAL 4 4 RX_REQ_ATE_OVRD_EN 5 5 TX_REQ_ATE_OVRD_VAL 6 6 TX_REQ_ATE_OVRD_EN 7 7 RX_ADAPT_AFE_EN_OVRD_VAL 8 8 RX_ADAPT_AFE_EN_OVRD_EN 9 9 RX_ADAPT_DFE_EN_OVRD_VAL 10 10 RX_ADAPT_DFE_EN_OVRD_EN 11 11 TX_DATA_EN_ATE_OVRD_VAL 12 12 TX_DATA_EN_ATE_OVRD_EN 13 13 RX_DATA_EN_ATE_OVRD_VAL 14 14 RX_DATA_EN_ATE_OVRD_EN 15 15 ixDPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN 2 0x3319 3 0 4294967295 RX_EQ_DELTA_IQ_OVRD_VAL 0 3 RX_EQ_DELTA_IQ_OVRD_EN 4 4 RESERVED_15_5 5 15 ixDPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN 2 0x331a 5 0 4294967295 RX_TERM_CTRL_OVRD_VAL 0 2 RX_TERM_CTRL_OVRD_EN 3 3 TX_TERM_CTRL_OVRD_VAL 4 6 TX_TERM_CTRL_OVRD_EN 7 7 RESERVED_15_8 8 15 ixDPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TXRX_TERM_CTRL_IN 2 0x331b 3 0 4294967295 RX_TERM_CTRL 0 2 TX_TERM_CTRL 3 5 RESERVED_15_6 6 15 ixDPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT_1 2 0x331c 2 0 4294967295 RX_CLK_EN 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_EQ_OVRD_IN_1 2 0x331d 4 0 4294967295 RX_EQ_AFE_GAIN_OVRD_VAL 0 3 RX_EQ_ATT_LVL_OVRD_VAL 4 6 RX_EQ_OVRD_EN 7 7 RESERVED_15_8 8 15 ixDPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_EQ_OVRD_IN_2 2 0x331e 3 0 4294967295 RX_EQ_DFE_TAP1_OVRD_VAL 0 7 RX_EQ_CTLE_BOOST_OVRD_VAL 8 12 RESERVED_15_13 13 15 ixDPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_PH2_CAL 2 0x331f 4 0 4294967295 PH2_CAL_ACK_VAL 0 0 PH2_CAL_REQ_VAL 1 1 PH2_CAL_REQ_OVRD_VAL 2 2 RESERVED_15_3 3 15 ixDPCSSYS_CR0_RAWLANE3_DIG_FSM_FSM_OVRD_CTL 2 0x3320 5 0 4294967295 FSM_JMP_ADDR 0 11 FSM_JMP_EN 12 12 FSM_CMD_START 13 13 FSM_OVRD_EN 14 14 FSM_BREAK 15 15 ixDPCSSYS_CR0_RAWLANE3_DIG_FSM_MEM_ADDR_MON 2 0x3321 1 0 4294967295 MEM_ADDR 0 15 ixDPCSSYS_CR0_RAWLANE3_DIG_FSM_STATUS_MON 2 0x3322 8 0 4294967295 STATE 0 4 CMD_RDY 5 5 ALU_OVFLW 6 6 ALU_RES_EQ0 7 7 WAIT_CNT_EQ0 8 8 WRMSK_DISABLED 9 9 RDMSK_DISABLED 10 10 RESERVED_15_11 11 15 ixDPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_RX_STARTUP_CAL 2 0x3323 2 0 4294967295 FAST_RX_STARTUP_CAL 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_RX_ADAPT 2 0x3324 2 0 4294967295 FAST_RX_ADAPT 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_RX_AFE_CAL 2 0x3325 2 0 4294967295 FAST_RX_AFE_CAL 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_RX_DFE_CAL 2 0x3326 2 0 4294967295 FAST_RX_DFE_CAL 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_RX_BYPASS_CAL 2 0x3327 2 0 4294967295 FAST_RX_BYPASS_CAL 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_RX_REFLVL_CAL 2 0x3328 2 0 4294967295 FAST_RX_REFLVL_CAL 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_RX_IQ_CAL 2 0x3329 2 0 4294967295 FAST_RX_IQ_CAL 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_RX_AFE_ADAPT 2 0x332a 2 0 4294967295 FAST_RX_AFE_ADAPT 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_RX_DFE_ADAPT 2 0x332b 2 0 4294967295 FAST_RX_DFE_ADAPT 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_SUP 2 0x332c 2 0 4294967295 FAST_SUP 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_TX_CMN_MODE 2 0x332d 2 0 4294967295 FAST_TX_CMN_MODE 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_TX_RXDET 2 0x332e 2 0 4294967295 FAST_TX_RXDET 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_RX_PWRUP 2 0x332f 2 0 4294967295 FAST_RX_PWRUP 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_RX_VCO_WAIT 2 0x3330 2 0 4294967295 FAST_RX_VCO_WAIT 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_RX_VCO_CAL 2 0x3331 2 0 4294967295 FAST_RX_VCO_CAL 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR0_RAWLANE3_DIG_FSM_CMNCAL_MPLL_STATUS 2 0x3332 3 0 4294967295 CMNCAL_MPLL_INIT 0 0 CMNCAL_MPLL_DONE 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_RX_CONT_CAL_ADAPT 2 0x3333 2 0 4294967295 FAST_RX_CONT_CAL_ADAPT 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_RX_CONT_ADAPT 2 0x3334 2 0 4294967295 FAST_RX_CONT_ADAPT 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_RX_CONT_DATA_CAL 2 0x3335 2 0 4294967295 FAST_RX_CONT_DATA_CAL 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_RX_CONT_PHASE_CAL 2 0x3336 2 0 4294967295 FAST_RX_CONT_PHASE_CAL 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_RX_CONT_AFE_CAL 2 0x3337 2 0 4294967295 FAST_RX_CONT_AFE_CAL 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_FLAGS 2 0x3338 12 0 4294967295 TX_FAST_DCC_CAL 0 0 RX_FAST_DCC_CAL 1 1 RX_FAST_VPHUD_CAL 2 2 RX_FAST_VREF_CAL 3 3 RX_FAST_SIGDET_CAL 4 4 RESERVED_2 5 7 TX_FAST_CONT_DCC_CAL 8 8 RX_FAST_CONT_DCC_CAL 9 9 RX_FAST_CONT_VPHUD_CAL 10 10 RX_FAST_CONT_VREF_CAL 11 11 RESERVED_1 12 14 TX_SKIP_SUP_CAL 15 15 ixDPCSSYS_CR0_RAWLANE3_DIG_FSM_CR_LOCK 2 0x3339 3 0 4294967295 CR_REG_LOCK 0 0 CR_MEM_LOCK 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR0_RAWLANE3_DIG_FSM_TX_DCC_FLAGS 2 0x333a 4 0 4294967295 RATE 0 0 DIV 1 1 MPLL 2 2 RESERVED_15_3 3 15 ixDPCSSYS_CR0_RAWLANE3_DIG_FSM_TX_DCC_STATUS 2 0x333b 2 0 4294967295 FLAG 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR0_RAWLANE3_DIG_FSM_OCLA 2 0x333c 4 0 4294967295 PC_EN 0 0 REG_BANK1_EN 1 1 REG_BANK2_EN 2 2 RESERVED_15_3 3 15 ixDPCSSYS_CR0_RAWLANE3_DIG_FSM_TX_EQ_UPDATE_FLAG 2 0x333d 2 0 4294967295 TX_EQ_UPDATE_FLAG 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR0_RAWLANE3_DIG_FSM_CMNCAL_RCAL_STATUS 2 0x333e 3 0 4294967295 CMNCAL_RCAL_INIT 0 0 CMNCAL_RCAL_DONE 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR0_RAWLANE3_DIG_FSM_RX_IQ_PHASE_OFFSET 2 0x333f 2 0 4294967295 RX_IQ_PHASE_OFFSET 0 3 RESERVED_15_4 4 15 ixDPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_RESET_RTN_REQ 2 0x3340 2 0 4294967295 RESET_RTN_REQ 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_RX_RESET_IRQ 2 0x3341 2 0 4294967295 RX_RESET 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_RX_REQ_IRQ 2 0x3342 2 0 4294967295 RX_REQ 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_RX_RATE_IRQ 2 0x3343 2 0 4294967295 RX_RATE_IRQ 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_RX_PSTATE_IRQ 2 0x3344 2 0 4294967295 RX_PSTATE_IRQ 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ 2 0x3345 2 0 4294967295 RX_ADAPT_REQ_IRQ 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ 2 0x3346 2 0 4294967295 RX_ADAPT_DIS_IRQ 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_RX_RESET_IRQ_CLR 2 0x3347 2 0 4294967295 RX_RESET_IRQ_CLR 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_RX_REQ_IRQ_CLR 2 0x3348 2 0 4294967295 RX_REQ_IRQ_CLR 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_RX_RATE_IRQ_CLR 2 0x3349 2 0 4294967295 RX_RATE_IRQ_CLR 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR 2 0x334a 2 0 4294967295 RX_PSTATE_IRQ_CLR 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR 2 0x334b 2 0 4294967295 RX_ADAPT_REQ_IRQ_CLR 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR 2 0x334c 2 0 4294967295 RX_ADAPT_DIS_IRQ_CLR 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK 2 0x334d 12 0 4294967295 RX_REQ_IRQ_MSK 0 0 RX_RATE_IRQ_MSK 1 1 RX_PSTATE_IRQ_MSK 2 2 RX_ADAPT_REQ_IRQ_MSK 3 3 RX_ADAPT_DIS_IRQ_MSK 4 4 RX_RESET_IRQ_MSK 5 5 LANE_XCVR_MODE_IRQ_MSK 6 6 RX_PH2_CAL_REQ_IRQ_MSK 7 7 RX_PH2_CAL_DIS_IRQ_MSK 8 8 LANE_RX2TX_SER_LB_EN_IRQ_MSK 9 9 DCC_ONDMD_IRQ_MSK 10 10 RESERVED_15_11 11 15 ixDPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK_2 2 0x334e 3 0 4294967295 TX_RESET_IRQ_MSK 0 0 TX_REQ_IRQ_MSK 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ 2 0x334f 2 0 4294967295 LANE_XCVR_MODE_IRQ 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR 2 0x3350 2 0 4294967295 LANE_XCVR_MODE_IRQ_CLR 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ 2 0x3351 2 0 4294967295 RX_PH2_CAL_REQ_IRQ 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ 2 0x3352 2 0 4294967295 RX_PH2_CAL_DIS_IRQ 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR 2 0x3353 2 0 4294967295 RX_PH2_CAL_REQ_IRQ_CLR 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR 2 0x3354 2 0 4294967295 RX_PH2_CAL_DIS_IRQ_CLR 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ 2 0x3355 2 0 4294967295 LANE_RX2TX_SER_LB_EN_IRQ 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR 2 0x3356 2 0 4294967295 LANE_RX2TX_SER_LB_EN_IRQ_CLR 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_DCC_ONDMD_IRQ 2 0x3357 2 0 4294967295 IRQ 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_TX_RESET_IRQ 2 0x3358 2 0 4294967295 TX_RESET 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_TX_REQ_IRQ 2 0x3359 2 0 4294967295 TX_REQ 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_TX_RESET_IRQ_CLR 2 0x335a 2 0 4294967295 TX_RESET_IRQ_CLR 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_TX_REQ_IRQ_CLR 2 0x335b 2 0 4294967295 TX_REQ_IRQ_CLR 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_LANE_OVRD_IN 2 0x3360 4 0 4294967295 LANE_MPLLA_EN_IN 0 0 LANE_MPLLB_EN_IN 1 1 LANE_OVRD_EN 2 2 RESERVED_15_3 3 15 ixDPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_LANE_OVRD_OUT 2 0x3361 4 0 4294967295 LANE_MPLLA_EN_OUT 0 0 LANE_MPLLB_EN_OUT 1 1 LANE_OVRD_EN 2 2 RESERVED_15_3 3 15 ixDPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_SUP_OVRD_IN 2 0x3362 4 0 4294967295 MPLLA_STATE 0 0 MPLLB_STATE 1 1 SUP_STATE_OVRD_EN 2 2 RESERVED_15_3 3 15 ixDPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_SUP_PMA_IN 2 0x3363 3 0 4294967295 MPLLA_STATE 0 0 MPLLB_STATE 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT 2 0x3364 16 0 4294967295 TX_REQ_OVRD_VAL 0 0 TX_REQ_OVRD_EN 1 1 TX_RESET_OVRD_VAL 2 2 TX_RESET_OVRD_EN 3 3 TX_BEACON_EN_OVRD_VAL 4 4 TX_BEACON_EN_OVRD_EN 5 5 TX_ASYNC_DRV_EN_OVRD_VAL 6 6 TX_ASYNC_DRV_EN_OVRD_EN 7 7 TX_ASYNC_EN_OVRD_VAL 8 8 TX_ASYNC_EN_OVRD_EN 9 9 TX_DWORD_CLK_SYNC_OVRD_VAL 10 10 TX_DWORD_CLK_SYNC_OVRD_EN 11 11 LANE_TX2RX_SER_LB_EN_OVRD_VAL 12 12 LANE_TX2RX_SER_LB_EN_OVRD_EN 13 13 TX_PMA_DATA_EN_OVRD_VAL_R 14 14 TX_PMA_DATA_EN_OVRD_EN_R 15 15 ixDPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_TX_PMA_IN 2 0x3365 2 0 4294967295 ACK 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT 2 0x3366 9 0 4294967295 RX_REQ_OVRD_VAL 0 0 RX_REQ_OVRD_EN 1 1 RX_RESET_OVRD_VAL 2 2 RX_RESET_OVRD_EN 3 3 LANE_RX2TX_PAR_LB_EN_OVRD_VAL 4 4 LANE_RX2TX_PAR_LB_EN_OVRD_EN 5 5 RX_PMA_DATA_EN_OVRD_VAL_R 6 6 RX_PMA_DATA_EN_OVRD_EN_R 7 7 RESERVED_15_8 8 15 ixDPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_RX_PMA_IN 2 0x3367 2 0 4294967295 ACK 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_LANE_RTUNE_CTL 2 0x3368 2 0 4294967295 LANE_RTUNE_REQ 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_SUP_PMA_IN_1 2 0x3369 2 0 4294967295 RTUNE_ACK 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_IN 2 0x336a 9 0 4294967295 RX_PMA_PWM_WORD_CLK_R 0 0 RX_PMA_PWM_WORD_CLK_OVRD_EN 1 1 RX_PMA_PWM_DATA_R 2 2 RX_PMA_PWM_DATA_OVRD_EN 3 3 RX_PMA_PWM_CLK_R 4 4 RX_PMA_PWM_CLK_OVRD_EN 5 5 RX_PMA_TERM_CTL_R 6 7 RX_PMA_TERM_CTL_OVRD_EN 8 8 RESERVED_15_9 9 15 ixDPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_OUT 2 0x336b 7 0 4294967295 RX_PMA_PWM_EN 0 0 RX_PMA_PWM_EN_OVRD_EN 1 1 RX_PMA_PWM_CLK_SEL 2 3 RX_PMA_PWM_CLK_SEL_OVRD_EN 4 4 RX_PMA_ASYNC_EN 5 5 RX_PMA_ASYNC_EN_OVRD_EN 6 6 RESERVED_15_7 7 15 ixDPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_RX_ADAPT_OVRD_OUT 2 0x336c 3 0 4294967295 RX_PMA_IQ_PHASE_ADJUST_MAP_OVRD_VAL 0 6 RX_PMA_IQ_PHASE_ADJUST_MAP_OVRD_EN 7 7 RESERVED_15_8 8 15 ixDPCSSYS_CR0_RAWLANE3_DIG_TX_CTL_TX_FSM_CTL 2 0x3380 6 0 4294967295 TX_WAIT_MPLL_OFF_TIME 0 6 TX_P2_ALLOW_RXDET 7 7 TX_P1_ALLOW_RXDET 8 8 TX_P0S_ALLOW_RXDET 9 9 TX_P0_ALLOW_RXDET 10 10 RESERVED_15_11 11 15 ixDPCSSYS_CR0_RAWLANE3_DIG_TX_CTL_TX_CLK_CTL 2 0x3381 4 0 4294967295 TX_CLK_EN 0 0 TX_CLK_SEL 1 4 ASYNC_BEACON_WAIT_TIME 5 10 RESERVED_15_11 11 15 ixDPCSSYS_CR0_RAWLANE3_DIG_TX_CTL_TX_DCC_CONT_STATUS 2 0x3382 2 0 4294967295 ENABLE 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR0_RAWLANE3_DIG_TX_CTL_OCLA 2 0x3383 2 0 4294967295 FSM_EN 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR0_RAWLANE3_DIG_TX_CTL_UPCS_OCLA 2 0x3384 3 0 4294967295 DATA_EN 0 1 CLK_EN 2 2 RESERVED_15_3 3 15 ixDPCSSYS_CR0_RAWLANE3_DIG_RX_CTL_RX_FSM_CTL 2 0x33a0 3 0 4294967295 EN_RX_CTL_FSM 0 0 RATE_CHG_IN_P1 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR0_RAWLANE3_DIG_RX_CTL_RX_LOS_MASK_CTL 2 0x33a1 2 0 4294967295 RX_LOS_MASK_CNT 0 8 RESERVED_15_9 9 15 ixDPCSSYS_CR0_RAWLANE3_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL 2 0x33a2 2 0 4294967295 RX_DATA_EN_OVRD_CNT 0 4 INT_REF_TRCK_CNT 5 15 ixDPCSSYS_CR0_RAWLANE3_DIG_RX_CTL_OFFCAN_CONT_STATUS 2 0x33a3 2 0 4294967295 ENABLE 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR0_RAWLANE3_DIG_RX_CTL_ADAPT_CONT_STATUS 2 0x33a4 2 0 4294967295 ENABLE 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR0_RAWLANE3_DIG_RX_CTL_UPCS_OCLA 2 0x33a5 3 0 4294967295 DATA_EN 0 2 CLK_EN 3 3 RESERVED_15_4 4 15 ixDPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN 2 0x33c0 11 0 4294967295 RATE_OVRD_VAL 0 1 RATE_OVRD_EN 2 2 WIDTH_OVRD_VAL 3 4 WIDTH_OVRD_EN 5 5 PSTATE_OVRD_VAL 6 7 PSTATE_OVRD_EN 8 8 LPD_OVRD_VAL 9 9 LPD_OVRD_EN 10 10 LANE_RX2TX_PAR_LB_EN_OVRD_VAL 11 11 LANE_RX2TX_PAR_LB_EN_OVRD_EN 12 12 RESERVED_15_13 13 15 ixDPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN 2 0x33c1 12 0 4294967295 PSTATE 0 1 LPD 2 2 WIDTH 3 4 RATE 5 7 MPLLB_SEL 8 8 MPLL_EN 9 9 OVRD_EN 10 10 MSTR_MPLLA_STATE 11 11 MSTR_MPLLB_STATE 12 12 MSTR_MPLL_OVRD_EN 13 13 TX_ASYNC_EN_OVR_VAL 14 14 TX_ASYNC_EN_OVR_EN 15 15 ixDPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1 2 0x33c2 13 0 4294967295 DETRX_REQ_OVRD_VAL 0 0 DETRX_REQ_OVRD_EN 1 1 VBOOST_EN_OVRD_VAL 2 2 VBOOST_EN_OVRD_EN 3 3 IBOOST_LVL_OVRD_VAL 4 7 IBOOST_LVL_OVRD_EN 8 8 TX_BEACON_EN_OVR_VAL 9 9 TX_BEACON_EN_OVR_EN 10 10 LANE_TX2RX_SER_LB_EN_OVRD_VAL 11 11 LANE_TX2RX_SER_LB_EN_OVRD_EN 12 12 TX_ASYNC_DATA_OVRD_VAL 13 13 TX_ASYNC_DATA_OVRD_EN 14 14 RESERVED_15_15 15 15 ixDPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_MASTER_MPLL_LOOP 2 0x33c3 3 0 4294967295 MPLLB_LOOP_EN 0 0 MPLLA_LOOP_EN 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1 2 0x33c4 11 0 4294967295 RESERVED 0 1 RX_LOS_LFPS_EN_OVRD_VAL 2 2 RX_LOS_LFPS_EN_OVRD_EN 3 3 RX_LOS_THRSHLD_OVRD_VAL 4 6 RX_LOS_THRSHLD_OVRD_EN 7 7 ADAPT_REQ 8 8 ADAPT_REQ_OVRD_EN 9 9 ADAPT_CONT 10 10 OFFCAN_CONT 11 11 CONT_OVRD_EN 12 12 RESERVED_15_13 13 15 ixDPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_2 2 0x33c5 4 0 4294967295 VCO_LD_VAL_OVRD 0 12 VCO_LD_VAL_OVRD_EN 13 13 VCO_LOWFREQ_VAL_OVRD 14 14 VCO_LOWFREQ_VAL_OVRD_EN 15 15 ixDPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_3 2 0x33c6 3 0 4294967295 REF_LD_VAL_OVRD 0 6 REF_LD_VAL_OVRD_EN 7 7 RESERVED_15_8 8 15 ixDPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT_2 2 0x33c7 3 0 4294967295 RX_VALID 0 0 RX_VALID_OVRD_EN 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_2 2 0x33c8 7 0 4294967295 LANE_TX2RX_SER_LB_EN_OVRD_VAL 0 0 LANE_TX2RX_SER_LB_EN_OVRD_EN 1 1 TX_DATA_EN_OVRD_VAL_R 2 2 TX_DATA_EN_OVRD_EN_R 3 3 TX_ASYNC_DATA_OVRD_VAL_R 4 4 TX_ASYNC_DATA_OVRD_EN_R 5 5 RESERVED_15_6 6 15 ixDPCSSYS_CR0_RAWAONLANE0_DIG_AFE_ATT_IDAC_OFST 2 0x4000 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR0_RAWAONLANE0_DIG_AFE_CTLE_IDAC_OFST 2 0x4001 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR0_RAWAONLANE0_DIG_RX_ADPT_IQ 2 0x4002 2 0 4294967295 IQ_ADPT_VAL 0 6 RESERVED_15_7 7 15 ixDPCSSYS_CR0_RAWAONLANE0_DIG_RX_ADAPT_FOM 2 0x4003 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR0_RAWAONLANE0_DIG_DFE_SUMMER_ODD_IDAC_OFST 2 0x4004 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR0_RAWAONLANE0_DIG_DFE_PHASE_EVEN_VDAC_OFST 2 0x4005 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR0_RAWAONLANE0_DIG_DFE_PHASE_ODD_VDAC_OFST 2 0x4006 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR0_RAWAONLANE0_DIG_DFE_EVEN_REF_LVL 2 0x4007 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR0_RAWAONLANE0_DIG_DFE_ODD_REF_LVL 2 0x4008 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR0_RAWAONLANE0_DIG_RX_PHSADJ_LIN 2 0x4009 2 0 4294967295 DATA 0 0 RESERVED_15_5 5 15 ixDPCSSYS_CR0_RAWAONLANE0_DIG_RX_PHSADJ_MAP 2 0x400a 2 0 4294967295 DATA 0 0 RESERVED_15_5 5 15 ixDPCSSYS_CR0_RAWAONLANE0_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST 2 0x400b 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR0_RAWAONLANE0_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST 2 0x400c 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR0_RAWAONLANE0_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST 2 0x400d 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR0_RAWAONLANE0_DIG_DFE_DATA_ODD_LOW_VDAC_OFST 2 0x400e 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR0_RAWAONLANE0_DIG_DFE_BYPASS_EVEN_VDAC_OFST 2 0x400f 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR0_RAWAONLANE0_DIG_DFE_BYPASS_ODD_VDAC_OFST 2 0x4010 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR0_RAWAONLANE0_DIG_DFE_ERROR_EVEN_VDAC_OFST 2 0x4011 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR0_RAWAONLANE0_DIG_DFE_ERROR_ODD_VDAC_OFST 2 0x4012 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR0_RAWAONLANE0_DIG_RX_IQ_PHASE_ADJUST 2 0x4013 2 0 4294967295 DATA 0 0 RESERVED_15_7 7 15 ixDPCSSYS_CR0_RAWAONLANE0_DIG_MPLLA_COARSE_TUNE 2 0x4014 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR0_RAWAONLANE0_DIG_MPLLB_COARSE_TUNE 2 0x4015 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR0_RAWAONLANE0_DIG_INIT_PWRUP_DONE 2 0x4016 3 0 4294967295 DATA 0 0 PH2_PWRUP_DONE 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR0_RAWAONLANE0_DIG_RX_ADPT_ATT 2 0x4017 2 0 4294967295 ATT_ADPT_VAL 0 7 RESERVED_15_8 8 15 ixDPCSSYS_CR0_RAWAONLANE0_DIG_RX_ADPT_VGA 2 0x4018 2 0 4294967295 VGA_ADPT_VAL 0 9 RESERVED_15_10 10 15 ixDPCSSYS_CR0_RAWAONLANE0_DIG_RX_ADPT_CTLE 2 0x4019 3 0 4294967295 CTLE_BOOST_ADPT_VAL 0 9 CTLE_POLE_ADPT_VAL 10 12 RESERVED_15_13 13 15 ixDPCSSYS_CR0_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP1 2 0x401a 2 0 4294967295 DFE_TAP1_ADPT_VAL 0 12 RESERVED_15_13 13 15 ixDPCSSYS_CR0_RAWAONLANE0_DIG_RX_ADAPT_DONE 2 0x401b 2 0 4294967295 DATA 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR0_RAWAONLANE0_DIG_FAST_FLAGS 2 0x401c 16 0 4294967295 FAST_RX_STARTUP_CAL 0 0 FAST_RX_ADAPT 1 1 FAST_RX_AFE_CAL 2 2 FAST_RX_DFE_CAL 3 3 FAST_RX_BYPASS_CAL 4 4 FAST_RX_REFLVL_CAL 5 5 FAST_RX_IQ_CAL 6 6 FAST_RX_AFE_ADAPT 7 7 FAST_RX_DFE_ADAPT 8 8 FAST_SUP 9 9 FAST_TX_CMN_MODE 10 10 FAST_TX_RXDET 11 11 FAST_RX_PWRUP 12 12 FAST_RX_VCO_WAIT 13 13 FAST_RX_VCO_CAL 14 14 RESERVED_15_15 15 15 ixDPCSSYS_CR0_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP2 2 0x401d 2 0 4294967295 DFE_TAP2_ADPT_VAL 0 11 RESERVED_15_12 12 15 ixDPCSSYS_CR0_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP3 2 0x401e 2 0 4294967295 DFE_TAP3_ADPT_VAL 0 11 RESERVED_15_12 12 15 ixDPCSSYS_CR0_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP4 2 0x401f 2 0 4294967295 DFE_TAP4_ADPT_VAL 0 11 RESERVED_15_12 12 15 ixDPCSSYS_CR0_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP5 2 0x4020 2 0 4294967295 DFE_TAP5_ADPT_VAL 0 11 RESERVED_15_12 12 15 ixDPCSSYS_CR0_RAWAONLANE0_DIG_RX_SLICER_CTRL_EVEN 2 0x4021 2 0 4294967295 RX_ANA_SLICER_CTRL_E 0 3 RESERVED_15_4 4 15 ixDPCSSYS_CR0_RAWAONLANE0_DIG_RX_SLICER_CTRL_ODD 2 0x4022 2 0 4294967295 RX_ANA_SLICER_CTRL_O 0 3 RESERVED_15_4 4 15 ixDPCSSYS_CR0_RAWAONLANE0_DIG_LANE_CMNCAL_MPLL_STATUS 2 0x4023 3 0 4294967295 LANE_CMNCAL_MPLL_INIT 0 0 LANE_CMNCAL_MPLL_DONE 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR0_RAWAONLANE0_DIG_ADPT_CTL_0 2 0x4024 1 0 4294967295 VAL 0 15 ixDPCSSYS_CR0_RAWAONLANE0_DIG_ADPT_CTL_1 2 0x4025 1 0 4294967295 VAL 0 15 ixDPCSSYS_CR0_RAWAONLANE0_DIG_ADPT_CTL_2 2 0x4026 1 0 4294967295 VAL 0 15 ixDPCSSYS_CR0_RAWAONLANE0_DIG_ADPT_CTL_3 2 0x4027 1 0 4294967295 VAL 0 15 ixDPCSSYS_CR0_RAWAONLANE0_DIG_ADPT_CTL_4 2 0x4028 1 0 4294967295 VAL 0 15 ixDPCSSYS_CR0_RAWAONLANE0_DIG_ADPT_CTL_5 2 0x4029 1 0 4294967295 VAL 0 15 ixDPCSSYS_CR0_RAWAONLANE0_DIG_ADPT_CTL_6 2 0x402a 1 0 4294967295 VAL 0 15 ixDPCSSYS_CR0_RAWAONLANE0_DIG_ADPT_CTL_7 2 0x402b 1 0 4294967295 VAL 0 15 ixDPCSSYS_CR0_RAWAONLANE0_DIG_MPLL_DISABLE 2 0x402c 3 0 4294967295 LANE_MPLLA_DISABLE 0 0 LANE_MPLLB_DISABLE 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR0_RAWAONLANE0_DIG_FAST_FLAGS_2 2 0x402d 16 0 4294967295 FAST_RX_CONT_CAL_ADAPT 0 0 FAST_RX_CONT_ADAPT 1 1 FAST_RX_CONT_DATA_CAL 2 2 FAST_RX_CONT_PHASE_CAL 3 3 FAST_RX_CONT_AFE_CAL 4 4 FAST_TX_CONT_DCC_CAL 5 5 FAST_RX_CONT_DCC_CAL 6 6 FAST_RX_CONT_VPHUD_CAL 7 7 FAST_RX_CONT_VREF_CAL 8 8 FAST_TX_DCC_CAL 9 9 FAST_RX_DCC_CAL 10 10 FAST_RX_VPHUD_CAL 11 11 FAST_RX_VREF_CAL 12 12 SKIP_TX_RTUNE_CAL 13 13 FAST_RX_SIGDET_CAL 14 14 RESERVED_15_15 15 15 ixDPCSSYS_CR0_RAWAONLANE0_DIG_LANE_CMNCAL_RCAL_STATUS 2 0x402e 3 0 4294967295 LANE_CMNCAL_RCAL_INIT 0 0 LANE_CMNCAL_RCAL_DONE 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR0_RAWAONLANE0_DIG_TXRX_OVRD_IN 2 0x402f 5 0 4294967295 RX_DISABLE_OVRD_VAL 0 0 RX_DISABLE_OVRD_EN 1 1 TX_DISABLE_OVRD_VAL 2 2 TX_DISABLE_OVRD_EN 3 3 RESERVED_15_4 4 15 ixDPCSSYS_CR0_RAWAONLANE0_DIG_RX_LOS_MASK_CTL 2 0x4030 2 0 4294967295 RX_LOS_MASK_CNT 0 8 RESERVED_15_9 9 15 ixDPCSSYS_CR0_RAWAONLANE0_DIG_RX_SIGDET_FILT_CTRL 2 0x4031 5 0 4294967295 ISOLATE_SIGDET_HF 0 0 RX_SIGDEF_HF_FILT_OVR_DIS 1 1 RX_SIGDEF_HF_FILT_OVR 2 2 RX_SIGDET_LF_OUT_FILT_EN 3 3 RESERVED_15_4 4 15 ixDPCSSYS_CR0_RAWAONLANE0_DIG_STATS 2 0x4032 3 0 4294967295 RX_VREFGEN_MASTER 0 0 RX_PMA_SQ_OUT 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR0_RAWAONLANE0_DIG_RX_OVRD_OUT_1 2 0x4033 11 0 4294967295 RX_PMA_SQ_CTRL_TRESH_OVRD_VAL 0 2 RX_PMA_SQ_CTRL_TRESH_OVRD_EN 3 3 RX_PMA_SQ_CTRL_RESP_OVRD_VAL 4 5 RX_PMA_SQ_CTRL_RESP_OVRD_EN 6 6 RX_PMA_SQ_WEAKKEEP_OVRD_VAL 7 7 RX_PMA_SQ_WEAKKEEP_OVRD_EN 8 8 RX_PMA_SQ_INV_POLARITY_OVRD_VAL 9 9 RX_PMA_SQ_INV_POLARITY_OVRD_EN 10 10 RX_PMA_SQ_EN_OVRD_VAL 11 11 RX_PMA_SQ_EN_OVRD_EN 12 12 RESERVED_15_13 13 15 ixDPCSSYS_CR0_RAWAONLANE0_DIG_RX_OVRD_OUT_2 2 0x4034 9 0 4294967295 RX_PMA_VREFGEN_EN_OVRD_VAL 0 0 RX_PMA_VREFGEN_EN_OVRD_EN 1 1 RX_SQ_OUT_OVRD_VAL 2 2 RX_SQ_OUT_OVRD_EN 3 3 RX_PMA_TERM_ACDC_OVRD_VAL 4 4 RX_PMA_TERM_ACDC_OVRD_EN 5 5 RX_PMA_TERM_EN_OVRD_VAL 6 6 RX_PMA_TERM_EN_OVRD_EN 7 7 RESERVED_15_8 8 15 ixDPCSSYS_CR0_RAWAONLANE0_DIG_RX_OVRD_OUT_3 2 0x4035 7 0 4294967295 RX_PMA_SIGDET_LF_FILTER_EN_OVRD_VAL 0 0 RX_PMA_SIGDET_LF_FILTER_EN_OVRD_EN 1 1 RX_PMA_SIGDET_LF_EN_OVRD_VAL 2 2 RX_PMA_SIGDET_LF_EN_OVRD_EN 3 3 RX_PMA_SIGDET_HF_EN_OVRD_VAL 4 4 RX_PMA_SIGDET_HF_EN_OVRD_EN 5 5 RESERVED_15_6 6 15 ixDPCSSYS_CR0_RAWAONLANE0_DIG_RX_SIGDET_CAL 2 0x4036 4 0 4294967295 RX_PMA_SIGDET_LF_THRESHOLD 0 2 RX_PMA_SIGDET_HF_THRESHOLD 3 5 RX_PMA_SIGDET_CAL_EN 6 6 RESERVED_15_7 7 15 ixDPCSSYS_CR0_RAWAONLANE0_DIG_RX_SIGDET_HF_CODE 2 0x4037 2 0 4294967295 RX_PMA_SIGDET_HF_CAL_TUNE 0 5 RESERVED_15_6 6 15 ixDPCSSYS_CR0_RAWAONLANE0_DIG_RX_SIGDET_LF_CODE 2 0x4038 2 0 4294967295 RX_PMA_SIGDET_LF_CAL_TUNE 0 5 RESERVED_15_6 6 15 ixDPCSSYS_CR0_RAWAONLANE0_DIG_RX_VREFGEN_EN 2 0x4039 2 0 4294967295 PULL_UP 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR0_RAWAONLANE0_DIG_CAL_IOFF_CODE 2 0x403a 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR0_RAWAONLANE0_DIG_CAL_ICONST_CODE 2 0x403b 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR0_RAWAONLANE0_DIG_CAL_VREFGEN_CODE 2 0x403c 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR0_RAWAONLANE0_DIG_RX_DCC_CAL_ICM_CODE_0 2 0x403d 2 0 4294967295 RX_DCC_CAL_ICM_CODE 0 9 RESERVED_15_10 10 15 ixDPCSSYS_CR0_RAWAONLANE0_DIG_RX_DCC_CAL_IDF_CODE_0 2 0x403e 2 0 4294967295 RX_DCC_CAL_IDF_CODE 0 9 RESERVED_15_10 10 15 ixDPCSSYS_CR0_RAWAONLANE0_DIG_RX_DCC_CAL_QCM_CODE_0 2 0x403f 2 0 4294967295 RX_DCC_CAL_QCM_CODE 0 9 RESERVED_15_10 10 15 ixDPCSSYS_CR0_RAWAONLANE0_DIG_RX_DCC_CAL_QDF_CODE_0 2 0x4040 2 0 4294967295 RX_DCC_CAL_QDF_CODE 0 9 RESERVED_15_10 10 15 ixDPCSSYS_CR0_RAWAONLANE0_DIG_RX_DCC_CAL_ICM_CODE_1 2 0x4041 2 0 4294967295 RX_DCC_CAL_ICM_CODE 0 9 RESERVED_15_10 10 15 ixDPCSSYS_CR0_RAWAONLANE0_DIG_RX_DCC_CAL_IDF_CODE_1 2 0x4042 2 0 4294967295 RX_DCC_CAL_IDF_CODE 0 9 RESERVED_15_10 10 15 ixDPCSSYS_CR0_RAWAONLANE0_DIG_RX_DCC_CAL_QCM_CODE_1 2 0x4043 2 0 4294967295 RX_DCC_CAL_QCM_CODE 0 9 RESERVED_15_10 10 15 ixDPCSSYS_CR0_RAWAONLANE0_DIG_RX_DCC_CAL_QDF_CODE_1 2 0x4044 2 0 4294967295 RX_DCC_CAL_QDF_CODE 0 9 RESERVED_15_10 10 15 ixDPCSSYS_CR0_RAWAONLANE0_DIG_TX_DCC_BANK_ADDR 2 0x4045 1 0 4294967295 ADDR 0 15 ixDPCSSYS_CR0_RAWAONLANE0_DIG_TX_DCC_BANK_DATA 2 0x4046 1 0 4294967295 DATA 0 15 ixDPCSSYS_CR0_RAWAONLANE0_DIG_TX_DCC_CONT 2 0x4047 2 0 4294967295 EN 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR0_RAWAONLANE0_DIG_MPLL_BG_CTL 2 0x4048 3 0 4294967295 MPLL_STATE_WAIT 0 0 MPLL_STATE_DLY_EN 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR0_RAWAONLANE0_DIG_SIGDET_OUT_OVRD 2 0x4049 5 0 4294967295 RX_SIGDET_HF_OUT_OVRD_VAL 0 0 RX_SIGDET_HF_OUT_OVRD_EN 1 1 RX_SIGDET_LF_OUT_OVRD_VAL 2 2 RX_SIGDET_LF_OUT_OVRD_EN 3 3 RESERVED_15_4 4 15 ixDPCSSYS_CR0_RAWAONLANE0_DIG_SIGDET_OUT_IN 2 0x404a 3 0 4294967295 RX_SIGDET_HF_OUT_OVRD_VAL 0 0 RX_SIGDET_LF_OUT_OVRD_VAL 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR0_RAWAONLANE0_DIG_FW_MM_CONFIG 2 0x404b 1 0 4294967295 DATA 0 0 ixDPCSSYS_CR0_RAWAONLANE0_DIG_FW_ADPT_CONFIG 2 0x404c 2 0 4294967295 REF_LVL_ADPT 0 7 FW_CONFIG 8 15 ixDPCSSYS_CR0_RAWAONLANE0_DIG_FW_CALIB_CONFIG 2 0x404d 1 0 4294967295 FW_CALIB 0 15 ixDPCSSYS_CR0_RAWAONLANE0_DIG_LANE_XCVR_MODE_OVRD_IN 2 0x404e 3 0 4294967295 LANE_XCVR_MODE_OVRD_VAL 0 1 LANE_XCVR_MODE_OVRD_EN 2 2 RESERVED_15_3 3 15 ixDPCSSYS_CR0_RAWAONLANE0_DIG_LANE_XCVR_MODE_IN 2 0x404f 2 0 4294967295 LANE_XCVR_MODE 0 1 RESERVED_15_2 2 15 ixDPCSSYS_CR0_RAWAONLANE0_DIG_RX_SIGDET_CONFIG 2 0x4050 4 0 4294967295 RX_SIGDET_HF_FILTER_COUNTER 0 4 RX_SIGDET_LF_FILTER_COUNTER 5 9 RX_SIGDET_LF_HOLD 10 10 RESERVED_15_11 11 15 ixDPCSSYS_CR0_RAWAONLANE0_DIG_TX_DCC_CONFIG 2 0x4051 1 0 4294967295 DATA 0 0 ixDPCSSYS_CR0_RAWAONLANE1_DIG_AFE_ATT_IDAC_OFST 2 0x4100 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR0_RAWAONLANE1_DIG_AFE_CTLE_IDAC_OFST 2 0x4101 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR0_RAWAONLANE1_DIG_RX_ADPT_IQ 2 0x4102 2 0 4294967295 IQ_ADPT_VAL 0 6 RESERVED_15_7 7 15 ixDPCSSYS_CR0_RAWAONLANE1_DIG_RX_ADAPT_FOM 2 0x4103 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR0_RAWAONLANE1_DIG_DFE_SUMMER_ODD_IDAC_OFST 2 0x4104 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR0_RAWAONLANE1_DIG_DFE_PHASE_EVEN_VDAC_OFST 2 0x4105 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR0_RAWAONLANE1_DIG_DFE_PHASE_ODD_VDAC_OFST 2 0x4106 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR0_RAWAONLANE1_DIG_DFE_EVEN_REF_LVL 2 0x4107 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR0_RAWAONLANE1_DIG_DFE_ODD_REF_LVL 2 0x4108 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR0_RAWAONLANE1_DIG_RX_PHSADJ_LIN 2 0x4109 2 0 4294967295 DATA 0 0 RESERVED_15_5 5 15 ixDPCSSYS_CR0_RAWAONLANE1_DIG_RX_PHSADJ_MAP 2 0x410a 2 0 4294967295 DATA 0 0 RESERVED_15_5 5 15 ixDPCSSYS_CR0_RAWAONLANE1_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST 2 0x410b 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR0_RAWAONLANE1_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST 2 0x410c 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR0_RAWAONLANE1_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST 2 0x410d 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR0_RAWAONLANE1_DIG_DFE_DATA_ODD_LOW_VDAC_OFST 2 0x410e 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR0_RAWAONLANE1_DIG_DFE_BYPASS_EVEN_VDAC_OFST 2 0x410f 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR0_RAWAONLANE1_DIG_DFE_BYPASS_ODD_VDAC_OFST 2 0x4110 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR0_RAWAONLANE1_DIG_DFE_ERROR_EVEN_VDAC_OFST 2 0x4111 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR0_RAWAONLANE1_DIG_DFE_ERROR_ODD_VDAC_OFST 2 0x4112 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR0_RAWAONLANE1_DIG_RX_IQ_PHASE_ADJUST 2 0x4113 2 0 4294967295 DATA 0 0 RESERVED_15_7 7 15 ixDPCSSYS_CR0_RAWAONLANE1_DIG_MPLLA_COARSE_TUNE 2 0x4114 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR0_RAWAONLANE1_DIG_MPLLB_COARSE_TUNE 2 0x4115 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR0_RAWAONLANE1_DIG_INIT_PWRUP_DONE 2 0x4116 3 0 4294967295 DATA 0 0 PH2_PWRUP_DONE 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR0_RAWAONLANE1_DIG_RX_ADPT_ATT 2 0x4117 2 0 4294967295 ATT_ADPT_VAL 0 7 RESERVED_15_8 8 15 ixDPCSSYS_CR0_RAWAONLANE1_DIG_RX_ADPT_VGA 2 0x4118 2 0 4294967295 VGA_ADPT_VAL 0 9 RESERVED_15_10 10 15 ixDPCSSYS_CR0_RAWAONLANE1_DIG_RX_ADPT_CTLE 2 0x4119 3 0 4294967295 CTLE_BOOST_ADPT_VAL 0 9 CTLE_POLE_ADPT_VAL 10 12 RESERVED_15_13 13 15 ixDPCSSYS_CR0_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP1 2 0x411a 2 0 4294967295 DFE_TAP1_ADPT_VAL 0 12 RESERVED_15_13 13 15 ixDPCSSYS_CR0_RAWAONLANE1_DIG_RX_ADAPT_DONE 2 0x411b 2 0 4294967295 DATA 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR0_RAWAONLANE1_DIG_FAST_FLAGS 2 0x411c 16 0 4294967295 FAST_RX_STARTUP_CAL 0 0 FAST_RX_ADAPT 1 1 FAST_RX_AFE_CAL 2 2 FAST_RX_DFE_CAL 3 3 FAST_RX_BYPASS_CAL 4 4 FAST_RX_REFLVL_CAL 5 5 FAST_RX_IQ_CAL 6 6 FAST_RX_AFE_ADAPT 7 7 FAST_RX_DFE_ADAPT 8 8 FAST_SUP 9 9 FAST_TX_CMN_MODE 10 10 FAST_TX_RXDET 11 11 FAST_RX_PWRUP 12 12 FAST_RX_VCO_WAIT 13 13 FAST_RX_VCO_CAL 14 14 RESERVED_15_15 15 15 ixDPCSSYS_CR0_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP2 2 0x411d 2 0 4294967295 DFE_TAP2_ADPT_VAL 0 11 RESERVED_15_12 12 15 ixDPCSSYS_CR0_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP3 2 0x411e 2 0 4294967295 DFE_TAP3_ADPT_VAL 0 11 RESERVED_15_12 12 15 ixDPCSSYS_CR0_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP4 2 0x411f 2 0 4294967295 DFE_TAP4_ADPT_VAL 0 11 RESERVED_15_12 12 15 ixDPCSSYS_CR0_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP5 2 0x4120 2 0 4294967295 DFE_TAP5_ADPT_VAL 0 11 RESERVED_15_12 12 15 ixDPCSSYS_CR0_RAWAONLANE1_DIG_RX_SLICER_CTRL_EVEN 2 0x4121 2 0 4294967295 RX_ANA_SLICER_CTRL_E 0 3 RESERVED_15_4 4 15 ixDPCSSYS_CR0_RAWAONLANE1_DIG_RX_SLICER_CTRL_ODD 2 0x4122 2 0 4294967295 RX_ANA_SLICER_CTRL_O 0 3 RESERVED_15_4 4 15 ixDPCSSYS_CR0_RAWAONLANE1_DIG_LANE_CMNCAL_MPLL_STATUS 2 0x4123 3 0 4294967295 LANE_CMNCAL_MPLL_INIT 0 0 LANE_CMNCAL_MPLL_DONE 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR0_RAWAONLANE1_DIG_ADPT_CTL_0 2 0x4124 1 0 4294967295 VAL 0 15 ixDPCSSYS_CR0_RAWAONLANE1_DIG_ADPT_CTL_1 2 0x4125 1 0 4294967295 VAL 0 15 ixDPCSSYS_CR0_RAWAONLANE1_DIG_ADPT_CTL_2 2 0x4126 1 0 4294967295 VAL 0 15 ixDPCSSYS_CR0_RAWAONLANE1_DIG_ADPT_CTL_3 2 0x4127 1 0 4294967295 VAL 0 15 ixDPCSSYS_CR0_RAWAONLANE1_DIG_ADPT_CTL_4 2 0x4128 1 0 4294967295 VAL 0 15 ixDPCSSYS_CR0_RAWAONLANE1_DIG_ADPT_CTL_5 2 0x4129 1 0 4294967295 VAL 0 15 ixDPCSSYS_CR0_RAWAONLANE1_DIG_ADPT_CTL_6 2 0x412a 1 0 4294967295 VAL 0 15 ixDPCSSYS_CR0_RAWAONLANE1_DIG_ADPT_CTL_7 2 0x412b 1 0 4294967295 VAL 0 15 ixDPCSSYS_CR0_RAWAONLANE1_DIG_MPLL_DISABLE 2 0x412c 3 0 4294967295 LANE_MPLLA_DISABLE 0 0 LANE_MPLLB_DISABLE 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR0_RAWAONLANE1_DIG_FAST_FLAGS_2 2 0x412d 16 0 4294967295 FAST_RX_CONT_CAL_ADAPT 0 0 FAST_RX_CONT_ADAPT 1 1 FAST_RX_CONT_DATA_CAL 2 2 FAST_RX_CONT_PHASE_CAL 3 3 FAST_RX_CONT_AFE_CAL 4 4 FAST_TX_CONT_DCC_CAL 5 5 FAST_RX_CONT_DCC_CAL 6 6 FAST_RX_CONT_VPHUD_CAL 7 7 FAST_RX_CONT_VREF_CAL 8 8 FAST_TX_DCC_CAL 9 9 FAST_RX_DCC_CAL 10 10 FAST_RX_VPHUD_CAL 11 11 FAST_RX_VREF_CAL 12 12 SKIP_TX_RTUNE_CAL 13 13 FAST_RX_SIGDET_CAL 14 14 RESERVED_15_15 15 15 ixDPCSSYS_CR0_RAWAONLANE1_DIG_LANE_CMNCAL_RCAL_STATUS 2 0x412e 3 0 4294967295 LANE_CMNCAL_RCAL_INIT 0 0 LANE_CMNCAL_RCAL_DONE 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR0_RAWAONLANE1_DIG_TXRX_OVRD_IN 2 0x412f 5 0 4294967295 RX_DISABLE_OVRD_VAL 0 0 RX_DISABLE_OVRD_EN 1 1 TX_DISABLE_OVRD_VAL 2 2 TX_DISABLE_OVRD_EN 3 3 RESERVED_15_4 4 15 ixDPCSSYS_CR0_RAWAONLANE1_DIG_RX_LOS_MASK_CTL 2 0x4130 2 0 4294967295 RX_LOS_MASK_CNT 0 8 RESERVED_15_9 9 15 ixDPCSSYS_CR0_RAWAONLANE1_DIG_RX_SIGDET_FILT_CTRL 2 0x4131 5 0 4294967295 ISOLATE_SIGDET_HF 0 0 RX_SIGDEF_HF_FILT_OVR_DIS 1 1 RX_SIGDEF_HF_FILT_OVR 2 2 RX_SIGDET_LF_OUT_FILT_EN 3 3 RESERVED_15_4 4 15 ixDPCSSYS_CR0_RAWAONLANE1_DIG_STATS 2 0x4132 3 0 4294967295 RX_VREFGEN_MASTER 0 0 RX_PMA_SQ_OUT 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR0_RAWAONLANE1_DIG_RX_OVRD_OUT_1 2 0x4133 11 0 4294967295 RX_PMA_SQ_CTRL_TRESH_OVRD_VAL 0 2 RX_PMA_SQ_CTRL_TRESH_OVRD_EN 3 3 RX_PMA_SQ_CTRL_RESP_OVRD_VAL 4 5 RX_PMA_SQ_CTRL_RESP_OVRD_EN 6 6 RX_PMA_SQ_WEAKKEEP_OVRD_VAL 7 7 RX_PMA_SQ_WEAKKEEP_OVRD_EN 8 8 RX_PMA_SQ_INV_POLARITY_OVRD_VAL 9 9 RX_PMA_SQ_INV_POLARITY_OVRD_EN 10 10 RX_PMA_SQ_EN_OVRD_VAL 11 11 RX_PMA_SQ_EN_OVRD_EN 12 12 RESERVED_15_13 13 15 ixDPCSSYS_CR0_RAWAONLANE1_DIG_RX_OVRD_OUT_2 2 0x4134 9 0 4294967295 RX_PMA_VREFGEN_EN_OVRD_VAL 0 0 RX_PMA_VREFGEN_EN_OVRD_EN 1 1 RX_SQ_OUT_OVRD_VAL 2 2 RX_SQ_OUT_OVRD_EN 3 3 RX_PMA_TERM_ACDC_OVRD_VAL 4 4 RX_PMA_TERM_ACDC_OVRD_EN 5 5 RX_PMA_TERM_EN_OVRD_VAL 6 6 RX_PMA_TERM_EN_OVRD_EN 7 7 RESERVED_15_8 8 15 ixDPCSSYS_CR0_RAWAONLANE1_DIG_RX_OVRD_OUT_3 2 0x4135 7 0 4294967295 RX_PMA_SIGDET_LF_FILTER_EN_OVRD_VAL 0 0 RX_PMA_SIGDET_LF_FILTER_EN_OVRD_EN 1 1 RX_PMA_SIGDET_LF_EN_OVRD_VAL 2 2 RX_PMA_SIGDET_LF_EN_OVRD_EN 3 3 RX_PMA_SIGDET_HF_EN_OVRD_VAL 4 4 RX_PMA_SIGDET_HF_EN_OVRD_EN 5 5 RESERVED_15_6 6 15 ixDPCSSYS_CR0_RAWAONLANE1_DIG_RX_SIGDET_CAL 2 0x4136 4 0 4294967295 RX_PMA_SIGDET_LF_THRESHOLD 0 2 RX_PMA_SIGDET_HF_THRESHOLD 3 5 RX_PMA_SIGDET_CAL_EN 6 6 RESERVED_15_7 7 15 ixDPCSSYS_CR0_RAWAONLANE1_DIG_RX_SIGDET_HF_CODE 2 0x4137 2 0 4294967295 RX_PMA_SIGDET_HF_CAL_TUNE 0 5 RESERVED_15_6 6 15 ixDPCSSYS_CR0_RAWAONLANE1_DIG_RX_SIGDET_LF_CODE 2 0x4138 2 0 4294967295 RX_PMA_SIGDET_LF_CAL_TUNE 0 5 RESERVED_15_6 6 15 ixDPCSSYS_CR0_RAWAONLANE1_DIG_RX_VREFGEN_EN 2 0x4139 2 0 4294967295 PULL_UP 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR0_RAWAONLANE1_DIG_CAL_IOFF_CODE 2 0x413a 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR0_RAWAONLANE1_DIG_CAL_ICONST_CODE 2 0x413b 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR0_RAWAONLANE1_DIG_CAL_VREFGEN_CODE 2 0x413c 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR0_RAWAONLANE1_DIG_RX_DCC_CAL_ICM_CODE_0 2 0x413d 2 0 4294967295 RX_DCC_CAL_ICM_CODE 0 9 RESERVED_15_10 10 15 ixDPCSSYS_CR0_RAWAONLANE1_DIG_RX_DCC_CAL_IDF_CODE_0 2 0x413e 2 0 4294967295 RX_DCC_CAL_IDF_CODE 0 9 RESERVED_15_10 10 15 ixDPCSSYS_CR0_RAWAONLANE1_DIG_RX_DCC_CAL_QCM_CODE_0 2 0x413f 2 0 4294967295 RX_DCC_CAL_QCM_CODE 0 9 RESERVED_15_10 10 15 ixDPCSSYS_CR0_RAWAONLANE1_DIG_RX_DCC_CAL_QDF_CODE_0 2 0x4140 2 0 4294967295 RX_DCC_CAL_QDF_CODE 0 9 RESERVED_15_10 10 15 ixDPCSSYS_CR0_RAWAONLANE1_DIG_RX_DCC_CAL_ICM_CODE_1 2 0x4141 2 0 4294967295 RX_DCC_CAL_ICM_CODE 0 9 RESERVED_15_10 10 15 ixDPCSSYS_CR0_RAWAONLANE1_DIG_RX_DCC_CAL_IDF_CODE_1 2 0x4142 2 0 4294967295 RX_DCC_CAL_IDF_CODE 0 9 RESERVED_15_10 10 15 ixDPCSSYS_CR0_RAWAONLANE1_DIG_RX_DCC_CAL_QCM_CODE_1 2 0x4143 2 0 4294967295 RX_DCC_CAL_QCM_CODE 0 9 RESERVED_15_10 10 15 ixDPCSSYS_CR0_RAWAONLANE1_DIG_RX_DCC_CAL_QDF_CODE_1 2 0x4144 2 0 4294967295 RX_DCC_CAL_QDF_CODE 0 9 RESERVED_15_10 10 15 ixDPCSSYS_CR0_RAWAONLANE1_DIG_TX_DCC_BANK_ADDR 2 0x4145 1 0 4294967295 ADDR 0 15 ixDPCSSYS_CR0_RAWAONLANE1_DIG_TX_DCC_BANK_DATA 2 0x4146 1 0 4294967295 DATA 0 15 ixDPCSSYS_CR0_RAWAONLANE1_DIG_TX_DCC_CONT 2 0x4147 2 0 4294967295 EN 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR0_RAWAONLANE1_DIG_MPLL_BG_CTL 2 0x4148 3 0 4294967295 MPLL_STATE_WAIT 0 0 MPLL_STATE_DLY_EN 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR0_RAWAONLANE1_DIG_SIGDET_OUT_OVRD 2 0x4149 5 0 4294967295 RX_SIGDET_HF_OUT_OVRD_VAL 0 0 RX_SIGDET_HF_OUT_OVRD_EN 1 1 RX_SIGDET_LF_OUT_OVRD_VAL 2 2 RX_SIGDET_LF_OUT_OVRD_EN 3 3 RESERVED_15_4 4 15 ixDPCSSYS_CR0_RAWAONLANE1_DIG_SIGDET_OUT_IN 2 0x414a 3 0 4294967295 RX_SIGDET_HF_OUT_OVRD_VAL 0 0 RX_SIGDET_LF_OUT_OVRD_VAL 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR0_RAWAONLANE1_DIG_FW_MM_CONFIG 2 0x414b 1 0 4294967295 DATA 0 0 ixDPCSSYS_CR0_RAWAONLANE1_DIG_FW_ADPT_CONFIG 2 0x414c 2 0 4294967295 REF_LVL_ADPT 0 7 FW_CONFIG 8 15 ixDPCSSYS_CR0_RAWAONLANE1_DIG_FW_CALIB_CONFIG 2 0x414d 1 0 4294967295 FW_CALIB 0 15 ixDPCSSYS_CR0_RAWAONLANE1_DIG_LANE_XCVR_MODE_OVRD_IN 2 0x414e 3 0 4294967295 LANE_XCVR_MODE_OVRD_VAL 0 1 LANE_XCVR_MODE_OVRD_EN 2 2 RESERVED_15_3 3 15 ixDPCSSYS_CR0_RAWAONLANE1_DIG_LANE_XCVR_MODE_IN 2 0x414f 2 0 4294967295 LANE_XCVR_MODE 0 1 RESERVED_15_2 2 15 ixDPCSSYS_CR0_RAWAONLANE1_DIG_RX_SIGDET_CONFIG 2 0x4150 4 0 4294967295 RX_SIGDET_HF_FILTER_COUNTER 0 4 RX_SIGDET_LF_FILTER_COUNTER 5 9 RX_SIGDET_LF_HOLD 10 10 RESERVED_15_11 11 15 ixDPCSSYS_CR0_RAWAONLANE1_DIG_TX_DCC_CONFIG 2 0x4151 1 0 4294967295 DATA 0 0 ixDPCSSYS_CR0_RAWAONLANE2_DIG_AFE_ATT_IDAC_OFST 2 0x4200 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR0_RAWAONLANE2_DIG_AFE_CTLE_IDAC_OFST 2 0x4201 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR0_RAWAONLANE2_DIG_RX_ADPT_IQ 2 0x4202 2 0 4294967295 IQ_ADPT_VAL 0 6 RESERVED_15_7 7 15 ixDPCSSYS_CR0_RAWAONLANE2_DIG_RX_ADAPT_FOM 2 0x4203 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR0_RAWAONLANE2_DIG_DFE_SUMMER_ODD_IDAC_OFST 2 0x4204 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR0_RAWAONLANE2_DIG_DFE_PHASE_EVEN_VDAC_OFST 2 0x4205 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR0_RAWAONLANE2_DIG_DFE_PHASE_ODD_VDAC_OFST 2 0x4206 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR0_RAWAONLANE2_DIG_DFE_EVEN_REF_LVL 2 0x4207 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR0_RAWAONLANE2_DIG_DFE_ODD_REF_LVL 2 0x4208 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR0_RAWAONLANE2_DIG_RX_PHSADJ_LIN 2 0x4209 2 0 4294967295 DATA 0 0 RESERVED_15_5 5 15 ixDPCSSYS_CR0_RAWAONLANE2_DIG_RX_PHSADJ_MAP 2 0x420a 2 0 4294967295 DATA 0 0 RESERVED_15_5 5 15 ixDPCSSYS_CR0_RAWAONLANE2_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST 2 0x420b 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR0_RAWAONLANE2_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST 2 0x420c 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR0_RAWAONLANE2_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST 2 0x420d 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR0_RAWAONLANE2_DIG_DFE_DATA_ODD_LOW_VDAC_OFST 2 0x420e 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR0_RAWAONLANE2_DIG_DFE_BYPASS_EVEN_VDAC_OFST 2 0x420f 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR0_RAWAONLANE2_DIG_DFE_BYPASS_ODD_VDAC_OFST 2 0x4210 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR0_RAWAONLANE2_DIG_DFE_ERROR_EVEN_VDAC_OFST 2 0x4211 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR0_RAWAONLANE2_DIG_DFE_ERROR_ODD_VDAC_OFST 2 0x4212 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR0_RAWAONLANE2_DIG_RX_IQ_PHASE_ADJUST 2 0x4213 2 0 4294967295 DATA 0 0 RESERVED_15_7 7 15 ixDPCSSYS_CR0_RAWAONLANE2_DIG_MPLLA_COARSE_TUNE 2 0x4214 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR0_RAWAONLANE2_DIG_MPLLB_COARSE_TUNE 2 0x4215 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR0_RAWAONLANE2_DIG_INIT_PWRUP_DONE 2 0x4216 3 0 4294967295 DATA 0 0 PH2_PWRUP_DONE 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR0_RAWAONLANE2_DIG_RX_ADPT_ATT 2 0x4217 2 0 4294967295 ATT_ADPT_VAL 0 7 RESERVED_15_8 8 15 ixDPCSSYS_CR0_RAWAONLANE2_DIG_RX_ADPT_VGA 2 0x4218 2 0 4294967295 VGA_ADPT_VAL 0 9 RESERVED_15_10 10 15 ixDPCSSYS_CR0_RAWAONLANE2_DIG_RX_ADPT_CTLE 2 0x4219 3 0 4294967295 CTLE_BOOST_ADPT_VAL 0 9 CTLE_POLE_ADPT_VAL 10 12 RESERVED_15_13 13 15 ixDPCSSYS_CR0_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP1 2 0x421a 2 0 4294967295 DFE_TAP1_ADPT_VAL 0 12 RESERVED_15_13 13 15 ixDPCSSYS_CR0_RAWAONLANE2_DIG_RX_ADAPT_DONE 2 0x421b 2 0 4294967295 DATA 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR0_RAWAONLANE2_DIG_FAST_FLAGS 2 0x421c 16 0 4294967295 FAST_RX_STARTUP_CAL 0 0 FAST_RX_ADAPT 1 1 FAST_RX_AFE_CAL 2 2 FAST_RX_DFE_CAL 3 3 FAST_RX_BYPASS_CAL 4 4 FAST_RX_REFLVL_CAL 5 5 FAST_RX_IQ_CAL 6 6 FAST_RX_AFE_ADAPT 7 7 FAST_RX_DFE_ADAPT 8 8 FAST_SUP 9 9 FAST_TX_CMN_MODE 10 10 FAST_TX_RXDET 11 11 FAST_RX_PWRUP 12 12 FAST_RX_VCO_WAIT 13 13 FAST_RX_VCO_CAL 14 14 RESERVED_15_15 15 15 ixDPCSSYS_CR0_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP2 2 0x421d 2 0 4294967295 DFE_TAP2_ADPT_VAL 0 11 RESERVED_15_12 12 15 ixDPCSSYS_CR0_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP3 2 0x421e 2 0 4294967295 DFE_TAP3_ADPT_VAL 0 11 RESERVED_15_12 12 15 ixDPCSSYS_CR0_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP4 2 0x421f 2 0 4294967295 DFE_TAP4_ADPT_VAL 0 11 RESERVED_15_12 12 15 ixDPCSSYS_CR0_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP5 2 0x4220 2 0 4294967295 DFE_TAP5_ADPT_VAL 0 11 RESERVED_15_12 12 15 ixDPCSSYS_CR0_RAWAONLANE2_DIG_RX_SLICER_CTRL_EVEN 2 0x4221 2 0 4294967295 RX_ANA_SLICER_CTRL_E 0 3 RESERVED_15_4 4 15 ixDPCSSYS_CR0_RAWAONLANE2_DIG_RX_SLICER_CTRL_ODD 2 0x4222 2 0 4294967295 RX_ANA_SLICER_CTRL_O 0 3 RESERVED_15_4 4 15 ixDPCSSYS_CR0_RAWAONLANE2_DIG_LANE_CMNCAL_MPLL_STATUS 2 0x4223 3 0 4294967295 LANE_CMNCAL_MPLL_INIT 0 0 LANE_CMNCAL_MPLL_DONE 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR0_RAWAONLANE2_DIG_ADPT_CTL_0 2 0x4224 1 0 4294967295 VAL 0 15 ixDPCSSYS_CR0_RAWAONLANE2_DIG_ADPT_CTL_1 2 0x4225 1 0 4294967295 VAL 0 15 ixDPCSSYS_CR0_RAWAONLANE2_DIG_ADPT_CTL_2 2 0x4226 1 0 4294967295 VAL 0 15 ixDPCSSYS_CR0_RAWAONLANE2_DIG_ADPT_CTL_3 2 0x4227 1 0 4294967295 VAL 0 15 ixDPCSSYS_CR0_RAWAONLANE2_DIG_ADPT_CTL_4 2 0x4228 1 0 4294967295 VAL 0 15 ixDPCSSYS_CR0_RAWAONLANE2_DIG_ADPT_CTL_5 2 0x4229 1 0 4294967295 VAL 0 15 ixDPCSSYS_CR0_RAWAONLANE2_DIG_ADPT_CTL_6 2 0x422a 1 0 4294967295 VAL 0 15 ixDPCSSYS_CR0_RAWAONLANE2_DIG_ADPT_CTL_7 2 0x422b 1 0 4294967295 VAL 0 15 ixDPCSSYS_CR0_RAWAONLANE2_DIG_MPLL_DISABLE 2 0x422c 3 0 4294967295 LANE_MPLLA_DISABLE 0 0 LANE_MPLLB_DISABLE 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR0_RAWAONLANE2_DIG_FAST_FLAGS_2 2 0x422d 16 0 4294967295 FAST_RX_CONT_CAL_ADAPT 0 0 FAST_RX_CONT_ADAPT 1 1 FAST_RX_CONT_DATA_CAL 2 2 FAST_RX_CONT_PHASE_CAL 3 3 FAST_RX_CONT_AFE_CAL 4 4 FAST_TX_CONT_DCC_CAL 5 5 FAST_RX_CONT_DCC_CAL 6 6 FAST_RX_CONT_VPHUD_CAL 7 7 FAST_RX_CONT_VREF_CAL 8 8 FAST_TX_DCC_CAL 9 9 FAST_RX_DCC_CAL 10 10 FAST_RX_VPHUD_CAL 11 11 FAST_RX_VREF_CAL 12 12 SKIP_TX_RTUNE_CAL 13 13 FAST_RX_SIGDET_CAL 14 14 RESERVED_15_15 15 15 ixDPCSSYS_CR0_RAWAONLANE2_DIG_LANE_CMNCAL_RCAL_STATUS 2 0x422e 3 0 4294967295 LANE_CMNCAL_RCAL_INIT 0 0 LANE_CMNCAL_RCAL_DONE 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR0_RAWAONLANE2_DIG_TXRX_OVRD_IN 2 0x422f 5 0 4294967295 RX_DISABLE_OVRD_VAL 0 0 RX_DISABLE_OVRD_EN 1 1 TX_DISABLE_OVRD_VAL 2 2 TX_DISABLE_OVRD_EN 3 3 RESERVED_15_4 4 15 ixDPCSSYS_CR0_RAWAONLANE2_DIG_RX_LOS_MASK_CTL 2 0x4230 2 0 4294967295 RX_LOS_MASK_CNT 0 8 RESERVED_15_9 9 15 ixDPCSSYS_CR0_RAWAONLANE2_DIG_RX_SIGDET_FILT_CTRL 2 0x4231 5 0 4294967295 ISOLATE_SIGDET_HF 0 0 RX_SIGDEF_HF_FILT_OVR_DIS 1 1 RX_SIGDEF_HF_FILT_OVR 2 2 RX_SIGDET_LF_OUT_FILT_EN 3 3 RESERVED_15_4 4 15 ixDPCSSYS_CR0_RAWAONLANE2_DIG_STATS 2 0x4232 3 0 4294967295 RX_VREFGEN_MASTER 0 0 RX_PMA_SQ_OUT 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR0_RAWAONLANE2_DIG_RX_OVRD_OUT_1 2 0x4233 11 0 4294967295 RX_PMA_SQ_CTRL_TRESH_OVRD_VAL 0 2 RX_PMA_SQ_CTRL_TRESH_OVRD_EN 3 3 RX_PMA_SQ_CTRL_RESP_OVRD_VAL 4 5 RX_PMA_SQ_CTRL_RESP_OVRD_EN 6 6 RX_PMA_SQ_WEAKKEEP_OVRD_VAL 7 7 RX_PMA_SQ_WEAKKEEP_OVRD_EN 8 8 RX_PMA_SQ_INV_POLARITY_OVRD_VAL 9 9 RX_PMA_SQ_INV_POLARITY_OVRD_EN 10 10 RX_PMA_SQ_EN_OVRD_VAL 11 11 RX_PMA_SQ_EN_OVRD_EN 12 12 RESERVED_15_13 13 15 ixDPCSSYS_CR0_RAWAONLANE2_DIG_RX_OVRD_OUT_2 2 0x4234 9 0 4294967295 RX_PMA_VREFGEN_EN_OVRD_VAL 0 0 RX_PMA_VREFGEN_EN_OVRD_EN 1 1 RX_SQ_OUT_OVRD_VAL 2 2 RX_SQ_OUT_OVRD_EN 3 3 RX_PMA_TERM_ACDC_OVRD_VAL 4 4 RX_PMA_TERM_ACDC_OVRD_EN 5 5 RX_PMA_TERM_EN_OVRD_VAL 6 6 RX_PMA_TERM_EN_OVRD_EN 7 7 RESERVED_15_8 8 15 ixDPCSSYS_CR0_RAWAONLANE2_DIG_RX_OVRD_OUT_3 2 0x4235 7 0 4294967295 RX_PMA_SIGDET_LF_FILTER_EN_OVRD_VAL 0 0 RX_PMA_SIGDET_LF_FILTER_EN_OVRD_EN 1 1 RX_PMA_SIGDET_LF_EN_OVRD_VAL 2 2 RX_PMA_SIGDET_LF_EN_OVRD_EN 3 3 RX_PMA_SIGDET_HF_EN_OVRD_VAL 4 4 RX_PMA_SIGDET_HF_EN_OVRD_EN 5 5 RESERVED_15_6 6 15 ixDPCSSYS_CR0_RAWAONLANE2_DIG_RX_SIGDET_CAL 2 0x4236 4 0 4294967295 RX_PMA_SIGDET_LF_THRESHOLD 0 2 RX_PMA_SIGDET_HF_THRESHOLD 3 5 RX_PMA_SIGDET_CAL_EN 6 6 RESERVED_15_7 7 15 ixDPCSSYS_CR0_RAWAONLANE2_DIG_RX_SIGDET_HF_CODE 2 0x4237 2 0 4294967295 RX_PMA_SIGDET_HF_CAL_TUNE 0 5 RESERVED_15_6 6 15 ixDPCSSYS_CR0_RAWAONLANE2_DIG_RX_SIGDET_LF_CODE 2 0x4238 2 0 4294967295 RX_PMA_SIGDET_LF_CAL_TUNE 0 5 RESERVED_15_6 6 15 ixDPCSSYS_CR0_RAWAONLANE2_DIG_RX_VREFGEN_EN 2 0x4239 2 0 4294967295 PULL_UP 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR0_RAWAONLANE2_DIG_CAL_IOFF_CODE 2 0x423a 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR0_RAWAONLANE2_DIG_CAL_ICONST_CODE 2 0x423b 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR0_RAWAONLANE2_DIG_CAL_VREFGEN_CODE 2 0x423c 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR0_RAWAONLANE2_DIG_RX_DCC_CAL_ICM_CODE_0 2 0x423d 2 0 4294967295 RX_DCC_CAL_ICM_CODE 0 9 RESERVED_15_10 10 15 ixDPCSSYS_CR0_RAWAONLANE2_DIG_RX_DCC_CAL_IDF_CODE_0 2 0x423e 2 0 4294967295 RX_DCC_CAL_IDF_CODE 0 9 RESERVED_15_10 10 15 ixDPCSSYS_CR0_RAWAONLANE2_DIG_RX_DCC_CAL_QCM_CODE_0 2 0x423f 2 0 4294967295 RX_DCC_CAL_QCM_CODE 0 9 RESERVED_15_10 10 15 ixDPCSSYS_CR0_RAWAONLANE2_DIG_RX_DCC_CAL_QDF_CODE_0 2 0x4240 2 0 4294967295 RX_DCC_CAL_QDF_CODE 0 9 RESERVED_15_10 10 15 ixDPCSSYS_CR0_RAWAONLANE2_DIG_RX_DCC_CAL_ICM_CODE_1 2 0x4241 2 0 4294967295 RX_DCC_CAL_ICM_CODE 0 9 RESERVED_15_10 10 15 ixDPCSSYS_CR0_RAWAONLANE2_DIG_RX_DCC_CAL_IDF_CODE_1 2 0x4242 2 0 4294967295 RX_DCC_CAL_IDF_CODE 0 9 RESERVED_15_10 10 15 ixDPCSSYS_CR0_RAWAONLANE2_DIG_RX_DCC_CAL_QCM_CODE_1 2 0x4243 2 0 4294967295 RX_DCC_CAL_QCM_CODE 0 9 RESERVED_15_10 10 15 ixDPCSSYS_CR0_RAWAONLANE2_DIG_RX_DCC_CAL_QDF_CODE_1 2 0x4244 2 0 4294967295 RX_DCC_CAL_QDF_CODE 0 9 RESERVED_15_10 10 15 ixDPCSSYS_CR0_RAWAONLANE2_DIG_TX_DCC_BANK_ADDR 2 0x4245 1 0 4294967295 ADDR 0 15 ixDPCSSYS_CR0_RAWAONLANE2_DIG_TX_DCC_BANK_DATA 2 0x4246 1 0 4294967295 DATA 0 15 ixDPCSSYS_CR0_RAWAONLANE2_DIG_TX_DCC_CONT 2 0x4247 2 0 4294967295 EN 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR0_RAWAONLANE2_DIG_MPLL_BG_CTL 2 0x4248 3 0 4294967295 MPLL_STATE_WAIT 0 0 MPLL_STATE_DLY_EN 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR0_RAWAONLANE2_DIG_SIGDET_OUT_OVRD 2 0x4249 5 0 4294967295 RX_SIGDET_HF_OUT_OVRD_VAL 0 0 RX_SIGDET_HF_OUT_OVRD_EN 1 1 RX_SIGDET_LF_OUT_OVRD_VAL 2 2 RX_SIGDET_LF_OUT_OVRD_EN 3 3 RESERVED_15_4 4 15 ixDPCSSYS_CR0_RAWAONLANE2_DIG_SIGDET_OUT_IN 2 0x424a 3 0 4294967295 RX_SIGDET_HF_OUT_OVRD_VAL 0 0 RX_SIGDET_LF_OUT_OVRD_VAL 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR0_RAWAONLANE2_DIG_FW_MM_CONFIG 2 0x424b 1 0 4294967295 DATA 0 0 ixDPCSSYS_CR0_RAWAONLANE2_DIG_FW_ADPT_CONFIG 2 0x424c 2 0 4294967295 REF_LVL_ADPT 0 7 FW_CONFIG 8 15 ixDPCSSYS_CR0_RAWAONLANE2_DIG_FW_CALIB_CONFIG 2 0x424d 1 0 4294967295 FW_CALIB 0 15 ixDPCSSYS_CR0_RAWAONLANE2_DIG_LANE_XCVR_MODE_OVRD_IN 2 0x424e 3 0 4294967295 LANE_XCVR_MODE_OVRD_VAL 0 1 LANE_XCVR_MODE_OVRD_EN 2 2 RESERVED_15_3 3 15 ixDPCSSYS_CR0_RAWAONLANE2_DIG_LANE_XCVR_MODE_IN 2 0x424f 2 0 4294967295 LANE_XCVR_MODE 0 1 RESERVED_15_2 2 15 ixDPCSSYS_CR0_RAWAONLANE2_DIG_RX_SIGDET_CONFIG 2 0x4250 4 0 4294967295 RX_SIGDET_HF_FILTER_COUNTER 0 4 RX_SIGDET_LF_FILTER_COUNTER 5 9 RX_SIGDET_LF_HOLD 10 10 RESERVED_15_11 11 15 ixDPCSSYS_CR0_RAWAONLANE2_DIG_TX_DCC_CONFIG 2 0x4251 1 0 4294967295 DATA 0 0 ixDPCSSYS_CR0_RAWAONLANE3_DIG_AFE_ATT_IDAC_OFST 2 0x4300 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR0_RAWAONLANE3_DIG_AFE_CTLE_IDAC_OFST 2 0x4301 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR0_RAWAONLANE3_DIG_RX_ADPT_IQ 2 0x4302 2 0 4294967295 IQ_ADPT_VAL 0 6 RESERVED_15_7 7 15 ixDPCSSYS_CR0_RAWAONLANE3_DIG_RX_ADAPT_FOM 2 0x4303 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR0_RAWAONLANE3_DIG_DFE_SUMMER_ODD_IDAC_OFST 2 0x4304 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR0_RAWAONLANE3_DIG_DFE_PHASE_EVEN_VDAC_OFST 2 0x4305 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR0_RAWAONLANE3_DIG_DFE_PHASE_ODD_VDAC_OFST 2 0x4306 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR0_RAWAONLANE3_DIG_DFE_EVEN_REF_LVL 2 0x4307 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR0_RAWAONLANE3_DIG_DFE_ODD_REF_LVL 2 0x4308 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR0_RAWAONLANE3_DIG_RX_PHSADJ_LIN 2 0x4309 2 0 4294967295 DATA 0 0 RESERVED_15_5 5 15 ixDPCSSYS_CR0_RAWAONLANE3_DIG_RX_PHSADJ_MAP 2 0x430a 2 0 4294967295 DATA 0 0 RESERVED_15_5 5 15 ixDPCSSYS_CR0_RAWAONLANE3_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST 2 0x430b 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR0_RAWAONLANE3_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST 2 0x430c 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR0_RAWAONLANE3_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST 2 0x430d 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR0_RAWAONLANE3_DIG_DFE_DATA_ODD_LOW_VDAC_OFST 2 0x430e 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR0_RAWAONLANE3_DIG_DFE_BYPASS_EVEN_VDAC_OFST 2 0x430f 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR0_RAWAONLANE3_DIG_DFE_BYPASS_ODD_VDAC_OFST 2 0x4310 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR0_RAWAONLANE3_DIG_DFE_ERROR_EVEN_VDAC_OFST 2 0x4311 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR0_RAWAONLANE3_DIG_DFE_ERROR_ODD_VDAC_OFST 2 0x4312 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR0_RAWAONLANE3_DIG_RX_IQ_PHASE_ADJUST 2 0x4313 2 0 4294967295 DATA 0 0 RESERVED_15_7 7 15 ixDPCSSYS_CR0_RAWAONLANE3_DIG_MPLLA_COARSE_TUNE 2 0x4314 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR0_RAWAONLANE3_DIG_MPLLB_COARSE_TUNE 2 0x4315 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR0_RAWAONLANE3_DIG_INIT_PWRUP_DONE 2 0x4316 3 0 4294967295 DATA 0 0 PH2_PWRUP_DONE 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR0_RAWAONLANE3_DIG_RX_ADPT_ATT 2 0x4317 2 0 4294967295 ATT_ADPT_VAL 0 7 RESERVED_15_8 8 15 ixDPCSSYS_CR0_RAWAONLANE3_DIG_RX_ADPT_VGA 2 0x4318 2 0 4294967295 VGA_ADPT_VAL 0 9 RESERVED_15_10 10 15 ixDPCSSYS_CR0_RAWAONLANE3_DIG_RX_ADPT_CTLE 2 0x4319 3 0 4294967295 CTLE_BOOST_ADPT_VAL 0 9 CTLE_POLE_ADPT_VAL 10 12 RESERVED_15_13 13 15 ixDPCSSYS_CR0_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP1 2 0x431a 2 0 4294967295 DFE_TAP1_ADPT_VAL 0 12 RESERVED_15_13 13 15 ixDPCSSYS_CR0_RAWAONLANE3_DIG_RX_ADAPT_DONE 2 0x431b 2 0 4294967295 DATA 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR0_RAWAONLANE3_DIG_FAST_FLAGS 2 0x431c 16 0 4294967295 FAST_RX_STARTUP_CAL 0 0 FAST_RX_ADAPT 1 1 FAST_RX_AFE_CAL 2 2 FAST_RX_DFE_CAL 3 3 FAST_RX_BYPASS_CAL 4 4 FAST_RX_REFLVL_CAL 5 5 FAST_RX_IQ_CAL 6 6 FAST_RX_AFE_ADAPT 7 7 FAST_RX_DFE_ADAPT 8 8 FAST_SUP 9 9 FAST_TX_CMN_MODE 10 10 FAST_TX_RXDET 11 11 FAST_RX_PWRUP 12 12 FAST_RX_VCO_WAIT 13 13 FAST_RX_VCO_CAL 14 14 RESERVED_15_15 15 15 ixDPCSSYS_CR0_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP2 2 0x431d 2 0 4294967295 DFE_TAP2_ADPT_VAL 0 11 RESERVED_15_12 12 15 ixDPCSSYS_CR0_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP3 2 0x431e 2 0 4294967295 DFE_TAP3_ADPT_VAL 0 11 RESERVED_15_12 12 15 ixDPCSSYS_CR0_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP4 2 0x431f 2 0 4294967295 DFE_TAP4_ADPT_VAL 0 11 RESERVED_15_12 12 15 ixDPCSSYS_CR0_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP5 2 0x4320 2 0 4294967295 DFE_TAP5_ADPT_VAL 0 11 RESERVED_15_12 12 15 ixDPCSSYS_CR0_RAWAONLANE3_DIG_RX_SLICER_CTRL_EVEN 2 0x4321 2 0 4294967295 RX_ANA_SLICER_CTRL_E 0 3 RESERVED_15_4 4 15 ixDPCSSYS_CR0_RAWAONLANE3_DIG_RX_SLICER_CTRL_ODD 2 0x4322 2 0 4294967295 RX_ANA_SLICER_CTRL_O 0 3 RESERVED_15_4 4 15 ixDPCSSYS_CR0_RAWAONLANE3_DIG_LANE_CMNCAL_MPLL_STATUS 2 0x4323 3 0 4294967295 LANE_CMNCAL_MPLL_INIT 0 0 LANE_CMNCAL_MPLL_DONE 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR0_RAWAONLANE3_DIG_ADPT_CTL_0 2 0x4324 1 0 4294967295 VAL 0 15 ixDPCSSYS_CR0_RAWAONLANE3_DIG_ADPT_CTL_1 2 0x4325 1 0 4294967295 VAL 0 15 ixDPCSSYS_CR0_RAWAONLANE3_DIG_ADPT_CTL_2 2 0x4326 1 0 4294967295 VAL 0 15 ixDPCSSYS_CR0_RAWAONLANE3_DIG_ADPT_CTL_3 2 0x4327 1 0 4294967295 VAL 0 15 ixDPCSSYS_CR0_RAWAONLANE3_DIG_ADPT_CTL_4 2 0x4328 1 0 4294967295 VAL 0 15 ixDPCSSYS_CR0_RAWAONLANE3_DIG_ADPT_CTL_5 2 0x4329 1 0 4294967295 VAL 0 15 ixDPCSSYS_CR0_RAWAONLANE3_DIG_ADPT_CTL_6 2 0x432a 1 0 4294967295 VAL 0 15 ixDPCSSYS_CR0_RAWAONLANE3_DIG_ADPT_CTL_7 2 0x432b 1 0 4294967295 VAL 0 15 ixDPCSSYS_CR0_RAWAONLANE3_DIG_MPLL_DISABLE 2 0x432c 3 0 4294967295 LANE_MPLLA_DISABLE 0 0 LANE_MPLLB_DISABLE 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR0_RAWAONLANE3_DIG_FAST_FLAGS_2 2 0x432d 16 0 4294967295 FAST_RX_CONT_CAL_ADAPT 0 0 FAST_RX_CONT_ADAPT 1 1 FAST_RX_CONT_DATA_CAL 2 2 FAST_RX_CONT_PHASE_CAL 3 3 FAST_RX_CONT_AFE_CAL 4 4 FAST_TX_CONT_DCC_CAL 5 5 FAST_RX_CONT_DCC_CAL 6 6 FAST_RX_CONT_VPHUD_CAL 7 7 FAST_RX_CONT_VREF_CAL 8 8 FAST_TX_DCC_CAL 9 9 FAST_RX_DCC_CAL 10 10 FAST_RX_VPHUD_CAL 11 11 FAST_RX_VREF_CAL 12 12 SKIP_TX_RTUNE_CAL 13 13 FAST_RX_SIGDET_CAL 14 14 RESERVED_15_15 15 15 ixDPCSSYS_CR0_RAWAONLANE3_DIG_LANE_CMNCAL_RCAL_STATUS 2 0x432e 3 0 4294967295 LANE_CMNCAL_RCAL_INIT 0 0 LANE_CMNCAL_RCAL_DONE 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR0_RAWAONLANE3_DIG_TXRX_OVRD_IN 2 0x432f 5 0 4294967295 RX_DISABLE_OVRD_VAL 0 0 RX_DISABLE_OVRD_EN 1 1 TX_DISABLE_OVRD_VAL 2 2 TX_DISABLE_OVRD_EN 3 3 RESERVED_15_4 4 15 ixDPCSSYS_CR0_RAWAONLANE3_DIG_RX_LOS_MASK_CTL 2 0x4330 2 0 4294967295 RX_LOS_MASK_CNT 0 8 RESERVED_15_9 9 15 ixDPCSSYS_CR0_RAWAONLANE3_DIG_RX_SIGDET_FILT_CTRL 2 0x4331 5 0 4294967295 ISOLATE_SIGDET_HF 0 0 RX_SIGDEF_HF_FILT_OVR_DIS 1 1 RX_SIGDEF_HF_FILT_OVR 2 2 RX_SIGDET_LF_OUT_FILT_EN 3 3 RESERVED_15_4 4 15 ixDPCSSYS_CR0_RAWAONLANE3_DIG_STATS 2 0x4332 3 0 4294967295 RX_VREFGEN_MASTER 0 0 RX_PMA_SQ_OUT 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR0_RAWAONLANE3_DIG_RX_OVRD_OUT_1 2 0x4333 11 0 4294967295 RX_PMA_SQ_CTRL_TRESH_OVRD_VAL 0 2 RX_PMA_SQ_CTRL_TRESH_OVRD_EN 3 3 RX_PMA_SQ_CTRL_RESP_OVRD_VAL 4 5 RX_PMA_SQ_CTRL_RESP_OVRD_EN 6 6 RX_PMA_SQ_WEAKKEEP_OVRD_VAL 7 7 RX_PMA_SQ_WEAKKEEP_OVRD_EN 8 8 RX_PMA_SQ_INV_POLARITY_OVRD_VAL 9 9 RX_PMA_SQ_INV_POLARITY_OVRD_EN 10 10 RX_PMA_SQ_EN_OVRD_VAL 11 11 RX_PMA_SQ_EN_OVRD_EN 12 12 RESERVED_15_13 13 15 ixDPCSSYS_CR0_RAWAONLANE3_DIG_RX_OVRD_OUT_2 2 0x4334 9 0 4294967295 RX_PMA_VREFGEN_EN_OVRD_VAL 0 0 RX_PMA_VREFGEN_EN_OVRD_EN 1 1 RX_SQ_OUT_OVRD_VAL 2 2 RX_SQ_OUT_OVRD_EN 3 3 RX_PMA_TERM_ACDC_OVRD_VAL 4 4 RX_PMA_TERM_ACDC_OVRD_EN 5 5 RX_PMA_TERM_EN_OVRD_VAL 6 6 RX_PMA_TERM_EN_OVRD_EN 7 7 RESERVED_15_8 8 15 ixDPCSSYS_CR0_RAWAONLANE3_DIG_RX_OVRD_OUT_3 2 0x4335 7 0 4294967295 RX_PMA_SIGDET_LF_FILTER_EN_OVRD_VAL 0 0 RX_PMA_SIGDET_LF_FILTER_EN_OVRD_EN 1 1 RX_PMA_SIGDET_LF_EN_OVRD_VAL 2 2 RX_PMA_SIGDET_LF_EN_OVRD_EN 3 3 RX_PMA_SIGDET_HF_EN_OVRD_VAL 4 4 RX_PMA_SIGDET_HF_EN_OVRD_EN 5 5 RESERVED_15_6 6 15 ixDPCSSYS_CR0_RAWAONLANE3_DIG_RX_SIGDET_CAL 2 0x4336 4 0 4294967295 RX_PMA_SIGDET_LF_THRESHOLD 0 2 RX_PMA_SIGDET_HF_THRESHOLD 3 5 RX_PMA_SIGDET_CAL_EN 6 6 RESERVED_15_7 7 15 ixDPCSSYS_CR0_RAWAONLANE3_DIG_RX_SIGDET_HF_CODE 2 0x4337 2 0 4294967295 RX_PMA_SIGDET_HF_CAL_TUNE 0 5 RESERVED_15_6 6 15 ixDPCSSYS_CR0_RAWAONLANE3_DIG_RX_SIGDET_LF_CODE 2 0x4338 2 0 4294967295 RX_PMA_SIGDET_LF_CAL_TUNE 0 5 RESERVED_15_6 6 15 ixDPCSSYS_CR0_RAWAONLANE3_DIG_RX_VREFGEN_EN 2 0x4339 2 0 4294967295 PULL_UP 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR0_RAWAONLANE3_DIG_CAL_IOFF_CODE 2 0x433a 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR0_RAWAONLANE3_DIG_CAL_ICONST_CODE 2 0x433b 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR0_RAWAONLANE3_DIG_CAL_VREFGEN_CODE 2 0x433c 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR0_RAWAONLANE3_DIG_RX_DCC_CAL_ICM_CODE_0 2 0x433d 2 0 4294967295 RX_DCC_CAL_ICM_CODE 0 9 RESERVED_15_10 10 15 ixDPCSSYS_CR0_RAWAONLANE3_DIG_RX_DCC_CAL_IDF_CODE_0 2 0x433e 2 0 4294967295 RX_DCC_CAL_IDF_CODE 0 9 RESERVED_15_10 10 15 ixDPCSSYS_CR0_RAWAONLANE3_DIG_RX_DCC_CAL_QCM_CODE_0 2 0x433f 2 0 4294967295 RX_DCC_CAL_QCM_CODE 0 9 RESERVED_15_10 10 15 ixDPCSSYS_CR0_RAWAONLANE3_DIG_RX_DCC_CAL_QDF_CODE_0 2 0x4340 2 0 4294967295 RX_DCC_CAL_QDF_CODE 0 9 RESERVED_15_10 10 15 ixDPCSSYS_CR0_RAWAONLANE3_DIG_RX_DCC_CAL_ICM_CODE_1 2 0x4341 2 0 4294967295 RX_DCC_CAL_ICM_CODE 0 9 RESERVED_15_10 10 15 ixDPCSSYS_CR0_RAWAONLANE3_DIG_RX_DCC_CAL_IDF_CODE_1 2 0x4342 2 0 4294967295 RX_DCC_CAL_IDF_CODE 0 9 RESERVED_15_10 10 15 ixDPCSSYS_CR0_RAWAONLANE3_DIG_RX_DCC_CAL_QCM_CODE_1 2 0x4343 2 0 4294967295 RX_DCC_CAL_QCM_CODE 0 9 RESERVED_15_10 10 15 ixDPCSSYS_CR0_RAWAONLANE3_DIG_RX_DCC_CAL_QDF_CODE_1 2 0x4344 2 0 4294967295 RX_DCC_CAL_QDF_CODE 0 9 RESERVED_15_10 10 15 ixDPCSSYS_CR0_RAWAONLANE3_DIG_TX_DCC_BANK_ADDR 2 0x4345 1 0 4294967295 ADDR 0 15 ixDPCSSYS_CR0_RAWAONLANE3_DIG_TX_DCC_BANK_DATA 2 0x4346 1 0 4294967295 DATA 0 15 ixDPCSSYS_CR0_RAWAONLANE3_DIG_TX_DCC_CONT 2 0x4347 2 0 4294967295 EN 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR0_RAWAONLANE3_DIG_MPLL_BG_CTL 2 0x4348 3 0 4294967295 MPLL_STATE_WAIT 0 0 MPLL_STATE_DLY_EN 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR0_RAWAONLANE3_DIG_SIGDET_OUT_OVRD 2 0x4349 5 0 4294967295 RX_SIGDET_HF_OUT_OVRD_VAL 0 0 RX_SIGDET_HF_OUT_OVRD_EN 1 1 RX_SIGDET_LF_OUT_OVRD_VAL 2 2 RX_SIGDET_LF_OUT_OVRD_EN 3 3 RESERVED_15_4 4 15 ixDPCSSYS_CR0_RAWAONLANE3_DIG_SIGDET_OUT_IN 2 0x434a 3 0 4294967295 RX_SIGDET_HF_OUT_OVRD_VAL 0 0 RX_SIGDET_LF_OUT_OVRD_VAL 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR0_RAWAONLANE3_DIG_FW_MM_CONFIG 2 0x434b 1 0 4294967295 DATA 0 0 ixDPCSSYS_CR0_RAWAONLANE3_DIG_FW_ADPT_CONFIG 2 0x434c 2 0 4294967295 REF_LVL_ADPT 0 7 FW_CONFIG 8 15 ixDPCSSYS_CR0_RAWAONLANE3_DIG_FW_CALIB_CONFIG 2 0x434d 1 0 4294967295 FW_CALIB 0 15 ixDPCSSYS_CR0_RAWAONLANE3_DIG_LANE_XCVR_MODE_OVRD_IN 2 0x434e 3 0 4294967295 LANE_XCVR_MODE_OVRD_VAL 0 1 LANE_XCVR_MODE_OVRD_EN 2 2 RESERVED_15_3 3 15 ixDPCSSYS_CR0_RAWAONLANE3_DIG_LANE_XCVR_MODE_IN 2 0x434f 2 0 4294967295 LANE_XCVR_MODE 0 1 RESERVED_15_2 2 15 ixDPCSSYS_CR0_RAWAONLANE3_DIG_RX_SIGDET_CONFIG 2 0x4350 4 0 4294967295 RX_SIGDET_HF_FILTER_COUNTER 0 4 RX_SIGDET_LF_FILTER_COUNTER 5 9 RX_SIGDET_LF_HOLD 10 10 RESERVED_15_11 11 15 ixDPCSSYS_CR0_RAWAONLANE3_DIG_TX_DCC_CONFIG 2 0x4351 1 0 4294967295 DATA 0 0 ixDPCSSYS_CR0_RAWAONLANEX_DIG_AFE_ATT_IDAC_OFST 2 0x7000 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR0_RAWAONLANEX_DIG_AFE_CTLE_IDAC_OFST 2 0x7001 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR0_RAWAONLANEX_DIG_RX_ADPT_IQ 2 0x7002 2 0 4294967295 IQ_ADPT_VAL 0 6 RESERVED_15_7 7 15 ixDPCSSYS_CR0_RAWAONLANEX_DIG_RX_ADAPT_FOM 2 0x7003 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR0_RAWAONLANEX_DIG_DFE_SUMMER_ODD_IDAC_OFST 2 0x7004 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR0_RAWAONLANEX_DIG_DFE_PHASE_EVEN_VDAC_OFST 2 0x7005 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR0_RAWAONLANEX_DIG_DFE_PHASE_ODD_VDAC_OFST 2 0x7006 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR0_RAWAONLANEX_DIG_DFE_EVEN_REF_LVL 2 0x7007 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR0_RAWAONLANEX_DIG_DFE_ODD_REF_LVL 2 0x7008 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR0_RAWAONLANEX_DIG_RX_PHSADJ_LIN 2 0x7009 2 0 4294967295 DATA 0 0 RESERVED_15_5 5 15 ixDPCSSYS_CR0_RAWAONLANEX_DIG_RX_PHSADJ_MAP 2 0x700a 2 0 4294967295 DATA 0 0 RESERVED_15_5 5 15 ixDPCSSYS_CR0_RAWAONLANEX_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST 2 0x700b 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR0_RAWAONLANEX_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST 2 0x700c 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR0_RAWAONLANEX_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST 2 0x700d 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR0_RAWAONLANEX_DIG_DFE_DATA_ODD_LOW_VDAC_OFST 2 0x700e 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR0_RAWAONLANEX_DIG_DFE_BYPASS_EVEN_VDAC_OFST 2 0x700f 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR0_RAWAONLANEX_DIG_DFE_BYPASS_ODD_VDAC_OFST 2 0x7010 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR0_RAWAONLANEX_DIG_DFE_ERROR_EVEN_VDAC_OFST 2 0x7011 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR0_RAWAONLANEX_DIG_DFE_ERROR_ODD_VDAC_OFST 2 0x7012 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR0_RAWAONLANEX_DIG_RX_IQ_PHASE_ADJUST 2 0x7013 2 0 4294967295 DATA 0 0 RESERVED_15_7 7 15 ixDPCSSYS_CR0_RAWAONLANEX_DIG_MPLLA_COARSE_TUNE 2 0x7014 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR0_RAWAONLANEX_DIG_MPLLB_COARSE_TUNE 2 0x7015 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR0_RAWAONLANEX_DIG_INIT_PWRUP_DONE 2 0x7016 3 0 4294967295 DATA 0 0 PH2_PWRUP_DONE 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR0_RAWAONLANEX_DIG_RX_ADPT_ATT 2 0x7017 2 0 4294967295 ATT_ADPT_VAL 0 7 RESERVED_15_8 8 15 ixDPCSSYS_CR0_RAWAONLANEX_DIG_RX_ADPT_VGA 2 0x7018 2 0 4294967295 VGA_ADPT_VAL 0 9 RESERVED_15_10 10 15 ixDPCSSYS_CR0_RAWAONLANEX_DIG_RX_ADPT_CTLE 2 0x7019 3 0 4294967295 CTLE_BOOST_ADPT_VAL 0 9 CTLE_POLE_ADPT_VAL 10 12 RESERVED_15_13 13 15 ixDPCSSYS_CR0_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP1 2 0x701a 2 0 4294967295 DFE_TAP1_ADPT_VAL 0 12 RESERVED_15_13 13 15 ixDPCSSYS_CR0_RAWAONLANEX_DIG_RX_ADAPT_DONE 2 0x701b 2 0 4294967295 DATA 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR0_RAWAONLANEX_DIG_FAST_FLAGS 2 0x701c 16 0 4294967295 FAST_RX_STARTUP_CAL 0 0 FAST_RX_ADAPT 1 1 FAST_RX_AFE_CAL 2 2 FAST_RX_DFE_CAL 3 3 FAST_RX_BYPASS_CAL 4 4 FAST_RX_REFLVL_CAL 5 5 FAST_RX_IQ_CAL 6 6 FAST_RX_AFE_ADAPT 7 7 FAST_RX_DFE_ADAPT 8 8 FAST_SUP 9 9 FAST_TX_CMN_MODE 10 10 FAST_TX_RXDET 11 11 FAST_RX_PWRUP 12 12 FAST_RX_VCO_WAIT 13 13 FAST_RX_VCO_CAL 14 14 RESERVED_15_15 15 15 ixDPCSSYS_CR0_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP2 2 0x701d 2 0 4294967295 DFE_TAP2_ADPT_VAL 0 11 RESERVED_15_12 12 15 ixDPCSSYS_CR0_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP3 2 0x701e 2 0 4294967295 DFE_TAP3_ADPT_VAL 0 11 RESERVED_15_12 12 15 ixDPCSSYS_CR0_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP4 2 0x701f 2 0 4294967295 DFE_TAP4_ADPT_VAL 0 11 RESERVED_15_12 12 15 ixDPCSSYS_CR0_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP5 2 0x7020 2 0 4294967295 DFE_TAP5_ADPT_VAL 0 11 RESERVED_15_12 12 15 ixDPCSSYS_CR0_RAWAONLANEX_DIG_RX_SLICER_CTRL_EVEN 2 0x7021 2 0 4294967295 RX_ANA_SLICER_CTRL_E 0 3 RESERVED_15_4 4 15 ixDPCSSYS_CR0_RAWAONLANEX_DIG_RX_SLICER_CTRL_ODD 2 0x7022 2 0 4294967295 RX_ANA_SLICER_CTRL_O 0 3 RESERVED_15_4 4 15 ixDPCSSYS_CR0_RAWAONLANEX_DIG_LANE_CMNCAL_MPLL_STATUS 2 0x7023 3 0 4294967295 LANE_CMNCAL_MPLL_INIT 0 0 LANE_CMNCAL_MPLL_DONE 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR0_RAWAONLANEX_DIG_ADPT_CTL_0 2 0x7024 1 0 4294967295 VAL 0 15 ixDPCSSYS_CR0_RAWAONLANEX_DIG_ADPT_CTL_1 2 0x7025 1 0 4294967295 VAL 0 15 ixDPCSSYS_CR0_RAWAONLANEX_DIG_ADPT_CTL_2 2 0x7026 1 0 4294967295 VAL 0 15 ixDPCSSYS_CR0_RAWAONLANEX_DIG_ADPT_CTL_3 2 0x7027 1 0 4294967295 VAL 0 15 ixDPCSSYS_CR0_RAWAONLANEX_DIG_ADPT_CTL_4 2 0x7028 1 0 4294967295 VAL 0 15 ixDPCSSYS_CR0_RAWAONLANEX_DIG_ADPT_CTL_5 2 0x7029 1 0 4294967295 VAL 0 15 ixDPCSSYS_CR0_RAWAONLANEX_DIG_ADPT_CTL_6 2 0x702a 1 0 4294967295 VAL 0 15 ixDPCSSYS_CR0_RAWAONLANEX_DIG_ADPT_CTL_7 2 0x702b 1 0 4294967295 VAL 0 15 ixDPCSSYS_CR0_RAWAONLANEX_DIG_MPLL_DISABLE 2 0x702c 3 0 4294967295 LANE_MPLLA_DISABLE 0 0 LANE_MPLLB_DISABLE 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR0_RAWAONLANEX_DIG_FAST_FLAGS_2 2 0x702d 16 0 4294967295 FAST_RX_CONT_CAL_ADAPT 0 0 FAST_RX_CONT_ADAPT 1 1 FAST_RX_CONT_DATA_CAL 2 2 FAST_RX_CONT_PHASE_CAL 3 3 FAST_RX_CONT_AFE_CAL 4 4 FAST_TX_CONT_DCC_CAL 5 5 FAST_RX_CONT_DCC_CAL 6 6 FAST_RX_CONT_VPHUD_CAL 7 7 FAST_RX_CONT_VREF_CAL 8 8 FAST_TX_DCC_CAL 9 9 FAST_RX_DCC_CAL 10 10 FAST_RX_VPHUD_CAL 11 11 FAST_RX_VREF_CAL 12 12 SKIP_TX_RTUNE_CAL 13 13 FAST_RX_SIGDET_CAL 14 14 RESERVED_15_15 15 15 ixDPCSSYS_CR0_RAWAONLANEX_DIG_LANE_CMNCAL_RCAL_STATUS 2 0x702e 3 0 4294967295 LANE_CMNCAL_RCAL_INIT 0 0 LANE_CMNCAL_RCAL_DONE 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR0_RAWAONLANEX_DIG_TXRX_OVRD_IN 2 0x702f 5 0 4294967295 RX_DISABLE_OVRD_VAL 0 0 RX_DISABLE_OVRD_EN 1 1 TX_DISABLE_OVRD_VAL 2 2 TX_DISABLE_OVRD_EN 3 3 RESERVED_15_4 4 15 ixDPCSSYS_CR0_RAWAONLANEX_DIG_RX_LOS_MASK_CTL 2 0x7030 2 0 4294967295 RX_LOS_MASK_CNT 0 8 RESERVED_15_9 9 15 ixDPCSSYS_CR0_RAWAONLANEX_DIG_RX_SIGDET_FILT_CTRL 2 0x7031 5 0 4294967295 ISOLATE_SIGDET_HF 0 0 RX_SIGDEF_HF_FILT_OVR_DIS 1 1 RX_SIGDEF_HF_FILT_OVR 2 2 RX_SIGDET_LF_OUT_FILT_EN 3 3 RESERVED_15_4 4 15 ixDPCSSYS_CR0_RAWAONLANEX_DIG_STATS 2 0x7032 3 0 4294967295 RX_VREFGEN_MASTER 0 0 RX_PMA_SQ_OUT 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR0_RAWAONLANEX_DIG_RX_OVRD_OUT_1 2 0x7033 11 0 4294967295 RX_PMA_SQ_CTRL_TRESH_OVRD_VAL 0 2 RX_PMA_SQ_CTRL_TRESH_OVRD_EN 3 3 RX_PMA_SQ_CTRL_RESP_OVRD_VAL 4 5 RX_PMA_SQ_CTRL_RESP_OVRD_EN 6 6 RX_PMA_SQ_WEAKKEEP_OVRD_VAL 7 7 RX_PMA_SQ_WEAKKEEP_OVRD_EN 8 8 RX_PMA_SQ_INV_POLARITY_OVRD_VAL 9 9 RX_PMA_SQ_INV_POLARITY_OVRD_EN 10 10 RX_PMA_SQ_EN_OVRD_VAL 11 11 RX_PMA_SQ_EN_OVRD_EN 12 12 RESERVED_15_13 13 15 ixDPCSSYS_CR0_RAWAONLANEX_DIG_RX_OVRD_OUT_2 2 0x7034 9 0 4294967295 RX_PMA_VREFGEN_EN_OVRD_VAL 0 0 RX_PMA_VREFGEN_EN_OVRD_EN 1 1 RX_SQ_OUT_OVRD_VAL 2 2 RX_SQ_OUT_OVRD_EN 3 3 RX_PMA_TERM_ACDC_OVRD_VAL 4 4 RX_PMA_TERM_ACDC_OVRD_EN 5 5 RX_PMA_TERM_EN_OVRD_VAL 6 6 RX_PMA_TERM_EN_OVRD_EN 7 7 RESERVED_15_8 8 15 ixDPCSSYS_CR0_RAWAONLANEX_DIG_RX_OVRD_OUT_3 2 0x7035 7 0 4294967295 RX_PMA_SIGDET_LF_FILTER_EN_OVRD_VAL 0 0 RX_PMA_SIGDET_LF_FILTER_EN_OVRD_EN 1 1 RX_PMA_SIGDET_LF_EN_OVRD_VAL 2 2 RX_PMA_SIGDET_LF_EN_OVRD_EN 3 3 RX_PMA_SIGDET_HF_EN_OVRD_VAL 4 4 RX_PMA_SIGDET_HF_EN_OVRD_EN 5 5 RESERVED_15_6 6 15 ixDPCSSYS_CR0_RAWAONLANEX_DIG_RX_SIGDET_CAL 2 0x7036 4 0 4294967295 RX_PMA_SIGDET_LF_THRESHOLD 0 2 RX_PMA_SIGDET_HF_THRESHOLD 3 5 RX_PMA_SIGDET_CAL_EN 6 6 RESERVED_15_7 7 15 ixDPCSSYS_CR0_RAWAONLANEX_DIG_RX_SIGDET_HF_CODE 2 0x7037 2 0 4294967295 RX_PMA_SIGDET_HF_CAL_TUNE 0 5 RESERVED_15_6 6 15 ixDPCSSYS_CR0_RAWAONLANEX_DIG_RX_SIGDET_LF_CODE 2 0x7038 2 0 4294967295 RX_PMA_SIGDET_LF_CAL_TUNE 0 5 RESERVED_15_6 6 15 ixDPCSSYS_CR0_RAWAONLANEX_DIG_RX_VREFGEN_EN 2 0x7039 2 0 4294967295 PULL_UP 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR0_RAWAONLANEX_DIG_CAL_IOFF_CODE 2 0x703a 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR0_RAWAONLANEX_DIG_CAL_ICONST_CODE 2 0x703b 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR0_RAWAONLANEX_DIG_CAL_VREFGEN_CODE 2 0x703c 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR0_RAWAONLANEX_DIG_RX_DCC_CAL_ICM_CODE_0 2 0x703d 2 0 4294967295 RX_DCC_CAL_ICM_CODE 0 9 RESERVED_15_10 10 15 ixDPCSSYS_CR0_RAWAONLANEX_DIG_RX_DCC_CAL_IDF_CODE_0 2 0x703e 2 0 4294967295 RX_DCC_CAL_IDF_CODE 0 9 RESERVED_15_10 10 15 ixDPCSSYS_CR0_RAWAONLANEX_DIG_RX_DCC_CAL_QCM_CODE_0 2 0x703f 2 0 4294967295 RX_DCC_CAL_QCM_CODE 0 9 RESERVED_15_10 10 15 ixDPCSSYS_CR0_RAWAONLANEX_DIG_RX_DCC_CAL_QDF_CODE_0 2 0x7040 2 0 4294967295 RX_DCC_CAL_QDF_CODE 0 9 RESERVED_15_10 10 15 ixDPCSSYS_CR0_RAWAONLANEX_DIG_RX_DCC_CAL_ICM_CODE_1 2 0x7041 2 0 4294967295 RX_DCC_CAL_ICM_CODE 0 9 RESERVED_15_10 10 15 ixDPCSSYS_CR0_RAWAONLANEX_DIG_RX_DCC_CAL_IDF_CODE_1 2 0x7042 2 0 4294967295 RX_DCC_CAL_IDF_CODE 0 9 RESERVED_15_10 10 15 ixDPCSSYS_CR0_RAWAONLANEX_DIG_RX_DCC_CAL_QCM_CODE_1 2 0x7043 2 0 4294967295 RX_DCC_CAL_QCM_CODE 0 9 RESERVED_15_10 10 15 ixDPCSSYS_CR0_RAWAONLANEX_DIG_RX_DCC_CAL_QDF_CODE_1 2 0x7044 2 0 4294967295 RX_DCC_CAL_QDF_CODE 0 9 RESERVED_15_10 10 15 ixDPCSSYS_CR0_RAWAONLANEX_DIG_TX_DCC_BANK_ADDR 2 0x7045 1 0 4294967295 ADDR 0 15 ixDPCSSYS_CR0_RAWAONLANEX_DIG_TX_DCC_BANK_DATA 2 0x7046 1 0 4294967295 DATA 0 15 ixDPCSSYS_CR0_RAWAONLANEX_DIG_TX_DCC_CONT 2 0x7047 2 0 4294967295 EN 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR0_RAWAONLANEX_DIG_MPLL_BG_CTL 2 0x7048 3 0 4294967295 MPLL_STATE_WAIT 0 0 MPLL_STATE_DLY_EN 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR0_RAWAONLANEX_DIG_SIGDET_OUT_OVRD 2 0x7049 5 0 4294967295 RX_SIGDET_HF_OUT_OVRD_VAL 0 0 RX_SIGDET_HF_OUT_OVRD_EN 1 1 RX_SIGDET_LF_OUT_OVRD_VAL 2 2 RX_SIGDET_LF_OUT_OVRD_EN 3 3 RESERVED_15_4 4 15 ixDPCSSYS_CR0_RAWAONLANEX_DIG_SIGDET_OUT_IN 2 0x704a 3 0 4294967295 RX_SIGDET_HF_OUT_OVRD_VAL 0 0 RX_SIGDET_LF_OUT_OVRD_VAL 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR0_RAWAONLANEX_DIG_FW_MM_CONFIG 2 0x704b 1 0 4294967295 DATA 0 0 ixDPCSSYS_CR0_RAWAONLANEX_DIG_FW_ADPT_CONFIG 2 0x704c 2 0 4294967295 REF_LVL_ADPT 0 7 FW_CONFIG 8 15 ixDPCSSYS_CR0_RAWAONLANEX_DIG_FW_CALIB_CONFIG 2 0x704d 1 0 4294967295 FW_CALIB 0 15 ixDPCSSYS_CR0_RAWAONLANEX_DIG_LANE_XCVR_MODE_OVRD_IN 2 0x704e 3 0 4294967295 LANE_XCVR_MODE_OVRD_VAL 0 1 LANE_XCVR_MODE_OVRD_EN 2 2 RESERVED_15_3 3 15 ixDPCSSYS_CR0_RAWAONLANEX_DIG_LANE_XCVR_MODE_IN 2 0x704f 2 0 4294967295 LANE_XCVR_MODE 0 1 RESERVED_15_2 2 15 ixDPCSSYS_CR0_RAWAONLANEX_DIG_RX_SIGDET_CONFIG 2 0x7050 4 0 4294967295 RX_SIGDET_HF_FILTER_COUNTER 0 4 RX_SIGDET_LF_FILTER_COUNTER 5 9 RX_SIGDET_LF_HOLD 10 10 RESERVED_15_11 11 15 ixDPCSSYS_CR0_RAWAONLANEX_DIG_TX_DCC_CONFIG 2 0x7051 1 0 4294967295 DATA 0 0 ixDPCSSYS_CR0_SUPX_DIG_IDCODE_LO 2 0x8000 1 0 4294967295 DATA 0 0 ixDPCSSYS_CR0_SUPX_DIG_IDCODE_HI 2 0x8001 1 0 4294967295 DATA 0 0 ixDPCSSYS_CR0_SUPX_DIG_REFCLK_OVRD_IN 2 0x8002 12 0 4294967295 REF_CLK_EN 0 0 REF_CLK_EN_OVRD_EN 1 1 REF_USE_PAD 2 2 REF_USE_PAD_OVRD_EN 3 3 REF_CLK_RANGE 4 8 REF_CLK_RANGE_OVRD_EN 9 9 BG_EN 10 10 BG_EN_OVRD_EN 11 11 HDMIMODE_EN 12 12 HDMIMODE_ENABLE_OVRD_EN 13 13 SUP_PRE_HP_OVRD 14 14 SUP_PRE_HP_OVRD_EN 15 15 ixDPCSSYS_CR0_SUPX_DIG_MPLLA_DIV_CLK_OVRD_IN 2 0x8003 4 0 4294967295 MPLLA_DIV_CLK_EN 0 0 MPLLA_DIV_MULTIPLIER 1 8 MPLLA_DIV_OVRD_EN 9 9 RESERVED_15_10 10 15 ixDPCSSYS_CR0_SUPX_DIG_MPLLA_HDMI_CLK_OVRD_IN 2 0x8004 4 0 4294967295 MPLLA_HDMI_PIXEL_CLK_DIV 0 1 MPLLA_HDMI_DIV 2 4 MPLLA_HDMI_OVRD_EN 5 5 RESERVED_15_6 6 15 ixDPCSSYS_CR0_SUPX_DIG_MPLLB_DIV_CLK_OVRD_IN 2 0x8005 4 0 4294967295 MPLLB_DIV_CLK_EN 0 0 MPLLB_DIV_MULTIPLIER 1 8 MPLLB_DIV_OVRD_EN 9 9 RESERVED_15_10 10 15 ixDPCSSYS_CR0_SUPX_DIG_MPLLB_HDMI_CLK_OVRD_IN 2 0x8006 4 0 4294967295 MPLLB_HDMI_PIXEL_CLK_DIV 0 1 MPLLB_HDMI_DIV 2 4 MPLLB_HDMI_OVRD_EN 5 5 RESERVED_15_6 6 15 ixDPCSSYS_CR0_SUPX_DIG_MPLLA_OVRD_IN_0 2 0x8007 12 0 4294967295 MPLLA_EN 0 0 MPLLA_DIV5_CLK_EN 1 1 MPLLA_TX_CLK_DIV 2 4 OVRD_EN 5 5 MPLLA_V2I 6 7 MPLLA_STANDBY 8 8 MPLLA_FREQ_VCO 9 10 MPLLA_CAL_FORCE 11 11 MPLL_FRACN_EN 12 12 MPLLA_CLK_SYNC_OVRD 13 13 MPLLA_CLK_SYNC_OVRD_EN 14 14 RESERVED_15_15 15 15 ixDPCSSYS_CR0_SUPX_DIG_MPLLA_OVRD_IN_1 2 0x8008 2 0 4294967295 MPLLA_MULTIPLIER 0 11 RESERVED_15_12 12 15 ixDPCSSYS_CR0_SUPX_DIG_MPLLA_OVRD_IN_2 2 0x8009 7 0 4294967295 MPLLA_SSC_EN 0 0 MPLLA_SSC_OVRD_EN 1 1 MPLLA_SSC_UP_SPREAD 2 2 MPLLA_PMIX_EN 3 3 MPLLA_WORD_DIV2_EN 4 4 MPLLA_FRACN_CFG_UPDATE_EN 5 5 RESERVED_15_6 6 15 ixDPCSSYS_CR0_SUPX_DIG_MPLLA_SSC_PEAK_1 2 0x800a 1 0 4294967295 MPLLA_SSC_PEAK_15_0 0 15 ixDPCSSYS_CR0_SUPX_DIG_MPLLA_SSC_PEAK_2 2 0x800b 2 0 4294967295 MPLLA_SSC_PEAK_19_16 0 3 RESERVED_15_4 4 15 ixDPCSSYS_CR0_SUPX_DIG_MPLLA_SSC_STEPSIZE_1 2 0x800c 1 0 4294967295 MPLLA_SSC_STEPSIZE_15_0 0 15 ixDPCSSYS_CR0_SUPX_DIG_MPLLA_SSC_STEPSIZE_2 2 0x800d 2 0 4294967295 MPLLA_SSC_STEPSIZE_20_16 0 4 RESERVED_15_5 5 15 ixDPCSSYS_CR0_SUPX_DIG_MPLLA_OVRD_IN_3 2 0x800e 1 0 4294967295 MPLLA_FRACN_QUOT 0 15 ixDPCSSYS_CR0_SUPX_DIG_MPLLA_OVRD_IN_4 2 0x800f 1 0 4294967295 MPLLA_FRACN_REM 0 15 ixDPCSSYS_CR0_SUPX_DIG_MPLLA_OVRD_IN_5 2 0x8010 1 0 4294967295 MPLLA_FRACN_DEN 0 15 ixDPCSSYS_CR0_SUPX_DIG_MPLLA_CP_OVRD_IN 2 0x8011 3 0 4294967295 MPLLA_CP_PROP 0 6 MPLLA_CP_INT 7 13 RESERVED_15_14 14 15 ixDPCSSYS_CR0_SUPX_DIG_MPLLA_CP_GS_OVRD_IN 2 0x8012 4 0 4294967295 MPLLA_CP_PROP_GS 0 6 MPLLA_CP_PROP_GS_OVR_EN 7 7 MPLLA_CP_INT_GS 8 14 MPLLA_CP_INT_GS_OVR_EN 15 15 ixDPCSSYS_CR0_SUPX_DIG_MPLLB_OVRD_IN_0 2 0x8013 12 0 4294967295 MPLLB_EN 0 0 MPLLB_DIV5_CLK_EN 1 1 MPLLB_TX_CLK_DIV 2 4 OVRD_EN 5 5 MPLLB_V2I 6 7 MPLLB_STANDBY 8 8 MPLLB_FREQ_VCO 9 10 MPLLB_CAL_FORCE 11 11 MPLL_FRACN_EN 12 12 MPLLB_CLK_SYNC_OVRD 13 13 MPLLB_CLK_SYNC_OVRD_EN 14 14 RESERVED_15_15 15 15 ixDPCSSYS_CR0_SUPX_DIG_MPLLB_OVRD_IN_1 2 0x8014 2 0 4294967295 MPLLB_MULTIPLIER 0 11 RESERVED_15_12 12 15 ixDPCSSYS_CR0_SUPX_DIG_MPLLB_OVRD_IN_2 2 0x8015 7 0 4294967295 MPLLB_SSC_EN 0 0 MPLLB_SSC_OVRD_EN 1 1 MPLLB_SSC_UP_SPREAD 2 2 MPLLB_PMIX_EN 3 3 MPLLB_WORD_DIV2_EN 4 4 MPLLB_FRACN_CFG_UPDATE_EN 5 5 RESERVED_15_6 6 15 ixDPCSSYS_CR0_SUPX_DIG_MPLLB_SSC_PEAK_1 2 0x8016 1 0 4294967295 MPLLB_SSC_PEAK_15_0 0 15 ixDPCSSYS_CR0_SUPX_DIG_MPLLB_SSC_PEAK_2 2 0x8017 2 0 4294967295 MPLLB_SSC_PEAK_19_16 0 3 RESERVED_15_4 4 15 ixDPCSSYS_CR0_SUPX_DIG_MPLLB_SSC_STEPSIZE_1 2 0x8018 1 0 4294967295 MPLLB_SSC_STEPSIZE_15_0 0 15 ixDPCSSYS_CR0_SUPX_DIG_MPLLB_SSC_STEPSIZE_2 2 0x8019 2 0 4294967295 MPLLB_SSC_STEPSIZE_20_16 0 4 RESERVED_15_5 5 15 ixDPCSSYS_CR0_SUPX_DIG_MPLLB_OVRD_IN_3 2 0x801a 1 0 4294967295 MPLLB_FRACN_QUOT 0 15 ixDPCSSYS_CR0_SUPX_DIG_MPLLB_OVRD_IN_4 2 0x801b 1 0 4294967295 MPLLB_FRACN_REM 0 15 ixDPCSSYS_CR0_SUPX_DIG_MPLLB_OVRD_IN_5 2 0x801c 1 0 4294967295 MPLLB_FRACN_DEN 0 15 ixDPCSSYS_CR0_SUPX_DIG_MPLLB_CP_OVRD_IN 2 0x801d 3 0 4294967295 MPLLB_CP_PROP 0 6 MPLLB_CP_INT 7 13 RESERVED_15_14 14 15 ixDPCSSYS_CR0_SUPX_DIG_MPLLB_CP_GS_OVRD_IN 2 0x801e 4 0 4294967295 MPLLB_CP_PROP_GS 0 6 MPLLB_CP_PROP_GS_OVR_EN 7 7 MPLLB_CP_INT_GS 8 14 MPLLB_CP_INT_GS_OVR_EN 15 15 ixDPCSSYS_CR0_SUPX_DIG_SUP_OVRD_IN 2 0x801f 8 0 4294967295 PRESCALER_OVRD_EN 0 0 RTUNE_REQ 1 1 RTUNE_OVRD_EN 2 2 TX_CAL_CODE 3 6 TX_CAL_CODE_EN 7 7 REF_ALT_CLK_LP_SEL_OVRD 8 8 REF_ALT_CLK_LP_SEL_OVRD_EN 9 9 RESERVED_15_10 10 15 ixDPCSSYS_CR0_SUPX_DIG_PRESCALER_OVRD_IN 2 0x8020 6 0 4294967295 DCO_RANGE 0 1 DCO_FINETUNE 2 7 REF_CLK_MPLLB_DIV 8 10 REF_CLK_MPLLA_DIV 11 13 REF_CLKDET_RESULT 14 14 REF_CLKDET_EN 15 15 ixDPCSSYS_CR0_SUPX_DIG_SUP_OVRD_OUT 2 0x8021 12 0 4294967295 RTUNE_ACK 0 0 RTUNE_ACK_OVRD_EN 1 1 MPLLA_STATE 2 2 MPLLA_STATE_OVRD_EN 3 3 MPLLB_STATE 4 4 MPLLB_STATE_OVRD_EN 5 5 BG_LANE_STATE 6 6 BG_LANE_STATE_OVRD_EN 7 7 BG_SUP_STATE 8 8 BG_SUP_STATE_OVRD_EN 9 9 REF_CLK_ACK 10 10 RESERVED_15_11 11 15 ixDPCSSYS_CR0_SUPX_DIG_LVL_OVRD_IN 2 0x8022 7 0 4294967295 RX_VREF_CTRL 0 2 RX_VREF_CTRL_EN 3 3 TX_VBOOST_LVL 4 6 TX_VBOOST_LVL_EN 7 7 SUP_RX_VCO_VREF_SEL_OVR 8 10 SUP_RX_VCO_VREF_SEL_OVR_EN 11 11 RESERVED_15_12 12 15 ixDPCSSYS_CR0_SUPX_DIG_MPLLA_ASIC_IN_0 2 0x8024 9 0 4294967295 MPLLA_EN 0 0 MPLLA_DIV5_CLK_EN 1 1 MPLLA_TX_CLK_DIV 2 4 MPLLA_V2I 5 6 MPLLA_STANDBY 7 7 MPLLA_FREQ_VCO 8 9 MPLLA_CAL_FORCE 10 10 MPLLA_FRACN_EN 11 11 RESERVED_15_12 12 15 ixDPCSSYS_CR0_SUPX_DIG_MPLLA_ASIC_IN_1 2 0x8025 2 0 4294967295 MPLLA_MULTIPLIER 0 11 RESERVED_15_12 12 15 ixDPCSSYS_CR0_SUPX_DIG_MPLLA_ASIC_IN_2 2 0x8026 7 0 4294967295 MPLLA_SSC_EN 0 0 MPLLA_SSC_UP_SPREAD 1 1 MPLLA_PMIX_EN 2 2 MPLLA_WORD_DIV2_EN 3 3 MPLLA_FRACN_CFG_UPDATE_EN 4 4 MPLLA_CLK_SYNC 5 5 RESERVED_15_6 6 15 ixDPCSSYS_CR0_SUPX_DIG_MPLLA_ASIC_IN_3 2 0x8027 1 0 4294967295 MPLLA_SSC_PEAK_15_0 0 15 ixDPCSSYS_CR0_SUPX_DIG_MPLLA_ASIC_IN_4 2 0x8028 2 0 4294967295 MPLLA_SSC_PEAK_19_16 0 3 RESERVED_15_4 4 15 ixDPCSSYS_CR0_SUPX_DIG_MPLLA_ASIC_IN_5 2 0x8029 1 0 4294967295 MPLLA_SSC_STEPSIZE_15_0 0 15 ixDPCSSYS_CR0_SUPX_DIG_MPLLA_ASIC_IN_6 2 0x802a 2 0 4294967295 MPLLA_SSC_STEPSIZE_20_16 0 3 RESERVED_15_4 4 15 ixDPCSSYS_CR0_SUPX_DIG_MPLLB_ASIC_IN_0 2 0x802b 9 0 4294967295 MPLLB_EN 0 0 MPLLB_DIV5_CLK_EN 1 1 MPLLB_TX_CLK_DIV 2 4 MPLLB_V2I 5 6 MPLLB_STANDBY 7 7 MPLLB_FREQ_VCO 8 9 MPLLB_CAL_FORCE 10 10 MPLLB_FRACN_EN 11 11 RESERVED_15_12 12 15 ixDPCSSYS_CR0_SUPX_DIG_MPLLB_ASIC_IN_1 2 0x802c 2 0 4294967295 MPLLB_MULTIPLIER 0 11 RESERVED_15_12 12 15 ixDPCSSYS_CR0_SUPX_DIG_MPLLB_ASIC_IN_2 2 0x802d 7 0 4294967295 MPLLB_SSC_EN 0 0 MPLLB_SSC_UP_SPREAD 1 1 MPLLB_PMIX_EN 2 2 MPLLB_WORD_DIV2_EN 3 3 MPLLB_FRACN_CFG_UPDATE_EN 4 4 MPLLB_CLK_SYNC 5 5 RESERVED_15_6 6 15 ixDPCSSYS_CR0_SUPX_DIG_MPLLB_ASIC_IN_3 2 0x802e 1 0 4294967295 MPLLB_SSC_PEAK_15_0 0 15 ixDPCSSYS_CR0_SUPX_DIG_MPLLB_ASIC_IN_4 2 0x802f 2 0 4294967295 MPLLB_SSC_PEAK_19_16 0 3 RESERVED_15_4 4 15 ixDPCSSYS_CR0_SUPX_DIG_MPLLB_ASIC_IN_5 2 0x8030 1 0 4294967295 MPLLB_SSC_STEPSIZE_15_0 0 15 ixDPCSSYS_CR0_SUPX_DIG_MPLLB_ASIC_IN_6 2 0x8031 2 0 4294967295 MPLLB_SSC_STEPSIZE_20_16 0 3 RESERVED_15_4 4 15 ixDPCSSYS_CR0_SUPX_DIG_MPLLA_DIV_CLK_ASIC_IN 2 0x8032 3 0 4294967295 MPLLA_DIV_CLK_EN 0 0 MPLLA_DIV_MULTIPLIER 1 8 RESERVED_15_9 9 15 ixDPCSSYS_CR0_SUPX_DIG_MPLLA_HDMI_CLK_ASIC_IN 2 0x8033 3 0 4294967295 MPLLA_HDMI_PIXEL_CLK_DIV 0 1 MPLLA_HDMI_DIV 2 4 RESERVED_15_5 5 15 ixDPCSSYS_CR0_SUPX_DIG_MPLLB_DIV_CLK_ASIC_IN 2 0x8034 3 0 4294967295 MPLLB_DIV_CLK_EN 0 0 MPLLB_DIV_MULTIPLIER 1 8 RESERVED_15_9 9 15 ixDPCSSYS_CR0_SUPX_DIG_MPLLB_HDMI_CLK_ASIC_IN 2 0x8035 3 0 4294967295 MPLLB_HDMI_PIXEL_CLK_DIV 0 1 MPLLB_HDMI_DIV 2 4 RESERVED_15_5 5 15 ixDPCSSYS_CR0_SUPX_DIG_ASIC_IN 2 0x8036 12 0 4294967295 PHY_RESET 0 0 REF_CLK_EN 1 1 REF_USE_PAD 2 2 TEST_BURNIN 3 3 TEST_POWERDOWN 4 4 RTUNE_REQ 5 5 RTUNE_ACK 6 6 MPLLA_STATE 7 7 MPLLB_STATE 8 8 TEST_TX_REF_CLK_EN 9 9 REF_ALT_CLK_LP_SEL 10 10 RESERVED_15_11 11 15 ixDPCSSYS_CR0_SUPX_DIG_LVL_ASIC_IN 2 0x8037 4 0 4294967295 RX_VREF_CTRL 0 2 TX_VBOOST_LVL 3 5 SUP_RX_VCO_VREF_SEL 6 8 RESERVED_15_9 9 15 ixDPCSSYS_CR0_SUPX_DIG_BANDGAP_ASIC_IN 2 0x8038 2 0 4294967295 BG_EN 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR0_SUPX_DIG_MPLLA_CP_ASIC_IN 2 0x8039 3 0 4294967295 MPLLA_CP_PROP 0 6 MPLLA_CP_INT 7 13 RESERVED_15_14 14 15 ixDPCSSYS_CR0_SUPX_DIG_MPLLA_CP_GS_ASIC_IN 2 0x803a 3 0 4294967295 MPLLA_CP_PROP_GS 0 6 MPLLA_CP_INT_GS 7 13 RESERVED_15_14 14 15 ixDPCSSYS_CR0_SUPX_DIG_MPLLB_CP_ASIC_IN 2 0x803b 3 0 4294967295 MPLLB_CP_PROP 0 6 MPLLB_CP_INT 7 13 RESERVED_15_14 14 15 ixDPCSSYS_CR0_SUPX_DIG_MPLLB_CP_GS_ASIC_IN 2 0x803c 3 0 4294967295 MPLLB_CP_PROP_GS 0 6 MPLLB_CP_INT_GS 7 13 RESERVED_15_14 14 15 ixDPCSSYS_CR0_SUPX_ANA_PRESCALER_CTRL 2 0x8040 7 0 4294967295 PSCALER_ATB_SELECT 0 0 PSCALER_MEAS_VREG 0 0 PSCALER_OVRD_FAST_START 0 0 PSCALER_FAST_START_REG 0 0 PSCALER_VREG_BOOST 0 0 PSCALER_HYST_REF 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR0_SUPX_ANA_RTUNE_CTRL 2 0x8041 9 0 4294967295 RT_ATB 0 0 RT_SEL_ATBF 0 0 RT_SEL_ATBP 0 0 RT_VP4O8_EN 0 0 RT_DAC_CHOP 0 0 RT_DAC_MODE 0 0 RT_EN_FRCON 0 0 PSCALER_VREG_FB_DIV_CTRL 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR0_SUPX_ANA_BG1 2 0x8042 6 0 4294967295 SUP_SEL_VBG_VREF 0 0 SUP_SEL_VPHUD_VREF 0 0 NC4 4 4 SUP_SEL_VPLL_REF 0 0 RT_VREF_SEL 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR0_SUPX_ANA_BG2 2 0x8043 9 0 4294967295 SUP_BYPASS_BG 0 0 SUP_CHOP_EN 0 0 SUP_TEMP_MEAS 0 0 VPHUD_SELREF 0 0 ATB_EXT_MEAS_EN 0 0 RT_TX_OFFSET_EN 0 0 SUP_SEL_TX_SWING_VREF 0 0 PSCALER_VREG_OVERRIDE_RING_CTRL 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR0_SUPX_ANA_SWITCH_PWR_MEAS 2 0x8044 3 0 4294967295 SUP_ATB_SW 0 0 SUP_TIE 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR0_SUPX_ANA_BG3 2 0x8045 4 0 4294967295 SUP_SEL_RX_VCO_TC_VREF 0 0 SUP_SEL_RX_CAL_VREF 0 0 NC7_4 4 7 RESERVED_15_8 8 15 ixDPCSSYS_CR0_SUPX_ANA_MPLLA_MISC1 2 0x8046 7 0 4294967295 OVRD_GEAR_RC_FILT 0 0 OVRD_TEST_RC_FILT 0 0 TEST_VREG_DIV 0 0 VBG_EN 0 0 COUNT_SEL_LOCK 0 0 PHASE_SEL_LOCK 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR0_SUPX_ANA_MPLLA_MISC2 2 0x8047 8 0 4294967295 OVRD_PR_BYPASS 0 0 PR_BYPASS 0 0 OVRD_GEARSHIFT 0 0 GEARSHIFT_REG 0 0 TEST_LOCK_GEAR 0 0 EN_CAL_SPO 0 0 TEST_BOOST 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR0_SUPX_ANA_MPLLA_OVRD 2 0x8048 9 0 4294967295 OVRD_ENABLE 0 0 ENABLE_REG 0 0 OVRD_CAL 0 0 CAL_REG 0 0 OVRD_FB_CLK_EN 0 0 FB_CLK_EN_REG 0 0 OVRD_RESET 0 0 RESET_REG 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR0_SUPX_ANA_MPLLA_ATB1 2 0x8049 3 0 4294967295 MEAS_IV_WRAP 0 0 ATB_SELECT 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR0_SUPX_ANA_MPLLA_ATB2 2 0x804a 2 0 4294967295 MEAS_IV_PLL 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR0_SUPX_ANA_MPLLA_ATB3 2 0x804b 3 0 4294967295 MEAS_IV_BIAS 0 0 CTR_UPLL_TUNNING 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR0_SUPX_ANA_MPLLA_CTR1 2 0x804c 5 0 4294967295 CTR_ICP_INT 0 0 CTR_VREF_EN 0 0 CTR_VREF_VMARG 0 0 CTR_CP_PLL 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR0_SUPX_ANA_MPLLA_CTR2 2 0x804d 2 0 4294967295 CTR_REGS_PLL 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR0_SUPX_ANA_MPLLA_CTR3 2 0x804e 4 0 4294967295 CTR_REGS_CP_PLL 0 0 CTR_SPO_PLL 0 0 CTR_VINT_CAP 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR0_SUPX_ANA_MPLLA_CTR4 2 0x804f 7 0 4294967295 CTR_CP_8X 0 0 CTR_FIL_REG 0 0 CTR_CP_PROP_REF 0 0 CTR_DOUBLER_GAIN 0 0 CTR_TEST_CASC 0 0 CTR_RC_FITER 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR0_SUPX_ANA_MPLLA_CTR5 2 0x8050 8 0 4294967295 CTR_STANDBY_MODE 0 0 CTR_LEG_SR_CON 0 0 CTR_VREG_RING_OVERRIDE 0 0 CTR_SPO_SPEED_OVERRIDE 0 0 CTR_BYPASS_LOCK_SPO_CAL 0 0 CTR_LOCK_SPO_CAL 0 0 CTR_UPLL_RESERVED 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR0_SUPX_ANA_MPLLA_RESERVED1 2 0x8051 8 0 4294967295 CTR_REF_FBK_BYPASS 0 0 CTR_BYPASS_TX 0 0 CTR_VREG_CLK_BYPASS 0 0 CTR_VREG_CLK_PMIX_BYPASS 0 0 CTR_VREG_RIGHT_BYPASS 0 0 CTR_VREG_LEFT_BYPASS 0 0 CTR_LEFT_RIGHT_GAIN 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR0_SUPX_ANA_MPLLA_RESERVED2 2 0x8052 5 0 4294967295 CTR_DLL_MODE_90 0 0 CTR_DLL_RESERVED 0 0 CTR_DIV24_DSQ_ENZ 0 0 CTR_DIV4 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR0_SUPX_ANA_MPLLB_MISC1 2 0x8053 7 0 4294967295 OVRD_GEAR_RC_FILT 0 0 OVRD_TEST_RC_FILT 0 0 TEST_VREG_DIV 0 0 VBG_EN 0 0 COUNT_SEL_LOCK 0 0 PHASE_SEL_LOCK 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR0_SUPX_ANA_MPLLB_MISC2 2 0x8054 8 0 4294967295 OVRD_PR_BYPASS 0 0 PR_BYPASS 0 0 OVRD_GEARSHIFT 0 0 GEARSHIFT_REG 0 0 TEST_LOCK_GEAR 0 0 EN_CAL_SPO 0 0 TEST_BOOST 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR0_SUPX_ANA_MPLLB_OVRD 2 0x8055 9 0 4294967295 OVRD_ENABLE 0 0 ENABLE_REG 0 0 OVRD_CAL 0 0 CAL_REG 0 0 OVRD_FB_CLK_EN 0 0 FB_CLK_EN_REG 0 0 OVRD_RESET 0 0 RESET_REG 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR0_SUPX_ANA_MPLLB_ATB1 2 0x8056 3 0 4294967295 MEAS_IV_WRAP 0 0 ATB_SELECT 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR0_SUPX_ANA_MPLLB_ATB2 2 0x8057 2 0 4294967295 MEAS_IV_PLL 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR0_SUPX_ANA_MPLLB_ATB3 2 0x8058 3 0 4294967295 MEAS_IV_BIAS 0 0 CTR_UPLL_TUNNING 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR0_SUPX_ANA_MPLLB_CTR1 2 0x8059 5 0 4294967295 CTR_ICP_INT 0 0 CTR_VREF_EN 0 0 CTR_VREF_VMARG 0 0 CTR_CP_PLL 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR0_SUPX_ANA_MPLLB_CTR2 2 0x805a 2 0 4294967295 CTR_REGS_PLL 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR0_SUPX_ANA_MPLLB_CTR3 2 0x805b 4 0 4294967295 CTR_REGS_CP_PLL 0 0 CTR_SPO_PLL 0 0 CTR_VINT_CAP 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR0_SUPX_ANA_MPLLB_CTR4 2 0x805c 7 0 4294967295 CTR_CP_8X 0 0 CTR_FIL_REG 0 0 CTR_CP_PROP_REF 0 0 CTR_DOUBLER_GAIN 0 0 CTR_TEST_CASC 0 0 CTR_RC_FITER 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR0_SUPX_ANA_MPLLB_CTR5 2 0x805d 8 0 4294967295 CTR_STANDBY_MODE 0 0 CTR_LEG_SR_CON 0 0 CTR_VREG_RING_OVERRIDE 0 0 CTR_SPO_SPEED_OVERRIDE 0 0 CTR_BYPASS_LOCK_SPO_CAL 0 0 CTR_LOCK_SPO_CAL 0 0 CTR_UPLL_RESERVED 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR0_SUPX_ANA_MPLLB_RESERVED1 2 0x805e 8 0 4294967295 CTR_REF_FBK_BYPASS 0 0 CTR_BYPASS_TX 0 0 CTR_VREG_CLK_BYPASS 0 0 CTR_VREG_CLK_PMIX_BYPASS 0 0 CTR_VREG_RIGHT_BYPASS 0 0 CTR_VREG_LEFT_BYPASS 0 0 CTR_LEFT_RIGHT_GAIN 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR0_SUPX_ANA_MPLLB_RESERVED2 2 0x805f 5 0 4294967295 CTR_DLL_MODE_90 0 0 CTR_DLL_RESERVED 0 0 CTR_DIV24_DSQ_ENZ 0 0 CTR_DIV4 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD 2 0x8061 8 0 4294967295 OVRD_SEL 0 0 MPLL_FBDIGCLK_EN 1 1 MPLL_PCLK_EN 2 2 FAST_MPLL_PWRUP 3 3 FAST_MPLL_LOCK 4 4 DTB_SEL 5 9 DIV10_EN 10 10 RESERVED 11 15 ixDPCSSYS_CR0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT 2 0x8062 11 0 4294967295 FSM_STATE 0 3 MPLL_R_LANES 4 4 MPLL_L_LANES 5 5 MPLL_PCLK_EN 6 6 MPLL_OUTPUT_EN 7 7 MPLL_FBCLK_EN 8 8 MPLL_CAL 9 9 MPLL_RST 10 10 MPLL_ANA_EN 11 11 MPLL_LOCK 12 12 RESERVED_15_13 13 15 ixDPCSSYS_CR0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE 2 0x8063 3 0 4294967295 MAX_RANGE 0 4 DAC_IN 5 9 RESERVED_15_10 10 15 ixDPCSSYS_CR0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_LOCK 2 0x8064 3 0 4294967295 LOCK_TIME 0 7 STABLE_TIME 8 13 RESERVED_15_14 14 15 ixDPCSSYS_CR0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS 2 0x8065 2 0 4294967295 GEARSHIFT_TIME 0 7 PRESET_TIME 8 15 ixDPCSSYS_CR0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE 2 0x8066 3 0 4294967295 PWRDN_WAIT_TIME 0 5 PCLK_EN_TIME 6 11 RESERVED_15_12 12 15 ixDPCSSYS_CR0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2 2 0x8067 3 0 4294967295 PCLK_DIS_TIME 0 5 PWRDN_TIME 6 11 RESERVED_15_12 12 15 ixDPCSSYS_CR0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_CAL 2 0x8068 3 0 4294967295 MPLL_CAL 0 0 MPLL_CAL_OVRD_EN 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT 2 0x8069 2 0 4294967295 MPLL_ANA_DAC_OUT 0 4 RESERVED_15_5 5 15 ixDPCSSYS_CR0_SUPX_DIG_MPLLA_SSC_GEN_SPREAD_TYPE 2 0x806b 3 0 4294967295 SPREAD_TYPE 0 1 OVR_EN 2 2 RESERVED_15_3 3 15 ixDPCSSYS_CR0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD 2 0x806d 8 0 4294967295 OVRD_SEL 0 0 MPLL_FBDIGCLK_EN 1 1 MPLL_PCLK_EN 2 2 FAST_MPLL_PWRUP 3 3 FAST_MPLL_LOCK 4 4 DTB_SEL 5 9 DIV10_EN 10 10 RESERVED 11 15 ixDPCSSYS_CR0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT 2 0x806e 11 0 4294967295 FSM_STATE 0 3 MPLL_R_LANES 4 4 MPLL_L_LANES 5 5 MPLL_PCLK_EN 6 6 MPLL_OUTPUT_EN 7 7 MPLL_FBCLK_EN 8 8 MPLL_CAL 9 9 MPLL_RST 10 10 MPLL_ANA_EN 11 11 MPLL_LOCK 12 12 RESERVED_15_13 13 15 ixDPCSSYS_CR0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE 2 0x806f 3 0 4294967295 MAX_RANGE 0 4 DAC_IN 5 9 RESERVED_15_10 10 15 ixDPCSSYS_CR0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_LOCK 2 0x8070 3 0 4294967295 LOCK_TIME 0 7 STABLE_TIME 8 13 RESERVED_15_14 14 15 ixDPCSSYS_CR0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS 2 0x8071 2 0 4294967295 GEARSHIFT_TIME 0 7 PRESET_TIME 8 15 ixDPCSSYS_CR0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE 2 0x8072 3 0 4294967295 PWRDN_WAIT_TIME 0 5 PCLK_EN_TIME 6 11 RESERVED_15_12 12 15 ixDPCSSYS_CR0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2 2 0x8073 3 0 4294967295 PCLK_DIS_TIME 0 5 PWRDN_TIME 6 11 RESERVED_15_12 12 15 ixDPCSSYS_CR0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_CAL 2 0x8074 3 0 4294967295 MPLL_CAL 0 0 MPLL_CAL_OVRD_EN 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT 2 0x8075 2 0 4294967295 MPLL_ANA_DAC_OUT 0 4 RESERVED_15_5 5 15 ixDPCSSYS_CR0_SUPX_DIG_MPLLB_SSC_GEN_SPREAD_TYPE 2 0x8077 3 0 4294967295 SPREAD_TYPE 0 1 OVR_EN 2 2 RESERVED_15_3 3 15 ixDPCSSYS_CR0_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_0 2 0x8078 3 0 4294967295 BG_SUP_EN_TIME 0 8 FAST_BG_WAIT 9 9 RESERVED_15_10 10 15 ixDPCSSYS_CR0_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_1 2 0x8079 2 0 4294967295 BG_LANE_EN_TIME 0 8 RESERVED_15_9 9 15 ixDPCSSYS_CR0_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_2 2 0x807a 3 0 4294967295 BG_KICK_START_EN_TIME 0 7 BG_SUP_STATE_UPD_EN 8 8 RESERVED_15_9 9 15 ixDPCSSYS_CR0_SUPX_DIG_CLK_RST_REF_PWRUP_TIME_0 2 0x807b 3 0 4294967295 REF_VREG_FAST_START_TIME 0 4 FAST_REF_WAIT 5 5 RESERVED_15_6 6 15 ixDPCSSYS_CR0_SUPX_DIG_CLK_RST_REF_VPHUD 2 0x807c 3 0 4294967295 SUP_ANA_VPHUD_SELVPH_I 0 0 SUP_ANA_VPHUD_EN_I 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR0_SUPX_DIG_RTUNE_CONFIG 2 0x8081 5 0 4294967295 RX_CAL_EN 0 0 FAST_RTUNE 1 1 TX_CAL_EN 2 2 SUP_ANA_TERM_CTRL 3 5 RESERVED_15_6 6 15 ixDPCSSYS_CR0_SUPX_DIG_RTUNE_STAT 2 0x8082 3 0 4294967295 STAT 0 9 DTB_RTUNE 10 11 RESERVED_15_12 12 15 ixDPCSSYS_CR0_SUPX_DIG_RTUNE_RX_SET_VAL 2 0x8083 2 0 4294967295 RX_SET_VAL 0 5 RESERVED_15_6 6 15 ixDPCSSYS_CR0_SUPX_DIG_RTUNE_TXDN_SET_VAL 2 0x8084 2 0 4294967295 TXDN_SET_VAL 0 9 RESERVED_15_10 10 15 ixDPCSSYS_CR0_SUPX_DIG_RTUNE_TXUP_SET_VAL 2 0x8085 2 0 4294967295 TXUP_SET_VAL 0 9 RESERVED_15_10 10 15 ixDPCSSYS_CR0_SUPX_DIG_RTUNE_RX_STAT 2 0x8086 2 0 4294967295 RX_STAT 0 5 RESERVED_15_6 6 15 ixDPCSSYS_CR0_SUPX_DIG_RTUNE_TXDN_STAT 2 0x8087 2 0 4294967295 TXDN_STAT 0 9 RESERVED_15_10 10 15 ixDPCSSYS_CR0_SUPX_DIG_RTUNE_TXUP_STAT 2 0x8088 2 0 4294967295 TXUP_STAT 0 9 RESERVED_15_10 10 15 ixDPCSSYS_CR0_SUPX_DIG_RTUNE_CONFIG_CNT0 2 0x8089 4 0 4294967295 RT_RESULT_TIME 0 3 RT_EVAL_TIME 4 7 RT_RST_TIME 8 11 RT_ACK_TIME 12 15 ixDPCSSYS_CR0_SUPX_DIG_RTUNE_CONFIG_CNT1 2 0x808a 3 0 4294967295 RT_TXDN_SETTLE_TIME 0 3 RT_PWRUP_TIME 4 8 RESERVED_15_9 9 15 ixDPCSSYS_CR0_SUPX_DIG_RTUNE_TX_CAL_CODE 2 0x808b 2 0 4294967295 VALUE 0 3 RESERVED_15_4 4 15 ixDPCSSYS_CR0_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0 2 0x808c 16 0 4294967295 MPLLA_WORD_CLK_EN 0 0 MPLLA_HDMI_CLK_EN 1 1 MPLLA_DIV_CLK_EN 2 2 MPLLA_OUTPUT_EN 3 3 MPLLA_CLK_EN_OVRD_EN 4 4 MPLLA_OUTPUT_L_EN 5 5 MPLLA_OUTPUT_R_EN 6 6 MPLLA_ANA_EN 7 7 MPLLA_RST 8 8 MPLLA_CAL 9 9 MPLLA_DIV5_CLK_EN 10 10 MPLLA_DIV10_CLK_EN 11 11 MPLLA_FBCLK_EN 12 12 MPLLA_GEARSHIFT_EN 13 13 MPLLA_STANDBY 14 14 OVRD_SEL 15 15 ixDPCSSYS_CR0_SUPX_DIG_ANA_MPLLA_OVRD_OUT_1 2 0x808d 2 0 4294967295 MPLLA_ANA_INT 0 9 RESERVED_15_10 10 15 ixDPCSSYS_CR0_SUPX_DIG_ANA_MPLLA_OVRD_OUT_2 2 0x808e 3 0 4294967295 MPLLA_CP_PROP 0 6 MPLLA_CP_INT 7 13 RESERVED_15_14 14 15 ixDPCSSYS_CR0_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0 2 0x808f 16 0 4294967295 MPLLB_WORD_CLK_EN 0 0 MPLLB_HDMI_CLK_EN 1 1 MPLLB_DIV_CLK_EN 2 2 MPLLB_OUTPUT_EN 3 3 MPLLB_CLK_EN_OVRD_EN 4 4 MPLLB_OUTPUT_L_EN 5 5 MPLLB_OUTPUT_R_EN 6 6 MPLLB_ANA_EN 7 7 MPLLB_RST 8 8 MPLLB_CAL 9 9 MPLLB_DIV5_CLK_EN 10 10 MPLLB_DIV10_CLK_EN 11 11 MPLLB_FBCLK_EN 12 12 MPLLB_GEARSHIFT_EN 13 13 MPLLB_STANDBY 14 14 OVRD_SEL 15 15 ixDPCSSYS_CR0_SUPX_DIG_ANA_MPLLB_OVRD_OUT_1 2 0x8090 2 0 4294967295 MPLLB_ANA_INT 0 9 RESERVED_15_10 10 15 ixDPCSSYS_CR0_SUPX_DIG_ANA_MPLLB_OVRD_OUT_2 2 0x8091 3 0 4294967295 MPLLB_CP_PROP 0 6 MPLLB_CP_INT 7 13 RESERVED_15_14 14 15 ixDPCSSYS_CR0_SUPX_DIG_ANA_RTUNE_OVRD_OUT 2 0x8092 6 0 4294967295 RTUNE_COMP_RST 0 0 RTUNE_MODE 1 2 RTUNE_EN 3 3 RTUNE_VALUE 4 13 RTUNE_OVRD_EN 14 14 RESERVED_15_15 15 15 ixDPCSSYS_CR0_SUPX_DIG_ANA_STAT 2 0x8093 3 0 4294967295 RT_ANA_COMP_RESULT 0 0 REF_ANA_CLKDET_RESULT 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR0_SUPX_DIG_ANA_BG_OVRD_OUT 2 0x8094 11 0 4294967295 BG_EN 0 0 BG_FAST_START 1 1 BG_KICK_START 2 2 BG_OVRD_EN 3 3 ANA_ASYNC_RST 4 4 ANA_ASYNC_RST_OVRD_EN 5 5 REF_VREG_FAST_START 6 6 REF_VREG_FAST_START_OVRD_EN 7 7 REF_VREG_REF_SEL 8 9 REF_VREG_REF_SEL_OVRD_EN 10 10 RESERVED_15_11 11 15 ixDPCSSYS_CR0_SUPX_DIG_ANA_MPLLA_PMIX_OVRD_OUT 2 0x8095 5 0 4294967295 MPLLA_PMIX_SEL 0 5 MPLLA_PMIX_EN 6 6 MPLLA_PMIX_SEL_OVRD_EN 7 7 MPLLA_PMIX_EN_OVRD_EN 8 8 RESERVED_15_9 9 15 ixDPCSSYS_CR0_SUPX_DIG_ANA_MPLLB_PMIX_OVRD_OUT 2 0x8096 5 0 4294967295 MPLLB_PMIX_SEL 0 5 MPLLB_PMIX_EN 6 6 MPLLB_PMIX_SEL_OVRD_EN 7 7 MPLLB_PMIX_EN_OVRD_EN 8 8 RESERVED_15_9 9 15 ixDPCSSYS_CR0_LANEX_DIG_ASIC_LANE_OVRD_IN 2 0x9000 5 0 4294967295 LANE_TX2RX_SER_LB 0 0 LANE_RX2TX_PAR_LB 1 1 EN 2 2 RX_ACJTAG_EN 3 3 RESERVED_15_4 4 15 ixDPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_0 2 0x9001 12 0 4294967295 REQ 0 0 REQ_OVRD_EN 1 1 PSTATE 2 3 PSTATE_OVRD_EN 4 4 RATE 5 7 RATE_OVRD_EN 8 8 WIDTH 9 10 WIDTH_OVRD_EN 11 11 MPLLB_SEL 12 12 MPLLB_SEL_OVRD_EN 13 13 DATA_EN 14 14 DATA_EN_OVRD_EN 15 15 ixDPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_1 2 0x9002 11 0 4294967295 NYQUIST_DATA 0 0 DISABLE 1 1 BEACON_EN 2 2 EN 3 3 TX_MAIN_CURSOR 4 9 MAIN_OVRD_EN 10 10 ASYNC_DRV_EN 11 11 ASYNC_DRV_OVRD_EN 12 12 TX_VREGDRV_BYP_OVRD 13 13 TX_VREGDRV_BYP_OVRD_EN 14 14 RESERVED_15_15 15 15 ixDPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_2 2 0x9003 6 0 4294967295 TX_PRE_CURSOR 0 5 PRE_OVRD_EN 6 6 TX_POST_CURSOR 7 12 POST_OVRD_EN 13 13 HDMIMODE_EN 14 14 HDMIMODE_ENABLE_OVRD_EN 15 15 ixDPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_3 2 0x9004 15 0 4294967295 CLK_RDY 0 0 CLK_RDY_OVRD_EN 1 1 DETECT_RX_REQ 2 2 DETECT_RX_REQ_OVRD_EN 3 3 INVERT 4 4 INVERT_OVRD_EN 5 5 LPD 6 6 LPD_OVRD_EN 7 7 TX_DC_COUP_EN 8 8 TX_DC_COUP_EN_OVRD_EN 9 9 PMA_EXTENDED_FIFO_EN 10 10 PMA_EXTENDED_FIFO_EN_OVRD_EN 11 11 TX_MPHY_MODE_EN 12 12 TX_MPHY_MODE_EN_OVRD_EN 13 13 RESERVED_15_14 14 15 ixDPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_4 2 0x9005 3 0 4294967295 RESET 0 0 RESET_OVRD_EN 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_OUT 2 0x9006 5 0 4294967295 TX_ACK 0 0 EN_TX_ACK 1 1 DETRX_RESULT 2 2 EN_DETRX_RESULT 3 3 RESERVED_15_4 4 15 ixDPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_0 2 0x9007 11 0 4294967295 REQ 0 0 REQ_OVRD_EN 1 1 DATA_EN 2 2 DATA_EN_OVRD_EN 3 3 PSTATE 4 5 PSTATE_OVRD_EN 6 6 RATE 7 8 RATE_OVRD_EN 9 9 WIDTH 10 11 WIDTH_OVRD_EN 12 12 RESERVED_15_13 13 15 ixDPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_1 2 0x9008 5 0 4294967295 RX_REF_LD_VAL_5_0 0 5 RX_CDR_VCO_LOWFREQ 6 6 EN 7 7 RX_REF_LD_VAL_6 8 8 RESERVED_15_9 9 15 ixDPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_2 2 0x9009 3 0 4294967295 RX_VCO_LD_VAL 0 12 EN 13 13 RESERVED_15_14 14 15 ixDPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_3 2 0x900a 11 0 4294967295 CDR_TRACK_EN 0 0 CDR_TRACK_EN_OVRD_EN 1 1 CDR_SSC_EN 2 2 CDR_SSC_EN_OVRD_EN 3 3 ALIGN_EN 4 4 ALIGN_EN_OVRD_EN 5 5 CLK_SHIFT 6 6 CLK_SHIFT_OVRD_EN 7 7 DISABLE 8 8 DISABLE_OVRD_EN 9 9 RESERVED_15_10 10 15 ixDPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_4 2 0x900b 11 0 4294967295 LPD 0 0 LPD_OVRD_EN 1 1 INVERT 2 2 INVERT_OVRD_EN 3 3 ADAPT_AFE_EN 4 4 ADAPT_DFE_EN 5 5 ADPT_OVRD_EN 6 6 TERM_EN 7 7 TERM_ACDC 8 8 TERM_OVRD_EN 9 9 RESERVED_15_10 10 15 ixDPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_5 2 0x900c 3 0 4294967295 RESET 0 0 RESET_OVRD_EN 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0 2 0x900d 4 0 4294967295 EQ_ATT_LVL 0 2 EQ_AFE_GAIN 3 6 RESERVED 7 10 EQ_CTLE_BOOST 11 15 ixDPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1 2 0x900e 3 0 4294967295 EQ_DFE_TAP2 0 6 EQ_DFE_TAP1 7 14 EQ_OVRD_EN 15 15 ixDPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_OUT_0 2 0x900f 9 0 4294967295 ACK 0 0 ACK_OVRD_EN 1 1 ADAPT_STS 2 3 ADAPT_STS_OVRD_EN 4 4 RX_ASYNC_DATA 5 5 RX_ASYNC_DATA_OVRD_EN 6 6 RX_SQ_WEAKKEEP_OUT 7 7 RX_SQ_WEAKKEEP_OUT_OVRD_EN 8 8 RESERVED_15_9 9 15 ixDPCSSYS_CR0_LANEX_DIG_ASIC_LANE_ASIC_IN 2 0x9010 3 0 4294967295 LANE_TX2RX_SER_LB 0 0 LANE_RX2TX_PAR_LB 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR0_LANEX_DIG_ASIC_TX_ASIC_IN_0 2 0x9011 12 0 4294967295 CLK_RDY 0 0 RESET 1 1 INVERT 2 2 DATA_EN 3 3 REQ 4 4 LPD 5 5 PSTATE 6 7 RATE 8 10 WIDTH 11 12 MPLLB_SEL 13 13 DETECT_RX_REQ 14 14 DISABLE 15 15 ixDPCSSYS_CR0_LANEX_DIG_ASIC_TX_ASIC_IN_1 2 0x9012 7 0 4294967295 BEACON_EN 0 0 TX_MAIN_CURSOR 1 6 TX_ASYNC_EN 7 7 TX_ASYNC_DATA 8 8 TX_ASYNC_DRV_EN 9 9 TX_VREGDRV_BYP 10 10 RESERVED_15_11 11 15 ixDPCSSYS_CR0_LANEX_DIG_ASIC_TX_ASIC_IN_2 2 0x9013 3 0 4294967295 TX_PRE_CURSOR 0 5 TX_POST_CURSOR 6 11 RESERVED_15_12 12 15 ixDPCSSYS_CR0_LANEX_DIG_ASIC_TX_ASIC_OUT 2 0x9014 3 0 4294967295 TX_ACK 0 0 DETRX_RESULT 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR0_LANEX_DIG_ASIC_RX_ASIC_IN_0 2 0x9015 13 0 4294967295 RESET 0 0 INVERT 1 1 DATA_EN 2 2 REQ 3 3 LPD 4 4 PSTATE 5 6 RATE 7 8 WIDTH 9 10 RESERVED 11 11 ADAPT_AFE_EN 12 12 ADAPT_DFE_EN 13 13 CDR_TRACK_EN 14 14 RESERVED_15_15 15 15 ixDPCSSYS_CR0_LANEX_DIG_ASIC_RX_ASIC_IN_1 2 0x9016 7 0 4294967295 CDR_SSC_EN 0 0 ALIGN_EN 1 1 CLK_SHIFT 2 2 DISABLE 3 3 RX_TERM_EN 4 4 RX_TERM_ACDC 5 5 RESERVED_15_6 6 15 ixDPCSSYS_CR0_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0 2 0x9017 4 0 4294967295 EQ_ATT_LVL 0 2 EQ_AFE_GAIN 3 6 RESERVED 7 10 EQ_CTLE_BOOST 11 15 ixDPCSSYS_CR0_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_1 2 0x9018 3 0 4294967295 EQ_DFE_TAP2 0 6 EQ_DFE_TAP1 7 14 RESERVED_15_15 15 15 ixDPCSSYS_CR0_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0 2 0x9019 3 0 4294967295 RX_CDR_VCO_LOWFREQ 0 0 RX_REF_LD_VAL 1 7 RESERVED_15_8 8 15 ixDPCSSYS_CR0_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1 2 0x901a 2 0 4294967295 RX_VCO_LD_VAL 0 12 RESERVED_15_13 13 15 ixDPCSSYS_CR0_LANEX_DIG_ASIC_RX_ASIC_OUT_0 2 0x901b 4 0 4294967295 ACK 0 0 VALID 1 1 ADAPT_STS 2 3 RESERVED_15_4 4 15 ixDPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_6 2 0x901c 10 0 4294967295 RX_PWM_CLK_SEL 0 1 RX_PWM_CLK_SEL_OVRD_EN 2 2 RX_TERM_LCC_ON 3 3 RX_TERM_LS_ON 4 4 RX_TERM_LS_LCC_ON_OVRD_EN 5 5 RX_TERM_CTL 6 7 RX_TERM_CTL_OVRD_EN 8 8 RX_PWM_EN 9 9 RX_PWM_EN_OVRD_EN 10 10 RESERVED_15_11 11 15 ixDPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_5 2 0x901d 15 0 4294967295 RPTR_EN_MASTER_LANE 0 0 RPTR_EN_MASTER_LANE_OVRD_EN 1 1 DIG_CLK_EN_OTHER_LANE 2 2 DIG_CLK_EN_OTHER_LANE_OVRD_EN 3 3 DIG_CLK_STATE_MASTER_LANE 4 4 DIG_CLK_STATE_MASTER_LANE_OVRD_EN 5 5 SHIFT_MASTER_LANE 6 6 SHIFT_MASTER_LANE_ORVD_EN 7 7 SHIFT_ACK_OTHER_LANE 8 8 SHIFT_ACK_OTHER_LANE_OVRD_EN 9 9 LANE_MASTER 10 10 LANE_MASTER_OVRD_IN_EN 11 11 TX_DWORD_CLK_SYNC_OVRD 12 12 TX_DWORD_CLK_SYNC_OVRD_EN 13 13 RESERVED_15_14 14 15 ixDPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_OUT_1 2 0x901e 11 0 4294967295 RPTR_EN_OUT 0 0 RPTR_EN_OUT_OVRD_EN 1 1 DIG_CLK_EN_OUT 2 2 DIG_CLK_EN_OUT_OVRD_EN 3 3 DIG_CLK_STATE_OUT 4 4 DIG_CLK_STATE_OUT_OVRD_EN 5 5 SHIFT_OUT 6 6 SHIFT_OUT_OVRD_EN 7 7 SHIFT_ACK_OUT 8 8 SHIFT_ACK_OUT_OVRD_EN 9 9 RESERVED_15_10 10 15 ixDPCSSYS_CR0_LANEX_DIG_ASIC_OCLA 2 0x901f 3 0 4294967295 RX_DWORD_OCLA_CLK_EN 0 0 RX_DWORD_OCLA_DATA_EN 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0 2 0x9020 11 0 4294967295 TX_P0_ANA_REFGEN_EN 0 0 TX_P0_ANA_VCM_HOLD 1 1 TX_P0_ANA_CLK_EN 2 2 TX_P0_ANA_WORD_CLK_EN 3 3 TX_P0_ANA_RESET 4 4 TX_P0_ANA_SERIAL_EN 5 5 TX_P0_DIG_CLK_EN 6 6 TX_P0_DATA_EN 7 7 TX_P0_ALLOW_RXDET 8 8 TX_P0_ANA_DCC_COMP_CAL_EN 9 9 RESERVED_15_10 10 15 ixDPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S 2 0x9021 11 0 4294967295 TX_P0S_ANA_REFGEN_EN 0 0 TX_P0S_ANA_VCM_HOLD 1 1 TX_P0S_ANA_CLK_EN 2 2 TX_P0S_ANA_WORD_CLK_EN 3 3 TX_P0S_ANA_RESET 4 4 TX_P0S_ANA_SERIAL_EN 5 5 TX_P0S_DIG_CLK_EN 6 6 TX_P0S_DATA_EN 7 7 TX_P0S_ALLOW_RXDET 8 8 TX_P0S_ANA_DCC_COMP_CAL_EN 9 9 RESERVED_15_10 10 15 ixDPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1 2 0x9022 11 0 4294967295 TX_P1_ANA_REFGEN_EN 0 0 TX_P1_ANA_VCM_HOLD 1 1 TX_P1_ANA_CLK_EN 2 2 TX_P1_ANA_WORD_CLK_EN 3 3 TX_P1_ANA_RESET 4 4 TX_P1_ANA_SERIAL_EN 5 5 TX_P1_DIG_CLK_EN 6 6 TX_P1_DATA_EN 7 7 TX_P1_ALLOW_RXDET 8 8 TX_P1_ANA_DCC_COMP_CAL_EN 9 9 RESERVED_15_10 10 15 ixDPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2 2 0x9023 12 0 4294967295 TX_P2_ANA_REFGEN_EN 0 0 TX_P2_ANA_VCM_HOLD 1 1 TX_P2_ANA_CLK_EN 2 2 TX_P2_ANA_WORD_CLK_EN 3 3 TX_P2_ANA_RESET 4 4 TX_P2_ANA_SERIAL_EN 5 5 TX_P2_DIG_CLK_EN 6 6 TX_P2_DATA_EN 7 7 TX_P2_ALLOW_RXDET 8 8 TX_P2_ALLOW_VBOOST 9 9 TX_P2_ANA_DCC_COMP_CAL_EN 10 10 RESERVED_15_11 11 15 ixDPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_0 2 0x9024 2 0 4294967295 TX_REFGEN_EN_TIME 0 7 TX_CLK_EN 8 15 ixDPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_1 2 0x9025 2 0 4294967295 TX_VCM_HOLD_TIME_14_0 0 14 SKIP_TX_VCM_HOLD_WAIT 15 15 ixDPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_2 2 0x9026 2 0 4294967295 TX_VBOOST_DIS_TIME_12_0 0 12 DTB_SEL 13 15 ixDPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_3 2 0x9027 3 0 4294967295 TX_VCM_HOLD_TIME_17_15 0 2 TX_VBOOST_DIS_TIME_13 3 3 RESERVED_15_4 4 15 ixDPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_4 2 0x9028 2 0 4294967295 TX_VCM_HOLD_GS_TIME 0 14 SKIP_TX_VCM_HOLD_GS_PULSE 15 15 ixDPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_5 2 0x9029 5 0 4294967295 TX_RXDET_TIME 0 9 FAST_TX_RXDET 10 10 TX_RESET_TIME 11 12 TX_SERIAL_EN_TIME 13 14 RESERVED_15_15 15 15 ixDPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_DCC_CR_BANK_ADDR 2 0x902a 1 0 4294967295 ADDR 0 15 ixDPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_DCC_CR_BANK_DATA 2 0x902b 1 0 4294967295 DATA 0 15 ixDPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_DCC_DAC_CTRL 2 0x902c 2 0 4294967295 CTRL 0 7 RESERVED_15_8 8 15 ixDPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_DCC_DAC_RANGE 2 0x902d 2 0 4294967295 CTRL 0 1 RESERVED_15_2 2 15 ixDPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_DCC_DAC_SEL 2 0x902e 6 0 4294967295 SEL 0 2 REQ 3 3 CTRL_UPD 4 4 RANGE_UPD 5 5 BIN_HOT 6 6 RESERVED_15_7 7 15 ixDPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_DCC_DAC_ACK 2 0x902f 2 0 4294967295 ACK 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_DCC_DAC_ADDR 2 0x9030 1 0 4294967295 ADDR 0 15 ixDPCSSYS_CR0_LANEX_DIG_TX_CLK_ALIGN_TX_CTL_0 2 0x9031 4 0 4294967295 TX_NUM_2UI_SHIFTS_16B_MODE 0 3 TX_NUM_2UI_SHIFTS_20B_MODE 4 7 TX_FIFO_BYPASS 8 8 RESERVED_15_9 9 15 ixDPCSSYS_CR0_LANEX_DIG_TX_LBERT_CTL 2 0x9032 4 0 4294967295 MODE 0 3 TRIGGER_ERR 4 4 PAT0 5 14 RESERVED_15_15 15 15 ixDPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0 2 0x9040 12 0 4294967295 RX_P0_ANA_AFE_EN 0 0 RX_P0_ANA_CLK_VREG_EN 1 1 RESERVED_1 2 2 RX_P0_ANA_CLK_EN 3 3 RESERVED_0 4 4 RX_P0_ANA_DESER_EN 5 5 RX_P0_ANA_CDR_EN 6 6 RX_P0_VCO_FREQ_RST 7 7 RX_P0_VCO_CAL_RST 8 8 RX_P0_VCO_CONTCAL_EN 9 9 RX_P0_DIG_CLK_EN 10 10 RESERVED_15_11 11 15 ixDPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S 2 0x9041 12 0 4294967295 RX_P0S_ANA_AFE_EN 0 0 RX_P0S_ANA_CLK_VREG_EN 1 1 RESERVED_2 2 2 RX_P0S_ANA_CLK_EN 3 3 RESERVED_4 4 4 RX_P0S_ANA_DESER_EN 5 5 RX_P0S_ANA_CDR_EN 6 6 RX_P0S_VCO_FREQ_RST 7 7 RX_P0S_VCO_CAL_RST 8 8 RX_P0S_VCO_CONTCAL_EN 9 9 RX_P0S_DIG_CLK_EN 10 10 RESERVED_15_11 11 15 ixDPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1 2 0x9042 12 0 4294967295 RX_P1_ANA_AFE_EN 0 0 RX_P1_ANA_CLK_VREG_EN 1 1 RESERVED_2 2 2 RX_P1_ANA_CLK_EN 3 3 RESERVED_4 4 4 RX_P1_ANA_DESER_EN 5 5 RX_P1_ANA_CDR_EN 6 6 RX_P1_VCO_FREQ_RST 7 7 RX_P1_VCO_CAL_RST 8 8 RX_P1_VCO_CONTCAL_EN 9 9 RX_P1_DIG_CLK_EN 10 10 RESERVED_15_11 11 15 ixDPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2 2 0x9043 12 0 4294967295 RX_P2_ANA_AFE_EN 0 0 RX_P2_ANA_CLK_VREG_EN 1 1 RESERVED_2 2 2 RX_P2_ANA_CLK_EN 3 3 RESERVED_4 4 4 RX_P2_ANA_DESER_EN 5 5 RX_P2_ANA_CDR_EN 6 6 RX_P2_VCO_FREQ_RST 7 7 RX_P2_VCO_CAL_RST 8 8 RX_P2_VCO_CONTCAL_EN 9 9 RX_P2_DIG_CLK_EN 10 10 RESERVED_15_11 11 15 ixDPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1 2 0x9045 5 0 4294967295 RX_AFE_EN_TIME 0 5 FAST_RX_AFE_EN 6 6 RX_VREG_EN_TIME 7 12 FAST_RX_VREG_EN 13 13 RESERVED_15_14 14 15 ixDPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_2 2 0x9046 4 0 4294967295 RX_CLK_EN_TIME 0 5 FAST_RX_CLK_EN 6 6 RX_FAST_START_TIME 7 10 RESERVED_15_11 11 15 ixDPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_3 2 0x9047 5 0 4294967295 RX_RATE_TIME 0 1 RSVD_3_7_2 2 7 RX_CDR_EN_TIME 8 11 RX_DESER_EN_TIME 12 13 RX_DESER_DIS_TIME 14 15 ixDPCSSYS_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0 2 0x9048 8 0 4294967295 INT_GAIN_CAL_FIXED_CNT 0 4 INT_GAIN_CAL_FIXED_CNT_EN 5 5 INT_GAIN_CAL_CNT_SHIFT 6 8 INT_GAIN_CAL_BOUNCE_CNT 9 11 DISABLE_BIN_HOLD 12 12 DISABLE_INT_GAIN_HOLD 13 13 DISABLE_COARSE_CALDONE 14 14 RESERVED_15_15 15 15 ixDPCSSYS_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1 2 0x9049 7 0 4294967295 RX_VCO_OVRD_SEL 0 0 RX_VCO_FREQ_RST 1 1 RX_VCO_CAL_RST 2 2 RX_VCO_CONTCAL_EN 3 3 DISABLE_INT_CAL_MODE 4 4 DPLL_CAL_UG 5 8 DTB_SEL 9 15 ixDPCSSYS_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2 2 0x904a 4 0 4294967295 FREQ_TUNE_START_VAL 0 9 FREQ_TUNE_CAL_STEPS 10 13 SKIP_RX_VCO_FREQ_TUNE_CAL 14 14 SKIP_RX_VCO_CAL 15 15 ixDPCSSYS_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0 2 0x904b 4 0 4294967295 RX_VCO_STARTUP_TIME 0 6 RX_VCO_UPDATE_TIME 7 10 RX_VCO_CNTR_PWRUP_TIME 11 14 FAST_RX_VCO_WAIT 15 15 ixDPCSSYS_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1 2 0x904c 2 0 4294967295 RX_VCO_CNTR_SETTLE_TIME 0 2 RESERVED_15_3 3 15 ixDPCSSYS_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0 2 0x904d 6 0 4294967295 RX_ANA_CDR_FREQ_TUNE 0 9 RX_ANA_VCO_CNTR_PD 10 10 RX_ANA_VCO_CNTR_EN 11 11 RX_ANA_CDR_STARTUP 12 12 RX_ANA_CDR_VCO_EN 13 13 RESERVED_15_14 14 15 ixDPCSSYS_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1 2 0x904e 7 0 4294967295 RX_VCO_FSM_STATE 0 3 RX_VCO_FREQ_RST 4 4 RX_VCO_CAL_RST 5 5 RX_VCO_CONTCAL_EN 6 6 RX_VCO_CAL_DONE 7 7 DPLL_FREQ_RST 8 8 RESERVED_15_9 9 15 ixDPCSSYS_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_2 2 0x904f 4 0 4294967295 VCO_CNTR_FINAL 0 12 VCOCLK_TOO_FAST 13 13 RX_VCO_CORRECT 14 14 RX_VCO_UP 15 15 ixDPCSSYS_CR0_LANEX_DIG_RX_RX_ALIGN_XAUI_COMM_MASK 2 0x9050 2 0 4294967295 XAUI_COMM_MASK 0 9 RESERVED_15_10 10 15 ixDPCSSYS_CR0_LANEX_DIG_RX_LBERT_CTL 2 0x9051 3 0 4294967295 MODE 0 3 SYNC 4 4 RESERVED_15_5 5 15 ixDPCSSYS_CR0_LANEX_DIG_RX_LBERT_ERR 2 0x9052 2 0 4294967295 COUNT 0 14 OV14 15 15 ixDPCSSYS_CR0_LANEX_DIG_RX_CDR_CDR_CTL_0 2 0x9053 7 0 4294967295 PHDET_EN 0 1 PHDET_EDGE 2 3 PHDET_POL 4 4 PHDET_EN_PR_MODE 5 5 ALWAYS_REALIGN 6 6 DTB_SEL 7 10 RESERVED_15_11 11 15 ixDPCSSYS_CR0_LANEX_DIG_RX_CDR_CDR_CTL_1 2 0x9054 2 0 4294967295 SSC_OFF_CNT0 0 9 SSC_OFF_CNT1 10 15 ixDPCSSYS_CR0_LANEX_DIG_RX_CDR_CDR_CTL_2 2 0x9055 2 0 4294967295 SSC_ON_CNT0 0 8 SSC_ON_CNT1 9 15 ixDPCSSYS_CR0_LANEX_DIG_RX_CDR_CDR_CTL_3 2 0x9056 6 0 4294967295 SSC_OFF_PHUG0 0 2 SSC_OFF_PHUG1 3 5 SSC_OFF_FRUG0 6 8 OVRD_DPLL_GAIN 9 9 PHUG_OVRD_VALUE 10 12 FRUG_OVRD_VALUE 13 15 ixDPCSSYS_CR0_LANEX_DIG_RX_CDR_CDR_CTL_4 2 0x9057 6 0 4294967295 SSC_OFF_FRUG1 0 2 SSC_ON_FRUG0 3 5 SSC_ON_FRUG1 6 8 SSC_ON_PHUG0 9 11 SSC_ON_PHUG1 12 14 RESERVED_15_15 15 15 ixDPCSSYS_CR0_LANEX_DIG_RX_CDR_STAT 2 0x9058 3 0 4294967295 PHUG_VALUE 0 2 FRUG_VALUE 3 5 RESERVED_15_6 6 15 ixDPCSSYS_CR0_LANEX_DIG_RX_DPLL_FREQ 2 0x9059 2 0 4294967295 VAL 0 13 RESERVED_15_14 14 15 ixDPCSSYS_CR0_LANEX_DIG_RX_DPLL_FREQ_BOUND_0 2 0x905a 3 0 4294967295 FREQ_BOUND_EN 0 0 UPPER_FREQ_BOUND 1 10 RESERVED_15_11 11 15 ixDPCSSYS_CR0_LANEX_DIG_RX_DPLL_FREQ_BOUND_1 2 0x905b 2 0 4294967295 LOWER_FREQ_BOUND 0 9 RESERVED_15_10 10 15 ixDPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_0 2 0x9060 4 0 4294967295 N_TOP_ASM1 0 9 N_TGG_ASM1 10 13 START_ASM1 14 14 ADPT_CLK_DIV4_EN 15 15 ixDPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1 2 0x9061 5 0 4294967295 N_WAIT_ASM1 0 6 FAST_AFE_DFE_SETTLE 7 7 CTLE_POLE_OVRD_VAL 8 10 CTLE_POLE_OVRD_EN 11 11 RESERVED_15_12 12 15 ixDPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_2 2 0x9062 3 0 4294967295 TGG_PTTRN_0 0 4 TGG_PTTRN_1 5 9 RESERVED_15_10 10 15 ixDPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3 2 0x9063 8 0 4294967295 CTLE_EN 0 4 VGA_EN 5 5 ATT_EN 6 6 DFE_EN 7 11 EYEHE_EN 12 12 EYEHO_EN 13 13 TGG_EN 14 14 ESL_TWICE_DSL 15 15 ixDPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_4 2 0x9064 4 0 4294967295 CTLE_TH 0 3 VGA_TH 4 7 DFE1_TH 8 11 DFE2_TH 12 15 ixDPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_5 2 0x9065 4 0 4294967295 DFE3_TH 0 3 DFE4_TH 4 7 DFE5_TH 8 11 TH_OFFSET 12 15 ixDPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6 2 0x9066 6 0 4294967295 CTLE_MU 0 2 VGA_MU 3 5 ATT_MU 6 8 VGA_SAT_CNT 9 11 VGA_SAT_CNT_STICKY 12 12 ATT_LOW_TH 13 15 ixDPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_7 2 0x9067 4 0 4294967295 VGA_MIN_SAT 0 4 VGA_LEV_HIGH 5 9 VGA_LEV_LOW 10 14 RESERVED_15_15 15 15 ixDPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8 2 0x9068 6 0 4294967295 DFE1_MU 0 2 DFE2_MU 3 5 DFE3_MU 6 8 DFE4_MU 9 11 DFE5_MU 12 14 RESERVED_15_15 15 15 ixDPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_9 2 0x9069 2 0 4294967295 ERR_SLE_ADPT_INIT 0 7 ERR_SLO_ADPT_INIT 8 15 ixDPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG 2 0x906a 6 0 4294967295 RST_ADPT_ATT 0 0 RST_ADPT_VGA 1 1 RST_ADPT_CTLE_BOOST 2 2 RST_ADPT_CTLE_POLE 3 3 RST_ADPT_TAP1 4 4 RESERVED_15_5 5 15 ixDPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ATT_STATUS 2 0x906b 3 0 4294967295 ATT_ADPT_CODE 0 7 ASM1_DON 8 8 RESERVED_15_9 9 15 ixDPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_VGA_STATUS 2 0x906c 3 0 4294967295 VGA_ADPT_CODE 0 9 ASM1_DONE 10 10 RESERVED_15_11 11 15 ixDPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_CTLE_STATUS 2 0x906d 4 0 4294967295 CTLE_BOOST_ADPT_CODE 0 9 CTLE_POLE_ADPT_CODE 10 12 ASM1_DONE 13 13 RESERVED_15_14 14 15 ixDPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_DFE_TAP1_STATUS 2 0x906e 3 0 4294967295 DFE_TAP1_ADPT_CODE 0 12 ASM1_DONE 13 13 RESERVED_15_14 14 15 ixDPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_DFE_TAP2_STATUS 2 0x906f 3 0 4294967295 DFE_TAP2_ADPT_CODE 0 11 ASM1_DONE 12 12 RESERVED_15_13 13 15 ixDPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_DFE_TAP3_STATUS 2 0x9070 3 0 4294967295 DFE_TAP3_ADPT_CODE 0 11 ASM1_DONE 12 12 RESERVED_15_13 13 15 ixDPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_DFE_TAP4_STATUS 2 0x9071 3 0 4294967295 DFE_TAP4_ADPT_CODE 0 11 ASM1_DONE 12 12 RESERVED_15_13 13 15 ixDPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_DFE_TAP5_STATUS 2 0x9072 3 0 4294967295 DFE_TAP5_ADPT_CODE 0 11 ASM1_DONE 12 12 RESERVED_15_13 13 15 ixDPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_DFE_DATA_EVEN_VDAC_OFST 2 0x9073 2 0 4294967295 DFE_DATA_EVEN_VDAC_OFST 0 7 RESERVED_15_8 8 15 ixDPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_DFE_DATA_ODD_VDAC_OFST 2 0x9074 2 0 4294967295 DFE_DATA_ODD_VDAC_OFST 0 7 RESERVED_15_8 8 15 ixDPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN 2 0x9075 2 0 4294967295 RX_ANA_SLICER_CTRL_E 0 3 RESERVED_15_4 4 15 ixDPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD 2 0x9076 2 0 4294967295 RX_ANA_SLICER_CTRL_O 0 3 RESERVED_15_4 4 15 ixDPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST 2 0x9077 2 0 4294967295 DFE_ERROR_EVEN_VDAC_OFST 0 7 RESERVED_15_8 8 15 ixDPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST 2 0x9078 2 0 4294967295 DFE_ERROR_ODD_VDAC_OFST 0 7 RESERVED_15_8 8 15 ixDPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL 2 0x9079 2 0 4294967295 E_SLO_LVL 0 7 E_SLE_LVL 8 15 ixDPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_RESET 2 0x907a 2 0 4294967295 RESET_ASM1 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1 2 0x907b 4 0 4294967295 DFE_T1_IDAC 0 4 DFE_T2_IDAC 5 9 DCC_START_IDAC 10 14 RESERVED_15_15 15 15 ixDPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2 2 0x907c 3 0 4294967295 DFE_DAT_EVEN_VDAC 0 4 DFE_DAT_ODD_VDAC 5 9 RESERVED_15_10 10 15 ixDPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3 2 0x907d 3 0 4294967295 DFE_ERR_EVEN_VDAC 0 4 DFE_ERR_ODD_VDAC 5 9 RESERVED_15_10 10 15 ixDPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_CR_BANK_ADDR 2 0x907e 1 0 4294967295 ADDR 0 15 ixDPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_CR_BANK_DATA 2 0x907f 1 0 4294967295 DATA 0 15 ixDPCSSYS_CR0_LANEX_DIG_RX_STAT_LD_VAL_1 2 0x9080 2 0 4294967295 SC1_LD_VAL 0 14 SC1_START 15 15 ixDPCSSYS_CR0_LANEX_DIG_RX_STAT_DATA_MSK 2 0x9081 1 0 4294967295 DATA_MSK_15_0 0 15 ixDPCSSYS_CR0_LANEX_DIG_RX_STAT_MATCH_CTL0 2 0x9082 4 0 4294967295 PTTRN_MSK_CR1A_4_0 0 4 PTTRN_CR1A_4_0 5 9 DATA_MSK_19_16 10 13 SCOPE_DLY 14 15 ixDPCSSYS_CR0_LANEX_DIG_RX_STAT_MATCH_CTL1 2 0x9083 5 0 4294967295 PTTRN_CR1B_EN 0 0 PTTRN_MSK_CR1B_4_0 1 5 PTTRN_CR1B_4_0 6 10 PTTRN_CR1A_ADPT_EN 11 11 RESERVED_15_12 12 15 ixDPCSSYS_CR0_LANEX_DIG_RX_STAT_STAT_CTL0 2 0x9084 10 0 4294967295 RESERVED_0 0 0 CORR_SHFT_SEL_VGA 1 1 CORR_SHFT_SEL 2 2 CORR_SRC_SEL 3 4 CORR_MODE_EN 5 5 STAT_SHFT_SEL 6 9 STAT_SRC_SEL 10 12 STAT_RXCLK_SEL 13 13 SC_TIMER_MODE 14 14 SKIP_EN 15 15 ixDPCSSYS_CR0_LANEX_DIG_RX_STAT_STAT_CTL1 2 0x9085 13 0 4294967295 STAT_CNT_0_EN 0 0 STAT_CNT_1_EN 1 1 STAT_CNT_2_EN 2 2 STAT_CNT_3_EN 3 3 STAT_CNT_4_EN 4 4 STAT_CNT_5_EN 5 5 STAT_CNT_6_EN 6 6 RESERVED_8_7 7 8 SC_PAUSE 9 9 STAT_CLK_EN 10 10 DATA_DLY_SEL 11 12 VLD_LOSS_CLR 13 13 VLD_CTL 14 15 ixDPCSSYS_CR0_LANEX_DIG_RX_STAT_SMPL_CNT1 2 0x9086 2 0 4294967295 SMPL_CNT1 0 14 SMPL_CNT1_DONE 15 15 ixDPCSSYS_CR0_LANEX_DIG_RX_STAT_STAT_CNT_0 2 0x9087 2 0 4294967295 STAT_CNT_0 0 14 SMPL_CNT1_DONE 15 15 ixDPCSSYS_CR0_LANEX_DIG_RX_STAT_STAT_CNT_1 2 0x9088 2 0 4294967295 STAT_CNT_1 0 14 SMPL_CNT1_DONE 15 15 ixDPCSSYS_CR0_LANEX_DIG_RX_STAT_STAT_CNT_2 2 0x9089 2 0 4294967295 STAT_CNT_2 0 14 SMPL_CNT1_DONE 15 15 ixDPCSSYS_CR0_LANEX_DIG_RX_STAT_STAT_CNT_3 2 0x908a 2 0 4294967295 STAT_CNT_3 0 14 SMPL_CNT1_DONE 15 15 ixDPCSSYS_CR0_LANEX_DIG_RX_STAT_STAT_CNT_4 2 0x908b 2 0 4294967295 STAT_CNT_4 0 14 SMPL_CNT1_DONE 15 15 ixDPCSSYS_CR0_LANEX_DIG_RX_STAT_STAT_CNT_5 2 0x908c 2 0 4294967295 STAT_CNT_5 0 14 SMPL_CNT1_DONE 15 15 ixDPCSSYS_CR0_LANEX_DIG_RX_STAT_STAT_CNT_6 2 0x908d 2 0 4294967295 STAT_CNT_6 0 14 SMPL_CNT1_DONE 15 15 ixDPCSSYS_CR0_LANEX_DIG_RX_STAT_CAL_COMP_CLK_CTL 2 0x908e 3 0 4294967295 PRECHRGE_CNT 0 2 REF_DIV_CNT 3 5 RESERVED_15_6 6 15 ixDPCSSYS_CR0_LANEX_DIG_RX_STAT_MATCH_CTL2 2 0x908f 2 0 4294967295 PTTRN_CR1A_19_5 0 14 RESERVED_15_15 15 15 ixDPCSSYS_CR0_LANEX_DIG_RX_STAT_MATCH_CTL3 2 0x9090 2 0 4294967295 PTTRN_MSK_CR1A_19_5 0 14 RESERVED_15_15 15 15 ixDPCSSYS_CR0_LANEX_DIG_RX_STAT_MATCH_CTL4 2 0x9091 2 0 4294967295 PTTRN_CR1B_19_5 0 14 RESERVED_15_15 15 15 ixDPCSSYS_CR0_LANEX_DIG_RX_STAT_MATCH_CTL5 2 0x9092 2 0 4294967295 PTTRN_MSK_CR1B_19_5 0 14 RESERVED_15_15 15 15 ixDPCSSYS_CR0_LANEX_DIG_RX_STAT_STAT_CTL2 2 0x9093 4 0 4294967295 DATA_DLY_SEL_2 0 0 SCOPE_DLY_2 1 1 DISABLE_SAMPLE_COUNT 2 2 RESERVED_15_3 3 15 ixDPCSSYS_CR0_LANEX_DIG_RX_STAT_STAT_STOP 2 0x9094 2 0 4294967295 SC1_STOP 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR0_LANEX_DIG_MPHY_RX_PWM_CTL 2 0x9095 3 0 4294967295 RX_PWM_POL 0 0 RX_PWM_DATA_POL 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR0_LANEX_DIG_MPHY_RX_TERM_LS_CTL 2 0x9096 2 0 4294967295 RX_TERM_LCC_CNT 0 2 RESERVED_15_3 3 15 ixDPCSSYS_CR0_LANEX_DIG_MPHY_RX_ANA_PWM_CLK_STABLE_CNT 2 0x9097 2 0 4294967295 PWM_CLK_STABLE_CNT 0 3 RESERVED_15_4 4 15 ixDPCSSYS_CR0_LANEX_DIG_ANA_TX_OVRD_OUT 2 0x90a0 15 0 4294967295 TX_ANA_CLK_SHIFT 0 0 TX_ANA_DATA_EN 1 1 TX_ANA_REFGEN_EN 2 2 TX_ANA_VCM_HOLD 3 3 TX_ANA_CLK_EN 4 4 TX_ANA_WORD_CLK_EN 5 5 TX_ANA_MPLLA_CLK_EN 6 6 TX_ANA_MPLLB_CLK_EN 7 7 TX_ANA_RESET 8 8 TX_ANA_SERIAL_EN 9 9 TX_ANA_DATA_RATE 10 11 RESERVED 12 12 TX_DIV4_EN 13 13 TX_RXDET_EN 14 14 TX_OVRD_EN 15 15 ixDPCSSYS_CR0_LANEX_DIG_ANA_TX_TERM_CODE_OVRD_OUT 2 0x90a1 5 0 4294967295 TX_TERM_CODE 0 9 TX_TERM_OVRD_EN 10 10 TX_DRV_SRC 11 12 TX_DRV_SRC_OVRD_EN 13 13 RESERVED_15_14 14 15 ixDPCSSYS_CR0_LANEX_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT 2 0x90a2 3 0 4294967295 TX_TERM_DN_CLK 0 0 TX_TERM_CLK_SELF_CLEAR_DISABLE 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR0_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_0 2 0x90a3 3 0 4294967295 TX_ANA_LOAD_CLK 0 0 TX_ANA_CTRL_LEG_PULL_EN_13_0 1 14 TX_EQ_OVRD_EN 15 15 ixDPCSSYS_CR0_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_1 2 0x90a4 2 0 4294967295 TX_ANA_CTRL_LEG_PULL_EN_19_14 0 5 RESERVED_15_6 6 15 ixDPCSSYS_CR0_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_2 2 0x90a5 4 0 4294967295 RESERVED 0 2 TX_ANA_CTRL_EQ_MUX_SEL 3 6 TX_ANA_CTRL_PRE 7 12 RESERVED_15_13 13 15 ixDPCSSYS_CR0_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_3 2 0x90a6 2 0 4294967295 TX_ANA_CTRL_POST 0 8 RESERVED_15_9 9 15 ixDPCSSYS_CR0_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_4 2 0x90a7 1 0 4294967295 TX_ANA_CTRL_LEG_PULL_DIR_19_4 0 15 ixDPCSSYS_CR0_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_5 2 0x90a8 2 0 4294967295 TX_ANA_CTRL_LEG_PULL_DIR_3_0 0 3 RESERVED_15_4 4 15 ixDPCSSYS_CR0_LANEX_DIG_ANA_RX_CTL_OVRD_OUT 2 0x90a9 9 0 4294967295 RESERVED 0 0 RX_ANA_DATA_RATE 1 2 RX_ANA_WORD_CLK_EN 3 3 RX_ANA_DIV4_EN 4 4 RX_ANA_DFE_TAPS_EN 5 5 RX_ANA_ADAPTATION_EN 6 6 RX_LBK_CLK_EN 7 7 RX_CTL_OVRD_EN 8 8 RESERVED_15_9 9 15 ixDPCSSYS_CR0_LANEX_DIG_ANA_RX_PWR_OVRD_OUT 2 0x90aa 9 0 4294967295 RX_ANA_AFE_EN 0 0 RX_ANA_CLK_VREG_EN 1 1 RX_ANA_CLK_DCC_EN 2 2 RX_ANA_CLK_EN 3 3 RX_ANA_CDR_EN 4 4 RX_ANA_DESERIAL_EN 5 5 RX_PWR_OVRD_EN 6 6 RX_ANA_FAST_START 7 7 RESERVED_15_8 8 15 ixDPCSSYS_CR0_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0 2 0x90ab 7 0 4294967295 RX_ANA_CDR_VCO_EN 0 0 RX_ANA_CDR_STARTUP 1 1 RX_VCO_CDR_OVRD_EN 2 2 RX_ANA_CDR_FREQ_TUNE 3 12 RX_ANA_VCO_CNTR_EN 13 13 RX_ANA_VCO_CNTR_CLK 14 14 RX_CDR_FREQ_TUNE_OVRD_EN 15 15 ixDPCSSYS_CR0_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_1 2 0x90ac 3 0 4294967295 RX_ANA_CDR_VCO_LOWFREQ 0 0 RX_ANA_VCO_CNTR_PD 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR0_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_2 2 0x90ad 3 0 4294967295 RX_ANA_CDR_FREQ_TUNE_CLK 0 0 CDR_FREQ_TUNE_CLK_SELF_CLEAR_DISABLE 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR0_LANEX_DIG_ANA_RX_CAL 2 0x90ae 7 0 4294967295 RX_ANA_CAL_MUXA_SEL 0 4 RX_ANA_CAL_MUXB_SEL 5 9 RX_ANA_CAL_LPFBYP_EN 10 10 RESERVED 11 11 RX_ANA_SLICER_CAL_EN 12 12 RX_ANA_CAL_MODE 13 14 RX_ANA_CAL_COMP_EN 15 15 ixDPCSSYS_CR0_LANEX_DIG_ANA_RX_DAC_CTRL 2 0x90af 2 0 4294967295 RX_ANA_CAL_DAC_CTRL 0 7 RESERVED_15_8 8 15 ixDPCSSYS_CR0_LANEX_DIG_ANA_RX_DAC_CTRL_OVRD 2 0x90b0 2 0 4294967295 RX_CAL_DAC_CTRL_OVRD 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR0_LANEX_DIG_ANA_RX_DAC_CTRL_SEL 2 0x90b1 2 0 4294967295 RX_ANA_CAL_DAC_CTRL_SEL 0 4 RESERVED_15_5 5 15 ixDPCSSYS_CR0_LANEX_DIG_ANA_RX_AFE_ATT_VGA 2 0x90b2 5 0 4294967295 RX_ANA_AFE_ATT_LVL 0 2 RX_ANA_AFE_GAIN 3 6 RESERVED 7 10 RX_AFE_OVRD_EN 11 11 RESERVED_15_12 12 15 ixDPCSSYS_CR0_LANEX_DIG_ANA_RX_AFE_CTLE 2 0x90b3 3 0 4294967295 RESERVED 0 2 RX_ANA_AFE_CTLE_BOOST 3 7 RESERVED_15_8 8 15 ixDPCSSYS_CR0_LANEX_DIG_ANA_RX_SCOPE 2 0x90b4 7 0 4294967295 RX_ANA_SCOPE_EN 0 0 RX_ANA_SCOPE_SEL 1 2 RX_ANA_SCOPE_PH_CLK 3 3 RX_ANA_SCOPE_PHASE 4 11 RX_ANA_SCOPE_CLK_EN 12 12 RX_SCOPE_SELF_CLEAR_DISABLE 13 13 RESERVED_15_14 14 15 ixDPCSSYS_CR0_LANEX_DIG_ANA_RX_SLICER_CTRL 2 0x90b5 4 0 4294967295 RX_ANA_SLICER_CTRL_E 0 3 RX_ANA_SLICER_CTRL_O 4 7 RX_ANA_SLICER_CTRL_OVRD_EN 8 8 RESERVED_15_9 9 15 ixDPCSSYS_CR0_LANEX_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST 2 0x90b6 2 0 4294967295 RX_ANA_IQ_PHASE_ADJUST 0 6 RESERVED_15_7 7 15 ixDPCSSYS_CR0_LANEX_DIG_ANA_RX_ANA_IQ_SENSE_EN 2 0x90b7 2 0 4294967295 RX_ANA_IQ_SENSE_EN 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR0_LANEX_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN 2 0x90b8 3 0 4294967295 RX_ANA_CAL_DAC_CTRL_EN 0 0 DAC_CTRL_SELF_CLEAR_DISABLE 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR0_LANEX_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE 2 0x90b9 3 0 4294967295 RX_ANA_AFE_UPDATE_EN 0 0 AFE_UPDATE_SELF_CLEAR_DISABLE 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR0_LANEX_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK 2 0x90ba 3 0 4294967295 RX_ANA_IQ_PHASE_ADJUST_CLK 0 0 PHASE_ADJUST_SELF_CLEAR_DISABLE 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR0_LANEX_DIG_ANA_STATUS_0 2 0x90bb 9 0 4294967295 TX_ANA_CLK_SHIFT_ACK 0 0 TX_ANA_RXDETP_RESULT 1 1 TX_ANA_RXDETM_RESULT 2 2 TX_ANA_LOOPBACK_EN 3 3 TX_ANA_CLK_LB_EN 4 4 RX_ANA_CAL_RESULT 5 5 RX_ANA_SCOPE_DATA 6 6 TX_ANA_DCC_CAL_RESULT 7 7 TX_ANA_CTRL_EQ_MUX 8 15 ixDPCSSYS_CR0_LANEX_DIG_ANA_STATUS_1 2 0x90bc 2 0 4294967295 RX_ANA_VCO_CNTR 0 12 RESERVED_15_13 13 15 ixDPCSSYS_CR0_LANEX_DIG_ANA_RX_TERM_CODE_OVRD_OUT 2 0x90bd 3 0 4294967295 RX_TERM_CODE 0 5 RX_TERM_OVRD_EN 6 6 RESERVED_15_7 7 15 ixDPCSSYS_CR0_LANEX_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT 2 0x90be 3 0 4294967295 RX_TERM_CLK 0 0 RX_TERM_CLK_SELF_CLEAR_DISABLE 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR0_LANEX_DIG_ANA_MPHY_OVRD_OUT 2 0x90bf 9 0 4294967295 RX_ANA_SQ_CTRL_TRESH 0 2 RX_ANA_SQ_CTRL_TRESH_OVRD_EN 3 3 RX_ANA_SQ_CTRL_RESP 4 5 RX_ANA_SQ_CTRL_RESP_OVRD_EN 6 6 RX_ANA_PWM_EN 7 7 RX_ANA_PWM_EN_OVRD_EN 8 8 RX_ANA_PWM_CLK_SEL 9 10 RX_ANA_PWM_CLK_SEL_OVRD_EN 11 11 RESERVED_15_12 12 15 ixDPCSSYS_CR0_LANEX_DIG_ANA_SIGDET_OVRD_OUT_1 2 0x90c0 7 0 4294967295 RX_ANA_SIGDET_HF_THRESH 0 2 RX_ANA_SIGDET_HF_THRESH_OVRD_EN 3 3 RX_ANA_SIGDET_HF_CAL_TUNE 4 9 RX_ANA_SIGDET_CAL_TUNE_OVRD_EN 10 10 RX_ANA_SIGDET_CAL_EN 11 11 RX_ANA_SIGDET_CAL_EN_OVRD_EN 12 12 RESERVED_15_13 13 15 ixDPCSSYS_CR0_LANEX_DIG_ANA_SIGDET_OVRD_OUT_2 2 0x90c1 7 0 4294967295 RX_ANA_SIGDET_LF_THRESH 0 2 RX_ANA_SIGDET_LF_THRESH_OVRD_EN 3 3 RX_ANA_SIGDET_LF_FILTER_EN 4 4 RX_ANA_SIGDET_LF_FILTER_EN_OVRD_EN 5 5 RX_ANA_SIGDET_CAL_TUNE 6 11 RX_ANA_SIGDET_CAL_TUNE_OVRD_EN 12 12 RESERVED_15_13 13 15 ixDPCSSYS_CR0_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT 2 0x90c2 8 0 4294967295 TX_ANA_DCC_CAL_RANGE 0 1 TX_ANA_DCC_CAL_RANGE_OVRD_EN 2 2 TX_ANA_DCC_CAL_COMP_EN 3 3 TX_ANA_DCC_CAL_COMP_EN_OVRD_EN 4 4 TX_ANA_DCC_CAL_CTRL 5 12 TX_ANA_DCC_CAL_CTRL_OVRD_EN 13 13 TX_ANA_DCC_CAL_CTRL_EN 14 14 TX_ANA_DCC_CAL_CTRL_EN_OVRD_EN 15 15 ixDPCSSYS_CR0_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2 2 0x90c3 5 0 4294967295 TX_ANA_DCC_CAL_CTRL_SEL 0 2 TX_ANA_DCC_CAL_CTRL_SEL_OVRD_EN 3 3 TX_ANA_DCC_CLK_COMP 4 4 TX_ANA_DCC_CLK_COMP_OVRD_EN 5 5 RESERVED_15_6 6 15 ixDPCSSYS_CR0_LANEX_DIG_ANA_TX_OVRD_OUT_2 2 0x90c4 6 0 4294967295 TX_ANA_FAST_START 0 0 TX_ANA_FAST_START_OVRD_EN 1 1 TX_CLK_LB_EN 2 2 TX_CLK_LB_EN_OVRD_EN 3 3 TX_ACJTAG_EN 4 4 RESERVED_15_5 5 15 ixDPCSSYS_CR0_LANEX_ANA_TX_OVRD_MEAS 2 0x90e0 9 0 4294967295 OVRD_CLK_SHIFT 0 0 CLK_SHIFT_REG 0 0 MEAS_ATB_CAL_MUX 0 0 MEAS_ATB_CAL_COMP 0 0 OVRD_VCM_HOLD 0 0 VCM_HOLD_REG 0 0 PULL_UP_REG 0 0 PULL_DN_REG 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR0_LANEX_ANA_TX_PWR_OVRD 2 0x90e1 9 0 4294967295 OVRD_TX_LOOPBACK 0 0 LOOPBACK_EN_REG 0 0 REFGEN_EN_REG 0 0 CLK_DIV_EN_REG 0 0 DATA_EN_REG_INT 0 0 CLK_EN_REG 0 0 SERIAL_EN_REG 0 0 OVRD_EN 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR0_LANEX_ANA_TX_ALT_BUS 2 0x90e2 6 0 4294967295 DRV_SOURCE_REG 0 0 OVRD_ALT_BUS 0 0 ATB_S_ENABLE 0 0 TX_ALT_RINGO 0 0 JTAG_DATA_REG 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR0_LANEX_ANA_TX_ATB1 2 0x90e3 9 0 4294967295 MEAS_ATB_GD 0 0 MEAS_ATB_VDDH 0 0 OVERRIDE_RXDETREF 0 0 MEAS_ATB_VPTX 0 0 OVERRIDE_REGREF 0 0 MEAS_ATB_VREG_DRV 0 0 MEAS_ATB_VREG 0 0 MEAS_ATB_VPH_HALF 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR0_LANEX_ANA_TX_ATB2 2 0x90e4 9 0 4294967295 MEAS_ATB_VCM 0 0 MEAS_ATB_CAL_VDAC_CM 0 0 MEAS_ATB_CAL_VDAC_DIFF 0 0 MEAS_ATB_TXM 0 0 MEAS_ATB_TXP 0 0 MEAS_ATB_RXDETREF 0 0 LFPS_HIGH_PRIORITY 0 0 OSC_DIV4_EN 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR0_LANEX_ANA_TX_DCC_DAC 2 0x90e5 2 0 4294967295 DCC_DAC_REG 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR0_LANEX_ANA_TX_DCC_CTRL1 2 0x90e6 7 0 4294967295 NC0 0 0 OVRD_DCC_DAC_CTRL_SEL 0 0 DCC_DAC_CTRL_SEL_REG 0 0 OVRD_DCC_DAC_CTRL_EN 0 0 DCC_DAC_CTRL_EN_REG 0 0 OVRD_DCC_DAC_REG 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR0_LANEX_ANA_TX_TERM_CODE 2 0x90e7 2 0 4294967295 TERM_CODE_REG_70 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR0_LANEX_ANA_TX_TERM_CODE_CTRL 2 0x90e8 8 0 4294967295 VREG_BOOST_1 0 0 OVRD_UPDATE_TERM 0 0 UPDATE_TERM_REG 0 0 OVRD_RESET_TERM 0 0 RESET_TERM_REG 0 0 OVRD_TERM_CODE 0 0 TERM_CODE_REG_98 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR0_LANEX_ANA_TX_OVRD_CLK 2 0x90e9 9 0 4294967295 VREG_BOOST_0 0 0 CLK_LB_EN_REG 0 0 OVRD_LB_EN 0 0 MPLLB_CLK_EN_REG 0 0 MPLLA_CLK_EN_REG 0 0 OVRD_MPLLAB_EN 0 0 WORD_CLK_EN_REG 0 0 OVRD_WORD_CLK_EN 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR0_LANEX_ANA_TX_MISC1 2 0x90ea 8 0 4294967295 MEAS_ATB_CAL_CLK_ALIGN 0 0 OVRD_DCC_DAC_CTRL_RANGE 0 0 DCC_DAC_CTRL_RANGE_REG 0 0 OVRD_VREF_SEL 0 0 VREF_SEL_REG 0 0 FORCE_ATB_TXM 0 0 FORCE_ATB_TXP 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR0_LANEX_ANA_TX_MISC2 2 0x90eb 8 0 4294967295 TX_PEAKING_LVL 0 0 VREG_CP_GAIN_CTRL 0 0 TX_SLEW_EN 0 0 EN_INV_POST 0 0 EN_INV_PRE 0 0 TX_VREG_EN_BYP 0 0 TX_VDRIVER_PULLDN_EN 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR0_LANEX_ANA_TX_MISC3 2 0x90ec 4 0 4294967295 TX_VREG_OVRD_RING_CTRL 0 0 TX_DCC_LOWV 0 0 NC7_2 2 7 RESERVED_15_8 8 15 ixDPCSSYS_CR0_LANEX_ANA_TX_RESERVED2 2 0x90ed 2 0 4294967295 NC7_0 0 7 RESERVED_15_8 8 15 ixDPCSSYS_CR0_LANEX_ANA_TX_RESERVED3 2 0x90ee 2 0 4294967295 NC7_0 0 7 RESERVED_15_8 8 15 ixDPCSSYS_CR0_LANEX_ANA_TX_RESERVED4 2 0x90ef 2 0 4294967295 NC7_0 0 7 RESERVED_15_8 8 15 ixDPCSSYS_CR0_LANEX_ANA_RX_CLK_1 2 0x90f0 8 0 4294967295 CDR_VCO_STARTUP_CODE 0 0 CDR_VCO_TEMP_COMP_EN 0 0 CDR_VCO_USE_UNCAL_BIAS 0 0 OVERRIDE_CDR_EN 0 0 OVRD_CLK_EN 0 0 CLK_EN_REG 0 0 NC7 7 7 RESERVED_15_8 8 15 ixDPCSSYS_CR0_LANEX_ANA_RX_CLK_2 2 0x90f1 5 0 4294967295 IQ_PHASE_ADJUST_REG 0 0 OVRD_IQ_PHASE_ADJUST 0 0 RX_LOOPBACK_CLK_REG 0 0 OVRD_RX_LOOPBACK_CLK 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR0_LANEX_ANA_RX_CDR_DES 2 0x90f2 7 0 4294967295 OVRD_WORD_CLK_EN 0 0 WORD_CLK_EN_REG 0 0 PHDET_ODD_REG 0 0 PHDET_EVEN_REG 0 0 SIGDET_VREF_EXT_EN 0 0 NC7_5 5 7 RESERVED_15_8 8 15 ixDPCSSYS_CR0_LANEX_ANA_RX_SLC_CTRL 2 0x90f3 3 0 4294967295 RX_SLICER_CTRL_O_REG 0 0 RX_SLICER_CTRL_E_REG 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR0_LANEX_ANA_RX_PWR_CTRL1 2 0x90f4 8 0 4294967295 OVRD_ACJT_EN 0 0 ACJT_EN_REG 0 0 OVRD_AFE_EN 0 0 AFE_EN_REG 0 0 AFE_CM_SEL 0 0 ATT_PULLDN_EN 0 0 NC7_7 7 7 RESERVED_15_8 8 15 ixDPCSSYS_CR0_LANEX_ANA_RX_PWR_CTRL2 2 0x90f5 9 0 4294967295 OVRD_DFE_EN 0 0 DFE_EN_REG 0 0 OVRD_DESERIAL_EN 0 0 DESERIAL_EN_REG 0 0 OVRD_LOOPBACK_EN 0 0 LOOPBACK_EN_REG 0 0 OVRD_FAST_START 0 0 FAST_START_REG 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR0_LANEX_ANA_RX_SQ 2 0x90f6 7 0 4294967295 SQ_CTRL_RESP_REG 0 0 OVRD_SQ_CTRL_RESP 0 0 NC4_3 3 4 SQ_CTRL_TRESH_REG 0 0 OVRD_SQ_CTRL_TRESH 0 0 AFE_LOOPBACK_SEL 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR0_LANEX_ANA_RX_CAL1 2 0x90f7 5 0 4294967295 DFE_TAPS_EN_REG 0 0 OVRD_DFE_TAPS_EN 0 0 CAL_MUXB_SEL_REG 0 0 OVRD_CAL_MUXB_SEL 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR0_LANEX_ANA_RX_CAL2 2 0x90f8 5 0 4294967295 AFE_PD_EQ_OFFSET 0 0 CAL_IDACS_USE_UNCAL 0 0 CAL_MUXA_SEL_REG 0 0 OVRD_CAL_MUXA_SEL 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR0_LANEX_ANA_RX_ATB_REGREF 2 0x90f9 8 0 4294967295 OVERRIDE_REGREF_VCO 0 0 OVERRIDE_REGREF_CLK 0 0 OVERRIDE_REGREF_IQC 0 0 BOOST_REGREF_IQC 0 0 OVRD_RX_SLICER_CTRL 0 0 OVRD_RX_TERM_AC_DCZ 0 0 RX_TERM_AC_DCZ_REG 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR0_LANEX_ANA_RX_ATB_MEAS1 2 0x90fa 9 0 4294967295 MASTER_ATB_EN 0 0 MEAS_ATB_VP 0 0 MEAS_ATB_GD 0 0 MEAS_ATB_VREG_VCO 0 0 MEAS_ATB_VREG_CLK 0 0 MEAS_ATB_VREG_IQC 0 0 REGS_FB_DIV_CTRL 0 0 RX_VREG_CLK_BYPASS 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR0_LANEX_ANA_RX_ATB_MEAS2 2 0x90fb 2 0 4294967295 MEAS_ATB_RX 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR0_LANEX_ANA_RX_ATB_MEAS3 2 0x90fc 7 0 4294967295 MEAS_ATB_CDR_VCO_GD 0 0 MEAS_ATB_CDR_VCO_VIREF_200U 0 0 MEAS_ATB_VIBIAS_CDR_VCO 0 0 MEAS_ATB_CDR_VCO_VOSC 0 0 MEAS_ATB_CAL_MUX 0 0 RX_VREG_OVERRIDE_RING_CTRL 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR0_LANEX_ANA_RX_ATB_MEAS4 2 0x90fd 3 0 4294967295 MEAS_ATB_CAL_VREF 0 0 NC7 7 7 RESERVED_15_8 8 15 ixDPCSSYS_CR0_LANEX_ANA_RX_ATB_FRC 2 0x90fe 2 0 4294967295 FRC_ATB_CAL_VREF 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR0_LANEX_ANA_RX_RESERVED1 2 0x90ff 2 0 4294967295 NC7_0 0 7 RESERVED_15_8 8 15 ixDPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN 2 0xe000 12 0 4294967295 PSTATE 0 1 LPD 2 2 WIDTH 3 4 RATE 5 7 MPLLB_SEL 8 8 MPLL_EN 9 9 OVRD_EN 10 10 MSTR_MPLLA_STATE 11 11 MSTR_MPLLB_STATE 12 12 MSTR_MPLL_OVRD_EN 13 13 TX_ASYNC_EN_OVR_VAL 14 14 TX_ASYNC_EN_OVR_EN 15 15 ixDPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1 2 0xe001 13 0 4294967295 RESET_OVRD_VAL 0 0 RESET_OVRD_EN 1 1 REQ_OVRD_VAL 2 2 REQ_OVRD_EN 3 3 DETRX_REQ_OVRD_VAL 4 4 DETRX_REQ_OVRD_EN 5 5 VBOOST_EN_OVRD_VAL 6 6 VBOOST_EN_OVRD_EN 7 7 IBOOST_LVL_OVRD_VAL 8 11 IBOOST_LVL_OVRD_EN 12 12 TX_BEACON_EN_OVR_VAL 13 13 TX_BEACON_EN_OVR_EN 14 14 RESERVED_15_15 15 15 ixDPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_PCS_IN 2 0xe002 12 0 4294967295 RESET 0 0 REQ 1 1 PSTATE 2 3 LPD 4 4 WIDTH 5 6 RATE 7 9 MPLLB_SEL 10 10 MPLL_EN 11 11 MSTR_MPLLA_STATE 12 12 MSTR_MPLLB_STATE 13 13 DETRX_REQ 14 14 RESERVED_15_15 15 15 ixDPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_OVRD_OUT 2 0xe003 6 0 4294967295 ACK 0 0 DETRX_RESULT 1 1 EN_CTL 2 2 TX_DWORD_CLK_SYNC_OVRD_VAL 3 3 TX_DWORD_CLK_SYNC_OVRD_EN 4 4 RESERVED_15_5 5 15 ixDPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_PCS_OUT 2 0xe004 2 0 4294967295 ACK 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN 2 0xe005 12 0 4294967295 RATE 0 1 WIDTH 2 3 PSTATE 4 5 LPD 6 6 OVRD_EN 7 7 ADAPT_AFE_EN 8 8 ADAPT_DFE_EN 9 9 LANE_RX2TX_PAR_LB_EN_OVRD_VAL 10 10 LANE_RX2TX_PAR_LB_EN_OVRD_EN 11 11 RX_DATA_EN_OVRD_VAL_R 12 12 RX_DATA_EN_OVRD_EN_R 13 13 RESERVED_15_14 14 15 ixDPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1 2 0xe006 12 0 4294967295 RESET_OVRD_VAL 0 0 RESET_OVRD_EN 1 1 REQ_OVRD_VAL 2 2 REQ_OVRD_EN 3 3 RX_LOS_THRSHLD_OVRD_VAL 4 6 RX_LOS_THRSHLD_OVRD_EN 7 7 ADAPT_REQ 8 8 ADAPT_REQ_OVRD_EN 9 9 ADAPT_CONT 10 10 OFFCAN_CONT 11 11 CONT_OVRD_EN 12 12 RESERVED_15_13 13 15 ixDPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_2 2 0xe007 4 0 4294967295 VCO_LD_VAL_OVRD 0 12 VCO_LD_VAL_OVRD_EN 13 13 VCO_LOWFREQ_VAL_OVRD 14 14 VCO_LOWFREQ_VAL_OVRD_EN 15 15 ixDPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_3 2 0xe008 3 0 4294967295 REF_LD_VAL_OVRD 0 6 REF_LD_VAL_OVRD_EN 7 7 RESERVED_15_8 8 15 ixDPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_PCS_IN 2 0xe009 13 0 4294967295 REQ 0 0 RATE 1 2 WIDTH 3 4 PSTATE 5 6 LPD 7 7 CDR_VCO_LOWFREQ 8 8 ADAPT_AFE_EN 9 9 ADAPT_DFE_EN 10 10 ADAPT_REQ 11 11 ADAPT_CONT 12 12 OFFCAN_CONT 13 13 RESET 14 14 RESERVED_15_15 15 15 ixDPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_1 2 0xe00a 2 0 4294967295 REF_LD_VAL 0 6 RESERVED_15_7 7 15 ixDPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_2 2 0xe00b 2 0 4294967295 VCO_LD_VAL 0 12 RESERVED_15_13 13 15 ixDPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_3 2 0xe00c 4 0 4294967295 EQ_ATT_LVL 0 2 EQ_VGA1_GAIN 3 6 EQ_VGA2_GAIN 7 10 EQ_CTLE_BOOST 11 15 ixDPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_4 2 0xe00d 3 0 4294967295 EQ_CTLE_POLE 0 2 EQ_DFE_TAP1 3 10 RESERVED_15_11 11 15 ixDPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT 2 0xe00e 3 0 4294967295 ACK 0 0 EN_CTL 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_PCS_OUT 2 0xe00f 2 0 4294967295 ACK 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_ADAPT_ACK 2 0xe010 2 0 4294967295 RX_ADAPT_ACK 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_ADAPT_FOM 2 0xe011 2 0 4294967295 RX_ADAPT_FOM 0 7 RESERVED_15_8 8 15 ixDPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_TXPRE_DIR 2 0xe012 2 0 4294967295 RX_TXPRE_DIR 0 1 RESERVED_15_2 2 15 ixDPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_TXMAIN_DIR 2 0xe013 2 0 4294967295 RX_TXMAIN_DIR 0 1 RESERVED_15_2 2 15 ixDPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_TXPOST_DIR 2 0xe014 2 0 4294967295 RX_TXPOST_DIR 0 1 RESERVED_15_2 2 15 ixDPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_LANE_NUMBER 2 0xe015 2 0 4294967295 LANE_NUMBER 0 3 RESERVED_15_4 4 15 ixDPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RESERVED_1 2 0xe016 1 0 4294967295 RESERVED_REG_1 0 15 ixDPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RESERVED_2 2 0xe017 1 0 4294967295 RESERVED_REG_2 0 15 ixDPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN 2 0xe018 16 0 4294967295 RX_RESET_ATE_OVRD_VAL 0 0 RX_RESET_ATE_OVRD_EN 1 1 TX_RESET_ATE_OVRD_VAL 2 2 TX_RESET_ATE_OVRD_EN 3 3 RX_REQ_ATE_OVRD_VAL 4 4 RX_REQ_ATE_OVRD_EN 5 5 TX_REQ_ATE_OVRD_VAL 6 6 TX_REQ_ATE_OVRD_EN 7 7 RX_ADAPT_AFE_EN_OVRD_VAL 8 8 RX_ADAPT_AFE_EN_OVRD_EN 9 9 RX_ADAPT_DFE_EN_OVRD_VAL 10 10 RX_ADAPT_DFE_EN_OVRD_EN 11 11 TX_DATA_EN_ATE_OVRD_VAL 12 12 TX_DATA_EN_ATE_OVRD_EN 13 13 RX_DATA_EN_ATE_OVRD_VAL 14 14 RX_DATA_EN_ATE_OVRD_EN 15 15 ixDPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN 2 0xe019 3 0 4294967295 RX_EQ_DELTA_IQ_OVRD_VAL 0 3 RX_EQ_DELTA_IQ_OVRD_EN 4 4 RESERVED_15_5 5 15 ixDPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN 2 0xe01a 5 0 4294967295 RX_TERM_CTRL_OVRD_VAL 0 2 RX_TERM_CTRL_OVRD_EN 3 3 TX_TERM_CTRL_OVRD_VAL 4 6 TX_TERM_CTRL_OVRD_EN 7 7 RESERVED_15_8 8 15 ixDPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TXRX_TERM_CTRL_IN 2 0xe01b 3 0 4294967295 RX_TERM_CTRL 0 2 TX_TERM_CTRL 3 5 RESERVED_15_6 6 15 ixDPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT_1 2 0xe01c 2 0 4294967295 RX_CLK_EN 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_EQ_OVRD_IN_1 2 0xe01d 4 0 4294967295 RX_EQ_AFE_GAIN_OVRD_VAL 0 3 RX_EQ_ATT_LVL_OVRD_VAL 4 6 RX_EQ_OVRD_EN 7 7 RESERVED_15_8 8 15 ixDPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_EQ_OVRD_IN_2 2 0xe01e 3 0 4294967295 RX_EQ_DFE_TAP1_OVRD_VAL 0 7 RX_EQ_CTLE_BOOST_OVRD_VAL 8 12 RESERVED_15_13 13 15 ixDPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_PH2_CAL 2 0xe01f 4 0 4294967295 PH2_CAL_ACK_VAL 0 0 PH2_CAL_REQ_VAL 1 1 PH2_CAL_REQ_OVRD_VAL 2 2 RESERVED_15_3 3 15 ixDPCSSYS_CR0_RAWLANEX_DIG_FSM_FSM_OVRD_CTL 2 0xe020 5 0 4294967295 FSM_JMP_ADDR 0 11 FSM_JMP_EN 12 12 FSM_CMD_START 13 13 FSM_OVRD_EN 14 14 FSM_BREAK 15 15 ixDPCSSYS_CR0_RAWLANEX_DIG_FSM_MEM_ADDR_MON 2 0xe021 1 0 4294967295 MEM_ADDR 0 15 ixDPCSSYS_CR0_RAWLANEX_DIG_FSM_STATUS_MON 2 0xe022 8 0 4294967295 STATE 0 4 CMD_RDY 5 5 ALU_OVFLW 6 6 ALU_RES_EQ0 7 7 WAIT_CNT_EQ0 8 8 WRMSK_DISABLED 9 9 RDMSK_DISABLED 10 10 RESERVED_15_11 11 15 ixDPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_RX_STARTUP_CAL 2 0xe023 2 0 4294967295 FAST_RX_STARTUP_CAL 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_RX_ADAPT 2 0xe024 2 0 4294967295 FAST_RX_ADAPT 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_RX_AFE_CAL 2 0xe025 2 0 4294967295 FAST_RX_AFE_CAL 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_RX_DFE_CAL 2 0xe026 2 0 4294967295 FAST_RX_DFE_CAL 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_RX_BYPASS_CAL 2 0xe027 2 0 4294967295 FAST_RX_BYPASS_CAL 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_RX_REFLVL_CAL 2 0xe028 2 0 4294967295 FAST_RX_REFLVL_CAL 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_RX_IQ_CAL 2 0xe029 2 0 4294967295 FAST_RX_IQ_CAL 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_RX_AFE_ADAPT 2 0xe02a 2 0 4294967295 FAST_RX_AFE_ADAPT 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_RX_DFE_ADAPT 2 0xe02b 2 0 4294967295 FAST_RX_DFE_ADAPT 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_SUP 2 0xe02c 2 0 4294967295 FAST_SUP 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_TX_CMN_MODE 2 0xe02d 2 0 4294967295 FAST_TX_CMN_MODE 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_TX_RXDET 2 0xe02e 2 0 4294967295 FAST_TX_RXDET 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_RX_PWRUP 2 0xe02f 2 0 4294967295 FAST_RX_PWRUP 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_RX_VCO_WAIT 2 0xe030 2 0 4294967295 FAST_RX_VCO_WAIT 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_RX_VCO_CAL 2 0xe031 2 0 4294967295 FAST_RX_VCO_CAL 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR0_RAWLANEX_DIG_FSM_CMNCAL_MPLL_STATUS 2 0xe032 3 0 4294967295 CMNCAL_MPLL_INIT 0 0 CMNCAL_MPLL_DONE 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_RX_CONT_CAL_ADAPT 2 0xe033 2 0 4294967295 FAST_RX_CONT_CAL_ADAPT 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_RX_CONT_ADAPT 2 0xe034 2 0 4294967295 FAST_RX_CONT_ADAPT 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_RX_CONT_DATA_CAL 2 0xe035 2 0 4294967295 FAST_RX_CONT_DATA_CAL 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_RX_CONT_PHASE_CAL 2 0xe036 2 0 4294967295 FAST_RX_CONT_PHASE_CAL 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_RX_CONT_AFE_CAL 2 0xe037 2 0 4294967295 FAST_RX_CONT_AFE_CAL 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_FLAGS 2 0xe038 12 0 4294967295 TX_FAST_DCC_CAL 0 0 RX_FAST_DCC_CAL 1 1 RX_FAST_VPHUD_CAL 2 2 RX_FAST_VREF_CAL 3 3 RX_FAST_SIGDET_CAL 4 4 RESERVED_2 5 7 TX_FAST_CONT_DCC_CAL 8 8 RX_FAST_CONT_DCC_CAL 9 9 RX_FAST_CONT_VPHUD_CAL 10 10 RX_FAST_CONT_VREF_CAL 11 11 RESERVED_1 12 14 TX_SKIP_SUP_CAL 15 15 ixDPCSSYS_CR0_RAWLANEX_DIG_FSM_CR_LOCK 2 0xe039 3 0 4294967295 CR_REG_LOCK 0 0 CR_MEM_LOCK 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR0_RAWLANEX_DIG_FSM_TX_DCC_FLAGS 2 0xe03a 4 0 4294967295 RATE 0 0 DIV 1 1 MPLL 2 2 RESERVED_15_3 3 15 ixDPCSSYS_CR0_RAWLANEX_DIG_FSM_TX_DCC_STATUS 2 0xe03b 2 0 4294967295 FLAG 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR0_RAWLANEX_DIG_FSM_OCLA 2 0xe03c 4 0 4294967295 PC_EN 0 0 REG_BANK1_EN 1 1 REG_BANK2_EN 2 2 RESERVED_15_3 3 15 ixDPCSSYS_CR0_RAWLANEX_DIG_FSM_TX_EQ_UPDATE_FLAG 2 0xe03d 2 0 4294967295 TX_EQ_UPDATE_FLAG 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR0_RAWLANEX_DIG_FSM_CMNCAL_RCAL_STATUS 2 0xe03e 3 0 4294967295 CMNCAL_RCAL_INIT 0 0 CMNCAL_RCAL_DONE 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR0_RAWLANEX_DIG_FSM_RX_IQ_PHASE_OFFSET 2 0xe03f 2 0 4294967295 RX_IQ_PHASE_OFFSET 0 3 RESERVED_15_4 4 15 ixDPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_RESET_RTN_REQ 2 0xe040 2 0 4294967295 RESET_RTN_REQ 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_RX_RESET_IRQ 2 0xe041 2 0 4294967295 RX_RESET 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_RX_REQ_IRQ 2 0xe042 2 0 4294967295 RX_REQ 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_RX_RATE_IRQ 2 0xe043 2 0 4294967295 RX_RATE_IRQ 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_RX_PSTATE_IRQ 2 0xe044 2 0 4294967295 RX_PSTATE_IRQ 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ 2 0xe045 2 0 4294967295 RX_ADAPT_REQ_IRQ 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ 2 0xe046 2 0 4294967295 RX_ADAPT_DIS_IRQ 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_RX_RESET_IRQ_CLR 2 0xe047 2 0 4294967295 RX_RESET_IRQ_CLR 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_RX_REQ_IRQ_CLR 2 0xe048 2 0 4294967295 RX_REQ_IRQ_CLR 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_RX_RATE_IRQ_CLR 2 0xe049 2 0 4294967295 RX_RATE_IRQ_CLR 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR 2 0xe04a 2 0 4294967295 RX_PSTATE_IRQ_CLR 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR 2 0xe04b 2 0 4294967295 RX_ADAPT_REQ_IRQ_CLR 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR 2 0xe04c 2 0 4294967295 RX_ADAPT_DIS_IRQ_CLR 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK 2 0xe04d 12 0 4294967295 RX_REQ_IRQ_MSK 0 0 RX_RATE_IRQ_MSK 1 1 RX_PSTATE_IRQ_MSK 2 2 RX_ADAPT_REQ_IRQ_MSK 3 3 RX_ADAPT_DIS_IRQ_MSK 4 4 RX_RESET_IRQ_MSK 5 5 LANE_XCVR_MODE_IRQ_MSK 6 6 RX_PH2_CAL_REQ_IRQ_MSK 7 7 RX_PH2_CAL_DIS_IRQ_MSK 8 8 LANE_RX2TX_SER_LB_EN_IRQ_MSK 9 9 DCC_ONDMD_IRQ_MSK 10 10 RESERVED_15_11 11 15 ixDPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK_2 2 0xe04e 3 0 4294967295 TX_RESET_IRQ_MSK 0 0 TX_REQ_IRQ_MSK 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ 2 0xe04f 2 0 4294967295 LANE_XCVR_MODE_IRQ 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR 2 0xe050 2 0 4294967295 LANE_XCVR_MODE_IRQ_CLR 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ 2 0xe051 2 0 4294967295 RX_PH2_CAL_REQ_IRQ 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ 2 0xe052 2 0 4294967295 RX_PH2_CAL_DIS_IRQ 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR 2 0xe053 2 0 4294967295 RX_PH2_CAL_REQ_IRQ_CLR 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR 2 0xe054 2 0 4294967295 RX_PH2_CAL_DIS_IRQ_CLR 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ 2 0xe055 2 0 4294967295 LANE_RX2TX_SER_LB_EN_IRQ 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR 2 0xe056 2 0 4294967295 LANE_RX2TX_SER_LB_EN_IRQ_CLR 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_DCC_ONDMD_IRQ 2 0xe057 2 0 4294967295 IRQ 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_TX_RESET_IRQ 2 0xe058 2 0 4294967295 TX_RESET 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_TX_REQ_IRQ 2 0xe059 2 0 4294967295 TX_REQ 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_TX_RESET_IRQ_CLR 2 0xe05a 2 0 4294967295 TX_RESET_IRQ_CLR 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_TX_REQ_IRQ_CLR 2 0xe05b 2 0 4294967295 TX_REQ_IRQ_CLR 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_LANE_OVRD_IN 2 0xe060 4 0 4294967295 LANE_MPLLA_EN_IN 0 0 LANE_MPLLB_EN_IN 1 1 LANE_OVRD_EN 2 2 RESERVED_15_3 3 15 ixDPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_LANE_OVRD_OUT 2 0xe061 4 0 4294967295 LANE_MPLLA_EN_OUT 0 0 LANE_MPLLB_EN_OUT 1 1 LANE_OVRD_EN 2 2 RESERVED_15_3 3 15 ixDPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_SUP_OVRD_IN 2 0xe062 4 0 4294967295 MPLLA_STATE 0 0 MPLLB_STATE 1 1 SUP_STATE_OVRD_EN 2 2 RESERVED_15_3 3 15 ixDPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_SUP_PMA_IN 2 0xe063 3 0 4294967295 MPLLA_STATE 0 0 MPLLB_STATE 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT 2 0xe064 16 0 4294967295 TX_REQ_OVRD_VAL 0 0 TX_REQ_OVRD_EN 1 1 TX_RESET_OVRD_VAL 2 2 TX_RESET_OVRD_EN 3 3 TX_BEACON_EN_OVRD_VAL 4 4 TX_BEACON_EN_OVRD_EN 5 5 TX_ASYNC_DRV_EN_OVRD_VAL 6 6 TX_ASYNC_DRV_EN_OVRD_EN 7 7 TX_ASYNC_EN_OVRD_VAL 8 8 TX_ASYNC_EN_OVRD_EN 9 9 TX_DWORD_CLK_SYNC_OVRD_VAL 10 10 TX_DWORD_CLK_SYNC_OVRD_EN 11 11 LANE_TX2RX_SER_LB_EN_OVRD_VAL 12 12 LANE_TX2RX_SER_LB_EN_OVRD_EN 13 13 TX_PMA_DATA_EN_OVRD_VAL_R 14 14 TX_PMA_DATA_EN_OVRD_EN_R 15 15 ixDPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_TX_PMA_IN 2 0xe065 2 0 4294967295 ACK 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT 2 0xe066 9 0 4294967295 RX_REQ_OVRD_VAL 0 0 RX_REQ_OVRD_EN 1 1 RX_RESET_OVRD_VAL 2 2 RX_RESET_OVRD_EN 3 3 LANE_RX2TX_PAR_LB_EN_OVRD_VAL 4 4 LANE_RX2TX_PAR_LB_EN_OVRD_EN 5 5 RX_PMA_DATA_EN_OVRD_VAL_R 6 6 RX_PMA_DATA_EN_OVRD_EN_R 7 7 RESERVED_15_8 8 15 ixDPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_RX_PMA_IN 2 0xe067 2 0 4294967295 ACK 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_LANE_RTUNE_CTL 2 0xe068 2 0 4294967295 LANE_RTUNE_REQ 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_SUP_PMA_IN_1 2 0xe069 2 0 4294967295 RTUNE_ACK 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_IN 2 0xe06a 9 0 4294967295 RX_PMA_PWM_WORD_CLK_R 0 0 RX_PMA_PWM_WORD_CLK_OVRD_EN 1 1 RX_PMA_PWM_DATA_R 2 2 RX_PMA_PWM_DATA_OVRD_EN 3 3 RX_PMA_PWM_CLK_R 4 4 RX_PMA_PWM_CLK_OVRD_EN 5 5 RX_PMA_TERM_CTL_R 6 7 RX_PMA_TERM_CTL_OVRD_EN 8 8 RESERVED_15_9 9 15 ixDPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_OUT 2 0xe06b 7 0 4294967295 RX_PMA_PWM_EN 0 0 RX_PMA_PWM_EN_OVRD_EN 1 1 RX_PMA_PWM_CLK_SEL 2 3 RX_PMA_PWM_CLK_SEL_OVRD_EN 4 4 RX_PMA_ASYNC_EN 5 5 RX_PMA_ASYNC_EN_OVRD_EN 6 6 RESERVED_15_7 7 15 ixDPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_RX_ADAPT_OVRD_OUT 2 0xe06c 3 0 4294967295 RX_PMA_IQ_PHASE_ADJUST_MAP_OVRD_VAL 0 6 RX_PMA_IQ_PHASE_ADJUST_MAP_OVRD_EN 7 7 RESERVED_15_8 8 15 ixDPCSSYS_CR0_RAWLANEX_DIG_TX_CTL_TX_FSM_CTL 2 0xe080 6 0 4294967295 TX_WAIT_MPLL_OFF_TIME 0 6 TX_P2_ALLOW_RXDET 7 7 TX_P1_ALLOW_RXDET 8 8 TX_P0S_ALLOW_RXDET 9 9 TX_P0_ALLOW_RXDET 10 10 RESERVED_15_11 11 15 ixDPCSSYS_CR0_RAWLANEX_DIG_TX_CTL_TX_CLK_CTL 2 0xe081 4 0 4294967295 TX_CLK_EN 0 0 TX_CLK_SEL 1 4 ASYNC_BEACON_WAIT_TIME 5 10 RESERVED_15_11 11 15 ixDPCSSYS_CR0_RAWLANEX_DIG_TX_CTL_TX_DCC_CONT_STATUS 2 0xe082 2 0 4294967295 ENABLE 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR0_RAWLANEX_DIG_TX_CTL_OCLA 2 0xe083 2 0 4294967295 FSM_EN 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR0_RAWLANEX_DIG_TX_CTL_UPCS_OCLA 2 0xe084 3 0 4294967295 DATA_EN 0 1 CLK_EN 2 2 RESERVED_15_3 3 15 ixDPCSSYS_CR0_RAWLANEX_DIG_RX_CTL_RX_FSM_CTL 2 0xe0a0 3 0 4294967295 EN_RX_CTL_FSM 0 0 RATE_CHG_IN_P1 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR0_RAWLANEX_DIG_RX_CTL_RX_LOS_MASK_CTL 2 0xe0a1 2 0 4294967295 RX_LOS_MASK_CNT 0 8 RESERVED_15_9 9 15 ixDPCSSYS_CR0_RAWLANEX_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL 2 0xe0a2 2 0 4294967295 RX_DATA_EN_OVRD_CNT 0 4 INT_REF_TRCK_CNT 5 15 ixDPCSSYS_CR0_RAWLANEX_DIG_RX_CTL_OFFCAN_CONT_STATUS 2 0xe0a3 2 0 4294967295 ENABLE 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR0_RAWLANEX_DIG_RX_CTL_ADAPT_CONT_STATUS 2 0xe0a4 2 0 4294967295 ENABLE 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR0_RAWLANEX_DIG_RX_CTL_UPCS_OCLA 2 0xe0a5 3 0 4294967295 DATA_EN 0 2 CLK_EN 3 3 RESERVED_15_4 4 15 ixDPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN 2 0xe0c0 11 0 4294967295 RATE_OVRD_VAL 0 1 RATE_OVRD_EN 2 2 WIDTH_OVRD_VAL 3 4 WIDTH_OVRD_EN 5 5 PSTATE_OVRD_VAL 6 7 PSTATE_OVRD_EN 8 8 LPD_OVRD_VAL 9 9 LPD_OVRD_EN 10 10 LANE_RX2TX_PAR_LB_EN_OVRD_VAL 11 11 LANE_RX2TX_PAR_LB_EN_OVRD_EN 12 12 RESERVED_15_13 13 15 ixDPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN 2 0xe0c1 12 0 4294967295 PSTATE 0 1 LPD 2 2 WIDTH 3 4 RATE 5 7 MPLLB_SEL 8 8 MPLL_EN 9 9 OVRD_EN 10 10 MSTR_MPLLA_STATE 11 11 MSTR_MPLLB_STATE 12 12 MSTR_MPLL_OVRD_EN 13 13 TX_ASYNC_EN_OVR_VAL 14 14 TX_ASYNC_EN_OVR_EN 15 15 ixDPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1 2 0xe0c2 13 0 4294967295 DETRX_REQ_OVRD_VAL 0 0 DETRX_REQ_OVRD_EN 1 1 VBOOST_EN_OVRD_VAL 2 2 VBOOST_EN_OVRD_EN 3 3 IBOOST_LVL_OVRD_VAL 4 7 IBOOST_LVL_OVRD_EN 8 8 TX_BEACON_EN_OVR_VAL 9 9 TX_BEACON_EN_OVR_EN 10 10 LANE_TX2RX_SER_LB_EN_OVRD_VAL 11 11 LANE_TX2RX_SER_LB_EN_OVRD_EN 12 12 TX_ASYNC_DATA_OVRD_VAL 13 13 TX_ASYNC_DATA_OVRD_EN 14 14 RESERVED_15_15 15 15 ixDPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_MASTER_MPLL_LOOP 2 0xe0c3 3 0 4294967295 MPLLB_LOOP_EN 0 0 MPLLA_LOOP_EN 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1 2 0xe0c4 11 0 4294967295 RESERVED 0 1 RX_LOS_LFPS_EN_OVRD_VAL 2 2 RX_LOS_LFPS_EN_OVRD_EN 3 3 RX_LOS_THRSHLD_OVRD_VAL 4 6 RX_LOS_THRSHLD_OVRD_EN 7 7 ADAPT_REQ 8 8 ADAPT_REQ_OVRD_EN 9 9 ADAPT_CONT 10 10 OFFCAN_CONT 11 11 CONT_OVRD_EN 12 12 RESERVED_15_13 13 15 ixDPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_2 2 0xe0c5 4 0 4294967295 VCO_LD_VAL_OVRD 0 12 VCO_LD_VAL_OVRD_EN 13 13 VCO_LOWFREQ_VAL_OVRD 14 14 VCO_LOWFREQ_VAL_OVRD_EN 15 15 ixDPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_3 2 0xe0c6 3 0 4294967295 REF_LD_VAL_OVRD 0 6 REF_LD_VAL_OVRD_EN 7 7 RESERVED_15_8 8 15 ixDPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT_2 2 0xe0c7 3 0 4294967295 RX_VALID 0 0 RX_VALID_OVRD_EN 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_2 2 0xe0c8 7 0 4294967295 LANE_TX2RX_SER_LB_EN_OVRD_VAL 0 0 LANE_TX2RX_SER_LB_EN_OVRD_EN 1 1 TX_DATA_EN_OVRD_VAL_R 2 2 TX_DATA_EN_OVRD_EN_R 3 3 TX_ASYNC_DATA_OVRD_VAL_R 4 4 TX_ASYNC_DATA_OVRD_EN_R 5 5 RESERVED_15_6 6 15 ixDPCSSYS_CR1_SUP_DIG_IDCODE_LO 2 0x0 1 0 4294967295 DATA 0 0 ixDPCSSYS_CR1_SUP_DIG_IDCODE_HI 2 0x1 1 0 4294967295 DATA 0 0 ixDPCSSYS_CR1_SUP_DIG_REFCLK_OVRD_IN 2 0x2 12 0 4294967295 REF_CLK_EN 0 0 REF_CLK_EN_OVRD_EN 1 1 REF_USE_PAD 2 2 REF_USE_PAD_OVRD_EN 3 3 REF_CLK_RANGE 4 8 REF_CLK_RANGE_OVRD_EN 9 9 BG_EN 10 10 BG_EN_OVRD_EN 11 11 HDMIMODE_EN 12 12 HDMIMODE_ENABLE_OVRD_EN 13 13 SUP_PRE_HP_OVRD 14 14 SUP_PRE_HP_OVRD_EN 15 15 ixDPCSSYS_CR1_SUP_DIG_MPLLA_DIV_CLK_OVRD_IN 2 0x3 4 0 4294967295 MPLLA_DIV_CLK_EN 0 0 MPLLA_DIV_MULTIPLIER 1 8 MPLLA_DIV_OVRD_EN 9 9 RESERVED_15_10 10 15 ixDPCSSYS_CR1_SUP_DIG_MPLLA_HDMI_CLK_OVRD_IN 2 0x4 4 0 4294967295 MPLLA_HDMI_PIXEL_CLK_DIV 0 1 MPLLA_HDMI_DIV 2 4 MPLLA_HDMI_OVRD_EN 5 5 RESERVED_15_6 6 15 ixDPCSSYS_CR1_SUP_DIG_MPLLB_DIV_CLK_OVRD_IN 2 0x5 4 0 4294967295 MPLLB_DIV_CLK_EN 0 0 MPLLB_DIV_MULTIPLIER 1 8 MPLLB_DIV_OVRD_EN 9 9 RESERVED_15_10 10 15 ixDPCSSYS_CR1_SUP_DIG_MPLLB_HDMI_CLK_OVRD_IN 2 0x6 4 0 4294967295 MPLLB_HDMI_PIXEL_CLK_DIV 0 1 MPLLB_HDMI_DIV 2 4 MPLLB_HDMI_OVRD_EN 5 5 RESERVED_15_6 6 15 ixDPCSSYS_CR1_SUP_DIG_MPLLA_OVRD_IN_0 2 0x7 12 0 4294967295 MPLLA_EN 0 0 MPLLA_DIV5_CLK_EN 1 1 MPLLA_TX_CLK_DIV 2 4 OVRD_EN 5 5 MPLLA_V2I 6 7 MPLLA_STANDBY 8 8 MPLLA_FREQ_VCO 9 10 MPLLA_CAL_FORCE 11 11 MPLL_FRACN_EN 12 12 MPLLA_CLK_SYNC_OVRD 13 13 MPLLA_CLK_SYNC_OVRD_EN 14 14 RESERVED_15_15 15 15 ixDPCSSYS_CR1_SUP_DIG_MPLLA_OVRD_IN_1 2 0x8 2 0 4294967295 MPLLA_MULTIPLIER 0 11 RESERVED_15_12 12 15 ixDPCSSYS_CR1_SUP_DIG_MPLLA_OVRD_IN_2 2 0x9 7 0 4294967295 MPLLA_SSC_EN 0 0 MPLLA_SSC_OVRD_EN 1 1 MPLLA_SSC_UP_SPREAD 2 2 MPLLA_PMIX_EN 3 3 MPLLA_WORD_DIV2_EN 4 4 MPLLA_FRACN_CFG_UPDATE_EN 5 5 RESERVED_15_6 6 15 ixDPCSSYS_CR1_SUP_DIG_MPLLA_SSC_PEAK_1 2 0xa 1 0 4294967295 MPLLA_SSC_PEAK_15_0 0 15 ixDPCSSYS_CR1_SUP_DIG_MPLLA_SSC_PEAK_2 2 0xb 2 0 4294967295 MPLLA_SSC_PEAK_19_16 0 3 RESERVED_15_4 4 15 ixDPCSSYS_CR1_SUP_DIG_MPLLA_SSC_STEPSIZE_1 2 0xc 1 0 4294967295 MPLLA_SSC_STEPSIZE_15_0 0 15 ixDPCSSYS_CR1_SUP_DIG_MPLLA_SSC_STEPSIZE_2 2 0xd 2 0 4294967295 MPLLA_SSC_STEPSIZE_20_16 0 4 RESERVED_15_5 5 15 ixDPCSSYS_CR1_SUP_DIG_MPLLA_OVRD_IN_3 2 0xe 1 0 4294967295 MPLLA_FRACN_QUOT 0 15 ixDPCSSYS_CR1_SUP_DIG_MPLLA_OVRD_IN_4 2 0xf 1 0 4294967295 MPLLA_FRACN_REM 0 15 ixDPCSSYS_CR1_SUP_DIG_MPLLA_OVRD_IN_5 2 0x10 1 0 4294967295 MPLLA_FRACN_DEN 0 15 ixDPCSSYS_CR1_SUP_DIG_MPLLA_CP_OVRD_IN 2 0x11 3 0 4294967295 MPLLA_CP_PROP 0 6 MPLLA_CP_INT 7 13 RESERVED_15_14 14 15 ixDPCSSYS_CR1_SUP_DIG_MPLLA_CP_GS_OVRD_IN 2 0x12 4 0 4294967295 MPLLA_CP_PROP_GS 0 6 MPLLA_CP_PROP_GS_OVR_EN 7 7 MPLLA_CP_INT_GS 8 14 MPLLA_CP_INT_GS_OVR_EN 15 15 ixDPCSSYS_CR1_SUP_DIG_MPLLB_OVRD_IN_0 2 0x13 12 0 4294967295 MPLLB_EN 0 0 MPLLB_DIV5_CLK_EN 1 1 MPLLB_TX_CLK_DIV 2 4 OVRD_EN 5 5 MPLLB_V2I 6 7 MPLLB_STANDBY 8 8 MPLLB_FREQ_VCO 9 10 MPLLB_CAL_FORCE 11 11 MPLL_FRACN_EN 12 12 MPLLB_CLK_SYNC_OVRD 13 13 MPLLB_CLK_SYNC_OVRD_EN 14 14 RESERVED_15_15 15 15 ixDPCSSYS_CR1_SUP_DIG_MPLLB_OVRD_IN_1 2 0x14 2 0 4294967295 MPLLB_MULTIPLIER 0 11 RESERVED_15_12 12 15 ixDPCSSYS_CR1_SUP_DIG_MPLLB_OVRD_IN_2 2 0x15 7 0 4294967295 MPLLB_SSC_EN 0 0 MPLLB_SSC_OVRD_EN 1 1 MPLLB_SSC_UP_SPREAD 2 2 MPLLB_PMIX_EN 3 3 MPLLB_WORD_DIV2_EN 4 4 MPLLB_FRACN_CFG_UPDATE_EN 5 5 RESERVED_15_6 6 15 ixDPCSSYS_CR1_SUP_DIG_MPLLB_SSC_PEAK_1 2 0x16 1 0 4294967295 MPLLB_SSC_PEAK_15_0 0 15 ixDPCSSYS_CR1_SUP_DIG_MPLLB_SSC_PEAK_2 2 0x17 2 0 4294967295 MPLLB_SSC_PEAK_19_16 0 3 RESERVED_15_4 4 15 ixDPCSSYS_CR1_SUP_DIG_MPLLB_SSC_STEPSIZE_1 2 0x18 1 0 4294967295 MPLLB_SSC_STEPSIZE_15_0 0 15 ixDPCSSYS_CR1_SUP_DIG_MPLLB_SSC_STEPSIZE_2 2 0x19 2 0 4294967295 MPLLB_SSC_STEPSIZE_20_16 0 4 RESERVED_15_5 5 15 ixDPCSSYS_CR1_SUP_DIG_MPLLB_OVRD_IN_3 2 0x1a 1 0 4294967295 MPLLB_FRACN_QUOT 0 15 ixDPCSSYS_CR1_SUP_DIG_MPLLB_OVRD_IN_4 2 0x1b 1 0 4294967295 MPLLB_FRACN_REM 0 15 ixDPCSSYS_CR1_SUP_DIG_MPLLB_OVRD_IN_5 2 0x1c 1 0 4294967295 MPLLB_FRACN_DEN 0 15 ixDPCSSYS_CR1_SUP_DIG_MPLLB_CP_OVRD_IN 2 0x1d 3 0 4294967295 MPLLB_CP_PROP 0 6 MPLLB_CP_INT 7 13 RESERVED_15_14 14 15 ixDPCSSYS_CR1_SUP_DIG_MPLLB_CP_GS_OVRD_IN 2 0x1e 4 0 4294967295 MPLLB_CP_PROP_GS 0 6 MPLLB_CP_PROP_GS_OVR_EN 7 7 MPLLB_CP_INT_GS 8 14 MPLLB_CP_INT_GS_OVR_EN 15 15 ixDPCSSYS_CR1_SUP_DIG_SUP_OVRD_IN 2 0x1f 8 0 4294967295 PRESCALER_OVRD_EN 0 0 RTUNE_REQ 1 1 RTUNE_OVRD_EN 2 2 TX_CAL_CODE 3 6 TX_CAL_CODE_EN 7 7 REF_ALT_CLK_LP_SEL_OVRD 8 8 REF_ALT_CLK_LP_SEL_OVRD_EN 9 9 RESERVED_15_10 10 15 ixDPCSSYS_CR1_SUP_DIG_PRESCALER_OVRD_IN 2 0x20 6 0 4294967295 DCO_RANGE 0 1 DCO_FINETUNE 2 7 REF_CLK_MPLLB_DIV 8 10 REF_CLK_MPLLA_DIV 11 13 REF_CLKDET_RESULT 14 14 REF_CLKDET_EN 15 15 ixDPCSSYS_CR1_SUP_DIG_SUP_OVRD_OUT 2 0x21 12 0 4294967295 RTUNE_ACK 0 0 RTUNE_ACK_OVRD_EN 1 1 MPLLA_STATE 2 2 MPLLA_STATE_OVRD_EN 3 3 MPLLB_STATE 4 4 MPLLB_STATE_OVRD_EN 5 5 BG_LANE_STATE 6 6 BG_LANE_STATE_OVRD_EN 7 7 BG_SUP_STATE 8 8 BG_SUP_STATE_OVRD_EN 9 9 REF_CLK_ACK 10 10 RESERVED_15_11 11 15 ixDPCSSYS_CR1_SUP_DIG_LVL_OVRD_IN 2 0x22 7 0 4294967295 RX_VREF_CTRL 0 2 RX_VREF_CTRL_EN 3 3 TX_VBOOST_LVL 4 6 TX_VBOOST_LVL_EN 7 7 SUP_RX_VCO_VREF_SEL_OVR 8 10 SUP_RX_VCO_VREF_SEL_OVR_EN 11 11 RESERVED_15_12 12 15 ixDPCSSYS_CR1_SUP_DIG_MPLLA_ASIC_IN_0 2 0x24 9 0 4294967295 MPLLA_EN 0 0 MPLLA_DIV5_CLK_EN 1 1 MPLLA_TX_CLK_DIV 2 4 MPLLA_V2I 5 6 MPLLA_STANDBY 7 7 MPLLA_FREQ_VCO 8 9 MPLLA_CAL_FORCE 10 10 MPLLA_FRACN_EN 11 11 RESERVED_15_12 12 15 ixDPCSSYS_CR1_SUP_DIG_MPLLA_ASIC_IN_1 2 0x25 2 0 4294967295 MPLLA_MULTIPLIER 0 11 RESERVED_15_12 12 15 ixDPCSSYS_CR1_SUP_DIG_MPLLA_ASIC_IN_2 2 0x26 7 0 4294967295 MPLLA_SSC_EN 0 0 MPLLA_SSC_UP_SPREAD 1 1 MPLLA_PMIX_EN 2 2 MPLLA_WORD_DIV2_EN 3 3 MPLLA_FRACN_CFG_UPDATE_EN 4 4 MPLLA_CLK_SYNC 5 5 RESERVED_15_6 6 15 ixDPCSSYS_CR1_SUP_DIG_MPLLA_ASIC_IN_3 2 0x27 1 0 4294967295 MPLLA_SSC_PEAK_15_0 0 15 ixDPCSSYS_CR1_SUP_DIG_MPLLA_ASIC_IN_4 2 0x28 2 0 4294967295 MPLLA_SSC_PEAK_19_16 0 3 RESERVED_15_4 4 15 ixDPCSSYS_CR1_SUP_DIG_MPLLA_ASIC_IN_5 2 0x29 1 0 4294967295 MPLLA_SSC_STEPSIZE_15_0 0 15 ixDPCSSYS_CR1_SUP_DIG_MPLLA_ASIC_IN_6 2 0x2a 2 0 4294967295 MPLLA_SSC_STEPSIZE_20_16 0 3 RESERVED_15_4 4 15 ixDPCSSYS_CR1_SUP_DIG_MPLLB_ASIC_IN_0 2 0x2b 9 0 4294967295 MPLLB_EN 0 0 MPLLB_DIV5_CLK_EN 1 1 MPLLB_TX_CLK_DIV 2 4 MPLLB_V2I 5 6 MPLLB_STANDBY 7 7 MPLLB_FREQ_VCO 8 9 MPLLB_CAL_FORCE 10 10 MPLLB_FRACN_EN 11 11 RESERVED_15_12 12 15 ixDPCSSYS_CR1_SUP_DIG_MPLLB_ASIC_IN_1 2 0x2c 2 0 4294967295 MPLLB_MULTIPLIER 0 11 RESERVED_15_12 12 15 ixDPCSSYS_CR1_SUP_DIG_MPLLB_ASIC_IN_2 2 0x2d 7 0 4294967295 MPLLB_SSC_EN 0 0 MPLLB_SSC_UP_SPREAD 1 1 MPLLB_PMIX_EN 2 2 MPLLB_WORD_DIV2_EN 3 3 MPLLB_FRACN_CFG_UPDATE_EN 4 4 MPLLB_CLK_SYNC 5 5 RESERVED_15_6 6 15 ixDPCSSYS_CR1_SUP_DIG_MPLLB_ASIC_IN_3 2 0x2e 1 0 4294967295 MPLLB_SSC_PEAK_15_0 0 15 ixDPCSSYS_CR1_SUP_DIG_MPLLB_ASIC_IN_4 2 0x2f 2 0 4294967295 MPLLB_SSC_PEAK_19_16 0 3 RESERVED_15_4 4 15 ixDPCSSYS_CR1_SUP_DIG_MPLLB_ASIC_IN_5 2 0x30 1 0 4294967295 MPLLB_SSC_STEPSIZE_15_0 0 15 ixDPCSSYS_CR1_SUP_DIG_MPLLB_ASIC_IN_6 2 0x31 2 0 4294967295 MPLLB_SSC_STEPSIZE_20_16 0 3 RESERVED_15_4 4 15 ixDPCSSYS_CR1_SUP_DIG_MPLLA_DIV_CLK_ASIC_IN 2 0x32 3 0 4294967295 MPLLA_DIV_CLK_EN 0 0 MPLLA_DIV_MULTIPLIER 1 8 RESERVED_15_9 9 15 ixDPCSSYS_CR1_SUP_DIG_MPLLA_HDMI_CLK_ASIC_IN 2 0x33 3 0 4294967295 MPLLA_HDMI_PIXEL_CLK_DIV 0 1 MPLLA_HDMI_DIV 2 4 RESERVED_15_5 5 15 ixDPCSSYS_CR1_SUP_DIG_MPLLB_DIV_CLK_ASIC_IN 2 0x34 3 0 4294967295 MPLLB_DIV_CLK_EN 0 0 MPLLB_DIV_MULTIPLIER 1 8 RESERVED_15_9 9 15 ixDPCSSYS_CR1_SUP_DIG_MPLLB_HDMI_CLK_ASIC_IN 2 0x35 3 0 4294967295 MPLLB_HDMI_PIXEL_CLK_DIV 0 1 MPLLB_HDMI_DIV 2 4 RESERVED_15_5 5 15 ixDPCSSYS_CR1_SUP_DIG_ASIC_IN 2 0x36 12 0 4294967295 PHY_RESET 0 0 REF_CLK_EN 1 1 REF_USE_PAD 2 2 TEST_BURNIN 3 3 TEST_POWERDOWN 4 4 RTUNE_REQ 5 5 RTUNE_ACK 6 6 MPLLA_STATE 7 7 MPLLB_STATE 8 8 TEST_TX_REF_CLK_EN 9 9 REF_ALT_CLK_LP_SEL 10 10 RESERVED_15_11 11 15 ixDPCSSYS_CR1_SUP_DIG_LVL_ASIC_IN 2 0x37 4 0 4294967295 RX_VREF_CTRL 0 2 TX_VBOOST_LVL 3 5 SUP_RX_VCO_VREF_SEL 6 8 RESERVED_15_9 9 15 ixDPCSSYS_CR1_SUP_DIG_BANDGAP_ASIC_IN 2 0x38 2 0 4294967295 BG_EN 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR1_SUP_DIG_MPLLA_CP_ASIC_IN 2 0x39 3 0 4294967295 MPLLA_CP_PROP 0 6 MPLLA_CP_INT 7 13 RESERVED_15_14 14 15 ixDPCSSYS_CR1_SUP_DIG_MPLLA_CP_GS_ASIC_IN 2 0x3a 3 0 4294967295 MPLLA_CP_PROP_GS 0 6 MPLLA_CP_INT_GS 7 13 RESERVED_15_14 14 15 ixDPCSSYS_CR1_SUP_DIG_MPLLB_CP_ASIC_IN 2 0x3b 3 0 4294967295 MPLLB_CP_PROP 0 6 MPLLB_CP_INT 7 13 RESERVED_15_14 14 15 ixDPCSSYS_CR1_SUP_DIG_MPLLB_CP_GS_ASIC_IN 2 0x3c 3 0 4294967295 MPLLB_CP_PROP_GS 0 6 MPLLB_CP_INT_GS 7 13 RESERVED_15_14 14 15 ixDPCSSYS_CR1_SUP_ANA_PRESCALER_CTRL 2 0x40 7 0 4294967295 PSCALER_ATB_SELECT 0 0 PSCALER_MEAS_VREG 0 0 PSCALER_OVRD_FAST_START 0 0 PSCALER_FAST_START_REG 0 0 PSCALER_VREG_BOOST 0 0 PSCALER_HYST_REF 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR1_SUP_ANA_RTUNE_CTRL 2 0x41 9 0 4294967295 RT_ATB 0 0 RT_SEL_ATBF 0 0 RT_SEL_ATBP 0 0 RT_VP4O8_EN 0 0 RT_DAC_CHOP 0 0 RT_DAC_MODE 0 0 RT_EN_FRCON 0 0 PSCALER_VREG_FB_DIV_CTRL 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR1_SUP_ANA_BG1 2 0x42 6 0 4294967295 SUP_SEL_VBG_VREF 0 0 SUP_SEL_VPHUD_VREF 0 0 NC4 4 4 SUP_SEL_VPLL_REF 0 0 RT_VREF_SEL 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR1_SUP_ANA_BG2 2 0x43 9 0 4294967295 SUP_BYPASS_BG 0 0 SUP_CHOP_EN 0 0 SUP_TEMP_MEAS 0 0 VPHUD_SELREF 0 0 ATB_EXT_MEAS_EN 0 0 RT_TX_OFFSET_EN 0 0 SUP_SEL_TX_SWING_VREF 0 0 PSCALER_VREG_OVERRIDE_RING_CTRL 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR1_SUP_ANA_SWITCH_PWR_MEAS 2 0x44 3 0 4294967295 SUP_ATB_SW 0 0 SUP_TIE 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR1_SUP_ANA_BG3 2 0x45 4 0 4294967295 SUP_SEL_RX_VCO_TC_VREF 0 0 SUP_SEL_RX_CAL_VREF 0 0 NC7_4 4 7 RESERVED_15_8 8 15 ixDPCSSYS_CR1_SUP_ANA_MPLLA_MISC1 2 0x46 7 0 4294967295 OVRD_GEAR_RC_FILT 0 0 OVRD_TEST_RC_FILT 0 0 TEST_VREG_DIV 0 0 VBG_EN 0 0 COUNT_SEL_LOCK 0 0 PHASE_SEL_LOCK 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR1_SUP_ANA_MPLLA_MISC2 2 0x47 8 0 4294967295 OVRD_PR_BYPASS 0 0 PR_BYPASS 0 0 OVRD_GEARSHIFT 0 0 GEARSHIFT_REG 0 0 TEST_LOCK_GEAR 0 0 EN_CAL_SPO 0 0 TEST_BOOST 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR1_SUP_ANA_MPLLA_OVRD 2 0x48 9 0 4294967295 OVRD_ENABLE 0 0 ENABLE_REG 0 0 OVRD_CAL 0 0 CAL_REG 0 0 OVRD_FB_CLK_EN 0 0 FB_CLK_EN_REG 0 0 OVRD_RESET 0 0 RESET_REG 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR1_SUP_ANA_MPLLA_ATB1 2 0x49 3 0 4294967295 MEAS_IV_WRAP 0 0 ATB_SELECT 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR1_SUP_ANA_MPLLA_ATB2 2 0x4a 2 0 4294967295 MEAS_IV_PLL 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR1_SUP_ANA_MPLLA_ATB3 2 0x4b 3 0 4294967295 MEAS_IV_BIAS 0 0 CTR_UPLL_TUNNING 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR1_SUP_ANA_MPLLA_CTR1 2 0x4c 5 0 4294967295 CTR_ICP_INT 0 0 CTR_VREF_EN 0 0 CTR_VREF_VMARG 0 0 CTR_CP_PLL 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR1_SUP_ANA_MPLLA_CTR2 2 0x4d 2 0 4294967295 CTR_REGS_PLL 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR1_SUP_ANA_MPLLA_CTR3 2 0x4e 4 0 4294967295 CTR_REGS_CP_PLL 0 0 CTR_SPO_PLL 0 0 CTR_VINT_CAP 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR1_SUP_ANA_MPLLA_CTR4 2 0x4f 7 0 4294967295 CTR_CP_8X 0 0 CTR_FIL_REG 0 0 CTR_CP_PROP_REF 0 0 CTR_DOUBLER_GAIN 0 0 CTR_TEST_CASC 0 0 CTR_RC_FITER 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR1_SUP_ANA_MPLLA_CTR5 2 0x50 8 0 4294967295 CTR_STANDBY_MODE 0 0 CTR_LEG_SR_CON 0 0 CTR_VREG_RING_OVERRIDE 0 0 CTR_SPO_SPEED_OVERRIDE 0 0 CTR_BYPASS_LOCK_SPO_CAL 0 0 CTR_LOCK_SPO_CAL 0 0 CTR_UPLL_RESERVED 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR1_SUP_ANA_MPLLA_RESERVED1 2 0x51 8 0 4294967295 CTR_REF_FBK_BYPASS 0 0 CTR_BYPASS_TX 0 0 CTR_VREG_CLK_BYPASS 0 0 CTR_VREG_CLK_PMIX_BYPASS 0 0 CTR_VREG_RIGHT_BYPASS 0 0 CTR_VREG_LEFT_BYPASS 0 0 CTR_LEFT_RIGHT_GAIN 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR1_SUP_ANA_MPLLA_RESERVED2 2 0x52 5 0 4294967295 CTR_DLL_MODE_90 0 0 CTR_DLL_RESERVED 0 0 CTR_DIV24_DSQ_ENZ 0 0 CTR_DIV4 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR1_SUP_ANA_MPLLB_MISC1 2 0x53 7 0 4294967295 OVRD_GEAR_RC_FILT 0 0 OVRD_TEST_RC_FILT 0 0 TEST_VREG_DIV 0 0 VBG_EN 0 0 COUNT_SEL_LOCK 0 0 PHASE_SEL_LOCK 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR1_SUP_ANA_MPLLB_MISC2 2 0x54 8 0 4294967295 OVRD_PR_BYPASS 0 0 PR_BYPASS 0 0 OVRD_GEARSHIFT 0 0 GEARSHIFT_REG 0 0 TEST_LOCK_GEAR 0 0 EN_CAL_SPO 0 0 TEST_BOOST 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR1_SUP_ANA_MPLLB_OVRD 2 0x55 9 0 4294967295 OVRD_ENABLE 0 0 ENABLE_REG 0 0 OVRD_CAL 0 0 CAL_REG 0 0 OVRD_FB_CLK_EN 0 0 FB_CLK_EN_REG 0 0 OVRD_RESET 0 0 RESET_REG 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR1_SUP_ANA_MPLLB_ATB1 2 0x56 3 0 4294967295 MEAS_IV_WRAP 0 0 ATB_SELECT 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR1_SUP_ANA_MPLLB_ATB2 2 0x57 2 0 4294967295 MEAS_IV_PLL 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR1_SUP_ANA_MPLLB_ATB3 2 0x58 3 0 4294967295 MEAS_IV_BIAS 0 0 CTR_UPLL_TUNNING 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR1_SUP_ANA_MPLLB_CTR1 2 0x59 5 0 4294967295 CTR_ICP_INT 0 0 CTR_VREF_EN 0 0 CTR_VREF_VMARG 0 0 CTR_CP_PLL 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR1_SUP_ANA_MPLLB_CTR2 2 0x5a 2 0 4294967295 CTR_REGS_PLL 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR1_SUP_ANA_MPLLB_CTR3 2 0x5b 4 0 4294967295 CTR_REGS_CP_PLL 0 0 CTR_SPO_PLL 0 0 CTR_VINT_CAP 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR1_SUP_ANA_MPLLB_CTR4 2 0x5c 7 0 4294967295 CTR_CP_8X 0 0 CTR_FIL_REG 0 0 CTR_CP_PROP_REF 0 0 CTR_DOUBLER_GAIN 0 0 CTR_TEST_CASC 0 0 CTR_RC_FITER 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR1_SUP_ANA_MPLLB_CTR5 2 0x5d 8 0 4294967295 CTR_STANDBY_MODE 0 0 CTR_LEG_SR_CON 0 0 CTR_VREG_RING_OVERRIDE 0 0 CTR_SPO_SPEED_OVERRIDE 0 0 CTR_BYPASS_LOCK_SPO_CAL 0 0 CTR_LOCK_SPO_CAL 0 0 CTR_UPLL_RESERVED 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR1_SUP_ANA_MPLLB_RESERVED1 2 0x5e 8 0 4294967295 CTR_REF_FBK_BYPASS 0 0 CTR_BYPASS_TX 0 0 CTR_VREG_CLK_BYPASS 0 0 CTR_VREG_CLK_PMIX_BYPASS 0 0 CTR_VREG_RIGHT_BYPASS 0 0 CTR_VREG_LEFT_BYPASS 0 0 CTR_LEFT_RIGHT_GAIN 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR1_SUP_ANA_MPLLB_RESERVED2 2 0x5f 5 0 4294967295 CTR_DLL_MODE_90 0 0 CTR_DLL_RESERVED 0 0 CTR_DIV24_DSQ_ENZ 0 0 CTR_DIV4 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD 2 0x61 8 0 4294967295 OVRD_SEL 0 0 MPLL_FBDIGCLK_EN 1 1 MPLL_PCLK_EN 2 2 FAST_MPLL_PWRUP 3 3 FAST_MPLL_LOCK 4 4 DTB_SEL 5 9 DIV10_EN 10 10 RESERVED 11 15 ixDPCSSYS_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT 2 0x62 11 0 4294967295 FSM_STATE 0 3 MPLL_R_LANES 4 4 MPLL_L_LANES 5 5 MPLL_PCLK_EN 6 6 MPLL_OUTPUT_EN 7 7 MPLL_FBCLK_EN 8 8 MPLL_CAL 9 9 MPLL_RST 10 10 MPLL_ANA_EN 11 11 MPLL_LOCK 12 12 RESERVED_15_13 13 15 ixDPCSSYS_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE 2 0x63 3 0 4294967295 MAX_RANGE 0 4 DAC_IN 5 9 RESERVED_15_10 10 15 ixDPCSSYS_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_LOCK 2 0x64 3 0 4294967295 LOCK_TIME 0 7 STABLE_TIME 8 13 RESERVED_15_14 14 15 ixDPCSSYS_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS 2 0x65 2 0 4294967295 GEARSHIFT_TIME 0 7 PRESET_TIME 8 15 ixDPCSSYS_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE 2 0x66 3 0 4294967295 PWRDN_WAIT_TIME 0 5 PCLK_EN_TIME 6 11 RESERVED_15_12 12 15 ixDPCSSYS_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2 2 0x67 3 0 4294967295 PCLK_DIS_TIME 0 5 PWRDN_TIME 6 11 RESERVED_15_12 12 15 ixDPCSSYS_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_CAL 2 0x68 3 0 4294967295 MPLL_CAL 0 0 MPLL_CAL_OVRD_EN 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT 2 0x69 2 0 4294967295 MPLL_ANA_DAC_OUT 0 4 RESERVED_15_5 5 15 ixDPCSSYS_CR1_SUP_DIG_MPLLA_SSC_GEN_SPREAD_TYPE 2 0x6b 3 0 4294967295 SPREAD_TYPE 0 1 OVR_EN 2 2 RESERVED_15_3 3 15 ixDPCSSYS_CR1_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD 2 0x6d 8 0 4294967295 OVRD_SEL 0 0 MPLL_FBDIGCLK_EN 1 1 MPLL_PCLK_EN 2 2 FAST_MPLL_PWRUP 3 3 FAST_MPLL_LOCK 4 4 DTB_SEL 5 9 DIV10_EN 10 10 RESERVED 11 15 ixDPCSSYS_CR1_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT 2 0x6e 11 0 4294967295 FSM_STATE 0 3 MPLL_R_LANES 4 4 MPLL_L_LANES 5 5 MPLL_PCLK_EN 6 6 MPLL_OUTPUT_EN 7 7 MPLL_FBCLK_EN 8 8 MPLL_CAL 9 9 MPLL_RST 10 10 MPLL_ANA_EN 11 11 MPLL_LOCK 12 12 RESERVED_15_13 13 15 ixDPCSSYS_CR1_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE 2 0x6f 3 0 4294967295 MAX_RANGE 0 4 DAC_IN 5 9 RESERVED_15_10 10 15 ixDPCSSYS_CR1_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_LOCK 2 0x70 3 0 4294967295 LOCK_TIME 0 7 STABLE_TIME 8 13 RESERVED_15_14 14 15 ixDPCSSYS_CR1_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS 2 0x71 2 0 4294967295 GEARSHIFT_TIME 0 7 PRESET_TIME 8 15 ixDPCSSYS_CR1_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE 2 0x72 3 0 4294967295 PWRDN_WAIT_TIME 0 5 PCLK_EN_TIME 6 11 RESERVED_15_12 12 15 ixDPCSSYS_CR1_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2 2 0x73 3 0 4294967295 PCLK_DIS_TIME 0 5 PWRDN_TIME 6 11 RESERVED_15_12 12 15 ixDPCSSYS_CR1_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_CAL 2 0x74 3 0 4294967295 MPLL_CAL 0 0 MPLL_CAL_OVRD_EN 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR1_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT 2 0x75 2 0 4294967295 MPLL_ANA_DAC_OUT 0 4 RESERVED_15_5 5 15 ixDPCSSYS_CR1_SUP_DIG_MPLLB_SSC_GEN_SPREAD_TYPE 2 0x77 3 0 4294967295 SPREAD_TYPE 0 1 OVR_EN 2 2 RESERVED_15_3 3 15 ixDPCSSYS_CR1_SUP_DIG_CLK_RST_BG_PWRUP_TIME_0 2 0x78 3 0 4294967295 BG_SUP_EN_TIME 0 8 FAST_BG_WAIT 9 9 RESERVED_15_10 10 15 ixDPCSSYS_CR1_SUP_DIG_CLK_RST_BG_PWRUP_TIME_1 2 0x79 2 0 4294967295 BG_LANE_EN_TIME 0 8 RESERVED_15_9 9 15 ixDPCSSYS_CR1_SUP_DIG_CLK_RST_BG_PWRUP_TIME_2 2 0x7a 3 0 4294967295 BG_KICK_START_EN_TIME 0 7 BG_SUP_STATE_UPD_EN 8 8 RESERVED_15_9 9 15 ixDPCSSYS_CR1_SUP_DIG_CLK_RST_REF_PWRUP_TIME_0 2 0x7b 3 0 4294967295 REF_VREG_FAST_START_TIME 0 4 FAST_REF_WAIT 5 5 RESERVED_15_6 6 15 ixDPCSSYS_CR1_SUP_DIG_CLK_RST_REF_VPHUD 2 0x7c 3 0 4294967295 SUP_ANA_VPHUD_SELVPH_I 0 0 SUP_ANA_VPHUD_EN_I 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR1_SUP_DIG_RTUNE_CONFIG 2 0x81 5 0 4294967295 RX_CAL_EN 0 0 FAST_RTUNE 1 1 TX_CAL_EN 2 2 SUP_ANA_TERM_CTRL 3 5 RESERVED_15_6 6 15 ixDPCSSYS_CR1_SUP_DIG_RTUNE_STAT 2 0x82 3 0 4294967295 STAT 0 9 DTB_RTUNE 10 11 RESERVED_15_12 12 15 ixDPCSSYS_CR1_SUP_DIG_RTUNE_RX_SET_VAL 2 0x83 2 0 4294967295 RX_SET_VAL 0 5 RESERVED_15_6 6 15 ixDPCSSYS_CR1_SUP_DIG_RTUNE_TXDN_SET_VAL 2 0x84 2 0 4294967295 TXDN_SET_VAL 0 9 RESERVED_15_10 10 15 ixDPCSSYS_CR1_SUP_DIG_RTUNE_TXUP_SET_VAL 2 0x85 2 0 4294967295 TXUP_SET_VAL 0 9 RESERVED_15_10 10 15 ixDPCSSYS_CR1_SUP_DIG_RTUNE_RX_STAT 2 0x86 2 0 4294967295 RX_STAT 0 5 RESERVED_15_6 6 15 ixDPCSSYS_CR1_SUP_DIG_RTUNE_TXDN_STAT 2 0x87 2 0 4294967295 TXDN_STAT 0 9 RESERVED_15_10 10 15 ixDPCSSYS_CR1_SUP_DIG_RTUNE_TXUP_STAT 2 0x88 2 0 4294967295 TXUP_STAT 0 9 RESERVED_15_10 10 15 ixDPCSSYS_CR1_SUP_DIG_RTUNE_CONFIG_CNT0 2 0x89 4 0 4294967295 RT_RESULT_TIME 0 3 RT_EVAL_TIME 4 7 RT_RST_TIME 8 11 RT_ACK_TIME 12 15 ixDPCSSYS_CR1_SUP_DIG_RTUNE_CONFIG_CNT1 2 0x8a 3 0 4294967295 RT_TXDN_SETTLE_TIME 0 3 RT_PWRUP_TIME 4 8 RESERVED_15_9 9 15 ixDPCSSYS_CR1_SUP_DIG_RTUNE_TX_CAL_CODE 2 0x8b 2 0 4294967295 VALUE 0 3 RESERVED_15_4 4 15 ixDPCSSYS_CR1_SUP_DIG_ANA_MPLLA_OVRD_OUT_0 2 0x8c 16 0 4294967295 MPLLA_WORD_CLK_EN 0 0 MPLLA_HDMI_CLK_EN 1 1 MPLLA_DIV_CLK_EN 2 2 MPLLA_OUTPUT_EN 3 3 MPLLA_CLK_EN_OVRD_EN 4 4 MPLLA_OUTPUT_L_EN 5 5 MPLLA_OUTPUT_R_EN 6 6 MPLLA_ANA_EN 7 7 MPLLA_RST 8 8 MPLLA_CAL 9 9 MPLLA_DIV5_CLK_EN 10 10 MPLLA_DIV10_CLK_EN 11 11 MPLLA_FBCLK_EN 12 12 MPLLA_GEARSHIFT_EN 13 13 MPLLA_STANDBY 14 14 OVRD_SEL 15 15 ixDPCSSYS_CR1_SUP_DIG_ANA_MPLLA_OVRD_OUT_1 2 0x8d 2 0 4294967295 MPLLA_ANA_INT 0 9 RESERVED_15_10 10 15 ixDPCSSYS_CR1_SUP_DIG_ANA_MPLLA_OVRD_OUT_2 2 0x8e 3 0 4294967295 MPLLA_CP_PROP 0 6 MPLLA_CP_INT 7 13 RESERVED_15_14 14 15 ixDPCSSYS_CR1_SUP_DIG_ANA_MPLLB_OVRD_OUT_0 2 0x8f 16 0 4294967295 MPLLB_WORD_CLK_EN 0 0 MPLLB_HDMI_CLK_EN 1 1 MPLLB_DIV_CLK_EN 2 2 MPLLB_OUTPUT_EN 3 3 MPLLB_CLK_EN_OVRD_EN 4 4 MPLLB_OUTPUT_L_EN 5 5 MPLLB_OUTPUT_R_EN 6 6 MPLLB_ANA_EN 7 7 MPLLB_RST 8 8 MPLLB_CAL 9 9 MPLLB_DIV5_CLK_EN 10 10 MPLLB_DIV10_CLK_EN 11 11 MPLLB_FBCLK_EN 12 12 MPLLB_GEARSHIFT_EN 13 13 MPLLB_STANDBY 14 14 OVRD_SEL 15 15 ixDPCSSYS_CR1_SUP_DIG_ANA_MPLLB_OVRD_OUT_1 2 0x90 2 0 4294967295 MPLLB_ANA_INT 0 9 RESERVED_15_10 10 15 ixDPCSSYS_CR1_SUP_DIG_ANA_MPLLB_OVRD_OUT_2 2 0x91 3 0 4294967295 MPLLB_CP_PROP 0 6 MPLLB_CP_INT 7 13 RESERVED_15_14 14 15 ixDPCSSYS_CR1_SUP_DIG_ANA_RTUNE_OVRD_OUT 2 0x92 6 0 4294967295 RTUNE_COMP_RST 0 0 RTUNE_MODE 1 2 RTUNE_EN 3 3 RTUNE_VALUE 4 13 RTUNE_OVRD_EN 14 14 RESERVED_15_15 15 15 ixDPCSSYS_CR1_SUP_DIG_ANA_STAT 2 0x93 3 0 4294967295 RT_ANA_COMP_RESULT 0 0 REF_ANA_CLKDET_RESULT 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR1_SUP_DIG_ANA_BG_OVRD_OUT 2 0x94 11 0 4294967295 BG_EN 0 0 BG_FAST_START 1 1 BG_KICK_START 2 2 BG_OVRD_EN 3 3 ANA_ASYNC_RST 4 4 ANA_ASYNC_RST_OVRD_EN 5 5 REF_VREG_FAST_START 6 6 REF_VREG_FAST_START_OVRD_EN 7 7 REF_VREG_REF_SEL 8 9 REF_VREG_REF_SEL_OVRD_EN 10 10 RESERVED_15_11 11 15 ixDPCSSYS_CR1_SUP_DIG_ANA_MPLLA_PMIX_OVRD_OUT 2 0x95 5 0 4294967295 MPLLA_PMIX_SEL 0 5 MPLLA_PMIX_EN 6 6 MPLLA_PMIX_SEL_OVRD_EN 7 7 MPLLA_PMIX_EN_OVRD_EN 8 8 RESERVED_15_9 9 15 ixDPCSSYS_CR1_SUP_DIG_ANA_MPLLB_PMIX_OVRD_OUT 2 0x96 5 0 4294967295 MPLLB_PMIX_SEL 0 5 MPLLB_PMIX_EN 6 6 MPLLB_PMIX_SEL_OVRD_EN 7 7 MPLLB_PMIX_EN_OVRD_EN 8 8 RESERVED_15_9 9 15 ixDPCSSYS_CR1_LANE0_DIG_ASIC_LANE_OVRD_IN 2 0x1000 5 0 4294967295 LANE_TX2RX_SER_LB 0 0 LANE_RX2TX_PAR_LB 1 1 EN 2 2 RX_ACJTAG_EN 3 3 RESERVED_15_4 4 15 ixDPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_0 2 0x1001 12 0 4294967295 REQ 0 0 REQ_OVRD_EN 1 1 PSTATE 2 3 PSTATE_OVRD_EN 4 4 RATE 5 7 RATE_OVRD_EN 8 8 WIDTH 9 10 WIDTH_OVRD_EN 11 11 MPLLB_SEL 12 12 MPLLB_SEL_OVRD_EN 13 13 DATA_EN 14 14 DATA_EN_OVRD_EN 15 15 ixDPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_1 2 0x1002 11 0 4294967295 NYQUIST_DATA 0 0 DISABLE 1 1 BEACON_EN 2 2 EN 3 3 TX_MAIN_CURSOR 4 9 MAIN_OVRD_EN 10 10 ASYNC_DRV_EN 11 11 ASYNC_DRV_OVRD_EN 12 12 TX_VREGDRV_BYP_OVRD 13 13 TX_VREGDRV_BYP_OVRD_EN 14 14 RESERVED_15_15 15 15 ixDPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_2 2 0x1003 6 0 4294967295 TX_PRE_CURSOR 0 5 PRE_OVRD_EN 6 6 TX_POST_CURSOR 7 12 POST_OVRD_EN 13 13 HDMIMODE_EN 14 14 HDMIMODE_ENABLE_OVRD_EN 15 15 ixDPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_3 2 0x1004 15 0 4294967295 CLK_RDY 0 0 CLK_RDY_OVRD_EN 1 1 DETECT_RX_REQ 2 2 DETECT_RX_REQ_OVRD_EN 3 3 INVERT 4 4 INVERT_OVRD_EN 5 5 LPD 6 6 LPD_OVRD_EN 7 7 TX_DC_COUP_EN 8 8 TX_DC_COUP_EN_OVRD_EN 9 9 PMA_EXTENDED_FIFO_EN 10 10 PMA_EXTENDED_FIFO_EN_OVRD_EN 11 11 TX_MPHY_MODE_EN 12 12 TX_MPHY_MODE_EN_OVRD_EN 13 13 RESERVED_15_14 14 15 ixDPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_4 2 0x1005 3 0 4294967295 RESET 0 0 RESET_OVRD_EN 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_OUT 2 0x1006 5 0 4294967295 TX_ACK 0 0 EN_TX_ACK 1 1 DETRX_RESULT 2 2 EN_DETRX_RESULT 3 3 RESERVED_15_4 4 15 ixDPCSSYS_CR1_LANE0_DIG_ASIC_RX_OVRD_OUT_0 2 0x100f 9 0 4294967295 ACK 0 0 ACK_OVRD_EN 1 1 ADAPT_STS 2 3 ADAPT_STS_OVRD_EN 4 4 RX_ASYNC_DATA 5 5 RX_ASYNC_DATA_OVRD_EN 6 6 RX_SQ_WEAKKEEP_OUT 7 7 RX_SQ_WEAKKEEP_OUT_OVRD_EN 8 8 RESERVED_15_9 9 15 ixDPCSSYS_CR1_LANE0_DIG_ASIC_LANE_ASIC_IN 2 0x1010 3 0 4294967295 LANE_TX2RX_SER_LB 0 0 LANE_RX2TX_PAR_LB 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR1_LANE0_DIG_ASIC_TX_ASIC_IN_0 2 0x1011 12 0 4294967295 CLK_RDY 0 0 RESET 1 1 INVERT 2 2 DATA_EN 3 3 REQ 4 4 LPD 5 5 PSTATE 6 7 RATE 8 10 WIDTH 11 12 MPLLB_SEL 13 13 DETECT_RX_REQ 14 14 DISABLE 15 15 ixDPCSSYS_CR1_LANE0_DIG_ASIC_TX_ASIC_IN_1 2 0x1012 7 0 4294967295 BEACON_EN 0 0 TX_MAIN_CURSOR 1 6 TX_ASYNC_EN 7 7 TX_ASYNC_DATA 8 8 TX_ASYNC_DRV_EN 9 9 TX_VREGDRV_BYP 10 10 RESERVED_15_11 11 15 ixDPCSSYS_CR1_LANE0_DIG_ASIC_TX_ASIC_IN_2 2 0x1013 3 0 4294967295 TX_PRE_CURSOR 0 5 TX_POST_CURSOR 6 11 RESERVED_15_12 12 15 ixDPCSSYS_CR1_LANE0_DIG_ASIC_TX_ASIC_OUT 2 0x1014 3 0 4294967295 TX_ACK 0 0 DETRX_RESULT 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR1_LANE0_DIG_ASIC_RX_ASIC_OUT_0 2 0x101b 4 0 4294967295 ACK 0 0 VALID 1 1 ADAPT_STS 2 3 RESERVED_15_4 4 15 ixDPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_5 2 0x101d 15 0 4294967295 RPTR_EN_MASTER_LANE 0 0 RPTR_EN_MASTER_LANE_OVRD_EN 1 1 DIG_CLK_EN_OTHER_LANE 2 2 DIG_CLK_EN_OTHER_LANE_OVRD_EN 3 3 DIG_CLK_STATE_MASTER_LANE 4 4 DIG_CLK_STATE_MASTER_LANE_OVRD_EN 5 5 SHIFT_MASTER_LANE 6 6 SHIFT_MASTER_LANE_ORVD_EN 7 7 SHIFT_ACK_OTHER_LANE 8 8 SHIFT_ACK_OTHER_LANE_OVRD_EN 9 9 LANE_MASTER 10 10 LANE_MASTER_OVRD_IN_EN 11 11 TX_DWORD_CLK_SYNC_OVRD 12 12 TX_DWORD_CLK_SYNC_OVRD_EN 13 13 RESERVED_15_14 14 15 ixDPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_OUT_1 2 0x101e 11 0 4294967295 RPTR_EN_OUT 0 0 RPTR_EN_OUT_OVRD_EN 1 1 DIG_CLK_EN_OUT 2 2 DIG_CLK_EN_OUT_OVRD_EN 3 3 DIG_CLK_STATE_OUT 4 4 DIG_CLK_STATE_OUT_OVRD_EN 5 5 SHIFT_OUT 6 6 SHIFT_OUT_OVRD_EN 7 7 SHIFT_ACK_OUT 8 8 SHIFT_ACK_OUT_OVRD_EN 9 9 RESERVED_15_10 10 15 ixDPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0 2 0x1020 11 0 4294967295 TX_P0_ANA_REFGEN_EN 0 0 TX_P0_ANA_VCM_HOLD 1 1 TX_P0_ANA_CLK_EN 2 2 TX_P0_ANA_WORD_CLK_EN 3 3 TX_P0_ANA_RESET 4 4 TX_P0_ANA_SERIAL_EN 5 5 TX_P0_DIG_CLK_EN 6 6 TX_P0_DATA_EN 7 7 TX_P0_ALLOW_RXDET 8 8 TX_P0_ANA_DCC_COMP_CAL_EN 9 9 RESERVED_15_10 10 15 ixDPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S 2 0x1021 11 0 4294967295 TX_P0S_ANA_REFGEN_EN 0 0 TX_P0S_ANA_VCM_HOLD 1 1 TX_P0S_ANA_CLK_EN 2 2 TX_P0S_ANA_WORD_CLK_EN 3 3 TX_P0S_ANA_RESET 4 4 TX_P0S_ANA_SERIAL_EN 5 5 TX_P0S_DIG_CLK_EN 6 6 TX_P0S_DATA_EN 7 7 TX_P0S_ALLOW_RXDET 8 8 TX_P0S_ANA_DCC_COMP_CAL_EN 9 9 RESERVED_15_10 10 15 ixDPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1 2 0x1022 11 0 4294967295 TX_P1_ANA_REFGEN_EN 0 0 TX_P1_ANA_VCM_HOLD 1 1 TX_P1_ANA_CLK_EN 2 2 TX_P1_ANA_WORD_CLK_EN 3 3 TX_P1_ANA_RESET 4 4 TX_P1_ANA_SERIAL_EN 5 5 TX_P1_DIG_CLK_EN 6 6 TX_P1_DATA_EN 7 7 TX_P1_ALLOW_RXDET 8 8 TX_P1_ANA_DCC_COMP_CAL_EN 9 9 RESERVED_15_10 10 15 ixDPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2 2 0x1023 12 0 4294967295 TX_P2_ANA_REFGEN_EN 0 0 TX_P2_ANA_VCM_HOLD 1 1 TX_P2_ANA_CLK_EN 2 2 TX_P2_ANA_WORD_CLK_EN 3 3 TX_P2_ANA_RESET 4 4 TX_P2_ANA_SERIAL_EN 5 5 TX_P2_DIG_CLK_EN 6 6 TX_P2_DATA_EN 7 7 TX_P2_ALLOW_RXDET 8 8 TX_P2_ALLOW_VBOOST 9 9 TX_P2_ANA_DCC_COMP_CAL_EN 10 10 RESERVED_15_11 11 15 ixDPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_0 2 0x1024 2 0 4294967295 TX_REFGEN_EN_TIME 0 7 TX_CLK_EN 8 15 ixDPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_1 2 0x1025 2 0 4294967295 TX_VCM_HOLD_TIME_14_0 0 14 SKIP_TX_VCM_HOLD_WAIT 15 15 ixDPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_2 2 0x1026 2 0 4294967295 TX_VBOOST_DIS_TIME_12_0 0 12 DTB_SEL 13 15 ixDPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_3 2 0x1027 3 0 4294967295 TX_VCM_HOLD_TIME_17_15 0 2 TX_VBOOST_DIS_TIME_13 3 3 RESERVED_15_4 4 15 ixDPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_4 2 0x1028 2 0 4294967295 TX_VCM_HOLD_GS_TIME 0 14 SKIP_TX_VCM_HOLD_GS_PULSE 15 15 ixDPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_5 2 0x1029 5 0 4294967295 TX_RXDET_TIME 0 9 FAST_TX_RXDET 10 10 TX_RESET_TIME 11 12 TX_SERIAL_EN_TIME 13 14 RESERVED_15_15 15 15 ixDPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_DCC_CR_BANK_ADDR 2 0x102a 1 0 4294967295 ADDR 0 15 ixDPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_DCC_CR_BANK_DATA 2 0x102b 1 0 4294967295 DATA 0 15 ixDPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_DCC_DAC_CTRL 2 0x102c 2 0 4294967295 CTRL 0 7 RESERVED_15_8 8 15 ixDPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_DCC_DAC_RANGE 2 0x102d 2 0 4294967295 CTRL 0 1 RESERVED_15_2 2 15 ixDPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_DCC_DAC_SEL 2 0x102e 6 0 4294967295 SEL 0 2 REQ 3 3 CTRL_UPD 4 4 RANGE_UPD 5 5 BIN_HOT 6 6 RESERVED_15_7 7 15 ixDPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_DCC_DAC_ACK 2 0x102f 2 0 4294967295 ACK 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_DCC_DAC_ADDR 2 0x1030 1 0 4294967295 ADDR 0 15 ixDPCSSYS_CR1_LANE0_DIG_TX_CLK_ALIGN_TX_CTL_0 2 0x1031 4 0 4294967295 TX_NUM_2UI_SHIFTS_16B_MODE 0 3 TX_NUM_2UI_SHIFTS_20B_MODE 4 7 TX_FIFO_BYPASS 8 8 RESERVED_15_9 9 15 ixDPCSSYS_CR1_LANE0_DIG_TX_LBERT_CTL 2 0x1032 4 0 4294967295 MODE 0 3 TRIGGER_ERR 4 4 PAT0 5 14 RESERVED_15_15 15 15 ixDPCSSYS_CR1_LANE0_DIG_RX_STAT_LD_VAL_1 2 0x1080 2 0 4294967295 SC1_LD_VAL 0 14 SC1_START 15 15 ixDPCSSYS_CR1_LANE0_DIG_RX_STAT_DATA_MSK 2 0x1081 1 0 4294967295 DATA_MSK_15_0 0 15 ixDPCSSYS_CR1_LANE0_DIG_RX_STAT_MATCH_CTL0 2 0x1082 4 0 4294967295 PTTRN_MSK_CR1A_4_0 0 4 PTTRN_CR1A_4_0 5 9 DATA_MSK_19_16 10 13 SCOPE_DLY 14 15 ixDPCSSYS_CR1_LANE0_DIG_RX_STAT_MATCH_CTL1 2 0x1083 5 0 4294967295 PTTRN_CR1B_EN 0 0 PTTRN_MSK_CR1B_4_0 1 5 PTTRN_CR1B_4_0 6 10 PTTRN_CR1A_ADPT_EN 11 11 RESERVED_15_12 12 15 ixDPCSSYS_CR1_LANE0_DIG_RX_STAT_STAT_CTL0 2 0x1084 10 0 4294967295 RESERVED_0 0 0 CORR_SHFT_SEL_VGA 1 1 CORR_SHFT_SEL 2 2 CORR_SRC_SEL 3 4 CORR_MODE_EN 5 5 STAT_SHFT_SEL 6 9 STAT_SRC_SEL 10 12 STAT_RXCLK_SEL 13 13 SC_TIMER_MODE 14 14 SKIP_EN 15 15 ixDPCSSYS_CR1_LANE0_DIG_RX_STAT_STAT_CTL1 2 0x1085 13 0 4294967295 STAT_CNT_0_EN 0 0 STAT_CNT_1_EN 1 1 STAT_CNT_2_EN 2 2 STAT_CNT_3_EN 3 3 STAT_CNT_4_EN 4 4 STAT_CNT_5_EN 5 5 STAT_CNT_6_EN 6 6 RESERVED_8_7 7 8 SC_PAUSE 9 9 STAT_CLK_EN 10 10 DATA_DLY_SEL 11 12 VLD_LOSS_CLR 13 13 VLD_CTL 14 15 ixDPCSSYS_CR1_LANE0_DIG_RX_STAT_SMPL_CNT1 2 0x1086 2 0 4294967295 SMPL_CNT1 0 14 SMPL_CNT1_DONE 15 15 ixDPCSSYS_CR1_LANE0_DIG_RX_STAT_STAT_CNT_0 2 0x1087 2 0 4294967295 STAT_CNT_0 0 14 SMPL_CNT1_DONE 15 15 ixDPCSSYS_CR1_LANE0_DIG_RX_STAT_STAT_CNT_1 2 0x1088 2 0 4294967295 STAT_CNT_1 0 14 SMPL_CNT1_DONE 15 15 ixDPCSSYS_CR1_LANE0_DIG_RX_STAT_STAT_CNT_2 2 0x1089 2 0 4294967295 STAT_CNT_2 0 14 SMPL_CNT1_DONE 15 15 ixDPCSSYS_CR1_LANE0_DIG_RX_STAT_STAT_CNT_3 2 0x108a 2 0 4294967295 STAT_CNT_3 0 14 SMPL_CNT1_DONE 15 15 ixDPCSSYS_CR1_LANE0_DIG_RX_STAT_STAT_CNT_4 2 0x108b 2 0 4294967295 STAT_CNT_4 0 14 SMPL_CNT1_DONE 15 15 ixDPCSSYS_CR1_LANE0_DIG_RX_STAT_STAT_CNT_5 2 0x108c 2 0 4294967295 STAT_CNT_5 0 14 SMPL_CNT1_DONE 15 15 ixDPCSSYS_CR1_LANE0_DIG_RX_STAT_STAT_CNT_6 2 0x108d 2 0 4294967295 STAT_CNT_6 0 14 SMPL_CNT1_DONE 15 15 ixDPCSSYS_CR1_LANE0_DIG_RX_STAT_CAL_COMP_CLK_CTL 2 0x108e 3 0 4294967295 PRECHRGE_CNT 0 2 REF_DIV_CNT 3 5 RESERVED_15_6 6 15 ixDPCSSYS_CR1_LANE0_DIG_RX_STAT_MATCH_CTL2 2 0x108f 2 0 4294967295 PTTRN_CR1A_19_5 0 14 RESERVED_15_15 15 15 ixDPCSSYS_CR1_LANE0_DIG_RX_STAT_MATCH_CTL3 2 0x1090 2 0 4294967295 PTTRN_MSK_CR1A_19_5 0 14 RESERVED_15_15 15 15 ixDPCSSYS_CR1_LANE0_DIG_RX_STAT_MATCH_CTL4 2 0x1091 2 0 4294967295 PTTRN_CR1B_19_5 0 14 RESERVED_15_15 15 15 ixDPCSSYS_CR1_LANE0_DIG_RX_STAT_MATCH_CTL5 2 0x1092 2 0 4294967295 PTTRN_MSK_CR1B_19_5 0 14 RESERVED_15_15 15 15 ixDPCSSYS_CR1_LANE0_DIG_RX_STAT_STAT_CTL2 2 0x1093 4 0 4294967295 DATA_DLY_SEL_2 0 0 SCOPE_DLY_2 1 1 DISABLE_SAMPLE_COUNT 2 2 RESERVED_15_3 3 15 ixDPCSSYS_CR1_LANE0_DIG_RX_STAT_STAT_STOP 2 0x1094 2 0 4294967295 SC1_STOP 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR1_LANE0_DIG_ANA_TX_OVRD_OUT 2 0x10a0 15 0 4294967295 TX_ANA_CLK_SHIFT 0 0 TX_ANA_DATA_EN 1 1 TX_ANA_REFGEN_EN 2 2 TX_ANA_VCM_HOLD 3 3 TX_ANA_CLK_EN 4 4 TX_ANA_WORD_CLK_EN 5 5 TX_ANA_MPLLA_CLK_EN 6 6 TX_ANA_MPLLB_CLK_EN 7 7 TX_ANA_RESET 8 8 TX_ANA_SERIAL_EN 9 9 TX_ANA_DATA_RATE 10 11 RESERVED 12 12 TX_DIV4_EN 13 13 TX_RXDET_EN 14 14 TX_OVRD_EN 15 15 ixDPCSSYS_CR1_LANE0_DIG_ANA_TX_TERM_CODE_OVRD_OUT 2 0x10a1 5 0 4294967295 TX_TERM_CODE 0 9 TX_TERM_OVRD_EN 10 10 TX_DRV_SRC 11 12 TX_DRV_SRC_OVRD_EN 13 13 RESERVED_15_14 14 15 ixDPCSSYS_CR1_LANE0_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT 2 0x10a2 3 0 4294967295 TX_TERM_DN_CLK 0 0 TX_TERM_CLK_SELF_CLEAR_DISABLE 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR1_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_0 2 0x10a3 3 0 4294967295 TX_ANA_LOAD_CLK 0 0 TX_ANA_CTRL_LEG_PULL_EN_13_0 1 14 TX_EQ_OVRD_EN 15 15 ixDPCSSYS_CR1_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_1 2 0x10a4 2 0 4294967295 TX_ANA_CTRL_LEG_PULL_EN_19_14 0 5 RESERVED_15_6 6 15 ixDPCSSYS_CR1_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_2 2 0x10a5 4 0 4294967295 RESERVED 0 2 TX_ANA_CTRL_EQ_MUX_SEL 3 6 TX_ANA_CTRL_PRE 7 12 RESERVED_15_13 13 15 ixDPCSSYS_CR1_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_3 2 0x10a6 2 0 4294967295 TX_ANA_CTRL_POST 0 8 RESERVED_15_9 9 15 ixDPCSSYS_CR1_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_4 2 0x10a7 1 0 4294967295 TX_ANA_CTRL_LEG_PULL_DIR_19_4 0 15 ixDPCSSYS_CR1_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_5 2 0x10a8 2 0 4294967295 TX_ANA_CTRL_LEG_PULL_DIR_3_0 0 3 RESERVED_15_4 4 15 ixDPCSSYS_CR1_LANE0_DIG_ANA_STATUS_0 2 0x10bb 9 0 4294967295 TX_ANA_CLK_SHIFT_ACK 0 0 TX_ANA_RXDETP_RESULT 1 1 TX_ANA_RXDETM_RESULT 2 2 TX_ANA_LOOPBACK_EN 3 3 TX_ANA_CLK_LB_EN 4 4 RX_ANA_CAL_RESULT 5 5 RX_ANA_SCOPE_DATA 6 6 TX_ANA_DCC_CAL_RESULT 7 7 TX_ANA_CTRL_EQ_MUX 8 15 ixDPCSSYS_CR1_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT 2 0x10c2 8 0 4294967295 TX_ANA_DCC_CAL_RANGE 0 1 TX_ANA_DCC_CAL_RANGE_OVRD_EN 2 2 TX_ANA_DCC_CAL_COMP_EN 3 3 TX_ANA_DCC_CAL_COMP_EN_OVRD_EN 4 4 TX_ANA_DCC_CAL_CTRL 5 12 TX_ANA_DCC_CAL_CTRL_OVRD_EN 13 13 TX_ANA_DCC_CAL_CTRL_EN 14 14 TX_ANA_DCC_CAL_CTRL_EN_OVRD_EN 15 15 ixDPCSSYS_CR1_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2 2 0x10c3 5 0 4294967295 TX_ANA_DCC_CAL_CTRL_SEL 0 2 TX_ANA_DCC_CAL_CTRL_SEL_OVRD_EN 3 3 TX_ANA_DCC_CLK_COMP 4 4 TX_ANA_DCC_CLK_COMP_OVRD_EN 5 5 RESERVED_15_6 6 15 ixDPCSSYS_CR1_LANE0_DIG_ANA_TX_OVRD_OUT_2 2 0x10c4 6 0 4294967295 TX_ANA_FAST_START 0 0 TX_ANA_FAST_START_OVRD_EN 1 1 TX_CLK_LB_EN 2 2 TX_CLK_LB_EN_OVRD_EN 3 3 TX_ACJTAG_EN 4 4 RESERVED_15_5 5 15 ixDPCSSYS_CR1_LANE0_ANA_TX_OVRD_MEAS 2 0x10e0 9 0 4294967295 OVRD_CLK_SHIFT 0 0 CLK_SHIFT_REG 0 0 MEAS_ATB_CAL_MUX 0 0 MEAS_ATB_CAL_COMP 0 0 OVRD_VCM_HOLD 0 0 VCM_HOLD_REG 0 0 PULL_UP_REG 0 0 PULL_DN_REG 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR1_LANE0_ANA_TX_PWR_OVRD 2 0x10e1 9 0 4294967295 OVRD_TX_LOOPBACK 0 0 LOOPBACK_EN_REG 0 0 REFGEN_EN_REG 0 0 CLK_DIV_EN_REG 0 0 DATA_EN_REG_INT 0 0 CLK_EN_REG 0 0 SERIAL_EN_REG 0 0 OVRD_EN 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR1_LANE0_ANA_TX_ALT_BUS 2 0x10e2 6 0 4294967295 DRV_SOURCE_REG 0 0 OVRD_ALT_BUS 0 0 ATB_S_ENABLE 0 0 TX_ALT_RINGO 0 0 JTAG_DATA_REG 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR1_LANE0_ANA_TX_ATB1 2 0x10e3 9 0 4294967295 MEAS_ATB_GD 0 0 MEAS_ATB_VDDH 0 0 OVERRIDE_RXDETREF 0 0 MEAS_ATB_VPTX 0 0 OVERRIDE_REGREF 0 0 MEAS_ATB_VREG_DRV 0 0 MEAS_ATB_VREG 0 0 MEAS_ATB_VPH_HALF 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR1_LANE0_ANA_TX_ATB2 2 0x10e4 9 0 4294967295 MEAS_ATB_VCM 0 0 MEAS_ATB_CAL_VDAC_CM 0 0 MEAS_ATB_CAL_VDAC_DIFF 0 0 MEAS_ATB_TXM 0 0 MEAS_ATB_TXP 0 0 MEAS_ATB_RXDETREF 0 0 LFPS_HIGH_PRIORITY 0 0 OSC_DIV4_EN 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR1_LANE0_ANA_TX_DCC_DAC 2 0x10e5 2 0 4294967295 DCC_DAC_REG 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR1_LANE0_ANA_TX_DCC_CTRL1 2 0x10e6 7 0 4294967295 NC0 0 0 OVRD_DCC_DAC_CTRL_SEL 0 0 DCC_DAC_CTRL_SEL_REG 0 0 OVRD_DCC_DAC_CTRL_EN 0 0 DCC_DAC_CTRL_EN_REG 0 0 OVRD_DCC_DAC_REG 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR1_LANE0_ANA_TX_TERM_CODE 2 0x10e7 2 0 4294967295 TERM_CODE_REG_70 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR1_LANE0_ANA_TX_TERM_CODE_CTRL 2 0x10e8 8 0 4294967295 VREG_BOOST_1 0 0 OVRD_UPDATE_TERM 0 0 UPDATE_TERM_REG 0 0 OVRD_RESET_TERM 0 0 RESET_TERM_REG 0 0 OVRD_TERM_CODE 0 0 TERM_CODE_REG_98 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR1_LANE0_ANA_TX_OVRD_CLK 2 0x10e9 9 0 4294967295 VREG_BOOST_0 0 0 CLK_LB_EN_REG 0 0 OVRD_LB_EN 0 0 MPLLB_CLK_EN_REG 0 0 MPLLA_CLK_EN_REG 0 0 OVRD_MPLLAB_EN 0 0 WORD_CLK_EN_REG 0 0 OVRD_WORD_CLK_EN 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR1_LANE0_ANA_TX_MISC1 2 0x10ea 8 0 4294967295 MEAS_ATB_CAL_CLK_ALIGN 0 0 OVRD_DCC_DAC_CTRL_RANGE 0 0 DCC_DAC_CTRL_RANGE_REG 0 0 OVRD_VREF_SEL 0 0 VREF_SEL_REG 0 0 FORCE_ATB_TXM 0 0 FORCE_ATB_TXP 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR1_LANE0_ANA_TX_MISC2 2 0x10eb 8 0 4294967295 TX_PEAKING_LVL 0 0 VREG_CP_GAIN_CTRL 0 0 TX_SLEW_EN 0 0 EN_INV_POST 0 0 EN_INV_PRE 0 0 TX_VREG_EN_BYP 0 0 TX_VDRIVER_PULLDN_EN 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR1_LANE0_ANA_TX_MISC3 2 0x10ec 4 0 4294967295 TX_VREG_OVRD_RING_CTRL 0 0 TX_DCC_LOWV 0 0 NC7_2 2 7 RESERVED_15_8 8 15 ixDPCSSYS_CR1_LANE0_ANA_TX_RESERVED2 2 0x10ed 2 0 4294967295 NC7_0 0 7 RESERVED_15_8 8 15 ixDPCSSYS_CR1_LANE0_ANA_TX_RESERVED3 2 0x10ee 2 0 4294967295 NC7_0 0 7 RESERVED_15_8 8 15 ixDPCSSYS_CR1_LANE0_ANA_TX_RESERVED4 2 0x10ef 2 0 4294967295 NC7_0 0 7 RESERVED_15_8 8 15 ixDPCSSYS_CR1_LANE1_DIG_ASIC_LANE_OVRD_IN 2 0x1100 5 0 4294967295 LANE_TX2RX_SER_LB 0 0 LANE_RX2TX_PAR_LB 1 1 EN 2 2 RX_ACJTAG_EN 3 3 RESERVED_15_4 4 15 ixDPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_0 2 0x1101 12 0 4294967295 REQ 0 0 REQ_OVRD_EN 1 1 PSTATE 2 3 PSTATE_OVRD_EN 4 4 RATE 5 7 RATE_OVRD_EN 8 8 WIDTH 9 10 WIDTH_OVRD_EN 11 11 MPLLB_SEL 12 12 MPLLB_SEL_OVRD_EN 13 13 DATA_EN 14 14 DATA_EN_OVRD_EN 15 15 ixDPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_1 2 0x1102 11 0 4294967295 NYQUIST_DATA 0 0 DISABLE 1 1 BEACON_EN 2 2 EN 3 3 TX_MAIN_CURSOR 4 9 MAIN_OVRD_EN 10 10 ASYNC_DRV_EN 11 11 ASYNC_DRV_OVRD_EN 12 12 TX_VREGDRV_BYP_OVRD 13 13 TX_VREGDRV_BYP_OVRD_EN 14 14 RESERVED_15_15 15 15 ixDPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_2 2 0x1103 6 0 4294967295 TX_PRE_CURSOR 0 5 PRE_OVRD_EN 6 6 TX_POST_CURSOR 7 12 POST_OVRD_EN 13 13 HDMIMODE_EN 14 14 HDMIMODE_ENABLE_OVRD_EN 15 15 ixDPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_3 2 0x1104 15 0 4294967295 CLK_RDY 0 0 CLK_RDY_OVRD_EN 1 1 DETECT_RX_REQ 2 2 DETECT_RX_REQ_OVRD_EN 3 3 INVERT 4 4 INVERT_OVRD_EN 5 5 LPD 6 6 LPD_OVRD_EN 7 7 TX_DC_COUP_EN 8 8 TX_DC_COUP_EN_OVRD_EN 9 9 PMA_EXTENDED_FIFO_EN 10 10 PMA_EXTENDED_FIFO_EN_OVRD_EN 11 11 TX_MPHY_MODE_EN 12 12 TX_MPHY_MODE_EN_OVRD_EN 13 13 RESERVED_15_14 14 15 ixDPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_4 2 0x1105 3 0 4294967295 RESET 0 0 RESET_OVRD_EN 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_OUT 2 0x1106 5 0 4294967295 TX_ACK 0 0 EN_TX_ACK 1 1 DETRX_RESULT 2 2 EN_DETRX_RESULT 3 3 RESERVED_15_4 4 15 ixDPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_0 2 0x1107 11 0 4294967295 REQ 0 0 REQ_OVRD_EN 1 1 DATA_EN 2 2 DATA_EN_OVRD_EN 3 3 PSTATE 4 5 PSTATE_OVRD_EN 6 6 RATE 7 8 RATE_OVRD_EN 9 9 WIDTH 10 11 WIDTH_OVRD_EN 12 12 RESERVED_15_13 13 15 ixDPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_1 2 0x1108 5 0 4294967295 RX_REF_LD_VAL_5_0 0 5 RX_CDR_VCO_LOWFREQ 6 6 EN 7 7 RX_REF_LD_VAL_6 8 8 RESERVED_15_9 9 15 ixDPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_2 2 0x1109 3 0 4294967295 RX_VCO_LD_VAL 0 12 EN 13 13 RESERVED_15_14 14 15 ixDPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_3 2 0x110a 11 0 4294967295 CDR_TRACK_EN 0 0 CDR_TRACK_EN_OVRD_EN 1 1 CDR_SSC_EN 2 2 CDR_SSC_EN_OVRD_EN 3 3 ALIGN_EN 4 4 ALIGN_EN_OVRD_EN 5 5 CLK_SHIFT 6 6 CLK_SHIFT_OVRD_EN 7 7 DISABLE 8 8 DISABLE_OVRD_EN 9 9 RESERVED_15_10 10 15 ixDPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_4 2 0x110b 11 0 4294967295 LPD 0 0 LPD_OVRD_EN 1 1 INVERT 2 2 INVERT_OVRD_EN 3 3 ADAPT_AFE_EN 4 4 ADAPT_DFE_EN 5 5 ADPT_OVRD_EN 6 6 TERM_EN 7 7 TERM_ACDC 8 8 TERM_OVRD_EN 9 9 RESERVED_15_10 10 15 ixDPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_5 2 0x110c 3 0 4294967295 RESET 0 0 RESET_OVRD_EN 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0 2 0x110d 4 0 4294967295 EQ_ATT_LVL 0 2 EQ_AFE_GAIN 3 6 RESERVED 7 10 EQ_CTLE_BOOST 11 15 ixDPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1 2 0x110e 3 0 4294967295 EQ_DFE_TAP2 0 6 EQ_DFE_TAP1 7 14 EQ_OVRD_EN 15 15 ixDPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_OUT_0 2 0x110f 9 0 4294967295 ACK 0 0 ACK_OVRD_EN 1 1 ADAPT_STS 2 3 ADAPT_STS_OVRD_EN 4 4 RX_ASYNC_DATA 5 5 RX_ASYNC_DATA_OVRD_EN 6 6 RX_SQ_WEAKKEEP_OUT 7 7 RX_SQ_WEAKKEEP_OUT_OVRD_EN 8 8 RESERVED_15_9 9 15 ixDPCSSYS_CR1_LANE1_DIG_ASIC_LANE_ASIC_IN 2 0x1110 3 0 4294967295 LANE_TX2RX_SER_LB 0 0 LANE_RX2TX_PAR_LB 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR1_LANE1_DIG_ASIC_TX_ASIC_IN_0 2 0x1111 12 0 4294967295 CLK_RDY 0 0 RESET 1 1 INVERT 2 2 DATA_EN 3 3 REQ 4 4 LPD 5 5 PSTATE 6 7 RATE 8 10 WIDTH 11 12 MPLLB_SEL 13 13 DETECT_RX_REQ 14 14 DISABLE 15 15 ixDPCSSYS_CR1_LANE1_DIG_ASIC_TX_ASIC_IN_1 2 0x1112 7 0 4294967295 BEACON_EN 0 0 TX_MAIN_CURSOR 1 6 TX_ASYNC_EN 7 7 TX_ASYNC_DATA 8 8 TX_ASYNC_DRV_EN 9 9 TX_VREGDRV_BYP 10 10 RESERVED_15_11 11 15 ixDPCSSYS_CR1_LANE1_DIG_ASIC_TX_ASIC_IN_2 2 0x1113 3 0 4294967295 TX_PRE_CURSOR 0 5 TX_POST_CURSOR 6 11 RESERVED_15_12 12 15 ixDPCSSYS_CR1_LANE1_DIG_ASIC_TX_ASIC_OUT 2 0x1114 3 0 4294967295 TX_ACK 0 0 DETRX_RESULT 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR1_LANE1_DIG_ASIC_RX_ASIC_IN_0 2 0x1115 13 0 4294967295 RESET 0 0 INVERT 1 1 DATA_EN 2 2 REQ 3 3 LPD 4 4 PSTATE 5 6 RATE 7 8 WIDTH 9 10 RESERVED 11 11 ADAPT_AFE_EN 12 12 ADAPT_DFE_EN 13 13 CDR_TRACK_EN 14 14 RESERVED_15_15 15 15 ixDPCSSYS_CR1_LANE1_DIG_ASIC_RX_ASIC_IN_1 2 0x1116 7 0 4294967295 CDR_SSC_EN 0 0 ALIGN_EN 1 1 CLK_SHIFT 2 2 DISABLE 3 3 RX_TERM_EN 4 4 RX_TERM_ACDC 5 5 RESERVED_15_6 6 15 ixDPCSSYS_CR1_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0 2 0x1117 4 0 4294967295 EQ_ATT_LVL 0 2 EQ_AFE_GAIN 3 6 RESERVED 7 10 EQ_CTLE_BOOST 11 15 ixDPCSSYS_CR1_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_1 2 0x1118 3 0 4294967295 EQ_DFE_TAP2 0 6 EQ_DFE_TAP1 7 14 RESERVED_15_15 15 15 ixDPCSSYS_CR1_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0 2 0x1119 3 0 4294967295 RX_CDR_VCO_LOWFREQ 0 0 RX_REF_LD_VAL 1 7 RESERVED_15_8 8 15 ixDPCSSYS_CR1_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1 2 0x111a 2 0 4294967295 RX_VCO_LD_VAL 0 12 RESERVED_15_13 13 15 ixDPCSSYS_CR1_LANE1_DIG_ASIC_RX_ASIC_OUT_0 2 0x111b 4 0 4294967295 ACK 0 0 VALID 1 1 ADAPT_STS 2 3 RESERVED_15_4 4 15 ixDPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_6 2 0x111c 10 0 4294967295 RX_PWM_CLK_SEL 0 1 RX_PWM_CLK_SEL_OVRD_EN 2 2 RX_TERM_LCC_ON 3 3 RX_TERM_LS_ON 4 4 RX_TERM_LS_LCC_ON_OVRD_EN 5 5 RX_TERM_CTL 6 7 RX_TERM_CTL_OVRD_EN 8 8 RX_PWM_EN 9 9 RX_PWM_EN_OVRD_EN 10 10 RESERVED_15_11 11 15 ixDPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_5 2 0x111d 15 0 4294967295 RPTR_EN_MASTER_LANE 0 0 RPTR_EN_MASTER_LANE_OVRD_EN 1 1 DIG_CLK_EN_OTHER_LANE 2 2 DIG_CLK_EN_OTHER_LANE_OVRD_EN 3 3 DIG_CLK_STATE_MASTER_LANE 4 4 DIG_CLK_STATE_MASTER_LANE_OVRD_EN 5 5 SHIFT_MASTER_LANE 6 6 SHIFT_MASTER_LANE_ORVD_EN 7 7 SHIFT_ACK_OTHER_LANE 8 8 SHIFT_ACK_OTHER_LANE_OVRD_EN 9 9 LANE_MASTER 10 10 LANE_MASTER_OVRD_IN_EN 11 11 TX_DWORD_CLK_SYNC_OVRD 12 12 TX_DWORD_CLK_SYNC_OVRD_EN 13 13 RESERVED_15_14 14 15 ixDPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_OUT_1 2 0x111e 11 0 4294967295 RPTR_EN_OUT 0 0 RPTR_EN_OUT_OVRD_EN 1 1 DIG_CLK_EN_OUT 2 2 DIG_CLK_EN_OUT_OVRD_EN 3 3 DIG_CLK_STATE_OUT 4 4 DIG_CLK_STATE_OUT_OVRD_EN 5 5 SHIFT_OUT 6 6 SHIFT_OUT_OVRD_EN 7 7 SHIFT_ACK_OUT 8 8 SHIFT_ACK_OUT_OVRD_EN 9 9 RESERVED_15_10 10 15 ixDPCSSYS_CR1_LANE1_DIG_ASIC_OCLA 2 0x111f 3 0 4294967295 RX_DWORD_OCLA_CLK_EN 0 0 RX_DWORD_OCLA_DATA_EN 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0 2 0x1120 11 0 4294967295 TX_P0_ANA_REFGEN_EN 0 0 TX_P0_ANA_VCM_HOLD 1 1 TX_P0_ANA_CLK_EN 2 2 TX_P0_ANA_WORD_CLK_EN 3 3 TX_P0_ANA_RESET 4 4 TX_P0_ANA_SERIAL_EN 5 5 TX_P0_DIG_CLK_EN 6 6 TX_P0_DATA_EN 7 7 TX_P0_ALLOW_RXDET 8 8 TX_P0_ANA_DCC_COMP_CAL_EN 9 9 RESERVED_15_10 10 15 ixDPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S 2 0x1121 11 0 4294967295 TX_P0S_ANA_REFGEN_EN 0 0 TX_P0S_ANA_VCM_HOLD 1 1 TX_P0S_ANA_CLK_EN 2 2 TX_P0S_ANA_WORD_CLK_EN 3 3 TX_P0S_ANA_RESET 4 4 TX_P0S_ANA_SERIAL_EN 5 5 TX_P0S_DIG_CLK_EN 6 6 TX_P0S_DATA_EN 7 7 TX_P0S_ALLOW_RXDET 8 8 TX_P0S_ANA_DCC_COMP_CAL_EN 9 9 RESERVED_15_10 10 15 ixDPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1 2 0x1122 11 0 4294967295 TX_P1_ANA_REFGEN_EN 0 0 TX_P1_ANA_VCM_HOLD 1 1 TX_P1_ANA_CLK_EN 2 2 TX_P1_ANA_WORD_CLK_EN 3 3 TX_P1_ANA_RESET 4 4 TX_P1_ANA_SERIAL_EN 5 5 TX_P1_DIG_CLK_EN 6 6 TX_P1_DATA_EN 7 7 TX_P1_ALLOW_RXDET 8 8 TX_P1_ANA_DCC_COMP_CAL_EN 9 9 RESERVED_15_10 10 15 ixDPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2 2 0x1123 12 0 4294967295 TX_P2_ANA_REFGEN_EN 0 0 TX_P2_ANA_VCM_HOLD 1 1 TX_P2_ANA_CLK_EN 2 2 TX_P2_ANA_WORD_CLK_EN 3 3 TX_P2_ANA_RESET 4 4 TX_P2_ANA_SERIAL_EN 5 5 TX_P2_DIG_CLK_EN 6 6 TX_P2_DATA_EN 7 7 TX_P2_ALLOW_RXDET 8 8 TX_P2_ALLOW_VBOOST 9 9 TX_P2_ANA_DCC_COMP_CAL_EN 10 10 RESERVED_15_11 11 15 ixDPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_0 2 0x1124 2 0 4294967295 TX_REFGEN_EN_TIME 0 7 TX_CLK_EN 8 15 ixDPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_1 2 0x1125 2 0 4294967295 TX_VCM_HOLD_TIME_14_0 0 14 SKIP_TX_VCM_HOLD_WAIT 15 15 ixDPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_2 2 0x1126 2 0 4294967295 TX_VBOOST_DIS_TIME_12_0 0 12 DTB_SEL 13 15 ixDPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_3 2 0x1127 3 0 4294967295 TX_VCM_HOLD_TIME_17_15 0 2 TX_VBOOST_DIS_TIME_13 3 3 RESERVED_15_4 4 15 ixDPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_4 2 0x1128 2 0 4294967295 TX_VCM_HOLD_GS_TIME 0 14 SKIP_TX_VCM_HOLD_GS_PULSE 15 15 ixDPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_5 2 0x1129 5 0 4294967295 TX_RXDET_TIME 0 9 FAST_TX_RXDET 10 10 TX_RESET_TIME 11 12 TX_SERIAL_EN_TIME 13 14 RESERVED_15_15 15 15 ixDPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_DCC_CR_BANK_ADDR 2 0x112a 1 0 4294967295 ADDR 0 15 ixDPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_DCC_CR_BANK_DATA 2 0x112b 1 0 4294967295 DATA 0 15 ixDPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_DCC_DAC_CTRL 2 0x112c 2 0 4294967295 CTRL 0 7 RESERVED_15_8 8 15 ixDPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_DCC_DAC_RANGE 2 0x112d 2 0 4294967295 CTRL 0 1 RESERVED_15_2 2 15 ixDPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_DCC_DAC_SEL 2 0x112e 6 0 4294967295 SEL 0 2 REQ 3 3 CTRL_UPD 4 4 RANGE_UPD 5 5 BIN_HOT 6 6 RESERVED_15_7 7 15 ixDPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_DCC_DAC_ACK 2 0x112f 2 0 4294967295 ACK 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_DCC_DAC_ADDR 2 0x1130 1 0 4294967295 ADDR 0 15 ixDPCSSYS_CR1_LANE1_DIG_TX_CLK_ALIGN_TX_CTL_0 2 0x1131 4 0 4294967295 TX_NUM_2UI_SHIFTS_16B_MODE 0 3 TX_NUM_2UI_SHIFTS_20B_MODE 4 7 TX_FIFO_BYPASS 8 8 RESERVED_15_9 9 15 ixDPCSSYS_CR1_LANE1_DIG_TX_LBERT_CTL 2 0x1132 4 0 4294967295 MODE 0 3 TRIGGER_ERR 4 4 PAT0 5 14 RESERVED_15_15 15 15 ixDPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0 2 0x1140 12 0 4294967295 RX_P0_ANA_AFE_EN 0 0 RX_P0_ANA_CLK_VREG_EN 1 1 RESERVED_1 2 2 RX_P0_ANA_CLK_EN 3 3 RESERVED_0 4 4 RX_P0_ANA_DESER_EN 5 5 RX_P0_ANA_CDR_EN 6 6 RX_P0_VCO_FREQ_RST 7 7 RX_P0_VCO_CAL_RST 8 8 RX_P0_VCO_CONTCAL_EN 9 9 RX_P0_DIG_CLK_EN 10 10 RESERVED_15_11 11 15 ixDPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S 2 0x1141 12 0 4294967295 RX_P0S_ANA_AFE_EN 0 0 RX_P0S_ANA_CLK_VREG_EN 1 1 RESERVED_2 2 2 RX_P0S_ANA_CLK_EN 3 3 RESERVED_4 4 4 RX_P0S_ANA_DESER_EN 5 5 RX_P0S_ANA_CDR_EN 6 6 RX_P0S_VCO_FREQ_RST 7 7 RX_P0S_VCO_CAL_RST 8 8 RX_P0S_VCO_CONTCAL_EN 9 9 RX_P0S_DIG_CLK_EN 10 10 RESERVED_15_11 11 15 ixDPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1 2 0x1142 12 0 4294967295 RX_P1_ANA_AFE_EN 0 0 RX_P1_ANA_CLK_VREG_EN 1 1 RESERVED_2 2 2 RX_P1_ANA_CLK_EN 3 3 RESERVED_4 4 4 RX_P1_ANA_DESER_EN 5 5 RX_P1_ANA_CDR_EN 6 6 RX_P1_VCO_FREQ_RST 7 7 RX_P1_VCO_CAL_RST 8 8 RX_P1_VCO_CONTCAL_EN 9 9 RX_P1_DIG_CLK_EN 10 10 RESERVED_15_11 11 15 ixDPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2 2 0x1143 12 0 4294967295 RX_P2_ANA_AFE_EN 0 0 RX_P2_ANA_CLK_VREG_EN 1 1 RESERVED_2 2 2 RX_P2_ANA_CLK_EN 3 3 RESERVED_4 4 4 RX_P2_ANA_DESER_EN 5 5 RX_P2_ANA_CDR_EN 6 6 RX_P2_VCO_FREQ_RST 7 7 RX_P2_VCO_CAL_RST 8 8 RX_P2_VCO_CONTCAL_EN 9 9 RX_P2_DIG_CLK_EN 10 10 RESERVED_15_11 11 15 ixDPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1 2 0x1145 5 0 4294967295 RX_AFE_EN_TIME 0 5 FAST_RX_AFE_EN 6 6 RX_VREG_EN_TIME 7 12 FAST_RX_VREG_EN 13 13 RESERVED_15_14 14 15 ixDPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_2 2 0x1146 4 0 4294967295 RX_CLK_EN_TIME 0 5 FAST_RX_CLK_EN 6 6 RX_FAST_START_TIME 7 10 RESERVED_15_11 11 15 ixDPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_3 2 0x1147 5 0 4294967295 RX_RATE_TIME 0 1 RSVD_3_7_2 2 7 RX_CDR_EN_TIME 8 11 RX_DESER_EN_TIME 12 13 RX_DESER_DIS_TIME 14 15 ixDPCSSYS_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0 2 0x1148 8 0 4294967295 INT_GAIN_CAL_FIXED_CNT 0 4 INT_GAIN_CAL_FIXED_CNT_EN 5 5 INT_GAIN_CAL_CNT_SHIFT 6 8 INT_GAIN_CAL_BOUNCE_CNT 9 11 DISABLE_BIN_HOLD 12 12 DISABLE_INT_GAIN_HOLD 13 13 DISABLE_COARSE_CALDONE 14 14 RESERVED_15_15 15 15 ixDPCSSYS_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1 2 0x1149 7 0 4294967295 RX_VCO_OVRD_SEL 0 0 RX_VCO_FREQ_RST 1 1 RX_VCO_CAL_RST 2 2 RX_VCO_CONTCAL_EN 3 3 DISABLE_INT_CAL_MODE 4 4 DPLL_CAL_UG 5 8 DTB_SEL 9 15 ixDPCSSYS_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2 2 0x114a 4 0 4294967295 FREQ_TUNE_START_VAL 0 9 FREQ_TUNE_CAL_STEPS 10 13 SKIP_RX_VCO_FREQ_TUNE_CAL 14 14 SKIP_RX_VCO_CAL 15 15 ixDPCSSYS_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0 2 0x114b 4 0 4294967295 RX_VCO_STARTUP_TIME 0 6 RX_VCO_UPDATE_TIME 7 10 RX_VCO_CNTR_PWRUP_TIME 11 14 FAST_RX_VCO_WAIT 15 15 ixDPCSSYS_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1 2 0x114c 2 0 4294967295 RX_VCO_CNTR_SETTLE_TIME 0 2 RESERVED_15_3 3 15 ixDPCSSYS_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0 2 0x114d 6 0 4294967295 RX_ANA_CDR_FREQ_TUNE 0 9 RX_ANA_VCO_CNTR_PD 10 10 RX_ANA_VCO_CNTR_EN 11 11 RX_ANA_CDR_STARTUP 12 12 RX_ANA_CDR_VCO_EN 13 13 RESERVED_15_14 14 15 ixDPCSSYS_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1 2 0x114e 7 0 4294967295 RX_VCO_FSM_STATE 0 3 RX_VCO_FREQ_RST 4 4 RX_VCO_CAL_RST 5 5 RX_VCO_CONTCAL_EN 6 6 RX_VCO_CAL_DONE 7 7 DPLL_FREQ_RST 8 8 RESERVED_15_9 9 15 ixDPCSSYS_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_2 2 0x114f 4 0 4294967295 VCO_CNTR_FINAL 0 12 VCOCLK_TOO_FAST 13 13 RX_VCO_CORRECT 14 14 RX_VCO_UP 15 15 ixDPCSSYS_CR1_LANE1_DIG_RX_RX_ALIGN_XAUI_COMM_MASK 2 0x1150 2 0 4294967295 XAUI_COMM_MASK 0 9 RESERVED_15_10 10 15 ixDPCSSYS_CR1_LANE1_DIG_RX_LBERT_CTL 2 0x1151 3 0 4294967295 MODE 0 3 SYNC 4 4 RESERVED_15_5 5 15 ixDPCSSYS_CR1_LANE1_DIG_RX_LBERT_ERR 2 0x1152 2 0 4294967295 COUNT 0 14 OV14 15 15 ixDPCSSYS_CR1_LANE1_DIG_RX_CDR_CDR_CTL_0 2 0x1153 7 0 4294967295 PHDET_EN 0 1 PHDET_EDGE 2 3 PHDET_POL 4 4 PHDET_EN_PR_MODE 5 5 ALWAYS_REALIGN 6 6 DTB_SEL 7 10 RESERVED_15_11 11 15 ixDPCSSYS_CR1_LANE1_DIG_RX_CDR_CDR_CTL_1 2 0x1154 2 0 4294967295 SSC_OFF_CNT0 0 9 SSC_OFF_CNT1 10 15 ixDPCSSYS_CR1_LANE1_DIG_RX_CDR_CDR_CTL_2 2 0x1155 2 0 4294967295 SSC_ON_CNT0 0 8 SSC_ON_CNT1 9 15 ixDPCSSYS_CR1_LANE1_DIG_RX_CDR_CDR_CTL_3 2 0x1156 6 0 4294967295 SSC_OFF_PHUG0 0 2 SSC_OFF_PHUG1 3 5 SSC_OFF_FRUG0 6 8 OVRD_DPLL_GAIN 9 9 PHUG_OVRD_VALUE 10 12 FRUG_OVRD_VALUE 13 15 ixDPCSSYS_CR1_LANE1_DIG_RX_CDR_CDR_CTL_4 2 0x1157 6 0 4294967295 SSC_OFF_FRUG1 0 2 SSC_ON_FRUG0 3 5 SSC_ON_FRUG1 6 8 SSC_ON_PHUG0 9 11 SSC_ON_PHUG1 12 14 RESERVED_15_15 15 15 ixDPCSSYS_CR1_LANE1_DIG_RX_CDR_STAT 2 0x1158 3 0 4294967295 PHUG_VALUE 0 2 FRUG_VALUE 3 5 RESERVED_15_6 6 15 ixDPCSSYS_CR1_LANE1_DIG_RX_DPLL_FREQ 2 0x1159 2 0 4294967295 VAL 0 13 RESERVED_15_14 14 15 ixDPCSSYS_CR1_LANE1_DIG_RX_DPLL_FREQ_BOUND_0 2 0x115a 3 0 4294967295 FREQ_BOUND_EN 0 0 UPPER_FREQ_BOUND 1 10 RESERVED_15_11 11 15 ixDPCSSYS_CR1_LANE1_DIG_RX_DPLL_FREQ_BOUND_1 2 0x115b 2 0 4294967295 LOWER_FREQ_BOUND 0 9 RESERVED_15_10 10 15 ixDPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_0 2 0x1160 4 0 4294967295 N_TOP_ASM1 0 9 N_TGG_ASM1 10 13 START_ASM1 14 14 ADPT_CLK_DIV4_EN 15 15 ixDPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1 2 0x1161 5 0 4294967295 N_WAIT_ASM1 0 6 FAST_AFE_DFE_SETTLE 7 7 CTLE_POLE_OVRD_VAL 8 10 CTLE_POLE_OVRD_EN 11 11 RESERVED_15_12 12 15 ixDPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_2 2 0x1162 3 0 4294967295 TGG_PTTRN_0 0 4 TGG_PTTRN_1 5 9 RESERVED_15_10 10 15 ixDPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3 2 0x1163 8 0 4294967295 CTLE_EN 0 4 VGA_EN 5 5 ATT_EN 6 6 DFE_EN 7 11 EYEHE_EN 12 12 EYEHO_EN 13 13 TGG_EN 14 14 ESL_TWICE_DSL 15 15 ixDPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_4 2 0x1164 4 0 4294967295 CTLE_TH 0 3 VGA_TH 4 7 DFE1_TH 8 11 DFE2_TH 12 15 ixDPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_5 2 0x1165 4 0 4294967295 DFE3_TH 0 3 DFE4_TH 4 7 DFE5_TH 8 11 TH_OFFSET 12 15 ixDPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6 2 0x1166 6 0 4294967295 CTLE_MU 0 2 VGA_MU 3 5 ATT_MU 6 8 VGA_SAT_CNT 9 11 VGA_SAT_CNT_STICKY 12 12 ATT_LOW_TH 13 15 ixDPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_7 2 0x1167 4 0 4294967295 VGA_MIN_SAT 0 4 VGA_LEV_HIGH 5 9 VGA_LEV_LOW 10 14 RESERVED_15_15 15 15 ixDPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8 2 0x1168 6 0 4294967295 DFE1_MU 0 2 DFE2_MU 3 5 DFE3_MU 6 8 DFE4_MU 9 11 DFE5_MU 12 14 RESERVED_15_15 15 15 ixDPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_9 2 0x1169 2 0 4294967295 ERR_SLE_ADPT_INIT 0 7 ERR_SLO_ADPT_INIT 8 15 ixDPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG 2 0x116a 6 0 4294967295 RST_ADPT_ATT 0 0 RST_ADPT_VGA 1 1 RST_ADPT_CTLE_BOOST 2 2 RST_ADPT_CTLE_POLE 3 3 RST_ADPT_TAP1 4 4 RESERVED_15_5 5 15 ixDPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ATT_STATUS 2 0x116b 3 0 4294967295 ATT_ADPT_CODE 0 7 ASM1_DON 8 8 RESERVED_15_9 9 15 ixDPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_VGA_STATUS 2 0x116c 3 0 4294967295 VGA_ADPT_CODE 0 9 ASM1_DONE 10 10 RESERVED_15_11 11 15 ixDPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_CTLE_STATUS 2 0x116d 4 0 4294967295 CTLE_BOOST_ADPT_CODE 0 9 CTLE_POLE_ADPT_CODE 10 12 ASM1_DONE 13 13 RESERVED_15_14 14 15 ixDPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_DFE_TAP1_STATUS 2 0x116e 3 0 4294967295 DFE_TAP1_ADPT_CODE 0 12 ASM1_DONE 13 13 RESERVED_15_14 14 15 ixDPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_DFE_TAP2_STATUS 2 0x116f 3 0 4294967295 DFE_TAP2_ADPT_CODE 0 11 ASM1_DONE 12 12 RESERVED_15_13 13 15 ixDPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_DFE_TAP3_STATUS 2 0x1170 3 0 4294967295 DFE_TAP3_ADPT_CODE 0 11 ASM1_DONE 12 12 RESERVED_15_13 13 15 ixDPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_DFE_TAP4_STATUS 2 0x1171 3 0 4294967295 DFE_TAP4_ADPT_CODE 0 11 ASM1_DONE 12 12 RESERVED_15_13 13 15 ixDPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_DFE_TAP5_STATUS 2 0x1172 3 0 4294967295 DFE_TAP5_ADPT_CODE 0 11 ASM1_DONE 12 12 RESERVED_15_13 13 15 ixDPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_DFE_DATA_EVEN_VDAC_OFST 2 0x1173 2 0 4294967295 DFE_DATA_EVEN_VDAC_OFST 0 7 RESERVED_15_8 8 15 ixDPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_DFE_DATA_ODD_VDAC_OFST 2 0x1174 2 0 4294967295 DFE_DATA_ODD_VDAC_OFST 0 7 RESERVED_15_8 8 15 ixDPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN 2 0x1175 2 0 4294967295 RX_ANA_SLICER_CTRL_E 0 3 RESERVED_15_4 4 15 ixDPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD 2 0x1176 2 0 4294967295 RX_ANA_SLICER_CTRL_O 0 3 RESERVED_15_4 4 15 ixDPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST 2 0x1177 2 0 4294967295 DFE_ERROR_EVEN_VDAC_OFST 0 7 RESERVED_15_8 8 15 ixDPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST 2 0x1178 2 0 4294967295 DFE_ERROR_ODD_VDAC_OFST 0 7 RESERVED_15_8 8 15 ixDPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL 2 0x1179 2 0 4294967295 E_SLO_LVL 0 7 E_SLE_LVL 8 15 ixDPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_RESET 2 0x117a 2 0 4294967295 RESET_ASM1 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1 2 0x117b 4 0 4294967295 DFE_T1_IDAC 0 4 DFE_T2_IDAC 5 9 DCC_START_IDAC 10 14 RESERVED_15_15 15 15 ixDPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2 2 0x117c 3 0 4294967295 DFE_DAT_EVEN_VDAC 0 4 DFE_DAT_ODD_VDAC 5 9 RESERVED_15_10 10 15 ixDPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3 2 0x117d 3 0 4294967295 DFE_ERR_EVEN_VDAC 0 4 DFE_ERR_ODD_VDAC 5 9 RESERVED_15_10 10 15 ixDPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_CR_BANK_ADDR 2 0x117e 1 0 4294967295 ADDR 0 15 ixDPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_CR_BANK_DATA 2 0x117f 1 0 4294967295 DATA 0 15 ixDPCSSYS_CR1_LANE1_DIG_RX_STAT_LD_VAL_1 2 0x1180 2 0 4294967295 SC1_LD_VAL 0 14 SC1_START 15 15 ixDPCSSYS_CR1_LANE1_DIG_RX_STAT_DATA_MSK 2 0x1181 1 0 4294967295 DATA_MSK_15_0 0 15 ixDPCSSYS_CR1_LANE1_DIG_RX_STAT_MATCH_CTL0 2 0x1182 4 0 4294967295 PTTRN_MSK_CR1A_4_0 0 4 PTTRN_CR1A_4_0 5 9 DATA_MSK_19_16 10 13 SCOPE_DLY 14 15 ixDPCSSYS_CR1_LANE1_DIG_RX_STAT_MATCH_CTL1 2 0x1183 5 0 4294967295 PTTRN_CR1B_EN 0 0 PTTRN_MSK_CR1B_4_0 1 5 PTTRN_CR1B_4_0 6 10 PTTRN_CR1A_ADPT_EN 11 11 RESERVED_15_12 12 15 ixDPCSSYS_CR1_LANE1_DIG_RX_STAT_STAT_CTL0 2 0x1184 10 0 4294967295 RESERVED_0 0 0 CORR_SHFT_SEL_VGA 1 1 CORR_SHFT_SEL 2 2 CORR_SRC_SEL 3 4 CORR_MODE_EN 5 5 STAT_SHFT_SEL 6 9 STAT_SRC_SEL 10 12 STAT_RXCLK_SEL 13 13 SC_TIMER_MODE 14 14 SKIP_EN 15 15 ixDPCSSYS_CR1_LANE1_DIG_RX_STAT_STAT_CTL1 2 0x1185 13 0 4294967295 STAT_CNT_0_EN 0 0 STAT_CNT_1_EN 1 1 STAT_CNT_2_EN 2 2 STAT_CNT_3_EN 3 3 STAT_CNT_4_EN 4 4 STAT_CNT_5_EN 5 5 STAT_CNT_6_EN 6 6 RESERVED_8_7 7 8 SC_PAUSE 9 9 STAT_CLK_EN 10 10 DATA_DLY_SEL 11 12 VLD_LOSS_CLR 13 13 VLD_CTL 14 15 ixDPCSSYS_CR1_LANE1_DIG_RX_STAT_SMPL_CNT1 2 0x1186 2 0 4294967295 SMPL_CNT1 0 14 SMPL_CNT1_DONE 15 15 ixDPCSSYS_CR1_LANE1_DIG_RX_STAT_STAT_CNT_0 2 0x1187 2 0 4294967295 STAT_CNT_0 0 14 SMPL_CNT1_DONE 15 15 ixDPCSSYS_CR1_LANE1_DIG_RX_STAT_STAT_CNT_1 2 0x1188 2 0 4294967295 STAT_CNT_1 0 14 SMPL_CNT1_DONE 15 15 ixDPCSSYS_CR1_LANE1_DIG_RX_STAT_STAT_CNT_2 2 0x1189 2 0 4294967295 STAT_CNT_2 0 14 SMPL_CNT1_DONE 15 15 ixDPCSSYS_CR1_LANE1_DIG_RX_STAT_STAT_CNT_3 2 0x118a 2 0 4294967295 STAT_CNT_3 0 14 SMPL_CNT1_DONE 15 15 ixDPCSSYS_CR1_LANE1_DIG_RX_STAT_STAT_CNT_4 2 0x118b 2 0 4294967295 STAT_CNT_4 0 14 SMPL_CNT1_DONE 15 15 ixDPCSSYS_CR1_LANE1_DIG_RX_STAT_STAT_CNT_5 2 0x118c 2 0 4294967295 STAT_CNT_5 0 14 SMPL_CNT1_DONE 15 15 ixDPCSSYS_CR1_LANE1_DIG_RX_STAT_STAT_CNT_6 2 0x118d 2 0 4294967295 STAT_CNT_6 0 14 SMPL_CNT1_DONE 15 15 ixDPCSSYS_CR1_LANE1_DIG_RX_STAT_CAL_COMP_CLK_CTL 2 0x118e 3 0 4294967295 PRECHRGE_CNT 0 2 REF_DIV_CNT 3 5 RESERVED_15_6 6 15 ixDPCSSYS_CR1_LANE1_DIG_RX_STAT_MATCH_CTL2 2 0x118f 2 0 4294967295 PTTRN_CR1A_19_5 0 14 RESERVED_15_15 15 15 ixDPCSSYS_CR1_LANE1_DIG_RX_STAT_MATCH_CTL3 2 0x1190 2 0 4294967295 PTTRN_MSK_CR1A_19_5 0 14 RESERVED_15_15 15 15 ixDPCSSYS_CR1_LANE1_DIG_RX_STAT_MATCH_CTL4 2 0x1191 2 0 4294967295 PTTRN_CR1B_19_5 0 14 RESERVED_15_15 15 15 ixDPCSSYS_CR1_LANE1_DIG_RX_STAT_MATCH_CTL5 2 0x1192 2 0 4294967295 PTTRN_MSK_CR1B_19_5 0 14 RESERVED_15_15 15 15 ixDPCSSYS_CR1_LANE1_DIG_RX_STAT_STAT_CTL2 2 0x1193 4 0 4294967295 DATA_DLY_SEL_2 0 0 SCOPE_DLY_2 1 1 DISABLE_SAMPLE_COUNT 2 2 RESERVED_15_3 3 15 ixDPCSSYS_CR1_LANE1_DIG_RX_STAT_STAT_STOP 2 0x1194 2 0 4294967295 SC1_STOP 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR1_LANE1_DIG_MPHY_RX_PWM_CTL 2 0x1195 3 0 4294967295 RX_PWM_POL 0 0 RX_PWM_DATA_POL 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR1_LANE1_DIG_MPHY_RX_TERM_LS_CTL 2 0x1196 2 0 4294967295 RX_TERM_LCC_CNT 0 2 RESERVED_15_3 3 15 ixDPCSSYS_CR1_LANE1_DIG_MPHY_RX_ANA_PWM_CLK_STABLE_CNT 2 0x1197 2 0 4294967295 PWM_CLK_STABLE_CNT 0 3 RESERVED_15_4 4 15 ixDPCSSYS_CR1_LANE1_DIG_ANA_TX_OVRD_OUT 2 0x11a0 15 0 4294967295 TX_ANA_CLK_SHIFT 0 0 TX_ANA_DATA_EN 1 1 TX_ANA_REFGEN_EN 2 2 TX_ANA_VCM_HOLD 3 3 TX_ANA_CLK_EN 4 4 TX_ANA_WORD_CLK_EN 5 5 TX_ANA_MPLLA_CLK_EN 6 6 TX_ANA_MPLLB_CLK_EN 7 7 TX_ANA_RESET 8 8 TX_ANA_SERIAL_EN 9 9 TX_ANA_DATA_RATE 10 11 RESERVED 12 12 TX_DIV4_EN 13 13 TX_RXDET_EN 14 14 TX_OVRD_EN 15 15 ixDPCSSYS_CR1_LANE1_DIG_ANA_TX_TERM_CODE_OVRD_OUT 2 0x11a1 5 0 4294967295 TX_TERM_CODE 0 9 TX_TERM_OVRD_EN 10 10 TX_DRV_SRC 11 12 TX_DRV_SRC_OVRD_EN 13 13 RESERVED_15_14 14 15 ixDPCSSYS_CR1_LANE1_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT 2 0x11a2 3 0 4294967295 TX_TERM_DN_CLK 0 0 TX_TERM_CLK_SELF_CLEAR_DISABLE 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR1_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_0 2 0x11a3 3 0 4294967295 TX_ANA_LOAD_CLK 0 0 TX_ANA_CTRL_LEG_PULL_EN_13_0 1 14 TX_EQ_OVRD_EN 15 15 ixDPCSSYS_CR1_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_1 2 0x11a4 2 0 4294967295 TX_ANA_CTRL_LEG_PULL_EN_19_14 0 5 RESERVED_15_6 6 15 ixDPCSSYS_CR1_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_2 2 0x11a5 4 0 4294967295 RESERVED 0 2 TX_ANA_CTRL_EQ_MUX_SEL 3 6 TX_ANA_CTRL_PRE 7 12 RESERVED_15_13 13 15 ixDPCSSYS_CR1_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_3 2 0x11a6 2 0 4294967295 TX_ANA_CTRL_POST 0 8 RESERVED_15_9 9 15 ixDPCSSYS_CR1_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_4 2 0x11a7 1 0 4294967295 TX_ANA_CTRL_LEG_PULL_DIR_19_4 0 15 ixDPCSSYS_CR1_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_5 2 0x11a8 2 0 4294967295 TX_ANA_CTRL_LEG_PULL_DIR_3_0 0 3 RESERVED_15_4 4 15 ixDPCSSYS_CR1_LANE1_DIG_ANA_RX_CTL_OVRD_OUT 2 0x11a9 9 0 4294967295 RESERVED 0 0 RX_ANA_DATA_RATE 1 2 RX_ANA_WORD_CLK_EN 3 3 RX_ANA_DIV4_EN 4 4 RX_ANA_DFE_TAPS_EN 5 5 RX_ANA_ADAPTATION_EN 6 6 RX_LBK_CLK_EN 7 7 RX_CTL_OVRD_EN 8 8 RESERVED_15_9 9 15 ixDPCSSYS_CR1_LANE1_DIG_ANA_RX_PWR_OVRD_OUT 2 0x11aa 9 0 4294967295 RX_ANA_AFE_EN 0 0 RX_ANA_CLK_VREG_EN 1 1 RX_ANA_CLK_DCC_EN 2 2 RX_ANA_CLK_EN 3 3 RX_ANA_CDR_EN 4 4 RX_ANA_DESERIAL_EN 5 5 RX_PWR_OVRD_EN 6 6 RX_ANA_FAST_START 7 7 RESERVED_15_8 8 15 ixDPCSSYS_CR1_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0 2 0x11ab 7 0 4294967295 RX_ANA_CDR_VCO_EN 0 0 RX_ANA_CDR_STARTUP 1 1 RX_VCO_CDR_OVRD_EN 2 2 RX_ANA_CDR_FREQ_TUNE 3 12 RX_ANA_VCO_CNTR_EN 13 13 RX_ANA_VCO_CNTR_CLK 14 14 RX_CDR_FREQ_TUNE_OVRD_EN 15 15 ixDPCSSYS_CR1_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_1 2 0x11ac 3 0 4294967295 RX_ANA_CDR_VCO_LOWFREQ 0 0 RX_ANA_VCO_CNTR_PD 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR1_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_2 2 0x11ad 3 0 4294967295 RX_ANA_CDR_FREQ_TUNE_CLK 0 0 CDR_FREQ_TUNE_CLK_SELF_CLEAR_DISABLE 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR1_LANE1_DIG_ANA_RX_CAL 2 0x11ae 7 0 4294967295 RX_ANA_CAL_MUXA_SEL 0 4 RX_ANA_CAL_MUXB_SEL 5 9 RX_ANA_CAL_LPFBYP_EN 10 10 RESERVED 11 11 RX_ANA_SLICER_CAL_EN 12 12 RX_ANA_CAL_MODE 13 14 RX_ANA_CAL_COMP_EN 15 15 ixDPCSSYS_CR1_LANE1_DIG_ANA_RX_DAC_CTRL 2 0x11af 2 0 4294967295 RX_ANA_CAL_DAC_CTRL 0 7 RESERVED_15_8 8 15 ixDPCSSYS_CR1_LANE1_DIG_ANA_RX_DAC_CTRL_OVRD 2 0x11b0 2 0 4294967295 RX_CAL_DAC_CTRL_OVRD 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR1_LANE1_DIG_ANA_RX_DAC_CTRL_SEL 2 0x11b1 2 0 4294967295 RX_ANA_CAL_DAC_CTRL_SEL 0 4 RESERVED_15_5 5 15 ixDPCSSYS_CR1_LANE1_DIG_ANA_RX_AFE_ATT_VGA 2 0x11b2 5 0 4294967295 RX_ANA_AFE_ATT_LVL 0 2 RX_ANA_AFE_GAIN 3 6 RESERVED 7 10 RX_AFE_OVRD_EN 11 11 RESERVED_15_12 12 15 ixDPCSSYS_CR1_LANE1_DIG_ANA_RX_AFE_CTLE 2 0x11b3 3 0 4294967295 RESERVED 0 2 RX_ANA_AFE_CTLE_BOOST 3 7 RESERVED_15_8 8 15 ixDPCSSYS_CR1_LANE1_DIG_ANA_RX_SCOPE 2 0x11b4 7 0 4294967295 RX_ANA_SCOPE_EN 0 0 RX_ANA_SCOPE_SEL 1 2 RX_ANA_SCOPE_PH_CLK 3 3 RX_ANA_SCOPE_PHASE 4 11 RX_ANA_SCOPE_CLK_EN 12 12 RX_SCOPE_SELF_CLEAR_DISABLE 13 13 RESERVED_15_14 14 15 ixDPCSSYS_CR1_LANE1_DIG_ANA_RX_SLICER_CTRL 2 0x11b5 4 0 4294967295 RX_ANA_SLICER_CTRL_E 0 3 RX_ANA_SLICER_CTRL_O 4 7 RX_ANA_SLICER_CTRL_OVRD_EN 8 8 RESERVED_15_9 9 15 ixDPCSSYS_CR1_LANE1_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST 2 0x11b6 2 0 4294967295 RX_ANA_IQ_PHASE_ADJUST 0 6 RESERVED_15_7 7 15 ixDPCSSYS_CR1_LANE1_DIG_ANA_RX_ANA_IQ_SENSE_EN 2 0x11b7 2 0 4294967295 RX_ANA_IQ_SENSE_EN 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR1_LANE1_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN 2 0x11b8 3 0 4294967295 RX_ANA_CAL_DAC_CTRL_EN 0 0 DAC_CTRL_SELF_CLEAR_DISABLE 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR1_LANE1_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE 2 0x11b9 3 0 4294967295 RX_ANA_AFE_UPDATE_EN 0 0 AFE_UPDATE_SELF_CLEAR_DISABLE 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR1_LANE1_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK 2 0x11ba 3 0 4294967295 RX_ANA_IQ_PHASE_ADJUST_CLK 0 0 PHASE_ADJUST_SELF_CLEAR_DISABLE 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR1_LANE1_DIG_ANA_STATUS_0 2 0x11bb 9 0 4294967295 TX_ANA_CLK_SHIFT_ACK 0 0 TX_ANA_RXDETP_RESULT 1 1 TX_ANA_RXDETM_RESULT 2 2 TX_ANA_LOOPBACK_EN 3 3 TX_ANA_CLK_LB_EN 4 4 RX_ANA_CAL_RESULT 5 5 RX_ANA_SCOPE_DATA 6 6 TX_ANA_DCC_CAL_RESULT 7 7 TX_ANA_CTRL_EQ_MUX 8 15 ixDPCSSYS_CR1_LANE1_DIG_ANA_STATUS_1 2 0x11bc 2 0 4294967295 RX_ANA_VCO_CNTR 0 12 RESERVED_15_13 13 15 ixDPCSSYS_CR1_LANE1_DIG_ANA_RX_TERM_CODE_OVRD_OUT 2 0x11bd 3 0 4294967295 RX_TERM_CODE 0 5 RX_TERM_OVRD_EN 6 6 RESERVED_15_7 7 15 ixDPCSSYS_CR1_LANE1_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT 2 0x11be 3 0 4294967295 RX_TERM_CLK 0 0 RX_TERM_CLK_SELF_CLEAR_DISABLE 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR1_LANE1_DIG_ANA_MPHY_OVRD_OUT 2 0x11bf 9 0 4294967295 RX_ANA_SQ_CTRL_TRESH 0 2 RX_ANA_SQ_CTRL_TRESH_OVRD_EN 3 3 RX_ANA_SQ_CTRL_RESP 4 5 RX_ANA_SQ_CTRL_RESP_OVRD_EN 6 6 RX_ANA_PWM_EN 7 7 RX_ANA_PWM_EN_OVRD_EN 8 8 RX_ANA_PWM_CLK_SEL 9 10 RX_ANA_PWM_CLK_SEL_OVRD_EN 11 11 RESERVED_15_12 12 15 ixDPCSSYS_CR1_LANE1_DIG_ANA_SIGDET_OVRD_OUT_1 2 0x11c0 7 0 4294967295 RX_ANA_SIGDET_HF_THRESH 0 2 RX_ANA_SIGDET_HF_THRESH_OVRD_EN 3 3 RX_ANA_SIGDET_HF_CAL_TUNE 4 9 RX_ANA_SIGDET_CAL_TUNE_OVRD_EN 10 10 RX_ANA_SIGDET_CAL_EN 11 11 RX_ANA_SIGDET_CAL_EN_OVRD_EN 12 12 RESERVED_15_13 13 15 ixDPCSSYS_CR1_LANE1_DIG_ANA_SIGDET_OVRD_OUT_2 2 0x11c1 7 0 4294967295 RX_ANA_SIGDET_LF_THRESH 0 2 RX_ANA_SIGDET_LF_THRESH_OVRD_EN 3 3 RX_ANA_SIGDET_LF_FILTER_EN 4 4 RX_ANA_SIGDET_LF_FILTER_EN_OVRD_EN 5 5 RX_ANA_SIGDET_CAL_TUNE 6 11 RX_ANA_SIGDET_CAL_TUNE_OVRD_EN 12 12 RESERVED_15_13 13 15 ixDPCSSYS_CR1_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT 2 0x11c2 8 0 4294967295 TX_ANA_DCC_CAL_RANGE 0 1 TX_ANA_DCC_CAL_RANGE_OVRD_EN 2 2 TX_ANA_DCC_CAL_COMP_EN 3 3 TX_ANA_DCC_CAL_COMP_EN_OVRD_EN 4 4 TX_ANA_DCC_CAL_CTRL 5 12 TX_ANA_DCC_CAL_CTRL_OVRD_EN 13 13 TX_ANA_DCC_CAL_CTRL_EN 14 14 TX_ANA_DCC_CAL_CTRL_EN_OVRD_EN 15 15 ixDPCSSYS_CR1_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2 2 0x11c3 5 0 4294967295 TX_ANA_DCC_CAL_CTRL_SEL 0 2 TX_ANA_DCC_CAL_CTRL_SEL_OVRD_EN 3 3 TX_ANA_DCC_CLK_COMP 4 4 TX_ANA_DCC_CLK_COMP_OVRD_EN 5 5 RESERVED_15_6 6 15 ixDPCSSYS_CR1_LANE1_DIG_ANA_TX_OVRD_OUT_2 2 0x11c4 6 0 4294967295 TX_ANA_FAST_START 0 0 TX_ANA_FAST_START_OVRD_EN 1 1 TX_CLK_LB_EN 2 2 TX_CLK_LB_EN_OVRD_EN 3 3 TX_ACJTAG_EN 4 4 RESERVED_15_5 5 15 ixDPCSSYS_CR1_LANE1_ANA_TX_OVRD_MEAS 2 0x11e0 9 0 4294967295 OVRD_CLK_SHIFT 0 0 CLK_SHIFT_REG 0 0 MEAS_ATB_CAL_MUX 0 0 MEAS_ATB_CAL_COMP 0 0 OVRD_VCM_HOLD 0 0 VCM_HOLD_REG 0 0 PULL_UP_REG 0 0 PULL_DN_REG 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR1_LANE1_ANA_TX_PWR_OVRD 2 0x11e1 9 0 4294967295 OVRD_TX_LOOPBACK 0 0 LOOPBACK_EN_REG 0 0 REFGEN_EN_REG 0 0 CLK_DIV_EN_REG 0 0 DATA_EN_REG_INT 0 0 CLK_EN_REG 0 0 SERIAL_EN_REG 0 0 OVRD_EN 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR1_LANE1_ANA_TX_ALT_BUS 2 0x11e2 6 0 4294967295 DRV_SOURCE_REG 0 0 OVRD_ALT_BUS 0 0 ATB_S_ENABLE 0 0 TX_ALT_RINGO 0 0 JTAG_DATA_REG 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR1_LANE1_ANA_TX_ATB1 2 0x11e3 9 0 4294967295 MEAS_ATB_GD 0 0 MEAS_ATB_VDDH 0 0 OVERRIDE_RXDETREF 0 0 MEAS_ATB_VPTX 0 0 OVERRIDE_REGREF 0 0 MEAS_ATB_VREG_DRV 0 0 MEAS_ATB_VREG 0 0 MEAS_ATB_VPH_HALF 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR1_LANE1_ANA_TX_ATB2 2 0x11e4 9 0 4294967295 MEAS_ATB_VCM 0 0 MEAS_ATB_CAL_VDAC_CM 0 0 MEAS_ATB_CAL_VDAC_DIFF 0 0 MEAS_ATB_TXM 0 0 MEAS_ATB_TXP 0 0 MEAS_ATB_RXDETREF 0 0 LFPS_HIGH_PRIORITY 0 0 OSC_DIV4_EN 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR1_LANE1_ANA_TX_DCC_DAC 2 0x11e5 2 0 4294967295 DCC_DAC_REG 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR1_LANE1_ANA_TX_DCC_CTRL1 2 0x11e6 7 0 4294967295 NC0 0 0 OVRD_DCC_DAC_CTRL_SEL 0 0 DCC_DAC_CTRL_SEL_REG 0 0 OVRD_DCC_DAC_CTRL_EN 0 0 DCC_DAC_CTRL_EN_REG 0 0 OVRD_DCC_DAC_REG 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR1_LANE1_ANA_TX_TERM_CODE 2 0x11e7 2 0 4294967295 TERM_CODE_REG_70 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR1_LANE1_ANA_TX_TERM_CODE_CTRL 2 0x11e8 8 0 4294967295 VREG_BOOST_1 0 0 OVRD_UPDATE_TERM 0 0 UPDATE_TERM_REG 0 0 OVRD_RESET_TERM 0 0 RESET_TERM_REG 0 0 OVRD_TERM_CODE 0 0 TERM_CODE_REG_98 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR1_LANE1_ANA_TX_OVRD_CLK 2 0x11e9 9 0 4294967295 VREG_BOOST_0 0 0 CLK_LB_EN_REG 0 0 OVRD_LB_EN 0 0 MPLLB_CLK_EN_REG 0 0 MPLLA_CLK_EN_REG 0 0 OVRD_MPLLAB_EN 0 0 WORD_CLK_EN_REG 0 0 OVRD_WORD_CLK_EN 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR1_LANE1_ANA_TX_MISC1 2 0x11ea 8 0 4294967295 MEAS_ATB_CAL_CLK_ALIGN 0 0 OVRD_DCC_DAC_CTRL_RANGE 0 0 DCC_DAC_CTRL_RANGE_REG 0 0 OVRD_VREF_SEL 0 0 VREF_SEL_REG 0 0 FORCE_ATB_TXM 0 0 FORCE_ATB_TXP 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR1_LANE1_ANA_TX_MISC2 2 0x11eb 8 0 4294967295 TX_PEAKING_LVL 0 0 VREG_CP_GAIN_CTRL 0 0 TX_SLEW_EN 0 0 EN_INV_POST 0 0 EN_INV_PRE 0 0 TX_VREG_EN_BYP 0 0 TX_VDRIVER_PULLDN_EN 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR1_LANE1_ANA_TX_MISC3 2 0x11ec 4 0 4294967295 TX_VREG_OVRD_RING_CTRL 0 0 TX_DCC_LOWV 0 0 NC7_2 2 7 RESERVED_15_8 8 15 ixDPCSSYS_CR1_LANE1_ANA_TX_RESERVED2 2 0x11ed 2 0 4294967295 NC7_0 0 7 RESERVED_15_8 8 15 ixDPCSSYS_CR1_LANE1_ANA_TX_RESERVED3 2 0x11ee 2 0 4294967295 NC7_0 0 7 RESERVED_15_8 8 15 ixDPCSSYS_CR1_LANE1_ANA_TX_RESERVED4 2 0x11ef 2 0 4294967295 NC7_0 0 7 RESERVED_15_8 8 15 ixDPCSSYS_CR1_LANE1_ANA_RX_CLK_1 2 0x11f0 8 0 4294967295 CDR_VCO_STARTUP_CODE 0 0 CDR_VCO_TEMP_COMP_EN 0 0 CDR_VCO_USE_UNCAL_BIAS 0 0 OVERRIDE_CDR_EN 0 0 OVRD_CLK_EN 0 0 CLK_EN_REG 0 0 NC7 7 7 RESERVED_15_8 8 15 ixDPCSSYS_CR1_LANE1_ANA_RX_CLK_2 2 0x11f1 5 0 4294967295 IQ_PHASE_ADJUST_REG 0 0 OVRD_IQ_PHASE_ADJUST 0 0 RX_LOOPBACK_CLK_REG 0 0 OVRD_RX_LOOPBACK_CLK 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR1_LANE1_ANA_RX_CDR_DES 2 0x11f2 7 0 4294967295 OVRD_WORD_CLK_EN 0 0 WORD_CLK_EN_REG 0 0 PHDET_ODD_REG 0 0 PHDET_EVEN_REG 0 0 SIGDET_VREF_EXT_EN 0 0 NC7_5 5 7 RESERVED_15_8 8 15 ixDPCSSYS_CR1_LANE1_ANA_RX_SLC_CTRL 2 0x11f3 3 0 4294967295 RX_SLICER_CTRL_O_REG 0 0 RX_SLICER_CTRL_E_REG 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR1_LANE1_ANA_RX_PWR_CTRL1 2 0x11f4 8 0 4294967295 OVRD_ACJT_EN 0 0 ACJT_EN_REG 0 0 OVRD_AFE_EN 0 0 AFE_EN_REG 0 0 AFE_CM_SEL 0 0 ATT_PULLDN_EN 0 0 NC7_7 7 7 RESERVED_15_8 8 15 ixDPCSSYS_CR1_LANE1_ANA_RX_PWR_CTRL2 2 0x11f5 9 0 4294967295 OVRD_DFE_EN 0 0 DFE_EN_REG 0 0 OVRD_DESERIAL_EN 0 0 DESERIAL_EN_REG 0 0 OVRD_LOOPBACK_EN 0 0 LOOPBACK_EN_REG 0 0 OVRD_FAST_START 0 0 FAST_START_REG 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR1_LANE1_ANA_RX_SQ 2 0x11f6 7 0 4294967295 SQ_CTRL_RESP_REG 0 0 OVRD_SQ_CTRL_RESP 0 0 NC4_3 3 4 SQ_CTRL_TRESH_REG 0 0 OVRD_SQ_CTRL_TRESH 0 0 AFE_LOOPBACK_SEL 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR1_LANE1_ANA_RX_CAL1 2 0x11f7 5 0 4294967295 DFE_TAPS_EN_REG 0 0 OVRD_DFE_TAPS_EN 0 0 CAL_MUXB_SEL_REG 0 0 OVRD_CAL_MUXB_SEL 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR1_LANE1_ANA_RX_CAL2 2 0x11f8 5 0 4294967295 AFE_PD_EQ_OFFSET 0 0 CAL_IDACS_USE_UNCAL 0 0 CAL_MUXA_SEL_REG 0 0 OVRD_CAL_MUXA_SEL 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR1_LANE1_ANA_RX_ATB_REGREF 2 0x11f9 8 0 4294967295 OVERRIDE_REGREF_VCO 0 0 OVERRIDE_REGREF_CLK 0 0 OVERRIDE_REGREF_IQC 0 0 BOOST_REGREF_IQC 0 0 OVRD_RX_SLICER_CTRL 0 0 OVRD_RX_TERM_AC_DCZ 0 0 RX_TERM_AC_DCZ_REG 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR1_LANE1_ANA_RX_ATB_MEAS1 2 0x11fa 9 0 4294967295 MASTER_ATB_EN 0 0 MEAS_ATB_VP 0 0 MEAS_ATB_GD 0 0 MEAS_ATB_VREG_VCO 0 0 MEAS_ATB_VREG_CLK 0 0 MEAS_ATB_VREG_IQC 0 0 REGS_FB_DIV_CTRL 0 0 RX_VREG_CLK_BYPASS 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR1_LANE1_ANA_RX_ATB_MEAS2 2 0x11fb 2 0 4294967295 MEAS_ATB_RX 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR1_LANE1_ANA_RX_ATB_MEAS3 2 0x11fc 7 0 4294967295 MEAS_ATB_CDR_VCO_GD 0 0 MEAS_ATB_CDR_VCO_VIREF_200U 0 0 MEAS_ATB_VIBIAS_CDR_VCO 0 0 MEAS_ATB_CDR_VCO_VOSC 0 0 MEAS_ATB_CAL_MUX 0 0 RX_VREG_OVERRIDE_RING_CTRL 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR1_LANE1_ANA_RX_ATB_MEAS4 2 0x11fd 3 0 4294967295 MEAS_ATB_CAL_VREF 0 0 NC7 7 7 RESERVED_15_8 8 15 ixDPCSSYS_CR1_LANE1_ANA_RX_ATB_FRC 2 0x11fe 2 0 4294967295 FRC_ATB_CAL_VREF 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR1_LANE1_ANA_RX_RESERVED1 2 0x11ff 2 0 4294967295 NC7_0 0 7 RESERVED_15_8 8 15 ixDPCSSYS_CR1_LANE2_DIG_ASIC_LANE_OVRD_IN 2 0x1200 5 0 4294967295 LANE_TX2RX_SER_LB 0 0 LANE_RX2TX_PAR_LB 1 1 EN 2 2 RX_ACJTAG_EN 3 3 RESERVED_15_4 4 15 ixDPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_0 2 0x1201 12 0 4294967295 REQ 0 0 REQ_OVRD_EN 1 1 PSTATE 2 3 PSTATE_OVRD_EN 4 4 RATE 5 7 RATE_OVRD_EN 8 8 WIDTH 9 10 WIDTH_OVRD_EN 11 11 MPLLB_SEL 12 12 MPLLB_SEL_OVRD_EN 13 13 DATA_EN 14 14 DATA_EN_OVRD_EN 15 15 ixDPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_1 2 0x1202 11 0 4294967295 NYQUIST_DATA 0 0 DISABLE 1 1 BEACON_EN 2 2 EN 3 3 TX_MAIN_CURSOR 4 9 MAIN_OVRD_EN 10 10 ASYNC_DRV_EN 11 11 ASYNC_DRV_OVRD_EN 12 12 TX_VREGDRV_BYP_OVRD 13 13 TX_VREGDRV_BYP_OVRD_EN 14 14 RESERVED_15_15 15 15 ixDPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_2 2 0x1203 6 0 4294967295 TX_PRE_CURSOR 0 5 PRE_OVRD_EN 6 6 TX_POST_CURSOR 7 12 POST_OVRD_EN 13 13 HDMIMODE_EN 14 14 HDMIMODE_ENABLE_OVRD_EN 15 15 ixDPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_3 2 0x1204 15 0 4294967295 CLK_RDY 0 0 CLK_RDY_OVRD_EN 1 1 DETECT_RX_REQ 2 2 DETECT_RX_REQ_OVRD_EN 3 3 INVERT 4 4 INVERT_OVRD_EN 5 5 LPD 6 6 LPD_OVRD_EN 7 7 TX_DC_COUP_EN 8 8 TX_DC_COUP_EN_OVRD_EN 9 9 PMA_EXTENDED_FIFO_EN 10 10 PMA_EXTENDED_FIFO_EN_OVRD_EN 11 11 TX_MPHY_MODE_EN 12 12 TX_MPHY_MODE_EN_OVRD_EN 13 13 RESERVED_15_14 14 15 ixDPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_4 2 0x1205 3 0 4294967295 RESET 0 0 RESET_OVRD_EN 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_OUT 2 0x1206 5 0 4294967295 TX_ACK 0 0 EN_TX_ACK 1 1 DETRX_RESULT 2 2 EN_DETRX_RESULT 3 3 RESERVED_15_4 4 15 ixDPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_0 2 0x1207 11 0 4294967295 REQ 0 0 REQ_OVRD_EN 1 1 DATA_EN 2 2 DATA_EN_OVRD_EN 3 3 PSTATE 4 5 PSTATE_OVRD_EN 6 6 RATE 7 8 RATE_OVRD_EN 9 9 WIDTH 10 11 WIDTH_OVRD_EN 12 12 RESERVED_15_13 13 15 ixDPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_1 2 0x1208 5 0 4294967295 RX_REF_LD_VAL_5_0 0 5 RX_CDR_VCO_LOWFREQ 6 6 EN 7 7 RX_REF_LD_VAL_6 8 8 RESERVED_15_9 9 15 ixDPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_2 2 0x1209 3 0 4294967295 RX_VCO_LD_VAL 0 12 EN 13 13 RESERVED_15_14 14 15 ixDPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_3 2 0x120a 11 0 4294967295 CDR_TRACK_EN 0 0 CDR_TRACK_EN_OVRD_EN 1 1 CDR_SSC_EN 2 2 CDR_SSC_EN_OVRD_EN 3 3 ALIGN_EN 4 4 ALIGN_EN_OVRD_EN 5 5 CLK_SHIFT 6 6 CLK_SHIFT_OVRD_EN 7 7 DISABLE 8 8 DISABLE_OVRD_EN 9 9 RESERVED_15_10 10 15 ixDPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_4 2 0x120b 11 0 4294967295 LPD 0 0 LPD_OVRD_EN 1 1 INVERT 2 2 INVERT_OVRD_EN 3 3 ADAPT_AFE_EN 4 4 ADAPT_DFE_EN 5 5 ADPT_OVRD_EN 6 6 TERM_EN 7 7 TERM_ACDC 8 8 TERM_OVRD_EN 9 9 RESERVED_15_10 10 15 ixDPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_5 2 0x120c 3 0 4294967295 RESET 0 0 RESET_OVRD_EN 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0 2 0x120d 4 0 4294967295 EQ_ATT_LVL 0 2 EQ_AFE_GAIN 3 6 RESERVED 7 10 EQ_CTLE_BOOST 11 15 ixDPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1 2 0x120e 3 0 4294967295 EQ_DFE_TAP2 0 6 EQ_DFE_TAP1 7 14 EQ_OVRD_EN 15 15 ixDPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_OUT_0 2 0x120f 9 0 4294967295 ACK 0 0 ACK_OVRD_EN 1 1 ADAPT_STS 2 3 ADAPT_STS_OVRD_EN 4 4 RX_ASYNC_DATA 5 5 RX_ASYNC_DATA_OVRD_EN 6 6 RX_SQ_WEAKKEEP_OUT 7 7 RX_SQ_WEAKKEEP_OUT_OVRD_EN 8 8 RESERVED_15_9 9 15 ixDPCSSYS_CR1_LANE2_DIG_ASIC_LANE_ASIC_IN 2 0x1210 3 0 4294967295 LANE_TX2RX_SER_LB 0 0 LANE_RX2TX_PAR_LB 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR1_LANE2_DIG_ASIC_TX_ASIC_IN_0 2 0x1211 12 0 4294967295 CLK_RDY 0 0 RESET 1 1 INVERT 2 2 DATA_EN 3 3 REQ 4 4 LPD 5 5 PSTATE 6 7 RATE 8 10 WIDTH 11 12 MPLLB_SEL 13 13 DETECT_RX_REQ 14 14 DISABLE 15 15 ixDPCSSYS_CR1_LANE2_DIG_ASIC_TX_ASIC_IN_1 2 0x1212 7 0 4294967295 BEACON_EN 0 0 TX_MAIN_CURSOR 1 6 TX_ASYNC_EN 7 7 TX_ASYNC_DATA 8 8 TX_ASYNC_DRV_EN 9 9 TX_VREGDRV_BYP 10 10 RESERVED_15_11 11 15 ixDPCSSYS_CR1_LANE2_DIG_ASIC_TX_ASIC_IN_2 2 0x1213 3 0 4294967295 TX_PRE_CURSOR 0 5 TX_POST_CURSOR 6 11 RESERVED_15_12 12 15 ixDPCSSYS_CR1_LANE2_DIG_ASIC_TX_ASIC_OUT 2 0x1214 3 0 4294967295 TX_ACK 0 0 DETRX_RESULT 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR1_LANE2_DIG_ASIC_RX_ASIC_IN_0 2 0x1215 13 0 4294967295 RESET 0 0 INVERT 1 1 DATA_EN 2 2 REQ 3 3 LPD 4 4 PSTATE 5 6 RATE 7 8 WIDTH 9 10 RESERVED 11 11 ADAPT_AFE_EN 12 12 ADAPT_DFE_EN 13 13 CDR_TRACK_EN 14 14 RESERVED_15_15 15 15 ixDPCSSYS_CR1_LANE2_DIG_ASIC_RX_ASIC_IN_1 2 0x1216 7 0 4294967295 CDR_SSC_EN 0 0 ALIGN_EN 1 1 CLK_SHIFT 2 2 DISABLE 3 3 RX_TERM_EN 4 4 RX_TERM_ACDC 5 5 RESERVED_15_6 6 15 ixDPCSSYS_CR1_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0 2 0x1217 4 0 4294967295 EQ_ATT_LVL 0 2 EQ_AFE_GAIN 3 6 RESERVED 7 10 EQ_CTLE_BOOST 11 15 ixDPCSSYS_CR1_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_1 2 0x1218 3 0 4294967295 EQ_DFE_TAP2 0 6 EQ_DFE_TAP1 7 14 RESERVED_15_15 15 15 ixDPCSSYS_CR1_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0 2 0x1219 3 0 4294967295 RX_CDR_VCO_LOWFREQ 0 0 RX_REF_LD_VAL 1 7 RESERVED_15_8 8 15 ixDPCSSYS_CR1_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1 2 0x121a 2 0 4294967295 RX_VCO_LD_VAL 0 12 RESERVED_15_13 13 15 ixDPCSSYS_CR1_LANE2_DIG_ASIC_RX_ASIC_OUT_0 2 0x121b 4 0 4294967295 ACK 0 0 VALID 1 1 ADAPT_STS 2 3 RESERVED_15_4 4 15 ixDPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_6 2 0x121c 10 0 4294967295 RX_PWM_CLK_SEL 0 1 RX_PWM_CLK_SEL_OVRD_EN 2 2 RX_TERM_LCC_ON 3 3 RX_TERM_LS_ON 4 4 RX_TERM_LS_LCC_ON_OVRD_EN 5 5 RX_TERM_CTL 6 7 RX_TERM_CTL_OVRD_EN 8 8 RX_PWM_EN 9 9 RX_PWM_EN_OVRD_EN 10 10 RESERVED_15_11 11 15 ixDPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_5 2 0x121d 15 0 4294967295 RPTR_EN_MASTER_LANE 0 0 RPTR_EN_MASTER_LANE_OVRD_EN 1 1 DIG_CLK_EN_OTHER_LANE 2 2 DIG_CLK_EN_OTHER_LANE_OVRD_EN 3 3 DIG_CLK_STATE_MASTER_LANE 4 4 DIG_CLK_STATE_MASTER_LANE_OVRD_EN 5 5 SHIFT_MASTER_LANE 6 6 SHIFT_MASTER_LANE_ORVD_EN 7 7 SHIFT_ACK_OTHER_LANE 8 8 SHIFT_ACK_OTHER_LANE_OVRD_EN 9 9 LANE_MASTER 10 10 LANE_MASTER_OVRD_IN_EN 11 11 TX_DWORD_CLK_SYNC_OVRD 12 12 TX_DWORD_CLK_SYNC_OVRD_EN 13 13 RESERVED_15_14 14 15 ixDPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_OUT_1 2 0x121e 11 0 4294967295 RPTR_EN_OUT 0 0 RPTR_EN_OUT_OVRD_EN 1 1 DIG_CLK_EN_OUT 2 2 DIG_CLK_EN_OUT_OVRD_EN 3 3 DIG_CLK_STATE_OUT 4 4 DIG_CLK_STATE_OUT_OVRD_EN 5 5 SHIFT_OUT 6 6 SHIFT_OUT_OVRD_EN 7 7 SHIFT_ACK_OUT 8 8 SHIFT_ACK_OUT_OVRD_EN 9 9 RESERVED_15_10 10 15 ixDPCSSYS_CR1_LANE2_DIG_ASIC_OCLA 2 0x121f 3 0 4294967295 RX_DWORD_OCLA_CLK_EN 0 0 RX_DWORD_OCLA_DATA_EN 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0 2 0x1220 11 0 4294967295 TX_P0_ANA_REFGEN_EN 0 0 TX_P0_ANA_VCM_HOLD 1 1 TX_P0_ANA_CLK_EN 2 2 TX_P0_ANA_WORD_CLK_EN 3 3 TX_P0_ANA_RESET 4 4 TX_P0_ANA_SERIAL_EN 5 5 TX_P0_DIG_CLK_EN 6 6 TX_P0_DATA_EN 7 7 TX_P0_ALLOW_RXDET 8 8 TX_P0_ANA_DCC_COMP_CAL_EN 9 9 RESERVED_15_10 10 15 ixDPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S 2 0x1221 11 0 4294967295 TX_P0S_ANA_REFGEN_EN 0 0 TX_P0S_ANA_VCM_HOLD 1 1 TX_P0S_ANA_CLK_EN 2 2 TX_P0S_ANA_WORD_CLK_EN 3 3 TX_P0S_ANA_RESET 4 4 TX_P0S_ANA_SERIAL_EN 5 5 TX_P0S_DIG_CLK_EN 6 6 TX_P0S_DATA_EN 7 7 TX_P0S_ALLOW_RXDET 8 8 TX_P0S_ANA_DCC_COMP_CAL_EN 9 9 RESERVED_15_10 10 15 ixDPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1 2 0x1222 11 0 4294967295 TX_P1_ANA_REFGEN_EN 0 0 TX_P1_ANA_VCM_HOLD 1 1 TX_P1_ANA_CLK_EN 2 2 TX_P1_ANA_WORD_CLK_EN 3 3 TX_P1_ANA_RESET 4 4 TX_P1_ANA_SERIAL_EN 5 5 TX_P1_DIG_CLK_EN 6 6 TX_P1_DATA_EN 7 7 TX_P1_ALLOW_RXDET 8 8 TX_P1_ANA_DCC_COMP_CAL_EN 9 9 RESERVED_15_10 10 15 ixDPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2 2 0x1223 12 0 4294967295 TX_P2_ANA_REFGEN_EN 0 0 TX_P2_ANA_VCM_HOLD 1 1 TX_P2_ANA_CLK_EN 2 2 TX_P2_ANA_WORD_CLK_EN 3 3 TX_P2_ANA_RESET 4 4 TX_P2_ANA_SERIAL_EN 5 5 TX_P2_DIG_CLK_EN 6 6 TX_P2_DATA_EN 7 7 TX_P2_ALLOW_RXDET 8 8 TX_P2_ALLOW_VBOOST 9 9 TX_P2_ANA_DCC_COMP_CAL_EN 10 10 RESERVED_15_11 11 15 ixDPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_0 2 0x1224 2 0 4294967295 TX_REFGEN_EN_TIME 0 7 TX_CLK_EN 8 15 ixDPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_1 2 0x1225 2 0 4294967295 TX_VCM_HOLD_TIME_14_0 0 14 SKIP_TX_VCM_HOLD_WAIT 15 15 ixDPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_2 2 0x1226 2 0 4294967295 TX_VBOOST_DIS_TIME_12_0 0 12 DTB_SEL 13 15 ixDPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_3 2 0x1227 3 0 4294967295 TX_VCM_HOLD_TIME_17_15 0 2 TX_VBOOST_DIS_TIME_13 3 3 RESERVED_15_4 4 15 ixDPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_4 2 0x1228 2 0 4294967295 TX_VCM_HOLD_GS_TIME 0 14 SKIP_TX_VCM_HOLD_GS_PULSE 15 15 ixDPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_5 2 0x1229 5 0 4294967295 TX_RXDET_TIME 0 9 FAST_TX_RXDET 10 10 TX_RESET_TIME 11 12 TX_SERIAL_EN_TIME 13 14 RESERVED_15_15 15 15 ixDPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_DCC_CR_BANK_ADDR 2 0x122a 1 0 4294967295 ADDR 0 15 ixDPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_DCC_CR_BANK_DATA 2 0x122b 1 0 4294967295 DATA 0 15 ixDPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_DCC_DAC_CTRL 2 0x122c 2 0 4294967295 CTRL 0 7 RESERVED_15_8 8 15 ixDPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_DCC_DAC_RANGE 2 0x122d 2 0 4294967295 CTRL 0 1 RESERVED_15_2 2 15 ixDPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_DCC_DAC_SEL 2 0x122e 6 0 4294967295 SEL 0 2 REQ 3 3 CTRL_UPD 4 4 RANGE_UPD 5 5 BIN_HOT 6 6 RESERVED_15_7 7 15 ixDPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_DCC_DAC_ACK 2 0x122f 2 0 4294967295 ACK 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_DCC_DAC_ADDR 2 0x1230 1 0 4294967295 ADDR 0 15 ixDPCSSYS_CR1_LANE2_DIG_TX_CLK_ALIGN_TX_CTL_0 2 0x1231 4 0 4294967295 TX_NUM_2UI_SHIFTS_16B_MODE 0 3 TX_NUM_2UI_SHIFTS_20B_MODE 4 7 TX_FIFO_BYPASS 8 8 RESERVED_15_9 9 15 ixDPCSSYS_CR1_LANE2_DIG_TX_LBERT_CTL 2 0x1232 4 0 4294967295 MODE 0 3 TRIGGER_ERR 4 4 PAT0 5 14 RESERVED_15_15 15 15 ixDPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0 2 0x1240 12 0 4294967295 RX_P0_ANA_AFE_EN 0 0 RX_P0_ANA_CLK_VREG_EN 1 1 RESERVED_1 2 2 RX_P0_ANA_CLK_EN 3 3 RESERVED_0 4 4 RX_P0_ANA_DESER_EN 5 5 RX_P0_ANA_CDR_EN 6 6 RX_P0_VCO_FREQ_RST 7 7 RX_P0_VCO_CAL_RST 8 8 RX_P0_VCO_CONTCAL_EN 9 9 RX_P0_DIG_CLK_EN 10 10 RESERVED_15_11 11 15 ixDPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S 2 0x1241 12 0 4294967295 RX_P0S_ANA_AFE_EN 0 0 RX_P0S_ANA_CLK_VREG_EN 1 1 RESERVED_2 2 2 RX_P0S_ANA_CLK_EN 3 3 RESERVED_4 4 4 RX_P0S_ANA_DESER_EN 5 5 RX_P0S_ANA_CDR_EN 6 6 RX_P0S_VCO_FREQ_RST 7 7 RX_P0S_VCO_CAL_RST 8 8 RX_P0S_VCO_CONTCAL_EN 9 9 RX_P0S_DIG_CLK_EN 10 10 RESERVED_15_11 11 15 ixDPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1 2 0x1242 12 0 4294967295 RX_P1_ANA_AFE_EN 0 0 RX_P1_ANA_CLK_VREG_EN 1 1 RESERVED_2 2 2 RX_P1_ANA_CLK_EN 3 3 RESERVED_4 4 4 RX_P1_ANA_DESER_EN 5 5 RX_P1_ANA_CDR_EN 6 6 RX_P1_VCO_FREQ_RST 7 7 RX_P1_VCO_CAL_RST 8 8 RX_P1_VCO_CONTCAL_EN 9 9 RX_P1_DIG_CLK_EN 10 10 RESERVED_15_11 11 15 ixDPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2 2 0x1243 12 0 4294967295 RX_P2_ANA_AFE_EN 0 0 RX_P2_ANA_CLK_VREG_EN 1 1 RESERVED_2 2 2 RX_P2_ANA_CLK_EN 3 3 RESERVED_4 4 4 RX_P2_ANA_DESER_EN 5 5 RX_P2_ANA_CDR_EN 6 6 RX_P2_VCO_FREQ_RST 7 7 RX_P2_VCO_CAL_RST 8 8 RX_P2_VCO_CONTCAL_EN 9 9 RX_P2_DIG_CLK_EN 10 10 RESERVED_15_11 11 15 ixDPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1 2 0x1245 5 0 4294967295 RX_AFE_EN_TIME 0 5 FAST_RX_AFE_EN 6 6 RX_VREG_EN_TIME 7 12 FAST_RX_VREG_EN 13 13 RESERVED_15_14 14 15 ixDPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_2 2 0x1246 4 0 4294967295 RX_CLK_EN_TIME 0 5 FAST_RX_CLK_EN 6 6 RX_FAST_START_TIME 7 10 RESERVED_15_11 11 15 ixDPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_3 2 0x1247 5 0 4294967295 RX_RATE_TIME 0 1 RSVD_3_7_2 2 7 RX_CDR_EN_TIME 8 11 RX_DESER_EN_TIME 12 13 RX_DESER_DIS_TIME 14 15 ixDPCSSYS_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0 2 0x1248 8 0 4294967295 INT_GAIN_CAL_FIXED_CNT 0 4 INT_GAIN_CAL_FIXED_CNT_EN 5 5 INT_GAIN_CAL_CNT_SHIFT 6 8 INT_GAIN_CAL_BOUNCE_CNT 9 11 DISABLE_BIN_HOLD 12 12 DISABLE_INT_GAIN_HOLD 13 13 DISABLE_COARSE_CALDONE 14 14 RESERVED_15_15 15 15 ixDPCSSYS_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1 2 0x1249 7 0 4294967295 RX_VCO_OVRD_SEL 0 0 RX_VCO_FREQ_RST 1 1 RX_VCO_CAL_RST 2 2 RX_VCO_CONTCAL_EN 3 3 DISABLE_INT_CAL_MODE 4 4 DPLL_CAL_UG 5 8 DTB_SEL 9 15 ixDPCSSYS_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2 2 0x124a 4 0 4294967295 FREQ_TUNE_START_VAL 0 9 FREQ_TUNE_CAL_STEPS 10 13 SKIP_RX_VCO_FREQ_TUNE_CAL 14 14 SKIP_RX_VCO_CAL 15 15 ixDPCSSYS_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0 2 0x124b 4 0 4294967295 RX_VCO_STARTUP_TIME 0 6 RX_VCO_UPDATE_TIME 7 10 RX_VCO_CNTR_PWRUP_TIME 11 14 FAST_RX_VCO_WAIT 15 15 ixDPCSSYS_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1 2 0x124c 2 0 4294967295 RX_VCO_CNTR_SETTLE_TIME 0 2 RESERVED_15_3 3 15 ixDPCSSYS_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0 2 0x124d 6 0 4294967295 RX_ANA_CDR_FREQ_TUNE 0 9 RX_ANA_VCO_CNTR_PD 10 10 RX_ANA_VCO_CNTR_EN 11 11 RX_ANA_CDR_STARTUP 12 12 RX_ANA_CDR_VCO_EN 13 13 RESERVED_15_14 14 15 ixDPCSSYS_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1 2 0x124e 7 0 4294967295 RX_VCO_FSM_STATE 0 3 RX_VCO_FREQ_RST 4 4 RX_VCO_CAL_RST 5 5 RX_VCO_CONTCAL_EN 6 6 RX_VCO_CAL_DONE 7 7 DPLL_FREQ_RST 8 8 RESERVED_15_9 9 15 ixDPCSSYS_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_2 2 0x124f 4 0 4294967295 VCO_CNTR_FINAL 0 12 VCOCLK_TOO_FAST 13 13 RX_VCO_CORRECT 14 14 RX_VCO_UP 15 15 ixDPCSSYS_CR1_LANE2_DIG_RX_RX_ALIGN_XAUI_COMM_MASK 2 0x1250 2 0 4294967295 XAUI_COMM_MASK 0 9 RESERVED_15_10 10 15 ixDPCSSYS_CR1_LANE2_DIG_RX_LBERT_CTL 2 0x1251 3 0 4294967295 MODE 0 3 SYNC 4 4 RESERVED_15_5 5 15 ixDPCSSYS_CR1_LANE2_DIG_RX_LBERT_ERR 2 0x1252 2 0 4294967295 COUNT 0 14 OV14 15 15 ixDPCSSYS_CR1_LANE2_DIG_RX_CDR_CDR_CTL_0 2 0x1253 7 0 4294967295 PHDET_EN 0 1 PHDET_EDGE 2 3 PHDET_POL 4 4 PHDET_EN_PR_MODE 5 5 ALWAYS_REALIGN 6 6 DTB_SEL 7 10 RESERVED_15_11 11 15 ixDPCSSYS_CR1_LANE2_DIG_RX_CDR_CDR_CTL_1 2 0x1254 2 0 4294967295 SSC_OFF_CNT0 0 9 SSC_OFF_CNT1 10 15 ixDPCSSYS_CR1_LANE2_DIG_RX_CDR_CDR_CTL_2 2 0x1255 2 0 4294967295 SSC_ON_CNT0 0 8 SSC_ON_CNT1 9 15 ixDPCSSYS_CR1_LANE2_DIG_RX_CDR_CDR_CTL_3 2 0x1256 6 0 4294967295 SSC_OFF_PHUG0 0 2 SSC_OFF_PHUG1 3 5 SSC_OFF_FRUG0 6 8 OVRD_DPLL_GAIN 9 9 PHUG_OVRD_VALUE 10 12 FRUG_OVRD_VALUE 13 15 ixDPCSSYS_CR1_LANE2_DIG_RX_CDR_CDR_CTL_4 2 0x1257 6 0 4294967295 SSC_OFF_FRUG1 0 2 SSC_ON_FRUG0 3 5 SSC_ON_FRUG1 6 8 SSC_ON_PHUG0 9 11 SSC_ON_PHUG1 12 14 RESERVED_15_15 15 15 ixDPCSSYS_CR1_LANE2_DIG_RX_CDR_STAT 2 0x1258 3 0 4294967295 PHUG_VALUE 0 2 FRUG_VALUE 3 5 RESERVED_15_6 6 15 ixDPCSSYS_CR1_LANE2_DIG_RX_DPLL_FREQ 2 0x1259 2 0 4294967295 VAL 0 13 RESERVED_15_14 14 15 ixDPCSSYS_CR1_LANE2_DIG_RX_DPLL_FREQ_BOUND_0 2 0x125a 3 0 4294967295 FREQ_BOUND_EN 0 0 UPPER_FREQ_BOUND 1 10 RESERVED_15_11 11 15 ixDPCSSYS_CR1_LANE2_DIG_RX_DPLL_FREQ_BOUND_1 2 0x125b 2 0 4294967295 LOWER_FREQ_BOUND 0 9 RESERVED_15_10 10 15 ixDPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_0 2 0x1260 4 0 4294967295 N_TOP_ASM1 0 9 N_TGG_ASM1 10 13 START_ASM1 14 14 ADPT_CLK_DIV4_EN 15 15 ixDPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1 2 0x1261 5 0 4294967295 N_WAIT_ASM1 0 6 FAST_AFE_DFE_SETTLE 7 7 CTLE_POLE_OVRD_VAL 8 10 CTLE_POLE_OVRD_EN 11 11 RESERVED_15_12 12 15 ixDPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_2 2 0x1262 3 0 4294967295 TGG_PTTRN_0 0 4 TGG_PTTRN_1 5 9 RESERVED_15_10 10 15 ixDPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3 2 0x1263 8 0 4294967295 CTLE_EN 0 4 VGA_EN 5 5 ATT_EN 6 6 DFE_EN 7 11 EYEHE_EN 12 12 EYEHO_EN 13 13 TGG_EN 14 14 ESL_TWICE_DSL 15 15 ixDPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_4 2 0x1264 4 0 4294967295 CTLE_TH 0 3 VGA_TH 4 7 DFE1_TH 8 11 DFE2_TH 12 15 ixDPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_5 2 0x1265 4 0 4294967295 DFE3_TH 0 3 DFE4_TH 4 7 DFE5_TH 8 11 TH_OFFSET 12 15 ixDPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6 2 0x1266 6 0 4294967295 CTLE_MU 0 2 VGA_MU 3 5 ATT_MU 6 8 VGA_SAT_CNT 9 11 VGA_SAT_CNT_STICKY 12 12 ATT_LOW_TH 13 15 ixDPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_7 2 0x1267 4 0 4294967295 VGA_MIN_SAT 0 4 VGA_LEV_HIGH 5 9 VGA_LEV_LOW 10 14 RESERVED_15_15 15 15 ixDPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8 2 0x1268 6 0 4294967295 DFE1_MU 0 2 DFE2_MU 3 5 DFE3_MU 6 8 DFE4_MU 9 11 DFE5_MU 12 14 RESERVED_15_15 15 15 ixDPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_9 2 0x1269 2 0 4294967295 ERR_SLE_ADPT_INIT 0 7 ERR_SLO_ADPT_INIT 8 15 ixDPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG 2 0x126a 6 0 4294967295 RST_ADPT_ATT 0 0 RST_ADPT_VGA 1 1 RST_ADPT_CTLE_BOOST 2 2 RST_ADPT_CTLE_POLE 3 3 RST_ADPT_TAP1 4 4 RESERVED_15_5 5 15 ixDPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ATT_STATUS 2 0x126b 3 0 4294967295 ATT_ADPT_CODE 0 7 ASM1_DON 8 8 RESERVED_15_9 9 15 ixDPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_VGA_STATUS 2 0x126c 3 0 4294967295 VGA_ADPT_CODE 0 9 ASM1_DONE 10 10 RESERVED_15_11 11 15 ixDPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_CTLE_STATUS 2 0x126d 4 0 4294967295 CTLE_BOOST_ADPT_CODE 0 9 CTLE_POLE_ADPT_CODE 10 12 ASM1_DONE 13 13 RESERVED_15_14 14 15 ixDPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_DFE_TAP1_STATUS 2 0x126e 3 0 4294967295 DFE_TAP1_ADPT_CODE 0 12 ASM1_DONE 13 13 RESERVED_15_14 14 15 ixDPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_DFE_TAP2_STATUS 2 0x126f 3 0 4294967295 DFE_TAP2_ADPT_CODE 0 11 ASM1_DONE 12 12 RESERVED_15_13 13 15 ixDPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_DFE_TAP3_STATUS 2 0x1270 3 0 4294967295 DFE_TAP3_ADPT_CODE 0 11 ASM1_DONE 12 12 RESERVED_15_13 13 15 ixDPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_DFE_TAP4_STATUS 2 0x1271 3 0 4294967295 DFE_TAP4_ADPT_CODE 0 11 ASM1_DONE 12 12 RESERVED_15_13 13 15 ixDPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_DFE_TAP5_STATUS 2 0x1272 3 0 4294967295 DFE_TAP5_ADPT_CODE 0 11 ASM1_DONE 12 12 RESERVED_15_13 13 15 ixDPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_DFE_DATA_EVEN_VDAC_OFST 2 0x1273 2 0 4294967295 DFE_DATA_EVEN_VDAC_OFST 0 7 RESERVED_15_8 8 15 ixDPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_DFE_DATA_ODD_VDAC_OFST 2 0x1274 2 0 4294967295 DFE_DATA_ODD_VDAC_OFST 0 7 RESERVED_15_8 8 15 ixDPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN 2 0x1275 2 0 4294967295 RX_ANA_SLICER_CTRL_E 0 3 RESERVED_15_4 4 15 ixDPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD 2 0x1276 2 0 4294967295 RX_ANA_SLICER_CTRL_O 0 3 RESERVED_15_4 4 15 ixDPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST 2 0x1277 2 0 4294967295 DFE_ERROR_EVEN_VDAC_OFST 0 7 RESERVED_15_8 8 15 ixDPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST 2 0x1278 2 0 4294967295 DFE_ERROR_ODD_VDAC_OFST 0 7 RESERVED_15_8 8 15 ixDPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL 2 0x1279 2 0 4294967295 E_SLO_LVL 0 7 E_SLE_LVL 8 15 ixDPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_RESET 2 0x127a 2 0 4294967295 RESET_ASM1 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1 2 0x127b 4 0 4294967295 DFE_T1_IDAC 0 4 DFE_T2_IDAC 5 9 DCC_START_IDAC 10 14 RESERVED_15_15 15 15 ixDPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2 2 0x127c 3 0 4294967295 DFE_DAT_EVEN_VDAC 0 4 DFE_DAT_ODD_VDAC 5 9 RESERVED_15_10 10 15 ixDPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3 2 0x127d 3 0 4294967295 DFE_ERR_EVEN_VDAC 0 4 DFE_ERR_ODD_VDAC 5 9 RESERVED_15_10 10 15 ixDPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_CR_BANK_ADDR 2 0x127e 1 0 4294967295 ADDR 0 15 ixDPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_CR_BANK_DATA 2 0x127f 1 0 4294967295 DATA 0 15 ixDPCSSYS_CR1_LANE2_DIG_RX_STAT_LD_VAL_1 2 0x1280 2 0 4294967295 SC1_LD_VAL 0 14 SC1_START 15 15 ixDPCSSYS_CR1_LANE2_DIG_RX_STAT_DATA_MSK 2 0x1281 1 0 4294967295 DATA_MSK_15_0 0 15 ixDPCSSYS_CR1_LANE2_DIG_RX_STAT_MATCH_CTL0 2 0x1282 4 0 4294967295 PTTRN_MSK_CR1A_4_0 0 4 PTTRN_CR1A_4_0 5 9 DATA_MSK_19_16 10 13 SCOPE_DLY 14 15 ixDPCSSYS_CR1_LANE2_DIG_RX_STAT_MATCH_CTL1 2 0x1283 5 0 4294967295 PTTRN_CR1B_EN 0 0 PTTRN_MSK_CR1B_4_0 1 5 PTTRN_CR1B_4_0 6 10 PTTRN_CR1A_ADPT_EN 11 11 RESERVED_15_12 12 15 ixDPCSSYS_CR1_LANE2_DIG_RX_STAT_STAT_CTL0 2 0x1284 10 0 4294967295 RESERVED_0 0 0 CORR_SHFT_SEL_VGA 1 1 CORR_SHFT_SEL 2 2 CORR_SRC_SEL 3 4 CORR_MODE_EN 5 5 STAT_SHFT_SEL 6 9 STAT_SRC_SEL 10 12 STAT_RXCLK_SEL 13 13 SC_TIMER_MODE 14 14 SKIP_EN 15 15 ixDPCSSYS_CR1_LANE2_DIG_RX_STAT_STAT_CTL1 2 0x1285 13 0 4294967295 STAT_CNT_0_EN 0 0 STAT_CNT_1_EN 1 1 STAT_CNT_2_EN 2 2 STAT_CNT_3_EN 3 3 STAT_CNT_4_EN 4 4 STAT_CNT_5_EN 5 5 STAT_CNT_6_EN 6 6 RESERVED_8_7 7 8 SC_PAUSE 9 9 STAT_CLK_EN 10 10 DATA_DLY_SEL 11 12 VLD_LOSS_CLR 13 13 VLD_CTL 14 15 ixDPCSSYS_CR1_LANE2_DIG_RX_STAT_SMPL_CNT1 2 0x1286 2 0 4294967295 SMPL_CNT1 0 14 SMPL_CNT1_DONE 15 15 ixDPCSSYS_CR1_LANE2_DIG_RX_STAT_STAT_CNT_0 2 0x1287 2 0 4294967295 STAT_CNT_0 0 14 SMPL_CNT1_DONE 15 15 ixDPCSSYS_CR1_LANE2_DIG_RX_STAT_STAT_CNT_1 2 0x1288 2 0 4294967295 STAT_CNT_1 0 14 SMPL_CNT1_DONE 15 15 ixDPCSSYS_CR1_LANE2_DIG_RX_STAT_STAT_CNT_2 2 0x1289 2 0 4294967295 STAT_CNT_2 0 14 SMPL_CNT1_DONE 15 15 ixDPCSSYS_CR1_LANE2_DIG_RX_STAT_STAT_CNT_3 2 0x128a 2 0 4294967295 STAT_CNT_3 0 14 SMPL_CNT1_DONE 15 15 ixDPCSSYS_CR1_LANE2_DIG_RX_STAT_STAT_CNT_4 2 0x128b 2 0 4294967295 STAT_CNT_4 0 14 SMPL_CNT1_DONE 15 15 ixDPCSSYS_CR1_LANE2_DIG_RX_STAT_STAT_CNT_5 2 0x128c 2 0 4294967295 STAT_CNT_5 0 14 SMPL_CNT1_DONE 15 15 ixDPCSSYS_CR1_LANE2_DIG_RX_STAT_STAT_CNT_6 2 0x128d 2 0 4294967295 STAT_CNT_6 0 14 SMPL_CNT1_DONE 15 15 ixDPCSSYS_CR1_LANE2_DIG_RX_STAT_CAL_COMP_CLK_CTL 2 0x128e 3 0 4294967295 PRECHRGE_CNT 0 2 REF_DIV_CNT 3 5 RESERVED_15_6 6 15 ixDPCSSYS_CR1_LANE2_DIG_RX_STAT_MATCH_CTL2 2 0x128f 2 0 4294967295 PTTRN_CR1A_19_5 0 14 RESERVED_15_15 15 15 ixDPCSSYS_CR1_LANE2_DIG_RX_STAT_MATCH_CTL3 2 0x1290 2 0 4294967295 PTTRN_MSK_CR1A_19_5 0 14 RESERVED_15_15 15 15 ixDPCSSYS_CR1_LANE2_DIG_RX_STAT_MATCH_CTL4 2 0x1291 2 0 4294967295 PTTRN_CR1B_19_5 0 14 RESERVED_15_15 15 15 ixDPCSSYS_CR1_LANE2_DIG_RX_STAT_MATCH_CTL5 2 0x1292 2 0 4294967295 PTTRN_MSK_CR1B_19_5 0 14 RESERVED_15_15 15 15 ixDPCSSYS_CR1_LANE2_DIG_RX_STAT_STAT_CTL2 2 0x1293 4 0 4294967295 DATA_DLY_SEL_2 0 0 SCOPE_DLY_2 1 1 DISABLE_SAMPLE_COUNT 2 2 RESERVED_15_3 3 15 ixDPCSSYS_CR1_LANE2_DIG_RX_STAT_STAT_STOP 2 0x1294 2 0 4294967295 SC1_STOP 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR1_LANE2_DIG_MPHY_RX_PWM_CTL 2 0x1295 3 0 4294967295 RX_PWM_POL 0 0 RX_PWM_DATA_POL 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR1_LANE2_DIG_MPHY_RX_TERM_LS_CTL 2 0x1296 2 0 4294967295 RX_TERM_LCC_CNT 0 2 RESERVED_15_3 3 15 ixDPCSSYS_CR1_LANE2_DIG_MPHY_RX_ANA_PWM_CLK_STABLE_CNT 2 0x1297 2 0 4294967295 PWM_CLK_STABLE_CNT 0 3 RESERVED_15_4 4 15 ixDPCSSYS_CR1_LANE2_DIG_ANA_TX_OVRD_OUT 2 0x12a0 15 0 4294967295 TX_ANA_CLK_SHIFT 0 0 TX_ANA_DATA_EN 1 1 TX_ANA_REFGEN_EN 2 2 TX_ANA_VCM_HOLD 3 3 TX_ANA_CLK_EN 4 4 TX_ANA_WORD_CLK_EN 5 5 TX_ANA_MPLLA_CLK_EN 6 6 TX_ANA_MPLLB_CLK_EN 7 7 TX_ANA_RESET 8 8 TX_ANA_SERIAL_EN 9 9 TX_ANA_DATA_RATE 10 11 RESERVED 12 12 TX_DIV4_EN 13 13 TX_RXDET_EN 14 14 TX_OVRD_EN 15 15 ixDPCSSYS_CR1_LANE2_DIG_ANA_TX_TERM_CODE_OVRD_OUT 2 0x12a1 5 0 4294967295 TX_TERM_CODE 0 9 TX_TERM_OVRD_EN 10 10 TX_DRV_SRC 11 12 TX_DRV_SRC_OVRD_EN 13 13 RESERVED_15_14 14 15 ixDPCSSYS_CR1_LANE2_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT 2 0x12a2 3 0 4294967295 TX_TERM_DN_CLK 0 0 TX_TERM_CLK_SELF_CLEAR_DISABLE 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR1_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_0 2 0x12a3 3 0 4294967295 TX_ANA_LOAD_CLK 0 0 TX_ANA_CTRL_LEG_PULL_EN_13_0 1 14 TX_EQ_OVRD_EN 15 15 ixDPCSSYS_CR1_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_1 2 0x12a4 2 0 4294967295 TX_ANA_CTRL_LEG_PULL_EN_19_14 0 5 RESERVED_15_6 6 15 ixDPCSSYS_CR1_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_2 2 0x12a5 4 0 4294967295 RESERVED 0 2 TX_ANA_CTRL_EQ_MUX_SEL 3 6 TX_ANA_CTRL_PRE 7 12 RESERVED_15_13 13 15 ixDPCSSYS_CR1_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_3 2 0x12a6 2 0 4294967295 TX_ANA_CTRL_POST 0 8 RESERVED_15_9 9 15 ixDPCSSYS_CR1_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_4 2 0x12a7 1 0 4294967295 TX_ANA_CTRL_LEG_PULL_DIR_19_4 0 15 ixDPCSSYS_CR1_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_5 2 0x12a8 2 0 4294967295 TX_ANA_CTRL_LEG_PULL_DIR_3_0 0 3 RESERVED_15_4 4 15 ixDPCSSYS_CR1_LANE2_DIG_ANA_RX_CTL_OVRD_OUT 2 0x12a9 9 0 4294967295 RESERVED 0 0 RX_ANA_DATA_RATE 1 2 RX_ANA_WORD_CLK_EN 3 3 RX_ANA_DIV4_EN 4 4 RX_ANA_DFE_TAPS_EN 5 5 RX_ANA_ADAPTATION_EN 6 6 RX_LBK_CLK_EN 7 7 RX_CTL_OVRD_EN 8 8 RESERVED_15_9 9 15 ixDPCSSYS_CR1_LANE2_DIG_ANA_RX_PWR_OVRD_OUT 2 0x12aa 9 0 4294967295 RX_ANA_AFE_EN 0 0 RX_ANA_CLK_VREG_EN 1 1 RX_ANA_CLK_DCC_EN 2 2 RX_ANA_CLK_EN 3 3 RX_ANA_CDR_EN 4 4 RX_ANA_DESERIAL_EN 5 5 RX_PWR_OVRD_EN 6 6 RX_ANA_FAST_START 7 7 RESERVED_15_8 8 15 ixDPCSSYS_CR1_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0 2 0x12ab 7 0 4294967295 RX_ANA_CDR_VCO_EN 0 0 RX_ANA_CDR_STARTUP 1 1 RX_VCO_CDR_OVRD_EN 2 2 RX_ANA_CDR_FREQ_TUNE 3 12 RX_ANA_VCO_CNTR_EN 13 13 RX_ANA_VCO_CNTR_CLK 14 14 RX_CDR_FREQ_TUNE_OVRD_EN 15 15 ixDPCSSYS_CR1_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_1 2 0x12ac 3 0 4294967295 RX_ANA_CDR_VCO_LOWFREQ 0 0 RX_ANA_VCO_CNTR_PD 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR1_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_2 2 0x12ad 3 0 4294967295 RX_ANA_CDR_FREQ_TUNE_CLK 0 0 CDR_FREQ_TUNE_CLK_SELF_CLEAR_DISABLE 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR1_LANE2_DIG_ANA_RX_CAL 2 0x12ae 7 0 4294967295 RX_ANA_CAL_MUXA_SEL 0 4 RX_ANA_CAL_MUXB_SEL 5 9 RX_ANA_CAL_LPFBYP_EN 10 10 RESERVED 11 11 RX_ANA_SLICER_CAL_EN 12 12 RX_ANA_CAL_MODE 13 14 RX_ANA_CAL_COMP_EN 15 15 ixDPCSSYS_CR1_LANE2_DIG_ANA_RX_DAC_CTRL 2 0x12af 2 0 4294967295 RX_ANA_CAL_DAC_CTRL 0 7 RESERVED_15_8 8 15 ixDPCSSYS_CR1_LANE2_DIG_ANA_RX_DAC_CTRL_OVRD 2 0x12b0 2 0 4294967295 RX_CAL_DAC_CTRL_OVRD 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR1_LANE2_DIG_ANA_RX_DAC_CTRL_SEL 2 0x12b1 2 0 4294967295 RX_ANA_CAL_DAC_CTRL_SEL 0 4 RESERVED_15_5 5 15 ixDPCSSYS_CR1_LANE2_DIG_ANA_RX_AFE_ATT_VGA 2 0x12b2 5 0 4294967295 RX_ANA_AFE_ATT_LVL 0 2 RX_ANA_AFE_GAIN 3 6 RESERVED 7 10 RX_AFE_OVRD_EN 11 11 RESERVED_15_12 12 15 ixDPCSSYS_CR1_LANE2_DIG_ANA_RX_AFE_CTLE 2 0x12b3 3 0 4294967295 RESERVED 0 2 RX_ANA_AFE_CTLE_BOOST 3 7 RESERVED_15_8 8 15 ixDPCSSYS_CR1_LANE2_DIG_ANA_RX_SCOPE 2 0x12b4 7 0 4294967295 RX_ANA_SCOPE_EN 0 0 RX_ANA_SCOPE_SEL 1 2 RX_ANA_SCOPE_PH_CLK 3 3 RX_ANA_SCOPE_PHASE 4 11 RX_ANA_SCOPE_CLK_EN 12 12 RX_SCOPE_SELF_CLEAR_DISABLE 13 13 RESERVED_15_14 14 15 ixDPCSSYS_CR1_LANE2_DIG_ANA_RX_SLICER_CTRL 2 0x12b5 4 0 4294967295 RX_ANA_SLICER_CTRL_E 0 3 RX_ANA_SLICER_CTRL_O 4 7 RX_ANA_SLICER_CTRL_OVRD_EN 8 8 RESERVED_15_9 9 15 ixDPCSSYS_CR1_LANE2_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST 2 0x12b6 2 0 4294967295 RX_ANA_IQ_PHASE_ADJUST 0 6 RESERVED_15_7 7 15 ixDPCSSYS_CR1_LANE2_DIG_ANA_RX_ANA_IQ_SENSE_EN 2 0x12b7 2 0 4294967295 RX_ANA_IQ_SENSE_EN 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR1_LANE2_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN 2 0x12b8 3 0 4294967295 RX_ANA_CAL_DAC_CTRL_EN 0 0 DAC_CTRL_SELF_CLEAR_DISABLE 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR1_LANE2_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE 2 0x12b9 3 0 4294967295 RX_ANA_AFE_UPDATE_EN 0 0 AFE_UPDATE_SELF_CLEAR_DISABLE 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR1_LANE2_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK 2 0x12ba 3 0 4294967295 RX_ANA_IQ_PHASE_ADJUST_CLK 0 0 PHASE_ADJUST_SELF_CLEAR_DISABLE 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR1_LANE2_DIG_ANA_STATUS_0 2 0x12bb 9 0 4294967295 TX_ANA_CLK_SHIFT_ACK 0 0 TX_ANA_RXDETP_RESULT 1 1 TX_ANA_RXDETM_RESULT 2 2 TX_ANA_LOOPBACK_EN 3 3 TX_ANA_CLK_LB_EN 4 4 RX_ANA_CAL_RESULT 5 5 RX_ANA_SCOPE_DATA 6 6 TX_ANA_DCC_CAL_RESULT 7 7 TX_ANA_CTRL_EQ_MUX 8 15 ixDPCSSYS_CR1_LANE2_DIG_ANA_STATUS_1 2 0x12bc 2 0 4294967295 RX_ANA_VCO_CNTR 0 12 RESERVED_15_13 13 15 ixDPCSSYS_CR1_LANE2_DIG_ANA_RX_TERM_CODE_OVRD_OUT 2 0x12bd 3 0 4294967295 RX_TERM_CODE 0 5 RX_TERM_OVRD_EN 6 6 RESERVED_15_7 7 15 ixDPCSSYS_CR1_LANE2_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT 2 0x12be 3 0 4294967295 RX_TERM_CLK 0 0 RX_TERM_CLK_SELF_CLEAR_DISABLE 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR1_LANE2_DIG_ANA_MPHY_OVRD_OUT 2 0x12bf 9 0 4294967295 RX_ANA_SQ_CTRL_TRESH 0 2 RX_ANA_SQ_CTRL_TRESH_OVRD_EN 3 3 RX_ANA_SQ_CTRL_RESP 4 5 RX_ANA_SQ_CTRL_RESP_OVRD_EN 6 6 RX_ANA_PWM_EN 7 7 RX_ANA_PWM_EN_OVRD_EN 8 8 RX_ANA_PWM_CLK_SEL 9 10 RX_ANA_PWM_CLK_SEL_OVRD_EN 11 11 RESERVED_15_12 12 15 ixDPCSSYS_CR1_LANE2_DIG_ANA_SIGDET_OVRD_OUT_1 2 0x12c0 7 0 4294967295 RX_ANA_SIGDET_HF_THRESH 0 2 RX_ANA_SIGDET_HF_THRESH_OVRD_EN 3 3 RX_ANA_SIGDET_HF_CAL_TUNE 4 9 RX_ANA_SIGDET_CAL_TUNE_OVRD_EN 10 10 RX_ANA_SIGDET_CAL_EN 11 11 RX_ANA_SIGDET_CAL_EN_OVRD_EN 12 12 RESERVED_15_13 13 15 ixDPCSSYS_CR1_LANE2_DIG_ANA_SIGDET_OVRD_OUT_2 2 0x12c1 7 0 4294967295 RX_ANA_SIGDET_LF_THRESH 0 2 RX_ANA_SIGDET_LF_THRESH_OVRD_EN 3 3 RX_ANA_SIGDET_LF_FILTER_EN 4 4 RX_ANA_SIGDET_LF_FILTER_EN_OVRD_EN 5 5 RX_ANA_SIGDET_CAL_TUNE 6 11 RX_ANA_SIGDET_CAL_TUNE_OVRD_EN 12 12 RESERVED_15_13 13 15 ixDPCSSYS_CR1_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT 2 0x12c2 8 0 4294967295 TX_ANA_DCC_CAL_RANGE 0 1 TX_ANA_DCC_CAL_RANGE_OVRD_EN 2 2 TX_ANA_DCC_CAL_COMP_EN 3 3 TX_ANA_DCC_CAL_COMP_EN_OVRD_EN 4 4 TX_ANA_DCC_CAL_CTRL 5 12 TX_ANA_DCC_CAL_CTRL_OVRD_EN 13 13 TX_ANA_DCC_CAL_CTRL_EN 14 14 TX_ANA_DCC_CAL_CTRL_EN_OVRD_EN 15 15 ixDPCSSYS_CR1_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2 2 0x12c3 5 0 4294967295 TX_ANA_DCC_CAL_CTRL_SEL 0 2 TX_ANA_DCC_CAL_CTRL_SEL_OVRD_EN 3 3 TX_ANA_DCC_CLK_COMP 4 4 TX_ANA_DCC_CLK_COMP_OVRD_EN 5 5 RESERVED_15_6 6 15 ixDPCSSYS_CR1_LANE2_DIG_ANA_TX_OVRD_OUT_2 2 0x12c4 6 0 4294967295 TX_ANA_FAST_START 0 0 TX_ANA_FAST_START_OVRD_EN 1 1 TX_CLK_LB_EN 2 2 TX_CLK_LB_EN_OVRD_EN 3 3 TX_ACJTAG_EN 4 4 RESERVED_15_5 5 15 ixDPCSSYS_CR1_LANE2_ANA_TX_OVRD_MEAS 2 0x12e0 9 0 4294967295 OVRD_CLK_SHIFT 0 0 CLK_SHIFT_REG 0 0 MEAS_ATB_CAL_MUX 0 0 MEAS_ATB_CAL_COMP 0 0 OVRD_VCM_HOLD 0 0 VCM_HOLD_REG 0 0 PULL_UP_REG 0 0 PULL_DN_REG 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR1_LANE2_ANA_TX_PWR_OVRD 2 0x12e1 9 0 4294967295 OVRD_TX_LOOPBACK 0 0 LOOPBACK_EN_REG 0 0 REFGEN_EN_REG 0 0 CLK_DIV_EN_REG 0 0 DATA_EN_REG_INT 0 0 CLK_EN_REG 0 0 SERIAL_EN_REG 0 0 OVRD_EN 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR1_LANE2_ANA_TX_ALT_BUS 2 0x12e2 6 0 4294967295 DRV_SOURCE_REG 0 0 OVRD_ALT_BUS 0 0 ATB_S_ENABLE 0 0 TX_ALT_RINGO 0 0 JTAG_DATA_REG 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR1_LANE2_ANA_TX_ATB1 2 0x12e3 9 0 4294967295 MEAS_ATB_GD 0 0 MEAS_ATB_VDDH 0 0 OVERRIDE_RXDETREF 0 0 MEAS_ATB_VPTX 0 0 OVERRIDE_REGREF 0 0 MEAS_ATB_VREG_DRV 0 0 MEAS_ATB_VREG 0 0 MEAS_ATB_VPH_HALF 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR1_LANE2_ANA_TX_ATB2 2 0x12e4 9 0 4294967295 MEAS_ATB_VCM 0 0 MEAS_ATB_CAL_VDAC_CM 0 0 MEAS_ATB_CAL_VDAC_DIFF 0 0 MEAS_ATB_TXM 0 0 MEAS_ATB_TXP 0 0 MEAS_ATB_RXDETREF 0 0 LFPS_HIGH_PRIORITY 0 0 OSC_DIV4_EN 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR1_LANE2_ANA_TX_DCC_DAC 2 0x12e5 2 0 4294967295 DCC_DAC_REG 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR1_LANE2_ANA_TX_DCC_CTRL1 2 0x12e6 7 0 4294967295 NC0 0 0 OVRD_DCC_DAC_CTRL_SEL 0 0 DCC_DAC_CTRL_SEL_REG 0 0 OVRD_DCC_DAC_CTRL_EN 0 0 DCC_DAC_CTRL_EN_REG 0 0 OVRD_DCC_DAC_REG 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR1_LANE2_ANA_TX_TERM_CODE 2 0x12e7 2 0 4294967295 TERM_CODE_REG_70 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR1_LANE2_ANA_TX_TERM_CODE_CTRL 2 0x12e8 8 0 4294967295 VREG_BOOST_1 0 0 OVRD_UPDATE_TERM 0 0 UPDATE_TERM_REG 0 0 OVRD_RESET_TERM 0 0 RESET_TERM_REG 0 0 OVRD_TERM_CODE 0 0 TERM_CODE_REG_98 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR1_LANE2_ANA_TX_OVRD_CLK 2 0x12e9 9 0 4294967295 VREG_BOOST_0 0 0 CLK_LB_EN_REG 0 0 OVRD_LB_EN 0 0 MPLLB_CLK_EN_REG 0 0 MPLLA_CLK_EN_REG 0 0 OVRD_MPLLAB_EN 0 0 WORD_CLK_EN_REG 0 0 OVRD_WORD_CLK_EN 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR1_LANE2_ANA_TX_MISC1 2 0x12ea 8 0 4294967295 MEAS_ATB_CAL_CLK_ALIGN 0 0 OVRD_DCC_DAC_CTRL_RANGE 0 0 DCC_DAC_CTRL_RANGE_REG 0 0 OVRD_VREF_SEL 0 0 VREF_SEL_REG 0 0 FORCE_ATB_TXM 0 0 FORCE_ATB_TXP 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR1_LANE2_ANA_TX_MISC2 2 0x12eb 8 0 4294967295 TX_PEAKING_LVL 0 0 VREG_CP_GAIN_CTRL 0 0 TX_SLEW_EN 0 0 EN_INV_POST 0 0 EN_INV_PRE 0 0 TX_VREG_EN_BYP 0 0 TX_VDRIVER_PULLDN_EN 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR1_LANE2_ANA_TX_MISC3 2 0x12ec 4 0 4294967295 TX_VREG_OVRD_RING_CTRL 0 0 TX_DCC_LOWV 0 0 NC7_2 2 7 RESERVED_15_8 8 15 ixDPCSSYS_CR1_LANE2_ANA_TX_RESERVED2 2 0x12ed 2 0 4294967295 NC7_0 0 7 RESERVED_15_8 8 15 ixDPCSSYS_CR1_LANE2_ANA_TX_RESERVED3 2 0x12ee 2 0 4294967295 NC7_0 0 7 RESERVED_15_8 8 15 ixDPCSSYS_CR1_LANE2_ANA_TX_RESERVED4 2 0x12ef 2 0 4294967295 NC7_0 0 7 RESERVED_15_8 8 15 ixDPCSSYS_CR1_LANE2_ANA_RX_CLK_1 2 0x12f0 8 0 4294967295 CDR_VCO_STARTUP_CODE 0 0 CDR_VCO_TEMP_COMP_EN 0 0 CDR_VCO_USE_UNCAL_BIAS 0 0 OVERRIDE_CDR_EN 0 0 OVRD_CLK_EN 0 0 CLK_EN_REG 0 0 NC7 7 7 RESERVED_15_8 8 15 ixDPCSSYS_CR1_LANE2_ANA_RX_CLK_2 2 0x12f1 5 0 4294967295 IQ_PHASE_ADJUST_REG 0 0 OVRD_IQ_PHASE_ADJUST 0 0 RX_LOOPBACK_CLK_REG 0 0 OVRD_RX_LOOPBACK_CLK 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR1_LANE2_ANA_RX_CDR_DES 2 0x12f2 7 0 4294967295 OVRD_WORD_CLK_EN 0 0 WORD_CLK_EN_REG 0 0 PHDET_ODD_REG 0 0 PHDET_EVEN_REG 0 0 SIGDET_VREF_EXT_EN 0 0 NC7_5 5 7 RESERVED_15_8 8 15 ixDPCSSYS_CR1_LANE2_ANA_RX_SLC_CTRL 2 0x12f3 3 0 4294967295 RX_SLICER_CTRL_O_REG 0 0 RX_SLICER_CTRL_E_REG 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR1_LANE2_ANA_RX_PWR_CTRL1 2 0x12f4 8 0 4294967295 OVRD_ACJT_EN 0 0 ACJT_EN_REG 0 0 OVRD_AFE_EN 0 0 AFE_EN_REG 0 0 AFE_CM_SEL 0 0 ATT_PULLDN_EN 0 0 NC7_7 7 7 RESERVED_15_8 8 15 ixDPCSSYS_CR1_LANE2_ANA_RX_PWR_CTRL2 2 0x12f5 9 0 4294967295 OVRD_DFE_EN 0 0 DFE_EN_REG 0 0 OVRD_DESERIAL_EN 0 0 DESERIAL_EN_REG 0 0 OVRD_LOOPBACK_EN 0 0 LOOPBACK_EN_REG 0 0 OVRD_FAST_START 0 0 FAST_START_REG 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR1_LANE2_ANA_RX_SQ 2 0x12f6 7 0 4294967295 SQ_CTRL_RESP_REG 0 0 OVRD_SQ_CTRL_RESP 0 0 NC4_3 3 4 SQ_CTRL_TRESH_REG 0 0 OVRD_SQ_CTRL_TRESH 0 0 AFE_LOOPBACK_SEL 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR1_LANE2_ANA_RX_CAL1 2 0x12f7 5 0 4294967295 DFE_TAPS_EN_REG 0 0 OVRD_DFE_TAPS_EN 0 0 CAL_MUXB_SEL_REG 0 0 OVRD_CAL_MUXB_SEL 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR1_LANE2_ANA_RX_CAL2 2 0x12f8 5 0 4294967295 AFE_PD_EQ_OFFSET 0 0 CAL_IDACS_USE_UNCAL 0 0 CAL_MUXA_SEL_REG 0 0 OVRD_CAL_MUXA_SEL 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR1_LANE2_ANA_RX_ATB_REGREF 2 0x12f9 8 0 4294967295 OVERRIDE_REGREF_VCO 0 0 OVERRIDE_REGREF_CLK 0 0 OVERRIDE_REGREF_IQC 0 0 BOOST_REGREF_IQC 0 0 OVRD_RX_SLICER_CTRL 0 0 OVRD_RX_TERM_AC_DCZ 0 0 RX_TERM_AC_DCZ_REG 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR1_LANE2_ANA_RX_ATB_MEAS1 2 0x12fa 9 0 4294967295 MASTER_ATB_EN 0 0 MEAS_ATB_VP 0 0 MEAS_ATB_GD 0 0 MEAS_ATB_VREG_VCO 0 0 MEAS_ATB_VREG_CLK 0 0 MEAS_ATB_VREG_IQC 0 0 REGS_FB_DIV_CTRL 0 0 RX_VREG_CLK_BYPASS 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR1_LANE2_ANA_RX_ATB_MEAS2 2 0x12fb 2 0 4294967295 MEAS_ATB_RX 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR1_LANE2_ANA_RX_ATB_MEAS3 2 0x12fc 7 0 4294967295 MEAS_ATB_CDR_VCO_GD 0 0 MEAS_ATB_CDR_VCO_VIREF_200U 0 0 MEAS_ATB_VIBIAS_CDR_VCO 0 0 MEAS_ATB_CDR_VCO_VOSC 0 0 MEAS_ATB_CAL_MUX 0 0 RX_VREG_OVERRIDE_RING_CTRL 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR1_LANE2_ANA_RX_ATB_MEAS4 2 0x12fd 3 0 4294967295 MEAS_ATB_CAL_VREF 0 0 NC7 7 7 RESERVED_15_8 8 15 ixDPCSSYS_CR1_LANE2_ANA_RX_ATB_FRC 2 0x12fe 2 0 4294967295 FRC_ATB_CAL_VREF 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR1_LANE2_ANA_RX_RESERVED1 2 0x12ff 2 0 4294967295 NC7_0 0 7 RESERVED_15_8 8 15 ixDPCSSYS_CR1_LANE3_DIG_ASIC_LANE_OVRD_IN 2 0x1300 5 0 4294967295 LANE_TX2RX_SER_LB 0 0 LANE_RX2TX_PAR_LB 1 1 EN 2 2 RX_ACJTAG_EN 3 3 RESERVED_15_4 4 15 ixDPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_0 2 0x1301 12 0 4294967295 REQ 0 0 REQ_OVRD_EN 1 1 PSTATE 2 3 PSTATE_OVRD_EN 4 4 RATE 5 7 RATE_OVRD_EN 8 8 WIDTH 9 10 WIDTH_OVRD_EN 11 11 MPLLB_SEL 12 12 MPLLB_SEL_OVRD_EN 13 13 DATA_EN 14 14 DATA_EN_OVRD_EN 15 15 ixDPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_1 2 0x1302 11 0 4294967295 NYQUIST_DATA 0 0 DISABLE 1 1 BEACON_EN 2 2 EN 3 3 TX_MAIN_CURSOR 4 9 MAIN_OVRD_EN 10 10 ASYNC_DRV_EN 11 11 ASYNC_DRV_OVRD_EN 12 12 TX_VREGDRV_BYP_OVRD 13 13 TX_VREGDRV_BYP_OVRD_EN 14 14 RESERVED_15_15 15 15 ixDPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_2 2 0x1303 6 0 4294967295 TX_PRE_CURSOR 0 5 PRE_OVRD_EN 6 6 TX_POST_CURSOR 7 12 POST_OVRD_EN 13 13 HDMIMODE_EN 14 14 HDMIMODE_ENABLE_OVRD_EN 15 15 ixDPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_3 2 0x1304 15 0 4294967295 CLK_RDY 0 0 CLK_RDY_OVRD_EN 1 1 DETECT_RX_REQ 2 2 DETECT_RX_REQ_OVRD_EN 3 3 INVERT 4 4 INVERT_OVRD_EN 5 5 LPD 6 6 LPD_OVRD_EN 7 7 TX_DC_COUP_EN 8 8 TX_DC_COUP_EN_OVRD_EN 9 9 PMA_EXTENDED_FIFO_EN 10 10 PMA_EXTENDED_FIFO_EN_OVRD_EN 11 11 TX_MPHY_MODE_EN 12 12 TX_MPHY_MODE_EN_OVRD_EN 13 13 RESERVED_15_14 14 15 ixDPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_4 2 0x1305 3 0 4294967295 RESET 0 0 RESET_OVRD_EN 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_OUT 2 0x1306 5 0 4294967295 TX_ACK 0 0 EN_TX_ACK 1 1 DETRX_RESULT 2 2 EN_DETRX_RESULT 3 3 RESERVED_15_4 4 15 ixDPCSSYS_CR1_LANE3_DIG_ASIC_RX_OVRD_OUT_0 2 0x130f 9 0 4294967295 ACK 0 0 ACK_OVRD_EN 1 1 ADAPT_STS 2 3 ADAPT_STS_OVRD_EN 4 4 RX_ASYNC_DATA 5 5 RX_ASYNC_DATA_OVRD_EN 6 6 RX_SQ_WEAKKEEP_OUT 7 7 RX_SQ_WEAKKEEP_OUT_OVRD_EN 8 8 RESERVED_15_9 9 15 ixDPCSSYS_CR1_LANE3_DIG_ASIC_LANE_ASIC_IN 2 0x1310 3 0 4294967295 LANE_TX2RX_SER_LB 0 0 LANE_RX2TX_PAR_LB 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR1_LANE3_DIG_ASIC_TX_ASIC_IN_0 2 0x1311 12 0 4294967295 CLK_RDY 0 0 RESET 1 1 INVERT 2 2 DATA_EN 3 3 REQ 4 4 LPD 5 5 PSTATE 6 7 RATE 8 10 WIDTH 11 12 MPLLB_SEL 13 13 DETECT_RX_REQ 14 14 DISABLE 15 15 ixDPCSSYS_CR1_LANE3_DIG_ASIC_TX_ASIC_IN_1 2 0x1312 7 0 4294967295 BEACON_EN 0 0 TX_MAIN_CURSOR 1 6 TX_ASYNC_EN 7 7 TX_ASYNC_DATA 8 8 TX_ASYNC_DRV_EN 9 9 TX_VREGDRV_BYP 10 10 RESERVED_15_11 11 15 ixDPCSSYS_CR1_LANE3_DIG_ASIC_TX_ASIC_IN_2 2 0x1313 3 0 4294967295 TX_PRE_CURSOR 0 5 TX_POST_CURSOR 6 11 RESERVED_15_12 12 15 ixDPCSSYS_CR1_LANE3_DIG_ASIC_TX_ASIC_OUT 2 0x1314 3 0 4294967295 TX_ACK 0 0 DETRX_RESULT 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR1_LANE3_DIG_ASIC_RX_ASIC_OUT_0 2 0x131b 4 0 4294967295 ACK 0 0 VALID 1 1 ADAPT_STS 2 3 RESERVED_15_4 4 15 ixDPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_5 2 0x131d 15 0 4294967295 RPTR_EN_MASTER_LANE 0 0 RPTR_EN_MASTER_LANE_OVRD_EN 1 1 DIG_CLK_EN_OTHER_LANE 2 2 DIG_CLK_EN_OTHER_LANE_OVRD_EN 3 3 DIG_CLK_STATE_MASTER_LANE 4 4 DIG_CLK_STATE_MASTER_LANE_OVRD_EN 5 5 SHIFT_MASTER_LANE 6 6 SHIFT_MASTER_LANE_ORVD_EN 7 7 SHIFT_ACK_OTHER_LANE 8 8 SHIFT_ACK_OTHER_LANE_OVRD_EN 9 9 LANE_MASTER 10 10 LANE_MASTER_OVRD_IN_EN 11 11 TX_DWORD_CLK_SYNC_OVRD 12 12 TX_DWORD_CLK_SYNC_OVRD_EN 13 13 RESERVED_15_14 14 15 ixDPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_OUT_1 2 0x131e 11 0 4294967295 RPTR_EN_OUT 0 0 RPTR_EN_OUT_OVRD_EN 1 1 DIG_CLK_EN_OUT 2 2 DIG_CLK_EN_OUT_OVRD_EN 3 3 DIG_CLK_STATE_OUT 4 4 DIG_CLK_STATE_OUT_OVRD_EN 5 5 SHIFT_OUT 6 6 SHIFT_OUT_OVRD_EN 7 7 SHIFT_ACK_OUT 8 8 SHIFT_ACK_OUT_OVRD_EN 9 9 RESERVED_15_10 10 15 ixDPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0 2 0x1320 11 0 4294967295 TX_P0_ANA_REFGEN_EN 0 0 TX_P0_ANA_VCM_HOLD 1 1 TX_P0_ANA_CLK_EN 2 2 TX_P0_ANA_WORD_CLK_EN 3 3 TX_P0_ANA_RESET 4 4 TX_P0_ANA_SERIAL_EN 5 5 TX_P0_DIG_CLK_EN 6 6 TX_P0_DATA_EN 7 7 TX_P0_ALLOW_RXDET 8 8 TX_P0_ANA_DCC_COMP_CAL_EN 9 9 RESERVED_15_10 10 15 ixDPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S 2 0x1321 11 0 4294967295 TX_P0S_ANA_REFGEN_EN 0 0 TX_P0S_ANA_VCM_HOLD 1 1 TX_P0S_ANA_CLK_EN 2 2 TX_P0S_ANA_WORD_CLK_EN 3 3 TX_P0S_ANA_RESET 4 4 TX_P0S_ANA_SERIAL_EN 5 5 TX_P0S_DIG_CLK_EN 6 6 TX_P0S_DATA_EN 7 7 TX_P0S_ALLOW_RXDET 8 8 TX_P0S_ANA_DCC_COMP_CAL_EN 9 9 RESERVED_15_10 10 15 ixDPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1 2 0x1322 11 0 4294967295 TX_P1_ANA_REFGEN_EN 0 0 TX_P1_ANA_VCM_HOLD 1 1 TX_P1_ANA_CLK_EN 2 2 TX_P1_ANA_WORD_CLK_EN 3 3 TX_P1_ANA_RESET 4 4 TX_P1_ANA_SERIAL_EN 5 5 TX_P1_DIG_CLK_EN 6 6 TX_P1_DATA_EN 7 7 TX_P1_ALLOW_RXDET 8 8 TX_P1_ANA_DCC_COMP_CAL_EN 9 9 RESERVED_15_10 10 15 ixDPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2 2 0x1323 12 0 4294967295 TX_P2_ANA_REFGEN_EN 0 0 TX_P2_ANA_VCM_HOLD 1 1 TX_P2_ANA_CLK_EN 2 2 TX_P2_ANA_WORD_CLK_EN 3 3 TX_P2_ANA_RESET 4 4 TX_P2_ANA_SERIAL_EN 5 5 TX_P2_DIG_CLK_EN 6 6 TX_P2_DATA_EN 7 7 TX_P2_ALLOW_RXDET 8 8 TX_P2_ALLOW_VBOOST 9 9 TX_P2_ANA_DCC_COMP_CAL_EN 10 10 RESERVED_15_11 11 15 ixDPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_0 2 0x1324 2 0 4294967295 TX_REFGEN_EN_TIME 0 7 TX_CLK_EN 8 15 ixDPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_1 2 0x1325 2 0 4294967295 TX_VCM_HOLD_TIME_14_0 0 14 SKIP_TX_VCM_HOLD_WAIT 15 15 ixDPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_2 2 0x1326 2 0 4294967295 TX_VBOOST_DIS_TIME_12_0 0 12 DTB_SEL 13 15 ixDPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_3 2 0x1327 3 0 4294967295 TX_VCM_HOLD_TIME_17_15 0 2 TX_VBOOST_DIS_TIME_13 3 3 RESERVED_15_4 4 15 ixDPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_4 2 0x1328 2 0 4294967295 TX_VCM_HOLD_GS_TIME 0 14 SKIP_TX_VCM_HOLD_GS_PULSE 15 15 ixDPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_5 2 0x1329 5 0 4294967295 TX_RXDET_TIME 0 9 FAST_TX_RXDET 10 10 TX_RESET_TIME 11 12 TX_SERIAL_EN_TIME 13 14 RESERVED_15_15 15 15 ixDPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_DCC_CR_BANK_ADDR 2 0x132a 1 0 4294967295 ADDR 0 15 ixDPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_DCC_CR_BANK_DATA 2 0x132b 1 0 4294967295 DATA 0 15 ixDPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_DCC_DAC_CTRL 2 0x132c 2 0 4294967295 CTRL 0 7 RESERVED_15_8 8 15 ixDPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_DCC_DAC_RANGE 2 0x132d 2 0 4294967295 CTRL 0 1 RESERVED_15_2 2 15 ixDPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_DCC_DAC_SEL 2 0x132e 6 0 4294967295 SEL 0 2 REQ 3 3 CTRL_UPD 4 4 RANGE_UPD 5 5 BIN_HOT 6 6 RESERVED_15_7 7 15 ixDPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_DCC_DAC_ACK 2 0x132f 2 0 4294967295 ACK 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_DCC_DAC_ADDR 2 0x1330 1 0 4294967295 ADDR 0 15 ixDPCSSYS_CR1_LANE3_DIG_TX_CLK_ALIGN_TX_CTL_0 2 0x1331 4 0 4294967295 TX_NUM_2UI_SHIFTS_16B_MODE 0 3 TX_NUM_2UI_SHIFTS_20B_MODE 4 7 TX_FIFO_BYPASS 8 8 RESERVED_15_9 9 15 ixDPCSSYS_CR1_LANE3_DIG_TX_LBERT_CTL 2 0x1332 4 0 4294967295 MODE 0 3 TRIGGER_ERR 4 4 PAT0 5 14 RESERVED_15_15 15 15 ixDPCSSYS_CR1_LANE3_DIG_RX_STAT_LD_VAL_1 2 0x1380 2 0 4294967295 SC1_LD_VAL 0 14 SC1_START 15 15 ixDPCSSYS_CR1_LANE3_DIG_RX_STAT_DATA_MSK 2 0x1381 1 0 4294967295 DATA_MSK_15_0 0 15 ixDPCSSYS_CR1_LANE3_DIG_RX_STAT_MATCH_CTL0 2 0x1382 4 0 4294967295 PTTRN_MSK_CR1A_4_0 0 4 PTTRN_CR1A_4_0 5 9 DATA_MSK_19_16 10 13 SCOPE_DLY 14 15 ixDPCSSYS_CR1_LANE3_DIG_RX_STAT_MATCH_CTL1 2 0x1383 5 0 4294967295 PTTRN_CR1B_EN 0 0 PTTRN_MSK_CR1B_4_0 1 5 PTTRN_CR1B_4_0 6 10 PTTRN_CR1A_ADPT_EN 11 11 RESERVED_15_12 12 15 ixDPCSSYS_CR1_LANE3_DIG_RX_STAT_STAT_CTL0 2 0x1384 10 0 4294967295 RESERVED_0 0 0 CORR_SHFT_SEL_VGA 1 1 CORR_SHFT_SEL 2 2 CORR_SRC_SEL 3 4 CORR_MODE_EN 5 5 STAT_SHFT_SEL 6 9 STAT_SRC_SEL 10 12 STAT_RXCLK_SEL 13 13 SC_TIMER_MODE 14 14 SKIP_EN 15 15 ixDPCSSYS_CR1_LANE3_DIG_RX_STAT_STAT_CTL1 2 0x1385 13 0 4294967295 STAT_CNT_0_EN 0 0 STAT_CNT_1_EN 1 1 STAT_CNT_2_EN 2 2 STAT_CNT_3_EN 3 3 STAT_CNT_4_EN 4 4 STAT_CNT_5_EN 5 5 STAT_CNT_6_EN 6 6 RESERVED_8_7 7 8 SC_PAUSE 9 9 STAT_CLK_EN 10 10 DATA_DLY_SEL 11 12 VLD_LOSS_CLR 13 13 VLD_CTL 14 15 ixDPCSSYS_CR1_LANE3_DIG_RX_STAT_SMPL_CNT1 2 0x1386 2 0 4294967295 SMPL_CNT1 0 14 SMPL_CNT1_DONE 15 15 ixDPCSSYS_CR1_LANE3_DIG_RX_STAT_STAT_CNT_0 2 0x1387 2 0 4294967295 STAT_CNT_0 0 14 SMPL_CNT1_DONE 15 15 ixDPCSSYS_CR1_LANE3_DIG_RX_STAT_STAT_CNT_1 2 0x1388 2 0 4294967295 STAT_CNT_1 0 14 SMPL_CNT1_DONE 15 15 ixDPCSSYS_CR1_LANE3_DIG_RX_STAT_STAT_CNT_2 2 0x1389 2 0 4294967295 STAT_CNT_2 0 14 SMPL_CNT1_DONE 15 15 ixDPCSSYS_CR1_LANE3_DIG_RX_STAT_STAT_CNT_3 2 0x138a 2 0 4294967295 STAT_CNT_3 0 14 SMPL_CNT1_DONE 15 15 ixDPCSSYS_CR1_LANE3_DIG_RX_STAT_STAT_CNT_4 2 0x138b 2 0 4294967295 STAT_CNT_4 0 14 SMPL_CNT1_DONE 15 15 ixDPCSSYS_CR1_LANE3_DIG_RX_STAT_STAT_CNT_5 2 0x138c 2 0 4294967295 STAT_CNT_5 0 14 SMPL_CNT1_DONE 15 15 ixDPCSSYS_CR1_LANE3_DIG_RX_STAT_STAT_CNT_6 2 0x138d 2 0 4294967295 STAT_CNT_6 0 14 SMPL_CNT1_DONE 15 15 ixDPCSSYS_CR1_LANE3_DIG_RX_STAT_CAL_COMP_CLK_CTL 2 0x138e 3 0 4294967295 PRECHRGE_CNT 0 2 REF_DIV_CNT 3 5 RESERVED_15_6 6 15 ixDPCSSYS_CR1_LANE3_DIG_RX_STAT_MATCH_CTL2 2 0x138f 2 0 4294967295 PTTRN_CR1A_19_5 0 14 RESERVED_15_15 15 15 ixDPCSSYS_CR1_LANE3_DIG_RX_STAT_MATCH_CTL3 2 0x1390 2 0 4294967295 PTTRN_MSK_CR1A_19_5 0 14 RESERVED_15_15 15 15 ixDPCSSYS_CR1_LANE3_DIG_RX_STAT_MATCH_CTL4 2 0x1391 2 0 4294967295 PTTRN_CR1B_19_5 0 14 RESERVED_15_15 15 15 ixDPCSSYS_CR1_LANE3_DIG_RX_STAT_MATCH_CTL5 2 0x1392 2 0 4294967295 PTTRN_MSK_CR1B_19_5 0 14 RESERVED_15_15 15 15 ixDPCSSYS_CR1_LANE3_DIG_RX_STAT_STAT_CTL2 2 0x1393 4 0 4294967295 DATA_DLY_SEL_2 0 0 SCOPE_DLY_2 1 1 DISABLE_SAMPLE_COUNT 2 2 RESERVED_15_3 3 15 ixDPCSSYS_CR1_LANE3_DIG_RX_STAT_STAT_STOP 2 0x1394 2 0 4294967295 SC1_STOP 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR1_LANE3_DIG_ANA_TX_OVRD_OUT 2 0x13a0 15 0 4294967295 TX_ANA_CLK_SHIFT 0 0 TX_ANA_DATA_EN 1 1 TX_ANA_REFGEN_EN 2 2 TX_ANA_VCM_HOLD 3 3 TX_ANA_CLK_EN 4 4 TX_ANA_WORD_CLK_EN 5 5 TX_ANA_MPLLA_CLK_EN 6 6 TX_ANA_MPLLB_CLK_EN 7 7 TX_ANA_RESET 8 8 TX_ANA_SERIAL_EN 9 9 TX_ANA_DATA_RATE 10 11 RESERVED 12 12 TX_DIV4_EN 13 13 TX_RXDET_EN 14 14 TX_OVRD_EN 15 15 ixDPCSSYS_CR1_LANE3_DIG_ANA_TX_TERM_CODE_OVRD_OUT 2 0x13a1 5 0 4294967295 TX_TERM_CODE 0 9 TX_TERM_OVRD_EN 10 10 TX_DRV_SRC 11 12 TX_DRV_SRC_OVRD_EN 13 13 RESERVED_15_14 14 15 ixDPCSSYS_CR1_LANE3_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT 2 0x13a2 3 0 4294967295 TX_TERM_DN_CLK 0 0 TX_TERM_CLK_SELF_CLEAR_DISABLE 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR1_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_0 2 0x13a3 3 0 4294967295 TX_ANA_LOAD_CLK 0 0 TX_ANA_CTRL_LEG_PULL_EN_13_0 1 14 TX_EQ_OVRD_EN 15 15 ixDPCSSYS_CR1_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_1 2 0x13a4 2 0 4294967295 TX_ANA_CTRL_LEG_PULL_EN_19_14 0 5 RESERVED_15_6 6 15 ixDPCSSYS_CR1_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_2 2 0x13a5 4 0 4294967295 RESERVED 0 2 TX_ANA_CTRL_EQ_MUX_SEL 3 6 TX_ANA_CTRL_PRE 7 12 RESERVED_15_13 13 15 ixDPCSSYS_CR1_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_3 2 0x13a6 2 0 4294967295 TX_ANA_CTRL_POST 0 8 RESERVED_15_9 9 15 ixDPCSSYS_CR1_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_4 2 0x13a7 1 0 4294967295 TX_ANA_CTRL_LEG_PULL_DIR_19_4 0 15 ixDPCSSYS_CR1_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_5 2 0x13a8 2 0 4294967295 TX_ANA_CTRL_LEG_PULL_DIR_3_0 0 3 RESERVED_15_4 4 15 ixDPCSSYS_CR1_LANE3_DIG_ANA_STATUS_0 2 0x13bb 9 0 4294967295 TX_ANA_CLK_SHIFT_ACK 0 0 TX_ANA_RXDETP_RESULT 1 1 TX_ANA_RXDETM_RESULT 2 2 TX_ANA_LOOPBACK_EN 3 3 TX_ANA_CLK_LB_EN 4 4 RX_ANA_CAL_RESULT 5 5 RX_ANA_SCOPE_DATA 6 6 TX_ANA_DCC_CAL_RESULT 7 7 TX_ANA_CTRL_EQ_MUX 8 15 ixDPCSSYS_CR1_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT 2 0x13c2 8 0 4294967295 TX_ANA_DCC_CAL_RANGE 0 1 TX_ANA_DCC_CAL_RANGE_OVRD_EN 2 2 TX_ANA_DCC_CAL_COMP_EN 3 3 TX_ANA_DCC_CAL_COMP_EN_OVRD_EN 4 4 TX_ANA_DCC_CAL_CTRL 5 12 TX_ANA_DCC_CAL_CTRL_OVRD_EN 13 13 TX_ANA_DCC_CAL_CTRL_EN 14 14 TX_ANA_DCC_CAL_CTRL_EN_OVRD_EN 15 15 ixDPCSSYS_CR1_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2 2 0x13c3 5 0 4294967295 TX_ANA_DCC_CAL_CTRL_SEL 0 2 TX_ANA_DCC_CAL_CTRL_SEL_OVRD_EN 3 3 TX_ANA_DCC_CLK_COMP 4 4 TX_ANA_DCC_CLK_COMP_OVRD_EN 5 5 RESERVED_15_6 6 15 ixDPCSSYS_CR1_LANE3_DIG_ANA_TX_OVRD_OUT_2 2 0x13c4 6 0 4294967295 TX_ANA_FAST_START 0 0 TX_ANA_FAST_START_OVRD_EN 1 1 TX_CLK_LB_EN 2 2 TX_CLK_LB_EN_OVRD_EN 3 3 TX_ACJTAG_EN 4 4 RESERVED_15_5 5 15 ixDPCSSYS_CR1_LANE3_ANA_TX_OVRD_MEAS 2 0x13e0 9 0 4294967295 OVRD_CLK_SHIFT 0 0 CLK_SHIFT_REG 0 0 MEAS_ATB_CAL_MUX 0 0 MEAS_ATB_CAL_COMP 0 0 OVRD_VCM_HOLD 0 0 VCM_HOLD_REG 0 0 PULL_UP_REG 0 0 PULL_DN_REG 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR1_LANE3_ANA_TX_PWR_OVRD 2 0x13e1 9 0 4294967295 OVRD_TX_LOOPBACK 0 0 LOOPBACK_EN_REG 0 0 REFGEN_EN_REG 0 0 CLK_DIV_EN_REG 0 0 DATA_EN_REG_INT 0 0 CLK_EN_REG 0 0 SERIAL_EN_REG 0 0 OVRD_EN 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR1_LANE3_ANA_TX_ALT_BUS 2 0x13e2 6 0 4294967295 DRV_SOURCE_REG 0 0 OVRD_ALT_BUS 0 0 ATB_S_ENABLE 0 0 TX_ALT_RINGO 0 0 JTAG_DATA_REG 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR1_LANE3_ANA_TX_ATB1 2 0x13e3 9 0 4294967295 MEAS_ATB_GD 0 0 MEAS_ATB_VDDH 0 0 OVERRIDE_RXDETREF 0 0 MEAS_ATB_VPTX 0 0 OVERRIDE_REGREF 0 0 MEAS_ATB_VREG_DRV 0 0 MEAS_ATB_VREG 0 0 MEAS_ATB_VPH_HALF 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR1_LANE3_ANA_TX_ATB2 2 0x13e4 9 0 4294967295 MEAS_ATB_VCM 0 0 MEAS_ATB_CAL_VDAC_CM 0 0 MEAS_ATB_CAL_VDAC_DIFF 0 0 MEAS_ATB_TXM 0 0 MEAS_ATB_TXP 0 0 MEAS_ATB_RXDETREF 0 0 LFPS_HIGH_PRIORITY 0 0 OSC_DIV4_EN 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR1_LANE3_ANA_TX_DCC_DAC 2 0x13e5 2 0 4294967295 DCC_DAC_REG 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR1_LANE3_ANA_TX_DCC_CTRL1 2 0x13e6 7 0 4294967295 NC0 0 0 OVRD_DCC_DAC_CTRL_SEL 0 0 DCC_DAC_CTRL_SEL_REG 0 0 OVRD_DCC_DAC_CTRL_EN 0 0 DCC_DAC_CTRL_EN_REG 0 0 OVRD_DCC_DAC_REG 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR1_LANE3_ANA_TX_TERM_CODE 2 0x13e7 2 0 4294967295 TERM_CODE_REG_70 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR1_LANE3_ANA_TX_TERM_CODE_CTRL 2 0x13e8 8 0 4294967295 VREG_BOOST_1 0 0 OVRD_UPDATE_TERM 0 0 UPDATE_TERM_REG 0 0 OVRD_RESET_TERM 0 0 RESET_TERM_REG 0 0 OVRD_TERM_CODE 0 0 TERM_CODE_REG_98 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR1_LANE3_ANA_TX_OVRD_CLK 2 0x13e9 9 0 4294967295 VREG_BOOST_0 0 0 CLK_LB_EN_REG 0 0 OVRD_LB_EN 0 0 MPLLB_CLK_EN_REG 0 0 MPLLA_CLK_EN_REG 0 0 OVRD_MPLLAB_EN 0 0 WORD_CLK_EN_REG 0 0 OVRD_WORD_CLK_EN 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR1_LANE3_ANA_TX_MISC1 2 0x13ea 8 0 4294967295 MEAS_ATB_CAL_CLK_ALIGN 0 0 OVRD_DCC_DAC_CTRL_RANGE 0 0 DCC_DAC_CTRL_RANGE_REG 0 0 OVRD_VREF_SEL 0 0 VREF_SEL_REG 0 0 FORCE_ATB_TXM 0 0 FORCE_ATB_TXP 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR1_LANE3_ANA_TX_MISC2 2 0x13eb 8 0 4294967295 TX_PEAKING_LVL 0 0 VREG_CP_GAIN_CTRL 0 0 TX_SLEW_EN 0 0 EN_INV_POST 0 0 EN_INV_PRE 0 0 TX_VREG_EN_BYP 0 0 TX_VDRIVER_PULLDN_EN 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR1_LANE3_ANA_TX_MISC3 2 0x13ec 4 0 4294967295 TX_VREG_OVRD_RING_CTRL 0 0 TX_DCC_LOWV 0 0 NC7_2 2 7 RESERVED_15_8 8 15 ixDPCSSYS_CR1_LANE3_ANA_TX_RESERVED2 2 0x13ed 2 0 4294967295 NC7_0 0 7 RESERVED_15_8 8 15 ixDPCSSYS_CR1_LANE3_ANA_TX_RESERVED3 2 0x13ee 2 0 4294967295 NC7_0 0 7 RESERVED_15_8 8 15 ixDPCSSYS_CR1_LANE3_ANA_TX_RESERVED4 2 0x13ef 2 0 4294967295 NC7_0 0 7 RESERVED_15_8 8 15 ixDPCSSYS_CR1_RAWCMN_DIG_CMN_CTL 2 0x2000 2 0 4294967295 PHY_FUNC_RST 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR1_RAWCMN_DIG_MPLLA_OVRD_IN 2 0x2001 10 0 4294967295 MPLLA_WORD_DIV2_EN_OVRD_VAL 0 0 MPLLA_WORD_DIV2_EN_OVRD_EN 1 1 MPLLA_TX_CLK_DIV_OVRD_VAL 2 4 MPLLA_TX_CLK_DIV_OVRD_EN 5 5 MPLLA_DIV10_CLK_EN_OVRD_VAL 6 6 MPLLA_DIV10_CLK_EN_OVRD_EN 7 7 MPLLA_DIV8_CLK_EN_OVRD_VAL 8 8 MPLLA_DIV8_CLK_EN_OVRD_EN 9 9 MPLLA_BW_OVRD_EN 10 10 RESERVED_15_11 11 15 ixDPCSSYS_CR1_RAWCMN_DIG_MPLLA_BW_OVRD_IN 2 0x2002 1 0 4294967295 MPLLA_BW_OVRD_VAL 0 15 ixDPCSSYS_CR1_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_0 2 0x2003 7 0 4294967295 MPLLA_SSC_RANGE_OVRD_VAL 0 2 MPLLA_SSC_RANGE_OVRD_EN 3 3 MPLLA_SSC_CLK_SEL_OVRD_VAL 4 6 MPLLA_SSC_CLK_SEL_OVRD_EN 7 7 MPLLA_SSC_EN_OVRD_VAL 8 8 MPLLA_SSC_EN_OVRD_EN 9 9 RESERVED_15_10 10 15 ixDPCSSYS_CR1_RAWCMN_DIG_MPLLB_OVRD_IN 2 0x2004 10 0 4294967295 MPLLB_WORD_DIV2_EN_OVRD_VAL 0 0 MPLLB_WORD_DIV2_EN_OVRD_EN 1 1 MPLLB_TX_CLK_DIV_OVRD_VAL 2 4 MPLLB_TX_CLK_DIV_OVRD_EN 5 5 MPLLB_DIV10_CLK_EN_OVRD_VAL 6 6 MPLLB_DIV10_CLK_EN_OVRD_EN 7 7 MPLLB_DIV8_CLK_EN_OVRD_VAL 8 8 MPLLB_DIV8_CLK_EN_OVRD_EN 9 9 MPLLB_BW_OVRD_EN 10 10 RESERVED_15_11 11 15 ixDPCSSYS_CR1_RAWCMN_DIG_MPLLB_BW_OVRD_IN 2 0x2005 1 0 4294967295 MPLLB_BW_OVRD_VAL 0 15 ixDPCSSYS_CR1_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_0 2 0x2006 7 0 4294967295 MPLLB_SSC_RANGE_OVRD_VAL 0 2 MPLLB_SSC_RANGE_OVRD_EN 3 3 MPLLB_SSC_CLK_SEL_OVRD_VAL 4 6 MPLLB_SSC_CLK_SEL_OVRD_EN 7 7 MPLLB_SSC_EN_OVRD_VAL 8 8 MPLLB_SSC_EN_OVRD_EN 9 9 RESERVED_15_10 10 15 ixDPCSSYS_CR1_RAWCMN_DIG_LANE_FSM_OP_XTND 2 0x2007 2 0 4294967295 DATA 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR1_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_1 2 0x2008 3 0 4294967295 MPLLA_FRACN_CTRL_OVRD_VAL 0 10 MPLLA_FRACN_CTRL_OVRD_EN 11 11 RESERVED_15_12 12 15 ixDPCSSYS_CR1_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_1 2 0x2009 3 0 4294967295 MPLLB_FRACN_CTRL_OVRD_VAL 0 10 MPLLB_FRACN_CTRL_OVRD_EN 11 11 RESERVED_15_12 12 15 ixDPCSSYS_CR1_RAWCMN_DIG_CMN_CTL_1 2 0x200a 13 0 4294967295 MPLLA_INIT_CAL_DISABLE_OVRD_VAL 0 0 MPLLA_INIT_CAL_DISABLE_OVRD_EN 1 1 MPLLB_INIT_CAL_DISABLE_OVRD_VAL 2 2 MPLLB_INIT_CAL_DISABLE_OVRD_EN 3 3 RTUNE_REQ_OVRD_VAL 4 4 RTUNE_REQ_OVRD_EN 5 5 HDMIMODE_ENABLE_OVRD_VAL 6 6 HDMIMODE_ENABLE_OVRD_EN 7 7 TX_PWM_CLK_SEL_OVRD_VAL 8 9 TX_PWM_CLK_SEL_OVRD_EN 10 10 TX_PWM_CLK_EN_OVRD_VAL 11 11 TX_PWM_CLK_EN_OVRD_EN 12 12 RESERVED_15_13 13 15 ixDPCSSYS_CR1_RAWCMN_DIG_MPLL_STATE_CTL 2 0x200b 8 0 4294967295 MPLL_OFF_TIME 0 5 MPLLA_STATE 6 6 MPLLB_STATE 7 7 MPLL_STATE_OVRD_OUT_EN 8 8 MPLL_FORCE_ON_TIME 9 12 MPLLB_BANK_SEL 13 13 MPLLA_BANK_SEL 14 14 RESERVED_15_15 15 15 ixDPCSSYS_CR1_RAWCMN_DIG_TX_CAL_CODE 2 0x200c 2 0 4294967295 DATA 0 0 RESERVED_15_4 4 15 ixDPCSSYS_CR1_RAWCMN_DIG_SRAM_INIT_DONE 2 0x200d 2 0 4294967295 DATA 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR1_RAWCMN_DIG_OCLA 2 0x200e 3 0 4294967295 DIV2_CLK_EN 0 0 TCA_OCLA_PROBE_SEL 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR1_RAWCMN_DIG_SUP_ANA_OVRD 2 0x200f 7 0 4294967295 REF_ALT_CLK_LP_SEL_OVRD_EN 0 0 REF_ALT_CLK_LP_SEL_OVRD_VAL 1 1 SUP_PRE_HP_OVRD_EN 2 2 SUP_PRE_HP_OVRD_VAL 3 3 SUP_RX_VCO_VREF_SEL_OVRD_EN 4 4 SUP_RX_VCO_VREF_SEL_OVRD_VAL 5 7 RESERVED_15_8 8 15 ixDPCSSYS_CR1_RAWCMN_DIG_PCS_RAW_ID_CODE 2 0x2010 1 0 4294967295 DATA 0 0 ixDPCSSYS_CR1_RAWCMN_DIG_FW_ID_CODE_1 2 0x2011 1 0 4294967295 W_ID_CODE_1 0 15 ixDPCSSYS_CR1_RAWCMN_DIG_FW_ID_CODE_2 2 0x2012 1 0 4294967295 W_ID_CODE_2 0 15 ixDPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_0 2 0x2020 2 0 4294967295 RTUNE_RX_VAL_0 0 5 RESERVED_15_6 6 15 ixDPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_0 2 0x2021 2 0 4294967295 RTUNE_TXDN_VAL_0 0 9 RESERVED_15_10 10 15 ixDPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_0 2 0x2022 2 0 4294967295 RTUNE_TXUP_VAL_0 0 9 RESERVED_15_10 10 15 ixDPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_1 2 0x2023 2 0 4294967295 RTUNE_RX_VAL_1 0 5 RESERVED_15_6 6 15 ixDPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_1 2 0x2024 2 0 4294967295 RTUNE_TXDN_VAL_1 0 9 RESERVED_15_10 10 15 ixDPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_1 2 0x2025 2 0 4294967295 RTUNE_TXUP_VAL_1 0 9 RESERVED_15_10 10 15 ixDPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_2 2 0x2026 2 0 4294967295 RTUNE_RX_VAL_2 0 5 RESERVED_15_6 6 15 ixDPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_2 2 0x2027 2 0 4294967295 RTUNE_TXDN_VAL_2 0 9 RESERVED_15_10 10 15 ixDPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_2 2 0x2028 2 0 4294967295 RTUNE_TXUP_VAL_2 0 9 RESERVED_15_10 10 15 ixDPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_3 2 0x2029 2 0 4294967295 RTUNE_RX_VAL_3 0 5 RESERVED_15_6 6 15 ixDPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_3 2 0x202a 2 0 4294967295 RTUNE_TXDN_VAL_3 0 9 RESERVED_15_10 10 15 ixDPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_3 2 0x202b 2 0 4294967295 RTUNE_TXUP_VAL_3 0 9 RESERVED_15_10 10 15 ixDPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_4 2 0x202c 2 0 4294967295 RTUNE_RX_VAL_4 0 5 RESERVED_15_6 6 15 ixDPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_4 2 0x202d 2 0 4294967295 RTUNE_TXDN_VAL_4 0 9 RESERVED_15_10 10 15 ixDPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_4 2 0x202e 2 0 4294967295 RTUNE_TXUP_VAL_4 0 9 RESERVED_15_10 10 15 ixDPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_5 2 0x202f 2 0 4294967295 RTUNE_RX_VAL_5 0 5 RESERVED_15_6 6 15 ixDPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_5 2 0x2030 2 0 4294967295 RTUNE_TXDN_VAL_5 0 9 RESERVED_15_10 10 15 ixDPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_5 2 0x2031 2 0 4294967295 RTUNE_TXUP_VAL_5 0 9 RESERVED_15_10 10 15 ixDPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_6 2 0x2032 2 0 4294967295 RTUNE_RX_VAL_6 0 5 RESERVED_15_6 6 15 ixDPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_6 2 0x2033 2 0 4294967295 RTUNE_TXDN_VAL_6 0 9 RESERVED_15_10 10 15 ixDPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_6 2 0x2034 2 0 4294967295 RTUNE_TXUP_VAL_6 0 9 RESERVED_15_10 10 15 ixDPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_7 2 0x2035 2 0 4294967295 RTUNE_RX_VAL_7 0 5 RESERVED_15_6 6 15 ixDPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_7 2 0x2036 2 0 4294967295 RTUNE_TXDN_VAL_7 0 9 RESERVED_15_10 10 15 ixDPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_7 2 0x2037 2 0 4294967295 RTUNE_TXUP_VAL_7 0 9 RESERVED_15_10 10 15 ixDPCSSYS_CR1_RAWCMN_DIG_AON_CMN_SRAM_BL_CFG 2 0x2038 5 0 4294967295 SRAM_PGATE_BL_EN 0 0 SRAM_BL_ROM 1 1 SRAM_BL_BYPASS 2 2 SRAM_BL_START 3 3 RESERVED_15_4 4 15 ixDPCSSYS_CR1_RAWCMN_DIG_AON_CMN_PG_OVRD_IN 2 0x2039 7 0 4294967295 PMA_PWR_STABLE_OVRD 0 0 PCS_PWR_STABLE_OVRD 1 1 PG_RESET_OVRD_VAL 2 2 PG_RESET_OVRD_EN 3 3 PG_MODE_EN_OVRD_VAL 4 4 PG_MODE_EN_OVRD_EN 5 5 RESERVED_15_6 6 15 ixDPCSSYS_CR1_RAWCMN_DIG_AON_CMN_PG_OVRD_OUT 2 0x203a 8 0 4294967295 PMA_PWR_EN_OVRD 0 0 PCS_PWR_EN_OVRD 1 1 MON_IN_VALID_OVRD_VAL 2 2 MON_IN_VALID_OVRD_EN 3 3 MON_IN_PULL_DOWN 4 4 ANA_ISOLATION_EN_OVRD_EN 5 5 ANA_ISOLATION_EN_OVRD_VAL 6 6 RESERVED_15_7 7 15 ixDPCSSYS_CR1_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN 2 0x203b 11 0 4294967295 MPLLA_FORCE_EN_OVRD_VAL 0 0 MPLLA_FORCE_EN_OVRD_EN 1 1 MPLLB_FORCE_EN_OVRD_VAL 2 2 MPLLB_FORCE_EN_OVRD_EN 3 3 REF_CLK_EN_OVRD_VAL 4 4 REF_CLK_EN_OVRD_EN 5 5 MPLLA_FORCE_ACK_OVRD_VAL 6 6 MPLLA_FORCE_ACK_OVRD_EN 7 7 MPLLB_FORCE_ACK_OVRD_VAL 8 8 MPLLB_FORCE_ACK_OVRD_EN 9 9 RESERVED_15_10 10 15 ixDPCSSYS_CR1_RAWCMN_DIG_AON_CMN_VREF_STATS 2 0x203c 3 0 4294967295 SUP_ANA_VPHUD_SELVPH 0 0 VREF_CAL_DONE 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RES_OVRD_IN 2 0x203d 8 0 4294967295 RES_REQ_IN 0 0 RES_ACK_IN 1 1 RES_OVRD_EN 2 2 RES_REQ_OUT 3 3 RES_REQ_OUT_OVRD_EN 4 4 RES_ACK_OUT 5 5 RES_ACK_OUT_OVRD_EN 6 6 RESERVED_15_7 7 15 ixDPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RES_ASIC_IN_OUT 2 0x203e 5 0 4294967295 RES_REQ_IN 0 0 RES_REQ_OUT 1 1 RES_ACK_IN 2 2 RES_ACK_OUT 3 3 RESERVED_15_4 4 15 ixDPCSSYS_CR1_RAWCMN_DIG_AON_CMN_REF_RANGE_OVRD 2 0x203f 3 0 4294967295 OVRD_VAL 0 4 OVRD_EN 5 5 RESERVED_15_6 6 15 ixDPCSSYS_CR1_RAWCMN_DIG_AON_CMN_MISC_CONF_IN_1 2 0x2040 2 0 4294967295 MPLL_PWRDN_TIME 0 9 RESERVED_15_10 10 15 ixDPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN 2 0x3000 12 0 4294967295 PSTATE 0 1 LPD 2 2 WIDTH 3 4 RATE 5 7 MPLLB_SEL 8 8 MPLL_EN 9 9 OVRD_EN 10 10 MSTR_MPLLA_STATE 11 11 MSTR_MPLLB_STATE 12 12 MSTR_MPLL_OVRD_EN 13 13 TX_ASYNC_EN_OVR_VAL 14 14 TX_ASYNC_EN_OVR_EN 15 15 ixDPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1 2 0x3001 13 0 4294967295 RESET_OVRD_VAL 0 0 RESET_OVRD_EN 1 1 REQ_OVRD_VAL 2 2 REQ_OVRD_EN 3 3 DETRX_REQ_OVRD_VAL 4 4 DETRX_REQ_OVRD_EN 5 5 VBOOST_EN_OVRD_VAL 6 6 VBOOST_EN_OVRD_EN 7 7 IBOOST_LVL_OVRD_VAL 8 11 IBOOST_LVL_OVRD_EN 12 12 TX_BEACON_EN_OVR_VAL 13 13 TX_BEACON_EN_OVR_EN 14 14 RESERVED_15_15 15 15 ixDPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_PCS_IN 2 0x3002 12 0 4294967295 RESET 0 0 REQ 1 1 PSTATE 2 3 LPD 4 4 WIDTH 5 6 RATE 7 9 MPLLB_SEL 10 10 MPLL_EN 11 11 MSTR_MPLLA_STATE 12 12 MSTR_MPLLB_STATE 13 13 DETRX_REQ 14 14 RESERVED_15_15 15 15 ixDPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_OVRD_OUT 2 0x3003 6 0 4294967295 ACK 0 0 DETRX_RESULT 1 1 EN_CTL 2 2 TX_DWORD_CLK_SYNC_OVRD_VAL 3 3 TX_DWORD_CLK_SYNC_OVRD_EN 4 4 RESERVED_15_5 5 15 ixDPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_PCS_OUT 2 0x3004 2 0 4294967295 ACK 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN 2 0x3005 12 0 4294967295 RATE 0 1 WIDTH 2 3 PSTATE 4 5 LPD 6 6 OVRD_EN 7 7 ADAPT_AFE_EN 8 8 ADAPT_DFE_EN 9 9 LANE_RX2TX_PAR_LB_EN_OVRD_VAL 10 10 LANE_RX2TX_PAR_LB_EN_OVRD_EN 11 11 RX_DATA_EN_OVRD_VAL_R 12 12 RX_DATA_EN_OVRD_EN_R 13 13 RESERVED_15_14 14 15 ixDPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1 2 0x3006 12 0 4294967295 RESET_OVRD_VAL 0 0 RESET_OVRD_EN 1 1 REQ_OVRD_VAL 2 2 REQ_OVRD_EN 3 3 RX_LOS_THRSHLD_OVRD_VAL 4 6 RX_LOS_THRSHLD_OVRD_EN 7 7 ADAPT_REQ 8 8 ADAPT_REQ_OVRD_EN 9 9 ADAPT_CONT 10 10 OFFCAN_CONT 11 11 CONT_OVRD_EN 12 12 RESERVED_15_13 13 15 ixDPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_2 2 0x3007 4 0 4294967295 VCO_LD_VAL_OVRD 0 12 VCO_LD_VAL_OVRD_EN 13 13 VCO_LOWFREQ_VAL_OVRD 14 14 VCO_LOWFREQ_VAL_OVRD_EN 15 15 ixDPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_3 2 0x3008 3 0 4294967295 REF_LD_VAL_OVRD 0 6 REF_LD_VAL_OVRD_EN 7 7 RESERVED_15_8 8 15 ixDPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_PCS_IN 2 0x3009 13 0 4294967295 REQ 0 0 RATE 1 2 WIDTH 3 4 PSTATE 5 6 LPD 7 7 CDR_VCO_LOWFREQ 8 8 ADAPT_AFE_EN 9 9 ADAPT_DFE_EN 10 10 ADAPT_REQ 11 11 ADAPT_CONT 12 12 OFFCAN_CONT 13 13 RESET 14 14 RESERVED_15_15 15 15 ixDPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_1 2 0x300a 2 0 4294967295 REF_LD_VAL 0 6 RESERVED_15_7 7 15 ixDPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_2 2 0x300b 2 0 4294967295 VCO_LD_VAL 0 12 RESERVED_15_13 13 15 ixDPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_3 2 0x300c 4 0 4294967295 EQ_ATT_LVL 0 2 EQ_VGA1_GAIN 3 6 EQ_VGA2_GAIN 7 10 EQ_CTLE_BOOST 11 15 ixDPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_4 2 0x300d 3 0 4294967295 EQ_CTLE_POLE 0 2 EQ_DFE_TAP1 3 10 RESERVED_15_11 11 15 ixDPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT 2 0x300e 3 0 4294967295 ACK 0 0 EN_CTL 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_PCS_OUT 2 0x300f 2 0 4294967295 ACK 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_ADAPT_ACK 2 0x3010 2 0 4294967295 RX_ADAPT_ACK 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_ADAPT_FOM 2 0x3011 2 0 4294967295 RX_ADAPT_FOM 0 7 RESERVED_15_8 8 15 ixDPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_TXPRE_DIR 2 0x3012 2 0 4294967295 RX_TXPRE_DIR 0 1 RESERVED_15_2 2 15 ixDPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_TXMAIN_DIR 2 0x3013 2 0 4294967295 RX_TXMAIN_DIR 0 1 RESERVED_15_2 2 15 ixDPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_TXPOST_DIR 2 0x3014 2 0 4294967295 RX_TXPOST_DIR 0 1 RESERVED_15_2 2 15 ixDPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_LANE_NUMBER 2 0x3015 2 0 4294967295 LANE_NUMBER 0 3 RESERVED_15_4 4 15 ixDPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RESERVED_1 2 0x3016 1 0 4294967295 RESERVED_REG_1 0 15 ixDPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RESERVED_2 2 0x3017 1 0 4294967295 RESERVED_REG_2 0 15 ixDPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN 2 0x3018 16 0 4294967295 RX_RESET_ATE_OVRD_VAL 0 0 RX_RESET_ATE_OVRD_EN 1 1 TX_RESET_ATE_OVRD_VAL 2 2 TX_RESET_ATE_OVRD_EN 3 3 RX_REQ_ATE_OVRD_VAL 4 4 RX_REQ_ATE_OVRD_EN 5 5 TX_REQ_ATE_OVRD_VAL 6 6 TX_REQ_ATE_OVRD_EN 7 7 RX_ADAPT_AFE_EN_OVRD_VAL 8 8 RX_ADAPT_AFE_EN_OVRD_EN 9 9 RX_ADAPT_DFE_EN_OVRD_VAL 10 10 RX_ADAPT_DFE_EN_OVRD_EN 11 11 TX_DATA_EN_ATE_OVRD_VAL 12 12 TX_DATA_EN_ATE_OVRD_EN 13 13 RX_DATA_EN_ATE_OVRD_VAL 14 14 RX_DATA_EN_ATE_OVRD_EN 15 15 ixDPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN 2 0x3019 3 0 4294967295 RX_EQ_DELTA_IQ_OVRD_VAL 0 3 RX_EQ_DELTA_IQ_OVRD_EN 4 4 RESERVED_15_5 5 15 ixDPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN 2 0x301a 5 0 4294967295 RX_TERM_CTRL_OVRD_VAL 0 2 RX_TERM_CTRL_OVRD_EN 3 3 TX_TERM_CTRL_OVRD_VAL 4 6 TX_TERM_CTRL_OVRD_EN 7 7 RESERVED_15_8 8 15 ixDPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TXRX_TERM_CTRL_IN 2 0x301b 3 0 4294967295 RX_TERM_CTRL 0 2 TX_TERM_CTRL 3 5 RESERVED_15_6 6 15 ixDPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT_1 2 0x301c 2 0 4294967295 RX_CLK_EN 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_EQ_OVRD_IN_1 2 0x301d 4 0 4294967295 RX_EQ_AFE_GAIN_OVRD_VAL 0 3 RX_EQ_ATT_LVL_OVRD_VAL 4 6 RX_EQ_OVRD_EN 7 7 RESERVED_15_8 8 15 ixDPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_EQ_OVRD_IN_2 2 0x301e 3 0 4294967295 RX_EQ_DFE_TAP1_OVRD_VAL 0 7 RX_EQ_CTLE_BOOST_OVRD_VAL 8 12 RESERVED_15_13 13 15 ixDPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_PH2_CAL 2 0x301f 4 0 4294967295 PH2_CAL_ACK_VAL 0 0 PH2_CAL_REQ_VAL 1 1 PH2_CAL_REQ_OVRD_VAL 2 2 RESERVED_15_3 3 15 ixDPCSSYS_CR1_RAWLANE0_DIG_FSM_FSM_OVRD_CTL 2 0x3020 5 0 4294967295 FSM_JMP_ADDR 0 11 FSM_JMP_EN 12 12 FSM_CMD_START 13 13 FSM_OVRD_EN 14 14 FSM_BREAK 15 15 ixDPCSSYS_CR1_RAWLANE0_DIG_FSM_MEM_ADDR_MON 2 0x3021 1 0 4294967295 MEM_ADDR 0 15 ixDPCSSYS_CR1_RAWLANE0_DIG_FSM_STATUS_MON 2 0x3022 8 0 4294967295 STATE 0 4 CMD_RDY 5 5 ALU_OVFLW 6 6 ALU_RES_EQ0 7 7 WAIT_CNT_EQ0 8 8 WRMSK_DISABLED 9 9 RDMSK_DISABLED 10 10 RESERVED_15_11 11 15 ixDPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_RX_STARTUP_CAL 2 0x3023 2 0 4294967295 FAST_RX_STARTUP_CAL 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_RX_ADAPT 2 0x3024 2 0 4294967295 FAST_RX_ADAPT 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_RX_AFE_CAL 2 0x3025 2 0 4294967295 FAST_RX_AFE_CAL 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_RX_DFE_CAL 2 0x3026 2 0 4294967295 FAST_RX_DFE_CAL 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_RX_BYPASS_CAL 2 0x3027 2 0 4294967295 FAST_RX_BYPASS_CAL 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_RX_REFLVL_CAL 2 0x3028 2 0 4294967295 FAST_RX_REFLVL_CAL 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_RX_IQ_CAL 2 0x3029 2 0 4294967295 FAST_RX_IQ_CAL 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_RX_AFE_ADAPT 2 0x302a 2 0 4294967295 FAST_RX_AFE_ADAPT 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_RX_DFE_ADAPT 2 0x302b 2 0 4294967295 FAST_RX_DFE_ADAPT 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_SUP 2 0x302c 2 0 4294967295 FAST_SUP 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_TX_CMN_MODE 2 0x302d 2 0 4294967295 FAST_TX_CMN_MODE 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_TX_RXDET 2 0x302e 2 0 4294967295 FAST_TX_RXDET 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_RX_PWRUP 2 0x302f 2 0 4294967295 FAST_RX_PWRUP 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_RX_VCO_WAIT 2 0x3030 2 0 4294967295 FAST_RX_VCO_WAIT 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_RX_VCO_CAL 2 0x3031 2 0 4294967295 FAST_RX_VCO_CAL 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR1_RAWLANE0_DIG_FSM_CMNCAL_MPLL_STATUS 2 0x3032 3 0 4294967295 CMNCAL_MPLL_INIT 0 0 CMNCAL_MPLL_DONE 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_RX_CONT_CAL_ADAPT 2 0x3033 2 0 4294967295 FAST_RX_CONT_CAL_ADAPT 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_RX_CONT_ADAPT 2 0x3034 2 0 4294967295 FAST_RX_CONT_ADAPT 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_RX_CONT_DATA_CAL 2 0x3035 2 0 4294967295 FAST_RX_CONT_DATA_CAL 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_RX_CONT_PHASE_CAL 2 0x3036 2 0 4294967295 FAST_RX_CONT_PHASE_CAL 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_RX_CONT_AFE_CAL 2 0x3037 2 0 4294967295 FAST_RX_CONT_AFE_CAL 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_FLAGS 2 0x3038 12 0 4294967295 TX_FAST_DCC_CAL 0 0 RX_FAST_DCC_CAL 1 1 RX_FAST_VPHUD_CAL 2 2 RX_FAST_VREF_CAL 3 3 RX_FAST_SIGDET_CAL 4 4 RESERVED_2 5 7 TX_FAST_CONT_DCC_CAL 8 8 RX_FAST_CONT_DCC_CAL 9 9 RX_FAST_CONT_VPHUD_CAL 10 10 RX_FAST_CONT_VREF_CAL 11 11 RESERVED_1 12 14 TX_SKIP_SUP_CAL 15 15 ixDPCSSYS_CR1_RAWLANE0_DIG_FSM_CR_LOCK 2 0x3039 3 0 4294967295 CR_REG_LOCK 0 0 CR_MEM_LOCK 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR1_RAWLANE0_DIG_FSM_TX_DCC_FLAGS 2 0x303a 4 0 4294967295 RATE 0 0 DIV 1 1 MPLL 2 2 RESERVED_15_3 3 15 ixDPCSSYS_CR1_RAWLANE0_DIG_FSM_TX_DCC_STATUS 2 0x303b 2 0 4294967295 FLAG 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR1_RAWLANE0_DIG_FSM_OCLA 2 0x303c 4 0 4294967295 PC_EN 0 0 REG_BANK1_EN 1 1 REG_BANK2_EN 2 2 RESERVED_15_3 3 15 ixDPCSSYS_CR1_RAWLANE0_DIG_FSM_TX_EQ_UPDATE_FLAG 2 0x303d 2 0 4294967295 TX_EQ_UPDATE_FLAG 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR1_RAWLANE0_DIG_FSM_CMNCAL_RCAL_STATUS 2 0x303e 3 0 4294967295 CMNCAL_RCAL_INIT 0 0 CMNCAL_RCAL_DONE 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR1_RAWLANE0_DIG_FSM_RX_IQ_PHASE_OFFSET 2 0x303f 2 0 4294967295 RX_IQ_PHASE_OFFSET 0 3 RESERVED_15_4 4 15 ixDPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_RESET_RTN_REQ 2 0x3040 2 0 4294967295 RESET_RTN_REQ 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_RX_RESET_IRQ 2 0x3041 2 0 4294967295 RX_RESET 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_RX_REQ_IRQ 2 0x3042 2 0 4294967295 RX_REQ 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_RX_RATE_IRQ 2 0x3043 2 0 4294967295 RX_RATE_IRQ 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_RX_PSTATE_IRQ 2 0x3044 2 0 4294967295 RX_PSTATE_IRQ 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ 2 0x3045 2 0 4294967295 RX_ADAPT_REQ_IRQ 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ 2 0x3046 2 0 4294967295 RX_ADAPT_DIS_IRQ 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_RX_RESET_IRQ_CLR 2 0x3047 2 0 4294967295 RX_RESET_IRQ_CLR 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_RX_REQ_IRQ_CLR 2 0x3048 2 0 4294967295 RX_REQ_IRQ_CLR 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_RX_RATE_IRQ_CLR 2 0x3049 2 0 4294967295 RX_RATE_IRQ_CLR 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR 2 0x304a 2 0 4294967295 RX_PSTATE_IRQ_CLR 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR 2 0x304b 2 0 4294967295 RX_ADAPT_REQ_IRQ_CLR 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR 2 0x304c 2 0 4294967295 RX_ADAPT_DIS_IRQ_CLR 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK 2 0x304d 12 0 4294967295 RX_REQ_IRQ_MSK 0 0 RX_RATE_IRQ_MSK 1 1 RX_PSTATE_IRQ_MSK 2 2 RX_ADAPT_REQ_IRQ_MSK 3 3 RX_ADAPT_DIS_IRQ_MSK 4 4 RX_RESET_IRQ_MSK 5 5 LANE_XCVR_MODE_IRQ_MSK 6 6 RX_PH2_CAL_REQ_IRQ_MSK 7 7 RX_PH2_CAL_DIS_IRQ_MSK 8 8 LANE_RX2TX_SER_LB_EN_IRQ_MSK 9 9 DCC_ONDMD_IRQ_MSK 10 10 RESERVED_15_11 11 15 ixDPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK_2 2 0x304e 3 0 4294967295 TX_RESET_IRQ_MSK 0 0 TX_REQ_IRQ_MSK 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ 2 0x304f 2 0 4294967295 LANE_XCVR_MODE_IRQ 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR 2 0x3050 2 0 4294967295 LANE_XCVR_MODE_IRQ_CLR 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ 2 0x3051 2 0 4294967295 RX_PH2_CAL_REQ_IRQ 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ 2 0x3052 2 0 4294967295 RX_PH2_CAL_DIS_IRQ 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR 2 0x3053 2 0 4294967295 RX_PH2_CAL_REQ_IRQ_CLR 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR 2 0x3054 2 0 4294967295 RX_PH2_CAL_DIS_IRQ_CLR 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ 2 0x3055 2 0 4294967295 LANE_RX2TX_SER_LB_EN_IRQ 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR 2 0x3056 2 0 4294967295 LANE_RX2TX_SER_LB_EN_IRQ_CLR 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_DCC_ONDMD_IRQ 2 0x3057 2 0 4294967295 IRQ 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_TX_RESET_IRQ 2 0x3058 2 0 4294967295 TX_RESET 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_TX_REQ_IRQ 2 0x3059 2 0 4294967295 TX_REQ 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_TX_RESET_IRQ_CLR 2 0x305a 2 0 4294967295 TX_RESET_IRQ_CLR 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_TX_REQ_IRQ_CLR 2 0x305b 2 0 4294967295 TX_REQ_IRQ_CLR 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_LANE_OVRD_IN 2 0x3060 4 0 4294967295 LANE_MPLLA_EN_IN 0 0 LANE_MPLLB_EN_IN 1 1 LANE_OVRD_EN 2 2 RESERVED_15_3 3 15 ixDPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_LANE_OVRD_OUT 2 0x3061 4 0 4294967295 LANE_MPLLA_EN_OUT 0 0 LANE_MPLLB_EN_OUT 1 1 LANE_OVRD_EN 2 2 RESERVED_15_3 3 15 ixDPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_SUP_OVRD_IN 2 0x3062 4 0 4294967295 MPLLA_STATE 0 0 MPLLB_STATE 1 1 SUP_STATE_OVRD_EN 2 2 RESERVED_15_3 3 15 ixDPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_SUP_PMA_IN 2 0x3063 3 0 4294967295 MPLLA_STATE 0 0 MPLLB_STATE 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT 2 0x3064 16 0 4294967295 TX_REQ_OVRD_VAL 0 0 TX_REQ_OVRD_EN 1 1 TX_RESET_OVRD_VAL 2 2 TX_RESET_OVRD_EN 3 3 TX_BEACON_EN_OVRD_VAL 4 4 TX_BEACON_EN_OVRD_EN 5 5 TX_ASYNC_DRV_EN_OVRD_VAL 6 6 TX_ASYNC_DRV_EN_OVRD_EN 7 7 TX_ASYNC_EN_OVRD_VAL 8 8 TX_ASYNC_EN_OVRD_EN 9 9 TX_DWORD_CLK_SYNC_OVRD_VAL 10 10 TX_DWORD_CLK_SYNC_OVRD_EN 11 11 LANE_TX2RX_SER_LB_EN_OVRD_VAL 12 12 LANE_TX2RX_SER_LB_EN_OVRD_EN 13 13 TX_PMA_DATA_EN_OVRD_VAL_R 14 14 TX_PMA_DATA_EN_OVRD_EN_R 15 15 ixDPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_TX_PMA_IN 2 0x3065 2 0 4294967295 ACK 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT 2 0x3066 9 0 4294967295 RX_REQ_OVRD_VAL 0 0 RX_REQ_OVRD_EN 1 1 RX_RESET_OVRD_VAL 2 2 RX_RESET_OVRD_EN 3 3 LANE_RX2TX_PAR_LB_EN_OVRD_VAL 4 4 LANE_RX2TX_PAR_LB_EN_OVRD_EN 5 5 RX_PMA_DATA_EN_OVRD_VAL_R 6 6 RX_PMA_DATA_EN_OVRD_EN_R 7 7 RESERVED_15_8 8 15 ixDPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_RX_PMA_IN 2 0x3067 2 0 4294967295 ACK 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_LANE_RTUNE_CTL 2 0x3068 2 0 4294967295 LANE_RTUNE_REQ 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_SUP_PMA_IN_1 2 0x3069 2 0 4294967295 RTUNE_ACK 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_IN 2 0x306a 9 0 4294967295 RX_PMA_PWM_WORD_CLK_R 0 0 RX_PMA_PWM_WORD_CLK_OVRD_EN 1 1 RX_PMA_PWM_DATA_R 2 2 RX_PMA_PWM_DATA_OVRD_EN 3 3 RX_PMA_PWM_CLK_R 4 4 RX_PMA_PWM_CLK_OVRD_EN 5 5 RX_PMA_TERM_CTL_R 6 7 RX_PMA_TERM_CTL_OVRD_EN 8 8 RESERVED_15_9 9 15 ixDPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_OUT 2 0x306b 7 0 4294967295 RX_PMA_PWM_EN 0 0 RX_PMA_PWM_EN_OVRD_EN 1 1 RX_PMA_PWM_CLK_SEL 2 3 RX_PMA_PWM_CLK_SEL_OVRD_EN 4 4 RX_PMA_ASYNC_EN 5 5 RX_PMA_ASYNC_EN_OVRD_EN 6 6 RESERVED_15_7 7 15 ixDPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_RX_ADAPT_OVRD_OUT 2 0x306c 3 0 4294967295 RX_PMA_IQ_PHASE_ADJUST_MAP_OVRD_VAL 0 6 RX_PMA_IQ_PHASE_ADJUST_MAP_OVRD_EN 7 7 RESERVED_15_8 8 15 ixDPCSSYS_CR1_RAWLANE0_DIG_TX_CTL_TX_FSM_CTL 2 0x3080 6 0 4294967295 TX_WAIT_MPLL_OFF_TIME 0 6 TX_P2_ALLOW_RXDET 7 7 TX_P1_ALLOW_RXDET 8 8 TX_P0S_ALLOW_RXDET 9 9 TX_P0_ALLOW_RXDET 10 10 RESERVED_15_11 11 15 ixDPCSSYS_CR1_RAWLANE0_DIG_TX_CTL_TX_CLK_CTL 2 0x3081 4 0 4294967295 TX_CLK_EN 0 0 TX_CLK_SEL 1 4 ASYNC_BEACON_WAIT_TIME 5 10 RESERVED_15_11 11 15 ixDPCSSYS_CR1_RAWLANE0_DIG_TX_CTL_TX_DCC_CONT_STATUS 2 0x3082 2 0 4294967295 ENABLE 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR1_RAWLANE0_DIG_TX_CTL_OCLA 2 0x3083 2 0 4294967295 FSM_EN 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR1_RAWLANE0_DIG_TX_CTL_UPCS_OCLA 2 0x3084 3 0 4294967295 DATA_EN 0 1 CLK_EN 2 2 RESERVED_15_3 3 15 ixDPCSSYS_CR1_RAWLANE0_DIG_RX_CTL_RX_FSM_CTL 2 0x30a0 3 0 4294967295 EN_RX_CTL_FSM 0 0 RATE_CHG_IN_P1 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR1_RAWLANE0_DIG_RX_CTL_RX_LOS_MASK_CTL 2 0x30a1 2 0 4294967295 RX_LOS_MASK_CNT 0 8 RESERVED_15_9 9 15 ixDPCSSYS_CR1_RAWLANE0_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL 2 0x30a2 2 0 4294967295 RX_DATA_EN_OVRD_CNT 0 4 INT_REF_TRCK_CNT 5 15 ixDPCSSYS_CR1_RAWLANE0_DIG_RX_CTL_OFFCAN_CONT_STATUS 2 0x30a3 2 0 4294967295 ENABLE 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR1_RAWLANE0_DIG_RX_CTL_ADAPT_CONT_STATUS 2 0x30a4 2 0 4294967295 ENABLE 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR1_RAWLANE0_DIG_RX_CTL_UPCS_OCLA 2 0x30a5 3 0 4294967295 DATA_EN 0 2 CLK_EN 3 3 RESERVED_15_4 4 15 ixDPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN 2 0x30c0 11 0 4294967295 RATE_OVRD_VAL 0 1 RATE_OVRD_EN 2 2 WIDTH_OVRD_VAL 3 4 WIDTH_OVRD_EN 5 5 PSTATE_OVRD_VAL 6 7 PSTATE_OVRD_EN 8 8 LPD_OVRD_VAL 9 9 LPD_OVRD_EN 10 10 LANE_RX2TX_PAR_LB_EN_OVRD_VAL 11 11 LANE_RX2TX_PAR_LB_EN_OVRD_EN 12 12 RESERVED_15_13 13 15 ixDPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN 2 0x30c1 12 0 4294967295 PSTATE 0 1 LPD 2 2 WIDTH 3 4 RATE 5 7 MPLLB_SEL 8 8 MPLL_EN 9 9 OVRD_EN 10 10 MSTR_MPLLA_STATE 11 11 MSTR_MPLLB_STATE 12 12 MSTR_MPLL_OVRD_EN 13 13 TX_ASYNC_EN_OVR_VAL 14 14 TX_ASYNC_EN_OVR_EN 15 15 ixDPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1 2 0x30c2 13 0 4294967295 DETRX_REQ_OVRD_VAL 0 0 DETRX_REQ_OVRD_EN 1 1 VBOOST_EN_OVRD_VAL 2 2 VBOOST_EN_OVRD_EN 3 3 IBOOST_LVL_OVRD_VAL 4 7 IBOOST_LVL_OVRD_EN 8 8 TX_BEACON_EN_OVR_VAL 9 9 TX_BEACON_EN_OVR_EN 10 10 LANE_TX2RX_SER_LB_EN_OVRD_VAL 11 11 LANE_TX2RX_SER_LB_EN_OVRD_EN 12 12 TX_ASYNC_DATA_OVRD_VAL 13 13 TX_ASYNC_DATA_OVRD_EN 14 14 RESERVED_15_15 15 15 ixDPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_MASTER_MPLL_LOOP 2 0x30c3 3 0 4294967295 MPLLB_LOOP_EN 0 0 MPLLA_LOOP_EN 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1 2 0x30c4 11 0 4294967295 RESERVED 0 1 RX_LOS_LFPS_EN_OVRD_VAL 2 2 RX_LOS_LFPS_EN_OVRD_EN 3 3 RX_LOS_THRSHLD_OVRD_VAL 4 6 RX_LOS_THRSHLD_OVRD_EN 7 7 ADAPT_REQ 8 8 ADAPT_REQ_OVRD_EN 9 9 ADAPT_CONT 10 10 OFFCAN_CONT 11 11 CONT_OVRD_EN 12 12 RESERVED_15_13 13 15 ixDPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_2 2 0x30c5 4 0 4294967295 VCO_LD_VAL_OVRD 0 12 VCO_LD_VAL_OVRD_EN 13 13 VCO_LOWFREQ_VAL_OVRD 14 14 VCO_LOWFREQ_VAL_OVRD_EN 15 15 ixDPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_3 2 0x30c6 3 0 4294967295 REF_LD_VAL_OVRD 0 6 REF_LD_VAL_OVRD_EN 7 7 RESERVED_15_8 8 15 ixDPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT_2 2 0x30c7 3 0 4294967295 RX_VALID 0 0 RX_VALID_OVRD_EN 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_2 2 0x30c8 7 0 4294967295 LANE_TX2RX_SER_LB_EN_OVRD_VAL 0 0 LANE_TX2RX_SER_LB_EN_OVRD_EN 1 1 TX_DATA_EN_OVRD_VAL_R 2 2 TX_DATA_EN_OVRD_EN_R 3 3 TX_ASYNC_DATA_OVRD_VAL_R 4 4 TX_ASYNC_DATA_OVRD_EN_R 5 5 RESERVED_15_6 6 15 ixDPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN 2 0x3100 12 0 4294967295 PSTATE 0 1 LPD 2 2 WIDTH 3 4 RATE 5 7 MPLLB_SEL 8 8 MPLL_EN 9 9 OVRD_EN 10 10 MSTR_MPLLA_STATE 11 11 MSTR_MPLLB_STATE 12 12 MSTR_MPLL_OVRD_EN 13 13 TX_ASYNC_EN_OVR_VAL 14 14 TX_ASYNC_EN_OVR_EN 15 15 ixDPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1 2 0x3101 13 0 4294967295 RESET_OVRD_VAL 0 0 RESET_OVRD_EN 1 1 REQ_OVRD_VAL 2 2 REQ_OVRD_EN 3 3 DETRX_REQ_OVRD_VAL 4 4 DETRX_REQ_OVRD_EN 5 5 VBOOST_EN_OVRD_VAL 6 6 VBOOST_EN_OVRD_EN 7 7 IBOOST_LVL_OVRD_VAL 8 11 IBOOST_LVL_OVRD_EN 12 12 TX_BEACON_EN_OVR_VAL 13 13 TX_BEACON_EN_OVR_EN 14 14 RESERVED_15_15 15 15 ixDPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_PCS_IN 2 0x3102 12 0 4294967295 RESET 0 0 REQ 1 1 PSTATE 2 3 LPD 4 4 WIDTH 5 6 RATE 7 9 MPLLB_SEL 10 10 MPLL_EN 11 11 MSTR_MPLLA_STATE 12 12 MSTR_MPLLB_STATE 13 13 DETRX_REQ 14 14 RESERVED_15_15 15 15 ixDPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_OVRD_OUT 2 0x3103 6 0 4294967295 ACK 0 0 DETRX_RESULT 1 1 EN_CTL 2 2 TX_DWORD_CLK_SYNC_OVRD_VAL 3 3 TX_DWORD_CLK_SYNC_OVRD_EN 4 4 RESERVED_15_5 5 15 ixDPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_PCS_OUT 2 0x3104 2 0 4294967295 ACK 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN 2 0x3105 12 0 4294967295 RATE 0 1 WIDTH 2 3 PSTATE 4 5 LPD 6 6 OVRD_EN 7 7 ADAPT_AFE_EN 8 8 ADAPT_DFE_EN 9 9 LANE_RX2TX_PAR_LB_EN_OVRD_VAL 10 10 LANE_RX2TX_PAR_LB_EN_OVRD_EN 11 11 RX_DATA_EN_OVRD_VAL_R 12 12 RX_DATA_EN_OVRD_EN_R 13 13 RESERVED_15_14 14 15 ixDPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1 2 0x3106 12 0 4294967295 RESET_OVRD_VAL 0 0 RESET_OVRD_EN 1 1 REQ_OVRD_VAL 2 2 REQ_OVRD_EN 3 3 RX_LOS_THRSHLD_OVRD_VAL 4 6 RX_LOS_THRSHLD_OVRD_EN 7 7 ADAPT_REQ 8 8 ADAPT_REQ_OVRD_EN 9 9 ADAPT_CONT 10 10 OFFCAN_CONT 11 11 CONT_OVRD_EN 12 12 RESERVED_15_13 13 15 ixDPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_2 2 0x3107 4 0 4294967295 VCO_LD_VAL_OVRD 0 12 VCO_LD_VAL_OVRD_EN 13 13 VCO_LOWFREQ_VAL_OVRD 14 14 VCO_LOWFREQ_VAL_OVRD_EN 15 15 ixDPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_3 2 0x3108 3 0 4294967295 REF_LD_VAL_OVRD 0 6 REF_LD_VAL_OVRD_EN 7 7 RESERVED_15_8 8 15 ixDPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_PCS_IN 2 0x3109 13 0 4294967295 REQ 0 0 RATE 1 2 WIDTH 3 4 PSTATE 5 6 LPD 7 7 CDR_VCO_LOWFREQ 8 8 ADAPT_AFE_EN 9 9 ADAPT_DFE_EN 10 10 ADAPT_REQ 11 11 ADAPT_CONT 12 12 OFFCAN_CONT 13 13 RESET 14 14 RESERVED_15_15 15 15 ixDPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_1 2 0x310a 2 0 4294967295 REF_LD_VAL 0 6 RESERVED_15_7 7 15 ixDPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_2 2 0x310b 2 0 4294967295 VCO_LD_VAL 0 12 RESERVED_15_13 13 15 ixDPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_3 2 0x310c 4 0 4294967295 EQ_ATT_LVL 0 2 EQ_VGA1_GAIN 3 6 EQ_VGA2_GAIN 7 10 EQ_CTLE_BOOST 11 15 ixDPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_4 2 0x310d 3 0 4294967295 EQ_CTLE_POLE 0 2 EQ_DFE_TAP1 3 10 RESERVED_15_11 11 15 ixDPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT 2 0x310e 3 0 4294967295 ACK 0 0 EN_CTL 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_PCS_OUT 2 0x310f 2 0 4294967295 ACK 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_ADAPT_ACK 2 0x3110 2 0 4294967295 RX_ADAPT_ACK 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_ADAPT_FOM 2 0x3111 2 0 4294967295 RX_ADAPT_FOM 0 7 RESERVED_15_8 8 15 ixDPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_TXPRE_DIR 2 0x3112 2 0 4294967295 RX_TXPRE_DIR 0 1 RESERVED_15_2 2 15 ixDPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_TXMAIN_DIR 2 0x3113 2 0 4294967295 RX_TXMAIN_DIR 0 1 RESERVED_15_2 2 15 ixDPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_TXPOST_DIR 2 0x3114 2 0 4294967295 RX_TXPOST_DIR 0 1 RESERVED_15_2 2 15 ixDPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_LANE_NUMBER 2 0x3115 2 0 4294967295 LANE_NUMBER 0 3 RESERVED_15_4 4 15 ixDPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RESERVED_1 2 0x3116 1 0 4294967295 RESERVED_REG_1 0 15 ixDPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RESERVED_2 2 0x3117 1 0 4294967295 RESERVED_REG_2 0 15 ixDPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN 2 0x3118 16 0 4294967295 RX_RESET_ATE_OVRD_VAL 0 0 RX_RESET_ATE_OVRD_EN 1 1 TX_RESET_ATE_OVRD_VAL 2 2 TX_RESET_ATE_OVRD_EN 3 3 RX_REQ_ATE_OVRD_VAL 4 4 RX_REQ_ATE_OVRD_EN 5 5 TX_REQ_ATE_OVRD_VAL 6 6 TX_REQ_ATE_OVRD_EN 7 7 RX_ADAPT_AFE_EN_OVRD_VAL 8 8 RX_ADAPT_AFE_EN_OVRD_EN 9 9 RX_ADAPT_DFE_EN_OVRD_VAL 10 10 RX_ADAPT_DFE_EN_OVRD_EN 11 11 TX_DATA_EN_ATE_OVRD_VAL 12 12 TX_DATA_EN_ATE_OVRD_EN 13 13 RX_DATA_EN_ATE_OVRD_VAL 14 14 RX_DATA_EN_ATE_OVRD_EN 15 15 ixDPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN 2 0x3119 3 0 4294967295 RX_EQ_DELTA_IQ_OVRD_VAL 0 3 RX_EQ_DELTA_IQ_OVRD_EN 4 4 RESERVED_15_5 5 15 ixDPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN 2 0x311a 5 0 4294967295 RX_TERM_CTRL_OVRD_VAL 0 2 RX_TERM_CTRL_OVRD_EN 3 3 TX_TERM_CTRL_OVRD_VAL 4 6 TX_TERM_CTRL_OVRD_EN 7 7 RESERVED_15_8 8 15 ixDPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TXRX_TERM_CTRL_IN 2 0x311b 3 0 4294967295 RX_TERM_CTRL 0 2 TX_TERM_CTRL 3 5 RESERVED_15_6 6 15 ixDPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT_1 2 0x311c 2 0 4294967295 RX_CLK_EN 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_EQ_OVRD_IN_1 2 0x311d 4 0 4294967295 RX_EQ_AFE_GAIN_OVRD_VAL 0 3 RX_EQ_ATT_LVL_OVRD_VAL 4 6 RX_EQ_OVRD_EN 7 7 RESERVED_15_8 8 15 ixDPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_EQ_OVRD_IN_2 2 0x311e 3 0 4294967295 RX_EQ_DFE_TAP1_OVRD_VAL 0 7 RX_EQ_CTLE_BOOST_OVRD_VAL 8 12 RESERVED_15_13 13 15 ixDPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_PH2_CAL 2 0x311f 4 0 4294967295 PH2_CAL_ACK_VAL 0 0 PH2_CAL_REQ_VAL 1 1 PH2_CAL_REQ_OVRD_VAL 2 2 RESERVED_15_3 3 15 ixDPCSSYS_CR1_RAWLANE1_DIG_FSM_FSM_OVRD_CTL 2 0x3120 5 0 4294967295 FSM_JMP_ADDR 0 11 FSM_JMP_EN 12 12 FSM_CMD_START 13 13 FSM_OVRD_EN 14 14 FSM_BREAK 15 15 ixDPCSSYS_CR1_RAWLANE1_DIG_FSM_MEM_ADDR_MON 2 0x3121 1 0 4294967295 MEM_ADDR 0 15 ixDPCSSYS_CR1_RAWLANE1_DIG_FSM_STATUS_MON 2 0x3122 8 0 4294967295 STATE 0 4 CMD_RDY 5 5 ALU_OVFLW 6 6 ALU_RES_EQ0 7 7 WAIT_CNT_EQ0 8 8 WRMSK_DISABLED 9 9 RDMSK_DISABLED 10 10 RESERVED_15_11 11 15 ixDPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_RX_STARTUP_CAL 2 0x3123 2 0 4294967295 FAST_RX_STARTUP_CAL 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_RX_ADAPT 2 0x3124 2 0 4294967295 FAST_RX_ADAPT 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_RX_AFE_CAL 2 0x3125 2 0 4294967295 FAST_RX_AFE_CAL 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_RX_DFE_CAL 2 0x3126 2 0 4294967295 FAST_RX_DFE_CAL 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_RX_BYPASS_CAL 2 0x3127 2 0 4294967295 FAST_RX_BYPASS_CAL 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_RX_REFLVL_CAL 2 0x3128 2 0 4294967295 FAST_RX_REFLVL_CAL 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_RX_IQ_CAL 2 0x3129 2 0 4294967295 FAST_RX_IQ_CAL 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_RX_AFE_ADAPT 2 0x312a 2 0 4294967295 FAST_RX_AFE_ADAPT 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_RX_DFE_ADAPT 2 0x312b 2 0 4294967295 FAST_RX_DFE_ADAPT 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_SUP 2 0x312c 2 0 4294967295 FAST_SUP 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_TX_CMN_MODE 2 0x312d 2 0 4294967295 FAST_TX_CMN_MODE 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_TX_RXDET 2 0x312e 2 0 4294967295 FAST_TX_RXDET 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_RX_PWRUP 2 0x312f 2 0 4294967295 FAST_RX_PWRUP 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_RX_VCO_WAIT 2 0x3130 2 0 4294967295 FAST_RX_VCO_WAIT 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_RX_VCO_CAL 2 0x3131 2 0 4294967295 FAST_RX_VCO_CAL 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR1_RAWLANE1_DIG_FSM_CMNCAL_MPLL_STATUS 2 0x3132 3 0 4294967295 CMNCAL_MPLL_INIT 0 0 CMNCAL_MPLL_DONE 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_RX_CONT_CAL_ADAPT 2 0x3133 2 0 4294967295 FAST_RX_CONT_CAL_ADAPT 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_RX_CONT_ADAPT 2 0x3134 2 0 4294967295 FAST_RX_CONT_ADAPT 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_RX_CONT_DATA_CAL 2 0x3135 2 0 4294967295 FAST_RX_CONT_DATA_CAL 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_RX_CONT_PHASE_CAL 2 0x3136 2 0 4294967295 FAST_RX_CONT_PHASE_CAL 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_RX_CONT_AFE_CAL 2 0x3137 2 0 4294967295 FAST_RX_CONT_AFE_CAL 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_FLAGS 2 0x3138 12 0 4294967295 TX_FAST_DCC_CAL 0 0 RX_FAST_DCC_CAL 1 1 RX_FAST_VPHUD_CAL 2 2 RX_FAST_VREF_CAL 3 3 RX_FAST_SIGDET_CAL 4 4 RESERVED_2 5 7 TX_FAST_CONT_DCC_CAL 8 8 RX_FAST_CONT_DCC_CAL 9 9 RX_FAST_CONT_VPHUD_CAL 10 10 RX_FAST_CONT_VREF_CAL 11 11 RESERVED_1 12 14 TX_SKIP_SUP_CAL 15 15 ixDPCSSYS_CR1_RAWLANE1_DIG_FSM_CR_LOCK 2 0x3139 3 0 4294967295 CR_REG_LOCK 0 0 CR_MEM_LOCK 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR1_RAWLANE1_DIG_FSM_TX_DCC_FLAGS 2 0x313a 4 0 4294967295 RATE 0 0 DIV 1 1 MPLL 2 2 RESERVED_15_3 3 15 ixDPCSSYS_CR1_RAWLANE1_DIG_FSM_TX_DCC_STATUS 2 0x313b 2 0 4294967295 FLAG 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR1_RAWLANE1_DIG_FSM_OCLA 2 0x313c 4 0 4294967295 PC_EN 0 0 REG_BANK1_EN 1 1 REG_BANK2_EN 2 2 RESERVED_15_3 3 15 ixDPCSSYS_CR1_RAWLANE1_DIG_FSM_TX_EQ_UPDATE_FLAG 2 0x313d 2 0 4294967295 TX_EQ_UPDATE_FLAG 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR1_RAWLANE1_DIG_FSM_CMNCAL_RCAL_STATUS 2 0x313e 3 0 4294967295 CMNCAL_RCAL_INIT 0 0 CMNCAL_RCAL_DONE 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR1_RAWLANE1_DIG_FSM_RX_IQ_PHASE_OFFSET 2 0x313f 2 0 4294967295 RX_IQ_PHASE_OFFSET 0 3 RESERVED_15_4 4 15 ixDPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_RESET_RTN_REQ 2 0x3140 2 0 4294967295 RESET_RTN_REQ 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_RX_RESET_IRQ 2 0x3141 2 0 4294967295 RX_RESET 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_RX_REQ_IRQ 2 0x3142 2 0 4294967295 RX_REQ 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_RX_RATE_IRQ 2 0x3143 2 0 4294967295 RX_RATE_IRQ 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_RX_PSTATE_IRQ 2 0x3144 2 0 4294967295 RX_PSTATE_IRQ 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ 2 0x3145 2 0 4294967295 RX_ADAPT_REQ_IRQ 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ 2 0x3146 2 0 4294967295 RX_ADAPT_DIS_IRQ 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_RX_RESET_IRQ_CLR 2 0x3147 2 0 4294967295 RX_RESET_IRQ_CLR 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_RX_REQ_IRQ_CLR 2 0x3148 2 0 4294967295 RX_REQ_IRQ_CLR 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_RX_RATE_IRQ_CLR 2 0x3149 2 0 4294967295 RX_RATE_IRQ_CLR 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR 2 0x314a 2 0 4294967295 RX_PSTATE_IRQ_CLR 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR 2 0x314b 2 0 4294967295 RX_ADAPT_REQ_IRQ_CLR 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR 2 0x314c 2 0 4294967295 RX_ADAPT_DIS_IRQ_CLR 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK 2 0x314d 12 0 4294967295 RX_REQ_IRQ_MSK 0 0 RX_RATE_IRQ_MSK 1 1 RX_PSTATE_IRQ_MSK 2 2 RX_ADAPT_REQ_IRQ_MSK 3 3 RX_ADAPT_DIS_IRQ_MSK 4 4 RX_RESET_IRQ_MSK 5 5 LANE_XCVR_MODE_IRQ_MSK 6 6 RX_PH2_CAL_REQ_IRQ_MSK 7 7 RX_PH2_CAL_DIS_IRQ_MSK 8 8 LANE_RX2TX_SER_LB_EN_IRQ_MSK 9 9 DCC_ONDMD_IRQ_MSK 10 10 RESERVED_15_11 11 15 ixDPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK_2 2 0x314e 3 0 4294967295 TX_RESET_IRQ_MSK 0 0 TX_REQ_IRQ_MSK 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ 2 0x314f 2 0 4294967295 LANE_XCVR_MODE_IRQ 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR 2 0x3150 2 0 4294967295 LANE_XCVR_MODE_IRQ_CLR 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ 2 0x3151 2 0 4294967295 RX_PH2_CAL_REQ_IRQ 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ 2 0x3152 2 0 4294967295 RX_PH2_CAL_DIS_IRQ 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR 2 0x3153 2 0 4294967295 RX_PH2_CAL_REQ_IRQ_CLR 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR 2 0x3154 2 0 4294967295 RX_PH2_CAL_DIS_IRQ_CLR 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ 2 0x3155 2 0 4294967295 LANE_RX2TX_SER_LB_EN_IRQ 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR 2 0x3156 2 0 4294967295 LANE_RX2TX_SER_LB_EN_IRQ_CLR 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_DCC_ONDMD_IRQ 2 0x3157 2 0 4294967295 IRQ 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_TX_RESET_IRQ 2 0x3158 2 0 4294967295 TX_RESET 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_TX_REQ_IRQ 2 0x3159 2 0 4294967295 TX_REQ 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_TX_RESET_IRQ_CLR 2 0x315a 2 0 4294967295 TX_RESET_IRQ_CLR 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_TX_REQ_IRQ_CLR 2 0x315b 2 0 4294967295 TX_REQ_IRQ_CLR 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_LANE_OVRD_IN 2 0x3160 4 0 4294967295 LANE_MPLLA_EN_IN 0 0 LANE_MPLLB_EN_IN 1 1 LANE_OVRD_EN 2 2 RESERVED_15_3 3 15 ixDPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_LANE_OVRD_OUT 2 0x3161 4 0 4294967295 LANE_MPLLA_EN_OUT 0 0 LANE_MPLLB_EN_OUT 1 1 LANE_OVRD_EN 2 2 RESERVED_15_3 3 15 ixDPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_SUP_OVRD_IN 2 0x3162 4 0 4294967295 MPLLA_STATE 0 0 MPLLB_STATE 1 1 SUP_STATE_OVRD_EN 2 2 RESERVED_15_3 3 15 ixDPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_SUP_PMA_IN 2 0x3163 3 0 4294967295 MPLLA_STATE 0 0 MPLLB_STATE 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT 2 0x3164 16 0 4294967295 TX_REQ_OVRD_VAL 0 0 TX_REQ_OVRD_EN 1 1 TX_RESET_OVRD_VAL 2 2 TX_RESET_OVRD_EN 3 3 TX_BEACON_EN_OVRD_VAL 4 4 TX_BEACON_EN_OVRD_EN 5 5 TX_ASYNC_DRV_EN_OVRD_VAL 6 6 TX_ASYNC_DRV_EN_OVRD_EN 7 7 TX_ASYNC_EN_OVRD_VAL 8 8 TX_ASYNC_EN_OVRD_EN 9 9 TX_DWORD_CLK_SYNC_OVRD_VAL 10 10 TX_DWORD_CLK_SYNC_OVRD_EN 11 11 LANE_TX2RX_SER_LB_EN_OVRD_VAL 12 12 LANE_TX2RX_SER_LB_EN_OVRD_EN 13 13 TX_PMA_DATA_EN_OVRD_VAL_R 14 14 TX_PMA_DATA_EN_OVRD_EN_R 15 15 ixDPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_TX_PMA_IN 2 0x3165 2 0 4294967295 ACK 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT 2 0x3166 9 0 4294967295 RX_REQ_OVRD_VAL 0 0 RX_REQ_OVRD_EN 1 1 RX_RESET_OVRD_VAL 2 2 RX_RESET_OVRD_EN 3 3 LANE_RX2TX_PAR_LB_EN_OVRD_VAL 4 4 LANE_RX2TX_PAR_LB_EN_OVRD_EN 5 5 RX_PMA_DATA_EN_OVRD_VAL_R 6 6 RX_PMA_DATA_EN_OVRD_EN_R 7 7 RESERVED_15_8 8 15 ixDPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_RX_PMA_IN 2 0x3167 2 0 4294967295 ACK 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_LANE_RTUNE_CTL 2 0x3168 2 0 4294967295 LANE_RTUNE_REQ 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_SUP_PMA_IN_1 2 0x3169 2 0 4294967295 RTUNE_ACK 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_IN 2 0x316a 9 0 4294967295 RX_PMA_PWM_WORD_CLK_R 0 0 RX_PMA_PWM_WORD_CLK_OVRD_EN 1 1 RX_PMA_PWM_DATA_R 2 2 RX_PMA_PWM_DATA_OVRD_EN 3 3 RX_PMA_PWM_CLK_R 4 4 RX_PMA_PWM_CLK_OVRD_EN 5 5 RX_PMA_TERM_CTL_R 6 7 RX_PMA_TERM_CTL_OVRD_EN 8 8 RESERVED_15_9 9 15 ixDPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_OUT 2 0x316b 7 0 4294967295 RX_PMA_PWM_EN 0 0 RX_PMA_PWM_EN_OVRD_EN 1 1 RX_PMA_PWM_CLK_SEL 2 3 RX_PMA_PWM_CLK_SEL_OVRD_EN 4 4 RX_PMA_ASYNC_EN 5 5 RX_PMA_ASYNC_EN_OVRD_EN 6 6 RESERVED_15_7 7 15 ixDPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_RX_ADAPT_OVRD_OUT 2 0x316c 3 0 4294967295 RX_PMA_IQ_PHASE_ADJUST_MAP_OVRD_VAL 0 6 RX_PMA_IQ_PHASE_ADJUST_MAP_OVRD_EN 7 7 RESERVED_15_8 8 15 ixDPCSSYS_CR1_RAWLANE1_DIG_TX_CTL_TX_FSM_CTL 2 0x3180 6 0 4294967295 TX_WAIT_MPLL_OFF_TIME 0 6 TX_P2_ALLOW_RXDET 7 7 TX_P1_ALLOW_RXDET 8 8 TX_P0S_ALLOW_RXDET 9 9 TX_P0_ALLOW_RXDET 10 10 RESERVED_15_11 11 15 ixDPCSSYS_CR1_RAWLANE1_DIG_TX_CTL_TX_CLK_CTL 2 0x3181 4 0 4294967295 TX_CLK_EN 0 0 TX_CLK_SEL 1 4 ASYNC_BEACON_WAIT_TIME 5 10 RESERVED_15_11 11 15 ixDPCSSYS_CR1_RAWLANE1_DIG_TX_CTL_TX_DCC_CONT_STATUS 2 0x3182 2 0 4294967295 ENABLE 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR1_RAWLANE1_DIG_TX_CTL_OCLA 2 0x3183 2 0 4294967295 FSM_EN 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR1_RAWLANE1_DIG_TX_CTL_UPCS_OCLA 2 0x3184 3 0 4294967295 DATA_EN 0 1 CLK_EN 2 2 RESERVED_15_3 3 15 ixDPCSSYS_CR1_RAWLANE1_DIG_RX_CTL_RX_FSM_CTL 2 0x31a0 3 0 4294967295 EN_RX_CTL_FSM 0 0 RATE_CHG_IN_P1 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR1_RAWLANE1_DIG_RX_CTL_RX_LOS_MASK_CTL 2 0x31a1 2 0 4294967295 RX_LOS_MASK_CNT 0 8 RESERVED_15_9 9 15 ixDPCSSYS_CR1_RAWLANE1_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL 2 0x31a2 2 0 4294967295 RX_DATA_EN_OVRD_CNT 0 4 INT_REF_TRCK_CNT 5 15 ixDPCSSYS_CR1_RAWLANE1_DIG_RX_CTL_OFFCAN_CONT_STATUS 2 0x31a3 2 0 4294967295 ENABLE 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR1_RAWLANE1_DIG_RX_CTL_ADAPT_CONT_STATUS 2 0x31a4 2 0 4294967295 ENABLE 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR1_RAWLANE1_DIG_RX_CTL_UPCS_OCLA 2 0x31a5 3 0 4294967295 DATA_EN 0 2 CLK_EN 3 3 RESERVED_15_4 4 15 ixDPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN 2 0x31c0 11 0 4294967295 RATE_OVRD_VAL 0 1 RATE_OVRD_EN 2 2 WIDTH_OVRD_VAL 3 4 WIDTH_OVRD_EN 5 5 PSTATE_OVRD_VAL 6 7 PSTATE_OVRD_EN 8 8 LPD_OVRD_VAL 9 9 LPD_OVRD_EN 10 10 LANE_RX2TX_PAR_LB_EN_OVRD_VAL 11 11 LANE_RX2TX_PAR_LB_EN_OVRD_EN 12 12 RESERVED_15_13 13 15 ixDPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN 2 0x31c1 12 0 4294967295 PSTATE 0 1 LPD 2 2 WIDTH 3 4 RATE 5 7 MPLLB_SEL 8 8 MPLL_EN 9 9 OVRD_EN 10 10 MSTR_MPLLA_STATE 11 11 MSTR_MPLLB_STATE 12 12 MSTR_MPLL_OVRD_EN 13 13 TX_ASYNC_EN_OVR_VAL 14 14 TX_ASYNC_EN_OVR_EN 15 15 ixDPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1 2 0x31c2 13 0 4294967295 DETRX_REQ_OVRD_VAL 0 0 DETRX_REQ_OVRD_EN 1 1 VBOOST_EN_OVRD_VAL 2 2 VBOOST_EN_OVRD_EN 3 3 IBOOST_LVL_OVRD_VAL 4 7 IBOOST_LVL_OVRD_EN 8 8 TX_BEACON_EN_OVR_VAL 9 9 TX_BEACON_EN_OVR_EN 10 10 LANE_TX2RX_SER_LB_EN_OVRD_VAL 11 11 LANE_TX2RX_SER_LB_EN_OVRD_EN 12 12 TX_ASYNC_DATA_OVRD_VAL 13 13 TX_ASYNC_DATA_OVRD_EN 14 14 RESERVED_15_15 15 15 ixDPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_MASTER_MPLL_LOOP 2 0x31c3 3 0 4294967295 MPLLB_LOOP_EN 0 0 MPLLA_LOOP_EN 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1 2 0x31c4 11 0 4294967295 RESERVED 0 1 RX_LOS_LFPS_EN_OVRD_VAL 2 2 RX_LOS_LFPS_EN_OVRD_EN 3 3 RX_LOS_THRSHLD_OVRD_VAL 4 6 RX_LOS_THRSHLD_OVRD_EN 7 7 ADAPT_REQ 8 8 ADAPT_REQ_OVRD_EN 9 9 ADAPT_CONT 10 10 OFFCAN_CONT 11 11 CONT_OVRD_EN 12 12 RESERVED_15_13 13 15 ixDPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_2 2 0x31c5 4 0 4294967295 VCO_LD_VAL_OVRD 0 12 VCO_LD_VAL_OVRD_EN 13 13 VCO_LOWFREQ_VAL_OVRD 14 14 VCO_LOWFREQ_VAL_OVRD_EN 15 15 ixDPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_3 2 0x31c6 3 0 4294967295 REF_LD_VAL_OVRD 0 6 REF_LD_VAL_OVRD_EN 7 7 RESERVED_15_8 8 15 ixDPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT_2 2 0x31c7 3 0 4294967295 RX_VALID 0 0 RX_VALID_OVRD_EN 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_2 2 0x31c8 7 0 4294967295 LANE_TX2RX_SER_LB_EN_OVRD_VAL 0 0 LANE_TX2RX_SER_LB_EN_OVRD_EN 1 1 TX_DATA_EN_OVRD_VAL_R 2 2 TX_DATA_EN_OVRD_EN_R 3 3 TX_ASYNC_DATA_OVRD_VAL_R 4 4 TX_ASYNC_DATA_OVRD_EN_R 5 5 RESERVED_15_6 6 15 ixDPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN 2 0x3200 12 0 4294967295 PSTATE 0 1 LPD 2 2 WIDTH 3 4 RATE 5 7 MPLLB_SEL 8 8 MPLL_EN 9 9 OVRD_EN 10 10 MSTR_MPLLA_STATE 11 11 MSTR_MPLLB_STATE 12 12 MSTR_MPLL_OVRD_EN 13 13 TX_ASYNC_EN_OVR_VAL 14 14 TX_ASYNC_EN_OVR_EN 15 15 ixDPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1 2 0x3201 13 0 4294967295 RESET_OVRD_VAL 0 0 RESET_OVRD_EN 1 1 REQ_OVRD_VAL 2 2 REQ_OVRD_EN 3 3 DETRX_REQ_OVRD_VAL 4 4 DETRX_REQ_OVRD_EN 5 5 VBOOST_EN_OVRD_VAL 6 6 VBOOST_EN_OVRD_EN 7 7 IBOOST_LVL_OVRD_VAL 8 11 IBOOST_LVL_OVRD_EN 12 12 TX_BEACON_EN_OVR_VAL 13 13 TX_BEACON_EN_OVR_EN 14 14 RESERVED_15_15 15 15 ixDPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_PCS_IN 2 0x3202 12 0 4294967295 RESET 0 0 REQ 1 1 PSTATE 2 3 LPD 4 4 WIDTH 5 6 RATE 7 9 MPLLB_SEL 10 10 MPLL_EN 11 11 MSTR_MPLLA_STATE 12 12 MSTR_MPLLB_STATE 13 13 DETRX_REQ 14 14 RESERVED_15_15 15 15 ixDPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_OVRD_OUT 2 0x3203 6 0 4294967295 ACK 0 0 DETRX_RESULT 1 1 EN_CTL 2 2 TX_DWORD_CLK_SYNC_OVRD_VAL 3 3 TX_DWORD_CLK_SYNC_OVRD_EN 4 4 RESERVED_15_5 5 15 ixDPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_PCS_OUT 2 0x3204 2 0 4294967295 ACK 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN 2 0x3205 12 0 4294967295 RATE 0 1 WIDTH 2 3 PSTATE 4 5 LPD 6 6 OVRD_EN 7 7 ADAPT_AFE_EN 8 8 ADAPT_DFE_EN 9 9 LANE_RX2TX_PAR_LB_EN_OVRD_VAL 10 10 LANE_RX2TX_PAR_LB_EN_OVRD_EN 11 11 RX_DATA_EN_OVRD_VAL_R 12 12 RX_DATA_EN_OVRD_EN_R 13 13 RESERVED_15_14 14 15 ixDPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1 2 0x3206 12 0 4294967295 RESET_OVRD_VAL 0 0 RESET_OVRD_EN 1 1 REQ_OVRD_VAL 2 2 REQ_OVRD_EN 3 3 RX_LOS_THRSHLD_OVRD_VAL 4 6 RX_LOS_THRSHLD_OVRD_EN 7 7 ADAPT_REQ 8 8 ADAPT_REQ_OVRD_EN 9 9 ADAPT_CONT 10 10 OFFCAN_CONT 11 11 CONT_OVRD_EN 12 12 RESERVED_15_13 13 15 ixDPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_2 2 0x3207 4 0 4294967295 VCO_LD_VAL_OVRD 0 12 VCO_LD_VAL_OVRD_EN 13 13 VCO_LOWFREQ_VAL_OVRD 14 14 VCO_LOWFREQ_VAL_OVRD_EN 15 15 ixDPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_3 2 0x3208 3 0 4294967295 REF_LD_VAL_OVRD 0 6 REF_LD_VAL_OVRD_EN 7 7 RESERVED_15_8 8 15 ixDPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_PCS_IN 2 0x3209 13 0 4294967295 REQ 0 0 RATE 1 2 WIDTH 3 4 PSTATE 5 6 LPD 7 7 CDR_VCO_LOWFREQ 8 8 ADAPT_AFE_EN 9 9 ADAPT_DFE_EN 10 10 ADAPT_REQ 11 11 ADAPT_CONT 12 12 OFFCAN_CONT 13 13 RESET 14 14 RESERVED_15_15 15 15 ixDPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_1 2 0x320a 2 0 4294967295 REF_LD_VAL 0 6 RESERVED_15_7 7 15 ixDPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_2 2 0x320b 2 0 4294967295 VCO_LD_VAL 0 12 RESERVED_15_13 13 15 ixDPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_3 2 0x320c 4 0 4294967295 EQ_ATT_LVL 0 2 EQ_VGA1_GAIN 3 6 EQ_VGA2_GAIN 7 10 EQ_CTLE_BOOST 11 15 ixDPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_4 2 0x320d 3 0 4294967295 EQ_CTLE_POLE 0 2 EQ_DFE_TAP1 3 10 RESERVED_15_11 11 15 ixDPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT 2 0x320e 3 0 4294967295 ACK 0 0 EN_CTL 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_PCS_OUT 2 0x320f 2 0 4294967295 ACK 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_ADAPT_ACK 2 0x3210 2 0 4294967295 RX_ADAPT_ACK 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_ADAPT_FOM 2 0x3211 2 0 4294967295 RX_ADAPT_FOM 0 7 RESERVED_15_8 8 15 ixDPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_TXPRE_DIR 2 0x3212 2 0 4294967295 RX_TXPRE_DIR 0 1 RESERVED_15_2 2 15 ixDPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_TXMAIN_DIR 2 0x3213 2 0 4294967295 RX_TXMAIN_DIR 0 1 RESERVED_15_2 2 15 ixDPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_TXPOST_DIR 2 0x3214 2 0 4294967295 RX_TXPOST_DIR 0 1 RESERVED_15_2 2 15 ixDPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_LANE_NUMBER 2 0x3215 2 0 4294967295 LANE_NUMBER 0 3 RESERVED_15_4 4 15 ixDPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RESERVED_1 2 0x3216 1 0 4294967295 RESERVED_REG_1 0 15 ixDPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RESERVED_2 2 0x3217 1 0 4294967295 RESERVED_REG_2 0 15 ixDPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN 2 0x3218 16 0 4294967295 RX_RESET_ATE_OVRD_VAL 0 0 RX_RESET_ATE_OVRD_EN 1 1 TX_RESET_ATE_OVRD_VAL 2 2 TX_RESET_ATE_OVRD_EN 3 3 RX_REQ_ATE_OVRD_VAL 4 4 RX_REQ_ATE_OVRD_EN 5 5 TX_REQ_ATE_OVRD_VAL 6 6 TX_REQ_ATE_OVRD_EN 7 7 RX_ADAPT_AFE_EN_OVRD_VAL 8 8 RX_ADAPT_AFE_EN_OVRD_EN 9 9 RX_ADAPT_DFE_EN_OVRD_VAL 10 10 RX_ADAPT_DFE_EN_OVRD_EN 11 11 TX_DATA_EN_ATE_OVRD_VAL 12 12 TX_DATA_EN_ATE_OVRD_EN 13 13 RX_DATA_EN_ATE_OVRD_VAL 14 14 RX_DATA_EN_ATE_OVRD_EN 15 15 ixDPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN 2 0x3219 3 0 4294967295 RX_EQ_DELTA_IQ_OVRD_VAL 0 3 RX_EQ_DELTA_IQ_OVRD_EN 4 4 RESERVED_15_5 5 15 ixDPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN 2 0x321a 5 0 4294967295 RX_TERM_CTRL_OVRD_VAL 0 2 RX_TERM_CTRL_OVRD_EN 3 3 TX_TERM_CTRL_OVRD_VAL 4 6 TX_TERM_CTRL_OVRD_EN 7 7 RESERVED_15_8 8 15 ixDPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TXRX_TERM_CTRL_IN 2 0x321b 3 0 4294967295 RX_TERM_CTRL 0 2 TX_TERM_CTRL 3 5 RESERVED_15_6 6 15 ixDPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT_1 2 0x321c 2 0 4294967295 RX_CLK_EN 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_EQ_OVRD_IN_1 2 0x321d 4 0 4294967295 RX_EQ_AFE_GAIN_OVRD_VAL 0 3 RX_EQ_ATT_LVL_OVRD_VAL 4 6 RX_EQ_OVRD_EN 7 7 RESERVED_15_8 8 15 ixDPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_EQ_OVRD_IN_2 2 0x321e 3 0 4294967295 RX_EQ_DFE_TAP1_OVRD_VAL 0 7 RX_EQ_CTLE_BOOST_OVRD_VAL 8 12 RESERVED_15_13 13 15 ixDPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_PH2_CAL 2 0x321f 4 0 4294967295 PH2_CAL_ACK_VAL 0 0 PH2_CAL_REQ_VAL 1 1 PH2_CAL_REQ_OVRD_VAL 2 2 RESERVED_15_3 3 15 ixDPCSSYS_CR1_RAWLANE2_DIG_FSM_FSM_OVRD_CTL 2 0x3220 5 0 4294967295 FSM_JMP_ADDR 0 11 FSM_JMP_EN 12 12 FSM_CMD_START 13 13 FSM_OVRD_EN 14 14 FSM_BREAK 15 15 ixDPCSSYS_CR1_RAWLANE2_DIG_FSM_MEM_ADDR_MON 2 0x3221 1 0 4294967295 MEM_ADDR 0 15 ixDPCSSYS_CR1_RAWLANE2_DIG_FSM_STATUS_MON 2 0x3222 8 0 4294967295 STATE 0 4 CMD_RDY 5 5 ALU_OVFLW 6 6 ALU_RES_EQ0 7 7 WAIT_CNT_EQ0 8 8 WRMSK_DISABLED 9 9 RDMSK_DISABLED 10 10 RESERVED_15_11 11 15 ixDPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_RX_STARTUP_CAL 2 0x3223 2 0 4294967295 FAST_RX_STARTUP_CAL 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_RX_ADAPT 2 0x3224 2 0 4294967295 FAST_RX_ADAPT 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_RX_AFE_CAL 2 0x3225 2 0 4294967295 FAST_RX_AFE_CAL 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_RX_DFE_CAL 2 0x3226 2 0 4294967295 FAST_RX_DFE_CAL 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_RX_BYPASS_CAL 2 0x3227 2 0 4294967295 FAST_RX_BYPASS_CAL 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_RX_REFLVL_CAL 2 0x3228 2 0 4294967295 FAST_RX_REFLVL_CAL 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_RX_IQ_CAL 2 0x3229 2 0 4294967295 FAST_RX_IQ_CAL 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_RX_AFE_ADAPT 2 0x322a 2 0 4294967295 FAST_RX_AFE_ADAPT 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_RX_DFE_ADAPT 2 0x322b 2 0 4294967295 FAST_RX_DFE_ADAPT 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_SUP 2 0x322c 2 0 4294967295 FAST_SUP 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_TX_CMN_MODE 2 0x322d 2 0 4294967295 FAST_TX_CMN_MODE 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_TX_RXDET 2 0x322e 2 0 4294967295 FAST_TX_RXDET 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_RX_PWRUP 2 0x322f 2 0 4294967295 FAST_RX_PWRUP 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_RX_VCO_WAIT 2 0x3230 2 0 4294967295 FAST_RX_VCO_WAIT 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_RX_VCO_CAL 2 0x3231 2 0 4294967295 FAST_RX_VCO_CAL 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR1_RAWLANE2_DIG_FSM_CMNCAL_MPLL_STATUS 2 0x3232 3 0 4294967295 CMNCAL_MPLL_INIT 0 0 CMNCAL_MPLL_DONE 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_RX_CONT_CAL_ADAPT 2 0x3233 2 0 4294967295 FAST_RX_CONT_CAL_ADAPT 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_RX_CONT_ADAPT 2 0x3234 2 0 4294967295 FAST_RX_CONT_ADAPT 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_RX_CONT_DATA_CAL 2 0x3235 2 0 4294967295 FAST_RX_CONT_DATA_CAL 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_RX_CONT_PHASE_CAL 2 0x3236 2 0 4294967295 FAST_RX_CONT_PHASE_CAL 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_RX_CONT_AFE_CAL 2 0x3237 2 0 4294967295 FAST_RX_CONT_AFE_CAL 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_FLAGS 2 0x3238 12 0 4294967295 TX_FAST_DCC_CAL 0 0 RX_FAST_DCC_CAL 1 1 RX_FAST_VPHUD_CAL 2 2 RX_FAST_VREF_CAL 3 3 RX_FAST_SIGDET_CAL 4 4 RESERVED_2 5 7 TX_FAST_CONT_DCC_CAL 8 8 RX_FAST_CONT_DCC_CAL 9 9 RX_FAST_CONT_VPHUD_CAL 10 10 RX_FAST_CONT_VREF_CAL 11 11 RESERVED_1 12 14 TX_SKIP_SUP_CAL 15 15 ixDPCSSYS_CR1_RAWLANE2_DIG_FSM_CR_LOCK 2 0x3239 3 0 4294967295 CR_REG_LOCK 0 0 CR_MEM_LOCK 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR1_RAWLANE2_DIG_FSM_TX_DCC_FLAGS 2 0x323a 4 0 4294967295 RATE 0 0 DIV 1 1 MPLL 2 2 RESERVED_15_3 3 15 ixDPCSSYS_CR1_RAWLANE2_DIG_FSM_TX_DCC_STATUS 2 0x323b 2 0 4294967295 FLAG 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR1_RAWLANE2_DIG_FSM_OCLA 2 0x323c 4 0 4294967295 PC_EN 0 0 REG_BANK1_EN 1 1 REG_BANK2_EN 2 2 RESERVED_15_3 3 15 ixDPCSSYS_CR1_RAWLANE2_DIG_FSM_TX_EQ_UPDATE_FLAG 2 0x323d 2 0 4294967295 TX_EQ_UPDATE_FLAG 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR1_RAWLANE2_DIG_FSM_CMNCAL_RCAL_STATUS 2 0x323e 3 0 4294967295 CMNCAL_RCAL_INIT 0 0 CMNCAL_RCAL_DONE 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR1_RAWLANE2_DIG_FSM_RX_IQ_PHASE_OFFSET 2 0x323f 2 0 4294967295 RX_IQ_PHASE_OFFSET 0 3 RESERVED_15_4 4 15 ixDPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_RESET_RTN_REQ 2 0x3240 2 0 4294967295 RESET_RTN_REQ 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_RX_RESET_IRQ 2 0x3241 2 0 4294967295 RX_RESET 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_RX_REQ_IRQ 2 0x3242 2 0 4294967295 RX_REQ 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_RX_RATE_IRQ 2 0x3243 2 0 4294967295 RX_RATE_IRQ 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_RX_PSTATE_IRQ 2 0x3244 2 0 4294967295 RX_PSTATE_IRQ 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ 2 0x3245 2 0 4294967295 RX_ADAPT_REQ_IRQ 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ 2 0x3246 2 0 4294967295 RX_ADAPT_DIS_IRQ 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_RX_RESET_IRQ_CLR 2 0x3247 2 0 4294967295 RX_RESET_IRQ_CLR 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_RX_REQ_IRQ_CLR 2 0x3248 2 0 4294967295 RX_REQ_IRQ_CLR 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_RX_RATE_IRQ_CLR 2 0x3249 2 0 4294967295 RX_RATE_IRQ_CLR 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR 2 0x324a 2 0 4294967295 RX_PSTATE_IRQ_CLR 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR 2 0x324b 2 0 4294967295 RX_ADAPT_REQ_IRQ_CLR 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR 2 0x324c 2 0 4294967295 RX_ADAPT_DIS_IRQ_CLR 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK 2 0x324d 12 0 4294967295 RX_REQ_IRQ_MSK 0 0 RX_RATE_IRQ_MSK 1 1 RX_PSTATE_IRQ_MSK 2 2 RX_ADAPT_REQ_IRQ_MSK 3 3 RX_ADAPT_DIS_IRQ_MSK 4 4 RX_RESET_IRQ_MSK 5 5 LANE_XCVR_MODE_IRQ_MSK 6 6 RX_PH2_CAL_REQ_IRQ_MSK 7 7 RX_PH2_CAL_DIS_IRQ_MSK 8 8 LANE_RX2TX_SER_LB_EN_IRQ_MSK 9 9 DCC_ONDMD_IRQ_MSK 10 10 RESERVED_15_11 11 15 ixDPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK_2 2 0x324e 3 0 4294967295 TX_RESET_IRQ_MSK 0 0 TX_REQ_IRQ_MSK 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ 2 0x324f 2 0 4294967295 LANE_XCVR_MODE_IRQ 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR 2 0x3250 2 0 4294967295 LANE_XCVR_MODE_IRQ_CLR 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ 2 0x3251 2 0 4294967295 RX_PH2_CAL_REQ_IRQ 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ 2 0x3252 2 0 4294967295 RX_PH2_CAL_DIS_IRQ 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR 2 0x3253 2 0 4294967295 RX_PH2_CAL_REQ_IRQ_CLR 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR 2 0x3254 2 0 4294967295 RX_PH2_CAL_DIS_IRQ_CLR 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ 2 0x3255 2 0 4294967295 LANE_RX2TX_SER_LB_EN_IRQ 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR 2 0x3256 2 0 4294967295 LANE_RX2TX_SER_LB_EN_IRQ_CLR 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_DCC_ONDMD_IRQ 2 0x3257 2 0 4294967295 IRQ 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_TX_RESET_IRQ 2 0x3258 2 0 4294967295 TX_RESET 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_TX_REQ_IRQ 2 0x3259 2 0 4294967295 TX_REQ 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_TX_RESET_IRQ_CLR 2 0x325a 2 0 4294967295 TX_RESET_IRQ_CLR 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_TX_REQ_IRQ_CLR 2 0x325b 2 0 4294967295 TX_REQ_IRQ_CLR 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_LANE_OVRD_IN 2 0x3260 4 0 4294967295 LANE_MPLLA_EN_IN 0 0 LANE_MPLLB_EN_IN 1 1 LANE_OVRD_EN 2 2 RESERVED_15_3 3 15 ixDPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_LANE_OVRD_OUT 2 0x3261 4 0 4294967295 LANE_MPLLA_EN_OUT 0 0 LANE_MPLLB_EN_OUT 1 1 LANE_OVRD_EN 2 2 RESERVED_15_3 3 15 ixDPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_SUP_OVRD_IN 2 0x3262 4 0 4294967295 MPLLA_STATE 0 0 MPLLB_STATE 1 1 SUP_STATE_OVRD_EN 2 2 RESERVED_15_3 3 15 ixDPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_SUP_PMA_IN 2 0x3263 3 0 4294967295 MPLLA_STATE 0 0 MPLLB_STATE 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT 2 0x3264 16 0 4294967295 TX_REQ_OVRD_VAL 0 0 TX_REQ_OVRD_EN 1 1 TX_RESET_OVRD_VAL 2 2 TX_RESET_OVRD_EN 3 3 TX_BEACON_EN_OVRD_VAL 4 4 TX_BEACON_EN_OVRD_EN 5 5 TX_ASYNC_DRV_EN_OVRD_VAL 6 6 TX_ASYNC_DRV_EN_OVRD_EN 7 7 TX_ASYNC_EN_OVRD_VAL 8 8 TX_ASYNC_EN_OVRD_EN 9 9 TX_DWORD_CLK_SYNC_OVRD_VAL 10 10 TX_DWORD_CLK_SYNC_OVRD_EN 11 11 LANE_TX2RX_SER_LB_EN_OVRD_VAL 12 12 LANE_TX2RX_SER_LB_EN_OVRD_EN 13 13 TX_PMA_DATA_EN_OVRD_VAL_R 14 14 TX_PMA_DATA_EN_OVRD_EN_R 15 15 ixDPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_TX_PMA_IN 2 0x3265 2 0 4294967295 ACK 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT 2 0x3266 9 0 4294967295 RX_REQ_OVRD_VAL 0 0 RX_REQ_OVRD_EN 1 1 RX_RESET_OVRD_VAL 2 2 RX_RESET_OVRD_EN 3 3 LANE_RX2TX_PAR_LB_EN_OVRD_VAL 4 4 LANE_RX2TX_PAR_LB_EN_OVRD_EN 5 5 RX_PMA_DATA_EN_OVRD_VAL_R 6 6 RX_PMA_DATA_EN_OVRD_EN_R 7 7 RESERVED_15_8 8 15 ixDPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_RX_PMA_IN 2 0x3267 2 0 4294967295 ACK 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_LANE_RTUNE_CTL 2 0x3268 2 0 4294967295 LANE_RTUNE_REQ 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_SUP_PMA_IN_1 2 0x3269 2 0 4294967295 RTUNE_ACK 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_IN 2 0x326a 9 0 4294967295 RX_PMA_PWM_WORD_CLK_R 0 0 RX_PMA_PWM_WORD_CLK_OVRD_EN 1 1 RX_PMA_PWM_DATA_R 2 2 RX_PMA_PWM_DATA_OVRD_EN 3 3 RX_PMA_PWM_CLK_R 4 4 RX_PMA_PWM_CLK_OVRD_EN 5 5 RX_PMA_TERM_CTL_R 6 7 RX_PMA_TERM_CTL_OVRD_EN 8 8 RESERVED_15_9 9 15 ixDPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_OUT 2 0x326b 7 0 4294967295 RX_PMA_PWM_EN 0 0 RX_PMA_PWM_EN_OVRD_EN 1 1 RX_PMA_PWM_CLK_SEL 2 3 RX_PMA_PWM_CLK_SEL_OVRD_EN 4 4 RX_PMA_ASYNC_EN 5 5 RX_PMA_ASYNC_EN_OVRD_EN 6 6 RESERVED_15_7 7 15 ixDPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_RX_ADAPT_OVRD_OUT 2 0x326c 3 0 4294967295 RX_PMA_IQ_PHASE_ADJUST_MAP_OVRD_VAL 0 6 RX_PMA_IQ_PHASE_ADJUST_MAP_OVRD_EN 7 7 RESERVED_15_8 8 15 ixDPCSSYS_CR1_RAWLANE2_DIG_TX_CTL_TX_FSM_CTL 2 0x3280 6 0 4294967295 TX_WAIT_MPLL_OFF_TIME 0 6 TX_P2_ALLOW_RXDET 7 7 TX_P1_ALLOW_RXDET 8 8 TX_P0S_ALLOW_RXDET 9 9 TX_P0_ALLOW_RXDET 10 10 RESERVED_15_11 11 15 ixDPCSSYS_CR1_RAWLANE2_DIG_TX_CTL_TX_CLK_CTL 2 0x3281 4 0 4294967295 TX_CLK_EN 0 0 TX_CLK_SEL 1 4 ASYNC_BEACON_WAIT_TIME 5 10 RESERVED_15_11 11 15 ixDPCSSYS_CR1_RAWLANE2_DIG_TX_CTL_TX_DCC_CONT_STATUS 2 0x3282 2 0 4294967295 ENABLE 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR1_RAWLANE2_DIG_TX_CTL_OCLA 2 0x3283 2 0 4294967295 FSM_EN 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR1_RAWLANE2_DIG_TX_CTL_UPCS_OCLA 2 0x3284 3 0 4294967295 DATA_EN 0 1 CLK_EN 2 2 RESERVED_15_3 3 15 ixDPCSSYS_CR1_RAWLANE2_DIG_RX_CTL_RX_FSM_CTL 2 0x32a0 3 0 4294967295 EN_RX_CTL_FSM 0 0 RATE_CHG_IN_P1 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR1_RAWLANE2_DIG_RX_CTL_RX_LOS_MASK_CTL 2 0x32a1 2 0 4294967295 RX_LOS_MASK_CNT 0 8 RESERVED_15_9 9 15 ixDPCSSYS_CR1_RAWLANE2_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL 2 0x32a2 2 0 4294967295 RX_DATA_EN_OVRD_CNT 0 4 INT_REF_TRCK_CNT 5 15 ixDPCSSYS_CR1_RAWLANE2_DIG_RX_CTL_OFFCAN_CONT_STATUS 2 0x32a3 2 0 4294967295 ENABLE 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR1_RAWLANE2_DIG_RX_CTL_ADAPT_CONT_STATUS 2 0x32a4 2 0 4294967295 ENABLE 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR1_RAWLANE2_DIG_RX_CTL_UPCS_OCLA 2 0x32a5 3 0 4294967295 DATA_EN 0 2 CLK_EN 3 3 RESERVED_15_4 4 15 ixDPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN 2 0x32c0 11 0 4294967295 RATE_OVRD_VAL 0 1 RATE_OVRD_EN 2 2 WIDTH_OVRD_VAL 3 4 WIDTH_OVRD_EN 5 5 PSTATE_OVRD_VAL 6 7 PSTATE_OVRD_EN 8 8 LPD_OVRD_VAL 9 9 LPD_OVRD_EN 10 10 LANE_RX2TX_PAR_LB_EN_OVRD_VAL 11 11 LANE_RX2TX_PAR_LB_EN_OVRD_EN 12 12 RESERVED_15_13 13 15 ixDPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN 2 0x32c1 12 0 4294967295 PSTATE 0 1 LPD 2 2 WIDTH 3 4 RATE 5 7 MPLLB_SEL 8 8 MPLL_EN 9 9 OVRD_EN 10 10 MSTR_MPLLA_STATE 11 11 MSTR_MPLLB_STATE 12 12 MSTR_MPLL_OVRD_EN 13 13 TX_ASYNC_EN_OVR_VAL 14 14 TX_ASYNC_EN_OVR_EN 15 15 ixDPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1 2 0x32c2 13 0 4294967295 DETRX_REQ_OVRD_VAL 0 0 DETRX_REQ_OVRD_EN 1 1 VBOOST_EN_OVRD_VAL 2 2 VBOOST_EN_OVRD_EN 3 3 IBOOST_LVL_OVRD_VAL 4 7 IBOOST_LVL_OVRD_EN 8 8 TX_BEACON_EN_OVR_VAL 9 9 TX_BEACON_EN_OVR_EN 10 10 LANE_TX2RX_SER_LB_EN_OVRD_VAL 11 11 LANE_TX2RX_SER_LB_EN_OVRD_EN 12 12 TX_ASYNC_DATA_OVRD_VAL 13 13 TX_ASYNC_DATA_OVRD_EN 14 14 RESERVED_15_15 15 15 ixDPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_MASTER_MPLL_LOOP 2 0x32c3 3 0 4294967295 MPLLB_LOOP_EN 0 0 MPLLA_LOOP_EN 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1 2 0x32c4 11 0 4294967295 RESERVED 0 1 RX_LOS_LFPS_EN_OVRD_VAL 2 2 RX_LOS_LFPS_EN_OVRD_EN 3 3 RX_LOS_THRSHLD_OVRD_VAL 4 6 RX_LOS_THRSHLD_OVRD_EN 7 7 ADAPT_REQ 8 8 ADAPT_REQ_OVRD_EN 9 9 ADAPT_CONT 10 10 OFFCAN_CONT 11 11 CONT_OVRD_EN 12 12 RESERVED_15_13 13 15 ixDPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_2 2 0x32c5 4 0 4294967295 VCO_LD_VAL_OVRD 0 12 VCO_LD_VAL_OVRD_EN 13 13 VCO_LOWFREQ_VAL_OVRD 14 14 VCO_LOWFREQ_VAL_OVRD_EN 15 15 ixDPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_3 2 0x32c6 3 0 4294967295 REF_LD_VAL_OVRD 0 6 REF_LD_VAL_OVRD_EN 7 7 RESERVED_15_8 8 15 ixDPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT_2 2 0x32c7 3 0 4294967295 RX_VALID 0 0 RX_VALID_OVRD_EN 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_2 2 0x32c8 7 0 4294967295 LANE_TX2RX_SER_LB_EN_OVRD_VAL 0 0 LANE_TX2RX_SER_LB_EN_OVRD_EN 1 1 TX_DATA_EN_OVRD_VAL_R 2 2 TX_DATA_EN_OVRD_EN_R 3 3 TX_ASYNC_DATA_OVRD_VAL_R 4 4 TX_ASYNC_DATA_OVRD_EN_R 5 5 RESERVED_15_6 6 15 ixDPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN 2 0x3300 12 0 4294967295 PSTATE 0 1 LPD 2 2 WIDTH 3 4 RATE 5 7 MPLLB_SEL 8 8 MPLL_EN 9 9 OVRD_EN 10 10 MSTR_MPLLA_STATE 11 11 MSTR_MPLLB_STATE 12 12 MSTR_MPLL_OVRD_EN 13 13 TX_ASYNC_EN_OVR_VAL 14 14 TX_ASYNC_EN_OVR_EN 15 15 ixDPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1 2 0x3301 13 0 4294967295 RESET_OVRD_VAL 0 0 RESET_OVRD_EN 1 1 REQ_OVRD_VAL 2 2 REQ_OVRD_EN 3 3 DETRX_REQ_OVRD_VAL 4 4 DETRX_REQ_OVRD_EN 5 5 VBOOST_EN_OVRD_VAL 6 6 VBOOST_EN_OVRD_EN 7 7 IBOOST_LVL_OVRD_VAL 8 11 IBOOST_LVL_OVRD_EN 12 12 TX_BEACON_EN_OVR_VAL 13 13 TX_BEACON_EN_OVR_EN 14 14 RESERVED_15_15 15 15 ixDPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_PCS_IN 2 0x3302 12 0 4294967295 RESET 0 0 REQ 1 1 PSTATE 2 3 LPD 4 4 WIDTH 5 6 RATE 7 9 MPLLB_SEL 10 10 MPLL_EN 11 11 MSTR_MPLLA_STATE 12 12 MSTR_MPLLB_STATE 13 13 DETRX_REQ 14 14 RESERVED_15_15 15 15 ixDPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_OVRD_OUT 2 0x3303 6 0 4294967295 ACK 0 0 DETRX_RESULT 1 1 EN_CTL 2 2 TX_DWORD_CLK_SYNC_OVRD_VAL 3 3 TX_DWORD_CLK_SYNC_OVRD_EN 4 4 RESERVED_15_5 5 15 ixDPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_PCS_OUT 2 0x3304 2 0 4294967295 ACK 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN 2 0x3305 12 0 4294967295 RATE 0 1 WIDTH 2 3 PSTATE 4 5 LPD 6 6 OVRD_EN 7 7 ADAPT_AFE_EN 8 8 ADAPT_DFE_EN 9 9 LANE_RX2TX_PAR_LB_EN_OVRD_VAL 10 10 LANE_RX2TX_PAR_LB_EN_OVRD_EN 11 11 RX_DATA_EN_OVRD_VAL_R 12 12 RX_DATA_EN_OVRD_EN_R 13 13 RESERVED_15_14 14 15 ixDPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1 2 0x3306 12 0 4294967295 RESET_OVRD_VAL 0 0 RESET_OVRD_EN 1 1 REQ_OVRD_VAL 2 2 REQ_OVRD_EN 3 3 RX_LOS_THRSHLD_OVRD_VAL 4 6 RX_LOS_THRSHLD_OVRD_EN 7 7 ADAPT_REQ 8 8 ADAPT_REQ_OVRD_EN 9 9 ADAPT_CONT 10 10 OFFCAN_CONT 11 11 CONT_OVRD_EN 12 12 RESERVED_15_13 13 15 ixDPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_2 2 0x3307 4 0 4294967295 VCO_LD_VAL_OVRD 0 12 VCO_LD_VAL_OVRD_EN 13 13 VCO_LOWFREQ_VAL_OVRD 14 14 VCO_LOWFREQ_VAL_OVRD_EN 15 15 ixDPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_3 2 0x3308 3 0 4294967295 REF_LD_VAL_OVRD 0 6 REF_LD_VAL_OVRD_EN 7 7 RESERVED_15_8 8 15 ixDPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_PCS_IN 2 0x3309 13 0 4294967295 REQ 0 0 RATE 1 2 WIDTH 3 4 PSTATE 5 6 LPD 7 7 CDR_VCO_LOWFREQ 8 8 ADAPT_AFE_EN 9 9 ADAPT_DFE_EN 10 10 ADAPT_REQ 11 11 ADAPT_CONT 12 12 OFFCAN_CONT 13 13 RESET 14 14 RESERVED_15_15 15 15 ixDPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_1 2 0x330a 2 0 4294967295 REF_LD_VAL 0 6 RESERVED_15_7 7 15 ixDPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_2 2 0x330b 2 0 4294967295 VCO_LD_VAL 0 12 RESERVED_15_13 13 15 ixDPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_3 2 0x330c 4 0 4294967295 EQ_ATT_LVL 0 2 EQ_VGA1_GAIN 3 6 EQ_VGA2_GAIN 7 10 EQ_CTLE_BOOST 11 15 ixDPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_4 2 0x330d 3 0 4294967295 EQ_CTLE_POLE 0 2 EQ_DFE_TAP1 3 10 RESERVED_15_11 11 15 ixDPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT 2 0x330e 3 0 4294967295 ACK 0 0 EN_CTL 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_PCS_OUT 2 0x330f 2 0 4294967295 ACK 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_ADAPT_ACK 2 0x3310 2 0 4294967295 RX_ADAPT_ACK 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_ADAPT_FOM 2 0x3311 2 0 4294967295 RX_ADAPT_FOM 0 7 RESERVED_15_8 8 15 ixDPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_TXPRE_DIR 2 0x3312 2 0 4294967295 RX_TXPRE_DIR 0 1 RESERVED_15_2 2 15 ixDPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_TXMAIN_DIR 2 0x3313 2 0 4294967295 RX_TXMAIN_DIR 0 1 RESERVED_15_2 2 15 ixDPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_TXPOST_DIR 2 0x3314 2 0 4294967295 RX_TXPOST_DIR 0 1 RESERVED_15_2 2 15 ixDPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_LANE_NUMBER 2 0x3315 2 0 4294967295 LANE_NUMBER 0 3 RESERVED_15_4 4 15 ixDPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RESERVED_1 2 0x3316 1 0 4294967295 RESERVED_REG_1 0 15 ixDPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RESERVED_2 2 0x3317 1 0 4294967295 RESERVED_REG_2 0 15 ixDPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN 2 0x3318 16 0 4294967295 RX_RESET_ATE_OVRD_VAL 0 0 RX_RESET_ATE_OVRD_EN 1 1 TX_RESET_ATE_OVRD_VAL 2 2 TX_RESET_ATE_OVRD_EN 3 3 RX_REQ_ATE_OVRD_VAL 4 4 RX_REQ_ATE_OVRD_EN 5 5 TX_REQ_ATE_OVRD_VAL 6 6 TX_REQ_ATE_OVRD_EN 7 7 RX_ADAPT_AFE_EN_OVRD_VAL 8 8 RX_ADAPT_AFE_EN_OVRD_EN 9 9 RX_ADAPT_DFE_EN_OVRD_VAL 10 10 RX_ADAPT_DFE_EN_OVRD_EN 11 11 TX_DATA_EN_ATE_OVRD_VAL 12 12 TX_DATA_EN_ATE_OVRD_EN 13 13 RX_DATA_EN_ATE_OVRD_VAL 14 14 RX_DATA_EN_ATE_OVRD_EN 15 15 ixDPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN 2 0x3319 3 0 4294967295 RX_EQ_DELTA_IQ_OVRD_VAL 0 3 RX_EQ_DELTA_IQ_OVRD_EN 4 4 RESERVED_15_5 5 15 ixDPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN 2 0x331a 5 0 4294967295 RX_TERM_CTRL_OVRD_VAL 0 2 RX_TERM_CTRL_OVRD_EN 3 3 TX_TERM_CTRL_OVRD_VAL 4 6 TX_TERM_CTRL_OVRD_EN 7 7 RESERVED_15_8 8 15 ixDPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TXRX_TERM_CTRL_IN 2 0x331b 3 0 4294967295 RX_TERM_CTRL 0 2 TX_TERM_CTRL 3 5 RESERVED_15_6 6 15 ixDPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT_1 2 0x331c 2 0 4294967295 RX_CLK_EN 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_EQ_OVRD_IN_1 2 0x331d 4 0 4294967295 RX_EQ_AFE_GAIN_OVRD_VAL 0 3 RX_EQ_ATT_LVL_OVRD_VAL 4 6 RX_EQ_OVRD_EN 7 7 RESERVED_15_8 8 15 ixDPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_EQ_OVRD_IN_2 2 0x331e 3 0 4294967295 RX_EQ_DFE_TAP1_OVRD_VAL 0 7 RX_EQ_CTLE_BOOST_OVRD_VAL 8 12 RESERVED_15_13 13 15 ixDPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_PH2_CAL 2 0x331f 4 0 4294967295 PH2_CAL_ACK_VAL 0 0 PH2_CAL_REQ_VAL 1 1 PH2_CAL_REQ_OVRD_VAL 2 2 RESERVED_15_3 3 15 ixDPCSSYS_CR1_RAWLANE3_DIG_FSM_FSM_OVRD_CTL 2 0x3320 5 0 4294967295 FSM_JMP_ADDR 0 11 FSM_JMP_EN 12 12 FSM_CMD_START 13 13 FSM_OVRD_EN 14 14 FSM_BREAK 15 15 ixDPCSSYS_CR1_RAWLANE3_DIG_FSM_MEM_ADDR_MON 2 0x3321 1 0 4294967295 MEM_ADDR 0 15 ixDPCSSYS_CR1_RAWLANE3_DIG_FSM_STATUS_MON 2 0x3322 8 0 4294967295 STATE 0 4 CMD_RDY 5 5 ALU_OVFLW 6 6 ALU_RES_EQ0 7 7 WAIT_CNT_EQ0 8 8 WRMSK_DISABLED 9 9 RDMSK_DISABLED 10 10 RESERVED_15_11 11 15 ixDPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_RX_STARTUP_CAL 2 0x3323 2 0 4294967295 FAST_RX_STARTUP_CAL 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_RX_ADAPT 2 0x3324 2 0 4294967295 FAST_RX_ADAPT 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_RX_AFE_CAL 2 0x3325 2 0 4294967295 FAST_RX_AFE_CAL 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_RX_DFE_CAL 2 0x3326 2 0 4294967295 FAST_RX_DFE_CAL 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_RX_BYPASS_CAL 2 0x3327 2 0 4294967295 FAST_RX_BYPASS_CAL 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_RX_REFLVL_CAL 2 0x3328 2 0 4294967295 FAST_RX_REFLVL_CAL 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_RX_IQ_CAL 2 0x3329 2 0 4294967295 FAST_RX_IQ_CAL 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_RX_AFE_ADAPT 2 0x332a 2 0 4294967295 FAST_RX_AFE_ADAPT 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_RX_DFE_ADAPT 2 0x332b 2 0 4294967295 FAST_RX_DFE_ADAPT 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_SUP 2 0x332c 2 0 4294967295 FAST_SUP 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_TX_CMN_MODE 2 0x332d 2 0 4294967295 FAST_TX_CMN_MODE 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_TX_RXDET 2 0x332e 2 0 4294967295 FAST_TX_RXDET 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_RX_PWRUP 2 0x332f 2 0 4294967295 FAST_RX_PWRUP 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_RX_VCO_WAIT 2 0x3330 2 0 4294967295 FAST_RX_VCO_WAIT 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_RX_VCO_CAL 2 0x3331 2 0 4294967295 FAST_RX_VCO_CAL 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR1_RAWLANE3_DIG_FSM_CMNCAL_MPLL_STATUS 2 0x3332 3 0 4294967295 CMNCAL_MPLL_INIT 0 0 CMNCAL_MPLL_DONE 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_RX_CONT_CAL_ADAPT 2 0x3333 2 0 4294967295 FAST_RX_CONT_CAL_ADAPT 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_RX_CONT_ADAPT 2 0x3334 2 0 4294967295 FAST_RX_CONT_ADAPT 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_RX_CONT_DATA_CAL 2 0x3335 2 0 4294967295 FAST_RX_CONT_DATA_CAL 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_RX_CONT_PHASE_CAL 2 0x3336 2 0 4294967295 FAST_RX_CONT_PHASE_CAL 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_RX_CONT_AFE_CAL 2 0x3337 2 0 4294967295 FAST_RX_CONT_AFE_CAL 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_FLAGS 2 0x3338 12 0 4294967295 TX_FAST_DCC_CAL 0 0 RX_FAST_DCC_CAL 1 1 RX_FAST_VPHUD_CAL 2 2 RX_FAST_VREF_CAL 3 3 RX_FAST_SIGDET_CAL 4 4 RESERVED_2 5 7 TX_FAST_CONT_DCC_CAL 8 8 RX_FAST_CONT_DCC_CAL 9 9 RX_FAST_CONT_VPHUD_CAL 10 10 RX_FAST_CONT_VREF_CAL 11 11 RESERVED_1 12 14 TX_SKIP_SUP_CAL 15 15 ixDPCSSYS_CR1_RAWLANE3_DIG_FSM_CR_LOCK 2 0x3339 3 0 4294967295 CR_REG_LOCK 0 0 CR_MEM_LOCK 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR1_RAWLANE3_DIG_FSM_TX_DCC_FLAGS 2 0x333a 4 0 4294967295 RATE 0 0 DIV 1 1 MPLL 2 2 RESERVED_15_3 3 15 ixDPCSSYS_CR1_RAWLANE3_DIG_FSM_TX_DCC_STATUS 2 0x333b 2 0 4294967295 FLAG 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR1_RAWLANE3_DIG_FSM_OCLA 2 0x333c 4 0 4294967295 PC_EN 0 0 REG_BANK1_EN 1 1 REG_BANK2_EN 2 2 RESERVED_15_3 3 15 ixDPCSSYS_CR1_RAWLANE3_DIG_FSM_TX_EQ_UPDATE_FLAG 2 0x333d 2 0 4294967295 TX_EQ_UPDATE_FLAG 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR1_RAWLANE3_DIG_FSM_CMNCAL_RCAL_STATUS 2 0x333e 3 0 4294967295 CMNCAL_RCAL_INIT 0 0 CMNCAL_RCAL_DONE 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR1_RAWLANE3_DIG_FSM_RX_IQ_PHASE_OFFSET 2 0x333f 2 0 4294967295 RX_IQ_PHASE_OFFSET 0 3 RESERVED_15_4 4 15 ixDPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_RESET_RTN_REQ 2 0x3340 2 0 4294967295 RESET_RTN_REQ 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_RX_RESET_IRQ 2 0x3341 2 0 4294967295 RX_RESET 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_RX_REQ_IRQ 2 0x3342 2 0 4294967295 RX_REQ 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_RX_RATE_IRQ 2 0x3343 2 0 4294967295 RX_RATE_IRQ 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_RX_PSTATE_IRQ 2 0x3344 2 0 4294967295 RX_PSTATE_IRQ 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ 2 0x3345 2 0 4294967295 RX_ADAPT_REQ_IRQ 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ 2 0x3346 2 0 4294967295 RX_ADAPT_DIS_IRQ 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_RX_RESET_IRQ_CLR 2 0x3347 2 0 4294967295 RX_RESET_IRQ_CLR 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_RX_REQ_IRQ_CLR 2 0x3348 2 0 4294967295 RX_REQ_IRQ_CLR 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_RX_RATE_IRQ_CLR 2 0x3349 2 0 4294967295 RX_RATE_IRQ_CLR 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR 2 0x334a 2 0 4294967295 RX_PSTATE_IRQ_CLR 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR 2 0x334b 2 0 4294967295 RX_ADAPT_REQ_IRQ_CLR 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR 2 0x334c 2 0 4294967295 RX_ADAPT_DIS_IRQ_CLR 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK 2 0x334d 12 0 4294967295 RX_REQ_IRQ_MSK 0 0 RX_RATE_IRQ_MSK 1 1 RX_PSTATE_IRQ_MSK 2 2 RX_ADAPT_REQ_IRQ_MSK 3 3 RX_ADAPT_DIS_IRQ_MSK 4 4 RX_RESET_IRQ_MSK 5 5 LANE_XCVR_MODE_IRQ_MSK 6 6 RX_PH2_CAL_REQ_IRQ_MSK 7 7 RX_PH2_CAL_DIS_IRQ_MSK 8 8 LANE_RX2TX_SER_LB_EN_IRQ_MSK 9 9 DCC_ONDMD_IRQ_MSK 10 10 RESERVED_15_11 11 15 ixDPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK_2 2 0x334e 3 0 4294967295 TX_RESET_IRQ_MSK 0 0 TX_REQ_IRQ_MSK 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ 2 0x334f 2 0 4294967295 LANE_XCVR_MODE_IRQ 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR 2 0x3350 2 0 4294967295 LANE_XCVR_MODE_IRQ_CLR 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ 2 0x3351 2 0 4294967295 RX_PH2_CAL_REQ_IRQ 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ 2 0x3352 2 0 4294967295 RX_PH2_CAL_DIS_IRQ 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR 2 0x3353 2 0 4294967295 RX_PH2_CAL_REQ_IRQ_CLR 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR 2 0x3354 2 0 4294967295 RX_PH2_CAL_DIS_IRQ_CLR 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ 2 0x3355 2 0 4294967295 LANE_RX2TX_SER_LB_EN_IRQ 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR 2 0x3356 2 0 4294967295 LANE_RX2TX_SER_LB_EN_IRQ_CLR 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_DCC_ONDMD_IRQ 2 0x3357 2 0 4294967295 IRQ 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_TX_RESET_IRQ 2 0x3358 2 0 4294967295 TX_RESET 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_TX_REQ_IRQ 2 0x3359 2 0 4294967295 TX_REQ 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_TX_RESET_IRQ_CLR 2 0x335a 2 0 4294967295 TX_RESET_IRQ_CLR 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_TX_REQ_IRQ_CLR 2 0x335b 2 0 4294967295 TX_REQ_IRQ_CLR 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_LANE_OVRD_IN 2 0x3360 4 0 4294967295 LANE_MPLLA_EN_IN 0 0 LANE_MPLLB_EN_IN 1 1 LANE_OVRD_EN 2 2 RESERVED_15_3 3 15 ixDPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_LANE_OVRD_OUT 2 0x3361 4 0 4294967295 LANE_MPLLA_EN_OUT 0 0 LANE_MPLLB_EN_OUT 1 1 LANE_OVRD_EN 2 2 RESERVED_15_3 3 15 ixDPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_SUP_OVRD_IN 2 0x3362 4 0 4294967295 MPLLA_STATE 0 0 MPLLB_STATE 1 1 SUP_STATE_OVRD_EN 2 2 RESERVED_15_3 3 15 ixDPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_SUP_PMA_IN 2 0x3363 3 0 4294967295 MPLLA_STATE 0 0 MPLLB_STATE 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT 2 0x3364 16 0 4294967295 TX_REQ_OVRD_VAL 0 0 TX_REQ_OVRD_EN 1 1 TX_RESET_OVRD_VAL 2 2 TX_RESET_OVRD_EN 3 3 TX_BEACON_EN_OVRD_VAL 4 4 TX_BEACON_EN_OVRD_EN 5 5 TX_ASYNC_DRV_EN_OVRD_VAL 6 6 TX_ASYNC_DRV_EN_OVRD_EN 7 7 TX_ASYNC_EN_OVRD_VAL 8 8 TX_ASYNC_EN_OVRD_EN 9 9 TX_DWORD_CLK_SYNC_OVRD_VAL 10 10 TX_DWORD_CLK_SYNC_OVRD_EN 11 11 LANE_TX2RX_SER_LB_EN_OVRD_VAL 12 12 LANE_TX2RX_SER_LB_EN_OVRD_EN 13 13 TX_PMA_DATA_EN_OVRD_VAL_R 14 14 TX_PMA_DATA_EN_OVRD_EN_R 15 15 ixDPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_TX_PMA_IN 2 0x3365 2 0 4294967295 ACK 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT 2 0x3366 9 0 4294967295 RX_REQ_OVRD_VAL 0 0 RX_REQ_OVRD_EN 1 1 RX_RESET_OVRD_VAL 2 2 RX_RESET_OVRD_EN 3 3 LANE_RX2TX_PAR_LB_EN_OVRD_VAL 4 4 LANE_RX2TX_PAR_LB_EN_OVRD_EN 5 5 RX_PMA_DATA_EN_OVRD_VAL_R 6 6 RX_PMA_DATA_EN_OVRD_EN_R 7 7 RESERVED_15_8 8 15 ixDPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_RX_PMA_IN 2 0x3367 2 0 4294967295 ACK 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_LANE_RTUNE_CTL 2 0x3368 2 0 4294967295 LANE_RTUNE_REQ 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_SUP_PMA_IN_1 2 0x3369 2 0 4294967295 RTUNE_ACK 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_IN 2 0x336a 9 0 4294967295 RX_PMA_PWM_WORD_CLK_R 0 0 RX_PMA_PWM_WORD_CLK_OVRD_EN 1 1 RX_PMA_PWM_DATA_R 2 2 RX_PMA_PWM_DATA_OVRD_EN 3 3 RX_PMA_PWM_CLK_R 4 4 RX_PMA_PWM_CLK_OVRD_EN 5 5 RX_PMA_TERM_CTL_R 6 7 RX_PMA_TERM_CTL_OVRD_EN 8 8 RESERVED_15_9 9 15 ixDPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_OUT 2 0x336b 7 0 4294967295 RX_PMA_PWM_EN 0 0 RX_PMA_PWM_EN_OVRD_EN 1 1 RX_PMA_PWM_CLK_SEL 2 3 RX_PMA_PWM_CLK_SEL_OVRD_EN 4 4 RX_PMA_ASYNC_EN 5 5 RX_PMA_ASYNC_EN_OVRD_EN 6 6 RESERVED_15_7 7 15 ixDPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_RX_ADAPT_OVRD_OUT 2 0x336c 3 0 4294967295 RX_PMA_IQ_PHASE_ADJUST_MAP_OVRD_VAL 0 6 RX_PMA_IQ_PHASE_ADJUST_MAP_OVRD_EN 7 7 RESERVED_15_8 8 15 ixDPCSSYS_CR1_RAWLANE3_DIG_TX_CTL_TX_FSM_CTL 2 0x3380 6 0 4294967295 TX_WAIT_MPLL_OFF_TIME 0 6 TX_P2_ALLOW_RXDET 7 7 TX_P1_ALLOW_RXDET 8 8 TX_P0S_ALLOW_RXDET 9 9 TX_P0_ALLOW_RXDET 10 10 RESERVED_15_11 11 15 ixDPCSSYS_CR1_RAWLANE3_DIG_TX_CTL_TX_CLK_CTL 2 0x3381 4 0 4294967295 TX_CLK_EN 0 0 TX_CLK_SEL 1 4 ASYNC_BEACON_WAIT_TIME 5 10 RESERVED_15_11 11 15 ixDPCSSYS_CR1_RAWLANE3_DIG_TX_CTL_TX_DCC_CONT_STATUS 2 0x3382 2 0 4294967295 ENABLE 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR1_RAWLANE3_DIG_TX_CTL_OCLA 2 0x3383 2 0 4294967295 FSM_EN 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR1_RAWLANE3_DIG_TX_CTL_UPCS_OCLA 2 0x3384 3 0 4294967295 DATA_EN 0 1 CLK_EN 2 2 RESERVED_15_3 3 15 ixDPCSSYS_CR1_RAWLANE3_DIG_RX_CTL_RX_FSM_CTL 2 0x33a0 3 0 4294967295 EN_RX_CTL_FSM 0 0 RATE_CHG_IN_P1 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR1_RAWLANE3_DIG_RX_CTL_RX_LOS_MASK_CTL 2 0x33a1 2 0 4294967295 RX_LOS_MASK_CNT 0 8 RESERVED_15_9 9 15 ixDPCSSYS_CR1_RAWLANE3_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL 2 0x33a2 2 0 4294967295 RX_DATA_EN_OVRD_CNT 0 4 INT_REF_TRCK_CNT 5 15 ixDPCSSYS_CR1_RAWLANE3_DIG_RX_CTL_OFFCAN_CONT_STATUS 2 0x33a3 2 0 4294967295 ENABLE 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR1_RAWLANE3_DIG_RX_CTL_ADAPT_CONT_STATUS 2 0x33a4 2 0 4294967295 ENABLE 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR1_RAWLANE3_DIG_RX_CTL_UPCS_OCLA 2 0x33a5 3 0 4294967295 DATA_EN 0 2 CLK_EN 3 3 RESERVED_15_4 4 15 ixDPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN 2 0x33c0 11 0 4294967295 RATE_OVRD_VAL 0 1 RATE_OVRD_EN 2 2 WIDTH_OVRD_VAL 3 4 WIDTH_OVRD_EN 5 5 PSTATE_OVRD_VAL 6 7 PSTATE_OVRD_EN 8 8 LPD_OVRD_VAL 9 9 LPD_OVRD_EN 10 10 LANE_RX2TX_PAR_LB_EN_OVRD_VAL 11 11 LANE_RX2TX_PAR_LB_EN_OVRD_EN 12 12 RESERVED_15_13 13 15 ixDPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN 2 0x33c1 12 0 4294967295 PSTATE 0 1 LPD 2 2 WIDTH 3 4 RATE 5 7 MPLLB_SEL 8 8 MPLL_EN 9 9 OVRD_EN 10 10 MSTR_MPLLA_STATE 11 11 MSTR_MPLLB_STATE 12 12 MSTR_MPLL_OVRD_EN 13 13 TX_ASYNC_EN_OVR_VAL 14 14 TX_ASYNC_EN_OVR_EN 15 15 ixDPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1 2 0x33c2 13 0 4294967295 DETRX_REQ_OVRD_VAL 0 0 DETRX_REQ_OVRD_EN 1 1 VBOOST_EN_OVRD_VAL 2 2 VBOOST_EN_OVRD_EN 3 3 IBOOST_LVL_OVRD_VAL 4 7 IBOOST_LVL_OVRD_EN 8 8 TX_BEACON_EN_OVR_VAL 9 9 TX_BEACON_EN_OVR_EN 10 10 LANE_TX2RX_SER_LB_EN_OVRD_VAL 11 11 LANE_TX2RX_SER_LB_EN_OVRD_EN 12 12 TX_ASYNC_DATA_OVRD_VAL 13 13 TX_ASYNC_DATA_OVRD_EN 14 14 RESERVED_15_15 15 15 ixDPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_MASTER_MPLL_LOOP 2 0x33c3 3 0 4294967295 MPLLB_LOOP_EN 0 0 MPLLA_LOOP_EN 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1 2 0x33c4 11 0 4294967295 RESERVED 0 1 RX_LOS_LFPS_EN_OVRD_VAL 2 2 RX_LOS_LFPS_EN_OVRD_EN 3 3 RX_LOS_THRSHLD_OVRD_VAL 4 6 RX_LOS_THRSHLD_OVRD_EN 7 7 ADAPT_REQ 8 8 ADAPT_REQ_OVRD_EN 9 9 ADAPT_CONT 10 10 OFFCAN_CONT 11 11 CONT_OVRD_EN 12 12 RESERVED_15_13 13 15 ixDPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_2 2 0x33c5 4 0 4294967295 VCO_LD_VAL_OVRD 0 12 VCO_LD_VAL_OVRD_EN 13 13 VCO_LOWFREQ_VAL_OVRD 14 14 VCO_LOWFREQ_VAL_OVRD_EN 15 15 ixDPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_3 2 0x33c6 3 0 4294967295 REF_LD_VAL_OVRD 0 6 REF_LD_VAL_OVRD_EN 7 7 RESERVED_15_8 8 15 ixDPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT_2 2 0x33c7 3 0 4294967295 RX_VALID 0 0 RX_VALID_OVRD_EN 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_2 2 0x33c8 7 0 4294967295 LANE_TX2RX_SER_LB_EN_OVRD_VAL 0 0 LANE_TX2RX_SER_LB_EN_OVRD_EN 1 1 TX_DATA_EN_OVRD_VAL_R 2 2 TX_DATA_EN_OVRD_EN_R 3 3 TX_ASYNC_DATA_OVRD_VAL_R 4 4 TX_ASYNC_DATA_OVRD_EN_R 5 5 RESERVED_15_6 6 15 ixDPCSSYS_CR1_RAWAONLANE0_DIG_AFE_ATT_IDAC_OFST 2 0x4000 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR1_RAWAONLANE0_DIG_AFE_CTLE_IDAC_OFST 2 0x4001 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR1_RAWAONLANE0_DIG_RX_ADPT_IQ 2 0x4002 2 0 4294967295 IQ_ADPT_VAL 0 6 RESERVED_15_7 7 15 ixDPCSSYS_CR1_RAWAONLANE0_DIG_RX_ADAPT_FOM 2 0x4003 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR1_RAWAONLANE0_DIG_DFE_SUMMER_ODD_IDAC_OFST 2 0x4004 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR1_RAWAONLANE0_DIG_DFE_PHASE_EVEN_VDAC_OFST 2 0x4005 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR1_RAWAONLANE0_DIG_DFE_PHASE_ODD_VDAC_OFST 2 0x4006 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR1_RAWAONLANE0_DIG_DFE_EVEN_REF_LVL 2 0x4007 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR1_RAWAONLANE0_DIG_DFE_ODD_REF_LVL 2 0x4008 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR1_RAWAONLANE0_DIG_RX_PHSADJ_LIN 2 0x4009 2 0 4294967295 DATA 0 0 RESERVED_15_5 5 15 ixDPCSSYS_CR1_RAWAONLANE0_DIG_RX_PHSADJ_MAP 2 0x400a 2 0 4294967295 DATA 0 0 RESERVED_15_5 5 15 ixDPCSSYS_CR1_RAWAONLANE0_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST 2 0x400b 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR1_RAWAONLANE0_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST 2 0x400c 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR1_RAWAONLANE0_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST 2 0x400d 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR1_RAWAONLANE0_DIG_DFE_DATA_ODD_LOW_VDAC_OFST 2 0x400e 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR1_RAWAONLANE0_DIG_DFE_BYPASS_EVEN_VDAC_OFST 2 0x400f 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR1_RAWAONLANE0_DIG_DFE_BYPASS_ODD_VDAC_OFST 2 0x4010 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR1_RAWAONLANE0_DIG_DFE_ERROR_EVEN_VDAC_OFST 2 0x4011 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR1_RAWAONLANE0_DIG_DFE_ERROR_ODD_VDAC_OFST 2 0x4012 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR1_RAWAONLANE0_DIG_RX_IQ_PHASE_ADJUST 2 0x4013 2 0 4294967295 DATA 0 0 RESERVED_15_7 7 15 ixDPCSSYS_CR1_RAWAONLANE0_DIG_MPLLA_COARSE_TUNE 2 0x4014 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR1_RAWAONLANE0_DIG_MPLLB_COARSE_TUNE 2 0x4015 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR1_RAWAONLANE0_DIG_INIT_PWRUP_DONE 2 0x4016 3 0 4294967295 DATA 0 0 PH2_PWRUP_DONE 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR1_RAWAONLANE0_DIG_RX_ADPT_ATT 2 0x4017 2 0 4294967295 ATT_ADPT_VAL 0 7 RESERVED_15_8 8 15 ixDPCSSYS_CR1_RAWAONLANE0_DIG_RX_ADPT_VGA 2 0x4018 2 0 4294967295 VGA_ADPT_VAL 0 9 RESERVED_15_10 10 15 ixDPCSSYS_CR1_RAWAONLANE0_DIG_RX_ADPT_CTLE 2 0x4019 3 0 4294967295 CTLE_BOOST_ADPT_VAL 0 9 CTLE_POLE_ADPT_VAL 10 12 RESERVED_15_13 13 15 ixDPCSSYS_CR1_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP1 2 0x401a 2 0 4294967295 DFE_TAP1_ADPT_VAL 0 12 RESERVED_15_13 13 15 ixDPCSSYS_CR1_RAWAONLANE0_DIG_RX_ADAPT_DONE 2 0x401b 2 0 4294967295 DATA 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR1_RAWAONLANE0_DIG_FAST_FLAGS 2 0x401c 16 0 4294967295 FAST_RX_STARTUP_CAL 0 0 FAST_RX_ADAPT 1 1 FAST_RX_AFE_CAL 2 2 FAST_RX_DFE_CAL 3 3 FAST_RX_BYPASS_CAL 4 4 FAST_RX_REFLVL_CAL 5 5 FAST_RX_IQ_CAL 6 6 FAST_RX_AFE_ADAPT 7 7 FAST_RX_DFE_ADAPT 8 8 FAST_SUP 9 9 FAST_TX_CMN_MODE 10 10 FAST_TX_RXDET 11 11 FAST_RX_PWRUP 12 12 FAST_RX_VCO_WAIT 13 13 FAST_RX_VCO_CAL 14 14 RESERVED_15_15 15 15 ixDPCSSYS_CR1_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP2 2 0x401d 2 0 4294967295 DFE_TAP2_ADPT_VAL 0 11 RESERVED_15_12 12 15 ixDPCSSYS_CR1_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP3 2 0x401e 2 0 4294967295 DFE_TAP3_ADPT_VAL 0 11 RESERVED_15_12 12 15 ixDPCSSYS_CR1_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP4 2 0x401f 2 0 4294967295 DFE_TAP4_ADPT_VAL 0 11 RESERVED_15_12 12 15 ixDPCSSYS_CR1_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP5 2 0x4020 2 0 4294967295 DFE_TAP5_ADPT_VAL 0 11 RESERVED_15_12 12 15 ixDPCSSYS_CR1_RAWAONLANE0_DIG_RX_SLICER_CTRL_EVEN 2 0x4021 2 0 4294967295 RX_ANA_SLICER_CTRL_E 0 3 RESERVED_15_4 4 15 ixDPCSSYS_CR1_RAWAONLANE0_DIG_RX_SLICER_CTRL_ODD 2 0x4022 2 0 4294967295 RX_ANA_SLICER_CTRL_O 0 3 RESERVED_15_4 4 15 ixDPCSSYS_CR1_RAWAONLANE0_DIG_LANE_CMNCAL_MPLL_STATUS 2 0x4023 3 0 4294967295 LANE_CMNCAL_MPLL_INIT 0 0 LANE_CMNCAL_MPLL_DONE 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR1_RAWAONLANE0_DIG_ADPT_CTL_0 2 0x4024 1 0 4294967295 VAL 0 15 ixDPCSSYS_CR1_RAWAONLANE0_DIG_ADPT_CTL_1 2 0x4025 1 0 4294967295 VAL 0 15 ixDPCSSYS_CR1_RAWAONLANE0_DIG_ADPT_CTL_2 2 0x4026 1 0 4294967295 VAL 0 15 ixDPCSSYS_CR1_RAWAONLANE0_DIG_ADPT_CTL_3 2 0x4027 1 0 4294967295 VAL 0 15 ixDPCSSYS_CR1_RAWAONLANE0_DIG_ADPT_CTL_4 2 0x4028 1 0 4294967295 VAL 0 15 ixDPCSSYS_CR1_RAWAONLANE0_DIG_ADPT_CTL_5 2 0x4029 1 0 4294967295 VAL 0 15 ixDPCSSYS_CR1_RAWAONLANE0_DIG_ADPT_CTL_6 2 0x402a 1 0 4294967295 VAL 0 15 ixDPCSSYS_CR1_RAWAONLANE0_DIG_ADPT_CTL_7 2 0x402b 1 0 4294967295 VAL 0 15 ixDPCSSYS_CR1_RAWAONLANE0_DIG_MPLL_DISABLE 2 0x402c 3 0 4294967295 LANE_MPLLA_DISABLE 0 0 LANE_MPLLB_DISABLE 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR1_RAWAONLANE0_DIG_FAST_FLAGS_2 2 0x402d 16 0 4294967295 FAST_RX_CONT_CAL_ADAPT 0 0 FAST_RX_CONT_ADAPT 1 1 FAST_RX_CONT_DATA_CAL 2 2 FAST_RX_CONT_PHASE_CAL 3 3 FAST_RX_CONT_AFE_CAL 4 4 FAST_TX_CONT_DCC_CAL 5 5 FAST_RX_CONT_DCC_CAL 6 6 FAST_RX_CONT_VPHUD_CAL 7 7 FAST_RX_CONT_VREF_CAL 8 8 FAST_TX_DCC_CAL 9 9 FAST_RX_DCC_CAL 10 10 FAST_RX_VPHUD_CAL 11 11 FAST_RX_VREF_CAL 12 12 SKIP_TX_RTUNE_CAL 13 13 FAST_RX_SIGDET_CAL 14 14 RESERVED_15_15 15 15 ixDPCSSYS_CR1_RAWAONLANE0_DIG_LANE_CMNCAL_RCAL_STATUS 2 0x402e 3 0 4294967295 LANE_CMNCAL_RCAL_INIT 0 0 LANE_CMNCAL_RCAL_DONE 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR1_RAWAONLANE0_DIG_TXRX_OVRD_IN 2 0x402f 5 0 4294967295 RX_DISABLE_OVRD_VAL 0 0 RX_DISABLE_OVRD_EN 1 1 TX_DISABLE_OVRD_VAL 2 2 TX_DISABLE_OVRD_EN 3 3 RESERVED_15_4 4 15 ixDPCSSYS_CR1_RAWAONLANE0_DIG_RX_LOS_MASK_CTL 2 0x4030 2 0 4294967295 RX_LOS_MASK_CNT 0 8 RESERVED_15_9 9 15 ixDPCSSYS_CR1_RAWAONLANE0_DIG_RX_SIGDET_FILT_CTRL 2 0x4031 5 0 4294967295 ISOLATE_SIGDET_HF 0 0 RX_SIGDEF_HF_FILT_OVR_DIS 1 1 RX_SIGDEF_HF_FILT_OVR 2 2 RX_SIGDET_LF_OUT_FILT_EN 3 3 RESERVED_15_4 4 15 ixDPCSSYS_CR1_RAWAONLANE0_DIG_STATS 2 0x4032 3 0 4294967295 RX_VREFGEN_MASTER 0 0 RX_PMA_SQ_OUT 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR1_RAWAONLANE0_DIG_RX_OVRD_OUT_1 2 0x4033 11 0 4294967295 RX_PMA_SQ_CTRL_TRESH_OVRD_VAL 0 2 RX_PMA_SQ_CTRL_TRESH_OVRD_EN 3 3 RX_PMA_SQ_CTRL_RESP_OVRD_VAL 4 5 RX_PMA_SQ_CTRL_RESP_OVRD_EN 6 6 RX_PMA_SQ_WEAKKEEP_OVRD_VAL 7 7 RX_PMA_SQ_WEAKKEEP_OVRD_EN 8 8 RX_PMA_SQ_INV_POLARITY_OVRD_VAL 9 9 RX_PMA_SQ_INV_POLARITY_OVRD_EN 10 10 RX_PMA_SQ_EN_OVRD_VAL 11 11 RX_PMA_SQ_EN_OVRD_EN 12 12 RESERVED_15_13 13 15 ixDPCSSYS_CR1_RAWAONLANE0_DIG_RX_OVRD_OUT_2 2 0x4034 9 0 4294967295 RX_PMA_VREFGEN_EN_OVRD_VAL 0 0 RX_PMA_VREFGEN_EN_OVRD_EN 1 1 RX_SQ_OUT_OVRD_VAL 2 2 RX_SQ_OUT_OVRD_EN 3 3 RX_PMA_TERM_ACDC_OVRD_VAL 4 4 RX_PMA_TERM_ACDC_OVRD_EN 5 5 RX_PMA_TERM_EN_OVRD_VAL 6 6 RX_PMA_TERM_EN_OVRD_EN 7 7 RESERVED_15_8 8 15 ixDPCSSYS_CR1_RAWAONLANE0_DIG_RX_OVRD_OUT_3 2 0x4035 7 0 4294967295 RX_PMA_SIGDET_LF_FILTER_EN_OVRD_VAL 0 0 RX_PMA_SIGDET_LF_FILTER_EN_OVRD_EN 1 1 RX_PMA_SIGDET_LF_EN_OVRD_VAL 2 2 RX_PMA_SIGDET_LF_EN_OVRD_EN 3 3 RX_PMA_SIGDET_HF_EN_OVRD_VAL 4 4 RX_PMA_SIGDET_HF_EN_OVRD_EN 5 5 RESERVED_15_6 6 15 ixDPCSSYS_CR1_RAWAONLANE0_DIG_RX_SIGDET_CAL 2 0x4036 4 0 4294967295 RX_PMA_SIGDET_LF_THRESHOLD 0 2 RX_PMA_SIGDET_HF_THRESHOLD 3 5 RX_PMA_SIGDET_CAL_EN 6 6 RESERVED_15_7 7 15 ixDPCSSYS_CR1_RAWAONLANE0_DIG_RX_SIGDET_HF_CODE 2 0x4037 2 0 4294967295 RX_PMA_SIGDET_HF_CAL_TUNE 0 5 RESERVED_15_6 6 15 ixDPCSSYS_CR1_RAWAONLANE0_DIG_RX_SIGDET_LF_CODE 2 0x4038 2 0 4294967295 RX_PMA_SIGDET_LF_CAL_TUNE 0 5 RESERVED_15_6 6 15 ixDPCSSYS_CR1_RAWAONLANE0_DIG_RX_VREFGEN_EN 2 0x4039 2 0 4294967295 PULL_UP 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR1_RAWAONLANE0_DIG_CAL_IOFF_CODE 2 0x403a 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR1_RAWAONLANE0_DIG_CAL_ICONST_CODE 2 0x403b 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR1_RAWAONLANE0_DIG_CAL_VREFGEN_CODE 2 0x403c 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR1_RAWAONLANE0_DIG_RX_DCC_CAL_ICM_CODE_0 2 0x403d 2 0 4294967295 RX_DCC_CAL_ICM_CODE 0 9 RESERVED_15_10 10 15 ixDPCSSYS_CR1_RAWAONLANE0_DIG_RX_DCC_CAL_IDF_CODE_0 2 0x403e 2 0 4294967295 RX_DCC_CAL_IDF_CODE 0 9 RESERVED_15_10 10 15 ixDPCSSYS_CR1_RAWAONLANE0_DIG_RX_DCC_CAL_QCM_CODE_0 2 0x403f 2 0 4294967295 RX_DCC_CAL_QCM_CODE 0 9 RESERVED_15_10 10 15 ixDPCSSYS_CR1_RAWAONLANE0_DIG_RX_DCC_CAL_QDF_CODE_0 2 0x4040 2 0 4294967295 RX_DCC_CAL_QDF_CODE 0 9 RESERVED_15_10 10 15 ixDPCSSYS_CR1_RAWAONLANE0_DIG_RX_DCC_CAL_ICM_CODE_1 2 0x4041 2 0 4294967295 RX_DCC_CAL_ICM_CODE 0 9 RESERVED_15_10 10 15 ixDPCSSYS_CR1_RAWAONLANE0_DIG_RX_DCC_CAL_IDF_CODE_1 2 0x4042 2 0 4294967295 RX_DCC_CAL_IDF_CODE 0 9 RESERVED_15_10 10 15 ixDPCSSYS_CR1_RAWAONLANE0_DIG_RX_DCC_CAL_QCM_CODE_1 2 0x4043 2 0 4294967295 RX_DCC_CAL_QCM_CODE 0 9 RESERVED_15_10 10 15 ixDPCSSYS_CR1_RAWAONLANE0_DIG_RX_DCC_CAL_QDF_CODE_1 2 0x4044 2 0 4294967295 RX_DCC_CAL_QDF_CODE 0 9 RESERVED_15_10 10 15 ixDPCSSYS_CR1_RAWAONLANE0_DIG_TX_DCC_BANK_ADDR 2 0x4045 1 0 4294967295 ADDR 0 15 ixDPCSSYS_CR1_RAWAONLANE0_DIG_TX_DCC_BANK_DATA 2 0x4046 1 0 4294967295 DATA 0 15 ixDPCSSYS_CR1_RAWAONLANE0_DIG_TX_DCC_CONT 2 0x4047 2 0 4294967295 EN 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR1_RAWAONLANE0_DIG_MPLL_BG_CTL 2 0x4048 3 0 4294967295 MPLL_STATE_WAIT 0 0 MPLL_STATE_DLY_EN 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR1_RAWAONLANE0_DIG_SIGDET_OUT_OVRD 2 0x4049 5 0 4294967295 RX_SIGDET_HF_OUT_OVRD_VAL 0 0 RX_SIGDET_HF_OUT_OVRD_EN 1 1 RX_SIGDET_LF_OUT_OVRD_VAL 2 2 RX_SIGDET_LF_OUT_OVRD_EN 3 3 RESERVED_15_4 4 15 ixDPCSSYS_CR1_RAWAONLANE0_DIG_SIGDET_OUT_IN 2 0x404a 3 0 4294967295 RX_SIGDET_HF_OUT_OVRD_VAL 0 0 RX_SIGDET_LF_OUT_OVRD_VAL 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR1_RAWAONLANE0_DIG_FW_MM_CONFIG 2 0x404b 1 0 4294967295 DATA 0 0 ixDPCSSYS_CR1_RAWAONLANE0_DIG_FW_ADPT_CONFIG 2 0x404c 2 0 4294967295 REF_LVL_ADPT 0 7 FW_CONFIG 8 15 ixDPCSSYS_CR1_RAWAONLANE0_DIG_FW_CALIB_CONFIG 2 0x404d 1 0 4294967295 FW_CALIB 0 15 ixDPCSSYS_CR1_RAWAONLANE0_DIG_LANE_XCVR_MODE_OVRD_IN 2 0x404e 3 0 4294967295 LANE_XCVR_MODE_OVRD_VAL 0 1 LANE_XCVR_MODE_OVRD_EN 2 2 RESERVED_15_3 3 15 ixDPCSSYS_CR1_RAWAONLANE0_DIG_LANE_XCVR_MODE_IN 2 0x404f 2 0 4294967295 LANE_XCVR_MODE 0 1 RESERVED_15_2 2 15 ixDPCSSYS_CR1_RAWAONLANE0_DIG_RX_SIGDET_CONFIG 2 0x4050 4 0 4294967295 RX_SIGDET_HF_FILTER_COUNTER 0 4 RX_SIGDET_LF_FILTER_COUNTER 5 9 RX_SIGDET_LF_HOLD 10 10 RESERVED_15_11 11 15 ixDPCSSYS_CR1_RAWAONLANE0_DIG_TX_DCC_CONFIG 2 0x4051 1 0 4294967295 DATA 0 0 ixDPCSSYS_CR1_RAWAONLANE1_DIG_AFE_ATT_IDAC_OFST 2 0x4100 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR1_RAWAONLANE1_DIG_AFE_CTLE_IDAC_OFST 2 0x4101 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR1_RAWAONLANE1_DIG_RX_ADPT_IQ 2 0x4102 2 0 4294967295 IQ_ADPT_VAL 0 6 RESERVED_15_7 7 15 ixDPCSSYS_CR1_RAWAONLANE1_DIG_RX_ADAPT_FOM 2 0x4103 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR1_RAWAONLANE1_DIG_DFE_SUMMER_ODD_IDAC_OFST 2 0x4104 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR1_RAWAONLANE1_DIG_DFE_PHASE_EVEN_VDAC_OFST 2 0x4105 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR1_RAWAONLANE1_DIG_DFE_PHASE_ODD_VDAC_OFST 2 0x4106 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR1_RAWAONLANE1_DIG_DFE_EVEN_REF_LVL 2 0x4107 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR1_RAWAONLANE1_DIG_DFE_ODD_REF_LVL 2 0x4108 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR1_RAWAONLANE1_DIG_RX_PHSADJ_LIN 2 0x4109 2 0 4294967295 DATA 0 0 RESERVED_15_5 5 15 ixDPCSSYS_CR1_RAWAONLANE1_DIG_RX_PHSADJ_MAP 2 0x410a 2 0 4294967295 DATA 0 0 RESERVED_15_5 5 15 ixDPCSSYS_CR1_RAWAONLANE1_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST 2 0x410b 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR1_RAWAONLANE1_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST 2 0x410c 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR1_RAWAONLANE1_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST 2 0x410d 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR1_RAWAONLANE1_DIG_DFE_DATA_ODD_LOW_VDAC_OFST 2 0x410e 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR1_RAWAONLANE1_DIG_DFE_BYPASS_EVEN_VDAC_OFST 2 0x410f 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR1_RAWAONLANE1_DIG_DFE_BYPASS_ODD_VDAC_OFST 2 0x4110 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR1_RAWAONLANE1_DIG_DFE_ERROR_EVEN_VDAC_OFST 2 0x4111 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR1_RAWAONLANE1_DIG_DFE_ERROR_ODD_VDAC_OFST 2 0x4112 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR1_RAWAONLANE1_DIG_RX_IQ_PHASE_ADJUST 2 0x4113 2 0 4294967295 DATA 0 0 RESERVED_15_7 7 15 ixDPCSSYS_CR1_RAWAONLANE1_DIG_MPLLA_COARSE_TUNE 2 0x4114 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR1_RAWAONLANE1_DIG_MPLLB_COARSE_TUNE 2 0x4115 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR1_RAWAONLANE1_DIG_INIT_PWRUP_DONE 2 0x4116 3 0 4294967295 DATA 0 0 PH2_PWRUP_DONE 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR1_RAWAONLANE1_DIG_RX_ADPT_ATT 2 0x4117 2 0 4294967295 ATT_ADPT_VAL 0 7 RESERVED_15_8 8 15 ixDPCSSYS_CR1_RAWAONLANE1_DIG_RX_ADPT_VGA 2 0x4118 2 0 4294967295 VGA_ADPT_VAL 0 9 RESERVED_15_10 10 15 ixDPCSSYS_CR1_RAWAONLANE1_DIG_RX_ADPT_CTLE 2 0x4119 3 0 4294967295 CTLE_BOOST_ADPT_VAL 0 9 CTLE_POLE_ADPT_VAL 10 12 RESERVED_15_13 13 15 ixDPCSSYS_CR1_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP1 2 0x411a 2 0 4294967295 DFE_TAP1_ADPT_VAL 0 12 RESERVED_15_13 13 15 ixDPCSSYS_CR1_RAWAONLANE1_DIG_RX_ADAPT_DONE 2 0x411b 2 0 4294967295 DATA 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR1_RAWAONLANE1_DIG_FAST_FLAGS 2 0x411c 16 0 4294967295 FAST_RX_STARTUP_CAL 0 0 FAST_RX_ADAPT 1 1 FAST_RX_AFE_CAL 2 2 FAST_RX_DFE_CAL 3 3 FAST_RX_BYPASS_CAL 4 4 FAST_RX_REFLVL_CAL 5 5 FAST_RX_IQ_CAL 6 6 FAST_RX_AFE_ADAPT 7 7 FAST_RX_DFE_ADAPT 8 8 FAST_SUP 9 9 FAST_TX_CMN_MODE 10 10 FAST_TX_RXDET 11 11 FAST_RX_PWRUP 12 12 FAST_RX_VCO_WAIT 13 13 FAST_RX_VCO_CAL 14 14 RESERVED_15_15 15 15 ixDPCSSYS_CR1_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP2 2 0x411d 2 0 4294967295 DFE_TAP2_ADPT_VAL 0 11 RESERVED_15_12 12 15 ixDPCSSYS_CR1_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP3 2 0x411e 2 0 4294967295 DFE_TAP3_ADPT_VAL 0 11 RESERVED_15_12 12 15 ixDPCSSYS_CR1_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP4 2 0x411f 2 0 4294967295 DFE_TAP4_ADPT_VAL 0 11 RESERVED_15_12 12 15 ixDPCSSYS_CR1_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP5 2 0x4120 2 0 4294967295 DFE_TAP5_ADPT_VAL 0 11 RESERVED_15_12 12 15 ixDPCSSYS_CR1_RAWAONLANE1_DIG_RX_SLICER_CTRL_EVEN 2 0x4121 2 0 4294967295 RX_ANA_SLICER_CTRL_E 0 3 RESERVED_15_4 4 15 ixDPCSSYS_CR1_RAWAONLANE1_DIG_RX_SLICER_CTRL_ODD 2 0x4122 2 0 4294967295 RX_ANA_SLICER_CTRL_O 0 3 RESERVED_15_4 4 15 ixDPCSSYS_CR1_RAWAONLANE1_DIG_LANE_CMNCAL_MPLL_STATUS 2 0x4123 3 0 4294967295 LANE_CMNCAL_MPLL_INIT 0 0 LANE_CMNCAL_MPLL_DONE 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR1_RAWAONLANE1_DIG_ADPT_CTL_0 2 0x4124 1 0 4294967295 VAL 0 15 ixDPCSSYS_CR1_RAWAONLANE1_DIG_ADPT_CTL_1 2 0x4125 1 0 4294967295 VAL 0 15 ixDPCSSYS_CR1_RAWAONLANE1_DIG_ADPT_CTL_2 2 0x4126 1 0 4294967295 VAL 0 15 ixDPCSSYS_CR1_RAWAONLANE1_DIG_ADPT_CTL_3 2 0x4127 1 0 4294967295 VAL 0 15 ixDPCSSYS_CR1_RAWAONLANE1_DIG_ADPT_CTL_4 2 0x4128 1 0 4294967295 VAL 0 15 ixDPCSSYS_CR1_RAWAONLANE1_DIG_ADPT_CTL_5 2 0x4129 1 0 4294967295 VAL 0 15 ixDPCSSYS_CR1_RAWAONLANE1_DIG_ADPT_CTL_6 2 0x412a 1 0 4294967295 VAL 0 15 ixDPCSSYS_CR1_RAWAONLANE1_DIG_ADPT_CTL_7 2 0x412b 1 0 4294967295 VAL 0 15 ixDPCSSYS_CR1_RAWAONLANE1_DIG_MPLL_DISABLE 2 0x412c 3 0 4294967295 LANE_MPLLA_DISABLE 0 0 LANE_MPLLB_DISABLE 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR1_RAWAONLANE1_DIG_FAST_FLAGS_2 2 0x412d 16 0 4294967295 FAST_RX_CONT_CAL_ADAPT 0 0 FAST_RX_CONT_ADAPT 1 1 FAST_RX_CONT_DATA_CAL 2 2 FAST_RX_CONT_PHASE_CAL 3 3 FAST_RX_CONT_AFE_CAL 4 4 FAST_TX_CONT_DCC_CAL 5 5 FAST_RX_CONT_DCC_CAL 6 6 FAST_RX_CONT_VPHUD_CAL 7 7 FAST_RX_CONT_VREF_CAL 8 8 FAST_TX_DCC_CAL 9 9 FAST_RX_DCC_CAL 10 10 FAST_RX_VPHUD_CAL 11 11 FAST_RX_VREF_CAL 12 12 SKIP_TX_RTUNE_CAL 13 13 FAST_RX_SIGDET_CAL 14 14 RESERVED_15_15 15 15 ixDPCSSYS_CR1_RAWAONLANE1_DIG_LANE_CMNCAL_RCAL_STATUS 2 0x412e 3 0 4294967295 LANE_CMNCAL_RCAL_INIT 0 0 LANE_CMNCAL_RCAL_DONE 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR1_RAWAONLANE1_DIG_TXRX_OVRD_IN 2 0x412f 5 0 4294967295 RX_DISABLE_OVRD_VAL 0 0 RX_DISABLE_OVRD_EN 1 1 TX_DISABLE_OVRD_VAL 2 2 TX_DISABLE_OVRD_EN 3 3 RESERVED_15_4 4 15 ixDPCSSYS_CR1_RAWAONLANE1_DIG_RX_LOS_MASK_CTL 2 0x4130 2 0 4294967295 RX_LOS_MASK_CNT 0 8 RESERVED_15_9 9 15 ixDPCSSYS_CR1_RAWAONLANE1_DIG_RX_SIGDET_FILT_CTRL 2 0x4131 5 0 4294967295 ISOLATE_SIGDET_HF 0 0 RX_SIGDEF_HF_FILT_OVR_DIS 1 1 RX_SIGDEF_HF_FILT_OVR 2 2 RX_SIGDET_LF_OUT_FILT_EN 3 3 RESERVED_15_4 4 15 ixDPCSSYS_CR1_RAWAONLANE1_DIG_STATS 2 0x4132 3 0 4294967295 RX_VREFGEN_MASTER 0 0 RX_PMA_SQ_OUT 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR1_RAWAONLANE1_DIG_RX_OVRD_OUT_1 2 0x4133 11 0 4294967295 RX_PMA_SQ_CTRL_TRESH_OVRD_VAL 0 2 RX_PMA_SQ_CTRL_TRESH_OVRD_EN 3 3 RX_PMA_SQ_CTRL_RESP_OVRD_VAL 4 5 RX_PMA_SQ_CTRL_RESP_OVRD_EN 6 6 RX_PMA_SQ_WEAKKEEP_OVRD_VAL 7 7 RX_PMA_SQ_WEAKKEEP_OVRD_EN 8 8 RX_PMA_SQ_INV_POLARITY_OVRD_VAL 9 9 RX_PMA_SQ_INV_POLARITY_OVRD_EN 10 10 RX_PMA_SQ_EN_OVRD_VAL 11 11 RX_PMA_SQ_EN_OVRD_EN 12 12 RESERVED_15_13 13 15 ixDPCSSYS_CR1_RAWAONLANE1_DIG_RX_OVRD_OUT_2 2 0x4134 9 0 4294967295 RX_PMA_VREFGEN_EN_OVRD_VAL 0 0 RX_PMA_VREFGEN_EN_OVRD_EN 1 1 RX_SQ_OUT_OVRD_VAL 2 2 RX_SQ_OUT_OVRD_EN 3 3 RX_PMA_TERM_ACDC_OVRD_VAL 4 4 RX_PMA_TERM_ACDC_OVRD_EN 5 5 RX_PMA_TERM_EN_OVRD_VAL 6 6 RX_PMA_TERM_EN_OVRD_EN 7 7 RESERVED_15_8 8 15 ixDPCSSYS_CR1_RAWAONLANE1_DIG_RX_OVRD_OUT_3 2 0x4135 7 0 4294967295 RX_PMA_SIGDET_LF_FILTER_EN_OVRD_VAL 0 0 RX_PMA_SIGDET_LF_FILTER_EN_OVRD_EN 1 1 RX_PMA_SIGDET_LF_EN_OVRD_VAL 2 2 RX_PMA_SIGDET_LF_EN_OVRD_EN 3 3 RX_PMA_SIGDET_HF_EN_OVRD_VAL 4 4 RX_PMA_SIGDET_HF_EN_OVRD_EN 5 5 RESERVED_15_6 6 15 ixDPCSSYS_CR1_RAWAONLANE1_DIG_RX_SIGDET_CAL 2 0x4136 4 0 4294967295 RX_PMA_SIGDET_LF_THRESHOLD 0 2 RX_PMA_SIGDET_HF_THRESHOLD 3 5 RX_PMA_SIGDET_CAL_EN 6 6 RESERVED_15_7 7 15 ixDPCSSYS_CR1_RAWAONLANE1_DIG_RX_SIGDET_HF_CODE 2 0x4137 2 0 4294967295 RX_PMA_SIGDET_HF_CAL_TUNE 0 5 RESERVED_15_6 6 15 ixDPCSSYS_CR1_RAWAONLANE1_DIG_RX_SIGDET_LF_CODE 2 0x4138 2 0 4294967295 RX_PMA_SIGDET_LF_CAL_TUNE 0 5 RESERVED_15_6 6 15 ixDPCSSYS_CR1_RAWAONLANE1_DIG_RX_VREFGEN_EN 2 0x4139 2 0 4294967295 PULL_UP 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR1_RAWAONLANE1_DIG_CAL_IOFF_CODE 2 0x413a 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR1_RAWAONLANE1_DIG_CAL_ICONST_CODE 2 0x413b 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR1_RAWAONLANE1_DIG_CAL_VREFGEN_CODE 2 0x413c 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR1_RAWAONLANE1_DIG_RX_DCC_CAL_ICM_CODE_0 2 0x413d 2 0 4294967295 RX_DCC_CAL_ICM_CODE 0 9 RESERVED_15_10 10 15 ixDPCSSYS_CR1_RAWAONLANE1_DIG_RX_DCC_CAL_IDF_CODE_0 2 0x413e 2 0 4294967295 RX_DCC_CAL_IDF_CODE 0 9 RESERVED_15_10 10 15 ixDPCSSYS_CR1_RAWAONLANE1_DIG_RX_DCC_CAL_QCM_CODE_0 2 0x413f 2 0 4294967295 RX_DCC_CAL_QCM_CODE 0 9 RESERVED_15_10 10 15 ixDPCSSYS_CR1_RAWAONLANE1_DIG_RX_DCC_CAL_QDF_CODE_0 2 0x4140 2 0 4294967295 RX_DCC_CAL_QDF_CODE 0 9 RESERVED_15_10 10 15 ixDPCSSYS_CR1_RAWAONLANE1_DIG_RX_DCC_CAL_ICM_CODE_1 2 0x4141 2 0 4294967295 RX_DCC_CAL_ICM_CODE 0 9 RESERVED_15_10 10 15 ixDPCSSYS_CR1_RAWAONLANE1_DIG_RX_DCC_CAL_IDF_CODE_1 2 0x4142 2 0 4294967295 RX_DCC_CAL_IDF_CODE 0 9 RESERVED_15_10 10 15 ixDPCSSYS_CR1_RAWAONLANE1_DIG_RX_DCC_CAL_QCM_CODE_1 2 0x4143 2 0 4294967295 RX_DCC_CAL_QCM_CODE 0 9 RESERVED_15_10 10 15 ixDPCSSYS_CR1_RAWAONLANE1_DIG_RX_DCC_CAL_QDF_CODE_1 2 0x4144 2 0 4294967295 RX_DCC_CAL_QDF_CODE 0 9 RESERVED_15_10 10 15 ixDPCSSYS_CR1_RAWAONLANE1_DIG_TX_DCC_BANK_ADDR 2 0x4145 1 0 4294967295 ADDR 0 15 ixDPCSSYS_CR1_RAWAONLANE1_DIG_TX_DCC_BANK_DATA 2 0x4146 1 0 4294967295 DATA 0 15 ixDPCSSYS_CR1_RAWAONLANE1_DIG_TX_DCC_CONT 2 0x4147 2 0 4294967295 EN 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR1_RAWAONLANE1_DIG_MPLL_BG_CTL 2 0x4148 3 0 4294967295 MPLL_STATE_WAIT 0 0 MPLL_STATE_DLY_EN 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR1_RAWAONLANE1_DIG_SIGDET_OUT_OVRD 2 0x4149 5 0 4294967295 RX_SIGDET_HF_OUT_OVRD_VAL 0 0 RX_SIGDET_HF_OUT_OVRD_EN 1 1 RX_SIGDET_LF_OUT_OVRD_VAL 2 2 RX_SIGDET_LF_OUT_OVRD_EN 3 3 RESERVED_15_4 4 15 ixDPCSSYS_CR1_RAWAONLANE1_DIG_SIGDET_OUT_IN 2 0x414a 3 0 4294967295 RX_SIGDET_HF_OUT_OVRD_VAL 0 0 RX_SIGDET_LF_OUT_OVRD_VAL 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR1_RAWAONLANE1_DIG_FW_MM_CONFIG 2 0x414b 1 0 4294967295 DATA 0 0 ixDPCSSYS_CR1_RAWAONLANE1_DIG_FW_ADPT_CONFIG 2 0x414c 2 0 4294967295 REF_LVL_ADPT 0 7 FW_CONFIG 8 15 ixDPCSSYS_CR1_RAWAONLANE1_DIG_FW_CALIB_CONFIG 2 0x414d 1 0 4294967295 FW_CALIB 0 15 ixDPCSSYS_CR1_RAWAONLANE1_DIG_LANE_XCVR_MODE_OVRD_IN 2 0x414e 3 0 4294967295 LANE_XCVR_MODE_OVRD_VAL 0 1 LANE_XCVR_MODE_OVRD_EN 2 2 RESERVED_15_3 3 15 ixDPCSSYS_CR1_RAWAONLANE1_DIG_LANE_XCVR_MODE_IN 2 0x414f 2 0 4294967295 LANE_XCVR_MODE 0 1 RESERVED_15_2 2 15 ixDPCSSYS_CR1_RAWAONLANE1_DIG_RX_SIGDET_CONFIG 2 0x4150 4 0 4294967295 RX_SIGDET_HF_FILTER_COUNTER 0 4 RX_SIGDET_LF_FILTER_COUNTER 5 9 RX_SIGDET_LF_HOLD 10 10 RESERVED_15_11 11 15 ixDPCSSYS_CR1_RAWAONLANE1_DIG_TX_DCC_CONFIG 2 0x4151 1 0 4294967295 DATA 0 0 ixDPCSSYS_CR1_RAWAONLANE2_DIG_AFE_ATT_IDAC_OFST 2 0x4200 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR1_RAWAONLANE2_DIG_AFE_CTLE_IDAC_OFST 2 0x4201 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR1_RAWAONLANE2_DIG_RX_ADPT_IQ 2 0x4202 2 0 4294967295 IQ_ADPT_VAL 0 6 RESERVED_15_7 7 15 ixDPCSSYS_CR1_RAWAONLANE2_DIG_RX_ADAPT_FOM 2 0x4203 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR1_RAWAONLANE2_DIG_DFE_SUMMER_ODD_IDAC_OFST 2 0x4204 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR1_RAWAONLANE2_DIG_DFE_PHASE_EVEN_VDAC_OFST 2 0x4205 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR1_RAWAONLANE2_DIG_DFE_PHASE_ODD_VDAC_OFST 2 0x4206 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR1_RAWAONLANE2_DIG_DFE_EVEN_REF_LVL 2 0x4207 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR1_RAWAONLANE2_DIG_DFE_ODD_REF_LVL 2 0x4208 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR1_RAWAONLANE2_DIG_RX_PHSADJ_LIN 2 0x4209 2 0 4294967295 DATA 0 0 RESERVED_15_5 5 15 ixDPCSSYS_CR1_RAWAONLANE2_DIG_RX_PHSADJ_MAP 2 0x420a 2 0 4294967295 DATA 0 0 RESERVED_15_5 5 15 ixDPCSSYS_CR1_RAWAONLANE2_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST 2 0x420b 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR1_RAWAONLANE2_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST 2 0x420c 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR1_RAWAONLANE2_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST 2 0x420d 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR1_RAWAONLANE2_DIG_DFE_DATA_ODD_LOW_VDAC_OFST 2 0x420e 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR1_RAWAONLANE2_DIG_DFE_BYPASS_EVEN_VDAC_OFST 2 0x420f 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR1_RAWAONLANE2_DIG_DFE_BYPASS_ODD_VDAC_OFST 2 0x4210 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR1_RAWAONLANE2_DIG_DFE_ERROR_EVEN_VDAC_OFST 2 0x4211 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR1_RAWAONLANE2_DIG_DFE_ERROR_ODD_VDAC_OFST 2 0x4212 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR1_RAWAONLANE2_DIG_RX_IQ_PHASE_ADJUST 2 0x4213 2 0 4294967295 DATA 0 0 RESERVED_15_7 7 15 ixDPCSSYS_CR1_RAWAONLANE2_DIG_MPLLA_COARSE_TUNE 2 0x4214 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR1_RAWAONLANE2_DIG_MPLLB_COARSE_TUNE 2 0x4215 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR1_RAWAONLANE2_DIG_INIT_PWRUP_DONE 2 0x4216 3 0 4294967295 DATA 0 0 PH2_PWRUP_DONE 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR1_RAWAONLANE2_DIG_RX_ADPT_ATT 2 0x4217 2 0 4294967295 ATT_ADPT_VAL 0 7 RESERVED_15_8 8 15 ixDPCSSYS_CR1_RAWAONLANE2_DIG_RX_ADPT_VGA 2 0x4218 2 0 4294967295 VGA_ADPT_VAL 0 9 RESERVED_15_10 10 15 ixDPCSSYS_CR1_RAWAONLANE2_DIG_RX_ADPT_CTLE 2 0x4219 3 0 4294967295 CTLE_BOOST_ADPT_VAL 0 9 CTLE_POLE_ADPT_VAL 10 12 RESERVED_15_13 13 15 ixDPCSSYS_CR1_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP1 2 0x421a 2 0 4294967295 DFE_TAP1_ADPT_VAL 0 12 RESERVED_15_13 13 15 ixDPCSSYS_CR1_RAWAONLANE2_DIG_RX_ADAPT_DONE 2 0x421b 2 0 4294967295 DATA 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR1_RAWAONLANE2_DIG_FAST_FLAGS 2 0x421c 16 0 4294967295 FAST_RX_STARTUP_CAL 0 0 FAST_RX_ADAPT 1 1 FAST_RX_AFE_CAL 2 2 FAST_RX_DFE_CAL 3 3 FAST_RX_BYPASS_CAL 4 4 FAST_RX_REFLVL_CAL 5 5 FAST_RX_IQ_CAL 6 6 FAST_RX_AFE_ADAPT 7 7 FAST_RX_DFE_ADAPT 8 8 FAST_SUP 9 9 FAST_TX_CMN_MODE 10 10 FAST_TX_RXDET 11 11 FAST_RX_PWRUP 12 12 FAST_RX_VCO_WAIT 13 13 FAST_RX_VCO_CAL 14 14 RESERVED_15_15 15 15 ixDPCSSYS_CR1_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP2 2 0x421d 2 0 4294967295 DFE_TAP2_ADPT_VAL 0 11 RESERVED_15_12 12 15 ixDPCSSYS_CR1_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP3 2 0x421e 2 0 4294967295 DFE_TAP3_ADPT_VAL 0 11 RESERVED_15_12 12 15 ixDPCSSYS_CR1_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP4 2 0x421f 2 0 4294967295 DFE_TAP4_ADPT_VAL 0 11 RESERVED_15_12 12 15 ixDPCSSYS_CR1_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP5 2 0x4220 2 0 4294967295 DFE_TAP5_ADPT_VAL 0 11 RESERVED_15_12 12 15 ixDPCSSYS_CR1_RAWAONLANE2_DIG_RX_SLICER_CTRL_EVEN 2 0x4221 2 0 4294967295 RX_ANA_SLICER_CTRL_E 0 3 RESERVED_15_4 4 15 ixDPCSSYS_CR1_RAWAONLANE2_DIG_RX_SLICER_CTRL_ODD 2 0x4222 2 0 4294967295 RX_ANA_SLICER_CTRL_O 0 3 RESERVED_15_4 4 15 ixDPCSSYS_CR1_RAWAONLANE2_DIG_LANE_CMNCAL_MPLL_STATUS 2 0x4223 3 0 4294967295 LANE_CMNCAL_MPLL_INIT 0 0 LANE_CMNCAL_MPLL_DONE 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR1_RAWAONLANE2_DIG_ADPT_CTL_0 2 0x4224 1 0 4294967295 VAL 0 15 ixDPCSSYS_CR1_RAWAONLANE2_DIG_ADPT_CTL_1 2 0x4225 1 0 4294967295 VAL 0 15 ixDPCSSYS_CR1_RAWAONLANE2_DIG_ADPT_CTL_2 2 0x4226 1 0 4294967295 VAL 0 15 ixDPCSSYS_CR1_RAWAONLANE2_DIG_ADPT_CTL_3 2 0x4227 1 0 4294967295 VAL 0 15 ixDPCSSYS_CR1_RAWAONLANE2_DIG_ADPT_CTL_4 2 0x4228 1 0 4294967295 VAL 0 15 ixDPCSSYS_CR1_RAWAONLANE2_DIG_ADPT_CTL_5 2 0x4229 1 0 4294967295 VAL 0 15 ixDPCSSYS_CR1_RAWAONLANE2_DIG_ADPT_CTL_6 2 0x422a 1 0 4294967295 VAL 0 15 ixDPCSSYS_CR1_RAWAONLANE2_DIG_ADPT_CTL_7 2 0x422b 1 0 4294967295 VAL 0 15 ixDPCSSYS_CR1_RAWAONLANE2_DIG_MPLL_DISABLE 2 0x422c 3 0 4294967295 LANE_MPLLA_DISABLE 0 0 LANE_MPLLB_DISABLE 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR1_RAWAONLANE2_DIG_FAST_FLAGS_2 2 0x422d 16 0 4294967295 FAST_RX_CONT_CAL_ADAPT 0 0 FAST_RX_CONT_ADAPT 1 1 FAST_RX_CONT_DATA_CAL 2 2 FAST_RX_CONT_PHASE_CAL 3 3 FAST_RX_CONT_AFE_CAL 4 4 FAST_TX_CONT_DCC_CAL 5 5 FAST_RX_CONT_DCC_CAL 6 6 FAST_RX_CONT_VPHUD_CAL 7 7 FAST_RX_CONT_VREF_CAL 8 8 FAST_TX_DCC_CAL 9 9 FAST_RX_DCC_CAL 10 10 FAST_RX_VPHUD_CAL 11 11 FAST_RX_VREF_CAL 12 12 SKIP_TX_RTUNE_CAL 13 13 FAST_RX_SIGDET_CAL 14 14 RESERVED_15_15 15 15 ixDPCSSYS_CR1_RAWAONLANE2_DIG_LANE_CMNCAL_RCAL_STATUS 2 0x422e 3 0 4294967295 LANE_CMNCAL_RCAL_INIT 0 0 LANE_CMNCAL_RCAL_DONE 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR1_RAWAONLANE2_DIG_TXRX_OVRD_IN 2 0x422f 5 0 4294967295 RX_DISABLE_OVRD_VAL 0 0 RX_DISABLE_OVRD_EN 1 1 TX_DISABLE_OVRD_VAL 2 2 TX_DISABLE_OVRD_EN 3 3 RESERVED_15_4 4 15 ixDPCSSYS_CR1_RAWAONLANE2_DIG_RX_LOS_MASK_CTL 2 0x4230 2 0 4294967295 RX_LOS_MASK_CNT 0 8 RESERVED_15_9 9 15 ixDPCSSYS_CR1_RAWAONLANE2_DIG_RX_SIGDET_FILT_CTRL 2 0x4231 5 0 4294967295 ISOLATE_SIGDET_HF 0 0 RX_SIGDEF_HF_FILT_OVR_DIS 1 1 RX_SIGDEF_HF_FILT_OVR 2 2 RX_SIGDET_LF_OUT_FILT_EN 3 3 RESERVED_15_4 4 15 ixDPCSSYS_CR1_RAWAONLANE2_DIG_STATS 2 0x4232 3 0 4294967295 RX_VREFGEN_MASTER 0 0 RX_PMA_SQ_OUT 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR1_RAWAONLANE2_DIG_RX_OVRD_OUT_1 2 0x4233 11 0 4294967295 RX_PMA_SQ_CTRL_TRESH_OVRD_VAL 0 2 RX_PMA_SQ_CTRL_TRESH_OVRD_EN 3 3 RX_PMA_SQ_CTRL_RESP_OVRD_VAL 4 5 RX_PMA_SQ_CTRL_RESP_OVRD_EN 6 6 RX_PMA_SQ_WEAKKEEP_OVRD_VAL 7 7 RX_PMA_SQ_WEAKKEEP_OVRD_EN 8 8 RX_PMA_SQ_INV_POLARITY_OVRD_VAL 9 9 RX_PMA_SQ_INV_POLARITY_OVRD_EN 10 10 RX_PMA_SQ_EN_OVRD_VAL 11 11 RX_PMA_SQ_EN_OVRD_EN 12 12 RESERVED_15_13 13 15 ixDPCSSYS_CR1_RAWAONLANE2_DIG_RX_OVRD_OUT_2 2 0x4234 9 0 4294967295 RX_PMA_VREFGEN_EN_OVRD_VAL 0 0 RX_PMA_VREFGEN_EN_OVRD_EN 1 1 RX_SQ_OUT_OVRD_VAL 2 2 RX_SQ_OUT_OVRD_EN 3 3 RX_PMA_TERM_ACDC_OVRD_VAL 4 4 RX_PMA_TERM_ACDC_OVRD_EN 5 5 RX_PMA_TERM_EN_OVRD_VAL 6 6 RX_PMA_TERM_EN_OVRD_EN 7 7 RESERVED_15_8 8 15 ixDPCSSYS_CR1_RAWAONLANE2_DIG_RX_OVRD_OUT_3 2 0x4235 7 0 4294967295 RX_PMA_SIGDET_LF_FILTER_EN_OVRD_VAL 0 0 RX_PMA_SIGDET_LF_FILTER_EN_OVRD_EN 1 1 RX_PMA_SIGDET_LF_EN_OVRD_VAL 2 2 RX_PMA_SIGDET_LF_EN_OVRD_EN 3 3 RX_PMA_SIGDET_HF_EN_OVRD_VAL 4 4 RX_PMA_SIGDET_HF_EN_OVRD_EN 5 5 RESERVED_15_6 6 15 ixDPCSSYS_CR1_RAWAONLANE2_DIG_RX_SIGDET_CAL 2 0x4236 4 0 4294967295 RX_PMA_SIGDET_LF_THRESHOLD 0 2 RX_PMA_SIGDET_HF_THRESHOLD 3 5 RX_PMA_SIGDET_CAL_EN 6 6 RESERVED_15_7 7 15 ixDPCSSYS_CR1_RAWAONLANE2_DIG_RX_SIGDET_HF_CODE 2 0x4237 2 0 4294967295 RX_PMA_SIGDET_HF_CAL_TUNE 0 5 RESERVED_15_6 6 15 ixDPCSSYS_CR1_RAWAONLANE2_DIG_RX_SIGDET_LF_CODE 2 0x4238 2 0 4294967295 RX_PMA_SIGDET_LF_CAL_TUNE 0 5 RESERVED_15_6 6 15 ixDPCSSYS_CR1_RAWAONLANE2_DIG_RX_VREFGEN_EN 2 0x4239 2 0 4294967295 PULL_UP 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR1_RAWAONLANE2_DIG_CAL_IOFF_CODE 2 0x423a 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR1_RAWAONLANE2_DIG_CAL_ICONST_CODE 2 0x423b 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR1_RAWAONLANE2_DIG_CAL_VREFGEN_CODE 2 0x423c 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR1_RAWAONLANE2_DIG_RX_DCC_CAL_ICM_CODE_0 2 0x423d 2 0 4294967295 RX_DCC_CAL_ICM_CODE 0 9 RESERVED_15_10 10 15 ixDPCSSYS_CR1_RAWAONLANE2_DIG_RX_DCC_CAL_IDF_CODE_0 2 0x423e 2 0 4294967295 RX_DCC_CAL_IDF_CODE 0 9 RESERVED_15_10 10 15 ixDPCSSYS_CR1_RAWAONLANE2_DIG_RX_DCC_CAL_QCM_CODE_0 2 0x423f 2 0 4294967295 RX_DCC_CAL_QCM_CODE 0 9 RESERVED_15_10 10 15 ixDPCSSYS_CR1_RAWAONLANE2_DIG_RX_DCC_CAL_QDF_CODE_0 2 0x4240 2 0 4294967295 RX_DCC_CAL_QDF_CODE 0 9 RESERVED_15_10 10 15 ixDPCSSYS_CR1_RAWAONLANE2_DIG_RX_DCC_CAL_ICM_CODE_1 2 0x4241 2 0 4294967295 RX_DCC_CAL_ICM_CODE 0 9 RESERVED_15_10 10 15 ixDPCSSYS_CR1_RAWAONLANE2_DIG_RX_DCC_CAL_IDF_CODE_1 2 0x4242 2 0 4294967295 RX_DCC_CAL_IDF_CODE 0 9 RESERVED_15_10 10 15 ixDPCSSYS_CR1_RAWAONLANE2_DIG_RX_DCC_CAL_QCM_CODE_1 2 0x4243 2 0 4294967295 RX_DCC_CAL_QCM_CODE 0 9 RESERVED_15_10 10 15 ixDPCSSYS_CR1_RAWAONLANE2_DIG_RX_DCC_CAL_QDF_CODE_1 2 0x4244 2 0 4294967295 RX_DCC_CAL_QDF_CODE 0 9 RESERVED_15_10 10 15 ixDPCSSYS_CR1_RAWAONLANE2_DIG_TX_DCC_BANK_ADDR 2 0x4245 1 0 4294967295 ADDR 0 15 ixDPCSSYS_CR1_RAWAONLANE2_DIG_TX_DCC_BANK_DATA 2 0x4246 1 0 4294967295 DATA 0 15 ixDPCSSYS_CR1_RAWAONLANE2_DIG_TX_DCC_CONT 2 0x4247 2 0 4294967295 EN 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR1_RAWAONLANE2_DIG_MPLL_BG_CTL 2 0x4248 3 0 4294967295 MPLL_STATE_WAIT 0 0 MPLL_STATE_DLY_EN 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR1_RAWAONLANE2_DIG_SIGDET_OUT_OVRD 2 0x4249 5 0 4294967295 RX_SIGDET_HF_OUT_OVRD_VAL 0 0 RX_SIGDET_HF_OUT_OVRD_EN 1 1 RX_SIGDET_LF_OUT_OVRD_VAL 2 2 RX_SIGDET_LF_OUT_OVRD_EN 3 3 RESERVED_15_4 4 15 ixDPCSSYS_CR1_RAWAONLANE2_DIG_SIGDET_OUT_IN 2 0x424a 3 0 4294967295 RX_SIGDET_HF_OUT_OVRD_VAL 0 0 RX_SIGDET_LF_OUT_OVRD_VAL 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR1_RAWAONLANE2_DIG_FW_MM_CONFIG 2 0x424b 1 0 4294967295 DATA 0 0 ixDPCSSYS_CR1_RAWAONLANE2_DIG_FW_ADPT_CONFIG 2 0x424c 2 0 4294967295 REF_LVL_ADPT 0 7 FW_CONFIG 8 15 ixDPCSSYS_CR1_RAWAONLANE2_DIG_FW_CALIB_CONFIG 2 0x424d 1 0 4294967295 FW_CALIB 0 15 ixDPCSSYS_CR1_RAWAONLANE2_DIG_LANE_XCVR_MODE_OVRD_IN 2 0x424e 3 0 4294967295 LANE_XCVR_MODE_OVRD_VAL 0 1 LANE_XCVR_MODE_OVRD_EN 2 2 RESERVED_15_3 3 15 ixDPCSSYS_CR1_RAWAONLANE2_DIG_LANE_XCVR_MODE_IN 2 0x424f 2 0 4294967295 LANE_XCVR_MODE 0 1 RESERVED_15_2 2 15 ixDPCSSYS_CR1_RAWAONLANE2_DIG_RX_SIGDET_CONFIG 2 0x4250 4 0 4294967295 RX_SIGDET_HF_FILTER_COUNTER 0 4 RX_SIGDET_LF_FILTER_COUNTER 5 9 RX_SIGDET_LF_HOLD 10 10 RESERVED_15_11 11 15 ixDPCSSYS_CR1_RAWAONLANE2_DIG_TX_DCC_CONFIG 2 0x4251 1 0 4294967295 DATA 0 0 ixDPCSSYS_CR1_RAWAONLANE3_DIG_AFE_ATT_IDAC_OFST 2 0x4300 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR1_RAWAONLANE3_DIG_AFE_CTLE_IDAC_OFST 2 0x4301 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR1_RAWAONLANE3_DIG_RX_ADPT_IQ 2 0x4302 2 0 4294967295 IQ_ADPT_VAL 0 6 RESERVED_15_7 7 15 ixDPCSSYS_CR1_RAWAONLANE3_DIG_RX_ADAPT_FOM 2 0x4303 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR1_RAWAONLANE3_DIG_DFE_SUMMER_ODD_IDAC_OFST 2 0x4304 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR1_RAWAONLANE3_DIG_DFE_PHASE_EVEN_VDAC_OFST 2 0x4305 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR1_RAWAONLANE3_DIG_DFE_PHASE_ODD_VDAC_OFST 2 0x4306 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR1_RAWAONLANE3_DIG_DFE_EVEN_REF_LVL 2 0x4307 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR1_RAWAONLANE3_DIG_DFE_ODD_REF_LVL 2 0x4308 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR1_RAWAONLANE3_DIG_RX_PHSADJ_LIN 2 0x4309 2 0 4294967295 DATA 0 0 RESERVED_15_5 5 15 ixDPCSSYS_CR1_RAWAONLANE3_DIG_RX_PHSADJ_MAP 2 0x430a 2 0 4294967295 DATA 0 0 RESERVED_15_5 5 15 ixDPCSSYS_CR1_RAWAONLANE3_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST 2 0x430b 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR1_RAWAONLANE3_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST 2 0x430c 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR1_RAWAONLANE3_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST 2 0x430d 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR1_RAWAONLANE3_DIG_DFE_DATA_ODD_LOW_VDAC_OFST 2 0x430e 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR1_RAWAONLANE3_DIG_DFE_BYPASS_EVEN_VDAC_OFST 2 0x430f 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR1_RAWAONLANE3_DIG_DFE_BYPASS_ODD_VDAC_OFST 2 0x4310 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR1_RAWAONLANE3_DIG_DFE_ERROR_EVEN_VDAC_OFST 2 0x4311 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR1_RAWAONLANE3_DIG_DFE_ERROR_ODD_VDAC_OFST 2 0x4312 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR1_RAWAONLANE3_DIG_RX_IQ_PHASE_ADJUST 2 0x4313 2 0 4294967295 DATA 0 0 RESERVED_15_7 7 15 ixDPCSSYS_CR1_RAWAONLANE3_DIG_MPLLA_COARSE_TUNE 2 0x4314 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR1_RAWAONLANE3_DIG_MPLLB_COARSE_TUNE 2 0x4315 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR1_RAWAONLANE3_DIG_INIT_PWRUP_DONE 2 0x4316 3 0 4294967295 DATA 0 0 PH2_PWRUP_DONE 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR1_RAWAONLANE3_DIG_RX_ADPT_ATT 2 0x4317 2 0 4294967295 ATT_ADPT_VAL 0 7 RESERVED_15_8 8 15 ixDPCSSYS_CR1_RAWAONLANE3_DIG_RX_ADPT_VGA 2 0x4318 2 0 4294967295 VGA_ADPT_VAL 0 9 RESERVED_15_10 10 15 ixDPCSSYS_CR1_RAWAONLANE3_DIG_RX_ADPT_CTLE 2 0x4319 3 0 4294967295 CTLE_BOOST_ADPT_VAL 0 9 CTLE_POLE_ADPT_VAL 10 12 RESERVED_15_13 13 15 ixDPCSSYS_CR1_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP1 2 0x431a 2 0 4294967295 DFE_TAP1_ADPT_VAL 0 12 RESERVED_15_13 13 15 ixDPCSSYS_CR1_RAWAONLANE3_DIG_RX_ADAPT_DONE 2 0x431b 2 0 4294967295 DATA 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR1_RAWAONLANE3_DIG_FAST_FLAGS 2 0x431c 16 0 4294967295 FAST_RX_STARTUP_CAL 0 0 FAST_RX_ADAPT 1 1 FAST_RX_AFE_CAL 2 2 FAST_RX_DFE_CAL 3 3 FAST_RX_BYPASS_CAL 4 4 FAST_RX_REFLVL_CAL 5 5 FAST_RX_IQ_CAL 6 6 FAST_RX_AFE_ADAPT 7 7 FAST_RX_DFE_ADAPT 8 8 FAST_SUP 9 9 FAST_TX_CMN_MODE 10 10 FAST_TX_RXDET 11 11 FAST_RX_PWRUP 12 12 FAST_RX_VCO_WAIT 13 13 FAST_RX_VCO_CAL 14 14 RESERVED_15_15 15 15 ixDPCSSYS_CR1_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP2 2 0x431d 2 0 4294967295 DFE_TAP2_ADPT_VAL 0 11 RESERVED_15_12 12 15 ixDPCSSYS_CR1_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP3 2 0x431e 2 0 4294967295 DFE_TAP3_ADPT_VAL 0 11 RESERVED_15_12 12 15 ixDPCSSYS_CR1_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP4 2 0x431f 2 0 4294967295 DFE_TAP4_ADPT_VAL 0 11 RESERVED_15_12 12 15 ixDPCSSYS_CR1_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP5 2 0x4320 2 0 4294967295 DFE_TAP5_ADPT_VAL 0 11 RESERVED_15_12 12 15 ixDPCSSYS_CR1_RAWAONLANE3_DIG_RX_SLICER_CTRL_EVEN 2 0x4321 2 0 4294967295 RX_ANA_SLICER_CTRL_E 0 3 RESERVED_15_4 4 15 ixDPCSSYS_CR1_RAWAONLANE3_DIG_RX_SLICER_CTRL_ODD 2 0x4322 2 0 4294967295 RX_ANA_SLICER_CTRL_O 0 3 RESERVED_15_4 4 15 ixDPCSSYS_CR1_RAWAONLANE3_DIG_LANE_CMNCAL_MPLL_STATUS 2 0x4323 3 0 4294967295 LANE_CMNCAL_MPLL_INIT 0 0 LANE_CMNCAL_MPLL_DONE 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR1_RAWAONLANE3_DIG_ADPT_CTL_0 2 0x4324 1 0 4294967295 VAL 0 15 ixDPCSSYS_CR1_RAWAONLANE3_DIG_ADPT_CTL_1 2 0x4325 1 0 4294967295 VAL 0 15 ixDPCSSYS_CR1_RAWAONLANE3_DIG_ADPT_CTL_2 2 0x4326 1 0 4294967295 VAL 0 15 ixDPCSSYS_CR1_RAWAONLANE3_DIG_ADPT_CTL_3 2 0x4327 1 0 4294967295 VAL 0 15 ixDPCSSYS_CR1_RAWAONLANE3_DIG_ADPT_CTL_4 2 0x4328 1 0 4294967295 VAL 0 15 ixDPCSSYS_CR1_RAWAONLANE3_DIG_ADPT_CTL_5 2 0x4329 1 0 4294967295 VAL 0 15 ixDPCSSYS_CR1_RAWAONLANE3_DIG_ADPT_CTL_6 2 0x432a 1 0 4294967295 VAL 0 15 ixDPCSSYS_CR1_RAWAONLANE3_DIG_ADPT_CTL_7 2 0x432b 1 0 4294967295 VAL 0 15 ixDPCSSYS_CR1_RAWAONLANE3_DIG_MPLL_DISABLE 2 0x432c 3 0 4294967295 LANE_MPLLA_DISABLE 0 0 LANE_MPLLB_DISABLE 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR1_RAWAONLANE3_DIG_FAST_FLAGS_2 2 0x432d 16 0 4294967295 FAST_RX_CONT_CAL_ADAPT 0 0 FAST_RX_CONT_ADAPT 1 1 FAST_RX_CONT_DATA_CAL 2 2 FAST_RX_CONT_PHASE_CAL 3 3 FAST_RX_CONT_AFE_CAL 4 4 FAST_TX_CONT_DCC_CAL 5 5 FAST_RX_CONT_DCC_CAL 6 6 FAST_RX_CONT_VPHUD_CAL 7 7 FAST_RX_CONT_VREF_CAL 8 8 FAST_TX_DCC_CAL 9 9 FAST_RX_DCC_CAL 10 10 FAST_RX_VPHUD_CAL 11 11 FAST_RX_VREF_CAL 12 12 SKIP_TX_RTUNE_CAL 13 13 FAST_RX_SIGDET_CAL 14 14 RESERVED_15_15 15 15 ixDPCSSYS_CR1_RAWAONLANE3_DIG_LANE_CMNCAL_RCAL_STATUS 2 0x432e 3 0 4294967295 LANE_CMNCAL_RCAL_INIT 0 0 LANE_CMNCAL_RCAL_DONE 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR1_RAWAONLANE3_DIG_TXRX_OVRD_IN 2 0x432f 5 0 4294967295 RX_DISABLE_OVRD_VAL 0 0 RX_DISABLE_OVRD_EN 1 1 TX_DISABLE_OVRD_VAL 2 2 TX_DISABLE_OVRD_EN 3 3 RESERVED_15_4 4 15 ixDPCSSYS_CR1_RAWAONLANE3_DIG_RX_LOS_MASK_CTL 2 0x4330 2 0 4294967295 RX_LOS_MASK_CNT 0 8 RESERVED_15_9 9 15 ixDPCSSYS_CR1_RAWAONLANE3_DIG_RX_SIGDET_FILT_CTRL 2 0x4331 5 0 4294967295 ISOLATE_SIGDET_HF 0 0 RX_SIGDEF_HF_FILT_OVR_DIS 1 1 RX_SIGDEF_HF_FILT_OVR 2 2 RX_SIGDET_LF_OUT_FILT_EN 3 3 RESERVED_15_4 4 15 ixDPCSSYS_CR1_RAWAONLANE3_DIG_STATS 2 0x4332 3 0 4294967295 RX_VREFGEN_MASTER 0 0 RX_PMA_SQ_OUT 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR1_RAWAONLANE3_DIG_RX_OVRD_OUT_1 2 0x4333 11 0 4294967295 RX_PMA_SQ_CTRL_TRESH_OVRD_VAL 0 2 RX_PMA_SQ_CTRL_TRESH_OVRD_EN 3 3 RX_PMA_SQ_CTRL_RESP_OVRD_VAL 4 5 RX_PMA_SQ_CTRL_RESP_OVRD_EN 6 6 RX_PMA_SQ_WEAKKEEP_OVRD_VAL 7 7 RX_PMA_SQ_WEAKKEEP_OVRD_EN 8 8 RX_PMA_SQ_INV_POLARITY_OVRD_VAL 9 9 RX_PMA_SQ_INV_POLARITY_OVRD_EN 10 10 RX_PMA_SQ_EN_OVRD_VAL 11 11 RX_PMA_SQ_EN_OVRD_EN 12 12 RESERVED_15_13 13 15 ixDPCSSYS_CR1_RAWAONLANE3_DIG_RX_OVRD_OUT_2 2 0x4334 9 0 4294967295 RX_PMA_VREFGEN_EN_OVRD_VAL 0 0 RX_PMA_VREFGEN_EN_OVRD_EN 1 1 RX_SQ_OUT_OVRD_VAL 2 2 RX_SQ_OUT_OVRD_EN 3 3 RX_PMA_TERM_ACDC_OVRD_VAL 4 4 RX_PMA_TERM_ACDC_OVRD_EN 5 5 RX_PMA_TERM_EN_OVRD_VAL 6 6 RX_PMA_TERM_EN_OVRD_EN 7 7 RESERVED_15_8 8 15 ixDPCSSYS_CR1_RAWAONLANE3_DIG_RX_OVRD_OUT_3 2 0x4335 7 0 4294967295 RX_PMA_SIGDET_LF_FILTER_EN_OVRD_VAL 0 0 RX_PMA_SIGDET_LF_FILTER_EN_OVRD_EN 1 1 RX_PMA_SIGDET_LF_EN_OVRD_VAL 2 2 RX_PMA_SIGDET_LF_EN_OVRD_EN 3 3 RX_PMA_SIGDET_HF_EN_OVRD_VAL 4 4 RX_PMA_SIGDET_HF_EN_OVRD_EN 5 5 RESERVED_15_6 6 15 ixDPCSSYS_CR1_RAWAONLANE3_DIG_RX_SIGDET_CAL 2 0x4336 4 0 4294967295 RX_PMA_SIGDET_LF_THRESHOLD 0 2 RX_PMA_SIGDET_HF_THRESHOLD 3 5 RX_PMA_SIGDET_CAL_EN 6 6 RESERVED_15_7 7 15 ixDPCSSYS_CR1_RAWAONLANE3_DIG_RX_SIGDET_HF_CODE 2 0x4337 2 0 4294967295 RX_PMA_SIGDET_HF_CAL_TUNE 0 5 RESERVED_15_6 6 15 ixDPCSSYS_CR1_RAWAONLANE3_DIG_RX_SIGDET_LF_CODE 2 0x4338 2 0 4294967295 RX_PMA_SIGDET_LF_CAL_TUNE 0 5 RESERVED_15_6 6 15 ixDPCSSYS_CR1_RAWAONLANE3_DIG_RX_VREFGEN_EN 2 0x4339 2 0 4294967295 PULL_UP 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR1_RAWAONLANE3_DIG_CAL_IOFF_CODE 2 0x433a 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR1_RAWAONLANE3_DIG_CAL_ICONST_CODE 2 0x433b 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR1_RAWAONLANE3_DIG_CAL_VREFGEN_CODE 2 0x433c 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR1_RAWAONLANE3_DIG_RX_DCC_CAL_ICM_CODE_0 2 0x433d 2 0 4294967295 RX_DCC_CAL_ICM_CODE 0 9 RESERVED_15_10 10 15 ixDPCSSYS_CR1_RAWAONLANE3_DIG_RX_DCC_CAL_IDF_CODE_0 2 0x433e 2 0 4294967295 RX_DCC_CAL_IDF_CODE 0 9 RESERVED_15_10 10 15 ixDPCSSYS_CR1_RAWAONLANE3_DIG_RX_DCC_CAL_QCM_CODE_0 2 0x433f 2 0 4294967295 RX_DCC_CAL_QCM_CODE 0 9 RESERVED_15_10 10 15 ixDPCSSYS_CR1_RAWAONLANE3_DIG_RX_DCC_CAL_QDF_CODE_0 2 0x4340 2 0 4294967295 RX_DCC_CAL_QDF_CODE 0 9 RESERVED_15_10 10 15 ixDPCSSYS_CR1_RAWAONLANE3_DIG_RX_DCC_CAL_ICM_CODE_1 2 0x4341 2 0 4294967295 RX_DCC_CAL_ICM_CODE 0 9 RESERVED_15_10 10 15 ixDPCSSYS_CR1_RAWAONLANE3_DIG_RX_DCC_CAL_IDF_CODE_1 2 0x4342 2 0 4294967295 RX_DCC_CAL_IDF_CODE 0 9 RESERVED_15_10 10 15 ixDPCSSYS_CR1_RAWAONLANE3_DIG_RX_DCC_CAL_QCM_CODE_1 2 0x4343 2 0 4294967295 RX_DCC_CAL_QCM_CODE 0 9 RESERVED_15_10 10 15 ixDPCSSYS_CR1_RAWAONLANE3_DIG_RX_DCC_CAL_QDF_CODE_1 2 0x4344 2 0 4294967295 RX_DCC_CAL_QDF_CODE 0 9 RESERVED_15_10 10 15 ixDPCSSYS_CR1_RAWAONLANE3_DIG_TX_DCC_BANK_ADDR 2 0x4345 1 0 4294967295 ADDR 0 15 ixDPCSSYS_CR1_RAWAONLANE3_DIG_TX_DCC_BANK_DATA 2 0x4346 1 0 4294967295 DATA 0 15 ixDPCSSYS_CR1_RAWAONLANE3_DIG_TX_DCC_CONT 2 0x4347 2 0 4294967295 EN 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR1_RAWAONLANE3_DIG_MPLL_BG_CTL 2 0x4348 3 0 4294967295 MPLL_STATE_WAIT 0 0 MPLL_STATE_DLY_EN 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR1_RAWAONLANE3_DIG_SIGDET_OUT_OVRD 2 0x4349 5 0 4294967295 RX_SIGDET_HF_OUT_OVRD_VAL 0 0 RX_SIGDET_HF_OUT_OVRD_EN 1 1 RX_SIGDET_LF_OUT_OVRD_VAL 2 2 RX_SIGDET_LF_OUT_OVRD_EN 3 3 RESERVED_15_4 4 15 ixDPCSSYS_CR1_RAWAONLANE3_DIG_SIGDET_OUT_IN 2 0x434a 3 0 4294967295 RX_SIGDET_HF_OUT_OVRD_VAL 0 0 RX_SIGDET_LF_OUT_OVRD_VAL 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR1_RAWAONLANE3_DIG_FW_MM_CONFIG 2 0x434b 1 0 4294967295 DATA 0 0 ixDPCSSYS_CR1_RAWAONLANE3_DIG_FW_ADPT_CONFIG 2 0x434c 2 0 4294967295 REF_LVL_ADPT 0 7 FW_CONFIG 8 15 ixDPCSSYS_CR1_RAWAONLANE3_DIG_FW_CALIB_CONFIG 2 0x434d 1 0 4294967295 FW_CALIB 0 15 ixDPCSSYS_CR1_RAWAONLANE3_DIG_LANE_XCVR_MODE_OVRD_IN 2 0x434e 3 0 4294967295 LANE_XCVR_MODE_OVRD_VAL 0 1 LANE_XCVR_MODE_OVRD_EN 2 2 RESERVED_15_3 3 15 ixDPCSSYS_CR1_RAWAONLANE3_DIG_LANE_XCVR_MODE_IN 2 0x434f 2 0 4294967295 LANE_XCVR_MODE 0 1 RESERVED_15_2 2 15 ixDPCSSYS_CR1_RAWAONLANE3_DIG_RX_SIGDET_CONFIG 2 0x4350 4 0 4294967295 RX_SIGDET_HF_FILTER_COUNTER 0 4 RX_SIGDET_LF_FILTER_COUNTER 5 9 RX_SIGDET_LF_HOLD 10 10 RESERVED_15_11 11 15 ixDPCSSYS_CR1_RAWAONLANE3_DIG_TX_DCC_CONFIG 2 0x4351 1 0 4294967295 DATA 0 0 ixDPCSSYS_CR1_RAWAONLANEX_DIG_AFE_ATT_IDAC_OFST 2 0x7000 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR1_RAWAONLANEX_DIG_AFE_CTLE_IDAC_OFST 2 0x7001 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR1_RAWAONLANEX_DIG_RX_ADPT_IQ 2 0x7002 2 0 4294967295 IQ_ADPT_VAL 0 6 RESERVED_15_7 7 15 ixDPCSSYS_CR1_RAWAONLANEX_DIG_RX_ADAPT_FOM 2 0x7003 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR1_RAWAONLANEX_DIG_DFE_SUMMER_ODD_IDAC_OFST 2 0x7004 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR1_RAWAONLANEX_DIG_DFE_PHASE_EVEN_VDAC_OFST 2 0x7005 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR1_RAWAONLANEX_DIG_DFE_PHASE_ODD_VDAC_OFST 2 0x7006 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR1_RAWAONLANEX_DIG_DFE_EVEN_REF_LVL 2 0x7007 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR1_RAWAONLANEX_DIG_DFE_ODD_REF_LVL 2 0x7008 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR1_RAWAONLANEX_DIG_RX_PHSADJ_LIN 2 0x7009 2 0 4294967295 DATA 0 0 RESERVED_15_5 5 15 ixDPCSSYS_CR1_RAWAONLANEX_DIG_RX_PHSADJ_MAP 2 0x700a 2 0 4294967295 DATA 0 0 RESERVED_15_5 5 15 ixDPCSSYS_CR1_RAWAONLANEX_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST 2 0x700b 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR1_RAWAONLANEX_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST 2 0x700c 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR1_RAWAONLANEX_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST 2 0x700d 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR1_RAWAONLANEX_DIG_DFE_DATA_ODD_LOW_VDAC_OFST 2 0x700e 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR1_RAWAONLANEX_DIG_DFE_BYPASS_EVEN_VDAC_OFST 2 0x700f 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR1_RAWAONLANEX_DIG_DFE_BYPASS_ODD_VDAC_OFST 2 0x7010 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR1_RAWAONLANEX_DIG_DFE_ERROR_EVEN_VDAC_OFST 2 0x7011 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR1_RAWAONLANEX_DIG_DFE_ERROR_ODD_VDAC_OFST 2 0x7012 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR1_RAWAONLANEX_DIG_RX_IQ_PHASE_ADJUST 2 0x7013 2 0 4294967295 DATA 0 0 RESERVED_15_7 7 15 ixDPCSSYS_CR1_RAWAONLANEX_DIG_MPLLA_COARSE_TUNE 2 0x7014 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR1_RAWAONLANEX_DIG_MPLLB_COARSE_TUNE 2 0x7015 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR1_RAWAONLANEX_DIG_INIT_PWRUP_DONE 2 0x7016 3 0 4294967295 DATA 0 0 PH2_PWRUP_DONE 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR1_RAWAONLANEX_DIG_RX_ADPT_ATT 2 0x7017 2 0 4294967295 ATT_ADPT_VAL 0 7 RESERVED_15_8 8 15 ixDPCSSYS_CR1_RAWAONLANEX_DIG_RX_ADPT_VGA 2 0x7018 2 0 4294967295 VGA_ADPT_VAL 0 9 RESERVED_15_10 10 15 ixDPCSSYS_CR1_RAWAONLANEX_DIG_RX_ADPT_CTLE 2 0x7019 3 0 4294967295 CTLE_BOOST_ADPT_VAL 0 9 CTLE_POLE_ADPT_VAL 10 12 RESERVED_15_13 13 15 ixDPCSSYS_CR1_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP1 2 0x701a 2 0 4294967295 DFE_TAP1_ADPT_VAL 0 12 RESERVED_15_13 13 15 ixDPCSSYS_CR1_RAWAONLANEX_DIG_RX_ADAPT_DONE 2 0x701b 2 0 4294967295 DATA 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR1_RAWAONLANEX_DIG_FAST_FLAGS 2 0x701c 16 0 4294967295 FAST_RX_STARTUP_CAL 0 0 FAST_RX_ADAPT 1 1 FAST_RX_AFE_CAL 2 2 FAST_RX_DFE_CAL 3 3 FAST_RX_BYPASS_CAL 4 4 FAST_RX_REFLVL_CAL 5 5 FAST_RX_IQ_CAL 6 6 FAST_RX_AFE_ADAPT 7 7 FAST_RX_DFE_ADAPT 8 8 FAST_SUP 9 9 FAST_TX_CMN_MODE 10 10 FAST_TX_RXDET 11 11 FAST_RX_PWRUP 12 12 FAST_RX_VCO_WAIT 13 13 FAST_RX_VCO_CAL 14 14 RESERVED_15_15 15 15 ixDPCSSYS_CR1_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP2 2 0x701d 2 0 4294967295 DFE_TAP2_ADPT_VAL 0 11 RESERVED_15_12 12 15 ixDPCSSYS_CR1_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP3 2 0x701e 2 0 4294967295 DFE_TAP3_ADPT_VAL 0 11 RESERVED_15_12 12 15 ixDPCSSYS_CR1_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP4 2 0x701f 2 0 4294967295 DFE_TAP4_ADPT_VAL 0 11 RESERVED_15_12 12 15 ixDPCSSYS_CR1_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP5 2 0x7020 2 0 4294967295 DFE_TAP5_ADPT_VAL 0 11 RESERVED_15_12 12 15 ixDPCSSYS_CR1_RAWAONLANEX_DIG_RX_SLICER_CTRL_EVEN 2 0x7021 2 0 4294967295 RX_ANA_SLICER_CTRL_E 0 3 RESERVED_15_4 4 15 ixDPCSSYS_CR1_RAWAONLANEX_DIG_RX_SLICER_CTRL_ODD 2 0x7022 2 0 4294967295 RX_ANA_SLICER_CTRL_O 0 3 RESERVED_15_4 4 15 ixDPCSSYS_CR1_RAWAONLANEX_DIG_LANE_CMNCAL_MPLL_STATUS 2 0x7023 3 0 4294967295 LANE_CMNCAL_MPLL_INIT 0 0 LANE_CMNCAL_MPLL_DONE 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR1_RAWAONLANEX_DIG_ADPT_CTL_0 2 0x7024 1 0 4294967295 VAL 0 15 ixDPCSSYS_CR1_RAWAONLANEX_DIG_ADPT_CTL_1 2 0x7025 1 0 4294967295 VAL 0 15 ixDPCSSYS_CR1_RAWAONLANEX_DIG_ADPT_CTL_2 2 0x7026 1 0 4294967295 VAL 0 15 ixDPCSSYS_CR1_RAWAONLANEX_DIG_ADPT_CTL_3 2 0x7027 1 0 4294967295 VAL 0 15 ixDPCSSYS_CR1_RAWAONLANEX_DIG_ADPT_CTL_4 2 0x7028 1 0 4294967295 VAL 0 15 ixDPCSSYS_CR1_RAWAONLANEX_DIG_ADPT_CTL_5 2 0x7029 1 0 4294967295 VAL 0 15 ixDPCSSYS_CR1_RAWAONLANEX_DIG_ADPT_CTL_6 2 0x702a 1 0 4294967295 VAL 0 15 ixDPCSSYS_CR1_RAWAONLANEX_DIG_ADPT_CTL_7 2 0x702b 1 0 4294967295 VAL 0 15 ixDPCSSYS_CR1_RAWAONLANEX_DIG_MPLL_DISABLE 2 0x702c 3 0 4294967295 LANE_MPLLA_DISABLE 0 0 LANE_MPLLB_DISABLE 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR1_RAWAONLANEX_DIG_FAST_FLAGS_2 2 0x702d 16 0 4294967295 FAST_RX_CONT_CAL_ADAPT 0 0 FAST_RX_CONT_ADAPT 1 1 FAST_RX_CONT_DATA_CAL 2 2 FAST_RX_CONT_PHASE_CAL 3 3 FAST_RX_CONT_AFE_CAL 4 4 FAST_TX_CONT_DCC_CAL 5 5 FAST_RX_CONT_DCC_CAL 6 6 FAST_RX_CONT_VPHUD_CAL 7 7 FAST_RX_CONT_VREF_CAL 8 8 FAST_TX_DCC_CAL 9 9 FAST_RX_DCC_CAL 10 10 FAST_RX_VPHUD_CAL 11 11 FAST_RX_VREF_CAL 12 12 SKIP_TX_RTUNE_CAL 13 13 FAST_RX_SIGDET_CAL 14 14 RESERVED_15_15 15 15 ixDPCSSYS_CR1_RAWAONLANEX_DIG_LANE_CMNCAL_RCAL_STATUS 2 0x702e 3 0 4294967295 LANE_CMNCAL_RCAL_INIT 0 0 LANE_CMNCAL_RCAL_DONE 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR1_RAWAONLANEX_DIG_TXRX_OVRD_IN 2 0x702f 5 0 4294967295 RX_DISABLE_OVRD_VAL 0 0 RX_DISABLE_OVRD_EN 1 1 TX_DISABLE_OVRD_VAL 2 2 TX_DISABLE_OVRD_EN 3 3 RESERVED_15_4 4 15 ixDPCSSYS_CR1_RAWAONLANEX_DIG_RX_LOS_MASK_CTL 2 0x7030 2 0 4294967295 RX_LOS_MASK_CNT 0 8 RESERVED_15_9 9 15 ixDPCSSYS_CR1_RAWAONLANEX_DIG_RX_SIGDET_FILT_CTRL 2 0x7031 5 0 4294967295 ISOLATE_SIGDET_HF 0 0 RX_SIGDEF_HF_FILT_OVR_DIS 1 1 RX_SIGDEF_HF_FILT_OVR 2 2 RX_SIGDET_LF_OUT_FILT_EN 3 3 RESERVED_15_4 4 15 ixDPCSSYS_CR1_RAWAONLANEX_DIG_STATS 2 0x7032 3 0 4294967295 RX_VREFGEN_MASTER 0 0 RX_PMA_SQ_OUT 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR1_RAWAONLANEX_DIG_RX_OVRD_OUT_1 2 0x7033 11 0 4294967295 RX_PMA_SQ_CTRL_TRESH_OVRD_VAL 0 2 RX_PMA_SQ_CTRL_TRESH_OVRD_EN 3 3 RX_PMA_SQ_CTRL_RESP_OVRD_VAL 4 5 RX_PMA_SQ_CTRL_RESP_OVRD_EN 6 6 RX_PMA_SQ_WEAKKEEP_OVRD_VAL 7 7 RX_PMA_SQ_WEAKKEEP_OVRD_EN 8 8 RX_PMA_SQ_INV_POLARITY_OVRD_VAL 9 9 RX_PMA_SQ_INV_POLARITY_OVRD_EN 10 10 RX_PMA_SQ_EN_OVRD_VAL 11 11 RX_PMA_SQ_EN_OVRD_EN 12 12 RESERVED_15_13 13 15 ixDPCSSYS_CR1_RAWAONLANEX_DIG_RX_OVRD_OUT_2 2 0x7034 9 0 4294967295 RX_PMA_VREFGEN_EN_OVRD_VAL 0 0 RX_PMA_VREFGEN_EN_OVRD_EN 1 1 RX_SQ_OUT_OVRD_VAL 2 2 RX_SQ_OUT_OVRD_EN 3 3 RX_PMA_TERM_ACDC_OVRD_VAL 4 4 RX_PMA_TERM_ACDC_OVRD_EN 5 5 RX_PMA_TERM_EN_OVRD_VAL 6 6 RX_PMA_TERM_EN_OVRD_EN 7 7 RESERVED_15_8 8 15 ixDPCSSYS_CR1_RAWAONLANEX_DIG_RX_OVRD_OUT_3 2 0x7035 7 0 4294967295 RX_PMA_SIGDET_LF_FILTER_EN_OVRD_VAL 0 0 RX_PMA_SIGDET_LF_FILTER_EN_OVRD_EN 1 1 RX_PMA_SIGDET_LF_EN_OVRD_VAL 2 2 RX_PMA_SIGDET_LF_EN_OVRD_EN 3 3 RX_PMA_SIGDET_HF_EN_OVRD_VAL 4 4 RX_PMA_SIGDET_HF_EN_OVRD_EN 5 5 RESERVED_15_6 6 15 ixDPCSSYS_CR1_RAWAONLANEX_DIG_RX_SIGDET_CAL 2 0x7036 4 0 4294967295 RX_PMA_SIGDET_LF_THRESHOLD 0 2 RX_PMA_SIGDET_HF_THRESHOLD 3 5 RX_PMA_SIGDET_CAL_EN 6 6 RESERVED_15_7 7 15 ixDPCSSYS_CR1_RAWAONLANEX_DIG_RX_SIGDET_HF_CODE 2 0x7037 2 0 4294967295 RX_PMA_SIGDET_HF_CAL_TUNE 0 5 RESERVED_15_6 6 15 ixDPCSSYS_CR1_RAWAONLANEX_DIG_RX_SIGDET_LF_CODE 2 0x7038 2 0 4294967295 RX_PMA_SIGDET_LF_CAL_TUNE 0 5 RESERVED_15_6 6 15 ixDPCSSYS_CR1_RAWAONLANEX_DIG_RX_VREFGEN_EN 2 0x7039 2 0 4294967295 PULL_UP 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR1_RAWAONLANEX_DIG_CAL_IOFF_CODE 2 0x703a 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR1_RAWAONLANEX_DIG_CAL_ICONST_CODE 2 0x703b 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR1_RAWAONLANEX_DIG_CAL_VREFGEN_CODE 2 0x703c 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR1_RAWAONLANEX_DIG_RX_DCC_CAL_ICM_CODE_0 2 0x703d 2 0 4294967295 RX_DCC_CAL_ICM_CODE 0 9 RESERVED_15_10 10 15 ixDPCSSYS_CR1_RAWAONLANEX_DIG_RX_DCC_CAL_IDF_CODE_0 2 0x703e 2 0 4294967295 RX_DCC_CAL_IDF_CODE 0 9 RESERVED_15_10 10 15 ixDPCSSYS_CR1_RAWAONLANEX_DIG_RX_DCC_CAL_QCM_CODE_0 2 0x703f 2 0 4294967295 RX_DCC_CAL_QCM_CODE 0 9 RESERVED_15_10 10 15 ixDPCSSYS_CR1_RAWAONLANEX_DIG_RX_DCC_CAL_QDF_CODE_0 2 0x7040 2 0 4294967295 RX_DCC_CAL_QDF_CODE 0 9 RESERVED_15_10 10 15 ixDPCSSYS_CR1_RAWAONLANEX_DIG_RX_DCC_CAL_ICM_CODE_1 2 0x7041 2 0 4294967295 RX_DCC_CAL_ICM_CODE 0 9 RESERVED_15_10 10 15 ixDPCSSYS_CR1_RAWAONLANEX_DIG_RX_DCC_CAL_IDF_CODE_1 2 0x7042 2 0 4294967295 RX_DCC_CAL_IDF_CODE 0 9 RESERVED_15_10 10 15 ixDPCSSYS_CR1_RAWAONLANEX_DIG_RX_DCC_CAL_QCM_CODE_1 2 0x7043 2 0 4294967295 RX_DCC_CAL_QCM_CODE 0 9 RESERVED_15_10 10 15 ixDPCSSYS_CR1_RAWAONLANEX_DIG_RX_DCC_CAL_QDF_CODE_1 2 0x7044 2 0 4294967295 RX_DCC_CAL_QDF_CODE 0 9 RESERVED_15_10 10 15 ixDPCSSYS_CR1_RAWAONLANEX_DIG_TX_DCC_BANK_ADDR 2 0x7045 1 0 4294967295 ADDR 0 15 ixDPCSSYS_CR1_RAWAONLANEX_DIG_TX_DCC_BANK_DATA 2 0x7046 1 0 4294967295 DATA 0 15 ixDPCSSYS_CR1_RAWAONLANEX_DIG_TX_DCC_CONT 2 0x7047 2 0 4294967295 EN 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR1_RAWAONLANEX_DIG_MPLL_BG_CTL 2 0x7048 3 0 4294967295 MPLL_STATE_WAIT 0 0 MPLL_STATE_DLY_EN 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR1_RAWAONLANEX_DIG_SIGDET_OUT_OVRD 2 0x7049 5 0 4294967295 RX_SIGDET_HF_OUT_OVRD_VAL 0 0 RX_SIGDET_HF_OUT_OVRD_EN 1 1 RX_SIGDET_LF_OUT_OVRD_VAL 2 2 RX_SIGDET_LF_OUT_OVRD_EN 3 3 RESERVED_15_4 4 15 ixDPCSSYS_CR1_RAWAONLANEX_DIG_SIGDET_OUT_IN 2 0x704a 3 0 4294967295 RX_SIGDET_HF_OUT_OVRD_VAL 0 0 RX_SIGDET_LF_OUT_OVRD_VAL 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR1_RAWAONLANEX_DIG_FW_MM_CONFIG 2 0x704b 1 0 4294967295 DATA 0 0 ixDPCSSYS_CR1_RAWAONLANEX_DIG_FW_ADPT_CONFIG 2 0x704c 2 0 4294967295 REF_LVL_ADPT 0 7 FW_CONFIG 8 15 ixDPCSSYS_CR1_RAWAONLANEX_DIG_FW_CALIB_CONFIG 2 0x704d 1 0 4294967295 FW_CALIB 0 15 ixDPCSSYS_CR1_RAWAONLANEX_DIG_LANE_XCVR_MODE_OVRD_IN 2 0x704e 3 0 4294967295 LANE_XCVR_MODE_OVRD_VAL 0 1 LANE_XCVR_MODE_OVRD_EN 2 2 RESERVED_15_3 3 15 ixDPCSSYS_CR1_RAWAONLANEX_DIG_LANE_XCVR_MODE_IN 2 0x704f 2 0 4294967295 LANE_XCVR_MODE 0 1 RESERVED_15_2 2 15 ixDPCSSYS_CR1_RAWAONLANEX_DIG_RX_SIGDET_CONFIG 2 0x7050 4 0 4294967295 RX_SIGDET_HF_FILTER_COUNTER 0 4 RX_SIGDET_LF_FILTER_COUNTER 5 9 RX_SIGDET_LF_HOLD 10 10 RESERVED_15_11 11 15 ixDPCSSYS_CR1_RAWAONLANEX_DIG_TX_DCC_CONFIG 2 0x7051 1 0 4294967295 DATA 0 0 ixDPCSSYS_CR1_SUPX_DIG_IDCODE_LO 2 0x8000 1 0 4294967295 DATA 0 0 ixDPCSSYS_CR1_SUPX_DIG_IDCODE_HI 2 0x8001 1 0 4294967295 DATA 0 0 ixDPCSSYS_CR1_SUPX_DIG_REFCLK_OVRD_IN 2 0x8002 12 0 4294967295 REF_CLK_EN 0 0 REF_CLK_EN_OVRD_EN 1 1 REF_USE_PAD 2 2 REF_USE_PAD_OVRD_EN 3 3 REF_CLK_RANGE 4 8 REF_CLK_RANGE_OVRD_EN 9 9 BG_EN 10 10 BG_EN_OVRD_EN 11 11 HDMIMODE_EN 12 12 HDMIMODE_ENABLE_OVRD_EN 13 13 SUP_PRE_HP_OVRD 14 14 SUP_PRE_HP_OVRD_EN 15 15 ixDPCSSYS_CR1_SUPX_DIG_MPLLA_DIV_CLK_OVRD_IN 2 0x8003 4 0 4294967295 MPLLA_DIV_CLK_EN 0 0 MPLLA_DIV_MULTIPLIER 1 8 MPLLA_DIV_OVRD_EN 9 9 RESERVED_15_10 10 15 ixDPCSSYS_CR1_SUPX_DIG_MPLLA_HDMI_CLK_OVRD_IN 2 0x8004 4 0 4294967295 MPLLA_HDMI_PIXEL_CLK_DIV 0 1 MPLLA_HDMI_DIV 2 4 MPLLA_HDMI_OVRD_EN 5 5 RESERVED_15_6 6 15 ixDPCSSYS_CR1_SUPX_DIG_MPLLB_DIV_CLK_OVRD_IN 2 0x8005 4 0 4294967295 MPLLB_DIV_CLK_EN 0 0 MPLLB_DIV_MULTIPLIER 1 8 MPLLB_DIV_OVRD_EN 9 9 RESERVED_15_10 10 15 ixDPCSSYS_CR1_SUPX_DIG_MPLLB_HDMI_CLK_OVRD_IN 2 0x8006 4 0 4294967295 MPLLB_HDMI_PIXEL_CLK_DIV 0 1 MPLLB_HDMI_DIV 2 4 MPLLB_HDMI_OVRD_EN 5 5 RESERVED_15_6 6 15 ixDPCSSYS_CR1_SUPX_DIG_MPLLA_OVRD_IN_0 2 0x8007 12 0 4294967295 MPLLA_EN 0 0 MPLLA_DIV5_CLK_EN 1 1 MPLLA_TX_CLK_DIV 2 4 OVRD_EN 5 5 MPLLA_V2I 6 7 MPLLA_STANDBY 8 8 MPLLA_FREQ_VCO 9 10 MPLLA_CAL_FORCE 11 11 MPLL_FRACN_EN 12 12 MPLLA_CLK_SYNC_OVRD 13 13 MPLLA_CLK_SYNC_OVRD_EN 14 14 RESERVED_15_15 15 15 ixDPCSSYS_CR1_SUPX_DIG_MPLLA_OVRD_IN_1 2 0x8008 2 0 4294967295 MPLLA_MULTIPLIER 0 11 RESERVED_15_12 12 15 ixDPCSSYS_CR1_SUPX_DIG_MPLLA_OVRD_IN_2 2 0x8009 7 0 4294967295 MPLLA_SSC_EN 0 0 MPLLA_SSC_OVRD_EN 1 1 MPLLA_SSC_UP_SPREAD 2 2 MPLLA_PMIX_EN 3 3 MPLLA_WORD_DIV2_EN 4 4 MPLLA_FRACN_CFG_UPDATE_EN 5 5 RESERVED_15_6 6 15 ixDPCSSYS_CR1_SUPX_DIG_MPLLA_SSC_PEAK_1 2 0x800a 1 0 4294967295 MPLLA_SSC_PEAK_15_0 0 15 ixDPCSSYS_CR1_SUPX_DIG_MPLLA_SSC_PEAK_2 2 0x800b 2 0 4294967295 MPLLA_SSC_PEAK_19_16 0 3 RESERVED_15_4 4 15 ixDPCSSYS_CR1_SUPX_DIG_MPLLA_SSC_STEPSIZE_1 2 0x800c 1 0 4294967295 MPLLA_SSC_STEPSIZE_15_0 0 15 ixDPCSSYS_CR1_SUPX_DIG_MPLLA_SSC_STEPSIZE_2 2 0x800d 2 0 4294967295 MPLLA_SSC_STEPSIZE_20_16 0 4 RESERVED_15_5 5 15 ixDPCSSYS_CR1_SUPX_DIG_MPLLA_OVRD_IN_3 2 0x800e 1 0 4294967295 MPLLA_FRACN_QUOT 0 15 ixDPCSSYS_CR1_SUPX_DIG_MPLLA_OVRD_IN_4 2 0x800f 1 0 4294967295 MPLLA_FRACN_REM 0 15 ixDPCSSYS_CR1_SUPX_DIG_MPLLA_OVRD_IN_5 2 0x8010 1 0 4294967295 MPLLA_FRACN_DEN 0 15 ixDPCSSYS_CR1_SUPX_DIG_MPLLA_CP_OVRD_IN 2 0x8011 3 0 4294967295 MPLLA_CP_PROP 0 6 MPLLA_CP_INT 7 13 RESERVED_15_14 14 15 ixDPCSSYS_CR1_SUPX_DIG_MPLLA_CP_GS_OVRD_IN 2 0x8012 4 0 4294967295 MPLLA_CP_PROP_GS 0 6 MPLLA_CP_PROP_GS_OVR_EN 7 7 MPLLA_CP_INT_GS 8 14 MPLLA_CP_INT_GS_OVR_EN 15 15 ixDPCSSYS_CR1_SUPX_DIG_MPLLB_OVRD_IN_0 2 0x8013 12 0 4294967295 MPLLB_EN 0 0 MPLLB_DIV5_CLK_EN 1 1 MPLLB_TX_CLK_DIV 2 4 OVRD_EN 5 5 MPLLB_V2I 6 7 MPLLB_STANDBY 8 8 MPLLB_FREQ_VCO 9 10 MPLLB_CAL_FORCE 11 11 MPLL_FRACN_EN 12 12 MPLLB_CLK_SYNC_OVRD 13 13 MPLLB_CLK_SYNC_OVRD_EN 14 14 RESERVED_15_15 15 15 ixDPCSSYS_CR1_SUPX_DIG_MPLLB_OVRD_IN_1 2 0x8014 2 0 4294967295 MPLLB_MULTIPLIER 0 11 RESERVED_15_12 12 15 ixDPCSSYS_CR1_SUPX_DIG_MPLLB_OVRD_IN_2 2 0x8015 7 0 4294967295 MPLLB_SSC_EN 0 0 MPLLB_SSC_OVRD_EN 1 1 MPLLB_SSC_UP_SPREAD 2 2 MPLLB_PMIX_EN 3 3 MPLLB_WORD_DIV2_EN 4 4 MPLLB_FRACN_CFG_UPDATE_EN 5 5 RESERVED_15_6 6 15 ixDPCSSYS_CR1_SUPX_DIG_MPLLB_SSC_PEAK_1 2 0x8016 1 0 4294967295 MPLLB_SSC_PEAK_15_0 0 15 ixDPCSSYS_CR1_SUPX_DIG_MPLLB_SSC_PEAK_2 2 0x8017 2 0 4294967295 MPLLB_SSC_PEAK_19_16 0 3 RESERVED_15_4 4 15 ixDPCSSYS_CR1_SUPX_DIG_MPLLB_SSC_STEPSIZE_1 2 0x8018 1 0 4294967295 MPLLB_SSC_STEPSIZE_15_0 0 15 ixDPCSSYS_CR1_SUPX_DIG_MPLLB_SSC_STEPSIZE_2 2 0x8019 2 0 4294967295 MPLLB_SSC_STEPSIZE_20_16 0 4 RESERVED_15_5 5 15 ixDPCSSYS_CR1_SUPX_DIG_MPLLB_OVRD_IN_3 2 0x801a 1 0 4294967295 MPLLB_FRACN_QUOT 0 15 ixDPCSSYS_CR1_SUPX_DIG_MPLLB_OVRD_IN_4 2 0x801b 1 0 4294967295 MPLLB_FRACN_REM 0 15 ixDPCSSYS_CR1_SUPX_DIG_MPLLB_OVRD_IN_5 2 0x801c 1 0 4294967295 MPLLB_FRACN_DEN 0 15 ixDPCSSYS_CR1_SUPX_DIG_MPLLB_CP_OVRD_IN 2 0x801d 3 0 4294967295 MPLLB_CP_PROP 0 6 MPLLB_CP_INT 7 13 RESERVED_15_14 14 15 ixDPCSSYS_CR1_SUPX_DIG_MPLLB_CP_GS_OVRD_IN 2 0x801e 4 0 4294967295 MPLLB_CP_PROP_GS 0 6 MPLLB_CP_PROP_GS_OVR_EN 7 7 MPLLB_CP_INT_GS 8 14 MPLLB_CP_INT_GS_OVR_EN 15 15 ixDPCSSYS_CR1_SUPX_DIG_SUP_OVRD_IN 2 0x801f 8 0 4294967295 PRESCALER_OVRD_EN 0 0 RTUNE_REQ 1 1 RTUNE_OVRD_EN 2 2 TX_CAL_CODE 3 6 TX_CAL_CODE_EN 7 7 REF_ALT_CLK_LP_SEL_OVRD 8 8 REF_ALT_CLK_LP_SEL_OVRD_EN 9 9 RESERVED_15_10 10 15 ixDPCSSYS_CR1_SUPX_DIG_PRESCALER_OVRD_IN 2 0x8020 6 0 4294967295 DCO_RANGE 0 1 DCO_FINETUNE 2 7 REF_CLK_MPLLB_DIV 8 10 REF_CLK_MPLLA_DIV 11 13 REF_CLKDET_RESULT 14 14 REF_CLKDET_EN 15 15 ixDPCSSYS_CR1_SUPX_DIG_SUP_OVRD_OUT 2 0x8021 12 0 4294967295 RTUNE_ACK 0 0 RTUNE_ACK_OVRD_EN 1 1 MPLLA_STATE 2 2 MPLLA_STATE_OVRD_EN 3 3 MPLLB_STATE 4 4 MPLLB_STATE_OVRD_EN 5 5 BG_LANE_STATE 6 6 BG_LANE_STATE_OVRD_EN 7 7 BG_SUP_STATE 8 8 BG_SUP_STATE_OVRD_EN 9 9 REF_CLK_ACK 10 10 RESERVED_15_11 11 15 ixDPCSSYS_CR1_SUPX_DIG_LVL_OVRD_IN 2 0x8022 7 0 4294967295 RX_VREF_CTRL 0 2 RX_VREF_CTRL_EN 3 3 TX_VBOOST_LVL 4 6 TX_VBOOST_LVL_EN 7 7 SUP_RX_VCO_VREF_SEL_OVR 8 10 SUP_RX_VCO_VREF_SEL_OVR_EN 11 11 RESERVED_15_12 12 15 ixDPCSSYS_CR1_SUPX_DIG_MPLLA_ASIC_IN_0 2 0x8024 9 0 4294967295 MPLLA_EN 0 0 MPLLA_DIV5_CLK_EN 1 1 MPLLA_TX_CLK_DIV 2 4 MPLLA_V2I 5 6 MPLLA_STANDBY 7 7 MPLLA_FREQ_VCO 8 9 MPLLA_CAL_FORCE 10 10 MPLLA_FRACN_EN 11 11 RESERVED_15_12 12 15 ixDPCSSYS_CR1_SUPX_DIG_MPLLA_ASIC_IN_1 2 0x8025 2 0 4294967295 MPLLA_MULTIPLIER 0 11 RESERVED_15_12 12 15 ixDPCSSYS_CR1_SUPX_DIG_MPLLA_ASIC_IN_2 2 0x8026 7 0 4294967295 MPLLA_SSC_EN 0 0 MPLLA_SSC_UP_SPREAD 1 1 MPLLA_PMIX_EN 2 2 MPLLA_WORD_DIV2_EN 3 3 MPLLA_FRACN_CFG_UPDATE_EN 4 4 MPLLA_CLK_SYNC 5 5 RESERVED_15_6 6 15 ixDPCSSYS_CR1_SUPX_DIG_MPLLA_ASIC_IN_3 2 0x8027 1 0 4294967295 MPLLA_SSC_PEAK_15_0 0 15 ixDPCSSYS_CR1_SUPX_DIG_MPLLA_ASIC_IN_4 2 0x8028 2 0 4294967295 MPLLA_SSC_PEAK_19_16 0 3 RESERVED_15_4 4 15 ixDPCSSYS_CR1_SUPX_DIG_MPLLA_ASIC_IN_5 2 0x8029 1 0 4294967295 MPLLA_SSC_STEPSIZE_15_0 0 15 ixDPCSSYS_CR1_SUPX_DIG_MPLLA_ASIC_IN_6 2 0x802a 2 0 4294967295 MPLLA_SSC_STEPSIZE_20_16 0 3 RESERVED_15_4 4 15 ixDPCSSYS_CR1_SUPX_DIG_MPLLB_ASIC_IN_0 2 0x802b 9 0 4294967295 MPLLB_EN 0 0 MPLLB_DIV5_CLK_EN 1 1 MPLLB_TX_CLK_DIV 2 4 MPLLB_V2I 5 6 MPLLB_STANDBY 7 7 MPLLB_FREQ_VCO 8 9 MPLLB_CAL_FORCE 10 10 MPLLB_FRACN_EN 11 11 RESERVED_15_12 12 15 ixDPCSSYS_CR1_SUPX_DIG_MPLLB_ASIC_IN_1 2 0x802c 2 0 4294967295 MPLLB_MULTIPLIER 0 11 RESERVED_15_12 12 15 ixDPCSSYS_CR1_SUPX_DIG_MPLLB_ASIC_IN_2 2 0x802d 7 0 4294967295 MPLLB_SSC_EN 0 0 MPLLB_SSC_UP_SPREAD 1 1 MPLLB_PMIX_EN 2 2 MPLLB_WORD_DIV2_EN 3 3 MPLLB_FRACN_CFG_UPDATE_EN 4 4 MPLLB_CLK_SYNC 5 5 RESERVED_15_6 6 15 ixDPCSSYS_CR1_SUPX_DIG_MPLLB_ASIC_IN_3 2 0x802e 1 0 4294967295 MPLLB_SSC_PEAK_15_0 0 15 ixDPCSSYS_CR1_SUPX_DIG_MPLLB_ASIC_IN_4 2 0x802f 2 0 4294967295 MPLLB_SSC_PEAK_19_16 0 3 RESERVED_15_4 4 15 ixDPCSSYS_CR1_SUPX_DIG_MPLLB_ASIC_IN_5 2 0x8030 1 0 4294967295 MPLLB_SSC_STEPSIZE_15_0 0 15 ixDPCSSYS_CR1_SUPX_DIG_MPLLB_ASIC_IN_6 2 0x8031 2 0 4294967295 MPLLB_SSC_STEPSIZE_20_16 0 3 RESERVED_15_4 4 15 ixDPCSSYS_CR1_SUPX_DIG_MPLLA_DIV_CLK_ASIC_IN 2 0x8032 3 0 4294967295 MPLLA_DIV_CLK_EN 0 0 MPLLA_DIV_MULTIPLIER 1 8 RESERVED_15_9 9 15 ixDPCSSYS_CR1_SUPX_DIG_MPLLA_HDMI_CLK_ASIC_IN 2 0x8033 3 0 4294967295 MPLLA_HDMI_PIXEL_CLK_DIV 0 1 MPLLA_HDMI_DIV 2 4 RESERVED_15_5 5 15 ixDPCSSYS_CR1_SUPX_DIG_MPLLB_DIV_CLK_ASIC_IN 2 0x8034 3 0 4294967295 MPLLB_DIV_CLK_EN 0 0 MPLLB_DIV_MULTIPLIER 1 8 RESERVED_15_9 9 15 ixDPCSSYS_CR1_SUPX_DIG_MPLLB_HDMI_CLK_ASIC_IN 2 0x8035 3 0 4294967295 MPLLB_HDMI_PIXEL_CLK_DIV 0 1 MPLLB_HDMI_DIV 2 4 RESERVED_15_5 5 15 ixDPCSSYS_CR1_SUPX_DIG_ASIC_IN 2 0x8036 12 0 4294967295 PHY_RESET 0 0 REF_CLK_EN 1 1 REF_USE_PAD 2 2 TEST_BURNIN 3 3 TEST_POWERDOWN 4 4 RTUNE_REQ 5 5 RTUNE_ACK 6 6 MPLLA_STATE 7 7 MPLLB_STATE 8 8 TEST_TX_REF_CLK_EN 9 9 REF_ALT_CLK_LP_SEL 10 10 RESERVED_15_11 11 15 ixDPCSSYS_CR1_SUPX_DIG_LVL_ASIC_IN 2 0x8037 4 0 4294967295 RX_VREF_CTRL 0 2 TX_VBOOST_LVL 3 5 SUP_RX_VCO_VREF_SEL 6 8 RESERVED_15_9 9 15 ixDPCSSYS_CR1_SUPX_DIG_BANDGAP_ASIC_IN 2 0x8038 2 0 4294967295 BG_EN 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR1_SUPX_DIG_MPLLA_CP_ASIC_IN 2 0x8039 3 0 4294967295 MPLLA_CP_PROP 0 6 MPLLA_CP_INT 7 13 RESERVED_15_14 14 15 ixDPCSSYS_CR1_SUPX_DIG_MPLLA_CP_GS_ASIC_IN 2 0x803a 3 0 4294967295 MPLLA_CP_PROP_GS 0 6 MPLLA_CP_INT_GS 7 13 RESERVED_15_14 14 15 ixDPCSSYS_CR1_SUPX_DIG_MPLLB_CP_ASIC_IN 2 0x803b 3 0 4294967295 MPLLB_CP_PROP 0 6 MPLLB_CP_INT 7 13 RESERVED_15_14 14 15 ixDPCSSYS_CR1_SUPX_DIG_MPLLB_CP_GS_ASIC_IN 2 0x803c 3 0 4294967295 MPLLB_CP_PROP_GS 0 6 MPLLB_CP_INT_GS 7 13 RESERVED_15_14 14 15 ixDPCSSYS_CR1_SUPX_ANA_PRESCALER_CTRL 2 0x8040 7 0 4294967295 PSCALER_ATB_SELECT 0 0 PSCALER_MEAS_VREG 0 0 PSCALER_OVRD_FAST_START 0 0 PSCALER_FAST_START_REG 0 0 PSCALER_VREG_BOOST 0 0 PSCALER_HYST_REF 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR1_SUPX_ANA_RTUNE_CTRL 2 0x8041 9 0 4294967295 RT_ATB 0 0 RT_SEL_ATBF 0 0 RT_SEL_ATBP 0 0 RT_VP4O8_EN 0 0 RT_DAC_CHOP 0 0 RT_DAC_MODE 0 0 RT_EN_FRCON 0 0 PSCALER_VREG_FB_DIV_CTRL 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR1_SUPX_ANA_BG1 2 0x8042 6 0 4294967295 SUP_SEL_VBG_VREF 0 0 SUP_SEL_VPHUD_VREF 0 0 NC4 4 4 SUP_SEL_VPLL_REF 0 0 RT_VREF_SEL 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR1_SUPX_ANA_BG2 2 0x8043 9 0 4294967295 SUP_BYPASS_BG 0 0 SUP_CHOP_EN 0 0 SUP_TEMP_MEAS 0 0 VPHUD_SELREF 0 0 ATB_EXT_MEAS_EN 0 0 RT_TX_OFFSET_EN 0 0 SUP_SEL_TX_SWING_VREF 0 0 PSCALER_VREG_OVERRIDE_RING_CTRL 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR1_SUPX_ANA_SWITCH_PWR_MEAS 2 0x8044 3 0 4294967295 SUP_ATB_SW 0 0 SUP_TIE 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR1_SUPX_ANA_BG3 2 0x8045 4 0 4294967295 SUP_SEL_RX_VCO_TC_VREF 0 0 SUP_SEL_RX_CAL_VREF 0 0 NC7_4 4 7 RESERVED_15_8 8 15 ixDPCSSYS_CR1_SUPX_ANA_MPLLA_MISC1 2 0x8046 7 0 4294967295 OVRD_GEAR_RC_FILT 0 0 OVRD_TEST_RC_FILT 0 0 TEST_VREG_DIV 0 0 VBG_EN 0 0 COUNT_SEL_LOCK 0 0 PHASE_SEL_LOCK 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR1_SUPX_ANA_MPLLA_MISC2 2 0x8047 8 0 4294967295 OVRD_PR_BYPASS 0 0 PR_BYPASS 0 0 OVRD_GEARSHIFT 0 0 GEARSHIFT_REG 0 0 TEST_LOCK_GEAR 0 0 EN_CAL_SPO 0 0 TEST_BOOST 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR1_SUPX_ANA_MPLLA_OVRD 2 0x8048 9 0 4294967295 OVRD_ENABLE 0 0 ENABLE_REG 0 0 OVRD_CAL 0 0 CAL_REG 0 0 OVRD_FB_CLK_EN 0 0 FB_CLK_EN_REG 0 0 OVRD_RESET 0 0 RESET_REG 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR1_SUPX_ANA_MPLLA_ATB1 2 0x8049 3 0 4294967295 MEAS_IV_WRAP 0 0 ATB_SELECT 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR1_SUPX_ANA_MPLLA_ATB2 2 0x804a 2 0 4294967295 MEAS_IV_PLL 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR1_SUPX_ANA_MPLLA_ATB3 2 0x804b 3 0 4294967295 MEAS_IV_BIAS 0 0 CTR_UPLL_TUNNING 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR1_SUPX_ANA_MPLLA_CTR1 2 0x804c 5 0 4294967295 CTR_ICP_INT 0 0 CTR_VREF_EN 0 0 CTR_VREF_VMARG 0 0 CTR_CP_PLL 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR1_SUPX_ANA_MPLLA_CTR2 2 0x804d 2 0 4294967295 CTR_REGS_PLL 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR1_SUPX_ANA_MPLLA_CTR3 2 0x804e 4 0 4294967295 CTR_REGS_CP_PLL 0 0 CTR_SPO_PLL 0 0 CTR_VINT_CAP 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR1_SUPX_ANA_MPLLA_CTR4 2 0x804f 7 0 4294967295 CTR_CP_8X 0 0 CTR_FIL_REG 0 0 CTR_CP_PROP_REF 0 0 CTR_DOUBLER_GAIN 0 0 CTR_TEST_CASC 0 0 CTR_RC_FITER 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR1_SUPX_ANA_MPLLA_CTR5 2 0x8050 8 0 4294967295 CTR_STANDBY_MODE 0 0 CTR_LEG_SR_CON 0 0 CTR_VREG_RING_OVERRIDE 0 0 CTR_SPO_SPEED_OVERRIDE 0 0 CTR_BYPASS_LOCK_SPO_CAL 0 0 CTR_LOCK_SPO_CAL 0 0 CTR_UPLL_RESERVED 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR1_SUPX_ANA_MPLLA_RESERVED1 2 0x8051 8 0 4294967295 CTR_REF_FBK_BYPASS 0 0 CTR_BYPASS_TX 0 0 CTR_VREG_CLK_BYPASS 0 0 CTR_VREG_CLK_PMIX_BYPASS 0 0 CTR_VREG_RIGHT_BYPASS 0 0 CTR_VREG_LEFT_BYPASS 0 0 CTR_LEFT_RIGHT_GAIN 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR1_SUPX_ANA_MPLLA_RESERVED2 2 0x8052 5 0 4294967295 CTR_DLL_MODE_90 0 0 CTR_DLL_RESERVED 0 0 CTR_DIV24_DSQ_ENZ 0 0 CTR_DIV4 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR1_SUPX_ANA_MPLLB_MISC1 2 0x8053 7 0 4294967295 OVRD_GEAR_RC_FILT 0 0 OVRD_TEST_RC_FILT 0 0 TEST_VREG_DIV 0 0 VBG_EN 0 0 COUNT_SEL_LOCK 0 0 PHASE_SEL_LOCK 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR1_SUPX_ANA_MPLLB_MISC2 2 0x8054 8 0 4294967295 OVRD_PR_BYPASS 0 0 PR_BYPASS 0 0 OVRD_GEARSHIFT 0 0 GEARSHIFT_REG 0 0 TEST_LOCK_GEAR 0 0 EN_CAL_SPO 0 0 TEST_BOOST 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR1_SUPX_ANA_MPLLB_OVRD 2 0x8055 9 0 4294967295 OVRD_ENABLE 0 0 ENABLE_REG 0 0 OVRD_CAL 0 0 CAL_REG 0 0 OVRD_FB_CLK_EN 0 0 FB_CLK_EN_REG 0 0 OVRD_RESET 0 0 RESET_REG 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR1_SUPX_ANA_MPLLB_ATB1 2 0x8056 3 0 4294967295 MEAS_IV_WRAP 0 0 ATB_SELECT 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR1_SUPX_ANA_MPLLB_ATB2 2 0x8057 2 0 4294967295 MEAS_IV_PLL 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR1_SUPX_ANA_MPLLB_ATB3 2 0x8058 3 0 4294967295 MEAS_IV_BIAS 0 0 CTR_UPLL_TUNNING 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR1_SUPX_ANA_MPLLB_CTR1 2 0x8059 5 0 4294967295 CTR_ICP_INT 0 0 CTR_VREF_EN 0 0 CTR_VREF_VMARG 0 0 CTR_CP_PLL 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR1_SUPX_ANA_MPLLB_CTR2 2 0x805a 2 0 4294967295 CTR_REGS_PLL 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR1_SUPX_ANA_MPLLB_CTR3 2 0x805b 4 0 4294967295 CTR_REGS_CP_PLL 0 0 CTR_SPO_PLL 0 0 CTR_VINT_CAP 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR1_SUPX_ANA_MPLLB_CTR4 2 0x805c 7 0 4294967295 CTR_CP_8X 0 0 CTR_FIL_REG 0 0 CTR_CP_PROP_REF 0 0 CTR_DOUBLER_GAIN 0 0 CTR_TEST_CASC 0 0 CTR_RC_FITER 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR1_SUPX_ANA_MPLLB_CTR5 2 0x805d 8 0 4294967295 CTR_STANDBY_MODE 0 0 CTR_LEG_SR_CON 0 0 CTR_VREG_RING_OVERRIDE 0 0 CTR_SPO_SPEED_OVERRIDE 0 0 CTR_BYPASS_LOCK_SPO_CAL 0 0 CTR_LOCK_SPO_CAL 0 0 CTR_UPLL_RESERVED 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR1_SUPX_ANA_MPLLB_RESERVED1 2 0x805e 8 0 4294967295 CTR_REF_FBK_BYPASS 0 0 CTR_BYPASS_TX 0 0 CTR_VREG_CLK_BYPASS 0 0 CTR_VREG_CLK_PMIX_BYPASS 0 0 CTR_VREG_RIGHT_BYPASS 0 0 CTR_VREG_LEFT_BYPASS 0 0 CTR_LEFT_RIGHT_GAIN 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR1_SUPX_ANA_MPLLB_RESERVED2 2 0x805f 5 0 4294967295 CTR_DLL_MODE_90 0 0 CTR_DLL_RESERVED 0 0 CTR_DIV24_DSQ_ENZ 0 0 CTR_DIV4 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD 2 0x8061 8 0 4294967295 OVRD_SEL 0 0 MPLL_FBDIGCLK_EN 1 1 MPLL_PCLK_EN 2 2 FAST_MPLL_PWRUP 3 3 FAST_MPLL_LOCK 4 4 DTB_SEL 5 9 DIV10_EN 10 10 RESERVED 11 15 ixDPCSSYS_CR1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT 2 0x8062 11 0 4294967295 FSM_STATE 0 3 MPLL_R_LANES 4 4 MPLL_L_LANES 5 5 MPLL_PCLK_EN 6 6 MPLL_OUTPUT_EN 7 7 MPLL_FBCLK_EN 8 8 MPLL_CAL 9 9 MPLL_RST 10 10 MPLL_ANA_EN 11 11 MPLL_LOCK 12 12 RESERVED_15_13 13 15 ixDPCSSYS_CR1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE 2 0x8063 3 0 4294967295 MAX_RANGE 0 4 DAC_IN 5 9 RESERVED_15_10 10 15 ixDPCSSYS_CR1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_LOCK 2 0x8064 3 0 4294967295 LOCK_TIME 0 7 STABLE_TIME 8 13 RESERVED_15_14 14 15 ixDPCSSYS_CR1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS 2 0x8065 2 0 4294967295 GEARSHIFT_TIME 0 7 PRESET_TIME 8 15 ixDPCSSYS_CR1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE 2 0x8066 3 0 4294967295 PWRDN_WAIT_TIME 0 5 PCLK_EN_TIME 6 11 RESERVED_15_12 12 15 ixDPCSSYS_CR1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2 2 0x8067 3 0 4294967295 PCLK_DIS_TIME 0 5 PWRDN_TIME 6 11 RESERVED_15_12 12 15 ixDPCSSYS_CR1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_CAL 2 0x8068 3 0 4294967295 MPLL_CAL 0 0 MPLL_CAL_OVRD_EN 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT 2 0x8069 2 0 4294967295 MPLL_ANA_DAC_OUT 0 4 RESERVED_15_5 5 15 ixDPCSSYS_CR1_SUPX_DIG_MPLLA_SSC_GEN_SPREAD_TYPE 2 0x806b 3 0 4294967295 SPREAD_TYPE 0 1 OVR_EN 2 2 RESERVED_15_3 3 15 ixDPCSSYS_CR1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD 2 0x806d 8 0 4294967295 OVRD_SEL 0 0 MPLL_FBDIGCLK_EN 1 1 MPLL_PCLK_EN 2 2 FAST_MPLL_PWRUP 3 3 FAST_MPLL_LOCK 4 4 DTB_SEL 5 9 DIV10_EN 10 10 RESERVED 11 15 ixDPCSSYS_CR1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT 2 0x806e 11 0 4294967295 FSM_STATE 0 3 MPLL_R_LANES 4 4 MPLL_L_LANES 5 5 MPLL_PCLK_EN 6 6 MPLL_OUTPUT_EN 7 7 MPLL_FBCLK_EN 8 8 MPLL_CAL 9 9 MPLL_RST 10 10 MPLL_ANA_EN 11 11 MPLL_LOCK 12 12 RESERVED_15_13 13 15 ixDPCSSYS_CR1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE 2 0x806f 3 0 4294967295 MAX_RANGE 0 4 DAC_IN 5 9 RESERVED_15_10 10 15 ixDPCSSYS_CR1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_LOCK 2 0x8070 3 0 4294967295 LOCK_TIME 0 7 STABLE_TIME 8 13 RESERVED_15_14 14 15 ixDPCSSYS_CR1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS 2 0x8071 2 0 4294967295 GEARSHIFT_TIME 0 7 PRESET_TIME 8 15 ixDPCSSYS_CR1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE 2 0x8072 3 0 4294967295 PWRDN_WAIT_TIME 0 5 PCLK_EN_TIME 6 11 RESERVED_15_12 12 15 ixDPCSSYS_CR1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2 2 0x8073 3 0 4294967295 PCLK_DIS_TIME 0 5 PWRDN_TIME 6 11 RESERVED_15_12 12 15 ixDPCSSYS_CR1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_CAL 2 0x8074 3 0 4294967295 MPLL_CAL 0 0 MPLL_CAL_OVRD_EN 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT 2 0x8075 2 0 4294967295 MPLL_ANA_DAC_OUT 0 4 RESERVED_15_5 5 15 ixDPCSSYS_CR1_SUPX_DIG_MPLLB_SSC_GEN_SPREAD_TYPE 2 0x8077 3 0 4294967295 SPREAD_TYPE 0 1 OVR_EN 2 2 RESERVED_15_3 3 15 ixDPCSSYS_CR1_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_0 2 0x8078 3 0 4294967295 BG_SUP_EN_TIME 0 8 FAST_BG_WAIT 9 9 RESERVED_15_10 10 15 ixDPCSSYS_CR1_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_1 2 0x8079 2 0 4294967295 BG_LANE_EN_TIME 0 8 RESERVED_15_9 9 15 ixDPCSSYS_CR1_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_2 2 0x807a 3 0 4294967295 BG_KICK_START_EN_TIME 0 7 BG_SUP_STATE_UPD_EN 8 8 RESERVED_15_9 9 15 ixDPCSSYS_CR1_SUPX_DIG_CLK_RST_REF_PWRUP_TIME_0 2 0x807b 3 0 4294967295 REF_VREG_FAST_START_TIME 0 4 FAST_REF_WAIT 5 5 RESERVED_15_6 6 15 ixDPCSSYS_CR1_SUPX_DIG_CLK_RST_REF_VPHUD 2 0x807c 3 0 4294967295 SUP_ANA_VPHUD_SELVPH_I 0 0 SUP_ANA_VPHUD_EN_I 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR1_SUPX_DIG_RTUNE_CONFIG 2 0x8081 5 0 4294967295 RX_CAL_EN 0 0 FAST_RTUNE 1 1 TX_CAL_EN 2 2 SUP_ANA_TERM_CTRL 3 5 RESERVED_15_6 6 15 ixDPCSSYS_CR1_SUPX_DIG_RTUNE_STAT 2 0x8082 3 0 4294967295 STAT 0 9 DTB_RTUNE 10 11 RESERVED_15_12 12 15 ixDPCSSYS_CR1_SUPX_DIG_RTUNE_RX_SET_VAL 2 0x8083 2 0 4294967295 RX_SET_VAL 0 5 RESERVED_15_6 6 15 ixDPCSSYS_CR1_SUPX_DIG_RTUNE_TXDN_SET_VAL 2 0x8084 2 0 4294967295 TXDN_SET_VAL 0 9 RESERVED_15_10 10 15 ixDPCSSYS_CR1_SUPX_DIG_RTUNE_TXUP_SET_VAL 2 0x8085 2 0 4294967295 TXUP_SET_VAL 0 9 RESERVED_15_10 10 15 ixDPCSSYS_CR1_SUPX_DIG_RTUNE_RX_STAT 2 0x8086 2 0 4294967295 RX_STAT 0 5 RESERVED_15_6 6 15 ixDPCSSYS_CR1_SUPX_DIG_RTUNE_TXDN_STAT 2 0x8087 2 0 4294967295 TXDN_STAT 0 9 RESERVED_15_10 10 15 ixDPCSSYS_CR1_SUPX_DIG_RTUNE_TXUP_STAT 2 0x8088 2 0 4294967295 TXUP_STAT 0 9 RESERVED_15_10 10 15 ixDPCSSYS_CR1_SUPX_DIG_RTUNE_CONFIG_CNT0 2 0x8089 4 0 4294967295 RT_RESULT_TIME 0 3 RT_EVAL_TIME 4 7 RT_RST_TIME 8 11 RT_ACK_TIME 12 15 ixDPCSSYS_CR1_SUPX_DIG_RTUNE_CONFIG_CNT1 2 0x808a 3 0 4294967295 RT_TXDN_SETTLE_TIME 0 3 RT_PWRUP_TIME 4 8 RESERVED_15_9 9 15 ixDPCSSYS_CR1_SUPX_DIG_RTUNE_TX_CAL_CODE 2 0x808b 2 0 4294967295 VALUE 0 3 RESERVED_15_4 4 15 ixDPCSSYS_CR1_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0 2 0x808c 16 0 4294967295 MPLLA_WORD_CLK_EN 0 0 MPLLA_HDMI_CLK_EN 1 1 MPLLA_DIV_CLK_EN 2 2 MPLLA_OUTPUT_EN 3 3 MPLLA_CLK_EN_OVRD_EN 4 4 MPLLA_OUTPUT_L_EN 5 5 MPLLA_OUTPUT_R_EN 6 6 MPLLA_ANA_EN 7 7 MPLLA_RST 8 8 MPLLA_CAL 9 9 MPLLA_DIV5_CLK_EN 10 10 MPLLA_DIV10_CLK_EN 11 11 MPLLA_FBCLK_EN 12 12 MPLLA_GEARSHIFT_EN 13 13 MPLLA_STANDBY 14 14 OVRD_SEL 15 15 ixDPCSSYS_CR1_SUPX_DIG_ANA_MPLLA_OVRD_OUT_1 2 0x808d 2 0 4294967295 MPLLA_ANA_INT 0 9 RESERVED_15_10 10 15 ixDPCSSYS_CR1_SUPX_DIG_ANA_MPLLA_OVRD_OUT_2 2 0x808e 3 0 4294967295 MPLLA_CP_PROP 0 6 MPLLA_CP_INT 7 13 RESERVED_15_14 14 15 ixDPCSSYS_CR1_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0 2 0x808f 16 0 4294967295 MPLLB_WORD_CLK_EN 0 0 MPLLB_HDMI_CLK_EN 1 1 MPLLB_DIV_CLK_EN 2 2 MPLLB_OUTPUT_EN 3 3 MPLLB_CLK_EN_OVRD_EN 4 4 MPLLB_OUTPUT_L_EN 5 5 MPLLB_OUTPUT_R_EN 6 6 MPLLB_ANA_EN 7 7 MPLLB_RST 8 8 MPLLB_CAL 9 9 MPLLB_DIV5_CLK_EN 10 10 MPLLB_DIV10_CLK_EN 11 11 MPLLB_FBCLK_EN 12 12 MPLLB_GEARSHIFT_EN 13 13 MPLLB_STANDBY 14 14 OVRD_SEL 15 15 ixDPCSSYS_CR1_SUPX_DIG_ANA_MPLLB_OVRD_OUT_1 2 0x8090 2 0 4294967295 MPLLB_ANA_INT 0 9 RESERVED_15_10 10 15 ixDPCSSYS_CR1_SUPX_DIG_ANA_MPLLB_OVRD_OUT_2 2 0x8091 3 0 4294967295 MPLLB_CP_PROP 0 6 MPLLB_CP_INT 7 13 RESERVED_15_14 14 15 ixDPCSSYS_CR1_SUPX_DIG_ANA_RTUNE_OVRD_OUT 2 0x8092 6 0 4294967295 RTUNE_COMP_RST 0 0 RTUNE_MODE 1 2 RTUNE_EN 3 3 RTUNE_VALUE 4 13 RTUNE_OVRD_EN 14 14 RESERVED_15_15 15 15 ixDPCSSYS_CR1_SUPX_DIG_ANA_STAT 2 0x8093 3 0 4294967295 RT_ANA_COMP_RESULT 0 0 REF_ANA_CLKDET_RESULT 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR1_SUPX_DIG_ANA_BG_OVRD_OUT 2 0x8094 11 0 4294967295 BG_EN 0 0 BG_FAST_START 1 1 BG_KICK_START 2 2 BG_OVRD_EN 3 3 ANA_ASYNC_RST 4 4 ANA_ASYNC_RST_OVRD_EN 5 5 REF_VREG_FAST_START 6 6 REF_VREG_FAST_START_OVRD_EN 7 7 REF_VREG_REF_SEL 8 9 REF_VREG_REF_SEL_OVRD_EN 10 10 RESERVED_15_11 11 15 ixDPCSSYS_CR1_SUPX_DIG_ANA_MPLLA_PMIX_OVRD_OUT 2 0x8095 5 0 4294967295 MPLLA_PMIX_SEL 0 5 MPLLA_PMIX_EN 6 6 MPLLA_PMIX_SEL_OVRD_EN 7 7 MPLLA_PMIX_EN_OVRD_EN 8 8 RESERVED_15_9 9 15 ixDPCSSYS_CR1_SUPX_DIG_ANA_MPLLB_PMIX_OVRD_OUT 2 0x8096 5 0 4294967295 MPLLB_PMIX_SEL 0 5 MPLLB_PMIX_EN 6 6 MPLLB_PMIX_SEL_OVRD_EN 7 7 MPLLB_PMIX_EN_OVRD_EN 8 8 RESERVED_15_9 9 15 ixDPCSSYS_CR1_LANEX_DIG_ASIC_LANE_OVRD_IN 2 0x9000 5 0 4294967295 LANE_TX2RX_SER_LB 0 0 LANE_RX2TX_PAR_LB 1 1 EN 2 2 RX_ACJTAG_EN 3 3 RESERVED_15_4 4 15 ixDPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_0 2 0x9001 12 0 4294967295 REQ 0 0 REQ_OVRD_EN 1 1 PSTATE 2 3 PSTATE_OVRD_EN 4 4 RATE 5 7 RATE_OVRD_EN 8 8 WIDTH 9 10 WIDTH_OVRD_EN 11 11 MPLLB_SEL 12 12 MPLLB_SEL_OVRD_EN 13 13 DATA_EN 14 14 DATA_EN_OVRD_EN 15 15 ixDPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_1 2 0x9002 11 0 4294967295 NYQUIST_DATA 0 0 DISABLE 1 1 BEACON_EN 2 2 EN 3 3 TX_MAIN_CURSOR 4 9 MAIN_OVRD_EN 10 10 ASYNC_DRV_EN 11 11 ASYNC_DRV_OVRD_EN 12 12 TX_VREGDRV_BYP_OVRD 13 13 TX_VREGDRV_BYP_OVRD_EN 14 14 RESERVED_15_15 15 15 ixDPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_2 2 0x9003 6 0 4294967295 TX_PRE_CURSOR 0 5 PRE_OVRD_EN 6 6 TX_POST_CURSOR 7 12 POST_OVRD_EN 13 13 HDMIMODE_EN 14 14 HDMIMODE_ENABLE_OVRD_EN 15 15 ixDPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_3 2 0x9004 15 0 4294967295 CLK_RDY 0 0 CLK_RDY_OVRD_EN 1 1 DETECT_RX_REQ 2 2 DETECT_RX_REQ_OVRD_EN 3 3 INVERT 4 4 INVERT_OVRD_EN 5 5 LPD 6 6 LPD_OVRD_EN 7 7 TX_DC_COUP_EN 8 8 TX_DC_COUP_EN_OVRD_EN 9 9 PMA_EXTENDED_FIFO_EN 10 10 PMA_EXTENDED_FIFO_EN_OVRD_EN 11 11 TX_MPHY_MODE_EN 12 12 TX_MPHY_MODE_EN_OVRD_EN 13 13 RESERVED_15_14 14 15 ixDPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_4 2 0x9005 3 0 4294967295 RESET 0 0 RESET_OVRD_EN 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_OUT 2 0x9006 5 0 4294967295 TX_ACK 0 0 EN_TX_ACK 1 1 DETRX_RESULT 2 2 EN_DETRX_RESULT 3 3 RESERVED_15_4 4 15 ixDPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_0 2 0x9007 11 0 4294967295 REQ 0 0 REQ_OVRD_EN 1 1 DATA_EN 2 2 DATA_EN_OVRD_EN 3 3 PSTATE 4 5 PSTATE_OVRD_EN 6 6 RATE 7 8 RATE_OVRD_EN 9 9 WIDTH 10 11 WIDTH_OVRD_EN 12 12 RESERVED_15_13 13 15 ixDPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_1 2 0x9008 5 0 4294967295 RX_REF_LD_VAL_5_0 0 5 RX_CDR_VCO_LOWFREQ 6 6 EN 7 7 RX_REF_LD_VAL_6 8 8 RESERVED_15_9 9 15 ixDPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_2 2 0x9009 3 0 4294967295 RX_VCO_LD_VAL 0 12 EN 13 13 RESERVED_15_14 14 15 ixDPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_3 2 0x900a 11 0 4294967295 CDR_TRACK_EN 0 0 CDR_TRACK_EN_OVRD_EN 1 1 CDR_SSC_EN 2 2 CDR_SSC_EN_OVRD_EN 3 3 ALIGN_EN 4 4 ALIGN_EN_OVRD_EN 5 5 CLK_SHIFT 6 6 CLK_SHIFT_OVRD_EN 7 7 DISABLE 8 8 DISABLE_OVRD_EN 9 9 RESERVED_15_10 10 15 ixDPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_4 2 0x900b 11 0 4294967295 LPD 0 0 LPD_OVRD_EN 1 1 INVERT 2 2 INVERT_OVRD_EN 3 3 ADAPT_AFE_EN 4 4 ADAPT_DFE_EN 5 5 ADPT_OVRD_EN 6 6 TERM_EN 7 7 TERM_ACDC 8 8 TERM_OVRD_EN 9 9 RESERVED_15_10 10 15 ixDPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_5 2 0x900c 3 0 4294967295 RESET 0 0 RESET_OVRD_EN 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0 2 0x900d 4 0 4294967295 EQ_ATT_LVL 0 2 EQ_AFE_GAIN 3 6 RESERVED 7 10 EQ_CTLE_BOOST 11 15 ixDPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1 2 0x900e 3 0 4294967295 EQ_DFE_TAP2 0 6 EQ_DFE_TAP1 7 14 EQ_OVRD_EN 15 15 ixDPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_OUT_0 2 0x900f 9 0 4294967295 ACK 0 0 ACK_OVRD_EN 1 1 ADAPT_STS 2 3 ADAPT_STS_OVRD_EN 4 4 RX_ASYNC_DATA 5 5 RX_ASYNC_DATA_OVRD_EN 6 6 RX_SQ_WEAKKEEP_OUT 7 7 RX_SQ_WEAKKEEP_OUT_OVRD_EN 8 8 RESERVED_15_9 9 15 ixDPCSSYS_CR1_LANEX_DIG_ASIC_LANE_ASIC_IN 2 0x9010 3 0 4294967295 LANE_TX2RX_SER_LB 0 0 LANE_RX2TX_PAR_LB 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR1_LANEX_DIG_ASIC_TX_ASIC_IN_0 2 0x9011 12 0 4294967295 CLK_RDY 0 0 RESET 1 1 INVERT 2 2 DATA_EN 3 3 REQ 4 4 LPD 5 5 PSTATE 6 7 RATE 8 10 WIDTH 11 12 MPLLB_SEL 13 13 DETECT_RX_REQ 14 14 DISABLE 15 15 ixDPCSSYS_CR1_LANEX_DIG_ASIC_TX_ASIC_IN_1 2 0x9012 7 0 4294967295 BEACON_EN 0 0 TX_MAIN_CURSOR 1 6 TX_ASYNC_EN 7 7 TX_ASYNC_DATA 8 8 TX_ASYNC_DRV_EN 9 9 TX_VREGDRV_BYP 10 10 RESERVED_15_11 11 15 ixDPCSSYS_CR1_LANEX_DIG_ASIC_TX_ASIC_IN_2 2 0x9013 3 0 4294967295 TX_PRE_CURSOR 0 5 TX_POST_CURSOR 6 11 RESERVED_15_12 12 15 ixDPCSSYS_CR1_LANEX_DIG_ASIC_TX_ASIC_OUT 2 0x9014 3 0 4294967295 TX_ACK 0 0 DETRX_RESULT 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR1_LANEX_DIG_ASIC_RX_ASIC_IN_0 2 0x9015 13 0 4294967295 RESET 0 0 INVERT 1 1 DATA_EN 2 2 REQ 3 3 LPD 4 4 PSTATE 5 6 RATE 7 8 WIDTH 9 10 RESERVED 11 11 ADAPT_AFE_EN 12 12 ADAPT_DFE_EN 13 13 CDR_TRACK_EN 14 14 RESERVED_15_15 15 15 ixDPCSSYS_CR1_LANEX_DIG_ASIC_RX_ASIC_IN_1 2 0x9016 7 0 4294967295 CDR_SSC_EN 0 0 ALIGN_EN 1 1 CLK_SHIFT 2 2 DISABLE 3 3 RX_TERM_EN 4 4 RX_TERM_ACDC 5 5 RESERVED_15_6 6 15 ixDPCSSYS_CR1_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0 2 0x9017 4 0 4294967295 EQ_ATT_LVL 0 2 EQ_AFE_GAIN 3 6 RESERVED 7 10 EQ_CTLE_BOOST 11 15 ixDPCSSYS_CR1_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_1 2 0x9018 3 0 4294967295 EQ_DFE_TAP2 0 6 EQ_DFE_TAP1 7 14 RESERVED_15_15 15 15 ixDPCSSYS_CR1_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0 2 0x9019 3 0 4294967295 RX_CDR_VCO_LOWFREQ 0 0 RX_REF_LD_VAL 1 7 RESERVED_15_8 8 15 ixDPCSSYS_CR1_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1 2 0x901a 2 0 4294967295 RX_VCO_LD_VAL 0 12 RESERVED_15_13 13 15 ixDPCSSYS_CR1_LANEX_DIG_ASIC_RX_ASIC_OUT_0 2 0x901b 4 0 4294967295 ACK 0 0 VALID 1 1 ADAPT_STS 2 3 RESERVED_15_4 4 15 ixDPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_6 2 0x901c 10 0 4294967295 RX_PWM_CLK_SEL 0 1 RX_PWM_CLK_SEL_OVRD_EN 2 2 RX_TERM_LCC_ON 3 3 RX_TERM_LS_ON 4 4 RX_TERM_LS_LCC_ON_OVRD_EN 5 5 RX_TERM_CTL 6 7 RX_TERM_CTL_OVRD_EN 8 8 RX_PWM_EN 9 9 RX_PWM_EN_OVRD_EN 10 10 RESERVED_15_11 11 15 ixDPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_5 2 0x901d 15 0 4294967295 RPTR_EN_MASTER_LANE 0 0 RPTR_EN_MASTER_LANE_OVRD_EN 1 1 DIG_CLK_EN_OTHER_LANE 2 2 DIG_CLK_EN_OTHER_LANE_OVRD_EN 3 3 DIG_CLK_STATE_MASTER_LANE 4 4 DIG_CLK_STATE_MASTER_LANE_OVRD_EN 5 5 SHIFT_MASTER_LANE 6 6 SHIFT_MASTER_LANE_ORVD_EN 7 7 SHIFT_ACK_OTHER_LANE 8 8 SHIFT_ACK_OTHER_LANE_OVRD_EN 9 9 LANE_MASTER 10 10 LANE_MASTER_OVRD_IN_EN 11 11 TX_DWORD_CLK_SYNC_OVRD 12 12 TX_DWORD_CLK_SYNC_OVRD_EN 13 13 RESERVED_15_14 14 15 ixDPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_OUT_1 2 0x901e 11 0 4294967295 RPTR_EN_OUT 0 0 RPTR_EN_OUT_OVRD_EN 1 1 DIG_CLK_EN_OUT 2 2 DIG_CLK_EN_OUT_OVRD_EN 3 3 DIG_CLK_STATE_OUT 4 4 DIG_CLK_STATE_OUT_OVRD_EN 5 5 SHIFT_OUT 6 6 SHIFT_OUT_OVRD_EN 7 7 SHIFT_ACK_OUT 8 8 SHIFT_ACK_OUT_OVRD_EN 9 9 RESERVED_15_10 10 15 ixDPCSSYS_CR1_LANEX_DIG_ASIC_OCLA 2 0x901f 3 0 4294967295 RX_DWORD_OCLA_CLK_EN 0 0 RX_DWORD_OCLA_DATA_EN 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0 2 0x9020 11 0 4294967295 TX_P0_ANA_REFGEN_EN 0 0 TX_P0_ANA_VCM_HOLD 1 1 TX_P0_ANA_CLK_EN 2 2 TX_P0_ANA_WORD_CLK_EN 3 3 TX_P0_ANA_RESET 4 4 TX_P0_ANA_SERIAL_EN 5 5 TX_P0_DIG_CLK_EN 6 6 TX_P0_DATA_EN 7 7 TX_P0_ALLOW_RXDET 8 8 TX_P0_ANA_DCC_COMP_CAL_EN 9 9 RESERVED_15_10 10 15 ixDPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S 2 0x9021 11 0 4294967295 TX_P0S_ANA_REFGEN_EN 0 0 TX_P0S_ANA_VCM_HOLD 1 1 TX_P0S_ANA_CLK_EN 2 2 TX_P0S_ANA_WORD_CLK_EN 3 3 TX_P0S_ANA_RESET 4 4 TX_P0S_ANA_SERIAL_EN 5 5 TX_P0S_DIG_CLK_EN 6 6 TX_P0S_DATA_EN 7 7 TX_P0S_ALLOW_RXDET 8 8 TX_P0S_ANA_DCC_COMP_CAL_EN 9 9 RESERVED_15_10 10 15 ixDPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1 2 0x9022 11 0 4294967295 TX_P1_ANA_REFGEN_EN 0 0 TX_P1_ANA_VCM_HOLD 1 1 TX_P1_ANA_CLK_EN 2 2 TX_P1_ANA_WORD_CLK_EN 3 3 TX_P1_ANA_RESET 4 4 TX_P1_ANA_SERIAL_EN 5 5 TX_P1_DIG_CLK_EN 6 6 TX_P1_DATA_EN 7 7 TX_P1_ALLOW_RXDET 8 8 TX_P1_ANA_DCC_COMP_CAL_EN 9 9 RESERVED_15_10 10 15 ixDPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2 2 0x9023 12 0 4294967295 TX_P2_ANA_REFGEN_EN 0 0 TX_P2_ANA_VCM_HOLD 1 1 TX_P2_ANA_CLK_EN 2 2 TX_P2_ANA_WORD_CLK_EN 3 3 TX_P2_ANA_RESET 4 4 TX_P2_ANA_SERIAL_EN 5 5 TX_P2_DIG_CLK_EN 6 6 TX_P2_DATA_EN 7 7 TX_P2_ALLOW_RXDET 8 8 TX_P2_ALLOW_VBOOST 9 9 TX_P2_ANA_DCC_COMP_CAL_EN 10 10 RESERVED_15_11 11 15 ixDPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_0 2 0x9024 2 0 4294967295 TX_REFGEN_EN_TIME 0 7 TX_CLK_EN 8 15 ixDPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_1 2 0x9025 2 0 4294967295 TX_VCM_HOLD_TIME_14_0 0 14 SKIP_TX_VCM_HOLD_WAIT 15 15 ixDPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_2 2 0x9026 2 0 4294967295 TX_VBOOST_DIS_TIME_12_0 0 12 DTB_SEL 13 15 ixDPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_3 2 0x9027 3 0 4294967295 TX_VCM_HOLD_TIME_17_15 0 2 TX_VBOOST_DIS_TIME_13 3 3 RESERVED_15_4 4 15 ixDPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_4 2 0x9028 2 0 4294967295 TX_VCM_HOLD_GS_TIME 0 14 SKIP_TX_VCM_HOLD_GS_PULSE 15 15 ixDPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_5 2 0x9029 5 0 4294967295 TX_RXDET_TIME 0 9 FAST_TX_RXDET 10 10 TX_RESET_TIME 11 12 TX_SERIAL_EN_TIME 13 14 RESERVED_15_15 15 15 ixDPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_DCC_CR_BANK_ADDR 2 0x902a 1 0 4294967295 ADDR 0 15 ixDPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_DCC_CR_BANK_DATA 2 0x902b 1 0 4294967295 DATA 0 15 ixDPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_DCC_DAC_CTRL 2 0x902c 2 0 4294967295 CTRL 0 7 RESERVED_15_8 8 15 ixDPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_DCC_DAC_RANGE 2 0x902d 2 0 4294967295 CTRL 0 1 RESERVED_15_2 2 15 ixDPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_DCC_DAC_SEL 2 0x902e 6 0 4294967295 SEL 0 2 REQ 3 3 CTRL_UPD 4 4 RANGE_UPD 5 5 BIN_HOT 6 6 RESERVED_15_7 7 15 ixDPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_DCC_DAC_ACK 2 0x902f 2 0 4294967295 ACK 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_DCC_DAC_ADDR 2 0x9030 1 0 4294967295 ADDR 0 15 ixDPCSSYS_CR1_LANEX_DIG_TX_CLK_ALIGN_TX_CTL_0 2 0x9031 4 0 4294967295 TX_NUM_2UI_SHIFTS_16B_MODE 0 3 TX_NUM_2UI_SHIFTS_20B_MODE 4 7 TX_FIFO_BYPASS 8 8 RESERVED_15_9 9 15 ixDPCSSYS_CR1_LANEX_DIG_TX_LBERT_CTL 2 0x9032 4 0 4294967295 MODE 0 3 TRIGGER_ERR 4 4 PAT0 5 14 RESERVED_15_15 15 15 ixDPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0 2 0x9040 12 0 4294967295 RX_P0_ANA_AFE_EN 0 0 RX_P0_ANA_CLK_VREG_EN 1 1 RESERVED_1 2 2 RX_P0_ANA_CLK_EN 3 3 RESERVED_0 4 4 RX_P0_ANA_DESER_EN 5 5 RX_P0_ANA_CDR_EN 6 6 RX_P0_VCO_FREQ_RST 7 7 RX_P0_VCO_CAL_RST 8 8 RX_P0_VCO_CONTCAL_EN 9 9 RX_P0_DIG_CLK_EN 10 10 RESERVED_15_11 11 15 ixDPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S 2 0x9041 12 0 4294967295 RX_P0S_ANA_AFE_EN 0 0 RX_P0S_ANA_CLK_VREG_EN 1 1 RESERVED_2 2 2 RX_P0S_ANA_CLK_EN 3 3 RESERVED_4 4 4 RX_P0S_ANA_DESER_EN 5 5 RX_P0S_ANA_CDR_EN 6 6 RX_P0S_VCO_FREQ_RST 7 7 RX_P0S_VCO_CAL_RST 8 8 RX_P0S_VCO_CONTCAL_EN 9 9 RX_P0S_DIG_CLK_EN 10 10 RESERVED_15_11 11 15 ixDPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1 2 0x9042 12 0 4294967295 RX_P1_ANA_AFE_EN 0 0 RX_P1_ANA_CLK_VREG_EN 1 1 RESERVED_2 2 2 RX_P1_ANA_CLK_EN 3 3 RESERVED_4 4 4 RX_P1_ANA_DESER_EN 5 5 RX_P1_ANA_CDR_EN 6 6 RX_P1_VCO_FREQ_RST 7 7 RX_P1_VCO_CAL_RST 8 8 RX_P1_VCO_CONTCAL_EN 9 9 RX_P1_DIG_CLK_EN 10 10 RESERVED_15_11 11 15 ixDPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2 2 0x9043 12 0 4294967295 RX_P2_ANA_AFE_EN 0 0 RX_P2_ANA_CLK_VREG_EN 1 1 RESERVED_2 2 2 RX_P2_ANA_CLK_EN 3 3 RESERVED_4 4 4 RX_P2_ANA_DESER_EN 5 5 RX_P2_ANA_CDR_EN 6 6 RX_P2_VCO_FREQ_RST 7 7 RX_P2_VCO_CAL_RST 8 8 RX_P2_VCO_CONTCAL_EN 9 9 RX_P2_DIG_CLK_EN 10 10 RESERVED_15_11 11 15 ixDPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1 2 0x9045 5 0 4294967295 RX_AFE_EN_TIME 0 5 FAST_RX_AFE_EN 6 6 RX_VREG_EN_TIME 7 12 FAST_RX_VREG_EN 13 13 RESERVED_15_14 14 15 ixDPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_2 2 0x9046 4 0 4294967295 RX_CLK_EN_TIME 0 5 FAST_RX_CLK_EN 6 6 RX_FAST_START_TIME 7 10 RESERVED_15_11 11 15 ixDPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_3 2 0x9047 5 0 4294967295 RX_RATE_TIME 0 1 RSVD_3_7_2 2 7 RX_CDR_EN_TIME 8 11 RX_DESER_EN_TIME 12 13 RX_DESER_DIS_TIME 14 15 ixDPCSSYS_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0 2 0x9048 8 0 4294967295 INT_GAIN_CAL_FIXED_CNT 0 4 INT_GAIN_CAL_FIXED_CNT_EN 5 5 INT_GAIN_CAL_CNT_SHIFT 6 8 INT_GAIN_CAL_BOUNCE_CNT 9 11 DISABLE_BIN_HOLD 12 12 DISABLE_INT_GAIN_HOLD 13 13 DISABLE_COARSE_CALDONE 14 14 RESERVED_15_15 15 15 ixDPCSSYS_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1 2 0x9049 7 0 4294967295 RX_VCO_OVRD_SEL 0 0 RX_VCO_FREQ_RST 1 1 RX_VCO_CAL_RST 2 2 RX_VCO_CONTCAL_EN 3 3 DISABLE_INT_CAL_MODE 4 4 DPLL_CAL_UG 5 8 DTB_SEL 9 15 ixDPCSSYS_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2 2 0x904a 4 0 4294967295 FREQ_TUNE_START_VAL 0 9 FREQ_TUNE_CAL_STEPS 10 13 SKIP_RX_VCO_FREQ_TUNE_CAL 14 14 SKIP_RX_VCO_CAL 15 15 ixDPCSSYS_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0 2 0x904b 4 0 4294967295 RX_VCO_STARTUP_TIME 0 6 RX_VCO_UPDATE_TIME 7 10 RX_VCO_CNTR_PWRUP_TIME 11 14 FAST_RX_VCO_WAIT 15 15 ixDPCSSYS_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1 2 0x904c 2 0 4294967295 RX_VCO_CNTR_SETTLE_TIME 0 2 RESERVED_15_3 3 15 ixDPCSSYS_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0 2 0x904d 6 0 4294967295 RX_ANA_CDR_FREQ_TUNE 0 9 RX_ANA_VCO_CNTR_PD 10 10 RX_ANA_VCO_CNTR_EN 11 11 RX_ANA_CDR_STARTUP 12 12 RX_ANA_CDR_VCO_EN 13 13 RESERVED_15_14 14 15 ixDPCSSYS_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1 2 0x904e 7 0 4294967295 RX_VCO_FSM_STATE 0 3 RX_VCO_FREQ_RST 4 4 RX_VCO_CAL_RST 5 5 RX_VCO_CONTCAL_EN 6 6 RX_VCO_CAL_DONE 7 7 DPLL_FREQ_RST 8 8 RESERVED_15_9 9 15 ixDPCSSYS_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_2 2 0x904f 4 0 4294967295 VCO_CNTR_FINAL 0 12 VCOCLK_TOO_FAST 13 13 RX_VCO_CORRECT 14 14 RX_VCO_UP 15 15 ixDPCSSYS_CR1_LANEX_DIG_RX_RX_ALIGN_XAUI_COMM_MASK 2 0x9050 2 0 4294967295 XAUI_COMM_MASK 0 9 RESERVED_15_10 10 15 ixDPCSSYS_CR1_LANEX_DIG_RX_LBERT_CTL 2 0x9051 3 0 4294967295 MODE 0 3 SYNC 4 4 RESERVED_15_5 5 15 ixDPCSSYS_CR1_LANEX_DIG_RX_LBERT_ERR 2 0x9052 2 0 4294967295 COUNT 0 14 OV14 15 15 ixDPCSSYS_CR1_LANEX_DIG_RX_CDR_CDR_CTL_0 2 0x9053 7 0 4294967295 PHDET_EN 0 1 PHDET_EDGE 2 3 PHDET_POL 4 4 PHDET_EN_PR_MODE 5 5 ALWAYS_REALIGN 6 6 DTB_SEL 7 10 RESERVED_15_11 11 15 ixDPCSSYS_CR1_LANEX_DIG_RX_CDR_CDR_CTL_1 2 0x9054 2 0 4294967295 SSC_OFF_CNT0 0 9 SSC_OFF_CNT1 10 15 ixDPCSSYS_CR1_LANEX_DIG_RX_CDR_CDR_CTL_2 2 0x9055 2 0 4294967295 SSC_ON_CNT0 0 8 SSC_ON_CNT1 9 15 ixDPCSSYS_CR1_LANEX_DIG_RX_CDR_CDR_CTL_3 2 0x9056 6 0 4294967295 SSC_OFF_PHUG0 0 2 SSC_OFF_PHUG1 3 5 SSC_OFF_FRUG0 6 8 OVRD_DPLL_GAIN 9 9 PHUG_OVRD_VALUE 10 12 FRUG_OVRD_VALUE 13 15 ixDPCSSYS_CR1_LANEX_DIG_RX_CDR_CDR_CTL_4 2 0x9057 6 0 4294967295 SSC_OFF_FRUG1 0 2 SSC_ON_FRUG0 3 5 SSC_ON_FRUG1 6 8 SSC_ON_PHUG0 9 11 SSC_ON_PHUG1 12 14 RESERVED_15_15 15 15 ixDPCSSYS_CR1_LANEX_DIG_RX_CDR_STAT 2 0x9058 3 0 4294967295 PHUG_VALUE 0 2 FRUG_VALUE 3 5 RESERVED_15_6 6 15 ixDPCSSYS_CR1_LANEX_DIG_RX_DPLL_FREQ 2 0x9059 2 0 4294967295 VAL 0 13 RESERVED_15_14 14 15 ixDPCSSYS_CR1_LANEX_DIG_RX_DPLL_FREQ_BOUND_0 2 0x905a 3 0 4294967295 FREQ_BOUND_EN 0 0 UPPER_FREQ_BOUND 1 10 RESERVED_15_11 11 15 ixDPCSSYS_CR1_LANEX_DIG_RX_DPLL_FREQ_BOUND_1 2 0x905b 2 0 4294967295 LOWER_FREQ_BOUND 0 9 RESERVED_15_10 10 15 ixDPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_0 2 0x9060 4 0 4294967295 N_TOP_ASM1 0 9 N_TGG_ASM1 10 13 START_ASM1 14 14 ADPT_CLK_DIV4_EN 15 15 ixDPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1 2 0x9061 5 0 4294967295 N_WAIT_ASM1 0 6 FAST_AFE_DFE_SETTLE 7 7 CTLE_POLE_OVRD_VAL 8 10 CTLE_POLE_OVRD_EN 11 11 RESERVED_15_12 12 15 ixDPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_2 2 0x9062 3 0 4294967295 TGG_PTTRN_0 0 4 TGG_PTTRN_1 5 9 RESERVED_15_10 10 15 ixDPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3 2 0x9063 8 0 4294967295 CTLE_EN 0 4 VGA_EN 5 5 ATT_EN 6 6 DFE_EN 7 11 EYEHE_EN 12 12 EYEHO_EN 13 13 TGG_EN 14 14 ESL_TWICE_DSL 15 15 ixDPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_4 2 0x9064 4 0 4294967295 CTLE_TH 0 3 VGA_TH 4 7 DFE1_TH 8 11 DFE2_TH 12 15 ixDPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_5 2 0x9065 4 0 4294967295 DFE3_TH 0 3 DFE4_TH 4 7 DFE5_TH 8 11 TH_OFFSET 12 15 ixDPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6 2 0x9066 6 0 4294967295 CTLE_MU 0 2 VGA_MU 3 5 ATT_MU 6 8 VGA_SAT_CNT 9 11 VGA_SAT_CNT_STICKY 12 12 ATT_LOW_TH 13 15 ixDPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_7 2 0x9067 4 0 4294967295 VGA_MIN_SAT 0 4 VGA_LEV_HIGH 5 9 VGA_LEV_LOW 10 14 RESERVED_15_15 15 15 ixDPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8 2 0x9068 6 0 4294967295 DFE1_MU 0 2 DFE2_MU 3 5 DFE3_MU 6 8 DFE4_MU 9 11 DFE5_MU 12 14 RESERVED_15_15 15 15 ixDPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_9 2 0x9069 2 0 4294967295 ERR_SLE_ADPT_INIT 0 7 ERR_SLO_ADPT_INIT 8 15 ixDPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG 2 0x906a 6 0 4294967295 RST_ADPT_ATT 0 0 RST_ADPT_VGA 1 1 RST_ADPT_CTLE_BOOST 2 2 RST_ADPT_CTLE_POLE 3 3 RST_ADPT_TAP1 4 4 RESERVED_15_5 5 15 ixDPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ATT_STATUS 2 0x906b 3 0 4294967295 ATT_ADPT_CODE 0 7 ASM1_DON 8 8 RESERVED_15_9 9 15 ixDPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_VGA_STATUS 2 0x906c 3 0 4294967295 VGA_ADPT_CODE 0 9 ASM1_DONE 10 10 RESERVED_15_11 11 15 ixDPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_CTLE_STATUS 2 0x906d 4 0 4294967295 CTLE_BOOST_ADPT_CODE 0 9 CTLE_POLE_ADPT_CODE 10 12 ASM1_DONE 13 13 RESERVED_15_14 14 15 ixDPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_DFE_TAP1_STATUS 2 0x906e 3 0 4294967295 DFE_TAP1_ADPT_CODE 0 12 ASM1_DONE 13 13 RESERVED_15_14 14 15 ixDPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_DFE_TAP2_STATUS 2 0x906f 3 0 4294967295 DFE_TAP2_ADPT_CODE 0 11 ASM1_DONE 12 12 RESERVED_15_13 13 15 ixDPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_DFE_TAP3_STATUS 2 0x9070 3 0 4294967295 DFE_TAP3_ADPT_CODE 0 11 ASM1_DONE 12 12 RESERVED_15_13 13 15 ixDPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_DFE_TAP4_STATUS 2 0x9071 3 0 4294967295 DFE_TAP4_ADPT_CODE 0 11 ASM1_DONE 12 12 RESERVED_15_13 13 15 ixDPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_DFE_TAP5_STATUS 2 0x9072 3 0 4294967295 DFE_TAP5_ADPT_CODE 0 11 ASM1_DONE 12 12 RESERVED_15_13 13 15 ixDPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_DFE_DATA_EVEN_VDAC_OFST 2 0x9073 2 0 4294967295 DFE_DATA_EVEN_VDAC_OFST 0 7 RESERVED_15_8 8 15 ixDPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_DFE_DATA_ODD_VDAC_OFST 2 0x9074 2 0 4294967295 DFE_DATA_ODD_VDAC_OFST 0 7 RESERVED_15_8 8 15 ixDPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN 2 0x9075 2 0 4294967295 RX_ANA_SLICER_CTRL_E 0 3 RESERVED_15_4 4 15 ixDPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD 2 0x9076 2 0 4294967295 RX_ANA_SLICER_CTRL_O 0 3 RESERVED_15_4 4 15 ixDPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST 2 0x9077 2 0 4294967295 DFE_ERROR_EVEN_VDAC_OFST 0 7 RESERVED_15_8 8 15 ixDPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST 2 0x9078 2 0 4294967295 DFE_ERROR_ODD_VDAC_OFST 0 7 RESERVED_15_8 8 15 ixDPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL 2 0x9079 2 0 4294967295 E_SLO_LVL 0 7 E_SLE_LVL 8 15 ixDPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_RESET 2 0x907a 2 0 4294967295 RESET_ASM1 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1 2 0x907b 4 0 4294967295 DFE_T1_IDAC 0 4 DFE_T2_IDAC 5 9 DCC_START_IDAC 10 14 RESERVED_15_15 15 15 ixDPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2 2 0x907c 3 0 4294967295 DFE_DAT_EVEN_VDAC 0 4 DFE_DAT_ODD_VDAC 5 9 RESERVED_15_10 10 15 ixDPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3 2 0x907d 3 0 4294967295 DFE_ERR_EVEN_VDAC 0 4 DFE_ERR_ODD_VDAC 5 9 RESERVED_15_10 10 15 ixDPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_CR_BANK_ADDR 2 0x907e 1 0 4294967295 ADDR 0 15 ixDPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_CR_BANK_DATA 2 0x907f 1 0 4294967295 DATA 0 15 ixDPCSSYS_CR1_LANEX_DIG_RX_STAT_LD_VAL_1 2 0x9080 2 0 4294967295 SC1_LD_VAL 0 14 SC1_START 15 15 ixDPCSSYS_CR1_LANEX_DIG_RX_STAT_DATA_MSK 2 0x9081 1 0 4294967295 DATA_MSK_15_0 0 15 ixDPCSSYS_CR1_LANEX_DIG_RX_STAT_MATCH_CTL0 2 0x9082 4 0 4294967295 PTTRN_MSK_CR1A_4_0 0 4 PTTRN_CR1A_4_0 5 9 DATA_MSK_19_16 10 13 SCOPE_DLY 14 15 ixDPCSSYS_CR1_LANEX_DIG_RX_STAT_MATCH_CTL1 2 0x9083 5 0 4294967295 PTTRN_CR1B_EN 0 0 PTTRN_MSK_CR1B_4_0 1 5 PTTRN_CR1B_4_0 6 10 PTTRN_CR1A_ADPT_EN 11 11 RESERVED_15_12 12 15 ixDPCSSYS_CR1_LANEX_DIG_RX_STAT_STAT_CTL0 2 0x9084 10 0 4294967295 RESERVED_0 0 0 CORR_SHFT_SEL_VGA 1 1 CORR_SHFT_SEL 2 2 CORR_SRC_SEL 3 4 CORR_MODE_EN 5 5 STAT_SHFT_SEL 6 9 STAT_SRC_SEL 10 12 STAT_RXCLK_SEL 13 13 SC_TIMER_MODE 14 14 SKIP_EN 15 15 ixDPCSSYS_CR1_LANEX_DIG_RX_STAT_STAT_CTL1 2 0x9085 13 0 4294967295 STAT_CNT_0_EN 0 0 STAT_CNT_1_EN 1 1 STAT_CNT_2_EN 2 2 STAT_CNT_3_EN 3 3 STAT_CNT_4_EN 4 4 STAT_CNT_5_EN 5 5 STAT_CNT_6_EN 6 6 RESERVED_8_7 7 8 SC_PAUSE 9 9 STAT_CLK_EN 10 10 DATA_DLY_SEL 11 12 VLD_LOSS_CLR 13 13 VLD_CTL 14 15 ixDPCSSYS_CR1_LANEX_DIG_RX_STAT_SMPL_CNT1 2 0x9086 2 0 4294967295 SMPL_CNT1 0 14 SMPL_CNT1_DONE 15 15 ixDPCSSYS_CR1_LANEX_DIG_RX_STAT_STAT_CNT_0 2 0x9087 2 0 4294967295 STAT_CNT_0 0 14 SMPL_CNT1_DONE 15 15 ixDPCSSYS_CR1_LANEX_DIG_RX_STAT_STAT_CNT_1 2 0x9088 2 0 4294967295 STAT_CNT_1 0 14 SMPL_CNT1_DONE 15 15 ixDPCSSYS_CR1_LANEX_DIG_RX_STAT_STAT_CNT_2 2 0x9089 2 0 4294967295 STAT_CNT_2 0 14 SMPL_CNT1_DONE 15 15 ixDPCSSYS_CR1_LANEX_DIG_RX_STAT_STAT_CNT_3 2 0x908a 2 0 4294967295 STAT_CNT_3 0 14 SMPL_CNT1_DONE 15 15 ixDPCSSYS_CR1_LANEX_DIG_RX_STAT_STAT_CNT_4 2 0x908b 2 0 4294967295 STAT_CNT_4 0 14 SMPL_CNT1_DONE 15 15 ixDPCSSYS_CR1_LANEX_DIG_RX_STAT_STAT_CNT_5 2 0x908c 2 0 4294967295 STAT_CNT_5 0 14 SMPL_CNT1_DONE 15 15 ixDPCSSYS_CR1_LANEX_DIG_RX_STAT_STAT_CNT_6 2 0x908d 2 0 4294967295 STAT_CNT_6 0 14 SMPL_CNT1_DONE 15 15 ixDPCSSYS_CR1_LANEX_DIG_RX_STAT_CAL_COMP_CLK_CTL 2 0x908e 3 0 4294967295 PRECHRGE_CNT 0 2 REF_DIV_CNT 3 5 RESERVED_15_6 6 15 ixDPCSSYS_CR1_LANEX_DIG_RX_STAT_MATCH_CTL2 2 0x908f 2 0 4294967295 PTTRN_CR1A_19_5 0 14 RESERVED_15_15 15 15 ixDPCSSYS_CR1_LANEX_DIG_RX_STAT_MATCH_CTL3 2 0x9090 2 0 4294967295 PTTRN_MSK_CR1A_19_5 0 14 RESERVED_15_15 15 15 ixDPCSSYS_CR1_LANEX_DIG_RX_STAT_MATCH_CTL4 2 0x9091 2 0 4294967295 PTTRN_CR1B_19_5 0 14 RESERVED_15_15 15 15 ixDPCSSYS_CR1_LANEX_DIG_RX_STAT_MATCH_CTL5 2 0x9092 2 0 4294967295 PTTRN_MSK_CR1B_19_5 0 14 RESERVED_15_15 15 15 ixDPCSSYS_CR1_LANEX_DIG_RX_STAT_STAT_CTL2 2 0x9093 4 0 4294967295 DATA_DLY_SEL_2 0 0 SCOPE_DLY_2 1 1 DISABLE_SAMPLE_COUNT 2 2 RESERVED_15_3 3 15 ixDPCSSYS_CR1_LANEX_DIG_RX_STAT_STAT_STOP 2 0x9094 2 0 4294967295 SC1_STOP 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR1_LANEX_DIG_MPHY_RX_PWM_CTL 2 0x9095 3 0 4294967295 RX_PWM_POL 0 0 RX_PWM_DATA_POL 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR1_LANEX_DIG_MPHY_RX_TERM_LS_CTL 2 0x9096 2 0 4294967295 RX_TERM_LCC_CNT 0 2 RESERVED_15_3 3 15 ixDPCSSYS_CR1_LANEX_DIG_MPHY_RX_ANA_PWM_CLK_STABLE_CNT 2 0x9097 2 0 4294967295 PWM_CLK_STABLE_CNT 0 3 RESERVED_15_4 4 15 ixDPCSSYS_CR1_LANEX_DIG_ANA_TX_OVRD_OUT 2 0x90a0 15 0 4294967295 TX_ANA_CLK_SHIFT 0 0 TX_ANA_DATA_EN 1 1 TX_ANA_REFGEN_EN 2 2 TX_ANA_VCM_HOLD 3 3 TX_ANA_CLK_EN 4 4 TX_ANA_WORD_CLK_EN 5 5 TX_ANA_MPLLA_CLK_EN 6 6 TX_ANA_MPLLB_CLK_EN 7 7 TX_ANA_RESET 8 8 TX_ANA_SERIAL_EN 9 9 TX_ANA_DATA_RATE 10 11 RESERVED 12 12 TX_DIV4_EN 13 13 TX_RXDET_EN 14 14 TX_OVRD_EN 15 15 ixDPCSSYS_CR1_LANEX_DIG_ANA_TX_TERM_CODE_OVRD_OUT 2 0x90a1 5 0 4294967295 TX_TERM_CODE 0 9 TX_TERM_OVRD_EN 10 10 TX_DRV_SRC 11 12 TX_DRV_SRC_OVRD_EN 13 13 RESERVED_15_14 14 15 ixDPCSSYS_CR1_LANEX_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT 2 0x90a2 3 0 4294967295 TX_TERM_DN_CLK 0 0 TX_TERM_CLK_SELF_CLEAR_DISABLE 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR1_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_0 2 0x90a3 3 0 4294967295 TX_ANA_LOAD_CLK 0 0 TX_ANA_CTRL_LEG_PULL_EN_13_0 1 14 TX_EQ_OVRD_EN 15 15 ixDPCSSYS_CR1_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_1 2 0x90a4 2 0 4294967295 TX_ANA_CTRL_LEG_PULL_EN_19_14 0 5 RESERVED_15_6 6 15 ixDPCSSYS_CR1_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_2 2 0x90a5 4 0 4294967295 RESERVED 0 2 TX_ANA_CTRL_EQ_MUX_SEL 3 6 TX_ANA_CTRL_PRE 7 12 RESERVED_15_13 13 15 ixDPCSSYS_CR1_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_3 2 0x90a6 2 0 4294967295 TX_ANA_CTRL_POST 0 8 RESERVED_15_9 9 15 ixDPCSSYS_CR1_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_4 2 0x90a7 1 0 4294967295 TX_ANA_CTRL_LEG_PULL_DIR_19_4 0 15 ixDPCSSYS_CR1_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_5 2 0x90a8 2 0 4294967295 TX_ANA_CTRL_LEG_PULL_DIR_3_0 0 3 RESERVED_15_4 4 15 ixDPCSSYS_CR1_LANEX_DIG_ANA_RX_CTL_OVRD_OUT 2 0x90a9 9 0 4294967295 RESERVED 0 0 RX_ANA_DATA_RATE 1 2 RX_ANA_WORD_CLK_EN 3 3 RX_ANA_DIV4_EN 4 4 RX_ANA_DFE_TAPS_EN 5 5 RX_ANA_ADAPTATION_EN 6 6 RX_LBK_CLK_EN 7 7 RX_CTL_OVRD_EN 8 8 RESERVED_15_9 9 15 ixDPCSSYS_CR1_LANEX_DIG_ANA_RX_PWR_OVRD_OUT 2 0x90aa 9 0 4294967295 RX_ANA_AFE_EN 0 0 RX_ANA_CLK_VREG_EN 1 1 RX_ANA_CLK_DCC_EN 2 2 RX_ANA_CLK_EN 3 3 RX_ANA_CDR_EN 4 4 RX_ANA_DESERIAL_EN 5 5 RX_PWR_OVRD_EN 6 6 RX_ANA_FAST_START 7 7 RESERVED_15_8 8 15 ixDPCSSYS_CR1_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0 2 0x90ab 7 0 4294967295 RX_ANA_CDR_VCO_EN 0 0 RX_ANA_CDR_STARTUP 1 1 RX_VCO_CDR_OVRD_EN 2 2 RX_ANA_CDR_FREQ_TUNE 3 12 RX_ANA_VCO_CNTR_EN 13 13 RX_ANA_VCO_CNTR_CLK 14 14 RX_CDR_FREQ_TUNE_OVRD_EN 15 15 ixDPCSSYS_CR1_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_1 2 0x90ac 3 0 4294967295 RX_ANA_CDR_VCO_LOWFREQ 0 0 RX_ANA_VCO_CNTR_PD 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR1_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_2 2 0x90ad 3 0 4294967295 RX_ANA_CDR_FREQ_TUNE_CLK 0 0 CDR_FREQ_TUNE_CLK_SELF_CLEAR_DISABLE 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR1_LANEX_DIG_ANA_RX_CAL 2 0x90ae 7 0 4294967295 RX_ANA_CAL_MUXA_SEL 0 4 RX_ANA_CAL_MUXB_SEL 5 9 RX_ANA_CAL_LPFBYP_EN 10 10 RESERVED 11 11 RX_ANA_SLICER_CAL_EN 12 12 RX_ANA_CAL_MODE 13 14 RX_ANA_CAL_COMP_EN 15 15 ixDPCSSYS_CR1_LANEX_DIG_ANA_RX_DAC_CTRL 2 0x90af 2 0 4294967295 RX_ANA_CAL_DAC_CTRL 0 7 RESERVED_15_8 8 15 ixDPCSSYS_CR1_LANEX_DIG_ANA_RX_DAC_CTRL_OVRD 2 0x90b0 2 0 4294967295 RX_CAL_DAC_CTRL_OVRD 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR1_LANEX_DIG_ANA_RX_DAC_CTRL_SEL 2 0x90b1 2 0 4294967295 RX_ANA_CAL_DAC_CTRL_SEL 0 4 RESERVED_15_5 5 15 ixDPCSSYS_CR1_LANEX_DIG_ANA_RX_AFE_ATT_VGA 2 0x90b2 5 0 4294967295 RX_ANA_AFE_ATT_LVL 0 2 RX_ANA_AFE_GAIN 3 6 RESERVED 7 10 RX_AFE_OVRD_EN 11 11 RESERVED_15_12 12 15 ixDPCSSYS_CR1_LANEX_DIG_ANA_RX_AFE_CTLE 2 0x90b3 3 0 4294967295 RESERVED 0 2 RX_ANA_AFE_CTLE_BOOST 3 7 RESERVED_15_8 8 15 ixDPCSSYS_CR1_LANEX_DIG_ANA_RX_SCOPE 2 0x90b4 7 0 4294967295 RX_ANA_SCOPE_EN 0 0 RX_ANA_SCOPE_SEL 1 2 RX_ANA_SCOPE_PH_CLK 3 3 RX_ANA_SCOPE_PHASE 4 11 RX_ANA_SCOPE_CLK_EN 12 12 RX_SCOPE_SELF_CLEAR_DISABLE 13 13 RESERVED_15_14 14 15 ixDPCSSYS_CR1_LANEX_DIG_ANA_RX_SLICER_CTRL 2 0x90b5 4 0 4294967295 RX_ANA_SLICER_CTRL_E 0 3 RX_ANA_SLICER_CTRL_O 4 7 RX_ANA_SLICER_CTRL_OVRD_EN 8 8 RESERVED_15_9 9 15 ixDPCSSYS_CR1_LANEX_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST 2 0x90b6 2 0 4294967295 RX_ANA_IQ_PHASE_ADJUST 0 6 RESERVED_15_7 7 15 ixDPCSSYS_CR1_LANEX_DIG_ANA_RX_ANA_IQ_SENSE_EN 2 0x90b7 2 0 4294967295 RX_ANA_IQ_SENSE_EN 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR1_LANEX_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN 2 0x90b8 3 0 4294967295 RX_ANA_CAL_DAC_CTRL_EN 0 0 DAC_CTRL_SELF_CLEAR_DISABLE 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR1_LANEX_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE 2 0x90b9 3 0 4294967295 RX_ANA_AFE_UPDATE_EN 0 0 AFE_UPDATE_SELF_CLEAR_DISABLE 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR1_LANEX_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK 2 0x90ba 3 0 4294967295 RX_ANA_IQ_PHASE_ADJUST_CLK 0 0 PHASE_ADJUST_SELF_CLEAR_DISABLE 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR1_LANEX_DIG_ANA_STATUS_0 2 0x90bb 9 0 4294967295 TX_ANA_CLK_SHIFT_ACK 0 0 TX_ANA_RXDETP_RESULT 1 1 TX_ANA_RXDETM_RESULT 2 2 TX_ANA_LOOPBACK_EN 3 3 TX_ANA_CLK_LB_EN 4 4 RX_ANA_CAL_RESULT 5 5 RX_ANA_SCOPE_DATA 6 6 TX_ANA_DCC_CAL_RESULT 7 7 TX_ANA_CTRL_EQ_MUX 8 15 ixDPCSSYS_CR1_LANEX_DIG_ANA_STATUS_1 2 0x90bc 2 0 4294967295 RX_ANA_VCO_CNTR 0 12 RESERVED_15_13 13 15 ixDPCSSYS_CR1_LANEX_DIG_ANA_RX_TERM_CODE_OVRD_OUT 2 0x90bd 3 0 4294967295 RX_TERM_CODE 0 5 RX_TERM_OVRD_EN 6 6 RESERVED_15_7 7 15 ixDPCSSYS_CR1_LANEX_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT 2 0x90be 3 0 4294967295 RX_TERM_CLK 0 0 RX_TERM_CLK_SELF_CLEAR_DISABLE 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR1_LANEX_DIG_ANA_MPHY_OVRD_OUT 2 0x90bf 9 0 4294967295 RX_ANA_SQ_CTRL_TRESH 0 2 RX_ANA_SQ_CTRL_TRESH_OVRD_EN 3 3 RX_ANA_SQ_CTRL_RESP 4 5 RX_ANA_SQ_CTRL_RESP_OVRD_EN 6 6 RX_ANA_PWM_EN 7 7 RX_ANA_PWM_EN_OVRD_EN 8 8 RX_ANA_PWM_CLK_SEL 9 10 RX_ANA_PWM_CLK_SEL_OVRD_EN 11 11 RESERVED_15_12 12 15 ixDPCSSYS_CR1_LANEX_DIG_ANA_SIGDET_OVRD_OUT_1 2 0x90c0 7 0 4294967295 RX_ANA_SIGDET_HF_THRESH 0 2 RX_ANA_SIGDET_HF_THRESH_OVRD_EN 3 3 RX_ANA_SIGDET_HF_CAL_TUNE 4 9 RX_ANA_SIGDET_CAL_TUNE_OVRD_EN 10 10 RX_ANA_SIGDET_CAL_EN 11 11 RX_ANA_SIGDET_CAL_EN_OVRD_EN 12 12 RESERVED_15_13 13 15 ixDPCSSYS_CR1_LANEX_DIG_ANA_SIGDET_OVRD_OUT_2 2 0x90c1 7 0 4294967295 RX_ANA_SIGDET_LF_THRESH 0 2 RX_ANA_SIGDET_LF_THRESH_OVRD_EN 3 3 RX_ANA_SIGDET_LF_FILTER_EN 4 4 RX_ANA_SIGDET_LF_FILTER_EN_OVRD_EN 5 5 RX_ANA_SIGDET_CAL_TUNE 6 11 RX_ANA_SIGDET_CAL_TUNE_OVRD_EN 12 12 RESERVED_15_13 13 15 ixDPCSSYS_CR1_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT 2 0x90c2 8 0 4294967295 TX_ANA_DCC_CAL_RANGE 0 1 TX_ANA_DCC_CAL_RANGE_OVRD_EN 2 2 TX_ANA_DCC_CAL_COMP_EN 3 3 TX_ANA_DCC_CAL_COMP_EN_OVRD_EN 4 4 TX_ANA_DCC_CAL_CTRL 5 12 TX_ANA_DCC_CAL_CTRL_OVRD_EN 13 13 TX_ANA_DCC_CAL_CTRL_EN 14 14 TX_ANA_DCC_CAL_CTRL_EN_OVRD_EN 15 15 ixDPCSSYS_CR1_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2 2 0x90c3 5 0 4294967295 TX_ANA_DCC_CAL_CTRL_SEL 0 2 TX_ANA_DCC_CAL_CTRL_SEL_OVRD_EN 3 3 TX_ANA_DCC_CLK_COMP 4 4 TX_ANA_DCC_CLK_COMP_OVRD_EN 5 5 RESERVED_15_6 6 15 ixDPCSSYS_CR1_LANEX_DIG_ANA_TX_OVRD_OUT_2 2 0x90c4 6 0 4294967295 TX_ANA_FAST_START 0 0 TX_ANA_FAST_START_OVRD_EN 1 1 TX_CLK_LB_EN 2 2 TX_CLK_LB_EN_OVRD_EN 3 3 TX_ACJTAG_EN 4 4 RESERVED_15_5 5 15 ixDPCSSYS_CR1_LANEX_ANA_TX_OVRD_MEAS 2 0x90e0 9 0 4294967295 OVRD_CLK_SHIFT 0 0 CLK_SHIFT_REG 0 0 MEAS_ATB_CAL_MUX 0 0 MEAS_ATB_CAL_COMP 0 0 OVRD_VCM_HOLD 0 0 VCM_HOLD_REG 0 0 PULL_UP_REG 0 0 PULL_DN_REG 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR1_LANEX_ANA_TX_PWR_OVRD 2 0x90e1 9 0 4294967295 OVRD_TX_LOOPBACK 0 0 LOOPBACK_EN_REG 0 0 REFGEN_EN_REG 0 0 CLK_DIV_EN_REG 0 0 DATA_EN_REG_INT 0 0 CLK_EN_REG 0 0 SERIAL_EN_REG 0 0 OVRD_EN 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR1_LANEX_ANA_TX_ALT_BUS 2 0x90e2 6 0 4294967295 DRV_SOURCE_REG 0 0 OVRD_ALT_BUS 0 0 ATB_S_ENABLE 0 0 TX_ALT_RINGO 0 0 JTAG_DATA_REG 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR1_LANEX_ANA_TX_ATB1 2 0x90e3 9 0 4294967295 MEAS_ATB_GD 0 0 MEAS_ATB_VDDH 0 0 OVERRIDE_RXDETREF 0 0 MEAS_ATB_VPTX 0 0 OVERRIDE_REGREF 0 0 MEAS_ATB_VREG_DRV 0 0 MEAS_ATB_VREG 0 0 MEAS_ATB_VPH_HALF 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR1_LANEX_ANA_TX_ATB2 2 0x90e4 9 0 4294967295 MEAS_ATB_VCM 0 0 MEAS_ATB_CAL_VDAC_CM 0 0 MEAS_ATB_CAL_VDAC_DIFF 0 0 MEAS_ATB_TXM 0 0 MEAS_ATB_TXP 0 0 MEAS_ATB_RXDETREF 0 0 LFPS_HIGH_PRIORITY 0 0 OSC_DIV4_EN 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR1_LANEX_ANA_TX_DCC_DAC 2 0x90e5 2 0 4294967295 DCC_DAC_REG 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR1_LANEX_ANA_TX_DCC_CTRL1 2 0x90e6 7 0 4294967295 NC0 0 0 OVRD_DCC_DAC_CTRL_SEL 0 0 DCC_DAC_CTRL_SEL_REG 0 0 OVRD_DCC_DAC_CTRL_EN 0 0 DCC_DAC_CTRL_EN_REG 0 0 OVRD_DCC_DAC_REG 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR1_LANEX_ANA_TX_TERM_CODE 2 0x90e7 2 0 4294967295 TERM_CODE_REG_70 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR1_LANEX_ANA_TX_TERM_CODE_CTRL 2 0x90e8 8 0 4294967295 VREG_BOOST_1 0 0 OVRD_UPDATE_TERM 0 0 UPDATE_TERM_REG 0 0 OVRD_RESET_TERM 0 0 RESET_TERM_REG 0 0 OVRD_TERM_CODE 0 0 TERM_CODE_REG_98 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR1_LANEX_ANA_TX_OVRD_CLK 2 0x90e9 9 0 4294967295 VREG_BOOST_0 0 0 CLK_LB_EN_REG 0 0 OVRD_LB_EN 0 0 MPLLB_CLK_EN_REG 0 0 MPLLA_CLK_EN_REG 0 0 OVRD_MPLLAB_EN 0 0 WORD_CLK_EN_REG 0 0 OVRD_WORD_CLK_EN 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR1_LANEX_ANA_TX_MISC1 2 0x90ea 8 0 4294967295 MEAS_ATB_CAL_CLK_ALIGN 0 0 OVRD_DCC_DAC_CTRL_RANGE 0 0 DCC_DAC_CTRL_RANGE_REG 0 0 OVRD_VREF_SEL 0 0 VREF_SEL_REG 0 0 FORCE_ATB_TXM 0 0 FORCE_ATB_TXP 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR1_LANEX_ANA_TX_MISC2 2 0x90eb 8 0 4294967295 TX_PEAKING_LVL 0 0 VREG_CP_GAIN_CTRL 0 0 TX_SLEW_EN 0 0 EN_INV_POST 0 0 EN_INV_PRE 0 0 TX_VREG_EN_BYP 0 0 TX_VDRIVER_PULLDN_EN 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR1_LANEX_ANA_TX_MISC3 2 0x90ec 4 0 4294967295 TX_VREG_OVRD_RING_CTRL 0 0 TX_DCC_LOWV 0 0 NC7_2 2 7 RESERVED_15_8 8 15 ixDPCSSYS_CR1_LANEX_ANA_TX_RESERVED2 2 0x90ed 2 0 4294967295 NC7_0 0 7 RESERVED_15_8 8 15 ixDPCSSYS_CR1_LANEX_ANA_TX_RESERVED3 2 0x90ee 2 0 4294967295 NC7_0 0 7 RESERVED_15_8 8 15 ixDPCSSYS_CR1_LANEX_ANA_TX_RESERVED4 2 0x90ef 2 0 4294967295 NC7_0 0 7 RESERVED_15_8 8 15 ixDPCSSYS_CR1_LANEX_ANA_RX_CLK_1 2 0x90f0 8 0 4294967295 CDR_VCO_STARTUP_CODE 0 0 CDR_VCO_TEMP_COMP_EN 0 0 CDR_VCO_USE_UNCAL_BIAS 0 0 OVERRIDE_CDR_EN 0 0 OVRD_CLK_EN 0 0 CLK_EN_REG 0 0 NC7 7 7 RESERVED_15_8 8 15 ixDPCSSYS_CR1_LANEX_ANA_RX_CLK_2 2 0x90f1 5 0 4294967295 IQ_PHASE_ADJUST_REG 0 0 OVRD_IQ_PHASE_ADJUST 0 0 RX_LOOPBACK_CLK_REG 0 0 OVRD_RX_LOOPBACK_CLK 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR1_LANEX_ANA_RX_CDR_DES 2 0x90f2 7 0 4294967295 OVRD_WORD_CLK_EN 0 0 WORD_CLK_EN_REG 0 0 PHDET_ODD_REG 0 0 PHDET_EVEN_REG 0 0 SIGDET_VREF_EXT_EN 0 0 NC7_5 5 7 RESERVED_15_8 8 15 ixDPCSSYS_CR1_LANEX_ANA_RX_SLC_CTRL 2 0x90f3 3 0 4294967295 RX_SLICER_CTRL_O_REG 0 0 RX_SLICER_CTRL_E_REG 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR1_LANEX_ANA_RX_PWR_CTRL1 2 0x90f4 8 0 4294967295 OVRD_ACJT_EN 0 0 ACJT_EN_REG 0 0 OVRD_AFE_EN 0 0 AFE_EN_REG 0 0 AFE_CM_SEL 0 0 ATT_PULLDN_EN 0 0 NC7_7 7 7 RESERVED_15_8 8 15 ixDPCSSYS_CR1_LANEX_ANA_RX_PWR_CTRL2 2 0x90f5 9 0 4294967295 OVRD_DFE_EN 0 0 DFE_EN_REG 0 0 OVRD_DESERIAL_EN 0 0 DESERIAL_EN_REG 0 0 OVRD_LOOPBACK_EN 0 0 LOOPBACK_EN_REG 0 0 OVRD_FAST_START 0 0 FAST_START_REG 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR1_LANEX_ANA_RX_SQ 2 0x90f6 7 0 4294967295 SQ_CTRL_RESP_REG 0 0 OVRD_SQ_CTRL_RESP 0 0 NC4_3 3 4 SQ_CTRL_TRESH_REG 0 0 OVRD_SQ_CTRL_TRESH 0 0 AFE_LOOPBACK_SEL 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR1_LANEX_ANA_RX_CAL1 2 0x90f7 5 0 4294967295 DFE_TAPS_EN_REG 0 0 OVRD_DFE_TAPS_EN 0 0 CAL_MUXB_SEL_REG 0 0 OVRD_CAL_MUXB_SEL 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR1_LANEX_ANA_RX_CAL2 2 0x90f8 5 0 4294967295 AFE_PD_EQ_OFFSET 0 0 CAL_IDACS_USE_UNCAL 0 0 CAL_MUXA_SEL_REG 0 0 OVRD_CAL_MUXA_SEL 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR1_LANEX_ANA_RX_ATB_REGREF 2 0x90f9 8 0 4294967295 OVERRIDE_REGREF_VCO 0 0 OVERRIDE_REGREF_CLK 0 0 OVERRIDE_REGREF_IQC 0 0 BOOST_REGREF_IQC 0 0 OVRD_RX_SLICER_CTRL 0 0 OVRD_RX_TERM_AC_DCZ 0 0 RX_TERM_AC_DCZ_REG 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR1_LANEX_ANA_RX_ATB_MEAS1 2 0x90fa 9 0 4294967295 MASTER_ATB_EN 0 0 MEAS_ATB_VP 0 0 MEAS_ATB_GD 0 0 MEAS_ATB_VREG_VCO 0 0 MEAS_ATB_VREG_CLK 0 0 MEAS_ATB_VREG_IQC 0 0 REGS_FB_DIV_CTRL 0 0 RX_VREG_CLK_BYPASS 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR1_LANEX_ANA_RX_ATB_MEAS2 2 0x90fb 2 0 4294967295 MEAS_ATB_RX 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR1_LANEX_ANA_RX_ATB_MEAS3 2 0x90fc 7 0 4294967295 MEAS_ATB_CDR_VCO_GD 0 0 MEAS_ATB_CDR_VCO_VIREF_200U 0 0 MEAS_ATB_VIBIAS_CDR_VCO 0 0 MEAS_ATB_CDR_VCO_VOSC 0 0 MEAS_ATB_CAL_MUX 0 0 RX_VREG_OVERRIDE_RING_CTRL 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR1_LANEX_ANA_RX_ATB_MEAS4 2 0x90fd 3 0 4294967295 MEAS_ATB_CAL_VREF 0 0 NC7 7 7 RESERVED_15_8 8 15 ixDPCSSYS_CR1_LANEX_ANA_RX_ATB_FRC 2 0x90fe 2 0 4294967295 FRC_ATB_CAL_VREF 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR1_LANEX_ANA_RX_RESERVED1 2 0x90ff 2 0 4294967295 NC7_0 0 7 RESERVED_15_8 8 15 ixDPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN 2 0xe000 12 0 4294967295 PSTATE 0 1 LPD 2 2 WIDTH 3 4 RATE 5 7 MPLLB_SEL 8 8 MPLL_EN 9 9 OVRD_EN 10 10 MSTR_MPLLA_STATE 11 11 MSTR_MPLLB_STATE 12 12 MSTR_MPLL_OVRD_EN 13 13 TX_ASYNC_EN_OVR_VAL 14 14 TX_ASYNC_EN_OVR_EN 15 15 ixDPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1 2 0xe001 13 0 4294967295 RESET_OVRD_VAL 0 0 RESET_OVRD_EN 1 1 REQ_OVRD_VAL 2 2 REQ_OVRD_EN 3 3 DETRX_REQ_OVRD_VAL 4 4 DETRX_REQ_OVRD_EN 5 5 VBOOST_EN_OVRD_VAL 6 6 VBOOST_EN_OVRD_EN 7 7 IBOOST_LVL_OVRD_VAL 8 11 IBOOST_LVL_OVRD_EN 12 12 TX_BEACON_EN_OVR_VAL 13 13 TX_BEACON_EN_OVR_EN 14 14 RESERVED_15_15 15 15 ixDPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_PCS_IN 2 0xe002 12 0 4294967295 RESET 0 0 REQ 1 1 PSTATE 2 3 LPD 4 4 WIDTH 5 6 RATE 7 9 MPLLB_SEL 10 10 MPLL_EN 11 11 MSTR_MPLLA_STATE 12 12 MSTR_MPLLB_STATE 13 13 DETRX_REQ 14 14 RESERVED_15_15 15 15 ixDPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_OVRD_OUT 2 0xe003 6 0 4294967295 ACK 0 0 DETRX_RESULT 1 1 EN_CTL 2 2 TX_DWORD_CLK_SYNC_OVRD_VAL 3 3 TX_DWORD_CLK_SYNC_OVRD_EN 4 4 RESERVED_15_5 5 15 ixDPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_PCS_OUT 2 0xe004 2 0 4294967295 ACK 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN 2 0xe005 12 0 4294967295 RATE 0 1 WIDTH 2 3 PSTATE 4 5 LPD 6 6 OVRD_EN 7 7 ADAPT_AFE_EN 8 8 ADAPT_DFE_EN 9 9 LANE_RX2TX_PAR_LB_EN_OVRD_VAL 10 10 LANE_RX2TX_PAR_LB_EN_OVRD_EN 11 11 RX_DATA_EN_OVRD_VAL_R 12 12 RX_DATA_EN_OVRD_EN_R 13 13 RESERVED_15_14 14 15 ixDPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1 2 0xe006 12 0 4294967295 RESET_OVRD_VAL 0 0 RESET_OVRD_EN 1 1 REQ_OVRD_VAL 2 2 REQ_OVRD_EN 3 3 RX_LOS_THRSHLD_OVRD_VAL 4 6 RX_LOS_THRSHLD_OVRD_EN 7 7 ADAPT_REQ 8 8 ADAPT_REQ_OVRD_EN 9 9 ADAPT_CONT 10 10 OFFCAN_CONT 11 11 CONT_OVRD_EN 12 12 RESERVED_15_13 13 15 ixDPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_2 2 0xe007 4 0 4294967295 VCO_LD_VAL_OVRD 0 12 VCO_LD_VAL_OVRD_EN 13 13 VCO_LOWFREQ_VAL_OVRD 14 14 VCO_LOWFREQ_VAL_OVRD_EN 15 15 ixDPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_3 2 0xe008 3 0 4294967295 REF_LD_VAL_OVRD 0 6 REF_LD_VAL_OVRD_EN 7 7 RESERVED_15_8 8 15 ixDPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_PCS_IN 2 0xe009 13 0 4294967295 REQ 0 0 RATE 1 2 WIDTH 3 4 PSTATE 5 6 LPD 7 7 CDR_VCO_LOWFREQ 8 8 ADAPT_AFE_EN 9 9 ADAPT_DFE_EN 10 10 ADAPT_REQ 11 11 ADAPT_CONT 12 12 OFFCAN_CONT 13 13 RESET 14 14 RESERVED_15_15 15 15 ixDPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_1 2 0xe00a 2 0 4294967295 REF_LD_VAL 0 6 RESERVED_15_7 7 15 ixDPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_2 2 0xe00b 2 0 4294967295 VCO_LD_VAL 0 12 RESERVED_15_13 13 15 ixDPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_3 2 0xe00c 4 0 4294967295 EQ_ATT_LVL 0 2 EQ_VGA1_GAIN 3 6 EQ_VGA2_GAIN 7 10 EQ_CTLE_BOOST 11 15 ixDPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_4 2 0xe00d 3 0 4294967295 EQ_CTLE_POLE 0 2 EQ_DFE_TAP1 3 10 RESERVED_15_11 11 15 ixDPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT 2 0xe00e 3 0 4294967295 ACK 0 0 EN_CTL 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_PCS_OUT 2 0xe00f 2 0 4294967295 ACK 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_ADAPT_ACK 2 0xe010 2 0 4294967295 RX_ADAPT_ACK 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_ADAPT_FOM 2 0xe011 2 0 4294967295 RX_ADAPT_FOM 0 7 RESERVED_15_8 8 15 ixDPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_TXPRE_DIR 2 0xe012 2 0 4294967295 RX_TXPRE_DIR 0 1 RESERVED_15_2 2 15 ixDPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_TXMAIN_DIR 2 0xe013 2 0 4294967295 RX_TXMAIN_DIR 0 1 RESERVED_15_2 2 15 ixDPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_TXPOST_DIR 2 0xe014 2 0 4294967295 RX_TXPOST_DIR 0 1 RESERVED_15_2 2 15 ixDPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_LANE_NUMBER 2 0xe015 2 0 4294967295 LANE_NUMBER 0 3 RESERVED_15_4 4 15 ixDPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RESERVED_1 2 0xe016 1 0 4294967295 RESERVED_REG_1 0 15 ixDPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RESERVED_2 2 0xe017 1 0 4294967295 RESERVED_REG_2 0 15 ixDPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN 2 0xe018 16 0 4294967295 RX_RESET_ATE_OVRD_VAL 0 0 RX_RESET_ATE_OVRD_EN 1 1 TX_RESET_ATE_OVRD_VAL 2 2 TX_RESET_ATE_OVRD_EN 3 3 RX_REQ_ATE_OVRD_VAL 4 4 RX_REQ_ATE_OVRD_EN 5 5 TX_REQ_ATE_OVRD_VAL 6 6 TX_REQ_ATE_OVRD_EN 7 7 RX_ADAPT_AFE_EN_OVRD_VAL 8 8 RX_ADAPT_AFE_EN_OVRD_EN 9 9 RX_ADAPT_DFE_EN_OVRD_VAL 10 10 RX_ADAPT_DFE_EN_OVRD_EN 11 11 TX_DATA_EN_ATE_OVRD_VAL 12 12 TX_DATA_EN_ATE_OVRD_EN 13 13 RX_DATA_EN_ATE_OVRD_VAL 14 14 RX_DATA_EN_ATE_OVRD_EN 15 15 ixDPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN 2 0xe019 3 0 4294967295 RX_EQ_DELTA_IQ_OVRD_VAL 0 3 RX_EQ_DELTA_IQ_OVRD_EN 4 4 RESERVED_15_5 5 15 ixDPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN 2 0xe01a 5 0 4294967295 RX_TERM_CTRL_OVRD_VAL 0 2 RX_TERM_CTRL_OVRD_EN 3 3 TX_TERM_CTRL_OVRD_VAL 4 6 TX_TERM_CTRL_OVRD_EN 7 7 RESERVED_15_8 8 15 ixDPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TXRX_TERM_CTRL_IN 2 0xe01b 3 0 4294967295 RX_TERM_CTRL 0 2 TX_TERM_CTRL 3 5 RESERVED_15_6 6 15 ixDPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT_1 2 0xe01c 2 0 4294967295 RX_CLK_EN 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_EQ_OVRD_IN_1 2 0xe01d 4 0 4294967295 RX_EQ_AFE_GAIN_OVRD_VAL 0 3 RX_EQ_ATT_LVL_OVRD_VAL 4 6 RX_EQ_OVRD_EN 7 7 RESERVED_15_8 8 15 ixDPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_EQ_OVRD_IN_2 2 0xe01e 3 0 4294967295 RX_EQ_DFE_TAP1_OVRD_VAL 0 7 RX_EQ_CTLE_BOOST_OVRD_VAL 8 12 RESERVED_15_13 13 15 ixDPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_PH2_CAL 2 0xe01f 4 0 4294967295 PH2_CAL_ACK_VAL 0 0 PH2_CAL_REQ_VAL 1 1 PH2_CAL_REQ_OVRD_VAL 2 2 RESERVED_15_3 3 15 ixDPCSSYS_CR1_RAWLANEX_DIG_FSM_FSM_OVRD_CTL 2 0xe020 5 0 4294967295 FSM_JMP_ADDR 0 11 FSM_JMP_EN 12 12 FSM_CMD_START 13 13 FSM_OVRD_EN 14 14 FSM_BREAK 15 15 ixDPCSSYS_CR1_RAWLANEX_DIG_FSM_MEM_ADDR_MON 2 0xe021 1 0 4294967295 MEM_ADDR 0 15 ixDPCSSYS_CR1_RAWLANEX_DIG_FSM_STATUS_MON 2 0xe022 8 0 4294967295 STATE 0 4 CMD_RDY 5 5 ALU_OVFLW 6 6 ALU_RES_EQ0 7 7 WAIT_CNT_EQ0 8 8 WRMSK_DISABLED 9 9 RDMSK_DISABLED 10 10 RESERVED_15_11 11 15 ixDPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_RX_STARTUP_CAL 2 0xe023 2 0 4294967295 FAST_RX_STARTUP_CAL 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_RX_ADAPT 2 0xe024 2 0 4294967295 FAST_RX_ADAPT 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_RX_AFE_CAL 2 0xe025 2 0 4294967295 FAST_RX_AFE_CAL 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_RX_DFE_CAL 2 0xe026 2 0 4294967295 FAST_RX_DFE_CAL 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_RX_BYPASS_CAL 2 0xe027 2 0 4294967295 FAST_RX_BYPASS_CAL 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_RX_REFLVL_CAL 2 0xe028 2 0 4294967295 FAST_RX_REFLVL_CAL 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_RX_IQ_CAL 2 0xe029 2 0 4294967295 FAST_RX_IQ_CAL 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_RX_AFE_ADAPT 2 0xe02a 2 0 4294967295 FAST_RX_AFE_ADAPT 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_RX_DFE_ADAPT 2 0xe02b 2 0 4294967295 FAST_RX_DFE_ADAPT 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_SUP 2 0xe02c 2 0 4294967295 FAST_SUP 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_TX_CMN_MODE 2 0xe02d 2 0 4294967295 FAST_TX_CMN_MODE 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_TX_RXDET 2 0xe02e 2 0 4294967295 FAST_TX_RXDET 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_RX_PWRUP 2 0xe02f 2 0 4294967295 FAST_RX_PWRUP 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_RX_VCO_WAIT 2 0xe030 2 0 4294967295 FAST_RX_VCO_WAIT 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_RX_VCO_CAL 2 0xe031 2 0 4294967295 FAST_RX_VCO_CAL 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR1_RAWLANEX_DIG_FSM_CMNCAL_MPLL_STATUS 2 0xe032 3 0 4294967295 CMNCAL_MPLL_INIT 0 0 CMNCAL_MPLL_DONE 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_RX_CONT_CAL_ADAPT 2 0xe033 2 0 4294967295 FAST_RX_CONT_CAL_ADAPT 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_RX_CONT_ADAPT 2 0xe034 2 0 4294967295 FAST_RX_CONT_ADAPT 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_RX_CONT_DATA_CAL 2 0xe035 2 0 4294967295 FAST_RX_CONT_DATA_CAL 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_RX_CONT_PHASE_CAL 2 0xe036 2 0 4294967295 FAST_RX_CONT_PHASE_CAL 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_RX_CONT_AFE_CAL 2 0xe037 2 0 4294967295 FAST_RX_CONT_AFE_CAL 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_FLAGS 2 0xe038 12 0 4294967295 TX_FAST_DCC_CAL 0 0 RX_FAST_DCC_CAL 1 1 RX_FAST_VPHUD_CAL 2 2 RX_FAST_VREF_CAL 3 3 RX_FAST_SIGDET_CAL 4 4 RESERVED_2 5 7 TX_FAST_CONT_DCC_CAL 8 8 RX_FAST_CONT_DCC_CAL 9 9 RX_FAST_CONT_VPHUD_CAL 10 10 RX_FAST_CONT_VREF_CAL 11 11 RESERVED_1 12 14 TX_SKIP_SUP_CAL 15 15 ixDPCSSYS_CR1_RAWLANEX_DIG_FSM_CR_LOCK 2 0xe039 3 0 4294967295 CR_REG_LOCK 0 0 CR_MEM_LOCK 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR1_RAWLANEX_DIG_FSM_TX_DCC_FLAGS 2 0xe03a 4 0 4294967295 RATE 0 0 DIV 1 1 MPLL 2 2 RESERVED_15_3 3 15 ixDPCSSYS_CR1_RAWLANEX_DIG_FSM_TX_DCC_STATUS 2 0xe03b 2 0 4294967295 FLAG 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR1_RAWLANEX_DIG_FSM_OCLA 2 0xe03c 4 0 4294967295 PC_EN 0 0 REG_BANK1_EN 1 1 REG_BANK2_EN 2 2 RESERVED_15_3 3 15 ixDPCSSYS_CR1_RAWLANEX_DIG_FSM_TX_EQ_UPDATE_FLAG 2 0xe03d 2 0 4294967295 TX_EQ_UPDATE_FLAG 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR1_RAWLANEX_DIG_FSM_CMNCAL_RCAL_STATUS 2 0xe03e 3 0 4294967295 CMNCAL_RCAL_INIT 0 0 CMNCAL_RCAL_DONE 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR1_RAWLANEX_DIG_FSM_RX_IQ_PHASE_OFFSET 2 0xe03f 2 0 4294967295 RX_IQ_PHASE_OFFSET 0 3 RESERVED_15_4 4 15 ixDPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_RESET_RTN_REQ 2 0xe040 2 0 4294967295 RESET_RTN_REQ 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_RX_RESET_IRQ 2 0xe041 2 0 4294967295 RX_RESET 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_RX_REQ_IRQ 2 0xe042 2 0 4294967295 RX_REQ 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_RX_RATE_IRQ 2 0xe043 2 0 4294967295 RX_RATE_IRQ 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_RX_PSTATE_IRQ 2 0xe044 2 0 4294967295 RX_PSTATE_IRQ 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ 2 0xe045 2 0 4294967295 RX_ADAPT_REQ_IRQ 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ 2 0xe046 2 0 4294967295 RX_ADAPT_DIS_IRQ 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_RX_RESET_IRQ_CLR 2 0xe047 2 0 4294967295 RX_RESET_IRQ_CLR 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_RX_REQ_IRQ_CLR 2 0xe048 2 0 4294967295 RX_REQ_IRQ_CLR 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_RX_RATE_IRQ_CLR 2 0xe049 2 0 4294967295 RX_RATE_IRQ_CLR 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR 2 0xe04a 2 0 4294967295 RX_PSTATE_IRQ_CLR 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR 2 0xe04b 2 0 4294967295 RX_ADAPT_REQ_IRQ_CLR 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR 2 0xe04c 2 0 4294967295 RX_ADAPT_DIS_IRQ_CLR 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK 2 0xe04d 12 0 4294967295 RX_REQ_IRQ_MSK 0 0 RX_RATE_IRQ_MSK 1 1 RX_PSTATE_IRQ_MSK 2 2 RX_ADAPT_REQ_IRQ_MSK 3 3 RX_ADAPT_DIS_IRQ_MSK 4 4 RX_RESET_IRQ_MSK 5 5 LANE_XCVR_MODE_IRQ_MSK 6 6 RX_PH2_CAL_REQ_IRQ_MSK 7 7 RX_PH2_CAL_DIS_IRQ_MSK 8 8 LANE_RX2TX_SER_LB_EN_IRQ_MSK 9 9 DCC_ONDMD_IRQ_MSK 10 10 RESERVED_15_11 11 15 ixDPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK_2 2 0xe04e 3 0 4294967295 TX_RESET_IRQ_MSK 0 0 TX_REQ_IRQ_MSK 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ 2 0xe04f 2 0 4294967295 LANE_XCVR_MODE_IRQ 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR 2 0xe050 2 0 4294967295 LANE_XCVR_MODE_IRQ_CLR 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ 2 0xe051 2 0 4294967295 RX_PH2_CAL_REQ_IRQ 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ 2 0xe052 2 0 4294967295 RX_PH2_CAL_DIS_IRQ 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR 2 0xe053 2 0 4294967295 RX_PH2_CAL_REQ_IRQ_CLR 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR 2 0xe054 2 0 4294967295 RX_PH2_CAL_DIS_IRQ_CLR 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ 2 0xe055 2 0 4294967295 LANE_RX2TX_SER_LB_EN_IRQ 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR 2 0xe056 2 0 4294967295 LANE_RX2TX_SER_LB_EN_IRQ_CLR 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_DCC_ONDMD_IRQ 2 0xe057 2 0 4294967295 IRQ 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_TX_RESET_IRQ 2 0xe058 2 0 4294967295 TX_RESET 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_TX_REQ_IRQ 2 0xe059 2 0 4294967295 TX_REQ 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_TX_RESET_IRQ_CLR 2 0xe05a 2 0 4294967295 TX_RESET_IRQ_CLR 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_TX_REQ_IRQ_CLR 2 0xe05b 2 0 4294967295 TX_REQ_IRQ_CLR 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_LANE_OVRD_IN 2 0xe060 4 0 4294967295 LANE_MPLLA_EN_IN 0 0 LANE_MPLLB_EN_IN 1 1 LANE_OVRD_EN 2 2 RESERVED_15_3 3 15 ixDPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_LANE_OVRD_OUT 2 0xe061 4 0 4294967295 LANE_MPLLA_EN_OUT 0 0 LANE_MPLLB_EN_OUT 1 1 LANE_OVRD_EN 2 2 RESERVED_15_3 3 15 ixDPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_SUP_OVRD_IN 2 0xe062 4 0 4294967295 MPLLA_STATE 0 0 MPLLB_STATE 1 1 SUP_STATE_OVRD_EN 2 2 RESERVED_15_3 3 15 ixDPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_SUP_PMA_IN 2 0xe063 3 0 4294967295 MPLLA_STATE 0 0 MPLLB_STATE 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT 2 0xe064 16 0 4294967295 TX_REQ_OVRD_VAL 0 0 TX_REQ_OVRD_EN 1 1 TX_RESET_OVRD_VAL 2 2 TX_RESET_OVRD_EN 3 3 TX_BEACON_EN_OVRD_VAL 4 4 TX_BEACON_EN_OVRD_EN 5 5 TX_ASYNC_DRV_EN_OVRD_VAL 6 6 TX_ASYNC_DRV_EN_OVRD_EN 7 7 TX_ASYNC_EN_OVRD_VAL 8 8 TX_ASYNC_EN_OVRD_EN 9 9 TX_DWORD_CLK_SYNC_OVRD_VAL 10 10 TX_DWORD_CLK_SYNC_OVRD_EN 11 11 LANE_TX2RX_SER_LB_EN_OVRD_VAL 12 12 LANE_TX2RX_SER_LB_EN_OVRD_EN 13 13 TX_PMA_DATA_EN_OVRD_VAL_R 14 14 TX_PMA_DATA_EN_OVRD_EN_R 15 15 ixDPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_TX_PMA_IN 2 0xe065 2 0 4294967295 ACK 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT 2 0xe066 9 0 4294967295 RX_REQ_OVRD_VAL 0 0 RX_REQ_OVRD_EN 1 1 RX_RESET_OVRD_VAL 2 2 RX_RESET_OVRD_EN 3 3 LANE_RX2TX_PAR_LB_EN_OVRD_VAL 4 4 LANE_RX2TX_PAR_LB_EN_OVRD_EN 5 5 RX_PMA_DATA_EN_OVRD_VAL_R 6 6 RX_PMA_DATA_EN_OVRD_EN_R 7 7 RESERVED_15_8 8 15 ixDPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_RX_PMA_IN 2 0xe067 2 0 4294967295 ACK 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_LANE_RTUNE_CTL 2 0xe068 2 0 4294967295 LANE_RTUNE_REQ 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_SUP_PMA_IN_1 2 0xe069 2 0 4294967295 RTUNE_ACK 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_IN 2 0xe06a 9 0 4294967295 RX_PMA_PWM_WORD_CLK_R 0 0 RX_PMA_PWM_WORD_CLK_OVRD_EN 1 1 RX_PMA_PWM_DATA_R 2 2 RX_PMA_PWM_DATA_OVRD_EN 3 3 RX_PMA_PWM_CLK_R 4 4 RX_PMA_PWM_CLK_OVRD_EN 5 5 RX_PMA_TERM_CTL_R 6 7 RX_PMA_TERM_CTL_OVRD_EN 8 8 RESERVED_15_9 9 15 ixDPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_OUT 2 0xe06b 7 0 4294967295 RX_PMA_PWM_EN 0 0 RX_PMA_PWM_EN_OVRD_EN 1 1 RX_PMA_PWM_CLK_SEL 2 3 RX_PMA_PWM_CLK_SEL_OVRD_EN 4 4 RX_PMA_ASYNC_EN 5 5 RX_PMA_ASYNC_EN_OVRD_EN 6 6 RESERVED_15_7 7 15 ixDPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_RX_ADAPT_OVRD_OUT 2 0xe06c 3 0 4294967295 RX_PMA_IQ_PHASE_ADJUST_MAP_OVRD_VAL 0 6 RX_PMA_IQ_PHASE_ADJUST_MAP_OVRD_EN 7 7 RESERVED_15_8 8 15 ixDPCSSYS_CR1_RAWLANEX_DIG_TX_CTL_TX_FSM_CTL 2 0xe080 6 0 4294967295 TX_WAIT_MPLL_OFF_TIME 0 6 TX_P2_ALLOW_RXDET 7 7 TX_P1_ALLOW_RXDET 8 8 TX_P0S_ALLOW_RXDET 9 9 TX_P0_ALLOW_RXDET 10 10 RESERVED_15_11 11 15 ixDPCSSYS_CR1_RAWLANEX_DIG_TX_CTL_TX_CLK_CTL 2 0xe081 4 0 4294967295 TX_CLK_EN 0 0 TX_CLK_SEL 1 4 ASYNC_BEACON_WAIT_TIME 5 10 RESERVED_15_11 11 15 ixDPCSSYS_CR1_RAWLANEX_DIG_TX_CTL_TX_DCC_CONT_STATUS 2 0xe082 2 0 4294967295 ENABLE 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR1_RAWLANEX_DIG_TX_CTL_OCLA 2 0xe083 2 0 4294967295 FSM_EN 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR1_RAWLANEX_DIG_TX_CTL_UPCS_OCLA 2 0xe084 3 0 4294967295 DATA_EN 0 1 CLK_EN 2 2 RESERVED_15_3 3 15 ixDPCSSYS_CR1_RAWLANEX_DIG_RX_CTL_RX_FSM_CTL 2 0xe0a0 3 0 4294967295 EN_RX_CTL_FSM 0 0 RATE_CHG_IN_P1 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR1_RAWLANEX_DIG_RX_CTL_RX_LOS_MASK_CTL 2 0xe0a1 2 0 4294967295 RX_LOS_MASK_CNT 0 8 RESERVED_15_9 9 15 ixDPCSSYS_CR1_RAWLANEX_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL 2 0xe0a2 2 0 4294967295 RX_DATA_EN_OVRD_CNT 0 4 INT_REF_TRCK_CNT 5 15 ixDPCSSYS_CR1_RAWLANEX_DIG_RX_CTL_OFFCAN_CONT_STATUS 2 0xe0a3 2 0 4294967295 ENABLE 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR1_RAWLANEX_DIG_RX_CTL_ADAPT_CONT_STATUS 2 0xe0a4 2 0 4294967295 ENABLE 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR1_RAWLANEX_DIG_RX_CTL_UPCS_OCLA 2 0xe0a5 3 0 4294967295 DATA_EN 0 2 CLK_EN 3 3 RESERVED_15_4 4 15 ixDPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN 2 0xe0c0 11 0 4294967295 RATE_OVRD_VAL 0 1 RATE_OVRD_EN 2 2 WIDTH_OVRD_VAL 3 4 WIDTH_OVRD_EN 5 5 PSTATE_OVRD_VAL 6 7 PSTATE_OVRD_EN 8 8 LPD_OVRD_VAL 9 9 LPD_OVRD_EN 10 10 LANE_RX2TX_PAR_LB_EN_OVRD_VAL 11 11 LANE_RX2TX_PAR_LB_EN_OVRD_EN 12 12 RESERVED_15_13 13 15 ixDPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN 2 0xe0c1 12 0 4294967295 PSTATE 0 1 LPD 2 2 WIDTH 3 4 RATE 5 7 MPLLB_SEL 8 8 MPLL_EN 9 9 OVRD_EN 10 10 MSTR_MPLLA_STATE 11 11 MSTR_MPLLB_STATE 12 12 MSTR_MPLL_OVRD_EN 13 13 TX_ASYNC_EN_OVR_VAL 14 14 TX_ASYNC_EN_OVR_EN 15 15 ixDPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1 2 0xe0c2 13 0 4294967295 DETRX_REQ_OVRD_VAL 0 0 DETRX_REQ_OVRD_EN 1 1 VBOOST_EN_OVRD_VAL 2 2 VBOOST_EN_OVRD_EN 3 3 IBOOST_LVL_OVRD_VAL 4 7 IBOOST_LVL_OVRD_EN 8 8 TX_BEACON_EN_OVR_VAL 9 9 TX_BEACON_EN_OVR_EN 10 10 LANE_TX2RX_SER_LB_EN_OVRD_VAL 11 11 LANE_TX2RX_SER_LB_EN_OVRD_EN 12 12 TX_ASYNC_DATA_OVRD_VAL 13 13 TX_ASYNC_DATA_OVRD_EN 14 14 RESERVED_15_15 15 15 ixDPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_MASTER_MPLL_LOOP 2 0xe0c3 3 0 4294967295 MPLLB_LOOP_EN 0 0 MPLLA_LOOP_EN 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1 2 0xe0c4 11 0 4294967295 RESERVED 0 1 RX_LOS_LFPS_EN_OVRD_VAL 2 2 RX_LOS_LFPS_EN_OVRD_EN 3 3 RX_LOS_THRSHLD_OVRD_VAL 4 6 RX_LOS_THRSHLD_OVRD_EN 7 7 ADAPT_REQ 8 8 ADAPT_REQ_OVRD_EN 9 9 ADAPT_CONT 10 10 OFFCAN_CONT 11 11 CONT_OVRD_EN 12 12 RESERVED_15_13 13 15 ixDPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_2 2 0xe0c5 4 0 4294967295 VCO_LD_VAL_OVRD 0 12 VCO_LD_VAL_OVRD_EN 13 13 VCO_LOWFREQ_VAL_OVRD 14 14 VCO_LOWFREQ_VAL_OVRD_EN 15 15 ixDPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_3 2 0xe0c6 3 0 4294967295 REF_LD_VAL_OVRD 0 6 REF_LD_VAL_OVRD_EN 7 7 RESERVED_15_8 8 15 ixDPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT_2 2 0xe0c7 3 0 4294967295 RX_VALID 0 0 RX_VALID_OVRD_EN 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_2 2 0xe0c8 7 0 4294967295 LANE_TX2RX_SER_LB_EN_OVRD_VAL 0 0 LANE_TX2RX_SER_LB_EN_OVRD_EN 1 1 TX_DATA_EN_OVRD_VAL_R 2 2 TX_DATA_EN_OVRD_EN_R 3 3 TX_ASYNC_DATA_OVRD_VAL_R 4 4 TX_ASYNC_DATA_OVRD_EN_R 5 5 RESERVED_15_6 6 15 ixDPCSSYS_CR2_SUP_DIG_IDCODE_LO 2 0x0 1 0 4294967295 DATA 0 0 ixDPCSSYS_CR2_SUP_DIG_IDCODE_HI 2 0x1 1 0 4294967295 DATA 0 0 ixDPCSSYS_CR2_SUP_DIG_REFCLK_OVRD_IN 2 0x2 12 0 4294967295 REF_CLK_EN 0 0 REF_CLK_EN_OVRD_EN 1 1 REF_USE_PAD 2 2 REF_USE_PAD_OVRD_EN 3 3 REF_CLK_RANGE 4 8 REF_CLK_RANGE_OVRD_EN 9 9 BG_EN 10 10 BG_EN_OVRD_EN 11 11 HDMIMODE_EN 12 12 HDMIMODE_ENABLE_OVRD_EN 13 13 SUP_PRE_HP_OVRD 14 14 SUP_PRE_HP_OVRD_EN 15 15 ixDPCSSYS_CR2_SUP_DIG_MPLLA_DIV_CLK_OVRD_IN 2 0x3 4 0 4294967295 MPLLA_DIV_CLK_EN 0 0 MPLLA_DIV_MULTIPLIER 1 8 MPLLA_DIV_OVRD_EN 9 9 RESERVED_15_10 10 15 ixDPCSSYS_CR2_SUP_DIG_MPLLA_HDMI_CLK_OVRD_IN 2 0x4 4 0 4294967295 MPLLA_HDMI_PIXEL_CLK_DIV 0 1 MPLLA_HDMI_DIV 2 4 MPLLA_HDMI_OVRD_EN 5 5 RESERVED_15_6 6 15 ixDPCSSYS_CR2_SUP_DIG_MPLLB_DIV_CLK_OVRD_IN 2 0x5 4 0 4294967295 MPLLB_DIV_CLK_EN 0 0 MPLLB_DIV_MULTIPLIER 1 8 MPLLB_DIV_OVRD_EN 9 9 RESERVED_15_10 10 15 ixDPCSSYS_CR2_SUP_DIG_MPLLB_HDMI_CLK_OVRD_IN 2 0x6 4 0 4294967295 MPLLB_HDMI_PIXEL_CLK_DIV 0 1 MPLLB_HDMI_DIV 2 4 MPLLB_HDMI_OVRD_EN 5 5 RESERVED_15_6 6 15 ixDPCSSYS_CR2_SUP_DIG_MPLLA_OVRD_IN_0 2 0x7 12 0 4294967295 MPLLA_EN 0 0 MPLLA_DIV5_CLK_EN 1 1 MPLLA_TX_CLK_DIV 2 4 OVRD_EN 5 5 MPLLA_V2I 6 7 MPLLA_STANDBY 8 8 MPLLA_FREQ_VCO 9 10 MPLLA_CAL_FORCE 11 11 MPLL_FRACN_EN 12 12 MPLLA_CLK_SYNC_OVRD 13 13 MPLLA_CLK_SYNC_OVRD_EN 14 14 RESERVED_15_15 15 15 ixDPCSSYS_CR2_SUP_DIG_MPLLA_OVRD_IN_1 2 0x8 2 0 4294967295 MPLLA_MULTIPLIER 0 11 RESERVED_15_12 12 15 ixDPCSSYS_CR2_SUP_DIG_MPLLA_OVRD_IN_2 2 0x9 7 0 4294967295 MPLLA_SSC_EN 0 0 MPLLA_SSC_OVRD_EN 1 1 MPLLA_SSC_UP_SPREAD 2 2 MPLLA_PMIX_EN 3 3 MPLLA_WORD_DIV2_EN 4 4 MPLLA_FRACN_CFG_UPDATE_EN 5 5 RESERVED_15_6 6 15 ixDPCSSYS_CR2_SUP_DIG_MPLLA_SSC_PEAK_1 2 0xa 1 0 4294967295 MPLLA_SSC_PEAK_15_0 0 15 ixDPCSSYS_CR2_SUP_DIG_MPLLA_SSC_PEAK_2 2 0xb 2 0 4294967295 MPLLA_SSC_PEAK_19_16 0 3 RESERVED_15_4 4 15 ixDPCSSYS_CR2_SUP_DIG_MPLLA_SSC_STEPSIZE_1 2 0xc 1 0 4294967295 MPLLA_SSC_STEPSIZE_15_0 0 15 ixDPCSSYS_CR2_SUP_DIG_MPLLA_SSC_STEPSIZE_2 2 0xd 2 0 4294967295 MPLLA_SSC_STEPSIZE_20_16 0 4 RESERVED_15_5 5 15 ixDPCSSYS_CR2_SUP_DIG_MPLLA_OVRD_IN_3 2 0xe 1 0 4294967295 MPLLA_FRACN_QUOT 0 15 ixDPCSSYS_CR2_SUP_DIG_MPLLA_OVRD_IN_4 2 0xf 1 0 4294967295 MPLLA_FRACN_REM 0 15 ixDPCSSYS_CR2_SUP_DIG_MPLLA_OVRD_IN_5 2 0x10 1 0 4294967295 MPLLA_FRACN_DEN 0 15 ixDPCSSYS_CR2_SUP_DIG_MPLLA_CP_OVRD_IN 2 0x11 3 0 4294967295 MPLLA_CP_PROP 0 6 MPLLA_CP_INT 7 13 RESERVED_15_14 14 15 ixDPCSSYS_CR2_SUP_DIG_MPLLA_CP_GS_OVRD_IN 2 0x12 4 0 4294967295 MPLLA_CP_PROP_GS 0 6 MPLLA_CP_PROP_GS_OVR_EN 7 7 MPLLA_CP_INT_GS 8 14 MPLLA_CP_INT_GS_OVR_EN 15 15 ixDPCSSYS_CR2_SUP_DIG_MPLLB_OVRD_IN_0 2 0x13 12 0 4294967295 MPLLB_EN 0 0 MPLLB_DIV5_CLK_EN 1 1 MPLLB_TX_CLK_DIV 2 4 OVRD_EN 5 5 MPLLB_V2I 6 7 MPLLB_STANDBY 8 8 MPLLB_FREQ_VCO 9 10 MPLLB_CAL_FORCE 11 11 MPLL_FRACN_EN 12 12 MPLLB_CLK_SYNC_OVRD 13 13 MPLLB_CLK_SYNC_OVRD_EN 14 14 RESERVED_15_15 15 15 ixDPCSSYS_CR2_SUP_DIG_MPLLB_OVRD_IN_1 2 0x14 2 0 4294967295 MPLLB_MULTIPLIER 0 11 RESERVED_15_12 12 15 ixDPCSSYS_CR2_SUP_DIG_MPLLB_OVRD_IN_2 2 0x15 7 0 4294967295 MPLLB_SSC_EN 0 0 MPLLB_SSC_OVRD_EN 1 1 MPLLB_SSC_UP_SPREAD 2 2 MPLLB_PMIX_EN 3 3 MPLLB_WORD_DIV2_EN 4 4 MPLLB_FRACN_CFG_UPDATE_EN 5 5 RESERVED_15_6 6 15 ixDPCSSYS_CR2_SUP_DIG_MPLLB_SSC_PEAK_1 2 0x16 1 0 4294967295 MPLLB_SSC_PEAK_15_0 0 15 ixDPCSSYS_CR2_SUP_DIG_MPLLB_SSC_PEAK_2 2 0x17 2 0 4294967295 MPLLB_SSC_PEAK_19_16 0 3 RESERVED_15_4 4 15 ixDPCSSYS_CR2_SUP_DIG_MPLLB_SSC_STEPSIZE_1 2 0x18 1 0 4294967295 MPLLB_SSC_STEPSIZE_15_0 0 15 ixDPCSSYS_CR2_SUP_DIG_MPLLB_SSC_STEPSIZE_2 2 0x19 2 0 4294967295 MPLLB_SSC_STEPSIZE_20_16 0 4 RESERVED_15_5 5 15 ixDPCSSYS_CR2_SUP_DIG_MPLLB_OVRD_IN_3 2 0x1a 1 0 4294967295 MPLLB_FRACN_QUOT 0 15 ixDPCSSYS_CR2_SUP_DIG_MPLLB_OVRD_IN_4 2 0x1b 1 0 4294967295 MPLLB_FRACN_REM 0 15 ixDPCSSYS_CR2_SUP_DIG_MPLLB_OVRD_IN_5 2 0x1c 1 0 4294967295 MPLLB_FRACN_DEN 0 15 ixDPCSSYS_CR2_SUP_DIG_MPLLB_CP_OVRD_IN 2 0x1d 3 0 4294967295 MPLLB_CP_PROP 0 6 MPLLB_CP_INT 7 13 RESERVED_15_14 14 15 ixDPCSSYS_CR2_SUP_DIG_MPLLB_CP_GS_OVRD_IN 2 0x1e 4 0 4294967295 MPLLB_CP_PROP_GS 0 6 MPLLB_CP_PROP_GS_OVR_EN 7 7 MPLLB_CP_INT_GS 8 14 MPLLB_CP_INT_GS_OVR_EN 15 15 ixDPCSSYS_CR2_SUP_DIG_SUP_OVRD_IN 2 0x1f 8 0 4294967295 PRESCALER_OVRD_EN 0 0 RTUNE_REQ 1 1 RTUNE_OVRD_EN 2 2 TX_CAL_CODE 3 6 TX_CAL_CODE_EN 7 7 REF_ALT_CLK_LP_SEL_OVRD 8 8 REF_ALT_CLK_LP_SEL_OVRD_EN 9 9 RESERVED_15_10 10 15 ixDPCSSYS_CR2_SUP_DIG_PRESCALER_OVRD_IN 2 0x20 6 0 4294967295 DCO_RANGE 0 1 DCO_FINETUNE 2 7 REF_CLK_MPLLB_DIV 8 10 REF_CLK_MPLLA_DIV 11 13 REF_CLKDET_RESULT 14 14 REF_CLKDET_EN 15 15 ixDPCSSYS_CR2_SUP_DIG_SUP_OVRD_OUT 2 0x21 12 0 4294967295 RTUNE_ACK 0 0 RTUNE_ACK_OVRD_EN 1 1 MPLLA_STATE 2 2 MPLLA_STATE_OVRD_EN 3 3 MPLLB_STATE 4 4 MPLLB_STATE_OVRD_EN 5 5 BG_LANE_STATE 6 6 BG_LANE_STATE_OVRD_EN 7 7 BG_SUP_STATE 8 8 BG_SUP_STATE_OVRD_EN 9 9 REF_CLK_ACK 10 10 RESERVED_15_11 11 15 ixDPCSSYS_CR2_SUP_DIG_LVL_OVRD_IN 2 0x22 7 0 4294967295 RX_VREF_CTRL 0 2 RX_VREF_CTRL_EN 3 3 TX_VBOOST_LVL 4 6 TX_VBOOST_LVL_EN 7 7 SUP_RX_VCO_VREF_SEL_OVR 8 10 SUP_RX_VCO_VREF_SEL_OVR_EN 11 11 RESERVED_15_12 12 15 ixDPCSSYS_CR2_SUP_DIG_MPLLA_ASIC_IN_0 2 0x24 9 0 4294967295 MPLLA_EN 0 0 MPLLA_DIV5_CLK_EN 1 1 MPLLA_TX_CLK_DIV 2 4 MPLLA_V2I 5 6 MPLLA_STANDBY 7 7 MPLLA_FREQ_VCO 8 9 MPLLA_CAL_FORCE 10 10 MPLLA_FRACN_EN 11 11 RESERVED_15_12 12 15 ixDPCSSYS_CR2_SUP_DIG_MPLLA_ASIC_IN_1 2 0x25 2 0 4294967295 MPLLA_MULTIPLIER 0 11 RESERVED_15_12 12 15 ixDPCSSYS_CR2_SUP_DIG_MPLLA_ASIC_IN_2 2 0x26 7 0 4294967295 MPLLA_SSC_EN 0 0 MPLLA_SSC_UP_SPREAD 1 1 MPLLA_PMIX_EN 2 2 MPLLA_WORD_DIV2_EN 3 3 MPLLA_FRACN_CFG_UPDATE_EN 4 4 MPLLA_CLK_SYNC 5 5 RESERVED_15_6 6 15 ixDPCSSYS_CR2_SUP_DIG_MPLLA_ASIC_IN_3 2 0x27 1 0 4294967295 MPLLA_SSC_PEAK_15_0 0 15 ixDPCSSYS_CR2_SUP_DIG_MPLLA_ASIC_IN_4 2 0x28 2 0 4294967295 MPLLA_SSC_PEAK_19_16 0 3 RESERVED_15_4 4 15 ixDPCSSYS_CR2_SUP_DIG_MPLLA_ASIC_IN_5 2 0x29 1 0 4294967295 MPLLA_SSC_STEPSIZE_15_0 0 15 ixDPCSSYS_CR2_SUP_DIG_MPLLA_ASIC_IN_6 2 0x2a 2 0 4294967295 MPLLA_SSC_STEPSIZE_20_16 0 3 RESERVED_15_4 4 15 ixDPCSSYS_CR2_SUP_DIG_MPLLB_ASIC_IN_0 2 0x2b 9 0 4294967295 MPLLB_EN 0 0 MPLLB_DIV5_CLK_EN 1 1 MPLLB_TX_CLK_DIV 2 4 MPLLB_V2I 5 6 MPLLB_STANDBY 7 7 MPLLB_FREQ_VCO 8 9 MPLLB_CAL_FORCE 10 10 MPLLB_FRACN_EN 11 11 RESERVED_15_12 12 15 ixDPCSSYS_CR2_SUP_DIG_MPLLB_ASIC_IN_1 2 0x2c 2 0 4294967295 MPLLB_MULTIPLIER 0 11 RESERVED_15_12 12 15 ixDPCSSYS_CR2_SUP_DIG_MPLLB_ASIC_IN_2 2 0x2d 7 0 4294967295 MPLLB_SSC_EN 0 0 MPLLB_SSC_UP_SPREAD 1 1 MPLLB_PMIX_EN 2 2 MPLLB_WORD_DIV2_EN 3 3 MPLLB_FRACN_CFG_UPDATE_EN 4 4 MPLLB_CLK_SYNC 5 5 RESERVED_15_6 6 15 ixDPCSSYS_CR2_SUP_DIG_MPLLB_ASIC_IN_3 2 0x2e 1 0 4294967295 MPLLB_SSC_PEAK_15_0 0 15 ixDPCSSYS_CR2_SUP_DIG_MPLLB_ASIC_IN_4 2 0x2f 2 0 4294967295 MPLLB_SSC_PEAK_19_16 0 3 RESERVED_15_4 4 15 ixDPCSSYS_CR2_SUP_DIG_MPLLB_ASIC_IN_5 2 0x30 1 0 4294967295 MPLLB_SSC_STEPSIZE_15_0 0 15 ixDPCSSYS_CR2_SUP_DIG_MPLLB_ASIC_IN_6 2 0x31 2 0 4294967295 MPLLB_SSC_STEPSIZE_20_16 0 3 RESERVED_15_4 4 15 ixDPCSSYS_CR2_SUP_DIG_MPLLA_DIV_CLK_ASIC_IN 2 0x32 3 0 4294967295 MPLLA_DIV_CLK_EN 0 0 MPLLA_DIV_MULTIPLIER 1 8 RESERVED_15_9 9 15 ixDPCSSYS_CR2_SUP_DIG_MPLLA_HDMI_CLK_ASIC_IN 2 0x33 3 0 4294967295 MPLLA_HDMI_PIXEL_CLK_DIV 0 1 MPLLA_HDMI_DIV 2 4 RESERVED_15_5 5 15 ixDPCSSYS_CR2_SUP_DIG_MPLLB_DIV_CLK_ASIC_IN 2 0x34 3 0 4294967295 MPLLB_DIV_CLK_EN 0 0 MPLLB_DIV_MULTIPLIER 1 8 RESERVED_15_9 9 15 ixDPCSSYS_CR2_SUP_DIG_MPLLB_HDMI_CLK_ASIC_IN 2 0x35 3 0 4294967295 MPLLB_HDMI_PIXEL_CLK_DIV 0 1 MPLLB_HDMI_DIV 2 4 RESERVED_15_5 5 15 ixDPCSSYS_CR2_SUP_DIG_ASIC_IN 2 0x36 12 0 4294967295 PHY_RESET 0 0 REF_CLK_EN 1 1 REF_USE_PAD 2 2 TEST_BURNIN 3 3 TEST_POWERDOWN 4 4 RTUNE_REQ 5 5 RTUNE_ACK 6 6 MPLLA_STATE 7 7 MPLLB_STATE 8 8 TEST_TX_REF_CLK_EN 9 9 REF_ALT_CLK_LP_SEL 10 10 RESERVED_15_11 11 15 ixDPCSSYS_CR2_SUP_DIG_LVL_ASIC_IN 2 0x37 4 0 4294967295 RX_VREF_CTRL 0 2 TX_VBOOST_LVL 3 5 SUP_RX_VCO_VREF_SEL 6 8 RESERVED_15_9 9 15 ixDPCSSYS_CR2_SUP_DIG_BANDGAP_ASIC_IN 2 0x38 2 0 4294967295 BG_EN 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR2_SUP_DIG_MPLLA_CP_ASIC_IN 2 0x39 3 0 4294967295 MPLLA_CP_PROP 0 6 MPLLA_CP_INT 7 13 RESERVED_15_14 14 15 ixDPCSSYS_CR2_SUP_DIG_MPLLA_CP_GS_ASIC_IN 2 0x3a 3 0 4294967295 MPLLA_CP_PROP_GS 0 6 MPLLA_CP_INT_GS 7 13 RESERVED_15_14 14 15 ixDPCSSYS_CR2_SUP_DIG_MPLLB_CP_ASIC_IN 2 0x3b 3 0 4294967295 MPLLB_CP_PROP 0 6 MPLLB_CP_INT 7 13 RESERVED_15_14 14 15 ixDPCSSYS_CR2_SUP_DIG_MPLLB_CP_GS_ASIC_IN 2 0x3c 3 0 4294967295 MPLLB_CP_PROP_GS 0 6 MPLLB_CP_INT_GS 7 13 RESERVED_15_14 14 15 ixDPCSSYS_CR2_SUP_ANA_PRESCALER_CTRL 2 0x40 7 0 4294967295 PSCALER_ATB_SELECT 0 0 PSCALER_MEAS_VREG 0 0 PSCALER_OVRD_FAST_START 0 0 PSCALER_FAST_START_REG 0 0 PSCALER_VREG_BOOST 0 0 PSCALER_HYST_REF 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR2_SUP_ANA_RTUNE_CTRL 2 0x41 9 0 4294967295 RT_ATB 0 0 RT_SEL_ATBF 0 0 RT_SEL_ATBP 0 0 RT_VP4O8_EN 0 0 RT_DAC_CHOP 0 0 RT_DAC_MODE 0 0 RT_EN_FRCON 0 0 PSCALER_VREG_FB_DIV_CTRL 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR2_SUP_ANA_BG1 2 0x42 6 0 4294967295 SUP_SEL_VBG_VREF 0 0 SUP_SEL_VPHUD_VREF 0 0 NC4 4 4 SUP_SEL_VPLL_REF 0 0 RT_VREF_SEL 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR2_SUP_ANA_BG2 2 0x43 9 0 4294967295 SUP_BYPASS_BG 0 0 SUP_CHOP_EN 0 0 SUP_TEMP_MEAS 0 0 VPHUD_SELREF 0 0 ATB_EXT_MEAS_EN 0 0 RT_TX_OFFSET_EN 0 0 SUP_SEL_TX_SWING_VREF 0 0 PSCALER_VREG_OVERRIDE_RING_CTRL 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR2_SUP_ANA_SWITCH_PWR_MEAS 2 0x44 3 0 4294967295 SUP_ATB_SW 0 0 SUP_TIE 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR2_SUP_ANA_BG3 2 0x45 4 0 4294967295 SUP_SEL_RX_VCO_TC_VREF 0 0 SUP_SEL_RX_CAL_VREF 0 0 NC7_4 4 7 RESERVED_15_8 8 15 ixDPCSSYS_CR2_SUP_ANA_MPLLA_MISC1 2 0x46 7 0 4294967295 OVRD_GEAR_RC_FILT 0 0 OVRD_TEST_RC_FILT 0 0 TEST_VREG_DIV 0 0 VBG_EN 0 0 COUNT_SEL_LOCK 0 0 PHASE_SEL_LOCK 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR2_SUP_ANA_MPLLA_MISC2 2 0x47 8 0 4294967295 OVRD_PR_BYPASS 0 0 PR_BYPASS 0 0 OVRD_GEARSHIFT 0 0 GEARSHIFT_REG 0 0 TEST_LOCK_GEAR 0 0 EN_CAL_SPO 0 0 TEST_BOOST 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR2_SUP_ANA_MPLLA_OVRD 2 0x48 9 0 4294967295 OVRD_ENABLE 0 0 ENABLE_REG 0 0 OVRD_CAL 0 0 CAL_REG 0 0 OVRD_FB_CLK_EN 0 0 FB_CLK_EN_REG 0 0 OVRD_RESET 0 0 RESET_REG 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR2_SUP_ANA_MPLLA_ATB1 2 0x49 3 0 4294967295 MEAS_IV_WRAP 0 0 ATB_SELECT 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR2_SUP_ANA_MPLLA_ATB2 2 0x4a 2 0 4294967295 MEAS_IV_PLL 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR2_SUP_ANA_MPLLA_ATB3 2 0x4b 3 0 4294967295 MEAS_IV_BIAS 0 0 CTR_UPLL_TUNNING 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR2_SUP_ANA_MPLLA_CTR1 2 0x4c 5 0 4294967295 CTR_ICP_INT 0 0 CTR_VREF_EN 0 0 CTR_VREF_VMARG 0 0 CTR_CP_PLL 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR2_SUP_ANA_MPLLA_CTR2 2 0x4d 2 0 4294967295 CTR_REGS_PLL 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR2_SUP_ANA_MPLLA_CTR3 2 0x4e 4 0 4294967295 CTR_REGS_CP_PLL 0 0 CTR_SPO_PLL 0 0 CTR_VINT_CAP 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR2_SUP_ANA_MPLLA_CTR4 2 0x4f 7 0 4294967295 CTR_CP_8X 0 0 CTR_FIL_REG 0 0 CTR_CP_PROP_REF 0 0 CTR_DOUBLER_GAIN 0 0 CTR_TEST_CASC 0 0 CTR_RC_FITER 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR2_SUP_ANA_MPLLA_CTR5 2 0x50 8 0 4294967295 CTR_STANDBY_MODE 0 0 CTR_LEG_SR_CON 0 0 CTR_VREG_RING_OVERRIDE 0 0 CTR_SPO_SPEED_OVERRIDE 0 0 CTR_BYPASS_LOCK_SPO_CAL 0 0 CTR_LOCK_SPO_CAL 0 0 CTR_UPLL_RESERVED 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR2_SUP_ANA_MPLLA_RESERVED1 2 0x51 8 0 4294967295 CTR_REF_FBK_BYPASS 0 0 CTR_BYPASS_TX 0 0 CTR_VREG_CLK_BYPASS 0 0 CTR_VREG_CLK_PMIX_BYPASS 0 0 CTR_VREG_RIGHT_BYPASS 0 0 CTR_VREG_LEFT_BYPASS 0 0 CTR_LEFT_RIGHT_GAIN 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR2_SUP_ANA_MPLLA_RESERVED2 2 0x52 5 0 4294967295 CTR_DLL_MODE_90 0 0 CTR_DLL_RESERVED 0 0 CTR_DIV24_DSQ_ENZ 0 0 CTR_DIV4 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR2_SUP_ANA_MPLLB_MISC1 2 0x53 7 0 4294967295 OVRD_GEAR_RC_FILT 0 0 OVRD_TEST_RC_FILT 0 0 TEST_VREG_DIV 0 0 VBG_EN 0 0 COUNT_SEL_LOCK 0 0 PHASE_SEL_LOCK 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR2_SUP_ANA_MPLLB_MISC2 2 0x54 8 0 4294967295 OVRD_PR_BYPASS 0 0 PR_BYPASS 0 0 OVRD_GEARSHIFT 0 0 GEARSHIFT_REG 0 0 TEST_LOCK_GEAR 0 0 EN_CAL_SPO 0 0 TEST_BOOST 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR2_SUP_ANA_MPLLB_OVRD 2 0x55 9 0 4294967295 OVRD_ENABLE 0 0 ENABLE_REG 0 0 OVRD_CAL 0 0 CAL_REG 0 0 OVRD_FB_CLK_EN 0 0 FB_CLK_EN_REG 0 0 OVRD_RESET 0 0 RESET_REG 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR2_SUP_ANA_MPLLB_ATB1 2 0x56 3 0 4294967295 MEAS_IV_WRAP 0 0 ATB_SELECT 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR2_SUP_ANA_MPLLB_ATB2 2 0x57 2 0 4294967295 MEAS_IV_PLL 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR2_SUP_ANA_MPLLB_ATB3 2 0x58 3 0 4294967295 MEAS_IV_BIAS 0 0 CTR_UPLL_TUNNING 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR2_SUP_ANA_MPLLB_CTR1 2 0x59 5 0 4294967295 CTR_ICP_INT 0 0 CTR_VREF_EN 0 0 CTR_VREF_VMARG 0 0 CTR_CP_PLL 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR2_SUP_ANA_MPLLB_CTR2 2 0x5a 2 0 4294967295 CTR_REGS_PLL 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR2_SUP_ANA_MPLLB_CTR3 2 0x5b 4 0 4294967295 CTR_REGS_CP_PLL 0 0 CTR_SPO_PLL 0 0 CTR_VINT_CAP 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR2_SUP_ANA_MPLLB_CTR4 2 0x5c 7 0 4294967295 CTR_CP_8X 0 0 CTR_FIL_REG 0 0 CTR_CP_PROP_REF 0 0 CTR_DOUBLER_GAIN 0 0 CTR_TEST_CASC 0 0 CTR_RC_FITER 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR2_SUP_ANA_MPLLB_CTR5 2 0x5d 8 0 4294967295 CTR_STANDBY_MODE 0 0 CTR_LEG_SR_CON 0 0 CTR_VREG_RING_OVERRIDE 0 0 CTR_SPO_SPEED_OVERRIDE 0 0 CTR_BYPASS_LOCK_SPO_CAL 0 0 CTR_LOCK_SPO_CAL 0 0 CTR_UPLL_RESERVED 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR2_SUP_ANA_MPLLB_RESERVED1 2 0x5e 8 0 4294967295 CTR_REF_FBK_BYPASS 0 0 CTR_BYPASS_TX 0 0 CTR_VREG_CLK_BYPASS 0 0 CTR_VREG_CLK_PMIX_BYPASS 0 0 CTR_VREG_RIGHT_BYPASS 0 0 CTR_VREG_LEFT_BYPASS 0 0 CTR_LEFT_RIGHT_GAIN 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR2_SUP_ANA_MPLLB_RESERVED2 2 0x5f 5 0 4294967295 CTR_DLL_MODE_90 0 0 CTR_DLL_RESERVED 0 0 CTR_DIV24_DSQ_ENZ 0 0 CTR_DIV4 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD 2 0x61 8 0 4294967295 OVRD_SEL 0 0 MPLL_FBDIGCLK_EN 1 1 MPLL_PCLK_EN 2 2 FAST_MPLL_PWRUP 3 3 FAST_MPLL_LOCK 4 4 DTB_SEL 5 9 DIV10_EN 10 10 RESERVED 11 15 ixDPCSSYS_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT 2 0x62 11 0 4294967295 FSM_STATE 0 3 MPLL_R_LANES 4 4 MPLL_L_LANES 5 5 MPLL_PCLK_EN 6 6 MPLL_OUTPUT_EN 7 7 MPLL_FBCLK_EN 8 8 MPLL_CAL 9 9 MPLL_RST 10 10 MPLL_ANA_EN 11 11 MPLL_LOCK 12 12 RESERVED_15_13 13 15 ixDPCSSYS_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE 2 0x63 3 0 4294967295 MAX_RANGE 0 4 DAC_IN 5 9 RESERVED_15_10 10 15 ixDPCSSYS_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_LOCK 2 0x64 3 0 4294967295 LOCK_TIME 0 7 STABLE_TIME 8 13 RESERVED_15_14 14 15 ixDPCSSYS_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS 2 0x65 2 0 4294967295 GEARSHIFT_TIME 0 7 PRESET_TIME 8 15 ixDPCSSYS_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE 2 0x66 3 0 4294967295 PWRDN_WAIT_TIME 0 5 PCLK_EN_TIME 6 11 RESERVED_15_12 12 15 ixDPCSSYS_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2 2 0x67 3 0 4294967295 PCLK_DIS_TIME 0 5 PWRDN_TIME 6 11 RESERVED_15_12 12 15 ixDPCSSYS_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_CAL 2 0x68 3 0 4294967295 MPLL_CAL 0 0 MPLL_CAL_OVRD_EN 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT 2 0x69 2 0 4294967295 MPLL_ANA_DAC_OUT 0 4 RESERVED_15_5 5 15 ixDPCSSYS_CR2_SUP_DIG_MPLLA_SSC_GEN_SPREAD_TYPE 2 0x6b 3 0 4294967295 SPREAD_TYPE 0 1 OVR_EN 2 2 RESERVED_15_3 3 15 ixDPCSSYS_CR2_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD 2 0x6d 8 0 4294967295 OVRD_SEL 0 0 MPLL_FBDIGCLK_EN 1 1 MPLL_PCLK_EN 2 2 FAST_MPLL_PWRUP 3 3 FAST_MPLL_LOCK 4 4 DTB_SEL 5 9 DIV10_EN 10 10 RESERVED 11 15 ixDPCSSYS_CR2_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT 2 0x6e 11 0 4294967295 FSM_STATE 0 3 MPLL_R_LANES 4 4 MPLL_L_LANES 5 5 MPLL_PCLK_EN 6 6 MPLL_OUTPUT_EN 7 7 MPLL_FBCLK_EN 8 8 MPLL_CAL 9 9 MPLL_RST 10 10 MPLL_ANA_EN 11 11 MPLL_LOCK 12 12 RESERVED_15_13 13 15 ixDPCSSYS_CR2_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE 2 0x6f 3 0 4294967295 MAX_RANGE 0 4 DAC_IN 5 9 RESERVED_15_10 10 15 ixDPCSSYS_CR2_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_LOCK 2 0x70 3 0 4294967295 LOCK_TIME 0 7 STABLE_TIME 8 13 RESERVED_15_14 14 15 ixDPCSSYS_CR2_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS 2 0x71 2 0 4294967295 GEARSHIFT_TIME 0 7 PRESET_TIME 8 15 ixDPCSSYS_CR2_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE 2 0x72 3 0 4294967295 PWRDN_WAIT_TIME 0 5 PCLK_EN_TIME 6 11 RESERVED_15_12 12 15 ixDPCSSYS_CR2_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2 2 0x73 3 0 4294967295 PCLK_DIS_TIME 0 5 PWRDN_TIME 6 11 RESERVED_15_12 12 15 ixDPCSSYS_CR2_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_CAL 2 0x74 3 0 4294967295 MPLL_CAL 0 0 MPLL_CAL_OVRD_EN 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR2_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT 2 0x75 2 0 4294967295 MPLL_ANA_DAC_OUT 0 4 RESERVED_15_5 5 15 ixDPCSSYS_CR2_SUP_DIG_MPLLB_SSC_GEN_SPREAD_TYPE 2 0x77 3 0 4294967295 SPREAD_TYPE 0 1 OVR_EN 2 2 RESERVED_15_3 3 15 ixDPCSSYS_CR2_SUP_DIG_CLK_RST_BG_PWRUP_TIME_0 2 0x78 3 0 4294967295 BG_SUP_EN_TIME 0 8 FAST_BG_WAIT 9 9 RESERVED_15_10 10 15 ixDPCSSYS_CR2_SUP_DIG_CLK_RST_BG_PWRUP_TIME_1 2 0x79 2 0 4294967295 BG_LANE_EN_TIME 0 8 RESERVED_15_9 9 15 ixDPCSSYS_CR2_SUP_DIG_CLK_RST_BG_PWRUP_TIME_2 2 0x7a 3 0 4294967295 BG_KICK_START_EN_TIME 0 7 BG_SUP_STATE_UPD_EN 8 8 RESERVED_15_9 9 15 ixDPCSSYS_CR2_SUP_DIG_CLK_RST_REF_PWRUP_TIME_0 2 0x7b 3 0 4294967295 REF_VREG_FAST_START_TIME 0 4 FAST_REF_WAIT 5 5 RESERVED_15_6 6 15 ixDPCSSYS_CR2_SUP_DIG_CLK_RST_REF_VPHUD 2 0x7c 3 0 4294967295 SUP_ANA_VPHUD_SELVPH_I 0 0 SUP_ANA_VPHUD_EN_I 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR2_SUP_DIG_RTUNE_CONFIG 2 0x81 5 0 4294967295 RX_CAL_EN 0 0 FAST_RTUNE 1 1 TX_CAL_EN 2 2 SUP_ANA_TERM_CTRL 3 5 RESERVED_15_6 6 15 ixDPCSSYS_CR2_SUP_DIG_RTUNE_STAT 2 0x82 3 0 4294967295 STAT 0 9 DTB_RTUNE 10 11 RESERVED_15_12 12 15 ixDPCSSYS_CR2_SUP_DIG_RTUNE_RX_SET_VAL 2 0x83 2 0 4294967295 RX_SET_VAL 0 5 RESERVED_15_6 6 15 ixDPCSSYS_CR2_SUP_DIG_RTUNE_TXDN_SET_VAL 2 0x84 2 0 4294967295 TXDN_SET_VAL 0 9 RESERVED_15_10 10 15 ixDPCSSYS_CR2_SUP_DIG_RTUNE_TXUP_SET_VAL 2 0x85 2 0 4294967295 TXUP_SET_VAL 0 9 RESERVED_15_10 10 15 ixDPCSSYS_CR2_SUP_DIG_RTUNE_RX_STAT 2 0x86 2 0 4294967295 RX_STAT 0 5 RESERVED_15_6 6 15 ixDPCSSYS_CR2_SUP_DIG_RTUNE_TXDN_STAT 2 0x87 2 0 4294967295 TXDN_STAT 0 9 RESERVED_15_10 10 15 ixDPCSSYS_CR2_SUP_DIG_RTUNE_TXUP_STAT 2 0x88 2 0 4294967295 TXUP_STAT 0 9 RESERVED_15_10 10 15 ixDPCSSYS_CR2_SUP_DIG_RTUNE_CONFIG_CNT0 2 0x89 4 0 4294967295 RT_RESULT_TIME 0 3 RT_EVAL_TIME 4 7 RT_RST_TIME 8 11 RT_ACK_TIME 12 15 ixDPCSSYS_CR2_SUP_DIG_RTUNE_CONFIG_CNT1 2 0x8a 3 0 4294967295 RT_TXDN_SETTLE_TIME 0 3 RT_PWRUP_TIME 4 8 RESERVED_15_9 9 15 ixDPCSSYS_CR2_SUP_DIG_RTUNE_TX_CAL_CODE 2 0x8b 2 0 4294967295 VALUE 0 3 RESERVED_15_4 4 15 ixDPCSSYS_CR2_SUP_DIG_ANA_MPLLA_OVRD_OUT_0 2 0x8c 16 0 4294967295 MPLLA_WORD_CLK_EN 0 0 MPLLA_HDMI_CLK_EN 1 1 MPLLA_DIV_CLK_EN 2 2 MPLLA_OUTPUT_EN 3 3 MPLLA_CLK_EN_OVRD_EN 4 4 MPLLA_OUTPUT_L_EN 5 5 MPLLA_OUTPUT_R_EN 6 6 MPLLA_ANA_EN 7 7 MPLLA_RST 8 8 MPLLA_CAL 9 9 MPLLA_DIV5_CLK_EN 10 10 MPLLA_DIV10_CLK_EN 11 11 MPLLA_FBCLK_EN 12 12 MPLLA_GEARSHIFT_EN 13 13 MPLLA_STANDBY 14 14 OVRD_SEL 15 15 ixDPCSSYS_CR2_SUP_DIG_ANA_MPLLA_OVRD_OUT_1 2 0x8d 2 0 4294967295 MPLLA_ANA_INT 0 9 RESERVED_15_10 10 15 ixDPCSSYS_CR2_SUP_DIG_ANA_MPLLA_OVRD_OUT_2 2 0x8e 3 0 4294967295 MPLLA_CP_PROP 0 6 MPLLA_CP_INT 7 13 RESERVED_15_14 14 15 ixDPCSSYS_CR2_SUP_DIG_ANA_MPLLB_OVRD_OUT_0 2 0x8f 16 0 4294967295 MPLLB_WORD_CLK_EN 0 0 MPLLB_HDMI_CLK_EN 1 1 MPLLB_DIV_CLK_EN 2 2 MPLLB_OUTPUT_EN 3 3 MPLLB_CLK_EN_OVRD_EN 4 4 MPLLB_OUTPUT_L_EN 5 5 MPLLB_OUTPUT_R_EN 6 6 MPLLB_ANA_EN 7 7 MPLLB_RST 8 8 MPLLB_CAL 9 9 MPLLB_DIV5_CLK_EN 10 10 MPLLB_DIV10_CLK_EN 11 11 MPLLB_FBCLK_EN 12 12 MPLLB_GEARSHIFT_EN 13 13 MPLLB_STANDBY 14 14 OVRD_SEL 15 15 ixDPCSSYS_CR2_SUP_DIG_ANA_MPLLB_OVRD_OUT_1 2 0x90 2 0 4294967295 MPLLB_ANA_INT 0 9 RESERVED_15_10 10 15 ixDPCSSYS_CR2_SUP_DIG_ANA_MPLLB_OVRD_OUT_2 2 0x91 3 0 4294967295 MPLLB_CP_PROP 0 6 MPLLB_CP_INT 7 13 RESERVED_15_14 14 15 ixDPCSSYS_CR2_SUP_DIG_ANA_RTUNE_OVRD_OUT 2 0x92 6 0 4294967295 RTUNE_COMP_RST 0 0 RTUNE_MODE 1 2 RTUNE_EN 3 3 RTUNE_VALUE 4 13 RTUNE_OVRD_EN 14 14 RESERVED_15_15 15 15 ixDPCSSYS_CR2_SUP_DIG_ANA_STAT 2 0x93 3 0 4294967295 RT_ANA_COMP_RESULT 0 0 REF_ANA_CLKDET_RESULT 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR2_SUP_DIG_ANA_BG_OVRD_OUT 2 0x94 11 0 4294967295 BG_EN 0 0 BG_FAST_START 1 1 BG_KICK_START 2 2 BG_OVRD_EN 3 3 ANA_ASYNC_RST 4 4 ANA_ASYNC_RST_OVRD_EN 5 5 REF_VREG_FAST_START 6 6 REF_VREG_FAST_START_OVRD_EN 7 7 REF_VREG_REF_SEL 8 9 REF_VREG_REF_SEL_OVRD_EN 10 10 RESERVED_15_11 11 15 ixDPCSSYS_CR2_SUP_DIG_ANA_MPLLA_PMIX_OVRD_OUT 2 0x95 5 0 4294967295 MPLLA_PMIX_SEL 0 5 MPLLA_PMIX_EN 6 6 MPLLA_PMIX_SEL_OVRD_EN 7 7 MPLLA_PMIX_EN_OVRD_EN 8 8 RESERVED_15_9 9 15 ixDPCSSYS_CR2_SUP_DIG_ANA_MPLLB_PMIX_OVRD_OUT 2 0x96 5 0 4294967295 MPLLB_PMIX_SEL 0 5 MPLLB_PMIX_EN 6 6 MPLLB_PMIX_SEL_OVRD_EN 7 7 MPLLB_PMIX_EN_OVRD_EN 8 8 RESERVED_15_9 9 15 ixDPCSSYS_CR2_LANE0_DIG_ASIC_LANE_OVRD_IN 2 0x1000 5 0 4294967295 LANE_TX2RX_SER_LB 0 0 LANE_RX2TX_PAR_LB 1 1 EN 2 2 RX_ACJTAG_EN 3 3 RESERVED_15_4 4 15 ixDPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_0 2 0x1001 12 0 4294967295 REQ 0 0 REQ_OVRD_EN 1 1 PSTATE 2 3 PSTATE_OVRD_EN 4 4 RATE 5 7 RATE_OVRD_EN 8 8 WIDTH 9 10 WIDTH_OVRD_EN 11 11 MPLLB_SEL 12 12 MPLLB_SEL_OVRD_EN 13 13 DATA_EN 14 14 DATA_EN_OVRD_EN 15 15 ixDPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_1 2 0x1002 11 0 4294967295 NYQUIST_DATA 0 0 DISABLE 1 1 BEACON_EN 2 2 EN 3 3 TX_MAIN_CURSOR 4 9 MAIN_OVRD_EN 10 10 ASYNC_DRV_EN 11 11 ASYNC_DRV_OVRD_EN 12 12 TX_VREGDRV_BYP_OVRD 13 13 TX_VREGDRV_BYP_OVRD_EN 14 14 RESERVED_15_15 15 15 ixDPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_2 2 0x1003 6 0 4294967295 TX_PRE_CURSOR 0 5 PRE_OVRD_EN 6 6 TX_POST_CURSOR 7 12 POST_OVRD_EN 13 13 HDMIMODE_EN 14 14 HDMIMODE_ENABLE_OVRD_EN 15 15 ixDPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_3 2 0x1004 15 0 4294967295 CLK_RDY 0 0 CLK_RDY_OVRD_EN 1 1 DETECT_RX_REQ 2 2 DETECT_RX_REQ_OVRD_EN 3 3 INVERT 4 4 INVERT_OVRD_EN 5 5 LPD 6 6 LPD_OVRD_EN 7 7 TX_DC_COUP_EN 8 8 TX_DC_COUP_EN_OVRD_EN 9 9 PMA_EXTENDED_FIFO_EN 10 10 PMA_EXTENDED_FIFO_EN_OVRD_EN 11 11 TX_MPHY_MODE_EN 12 12 TX_MPHY_MODE_EN_OVRD_EN 13 13 RESERVED_15_14 14 15 ixDPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_4 2 0x1005 3 0 4294967295 RESET 0 0 RESET_OVRD_EN 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_OUT 2 0x1006 5 0 4294967295 TX_ACK 0 0 EN_TX_ACK 1 1 DETRX_RESULT 2 2 EN_DETRX_RESULT 3 3 RESERVED_15_4 4 15 ixDPCSSYS_CR2_LANE0_DIG_ASIC_RX_OVRD_OUT_0 2 0x100f 9 0 4294967295 ACK 0 0 ACK_OVRD_EN 1 1 ADAPT_STS 2 3 ADAPT_STS_OVRD_EN 4 4 RX_ASYNC_DATA 5 5 RX_ASYNC_DATA_OVRD_EN 6 6 RX_SQ_WEAKKEEP_OUT 7 7 RX_SQ_WEAKKEEP_OUT_OVRD_EN 8 8 RESERVED_15_9 9 15 ixDPCSSYS_CR2_LANE0_DIG_ASIC_LANE_ASIC_IN 2 0x1010 3 0 4294967295 LANE_TX2RX_SER_LB 0 0 LANE_RX2TX_PAR_LB 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR2_LANE0_DIG_ASIC_TX_ASIC_IN_0 2 0x1011 12 0 4294967295 CLK_RDY 0 0 RESET 1 1 INVERT 2 2 DATA_EN 3 3 REQ 4 4 LPD 5 5 PSTATE 6 7 RATE 8 10 WIDTH 11 12 MPLLB_SEL 13 13 DETECT_RX_REQ 14 14 DISABLE 15 15 ixDPCSSYS_CR2_LANE0_DIG_ASIC_TX_ASIC_IN_1 2 0x1012 7 0 4294967295 BEACON_EN 0 0 TX_MAIN_CURSOR 1 6 TX_ASYNC_EN 7 7 TX_ASYNC_DATA 8 8 TX_ASYNC_DRV_EN 9 9 TX_VREGDRV_BYP 10 10 RESERVED_15_11 11 15 ixDPCSSYS_CR2_LANE0_DIG_ASIC_TX_ASIC_IN_2 2 0x1013 3 0 4294967295 TX_PRE_CURSOR 0 5 TX_POST_CURSOR 6 11 RESERVED_15_12 12 15 ixDPCSSYS_CR2_LANE0_DIG_ASIC_TX_ASIC_OUT 2 0x1014 3 0 4294967295 TX_ACK 0 0 DETRX_RESULT 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR2_LANE0_DIG_ASIC_RX_ASIC_OUT_0 2 0x101b 4 0 4294967295 ACK 0 0 VALID 1 1 ADAPT_STS 2 3 RESERVED_15_4 4 15 ixDPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_5 2 0x101d 15 0 4294967295 RPTR_EN_MASTER_LANE 0 0 RPTR_EN_MASTER_LANE_OVRD_EN 1 1 DIG_CLK_EN_OTHER_LANE 2 2 DIG_CLK_EN_OTHER_LANE_OVRD_EN 3 3 DIG_CLK_STATE_MASTER_LANE 4 4 DIG_CLK_STATE_MASTER_LANE_OVRD_EN 5 5 SHIFT_MASTER_LANE 6 6 SHIFT_MASTER_LANE_ORVD_EN 7 7 SHIFT_ACK_OTHER_LANE 8 8 SHIFT_ACK_OTHER_LANE_OVRD_EN 9 9 LANE_MASTER 10 10 LANE_MASTER_OVRD_IN_EN 11 11 TX_DWORD_CLK_SYNC_OVRD 12 12 TX_DWORD_CLK_SYNC_OVRD_EN 13 13 RESERVED_15_14 14 15 ixDPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_OUT_1 2 0x101e 11 0 4294967295 RPTR_EN_OUT 0 0 RPTR_EN_OUT_OVRD_EN 1 1 DIG_CLK_EN_OUT 2 2 DIG_CLK_EN_OUT_OVRD_EN 3 3 DIG_CLK_STATE_OUT 4 4 DIG_CLK_STATE_OUT_OVRD_EN 5 5 SHIFT_OUT 6 6 SHIFT_OUT_OVRD_EN 7 7 SHIFT_ACK_OUT 8 8 SHIFT_ACK_OUT_OVRD_EN 9 9 RESERVED_15_10 10 15 ixDPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0 2 0x1020 11 0 4294967295 TX_P0_ANA_REFGEN_EN 0 0 TX_P0_ANA_VCM_HOLD 1 1 TX_P0_ANA_CLK_EN 2 2 TX_P0_ANA_WORD_CLK_EN 3 3 TX_P0_ANA_RESET 4 4 TX_P0_ANA_SERIAL_EN 5 5 TX_P0_DIG_CLK_EN 6 6 TX_P0_DATA_EN 7 7 TX_P0_ALLOW_RXDET 8 8 TX_P0_ANA_DCC_COMP_CAL_EN 9 9 RESERVED_15_10 10 15 ixDPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S 2 0x1021 11 0 4294967295 TX_P0S_ANA_REFGEN_EN 0 0 TX_P0S_ANA_VCM_HOLD 1 1 TX_P0S_ANA_CLK_EN 2 2 TX_P0S_ANA_WORD_CLK_EN 3 3 TX_P0S_ANA_RESET 4 4 TX_P0S_ANA_SERIAL_EN 5 5 TX_P0S_DIG_CLK_EN 6 6 TX_P0S_DATA_EN 7 7 TX_P0S_ALLOW_RXDET 8 8 TX_P0S_ANA_DCC_COMP_CAL_EN 9 9 RESERVED_15_10 10 15 ixDPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1 2 0x1022 11 0 4294967295 TX_P1_ANA_REFGEN_EN 0 0 TX_P1_ANA_VCM_HOLD 1 1 TX_P1_ANA_CLK_EN 2 2 TX_P1_ANA_WORD_CLK_EN 3 3 TX_P1_ANA_RESET 4 4 TX_P1_ANA_SERIAL_EN 5 5 TX_P1_DIG_CLK_EN 6 6 TX_P1_DATA_EN 7 7 TX_P1_ALLOW_RXDET 8 8 TX_P1_ANA_DCC_COMP_CAL_EN 9 9 RESERVED_15_10 10 15 ixDPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2 2 0x1023 12 0 4294967295 TX_P2_ANA_REFGEN_EN 0 0 TX_P2_ANA_VCM_HOLD 1 1 TX_P2_ANA_CLK_EN 2 2 TX_P2_ANA_WORD_CLK_EN 3 3 TX_P2_ANA_RESET 4 4 TX_P2_ANA_SERIAL_EN 5 5 TX_P2_DIG_CLK_EN 6 6 TX_P2_DATA_EN 7 7 TX_P2_ALLOW_RXDET 8 8 TX_P2_ALLOW_VBOOST 9 9 TX_P2_ANA_DCC_COMP_CAL_EN 10 10 RESERVED_15_11 11 15 ixDPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_0 2 0x1024 2 0 4294967295 TX_REFGEN_EN_TIME 0 7 TX_CLK_EN 8 15 ixDPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_1 2 0x1025 2 0 4294967295 TX_VCM_HOLD_TIME_14_0 0 14 SKIP_TX_VCM_HOLD_WAIT 15 15 ixDPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_2 2 0x1026 2 0 4294967295 TX_VBOOST_DIS_TIME_12_0 0 12 DTB_SEL 13 15 ixDPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_3 2 0x1027 3 0 4294967295 TX_VCM_HOLD_TIME_17_15 0 2 TX_VBOOST_DIS_TIME_13 3 3 RESERVED_15_4 4 15 ixDPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_4 2 0x1028 2 0 4294967295 TX_VCM_HOLD_GS_TIME 0 14 SKIP_TX_VCM_HOLD_GS_PULSE 15 15 ixDPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_5 2 0x1029 5 0 4294967295 TX_RXDET_TIME 0 9 FAST_TX_RXDET 10 10 TX_RESET_TIME 11 12 TX_SERIAL_EN_TIME 13 14 RESERVED_15_15 15 15 ixDPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_DCC_CR_BANK_ADDR 2 0x102a 1 0 4294967295 ADDR 0 15 ixDPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_DCC_CR_BANK_DATA 2 0x102b 1 0 4294967295 DATA 0 15 ixDPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_DCC_DAC_CTRL 2 0x102c 2 0 4294967295 CTRL 0 7 RESERVED_15_8 8 15 ixDPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_DCC_DAC_RANGE 2 0x102d 2 0 4294967295 CTRL 0 1 RESERVED_15_2 2 15 ixDPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_DCC_DAC_SEL 2 0x102e 6 0 4294967295 SEL 0 2 REQ 3 3 CTRL_UPD 4 4 RANGE_UPD 5 5 BIN_HOT 6 6 RESERVED_15_7 7 15 ixDPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_DCC_DAC_ACK 2 0x102f 2 0 4294967295 ACK 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_DCC_DAC_ADDR 2 0x1030 1 0 4294967295 ADDR 0 15 ixDPCSSYS_CR2_LANE0_DIG_TX_CLK_ALIGN_TX_CTL_0 2 0x1031 4 0 4294967295 TX_NUM_2UI_SHIFTS_16B_MODE 0 3 TX_NUM_2UI_SHIFTS_20B_MODE 4 7 TX_FIFO_BYPASS 8 8 RESERVED_15_9 9 15 ixDPCSSYS_CR2_LANE0_DIG_TX_LBERT_CTL 2 0x1032 4 0 4294967295 MODE 0 3 TRIGGER_ERR 4 4 PAT0 5 14 RESERVED_15_15 15 15 ixDPCSSYS_CR2_LANE0_DIG_RX_STAT_LD_VAL_1 2 0x1080 2 0 4294967295 SC1_LD_VAL 0 14 SC1_START 15 15 ixDPCSSYS_CR2_LANE0_DIG_RX_STAT_DATA_MSK 2 0x1081 1 0 4294967295 DATA_MSK_15_0 0 15 ixDPCSSYS_CR2_LANE0_DIG_RX_STAT_MATCH_CTL0 2 0x1082 4 0 4294967295 PTTRN_MSK_CR1A_4_0 0 4 PTTRN_CR1A_4_0 5 9 DATA_MSK_19_16 10 13 SCOPE_DLY 14 15 ixDPCSSYS_CR2_LANE0_DIG_RX_STAT_MATCH_CTL1 2 0x1083 5 0 4294967295 PTTRN_CR1B_EN 0 0 PTTRN_MSK_CR1B_4_0 1 5 PTTRN_CR1B_4_0 6 10 PTTRN_CR1A_ADPT_EN 11 11 RESERVED_15_12 12 15 ixDPCSSYS_CR2_LANE0_DIG_RX_STAT_STAT_CTL0 2 0x1084 10 0 4294967295 RESERVED_0 0 0 CORR_SHFT_SEL_VGA 1 1 CORR_SHFT_SEL 2 2 CORR_SRC_SEL 3 4 CORR_MODE_EN 5 5 STAT_SHFT_SEL 6 9 STAT_SRC_SEL 10 12 STAT_RXCLK_SEL 13 13 SC_TIMER_MODE 14 14 SKIP_EN 15 15 ixDPCSSYS_CR2_LANE0_DIG_RX_STAT_STAT_CTL1 2 0x1085 13 0 4294967295 STAT_CNT_0_EN 0 0 STAT_CNT_1_EN 1 1 STAT_CNT_2_EN 2 2 STAT_CNT_3_EN 3 3 STAT_CNT_4_EN 4 4 STAT_CNT_5_EN 5 5 STAT_CNT_6_EN 6 6 RESERVED_8_7 7 8 SC_PAUSE 9 9 STAT_CLK_EN 10 10 DATA_DLY_SEL 11 12 VLD_LOSS_CLR 13 13 VLD_CTL 14 15 ixDPCSSYS_CR2_LANE0_DIG_RX_STAT_SMPL_CNT1 2 0x1086 2 0 4294967295 SMPL_CNT1 0 14 SMPL_CNT1_DONE 15 15 ixDPCSSYS_CR2_LANE0_DIG_RX_STAT_STAT_CNT_0 2 0x1087 2 0 4294967295 STAT_CNT_0 0 14 SMPL_CNT1_DONE 15 15 ixDPCSSYS_CR2_LANE0_DIG_RX_STAT_STAT_CNT_1 2 0x1088 2 0 4294967295 STAT_CNT_1 0 14 SMPL_CNT1_DONE 15 15 ixDPCSSYS_CR2_LANE0_DIG_RX_STAT_STAT_CNT_2 2 0x1089 2 0 4294967295 STAT_CNT_2 0 14 SMPL_CNT1_DONE 15 15 ixDPCSSYS_CR2_LANE0_DIG_RX_STAT_STAT_CNT_3 2 0x108a 2 0 4294967295 STAT_CNT_3 0 14 SMPL_CNT1_DONE 15 15 ixDPCSSYS_CR2_LANE0_DIG_RX_STAT_STAT_CNT_4 2 0x108b 2 0 4294967295 STAT_CNT_4 0 14 SMPL_CNT1_DONE 15 15 ixDPCSSYS_CR2_LANE0_DIG_RX_STAT_STAT_CNT_5 2 0x108c 2 0 4294967295 STAT_CNT_5 0 14 SMPL_CNT1_DONE 15 15 ixDPCSSYS_CR2_LANE0_DIG_RX_STAT_STAT_CNT_6 2 0x108d 2 0 4294967295 STAT_CNT_6 0 14 SMPL_CNT1_DONE 15 15 ixDPCSSYS_CR2_LANE0_DIG_RX_STAT_CAL_COMP_CLK_CTL 2 0x108e 3 0 4294967295 PRECHRGE_CNT 0 2 REF_DIV_CNT 3 5 RESERVED_15_6 6 15 ixDPCSSYS_CR2_LANE0_DIG_RX_STAT_MATCH_CTL2 2 0x108f 2 0 4294967295 PTTRN_CR1A_19_5 0 14 RESERVED_15_15 15 15 ixDPCSSYS_CR2_LANE0_DIG_RX_STAT_MATCH_CTL3 2 0x1090 2 0 4294967295 PTTRN_MSK_CR1A_19_5 0 14 RESERVED_15_15 15 15 ixDPCSSYS_CR2_LANE0_DIG_RX_STAT_MATCH_CTL4 2 0x1091 2 0 4294967295 PTTRN_CR1B_19_5 0 14 RESERVED_15_15 15 15 ixDPCSSYS_CR2_LANE0_DIG_RX_STAT_MATCH_CTL5 2 0x1092 2 0 4294967295 PTTRN_MSK_CR1B_19_5 0 14 RESERVED_15_15 15 15 ixDPCSSYS_CR2_LANE0_DIG_RX_STAT_STAT_CTL2 2 0x1093 4 0 4294967295 DATA_DLY_SEL_2 0 0 SCOPE_DLY_2 1 1 DISABLE_SAMPLE_COUNT 2 2 RESERVED_15_3 3 15 ixDPCSSYS_CR2_LANE0_DIG_RX_STAT_STAT_STOP 2 0x1094 2 0 4294967295 SC1_STOP 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR2_LANE0_DIG_ANA_TX_OVRD_OUT 2 0x10a0 15 0 4294967295 TX_ANA_CLK_SHIFT 0 0 TX_ANA_DATA_EN 1 1 TX_ANA_REFGEN_EN 2 2 TX_ANA_VCM_HOLD 3 3 TX_ANA_CLK_EN 4 4 TX_ANA_WORD_CLK_EN 5 5 TX_ANA_MPLLA_CLK_EN 6 6 TX_ANA_MPLLB_CLK_EN 7 7 TX_ANA_RESET 8 8 TX_ANA_SERIAL_EN 9 9 TX_ANA_DATA_RATE 10 11 RESERVED 12 12 TX_DIV4_EN 13 13 TX_RXDET_EN 14 14 TX_OVRD_EN 15 15 ixDPCSSYS_CR2_LANE0_DIG_ANA_TX_TERM_CODE_OVRD_OUT 2 0x10a1 5 0 4294967295 TX_TERM_CODE 0 9 TX_TERM_OVRD_EN 10 10 TX_DRV_SRC 11 12 TX_DRV_SRC_OVRD_EN 13 13 RESERVED_15_14 14 15 ixDPCSSYS_CR2_LANE0_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT 2 0x10a2 3 0 4294967295 TX_TERM_DN_CLK 0 0 TX_TERM_CLK_SELF_CLEAR_DISABLE 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR2_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_0 2 0x10a3 3 0 4294967295 TX_ANA_LOAD_CLK 0 0 TX_ANA_CTRL_LEG_PULL_EN_13_0 1 14 TX_EQ_OVRD_EN 15 15 ixDPCSSYS_CR2_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_1 2 0x10a4 2 0 4294967295 TX_ANA_CTRL_LEG_PULL_EN_19_14 0 5 RESERVED_15_6 6 15 ixDPCSSYS_CR2_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_2 2 0x10a5 4 0 4294967295 RESERVED 0 2 TX_ANA_CTRL_EQ_MUX_SEL 3 6 TX_ANA_CTRL_PRE 7 12 RESERVED_15_13 13 15 ixDPCSSYS_CR2_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_3 2 0x10a6 2 0 4294967295 TX_ANA_CTRL_POST 0 8 RESERVED_15_9 9 15 ixDPCSSYS_CR2_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_4 2 0x10a7 1 0 4294967295 TX_ANA_CTRL_LEG_PULL_DIR_19_4 0 15 ixDPCSSYS_CR2_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_5 2 0x10a8 2 0 4294967295 TX_ANA_CTRL_LEG_PULL_DIR_3_0 0 3 RESERVED_15_4 4 15 ixDPCSSYS_CR2_LANE0_DIG_ANA_STATUS_0 2 0x10bb 9 0 4294967295 TX_ANA_CLK_SHIFT_ACK 0 0 TX_ANA_RXDETP_RESULT 1 1 TX_ANA_RXDETM_RESULT 2 2 TX_ANA_LOOPBACK_EN 3 3 TX_ANA_CLK_LB_EN 4 4 RX_ANA_CAL_RESULT 5 5 RX_ANA_SCOPE_DATA 6 6 TX_ANA_DCC_CAL_RESULT 7 7 TX_ANA_CTRL_EQ_MUX 8 15 ixDPCSSYS_CR2_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT 2 0x10c2 8 0 4294967295 TX_ANA_DCC_CAL_RANGE 0 1 TX_ANA_DCC_CAL_RANGE_OVRD_EN 2 2 TX_ANA_DCC_CAL_COMP_EN 3 3 TX_ANA_DCC_CAL_COMP_EN_OVRD_EN 4 4 TX_ANA_DCC_CAL_CTRL 5 12 TX_ANA_DCC_CAL_CTRL_OVRD_EN 13 13 TX_ANA_DCC_CAL_CTRL_EN 14 14 TX_ANA_DCC_CAL_CTRL_EN_OVRD_EN 15 15 ixDPCSSYS_CR2_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2 2 0x10c3 5 0 4294967295 TX_ANA_DCC_CAL_CTRL_SEL 0 2 TX_ANA_DCC_CAL_CTRL_SEL_OVRD_EN 3 3 TX_ANA_DCC_CLK_COMP 4 4 TX_ANA_DCC_CLK_COMP_OVRD_EN 5 5 RESERVED_15_6 6 15 ixDPCSSYS_CR2_LANE0_DIG_ANA_TX_OVRD_OUT_2 2 0x10c4 6 0 4294967295 TX_ANA_FAST_START 0 0 TX_ANA_FAST_START_OVRD_EN 1 1 TX_CLK_LB_EN 2 2 TX_CLK_LB_EN_OVRD_EN 3 3 TX_ACJTAG_EN 4 4 RESERVED_15_5 5 15 ixDPCSSYS_CR2_LANE0_ANA_TX_OVRD_MEAS 2 0x10e0 9 0 4294967295 OVRD_CLK_SHIFT 0 0 CLK_SHIFT_REG 0 0 MEAS_ATB_CAL_MUX 0 0 MEAS_ATB_CAL_COMP 0 0 OVRD_VCM_HOLD 0 0 VCM_HOLD_REG 0 0 PULL_UP_REG 0 0 PULL_DN_REG 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR2_LANE0_ANA_TX_PWR_OVRD 2 0x10e1 9 0 4294967295 OVRD_TX_LOOPBACK 0 0 LOOPBACK_EN_REG 0 0 REFGEN_EN_REG 0 0 CLK_DIV_EN_REG 0 0 DATA_EN_REG_INT 0 0 CLK_EN_REG 0 0 SERIAL_EN_REG 0 0 OVRD_EN 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR2_LANE0_ANA_TX_ALT_BUS 2 0x10e2 6 0 4294967295 DRV_SOURCE_REG 0 0 OVRD_ALT_BUS 0 0 ATB_S_ENABLE 0 0 TX_ALT_RINGO 0 0 JTAG_DATA_REG 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR2_LANE0_ANA_TX_ATB1 2 0x10e3 9 0 4294967295 MEAS_ATB_GD 0 0 MEAS_ATB_VDDH 0 0 OVERRIDE_RXDETREF 0 0 MEAS_ATB_VPTX 0 0 OVERRIDE_REGREF 0 0 MEAS_ATB_VREG_DRV 0 0 MEAS_ATB_VREG 0 0 MEAS_ATB_VPH_HALF 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR2_LANE0_ANA_TX_ATB2 2 0x10e4 9 0 4294967295 MEAS_ATB_VCM 0 0 MEAS_ATB_CAL_VDAC_CM 0 0 MEAS_ATB_CAL_VDAC_DIFF 0 0 MEAS_ATB_TXM 0 0 MEAS_ATB_TXP 0 0 MEAS_ATB_RXDETREF 0 0 LFPS_HIGH_PRIORITY 0 0 OSC_DIV4_EN 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR2_LANE0_ANA_TX_DCC_DAC 2 0x10e5 2 0 4294967295 DCC_DAC_REG 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR2_LANE0_ANA_TX_DCC_CTRL1 2 0x10e6 7 0 4294967295 NC0 0 0 OVRD_DCC_DAC_CTRL_SEL 0 0 DCC_DAC_CTRL_SEL_REG 0 0 OVRD_DCC_DAC_CTRL_EN 0 0 DCC_DAC_CTRL_EN_REG 0 0 OVRD_DCC_DAC_REG 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR2_LANE0_ANA_TX_TERM_CODE 2 0x10e7 2 0 4294967295 TERM_CODE_REG_70 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR2_LANE0_ANA_TX_TERM_CODE_CTRL 2 0x10e8 8 0 4294967295 VREG_BOOST_1 0 0 OVRD_UPDATE_TERM 0 0 UPDATE_TERM_REG 0 0 OVRD_RESET_TERM 0 0 RESET_TERM_REG 0 0 OVRD_TERM_CODE 0 0 TERM_CODE_REG_98 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR2_LANE0_ANA_TX_OVRD_CLK 2 0x10e9 9 0 4294967295 VREG_BOOST_0 0 0 CLK_LB_EN_REG 0 0 OVRD_LB_EN 0 0 MPLLB_CLK_EN_REG 0 0 MPLLA_CLK_EN_REG 0 0 OVRD_MPLLAB_EN 0 0 WORD_CLK_EN_REG 0 0 OVRD_WORD_CLK_EN 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR2_LANE0_ANA_TX_MISC1 2 0x10ea 8 0 4294967295 MEAS_ATB_CAL_CLK_ALIGN 0 0 OVRD_DCC_DAC_CTRL_RANGE 0 0 DCC_DAC_CTRL_RANGE_REG 0 0 OVRD_VREF_SEL 0 0 VREF_SEL_REG 0 0 FORCE_ATB_TXM 0 0 FORCE_ATB_TXP 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR2_LANE0_ANA_TX_MISC2 2 0x10eb 8 0 4294967295 TX_PEAKING_LVL 0 0 VREG_CP_GAIN_CTRL 0 0 TX_SLEW_EN 0 0 EN_INV_POST 0 0 EN_INV_PRE 0 0 TX_VREG_EN_BYP 0 0 TX_VDRIVER_PULLDN_EN 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR2_LANE0_ANA_TX_MISC3 2 0x10ec 4 0 4294967295 TX_VREG_OVRD_RING_CTRL 0 0 TX_DCC_LOWV 0 0 NC7_2 2 7 RESERVED_15_8 8 15 ixDPCSSYS_CR2_LANE0_ANA_TX_RESERVED2 2 0x10ed 2 0 4294967295 NC7_0 0 7 RESERVED_15_8 8 15 ixDPCSSYS_CR2_LANE0_ANA_TX_RESERVED3 2 0x10ee 2 0 4294967295 NC7_0 0 7 RESERVED_15_8 8 15 ixDPCSSYS_CR2_LANE0_ANA_TX_RESERVED4 2 0x10ef 2 0 4294967295 NC7_0 0 7 RESERVED_15_8 8 15 ixDPCSSYS_CR2_LANE1_DIG_ASIC_LANE_OVRD_IN 2 0x1100 5 0 4294967295 LANE_TX2RX_SER_LB 0 0 LANE_RX2TX_PAR_LB 1 1 EN 2 2 RX_ACJTAG_EN 3 3 RESERVED_15_4 4 15 ixDPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_0 2 0x1101 12 0 4294967295 REQ 0 0 REQ_OVRD_EN 1 1 PSTATE 2 3 PSTATE_OVRD_EN 4 4 RATE 5 7 RATE_OVRD_EN 8 8 WIDTH 9 10 WIDTH_OVRD_EN 11 11 MPLLB_SEL 12 12 MPLLB_SEL_OVRD_EN 13 13 DATA_EN 14 14 DATA_EN_OVRD_EN 15 15 ixDPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_1 2 0x1102 11 0 4294967295 NYQUIST_DATA 0 0 DISABLE 1 1 BEACON_EN 2 2 EN 3 3 TX_MAIN_CURSOR 4 9 MAIN_OVRD_EN 10 10 ASYNC_DRV_EN 11 11 ASYNC_DRV_OVRD_EN 12 12 TX_VREGDRV_BYP_OVRD 13 13 TX_VREGDRV_BYP_OVRD_EN 14 14 RESERVED_15_15 15 15 ixDPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_2 2 0x1103 6 0 4294967295 TX_PRE_CURSOR 0 5 PRE_OVRD_EN 6 6 TX_POST_CURSOR 7 12 POST_OVRD_EN 13 13 HDMIMODE_EN 14 14 HDMIMODE_ENABLE_OVRD_EN 15 15 ixDPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_3 2 0x1104 15 0 4294967295 CLK_RDY 0 0 CLK_RDY_OVRD_EN 1 1 DETECT_RX_REQ 2 2 DETECT_RX_REQ_OVRD_EN 3 3 INVERT 4 4 INVERT_OVRD_EN 5 5 LPD 6 6 LPD_OVRD_EN 7 7 TX_DC_COUP_EN 8 8 TX_DC_COUP_EN_OVRD_EN 9 9 PMA_EXTENDED_FIFO_EN 10 10 PMA_EXTENDED_FIFO_EN_OVRD_EN 11 11 TX_MPHY_MODE_EN 12 12 TX_MPHY_MODE_EN_OVRD_EN 13 13 RESERVED_15_14 14 15 ixDPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_4 2 0x1105 3 0 4294967295 RESET 0 0 RESET_OVRD_EN 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_OUT 2 0x1106 5 0 4294967295 TX_ACK 0 0 EN_TX_ACK 1 1 DETRX_RESULT 2 2 EN_DETRX_RESULT 3 3 RESERVED_15_4 4 15 ixDPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_0 2 0x1107 11 0 4294967295 REQ 0 0 REQ_OVRD_EN 1 1 DATA_EN 2 2 DATA_EN_OVRD_EN 3 3 PSTATE 4 5 PSTATE_OVRD_EN 6 6 RATE 7 8 RATE_OVRD_EN 9 9 WIDTH 10 11 WIDTH_OVRD_EN 12 12 RESERVED_15_13 13 15 ixDPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_1 2 0x1108 5 0 4294967295 RX_REF_LD_VAL_5_0 0 5 RX_CDR_VCO_LOWFREQ 6 6 EN 7 7 RX_REF_LD_VAL_6 8 8 RESERVED_15_9 9 15 ixDPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_2 2 0x1109 3 0 4294967295 RX_VCO_LD_VAL 0 12 EN 13 13 RESERVED_15_14 14 15 ixDPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_3 2 0x110a 11 0 4294967295 CDR_TRACK_EN 0 0 CDR_TRACK_EN_OVRD_EN 1 1 CDR_SSC_EN 2 2 CDR_SSC_EN_OVRD_EN 3 3 ALIGN_EN 4 4 ALIGN_EN_OVRD_EN 5 5 CLK_SHIFT 6 6 CLK_SHIFT_OVRD_EN 7 7 DISABLE 8 8 DISABLE_OVRD_EN 9 9 RESERVED_15_10 10 15 ixDPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_4 2 0x110b 11 0 4294967295 LPD 0 0 LPD_OVRD_EN 1 1 INVERT 2 2 INVERT_OVRD_EN 3 3 ADAPT_AFE_EN 4 4 ADAPT_DFE_EN 5 5 ADPT_OVRD_EN 6 6 TERM_EN 7 7 TERM_ACDC 8 8 TERM_OVRD_EN 9 9 RESERVED_15_10 10 15 ixDPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_5 2 0x110c 3 0 4294967295 RESET 0 0 RESET_OVRD_EN 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0 2 0x110d 4 0 4294967295 EQ_ATT_LVL 0 2 EQ_AFE_GAIN 3 6 RESERVED 7 10 EQ_CTLE_BOOST 11 15 ixDPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1 2 0x110e 3 0 4294967295 EQ_DFE_TAP2 0 6 EQ_DFE_TAP1 7 14 EQ_OVRD_EN 15 15 ixDPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_OUT_0 2 0x110f 9 0 4294967295 ACK 0 0 ACK_OVRD_EN 1 1 ADAPT_STS 2 3 ADAPT_STS_OVRD_EN 4 4 RX_ASYNC_DATA 5 5 RX_ASYNC_DATA_OVRD_EN 6 6 RX_SQ_WEAKKEEP_OUT 7 7 RX_SQ_WEAKKEEP_OUT_OVRD_EN 8 8 RESERVED_15_9 9 15 ixDPCSSYS_CR2_LANE1_DIG_ASIC_LANE_ASIC_IN 2 0x1110 3 0 4294967295 LANE_TX2RX_SER_LB 0 0 LANE_RX2TX_PAR_LB 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR2_LANE1_DIG_ASIC_TX_ASIC_IN_0 2 0x1111 12 0 4294967295 CLK_RDY 0 0 RESET 1 1 INVERT 2 2 DATA_EN 3 3 REQ 4 4 LPD 5 5 PSTATE 6 7 RATE 8 10 WIDTH 11 12 MPLLB_SEL 13 13 DETECT_RX_REQ 14 14 DISABLE 15 15 ixDPCSSYS_CR2_LANE1_DIG_ASIC_TX_ASIC_IN_1 2 0x1112 7 0 4294967295 BEACON_EN 0 0 TX_MAIN_CURSOR 1 6 TX_ASYNC_EN 7 7 TX_ASYNC_DATA 8 8 TX_ASYNC_DRV_EN 9 9 TX_VREGDRV_BYP 10 10 RESERVED_15_11 11 15 ixDPCSSYS_CR2_LANE1_DIG_ASIC_TX_ASIC_IN_2 2 0x1113 3 0 4294967295 TX_PRE_CURSOR 0 5 TX_POST_CURSOR 6 11 RESERVED_15_12 12 15 ixDPCSSYS_CR2_LANE1_DIG_ASIC_TX_ASIC_OUT 2 0x1114 3 0 4294967295 TX_ACK 0 0 DETRX_RESULT 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR2_LANE1_DIG_ASIC_RX_ASIC_IN_0 2 0x1115 13 0 4294967295 RESET 0 0 INVERT 1 1 DATA_EN 2 2 REQ 3 3 LPD 4 4 PSTATE 5 6 RATE 7 8 WIDTH 9 10 RESERVED 11 11 ADAPT_AFE_EN 12 12 ADAPT_DFE_EN 13 13 CDR_TRACK_EN 14 14 RESERVED_15_15 15 15 ixDPCSSYS_CR2_LANE1_DIG_ASIC_RX_ASIC_IN_1 2 0x1116 7 0 4294967295 CDR_SSC_EN 0 0 ALIGN_EN 1 1 CLK_SHIFT 2 2 DISABLE 3 3 RX_TERM_EN 4 4 RX_TERM_ACDC 5 5 RESERVED_15_6 6 15 ixDPCSSYS_CR2_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0 2 0x1117 4 0 4294967295 EQ_ATT_LVL 0 2 EQ_AFE_GAIN 3 6 RESERVED 7 10 EQ_CTLE_BOOST 11 15 ixDPCSSYS_CR2_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_1 2 0x1118 3 0 4294967295 EQ_DFE_TAP2 0 6 EQ_DFE_TAP1 7 14 RESERVED_15_15 15 15 ixDPCSSYS_CR2_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0 2 0x1119 3 0 4294967295 RX_CDR_VCO_LOWFREQ 0 0 RX_REF_LD_VAL 1 7 RESERVED_15_8 8 15 ixDPCSSYS_CR2_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1 2 0x111a 2 0 4294967295 RX_VCO_LD_VAL 0 12 RESERVED_15_13 13 15 ixDPCSSYS_CR2_LANE1_DIG_ASIC_RX_ASIC_OUT_0 2 0x111b 4 0 4294967295 ACK 0 0 VALID 1 1 ADAPT_STS 2 3 RESERVED_15_4 4 15 ixDPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_6 2 0x111c 10 0 4294967295 RX_PWM_CLK_SEL 0 1 RX_PWM_CLK_SEL_OVRD_EN 2 2 RX_TERM_LCC_ON 3 3 RX_TERM_LS_ON 4 4 RX_TERM_LS_LCC_ON_OVRD_EN 5 5 RX_TERM_CTL 6 7 RX_TERM_CTL_OVRD_EN 8 8 RX_PWM_EN 9 9 RX_PWM_EN_OVRD_EN 10 10 RESERVED_15_11 11 15 ixDPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_5 2 0x111d 15 0 4294967295 RPTR_EN_MASTER_LANE 0 0 RPTR_EN_MASTER_LANE_OVRD_EN 1 1 DIG_CLK_EN_OTHER_LANE 2 2 DIG_CLK_EN_OTHER_LANE_OVRD_EN 3 3 DIG_CLK_STATE_MASTER_LANE 4 4 DIG_CLK_STATE_MASTER_LANE_OVRD_EN 5 5 SHIFT_MASTER_LANE 6 6 SHIFT_MASTER_LANE_ORVD_EN 7 7 SHIFT_ACK_OTHER_LANE 8 8 SHIFT_ACK_OTHER_LANE_OVRD_EN 9 9 LANE_MASTER 10 10 LANE_MASTER_OVRD_IN_EN 11 11 TX_DWORD_CLK_SYNC_OVRD 12 12 TX_DWORD_CLK_SYNC_OVRD_EN 13 13 RESERVED_15_14 14 15 ixDPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_OUT_1 2 0x111e 11 0 4294967295 RPTR_EN_OUT 0 0 RPTR_EN_OUT_OVRD_EN 1 1 DIG_CLK_EN_OUT 2 2 DIG_CLK_EN_OUT_OVRD_EN 3 3 DIG_CLK_STATE_OUT 4 4 DIG_CLK_STATE_OUT_OVRD_EN 5 5 SHIFT_OUT 6 6 SHIFT_OUT_OVRD_EN 7 7 SHIFT_ACK_OUT 8 8 SHIFT_ACK_OUT_OVRD_EN 9 9 RESERVED_15_10 10 15 ixDPCSSYS_CR2_LANE1_DIG_ASIC_OCLA 2 0x111f 3 0 4294967295 RX_DWORD_OCLA_CLK_EN 0 0 RX_DWORD_OCLA_DATA_EN 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0 2 0x1120 11 0 4294967295 TX_P0_ANA_REFGEN_EN 0 0 TX_P0_ANA_VCM_HOLD 1 1 TX_P0_ANA_CLK_EN 2 2 TX_P0_ANA_WORD_CLK_EN 3 3 TX_P0_ANA_RESET 4 4 TX_P0_ANA_SERIAL_EN 5 5 TX_P0_DIG_CLK_EN 6 6 TX_P0_DATA_EN 7 7 TX_P0_ALLOW_RXDET 8 8 TX_P0_ANA_DCC_COMP_CAL_EN 9 9 RESERVED_15_10 10 15 ixDPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S 2 0x1121 11 0 4294967295 TX_P0S_ANA_REFGEN_EN 0 0 TX_P0S_ANA_VCM_HOLD 1 1 TX_P0S_ANA_CLK_EN 2 2 TX_P0S_ANA_WORD_CLK_EN 3 3 TX_P0S_ANA_RESET 4 4 TX_P0S_ANA_SERIAL_EN 5 5 TX_P0S_DIG_CLK_EN 6 6 TX_P0S_DATA_EN 7 7 TX_P0S_ALLOW_RXDET 8 8 TX_P0S_ANA_DCC_COMP_CAL_EN 9 9 RESERVED_15_10 10 15 ixDPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1 2 0x1122 11 0 4294967295 TX_P1_ANA_REFGEN_EN 0 0 TX_P1_ANA_VCM_HOLD 1 1 TX_P1_ANA_CLK_EN 2 2 TX_P1_ANA_WORD_CLK_EN 3 3 TX_P1_ANA_RESET 4 4 TX_P1_ANA_SERIAL_EN 5 5 TX_P1_DIG_CLK_EN 6 6 TX_P1_DATA_EN 7 7 TX_P1_ALLOW_RXDET 8 8 TX_P1_ANA_DCC_COMP_CAL_EN 9 9 RESERVED_15_10 10 15 ixDPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2 2 0x1123 12 0 4294967295 TX_P2_ANA_REFGEN_EN 0 0 TX_P2_ANA_VCM_HOLD 1 1 TX_P2_ANA_CLK_EN 2 2 TX_P2_ANA_WORD_CLK_EN 3 3 TX_P2_ANA_RESET 4 4 TX_P2_ANA_SERIAL_EN 5 5 TX_P2_DIG_CLK_EN 6 6 TX_P2_DATA_EN 7 7 TX_P2_ALLOW_RXDET 8 8 TX_P2_ALLOW_VBOOST 9 9 TX_P2_ANA_DCC_COMP_CAL_EN 10 10 RESERVED_15_11 11 15 ixDPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_0 2 0x1124 2 0 4294967295 TX_REFGEN_EN_TIME 0 7 TX_CLK_EN 8 15 ixDPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_1 2 0x1125 2 0 4294967295 TX_VCM_HOLD_TIME_14_0 0 14 SKIP_TX_VCM_HOLD_WAIT 15 15 ixDPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_2 2 0x1126 2 0 4294967295 TX_VBOOST_DIS_TIME_12_0 0 12 DTB_SEL 13 15 ixDPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_3 2 0x1127 3 0 4294967295 TX_VCM_HOLD_TIME_17_15 0 2 TX_VBOOST_DIS_TIME_13 3 3 RESERVED_15_4 4 15 ixDPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_4 2 0x1128 2 0 4294967295 TX_VCM_HOLD_GS_TIME 0 14 SKIP_TX_VCM_HOLD_GS_PULSE 15 15 ixDPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_5 2 0x1129 5 0 4294967295 TX_RXDET_TIME 0 9 FAST_TX_RXDET 10 10 TX_RESET_TIME 11 12 TX_SERIAL_EN_TIME 13 14 RESERVED_15_15 15 15 ixDPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_DCC_CR_BANK_ADDR 2 0x112a 1 0 4294967295 ADDR 0 15 ixDPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_DCC_CR_BANK_DATA 2 0x112b 1 0 4294967295 DATA 0 15 ixDPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_DCC_DAC_CTRL 2 0x112c 2 0 4294967295 CTRL 0 7 RESERVED_15_8 8 15 ixDPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_DCC_DAC_RANGE 2 0x112d 2 0 4294967295 CTRL 0 1 RESERVED_15_2 2 15 ixDPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_DCC_DAC_SEL 2 0x112e 6 0 4294967295 SEL 0 2 REQ 3 3 CTRL_UPD 4 4 RANGE_UPD 5 5 BIN_HOT 6 6 RESERVED_15_7 7 15 ixDPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_DCC_DAC_ACK 2 0x112f 2 0 4294967295 ACK 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_DCC_DAC_ADDR 2 0x1130 1 0 4294967295 ADDR 0 15 ixDPCSSYS_CR2_LANE1_DIG_TX_CLK_ALIGN_TX_CTL_0 2 0x1131 4 0 4294967295 TX_NUM_2UI_SHIFTS_16B_MODE 0 3 TX_NUM_2UI_SHIFTS_20B_MODE 4 7 TX_FIFO_BYPASS 8 8 RESERVED_15_9 9 15 ixDPCSSYS_CR2_LANE1_DIG_TX_LBERT_CTL 2 0x1132 4 0 4294967295 MODE 0 3 TRIGGER_ERR 4 4 PAT0 5 14 RESERVED_15_15 15 15 ixDPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0 2 0x1140 12 0 4294967295 RX_P0_ANA_AFE_EN 0 0 RX_P0_ANA_CLK_VREG_EN 1 1 RESERVED_1 2 2 RX_P0_ANA_CLK_EN 3 3 RESERVED_0 4 4 RX_P0_ANA_DESER_EN 5 5 RX_P0_ANA_CDR_EN 6 6 RX_P0_VCO_FREQ_RST 7 7 RX_P0_VCO_CAL_RST 8 8 RX_P0_VCO_CONTCAL_EN 9 9 RX_P0_DIG_CLK_EN 10 10 RESERVED_15_11 11 15 ixDPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S 2 0x1141 12 0 4294967295 RX_P0S_ANA_AFE_EN 0 0 RX_P0S_ANA_CLK_VREG_EN 1 1 RESERVED_2 2 2 RX_P0S_ANA_CLK_EN 3 3 RESERVED_4 4 4 RX_P0S_ANA_DESER_EN 5 5 RX_P0S_ANA_CDR_EN 6 6 RX_P0S_VCO_FREQ_RST 7 7 RX_P0S_VCO_CAL_RST 8 8 RX_P0S_VCO_CONTCAL_EN 9 9 RX_P0S_DIG_CLK_EN 10 10 RESERVED_15_11 11 15 ixDPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1 2 0x1142 12 0 4294967295 RX_P1_ANA_AFE_EN 0 0 RX_P1_ANA_CLK_VREG_EN 1 1 RESERVED_2 2 2 RX_P1_ANA_CLK_EN 3 3 RESERVED_4 4 4 RX_P1_ANA_DESER_EN 5 5 RX_P1_ANA_CDR_EN 6 6 RX_P1_VCO_FREQ_RST 7 7 RX_P1_VCO_CAL_RST 8 8 RX_P1_VCO_CONTCAL_EN 9 9 RX_P1_DIG_CLK_EN 10 10 RESERVED_15_11 11 15 ixDPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2 2 0x1143 12 0 4294967295 RX_P2_ANA_AFE_EN 0 0 RX_P2_ANA_CLK_VREG_EN 1 1 RESERVED_2 2 2 RX_P2_ANA_CLK_EN 3 3 RESERVED_4 4 4 RX_P2_ANA_DESER_EN 5 5 RX_P2_ANA_CDR_EN 6 6 RX_P2_VCO_FREQ_RST 7 7 RX_P2_VCO_CAL_RST 8 8 RX_P2_VCO_CONTCAL_EN 9 9 RX_P2_DIG_CLK_EN 10 10 RESERVED_15_11 11 15 ixDPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1 2 0x1145 5 0 4294967295 RX_AFE_EN_TIME 0 5 FAST_RX_AFE_EN 6 6 RX_VREG_EN_TIME 7 12 FAST_RX_VREG_EN 13 13 RESERVED_15_14 14 15 ixDPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_2 2 0x1146 4 0 4294967295 RX_CLK_EN_TIME 0 5 FAST_RX_CLK_EN 6 6 RX_FAST_START_TIME 7 10 RESERVED_15_11 11 15 ixDPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_3 2 0x1147 5 0 4294967295 RX_RATE_TIME 0 1 RSVD_3_7_2 2 7 RX_CDR_EN_TIME 8 11 RX_DESER_EN_TIME 12 13 RX_DESER_DIS_TIME 14 15 ixDPCSSYS_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0 2 0x1148 8 0 4294967295 INT_GAIN_CAL_FIXED_CNT 0 4 INT_GAIN_CAL_FIXED_CNT_EN 5 5 INT_GAIN_CAL_CNT_SHIFT 6 8 INT_GAIN_CAL_BOUNCE_CNT 9 11 DISABLE_BIN_HOLD 12 12 DISABLE_INT_GAIN_HOLD 13 13 DISABLE_COARSE_CALDONE 14 14 RESERVED_15_15 15 15 ixDPCSSYS_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1 2 0x1149 7 0 4294967295 RX_VCO_OVRD_SEL 0 0 RX_VCO_FREQ_RST 1 1 RX_VCO_CAL_RST 2 2 RX_VCO_CONTCAL_EN 3 3 DISABLE_INT_CAL_MODE 4 4 DPLL_CAL_UG 5 8 DTB_SEL 9 15 ixDPCSSYS_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2 2 0x114a 4 0 4294967295 FREQ_TUNE_START_VAL 0 9 FREQ_TUNE_CAL_STEPS 10 13 SKIP_RX_VCO_FREQ_TUNE_CAL 14 14 SKIP_RX_VCO_CAL 15 15 ixDPCSSYS_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0 2 0x114b 4 0 4294967295 RX_VCO_STARTUP_TIME 0 6 RX_VCO_UPDATE_TIME 7 10 RX_VCO_CNTR_PWRUP_TIME 11 14 FAST_RX_VCO_WAIT 15 15 ixDPCSSYS_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1 2 0x114c 2 0 4294967295 RX_VCO_CNTR_SETTLE_TIME 0 2 RESERVED_15_3 3 15 ixDPCSSYS_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0 2 0x114d 6 0 4294967295 RX_ANA_CDR_FREQ_TUNE 0 9 RX_ANA_VCO_CNTR_PD 10 10 RX_ANA_VCO_CNTR_EN 11 11 RX_ANA_CDR_STARTUP 12 12 RX_ANA_CDR_VCO_EN 13 13 RESERVED_15_14 14 15 ixDPCSSYS_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1 2 0x114e 7 0 4294967295 RX_VCO_FSM_STATE 0 3 RX_VCO_FREQ_RST 4 4 RX_VCO_CAL_RST 5 5 RX_VCO_CONTCAL_EN 6 6 RX_VCO_CAL_DONE 7 7 DPLL_FREQ_RST 8 8 RESERVED_15_9 9 15 ixDPCSSYS_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_2 2 0x114f 4 0 4294967295 VCO_CNTR_FINAL 0 12 VCOCLK_TOO_FAST 13 13 RX_VCO_CORRECT 14 14 RX_VCO_UP 15 15 ixDPCSSYS_CR2_LANE1_DIG_RX_RX_ALIGN_XAUI_COMM_MASK 2 0x1150 2 0 4294967295 XAUI_COMM_MASK 0 9 RESERVED_15_10 10 15 ixDPCSSYS_CR2_LANE1_DIG_RX_LBERT_CTL 2 0x1151 3 0 4294967295 MODE 0 3 SYNC 4 4 RESERVED_15_5 5 15 ixDPCSSYS_CR2_LANE1_DIG_RX_LBERT_ERR 2 0x1152 2 0 4294967295 COUNT 0 14 OV14 15 15 ixDPCSSYS_CR2_LANE1_DIG_RX_CDR_CDR_CTL_0 2 0x1153 7 0 4294967295 PHDET_EN 0 1 PHDET_EDGE 2 3 PHDET_POL 4 4 PHDET_EN_PR_MODE 5 5 ALWAYS_REALIGN 6 6 DTB_SEL 7 10 RESERVED_15_11 11 15 ixDPCSSYS_CR2_LANE1_DIG_RX_CDR_CDR_CTL_1 2 0x1154 2 0 4294967295 SSC_OFF_CNT0 0 9 SSC_OFF_CNT1 10 15 ixDPCSSYS_CR2_LANE1_DIG_RX_CDR_CDR_CTL_2 2 0x1155 2 0 4294967295 SSC_ON_CNT0 0 8 SSC_ON_CNT1 9 15 ixDPCSSYS_CR2_LANE1_DIG_RX_CDR_CDR_CTL_3 2 0x1156 6 0 4294967295 SSC_OFF_PHUG0 0 2 SSC_OFF_PHUG1 3 5 SSC_OFF_FRUG0 6 8 OVRD_DPLL_GAIN 9 9 PHUG_OVRD_VALUE 10 12 FRUG_OVRD_VALUE 13 15 ixDPCSSYS_CR2_LANE1_DIG_RX_CDR_CDR_CTL_4 2 0x1157 6 0 4294967295 SSC_OFF_FRUG1 0 2 SSC_ON_FRUG0 3 5 SSC_ON_FRUG1 6 8 SSC_ON_PHUG0 9 11 SSC_ON_PHUG1 12 14 RESERVED_15_15 15 15 ixDPCSSYS_CR2_LANE1_DIG_RX_CDR_STAT 2 0x1158 3 0 4294967295 PHUG_VALUE 0 2 FRUG_VALUE 3 5 RESERVED_15_6 6 15 ixDPCSSYS_CR2_LANE1_DIG_RX_DPLL_FREQ 2 0x1159 2 0 4294967295 VAL 0 13 RESERVED_15_14 14 15 ixDPCSSYS_CR2_LANE1_DIG_RX_DPLL_FREQ_BOUND_0 2 0x115a 3 0 4294967295 FREQ_BOUND_EN 0 0 UPPER_FREQ_BOUND 1 10 RESERVED_15_11 11 15 ixDPCSSYS_CR2_LANE1_DIG_RX_DPLL_FREQ_BOUND_1 2 0x115b 2 0 4294967295 LOWER_FREQ_BOUND 0 9 RESERVED_15_10 10 15 ixDPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_0 2 0x1160 4 0 4294967295 N_TOP_ASM1 0 9 N_TGG_ASM1 10 13 START_ASM1 14 14 ADPT_CLK_DIV4_EN 15 15 ixDPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1 2 0x1161 5 0 4294967295 N_WAIT_ASM1 0 6 FAST_AFE_DFE_SETTLE 7 7 CTLE_POLE_OVRD_VAL 8 10 CTLE_POLE_OVRD_EN 11 11 RESERVED_15_12 12 15 ixDPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_2 2 0x1162 3 0 4294967295 TGG_PTTRN_0 0 4 TGG_PTTRN_1 5 9 RESERVED_15_10 10 15 ixDPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3 2 0x1163 8 0 4294967295 CTLE_EN 0 4 VGA_EN 5 5 ATT_EN 6 6 DFE_EN 7 11 EYEHE_EN 12 12 EYEHO_EN 13 13 TGG_EN 14 14 ESL_TWICE_DSL 15 15 ixDPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_4 2 0x1164 4 0 4294967295 CTLE_TH 0 3 VGA_TH 4 7 DFE1_TH 8 11 DFE2_TH 12 15 ixDPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_5 2 0x1165 4 0 4294967295 DFE3_TH 0 3 DFE4_TH 4 7 DFE5_TH 8 11 TH_OFFSET 12 15 ixDPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6 2 0x1166 6 0 4294967295 CTLE_MU 0 2 VGA_MU 3 5 ATT_MU 6 8 VGA_SAT_CNT 9 11 VGA_SAT_CNT_STICKY 12 12 ATT_LOW_TH 13 15 ixDPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_7 2 0x1167 4 0 4294967295 VGA_MIN_SAT 0 4 VGA_LEV_HIGH 5 9 VGA_LEV_LOW 10 14 RESERVED_15_15 15 15 ixDPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8 2 0x1168 6 0 4294967295 DFE1_MU 0 2 DFE2_MU 3 5 DFE3_MU 6 8 DFE4_MU 9 11 DFE5_MU 12 14 RESERVED_15_15 15 15 ixDPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_9 2 0x1169 2 0 4294967295 ERR_SLE_ADPT_INIT 0 7 ERR_SLO_ADPT_INIT 8 15 ixDPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG 2 0x116a 6 0 4294967295 RST_ADPT_ATT 0 0 RST_ADPT_VGA 1 1 RST_ADPT_CTLE_BOOST 2 2 RST_ADPT_CTLE_POLE 3 3 RST_ADPT_TAP1 4 4 RESERVED_15_5 5 15 ixDPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ATT_STATUS 2 0x116b 3 0 4294967295 ATT_ADPT_CODE 0 7 ASM1_DON 8 8 RESERVED_15_9 9 15 ixDPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_VGA_STATUS 2 0x116c 3 0 4294967295 VGA_ADPT_CODE 0 9 ASM1_DONE 10 10 RESERVED_15_11 11 15 ixDPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_CTLE_STATUS 2 0x116d 4 0 4294967295 CTLE_BOOST_ADPT_CODE 0 9 CTLE_POLE_ADPT_CODE 10 12 ASM1_DONE 13 13 RESERVED_15_14 14 15 ixDPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_DFE_TAP1_STATUS 2 0x116e 3 0 4294967295 DFE_TAP1_ADPT_CODE 0 12 ASM1_DONE 13 13 RESERVED_15_14 14 15 ixDPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_DFE_TAP2_STATUS 2 0x116f 3 0 4294967295 DFE_TAP2_ADPT_CODE 0 11 ASM1_DONE 12 12 RESERVED_15_13 13 15 ixDPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_DFE_TAP3_STATUS 2 0x1170 3 0 4294967295 DFE_TAP3_ADPT_CODE 0 11 ASM1_DONE 12 12 RESERVED_15_13 13 15 ixDPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_DFE_TAP4_STATUS 2 0x1171 3 0 4294967295 DFE_TAP4_ADPT_CODE 0 11 ASM1_DONE 12 12 RESERVED_15_13 13 15 ixDPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_DFE_TAP5_STATUS 2 0x1172 3 0 4294967295 DFE_TAP5_ADPT_CODE 0 11 ASM1_DONE 12 12 RESERVED_15_13 13 15 ixDPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_DFE_DATA_EVEN_VDAC_OFST 2 0x1173 2 0 4294967295 DFE_DATA_EVEN_VDAC_OFST 0 7 RESERVED_15_8 8 15 ixDPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_DFE_DATA_ODD_VDAC_OFST 2 0x1174 2 0 4294967295 DFE_DATA_ODD_VDAC_OFST 0 7 RESERVED_15_8 8 15 ixDPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN 2 0x1175 2 0 4294967295 RX_ANA_SLICER_CTRL_E 0 3 RESERVED_15_4 4 15 ixDPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD 2 0x1176 2 0 4294967295 RX_ANA_SLICER_CTRL_O 0 3 RESERVED_15_4 4 15 ixDPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST 2 0x1177 2 0 4294967295 DFE_ERROR_EVEN_VDAC_OFST 0 7 RESERVED_15_8 8 15 ixDPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST 2 0x1178 2 0 4294967295 DFE_ERROR_ODD_VDAC_OFST 0 7 RESERVED_15_8 8 15 ixDPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL 2 0x1179 2 0 4294967295 E_SLO_LVL 0 7 E_SLE_LVL 8 15 ixDPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_RESET 2 0x117a 2 0 4294967295 RESET_ASM1 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1 2 0x117b 4 0 4294967295 DFE_T1_IDAC 0 4 DFE_T2_IDAC 5 9 DCC_START_IDAC 10 14 RESERVED_15_15 15 15 ixDPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2 2 0x117c 3 0 4294967295 DFE_DAT_EVEN_VDAC 0 4 DFE_DAT_ODD_VDAC 5 9 RESERVED_15_10 10 15 ixDPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3 2 0x117d 3 0 4294967295 DFE_ERR_EVEN_VDAC 0 4 DFE_ERR_ODD_VDAC 5 9 RESERVED_15_10 10 15 ixDPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_CR_BANK_ADDR 2 0x117e 1 0 4294967295 ADDR 0 15 ixDPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_CR_BANK_DATA 2 0x117f 1 0 4294967295 DATA 0 15 ixDPCSSYS_CR2_LANE1_DIG_RX_STAT_LD_VAL_1 2 0x1180 2 0 4294967295 SC1_LD_VAL 0 14 SC1_START 15 15 ixDPCSSYS_CR2_LANE1_DIG_RX_STAT_DATA_MSK 2 0x1181 1 0 4294967295 DATA_MSK_15_0 0 15 ixDPCSSYS_CR2_LANE1_DIG_RX_STAT_MATCH_CTL0 2 0x1182 4 0 4294967295 PTTRN_MSK_CR1A_4_0 0 4 PTTRN_CR1A_4_0 5 9 DATA_MSK_19_16 10 13 SCOPE_DLY 14 15 ixDPCSSYS_CR2_LANE1_DIG_RX_STAT_MATCH_CTL1 2 0x1183 5 0 4294967295 PTTRN_CR1B_EN 0 0 PTTRN_MSK_CR1B_4_0 1 5 PTTRN_CR1B_4_0 6 10 PTTRN_CR1A_ADPT_EN 11 11 RESERVED_15_12 12 15 ixDPCSSYS_CR2_LANE1_DIG_RX_STAT_STAT_CTL0 2 0x1184 10 0 4294967295 RESERVED_0 0 0 CORR_SHFT_SEL_VGA 1 1 CORR_SHFT_SEL 2 2 CORR_SRC_SEL 3 4 CORR_MODE_EN 5 5 STAT_SHFT_SEL 6 9 STAT_SRC_SEL 10 12 STAT_RXCLK_SEL 13 13 SC_TIMER_MODE 14 14 SKIP_EN 15 15 ixDPCSSYS_CR2_LANE1_DIG_RX_STAT_STAT_CTL1 2 0x1185 13 0 4294967295 STAT_CNT_0_EN 0 0 STAT_CNT_1_EN 1 1 STAT_CNT_2_EN 2 2 STAT_CNT_3_EN 3 3 STAT_CNT_4_EN 4 4 STAT_CNT_5_EN 5 5 STAT_CNT_6_EN 6 6 RESERVED_8_7 7 8 SC_PAUSE 9 9 STAT_CLK_EN 10 10 DATA_DLY_SEL 11 12 VLD_LOSS_CLR 13 13 VLD_CTL 14 15 ixDPCSSYS_CR2_LANE1_DIG_RX_STAT_SMPL_CNT1 2 0x1186 2 0 4294967295 SMPL_CNT1 0 14 SMPL_CNT1_DONE 15 15 ixDPCSSYS_CR2_LANE1_DIG_RX_STAT_STAT_CNT_0 2 0x1187 2 0 4294967295 STAT_CNT_0 0 14 SMPL_CNT1_DONE 15 15 ixDPCSSYS_CR2_LANE1_DIG_RX_STAT_STAT_CNT_1 2 0x1188 2 0 4294967295 STAT_CNT_1 0 14 SMPL_CNT1_DONE 15 15 ixDPCSSYS_CR2_LANE1_DIG_RX_STAT_STAT_CNT_2 2 0x1189 2 0 4294967295 STAT_CNT_2 0 14 SMPL_CNT1_DONE 15 15 ixDPCSSYS_CR2_LANE1_DIG_RX_STAT_STAT_CNT_3 2 0x118a 2 0 4294967295 STAT_CNT_3 0 14 SMPL_CNT1_DONE 15 15 ixDPCSSYS_CR2_LANE1_DIG_RX_STAT_STAT_CNT_4 2 0x118b 2 0 4294967295 STAT_CNT_4 0 14 SMPL_CNT1_DONE 15 15 ixDPCSSYS_CR2_LANE1_DIG_RX_STAT_STAT_CNT_5 2 0x118c 2 0 4294967295 STAT_CNT_5 0 14 SMPL_CNT1_DONE 15 15 ixDPCSSYS_CR2_LANE1_DIG_RX_STAT_STAT_CNT_6 2 0x118d 2 0 4294967295 STAT_CNT_6 0 14 SMPL_CNT1_DONE 15 15 ixDPCSSYS_CR2_LANE1_DIG_RX_STAT_CAL_COMP_CLK_CTL 2 0x118e 3 0 4294967295 PRECHRGE_CNT 0 2 REF_DIV_CNT 3 5 RESERVED_15_6 6 15 ixDPCSSYS_CR2_LANE1_DIG_RX_STAT_MATCH_CTL2 2 0x118f 2 0 4294967295 PTTRN_CR1A_19_5 0 14 RESERVED_15_15 15 15 ixDPCSSYS_CR2_LANE1_DIG_RX_STAT_MATCH_CTL3 2 0x1190 2 0 4294967295 PTTRN_MSK_CR1A_19_5 0 14 RESERVED_15_15 15 15 ixDPCSSYS_CR2_LANE1_DIG_RX_STAT_MATCH_CTL4 2 0x1191 2 0 4294967295 PTTRN_CR1B_19_5 0 14 RESERVED_15_15 15 15 ixDPCSSYS_CR2_LANE1_DIG_RX_STAT_MATCH_CTL5 2 0x1192 2 0 4294967295 PTTRN_MSK_CR1B_19_5 0 14 RESERVED_15_15 15 15 ixDPCSSYS_CR2_LANE1_DIG_RX_STAT_STAT_CTL2 2 0x1193 4 0 4294967295 DATA_DLY_SEL_2 0 0 SCOPE_DLY_2 1 1 DISABLE_SAMPLE_COUNT 2 2 RESERVED_15_3 3 15 ixDPCSSYS_CR2_LANE1_DIG_RX_STAT_STAT_STOP 2 0x1194 2 0 4294967295 SC1_STOP 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR2_LANE1_DIG_MPHY_RX_PWM_CTL 2 0x1195 3 0 4294967295 RX_PWM_POL 0 0 RX_PWM_DATA_POL 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR2_LANE1_DIG_MPHY_RX_TERM_LS_CTL 2 0x1196 2 0 4294967295 RX_TERM_LCC_CNT 0 2 RESERVED_15_3 3 15 ixDPCSSYS_CR2_LANE1_DIG_MPHY_RX_ANA_PWM_CLK_STABLE_CNT 2 0x1197 2 0 4294967295 PWM_CLK_STABLE_CNT 0 3 RESERVED_15_4 4 15 ixDPCSSYS_CR2_LANE1_DIG_ANA_TX_OVRD_OUT 2 0x11a0 15 0 4294967295 TX_ANA_CLK_SHIFT 0 0 TX_ANA_DATA_EN 1 1 TX_ANA_REFGEN_EN 2 2 TX_ANA_VCM_HOLD 3 3 TX_ANA_CLK_EN 4 4 TX_ANA_WORD_CLK_EN 5 5 TX_ANA_MPLLA_CLK_EN 6 6 TX_ANA_MPLLB_CLK_EN 7 7 TX_ANA_RESET 8 8 TX_ANA_SERIAL_EN 9 9 TX_ANA_DATA_RATE 10 11 RESERVED 12 12 TX_DIV4_EN 13 13 TX_RXDET_EN 14 14 TX_OVRD_EN 15 15 ixDPCSSYS_CR2_LANE1_DIG_ANA_TX_TERM_CODE_OVRD_OUT 2 0x11a1 5 0 4294967295 TX_TERM_CODE 0 9 TX_TERM_OVRD_EN 10 10 TX_DRV_SRC 11 12 TX_DRV_SRC_OVRD_EN 13 13 RESERVED_15_14 14 15 ixDPCSSYS_CR2_LANE1_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT 2 0x11a2 3 0 4294967295 TX_TERM_DN_CLK 0 0 TX_TERM_CLK_SELF_CLEAR_DISABLE 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR2_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_0 2 0x11a3 3 0 4294967295 TX_ANA_LOAD_CLK 0 0 TX_ANA_CTRL_LEG_PULL_EN_13_0 1 14 TX_EQ_OVRD_EN 15 15 ixDPCSSYS_CR2_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_1 2 0x11a4 2 0 4294967295 TX_ANA_CTRL_LEG_PULL_EN_19_14 0 5 RESERVED_15_6 6 15 ixDPCSSYS_CR2_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_2 2 0x11a5 4 0 4294967295 RESERVED 0 2 TX_ANA_CTRL_EQ_MUX_SEL 3 6 TX_ANA_CTRL_PRE 7 12 RESERVED_15_13 13 15 ixDPCSSYS_CR2_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_3 2 0x11a6 2 0 4294967295 TX_ANA_CTRL_POST 0 8 RESERVED_15_9 9 15 ixDPCSSYS_CR2_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_4 2 0x11a7 1 0 4294967295 TX_ANA_CTRL_LEG_PULL_DIR_19_4 0 15 ixDPCSSYS_CR2_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_5 2 0x11a8 2 0 4294967295 TX_ANA_CTRL_LEG_PULL_DIR_3_0 0 3 RESERVED_15_4 4 15 ixDPCSSYS_CR2_LANE1_DIG_ANA_RX_CTL_OVRD_OUT 2 0x11a9 9 0 4294967295 RESERVED 0 0 RX_ANA_DATA_RATE 1 2 RX_ANA_WORD_CLK_EN 3 3 RX_ANA_DIV4_EN 4 4 RX_ANA_DFE_TAPS_EN 5 5 RX_ANA_ADAPTATION_EN 6 6 RX_LBK_CLK_EN 7 7 RX_CTL_OVRD_EN 8 8 RESERVED_15_9 9 15 ixDPCSSYS_CR2_LANE1_DIG_ANA_RX_PWR_OVRD_OUT 2 0x11aa 9 0 4294967295 RX_ANA_AFE_EN 0 0 RX_ANA_CLK_VREG_EN 1 1 RX_ANA_CLK_DCC_EN 2 2 RX_ANA_CLK_EN 3 3 RX_ANA_CDR_EN 4 4 RX_ANA_DESERIAL_EN 5 5 RX_PWR_OVRD_EN 6 6 RX_ANA_FAST_START 7 7 RESERVED_15_8 8 15 ixDPCSSYS_CR2_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0 2 0x11ab 7 0 4294967295 RX_ANA_CDR_VCO_EN 0 0 RX_ANA_CDR_STARTUP 1 1 RX_VCO_CDR_OVRD_EN 2 2 RX_ANA_CDR_FREQ_TUNE 3 12 RX_ANA_VCO_CNTR_EN 13 13 RX_ANA_VCO_CNTR_CLK 14 14 RX_CDR_FREQ_TUNE_OVRD_EN 15 15 ixDPCSSYS_CR2_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_1 2 0x11ac 3 0 4294967295 RX_ANA_CDR_VCO_LOWFREQ 0 0 RX_ANA_VCO_CNTR_PD 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR2_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_2 2 0x11ad 3 0 4294967295 RX_ANA_CDR_FREQ_TUNE_CLK 0 0 CDR_FREQ_TUNE_CLK_SELF_CLEAR_DISABLE 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR2_LANE1_DIG_ANA_RX_CAL 2 0x11ae 7 0 4294967295 RX_ANA_CAL_MUXA_SEL 0 4 RX_ANA_CAL_MUXB_SEL 5 9 RX_ANA_CAL_LPFBYP_EN 10 10 RESERVED 11 11 RX_ANA_SLICER_CAL_EN 12 12 RX_ANA_CAL_MODE 13 14 RX_ANA_CAL_COMP_EN 15 15 ixDPCSSYS_CR2_LANE1_DIG_ANA_RX_DAC_CTRL 2 0x11af 2 0 4294967295 RX_ANA_CAL_DAC_CTRL 0 7 RESERVED_15_8 8 15 ixDPCSSYS_CR2_LANE1_DIG_ANA_RX_DAC_CTRL_OVRD 2 0x11b0 2 0 4294967295 RX_CAL_DAC_CTRL_OVRD 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR2_LANE1_DIG_ANA_RX_DAC_CTRL_SEL 2 0x11b1 2 0 4294967295 RX_ANA_CAL_DAC_CTRL_SEL 0 4 RESERVED_15_5 5 15 ixDPCSSYS_CR2_LANE1_DIG_ANA_RX_AFE_ATT_VGA 2 0x11b2 5 0 4294967295 RX_ANA_AFE_ATT_LVL 0 2 RX_ANA_AFE_GAIN 3 6 RESERVED 7 10 RX_AFE_OVRD_EN 11 11 RESERVED_15_12 12 15 ixDPCSSYS_CR2_LANE1_DIG_ANA_RX_AFE_CTLE 2 0x11b3 3 0 4294967295 RESERVED 0 2 RX_ANA_AFE_CTLE_BOOST 3 7 RESERVED_15_8 8 15 ixDPCSSYS_CR2_LANE1_DIG_ANA_RX_SCOPE 2 0x11b4 7 0 4294967295 RX_ANA_SCOPE_EN 0 0 RX_ANA_SCOPE_SEL 1 2 RX_ANA_SCOPE_PH_CLK 3 3 RX_ANA_SCOPE_PHASE 4 11 RX_ANA_SCOPE_CLK_EN 12 12 RX_SCOPE_SELF_CLEAR_DISABLE 13 13 RESERVED_15_14 14 15 ixDPCSSYS_CR2_LANE1_DIG_ANA_RX_SLICER_CTRL 2 0x11b5 4 0 4294967295 RX_ANA_SLICER_CTRL_E 0 3 RX_ANA_SLICER_CTRL_O 4 7 RX_ANA_SLICER_CTRL_OVRD_EN 8 8 RESERVED_15_9 9 15 ixDPCSSYS_CR2_LANE1_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST 2 0x11b6 2 0 4294967295 RX_ANA_IQ_PHASE_ADJUST 0 6 RESERVED_15_7 7 15 ixDPCSSYS_CR2_LANE1_DIG_ANA_RX_ANA_IQ_SENSE_EN 2 0x11b7 2 0 4294967295 RX_ANA_IQ_SENSE_EN 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR2_LANE1_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN 2 0x11b8 3 0 4294967295 RX_ANA_CAL_DAC_CTRL_EN 0 0 DAC_CTRL_SELF_CLEAR_DISABLE 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR2_LANE1_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE 2 0x11b9 3 0 4294967295 RX_ANA_AFE_UPDATE_EN 0 0 AFE_UPDATE_SELF_CLEAR_DISABLE 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR2_LANE1_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK 2 0x11ba 3 0 4294967295 RX_ANA_IQ_PHASE_ADJUST_CLK 0 0 PHASE_ADJUST_SELF_CLEAR_DISABLE 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR2_LANE1_DIG_ANA_STATUS_0 2 0x11bb 9 0 4294967295 TX_ANA_CLK_SHIFT_ACK 0 0 TX_ANA_RXDETP_RESULT 1 1 TX_ANA_RXDETM_RESULT 2 2 TX_ANA_LOOPBACK_EN 3 3 TX_ANA_CLK_LB_EN 4 4 RX_ANA_CAL_RESULT 5 5 RX_ANA_SCOPE_DATA 6 6 TX_ANA_DCC_CAL_RESULT 7 7 TX_ANA_CTRL_EQ_MUX 8 15 ixDPCSSYS_CR2_LANE1_DIG_ANA_STATUS_1 2 0x11bc 2 0 4294967295 RX_ANA_VCO_CNTR 0 12 RESERVED_15_13 13 15 ixDPCSSYS_CR2_LANE1_DIG_ANA_RX_TERM_CODE_OVRD_OUT 2 0x11bd 3 0 4294967295 RX_TERM_CODE 0 5 RX_TERM_OVRD_EN 6 6 RESERVED_15_7 7 15 ixDPCSSYS_CR2_LANE1_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT 2 0x11be 3 0 4294967295 RX_TERM_CLK 0 0 RX_TERM_CLK_SELF_CLEAR_DISABLE 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR2_LANE1_DIG_ANA_MPHY_OVRD_OUT 2 0x11bf 9 0 4294967295 RX_ANA_SQ_CTRL_TRESH 0 2 RX_ANA_SQ_CTRL_TRESH_OVRD_EN 3 3 RX_ANA_SQ_CTRL_RESP 4 5 RX_ANA_SQ_CTRL_RESP_OVRD_EN 6 6 RX_ANA_PWM_EN 7 7 RX_ANA_PWM_EN_OVRD_EN 8 8 RX_ANA_PWM_CLK_SEL 9 10 RX_ANA_PWM_CLK_SEL_OVRD_EN 11 11 RESERVED_15_12 12 15 ixDPCSSYS_CR2_LANE1_DIG_ANA_SIGDET_OVRD_OUT_1 2 0x11c0 7 0 4294967295 RX_ANA_SIGDET_HF_THRESH 0 2 RX_ANA_SIGDET_HF_THRESH_OVRD_EN 3 3 RX_ANA_SIGDET_HF_CAL_TUNE 4 9 RX_ANA_SIGDET_CAL_TUNE_OVRD_EN 10 10 RX_ANA_SIGDET_CAL_EN 11 11 RX_ANA_SIGDET_CAL_EN_OVRD_EN 12 12 RESERVED_15_13 13 15 ixDPCSSYS_CR2_LANE1_DIG_ANA_SIGDET_OVRD_OUT_2 2 0x11c1 7 0 4294967295 RX_ANA_SIGDET_LF_THRESH 0 2 RX_ANA_SIGDET_LF_THRESH_OVRD_EN 3 3 RX_ANA_SIGDET_LF_FILTER_EN 4 4 RX_ANA_SIGDET_LF_FILTER_EN_OVRD_EN 5 5 RX_ANA_SIGDET_CAL_TUNE 6 11 RX_ANA_SIGDET_CAL_TUNE_OVRD_EN 12 12 RESERVED_15_13 13 15 ixDPCSSYS_CR2_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT 2 0x11c2 8 0 4294967295 TX_ANA_DCC_CAL_RANGE 0 1 TX_ANA_DCC_CAL_RANGE_OVRD_EN 2 2 TX_ANA_DCC_CAL_COMP_EN 3 3 TX_ANA_DCC_CAL_COMP_EN_OVRD_EN 4 4 TX_ANA_DCC_CAL_CTRL 5 12 TX_ANA_DCC_CAL_CTRL_OVRD_EN 13 13 TX_ANA_DCC_CAL_CTRL_EN 14 14 TX_ANA_DCC_CAL_CTRL_EN_OVRD_EN 15 15 ixDPCSSYS_CR2_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2 2 0x11c3 5 0 4294967295 TX_ANA_DCC_CAL_CTRL_SEL 0 2 TX_ANA_DCC_CAL_CTRL_SEL_OVRD_EN 3 3 TX_ANA_DCC_CLK_COMP 4 4 TX_ANA_DCC_CLK_COMP_OVRD_EN 5 5 RESERVED_15_6 6 15 ixDPCSSYS_CR2_LANE1_DIG_ANA_TX_OVRD_OUT_2 2 0x11c4 6 0 4294967295 TX_ANA_FAST_START 0 0 TX_ANA_FAST_START_OVRD_EN 1 1 TX_CLK_LB_EN 2 2 TX_CLK_LB_EN_OVRD_EN 3 3 TX_ACJTAG_EN 4 4 RESERVED_15_5 5 15 ixDPCSSYS_CR2_LANE1_ANA_TX_OVRD_MEAS 2 0x11e0 9 0 4294967295 OVRD_CLK_SHIFT 0 0 CLK_SHIFT_REG 0 0 MEAS_ATB_CAL_MUX 0 0 MEAS_ATB_CAL_COMP 0 0 OVRD_VCM_HOLD 0 0 VCM_HOLD_REG 0 0 PULL_UP_REG 0 0 PULL_DN_REG 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR2_LANE1_ANA_TX_PWR_OVRD 2 0x11e1 9 0 4294967295 OVRD_TX_LOOPBACK 0 0 LOOPBACK_EN_REG 0 0 REFGEN_EN_REG 0 0 CLK_DIV_EN_REG 0 0 DATA_EN_REG_INT 0 0 CLK_EN_REG 0 0 SERIAL_EN_REG 0 0 OVRD_EN 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR2_LANE1_ANA_TX_ALT_BUS 2 0x11e2 6 0 4294967295 DRV_SOURCE_REG 0 0 OVRD_ALT_BUS 0 0 ATB_S_ENABLE 0 0 TX_ALT_RINGO 0 0 JTAG_DATA_REG 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR2_LANE1_ANA_TX_ATB1 2 0x11e3 9 0 4294967295 MEAS_ATB_GD 0 0 MEAS_ATB_VDDH 0 0 OVERRIDE_RXDETREF 0 0 MEAS_ATB_VPTX 0 0 OVERRIDE_REGREF 0 0 MEAS_ATB_VREG_DRV 0 0 MEAS_ATB_VREG 0 0 MEAS_ATB_VPH_HALF 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR2_LANE1_ANA_TX_ATB2 2 0x11e4 9 0 4294967295 MEAS_ATB_VCM 0 0 MEAS_ATB_CAL_VDAC_CM 0 0 MEAS_ATB_CAL_VDAC_DIFF 0 0 MEAS_ATB_TXM 0 0 MEAS_ATB_TXP 0 0 MEAS_ATB_RXDETREF 0 0 LFPS_HIGH_PRIORITY 0 0 OSC_DIV4_EN 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR2_LANE1_ANA_TX_DCC_DAC 2 0x11e5 2 0 4294967295 DCC_DAC_REG 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR2_LANE1_ANA_TX_DCC_CTRL1 2 0x11e6 7 0 4294967295 NC0 0 0 OVRD_DCC_DAC_CTRL_SEL 0 0 DCC_DAC_CTRL_SEL_REG 0 0 OVRD_DCC_DAC_CTRL_EN 0 0 DCC_DAC_CTRL_EN_REG 0 0 OVRD_DCC_DAC_REG 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR2_LANE1_ANA_TX_TERM_CODE 2 0x11e7 2 0 4294967295 TERM_CODE_REG_70 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR2_LANE1_ANA_TX_TERM_CODE_CTRL 2 0x11e8 8 0 4294967295 VREG_BOOST_1 0 0 OVRD_UPDATE_TERM 0 0 UPDATE_TERM_REG 0 0 OVRD_RESET_TERM 0 0 RESET_TERM_REG 0 0 OVRD_TERM_CODE 0 0 TERM_CODE_REG_98 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR2_LANE1_ANA_TX_OVRD_CLK 2 0x11e9 9 0 4294967295 VREG_BOOST_0 0 0 CLK_LB_EN_REG 0 0 OVRD_LB_EN 0 0 MPLLB_CLK_EN_REG 0 0 MPLLA_CLK_EN_REG 0 0 OVRD_MPLLAB_EN 0 0 WORD_CLK_EN_REG 0 0 OVRD_WORD_CLK_EN 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR2_LANE1_ANA_TX_MISC1 2 0x11ea 8 0 4294967295 MEAS_ATB_CAL_CLK_ALIGN 0 0 OVRD_DCC_DAC_CTRL_RANGE 0 0 DCC_DAC_CTRL_RANGE_REG 0 0 OVRD_VREF_SEL 0 0 VREF_SEL_REG 0 0 FORCE_ATB_TXM 0 0 FORCE_ATB_TXP 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR2_LANE1_ANA_TX_MISC2 2 0x11eb 8 0 4294967295 TX_PEAKING_LVL 0 0 VREG_CP_GAIN_CTRL 0 0 TX_SLEW_EN 0 0 EN_INV_POST 0 0 EN_INV_PRE 0 0 TX_VREG_EN_BYP 0 0 TX_VDRIVER_PULLDN_EN 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR2_LANE1_ANA_TX_MISC3 2 0x11ec 4 0 4294967295 TX_VREG_OVRD_RING_CTRL 0 0 TX_DCC_LOWV 0 0 NC7_2 2 7 RESERVED_15_8 8 15 ixDPCSSYS_CR2_LANE1_ANA_TX_RESERVED2 2 0x11ed 2 0 4294967295 NC7_0 0 7 RESERVED_15_8 8 15 ixDPCSSYS_CR2_LANE1_ANA_TX_RESERVED3 2 0x11ee 2 0 4294967295 NC7_0 0 7 RESERVED_15_8 8 15 ixDPCSSYS_CR2_LANE1_ANA_TX_RESERVED4 2 0x11ef 2 0 4294967295 NC7_0 0 7 RESERVED_15_8 8 15 ixDPCSSYS_CR2_LANE1_ANA_RX_CLK_1 2 0x11f0 8 0 4294967295 CDR_VCO_STARTUP_CODE 0 0 CDR_VCO_TEMP_COMP_EN 0 0 CDR_VCO_USE_UNCAL_BIAS 0 0 OVERRIDE_CDR_EN 0 0 OVRD_CLK_EN 0 0 CLK_EN_REG 0 0 NC7 7 7 RESERVED_15_8 8 15 ixDPCSSYS_CR2_LANE1_ANA_RX_CLK_2 2 0x11f1 5 0 4294967295 IQ_PHASE_ADJUST_REG 0 0 OVRD_IQ_PHASE_ADJUST 0 0 RX_LOOPBACK_CLK_REG 0 0 OVRD_RX_LOOPBACK_CLK 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR2_LANE1_ANA_RX_CDR_DES 2 0x11f2 7 0 4294967295 OVRD_WORD_CLK_EN 0 0 WORD_CLK_EN_REG 0 0 PHDET_ODD_REG 0 0 PHDET_EVEN_REG 0 0 SIGDET_VREF_EXT_EN 0 0 NC7_5 5 7 RESERVED_15_8 8 15 ixDPCSSYS_CR2_LANE1_ANA_RX_SLC_CTRL 2 0x11f3 3 0 4294967295 RX_SLICER_CTRL_O_REG 0 0 RX_SLICER_CTRL_E_REG 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR2_LANE1_ANA_RX_PWR_CTRL1 2 0x11f4 8 0 4294967295 OVRD_ACJT_EN 0 0 ACJT_EN_REG 0 0 OVRD_AFE_EN 0 0 AFE_EN_REG 0 0 AFE_CM_SEL 0 0 ATT_PULLDN_EN 0 0 NC7_7 7 7 RESERVED_15_8 8 15 ixDPCSSYS_CR2_LANE1_ANA_RX_PWR_CTRL2 2 0x11f5 9 0 4294967295 OVRD_DFE_EN 0 0 DFE_EN_REG 0 0 OVRD_DESERIAL_EN 0 0 DESERIAL_EN_REG 0 0 OVRD_LOOPBACK_EN 0 0 LOOPBACK_EN_REG 0 0 OVRD_FAST_START 0 0 FAST_START_REG 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR2_LANE1_ANA_RX_SQ 2 0x11f6 7 0 4294967295 SQ_CTRL_RESP_REG 0 0 OVRD_SQ_CTRL_RESP 0 0 NC4_3 3 4 SQ_CTRL_TRESH_REG 0 0 OVRD_SQ_CTRL_TRESH 0 0 AFE_LOOPBACK_SEL 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR2_LANE1_ANA_RX_CAL1 2 0x11f7 5 0 4294967295 DFE_TAPS_EN_REG 0 0 OVRD_DFE_TAPS_EN 0 0 CAL_MUXB_SEL_REG 0 0 OVRD_CAL_MUXB_SEL 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR2_LANE1_ANA_RX_CAL2 2 0x11f8 5 0 4294967295 AFE_PD_EQ_OFFSET 0 0 CAL_IDACS_USE_UNCAL 0 0 CAL_MUXA_SEL_REG 0 0 OVRD_CAL_MUXA_SEL 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR2_LANE1_ANA_RX_ATB_REGREF 2 0x11f9 8 0 4294967295 OVERRIDE_REGREF_VCO 0 0 OVERRIDE_REGREF_CLK 0 0 OVERRIDE_REGREF_IQC 0 0 BOOST_REGREF_IQC 0 0 OVRD_RX_SLICER_CTRL 0 0 OVRD_RX_TERM_AC_DCZ 0 0 RX_TERM_AC_DCZ_REG 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR2_LANE1_ANA_RX_ATB_MEAS1 2 0x11fa 9 0 4294967295 MASTER_ATB_EN 0 0 MEAS_ATB_VP 0 0 MEAS_ATB_GD 0 0 MEAS_ATB_VREG_VCO 0 0 MEAS_ATB_VREG_CLK 0 0 MEAS_ATB_VREG_IQC 0 0 REGS_FB_DIV_CTRL 0 0 RX_VREG_CLK_BYPASS 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR2_LANE1_ANA_RX_ATB_MEAS2 2 0x11fb 2 0 4294967295 MEAS_ATB_RX 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR2_LANE1_ANA_RX_ATB_MEAS3 2 0x11fc 7 0 4294967295 MEAS_ATB_CDR_VCO_GD 0 0 MEAS_ATB_CDR_VCO_VIREF_200U 0 0 MEAS_ATB_VIBIAS_CDR_VCO 0 0 MEAS_ATB_CDR_VCO_VOSC 0 0 MEAS_ATB_CAL_MUX 0 0 RX_VREG_OVERRIDE_RING_CTRL 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR2_LANE1_ANA_RX_ATB_MEAS4 2 0x11fd 3 0 4294967295 MEAS_ATB_CAL_VREF 0 0 NC7 7 7 RESERVED_15_8 8 15 ixDPCSSYS_CR2_LANE1_ANA_RX_ATB_FRC 2 0x11fe 2 0 4294967295 FRC_ATB_CAL_VREF 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR2_LANE1_ANA_RX_RESERVED1 2 0x11ff 2 0 4294967295 NC7_0 0 7 RESERVED_15_8 8 15 ixDPCSSYS_CR2_LANE2_DIG_ASIC_LANE_OVRD_IN 2 0x1200 5 0 4294967295 LANE_TX2RX_SER_LB 0 0 LANE_RX2TX_PAR_LB 1 1 EN 2 2 RX_ACJTAG_EN 3 3 RESERVED_15_4 4 15 ixDPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_0 2 0x1201 12 0 4294967295 REQ 0 0 REQ_OVRD_EN 1 1 PSTATE 2 3 PSTATE_OVRD_EN 4 4 RATE 5 7 RATE_OVRD_EN 8 8 WIDTH 9 10 WIDTH_OVRD_EN 11 11 MPLLB_SEL 12 12 MPLLB_SEL_OVRD_EN 13 13 DATA_EN 14 14 DATA_EN_OVRD_EN 15 15 ixDPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_1 2 0x1202 11 0 4294967295 NYQUIST_DATA 0 0 DISABLE 1 1 BEACON_EN 2 2 EN 3 3 TX_MAIN_CURSOR 4 9 MAIN_OVRD_EN 10 10 ASYNC_DRV_EN 11 11 ASYNC_DRV_OVRD_EN 12 12 TX_VREGDRV_BYP_OVRD 13 13 TX_VREGDRV_BYP_OVRD_EN 14 14 RESERVED_15_15 15 15 ixDPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_2 2 0x1203 6 0 4294967295 TX_PRE_CURSOR 0 5 PRE_OVRD_EN 6 6 TX_POST_CURSOR 7 12 POST_OVRD_EN 13 13 HDMIMODE_EN 14 14 HDMIMODE_ENABLE_OVRD_EN 15 15 ixDPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_3 2 0x1204 15 0 4294967295 CLK_RDY 0 0 CLK_RDY_OVRD_EN 1 1 DETECT_RX_REQ 2 2 DETECT_RX_REQ_OVRD_EN 3 3 INVERT 4 4 INVERT_OVRD_EN 5 5 LPD 6 6 LPD_OVRD_EN 7 7 TX_DC_COUP_EN 8 8 TX_DC_COUP_EN_OVRD_EN 9 9 PMA_EXTENDED_FIFO_EN 10 10 PMA_EXTENDED_FIFO_EN_OVRD_EN 11 11 TX_MPHY_MODE_EN 12 12 TX_MPHY_MODE_EN_OVRD_EN 13 13 RESERVED_15_14 14 15 ixDPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_4 2 0x1205 3 0 4294967295 RESET 0 0 RESET_OVRD_EN 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_OUT 2 0x1206 5 0 4294967295 TX_ACK 0 0 EN_TX_ACK 1 1 DETRX_RESULT 2 2 EN_DETRX_RESULT 3 3 RESERVED_15_4 4 15 ixDPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_0 2 0x1207 11 0 4294967295 REQ 0 0 REQ_OVRD_EN 1 1 DATA_EN 2 2 DATA_EN_OVRD_EN 3 3 PSTATE 4 5 PSTATE_OVRD_EN 6 6 RATE 7 8 RATE_OVRD_EN 9 9 WIDTH 10 11 WIDTH_OVRD_EN 12 12 RESERVED_15_13 13 15 ixDPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_1 2 0x1208 5 0 4294967295 RX_REF_LD_VAL_5_0 0 5 RX_CDR_VCO_LOWFREQ 6 6 EN 7 7 RX_REF_LD_VAL_6 8 8 RESERVED_15_9 9 15 ixDPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_2 2 0x1209 3 0 4294967295 RX_VCO_LD_VAL 0 12 EN 13 13 RESERVED_15_14 14 15 ixDPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_3 2 0x120a 11 0 4294967295 CDR_TRACK_EN 0 0 CDR_TRACK_EN_OVRD_EN 1 1 CDR_SSC_EN 2 2 CDR_SSC_EN_OVRD_EN 3 3 ALIGN_EN 4 4 ALIGN_EN_OVRD_EN 5 5 CLK_SHIFT 6 6 CLK_SHIFT_OVRD_EN 7 7 DISABLE 8 8 DISABLE_OVRD_EN 9 9 RESERVED_15_10 10 15 ixDPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_4 2 0x120b 11 0 4294967295 LPD 0 0 LPD_OVRD_EN 1 1 INVERT 2 2 INVERT_OVRD_EN 3 3 ADAPT_AFE_EN 4 4 ADAPT_DFE_EN 5 5 ADPT_OVRD_EN 6 6 TERM_EN 7 7 TERM_ACDC 8 8 TERM_OVRD_EN 9 9 RESERVED_15_10 10 15 ixDPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_5 2 0x120c 3 0 4294967295 RESET 0 0 RESET_OVRD_EN 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0 2 0x120d 4 0 4294967295 EQ_ATT_LVL 0 2 EQ_AFE_GAIN 3 6 RESERVED 7 10 EQ_CTLE_BOOST 11 15 ixDPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1 2 0x120e 3 0 4294967295 EQ_DFE_TAP2 0 6 EQ_DFE_TAP1 7 14 EQ_OVRD_EN 15 15 ixDPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_OUT_0 2 0x120f 9 0 4294967295 ACK 0 0 ACK_OVRD_EN 1 1 ADAPT_STS 2 3 ADAPT_STS_OVRD_EN 4 4 RX_ASYNC_DATA 5 5 RX_ASYNC_DATA_OVRD_EN 6 6 RX_SQ_WEAKKEEP_OUT 7 7 RX_SQ_WEAKKEEP_OUT_OVRD_EN 8 8 RESERVED_15_9 9 15 ixDPCSSYS_CR2_LANE2_DIG_ASIC_LANE_ASIC_IN 2 0x1210 3 0 4294967295 LANE_TX2RX_SER_LB 0 0 LANE_RX2TX_PAR_LB 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR2_LANE2_DIG_ASIC_TX_ASIC_IN_0 2 0x1211 12 0 4294967295 CLK_RDY 0 0 RESET 1 1 INVERT 2 2 DATA_EN 3 3 REQ 4 4 LPD 5 5 PSTATE 6 7 RATE 8 10 WIDTH 11 12 MPLLB_SEL 13 13 DETECT_RX_REQ 14 14 DISABLE 15 15 ixDPCSSYS_CR2_LANE2_DIG_ASIC_TX_ASIC_IN_1 2 0x1212 7 0 4294967295 BEACON_EN 0 0 TX_MAIN_CURSOR 1 6 TX_ASYNC_EN 7 7 TX_ASYNC_DATA 8 8 TX_ASYNC_DRV_EN 9 9 TX_VREGDRV_BYP 10 10 RESERVED_15_11 11 15 ixDPCSSYS_CR2_LANE2_DIG_ASIC_TX_ASIC_IN_2 2 0x1213 3 0 4294967295 TX_PRE_CURSOR 0 5 TX_POST_CURSOR 6 11 RESERVED_15_12 12 15 ixDPCSSYS_CR2_LANE2_DIG_ASIC_TX_ASIC_OUT 2 0x1214 3 0 4294967295 TX_ACK 0 0 DETRX_RESULT 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR2_LANE2_DIG_ASIC_RX_ASIC_IN_0 2 0x1215 13 0 4294967295 RESET 0 0 INVERT 1 1 DATA_EN 2 2 REQ 3 3 LPD 4 4 PSTATE 5 6 RATE 7 8 WIDTH 9 10 RESERVED 11 11 ADAPT_AFE_EN 12 12 ADAPT_DFE_EN 13 13 CDR_TRACK_EN 14 14 RESERVED_15_15 15 15 ixDPCSSYS_CR2_LANE2_DIG_ASIC_RX_ASIC_IN_1 2 0x1216 7 0 4294967295 CDR_SSC_EN 0 0 ALIGN_EN 1 1 CLK_SHIFT 2 2 DISABLE 3 3 RX_TERM_EN 4 4 RX_TERM_ACDC 5 5 RESERVED_15_6 6 15 ixDPCSSYS_CR2_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0 2 0x1217 4 0 4294967295 EQ_ATT_LVL 0 2 EQ_AFE_GAIN 3 6 RESERVED 7 10 EQ_CTLE_BOOST 11 15 ixDPCSSYS_CR2_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_1 2 0x1218 3 0 4294967295 EQ_DFE_TAP2 0 6 EQ_DFE_TAP1 7 14 RESERVED_15_15 15 15 ixDPCSSYS_CR2_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0 2 0x1219 3 0 4294967295 RX_CDR_VCO_LOWFREQ 0 0 RX_REF_LD_VAL 1 7 RESERVED_15_8 8 15 ixDPCSSYS_CR2_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1 2 0x121a 2 0 4294967295 RX_VCO_LD_VAL 0 12 RESERVED_15_13 13 15 ixDPCSSYS_CR2_LANE2_DIG_ASIC_RX_ASIC_OUT_0 2 0x121b 4 0 4294967295 ACK 0 0 VALID 1 1 ADAPT_STS 2 3 RESERVED_15_4 4 15 ixDPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_6 2 0x121c 10 0 4294967295 RX_PWM_CLK_SEL 0 1 RX_PWM_CLK_SEL_OVRD_EN 2 2 RX_TERM_LCC_ON 3 3 RX_TERM_LS_ON 4 4 RX_TERM_LS_LCC_ON_OVRD_EN 5 5 RX_TERM_CTL 6 7 RX_TERM_CTL_OVRD_EN 8 8 RX_PWM_EN 9 9 RX_PWM_EN_OVRD_EN 10 10 RESERVED_15_11 11 15 ixDPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_5 2 0x121d 15 0 4294967295 RPTR_EN_MASTER_LANE 0 0 RPTR_EN_MASTER_LANE_OVRD_EN 1 1 DIG_CLK_EN_OTHER_LANE 2 2 DIG_CLK_EN_OTHER_LANE_OVRD_EN 3 3 DIG_CLK_STATE_MASTER_LANE 4 4 DIG_CLK_STATE_MASTER_LANE_OVRD_EN 5 5 SHIFT_MASTER_LANE 6 6 SHIFT_MASTER_LANE_ORVD_EN 7 7 SHIFT_ACK_OTHER_LANE 8 8 SHIFT_ACK_OTHER_LANE_OVRD_EN 9 9 LANE_MASTER 10 10 LANE_MASTER_OVRD_IN_EN 11 11 TX_DWORD_CLK_SYNC_OVRD 12 12 TX_DWORD_CLK_SYNC_OVRD_EN 13 13 RESERVED_15_14 14 15 ixDPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_OUT_1 2 0x121e 11 0 4294967295 RPTR_EN_OUT 0 0 RPTR_EN_OUT_OVRD_EN 1 1 DIG_CLK_EN_OUT 2 2 DIG_CLK_EN_OUT_OVRD_EN 3 3 DIG_CLK_STATE_OUT 4 4 DIG_CLK_STATE_OUT_OVRD_EN 5 5 SHIFT_OUT 6 6 SHIFT_OUT_OVRD_EN 7 7 SHIFT_ACK_OUT 8 8 SHIFT_ACK_OUT_OVRD_EN 9 9 RESERVED_15_10 10 15 ixDPCSSYS_CR2_LANE2_DIG_ASIC_OCLA 2 0x121f 3 0 4294967295 RX_DWORD_OCLA_CLK_EN 0 0 RX_DWORD_OCLA_DATA_EN 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0 2 0x1220 11 0 4294967295 TX_P0_ANA_REFGEN_EN 0 0 TX_P0_ANA_VCM_HOLD 1 1 TX_P0_ANA_CLK_EN 2 2 TX_P0_ANA_WORD_CLK_EN 3 3 TX_P0_ANA_RESET 4 4 TX_P0_ANA_SERIAL_EN 5 5 TX_P0_DIG_CLK_EN 6 6 TX_P0_DATA_EN 7 7 TX_P0_ALLOW_RXDET 8 8 TX_P0_ANA_DCC_COMP_CAL_EN 9 9 RESERVED_15_10 10 15 ixDPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S 2 0x1221 11 0 4294967295 TX_P0S_ANA_REFGEN_EN 0 0 TX_P0S_ANA_VCM_HOLD 1 1 TX_P0S_ANA_CLK_EN 2 2 TX_P0S_ANA_WORD_CLK_EN 3 3 TX_P0S_ANA_RESET 4 4 TX_P0S_ANA_SERIAL_EN 5 5 TX_P0S_DIG_CLK_EN 6 6 TX_P0S_DATA_EN 7 7 TX_P0S_ALLOW_RXDET 8 8 TX_P0S_ANA_DCC_COMP_CAL_EN 9 9 RESERVED_15_10 10 15 ixDPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1 2 0x1222 11 0 4294967295 TX_P1_ANA_REFGEN_EN 0 0 TX_P1_ANA_VCM_HOLD 1 1 TX_P1_ANA_CLK_EN 2 2 TX_P1_ANA_WORD_CLK_EN 3 3 TX_P1_ANA_RESET 4 4 TX_P1_ANA_SERIAL_EN 5 5 TX_P1_DIG_CLK_EN 6 6 TX_P1_DATA_EN 7 7 TX_P1_ALLOW_RXDET 8 8 TX_P1_ANA_DCC_COMP_CAL_EN 9 9 RESERVED_15_10 10 15 ixDPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2 2 0x1223 12 0 4294967295 TX_P2_ANA_REFGEN_EN 0 0 TX_P2_ANA_VCM_HOLD 1 1 TX_P2_ANA_CLK_EN 2 2 TX_P2_ANA_WORD_CLK_EN 3 3 TX_P2_ANA_RESET 4 4 TX_P2_ANA_SERIAL_EN 5 5 TX_P2_DIG_CLK_EN 6 6 TX_P2_DATA_EN 7 7 TX_P2_ALLOW_RXDET 8 8 TX_P2_ALLOW_VBOOST 9 9 TX_P2_ANA_DCC_COMP_CAL_EN 10 10 RESERVED_15_11 11 15 ixDPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_0 2 0x1224 2 0 4294967295 TX_REFGEN_EN_TIME 0 7 TX_CLK_EN 8 15 ixDPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_1 2 0x1225 2 0 4294967295 TX_VCM_HOLD_TIME_14_0 0 14 SKIP_TX_VCM_HOLD_WAIT 15 15 ixDPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_2 2 0x1226 2 0 4294967295 TX_VBOOST_DIS_TIME_12_0 0 12 DTB_SEL 13 15 ixDPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_3 2 0x1227 3 0 4294967295 TX_VCM_HOLD_TIME_17_15 0 2 TX_VBOOST_DIS_TIME_13 3 3 RESERVED_15_4 4 15 ixDPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_4 2 0x1228 2 0 4294967295 TX_VCM_HOLD_GS_TIME 0 14 SKIP_TX_VCM_HOLD_GS_PULSE 15 15 ixDPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_5 2 0x1229 5 0 4294967295 TX_RXDET_TIME 0 9 FAST_TX_RXDET 10 10 TX_RESET_TIME 11 12 TX_SERIAL_EN_TIME 13 14 RESERVED_15_15 15 15 ixDPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_DCC_CR_BANK_ADDR 2 0x122a 1 0 4294967295 ADDR 0 15 ixDPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_DCC_CR_BANK_DATA 2 0x122b 1 0 4294967295 DATA 0 15 ixDPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_DCC_DAC_CTRL 2 0x122c 2 0 4294967295 CTRL 0 7 RESERVED_15_8 8 15 ixDPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_DCC_DAC_RANGE 2 0x122d 2 0 4294967295 CTRL 0 1 RESERVED_15_2 2 15 ixDPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_DCC_DAC_SEL 2 0x122e 6 0 4294967295 SEL 0 2 REQ 3 3 CTRL_UPD 4 4 RANGE_UPD 5 5 BIN_HOT 6 6 RESERVED_15_7 7 15 ixDPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_DCC_DAC_ACK 2 0x122f 2 0 4294967295 ACK 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_DCC_DAC_ADDR 2 0x1230 1 0 4294967295 ADDR 0 15 ixDPCSSYS_CR2_LANE2_DIG_TX_CLK_ALIGN_TX_CTL_0 2 0x1231 4 0 4294967295 TX_NUM_2UI_SHIFTS_16B_MODE 0 3 TX_NUM_2UI_SHIFTS_20B_MODE 4 7 TX_FIFO_BYPASS 8 8 RESERVED_15_9 9 15 ixDPCSSYS_CR2_LANE2_DIG_TX_LBERT_CTL 2 0x1232 4 0 4294967295 MODE 0 3 TRIGGER_ERR 4 4 PAT0 5 14 RESERVED_15_15 15 15 ixDPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0 2 0x1240 12 0 4294967295 RX_P0_ANA_AFE_EN 0 0 RX_P0_ANA_CLK_VREG_EN 1 1 RESERVED_1 2 2 RX_P0_ANA_CLK_EN 3 3 RESERVED_0 4 4 RX_P0_ANA_DESER_EN 5 5 RX_P0_ANA_CDR_EN 6 6 RX_P0_VCO_FREQ_RST 7 7 RX_P0_VCO_CAL_RST 8 8 RX_P0_VCO_CONTCAL_EN 9 9 RX_P0_DIG_CLK_EN 10 10 RESERVED_15_11 11 15 ixDPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S 2 0x1241 12 0 4294967295 RX_P0S_ANA_AFE_EN 0 0 RX_P0S_ANA_CLK_VREG_EN 1 1 RESERVED_2 2 2 RX_P0S_ANA_CLK_EN 3 3 RESERVED_4 4 4 RX_P0S_ANA_DESER_EN 5 5 RX_P0S_ANA_CDR_EN 6 6 RX_P0S_VCO_FREQ_RST 7 7 RX_P0S_VCO_CAL_RST 8 8 RX_P0S_VCO_CONTCAL_EN 9 9 RX_P0S_DIG_CLK_EN 10 10 RESERVED_15_11 11 15 ixDPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1 2 0x1242 12 0 4294967295 RX_P1_ANA_AFE_EN 0 0 RX_P1_ANA_CLK_VREG_EN 1 1 RESERVED_2 2 2 RX_P1_ANA_CLK_EN 3 3 RESERVED_4 4 4 RX_P1_ANA_DESER_EN 5 5 RX_P1_ANA_CDR_EN 6 6 RX_P1_VCO_FREQ_RST 7 7 RX_P1_VCO_CAL_RST 8 8 RX_P1_VCO_CONTCAL_EN 9 9 RX_P1_DIG_CLK_EN 10 10 RESERVED_15_11 11 15 ixDPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2 2 0x1243 12 0 4294967295 RX_P2_ANA_AFE_EN 0 0 RX_P2_ANA_CLK_VREG_EN 1 1 RESERVED_2 2 2 RX_P2_ANA_CLK_EN 3 3 RESERVED_4 4 4 RX_P2_ANA_DESER_EN 5 5 RX_P2_ANA_CDR_EN 6 6 RX_P2_VCO_FREQ_RST 7 7 RX_P2_VCO_CAL_RST 8 8 RX_P2_VCO_CONTCAL_EN 9 9 RX_P2_DIG_CLK_EN 10 10 RESERVED_15_11 11 15 ixDPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1 2 0x1245 5 0 4294967295 RX_AFE_EN_TIME 0 5 FAST_RX_AFE_EN 6 6 RX_VREG_EN_TIME 7 12 FAST_RX_VREG_EN 13 13 RESERVED_15_14 14 15 ixDPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_2 2 0x1246 4 0 4294967295 RX_CLK_EN_TIME 0 5 FAST_RX_CLK_EN 6 6 RX_FAST_START_TIME 7 10 RESERVED_15_11 11 15 ixDPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_3 2 0x1247 5 0 4294967295 RX_RATE_TIME 0 1 RSVD_3_7_2 2 7 RX_CDR_EN_TIME 8 11 RX_DESER_EN_TIME 12 13 RX_DESER_DIS_TIME 14 15 ixDPCSSYS_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0 2 0x1248 8 0 4294967295 INT_GAIN_CAL_FIXED_CNT 0 4 INT_GAIN_CAL_FIXED_CNT_EN 5 5 INT_GAIN_CAL_CNT_SHIFT 6 8 INT_GAIN_CAL_BOUNCE_CNT 9 11 DISABLE_BIN_HOLD 12 12 DISABLE_INT_GAIN_HOLD 13 13 DISABLE_COARSE_CALDONE 14 14 RESERVED_15_15 15 15 ixDPCSSYS_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1 2 0x1249 7 0 4294967295 RX_VCO_OVRD_SEL 0 0 RX_VCO_FREQ_RST 1 1 RX_VCO_CAL_RST 2 2 RX_VCO_CONTCAL_EN 3 3 DISABLE_INT_CAL_MODE 4 4 DPLL_CAL_UG 5 8 DTB_SEL 9 15 ixDPCSSYS_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2 2 0x124a 4 0 4294967295 FREQ_TUNE_START_VAL 0 9 FREQ_TUNE_CAL_STEPS 10 13 SKIP_RX_VCO_FREQ_TUNE_CAL 14 14 SKIP_RX_VCO_CAL 15 15 ixDPCSSYS_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0 2 0x124b 4 0 4294967295 RX_VCO_STARTUP_TIME 0 6 RX_VCO_UPDATE_TIME 7 10 RX_VCO_CNTR_PWRUP_TIME 11 14 FAST_RX_VCO_WAIT 15 15 ixDPCSSYS_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1 2 0x124c 2 0 4294967295 RX_VCO_CNTR_SETTLE_TIME 0 2 RESERVED_15_3 3 15 ixDPCSSYS_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0 2 0x124d 6 0 4294967295 RX_ANA_CDR_FREQ_TUNE 0 9 RX_ANA_VCO_CNTR_PD 10 10 RX_ANA_VCO_CNTR_EN 11 11 RX_ANA_CDR_STARTUP 12 12 RX_ANA_CDR_VCO_EN 13 13 RESERVED_15_14 14 15 ixDPCSSYS_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1 2 0x124e 7 0 4294967295 RX_VCO_FSM_STATE 0 3 RX_VCO_FREQ_RST 4 4 RX_VCO_CAL_RST 5 5 RX_VCO_CONTCAL_EN 6 6 RX_VCO_CAL_DONE 7 7 DPLL_FREQ_RST 8 8 RESERVED_15_9 9 15 ixDPCSSYS_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_2 2 0x124f 4 0 4294967295 VCO_CNTR_FINAL 0 12 VCOCLK_TOO_FAST 13 13 RX_VCO_CORRECT 14 14 RX_VCO_UP 15 15 ixDPCSSYS_CR2_LANE2_DIG_RX_RX_ALIGN_XAUI_COMM_MASK 2 0x1250 2 0 4294967295 XAUI_COMM_MASK 0 9 RESERVED_15_10 10 15 ixDPCSSYS_CR2_LANE2_DIG_RX_LBERT_CTL 2 0x1251 3 0 4294967295 MODE 0 3 SYNC 4 4 RESERVED_15_5 5 15 ixDPCSSYS_CR2_LANE2_DIG_RX_LBERT_ERR 2 0x1252 2 0 4294967295 COUNT 0 14 OV14 15 15 ixDPCSSYS_CR2_LANE2_DIG_RX_CDR_CDR_CTL_0 2 0x1253 7 0 4294967295 PHDET_EN 0 1 PHDET_EDGE 2 3 PHDET_POL 4 4 PHDET_EN_PR_MODE 5 5 ALWAYS_REALIGN 6 6 DTB_SEL 7 10 RESERVED_15_11 11 15 ixDPCSSYS_CR2_LANE2_DIG_RX_CDR_CDR_CTL_1 2 0x1254 2 0 4294967295 SSC_OFF_CNT0 0 9 SSC_OFF_CNT1 10 15 ixDPCSSYS_CR2_LANE2_DIG_RX_CDR_CDR_CTL_2 2 0x1255 2 0 4294967295 SSC_ON_CNT0 0 8 SSC_ON_CNT1 9 15 ixDPCSSYS_CR2_LANE2_DIG_RX_CDR_CDR_CTL_3 2 0x1256 6 0 4294967295 SSC_OFF_PHUG0 0 2 SSC_OFF_PHUG1 3 5 SSC_OFF_FRUG0 6 8 OVRD_DPLL_GAIN 9 9 PHUG_OVRD_VALUE 10 12 FRUG_OVRD_VALUE 13 15 ixDPCSSYS_CR2_LANE2_DIG_RX_CDR_CDR_CTL_4 2 0x1257 6 0 4294967295 SSC_OFF_FRUG1 0 2 SSC_ON_FRUG0 3 5 SSC_ON_FRUG1 6 8 SSC_ON_PHUG0 9 11 SSC_ON_PHUG1 12 14 RESERVED_15_15 15 15 ixDPCSSYS_CR2_LANE2_DIG_RX_CDR_STAT 2 0x1258 3 0 4294967295 PHUG_VALUE 0 2 FRUG_VALUE 3 5 RESERVED_15_6 6 15 ixDPCSSYS_CR2_LANE2_DIG_RX_DPLL_FREQ 2 0x1259 2 0 4294967295 VAL 0 13 RESERVED_15_14 14 15 ixDPCSSYS_CR2_LANE2_DIG_RX_DPLL_FREQ_BOUND_0 2 0x125a 3 0 4294967295 FREQ_BOUND_EN 0 0 UPPER_FREQ_BOUND 1 10 RESERVED_15_11 11 15 ixDPCSSYS_CR2_LANE2_DIG_RX_DPLL_FREQ_BOUND_1 2 0x125b 2 0 4294967295 LOWER_FREQ_BOUND 0 9 RESERVED_15_10 10 15 ixDPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_0 2 0x1260 4 0 4294967295 N_TOP_ASM1 0 9 N_TGG_ASM1 10 13 START_ASM1 14 14 ADPT_CLK_DIV4_EN 15 15 ixDPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1 2 0x1261 5 0 4294967295 N_WAIT_ASM1 0 6 FAST_AFE_DFE_SETTLE 7 7 CTLE_POLE_OVRD_VAL 8 10 CTLE_POLE_OVRD_EN 11 11 RESERVED_15_12 12 15 ixDPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_2 2 0x1262 3 0 4294967295 TGG_PTTRN_0 0 4 TGG_PTTRN_1 5 9 RESERVED_15_10 10 15 ixDPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3 2 0x1263 8 0 4294967295 CTLE_EN 0 4 VGA_EN 5 5 ATT_EN 6 6 DFE_EN 7 11 EYEHE_EN 12 12 EYEHO_EN 13 13 TGG_EN 14 14 ESL_TWICE_DSL 15 15 ixDPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_4 2 0x1264 4 0 4294967295 CTLE_TH 0 3 VGA_TH 4 7 DFE1_TH 8 11 DFE2_TH 12 15 ixDPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_5 2 0x1265 4 0 4294967295 DFE3_TH 0 3 DFE4_TH 4 7 DFE5_TH 8 11 TH_OFFSET 12 15 ixDPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6 2 0x1266 6 0 4294967295 CTLE_MU 0 2 VGA_MU 3 5 ATT_MU 6 8 VGA_SAT_CNT 9 11 VGA_SAT_CNT_STICKY 12 12 ATT_LOW_TH 13 15 ixDPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_7 2 0x1267 4 0 4294967295 VGA_MIN_SAT 0 4 VGA_LEV_HIGH 5 9 VGA_LEV_LOW 10 14 RESERVED_15_15 15 15 ixDPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8 2 0x1268 6 0 4294967295 DFE1_MU 0 2 DFE2_MU 3 5 DFE3_MU 6 8 DFE4_MU 9 11 DFE5_MU 12 14 RESERVED_15_15 15 15 ixDPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_9 2 0x1269 2 0 4294967295 ERR_SLE_ADPT_INIT 0 7 ERR_SLO_ADPT_INIT 8 15 ixDPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG 2 0x126a 6 0 4294967295 RST_ADPT_ATT 0 0 RST_ADPT_VGA 1 1 RST_ADPT_CTLE_BOOST 2 2 RST_ADPT_CTLE_POLE 3 3 RST_ADPT_TAP1 4 4 RESERVED_15_5 5 15 ixDPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ATT_STATUS 2 0x126b 3 0 4294967295 ATT_ADPT_CODE 0 7 ASM1_DON 8 8 RESERVED_15_9 9 15 ixDPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_VGA_STATUS 2 0x126c 3 0 4294967295 VGA_ADPT_CODE 0 9 ASM1_DONE 10 10 RESERVED_15_11 11 15 ixDPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_CTLE_STATUS 2 0x126d 4 0 4294967295 CTLE_BOOST_ADPT_CODE 0 9 CTLE_POLE_ADPT_CODE 10 12 ASM1_DONE 13 13 RESERVED_15_14 14 15 ixDPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_DFE_TAP1_STATUS 2 0x126e 3 0 4294967295 DFE_TAP1_ADPT_CODE 0 12 ASM1_DONE 13 13 RESERVED_15_14 14 15 ixDPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_DFE_TAP2_STATUS 2 0x126f 3 0 4294967295 DFE_TAP2_ADPT_CODE 0 11 ASM1_DONE 12 12 RESERVED_15_13 13 15 ixDPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_DFE_TAP3_STATUS 2 0x1270 3 0 4294967295 DFE_TAP3_ADPT_CODE 0 11 ASM1_DONE 12 12 RESERVED_15_13 13 15 ixDPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_DFE_TAP4_STATUS 2 0x1271 3 0 4294967295 DFE_TAP4_ADPT_CODE 0 11 ASM1_DONE 12 12 RESERVED_15_13 13 15 ixDPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_DFE_TAP5_STATUS 2 0x1272 3 0 4294967295 DFE_TAP5_ADPT_CODE 0 11 ASM1_DONE 12 12 RESERVED_15_13 13 15 ixDPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_DFE_DATA_EVEN_VDAC_OFST 2 0x1273 2 0 4294967295 DFE_DATA_EVEN_VDAC_OFST 0 7 RESERVED_15_8 8 15 ixDPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_DFE_DATA_ODD_VDAC_OFST 2 0x1274 2 0 4294967295 DFE_DATA_ODD_VDAC_OFST 0 7 RESERVED_15_8 8 15 ixDPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN 2 0x1275 2 0 4294967295 RX_ANA_SLICER_CTRL_E 0 3 RESERVED_15_4 4 15 ixDPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD 2 0x1276 2 0 4294967295 RX_ANA_SLICER_CTRL_O 0 3 RESERVED_15_4 4 15 ixDPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST 2 0x1277 2 0 4294967295 DFE_ERROR_EVEN_VDAC_OFST 0 7 RESERVED_15_8 8 15 ixDPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST 2 0x1278 2 0 4294967295 DFE_ERROR_ODD_VDAC_OFST 0 7 RESERVED_15_8 8 15 ixDPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL 2 0x1279 2 0 4294967295 E_SLO_LVL 0 7 E_SLE_LVL 8 15 ixDPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_RESET 2 0x127a 2 0 4294967295 RESET_ASM1 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1 2 0x127b 4 0 4294967295 DFE_T1_IDAC 0 4 DFE_T2_IDAC 5 9 DCC_START_IDAC 10 14 RESERVED_15_15 15 15 ixDPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2 2 0x127c 3 0 4294967295 DFE_DAT_EVEN_VDAC 0 4 DFE_DAT_ODD_VDAC 5 9 RESERVED_15_10 10 15 ixDPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3 2 0x127d 3 0 4294967295 DFE_ERR_EVEN_VDAC 0 4 DFE_ERR_ODD_VDAC 5 9 RESERVED_15_10 10 15 ixDPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_CR_BANK_ADDR 2 0x127e 1 0 4294967295 ADDR 0 15 ixDPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_CR_BANK_DATA 2 0x127f 1 0 4294967295 DATA 0 15 ixDPCSSYS_CR2_LANE2_DIG_RX_STAT_LD_VAL_1 2 0x1280 2 0 4294967295 SC1_LD_VAL 0 14 SC1_START 15 15 ixDPCSSYS_CR2_LANE2_DIG_RX_STAT_DATA_MSK 2 0x1281 1 0 4294967295 DATA_MSK_15_0 0 15 ixDPCSSYS_CR2_LANE2_DIG_RX_STAT_MATCH_CTL0 2 0x1282 4 0 4294967295 PTTRN_MSK_CR1A_4_0 0 4 PTTRN_CR1A_4_0 5 9 DATA_MSK_19_16 10 13 SCOPE_DLY 14 15 ixDPCSSYS_CR2_LANE2_DIG_RX_STAT_MATCH_CTL1 2 0x1283 5 0 4294967295 PTTRN_CR1B_EN 0 0 PTTRN_MSK_CR1B_4_0 1 5 PTTRN_CR1B_4_0 6 10 PTTRN_CR1A_ADPT_EN 11 11 RESERVED_15_12 12 15 ixDPCSSYS_CR2_LANE2_DIG_RX_STAT_STAT_CTL0 2 0x1284 10 0 4294967295 RESERVED_0 0 0 CORR_SHFT_SEL_VGA 1 1 CORR_SHFT_SEL 2 2 CORR_SRC_SEL 3 4 CORR_MODE_EN 5 5 STAT_SHFT_SEL 6 9 STAT_SRC_SEL 10 12 STAT_RXCLK_SEL 13 13 SC_TIMER_MODE 14 14 SKIP_EN 15 15 ixDPCSSYS_CR2_LANE2_DIG_RX_STAT_STAT_CTL1 2 0x1285 13 0 4294967295 STAT_CNT_0_EN 0 0 STAT_CNT_1_EN 1 1 STAT_CNT_2_EN 2 2 STAT_CNT_3_EN 3 3 STAT_CNT_4_EN 4 4 STAT_CNT_5_EN 5 5 STAT_CNT_6_EN 6 6 RESERVED_8_7 7 8 SC_PAUSE 9 9 STAT_CLK_EN 10 10 DATA_DLY_SEL 11 12 VLD_LOSS_CLR 13 13 VLD_CTL 14 15 ixDPCSSYS_CR2_LANE2_DIG_RX_STAT_SMPL_CNT1 2 0x1286 2 0 4294967295 SMPL_CNT1 0 14 SMPL_CNT1_DONE 15 15 ixDPCSSYS_CR2_LANE2_DIG_RX_STAT_STAT_CNT_0 2 0x1287 2 0 4294967295 STAT_CNT_0 0 14 SMPL_CNT1_DONE 15 15 ixDPCSSYS_CR2_LANE2_DIG_RX_STAT_STAT_CNT_1 2 0x1288 2 0 4294967295 STAT_CNT_1 0 14 SMPL_CNT1_DONE 15 15 ixDPCSSYS_CR2_LANE2_DIG_RX_STAT_STAT_CNT_2 2 0x1289 2 0 4294967295 STAT_CNT_2 0 14 SMPL_CNT1_DONE 15 15 ixDPCSSYS_CR2_LANE2_DIG_RX_STAT_STAT_CNT_3 2 0x128a 2 0 4294967295 STAT_CNT_3 0 14 SMPL_CNT1_DONE 15 15 ixDPCSSYS_CR2_LANE2_DIG_RX_STAT_STAT_CNT_4 2 0x128b 2 0 4294967295 STAT_CNT_4 0 14 SMPL_CNT1_DONE 15 15 ixDPCSSYS_CR2_LANE2_DIG_RX_STAT_STAT_CNT_5 2 0x128c 2 0 4294967295 STAT_CNT_5 0 14 SMPL_CNT1_DONE 15 15 ixDPCSSYS_CR2_LANE2_DIG_RX_STAT_STAT_CNT_6 2 0x128d 2 0 4294967295 STAT_CNT_6 0 14 SMPL_CNT1_DONE 15 15 ixDPCSSYS_CR2_LANE2_DIG_RX_STAT_CAL_COMP_CLK_CTL 2 0x128e 3 0 4294967295 PRECHRGE_CNT 0 2 REF_DIV_CNT 3 5 RESERVED_15_6 6 15 ixDPCSSYS_CR2_LANE2_DIG_RX_STAT_MATCH_CTL2 2 0x128f 2 0 4294967295 PTTRN_CR1A_19_5 0 14 RESERVED_15_15 15 15 ixDPCSSYS_CR2_LANE2_DIG_RX_STAT_MATCH_CTL3 2 0x1290 2 0 4294967295 PTTRN_MSK_CR1A_19_5 0 14 RESERVED_15_15 15 15 ixDPCSSYS_CR2_LANE2_DIG_RX_STAT_MATCH_CTL4 2 0x1291 2 0 4294967295 PTTRN_CR1B_19_5 0 14 RESERVED_15_15 15 15 ixDPCSSYS_CR2_LANE2_DIG_RX_STAT_MATCH_CTL5 2 0x1292 2 0 4294967295 PTTRN_MSK_CR1B_19_5 0 14 RESERVED_15_15 15 15 ixDPCSSYS_CR2_LANE2_DIG_RX_STAT_STAT_CTL2 2 0x1293 4 0 4294967295 DATA_DLY_SEL_2 0 0 SCOPE_DLY_2 1 1 DISABLE_SAMPLE_COUNT 2 2 RESERVED_15_3 3 15 ixDPCSSYS_CR2_LANE2_DIG_RX_STAT_STAT_STOP 2 0x1294 2 0 4294967295 SC1_STOP 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR2_LANE2_DIG_MPHY_RX_PWM_CTL 2 0x1295 3 0 4294967295 RX_PWM_POL 0 0 RX_PWM_DATA_POL 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR2_LANE2_DIG_MPHY_RX_TERM_LS_CTL 2 0x1296 2 0 4294967295 RX_TERM_LCC_CNT 0 2 RESERVED_15_3 3 15 ixDPCSSYS_CR2_LANE2_DIG_MPHY_RX_ANA_PWM_CLK_STABLE_CNT 2 0x1297 2 0 4294967295 PWM_CLK_STABLE_CNT 0 3 RESERVED_15_4 4 15 ixDPCSSYS_CR2_LANE2_DIG_ANA_TX_OVRD_OUT 2 0x12a0 15 0 4294967295 TX_ANA_CLK_SHIFT 0 0 TX_ANA_DATA_EN 1 1 TX_ANA_REFGEN_EN 2 2 TX_ANA_VCM_HOLD 3 3 TX_ANA_CLK_EN 4 4 TX_ANA_WORD_CLK_EN 5 5 TX_ANA_MPLLA_CLK_EN 6 6 TX_ANA_MPLLB_CLK_EN 7 7 TX_ANA_RESET 8 8 TX_ANA_SERIAL_EN 9 9 TX_ANA_DATA_RATE 10 11 RESERVED 12 12 TX_DIV4_EN 13 13 TX_RXDET_EN 14 14 TX_OVRD_EN 15 15 ixDPCSSYS_CR2_LANE2_DIG_ANA_TX_TERM_CODE_OVRD_OUT 2 0x12a1 5 0 4294967295 TX_TERM_CODE 0 9 TX_TERM_OVRD_EN 10 10 TX_DRV_SRC 11 12 TX_DRV_SRC_OVRD_EN 13 13 RESERVED_15_14 14 15 ixDPCSSYS_CR2_LANE2_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT 2 0x12a2 3 0 4294967295 TX_TERM_DN_CLK 0 0 TX_TERM_CLK_SELF_CLEAR_DISABLE 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR2_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_0 2 0x12a3 3 0 4294967295 TX_ANA_LOAD_CLK 0 0 TX_ANA_CTRL_LEG_PULL_EN_13_0 1 14 TX_EQ_OVRD_EN 15 15 ixDPCSSYS_CR2_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_1 2 0x12a4 2 0 4294967295 TX_ANA_CTRL_LEG_PULL_EN_19_14 0 5 RESERVED_15_6 6 15 ixDPCSSYS_CR2_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_2 2 0x12a5 4 0 4294967295 RESERVED 0 2 TX_ANA_CTRL_EQ_MUX_SEL 3 6 TX_ANA_CTRL_PRE 7 12 RESERVED_15_13 13 15 ixDPCSSYS_CR2_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_3 2 0x12a6 2 0 4294967295 TX_ANA_CTRL_POST 0 8 RESERVED_15_9 9 15 ixDPCSSYS_CR2_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_4 2 0x12a7 1 0 4294967295 TX_ANA_CTRL_LEG_PULL_DIR_19_4 0 15 ixDPCSSYS_CR2_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_5 2 0x12a8 2 0 4294967295 TX_ANA_CTRL_LEG_PULL_DIR_3_0 0 3 RESERVED_15_4 4 15 ixDPCSSYS_CR2_LANE2_DIG_ANA_RX_CTL_OVRD_OUT 2 0x12a9 9 0 4294967295 RESERVED 0 0 RX_ANA_DATA_RATE 1 2 RX_ANA_WORD_CLK_EN 3 3 RX_ANA_DIV4_EN 4 4 RX_ANA_DFE_TAPS_EN 5 5 RX_ANA_ADAPTATION_EN 6 6 RX_LBK_CLK_EN 7 7 RX_CTL_OVRD_EN 8 8 RESERVED_15_9 9 15 ixDPCSSYS_CR2_LANE2_DIG_ANA_RX_PWR_OVRD_OUT 2 0x12aa 9 0 4294967295 RX_ANA_AFE_EN 0 0 RX_ANA_CLK_VREG_EN 1 1 RX_ANA_CLK_DCC_EN 2 2 RX_ANA_CLK_EN 3 3 RX_ANA_CDR_EN 4 4 RX_ANA_DESERIAL_EN 5 5 RX_PWR_OVRD_EN 6 6 RX_ANA_FAST_START 7 7 RESERVED_15_8 8 15 ixDPCSSYS_CR2_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0 2 0x12ab 7 0 4294967295 RX_ANA_CDR_VCO_EN 0 0 RX_ANA_CDR_STARTUP 1 1 RX_VCO_CDR_OVRD_EN 2 2 RX_ANA_CDR_FREQ_TUNE 3 12 RX_ANA_VCO_CNTR_EN 13 13 RX_ANA_VCO_CNTR_CLK 14 14 RX_CDR_FREQ_TUNE_OVRD_EN 15 15 ixDPCSSYS_CR2_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_1 2 0x12ac 3 0 4294967295 RX_ANA_CDR_VCO_LOWFREQ 0 0 RX_ANA_VCO_CNTR_PD 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR2_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_2 2 0x12ad 3 0 4294967295 RX_ANA_CDR_FREQ_TUNE_CLK 0 0 CDR_FREQ_TUNE_CLK_SELF_CLEAR_DISABLE 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR2_LANE2_DIG_ANA_RX_CAL 2 0x12ae 7 0 4294967295 RX_ANA_CAL_MUXA_SEL 0 4 RX_ANA_CAL_MUXB_SEL 5 9 RX_ANA_CAL_LPFBYP_EN 10 10 RESERVED 11 11 RX_ANA_SLICER_CAL_EN 12 12 RX_ANA_CAL_MODE 13 14 RX_ANA_CAL_COMP_EN 15 15 ixDPCSSYS_CR2_LANE2_DIG_ANA_RX_DAC_CTRL 2 0x12af 2 0 4294967295 RX_ANA_CAL_DAC_CTRL 0 7 RESERVED_15_8 8 15 ixDPCSSYS_CR2_LANE2_DIG_ANA_RX_DAC_CTRL_OVRD 2 0x12b0 2 0 4294967295 RX_CAL_DAC_CTRL_OVRD 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR2_LANE2_DIG_ANA_RX_DAC_CTRL_SEL 2 0x12b1 2 0 4294967295 RX_ANA_CAL_DAC_CTRL_SEL 0 4 RESERVED_15_5 5 15 ixDPCSSYS_CR2_LANE2_DIG_ANA_RX_AFE_ATT_VGA 2 0x12b2 5 0 4294967295 RX_ANA_AFE_ATT_LVL 0 2 RX_ANA_AFE_GAIN 3 6 RESERVED 7 10 RX_AFE_OVRD_EN 11 11 RESERVED_15_12 12 15 ixDPCSSYS_CR2_LANE2_DIG_ANA_RX_AFE_CTLE 2 0x12b3 3 0 4294967295 RESERVED 0 2 RX_ANA_AFE_CTLE_BOOST 3 7 RESERVED_15_8 8 15 ixDPCSSYS_CR2_LANE2_DIG_ANA_RX_SCOPE 2 0x12b4 7 0 4294967295 RX_ANA_SCOPE_EN 0 0 RX_ANA_SCOPE_SEL 1 2 RX_ANA_SCOPE_PH_CLK 3 3 RX_ANA_SCOPE_PHASE 4 11 RX_ANA_SCOPE_CLK_EN 12 12 RX_SCOPE_SELF_CLEAR_DISABLE 13 13 RESERVED_15_14 14 15 ixDPCSSYS_CR2_LANE2_DIG_ANA_RX_SLICER_CTRL 2 0x12b5 4 0 4294967295 RX_ANA_SLICER_CTRL_E 0 3 RX_ANA_SLICER_CTRL_O 4 7 RX_ANA_SLICER_CTRL_OVRD_EN 8 8 RESERVED_15_9 9 15 ixDPCSSYS_CR2_LANE2_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST 2 0x12b6 2 0 4294967295 RX_ANA_IQ_PHASE_ADJUST 0 6 RESERVED_15_7 7 15 ixDPCSSYS_CR2_LANE2_DIG_ANA_RX_ANA_IQ_SENSE_EN 2 0x12b7 2 0 4294967295 RX_ANA_IQ_SENSE_EN 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR2_LANE2_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN 2 0x12b8 3 0 4294967295 RX_ANA_CAL_DAC_CTRL_EN 0 0 DAC_CTRL_SELF_CLEAR_DISABLE 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR2_LANE2_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE 2 0x12b9 3 0 4294967295 RX_ANA_AFE_UPDATE_EN 0 0 AFE_UPDATE_SELF_CLEAR_DISABLE 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR2_LANE2_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK 2 0x12ba 3 0 4294967295 RX_ANA_IQ_PHASE_ADJUST_CLK 0 0 PHASE_ADJUST_SELF_CLEAR_DISABLE 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR2_LANE2_DIG_ANA_STATUS_0 2 0x12bb 9 0 4294967295 TX_ANA_CLK_SHIFT_ACK 0 0 TX_ANA_RXDETP_RESULT 1 1 TX_ANA_RXDETM_RESULT 2 2 TX_ANA_LOOPBACK_EN 3 3 TX_ANA_CLK_LB_EN 4 4 RX_ANA_CAL_RESULT 5 5 RX_ANA_SCOPE_DATA 6 6 TX_ANA_DCC_CAL_RESULT 7 7 TX_ANA_CTRL_EQ_MUX 8 15 ixDPCSSYS_CR2_LANE2_DIG_ANA_STATUS_1 2 0x12bc 2 0 4294967295 RX_ANA_VCO_CNTR 0 12 RESERVED_15_13 13 15 ixDPCSSYS_CR2_LANE2_DIG_ANA_RX_TERM_CODE_OVRD_OUT 2 0x12bd 3 0 4294967295 RX_TERM_CODE 0 5 RX_TERM_OVRD_EN 6 6 RESERVED_15_7 7 15 ixDPCSSYS_CR2_LANE2_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT 2 0x12be 3 0 4294967295 RX_TERM_CLK 0 0 RX_TERM_CLK_SELF_CLEAR_DISABLE 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR2_LANE2_DIG_ANA_MPHY_OVRD_OUT 2 0x12bf 9 0 4294967295 RX_ANA_SQ_CTRL_TRESH 0 2 RX_ANA_SQ_CTRL_TRESH_OVRD_EN 3 3 RX_ANA_SQ_CTRL_RESP 4 5 RX_ANA_SQ_CTRL_RESP_OVRD_EN 6 6 RX_ANA_PWM_EN 7 7 RX_ANA_PWM_EN_OVRD_EN 8 8 RX_ANA_PWM_CLK_SEL 9 10 RX_ANA_PWM_CLK_SEL_OVRD_EN 11 11 RESERVED_15_12 12 15 ixDPCSSYS_CR2_LANE2_DIG_ANA_SIGDET_OVRD_OUT_1 2 0x12c0 7 0 4294967295 RX_ANA_SIGDET_HF_THRESH 0 2 RX_ANA_SIGDET_HF_THRESH_OVRD_EN 3 3 RX_ANA_SIGDET_HF_CAL_TUNE 4 9 RX_ANA_SIGDET_CAL_TUNE_OVRD_EN 10 10 RX_ANA_SIGDET_CAL_EN 11 11 RX_ANA_SIGDET_CAL_EN_OVRD_EN 12 12 RESERVED_15_13 13 15 ixDPCSSYS_CR2_LANE2_DIG_ANA_SIGDET_OVRD_OUT_2 2 0x12c1 7 0 4294967295 RX_ANA_SIGDET_LF_THRESH 0 2 RX_ANA_SIGDET_LF_THRESH_OVRD_EN 3 3 RX_ANA_SIGDET_LF_FILTER_EN 4 4 RX_ANA_SIGDET_LF_FILTER_EN_OVRD_EN 5 5 RX_ANA_SIGDET_CAL_TUNE 6 11 RX_ANA_SIGDET_CAL_TUNE_OVRD_EN 12 12 RESERVED_15_13 13 15 ixDPCSSYS_CR2_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT 2 0x12c2 8 0 4294967295 TX_ANA_DCC_CAL_RANGE 0 1 TX_ANA_DCC_CAL_RANGE_OVRD_EN 2 2 TX_ANA_DCC_CAL_COMP_EN 3 3 TX_ANA_DCC_CAL_COMP_EN_OVRD_EN 4 4 TX_ANA_DCC_CAL_CTRL 5 12 TX_ANA_DCC_CAL_CTRL_OVRD_EN 13 13 TX_ANA_DCC_CAL_CTRL_EN 14 14 TX_ANA_DCC_CAL_CTRL_EN_OVRD_EN 15 15 ixDPCSSYS_CR2_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2 2 0x12c3 5 0 4294967295 TX_ANA_DCC_CAL_CTRL_SEL 0 2 TX_ANA_DCC_CAL_CTRL_SEL_OVRD_EN 3 3 TX_ANA_DCC_CLK_COMP 4 4 TX_ANA_DCC_CLK_COMP_OVRD_EN 5 5 RESERVED_15_6 6 15 ixDPCSSYS_CR2_LANE2_DIG_ANA_TX_OVRD_OUT_2 2 0x12c4 6 0 4294967295 TX_ANA_FAST_START 0 0 TX_ANA_FAST_START_OVRD_EN 1 1 TX_CLK_LB_EN 2 2 TX_CLK_LB_EN_OVRD_EN 3 3 TX_ACJTAG_EN 4 4 RESERVED_15_5 5 15 ixDPCSSYS_CR2_LANE2_ANA_TX_OVRD_MEAS 2 0x12e0 9 0 4294967295 OVRD_CLK_SHIFT 0 0 CLK_SHIFT_REG 0 0 MEAS_ATB_CAL_MUX 0 0 MEAS_ATB_CAL_COMP 0 0 OVRD_VCM_HOLD 0 0 VCM_HOLD_REG 0 0 PULL_UP_REG 0 0 PULL_DN_REG 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR2_LANE2_ANA_TX_PWR_OVRD 2 0x12e1 9 0 4294967295 OVRD_TX_LOOPBACK 0 0 LOOPBACK_EN_REG 0 0 REFGEN_EN_REG 0 0 CLK_DIV_EN_REG 0 0 DATA_EN_REG_INT 0 0 CLK_EN_REG 0 0 SERIAL_EN_REG 0 0 OVRD_EN 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR2_LANE2_ANA_TX_ALT_BUS 2 0x12e2 6 0 4294967295 DRV_SOURCE_REG 0 0 OVRD_ALT_BUS 0 0 ATB_S_ENABLE 0 0 TX_ALT_RINGO 0 0 JTAG_DATA_REG 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR2_LANE2_ANA_TX_ATB1 2 0x12e3 9 0 4294967295 MEAS_ATB_GD 0 0 MEAS_ATB_VDDH 0 0 OVERRIDE_RXDETREF 0 0 MEAS_ATB_VPTX 0 0 OVERRIDE_REGREF 0 0 MEAS_ATB_VREG_DRV 0 0 MEAS_ATB_VREG 0 0 MEAS_ATB_VPH_HALF 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR2_LANE2_ANA_TX_ATB2 2 0x12e4 9 0 4294967295 MEAS_ATB_VCM 0 0 MEAS_ATB_CAL_VDAC_CM 0 0 MEAS_ATB_CAL_VDAC_DIFF 0 0 MEAS_ATB_TXM 0 0 MEAS_ATB_TXP 0 0 MEAS_ATB_RXDETREF 0 0 LFPS_HIGH_PRIORITY 0 0 OSC_DIV4_EN 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR2_LANE2_ANA_TX_DCC_DAC 2 0x12e5 2 0 4294967295 DCC_DAC_REG 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR2_LANE2_ANA_TX_DCC_CTRL1 2 0x12e6 7 0 4294967295 NC0 0 0 OVRD_DCC_DAC_CTRL_SEL 0 0 DCC_DAC_CTRL_SEL_REG 0 0 OVRD_DCC_DAC_CTRL_EN 0 0 DCC_DAC_CTRL_EN_REG 0 0 OVRD_DCC_DAC_REG 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR2_LANE2_ANA_TX_TERM_CODE 2 0x12e7 2 0 4294967295 TERM_CODE_REG_70 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR2_LANE2_ANA_TX_TERM_CODE_CTRL 2 0x12e8 8 0 4294967295 VREG_BOOST_1 0 0 OVRD_UPDATE_TERM 0 0 UPDATE_TERM_REG 0 0 OVRD_RESET_TERM 0 0 RESET_TERM_REG 0 0 OVRD_TERM_CODE 0 0 TERM_CODE_REG_98 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR2_LANE2_ANA_TX_OVRD_CLK 2 0x12e9 9 0 4294967295 VREG_BOOST_0 0 0 CLK_LB_EN_REG 0 0 OVRD_LB_EN 0 0 MPLLB_CLK_EN_REG 0 0 MPLLA_CLK_EN_REG 0 0 OVRD_MPLLAB_EN 0 0 WORD_CLK_EN_REG 0 0 OVRD_WORD_CLK_EN 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR2_LANE2_ANA_TX_MISC1 2 0x12ea 8 0 4294967295 MEAS_ATB_CAL_CLK_ALIGN 0 0 OVRD_DCC_DAC_CTRL_RANGE 0 0 DCC_DAC_CTRL_RANGE_REG 0 0 OVRD_VREF_SEL 0 0 VREF_SEL_REG 0 0 FORCE_ATB_TXM 0 0 FORCE_ATB_TXP 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR2_LANE2_ANA_TX_MISC2 2 0x12eb 8 0 4294967295 TX_PEAKING_LVL 0 0 VREG_CP_GAIN_CTRL 0 0 TX_SLEW_EN 0 0 EN_INV_POST 0 0 EN_INV_PRE 0 0 TX_VREG_EN_BYP 0 0 TX_VDRIVER_PULLDN_EN 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR2_LANE2_ANA_TX_MISC3 2 0x12ec 4 0 4294967295 TX_VREG_OVRD_RING_CTRL 0 0 TX_DCC_LOWV 0 0 NC7_2 2 7 RESERVED_15_8 8 15 ixDPCSSYS_CR2_LANE2_ANA_TX_RESERVED2 2 0x12ed 2 0 4294967295 NC7_0 0 7 RESERVED_15_8 8 15 ixDPCSSYS_CR2_LANE2_ANA_TX_RESERVED3 2 0x12ee 2 0 4294967295 NC7_0 0 7 RESERVED_15_8 8 15 ixDPCSSYS_CR2_LANE2_ANA_TX_RESERVED4 2 0x12ef 2 0 4294967295 NC7_0 0 7 RESERVED_15_8 8 15 ixDPCSSYS_CR2_LANE2_ANA_RX_CLK_1 2 0x12f0 8 0 4294967295 CDR_VCO_STARTUP_CODE 0 0 CDR_VCO_TEMP_COMP_EN 0 0 CDR_VCO_USE_UNCAL_BIAS 0 0 OVERRIDE_CDR_EN 0 0 OVRD_CLK_EN 0 0 CLK_EN_REG 0 0 NC7 7 7 RESERVED_15_8 8 15 ixDPCSSYS_CR2_LANE2_ANA_RX_CLK_2 2 0x12f1 5 0 4294967295 IQ_PHASE_ADJUST_REG 0 0 OVRD_IQ_PHASE_ADJUST 0 0 RX_LOOPBACK_CLK_REG 0 0 OVRD_RX_LOOPBACK_CLK 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR2_LANE2_ANA_RX_CDR_DES 2 0x12f2 7 0 4294967295 OVRD_WORD_CLK_EN 0 0 WORD_CLK_EN_REG 0 0 PHDET_ODD_REG 0 0 PHDET_EVEN_REG 0 0 SIGDET_VREF_EXT_EN 0 0 NC7_5 5 7 RESERVED_15_8 8 15 ixDPCSSYS_CR2_LANE2_ANA_RX_SLC_CTRL 2 0x12f3 3 0 4294967295 RX_SLICER_CTRL_O_REG 0 0 RX_SLICER_CTRL_E_REG 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR2_LANE2_ANA_RX_PWR_CTRL1 2 0x12f4 8 0 4294967295 OVRD_ACJT_EN 0 0 ACJT_EN_REG 0 0 OVRD_AFE_EN 0 0 AFE_EN_REG 0 0 AFE_CM_SEL 0 0 ATT_PULLDN_EN 0 0 NC7_7 7 7 RESERVED_15_8 8 15 ixDPCSSYS_CR2_LANE2_ANA_RX_PWR_CTRL2 2 0x12f5 9 0 4294967295 OVRD_DFE_EN 0 0 DFE_EN_REG 0 0 OVRD_DESERIAL_EN 0 0 DESERIAL_EN_REG 0 0 OVRD_LOOPBACK_EN 0 0 LOOPBACK_EN_REG 0 0 OVRD_FAST_START 0 0 FAST_START_REG 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR2_LANE2_ANA_RX_SQ 2 0x12f6 7 0 4294967295 SQ_CTRL_RESP_REG 0 0 OVRD_SQ_CTRL_RESP 0 0 NC4_3 3 4 SQ_CTRL_TRESH_REG 0 0 OVRD_SQ_CTRL_TRESH 0 0 AFE_LOOPBACK_SEL 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR2_LANE2_ANA_RX_CAL1 2 0x12f7 5 0 4294967295 DFE_TAPS_EN_REG 0 0 OVRD_DFE_TAPS_EN 0 0 CAL_MUXB_SEL_REG 0 0 OVRD_CAL_MUXB_SEL 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR2_LANE2_ANA_RX_CAL2 2 0x12f8 5 0 4294967295 AFE_PD_EQ_OFFSET 0 0 CAL_IDACS_USE_UNCAL 0 0 CAL_MUXA_SEL_REG 0 0 OVRD_CAL_MUXA_SEL 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR2_LANE2_ANA_RX_ATB_REGREF 2 0x12f9 8 0 4294967295 OVERRIDE_REGREF_VCO 0 0 OVERRIDE_REGREF_CLK 0 0 OVERRIDE_REGREF_IQC 0 0 BOOST_REGREF_IQC 0 0 OVRD_RX_SLICER_CTRL 0 0 OVRD_RX_TERM_AC_DCZ 0 0 RX_TERM_AC_DCZ_REG 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR2_LANE2_ANA_RX_ATB_MEAS1 2 0x12fa 9 0 4294967295 MASTER_ATB_EN 0 0 MEAS_ATB_VP 0 0 MEAS_ATB_GD 0 0 MEAS_ATB_VREG_VCO 0 0 MEAS_ATB_VREG_CLK 0 0 MEAS_ATB_VREG_IQC 0 0 REGS_FB_DIV_CTRL 0 0 RX_VREG_CLK_BYPASS 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR2_LANE2_ANA_RX_ATB_MEAS2 2 0x12fb 2 0 4294967295 MEAS_ATB_RX 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR2_LANE2_ANA_RX_ATB_MEAS3 2 0x12fc 7 0 4294967295 MEAS_ATB_CDR_VCO_GD 0 0 MEAS_ATB_CDR_VCO_VIREF_200U 0 0 MEAS_ATB_VIBIAS_CDR_VCO 0 0 MEAS_ATB_CDR_VCO_VOSC 0 0 MEAS_ATB_CAL_MUX 0 0 RX_VREG_OVERRIDE_RING_CTRL 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR2_LANE2_ANA_RX_ATB_MEAS4 2 0x12fd 3 0 4294967295 MEAS_ATB_CAL_VREF 0 0 NC7 7 7 RESERVED_15_8 8 15 ixDPCSSYS_CR2_LANE2_ANA_RX_ATB_FRC 2 0x12fe 2 0 4294967295 FRC_ATB_CAL_VREF 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR2_LANE2_ANA_RX_RESERVED1 2 0x12ff 2 0 4294967295 NC7_0 0 7 RESERVED_15_8 8 15 ixDPCSSYS_CR2_LANE3_DIG_ASIC_LANE_OVRD_IN 2 0x1300 5 0 4294967295 LANE_TX2RX_SER_LB 0 0 LANE_RX2TX_PAR_LB 1 1 EN 2 2 RX_ACJTAG_EN 3 3 RESERVED_15_4 4 15 ixDPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_0 2 0x1301 12 0 4294967295 REQ 0 0 REQ_OVRD_EN 1 1 PSTATE 2 3 PSTATE_OVRD_EN 4 4 RATE 5 7 RATE_OVRD_EN 8 8 WIDTH 9 10 WIDTH_OVRD_EN 11 11 MPLLB_SEL 12 12 MPLLB_SEL_OVRD_EN 13 13 DATA_EN 14 14 DATA_EN_OVRD_EN 15 15 ixDPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_1 2 0x1302 11 0 4294967295 NYQUIST_DATA 0 0 DISABLE 1 1 BEACON_EN 2 2 EN 3 3 TX_MAIN_CURSOR 4 9 MAIN_OVRD_EN 10 10 ASYNC_DRV_EN 11 11 ASYNC_DRV_OVRD_EN 12 12 TX_VREGDRV_BYP_OVRD 13 13 TX_VREGDRV_BYP_OVRD_EN 14 14 RESERVED_15_15 15 15 ixDPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_2 2 0x1303 6 0 4294967295 TX_PRE_CURSOR 0 5 PRE_OVRD_EN 6 6 TX_POST_CURSOR 7 12 POST_OVRD_EN 13 13 HDMIMODE_EN 14 14 HDMIMODE_ENABLE_OVRD_EN 15 15 ixDPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_3 2 0x1304 15 0 4294967295 CLK_RDY 0 0 CLK_RDY_OVRD_EN 1 1 DETECT_RX_REQ 2 2 DETECT_RX_REQ_OVRD_EN 3 3 INVERT 4 4 INVERT_OVRD_EN 5 5 LPD 6 6 LPD_OVRD_EN 7 7 TX_DC_COUP_EN 8 8 TX_DC_COUP_EN_OVRD_EN 9 9 PMA_EXTENDED_FIFO_EN 10 10 PMA_EXTENDED_FIFO_EN_OVRD_EN 11 11 TX_MPHY_MODE_EN 12 12 TX_MPHY_MODE_EN_OVRD_EN 13 13 RESERVED_15_14 14 15 ixDPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_4 2 0x1305 3 0 4294967295 RESET 0 0 RESET_OVRD_EN 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_OUT 2 0x1306 5 0 4294967295 TX_ACK 0 0 EN_TX_ACK 1 1 DETRX_RESULT 2 2 EN_DETRX_RESULT 3 3 RESERVED_15_4 4 15 ixDPCSSYS_CR2_LANE3_DIG_ASIC_RX_OVRD_OUT_0 2 0x130f 9 0 4294967295 ACK 0 0 ACK_OVRD_EN 1 1 ADAPT_STS 2 3 ADAPT_STS_OVRD_EN 4 4 RX_ASYNC_DATA 5 5 RX_ASYNC_DATA_OVRD_EN 6 6 RX_SQ_WEAKKEEP_OUT 7 7 RX_SQ_WEAKKEEP_OUT_OVRD_EN 8 8 RESERVED_15_9 9 15 ixDPCSSYS_CR2_LANE3_DIG_ASIC_LANE_ASIC_IN 2 0x1310 3 0 4294967295 LANE_TX2RX_SER_LB 0 0 LANE_RX2TX_PAR_LB 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR2_LANE3_DIG_ASIC_TX_ASIC_IN_0 2 0x1311 12 0 4294967295 CLK_RDY 0 0 RESET 1 1 INVERT 2 2 DATA_EN 3 3 REQ 4 4 LPD 5 5 PSTATE 6 7 RATE 8 10 WIDTH 11 12 MPLLB_SEL 13 13 DETECT_RX_REQ 14 14 DISABLE 15 15 ixDPCSSYS_CR2_LANE3_DIG_ASIC_TX_ASIC_IN_1 2 0x1312 7 0 4294967295 BEACON_EN 0 0 TX_MAIN_CURSOR 1 6 TX_ASYNC_EN 7 7 TX_ASYNC_DATA 8 8 TX_ASYNC_DRV_EN 9 9 TX_VREGDRV_BYP 10 10 RESERVED_15_11 11 15 ixDPCSSYS_CR2_LANE3_DIG_ASIC_TX_ASIC_IN_2 2 0x1313 3 0 4294967295 TX_PRE_CURSOR 0 5 TX_POST_CURSOR 6 11 RESERVED_15_12 12 15 ixDPCSSYS_CR2_LANE3_DIG_ASIC_TX_ASIC_OUT 2 0x1314 3 0 4294967295 TX_ACK 0 0 DETRX_RESULT 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR2_LANE3_DIG_ASIC_RX_ASIC_OUT_0 2 0x131b 4 0 4294967295 ACK 0 0 VALID 1 1 ADAPT_STS 2 3 RESERVED_15_4 4 15 ixDPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_5 2 0x131d 15 0 4294967295 RPTR_EN_MASTER_LANE 0 0 RPTR_EN_MASTER_LANE_OVRD_EN 1 1 DIG_CLK_EN_OTHER_LANE 2 2 DIG_CLK_EN_OTHER_LANE_OVRD_EN 3 3 DIG_CLK_STATE_MASTER_LANE 4 4 DIG_CLK_STATE_MASTER_LANE_OVRD_EN 5 5 SHIFT_MASTER_LANE 6 6 SHIFT_MASTER_LANE_ORVD_EN 7 7 SHIFT_ACK_OTHER_LANE 8 8 SHIFT_ACK_OTHER_LANE_OVRD_EN 9 9 LANE_MASTER 10 10 LANE_MASTER_OVRD_IN_EN 11 11 TX_DWORD_CLK_SYNC_OVRD 12 12 TX_DWORD_CLK_SYNC_OVRD_EN 13 13 RESERVED_15_14 14 15 ixDPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_OUT_1 2 0x131e 11 0 4294967295 RPTR_EN_OUT 0 0 RPTR_EN_OUT_OVRD_EN 1 1 DIG_CLK_EN_OUT 2 2 DIG_CLK_EN_OUT_OVRD_EN 3 3 DIG_CLK_STATE_OUT 4 4 DIG_CLK_STATE_OUT_OVRD_EN 5 5 SHIFT_OUT 6 6 SHIFT_OUT_OVRD_EN 7 7 SHIFT_ACK_OUT 8 8 SHIFT_ACK_OUT_OVRD_EN 9 9 RESERVED_15_10 10 15 ixDPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0 2 0x1320 11 0 4294967295 TX_P0_ANA_REFGEN_EN 0 0 TX_P0_ANA_VCM_HOLD 1 1 TX_P0_ANA_CLK_EN 2 2 TX_P0_ANA_WORD_CLK_EN 3 3 TX_P0_ANA_RESET 4 4 TX_P0_ANA_SERIAL_EN 5 5 TX_P0_DIG_CLK_EN 6 6 TX_P0_DATA_EN 7 7 TX_P0_ALLOW_RXDET 8 8 TX_P0_ANA_DCC_COMP_CAL_EN 9 9 RESERVED_15_10 10 15 ixDPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S 2 0x1321 11 0 4294967295 TX_P0S_ANA_REFGEN_EN 0 0 TX_P0S_ANA_VCM_HOLD 1 1 TX_P0S_ANA_CLK_EN 2 2 TX_P0S_ANA_WORD_CLK_EN 3 3 TX_P0S_ANA_RESET 4 4 TX_P0S_ANA_SERIAL_EN 5 5 TX_P0S_DIG_CLK_EN 6 6 TX_P0S_DATA_EN 7 7 TX_P0S_ALLOW_RXDET 8 8 TX_P0S_ANA_DCC_COMP_CAL_EN 9 9 RESERVED_15_10 10 15 ixDPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1 2 0x1322 11 0 4294967295 TX_P1_ANA_REFGEN_EN 0 0 TX_P1_ANA_VCM_HOLD 1 1 TX_P1_ANA_CLK_EN 2 2 TX_P1_ANA_WORD_CLK_EN 3 3 TX_P1_ANA_RESET 4 4 TX_P1_ANA_SERIAL_EN 5 5 TX_P1_DIG_CLK_EN 6 6 TX_P1_DATA_EN 7 7 TX_P1_ALLOW_RXDET 8 8 TX_P1_ANA_DCC_COMP_CAL_EN 9 9 RESERVED_15_10 10 15 ixDPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2 2 0x1323 12 0 4294967295 TX_P2_ANA_REFGEN_EN 0 0 TX_P2_ANA_VCM_HOLD 1 1 TX_P2_ANA_CLK_EN 2 2 TX_P2_ANA_WORD_CLK_EN 3 3 TX_P2_ANA_RESET 4 4 TX_P2_ANA_SERIAL_EN 5 5 TX_P2_DIG_CLK_EN 6 6 TX_P2_DATA_EN 7 7 TX_P2_ALLOW_RXDET 8 8 TX_P2_ALLOW_VBOOST 9 9 TX_P2_ANA_DCC_COMP_CAL_EN 10 10 RESERVED_15_11 11 15 ixDPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_0 2 0x1324 2 0 4294967295 TX_REFGEN_EN_TIME 0 7 TX_CLK_EN 8 15 ixDPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_1 2 0x1325 2 0 4294967295 TX_VCM_HOLD_TIME_14_0 0 14 SKIP_TX_VCM_HOLD_WAIT 15 15 ixDPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_2 2 0x1326 2 0 4294967295 TX_VBOOST_DIS_TIME_12_0 0 12 DTB_SEL 13 15 ixDPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_3 2 0x1327 3 0 4294967295 TX_VCM_HOLD_TIME_17_15 0 2 TX_VBOOST_DIS_TIME_13 3 3 RESERVED_15_4 4 15 ixDPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_4 2 0x1328 2 0 4294967295 TX_VCM_HOLD_GS_TIME 0 14 SKIP_TX_VCM_HOLD_GS_PULSE 15 15 ixDPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_5 2 0x1329 5 0 4294967295 TX_RXDET_TIME 0 9 FAST_TX_RXDET 10 10 TX_RESET_TIME 11 12 TX_SERIAL_EN_TIME 13 14 RESERVED_15_15 15 15 ixDPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_DCC_CR_BANK_ADDR 2 0x132a 1 0 4294967295 ADDR 0 15 ixDPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_DCC_CR_BANK_DATA 2 0x132b 1 0 4294967295 DATA 0 15 ixDPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_DCC_DAC_CTRL 2 0x132c 2 0 4294967295 CTRL 0 7 RESERVED_15_8 8 15 ixDPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_DCC_DAC_RANGE 2 0x132d 2 0 4294967295 CTRL 0 1 RESERVED_15_2 2 15 ixDPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_DCC_DAC_SEL 2 0x132e 6 0 4294967295 SEL 0 2 REQ 3 3 CTRL_UPD 4 4 RANGE_UPD 5 5 BIN_HOT 6 6 RESERVED_15_7 7 15 ixDPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_DCC_DAC_ACK 2 0x132f 2 0 4294967295 ACK 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_DCC_DAC_ADDR 2 0x1330 1 0 4294967295 ADDR 0 15 ixDPCSSYS_CR2_LANE3_DIG_TX_CLK_ALIGN_TX_CTL_0 2 0x1331 4 0 4294967295 TX_NUM_2UI_SHIFTS_16B_MODE 0 3 TX_NUM_2UI_SHIFTS_20B_MODE 4 7 TX_FIFO_BYPASS 8 8 RESERVED_15_9 9 15 ixDPCSSYS_CR2_LANE3_DIG_TX_LBERT_CTL 2 0x1332 4 0 4294967295 MODE 0 3 TRIGGER_ERR 4 4 PAT0 5 14 RESERVED_15_15 15 15 ixDPCSSYS_CR2_LANE3_DIG_RX_STAT_LD_VAL_1 2 0x1380 2 0 4294967295 SC1_LD_VAL 0 14 SC1_START 15 15 ixDPCSSYS_CR2_LANE3_DIG_RX_STAT_DATA_MSK 2 0x1381 1 0 4294967295 DATA_MSK_15_0 0 15 ixDPCSSYS_CR2_LANE3_DIG_RX_STAT_MATCH_CTL0 2 0x1382 4 0 4294967295 PTTRN_MSK_CR1A_4_0 0 4 PTTRN_CR1A_4_0 5 9 DATA_MSK_19_16 10 13 SCOPE_DLY 14 15 ixDPCSSYS_CR2_LANE3_DIG_RX_STAT_MATCH_CTL1 2 0x1383 5 0 4294967295 PTTRN_CR1B_EN 0 0 PTTRN_MSK_CR1B_4_0 1 5 PTTRN_CR1B_4_0 6 10 PTTRN_CR1A_ADPT_EN 11 11 RESERVED_15_12 12 15 ixDPCSSYS_CR2_LANE3_DIG_RX_STAT_STAT_CTL0 2 0x1384 10 0 4294967295 RESERVED_0 0 0 CORR_SHFT_SEL_VGA 1 1 CORR_SHFT_SEL 2 2 CORR_SRC_SEL 3 4 CORR_MODE_EN 5 5 STAT_SHFT_SEL 6 9 STAT_SRC_SEL 10 12 STAT_RXCLK_SEL 13 13 SC_TIMER_MODE 14 14 SKIP_EN 15 15 ixDPCSSYS_CR2_LANE3_DIG_RX_STAT_STAT_CTL1 2 0x1385 13 0 4294967295 STAT_CNT_0_EN 0 0 STAT_CNT_1_EN 1 1 STAT_CNT_2_EN 2 2 STAT_CNT_3_EN 3 3 STAT_CNT_4_EN 4 4 STAT_CNT_5_EN 5 5 STAT_CNT_6_EN 6 6 RESERVED_8_7 7 8 SC_PAUSE 9 9 STAT_CLK_EN 10 10 DATA_DLY_SEL 11 12 VLD_LOSS_CLR 13 13 VLD_CTL 14 15 ixDPCSSYS_CR2_LANE3_DIG_RX_STAT_SMPL_CNT1 2 0x1386 2 0 4294967295 SMPL_CNT1 0 14 SMPL_CNT1_DONE 15 15 ixDPCSSYS_CR2_LANE3_DIG_RX_STAT_STAT_CNT_0 2 0x1387 2 0 4294967295 STAT_CNT_0 0 14 SMPL_CNT1_DONE 15 15 ixDPCSSYS_CR2_LANE3_DIG_RX_STAT_STAT_CNT_1 2 0x1388 2 0 4294967295 STAT_CNT_1 0 14 SMPL_CNT1_DONE 15 15 ixDPCSSYS_CR2_LANE3_DIG_RX_STAT_STAT_CNT_2 2 0x1389 2 0 4294967295 STAT_CNT_2 0 14 SMPL_CNT1_DONE 15 15 ixDPCSSYS_CR2_LANE3_DIG_RX_STAT_STAT_CNT_3 2 0x138a 2 0 4294967295 STAT_CNT_3 0 14 SMPL_CNT1_DONE 15 15 ixDPCSSYS_CR2_LANE3_DIG_RX_STAT_STAT_CNT_4 2 0x138b 2 0 4294967295 STAT_CNT_4 0 14 SMPL_CNT1_DONE 15 15 ixDPCSSYS_CR2_LANE3_DIG_RX_STAT_STAT_CNT_5 2 0x138c 2 0 4294967295 STAT_CNT_5 0 14 SMPL_CNT1_DONE 15 15 ixDPCSSYS_CR2_LANE3_DIG_RX_STAT_STAT_CNT_6 2 0x138d 2 0 4294967295 STAT_CNT_6 0 14 SMPL_CNT1_DONE 15 15 ixDPCSSYS_CR2_LANE3_DIG_RX_STAT_CAL_COMP_CLK_CTL 2 0x138e 3 0 4294967295 PRECHRGE_CNT 0 2 REF_DIV_CNT 3 5 RESERVED_15_6 6 15 ixDPCSSYS_CR2_LANE3_DIG_RX_STAT_MATCH_CTL2 2 0x138f 2 0 4294967295 PTTRN_CR1A_19_5 0 14 RESERVED_15_15 15 15 ixDPCSSYS_CR2_LANE3_DIG_RX_STAT_MATCH_CTL3 2 0x1390 2 0 4294967295 PTTRN_MSK_CR1A_19_5 0 14 RESERVED_15_15 15 15 ixDPCSSYS_CR2_LANE3_DIG_RX_STAT_MATCH_CTL4 2 0x1391 2 0 4294967295 PTTRN_CR1B_19_5 0 14 RESERVED_15_15 15 15 ixDPCSSYS_CR2_LANE3_DIG_RX_STAT_MATCH_CTL5 2 0x1392 2 0 4294967295 PTTRN_MSK_CR1B_19_5 0 14 RESERVED_15_15 15 15 ixDPCSSYS_CR2_LANE3_DIG_RX_STAT_STAT_CTL2 2 0x1393 4 0 4294967295 DATA_DLY_SEL_2 0 0 SCOPE_DLY_2 1 1 DISABLE_SAMPLE_COUNT 2 2 RESERVED_15_3 3 15 ixDPCSSYS_CR2_LANE3_DIG_RX_STAT_STAT_STOP 2 0x1394 2 0 4294967295 SC1_STOP 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR2_LANE3_DIG_ANA_TX_OVRD_OUT 2 0x13a0 15 0 4294967295 TX_ANA_CLK_SHIFT 0 0 TX_ANA_DATA_EN 1 1 TX_ANA_REFGEN_EN 2 2 TX_ANA_VCM_HOLD 3 3 TX_ANA_CLK_EN 4 4 TX_ANA_WORD_CLK_EN 5 5 TX_ANA_MPLLA_CLK_EN 6 6 TX_ANA_MPLLB_CLK_EN 7 7 TX_ANA_RESET 8 8 TX_ANA_SERIAL_EN 9 9 TX_ANA_DATA_RATE 10 11 RESERVED 12 12 TX_DIV4_EN 13 13 TX_RXDET_EN 14 14 TX_OVRD_EN 15 15 ixDPCSSYS_CR2_LANE3_DIG_ANA_TX_TERM_CODE_OVRD_OUT 2 0x13a1 5 0 4294967295 TX_TERM_CODE 0 9 TX_TERM_OVRD_EN 10 10 TX_DRV_SRC 11 12 TX_DRV_SRC_OVRD_EN 13 13 RESERVED_15_14 14 15 ixDPCSSYS_CR2_LANE3_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT 2 0x13a2 3 0 4294967295 TX_TERM_DN_CLK 0 0 TX_TERM_CLK_SELF_CLEAR_DISABLE 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR2_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_0 2 0x13a3 3 0 4294967295 TX_ANA_LOAD_CLK 0 0 TX_ANA_CTRL_LEG_PULL_EN_13_0 1 14 TX_EQ_OVRD_EN 15 15 ixDPCSSYS_CR2_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_1 2 0x13a4 2 0 4294967295 TX_ANA_CTRL_LEG_PULL_EN_19_14 0 5 RESERVED_15_6 6 15 ixDPCSSYS_CR2_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_2 2 0x13a5 4 0 4294967295 RESERVED 0 2 TX_ANA_CTRL_EQ_MUX_SEL 3 6 TX_ANA_CTRL_PRE 7 12 RESERVED_15_13 13 15 ixDPCSSYS_CR2_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_3 2 0x13a6 2 0 4294967295 TX_ANA_CTRL_POST 0 8 RESERVED_15_9 9 15 ixDPCSSYS_CR2_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_4 2 0x13a7 1 0 4294967295 TX_ANA_CTRL_LEG_PULL_DIR_19_4 0 15 ixDPCSSYS_CR2_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_5 2 0x13a8 2 0 4294967295 TX_ANA_CTRL_LEG_PULL_DIR_3_0 0 3 RESERVED_15_4 4 15 ixDPCSSYS_CR2_LANE3_DIG_ANA_STATUS_0 2 0x13bb 9 0 4294967295 TX_ANA_CLK_SHIFT_ACK 0 0 TX_ANA_RXDETP_RESULT 1 1 TX_ANA_RXDETM_RESULT 2 2 TX_ANA_LOOPBACK_EN 3 3 TX_ANA_CLK_LB_EN 4 4 RX_ANA_CAL_RESULT 5 5 RX_ANA_SCOPE_DATA 6 6 TX_ANA_DCC_CAL_RESULT 7 7 TX_ANA_CTRL_EQ_MUX 8 15 ixDPCSSYS_CR2_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT 2 0x13c2 8 0 4294967295 TX_ANA_DCC_CAL_RANGE 0 1 TX_ANA_DCC_CAL_RANGE_OVRD_EN 2 2 TX_ANA_DCC_CAL_COMP_EN 3 3 TX_ANA_DCC_CAL_COMP_EN_OVRD_EN 4 4 TX_ANA_DCC_CAL_CTRL 5 12 TX_ANA_DCC_CAL_CTRL_OVRD_EN 13 13 TX_ANA_DCC_CAL_CTRL_EN 14 14 TX_ANA_DCC_CAL_CTRL_EN_OVRD_EN 15 15 ixDPCSSYS_CR2_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2 2 0x13c3 5 0 4294967295 TX_ANA_DCC_CAL_CTRL_SEL 0 2 TX_ANA_DCC_CAL_CTRL_SEL_OVRD_EN 3 3 TX_ANA_DCC_CLK_COMP 4 4 TX_ANA_DCC_CLK_COMP_OVRD_EN 5 5 RESERVED_15_6 6 15 ixDPCSSYS_CR2_LANE3_DIG_ANA_TX_OVRD_OUT_2 2 0x13c4 6 0 4294967295 TX_ANA_FAST_START 0 0 TX_ANA_FAST_START_OVRD_EN 1 1 TX_CLK_LB_EN 2 2 TX_CLK_LB_EN_OVRD_EN 3 3 TX_ACJTAG_EN 4 4 RESERVED_15_5 5 15 ixDPCSSYS_CR2_LANE3_ANA_TX_OVRD_MEAS 2 0x13e0 9 0 4294967295 OVRD_CLK_SHIFT 0 0 CLK_SHIFT_REG 0 0 MEAS_ATB_CAL_MUX 0 0 MEAS_ATB_CAL_COMP 0 0 OVRD_VCM_HOLD 0 0 VCM_HOLD_REG 0 0 PULL_UP_REG 0 0 PULL_DN_REG 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR2_LANE3_ANA_TX_PWR_OVRD 2 0x13e1 9 0 4294967295 OVRD_TX_LOOPBACK 0 0 LOOPBACK_EN_REG 0 0 REFGEN_EN_REG 0 0 CLK_DIV_EN_REG 0 0 DATA_EN_REG_INT 0 0 CLK_EN_REG 0 0 SERIAL_EN_REG 0 0 OVRD_EN 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR2_LANE3_ANA_TX_ALT_BUS 2 0x13e2 6 0 4294967295 DRV_SOURCE_REG 0 0 OVRD_ALT_BUS 0 0 ATB_S_ENABLE 0 0 TX_ALT_RINGO 0 0 JTAG_DATA_REG 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR2_LANE3_ANA_TX_ATB1 2 0x13e3 9 0 4294967295 MEAS_ATB_GD 0 0 MEAS_ATB_VDDH 0 0 OVERRIDE_RXDETREF 0 0 MEAS_ATB_VPTX 0 0 OVERRIDE_REGREF 0 0 MEAS_ATB_VREG_DRV 0 0 MEAS_ATB_VREG 0 0 MEAS_ATB_VPH_HALF 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR2_LANE3_ANA_TX_ATB2 2 0x13e4 9 0 4294967295 MEAS_ATB_VCM 0 0 MEAS_ATB_CAL_VDAC_CM 0 0 MEAS_ATB_CAL_VDAC_DIFF 0 0 MEAS_ATB_TXM 0 0 MEAS_ATB_TXP 0 0 MEAS_ATB_RXDETREF 0 0 LFPS_HIGH_PRIORITY 0 0 OSC_DIV4_EN 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR2_LANE3_ANA_TX_DCC_DAC 2 0x13e5 2 0 4294967295 DCC_DAC_REG 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR2_LANE3_ANA_TX_DCC_CTRL1 2 0x13e6 7 0 4294967295 NC0 0 0 OVRD_DCC_DAC_CTRL_SEL 0 0 DCC_DAC_CTRL_SEL_REG 0 0 OVRD_DCC_DAC_CTRL_EN 0 0 DCC_DAC_CTRL_EN_REG 0 0 OVRD_DCC_DAC_REG 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR2_LANE3_ANA_TX_TERM_CODE 2 0x13e7 2 0 4294967295 TERM_CODE_REG_70 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR2_LANE3_ANA_TX_TERM_CODE_CTRL 2 0x13e8 8 0 4294967295 VREG_BOOST_1 0 0 OVRD_UPDATE_TERM 0 0 UPDATE_TERM_REG 0 0 OVRD_RESET_TERM 0 0 RESET_TERM_REG 0 0 OVRD_TERM_CODE 0 0 TERM_CODE_REG_98 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR2_LANE3_ANA_TX_OVRD_CLK 2 0x13e9 9 0 4294967295 VREG_BOOST_0 0 0 CLK_LB_EN_REG 0 0 OVRD_LB_EN 0 0 MPLLB_CLK_EN_REG 0 0 MPLLA_CLK_EN_REG 0 0 OVRD_MPLLAB_EN 0 0 WORD_CLK_EN_REG 0 0 OVRD_WORD_CLK_EN 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR2_LANE3_ANA_TX_MISC1 2 0x13ea 8 0 4294967295 MEAS_ATB_CAL_CLK_ALIGN 0 0 OVRD_DCC_DAC_CTRL_RANGE 0 0 DCC_DAC_CTRL_RANGE_REG 0 0 OVRD_VREF_SEL 0 0 VREF_SEL_REG 0 0 FORCE_ATB_TXM 0 0 FORCE_ATB_TXP 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR2_LANE3_ANA_TX_MISC2 2 0x13eb 8 0 4294967295 TX_PEAKING_LVL 0 0 VREG_CP_GAIN_CTRL 0 0 TX_SLEW_EN 0 0 EN_INV_POST 0 0 EN_INV_PRE 0 0 TX_VREG_EN_BYP 0 0 TX_VDRIVER_PULLDN_EN 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR2_LANE3_ANA_TX_MISC3 2 0x13ec 4 0 4294967295 TX_VREG_OVRD_RING_CTRL 0 0 TX_DCC_LOWV 0 0 NC7_2 2 7 RESERVED_15_8 8 15 ixDPCSSYS_CR2_LANE3_ANA_TX_RESERVED2 2 0x13ed 2 0 4294967295 NC7_0 0 7 RESERVED_15_8 8 15 ixDPCSSYS_CR2_LANE3_ANA_TX_RESERVED3 2 0x13ee 2 0 4294967295 NC7_0 0 7 RESERVED_15_8 8 15 ixDPCSSYS_CR2_LANE3_ANA_TX_RESERVED4 2 0x13ef 2 0 4294967295 NC7_0 0 7 RESERVED_15_8 8 15 ixDPCSSYS_CR2_RAWCMN_DIG_CMN_CTL 2 0x2000 2 0 4294967295 PHY_FUNC_RST 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR2_RAWCMN_DIG_MPLLA_OVRD_IN 2 0x2001 10 0 4294967295 MPLLA_WORD_DIV2_EN_OVRD_VAL 0 0 MPLLA_WORD_DIV2_EN_OVRD_EN 1 1 MPLLA_TX_CLK_DIV_OVRD_VAL 2 4 MPLLA_TX_CLK_DIV_OVRD_EN 5 5 MPLLA_DIV10_CLK_EN_OVRD_VAL 6 6 MPLLA_DIV10_CLK_EN_OVRD_EN 7 7 MPLLA_DIV8_CLK_EN_OVRD_VAL 8 8 MPLLA_DIV8_CLK_EN_OVRD_EN 9 9 MPLLA_BW_OVRD_EN 10 10 RESERVED_15_11 11 15 ixDPCSSYS_CR2_RAWCMN_DIG_MPLLA_BW_OVRD_IN 2 0x2002 1 0 4294967295 MPLLA_BW_OVRD_VAL 0 15 ixDPCSSYS_CR2_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_0 2 0x2003 7 0 4294967295 MPLLA_SSC_RANGE_OVRD_VAL 0 2 MPLLA_SSC_RANGE_OVRD_EN 3 3 MPLLA_SSC_CLK_SEL_OVRD_VAL 4 6 MPLLA_SSC_CLK_SEL_OVRD_EN 7 7 MPLLA_SSC_EN_OVRD_VAL 8 8 MPLLA_SSC_EN_OVRD_EN 9 9 RESERVED_15_10 10 15 ixDPCSSYS_CR2_RAWCMN_DIG_MPLLB_OVRD_IN 2 0x2004 10 0 4294967295 MPLLB_WORD_DIV2_EN_OVRD_VAL 0 0 MPLLB_WORD_DIV2_EN_OVRD_EN 1 1 MPLLB_TX_CLK_DIV_OVRD_VAL 2 4 MPLLB_TX_CLK_DIV_OVRD_EN 5 5 MPLLB_DIV10_CLK_EN_OVRD_VAL 6 6 MPLLB_DIV10_CLK_EN_OVRD_EN 7 7 MPLLB_DIV8_CLK_EN_OVRD_VAL 8 8 MPLLB_DIV8_CLK_EN_OVRD_EN 9 9 MPLLB_BW_OVRD_EN 10 10 RESERVED_15_11 11 15 ixDPCSSYS_CR2_RAWCMN_DIG_MPLLB_BW_OVRD_IN 2 0x2005 1 0 4294967295 MPLLB_BW_OVRD_VAL 0 15 ixDPCSSYS_CR2_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_0 2 0x2006 7 0 4294967295 MPLLB_SSC_RANGE_OVRD_VAL 0 2 MPLLB_SSC_RANGE_OVRD_EN 3 3 MPLLB_SSC_CLK_SEL_OVRD_VAL 4 6 MPLLB_SSC_CLK_SEL_OVRD_EN 7 7 MPLLB_SSC_EN_OVRD_VAL 8 8 MPLLB_SSC_EN_OVRD_EN 9 9 RESERVED_15_10 10 15 ixDPCSSYS_CR2_RAWCMN_DIG_LANE_FSM_OP_XTND 2 0x2007 2 0 4294967295 DATA 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR2_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_1 2 0x2008 3 0 4294967295 MPLLA_FRACN_CTRL_OVRD_VAL 0 10 MPLLA_FRACN_CTRL_OVRD_EN 11 11 RESERVED_15_12 12 15 ixDPCSSYS_CR2_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_1 2 0x2009 3 0 4294967295 MPLLB_FRACN_CTRL_OVRD_VAL 0 10 MPLLB_FRACN_CTRL_OVRD_EN 11 11 RESERVED_15_12 12 15 ixDPCSSYS_CR2_RAWCMN_DIG_CMN_CTL_1 2 0x200a 13 0 4294967295 MPLLA_INIT_CAL_DISABLE_OVRD_VAL 0 0 MPLLA_INIT_CAL_DISABLE_OVRD_EN 1 1 MPLLB_INIT_CAL_DISABLE_OVRD_VAL 2 2 MPLLB_INIT_CAL_DISABLE_OVRD_EN 3 3 RTUNE_REQ_OVRD_VAL 4 4 RTUNE_REQ_OVRD_EN 5 5 HDMIMODE_ENABLE_OVRD_VAL 6 6 HDMIMODE_ENABLE_OVRD_EN 7 7 TX_PWM_CLK_SEL_OVRD_VAL 8 9 TX_PWM_CLK_SEL_OVRD_EN 10 10 TX_PWM_CLK_EN_OVRD_VAL 11 11 TX_PWM_CLK_EN_OVRD_EN 12 12 RESERVED_15_13 13 15 ixDPCSSYS_CR2_RAWCMN_DIG_MPLL_STATE_CTL 2 0x200b 8 0 4294967295 MPLL_OFF_TIME 0 5 MPLLA_STATE 6 6 MPLLB_STATE 7 7 MPLL_STATE_OVRD_OUT_EN 8 8 MPLL_FORCE_ON_TIME 9 12 MPLLB_BANK_SEL 13 13 MPLLA_BANK_SEL 14 14 RESERVED_15_15 15 15 ixDPCSSYS_CR2_RAWCMN_DIG_TX_CAL_CODE 2 0x200c 2 0 4294967295 DATA 0 0 RESERVED_15_4 4 15 ixDPCSSYS_CR2_RAWCMN_DIG_SRAM_INIT_DONE 2 0x200d 2 0 4294967295 DATA 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR2_RAWCMN_DIG_OCLA 2 0x200e 3 0 4294967295 DIV2_CLK_EN 0 0 TCA_OCLA_PROBE_SEL 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR2_RAWCMN_DIG_SUP_ANA_OVRD 2 0x200f 7 0 4294967295 REF_ALT_CLK_LP_SEL_OVRD_EN 0 0 REF_ALT_CLK_LP_SEL_OVRD_VAL 1 1 SUP_PRE_HP_OVRD_EN 2 2 SUP_PRE_HP_OVRD_VAL 3 3 SUP_RX_VCO_VREF_SEL_OVRD_EN 4 4 SUP_RX_VCO_VREF_SEL_OVRD_VAL 5 7 RESERVED_15_8 8 15 ixDPCSSYS_CR2_RAWCMN_DIG_PCS_RAW_ID_CODE 2 0x2010 1 0 4294967295 DATA 0 0 ixDPCSSYS_CR2_RAWCMN_DIG_FW_ID_CODE_1 2 0x2011 1 0 4294967295 W_ID_CODE_1 0 15 ixDPCSSYS_CR2_RAWCMN_DIG_FW_ID_CODE_2 2 0x2012 1 0 4294967295 W_ID_CODE_2 0 15 ixDPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_0 2 0x2020 2 0 4294967295 RTUNE_RX_VAL_0 0 5 RESERVED_15_6 6 15 ixDPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_0 2 0x2021 2 0 4294967295 RTUNE_TXDN_VAL_0 0 9 RESERVED_15_10 10 15 ixDPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_0 2 0x2022 2 0 4294967295 RTUNE_TXUP_VAL_0 0 9 RESERVED_15_10 10 15 ixDPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_1 2 0x2023 2 0 4294967295 RTUNE_RX_VAL_1 0 5 RESERVED_15_6 6 15 ixDPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_1 2 0x2024 2 0 4294967295 RTUNE_TXDN_VAL_1 0 9 RESERVED_15_10 10 15 ixDPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_1 2 0x2025 2 0 4294967295 RTUNE_TXUP_VAL_1 0 9 RESERVED_15_10 10 15 ixDPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_2 2 0x2026 2 0 4294967295 RTUNE_RX_VAL_2 0 5 RESERVED_15_6 6 15 ixDPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_2 2 0x2027 2 0 4294967295 RTUNE_TXDN_VAL_2 0 9 RESERVED_15_10 10 15 ixDPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_2 2 0x2028 2 0 4294967295 RTUNE_TXUP_VAL_2 0 9 RESERVED_15_10 10 15 ixDPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_3 2 0x2029 2 0 4294967295 RTUNE_RX_VAL_3 0 5 RESERVED_15_6 6 15 ixDPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_3 2 0x202a 2 0 4294967295 RTUNE_TXDN_VAL_3 0 9 RESERVED_15_10 10 15 ixDPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_3 2 0x202b 2 0 4294967295 RTUNE_TXUP_VAL_3 0 9 RESERVED_15_10 10 15 ixDPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_4 2 0x202c 2 0 4294967295 RTUNE_RX_VAL_4 0 5 RESERVED_15_6 6 15 ixDPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_4 2 0x202d 2 0 4294967295 RTUNE_TXDN_VAL_4 0 9 RESERVED_15_10 10 15 ixDPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_4 2 0x202e 2 0 4294967295 RTUNE_TXUP_VAL_4 0 9 RESERVED_15_10 10 15 ixDPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_5 2 0x202f 2 0 4294967295 RTUNE_RX_VAL_5 0 5 RESERVED_15_6 6 15 ixDPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_5 2 0x2030 2 0 4294967295 RTUNE_TXDN_VAL_5 0 9 RESERVED_15_10 10 15 ixDPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_5 2 0x2031 2 0 4294967295 RTUNE_TXUP_VAL_5 0 9 RESERVED_15_10 10 15 ixDPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_6 2 0x2032 2 0 4294967295 RTUNE_RX_VAL_6 0 5 RESERVED_15_6 6 15 ixDPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_6 2 0x2033 2 0 4294967295 RTUNE_TXDN_VAL_6 0 9 RESERVED_15_10 10 15 ixDPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_6 2 0x2034 2 0 4294967295 RTUNE_TXUP_VAL_6 0 9 RESERVED_15_10 10 15 ixDPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_7 2 0x2035 2 0 4294967295 RTUNE_RX_VAL_7 0 5 RESERVED_15_6 6 15 ixDPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_7 2 0x2036 2 0 4294967295 RTUNE_TXDN_VAL_7 0 9 RESERVED_15_10 10 15 ixDPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_7 2 0x2037 2 0 4294967295 RTUNE_TXUP_VAL_7 0 9 RESERVED_15_10 10 15 ixDPCSSYS_CR2_RAWCMN_DIG_AON_CMN_SRAM_BL_CFG 2 0x2038 5 0 4294967295 SRAM_PGATE_BL_EN 0 0 SRAM_BL_ROM 1 1 SRAM_BL_BYPASS 2 2 SRAM_BL_START 3 3 RESERVED_15_4 4 15 ixDPCSSYS_CR2_RAWCMN_DIG_AON_CMN_PG_OVRD_IN 2 0x2039 7 0 4294967295 PMA_PWR_STABLE_OVRD 0 0 PCS_PWR_STABLE_OVRD 1 1 PG_RESET_OVRD_VAL 2 2 PG_RESET_OVRD_EN 3 3 PG_MODE_EN_OVRD_VAL 4 4 PG_MODE_EN_OVRD_EN 5 5 RESERVED_15_6 6 15 ixDPCSSYS_CR2_RAWCMN_DIG_AON_CMN_PG_OVRD_OUT 2 0x203a 8 0 4294967295 PMA_PWR_EN_OVRD 0 0 PCS_PWR_EN_OVRD 1 1 MON_IN_VALID_OVRD_VAL 2 2 MON_IN_VALID_OVRD_EN 3 3 MON_IN_PULL_DOWN 4 4 ANA_ISOLATION_EN_OVRD_EN 5 5 ANA_ISOLATION_EN_OVRD_VAL 6 6 RESERVED_15_7 7 15 ixDPCSSYS_CR2_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN 2 0x203b 11 0 4294967295 MPLLA_FORCE_EN_OVRD_VAL 0 0 MPLLA_FORCE_EN_OVRD_EN 1 1 MPLLB_FORCE_EN_OVRD_VAL 2 2 MPLLB_FORCE_EN_OVRD_EN 3 3 REF_CLK_EN_OVRD_VAL 4 4 REF_CLK_EN_OVRD_EN 5 5 MPLLA_FORCE_ACK_OVRD_VAL 6 6 MPLLA_FORCE_ACK_OVRD_EN 7 7 MPLLB_FORCE_ACK_OVRD_VAL 8 8 MPLLB_FORCE_ACK_OVRD_EN 9 9 RESERVED_15_10 10 15 ixDPCSSYS_CR2_RAWCMN_DIG_AON_CMN_VREF_STATS 2 0x203c 3 0 4294967295 SUP_ANA_VPHUD_SELVPH 0 0 VREF_CAL_DONE 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RES_OVRD_IN 2 0x203d 8 0 4294967295 RES_REQ_IN 0 0 RES_ACK_IN 1 1 RES_OVRD_EN 2 2 RES_REQ_OUT 3 3 RES_REQ_OUT_OVRD_EN 4 4 RES_ACK_OUT 5 5 RES_ACK_OUT_OVRD_EN 6 6 RESERVED_15_7 7 15 ixDPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RES_ASIC_IN_OUT 2 0x203e 5 0 4294967295 RES_REQ_IN 0 0 RES_REQ_OUT 1 1 RES_ACK_IN 2 2 RES_ACK_OUT 3 3 RESERVED_15_4 4 15 ixDPCSSYS_CR2_RAWCMN_DIG_AON_CMN_REF_RANGE_OVRD 2 0x203f 3 0 4294967295 OVRD_VAL 0 4 OVRD_EN 5 5 RESERVED_15_6 6 15 ixDPCSSYS_CR2_RAWCMN_DIG_AON_CMN_MISC_CONF_IN_1 2 0x2040 2 0 4294967295 MPLL_PWRDN_TIME 0 9 RESERVED_15_10 10 15 ixDPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN 2 0x3000 12 0 4294967295 PSTATE 0 1 LPD 2 2 WIDTH 3 4 RATE 5 7 MPLLB_SEL 8 8 MPLL_EN 9 9 OVRD_EN 10 10 MSTR_MPLLA_STATE 11 11 MSTR_MPLLB_STATE 12 12 MSTR_MPLL_OVRD_EN 13 13 TX_ASYNC_EN_OVR_VAL 14 14 TX_ASYNC_EN_OVR_EN 15 15 ixDPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1 2 0x3001 13 0 4294967295 RESET_OVRD_VAL 0 0 RESET_OVRD_EN 1 1 REQ_OVRD_VAL 2 2 REQ_OVRD_EN 3 3 DETRX_REQ_OVRD_VAL 4 4 DETRX_REQ_OVRD_EN 5 5 VBOOST_EN_OVRD_VAL 6 6 VBOOST_EN_OVRD_EN 7 7 IBOOST_LVL_OVRD_VAL 8 11 IBOOST_LVL_OVRD_EN 12 12 TX_BEACON_EN_OVR_VAL 13 13 TX_BEACON_EN_OVR_EN 14 14 RESERVED_15_15 15 15 ixDPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_PCS_IN 2 0x3002 12 0 4294967295 RESET 0 0 REQ 1 1 PSTATE 2 3 LPD 4 4 WIDTH 5 6 RATE 7 9 MPLLB_SEL 10 10 MPLL_EN 11 11 MSTR_MPLLA_STATE 12 12 MSTR_MPLLB_STATE 13 13 DETRX_REQ 14 14 RESERVED_15_15 15 15 ixDPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_OVRD_OUT 2 0x3003 6 0 4294967295 ACK 0 0 DETRX_RESULT 1 1 EN_CTL 2 2 TX_DWORD_CLK_SYNC_OVRD_VAL 3 3 TX_DWORD_CLK_SYNC_OVRD_EN 4 4 RESERVED_15_5 5 15 ixDPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_PCS_OUT 2 0x3004 2 0 4294967295 ACK 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN 2 0x3005 12 0 4294967295 RATE 0 1 WIDTH 2 3 PSTATE 4 5 LPD 6 6 OVRD_EN 7 7 ADAPT_AFE_EN 8 8 ADAPT_DFE_EN 9 9 LANE_RX2TX_PAR_LB_EN_OVRD_VAL 10 10 LANE_RX2TX_PAR_LB_EN_OVRD_EN 11 11 RX_DATA_EN_OVRD_VAL_R 12 12 RX_DATA_EN_OVRD_EN_R 13 13 RESERVED_15_14 14 15 ixDPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1 2 0x3006 12 0 4294967295 RESET_OVRD_VAL 0 0 RESET_OVRD_EN 1 1 REQ_OVRD_VAL 2 2 REQ_OVRD_EN 3 3 RX_LOS_THRSHLD_OVRD_VAL 4 6 RX_LOS_THRSHLD_OVRD_EN 7 7 ADAPT_REQ 8 8 ADAPT_REQ_OVRD_EN 9 9 ADAPT_CONT 10 10 OFFCAN_CONT 11 11 CONT_OVRD_EN 12 12 RESERVED_15_13 13 15 ixDPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_2 2 0x3007 4 0 4294967295 VCO_LD_VAL_OVRD 0 12 VCO_LD_VAL_OVRD_EN 13 13 VCO_LOWFREQ_VAL_OVRD 14 14 VCO_LOWFREQ_VAL_OVRD_EN 15 15 ixDPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_3 2 0x3008 3 0 4294967295 REF_LD_VAL_OVRD 0 6 REF_LD_VAL_OVRD_EN 7 7 RESERVED_15_8 8 15 ixDPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_PCS_IN 2 0x3009 13 0 4294967295 REQ 0 0 RATE 1 2 WIDTH 3 4 PSTATE 5 6 LPD 7 7 CDR_VCO_LOWFREQ 8 8 ADAPT_AFE_EN 9 9 ADAPT_DFE_EN 10 10 ADAPT_REQ 11 11 ADAPT_CONT 12 12 OFFCAN_CONT 13 13 RESET 14 14 RESERVED_15_15 15 15 ixDPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_1 2 0x300a 2 0 4294967295 REF_LD_VAL 0 6 RESERVED_15_7 7 15 ixDPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_2 2 0x300b 2 0 4294967295 VCO_LD_VAL 0 12 RESERVED_15_13 13 15 ixDPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_3 2 0x300c 4 0 4294967295 EQ_ATT_LVL 0 2 EQ_VGA1_GAIN 3 6 EQ_VGA2_GAIN 7 10 EQ_CTLE_BOOST 11 15 ixDPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_4 2 0x300d 3 0 4294967295 EQ_CTLE_POLE 0 2 EQ_DFE_TAP1 3 10 RESERVED_15_11 11 15 ixDPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT 2 0x300e 3 0 4294967295 ACK 0 0 EN_CTL 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_PCS_OUT 2 0x300f 2 0 4294967295 ACK 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_ADAPT_ACK 2 0x3010 2 0 4294967295 RX_ADAPT_ACK 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_ADAPT_FOM 2 0x3011 2 0 4294967295 RX_ADAPT_FOM 0 7 RESERVED_15_8 8 15 ixDPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_TXPRE_DIR 2 0x3012 2 0 4294967295 RX_TXPRE_DIR 0 1 RESERVED_15_2 2 15 ixDPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_TXMAIN_DIR 2 0x3013 2 0 4294967295 RX_TXMAIN_DIR 0 1 RESERVED_15_2 2 15 ixDPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_TXPOST_DIR 2 0x3014 2 0 4294967295 RX_TXPOST_DIR 0 1 RESERVED_15_2 2 15 ixDPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_LANE_NUMBER 2 0x3015 2 0 4294967295 LANE_NUMBER 0 3 RESERVED_15_4 4 15 ixDPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RESERVED_1 2 0x3016 1 0 4294967295 RESERVED_REG_1 0 15 ixDPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RESERVED_2 2 0x3017 1 0 4294967295 RESERVED_REG_2 0 15 ixDPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN 2 0x3018 16 0 4294967295 RX_RESET_ATE_OVRD_VAL 0 0 RX_RESET_ATE_OVRD_EN 1 1 TX_RESET_ATE_OVRD_VAL 2 2 TX_RESET_ATE_OVRD_EN 3 3 RX_REQ_ATE_OVRD_VAL 4 4 RX_REQ_ATE_OVRD_EN 5 5 TX_REQ_ATE_OVRD_VAL 6 6 TX_REQ_ATE_OVRD_EN 7 7 RX_ADAPT_AFE_EN_OVRD_VAL 8 8 RX_ADAPT_AFE_EN_OVRD_EN 9 9 RX_ADAPT_DFE_EN_OVRD_VAL 10 10 RX_ADAPT_DFE_EN_OVRD_EN 11 11 TX_DATA_EN_ATE_OVRD_VAL 12 12 TX_DATA_EN_ATE_OVRD_EN 13 13 RX_DATA_EN_ATE_OVRD_VAL 14 14 RX_DATA_EN_ATE_OVRD_EN 15 15 ixDPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN 2 0x3019 3 0 4294967295 RX_EQ_DELTA_IQ_OVRD_VAL 0 3 RX_EQ_DELTA_IQ_OVRD_EN 4 4 RESERVED_15_5 5 15 ixDPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN 2 0x301a 5 0 4294967295 RX_TERM_CTRL_OVRD_VAL 0 2 RX_TERM_CTRL_OVRD_EN 3 3 TX_TERM_CTRL_OVRD_VAL 4 6 TX_TERM_CTRL_OVRD_EN 7 7 RESERVED_15_8 8 15 ixDPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TXRX_TERM_CTRL_IN 2 0x301b 3 0 4294967295 RX_TERM_CTRL 0 2 TX_TERM_CTRL 3 5 RESERVED_15_6 6 15 ixDPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT_1 2 0x301c 2 0 4294967295 RX_CLK_EN 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_EQ_OVRD_IN_1 2 0x301d 4 0 4294967295 RX_EQ_AFE_GAIN_OVRD_VAL 0 3 RX_EQ_ATT_LVL_OVRD_VAL 4 6 RX_EQ_OVRD_EN 7 7 RESERVED_15_8 8 15 ixDPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_EQ_OVRD_IN_2 2 0x301e 3 0 4294967295 RX_EQ_DFE_TAP1_OVRD_VAL 0 7 RX_EQ_CTLE_BOOST_OVRD_VAL 8 12 RESERVED_15_13 13 15 ixDPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_PH2_CAL 2 0x301f 4 0 4294967295 PH2_CAL_ACK_VAL 0 0 PH2_CAL_REQ_VAL 1 1 PH2_CAL_REQ_OVRD_VAL 2 2 RESERVED_15_3 3 15 ixDPCSSYS_CR2_RAWLANE0_DIG_FSM_FSM_OVRD_CTL 2 0x3020 5 0 4294967295 FSM_JMP_ADDR 0 11 FSM_JMP_EN 12 12 FSM_CMD_START 13 13 FSM_OVRD_EN 14 14 FSM_BREAK 15 15 ixDPCSSYS_CR2_RAWLANE0_DIG_FSM_MEM_ADDR_MON 2 0x3021 1 0 4294967295 MEM_ADDR 0 15 ixDPCSSYS_CR2_RAWLANE0_DIG_FSM_STATUS_MON 2 0x3022 8 0 4294967295 STATE 0 4 CMD_RDY 5 5 ALU_OVFLW 6 6 ALU_RES_EQ0 7 7 WAIT_CNT_EQ0 8 8 WRMSK_DISABLED 9 9 RDMSK_DISABLED 10 10 RESERVED_15_11 11 15 ixDPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_RX_STARTUP_CAL 2 0x3023 2 0 4294967295 FAST_RX_STARTUP_CAL 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_RX_ADAPT 2 0x3024 2 0 4294967295 FAST_RX_ADAPT 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_RX_AFE_CAL 2 0x3025 2 0 4294967295 FAST_RX_AFE_CAL 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_RX_DFE_CAL 2 0x3026 2 0 4294967295 FAST_RX_DFE_CAL 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_RX_BYPASS_CAL 2 0x3027 2 0 4294967295 FAST_RX_BYPASS_CAL 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_RX_REFLVL_CAL 2 0x3028 2 0 4294967295 FAST_RX_REFLVL_CAL 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_RX_IQ_CAL 2 0x3029 2 0 4294967295 FAST_RX_IQ_CAL 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_RX_AFE_ADAPT 2 0x302a 2 0 4294967295 FAST_RX_AFE_ADAPT 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_RX_DFE_ADAPT 2 0x302b 2 0 4294967295 FAST_RX_DFE_ADAPT 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_SUP 2 0x302c 2 0 4294967295 FAST_SUP 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_TX_CMN_MODE 2 0x302d 2 0 4294967295 FAST_TX_CMN_MODE 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_TX_RXDET 2 0x302e 2 0 4294967295 FAST_TX_RXDET 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_RX_PWRUP 2 0x302f 2 0 4294967295 FAST_RX_PWRUP 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_RX_VCO_WAIT 2 0x3030 2 0 4294967295 FAST_RX_VCO_WAIT 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_RX_VCO_CAL 2 0x3031 2 0 4294967295 FAST_RX_VCO_CAL 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR2_RAWLANE0_DIG_FSM_CMNCAL_MPLL_STATUS 2 0x3032 3 0 4294967295 CMNCAL_MPLL_INIT 0 0 CMNCAL_MPLL_DONE 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_RX_CONT_CAL_ADAPT 2 0x3033 2 0 4294967295 FAST_RX_CONT_CAL_ADAPT 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_RX_CONT_ADAPT 2 0x3034 2 0 4294967295 FAST_RX_CONT_ADAPT 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_RX_CONT_DATA_CAL 2 0x3035 2 0 4294967295 FAST_RX_CONT_DATA_CAL 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_RX_CONT_PHASE_CAL 2 0x3036 2 0 4294967295 FAST_RX_CONT_PHASE_CAL 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_RX_CONT_AFE_CAL 2 0x3037 2 0 4294967295 FAST_RX_CONT_AFE_CAL 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_FLAGS 2 0x3038 12 0 4294967295 TX_FAST_DCC_CAL 0 0 RX_FAST_DCC_CAL 1 1 RX_FAST_VPHUD_CAL 2 2 RX_FAST_VREF_CAL 3 3 RX_FAST_SIGDET_CAL 4 4 RESERVED_2 5 7 TX_FAST_CONT_DCC_CAL 8 8 RX_FAST_CONT_DCC_CAL 9 9 RX_FAST_CONT_VPHUD_CAL 10 10 RX_FAST_CONT_VREF_CAL 11 11 RESERVED_1 12 14 TX_SKIP_SUP_CAL 15 15 ixDPCSSYS_CR2_RAWLANE0_DIG_FSM_CR_LOCK 2 0x3039 3 0 4294967295 CR_REG_LOCK 0 0 CR_MEM_LOCK 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR2_RAWLANE0_DIG_FSM_TX_DCC_FLAGS 2 0x303a 4 0 4294967295 RATE 0 0 DIV 1 1 MPLL 2 2 RESERVED_15_3 3 15 ixDPCSSYS_CR2_RAWLANE0_DIG_FSM_TX_DCC_STATUS 2 0x303b 2 0 4294967295 FLAG 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR2_RAWLANE0_DIG_FSM_OCLA 2 0x303c 4 0 4294967295 PC_EN 0 0 REG_BANK1_EN 1 1 REG_BANK2_EN 2 2 RESERVED_15_3 3 15 ixDPCSSYS_CR2_RAWLANE0_DIG_FSM_TX_EQ_UPDATE_FLAG 2 0x303d 2 0 4294967295 TX_EQ_UPDATE_FLAG 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR2_RAWLANE0_DIG_FSM_CMNCAL_RCAL_STATUS 2 0x303e 3 0 4294967295 CMNCAL_RCAL_INIT 0 0 CMNCAL_RCAL_DONE 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR2_RAWLANE0_DIG_FSM_RX_IQ_PHASE_OFFSET 2 0x303f 2 0 4294967295 RX_IQ_PHASE_OFFSET 0 3 RESERVED_15_4 4 15 ixDPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_RESET_RTN_REQ 2 0x3040 2 0 4294967295 RESET_RTN_REQ 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_RX_RESET_IRQ 2 0x3041 2 0 4294967295 RX_RESET 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_RX_REQ_IRQ 2 0x3042 2 0 4294967295 RX_REQ 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_RX_RATE_IRQ 2 0x3043 2 0 4294967295 RX_RATE_IRQ 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_RX_PSTATE_IRQ 2 0x3044 2 0 4294967295 RX_PSTATE_IRQ 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ 2 0x3045 2 0 4294967295 RX_ADAPT_REQ_IRQ 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ 2 0x3046 2 0 4294967295 RX_ADAPT_DIS_IRQ 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_RX_RESET_IRQ_CLR 2 0x3047 2 0 4294967295 RX_RESET_IRQ_CLR 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_RX_REQ_IRQ_CLR 2 0x3048 2 0 4294967295 RX_REQ_IRQ_CLR 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_RX_RATE_IRQ_CLR 2 0x3049 2 0 4294967295 RX_RATE_IRQ_CLR 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR 2 0x304a 2 0 4294967295 RX_PSTATE_IRQ_CLR 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR 2 0x304b 2 0 4294967295 RX_ADAPT_REQ_IRQ_CLR 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR 2 0x304c 2 0 4294967295 RX_ADAPT_DIS_IRQ_CLR 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK 2 0x304d 12 0 4294967295 RX_REQ_IRQ_MSK 0 0 RX_RATE_IRQ_MSK 1 1 RX_PSTATE_IRQ_MSK 2 2 RX_ADAPT_REQ_IRQ_MSK 3 3 RX_ADAPT_DIS_IRQ_MSK 4 4 RX_RESET_IRQ_MSK 5 5 LANE_XCVR_MODE_IRQ_MSK 6 6 RX_PH2_CAL_REQ_IRQ_MSK 7 7 RX_PH2_CAL_DIS_IRQ_MSK 8 8 LANE_RX2TX_SER_LB_EN_IRQ_MSK 9 9 DCC_ONDMD_IRQ_MSK 10 10 RESERVED_15_11 11 15 ixDPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK_2 2 0x304e 3 0 4294967295 TX_RESET_IRQ_MSK 0 0 TX_REQ_IRQ_MSK 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ 2 0x304f 2 0 4294967295 LANE_XCVR_MODE_IRQ 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR 2 0x3050 2 0 4294967295 LANE_XCVR_MODE_IRQ_CLR 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ 2 0x3051 2 0 4294967295 RX_PH2_CAL_REQ_IRQ 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ 2 0x3052 2 0 4294967295 RX_PH2_CAL_DIS_IRQ 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR 2 0x3053 2 0 4294967295 RX_PH2_CAL_REQ_IRQ_CLR 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR 2 0x3054 2 0 4294967295 RX_PH2_CAL_DIS_IRQ_CLR 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ 2 0x3055 2 0 4294967295 LANE_RX2TX_SER_LB_EN_IRQ 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR 2 0x3056 2 0 4294967295 LANE_RX2TX_SER_LB_EN_IRQ_CLR 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_DCC_ONDMD_IRQ 2 0x3057 2 0 4294967295 IRQ 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_TX_RESET_IRQ 2 0x3058 2 0 4294967295 TX_RESET 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_TX_REQ_IRQ 2 0x3059 2 0 4294967295 TX_REQ 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_TX_RESET_IRQ_CLR 2 0x305a 2 0 4294967295 TX_RESET_IRQ_CLR 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_TX_REQ_IRQ_CLR 2 0x305b 2 0 4294967295 TX_REQ_IRQ_CLR 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_LANE_OVRD_IN 2 0x3060 4 0 4294967295 LANE_MPLLA_EN_IN 0 0 LANE_MPLLB_EN_IN 1 1 LANE_OVRD_EN 2 2 RESERVED_15_3 3 15 ixDPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_LANE_OVRD_OUT 2 0x3061 4 0 4294967295 LANE_MPLLA_EN_OUT 0 0 LANE_MPLLB_EN_OUT 1 1 LANE_OVRD_EN 2 2 RESERVED_15_3 3 15 ixDPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_SUP_OVRD_IN 2 0x3062 4 0 4294967295 MPLLA_STATE 0 0 MPLLB_STATE 1 1 SUP_STATE_OVRD_EN 2 2 RESERVED_15_3 3 15 ixDPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_SUP_PMA_IN 2 0x3063 3 0 4294967295 MPLLA_STATE 0 0 MPLLB_STATE 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT 2 0x3064 16 0 4294967295 TX_REQ_OVRD_VAL 0 0 TX_REQ_OVRD_EN 1 1 TX_RESET_OVRD_VAL 2 2 TX_RESET_OVRD_EN 3 3 TX_BEACON_EN_OVRD_VAL 4 4 TX_BEACON_EN_OVRD_EN 5 5 TX_ASYNC_DRV_EN_OVRD_VAL 6 6 TX_ASYNC_DRV_EN_OVRD_EN 7 7 TX_ASYNC_EN_OVRD_VAL 8 8 TX_ASYNC_EN_OVRD_EN 9 9 TX_DWORD_CLK_SYNC_OVRD_VAL 10 10 TX_DWORD_CLK_SYNC_OVRD_EN 11 11 LANE_TX2RX_SER_LB_EN_OVRD_VAL 12 12 LANE_TX2RX_SER_LB_EN_OVRD_EN 13 13 TX_PMA_DATA_EN_OVRD_VAL_R 14 14 TX_PMA_DATA_EN_OVRD_EN_R 15 15 ixDPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_TX_PMA_IN 2 0x3065 2 0 4294967295 ACK 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT 2 0x3066 9 0 4294967295 RX_REQ_OVRD_VAL 0 0 RX_REQ_OVRD_EN 1 1 RX_RESET_OVRD_VAL 2 2 RX_RESET_OVRD_EN 3 3 LANE_RX2TX_PAR_LB_EN_OVRD_VAL 4 4 LANE_RX2TX_PAR_LB_EN_OVRD_EN 5 5 RX_PMA_DATA_EN_OVRD_VAL_R 6 6 RX_PMA_DATA_EN_OVRD_EN_R 7 7 RESERVED_15_8 8 15 ixDPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_RX_PMA_IN 2 0x3067 2 0 4294967295 ACK 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_LANE_RTUNE_CTL 2 0x3068 2 0 4294967295 LANE_RTUNE_REQ 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_SUP_PMA_IN_1 2 0x3069 2 0 4294967295 RTUNE_ACK 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_IN 2 0x306a 9 0 4294967295 RX_PMA_PWM_WORD_CLK_R 0 0 RX_PMA_PWM_WORD_CLK_OVRD_EN 1 1 RX_PMA_PWM_DATA_R 2 2 RX_PMA_PWM_DATA_OVRD_EN 3 3 RX_PMA_PWM_CLK_R 4 4 RX_PMA_PWM_CLK_OVRD_EN 5 5 RX_PMA_TERM_CTL_R 6 7 RX_PMA_TERM_CTL_OVRD_EN 8 8 RESERVED_15_9 9 15 ixDPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_OUT 2 0x306b 7 0 4294967295 RX_PMA_PWM_EN 0 0 RX_PMA_PWM_EN_OVRD_EN 1 1 RX_PMA_PWM_CLK_SEL 2 3 RX_PMA_PWM_CLK_SEL_OVRD_EN 4 4 RX_PMA_ASYNC_EN 5 5 RX_PMA_ASYNC_EN_OVRD_EN 6 6 RESERVED_15_7 7 15 ixDPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_RX_ADAPT_OVRD_OUT 2 0x306c 3 0 4294967295 RX_PMA_IQ_PHASE_ADJUST_MAP_OVRD_VAL 0 6 RX_PMA_IQ_PHASE_ADJUST_MAP_OVRD_EN 7 7 RESERVED_15_8 8 15 ixDPCSSYS_CR2_RAWLANE0_DIG_TX_CTL_TX_FSM_CTL 2 0x3080 6 0 4294967295 TX_WAIT_MPLL_OFF_TIME 0 6 TX_P2_ALLOW_RXDET 7 7 TX_P1_ALLOW_RXDET 8 8 TX_P0S_ALLOW_RXDET 9 9 TX_P0_ALLOW_RXDET 10 10 RESERVED_15_11 11 15 ixDPCSSYS_CR2_RAWLANE0_DIG_TX_CTL_TX_CLK_CTL 2 0x3081 4 0 4294967295 TX_CLK_EN 0 0 TX_CLK_SEL 1 4 ASYNC_BEACON_WAIT_TIME 5 10 RESERVED_15_11 11 15 ixDPCSSYS_CR2_RAWLANE0_DIG_TX_CTL_TX_DCC_CONT_STATUS 2 0x3082 2 0 4294967295 ENABLE 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR2_RAWLANE0_DIG_TX_CTL_OCLA 2 0x3083 2 0 4294967295 FSM_EN 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR2_RAWLANE0_DIG_TX_CTL_UPCS_OCLA 2 0x3084 3 0 4294967295 DATA_EN 0 1 CLK_EN 2 2 RESERVED_15_3 3 15 ixDPCSSYS_CR2_RAWLANE0_DIG_RX_CTL_RX_FSM_CTL 2 0x30a0 3 0 4294967295 EN_RX_CTL_FSM 0 0 RATE_CHG_IN_P1 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR2_RAWLANE0_DIG_RX_CTL_RX_LOS_MASK_CTL 2 0x30a1 2 0 4294967295 RX_LOS_MASK_CNT 0 8 RESERVED_15_9 9 15 ixDPCSSYS_CR2_RAWLANE0_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL 2 0x30a2 2 0 4294967295 RX_DATA_EN_OVRD_CNT 0 4 INT_REF_TRCK_CNT 5 15 ixDPCSSYS_CR2_RAWLANE0_DIG_RX_CTL_OFFCAN_CONT_STATUS 2 0x30a3 2 0 4294967295 ENABLE 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR2_RAWLANE0_DIG_RX_CTL_ADAPT_CONT_STATUS 2 0x30a4 2 0 4294967295 ENABLE 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR2_RAWLANE0_DIG_RX_CTL_UPCS_OCLA 2 0x30a5 3 0 4294967295 DATA_EN 0 2 CLK_EN 3 3 RESERVED_15_4 4 15 ixDPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN 2 0x30c0 11 0 4294967295 RATE_OVRD_VAL 0 1 RATE_OVRD_EN 2 2 WIDTH_OVRD_VAL 3 4 WIDTH_OVRD_EN 5 5 PSTATE_OVRD_VAL 6 7 PSTATE_OVRD_EN 8 8 LPD_OVRD_VAL 9 9 LPD_OVRD_EN 10 10 LANE_RX2TX_PAR_LB_EN_OVRD_VAL 11 11 LANE_RX2TX_PAR_LB_EN_OVRD_EN 12 12 RESERVED_15_13 13 15 ixDPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN 2 0x30c1 12 0 4294967295 PSTATE 0 1 LPD 2 2 WIDTH 3 4 RATE 5 7 MPLLB_SEL 8 8 MPLL_EN 9 9 OVRD_EN 10 10 MSTR_MPLLA_STATE 11 11 MSTR_MPLLB_STATE 12 12 MSTR_MPLL_OVRD_EN 13 13 TX_ASYNC_EN_OVR_VAL 14 14 TX_ASYNC_EN_OVR_EN 15 15 ixDPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1 2 0x30c2 13 0 4294967295 DETRX_REQ_OVRD_VAL 0 0 DETRX_REQ_OVRD_EN 1 1 VBOOST_EN_OVRD_VAL 2 2 VBOOST_EN_OVRD_EN 3 3 IBOOST_LVL_OVRD_VAL 4 7 IBOOST_LVL_OVRD_EN 8 8 TX_BEACON_EN_OVR_VAL 9 9 TX_BEACON_EN_OVR_EN 10 10 LANE_TX2RX_SER_LB_EN_OVRD_VAL 11 11 LANE_TX2RX_SER_LB_EN_OVRD_EN 12 12 TX_ASYNC_DATA_OVRD_VAL 13 13 TX_ASYNC_DATA_OVRD_EN 14 14 RESERVED_15_15 15 15 ixDPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_MASTER_MPLL_LOOP 2 0x30c3 3 0 4294967295 MPLLB_LOOP_EN 0 0 MPLLA_LOOP_EN 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1 2 0x30c4 11 0 4294967295 RESERVED 0 1 RX_LOS_LFPS_EN_OVRD_VAL 2 2 RX_LOS_LFPS_EN_OVRD_EN 3 3 RX_LOS_THRSHLD_OVRD_VAL 4 6 RX_LOS_THRSHLD_OVRD_EN 7 7 ADAPT_REQ 8 8 ADAPT_REQ_OVRD_EN 9 9 ADAPT_CONT 10 10 OFFCAN_CONT 11 11 CONT_OVRD_EN 12 12 RESERVED_15_13 13 15 ixDPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_2 2 0x30c5 4 0 4294967295 VCO_LD_VAL_OVRD 0 12 VCO_LD_VAL_OVRD_EN 13 13 VCO_LOWFREQ_VAL_OVRD 14 14 VCO_LOWFREQ_VAL_OVRD_EN 15 15 ixDPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_3 2 0x30c6 3 0 4294967295 REF_LD_VAL_OVRD 0 6 REF_LD_VAL_OVRD_EN 7 7 RESERVED_15_8 8 15 ixDPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT_2 2 0x30c7 3 0 4294967295 RX_VALID 0 0 RX_VALID_OVRD_EN 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_2 2 0x30c8 7 0 4294967295 LANE_TX2RX_SER_LB_EN_OVRD_VAL 0 0 LANE_TX2RX_SER_LB_EN_OVRD_EN 1 1 TX_DATA_EN_OVRD_VAL_R 2 2 TX_DATA_EN_OVRD_EN_R 3 3 TX_ASYNC_DATA_OVRD_VAL_R 4 4 TX_ASYNC_DATA_OVRD_EN_R 5 5 RESERVED_15_6 6 15 ixDPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN 2 0x3100 12 0 4294967295 PSTATE 0 1 LPD 2 2 WIDTH 3 4 RATE 5 7 MPLLB_SEL 8 8 MPLL_EN 9 9 OVRD_EN 10 10 MSTR_MPLLA_STATE 11 11 MSTR_MPLLB_STATE 12 12 MSTR_MPLL_OVRD_EN 13 13 TX_ASYNC_EN_OVR_VAL 14 14 TX_ASYNC_EN_OVR_EN 15 15 ixDPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1 2 0x3101 13 0 4294967295 RESET_OVRD_VAL 0 0 RESET_OVRD_EN 1 1 REQ_OVRD_VAL 2 2 REQ_OVRD_EN 3 3 DETRX_REQ_OVRD_VAL 4 4 DETRX_REQ_OVRD_EN 5 5 VBOOST_EN_OVRD_VAL 6 6 VBOOST_EN_OVRD_EN 7 7 IBOOST_LVL_OVRD_VAL 8 11 IBOOST_LVL_OVRD_EN 12 12 TX_BEACON_EN_OVR_VAL 13 13 TX_BEACON_EN_OVR_EN 14 14 RESERVED_15_15 15 15 ixDPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_PCS_IN 2 0x3102 12 0 4294967295 RESET 0 0 REQ 1 1 PSTATE 2 3 LPD 4 4 WIDTH 5 6 RATE 7 9 MPLLB_SEL 10 10 MPLL_EN 11 11 MSTR_MPLLA_STATE 12 12 MSTR_MPLLB_STATE 13 13 DETRX_REQ 14 14 RESERVED_15_15 15 15 ixDPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_OVRD_OUT 2 0x3103 6 0 4294967295 ACK 0 0 DETRX_RESULT 1 1 EN_CTL 2 2 TX_DWORD_CLK_SYNC_OVRD_VAL 3 3 TX_DWORD_CLK_SYNC_OVRD_EN 4 4 RESERVED_15_5 5 15 ixDPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_PCS_OUT 2 0x3104 2 0 4294967295 ACK 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN 2 0x3105 12 0 4294967295 RATE 0 1 WIDTH 2 3 PSTATE 4 5 LPD 6 6 OVRD_EN 7 7 ADAPT_AFE_EN 8 8 ADAPT_DFE_EN 9 9 LANE_RX2TX_PAR_LB_EN_OVRD_VAL 10 10 LANE_RX2TX_PAR_LB_EN_OVRD_EN 11 11 RX_DATA_EN_OVRD_VAL_R 12 12 RX_DATA_EN_OVRD_EN_R 13 13 RESERVED_15_14 14 15 ixDPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1 2 0x3106 12 0 4294967295 RESET_OVRD_VAL 0 0 RESET_OVRD_EN 1 1 REQ_OVRD_VAL 2 2 REQ_OVRD_EN 3 3 RX_LOS_THRSHLD_OVRD_VAL 4 6 RX_LOS_THRSHLD_OVRD_EN 7 7 ADAPT_REQ 8 8 ADAPT_REQ_OVRD_EN 9 9 ADAPT_CONT 10 10 OFFCAN_CONT 11 11 CONT_OVRD_EN 12 12 RESERVED_15_13 13 15 ixDPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_2 2 0x3107 4 0 4294967295 VCO_LD_VAL_OVRD 0 12 VCO_LD_VAL_OVRD_EN 13 13 VCO_LOWFREQ_VAL_OVRD 14 14 VCO_LOWFREQ_VAL_OVRD_EN 15 15 ixDPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_3 2 0x3108 3 0 4294967295 REF_LD_VAL_OVRD 0 6 REF_LD_VAL_OVRD_EN 7 7 RESERVED_15_8 8 15 ixDPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_PCS_IN 2 0x3109 13 0 4294967295 REQ 0 0 RATE 1 2 WIDTH 3 4 PSTATE 5 6 LPD 7 7 CDR_VCO_LOWFREQ 8 8 ADAPT_AFE_EN 9 9 ADAPT_DFE_EN 10 10 ADAPT_REQ 11 11 ADAPT_CONT 12 12 OFFCAN_CONT 13 13 RESET 14 14 RESERVED_15_15 15 15 ixDPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_1 2 0x310a 2 0 4294967295 REF_LD_VAL 0 6 RESERVED_15_7 7 15 ixDPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_2 2 0x310b 2 0 4294967295 VCO_LD_VAL 0 12 RESERVED_15_13 13 15 ixDPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_3 2 0x310c 4 0 4294967295 EQ_ATT_LVL 0 2 EQ_VGA1_GAIN 3 6 EQ_VGA2_GAIN 7 10 EQ_CTLE_BOOST 11 15 ixDPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_4 2 0x310d 3 0 4294967295 EQ_CTLE_POLE 0 2 EQ_DFE_TAP1 3 10 RESERVED_15_11 11 15 ixDPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT 2 0x310e 3 0 4294967295 ACK 0 0 EN_CTL 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_PCS_OUT 2 0x310f 2 0 4294967295 ACK 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_ADAPT_ACK 2 0x3110 2 0 4294967295 RX_ADAPT_ACK 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_ADAPT_FOM 2 0x3111 2 0 4294967295 RX_ADAPT_FOM 0 7 RESERVED_15_8 8 15 ixDPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_TXPRE_DIR 2 0x3112 2 0 4294967295 RX_TXPRE_DIR 0 1 RESERVED_15_2 2 15 ixDPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_TXMAIN_DIR 2 0x3113 2 0 4294967295 RX_TXMAIN_DIR 0 1 RESERVED_15_2 2 15 ixDPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_TXPOST_DIR 2 0x3114 2 0 4294967295 RX_TXPOST_DIR 0 1 RESERVED_15_2 2 15 ixDPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_LANE_NUMBER 2 0x3115 2 0 4294967295 LANE_NUMBER 0 3 RESERVED_15_4 4 15 ixDPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RESERVED_1 2 0x3116 1 0 4294967295 RESERVED_REG_1 0 15 ixDPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RESERVED_2 2 0x3117 1 0 4294967295 RESERVED_REG_2 0 15 ixDPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN 2 0x3118 16 0 4294967295 RX_RESET_ATE_OVRD_VAL 0 0 RX_RESET_ATE_OVRD_EN 1 1 TX_RESET_ATE_OVRD_VAL 2 2 TX_RESET_ATE_OVRD_EN 3 3 RX_REQ_ATE_OVRD_VAL 4 4 RX_REQ_ATE_OVRD_EN 5 5 TX_REQ_ATE_OVRD_VAL 6 6 TX_REQ_ATE_OVRD_EN 7 7 RX_ADAPT_AFE_EN_OVRD_VAL 8 8 RX_ADAPT_AFE_EN_OVRD_EN 9 9 RX_ADAPT_DFE_EN_OVRD_VAL 10 10 RX_ADAPT_DFE_EN_OVRD_EN 11 11 TX_DATA_EN_ATE_OVRD_VAL 12 12 TX_DATA_EN_ATE_OVRD_EN 13 13 RX_DATA_EN_ATE_OVRD_VAL 14 14 RX_DATA_EN_ATE_OVRD_EN 15 15 ixDPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN 2 0x3119 3 0 4294967295 RX_EQ_DELTA_IQ_OVRD_VAL 0 3 RX_EQ_DELTA_IQ_OVRD_EN 4 4 RESERVED_15_5 5 15 ixDPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN 2 0x311a 5 0 4294967295 RX_TERM_CTRL_OVRD_VAL 0 2 RX_TERM_CTRL_OVRD_EN 3 3 TX_TERM_CTRL_OVRD_VAL 4 6 TX_TERM_CTRL_OVRD_EN 7 7 RESERVED_15_8 8 15 ixDPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TXRX_TERM_CTRL_IN 2 0x311b 3 0 4294967295 RX_TERM_CTRL 0 2 TX_TERM_CTRL 3 5 RESERVED_15_6 6 15 ixDPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT_1 2 0x311c 2 0 4294967295 RX_CLK_EN 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_EQ_OVRD_IN_1 2 0x311d 4 0 4294967295 RX_EQ_AFE_GAIN_OVRD_VAL 0 3 RX_EQ_ATT_LVL_OVRD_VAL 4 6 RX_EQ_OVRD_EN 7 7 RESERVED_15_8 8 15 ixDPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_EQ_OVRD_IN_2 2 0x311e 3 0 4294967295 RX_EQ_DFE_TAP1_OVRD_VAL 0 7 RX_EQ_CTLE_BOOST_OVRD_VAL 8 12 RESERVED_15_13 13 15 ixDPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_PH2_CAL 2 0x311f 4 0 4294967295 PH2_CAL_ACK_VAL 0 0 PH2_CAL_REQ_VAL 1 1 PH2_CAL_REQ_OVRD_VAL 2 2 RESERVED_15_3 3 15 ixDPCSSYS_CR2_RAWLANE1_DIG_FSM_FSM_OVRD_CTL 2 0x3120 5 0 4294967295 FSM_JMP_ADDR 0 11 FSM_JMP_EN 12 12 FSM_CMD_START 13 13 FSM_OVRD_EN 14 14 FSM_BREAK 15 15 ixDPCSSYS_CR2_RAWLANE1_DIG_FSM_MEM_ADDR_MON 2 0x3121 1 0 4294967295 MEM_ADDR 0 15 ixDPCSSYS_CR2_RAWLANE1_DIG_FSM_STATUS_MON 2 0x3122 8 0 4294967295 STATE 0 4 CMD_RDY 5 5 ALU_OVFLW 6 6 ALU_RES_EQ0 7 7 WAIT_CNT_EQ0 8 8 WRMSK_DISABLED 9 9 RDMSK_DISABLED 10 10 RESERVED_15_11 11 15 ixDPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_RX_STARTUP_CAL 2 0x3123 2 0 4294967295 FAST_RX_STARTUP_CAL 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_RX_ADAPT 2 0x3124 2 0 4294967295 FAST_RX_ADAPT 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_RX_AFE_CAL 2 0x3125 2 0 4294967295 FAST_RX_AFE_CAL 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_RX_DFE_CAL 2 0x3126 2 0 4294967295 FAST_RX_DFE_CAL 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_RX_BYPASS_CAL 2 0x3127 2 0 4294967295 FAST_RX_BYPASS_CAL 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_RX_REFLVL_CAL 2 0x3128 2 0 4294967295 FAST_RX_REFLVL_CAL 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_RX_IQ_CAL 2 0x3129 2 0 4294967295 FAST_RX_IQ_CAL 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_RX_AFE_ADAPT 2 0x312a 2 0 4294967295 FAST_RX_AFE_ADAPT 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_RX_DFE_ADAPT 2 0x312b 2 0 4294967295 FAST_RX_DFE_ADAPT 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_SUP 2 0x312c 2 0 4294967295 FAST_SUP 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_TX_CMN_MODE 2 0x312d 2 0 4294967295 FAST_TX_CMN_MODE 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_TX_RXDET 2 0x312e 2 0 4294967295 FAST_TX_RXDET 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_RX_PWRUP 2 0x312f 2 0 4294967295 FAST_RX_PWRUP 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_RX_VCO_WAIT 2 0x3130 2 0 4294967295 FAST_RX_VCO_WAIT 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_RX_VCO_CAL 2 0x3131 2 0 4294967295 FAST_RX_VCO_CAL 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR2_RAWLANE1_DIG_FSM_CMNCAL_MPLL_STATUS 2 0x3132 3 0 4294967295 CMNCAL_MPLL_INIT 0 0 CMNCAL_MPLL_DONE 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_RX_CONT_CAL_ADAPT 2 0x3133 2 0 4294967295 FAST_RX_CONT_CAL_ADAPT 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_RX_CONT_ADAPT 2 0x3134 2 0 4294967295 FAST_RX_CONT_ADAPT 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_RX_CONT_DATA_CAL 2 0x3135 2 0 4294967295 FAST_RX_CONT_DATA_CAL 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_RX_CONT_PHASE_CAL 2 0x3136 2 0 4294967295 FAST_RX_CONT_PHASE_CAL 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_RX_CONT_AFE_CAL 2 0x3137 2 0 4294967295 FAST_RX_CONT_AFE_CAL 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_FLAGS 2 0x3138 12 0 4294967295 TX_FAST_DCC_CAL 0 0 RX_FAST_DCC_CAL 1 1 RX_FAST_VPHUD_CAL 2 2 RX_FAST_VREF_CAL 3 3 RX_FAST_SIGDET_CAL 4 4 RESERVED_2 5 7 TX_FAST_CONT_DCC_CAL 8 8 RX_FAST_CONT_DCC_CAL 9 9 RX_FAST_CONT_VPHUD_CAL 10 10 RX_FAST_CONT_VREF_CAL 11 11 RESERVED_1 12 14 TX_SKIP_SUP_CAL 15 15 ixDPCSSYS_CR2_RAWLANE1_DIG_FSM_CR_LOCK 2 0x3139 3 0 4294967295 CR_REG_LOCK 0 0 CR_MEM_LOCK 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR2_RAWLANE1_DIG_FSM_TX_DCC_FLAGS 2 0x313a 4 0 4294967295 RATE 0 0 DIV 1 1 MPLL 2 2 RESERVED_15_3 3 15 ixDPCSSYS_CR2_RAWLANE1_DIG_FSM_TX_DCC_STATUS 2 0x313b 2 0 4294967295 FLAG 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR2_RAWLANE1_DIG_FSM_OCLA 2 0x313c 4 0 4294967295 PC_EN 0 0 REG_BANK1_EN 1 1 REG_BANK2_EN 2 2 RESERVED_15_3 3 15 ixDPCSSYS_CR2_RAWLANE1_DIG_FSM_TX_EQ_UPDATE_FLAG 2 0x313d 2 0 4294967295 TX_EQ_UPDATE_FLAG 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR2_RAWLANE1_DIG_FSM_CMNCAL_RCAL_STATUS 2 0x313e 3 0 4294967295 CMNCAL_RCAL_INIT 0 0 CMNCAL_RCAL_DONE 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR2_RAWLANE1_DIG_FSM_RX_IQ_PHASE_OFFSET 2 0x313f 2 0 4294967295 RX_IQ_PHASE_OFFSET 0 3 RESERVED_15_4 4 15 ixDPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_RESET_RTN_REQ 2 0x3140 2 0 4294967295 RESET_RTN_REQ 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_RX_RESET_IRQ 2 0x3141 2 0 4294967295 RX_RESET 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_RX_REQ_IRQ 2 0x3142 2 0 4294967295 RX_REQ 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_RX_RATE_IRQ 2 0x3143 2 0 4294967295 RX_RATE_IRQ 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_RX_PSTATE_IRQ 2 0x3144 2 0 4294967295 RX_PSTATE_IRQ 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ 2 0x3145 2 0 4294967295 RX_ADAPT_REQ_IRQ 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ 2 0x3146 2 0 4294967295 RX_ADAPT_DIS_IRQ 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_RX_RESET_IRQ_CLR 2 0x3147 2 0 4294967295 RX_RESET_IRQ_CLR 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_RX_REQ_IRQ_CLR 2 0x3148 2 0 4294967295 RX_REQ_IRQ_CLR 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_RX_RATE_IRQ_CLR 2 0x3149 2 0 4294967295 RX_RATE_IRQ_CLR 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR 2 0x314a 2 0 4294967295 RX_PSTATE_IRQ_CLR 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR 2 0x314b 2 0 4294967295 RX_ADAPT_REQ_IRQ_CLR 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR 2 0x314c 2 0 4294967295 RX_ADAPT_DIS_IRQ_CLR 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK 2 0x314d 12 0 4294967295 RX_REQ_IRQ_MSK 0 0 RX_RATE_IRQ_MSK 1 1 RX_PSTATE_IRQ_MSK 2 2 RX_ADAPT_REQ_IRQ_MSK 3 3 RX_ADAPT_DIS_IRQ_MSK 4 4 RX_RESET_IRQ_MSK 5 5 LANE_XCVR_MODE_IRQ_MSK 6 6 RX_PH2_CAL_REQ_IRQ_MSK 7 7 RX_PH2_CAL_DIS_IRQ_MSK 8 8 LANE_RX2TX_SER_LB_EN_IRQ_MSK 9 9 DCC_ONDMD_IRQ_MSK 10 10 RESERVED_15_11 11 15 ixDPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK_2 2 0x314e 3 0 4294967295 TX_RESET_IRQ_MSK 0 0 TX_REQ_IRQ_MSK 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ 2 0x314f 2 0 4294967295 LANE_XCVR_MODE_IRQ 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR 2 0x3150 2 0 4294967295 LANE_XCVR_MODE_IRQ_CLR 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ 2 0x3151 2 0 4294967295 RX_PH2_CAL_REQ_IRQ 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ 2 0x3152 2 0 4294967295 RX_PH2_CAL_DIS_IRQ 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR 2 0x3153 2 0 4294967295 RX_PH2_CAL_REQ_IRQ_CLR 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR 2 0x3154 2 0 4294967295 RX_PH2_CAL_DIS_IRQ_CLR 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ 2 0x3155 2 0 4294967295 LANE_RX2TX_SER_LB_EN_IRQ 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR 2 0x3156 2 0 4294967295 LANE_RX2TX_SER_LB_EN_IRQ_CLR 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_DCC_ONDMD_IRQ 2 0x3157 2 0 4294967295 IRQ 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_TX_RESET_IRQ 2 0x3158 2 0 4294967295 TX_RESET 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_TX_REQ_IRQ 2 0x3159 2 0 4294967295 TX_REQ 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_TX_RESET_IRQ_CLR 2 0x315a 2 0 4294967295 TX_RESET_IRQ_CLR 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_TX_REQ_IRQ_CLR 2 0x315b 2 0 4294967295 TX_REQ_IRQ_CLR 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_LANE_OVRD_IN 2 0x3160 4 0 4294967295 LANE_MPLLA_EN_IN 0 0 LANE_MPLLB_EN_IN 1 1 LANE_OVRD_EN 2 2 RESERVED_15_3 3 15 ixDPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_LANE_OVRD_OUT 2 0x3161 4 0 4294967295 LANE_MPLLA_EN_OUT 0 0 LANE_MPLLB_EN_OUT 1 1 LANE_OVRD_EN 2 2 RESERVED_15_3 3 15 ixDPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_SUP_OVRD_IN 2 0x3162 4 0 4294967295 MPLLA_STATE 0 0 MPLLB_STATE 1 1 SUP_STATE_OVRD_EN 2 2 RESERVED_15_3 3 15 ixDPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_SUP_PMA_IN 2 0x3163 3 0 4294967295 MPLLA_STATE 0 0 MPLLB_STATE 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT 2 0x3164 16 0 4294967295 TX_REQ_OVRD_VAL 0 0 TX_REQ_OVRD_EN 1 1 TX_RESET_OVRD_VAL 2 2 TX_RESET_OVRD_EN 3 3 TX_BEACON_EN_OVRD_VAL 4 4 TX_BEACON_EN_OVRD_EN 5 5 TX_ASYNC_DRV_EN_OVRD_VAL 6 6 TX_ASYNC_DRV_EN_OVRD_EN 7 7 TX_ASYNC_EN_OVRD_VAL 8 8 TX_ASYNC_EN_OVRD_EN 9 9 TX_DWORD_CLK_SYNC_OVRD_VAL 10 10 TX_DWORD_CLK_SYNC_OVRD_EN 11 11 LANE_TX2RX_SER_LB_EN_OVRD_VAL 12 12 LANE_TX2RX_SER_LB_EN_OVRD_EN 13 13 TX_PMA_DATA_EN_OVRD_VAL_R 14 14 TX_PMA_DATA_EN_OVRD_EN_R 15 15 ixDPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_TX_PMA_IN 2 0x3165 2 0 4294967295 ACK 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT 2 0x3166 9 0 4294967295 RX_REQ_OVRD_VAL 0 0 RX_REQ_OVRD_EN 1 1 RX_RESET_OVRD_VAL 2 2 RX_RESET_OVRD_EN 3 3 LANE_RX2TX_PAR_LB_EN_OVRD_VAL 4 4 LANE_RX2TX_PAR_LB_EN_OVRD_EN 5 5 RX_PMA_DATA_EN_OVRD_VAL_R 6 6 RX_PMA_DATA_EN_OVRD_EN_R 7 7 RESERVED_15_8 8 15 ixDPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_RX_PMA_IN 2 0x3167 2 0 4294967295 ACK 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_LANE_RTUNE_CTL 2 0x3168 2 0 4294967295 LANE_RTUNE_REQ 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_SUP_PMA_IN_1 2 0x3169 2 0 4294967295 RTUNE_ACK 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_IN 2 0x316a 9 0 4294967295 RX_PMA_PWM_WORD_CLK_R 0 0 RX_PMA_PWM_WORD_CLK_OVRD_EN 1 1 RX_PMA_PWM_DATA_R 2 2 RX_PMA_PWM_DATA_OVRD_EN 3 3 RX_PMA_PWM_CLK_R 4 4 RX_PMA_PWM_CLK_OVRD_EN 5 5 RX_PMA_TERM_CTL_R 6 7 RX_PMA_TERM_CTL_OVRD_EN 8 8 RESERVED_15_9 9 15 ixDPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_OUT 2 0x316b 7 0 4294967295 RX_PMA_PWM_EN 0 0 RX_PMA_PWM_EN_OVRD_EN 1 1 RX_PMA_PWM_CLK_SEL 2 3 RX_PMA_PWM_CLK_SEL_OVRD_EN 4 4 RX_PMA_ASYNC_EN 5 5 RX_PMA_ASYNC_EN_OVRD_EN 6 6 RESERVED_15_7 7 15 ixDPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_RX_ADAPT_OVRD_OUT 2 0x316c 3 0 4294967295 RX_PMA_IQ_PHASE_ADJUST_MAP_OVRD_VAL 0 6 RX_PMA_IQ_PHASE_ADJUST_MAP_OVRD_EN 7 7 RESERVED_15_8 8 15 ixDPCSSYS_CR2_RAWLANE1_DIG_TX_CTL_TX_FSM_CTL 2 0x3180 6 0 4294967295 TX_WAIT_MPLL_OFF_TIME 0 6 TX_P2_ALLOW_RXDET 7 7 TX_P1_ALLOW_RXDET 8 8 TX_P0S_ALLOW_RXDET 9 9 TX_P0_ALLOW_RXDET 10 10 RESERVED_15_11 11 15 ixDPCSSYS_CR2_RAWLANE1_DIG_TX_CTL_TX_CLK_CTL 2 0x3181 4 0 4294967295 TX_CLK_EN 0 0 TX_CLK_SEL 1 4 ASYNC_BEACON_WAIT_TIME 5 10 RESERVED_15_11 11 15 ixDPCSSYS_CR2_RAWLANE1_DIG_TX_CTL_TX_DCC_CONT_STATUS 2 0x3182 2 0 4294967295 ENABLE 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR2_RAWLANE1_DIG_TX_CTL_OCLA 2 0x3183 2 0 4294967295 FSM_EN 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR2_RAWLANE1_DIG_TX_CTL_UPCS_OCLA 2 0x3184 3 0 4294967295 DATA_EN 0 1 CLK_EN 2 2 RESERVED_15_3 3 15 ixDPCSSYS_CR2_RAWLANE1_DIG_RX_CTL_RX_FSM_CTL 2 0x31a0 3 0 4294967295 EN_RX_CTL_FSM 0 0 RATE_CHG_IN_P1 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR2_RAWLANE1_DIG_RX_CTL_RX_LOS_MASK_CTL 2 0x31a1 2 0 4294967295 RX_LOS_MASK_CNT 0 8 RESERVED_15_9 9 15 ixDPCSSYS_CR2_RAWLANE1_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL 2 0x31a2 2 0 4294967295 RX_DATA_EN_OVRD_CNT 0 4 INT_REF_TRCK_CNT 5 15 ixDPCSSYS_CR2_RAWLANE1_DIG_RX_CTL_OFFCAN_CONT_STATUS 2 0x31a3 2 0 4294967295 ENABLE 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR2_RAWLANE1_DIG_RX_CTL_ADAPT_CONT_STATUS 2 0x31a4 2 0 4294967295 ENABLE 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR2_RAWLANE1_DIG_RX_CTL_UPCS_OCLA 2 0x31a5 3 0 4294967295 DATA_EN 0 2 CLK_EN 3 3 RESERVED_15_4 4 15 ixDPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN 2 0x31c0 11 0 4294967295 RATE_OVRD_VAL 0 1 RATE_OVRD_EN 2 2 WIDTH_OVRD_VAL 3 4 WIDTH_OVRD_EN 5 5 PSTATE_OVRD_VAL 6 7 PSTATE_OVRD_EN 8 8 LPD_OVRD_VAL 9 9 LPD_OVRD_EN 10 10 LANE_RX2TX_PAR_LB_EN_OVRD_VAL 11 11 LANE_RX2TX_PAR_LB_EN_OVRD_EN 12 12 RESERVED_15_13 13 15 ixDPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN 2 0x31c1 12 0 4294967295 PSTATE 0 1 LPD 2 2 WIDTH 3 4 RATE 5 7 MPLLB_SEL 8 8 MPLL_EN 9 9 OVRD_EN 10 10 MSTR_MPLLA_STATE 11 11 MSTR_MPLLB_STATE 12 12 MSTR_MPLL_OVRD_EN 13 13 TX_ASYNC_EN_OVR_VAL 14 14 TX_ASYNC_EN_OVR_EN 15 15 ixDPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1 2 0x31c2 13 0 4294967295 DETRX_REQ_OVRD_VAL 0 0 DETRX_REQ_OVRD_EN 1 1 VBOOST_EN_OVRD_VAL 2 2 VBOOST_EN_OVRD_EN 3 3 IBOOST_LVL_OVRD_VAL 4 7 IBOOST_LVL_OVRD_EN 8 8 TX_BEACON_EN_OVR_VAL 9 9 TX_BEACON_EN_OVR_EN 10 10 LANE_TX2RX_SER_LB_EN_OVRD_VAL 11 11 LANE_TX2RX_SER_LB_EN_OVRD_EN 12 12 TX_ASYNC_DATA_OVRD_VAL 13 13 TX_ASYNC_DATA_OVRD_EN 14 14 RESERVED_15_15 15 15 ixDPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_MASTER_MPLL_LOOP 2 0x31c3 3 0 4294967295 MPLLB_LOOP_EN 0 0 MPLLA_LOOP_EN 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1 2 0x31c4 11 0 4294967295 RESERVED 0 1 RX_LOS_LFPS_EN_OVRD_VAL 2 2 RX_LOS_LFPS_EN_OVRD_EN 3 3 RX_LOS_THRSHLD_OVRD_VAL 4 6 RX_LOS_THRSHLD_OVRD_EN 7 7 ADAPT_REQ 8 8 ADAPT_REQ_OVRD_EN 9 9 ADAPT_CONT 10 10 OFFCAN_CONT 11 11 CONT_OVRD_EN 12 12 RESERVED_15_13 13 15 ixDPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_2 2 0x31c5 4 0 4294967295 VCO_LD_VAL_OVRD 0 12 VCO_LD_VAL_OVRD_EN 13 13 VCO_LOWFREQ_VAL_OVRD 14 14 VCO_LOWFREQ_VAL_OVRD_EN 15 15 ixDPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_3 2 0x31c6 3 0 4294967295 REF_LD_VAL_OVRD 0 6 REF_LD_VAL_OVRD_EN 7 7 RESERVED_15_8 8 15 ixDPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT_2 2 0x31c7 3 0 4294967295 RX_VALID 0 0 RX_VALID_OVRD_EN 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_2 2 0x31c8 7 0 4294967295 LANE_TX2RX_SER_LB_EN_OVRD_VAL 0 0 LANE_TX2RX_SER_LB_EN_OVRD_EN 1 1 TX_DATA_EN_OVRD_VAL_R 2 2 TX_DATA_EN_OVRD_EN_R 3 3 TX_ASYNC_DATA_OVRD_VAL_R 4 4 TX_ASYNC_DATA_OVRD_EN_R 5 5 RESERVED_15_6 6 15 ixDPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN 2 0x3200 12 0 4294967295 PSTATE 0 1 LPD 2 2 WIDTH 3 4 RATE 5 7 MPLLB_SEL 8 8 MPLL_EN 9 9 OVRD_EN 10 10 MSTR_MPLLA_STATE 11 11 MSTR_MPLLB_STATE 12 12 MSTR_MPLL_OVRD_EN 13 13 TX_ASYNC_EN_OVR_VAL 14 14 TX_ASYNC_EN_OVR_EN 15 15 ixDPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1 2 0x3201 13 0 4294967295 RESET_OVRD_VAL 0 0 RESET_OVRD_EN 1 1 REQ_OVRD_VAL 2 2 REQ_OVRD_EN 3 3 DETRX_REQ_OVRD_VAL 4 4 DETRX_REQ_OVRD_EN 5 5 VBOOST_EN_OVRD_VAL 6 6 VBOOST_EN_OVRD_EN 7 7 IBOOST_LVL_OVRD_VAL 8 11 IBOOST_LVL_OVRD_EN 12 12 TX_BEACON_EN_OVR_VAL 13 13 TX_BEACON_EN_OVR_EN 14 14 RESERVED_15_15 15 15 ixDPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_PCS_IN 2 0x3202 12 0 4294967295 RESET 0 0 REQ 1 1 PSTATE 2 3 LPD 4 4 WIDTH 5 6 RATE 7 9 MPLLB_SEL 10 10 MPLL_EN 11 11 MSTR_MPLLA_STATE 12 12 MSTR_MPLLB_STATE 13 13 DETRX_REQ 14 14 RESERVED_15_15 15 15 ixDPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_OVRD_OUT 2 0x3203 6 0 4294967295 ACK 0 0 DETRX_RESULT 1 1 EN_CTL 2 2 TX_DWORD_CLK_SYNC_OVRD_VAL 3 3 TX_DWORD_CLK_SYNC_OVRD_EN 4 4 RESERVED_15_5 5 15 ixDPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_PCS_OUT 2 0x3204 2 0 4294967295 ACK 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN 2 0x3205 12 0 4294967295 RATE 0 1 WIDTH 2 3 PSTATE 4 5 LPD 6 6 OVRD_EN 7 7 ADAPT_AFE_EN 8 8 ADAPT_DFE_EN 9 9 LANE_RX2TX_PAR_LB_EN_OVRD_VAL 10 10 LANE_RX2TX_PAR_LB_EN_OVRD_EN 11 11 RX_DATA_EN_OVRD_VAL_R 12 12 RX_DATA_EN_OVRD_EN_R 13 13 RESERVED_15_14 14 15 ixDPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1 2 0x3206 12 0 4294967295 RESET_OVRD_VAL 0 0 RESET_OVRD_EN 1 1 REQ_OVRD_VAL 2 2 REQ_OVRD_EN 3 3 RX_LOS_THRSHLD_OVRD_VAL 4 6 RX_LOS_THRSHLD_OVRD_EN 7 7 ADAPT_REQ 8 8 ADAPT_REQ_OVRD_EN 9 9 ADAPT_CONT 10 10 OFFCAN_CONT 11 11 CONT_OVRD_EN 12 12 RESERVED_15_13 13 15 ixDPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_2 2 0x3207 4 0 4294967295 VCO_LD_VAL_OVRD 0 12 VCO_LD_VAL_OVRD_EN 13 13 VCO_LOWFREQ_VAL_OVRD 14 14 VCO_LOWFREQ_VAL_OVRD_EN 15 15 ixDPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_3 2 0x3208 3 0 4294967295 REF_LD_VAL_OVRD 0 6 REF_LD_VAL_OVRD_EN 7 7 RESERVED_15_8 8 15 ixDPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_PCS_IN 2 0x3209 13 0 4294967295 REQ 0 0 RATE 1 2 WIDTH 3 4 PSTATE 5 6 LPD 7 7 CDR_VCO_LOWFREQ 8 8 ADAPT_AFE_EN 9 9 ADAPT_DFE_EN 10 10 ADAPT_REQ 11 11 ADAPT_CONT 12 12 OFFCAN_CONT 13 13 RESET 14 14 RESERVED_15_15 15 15 ixDPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_1 2 0x320a 2 0 4294967295 REF_LD_VAL 0 6 RESERVED_15_7 7 15 ixDPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_2 2 0x320b 2 0 4294967295 VCO_LD_VAL 0 12 RESERVED_15_13 13 15 ixDPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_3 2 0x320c 4 0 4294967295 EQ_ATT_LVL 0 2 EQ_VGA1_GAIN 3 6 EQ_VGA2_GAIN 7 10 EQ_CTLE_BOOST 11 15 ixDPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_4 2 0x320d 3 0 4294967295 EQ_CTLE_POLE 0 2 EQ_DFE_TAP1 3 10 RESERVED_15_11 11 15 ixDPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT 2 0x320e 3 0 4294967295 ACK 0 0 EN_CTL 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_PCS_OUT 2 0x320f 2 0 4294967295 ACK 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_ADAPT_ACK 2 0x3210 2 0 4294967295 RX_ADAPT_ACK 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_ADAPT_FOM 2 0x3211 2 0 4294967295 RX_ADAPT_FOM 0 7 RESERVED_15_8 8 15 ixDPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_TXPRE_DIR 2 0x3212 2 0 4294967295 RX_TXPRE_DIR 0 1 RESERVED_15_2 2 15 ixDPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_TXMAIN_DIR 2 0x3213 2 0 4294967295 RX_TXMAIN_DIR 0 1 RESERVED_15_2 2 15 ixDPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_TXPOST_DIR 2 0x3214 2 0 4294967295 RX_TXPOST_DIR 0 1 RESERVED_15_2 2 15 ixDPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_LANE_NUMBER 2 0x3215 2 0 4294967295 LANE_NUMBER 0 3 RESERVED_15_4 4 15 ixDPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RESERVED_1 2 0x3216 1 0 4294967295 RESERVED_REG_1 0 15 ixDPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RESERVED_2 2 0x3217 1 0 4294967295 RESERVED_REG_2 0 15 ixDPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN 2 0x3218 16 0 4294967295 RX_RESET_ATE_OVRD_VAL 0 0 RX_RESET_ATE_OVRD_EN 1 1 TX_RESET_ATE_OVRD_VAL 2 2 TX_RESET_ATE_OVRD_EN 3 3 RX_REQ_ATE_OVRD_VAL 4 4 RX_REQ_ATE_OVRD_EN 5 5 TX_REQ_ATE_OVRD_VAL 6 6 TX_REQ_ATE_OVRD_EN 7 7 RX_ADAPT_AFE_EN_OVRD_VAL 8 8 RX_ADAPT_AFE_EN_OVRD_EN 9 9 RX_ADAPT_DFE_EN_OVRD_VAL 10 10 RX_ADAPT_DFE_EN_OVRD_EN 11 11 TX_DATA_EN_ATE_OVRD_VAL 12 12 TX_DATA_EN_ATE_OVRD_EN 13 13 RX_DATA_EN_ATE_OVRD_VAL 14 14 RX_DATA_EN_ATE_OVRD_EN 15 15 ixDPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN 2 0x3219 3 0 4294967295 RX_EQ_DELTA_IQ_OVRD_VAL 0 3 RX_EQ_DELTA_IQ_OVRD_EN 4 4 RESERVED_15_5 5 15 ixDPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN 2 0x321a 5 0 4294967295 RX_TERM_CTRL_OVRD_VAL 0 2 RX_TERM_CTRL_OVRD_EN 3 3 TX_TERM_CTRL_OVRD_VAL 4 6 TX_TERM_CTRL_OVRD_EN 7 7 RESERVED_15_8 8 15 ixDPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TXRX_TERM_CTRL_IN 2 0x321b 3 0 4294967295 RX_TERM_CTRL 0 2 TX_TERM_CTRL 3 5 RESERVED_15_6 6 15 ixDPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT_1 2 0x321c 2 0 4294967295 RX_CLK_EN 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_EQ_OVRD_IN_1 2 0x321d 4 0 4294967295 RX_EQ_AFE_GAIN_OVRD_VAL 0 3 RX_EQ_ATT_LVL_OVRD_VAL 4 6 RX_EQ_OVRD_EN 7 7 RESERVED_15_8 8 15 ixDPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_EQ_OVRD_IN_2 2 0x321e 3 0 4294967295 RX_EQ_DFE_TAP1_OVRD_VAL 0 7 RX_EQ_CTLE_BOOST_OVRD_VAL 8 12 RESERVED_15_13 13 15 ixDPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_PH2_CAL 2 0x321f 4 0 4294967295 PH2_CAL_ACK_VAL 0 0 PH2_CAL_REQ_VAL 1 1 PH2_CAL_REQ_OVRD_VAL 2 2 RESERVED_15_3 3 15 ixDPCSSYS_CR2_RAWLANE2_DIG_FSM_FSM_OVRD_CTL 2 0x3220 5 0 4294967295 FSM_JMP_ADDR 0 11 FSM_JMP_EN 12 12 FSM_CMD_START 13 13 FSM_OVRD_EN 14 14 FSM_BREAK 15 15 ixDPCSSYS_CR2_RAWLANE2_DIG_FSM_MEM_ADDR_MON 2 0x3221 1 0 4294967295 MEM_ADDR 0 15 ixDPCSSYS_CR2_RAWLANE2_DIG_FSM_STATUS_MON 2 0x3222 8 0 4294967295 STATE 0 4 CMD_RDY 5 5 ALU_OVFLW 6 6 ALU_RES_EQ0 7 7 WAIT_CNT_EQ0 8 8 WRMSK_DISABLED 9 9 RDMSK_DISABLED 10 10 RESERVED_15_11 11 15 ixDPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_RX_STARTUP_CAL 2 0x3223 2 0 4294967295 FAST_RX_STARTUP_CAL 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_RX_ADAPT 2 0x3224 2 0 4294967295 FAST_RX_ADAPT 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_RX_AFE_CAL 2 0x3225 2 0 4294967295 FAST_RX_AFE_CAL 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_RX_DFE_CAL 2 0x3226 2 0 4294967295 FAST_RX_DFE_CAL 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_RX_BYPASS_CAL 2 0x3227 2 0 4294967295 FAST_RX_BYPASS_CAL 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_RX_REFLVL_CAL 2 0x3228 2 0 4294967295 FAST_RX_REFLVL_CAL 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_RX_IQ_CAL 2 0x3229 2 0 4294967295 FAST_RX_IQ_CAL 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_RX_AFE_ADAPT 2 0x322a 2 0 4294967295 FAST_RX_AFE_ADAPT 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_RX_DFE_ADAPT 2 0x322b 2 0 4294967295 FAST_RX_DFE_ADAPT 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_SUP 2 0x322c 2 0 4294967295 FAST_SUP 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_TX_CMN_MODE 2 0x322d 2 0 4294967295 FAST_TX_CMN_MODE 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_TX_RXDET 2 0x322e 2 0 4294967295 FAST_TX_RXDET 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_RX_PWRUP 2 0x322f 2 0 4294967295 FAST_RX_PWRUP 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_RX_VCO_WAIT 2 0x3230 2 0 4294967295 FAST_RX_VCO_WAIT 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_RX_VCO_CAL 2 0x3231 2 0 4294967295 FAST_RX_VCO_CAL 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR2_RAWLANE2_DIG_FSM_CMNCAL_MPLL_STATUS 2 0x3232 3 0 4294967295 CMNCAL_MPLL_INIT 0 0 CMNCAL_MPLL_DONE 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_RX_CONT_CAL_ADAPT 2 0x3233 2 0 4294967295 FAST_RX_CONT_CAL_ADAPT 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_RX_CONT_ADAPT 2 0x3234 2 0 4294967295 FAST_RX_CONT_ADAPT 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_RX_CONT_DATA_CAL 2 0x3235 2 0 4294967295 FAST_RX_CONT_DATA_CAL 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_RX_CONT_PHASE_CAL 2 0x3236 2 0 4294967295 FAST_RX_CONT_PHASE_CAL 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_RX_CONT_AFE_CAL 2 0x3237 2 0 4294967295 FAST_RX_CONT_AFE_CAL 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_FLAGS 2 0x3238 12 0 4294967295 TX_FAST_DCC_CAL 0 0 RX_FAST_DCC_CAL 1 1 RX_FAST_VPHUD_CAL 2 2 RX_FAST_VREF_CAL 3 3 RX_FAST_SIGDET_CAL 4 4 RESERVED_2 5 7 TX_FAST_CONT_DCC_CAL 8 8 RX_FAST_CONT_DCC_CAL 9 9 RX_FAST_CONT_VPHUD_CAL 10 10 RX_FAST_CONT_VREF_CAL 11 11 RESERVED_1 12 14 TX_SKIP_SUP_CAL 15 15 ixDPCSSYS_CR2_RAWLANE2_DIG_FSM_CR_LOCK 2 0x3239 3 0 4294967295 CR_REG_LOCK 0 0 CR_MEM_LOCK 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR2_RAWLANE2_DIG_FSM_TX_DCC_FLAGS 2 0x323a 4 0 4294967295 RATE 0 0 DIV 1 1 MPLL 2 2 RESERVED_15_3 3 15 ixDPCSSYS_CR2_RAWLANE2_DIG_FSM_TX_DCC_STATUS 2 0x323b 2 0 4294967295 FLAG 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR2_RAWLANE2_DIG_FSM_OCLA 2 0x323c 4 0 4294967295 PC_EN 0 0 REG_BANK1_EN 1 1 REG_BANK2_EN 2 2 RESERVED_15_3 3 15 ixDPCSSYS_CR2_RAWLANE2_DIG_FSM_TX_EQ_UPDATE_FLAG 2 0x323d 2 0 4294967295 TX_EQ_UPDATE_FLAG 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR2_RAWLANE2_DIG_FSM_CMNCAL_RCAL_STATUS 2 0x323e 3 0 4294967295 CMNCAL_RCAL_INIT 0 0 CMNCAL_RCAL_DONE 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR2_RAWLANE2_DIG_FSM_RX_IQ_PHASE_OFFSET 2 0x323f 2 0 4294967295 RX_IQ_PHASE_OFFSET 0 3 RESERVED_15_4 4 15 ixDPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_RESET_RTN_REQ 2 0x3240 2 0 4294967295 RESET_RTN_REQ 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_RX_RESET_IRQ 2 0x3241 2 0 4294967295 RX_RESET 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_RX_REQ_IRQ 2 0x3242 2 0 4294967295 RX_REQ 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_RX_RATE_IRQ 2 0x3243 2 0 4294967295 RX_RATE_IRQ 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_RX_PSTATE_IRQ 2 0x3244 2 0 4294967295 RX_PSTATE_IRQ 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ 2 0x3245 2 0 4294967295 RX_ADAPT_REQ_IRQ 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ 2 0x3246 2 0 4294967295 RX_ADAPT_DIS_IRQ 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_RX_RESET_IRQ_CLR 2 0x3247 2 0 4294967295 RX_RESET_IRQ_CLR 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_RX_REQ_IRQ_CLR 2 0x3248 2 0 4294967295 RX_REQ_IRQ_CLR 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_RX_RATE_IRQ_CLR 2 0x3249 2 0 4294967295 RX_RATE_IRQ_CLR 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR 2 0x324a 2 0 4294967295 RX_PSTATE_IRQ_CLR 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR 2 0x324b 2 0 4294967295 RX_ADAPT_REQ_IRQ_CLR 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR 2 0x324c 2 0 4294967295 RX_ADAPT_DIS_IRQ_CLR 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK 2 0x324d 12 0 4294967295 RX_REQ_IRQ_MSK 0 0 RX_RATE_IRQ_MSK 1 1 RX_PSTATE_IRQ_MSK 2 2 RX_ADAPT_REQ_IRQ_MSK 3 3 RX_ADAPT_DIS_IRQ_MSK 4 4 RX_RESET_IRQ_MSK 5 5 LANE_XCVR_MODE_IRQ_MSK 6 6 RX_PH2_CAL_REQ_IRQ_MSK 7 7 RX_PH2_CAL_DIS_IRQ_MSK 8 8 LANE_RX2TX_SER_LB_EN_IRQ_MSK 9 9 DCC_ONDMD_IRQ_MSK 10 10 RESERVED_15_11 11 15 ixDPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK_2 2 0x324e 3 0 4294967295 TX_RESET_IRQ_MSK 0 0 TX_REQ_IRQ_MSK 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ 2 0x324f 2 0 4294967295 LANE_XCVR_MODE_IRQ 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR 2 0x3250 2 0 4294967295 LANE_XCVR_MODE_IRQ_CLR 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ 2 0x3251 2 0 4294967295 RX_PH2_CAL_REQ_IRQ 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ 2 0x3252 2 0 4294967295 RX_PH2_CAL_DIS_IRQ 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR 2 0x3253 2 0 4294967295 RX_PH2_CAL_REQ_IRQ_CLR 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR 2 0x3254 2 0 4294967295 RX_PH2_CAL_DIS_IRQ_CLR 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ 2 0x3255 2 0 4294967295 LANE_RX2TX_SER_LB_EN_IRQ 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR 2 0x3256 2 0 4294967295 LANE_RX2TX_SER_LB_EN_IRQ_CLR 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_DCC_ONDMD_IRQ 2 0x3257 2 0 4294967295 IRQ 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_TX_RESET_IRQ 2 0x3258 2 0 4294967295 TX_RESET 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_TX_REQ_IRQ 2 0x3259 2 0 4294967295 TX_REQ 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_TX_RESET_IRQ_CLR 2 0x325a 2 0 4294967295 TX_RESET_IRQ_CLR 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_TX_REQ_IRQ_CLR 2 0x325b 2 0 4294967295 TX_REQ_IRQ_CLR 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_LANE_OVRD_IN 2 0x3260 4 0 4294967295 LANE_MPLLA_EN_IN 0 0 LANE_MPLLB_EN_IN 1 1 LANE_OVRD_EN 2 2 RESERVED_15_3 3 15 ixDPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_LANE_OVRD_OUT 2 0x3261 4 0 4294967295 LANE_MPLLA_EN_OUT 0 0 LANE_MPLLB_EN_OUT 1 1 LANE_OVRD_EN 2 2 RESERVED_15_3 3 15 ixDPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_SUP_OVRD_IN 2 0x3262 4 0 4294967295 MPLLA_STATE 0 0 MPLLB_STATE 1 1 SUP_STATE_OVRD_EN 2 2 RESERVED_15_3 3 15 ixDPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_SUP_PMA_IN 2 0x3263 3 0 4294967295 MPLLA_STATE 0 0 MPLLB_STATE 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT 2 0x3264 16 0 4294967295 TX_REQ_OVRD_VAL 0 0 TX_REQ_OVRD_EN 1 1 TX_RESET_OVRD_VAL 2 2 TX_RESET_OVRD_EN 3 3 TX_BEACON_EN_OVRD_VAL 4 4 TX_BEACON_EN_OVRD_EN 5 5 TX_ASYNC_DRV_EN_OVRD_VAL 6 6 TX_ASYNC_DRV_EN_OVRD_EN 7 7 TX_ASYNC_EN_OVRD_VAL 8 8 TX_ASYNC_EN_OVRD_EN 9 9 TX_DWORD_CLK_SYNC_OVRD_VAL 10 10 TX_DWORD_CLK_SYNC_OVRD_EN 11 11 LANE_TX2RX_SER_LB_EN_OVRD_VAL 12 12 LANE_TX2RX_SER_LB_EN_OVRD_EN 13 13 TX_PMA_DATA_EN_OVRD_VAL_R 14 14 TX_PMA_DATA_EN_OVRD_EN_R 15 15 ixDPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_TX_PMA_IN 2 0x3265 2 0 4294967295 ACK 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT 2 0x3266 9 0 4294967295 RX_REQ_OVRD_VAL 0 0 RX_REQ_OVRD_EN 1 1 RX_RESET_OVRD_VAL 2 2 RX_RESET_OVRD_EN 3 3 LANE_RX2TX_PAR_LB_EN_OVRD_VAL 4 4 LANE_RX2TX_PAR_LB_EN_OVRD_EN 5 5 RX_PMA_DATA_EN_OVRD_VAL_R 6 6 RX_PMA_DATA_EN_OVRD_EN_R 7 7 RESERVED_15_8 8 15 ixDPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_RX_PMA_IN 2 0x3267 2 0 4294967295 ACK 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_LANE_RTUNE_CTL 2 0x3268 2 0 4294967295 LANE_RTUNE_REQ 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_SUP_PMA_IN_1 2 0x3269 2 0 4294967295 RTUNE_ACK 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_IN 2 0x326a 9 0 4294967295 RX_PMA_PWM_WORD_CLK_R 0 0 RX_PMA_PWM_WORD_CLK_OVRD_EN 1 1 RX_PMA_PWM_DATA_R 2 2 RX_PMA_PWM_DATA_OVRD_EN 3 3 RX_PMA_PWM_CLK_R 4 4 RX_PMA_PWM_CLK_OVRD_EN 5 5 RX_PMA_TERM_CTL_R 6 7 RX_PMA_TERM_CTL_OVRD_EN 8 8 RESERVED_15_9 9 15 ixDPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_OUT 2 0x326b 7 0 4294967295 RX_PMA_PWM_EN 0 0 RX_PMA_PWM_EN_OVRD_EN 1 1 RX_PMA_PWM_CLK_SEL 2 3 RX_PMA_PWM_CLK_SEL_OVRD_EN 4 4 RX_PMA_ASYNC_EN 5 5 RX_PMA_ASYNC_EN_OVRD_EN 6 6 RESERVED_15_7 7 15 ixDPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_RX_ADAPT_OVRD_OUT 2 0x326c 3 0 4294967295 RX_PMA_IQ_PHASE_ADJUST_MAP_OVRD_VAL 0 6 RX_PMA_IQ_PHASE_ADJUST_MAP_OVRD_EN 7 7 RESERVED_15_8 8 15 ixDPCSSYS_CR2_RAWLANE2_DIG_TX_CTL_TX_FSM_CTL 2 0x3280 6 0 4294967295 TX_WAIT_MPLL_OFF_TIME 0 6 TX_P2_ALLOW_RXDET 7 7 TX_P1_ALLOW_RXDET 8 8 TX_P0S_ALLOW_RXDET 9 9 TX_P0_ALLOW_RXDET 10 10 RESERVED_15_11 11 15 ixDPCSSYS_CR2_RAWLANE2_DIG_TX_CTL_TX_CLK_CTL 2 0x3281 4 0 4294967295 TX_CLK_EN 0 0 TX_CLK_SEL 1 4 ASYNC_BEACON_WAIT_TIME 5 10 RESERVED_15_11 11 15 ixDPCSSYS_CR2_RAWLANE2_DIG_TX_CTL_TX_DCC_CONT_STATUS 2 0x3282 2 0 4294967295 ENABLE 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR2_RAWLANE2_DIG_TX_CTL_OCLA 2 0x3283 2 0 4294967295 FSM_EN 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR2_RAWLANE2_DIG_TX_CTL_UPCS_OCLA 2 0x3284 3 0 4294967295 DATA_EN 0 1 CLK_EN 2 2 RESERVED_15_3 3 15 ixDPCSSYS_CR2_RAWLANE2_DIG_RX_CTL_RX_FSM_CTL 2 0x32a0 3 0 4294967295 EN_RX_CTL_FSM 0 0 RATE_CHG_IN_P1 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR2_RAWLANE2_DIG_RX_CTL_RX_LOS_MASK_CTL 2 0x32a1 2 0 4294967295 RX_LOS_MASK_CNT 0 8 RESERVED_15_9 9 15 ixDPCSSYS_CR2_RAWLANE2_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL 2 0x32a2 2 0 4294967295 RX_DATA_EN_OVRD_CNT 0 4 INT_REF_TRCK_CNT 5 15 ixDPCSSYS_CR2_RAWLANE2_DIG_RX_CTL_OFFCAN_CONT_STATUS 2 0x32a3 2 0 4294967295 ENABLE 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR2_RAWLANE2_DIG_RX_CTL_ADAPT_CONT_STATUS 2 0x32a4 2 0 4294967295 ENABLE 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR2_RAWLANE2_DIG_RX_CTL_UPCS_OCLA 2 0x32a5 3 0 4294967295 DATA_EN 0 2 CLK_EN 3 3 RESERVED_15_4 4 15 ixDPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN 2 0x32c0 11 0 4294967295 RATE_OVRD_VAL 0 1 RATE_OVRD_EN 2 2 WIDTH_OVRD_VAL 3 4 WIDTH_OVRD_EN 5 5 PSTATE_OVRD_VAL 6 7 PSTATE_OVRD_EN 8 8 LPD_OVRD_VAL 9 9 LPD_OVRD_EN 10 10 LANE_RX2TX_PAR_LB_EN_OVRD_VAL 11 11 LANE_RX2TX_PAR_LB_EN_OVRD_EN 12 12 RESERVED_15_13 13 15 ixDPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN 2 0x32c1 12 0 4294967295 PSTATE 0 1 LPD 2 2 WIDTH 3 4 RATE 5 7 MPLLB_SEL 8 8 MPLL_EN 9 9 OVRD_EN 10 10 MSTR_MPLLA_STATE 11 11 MSTR_MPLLB_STATE 12 12 MSTR_MPLL_OVRD_EN 13 13 TX_ASYNC_EN_OVR_VAL 14 14 TX_ASYNC_EN_OVR_EN 15 15 ixDPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1 2 0x32c2 13 0 4294967295 DETRX_REQ_OVRD_VAL 0 0 DETRX_REQ_OVRD_EN 1 1 VBOOST_EN_OVRD_VAL 2 2 VBOOST_EN_OVRD_EN 3 3 IBOOST_LVL_OVRD_VAL 4 7 IBOOST_LVL_OVRD_EN 8 8 TX_BEACON_EN_OVR_VAL 9 9 TX_BEACON_EN_OVR_EN 10 10 LANE_TX2RX_SER_LB_EN_OVRD_VAL 11 11 LANE_TX2RX_SER_LB_EN_OVRD_EN 12 12 TX_ASYNC_DATA_OVRD_VAL 13 13 TX_ASYNC_DATA_OVRD_EN 14 14 RESERVED_15_15 15 15 ixDPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_MASTER_MPLL_LOOP 2 0x32c3 3 0 4294967295 MPLLB_LOOP_EN 0 0 MPLLA_LOOP_EN 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1 2 0x32c4 11 0 4294967295 RESERVED 0 1 RX_LOS_LFPS_EN_OVRD_VAL 2 2 RX_LOS_LFPS_EN_OVRD_EN 3 3 RX_LOS_THRSHLD_OVRD_VAL 4 6 RX_LOS_THRSHLD_OVRD_EN 7 7 ADAPT_REQ 8 8 ADAPT_REQ_OVRD_EN 9 9 ADAPT_CONT 10 10 OFFCAN_CONT 11 11 CONT_OVRD_EN 12 12 RESERVED_15_13 13 15 ixDPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_2 2 0x32c5 4 0 4294967295 VCO_LD_VAL_OVRD 0 12 VCO_LD_VAL_OVRD_EN 13 13 VCO_LOWFREQ_VAL_OVRD 14 14 VCO_LOWFREQ_VAL_OVRD_EN 15 15 ixDPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_3 2 0x32c6 3 0 4294967295 REF_LD_VAL_OVRD 0 6 REF_LD_VAL_OVRD_EN 7 7 RESERVED_15_8 8 15 ixDPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT_2 2 0x32c7 3 0 4294967295 RX_VALID 0 0 RX_VALID_OVRD_EN 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_2 2 0x32c8 7 0 4294967295 LANE_TX2RX_SER_LB_EN_OVRD_VAL 0 0 LANE_TX2RX_SER_LB_EN_OVRD_EN 1 1 TX_DATA_EN_OVRD_VAL_R 2 2 TX_DATA_EN_OVRD_EN_R 3 3 TX_ASYNC_DATA_OVRD_VAL_R 4 4 TX_ASYNC_DATA_OVRD_EN_R 5 5 RESERVED_15_6 6 15 ixDPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN 2 0x3300 12 0 4294967295 PSTATE 0 1 LPD 2 2 WIDTH 3 4 RATE 5 7 MPLLB_SEL 8 8 MPLL_EN 9 9 OVRD_EN 10 10 MSTR_MPLLA_STATE 11 11 MSTR_MPLLB_STATE 12 12 MSTR_MPLL_OVRD_EN 13 13 TX_ASYNC_EN_OVR_VAL 14 14 TX_ASYNC_EN_OVR_EN 15 15 ixDPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1 2 0x3301 13 0 4294967295 RESET_OVRD_VAL 0 0 RESET_OVRD_EN 1 1 REQ_OVRD_VAL 2 2 REQ_OVRD_EN 3 3 DETRX_REQ_OVRD_VAL 4 4 DETRX_REQ_OVRD_EN 5 5 VBOOST_EN_OVRD_VAL 6 6 VBOOST_EN_OVRD_EN 7 7 IBOOST_LVL_OVRD_VAL 8 11 IBOOST_LVL_OVRD_EN 12 12 TX_BEACON_EN_OVR_VAL 13 13 TX_BEACON_EN_OVR_EN 14 14 RESERVED_15_15 15 15 ixDPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_PCS_IN 2 0x3302 12 0 4294967295 RESET 0 0 REQ 1 1 PSTATE 2 3 LPD 4 4 WIDTH 5 6 RATE 7 9 MPLLB_SEL 10 10 MPLL_EN 11 11 MSTR_MPLLA_STATE 12 12 MSTR_MPLLB_STATE 13 13 DETRX_REQ 14 14 RESERVED_15_15 15 15 ixDPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_OVRD_OUT 2 0x3303 6 0 4294967295 ACK 0 0 DETRX_RESULT 1 1 EN_CTL 2 2 TX_DWORD_CLK_SYNC_OVRD_VAL 3 3 TX_DWORD_CLK_SYNC_OVRD_EN 4 4 RESERVED_15_5 5 15 ixDPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_PCS_OUT 2 0x3304 2 0 4294967295 ACK 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN 2 0x3305 12 0 4294967295 RATE 0 1 WIDTH 2 3 PSTATE 4 5 LPD 6 6 OVRD_EN 7 7 ADAPT_AFE_EN 8 8 ADAPT_DFE_EN 9 9 LANE_RX2TX_PAR_LB_EN_OVRD_VAL 10 10 LANE_RX2TX_PAR_LB_EN_OVRD_EN 11 11 RX_DATA_EN_OVRD_VAL_R 12 12 RX_DATA_EN_OVRD_EN_R 13 13 RESERVED_15_14 14 15 ixDPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1 2 0x3306 12 0 4294967295 RESET_OVRD_VAL 0 0 RESET_OVRD_EN 1 1 REQ_OVRD_VAL 2 2 REQ_OVRD_EN 3 3 RX_LOS_THRSHLD_OVRD_VAL 4 6 RX_LOS_THRSHLD_OVRD_EN 7 7 ADAPT_REQ 8 8 ADAPT_REQ_OVRD_EN 9 9 ADAPT_CONT 10 10 OFFCAN_CONT 11 11 CONT_OVRD_EN 12 12 RESERVED_15_13 13 15 ixDPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_2 2 0x3307 4 0 4294967295 VCO_LD_VAL_OVRD 0 12 VCO_LD_VAL_OVRD_EN 13 13 VCO_LOWFREQ_VAL_OVRD 14 14 VCO_LOWFREQ_VAL_OVRD_EN 15 15 ixDPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_3 2 0x3308 3 0 4294967295 REF_LD_VAL_OVRD 0 6 REF_LD_VAL_OVRD_EN 7 7 RESERVED_15_8 8 15 ixDPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_PCS_IN 2 0x3309 13 0 4294967295 REQ 0 0 RATE 1 2 WIDTH 3 4 PSTATE 5 6 LPD 7 7 CDR_VCO_LOWFREQ 8 8 ADAPT_AFE_EN 9 9 ADAPT_DFE_EN 10 10 ADAPT_REQ 11 11 ADAPT_CONT 12 12 OFFCAN_CONT 13 13 RESET 14 14 RESERVED_15_15 15 15 ixDPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_1 2 0x330a 2 0 4294967295 REF_LD_VAL 0 6 RESERVED_15_7 7 15 ixDPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_2 2 0x330b 2 0 4294967295 VCO_LD_VAL 0 12 RESERVED_15_13 13 15 ixDPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_3 2 0x330c 4 0 4294967295 EQ_ATT_LVL 0 2 EQ_VGA1_GAIN 3 6 EQ_VGA2_GAIN 7 10 EQ_CTLE_BOOST 11 15 ixDPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_4 2 0x330d 3 0 4294967295 EQ_CTLE_POLE 0 2 EQ_DFE_TAP1 3 10 RESERVED_15_11 11 15 ixDPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT 2 0x330e 3 0 4294967295 ACK 0 0 EN_CTL 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_PCS_OUT 2 0x330f 2 0 4294967295 ACK 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_ADAPT_ACK 2 0x3310 2 0 4294967295 RX_ADAPT_ACK 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_ADAPT_FOM 2 0x3311 2 0 4294967295 RX_ADAPT_FOM 0 7 RESERVED_15_8 8 15 ixDPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_TXPRE_DIR 2 0x3312 2 0 4294967295 RX_TXPRE_DIR 0 1 RESERVED_15_2 2 15 ixDPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_TXMAIN_DIR 2 0x3313 2 0 4294967295 RX_TXMAIN_DIR 0 1 RESERVED_15_2 2 15 ixDPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_TXPOST_DIR 2 0x3314 2 0 4294967295 RX_TXPOST_DIR 0 1 RESERVED_15_2 2 15 ixDPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_LANE_NUMBER 2 0x3315 2 0 4294967295 LANE_NUMBER 0 3 RESERVED_15_4 4 15 ixDPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RESERVED_1 2 0x3316 1 0 4294967295 RESERVED_REG_1 0 15 ixDPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RESERVED_2 2 0x3317 1 0 4294967295 RESERVED_REG_2 0 15 ixDPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN 2 0x3318 16 0 4294967295 RX_RESET_ATE_OVRD_VAL 0 0 RX_RESET_ATE_OVRD_EN 1 1 TX_RESET_ATE_OVRD_VAL 2 2 TX_RESET_ATE_OVRD_EN 3 3 RX_REQ_ATE_OVRD_VAL 4 4 RX_REQ_ATE_OVRD_EN 5 5 TX_REQ_ATE_OVRD_VAL 6 6 TX_REQ_ATE_OVRD_EN 7 7 RX_ADAPT_AFE_EN_OVRD_VAL 8 8 RX_ADAPT_AFE_EN_OVRD_EN 9 9 RX_ADAPT_DFE_EN_OVRD_VAL 10 10 RX_ADAPT_DFE_EN_OVRD_EN 11 11 TX_DATA_EN_ATE_OVRD_VAL 12 12 TX_DATA_EN_ATE_OVRD_EN 13 13 RX_DATA_EN_ATE_OVRD_VAL 14 14 RX_DATA_EN_ATE_OVRD_EN 15 15 ixDPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN 2 0x3319 3 0 4294967295 RX_EQ_DELTA_IQ_OVRD_VAL 0 3 RX_EQ_DELTA_IQ_OVRD_EN 4 4 RESERVED_15_5 5 15 ixDPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN 2 0x331a 5 0 4294967295 RX_TERM_CTRL_OVRD_VAL 0 2 RX_TERM_CTRL_OVRD_EN 3 3 TX_TERM_CTRL_OVRD_VAL 4 6 TX_TERM_CTRL_OVRD_EN 7 7 RESERVED_15_8 8 15 ixDPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TXRX_TERM_CTRL_IN 2 0x331b 3 0 4294967295 RX_TERM_CTRL 0 2 TX_TERM_CTRL 3 5 RESERVED_15_6 6 15 ixDPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT_1 2 0x331c 2 0 4294967295 RX_CLK_EN 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_EQ_OVRD_IN_1 2 0x331d 4 0 4294967295 RX_EQ_AFE_GAIN_OVRD_VAL 0 3 RX_EQ_ATT_LVL_OVRD_VAL 4 6 RX_EQ_OVRD_EN 7 7 RESERVED_15_8 8 15 ixDPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_EQ_OVRD_IN_2 2 0x331e 3 0 4294967295 RX_EQ_DFE_TAP1_OVRD_VAL 0 7 RX_EQ_CTLE_BOOST_OVRD_VAL 8 12 RESERVED_15_13 13 15 ixDPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_PH2_CAL 2 0x331f 4 0 4294967295 PH2_CAL_ACK_VAL 0 0 PH2_CAL_REQ_VAL 1 1 PH2_CAL_REQ_OVRD_VAL 2 2 RESERVED_15_3 3 15 ixDPCSSYS_CR2_RAWLANE3_DIG_FSM_FSM_OVRD_CTL 2 0x3320 5 0 4294967295 FSM_JMP_ADDR 0 11 FSM_JMP_EN 12 12 FSM_CMD_START 13 13 FSM_OVRD_EN 14 14 FSM_BREAK 15 15 ixDPCSSYS_CR2_RAWLANE3_DIG_FSM_MEM_ADDR_MON 2 0x3321 1 0 4294967295 MEM_ADDR 0 15 ixDPCSSYS_CR2_RAWLANE3_DIG_FSM_STATUS_MON 2 0x3322 8 0 4294967295 STATE 0 4 CMD_RDY 5 5 ALU_OVFLW 6 6 ALU_RES_EQ0 7 7 WAIT_CNT_EQ0 8 8 WRMSK_DISABLED 9 9 RDMSK_DISABLED 10 10 RESERVED_15_11 11 15 ixDPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_RX_STARTUP_CAL 2 0x3323 2 0 4294967295 FAST_RX_STARTUP_CAL 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_RX_ADAPT 2 0x3324 2 0 4294967295 FAST_RX_ADAPT 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_RX_AFE_CAL 2 0x3325 2 0 4294967295 FAST_RX_AFE_CAL 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_RX_DFE_CAL 2 0x3326 2 0 4294967295 FAST_RX_DFE_CAL 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_RX_BYPASS_CAL 2 0x3327 2 0 4294967295 FAST_RX_BYPASS_CAL 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_RX_REFLVL_CAL 2 0x3328 2 0 4294967295 FAST_RX_REFLVL_CAL 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_RX_IQ_CAL 2 0x3329 2 0 4294967295 FAST_RX_IQ_CAL 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_RX_AFE_ADAPT 2 0x332a 2 0 4294967295 FAST_RX_AFE_ADAPT 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_RX_DFE_ADAPT 2 0x332b 2 0 4294967295 FAST_RX_DFE_ADAPT 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_SUP 2 0x332c 2 0 4294967295 FAST_SUP 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_TX_CMN_MODE 2 0x332d 2 0 4294967295 FAST_TX_CMN_MODE 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_TX_RXDET 2 0x332e 2 0 4294967295 FAST_TX_RXDET 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_RX_PWRUP 2 0x332f 2 0 4294967295 FAST_RX_PWRUP 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_RX_VCO_WAIT 2 0x3330 2 0 4294967295 FAST_RX_VCO_WAIT 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_RX_VCO_CAL 2 0x3331 2 0 4294967295 FAST_RX_VCO_CAL 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR2_RAWLANE3_DIG_FSM_CMNCAL_MPLL_STATUS 2 0x3332 3 0 4294967295 CMNCAL_MPLL_INIT 0 0 CMNCAL_MPLL_DONE 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_RX_CONT_CAL_ADAPT 2 0x3333 2 0 4294967295 FAST_RX_CONT_CAL_ADAPT 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_RX_CONT_ADAPT 2 0x3334 2 0 4294967295 FAST_RX_CONT_ADAPT 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_RX_CONT_DATA_CAL 2 0x3335 2 0 4294967295 FAST_RX_CONT_DATA_CAL 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_RX_CONT_PHASE_CAL 2 0x3336 2 0 4294967295 FAST_RX_CONT_PHASE_CAL 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_RX_CONT_AFE_CAL 2 0x3337 2 0 4294967295 FAST_RX_CONT_AFE_CAL 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_FLAGS 2 0x3338 12 0 4294967295 TX_FAST_DCC_CAL 0 0 RX_FAST_DCC_CAL 1 1 RX_FAST_VPHUD_CAL 2 2 RX_FAST_VREF_CAL 3 3 RX_FAST_SIGDET_CAL 4 4 RESERVED_2 5 7 TX_FAST_CONT_DCC_CAL 8 8 RX_FAST_CONT_DCC_CAL 9 9 RX_FAST_CONT_VPHUD_CAL 10 10 RX_FAST_CONT_VREF_CAL 11 11 RESERVED_1 12 14 TX_SKIP_SUP_CAL 15 15 ixDPCSSYS_CR2_RAWLANE3_DIG_FSM_CR_LOCK 2 0x3339 3 0 4294967295 CR_REG_LOCK 0 0 CR_MEM_LOCK 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR2_RAWLANE3_DIG_FSM_TX_DCC_FLAGS 2 0x333a 4 0 4294967295 RATE 0 0 DIV 1 1 MPLL 2 2 RESERVED_15_3 3 15 ixDPCSSYS_CR2_RAWLANE3_DIG_FSM_TX_DCC_STATUS 2 0x333b 2 0 4294967295 FLAG 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR2_RAWLANE3_DIG_FSM_OCLA 2 0x333c 4 0 4294967295 PC_EN 0 0 REG_BANK1_EN 1 1 REG_BANK2_EN 2 2 RESERVED_15_3 3 15 ixDPCSSYS_CR2_RAWLANE3_DIG_FSM_TX_EQ_UPDATE_FLAG 2 0x333d 2 0 4294967295 TX_EQ_UPDATE_FLAG 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR2_RAWLANE3_DIG_FSM_CMNCAL_RCAL_STATUS 2 0x333e 3 0 4294967295 CMNCAL_RCAL_INIT 0 0 CMNCAL_RCAL_DONE 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR2_RAWLANE3_DIG_FSM_RX_IQ_PHASE_OFFSET 2 0x333f 2 0 4294967295 RX_IQ_PHASE_OFFSET 0 3 RESERVED_15_4 4 15 ixDPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_RESET_RTN_REQ 2 0x3340 2 0 4294967295 RESET_RTN_REQ 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_RX_RESET_IRQ 2 0x3341 2 0 4294967295 RX_RESET 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_RX_REQ_IRQ 2 0x3342 2 0 4294967295 RX_REQ 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_RX_RATE_IRQ 2 0x3343 2 0 4294967295 RX_RATE_IRQ 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_RX_PSTATE_IRQ 2 0x3344 2 0 4294967295 RX_PSTATE_IRQ 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ 2 0x3345 2 0 4294967295 RX_ADAPT_REQ_IRQ 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ 2 0x3346 2 0 4294967295 RX_ADAPT_DIS_IRQ 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_RX_RESET_IRQ_CLR 2 0x3347 2 0 4294967295 RX_RESET_IRQ_CLR 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_RX_REQ_IRQ_CLR 2 0x3348 2 0 4294967295 RX_REQ_IRQ_CLR 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_RX_RATE_IRQ_CLR 2 0x3349 2 0 4294967295 RX_RATE_IRQ_CLR 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR 2 0x334a 2 0 4294967295 RX_PSTATE_IRQ_CLR 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR 2 0x334b 2 0 4294967295 RX_ADAPT_REQ_IRQ_CLR 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR 2 0x334c 2 0 4294967295 RX_ADAPT_DIS_IRQ_CLR 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK 2 0x334d 12 0 4294967295 RX_REQ_IRQ_MSK 0 0 RX_RATE_IRQ_MSK 1 1 RX_PSTATE_IRQ_MSK 2 2 RX_ADAPT_REQ_IRQ_MSK 3 3 RX_ADAPT_DIS_IRQ_MSK 4 4 RX_RESET_IRQ_MSK 5 5 LANE_XCVR_MODE_IRQ_MSK 6 6 RX_PH2_CAL_REQ_IRQ_MSK 7 7 RX_PH2_CAL_DIS_IRQ_MSK 8 8 LANE_RX2TX_SER_LB_EN_IRQ_MSK 9 9 DCC_ONDMD_IRQ_MSK 10 10 RESERVED_15_11 11 15 ixDPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK_2 2 0x334e 3 0 4294967295 TX_RESET_IRQ_MSK 0 0 TX_REQ_IRQ_MSK 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ 2 0x334f 2 0 4294967295 LANE_XCVR_MODE_IRQ 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR 2 0x3350 2 0 4294967295 LANE_XCVR_MODE_IRQ_CLR 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ 2 0x3351 2 0 4294967295 RX_PH2_CAL_REQ_IRQ 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ 2 0x3352 2 0 4294967295 RX_PH2_CAL_DIS_IRQ 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR 2 0x3353 2 0 4294967295 RX_PH2_CAL_REQ_IRQ_CLR 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR 2 0x3354 2 0 4294967295 RX_PH2_CAL_DIS_IRQ_CLR 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ 2 0x3355 2 0 4294967295 LANE_RX2TX_SER_LB_EN_IRQ 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR 2 0x3356 2 0 4294967295 LANE_RX2TX_SER_LB_EN_IRQ_CLR 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_DCC_ONDMD_IRQ 2 0x3357 2 0 4294967295 IRQ 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_TX_RESET_IRQ 2 0x3358 2 0 4294967295 TX_RESET 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_TX_REQ_IRQ 2 0x3359 2 0 4294967295 TX_REQ 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_TX_RESET_IRQ_CLR 2 0x335a 2 0 4294967295 TX_RESET_IRQ_CLR 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_TX_REQ_IRQ_CLR 2 0x335b 2 0 4294967295 TX_REQ_IRQ_CLR 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_LANE_OVRD_IN 2 0x3360 4 0 4294967295 LANE_MPLLA_EN_IN 0 0 LANE_MPLLB_EN_IN 1 1 LANE_OVRD_EN 2 2 RESERVED_15_3 3 15 ixDPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_LANE_OVRD_OUT 2 0x3361 4 0 4294967295 LANE_MPLLA_EN_OUT 0 0 LANE_MPLLB_EN_OUT 1 1 LANE_OVRD_EN 2 2 RESERVED_15_3 3 15 ixDPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_SUP_OVRD_IN 2 0x3362 4 0 4294967295 MPLLA_STATE 0 0 MPLLB_STATE 1 1 SUP_STATE_OVRD_EN 2 2 RESERVED_15_3 3 15 ixDPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_SUP_PMA_IN 2 0x3363 3 0 4294967295 MPLLA_STATE 0 0 MPLLB_STATE 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT 2 0x3364 16 0 4294967295 TX_REQ_OVRD_VAL 0 0 TX_REQ_OVRD_EN 1 1 TX_RESET_OVRD_VAL 2 2 TX_RESET_OVRD_EN 3 3 TX_BEACON_EN_OVRD_VAL 4 4 TX_BEACON_EN_OVRD_EN 5 5 TX_ASYNC_DRV_EN_OVRD_VAL 6 6 TX_ASYNC_DRV_EN_OVRD_EN 7 7 TX_ASYNC_EN_OVRD_VAL 8 8 TX_ASYNC_EN_OVRD_EN 9 9 TX_DWORD_CLK_SYNC_OVRD_VAL 10 10 TX_DWORD_CLK_SYNC_OVRD_EN 11 11 LANE_TX2RX_SER_LB_EN_OVRD_VAL 12 12 LANE_TX2RX_SER_LB_EN_OVRD_EN 13 13 TX_PMA_DATA_EN_OVRD_VAL_R 14 14 TX_PMA_DATA_EN_OVRD_EN_R 15 15 ixDPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_TX_PMA_IN 2 0x3365 2 0 4294967295 ACK 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT 2 0x3366 9 0 4294967295 RX_REQ_OVRD_VAL 0 0 RX_REQ_OVRD_EN 1 1 RX_RESET_OVRD_VAL 2 2 RX_RESET_OVRD_EN 3 3 LANE_RX2TX_PAR_LB_EN_OVRD_VAL 4 4 LANE_RX2TX_PAR_LB_EN_OVRD_EN 5 5 RX_PMA_DATA_EN_OVRD_VAL_R 6 6 RX_PMA_DATA_EN_OVRD_EN_R 7 7 RESERVED_15_8 8 15 ixDPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_RX_PMA_IN 2 0x3367 2 0 4294967295 ACK 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_LANE_RTUNE_CTL 2 0x3368 2 0 4294967295 LANE_RTUNE_REQ 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_SUP_PMA_IN_1 2 0x3369 2 0 4294967295 RTUNE_ACK 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_IN 2 0x336a 9 0 4294967295 RX_PMA_PWM_WORD_CLK_R 0 0 RX_PMA_PWM_WORD_CLK_OVRD_EN 1 1 RX_PMA_PWM_DATA_R 2 2 RX_PMA_PWM_DATA_OVRD_EN 3 3 RX_PMA_PWM_CLK_R 4 4 RX_PMA_PWM_CLK_OVRD_EN 5 5 RX_PMA_TERM_CTL_R 6 7 RX_PMA_TERM_CTL_OVRD_EN 8 8 RESERVED_15_9 9 15 ixDPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_OUT 2 0x336b 7 0 4294967295 RX_PMA_PWM_EN 0 0 RX_PMA_PWM_EN_OVRD_EN 1 1 RX_PMA_PWM_CLK_SEL 2 3 RX_PMA_PWM_CLK_SEL_OVRD_EN 4 4 RX_PMA_ASYNC_EN 5 5 RX_PMA_ASYNC_EN_OVRD_EN 6 6 RESERVED_15_7 7 15 ixDPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_RX_ADAPT_OVRD_OUT 2 0x336c 3 0 4294967295 RX_PMA_IQ_PHASE_ADJUST_MAP_OVRD_VAL 0 6 RX_PMA_IQ_PHASE_ADJUST_MAP_OVRD_EN 7 7 RESERVED_15_8 8 15 ixDPCSSYS_CR2_RAWLANE3_DIG_TX_CTL_TX_FSM_CTL 2 0x3380 6 0 4294967295 TX_WAIT_MPLL_OFF_TIME 0 6 TX_P2_ALLOW_RXDET 7 7 TX_P1_ALLOW_RXDET 8 8 TX_P0S_ALLOW_RXDET 9 9 TX_P0_ALLOW_RXDET 10 10 RESERVED_15_11 11 15 ixDPCSSYS_CR2_RAWLANE3_DIG_TX_CTL_TX_CLK_CTL 2 0x3381 4 0 4294967295 TX_CLK_EN 0 0 TX_CLK_SEL 1 4 ASYNC_BEACON_WAIT_TIME 5 10 RESERVED_15_11 11 15 ixDPCSSYS_CR2_RAWLANE3_DIG_TX_CTL_TX_DCC_CONT_STATUS 2 0x3382 2 0 4294967295 ENABLE 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR2_RAWLANE3_DIG_TX_CTL_OCLA 2 0x3383 2 0 4294967295 FSM_EN 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR2_RAWLANE3_DIG_TX_CTL_UPCS_OCLA 2 0x3384 3 0 4294967295 DATA_EN 0 1 CLK_EN 2 2 RESERVED_15_3 3 15 ixDPCSSYS_CR2_RAWLANE3_DIG_RX_CTL_RX_FSM_CTL 2 0x33a0 3 0 4294967295 EN_RX_CTL_FSM 0 0 RATE_CHG_IN_P1 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR2_RAWLANE3_DIG_RX_CTL_RX_LOS_MASK_CTL 2 0x33a1 2 0 4294967295 RX_LOS_MASK_CNT 0 8 RESERVED_15_9 9 15 ixDPCSSYS_CR2_RAWLANE3_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL 2 0x33a2 2 0 4294967295 RX_DATA_EN_OVRD_CNT 0 4 INT_REF_TRCK_CNT 5 15 ixDPCSSYS_CR2_RAWLANE3_DIG_RX_CTL_OFFCAN_CONT_STATUS 2 0x33a3 2 0 4294967295 ENABLE 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR2_RAWLANE3_DIG_RX_CTL_ADAPT_CONT_STATUS 2 0x33a4 2 0 4294967295 ENABLE 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR2_RAWLANE3_DIG_RX_CTL_UPCS_OCLA 2 0x33a5 3 0 4294967295 DATA_EN 0 2 CLK_EN 3 3 RESERVED_15_4 4 15 ixDPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN 2 0x33c0 11 0 4294967295 RATE_OVRD_VAL 0 1 RATE_OVRD_EN 2 2 WIDTH_OVRD_VAL 3 4 WIDTH_OVRD_EN 5 5 PSTATE_OVRD_VAL 6 7 PSTATE_OVRD_EN 8 8 LPD_OVRD_VAL 9 9 LPD_OVRD_EN 10 10 LANE_RX2TX_PAR_LB_EN_OVRD_VAL 11 11 LANE_RX2TX_PAR_LB_EN_OVRD_EN 12 12 RESERVED_15_13 13 15 ixDPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN 2 0x33c1 12 0 4294967295 PSTATE 0 1 LPD 2 2 WIDTH 3 4 RATE 5 7 MPLLB_SEL 8 8 MPLL_EN 9 9 OVRD_EN 10 10 MSTR_MPLLA_STATE 11 11 MSTR_MPLLB_STATE 12 12 MSTR_MPLL_OVRD_EN 13 13 TX_ASYNC_EN_OVR_VAL 14 14 TX_ASYNC_EN_OVR_EN 15 15 ixDPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1 2 0x33c2 13 0 4294967295 DETRX_REQ_OVRD_VAL 0 0 DETRX_REQ_OVRD_EN 1 1 VBOOST_EN_OVRD_VAL 2 2 VBOOST_EN_OVRD_EN 3 3 IBOOST_LVL_OVRD_VAL 4 7 IBOOST_LVL_OVRD_EN 8 8 TX_BEACON_EN_OVR_VAL 9 9 TX_BEACON_EN_OVR_EN 10 10 LANE_TX2RX_SER_LB_EN_OVRD_VAL 11 11 LANE_TX2RX_SER_LB_EN_OVRD_EN 12 12 TX_ASYNC_DATA_OVRD_VAL 13 13 TX_ASYNC_DATA_OVRD_EN 14 14 RESERVED_15_15 15 15 ixDPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_MASTER_MPLL_LOOP 2 0x33c3 3 0 4294967295 MPLLB_LOOP_EN 0 0 MPLLA_LOOP_EN 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1 2 0x33c4 11 0 4294967295 RESERVED 0 1 RX_LOS_LFPS_EN_OVRD_VAL 2 2 RX_LOS_LFPS_EN_OVRD_EN 3 3 RX_LOS_THRSHLD_OVRD_VAL 4 6 RX_LOS_THRSHLD_OVRD_EN 7 7 ADAPT_REQ 8 8 ADAPT_REQ_OVRD_EN 9 9 ADAPT_CONT 10 10 OFFCAN_CONT 11 11 CONT_OVRD_EN 12 12 RESERVED_15_13 13 15 ixDPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_2 2 0x33c5 4 0 4294967295 VCO_LD_VAL_OVRD 0 12 VCO_LD_VAL_OVRD_EN 13 13 VCO_LOWFREQ_VAL_OVRD 14 14 VCO_LOWFREQ_VAL_OVRD_EN 15 15 ixDPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_3 2 0x33c6 3 0 4294967295 REF_LD_VAL_OVRD 0 6 REF_LD_VAL_OVRD_EN 7 7 RESERVED_15_8 8 15 ixDPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT_2 2 0x33c7 3 0 4294967295 RX_VALID 0 0 RX_VALID_OVRD_EN 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_2 2 0x33c8 7 0 4294967295 LANE_TX2RX_SER_LB_EN_OVRD_VAL 0 0 LANE_TX2RX_SER_LB_EN_OVRD_EN 1 1 TX_DATA_EN_OVRD_VAL_R 2 2 TX_DATA_EN_OVRD_EN_R 3 3 TX_ASYNC_DATA_OVRD_VAL_R 4 4 TX_ASYNC_DATA_OVRD_EN_R 5 5 RESERVED_15_6 6 15 ixDPCSSYS_CR2_RAWAONLANE0_DIG_AFE_ATT_IDAC_OFST 2 0x4000 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR2_RAWAONLANE0_DIG_AFE_CTLE_IDAC_OFST 2 0x4001 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR2_RAWAONLANE0_DIG_RX_ADPT_IQ 2 0x4002 2 0 4294967295 IQ_ADPT_VAL 0 6 RESERVED_15_7 7 15 ixDPCSSYS_CR2_RAWAONLANE0_DIG_RX_ADAPT_FOM 2 0x4003 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR2_RAWAONLANE0_DIG_DFE_SUMMER_ODD_IDAC_OFST 2 0x4004 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR2_RAWAONLANE0_DIG_DFE_PHASE_EVEN_VDAC_OFST 2 0x4005 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR2_RAWAONLANE0_DIG_DFE_PHASE_ODD_VDAC_OFST 2 0x4006 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR2_RAWAONLANE0_DIG_DFE_EVEN_REF_LVL 2 0x4007 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR2_RAWAONLANE0_DIG_DFE_ODD_REF_LVL 2 0x4008 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR2_RAWAONLANE0_DIG_RX_PHSADJ_LIN 2 0x4009 2 0 4294967295 DATA 0 0 RESERVED_15_5 5 15 ixDPCSSYS_CR2_RAWAONLANE0_DIG_RX_PHSADJ_MAP 2 0x400a 2 0 4294967295 DATA 0 0 RESERVED_15_5 5 15 ixDPCSSYS_CR2_RAWAONLANE0_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST 2 0x400b 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR2_RAWAONLANE0_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST 2 0x400c 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR2_RAWAONLANE0_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST 2 0x400d 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR2_RAWAONLANE0_DIG_DFE_DATA_ODD_LOW_VDAC_OFST 2 0x400e 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR2_RAWAONLANE0_DIG_DFE_BYPASS_EVEN_VDAC_OFST 2 0x400f 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR2_RAWAONLANE0_DIG_DFE_BYPASS_ODD_VDAC_OFST 2 0x4010 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR2_RAWAONLANE0_DIG_DFE_ERROR_EVEN_VDAC_OFST 2 0x4011 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR2_RAWAONLANE0_DIG_DFE_ERROR_ODD_VDAC_OFST 2 0x4012 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR2_RAWAONLANE0_DIG_RX_IQ_PHASE_ADJUST 2 0x4013 2 0 4294967295 DATA 0 0 RESERVED_15_7 7 15 ixDPCSSYS_CR2_RAWAONLANE0_DIG_MPLLA_COARSE_TUNE 2 0x4014 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR2_RAWAONLANE0_DIG_MPLLB_COARSE_TUNE 2 0x4015 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR2_RAWAONLANE0_DIG_INIT_PWRUP_DONE 2 0x4016 3 0 4294967295 DATA 0 0 PH2_PWRUP_DONE 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR2_RAWAONLANE0_DIG_RX_ADPT_ATT 2 0x4017 2 0 4294967295 ATT_ADPT_VAL 0 7 RESERVED_15_8 8 15 ixDPCSSYS_CR2_RAWAONLANE0_DIG_RX_ADPT_VGA 2 0x4018 2 0 4294967295 VGA_ADPT_VAL 0 9 RESERVED_15_10 10 15 ixDPCSSYS_CR2_RAWAONLANE0_DIG_RX_ADPT_CTLE 2 0x4019 3 0 4294967295 CTLE_BOOST_ADPT_VAL 0 9 CTLE_POLE_ADPT_VAL 10 12 RESERVED_15_13 13 15 ixDPCSSYS_CR2_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP1 2 0x401a 2 0 4294967295 DFE_TAP1_ADPT_VAL 0 12 RESERVED_15_13 13 15 ixDPCSSYS_CR2_RAWAONLANE0_DIG_RX_ADAPT_DONE 2 0x401b 2 0 4294967295 DATA 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR2_RAWAONLANE0_DIG_FAST_FLAGS 2 0x401c 16 0 4294967295 FAST_RX_STARTUP_CAL 0 0 FAST_RX_ADAPT 1 1 FAST_RX_AFE_CAL 2 2 FAST_RX_DFE_CAL 3 3 FAST_RX_BYPASS_CAL 4 4 FAST_RX_REFLVL_CAL 5 5 FAST_RX_IQ_CAL 6 6 FAST_RX_AFE_ADAPT 7 7 FAST_RX_DFE_ADAPT 8 8 FAST_SUP 9 9 FAST_TX_CMN_MODE 10 10 FAST_TX_RXDET 11 11 FAST_RX_PWRUP 12 12 FAST_RX_VCO_WAIT 13 13 FAST_RX_VCO_CAL 14 14 RESERVED_15_15 15 15 ixDPCSSYS_CR2_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP2 2 0x401d 2 0 4294967295 DFE_TAP2_ADPT_VAL 0 11 RESERVED_15_12 12 15 ixDPCSSYS_CR2_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP3 2 0x401e 2 0 4294967295 DFE_TAP3_ADPT_VAL 0 11 RESERVED_15_12 12 15 ixDPCSSYS_CR2_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP4 2 0x401f 2 0 4294967295 DFE_TAP4_ADPT_VAL 0 11 RESERVED_15_12 12 15 ixDPCSSYS_CR2_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP5 2 0x4020 2 0 4294967295 DFE_TAP5_ADPT_VAL 0 11 RESERVED_15_12 12 15 ixDPCSSYS_CR2_RAWAONLANE0_DIG_RX_SLICER_CTRL_EVEN 2 0x4021 2 0 4294967295 RX_ANA_SLICER_CTRL_E 0 3 RESERVED_15_4 4 15 ixDPCSSYS_CR2_RAWAONLANE0_DIG_RX_SLICER_CTRL_ODD 2 0x4022 2 0 4294967295 RX_ANA_SLICER_CTRL_O 0 3 RESERVED_15_4 4 15 ixDPCSSYS_CR2_RAWAONLANE0_DIG_LANE_CMNCAL_MPLL_STATUS 2 0x4023 3 0 4294967295 LANE_CMNCAL_MPLL_INIT 0 0 LANE_CMNCAL_MPLL_DONE 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR2_RAWAONLANE0_DIG_ADPT_CTL_0 2 0x4024 1 0 4294967295 VAL 0 15 ixDPCSSYS_CR2_RAWAONLANE0_DIG_ADPT_CTL_1 2 0x4025 1 0 4294967295 VAL 0 15 ixDPCSSYS_CR2_RAWAONLANE0_DIG_ADPT_CTL_2 2 0x4026 1 0 4294967295 VAL 0 15 ixDPCSSYS_CR2_RAWAONLANE0_DIG_ADPT_CTL_3 2 0x4027 1 0 4294967295 VAL 0 15 ixDPCSSYS_CR2_RAWAONLANE0_DIG_ADPT_CTL_4 2 0x4028 1 0 4294967295 VAL 0 15 ixDPCSSYS_CR2_RAWAONLANE0_DIG_ADPT_CTL_5 2 0x4029 1 0 4294967295 VAL 0 15 ixDPCSSYS_CR2_RAWAONLANE0_DIG_ADPT_CTL_6 2 0x402a 1 0 4294967295 VAL 0 15 ixDPCSSYS_CR2_RAWAONLANE0_DIG_ADPT_CTL_7 2 0x402b 1 0 4294967295 VAL 0 15 ixDPCSSYS_CR2_RAWAONLANE0_DIG_MPLL_DISABLE 2 0x402c 3 0 4294967295 LANE_MPLLA_DISABLE 0 0 LANE_MPLLB_DISABLE 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR2_RAWAONLANE0_DIG_FAST_FLAGS_2 2 0x402d 16 0 4294967295 FAST_RX_CONT_CAL_ADAPT 0 0 FAST_RX_CONT_ADAPT 1 1 FAST_RX_CONT_DATA_CAL 2 2 FAST_RX_CONT_PHASE_CAL 3 3 FAST_RX_CONT_AFE_CAL 4 4 FAST_TX_CONT_DCC_CAL 5 5 FAST_RX_CONT_DCC_CAL 6 6 FAST_RX_CONT_VPHUD_CAL 7 7 FAST_RX_CONT_VREF_CAL 8 8 FAST_TX_DCC_CAL 9 9 FAST_RX_DCC_CAL 10 10 FAST_RX_VPHUD_CAL 11 11 FAST_RX_VREF_CAL 12 12 SKIP_TX_RTUNE_CAL 13 13 FAST_RX_SIGDET_CAL 14 14 RESERVED_15_15 15 15 ixDPCSSYS_CR2_RAWAONLANE0_DIG_LANE_CMNCAL_RCAL_STATUS 2 0x402e 3 0 4294967295 LANE_CMNCAL_RCAL_INIT 0 0 LANE_CMNCAL_RCAL_DONE 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR2_RAWAONLANE0_DIG_TXRX_OVRD_IN 2 0x402f 5 0 4294967295 RX_DISABLE_OVRD_VAL 0 0 RX_DISABLE_OVRD_EN 1 1 TX_DISABLE_OVRD_VAL 2 2 TX_DISABLE_OVRD_EN 3 3 RESERVED_15_4 4 15 ixDPCSSYS_CR2_RAWAONLANE0_DIG_RX_LOS_MASK_CTL 2 0x4030 2 0 4294967295 RX_LOS_MASK_CNT 0 8 RESERVED_15_9 9 15 ixDPCSSYS_CR2_RAWAONLANE0_DIG_RX_SIGDET_FILT_CTRL 2 0x4031 5 0 4294967295 ISOLATE_SIGDET_HF 0 0 RX_SIGDEF_HF_FILT_OVR_DIS 1 1 RX_SIGDEF_HF_FILT_OVR 2 2 RX_SIGDET_LF_OUT_FILT_EN 3 3 RESERVED_15_4 4 15 ixDPCSSYS_CR2_RAWAONLANE0_DIG_STATS 2 0x4032 3 0 4294967295 RX_VREFGEN_MASTER 0 0 RX_PMA_SQ_OUT 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR2_RAWAONLANE0_DIG_RX_OVRD_OUT_1 2 0x4033 11 0 4294967295 RX_PMA_SQ_CTRL_TRESH_OVRD_VAL 0 2 RX_PMA_SQ_CTRL_TRESH_OVRD_EN 3 3 RX_PMA_SQ_CTRL_RESP_OVRD_VAL 4 5 RX_PMA_SQ_CTRL_RESP_OVRD_EN 6 6 RX_PMA_SQ_WEAKKEEP_OVRD_VAL 7 7 RX_PMA_SQ_WEAKKEEP_OVRD_EN 8 8 RX_PMA_SQ_INV_POLARITY_OVRD_VAL 9 9 RX_PMA_SQ_INV_POLARITY_OVRD_EN 10 10 RX_PMA_SQ_EN_OVRD_VAL 11 11 RX_PMA_SQ_EN_OVRD_EN 12 12 RESERVED_15_13 13 15 ixDPCSSYS_CR2_RAWAONLANE0_DIG_RX_OVRD_OUT_2 2 0x4034 9 0 4294967295 RX_PMA_VREFGEN_EN_OVRD_VAL 0 0 RX_PMA_VREFGEN_EN_OVRD_EN 1 1 RX_SQ_OUT_OVRD_VAL 2 2 RX_SQ_OUT_OVRD_EN 3 3 RX_PMA_TERM_ACDC_OVRD_VAL 4 4 RX_PMA_TERM_ACDC_OVRD_EN 5 5 RX_PMA_TERM_EN_OVRD_VAL 6 6 RX_PMA_TERM_EN_OVRD_EN 7 7 RESERVED_15_8 8 15 ixDPCSSYS_CR2_RAWAONLANE0_DIG_RX_OVRD_OUT_3 2 0x4035 7 0 4294967295 RX_PMA_SIGDET_LF_FILTER_EN_OVRD_VAL 0 0 RX_PMA_SIGDET_LF_FILTER_EN_OVRD_EN 1 1 RX_PMA_SIGDET_LF_EN_OVRD_VAL 2 2 RX_PMA_SIGDET_LF_EN_OVRD_EN 3 3 RX_PMA_SIGDET_HF_EN_OVRD_VAL 4 4 RX_PMA_SIGDET_HF_EN_OVRD_EN 5 5 RESERVED_15_6 6 15 ixDPCSSYS_CR2_RAWAONLANE0_DIG_RX_SIGDET_CAL 2 0x4036 4 0 4294967295 RX_PMA_SIGDET_LF_THRESHOLD 0 2 RX_PMA_SIGDET_HF_THRESHOLD 3 5 RX_PMA_SIGDET_CAL_EN 6 6 RESERVED_15_7 7 15 ixDPCSSYS_CR2_RAWAONLANE0_DIG_RX_SIGDET_HF_CODE 2 0x4037 2 0 4294967295 RX_PMA_SIGDET_HF_CAL_TUNE 0 5 RESERVED_15_6 6 15 ixDPCSSYS_CR2_RAWAONLANE0_DIG_RX_SIGDET_LF_CODE 2 0x4038 2 0 4294967295 RX_PMA_SIGDET_LF_CAL_TUNE 0 5 RESERVED_15_6 6 15 ixDPCSSYS_CR2_RAWAONLANE0_DIG_RX_VREFGEN_EN 2 0x4039 2 0 4294967295 PULL_UP 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR2_RAWAONLANE0_DIG_CAL_IOFF_CODE 2 0x403a 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR2_RAWAONLANE0_DIG_CAL_ICONST_CODE 2 0x403b 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR2_RAWAONLANE0_DIG_CAL_VREFGEN_CODE 2 0x403c 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR2_RAWAONLANE0_DIG_RX_DCC_CAL_ICM_CODE_0 2 0x403d 2 0 4294967295 RX_DCC_CAL_ICM_CODE 0 9 RESERVED_15_10 10 15 ixDPCSSYS_CR2_RAWAONLANE0_DIG_RX_DCC_CAL_IDF_CODE_0 2 0x403e 2 0 4294967295 RX_DCC_CAL_IDF_CODE 0 9 RESERVED_15_10 10 15 ixDPCSSYS_CR2_RAWAONLANE0_DIG_RX_DCC_CAL_QCM_CODE_0 2 0x403f 2 0 4294967295 RX_DCC_CAL_QCM_CODE 0 9 RESERVED_15_10 10 15 ixDPCSSYS_CR2_RAWAONLANE0_DIG_RX_DCC_CAL_QDF_CODE_0 2 0x4040 2 0 4294967295 RX_DCC_CAL_QDF_CODE 0 9 RESERVED_15_10 10 15 ixDPCSSYS_CR2_RAWAONLANE0_DIG_RX_DCC_CAL_ICM_CODE_1 2 0x4041 2 0 4294967295 RX_DCC_CAL_ICM_CODE 0 9 RESERVED_15_10 10 15 ixDPCSSYS_CR2_RAWAONLANE0_DIG_RX_DCC_CAL_IDF_CODE_1 2 0x4042 2 0 4294967295 RX_DCC_CAL_IDF_CODE 0 9 RESERVED_15_10 10 15 ixDPCSSYS_CR2_RAWAONLANE0_DIG_RX_DCC_CAL_QCM_CODE_1 2 0x4043 2 0 4294967295 RX_DCC_CAL_QCM_CODE 0 9 RESERVED_15_10 10 15 ixDPCSSYS_CR2_RAWAONLANE0_DIG_RX_DCC_CAL_QDF_CODE_1 2 0x4044 2 0 4294967295 RX_DCC_CAL_QDF_CODE 0 9 RESERVED_15_10 10 15 ixDPCSSYS_CR2_RAWAONLANE0_DIG_TX_DCC_BANK_ADDR 2 0x4045 1 0 4294967295 ADDR 0 15 ixDPCSSYS_CR2_RAWAONLANE0_DIG_TX_DCC_BANK_DATA 2 0x4046 1 0 4294967295 DATA 0 15 ixDPCSSYS_CR2_RAWAONLANE0_DIG_TX_DCC_CONT 2 0x4047 2 0 4294967295 EN 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR2_RAWAONLANE0_DIG_MPLL_BG_CTL 2 0x4048 3 0 4294967295 MPLL_STATE_WAIT 0 0 MPLL_STATE_DLY_EN 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR2_RAWAONLANE0_DIG_SIGDET_OUT_OVRD 2 0x4049 5 0 4294967295 RX_SIGDET_HF_OUT_OVRD_VAL 0 0 RX_SIGDET_HF_OUT_OVRD_EN 1 1 RX_SIGDET_LF_OUT_OVRD_VAL 2 2 RX_SIGDET_LF_OUT_OVRD_EN 3 3 RESERVED_15_4 4 15 ixDPCSSYS_CR2_RAWAONLANE0_DIG_SIGDET_OUT_IN 2 0x404a 3 0 4294967295 RX_SIGDET_HF_OUT_OVRD_VAL 0 0 RX_SIGDET_LF_OUT_OVRD_VAL 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR2_RAWAONLANE0_DIG_FW_MM_CONFIG 2 0x404b 1 0 4294967295 DATA 0 0 ixDPCSSYS_CR2_RAWAONLANE0_DIG_FW_ADPT_CONFIG 2 0x404c 2 0 4294967295 REF_LVL_ADPT 0 7 FW_CONFIG 8 15 ixDPCSSYS_CR2_RAWAONLANE0_DIG_FW_CALIB_CONFIG 2 0x404d 1 0 4294967295 FW_CALIB 0 15 ixDPCSSYS_CR2_RAWAONLANE0_DIG_LANE_XCVR_MODE_OVRD_IN 2 0x404e 3 0 4294967295 LANE_XCVR_MODE_OVRD_VAL 0 1 LANE_XCVR_MODE_OVRD_EN 2 2 RESERVED_15_3 3 15 ixDPCSSYS_CR2_RAWAONLANE0_DIG_LANE_XCVR_MODE_IN 2 0x404f 2 0 4294967295 LANE_XCVR_MODE 0 1 RESERVED_15_2 2 15 ixDPCSSYS_CR2_RAWAONLANE0_DIG_RX_SIGDET_CONFIG 2 0x4050 4 0 4294967295 RX_SIGDET_HF_FILTER_COUNTER 0 4 RX_SIGDET_LF_FILTER_COUNTER 5 9 RX_SIGDET_LF_HOLD 10 10 RESERVED_15_11 11 15 ixDPCSSYS_CR2_RAWAONLANE0_DIG_TX_DCC_CONFIG 2 0x4051 1 0 4294967295 DATA 0 0 ixDPCSSYS_CR2_RAWAONLANE1_DIG_AFE_ATT_IDAC_OFST 2 0x4100 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR2_RAWAONLANE1_DIG_AFE_CTLE_IDAC_OFST 2 0x4101 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR2_RAWAONLANE1_DIG_RX_ADPT_IQ 2 0x4102 2 0 4294967295 IQ_ADPT_VAL 0 6 RESERVED_15_7 7 15 ixDPCSSYS_CR2_RAWAONLANE1_DIG_RX_ADAPT_FOM 2 0x4103 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR2_RAWAONLANE1_DIG_DFE_SUMMER_ODD_IDAC_OFST 2 0x4104 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR2_RAWAONLANE1_DIG_DFE_PHASE_EVEN_VDAC_OFST 2 0x4105 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR2_RAWAONLANE1_DIG_DFE_PHASE_ODD_VDAC_OFST 2 0x4106 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR2_RAWAONLANE1_DIG_DFE_EVEN_REF_LVL 2 0x4107 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR2_RAWAONLANE1_DIG_DFE_ODD_REF_LVL 2 0x4108 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR2_RAWAONLANE1_DIG_RX_PHSADJ_LIN 2 0x4109 2 0 4294967295 DATA 0 0 RESERVED_15_5 5 15 ixDPCSSYS_CR2_RAWAONLANE1_DIG_RX_PHSADJ_MAP 2 0x410a 2 0 4294967295 DATA 0 0 RESERVED_15_5 5 15 ixDPCSSYS_CR2_RAWAONLANE1_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST 2 0x410b 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR2_RAWAONLANE1_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST 2 0x410c 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR2_RAWAONLANE1_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST 2 0x410d 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR2_RAWAONLANE1_DIG_DFE_DATA_ODD_LOW_VDAC_OFST 2 0x410e 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR2_RAWAONLANE1_DIG_DFE_BYPASS_EVEN_VDAC_OFST 2 0x410f 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR2_RAWAONLANE1_DIG_DFE_BYPASS_ODD_VDAC_OFST 2 0x4110 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR2_RAWAONLANE1_DIG_DFE_ERROR_EVEN_VDAC_OFST 2 0x4111 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR2_RAWAONLANE1_DIG_DFE_ERROR_ODD_VDAC_OFST 2 0x4112 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR2_RAWAONLANE1_DIG_RX_IQ_PHASE_ADJUST 2 0x4113 2 0 4294967295 DATA 0 0 RESERVED_15_7 7 15 ixDPCSSYS_CR2_RAWAONLANE1_DIG_MPLLA_COARSE_TUNE 2 0x4114 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR2_RAWAONLANE1_DIG_MPLLB_COARSE_TUNE 2 0x4115 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR2_RAWAONLANE1_DIG_INIT_PWRUP_DONE 2 0x4116 3 0 4294967295 DATA 0 0 PH2_PWRUP_DONE 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR2_RAWAONLANE1_DIG_RX_ADPT_ATT 2 0x4117 2 0 4294967295 ATT_ADPT_VAL 0 7 RESERVED_15_8 8 15 ixDPCSSYS_CR2_RAWAONLANE1_DIG_RX_ADPT_VGA 2 0x4118 2 0 4294967295 VGA_ADPT_VAL 0 9 RESERVED_15_10 10 15 ixDPCSSYS_CR2_RAWAONLANE1_DIG_RX_ADPT_CTLE 2 0x4119 3 0 4294967295 CTLE_BOOST_ADPT_VAL 0 9 CTLE_POLE_ADPT_VAL 10 12 RESERVED_15_13 13 15 ixDPCSSYS_CR2_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP1 2 0x411a 2 0 4294967295 DFE_TAP1_ADPT_VAL 0 12 RESERVED_15_13 13 15 ixDPCSSYS_CR2_RAWAONLANE1_DIG_RX_ADAPT_DONE 2 0x411b 2 0 4294967295 DATA 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR2_RAWAONLANE1_DIG_FAST_FLAGS 2 0x411c 16 0 4294967295 FAST_RX_STARTUP_CAL 0 0 FAST_RX_ADAPT 1 1 FAST_RX_AFE_CAL 2 2 FAST_RX_DFE_CAL 3 3 FAST_RX_BYPASS_CAL 4 4 FAST_RX_REFLVL_CAL 5 5 FAST_RX_IQ_CAL 6 6 FAST_RX_AFE_ADAPT 7 7 FAST_RX_DFE_ADAPT 8 8 FAST_SUP 9 9 FAST_TX_CMN_MODE 10 10 FAST_TX_RXDET 11 11 FAST_RX_PWRUP 12 12 FAST_RX_VCO_WAIT 13 13 FAST_RX_VCO_CAL 14 14 RESERVED_15_15 15 15 ixDPCSSYS_CR2_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP2 2 0x411d 2 0 4294967295 DFE_TAP2_ADPT_VAL 0 11 RESERVED_15_12 12 15 ixDPCSSYS_CR2_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP3 2 0x411e 2 0 4294967295 DFE_TAP3_ADPT_VAL 0 11 RESERVED_15_12 12 15 ixDPCSSYS_CR2_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP4 2 0x411f 2 0 4294967295 DFE_TAP4_ADPT_VAL 0 11 RESERVED_15_12 12 15 ixDPCSSYS_CR2_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP5 2 0x4120 2 0 4294967295 DFE_TAP5_ADPT_VAL 0 11 RESERVED_15_12 12 15 ixDPCSSYS_CR2_RAWAONLANE1_DIG_RX_SLICER_CTRL_EVEN 2 0x4121 2 0 4294967295 RX_ANA_SLICER_CTRL_E 0 3 RESERVED_15_4 4 15 ixDPCSSYS_CR2_RAWAONLANE1_DIG_RX_SLICER_CTRL_ODD 2 0x4122 2 0 4294967295 RX_ANA_SLICER_CTRL_O 0 3 RESERVED_15_4 4 15 ixDPCSSYS_CR2_RAWAONLANE1_DIG_LANE_CMNCAL_MPLL_STATUS 2 0x4123 3 0 4294967295 LANE_CMNCAL_MPLL_INIT 0 0 LANE_CMNCAL_MPLL_DONE 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR2_RAWAONLANE1_DIG_ADPT_CTL_0 2 0x4124 1 0 4294967295 VAL 0 15 ixDPCSSYS_CR2_RAWAONLANE1_DIG_ADPT_CTL_1 2 0x4125 1 0 4294967295 VAL 0 15 ixDPCSSYS_CR2_RAWAONLANE1_DIG_ADPT_CTL_2 2 0x4126 1 0 4294967295 VAL 0 15 ixDPCSSYS_CR2_RAWAONLANE1_DIG_ADPT_CTL_3 2 0x4127 1 0 4294967295 VAL 0 15 ixDPCSSYS_CR2_RAWAONLANE1_DIG_ADPT_CTL_4 2 0x4128 1 0 4294967295 VAL 0 15 ixDPCSSYS_CR2_RAWAONLANE1_DIG_ADPT_CTL_5 2 0x4129 1 0 4294967295 VAL 0 15 ixDPCSSYS_CR2_RAWAONLANE1_DIG_ADPT_CTL_6 2 0x412a 1 0 4294967295 VAL 0 15 ixDPCSSYS_CR2_RAWAONLANE1_DIG_ADPT_CTL_7 2 0x412b 1 0 4294967295 VAL 0 15 ixDPCSSYS_CR2_RAWAONLANE1_DIG_MPLL_DISABLE 2 0x412c 3 0 4294967295 LANE_MPLLA_DISABLE 0 0 LANE_MPLLB_DISABLE 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR2_RAWAONLANE1_DIG_FAST_FLAGS_2 2 0x412d 16 0 4294967295 FAST_RX_CONT_CAL_ADAPT 0 0 FAST_RX_CONT_ADAPT 1 1 FAST_RX_CONT_DATA_CAL 2 2 FAST_RX_CONT_PHASE_CAL 3 3 FAST_RX_CONT_AFE_CAL 4 4 FAST_TX_CONT_DCC_CAL 5 5 FAST_RX_CONT_DCC_CAL 6 6 FAST_RX_CONT_VPHUD_CAL 7 7 FAST_RX_CONT_VREF_CAL 8 8 FAST_TX_DCC_CAL 9 9 FAST_RX_DCC_CAL 10 10 FAST_RX_VPHUD_CAL 11 11 FAST_RX_VREF_CAL 12 12 SKIP_TX_RTUNE_CAL 13 13 FAST_RX_SIGDET_CAL 14 14 RESERVED_15_15 15 15 ixDPCSSYS_CR2_RAWAONLANE1_DIG_LANE_CMNCAL_RCAL_STATUS 2 0x412e 3 0 4294967295 LANE_CMNCAL_RCAL_INIT 0 0 LANE_CMNCAL_RCAL_DONE 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR2_RAWAONLANE1_DIG_TXRX_OVRD_IN 2 0x412f 5 0 4294967295 RX_DISABLE_OVRD_VAL 0 0 RX_DISABLE_OVRD_EN 1 1 TX_DISABLE_OVRD_VAL 2 2 TX_DISABLE_OVRD_EN 3 3 RESERVED_15_4 4 15 ixDPCSSYS_CR2_RAWAONLANE1_DIG_RX_LOS_MASK_CTL 2 0x4130 2 0 4294967295 RX_LOS_MASK_CNT 0 8 RESERVED_15_9 9 15 ixDPCSSYS_CR2_RAWAONLANE1_DIG_RX_SIGDET_FILT_CTRL 2 0x4131 5 0 4294967295 ISOLATE_SIGDET_HF 0 0 RX_SIGDEF_HF_FILT_OVR_DIS 1 1 RX_SIGDEF_HF_FILT_OVR 2 2 RX_SIGDET_LF_OUT_FILT_EN 3 3 RESERVED_15_4 4 15 ixDPCSSYS_CR2_RAWAONLANE1_DIG_STATS 2 0x4132 3 0 4294967295 RX_VREFGEN_MASTER 0 0 RX_PMA_SQ_OUT 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR2_RAWAONLANE1_DIG_RX_OVRD_OUT_1 2 0x4133 11 0 4294967295 RX_PMA_SQ_CTRL_TRESH_OVRD_VAL 0 2 RX_PMA_SQ_CTRL_TRESH_OVRD_EN 3 3 RX_PMA_SQ_CTRL_RESP_OVRD_VAL 4 5 RX_PMA_SQ_CTRL_RESP_OVRD_EN 6 6 RX_PMA_SQ_WEAKKEEP_OVRD_VAL 7 7 RX_PMA_SQ_WEAKKEEP_OVRD_EN 8 8 RX_PMA_SQ_INV_POLARITY_OVRD_VAL 9 9 RX_PMA_SQ_INV_POLARITY_OVRD_EN 10 10 RX_PMA_SQ_EN_OVRD_VAL 11 11 RX_PMA_SQ_EN_OVRD_EN 12 12 RESERVED_15_13 13 15 ixDPCSSYS_CR2_RAWAONLANE1_DIG_RX_OVRD_OUT_2 2 0x4134 9 0 4294967295 RX_PMA_VREFGEN_EN_OVRD_VAL 0 0 RX_PMA_VREFGEN_EN_OVRD_EN 1 1 RX_SQ_OUT_OVRD_VAL 2 2 RX_SQ_OUT_OVRD_EN 3 3 RX_PMA_TERM_ACDC_OVRD_VAL 4 4 RX_PMA_TERM_ACDC_OVRD_EN 5 5 RX_PMA_TERM_EN_OVRD_VAL 6 6 RX_PMA_TERM_EN_OVRD_EN 7 7 RESERVED_15_8 8 15 ixDPCSSYS_CR2_RAWAONLANE1_DIG_RX_OVRD_OUT_3 2 0x4135 7 0 4294967295 RX_PMA_SIGDET_LF_FILTER_EN_OVRD_VAL 0 0 RX_PMA_SIGDET_LF_FILTER_EN_OVRD_EN 1 1 RX_PMA_SIGDET_LF_EN_OVRD_VAL 2 2 RX_PMA_SIGDET_LF_EN_OVRD_EN 3 3 RX_PMA_SIGDET_HF_EN_OVRD_VAL 4 4 RX_PMA_SIGDET_HF_EN_OVRD_EN 5 5 RESERVED_15_6 6 15 ixDPCSSYS_CR2_RAWAONLANE1_DIG_RX_SIGDET_CAL 2 0x4136 4 0 4294967295 RX_PMA_SIGDET_LF_THRESHOLD 0 2 RX_PMA_SIGDET_HF_THRESHOLD 3 5 RX_PMA_SIGDET_CAL_EN 6 6 RESERVED_15_7 7 15 ixDPCSSYS_CR2_RAWAONLANE1_DIG_RX_SIGDET_HF_CODE 2 0x4137 2 0 4294967295 RX_PMA_SIGDET_HF_CAL_TUNE 0 5 RESERVED_15_6 6 15 ixDPCSSYS_CR2_RAWAONLANE1_DIG_RX_SIGDET_LF_CODE 2 0x4138 2 0 4294967295 RX_PMA_SIGDET_LF_CAL_TUNE 0 5 RESERVED_15_6 6 15 ixDPCSSYS_CR2_RAWAONLANE1_DIG_RX_VREFGEN_EN 2 0x4139 2 0 4294967295 PULL_UP 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR2_RAWAONLANE1_DIG_CAL_IOFF_CODE 2 0x413a 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR2_RAWAONLANE1_DIG_CAL_ICONST_CODE 2 0x413b 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR2_RAWAONLANE1_DIG_CAL_VREFGEN_CODE 2 0x413c 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR2_RAWAONLANE1_DIG_RX_DCC_CAL_ICM_CODE_0 2 0x413d 2 0 4294967295 RX_DCC_CAL_ICM_CODE 0 9 RESERVED_15_10 10 15 ixDPCSSYS_CR2_RAWAONLANE1_DIG_RX_DCC_CAL_IDF_CODE_0 2 0x413e 2 0 4294967295 RX_DCC_CAL_IDF_CODE 0 9 RESERVED_15_10 10 15 ixDPCSSYS_CR2_RAWAONLANE1_DIG_RX_DCC_CAL_QCM_CODE_0 2 0x413f 2 0 4294967295 RX_DCC_CAL_QCM_CODE 0 9 RESERVED_15_10 10 15 ixDPCSSYS_CR2_RAWAONLANE1_DIG_RX_DCC_CAL_QDF_CODE_0 2 0x4140 2 0 4294967295 RX_DCC_CAL_QDF_CODE 0 9 RESERVED_15_10 10 15 ixDPCSSYS_CR2_RAWAONLANE1_DIG_RX_DCC_CAL_ICM_CODE_1 2 0x4141 2 0 4294967295 RX_DCC_CAL_ICM_CODE 0 9 RESERVED_15_10 10 15 ixDPCSSYS_CR2_RAWAONLANE1_DIG_RX_DCC_CAL_IDF_CODE_1 2 0x4142 2 0 4294967295 RX_DCC_CAL_IDF_CODE 0 9 RESERVED_15_10 10 15 ixDPCSSYS_CR2_RAWAONLANE1_DIG_RX_DCC_CAL_QCM_CODE_1 2 0x4143 2 0 4294967295 RX_DCC_CAL_QCM_CODE 0 9 RESERVED_15_10 10 15 ixDPCSSYS_CR2_RAWAONLANE1_DIG_RX_DCC_CAL_QDF_CODE_1 2 0x4144 2 0 4294967295 RX_DCC_CAL_QDF_CODE 0 9 RESERVED_15_10 10 15 ixDPCSSYS_CR2_RAWAONLANE1_DIG_TX_DCC_BANK_ADDR 2 0x4145 1 0 4294967295 ADDR 0 15 ixDPCSSYS_CR2_RAWAONLANE1_DIG_TX_DCC_BANK_DATA 2 0x4146 1 0 4294967295 DATA 0 15 ixDPCSSYS_CR2_RAWAONLANE1_DIG_TX_DCC_CONT 2 0x4147 2 0 4294967295 EN 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR2_RAWAONLANE1_DIG_MPLL_BG_CTL 2 0x4148 3 0 4294967295 MPLL_STATE_WAIT 0 0 MPLL_STATE_DLY_EN 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR2_RAWAONLANE1_DIG_SIGDET_OUT_OVRD 2 0x4149 5 0 4294967295 RX_SIGDET_HF_OUT_OVRD_VAL 0 0 RX_SIGDET_HF_OUT_OVRD_EN 1 1 RX_SIGDET_LF_OUT_OVRD_VAL 2 2 RX_SIGDET_LF_OUT_OVRD_EN 3 3 RESERVED_15_4 4 15 ixDPCSSYS_CR2_RAWAONLANE1_DIG_SIGDET_OUT_IN 2 0x414a 3 0 4294967295 RX_SIGDET_HF_OUT_OVRD_VAL 0 0 RX_SIGDET_LF_OUT_OVRD_VAL 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR2_RAWAONLANE1_DIG_FW_MM_CONFIG 2 0x414b 1 0 4294967295 DATA 0 0 ixDPCSSYS_CR2_RAWAONLANE1_DIG_FW_ADPT_CONFIG 2 0x414c 2 0 4294967295 REF_LVL_ADPT 0 7 FW_CONFIG 8 15 ixDPCSSYS_CR2_RAWAONLANE1_DIG_FW_CALIB_CONFIG 2 0x414d 1 0 4294967295 FW_CALIB 0 15 ixDPCSSYS_CR2_RAWAONLANE1_DIG_LANE_XCVR_MODE_OVRD_IN 2 0x414e 3 0 4294967295 LANE_XCVR_MODE_OVRD_VAL 0 1 LANE_XCVR_MODE_OVRD_EN 2 2 RESERVED_15_3 3 15 ixDPCSSYS_CR2_RAWAONLANE1_DIG_LANE_XCVR_MODE_IN 2 0x414f 2 0 4294967295 LANE_XCVR_MODE 0 1 RESERVED_15_2 2 15 ixDPCSSYS_CR2_RAWAONLANE1_DIG_RX_SIGDET_CONFIG 2 0x4150 4 0 4294967295 RX_SIGDET_HF_FILTER_COUNTER 0 4 RX_SIGDET_LF_FILTER_COUNTER 5 9 RX_SIGDET_LF_HOLD 10 10 RESERVED_15_11 11 15 ixDPCSSYS_CR2_RAWAONLANE1_DIG_TX_DCC_CONFIG 2 0x4151 1 0 4294967295 DATA 0 0 ixDPCSSYS_CR2_RAWAONLANE2_DIG_AFE_ATT_IDAC_OFST 2 0x4200 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR2_RAWAONLANE2_DIG_AFE_CTLE_IDAC_OFST 2 0x4201 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR2_RAWAONLANE2_DIG_RX_ADPT_IQ 2 0x4202 2 0 4294967295 IQ_ADPT_VAL 0 6 RESERVED_15_7 7 15 ixDPCSSYS_CR2_RAWAONLANE2_DIG_RX_ADAPT_FOM 2 0x4203 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR2_RAWAONLANE2_DIG_DFE_SUMMER_ODD_IDAC_OFST 2 0x4204 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR2_RAWAONLANE2_DIG_DFE_PHASE_EVEN_VDAC_OFST 2 0x4205 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR2_RAWAONLANE2_DIG_DFE_PHASE_ODD_VDAC_OFST 2 0x4206 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR2_RAWAONLANE2_DIG_DFE_EVEN_REF_LVL 2 0x4207 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR2_RAWAONLANE2_DIG_DFE_ODD_REF_LVL 2 0x4208 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR2_RAWAONLANE2_DIG_RX_PHSADJ_LIN 2 0x4209 2 0 4294967295 DATA 0 0 RESERVED_15_5 5 15 ixDPCSSYS_CR2_RAWAONLANE2_DIG_RX_PHSADJ_MAP 2 0x420a 2 0 4294967295 DATA 0 0 RESERVED_15_5 5 15 ixDPCSSYS_CR2_RAWAONLANE2_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST 2 0x420b 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR2_RAWAONLANE2_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST 2 0x420c 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR2_RAWAONLANE2_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST 2 0x420d 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR2_RAWAONLANE2_DIG_DFE_DATA_ODD_LOW_VDAC_OFST 2 0x420e 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR2_RAWAONLANE2_DIG_DFE_BYPASS_EVEN_VDAC_OFST 2 0x420f 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR2_RAWAONLANE2_DIG_DFE_BYPASS_ODD_VDAC_OFST 2 0x4210 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR2_RAWAONLANE2_DIG_DFE_ERROR_EVEN_VDAC_OFST 2 0x4211 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR2_RAWAONLANE2_DIG_DFE_ERROR_ODD_VDAC_OFST 2 0x4212 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR2_RAWAONLANE2_DIG_RX_IQ_PHASE_ADJUST 2 0x4213 2 0 4294967295 DATA 0 0 RESERVED_15_7 7 15 ixDPCSSYS_CR2_RAWAONLANE2_DIG_MPLLA_COARSE_TUNE 2 0x4214 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR2_RAWAONLANE2_DIG_MPLLB_COARSE_TUNE 2 0x4215 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR2_RAWAONLANE2_DIG_INIT_PWRUP_DONE 2 0x4216 3 0 4294967295 DATA 0 0 PH2_PWRUP_DONE 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR2_RAWAONLANE2_DIG_RX_ADPT_ATT 2 0x4217 2 0 4294967295 ATT_ADPT_VAL 0 7 RESERVED_15_8 8 15 ixDPCSSYS_CR2_RAWAONLANE2_DIG_RX_ADPT_VGA 2 0x4218 2 0 4294967295 VGA_ADPT_VAL 0 9 RESERVED_15_10 10 15 ixDPCSSYS_CR2_RAWAONLANE2_DIG_RX_ADPT_CTLE 2 0x4219 3 0 4294967295 CTLE_BOOST_ADPT_VAL 0 9 CTLE_POLE_ADPT_VAL 10 12 RESERVED_15_13 13 15 ixDPCSSYS_CR2_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP1 2 0x421a 2 0 4294967295 DFE_TAP1_ADPT_VAL 0 12 RESERVED_15_13 13 15 ixDPCSSYS_CR2_RAWAONLANE2_DIG_RX_ADAPT_DONE 2 0x421b 2 0 4294967295 DATA 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR2_RAWAONLANE2_DIG_FAST_FLAGS 2 0x421c 16 0 4294967295 FAST_RX_STARTUP_CAL 0 0 FAST_RX_ADAPT 1 1 FAST_RX_AFE_CAL 2 2 FAST_RX_DFE_CAL 3 3 FAST_RX_BYPASS_CAL 4 4 FAST_RX_REFLVL_CAL 5 5 FAST_RX_IQ_CAL 6 6 FAST_RX_AFE_ADAPT 7 7 FAST_RX_DFE_ADAPT 8 8 FAST_SUP 9 9 FAST_TX_CMN_MODE 10 10 FAST_TX_RXDET 11 11 FAST_RX_PWRUP 12 12 FAST_RX_VCO_WAIT 13 13 FAST_RX_VCO_CAL 14 14 RESERVED_15_15 15 15 ixDPCSSYS_CR2_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP2 2 0x421d 2 0 4294967295 DFE_TAP2_ADPT_VAL 0 11 RESERVED_15_12 12 15 ixDPCSSYS_CR2_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP3 2 0x421e 2 0 4294967295 DFE_TAP3_ADPT_VAL 0 11 RESERVED_15_12 12 15 ixDPCSSYS_CR2_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP4 2 0x421f 2 0 4294967295 DFE_TAP4_ADPT_VAL 0 11 RESERVED_15_12 12 15 ixDPCSSYS_CR2_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP5 2 0x4220 2 0 4294967295 DFE_TAP5_ADPT_VAL 0 11 RESERVED_15_12 12 15 ixDPCSSYS_CR2_RAWAONLANE2_DIG_RX_SLICER_CTRL_EVEN 2 0x4221 2 0 4294967295 RX_ANA_SLICER_CTRL_E 0 3 RESERVED_15_4 4 15 ixDPCSSYS_CR2_RAWAONLANE2_DIG_RX_SLICER_CTRL_ODD 2 0x4222 2 0 4294967295 RX_ANA_SLICER_CTRL_O 0 3 RESERVED_15_4 4 15 ixDPCSSYS_CR2_RAWAONLANE2_DIG_LANE_CMNCAL_MPLL_STATUS 2 0x4223 3 0 4294967295 LANE_CMNCAL_MPLL_INIT 0 0 LANE_CMNCAL_MPLL_DONE 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR2_RAWAONLANE2_DIG_ADPT_CTL_0 2 0x4224 1 0 4294967295 VAL 0 15 ixDPCSSYS_CR2_RAWAONLANE2_DIG_ADPT_CTL_1 2 0x4225 1 0 4294967295 VAL 0 15 ixDPCSSYS_CR2_RAWAONLANE2_DIG_ADPT_CTL_2 2 0x4226 1 0 4294967295 VAL 0 15 ixDPCSSYS_CR2_RAWAONLANE2_DIG_ADPT_CTL_3 2 0x4227 1 0 4294967295 VAL 0 15 ixDPCSSYS_CR2_RAWAONLANE2_DIG_ADPT_CTL_4 2 0x4228 1 0 4294967295 VAL 0 15 ixDPCSSYS_CR2_RAWAONLANE2_DIG_ADPT_CTL_5 2 0x4229 1 0 4294967295 VAL 0 15 ixDPCSSYS_CR2_RAWAONLANE2_DIG_ADPT_CTL_6 2 0x422a 1 0 4294967295 VAL 0 15 ixDPCSSYS_CR2_RAWAONLANE2_DIG_ADPT_CTL_7 2 0x422b 1 0 4294967295 VAL 0 15 ixDPCSSYS_CR2_RAWAONLANE2_DIG_MPLL_DISABLE 2 0x422c 3 0 4294967295 LANE_MPLLA_DISABLE 0 0 LANE_MPLLB_DISABLE 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR2_RAWAONLANE2_DIG_FAST_FLAGS_2 2 0x422d 16 0 4294967295 FAST_RX_CONT_CAL_ADAPT 0 0 FAST_RX_CONT_ADAPT 1 1 FAST_RX_CONT_DATA_CAL 2 2 FAST_RX_CONT_PHASE_CAL 3 3 FAST_RX_CONT_AFE_CAL 4 4 FAST_TX_CONT_DCC_CAL 5 5 FAST_RX_CONT_DCC_CAL 6 6 FAST_RX_CONT_VPHUD_CAL 7 7 FAST_RX_CONT_VREF_CAL 8 8 FAST_TX_DCC_CAL 9 9 FAST_RX_DCC_CAL 10 10 FAST_RX_VPHUD_CAL 11 11 FAST_RX_VREF_CAL 12 12 SKIP_TX_RTUNE_CAL 13 13 FAST_RX_SIGDET_CAL 14 14 RESERVED_15_15 15 15 ixDPCSSYS_CR2_RAWAONLANE2_DIG_LANE_CMNCAL_RCAL_STATUS 2 0x422e 3 0 4294967295 LANE_CMNCAL_RCAL_INIT 0 0 LANE_CMNCAL_RCAL_DONE 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR2_RAWAONLANE2_DIG_TXRX_OVRD_IN 2 0x422f 5 0 4294967295 RX_DISABLE_OVRD_VAL 0 0 RX_DISABLE_OVRD_EN 1 1 TX_DISABLE_OVRD_VAL 2 2 TX_DISABLE_OVRD_EN 3 3 RESERVED_15_4 4 15 ixDPCSSYS_CR2_RAWAONLANE2_DIG_RX_LOS_MASK_CTL 2 0x4230 2 0 4294967295 RX_LOS_MASK_CNT 0 8 RESERVED_15_9 9 15 ixDPCSSYS_CR2_RAWAONLANE2_DIG_RX_SIGDET_FILT_CTRL 2 0x4231 5 0 4294967295 ISOLATE_SIGDET_HF 0 0 RX_SIGDEF_HF_FILT_OVR_DIS 1 1 RX_SIGDEF_HF_FILT_OVR 2 2 RX_SIGDET_LF_OUT_FILT_EN 3 3 RESERVED_15_4 4 15 ixDPCSSYS_CR2_RAWAONLANE2_DIG_STATS 2 0x4232 3 0 4294967295 RX_VREFGEN_MASTER 0 0 RX_PMA_SQ_OUT 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR2_RAWAONLANE2_DIG_RX_OVRD_OUT_1 2 0x4233 11 0 4294967295 RX_PMA_SQ_CTRL_TRESH_OVRD_VAL 0 2 RX_PMA_SQ_CTRL_TRESH_OVRD_EN 3 3 RX_PMA_SQ_CTRL_RESP_OVRD_VAL 4 5 RX_PMA_SQ_CTRL_RESP_OVRD_EN 6 6 RX_PMA_SQ_WEAKKEEP_OVRD_VAL 7 7 RX_PMA_SQ_WEAKKEEP_OVRD_EN 8 8 RX_PMA_SQ_INV_POLARITY_OVRD_VAL 9 9 RX_PMA_SQ_INV_POLARITY_OVRD_EN 10 10 RX_PMA_SQ_EN_OVRD_VAL 11 11 RX_PMA_SQ_EN_OVRD_EN 12 12 RESERVED_15_13 13 15 ixDPCSSYS_CR2_RAWAONLANE2_DIG_RX_OVRD_OUT_2 2 0x4234 9 0 4294967295 RX_PMA_VREFGEN_EN_OVRD_VAL 0 0 RX_PMA_VREFGEN_EN_OVRD_EN 1 1 RX_SQ_OUT_OVRD_VAL 2 2 RX_SQ_OUT_OVRD_EN 3 3 RX_PMA_TERM_ACDC_OVRD_VAL 4 4 RX_PMA_TERM_ACDC_OVRD_EN 5 5 RX_PMA_TERM_EN_OVRD_VAL 6 6 RX_PMA_TERM_EN_OVRD_EN 7 7 RESERVED_15_8 8 15 ixDPCSSYS_CR2_RAWAONLANE2_DIG_RX_OVRD_OUT_3 2 0x4235 7 0 4294967295 RX_PMA_SIGDET_LF_FILTER_EN_OVRD_VAL 0 0 RX_PMA_SIGDET_LF_FILTER_EN_OVRD_EN 1 1 RX_PMA_SIGDET_LF_EN_OVRD_VAL 2 2 RX_PMA_SIGDET_LF_EN_OVRD_EN 3 3 RX_PMA_SIGDET_HF_EN_OVRD_VAL 4 4 RX_PMA_SIGDET_HF_EN_OVRD_EN 5 5 RESERVED_15_6 6 15 ixDPCSSYS_CR2_RAWAONLANE2_DIG_RX_SIGDET_CAL 2 0x4236 4 0 4294967295 RX_PMA_SIGDET_LF_THRESHOLD 0 2 RX_PMA_SIGDET_HF_THRESHOLD 3 5 RX_PMA_SIGDET_CAL_EN 6 6 RESERVED_15_7 7 15 ixDPCSSYS_CR2_RAWAONLANE2_DIG_RX_SIGDET_HF_CODE 2 0x4237 2 0 4294967295 RX_PMA_SIGDET_HF_CAL_TUNE 0 5 RESERVED_15_6 6 15 ixDPCSSYS_CR2_RAWAONLANE2_DIG_RX_SIGDET_LF_CODE 2 0x4238 2 0 4294967295 RX_PMA_SIGDET_LF_CAL_TUNE 0 5 RESERVED_15_6 6 15 ixDPCSSYS_CR2_RAWAONLANE2_DIG_RX_VREFGEN_EN 2 0x4239 2 0 4294967295 PULL_UP 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR2_RAWAONLANE2_DIG_CAL_IOFF_CODE 2 0x423a 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR2_RAWAONLANE2_DIG_CAL_ICONST_CODE 2 0x423b 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR2_RAWAONLANE2_DIG_CAL_VREFGEN_CODE 2 0x423c 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR2_RAWAONLANE2_DIG_RX_DCC_CAL_ICM_CODE_0 2 0x423d 2 0 4294967295 RX_DCC_CAL_ICM_CODE 0 9 RESERVED_15_10 10 15 ixDPCSSYS_CR2_RAWAONLANE2_DIG_RX_DCC_CAL_IDF_CODE_0 2 0x423e 2 0 4294967295 RX_DCC_CAL_IDF_CODE 0 9 RESERVED_15_10 10 15 ixDPCSSYS_CR2_RAWAONLANE2_DIG_RX_DCC_CAL_QCM_CODE_0 2 0x423f 2 0 4294967295 RX_DCC_CAL_QCM_CODE 0 9 RESERVED_15_10 10 15 ixDPCSSYS_CR2_RAWAONLANE2_DIG_RX_DCC_CAL_QDF_CODE_0 2 0x4240 2 0 4294967295 RX_DCC_CAL_QDF_CODE 0 9 RESERVED_15_10 10 15 ixDPCSSYS_CR2_RAWAONLANE2_DIG_RX_DCC_CAL_ICM_CODE_1 2 0x4241 2 0 4294967295 RX_DCC_CAL_ICM_CODE 0 9 RESERVED_15_10 10 15 ixDPCSSYS_CR2_RAWAONLANE2_DIG_RX_DCC_CAL_IDF_CODE_1 2 0x4242 2 0 4294967295 RX_DCC_CAL_IDF_CODE 0 9 RESERVED_15_10 10 15 ixDPCSSYS_CR2_RAWAONLANE2_DIG_RX_DCC_CAL_QCM_CODE_1 2 0x4243 2 0 4294967295 RX_DCC_CAL_QCM_CODE 0 9 RESERVED_15_10 10 15 ixDPCSSYS_CR2_RAWAONLANE2_DIG_RX_DCC_CAL_QDF_CODE_1 2 0x4244 2 0 4294967295 RX_DCC_CAL_QDF_CODE 0 9 RESERVED_15_10 10 15 ixDPCSSYS_CR2_RAWAONLANE2_DIG_TX_DCC_BANK_ADDR 2 0x4245 1 0 4294967295 ADDR 0 15 ixDPCSSYS_CR2_RAWAONLANE2_DIG_TX_DCC_BANK_DATA 2 0x4246 1 0 4294967295 DATA 0 15 ixDPCSSYS_CR2_RAWAONLANE2_DIG_TX_DCC_CONT 2 0x4247 2 0 4294967295 EN 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR2_RAWAONLANE2_DIG_MPLL_BG_CTL 2 0x4248 3 0 4294967295 MPLL_STATE_WAIT 0 0 MPLL_STATE_DLY_EN 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR2_RAWAONLANE2_DIG_SIGDET_OUT_OVRD 2 0x4249 5 0 4294967295 RX_SIGDET_HF_OUT_OVRD_VAL 0 0 RX_SIGDET_HF_OUT_OVRD_EN 1 1 RX_SIGDET_LF_OUT_OVRD_VAL 2 2 RX_SIGDET_LF_OUT_OVRD_EN 3 3 RESERVED_15_4 4 15 ixDPCSSYS_CR2_RAWAONLANE2_DIG_SIGDET_OUT_IN 2 0x424a 3 0 4294967295 RX_SIGDET_HF_OUT_OVRD_VAL 0 0 RX_SIGDET_LF_OUT_OVRD_VAL 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR2_RAWAONLANE2_DIG_FW_MM_CONFIG 2 0x424b 1 0 4294967295 DATA 0 0 ixDPCSSYS_CR2_RAWAONLANE2_DIG_FW_ADPT_CONFIG 2 0x424c 2 0 4294967295 REF_LVL_ADPT 0 7 FW_CONFIG 8 15 ixDPCSSYS_CR2_RAWAONLANE2_DIG_FW_CALIB_CONFIG 2 0x424d 1 0 4294967295 FW_CALIB 0 15 ixDPCSSYS_CR2_RAWAONLANE2_DIG_LANE_XCVR_MODE_OVRD_IN 2 0x424e 3 0 4294967295 LANE_XCVR_MODE_OVRD_VAL 0 1 LANE_XCVR_MODE_OVRD_EN 2 2 RESERVED_15_3 3 15 ixDPCSSYS_CR2_RAWAONLANE2_DIG_LANE_XCVR_MODE_IN 2 0x424f 2 0 4294967295 LANE_XCVR_MODE 0 1 RESERVED_15_2 2 15 ixDPCSSYS_CR2_RAWAONLANE2_DIG_RX_SIGDET_CONFIG 2 0x4250 4 0 4294967295 RX_SIGDET_HF_FILTER_COUNTER 0 4 RX_SIGDET_LF_FILTER_COUNTER 5 9 RX_SIGDET_LF_HOLD 10 10 RESERVED_15_11 11 15 ixDPCSSYS_CR2_RAWAONLANE2_DIG_TX_DCC_CONFIG 2 0x4251 1 0 4294967295 DATA 0 0 ixDPCSSYS_CR2_RAWAONLANE3_DIG_AFE_ATT_IDAC_OFST 2 0x4300 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR2_RAWAONLANE3_DIG_AFE_CTLE_IDAC_OFST 2 0x4301 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR2_RAWAONLANE3_DIG_RX_ADPT_IQ 2 0x4302 2 0 4294967295 IQ_ADPT_VAL 0 6 RESERVED_15_7 7 15 ixDPCSSYS_CR2_RAWAONLANE3_DIG_RX_ADAPT_FOM 2 0x4303 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR2_RAWAONLANE3_DIG_DFE_SUMMER_ODD_IDAC_OFST 2 0x4304 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR2_RAWAONLANE3_DIG_DFE_PHASE_EVEN_VDAC_OFST 2 0x4305 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR2_RAWAONLANE3_DIG_DFE_PHASE_ODD_VDAC_OFST 2 0x4306 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR2_RAWAONLANE3_DIG_DFE_EVEN_REF_LVL 2 0x4307 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR2_RAWAONLANE3_DIG_DFE_ODD_REF_LVL 2 0x4308 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR2_RAWAONLANE3_DIG_RX_PHSADJ_LIN 2 0x4309 2 0 4294967295 DATA 0 0 RESERVED_15_5 5 15 ixDPCSSYS_CR2_RAWAONLANE3_DIG_RX_PHSADJ_MAP 2 0x430a 2 0 4294967295 DATA 0 0 RESERVED_15_5 5 15 ixDPCSSYS_CR2_RAWAONLANE3_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST 2 0x430b 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR2_RAWAONLANE3_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST 2 0x430c 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR2_RAWAONLANE3_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST 2 0x430d 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR2_RAWAONLANE3_DIG_DFE_DATA_ODD_LOW_VDAC_OFST 2 0x430e 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR2_RAWAONLANE3_DIG_DFE_BYPASS_EVEN_VDAC_OFST 2 0x430f 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR2_RAWAONLANE3_DIG_DFE_BYPASS_ODD_VDAC_OFST 2 0x4310 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR2_RAWAONLANE3_DIG_DFE_ERROR_EVEN_VDAC_OFST 2 0x4311 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR2_RAWAONLANE3_DIG_DFE_ERROR_ODD_VDAC_OFST 2 0x4312 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR2_RAWAONLANE3_DIG_RX_IQ_PHASE_ADJUST 2 0x4313 2 0 4294967295 DATA 0 0 RESERVED_15_7 7 15 ixDPCSSYS_CR2_RAWAONLANE3_DIG_MPLLA_COARSE_TUNE 2 0x4314 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR2_RAWAONLANE3_DIG_MPLLB_COARSE_TUNE 2 0x4315 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR2_RAWAONLANE3_DIG_INIT_PWRUP_DONE 2 0x4316 3 0 4294967295 DATA 0 0 PH2_PWRUP_DONE 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR2_RAWAONLANE3_DIG_RX_ADPT_ATT 2 0x4317 2 0 4294967295 ATT_ADPT_VAL 0 7 RESERVED_15_8 8 15 ixDPCSSYS_CR2_RAWAONLANE3_DIG_RX_ADPT_VGA 2 0x4318 2 0 4294967295 VGA_ADPT_VAL 0 9 RESERVED_15_10 10 15 ixDPCSSYS_CR2_RAWAONLANE3_DIG_RX_ADPT_CTLE 2 0x4319 3 0 4294967295 CTLE_BOOST_ADPT_VAL 0 9 CTLE_POLE_ADPT_VAL 10 12 RESERVED_15_13 13 15 ixDPCSSYS_CR2_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP1 2 0x431a 2 0 4294967295 DFE_TAP1_ADPT_VAL 0 12 RESERVED_15_13 13 15 ixDPCSSYS_CR2_RAWAONLANE3_DIG_RX_ADAPT_DONE 2 0x431b 2 0 4294967295 DATA 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR2_RAWAONLANE3_DIG_FAST_FLAGS 2 0x431c 16 0 4294967295 FAST_RX_STARTUP_CAL 0 0 FAST_RX_ADAPT 1 1 FAST_RX_AFE_CAL 2 2 FAST_RX_DFE_CAL 3 3 FAST_RX_BYPASS_CAL 4 4 FAST_RX_REFLVL_CAL 5 5 FAST_RX_IQ_CAL 6 6 FAST_RX_AFE_ADAPT 7 7 FAST_RX_DFE_ADAPT 8 8 FAST_SUP 9 9 FAST_TX_CMN_MODE 10 10 FAST_TX_RXDET 11 11 FAST_RX_PWRUP 12 12 FAST_RX_VCO_WAIT 13 13 FAST_RX_VCO_CAL 14 14 RESERVED_15_15 15 15 ixDPCSSYS_CR2_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP2 2 0x431d 2 0 4294967295 DFE_TAP2_ADPT_VAL 0 11 RESERVED_15_12 12 15 ixDPCSSYS_CR2_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP3 2 0x431e 2 0 4294967295 DFE_TAP3_ADPT_VAL 0 11 RESERVED_15_12 12 15 ixDPCSSYS_CR2_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP4 2 0x431f 2 0 4294967295 DFE_TAP4_ADPT_VAL 0 11 RESERVED_15_12 12 15 ixDPCSSYS_CR2_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP5 2 0x4320 2 0 4294967295 DFE_TAP5_ADPT_VAL 0 11 RESERVED_15_12 12 15 ixDPCSSYS_CR2_RAWAONLANE3_DIG_RX_SLICER_CTRL_EVEN 2 0x4321 2 0 4294967295 RX_ANA_SLICER_CTRL_E 0 3 RESERVED_15_4 4 15 ixDPCSSYS_CR2_RAWAONLANE3_DIG_RX_SLICER_CTRL_ODD 2 0x4322 2 0 4294967295 RX_ANA_SLICER_CTRL_O 0 3 RESERVED_15_4 4 15 ixDPCSSYS_CR2_RAWAONLANE3_DIG_LANE_CMNCAL_MPLL_STATUS 2 0x4323 3 0 4294967295 LANE_CMNCAL_MPLL_INIT 0 0 LANE_CMNCAL_MPLL_DONE 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR2_RAWAONLANE3_DIG_ADPT_CTL_0 2 0x4324 1 0 4294967295 VAL 0 15 ixDPCSSYS_CR2_RAWAONLANE3_DIG_ADPT_CTL_1 2 0x4325 1 0 4294967295 VAL 0 15 ixDPCSSYS_CR2_RAWAONLANE3_DIG_ADPT_CTL_2 2 0x4326 1 0 4294967295 VAL 0 15 ixDPCSSYS_CR2_RAWAONLANE3_DIG_ADPT_CTL_3 2 0x4327 1 0 4294967295 VAL 0 15 ixDPCSSYS_CR2_RAWAONLANE3_DIG_ADPT_CTL_4 2 0x4328 1 0 4294967295 VAL 0 15 ixDPCSSYS_CR2_RAWAONLANE3_DIG_ADPT_CTL_5 2 0x4329 1 0 4294967295 VAL 0 15 ixDPCSSYS_CR2_RAWAONLANE3_DIG_ADPT_CTL_6 2 0x432a 1 0 4294967295 VAL 0 15 ixDPCSSYS_CR2_RAWAONLANE3_DIG_ADPT_CTL_7 2 0x432b 1 0 4294967295 VAL 0 15 ixDPCSSYS_CR2_RAWAONLANE3_DIG_MPLL_DISABLE 2 0x432c 3 0 4294967295 LANE_MPLLA_DISABLE 0 0 LANE_MPLLB_DISABLE 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR2_RAWAONLANE3_DIG_FAST_FLAGS_2 2 0x432d 16 0 4294967295 FAST_RX_CONT_CAL_ADAPT 0 0 FAST_RX_CONT_ADAPT 1 1 FAST_RX_CONT_DATA_CAL 2 2 FAST_RX_CONT_PHASE_CAL 3 3 FAST_RX_CONT_AFE_CAL 4 4 FAST_TX_CONT_DCC_CAL 5 5 FAST_RX_CONT_DCC_CAL 6 6 FAST_RX_CONT_VPHUD_CAL 7 7 FAST_RX_CONT_VREF_CAL 8 8 FAST_TX_DCC_CAL 9 9 FAST_RX_DCC_CAL 10 10 FAST_RX_VPHUD_CAL 11 11 FAST_RX_VREF_CAL 12 12 SKIP_TX_RTUNE_CAL 13 13 FAST_RX_SIGDET_CAL 14 14 RESERVED_15_15 15 15 ixDPCSSYS_CR2_RAWAONLANE3_DIG_LANE_CMNCAL_RCAL_STATUS 2 0x432e 3 0 4294967295 LANE_CMNCAL_RCAL_INIT 0 0 LANE_CMNCAL_RCAL_DONE 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR2_RAWAONLANE3_DIG_TXRX_OVRD_IN 2 0x432f 5 0 4294967295 RX_DISABLE_OVRD_VAL 0 0 RX_DISABLE_OVRD_EN 1 1 TX_DISABLE_OVRD_VAL 2 2 TX_DISABLE_OVRD_EN 3 3 RESERVED_15_4 4 15 ixDPCSSYS_CR2_RAWAONLANE3_DIG_RX_LOS_MASK_CTL 2 0x4330 2 0 4294967295 RX_LOS_MASK_CNT 0 8 RESERVED_15_9 9 15 ixDPCSSYS_CR2_RAWAONLANE3_DIG_RX_SIGDET_FILT_CTRL 2 0x4331 5 0 4294967295 ISOLATE_SIGDET_HF 0 0 RX_SIGDEF_HF_FILT_OVR_DIS 1 1 RX_SIGDEF_HF_FILT_OVR 2 2 RX_SIGDET_LF_OUT_FILT_EN 3 3 RESERVED_15_4 4 15 ixDPCSSYS_CR2_RAWAONLANE3_DIG_STATS 2 0x4332 3 0 4294967295 RX_VREFGEN_MASTER 0 0 RX_PMA_SQ_OUT 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR2_RAWAONLANE3_DIG_RX_OVRD_OUT_1 2 0x4333 11 0 4294967295 RX_PMA_SQ_CTRL_TRESH_OVRD_VAL 0 2 RX_PMA_SQ_CTRL_TRESH_OVRD_EN 3 3 RX_PMA_SQ_CTRL_RESP_OVRD_VAL 4 5 RX_PMA_SQ_CTRL_RESP_OVRD_EN 6 6 RX_PMA_SQ_WEAKKEEP_OVRD_VAL 7 7 RX_PMA_SQ_WEAKKEEP_OVRD_EN 8 8 RX_PMA_SQ_INV_POLARITY_OVRD_VAL 9 9 RX_PMA_SQ_INV_POLARITY_OVRD_EN 10 10 RX_PMA_SQ_EN_OVRD_VAL 11 11 RX_PMA_SQ_EN_OVRD_EN 12 12 RESERVED_15_13 13 15 ixDPCSSYS_CR2_RAWAONLANE3_DIG_RX_OVRD_OUT_2 2 0x4334 9 0 4294967295 RX_PMA_VREFGEN_EN_OVRD_VAL 0 0 RX_PMA_VREFGEN_EN_OVRD_EN 1 1 RX_SQ_OUT_OVRD_VAL 2 2 RX_SQ_OUT_OVRD_EN 3 3 RX_PMA_TERM_ACDC_OVRD_VAL 4 4 RX_PMA_TERM_ACDC_OVRD_EN 5 5 RX_PMA_TERM_EN_OVRD_VAL 6 6 RX_PMA_TERM_EN_OVRD_EN 7 7 RESERVED_15_8 8 15 ixDPCSSYS_CR2_RAWAONLANE3_DIG_RX_OVRD_OUT_3 2 0x4335 7 0 4294967295 RX_PMA_SIGDET_LF_FILTER_EN_OVRD_VAL 0 0 RX_PMA_SIGDET_LF_FILTER_EN_OVRD_EN 1 1 RX_PMA_SIGDET_LF_EN_OVRD_VAL 2 2 RX_PMA_SIGDET_LF_EN_OVRD_EN 3 3 RX_PMA_SIGDET_HF_EN_OVRD_VAL 4 4 RX_PMA_SIGDET_HF_EN_OVRD_EN 5 5 RESERVED_15_6 6 15 ixDPCSSYS_CR2_RAWAONLANE3_DIG_RX_SIGDET_CAL 2 0x4336 4 0 4294967295 RX_PMA_SIGDET_LF_THRESHOLD 0 2 RX_PMA_SIGDET_HF_THRESHOLD 3 5 RX_PMA_SIGDET_CAL_EN 6 6 RESERVED_15_7 7 15 ixDPCSSYS_CR2_RAWAONLANE3_DIG_RX_SIGDET_HF_CODE 2 0x4337 2 0 4294967295 RX_PMA_SIGDET_HF_CAL_TUNE 0 5 RESERVED_15_6 6 15 ixDPCSSYS_CR2_RAWAONLANE3_DIG_RX_SIGDET_LF_CODE 2 0x4338 2 0 4294967295 RX_PMA_SIGDET_LF_CAL_TUNE 0 5 RESERVED_15_6 6 15 ixDPCSSYS_CR2_RAWAONLANE3_DIG_RX_VREFGEN_EN 2 0x4339 2 0 4294967295 PULL_UP 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR2_RAWAONLANE3_DIG_CAL_IOFF_CODE 2 0x433a 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR2_RAWAONLANE3_DIG_CAL_ICONST_CODE 2 0x433b 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR2_RAWAONLANE3_DIG_CAL_VREFGEN_CODE 2 0x433c 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR2_RAWAONLANE3_DIG_RX_DCC_CAL_ICM_CODE_0 2 0x433d 2 0 4294967295 RX_DCC_CAL_ICM_CODE 0 9 RESERVED_15_10 10 15 ixDPCSSYS_CR2_RAWAONLANE3_DIG_RX_DCC_CAL_IDF_CODE_0 2 0x433e 2 0 4294967295 RX_DCC_CAL_IDF_CODE 0 9 RESERVED_15_10 10 15 ixDPCSSYS_CR2_RAWAONLANE3_DIG_RX_DCC_CAL_QCM_CODE_0 2 0x433f 2 0 4294967295 RX_DCC_CAL_QCM_CODE 0 9 RESERVED_15_10 10 15 ixDPCSSYS_CR2_RAWAONLANE3_DIG_RX_DCC_CAL_QDF_CODE_0 2 0x4340 2 0 4294967295 RX_DCC_CAL_QDF_CODE 0 9 RESERVED_15_10 10 15 ixDPCSSYS_CR2_RAWAONLANE3_DIG_RX_DCC_CAL_ICM_CODE_1 2 0x4341 2 0 4294967295 RX_DCC_CAL_ICM_CODE 0 9 RESERVED_15_10 10 15 ixDPCSSYS_CR2_RAWAONLANE3_DIG_RX_DCC_CAL_IDF_CODE_1 2 0x4342 2 0 4294967295 RX_DCC_CAL_IDF_CODE 0 9 RESERVED_15_10 10 15 ixDPCSSYS_CR2_RAWAONLANE3_DIG_RX_DCC_CAL_QCM_CODE_1 2 0x4343 2 0 4294967295 RX_DCC_CAL_QCM_CODE 0 9 RESERVED_15_10 10 15 ixDPCSSYS_CR2_RAWAONLANE3_DIG_RX_DCC_CAL_QDF_CODE_1 2 0x4344 2 0 4294967295 RX_DCC_CAL_QDF_CODE 0 9 RESERVED_15_10 10 15 ixDPCSSYS_CR2_RAWAONLANE3_DIG_TX_DCC_BANK_ADDR 2 0x4345 1 0 4294967295 ADDR 0 15 ixDPCSSYS_CR2_RAWAONLANE3_DIG_TX_DCC_BANK_DATA 2 0x4346 1 0 4294967295 DATA 0 15 ixDPCSSYS_CR2_RAWAONLANE3_DIG_TX_DCC_CONT 2 0x4347 2 0 4294967295 EN 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR2_RAWAONLANE3_DIG_MPLL_BG_CTL 2 0x4348 3 0 4294967295 MPLL_STATE_WAIT 0 0 MPLL_STATE_DLY_EN 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR2_RAWAONLANE3_DIG_SIGDET_OUT_OVRD 2 0x4349 5 0 4294967295 RX_SIGDET_HF_OUT_OVRD_VAL 0 0 RX_SIGDET_HF_OUT_OVRD_EN 1 1 RX_SIGDET_LF_OUT_OVRD_VAL 2 2 RX_SIGDET_LF_OUT_OVRD_EN 3 3 RESERVED_15_4 4 15 ixDPCSSYS_CR2_RAWAONLANE3_DIG_SIGDET_OUT_IN 2 0x434a 3 0 4294967295 RX_SIGDET_HF_OUT_OVRD_VAL 0 0 RX_SIGDET_LF_OUT_OVRD_VAL 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR2_RAWAONLANE3_DIG_FW_MM_CONFIG 2 0x434b 1 0 4294967295 DATA 0 0 ixDPCSSYS_CR2_RAWAONLANE3_DIG_FW_ADPT_CONFIG 2 0x434c 2 0 4294967295 REF_LVL_ADPT 0 7 FW_CONFIG 8 15 ixDPCSSYS_CR2_RAWAONLANE3_DIG_FW_CALIB_CONFIG 2 0x434d 1 0 4294967295 FW_CALIB 0 15 ixDPCSSYS_CR2_RAWAONLANE3_DIG_LANE_XCVR_MODE_OVRD_IN 2 0x434e 3 0 4294967295 LANE_XCVR_MODE_OVRD_VAL 0 1 LANE_XCVR_MODE_OVRD_EN 2 2 RESERVED_15_3 3 15 ixDPCSSYS_CR2_RAWAONLANE3_DIG_LANE_XCVR_MODE_IN 2 0x434f 2 0 4294967295 LANE_XCVR_MODE 0 1 RESERVED_15_2 2 15 ixDPCSSYS_CR2_RAWAONLANE3_DIG_RX_SIGDET_CONFIG 2 0x4350 4 0 4294967295 RX_SIGDET_HF_FILTER_COUNTER 0 4 RX_SIGDET_LF_FILTER_COUNTER 5 9 RX_SIGDET_LF_HOLD 10 10 RESERVED_15_11 11 15 ixDPCSSYS_CR2_RAWAONLANE3_DIG_TX_DCC_CONFIG 2 0x4351 1 0 4294967295 DATA 0 0 ixDPCSSYS_CR2_RAWAONLANEX_DIG_AFE_ATT_IDAC_OFST 2 0x7000 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR2_RAWAONLANEX_DIG_AFE_CTLE_IDAC_OFST 2 0x7001 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR2_RAWAONLANEX_DIG_RX_ADPT_IQ 2 0x7002 2 0 4294967295 IQ_ADPT_VAL 0 6 RESERVED_15_7 7 15 ixDPCSSYS_CR2_RAWAONLANEX_DIG_RX_ADAPT_FOM 2 0x7003 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR2_RAWAONLANEX_DIG_DFE_SUMMER_ODD_IDAC_OFST 2 0x7004 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR2_RAWAONLANEX_DIG_DFE_PHASE_EVEN_VDAC_OFST 2 0x7005 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR2_RAWAONLANEX_DIG_DFE_PHASE_ODD_VDAC_OFST 2 0x7006 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR2_RAWAONLANEX_DIG_DFE_EVEN_REF_LVL 2 0x7007 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR2_RAWAONLANEX_DIG_DFE_ODD_REF_LVL 2 0x7008 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR2_RAWAONLANEX_DIG_RX_PHSADJ_LIN 2 0x7009 2 0 4294967295 DATA 0 0 RESERVED_15_5 5 15 ixDPCSSYS_CR2_RAWAONLANEX_DIG_RX_PHSADJ_MAP 2 0x700a 2 0 4294967295 DATA 0 0 RESERVED_15_5 5 15 ixDPCSSYS_CR2_RAWAONLANEX_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST 2 0x700b 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR2_RAWAONLANEX_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST 2 0x700c 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR2_RAWAONLANEX_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST 2 0x700d 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR2_RAWAONLANEX_DIG_DFE_DATA_ODD_LOW_VDAC_OFST 2 0x700e 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR2_RAWAONLANEX_DIG_DFE_BYPASS_EVEN_VDAC_OFST 2 0x700f 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR2_RAWAONLANEX_DIG_DFE_BYPASS_ODD_VDAC_OFST 2 0x7010 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR2_RAWAONLANEX_DIG_DFE_ERROR_EVEN_VDAC_OFST 2 0x7011 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR2_RAWAONLANEX_DIG_DFE_ERROR_ODD_VDAC_OFST 2 0x7012 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR2_RAWAONLANEX_DIG_RX_IQ_PHASE_ADJUST 2 0x7013 2 0 4294967295 DATA 0 0 RESERVED_15_7 7 15 ixDPCSSYS_CR2_RAWAONLANEX_DIG_MPLLA_COARSE_TUNE 2 0x7014 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR2_RAWAONLANEX_DIG_MPLLB_COARSE_TUNE 2 0x7015 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR2_RAWAONLANEX_DIG_INIT_PWRUP_DONE 2 0x7016 3 0 4294967295 DATA 0 0 PH2_PWRUP_DONE 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR2_RAWAONLANEX_DIG_RX_ADPT_ATT 2 0x7017 2 0 4294967295 ATT_ADPT_VAL 0 7 RESERVED_15_8 8 15 ixDPCSSYS_CR2_RAWAONLANEX_DIG_RX_ADPT_VGA 2 0x7018 2 0 4294967295 VGA_ADPT_VAL 0 9 RESERVED_15_10 10 15 ixDPCSSYS_CR2_RAWAONLANEX_DIG_RX_ADPT_CTLE 2 0x7019 3 0 4294967295 CTLE_BOOST_ADPT_VAL 0 9 CTLE_POLE_ADPT_VAL 10 12 RESERVED_15_13 13 15 ixDPCSSYS_CR2_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP1 2 0x701a 2 0 4294967295 DFE_TAP1_ADPT_VAL 0 12 RESERVED_15_13 13 15 ixDPCSSYS_CR2_RAWAONLANEX_DIG_RX_ADAPT_DONE 2 0x701b 2 0 4294967295 DATA 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR2_RAWAONLANEX_DIG_FAST_FLAGS 2 0x701c 16 0 4294967295 FAST_RX_STARTUP_CAL 0 0 FAST_RX_ADAPT 1 1 FAST_RX_AFE_CAL 2 2 FAST_RX_DFE_CAL 3 3 FAST_RX_BYPASS_CAL 4 4 FAST_RX_REFLVL_CAL 5 5 FAST_RX_IQ_CAL 6 6 FAST_RX_AFE_ADAPT 7 7 FAST_RX_DFE_ADAPT 8 8 FAST_SUP 9 9 FAST_TX_CMN_MODE 10 10 FAST_TX_RXDET 11 11 FAST_RX_PWRUP 12 12 FAST_RX_VCO_WAIT 13 13 FAST_RX_VCO_CAL 14 14 RESERVED_15_15 15 15 ixDPCSSYS_CR2_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP2 2 0x701d 2 0 4294967295 DFE_TAP2_ADPT_VAL 0 11 RESERVED_15_12 12 15 ixDPCSSYS_CR2_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP3 2 0x701e 2 0 4294967295 DFE_TAP3_ADPT_VAL 0 11 RESERVED_15_12 12 15 ixDPCSSYS_CR2_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP4 2 0x701f 2 0 4294967295 DFE_TAP4_ADPT_VAL 0 11 RESERVED_15_12 12 15 ixDPCSSYS_CR2_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP5 2 0x7020 2 0 4294967295 DFE_TAP5_ADPT_VAL 0 11 RESERVED_15_12 12 15 ixDPCSSYS_CR2_RAWAONLANEX_DIG_RX_SLICER_CTRL_EVEN 2 0x7021 2 0 4294967295 RX_ANA_SLICER_CTRL_E 0 3 RESERVED_15_4 4 15 ixDPCSSYS_CR2_RAWAONLANEX_DIG_RX_SLICER_CTRL_ODD 2 0x7022 2 0 4294967295 RX_ANA_SLICER_CTRL_O 0 3 RESERVED_15_4 4 15 ixDPCSSYS_CR2_RAWAONLANEX_DIG_LANE_CMNCAL_MPLL_STATUS 2 0x7023 3 0 4294967295 LANE_CMNCAL_MPLL_INIT 0 0 LANE_CMNCAL_MPLL_DONE 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR2_RAWAONLANEX_DIG_ADPT_CTL_0 2 0x7024 1 0 4294967295 VAL 0 15 ixDPCSSYS_CR2_RAWAONLANEX_DIG_ADPT_CTL_1 2 0x7025 1 0 4294967295 VAL 0 15 ixDPCSSYS_CR2_RAWAONLANEX_DIG_ADPT_CTL_2 2 0x7026 1 0 4294967295 VAL 0 15 ixDPCSSYS_CR2_RAWAONLANEX_DIG_ADPT_CTL_3 2 0x7027 1 0 4294967295 VAL 0 15 ixDPCSSYS_CR2_RAWAONLANEX_DIG_ADPT_CTL_4 2 0x7028 1 0 4294967295 VAL 0 15 ixDPCSSYS_CR2_RAWAONLANEX_DIG_ADPT_CTL_5 2 0x7029 1 0 4294967295 VAL 0 15 ixDPCSSYS_CR2_RAWAONLANEX_DIG_ADPT_CTL_6 2 0x702a 1 0 4294967295 VAL 0 15 ixDPCSSYS_CR2_RAWAONLANEX_DIG_ADPT_CTL_7 2 0x702b 1 0 4294967295 VAL 0 15 ixDPCSSYS_CR2_RAWAONLANEX_DIG_MPLL_DISABLE 2 0x702c 3 0 4294967295 LANE_MPLLA_DISABLE 0 0 LANE_MPLLB_DISABLE 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR2_RAWAONLANEX_DIG_FAST_FLAGS_2 2 0x702d 16 0 4294967295 FAST_RX_CONT_CAL_ADAPT 0 0 FAST_RX_CONT_ADAPT 1 1 FAST_RX_CONT_DATA_CAL 2 2 FAST_RX_CONT_PHASE_CAL 3 3 FAST_RX_CONT_AFE_CAL 4 4 FAST_TX_CONT_DCC_CAL 5 5 FAST_RX_CONT_DCC_CAL 6 6 FAST_RX_CONT_VPHUD_CAL 7 7 FAST_RX_CONT_VREF_CAL 8 8 FAST_TX_DCC_CAL 9 9 FAST_RX_DCC_CAL 10 10 FAST_RX_VPHUD_CAL 11 11 FAST_RX_VREF_CAL 12 12 SKIP_TX_RTUNE_CAL 13 13 FAST_RX_SIGDET_CAL 14 14 RESERVED_15_15 15 15 ixDPCSSYS_CR2_RAWAONLANEX_DIG_LANE_CMNCAL_RCAL_STATUS 2 0x702e 3 0 4294967295 LANE_CMNCAL_RCAL_INIT 0 0 LANE_CMNCAL_RCAL_DONE 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR2_RAWAONLANEX_DIG_TXRX_OVRD_IN 2 0x702f 5 0 4294967295 RX_DISABLE_OVRD_VAL 0 0 RX_DISABLE_OVRD_EN 1 1 TX_DISABLE_OVRD_VAL 2 2 TX_DISABLE_OVRD_EN 3 3 RESERVED_15_4 4 15 ixDPCSSYS_CR2_RAWAONLANEX_DIG_RX_LOS_MASK_CTL 2 0x7030 2 0 4294967295 RX_LOS_MASK_CNT 0 8 RESERVED_15_9 9 15 ixDPCSSYS_CR2_RAWAONLANEX_DIG_RX_SIGDET_FILT_CTRL 2 0x7031 5 0 4294967295 ISOLATE_SIGDET_HF 0 0 RX_SIGDEF_HF_FILT_OVR_DIS 1 1 RX_SIGDEF_HF_FILT_OVR 2 2 RX_SIGDET_LF_OUT_FILT_EN 3 3 RESERVED_15_4 4 15 ixDPCSSYS_CR2_RAWAONLANEX_DIG_STATS 2 0x7032 3 0 4294967295 RX_VREFGEN_MASTER 0 0 RX_PMA_SQ_OUT 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR2_RAWAONLANEX_DIG_RX_OVRD_OUT_1 2 0x7033 11 0 4294967295 RX_PMA_SQ_CTRL_TRESH_OVRD_VAL 0 2 RX_PMA_SQ_CTRL_TRESH_OVRD_EN 3 3 RX_PMA_SQ_CTRL_RESP_OVRD_VAL 4 5 RX_PMA_SQ_CTRL_RESP_OVRD_EN 6 6 RX_PMA_SQ_WEAKKEEP_OVRD_VAL 7 7 RX_PMA_SQ_WEAKKEEP_OVRD_EN 8 8 RX_PMA_SQ_INV_POLARITY_OVRD_VAL 9 9 RX_PMA_SQ_INV_POLARITY_OVRD_EN 10 10 RX_PMA_SQ_EN_OVRD_VAL 11 11 RX_PMA_SQ_EN_OVRD_EN 12 12 RESERVED_15_13 13 15 ixDPCSSYS_CR2_RAWAONLANEX_DIG_RX_OVRD_OUT_2 2 0x7034 9 0 4294967295 RX_PMA_VREFGEN_EN_OVRD_VAL 0 0 RX_PMA_VREFGEN_EN_OVRD_EN 1 1 RX_SQ_OUT_OVRD_VAL 2 2 RX_SQ_OUT_OVRD_EN 3 3 RX_PMA_TERM_ACDC_OVRD_VAL 4 4 RX_PMA_TERM_ACDC_OVRD_EN 5 5 RX_PMA_TERM_EN_OVRD_VAL 6 6 RX_PMA_TERM_EN_OVRD_EN 7 7 RESERVED_15_8 8 15 ixDPCSSYS_CR2_RAWAONLANEX_DIG_RX_OVRD_OUT_3 2 0x7035 7 0 4294967295 RX_PMA_SIGDET_LF_FILTER_EN_OVRD_VAL 0 0 RX_PMA_SIGDET_LF_FILTER_EN_OVRD_EN 1 1 RX_PMA_SIGDET_LF_EN_OVRD_VAL 2 2 RX_PMA_SIGDET_LF_EN_OVRD_EN 3 3 RX_PMA_SIGDET_HF_EN_OVRD_VAL 4 4 RX_PMA_SIGDET_HF_EN_OVRD_EN 5 5 RESERVED_15_6 6 15 ixDPCSSYS_CR2_RAWAONLANEX_DIG_RX_SIGDET_CAL 2 0x7036 4 0 4294967295 RX_PMA_SIGDET_LF_THRESHOLD 0 2 RX_PMA_SIGDET_HF_THRESHOLD 3 5 RX_PMA_SIGDET_CAL_EN 6 6 RESERVED_15_7 7 15 ixDPCSSYS_CR2_RAWAONLANEX_DIG_RX_SIGDET_HF_CODE 2 0x7037 2 0 4294967295 RX_PMA_SIGDET_HF_CAL_TUNE 0 5 RESERVED_15_6 6 15 ixDPCSSYS_CR2_RAWAONLANEX_DIG_RX_SIGDET_LF_CODE 2 0x7038 2 0 4294967295 RX_PMA_SIGDET_LF_CAL_TUNE 0 5 RESERVED_15_6 6 15 ixDPCSSYS_CR2_RAWAONLANEX_DIG_RX_VREFGEN_EN 2 0x7039 2 0 4294967295 PULL_UP 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR2_RAWAONLANEX_DIG_CAL_IOFF_CODE 2 0x703a 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR2_RAWAONLANEX_DIG_CAL_ICONST_CODE 2 0x703b 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR2_RAWAONLANEX_DIG_CAL_VREFGEN_CODE 2 0x703c 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR2_RAWAONLANEX_DIG_RX_DCC_CAL_ICM_CODE_0 2 0x703d 2 0 4294967295 RX_DCC_CAL_ICM_CODE 0 9 RESERVED_15_10 10 15 ixDPCSSYS_CR2_RAWAONLANEX_DIG_RX_DCC_CAL_IDF_CODE_0 2 0x703e 2 0 4294967295 RX_DCC_CAL_IDF_CODE 0 9 RESERVED_15_10 10 15 ixDPCSSYS_CR2_RAWAONLANEX_DIG_RX_DCC_CAL_QCM_CODE_0 2 0x703f 2 0 4294967295 RX_DCC_CAL_QCM_CODE 0 9 RESERVED_15_10 10 15 ixDPCSSYS_CR2_RAWAONLANEX_DIG_RX_DCC_CAL_QDF_CODE_0 2 0x7040 2 0 4294967295 RX_DCC_CAL_QDF_CODE 0 9 RESERVED_15_10 10 15 ixDPCSSYS_CR2_RAWAONLANEX_DIG_RX_DCC_CAL_ICM_CODE_1 2 0x7041 2 0 4294967295 RX_DCC_CAL_ICM_CODE 0 9 RESERVED_15_10 10 15 ixDPCSSYS_CR2_RAWAONLANEX_DIG_RX_DCC_CAL_IDF_CODE_1 2 0x7042 2 0 4294967295 RX_DCC_CAL_IDF_CODE 0 9 RESERVED_15_10 10 15 ixDPCSSYS_CR2_RAWAONLANEX_DIG_RX_DCC_CAL_QCM_CODE_1 2 0x7043 2 0 4294967295 RX_DCC_CAL_QCM_CODE 0 9 RESERVED_15_10 10 15 ixDPCSSYS_CR2_RAWAONLANEX_DIG_RX_DCC_CAL_QDF_CODE_1 2 0x7044 2 0 4294967295 RX_DCC_CAL_QDF_CODE 0 9 RESERVED_15_10 10 15 ixDPCSSYS_CR2_RAWAONLANEX_DIG_TX_DCC_BANK_ADDR 2 0x7045 1 0 4294967295 ADDR 0 15 ixDPCSSYS_CR2_RAWAONLANEX_DIG_TX_DCC_BANK_DATA 2 0x7046 1 0 4294967295 DATA 0 15 ixDPCSSYS_CR2_RAWAONLANEX_DIG_TX_DCC_CONT 2 0x7047 2 0 4294967295 EN 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR2_RAWAONLANEX_DIG_MPLL_BG_CTL 2 0x7048 3 0 4294967295 MPLL_STATE_WAIT 0 0 MPLL_STATE_DLY_EN 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR2_RAWAONLANEX_DIG_SIGDET_OUT_OVRD 2 0x7049 5 0 4294967295 RX_SIGDET_HF_OUT_OVRD_VAL 0 0 RX_SIGDET_HF_OUT_OVRD_EN 1 1 RX_SIGDET_LF_OUT_OVRD_VAL 2 2 RX_SIGDET_LF_OUT_OVRD_EN 3 3 RESERVED_15_4 4 15 ixDPCSSYS_CR2_RAWAONLANEX_DIG_SIGDET_OUT_IN 2 0x704a 3 0 4294967295 RX_SIGDET_HF_OUT_OVRD_VAL 0 0 RX_SIGDET_LF_OUT_OVRD_VAL 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR2_RAWAONLANEX_DIG_FW_MM_CONFIG 2 0x704b 1 0 4294967295 DATA 0 0 ixDPCSSYS_CR2_RAWAONLANEX_DIG_FW_ADPT_CONFIG 2 0x704c 2 0 4294967295 REF_LVL_ADPT 0 7 FW_CONFIG 8 15 ixDPCSSYS_CR2_RAWAONLANEX_DIG_FW_CALIB_CONFIG 2 0x704d 1 0 4294967295 FW_CALIB 0 15 ixDPCSSYS_CR2_RAWAONLANEX_DIG_LANE_XCVR_MODE_OVRD_IN 2 0x704e 3 0 4294967295 LANE_XCVR_MODE_OVRD_VAL 0 1 LANE_XCVR_MODE_OVRD_EN 2 2 RESERVED_15_3 3 15 ixDPCSSYS_CR2_RAWAONLANEX_DIG_LANE_XCVR_MODE_IN 2 0x704f 2 0 4294967295 LANE_XCVR_MODE 0 1 RESERVED_15_2 2 15 ixDPCSSYS_CR2_RAWAONLANEX_DIG_RX_SIGDET_CONFIG 2 0x7050 4 0 4294967295 RX_SIGDET_HF_FILTER_COUNTER 0 4 RX_SIGDET_LF_FILTER_COUNTER 5 9 RX_SIGDET_LF_HOLD 10 10 RESERVED_15_11 11 15 ixDPCSSYS_CR2_RAWAONLANEX_DIG_TX_DCC_CONFIG 2 0x7051 1 0 4294967295 DATA 0 0 ixDPCSSYS_CR2_SUPX_DIG_IDCODE_LO 2 0x8000 1 0 4294967295 DATA 0 0 ixDPCSSYS_CR2_SUPX_DIG_IDCODE_HI 2 0x8001 1 0 4294967295 DATA 0 0 ixDPCSSYS_CR2_SUPX_DIG_REFCLK_OVRD_IN 2 0x8002 12 0 4294967295 REF_CLK_EN 0 0 REF_CLK_EN_OVRD_EN 1 1 REF_USE_PAD 2 2 REF_USE_PAD_OVRD_EN 3 3 REF_CLK_RANGE 4 8 REF_CLK_RANGE_OVRD_EN 9 9 BG_EN 10 10 BG_EN_OVRD_EN 11 11 HDMIMODE_EN 12 12 HDMIMODE_ENABLE_OVRD_EN 13 13 SUP_PRE_HP_OVRD 14 14 SUP_PRE_HP_OVRD_EN 15 15 ixDPCSSYS_CR2_SUPX_DIG_MPLLA_DIV_CLK_OVRD_IN 2 0x8003 4 0 4294967295 MPLLA_DIV_CLK_EN 0 0 MPLLA_DIV_MULTIPLIER 1 8 MPLLA_DIV_OVRD_EN 9 9 RESERVED_15_10 10 15 ixDPCSSYS_CR2_SUPX_DIG_MPLLA_HDMI_CLK_OVRD_IN 2 0x8004 4 0 4294967295 MPLLA_HDMI_PIXEL_CLK_DIV 0 1 MPLLA_HDMI_DIV 2 4 MPLLA_HDMI_OVRD_EN 5 5 RESERVED_15_6 6 15 ixDPCSSYS_CR2_SUPX_DIG_MPLLB_DIV_CLK_OVRD_IN 2 0x8005 4 0 4294967295 MPLLB_DIV_CLK_EN 0 0 MPLLB_DIV_MULTIPLIER 1 8 MPLLB_DIV_OVRD_EN 9 9 RESERVED_15_10 10 15 ixDPCSSYS_CR2_SUPX_DIG_MPLLB_HDMI_CLK_OVRD_IN 2 0x8006 4 0 4294967295 MPLLB_HDMI_PIXEL_CLK_DIV 0 1 MPLLB_HDMI_DIV 2 4 MPLLB_HDMI_OVRD_EN 5 5 RESERVED_15_6 6 15 ixDPCSSYS_CR2_SUPX_DIG_MPLLA_OVRD_IN_0 2 0x8007 12 0 4294967295 MPLLA_EN 0 0 MPLLA_DIV5_CLK_EN 1 1 MPLLA_TX_CLK_DIV 2 4 OVRD_EN 5 5 MPLLA_V2I 6 7 MPLLA_STANDBY 8 8 MPLLA_FREQ_VCO 9 10 MPLLA_CAL_FORCE 11 11 MPLL_FRACN_EN 12 12 MPLLA_CLK_SYNC_OVRD 13 13 MPLLA_CLK_SYNC_OVRD_EN 14 14 RESERVED_15_15 15 15 ixDPCSSYS_CR2_SUPX_DIG_MPLLA_OVRD_IN_1 2 0x8008 2 0 4294967295 MPLLA_MULTIPLIER 0 11 RESERVED_15_12 12 15 ixDPCSSYS_CR2_SUPX_DIG_MPLLA_OVRD_IN_2 2 0x8009 7 0 4294967295 MPLLA_SSC_EN 0 0 MPLLA_SSC_OVRD_EN 1 1 MPLLA_SSC_UP_SPREAD 2 2 MPLLA_PMIX_EN 3 3 MPLLA_WORD_DIV2_EN 4 4 MPLLA_FRACN_CFG_UPDATE_EN 5 5 RESERVED_15_6 6 15 ixDPCSSYS_CR2_SUPX_DIG_MPLLA_SSC_PEAK_1 2 0x800a 1 0 4294967295 MPLLA_SSC_PEAK_15_0 0 15 ixDPCSSYS_CR2_SUPX_DIG_MPLLA_SSC_PEAK_2 2 0x800b 2 0 4294967295 MPLLA_SSC_PEAK_19_16 0 3 RESERVED_15_4 4 15 ixDPCSSYS_CR2_SUPX_DIG_MPLLA_SSC_STEPSIZE_1 2 0x800c 1 0 4294967295 MPLLA_SSC_STEPSIZE_15_0 0 15 ixDPCSSYS_CR2_SUPX_DIG_MPLLA_SSC_STEPSIZE_2 2 0x800d 2 0 4294967295 MPLLA_SSC_STEPSIZE_20_16 0 4 RESERVED_15_5 5 15 ixDPCSSYS_CR2_SUPX_DIG_MPLLA_OVRD_IN_3 2 0x800e 1 0 4294967295 MPLLA_FRACN_QUOT 0 15 ixDPCSSYS_CR2_SUPX_DIG_MPLLA_OVRD_IN_4 2 0x800f 1 0 4294967295 MPLLA_FRACN_REM 0 15 ixDPCSSYS_CR2_SUPX_DIG_MPLLA_OVRD_IN_5 2 0x8010 1 0 4294967295 MPLLA_FRACN_DEN 0 15 ixDPCSSYS_CR2_SUPX_DIG_MPLLA_CP_OVRD_IN 2 0x8011 3 0 4294967295 MPLLA_CP_PROP 0 6 MPLLA_CP_INT 7 13 RESERVED_15_14 14 15 ixDPCSSYS_CR2_SUPX_DIG_MPLLA_CP_GS_OVRD_IN 2 0x8012 4 0 4294967295 MPLLA_CP_PROP_GS 0 6 MPLLA_CP_PROP_GS_OVR_EN 7 7 MPLLA_CP_INT_GS 8 14 MPLLA_CP_INT_GS_OVR_EN 15 15 ixDPCSSYS_CR2_SUPX_DIG_MPLLB_OVRD_IN_0 2 0x8013 12 0 4294967295 MPLLB_EN 0 0 MPLLB_DIV5_CLK_EN 1 1 MPLLB_TX_CLK_DIV 2 4 OVRD_EN 5 5 MPLLB_V2I 6 7 MPLLB_STANDBY 8 8 MPLLB_FREQ_VCO 9 10 MPLLB_CAL_FORCE 11 11 MPLL_FRACN_EN 12 12 MPLLB_CLK_SYNC_OVRD 13 13 MPLLB_CLK_SYNC_OVRD_EN 14 14 RESERVED_15_15 15 15 ixDPCSSYS_CR2_SUPX_DIG_MPLLB_OVRD_IN_1 2 0x8014 2 0 4294967295 MPLLB_MULTIPLIER 0 11 RESERVED_15_12 12 15 ixDPCSSYS_CR2_SUPX_DIG_MPLLB_OVRD_IN_2 2 0x8015 7 0 4294967295 MPLLB_SSC_EN 0 0 MPLLB_SSC_OVRD_EN 1 1 MPLLB_SSC_UP_SPREAD 2 2 MPLLB_PMIX_EN 3 3 MPLLB_WORD_DIV2_EN 4 4 MPLLB_FRACN_CFG_UPDATE_EN 5 5 RESERVED_15_6 6 15 ixDPCSSYS_CR2_SUPX_DIG_MPLLB_SSC_PEAK_1 2 0x8016 1 0 4294967295 MPLLB_SSC_PEAK_15_0 0 15 ixDPCSSYS_CR2_SUPX_DIG_MPLLB_SSC_PEAK_2 2 0x8017 2 0 4294967295 MPLLB_SSC_PEAK_19_16 0 3 RESERVED_15_4 4 15 ixDPCSSYS_CR2_SUPX_DIG_MPLLB_SSC_STEPSIZE_1 2 0x8018 1 0 4294967295 MPLLB_SSC_STEPSIZE_15_0 0 15 ixDPCSSYS_CR2_SUPX_DIG_MPLLB_SSC_STEPSIZE_2 2 0x8019 2 0 4294967295 MPLLB_SSC_STEPSIZE_20_16 0 4 RESERVED_15_5 5 15 ixDPCSSYS_CR2_SUPX_DIG_MPLLB_OVRD_IN_3 2 0x801a 1 0 4294967295 MPLLB_FRACN_QUOT 0 15 ixDPCSSYS_CR2_SUPX_DIG_MPLLB_OVRD_IN_4 2 0x801b 1 0 4294967295 MPLLB_FRACN_REM 0 15 ixDPCSSYS_CR2_SUPX_DIG_MPLLB_OVRD_IN_5 2 0x801c 1 0 4294967295 MPLLB_FRACN_DEN 0 15 ixDPCSSYS_CR2_SUPX_DIG_MPLLB_CP_OVRD_IN 2 0x801d 3 0 4294967295 MPLLB_CP_PROP 0 6 MPLLB_CP_INT 7 13 RESERVED_15_14 14 15 ixDPCSSYS_CR2_SUPX_DIG_MPLLB_CP_GS_OVRD_IN 2 0x801e 4 0 4294967295 MPLLB_CP_PROP_GS 0 6 MPLLB_CP_PROP_GS_OVR_EN 7 7 MPLLB_CP_INT_GS 8 14 MPLLB_CP_INT_GS_OVR_EN 15 15 ixDPCSSYS_CR2_SUPX_DIG_SUP_OVRD_IN 2 0x801f 8 0 4294967295 PRESCALER_OVRD_EN 0 0 RTUNE_REQ 1 1 RTUNE_OVRD_EN 2 2 TX_CAL_CODE 3 6 TX_CAL_CODE_EN 7 7 REF_ALT_CLK_LP_SEL_OVRD 8 8 REF_ALT_CLK_LP_SEL_OVRD_EN 9 9 RESERVED_15_10 10 15 ixDPCSSYS_CR2_SUPX_DIG_PRESCALER_OVRD_IN 2 0x8020 6 0 4294967295 DCO_RANGE 0 1 DCO_FINETUNE 2 7 REF_CLK_MPLLB_DIV 8 10 REF_CLK_MPLLA_DIV 11 13 REF_CLKDET_RESULT 14 14 REF_CLKDET_EN 15 15 ixDPCSSYS_CR2_SUPX_DIG_SUP_OVRD_OUT 2 0x8021 12 0 4294967295 RTUNE_ACK 0 0 RTUNE_ACK_OVRD_EN 1 1 MPLLA_STATE 2 2 MPLLA_STATE_OVRD_EN 3 3 MPLLB_STATE 4 4 MPLLB_STATE_OVRD_EN 5 5 BG_LANE_STATE 6 6 BG_LANE_STATE_OVRD_EN 7 7 BG_SUP_STATE 8 8 BG_SUP_STATE_OVRD_EN 9 9 REF_CLK_ACK 10 10 RESERVED_15_11 11 15 ixDPCSSYS_CR2_SUPX_DIG_LVL_OVRD_IN 2 0x8022 7 0 4294967295 RX_VREF_CTRL 0 2 RX_VREF_CTRL_EN 3 3 TX_VBOOST_LVL 4 6 TX_VBOOST_LVL_EN 7 7 SUP_RX_VCO_VREF_SEL_OVR 8 10 SUP_RX_VCO_VREF_SEL_OVR_EN 11 11 RESERVED_15_12 12 15 ixDPCSSYS_CR2_SUPX_DIG_MPLLA_ASIC_IN_0 2 0x8024 9 0 4294967295 MPLLA_EN 0 0 MPLLA_DIV5_CLK_EN 1 1 MPLLA_TX_CLK_DIV 2 4 MPLLA_V2I 5 6 MPLLA_STANDBY 7 7 MPLLA_FREQ_VCO 8 9 MPLLA_CAL_FORCE 10 10 MPLLA_FRACN_EN 11 11 RESERVED_15_12 12 15 ixDPCSSYS_CR2_SUPX_DIG_MPLLA_ASIC_IN_1 2 0x8025 2 0 4294967295 MPLLA_MULTIPLIER 0 11 RESERVED_15_12 12 15 ixDPCSSYS_CR2_SUPX_DIG_MPLLA_ASIC_IN_2 2 0x8026 7 0 4294967295 MPLLA_SSC_EN 0 0 MPLLA_SSC_UP_SPREAD 1 1 MPLLA_PMIX_EN 2 2 MPLLA_WORD_DIV2_EN 3 3 MPLLA_FRACN_CFG_UPDATE_EN 4 4 MPLLA_CLK_SYNC 5 5 RESERVED_15_6 6 15 ixDPCSSYS_CR2_SUPX_DIG_MPLLA_ASIC_IN_3 2 0x8027 1 0 4294967295 MPLLA_SSC_PEAK_15_0 0 15 ixDPCSSYS_CR2_SUPX_DIG_MPLLA_ASIC_IN_4 2 0x8028 2 0 4294967295 MPLLA_SSC_PEAK_19_16 0 3 RESERVED_15_4 4 15 ixDPCSSYS_CR2_SUPX_DIG_MPLLA_ASIC_IN_5 2 0x8029 1 0 4294967295 MPLLA_SSC_STEPSIZE_15_0 0 15 ixDPCSSYS_CR2_SUPX_DIG_MPLLA_ASIC_IN_6 2 0x802a 2 0 4294967295 MPLLA_SSC_STEPSIZE_20_16 0 3 RESERVED_15_4 4 15 ixDPCSSYS_CR2_SUPX_DIG_MPLLB_ASIC_IN_0 2 0x802b 9 0 4294967295 MPLLB_EN 0 0 MPLLB_DIV5_CLK_EN 1 1 MPLLB_TX_CLK_DIV 2 4 MPLLB_V2I 5 6 MPLLB_STANDBY 7 7 MPLLB_FREQ_VCO 8 9 MPLLB_CAL_FORCE 10 10 MPLLB_FRACN_EN 11 11 RESERVED_15_12 12 15 ixDPCSSYS_CR2_SUPX_DIG_MPLLB_ASIC_IN_1 2 0x802c 2 0 4294967295 MPLLB_MULTIPLIER 0 11 RESERVED_15_12 12 15 ixDPCSSYS_CR2_SUPX_DIG_MPLLB_ASIC_IN_2 2 0x802d 7 0 4294967295 MPLLB_SSC_EN 0 0 MPLLB_SSC_UP_SPREAD 1 1 MPLLB_PMIX_EN 2 2 MPLLB_WORD_DIV2_EN 3 3 MPLLB_FRACN_CFG_UPDATE_EN 4 4 MPLLB_CLK_SYNC 5 5 RESERVED_15_6 6 15 ixDPCSSYS_CR2_SUPX_DIG_MPLLB_ASIC_IN_3 2 0x802e 1 0 4294967295 MPLLB_SSC_PEAK_15_0 0 15 ixDPCSSYS_CR2_SUPX_DIG_MPLLB_ASIC_IN_4 2 0x802f 2 0 4294967295 MPLLB_SSC_PEAK_19_16 0 3 RESERVED_15_4 4 15 ixDPCSSYS_CR2_SUPX_DIG_MPLLB_ASIC_IN_5 2 0x8030 1 0 4294967295 MPLLB_SSC_STEPSIZE_15_0 0 15 ixDPCSSYS_CR2_SUPX_DIG_MPLLB_ASIC_IN_6 2 0x8031 2 0 4294967295 MPLLB_SSC_STEPSIZE_20_16 0 3 RESERVED_15_4 4 15 ixDPCSSYS_CR2_SUPX_DIG_MPLLA_DIV_CLK_ASIC_IN 2 0x8032 3 0 4294967295 MPLLA_DIV_CLK_EN 0 0 MPLLA_DIV_MULTIPLIER 1 8 RESERVED_15_9 9 15 ixDPCSSYS_CR2_SUPX_DIG_MPLLA_HDMI_CLK_ASIC_IN 2 0x8033 3 0 4294967295 MPLLA_HDMI_PIXEL_CLK_DIV 0 1 MPLLA_HDMI_DIV 2 4 RESERVED_15_5 5 15 ixDPCSSYS_CR2_SUPX_DIG_MPLLB_DIV_CLK_ASIC_IN 2 0x8034 3 0 4294967295 MPLLB_DIV_CLK_EN 0 0 MPLLB_DIV_MULTIPLIER 1 8 RESERVED_15_9 9 15 ixDPCSSYS_CR2_SUPX_DIG_MPLLB_HDMI_CLK_ASIC_IN 2 0x8035 3 0 4294967295 MPLLB_HDMI_PIXEL_CLK_DIV 0 1 MPLLB_HDMI_DIV 2 4 RESERVED_15_5 5 15 ixDPCSSYS_CR2_SUPX_DIG_ASIC_IN 2 0x8036 12 0 4294967295 PHY_RESET 0 0 REF_CLK_EN 1 1 REF_USE_PAD 2 2 TEST_BURNIN 3 3 TEST_POWERDOWN 4 4 RTUNE_REQ 5 5 RTUNE_ACK 6 6 MPLLA_STATE 7 7 MPLLB_STATE 8 8 TEST_TX_REF_CLK_EN 9 9 REF_ALT_CLK_LP_SEL 10 10 RESERVED_15_11 11 15 ixDPCSSYS_CR2_SUPX_DIG_LVL_ASIC_IN 2 0x8037 4 0 4294967295 RX_VREF_CTRL 0 2 TX_VBOOST_LVL 3 5 SUP_RX_VCO_VREF_SEL 6 8 RESERVED_15_9 9 15 ixDPCSSYS_CR2_SUPX_DIG_BANDGAP_ASIC_IN 2 0x8038 2 0 4294967295 BG_EN 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR2_SUPX_DIG_MPLLA_CP_ASIC_IN 2 0x8039 3 0 4294967295 MPLLA_CP_PROP 0 6 MPLLA_CP_INT 7 13 RESERVED_15_14 14 15 ixDPCSSYS_CR2_SUPX_DIG_MPLLA_CP_GS_ASIC_IN 2 0x803a 3 0 4294967295 MPLLA_CP_PROP_GS 0 6 MPLLA_CP_INT_GS 7 13 RESERVED_15_14 14 15 ixDPCSSYS_CR2_SUPX_DIG_MPLLB_CP_ASIC_IN 2 0x803b 3 0 4294967295 MPLLB_CP_PROP 0 6 MPLLB_CP_INT 7 13 RESERVED_15_14 14 15 ixDPCSSYS_CR2_SUPX_DIG_MPLLB_CP_GS_ASIC_IN 2 0x803c 3 0 4294967295 MPLLB_CP_PROP_GS 0 6 MPLLB_CP_INT_GS 7 13 RESERVED_15_14 14 15 ixDPCSSYS_CR2_SUPX_ANA_PRESCALER_CTRL 2 0x8040 7 0 4294967295 PSCALER_ATB_SELECT 0 0 PSCALER_MEAS_VREG 0 0 PSCALER_OVRD_FAST_START 0 0 PSCALER_FAST_START_REG 0 0 PSCALER_VREG_BOOST 0 0 PSCALER_HYST_REF 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR2_SUPX_ANA_RTUNE_CTRL 2 0x8041 9 0 4294967295 RT_ATB 0 0 RT_SEL_ATBF 0 0 RT_SEL_ATBP 0 0 RT_VP4O8_EN 0 0 RT_DAC_CHOP 0 0 RT_DAC_MODE 0 0 RT_EN_FRCON 0 0 PSCALER_VREG_FB_DIV_CTRL 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR2_SUPX_ANA_BG1 2 0x8042 6 0 4294967295 SUP_SEL_VBG_VREF 0 0 SUP_SEL_VPHUD_VREF 0 0 NC4 4 4 SUP_SEL_VPLL_REF 0 0 RT_VREF_SEL 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR2_SUPX_ANA_BG2 2 0x8043 9 0 4294967295 SUP_BYPASS_BG 0 0 SUP_CHOP_EN 0 0 SUP_TEMP_MEAS 0 0 VPHUD_SELREF 0 0 ATB_EXT_MEAS_EN 0 0 RT_TX_OFFSET_EN 0 0 SUP_SEL_TX_SWING_VREF 0 0 PSCALER_VREG_OVERRIDE_RING_CTRL 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR2_SUPX_ANA_SWITCH_PWR_MEAS 2 0x8044 3 0 4294967295 SUP_ATB_SW 0 0 SUP_TIE 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR2_SUPX_ANA_BG3 2 0x8045 4 0 4294967295 SUP_SEL_RX_VCO_TC_VREF 0 0 SUP_SEL_RX_CAL_VREF 0 0 NC7_4 4 7 RESERVED_15_8 8 15 ixDPCSSYS_CR2_SUPX_ANA_MPLLA_MISC1 2 0x8046 7 0 4294967295 OVRD_GEAR_RC_FILT 0 0 OVRD_TEST_RC_FILT 0 0 TEST_VREG_DIV 0 0 VBG_EN 0 0 COUNT_SEL_LOCK 0 0 PHASE_SEL_LOCK 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR2_SUPX_ANA_MPLLA_MISC2 2 0x8047 8 0 4294967295 OVRD_PR_BYPASS 0 0 PR_BYPASS 0 0 OVRD_GEARSHIFT 0 0 GEARSHIFT_REG 0 0 TEST_LOCK_GEAR 0 0 EN_CAL_SPO 0 0 TEST_BOOST 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR2_SUPX_ANA_MPLLA_OVRD 2 0x8048 9 0 4294967295 OVRD_ENABLE 0 0 ENABLE_REG 0 0 OVRD_CAL 0 0 CAL_REG 0 0 OVRD_FB_CLK_EN 0 0 FB_CLK_EN_REG 0 0 OVRD_RESET 0 0 RESET_REG 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR2_SUPX_ANA_MPLLA_ATB1 2 0x8049 3 0 4294967295 MEAS_IV_WRAP 0 0 ATB_SELECT 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR2_SUPX_ANA_MPLLA_ATB2 2 0x804a 2 0 4294967295 MEAS_IV_PLL 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR2_SUPX_ANA_MPLLA_ATB3 2 0x804b 3 0 4294967295 MEAS_IV_BIAS 0 0 CTR_UPLL_TUNNING 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR2_SUPX_ANA_MPLLA_CTR1 2 0x804c 5 0 4294967295 CTR_ICP_INT 0 0 CTR_VREF_EN 0 0 CTR_VREF_VMARG 0 0 CTR_CP_PLL 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR2_SUPX_ANA_MPLLA_CTR2 2 0x804d 2 0 4294967295 CTR_REGS_PLL 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR2_SUPX_ANA_MPLLA_CTR3 2 0x804e 4 0 4294967295 CTR_REGS_CP_PLL 0 0 CTR_SPO_PLL 0 0 CTR_VINT_CAP 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR2_SUPX_ANA_MPLLA_CTR4 2 0x804f 7 0 4294967295 CTR_CP_8X 0 0 CTR_FIL_REG 0 0 CTR_CP_PROP_REF 0 0 CTR_DOUBLER_GAIN 0 0 CTR_TEST_CASC 0 0 CTR_RC_FITER 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR2_SUPX_ANA_MPLLA_CTR5 2 0x8050 8 0 4294967295 CTR_STANDBY_MODE 0 0 CTR_LEG_SR_CON 0 0 CTR_VREG_RING_OVERRIDE 0 0 CTR_SPO_SPEED_OVERRIDE 0 0 CTR_BYPASS_LOCK_SPO_CAL 0 0 CTR_LOCK_SPO_CAL 0 0 CTR_UPLL_RESERVED 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR2_SUPX_ANA_MPLLA_RESERVED1 2 0x8051 8 0 4294967295 CTR_REF_FBK_BYPASS 0 0 CTR_BYPASS_TX 0 0 CTR_VREG_CLK_BYPASS 0 0 CTR_VREG_CLK_PMIX_BYPASS 0 0 CTR_VREG_RIGHT_BYPASS 0 0 CTR_VREG_LEFT_BYPASS 0 0 CTR_LEFT_RIGHT_GAIN 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR2_SUPX_ANA_MPLLA_RESERVED2 2 0x8052 5 0 4294967295 CTR_DLL_MODE_90 0 0 CTR_DLL_RESERVED 0 0 CTR_DIV24_DSQ_ENZ 0 0 CTR_DIV4 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR2_SUPX_ANA_MPLLB_MISC1 2 0x8053 7 0 4294967295 OVRD_GEAR_RC_FILT 0 0 OVRD_TEST_RC_FILT 0 0 TEST_VREG_DIV 0 0 VBG_EN 0 0 COUNT_SEL_LOCK 0 0 PHASE_SEL_LOCK 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR2_SUPX_ANA_MPLLB_MISC2 2 0x8054 8 0 4294967295 OVRD_PR_BYPASS 0 0 PR_BYPASS 0 0 OVRD_GEARSHIFT 0 0 GEARSHIFT_REG 0 0 TEST_LOCK_GEAR 0 0 EN_CAL_SPO 0 0 TEST_BOOST 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR2_SUPX_ANA_MPLLB_OVRD 2 0x8055 9 0 4294967295 OVRD_ENABLE 0 0 ENABLE_REG 0 0 OVRD_CAL 0 0 CAL_REG 0 0 OVRD_FB_CLK_EN 0 0 FB_CLK_EN_REG 0 0 OVRD_RESET 0 0 RESET_REG 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR2_SUPX_ANA_MPLLB_ATB1 2 0x8056 3 0 4294967295 MEAS_IV_WRAP 0 0 ATB_SELECT 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR2_SUPX_ANA_MPLLB_ATB2 2 0x8057 2 0 4294967295 MEAS_IV_PLL 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR2_SUPX_ANA_MPLLB_ATB3 2 0x8058 3 0 4294967295 MEAS_IV_BIAS 0 0 CTR_UPLL_TUNNING 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR2_SUPX_ANA_MPLLB_CTR1 2 0x8059 5 0 4294967295 CTR_ICP_INT 0 0 CTR_VREF_EN 0 0 CTR_VREF_VMARG 0 0 CTR_CP_PLL 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR2_SUPX_ANA_MPLLB_CTR2 2 0x805a 2 0 4294967295 CTR_REGS_PLL 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR2_SUPX_ANA_MPLLB_CTR3 2 0x805b 4 0 4294967295 CTR_REGS_CP_PLL 0 0 CTR_SPO_PLL 0 0 CTR_VINT_CAP 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR2_SUPX_ANA_MPLLB_CTR4 2 0x805c 7 0 4294967295 CTR_CP_8X 0 0 CTR_FIL_REG 0 0 CTR_CP_PROP_REF 0 0 CTR_DOUBLER_GAIN 0 0 CTR_TEST_CASC 0 0 CTR_RC_FITER 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR2_SUPX_ANA_MPLLB_CTR5 2 0x805d 8 0 4294967295 CTR_STANDBY_MODE 0 0 CTR_LEG_SR_CON 0 0 CTR_VREG_RING_OVERRIDE 0 0 CTR_SPO_SPEED_OVERRIDE 0 0 CTR_BYPASS_LOCK_SPO_CAL 0 0 CTR_LOCK_SPO_CAL 0 0 CTR_UPLL_RESERVED 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR2_SUPX_ANA_MPLLB_RESERVED1 2 0x805e 8 0 4294967295 CTR_REF_FBK_BYPASS 0 0 CTR_BYPASS_TX 0 0 CTR_VREG_CLK_BYPASS 0 0 CTR_VREG_CLK_PMIX_BYPASS 0 0 CTR_VREG_RIGHT_BYPASS 0 0 CTR_VREG_LEFT_BYPASS 0 0 CTR_LEFT_RIGHT_GAIN 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR2_SUPX_ANA_MPLLB_RESERVED2 2 0x805f 5 0 4294967295 CTR_DLL_MODE_90 0 0 CTR_DLL_RESERVED 0 0 CTR_DIV24_DSQ_ENZ 0 0 CTR_DIV4 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD 2 0x8061 8 0 4294967295 OVRD_SEL 0 0 MPLL_FBDIGCLK_EN 1 1 MPLL_PCLK_EN 2 2 FAST_MPLL_PWRUP 3 3 FAST_MPLL_LOCK 4 4 DTB_SEL 5 9 DIV10_EN 10 10 RESERVED 11 15 ixDPCSSYS_CR2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT 2 0x8062 11 0 4294967295 FSM_STATE 0 3 MPLL_R_LANES 4 4 MPLL_L_LANES 5 5 MPLL_PCLK_EN 6 6 MPLL_OUTPUT_EN 7 7 MPLL_FBCLK_EN 8 8 MPLL_CAL 9 9 MPLL_RST 10 10 MPLL_ANA_EN 11 11 MPLL_LOCK 12 12 RESERVED_15_13 13 15 ixDPCSSYS_CR2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE 2 0x8063 3 0 4294967295 MAX_RANGE 0 4 DAC_IN 5 9 RESERVED_15_10 10 15 ixDPCSSYS_CR2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_LOCK 2 0x8064 3 0 4294967295 LOCK_TIME 0 7 STABLE_TIME 8 13 RESERVED_15_14 14 15 ixDPCSSYS_CR2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS 2 0x8065 2 0 4294967295 GEARSHIFT_TIME 0 7 PRESET_TIME 8 15 ixDPCSSYS_CR2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE 2 0x8066 3 0 4294967295 PWRDN_WAIT_TIME 0 5 PCLK_EN_TIME 6 11 RESERVED_15_12 12 15 ixDPCSSYS_CR2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2 2 0x8067 3 0 4294967295 PCLK_DIS_TIME 0 5 PWRDN_TIME 6 11 RESERVED_15_12 12 15 ixDPCSSYS_CR2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_CAL 2 0x8068 3 0 4294967295 MPLL_CAL 0 0 MPLL_CAL_OVRD_EN 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT 2 0x8069 2 0 4294967295 MPLL_ANA_DAC_OUT 0 4 RESERVED_15_5 5 15 ixDPCSSYS_CR2_SUPX_DIG_MPLLA_SSC_GEN_SPREAD_TYPE 2 0x806b 3 0 4294967295 SPREAD_TYPE 0 1 OVR_EN 2 2 RESERVED_15_3 3 15 ixDPCSSYS_CR2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD 2 0x806d 8 0 4294967295 OVRD_SEL 0 0 MPLL_FBDIGCLK_EN 1 1 MPLL_PCLK_EN 2 2 FAST_MPLL_PWRUP 3 3 FAST_MPLL_LOCK 4 4 DTB_SEL 5 9 DIV10_EN 10 10 RESERVED 11 15 ixDPCSSYS_CR2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT 2 0x806e 11 0 4294967295 FSM_STATE 0 3 MPLL_R_LANES 4 4 MPLL_L_LANES 5 5 MPLL_PCLK_EN 6 6 MPLL_OUTPUT_EN 7 7 MPLL_FBCLK_EN 8 8 MPLL_CAL 9 9 MPLL_RST 10 10 MPLL_ANA_EN 11 11 MPLL_LOCK 12 12 RESERVED_15_13 13 15 ixDPCSSYS_CR2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE 2 0x806f 3 0 4294967295 MAX_RANGE 0 4 DAC_IN 5 9 RESERVED_15_10 10 15 ixDPCSSYS_CR2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_LOCK 2 0x8070 3 0 4294967295 LOCK_TIME 0 7 STABLE_TIME 8 13 RESERVED_15_14 14 15 ixDPCSSYS_CR2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS 2 0x8071 2 0 4294967295 GEARSHIFT_TIME 0 7 PRESET_TIME 8 15 ixDPCSSYS_CR2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE 2 0x8072 3 0 4294967295 PWRDN_WAIT_TIME 0 5 PCLK_EN_TIME 6 11 RESERVED_15_12 12 15 ixDPCSSYS_CR2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2 2 0x8073 3 0 4294967295 PCLK_DIS_TIME 0 5 PWRDN_TIME 6 11 RESERVED_15_12 12 15 ixDPCSSYS_CR2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_CAL 2 0x8074 3 0 4294967295 MPLL_CAL 0 0 MPLL_CAL_OVRD_EN 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT 2 0x8075 2 0 4294967295 MPLL_ANA_DAC_OUT 0 4 RESERVED_15_5 5 15 ixDPCSSYS_CR2_SUPX_DIG_MPLLB_SSC_GEN_SPREAD_TYPE 2 0x8077 3 0 4294967295 SPREAD_TYPE 0 1 OVR_EN 2 2 RESERVED_15_3 3 15 ixDPCSSYS_CR2_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_0 2 0x8078 3 0 4294967295 BG_SUP_EN_TIME 0 8 FAST_BG_WAIT 9 9 RESERVED_15_10 10 15 ixDPCSSYS_CR2_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_1 2 0x8079 2 0 4294967295 BG_LANE_EN_TIME 0 8 RESERVED_15_9 9 15 ixDPCSSYS_CR2_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_2 2 0x807a 3 0 4294967295 BG_KICK_START_EN_TIME 0 7 BG_SUP_STATE_UPD_EN 8 8 RESERVED_15_9 9 15 ixDPCSSYS_CR2_SUPX_DIG_CLK_RST_REF_PWRUP_TIME_0 2 0x807b 3 0 4294967295 REF_VREG_FAST_START_TIME 0 4 FAST_REF_WAIT 5 5 RESERVED_15_6 6 15 ixDPCSSYS_CR2_SUPX_DIG_CLK_RST_REF_VPHUD 2 0x807c 3 0 4294967295 SUP_ANA_VPHUD_SELVPH_I 0 0 SUP_ANA_VPHUD_EN_I 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR2_SUPX_DIG_RTUNE_CONFIG 2 0x8081 5 0 4294967295 RX_CAL_EN 0 0 FAST_RTUNE 1 1 TX_CAL_EN 2 2 SUP_ANA_TERM_CTRL 3 5 RESERVED_15_6 6 15 ixDPCSSYS_CR2_SUPX_DIG_RTUNE_STAT 2 0x8082 3 0 4294967295 STAT 0 9 DTB_RTUNE 10 11 RESERVED_15_12 12 15 ixDPCSSYS_CR2_SUPX_DIG_RTUNE_RX_SET_VAL 2 0x8083 2 0 4294967295 RX_SET_VAL 0 5 RESERVED_15_6 6 15 ixDPCSSYS_CR2_SUPX_DIG_RTUNE_TXDN_SET_VAL 2 0x8084 2 0 4294967295 TXDN_SET_VAL 0 9 RESERVED_15_10 10 15 ixDPCSSYS_CR2_SUPX_DIG_RTUNE_TXUP_SET_VAL 2 0x8085 2 0 4294967295 TXUP_SET_VAL 0 9 RESERVED_15_10 10 15 ixDPCSSYS_CR2_SUPX_DIG_RTUNE_RX_STAT 2 0x8086 2 0 4294967295 RX_STAT 0 5 RESERVED_15_6 6 15 ixDPCSSYS_CR2_SUPX_DIG_RTUNE_TXDN_STAT 2 0x8087 2 0 4294967295 TXDN_STAT 0 9 RESERVED_15_10 10 15 ixDPCSSYS_CR2_SUPX_DIG_RTUNE_TXUP_STAT 2 0x8088 2 0 4294967295 TXUP_STAT 0 9 RESERVED_15_10 10 15 ixDPCSSYS_CR2_SUPX_DIG_RTUNE_CONFIG_CNT0 2 0x8089 4 0 4294967295 RT_RESULT_TIME 0 3 RT_EVAL_TIME 4 7 RT_RST_TIME 8 11 RT_ACK_TIME 12 15 ixDPCSSYS_CR2_SUPX_DIG_RTUNE_CONFIG_CNT1 2 0x808a 3 0 4294967295 RT_TXDN_SETTLE_TIME 0 3 RT_PWRUP_TIME 4 8 RESERVED_15_9 9 15 ixDPCSSYS_CR2_SUPX_DIG_RTUNE_TX_CAL_CODE 2 0x808b 2 0 4294967295 VALUE 0 3 RESERVED_15_4 4 15 ixDPCSSYS_CR2_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0 2 0x808c 16 0 4294967295 MPLLA_WORD_CLK_EN 0 0 MPLLA_HDMI_CLK_EN 1 1 MPLLA_DIV_CLK_EN 2 2 MPLLA_OUTPUT_EN 3 3 MPLLA_CLK_EN_OVRD_EN 4 4 MPLLA_OUTPUT_L_EN 5 5 MPLLA_OUTPUT_R_EN 6 6 MPLLA_ANA_EN 7 7 MPLLA_RST 8 8 MPLLA_CAL 9 9 MPLLA_DIV5_CLK_EN 10 10 MPLLA_DIV10_CLK_EN 11 11 MPLLA_FBCLK_EN 12 12 MPLLA_GEARSHIFT_EN 13 13 MPLLA_STANDBY 14 14 OVRD_SEL 15 15 ixDPCSSYS_CR2_SUPX_DIG_ANA_MPLLA_OVRD_OUT_1 2 0x808d 2 0 4294967295 MPLLA_ANA_INT 0 9 RESERVED_15_10 10 15 ixDPCSSYS_CR2_SUPX_DIG_ANA_MPLLA_OVRD_OUT_2 2 0x808e 3 0 4294967295 MPLLA_CP_PROP 0 6 MPLLA_CP_INT 7 13 RESERVED_15_14 14 15 ixDPCSSYS_CR2_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0 2 0x808f 16 0 4294967295 MPLLB_WORD_CLK_EN 0 0 MPLLB_HDMI_CLK_EN 1 1 MPLLB_DIV_CLK_EN 2 2 MPLLB_OUTPUT_EN 3 3 MPLLB_CLK_EN_OVRD_EN 4 4 MPLLB_OUTPUT_L_EN 5 5 MPLLB_OUTPUT_R_EN 6 6 MPLLB_ANA_EN 7 7 MPLLB_RST 8 8 MPLLB_CAL 9 9 MPLLB_DIV5_CLK_EN 10 10 MPLLB_DIV10_CLK_EN 11 11 MPLLB_FBCLK_EN 12 12 MPLLB_GEARSHIFT_EN 13 13 MPLLB_STANDBY 14 14 OVRD_SEL 15 15 ixDPCSSYS_CR2_SUPX_DIG_ANA_MPLLB_OVRD_OUT_1 2 0x8090 2 0 4294967295 MPLLB_ANA_INT 0 9 RESERVED_15_10 10 15 ixDPCSSYS_CR2_SUPX_DIG_ANA_MPLLB_OVRD_OUT_2 2 0x8091 3 0 4294967295 MPLLB_CP_PROP 0 6 MPLLB_CP_INT 7 13 RESERVED_15_14 14 15 ixDPCSSYS_CR2_SUPX_DIG_ANA_RTUNE_OVRD_OUT 2 0x8092 6 0 4294967295 RTUNE_COMP_RST 0 0 RTUNE_MODE 1 2 RTUNE_EN 3 3 RTUNE_VALUE 4 13 RTUNE_OVRD_EN 14 14 RESERVED_15_15 15 15 ixDPCSSYS_CR2_SUPX_DIG_ANA_STAT 2 0x8093 3 0 4294967295 RT_ANA_COMP_RESULT 0 0 REF_ANA_CLKDET_RESULT 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR2_SUPX_DIG_ANA_BG_OVRD_OUT 2 0x8094 11 0 4294967295 BG_EN 0 0 BG_FAST_START 1 1 BG_KICK_START 2 2 BG_OVRD_EN 3 3 ANA_ASYNC_RST 4 4 ANA_ASYNC_RST_OVRD_EN 5 5 REF_VREG_FAST_START 6 6 REF_VREG_FAST_START_OVRD_EN 7 7 REF_VREG_REF_SEL 8 9 REF_VREG_REF_SEL_OVRD_EN 10 10 RESERVED_15_11 11 15 ixDPCSSYS_CR2_SUPX_DIG_ANA_MPLLA_PMIX_OVRD_OUT 2 0x8095 5 0 4294967295 MPLLA_PMIX_SEL 0 5 MPLLA_PMIX_EN 6 6 MPLLA_PMIX_SEL_OVRD_EN 7 7 MPLLA_PMIX_EN_OVRD_EN 8 8 RESERVED_15_9 9 15 ixDPCSSYS_CR2_SUPX_DIG_ANA_MPLLB_PMIX_OVRD_OUT 2 0x8096 5 0 4294967295 MPLLB_PMIX_SEL 0 5 MPLLB_PMIX_EN 6 6 MPLLB_PMIX_SEL_OVRD_EN 7 7 MPLLB_PMIX_EN_OVRD_EN 8 8 RESERVED_15_9 9 15 ixDPCSSYS_CR2_LANEX_DIG_ASIC_LANE_OVRD_IN 2 0x9000 5 0 4294967295 LANE_TX2RX_SER_LB 0 0 LANE_RX2TX_PAR_LB 1 1 EN 2 2 RX_ACJTAG_EN 3 3 RESERVED_15_4 4 15 ixDPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_0 2 0x9001 12 0 4294967295 REQ 0 0 REQ_OVRD_EN 1 1 PSTATE 2 3 PSTATE_OVRD_EN 4 4 RATE 5 7 RATE_OVRD_EN 8 8 WIDTH 9 10 WIDTH_OVRD_EN 11 11 MPLLB_SEL 12 12 MPLLB_SEL_OVRD_EN 13 13 DATA_EN 14 14 DATA_EN_OVRD_EN 15 15 ixDPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_1 2 0x9002 11 0 4294967295 NYQUIST_DATA 0 0 DISABLE 1 1 BEACON_EN 2 2 EN 3 3 TX_MAIN_CURSOR 4 9 MAIN_OVRD_EN 10 10 ASYNC_DRV_EN 11 11 ASYNC_DRV_OVRD_EN 12 12 TX_VREGDRV_BYP_OVRD 13 13 TX_VREGDRV_BYP_OVRD_EN 14 14 RESERVED_15_15 15 15 ixDPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_2 2 0x9003 6 0 4294967295 TX_PRE_CURSOR 0 5 PRE_OVRD_EN 6 6 TX_POST_CURSOR 7 12 POST_OVRD_EN 13 13 HDMIMODE_EN 14 14 HDMIMODE_ENABLE_OVRD_EN 15 15 ixDPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_3 2 0x9004 15 0 4294967295 CLK_RDY 0 0 CLK_RDY_OVRD_EN 1 1 DETECT_RX_REQ 2 2 DETECT_RX_REQ_OVRD_EN 3 3 INVERT 4 4 INVERT_OVRD_EN 5 5 LPD 6 6 LPD_OVRD_EN 7 7 TX_DC_COUP_EN 8 8 TX_DC_COUP_EN_OVRD_EN 9 9 PMA_EXTENDED_FIFO_EN 10 10 PMA_EXTENDED_FIFO_EN_OVRD_EN 11 11 TX_MPHY_MODE_EN 12 12 TX_MPHY_MODE_EN_OVRD_EN 13 13 RESERVED_15_14 14 15 ixDPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_4 2 0x9005 3 0 4294967295 RESET 0 0 RESET_OVRD_EN 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_OUT 2 0x9006 5 0 4294967295 TX_ACK 0 0 EN_TX_ACK 1 1 DETRX_RESULT 2 2 EN_DETRX_RESULT 3 3 RESERVED_15_4 4 15 ixDPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_0 2 0x9007 11 0 4294967295 REQ 0 0 REQ_OVRD_EN 1 1 DATA_EN 2 2 DATA_EN_OVRD_EN 3 3 PSTATE 4 5 PSTATE_OVRD_EN 6 6 RATE 7 8 RATE_OVRD_EN 9 9 WIDTH 10 11 WIDTH_OVRD_EN 12 12 RESERVED_15_13 13 15 ixDPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_1 2 0x9008 5 0 4294967295 RX_REF_LD_VAL_5_0 0 5 RX_CDR_VCO_LOWFREQ 6 6 EN 7 7 RX_REF_LD_VAL_6 8 8 RESERVED_15_9 9 15 ixDPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_2 2 0x9009 3 0 4294967295 RX_VCO_LD_VAL 0 12 EN 13 13 RESERVED_15_14 14 15 ixDPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_3 2 0x900a 11 0 4294967295 CDR_TRACK_EN 0 0 CDR_TRACK_EN_OVRD_EN 1 1 CDR_SSC_EN 2 2 CDR_SSC_EN_OVRD_EN 3 3 ALIGN_EN 4 4 ALIGN_EN_OVRD_EN 5 5 CLK_SHIFT 6 6 CLK_SHIFT_OVRD_EN 7 7 DISABLE 8 8 DISABLE_OVRD_EN 9 9 RESERVED_15_10 10 15 ixDPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_4 2 0x900b 11 0 4294967295 LPD 0 0 LPD_OVRD_EN 1 1 INVERT 2 2 INVERT_OVRD_EN 3 3 ADAPT_AFE_EN 4 4 ADAPT_DFE_EN 5 5 ADPT_OVRD_EN 6 6 TERM_EN 7 7 TERM_ACDC 8 8 TERM_OVRD_EN 9 9 RESERVED_15_10 10 15 ixDPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_5 2 0x900c 3 0 4294967295 RESET 0 0 RESET_OVRD_EN 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0 2 0x900d 4 0 4294967295 EQ_ATT_LVL 0 2 EQ_AFE_GAIN 3 6 RESERVED 7 10 EQ_CTLE_BOOST 11 15 ixDPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1 2 0x900e 3 0 4294967295 EQ_DFE_TAP2 0 6 EQ_DFE_TAP1 7 14 EQ_OVRD_EN 15 15 ixDPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_OUT_0 2 0x900f 9 0 4294967295 ACK 0 0 ACK_OVRD_EN 1 1 ADAPT_STS 2 3 ADAPT_STS_OVRD_EN 4 4 RX_ASYNC_DATA 5 5 RX_ASYNC_DATA_OVRD_EN 6 6 RX_SQ_WEAKKEEP_OUT 7 7 RX_SQ_WEAKKEEP_OUT_OVRD_EN 8 8 RESERVED_15_9 9 15 ixDPCSSYS_CR2_LANEX_DIG_ASIC_LANE_ASIC_IN 2 0x9010 3 0 4294967295 LANE_TX2RX_SER_LB 0 0 LANE_RX2TX_PAR_LB 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR2_LANEX_DIG_ASIC_TX_ASIC_IN_0 2 0x9011 12 0 4294967295 CLK_RDY 0 0 RESET 1 1 INVERT 2 2 DATA_EN 3 3 REQ 4 4 LPD 5 5 PSTATE 6 7 RATE 8 10 WIDTH 11 12 MPLLB_SEL 13 13 DETECT_RX_REQ 14 14 DISABLE 15 15 ixDPCSSYS_CR2_LANEX_DIG_ASIC_TX_ASIC_IN_1 2 0x9012 7 0 4294967295 BEACON_EN 0 0 TX_MAIN_CURSOR 1 6 TX_ASYNC_EN 7 7 TX_ASYNC_DATA 8 8 TX_ASYNC_DRV_EN 9 9 TX_VREGDRV_BYP 10 10 RESERVED_15_11 11 15 ixDPCSSYS_CR2_LANEX_DIG_ASIC_TX_ASIC_IN_2 2 0x9013 3 0 4294967295 TX_PRE_CURSOR 0 5 TX_POST_CURSOR 6 11 RESERVED_15_12 12 15 ixDPCSSYS_CR2_LANEX_DIG_ASIC_TX_ASIC_OUT 2 0x9014 3 0 4294967295 TX_ACK 0 0 DETRX_RESULT 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR2_LANEX_DIG_ASIC_RX_ASIC_IN_0 2 0x9015 13 0 4294967295 RESET 0 0 INVERT 1 1 DATA_EN 2 2 REQ 3 3 LPD 4 4 PSTATE 5 6 RATE 7 8 WIDTH 9 10 RESERVED 11 11 ADAPT_AFE_EN 12 12 ADAPT_DFE_EN 13 13 CDR_TRACK_EN 14 14 RESERVED_15_15 15 15 ixDPCSSYS_CR2_LANEX_DIG_ASIC_RX_ASIC_IN_1 2 0x9016 7 0 4294967295 CDR_SSC_EN 0 0 ALIGN_EN 1 1 CLK_SHIFT 2 2 DISABLE 3 3 RX_TERM_EN 4 4 RX_TERM_ACDC 5 5 RESERVED_15_6 6 15 ixDPCSSYS_CR2_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0 2 0x9017 4 0 4294967295 EQ_ATT_LVL 0 2 EQ_AFE_GAIN 3 6 RESERVED 7 10 EQ_CTLE_BOOST 11 15 ixDPCSSYS_CR2_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_1 2 0x9018 3 0 4294967295 EQ_DFE_TAP2 0 6 EQ_DFE_TAP1 7 14 RESERVED_15_15 15 15 ixDPCSSYS_CR2_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0 2 0x9019 3 0 4294967295 RX_CDR_VCO_LOWFREQ 0 0 RX_REF_LD_VAL 1 7 RESERVED_15_8 8 15 ixDPCSSYS_CR2_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1 2 0x901a 2 0 4294967295 RX_VCO_LD_VAL 0 12 RESERVED_15_13 13 15 ixDPCSSYS_CR2_LANEX_DIG_ASIC_RX_ASIC_OUT_0 2 0x901b 4 0 4294967295 ACK 0 0 VALID 1 1 ADAPT_STS 2 3 RESERVED_15_4 4 15 ixDPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_6 2 0x901c 10 0 4294967295 RX_PWM_CLK_SEL 0 1 RX_PWM_CLK_SEL_OVRD_EN 2 2 RX_TERM_LCC_ON 3 3 RX_TERM_LS_ON 4 4 RX_TERM_LS_LCC_ON_OVRD_EN 5 5 RX_TERM_CTL 6 7 RX_TERM_CTL_OVRD_EN 8 8 RX_PWM_EN 9 9 RX_PWM_EN_OVRD_EN 10 10 RESERVED_15_11 11 15 ixDPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_5 2 0x901d 15 0 4294967295 RPTR_EN_MASTER_LANE 0 0 RPTR_EN_MASTER_LANE_OVRD_EN 1 1 DIG_CLK_EN_OTHER_LANE 2 2 DIG_CLK_EN_OTHER_LANE_OVRD_EN 3 3 DIG_CLK_STATE_MASTER_LANE 4 4 DIG_CLK_STATE_MASTER_LANE_OVRD_EN 5 5 SHIFT_MASTER_LANE 6 6 SHIFT_MASTER_LANE_ORVD_EN 7 7 SHIFT_ACK_OTHER_LANE 8 8 SHIFT_ACK_OTHER_LANE_OVRD_EN 9 9 LANE_MASTER 10 10 LANE_MASTER_OVRD_IN_EN 11 11 TX_DWORD_CLK_SYNC_OVRD 12 12 TX_DWORD_CLK_SYNC_OVRD_EN 13 13 RESERVED_15_14 14 15 ixDPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_OUT_1 2 0x901e 11 0 4294967295 RPTR_EN_OUT 0 0 RPTR_EN_OUT_OVRD_EN 1 1 DIG_CLK_EN_OUT 2 2 DIG_CLK_EN_OUT_OVRD_EN 3 3 DIG_CLK_STATE_OUT 4 4 DIG_CLK_STATE_OUT_OVRD_EN 5 5 SHIFT_OUT 6 6 SHIFT_OUT_OVRD_EN 7 7 SHIFT_ACK_OUT 8 8 SHIFT_ACK_OUT_OVRD_EN 9 9 RESERVED_15_10 10 15 ixDPCSSYS_CR2_LANEX_DIG_ASIC_OCLA 2 0x901f 3 0 4294967295 RX_DWORD_OCLA_CLK_EN 0 0 RX_DWORD_OCLA_DATA_EN 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0 2 0x9020 11 0 4294967295 TX_P0_ANA_REFGEN_EN 0 0 TX_P0_ANA_VCM_HOLD 1 1 TX_P0_ANA_CLK_EN 2 2 TX_P0_ANA_WORD_CLK_EN 3 3 TX_P0_ANA_RESET 4 4 TX_P0_ANA_SERIAL_EN 5 5 TX_P0_DIG_CLK_EN 6 6 TX_P0_DATA_EN 7 7 TX_P0_ALLOW_RXDET 8 8 TX_P0_ANA_DCC_COMP_CAL_EN 9 9 RESERVED_15_10 10 15 ixDPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S 2 0x9021 11 0 4294967295 TX_P0S_ANA_REFGEN_EN 0 0 TX_P0S_ANA_VCM_HOLD 1 1 TX_P0S_ANA_CLK_EN 2 2 TX_P0S_ANA_WORD_CLK_EN 3 3 TX_P0S_ANA_RESET 4 4 TX_P0S_ANA_SERIAL_EN 5 5 TX_P0S_DIG_CLK_EN 6 6 TX_P0S_DATA_EN 7 7 TX_P0S_ALLOW_RXDET 8 8 TX_P0S_ANA_DCC_COMP_CAL_EN 9 9 RESERVED_15_10 10 15 ixDPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1 2 0x9022 11 0 4294967295 TX_P1_ANA_REFGEN_EN 0 0 TX_P1_ANA_VCM_HOLD 1 1 TX_P1_ANA_CLK_EN 2 2 TX_P1_ANA_WORD_CLK_EN 3 3 TX_P1_ANA_RESET 4 4 TX_P1_ANA_SERIAL_EN 5 5 TX_P1_DIG_CLK_EN 6 6 TX_P1_DATA_EN 7 7 TX_P1_ALLOW_RXDET 8 8 TX_P1_ANA_DCC_COMP_CAL_EN 9 9 RESERVED_15_10 10 15 ixDPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2 2 0x9023 12 0 4294967295 TX_P2_ANA_REFGEN_EN 0 0 TX_P2_ANA_VCM_HOLD 1 1 TX_P2_ANA_CLK_EN 2 2 TX_P2_ANA_WORD_CLK_EN 3 3 TX_P2_ANA_RESET 4 4 TX_P2_ANA_SERIAL_EN 5 5 TX_P2_DIG_CLK_EN 6 6 TX_P2_DATA_EN 7 7 TX_P2_ALLOW_RXDET 8 8 TX_P2_ALLOW_VBOOST 9 9 TX_P2_ANA_DCC_COMP_CAL_EN 10 10 RESERVED_15_11 11 15 ixDPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_0 2 0x9024 2 0 4294967295 TX_REFGEN_EN_TIME 0 7 TX_CLK_EN 8 15 ixDPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_1 2 0x9025 2 0 4294967295 TX_VCM_HOLD_TIME_14_0 0 14 SKIP_TX_VCM_HOLD_WAIT 15 15 ixDPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_2 2 0x9026 2 0 4294967295 TX_VBOOST_DIS_TIME_12_0 0 12 DTB_SEL 13 15 ixDPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_3 2 0x9027 3 0 4294967295 TX_VCM_HOLD_TIME_17_15 0 2 TX_VBOOST_DIS_TIME_13 3 3 RESERVED_15_4 4 15 ixDPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_4 2 0x9028 2 0 4294967295 TX_VCM_HOLD_GS_TIME 0 14 SKIP_TX_VCM_HOLD_GS_PULSE 15 15 ixDPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_5 2 0x9029 5 0 4294967295 TX_RXDET_TIME 0 9 FAST_TX_RXDET 10 10 TX_RESET_TIME 11 12 TX_SERIAL_EN_TIME 13 14 RESERVED_15_15 15 15 ixDPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_DCC_CR_BANK_ADDR 2 0x902a 1 0 4294967295 ADDR 0 15 ixDPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_DCC_CR_BANK_DATA 2 0x902b 1 0 4294967295 DATA 0 15 ixDPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_DCC_DAC_CTRL 2 0x902c 2 0 4294967295 CTRL 0 7 RESERVED_15_8 8 15 ixDPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_DCC_DAC_RANGE 2 0x902d 2 0 4294967295 CTRL 0 1 RESERVED_15_2 2 15 ixDPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_DCC_DAC_SEL 2 0x902e 6 0 4294967295 SEL 0 2 REQ 3 3 CTRL_UPD 4 4 RANGE_UPD 5 5 BIN_HOT 6 6 RESERVED_15_7 7 15 ixDPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_DCC_DAC_ACK 2 0x902f 2 0 4294967295 ACK 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_DCC_DAC_ADDR 2 0x9030 1 0 4294967295 ADDR 0 15 ixDPCSSYS_CR2_LANEX_DIG_TX_CLK_ALIGN_TX_CTL_0 2 0x9031 4 0 4294967295 TX_NUM_2UI_SHIFTS_16B_MODE 0 3 TX_NUM_2UI_SHIFTS_20B_MODE 4 7 TX_FIFO_BYPASS 8 8 RESERVED_15_9 9 15 ixDPCSSYS_CR2_LANEX_DIG_TX_LBERT_CTL 2 0x9032 4 0 4294967295 MODE 0 3 TRIGGER_ERR 4 4 PAT0 5 14 RESERVED_15_15 15 15 ixDPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0 2 0x9040 12 0 4294967295 RX_P0_ANA_AFE_EN 0 0 RX_P0_ANA_CLK_VREG_EN 1 1 RESERVED_1 2 2 RX_P0_ANA_CLK_EN 3 3 RESERVED_0 4 4 RX_P0_ANA_DESER_EN 5 5 RX_P0_ANA_CDR_EN 6 6 RX_P0_VCO_FREQ_RST 7 7 RX_P0_VCO_CAL_RST 8 8 RX_P0_VCO_CONTCAL_EN 9 9 RX_P0_DIG_CLK_EN 10 10 RESERVED_15_11 11 15 ixDPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S 2 0x9041 12 0 4294967295 RX_P0S_ANA_AFE_EN 0 0 RX_P0S_ANA_CLK_VREG_EN 1 1 RESERVED_2 2 2 RX_P0S_ANA_CLK_EN 3 3 RESERVED_4 4 4 RX_P0S_ANA_DESER_EN 5 5 RX_P0S_ANA_CDR_EN 6 6 RX_P0S_VCO_FREQ_RST 7 7 RX_P0S_VCO_CAL_RST 8 8 RX_P0S_VCO_CONTCAL_EN 9 9 RX_P0S_DIG_CLK_EN 10 10 RESERVED_15_11 11 15 ixDPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1 2 0x9042 12 0 4294967295 RX_P1_ANA_AFE_EN 0 0 RX_P1_ANA_CLK_VREG_EN 1 1 RESERVED_2 2 2 RX_P1_ANA_CLK_EN 3 3 RESERVED_4 4 4 RX_P1_ANA_DESER_EN 5 5 RX_P1_ANA_CDR_EN 6 6 RX_P1_VCO_FREQ_RST 7 7 RX_P1_VCO_CAL_RST 8 8 RX_P1_VCO_CONTCAL_EN 9 9 RX_P1_DIG_CLK_EN 10 10 RESERVED_15_11 11 15 ixDPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2 2 0x9043 12 0 4294967295 RX_P2_ANA_AFE_EN 0 0 RX_P2_ANA_CLK_VREG_EN 1 1 RESERVED_2 2 2 RX_P2_ANA_CLK_EN 3 3 RESERVED_4 4 4 RX_P2_ANA_DESER_EN 5 5 RX_P2_ANA_CDR_EN 6 6 RX_P2_VCO_FREQ_RST 7 7 RX_P2_VCO_CAL_RST 8 8 RX_P2_VCO_CONTCAL_EN 9 9 RX_P2_DIG_CLK_EN 10 10 RESERVED_15_11 11 15 ixDPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1 2 0x9045 5 0 4294967295 RX_AFE_EN_TIME 0 5 FAST_RX_AFE_EN 6 6 RX_VREG_EN_TIME 7 12 FAST_RX_VREG_EN 13 13 RESERVED_15_14 14 15 ixDPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_2 2 0x9046 4 0 4294967295 RX_CLK_EN_TIME 0 5 FAST_RX_CLK_EN 6 6 RX_FAST_START_TIME 7 10 RESERVED_15_11 11 15 ixDPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_3 2 0x9047 5 0 4294967295 RX_RATE_TIME 0 1 RSVD_3_7_2 2 7 RX_CDR_EN_TIME 8 11 RX_DESER_EN_TIME 12 13 RX_DESER_DIS_TIME 14 15 ixDPCSSYS_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0 2 0x9048 8 0 4294967295 INT_GAIN_CAL_FIXED_CNT 0 4 INT_GAIN_CAL_FIXED_CNT_EN 5 5 INT_GAIN_CAL_CNT_SHIFT 6 8 INT_GAIN_CAL_BOUNCE_CNT 9 11 DISABLE_BIN_HOLD 12 12 DISABLE_INT_GAIN_HOLD 13 13 DISABLE_COARSE_CALDONE 14 14 RESERVED_15_15 15 15 ixDPCSSYS_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1 2 0x9049 7 0 4294967295 RX_VCO_OVRD_SEL 0 0 RX_VCO_FREQ_RST 1 1 RX_VCO_CAL_RST 2 2 RX_VCO_CONTCAL_EN 3 3 DISABLE_INT_CAL_MODE 4 4 DPLL_CAL_UG 5 8 DTB_SEL 9 15 ixDPCSSYS_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2 2 0x904a 4 0 4294967295 FREQ_TUNE_START_VAL 0 9 FREQ_TUNE_CAL_STEPS 10 13 SKIP_RX_VCO_FREQ_TUNE_CAL 14 14 SKIP_RX_VCO_CAL 15 15 ixDPCSSYS_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0 2 0x904b 4 0 4294967295 RX_VCO_STARTUP_TIME 0 6 RX_VCO_UPDATE_TIME 7 10 RX_VCO_CNTR_PWRUP_TIME 11 14 FAST_RX_VCO_WAIT 15 15 ixDPCSSYS_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1 2 0x904c 2 0 4294967295 RX_VCO_CNTR_SETTLE_TIME 0 2 RESERVED_15_3 3 15 ixDPCSSYS_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0 2 0x904d 6 0 4294967295 RX_ANA_CDR_FREQ_TUNE 0 9 RX_ANA_VCO_CNTR_PD 10 10 RX_ANA_VCO_CNTR_EN 11 11 RX_ANA_CDR_STARTUP 12 12 RX_ANA_CDR_VCO_EN 13 13 RESERVED_15_14 14 15 ixDPCSSYS_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1 2 0x904e 7 0 4294967295 RX_VCO_FSM_STATE 0 3 RX_VCO_FREQ_RST 4 4 RX_VCO_CAL_RST 5 5 RX_VCO_CONTCAL_EN 6 6 RX_VCO_CAL_DONE 7 7 DPLL_FREQ_RST 8 8 RESERVED_15_9 9 15 ixDPCSSYS_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_2 2 0x904f 4 0 4294967295 VCO_CNTR_FINAL 0 12 VCOCLK_TOO_FAST 13 13 RX_VCO_CORRECT 14 14 RX_VCO_UP 15 15 ixDPCSSYS_CR2_LANEX_DIG_RX_RX_ALIGN_XAUI_COMM_MASK 2 0x9050 2 0 4294967295 XAUI_COMM_MASK 0 9 RESERVED_15_10 10 15 ixDPCSSYS_CR2_LANEX_DIG_RX_LBERT_CTL 2 0x9051 3 0 4294967295 MODE 0 3 SYNC 4 4 RESERVED_15_5 5 15 ixDPCSSYS_CR2_LANEX_DIG_RX_LBERT_ERR 2 0x9052 2 0 4294967295 COUNT 0 14 OV14 15 15 ixDPCSSYS_CR2_LANEX_DIG_RX_CDR_CDR_CTL_0 2 0x9053 7 0 4294967295 PHDET_EN 0 1 PHDET_EDGE 2 3 PHDET_POL 4 4 PHDET_EN_PR_MODE 5 5 ALWAYS_REALIGN 6 6 DTB_SEL 7 10 RESERVED_15_11 11 15 ixDPCSSYS_CR2_LANEX_DIG_RX_CDR_CDR_CTL_1 2 0x9054 2 0 4294967295 SSC_OFF_CNT0 0 9 SSC_OFF_CNT1 10 15 ixDPCSSYS_CR2_LANEX_DIG_RX_CDR_CDR_CTL_2 2 0x9055 2 0 4294967295 SSC_ON_CNT0 0 8 SSC_ON_CNT1 9 15 ixDPCSSYS_CR2_LANEX_DIG_RX_CDR_CDR_CTL_3 2 0x9056 6 0 4294967295 SSC_OFF_PHUG0 0 2 SSC_OFF_PHUG1 3 5 SSC_OFF_FRUG0 6 8 OVRD_DPLL_GAIN 9 9 PHUG_OVRD_VALUE 10 12 FRUG_OVRD_VALUE 13 15 ixDPCSSYS_CR2_LANEX_DIG_RX_CDR_CDR_CTL_4 2 0x9057 6 0 4294967295 SSC_OFF_FRUG1 0 2 SSC_ON_FRUG0 3 5 SSC_ON_FRUG1 6 8 SSC_ON_PHUG0 9 11 SSC_ON_PHUG1 12 14 RESERVED_15_15 15 15 ixDPCSSYS_CR2_LANEX_DIG_RX_CDR_STAT 2 0x9058 3 0 4294967295 PHUG_VALUE 0 2 FRUG_VALUE 3 5 RESERVED_15_6 6 15 ixDPCSSYS_CR2_LANEX_DIG_RX_DPLL_FREQ 2 0x9059 2 0 4294967295 VAL 0 13 RESERVED_15_14 14 15 ixDPCSSYS_CR2_LANEX_DIG_RX_DPLL_FREQ_BOUND_0 2 0x905a 3 0 4294967295 FREQ_BOUND_EN 0 0 UPPER_FREQ_BOUND 1 10 RESERVED_15_11 11 15 ixDPCSSYS_CR2_LANEX_DIG_RX_DPLL_FREQ_BOUND_1 2 0x905b 2 0 4294967295 LOWER_FREQ_BOUND 0 9 RESERVED_15_10 10 15 ixDPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_0 2 0x9060 4 0 4294967295 N_TOP_ASM1 0 9 N_TGG_ASM1 10 13 START_ASM1 14 14 ADPT_CLK_DIV4_EN 15 15 ixDPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1 2 0x9061 5 0 4294967295 N_WAIT_ASM1 0 6 FAST_AFE_DFE_SETTLE 7 7 CTLE_POLE_OVRD_VAL 8 10 CTLE_POLE_OVRD_EN 11 11 RESERVED_15_12 12 15 ixDPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_2 2 0x9062 3 0 4294967295 TGG_PTTRN_0 0 4 TGG_PTTRN_1 5 9 RESERVED_15_10 10 15 ixDPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3 2 0x9063 8 0 4294967295 CTLE_EN 0 4 VGA_EN 5 5 ATT_EN 6 6 DFE_EN 7 11 EYEHE_EN 12 12 EYEHO_EN 13 13 TGG_EN 14 14 ESL_TWICE_DSL 15 15 ixDPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_4 2 0x9064 4 0 4294967295 CTLE_TH 0 3 VGA_TH 4 7 DFE1_TH 8 11 DFE2_TH 12 15 ixDPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_5 2 0x9065 4 0 4294967295 DFE3_TH 0 3 DFE4_TH 4 7 DFE5_TH 8 11 TH_OFFSET 12 15 ixDPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6 2 0x9066 6 0 4294967295 CTLE_MU 0 2 VGA_MU 3 5 ATT_MU 6 8 VGA_SAT_CNT 9 11 VGA_SAT_CNT_STICKY 12 12 ATT_LOW_TH 13 15 ixDPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_7 2 0x9067 4 0 4294967295 VGA_MIN_SAT 0 4 VGA_LEV_HIGH 5 9 VGA_LEV_LOW 10 14 RESERVED_15_15 15 15 ixDPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8 2 0x9068 6 0 4294967295 DFE1_MU 0 2 DFE2_MU 3 5 DFE3_MU 6 8 DFE4_MU 9 11 DFE5_MU 12 14 RESERVED_15_15 15 15 ixDPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_9 2 0x9069 2 0 4294967295 ERR_SLE_ADPT_INIT 0 7 ERR_SLO_ADPT_INIT 8 15 ixDPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG 2 0x906a 6 0 4294967295 RST_ADPT_ATT 0 0 RST_ADPT_VGA 1 1 RST_ADPT_CTLE_BOOST 2 2 RST_ADPT_CTLE_POLE 3 3 RST_ADPT_TAP1 4 4 RESERVED_15_5 5 15 ixDPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ATT_STATUS 2 0x906b 3 0 4294967295 ATT_ADPT_CODE 0 7 ASM1_DON 8 8 RESERVED_15_9 9 15 ixDPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_VGA_STATUS 2 0x906c 3 0 4294967295 VGA_ADPT_CODE 0 9 ASM1_DONE 10 10 RESERVED_15_11 11 15 ixDPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_CTLE_STATUS 2 0x906d 4 0 4294967295 CTLE_BOOST_ADPT_CODE 0 9 CTLE_POLE_ADPT_CODE 10 12 ASM1_DONE 13 13 RESERVED_15_14 14 15 ixDPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_DFE_TAP1_STATUS 2 0x906e 3 0 4294967295 DFE_TAP1_ADPT_CODE 0 12 ASM1_DONE 13 13 RESERVED_15_14 14 15 ixDPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_DFE_TAP2_STATUS 2 0x906f 3 0 4294967295 DFE_TAP2_ADPT_CODE 0 11 ASM1_DONE 12 12 RESERVED_15_13 13 15 ixDPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_DFE_TAP3_STATUS 2 0x9070 3 0 4294967295 DFE_TAP3_ADPT_CODE 0 11 ASM1_DONE 12 12 RESERVED_15_13 13 15 ixDPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_DFE_TAP4_STATUS 2 0x9071 3 0 4294967295 DFE_TAP4_ADPT_CODE 0 11 ASM1_DONE 12 12 RESERVED_15_13 13 15 ixDPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_DFE_TAP5_STATUS 2 0x9072 3 0 4294967295 DFE_TAP5_ADPT_CODE 0 11 ASM1_DONE 12 12 RESERVED_15_13 13 15 ixDPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_DFE_DATA_EVEN_VDAC_OFST 2 0x9073 2 0 4294967295 DFE_DATA_EVEN_VDAC_OFST 0 7 RESERVED_15_8 8 15 ixDPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_DFE_DATA_ODD_VDAC_OFST 2 0x9074 2 0 4294967295 DFE_DATA_ODD_VDAC_OFST 0 7 RESERVED_15_8 8 15 ixDPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN 2 0x9075 2 0 4294967295 RX_ANA_SLICER_CTRL_E 0 3 RESERVED_15_4 4 15 ixDPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD 2 0x9076 2 0 4294967295 RX_ANA_SLICER_CTRL_O 0 3 RESERVED_15_4 4 15 ixDPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST 2 0x9077 2 0 4294967295 DFE_ERROR_EVEN_VDAC_OFST 0 7 RESERVED_15_8 8 15 ixDPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST 2 0x9078 2 0 4294967295 DFE_ERROR_ODD_VDAC_OFST 0 7 RESERVED_15_8 8 15 ixDPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL 2 0x9079 2 0 4294967295 E_SLO_LVL 0 7 E_SLE_LVL 8 15 ixDPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_RESET 2 0x907a 2 0 4294967295 RESET_ASM1 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1 2 0x907b 4 0 4294967295 DFE_T1_IDAC 0 4 DFE_T2_IDAC 5 9 DCC_START_IDAC 10 14 RESERVED_15_15 15 15 ixDPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2 2 0x907c 3 0 4294967295 DFE_DAT_EVEN_VDAC 0 4 DFE_DAT_ODD_VDAC 5 9 RESERVED_15_10 10 15 ixDPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3 2 0x907d 3 0 4294967295 DFE_ERR_EVEN_VDAC 0 4 DFE_ERR_ODD_VDAC 5 9 RESERVED_15_10 10 15 ixDPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_CR_BANK_ADDR 2 0x907e 1 0 4294967295 ADDR 0 15 ixDPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_CR_BANK_DATA 2 0x907f 1 0 4294967295 DATA 0 15 ixDPCSSYS_CR2_LANEX_DIG_RX_STAT_LD_VAL_1 2 0x9080 2 0 4294967295 SC1_LD_VAL 0 14 SC1_START 15 15 ixDPCSSYS_CR2_LANEX_DIG_RX_STAT_DATA_MSK 2 0x9081 1 0 4294967295 DATA_MSK_15_0 0 15 ixDPCSSYS_CR2_LANEX_DIG_RX_STAT_MATCH_CTL0 2 0x9082 4 0 4294967295 PTTRN_MSK_CR1A_4_0 0 4 PTTRN_CR1A_4_0 5 9 DATA_MSK_19_16 10 13 SCOPE_DLY 14 15 ixDPCSSYS_CR2_LANEX_DIG_RX_STAT_MATCH_CTL1 2 0x9083 5 0 4294967295 PTTRN_CR1B_EN 0 0 PTTRN_MSK_CR1B_4_0 1 5 PTTRN_CR1B_4_0 6 10 PTTRN_CR1A_ADPT_EN 11 11 RESERVED_15_12 12 15 ixDPCSSYS_CR2_LANEX_DIG_RX_STAT_STAT_CTL0 2 0x9084 10 0 4294967295 RESERVED_0 0 0 CORR_SHFT_SEL_VGA 1 1 CORR_SHFT_SEL 2 2 CORR_SRC_SEL 3 4 CORR_MODE_EN 5 5 STAT_SHFT_SEL 6 9 STAT_SRC_SEL 10 12 STAT_RXCLK_SEL 13 13 SC_TIMER_MODE 14 14 SKIP_EN 15 15 ixDPCSSYS_CR2_LANEX_DIG_RX_STAT_STAT_CTL1 2 0x9085 13 0 4294967295 STAT_CNT_0_EN 0 0 STAT_CNT_1_EN 1 1 STAT_CNT_2_EN 2 2 STAT_CNT_3_EN 3 3 STAT_CNT_4_EN 4 4 STAT_CNT_5_EN 5 5 STAT_CNT_6_EN 6 6 RESERVED_8_7 7 8 SC_PAUSE 9 9 STAT_CLK_EN 10 10 DATA_DLY_SEL 11 12 VLD_LOSS_CLR 13 13 VLD_CTL 14 15 ixDPCSSYS_CR2_LANEX_DIG_RX_STAT_SMPL_CNT1 2 0x9086 2 0 4294967295 SMPL_CNT1 0 14 SMPL_CNT1_DONE 15 15 ixDPCSSYS_CR2_LANEX_DIG_RX_STAT_STAT_CNT_0 2 0x9087 2 0 4294967295 STAT_CNT_0 0 14 SMPL_CNT1_DONE 15 15 ixDPCSSYS_CR2_LANEX_DIG_RX_STAT_STAT_CNT_1 2 0x9088 2 0 4294967295 STAT_CNT_1 0 14 SMPL_CNT1_DONE 15 15 ixDPCSSYS_CR2_LANEX_DIG_RX_STAT_STAT_CNT_2 2 0x9089 2 0 4294967295 STAT_CNT_2 0 14 SMPL_CNT1_DONE 15 15 ixDPCSSYS_CR2_LANEX_DIG_RX_STAT_STAT_CNT_3 2 0x908a 2 0 4294967295 STAT_CNT_3 0 14 SMPL_CNT1_DONE 15 15 ixDPCSSYS_CR2_LANEX_DIG_RX_STAT_STAT_CNT_4 2 0x908b 2 0 4294967295 STAT_CNT_4 0 14 SMPL_CNT1_DONE 15 15 ixDPCSSYS_CR2_LANEX_DIG_RX_STAT_STAT_CNT_5 2 0x908c 2 0 4294967295 STAT_CNT_5 0 14 SMPL_CNT1_DONE 15 15 ixDPCSSYS_CR2_LANEX_DIG_RX_STAT_STAT_CNT_6 2 0x908d 2 0 4294967295 STAT_CNT_6 0 14 SMPL_CNT1_DONE 15 15 ixDPCSSYS_CR2_LANEX_DIG_RX_STAT_CAL_COMP_CLK_CTL 2 0x908e 3 0 4294967295 PRECHRGE_CNT 0 2 REF_DIV_CNT 3 5 RESERVED_15_6 6 15 ixDPCSSYS_CR2_LANEX_DIG_RX_STAT_MATCH_CTL2 2 0x908f 2 0 4294967295 PTTRN_CR1A_19_5 0 14 RESERVED_15_15 15 15 ixDPCSSYS_CR2_LANEX_DIG_RX_STAT_MATCH_CTL3 2 0x9090 2 0 4294967295 PTTRN_MSK_CR1A_19_5 0 14 RESERVED_15_15 15 15 ixDPCSSYS_CR2_LANEX_DIG_RX_STAT_MATCH_CTL4 2 0x9091 2 0 4294967295 PTTRN_CR1B_19_5 0 14 RESERVED_15_15 15 15 ixDPCSSYS_CR2_LANEX_DIG_RX_STAT_MATCH_CTL5 2 0x9092 2 0 4294967295 PTTRN_MSK_CR1B_19_5 0 14 RESERVED_15_15 15 15 ixDPCSSYS_CR2_LANEX_DIG_RX_STAT_STAT_CTL2 2 0x9093 4 0 4294967295 DATA_DLY_SEL_2 0 0 SCOPE_DLY_2 1 1 DISABLE_SAMPLE_COUNT 2 2 RESERVED_15_3 3 15 ixDPCSSYS_CR2_LANEX_DIG_RX_STAT_STAT_STOP 2 0x9094 2 0 4294967295 SC1_STOP 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR2_LANEX_DIG_MPHY_RX_PWM_CTL 2 0x9095 3 0 4294967295 RX_PWM_POL 0 0 RX_PWM_DATA_POL 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR2_LANEX_DIG_MPHY_RX_TERM_LS_CTL 2 0x9096 2 0 4294967295 RX_TERM_LCC_CNT 0 2 RESERVED_15_3 3 15 ixDPCSSYS_CR2_LANEX_DIG_MPHY_RX_ANA_PWM_CLK_STABLE_CNT 2 0x9097 2 0 4294967295 PWM_CLK_STABLE_CNT 0 3 RESERVED_15_4 4 15 ixDPCSSYS_CR2_LANEX_DIG_ANA_TX_OVRD_OUT 2 0x90a0 15 0 4294967295 TX_ANA_CLK_SHIFT 0 0 TX_ANA_DATA_EN 1 1 TX_ANA_REFGEN_EN 2 2 TX_ANA_VCM_HOLD 3 3 TX_ANA_CLK_EN 4 4 TX_ANA_WORD_CLK_EN 5 5 TX_ANA_MPLLA_CLK_EN 6 6 TX_ANA_MPLLB_CLK_EN 7 7 TX_ANA_RESET 8 8 TX_ANA_SERIAL_EN 9 9 TX_ANA_DATA_RATE 10 11 RESERVED 12 12 TX_DIV4_EN 13 13 TX_RXDET_EN 14 14 TX_OVRD_EN 15 15 ixDPCSSYS_CR2_LANEX_DIG_ANA_TX_TERM_CODE_OVRD_OUT 2 0x90a1 5 0 4294967295 TX_TERM_CODE 0 9 TX_TERM_OVRD_EN 10 10 TX_DRV_SRC 11 12 TX_DRV_SRC_OVRD_EN 13 13 RESERVED_15_14 14 15 ixDPCSSYS_CR2_LANEX_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT 2 0x90a2 3 0 4294967295 TX_TERM_DN_CLK 0 0 TX_TERM_CLK_SELF_CLEAR_DISABLE 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR2_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_0 2 0x90a3 3 0 4294967295 TX_ANA_LOAD_CLK 0 0 TX_ANA_CTRL_LEG_PULL_EN_13_0 1 14 TX_EQ_OVRD_EN 15 15 ixDPCSSYS_CR2_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_1 2 0x90a4 2 0 4294967295 TX_ANA_CTRL_LEG_PULL_EN_19_14 0 5 RESERVED_15_6 6 15 ixDPCSSYS_CR2_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_2 2 0x90a5 4 0 4294967295 RESERVED 0 2 TX_ANA_CTRL_EQ_MUX_SEL 3 6 TX_ANA_CTRL_PRE 7 12 RESERVED_15_13 13 15 ixDPCSSYS_CR2_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_3 2 0x90a6 2 0 4294967295 TX_ANA_CTRL_POST 0 8 RESERVED_15_9 9 15 ixDPCSSYS_CR2_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_4 2 0x90a7 1 0 4294967295 TX_ANA_CTRL_LEG_PULL_DIR_19_4 0 15 ixDPCSSYS_CR2_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_5 2 0x90a8 2 0 4294967295 TX_ANA_CTRL_LEG_PULL_DIR_3_0 0 3 RESERVED_15_4 4 15 ixDPCSSYS_CR2_LANEX_DIG_ANA_RX_CTL_OVRD_OUT 2 0x90a9 9 0 4294967295 RESERVED 0 0 RX_ANA_DATA_RATE 1 2 RX_ANA_WORD_CLK_EN 3 3 RX_ANA_DIV4_EN 4 4 RX_ANA_DFE_TAPS_EN 5 5 RX_ANA_ADAPTATION_EN 6 6 RX_LBK_CLK_EN 7 7 RX_CTL_OVRD_EN 8 8 RESERVED_15_9 9 15 ixDPCSSYS_CR2_LANEX_DIG_ANA_RX_PWR_OVRD_OUT 2 0x90aa 9 0 4294967295 RX_ANA_AFE_EN 0 0 RX_ANA_CLK_VREG_EN 1 1 RX_ANA_CLK_DCC_EN 2 2 RX_ANA_CLK_EN 3 3 RX_ANA_CDR_EN 4 4 RX_ANA_DESERIAL_EN 5 5 RX_PWR_OVRD_EN 6 6 RX_ANA_FAST_START 7 7 RESERVED_15_8 8 15 ixDPCSSYS_CR2_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0 2 0x90ab 7 0 4294967295 RX_ANA_CDR_VCO_EN 0 0 RX_ANA_CDR_STARTUP 1 1 RX_VCO_CDR_OVRD_EN 2 2 RX_ANA_CDR_FREQ_TUNE 3 12 RX_ANA_VCO_CNTR_EN 13 13 RX_ANA_VCO_CNTR_CLK 14 14 RX_CDR_FREQ_TUNE_OVRD_EN 15 15 ixDPCSSYS_CR2_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_1 2 0x90ac 3 0 4294967295 RX_ANA_CDR_VCO_LOWFREQ 0 0 RX_ANA_VCO_CNTR_PD 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR2_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_2 2 0x90ad 3 0 4294967295 RX_ANA_CDR_FREQ_TUNE_CLK 0 0 CDR_FREQ_TUNE_CLK_SELF_CLEAR_DISABLE 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR2_LANEX_DIG_ANA_RX_CAL 2 0x90ae 7 0 4294967295 RX_ANA_CAL_MUXA_SEL 0 4 RX_ANA_CAL_MUXB_SEL 5 9 RX_ANA_CAL_LPFBYP_EN 10 10 RESERVED 11 11 RX_ANA_SLICER_CAL_EN 12 12 RX_ANA_CAL_MODE 13 14 RX_ANA_CAL_COMP_EN 15 15 ixDPCSSYS_CR2_LANEX_DIG_ANA_RX_DAC_CTRL 2 0x90af 2 0 4294967295 RX_ANA_CAL_DAC_CTRL 0 7 RESERVED_15_8 8 15 ixDPCSSYS_CR2_LANEX_DIG_ANA_RX_DAC_CTRL_OVRD 2 0x90b0 2 0 4294967295 RX_CAL_DAC_CTRL_OVRD 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR2_LANEX_DIG_ANA_RX_DAC_CTRL_SEL 2 0x90b1 2 0 4294967295 RX_ANA_CAL_DAC_CTRL_SEL 0 4 RESERVED_15_5 5 15 ixDPCSSYS_CR2_LANEX_DIG_ANA_RX_AFE_ATT_VGA 2 0x90b2 5 0 4294967295 RX_ANA_AFE_ATT_LVL 0 2 RX_ANA_AFE_GAIN 3 6 RESERVED 7 10 RX_AFE_OVRD_EN 11 11 RESERVED_15_12 12 15 ixDPCSSYS_CR2_LANEX_DIG_ANA_RX_AFE_CTLE 2 0x90b3 3 0 4294967295 RESERVED 0 2 RX_ANA_AFE_CTLE_BOOST 3 7 RESERVED_15_8 8 15 ixDPCSSYS_CR2_LANEX_DIG_ANA_RX_SCOPE 2 0x90b4 7 0 4294967295 RX_ANA_SCOPE_EN 0 0 RX_ANA_SCOPE_SEL 1 2 RX_ANA_SCOPE_PH_CLK 3 3 RX_ANA_SCOPE_PHASE 4 11 RX_ANA_SCOPE_CLK_EN 12 12 RX_SCOPE_SELF_CLEAR_DISABLE 13 13 RESERVED_15_14 14 15 ixDPCSSYS_CR2_LANEX_DIG_ANA_RX_SLICER_CTRL 2 0x90b5 4 0 4294967295 RX_ANA_SLICER_CTRL_E 0 3 RX_ANA_SLICER_CTRL_O 4 7 RX_ANA_SLICER_CTRL_OVRD_EN 8 8 RESERVED_15_9 9 15 ixDPCSSYS_CR2_LANEX_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST 2 0x90b6 2 0 4294967295 RX_ANA_IQ_PHASE_ADJUST 0 6 RESERVED_15_7 7 15 ixDPCSSYS_CR2_LANEX_DIG_ANA_RX_ANA_IQ_SENSE_EN 2 0x90b7 2 0 4294967295 RX_ANA_IQ_SENSE_EN 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR2_LANEX_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN 2 0x90b8 3 0 4294967295 RX_ANA_CAL_DAC_CTRL_EN 0 0 DAC_CTRL_SELF_CLEAR_DISABLE 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR2_LANEX_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE 2 0x90b9 3 0 4294967295 RX_ANA_AFE_UPDATE_EN 0 0 AFE_UPDATE_SELF_CLEAR_DISABLE 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR2_LANEX_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK 2 0x90ba 3 0 4294967295 RX_ANA_IQ_PHASE_ADJUST_CLK 0 0 PHASE_ADJUST_SELF_CLEAR_DISABLE 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR2_LANEX_DIG_ANA_STATUS_0 2 0x90bb 9 0 4294967295 TX_ANA_CLK_SHIFT_ACK 0 0 TX_ANA_RXDETP_RESULT 1 1 TX_ANA_RXDETM_RESULT 2 2 TX_ANA_LOOPBACK_EN 3 3 TX_ANA_CLK_LB_EN 4 4 RX_ANA_CAL_RESULT 5 5 RX_ANA_SCOPE_DATA 6 6 TX_ANA_DCC_CAL_RESULT 7 7 TX_ANA_CTRL_EQ_MUX 8 15 ixDPCSSYS_CR2_LANEX_DIG_ANA_STATUS_1 2 0x90bc 2 0 4294967295 RX_ANA_VCO_CNTR 0 12 RESERVED_15_13 13 15 ixDPCSSYS_CR2_LANEX_DIG_ANA_RX_TERM_CODE_OVRD_OUT 2 0x90bd 3 0 4294967295 RX_TERM_CODE 0 5 RX_TERM_OVRD_EN 6 6 RESERVED_15_7 7 15 ixDPCSSYS_CR2_LANEX_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT 2 0x90be 3 0 4294967295 RX_TERM_CLK 0 0 RX_TERM_CLK_SELF_CLEAR_DISABLE 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR2_LANEX_DIG_ANA_MPHY_OVRD_OUT 2 0x90bf 9 0 4294967295 RX_ANA_SQ_CTRL_TRESH 0 2 RX_ANA_SQ_CTRL_TRESH_OVRD_EN 3 3 RX_ANA_SQ_CTRL_RESP 4 5 RX_ANA_SQ_CTRL_RESP_OVRD_EN 6 6 RX_ANA_PWM_EN 7 7 RX_ANA_PWM_EN_OVRD_EN 8 8 RX_ANA_PWM_CLK_SEL 9 10 RX_ANA_PWM_CLK_SEL_OVRD_EN 11 11 RESERVED_15_12 12 15 ixDPCSSYS_CR2_LANEX_DIG_ANA_SIGDET_OVRD_OUT_1 2 0x90c0 7 0 4294967295 RX_ANA_SIGDET_HF_THRESH 0 2 RX_ANA_SIGDET_HF_THRESH_OVRD_EN 3 3 RX_ANA_SIGDET_HF_CAL_TUNE 4 9 RX_ANA_SIGDET_CAL_TUNE_OVRD_EN 10 10 RX_ANA_SIGDET_CAL_EN 11 11 RX_ANA_SIGDET_CAL_EN_OVRD_EN 12 12 RESERVED_15_13 13 15 ixDPCSSYS_CR2_LANEX_DIG_ANA_SIGDET_OVRD_OUT_2 2 0x90c1 7 0 4294967295 RX_ANA_SIGDET_LF_THRESH 0 2 RX_ANA_SIGDET_LF_THRESH_OVRD_EN 3 3 RX_ANA_SIGDET_LF_FILTER_EN 4 4 RX_ANA_SIGDET_LF_FILTER_EN_OVRD_EN 5 5 RX_ANA_SIGDET_CAL_TUNE 6 11 RX_ANA_SIGDET_CAL_TUNE_OVRD_EN 12 12 RESERVED_15_13 13 15 ixDPCSSYS_CR2_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT 2 0x90c2 8 0 4294967295 TX_ANA_DCC_CAL_RANGE 0 1 TX_ANA_DCC_CAL_RANGE_OVRD_EN 2 2 TX_ANA_DCC_CAL_COMP_EN 3 3 TX_ANA_DCC_CAL_COMP_EN_OVRD_EN 4 4 TX_ANA_DCC_CAL_CTRL 5 12 TX_ANA_DCC_CAL_CTRL_OVRD_EN 13 13 TX_ANA_DCC_CAL_CTRL_EN 14 14 TX_ANA_DCC_CAL_CTRL_EN_OVRD_EN 15 15 ixDPCSSYS_CR2_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2 2 0x90c3 5 0 4294967295 TX_ANA_DCC_CAL_CTRL_SEL 0 2 TX_ANA_DCC_CAL_CTRL_SEL_OVRD_EN 3 3 TX_ANA_DCC_CLK_COMP 4 4 TX_ANA_DCC_CLK_COMP_OVRD_EN 5 5 RESERVED_15_6 6 15 ixDPCSSYS_CR2_LANEX_DIG_ANA_TX_OVRD_OUT_2 2 0x90c4 6 0 4294967295 TX_ANA_FAST_START 0 0 TX_ANA_FAST_START_OVRD_EN 1 1 TX_CLK_LB_EN 2 2 TX_CLK_LB_EN_OVRD_EN 3 3 TX_ACJTAG_EN 4 4 RESERVED_15_5 5 15 ixDPCSSYS_CR2_LANEX_ANA_TX_OVRD_MEAS 2 0x90e0 9 0 4294967295 OVRD_CLK_SHIFT 0 0 CLK_SHIFT_REG 0 0 MEAS_ATB_CAL_MUX 0 0 MEAS_ATB_CAL_COMP 0 0 OVRD_VCM_HOLD 0 0 VCM_HOLD_REG 0 0 PULL_UP_REG 0 0 PULL_DN_REG 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR2_LANEX_ANA_TX_PWR_OVRD 2 0x90e1 9 0 4294967295 OVRD_TX_LOOPBACK 0 0 LOOPBACK_EN_REG 0 0 REFGEN_EN_REG 0 0 CLK_DIV_EN_REG 0 0 DATA_EN_REG_INT 0 0 CLK_EN_REG 0 0 SERIAL_EN_REG 0 0 OVRD_EN 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR2_LANEX_ANA_TX_ALT_BUS 2 0x90e2 6 0 4294967295 DRV_SOURCE_REG 0 0 OVRD_ALT_BUS 0 0 ATB_S_ENABLE 0 0 TX_ALT_RINGO 0 0 JTAG_DATA_REG 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR2_LANEX_ANA_TX_ATB1 2 0x90e3 9 0 4294967295 MEAS_ATB_GD 0 0 MEAS_ATB_VDDH 0 0 OVERRIDE_RXDETREF 0 0 MEAS_ATB_VPTX 0 0 OVERRIDE_REGREF 0 0 MEAS_ATB_VREG_DRV 0 0 MEAS_ATB_VREG 0 0 MEAS_ATB_VPH_HALF 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR2_LANEX_ANA_TX_ATB2 2 0x90e4 9 0 4294967295 MEAS_ATB_VCM 0 0 MEAS_ATB_CAL_VDAC_CM 0 0 MEAS_ATB_CAL_VDAC_DIFF 0 0 MEAS_ATB_TXM 0 0 MEAS_ATB_TXP 0 0 MEAS_ATB_RXDETREF 0 0 LFPS_HIGH_PRIORITY 0 0 OSC_DIV4_EN 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR2_LANEX_ANA_TX_DCC_DAC 2 0x90e5 2 0 4294967295 DCC_DAC_REG 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR2_LANEX_ANA_TX_DCC_CTRL1 2 0x90e6 7 0 4294967295 NC0 0 0 OVRD_DCC_DAC_CTRL_SEL 0 0 DCC_DAC_CTRL_SEL_REG 0 0 OVRD_DCC_DAC_CTRL_EN 0 0 DCC_DAC_CTRL_EN_REG 0 0 OVRD_DCC_DAC_REG 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR2_LANEX_ANA_TX_TERM_CODE 2 0x90e7 2 0 4294967295 TERM_CODE_REG_70 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR2_LANEX_ANA_TX_TERM_CODE_CTRL 2 0x90e8 8 0 4294967295 VREG_BOOST_1 0 0 OVRD_UPDATE_TERM 0 0 UPDATE_TERM_REG 0 0 OVRD_RESET_TERM 0 0 RESET_TERM_REG 0 0 OVRD_TERM_CODE 0 0 TERM_CODE_REG_98 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR2_LANEX_ANA_TX_OVRD_CLK 2 0x90e9 9 0 4294967295 VREG_BOOST_0 0 0 CLK_LB_EN_REG 0 0 OVRD_LB_EN 0 0 MPLLB_CLK_EN_REG 0 0 MPLLA_CLK_EN_REG 0 0 OVRD_MPLLAB_EN 0 0 WORD_CLK_EN_REG 0 0 OVRD_WORD_CLK_EN 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR2_LANEX_ANA_TX_MISC1 2 0x90ea 8 0 4294967295 MEAS_ATB_CAL_CLK_ALIGN 0 0 OVRD_DCC_DAC_CTRL_RANGE 0 0 DCC_DAC_CTRL_RANGE_REG 0 0 OVRD_VREF_SEL 0 0 VREF_SEL_REG 0 0 FORCE_ATB_TXM 0 0 FORCE_ATB_TXP 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR2_LANEX_ANA_TX_MISC2 2 0x90eb 8 0 4294967295 TX_PEAKING_LVL 0 0 VREG_CP_GAIN_CTRL 0 0 TX_SLEW_EN 0 0 EN_INV_POST 0 0 EN_INV_PRE 0 0 TX_VREG_EN_BYP 0 0 TX_VDRIVER_PULLDN_EN 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR2_LANEX_ANA_TX_MISC3 2 0x90ec 4 0 4294967295 TX_VREG_OVRD_RING_CTRL 0 0 TX_DCC_LOWV 0 0 NC7_2 2 7 RESERVED_15_8 8 15 ixDPCSSYS_CR2_LANEX_ANA_TX_RESERVED2 2 0x90ed 2 0 4294967295 NC7_0 0 7 RESERVED_15_8 8 15 ixDPCSSYS_CR2_LANEX_ANA_TX_RESERVED3 2 0x90ee 2 0 4294967295 NC7_0 0 7 RESERVED_15_8 8 15 ixDPCSSYS_CR2_LANEX_ANA_TX_RESERVED4 2 0x90ef 2 0 4294967295 NC7_0 0 7 RESERVED_15_8 8 15 ixDPCSSYS_CR2_LANEX_ANA_RX_CLK_1 2 0x90f0 8 0 4294967295 CDR_VCO_STARTUP_CODE 0 0 CDR_VCO_TEMP_COMP_EN 0 0 CDR_VCO_USE_UNCAL_BIAS 0 0 OVERRIDE_CDR_EN 0 0 OVRD_CLK_EN 0 0 CLK_EN_REG 0 0 NC7 7 7 RESERVED_15_8 8 15 ixDPCSSYS_CR2_LANEX_ANA_RX_CLK_2 2 0x90f1 5 0 4294967295 IQ_PHASE_ADJUST_REG 0 0 OVRD_IQ_PHASE_ADJUST 0 0 RX_LOOPBACK_CLK_REG 0 0 OVRD_RX_LOOPBACK_CLK 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR2_LANEX_ANA_RX_CDR_DES 2 0x90f2 7 0 4294967295 OVRD_WORD_CLK_EN 0 0 WORD_CLK_EN_REG 0 0 PHDET_ODD_REG 0 0 PHDET_EVEN_REG 0 0 SIGDET_VREF_EXT_EN 0 0 NC7_5 5 7 RESERVED_15_8 8 15 ixDPCSSYS_CR2_LANEX_ANA_RX_SLC_CTRL 2 0x90f3 3 0 4294967295 RX_SLICER_CTRL_O_REG 0 0 RX_SLICER_CTRL_E_REG 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR2_LANEX_ANA_RX_PWR_CTRL1 2 0x90f4 8 0 4294967295 OVRD_ACJT_EN 0 0 ACJT_EN_REG 0 0 OVRD_AFE_EN 0 0 AFE_EN_REG 0 0 AFE_CM_SEL 0 0 ATT_PULLDN_EN 0 0 NC7_7 7 7 RESERVED_15_8 8 15 ixDPCSSYS_CR2_LANEX_ANA_RX_PWR_CTRL2 2 0x90f5 9 0 4294967295 OVRD_DFE_EN 0 0 DFE_EN_REG 0 0 OVRD_DESERIAL_EN 0 0 DESERIAL_EN_REG 0 0 OVRD_LOOPBACK_EN 0 0 LOOPBACK_EN_REG 0 0 OVRD_FAST_START 0 0 FAST_START_REG 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR2_LANEX_ANA_RX_SQ 2 0x90f6 7 0 4294967295 SQ_CTRL_RESP_REG 0 0 OVRD_SQ_CTRL_RESP 0 0 NC4_3 3 4 SQ_CTRL_TRESH_REG 0 0 OVRD_SQ_CTRL_TRESH 0 0 AFE_LOOPBACK_SEL 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR2_LANEX_ANA_RX_CAL1 2 0x90f7 5 0 4294967295 DFE_TAPS_EN_REG 0 0 OVRD_DFE_TAPS_EN 0 0 CAL_MUXB_SEL_REG 0 0 OVRD_CAL_MUXB_SEL 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR2_LANEX_ANA_RX_CAL2 2 0x90f8 5 0 4294967295 AFE_PD_EQ_OFFSET 0 0 CAL_IDACS_USE_UNCAL 0 0 CAL_MUXA_SEL_REG 0 0 OVRD_CAL_MUXA_SEL 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR2_LANEX_ANA_RX_ATB_REGREF 2 0x90f9 8 0 4294967295 OVERRIDE_REGREF_VCO 0 0 OVERRIDE_REGREF_CLK 0 0 OVERRIDE_REGREF_IQC 0 0 BOOST_REGREF_IQC 0 0 OVRD_RX_SLICER_CTRL 0 0 OVRD_RX_TERM_AC_DCZ 0 0 RX_TERM_AC_DCZ_REG 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR2_LANEX_ANA_RX_ATB_MEAS1 2 0x90fa 9 0 4294967295 MASTER_ATB_EN 0 0 MEAS_ATB_VP 0 0 MEAS_ATB_GD 0 0 MEAS_ATB_VREG_VCO 0 0 MEAS_ATB_VREG_CLK 0 0 MEAS_ATB_VREG_IQC 0 0 REGS_FB_DIV_CTRL 0 0 RX_VREG_CLK_BYPASS 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR2_LANEX_ANA_RX_ATB_MEAS2 2 0x90fb 2 0 4294967295 MEAS_ATB_RX 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR2_LANEX_ANA_RX_ATB_MEAS3 2 0x90fc 7 0 4294967295 MEAS_ATB_CDR_VCO_GD 0 0 MEAS_ATB_CDR_VCO_VIREF_200U 0 0 MEAS_ATB_VIBIAS_CDR_VCO 0 0 MEAS_ATB_CDR_VCO_VOSC 0 0 MEAS_ATB_CAL_MUX 0 0 RX_VREG_OVERRIDE_RING_CTRL 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR2_LANEX_ANA_RX_ATB_MEAS4 2 0x90fd 3 0 4294967295 MEAS_ATB_CAL_VREF 0 0 NC7 7 7 RESERVED_15_8 8 15 ixDPCSSYS_CR2_LANEX_ANA_RX_ATB_FRC 2 0x90fe 2 0 4294967295 FRC_ATB_CAL_VREF 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR2_LANEX_ANA_RX_RESERVED1 2 0x90ff 2 0 4294967295 NC7_0 0 7 RESERVED_15_8 8 15 ixDPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN 2 0xe000 12 0 4294967295 PSTATE 0 1 LPD 2 2 WIDTH 3 4 RATE 5 7 MPLLB_SEL 8 8 MPLL_EN 9 9 OVRD_EN 10 10 MSTR_MPLLA_STATE 11 11 MSTR_MPLLB_STATE 12 12 MSTR_MPLL_OVRD_EN 13 13 TX_ASYNC_EN_OVR_VAL 14 14 TX_ASYNC_EN_OVR_EN 15 15 ixDPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1 2 0xe001 13 0 4294967295 RESET_OVRD_VAL 0 0 RESET_OVRD_EN 1 1 REQ_OVRD_VAL 2 2 REQ_OVRD_EN 3 3 DETRX_REQ_OVRD_VAL 4 4 DETRX_REQ_OVRD_EN 5 5 VBOOST_EN_OVRD_VAL 6 6 VBOOST_EN_OVRD_EN 7 7 IBOOST_LVL_OVRD_VAL 8 11 IBOOST_LVL_OVRD_EN 12 12 TX_BEACON_EN_OVR_VAL 13 13 TX_BEACON_EN_OVR_EN 14 14 RESERVED_15_15 15 15 ixDPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_PCS_IN 2 0xe002 12 0 4294967295 RESET 0 0 REQ 1 1 PSTATE 2 3 LPD 4 4 WIDTH 5 6 RATE 7 9 MPLLB_SEL 10 10 MPLL_EN 11 11 MSTR_MPLLA_STATE 12 12 MSTR_MPLLB_STATE 13 13 DETRX_REQ 14 14 RESERVED_15_15 15 15 ixDPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_OVRD_OUT 2 0xe003 6 0 4294967295 ACK 0 0 DETRX_RESULT 1 1 EN_CTL 2 2 TX_DWORD_CLK_SYNC_OVRD_VAL 3 3 TX_DWORD_CLK_SYNC_OVRD_EN 4 4 RESERVED_15_5 5 15 ixDPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_PCS_OUT 2 0xe004 2 0 4294967295 ACK 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN 2 0xe005 12 0 4294967295 RATE 0 1 WIDTH 2 3 PSTATE 4 5 LPD 6 6 OVRD_EN 7 7 ADAPT_AFE_EN 8 8 ADAPT_DFE_EN 9 9 LANE_RX2TX_PAR_LB_EN_OVRD_VAL 10 10 LANE_RX2TX_PAR_LB_EN_OVRD_EN 11 11 RX_DATA_EN_OVRD_VAL_R 12 12 RX_DATA_EN_OVRD_EN_R 13 13 RESERVED_15_14 14 15 ixDPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1 2 0xe006 12 0 4294967295 RESET_OVRD_VAL 0 0 RESET_OVRD_EN 1 1 REQ_OVRD_VAL 2 2 REQ_OVRD_EN 3 3 RX_LOS_THRSHLD_OVRD_VAL 4 6 RX_LOS_THRSHLD_OVRD_EN 7 7 ADAPT_REQ 8 8 ADAPT_REQ_OVRD_EN 9 9 ADAPT_CONT 10 10 OFFCAN_CONT 11 11 CONT_OVRD_EN 12 12 RESERVED_15_13 13 15 ixDPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_2 2 0xe007 4 0 4294967295 VCO_LD_VAL_OVRD 0 12 VCO_LD_VAL_OVRD_EN 13 13 VCO_LOWFREQ_VAL_OVRD 14 14 VCO_LOWFREQ_VAL_OVRD_EN 15 15 ixDPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_3 2 0xe008 3 0 4294967295 REF_LD_VAL_OVRD 0 6 REF_LD_VAL_OVRD_EN 7 7 RESERVED_15_8 8 15 ixDPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_PCS_IN 2 0xe009 13 0 4294967295 REQ 0 0 RATE 1 2 WIDTH 3 4 PSTATE 5 6 LPD 7 7 CDR_VCO_LOWFREQ 8 8 ADAPT_AFE_EN 9 9 ADAPT_DFE_EN 10 10 ADAPT_REQ 11 11 ADAPT_CONT 12 12 OFFCAN_CONT 13 13 RESET 14 14 RESERVED_15_15 15 15 ixDPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_1 2 0xe00a 2 0 4294967295 REF_LD_VAL 0 6 RESERVED_15_7 7 15 ixDPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_2 2 0xe00b 2 0 4294967295 VCO_LD_VAL 0 12 RESERVED_15_13 13 15 ixDPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_3 2 0xe00c 4 0 4294967295 EQ_ATT_LVL 0 2 EQ_VGA1_GAIN 3 6 EQ_VGA2_GAIN 7 10 EQ_CTLE_BOOST 11 15 ixDPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_4 2 0xe00d 3 0 4294967295 EQ_CTLE_POLE 0 2 EQ_DFE_TAP1 3 10 RESERVED_15_11 11 15 ixDPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT 2 0xe00e 3 0 4294967295 ACK 0 0 EN_CTL 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_PCS_OUT 2 0xe00f 2 0 4294967295 ACK 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_ADAPT_ACK 2 0xe010 2 0 4294967295 RX_ADAPT_ACK 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_ADAPT_FOM 2 0xe011 2 0 4294967295 RX_ADAPT_FOM 0 7 RESERVED_15_8 8 15 ixDPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_TXPRE_DIR 2 0xe012 2 0 4294967295 RX_TXPRE_DIR 0 1 RESERVED_15_2 2 15 ixDPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_TXMAIN_DIR 2 0xe013 2 0 4294967295 RX_TXMAIN_DIR 0 1 RESERVED_15_2 2 15 ixDPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_TXPOST_DIR 2 0xe014 2 0 4294967295 RX_TXPOST_DIR 0 1 RESERVED_15_2 2 15 ixDPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_LANE_NUMBER 2 0xe015 2 0 4294967295 LANE_NUMBER 0 3 RESERVED_15_4 4 15 ixDPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RESERVED_1 2 0xe016 1 0 4294967295 RESERVED_REG_1 0 15 ixDPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RESERVED_2 2 0xe017 1 0 4294967295 RESERVED_REG_2 0 15 ixDPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN 2 0xe018 16 0 4294967295 RX_RESET_ATE_OVRD_VAL 0 0 RX_RESET_ATE_OVRD_EN 1 1 TX_RESET_ATE_OVRD_VAL 2 2 TX_RESET_ATE_OVRD_EN 3 3 RX_REQ_ATE_OVRD_VAL 4 4 RX_REQ_ATE_OVRD_EN 5 5 TX_REQ_ATE_OVRD_VAL 6 6 TX_REQ_ATE_OVRD_EN 7 7 RX_ADAPT_AFE_EN_OVRD_VAL 8 8 RX_ADAPT_AFE_EN_OVRD_EN 9 9 RX_ADAPT_DFE_EN_OVRD_VAL 10 10 RX_ADAPT_DFE_EN_OVRD_EN 11 11 TX_DATA_EN_ATE_OVRD_VAL 12 12 TX_DATA_EN_ATE_OVRD_EN 13 13 RX_DATA_EN_ATE_OVRD_VAL 14 14 RX_DATA_EN_ATE_OVRD_EN 15 15 ixDPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN 2 0xe019 3 0 4294967295 RX_EQ_DELTA_IQ_OVRD_VAL 0 3 RX_EQ_DELTA_IQ_OVRD_EN 4 4 RESERVED_15_5 5 15 ixDPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN 2 0xe01a 5 0 4294967295 RX_TERM_CTRL_OVRD_VAL 0 2 RX_TERM_CTRL_OVRD_EN 3 3 TX_TERM_CTRL_OVRD_VAL 4 6 TX_TERM_CTRL_OVRD_EN 7 7 RESERVED_15_8 8 15 ixDPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TXRX_TERM_CTRL_IN 2 0xe01b 3 0 4294967295 RX_TERM_CTRL 0 2 TX_TERM_CTRL 3 5 RESERVED_15_6 6 15 ixDPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT_1 2 0xe01c 2 0 4294967295 RX_CLK_EN 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_EQ_OVRD_IN_1 2 0xe01d 4 0 4294967295 RX_EQ_AFE_GAIN_OVRD_VAL 0 3 RX_EQ_ATT_LVL_OVRD_VAL 4 6 RX_EQ_OVRD_EN 7 7 RESERVED_15_8 8 15 ixDPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_EQ_OVRD_IN_2 2 0xe01e 3 0 4294967295 RX_EQ_DFE_TAP1_OVRD_VAL 0 7 RX_EQ_CTLE_BOOST_OVRD_VAL 8 12 RESERVED_15_13 13 15 ixDPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_PH2_CAL 2 0xe01f 4 0 4294967295 PH2_CAL_ACK_VAL 0 0 PH2_CAL_REQ_VAL 1 1 PH2_CAL_REQ_OVRD_VAL 2 2 RESERVED_15_3 3 15 ixDPCSSYS_CR2_RAWLANEX_DIG_FSM_FSM_OVRD_CTL 2 0xe020 5 0 4294967295 FSM_JMP_ADDR 0 11 FSM_JMP_EN 12 12 FSM_CMD_START 13 13 FSM_OVRD_EN 14 14 FSM_BREAK 15 15 ixDPCSSYS_CR2_RAWLANEX_DIG_FSM_MEM_ADDR_MON 2 0xe021 1 0 4294967295 MEM_ADDR 0 15 ixDPCSSYS_CR2_RAWLANEX_DIG_FSM_STATUS_MON 2 0xe022 8 0 4294967295 STATE 0 4 CMD_RDY 5 5 ALU_OVFLW 6 6 ALU_RES_EQ0 7 7 WAIT_CNT_EQ0 8 8 WRMSK_DISABLED 9 9 RDMSK_DISABLED 10 10 RESERVED_15_11 11 15 ixDPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_RX_STARTUP_CAL 2 0xe023 2 0 4294967295 FAST_RX_STARTUP_CAL 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_RX_ADAPT 2 0xe024 2 0 4294967295 FAST_RX_ADAPT 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_RX_AFE_CAL 2 0xe025 2 0 4294967295 FAST_RX_AFE_CAL 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_RX_DFE_CAL 2 0xe026 2 0 4294967295 FAST_RX_DFE_CAL 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_RX_BYPASS_CAL 2 0xe027 2 0 4294967295 FAST_RX_BYPASS_CAL 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_RX_REFLVL_CAL 2 0xe028 2 0 4294967295 FAST_RX_REFLVL_CAL 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_RX_IQ_CAL 2 0xe029 2 0 4294967295 FAST_RX_IQ_CAL 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_RX_AFE_ADAPT 2 0xe02a 2 0 4294967295 FAST_RX_AFE_ADAPT 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_RX_DFE_ADAPT 2 0xe02b 2 0 4294967295 FAST_RX_DFE_ADAPT 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_SUP 2 0xe02c 2 0 4294967295 FAST_SUP 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_TX_CMN_MODE 2 0xe02d 2 0 4294967295 FAST_TX_CMN_MODE 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_TX_RXDET 2 0xe02e 2 0 4294967295 FAST_TX_RXDET 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_RX_PWRUP 2 0xe02f 2 0 4294967295 FAST_RX_PWRUP 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_RX_VCO_WAIT 2 0xe030 2 0 4294967295 FAST_RX_VCO_WAIT 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_RX_VCO_CAL 2 0xe031 2 0 4294967295 FAST_RX_VCO_CAL 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR2_RAWLANEX_DIG_FSM_CMNCAL_MPLL_STATUS 2 0xe032 3 0 4294967295 CMNCAL_MPLL_INIT 0 0 CMNCAL_MPLL_DONE 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_RX_CONT_CAL_ADAPT 2 0xe033 2 0 4294967295 FAST_RX_CONT_CAL_ADAPT 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_RX_CONT_ADAPT 2 0xe034 2 0 4294967295 FAST_RX_CONT_ADAPT 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_RX_CONT_DATA_CAL 2 0xe035 2 0 4294967295 FAST_RX_CONT_DATA_CAL 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_RX_CONT_PHASE_CAL 2 0xe036 2 0 4294967295 FAST_RX_CONT_PHASE_CAL 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_RX_CONT_AFE_CAL 2 0xe037 2 0 4294967295 FAST_RX_CONT_AFE_CAL 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_FLAGS 2 0xe038 12 0 4294967295 TX_FAST_DCC_CAL 0 0 RX_FAST_DCC_CAL 1 1 RX_FAST_VPHUD_CAL 2 2 RX_FAST_VREF_CAL 3 3 RX_FAST_SIGDET_CAL 4 4 RESERVED_2 5 7 TX_FAST_CONT_DCC_CAL 8 8 RX_FAST_CONT_DCC_CAL 9 9 RX_FAST_CONT_VPHUD_CAL 10 10 RX_FAST_CONT_VREF_CAL 11 11 RESERVED_1 12 14 TX_SKIP_SUP_CAL 15 15 ixDPCSSYS_CR2_RAWLANEX_DIG_FSM_CR_LOCK 2 0xe039 3 0 4294967295 CR_REG_LOCK 0 0 CR_MEM_LOCK 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR2_RAWLANEX_DIG_FSM_TX_DCC_FLAGS 2 0xe03a 4 0 4294967295 RATE 0 0 DIV 1 1 MPLL 2 2 RESERVED_15_3 3 15 ixDPCSSYS_CR2_RAWLANEX_DIG_FSM_TX_DCC_STATUS 2 0xe03b 2 0 4294967295 FLAG 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR2_RAWLANEX_DIG_FSM_OCLA 2 0xe03c 4 0 4294967295 PC_EN 0 0 REG_BANK1_EN 1 1 REG_BANK2_EN 2 2 RESERVED_15_3 3 15 ixDPCSSYS_CR2_RAWLANEX_DIG_FSM_TX_EQ_UPDATE_FLAG 2 0xe03d 2 0 4294967295 TX_EQ_UPDATE_FLAG 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR2_RAWLANEX_DIG_FSM_CMNCAL_RCAL_STATUS 2 0xe03e 3 0 4294967295 CMNCAL_RCAL_INIT 0 0 CMNCAL_RCAL_DONE 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR2_RAWLANEX_DIG_FSM_RX_IQ_PHASE_OFFSET 2 0xe03f 2 0 4294967295 RX_IQ_PHASE_OFFSET 0 3 RESERVED_15_4 4 15 ixDPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_RESET_RTN_REQ 2 0xe040 2 0 4294967295 RESET_RTN_REQ 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_RX_RESET_IRQ 2 0xe041 2 0 4294967295 RX_RESET 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_RX_REQ_IRQ 2 0xe042 2 0 4294967295 RX_REQ 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_RX_RATE_IRQ 2 0xe043 2 0 4294967295 RX_RATE_IRQ 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_RX_PSTATE_IRQ 2 0xe044 2 0 4294967295 RX_PSTATE_IRQ 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ 2 0xe045 2 0 4294967295 RX_ADAPT_REQ_IRQ 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ 2 0xe046 2 0 4294967295 RX_ADAPT_DIS_IRQ 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_RX_RESET_IRQ_CLR 2 0xe047 2 0 4294967295 RX_RESET_IRQ_CLR 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_RX_REQ_IRQ_CLR 2 0xe048 2 0 4294967295 RX_REQ_IRQ_CLR 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_RX_RATE_IRQ_CLR 2 0xe049 2 0 4294967295 RX_RATE_IRQ_CLR 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR 2 0xe04a 2 0 4294967295 RX_PSTATE_IRQ_CLR 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR 2 0xe04b 2 0 4294967295 RX_ADAPT_REQ_IRQ_CLR 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR 2 0xe04c 2 0 4294967295 RX_ADAPT_DIS_IRQ_CLR 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK 2 0xe04d 12 0 4294967295 RX_REQ_IRQ_MSK 0 0 RX_RATE_IRQ_MSK 1 1 RX_PSTATE_IRQ_MSK 2 2 RX_ADAPT_REQ_IRQ_MSK 3 3 RX_ADAPT_DIS_IRQ_MSK 4 4 RX_RESET_IRQ_MSK 5 5 LANE_XCVR_MODE_IRQ_MSK 6 6 RX_PH2_CAL_REQ_IRQ_MSK 7 7 RX_PH2_CAL_DIS_IRQ_MSK 8 8 LANE_RX2TX_SER_LB_EN_IRQ_MSK 9 9 DCC_ONDMD_IRQ_MSK 10 10 RESERVED_15_11 11 15 ixDPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK_2 2 0xe04e 3 0 4294967295 TX_RESET_IRQ_MSK 0 0 TX_REQ_IRQ_MSK 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ 2 0xe04f 2 0 4294967295 LANE_XCVR_MODE_IRQ 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR 2 0xe050 2 0 4294967295 LANE_XCVR_MODE_IRQ_CLR 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ 2 0xe051 2 0 4294967295 RX_PH2_CAL_REQ_IRQ 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ 2 0xe052 2 0 4294967295 RX_PH2_CAL_DIS_IRQ 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR 2 0xe053 2 0 4294967295 RX_PH2_CAL_REQ_IRQ_CLR 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR 2 0xe054 2 0 4294967295 RX_PH2_CAL_DIS_IRQ_CLR 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ 2 0xe055 2 0 4294967295 LANE_RX2TX_SER_LB_EN_IRQ 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR 2 0xe056 2 0 4294967295 LANE_RX2TX_SER_LB_EN_IRQ_CLR 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_DCC_ONDMD_IRQ 2 0xe057 2 0 4294967295 IRQ 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_TX_RESET_IRQ 2 0xe058 2 0 4294967295 TX_RESET 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_TX_REQ_IRQ 2 0xe059 2 0 4294967295 TX_REQ 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_TX_RESET_IRQ_CLR 2 0xe05a 2 0 4294967295 TX_RESET_IRQ_CLR 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_TX_REQ_IRQ_CLR 2 0xe05b 2 0 4294967295 TX_REQ_IRQ_CLR 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_LANE_OVRD_IN 2 0xe060 4 0 4294967295 LANE_MPLLA_EN_IN 0 0 LANE_MPLLB_EN_IN 1 1 LANE_OVRD_EN 2 2 RESERVED_15_3 3 15 ixDPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_LANE_OVRD_OUT 2 0xe061 4 0 4294967295 LANE_MPLLA_EN_OUT 0 0 LANE_MPLLB_EN_OUT 1 1 LANE_OVRD_EN 2 2 RESERVED_15_3 3 15 ixDPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_SUP_OVRD_IN 2 0xe062 4 0 4294967295 MPLLA_STATE 0 0 MPLLB_STATE 1 1 SUP_STATE_OVRD_EN 2 2 RESERVED_15_3 3 15 ixDPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_SUP_PMA_IN 2 0xe063 3 0 4294967295 MPLLA_STATE 0 0 MPLLB_STATE 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT 2 0xe064 16 0 4294967295 TX_REQ_OVRD_VAL 0 0 TX_REQ_OVRD_EN 1 1 TX_RESET_OVRD_VAL 2 2 TX_RESET_OVRD_EN 3 3 TX_BEACON_EN_OVRD_VAL 4 4 TX_BEACON_EN_OVRD_EN 5 5 TX_ASYNC_DRV_EN_OVRD_VAL 6 6 TX_ASYNC_DRV_EN_OVRD_EN 7 7 TX_ASYNC_EN_OVRD_VAL 8 8 TX_ASYNC_EN_OVRD_EN 9 9 TX_DWORD_CLK_SYNC_OVRD_VAL 10 10 TX_DWORD_CLK_SYNC_OVRD_EN 11 11 LANE_TX2RX_SER_LB_EN_OVRD_VAL 12 12 LANE_TX2RX_SER_LB_EN_OVRD_EN 13 13 TX_PMA_DATA_EN_OVRD_VAL_R 14 14 TX_PMA_DATA_EN_OVRD_EN_R 15 15 ixDPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_TX_PMA_IN 2 0xe065 2 0 4294967295 ACK 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT 2 0xe066 9 0 4294967295 RX_REQ_OVRD_VAL 0 0 RX_REQ_OVRD_EN 1 1 RX_RESET_OVRD_VAL 2 2 RX_RESET_OVRD_EN 3 3 LANE_RX2TX_PAR_LB_EN_OVRD_VAL 4 4 LANE_RX2TX_PAR_LB_EN_OVRD_EN 5 5 RX_PMA_DATA_EN_OVRD_VAL_R 6 6 RX_PMA_DATA_EN_OVRD_EN_R 7 7 RESERVED_15_8 8 15 ixDPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_RX_PMA_IN 2 0xe067 2 0 4294967295 ACK 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_LANE_RTUNE_CTL 2 0xe068 2 0 4294967295 LANE_RTUNE_REQ 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_SUP_PMA_IN_1 2 0xe069 2 0 4294967295 RTUNE_ACK 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_IN 2 0xe06a 9 0 4294967295 RX_PMA_PWM_WORD_CLK_R 0 0 RX_PMA_PWM_WORD_CLK_OVRD_EN 1 1 RX_PMA_PWM_DATA_R 2 2 RX_PMA_PWM_DATA_OVRD_EN 3 3 RX_PMA_PWM_CLK_R 4 4 RX_PMA_PWM_CLK_OVRD_EN 5 5 RX_PMA_TERM_CTL_R 6 7 RX_PMA_TERM_CTL_OVRD_EN 8 8 RESERVED_15_9 9 15 ixDPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_OUT 2 0xe06b 7 0 4294967295 RX_PMA_PWM_EN 0 0 RX_PMA_PWM_EN_OVRD_EN 1 1 RX_PMA_PWM_CLK_SEL 2 3 RX_PMA_PWM_CLK_SEL_OVRD_EN 4 4 RX_PMA_ASYNC_EN 5 5 RX_PMA_ASYNC_EN_OVRD_EN 6 6 RESERVED_15_7 7 15 ixDPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_RX_ADAPT_OVRD_OUT 2 0xe06c 3 0 4294967295 RX_PMA_IQ_PHASE_ADJUST_MAP_OVRD_VAL 0 6 RX_PMA_IQ_PHASE_ADJUST_MAP_OVRD_EN 7 7 RESERVED_15_8 8 15 ixDPCSSYS_CR2_RAWLANEX_DIG_TX_CTL_TX_FSM_CTL 2 0xe080 6 0 4294967295 TX_WAIT_MPLL_OFF_TIME 0 6 TX_P2_ALLOW_RXDET 7 7 TX_P1_ALLOW_RXDET 8 8 TX_P0S_ALLOW_RXDET 9 9 TX_P0_ALLOW_RXDET 10 10 RESERVED_15_11 11 15 ixDPCSSYS_CR2_RAWLANEX_DIG_TX_CTL_TX_CLK_CTL 2 0xe081 4 0 4294967295 TX_CLK_EN 0 0 TX_CLK_SEL 1 4 ASYNC_BEACON_WAIT_TIME 5 10 RESERVED_15_11 11 15 ixDPCSSYS_CR2_RAWLANEX_DIG_TX_CTL_TX_DCC_CONT_STATUS 2 0xe082 2 0 4294967295 ENABLE 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR2_RAWLANEX_DIG_TX_CTL_OCLA 2 0xe083 2 0 4294967295 FSM_EN 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR2_RAWLANEX_DIG_TX_CTL_UPCS_OCLA 2 0xe084 3 0 4294967295 DATA_EN 0 1 CLK_EN 2 2 RESERVED_15_3 3 15 ixDPCSSYS_CR2_RAWLANEX_DIG_RX_CTL_RX_FSM_CTL 2 0xe0a0 3 0 4294967295 EN_RX_CTL_FSM 0 0 RATE_CHG_IN_P1 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR2_RAWLANEX_DIG_RX_CTL_RX_LOS_MASK_CTL 2 0xe0a1 2 0 4294967295 RX_LOS_MASK_CNT 0 8 RESERVED_15_9 9 15 ixDPCSSYS_CR2_RAWLANEX_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL 2 0xe0a2 2 0 4294967295 RX_DATA_EN_OVRD_CNT 0 4 INT_REF_TRCK_CNT 5 15 ixDPCSSYS_CR2_RAWLANEX_DIG_RX_CTL_OFFCAN_CONT_STATUS 2 0xe0a3 2 0 4294967295 ENABLE 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR2_RAWLANEX_DIG_RX_CTL_ADAPT_CONT_STATUS 2 0xe0a4 2 0 4294967295 ENABLE 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR2_RAWLANEX_DIG_RX_CTL_UPCS_OCLA 2 0xe0a5 3 0 4294967295 DATA_EN 0 2 CLK_EN 3 3 RESERVED_15_4 4 15 ixDPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN 2 0xe0c0 11 0 4294967295 RATE_OVRD_VAL 0 1 RATE_OVRD_EN 2 2 WIDTH_OVRD_VAL 3 4 WIDTH_OVRD_EN 5 5 PSTATE_OVRD_VAL 6 7 PSTATE_OVRD_EN 8 8 LPD_OVRD_VAL 9 9 LPD_OVRD_EN 10 10 LANE_RX2TX_PAR_LB_EN_OVRD_VAL 11 11 LANE_RX2TX_PAR_LB_EN_OVRD_EN 12 12 RESERVED_15_13 13 15 ixDPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN 2 0xe0c1 12 0 4294967295 PSTATE 0 1 LPD 2 2 WIDTH 3 4 RATE 5 7 MPLLB_SEL 8 8 MPLL_EN 9 9 OVRD_EN 10 10 MSTR_MPLLA_STATE 11 11 MSTR_MPLLB_STATE 12 12 MSTR_MPLL_OVRD_EN 13 13 TX_ASYNC_EN_OVR_VAL 14 14 TX_ASYNC_EN_OVR_EN 15 15 ixDPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1 2 0xe0c2 13 0 4294967295 DETRX_REQ_OVRD_VAL 0 0 DETRX_REQ_OVRD_EN 1 1 VBOOST_EN_OVRD_VAL 2 2 VBOOST_EN_OVRD_EN 3 3 IBOOST_LVL_OVRD_VAL 4 7 IBOOST_LVL_OVRD_EN 8 8 TX_BEACON_EN_OVR_VAL 9 9 TX_BEACON_EN_OVR_EN 10 10 LANE_TX2RX_SER_LB_EN_OVRD_VAL 11 11 LANE_TX2RX_SER_LB_EN_OVRD_EN 12 12 TX_ASYNC_DATA_OVRD_VAL 13 13 TX_ASYNC_DATA_OVRD_EN 14 14 RESERVED_15_15 15 15 ixDPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_MASTER_MPLL_LOOP 2 0xe0c3 3 0 4294967295 MPLLB_LOOP_EN 0 0 MPLLA_LOOP_EN 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1 2 0xe0c4 11 0 4294967295 RESERVED 0 1 RX_LOS_LFPS_EN_OVRD_VAL 2 2 RX_LOS_LFPS_EN_OVRD_EN 3 3 RX_LOS_THRSHLD_OVRD_VAL 4 6 RX_LOS_THRSHLD_OVRD_EN 7 7 ADAPT_REQ 8 8 ADAPT_REQ_OVRD_EN 9 9 ADAPT_CONT 10 10 OFFCAN_CONT 11 11 CONT_OVRD_EN 12 12 RESERVED_15_13 13 15 ixDPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_2 2 0xe0c5 4 0 4294967295 VCO_LD_VAL_OVRD 0 12 VCO_LD_VAL_OVRD_EN 13 13 VCO_LOWFREQ_VAL_OVRD 14 14 VCO_LOWFREQ_VAL_OVRD_EN 15 15 ixDPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_3 2 0xe0c6 3 0 4294967295 REF_LD_VAL_OVRD 0 6 REF_LD_VAL_OVRD_EN 7 7 RESERVED_15_8 8 15 ixDPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT_2 2 0xe0c7 3 0 4294967295 RX_VALID 0 0 RX_VALID_OVRD_EN 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_2 2 0xe0c8 7 0 4294967295 LANE_TX2RX_SER_LB_EN_OVRD_VAL 0 0 LANE_TX2RX_SER_LB_EN_OVRD_EN 1 1 TX_DATA_EN_OVRD_VAL_R 2 2 TX_DATA_EN_OVRD_EN_R 3 3 TX_ASYNC_DATA_OVRD_VAL_R 4 4 TX_ASYNC_DATA_OVRD_EN_R 5 5 RESERVED_15_6 6 15 ixDPCSSYS_CR3_SUP_DIG_IDCODE_LO 2 0x0 1 0 4294967295 DATA 0 0 ixDPCSSYS_CR3_SUP_DIG_IDCODE_HI 2 0x1 1 0 4294967295 DATA 0 0 ixDPCSSYS_CR3_SUP_DIG_REFCLK_OVRD_IN 2 0x2 12 0 4294967295 REF_CLK_EN 0 0 REF_CLK_EN_OVRD_EN 1 1 REF_USE_PAD 2 2 REF_USE_PAD_OVRD_EN 3 3 REF_CLK_RANGE 4 8 REF_CLK_RANGE_OVRD_EN 9 9 BG_EN 10 10 BG_EN_OVRD_EN 11 11 HDMIMODE_EN 12 12 HDMIMODE_ENABLE_OVRD_EN 13 13 SUP_PRE_HP_OVRD 14 14 SUP_PRE_HP_OVRD_EN 15 15 ixDPCSSYS_CR3_SUP_DIG_MPLLA_DIV_CLK_OVRD_IN 2 0x3 4 0 4294967295 MPLLA_DIV_CLK_EN 0 0 MPLLA_DIV_MULTIPLIER 1 8 MPLLA_DIV_OVRD_EN 9 9 RESERVED_15_10 10 15 ixDPCSSYS_CR3_SUP_DIG_MPLLA_HDMI_CLK_OVRD_IN 2 0x4 4 0 4294967295 MPLLA_HDMI_PIXEL_CLK_DIV 0 1 MPLLA_HDMI_DIV 2 4 MPLLA_HDMI_OVRD_EN 5 5 RESERVED_15_6 6 15 ixDPCSSYS_CR3_SUP_DIG_MPLLB_DIV_CLK_OVRD_IN 2 0x5 4 0 4294967295 MPLLB_DIV_CLK_EN 0 0 MPLLB_DIV_MULTIPLIER 1 8 MPLLB_DIV_OVRD_EN 9 9 RESERVED_15_10 10 15 ixDPCSSYS_CR3_SUP_DIG_MPLLB_HDMI_CLK_OVRD_IN 2 0x6 4 0 4294967295 MPLLB_HDMI_PIXEL_CLK_DIV 0 1 MPLLB_HDMI_DIV 2 4 MPLLB_HDMI_OVRD_EN 5 5 RESERVED_15_6 6 15 ixDPCSSYS_CR3_SUP_DIG_MPLLA_OVRD_IN_0 2 0x7 12 0 4294967295 MPLLA_EN 0 0 MPLLA_DIV5_CLK_EN 1 1 MPLLA_TX_CLK_DIV 2 4 OVRD_EN 5 5 MPLLA_V2I 6 7 MPLLA_STANDBY 8 8 MPLLA_FREQ_VCO 9 10 MPLLA_CAL_FORCE 11 11 MPLL_FRACN_EN 12 12 MPLLA_CLK_SYNC_OVRD 13 13 MPLLA_CLK_SYNC_OVRD_EN 14 14 RESERVED_15_15 15 15 ixDPCSSYS_CR3_SUP_DIG_MPLLA_OVRD_IN_1 2 0x8 2 0 4294967295 MPLLA_MULTIPLIER 0 11 RESERVED_15_12 12 15 ixDPCSSYS_CR3_SUP_DIG_MPLLA_OVRD_IN_2 2 0x9 7 0 4294967295 MPLLA_SSC_EN 0 0 MPLLA_SSC_OVRD_EN 1 1 MPLLA_SSC_UP_SPREAD 2 2 MPLLA_PMIX_EN 3 3 MPLLA_WORD_DIV2_EN 4 4 MPLLA_FRACN_CFG_UPDATE_EN 5 5 RESERVED_15_6 6 15 ixDPCSSYS_CR3_SUP_DIG_MPLLA_SSC_PEAK_1 2 0xa 1 0 4294967295 MPLLA_SSC_PEAK_15_0 0 15 ixDPCSSYS_CR3_SUP_DIG_MPLLA_SSC_PEAK_2 2 0xb 2 0 4294967295 MPLLA_SSC_PEAK_19_16 0 3 RESERVED_15_4 4 15 ixDPCSSYS_CR3_SUP_DIG_MPLLA_SSC_STEPSIZE_1 2 0xc 1 0 4294967295 MPLLA_SSC_STEPSIZE_15_0 0 15 ixDPCSSYS_CR3_SUP_DIG_MPLLA_SSC_STEPSIZE_2 2 0xd 2 0 4294967295 MPLLA_SSC_STEPSIZE_20_16 0 4 RESERVED_15_5 5 15 ixDPCSSYS_CR3_SUP_DIG_MPLLA_OVRD_IN_3 2 0xe 1 0 4294967295 MPLLA_FRACN_QUOT 0 15 ixDPCSSYS_CR3_SUP_DIG_MPLLA_OVRD_IN_4 2 0xf 1 0 4294967295 MPLLA_FRACN_REM 0 15 ixDPCSSYS_CR3_SUP_DIG_MPLLA_OVRD_IN_5 2 0x10 1 0 4294967295 MPLLA_FRACN_DEN 0 15 ixDPCSSYS_CR3_SUP_DIG_MPLLA_CP_OVRD_IN 2 0x11 3 0 4294967295 MPLLA_CP_PROP 0 6 MPLLA_CP_INT 7 13 RESERVED_15_14 14 15 ixDPCSSYS_CR3_SUP_DIG_MPLLA_CP_GS_OVRD_IN 2 0x12 4 0 4294967295 MPLLA_CP_PROP_GS 0 6 MPLLA_CP_PROP_GS_OVR_EN 7 7 MPLLA_CP_INT_GS 8 14 MPLLA_CP_INT_GS_OVR_EN 15 15 ixDPCSSYS_CR3_SUP_DIG_MPLLB_OVRD_IN_0 2 0x13 12 0 4294967295 MPLLB_EN 0 0 MPLLB_DIV5_CLK_EN 1 1 MPLLB_TX_CLK_DIV 2 4 OVRD_EN 5 5 MPLLB_V2I 6 7 MPLLB_STANDBY 8 8 MPLLB_FREQ_VCO 9 10 MPLLB_CAL_FORCE 11 11 MPLL_FRACN_EN 12 12 MPLLB_CLK_SYNC_OVRD 13 13 MPLLB_CLK_SYNC_OVRD_EN 14 14 RESERVED_15_15 15 15 ixDPCSSYS_CR3_SUP_DIG_MPLLB_OVRD_IN_1 2 0x14 2 0 4294967295 MPLLB_MULTIPLIER 0 11 RESERVED_15_12 12 15 ixDPCSSYS_CR3_SUP_DIG_MPLLB_OVRD_IN_2 2 0x15 7 0 4294967295 MPLLB_SSC_EN 0 0 MPLLB_SSC_OVRD_EN 1 1 MPLLB_SSC_UP_SPREAD 2 2 MPLLB_PMIX_EN 3 3 MPLLB_WORD_DIV2_EN 4 4 MPLLB_FRACN_CFG_UPDATE_EN 5 5 RESERVED_15_6 6 15 ixDPCSSYS_CR3_SUP_DIG_MPLLB_SSC_PEAK_1 2 0x16 1 0 4294967295 MPLLB_SSC_PEAK_15_0 0 15 ixDPCSSYS_CR3_SUP_DIG_MPLLB_SSC_PEAK_2 2 0x17 2 0 4294967295 MPLLB_SSC_PEAK_19_16 0 3 RESERVED_15_4 4 15 ixDPCSSYS_CR3_SUP_DIG_MPLLB_SSC_STEPSIZE_1 2 0x18 1 0 4294967295 MPLLB_SSC_STEPSIZE_15_0 0 15 ixDPCSSYS_CR3_SUP_DIG_MPLLB_SSC_STEPSIZE_2 2 0x19 2 0 4294967295 MPLLB_SSC_STEPSIZE_20_16 0 4 RESERVED_15_5 5 15 ixDPCSSYS_CR3_SUP_DIG_MPLLB_OVRD_IN_3 2 0x1a 1 0 4294967295 MPLLB_FRACN_QUOT 0 15 ixDPCSSYS_CR3_SUP_DIG_MPLLB_OVRD_IN_4 2 0x1b 1 0 4294967295 MPLLB_FRACN_REM 0 15 ixDPCSSYS_CR3_SUP_DIG_MPLLB_OVRD_IN_5 2 0x1c 1 0 4294967295 MPLLB_FRACN_DEN 0 15 ixDPCSSYS_CR3_SUP_DIG_MPLLB_CP_OVRD_IN 2 0x1d 3 0 4294967295 MPLLB_CP_PROP 0 6 MPLLB_CP_INT 7 13 RESERVED_15_14 14 15 ixDPCSSYS_CR3_SUP_DIG_MPLLB_CP_GS_OVRD_IN 2 0x1e 4 0 4294967295 MPLLB_CP_PROP_GS 0 6 MPLLB_CP_PROP_GS_OVR_EN 7 7 MPLLB_CP_INT_GS 8 14 MPLLB_CP_INT_GS_OVR_EN 15 15 ixDPCSSYS_CR3_SUP_DIG_SUP_OVRD_IN 2 0x1f 8 0 4294967295 PRESCALER_OVRD_EN 0 0 RTUNE_REQ 1 1 RTUNE_OVRD_EN 2 2 TX_CAL_CODE 3 6 TX_CAL_CODE_EN 7 7 REF_ALT_CLK_LP_SEL_OVRD 8 8 REF_ALT_CLK_LP_SEL_OVRD_EN 9 9 RESERVED_15_10 10 15 ixDPCSSYS_CR3_SUP_DIG_PRESCALER_OVRD_IN 2 0x20 6 0 4294967295 DCO_RANGE 0 1 DCO_FINETUNE 2 7 REF_CLK_MPLLB_DIV 8 10 REF_CLK_MPLLA_DIV 11 13 REF_CLKDET_RESULT 14 14 REF_CLKDET_EN 15 15 ixDPCSSYS_CR3_SUP_DIG_SUP_OVRD_OUT 2 0x21 12 0 4294967295 RTUNE_ACK 0 0 RTUNE_ACK_OVRD_EN 1 1 MPLLA_STATE 2 2 MPLLA_STATE_OVRD_EN 3 3 MPLLB_STATE 4 4 MPLLB_STATE_OVRD_EN 5 5 BG_LANE_STATE 6 6 BG_LANE_STATE_OVRD_EN 7 7 BG_SUP_STATE 8 8 BG_SUP_STATE_OVRD_EN 9 9 REF_CLK_ACK 10 10 RESERVED_15_11 11 15 ixDPCSSYS_CR3_SUP_DIG_LVL_OVRD_IN 2 0x22 7 0 4294967295 RX_VREF_CTRL 0 2 RX_VREF_CTRL_EN 3 3 TX_VBOOST_LVL 4 6 TX_VBOOST_LVL_EN 7 7 SUP_RX_VCO_VREF_SEL_OVR 8 10 SUP_RX_VCO_VREF_SEL_OVR_EN 11 11 RESERVED_15_12 12 15 ixDPCSSYS_CR3_SUP_DIG_MPLLA_ASIC_IN_0 2 0x24 9 0 4294967295 MPLLA_EN 0 0 MPLLA_DIV5_CLK_EN 1 1 MPLLA_TX_CLK_DIV 2 4 MPLLA_V2I 5 6 MPLLA_STANDBY 7 7 MPLLA_FREQ_VCO 8 9 MPLLA_CAL_FORCE 10 10 MPLLA_FRACN_EN 11 11 RESERVED_15_12 12 15 ixDPCSSYS_CR3_SUP_DIG_MPLLA_ASIC_IN_1 2 0x25 2 0 4294967295 MPLLA_MULTIPLIER 0 11 RESERVED_15_12 12 15 ixDPCSSYS_CR3_SUP_DIG_MPLLA_ASIC_IN_2 2 0x26 7 0 4294967295 MPLLA_SSC_EN 0 0 MPLLA_SSC_UP_SPREAD 1 1 MPLLA_PMIX_EN 2 2 MPLLA_WORD_DIV2_EN 3 3 MPLLA_FRACN_CFG_UPDATE_EN 4 4 MPLLA_CLK_SYNC 5 5 RESERVED_15_6 6 15 ixDPCSSYS_CR3_SUP_DIG_MPLLA_ASIC_IN_3 2 0x27 1 0 4294967295 MPLLA_SSC_PEAK_15_0 0 15 ixDPCSSYS_CR3_SUP_DIG_MPLLA_ASIC_IN_4 2 0x28 2 0 4294967295 MPLLA_SSC_PEAK_19_16 0 3 RESERVED_15_4 4 15 ixDPCSSYS_CR3_SUP_DIG_MPLLA_ASIC_IN_5 2 0x29 1 0 4294967295 MPLLA_SSC_STEPSIZE_15_0 0 15 ixDPCSSYS_CR3_SUP_DIG_MPLLA_ASIC_IN_6 2 0x2a 2 0 4294967295 MPLLA_SSC_STEPSIZE_20_16 0 3 RESERVED_15_4 4 15 ixDPCSSYS_CR3_SUP_DIG_MPLLB_ASIC_IN_0 2 0x2b 9 0 4294967295 MPLLB_EN 0 0 MPLLB_DIV5_CLK_EN 1 1 MPLLB_TX_CLK_DIV 2 4 MPLLB_V2I 5 6 MPLLB_STANDBY 7 7 MPLLB_FREQ_VCO 8 9 MPLLB_CAL_FORCE 10 10 MPLLB_FRACN_EN 11 11 RESERVED_15_12 12 15 ixDPCSSYS_CR3_SUP_DIG_MPLLB_ASIC_IN_1 2 0x2c 2 0 4294967295 MPLLB_MULTIPLIER 0 11 RESERVED_15_12 12 15 ixDPCSSYS_CR3_SUP_DIG_MPLLB_ASIC_IN_2 2 0x2d 7 0 4294967295 MPLLB_SSC_EN 0 0 MPLLB_SSC_UP_SPREAD 1 1 MPLLB_PMIX_EN 2 2 MPLLB_WORD_DIV2_EN 3 3 MPLLB_FRACN_CFG_UPDATE_EN 4 4 MPLLB_CLK_SYNC 5 5 RESERVED_15_6 6 15 ixDPCSSYS_CR3_SUP_DIG_MPLLB_ASIC_IN_3 2 0x2e 1 0 4294967295 MPLLB_SSC_PEAK_15_0 0 15 ixDPCSSYS_CR3_SUP_DIG_MPLLB_ASIC_IN_4 2 0x2f 2 0 4294967295 MPLLB_SSC_PEAK_19_16 0 3 RESERVED_15_4 4 15 ixDPCSSYS_CR3_SUP_DIG_MPLLB_ASIC_IN_5 2 0x30 1 0 4294967295 MPLLB_SSC_STEPSIZE_15_0 0 15 ixDPCSSYS_CR3_SUP_DIG_MPLLB_ASIC_IN_6 2 0x31 2 0 4294967295 MPLLB_SSC_STEPSIZE_20_16 0 3 RESERVED_15_4 4 15 ixDPCSSYS_CR3_SUP_DIG_MPLLA_DIV_CLK_ASIC_IN 2 0x32 3 0 4294967295 MPLLA_DIV_CLK_EN 0 0 MPLLA_DIV_MULTIPLIER 1 8 RESERVED_15_9 9 15 ixDPCSSYS_CR3_SUP_DIG_MPLLA_HDMI_CLK_ASIC_IN 2 0x33 3 0 4294967295 MPLLA_HDMI_PIXEL_CLK_DIV 0 1 MPLLA_HDMI_DIV 2 4 RESERVED_15_5 5 15 ixDPCSSYS_CR3_SUP_DIG_MPLLB_DIV_CLK_ASIC_IN 2 0x34 3 0 4294967295 MPLLB_DIV_CLK_EN 0 0 MPLLB_DIV_MULTIPLIER 1 8 RESERVED_15_9 9 15 ixDPCSSYS_CR3_SUP_DIG_MPLLB_HDMI_CLK_ASIC_IN 2 0x35 3 0 4294967295 MPLLB_HDMI_PIXEL_CLK_DIV 0 1 MPLLB_HDMI_DIV 2 4 RESERVED_15_5 5 15 ixDPCSSYS_CR3_SUP_DIG_ASIC_IN 2 0x36 12 0 4294967295 PHY_RESET 0 0 REF_CLK_EN 1 1 REF_USE_PAD 2 2 TEST_BURNIN 3 3 TEST_POWERDOWN 4 4 RTUNE_REQ 5 5 RTUNE_ACK 6 6 MPLLA_STATE 7 7 MPLLB_STATE 8 8 TEST_TX_REF_CLK_EN 9 9 REF_ALT_CLK_LP_SEL 10 10 RESERVED_15_11 11 15 ixDPCSSYS_CR3_SUP_DIG_LVL_ASIC_IN 2 0x37 4 0 4294967295 RX_VREF_CTRL 0 2 TX_VBOOST_LVL 3 5 SUP_RX_VCO_VREF_SEL 6 8 RESERVED_15_9 9 15 ixDPCSSYS_CR3_SUP_DIG_BANDGAP_ASIC_IN 2 0x38 2 0 4294967295 BG_EN 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR3_SUP_DIG_MPLLA_CP_ASIC_IN 2 0x39 3 0 4294967295 MPLLA_CP_PROP 0 6 MPLLA_CP_INT 7 13 RESERVED_15_14 14 15 ixDPCSSYS_CR3_SUP_DIG_MPLLA_CP_GS_ASIC_IN 2 0x3a 3 0 4294967295 MPLLA_CP_PROP_GS 0 6 MPLLA_CP_INT_GS 7 13 RESERVED_15_14 14 15 ixDPCSSYS_CR3_SUP_DIG_MPLLB_CP_ASIC_IN 2 0x3b 3 0 4294967295 MPLLB_CP_PROP 0 6 MPLLB_CP_INT 7 13 RESERVED_15_14 14 15 ixDPCSSYS_CR3_SUP_DIG_MPLLB_CP_GS_ASIC_IN 2 0x3c 3 0 4294967295 MPLLB_CP_PROP_GS 0 6 MPLLB_CP_INT_GS 7 13 RESERVED_15_14 14 15 ixDPCSSYS_CR3_SUP_ANA_PRESCALER_CTRL 2 0x40 7 0 4294967295 PSCALER_ATB_SELECT 0 0 PSCALER_MEAS_VREG 0 0 PSCALER_OVRD_FAST_START 0 0 PSCALER_FAST_START_REG 0 0 PSCALER_VREG_BOOST 0 0 PSCALER_HYST_REF 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR3_SUP_ANA_RTUNE_CTRL 2 0x41 9 0 4294967295 RT_ATB 0 0 RT_SEL_ATBF 0 0 RT_SEL_ATBP 0 0 RT_VP4O8_EN 0 0 RT_DAC_CHOP 0 0 RT_DAC_MODE 0 0 RT_EN_FRCON 0 0 PSCALER_VREG_FB_DIV_CTRL 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR3_SUP_ANA_BG1 2 0x42 6 0 4294967295 SUP_SEL_VBG_VREF 0 0 SUP_SEL_VPHUD_VREF 0 0 NC4 4 4 SUP_SEL_VPLL_REF 0 0 RT_VREF_SEL 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR3_SUP_ANA_BG2 2 0x43 9 0 4294967295 SUP_BYPASS_BG 0 0 SUP_CHOP_EN 0 0 SUP_TEMP_MEAS 0 0 VPHUD_SELREF 0 0 ATB_EXT_MEAS_EN 0 0 RT_TX_OFFSET_EN 0 0 SUP_SEL_TX_SWING_VREF 0 0 PSCALER_VREG_OVERRIDE_RING_CTRL 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR3_SUP_ANA_SWITCH_PWR_MEAS 2 0x44 3 0 4294967295 SUP_ATB_SW 0 0 SUP_TIE 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR3_SUP_ANA_BG3 2 0x45 4 0 4294967295 SUP_SEL_RX_VCO_TC_VREF 0 0 SUP_SEL_RX_CAL_VREF 0 0 NC7_4 4 7 RESERVED_15_8 8 15 ixDPCSSYS_CR3_SUP_ANA_MPLLA_MISC1 2 0x46 7 0 4294967295 OVRD_GEAR_RC_FILT 0 0 OVRD_TEST_RC_FILT 0 0 TEST_VREG_DIV 0 0 VBG_EN 0 0 COUNT_SEL_LOCK 0 0 PHASE_SEL_LOCK 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR3_SUP_ANA_MPLLA_MISC2 2 0x47 8 0 4294967295 OVRD_PR_BYPASS 0 0 PR_BYPASS 0 0 OVRD_GEARSHIFT 0 0 GEARSHIFT_REG 0 0 TEST_LOCK_GEAR 0 0 EN_CAL_SPO 0 0 TEST_BOOST 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR3_SUP_ANA_MPLLA_OVRD 2 0x48 9 0 4294967295 OVRD_ENABLE 0 0 ENABLE_REG 0 0 OVRD_CAL 0 0 CAL_REG 0 0 OVRD_FB_CLK_EN 0 0 FB_CLK_EN_REG 0 0 OVRD_RESET 0 0 RESET_REG 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR3_SUP_ANA_MPLLA_ATB1 2 0x49 3 0 4294967295 MEAS_IV_WRAP 0 0 ATB_SELECT 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR3_SUP_ANA_MPLLA_ATB2 2 0x4a 2 0 4294967295 MEAS_IV_PLL 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR3_SUP_ANA_MPLLA_ATB3 2 0x4b 3 0 4294967295 MEAS_IV_BIAS 0 0 CTR_UPLL_TUNNING 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR3_SUP_ANA_MPLLA_CTR1 2 0x4c 5 0 4294967295 CTR_ICP_INT 0 0 CTR_VREF_EN 0 0 CTR_VREF_VMARG 0 0 CTR_CP_PLL 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR3_SUP_ANA_MPLLA_CTR2 2 0x4d 2 0 4294967295 CTR_REGS_PLL 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR3_SUP_ANA_MPLLA_CTR3 2 0x4e 4 0 4294967295 CTR_REGS_CP_PLL 0 0 CTR_SPO_PLL 0 0 CTR_VINT_CAP 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR3_SUP_ANA_MPLLA_CTR4 2 0x4f 7 0 4294967295 CTR_CP_8X 0 0 CTR_FIL_REG 0 0 CTR_CP_PROP_REF 0 0 CTR_DOUBLER_GAIN 0 0 CTR_TEST_CASC 0 0 CTR_RC_FITER 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR3_SUP_ANA_MPLLA_CTR5 2 0x50 8 0 4294967295 CTR_STANDBY_MODE 0 0 CTR_LEG_SR_CON 0 0 CTR_VREG_RING_OVERRIDE 0 0 CTR_SPO_SPEED_OVERRIDE 0 0 CTR_BYPASS_LOCK_SPO_CAL 0 0 CTR_LOCK_SPO_CAL 0 0 CTR_UPLL_RESERVED 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR3_SUP_ANA_MPLLA_RESERVED1 2 0x51 8 0 4294967295 CTR_REF_FBK_BYPASS 0 0 CTR_BYPASS_TX 0 0 CTR_VREG_CLK_BYPASS 0 0 CTR_VREG_CLK_PMIX_BYPASS 0 0 CTR_VREG_RIGHT_BYPASS 0 0 CTR_VREG_LEFT_BYPASS 0 0 CTR_LEFT_RIGHT_GAIN 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR3_SUP_ANA_MPLLA_RESERVED2 2 0x52 5 0 4294967295 CTR_DLL_MODE_90 0 0 CTR_DLL_RESERVED 0 0 CTR_DIV24_DSQ_ENZ 0 0 CTR_DIV4 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR3_SUP_ANA_MPLLB_MISC1 2 0x53 7 0 4294967295 OVRD_GEAR_RC_FILT 0 0 OVRD_TEST_RC_FILT 0 0 TEST_VREG_DIV 0 0 VBG_EN 0 0 COUNT_SEL_LOCK 0 0 PHASE_SEL_LOCK 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR3_SUP_ANA_MPLLB_MISC2 2 0x54 8 0 4294967295 OVRD_PR_BYPASS 0 0 PR_BYPASS 0 0 OVRD_GEARSHIFT 0 0 GEARSHIFT_REG 0 0 TEST_LOCK_GEAR 0 0 EN_CAL_SPO 0 0 TEST_BOOST 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR3_SUP_ANA_MPLLB_OVRD 2 0x55 9 0 4294967295 OVRD_ENABLE 0 0 ENABLE_REG 0 0 OVRD_CAL 0 0 CAL_REG 0 0 OVRD_FB_CLK_EN 0 0 FB_CLK_EN_REG 0 0 OVRD_RESET 0 0 RESET_REG 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR3_SUP_ANA_MPLLB_ATB1 2 0x56 3 0 4294967295 MEAS_IV_WRAP 0 0 ATB_SELECT 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR3_SUP_ANA_MPLLB_ATB2 2 0x57 2 0 4294967295 MEAS_IV_PLL 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR3_SUP_ANA_MPLLB_ATB3 2 0x58 3 0 4294967295 MEAS_IV_BIAS 0 0 CTR_UPLL_TUNNING 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR3_SUP_ANA_MPLLB_CTR1 2 0x59 5 0 4294967295 CTR_ICP_INT 0 0 CTR_VREF_EN 0 0 CTR_VREF_VMARG 0 0 CTR_CP_PLL 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR3_SUP_ANA_MPLLB_CTR2 2 0x5a 2 0 4294967295 CTR_REGS_PLL 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR3_SUP_ANA_MPLLB_CTR3 2 0x5b 4 0 4294967295 CTR_REGS_CP_PLL 0 0 CTR_SPO_PLL 0 0 CTR_VINT_CAP 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR3_SUP_ANA_MPLLB_CTR4 2 0x5c 7 0 4294967295 CTR_CP_8X 0 0 CTR_FIL_REG 0 0 CTR_CP_PROP_REF 0 0 CTR_DOUBLER_GAIN 0 0 CTR_TEST_CASC 0 0 CTR_RC_FITER 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR3_SUP_ANA_MPLLB_CTR5 2 0x5d 8 0 4294967295 CTR_STANDBY_MODE 0 0 CTR_LEG_SR_CON 0 0 CTR_VREG_RING_OVERRIDE 0 0 CTR_SPO_SPEED_OVERRIDE 0 0 CTR_BYPASS_LOCK_SPO_CAL 0 0 CTR_LOCK_SPO_CAL 0 0 CTR_UPLL_RESERVED 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR3_SUP_ANA_MPLLB_RESERVED1 2 0x5e 8 0 4294967295 CTR_REF_FBK_BYPASS 0 0 CTR_BYPASS_TX 0 0 CTR_VREG_CLK_BYPASS 0 0 CTR_VREG_CLK_PMIX_BYPASS 0 0 CTR_VREG_RIGHT_BYPASS 0 0 CTR_VREG_LEFT_BYPASS 0 0 CTR_LEFT_RIGHT_GAIN 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR3_SUP_ANA_MPLLB_RESERVED2 2 0x5f 5 0 4294967295 CTR_DLL_MODE_90 0 0 CTR_DLL_RESERVED 0 0 CTR_DIV24_DSQ_ENZ 0 0 CTR_DIV4 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD 2 0x61 8 0 4294967295 OVRD_SEL 0 0 MPLL_FBDIGCLK_EN 1 1 MPLL_PCLK_EN 2 2 FAST_MPLL_PWRUP 3 3 FAST_MPLL_LOCK 4 4 DTB_SEL 5 9 DIV10_EN 10 10 RESERVED 11 15 ixDPCSSYS_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT 2 0x62 11 0 4294967295 FSM_STATE 0 3 MPLL_R_LANES 4 4 MPLL_L_LANES 5 5 MPLL_PCLK_EN 6 6 MPLL_OUTPUT_EN 7 7 MPLL_FBCLK_EN 8 8 MPLL_CAL 9 9 MPLL_RST 10 10 MPLL_ANA_EN 11 11 MPLL_LOCK 12 12 RESERVED_15_13 13 15 ixDPCSSYS_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE 2 0x63 3 0 4294967295 MAX_RANGE 0 4 DAC_IN 5 9 RESERVED_15_10 10 15 ixDPCSSYS_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_LOCK 2 0x64 3 0 4294967295 LOCK_TIME 0 7 STABLE_TIME 8 13 RESERVED_15_14 14 15 ixDPCSSYS_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS 2 0x65 2 0 4294967295 GEARSHIFT_TIME 0 7 PRESET_TIME 8 15 ixDPCSSYS_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE 2 0x66 3 0 4294967295 PWRDN_WAIT_TIME 0 5 PCLK_EN_TIME 6 11 RESERVED_15_12 12 15 ixDPCSSYS_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2 2 0x67 3 0 4294967295 PCLK_DIS_TIME 0 5 PWRDN_TIME 6 11 RESERVED_15_12 12 15 ixDPCSSYS_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_CAL 2 0x68 3 0 4294967295 MPLL_CAL 0 0 MPLL_CAL_OVRD_EN 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT 2 0x69 2 0 4294967295 MPLL_ANA_DAC_OUT 0 4 RESERVED_15_5 5 15 ixDPCSSYS_CR3_SUP_DIG_MPLLA_SSC_GEN_SPREAD_TYPE 2 0x6b 3 0 4294967295 SPREAD_TYPE 0 1 OVR_EN 2 2 RESERVED_15_3 3 15 ixDPCSSYS_CR3_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD 2 0x6d 8 0 4294967295 OVRD_SEL 0 0 MPLL_FBDIGCLK_EN 1 1 MPLL_PCLK_EN 2 2 FAST_MPLL_PWRUP 3 3 FAST_MPLL_LOCK 4 4 DTB_SEL 5 9 DIV10_EN 10 10 RESERVED 11 15 ixDPCSSYS_CR3_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT 2 0x6e 11 0 4294967295 FSM_STATE 0 3 MPLL_R_LANES 4 4 MPLL_L_LANES 5 5 MPLL_PCLK_EN 6 6 MPLL_OUTPUT_EN 7 7 MPLL_FBCLK_EN 8 8 MPLL_CAL 9 9 MPLL_RST 10 10 MPLL_ANA_EN 11 11 MPLL_LOCK 12 12 RESERVED_15_13 13 15 ixDPCSSYS_CR3_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE 2 0x6f 3 0 4294967295 MAX_RANGE 0 4 DAC_IN 5 9 RESERVED_15_10 10 15 ixDPCSSYS_CR3_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_LOCK 2 0x70 3 0 4294967295 LOCK_TIME 0 7 STABLE_TIME 8 13 RESERVED_15_14 14 15 ixDPCSSYS_CR3_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS 2 0x71 2 0 4294967295 GEARSHIFT_TIME 0 7 PRESET_TIME 8 15 ixDPCSSYS_CR3_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE 2 0x72 3 0 4294967295 PWRDN_WAIT_TIME 0 5 PCLK_EN_TIME 6 11 RESERVED_15_12 12 15 ixDPCSSYS_CR3_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2 2 0x73 3 0 4294967295 PCLK_DIS_TIME 0 5 PWRDN_TIME 6 11 RESERVED_15_12 12 15 ixDPCSSYS_CR3_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_CAL 2 0x74 3 0 4294967295 MPLL_CAL 0 0 MPLL_CAL_OVRD_EN 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR3_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT 2 0x75 2 0 4294967295 MPLL_ANA_DAC_OUT 0 4 RESERVED_15_5 5 15 ixDPCSSYS_CR3_SUP_DIG_MPLLB_SSC_GEN_SPREAD_TYPE 2 0x77 3 0 4294967295 SPREAD_TYPE 0 1 OVR_EN 2 2 RESERVED_15_3 3 15 ixDPCSSYS_CR3_SUP_DIG_CLK_RST_BG_PWRUP_TIME_0 2 0x78 3 0 4294967295 BG_SUP_EN_TIME 0 8 FAST_BG_WAIT 9 9 RESERVED_15_10 10 15 ixDPCSSYS_CR3_SUP_DIG_CLK_RST_BG_PWRUP_TIME_1 2 0x79 2 0 4294967295 BG_LANE_EN_TIME 0 8 RESERVED_15_9 9 15 ixDPCSSYS_CR3_SUP_DIG_CLK_RST_BG_PWRUP_TIME_2 2 0x7a 3 0 4294967295 BG_KICK_START_EN_TIME 0 7 BG_SUP_STATE_UPD_EN 8 8 RESERVED_15_9 9 15 ixDPCSSYS_CR3_SUP_DIG_CLK_RST_REF_PWRUP_TIME_0 2 0x7b 3 0 4294967295 REF_VREG_FAST_START_TIME 0 4 FAST_REF_WAIT 5 5 RESERVED_15_6 6 15 ixDPCSSYS_CR3_SUP_DIG_CLK_RST_REF_VPHUD 2 0x7c 3 0 4294967295 SUP_ANA_VPHUD_SELVPH_I 0 0 SUP_ANA_VPHUD_EN_I 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR3_SUP_DIG_RTUNE_CONFIG 2 0x81 5 0 4294967295 RX_CAL_EN 0 0 FAST_RTUNE 1 1 TX_CAL_EN 2 2 SUP_ANA_TERM_CTRL 3 5 RESERVED_15_6 6 15 ixDPCSSYS_CR3_SUP_DIG_RTUNE_STAT 2 0x82 3 0 4294967295 STAT 0 9 DTB_RTUNE 10 11 RESERVED_15_12 12 15 ixDPCSSYS_CR3_SUP_DIG_RTUNE_RX_SET_VAL 2 0x83 2 0 4294967295 RX_SET_VAL 0 5 RESERVED_15_6 6 15 ixDPCSSYS_CR3_SUP_DIG_RTUNE_TXDN_SET_VAL 2 0x84 2 0 4294967295 TXDN_SET_VAL 0 9 RESERVED_15_10 10 15 ixDPCSSYS_CR3_SUP_DIG_RTUNE_TXUP_SET_VAL 2 0x85 2 0 4294967295 TXUP_SET_VAL 0 9 RESERVED_15_10 10 15 ixDPCSSYS_CR3_SUP_DIG_RTUNE_RX_STAT 2 0x86 2 0 4294967295 RX_STAT 0 5 RESERVED_15_6 6 15 ixDPCSSYS_CR3_SUP_DIG_RTUNE_TXDN_STAT 2 0x87 2 0 4294967295 TXDN_STAT 0 9 RESERVED_15_10 10 15 ixDPCSSYS_CR3_SUP_DIG_RTUNE_TXUP_STAT 2 0x88 2 0 4294967295 TXUP_STAT 0 9 RESERVED_15_10 10 15 ixDPCSSYS_CR3_SUP_DIG_RTUNE_CONFIG_CNT0 2 0x89 4 0 4294967295 RT_RESULT_TIME 0 3 RT_EVAL_TIME 4 7 RT_RST_TIME 8 11 RT_ACK_TIME 12 15 ixDPCSSYS_CR3_SUP_DIG_RTUNE_CONFIG_CNT1 2 0x8a 3 0 4294967295 RT_TXDN_SETTLE_TIME 0 3 RT_PWRUP_TIME 4 8 RESERVED_15_9 9 15 ixDPCSSYS_CR3_SUP_DIG_RTUNE_TX_CAL_CODE 2 0x8b 2 0 4294967295 VALUE 0 3 RESERVED_15_4 4 15 ixDPCSSYS_CR3_SUP_DIG_ANA_MPLLA_OVRD_OUT_0 2 0x8c 16 0 4294967295 MPLLA_WORD_CLK_EN 0 0 MPLLA_HDMI_CLK_EN 1 1 MPLLA_DIV_CLK_EN 2 2 MPLLA_OUTPUT_EN 3 3 MPLLA_CLK_EN_OVRD_EN 4 4 MPLLA_OUTPUT_L_EN 5 5 MPLLA_OUTPUT_R_EN 6 6 MPLLA_ANA_EN 7 7 MPLLA_RST 8 8 MPLLA_CAL 9 9 MPLLA_DIV5_CLK_EN 10 10 MPLLA_DIV10_CLK_EN 11 11 MPLLA_FBCLK_EN 12 12 MPLLA_GEARSHIFT_EN 13 13 MPLLA_STANDBY 14 14 OVRD_SEL 15 15 ixDPCSSYS_CR3_SUP_DIG_ANA_MPLLA_OVRD_OUT_1 2 0x8d 2 0 4294967295 MPLLA_ANA_INT 0 9 RESERVED_15_10 10 15 ixDPCSSYS_CR3_SUP_DIG_ANA_MPLLA_OVRD_OUT_2 2 0x8e 3 0 4294967295 MPLLA_CP_PROP 0 6 MPLLA_CP_INT 7 13 RESERVED_15_14 14 15 ixDPCSSYS_CR3_SUP_DIG_ANA_MPLLB_OVRD_OUT_0 2 0x8f 16 0 4294967295 MPLLB_WORD_CLK_EN 0 0 MPLLB_HDMI_CLK_EN 1 1 MPLLB_DIV_CLK_EN 2 2 MPLLB_OUTPUT_EN 3 3 MPLLB_CLK_EN_OVRD_EN 4 4 MPLLB_OUTPUT_L_EN 5 5 MPLLB_OUTPUT_R_EN 6 6 MPLLB_ANA_EN 7 7 MPLLB_RST 8 8 MPLLB_CAL 9 9 MPLLB_DIV5_CLK_EN 10 10 MPLLB_DIV10_CLK_EN 11 11 MPLLB_FBCLK_EN 12 12 MPLLB_GEARSHIFT_EN 13 13 MPLLB_STANDBY 14 14 OVRD_SEL 15 15 ixDPCSSYS_CR3_SUP_DIG_ANA_MPLLB_OVRD_OUT_1 2 0x90 2 0 4294967295 MPLLB_ANA_INT 0 9 RESERVED_15_10 10 15 ixDPCSSYS_CR3_SUP_DIG_ANA_MPLLB_OVRD_OUT_2 2 0x91 3 0 4294967295 MPLLB_CP_PROP 0 6 MPLLB_CP_INT 7 13 RESERVED_15_14 14 15 ixDPCSSYS_CR3_SUP_DIG_ANA_RTUNE_OVRD_OUT 2 0x92 6 0 4294967295 RTUNE_COMP_RST 0 0 RTUNE_MODE 1 2 RTUNE_EN 3 3 RTUNE_VALUE 4 13 RTUNE_OVRD_EN 14 14 RESERVED_15_15 15 15 ixDPCSSYS_CR3_SUP_DIG_ANA_STAT 2 0x93 3 0 4294967295 RT_ANA_COMP_RESULT 0 0 REF_ANA_CLKDET_RESULT 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR3_SUP_DIG_ANA_BG_OVRD_OUT 2 0x94 11 0 4294967295 BG_EN 0 0 BG_FAST_START 1 1 BG_KICK_START 2 2 BG_OVRD_EN 3 3 ANA_ASYNC_RST 4 4 ANA_ASYNC_RST_OVRD_EN 5 5 REF_VREG_FAST_START 6 6 REF_VREG_FAST_START_OVRD_EN 7 7 REF_VREG_REF_SEL 8 9 REF_VREG_REF_SEL_OVRD_EN 10 10 RESERVED_15_11 11 15 ixDPCSSYS_CR3_SUP_DIG_ANA_MPLLA_PMIX_OVRD_OUT 2 0x95 5 0 4294967295 MPLLA_PMIX_SEL 0 5 MPLLA_PMIX_EN 6 6 MPLLA_PMIX_SEL_OVRD_EN 7 7 MPLLA_PMIX_EN_OVRD_EN 8 8 RESERVED_15_9 9 15 ixDPCSSYS_CR3_SUP_DIG_ANA_MPLLB_PMIX_OVRD_OUT 2 0x96 5 0 4294967295 MPLLB_PMIX_SEL 0 5 MPLLB_PMIX_EN 6 6 MPLLB_PMIX_SEL_OVRD_EN 7 7 MPLLB_PMIX_EN_OVRD_EN 8 8 RESERVED_15_9 9 15 ixDPCSSYS_CR3_LANE0_DIG_ASIC_LANE_OVRD_IN 2 0x1000 5 0 4294967295 LANE_TX2RX_SER_LB 0 0 LANE_RX2TX_PAR_LB 1 1 EN 2 2 RX_ACJTAG_EN 3 3 RESERVED_15_4 4 15 ixDPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_0 2 0x1001 12 0 4294967295 REQ 0 0 REQ_OVRD_EN 1 1 PSTATE 2 3 PSTATE_OVRD_EN 4 4 RATE 5 7 RATE_OVRD_EN 8 8 WIDTH 9 10 WIDTH_OVRD_EN 11 11 MPLLB_SEL 12 12 MPLLB_SEL_OVRD_EN 13 13 DATA_EN 14 14 DATA_EN_OVRD_EN 15 15 ixDPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_1 2 0x1002 11 0 4294967295 NYQUIST_DATA 0 0 DISABLE 1 1 BEACON_EN 2 2 EN 3 3 TX_MAIN_CURSOR 4 9 MAIN_OVRD_EN 10 10 ASYNC_DRV_EN 11 11 ASYNC_DRV_OVRD_EN 12 12 TX_VREGDRV_BYP_OVRD 13 13 TX_VREGDRV_BYP_OVRD_EN 14 14 RESERVED_15_15 15 15 ixDPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_2 2 0x1003 6 0 4294967295 TX_PRE_CURSOR 0 5 PRE_OVRD_EN 6 6 TX_POST_CURSOR 7 12 POST_OVRD_EN 13 13 HDMIMODE_EN 14 14 HDMIMODE_ENABLE_OVRD_EN 15 15 ixDPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_3 2 0x1004 15 0 4294967295 CLK_RDY 0 0 CLK_RDY_OVRD_EN 1 1 DETECT_RX_REQ 2 2 DETECT_RX_REQ_OVRD_EN 3 3 INVERT 4 4 INVERT_OVRD_EN 5 5 LPD 6 6 LPD_OVRD_EN 7 7 TX_DC_COUP_EN 8 8 TX_DC_COUP_EN_OVRD_EN 9 9 PMA_EXTENDED_FIFO_EN 10 10 PMA_EXTENDED_FIFO_EN_OVRD_EN 11 11 TX_MPHY_MODE_EN 12 12 TX_MPHY_MODE_EN_OVRD_EN 13 13 RESERVED_15_14 14 15 ixDPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_4 2 0x1005 3 0 4294967295 RESET 0 0 RESET_OVRD_EN 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_OUT 2 0x1006 5 0 4294967295 TX_ACK 0 0 EN_TX_ACK 1 1 DETRX_RESULT 2 2 EN_DETRX_RESULT 3 3 RESERVED_15_4 4 15 ixDPCSSYS_CR3_LANE0_DIG_ASIC_RX_OVRD_OUT_0 2 0x100f 9 0 4294967295 ACK 0 0 ACK_OVRD_EN 1 1 ADAPT_STS 2 3 ADAPT_STS_OVRD_EN 4 4 RX_ASYNC_DATA 5 5 RX_ASYNC_DATA_OVRD_EN 6 6 RX_SQ_WEAKKEEP_OUT 7 7 RX_SQ_WEAKKEEP_OUT_OVRD_EN 8 8 RESERVED_15_9 9 15 ixDPCSSYS_CR3_LANE0_DIG_ASIC_LANE_ASIC_IN 2 0x1010 3 0 4294967295 LANE_TX2RX_SER_LB 0 0 LANE_RX2TX_PAR_LB 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR3_LANE0_DIG_ASIC_TX_ASIC_IN_0 2 0x1011 12 0 4294967295 CLK_RDY 0 0 RESET 1 1 INVERT 2 2 DATA_EN 3 3 REQ 4 4 LPD 5 5 PSTATE 6 7 RATE 8 10 WIDTH 11 12 MPLLB_SEL 13 13 DETECT_RX_REQ 14 14 DISABLE 15 15 ixDPCSSYS_CR3_LANE0_DIG_ASIC_TX_ASIC_IN_1 2 0x1012 7 0 4294967295 BEACON_EN 0 0 TX_MAIN_CURSOR 1 6 TX_ASYNC_EN 7 7 TX_ASYNC_DATA 8 8 TX_ASYNC_DRV_EN 9 9 TX_VREGDRV_BYP 10 10 RESERVED_15_11 11 15 ixDPCSSYS_CR3_LANE0_DIG_ASIC_TX_ASIC_IN_2 2 0x1013 3 0 4294967295 TX_PRE_CURSOR 0 5 TX_POST_CURSOR 6 11 RESERVED_15_12 12 15 ixDPCSSYS_CR3_LANE0_DIG_ASIC_TX_ASIC_OUT 2 0x1014 3 0 4294967295 TX_ACK 0 0 DETRX_RESULT 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR3_LANE0_DIG_ASIC_RX_ASIC_OUT_0 2 0x101b 4 0 4294967295 ACK 0 0 VALID 1 1 ADAPT_STS 2 3 RESERVED_15_4 4 15 ixDPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_5 2 0x101d 15 0 4294967295 RPTR_EN_MASTER_LANE 0 0 RPTR_EN_MASTER_LANE_OVRD_EN 1 1 DIG_CLK_EN_OTHER_LANE 2 2 DIG_CLK_EN_OTHER_LANE_OVRD_EN 3 3 DIG_CLK_STATE_MASTER_LANE 4 4 DIG_CLK_STATE_MASTER_LANE_OVRD_EN 5 5 SHIFT_MASTER_LANE 6 6 SHIFT_MASTER_LANE_ORVD_EN 7 7 SHIFT_ACK_OTHER_LANE 8 8 SHIFT_ACK_OTHER_LANE_OVRD_EN 9 9 LANE_MASTER 10 10 LANE_MASTER_OVRD_IN_EN 11 11 TX_DWORD_CLK_SYNC_OVRD 12 12 TX_DWORD_CLK_SYNC_OVRD_EN 13 13 RESERVED_15_14 14 15 ixDPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_OUT_1 2 0x101e 11 0 4294967295 RPTR_EN_OUT 0 0 RPTR_EN_OUT_OVRD_EN 1 1 DIG_CLK_EN_OUT 2 2 DIG_CLK_EN_OUT_OVRD_EN 3 3 DIG_CLK_STATE_OUT 4 4 DIG_CLK_STATE_OUT_OVRD_EN 5 5 SHIFT_OUT 6 6 SHIFT_OUT_OVRD_EN 7 7 SHIFT_ACK_OUT 8 8 SHIFT_ACK_OUT_OVRD_EN 9 9 RESERVED_15_10 10 15 ixDPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0 2 0x1020 11 0 4294967295 TX_P0_ANA_REFGEN_EN 0 0 TX_P0_ANA_VCM_HOLD 1 1 TX_P0_ANA_CLK_EN 2 2 TX_P0_ANA_WORD_CLK_EN 3 3 TX_P0_ANA_RESET 4 4 TX_P0_ANA_SERIAL_EN 5 5 TX_P0_DIG_CLK_EN 6 6 TX_P0_DATA_EN 7 7 TX_P0_ALLOW_RXDET 8 8 TX_P0_ANA_DCC_COMP_CAL_EN 9 9 RESERVED_15_10 10 15 ixDPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S 2 0x1021 11 0 4294967295 TX_P0S_ANA_REFGEN_EN 0 0 TX_P0S_ANA_VCM_HOLD 1 1 TX_P0S_ANA_CLK_EN 2 2 TX_P0S_ANA_WORD_CLK_EN 3 3 TX_P0S_ANA_RESET 4 4 TX_P0S_ANA_SERIAL_EN 5 5 TX_P0S_DIG_CLK_EN 6 6 TX_P0S_DATA_EN 7 7 TX_P0S_ALLOW_RXDET 8 8 TX_P0S_ANA_DCC_COMP_CAL_EN 9 9 RESERVED_15_10 10 15 ixDPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1 2 0x1022 11 0 4294967295 TX_P1_ANA_REFGEN_EN 0 0 TX_P1_ANA_VCM_HOLD 1 1 TX_P1_ANA_CLK_EN 2 2 TX_P1_ANA_WORD_CLK_EN 3 3 TX_P1_ANA_RESET 4 4 TX_P1_ANA_SERIAL_EN 5 5 TX_P1_DIG_CLK_EN 6 6 TX_P1_DATA_EN 7 7 TX_P1_ALLOW_RXDET 8 8 TX_P1_ANA_DCC_COMP_CAL_EN 9 9 RESERVED_15_10 10 15 ixDPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2 2 0x1023 12 0 4294967295 TX_P2_ANA_REFGEN_EN 0 0 TX_P2_ANA_VCM_HOLD 1 1 TX_P2_ANA_CLK_EN 2 2 TX_P2_ANA_WORD_CLK_EN 3 3 TX_P2_ANA_RESET 4 4 TX_P2_ANA_SERIAL_EN 5 5 TX_P2_DIG_CLK_EN 6 6 TX_P2_DATA_EN 7 7 TX_P2_ALLOW_RXDET 8 8 TX_P2_ALLOW_VBOOST 9 9 TX_P2_ANA_DCC_COMP_CAL_EN 10 10 RESERVED_15_11 11 15 ixDPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_0 2 0x1024 2 0 4294967295 TX_REFGEN_EN_TIME 0 7 TX_CLK_EN 8 15 ixDPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_1 2 0x1025 2 0 4294967295 TX_VCM_HOLD_TIME_14_0 0 14 SKIP_TX_VCM_HOLD_WAIT 15 15 ixDPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_2 2 0x1026 2 0 4294967295 TX_VBOOST_DIS_TIME_12_0 0 12 DTB_SEL 13 15 ixDPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_3 2 0x1027 3 0 4294967295 TX_VCM_HOLD_TIME_17_15 0 2 TX_VBOOST_DIS_TIME_13 3 3 RESERVED_15_4 4 15 ixDPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_4 2 0x1028 2 0 4294967295 TX_VCM_HOLD_GS_TIME 0 14 SKIP_TX_VCM_HOLD_GS_PULSE 15 15 ixDPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_5 2 0x1029 5 0 4294967295 TX_RXDET_TIME 0 9 FAST_TX_RXDET 10 10 TX_RESET_TIME 11 12 TX_SERIAL_EN_TIME 13 14 RESERVED_15_15 15 15 ixDPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_DCC_CR_BANK_ADDR 2 0x102a 1 0 4294967295 ADDR 0 15 ixDPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_DCC_CR_BANK_DATA 2 0x102b 1 0 4294967295 DATA 0 15 ixDPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_DCC_DAC_CTRL 2 0x102c 2 0 4294967295 CTRL 0 7 RESERVED_15_8 8 15 ixDPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_DCC_DAC_RANGE 2 0x102d 2 0 4294967295 CTRL 0 1 RESERVED_15_2 2 15 ixDPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_DCC_DAC_SEL 2 0x102e 6 0 4294967295 SEL 0 2 REQ 3 3 CTRL_UPD 4 4 RANGE_UPD 5 5 BIN_HOT 6 6 RESERVED_15_7 7 15 ixDPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_DCC_DAC_ACK 2 0x102f 2 0 4294967295 ACK 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_DCC_DAC_ADDR 2 0x1030 1 0 4294967295 ADDR 0 15 ixDPCSSYS_CR3_LANE0_DIG_TX_CLK_ALIGN_TX_CTL_0 2 0x1031 4 0 4294967295 TX_NUM_2UI_SHIFTS_16B_MODE 0 3 TX_NUM_2UI_SHIFTS_20B_MODE 4 7 TX_FIFO_BYPASS 8 8 RESERVED_15_9 9 15 ixDPCSSYS_CR3_LANE0_DIG_TX_LBERT_CTL 2 0x1032 4 0 4294967295 MODE 0 3 TRIGGER_ERR 4 4 PAT0 5 14 RESERVED_15_15 15 15 ixDPCSSYS_CR3_LANE0_DIG_RX_STAT_LD_VAL_1 2 0x1080 2 0 4294967295 SC1_LD_VAL 0 14 SC1_START 15 15 ixDPCSSYS_CR3_LANE0_DIG_RX_STAT_DATA_MSK 2 0x1081 1 0 4294967295 DATA_MSK_15_0 0 15 ixDPCSSYS_CR3_LANE0_DIG_RX_STAT_MATCH_CTL0 2 0x1082 4 0 4294967295 PTTRN_MSK_CR1A_4_0 0 4 PTTRN_CR1A_4_0 5 9 DATA_MSK_19_16 10 13 SCOPE_DLY 14 15 ixDPCSSYS_CR3_LANE0_DIG_RX_STAT_MATCH_CTL1 2 0x1083 5 0 4294967295 PTTRN_CR1B_EN 0 0 PTTRN_MSK_CR1B_4_0 1 5 PTTRN_CR1B_4_0 6 10 PTTRN_CR1A_ADPT_EN 11 11 RESERVED_15_12 12 15 ixDPCSSYS_CR3_LANE0_DIG_RX_STAT_STAT_CTL0 2 0x1084 10 0 4294967295 RESERVED_0 0 0 CORR_SHFT_SEL_VGA 1 1 CORR_SHFT_SEL 2 2 CORR_SRC_SEL 3 4 CORR_MODE_EN 5 5 STAT_SHFT_SEL 6 9 STAT_SRC_SEL 10 12 STAT_RXCLK_SEL 13 13 SC_TIMER_MODE 14 14 SKIP_EN 15 15 ixDPCSSYS_CR3_LANE0_DIG_RX_STAT_STAT_CTL1 2 0x1085 13 0 4294967295 STAT_CNT_0_EN 0 0 STAT_CNT_1_EN 1 1 STAT_CNT_2_EN 2 2 STAT_CNT_3_EN 3 3 STAT_CNT_4_EN 4 4 STAT_CNT_5_EN 5 5 STAT_CNT_6_EN 6 6 RESERVED_8_7 7 8 SC_PAUSE 9 9 STAT_CLK_EN 10 10 DATA_DLY_SEL 11 12 VLD_LOSS_CLR 13 13 VLD_CTL 14 15 ixDPCSSYS_CR3_LANE0_DIG_RX_STAT_SMPL_CNT1 2 0x1086 2 0 4294967295 SMPL_CNT1 0 14 SMPL_CNT1_DONE 15 15 ixDPCSSYS_CR3_LANE0_DIG_RX_STAT_STAT_CNT_0 2 0x1087 2 0 4294967295 STAT_CNT_0 0 14 SMPL_CNT1_DONE 15 15 ixDPCSSYS_CR3_LANE0_DIG_RX_STAT_STAT_CNT_1 2 0x1088 2 0 4294967295 STAT_CNT_1 0 14 SMPL_CNT1_DONE 15 15 ixDPCSSYS_CR3_LANE0_DIG_RX_STAT_STAT_CNT_2 2 0x1089 2 0 4294967295 STAT_CNT_2 0 14 SMPL_CNT1_DONE 15 15 ixDPCSSYS_CR3_LANE0_DIG_RX_STAT_STAT_CNT_3 2 0x108a 2 0 4294967295 STAT_CNT_3 0 14 SMPL_CNT1_DONE 15 15 ixDPCSSYS_CR3_LANE0_DIG_RX_STAT_STAT_CNT_4 2 0x108b 2 0 4294967295 STAT_CNT_4 0 14 SMPL_CNT1_DONE 15 15 ixDPCSSYS_CR3_LANE0_DIG_RX_STAT_STAT_CNT_5 2 0x108c 2 0 4294967295 STAT_CNT_5 0 14 SMPL_CNT1_DONE 15 15 ixDPCSSYS_CR3_LANE0_DIG_RX_STAT_STAT_CNT_6 2 0x108d 2 0 4294967295 STAT_CNT_6 0 14 SMPL_CNT1_DONE 15 15 ixDPCSSYS_CR3_LANE0_DIG_RX_STAT_CAL_COMP_CLK_CTL 2 0x108e 3 0 4294967295 PRECHRGE_CNT 0 2 REF_DIV_CNT 3 5 RESERVED_15_6 6 15 ixDPCSSYS_CR3_LANE0_DIG_RX_STAT_MATCH_CTL2 2 0x108f 2 0 4294967295 PTTRN_CR1A_19_5 0 14 RESERVED_15_15 15 15 ixDPCSSYS_CR3_LANE0_DIG_RX_STAT_MATCH_CTL3 2 0x1090 2 0 4294967295 PTTRN_MSK_CR1A_19_5 0 14 RESERVED_15_15 15 15 ixDPCSSYS_CR3_LANE0_DIG_RX_STAT_MATCH_CTL4 2 0x1091 2 0 4294967295 PTTRN_CR1B_19_5 0 14 RESERVED_15_15 15 15 ixDPCSSYS_CR3_LANE0_DIG_RX_STAT_MATCH_CTL5 2 0x1092 2 0 4294967295 PTTRN_MSK_CR1B_19_5 0 14 RESERVED_15_15 15 15 ixDPCSSYS_CR3_LANE0_DIG_RX_STAT_STAT_CTL2 2 0x1093 4 0 4294967295 DATA_DLY_SEL_2 0 0 SCOPE_DLY_2 1 1 DISABLE_SAMPLE_COUNT 2 2 RESERVED_15_3 3 15 ixDPCSSYS_CR3_LANE0_DIG_RX_STAT_STAT_STOP 2 0x1094 2 0 4294967295 SC1_STOP 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR3_LANE0_DIG_ANA_TX_OVRD_OUT 2 0x10a0 15 0 4294967295 TX_ANA_CLK_SHIFT 0 0 TX_ANA_DATA_EN 1 1 TX_ANA_REFGEN_EN 2 2 TX_ANA_VCM_HOLD 3 3 TX_ANA_CLK_EN 4 4 TX_ANA_WORD_CLK_EN 5 5 TX_ANA_MPLLA_CLK_EN 6 6 TX_ANA_MPLLB_CLK_EN 7 7 TX_ANA_RESET 8 8 TX_ANA_SERIAL_EN 9 9 TX_ANA_DATA_RATE 10 11 RESERVED 12 12 TX_DIV4_EN 13 13 TX_RXDET_EN 14 14 TX_OVRD_EN 15 15 ixDPCSSYS_CR3_LANE0_DIG_ANA_TX_TERM_CODE_OVRD_OUT 2 0x10a1 5 0 4294967295 TX_TERM_CODE 0 9 TX_TERM_OVRD_EN 10 10 TX_DRV_SRC 11 12 TX_DRV_SRC_OVRD_EN 13 13 RESERVED_15_14 14 15 ixDPCSSYS_CR3_LANE0_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT 2 0x10a2 3 0 4294967295 TX_TERM_DN_CLK 0 0 TX_TERM_CLK_SELF_CLEAR_DISABLE 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR3_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_0 2 0x10a3 3 0 4294967295 TX_ANA_LOAD_CLK 0 0 TX_ANA_CTRL_LEG_PULL_EN_13_0 1 14 TX_EQ_OVRD_EN 15 15 ixDPCSSYS_CR3_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_1 2 0x10a4 2 0 4294967295 TX_ANA_CTRL_LEG_PULL_EN_19_14 0 5 RESERVED_15_6 6 15 ixDPCSSYS_CR3_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_2 2 0x10a5 4 0 4294967295 RESERVED 0 2 TX_ANA_CTRL_EQ_MUX_SEL 3 6 TX_ANA_CTRL_PRE 7 12 RESERVED_15_13 13 15 ixDPCSSYS_CR3_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_3 2 0x10a6 2 0 4294967295 TX_ANA_CTRL_POST 0 8 RESERVED_15_9 9 15 ixDPCSSYS_CR3_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_4 2 0x10a7 1 0 4294967295 TX_ANA_CTRL_LEG_PULL_DIR_19_4 0 15 ixDPCSSYS_CR3_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_5 2 0x10a8 2 0 4294967295 TX_ANA_CTRL_LEG_PULL_DIR_3_0 0 3 RESERVED_15_4 4 15 ixDPCSSYS_CR3_LANE0_DIG_ANA_STATUS_0 2 0x10bb 9 0 4294967295 TX_ANA_CLK_SHIFT_ACK 0 0 TX_ANA_RXDETP_RESULT 1 1 TX_ANA_RXDETM_RESULT 2 2 TX_ANA_LOOPBACK_EN 3 3 TX_ANA_CLK_LB_EN 4 4 RX_ANA_CAL_RESULT 5 5 RX_ANA_SCOPE_DATA 6 6 TX_ANA_DCC_CAL_RESULT 7 7 TX_ANA_CTRL_EQ_MUX 8 15 ixDPCSSYS_CR3_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT 2 0x10c2 8 0 4294967295 TX_ANA_DCC_CAL_RANGE 0 1 TX_ANA_DCC_CAL_RANGE_OVRD_EN 2 2 TX_ANA_DCC_CAL_COMP_EN 3 3 TX_ANA_DCC_CAL_COMP_EN_OVRD_EN 4 4 TX_ANA_DCC_CAL_CTRL 5 12 TX_ANA_DCC_CAL_CTRL_OVRD_EN 13 13 TX_ANA_DCC_CAL_CTRL_EN 14 14 TX_ANA_DCC_CAL_CTRL_EN_OVRD_EN 15 15 ixDPCSSYS_CR3_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2 2 0x10c3 5 0 4294967295 TX_ANA_DCC_CAL_CTRL_SEL 0 2 TX_ANA_DCC_CAL_CTRL_SEL_OVRD_EN 3 3 TX_ANA_DCC_CLK_COMP 4 4 TX_ANA_DCC_CLK_COMP_OVRD_EN 5 5 RESERVED_15_6 6 15 ixDPCSSYS_CR3_LANE0_DIG_ANA_TX_OVRD_OUT_2 2 0x10c4 6 0 4294967295 TX_ANA_FAST_START 0 0 TX_ANA_FAST_START_OVRD_EN 1 1 TX_CLK_LB_EN 2 2 TX_CLK_LB_EN_OVRD_EN 3 3 TX_ACJTAG_EN 4 4 RESERVED_15_5 5 15 ixDPCSSYS_CR3_LANE0_ANA_TX_OVRD_MEAS 2 0x10e0 9 0 4294967295 OVRD_CLK_SHIFT 0 0 CLK_SHIFT_REG 0 0 MEAS_ATB_CAL_MUX 0 0 MEAS_ATB_CAL_COMP 0 0 OVRD_VCM_HOLD 0 0 VCM_HOLD_REG 0 0 PULL_UP_REG 0 0 PULL_DN_REG 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR3_LANE0_ANA_TX_PWR_OVRD 2 0x10e1 9 0 4294967295 OVRD_TX_LOOPBACK 0 0 LOOPBACK_EN_REG 0 0 REFGEN_EN_REG 0 0 CLK_DIV_EN_REG 0 0 DATA_EN_REG_INT 0 0 CLK_EN_REG 0 0 SERIAL_EN_REG 0 0 OVRD_EN 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR3_LANE0_ANA_TX_ALT_BUS 2 0x10e2 6 0 4294967295 DRV_SOURCE_REG 0 0 OVRD_ALT_BUS 0 0 ATB_S_ENABLE 0 0 TX_ALT_RINGO 0 0 JTAG_DATA_REG 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR3_LANE0_ANA_TX_ATB1 2 0x10e3 9 0 4294967295 MEAS_ATB_GD 0 0 MEAS_ATB_VDDH 0 0 OVERRIDE_RXDETREF 0 0 MEAS_ATB_VPTX 0 0 OVERRIDE_REGREF 0 0 MEAS_ATB_VREG_DRV 0 0 MEAS_ATB_VREG 0 0 MEAS_ATB_VPH_HALF 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR3_LANE0_ANA_TX_ATB2 2 0x10e4 9 0 4294967295 MEAS_ATB_VCM 0 0 MEAS_ATB_CAL_VDAC_CM 0 0 MEAS_ATB_CAL_VDAC_DIFF 0 0 MEAS_ATB_TXM 0 0 MEAS_ATB_TXP 0 0 MEAS_ATB_RXDETREF 0 0 LFPS_HIGH_PRIORITY 0 0 OSC_DIV4_EN 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR3_LANE0_ANA_TX_DCC_DAC 2 0x10e5 2 0 4294967295 DCC_DAC_REG 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR3_LANE0_ANA_TX_DCC_CTRL1 2 0x10e6 7 0 4294967295 NC0 0 0 OVRD_DCC_DAC_CTRL_SEL 0 0 DCC_DAC_CTRL_SEL_REG 0 0 OVRD_DCC_DAC_CTRL_EN 0 0 DCC_DAC_CTRL_EN_REG 0 0 OVRD_DCC_DAC_REG 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR3_LANE0_ANA_TX_TERM_CODE 2 0x10e7 2 0 4294967295 TERM_CODE_REG_70 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR3_LANE0_ANA_TX_TERM_CODE_CTRL 2 0x10e8 8 0 4294967295 VREG_BOOST_1 0 0 OVRD_UPDATE_TERM 0 0 UPDATE_TERM_REG 0 0 OVRD_RESET_TERM 0 0 RESET_TERM_REG 0 0 OVRD_TERM_CODE 0 0 TERM_CODE_REG_98 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR3_LANE0_ANA_TX_OVRD_CLK 2 0x10e9 9 0 4294967295 VREG_BOOST_0 0 0 CLK_LB_EN_REG 0 0 OVRD_LB_EN 0 0 MPLLB_CLK_EN_REG 0 0 MPLLA_CLK_EN_REG 0 0 OVRD_MPLLAB_EN 0 0 WORD_CLK_EN_REG 0 0 OVRD_WORD_CLK_EN 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR3_LANE0_ANA_TX_MISC1 2 0x10ea 8 0 4294967295 MEAS_ATB_CAL_CLK_ALIGN 0 0 OVRD_DCC_DAC_CTRL_RANGE 0 0 DCC_DAC_CTRL_RANGE_REG 0 0 OVRD_VREF_SEL 0 0 VREF_SEL_REG 0 0 FORCE_ATB_TXM 0 0 FORCE_ATB_TXP 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR3_LANE0_ANA_TX_MISC2 2 0x10eb 8 0 4294967295 TX_PEAKING_LVL 0 0 VREG_CP_GAIN_CTRL 0 0 TX_SLEW_EN 0 0 EN_INV_POST 0 0 EN_INV_PRE 0 0 TX_VREG_EN_BYP 0 0 TX_VDRIVER_PULLDN_EN 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR3_LANE0_ANA_TX_MISC3 2 0x10ec 4 0 4294967295 TX_VREG_OVRD_RING_CTRL 0 0 TX_DCC_LOWV 0 0 NC7_2 2 7 RESERVED_15_8 8 15 ixDPCSSYS_CR3_LANE0_ANA_TX_RESERVED2 2 0x10ed 2 0 4294967295 NC7_0 0 7 RESERVED_15_8 8 15 ixDPCSSYS_CR3_LANE0_ANA_TX_RESERVED3 2 0x10ee 2 0 4294967295 NC7_0 0 7 RESERVED_15_8 8 15 ixDPCSSYS_CR3_LANE0_ANA_TX_RESERVED4 2 0x10ef 2 0 4294967295 NC7_0 0 7 RESERVED_15_8 8 15 ixDPCSSYS_CR3_LANE1_DIG_ASIC_LANE_OVRD_IN 2 0x1100 5 0 4294967295 LANE_TX2RX_SER_LB 0 0 LANE_RX2TX_PAR_LB 1 1 EN 2 2 RX_ACJTAG_EN 3 3 RESERVED_15_4 4 15 ixDPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_0 2 0x1101 12 0 4294967295 REQ 0 0 REQ_OVRD_EN 1 1 PSTATE 2 3 PSTATE_OVRD_EN 4 4 RATE 5 7 RATE_OVRD_EN 8 8 WIDTH 9 10 WIDTH_OVRD_EN 11 11 MPLLB_SEL 12 12 MPLLB_SEL_OVRD_EN 13 13 DATA_EN 14 14 DATA_EN_OVRD_EN 15 15 ixDPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_1 2 0x1102 11 0 4294967295 NYQUIST_DATA 0 0 DISABLE 1 1 BEACON_EN 2 2 EN 3 3 TX_MAIN_CURSOR 4 9 MAIN_OVRD_EN 10 10 ASYNC_DRV_EN 11 11 ASYNC_DRV_OVRD_EN 12 12 TX_VREGDRV_BYP_OVRD 13 13 TX_VREGDRV_BYP_OVRD_EN 14 14 RESERVED_15_15 15 15 ixDPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_2 2 0x1103 6 0 4294967295 TX_PRE_CURSOR 0 5 PRE_OVRD_EN 6 6 TX_POST_CURSOR 7 12 POST_OVRD_EN 13 13 HDMIMODE_EN 14 14 HDMIMODE_ENABLE_OVRD_EN 15 15 ixDPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_3 2 0x1104 15 0 4294967295 CLK_RDY 0 0 CLK_RDY_OVRD_EN 1 1 DETECT_RX_REQ 2 2 DETECT_RX_REQ_OVRD_EN 3 3 INVERT 4 4 INVERT_OVRD_EN 5 5 LPD 6 6 LPD_OVRD_EN 7 7 TX_DC_COUP_EN 8 8 TX_DC_COUP_EN_OVRD_EN 9 9 PMA_EXTENDED_FIFO_EN 10 10 PMA_EXTENDED_FIFO_EN_OVRD_EN 11 11 TX_MPHY_MODE_EN 12 12 TX_MPHY_MODE_EN_OVRD_EN 13 13 RESERVED_15_14 14 15 ixDPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_4 2 0x1105 3 0 4294967295 RESET 0 0 RESET_OVRD_EN 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_OUT 2 0x1106 5 0 4294967295 TX_ACK 0 0 EN_TX_ACK 1 1 DETRX_RESULT 2 2 EN_DETRX_RESULT 3 3 RESERVED_15_4 4 15 ixDPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_0 2 0x1107 11 0 4294967295 REQ 0 0 REQ_OVRD_EN 1 1 DATA_EN 2 2 DATA_EN_OVRD_EN 3 3 PSTATE 4 5 PSTATE_OVRD_EN 6 6 RATE 7 8 RATE_OVRD_EN 9 9 WIDTH 10 11 WIDTH_OVRD_EN 12 12 RESERVED_15_13 13 15 ixDPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_1 2 0x1108 5 0 4294967295 RX_REF_LD_VAL_5_0 0 5 RX_CDR_VCO_LOWFREQ 6 6 EN 7 7 RX_REF_LD_VAL_6 8 8 RESERVED_15_9 9 15 ixDPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_2 2 0x1109 3 0 4294967295 RX_VCO_LD_VAL 0 12 EN 13 13 RESERVED_15_14 14 15 ixDPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_3 2 0x110a 11 0 4294967295 CDR_TRACK_EN 0 0 CDR_TRACK_EN_OVRD_EN 1 1 CDR_SSC_EN 2 2 CDR_SSC_EN_OVRD_EN 3 3 ALIGN_EN 4 4 ALIGN_EN_OVRD_EN 5 5 CLK_SHIFT 6 6 CLK_SHIFT_OVRD_EN 7 7 DISABLE 8 8 DISABLE_OVRD_EN 9 9 RESERVED_15_10 10 15 ixDPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_4 2 0x110b 11 0 4294967295 LPD 0 0 LPD_OVRD_EN 1 1 INVERT 2 2 INVERT_OVRD_EN 3 3 ADAPT_AFE_EN 4 4 ADAPT_DFE_EN 5 5 ADPT_OVRD_EN 6 6 TERM_EN 7 7 TERM_ACDC 8 8 TERM_OVRD_EN 9 9 RESERVED_15_10 10 15 ixDPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_5 2 0x110c 3 0 4294967295 RESET 0 0 RESET_OVRD_EN 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0 2 0x110d 4 0 4294967295 EQ_ATT_LVL 0 2 EQ_AFE_GAIN 3 6 RESERVED 7 10 EQ_CTLE_BOOST 11 15 ixDPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1 2 0x110e 3 0 4294967295 EQ_DFE_TAP2 0 6 EQ_DFE_TAP1 7 14 EQ_OVRD_EN 15 15 ixDPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_OUT_0 2 0x110f 9 0 4294967295 ACK 0 0 ACK_OVRD_EN 1 1 ADAPT_STS 2 3 ADAPT_STS_OVRD_EN 4 4 RX_ASYNC_DATA 5 5 RX_ASYNC_DATA_OVRD_EN 6 6 RX_SQ_WEAKKEEP_OUT 7 7 RX_SQ_WEAKKEEP_OUT_OVRD_EN 8 8 RESERVED_15_9 9 15 ixDPCSSYS_CR3_LANE1_DIG_ASIC_LANE_ASIC_IN 2 0x1110 3 0 4294967295 LANE_TX2RX_SER_LB 0 0 LANE_RX2TX_PAR_LB 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR3_LANE1_DIG_ASIC_TX_ASIC_IN_0 2 0x1111 12 0 4294967295 CLK_RDY 0 0 RESET 1 1 INVERT 2 2 DATA_EN 3 3 REQ 4 4 LPD 5 5 PSTATE 6 7 RATE 8 10 WIDTH 11 12 MPLLB_SEL 13 13 DETECT_RX_REQ 14 14 DISABLE 15 15 ixDPCSSYS_CR3_LANE1_DIG_ASIC_TX_ASIC_IN_1 2 0x1112 7 0 4294967295 BEACON_EN 0 0 TX_MAIN_CURSOR 1 6 TX_ASYNC_EN 7 7 TX_ASYNC_DATA 8 8 TX_ASYNC_DRV_EN 9 9 TX_VREGDRV_BYP 10 10 RESERVED_15_11 11 15 ixDPCSSYS_CR3_LANE1_DIG_ASIC_TX_ASIC_IN_2 2 0x1113 3 0 4294967295 TX_PRE_CURSOR 0 5 TX_POST_CURSOR 6 11 RESERVED_15_12 12 15 ixDPCSSYS_CR3_LANE1_DIG_ASIC_TX_ASIC_OUT 2 0x1114 3 0 4294967295 TX_ACK 0 0 DETRX_RESULT 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR3_LANE1_DIG_ASIC_RX_ASIC_IN_0 2 0x1115 13 0 4294967295 RESET 0 0 INVERT 1 1 DATA_EN 2 2 REQ 3 3 LPD 4 4 PSTATE 5 6 RATE 7 8 WIDTH 9 10 RESERVED 11 11 ADAPT_AFE_EN 12 12 ADAPT_DFE_EN 13 13 CDR_TRACK_EN 14 14 RESERVED_15_15 15 15 ixDPCSSYS_CR3_LANE1_DIG_ASIC_RX_ASIC_IN_1 2 0x1116 7 0 4294967295 CDR_SSC_EN 0 0 ALIGN_EN 1 1 CLK_SHIFT 2 2 DISABLE 3 3 RX_TERM_EN 4 4 RX_TERM_ACDC 5 5 RESERVED_15_6 6 15 ixDPCSSYS_CR3_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0 2 0x1117 4 0 4294967295 EQ_ATT_LVL 0 2 EQ_AFE_GAIN 3 6 RESERVED 7 10 EQ_CTLE_BOOST 11 15 ixDPCSSYS_CR3_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_1 2 0x1118 3 0 4294967295 EQ_DFE_TAP2 0 6 EQ_DFE_TAP1 7 14 RESERVED_15_15 15 15 ixDPCSSYS_CR3_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0 2 0x1119 3 0 4294967295 RX_CDR_VCO_LOWFREQ 0 0 RX_REF_LD_VAL 1 7 RESERVED_15_8 8 15 ixDPCSSYS_CR3_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1 2 0x111a 2 0 4294967295 RX_VCO_LD_VAL 0 12 RESERVED_15_13 13 15 ixDPCSSYS_CR3_LANE1_DIG_ASIC_RX_ASIC_OUT_0 2 0x111b 4 0 4294967295 ACK 0 0 VALID 1 1 ADAPT_STS 2 3 RESERVED_15_4 4 15 ixDPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_6 2 0x111c 10 0 4294967295 RX_PWM_CLK_SEL 0 1 RX_PWM_CLK_SEL_OVRD_EN 2 2 RX_TERM_LCC_ON 3 3 RX_TERM_LS_ON 4 4 RX_TERM_LS_LCC_ON_OVRD_EN 5 5 RX_TERM_CTL 6 7 RX_TERM_CTL_OVRD_EN 8 8 RX_PWM_EN 9 9 RX_PWM_EN_OVRD_EN 10 10 RESERVED_15_11 11 15 ixDPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_5 2 0x111d 15 0 4294967295 RPTR_EN_MASTER_LANE 0 0 RPTR_EN_MASTER_LANE_OVRD_EN 1 1 DIG_CLK_EN_OTHER_LANE 2 2 DIG_CLK_EN_OTHER_LANE_OVRD_EN 3 3 DIG_CLK_STATE_MASTER_LANE 4 4 DIG_CLK_STATE_MASTER_LANE_OVRD_EN 5 5 SHIFT_MASTER_LANE 6 6 SHIFT_MASTER_LANE_ORVD_EN 7 7 SHIFT_ACK_OTHER_LANE 8 8 SHIFT_ACK_OTHER_LANE_OVRD_EN 9 9 LANE_MASTER 10 10 LANE_MASTER_OVRD_IN_EN 11 11 TX_DWORD_CLK_SYNC_OVRD 12 12 TX_DWORD_CLK_SYNC_OVRD_EN 13 13 RESERVED_15_14 14 15 ixDPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_OUT_1 2 0x111e 11 0 4294967295 RPTR_EN_OUT 0 0 RPTR_EN_OUT_OVRD_EN 1 1 DIG_CLK_EN_OUT 2 2 DIG_CLK_EN_OUT_OVRD_EN 3 3 DIG_CLK_STATE_OUT 4 4 DIG_CLK_STATE_OUT_OVRD_EN 5 5 SHIFT_OUT 6 6 SHIFT_OUT_OVRD_EN 7 7 SHIFT_ACK_OUT 8 8 SHIFT_ACK_OUT_OVRD_EN 9 9 RESERVED_15_10 10 15 ixDPCSSYS_CR3_LANE1_DIG_ASIC_OCLA 2 0x111f 3 0 4294967295 RX_DWORD_OCLA_CLK_EN 0 0 RX_DWORD_OCLA_DATA_EN 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0 2 0x1120 11 0 4294967295 TX_P0_ANA_REFGEN_EN 0 0 TX_P0_ANA_VCM_HOLD 1 1 TX_P0_ANA_CLK_EN 2 2 TX_P0_ANA_WORD_CLK_EN 3 3 TX_P0_ANA_RESET 4 4 TX_P0_ANA_SERIAL_EN 5 5 TX_P0_DIG_CLK_EN 6 6 TX_P0_DATA_EN 7 7 TX_P0_ALLOW_RXDET 8 8 TX_P0_ANA_DCC_COMP_CAL_EN 9 9 RESERVED_15_10 10 15 ixDPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S 2 0x1121 11 0 4294967295 TX_P0S_ANA_REFGEN_EN 0 0 TX_P0S_ANA_VCM_HOLD 1 1 TX_P0S_ANA_CLK_EN 2 2 TX_P0S_ANA_WORD_CLK_EN 3 3 TX_P0S_ANA_RESET 4 4 TX_P0S_ANA_SERIAL_EN 5 5 TX_P0S_DIG_CLK_EN 6 6 TX_P0S_DATA_EN 7 7 TX_P0S_ALLOW_RXDET 8 8 TX_P0S_ANA_DCC_COMP_CAL_EN 9 9 RESERVED_15_10 10 15 ixDPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1 2 0x1122 11 0 4294967295 TX_P1_ANA_REFGEN_EN 0 0 TX_P1_ANA_VCM_HOLD 1 1 TX_P1_ANA_CLK_EN 2 2 TX_P1_ANA_WORD_CLK_EN 3 3 TX_P1_ANA_RESET 4 4 TX_P1_ANA_SERIAL_EN 5 5 TX_P1_DIG_CLK_EN 6 6 TX_P1_DATA_EN 7 7 TX_P1_ALLOW_RXDET 8 8 TX_P1_ANA_DCC_COMP_CAL_EN 9 9 RESERVED_15_10 10 15 ixDPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2 2 0x1123 12 0 4294967295 TX_P2_ANA_REFGEN_EN 0 0 TX_P2_ANA_VCM_HOLD 1 1 TX_P2_ANA_CLK_EN 2 2 TX_P2_ANA_WORD_CLK_EN 3 3 TX_P2_ANA_RESET 4 4 TX_P2_ANA_SERIAL_EN 5 5 TX_P2_DIG_CLK_EN 6 6 TX_P2_DATA_EN 7 7 TX_P2_ALLOW_RXDET 8 8 TX_P2_ALLOW_VBOOST 9 9 TX_P2_ANA_DCC_COMP_CAL_EN 10 10 RESERVED_15_11 11 15 ixDPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_0 2 0x1124 2 0 4294967295 TX_REFGEN_EN_TIME 0 7 TX_CLK_EN 8 15 ixDPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_1 2 0x1125 2 0 4294967295 TX_VCM_HOLD_TIME_14_0 0 14 SKIP_TX_VCM_HOLD_WAIT 15 15 ixDPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_2 2 0x1126 2 0 4294967295 TX_VBOOST_DIS_TIME_12_0 0 12 DTB_SEL 13 15 ixDPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_3 2 0x1127 3 0 4294967295 TX_VCM_HOLD_TIME_17_15 0 2 TX_VBOOST_DIS_TIME_13 3 3 RESERVED_15_4 4 15 ixDPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_4 2 0x1128 2 0 4294967295 TX_VCM_HOLD_GS_TIME 0 14 SKIP_TX_VCM_HOLD_GS_PULSE 15 15 ixDPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_5 2 0x1129 5 0 4294967295 TX_RXDET_TIME 0 9 FAST_TX_RXDET 10 10 TX_RESET_TIME 11 12 TX_SERIAL_EN_TIME 13 14 RESERVED_15_15 15 15 ixDPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_DCC_CR_BANK_ADDR 2 0x112a 1 0 4294967295 ADDR 0 15 ixDPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_DCC_CR_BANK_DATA 2 0x112b 1 0 4294967295 DATA 0 15 ixDPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_DCC_DAC_CTRL 2 0x112c 2 0 4294967295 CTRL 0 7 RESERVED_15_8 8 15 ixDPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_DCC_DAC_RANGE 2 0x112d 2 0 4294967295 CTRL 0 1 RESERVED_15_2 2 15 ixDPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_DCC_DAC_SEL 2 0x112e 6 0 4294967295 SEL 0 2 REQ 3 3 CTRL_UPD 4 4 RANGE_UPD 5 5 BIN_HOT 6 6 RESERVED_15_7 7 15 ixDPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_DCC_DAC_ACK 2 0x112f 2 0 4294967295 ACK 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_DCC_DAC_ADDR 2 0x1130 1 0 4294967295 ADDR 0 15 ixDPCSSYS_CR3_LANE1_DIG_TX_CLK_ALIGN_TX_CTL_0 2 0x1131 4 0 4294967295 TX_NUM_2UI_SHIFTS_16B_MODE 0 3 TX_NUM_2UI_SHIFTS_20B_MODE 4 7 TX_FIFO_BYPASS 8 8 RESERVED_15_9 9 15 ixDPCSSYS_CR3_LANE1_DIG_TX_LBERT_CTL 2 0x1132 4 0 4294967295 MODE 0 3 TRIGGER_ERR 4 4 PAT0 5 14 RESERVED_15_15 15 15 ixDPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0 2 0x1140 12 0 4294967295 RX_P0_ANA_AFE_EN 0 0 RX_P0_ANA_CLK_VREG_EN 1 1 RESERVED_1 2 2 RX_P0_ANA_CLK_EN 3 3 RESERVED_0 4 4 RX_P0_ANA_DESER_EN 5 5 RX_P0_ANA_CDR_EN 6 6 RX_P0_VCO_FREQ_RST 7 7 RX_P0_VCO_CAL_RST 8 8 RX_P0_VCO_CONTCAL_EN 9 9 RX_P0_DIG_CLK_EN 10 10 RESERVED_15_11 11 15 ixDPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S 2 0x1141 12 0 4294967295 RX_P0S_ANA_AFE_EN 0 0 RX_P0S_ANA_CLK_VREG_EN 1 1 RESERVED_2 2 2 RX_P0S_ANA_CLK_EN 3 3 RESERVED_4 4 4 RX_P0S_ANA_DESER_EN 5 5 RX_P0S_ANA_CDR_EN 6 6 RX_P0S_VCO_FREQ_RST 7 7 RX_P0S_VCO_CAL_RST 8 8 RX_P0S_VCO_CONTCAL_EN 9 9 RX_P0S_DIG_CLK_EN 10 10 RESERVED_15_11 11 15 ixDPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1 2 0x1142 12 0 4294967295 RX_P1_ANA_AFE_EN 0 0 RX_P1_ANA_CLK_VREG_EN 1 1 RESERVED_2 2 2 RX_P1_ANA_CLK_EN 3 3 RESERVED_4 4 4 RX_P1_ANA_DESER_EN 5 5 RX_P1_ANA_CDR_EN 6 6 RX_P1_VCO_FREQ_RST 7 7 RX_P1_VCO_CAL_RST 8 8 RX_P1_VCO_CONTCAL_EN 9 9 RX_P1_DIG_CLK_EN 10 10 RESERVED_15_11 11 15 ixDPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2 2 0x1143 12 0 4294967295 RX_P2_ANA_AFE_EN 0 0 RX_P2_ANA_CLK_VREG_EN 1 1 RESERVED_2 2 2 RX_P2_ANA_CLK_EN 3 3 RESERVED_4 4 4 RX_P2_ANA_DESER_EN 5 5 RX_P2_ANA_CDR_EN 6 6 RX_P2_VCO_FREQ_RST 7 7 RX_P2_VCO_CAL_RST 8 8 RX_P2_VCO_CONTCAL_EN 9 9 RX_P2_DIG_CLK_EN 10 10 RESERVED_15_11 11 15 ixDPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1 2 0x1145 5 0 4294967295 RX_AFE_EN_TIME 0 5 FAST_RX_AFE_EN 6 6 RX_VREG_EN_TIME 7 12 FAST_RX_VREG_EN 13 13 RESERVED_15_14 14 15 ixDPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_2 2 0x1146 4 0 4294967295 RX_CLK_EN_TIME 0 5 FAST_RX_CLK_EN 6 6 RX_FAST_START_TIME 7 10 RESERVED_15_11 11 15 ixDPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_3 2 0x1147 5 0 4294967295 RX_RATE_TIME 0 1 RSVD_3_7_2 2 7 RX_CDR_EN_TIME 8 11 RX_DESER_EN_TIME 12 13 RX_DESER_DIS_TIME 14 15 ixDPCSSYS_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0 2 0x1148 8 0 4294967295 INT_GAIN_CAL_FIXED_CNT 0 4 INT_GAIN_CAL_FIXED_CNT_EN 5 5 INT_GAIN_CAL_CNT_SHIFT 6 8 INT_GAIN_CAL_BOUNCE_CNT 9 11 DISABLE_BIN_HOLD 12 12 DISABLE_INT_GAIN_HOLD 13 13 DISABLE_COARSE_CALDONE 14 14 RESERVED_15_15 15 15 ixDPCSSYS_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1 2 0x1149 7 0 4294967295 RX_VCO_OVRD_SEL 0 0 RX_VCO_FREQ_RST 1 1 RX_VCO_CAL_RST 2 2 RX_VCO_CONTCAL_EN 3 3 DISABLE_INT_CAL_MODE 4 4 DPLL_CAL_UG 5 8 DTB_SEL 9 15 ixDPCSSYS_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2 2 0x114a 4 0 4294967295 FREQ_TUNE_START_VAL 0 9 FREQ_TUNE_CAL_STEPS 10 13 SKIP_RX_VCO_FREQ_TUNE_CAL 14 14 SKIP_RX_VCO_CAL 15 15 ixDPCSSYS_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0 2 0x114b 4 0 4294967295 RX_VCO_STARTUP_TIME 0 6 RX_VCO_UPDATE_TIME 7 10 RX_VCO_CNTR_PWRUP_TIME 11 14 FAST_RX_VCO_WAIT 15 15 ixDPCSSYS_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1 2 0x114c 2 0 4294967295 RX_VCO_CNTR_SETTLE_TIME 0 2 RESERVED_15_3 3 15 ixDPCSSYS_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0 2 0x114d 6 0 4294967295 RX_ANA_CDR_FREQ_TUNE 0 9 RX_ANA_VCO_CNTR_PD 10 10 RX_ANA_VCO_CNTR_EN 11 11 RX_ANA_CDR_STARTUP 12 12 RX_ANA_CDR_VCO_EN 13 13 RESERVED_15_14 14 15 ixDPCSSYS_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1 2 0x114e 7 0 4294967295 RX_VCO_FSM_STATE 0 3 RX_VCO_FREQ_RST 4 4 RX_VCO_CAL_RST 5 5 RX_VCO_CONTCAL_EN 6 6 RX_VCO_CAL_DONE 7 7 DPLL_FREQ_RST 8 8 RESERVED_15_9 9 15 ixDPCSSYS_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_2 2 0x114f 4 0 4294967295 VCO_CNTR_FINAL 0 12 VCOCLK_TOO_FAST 13 13 RX_VCO_CORRECT 14 14 RX_VCO_UP 15 15 ixDPCSSYS_CR3_LANE1_DIG_RX_RX_ALIGN_XAUI_COMM_MASK 2 0x1150 2 0 4294967295 XAUI_COMM_MASK 0 9 RESERVED_15_10 10 15 ixDPCSSYS_CR3_LANE1_DIG_RX_LBERT_CTL 2 0x1151 3 0 4294967295 MODE 0 3 SYNC 4 4 RESERVED_15_5 5 15 ixDPCSSYS_CR3_LANE1_DIG_RX_LBERT_ERR 2 0x1152 2 0 4294967295 COUNT 0 14 OV14 15 15 ixDPCSSYS_CR3_LANE1_DIG_RX_CDR_CDR_CTL_0 2 0x1153 7 0 4294967295 PHDET_EN 0 1 PHDET_EDGE 2 3 PHDET_POL 4 4 PHDET_EN_PR_MODE 5 5 ALWAYS_REALIGN 6 6 DTB_SEL 7 10 RESERVED_15_11 11 15 ixDPCSSYS_CR3_LANE1_DIG_RX_CDR_CDR_CTL_1 2 0x1154 2 0 4294967295 SSC_OFF_CNT0 0 9 SSC_OFF_CNT1 10 15 ixDPCSSYS_CR3_LANE1_DIG_RX_CDR_CDR_CTL_2 2 0x1155 2 0 4294967295 SSC_ON_CNT0 0 8 SSC_ON_CNT1 9 15 ixDPCSSYS_CR3_LANE1_DIG_RX_CDR_CDR_CTL_3 2 0x1156 6 0 4294967295 SSC_OFF_PHUG0 0 2 SSC_OFF_PHUG1 3 5 SSC_OFF_FRUG0 6 8 OVRD_DPLL_GAIN 9 9 PHUG_OVRD_VALUE 10 12 FRUG_OVRD_VALUE 13 15 ixDPCSSYS_CR3_LANE1_DIG_RX_CDR_CDR_CTL_4 2 0x1157 6 0 4294967295 SSC_OFF_FRUG1 0 2 SSC_ON_FRUG0 3 5 SSC_ON_FRUG1 6 8 SSC_ON_PHUG0 9 11 SSC_ON_PHUG1 12 14 RESERVED_15_15 15 15 ixDPCSSYS_CR3_LANE1_DIG_RX_CDR_STAT 2 0x1158 3 0 4294967295 PHUG_VALUE 0 2 FRUG_VALUE 3 5 RESERVED_15_6 6 15 ixDPCSSYS_CR3_LANE1_DIG_RX_DPLL_FREQ 2 0x1159 2 0 4294967295 VAL 0 13 RESERVED_15_14 14 15 ixDPCSSYS_CR3_LANE1_DIG_RX_DPLL_FREQ_BOUND_0 2 0x115a 3 0 4294967295 FREQ_BOUND_EN 0 0 UPPER_FREQ_BOUND 1 10 RESERVED_15_11 11 15 ixDPCSSYS_CR3_LANE1_DIG_RX_DPLL_FREQ_BOUND_1 2 0x115b 2 0 4294967295 LOWER_FREQ_BOUND 0 9 RESERVED_15_10 10 15 ixDPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_0 2 0x1160 4 0 4294967295 N_TOP_ASM1 0 9 N_TGG_ASM1 10 13 START_ASM1 14 14 ADPT_CLK_DIV4_EN 15 15 ixDPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1 2 0x1161 5 0 4294967295 N_WAIT_ASM1 0 6 FAST_AFE_DFE_SETTLE 7 7 CTLE_POLE_OVRD_VAL 8 10 CTLE_POLE_OVRD_EN 11 11 RESERVED_15_12 12 15 ixDPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_2 2 0x1162 3 0 4294967295 TGG_PTTRN_0 0 4 TGG_PTTRN_1 5 9 RESERVED_15_10 10 15 ixDPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3 2 0x1163 8 0 4294967295 CTLE_EN 0 4 VGA_EN 5 5 ATT_EN 6 6 DFE_EN 7 11 EYEHE_EN 12 12 EYEHO_EN 13 13 TGG_EN 14 14 ESL_TWICE_DSL 15 15 ixDPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_4 2 0x1164 4 0 4294967295 CTLE_TH 0 3 VGA_TH 4 7 DFE1_TH 8 11 DFE2_TH 12 15 ixDPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_5 2 0x1165 4 0 4294967295 DFE3_TH 0 3 DFE4_TH 4 7 DFE5_TH 8 11 TH_OFFSET 12 15 ixDPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6 2 0x1166 6 0 4294967295 CTLE_MU 0 2 VGA_MU 3 5 ATT_MU 6 8 VGA_SAT_CNT 9 11 VGA_SAT_CNT_STICKY 12 12 ATT_LOW_TH 13 15 ixDPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_7 2 0x1167 4 0 4294967295 VGA_MIN_SAT 0 4 VGA_LEV_HIGH 5 9 VGA_LEV_LOW 10 14 RESERVED_15_15 15 15 ixDPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8 2 0x1168 6 0 4294967295 DFE1_MU 0 2 DFE2_MU 3 5 DFE3_MU 6 8 DFE4_MU 9 11 DFE5_MU 12 14 RESERVED_15_15 15 15 ixDPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_9 2 0x1169 2 0 4294967295 ERR_SLE_ADPT_INIT 0 7 ERR_SLO_ADPT_INIT 8 15 ixDPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG 2 0x116a 6 0 4294967295 RST_ADPT_ATT 0 0 RST_ADPT_VGA 1 1 RST_ADPT_CTLE_BOOST 2 2 RST_ADPT_CTLE_POLE 3 3 RST_ADPT_TAP1 4 4 RESERVED_15_5 5 15 ixDPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ATT_STATUS 2 0x116b 3 0 4294967295 ATT_ADPT_CODE 0 7 ASM1_DON 8 8 RESERVED_15_9 9 15 ixDPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_VGA_STATUS 2 0x116c 3 0 4294967295 VGA_ADPT_CODE 0 9 ASM1_DONE 10 10 RESERVED_15_11 11 15 ixDPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_CTLE_STATUS 2 0x116d 4 0 4294967295 CTLE_BOOST_ADPT_CODE 0 9 CTLE_POLE_ADPT_CODE 10 12 ASM1_DONE 13 13 RESERVED_15_14 14 15 ixDPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_DFE_TAP1_STATUS 2 0x116e 3 0 4294967295 DFE_TAP1_ADPT_CODE 0 12 ASM1_DONE 13 13 RESERVED_15_14 14 15 ixDPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_DFE_TAP2_STATUS 2 0x116f 3 0 4294967295 DFE_TAP2_ADPT_CODE 0 11 ASM1_DONE 12 12 RESERVED_15_13 13 15 ixDPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_DFE_TAP3_STATUS 2 0x1170 3 0 4294967295 DFE_TAP3_ADPT_CODE 0 11 ASM1_DONE 12 12 RESERVED_15_13 13 15 ixDPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_DFE_TAP4_STATUS 2 0x1171 3 0 4294967295 DFE_TAP4_ADPT_CODE 0 11 ASM1_DONE 12 12 RESERVED_15_13 13 15 ixDPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_DFE_TAP5_STATUS 2 0x1172 3 0 4294967295 DFE_TAP5_ADPT_CODE 0 11 ASM1_DONE 12 12 RESERVED_15_13 13 15 ixDPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_DFE_DATA_EVEN_VDAC_OFST 2 0x1173 2 0 4294967295 DFE_DATA_EVEN_VDAC_OFST 0 7 RESERVED_15_8 8 15 ixDPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_DFE_DATA_ODD_VDAC_OFST 2 0x1174 2 0 4294967295 DFE_DATA_ODD_VDAC_OFST 0 7 RESERVED_15_8 8 15 ixDPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN 2 0x1175 2 0 4294967295 RX_ANA_SLICER_CTRL_E 0 3 RESERVED_15_4 4 15 ixDPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD 2 0x1176 2 0 4294967295 RX_ANA_SLICER_CTRL_O 0 3 RESERVED_15_4 4 15 ixDPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST 2 0x1177 2 0 4294967295 DFE_ERROR_EVEN_VDAC_OFST 0 7 RESERVED_15_8 8 15 ixDPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST 2 0x1178 2 0 4294967295 DFE_ERROR_ODD_VDAC_OFST 0 7 RESERVED_15_8 8 15 ixDPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL 2 0x1179 2 0 4294967295 E_SLO_LVL 0 7 E_SLE_LVL 8 15 ixDPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_RESET 2 0x117a 2 0 4294967295 RESET_ASM1 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1 2 0x117b 4 0 4294967295 DFE_T1_IDAC 0 4 DFE_T2_IDAC 5 9 DCC_START_IDAC 10 14 RESERVED_15_15 15 15 ixDPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2 2 0x117c 3 0 4294967295 DFE_DAT_EVEN_VDAC 0 4 DFE_DAT_ODD_VDAC 5 9 RESERVED_15_10 10 15 ixDPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3 2 0x117d 3 0 4294967295 DFE_ERR_EVEN_VDAC 0 4 DFE_ERR_ODD_VDAC 5 9 RESERVED_15_10 10 15 ixDPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_CR_BANK_ADDR 2 0x117e 1 0 4294967295 ADDR 0 15 ixDPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_CR_BANK_DATA 2 0x117f 1 0 4294967295 DATA 0 15 ixDPCSSYS_CR3_LANE1_DIG_RX_STAT_LD_VAL_1 2 0x1180 2 0 4294967295 SC1_LD_VAL 0 14 SC1_START 15 15 ixDPCSSYS_CR3_LANE1_DIG_RX_STAT_DATA_MSK 2 0x1181 1 0 4294967295 DATA_MSK_15_0 0 15 ixDPCSSYS_CR3_LANE1_DIG_RX_STAT_MATCH_CTL0 2 0x1182 4 0 4294967295 PTTRN_MSK_CR1A_4_0 0 4 PTTRN_CR1A_4_0 5 9 DATA_MSK_19_16 10 13 SCOPE_DLY 14 15 ixDPCSSYS_CR3_LANE1_DIG_RX_STAT_MATCH_CTL1 2 0x1183 5 0 4294967295 PTTRN_CR1B_EN 0 0 PTTRN_MSK_CR1B_4_0 1 5 PTTRN_CR1B_4_0 6 10 PTTRN_CR1A_ADPT_EN 11 11 RESERVED_15_12 12 15 ixDPCSSYS_CR3_LANE1_DIG_RX_STAT_STAT_CTL0 2 0x1184 10 0 4294967295 RESERVED_0 0 0 CORR_SHFT_SEL_VGA 1 1 CORR_SHFT_SEL 2 2 CORR_SRC_SEL 3 4 CORR_MODE_EN 5 5 STAT_SHFT_SEL 6 9 STAT_SRC_SEL 10 12 STAT_RXCLK_SEL 13 13 SC_TIMER_MODE 14 14 SKIP_EN 15 15 ixDPCSSYS_CR3_LANE1_DIG_RX_STAT_STAT_CTL1 2 0x1185 13 0 4294967295 STAT_CNT_0_EN 0 0 STAT_CNT_1_EN 1 1 STAT_CNT_2_EN 2 2 STAT_CNT_3_EN 3 3 STAT_CNT_4_EN 4 4 STAT_CNT_5_EN 5 5 STAT_CNT_6_EN 6 6 RESERVED_8_7 7 8 SC_PAUSE 9 9 STAT_CLK_EN 10 10 DATA_DLY_SEL 11 12 VLD_LOSS_CLR 13 13 VLD_CTL 14 15 ixDPCSSYS_CR3_LANE1_DIG_RX_STAT_SMPL_CNT1 2 0x1186 2 0 4294967295 SMPL_CNT1 0 14 SMPL_CNT1_DONE 15 15 ixDPCSSYS_CR3_LANE1_DIG_RX_STAT_STAT_CNT_0 2 0x1187 2 0 4294967295 STAT_CNT_0 0 14 SMPL_CNT1_DONE 15 15 ixDPCSSYS_CR3_LANE1_DIG_RX_STAT_STAT_CNT_1 2 0x1188 2 0 4294967295 STAT_CNT_1 0 14 SMPL_CNT1_DONE 15 15 ixDPCSSYS_CR3_LANE1_DIG_RX_STAT_STAT_CNT_2 2 0x1189 2 0 4294967295 STAT_CNT_2 0 14 SMPL_CNT1_DONE 15 15 ixDPCSSYS_CR3_LANE1_DIG_RX_STAT_STAT_CNT_3 2 0x118a 2 0 4294967295 STAT_CNT_3 0 14 SMPL_CNT1_DONE 15 15 ixDPCSSYS_CR3_LANE1_DIG_RX_STAT_STAT_CNT_4 2 0x118b 2 0 4294967295 STAT_CNT_4 0 14 SMPL_CNT1_DONE 15 15 ixDPCSSYS_CR3_LANE1_DIG_RX_STAT_STAT_CNT_5 2 0x118c 2 0 4294967295 STAT_CNT_5 0 14 SMPL_CNT1_DONE 15 15 ixDPCSSYS_CR3_LANE1_DIG_RX_STAT_STAT_CNT_6 2 0x118d 2 0 4294967295 STAT_CNT_6 0 14 SMPL_CNT1_DONE 15 15 ixDPCSSYS_CR3_LANE1_DIG_RX_STAT_CAL_COMP_CLK_CTL 2 0x118e 3 0 4294967295 PRECHRGE_CNT 0 2 REF_DIV_CNT 3 5 RESERVED_15_6 6 15 ixDPCSSYS_CR3_LANE1_DIG_RX_STAT_MATCH_CTL2 2 0x118f 2 0 4294967295 PTTRN_CR1A_19_5 0 14 RESERVED_15_15 15 15 ixDPCSSYS_CR3_LANE1_DIG_RX_STAT_MATCH_CTL3 2 0x1190 2 0 4294967295 PTTRN_MSK_CR1A_19_5 0 14 RESERVED_15_15 15 15 ixDPCSSYS_CR3_LANE1_DIG_RX_STAT_MATCH_CTL4 2 0x1191 2 0 4294967295 PTTRN_CR1B_19_5 0 14 RESERVED_15_15 15 15 ixDPCSSYS_CR3_LANE1_DIG_RX_STAT_MATCH_CTL5 2 0x1192 2 0 4294967295 PTTRN_MSK_CR1B_19_5 0 14 RESERVED_15_15 15 15 ixDPCSSYS_CR3_LANE1_DIG_RX_STAT_STAT_CTL2 2 0x1193 4 0 4294967295 DATA_DLY_SEL_2 0 0 SCOPE_DLY_2 1 1 DISABLE_SAMPLE_COUNT 2 2 RESERVED_15_3 3 15 ixDPCSSYS_CR3_LANE1_DIG_RX_STAT_STAT_STOP 2 0x1194 2 0 4294967295 SC1_STOP 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR3_LANE1_DIG_MPHY_RX_PWM_CTL 2 0x1195 3 0 4294967295 RX_PWM_POL 0 0 RX_PWM_DATA_POL 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR3_LANE1_DIG_MPHY_RX_TERM_LS_CTL 2 0x1196 2 0 4294967295 RX_TERM_LCC_CNT 0 2 RESERVED_15_3 3 15 ixDPCSSYS_CR3_LANE1_DIG_MPHY_RX_ANA_PWM_CLK_STABLE_CNT 2 0x1197 2 0 4294967295 PWM_CLK_STABLE_CNT 0 3 RESERVED_15_4 4 15 ixDPCSSYS_CR3_LANE1_DIG_ANA_TX_OVRD_OUT 2 0x11a0 15 0 4294967295 TX_ANA_CLK_SHIFT 0 0 TX_ANA_DATA_EN 1 1 TX_ANA_REFGEN_EN 2 2 TX_ANA_VCM_HOLD 3 3 TX_ANA_CLK_EN 4 4 TX_ANA_WORD_CLK_EN 5 5 TX_ANA_MPLLA_CLK_EN 6 6 TX_ANA_MPLLB_CLK_EN 7 7 TX_ANA_RESET 8 8 TX_ANA_SERIAL_EN 9 9 TX_ANA_DATA_RATE 10 11 RESERVED 12 12 TX_DIV4_EN 13 13 TX_RXDET_EN 14 14 TX_OVRD_EN 15 15 ixDPCSSYS_CR3_LANE1_DIG_ANA_TX_TERM_CODE_OVRD_OUT 2 0x11a1 5 0 4294967295 TX_TERM_CODE 0 9 TX_TERM_OVRD_EN 10 10 TX_DRV_SRC 11 12 TX_DRV_SRC_OVRD_EN 13 13 RESERVED_15_14 14 15 ixDPCSSYS_CR3_LANE1_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT 2 0x11a2 3 0 4294967295 TX_TERM_DN_CLK 0 0 TX_TERM_CLK_SELF_CLEAR_DISABLE 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR3_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_0 2 0x11a3 3 0 4294967295 TX_ANA_LOAD_CLK 0 0 TX_ANA_CTRL_LEG_PULL_EN_13_0 1 14 TX_EQ_OVRD_EN 15 15 ixDPCSSYS_CR3_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_1 2 0x11a4 2 0 4294967295 TX_ANA_CTRL_LEG_PULL_EN_19_14 0 5 RESERVED_15_6 6 15 ixDPCSSYS_CR3_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_2 2 0x11a5 4 0 4294967295 RESERVED 0 2 TX_ANA_CTRL_EQ_MUX_SEL 3 6 TX_ANA_CTRL_PRE 7 12 RESERVED_15_13 13 15 ixDPCSSYS_CR3_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_3 2 0x11a6 2 0 4294967295 TX_ANA_CTRL_POST 0 8 RESERVED_15_9 9 15 ixDPCSSYS_CR3_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_4 2 0x11a7 1 0 4294967295 TX_ANA_CTRL_LEG_PULL_DIR_19_4 0 15 ixDPCSSYS_CR3_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_5 2 0x11a8 2 0 4294967295 TX_ANA_CTRL_LEG_PULL_DIR_3_0 0 3 RESERVED_15_4 4 15 ixDPCSSYS_CR3_LANE1_DIG_ANA_RX_CTL_OVRD_OUT 2 0x11a9 9 0 4294967295 RESERVED 0 0 RX_ANA_DATA_RATE 1 2 RX_ANA_WORD_CLK_EN 3 3 RX_ANA_DIV4_EN 4 4 RX_ANA_DFE_TAPS_EN 5 5 RX_ANA_ADAPTATION_EN 6 6 RX_LBK_CLK_EN 7 7 RX_CTL_OVRD_EN 8 8 RESERVED_15_9 9 15 ixDPCSSYS_CR3_LANE1_DIG_ANA_RX_PWR_OVRD_OUT 2 0x11aa 9 0 4294967295 RX_ANA_AFE_EN 0 0 RX_ANA_CLK_VREG_EN 1 1 RX_ANA_CLK_DCC_EN 2 2 RX_ANA_CLK_EN 3 3 RX_ANA_CDR_EN 4 4 RX_ANA_DESERIAL_EN 5 5 RX_PWR_OVRD_EN 6 6 RX_ANA_FAST_START 7 7 RESERVED_15_8 8 15 ixDPCSSYS_CR3_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0 2 0x11ab 7 0 4294967295 RX_ANA_CDR_VCO_EN 0 0 RX_ANA_CDR_STARTUP 1 1 RX_VCO_CDR_OVRD_EN 2 2 RX_ANA_CDR_FREQ_TUNE 3 12 RX_ANA_VCO_CNTR_EN 13 13 RX_ANA_VCO_CNTR_CLK 14 14 RX_CDR_FREQ_TUNE_OVRD_EN 15 15 ixDPCSSYS_CR3_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_1 2 0x11ac 3 0 4294967295 RX_ANA_CDR_VCO_LOWFREQ 0 0 RX_ANA_VCO_CNTR_PD 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR3_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_2 2 0x11ad 3 0 4294967295 RX_ANA_CDR_FREQ_TUNE_CLK 0 0 CDR_FREQ_TUNE_CLK_SELF_CLEAR_DISABLE 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR3_LANE1_DIG_ANA_RX_CAL 2 0x11ae 7 0 4294967295 RX_ANA_CAL_MUXA_SEL 0 4 RX_ANA_CAL_MUXB_SEL 5 9 RX_ANA_CAL_LPFBYP_EN 10 10 RESERVED 11 11 RX_ANA_SLICER_CAL_EN 12 12 RX_ANA_CAL_MODE 13 14 RX_ANA_CAL_COMP_EN 15 15 ixDPCSSYS_CR3_LANE1_DIG_ANA_RX_DAC_CTRL 2 0x11af 2 0 4294967295 RX_ANA_CAL_DAC_CTRL 0 7 RESERVED_15_8 8 15 ixDPCSSYS_CR3_LANE1_DIG_ANA_RX_DAC_CTRL_OVRD 2 0x11b0 2 0 4294967295 RX_CAL_DAC_CTRL_OVRD 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR3_LANE1_DIG_ANA_RX_DAC_CTRL_SEL 2 0x11b1 2 0 4294967295 RX_ANA_CAL_DAC_CTRL_SEL 0 4 RESERVED_15_5 5 15 ixDPCSSYS_CR3_LANE1_DIG_ANA_RX_AFE_ATT_VGA 2 0x11b2 5 0 4294967295 RX_ANA_AFE_ATT_LVL 0 2 RX_ANA_AFE_GAIN 3 6 RESERVED 7 10 RX_AFE_OVRD_EN 11 11 RESERVED_15_12 12 15 ixDPCSSYS_CR3_LANE1_DIG_ANA_RX_AFE_CTLE 2 0x11b3 3 0 4294967295 RESERVED 0 2 RX_ANA_AFE_CTLE_BOOST 3 7 RESERVED_15_8 8 15 ixDPCSSYS_CR3_LANE1_DIG_ANA_RX_SCOPE 2 0x11b4 7 0 4294967295 RX_ANA_SCOPE_EN 0 0 RX_ANA_SCOPE_SEL 1 2 RX_ANA_SCOPE_PH_CLK 3 3 RX_ANA_SCOPE_PHASE 4 11 RX_ANA_SCOPE_CLK_EN 12 12 RX_SCOPE_SELF_CLEAR_DISABLE 13 13 RESERVED_15_14 14 15 ixDPCSSYS_CR3_LANE1_DIG_ANA_RX_SLICER_CTRL 2 0x11b5 4 0 4294967295 RX_ANA_SLICER_CTRL_E 0 3 RX_ANA_SLICER_CTRL_O 4 7 RX_ANA_SLICER_CTRL_OVRD_EN 8 8 RESERVED_15_9 9 15 ixDPCSSYS_CR3_LANE1_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST 2 0x11b6 2 0 4294967295 RX_ANA_IQ_PHASE_ADJUST 0 6 RESERVED_15_7 7 15 ixDPCSSYS_CR3_LANE1_DIG_ANA_RX_ANA_IQ_SENSE_EN 2 0x11b7 2 0 4294967295 RX_ANA_IQ_SENSE_EN 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR3_LANE1_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN 2 0x11b8 3 0 4294967295 RX_ANA_CAL_DAC_CTRL_EN 0 0 DAC_CTRL_SELF_CLEAR_DISABLE 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR3_LANE1_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE 2 0x11b9 3 0 4294967295 RX_ANA_AFE_UPDATE_EN 0 0 AFE_UPDATE_SELF_CLEAR_DISABLE 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR3_LANE1_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK 2 0x11ba 3 0 4294967295 RX_ANA_IQ_PHASE_ADJUST_CLK 0 0 PHASE_ADJUST_SELF_CLEAR_DISABLE 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR3_LANE1_DIG_ANA_STATUS_0 2 0x11bb 9 0 4294967295 TX_ANA_CLK_SHIFT_ACK 0 0 TX_ANA_RXDETP_RESULT 1 1 TX_ANA_RXDETM_RESULT 2 2 TX_ANA_LOOPBACK_EN 3 3 TX_ANA_CLK_LB_EN 4 4 RX_ANA_CAL_RESULT 5 5 RX_ANA_SCOPE_DATA 6 6 TX_ANA_DCC_CAL_RESULT 7 7 TX_ANA_CTRL_EQ_MUX 8 15 ixDPCSSYS_CR3_LANE1_DIG_ANA_STATUS_1 2 0x11bc 2 0 4294967295 RX_ANA_VCO_CNTR 0 12 RESERVED_15_13 13 15 ixDPCSSYS_CR3_LANE1_DIG_ANA_RX_TERM_CODE_OVRD_OUT 2 0x11bd 3 0 4294967295 RX_TERM_CODE 0 5 RX_TERM_OVRD_EN 6 6 RESERVED_15_7 7 15 ixDPCSSYS_CR3_LANE1_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT 2 0x11be 3 0 4294967295 RX_TERM_CLK 0 0 RX_TERM_CLK_SELF_CLEAR_DISABLE 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR3_LANE1_DIG_ANA_MPHY_OVRD_OUT 2 0x11bf 9 0 4294967295 RX_ANA_SQ_CTRL_TRESH 0 2 RX_ANA_SQ_CTRL_TRESH_OVRD_EN 3 3 RX_ANA_SQ_CTRL_RESP 4 5 RX_ANA_SQ_CTRL_RESP_OVRD_EN 6 6 RX_ANA_PWM_EN 7 7 RX_ANA_PWM_EN_OVRD_EN 8 8 RX_ANA_PWM_CLK_SEL 9 10 RX_ANA_PWM_CLK_SEL_OVRD_EN 11 11 RESERVED_15_12 12 15 ixDPCSSYS_CR3_LANE1_DIG_ANA_SIGDET_OVRD_OUT_1 2 0x11c0 7 0 4294967295 RX_ANA_SIGDET_HF_THRESH 0 2 RX_ANA_SIGDET_HF_THRESH_OVRD_EN 3 3 RX_ANA_SIGDET_HF_CAL_TUNE 4 9 RX_ANA_SIGDET_CAL_TUNE_OVRD_EN 10 10 RX_ANA_SIGDET_CAL_EN 11 11 RX_ANA_SIGDET_CAL_EN_OVRD_EN 12 12 RESERVED_15_13 13 15 ixDPCSSYS_CR3_LANE1_DIG_ANA_SIGDET_OVRD_OUT_2 2 0x11c1 7 0 4294967295 RX_ANA_SIGDET_LF_THRESH 0 2 RX_ANA_SIGDET_LF_THRESH_OVRD_EN 3 3 RX_ANA_SIGDET_LF_FILTER_EN 4 4 RX_ANA_SIGDET_LF_FILTER_EN_OVRD_EN 5 5 RX_ANA_SIGDET_CAL_TUNE 6 11 RX_ANA_SIGDET_CAL_TUNE_OVRD_EN 12 12 RESERVED_15_13 13 15 ixDPCSSYS_CR3_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT 2 0x11c2 8 0 4294967295 TX_ANA_DCC_CAL_RANGE 0 1 TX_ANA_DCC_CAL_RANGE_OVRD_EN 2 2 TX_ANA_DCC_CAL_COMP_EN 3 3 TX_ANA_DCC_CAL_COMP_EN_OVRD_EN 4 4 TX_ANA_DCC_CAL_CTRL 5 12 TX_ANA_DCC_CAL_CTRL_OVRD_EN 13 13 TX_ANA_DCC_CAL_CTRL_EN 14 14 TX_ANA_DCC_CAL_CTRL_EN_OVRD_EN 15 15 ixDPCSSYS_CR3_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2 2 0x11c3 5 0 4294967295 TX_ANA_DCC_CAL_CTRL_SEL 0 2 TX_ANA_DCC_CAL_CTRL_SEL_OVRD_EN 3 3 TX_ANA_DCC_CLK_COMP 4 4 TX_ANA_DCC_CLK_COMP_OVRD_EN 5 5 RESERVED_15_6 6 15 ixDPCSSYS_CR3_LANE1_DIG_ANA_TX_OVRD_OUT_2 2 0x11c4 6 0 4294967295 TX_ANA_FAST_START 0 0 TX_ANA_FAST_START_OVRD_EN 1 1 TX_CLK_LB_EN 2 2 TX_CLK_LB_EN_OVRD_EN 3 3 TX_ACJTAG_EN 4 4 RESERVED_15_5 5 15 ixDPCSSYS_CR3_LANE1_ANA_TX_OVRD_MEAS 2 0x11e0 9 0 4294967295 OVRD_CLK_SHIFT 0 0 CLK_SHIFT_REG 0 0 MEAS_ATB_CAL_MUX 0 0 MEAS_ATB_CAL_COMP 0 0 OVRD_VCM_HOLD 0 0 VCM_HOLD_REG 0 0 PULL_UP_REG 0 0 PULL_DN_REG 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR3_LANE1_ANA_TX_PWR_OVRD 2 0x11e1 9 0 4294967295 OVRD_TX_LOOPBACK 0 0 LOOPBACK_EN_REG 0 0 REFGEN_EN_REG 0 0 CLK_DIV_EN_REG 0 0 DATA_EN_REG_INT 0 0 CLK_EN_REG 0 0 SERIAL_EN_REG 0 0 OVRD_EN 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR3_LANE1_ANA_TX_ALT_BUS 2 0x11e2 6 0 4294967295 DRV_SOURCE_REG 0 0 OVRD_ALT_BUS 0 0 ATB_S_ENABLE 0 0 TX_ALT_RINGO 0 0 JTAG_DATA_REG 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR3_LANE1_ANA_TX_ATB1 2 0x11e3 9 0 4294967295 MEAS_ATB_GD 0 0 MEAS_ATB_VDDH 0 0 OVERRIDE_RXDETREF 0 0 MEAS_ATB_VPTX 0 0 OVERRIDE_REGREF 0 0 MEAS_ATB_VREG_DRV 0 0 MEAS_ATB_VREG 0 0 MEAS_ATB_VPH_HALF 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR3_LANE1_ANA_TX_ATB2 2 0x11e4 9 0 4294967295 MEAS_ATB_VCM 0 0 MEAS_ATB_CAL_VDAC_CM 0 0 MEAS_ATB_CAL_VDAC_DIFF 0 0 MEAS_ATB_TXM 0 0 MEAS_ATB_TXP 0 0 MEAS_ATB_RXDETREF 0 0 LFPS_HIGH_PRIORITY 0 0 OSC_DIV4_EN 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR3_LANE1_ANA_TX_DCC_DAC 2 0x11e5 2 0 4294967295 DCC_DAC_REG 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR3_LANE1_ANA_TX_DCC_CTRL1 2 0x11e6 7 0 4294967295 NC0 0 0 OVRD_DCC_DAC_CTRL_SEL 0 0 DCC_DAC_CTRL_SEL_REG 0 0 OVRD_DCC_DAC_CTRL_EN 0 0 DCC_DAC_CTRL_EN_REG 0 0 OVRD_DCC_DAC_REG 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR3_LANE1_ANA_TX_TERM_CODE 2 0x11e7 2 0 4294967295 TERM_CODE_REG_70 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR3_LANE1_ANA_TX_TERM_CODE_CTRL 2 0x11e8 8 0 4294967295 VREG_BOOST_1 0 0 OVRD_UPDATE_TERM 0 0 UPDATE_TERM_REG 0 0 OVRD_RESET_TERM 0 0 RESET_TERM_REG 0 0 OVRD_TERM_CODE 0 0 TERM_CODE_REG_98 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR3_LANE1_ANA_TX_OVRD_CLK 2 0x11e9 9 0 4294967295 VREG_BOOST_0 0 0 CLK_LB_EN_REG 0 0 OVRD_LB_EN 0 0 MPLLB_CLK_EN_REG 0 0 MPLLA_CLK_EN_REG 0 0 OVRD_MPLLAB_EN 0 0 WORD_CLK_EN_REG 0 0 OVRD_WORD_CLK_EN 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR3_LANE1_ANA_TX_MISC1 2 0x11ea 8 0 4294967295 MEAS_ATB_CAL_CLK_ALIGN 0 0 OVRD_DCC_DAC_CTRL_RANGE 0 0 DCC_DAC_CTRL_RANGE_REG 0 0 OVRD_VREF_SEL 0 0 VREF_SEL_REG 0 0 FORCE_ATB_TXM 0 0 FORCE_ATB_TXP 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR3_LANE1_ANA_TX_MISC2 2 0x11eb 8 0 4294967295 TX_PEAKING_LVL 0 0 VREG_CP_GAIN_CTRL 0 0 TX_SLEW_EN 0 0 EN_INV_POST 0 0 EN_INV_PRE 0 0 TX_VREG_EN_BYP 0 0 TX_VDRIVER_PULLDN_EN 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR3_LANE1_ANA_TX_MISC3 2 0x11ec 4 0 4294967295 TX_VREG_OVRD_RING_CTRL 0 0 TX_DCC_LOWV 0 0 NC7_2 2 7 RESERVED_15_8 8 15 ixDPCSSYS_CR3_LANE1_ANA_TX_RESERVED2 2 0x11ed 2 0 4294967295 NC7_0 0 7 RESERVED_15_8 8 15 ixDPCSSYS_CR3_LANE1_ANA_TX_RESERVED3 2 0x11ee 2 0 4294967295 NC7_0 0 7 RESERVED_15_8 8 15 ixDPCSSYS_CR3_LANE1_ANA_TX_RESERVED4 2 0x11ef 2 0 4294967295 NC7_0 0 7 RESERVED_15_8 8 15 ixDPCSSYS_CR3_LANE1_ANA_RX_CLK_1 2 0x11f0 8 0 4294967295 CDR_VCO_STARTUP_CODE 0 0 CDR_VCO_TEMP_COMP_EN 0 0 CDR_VCO_USE_UNCAL_BIAS 0 0 OVERRIDE_CDR_EN 0 0 OVRD_CLK_EN 0 0 CLK_EN_REG 0 0 NC7 7 7 RESERVED_15_8 8 15 ixDPCSSYS_CR3_LANE1_ANA_RX_CLK_2 2 0x11f1 5 0 4294967295 IQ_PHASE_ADJUST_REG 0 0 OVRD_IQ_PHASE_ADJUST 0 0 RX_LOOPBACK_CLK_REG 0 0 OVRD_RX_LOOPBACK_CLK 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR3_LANE1_ANA_RX_CDR_DES 2 0x11f2 7 0 4294967295 OVRD_WORD_CLK_EN 0 0 WORD_CLK_EN_REG 0 0 PHDET_ODD_REG 0 0 PHDET_EVEN_REG 0 0 SIGDET_VREF_EXT_EN 0 0 NC7_5 5 7 RESERVED_15_8 8 15 ixDPCSSYS_CR3_LANE1_ANA_RX_SLC_CTRL 2 0x11f3 3 0 4294967295 RX_SLICER_CTRL_O_REG 0 0 RX_SLICER_CTRL_E_REG 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR3_LANE1_ANA_RX_PWR_CTRL1 2 0x11f4 8 0 4294967295 OVRD_ACJT_EN 0 0 ACJT_EN_REG 0 0 OVRD_AFE_EN 0 0 AFE_EN_REG 0 0 AFE_CM_SEL 0 0 ATT_PULLDN_EN 0 0 NC7_7 7 7 RESERVED_15_8 8 15 ixDPCSSYS_CR3_LANE1_ANA_RX_PWR_CTRL2 2 0x11f5 9 0 4294967295 OVRD_DFE_EN 0 0 DFE_EN_REG 0 0 OVRD_DESERIAL_EN 0 0 DESERIAL_EN_REG 0 0 OVRD_LOOPBACK_EN 0 0 LOOPBACK_EN_REG 0 0 OVRD_FAST_START 0 0 FAST_START_REG 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR3_LANE1_ANA_RX_SQ 2 0x11f6 7 0 4294967295 SQ_CTRL_RESP_REG 0 0 OVRD_SQ_CTRL_RESP 0 0 NC4_3 3 4 SQ_CTRL_TRESH_REG 0 0 OVRD_SQ_CTRL_TRESH 0 0 AFE_LOOPBACK_SEL 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR3_LANE1_ANA_RX_CAL1 2 0x11f7 5 0 4294967295 DFE_TAPS_EN_REG 0 0 OVRD_DFE_TAPS_EN 0 0 CAL_MUXB_SEL_REG 0 0 OVRD_CAL_MUXB_SEL 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR3_LANE1_ANA_RX_CAL2 2 0x11f8 5 0 4294967295 AFE_PD_EQ_OFFSET 0 0 CAL_IDACS_USE_UNCAL 0 0 CAL_MUXA_SEL_REG 0 0 OVRD_CAL_MUXA_SEL 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR3_LANE1_ANA_RX_ATB_REGREF 2 0x11f9 8 0 4294967295 OVERRIDE_REGREF_VCO 0 0 OVERRIDE_REGREF_CLK 0 0 OVERRIDE_REGREF_IQC 0 0 BOOST_REGREF_IQC 0 0 OVRD_RX_SLICER_CTRL 0 0 OVRD_RX_TERM_AC_DCZ 0 0 RX_TERM_AC_DCZ_REG 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR3_LANE1_ANA_RX_ATB_MEAS1 2 0x11fa 9 0 4294967295 MASTER_ATB_EN 0 0 MEAS_ATB_VP 0 0 MEAS_ATB_GD 0 0 MEAS_ATB_VREG_VCO 0 0 MEAS_ATB_VREG_CLK 0 0 MEAS_ATB_VREG_IQC 0 0 REGS_FB_DIV_CTRL 0 0 RX_VREG_CLK_BYPASS 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR3_LANE1_ANA_RX_ATB_MEAS2 2 0x11fb 2 0 4294967295 MEAS_ATB_RX 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR3_LANE1_ANA_RX_ATB_MEAS3 2 0x11fc 7 0 4294967295 MEAS_ATB_CDR_VCO_GD 0 0 MEAS_ATB_CDR_VCO_VIREF_200U 0 0 MEAS_ATB_VIBIAS_CDR_VCO 0 0 MEAS_ATB_CDR_VCO_VOSC 0 0 MEAS_ATB_CAL_MUX 0 0 RX_VREG_OVERRIDE_RING_CTRL 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR3_LANE1_ANA_RX_ATB_MEAS4 2 0x11fd 3 0 4294967295 MEAS_ATB_CAL_VREF 0 0 NC7 7 7 RESERVED_15_8 8 15 ixDPCSSYS_CR3_LANE1_ANA_RX_ATB_FRC 2 0x11fe 2 0 4294967295 FRC_ATB_CAL_VREF 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR3_LANE1_ANA_RX_RESERVED1 2 0x11ff 2 0 4294967295 NC7_0 0 7 RESERVED_15_8 8 15 ixDPCSSYS_CR3_LANE2_DIG_ASIC_LANE_OVRD_IN 2 0x1200 5 0 4294967295 LANE_TX2RX_SER_LB 0 0 LANE_RX2TX_PAR_LB 1 1 EN 2 2 RX_ACJTAG_EN 3 3 RESERVED_15_4 4 15 ixDPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_0 2 0x1201 12 0 4294967295 REQ 0 0 REQ_OVRD_EN 1 1 PSTATE 2 3 PSTATE_OVRD_EN 4 4 RATE 5 7 RATE_OVRD_EN 8 8 WIDTH 9 10 WIDTH_OVRD_EN 11 11 MPLLB_SEL 12 12 MPLLB_SEL_OVRD_EN 13 13 DATA_EN 14 14 DATA_EN_OVRD_EN 15 15 ixDPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_1 2 0x1202 11 0 4294967295 NYQUIST_DATA 0 0 DISABLE 1 1 BEACON_EN 2 2 EN 3 3 TX_MAIN_CURSOR 4 9 MAIN_OVRD_EN 10 10 ASYNC_DRV_EN 11 11 ASYNC_DRV_OVRD_EN 12 12 TX_VREGDRV_BYP_OVRD 13 13 TX_VREGDRV_BYP_OVRD_EN 14 14 RESERVED_15_15 15 15 ixDPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_2 2 0x1203 6 0 4294967295 TX_PRE_CURSOR 0 5 PRE_OVRD_EN 6 6 TX_POST_CURSOR 7 12 POST_OVRD_EN 13 13 HDMIMODE_EN 14 14 HDMIMODE_ENABLE_OVRD_EN 15 15 ixDPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_3 2 0x1204 15 0 4294967295 CLK_RDY 0 0 CLK_RDY_OVRD_EN 1 1 DETECT_RX_REQ 2 2 DETECT_RX_REQ_OVRD_EN 3 3 INVERT 4 4 INVERT_OVRD_EN 5 5 LPD 6 6 LPD_OVRD_EN 7 7 TX_DC_COUP_EN 8 8 TX_DC_COUP_EN_OVRD_EN 9 9 PMA_EXTENDED_FIFO_EN 10 10 PMA_EXTENDED_FIFO_EN_OVRD_EN 11 11 TX_MPHY_MODE_EN 12 12 TX_MPHY_MODE_EN_OVRD_EN 13 13 RESERVED_15_14 14 15 ixDPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_4 2 0x1205 3 0 4294967295 RESET 0 0 RESET_OVRD_EN 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_OUT 2 0x1206 5 0 4294967295 TX_ACK 0 0 EN_TX_ACK 1 1 DETRX_RESULT 2 2 EN_DETRX_RESULT 3 3 RESERVED_15_4 4 15 ixDPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_0 2 0x1207 11 0 4294967295 REQ 0 0 REQ_OVRD_EN 1 1 DATA_EN 2 2 DATA_EN_OVRD_EN 3 3 PSTATE 4 5 PSTATE_OVRD_EN 6 6 RATE 7 8 RATE_OVRD_EN 9 9 WIDTH 10 11 WIDTH_OVRD_EN 12 12 RESERVED_15_13 13 15 ixDPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_1 2 0x1208 5 0 4294967295 RX_REF_LD_VAL_5_0 0 5 RX_CDR_VCO_LOWFREQ 6 6 EN 7 7 RX_REF_LD_VAL_6 8 8 RESERVED_15_9 9 15 ixDPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_2 2 0x1209 3 0 4294967295 RX_VCO_LD_VAL 0 12 EN 13 13 RESERVED_15_14 14 15 ixDPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_3 2 0x120a 11 0 4294967295 CDR_TRACK_EN 0 0 CDR_TRACK_EN_OVRD_EN 1 1 CDR_SSC_EN 2 2 CDR_SSC_EN_OVRD_EN 3 3 ALIGN_EN 4 4 ALIGN_EN_OVRD_EN 5 5 CLK_SHIFT 6 6 CLK_SHIFT_OVRD_EN 7 7 DISABLE 8 8 DISABLE_OVRD_EN 9 9 RESERVED_15_10 10 15 ixDPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_4 2 0x120b 11 0 4294967295 LPD 0 0 LPD_OVRD_EN 1 1 INVERT 2 2 INVERT_OVRD_EN 3 3 ADAPT_AFE_EN 4 4 ADAPT_DFE_EN 5 5 ADPT_OVRD_EN 6 6 TERM_EN 7 7 TERM_ACDC 8 8 TERM_OVRD_EN 9 9 RESERVED_15_10 10 15 ixDPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_5 2 0x120c 3 0 4294967295 RESET 0 0 RESET_OVRD_EN 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0 2 0x120d 4 0 4294967295 EQ_ATT_LVL 0 2 EQ_AFE_GAIN 3 6 RESERVED 7 10 EQ_CTLE_BOOST 11 15 ixDPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1 2 0x120e 3 0 4294967295 EQ_DFE_TAP2 0 6 EQ_DFE_TAP1 7 14 EQ_OVRD_EN 15 15 ixDPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_OUT_0 2 0x120f 9 0 4294967295 ACK 0 0 ACK_OVRD_EN 1 1 ADAPT_STS 2 3 ADAPT_STS_OVRD_EN 4 4 RX_ASYNC_DATA 5 5 RX_ASYNC_DATA_OVRD_EN 6 6 RX_SQ_WEAKKEEP_OUT 7 7 RX_SQ_WEAKKEEP_OUT_OVRD_EN 8 8 RESERVED_15_9 9 15 ixDPCSSYS_CR3_LANE2_DIG_ASIC_LANE_ASIC_IN 2 0x1210 3 0 4294967295 LANE_TX2RX_SER_LB 0 0 LANE_RX2TX_PAR_LB 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR3_LANE2_DIG_ASIC_TX_ASIC_IN_0 2 0x1211 12 0 4294967295 CLK_RDY 0 0 RESET 1 1 INVERT 2 2 DATA_EN 3 3 REQ 4 4 LPD 5 5 PSTATE 6 7 RATE 8 10 WIDTH 11 12 MPLLB_SEL 13 13 DETECT_RX_REQ 14 14 DISABLE 15 15 ixDPCSSYS_CR3_LANE2_DIG_ASIC_TX_ASIC_IN_1 2 0x1212 7 0 4294967295 BEACON_EN 0 0 TX_MAIN_CURSOR 1 6 TX_ASYNC_EN 7 7 TX_ASYNC_DATA 8 8 TX_ASYNC_DRV_EN 9 9 TX_VREGDRV_BYP 10 10 RESERVED_15_11 11 15 ixDPCSSYS_CR3_LANE2_DIG_ASIC_TX_ASIC_IN_2 2 0x1213 3 0 4294967295 TX_PRE_CURSOR 0 5 TX_POST_CURSOR 6 11 RESERVED_15_12 12 15 ixDPCSSYS_CR3_LANE2_DIG_ASIC_TX_ASIC_OUT 2 0x1214 3 0 4294967295 TX_ACK 0 0 DETRX_RESULT 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR3_LANE2_DIG_ASIC_RX_ASIC_IN_0 2 0x1215 13 0 4294967295 RESET 0 0 INVERT 1 1 DATA_EN 2 2 REQ 3 3 LPD 4 4 PSTATE 5 6 RATE 7 8 WIDTH 9 10 RESERVED 11 11 ADAPT_AFE_EN 12 12 ADAPT_DFE_EN 13 13 CDR_TRACK_EN 14 14 RESERVED_15_15 15 15 ixDPCSSYS_CR3_LANE2_DIG_ASIC_RX_ASIC_IN_1 2 0x1216 7 0 4294967295 CDR_SSC_EN 0 0 ALIGN_EN 1 1 CLK_SHIFT 2 2 DISABLE 3 3 RX_TERM_EN 4 4 RX_TERM_ACDC 5 5 RESERVED_15_6 6 15 ixDPCSSYS_CR3_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0 2 0x1217 4 0 4294967295 EQ_ATT_LVL 0 2 EQ_AFE_GAIN 3 6 RESERVED 7 10 EQ_CTLE_BOOST 11 15 ixDPCSSYS_CR3_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_1 2 0x1218 3 0 4294967295 EQ_DFE_TAP2 0 6 EQ_DFE_TAP1 7 14 RESERVED_15_15 15 15 ixDPCSSYS_CR3_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0 2 0x1219 3 0 4294967295 RX_CDR_VCO_LOWFREQ 0 0 RX_REF_LD_VAL 1 7 RESERVED_15_8 8 15 ixDPCSSYS_CR3_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1 2 0x121a 2 0 4294967295 RX_VCO_LD_VAL 0 12 RESERVED_15_13 13 15 ixDPCSSYS_CR3_LANE2_DIG_ASIC_RX_ASIC_OUT_0 2 0x121b 4 0 4294967295 ACK 0 0 VALID 1 1 ADAPT_STS 2 3 RESERVED_15_4 4 15 ixDPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_6 2 0x121c 10 0 4294967295 RX_PWM_CLK_SEL 0 1 RX_PWM_CLK_SEL_OVRD_EN 2 2 RX_TERM_LCC_ON 3 3 RX_TERM_LS_ON 4 4 RX_TERM_LS_LCC_ON_OVRD_EN 5 5 RX_TERM_CTL 6 7 RX_TERM_CTL_OVRD_EN 8 8 RX_PWM_EN 9 9 RX_PWM_EN_OVRD_EN 10 10 RESERVED_15_11 11 15 ixDPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_5 2 0x121d 15 0 4294967295 RPTR_EN_MASTER_LANE 0 0 RPTR_EN_MASTER_LANE_OVRD_EN 1 1 DIG_CLK_EN_OTHER_LANE 2 2 DIG_CLK_EN_OTHER_LANE_OVRD_EN 3 3 DIG_CLK_STATE_MASTER_LANE 4 4 DIG_CLK_STATE_MASTER_LANE_OVRD_EN 5 5 SHIFT_MASTER_LANE 6 6 SHIFT_MASTER_LANE_ORVD_EN 7 7 SHIFT_ACK_OTHER_LANE 8 8 SHIFT_ACK_OTHER_LANE_OVRD_EN 9 9 LANE_MASTER 10 10 LANE_MASTER_OVRD_IN_EN 11 11 TX_DWORD_CLK_SYNC_OVRD 12 12 TX_DWORD_CLK_SYNC_OVRD_EN 13 13 RESERVED_15_14 14 15 ixDPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_OUT_1 2 0x121e 11 0 4294967295 RPTR_EN_OUT 0 0 RPTR_EN_OUT_OVRD_EN 1 1 DIG_CLK_EN_OUT 2 2 DIG_CLK_EN_OUT_OVRD_EN 3 3 DIG_CLK_STATE_OUT 4 4 DIG_CLK_STATE_OUT_OVRD_EN 5 5 SHIFT_OUT 6 6 SHIFT_OUT_OVRD_EN 7 7 SHIFT_ACK_OUT 8 8 SHIFT_ACK_OUT_OVRD_EN 9 9 RESERVED_15_10 10 15 ixDPCSSYS_CR3_LANE2_DIG_ASIC_OCLA 2 0x121f 3 0 4294967295 RX_DWORD_OCLA_CLK_EN 0 0 RX_DWORD_OCLA_DATA_EN 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0 2 0x1220 11 0 4294967295 TX_P0_ANA_REFGEN_EN 0 0 TX_P0_ANA_VCM_HOLD 1 1 TX_P0_ANA_CLK_EN 2 2 TX_P0_ANA_WORD_CLK_EN 3 3 TX_P0_ANA_RESET 4 4 TX_P0_ANA_SERIAL_EN 5 5 TX_P0_DIG_CLK_EN 6 6 TX_P0_DATA_EN 7 7 TX_P0_ALLOW_RXDET 8 8 TX_P0_ANA_DCC_COMP_CAL_EN 9 9 RESERVED_15_10 10 15 ixDPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S 2 0x1221 11 0 4294967295 TX_P0S_ANA_REFGEN_EN 0 0 TX_P0S_ANA_VCM_HOLD 1 1 TX_P0S_ANA_CLK_EN 2 2 TX_P0S_ANA_WORD_CLK_EN 3 3 TX_P0S_ANA_RESET 4 4 TX_P0S_ANA_SERIAL_EN 5 5 TX_P0S_DIG_CLK_EN 6 6 TX_P0S_DATA_EN 7 7 TX_P0S_ALLOW_RXDET 8 8 TX_P0S_ANA_DCC_COMP_CAL_EN 9 9 RESERVED_15_10 10 15 ixDPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1 2 0x1222 11 0 4294967295 TX_P1_ANA_REFGEN_EN 0 0 TX_P1_ANA_VCM_HOLD 1 1 TX_P1_ANA_CLK_EN 2 2 TX_P1_ANA_WORD_CLK_EN 3 3 TX_P1_ANA_RESET 4 4 TX_P1_ANA_SERIAL_EN 5 5 TX_P1_DIG_CLK_EN 6 6 TX_P1_DATA_EN 7 7 TX_P1_ALLOW_RXDET 8 8 TX_P1_ANA_DCC_COMP_CAL_EN 9 9 RESERVED_15_10 10 15 ixDPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2 2 0x1223 12 0 4294967295 TX_P2_ANA_REFGEN_EN 0 0 TX_P2_ANA_VCM_HOLD 1 1 TX_P2_ANA_CLK_EN 2 2 TX_P2_ANA_WORD_CLK_EN 3 3 TX_P2_ANA_RESET 4 4 TX_P2_ANA_SERIAL_EN 5 5 TX_P2_DIG_CLK_EN 6 6 TX_P2_DATA_EN 7 7 TX_P2_ALLOW_RXDET 8 8 TX_P2_ALLOW_VBOOST 9 9 TX_P2_ANA_DCC_COMP_CAL_EN 10 10 RESERVED_15_11 11 15 ixDPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_0 2 0x1224 2 0 4294967295 TX_REFGEN_EN_TIME 0 7 TX_CLK_EN 8 15 ixDPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_1 2 0x1225 2 0 4294967295 TX_VCM_HOLD_TIME_14_0 0 14 SKIP_TX_VCM_HOLD_WAIT 15 15 ixDPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_2 2 0x1226 2 0 4294967295 TX_VBOOST_DIS_TIME_12_0 0 12 DTB_SEL 13 15 ixDPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_3 2 0x1227 3 0 4294967295 TX_VCM_HOLD_TIME_17_15 0 2 TX_VBOOST_DIS_TIME_13 3 3 RESERVED_15_4 4 15 ixDPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_4 2 0x1228 2 0 4294967295 TX_VCM_HOLD_GS_TIME 0 14 SKIP_TX_VCM_HOLD_GS_PULSE 15 15 ixDPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_5 2 0x1229 5 0 4294967295 TX_RXDET_TIME 0 9 FAST_TX_RXDET 10 10 TX_RESET_TIME 11 12 TX_SERIAL_EN_TIME 13 14 RESERVED_15_15 15 15 ixDPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_DCC_CR_BANK_ADDR 2 0x122a 1 0 4294967295 ADDR 0 15 ixDPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_DCC_CR_BANK_DATA 2 0x122b 1 0 4294967295 DATA 0 15 ixDPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_DCC_DAC_CTRL 2 0x122c 2 0 4294967295 CTRL 0 7 RESERVED_15_8 8 15 ixDPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_DCC_DAC_RANGE 2 0x122d 2 0 4294967295 CTRL 0 1 RESERVED_15_2 2 15 ixDPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_DCC_DAC_SEL 2 0x122e 6 0 4294967295 SEL 0 2 REQ 3 3 CTRL_UPD 4 4 RANGE_UPD 5 5 BIN_HOT 6 6 RESERVED_15_7 7 15 ixDPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_DCC_DAC_ACK 2 0x122f 2 0 4294967295 ACK 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_DCC_DAC_ADDR 2 0x1230 1 0 4294967295 ADDR 0 15 ixDPCSSYS_CR3_LANE2_DIG_TX_CLK_ALIGN_TX_CTL_0 2 0x1231 4 0 4294967295 TX_NUM_2UI_SHIFTS_16B_MODE 0 3 TX_NUM_2UI_SHIFTS_20B_MODE 4 7 TX_FIFO_BYPASS 8 8 RESERVED_15_9 9 15 ixDPCSSYS_CR3_LANE2_DIG_TX_LBERT_CTL 2 0x1232 4 0 4294967295 MODE 0 3 TRIGGER_ERR 4 4 PAT0 5 14 RESERVED_15_15 15 15 ixDPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0 2 0x1240 12 0 4294967295 RX_P0_ANA_AFE_EN 0 0 RX_P0_ANA_CLK_VREG_EN 1 1 RESERVED_1 2 2 RX_P0_ANA_CLK_EN 3 3 RESERVED_0 4 4 RX_P0_ANA_DESER_EN 5 5 RX_P0_ANA_CDR_EN 6 6 RX_P0_VCO_FREQ_RST 7 7 RX_P0_VCO_CAL_RST 8 8 RX_P0_VCO_CONTCAL_EN 9 9 RX_P0_DIG_CLK_EN 10 10 RESERVED_15_11 11 15 ixDPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S 2 0x1241 12 0 4294967295 RX_P0S_ANA_AFE_EN 0 0 RX_P0S_ANA_CLK_VREG_EN 1 1 RESERVED_2 2 2 RX_P0S_ANA_CLK_EN 3 3 RESERVED_4 4 4 RX_P0S_ANA_DESER_EN 5 5 RX_P0S_ANA_CDR_EN 6 6 RX_P0S_VCO_FREQ_RST 7 7 RX_P0S_VCO_CAL_RST 8 8 RX_P0S_VCO_CONTCAL_EN 9 9 RX_P0S_DIG_CLK_EN 10 10 RESERVED_15_11 11 15 ixDPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1 2 0x1242 12 0 4294967295 RX_P1_ANA_AFE_EN 0 0 RX_P1_ANA_CLK_VREG_EN 1 1 RESERVED_2 2 2 RX_P1_ANA_CLK_EN 3 3 RESERVED_4 4 4 RX_P1_ANA_DESER_EN 5 5 RX_P1_ANA_CDR_EN 6 6 RX_P1_VCO_FREQ_RST 7 7 RX_P1_VCO_CAL_RST 8 8 RX_P1_VCO_CONTCAL_EN 9 9 RX_P1_DIG_CLK_EN 10 10 RESERVED_15_11 11 15 ixDPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2 2 0x1243 12 0 4294967295 RX_P2_ANA_AFE_EN 0 0 RX_P2_ANA_CLK_VREG_EN 1 1 RESERVED_2 2 2 RX_P2_ANA_CLK_EN 3 3 RESERVED_4 4 4 RX_P2_ANA_DESER_EN 5 5 RX_P2_ANA_CDR_EN 6 6 RX_P2_VCO_FREQ_RST 7 7 RX_P2_VCO_CAL_RST 8 8 RX_P2_VCO_CONTCAL_EN 9 9 RX_P2_DIG_CLK_EN 10 10 RESERVED_15_11 11 15 ixDPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1 2 0x1245 5 0 4294967295 RX_AFE_EN_TIME 0 5 FAST_RX_AFE_EN 6 6 RX_VREG_EN_TIME 7 12 FAST_RX_VREG_EN 13 13 RESERVED_15_14 14 15 ixDPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_2 2 0x1246 4 0 4294967295 RX_CLK_EN_TIME 0 5 FAST_RX_CLK_EN 6 6 RX_FAST_START_TIME 7 10 RESERVED_15_11 11 15 ixDPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_3 2 0x1247 5 0 4294967295 RX_RATE_TIME 0 1 RSVD_3_7_2 2 7 RX_CDR_EN_TIME 8 11 RX_DESER_EN_TIME 12 13 RX_DESER_DIS_TIME 14 15 ixDPCSSYS_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0 2 0x1248 8 0 4294967295 INT_GAIN_CAL_FIXED_CNT 0 4 INT_GAIN_CAL_FIXED_CNT_EN 5 5 INT_GAIN_CAL_CNT_SHIFT 6 8 INT_GAIN_CAL_BOUNCE_CNT 9 11 DISABLE_BIN_HOLD 12 12 DISABLE_INT_GAIN_HOLD 13 13 DISABLE_COARSE_CALDONE 14 14 RESERVED_15_15 15 15 ixDPCSSYS_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1 2 0x1249 7 0 4294967295 RX_VCO_OVRD_SEL 0 0 RX_VCO_FREQ_RST 1 1 RX_VCO_CAL_RST 2 2 RX_VCO_CONTCAL_EN 3 3 DISABLE_INT_CAL_MODE 4 4 DPLL_CAL_UG 5 8 DTB_SEL 9 15 ixDPCSSYS_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2 2 0x124a 4 0 4294967295 FREQ_TUNE_START_VAL 0 9 FREQ_TUNE_CAL_STEPS 10 13 SKIP_RX_VCO_FREQ_TUNE_CAL 14 14 SKIP_RX_VCO_CAL 15 15 ixDPCSSYS_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0 2 0x124b 4 0 4294967295 RX_VCO_STARTUP_TIME 0 6 RX_VCO_UPDATE_TIME 7 10 RX_VCO_CNTR_PWRUP_TIME 11 14 FAST_RX_VCO_WAIT 15 15 ixDPCSSYS_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1 2 0x124c 2 0 4294967295 RX_VCO_CNTR_SETTLE_TIME 0 2 RESERVED_15_3 3 15 ixDPCSSYS_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0 2 0x124d 6 0 4294967295 RX_ANA_CDR_FREQ_TUNE 0 9 RX_ANA_VCO_CNTR_PD 10 10 RX_ANA_VCO_CNTR_EN 11 11 RX_ANA_CDR_STARTUP 12 12 RX_ANA_CDR_VCO_EN 13 13 RESERVED_15_14 14 15 ixDPCSSYS_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1 2 0x124e 7 0 4294967295 RX_VCO_FSM_STATE 0 3 RX_VCO_FREQ_RST 4 4 RX_VCO_CAL_RST 5 5 RX_VCO_CONTCAL_EN 6 6 RX_VCO_CAL_DONE 7 7 DPLL_FREQ_RST 8 8 RESERVED_15_9 9 15 ixDPCSSYS_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_2 2 0x124f 4 0 4294967295 VCO_CNTR_FINAL 0 12 VCOCLK_TOO_FAST 13 13 RX_VCO_CORRECT 14 14 RX_VCO_UP 15 15 ixDPCSSYS_CR3_LANE2_DIG_RX_RX_ALIGN_XAUI_COMM_MASK 2 0x1250 2 0 4294967295 XAUI_COMM_MASK 0 9 RESERVED_15_10 10 15 ixDPCSSYS_CR3_LANE2_DIG_RX_LBERT_CTL 2 0x1251 3 0 4294967295 MODE 0 3 SYNC 4 4 RESERVED_15_5 5 15 ixDPCSSYS_CR3_LANE2_DIG_RX_LBERT_ERR 2 0x1252 2 0 4294967295 COUNT 0 14 OV14 15 15 ixDPCSSYS_CR3_LANE2_DIG_RX_CDR_CDR_CTL_0 2 0x1253 7 0 4294967295 PHDET_EN 0 1 PHDET_EDGE 2 3 PHDET_POL 4 4 PHDET_EN_PR_MODE 5 5 ALWAYS_REALIGN 6 6 DTB_SEL 7 10 RESERVED_15_11 11 15 ixDPCSSYS_CR3_LANE2_DIG_RX_CDR_CDR_CTL_1 2 0x1254 2 0 4294967295 SSC_OFF_CNT0 0 9 SSC_OFF_CNT1 10 15 ixDPCSSYS_CR3_LANE2_DIG_RX_CDR_CDR_CTL_2 2 0x1255 2 0 4294967295 SSC_ON_CNT0 0 8 SSC_ON_CNT1 9 15 ixDPCSSYS_CR3_LANE2_DIG_RX_CDR_CDR_CTL_3 2 0x1256 6 0 4294967295 SSC_OFF_PHUG0 0 2 SSC_OFF_PHUG1 3 5 SSC_OFF_FRUG0 6 8 OVRD_DPLL_GAIN 9 9 PHUG_OVRD_VALUE 10 12 FRUG_OVRD_VALUE 13 15 ixDPCSSYS_CR3_LANE2_DIG_RX_CDR_CDR_CTL_4 2 0x1257 6 0 4294967295 SSC_OFF_FRUG1 0 2 SSC_ON_FRUG0 3 5 SSC_ON_FRUG1 6 8 SSC_ON_PHUG0 9 11 SSC_ON_PHUG1 12 14 RESERVED_15_15 15 15 ixDPCSSYS_CR3_LANE2_DIG_RX_CDR_STAT 2 0x1258 3 0 4294967295 PHUG_VALUE 0 2 FRUG_VALUE 3 5 RESERVED_15_6 6 15 ixDPCSSYS_CR3_LANE2_DIG_RX_DPLL_FREQ 2 0x1259 2 0 4294967295 VAL 0 13 RESERVED_15_14 14 15 ixDPCSSYS_CR3_LANE2_DIG_RX_DPLL_FREQ_BOUND_0 2 0x125a 3 0 4294967295 FREQ_BOUND_EN 0 0 UPPER_FREQ_BOUND 1 10 RESERVED_15_11 11 15 ixDPCSSYS_CR3_LANE2_DIG_RX_DPLL_FREQ_BOUND_1 2 0x125b 2 0 4294967295 LOWER_FREQ_BOUND 0 9 RESERVED_15_10 10 15 ixDPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_0 2 0x1260 4 0 4294967295 N_TOP_ASM1 0 9 N_TGG_ASM1 10 13 START_ASM1 14 14 ADPT_CLK_DIV4_EN 15 15 ixDPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1 2 0x1261 5 0 4294967295 N_WAIT_ASM1 0 6 FAST_AFE_DFE_SETTLE 7 7 CTLE_POLE_OVRD_VAL 8 10 CTLE_POLE_OVRD_EN 11 11 RESERVED_15_12 12 15 ixDPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_2 2 0x1262 3 0 4294967295 TGG_PTTRN_0 0 4 TGG_PTTRN_1 5 9 RESERVED_15_10 10 15 ixDPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3 2 0x1263 8 0 4294967295 CTLE_EN 0 4 VGA_EN 5 5 ATT_EN 6 6 DFE_EN 7 11 EYEHE_EN 12 12 EYEHO_EN 13 13 TGG_EN 14 14 ESL_TWICE_DSL 15 15 ixDPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_4 2 0x1264 4 0 4294967295 CTLE_TH 0 3 VGA_TH 4 7 DFE1_TH 8 11 DFE2_TH 12 15 ixDPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_5 2 0x1265 4 0 4294967295 DFE3_TH 0 3 DFE4_TH 4 7 DFE5_TH 8 11 TH_OFFSET 12 15 ixDPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6 2 0x1266 6 0 4294967295 CTLE_MU 0 2 VGA_MU 3 5 ATT_MU 6 8 VGA_SAT_CNT 9 11 VGA_SAT_CNT_STICKY 12 12 ATT_LOW_TH 13 15 ixDPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_7 2 0x1267 4 0 4294967295 VGA_MIN_SAT 0 4 VGA_LEV_HIGH 5 9 VGA_LEV_LOW 10 14 RESERVED_15_15 15 15 ixDPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8 2 0x1268 6 0 4294967295 DFE1_MU 0 2 DFE2_MU 3 5 DFE3_MU 6 8 DFE4_MU 9 11 DFE5_MU 12 14 RESERVED_15_15 15 15 ixDPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_9 2 0x1269 2 0 4294967295 ERR_SLE_ADPT_INIT 0 7 ERR_SLO_ADPT_INIT 8 15 ixDPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG 2 0x126a 6 0 4294967295 RST_ADPT_ATT 0 0 RST_ADPT_VGA 1 1 RST_ADPT_CTLE_BOOST 2 2 RST_ADPT_CTLE_POLE 3 3 RST_ADPT_TAP1 4 4 RESERVED_15_5 5 15 ixDPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ATT_STATUS 2 0x126b 3 0 4294967295 ATT_ADPT_CODE 0 7 ASM1_DON 8 8 RESERVED_15_9 9 15 ixDPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_VGA_STATUS 2 0x126c 3 0 4294967295 VGA_ADPT_CODE 0 9 ASM1_DONE 10 10 RESERVED_15_11 11 15 ixDPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_CTLE_STATUS 2 0x126d 4 0 4294967295 CTLE_BOOST_ADPT_CODE 0 9 CTLE_POLE_ADPT_CODE 10 12 ASM1_DONE 13 13 RESERVED_15_14 14 15 ixDPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_DFE_TAP1_STATUS 2 0x126e 3 0 4294967295 DFE_TAP1_ADPT_CODE 0 12 ASM1_DONE 13 13 RESERVED_15_14 14 15 ixDPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_DFE_TAP2_STATUS 2 0x126f 3 0 4294967295 DFE_TAP2_ADPT_CODE 0 11 ASM1_DONE 12 12 RESERVED_15_13 13 15 ixDPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_DFE_TAP3_STATUS 2 0x1270 3 0 4294967295 DFE_TAP3_ADPT_CODE 0 11 ASM1_DONE 12 12 RESERVED_15_13 13 15 ixDPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_DFE_TAP4_STATUS 2 0x1271 3 0 4294967295 DFE_TAP4_ADPT_CODE 0 11 ASM1_DONE 12 12 RESERVED_15_13 13 15 ixDPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_DFE_TAP5_STATUS 2 0x1272 3 0 4294967295 DFE_TAP5_ADPT_CODE 0 11 ASM1_DONE 12 12 RESERVED_15_13 13 15 ixDPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_DFE_DATA_EVEN_VDAC_OFST 2 0x1273 2 0 4294967295 DFE_DATA_EVEN_VDAC_OFST 0 7 RESERVED_15_8 8 15 ixDPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_DFE_DATA_ODD_VDAC_OFST 2 0x1274 2 0 4294967295 DFE_DATA_ODD_VDAC_OFST 0 7 RESERVED_15_8 8 15 ixDPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN 2 0x1275 2 0 4294967295 RX_ANA_SLICER_CTRL_E 0 3 RESERVED_15_4 4 15 ixDPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD 2 0x1276 2 0 4294967295 RX_ANA_SLICER_CTRL_O 0 3 RESERVED_15_4 4 15 ixDPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST 2 0x1277 2 0 4294967295 DFE_ERROR_EVEN_VDAC_OFST 0 7 RESERVED_15_8 8 15 ixDPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST 2 0x1278 2 0 4294967295 DFE_ERROR_ODD_VDAC_OFST 0 7 RESERVED_15_8 8 15 ixDPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL 2 0x1279 2 0 4294967295 E_SLO_LVL 0 7 E_SLE_LVL 8 15 ixDPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_RESET 2 0x127a 2 0 4294967295 RESET_ASM1 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1 2 0x127b 4 0 4294967295 DFE_T1_IDAC 0 4 DFE_T2_IDAC 5 9 DCC_START_IDAC 10 14 RESERVED_15_15 15 15 ixDPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2 2 0x127c 3 0 4294967295 DFE_DAT_EVEN_VDAC 0 4 DFE_DAT_ODD_VDAC 5 9 RESERVED_15_10 10 15 ixDPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3 2 0x127d 3 0 4294967295 DFE_ERR_EVEN_VDAC 0 4 DFE_ERR_ODD_VDAC 5 9 RESERVED_15_10 10 15 ixDPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_CR_BANK_ADDR 2 0x127e 1 0 4294967295 ADDR 0 15 ixDPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_CR_BANK_DATA 2 0x127f 1 0 4294967295 DATA 0 15 ixDPCSSYS_CR3_LANE2_DIG_RX_STAT_LD_VAL_1 2 0x1280 2 0 4294967295 SC1_LD_VAL 0 14 SC1_START 15 15 ixDPCSSYS_CR3_LANE2_DIG_RX_STAT_DATA_MSK 2 0x1281 1 0 4294967295 DATA_MSK_15_0 0 15 ixDPCSSYS_CR3_LANE2_DIG_RX_STAT_MATCH_CTL0 2 0x1282 4 0 4294967295 PTTRN_MSK_CR1A_4_0 0 4 PTTRN_CR1A_4_0 5 9 DATA_MSK_19_16 10 13 SCOPE_DLY 14 15 ixDPCSSYS_CR3_LANE2_DIG_RX_STAT_MATCH_CTL1 2 0x1283 5 0 4294967295 PTTRN_CR1B_EN 0 0 PTTRN_MSK_CR1B_4_0 1 5 PTTRN_CR1B_4_0 6 10 PTTRN_CR1A_ADPT_EN 11 11 RESERVED_15_12 12 15 ixDPCSSYS_CR3_LANE2_DIG_RX_STAT_STAT_CTL0 2 0x1284 10 0 4294967295 RESERVED_0 0 0 CORR_SHFT_SEL_VGA 1 1 CORR_SHFT_SEL 2 2 CORR_SRC_SEL 3 4 CORR_MODE_EN 5 5 STAT_SHFT_SEL 6 9 STAT_SRC_SEL 10 12 STAT_RXCLK_SEL 13 13 SC_TIMER_MODE 14 14 SKIP_EN 15 15 ixDPCSSYS_CR3_LANE2_DIG_RX_STAT_STAT_CTL1 2 0x1285 13 0 4294967295 STAT_CNT_0_EN 0 0 STAT_CNT_1_EN 1 1 STAT_CNT_2_EN 2 2 STAT_CNT_3_EN 3 3 STAT_CNT_4_EN 4 4 STAT_CNT_5_EN 5 5 STAT_CNT_6_EN 6 6 RESERVED_8_7 7 8 SC_PAUSE 9 9 STAT_CLK_EN 10 10 DATA_DLY_SEL 11 12 VLD_LOSS_CLR 13 13 VLD_CTL 14 15 ixDPCSSYS_CR3_LANE2_DIG_RX_STAT_SMPL_CNT1 2 0x1286 2 0 4294967295 SMPL_CNT1 0 14 SMPL_CNT1_DONE 15 15 ixDPCSSYS_CR3_LANE2_DIG_RX_STAT_STAT_CNT_0 2 0x1287 2 0 4294967295 STAT_CNT_0 0 14 SMPL_CNT1_DONE 15 15 ixDPCSSYS_CR3_LANE2_DIG_RX_STAT_STAT_CNT_1 2 0x1288 2 0 4294967295 STAT_CNT_1 0 14 SMPL_CNT1_DONE 15 15 ixDPCSSYS_CR3_LANE2_DIG_RX_STAT_STAT_CNT_2 2 0x1289 2 0 4294967295 STAT_CNT_2 0 14 SMPL_CNT1_DONE 15 15 ixDPCSSYS_CR3_LANE2_DIG_RX_STAT_STAT_CNT_3 2 0x128a 2 0 4294967295 STAT_CNT_3 0 14 SMPL_CNT1_DONE 15 15 ixDPCSSYS_CR3_LANE2_DIG_RX_STAT_STAT_CNT_4 2 0x128b 2 0 4294967295 STAT_CNT_4 0 14 SMPL_CNT1_DONE 15 15 ixDPCSSYS_CR3_LANE2_DIG_RX_STAT_STAT_CNT_5 2 0x128c 2 0 4294967295 STAT_CNT_5 0 14 SMPL_CNT1_DONE 15 15 ixDPCSSYS_CR3_LANE2_DIG_RX_STAT_STAT_CNT_6 2 0x128d 2 0 4294967295 STAT_CNT_6 0 14 SMPL_CNT1_DONE 15 15 ixDPCSSYS_CR3_LANE2_DIG_RX_STAT_CAL_COMP_CLK_CTL 2 0x128e 3 0 4294967295 PRECHRGE_CNT 0 2 REF_DIV_CNT 3 5 RESERVED_15_6 6 15 ixDPCSSYS_CR3_LANE2_DIG_RX_STAT_MATCH_CTL2 2 0x128f 2 0 4294967295 PTTRN_CR1A_19_5 0 14 RESERVED_15_15 15 15 ixDPCSSYS_CR3_LANE2_DIG_RX_STAT_MATCH_CTL3 2 0x1290 2 0 4294967295 PTTRN_MSK_CR1A_19_5 0 14 RESERVED_15_15 15 15 ixDPCSSYS_CR3_LANE2_DIG_RX_STAT_MATCH_CTL4 2 0x1291 2 0 4294967295 PTTRN_CR1B_19_5 0 14 RESERVED_15_15 15 15 ixDPCSSYS_CR3_LANE2_DIG_RX_STAT_MATCH_CTL5 2 0x1292 2 0 4294967295 PTTRN_MSK_CR1B_19_5 0 14 RESERVED_15_15 15 15 ixDPCSSYS_CR3_LANE2_DIG_RX_STAT_STAT_CTL2 2 0x1293 4 0 4294967295 DATA_DLY_SEL_2 0 0 SCOPE_DLY_2 1 1 DISABLE_SAMPLE_COUNT 2 2 RESERVED_15_3 3 15 ixDPCSSYS_CR3_LANE2_DIG_RX_STAT_STAT_STOP 2 0x1294 2 0 4294967295 SC1_STOP 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR3_LANE2_DIG_MPHY_RX_PWM_CTL 2 0x1295 3 0 4294967295 RX_PWM_POL 0 0 RX_PWM_DATA_POL 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR3_LANE2_DIG_MPHY_RX_TERM_LS_CTL 2 0x1296 2 0 4294967295 RX_TERM_LCC_CNT 0 2 RESERVED_15_3 3 15 ixDPCSSYS_CR3_LANE2_DIG_MPHY_RX_ANA_PWM_CLK_STABLE_CNT 2 0x1297 2 0 4294967295 PWM_CLK_STABLE_CNT 0 3 RESERVED_15_4 4 15 ixDPCSSYS_CR3_LANE2_DIG_ANA_TX_OVRD_OUT 2 0x12a0 15 0 4294967295 TX_ANA_CLK_SHIFT 0 0 TX_ANA_DATA_EN 1 1 TX_ANA_REFGEN_EN 2 2 TX_ANA_VCM_HOLD 3 3 TX_ANA_CLK_EN 4 4 TX_ANA_WORD_CLK_EN 5 5 TX_ANA_MPLLA_CLK_EN 6 6 TX_ANA_MPLLB_CLK_EN 7 7 TX_ANA_RESET 8 8 TX_ANA_SERIAL_EN 9 9 TX_ANA_DATA_RATE 10 11 RESERVED 12 12 TX_DIV4_EN 13 13 TX_RXDET_EN 14 14 TX_OVRD_EN 15 15 ixDPCSSYS_CR3_LANE2_DIG_ANA_TX_TERM_CODE_OVRD_OUT 2 0x12a1 5 0 4294967295 TX_TERM_CODE 0 9 TX_TERM_OVRD_EN 10 10 TX_DRV_SRC 11 12 TX_DRV_SRC_OVRD_EN 13 13 RESERVED_15_14 14 15 ixDPCSSYS_CR3_LANE2_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT 2 0x12a2 3 0 4294967295 TX_TERM_DN_CLK 0 0 TX_TERM_CLK_SELF_CLEAR_DISABLE 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR3_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_0 2 0x12a3 3 0 4294967295 TX_ANA_LOAD_CLK 0 0 TX_ANA_CTRL_LEG_PULL_EN_13_0 1 14 TX_EQ_OVRD_EN 15 15 ixDPCSSYS_CR3_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_1 2 0x12a4 2 0 4294967295 TX_ANA_CTRL_LEG_PULL_EN_19_14 0 5 RESERVED_15_6 6 15 ixDPCSSYS_CR3_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_2 2 0x12a5 4 0 4294967295 RESERVED 0 2 TX_ANA_CTRL_EQ_MUX_SEL 3 6 TX_ANA_CTRL_PRE 7 12 RESERVED_15_13 13 15 ixDPCSSYS_CR3_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_3 2 0x12a6 2 0 4294967295 TX_ANA_CTRL_POST 0 8 RESERVED_15_9 9 15 ixDPCSSYS_CR3_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_4 2 0x12a7 1 0 4294967295 TX_ANA_CTRL_LEG_PULL_DIR_19_4 0 15 ixDPCSSYS_CR3_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_5 2 0x12a8 2 0 4294967295 TX_ANA_CTRL_LEG_PULL_DIR_3_0 0 3 RESERVED_15_4 4 15 ixDPCSSYS_CR3_LANE2_DIG_ANA_RX_CTL_OVRD_OUT 2 0x12a9 9 0 4294967295 RESERVED 0 0 RX_ANA_DATA_RATE 1 2 RX_ANA_WORD_CLK_EN 3 3 RX_ANA_DIV4_EN 4 4 RX_ANA_DFE_TAPS_EN 5 5 RX_ANA_ADAPTATION_EN 6 6 RX_LBK_CLK_EN 7 7 RX_CTL_OVRD_EN 8 8 RESERVED_15_9 9 15 ixDPCSSYS_CR3_LANE2_DIG_ANA_RX_PWR_OVRD_OUT 2 0x12aa 9 0 4294967295 RX_ANA_AFE_EN 0 0 RX_ANA_CLK_VREG_EN 1 1 RX_ANA_CLK_DCC_EN 2 2 RX_ANA_CLK_EN 3 3 RX_ANA_CDR_EN 4 4 RX_ANA_DESERIAL_EN 5 5 RX_PWR_OVRD_EN 6 6 RX_ANA_FAST_START 7 7 RESERVED_15_8 8 15 ixDPCSSYS_CR3_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0 2 0x12ab 7 0 4294967295 RX_ANA_CDR_VCO_EN 0 0 RX_ANA_CDR_STARTUP 1 1 RX_VCO_CDR_OVRD_EN 2 2 RX_ANA_CDR_FREQ_TUNE 3 12 RX_ANA_VCO_CNTR_EN 13 13 RX_ANA_VCO_CNTR_CLK 14 14 RX_CDR_FREQ_TUNE_OVRD_EN 15 15 ixDPCSSYS_CR3_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_1 2 0x12ac 3 0 4294967295 RX_ANA_CDR_VCO_LOWFREQ 0 0 RX_ANA_VCO_CNTR_PD 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR3_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_2 2 0x12ad 3 0 4294967295 RX_ANA_CDR_FREQ_TUNE_CLK 0 0 CDR_FREQ_TUNE_CLK_SELF_CLEAR_DISABLE 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR3_LANE2_DIG_ANA_RX_CAL 2 0x12ae 7 0 4294967295 RX_ANA_CAL_MUXA_SEL 0 4 RX_ANA_CAL_MUXB_SEL 5 9 RX_ANA_CAL_LPFBYP_EN 10 10 RESERVED 11 11 RX_ANA_SLICER_CAL_EN 12 12 RX_ANA_CAL_MODE 13 14 RX_ANA_CAL_COMP_EN 15 15 ixDPCSSYS_CR3_LANE2_DIG_ANA_RX_DAC_CTRL 2 0x12af 2 0 4294967295 RX_ANA_CAL_DAC_CTRL 0 7 RESERVED_15_8 8 15 ixDPCSSYS_CR3_LANE2_DIG_ANA_RX_DAC_CTRL_OVRD 2 0x12b0 2 0 4294967295 RX_CAL_DAC_CTRL_OVRD 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR3_LANE2_DIG_ANA_RX_DAC_CTRL_SEL 2 0x12b1 2 0 4294967295 RX_ANA_CAL_DAC_CTRL_SEL 0 4 RESERVED_15_5 5 15 ixDPCSSYS_CR3_LANE2_DIG_ANA_RX_AFE_ATT_VGA 2 0x12b2 5 0 4294967295 RX_ANA_AFE_ATT_LVL 0 2 RX_ANA_AFE_GAIN 3 6 RESERVED 7 10 RX_AFE_OVRD_EN 11 11 RESERVED_15_12 12 15 ixDPCSSYS_CR3_LANE2_DIG_ANA_RX_AFE_CTLE 2 0x12b3 3 0 4294967295 RESERVED 0 2 RX_ANA_AFE_CTLE_BOOST 3 7 RESERVED_15_8 8 15 ixDPCSSYS_CR3_LANE2_DIG_ANA_RX_SCOPE 2 0x12b4 7 0 4294967295 RX_ANA_SCOPE_EN 0 0 RX_ANA_SCOPE_SEL 1 2 RX_ANA_SCOPE_PH_CLK 3 3 RX_ANA_SCOPE_PHASE 4 11 RX_ANA_SCOPE_CLK_EN 12 12 RX_SCOPE_SELF_CLEAR_DISABLE 13 13 RESERVED_15_14 14 15 ixDPCSSYS_CR3_LANE2_DIG_ANA_RX_SLICER_CTRL 2 0x12b5 4 0 4294967295 RX_ANA_SLICER_CTRL_E 0 3 RX_ANA_SLICER_CTRL_O 4 7 RX_ANA_SLICER_CTRL_OVRD_EN 8 8 RESERVED_15_9 9 15 ixDPCSSYS_CR3_LANE2_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST 2 0x12b6 2 0 4294967295 RX_ANA_IQ_PHASE_ADJUST 0 6 RESERVED_15_7 7 15 ixDPCSSYS_CR3_LANE2_DIG_ANA_RX_ANA_IQ_SENSE_EN 2 0x12b7 2 0 4294967295 RX_ANA_IQ_SENSE_EN 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR3_LANE2_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN 2 0x12b8 3 0 4294967295 RX_ANA_CAL_DAC_CTRL_EN 0 0 DAC_CTRL_SELF_CLEAR_DISABLE 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR3_LANE2_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE 2 0x12b9 3 0 4294967295 RX_ANA_AFE_UPDATE_EN 0 0 AFE_UPDATE_SELF_CLEAR_DISABLE 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR3_LANE2_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK 2 0x12ba 3 0 4294967295 RX_ANA_IQ_PHASE_ADJUST_CLK 0 0 PHASE_ADJUST_SELF_CLEAR_DISABLE 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR3_LANE2_DIG_ANA_STATUS_0 2 0x12bb 9 0 4294967295 TX_ANA_CLK_SHIFT_ACK 0 0 TX_ANA_RXDETP_RESULT 1 1 TX_ANA_RXDETM_RESULT 2 2 TX_ANA_LOOPBACK_EN 3 3 TX_ANA_CLK_LB_EN 4 4 RX_ANA_CAL_RESULT 5 5 RX_ANA_SCOPE_DATA 6 6 TX_ANA_DCC_CAL_RESULT 7 7 TX_ANA_CTRL_EQ_MUX 8 15 ixDPCSSYS_CR3_LANE2_DIG_ANA_STATUS_1 2 0x12bc 2 0 4294967295 RX_ANA_VCO_CNTR 0 12 RESERVED_15_13 13 15 ixDPCSSYS_CR3_LANE2_DIG_ANA_RX_TERM_CODE_OVRD_OUT 2 0x12bd 3 0 4294967295 RX_TERM_CODE 0 5 RX_TERM_OVRD_EN 6 6 RESERVED_15_7 7 15 ixDPCSSYS_CR3_LANE2_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT 2 0x12be 3 0 4294967295 RX_TERM_CLK 0 0 RX_TERM_CLK_SELF_CLEAR_DISABLE 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR3_LANE2_DIG_ANA_MPHY_OVRD_OUT 2 0x12bf 9 0 4294967295 RX_ANA_SQ_CTRL_TRESH 0 2 RX_ANA_SQ_CTRL_TRESH_OVRD_EN 3 3 RX_ANA_SQ_CTRL_RESP 4 5 RX_ANA_SQ_CTRL_RESP_OVRD_EN 6 6 RX_ANA_PWM_EN 7 7 RX_ANA_PWM_EN_OVRD_EN 8 8 RX_ANA_PWM_CLK_SEL 9 10 RX_ANA_PWM_CLK_SEL_OVRD_EN 11 11 RESERVED_15_12 12 15 ixDPCSSYS_CR3_LANE2_DIG_ANA_SIGDET_OVRD_OUT_1 2 0x12c0 7 0 4294967295 RX_ANA_SIGDET_HF_THRESH 0 2 RX_ANA_SIGDET_HF_THRESH_OVRD_EN 3 3 RX_ANA_SIGDET_HF_CAL_TUNE 4 9 RX_ANA_SIGDET_CAL_TUNE_OVRD_EN 10 10 RX_ANA_SIGDET_CAL_EN 11 11 RX_ANA_SIGDET_CAL_EN_OVRD_EN 12 12 RESERVED_15_13 13 15 ixDPCSSYS_CR3_LANE2_DIG_ANA_SIGDET_OVRD_OUT_2 2 0x12c1 7 0 4294967295 RX_ANA_SIGDET_LF_THRESH 0 2 RX_ANA_SIGDET_LF_THRESH_OVRD_EN 3 3 RX_ANA_SIGDET_LF_FILTER_EN 4 4 RX_ANA_SIGDET_LF_FILTER_EN_OVRD_EN 5 5 RX_ANA_SIGDET_CAL_TUNE 6 11 RX_ANA_SIGDET_CAL_TUNE_OVRD_EN 12 12 RESERVED_15_13 13 15 ixDPCSSYS_CR3_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT 2 0x12c2 8 0 4294967295 TX_ANA_DCC_CAL_RANGE 0 1 TX_ANA_DCC_CAL_RANGE_OVRD_EN 2 2 TX_ANA_DCC_CAL_COMP_EN 3 3 TX_ANA_DCC_CAL_COMP_EN_OVRD_EN 4 4 TX_ANA_DCC_CAL_CTRL 5 12 TX_ANA_DCC_CAL_CTRL_OVRD_EN 13 13 TX_ANA_DCC_CAL_CTRL_EN 14 14 TX_ANA_DCC_CAL_CTRL_EN_OVRD_EN 15 15 ixDPCSSYS_CR3_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2 2 0x12c3 5 0 4294967295 TX_ANA_DCC_CAL_CTRL_SEL 0 2 TX_ANA_DCC_CAL_CTRL_SEL_OVRD_EN 3 3 TX_ANA_DCC_CLK_COMP 4 4 TX_ANA_DCC_CLK_COMP_OVRD_EN 5 5 RESERVED_15_6 6 15 ixDPCSSYS_CR3_LANE2_DIG_ANA_TX_OVRD_OUT_2 2 0x12c4 6 0 4294967295 TX_ANA_FAST_START 0 0 TX_ANA_FAST_START_OVRD_EN 1 1 TX_CLK_LB_EN 2 2 TX_CLK_LB_EN_OVRD_EN 3 3 TX_ACJTAG_EN 4 4 RESERVED_15_5 5 15 ixDPCSSYS_CR3_LANE2_ANA_TX_OVRD_MEAS 2 0x12e0 9 0 4294967295 OVRD_CLK_SHIFT 0 0 CLK_SHIFT_REG 0 0 MEAS_ATB_CAL_MUX 0 0 MEAS_ATB_CAL_COMP 0 0 OVRD_VCM_HOLD 0 0 VCM_HOLD_REG 0 0 PULL_UP_REG 0 0 PULL_DN_REG 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR3_LANE2_ANA_TX_PWR_OVRD 2 0x12e1 9 0 4294967295 OVRD_TX_LOOPBACK 0 0 LOOPBACK_EN_REG 0 0 REFGEN_EN_REG 0 0 CLK_DIV_EN_REG 0 0 DATA_EN_REG_INT 0 0 CLK_EN_REG 0 0 SERIAL_EN_REG 0 0 OVRD_EN 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR3_LANE2_ANA_TX_ALT_BUS 2 0x12e2 6 0 4294967295 DRV_SOURCE_REG 0 0 OVRD_ALT_BUS 0 0 ATB_S_ENABLE 0 0 TX_ALT_RINGO 0 0 JTAG_DATA_REG 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR3_LANE2_ANA_TX_ATB1 2 0x12e3 9 0 4294967295 MEAS_ATB_GD 0 0 MEAS_ATB_VDDH 0 0 OVERRIDE_RXDETREF 0 0 MEAS_ATB_VPTX 0 0 OVERRIDE_REGREF 0 0 MEAS_ATB_VREG_DRV 0 0 MEAS_ATB_VREG 0 0 MEAS_ATB_VPH_HALF 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR3_LANE2_ANA_TX_ATB2 2 0x12e4 9 0 4294967295 MEAS_ATB_VCM 0 0 MEAS_ATB_CAL_VDAC_CM 0 0 MEAS_ATB_CAL_VDAC_DIFF 0 0 MEAS_ATB_TXM 0 0 MEAS_ATB_TXP 0 0 MEAS_ATB_RXDETREF 0 0 LFPS_HIGH_PRIORITY 0 0 OSC_DIV4_EN 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR3_LANE2_ANA_TX_DCC_DAC 2 0x12e5 2 0 4294967295 DCC_DAC_REG 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR3_LANE2_ANA_TX_DCC_CTRL1 2 0x12e6 7 0 4294967295 NC0 0 0 OVRD_DCC_DAC_CTRL_SEL 0 0 DCC_DAC_CTRL_SEL_REG 0 0 OVRD_DCC_DAC_CTRL_EN 0 0 DCC_DAC_CTRL_EN_REG 0 0 OVRD_DCC_DAC_REG 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR3_LANE2_ANA_TX_TERM_CODE 2 0x12e7 2 0 4294967295 TERM_CODE_REG_70 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR3_LANE2_ANA_TX_TERM_CODE_CTRL 2 0x12e8 8 0 4294967295 VREG_BOOST_1 0 0 OVRD_UPDATE_TERM 0 0 UPDATE_TERM_REG 0 0 OVRD_RESET_TERM 0 0 RESET_TERM_REG 0 0 OVRD_TERM_CODE 0 0 TERM_CODE_REG_98 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR3_LANE2_ANA_TX_OVRD_CLK 2 0x12e9 9 0 4294967295 VREG_BOOST_0 0 0 CLK_LB_EN_REG 0 0 OVRD_LB_EN 0 0 MPLLB_CLK_EN_REG 0 0 MPLLA_CLK_EN_REG 0 0 OVRD_MPLLAB_EN 0 0 WORD_CLK_EN_REG 0 0 OVRD_WORD_CLK_EN 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR3_LANE2_ANA_TX_MISC1 2 0x12ea 8 0 4294967295 MEAS_ATB_CAL_CLK_ALIGN 0 0 OVRD_DCC_DAC_CTRL_RANGE 0 0 DCC_DAC_CTRL_RANGE_REG 0 0 OVRD_VREF_SEL 0 0 VREF_SEL_REG 0 0 FORCE_ATB_TXM 0 0 FORCE_ATB_TXP 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR3_LANE2_ANA_TX_MISC2 2 0x12eb 8 0 4294967295 TX_PEAKING_LVL 0 0 VREG_CP_GAIN_CTRL 0 0 TX_SLEW_EN 0 0 EN_INV_POST 0 0 EN_INV_PRE 0 0 TX_VREG_EN_BYP 0 0 TX_VDRIVER_PULLDN_EN 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR3_LANE2_ANA_TX_MISC3 2 0x12ec 4 0 4294967295 TX_VREG_OVRD_RING_CTRL 0 0 TX_DCC_LOWV 0 0 NC7_2 2 7 RESERVED_15_8 8 15 ixDPCSSYS_CR3_LANE2_ANA_TX_RESERVED2 2 0x12ed 2 0 4294967295 NC7_0 0 7 RESERVED_15_8 8 15 ixDPCSSYS_CR3_LANE2_ANA_TX_RESERVED3 2 0x12ee 2 0 4294967295 NC7_0 0 7 RESERVED_15_8 8 15 ixDPCSSYS_CR3_LANE2_ANA_TX_RESERVED4 2 0x12ef 2 0 4294967295 NC7_0 0 7 RESERVED_15_8 8 15 ixDPCSSYS_CR3_LANE2_ANA_RX_CLK_1 2 0x12f0 8 0 4294967295 CDR_VCO_STARTUP_CODE 0 0 CDR_VCO_TEMP_COMP_EN 0 0 CDR_VCO_USE_UNCAL_BIAS 0 0 OVERRIDE_CDR_EN 0 0 OVRD_CLK_EN 0 0 CLK_EN_REG 0 0 NC7 7 7 RESERVED_15_8 8 15 ixDPCSSYS_CR3_LANE2_ANA_RX_CLK_2 2 0x12f1 5 0 4294967295 IQ_PHASE_ADJUST_REG 0 0 OVRD_IQ_PHASE_ADJUST 0 0 RX_LOOPBACK_CLK_REG 0 0 OVRD_RX_LOOPBACK_CLK 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR3_LANE2_ANA_RX_CDR_DES 2 0x12f2 7 0 4294967295 OVRD_WORD_CLK_EN 0 0 WORD_CLK_EN_REG 0 0 PHDET_ODD_REG 0 0 PHDET_EVEN_REG 0 0 SIGDET_VREF_EXT_EN 0 0 NC7_5 5 7 RESERVED_15_8 8 15 ixDPCSSYS_CR3_LANE2_ANA_RX_SLC_CTRL 2 0x12f3 3 0 4294967295 RX_SLICER_CTRL_O_REG 0 0 RX_SLICER_CTRL_E_REG 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR3_LANE2_ANA_RX_PWR_CTRL1 2 0x12f4 8 0 4294967295 OVRD_ACJT_EN 0 0 ACJT_EN_REG 0 0 OVRD_AFE_EN 0 0 AFE_EN_REG 0 0 AFE_CM_SEL 0 0 ATT_PULLDN_EN 0 0 NC7_7 7 7 RESERVED_15_8 8 15 ixDPCSSYS_CR3_LANE2_ANA_RX_PWR_CTRL2 2 0x12f5 9 0 4294967295 OVRD_DFE_EN 0 0 DFE_EN_REG 0 0 OVRD_DESERIAL_EN 0 0 DESERIAL_EN_REG 0 0 OVRD_LOOPBACK_EN 0 0 LOOPBACK_EN_REG 0 0 OVRD_FAST_START 0 0 FAST_START_REG 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR3_LANE2_ANA_RX_SQ 2 0x12f6 7 0 4294967295 SQ_CTRL_RESP_REG 0 0 OVRD_SQ_CTRL_RESP 0 0 NC4_3 3 4 SQ_CTRL_TRESH_REG 0 0 OVRD_SQ_CTRL_TRESH 0 0 AFE_LOOPBACK_SEL 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR3_LANE2_ANA_RX_CAL1 2 0x12f7 5 0 4294967295 DFE_TAPS_EN_REG 0 0 OVRD_DFE_TAPS_EN 0 0 CAL_MUXB_SEL_REG 0 0 OVRD_CAL_MUXB_SEL 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR3_LANE2_ANA_RX_CAL2 2 0x12f8 5 0 4294967295 AFE_PD_EQ_OFFSET 0 0 CAL_IDACS_USE_UNCAL 0 0 CAL_MUXA_SEL_REG 0 0 OVRD_CAL_MUXA_SEL 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR3_LANE2_ANA_RX_ATB_REGREF 2 0x12f9 8 0 4294967295 OVERRIDE_REGREF_VCO 0 0 OVERRIDE_REGREF_CLK 0 0 OVERRIDE_REGREF_IQC 0 0 BOOST_REGREF_IQC 0 0 OVRD_RX_SLICER_CTRL 0 0 OVRD_RX_TERM_AC_DCZ 0 0 RX_TERM_AC_DCZ_REG 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR3_LANE2_ANA_RX_ATB_MEAS1 2 0x12fa 9 0 4294967295 MASTER_ATB_EN 0 0 MEAS_ATB_VP 0 0 MEAS_ATB_GD 0 0 MEAS_ATB_VREG_VCO 0 0 MEAS_ATB_VREG_CLK 0 0 MEAS_ATB_VREG_IQC 0 0 REGS_FB_DIV_CTRL 0 0 RX_VREG_CLK_BYPASS 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR3_LANE2_ANA_RX_ATB_MEAS2 2 0x12fb 2 0 4294967295 MEAS_ATB_RX 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR3_LANE2_ANA_RX_ATB_MEAS3 2 0x12fc 7 0 4294967295 MEAS_ATB_CDR_VCO_GD 0 0 MEAS_ATB_CDR_VCO_VIREF_200U 0 0 MEAS_ATB_VIBIAS_CDR_VCO 0 0 MEAS_ATB_CDR_VCO_VOSC 0 0 MEAS_ATB_CAL_MUX 0 0 RX_VREG_OVERRIDE_RING_CTRL 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR3_LANE2_ANA_RX_ATB_MEAS4 2 0x12fd 3 0 4294967295 MEAS_ATB_CAL_VREF 0 0 NC7 7 7 RESERVED_15_8 8 15 ixDPCSSYS_CR3_LANE2_ANA_RX_ATB_FRC 2 0x12fe 2 0 4294967295 FRC_ATB_CAL_VREF 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR3_LANE2_ANA_RX_RESERVED1 2 0x12ff 2 0 4294967295 NC7_0 0 7 RESERVED_15_8 8 15 ixDPCSSYS_CR3_LANE3_DIG_ASIC_LANE_OVRD_IN 2 0x1300 5 0 4294967295 LANE_TX2RX_SER_LB 0 0 LANE_RX2TX_PAR_LB 1 1 EN 2 2 RX_ACJTAG_EN 3 3 RESERVED_15_4 4 15 ixDPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_0 2 0x1301 12 0 4294967295 REQ 0 0 REQ_OVRD_EN 1 1 PSTATE 2 3 PSTATE_OVRD_EN 4 4 RATE 5 7 RATE_OVRD_EN 8 8 WIDTH 9 10 WIDTH_OVRD_EN 11 11 MPLLB_SEL 12 12 MPLLB_SEL_OVRD_EN 13 13 DATA_EN 14 14 DATA_EN_OVRD_EN 15 15 ixDPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_1 2 0x1302 11 0 4294967295 NYQUIST_DATA 0 0 DISABLE 1 1 BEACON_EN 2 2 EN 3 3 TX_MAIN_CURSOR 4 9 MAIN_OVRD_EN 10 10 ASYNC_DRV_EN 11 11 ASYNC_DRV_OVRD_EN 12 12 TX_VREGDRV_BYP_OVRD 13 13 TX_VREGDRV_BYP_OVRD_EN 14 14 RESERVED_15_15 15 15 ixDPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_2 2 0x1303 6 0 4294967295 TX_PRE_CURSOR 0 5 PRE_OVRD_EN 6 6 TX_POST_CURSOR 7 12 POST_OVRD_EN 13 13 HDMIMODE_EN 14 14 HDMIMODE_ENABLE_OVRD_EN 15 15 ixDPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_3 2 0x1304 15 0 4294967295 CLK_RDY 0 0 CLK_RDY_OVRD_EN 1 1 DETECT_RX_REQ 2 2 DETECT_RX_REQ_OVRD_EN 3 3 INVERT 4 4 INVERT_OVRD_EN 5 5 LPD 6 6 LPD_OVRD_EN 7 7 TX_DC_COUP_EN 8 8 TX_DC_COUP_EN_OVRD_EN 9 9 PMA_EXTENDED_FIFO_EN 10 10 PMA_EXTENDED_FIFO_EN_OVRD_EN 11 11 TX_MPHY_MODE_EN 12 12 TX_MPHY_MODE_EN_OVRD_EN 13 13 RESERVED_15_14 14 15 ixDPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_4 2 0x1305 3 0 4294967295 RESET 0 0 RESET_OVRD_EN 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_OUT 2 0x1306 5 0 4294967295 TX_ACK 0 0 EN_TX_ACK 1 1 DETRX_RESULT 2 2 EN_DETRX_RESULT 3 3 RESERVED_15_4 4 15 ixDPCSSYS_CR3_LANE3_DIG_ASIC_RX_OVRD_OUT_0 2 0x130f 9 0 4294967295 ACK 0 0 ACK_OVRD_EN 1 1 ADAPT_STS 2 3 ADAPT_STS_OVRD_EN 4 4 RX_ASYNC_DATA 5 5 RX_ASYNC_DATA_OVRD_EN 6 6 RX_SQ_WEAKKEEP_OUT 7 7 RX_SQ_WEAKKEEP_OUT_OVRD_EN 8 8 RESERVED_15_9 9 15 ixDPCSSYS_CR3_LANE3_DIG_ASIC_LANE_ASIC_IN 2 0x1310 3 0 4294967295 LANE_TX2RX_SER_LB 0 0 LANE_RX2TX_PAR_LB 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR3_LANE3_DIG_ASIC_TX_ASIC_IN_0 2 0x1311 12 0 4294967295 CLK_RDY 0 0 RESET 1 1 INVERT 2 2 DATA_EN 3 3 REQ 4 4 LPD 5 5 PSTATE 6 7 RATE 8 10 WIDTH 11 12 MPLLB_SEL 13 13 DETECT_RX_REQ 14 14 DISABLE 15 15 ixDPCSSYS_CR3_LANE3_DIG_ASIC_TX_ASIC_IN_1 2 0x1312 7 0 4294967295 BEACON_EN 0 0 TX_MAIN_CURSOR 1 6 TX_ASYNC_EN 7 7 TX_ASYNC_DATA 8 8 TX_ASYNC_DRV_EN 9 9 TX_VREGDRV_BYP 10 10 RESERVED_15_11 11 15 ixDPCSSYS_CR3_LANE3_DIG_ASIC_TX_ASIC_IN_2 2 0x1313 3 0 4294967295 TX_PRE_CURSOR 0 5 TX_POST_CURSOR 6 11 RESERVED_15_12 12 15 ixDPCSSYS_CR3_LANE3_DIG_ASIC_TX_ASIC_OUT 2 0x1314 3 0 4294967295 TX_ACK 0 0 DETRX_RESULT 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR3_LANE3_DIG_ASIC_RX_ASIC_OUT_0 2 0x131b 4 0 4294967295 ACK 0 0 VALID 1 1 ADAPT_STS 2 3 RESERVED_15_4 4 15 ixDPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_5 2 0x131d 15 0 4294967295 RPTR_EN_MASTER_LANE 0 0 RPTR_EN_MASTER_LANE_OVRD_EN 1 1 DIG_CLK_EN_OTHER_LANE 2 2 DIG_CLK_EN_OTHER_LANE_OVRD_EN 3 3 DIG_CLK_STATE_MASTER_LANE 4 4 DIG_CLK_STATE_MASTER_LANE_OVRD_EN 5 5 SHIFT_MASTER_LANE 6 6 SHIFT_MASTER_LANE_ORVD_EN 7 7 SHIFT_ACK_OTHER_LANE 8 8 SHIFT_ACK_OTHER_LANE_OVRD_EN 9 9 LANE_MASTER 10 10 LANE_MASTER_OVRD_IN_EN 11 11 TX_DWORD_CLK_SYNC_OVRD 12 12 TX_DWORD_CLK_SYNC_OVRD_EN 13 13 RESERVED_15_14 14 15 ixDPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_OUT_1 2 0x131e 11 0 4294967295 RPTR_EN_OUT 0 0 RPTR_EN_OUT_OVRD_EN 1 1 DIG_CLK_EN_OUT 2 2 DIG_CLK_EN_OUT_OVRD_EN 3 3 DIG_CLK_STATE_OUT 4 4 DIG_CLK_STATE_OUT_OVRD_EN 5 5 SHIFT_OUT 6 6 SHIFT_OUT_OVRD_EN 7 7 SHIFT_ACK_OUT 8 8 SHIFT_ACK_OUT_OVRD_EN 9 9 RESERVED_15_10 10 15 ixDPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0 2 0x1320 11 0 4294967295 TX_P0_ANA_REFGEN_EN 0 0 TX_P0_ANA_VCM_HOLD 1 1 TX_P0_ANA_CLK_EN 2 2 TX_P0_ANA_WORD_CLK_EN 3 3 TX_P0_ANA_RESET 4 4 TX_P0_ANA_SERIAL_EN 5 5 TX_P0_DIG_CLK_EN 6 6 TX_P0_DATA_EN 7 7 TX_P0_ALLOW_RXDET 8 8 TX_P0_ANA_DCC_COMP_CAL_EN 9 9 RESERVED_15_10 10 15 ixDPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S 2 0x1321 11 0 4294967295 TX_P0S_ANA_REFGEN_EN 0 0 TX_P0S_ANA_VCM_HOLD 1 1 TX_P0S_ANA_CLK_EN 2 2 TX_P0S_ANA_WORD_CLK_EN 3 3 TX_P0S_ANA_RESET 4 4 TX_P0S_ANA_SERIAL_EN 5 5 TX_P0S_DIG_CLK_EN 6 6 TX_P0S_DATA_EN 7 7 TX_P0S_ALLOW_RXDET 8 8 TX_P0S_ANA_DCC_COMP_CAL_EN 9 9 RESERVED_15_10 10 15 ixDPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1 2 0x1322 11 0 4294967295 TX_P1_ANA_REFGEN_EN 0 0 TX_P1_ANA_VCM_HOLD 1 1 TX_P1_ANA_CLK_EN 2 2 TX_P1_ANA_WORD_CLK_EN 3 3 TX_P1_ANA_RESET 4 4 TX_P1_ANA_SERIAL_EN 5 5 TX_P1_DIG_CLK_EN 6 6 TX_P1_DATA_EN 7 7 TX_P1_ALLOW_RXDET 8 8 TX_P1_ANA_DCC_COMP_CAL_EN 9 9 RESERVED_15_10 10 15 ixDPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2 2 0x1323 12 0 4294967295 TX_P2_ANA_REFGEN_EN 0 0 TX_P2_ANA_VCM_HOLD 1 1 TX_P2_ANA_CLK_EN 2 2 TX_P2_ANA_WORD_CLK_EN 3 3 TX_P2_ANA_RESET 4 4 TX_P2_ANA_SERIAL_EN 5 5 TX_P2_DIG_CLK_EN 6 6 TX_P2_DATA_EN 7 7 TX_P2_ALLOW_RXDET 8 8 TX_P2_ALLOW_VBOOST 9 9 TX_P2_ANA_DCC_COMP_CAL_EN 10 10 RESERVED_15_11 11 15 ixDPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_0 2 0x1324 2 0 4294967295 TX_REFGEN_EN_TIME 0 7 TX_CLK_EN 8 15 ixDPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_1 2 0x1325 2 0 4294967295 TX_VCM_HOLD_TIME_14_0 0 14 SKIP_TX_VCM_HOLD_WAIT 15 15 ixDPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_2 2 0x1326 2 0 4294967295 TX_VBOOST_DIS_TIME_12_0 0 12 DTB_SEL 13 15 ixDPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_3 2 0x1327 3 0 4294967295 TX_VCM_HOLD_TIME_17_15 0 2 TX_VBOOST_DIS_TIME_13 3 3 RESERVED_15_4 4 15 ixDPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_4 2 0x1328 2 0 4294967295 TX_VCM_HOLD_GS_TIME 0 14 SKIP_TX_VCM_HOLD_GS_PULSE 15 15 ixDPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_5 2 0x1329 5 0 4294967295 TX_RXDET_TIME 0 9 FAST_TX_RXDET 10 10 TX_RESET_TIME 11 12 TX_SERIAL_EN_TIME 13 14 RESERVED_15_15 15 15 ixDPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_DCC_CR_BANK_ADDR 2 0x132a 1 0 4294967295 ADDR 0 15 ixDPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_DCC_CR_BANK_DATA 2 0x132b 1 0 4294967295 DATA 0 15 ixDPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_DCC_DAC_CTRL 2 0x132c 2 0 4294967295 CTRL 0 7 RESERVED_15_8 8 15 ixDPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_DCC_DAC_RANGE 2 0x132d 2 0 4294967295 CTRL 0 1 RESERVED_15_2 2 15 ixDPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_DCC_DAC_SEL 2 0x132e 6 0 4294967295 SEL 0 2 REQ 3 3 CTRL_UPD 4 4 RANGE_UPD 5 5 BIN_HOT 6 6 RESERVED_15_7 7 15 ixDPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_DCC_DAC_ACK 2 0x132f 2 0 4294967295 ACK 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_DCC_DAC_ADDR 2 0x1330 1 0 4294967295 ADDR 0 15 ixDPCSSYS_CR3_LANE3_DIG_TX_CLK_ALIGN_TX_CTL_0 2 0x1331 4 0 4294967295 TX_NUM_2UI_SHIFTS_16B_MODE 0 3 TX_NUM_2UI_SHIFTS_20B_MODE 4 7 TX_FIFO_BYPASS 8 8 RESERVED_15_9 9 15 ixDPCSSYS_CR3_LANE3_DIG_TX_LBERT_CTL 2 0x1332 4 0 4294967295 MODE 0 3 TRIGGER_ERR 4 4 PAT0 5 14 RESERVED_15_15 15 15 ixDPCSSYS_CR3_LANE3_DIG_RX_STAT_LD_VAL_1 2 0x1380 2 0 4294967295 SC1_LD_VAL 0 14 SC1_START 15 15 ixDPCSSYS_CR3_LANE3_DIG_RX_STAT_DATA_MSK 2 0x1381 1 0 4294967295 DATA_MSK_15_0 0 15 ixDPCSSYS_CR3_LANE3_DIG_RX_STAT_MATCH_CTL0 2 0x1382 4 0 4294967295 PTTRN_MSK_CR1A_4_0 0 4 PTTRN_CR1A_4_0 5 9 DATA_MSK_19_16 10 13 SCOPE_DLY 14 15 ixDPCSSYS_CR3_LANE3_DIG_RX_STAT_MATCH_CTL1 2 0x1383 5 0 4294967295 PTTRN_CR1B_EN 0 0 PTTRN_MSK_CR1B_4_0 1 5 PTTRN_CR1B_4_0 6 10 PTTRN_CR1A_ADPT_EN 11 11 RESERVED_15_12 12 15 ixDPCSSYS_CR3_LANE3_DIG_RX_STAT_STAT_CTL0 2 0x1384 10 0 4294967295 RESERVED_0 0 0 CORR_SHFT_SEL_VGA 1 1 CORR_SHFT_SEL 2 2 CORR_SRC_SEL 3 4 CORR_MODE_EN 5 5 STAT_SHFT_SEL 6 9 STAT_SRC_SEL 10 12 STAT_RXCLK_SEL 13 13 SC_TIMER_MODE 14 14 SKIP_EN 15 15 ixDPCSSYS_CR3_LANE3_DIG_RX_STAT_STAT_CTL1 2 0x1385 13 0 4294967295 STAT_CNT_0_EN 0 0 STAT_CNT_1_EN 1 1 STAT_CNT_2_EN 2 2 STAT_CNT_3_EN 3 3 STAT_CNT_4_EN 4 4 STAT_CNT_5_EN 5 5 STAT_CNT_6_EN 6 6 RESERVED_8_7 7 8 SC_PAUSE 9 9 STAT_CLK_EN 10 10 DATA_DLY_SEL 11 12 VLD_LOSS_CLR 13 13 VLD_CTL 14 15 ixDPCSSYS_CR3_LANE3_DIG_RX_STAT_SMPL_CNT1 2 0x1386 2 0 4294967295 SMPL_CNT1 0 14 SMPL_CNT1_DONE 15 15 ixDPCSSYS_CR3_LANE3_DIG_RX_STAT_STAT_CNT_0 2 0x1387 2 0 4294967295 STAT_CNT_0 0 14 SMPL_CNT1_DONE 15 15 ixDPCSSYS_CR3_LANE3_DIG_RX_STAT_STAT_CNT_1 2 0x1388 2 0 4294967295 STAT_CNT_1 0 14 SMPL_CNT1_DONE 15 15 ixDPCSSYS_CR3_LANE3_DIG_RX_STAT_STAT_CNT_2 2 0x1389 2 0 4294967295 STAT_CNT_2 0 14 SMPL_CNT1_DONE 15 15 ixDPCSSYS_CR3_LANE3_DIG_RX_STAT_STAT_CNT_3 2 0x138a 2 0 4294967295 STAT_CNT_3 0 14 SMPL_CNT1_DONE 15 15 ixDPCSSYS_CR3_LANE3_DIG_RX_STAT_STAT_CNT_4 2 0x138b 2 0 4294967295 STAT_CNT_4 0 14 SMPL_CNT1_DONE 15 15 ixDPCSSYS_CR3_LANE3_DIG_RX_STAT_STAT_CNT_5 2 0x138c 2 0 4294967295 STAT_CNT_5 0 14 SMPL_CNT1_DONE 15 15 ixDPCSSYS_CR3_LANE3_DIG_RX_STAT_STAT_CNT_6 2 0x138d 2 0 4294967295 STAT_CNT_6 0 14 SMPL_CNT1_DONE 15 15 ixDPCSSYS_CR3_LANE3_DIG_RX_STAT_CAL_COMP_CLK_CTL 2 0x138e 3 0 4294967295 PRECHRGE_CNT 0 2 REF_DIV_CNT 3 5 RESERVED_15_6 6 15 ixDPCSSYS_CR3_LANE3_DIG_RX_STAT_MATCH_CTL2 2 0x138f 2 0 4294967295 PTTRN_CR1A_19_5 0 14 RESERVED_15_15 15 15 ixDPCSSYS_CR3_LANE3_DIG_RX_STAT_MATCH_CTL3 2 0x1390 2 0 4294967295 PTTRN_MSK_CR1A_19_5 0 14 RESERVED_15_15 15 15 ixDPCSSYS_CR3_LANE3_DIG_RX_STAT_MATCH_CTL4 2 0x1391 2 0 4294967295 PTTRN_CR1B_19_5 0 14 RESERVED_15_15 15 15 ixDPCSSYS_CR3_LANE3_DIG_RX_STAT_MATCH_CTL5 2 0x1392 2 0 4294967295 PTTRN_MSK_CR1B_19_5 0 14 RESERVED_15_15 15 15 ixDPCSSYS_CR3_LANE3_DIG_RX_STAT_STAT_CTL2 2 0x1393 4 0 4294967295 DATA_DLY_SEL_2 0 0 SCOPE_DLY_2 1 1 DISABLE_SAMPLE_COUNT 2 2 RESERVED_15_3 3 15 ixDPCSSYS_CR3_LANE3_DIG_RX_STAT_STAT_STOP 2 0x1394 2 0 4294967295 SC1_STOP 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR3_LANE3_DIG_ANA_TX_OVRD_OUT 2 0x13a0 15 0 4294967295 TX_ANA_CLK_SHIFT 0 0 TX_ANA_DATA_EN 1 1 TX_ANA_REFGEN_EN 2 2 TX_ANA_VCM_HOLD 3 3 TX_ANA_CLK_EN 4 4 TX_ANA_WORD_CLK_EN 5 5 TX_ANA_MPLLA_CLK_EN 6 6 TX_ANA_MPLLB_CLK_EN 7 7 TX_ANA_RESET 8 8 TX_ANA_SERIAL_EN 9 9 TX_ANA_DATA_RATE 10 11 RESERVED 12 12 TX_DIV4_EN 13 13 TX_RXDET_EN 14 14 TX_OVRD_EN 15 15 ixDPCSSYS_CR3_LANE3_DIG_ANA_TX_TERM_CODE_OVRD_OUT 2 0x13a1 5 0 4294967295 TX_TERM_CODE 0 9 TX_TERM_OVRD_EN 10 10 TX_DRV_SRC 11 12 TX_DRV_SRC_OVRD_EN 13 13 RESERVED_15_14 14 15 ixDPCSSYS_CR3_LANE3_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT 2 0x13a2 3 0 4294967295 TX_TERM_DN_CLK 0 0 TX_TERM_CLK_SELF_CLEAR_DISABLE 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR3_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_0 2 0x13a3 3 0 4294967295 TX_ANA_LOAD_CLK 0 0 TX_ANA_CTRL_LEG_PULL_EN_13_0 1 14 TX_EQ_OVRD_EN 15 15 ixDPCSSYS_CR3_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_1 2 0x13a4 2 0 4294967295 TX_ANA_CTRL_LEG_PULL_EN_19_14 0 5 RESERVED_15_6 6 15 ixDPCSSYS_CR3_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_2 2 0x13a5 4 0 4294967295 RESERVED 0 2 TX_ANA_CTRL_EQ_MUX_SEL 3 6 TX_ANA_CTRL_PRE 7 12 RESERVED_15_13 13 15 ixDPCSSYS_CR3_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_3 2 0x13a6 2 0 4294967295 TX_ANA_CTRL_POST 0 8 RESERVED_15_9 9 15 ixDPCSSYS_CR3_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_4 2 0x13a7 1 0 4294967295 TX_ANA_CTRL_LEG_PULL_DIR_19_4 0 15 ixDPCSSYS_CR3_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_5 2 0x13a8 2 0 4294967295 TX_ANA_CTRL_LEG_PULL_DIR_3_0 0 3 RESERVED_15_4 4 15 ixDPCSSYS_CR3_LANE3_DIG_ANA_STATUS_0 2 0x13bb 9 0 4294967295 TX_ANA_CLK_SHIFT_ACK 0 0 TX_ANA_RXDETP_RESULT 1 1 TX_ANA_RXDETM_RESULT 2 2 TX_ANA_LOOPBACK_EN 3 3 TX_ANA_CLK_LB_EN 4 4 RX_ANA_CAL_RESULT 5 5 RX_ANA_SCOPE_DATA 6 6 TX_ANA_DCC_CAL_RESULT 7 7 TX_ANA_CTRL_EQ_MUX 8 15 ixDPCSSYS_CR3_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT 2 0x13c2 8 0 4294967295 TX_ANA_DCC_CAL_RANGE 0 1 TX_ANA_DCC_CAL_RANGE_OVRD_EN 2 2 TX_ANA_DCC_CAL_COMP_EN 3 3 TX_ANA_DCC_CAL_COMP_EN_OVRD_EN 4 4 TX_ANA_DCC_CAL_CTRL 5 12 TX_ANA_DCC_CAL_CTRL_OVRD_EN 13 13 TX_ANA_DCC_CAL_CTRL_EN 14 14 TX_ANA_DCC_CAL_CTRL_EN_OVRD_EN 15 15 ixDPCSSYS_CR3_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2 2 0x13c3 5 0 4294967295 TX_ANA_DCC_CAL_CTRL_SEL 0 2 TX_ANA_DCC_CAL_CTRL_SEL_OVRD_EN 3 3 TX_ANA_DCC_CLK_COMP 4 4 TX_ANA_DCC_CLK_COMP_OVRD_EN 5 5 RESERVED_15_6 6 15 ixDPCSSYS_CR3_LANE3_DIG_ANA_TX_OVRD_OUT_2 2 0x13c4 6 0 4294967295 TX_ANA_FAST_START 0 0 TX_ANA_FAST_START_OVRD_EN 1 1 TX_CLK_LB_EN 2 2 TX_CLK_LB_EN_OVRD_EN 3 3 TX_ACJTAG_EN 4 4 RESERVED_15_5 5 15 ixDPCSSYS_CR3_LANE3_ANA_TX_OVRD_MEAS 2 0x13e0 9 0 4294967295 OVRD_CLK_SHIFT 0 0 CLK_SHIFT_REG 0 0 MEAS_ATB_CAL_MUX 0 0 MEAS_ATB_CAL_COMP 0 0 OVRD_VCM_HOLD 0 0 VCM_HOLD_REG 0 0 PULL_UP_REG 0 0 PULL_DN_REG 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR3_LANE3_ANA_TX_PWR_OVRD 2 0x13e1 9 0 4294967295 OVRD_TX_LOOPBACK 0 0 LOOPBACK_EN_REG 0 0 REFGEN_EN_REG 0 0 CLK_DIV_EN_REG 0 0 DATA_EN_REG_INT 0 0 CLK_EN_REG 0 0 SERIAL_EN_REG 0 0 OVRD_EN 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR3_LANE3_ANA_TX_ALT_BUS 2 0x13e2 6 0 4294967295 DRV_SOURCE_REG 0 0 OVRD_ALT_BUS 0 0 ATB_S_ENABLE 0 0 TX_ALT_RINGO 0 0 JTAG_DATA_REG 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR3_LANE3_ANA_TX_ATB1 2 0x13e3 9 0 4294967295 MEAS_ATB_GD 0 0 MEAS_ATB_VDDH 0 0 OVERRIDE_RXDETREF 0 0 MEAS_ATB_VPTX 0 0 OVERRIDE_REGREF 0 0 MEAS_ATB_VREG_DRV 0 0 MEAS_ATB_VREG 0 0 MEAS_ATB_VPH_HALF 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR3_LANE3_ANA_TX_ATB2 2 0x13e4 9 0 4294967295 MEAS_ATB_VCM 0 0 MEAS_ATB_CAL_VDAC_CM 0 0 MEAS_ATB_CAL_VDAC_DIFF 0 0 MEAS_ATB_TXM 0 0 MEAS_ATB_TXP 0 0 MEAS_ATB_RXDETREF 0 0 LFPS_HIGH_PRIORITY 0 0 OSC_DIV4_EN 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR3_LANE3_ANA_TX_DCC_DAC 2 0x13e5 2 0 4294967295 DCC_DAC_REG 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR3_LANE3_ANA_TX_DCC_CTRL1 2 0x13e6 7 0 4294967295 NC0 0 0 OVRD_DCC_DAC_CTRL_SEL 0 0 DCC_DAC_CTRL_SEL_REG 0 0 OVRD_DCC_DAC_CTRL_EN 0 0 DCC_DAC_CTRL_EN_REG 0 0 OVRD_DCC_DAC_REG 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR3_LANE3_ANA_TX_TERM_CODE 2 0x13e7 2 0 4294967295 TERM_CODE_REG_70 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR3_LANE3_ANA_TX_TERM_CODE_CTRL 2 0x13e8 8 0 4294967295 VREG_BOOST_1 0 0 OVRD_UPDATE_TERM 0 0 UPDATE_TERM_REG 0 0 OVRD_RESET_TERM 0 0 RESET_TERM_REG 0 0 OVRD_TERM_CODE 0 0 TERM_CODE_REG_98 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR3_LANE3_ANA_TX_OVRD_CLK 2 0x13e9 9 0 4294967295 VREG_BOOST_0 0 0 CLK_LB_EN_REG 0 0 OVRD_LB_EN 0 0 MPLLB_CLK_EN_REG 0 0 MPLLA_CLK_EN_REG 0 0 OVRD_MPLLAB_EN 0 0 WORD_CLK_EN_REG 0 0 OVRD_WORD_CLK_EN 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR3_LANE3_ANA_TX_MISC1 2 0x13ea 8 0 4294967295 MEAS_ATB_CAL_CLK_ALIGN 0 0 OVRD_DCC_DAC_CTRL_RANGE 0 0 DCC_DAC_CTRL_RANGE_REG 0 0 OVRD_VREF_SEL 0 0 VREF_SEL_REG 0 0 FORCE_ATB_TXM 0 0 FORCE_ATB_TXP 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR3_LANE3_ANA_TX_MISC2 2 0x13eb 8 0 4294967295 TX_PEAKING_LVL 0 0 VREG_CP_GAIN_CTRL 0 0 TX_SLEW_EN 0 0 EN_INV_POST 0 0 EN_INV_PRE 0 0 TX_VREG_EN_BYP 0 0 TX_VDRIVER_PULLDN_EN 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR3_LANE3_ANA_TX_MISC3 2 0x13ec 4 0 4294967295 TX_VREG_OVRD_RING_CTRL 0 0 TX_DCC_LOWV 0 0 NC7_2 2 7 RESERVED_15_8 8 15 ixDPCSSYS_CR3_LANE3_ANA_TX_RESERVED2 2 0x13ed 2 0 4294967295 NC7_0 0 7 RESERVED_15_8 8 15 ixDPCSSYS_CR3_LANE3_ANA_TX_RESERVED3 2 0x13ee 2 0 4294967295 NC7_0 0 7 RESERVED_15_8 8 15 ixDPCSSYS_CR3_LANE3_ANA_TX_RESERVED4 2 0x13ef 2 0 4294967295 NC7_0 0 7 RESERVED_15_8 8 15 ixDPCSSYS_CR3_RAWCMN_DIG_CMN_CTL 2 0x2000 2 0 4294967295 PHY_FUNC_RST 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR3_RAWCMN_DIG_MPLLA_OVRD_IN 2 0x2001 10 0 4294967295 MPLLA_WORD_DIV2_EN_OVRD_VAL 0 0 MPLLA_WORD_DIV2_EN_OVRD_EN 1 1 MPLLA_TX_CLK_DIV_OVRD_VAL 2 4 MPLLA_TX_CLK_DIV_OVRD_EN 5 5 MPLLA_DIV10_CLK_EN_OVRD_VAL 6 6 MPLLA_DIV10_CLK_EN_OVRD_EN 7 7 MPLLA_DIV8_CLK_EN_OVRD_VAL 8 8 MPLLA_DIV8_CLK_EN_OVRD_EN 9 9 MPLLA_BW_OVRD_EN 10 10 RESERVED_15_11 11 15 ixDPCSSYS_CR3_RAWCMN_DIG_MPLLA_BW_OVRD_IN 2 0x2002 1 0 4294967295 MPLLA_BW_OVRD_VAL 0 15 ixDPCSSYS_CR3_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_0 2 0x2003 7 0 4294967295 MPLLA_SSC_RANGE_OVRD_VAL 0 2 MPLLA_SSC_RANGE_OVRD_EN 3 3 MPLLA_SSC_CLK_SEL_OVRD_VAL 4 6 MPLLA_SSC_CLK_SEL_OVRD_EN 7 7 MPLLA_SSC_EN_OVRD_VAL 8 8 MPLLA_SSC_EN_OVRD_EN 9 9 RESERVED_15_10 10 15 ixDPCSSYS_CR3_RAWCMN_DIG_MPLLB_OVRD_IN 2 0x2004 10 0 4294967295 MPLLB_WORD_DIV2_EN_OVRD_VAL 0 0 MPLLB_WORD_DIV2_EN_OVRD_EN 1 1 MPLLB_TX_CLK_DIV_OVRD_VAL 2 4 MPLLB_TX_CLK_DIV_OVRD_EN 5 5 MPLLB_DIV10_CLK_EN_OVRD_VAL 6 6 MPLLB_DIV10_CLK_EN_OVRD_EN 7 7 MPLLB_DIV8_CLK_EN_OVRD_VAL 8 8 MPLLB_DIV8_CLK_EN_OVRD_EN 9 9 MPLLB_BW_OVRD_EN 10 10 RESERVED_15_11 11 15 ixDPCSSYS_CR3_RAWCMN_DIG_MPLLB_BW_OVRD_IN 2 0x2005 1 0 4294967295 MPLLB_BW_OVRD_VAL 0 15 ixDPCSSYS_CR3_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_0 2 0x2006 7 0 4294967295 MPLLB_SSC_RANGE_OVRD_VAL 0 2 MPLLB_SSC_RANGE_OVRD_EN 3 3 MPLLB_SSC_CLK_SEL_OVRD_VAL 4 6 MPLLB_SSC_CLK_SEL_OVRD_EN 7 7 MPLLB_SSC_EN_OVRD_VAL 8 8 MPLLB_SSC_EN_OVRD_EN 9 9 RESERVED_15_10 10 15 ixDPCSSYS_CR3_RAWCMN_DIG_LANE_FSM_OP_XTND 2 0x2007 2 0 4294967295 DATA 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR3_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_1 2 0x2008 3 0 4294967295 MPLLA_FRACN_CTRL_OVRD_VAL 0 10 MPLLA_FRACN_CTRL_OVRD_EN 11 11 RESERVED_15_12 12 15 ixDPCSSYS_CR3_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_1 2 0x2009 3 0 4294967295 MPLLB_FRACN_CTRL_OVRD_VAL 0 10 MPLLB_FRACN_CTRL_OVRD_EN 11 11 RESERVED_15_12 12 15 ixDPCSSYS_CR3_RAWCMN_DIG_CMN_CTL_1 2 0x200a 13 0 4294967295 MPLLA_INIT_CAL_DISABLE_OVRD_VAL 0 0 MPLLA_INIT_CAL_DISABLE_OVRD_EN 1 1 MPLLB_INIT_CAL_DISABLE_OVRD_VAL 2 2 MPLLB_INIT_CAL_DISABLE_OVRD_EN 3 3 RTUNE_REQ_OVRD_VAL 4 4 RTUNE_REQ_OVRD_EN 5 5 HDMIMODE_ENABLE_OVRD_VAL 6 6 HDMIMODE_ENABLE_OVRD_EN 7 7 TX_PWM_CLK_SEL_OVRD_VAL 8 9 TX_PWM_CLK_SEL_OVRD_EN 10 10 TX_PWM_CLK_EN_OVRD_VAL 11 11 TX_PWM_CLK_EN_OVRD_EN 12 12 RESERVED_15_13 13 15 ixDPCSSYS_CR3_RAWCMN_DIG_MPLL_STATE_CTL 2 0x200b 8 0 4294967295 MPLL_OFF_TIME 0 5 MPLLA_STATE 6 6 MPLLB_STATE 7 7 MPLL_STATE_OVRD_OUT_EN 8 8 MPLL_FORCE_ON_TIME 9 12 MPLLB_BANK_SEL 13 13 MPLLA_BANK_SEL 14 14 RESERVED_15_15 15 15 ixDPCSSYS_CR3_RAWCMN_DIG_TX_CAL_CODE 2 0x200c 2 0 4294967295 DATA 0 0 RESERVED_15_4 4 15 ixDPCSSYS_CR3_RAWCMN_DIG_SRAM_INIT_DONE 2 0x200d 2 0 4294967295 DATA 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR3_RAWCMN_DIG_OCLA 2 0x200e 3 0 4294967295 DIV2_CLK_EN 0 0 TCA_OCLA_PROBE_SEL 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR3_RAWCMN_DIG_SUP_ANA_OVRD 2 0x200f 7 0 4294967295 REF_ALT_CLK_LP_SEL_OVRD_EN 0 0 REF_ALT_CLK_LP_SEL_OVRD_VAL 1 1 SUP_PRE_HP_OVRD_EN 2 2 SUP_PRE_HP_OVRD_VAL 3 3 SUP_RX_VCO_VREF_SEL_OVRD_EN 4 4 SUP_RX_VCO_VREF_SEL_OVRD_VAL 5 7 RESERVED_15_8 8 15 ixDPCSSYS_CR3_RAWCMN_DIG_PCS_RAW_ID_CODE 2 0x2010 1 0 4294967295 DATA 0 0 ixDPCSSYS_CR3_RAWCMN_DIG_FW_ID_CODE_1 2 0x2011 1 0 4294967295 W_ID_CODE_1 0 15 ixDPCSSYS_CR3_RAWCMN_DIG_FW_ID_CODE_2 2 0x2012 1 0 4294967295 W_ID_CODE_2 0 15 ixDPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_0 2 0x2020 2 0 4294967295 RTUNE_RX_VAL_0 0 5 RESERVED_15_6 6 15 ixDPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_0 2 0x2021 2 0 4294967295 RTUNE_TXDN_VAL_0 0 9 RESERVED_15_10 10 15 ixDPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_0 2 0x2022 2 0 4294967295 RTUNE_TXUP_VAL_0 0 9 RESERVED_15_10 10 15 ixDPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_1 2 0x2023 2 0 4294967295 RTUNE_RX_VAL_1 0 5 RESERVED_15_6 6 15 ixDPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_1 2 0x2024 2 0 4294967295 RTUNE_TXDN_VAL_1 0 9 RESERVED_15_10 10 15 ixDPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_1 2 0x2025 2 0 4294967295 RTUNE_TXUP_VAL_1 0 9 RESERVED_15_10 10 15 ixDPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_2 2 0x2026 2 0 4294967295 RTUNE_RX_VAL_2 0 5 RESERVED_15_6 6 15 ixDPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_2 2 0x2027 2 0 4294967295 RTUNE_TXDN_VAL_2 0 9 RESERVED_15_10 10 15 ixDPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_2 2 0x2028 2 0 4294967295 RTUNE_TXUP_VAL_2 0 9 RESERVED_15_10 10 15 ixDPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_3 2 0x2029 2 0 4294967295 RTUNE_RX_VAL_3 0 5 RESERVED_15_6 6 15 ixDPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_3 2 0x202a 2 0 4294967295 RTUNE_TXDN_VAL_3 0 9 RESERVED_15_10 10 15 ixDPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_3 2 0x202b 2 0 4294967295 RTUNE_TXUP_VAL_3 0 9 RESERVED_15_10 10 15 ixDPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_4 2 0x202c 2 0 4294967295 RTUNE_RX_VAL_4 0 5 RESERVED_15_6 6 15 ixDPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_4 2 0x202d 2 0 4294967295 RTUNE_TXDN_VAL_4 0 9 RESERVED_15_10 10 15 ixDPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_4 2 0x202e 2 0 4294967295 RTUNE_TXUP_VAL_4 0 9 RESERVED_15_10 10 15 ixDPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_5 2 0x202f 2 0 4294967295 RTUNE_RX_VAL_5 0 5 RESERVED_15_6 6 15 ixDPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_5 2 0x2030 2 0 4294967295 RTUNE_TXDN_VAL_5 0 9 RESERVED_15_10 10 15 ixDPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_5 2 0x2031 2 0 4294967295 RTUNE_TXUP_VAL_5 0 9 RESERVED_15_10 10 15 ixDPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_6 2 0x2032 2 0 4294967295 RTUNE_RX_VAL_6 0 5 RESERVED_15_6 6 15 ixDPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_6 2 0x2033 2 0 4294967295 RTUNE_TXDN_VAL_6 0 9 RESERVED_15_10 10 15 ixDPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_6 2 0x2034 2 0 4294967295 RTUNE_TXUP_VAL_6 0 9 RESERVED_15_10 10 15 ixDPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_7 2 0x2035 2 0 4294967295 RTUNE_RX_VAL_7 0 5 RESERVED_15_6 6 15 ixDPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_7 2 0x2036 2 0 4294967295 RTUNE_TXDN_VAL_7 0 9 RESERVED_15_10 10 15 ixDPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_7 2 0x2037 2 0 4294967295 RTUNE_TXUP_VAL_7 0 9 RESERVED_15_10 10 15 ixDPCSSYS_CR3_RAWCMN_DIG_AON_CMN_SRAM_BL_CFG 2 0x2038 5 0 4294967295 SRAM_PGATE_BL_EN 0 0 SRAM_BL_ROM 1 1 SRAM_BL_BYPASS 2 2 SRAM_BL_START 3 3 RESERVED_15_4 4 15 ixDPCSSYS_CR3_RAWCMN_DIG_AON_CMN_PG_OVRD_IN 2 0x2039 7 0 4294967295 PMA_PWR_STABLE_OVRD 0 0 PCS_PWR_STABLE_OVRD 1 1 PG_RESET_OVRD_VAL 2 2 PG_RESET_OVRD_EN 3 3 PG_MODE_EN_OVRD_VAL 4 4 PG_MODE_EN_OVRD_EN 5 5 RESERVED_15_6 6 15 ixDPCSSYS_CR3_RAWCMN_DIG_AON_CMN_PG_OVRD_OUT 2 0x203a 8 0 4294967295 PMA_PWR_EN_OVRD 0 0 PCS_PWR_EN_OVRD 1 1 MON_IN_VALID_OVRD_VAL 2 2 MON_IN_VALID_OVRD_EN 3 3 MON_IN_PULL_DOWN 4 4 ANA_ISOLATION_EN_OVRD_EN 5 5 ANA_ISOLATION_EN_OVRD_VAL 6 6 RESERVED_15_7 7 15 ixDPCSSYS_CR3_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN 2 0x203b 11 0 4294967295 MPLLA_FORCE_EN_OVRD_VAL 0 0 MPLLA_FORCE_EN_OVRD_EN 1 1 MPLLB_FORCE_EN_OVRD_VAL 2 2 MPLLB_FORCE_EN_OVRD_EN 3 3 REF_CLK_EN_OVRD_VAL 4 4 REF_CLK_EN_OVRD_EN 5 5 MPLLA_FORCE_ACK_OVRD_VAL 6 6 MPLLA_FORCE_ACK_OVRD_EN 7 7 MPLLB_FORCE_ACK_OVRD_VAL 8 8 MPLLB_FORCE_ACK_OVRD_EN 9 9 RESERVED_15_10 10 15 ixDPCSSYS_CR3_RAWCMN_DIG_AON_CMN_VREF_STATS 2 0x203c 3 0 4294967295 SUP_ANA_VPHUD_SELVPH 0 0 VREF_CAL_DONE 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RES_OVRD_IN 2 0x203d 8 0 4294967295 RES_REQ_IN 0 0 RES_ACK_IN 1 1 RES_OVRD_EN 2 2 RES_REQ_OUT 3 3 RES_REQ_OUT_OVRD_EN 4 4 RES_ACK_OUT 5 5 RES_ACK_OUT_OVRD_EN 6 6 RESERVED_15_7 7 15 ixDPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RES_ASIC_IN_OUT 2 0x203e 5 0 4294967295 RES_REQ_IN 0 0 RES_REQ_OUT 1 1 RES_ACK_IN 2 2 RES_ACK_OUT 3 3 RESERVED_15_4 4 15 ixDPCSSYS_CR3_RAWCMN_DIG_AON_CMN_REF_RANGE_OVRD 2 0x203f 3 0 4294967295 OVRD_VAL 0 4 OVRD_EN 5 5 RESERVED_15_6 6 15 ixDPCSSYS_CR3_RAWCMN_DIG_AON_CMN_MISC_CONF_IN_1 2 0x2040 2 0 4294967295 MPLL_PWRDN_TIME 0 9 RESERVED_15_10 10 15 ixDPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN 2 0x3000 12 0 4294967295 PSTATE 0 1 LPD 2 2 WIDTH 3 4 RATE 5 7 MPLLB_SEL 8 8 MPLL_EN 9 9 OVRD_EN 10 10 MSTR_MPLLA_STATE 11 11 MSTR_MPLLB_STATE 12 12 MSTR_MPLL_OVRD_EN 13 13 TX_ASYNC_EN_OVR_VAL 14 14 TX_ASYNC_EN_OVR_EN 15 15 ixDPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1 2 0x3001 13 0 4294967295 RESET_OVRD_VAL 0 0 RESET_OVRD_EN 1 1 REQ_OVRD_VAL 2 2 REQ_OVRD_EN 3 3 DETRX_REQ_OVRD_VAL 4 4 DETRX_REQ_OVRD_EN 5 5 VBOOST_EN_OVRD_VAL 6 6 VBOOST_EN_OVRD_EN 7 7 IBOOST_LVL_OVRD_VAL 8 11 IBOOST_LVL_OVRD_EN 12 12 TX_BEACON_EN_OVR_VAL 13 13 TX_BEACON_EN_OVR_EN 14 14 RESERVED_15_15 15 15 ixDPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_PCS_IN 2 0x3002 12 0 4294967295 RESET 0 0 REQ 1 1 PSTATE 2 3 LPD 4 4 WIDTH 5 6 RATE 7 9 MPLLB_SEL 10 10 MPLL_EN 11 11 MSTR_MPLLA_STATE 12 12 MSTR_MPLLB_STATE 13 13 DETRX_REQ 14 14 RESERVED_15_15 15 15 ixDPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_OVRD_OUT 2 0x3003 6 0 4294967295 ACK 0 0 DETRX_RESULT 1 1 EN_CTL 2 2 TX_DWORD_CLK_SYNC_OVRD_VAL 3 3 TX_DWORD_CLK_SYNC_OVRD_EN 4 4 RESERVED_15_5 5 15 ixDPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_PCS_OUT 2 0x3004 2 0 4294967295 ACK 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN 2 0x3005 12 0 4294967295 RATE 0 1 WIDTH 2 3 PSTATE 4 5 LPD 6 6 OVRD_EN 7 7 ADAPT_AFE_EN 8 8 ADAPT_DFE_EN 9 9 LANE_RX2TX_PAR_LB_EN_OVRD_VAL 10 10 LANE_RX2TX_PAR_LB_EN_OVRD_EN 11 11 RX_DATA_EN_OVRD_VAL_R 12 12 RX_DATA_EN_OVRD_EN_R 13 13 RESERVED_15_14 14 15 ixDPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1 2 0x3006 12 0 4294967295 RESET_OVRD_VAL 0 0 RESET_OVRD_EN 1 1 REQ_OVRD_VAL 2 2 REQ_OVRD_EN 3 3 RX_LOS_THRSHLD_OVRD_VAL 4 6 RX_LOS_THRSHLD_OVRD_EN 7 7 ADAPT_REQ 8 8 ADAPT_REQ_OVRD_EN 9 9 ADAPT_CONT 10 10 OFFCAN_CONT 11 11 CONT_OVRD_EN 12 12 RESERVED_15_13 13 15 ixDPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_2 2 0x3007 4 0 4294967295 VCO_LD_VAL_OVRD 0 12 VCO_LD_VAL_OVRD_EN 13 13 VCO_LOWFREQ_VAL_OVRD 14 14 VCO_LOWFREQ_VAL_OVRD_EN 15 15 ixDPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_3 2 0x3008 3 0 4294967295 REF_LD_VAL_OVRD 0 6 REF_LD_VAL_OVRD_EN 7 7 RESERVED_15_8 8 15 ixDPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_PCS_IN 2 0x3009 13 0 4294967295 REQ 0 0 RATE 1 2 WIDTH 3 4 PSTATE 5 6 LPD 7 7 CDR_VCO_LOWFREQ 8 8 ADAPT_AFE_EN 9 9 ADAPT_DFE_EN 10 10 ADAPT_REQ 11 11 ADAPT_CONT 12 12 OFFCAN_CONT 13 13 RESET 14 14 RESERVED_15_15 15 15 ixDPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_1 2 0x300a 2 0 4294967295 REF_LD_VAL 0 6 RESERVED_15_7 7 15 ixDPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_2 2 0x300b 2 0 4294967295 VCO_LD_VAL 0 12 RESERVED_15_13 13 15 ixDPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_3 2 0x300c 4 0 4294967295 EQ_ATT_LVL 0 2 EQ_VGA1_GAIN 3 6 EQ_VGA2_GAIN 7 10 EQ_CTLE_BOOST 11 15 ixDPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_4 2 0x300d 3 0 4294967295 EQ_CTLE_POLE 0 2 EQ_DFE_TAP1 3 10 RESERVED_15_11 11 15 ixDPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT 2 0x300e 3 0 4294967295 ACK 0 0 EN_CTL 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_PCS_OUT 2 0x300f 2 0 4294967295 ACK 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_ADAPT_ACK 2 0x3010 2 0 4294967295 RX_ADAPT_ACK 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_ADAPT_FOM 2 0x3011 2 0 4294967295 RX_ADAPT_FOM 0 7 RESERVED_15_8 8 15 ixDPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_TXPRE_DIR 2 0x3012 2 0 4294967295 RX_TXPRE_DIR 0 1 RESERVED_15_2 2 15 ixDPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_TXMAIN_DIR 2 0x3013 2 0 4294967295 RX_TXMAIN_DIR 0 1 RESERVED_15_2 2 15 ixDPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_TXPOST_DIR 2 0x3014 2 0 4294967295 RX_TXPOST_DIR 0 1 RESERVED_15_2 2 15 ixDPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_LANE_NUMBER 2 0x3015 2 0 4294967295 LANE_NUMBER 0 3 RESERVED_15_4 4 15 ixDPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RESERVED_1 2 0x3016 1 0 4294967295 RESERVED_REG_1 0 15 ixDPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RESERVED_2 2 0x3017 1 0 4294967295 RESERVED_REG_2 0 15 ixDPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN 2 0x3018 16 0 4294967295 RX_RESET_ATE_OVRD_VAL 0 0 RX_RESET_ATE_OVRD_EN 1 1 TX_RESET_ATE_OVRD_VAL 2 2 TX_RESET_ATE_OVRD_EN 3 3 RX_REQ_ATE_OVRD_VAL 4 4 RX_REQ_ATE_OVRD_EN 5 5 TX_REQ_ATE_OVRD_VAL 6 6 TX_REQ_ATE_OVRD_EN 7 7 RX_ADAPT_AFE_EN_OVRD_VAL 8 8 RX_ADAPT_AFE_EN_OVRD_EN 9 9 RX_ADAPT_DFE_EN_OVRD_VAL 10 10 RX_ADAPT_DFE_EN_OVRD_EN 11 11 TX_DATA_EN_ATE_OVRD_VAL 12 12 TX_DATA_EN_ATE_OVRD_EN 13 13 RX_DATA_EN_ATE_OVRD_VAL 14 14 RX_DATA_EN_ATE_OVRD_EN 15 15 ixDPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN 2 0x3019 3 0 4294967295 RX_EQ_DELTA_IQ_OVRD_VAL 0 3 RX_EQ_DELTA_IQ_OVRD_EN 4 4 RESERVED_15_5 5 15 ixDPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN 2 0x301a 5 0 4294967295 RX_TERM_CTRL_OVRD_VAL 0 2 RX_TERM_CTRL_OVRD_EN 3 3 TX_TERM_CTRL_OVRD_VAL 4 6 TX_TERM_CTRL_OVRD_EN 7 7 RESERVED_15_8 8 15 ixDPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TXRX_TERM_CTRL_IN 2 0x301b 3 0 4294967295 RX_TERM_CTRL 0 2 TX_TERM_CTRL 3 5 RESERVED_15_6 6 15 ixDPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT_1 2 0x301c 2 0 4294967295 RX_CLK_EN 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_EQ_OVRD_IN_1 2 0x301d 4 0 4294967295 RX_EQ_AFE_GAIN_OVRD_VAL 0 3 RX_EQ_ATT_LVL_OVRD_VAL 4 6 RX_EQ_OVRD_EN 7 7 RESERVED_15_8 8 15 ixDPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_EQ_OVRD_IN_2 2 0x301e 3 0 4294967295 RX_EQ_DFE_TAP1_OVRD_VAL 0 7 RX_EQ_CTLE_BOOST_OVRD_VAL 8 12 RESERVED_15_13 13 15 ixDPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_PH2_CAL 2 0x301f 4 0 4294967295 PH2_CAL_ACK_VAL 0 0 PH2_CAL_REQ_VAL 1 1 PH2_CAL_REQ_OVRD_VAL 2 2 RESERVED_15_3 3 15 ixDPCSSYS_CR3_RAWLANE0_DIG_FSM_FSM_OVRD_CTL 2 0x3020 5 0 4294967295 FSM_JMP_ADDR 0 11 FSM_JMP_EN 12 12 FSM_CMD_START 13 13 FSM_OVRD_EN 14 14 FSM_BREAK 15 15 ixDPCSSYS_CR3_RAWLANE0_DIG_FSM_MEM_ADDR_MON 2 0x3021 1 0 4294967295 MEM_ADDR 0 15 ixDPCSSYS_CR3_RAWLANE0_DIG_FSM_STATUS_MON 2 0x3022 8 0 4294967295 STATE 0 4 CMD_RDY 5 5 ALU_OVFLW 6 6 ALU_RES_EQ0 7 7 WAIT_CNT_EQ0 8 8 WRMSK_DISABLED 9 9 RDMSK_DISABLED 10 10 RESERVED_15_11 11 15 ixDPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_RX_STARTUP_CAL 2 0x3023 2 0 4294967295 FAST_RX_STARTUP_CAL 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_RX_ADAPT 2 0x3024 2 0 4294967295 FAST_RX_ADAPT 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_RX_AFE_CAL 2 0x3025 2 0 4294967295 FAST_RX_AFE_CAL 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_RX_DFE_CAL 2 0x3026 2 0 4294967295 FAST_RX_DFE_CAL 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_RX_BYPASS_CAL 2 0x3027 2 0 4294967295 FAST_RX_BYPASS_CAL 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_RX_REFLVL_CAL 2 0x3028 2 0 4294967295 FAST_RX_REFLVL_CAL 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_RX_IQ_CAL 2 0x3029 2 0 4294967295 FAST_RX_IQ_CAL 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_RX_AFE_ADAPT 2 0x302a 2 0 4294967295 FAST_RX_AFE_ADAPT 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_RX_DFE_ADAPT 2 0x302b 2 0 4294967295 FAST_RX_DFE_ADAPT 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_SUP 2 0x302c 2 0 4294967295 FAST_SUP 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_TX_CMN_MODE 2 0x302d 2 0 4294967295 FAST_TX_CMN_MODE 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_TX_RXDET 2 0x302e 2 0 4294967295 FAST_TX_RXDET 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_RX_PWRUP 2 0x302f 2 0 4294967295 FAST_RX_PWRUP 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_RX_VCO_WAIT 2 0x3030 2 0 4294967295 FAST_RX_VCO_WAIT 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_RX_VCO_CAL 2 0x3031 2 0 4294967295 FAST_RX_VCO_CAL 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR3_RAWLANE0_DIG_FSM_CMNCAL_MPLL_STATUS 2 0x3032 3 0 4294967295 CMNCAL_MPLL_INIT 0 0 CMNCAL_MPLL_DONE 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_RX_CONT_CAL_ADAPT 2 0x3033 2 0 4294967295 FAST_RX_CONT_CAL_ADAPT 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_RX_CONT_ADAPT 2 0x3034 2 0 4294967295 FAST_RX_CONT_ADAPT 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_RX_CONT_DATA_CAL 2 0x3035 2 0 4294967295 FAST_RX_CONT_DATA_CAL 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_RX_CONT_PHASE_CAL 2 0x3036 2 0 4294967295 FAST_RX_CONT_PHASE_CAL 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_RX_CONT_AFE_CAL 2 0x3037 2 0 4294967295 FAST_RX_CONT_AFE_CAL 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_FLAGS 2 0x3038 12 0 4294967295 TX_FAST_DCC_CAL 0 0 RX_FAST_DCC_CAL 1 1 RX_FAST_VPHUD_CAL 2 2 RX_FAST_VREF_CAL 3 3 RX_FAST_SIGDET_CAL 4 4 RESERVED_2 5 7 TX_FAST_CONT_DCC_CAL 8 8 RX_FAST_CONT_DCC_CAL 9 9 RX_FAST_CONT_VPHUD_CAL 10 10 RX_FAST_CONT_VREF_CAL 11 11 RESERVED_1 12 14 TX_SKIP_SUP_CAL 15 15 ixDPCSSYS_CR3_RAWLANE0_DIG_FSM_CR_LOCK 2 0x3039 3 0 4294967295 CR_REG_LOCK 0 0 CR_MEM_LOCK 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR3_RAWLANE0_DIG_FSM_TX_DCC_FLAGS 2 0x303a 4 0 4294967295 RATE 0 0 DIV 1 1 MPLL 2 2 RESERVED_15_3 3 15 ixDPCSSYS_CR3_RAWLANE0_DIG_FSM_TX_DCC_STATUS 2 0x303b 2 0 4294967295 FLAG 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR3_RAWLANE0_DIG_FSM_OCLA 2 0x303c 4 0 4294967295 PC_EN 0 0 REG_BANK1_EN 1 1 REG_BANK2_EN 2 2 RESERVED_15_3 3 15 ixDPCSSYS_CR3_RAWLANE0_DIG_FSM_TX_EQ_UPDATE_FLAG 2 0x303d 2 0 4294967295 TX_EQ_UPDATE_FLAG 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR3_RAWLANE0_DIG_FSM_CMNCAL_RCAL_STATUS 2 0x303e 3 0 4294967295 CMNCAL_RCAL_INIT 0 0 CMNCAL_RCAL_DONE 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR3_RAWLANE0_DIG_FSM_RX_IQ_PHASE_OFFSET 2 0x303f 2 0 4294967295 RX_IQ_PHASE_OFFSET 0 3 RESERVED_15_4 4 15 ixDPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_RESET_RTN_REQ 2 0x3040 2 0 4294967295 RESET_RTN_REQ 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_RX_RESET_IRQ 2 0x3041 2 0 4294967295 RX_RESET 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_RX_REQ_IRQ 2 0x3042 2 0 4294967295 RX_REQ 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_RX_RATE_IRQ 2 0x3043 2 0 4294967295 RX_RATE_IRQ 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_RX_PSTATE_IRQ 2 0x3044 2 0 4294967295 RX_PSTATE_IRQ 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ 2 0x3045 2 0 4294967295 RX_ADAPT_REQ_IRQ 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ 2 0x3046 2 0 4294967295 RX_ADAPT_DIS_IRQ 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_RX_RESET_IRQ_CLR 2 0x3047 2 0 4294967295 RX_RESET_IRQ_CLR 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_RX_REQ_IRQ_CLR 2 0x3048 2 0 4294967295 RX_REQ_IRQ_CLR 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_RX_RATE_IRQ_CLR 2 0x3049 2 0 4294967295 RX_RATE_IRQ_CLR 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR 2 0x304a 2 0 4294967295 RX_PSTATE_IRQ_CLR 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR 2 0x304b 2 0 4294967295 RX_ADAPT_REQ_IRQ_CLR 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR 2 0x304c 2 0 4294967295 RX_ADAPT_DIS_IRQ_CLR 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK 2 0x304d 12 0 4294967295 RX_REQ_IRQ_MSK 0 0 RX_RATE_IRQ_MSK 1 1 RX_PSTATE_IRQ_MSK 2 2 RX_ADAPT_REQ_IRQ_MSK 3 3 RX_ADAPT_DIS_IRQ_MSK 4 4 RX_RESET_IRQ_MSK 5 5 LANE_XCVR_MODE_IRQ_MSK 6 6 RX_PH2_CAL_REQ_IRQ_MSK 7 7 RX_PH2_CAL_DIS_IRQ_MSK 8 8 LANE_RX2TX_SER_LB_EN_IRQ_MSK 9 9 DCC_ONDMD_IRQ_MSK 10 10 RESERVED_15_11 11 15 ixDPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK_2 2 0x304e 3 0 4294967295 TX_RESET_IRQ_MSK 0 0 TX_REQ_IRQ_MSK 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ 2 0x304f 2 0 4294967295 LANE_XCVR_MODE_IRQ 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR 2 0x3050 2 0 4294967295 LANE_XCVR_MODE_IRQ_CLR 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ 2 0x3051 2 0 4294967295 RX_PH2_CAL_REQ_IRQ 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ 2 0x3052 2 0 4294967295 RX_PH2_CAL_DIS_IRQ 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR 2 0x3053 2 0 4294967295 RX_PH2_CAL_REQ_IRQ_CLR 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR 2 0x3054 2 0 4294967295 RX_PH2_CAL_DIS_IRQ_CLR 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ 2 0x3055 2 0 4294967295 LANE_RX2TX_SER_LB_EN_IRQ 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR 2 0x3056 2 0 4294967295 LANE_RX2TX_SER_LB_EN_IRQ_CLR 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_DCC_ONDMD_IRQ 2 0x3057 2 0 4294967295 IRQ 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_TX_RESET_IRQ 2 0x3058 2 0 4294967295 TX_RESET 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_TX_REQ_IRQ 2 0x3059 2 0 4294967295 TX_REQ 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_TX_RESET_IRQ_CLR 2 0x305a 2 0 4294967295 TX_RESET_IRQ_CLR 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_TX_REQ_IRQ_CLR 2 0x305b 2 0 4294967295 TX_REQ_IRQ_CLR 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_LANE_OVRD_IN 2 0x3060 4 0 4294967295 LANE_MPLLA_EN_IN 0 0 LANE_MPLLB_EN_IN 1 1 LANE_OVRD_EN 2 2 RESERVED_15_3 3 15 ixDPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_LANE_OVRD_OUT 2 0x3061 4 0 4294967295 LANE_MPLLA_EN_OUT 0 0 LANE_MPLLB_EN_OUT 1 1 LANE_OVRD_EN 2 2 RESERVED_15_3 3 15 ixDPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_SUP_OVRD_IN 2 0x3062 4 0 4294967295 MPLLA_STATE 0 0 MPLLB_STATE 1 1 SUP_STATE_OVRD_EN 2 2 RESERVED_15_3 3 15 ixDPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_SUP_PMA_IN 2 0x3063 3 0 4294967295 MPLLA_STATE 0 0 MPLLB_STATE 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT 2 0x3064 16 0 4294967295 TX_REQ_OVRD_VAL 0 0 TX_REQ_OVRD_EN 1 1 TX_RESET_OVRD_VAL 2 2 TX_RESET_OVRD_EN 3 3 TX_BEACON_EN_OVRD_VAL 4 4 TX_BEACON_EN_OVRD_EN 5 5 TX_ASYNC_DRV_EN_OVRD_VAL 6 6 TX_ASYNC_DRV_EN_OVRD_EN 7 7 TX_ASYNC_EN_OVRD_VAL 8 8 TX_ASYNC_EN_OVRD_EN 9 9 TX_DWORD_CLK_SYNC_OVRD_VAL 10 10 TX_DWORD_CLK_SYNC_OVRD_EN 11 11 LANE_TX2RX_SER_LB_EN_OVRD_VAL 12 12 LANE_TX2RX_SER_LB_EN_OVRD_EN 13 13 TX_PMA_DATA_EN_OVRD_VAL_R 14 14 TX_PMA_DATA_EN_OVRD_EN_R 15 15 ixDPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_TX_PMA_IN 2 0x3065 2 0 4294967295 ACK 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT 2 0x3066 9 0 4294967295 RX_REQ_OVRD_VAL 0 0 RX_REQ_OVRD_EN 1 1 RX_RESET_OVRD_VAL 2 2 RX_RESET_OVRD_EN 3 3 LANE_RX2TX_PAR_LB_EN_OVRD_VAL 4 4 LANE_RX2TX_PAR_LB_EN_OVRD_EN 5 5 RX_PMA_DATA_EN_OVRD_VAL_R 6 6 RX_PMA_DATA_EN_OVRD_EN_R 7 7 RESERVED_15_8 8 15 ixDPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_RX_PMA_IN 2 0x3067 2 0 4294967295 ACK 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_LANE_RTUNE_CTL 2 0x3068 2 0 4294967295 LANE_RTUNE_REQ 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_SUP_PMA_IN_1 2 0x3069 2 0 4294967295 RTUNE_ACK 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_IN 2 0x306a 9 0 4294967295 RX_PMA_PWM_WORD_CLK_R 0 0 RX_PMA_PWM_WORD_CLK_OVRD_EN 1 1 RX_PMA_PWM_DATA_R 2 2 RX_PMA_PWM_DATA_OVRD_EN 3 3 RX_PMA_PWM_CLK_R 4 4 RX_PMA_PWM_CLK_OVRD_EN 5 5 RX_PMA_TERM_CTL_R 6 7 RX_PMA_TERM_CTL_OVRD_EN 8 8 RESERVED_15_9 9 15 ixDPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_OUT 2 0x306b 7 0 4294967295 RX_PMA_PWM_EN 0 0 RX_PMA_PWM_EN_OVRD_EN 1 1 RX_PMA_PWM_CLK_SEL 2 3 RX_PMA_PWM_CLK_SEL_OVRD_EN 4 4 RX_PMA_ASYNC_EN 5 5 RX_PMA_ASYNC_EN_OVRD_EN 6 6 RESERVED_15_7 7 15 ixDPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_RX_ADAPT_OVRD_OUT 2 0x306c 3 0 4294967295 RX_PMA_IQ_PHASE_ADJUST_MAP_OVRD_VAL 0 6 RX_PMA_IQ_PHASE_ADJUST_MAP_OVRD_EN 7 7 RESERVED_15_8 8 15 ixDPCSSYS_CR3_RAWLANE0_DIG_TX_CTL_TX_FSM_CTL 2 0x3080 6 0 4294967295 TX_WAIT_MPLL_OFF_TIME 0 6 TX_P2_ALLOW_RXDET 7 7 TX_P1_ALLOW_RXDET 8 8 TX_P0S_ALLOW_RXDET 9 9 TX_P0_ALLOW_RXDET 10 10 RESERVED_15_11 11 15 ixDPCSSYS_CR3_RAWLANE0_DIG_TX_CTL_TX_CLK_CTL 2 0x3081 4 0 4294967295 TX_CLK_EN 0 0 TX_CLK_SEL 1 4 ASYNC_BEACON_WAIT_TIME 5 10 RESERVED_15_11 11 15 ixDPCSSYS_CR3_RAWLANE0_DIG_TX_CTL_TX_DCC_CONT_STATUS 2 0x3082 2 0 4294967295 ENABLE 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR3_RAWLANE0_DIG_TX_CTL_OCLA 2 0x3083 2 0 4294967295 FSM_EN 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR3_RAWLANE0_DIG_TX_CTL_UPCS_OCLA 2 0x3084 3 0 4294967295 DATA_EN 0 1 CLK_EN 2 2 RESERVED_15_3 3 15 ixDPCSSYS_CR3_RAWLANE0_DIG_RX_CTL_RX_FSM_CTL 2 0x30a0 3 0 4294967295 EN_RX_CTL_FSM 0 0 RATE_CHG_IN_P1 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR3_RAWLANE0_DIG_RX_CTL_RX_LOS_MASK_CTL 2 0x30a1 2 0 4294967295 RX_LOS_MASK_CNT 0 8 RESERVED_15_9 9 15 ixDPCSSYS_CR3_RAWLANE0_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL 2 0x30a2 2 0 4294967295 RX_DATA_EN_OVRD_CNT 0 4 INT_REF_TRCK_CNT 5 15 ixDPCSSYS_CR3_RAWLANE0_DIG_RX_CTL_OFFCAN_CONT_STATUS 2 0x30a3 2 0 4294967295 ENABLE 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR3_RAWLANE0_DIG_RX_CTL_ADAPT_CONT_STATUS 2 0x30a4 2 0 4294967295 ENABLE 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR3_RAWLANE0_DIG_RX_CTL_UPCS_OCLA 2 0x30a5 3 0 4294967295 DATA_EN 0 2 CLK_EN 3 3 RESERVED_15_4 4 15 ixDPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN 2 0x30c0 11 0 4294967295 RATE_OVRD_VAL 0 1 RATE_OVRD_EN 2 2 WIDTH_OVRD_VAL 3 4 WIDTH_OVRD_EN 5 5 PSTATE_OVRD_VAL 6 7 PSTATE_OVRD_EN 8 8 LPD_OVRD_VAL 9 9 LPD_OVRD_EN 10 10 LANE_RX2TX_PAR_LB_EN_OVRD_VAL 11 11 LANE_RX2TX_PAR_LB_EN_OVRD_EN 12 12 RESERVED_15_13 13 15 ixDPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN 2 0x30c1 12 0 4294967295 PSTATE 0 1 LPD 2 2 WIDTH 3 4 RATE 5 7 MPLLB_SEL 8 8 MPLL_EN 9 9 OVRD_EN 10 10 MSTR_MPLLA_STATE 11 11 MSTR_MPLLB_STATE 12 12 MSTR_MPLL_OVRD_EN 13 13 TX_ASYNC_EN_OVR_VAL 14 14 TX_ASYNC_EN_OVR_EN 15 15 ixDPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1 2 0x30c2 13 0 4294967295 DETRX_REQ_OVRD_VAL 0 0 DETRX_REQ_OVRD_EN 1 1 VBOOST_EN_OVRD_VAL 2 2 VBOOST_EN_OVRD_EN 3 3 IBOOST_LVL_OVRD_VAL 4 7 IBOOST_LVL_OVRD_EN 8 8 TX_BEACON_EN_OVR_VAL 9 9 TX_BEACON_EN_OVR_EN 10 10 LANE_TX2RX_SER_LB_EN_OVRD_VAL 11 11 LANE_TX2RX_SER_LB_EN_OVRD_EN 12 12 TX_ASYNC_DATA_OVRD_VAL 13 13 TX_ASYNC_DATA_OVRD_EN 14 14 RESERVED_15_15 15 15 ixDPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_MASTER_MPLL_LOOP 2 0x30c3 3 0 4294967295 MPLLB_LOOP_EN 0 0 MPLLA_LOOP_EN 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1 2 0x30c4 11 0 4294967295 RESERVED 0 1 RX_LOS_LFPS_EN_OVRD_VAL 2 2 RX_LOS_LFPS_EN_OVRD_EN 3 3 RX_LOS_THRSHLD_OVRD_VAL 4 6 RX_LOS_THRSHLD_OVRD_EN 7 7 ADAPT_REQ 8 8 ADAPT_REQ_OVRD_EN 9 9 ADAPT_CONT 10 10 OFFCAN_CONT 11 11 CONT_OVRD_EN 12 12 RESERVED_15_13 13 15 ixDPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_2 2 0x30c5 4 0 4294967295 VCO_LD_VAL_OVRD 0 12 VCO_LD_VAL_OVRD_EN 13 13 VCO_LOWFREQ_VAL_OVRD 14 14 VCO_LOWFREQ_VAL_OVRD_EN 15 15 ixDPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_3 2 0x30c6 3 0 4294967295 REF_LD_VAL_OVRD 0 6 REF_LD_VAL_OVRD_EN 7 7 RESERVED_15_8 8 15 ixDPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT_2 2 0x30c7 3 0 4294967295 RX_VALID 0 0 RX_VALID_OVRD_EN 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_2 2 0x30c8 7 0 4294967295 LANE_TX2RX_SER_LB_EN_OVRD_VAL 0 0 LANE_TX2RX_SER_LB_EN_OVRD_EN 1 1 TX_DATA_EN_OVRD_VAL_R 2 2 TX_DATA_EN_OVRD_EN_R 3 3 TX_ASYNC_DATA_OVRD_VAL_R 4 4 TX_ASYNC_DATA_OVRD_EN_R 5 5 RESERVED_15_6 6 15 ixDPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN 2 0x3100 12 0 4294967295 PSTATE 0 1 LPD 2 2 WIDTH 3 4 RATE 5 7 MPLLB_SEL 8 8 MPLL_EN 9 9 OVRD_EN 10 10 MSTR_MPLLA_STATE 11 11 MSTR_MPLLB_STATE 12 12 MSTR_MPLL_OVRD_EN 13 13 TX_ASYNC_EN_OVR_VAL 14 14 TX_ASYNC_EN_OVR_EN 15 15 ixDPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1 2 0x3101 13 0 4294967295 RESET_OVRD_VAL 0 0 RESET_OVRD_EN 1 1 REQ_OVRD_VAL 2 2 REQ_OVRD_EN 3 3 DETRX_REQ_OVRD_VAL 4 4 DETRX_REQ_OVRD_EN 5 5 VBOOST_EN_OVRD_VAL 6 6 VBOOST_EN_OVRD_EN 7 7 IBOOST_LVL_OVRD_VAL 8 11 IBOOST_LVL_OVRD_EN 12 12 TX_BEACON_EN_OVR_VAL 13 13 TX_BEACON_EN_OVR_EN 14 14 RESERVED_15_15 15 15 ixDPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_PCS_IN 2 0x3102 12 0 4294967295 RESET 0 0 REQ 1 1 PSTATE 2 3 LPD 4 4 WIDTH 5 6 RATE 7 9 MPLLB_SEL 10 10 MPLL_EN 11 11 MSTR_MPLLA_STATE 12 12 MSTR_MPLLB_STATE 13 13 DETRX_REQ 14 14 RESERVED_15_15 15 15 ixDPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_OVRD_OUT 2 0x3103 6 0 4294967295 ACK 0 0 DETRX_RESULT 1 1 EN_CTL 2 2 TX_DWORD_CLK_SYNC_OVRD_VAL 3 3 TX_DWORD_CLK_SYNC_OVRD_EN 4 4 RESERVED_15_5 5 15 ixDPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_PCS_OUT 2 0x3104 2 0 4294967295 ACK 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN 2 0x3105 12 0 4294967295 RATE 0 1 WIDTH 2 3 PSTATE 4 5 LPD 6 6 OVRD_EN 7 7 ADAPT_AFE_EN 8 8 ADAPT_DFE_EN 9 9 LANE_RX2TX_PAR_LB_EN_OVRD_VAL 10 10 LANE_RX2TX_PAR_LB_EN_OVRD_EN 11 11 RX_DATA_EN_OVRD_VAL_R 12 12 RX_DATA_EN_OVRD_EN_R 13 13 RESERVED_15_14 14 15 ixDPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1 2 0x3106 12 0 4294967295 RESET_OVRD_VAL 0 0 RESET_OVRD_EN 1 1 REQ_OVRD_VAL 2 2 REQ_OVRD_EN 3 3 RX_LOS_THRSHLD_OVRD_VAL 4 6 RX_LOS_THRSHLD_OVRD_EN 7 7 ADAPT_REQ 8 8 ADAPT_REQ_OVRD_EN 9 9 ADAPT_CONT 10 10 OFFCAN_CONT 11 11 CONT_OVRD_EN 12 12 RESERVED_15_13 13 15 ixDPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_2 2 0x3107 4 0 4294967295 VCO_LD_VAL_OVRD 0 12 VCO_LD_VAL_OVRD_EN 13 13 VCO_LOWFREQ_VAL_OVRD 14 14 VCO_LOWFREQ_VAL_OVRD_EN 15 15 ixDPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_3 2 0x3108 3 0 4294967295 REF_LD_VAL_OVRD 0 6 REF_LD_VAL_OVRD_EN 7 7 RESERVED_15_8 8 15 ixDPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_PCS_IN 2 0x3109 13 0 4294967295 REQ 0 0 RATE 1 2 WIDTH 3 4 PSTATE 5 6 LPD 7 7 CDR_VCO_LOWFREQ 8 8 ADAPT_AFE_EN 9 9 ADAPT_DFE_EN 10 10 ADAPT_REQ 11 11 ADAPT_CONT 12 12 OFFCAN_CONT 13 13 RESET 14 14 RESERVED_15_15 15 15 ixDPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_1 2 0x310a 2 0 4294967295 REF_LD_VAL 0 6 RESERVED_15_7 7 15 ixDPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_2 2 0x310b 2 0 4294967295 VCO_LD_VAL 0 12 RESERVED_15_13 13 15 ixDPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_3 2 0x310c 4 0 4294967295 EQ_ATT_LVL 0 2 EQ_VGA1_GAIN 3 6 EQ_VGA2_GAIN 7 10 EQ_CTLE_BOOST 11 15 ixDPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_4 2 0x310d 3 0 4294967295 EQ_CTLE_POLE 0 2 EQ_DFE_TAP1 3 10 RESERVED_15_11 11 15 ixDPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT 2 0x310e 3 0 4294967295 ACK 0 0 EN_CTL 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_PCS_OUT 2 0x310f 2 0 4294967295 ACK 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_ADAPT_ACK 2 0x3110 2 0 4294967295 RX_ADAPT_ACK 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_ADAPT_FOM 2 0x3111 2 0 4294967295 RX_ADAPT_FOM 0 7 RESERVED_15_8 8 15 ixDPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_TXPRE_DIR 2 0x3112 2 0 4294967295 RX_TXPRE_DIR 0 1 RESERVED_15_2 2 15 ixDPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_TXMAIN_DIR 2 0x3113 2 0 4294967295 RX_TXMAIN_DIR 0 1 RESERVED_15_2 2 15 ixDPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_TXPOST_DIR 2 0x3114 2 0 4294967295 RX_TXPOST_DIR 0 1 RESERVED_15_2 2 15 ixDPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_LANE_NUMBER 2 0x3115 2 0 4294967295 LANE_NUMBER 0 3 RESERVED_15_4 4 15 ixDPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RESERVED_1 2 0x3116 1 0 4294967295 RESERVED_REG_1 0 15 ixDPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RESERVED_2 2 0x3117 1 0 4294967295 RESERVED_REG_2 0 15 ixDPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN 2 0x3118 16 0 4294967295 RX_RESET_ATE_OVRD_VAL 0 0 RX_RESET_ATE_OVRD_EN 1 1 TX_RESET_ATE_OVRD_VAL 2 2 TX_RESET_ATE_OVRD_EN 3 3 RX_REQ_ATE_OVRD_VAL 4 4 RX_REQ_ATE_OVRD_EN 5 5 TX_REQ_ATE_OVRD_VAL 6 6 TX_REQ_ATE_OVRD_EN 7 7 RX_ADAPT_AFE_EN_OVRD_VAL 8 8 RX_ADAPT_AFE_EN_OVRD_EN 9 9 RX_ADAPT_DFE_EN_OVRD_VAL 10 10 RX_ADAPT_DFE_EN_OVRD_EN 11 11 TX_DATA_EN_ATE_OVRD_VAL 12 12 TX_DATA_EN_ATE_OVRD_EN 13 13 RX_DATA_EN_ATE_OVRD_VAL 14 14 RX_DATA_EN_ATE_OVRD_EN 15 15 ixDPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN 2 0x3119 3 0 4294967295 RX_EQ_DELTA_IQ_OVRD_VAL 0 3 RX_EQ_DELTA_IQ_OVRD_EN 4 4 RESERVED_15_5 5 15 ixDPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN 2 0x311a 5 0 4294967295 RX_TERM_CTRL_OVRD_VAL 0 2 RX_TERM_CTRL_OVRD_EN 3 3 TX_TERM_CTRL_OVRD_VAL 4 6 TX_TERM_CTRL_OVRD_EN 7 7 RESERVED_15_8 8 15 ixDPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TXRX_TERM_CTRL_IN 2 0x311b 3 0 4294967295 RX_TERM_CTRL 0 2 TX_TERM_CTRL 3 5 RESERVED_15_6 6 15 ixDPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT_1 2 0x311c 2 0 4294967295 RX_CLK_EN 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_EQ_OVRD_IN_1 2 0x311d 4 0 4294967295 RX_EQ_AFE_GAIN_OVRD_VAL 0 3 RX_EQ_ATT_LVL_OVRD_VAL 4 6 RX_EQ_OVRD_EN 7 7 RESERVED_15_8 8 15 ixDPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_EQ_OVRD_IN_2 2 0x311e 3 0 4294967295 RX_EQ_DFE_TAP1_OVRD_VAL 0 7 RX_EQ_CTLE_BOOST_OVRD_VAL 8 12 RESERVED_15_13 13 15 ixDPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_PH2_CAL 2 0x311f 4 0 4294967295 PH2_CAL_ACK_VAL 0 0 PH2_CAL_REQ_VAL 1 1 PH2_CAL_REQ_OVRD_VAL 2 2 RESERVED_15_3 3 15 ixDPCSSYS_CR3_RAWLANE1_DIG_FSM_FSM_OVRD_CTL 2 0x3120 5 0 4294967295 FSM_JMP_ADDR 0 11 FSM_JMP_EN 12 12 FSM_CMD_START 13 13 FSM_OVRD_EN 14 14 FSM_BREAK 15 15 ixDPCSSYS_CR3_RAWLANE1_DIG_FSM_MEM_ADDR_MON 2 0x3121 1 0 4294967295 MEM_ADDR 0 15 ixDPCSSYS_CR3_RAWLANE1_DIG_FSM_STATUS_MON 2 0x3122 8 0 4294967295 STATE 0 4 CMD_RDY 5 5 ALU_OVFLW 6 6 ALU_RES_EQ0 7 7 WAIT_CNT_EQ0 8 8 WRMSK_DISABLED 9 9 RDMSK_DISABLED 10 10 RESERVED_15_11 11 15 ixDPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_RX_STARTUP_CAL 2 0x3123 2 0 4294967295 FAST_RX_STARTUP_CAL 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_RX_ADAPT 2 0x3124 2 0 4294967295 FAST_RX_ADAPT 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_RX_AFE_CAL 2 0x3125 2 0 4294967295 FAST_RX_AFE_CAL 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_RX_DFE_CAL 2 0x3126 2 0 4294967295 FAST_RX_DFE_CAL 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_RX_BYPASS_CAL 2 0x3127 2 0 4294967295 FAST_RX_BYPASS_CAL 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_RX_REFLVL_CAL 2 0x3128 2 0 4294967295 FAST_RX_REFLVL_CAL 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_RX_IQ_CAL 2 0x3129 2 0 4294967295 FAST_RX_IQ_CAL 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_RX_AFE_ADAPT 2 0x312a 2 0 4294967295 FAST_RX_AFE_ADAPT 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_RX_DFE_ADAPT 2 0x312b 2 0 4294967295 FAST_RX_DFE_ADAPT 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_SUP 2 0x312c 2 0 4294967295 FAST_SUP 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_TX_CMN_MODE 2 0x312d 2 0 4294967295 FAST_TX_CMN_MODE 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_TX_RXDET 2 0x312e 2 0 4294967295 FAST_TX_RXDET 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_RX_PWRUP 2 0x312f 2 0 4294967295 FAST_RX_PWRUP 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_RX_VCO_WAIT 2 0x3130 2 0 4294967295 FAST_RX_VCO_WAIT 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_RX_VCO_CAL 2 0x3131 2 0 4294967295 FAST_RX_VCO_CAL 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR3_RAWLANE1_DIG_FSM_CMNCAL_MPLL_STATUS 2 0x3132 3 0 4294967295 CMNCAL_MPLL_INIT 0 0 CMNCAL_MPLL_DONE 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_RX_CONT_CAL_ADAPT 2 0x3133 2 0 4294967295 FAST_RX_CONT_CAL_ADAPT 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_RX_CONT_ADAPT 2 0x3134 2 0 4294967295 FAST_RX_CONT_ADAPT 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_RX_CONT_DATA_CAL 2 0x3135 2 0 4294967295 FAST_RX_CONT_DATA_CAL 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_RX_CONT_PHASE_CAL 2 0x3136 2 0 4294967295 FAST_RX_CONT_PHASE_CAL 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_RX_CONT_AFE_CAL 2 0x3137 2 0 4294967295 FAST_RX_CONT_AFE_CAL 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_FLAGS 2 0x3138 12 0 4294967295 TX_FAST_DCC_CAL 0 0 RX_FAST_DCC_CAL 1 1 RX_FAST_VPHUD_CAL 2 2 RX_FAST_VREF_CAL 3 3 RX_FAST_SIGDET_CAL 4 4 RESERVED_2 5 7 TX_FAST_CONT_DCC_CAL 8 8 RX_FAST_CONT_DCC_CAL 9 9 RX_FAST_CONT_VPHUD_CAL 10 10 RX_FAST_CONT_VREF_CAL 11 11 RESERVED_1 12 14 TX_SKIP_SUP_CAL 15 15 ixDPCSSYS_CR3_RAWLANE1_DIG_FSM_CR_LOCK 2 0x3139 3 0 4294967295 CR_REG_LOCK 0 0 CR_MEM_LOCK 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR3_RAWLANE1_DIG_FSM_TX_DCC_FLAGS 2 0x313a 4 0 4294967295 RATE 0 0 DIV 1 1 MPLL 2 2 RESERVED_15_3 3 15 ixDPCSSYS_CR3_RAWLANE1_DIG_FSM_TX_DCC_STATUS 2 0x313b 2 0 4294967295 FLAG 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR3_RAWLANE1_DIG_FSM_OCLA 2 0x313c 4 0 4294967295 PC_EN 0 0 REG_BANK1_EN 1 1 REG_BANK2_EN 2 2 RESERVED_15_3 3 15 ixDPCSSYS_CR3_RAWLANE1_DIG_FSM_TX_EQ_UPDATE_FLAG 2 0x313d 2 0 4294967295 TX_EQ_UPDATE_FLAG 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR3_RAWLANE1_DIG_FSM_CMNCAL_RCAL_STATUS 2 0x313e 3 0 4294967295 CMNCAL_RCAL_INIT 0 0 CMNCAL_RCAL_DONE 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR3_RAWLANE1_DIG_FSM_RX_IQ_PHASE_OFFSET 2 0x313f 2 0 4294967295 RX_IQ_PHASE_OFFSET 0 3 RESERVED_15_4 4 15 ixDPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_RESET_RTN_REQ 2 0x3140 2 0 4294967295 RESET_RTN_REQ 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_RX_RESET_IRQ 2 0x3141 2 0 4294967295 RX_RESET 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_RX_REQ_IRQ 2 0x3142 2 0 4294967295 RX_REQ 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_RX_RATE_IRQ 2 0x3143 2 0 4294967295 RX_RATE_IRQ 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_RX_PSTATE_IRQ 2 0x3144 2 0 4294967295 RX_PSTATE_IRQ 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ 2 0x3145 2 0 4294967295 RX_ADAPT_REQ_IRQ 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ 2 0x3146 2 0 4294967295 RX_ADAPT_DIS_IRQ 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_RX_RESET_IRQ_CLR 2 0x3147 2 0 4294967295 RX_RESET_IRQ_CLR 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_RX_REQ_IRQ_CLR 2 0x3148 2 0 4294967295 RX_REQ_IRQ_CLR 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_RX_RATE_IRQ_CLR 2 0x3149 2 0 4294967295 RX_RATE_IRQ_CLR 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR 2 0x314a 2 0 4294967295 RX_PSTATE_IRQ_CLR 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR 2 0x314b 2 0 4294967295 RX_ADAPT_REQ_IRQ_CLR 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR 2 0x314c 2 0 4294967295 RX_ADAPT_DIS_IRQ_CLR 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK 2 0x314d 12 0 4294967295 RX_REQ_IRQ_MSK 0 0 RX_RATE_IRQ_MSK 1 1 RX_PSTATE_IRQ_MSK 2 2 RX_ADAPT_REQ_IRQ_MSK 3 3 RX_ADAPT_DIS_IRQ_MSK 4 4 RX_RESET_IRQ_MSK 5 5 LANE_XCVR_MODE_IRQ_MSK 6 6 RX_PH2_CAL_REQ_IRQ_MSK 7 7 RX_PH2_CAL_DIS_IRQ_MSK 8 8 LANE_RX2TX_SER_LB_EN_IRQ_MSK 9 9 DCC_ONDMD_IRQ_MSK 10 10 RESERVED_15_11 11 15 ixDPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK_2 2 0x314e 3 0 4294967295 TX_RESET_IRQ_MSK 0 0 TX_REQ_IRQ_MSK 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ 2 0x314f 2 0 4294967295 LANE_XCVR_MODE_IRQ 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR 2 0x3150 2 0 4294967295 LANE_XCVR_MODE_IRQ_CLR 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ 2 0x3151 2 0 4294967295 RX_PH2_CAL_REQ_IRQ 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ 2 0x3152 2 0 4294967295 RX_PH2_CAL_DIS_IRQ 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR 2 0x3153 2 0 4294967295 RX_PH2_CAL_REQ_IRQ_CLR 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR 2 0x3154 2 0 4294967295 RX_PH2_CAL_DIS_IRQ_CLR 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ 2 0x3155 2 0 4294967295 LANE_RX2TX_SER_LB_EN_IRQ 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR 2 0x3156 2 0 4294967295 LANE_RX2TX_SER_LB_EN_IRQ_CLR 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_DCC_ONDMD_IRQ 2 0x3157 2 0 4294967295 IRQ 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_TX_RESET_IRQ 2 0x3158 2 0 4294967295 TX_RESET 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_TX_REQ_IRQ 2 0x3159 2 0 4294967295 TX_REQ 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_TX_RESET_IRQ_CLR 2 0x315a 2 0 4294967295 TX_RESET_IRQ_CLR 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_TX_REQ_IRQ_CLR 2 0x315b 2 0 4294967295 TX_REQ_IRQ_CLR 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_LANE_OVRD_IN 2 0x3160 4 0 4294967295 LANE_MPLLA_EN_IN 0 0 LANE_MPLLB_EN_IN 1 1 LANE_OVRD_EN 2 2 RESERVED_15_3 3 15 ixDPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_LANE_OVRD_OUT 2 0x3161 4 0 4294967295 LANE_MPLLA_EN_OUT 0 0 LANE_MPLLB_EN_OUT 1 1 LANE_OVRD_EN 2 2 RESERVED_15_3 3 15 ixDPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_SUP_OVRD_IN 2 0x3162 4 0 4294967295 MPLLA_STATE 0 0 MPLLB_STATE 1 1 SUP_STATE_OVRD_EN 2 2 RESERVED_15_3 3 15 ixDPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_SUP_PMA_IN 2 0x3163 3 0 4294967295 MPLLA_STATE 0 0 MPLLB_STATE 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT 2 0x3164 16 0 4294967295 TX_REQ_OVRD_VAL 0 0 TX_REQ_OVRD_EN 1 1 TX_RESET_OVRD_VAL 2 2 TX_RESET_OVRD_EN 3 3 TX_BEACON_EN_OVRD_VAL 4 4 TX_BEACON_EN_OVRD_EN 5 5 TX_ASYNC_DRV_EN_OVRD_VAL 6 6 TX_ASYNC_DRV_EN_OVRD_EN 7 7 TX_ASYNC_EN_OVRD_VAL 8 8 TX_ASYNC_EN_OVRD_EN 9 9 TX_DWORD_CLK_SYNC_OVRD_VAL 10 10 TX_DWORD_CLK_SYNC_OVRD_EN 11 11 LANE_TX2RX_SER_LB_EN_OVRD_VAL 12 12 LANE_TX2RX_SER_LB_EN_OVRD_EN 13 13 TX_PMA_DATA_EN_OVRD_VAL_R 14 14 TX_PMA_DATA_EN_OVRD_EN_R 15 15 ixDPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_TX_PMA_IN 2 0x3165 2 0 4294967295 ACK 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT 2 0x3166 9 0 4294967295 RX_REQ_OVRD_VAL 0 0 RX_REQ_OVRD_EN 1 1 RX_RESET_OVRD_VAL 2 2 RX_RESET_OVRD_EN 3 3 LANE_RX2TX_PAR_LB_EN_OVRD_VAL 4 4 LANE_RX2TX_PAR_LB_EN_OVRD_EN 5 5 RX_PMA_DATA_EN_OVRD_VAL_R 6 6 RX_PMA_DATA_EN_OVRD_EN_R 7 7 RESERVED_15_8 8 15 ixDPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_RX_PMA_IN 2 0x3167 2 0 4294967295 ACK 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_LANE_RTUNE_CTL 2 0x3168 2 0 4294967295 LANE_RTUNE_REQ 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_SUP_PMA_IN_1 2 0x3169 2 0 4294967295 RTUNE_ACK 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_IN 2 0x316a 9 0 4294967295 RX_PMA_PWM_WORD_CLK_R 0 0 RX_PMA_PWM_WORD_CLK_OVRD_EN 1 1 RX_PMA_PWM_DATA_R 2 2 RX_PMA_PWM_DATA_OVRD_EN 3 3 RX_PMA_PWM_CLK_R 4 4 RX_PMA_PWM_CLK_OVRD_EN 5 5 RX_PMA_TERM_CTL_R 6 7 RX_PMA_TERM_CTL_OVRD_EN 8 8 RESERVED_15_9 9 15 ixDPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_OUT 2 0x316b 7 0 4294967295 RX_PMA_PWM_EN 0 0 RX_PMA_PWM_EN_OVRD_EN 1 1 RX_PMA_PWM_CLK_SEL 2 3 RX_PMA_PWM_CLK_SEL_OVRD_EN 4 4 RX_PMA_ASYNC_EN 5 5 RX_PMA_ASYNC_EN_OVRD_EN 6 6 RESERVED_15_7 7 15 ixDPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_RX_ADAPT_OVRD_OUT 2 0x316c 3 0 4294967295 RX_PMA_IQ_PHASE_ADJUST_MAP_OVRD_VAL 0 6 RX_PMA_IQ_PHASE_ADJUST_MAP_OVRD_EN 7 7 RESERVED_15_8 8 15 ixDPCSSYS_CR3_RAWLANE1_DIG_TX_CTL_TX_FSM_CTL 2 0x3180 6 0 4294967295 TX_WAIT_MPLL_OFF_TIME 0 6 TX_P2_ALLOW_RXDET 7 7 TX_P1_ALLOW_RXDET 8 8 TX_P0S_ALLOW_RXDET 9 9 TX_P0_ALLOW_RXDET 10 10 RESERVED_15_11 11 15 ixDPCSSYS_CR3_RAWLANE1_DIG_TX_CTL_TX_CLK_CTL 2 0x3181 4 0 4294967295 TX_CLK_EN 0 0 TX_CLK_SEL 1 4 ASYNC_BEACON_WAIT_TIME 5 10 RESERVED_15_11 11 15 ixDPCSSYS_CR3_RAWLANE1_DIG_TX_CTL_TX_DCC_CONT_STATUS 2 0x3182 2 0 4294967295 ENABLE 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR3_RAWLANE1_DIG_TX_CTL_OCLA 2 0x3183 2 0 4294967295 FSM_EN 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR3_RAWLANE1_DIG_TX_CTL_UPCS_OCLA 2 0x3184 3 0 4294967295 DATA_EN 0 1 CLK_EN 2 2 RESERVED_15_3 3 15 ixDPCSSYS_CR3_RAWLANE1_DIG_RX_CTL_RX_FSM_CTL 2 0x31a0 3 0 4294967295 EN_RX_CTL_FSM 0 0 RATE_CHG_IN_P1 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR3_RAWLANE1_DIG_RX_CTL_RX_LOS_MASK_CTL 2 0x31a1 2 0 4294967295 RX_LOS_MASK_CNT 0 8 RESERVED_15_9 9 15 ixDPCSSYS_CR3_RAWLANE1_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL 2 0x31a2 2 0 4294967295 RX_DATA_EN_OVRD_CNT 0 4 INT_REF_TRCK_CNT 5 15 ixDPCSSYS_CR3_RAWLANE1_DIG_RX_CTL_OFFCAN_CONT_STATUS 2 0x31a3 2 0 4294967295 ENABLE 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR3_RAWLANE1_DIG_RX_CTL_ADAPT_CONT_STATUS 2 0x31a4 2 0 4294967295 ENABLE 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR3_RAWLANE1_DIG_RX_CTL_UPCS_OCLA 2 0x31a5 3 0 4294967295 DATA_EN 0 2 CLK_EN 3 3 RESERVED_15_4 4 15 ixDPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN 2 0x31c0 11 0 4294967295 RATE_OVRD_VAL 0 1 RATE_OVRD_EN 2 2 WIDTH_OVRD_VAL 3 4 WIDTH_OVRD_EN 5 5 PSTATE_OVRD_VAL 6 7 PSTATE_OVRD_EN 8 8 LPD_OVRD_VAL 9 9 LPD_OVRD_EN 10 10 LANE_RX2TX_PAR_LB_EN_OVRD_VAL 11 11 LANE_RX2TX_PAR_LB_EN_OVRD_EN 12 12 RESERVED_15_13 13 15 ixDPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN 2 0x31c1 12 0 4294967295 PSTATE 0 1 LPD 2 2 WIDTH 3 4 RATE 5 7 MPLLB_SEL 8 8 MPLL_EN 9 9 OVRD_EN 10 10 MSTR_MPLLA_STATE 11 11 MSTR_MPLLB_STATE 12 12 MSTR_MPLL_OVRD_EN 13 13 TX_ASYNC_EN_OVR_VAL 14 14 TX_ASYNC_EN_OVR_EN 15 15 ixDPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1 2 0x31c2 13 0 4294967295 DETRX_REQ_OVRD_VAL 0 0 DETRX_REQ_OVRD_EN 1 1 VBOOST_EN_OVRD_VAL 2 2 VBOOST_EN_OVRD_EN 3 3 IBOOST_LVL_OVRD_VAL 4 7 IBOOST_LVL_OVRD_EN 8 8 TX_BEACON_EN_OVR_VAL 9 9 TX_BEACON_EN_OVR_EN 10 10 LANE_TX2RX_SER_LB_EN_OVRD_VAL 11 11 LANE_TX2RX_SER_LB_EN_OVRD_EN 12 12 TX_ASYNC_DATA_OVRD_VAL 13 13 TX_ASYNC_DATA_OVRD_EN 14 14 RESERVED_15_15 15 15 ixDPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_MASTER_MPLL_LOOP 2 0x31c3 3 0 4294967295 MPLLB_LOOP_EN 0 0 MPLLA_LOOP_EN 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1 2 0x31c4 11 0 4294967295 RESERVED 0 1 RX_LOS_LFPS_EN_OVRD_VAL 2 2 RX_LOS_LFPS_EN_OVRD_EN 3 3 RX_LOS_THRSHLD_OVRD_VAL 4 6 RX_LOS_THRSHLD_OVRD_EN 7 7 ADAPT_REQ 8 8 ADAPT_REQ_OVRD_EN 9 9 ADAPT_CONT 10 10 OFFCAN_CONT 11 11 CONT_OVRD_EN 12 12 RESERVED_15_13 13 15 ixDPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_2 2 0x31c5 4 0 4294967295 VCO_LD_VAL_OVRD 0 12 VCO_LD_VAL_OVRD_EN 13 13 VCO_LOWFREQ_VAL_OVRD 14 14 VCO_LOWFREQ_VAL_OVRD_EN 15 15 ixDPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_3 2 0x31c6 3 0 4294967295 REF_LD_VAL_OVRD 0 6 REF_LD_VAL_OVRD_EN 7 7 RESERVED_15_8 8 15 ixDPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT_2 2 0x31c7 3 0 4294967295 RX_VALID 0 0 RX_VALID_OVRD_EN 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_2 2 0x31c8 7 0 4294967295 LANE_TX2RX_SER_LB_EN_OVRD_VAL 0 0 LANE_TX2RX_SER_LB_EN_OVRD_EN 1 1 TX_DATA_EN_OVRD_VAL_R 2 2 TX_DATA_EN_OVRD_EN_R 3 3 TX_ASYNC_DATA_OVRD_VAL_R 4 4 TX_ASYNC_DATA_OVRD_EN_R 5 5 RESERVED_15_6 6 15 ixDPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN 2 0x3200 12 0 4294967295 PSTATE 0 1 LPD 2 2 WIDTH 3 4 RATE 5 7 MPLLB_SEL 8 8 MPLL_EN 9 9 OVRD_EN 10 10 MSTR_MPLLA_STATE 11 11 MSTR_MPLLB_STATE 12 12 MSTR_MPLL_OVRD_EN 13 13 TX_ASYNC_EN_OVR_VAL 14 14 TX_ASYNC_EN_OVR_EN 15 15 ixDPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1 2 0x3201 13 0 4294967295 RESET_OVRD_VAL 0 0 RESET_OVRD_EN 1 1 REQ_OVRD_VAL 2 2 REQ_OVRD_EN 3 3 DETRX_REQ_OVRD_VAL 4 4 DETRX_REQ_OVRD_EN 5 5 VBOOST_EN_OVRD_VAL 6 6 VBOOST_EN_OVRD_EN 7 7 IBOOST_LVL_OVRD_VAL 8 11 IBOOST_LVL_OVRD_EN 12 12 TX_BEACON_EN_OVR_VAL 13 13 TX_BEACON_EN_OVR_EN 14 14 RESERVED_15_15 15 15 ixDPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_PCS_IN 2 0x3202 12 0 4294967295 RESET 0 0 REQ 1 1 PSTATE 2 3 LPD 4 4 WIDTH 5 6 RATE 7 9 MPLLB_SEL 10 10 MPLL_EN 11 11 MSTR_MPLLA_STATE 12 12 MSTR_MPLLB_STATE 13 13 DETRX_REQ 14 14 RESERVED_15_15 15 15 ixDPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_OVRD_OUT 2 0x3203 6 0 4294967295 ACK 0 0 DETRX_RESULT 1 1 EN_CTL 2 2 TX_DWORD_CLK_SYNC_OVRD_VAL 3 3 TX_DWORD_CLK_SYNC_OVRD_EN 4 4 RESERVED_15_5 5 15 ixDPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_PCS_OUT 2 0x3204 2 0 4294967295 ACK 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN 2 0x3205 12 0 4294967295 RATE 0 1 WIDTH 2 3 PSTATE 4 5 LPD 6 6 OVRD_EN 7 7 ADAPT_AFE_EN 8 8 ADAPT_DFE_EN 9 9 LANE_RX2TX_PAR_LB_EN_OVRD_VAL 10 10 LANE_RX2TX_PAR_LB_EN_OVRD_EN 11 11 RX_DATA_EN_OVRD_VAL_R 12 12 RX_DATA_EN_OVRD_EN_R 13 13 RESERVED_15_14 14 15 ixDPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1 2 0x3206 12 0 4294967295 RESET_OVRD_VAL 0 0 RESET_OVRD_EN 1 1 REQ_OVRD_VAL 2 2 REQ_OVRD_EN 3 3 RX_LOS_THRSHLD_OVRD_VAL 4 6 RX_LOS_THRSHLD_OVRD_EN 7 7 ADAPT_REQ 8 8 ADAPT_REQ_OVRD_EN 9 9 ADAPT_CONT 10 10 OFFCAN_CONT 11 11 CONT_OVRD_EN 12 12 RESERVED_15_13 13 15 ixDPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_2 2 0x3207 4 0 4294967295 VCO_LD_VAL_OVRD 0 12 VCO_LD_VAL_OVRD_EN 13 13 VCO_LOWFREQ_VAL_OVRD 14 14 VCO_LOWFREQ_VAL_OVRD_EN 15 15 ixDPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_3 2 0x3208 3 0 4294967295 REF_LD_VAL_OVRD 0 6 REF_LD_VAL_OVRD_EN 7 7 RESERVED_15_8 8 15 ixDPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_PCS_IN 2 0x3209 13 0 4294967295 REQ 0 0 RATE 1 2 WIDTH 3 4 PSTATE 5 6 LPD 7 7 CDR_VCO_LOWFREQ 8 8 ADAPT_AFE_EN 9 9 ADAPT_DFE_EN 10 10 ADAPT_REQ 11 11 ADAPT_CONT 12 12 OFFCAN_CONT 13 13 RESET 14 14 RESERVED_15_15 15 15 ixDPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_1 2 0x320a 2 0 4294967295 REF_LD_VAL 0 6 RESERVED_15_7 7 15 ixDPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_2 2 0x320b 2 0 4294967295 VCO_LD_VAL 0 12 RESERVED_15_13 13 15 ixDPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_3 2 0x320c 4 0 4294967295 EQ_ATT_LVL 0 2 EQ_VGA1_GAIN 3 6 EQ_VGA2_GAIN 7 10 EQ_CTLE_BOOST 11 15 ixDPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_4 2 0x320d 3 0 4294967295 EQ_CTLE_POLE 0 2 EQ_DFE_TAP1 3 10 RESERVED_15_11 11 15 ixDPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT 2 0x320e 3 0 4294967295 ACK 0 0 EN_CTL 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_PCS_OUT 2 0x320f 2 0 4294967295 ACK 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_ADAPT_ACK 2 0x3210 2 0 4294967295 RX_ADAPT_ACK 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_ADAPT_FOM 2 0x3211 2 0 4294967295 RX_ADAPT_FOM 0 7 RESERVED_15_8 8 15 ixDPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_TXPRE_DIR 2 0x3212 2 0 4294967295 RX_TXPRE_DIR 0 1 RESERVED_15_2 2 15 ixDPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_TXMAIN_DIR 2 0x3213 2 0 4294967295 RX_TXMAIN_DIR 0 1 RESERVED_15_2 2 15 ixDPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_TXPOST_DIR 2 0x3214 2 0 4294967295 RX_TXPOST_DIR 0 1 RESERVED_15_2 2 15 ixDPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_LANE_NUMBER 2 0x3215 2 0 4294967295 LANE_NUMBER 0 3 RESERVED_15_4 4 15 ixDPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RESERVED_1 2 0x3216 1 0 4294967295 RESERVED_REG_1 0 15 ixDPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RESERVED_2 2 0x3217 1 0 4294967295 RESERVED_REG_2 0 15 ixDPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN 2 0x3218 16 0 4294967295 RX_RESET_ATE_OVRD_VAL 0 0 RX_RESET_ATE_OVRD_EN 1 1 TX_RESET_ATE_OVRD_VAL 2 2 TX_RESET_ATE_OVRD_EN 3 3 RX_REQ_ATE_OVRD_VAL 4 4 RX_REQ_ATE_OVRD_EN 5 5 TX_REQ_ATE_OVRD_VAL 6 6 TX_REQ_ATE_OVRD_EN 7 7 RX_ADAPT_AFE_EN_OVRD_VAL 8 8 RX_ADAPT_AFE_EN_OVRD_EN 9 9 RX_ADAPT_DFE_EN_OVRD_VAL 10 10 RX_ADAPT_DFE_EN_OVRD_EN 11 11 TX_DATA_EN_ATE_OVRD_VAL 12 12 TX_DATA_EN_ATE_OVRD_EN 13 13 RX_DATA_EN_ATE_OVRD_VAL 14 14 RX_DATA_EN_ATE_OVRD_EN 15 15 ixDPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN 2 0x3219 3 0 4294967295 RX_EQ_DELTA_IQ_OVRD_VAL 0 3 RX_EQ_DELTA_IQ_OVRD_EN 4 4 RESERVED_15_5 5 15 ixDPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN 2 0x321a 5 0 4294967295 RX_TERM_CTRL_OVRD_VAL 0 2 RX_TERM_CTRL_OVRD_EN 3 3 TX_TERM_CTRL_OVRD_VAL 4 6 TX_TERM_CTRL_OVRD_EN 7 7 RESERVED_15_8 8 15 ixDPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TXRX_TERM_CTRL_IN 2 0x321b 3 0 4294967295 RX_TERM_CTRL 0 2 TX_TERM_CTRL 3 5 RESERVED_15_6 6 15 ixDPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT_1 2 0x321c 2 0 4294967295 RX_CLK_EN 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_EQ_OVRD_IN_1 2 0x321d 4 0 4294967295 RX_EQ_AFE_GAIN_OVRD_VAL 0 3 RX_EQ_ATT_LVL_OVRD_VAL 4 6 RX_EQ_OVRD_EN 7 7 RESERVED_15_8 8 15 ixDPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_EQ_OVRD_IN_2 2 0x321e 3 0 4294967295 RX_EQ_DFE_TAP1_OVRD_VAL 0 7 RX_EQ_CTLE_BOOST_OVRD_VAL 8 12 RESERVED_15_13 13 15 ixDPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_PH2_CAL 2 0x321f 4 0 4294967295 PH2_CAL_ACK_VAL 0 0 PH2_CAL_REQ_VAL 1 1 PH2_CAL_REQ_OVRD_VAL 2 2 RESERVED_15_3 3 15 ixDPCSSYS_CR3_RAWLANE2_DIG_FSM_FSM_OVRD_CTL 2 0x3220 5 0 4294967295 FSM_JMP_ADDR 0 11 FSM_JMP_EN 12 12 FSM_CMD_START 13 13 FSM_OVRD_EN 14 14 FSM_BREAK 15 15 ixDPCSSYS_CR3_RAWLANE2_DIG_FSM_MEM_ADDR_MON 2 0x3221 1 0 4294967295 MEM_ADDR 0 15 ixDPCSSYS_CR3_RAWLANE2_DIG_FSM_STATUS_MON 2 0x3222 8 0 4294967295 STATE 0 4 CMD_RDY 5 5 ALU_OVFLW 6 6 ALU_RES_EQ0 7 7 WAIT_CNT_EQ0 8 8 WRMSK_DISABLED 9 9 RDMSK_DISABLED 10 10 RESERVED_15_11 11 15 ixDPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_RX_STARTUP_CAL 2 0x3223 2 0 4294967295 FAST_RX_STARTUP_CAL 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_RX_ADAPT 2 0x3224 2 0 4294967295 FAST_RX_ADAPT 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_RX_AFE_CAL 2 0x3225 2 0 4294967295 FAST_RX_AFE_CAL 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_RX_DFE_CAL 2 0x3226 2 0 4294967295 FAST_RX_DFE_CAL 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_RX_BYPASS_CAL 2 0x3227 2 0 4294967295 FAST_RX_BYPASS_CAL 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_RX_REFLVL_CAL 2 0x3228 2 0 4294967295 FAST_RX_REFLVL_CAL 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_RX_IQ_CAL 2 0x3229 2 0 4294967295 FAST_RX_IQ_CAL 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_RX_AFE_ADAPT 2 0x322a 2 0 4294967295 FAST_RX_AFE_ADAPT 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_RX_DFE_ADAPT 2 0x322b 2 0 4294967295 FAST_RX_DFE_ADAPT 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_SUP 2 0x322c 2 0 4294967295 FAST_SUP 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_TX_CMN_MODE 2 0x322d 2 0 4294967295 FAST_TX_CMN_MODE 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_TX_RXDET 2 0x322e 2 0 4294967295 FAST_TX_RXDET 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_RX_PWRUP 2 0x322f 2 0 4294967295 FAST_RX_PWRUP 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_RX_VCO_WAIT 2 0x3230 2 0 4294967295 FAST_RX_VCO_WAIT 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_RX_VCO_CAL 2 0x3231 2 0 4294967295 FAST_RX_VCO_CAL 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR3_RAWLANE2_DIG_FSM_CMNCAL_MPLL_STATUS 2 0x3232 3 0 4294967295 CMNCAL_MPLL_INIT 0 0 CMNCAL_MPLL_DONE 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_RX_CONT_CAL_ADAPT 2 0x3233 2 0 4294967295 FAST_RX_CONT_CAL_ADAPT 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_RX_CONT_ADAPT 2 0x3234 2 0 4294967295 FAST_RX_CONT_ADAPT 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_RX_CONT_DATA_CAL 2 0x3235 2 0 4294967295 FAST_RX_CONT_DATA_CAL 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_RX_CONT_PHASE_CAL 2 0x3236 2 0 4294967295 FAST_RX_CONT_PHASE_CAL 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_RX_CONT_AFE_CAL 2 0x3237 2 0 4294967295 FAST_RX_CONT_AFE_CAL 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_FLAGS 2 0x3238 12 0 4294967295 TX_FAST_DCC_CAL 0 0 RX_FAST_DCC_CAL 1 1 RX_FAST_VPHUD_CAL 2 2 RX_FAST_VREF_CAL 3 3 RX_FAST_SIGDET_CAL 4 4 RESERVED_2 5 7 TX_FAST_CONT_DCC_CAL 8 8 RX_FAST_CONT_DCC_CAL 9 9 RX_FAST_CONT_VPHUD_CAL 10 10 RX_FAST_CONT_VREF_CAL 11 11 RESERVED_1 12 14 TX_SKIP_SUP_CAL 15 15 ixDPCSSYS_CR3_RAWLANE2_DIG_FSM_CR_LOCK 2 0x3239 3 0 4294967295 CR_REG_LOCK 0 0 CR_MEM_LOCK 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR3_RAWLANE2_DIG_FSM_TX_DCC_FLAGS 2 0x323a 4 0 4294967295 RATE 0 0 DIV 1 1 MPLL 2 2 RESERVED_15_3 3 15 ixDPCSSYS_CR3_RAWLANE2_DIG_FSM_TX_DCC_STATUS 2 0x323b 2 0 4294967295 FLAG 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR3_RAWLANE2_DIG_FSM_OCLA 2 0x323c 4 0 4294967295 PC_EN 0 0 REG_BANK1_EN 1 1 REG_BANK2_EN 2 2 RESERVED_15_3 3 15 ixDPCSSYS_CR3_RAWLANE2_DIG_FSM_TX_EQ_UPDATE_FLAG 2 0x323d 2 0 4294967295 TX_EQ_UPDATE_FLAG 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR3_RAWLANE2_DIG_FSM_CMNCAL_RCAL_STATUS 2 0x323e 3 0 4294967295 CMNCAL_RCAL_INIT 0 0 CMNCAL_RCAL_DONE 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR3_RAWLANE2_DIG_FSM_RX_IQ_PHASE_OFFSET 2 0x323f 2 0 4294967295 RX_IQ_PHASE_OFFSET 0 3 RESERVED_15_4 4 15 ixDPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_RESET_RTN_REQ 2 0x3240 2 0 4294967295 RESET_RTN_REQ 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_RX_RESET_IRQ 2 0x3241 2 0 4294967295 RX_RESET 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_RX_REQ_IRQ 2 0x3242 2 0 4294967295 RX_REQ 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_RX_RATE_IRQ 2 0x3243 2 0 4294967295 RX_RATE_IRQ 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_RX_PSTATE_IRQ 2 0x3244 2 0 4294967295 RX_PSTATE_IRQ 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ 2 0x3245 2 0 4294967295 RX_ADAPT_REQ_IRQ 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ 2 0x3246 2 0 4294967295 RX_ADAPT_DIS_IRQ 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_RX_RESET_IRQ_CLR 2 0x3247 2 0 4294967295 RX_RESET_IRQ_CLR 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_RX_REQ_IRQ_CLR 2 0x3248 2 0 4294967295 RX_REQ_IRQ_CLR 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_RX_RATE_IRQ_CLR 2 0x3249 2 0 4294967295 RX_RATE_IRQ_CLR 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR 2 0x324a 2 0 4294967295 RX_PSTATE_IRQ_CLR 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR 2 0x324b 2 0 4294967295 RX_ADAPT_REQ_IRQ_CLR 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR 2 0x324c 2 0 4294967295 RX_ADAPT_DIS_IRQ_CLR 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK 2 0x324d 12 0 4294967295 RX_REQ_IRQ_MSK 0 0 RX_RATE_IRQ_MSK 1 1 RX_PSTATE_IRQ_MSK 2 2 RX_ADAPT_REQ_IRQ_MSK 3 3 RX_ADAPT_DIS_IRQ_MSK 4 4 RX_RESET_IRQ_MSK 5 5 LANE_XCVR_MODE_IRQ_MSK 6 6 RX_PH2_CAL_REQ_IRQ_MSK 7 7 RX_PH2_CAL_DIS_IRQ_MSK 8 8 LANE_RX2TX_SER_LB_EN_IRQ_MSK 9 9 DCC_ONDMD_IRQ_MSK 10 10 RESERVED_15_11 11 15 ixDPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK_2 2 0x324e 3 0 4294967295 TX_RESET_IRQ_MSK 0 0 TX_REQ_IRQ_MSK 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ 2 0x324f 2 0 4294967295 LANE_XCVR_MODE_IRQ 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR 2 0x3250 2 0 4294967295 LANE_XCVR_MODE_IRQ_CLR 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ 2 0x3251 2 0 4294967295 RX_PH2_CAL_REQ_IRQ 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ 2 0x3252 2 0 4294967295 RX_PH2_CAL_DIS_IRQ 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR 2 0x3253 2 0 4294967295 RX_PH2_CAL_REQ_IRQ_CLR 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR 2 0x3254 2 0 4294967295 RX_PH2_CAL_DIS_IRQ_CLR 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ 2 0x3255 2 0 4294967295 LANE_RX2TX_SER_LB_EN_IRQ 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR 2 0x3256 2 0 4294967295 LANE_RX2TX_SER_LB_EN_IRQ_CLR 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_DCC_ONDMD_IRQ 2 0x3257 2 0 4294967295 IRQ 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_TX_RESET_IRQ 2 0x3258 2 0 4294967295 TX_RESET 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_TX_REQ_IRQ 2 0x3259 2 0 4294967295 TX_REQ 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_TX_RESET_IRQ_CLR 2 0x325a 2 0 4294967295 TX_RESET_IRQ_CLR 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_TX_REQ_IRQ_CLR 2 0x325b 2 0 4294967295 TX_REQ_IRQ_CLR 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_LANE_OVRD_IN 2 0x3260 4 0 4294967295 LANE_MPLLA_EN_IN 0 0 LANE_MPLLB_EN_IN 1 1 LANE_OVRD_EN 2 2 RESERVED_15_3 3 15 ixDPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_LANE_OVRD_OUT 2 0x3261 4 0 4294967295 LANE_MPLLA_EN_OUT 0 0 LANE_MPLLB_EN_OUT 1 1 LANE_OVRD_EN 2 2 RESERVED_15_3 3 15 ixDPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_SUP_OVRD_IN 2 0x3262 4 0 4294967295 MPLLA_STATE 0 0 MPLLB_STATE 1 1 SUP_STATE_OVRD_EN 2 2 RESERVED_15_3 3 15 ixDPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_SUP_PMA_IN 2 0x3263 3 0 4294967295 MPLLA_STATE 0 0 MPLLB_STATE 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT 2 0x3264 16 0 4294967295 TX_REQ_OVRD_VAL 0 0 TX_REQ_OVRD_EN 1 1 TX_RESET_OVRD_VAL 2 2 TX_RESET_OVRD_EN 3 3 TX_BEACON_EN_OVRD_VAL 4 4 TX_BEACON_EN_OVRD_EN 5 5 TX_ASYNC_DRV_EN_OVRD_VAL 6 6 TX_ASYNC_DRV_EN_OVRD_EN 7 7 TX_ASYNC_EN_OVRD_VAL 8 8 TX_ASYNC_EN_OVRD_EN 9 9 TX_DWORD_CLK_SYNC_OVRD_VAL 10 10 TX_DWORD_CLK_SYNC_OVRD_EN 11 11 LANE_TX2RX_SER_LB_EN_OVRD_VAL 12 12 LANE_TX2RX_SER_LB_EN_OVRD_EN 13 13 TX_PMA_DATA_EN_OVRD_VAL_R 14 14 TX_PMA_DATA_EN_OVRD_EN_R 15 15 ixDPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_TX_PMA_IN 2 0x3265 2 0 4294967295 ACK 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT 2 0x3266 9 0 4294967295 RX_REQ_OVRD_VAL 0 0 RX_REQ_OVRD_EN 1 1 RX_RESET_OVRD_VAL 2 2 RX_RESET_OVRD_EN 3 3 LANE_RX2TX_PAR_LB_EN_OVRD_VAL 4 4 LANE_RX2TX_PAR_LB_EN_OVRD_EN 5 5 RX_PMA_DATA_EN_OVRD_VAL_R 6 6 RX_PMA_DATA_EN_OVRD_EN_R 7 7 RESERVED_15_8 8 15 ixDPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_RX_PMA_IN 2 0x3267 2 0 4294967295 ACK 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_LANE_RTUNE_CTL 2 0x3268 2 0 4294967295 LANE_RTUNE_REQ 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_SUP_PMA_IN_1 2 0x3269 2 0 4294967295 RTUNE_ACK 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_IN 2 0x326a 9 0 4294967295 RX_PMA_PWM_WORD_CLK_R 0 0 RX_PMA_PWM_WORD_CLK_OVRD_EN 1 1 RX_PMA_PWM_DATA_R 2 2 RX_PMA_PWM_DATA_OVRD_EN 3 3 RX_PMA_PWM_CLK_R 4 4 RX_PMA_PWM_CLK_OVRD_EN 5 5 RX_PMA_TERM_CTL_R 6 7 RX_PMA_TERM_CTL_OVRD_EN 8 8 RESERVED_15_9 9 15 ixDPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_OUT 2 0x326b 7 0 4294967295 RX_PMA_PWM_EN 0 0 RX_PMA_PWM_EN_OVRD_EN 1 1 RX_PMA_PWM_CLK_SEL 2 3 RX_PMA_PWM_CLK_SEL_OVRD_EN 4 4 RX_PMA_ASYNC_EN 5 5 RX_PMA_ASYNC_EN_OVRD_EN 6 6 RESERVED_15_7 7 15 ixDPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_RX_ADAPT_OVRD_OUT 2 0x326c 3 0 4294967295 RX_PMA_IQ_PHASE_ADJUST_MAP_OVRD_VAL 0 6 RX_PMA_IQ_PHASE_ADJUST_MAP_OVRD_EN 7 7 RESERVED_15_8 8 15 ixDPCSSYS_CR3_RAWLANE2_DIG_TX_CTL_TX_FSM_CTL 2 0x3280 6 0 4294967295 TX_WAIT_MPLL_OFF_TIME 0 6 TX_P2_ALLOW_RXDET 7 7 TX_P1_ALLOW_RXDET 8 8 TX_P0S_ALLOW_RXDET 9 9 TX_P0_ALLOW_RXDET 10 10 RESERVED_15_11 11 15 ixDPCSSYS_CR3_RAWLANE2_DIG_TX_CTL_TX_CLK_CTL 2 0x3281 4 0 4294967295 TX_CLK_EN 0 0 TX_CLK_SEL 1 4 ASYNC_BEACON_WAIT_TIME 5 10 RESERVED_15_11 11 15 ixDPCSSYS_CR3_RAWLANE2_DIG_TX_CTL_TX_DCC_CONT_STATUS 2 0x3282 2 0 4294967295 ENABLE 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR3_RAWLANE2_DIG_TX_CTL_OCLA 2 0x3283 2 0 4294967295 FSM_EN 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR3_RAWLANE2_DIG_TX_CTL_UPCS_OCLA 2 0x3284 3 0 4294967295 DATA_EN 0 1 CLK_EN 2 2 RESERVED_15_3 3 15 ixDPCSSYS_CR3_RAWLANE2_DIG_RX_CTL_RX_FSM_CTL 2 0x32a0 3 0 4294967295 EN_RX_CTL_FSM 0 0 RATE_CHG_IN_P1 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR3_RAWLANE2_DIG_RX_CTL_RX_LOS_MASK_CTL 2 0x32a1 2 0 4294967295 RX_LOS_MASK_CNT 0 8 RESERVED_15_9 9 15 ixDPCSSYS_CR3_RAWLANE2_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL 2 0x32a2 2 0 4294967295 RX_DATA_EN_OVRD_CNT 0 4 INT_REF_TRCK_CNT 5 15 ixDPCSSYS_CR3_RAWLANE2_DIG_RX_CTL_OFFCAN_CONT_STATUS 2 0x32a3 2 0 4294967295 ENABLE 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR3_RAWLANE2_DIG_RX_CTL_ADAPT_CONT_STATUS 2 0x32a4 2 0 4294967295 ENABLE 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR3_RAWLANE2_DIG_RX_CTL_UPCS_OCLA 2 0x32a5 3 0 4294967295 DATA_EN 0 2 CLK_EN 3 3 RESERVED_15_4 4 15 ixDPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN 2 0x32c0 11 0 4294967295 RATE_OVRD_VAL 0 1 RATE_OVRD_EN 2 2 WIDTH_OVRD_VAL 3 4 WIDTH_OVRD_EN 5 5 PSTATE_OVRD_VAL 6 7 PSTATE_OVRD_EN 8 8 LPD_OVRD_VAL 9 9 LPD_OVRD_EN 10 10 LANE_RX2TX_PAR_LB_EN_OVRD_VAL 11 11 LANE_RX2TX_PAR_LB_EN_OVRD_EN 12 12 RESERVED_15_13 13 15 ixDPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN 2 0x32c1 12 0 4294967295 PSTATE 0 1 LPD 2 2 WIDTH 3 4 RATE 5 7 MPLLB_SEL 8 8 MPLL_EN 9 9 OVRD_EN 10 10 MSTR_MPLLA_STATE 11 11 MSTR_MPLLB_STATE 12 12 MSTR_MPLL_OVRD_EN 13 13 TX_ASYNC_EN_OVR_VAL 14 14 TX_ASYNC_EN_OVR_EN 15 15 ixDPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1 2 0x32c2 13 0 4294967295 DETRX_REQ_OVRD_VAL 0 0 DETRX_REQ_OVRD_EN 1 1 VBOOST_EN_OVRD_VAL 2 2 VBOOST_EN_OVRD_EN 3 3 IBOOST_LVL_OVRD_VAL 4 7 IBOOST_LVL_OVRD_EN 8 8 TX_BEACON_EN_OVR_VAL 9 9 TX_BEACON_EN_OVR_EN 10 10 LANE_TX2RX_SER_LB_EN_OVRD_VAL 11 11 LANE_TX2RX_SER_LB_EN_OVRD_EN 12 12 TX_ASYNC_DATA_OVRD_VAL 13 13 TX_ASYNC_DATA_OVRD_EN 14 14 RESERVED_15_15 15 15 ixDPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_MASTER_MPLL_LOOP 2 0x32c3 3 0 4294967295 MPLLB_LOOP_EN 0 0 MPLLA_LOOP_EN 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1 2 0x32c4 11 0 4294967295 RESERVED 0 1 RX_LOS_LFPS_EN_OVRD_VAL 2 2 RX_LOS_LFPS_EN_OVRD_EN 3 3 RX_LOS_THRSHLD_OVRD_VAL 4 6 RX_LOS_THRSHLD_OVRD_EN 7 7 ADAPT_REQ 8 8 ADAPT_REQ_OVRD_EN 9 9 ADAPT_CONT 10 10 OFFCAN_CONT 11 11 CONT_OVRD_EN 12 12 RESERVED_15_13 13 15 ixDPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_2 2 0x32c5 4 0 4294967295 VCO_LD_VAL_OVRD 0 12 VCO_LD_VAL_OVRD_EN 13 13 VCO_LOWFREQ_VAL_OVRD 14 14 VCO_LOWFREQ_VAL_OVRD_EN 15 15 ixDPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_3 2 0x32c6 3 0 4294967295 REF_LD_VAL_OVRD 0 6 REF_LD_VAL_OVRD_EN 7 7 RESERVED_15_8 8 15 ixDPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT_2 2 0x32c7 3 0 4294967295 RX_VALID 0 0 RX_VALID_OVRD_EN 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_2 2 0x32c8 7 0 4294967295 LANE_TX2RX_SER_LB_EN_OVRD_VAL 0 0 LANE_TX2RX_SER_LB_EN_OVRD_EN 1 1 TX_DATA_EN_OVRD_VAL_R 2 2 TX_DATA_EN_OVRD_EN_R 3 3 TX_ASYNC_DATA_OVRD_VAL_R 4 4 TX_ASYNC_DATA_OVRD_EN_R 5 5 RESERVED_15_6 6 15 ixDPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN 2 0x3300 12 0 4294967295 PSTATE 0 1 LPD 2 2 WIDTH 3 4 RATE 5 7 MPLLB_SEL 8 8 MPLL_EN 9 9 OVRD_EN 10 10 MSTR_MPLLA_STATE 11 11 MSTR_MPLLB_STATE 12 12 MSTR_MPLL_OVRD_EN 13 13 TX_ASYNC_EN_OVR_VAL 14 14 TX_ASYNC_EN_OVR_EN 15 15 ixDPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1 2 0x3301 13 0 4294967295 RESET_OVRD_VAL 0 0 RESET_OVRD_EN 1 1 REQ_OVRD_VAL 2 2 REQ_OVRD_EN 3 3 DETRX_REQ_OVRD_VAL 4 4 DETRX_REQ_OVRD_EN 5 5 VBOOST_EN_OVRD_VAL 6 6 VBOOST_EN_OVRD_EN 7 7 IBOOST_LVL_OVRD_VAL 8 11 IBOOST_LVL_OVRD_EN 12 12 TX_BEACON_EN_OVR_VAL 13 13 TX_BEACON_EN_OVR_EN 14 14 RESERVED_15_15 15 15 ixDPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_PCS_IN 2 0x3302 12 0 4294967295 RESET 0 0 REQ 1 1 PSTATE 2 3 LPD 4 4 WIDTH 5 6 RATE 7 9 MPLLB_SEL 10 10 MPLL_EN 11 11 MSTR_MPLLA_STATE 12 12 MSTR_MPLLB_STATE 13 13 DETRX_REQ 14 14 RESERVED_15_15 15 15 ixDPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_OVRD_OUT 2 0x3303 6 0 4294967295 ACK 0 0 DETRX_RESULT 1 1 EN_CTL 2 2 TX_DWORD_CLK_SYNC_OVRD_VAL 3 3 TX_DWORD_CLK_SYNC_OVRD_EN 4 4 RESERVED_15_5 5 15 ixDPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_PCS_OUT 2 0x3304 2 0 4294967295 ACK 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN 2 0x3305 12 0 4294967295 RATE 0 1 WIDTH 2 3 PSTATE 4 5 LPD 6 6 OVRD_EN 7 7 ADAPT_AFE_EN 8 8 ADAPT_DFE_EN 9 9 LANE_RX2TX_PAR_LB_EN_OVRD_VAL 10 10 LANE_RX2TX_PAR_LB_EN_OVRD_EN 11 11 RX_DATA_EN_OVRD_VAL_R 12 12 RX_DATA_EN_OVRD_EN_R 13 13 RESERVED_15_14 14 15 ixDPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1 2 0x3306 12 0 4294967295 RESET_OVRD_VAL 0 0 RESET_OVRD_EN 1 1 REQ_OVRD_VAL 2 2 REQ_OVRD_EN 3 3 RX_LOS_THRSHLD_OVRD_VAL 4 6 RX_LOS_THRSHLD_OVRD_EN 7 7 ADAPT_REQ 8 8 ADAPT_REQ_OVRD_EN 9 9 ADAPT_CONT 10 10 OFFCAN_CONT 11 11 CONT_OVRD_EN 12 12 RESERVED_15_13 13 15 ixDPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_2 2 0x3307 4 0 4294967295 VCO_LD_VAL_OVRD 0 12 VCO_LD_VAL_OVRD_EN 13 13 VCO_LOWFREQ_VAL_OVRD 14 14 VCO_LOWFREQ_VAL_OVRD_EN 15 15 ixDPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_3 2 0x3308 3 0 4294967295 REF_LD_VAL_OVRD 0 6 REF_LD_VAL_OVRD_EN 7 7 RESERVED_15_8 8 15 ixDPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_PCS_IN 2 0x3309 13 0 4294967295 REQ 0 0 RATE 1 2 WIDTH 3 4 PSTATE 5 6 LPD 7 7 CDR_VCO_LOWFREQ 8 8 ADAPT_AFE_EN 9 9 ADAPT_DFE_EN 10 10 ADAPT_REQ 11 11 ADAPT_CONT 12 12 OFFCAN_CONT 13 13 RESET 14 14 RESERVED_15_15 15 15 ixDPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_1 2 0x330a 2 0 4294967295 REF_LD_VAL 0 6 RESERVED_15_7 7 15 ixDPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_2 2 0x330b 2 0 4294967295 VCO_LD_VAL 0 12 RESERVED_15_13 13 15 ixDPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_3 2 0x330c 4 0 4294967295 EQ_ATT_LVL 0 2 EQ_VGA1_GAIN 3 6 EQ_VGA2_GAIN 7 10 EQ_CTLE_BOOST 11 15 ixDPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_4 2 0x330d 3 0 4294967295 EQ_CTLE_POLE 0 2 EQ_DFE_TAP1 3 10 RESERVED_15_11 11 15 ixDPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT 2 0x330e 3 0 4294967295 ACK 0 0 EN_CTL 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_PCS_OUT 2 0x330f 2 0 4294967295 ACK 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_ADAPT_ACK 2 0x3310 2 0 4294967295 RX_ADAPT_ACK 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_ADAPT_FOM 2 0x3311 2 0 4294967295 RX_ADAPT_FOM 0 7 RESERVED_15_8 8 15 ixDPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_TXPRE_DIR 2 0x3312 2 0 4294967295 RX_TXPRE_DIR 0 1 RESERVED_15_2 2 15 ixDPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_TXMAIN_DIR 2 0x3313 2 0 4294967295 RX_TXMAIN_DIR 0 1 RESERVED_15_2 2 15 ixDPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_TXPOST_DIR 2 0x3314 2 0 4294967295 RX_TXPOST_DIR 0 1 RESERVED_15_2 2 15 ixDPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_LANE_NUMBER 2 0x3315 2 0 4294967295 LANE_NUMBER 0 3 RESERVED_15_4 4 15 ixDPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RESERVED_1 2 0x3316 1 0 4294967295 RESERVED_REG_1 0 15 ixDPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RESERVED_2 2 0x3317 1 0 4294967295 RESERVED_REG_2 0 15 ixDPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN 2 0x3318 16 0 4294967295 RX_RESET_ATE_OVRD_VAL 0 0 RX_RESET_ATE_OVRD_EN 1 1 TX_RESET_ATE_OVRD_VAL 2 2 TX_RESET_ATE_OVRD_EN 3 3 RX_REQ_ATE_OVRD_VAL 4 4 RX_REQ_ATE_OVRD_EN 5 5 TX_REQ_ATE_OVRD_VAL 6 6 TX_REQ_ATE_OVRD_EN 7 7 RX_ADAPT_AFE_EN_OVRD_VAL 8 8 RX_ADAPT_AFE_EN_OVRD_EN 9 9 RX_ADAPT_DFE_EN_OVRD_VAL 10 10 RX_ADAPT_DFE_EN_OVRD_EN 11 11 TX_DATA_EN_ATE_OVRD_VAL 12 12 TX_DATA_EN_ATE_OVRD_EN 13 13 RX_DATA_EN_ATE_OVRD_VAL 14 14 RX_DATA_EN_ATE_OVRD_EN 15 15 ixDPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN 2 0x3319 3 0 4294967295 RX_EQ_DELTA_IQ_OVRD_VAL 0 3 RX_EQ_DELTA_IQ_OVRD_EN 4 4 RESERVED_15_5 5 15 ixDPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN 2 0x331a 5 0 4294967295 RX_TERM_CTRL_OVRD_VAL 0 2 RX_TERM_CTRL_OVRD_EN 3 3 TX_TERM_CTRL_OVRD_VAL 4 6 TX_TERM_CTRL_OVRD_EN 7 7 RESERVED_15_8 8 15 ixDPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TXRX_TERM_CTRL_IN 2 0x331b 3 0 4294967295 RX_TERM_CTRL 0 2 TX_TERM_CTRL 3 5 RESERVED_15_6 6 15 ixDPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT_1 2 0x331c 2 0 4294967295 RX_CLK_EN 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_EQ_OVRD_IN_1 2 0x331d 4 0 4294967295 RX_EQ_AFE_GAIN_OVRD_VAL 0 3 RX_EQ_ATT_LVL_OVRD_VAL 4 6 RX_EQ_OVRD_EN 7 7 RESERVED_15_8 8 15 ixDPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_EQ_OVRD_IN_2 2 0x331e 3 0 4294967295 RX_EQ_DFE_TAP1_OVRD_VAL 0 7 RX_EQ_CTLE_BOOST_OVRD_VAL 8 12 RESERVED_15_13 13 15 ixDPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_PH2_CAL 2 0x331f 4 0 4294967295 PH2_CAL_ACK_VAL 0 0 PH2_CAL_REQ_VAL 1 1 PH2_CAL_REQ_OVRD_VAL 2 2 RESERVED_15_3 3 15 ixDPCSSYS_CR3_RAWLANE3_DIG_FSM_FSM_OVRD_CTL 2 0x3320 5 0 4294967295 FSM_JMP_ADDR 0 11 FSM_JMP_EN 12 12 FSM_CMD_START 13 13 FSM_OVRD_EN 14 14 FSM_BREAK 15 15 ixDPCSSYS_CR3_RAWLANE3_DIG_FSM_MEM_ADDR_MON 2 0x3321 1 0 4294967295 MEM_ADDR 0 15 ixDPCSSYS_CR3_RAWLANE3_DIG_FSM_STATUS_MON 2 0x3322 8 0 4294967295 STATE 0 4 CMD_RDY 5 5 ALU_OVFLW 6 6 ALU_RES_EQ0 7 7 WAIT_CNT_EQ0 8 8 WRMSK_DISABLED 9 9 RDMSK_DISABLED 10 10 RESERVED_15_11 11 15 ixDPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_RX_STARTUP_CAL 2 0x3323 2 0 4294967295 FAST_RX_STARTUP_CAL 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_RX_ADAPT 2 0x3324 2 0 4294967295 FAST_RX_ADAPT 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_RX_AFE_CAL 2 0x3325 2 0 4294967295 FAST_RX_AFE_CAL 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_RX_DFE_CAL 2 0x3326 2 0 4294967295 FAST_RX_DFE_CAL 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_RX_BYPASS_CAL 2 0x3327 2 0 4294967295 FAST_RX_BYPASS_CAL 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_RX_REFLVL_CAL 2 0x3328 2 0 4294967295 FAST_RX_REFLVL_CAL 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_RX_IQ_CAL 2 0x3329 2 0 4294967295 FAST_RX_IQ_CAL 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_RX_AFE_ADAPT 2 0x332a 2 0 4294967295 FAST_RX_AFE_ADAPT 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_RX_DFE_ADAPT 2 0x332b 2 0 4294967295 FAST_RX_DFE_ADAPT 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_SUP 2 0x332c 2 0 4294967295 FAST_SUP 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_TX_CMN_MODE 2 0x332d 2 0 4294967295 FAST_TX_CMN_MODE 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_TX_RXDET 2 0x332e 2 0 4294967295 FAST_TX_RXDET 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_RX_PWRUP 2 0x332f 2 0 4294967295 FAST_RX_PWRUP 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_RX_VCO_WAIT 2 0x3330 2 0 4294967295 FAST_RX_VCO_WAIT 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_RX_VCO_CAL 2 0x3331 2 0 4294967295 FAST_RX_VCO_CAL 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR3_RAWLANE3_DIG_FSM_CMNCAL_MPLL_STATUS 2 0x3332 3 0 4294967295 CMNCAL_MPLL_INIT 0 0 CMNCAL_MPLL_DONE 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_RX_CONT_CAL_ADAPT 2 0x3333 2 0 4294967295 FAST_RX_CONT_CAL_ADAPT 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_RX_CONT_ADAPT 2 0x3334 2 0 4294967295 FAST_RX_CONT_ADAPT 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_RX_CONT_DATA_CAL 2 0x3335 2 0 4294967295 FAST_RX_CONT_DATA_CAL 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_RX_CONT_PHASE_CAL 2 0x3336 2 0 4294967295 FAST_RX_CONT_PHASE_CAL 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_RX_CONT_AFE_CAL 2 0x3337 2 0 4294967295 FAST_RX_CONT_AFE_CAL 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_FLAGS 2 0x3338 12 0 4294967295 TX_FAST_DCC_CAL 0 0 RX_FAST_DCC_CAL 1 1 RX_FAST_VPHUD_CAL 2 2 RX_FAST_VREF_CAL 3 3 RX_FAST_SIGDET_CAL 4 4 RESERVED_2 5 7 TX_FAST_CONT_DCC_CAL 8 8 RX_FAST_CONT_DCC_CAL 9 9 RX_FAST_CONT_VPHUD_CAL 10 10 RX_FAST_CONT_VREF_CAL 11 11 RESERVED_1 12 14 TX_SKIP_SUP_CAL 15 15 ixDPCSSYS_CR3_RAWLANE3_DIG_FSM_CR_LOCK 2 0x3339 3 0 4294967295 CR_REG_LOCK 0 0 CR_MEM_LOCK 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR3_RAWLANE3_DIG_FSM_TX_DCC_FLAGS 2 0x333a 4 0 4294967295 RATE 0 0 DIV 1 1 MPLL 2 2 RESERVED_15_3 3 15 ixDPCSSYS_CR3_RAWLANE3_DIG_FSM_TX_DCC_STATUS 2 0x333b 2 0 4294967295 FLAG 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR3_RAWLANE3_DIG_FSM_OCLA 2 0x333c 4 0 4294967295 PC_EN 0 0 REG_BANK1_EN 1 1 REG_BANK2_EN 2 2 RESERVED_15_3 3 15 ixDPCSSYS_CR3_RAWLANE3_DIG_FSM_TX_EQ_UPDATE_FLAG 2 0x333d 2 0 4294967295 TX_EQ_UPDATE_FLAG 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR3_RAWLANE3_DIG_FSM_CMNCAL_RCAL_STATUS 2 0x333e 3 0 4294967295 CMNCAL_RCAL_INIT 0 0 CMNCAL_RCAL_DONE 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR3_RAWLANE3_DIG_FSM_RX_IQ_PHASE_OFFSET 2 0x333f 2 0 4294967295 RX_IQ_PHASE_OFFSET 0 3 RESERVED_15_4 4 15 ixDPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_RESET_RTN_REQ 2 0x3340 2 0 4294967295 RESET_RTN_REQ 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_RX_RESET_IRQ 2 0x3341 2 0 4294967295 RX_RESET 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_RX_REQ_IRQ 2 0x3342 2 0 4294967295 RX_REQ 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_RX_RATE_IRQ 2 0x3343 2 0 4294967295 RX_RATE_IRQ 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_RX_PSTATE_IRQ 2 0x3344 2 0 4294967295 RX_PSTATE_IRQ 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ 2 0x3345 2 0 4294967295 RX_ADAPT_REQ_IRQ 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ 2 0x3346 2 0 4294967295 RX_ADAPT_DIS_IRQ 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_RX_RESET_IRQ_CLR 2 0x3347 2 0 4294967295 RX_RESET_IRQ_CLR 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_RX_REQ_IRQ_CLR 2 0x3348 2 0 4294967295 RX_REQ_IRQ_CLR 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_RX_RATE_IRQ_CLR 2 0x3349 2 0 4294967295 RX_RATE_IRQ_CLR 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR 2 0x334a 2 0 4294967295 RX_PSTATE_IRQ_CLR 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR 2 0x334b 2 0 4294967295 RX_ADAPT_REQ_IRQ_CLR 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR 2 0x334c 2 0 4294967295 RX_ADAPT_DIS_IRQ_CLR 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK 2 0x334d 12 0 4294967295 RX_REQ_IRQ_MSK 0 0 RX_RATE_IRQ_MSK 1 1 RX_PSTATE_IRQ_MSK 2 2 RX_ADAPT_REQ_IRQ_MSK 3 3 RX_ADAPT_DIS_IRQ_MSK 4 4 RX_RESET_IRQ_MSK 5 5 LANE_XCVR_MODE_IRQ_MSK 6 6 RX_PH2_CAL_REQ_IRQ_MSK 7 7 RX_PH2_CAL_DIS_IRQ_MSK 8 8 LANE_RX2TX_SER_LB_EN_IRQ_MSK 9 9 DCC_ONDMD_IRQ_MSK 10 10 RESERVED_15_11 11 15 ixDPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK_2 2 0x334e 3 0 4294967295 TX_RESET_IRQ_MSK 0 0 TX_REQ_IRQ_MSK 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ 2 0x334f 2 0 4294967295 LANE_XCVR_MODE_IRQ 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR 2 0x3350 2 0 4294967295 LANE_XCVR_MODE_IRQ_CLR 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ 2 0x3351 2 0 4294967295 RX_PH2_CAL_REQ_IRQ 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ 2 0x3352 2 0 4294967295 RX_PH2_CAL_DIS_IRQ 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR 2 0x3353 2 0 4294967295 RX_PH2_CAL_REQ_IRQ_CLR 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR 2 0x3354 2 0 4294967295 RX_PH2_CAL_DIS_IRQ_CLR 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ 2 0x3355 2 0 4294967295 LANE_RX2TX_SER_LB_EN_IRQ 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR 2 0x3356 2 0 4294967295 LANE_RX2TX_SER_LB_EN_IRQ_CLR 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_DCC_ONDMD_IRQ 2 0x3357 2 0 4294967295 IRQ 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_TX_RESET_IRQ 2 0x3358 2 0 4294967295 TX_RESET 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_TX_REQ_IRQ 2 0x3359 2 0 4294967295 TX_REQ 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_TX_RESET_IRQ_CLR 2 0x335a 2 0 4294967295 TX_RESET_IRQ_CLR 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_TX_REQ_IRQ_CLR 2 0x335b 2 0 4294967295 TX_REQ_IRQ_CLR 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_LANE_OVRD_IN 2 0x3360 4 0 4294967295 LANE_MPLLA_EN_IN 0 0 LANE_MPLLB_EN_IN 1 1 LANE_OVRD_EN 2 2 RESERVED_15_3 3 15 ixDPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_LANE_OVRD_OUT 2 0x3361 4 0 4294967295 LANE_MPLLA_EN_OUT 0 0 LANE_MPLLB_EN_OUT 1 1 LANE_OVRD_EN 2 2 RESERVED_15_3 3 15 ixDPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_SUP_OVRD_IN 2 0x3362 4 0 4294967295 MPLLA_STATE 0 0 MPLLB_STATE 1 1 SUP_STATE_OVRD_EN 2 2 RESERVED_15_3 3 15 ixDPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_SUP_PMA_IN 2 0x3363 3 0 4294967295 MPLLA_STATE 0 0 MPLLB_STATE 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT 2 0x3364 16 0 4294967295 TX_REQ_OVRD_VAL 0 0 TX_REQ_OVRD_EN 1 1 TX_RESET_OVRD_VAL 2 2 TX_RESET_OVRD_EN 3 3 TX_BEACON_EN_OVRD_VAL 4 4 TX_BEACON_EN_OVRD_EN 5 5 TX_ASYNC_DRV_EN_OVRD_VAL 6 6 TX_ASYNC_DRV_EN_OVRD_EN 7 7 TX_ASYNC_EN_OVRD_VAL 8 8 TX_ASYNC_EN_OVRD_EN 9 9 TX_DWORD_CLK_SYNC_OVRD_VAL 10 10 TX_DWORD_CLK_SYNC_OVRD_EN 11 11 LANE_TX2RX_SER_LB_EN_OVRD_VAL 12 12 LANE_TX2RX_SER_LB_EN_OVRD_EN 13 13 TX_PMA_DATA_EN_OVRD_VAL_R 14 14 TX_PMA_DATA_EN_OVRD_EN_R 15 15 ixDPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_TX_PMA_IN 2 0x3365 2 0 4294967295 ACK 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT 2 0x3366 9 0 4294967295 RX_REQ_OVRD_VAL 0 0 RX_REQ_OVRD_EN 1 1 RX_RESET_OVRD_VAL 2 2 RX_RESET_OVRD_EN 3 3 LANE_RX2TX_PAR_LB_EN_OVRD_VAL 4 4 LANE_RX2TX_PAR_LB_EN_OVRD_EN 5 5 RX_PMA_DATA_EN_OVRD_VAL_R 6 6 RX_PMA_DATA_EN_OVRD_EN_R 7 7 RESERVED_15_8 8 15 ixDPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_RX_PMA_IN 2 0x3367 2 0 4294967295 ACK 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_LANE_RTUNE_CTL 2 0x3368 2 0 4294967295 LANE_RTUNE_REQ 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_SUP_PMA_IN_1 2 0x3369 2 0 4294967295 RTUNE_ACK 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_IN 2 0x336a 9 0 4294967295 RX_PMA_PWM_WORD_CLK_R 0 0 RX_PMA_PWM_WORD_CLK_OVRD_EN 1 1 RX_PMA_PWM_DATA_R 2 2 RX_PMA_PWM_DATA_OVRD_EN 3 3 RX_PMA_PWM_CLK_R 4 4 RX_PMA_PWM_CLK_OVRD_EN 5 5 RX_PMA_TERM_CTL_R 6 7 RX_PMA_TERM_CTL_OVRD_EN 8 8 RESERVED_15_9 9 15 ixDPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_OUT 2 0x336b 7 0 4294967295 RX_PMA_PWM_EN 0 0 RX_PMA_PWM_EN_OVRD_EN 1 1 RX_PMA_PWM_CLK_SEL 2 3 RX_PMA_PWM_CLK_SEL_OVRD_EN 4 4 RX_PMA_ASYNC_EN 5 5 RX_PMA_ASYNC_EN_OVRD_EN 6 6 RESERVED_15_7 7 15 ixDPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_RX_ADAPT_OVRD_OUT 2 0x336c 3 0 4294967295 RX_PMA_IQ_PHASE_ADJUST_MAP_OVRD_VAL 0 6 RX_PMA_IQ_PHASE_ADJUST_MAP_OVRD_EN 7 7 RESERVED_15_8 8 15 ixDPCSSYS_CR3_RAWLANE3_DIG_TX_CTL_TX_FSM_CTL 2 0x3380 6 0 4294967295 TX_WAIT_MPLL_OFF_TIME 0 6 TX_P2_ALLOW_RXDET 7 7 TX_P1_ALLOW_RXDET 8 8 TX_P0S_ALLOW_RXDET 9 9 TX_P0_ALLOW_RXDET 10 10 RESERVED_15_11 11 15 ixDPCSSYS_CR3_RAWLANE3_DIG_TX_CTL_TX_CLK_CTL 2 0x3381 4 0 4294967295 TX_CLK_EN 0 0 TX_CLK_SEL 1 4 ASYNC_BEACON_WAIT_TIME 5 10 RESERVED_15_11 11 15 ixDPCSSYS_CR3_RAWLANE3_DIG_TX_CTL_TX_DCC_CONT_STATUS 2 0x3382 2 0 4294967295 ENABLE 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR3_RAWLANE3_DIG_TX_CTL_OCLA 2 0x3383 2 0 4294967295 FSM_EN 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR3_RAWLANE3_DIG_TX_CTL_UPCS_OCLA 2 0x3384 3 0 4294967295 DATA_EN 0 1 CLK_EN 2 2 RESERVED_15_3 3 15 ixDPCSSYS_CR3_RAWLANE3_DIG_RX_CTL_RX_FSM_CTL 2 0x33a0 3 0 4294967295 EN_RX_CTL_FSM 0 0 RATE_CHG_IN_P1 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR3_RAWLANE3_DIG_RX_CTL_RX_LOS_MASK_CTL 2 0x33a1 2 0 4294967295 RX_LOS_MASK_CNT 0 8 RESERVED_15_9 9 15 ixDPCSSYS_CR3_RAWLANE3_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL 2 0x33a2 2 0 4294967295 RX_DATA_EN_OVRD_CNT 0 4 INT_REF_TRCK_CNT 5 15 ixDPCSSYS_CR3_RAWLANE3_DIG_RX_CTL_OFFCAN_CONT_STATUS 2 0x33a3 2 0 4294967295 ENABLE 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR3_RAWLANE3_DIG_RX_CTL_ADAPT_CONT_STATUS 2 0x33a4 2 0 4294967295 ENABLE 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR3_RAWLANE3_DIG_RX_CTL_UPCS_OCLA 2 0x33a5 3 0 4294967295 DATA_EN 0 2 CLK_EN 3 3 RESERVED_15_4 4 15 ixDPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN 2 0x33c0 11 0 4294967295 RATE_OVRD_VAL 0 1 RATE_OVRD_EN 2 2 WIDTH_OVRD_VAL 3 4 WIDTH_OVRD_EN 5 5 PSTATE_OVRD_VAL 6 7 PSTATE_OVRD_EN 8 8 LPD_OVRD_VAL 9 9 LPD_OVRD_EN 10 10 LANE_RX2TX_PAR_LB_EN_OVRD_VAL 11 11 LANE_RX2TX_PAR_LB_EN_OVRD_EN 12 12 RESERVED_15_13 13 15 ixDPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN 2 0x33c1 12 0 4294967295 PSTATE 0 1 LPD 2 2 WIDTH 3 4 RATE 5 7 MPLLB_SEL 8 8 MPLL_EN 9 9 OVRD_EN 10 10 MSTR_MPLLA_STATE 11 11 MSTR_MPLLB_STATE 12 12 MSTR_MPLL_OVRD_EN 13 13 TX_ASYNC_EN_OVR_VAL 14 14 TX_ASYNC_EN_OVR_EN 15 15 ixDPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1 2 0x33c2 13 0 4294967295 DETRX_REQ_OVRD_VAL 0 0 DETRX_REQ_OVRD_EN 1 1 VBOOST_EN_OVRD_VAL 2 2 VBOOST_EN_OVRD_EN 3 3 IBOOST_LVL_OVRD_VAL 4 7 IBOOST_LVL_OVRD_EN 8 8 TX_BEACON_EN_OVR_VAL 9 9 TX_BEACON_EN_OVR_EN 10 10 LANE_TX2RX_SER_LB_EN_OVRD_VAL 11 11 LANE_TX2RX_SER_LB_EN_OVRD_EN 12 12 TX_ASYNC_DATA_OVRD_VAL 13 13 TX_ASYNC_DATA_OVRD_EN 14 14 RESERVED_15_15 15 15 ixDPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_MASTER_MPLL_LOOP 2 0x33c3 3 0 4294967295 MPLLB_LOOP_EN 0 0 MPLLA_LOOP_EN 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1 2 0x33c4 11 0 4294967295 RESERVED 0 1 RX_LOS_LFPS_EN_OVRD_VAL 2 2 RX_LOS_LFPS_EN_OVRD_EN 3 3 RX_LOS_THRSHLD_OVRD_VAL 4 6 RX_LOS_THRSHLD_OVRD_EN 7 7 ADAPT_REQ 8 8 ADAPT_REQ_OVRD_EN 9 9 ADAPT_CONT 10 10 OFFCAN_CONT 11 11 CONT_OVRD_EN 12 12 RESERVED_15_13 13 15 ixDPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_2 2 0x33c5 4 0 4294967295 VCO_LD_VAL_OVRD 0 12 VCO_LD_VAL_OVRD_EN 13 13 VCO_LOWFREQ_VAL_OVRD 14 14 VCO_LOWFREQ_VAL_OVRD_EN 15 15 ixDPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_3 2 0x33c6 3 0 4294967295 REF_LD_VAL_OVRD 0 6 REF_LD_VAL_OVRD_EN 7 7 RESERVED_15_8 8 15 ixDPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT_2 2 0x33c7 3 0 4294967295 RX_VALID 0 0 RX_VALID_OVRD_EN 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_2 2 0x33c8 7 0 4294967295 LANE_TX2RX_SER_LB_EN_OVRD_VAL 0 0 LANE_TX2RX_SER_LB_EN_OVRD_EN 1 1 TX_DATA_EN_OVRD_VAL_R 2 2 TX_DATA_EN_OVRD_EN_R 3 3 TX_ASYNC_DATA_OVRD_VAL_R 4 4 TX_ASYNC_DATA_OVRD_EN_R 5 5 RESERVED_15_6 6 15 ixDPCSSYS_CR3_RAWAONLANE0_DIG_AFE_ATT_IDAC_OFST 2 0x4000 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR3_RAWAONLANE0_DIG_AFE_CTLE_IDAC_OFST 2 0x4001 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR3_RAWAONLANE0_DIG_RX_ADPT_IQ 2 0x4002 2 0 4294967295 IQ_ADPT_VAL 0 6 RESERVED_15_7 7 15 ixDPCSSYS_CR3_RAWAONLANE0_DIG_RX_ADAPT_FOM 2 0x4003 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR3_RAWAONLANE0_DIG_DFE_SUMMER_ODD_IDAC_OFST 2 0x4004 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR3_RAWAONLANE0_DIG_DFE_PHASE_EVEN_VDAC_OFST 2 0x4005 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR3_RAWAONLANE0_DIG_DFE_PHASE_ODD_VDAC_OFST 2 0x4006 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR3_RAWAONLANE0_DIG_DFE_EVEN_REF_LVL 2 0x4007 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR3_RAWAONLANE0_DIG_DFE_ODD_REF_LVL 2 0x4008 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR3_RAWAONLANE0_DIG_RX_PHSADJ_LIN 2 0x4009 2 0 4294967295 DATA 0 0 RESERVED_15_5 5 15 ixDPCSSYS_CR3_RAWAONLANE0_DIG_RX_PHSADJ_MAP 2 0x400a 2 0 4294967295 DATA 0 0 RESERVED_15_5 5 15 ixDPCSSYS_CR3_RAWAONLANE0_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST 2 0x400b 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR3_RAWAONLANE0_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST 2 0x400c 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR3_RAWAONLANE0_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST 2 0x400d 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR3_RAWAONLANE0_DIG_DFE_DATA_ODD_LOW_VDAC_OFST 2 0x400e 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR3_RAWAONLANE0_DIG_DFE_BYPASS_EVEN_VDAC_OFST 2 0x400f 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR3_RAWAONLANE0_DIG_DFE_BYPASS_ODD_VDAC_OFST 2 0x4010 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR3_RAWAONLANE0_DIG_DFE_ERROR_EVEN_VDAC_OFST 2 0x4011 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR3_RAWAONLANE0_DIG_DFE_ERROR_ODD_VDAC_OFST 2 0x4012 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR3_RAWAONLANE0_DIG_RX_IQ_PHASE_ADJUST 2 0x4013 2 0 4294967295 DATA 0 0 RESERVED_15_7 7 15 ixDPCSSYS_CR3_RAWAONLANE0_DIG_MPLLA_COARSE_TUNE 2 0x4014 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR3_RAWAONLANE0_DIG_MPLLB_COARSE_TUNE 2 0x4015 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR3_RAWAONLANE0_DIG_INIT_PWRUP_DONE 2 0x4016 3 0 4294967295 DATA 0 0 PH2_PWRUP_DONE 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR3_RAWAONLANE0_DIG_RX_ADPT_ATT 2 0x4017 2 0 4294967295 ATT_ADPT_VAL 0 7 RESERVED_15_8 8 15 ixDPCSSYS_CR3_RAWAONLANE0_DIG_RX_ADPT_VGA 2 0x4018 2 0 4294967295 VGA_ADPT_VAL 0 9 RESERVED_15_10 10 15 ixDPCSSYS_CR3_RAWAONLANE0_DIG_RX_ADPT_CTLE 2 0x4019 3 0 4294967295 CTLE_BOOST_ADPT_VAL 0 9 CTLE_POLE_ADPT_VAL 10 12 RESERVED_15_13 13 15 ixDPCSSYS_CR3_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP1 2 0x401a 2 0 4294967295 DFE_TAP1_ADPT_VAL 0 12 RESERVED_15_13 13 15 ixDPCSSYS_CR3_RAWAONLANE0_DIG_RX_ADAPT_DONE 2 0x401b 2 0 4294967295 DATA 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR3_RAWAONLANE0_DIG_FAST_FLAGS 2 0x401c 16 0 4294967295 FAST_RX_STARTUP_CAL 0 0 FAST_RX_ADAPT 1 1 FAST_RX_AFE_CAL 2 2 FAST_RX_DFE_CAL 3 3 FAST_RX_BYPASS_CAL 4 4 FAST_RX_REFLVL_CAL 5 5 FAST_RX_IQ_CAL 6 6 FAST_RX_AFE_ADAPT 7 7 FAST_RX_DFE_ADAPT 8 8 FAST_SUP 9 9 FAST_TX_CMN_MODE 10 10 FAST_TX_RXDET 11 11 FAST_RX_PWRUP 12 12 FAST_RX_VCO_WAIT 13 13 FAST_RX_VCO_CAL 14 14 RESERVED_15_15 15 15 ixDPCSSYS_CR3_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP2 2 0x401d 2 0 4294967295 DFE_TAP2_ADPT_VAL 0 11 RESERVED_15_12 12 15 ixDPCSSYS_CR3_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP3 2 0x401e 2 0 4294967295 DFE_TAP3_ADPT_VAL 0 11 RESERVED_15_12 12 15 ixDPCSSYS_CR3_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP4 2 0x401f 2 0 4294967295 DFE_TAP4_ADPT_VAL 0 11 RESERVED_15_12 12 15 ixDPCSSYS_CR3_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP5 2 0x4020 2 0 4294967295 DFE_TAP5_ADPT_VAL 0 11 RESERVED_15_12 12 15 ixDPCSSYS_CR3_RAWAONLANE0_DIG_RX_SLICER_CTRL_EVEN 2 0x4021 2 0 4294967295 RX_ANA_SLICER_CTRL_E 0 3 RESERVED_15_4 4 15 ixDPCSSYS_CR3_RAWAONLANE0_DIG_RX_SLICER_CTRL_ODD 2 0x4022 2 0 4294967295 RX_ANA_SLICER_CTRL_O 0 3 RESERVED_15_4 4 15 ixDPCSSYS_CR3_RAWAONLANE0_DIG_LANE_CMNCAL_MPLL_STATUS 2 0x4023 3 0 4294967295 LANE_CMNCAL_MPLL_INIT 0 0 LANE_CMNCAL_MPLL_DONE 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR3_RAWAONLANE0_DIG_ADPT_CTL_0 2 0x4024 1 0 4294967295 VAL 0 15 ixDPCSSYS_CR3_RAWAONLANE0_DIG_ADPT_CTL_1 2 0x4025 1 0 4294967295 VAL 0 15 ixDPCSSYS_CR3_RAWAONLANE0_DIG_ADPT_CTL_2 2 0x4026 1 0 4294967295 VAL 0 15 ixDPCSSYS_CR3_RAWAONLANE0_DIG_ADPT_CTL_3 2 0x4027 1 0 4294967295 VAL 0 15 ixDPCSSYS_CR3_RAWAONLANE0_DIG_ADPT_CTL_4 2 0x4028 1 0 4294967295 VAL 0 15 ixDPCSSYS_CR3_RAWAONLANE0_DIG_ADPT_CTL_5 2 0x4029 1 0 4294967295 VAL 0 15 ixDPCSSYS_CR3_RAWAONLANE0_DIG_ADPT_CTL_6 2 0x402a 1 0 4294967295 VAL 0 15 ixDPCSSYS_CR3_RAWAONLANE0_DIG_ADPT_CTL_7 2 0x402b 1 0 4294967295 VAL 0 15 ixDPCSSYS_CR3_RAWAONLANE0_DIG_MPLL_DISABLE 2 0x402c 3 0 4294967295 LANE_MPLLA_DISABLE 0 0 LANE_MPLLB_DISABLE 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR3_RAWAONLANE0_DIG_FAST_FLAGS_2 2 0x402d 16 0 4294967295 FAST_RX_CONT_CAL_ADAPT 0 0 FAST_RX_CONT_ADAPT 1 1 FAST_RX_CONT_DATA_CAL 2 2 FAST_RX_CONT_PHASE_CAL 3 3 FAST_RX_CONT_AFE_CAL 4 4 FAST_TX_CONT_DCC_CAL 5 5 FAST_RX_CONT_DCC_CAL 6 6 FAST_RX_CONT_VPHUD_CAL 7 7 FAST_RX_CONT_VREF_CAL 8 8 FAST_TX_DCC_CAL 9 9 FAST_RX_DCC_CAL 10 10 FAST_RX_VPHUD_CAL 11 11 FAST_RX_VREF_CAL 12 12 SKIP_TX_RTUNE_CAL 13 13 FAST_RX_SIGDET_CAL 14 14 RESERVED_15_15 15 15 ixDPCSSYS_CR3_RAWAONLANE0_DIG_LANE_CMNCAL_RCAL_STATUS 2 0x402e 3 0 4294967295 LANE_CMNCAL_RCAL_INIT 0 0 LANE_CMNCAL_RCAL_DONE 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR3_RAWAONLANE0_DIG_TXRX_OVRD_IN 2 0x402f 5 0 4294967295 RX_DISABLE_OVRD_VAL 0 0 RX_DISABLE_OVRD_EN 1 1 TX_DISABLE_OVRD_VAL 2 2 TX_DISABLE_OVRD_EN 3 3 RESERVED_15_4 4 15 ixDPCSSYS_CR3_RAWAONLANE0_DIG_RX_LOS_MASK_CTL 2 0x4030 2 0 4294967295 RX_LOS_MASK_CNT 0 8 RESERVED_15_9 9 15 ixDPCSSYS_CR3_RAWAONLANE0_DIG_RX_SIGDET_FILT_CTRL 2 0x4031 5 0 4294967295 ISOLATE_SIGDET_HF 0 0 RX_SIGDEF_HF_FILT_OVR_DIS 1 1 RX_SIGDEF_HF_FILT_OVR 2 2 RX_SIGDET_LF_OUT_FILT_EN 3 3 RESERVED_15_4 4 15 ixDPCSSYS_CR3_RAWAONLANE0_DIG_STATS 2 0x4032 3 0 4294967295 RX_VREFGEN_MASTER 0 0 RX_PMA_SQ_OUT 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR3_RAWAONLANE0_DIG_RX_OVRD_OUT_1 2 0x4033 11 0 4294967295 RX_PMA_SQ_CTRL_TRESH_OVRD_VAL 0 2 RX_PMA_SQ_CTRL_TRESH_OVRD_EN 3 3 RX_PMA_SQ_CTRL_RESP_OVRD_VAL 4 5 RX_PMA_SQ_CTRL_RESP_OVRD_EN 6 6 RX_PMA_SQ_WEAKKEEP_OVRD_VAL 7 7 RX_PMA_SQ_WEAKKEEP_OVRD_EN 8 8 RX_PMA_SQ_INV_POLARITY_OVRD_VAL 9 9 RX_PMA_SQ_INV_POLARITY_OVRD_EN 10 10 RX_PMA_SQ_EN_OVRD_VAL 11 11 RX_PMA_SQ_EN_OVRD_EN 12 12 RESERVED_15_13 13 15 ixDPCSSYS_CR3_RAWAONLANE0_DIG_RX_OVRD_OUT_2 2 0x4034 9 0 4294967295 RX_PMA_VREFGEN_EN_OVRD_VAL 0 0 RX_PMA_VREFGEN_EN_OVRD_EN 1 1 RX_SQ_OUT_OVRD_VAL 2 2 RX_SQ_OUT_OVRD_EN 3 3 RX_PMA_TERM_ACDC_OVRD_VAL 4 4 RX_PMA_TERM_ACDC_OVRD_EN 5 5 RX_PMA_TERM_EN_OVRD_VAL 6 6 RX_PMA_TERM_EN_OVRD_EN 7 7 RESERVED_15_8 8 15 ixDPCSSYS_CR3_RAWAONLANE0_DIG_RX_OVRD_OUT_3 2 0x4035 7 0 4294967295 RX_PMA_SIGDET_LF_FILTER_EN_OVRD_VAL 0 0 RX_PMA_SIGDET_LF_FILTER_EN_OVRD_EN 1 1 RX_PMA_SIGDET_LF_EN_OVRD_VAL 2 2 RX_PMA_SIGDET_LF_EN_OVRD_EN 3 3 RX_PMA_SIGDET_HF_EN_OVRD_VAL 4 4 RX_PMA_SIGDET_HF_EN_OVRD_EN 5 5 RESERVED_15_6 6 15 ixDPCSSYS_CR3_RAWAONLANE0_DIG_RX_SIGDET_CAL 2 0x4036 4 0 4294967295 RX_PMA_SIGDET_LF_THRESHOLD 0 2 RX_PMA_SIGDET_HF_THRESHOLD 3 5 RX_PMA_SIGDET_CAL_EN 6 6 RESERVED_15_7 7 15 ixDPCSSYS_CR3_RAWAONLANE0_DIG_RX_SIGDET_HF_CODE 2 0x4037 2 0 4294967295 RX_PMA_SIGDET_HF_CAL_TUNE 0 5 RESERVED_15_6 6 15 ixDPCSSYS_CR3_RAWAONLANE0_DIG_RX_SIGDET_LF_CODE 2 0x4038 2 0 4294967295 RX_PMA_SIGDET_LF_CAL_TUNE 0 5 RESERVED_15_6 6 15 ixDPCSSYS_CR3_RAWAONLANE0_DIG_RX_VREFGEN_EN 2 0x4039 2 0 4294967295 PULL_UP 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR3_RAWAONLANE0_DIG_CAL_IOFF_CODE 2 0x403a 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR3_RAWAONLANE0_DIG_CAL_ICONST_CODE 2 0x403b 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR3_RAWAONLANE0_DIG_CAL_VREFGEN_CODE 2 0x403c 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR3_RAWAONLANE0_DIG_RX_DCC_CAL_ICM_CODE_0 2 0x403d 2 0 4294967295 RX_DCC_CAL_ICM_CODE 0 9 RESERVED_15_10 10 15 ixDPCSSYS_CR3_RAWAONLANE0_DIG_RX_DCC_CAL_IDF_CODE_0 2 0x403e 2 0 4294967295 RX_DCC_CAL_IDF_CODE 0 9 RESERVED_15_10 10 15 ixDPCSSYS_CR3_RAWAONLANE0_DIG_RX_DCC_CAL_QCM_CODE_0 2 0x403f 2 0 4294967295 RX_DCC_CAL_QCM_CODE 0 9 RESERVED_15_10 10 15 ixDPCSSYS_CR3_RAWAONLANE0_DIG_RX_DCC_CAL_QDF_CODE_0 2 0x4040 2 0 4294967295 RX_DCC_CAL_QDF_CODE 0 9 RESERVED_15_10 10 15 ixDPCSSYS_CR3_RAWAONLANE0_DIG_RX_DCC_CAL_ICM_CODE_1 2 0x4041 2 0 4294967295 RX_DCC_CAL_ICM_CODE 0 9 RESERVED_15_10 10 15 ixDPCSSYS_CR3_RAWAONLANE0_DIG_RX_DCC_CAL_IDF_CODE_1 2 0x4042 2 0 4294967295 RX_DCC_CAL_IDF_CODE 0 9 RESERVED_15_10 10 15 ixDPCSSYS_CR3_RAWAONLANE0_DIG_RX_DCC_CAL_QCM_CODE_1 2 0x4043 2 0 4294967295 RX_DCC_CAL_QCM_CODE 0 9 RESERVED_15_10 10 15 ixDPCSSYS_CR3_RAWAONLANE0_DIG_RX_DCC_CAL_QDF_CODE_1 2 0x4044 2 0 4294967295 RX_DCC_CAL_QDF_CODE 0 9 RESERVED_15_10 10 15 ixDPCSSYS_CR3_RAWAONLANE0_DIG_TX_DCC_BANK_ADDR 2 0x4045 1 0 4294967295 ADDR 0 15 ixDPCSSYS_CR3_RAWAONLANE0_DIG_TX_DCC_BANK_DATA 2 0x4046 1 0 4294967295 DATA 0 15 ixDPCSSYS_CR3_RAWAONLANE0_DIG_TX_DCC_CONT 2 0x4047 2 0 4294967295 EN 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR3_RAWAONLANE0_DIG_MPLL_BG_CTL 2 0x4048 3 0 4294967295 MPLL_STATE_WAIT 0 0 MPLL_STATE_DLY_EN 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR3_RAWAONLANE0_DIG_SIGDET_OUT_OVRD 2 0x4049 5 0 4294967295 RX_SIGDET_HF_OUT_OVRD_VAL 0 0 RX_SIGDET_HF_OUT_OVRD_EN 1 1 RX_SIGDET_LF_OUT_OVRD_VAL 2 2 RX_SIGDET_LF_OUT_OVRD_EN 3 3 RESERVED_15_4 4 15 ixDPCSSYS_CR3_RAWAONLANE0_DIG_SIGDET_OUT_IN 2 0x404a 3 0 4294967295 RX_SIGDET_HF_OUT_OVRD_VAL 0 0 RX_SIGDET_LF_OUT_OVRD_VAL 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR3_RAWAONLANE0_DIG_FW_MM_CONFIG 2 0x404b 1 0 4294967295 DATA 0 0 ixDPCSSYS_CR3_RAWAONLANE0_DIG_FW_ADPT_CONFIG 2 0x404c 2 0 4294967295 REF_LVL_ADPT 0 7 FW_CONFIG 8 15 ixDPCSSYS_CR3_RAWAONLANE0_DIG_FW_CALIB_CONFIG 2 0x404d 1 0 4294967295 FW_CALIB 0 15 ixDPCSSYS_CR3_RAWAONLANE0_DIG_LANE_XCVR_MODE_OVRD_IN 2 0x404e 3 0 4294967295 LANE_XCVR_MODE_OVRD_VAL 0 1 LANE_XCVR_MODE_OVRD_EN 2 2 RESERVED_15_3 3 15 ixDPCSSYS_CR3_RAWAONLANE0_DIG_LANE_XCVR_MODE_IN 2 0x404f 2 0 4294967295 LANE_XCVR_MODE 0 1 RESERVED_15_2 2 15 ixDPCSSYS_CR3_RAWAONLANE0_DIG_RX_SIGDET_CONFIG 2 0x4050 4 0 4294967295 RX_SIGDET_HF_FILTER_COUNTER 0 4 RX_SIGDET_LF_FILTER_COUNTER 5 9 RX_SIGDET_LF_HOLD 10 10 RESERVED_15_11 11 15 ixDPCSSYS_CR3_RAWAONLANE0_DIG_TX_DCC_CONFIG 2 0x4051 1 0 4294967295 DATA 0 0 ixDPCSSYS_CR3_RAWAONLANE1_DIG_AFE_ATT_IDAC_OFST 2 0x4100 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR3_RAWAONLANE1_DIG_AFE_CTLE_IDAC_OFST 2 0x4101 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR3_RAWAONLANE1_DIG_RX_ADPT_IQ 2 0x4102 2 0 4294967295 IQ_ADPT_VAL 0 6 RESERVED_15_7 7 15 ixDPCSSYS_CR3_RAWAONLANE1_DIG_RX_ADAPT_FOM 2 0x4103 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR3_RAWAONLANE1_DIG_DFE_SUMMER_ODD_IDAC_OFST 2 0x4104 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR3_RAWAONLANE1_DIG_DFE_PHASE_EVEN_VDAC_OFST 2 0x4105 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR3_RAWAONLANE1_DIG_DFE_PHASE_ODD_VDAC_OFST 2 0x4106 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR3_RAWAONLANE1_DIG_DFE_EVEN_REF_LVL 2 0x4107 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR3_RAWAONLANE1_DIG_DFE_ODD_REF_LVL 2 0x4108 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR3_RAWAONLANE1_DIG_RX_PHSADJ_LIN 2 0x4109 2 0 4294967295 DATA 0 0 RESERVED_15_5 5 15 ixDPCSSYS_CR3_RAWAONLANE1_DIG_RX_PHSADJ_MAP 2 0x410a 2 0 4294967295 DATA 0 0 RESERVED_15_5 5 15 ixDPCSSYS_CR3_RAWAONLANE1_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST 2 0x410b 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR3_RAWAONLANE1_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST 2 0x410c 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR3_RAWAONLANE1_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST 2 0x410d 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR3_RAWAONLANE1_DIG_DFE_DATA_ODD_LOW_VDAC_OFST 2 0x410e 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR3_RAWAONLANE1_DIG_DFE_BYPASS_EVEN_VDAC_OFST 2 0x410f 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR3_RAWAONLANE1_DIG_DFE_BYPASS_ODD_VDAC_OFST 2 0x4110 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR3_RAWAONLANE1_DIG_DFE_ERROR_EVEN_VDAC_OFST 2 0x4111 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR3_RAWAONLANE1_DIG_DFE_ERROR_ODD_VDAC_OFST 2 0x4112 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR3_RAWAONLANE1_DIG_RX_IQ_PHASE_ADJUST 2 0x4113 2 0 4294967295 DATA 0 0 RESERVED_15_7 7 15 ixDPCSSYS_CR3_RAWAONLANE1_DIG_MPLLA_COARSE_TUNE 2 0x4114 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR3_RAWAONLANE1_DIG_MPLLB_COARSE_TUNE 2 0x4115 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR3_RAWAONLANE1_DIG_INIT_PWRUP_DONE 2 0x4116 3 0 4294967295 DATA 0 0 PH2_PWRUP_DONE 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR3_RAWAONLANE1_DIG_RX_ADPT_ATT 2 0x4117 2 0 4294967295 ATT_ADPT_VAL 0 7 RESERVED_15_8 8 15 ixDPCSSYS_CR3_RAWAONLANE1_DIG_RX_ADPT_VGA 2 0x4118 2 0 4294967295 VGA_ADPT_VAL 0 9 RESERVED_15_10 10 15 ixDPCSSYS_CR3_RAWAONLANE1_DIG_RX_ADPT_CTLE 2 0x4119 3 0 4294967295 CTLE_BOOST_ADPT_VAL 0 9 CTLE_POLE_ADPT_VAL 10 12 RESERVED_15_13 13 15 ixDPCSSYS_CR3_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP1 2 0x411a 2 0 4294967295 DFE_TAP1_ADPT_VAL 0 12 RESERVED_15_13 13 15 ixDPCSSYS_CR3_RAWAONLANE1_DIG_RX_ADAPT_DONE 2 0x411b 2 0 4294967295 DATA 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR3_RAWAONLANE1_DIG_FAST_FLAGS 2 0x411c 16 0 4294967295 FAST_RX_STARTUP_CAL 0 0 FAST_RX_ADAPT 1 1 FAST_RX_AFE_CAL 2 2 FAST_RX_DFE_CAL 3 3 FAST_RX_BYPASS_CAL 4 4 FAST_RX_REFLVL_CAL 5 5 FAST_RX_IQ_CAL 6 6 FAST_RX_AFE_ADAPT 7 7 FAST_RX_DFE_ADAPT 8 8 FAST_SUP 9 9 FAST_TX_CMN_MODE 10 10 FAST_TX_RXDET 11 11 FAST_RX_PWRUP 12 12 FAST_RX_VCO_WAIT 13 13 FAST_RX_VCO_CAL 14 14 RESERVED_15_15 15 15 ixDPCSSYS_CR3_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP2 2 0x411d 2 0 4294967295 DFE_TAP2_ADPT_VAL 0 11 RESERVED_15_12 12 15 ixDPCSSYS_CR3_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP3 2 0x411e 2 0 4294967295 DFE_TAP3_ADPT_VAL 0 11 RESERVED_15_12 12 15 ixDPCSSYS_CR3_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP4 2 0x411f 2 0 4294967295 DFE_TAP4_ADPT_VAL 0 11 RESERVED_15_12 12 15 ixDPCSSYS_CR3_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP5 2 0x4120 2 0 4294967295 DFE_TAP5_ADPT_VAL 0 11 RESERVED_15_12 12 15 ixDPCSSYS_CR3_RAWAONLANE1_DIG_RX_SLICER_CTRL_EVEN 2 0x4121 2 0 4294967295 RX_ANA_SLICER_CTRL_E 0 3 RESERVED_15_4 4 15 ixDPCSSYS_CR3_RAWAONLANE1_DIG_RX_SLICER_CTRL_ODD 2 0x4122 2 0 4294967295 RX_ANA_SLICER_CTRL_O 0 3 RESERVED_15_4 4 15 ixDPCSSYS_CR3_RAWAONLANE1_DIG_LANE_CMNCAL_MPLL_STATUS 2 0x4123 3 0 4294967295 LANE_CMNCAL_MPLL_INIT 0 0 LANE_CMNCAL_MPLL_DONE 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR3_RAWAONLANE1_DIG_ADPT_CTL_0 2 0x4124 1 0 4294967295 VAL 0 15 ixDPCSSYS_CR3_RAWAONLANE1_DIG_ADPT_CTL_1 2 0x4125 1 0 4294967295 VAL 0 15 ixDPCSSYS_CR3_RAWAONLANE1_DIG_ADPT_CTL_2 2 0x4126 1 0 4294967295 VAL 0 15 ixDPCSSYS_CR3_RAWAONLANE1_DIG_ADPT_CTL_3 2 0x4127 1 0 4294967295 VAL 0 15 ixDPCSSYS_CR3_RAWAONLANE1_DIG_ADPT_CTL_4 2 0x4128 1 0 4294967295 VAL 0 15 ixDPCSSYS_CR3_RAWAONLANE1_DIG_ADPT_CTL_5 2 0x4129 1 0 4294967295 VAL 0 15 ixDPCSSYS_CR3_RAWAONLANE1_DIG_ADPT_CTL_6 2 0x412a 1 0 4294967295 VAL 0 15 ixDPCSSYS_CR3_RAWAONLANE1_DIG_ADPT_CTL_7 2 0x412b 1 0 4294967295 VAL 0 15 ixDPCSSYS_CR3_RAWAONLANE1_DIG_MPLL_DISABLE 2 0x412c 3 0 4294967295 LANE_MPLLA_DISABLE 0 0 LANE_MPLLB_DISABLE 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR3_RAWAONLANE1_DIG_FAST_FLAGS_2 2 0x412d 16 0 4294967295 FAST_RX_CONT_CAL_ADAPT 0 0 FAST_RX_CONT_ADAPT 1 1 FAST_RX_CONT_DATA_CAL 2 2 FAST_RX_CONT_PHASE_CAL 3 3 FAST_RX_CONT_AFE_CAL 4 4 FAST_TX_CONT_DCC_CAL 5 5 FAST_RX_CONT_DCC_CAL 6 6 FAST_RX_CONT_VPHUD_CAL 7 7 FAST_RX_CONT_VREF_CAL 8 8 FAST_TX_DCC_CAL 9 9 FAST_RX_DCC_CAL 10 10 FAST_RX_VPHUD_CAL 11 11 FAST_RX_VREF_CAL 12 12 SKIP_TX_RTUNE_CAL 13 13 FAST_RX_SIGDET_CAL 14 14 RESERVED_15_15 15 15 ixDPCSSYS_CR3_RAWAONLANE1_DIG_LANE_CMNCAL_RCAL_STATUS 2 0x412e 3 0 4294967295 LANE_CMNCAL_RCAL_INIT 0 0 LANE_CMNCAL_RCAL_DONE 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR3_RAWAONLANE1_DIG_TXRX_OVRD_IN 2 0x412f 5 0 4294967295 RX_DISABLE_OVRD_VAL 0 0 RX_DISABLE_OVRD_EN 1 1 TX_DISABLE_OVRD_VAL 2 2 TX_DISABLE_OVRD_EN 3 3 RESERVED_15_4 4 15 ixDPCSSYS_CR3_RAWAONLANE1_DIG_RX_LOS_MASK_CTL 2 0x4130 2 0 4294967295 RX_LOS_MASK_CNT 0 8 RESERVED_15_9 9 15 ixDPCSSYS_CR3_RAWAONLANE1_DIG_RX_SIGDET_FILT_CTRL 2 0x4131 5 0 4294967295 ISOLATE_SIGDET_HF 0 0 RX_SIGDEF_HF_FILT_OVR_DIS 1 1 RX_SIGDEF_HF_FILT_OVR 2 2 RX_SIGDET_LF_OUT_FILT_EN 3 3 RESERVED_15_4 4 15 ixDPCSSYS_CR3_RAWAONLANE1_DIG_STATS 2 0x4132 3 0 4294967295 RX_VREFGEN_MASTER 0 0 RX_PMA_SQ_OUT 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR3_RAWAONLANE1_DIG_RX_OVRD_OUT_1 2 0x4133 11 0 4294967295 RX_PMA_SQ_CTRL_TRESH_OVRD_VAL 0 2 RX_PMA_SQ_CTRL_TRESH_OVRD_EN 3 3 RX_PMA_SQ_CTRL_RESP_OVRD_VAL 4 5 RX_PMA_SQ_CTRL_RESP_OVRD_EN 6 6 RX_PMA_SQ_WEAKKEEP_OVRD_VAL 7 7 RX_PMA_SQ_WEAKKEEP_OVRD_EN 8 8 RX_PMA_SQ_INV_POLARITY_OVRD_VAL 9 9 RX_PMA_SQ_INV_POLARITY_OVRD_EN 10 10 RX_PMA_SQ_EN_OVRD_VAL 11 11 RX_PMA_SQ_EN_OVRD_EN 12 12 RESERVED_15_13 13 15 ixDPCSSYS_CR3_RAWAONLANE1_DIG_RX_OVRD_OUT_2 2 0x4134 9 0 4294967295 RX_PMA_VREFGEN_EN_OVRD_VAL 0 0 RX_PMA_VREFGEN_EN_OVRD_EN 1 1 RX_SQ_OUT_OVRD_VAL 2 2 RX_SQ_OUT_OVRD_EN 3 3 RX_PMA_TERM_ACDC_OVRD_VAL 4 4 RX_PMA_TERM_ACDC_OVRD_EN 5 5 RX_PMA_TERM_EN_OVRD_VAL 6 6 RX_PMA_TERM_EN_OVRD_EN 7 7 RESERVED_15_8 8 15 ixDPCSSYS_CR3_RAWAONLANE1_DIG_RX_OVRD_OUT_3 2 0x4135 7 0 4294967295 RX_PMA_SIGDET_LF_FILTER_EN_OVRD_VAL 0 0 RX_PMA_SIGDET_LF_FILTER_EN_OVRD_EN 1 1 RX_PMA_SIGDET_LF_EN_OVRD_VAL 2 2 RX_PMA_SIGDET_LF_EN_OVRD_EN 3 3 RX_PMA_SIGDET_HF_EN_OVRD_VAL 4 4 RX_PMA_SIGDET_HF_EN_OVRD_EN 5 5 RESERVED_15_6 6 15 ixDPCSSYS_CR3_RAWAONLANE1_DIG_RX_SIGDET_CAL 2 0x4136 4 0 4294967295 RX_PMA_SIGDET_LF_THRESHOLD 0 2 RX_PMA_SIGDET_HF_THRESHOLD 3 5 RX_PMA_SIGDET_CAL_EN 6 6 RESERVED_15_7 7 15 ixDPCSSYS_CR3_RAWAONLANE1_DIG_RX_SIGDET_HF_CODE 2 0x4137 2 0 4294967295 RX_PMA_SIGDET_HF_CAL_TUNE 0 5 RESERVED_15_6 6 15 ixDPCSSYS_CR3_RAWAONLANE1_DIG_RX_SIGDET_LF_CODE 2 0x4138 2 0 4294967295 RX_PMA_SIGDET_LF_CAL_TUNE 0 5 RESERVED_15_6 6 15 ixDPCSSYS_CR3_RAWAONLANE1_DIG_RX_VREFGEN_EN 2 0x4139 2 0 4294967295 PULL_UP 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR3_RAWAONLANE1_DIG_CAL_IOFF_CODE 2 0x413a 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR3_RAWAONLANE1_DIG_CAL_ICONST_CODE 2 0x413b 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR3_RAWAONLANE1_DIG_CAL_VREFGEN_CODE 2 0x413c 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR3_RAWAONLANE1_DIG_RX_DCC_CAL_ICM_CODE_0 2 0x413d 2 0 4294967295 RX_DCC_CAL_ICM_CODE 0 9 RESERVED_15_10 10 15 ixDPCSSYS_CR3_RAWAONLANE1_DIG_RX_DCC_CAL_IDF_CODE_0 2 0x413e 2 0 4294967295 RX_DCC_CAL_IDF_CODE 0 9 RESERVED_15_10 10 15 ixDPCSSYS_CR3_RAWAONLANE1_DIG_RX_DCC_CAL_QCM_CODE_0 2 0x413f 2 0 4294967295 RX_DCC_CAL_QCM_CODE 0 9 RESERVED_15_10 10 15 ixDPCSSYS_CR3_RAWAONLANE1_DIG_RX_DCC_CAL_QDF_CODE_0 2 0x4140 2 0 4294967295 RX_DCC_CAL_QDF_CODE 0 9 RESERVED_15_10 10 15 ixDPCSSYS_CR3_RAWAONLANE1_DIG_RX_DCC_CAL_ICM_CODE_1 2 0x4141 2 0 4294967295 RX_DCC_CAL_ICM_CODE 0 9 RESERVED_15_10 10 15 ixDPCSSYS_CR3_RAWAONLANE1_DIG_RX_DCC_CAL_IDF_CODE_1 2 0x4142 2 0 4294967295 RX_DCC_CAL_IDF_CODE 0 9 RESERVED_15_10 10 15 ixDPCSSYS_CR3_RAWAONLANE1_DIG_RX_DCC_CAL_QCM_CODE_1 2 0x4143 2 0 4294967295 RX_DCC_CAL_QCM_CODE 0 9 RESERVED_15_10 10 15 ixDPCSSYS_CR3_RAWAONLANE1_DIG_RX_DCC_CAL_QDF_CODE_1 2 0x4144 2 0 4294967295 RX_DCC_CAL_QDF_CODE 0 9 RESERVED_15_10 10 15 ixDPCSSYS_CR3_RAWAONLANE1_DIG_TX_DCC_BANK_ADDR 2 0x4145 1 0 4294967295 ADDR 0 15 ixDPCSSYS_CR3_RAWAONLANE1_DIG_TX_DCC_BANK_DATA 2 0x4146 1 0 4294967295 DATA 0 15 ixDPCSSYS_CR3_RAWAONLANE1_DIG_TX_DCC_CONT 2 0x4147 2 0 4294967295 EN 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR3_RAWAONLANE1_DIG_MPLL_BG_CTL 2 0x4148 3 0 4294967295 MPLL_STATE_WAIT 0 0 MPLL_STATE_DLY_EN 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR3_RAWAONLANE1_DIG_SIGDET_OUT_OVRD 2 0x4149 5 0 4294967295 RX_SIGDET_HF_OUT_OVRD_VAL 0 0 RX_SIGDET_HF_OUT_OVRD_EN 1 1 RX_SIGDET_LF_OUT_OVRD_VAL 2 2 RX_SIGDET_LF_OUT_OVRD_EN 3 3 RESERVED_15_4 4 15 ixDPCSSYS_CR3_RAWAONLANE1_DIG_SIGDET_OUT_IN 2 0x414a 3 0 4294967295 RX_SIGDET_HF_OUT_OVRD_VAL 0 0 RX_SIGDET_LF_OUT_OVRD_VAL 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR3_RAWAONLANE1_DIG_FW_MM_CONFIG 2 0x414b 1 0 4294967295 DATA 0 0 ixDPCSSYS_CR3_RAWAONLANE1_DIG_FW_ADPT_CONFIG 2 0x414c 2 0 4294967295 REF_LVL_ADPT 0 7 FW_CONFIG 8 15 ixDPCSSYS_CR3_RAWAONLANE1_DIG_FW_CALIB_CONFIG 2 0x414d 1 0 4294967295 FW_CALIB 0 15 ixDPCSSYS_CR3_RAWAONLANE1_DIG_LANE_XCVR_MODE_OVRD_IN 2 0x414e 3 0 4294967295 LANE_XCVR_MODE_OVRD_VAL 0 1 LANE_XCVR_MODE_OVRD_EN 2 2 RESERVED_15_3 3 15 ixDPCSSYS_CR3_RAWAONLANE1_DIG_LANE_XCVR_MODE_IN 2 0x414f 2 0 4294967295 LANE_XCVR_MODE 0 1 RESERVED_15_2 2 15 ixDPCSSYS_CR3_RAWAONLANE1_DIG_RX_SIGDET_CONFIG 2 0x4150 4 0 4294967295 RX_SIGDET_HF_FILTER_COUNTER 0 4 RX_SIGDET_LF_FILTER_COUNTER 5 9 RX_SIGDET_LF_HOLD 10 10 RESERVED_15_11 11 15 ixDPCSSYS_CR3_RAWAONLANE1_DIG_TX_DCC_CONFIG 2 0x4151 1 0 4294967295 DATA 0 0 ixDPCSSYS_CR3_RAWAONLANE2_DIG_AFE_ATT_IDAC_OFST 2 0x4200 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR3_RAWAONLANE2_DIG_AFE_CTLE_IDAC_OFST 2 0x4201 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR3_RAWAONLANE2_DIG_RX_ADPT_IQ 2 0x4202 2 0 4294967295 IQ_ADPT_VAL 0 6 RESERVED_15_7 7 15 ixDPCSSYS_CR3_RAWAONLANE2_DIG_RX_ADAPT_FOM 2 0x4203 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR3_RAWAONLANE2_DIG_DFE_SUMMER_ODD_IDAC_OFST 2 0x4204 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR3_RAWAONLANE2_DIG_DFE_PHASE_EVEN_VDAC_OFST 2 0x4205 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR3_RAWAONLANE2_DIG_DFE_PHASE_ODD_VDAC_OFST 2 0x4206 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR3_RAWAONLANE2_DIG_DFE_EVEN_REF_LVL 2 0x4207 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR3_RAWAONLANE2_DIG_DFE_ODD_REF_LVL 2 0x4208 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR3_RAWAONLANE2_DIG_RX_PHSADJ_LIN 2 0x4209 2 0 4294967295 DATA 0 0 RESERVED_15_5 5 15 ixDPCSSYS_CR3_RAWAONLANE2_DIG_RX_PHSADJ_MAP 2 0x420a 2 0 4294967295 DATA 0 0 RESERVED_15_5 5 15 ixDPCSSYS_CR3_RAWAONLANE2_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST 2 0x420b 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR3_RAWAONLANE2_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST 2 0x420c 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR3_RAWAONLANE2_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST 2 0x420d 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR3_RAWAONLANE2_DIG_DFE_DATA_ODD_LOW_VDAC_OFST 2 0x420e 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR3_RAWAONLANE2_DIG_DFE_BYPASS_EVEN_VDAC_OFST 2 0x420f 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR3_RAWAONLANE2_DIG_DFE_BYPASS_ODD_VDAC_OFST 2 0x4210 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR3_RAWAONLANE2_DIG_DFE_ERROR_EVEN_VDAC_OFST 2 0x4211 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR3_RAWAONLANE2_DIG_DFE_ERROR_ODD_VDAC_OFST 2 0x4212 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR3_RAWAONLANE2_DIG_RX_IQ_PHASE_ADJUST 2 0x4213 2 0 4294967295 DATA 0 0 RESERVED_15_7 7 15 ixDPCSSYS_CR3_RAWAONLANE2_DIG_MPLLA_COARSE_TUNE 2 0x4214 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR3_RAWAONLANE2_DIG_MPLLB_COARSE_TUNE 2 0x4215 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR3_RAWAONLANE2_DIG_INIT_PWRUP_DONE 2 0x4216 3 0 4294967295 DATA 0 0 PH2_PWRUP_DONE 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR3_RAWAONLANE2_DIG_RX_ADPT_ATT 2 0x4217 2 0 4294967295 ATT_ADPT_VAL 0 7 RESERVED_15_8 8 15 ixDPCSSYS_CR3_RAWAONLANE2_DIG_RX_ADPT_VGA 2 0x4218 2 0 4294967295 VGA_ADPT_VAL 0 9 RESERVED_15_10 10 15 ixDPCSSYS_CR3_RAWAONLANE2_DIG_RX_ADPT_CTLE 2 0x4219 3 0 4294967295 CTLE_BOOST_ADPT_VAL 0 9 CTLE_POLE_ADPT_VAL 10 12 RESERVED_15_13 13 15 ixDPCSSYS_CR3_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP1 2 0x421a 2 0 4294967295 DFE_TAP1_ADPT_VAL 0 12 RESERVED_15_13 13 15 ixDPCSSYS_CR3_RAWAONLANE2_DIG_RX_ADAPT_DONE 2 0x421b 2 0 4294967295 DATA 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR3_RAWAONLANE2_DIG_FAST_FLAGS 2 0x421c 16 0 4294967295 FAST_RX_STARTUP_CAL 0 0 FAST_RX_ADAPT 1 1 FAST_RX_AFE_CAL 2 2 FAST_RX_DFE_CAL 3 3 FAST_RX_BYPASS_CAL 4 4 FAST_RX_REFLVL_CAL 5 5 FAST_RX_IQ_CAL 6 6 FAST_RX_AFE_ADAPT 7 7 FAST_RX_DFE_ADAPT 8 8 FAST_SUP 9 9 FAST_TX_CMN_MODE 10 10 FAST_TX_RXDET 11 11 FAST_RX_PWRUP 12 12 FAST_RX_VCO_WAIT 13 13 FAST_RX_VCO_CAL 14 14 RESERVED_15_15 15 15 ixDPCSSYS_CR3_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP2 2 0x421d 2 0 4294967295 DFE_TAP2_ADPT_VAL 0 11 RESERVED_15_12 12 15 ixDPCSSYS_CR3_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP3 2 0x421e 2 0 4294967295 DFE_TAP3_ADPT_VAL 0 11 RESERVED_15_12 12 15 ixDPCSSYS_CR3_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP4 2 0x421f 2 0 4294967295 DFE_TAP4_ADPT_VAL 0 11 RESERVED_15_12 12 15 ixDPCSSYS_CR3_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP5 2 0x4220 2 0 4294967295 DFE_TAP5_ADPT_VAL 0 11 RESERVED_15_12 12 15 ixDPCSSYS_CR3_RAWAONLANE2_DIG_RX_SLICER_CTRL_EVEN 2 0x4221 2 0 4294967295 RX_ANA_SLICER_CTRL_E 0 3 RESERVED_15_4 4 15 ixDPCSSYS_CR3_RAWAONLANE2_DIG_RX_SLICER_CTRL_ODD 2 0x4222 2 0 4294967295 RX_ANA_SLICER_CTRL_O 0 3 RESERVED_15_4 4 15 ixDPCSSYS_CR3_RAWAONLANE2_DIG_LANE_CMNCAL_MPLL_STATUS 2 0x4223 3 0 4294967295 LANE_CMNCAL_MPLL_INIT 0 0 LANE_CMNCAL_MPLL_DONE 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR3_RAWAONLANE2_DIG_ADPT_CTL_0 2 0x4224 1 0 4294967295 VAL 0 15 ixDPCSSYS_CR3_RAWAONLANE2_DIG_ADPT_CTL_1 2 0x4225 1 0 4294967295 VAL 0 15 ixDPCSSYS_CR3_RAWAONLANE2_DIG_ADPT_CTL_2 2 0x4226 1 0 4294967295 VAL 0 15 ixDPCSSYS_CR3_RAWAONLANE2_DIG_ADPT_CTL_3 2 0x4227 1 0 4294967295 VAL 0 15 ixDPCSSYS_CR3_RAWAONLANE2_DIG_ADPT_CTL_4 2 0x4228 1 0 4294967295 VAL 0 15 ixDPCSSYS_CR3_RAWAONLANE2_DIG_ADPT_CTL_5 2 0x4229 1 0 4294967295 VAL 0 15 ixDPCSSYS_CR3_RAWAONLANE2_DIG_ADPT_CTL_6 2 0x422a 1 0 4294967295 VAL 0 15 ixDPCSSYS_CR3_RAWAONLANE2_DIG_ADPT_CTL_7 2 0x422b 1 0 4294967295 VAL 0 15 ixDPCSSYS_CR3_RAWAONLANE2_DIG_MPLL_DISABLE 2 0x422c 3 0 4294967295 LANE_MPLLA_DISABLE 0 0 LANE_MPLLB_DISABLE 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR3_RAWAONLANE2_DIG_FAST_FLAGS_2 2 0x422d 16 0 4294967295 FAST_RX_CONT_CAL_ADAPT 0 0 FAST_RX_CONT_ADAPT 1 1 FAST_RX_CONT_DATA_CAL 2 2 FAST_RX_CONT_PHASE_CAL 3 3 FAST_RX_CONT_AFE_CAL 4 4 FAST_TX_CONT_DCC_CAL 5 5 FAST_RX_CONT_DCC_CAL 6 6 FAST_RX_CONT_VPHUD_CAL 7 7 FAST_RX_CONT_VREF_CAL 8 8 FAST_TX_DCC_CAL 9 9 FAST_RX_DCC_CAL 10 10 FAST_RX_VPHUD_CAL 11 11 FAST_RX_VREF_CAL 12 12 SKIP_TX_RTUNE_CAL 13 13 FAST_RX_SIGDET_CAL 14 14 RESERVED_15_15 15 15 ixDPCSSYS_CR3_RAWAONLANE2_DIG_LANE_CMNCAL_RCAL_STATUS 2 0x422e 3 0 4294967295 LANE_CMNCAL_RCAL_INIT 0 0 LANE_CMNCAL_RCAL_DONE 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR3_RAWAONLANE2_DIG_TXRX_OVRD_IN 2 0x422f 5 0 4294967295 RX_DISABLE_OVRD_VAL 0 0 RX_DISABLE_OVRD_EN 1 1 TX_DISABLE_OVRD_VAL 2 2 TX_DISABLE_OVRD_EN 3 3 RESERVED_15_4 4 15 ixDPCSSYS_CR3_RAWAONLANE2_DIG_RX_LOS_MASK_CTL 2 0x4230 2 0 4294967295 RX_LOS_MASK_CNT 0 8 RESERVED_15_9 9 15 ixDPCSSYS_CR3_RAWAONLANE2_DIG_RX_SIGDET_FILT_CTRL 2 0x4231 5 0 4294967295 ISOLATE_SIGDET_HF 0 0 RX_SIGDEF_HF_FILT_OVR_DIS 1 1 RX_SIGDEF_HF_FILT_OVR 2 2 RX_SIGDET_LF_OUT_FILT_EN 3 3 RESERVED_15_4 4 15 ixDPCSSYS_CR3_RAWAONLANE2_DIG_STATS 2 0x4232 3 0 4294967295 RX_VREFGEN_MASTER 0 0 RX_PMA_SQ_OUT 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR3_RAWAONLANE2_DIG_RX_OVRD_OUT_1 2 0x4233 11 0 4294967295 RX_PMA_SQ_CTRL_TRESH_OVRD_VAL 0 2 RX_PMA_SQ_CTRL_TRESH_OVRD_EN 3 3 RX_PMA_SQ_CTRL_RESP_OVRD_VAL 4 5 RX_PMA_SQ_CTRL_RESP_OVRD_EN 6 6 RX_PMA_SQ_WEAKKEEP_OVRD_VAL 7 7 RX_PMA_SQ_WEAKKEEP_OVRD_EN 8 8 RX_PMA_SQ_INV_POLARITY_OVRD_VAL 9 9 RX_PMA_SQ_INV_POLARITY_OVRD_EN 10 10 RX_PMA_SQ_EN_OVRD_VAL 11 11 RX_PMA_SQ_EN_OVRD_EN 12 12 RESERVED_15_13 13 15 ixDPCSSYS_CR3_RAWAONLANE2_DIG_RX_OVRD_OUT_2 2 0x4234 9 0 4294967295 RX_PMA_VREFGEN_EN_OVRD_VAL 0 0 RX_PMA_VREFGEN_EN_OVRD_EN 1 1 RX_SQ_OUT_OVRD_VAL 2 2 RX_SQ_OUT_OVRD_EN 3 3 RX_PMA_TERM_ACDC_OVRD_VAL 4 4 RX_PMA_TERM_ACDC_OVRD_EN 5 5 RX_PMA_TERM_EN_OVRD_VAL 6 6 RX_PMA_TERM_EN_OVRD_EN 7 7 RESERVED_15_8 8 15 ixDPCSSYS_CR3_RAWAONLANE2_DIG_RX_OVRD_OUT_3 2 0x4235 7 0 4294967295 RX_PMA_SIGDET_LF_FILTER_EN_OVRD_VAL 0 0 RX_PMA_SIGDET_LF_FILTER_EN_OVRD_EN 1 1 RX_PMA_SIGDET_LF_EN_OVRD_VAL 2 2 RX_PMA_SIGDET_LF_EN_OVRD_EN 3 3 RX_PMA_SIGDET_HF_EN_OVRD_VAL 4 4 RX_PMA_SIGDET_HF_EN_OVRD_EN 5 5 RESERVED_15_6 6 15 ixDPCSSYS_CR3_RAWAONLANE2_DIG_RX_SIGDET_CAL 2 0x4236 4 0 4294967295 RX_PMA_SIGDET_LF_THRESHOLD 0 2 RX_PMA_SIGDET_HF_THRESHOLD 3 5 RX_PMA_SIGDET_CAL_EN 6 6 RESERVED_15_7 7 15 ixDPCSSYS_CR3_RAWAONLANE2_DIG_RX_SIGDET_HF_CODE 2 0x4237 2 0 4294967295 RX_PMA_SIGDET_HF_CAL_TUNE 0 5 RESERVED_15_6 6 15 ixDPCSSYS_CR3_RAWAONLANE2_DIG_RX_SIGDET_LF_CODE 2 0x4238 2 0 4294967295 RX_PMA_SIGDET_LF_CAL_TUNE 0 5 RESERVED_15_6 6 15 ixDPCSSYS_CR3_RAWAONLANE2_DIG_RX_VREFGEN_EN 2 0x4239 2 0 4294967295 PULL_UP 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR3_RAWAONLANE2_DIG_CAL_IOFF_CODE 2 0x423a 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR3_RAWAONLANE2_DIG_CAL_ICONST_CODE 2 0x423b 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR3_RAWAONLANE2_DIG_CAL_VREFGEN_CODE 2 0x423c 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR3_RAWAONLANE2_DIG_RX_DCC_CAL_ICM_CODE_0 2 0x423d 2 0 4294967295 RX_DCC_CAL_ICM_CODE 0 9 RESERVED_15_10 10 15 ixDPCSSYS_CR3_RAWAONLANE2_DIG_RX_DCC_CAL_IDF_CODE_0 2 0x423e 2 0 4294967295 RX_DCC_CAL_IDF_CODE 0 9 RESERVED_15_10 10 15 ixDPCSSYS_CR3_RAWAONLANE2_DIG_RX_DCC_CAL_QCM_CODE_0 2 0x423f 2 0 4294967295 RX_DCC_CAL_QCM_CODE 0 9 RESERVED_15_10 10 15 ixDPCSSYS_CR3_RAWAONLANE2_DIG_RX_DCC_CAL_QDF_CODE_0 2 0x4240 2 0 4294967295 RX_DCC_CAL_QDF_CODE 0 9 RESERVED_15_10 10 15 ixDPCSSYS_CR3_RAWAONLANE2_DIG_RX_DCC_CAL_ICM_CODE_1 2 0x4241 2 0 4294967295 RX_DCC_CAL_ICM_CODE 0 9 RESERVED_15_10 10 15 ixDPCSSYS_CR3_RAWAONLANE2_DIG_RX_DCC_CAL_IDF_CODE_1 2 0x4242 2 0 4294967295 RX_DCC_CAL_IDF_CODE 0 9 RESERVED_15_10 10 15 ixDPCSSYS_CR3_RAWAONLANE2_DIG_RX_DCC_CAL_QCM_CODE_1 2 0x4243 2 0 4294967295 RX_DCC_CAL_QCM_CODE 0 9 RESERVED_15_10 10 15 ixDPCSSYS_CR3_RAWAONLANE2_DIG_RX_DCC_CAL_QDF_CODE_1 2 0x4244 2 0 4294967295 RX_DCC_CAL_QDF_CODE 0 9 RESERVED_15_10 10 15 ixDPCSSYS_CR3_RAWAONLANE2_DIG_TX_DCC_BANK_ADDR 2 0x4245 1 0 4294967295 ADDR 0 15 ixDPCSSYS_CR3_RAWAONLANE2_DIG_TX_DCC_BANK_DATA 2 0x4246 1 0 4294967295 DATA 0 15 ixDPCSSYS_CR3_RAWAONLANE2_DIG_TX_DCC_CONT 2 0x4247 2 0 4294967295 EN 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR3_RAWAONLANE2_DIG_MPLL_BG_CTL 2 0x4248 3 0 4294967295 MPLL_STATE_WAIT 0 0 MPLL_STATE_DLY_EN 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR3_RAWAONLANE2_DIG_SIGDET_OUT_OVRD 2 0x4249 5 0 4294967295 RX_SIGDET_HF_OUT_OVRD_VAL 0 0 RX_SIGDET_HF_OUT_OVRD_EN 1 1 RX_SIGDET_LF_OUT_OVRD_VAL 2 2 RX_SIGDET_LF_OUT_OVRD_EN 3 3 RESERVED_15_4 4 15 ixDPCSSYS_CR3_RAWAONLANE2_DIG_SIGDET_OUT_IN 2 0x424a 3 0 4294967295 RX_SIGDET_HF_OUT_OVRD_VAL 0 0 RX_SIGDET_LF_OUT_OVRD_VAL 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR3_RAWAONLANE2_DIG_FW_MM_CONFIG 2 0x424b 1 0 4294967295 DATA 0 0 ixDPCSSYS_CR3_RAWAONLANE2_DIG_FW_ADPT_CONFIG 2 0x424c 2 0 4294967295 REF_LVL_ADPT 0 7 FW_CONFIG 8 15 ixDPCSSYS_CR3_RAWAONLANE2_DIG_FW_CALIB_CONFIG 2 0x424d 1 0 4294967295 FW_CALIB 0 15 ixDPCSSYS_CR3_RAWAONLANE2_DIG_LANE_XCVR_MODE_OVRD_IN 2 0x424e 3 0 4294967295 LANE_XCVR_MODE_OVRD_VAL 0 1 LANE_XCVR_MODE_OVRD_EN 2 2 RESERVED_15_3 3 15 ixDPCSSYS_CR3_RAWAONLANE2_DIG_LANE_XCVR_MODE_IN 2 0x424f 2 0 4294967295 LANE_XCVR_MODE 0 1 RESERVED_15_2 2 15 ixDPCSSYS_CR3_RAWAONLANE2_DIG_RX_SIGDET_CONFIG 2 0x4250 4 0 4294967295 RX_SIGDET_HF_FILTER_COUNTER 0 4 RX_SIGDET_LF_FILTER_COUNTER 5 9 RX_SIGDET_LF_HOLD 10 10 RESERVED_15_11 11 15 ixDPCSSYS_CR3_RAWAONLANE2_DIG_TX_DCC_CONFIG 2 0x4251 1 0 4294967295 DATA 0 0 ixDPCSSYS_CR3_RAWAONLANE3_DIG_AFE_ATT_IDAC_OFST 2 0x4300 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR3_RAWAONLANE3_DIG_AFE_CTLE_IDAC_OFST 2 0x4301 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR3_RAWAONLANE3_DIG_RX_ADPT_IQ 2 0x4302 2 0 4294967295 IQ_ADPT_VAL 0 6 RESERVED_15_7 7 15 ixDPCSSYS_CR3_RAWAONLANE3_DIG_RX_ADAPT_FOM 2 0x4303 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR3_RAWAONLANE3_DIG_DFE_SUMMER_ODD_IDAC_OFST 2 0x4304 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR3_RAWAONLANE3_DIG_DFE_PHASE_EVEN_VDAC_OFST 2 0x4305 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR3_RAWAONLANE3_DIG_DFE_PHASE_ODD_VDAC_OFST 2 0x4306 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR3_RAWAONLANE3_DIG_DFE_EVEN_REF_LVL 2 0x4307 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR3_RAWAONLANE3_DIG_DFE_ODD_REF_LVL 2 0x4308 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR3_RAWAONLANE3_DIG_RX_PHSADJ_LIN 2 0x4309 2 0 4294967295 DATA 0 0 RESERVED_15_5 5 15 ixDPCSSYS_CR3_RAWAONLANE3_DIG_RX_PHSADJ_MAP 2 0x430a 2 0 4294967295 DATA 0 0 RESERVED_15_5 5 15 ixDPCSSYS_CR3_RAWAONLANE3_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST 2 0x430b 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR3_RAWAONLANE3_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST 2 0x430c 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR3_RAWAONLANE3_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST 2 0x430d 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR3_RAWAONLANE3_DIG_DFE_DATA_ODD_LOW_VDAC_OFST 2 0x430e 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR3_RAWAONLANE3_DIG_DFE_BYPASS_EVEN_VDAC_OFST 2 0x430f 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR3_RAWAONLANE3_DIG_DFE_BYPASS_ODD_VDAC_OFST 2 0x4310 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR3_RAWAONLANE3_DIG_DFE_ERROR_EVEN_VDAC_OFST 2 0x4311 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR3_RAWAONLANE3_DIG_DFE_ERROR_ODD_VDAC_OFST 2 0x4312 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR3_RAWAONLANE3_DIG_RX_IQ_PHASE_ADJUST 2 0x4313 2 0 4294967295 DATA 0 0 RESERVED_15_7 7 15 ixDPCSSYS_CR3_RAWAONLANE3_DIG_MPLLA_COARSE_TUNE 2 0x4314 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR3_RAWAONLANE3_DIG_MPLLB_COARSE_TUNE 2 0x4315 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR3_RAWAONLANE3_DIG_INIT_PWRUP_DONE 2 0x4316 3 0 4294967295 DATA 0 0 PH2_PWRUP_DONE 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR3_RAWAONLANE3_DIG_RX_ADPT_ATT 2 0x4317 2 0 4294967295 ATT_ADPT_VAL 0 7 RESERVED_15_8 8 15 ixDPCSSYS_CR3_RAWAONLANE3_DIG_RX_ADPT_VGA 2 0x4318 2 0 4294967295 VGA_ADPT_VAL 0 9 RESERVED_15_10 10 15 ixDPCSSYS_CR3_RAWAONLANE3_DIG_RX_ADPT_CTLE 2 0x4319 3 0 4294967295 CTLE_BOOST_ADPT_VAL 0 9 CTLE_POLE_ADPT_VAL 10 12 RESERVED_15_13 13 15 ixDPCSSYS_CR3_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP1 2 0x431a 2 0 4294967295 DFE_TAP1_ADPT_VAL 0 12 RESERVED_15_13 13 15 ixDPCSSYS_CR3_RAWAONLANE3_DIG_RX_ADAPT_DONE 2 0x431b 2 0 4294967295 DATA 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR3_RAWAONLANE3_DIG_FAST_FLAGS 2 0x431c 16 0 4294967295 FAST_RX_STARTUP_CAL 0 0 FAST_RX_ADAPT 1 1 FAST_RX_AFE_CAL 2 2 FAST_RX_DFE_CAL 3 3 FAST_RX_BYPASS_CAL 4 4 FAST_RX_REFLVL_CAL 5 5 FAST_RX_IQ_CAL 6 6 FAST_RX_AFE_ADAPT 7 7 FAST_RX_DFE_ADAPT 8 8 FAST_SUP 9 9 FAST_TX_CMN_MODE 10 10 FAST_TX_RXDET 11 11 FAST_RX_PWRUP 12 12 FAST_RX_VCO_WAIT 13 13 FAST_RX_VCO_CAL 14 14 RESERVED_15_15 15 15 ixDPCSSYS_CR3_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP2 2 0x431d 2 0 4294967295 DFE_TAP2_ADPT_VAL 0 11 RESERVED_15_12 12 15 ixDPCSSYS_CR3_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP3 2 0x431e 2 0 4294967295 DFE_TAP3_ADPT_VAL 0 11 RESERVED_15_12 12 15 ixDPCSSYS_CR3_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP4 2 0x431f 2 0 4294967295 DFE_TAP4_ADPT_VAL 0 11 RESERVED_15_12 12 15 ixDPCSSYS_CR3_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP5 2 0x4320 2 0 4294967295 DFE_TAP5_ADPT_VAL 0 11 RESERVED_15_12 12 15 ixDPCSSYS_CR3_RAWAONLANE3_DIG_RX_SLICER_CTRL_EVEN 2 0x4321 2 0 4294967295 RX_ANA_SLICER_CTRL_E 0 3 RESERVED_15_4 4 15 ixDPCSSYS_CR3_RAWAONLANE3_DIG_RX_SLICER_CTRL_ODD 2 0x4322 2 0 4294967295 RX_ANA_SLICER_CTRL_O 0 3 RESERVED_15_4 4 15 ixDPCSSYS_CR3_RAWAONLANE3_DIG_LANE_CMNCAL_MPLL_STATUS 2 0x4323 3 0 4294967295 LANE_CMNCAL_MPLL_INIT 0 0 LANE_CMNCAL_MPLL_DONE 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR3_RAWAONLANE3_DIG_ADPT_CTL_0 2 0x4324 1 0 4294967295 VAL 0 15 ixDPCSSYS_CR3_RAWAONLANE3_DIG_ADPT_CTL_1 2 0x4325 1 0 4294967295 VAL 0 15 ixDPCSSYS_CR3_RAWAONLANE3_DIG_ADPT_CTL_2 2 0x4326 1 0 4294967295 VAL 0 15 ixDPCSSYS_CR3_RAWAONLANE3_DIG_ADPT_CTL_3 2 0x4327 1 0 4294967295 VAL 0 15 ixDPCSSYS_CR3_RAWAONLANE3_DIG_ADPT_CTL_4 2 0x4328 1 0 4294967295 VAL 0 15 ixDPCSSYS_CR3_RAWAONLANE3_DIG_ADPT_CTL_5 2 0x4329 1 0 4294967295 VAL 0 15 ixDPCSSYS_CR3_RAWAONLANE3_DIG_ADPT_CTL_6 2 0x432a 1 0 4294967295 VAL 0 15 ixDPCSSYS_CR3_RAWAONLANE3_DIG_ADPT_CTL_7 2 0x432b 1 0 4294967295 VAL 0 15 ixDPCSSYS_CR3_RAWAONLANE3_DIG_MPLL_DISABLE 2 0x432c 3 0 4294967295 LANE_MPLLA_DISABLE 0 0 LANE_MPLLB_DISABLE 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR3_RAWAONLANE3_DIG_FAST_FLAGS_2 2 0x432d 16 0 4294967295 FAST_RX_CONT_CAL_ADAPT 0 0 FAST_RX_CONT_ADAPT 1 1 FAST_RX_CONT_DATA_CAL 2 2 FAST_RX_CONT_PHASE_CAL 3 3 FAST_RX_CONT_AFE_CAL 4 4 FAST_TX_CONT_DCC_CAL 5 5 FAST_RX_CONT_DCC_CAL 6 6 FAST_RX_CONT_VPHUD_CAL 7 7 FAST_RX_CONT_VREF_CAL 8 8 FAST_TX_DCC_CAL 9 9 FAST_RX_DCC_CAL 10 10 FAST_RX_VPHUD_CAL 11 11 FAST_RX_VREF_CAL 12 12 SKIP_TX_RTUNE_CAL 13 13 FAST_RX_SIGDET_CAL 14 14 RESERVED_15_15 15 15 ixDPCSSYS_CR3_RAWAONLANE3_DIG_LANE_CMNCAL_RCAL_STATUS 2 0x432e 3 0 4294967295 LANE_CMNCAL_RCAL_INIT 0 0 LANE_CMNCAL_RCAL_DONE 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR3_RAWAONLANE3_DIG_TXRX_OVRD_IN 2 0x432f 5 0 4294967295 RX_DISABLE_OVRD_VAL 0 0 RX_DISABLE_OVRD_EN 1 1 TX_DISABLE_OVRD_VAL 2 2 TX_DISABLE_OVRD_EN 3 3 RESERVED_15_4 4 15 ixDPCSSYS_CR3_RAWAONLANE3_DIG_RX_LOS_MASK_CTL 2 0x4330 2 0 4294967295 RX_LOS_MASK_CNT 0 8 RESERVED_15_9 9 15 ixDPCSSYS_CR3_RAWAONLANE3_DIG_RX_SIGDET_FILT_CTRL 2 0x4331 5 0 4294967295 ISOLATE_SIGDET_HF 0 0 RX_SIGDEF_HF_FILT_OVR_DIS 1 1 RX_SIGDEF_HF_FILT_OVR 2 2 RX_SIGDET_LF_OUT_FILT_EN 3 3 RESERVED_15_4 4 15 ixDPCSSYS_CR3_RAWAONLANE3_DIG_STATS 2 0x4332 3 0 4294967295 RX_VREFGEN_MASTER 0 0 RX_PMA_SQ_OUT 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR3_RAWAONLANE3_DIG_RX_OVRD_OUT_1 2 0x4333 11 0 4294967295 RX_PMA_SQ_CTRL_TRESH_OVRD_VAL 0 2 RX_PMA_SQ_CTRL_TRESH_OVRD_EN 3 3 RX_PMA_SQ_CTRL_RESP_OVRD_VAL 4 5 RX_PMA_SQ_CTRL_RESP_OVRD_EN 6 6 RX_PMA_SQ_WEAKKEEP_OVRD_VAL 7 7 RX_PMA_SQ_WEAKKEEP_OVRD_EN 8 8 RX_PMA_SQ_INV_POLARITY_OVRD_VAL 9 9 RX_PMA_SQ_INV_POLARITY_OVRD_EN 10 10 RX_PMA_SQ_EN_OVRD_VAL 11 11 RX_PMA_SQ_EN_OVRD_EN 12 12 RESERVED_15_13 13 15 ixDPCSSYS_CR3_RAWAONLANE3_DIG_RX_OVRD_OUT_2 2 0x4334 9 0 4294967295 RX_PMA_VREFGEN_EN_OVRD_VAL 0 0 RX_PMA_VREFGEN_EN_OVRD_EN 1 1 RX_SQ_OUT_OVRD_VAL 2 2 RX_SQ_OUT_OVRD_EN 3 3 RX_PMA_TERM_ACDC_OVRD_VAL 4 4 RX_PMA_TERM_ACDC_OVRD_EN 5 5 RX_PMA_TERM_EN_OVRD_VAL 6 6 RX_PMA_TERM_EN_OVRD_EN 7 7 RESERVED_15_8 8 15 ixDPCSSYS_CR3_RAWAONLANE3_DIG_RX_OVRD_OUT_3 2 0x4335 7 0 4294967295 RX_PMA_SIGDET_LF_FILTER_EN_OVRD_VAL 0 0 RX_PMA_SIGDET_LF_FILTER_EN_OVRD_EN 1 1 RX_PMA_SIGDET_LF_EN_OVRD_VAL 2 2 RX_PMA_SIGDET_LF_EN_OVRD_EN 3 3 RX_PMA_SIGDET_HF_EN_OVRD_VAL 4 4 RX_PMA_SIGDET_HF_EN_OVRD_EN 5 5 RESERVED_15_6 6 15 ixDPCSSYS_CR3_RAWAONLANE3_DIG_RX_SIGDET_CAL 2 0x4336 4 0 4294967295 RX_PMA_SIGDET_LF_THRESHOLD 0 2 RX_PMA_SIGDET_HF_THRESHOLD 3 5 RX_PMA_SIGDET_CAL_EN 6 6 RESERVED_15_7 7 15 ixDPCSSYS_CR3_RAWAONLANE3_DIG_RX_SIGDET_HF_CODE 2 0x4337 2 0 4294967295 RX_PMA_SIGDET_HF_CAL_TUNE 0 5 RESERVED_15_6 6 15 ixDPCSSYS_CR3_RAWAONLANE3_DIG_RX_SIGDET_LF_CODE 2 0x4338 2 0 4294967295 RX_PMA_SIGDET_LF_CAL_TUNE 0 5 RESERVED_15_6 6 15 ixDPCSSYS_CR3_RAWAONLANE3_DIG_RX_VREFGEN_EN 2 0x4339 2 0 4294967295 PULL_UP 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR3_RAWAONLANE3_DIG_CAL_IOFF_CODE 2 0x433a 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR3_RAWAONLANE3_DIG_CAL_ICONST_CODE 2 0x433b 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR3_RAWAONLANE3_DIG_CAL_VREFGEN_CODE 2 0x433c 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR3_RAWAONLANE3_DIG_RX_DCC_CAL_ICM_CODE_0 2 0x433d 2 0 4294967295 RX_DCC_CAL_ICM_CODE 0 9 RESERVED_15_10 10 15 ixDPCSSYS_CR3_RAWAONLANE3_DIG_RX_DCC_CAL_IDF_CODE_0 2 0x433e 2 0 4294967295 RX_DCC_CAL_IDF_CODE 0 9 RESERVED_15_10 10 15 ixDPCSSYS_CR3_RAWAONLANE3_DIG_RX_DCC_CAL_QCM_CODE_0 2 0x433f 2 0 4294967295 RX_DCC_CAL_QCM_CODE 0 9 RESERVED_15_10 10 15 ixDPCSSYS_CR3_RAWAONLANE3_DIG_RX_DCC_CAL_QDF_CODE_0 2 0x4340 2 0 4294967295 RX_DCC_CAL_QDF_CODE 0 9 RESERVED_15_10 10 15 ixDPCSSYS_CR3_RAWAONLANE3_DIG_RX_DCC_CAL_ICM_CODE_1 2 0x4341 2 0 4294967295 RX_DCC_CAL_ICM_CODE 0 9 RESERVED_15_10 10 15 ixDPCSSYS_CR3_RAWAONLANE3_DIG_RX_DCC_CAL_IDF_CODE_1 2 0x4342 2 0 4294967295 RX_DCC_CAL_IDF_CODE 0 9 RESERVED_15_10 10 15 ixDPCSSYS_CR3_RAWAONLANE3_DIG_RX_DCC_CAL_QCM_CODE_1 2 0x4343 2 0 4294967295 RX_DCC_CAL_QCM_CODE 0 9 RESERVED_15_10 10 15 ixDPCSSYS_CR3_RAWAONLANE3_DIG_RX_DCC_CAL_QDF_CODE_1 2 0x4344 2 0 4294967295 RX_DCC_CAL_QDF_CODE 0 9 RESERVED_15_10 10 15 ixDPCSSYS_CR3_RAWAONLANE3_DIG_TX_DCC_BANK_ADDR 2 0x4345 1 0 4294967295 ADDR 0 15 ixDPCSSYS_CR3_RAWAONLANE3_DIG_TX_DCC_BANK_DATA 2 0x4346 1 0 4294967295 DATA 0 15 ixDPCSSYS_CR3_RAWAONLANE3_DIG_TX_DCC_CONT 2 0x4347 2 0 4294967295 EN 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR3_RAWAONLANE3_DIG_MPLL_BG_CTL 2 0x4348 3 0 4294967295 MPLL_STATE_WAIT 0 0 MPLL_STATE_DLY_EN 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR3_RAWAONLANE3_DIG_SIGDET_OUT_OVRD 2 0x4349 5 0 4294967295 RX_SIGDET_HF_OUT_OVRD_VAL 0 0 RX_SIGDET_HF_OUT_OVRD_EN 1 1 RX_SIGDET_LF_OUT_OVRD_VAL 2 2 RX_SIGDET_LF_OUT_OVRD_EN 3 3 RESERVED_15_4 4 15 ixDPCSSYS_CR3_RAWAONLANE3_DIG_SIGDET_OUT_IN 2 0x434a 3 0 4294967295 RX_SIGDET_HF_OUT_OVRD_VAL 0 0 RX_SIGDET_LF_OUT_OVRD_VAL 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR3_RAWAONLANE3_DIG_FW_MM_CONFIG 2 0x434b 1 0 4294967295 DATA 0 0 ixDPCSSYS_CR3_RAWAONLANE3_DIG_FW_ADPT_CONFIG 2 0x434c 2 0 4294967295 REF_LVL_ADPT 0 7 FW_CONFIG 8 15 ixDPCSSYS_CR3_RAWAONLANE3_DIG_FW_CALIB_CONFIG 2 0x434d 1 0 4294967295 FW_CALIB 0 15 ixDPCSSYS_CR3_RAWAONLANE3_DIG_LANE_XCVR_MODE_OVRD_IN 2 0x434e 3 0 4294967295 LANE_XCVR_MODE_OVRD_VAL 0 1 LANE_XCVR_MODE_OVRD_EN 2 2 RESERVED_15_3 3 15 ixDPCSSYS_CR3_RAWAONLANE3_DIG_LANE_XCVR_MODE_IN 2 0x434f 2 0 4294967295 LANE_XCVR_MODE 0 1 RESERVED_15_2 2 15 ixDPCSSYS_CR3_RAWAONLANE3_DIG_RX_SIGDET_CONFIG 2 0x4350 4 0 4294967295 RX_SIGDET_HF_FILTER_COUNTER 0 4 RX_SIGDET_LF_FILTER_COUNTER 5 9 RX_SIGDET_LF_HOLD 10 10 RESERVED_15_11 11 15 ixDPCSSYS_CR3_RAWAONLANE3_DIG_TX_DCC_CONFIG 2 0x4351 1 0 4294967295 DATA 0 0 ixDPCSSYS_CR3_RAWAONLANEX_DIG_AFE_ATT_IDAC_OFST 2 0x7000 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR3_RAWAONLANEX_DIG_AFE_CTLE_IDAC_OFST 2 0x7001 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR3_RAWAONLANEX_DIG_RX_ADPT_IQ 2 0x7002 2 0 4294967295 IQ_ADPT_VAL 0 6 RESERVED_15_7 7 15 ixDPCSSYS_CR3_RAWAONLANEX_DIG_RX_ADAPT_FOM 2 0x7003 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR3_RAWAONLANEX_DIG_DFE_SUMMER_ODD_IDAC_OFST 2 0x7004 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR3_RAWAONLANEX_DIG_DFE_PHASE_EVEN_VDAC_OFST 2 0x7005 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR3_RAWAONLANEX_DIG_DFE_PHASE_ODD_VDAC_OFST 2 0x7006 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR3_RAWAONLANEX_DIG_DFE_EVEN_REF_LVL 2 0x7007 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR3_RAWAONLANEX_DIG_DFE_ODD_REF_LVL 2 0x7008 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR3_RAWAONLANEX_DIG_RX_PHSADJ_LIN 2 0x7009 2 0 4294967295 DATA 0 0 RESERVED_15_5 5 15 ixDPCSSYS_CR3_RAWAONLANEX_DIG_RX_PHSADJ_MAP 2 0x700a 2 0 4294967295 DATA 0 0 RESERVED_15_5 5 15 ixDPCSSYS_CR3_RAWAONLANEX_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST 2 0x700b 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR3_RAWAONLANEX_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST 2 0x700c 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR3_RAWAONLANEX_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST 2 0x700d 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR3_RAWAONLANEX_DIG_DFE_DATA_ODD_LOW_VDAC_OFST 2 0x700e 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR3_RAWAONLANEX_DIG_DFE_BYPASS_EVEN_VDAC_OFST 2 0x700f 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR3_RAWAONLANEX_DIG_DFE_BYPASS_ODD_VDAC_OFST 2 0x7010 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR3_RAWAONLANEX_DIG_DFE_ERROR_EVEN_VDAC_OFST 2 0x7011 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR3_RAWAONLANEX_DIG_DFE_ERROR_ODD_VDAC_OFST 2 0x7012 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR3_RAWAONLANEX_DIG_RX_IQ_PHASE_ADJUST 2 0x7013 2 0 4294967295 DATA 0 0 RESERVED_15_7 7 15 ixDPCSSYS_CR3_RAWAONLANEX_DIG_MPLLA_COARSE_TUNE 2 0x7014 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR3_RAWAONLANEX_DIG_MPLLB_COARSE_TUNE 2 0x7015 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR3_RAWAONLANEX_DIG_INIT_PWRUP_DONE 2 0x7016 3 0 4294967295 DATA 0 0 PH2_PWRUP_DONE 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR3_RAWAONLANEX_DIG_RX_ADPT_ATT 2 0x7017 2 0 4294967295 ATT_ADPT_VAL 0 7 RESERVED_15_8 8 15 ixDPCSSYS_CR3_RAWAONLANEX_DIG_RX_ADPT_VGA 2 0x7018 2 0 4294967295 VGA_ADPT_VAL 0 9 RESERVED_15_10 10 15 ixDPCSSYS_CR3_RAWAONLANEX_DIG_RX_ADPT_CTLE 2 0x7019 3 0 4294967295 CTLE_BOOST_ADPT_VAL 0 9 CTLE_POLE_ADPT_VAL 10 12 RESERVED_15_13 13 15 ixDPCSSYS_CR3_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP1 2 0x701a 2 0 4294967295 DFE_TAP1_ADPT_VAL 0 12 RESERVED_15_13 13 15 ixDPCSSYS_CR3_RAWAONLANEX_DIG_RX_ADAPT_DONE 2 0x701b 2 0 4294967295 DATA 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR3_RAWAONLANEX_DIG_FAST_FLAGS 2 0x701c 16 0 4294967295 FAST_RX_STARTUP_CAL 0 0 FAST_RX_ADAPT 1 1 FAST_RX_AFE_CAL 2 2 FAST_RX_DFE_CAL 3 3 FAST_RX_BYPASS_CAL 4 4 FAST_RX_REFLVL_CAL 5 5 FAST_RX_IQ_CAL 6 6 FAST_RX_AFE_ADAPT 7 7 FAST_RX_DFE_ADAPT 8 8 FAST_SUP 9 9 FAST_TX_CMN_MODE 10 10 FAST_TX_RXDET 11 11 FAST_RX_PWRUP 12 12 FAST_RX_VCO_WAIT 13 13 FAST_RX_VCO_CAL 14 14 RESERVED_15_15 15 15 ixDPCSSYS_CR3_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP2 2 0x701d 2 0 4294967295 DFE_TAP2_ADPT_VAL 0 11 RESERVED_15_12 12 15 ixDPCSSYS_CR3_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP3 2 0x701e 2 0 4294967295 DFE_TAP3_ADPT_VAL 0 11 RESERVED_15_12 12 15 ixDPCSSYS_CR3_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP4 2 0x701f 2 0 4294967295 DFE_TAP4_ADPT_VAL 0 11 RESERVED_15_12 12 15 ixDPCSSYS_CR3_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP5 2 0x7020 2 0 4294967295 DFE_TAP5_ADPT_VAL 0 11 RESERVED_15_12 12 15 ixDPCSSYS_CR3_RAWAONLANEX_DIG_RX_SLICER_CTRL_EVEN 2 0x7021 2 0 4294967295 RX_ANA_SLICER_CTRL_E 0 3 RESERVED_15_4 4 15 ixDPCSSYS_CR3_RAWAONLANEX_DIG_RX_SLICER_CTRL_ODD 2 0x7022 2 0 4294967295 RX_ANA_SLICER_CTRL_O 0 3 RESERVED_15_4 4 15 ixDPCSSYS_CR3_RAWAONLANEX_DIG_LANE_CMNCAL_MPLL_STATUS 2 0x7023 3 0 4294967295 LANE_CMNCAL_MPLL_INIT 0 0 LANE_CMNCAL_MPLL_DONE 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR3_RAWAONLANEX_DIG_ADPT_CTL_0 2 0x7024 1 0 4294967295 VAL 0 15 ixDPCSSYS_CR3_RAWAONLANEX_DIG_ADPT_CTL_1 2 0x7025 1 0 4294967295 VAL 0 15 ixDPCSSYS_CR3_RAWAONLANEX_DIG_ADPT_CTL_2 2 0x7026 1 0 4294967295 VAL 0 15 ixDPCSSYS_CR3_RAWAONLANEX_DIG_ADPT_CTL_3 2 0x7027 1 0 4294967295 VAL 0 15 ixDPCSSYS_CR3_RAWAONLANEX_DIG_ADPT_CTL_4 2 0x7028 1 0 4294967295 VAL 0 15 ixDPCSSYS_CR3_RAWAONLANEX_DIG_ADPT_CTL_5 2 0x7029 1 0 4294967295 VAL 0 15 ixDPCSSYS_CR3_RAWAONLANEX_DIG_ADPT_CTL_6 2 0x702a 1 0 4294967295 VAL 0 15 ixDPCSSYS_CR3_RAWAONLANEX_DIG_ADPT_CTL_7 2 0x702b 1 0 4294967295 VAL 0 15 ixDPCSSYS_CR3_RAWAONLANEX_DIG_MPLL_DISABLE 2 0x702c 3 0 4294967295 LANE_MPLLA_DISABLE 0 0 LANE_MPLLB_DISABLE 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR3_RAWAONLANEX_DIG_FAST_FLAGS_2 2 0x702d 16 0 4294967295 FAST_RX_CONT_CAL_ADAPT 0 0 FAST_RX_CONT_ADAPT 1 1 FAST_RX_CONT_DATA_CAL 2 2 FAST_RX_CONT_PHASE_CAL 3 3 FAST_RX_CONT_AFE_CAL 4 4 FAST_TX_CONT_DCC_CAL 5 5 FAST_RX_CONT_DCC_CAL 6 6 FAST_RX_CONT_VPHUD_CAL 7 7 FAST_RX_CONT_VREF_CAL 8 8 FAST_TX_DCC_CAL 9 9 FAST_RX_DCC_CAL 10 10 FAST_RX_VPHUD_CAL 11 11 FAST_RX_VREF_CAL 12 12 SKIP_TX_RTUNE_CAL 13 13 FAST_RX_SIGDET_CAL 14 14 RESERVED_15_15 15 15 ixDPCSSYS_CR3_RAWAONLANEX_DIG_LANE_CMNCAL_RCAL_STATUS 2 0x702e 3 0 4294967295 LANE_CMNCAL_RCAL_INIT 0 0 LANE_CMNCAL_RCAL_DONE 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR3_RAWAONLANEX_DIG_TXRX_OVRD_IN 2 0x702f 5 0 4294967295 RX_DISABLE_OVRD_VAL 0 0 RX_DISABLE_OVRD_EN 1 1 TX_DISABLE_OVRD_VAL 2 2 TX_DISABLE_OVRD_EN 3 3 RESERVED_15_4 4 15 ixDPCSSYS_CR3_RAWAONLANEX_DIG_RX_LOS_MASK_CTL 2 0x7030 2 0 4294967295 RX_LOS_MASK_CNT 0 8 RESERVED_15_9 9 15 ixDPCSSYS_CR3_RAWAONLANEX_DIG_RX_SIGDET_FILT_CTRL 2 0x7031 5 0 4294967295 ISOLATE_SIGDET_HF 0 0 RX_SIGDEF_HF_FILT_OVR_DIS 1 1 RX_SIGDEF_HF_FILT_OVR 2 2 RX_SIGDET_LF_OUT_FILT_EN 3 3 RESERVED_15_4 4 15 ixDPCSSYS_CR3_RAWAONLANEX_DIG_STATS 2 0x7032 3 0 4294967295 RX_VREFGEN_MASTER 0 0 RX_PMA_SQ_OUT 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR3_RAWAONLANEX_DIG_RX_OVRD_OUT_1 2 0x7033 11 0 4294967295 RX_PMA_SQ_CTRL_TRESH_OVRD_VAL 0 2 RX_PMA_SQ_CTRL_TRESH_OVRD_EN 3 3 RX_PMA_SQ_CTRL_RESP_OVRD_VAL 4 5 RX_PMA_SQ_CTRL_RESP_OVRD_EN 6 6 RX_PMA_SQ_WEAKKEEP_OVRD_VAL 7 7 RX_PMA_SQ_WEAKKEEP_OVRD_EN 8 8 RX_PMA_SQ_INV_POLARITY_OVRD_VAL 9 9 RX_PMA_SQ_INV_POLARITY_OVRD_EN 10 10 RX_PMA_SQ_EN_OVRD_VAL 11 11 RX_PMA_SQ_EN_OVRD_EN 12 12 RESERVED_15_13 13 15 ixDPCSSYS_CR3_RAWAONLANEX_DIG_RX_OVRD_OUT_2 2 0x7034 9 0 4294967295 RX_PMA_VREFGEN_EN_OVRD_VAL 0 0 RX_PMA_VREFGEN_EN_OVRD_EN 1 1 RX_SQ_OUT_OVRD_VAL 2 2 RX_SQ_OUT_OVRD_EN 3 3 RX_PMA_TERM_ACDC_OVRD_VAL 4 4 RX_PMA_TERM_ACDC_OVRD_EN 5 5 RX_PMA_TERM_EN_OVRD_VAL 6 6 RX_PMA_TERM_EN_OVRD_EN 7 7 RESERVED_15_8 8 15 ixDPCSSYS_CR3_RAWAONLANEX_DIG_RX_OVRD_OUT_3 2 0x7035 7 0 4294967295 RX_PMA_SIGDET_LF_FILTER_EN_OVRD_VAL 0 0 RX_PMA_SIGDET_LF_FILTER_EN_OVRD_EN 1 1 RX_PMA_SIGDET_LF_EN_OVRD_VAL 2 2 RX_PMA_SIGDET_LF_EN_OVRD_EN 3 3 RX_PMA_SIGDET_HF_EN_OVRD_VAL 4 4 RX_PMA_SIGDET_HF_EN_OVRD_EN 5 5 RESERVED_15_6 6 15 ixDPCSSYS_CR3_RAWAONLANEX_DIG_RX_SIGDET_CAL 2 0x7036 4 0 4294967295 RX_PMA_SIGDET_LF_THRESHOLD 0 2 RX_PMA_SIGDET_HF_THRESHOLD 3 5 RX_PMA_SIGDET_CAL_EN 6 6 RESERVED_15_7 7 15 ixDPCSSYS_CR3_RAWAONLANEX_DIG_RX_SIGDET_HF_CODE 2 0x7037 2 0 4294967295 RX_PMA_SIGDET_HF_CAL_TUNE 0 5 RESERVED_15_6 6 15 ixDPCSSYS_CR3_RAWAONLANEX_DIG_RX_SIGDET_LF_CODE 2 0x7038 2 0 4294967295 RX_PMA_SIGDET_LF_CAL_TUNE 0 5 RESERVED_15_6 6 15 ixDPCSSYS_CR3_RAWAONLANEX_DIG_RX_VREFGEN_EN 2 0x7039 2 0 4294967295 PULL_UP 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR3_RAWAONLANEX_DIG_CAL_IOFF_CODE 2 0x703a 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR3_RAWAONLANEX_DIG_CAL_ICONST_CODE 2 0x703b 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR3_RAWAONLANEX_DIG_CAL_VREFGEN_CODE 2 0x703c 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR3_RAWAONLANEX_DIG_RX_DCC_CAL_ICM_CODE_0 2 0x703d 2 0 4294967295 RX_DCC_CAL_ICM_CODE 0 9 RESERVED_15_10 10 15 ixDPCSSYS_CR3_RAWAONLANEX_DIG_RX_DCC_CAL_IDF_CODE_0 2 0x703e 2 0 4294967295 RX_DCC_CAL_IDF_CODE 0 9 RESERVED_15_10 10 15 ixDPCSSYS_CR3_RAWAONLANEX_DIG_RX_DCC_CAL_QCM_CODE_0 2 0x703f 2 0 4294967295 RX_DCC_CAL_QCM_CODE 0 9 RESERVED_15_10 10 15 ixDPCSSYS_CR3_RAWAONLANEX_DIG_RX_DCC_CAL_QDF_CODE_0 2 0x7040 2 0 4294967295 RX_DCC_CAL_QDF_CODE 0 9 RESERVED_15_10 10 15 ixDPCSSYS_CR3_RAWAONLANEX_DIG_RX_DCC_CAL_ICM_CODE_1 2 0x7041 2 0 4294967295 RX_DCC_CAL_ICM_CODE 0 9 RESERVED_15_10 10 15 ixDPCSSYS_CR3_RAWAONLANEX_DIG_RX_DCC_CAL_IDF_CODE_1 2 0x7042 2 0 4294967295 RX_DCC_CAL_IDF_CODE 0 9 RESERVED_15_10 10 15 ixDPCSSYS_CR3_RAWAONLANEX_DIG_RX_DCC_CAL_QCM_CODE_1 2 0x7043 2 0 4294967295 RX_DCC_CAL_QCM_CODE 0 9 RESERVED_15_10 10 15 ixDPCSSYS_CR3_RAWAONLANEX_DIG_RX_DCC_CAL_QDF_CODE_1 2 0x7044 2 0 4294967295 RX_DCC_CAL_QDF_CODE 0 9 RESERVED_15_10 10 15 ixDPCSSYS_CR3_RAWAONLANEX_DIG_TX_DCC_BANK_ADDR 2 0x7045 1 0 4294967295 ADDR 0 15 ixDPCSSYS_CR3_RAWAONLANEX_DIG_TX_DCC_BANK_DATA 2 0x7046 1 0 4294967295 DATA 0 15 ixDPCSSYS_CR3_RAWAONLANEX_DIG_TX_DCC_CONT 2 0x7047 2 0 4294967295 EN 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR3_RAWAONLANEX_DIG_MPLL_BG_CTL 2 0x7048 3 0 4294967295 MPLL_STATE_WAIT 0 0 MPLL_STATE_DLY_EN 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR3_RAWAONLANEX_DIG_SIGDET_OUT_OVRD 2 0x7049 5 0 4294967295 RX_SIGDET_HF_OUT_OVRD_VAL 0 0 RX_SIGDET_HF_OUT_OVRD_EN 1 1 RX_SIGDET_LF_OUT_OVRD_VAL 2 2 RX_SIGDET_LF_OUT_OVRD_EN 3 3 RESERVED_15_4 4 15 ixDPCSSYS_CR3_RAWAONLANEX_DIG_SIGDET_OUT_IN 2 0x704a 3 0 4294967295 RX_SIGDET_HF_OUT_OVRD_VAL 0 0 RX_SIGDET_LF_OUT_OVRD_VAL 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR3_RAWAONLANEX_DIG_FW_MM_CONFIG 2 0x704b 1 0 4294967295 DATA 0 0 ixDPCSSYS_CR3_RAWAONLANEX_DIG_FW_ADPT_CONFIG 2 0x704c 2 0 4294967295 REF_LVL_ADPT 0 7 FW_CONFIG 8 15 ixDPCSSYS_CR3_RAWAONLANEX_DIG_FW_CALIB_CONFIG 2 0x704d 1 0 4294967295 FW_CALIB 0 15 ixDPCSSYS_CR3_RAWAONLANEX_DIG_LANE_XCVR_MODE_OVRD_IN 2 0x704e 3 0 4294967295 LANE_XCVR_MODE_OVRD_VAL 0 1 LANE_XCVR_MODE_OVRD_EN 2 2 RESERVED_15_3 3 15 ixDPCSSYS_CR3_RAWAONLANEX_DIG_LANE_XCVR_MODE_IN 2 0x704f 2 0 4294967295 LANE_XCVR_MODE 0 1 RESERVED_15_2 2 15 ixDPCSSYS_CR3_RAWAONLANEX_DIG_RX_SIGDET_CONFIG 2 0x7050 4 0 4294967295 RX_SIGDET_HF_FILTER_COUNTER 0 4 RX_SIGDET_LF_FILTER_COUNTER 5 9 RX_SIGDET_LF_HOLD 10 10 RESERVED_15_11 11 15 ixDPCSSYS_CR3_RAWAONLANEX_DIG_TX_DCC_CONFIG 2 0x7051 1 0 4294967295 DATA 0 0 ixDPCSSYS_CR3_SUPX_DIG_IDCODE_LO 2 0x8000 1 0 4294967295 DATA 0 0 ixDPCSSYS_CR3_SUPX_DIG_IDCODE_HI 2 0x8001 1 0 4294967295 DATA 0 0 ixDPCSSYS_CR3_SUPX_DIG_REFCLK_OVRD_IN 2 0x8002 12 0 4294967295 REF_CLK_EN 0 0 REF_CLK_EN_OVRD_EN 1 1 REF_USE_PAD 2 2 REF_USE_PAD_OVRD_EN 3 3 REF_CLK_RANGE 4 8 REF_CLK_RANGE_OVRD_EN 9 9 BG_EN 10 10 BG_EN_OVRD_EN 11 11 HDMIMODE_EN 12 12 HDMIMODE_ENABLE_OVRD_EN 13 13 SUP_PRE_HP_OVRD 14 14 SUP_PRE_HP_OVRD_EN 15 15 ixDPCSSYS_CR3_SUPX_DIG_MPLLA_DIV_CLK_OVRD_IN 2 0x8003 4 0 4294967295 MPLLA_DIV_CLK_EN 0 0 MPLLA_DIV_MULTIPLIER 1 8 MPLLA_DIV_OVRD_EN 9 9 RESERVED_15_10 10 15 ixDPCSSYS_CR3_SUPX_DIG_MPLLA_HDMI_CLK_OVRD_IN 2 0x8004 4 0 4294967295 MPLLA_HDMI_PIXEL_CLK_DIV 0 1 MPLLA_HDMI_DIV 2 4 MPLLA_HDMI_OVRD_EN 5 5 RESERVED_15_6 6 15 ixDPCSSYS_CR3_SUPX_DIG_MPLLB_DIV_CLK_OVRD_IN 2 0x8005 4 0 4294967295 MPLLB_DIV_CLK_EN 0 0 MPLLB_DIV_MULTIPLIER 1 8 MPLLB_DIV_OVRD_EN 9 9 RESERVED_15_10 10 15 ixDPCSSYS_CR3_SUPX_DIG_MPLLB_HDMI_CLK_OVRD_IN 2 0x8006 4 0 4294967295 MPLLB_HDMI_PIXEL_CLK_DIV 0 1 MPLLB_HDMI_DIV 2 4 MPLLB_HDMI_OVRD_EN 5 5 RESERVED_15_6 6 15 ixDPCSSYS_CR3_SUPX_DIG_MPLLA_OVRD_IN_0 2 0x8007 12 0 4294967295 MPLLA_EN 0 0 MPLLA_DIV5_CLK_EN 1 1 MPLLA_TX_CLK_DIV 2 4 OVRD_EN 5 5 MPLLA_V2I 6 7 MPLLA_STANDBY 8 8 MPLLA_FREQ_VCO 9 10 MPLLA_CAL_FORCE 11 11 MPLL_FRACN_EN 12 12 MPLLA_CLK_SYNC_OVRD 13 13 MPLLA_CLK_SYNC_OVRD_EN 14 14 RESERVED_15_15 15 15 ixDPCSSYS_CR3_SUPX_DIG_MPLLA_OVRD_IN_1 2 0x8008 2 0 4294967295 MPLLA_MULTIPLIER 0 11 RESERVED_15_12 12 15 ixDPCSSYS_CR3_SUPX_DIG_MPLLA_OVRD_IN_2 2 0x8009 7 0 4294967295 MPLLA_SSC_EN 0 0 MPLLA_SSC_OVRD_EN 1 1 MPLLA_SSC_UP_SPREAD 2 2 MPLLA_PMIX_EN 3 3 MPLLA_WORD_DIV2_EN 4 4 MPLLA_FRACN_CFG_UPDATE_EN 5 5 RESERVED_15_6 6 15 ixDPCSSYS_CR3_SUPX_DIG_MPLLA_SSC_PEAK_1 2 0x800a 1 0 4294967295 MPLLA_SSC_PEAK_15_0 0 15 ixDPCSSYS_CR3_SUPX_DIG_MPLLA_SSC_PEAK_2 2 0x800b 2 0 4294967295 MPLLA_SSC_PEAK_19_16 0 3 RESERVED_15_4 4 15 ixDPCSSYS_CR3_SUPX_DIG_MPLLA_SSC_STEPSIZE_1 2 0x800c 1 0 4294967295 MPLLA_SSC_STEPSIZE_15_0 0 15 ixDPCSSYS_CR3_SUPX_DIG_MPLLA_SSC_STEPSIZE_2 2 0x800d 2 0 4294967295 MPLLA_SSC_STEPSIZE_20_16 0 4 RESERVED_15_5 5 15 ixDPCSSYS_CR3_SUPX_DIG_MPLLA_OVRD_IN_3 2 0x800e 1 0 4294967295 MPLLA_FRACN_QUOT 0 15 ixDPCSSYS_CR3_SUPX_DIG_MPLLA_OVRD_IN_4 2 0x800f 1 0 4294967295 MPLLA_FRACN_REM 0 15 ixDPCSSYS_CR3_SUPX_DIG_MPLLA_OVRD_IN_5 2 0x8010 1 0 4294967295 MPLLA_FRACN_DEN 0 15 ixDPCSSYS_CR3_SUPX_DIG_MPLLA_CP_OVRD_IN 2 0x8011 3 0 4294967295 MPLLA_CP_PROP 0 6 MPLLA_CP_INT 7 13 RESERVED_15_14 14 15 ixDPCSSYS_CR3_SUPX_DIG_MPLLA_CP_GS_OVRD_IN 2 0x8012 4 0 4294967295 MPLLA_CP_PROP_GS 0 6 MPLLA_CP_PROP_GS_OVR_EN 7 7 MPLLA_CP_INT_GS 8 14 MPLLA_CP_INT_GS_OVR_EN 15 15 ixDPCSSYS_CR3_SUPX_DIG_MPLLB_OVRD_IN_0 2 0x8013 12 0 4294967295 MPLLB_EN 0 0 MPLLB_DIV5_CLK_EN 1 1 MPLLB_TX_CLK_DIV 2 4 OVRD_EN 5 5 MPLLB_V2I 6 7 MPLLB_STANDBY 8 8 MPLLB_FREQ_VCO 9 10 MPLLB_CAL_FORCE 11 11 MPLL_FRACN_EN 12 12 MPLLB_CLK_SYNC_OVRD 13 13 MPLLB_CLK_SYNC_OVRD_EN 14 14 RESERVED_15_15 15 15 ixDPCSSYS_CR3_SUPX_DIG_MPLLB_OVRD_IN_1 2 0x8014 2 0 4294967295 MPLLB_MULTIPLIER 0 11 RESERVED_15_12 12 15 ixDPCSSYS_CR3_SUPX_DIG_MPLLB_OVRD_IN_2 2 0x8015 7 0 4294967295 MPLLB_SSC_EN 0 0 MPLLB_SSC_OVRD_EN 1 1 MPLLB_SSC_UP_SPREAD 2 2 MPLLB_PMIX_EN 3 3 MPLLB_WORD_DIV2_EN 4 4 MPLLB_FRACN_CFG_UPDATE_EN 5 5 RESERVED_15_6 6 15 ixDPCSSYS_CR3_SUPX_DIG_MPLLB_SSC_PEAK_1 2 0x8016 1 0 4294967295 MPLLB_SSC_PEAK_15_0 0 15 ixDPCSSYS_CR3_SUPX_DIG_MPLLB_SSC_PEAK_2 2 0x8017 2 0 4294967295 MPLLB_SSC_PEAK_19_16 0 3 RESERVED_15_4 4 15 ixDPCSSYS_CR3_SUPX_DIG_MPLLB_SSC_STEPSIZE_1 2 0x8018 1 0 4294967295 MPLLB_SSC_STEPSIZE_15_0 0 15 ixDPCSSYS_CR3_SUPX_DIG_MPLLB_SSC_STEPSIZE_2 2 0x8019 2 0 4294967295 MPLLB_SSC_STEPSIZE_20_16 0 4 RESERVED_15_5 5 15 ixDPCSSYS_CR3_SUPX_DIG_MPLLB_OVRD_IN_3 2 0x801a 1 0 4294967295 MPLLB_FRACN_QUOT 0 15 ixDPCSSYS_CR3_SUPX_DIG_MPLLB_OVRD_IN_4 2 0x801b 1 0 4294967295 MPLLB_FRACN_REM 0 15 ixDPCSSYS_CR3_SUPX_DIG_MPLLB_OVRD_IN_5 2 0x801c 1 0 4294967295 MPLLB_FRACN_DEN 0 15 ixDPCSSYS_CR3_SUPX_DIG_MPLLB_CP_OVRD_IN 2 0x801d 3 0 4294967295 MPLLB_CP_PROP 0 6 MPLLB_CP_INT 7 13 RESERVED_15_14 14 15 ixDPCSSYS_CR3_SUPX_DIG_MPLLB_CP_GS_OVRD_IN 2 0x801e 4 0 4294967295 MPLLB_CP_PROP_GS 0 6 MPLLB_CP_PROP_GS_OVR_EN 7 7 MPLLB_CP_INT_GS 8 14 MPLLB_CP_INT_GS_OVR_EN 15 15 ixDPCSSYS_CR3_SUPX_DIG_SUP_OVRD_IN 2 0x801f 8 0 4294967295 PRESCALER_OVRD_EN 0 0 RTUNE_REQ 1 1 RTUNE_OVRD_EN 2 2 TX_CAL_CODE 3 6 TX_CAL_CODE_EN 7 7 REF_ALT_CLK_LP_SEL_OVRD 8 8 REF_ALT_CLK_LP_SEL_OVRD_EN 9 9 RESERVED_15_10 10 15 ixDPCSSYS_CR3_SUPX_DIG_PRESCALER_OVRD_IN 2 0x8020 6 0 4294967295 DCO_RANGE 0 1 DCO_FINETUNE 2 7 REF_CLK_MPLLB_DIV 8 10 REF_CLK_MPLLA_DIV 11 13 REF_CLKDET_RESULT 14 14 REF_CLKDET_EN 15 15 ixDPCSSYS_CR3_SUPX_DIG_SUP_OVRD_OUT 2 0x8021 12 0 4294967295 RTUNE_ACK 0 0 RTUNE_ACK_OVRD_EN 1 1 MPLLA_STATE 2 2 MPLLA_STATE_OVRD_EN 3 3 MPLLB_STATE 4 4 MPLLB_STATE_OVRD_EN 5 5 BG_LANE_STATE 6 6 BG_LANE_STATE_OVRD_EN 7 7 BG_SUP_STATE 8 8 BG_SUP_STATE_OVRD_EN 9 9 REF_CLK_ACK 10 10 RESERVED_15_11 11 15 ixDPCSSYS_CR3_SUPX_DIG_LVL_OVRD_IN 2 0x8022 7 0 4294967295 RX_VREF_CTRL 0 2 RX_VREF_CTRL_EN 3 3 TX_VBOOST_LVL 4 6 TX_VBOOST_LVL_EN 7 7 SUP_RX_VCO_VREF_SEL_OVR 8 10 SUP_RX_VCO_VREF_SEL_OVR_EN 11 11 RESERVED_15_12 12 15 ixDPCSSYS_CR3_SUPX_DIG_MPLLA_ASIC_IN_0 2 0x8024 9 0 4294967295 MPLLA_EN 0 0 MPLLA_DIV5_CLK_EN 1 1 MPLLA_TX_CLK_DIV 2 4 MPLLA_V2I 5 6 MPLLA_STANDBY 7 7 MPLLA_FREQ_VCO 8 9 MPLLA_CAL_FORCE 10 10 MPLLA_FRACN_EN 11 11 RESERVED_15_12 12 15 ixDPCSSYS_CR3_SUPX_DIG_MPLLA_ASIC_IN_1 2 0x8025 2 0 4294967295 MPLLA_MULTIPLIER 0 11 RESERVED_15_12 12 15 ixDPCSSYS_CR3_SUPX_DIG_MPLLA_ASIC_IN_2 2 0x8026 7 0 4294967295 MPLLA_SSC_EN 0 0 MPLLA_SSC_UP_SPREAD 1 1 MPLLA_PMIX_EN 2 2 MPLLA_WORD_DIV2_EN 3 3 MPLLA_FRACN_CFG_UPDATE_EN 4 4 MPLLA_CLK_SYNC 5 5 RESERVED_15_6 6 15 ixDPCSSYS_CR3_SUPX_DIG_MPLLA_ASIC_IN_3 2 0x8027 1 0 4294967295 MPLLA_SSC_PEAK_15_0 0 15 ixDPCSSYS_CR3_SUPX_DIG_MPLLA_ASIC_IN_4 2 0x8028 2 0 4294967295 MPLLA_SSC_PEAK_19_16 0 3 RESERVED_15_4 4 15 ixDPCSSYS_CR3_SUPX_DIG_MPLLA_ASIC_IN_5 2 0x8029 1 0 4294967295 MPLLA_SSC_STEPSIZE_15_0 0 15 ixDPCSSYS_CR3_SUPX_DIG_MPLLA_ASIC_IN_6 2 0x802a 2 0 4294967295 MPLLA_SSC_STEPSIZE_20_16 0 3 RESERVED_15_4 4 15 ixDPCSSYS_CR3_SUPX_DIG_MPLLB_ASIC_IN_0 2 0x802b 9 0 4294967295 MPLLB_EN 0 0 MPLLB_DIV5_CLK_EN 1 1 MPLLB_TX_CLK_DIV 2 4 MPLLB_V2I 5 6 MPLLB_STANDBY 7 7 MPLLB_FREQ_VCO 8 9 MPLLB_CAL_FORCE 10 10 MPLLB_FRACN_EN 11 11 RESERVED_15_12 12 15 ixDPCSSYS_CR3_SUPX_DIG_MPLLB_ASIC_IN_1 2 0x802c 2 0 4294967295 MPLLB_MULTIPLIER 0 11 RESERVED_15_12 12 15 ixDPCSSYS_CR3_SUPX_DIG_MPLLB_ASIC_IN_2 2 0x802d 7 0 4294967295 MPLLB_SSC_EN 0 0 MPLLB_SSC_UP_SPREAD 1 1 MPLLB_PMIX_EN 2 2 MPLLB_WORD_DIV2_EN 3 3 MPLLB_FRACN_CFG_UPDATE_EN 4 4 MPLLB_CLK_SYNC 5 5 RESERVED_15_6 6 15 ixDPCSSYS_CR3_SUPX_DIG_MPLLB_ASIC_IN_3 2 0x802e 1 0 4294967295 MPLLB_SSC_PEAK_15_0 0 15 ixDPCSSYS_CR3_SUPX_DIG_MPLLB_ASIC_IN_4 2 0x802f 2 0 4294967295 MPLLB_SSC_PEAK_19_16 0 3 RESERVED_15_4 4 15 ixDPCSSYS_CR3_SUPX_DIG_MPLLB_ASIC_IN_5 2 0x8030 1 0 4294967295 MPLLB_SSC_STEPSIZE_15_0 0 15 ixDPCSSYS_CR3_SUPX_DIG_MPLLB_ASIC_IN_6 2 0x8031 2 0 4294967295 MPLLB_SSC_STEPSIZE_20_16 0 3 RESERVED_15_4 4 15 ixDPCSSYS_CR3_SUPX_DIG_MPLLA_DIV_CLK_ASIC_IN 2 0x8032 3 0 4294967295 MPLLA_DIV_CLK_EN 0 0 MPLLA_DIV_MULTIPLIER 1 8 RESERVED_15_9 9 15 ixDPCSSYS_CR3_SUPX_DIG_MPLLA_HDMI_CLK_ASIC_IN 2 0x8033 3 0 4294967295 MPLLA_HDMI_PIXEL_CLK_DIV 0 1 MPLLA_HDMI_DIV 2 4 RESERVED_15_5 5 15 ixDPCSSYS_CR3_SUPX_DIG_MPLLB_DIV_CLK_ASIC_IN 2 0x8034 3 0 4294967295 MPLLB_DIV_CLK_EN 0 0 MPLLB_DIV_MULTIPLIER 1 8 RESERVED_15_9 9 15 ixDPCSSYS_CR3_SUPX_DIG_MPLLB_HDMI_CLK_ASIC_IN 2 0x8035 3 0 4294967295 MPLLB_HDMI_PIXEL_CLK_DIV 0 1 MPLLB_HDMI_DIV 2 4 RESERVED_15_5 5 15 ixDPCSSYS_CR3_SUPX_DIG_ASIC_IN 2 0x8036 12 0 4294967295 PHY_RESET 0 0 REF_CLK_EN 1 1 REF_USE_PAD 2 2 TEST_BURNIN 3 3 TEST_POWERDOWN 4 4 RTUNE_REQ 5 5 RTUNE_ACK 6 6 MPLLA_STATE 7 7 MPLLB_STATE 8 8 TEST_TX_REF_CLK_EN 9 9 REF_ALT_CLK_LP_SEL 10 10 RESERVED_15_11 11 15 ixDPCSSYS_CR3_SUPX_DIG_LVL_ASIC_IN 2 0x8037 4 0 4294967295 RX_VREF_CTRL 0 2 TX_VBOOST_LVL 3 5 SUP_RX_VCO_VREF_SEL 6 8 RESERVED_15_9 9 15 ixDPCSSYS_CR3_SUPX_DIG_BANDGAP_ASIC_IN 2 0x8038 2 0 4294967295 BG_EN 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR3_SUPX_DIG_MPLLA_CP_ASIC_IN 2 0x8039 3 0 4294967295 MPLLA_CP_PROP 0 6 MPLLA_CP_INT 7 13 RESERVED_15_14 14 15 ixDPCSSYS_CR3_SUPX_DIG_MPLLA_CP_GS_ASIC_IN 2 0x803a 3 0 4294967295 MPLLA_CP_PROP_GS 0 6 MPLLA_CP_INT_GS 7 13 RESERVED_15_14 14 15 ixDPCSSYS_CR3_SUPX_DIG_MPLLB_CP_ASIC_IN 2 0x803b 3 0 4294967295 MPLLB_CP_PROP 0 6 MPLLB_CP_INT 7 13 RESERVED_15_14 14 15 ixDPCSSYS_CR3_SUPX_DIG_MPLLB_CP_GS_ASIC_IN 2 0x803c 3 0 4294967295 MPLLB_CP_PROP_GS 0 6 MPLLB_CP_INT_GS 7 13 RESERVED_15_14 14 15 ixDPCSSYS_CR3_SUPX_ANA_PRESCALER_CTRL 2 0x8040 7 0 4294967295 PSCALER_ATB_SELECT 0 0 PSCALER_MEAS_VREG 0 0 PSCALER_OVRD_FAST_START 0 0 PSCALER_FAST_START_REG 0 0 PSCALER_VREG_BOOST 0 0 PSCALER_HYST_REF 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR3_SUPX_ANA_RTUNE_CTRL 2 0x8041 9 0 4294967295 RT_ATB 0 0 RT_SEL_ATBF 0 0 RT_SEL_ATBP 0 0 RT_VP4O8_EN 0 0 RT_DAC_CHOP 0 0 RT_DAC_MODE 0 0 RT_EN_FRCON 0 0 PSCALER_VREG_FB_DIV_CTRL 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR3_SUPX_ANA_BG1 2 0x8042 6 0 4294967295 SUP_SEL_VBG_VREF 0 0 SUP_SEL_VPHUD_VREF 0 0 NC4 4 4 SUP_SEL_VPLL_REF 0 0 RT_VREF_SEL 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR3_SUPX_ANA_BG2 2 0x8043 9 0 4294967295 SUP_BYPASS_BG 0 0 SUP_CHOP_EN 0 0 SUP_TEMP_MEAS 0 0 VPHUD_SELREF 0 0 ATB_EXT_MEAS_EN 0 0 RT_TX_OFFSET_EN 0 0 SUP_SEL_TX_SWING_VREF 0 0 PSCALER_VREG_OVERRIDE_RING_CTRL 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR3_SUPX_ANA_SWITCH_PWR_MEAS 2 0x8044 3 0 4294967295 SUP_ATB_SW 0 0 SUP_TIE 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR3_SUPX_ANA_BG3 2 0x8045 4 0 4294967295 SUP_SEL_RX_VCO_TC_VREF 0 0 SUP_SEL_RX_CAL_VREF 0 0 NC7_4 4 7 RESERVED_15_8 8 15 ixDPCSSYS_CR3_SUPX_ANA_MPLLA_MISC1 2 0x8046 7 0 4294967295 OVRD_GEAR_RC_FILT 0 0 OVRD_TEST_RC_FILT 0 0 TEST_VREG_DIV 0 0 VBG_EN 0 0 COUNT_SEL_LOCK 0 0 PHASE_SEL_LOCK 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR3_SUPX_ANA_MPLLA_MISC2 2 0x8047 8 0 4294967295 OVRD_PR_BYPASS 0 0 PR_BYPASS 0 0 OVRD_GEARSHIFT 0 0 GEARSHIFT_REG 0 0 TEST_LOCK_GEAR 0 0 EN_CAL_SPO 0 0 TEST_BOOST 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR3_SUPX_ANA_MPLLA_OVRD 2 0x8048 9 0 4294967295 OVRD_ENABLE 0 0 ENABLE_REG 0 0 OVRD_CAL 0 0 CAL_REG 0 0 OVRD_FB_CLK_EN 0 0 FB_CLK_EN_REG 0 0 OVRD_RESET 0 0 RESET_REG 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR3_SUPX_ANA_MPLLA_ATB1 2 0x8049 3 0 4294967295 MEAS_IV_WRAP 0 0 ATB_SELECT 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR3_SUPX_ANA_MPLLA_ATB2 2 0x804a 2 0 4294967295 MEAS_IV_PLL 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR3_SUPX_ANA_MPLLA_ATB3 2 0x804b 3 0 4294967295 MEAS_IV_BIAS 0 0 CTR_UPLL_TUNNING 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR3_SUPX_ANA_MPLLA_CTR1 2 0x804c 5 0 4294967295 CTR_ICP_INT 0 0 CTR_VREF_EN 0 0 CTR_VREF_VMARG 0 0 CTR_CP_PLL 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR3_SUPX_ANA_MPLLA_CTR2 2 0x804d 2 0 4294967295 CTR_REGS_PLL 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR3_SUPX_ANA_MPLLA_CTR3 2 0x804e 4 0 4294967295 CTR_REGS_CP_PLL 0 0 CTR_SPO_PLL 0 0 CTR_VINT_CAP 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR3_SUPX_ANA_MPLLA_CTR4 2 0x804f 7 0 4294967295 CTR_CP_8X 0 0 CTR_FIL_REG 0 0 CTR_CP_PROP_REF 0 0 CTR_DOUBLER_GAIN 0 0 CTR_TEST_CASC 0 0 CTR_RC_FITER 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR3_SUPX_ANA_MPLLA_CTR5 2 0x8050 8 0 4294967295 CTR_STANDBY_MODE 0 0 CTR_LEG_SR_CON 0 0 CTR_VREG_RING_OVERRIDE 0 0 CTR_SPO_SPEED_OVERRIDE 0 0 CTR_BYPASS_LOCK_SPO_CAL 0 0 CTR_LOCK_SPO_CAL 0 0 CTR_UPLL_RESERVED 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR3_SUPX_ANA_MPLLA_RESERVED1 2 0x8051 8 0 4294967295 CTR_REF_FBK_BYPASS 0 0 CTR_BYPASS_TX 0 0 CTR_VREG_CLK_BYPASS 0 0 CTR_VREG_CLK_PMIX_BYPASS 0 0 CTR_VREG_RIGHT_BYPASS 0 0 CTR_VREG_LEFT_BYPASS 0 0 CTR_LEFT_RIGHT_GAIN 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR3_SUPX_ANA_MPLLA_RESERVED2 2 0x8052 5 0 4294967295 CTR_DLL_MODE_90 0 0 CTR_DLL_RESERVED 0 0 CTR_DIV24_DSQ_ENZ 0 0 CTR_DIV4 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR3_SUPX_ANA_MPLLB_MISC1 2 0x8053 7 0 4294967295 OVRD_GEAR_RC_FILT 0 0 OVRD_TEST_RC_FILT 0 0 TEST_VREG_DIV 0 0 VBG_EN 0 0 COUNT_SEL_LOCK 0 0 PHASE_SEL_LOCK 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR3_SUPX_ANA_MPLLB_MISC2 2 0x8054 8 0 4294967295 OVRD_PR_BYPASS 0 0 PR_BYPASS 0 0 OVRD_GEARSHIFT 0 0 GEARSHIFT_REG 0 0 TEST_LOCK_GEAR 0 0 EN_CAL_SPO 0 0 TEST_BOOST 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR3_SUPX_ANA_MPLLB_OVRD 2 0x8055 9 0 4294967295 OVRD_ENABLE 0 0 ENABLE_REG 0 0 OVRD_CAL 0 0 CAL_REG 0 0 OVRD_FB_CLK_EN 0 0 FB_CLK_EN_REG 0 0 OVRD_RESET 0 0 RESET_REG 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR3_SUPX_ANA_MPLLB_ATB1 2 0x8056 3 0 4294967295 MEAS_IV_WRAP 0 0 ATB_SELECT 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR3_SUPX_ANA_MPLLB_ATB2 2 0x8057 2 0 4294967295 MEAS_IV_PLL 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR3_SUPX_ANA_MPLLB_ATB3 2 0x8058 3 0 4294967295 MEAS_IV_BIAS 0 0 CTR_UPLL_TUNNING 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR3_SUPX_ANA_MPLLB_CTR1 2 0x8059 5 0 4294967295 CTR_ICP_INT 0 0 CTR_VREF_EN 0 0 CTR_VREF_VMARG 0 0 CTR_CP_PLL 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR3_SUPX_ANA_MPLLB_CTR2 2 0x805a 2 0 4294967295 CTR_REGS_PLL 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR3_SUPX_ANA_MPLLB_CTR3 2 0x805b 4 0 4294967295 CTR_REGS_CP_PLL 0 0 CTR_SPO_PLL 0 0 CTR_VINT_CAP 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR3_SUPX_ANA_MPLLB_CTR4 2 0x805c 7 0 4294967295 CTR_CP_8X 0 0 CTR_FIL_REG 0 0 CTR_CP_PROP_REF 0 0 CTR_DOUBLER_GAIN 0 0 CTR_TEST_CASC 0 0 CTR_RC_FITER 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR3_SUPX_ANA_MPLLB_CTR5 2 0x805d 8 0 4294967295 CTR_STANDBY_MODE 0 0 CTR_LEG_SR_CON 0 0 CTR_VREG_RING_OVERRIDE 0 0 CTR_SPO_SPEED_OVERRIDE 0 0 CTR_BYPASS_LOCK_SPO_CAL 0 0 CTR_LOCK_SPO_CAL 0 0 CTR_UPLL_RESERVED 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR3_SUPX_ANA_MPLLB_RESERVED1 2 0x805e 8 0 4294967295 CTR_REF_FBK_BYPASS 0 0 CTR_BYPASS_TX 0 0 CTR_VREG_CLK_BYPASS 0 0 CTR_VREG_CLK_PMIX_BYPASS 0 0 CTR_VREG_RIGHT_BYPASS 0 0 CTR_VREG_LEFT_BYPASS 0 0 CTR_LEFT_RIGHT_GAIN 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR3_SUPX_ANA_MPLLB_RESERVED2 2 0x805f 5 0 4294967295 CTR_DLL_MODE_90 0 0 CTR_DLL_RESERVED 0 0 CTR_DIV24_DSQ_ENZ 0 0 CTR_DIV4 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD 2 0x8061 8 0 4294967295 OVRD_SEL 0 0 MPLL_FBDIGCLK_EN 1 1 MPLL_PCLK_EN 2 2 FAST_MPLL_PWRUP 3 3 FAST_MPLL_LOCK 4 4 DTB_SEL 5 9 DIV10_EN 10 10 RESERVED 11 15 ixDPCSSYS_CR3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT 2 0x8062 11 0 4294967295 FSM_STATE 0 3 MPLL_R_LANES 4 4 MPLL_L_LANES 5 5 MPLL_PCLK_EN 6 6 MPLL_OUTPUT_EN 7 7 MPLL_FBCLK_EN 8 8 MPLL_CAL 9 9 MPLL_RST 10 10 MPLL_ANA_EN 11 11 MPLL_LOCK 12 12 RESERVED_15_13 13 15 ixDPCSSYS_CR3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE 2 0x8063 3 0 4294967295 MAX_RANGE 0 4 DAC_IN 5 9 RESERVED_15_10 10 15 ixDPCSSYS_CR3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_LOCK 2 0x8064 3 0 4294967295 LOCK_TIME 0 7 STABLE_TIME 8 13 RESERVED_15_14 14 15 ixDPCSSYS_CR3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS 2 0x8065 2 0 4294967295 GEARSHIFT_TIME 0 7 PRESET_TIME 8 15 ixDPCSSYS_CR3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE 2 0x8066 3 0 4294967295 PWRDN_WAIT_TIME 0 5 PCLK_EN_TIME 6 11 RESERVED_15_12 12 15 ixDPCSSYS_CR3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2 2 0x8067 3 0 4294967295 PCLK_DIS_TIME 0 5 PWRDN_TIME 6 11 RESERVED_15_12 12 15 ixDPCSSYS_CR3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_CAL 2 0x8068 3 0 4294967295 MPLL_CAL 0 0 MPLL_CAL_OVRD_EN 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT 2 0x8069 2 0 4294967295 MPLL_ANA_DAC_OUT 0 4 RESERVED_15_5 5 15 ixDPCSSYS_CR3_SUPX_DIG_MPLLA_SSC_GEN_SPREAD_TYPE 2 0x806b 3 0 4294967295 SPREAD_TYPE 0 1 OVR_EN 2 2 RESERVED_15_3 3 15 ixDPCSSYS_CR3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD 2 0x806d 8 0 4294967295 OVRD_SEL 0 0 MPLL_FBDIGCLK_EN 1 1 MPLL_PCLK_EN 2 2 FAST_MPLL_PWRUP 3 3 FAST_MPLL_LOCK 4 4 DTB_SEL 5 9 DIV10_EN 10 10 RESERVED 11 15 ixDPCSSYS_CR3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT 2 0x806e 11 0 4294967295 FSM_STATE 0 3 MPLL_R_LANES 4 4 MPLL_L_LANES 5 5 MPLL_PCLK_EN 6 6 MPLL_OUTPUT_EN 7 7 MPLL_FBCLK_EN 8 8 MPLL_CAL 9 9 MPLL_RST 10 10 MPLL_ANA_EN 11 11 MPLL_LOCK 12 12 RESERVED_15_13 13 15 ixDPCSSYS_CR3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE 2 0x806f 3 0 4294967295 MAX_RANGE 0 4 DAC_IN 5 9 RESERVED_15_10 10 15 ixDPCSSYS_CR3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_LOCK 2 0x8070 3 0 4294967295 LOCK_TIME 0 7 STABLE_TIME 8 13 RESERVED_15_14 14 15 ixDPCSSYS_CR3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS 2 0x8071 2 0 4294967295 GEARSHIFT_TIME 0 7 PRESET_TIME 8 15 ixDPCSSYS_CR3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE 2 0x8072 3 0 4294967295 PWRDN_WAIT_TIME 0 5 PCLK_EN_TIME 6 11 RESERVED_15_12 12 15 ixDPCSSYS_CR3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2 2 0x8073 3 0 4294967295 PCLK_DIS_TIME 0 5 PWRDN_TIME 6 11 RESERVED_15_12 12 15 ixDPCSSYS_CR3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_CAL 2 0x8074 3 0 4294967295 MPLL_CAL 0 0 MPLL_CAL_OVRD_EN 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT 2 0x8075 2 0 4294967295 MPLL_ANA_DAC_OUT 0 4 RESERVED_15_5 5 15 ixDPCSSYS_CR3_SUPX_DIG_MPLLB_SSC_GEN_SPREAD_TYPE 2 0x8077 3 0 4294967295 SPREAD_TYPE 0 1 OVR_EN 2 2 RESERVED_15_3 3 15 ixDPCSSYS_CR3_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_0 2 0x8078 3 0 4294967295 BG_SUP_EN_TIME 0 8 FAST_BG_WAIT 9 9 RESERVED_15_10 10 15 ixDPCSSYS_CR3_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_1 2 0x8079 2 0 4294967295 BG_LANE_EN_TIME 0 8 RESERVED_15_9 9 15 ixDPCSSYS_CR3_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_2 2 0x807a 3 0 4294967295 BG_KICK_START_EN_TIME 0 7 BG_SUP_STATE_UPD_EN 8 8 RESERVED_15_9 9 15 ixDPCSSYS_CR3_SUPX_DIG_CLK_RST_REF_PWRUP_TIME_0 2 0x807b 3 0 4294967295 REF_VREG_FAST_START_TIME 0 4 FAST_REF_WAIT 5 5 RESERVED_15_6 6 15 ixDPCSSYS_CR3_SUPX_DIG_CLK_RST_REF_VPHUD 2 0x807c 3 0 4294967295 SUP_ANA_VPHUD_SELVPH_I 0 0 SUP_ANA_VPHUD_EN_I 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR3_SUPX_DIG_RTUNE_CONFIG 2 0x8081 5 0 4294967295 RX_CAL_EN 0 0 FAST_RTUNE 1 1 TX_CAL_EN 2 2 SUP_ANA_TERM_CTRL 3 5 RESERVED_15_6 6 15 ixDPCSSYS_CR3_SUPX_DIG_RTUNE_STAT 2 0x8082 3 0 4294967295 STAT 0 9 DTB_RTUNE 10 11 RESERVED_15_12 12 15 ixDPCSSYS_CR3_SUPX_DIG_RTUNE_RX_SET_VAL 2 0x8083 2 0 4294967295 RX_SET_VAL 0 5 RESERVED_15_6 6 15 ixDPCSSYS_CR3_SUPX_DIG_RTUNE_TXDN_SET_VAL 2 0x8084 2 0 4294967295 TXDN_SET_VAL 0 9 RESERVED_15_10 10 15 ixDPCSSYS_CR3_SUPX_DIG_RTUNE_TXUP_SET_VAL 2 0x8085 2 0 4294967295 TXUP_SET_VAL 0 9 RESERVED_15_10 10 15 ixDPCSSYS_CR3_SUPX_DIG_RTUNE_RX_STAT 2 0x8086 2 0 4294967295 RX_STAT 0 5 RESERVED_15_6 6 15 ixDPCSSYS_CR3_SUPX_DIG_RTUNE_TXDN_STAT 2 0x8087 2 0 4294967295 TXDN_STAT 0 9 RESERVED_15_10 10 15 ixDPCSSYS_CR3_SUPX_DIG_RTUNE_TXUP_STAT 2 0x8088 2 0 4294967295 TXUP_STAT 0 9 RESERVED_15_10 10 15 ixDPCSSYS_CR3_SUPX_DIG_RTUNE_CONFIG_CNT0 2 0x8089 4 0 4294967295 RT_RESULT_TIME 0 3 RT_EVAL_TIME 4 7 RT_RST_TIME 8 11 RT_ACK_TIME 12 15 ixDPCSSYS_CR3_SUPX_DIG_RTUNE_CONFIG_CNT1 2 0x808a 3 0 4294967295 RT_TXDN_SETTLE_TIME 0 3 RT_PWRUP_TIME 4 8 RESERVED_15_9 9 15 ixDPCSSYS_CR3_SUPX_DIG_RTUNE_TX_CAL_CODE 2 0x808b 2 0 4294967295 VALUE 0 3 RESERVED_15_4 4 15 ixDPCSSYS_CR3_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0 2 0x808c 16 0 4294967295 MPLLA_WORD_CLK_EN 0 0 MPLLA_HDMI_CLK_EN 1 1 MPLLA_DIV_CLK_EN 2 2 MPLLA_OUTPUT_EN 3 3 MPLLA_CLK_EN_OVRD_EN 4 4 MPLLA_OUTPUT_L_EN 5 5 MPLLA_OUTPUT_R_EN 6 6 MPLLA_ANA_EN 7 7 MPLLA_RST 8 8 MPLLA_CAL 9 9 MPLLA_DIV5_CLK_EN 10 10 MPLLA_DIV10_CLK_EN 11 11 MPLLA_FBCLK_EN 12 12 MPLLA_GEARSHIFT_EN 13 13 MPLLA_STANDBY 14 14 OVRD_SEL 15 15 ixDPCSSYS_CR3_SUPX_DIG_ANA_MPLLA_OVRD_OUT_1 2 0x808d 2 0 4294967295 MPLLA_ANA_INT 0 9 RESERVED_15_10 10 15 ixDPCSSYS_CR3_SUPX_DIG_ANA_MPLLA_OVRD_OUT_2 2 0x808e 3 0 4294967295 MPLLA_CP_PROP 0 6 MPLLA_CP_INT 7 13 RESERVED_15_14 14 15 ixDPCSSYS_CR3_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0 2 0x808f 16 0 4294967295 MPLLB_WORD_CLK_EN 0 0 MPLLB_HDMI_CLK_EN 1 1 MPLLB_DIV_CLK_EN 2 2 MPLLB_OUTPUT_EN 3 3 MPLLB_CLK_EN_OVRD_EN 4 4 MPLLB_OUTPUT_L_EN 5 5 MPLLB_OUTPUT_R_EN 6 6 MPLLB_ANA_EN 7 7 MPLLB_RST 8 8 MPLLB_CAL 9 9 MPLLB_DIV5_CLK_EN 10 10 MPLLB_DIV10_CLK_EN 11 11 MPLLB_FBCLK_EN 12 12 MPLLB_GEARSHIFT_EN 13 13 MPLLB_STANDBY 14 14 OVRD_SEL 15 15 ixDPCSSYS_CR3_SUPX_DIG_ANA_MPLLB_OVRD_OUT_1 2 0x8090 2 0 4294967295 MPLLB_ANA_INT 0 9 RESERVED_15_10 10 15 ixDPCSSYS_CR3_SUPX_DIG_ANA_MPLLB_OVRD_OUT_2 2 0x8091 3 0 4294967295 MPLLB_CP_PROP 0 6 MPLLB_CP_INT 7 13 RESERVED_15_14 14 15 ixDPCSSYS_CR3_SUPX_DIG_ANA_RTUNE_OVRD_OUT 2 0x8092 6 0 4294967295 RTUNE_COMP_RST 0 0 RTUNE_MODE 1 2 RTUNE_EN 3 3 RTUNE_VALUE 4 13 RTUNE_OVRD_EN 14 14 RESERVED_15_15 15 15 ixDPCSSYS_CR3_SUPX_DIG_ANA_STAT 2 0x8093 3 0 4294967295 RT_ANA_COMP_RESULT 0 0 REF_ANA_CLKDET_RESULT 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR3_SUPX_DIG_ANA_BG_OVRD_OUT 2 0x8094 11 0 4294967295 BG_EN 0 0 BG_FAST_START 1 1 BG_KICK_START 2 2 BG_OVRD_EN 3 3 ANA_ASYNC_RST 4 4 ANA_ASYNC_RST_OVRD_EN 5 5 REF_VREG_FAST_START 6 6 REF_VREG_FAST_START_OVRD_EN 7 7 REF_VREG_REF_SEL 8 9 REF_VREG_REF_SEL_OVRD_EN 10 10 RESERVED_15_11 11 15 ixDPCSSYS_CR3_SUPX_DIG_ANA_MPLLA_PMIX_OVRD_OUT 2 0x8095 5 0 4294967295 MPLLA_PMIX_SEL 0 5 MPLLA_PMIX_EN 6 6 MPLLA_PMIX_SEL_OVRD_EN 7 7 MPLLA_PMIX_EN_OVRD_EN 8 8 RESERVED_15_9 9 15 ixDPCSSYS_CR3_SUPX_DIG_ANA_MPLLB_PMIX_OVRD_OUT 2 0x8096 5 0 4294967295 MPLLB_PMIX_SEL 0 5 MPLLB_PMIX_EN 6 6 MPLLB_PMIX_SEL_OVRD_EN 7 7 MPLLB_PMIX_EN_OVRD_EN 8 8 RESERVED_15_9 9 15 ixDPCSSYS_CR3_LANEX_DIG_ASIC_LANE_OVRD_IN 2 0x9000 5 0 4294967295 LANE_TX2RX_SER_LB 0 0 LANE_RX2TX_PAR_LB 1 1 EN 2 2 RX_ACJTAG_EN 3 3 RESERVED_15_4 4 15 ixDPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_0 2 0x9001 12 0 4294967295 REQ 0 0 REQ_OVRD_EN 1 1 PSTATE 2 3 PSTATE_OVRD_EN 4 4 RATE 5 7 RATE_OVRD_EN 8 8 WIDTH 9 10 WIDTH_OVRD_EN 11 11 MPLLB_SEL 12 12 MPLLB_SEL_OVRD_EN 13 13 DATA_EN 14 14 DATA_EN_OVRD_EN 15 15 ixDPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_1 2 0x9002 11 0 4294967295 NYQUIST_DATA 0 0 DISABLE 1 1 BEACON_EN 2 2 EN 3 3 TX_MAIN_CURSOR 4 9 MAIN_OVRD_EN 10 10 ASYNC_DRV_EN 11 11 ASYNC_DRV_OVRD_EN 12 12 TX_VREGDRV_BYP_OVRD 13 13 TX_VREGDRV_BYP_OVRD_EN 14 14 RESERVED_15_15 15 15 ixDPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_2 2 0x9003 6 0 4294967295 TX_PRE_CURSOR 0 5 PRE_OVRD_EN 6 6 TX_POST_CURSOR 7 12 POST_OVRD_EN 13 13 HDMIMODE_EN 14 14 HDMIMODE_ENABLE_OVRD_EN 15 15 ixDPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_3 2 0x9004 15 0 4294967295 CLK_RDY 0 0 CLK_RDY_OVRD_EN 1 1 DETECT_RX_REQ 2 2 DETECT_RX_REQ_OVRD_EN 3 3 INVERT 4 4 INVERT_OVRD_EN 5 5 LPD 6 6 LPD_OVRD_EN 7 7 TX_DC_COUP_EN 8 8 TX_DC_COUP_EN_OVRD_EN 9 9 PMA_EXTENDED_FIFO_EN 10 10 PMA_EXTENDED_FIFO_EN_OVRD_EN 11 11 TX_MPHY_MODE_EN 12 12 TX_MPHY_MODE_EN_OVRD_EN 13 13 RESERVED_15_14 14 15 ixDPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_4 2 0x9005 3 0 4294967295 RESET 0 0 RESET_OVRD_EN 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_OUT 2 0x9006 5 0 4294967295 TX_ACK 0 0 EN_TX_ACK 1 1 DETRX_RESULT 2 2 EN_DETRX_RESULT 3 3 RESERVED_15_4 4 15 ixDPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_0 2 0x9007 11 0 4294967295 REQ 0 0 REQ_OVRD_EN 1 1 DATA_EN 2 2 DATA_EN_OVRD_EN 3 3 PSTATE 4 5 PSTATE_OVRD_EN 6 6 RATE 7 8 RATE_OVRD_EN 9 9 WIDTH 10 11 WIDTH_OVRD_EN 12 12 RESERVED_15_13 13 15 ixDPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_1 2 0x9008 5 0 4294967295 RX_REF_LD_VAL_5_0 0 5 RX_CDR_VCO_LOWFREQ 6 6 EN 7 7 RX_REF_LD_VAL_6 8 8 RESERVED_15_9 9 15 ixDPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_2 2 0x9009 3 0 4294967295 RX_VCO_LD_VAL 0 12 EN 13 13 RESERVED_15_14 14 15 ixDPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_3 2 0x900a 11 0 4294967295 CDR_TRACK_EN 0 0 CDR_TRACK_EN_OVRD_EN 1 1 CDR_SSC_EN 2 2 CDR_SSC_EN_OVRD_EN 3 3 ALIGN_EN 4 4 ALIGN_EN_OVRD_EN 5 5 CLK_SHIFT 6 6 CLK_SHIFT_OVRD_EN 7 7 DISABLE 8 8 DISABLE_OVRD_EN 9 9 RESERVED_15_10 10 15 ixDPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_4 2 0x900b 11 0 4294967295 LPD 0 0 LPD_OVRD_EN 1 1 INVERT 2 2 INVERT_OVRD_EN 3 3 ADAPT_AFE_EN 4 4 ADAPT_DFE_EN 5 5 ADPT_OVRD_EN 6 6 TERM_EN 7 7 TERM_ACDC 8 8 TERM_OVRD_EN 9 9 RESERVED_15_10 10 15 ixDPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_5 2 0x900c 3 0 4294967295 RESET 0 0 RESET_OVRD_EN 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0 2 0x900d 4 0 4294967295 EQ_ATT_LVL 0 2 EQ_AFE_GAIN 3 6 RESERVED 7 10 EQ_CTLE_BOOST 11 15 ixDPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1 2 0x900e 3 0 4294967295 EQ_DFE_TAP2 0 6 EQ_DFE_TAP1 7 14 EQ_OVRD_EN 15 15 ixDPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_OUT_0 2 0x900f 9 0 4294967295 ACK 0 0 ACK_OVRD_EN 1 1 ADAPT_STS 2 3 ADAPT_STS_OVRD_EN 4 4 RX_ASYNC_DATA 5 5 RX_ASYNC_DATA_OVRD_EN 6 6 RX_SQ_WEAKKEEP_OUT 7 7 RX_SQ_WEAKKEEP_OUT_OVRD_EN 8 8 RESERVED_15_9 9 15 ixDPCSSYS_CR3_LANEX_DIG_ASIC_LANE_ASIC_IN 2 0x9010 3 0 4294967295 LANE_TX2RX_SER_LB 0 0 LANE_RX2TX_PAR_LB 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR3_LANEX_DIG_ASIC_TX_ASIC_IN_0 2 0x9011 12 0 4294967295 CLK_RDY 0 0 RESET 1 1 INVERT 2 2 DATA_EN 3 3 REQ 4 4 LPD 5 5 PSTATE 6 7 RATE 8 10 WIDTH 11 12 MPLLB_SEL 13 13 DETECT_RX_REQ 14 14 DISABLE 15 15 ixDPCSSYS_CR3_LANEX_DIG_ASIC_TX_ASIC_IN_1 2 0x9012 7 0 4294967295 BEACON_EN 0 0 TX_MAIN_CURSOR 1 6 TX_ASYNC_EN 7 7 TX_ASYNC_DATA 8 8 TX_ASYNC_DRV_EN 9 9 TX_VREGDRV_BYP 10 10 RESERVED_15_11 11 15 ixDPCSSYS_CR3_LANEX_DIG_ASIC_TX_ASIC_IN_2 2 0x9013 3 0 4294967295 TX_PRE_CURSOR 0 5 TX_POST_CURSOR 6 11 RESERVED_15_12 12 15 ixDPCSSYS_CR3_LANEX_DIG_ASIC_TX_ASIC_OUT 2 0x9014 3 0 4294967295 TX_ACK 0 0 DETRX_RESULT 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR3_LANEX_DIG_ASIC_RX_ASIC_IN_0 2 0x9015 13 0 4294967295 RESET 0 0 INVERT 1 1 DATA_EN 2 2 REQ 3 3 LPD 4 4 PSTATE 5 6 RATE 7 8 WIDTH 9 10 RESERVED 11 11 ADAPT_AFE_EN 12 12 ADAPT_DFE_EN 13 13 CDR_TRACK_EN 14 14 RESERVED_15_15 15 15 ixDPCSSYS_CR3_LANEX_DIG_ASIC_RX_ASIC_IN_1 2 0x9016 7 0 4294967295 CDR_SSC_EN 0 0 ALIGN_EN 1 1 CLK_SHIFT 2 2 DISABLE 3 3 RX_TERM_EN 4 4 RX_TERM_ACDC 5 5 RESERVED_15_6 6 15 ixDPCSSYS_CR3_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0 2 0x9017 4 0 4294967295 EQ_ATT_LVL 0 2 EQ_AFE_GAIN 3 6 RESERVED 7 10 EQ_CTLE_BOOST 11 15 ixDPCSSYS_CR3_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_1 2 0x9018 3 0 4294967295 EQ_DFE_TAP2 0 6 EQ_DFE_TAP1 7 14 RESERVED_15_15 15 15 ixDPCSSYS_CR3_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0 2 0x9019 3 0 4294967295 RX_CDR_VCO_LOWFREQ 0 0 RX_REF_LD_VAL 1 7 RESERVED_15_8 8 15 ixDPCSSYS_CR3_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1 2 0x901a 2 0 4294967295 RX_VCO_LD_VAL 0 12 RESERVED_15_13 13 15 ixDPCSSYS_CR3_LANEX_DIG_ASIC_RX_ASIC_OUT_0 2 0x901b 4 0 4294967295 ACK 0 0 VALID 1 1 ADAPT_STS 2 3 RESERVED_15_4 4 15 ixDPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_6 2 0x901c 10 0 4294967295 RX_PWM_CLK_SEL 0 1 RX_PWM_CLK_SEL_OVRD_EN 2 2 RX_TERM_LCC_ON 3 3 RX_TERM_LS_ON 4 4 RX_TERM_LS_LCC_ON_OVRD_EN 5 5 RX_TERM_CTL 6 7 RX_TERM_CTL_OVRD_EN 8 8 RX_PWM_EN 9 9 RX_PWM_EN_OVRD_EN 10 10 RESERVED_15_11 11 15 ixDPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_5 2 0x901d 15 0 4294967295 RPTR_EN_MASTER_LANE 0 0 RPTR_EN_MASTER_LANE_OVRD_EN 1 1 DIG_CLK_EN_OTHER_LANE 2 2 DIG_CLK_EN_OTHER_LANE_OVRD_EN 3 3 DIG_CLK_STATE_MASTER_LANE 4 4 DIG_CLK_STATE_MASTER_LANE_OVRD_EN 5 5 SHIFT_MASTER_LANE 6 6 SHIFT_MASTER_LANE_ORVD_EN 7 7 SHIFT_ACK_OTHER_LANE 8 8 SHIFT_ACK_OTHER_LANE_OVRD_EN 9 9 LANE_MASTER 10 10 LANE_MASTER_OVRD_IN_EN 11 11 TX_DWORD_CLK_SYNC_OVRD 12 12 TX_DWORD_CLK_SYNC_OVRD_EN 13 13 RESERVED_15_14 14 15 ixDPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_OUT_1 2 0x901e 11 0 4294967295 RPTR_EN_OUT 0 0 RPTR_EN_OUT_OVRD_EN 1 1 DIG_CLK_EN_OUT 2 2 DIG_CLK_EN_OUT_OVRD_EN 3 3 DIG_CLK_STATE_OUT 4 4 DIG_CLK_STATE_OUT_OVRD_EN 5 5 SHIFT_OUT 6 6 SHIFT_OUT_OVRD_EN 7 7 SHIFT_ACK_OUT 8 8 SHIFT_ACK_OUT_OVRD_EN 9 9 RESERVED_15_10 10 15 ixDPCSSYS_CR3_LANEX_DIG_ASIC_OCLA 2 0x901f 3 0 4294967295 RX_DWORD_OCLA_CLK_EN 0 0 RX_DWORD_OCLA_DATA_EN 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0 2 0x9020 11 0 4294967295 TX_P0_ANA_REFGEN_EN 0 0 TX_P0_ANA_VCM_HOLD 1 1 TX_P0_ANA_CLK_EN 2 2 TX_P0_ANA_WORD_CLK_EN 3 3 TX_P0_ANA_RESET 4 4 TX_P0_ANA_SERIAL_EN 5 5 TX_P0_DIG_CLK_EN 6 6 TX_P0_DATA_EN 7 7 TX_P0_ALLOW_RXDET 8 8 TX_P0_ANA_DCC_COMP_CAL_EN 9 9 RESERVED_15_10 10 15 ixDPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S 2 0x9021 11 0 4294967295 TX_P0S_ANA_REFGEN_EN 0 0 TX_P0S_ANA_VCM_HOLD 1 1 TX_P0S_ANA_CLK_EN 2 2 TX_P0S_ANA_WORD_CLK_EN 3 3 TX_P0S_ANA_RESET 4 4 TX_P0S_ANA_SERIAL_EN 5 5 TX_P0S_DIG_CLK_EN 6 6 TX_P0S_DATA_EN 7 7 TX_P0S_ALLOW_RXDET 8 8 TX_P0S_ANA_DCC_COMP_CAL_EN 9 9 RESERVED_15_10 10 15 ixDPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1 2 0x9022 11 0 4294967295 TX_P1_ANA_REFGEN_EN 0 0 TX_P1_ANA_VCM_HOLD 1 1 TX_P1_ANA_CLK_EN 2 2 TX_P1_ANA_WORD_CLK_EN 3 3 TX_P1_ANA_RESET 4 4 TX_P1_ANA_SERIAL_EN 5 5 TX_P1_DIG_CLK_EN 6 6 TX_P1_DATA_EN 7 7 TX_P1_ALLOW_RXDET 8 8 TX_P1_ANA_DCC_COMP_CAL_EN 9 9 RESERVED_15_10 10 15 ixDPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2 2 0x9023 12 0 4294967295 TX_P2_ANA_REFGEN_EN 0 0 TX_P2_ANA_VCM_HOLD 1 1 TX_P2_ANA_CLK_EN 2 2 TX_P2_ANA_WORD_CLK_EN 3 3 TX_P2_ANA_RESET 4 4 TX_P2_ANA_SERIAL_EN 5 5 TX_P2_DIG_CLK_EN 6 6 TX_P2_DATA_EN 7 7 TX_P2_ALLOW_RXDET 8 8 TX_P2_ALLOW_VBOOST 9 9 TX_P2_ANA_DCC_COMP_CAL_EN 10 10 RESERVED_15_11 11 15 ixDPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_0 2 0x9024 2 0 4294967295 TX_REFGEN_EN_TIME 0 7 TX_CLK_EN 8 15 ixDPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_1 2 0x9025 2 0 4294967295 TX_VCM_HOLD_TIME_14_0 0 14 SKIP_TX_VCM_HOLD_WAIT 15 15 ixDPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_2 2 0x9026 2 0 4294967295 TX_VBOOST_DIS_TIME_12_0 0 12 DTB_SEL 13 15 ixDPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_3 2 0x9027 3 0 4294967295 TX_VCM_HOLD_TIME_17_15 0 2 TX_VBOOST_DIS_TIME_13 3 3 RESERVED_15_4 4 15 ixDPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_4 2 0x9028 2 0 4294967295 TX_VCM_HOLD_GS_TIME 0 14 SKIP_TX_VCM_HOLD_GS_PULSE 15 15 ixDPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_5 2 0x9029 5 0 4294967295 TX_RXDET_TIME 0 9 FAST_TX_RXDET 10 10 TX_RESET_TIME 11 12 TX_SERIAL_EN_TIME 13 14 RESERVED_15_15 15 15 ixDPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_DCC_CR_BANK_ADDR 2 0x902a 1 0 4294967295 ADDR 0 15 ixDPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_DCC_CR_BANK_DATA 2 0x902b 1 0 4294967295 DATA 0 15 ixDPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_DCC_DAC_CTRL 2 0x902c 2 0 4294967295 CTRL 0 7 RESERVED_15_8 8 15 ixDPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_DCC_DAC_RANGE 2 0x902d 2 0 4294967295 CTRL 0 1 RESERVED_15_2 2 15 ixDPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_DCC_DAC_SEL 2 0x902e 6 0 4294967295 SEL 0 2 REQ 3 3 CTRL_UPD 4 4 RANGE_UPD 5 5 BIN_HOT 6 6 RESERVED_15_7 7 15 ixDPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_DCC_DAC_ACK 2 0x902f 2 0 4294967295 ACK 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_DCC_DAC_ADDR 2 0x9030 1 0 4294967295 ADDR 0 15 ixDPCSSYS_CR3_LANEX_DIG_TX_CLK_ALIGN_TX_CTL_0 2 0x9031 4 0 4294967295 TX_NUM_2UI_SHIFTS_16B_MODE 0 3 TX_NUM_2UI_SHIFTS_20B_MODE 4 7 TX_FIFO_BYPASS 8 8 RESERVED_15_9 9 15 ixDPCSSYS_CR3_LANEX_DIG_TX_LBERT_CTL 2 0x9032 4 0 4294967295 MODE 0 3 TRIGGER_ERR 4 4 PAT0 5 14 RESERVED_15_15 15 15 ixDPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0 2 0x9040 12 0 4294967295 RX_P0_ANA_AFE_EN 0 0 RX_P0_ANA_CLK_VREG_EN 1 1 RESERVED_1 2 2 RX_P0_ANA_CLK_EN 3 3 RESERVED_0 4 4 RX_P0_ANA_DESER_EN 5 5 RX_P0_ANA_CDR_EN 6 6 RX_P0_VCO_FREQ_RST 7 7 RX_P0_VCO_CAL_RST 8 8 RX_P0_VCO_CONTCAL_EN 9 9 RX_P0_DIG_CLK_EN 10 10 RESERVED_15_11 11 15 ixDPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S 2 0x9041 12 0 4294967295 RX_P0S_ANA_AFE_EN 0 0 RX_P0S_ANA_CLK_VREG_EN 1 1 RESERVED_2 2 2 RX_P0S_ANA_CLK_EN 3 3 RESERVED_4 4 4 RX_P0S_ANA_DESER_EN 5 5 RX_P0S_ANA_CDR_EN 6 6 RX_P0S_VCO_FREQ_RST 7 7 RX_P0S_VCO_CAL_RST 8 8 RX_P0S_VCO_CONTCAL_EN 9 9 RX_P0S_DIG_CLK_EN 10 10 RESERVED_15_11 11 15 ixDPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1 2 0x9042 12 0 4294967295 RX_P1_ANA_AFE_EN 0 0 RX_P1_ANA_CLK_VREG_EN 1 1 RESERVED_2 2 2 RX_P1_ANA_CLK_EN 3 3 RESERVED_4 4 4 RX_P1_ANA_DESER_EN 5 5 RX_P1_ANA_CDR_EN 6 6 RX_P1_VCO_FREQ_RST 7 7 RX_P1_VCO_CAL_RST 8 8 RX_P1_VCO_CONTCAL_EN 9 9 RX_P1_DIG_CLK_EN 10 10 RESERVED_15_11 11 15 ixDPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2 2 0x9043 12 0 4294967295 RX_P2_ANA_AFE_EN 0 0 RX_P2_ANA_CLK_VREG_EN 1 1 RESERVED_2 2 2 RX_P2_ANA_CLK_EN 3 3 RESERVED_4 4 4 RX_P2_ANA_DESER_EN 5 5 RX_P2_ANA_CDR_EN 6 6 RX_P2_VCO_FREQ_RST 7 7 RX_P2_VCO_CAL_RST 8 8 RX_P2_VCO_CONTCAL_EN 9 9 RX_P2_DIG_CLK_EN 10 10 RESERVED_15_11 11 15 ixDPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1 2 0x9045 5 0 4294967295 RX_AFE_EN_TIME 0 5 FAST_RX_AFE_EN 6 6 RX_VREG_EN_TIME 7 12 FAST_RX_VREG_EN 13 13 RESERVED_15_14 14 15 ixDPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_2 2 0x9046 4 0 4294967295 RX_CLK_EN_TIME 0 5 FAST_RX_CLK_EN 6 6 RX_FAST_START_TIME 7 10 RESERVED_15_11 11 15 ixDPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_3 2 0x9047 5 0 4294967295 RX_RATE_TIME 0 1 RSVD_3_7_2 2 7 RX_CDR_EN_TIME 8 11 RX_DESER_EN_TIME 12 13 RX_DESER_DIS_TIME 14 15 ixDPCSSYS_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0 2 0x9048 8 0 4294967295 INT_GAIN_CAL_FIXED_CNT 0 4 INT_GAIN_CAL_FIXED_CNT_EN 5 5 INT_GAIN_CAL_CNT_SHIFT 6 8 INT_GAIN_CAL_BOUNCE_CNT 9 11 DISABLE_BIN_HOLD 12 12 DISABLE_INT_GAIN_HOLD 13 13 DISABLE_COARSE_CALDONE 14 14 RESERVED_15_15 15 15 ixDPCSSYS_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1 2 0x9049 7 0 4294967295 RX_VCO_OVRD_SEL 0 0 RX_VCO_FREQ_RST 1 1 RX_VCO_CAL_RST 2 2 RX_VCO_CONTCAL_EN 3 3 DISABLE_INT_CAL_MODE 4 4 DPLL_CAL_UG 5 8 DTB_SEL 9 15 ixDPCSSYS_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2 2 0x904a 4 0 4294967295 FREQ_TUNE_START_VAL 0 9 FREQ_TUNE_CAL_STEPS 10 13 SKIP_RX_VCO_FREQ_TUNE_CAL 14 14 SKIP_RX_VCO_CAL 15 15 ixDPCSSYS_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0 2 0x904b 4 0 4294967295 RX_VCO_STARTUP_TIME 0 6 RX_VCO_UPDATE_TIME 7 10 RX_VCO_CNTR_PWRUP_TIME 11 14 FAST_RX_VCO_WAIT 15 15 ixDPCSSYS_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1 2 0x904c 2 0 4294967295 RX_VCO_CNTR_SETTLE_TIME 0 2 RESERVED_15_3 3 15 ixDPCSSYS_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0 2 0x904d 6 0 4294967295 RX_ANA_CDR_FREQ_TUNE 0 9 RX_ANA_VCO_CNTR_PD 10 10 RX_ANA_VCO_CNTR_EN 11 11 RX_ANA_CDR_STARTUP 12 12 RX_ANA_CDR_VCO_EN 13 13 RESERVED_15_14 14 15 ixDPCSSYS_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1 2 0x904e 7 0 4294967295 RX_VCO_FSM_STATE 0 3 RX_VCO_FREQ_RST 4 4 RX_VCO_CAL_RST 5 5 RX_VCO_CONTCAL_EN 6 6 RX_VCO_CAL_DONE 7 7 DPLL_FREQ_RST 8 8 RESERVED_15_9 9 15 ixDPCSSYS_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_2 2 0x904f 4 0 4294967295 VCO_CNTR_FINAL 0 12 VCOCLK_TOO_FAST 13 13 RX_VCO_CORRECT 14 14 RX_VCO_UP 15 15 ixDPCSSYS_CR3_LANEX_DIG_RX_RX_ALIGN_XAUI_COMM_MASK 2 0x9050 2 0 4294967295 XAUI_COMM_MASK 0 9 RESERVED_15_10 10 15 ixDPCSSYS_CR3_LANEX_DIG_RX_LBERT_CTL 2 0x9051 3 0 4294967295 MODE 0 3 SYNC 4 4 RESERVED_15_5 5 15 ixDPCSSYS_CR3_LANEX_DIG_RX_LBERT_ERR 2 0x9052 2 0 4294967295 COUNT 0 14 OV14 15 15 ixDPCSSYS_CR3_LANEX_DIG_RX_CDR_CDR_CTL_0 2 0x9053 7 0 4294967295 PHDET_EN 0 1 PHDET_EDGE 2 3 PHDET_POL 4 4 PHDET_EN_PR_MODE 5 5 ALWAYS_REALIGN 6 6 DTB_SEL 7 10 RESERVED_15_11 11 15 ixDPCSSYS_CR3_LANEX_DIG_RX_CDR_CDR_CTL_1 2 0x9054 2 0 4294967295 SSC_OFF_CNT0 0 9 SSC_OFF_CNT1 10 15 ixDPCSSYS_CR3_LANEX_DIG_RX_CDR_CDR_CTL_2 2 0x9055 2 0 4294967295 SSC_ON_CNT0 0 8 SSC_ON_CNT1 9 15 ixDPCSSYS_CR3_LANEX_DIG_RX_CDR_CDR_CTL_3 2 0x9056 6 0 4294967295 SSC_OFF_PHUG0 0 2 SSC_OFF_PHUG1 3 5 SSC_OFF_FRUG0 6 8 OVRD_DPLL_GAIN 9 9 PHUG_OVRD_VALUE 10 12 FRUG_OVRD_VALUE 13 15 ixDPCSSYS_CR3_LANEX_DIG_RX_CDR_CDR_CTL_4 2 0x9057 6 0 4294967295 SSC_OFF_FRUG1 0 2 SSC_ON_FRUG0 3 5 SSC_ON_FRUG1 6 8 SSC_ON_PHUG0 9 11 SSC_ON_PHUG1 12 14 RESERVED_15_15 15 15 ixDPCSSYS_CR3_LANEX_DIG_RX_CDR_STAT 2 0x9058 3 0 4294967295 PHUG_VALUE 0 2 FRUG_VALUE 3 5 RESERVED_15_6 6 15 ixDPCSSYS_CR3_LANEX_DIG_RX_DPLL_FREQ 2 0x9059 2 0 4294967295 VAL 0 13 RESERVED_15_14 14 15 ixDPCSSYS_CR3_LANEX_DIG_RX_DPLL_FREQ_BOUND_0 2 0x905a 3 0 4294967295 FREQ_BOUND_EN 0 0 UPPER_FREQ_BOUND 1 10 RESERVED_15_11 11 15 ixDPCSSYS_CR3_LANEX_DIG_RX_DPLL_FREQ_BOUND_1 2 0x905b 2 0 4294967295 LOWER_FREQ_BOUND 0 9 RESERVED_15_10 10 15 ixDPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_0 2 0x9060 4 0 4294967295 N_TOP_ASM1 0 9 N_TGG_ASM1 10 13 START_ASM1 14 14 ADPT_CLK_DIV4_EN 15 15 ixDPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1 2 0x9061 5 0 4294967295 N_WAIT_ASM1 0 6 FAST_AFE_DFE_SETTLE 7 7 CTLE_POLE_OVRD_VAL 8 10 CTLE_POLE_OVRD_EN 11 11 RESERVED_15_12 12 15 ixDPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_2 2 0x9062 3 0 4294967295 TGG_PTTRN_0 0 4 TGG_PTTRN_1 5 9 RESERVED_15_10 10 15 ixDPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3 2 0x9063 8 0 4294967295 CTLE_EN 0 4 VGA_EN 5 5 ATT_EN 6 6 DFE_EN 7 11 EYEHE_EN 12 12 EYEHO_EN 13 13 TGG_EN 14 14 ESL_TWICE_DSL 15 15 ixDPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_4 2 0x9064 4 0 4294967295 CTLE_TH 0 3 VGA_TH 4 7 DFE1_TH 8 11 DFE2_TH 12 15 ixDPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_5 2 0x9065 4 0 4294967295 DFE3_TH 0 3 DFE4_TH 4 7 DFE5_TH 8 11 TH_OFFSET 12 15 ixDPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6 2 0x9066 6 0 4294967295 CTLE_MU 0 2 VGA_MU 3 5 ATT_MU 6 8 VGA_SAT_CNT 9 11 VGA_SAT_CNT_STICKY 12 12 ATT_LOW_TH 13 15 ixDPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_7 2 0x9067 4 0 4294967295 VGA_MIN_SAT 0 4 VGA_LEV_HIGH 5 9 VGA_LEV_LOW 10 14 RESERVED_15_15 15 15 ixDPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8 2 0x9068 6 0 4294967295 DFE1_MU 0 2 DFE2_MU 3 5 DFE3_MU 6 8 DFE4_MU 9 11 DFE5_MU 12 14 RESERVED_15_15 15 15 ixDPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_9 2 0x9069 2 0 4294967295 ERR_SLE_ADPT_INIT 0 7 ERR_SLO_ADPT_INIT 8 15 ixDPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG 2 0x906a 6 0 4294967295 RST_ADPT_ATT 0 0 RST_ADPT_VGA 1 1 RST_ADPT_CTLE_BOOST 2 2 RST_ADPT_CTLE_POLE 3 3 RST_ADPT_TAP1 4 4 RESERVED_15_5 5 15 ixDPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ATT_STATUS 2 0x906b 3 0 4294967295 ATT_ADPT_CODE 0 7 ASM1_DON 8 8 RESERVED_15_9 9 15 ixDPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_VGA_STATUS 2 0x906c 3 0 4294967295 VGA_ADPT_CODE 0 9 ASM1_DONE 10 10 RESERVED_15_11 11 15 ixDPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_CTLE_STATUS 2 0x906d 4 0 4294967295 CTLE_BOOST_ADPT_CODE 0 9 CTLE_POLE_ADPT_CODE 10 12 ASM1_DONE 13 13 RESERVED_15_14 14 15 ixDPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_DFE_TAP1_STATUS 2 0x906e 3 0 4294967295 DFE_TAP1_ADPT_CODE 0 12 ASM1_DONE 13 13 RESERVED_15_14 14 15 ixDPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_DFE_TAP2_STATUS 2 0x906f 3 0 4294967295 DFE_TAP2_ADPT_CODE 0 11 ASM1_DONE 12 12 RESERVED_15_13 13 15 ixDPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_DFE_TAP3_STATUS 2 0x9070 3 0 4294967295 DFE_TAP3_ADPT_CODE 0 11 ASM1_DONE 12 12 RESERVED_15_13 13 15 ixDPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_DFE_TAP4_STATUS 2 0x9071 3 0 4294967295 DFE_TAP4_ADPT_CODE 0 11 ASM1_DONE 12 12 RESERVED_15_13 13 15 ixDPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_DFE_TAP5_STATUS 2 0x9072 3 0 4294967295 DFE_TAP5_ADPT_CODE 0 11 ASM1_DONE 12 12 RESERVED_15_13 13 15 ixDPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_DFE_DATA_EVEN_VDAC_OFST 2 0x9073 2 0 4294967295 DFE_DATA_EVEN_VDAC_OFST 0 7 RESERVED_15_8 8 15 ixDPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_DFE_DATA_ODD_VDAC_OFST 2 0x9074 2 0 4294967295 DFE_DATA_ODD_VDAC_OFST 0 7 RESERVED_15_8 8 15 ixDPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN 2 0x9075 2 0 4294967295 RX_ANA_SLICER_CTRL_E 0 3 RESERVED_15_4 4 15 ixDPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD 2 0x9076 2 0 4294967295 RX_ANA_SLICER_CTRL_O 0 3 RESERVED_15_4 4 15 ixDPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST 2 0x9077 2 0 4294967295 DFE_ERROR_EVEN_VDAC_OFST 0 7 RESERVED_15_8 8 15 ixDPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST 2 0x9078 2 0 4294967295 DFE_ERROR_ODD_VDAC_OFST 0 7 RESERVED_15_8 8 15 ixDPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL 2 0x9079 2 0 4294967295 E_SLO_LVL 0 7 E_SLE_LVL 8 15 ixDPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_RESET 2 0x907a 2 0 4294967295 RESET_ASM1 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1 2 0x907b 4 0 4294967295 DFE_T1_IDAC 0 4 DFE_T2_IDAC 5 9 DCC_START_IDAC 10 14 RESERVED_15_15 15 15 ixDPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2 2 0x907c 3 0 4294967295 DFE_DAT_EVEN_VDAC 0 4 DFE_DAT_ODD_VDAC 5 9 RESERVED_15_10 10 15 ixDPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3 2 0x907d 3 0 4294967295 DFE_ERR_EVEN_VDAC 0 4 DFE_ERR_ODD_VDAC 5 9 RESERVED_15_10 10 15 ixDPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_CR_BANK_ADDR 2 0x907e 1 0 4294967295 ADDR 0 15 ixDPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_CR_BANK_DATA 2 0x907f 1 0 4294967295 DATA 0 15 ixDPCSSYS_CR3_LANEX_DIG_RX_STAT_LD_VAL_1 2 0x9080 2 0 4294967295 SC1_LD_VAL 0 14 SC1_START 15 15 ixDPCSSYS_CR3_LANEX_DIG_RX_STAT_DATA_MSK 2 0x9081 1 0 4294967295 DATA_MSK_15_0 0 15 ixDPCSSYS_CR3_LANEX_DIG_RX_STAT_MATCH_CTL0 2 0x9082 4 0 4294967295 PTTRN_MSK_CR1A_4_0 0 4 PTTRN_CR1A_4_0 5 9 DATA_MSK_19_16 10 13 SCOPE_DLY 14 15 ixDPCSSYS_CR3_LANEX_DIG_RX_STAT_MATCH_CTL1 2 0x9083 5 0 4294967295 PTTRN_CR1B_EN 0 0 PTTRN_MSK_CR1B_4_0 1 5 PTTRN_CR1B_4_0 6 10 PTTRN_CR1A_ADPT_EN 11 11 RESERVED_15_12 12 15 ixDPCSSYS_CR3_LANEX_DIG_RX_STAT_STAT_CTL0 2 0x9084 10 0 4294967295 RESERVED_0 0 0 CORR_SHFT_SEL_VGA 1 1 CORR_SHFT_SEL 2 2 CORR_SRC_SEL 3 4 CORR_MODE_EN 5 5 STAT_SHFT_SEL 6 9 STAT_SRC_SEL 10 12 STAT_RXCLK_SEL 13 13 SC_TIMER_MODE 14 14 SKIP_EN 15 15 ixDPCSSYS_CR3_LANEX_DIG_RX_STAT_STAT_CTL1 2 0x9085 13 0 4294967295 STAT_CNT_0_EN 0 0 STAT_CNT_1_EN 1 1 STAT_CNT_2_EN 2 2 STAT_CNT_3_EN 3 3 STAT_CNT_4_EN 4 4 STAT_CNT_5_EN 5 5 STAT_CNT_6_EN 6 6 RESERVED_8_7 7 8 SC_PAUSE 9 9 STAT_CLK_EN 10 10 DATA_DLY_SEL 11 12 VLD_LOSS_CLR 13 13 VLD_CTL 14 15 ixDPCSSYS_CR3_LANEX_DIG_RX_STAT_SMPL_CNT1 2 0x9086 2 0 4294967295 SMPL_CNT1 0 14 SMPL_CNT1_DONE 15 15 ixDPCSSYS_CR3_LANEX_DIG_RX_STAT_STAT_CNT_0 2 0x9087 2 0 4294967295 STAT_CNT_0 0 14 SMPL_CNT1_DONE 15 15 ixDPCSSYS_CR3_LANEX_DIG_RX_STAT_STAT_CNT_1 2 0x9088 2 0 4294967295 STAT_CNT_1 0 14 SMPL_CNT1_DONE 15 15 ixDPCSSYS_CR3_LANEX_DIG_RX_STAT_STAT_CNT_2 2 0x9089 2 0 4294967295 STAT_CNT_2 0 14 SMPL_CNT1_DONE 15 15 ixDPCSSYS_CR3_LANEX_DIG_RX_STAT_STAT_CNT_3 2 0x908a 2 0 4294967295 STAT_CNT_3 0 14 SMPL_CNT1_DONE 15 15 ixDPCSSYS_CR3_LANEX_DIG_RX_STAT_STAT_CNT_4 2 0x908b 2 0 4294967295 STAT_CNT_4 0 14 SMPL_CNT1_DONE 15 15 ixDPCSSYS_CR3_LANEX_DIG_RX_STAT_STAT_CNT_5 2 0x908c 2 0 4294967295 STAT_CNT_5 0 14 SMPL_CNT1_DONE 15 15 ixDPCSSYS_CR3_LANEX_DIG_RX_STAT_STAT_CNT_6 2 0x908d 2 0 4294967295 STAT_CNT_6 0 14 SMPL_CNT1_DONE 15 15 ixDPCSSYS_CR3_LANEX_DIG_RX_STAT_CAL_COMP_CLK_CTL 2 0x908e 3 0 4294967295 PRECHRGE_CNT 0 2 REF_DIV_CNT 3 5 RESERVED_15_6 6 15 ixDPCSSYS_CR3_LANEX_DIG_RX_STAT_MATCH_CTL2 2 0x908f 2 0 4294967295 PTTRN_CR1A_19_5 0 14 RESERVED_15_15 15 15 ixDPCSSYS_CR3_LANEX_DIG_RX_STAT_MATCH_CTL3 2 0x9090 2 0 4294967295 PTTRN_MSK_CR1A_19_5 0 14 RESERVED_15_15 15 15 ixDPCSSYS_CR3_LANEX_DIG_RX_STAT_MATCH_CTL4 2 0x9091 2 0 4294967295 PTTRN_CR1B_19_5 0 14 RESERVED_15_15 15 15 ixDPCSSYS_CR3_LANEX_DIG_RX_STAT_MATCH_CTL5 2 0x9092 2 0 4294967295 PTTRN_MSK_CR1B_19_5 0 14 RESERVED_15_15 15 15 ixDPCSSYS_CR3_LANEX_DIG_RX_STAT_STAT_CTL2 2 0x9093 4 0 4294967295 DATA_DLY_SEL_2 0 0 SCOPE_DLY_2 1 1 DISABLE_SAMPLE_COUNT 2 2 RESERVED_15_3 3 15 ixDPCSSYS_CR3_LANEX_DIG_RX_STAT_STAT_STOP 2 0x9094 2 0 4294967295 SC1_STOP 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR3_LANEX_DIG_MPHY_RX_PWM_CTL 2 0x9095 3 0 4294967295 RX_PWM_POL 0 0 RX_PWM_DATA_POL 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR3_LANEX_DIG_MPHY_RX_TERM_LS_CTL 2 0x9096 2 0 4294967295 RX_TERM_LCC_CNT 0 2 RESERVED_15_3 3 15 ixDPCSSYS_CR3_LANEX_DIG_MPHY_RX_ANA_PWM_CLK_STABLE_CNT 2 0x9097 2 0 4294967295 PWM_CLK_STABLE_CNT 0 3 RESERVED_15_4 4 15 ixDPCSSYS_CR3_LANEX_DIG_ANA_TX_OVRD_OUT 2 0x90a0 15 0 4294967295 TX_ANA_CLK_SHIFT 0 0 TX_ANA_DATA_EN 1 1 TX_ANA_REFGEN_EN 2 2 TX_ANA_VCM_HOLD 3 3 TX_ANA_CLK_EN 4 4 TX_ANA_WORD_CLK_EN 5 5 TX_ANA_MPLLA_CLK_EN 6 6 TX_ANA_MPLLB_CLK_EN 7 7 TX_ANA_RESET 8 8 TX_ANA_SERIAL_EN 9 9 TX_ANA_DATA_RATE 10 11 RESERVED 12 12 TX_DIV4_EN 13 13 TX_RXDET_EN 14 14 TX_OVRD_EN 15 15 ixDPCSSYS_CR3_LANEX_DIG_ANA_TX_TERM_CODE_OVRD_OUT 2 0x90a1 5 0 4294967295 TX_TERM_CODE 0 9 TX_TERM_OVRD_EN 10 10 TX_DRV_SRC 11 12 TX_DRV_SRC_OVRD_EN 13 13 RESERVED_15_14 14 15 ixDPCSSYS_CR3_LANEX_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT 2 0x90a2 3 0 4294967295 TX_TERM_DN_CLK 0 0 TX_TERM_CLK_SELF_CLEAR_DISABLE 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR3_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_0 2 0x90a3 3 0 4294967295 TX_ANA_LOAD_CLK 0 0 TX_ANA_CTRL_LEG_PULL_EN_13_0 1 14 TX_EQ_OVRD_EN 15 15 ixDPCSSYS_CR3_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_1 2 0x90a4 2 0 4294967295 TX_ANA_CTRL_LEG_PULL_EN_19_14 0 5 RESERVED_15_6 6 15 ixDPCSSYS_CR3_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_2 2 0x90a5 4 0 4294967295 RESERVED 0 2 TX_ANA_CTRL_EQ_MUX_SEL 3 6 TX_ANA_CTRL_PRE 7 12 RESERVED_15_13 13 15 ixDPCSSYS_CR3_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_3 2 0x90a6 2 0 4294967295 TX_ANA_CTRL_POST 0 8 RESERVED_15_9 9 15 ixDPCSSYS_CR3_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_4 2 0x90a7 1 0 4294967295 TX_ANA_CTRL_LEG_PULL_DIR_19_4 0 15 ixDPCSSYS_CR3_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_5 2 0x90a8 2 0 4294967295 TX_ANA_CTRL_LEG_PULL_DIR_3_0 0 3 RESERVED_15_4 4 15 ixDPCSSYS_CR3_LANEX_DIG_ANA_RX_CTL_OVRD_OUT 2 0x90a9 9 0 4294967295 RESERVED 0 0 RX_ANA_DATA_RATE 1 2 RX_ANA_WORD_CLK_EN 3 3 RX_ANA_DIV4_EN 4 4 RX_ANA_DFE_TAPS_EN 5 5 RX_ANA_ADAPTATION_EN 6 6 RX_LBK_CLK_EN 7 7 RX_CTL_OVRD_EN 8 8 RESERVED_15_9 9 15 ixDPCSSYS_CR3_LANEX_DIG_ANA_RX_PWR_OVRD_OUT 2 0x90aa 9 0 4294967295 RX_ANA_AFE_EN 0 0 RX_ANA_CLK_VREG_EN 1 1 RX_ANA_CLK_DCC_EN 2 2 RX_ANA_CLK_EN 3 3 RX_ANA_CDR_EN 4 4 RX_ANA_DESERIAL_EN 5 5 RX_PWR_OVRD_EN 6 6 RX_ANA_FAST_START 7 7 RESERVED_15_8 8 15 ixDPCSSYS_CR3_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0 2 0x90ab 7 0 4294967295 RX_ANA_CDR_VCO_EN 0 0 RX_ANA_CDR_STARTUP 1 1 RX_VCO_CDR_OVRD_EN 2 2 RX_ANA_CDR_FREQ_TUNE 3 12 RX_ANA_VCO_CNTR_EN 13 13 RX_ANA_VCO_CNTR_CLK 14 14 RX_CDR_FREQ_TUNE_OVRD_EN 15 15 ixDPCSSYS_CR3_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_1 2 0x90ac 3 0 4294967295 RX_ANA_CDR_VCO_LOWFREQ 0 0 RX_ANA_VCO_CNTR_PD 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR3_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_2 2 0x90ad 3 0 4294967295 RX_ANA_CDR_FREQ_TUNE_CLK 0 0 CDR_FREQ_TUNE_CLK_SELF_CLEAR_DISABLE 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR3_LANEX_DIG_ANA_RX_CAL 2 0x90ae 7 0 4294967295 RX_ANA_CAL_MUXA_SEL 0 4 RX_ANA_CAL_MUXB_SEL 5 9 RX_ANA_CAL_LPFBYP_EN 10 10 RESERVED 11 11 RX_ANA_SLICER_CAL_EN 12 12 RX_ANA_CAL_MODE 13 14 RX_ANA_CAL_COMP_EN 15 15 ixDPCSSYS_CR3_LANEX_DIG_ANA_RX_DAC_CTRL 2 0x90af 2 0 4294967295 RX_ANA_CAL_DAC_CTRL 0 7 RESERVED_15_8 8 15 ixDPCSSYS_CR3_LANEX_DIG_ANA_RX_DAC_CTRL_OVRD 2 0x90b0 2 0 4294967295 RX_CAL_DAC_CTRL_OVRD 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR3_LANEX_DIG_ANA_RX_DAC_CTRL_SEL 2 0x90b1 2 0 4294967295 RX_ANA_CAL_DAC_CTRL_SEL 0 4 RESERVED_15_5 5 15 ixDPCSSYS_CR3_LANEX_DIG_ANA_RX_AFE_ATT_VGA 2 0x90b2 5 0 4294967295 RX_ANA_AFE_ATT_LVL 0 2 RX_ANA_AFE_GAIN 3 6 RESERVED 7 10 RX_AFE_OVRD_EN 11 11 RESERVED_15_12 12 15 ixDPCSSYS_CR3_LANEX_DIG_ANA_RX_AFE_CTLE 2 0x90b3 3 0 4294967295 RESERVED 0 2 RX_ANA_AFE_CTLE_BOOST 3 7 RESERVED_15_8 8 15 ixDPCSSYS_CR3_LANEX_DIG_ANA_RX_SCOPE 2 0x90b4 7 0 4294967295 RX_ANA_SCOPE_EN 0 0 RX_ANA_SCOPE_SEL 1 2 RX_ANA_SCOPE_PH_CLK 3 3 RX_ANA_SCOPE_PHASE 4 11 RX_ANA_SCOPE_CLK_EN 12 12 RX_SCOPE_SELF_CLEAR_DISABLE 13 13 RESERVED_15_14 14 15 ixDPCSSYS_CR3_LANEX_DIG_ANA_RX_SLICER_CTRL 2 0x90b5 4 0 4294967295 RX_ANA_SLICER_CTRL_E 0 3 RX_ANA_SLICER_CTRL_O 4 7 RX_ANA_SLICER_CTRL_OVRD_EN 8 8 RESERVED_15_9 9 15 ixDPCSSYS_CR3_LANEX_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST 2 0x90b6 2 0 4294967295 RX_ANA_IQ_PHASE_ADJUST 0 6 RESERVED_15_7 7 15 ixDPCSSYS_CR3_LANEX_DIG_ANA_RX_ANA_IQ_SENSE_EN 2 0x90b7 2 0 4294967295 RX_ANA_IQ_SENSE_EN 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR3_LANEX_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN 2 0x90b8 3 0 4294967295 RX_ANA_CAL_DAC_CTRL_EN 0 0 DAC_CTRL_SELF_CLEAR_DISABLE 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR3_LANEX_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE 2 0x90b9 3 0 4294967295 RX_ANA_AFE_UPDATE_EN 0 0 AFE_UPDATE_SELF_CLEAR_DISABLE 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR3_LANEX_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK 2 0x90ba 3 0 4294967295 RX_ANA_IQ_PHASE_ADJUST_CLK 0 0 PHASE_ADJUST_SELF_CLEAR_DISABLE 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR3_LANEX_DIG_ANA_STATUS_0 2 0x90bb 9 0 4294967295 TX_ANA_CLK_SHIFT_ACK 0 0 TX_ANA_RXDETP_RESULT 1 1 TX_ANA_RXDETM_RESULT 2 2 TX_ANA_LOOPBACK_EN 3 3 TX_ANA_CLK_LB_EN 4 4 RX_ANA_CAL_RESULT 5 5 RX_ANA_SCOPE_DATA 6 6 TX_ANA_DCC_CAL_RESULT 7 7 TX_ANA_CTRL_EQ_MUX 8 15 ixDPCSSYS_CR3_LANEX_DIG_ANA_STATUS_1 2 0x90bc 2 0 4294967295 RX_ANA_VCO_CNTR 0 12 RESERVED_15_13 13 15 ixDPCSSYS_CR3_LANEX_DIG_ANA_RX_TERM_CODE_OVRD_OUT 2 0x90bd 3 0 4294967295 RX_TERM_CODE 0 5 RX_TERM_OVRD_EN 6 6 RESERVED_15_7 7 15 ixDPCSSYS_CR3_LANEX_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT 2 0x90be 3 0 4294967295 RX_TERM_CLK 0 0 RX_TERM_CLK_SELF_CLEAR_DISABLE 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR3_LANEX_DIG_ANA_MPHY_OVRD_OUT 2 0x90bf 9 0 4294967295 RX_ANA_SQ_CTRL_TRESH 0 2 RX_ANA_SQ_CTRL_TRESH_OVRD_EN 3 3 RX_ANA_SQ_CTRL_RESP 4 5 RX_ANA_SQ_CTRL_RESP_OVRD_EN 6 6 RX_ANA_PWM_EN 7 7 RX_ANA_PWM_EN_OVRD_EN 8 8 RX_ANA_PWM_CLK_SEL 9 10 RX_ANA_PWM_CLK_SEL_OVRD_EN 11 11 RESERVED_15_12 12 15 ixDPCSSYS_CR3_LANEX_DIG_ANA_SIGDET_OVRD_OUT_1 2 0x90c0 7 0 4294967295 RX_ANA_SIGDET_HF_THRESH 0 2 RX_ANA_SIGDET_HF_THRESH_OVRD_EN 3 3 RX_ANA_SIGDET_HF_CAL_TUNE 4 9 RX_ANA_SIGDET_CAL_TUNE_OVRD_EN 10 10 RX_ANA_SIGDET_CAL_EN 11 11 RX_ANA_SIGDET_CAL_EN_OVRD_EN 12 12 RESERVED_15_13 13 15 ixDPCSSYS_CR3_LANEX_DIG_ANA_SIGDET_OVRD_OUT_2 2 0x90c1 7 0 4294967295 RX_ANA_SIGDET_LF_THRESH 0 2 RX_ANA_SIGDET_LF_THRESH_OVRD_EN 3 3 RX_ANA_SIGDET_LF_FILTER_EN 4 4 RX_ANA_SIGDET_LF_FILTER_EN_OVRD_EN 5 5 RX_ANA_SIGDET_CAL_TUNE 6 11 RX_ANA_SIGDET_CAL_TUNE_OVRD_EN 12 12 RESERVED_15_13 13 15 ixDPCSSYS_CR3_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT 2 0x90c2 8 0 4294967295 TX_ANA_DCC_CAL_RANGE 0 1 TX_ANA_DCC_CAL_RANGE_OVRD_EN 2 2 TX_ANA_DCC_CAL_COMP_EN 3 3 TX_ANA_DCC_CAL_COMP_EN_OVRD_EN 4 4 TX_ANA_DCC_CAL_CTRL 5 12 TX_ANA_DCC_CAL_CTRL_OVRD_EN 13 13 TX_ANA_DCC_CAL_CTRL_EN 14 14 TX_ANA_DCC_CAL_CTRL_EN_OVRD_EN 15 15 ixDPCSSYS_CR3_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2 2 0x90c3 5 0 4294967295 TX_ANA_DCC_CAL_CTRL_SEL 0 2 TX_ANA_DCC_CAL_CTRL_SEL_OVRD_EN 3 3 TX_ANA_DCC_CLK_COMP 4 4 TX_ANA_DCC_CLK_COMP_OVRD_EN 5 5 RESERVED_15_6 6 15 ixDPCSSYS_CR3_LANEX_DIG_ANA_TX_OVRD_OUT_2 2 0x90c4 6 0 4294967295 TX_ANA_FAST_START 0 0 TX_ANA_FAST_START_OVRD_EN 1 1 TX_CLK_LB_EN 2 2 TX_CLK_LB_EN_OVRD_EN 3 3 TX_ACJTAG_EN 4 4 RESERVED_15_5 5 15 ixDPCSSYS_CR3_LANEX_ANA_TX_OVRD_MEAS 2 0x90e0 9 0 4294967295 OVRD_CLK_SHIFT 0 0 CLK_SHIFT_REG 0 0 MEAS_ATB_CAL_MUX 0 0 MEAS_ATB_CAL_COMP 0 0 OVRD_VCM_HOLD 0 0 VCM_HOLD_REG 0 0 PULL_UP_REG 0 0 PULL_DN_REG 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR3_LANEX_ANA_TX_PWR_OVRD 2 0x90e1 9 0 4294967295 OVRD_TX_LOOPBACK 0 0 LOOPBACK_EN_REG 0 0 REFGEN_EN_REG 0 0 CLK_DIV_EN_REG 0 0 DATA_EN_REG_INT 0 0 CLK_EN_REG 0 0 SERIAL_EN_REG 0 0 OVRD_EN 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR3_LANEX_ANA_TX_ALT_BUS 2 0x90e2 6 0 4294967295 DRV_SOURCE_REG 0 0 OVRD_ALT_BUS 0 0 ATB_S_ENABLE 0 0 TX_ALT_RINGO 0 0 JTAG_DATA_REG 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR3_LANEX_ANA_TX_ATB1 2 0x90e3 9 0 4294967295 MEAS_ATB_GD 0 0 MEAS_ATB_VDDH 0 0 OVERRIDE_RXDETREF 0 0 MEAS_ATB_VPTX 0 0 OVERRIDE_REGREF 0 0 MEAS_ATB_VREG_DRV 0 0 MEAS_ATB_VREG 0 0 MEAS_ATB_VPH_HALF 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR3_LANEX_ANA_TX_ATB2 2 0x90e4 9 0 4294967295 MEAS_ATB_VCM 0 0 MEAS_ATB_CAL_VDAC_CM 0 0 MEAS_ATB_CAL_VDAC_DIFF 0 0 MEAS_ATB_TXM 0 0 MEAS_ATB_TXP 0 0 MEAS_ATB_RXDETREF 0 0 LFPS_HIGH_PRIORITY 0 0 OSC_DIV4_EN 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR3_LANEX_ANA_TX_DCC_DAC 2 0x90e5 2 0 4294967295 DCC_DAC_REG 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR3_LANEX_ANA_TX_DCC_CTRL1 2 0x90e6 7 0 4294967295 NC0 0 0 OVRD_DCC_DAC_CTRL_SEL 0 0 DCC_DAC_CTRL_SEL_REG 0 0 OVRD_DCC_DAC_CTRL_EN 0 0 DCC_DAC_CTRL_EN_REG 0 0 OVRD_DCC_DAC_REG 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR3_LANEX_ANA_TX_TERM_CODE 2 0x90e7 2 0 4294967295 TERM_CODE_REG_70 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR3_LANEX_ANA_TX_TERM_CODE_CTRL 2 0x90e8 8 0 4294967295 VREG_BOOST_1 0 0 OVRD_UPDATE_TERM 0 0 UPDATE_TERM_REG 0 0 OVRD_RESET_TERM 0 0 RESET_TERM_REG 0 0 OVRD_TERM_CODE 0 0 TERM_CODE_REG_98 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR3_LANEX_ANA_TX_OVRD_CLK 2 0x90e9 9 0 4294967295 VREG_BOOST_0 0 0 CLK_LB_EN_REG 0 0 OVRD_LB_EN 0 0 MPLLB_CLK_EN_REG 0 0 MPLLA_CLK_EN_REG 0 0 OVRD_MPLLAB_EN 0 0 WORD_CLK_EN_REG 0 0 OVRD_WORD_CLK_EN 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR3_LANEX_ANA_TX_MISC1 2 0x90ea 8 0 4294967295 MEAS_ATB_CAL_CLK_ALIGN 0 0 OVRD_DCC_DAC_CTRL_RANGE 0 0 DCC_DAC_CTRL_RANGE_REG 0 0 OVRD_VREF_SEL 0 0 VREF_SEL_REG 0 0 FORCE_ATB_TXM 0 0 FORCE_ATB_TXP 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR3_LANEX_ANA_TX_MISC2 2 0x90eb 8 0 4294967295 TX_PEAKING_LVL 0 0 VREG_CP_GAIN_CTRL 0 0 TX_SLEW_EN 0 0 EN_INV_POST 0 0 EN_INV_PRE 0 0 TX_VREG_EN_BYP 0 0 TX_VDRIVER_PULLDN_EN 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR3_LANEX_ANA_TX_MISC3 2 0x90ec 4 0 4294967295 TX_VREG_OVRD_RING_CTRL 0 0 TX_DCC_LOWV 0 0 NC7_2 2 7 RESERVED_15_8 8 15 ixDPCSSYS_CR3_LANEX_ANA_TX_RESERVED2 2 0x90ed 2 0 4294967295 NC7_0 0 7 RESERVED_15_8 8 15 ixDPCSSYS_CR3_LANEX_ANA_TX_RESERVED3 2 0x90ee 2 0 4294967295 NC7_0 0 7 RESERVED_15_8 8 15 ixDPCSSYS_CR3_LANEX_ANA_TX_RESERVED4 2 0x90ef 2 0 4294967295 NC7_0 0 7 RESERVED_15_8 8 15 ixDPCSSYS_CR3_LANEX_ANA_RX_CLK_1 2 0x90f0 8 0 4294967295 CDR_VCO_STARTUP_CODE 0 0 CDR_VCO_TEMP_COMP_EN 0 0 CDR_VCO_USE_UNCAL_BIAS 0 0 OVERRIDE_CDR_EN 0 0 OVRD_CLK_EN 0 0 CLK_EN_REG 0 0 NC7 7 7 RESERVED_15_8 8 15 ixDPCSSYS_CR3_LANEX_ANA_RX_CLK_2 2 0x90f1 5 0 4294967295 IQ_PHASE_ADJUST_REG 0 0 OVRD_IQ_PHASE_ADJUST 0 0 RX_LOOPBACK_CLK_REG 0 0 OVRD_RX_LOOPBACK_CLK 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR3_LANEX_ANA_RX_CDR_DES 2 0x90f2 7 0 4294967295 OVRD_WORD_CLK_EN 0 0 WORD_CLK_EN_REG 0 0 PHDET_ODD_REG 0 0 PHDET_EVEN_REG 0 0 SIGDET_VREF_EXT_EN 0 0 NC7_5 5 7 RESERVED_15_8 8 15 ixDPCSSYS_CR3_LANEX_ANA_RX_SLC_CTRL 2 0x90f3 3 0 4294967295 RX_SLICER_CTRL_O_REG 0 0 RX_SLICER_CTRL_E_REG 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR3_LANEX_ANA_RX_PWR_CTRL1 2 0x90f4 8 0 4294967295 OVRD_ACJT_EN 0 0 ACJT_EN_REG 0 0 OVRD_AFE_EN 0 0 AFE_EN_REG 0 0 AFE_CM_SEL 0 0 ATT_PULLDN_EN 0 0 NC7_7 7 7 RESERVED_15_8 8 15 ixDPCSSYS_CR3_LANEX_ANA_RX_PWR_CTRL2 2 0x90f5 9 0 4294967295 OVRD_DFE_EN 0 0 DFE_EN_REG 0 0 OVRD_DESERIAL_EN 0 0 DESERIAL_EN_REG 0 0 OVRD_LOOPBACK_EN 0 0 LOOPBACK_EN_REG 0 0 OVRD_FAST_START 0 0 FAST_START_REG 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR3_LANEX_ANA_RX_SQ 2 0x90f6 7 0 4294967295 SQ_CTRL_RESP_REG 0 0 OVRD_SQ_CTRL_RESP 0 0 NC4_3 3 4 SQ_CTRL_TRESH_REG 0 0 OVRD_SQ_CTRL_TRESH 0 0 AFE_LOOPBACK_SEL 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR3_LANEX_ANA_RX_CAL1 2 0x90f7 5 0 4294967295 DFE_TAPS_EN_REG 0 0 OVRD_DFE_TAPS_EN 0 0 CAL_MUXB_SEL_REG 0 0 OVRD_CAL_MUXB_SEL 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR3_LANEX_ANA_RX_CAL2 2 0x90f8 5 0 4294967295 AFE_PD_EQ_OFFSET 0 0 CAL_IDACS_USE_UNCAL 0 0 CAL_MUXA_SEL_REG 0 0 OVRD_CAL_MUXA_SEL 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR3_LANEX_ANA_RX_ATB_REGREF 2 0x90f9 8 0 4294967295 OVERRIDE_REGREF_VCO 0 0 OVERRIDE_REGREF_CLK 0 0 OVERRIDE_REGREF_IQC 0 0 BOOST_REGREF_IQC 0 0 OVRD_RX_SLICER_CTRL 0 0 OVRD_RX_TERM_AC_DCZ 0 0 RX_TERM_AC_DCZ_REG 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR3_LANEX_ANA_RX_ATB_MEAS1 2 0x90fa 9 0 4294967295 MASTER_ATB_EN 0 0 MEAS_ATB_VP 0 0 MEAS_ATB_GD 0 0 MEAS_ATB_VREG_VCO 0 0 MEAS_ATB_VREG_CLK 0 0 MEAS_ATB_VREG_IQC 0 0 REGS_FB_DIV_CTRL 0 0 RX_VREG_CLK_BYPASS 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR3_LANEX_ANA_RX_ATB_MEAS2 2 0x90fb 2 0 4294967295 MEAS_ATB_RX 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR3_LANEX_ANA_RX_ATB_MEAS3 2 0x90fc 7 0 4294967295 MEAS_ATB_CDR_VCO_GD 0 0 MEAS_ATB_CDR_VCO_VIREF_200U 0 0 MEAS_ATB_VIBIAS_CDR_VCO 0 0 MEAS_ATB_CDR_VCO_VOSC 0 0 MEAS_ATB_CAL_MUX 0 0 RX_VREG_OVERRIDE_RING_CTRL 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR3_LANEX_ANA_RX_ATB_MEAS4 2 0x90fd 3 0 4294967295 MEAS_ATB_CAL_VREF 0 0 NC7 7 7 RESERVED_15_8 8 15 ixDPCSSYS_CR3_LANEX_ANA_RX_ATB_FRC 2 0x90fe 2 0 4294967295 FRC_ATB_CAL_VREF 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR3_LANEX_ANA_RX_RESERVED1 2 0x90ff 2 0 4294967295 NC7_0 0 7 RESERVED_15_8 8 15 ixDPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN 2 0xe000 12 0 4294967295 PSTATE 0 1 LPD 2 2 WIDTH 3 4 RATE 5 7 MPLLB_SEL 8 8 MPLL_EN 9 9 OVRD_EN 10 10 MSTR_MPLLA_STATE 11 11 MSTR_MPLLB_STATE 12 12 MSTR_MPLL_OVRD_EN 13 13 TX_ASYNC_EN_OVR_VAL 14 14 TX_ASYNC_EN_OVR_EN 15 15 ixDPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1 2 0xe001 13 0 4294967295 RESET_OVRD_VAL 0 0 RESET_OVRD_EN 1 1 REQ_OVRD_VAL 2 2 REQ_OVRD_EN 3 3 DETRX_REQ_OVRD_VAL 4 4 DETRX_REQ_OVRD_EN 5 5 VBOOST_EN_OVRD_VAL 6 6 VBOOST_EN_OVRD_EN 7 7 IBOOST_LVL_OVRD_VAL 8 11 IBOOST_LVL_OVRD_EN 12 12 TX_BEACON_EN_OVR_VAL 13 13 TX_BEACON_EN_OVR_EN 14 14 RESERVED_15_15 15 15 ixDPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_PCS_IN 2 0xe002 12 0 4294967295 RESET 0 0 REQ 1 1 PSTATE 2 3 LPD 4 4 WIDTH 5 6 RATE 7 9 MPLLB_SEL 10 10 MPLL_EN 11 11 MSTR_MPLLA_STATE 12 12 MSTR_MPLLB_STATE 13 13 DETRX_REQ 14 14 RESERVED_15_15 15 15 ixDPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_OVRD_OUT 2 0xe003 6 0 4294967295 ACK 0 0 DETRX_RESULT 1 1 EN_CTL 2 2 TX_DWORD_CLK_SYNC_OVRD_VAL 3 3 TX_DWORD_CLK_SYNC_OVRD_EN 4 4 RESERVED_15_5 5 15 ixDPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_PCS_OUT 2 0xe004 2 0 4294967295 ACK 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN 2 0xe005 12 0 4294967295 RATE 0 1 WIDTH 2 3 PSTATE 4 5 LPD 6 6 OVRD_EN 7 7 ADAPT_AFE_EN 8 8 ADAPT_DFE_EN 9 9 LANE_RX2TX_PAR_LB_EN_OVRD_VAL 10 10 LANE_RX2TX_PAR_LB_EN_OVRD_EN 11 11 RX_DATA_EN_OVRD_VAL_R 12 12 RX_DATA_EN_OVRD_EN_R 13 13 RESERVED_15_14 14 15 ixDPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1 2 0xe006 12 0 4294967295 RESET_OVRD_VAL 0 0 RESET_OVRD_EN 1 1 REQ_OVRD_VAL 2 2 REQ_OVRD_EN 3 3 RX_LOS_THRSHLD_OVRD_VAL 4 6 RX_LOS_THRSHLD_OVRD_EN 7 7 ADAPT_REQ 8 8 ADAPT_REQ_OVRD_EN 9 9 ADAPT_CONT 10 10 OFFCAN_CONT 11 11 CONT_OVRD_EN 12 12 RESERVED_15_13 13 15 ixDPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_2 2 0xe007 4 0 4294967295 VCO_LD_VAL_OVRD 0 12 VCO_LD_VAL_OVRD_EN 13 13 VCO_LOWFREQ_VAL_OVRD 14 14 VCO_LOWFREQ_VAL_OVRD_EN 15 15 ixDPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_3 2 0xe008 3 0 4294967295 REF_LD_VAL_OVRD 0 6 REF_LD_VAL_OVRD_EN 7 7 RESERVED_15_8 8 15 ixDPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_PCS_IN 2 0xe009 13 0 4294967295 REQ 0 0 RATE 1 2 WIDTH 3 4 PSTATE 5 6 LPD 7 7 CDR_VCO_LOWFREQ 8 8 ADAPT_AFE_EN 9 9 ADAPT_DFE_EN 10 10 ADAPT_REQ 11 11 ADAPT_CONT 12 12 OFFCAN_CONT 13 13 RESET 14 14 RESERVED_15_15 15 15 ixDPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_1 2 0xe00a 2 0 4294967295 REF_LD_VAL 0 6 RESERVED_15_7 7 15 ixDPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_2 2 0xe00b 2 0 4294967295 VCO_LD_VAL 0 12 RESERVED_15_13 13 15 ixDPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_3 2 0xe00c 4 0 4294967295 EQ_ATT_LVL 0 2 EQ_VGA1_GAIN 3 6 EQ_VGA2_GAIN 7 10 EQ_CTLE_BOOST 11 15 ixDPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_4 2 0xe00d 3 0 4294967295 EQ_CTLE_POLE 0 2 EQ_DFE_TAP1 3 10 RESERVED_15_11 11 15 ixDPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT 2 0xe00e 3 0 4294967295 ACK 0 0 EN_CTL 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_PCS_OUT 2 0xe00f 2 0 4294967295 ACK 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_ADAPT_ACK 2 0xe010 2 0 4294967295 RX_ADAPT_ACK 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_ADAPT_FOM 2 0xe011 2 0 4294967295 RX_ADAPT_FOM 0 7 RESERVED_15_8 8 15 ixDPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_TXPRE_DIR 2 0xe012 2 0 4294967295 RX_TXPRE_DIR 0 1 RESERVED_15_2 2 15 ixDPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_TXMAIN_DIR 2 0xe013 2 0 4294967295 RX_TXMAIN_DIR 0 1 RESERVED_15_2 2 15 ixDPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_TXPOST_DIR 2 0xe014 2 0 4294967295 RX_TXPOST_DIR 0 1 RESERVED_15_2 2 15 ixDPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_LANE_NUMBER 2 0xe015 2 0 4294967295 LANE_NUMBER 0 3 RESERVED_15_4 4 15 ixDPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RESERVED_1 2 0xe016 1 0 4294967295 RESERVED_REG_1 0 15 ixDPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RESERVED_2 2 0xe017 1 0 4294967295 RESERVED_REG_2 0 15 ixDPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN 2 0xe018 16 0 4294967295 RX_RESET_ATE_OVRD_VAL 0 0 RX_RESET_ATE_OVRD_EN 1 1 TX_RESET_ATE_OVRD_VAL 2 2 TX_RESET_ATE_OVRD_EN 3 3 RX_REQ_ATE_OVRD_VAL 4 4 RX_REQ_ATE_OVRD_EN 5 5 TX_REQ_ATE_OVRD_VAL 6 6 TX_REQ_ATE_OVRD_EN 7 7 RX_ADAPT_AFE_EN_OVRD_VAL 8 8 RX_ADAPT_AFE_EN_OVRD_EN 9 9 RX_ADAPT_DFE_EN_OVRD_VAL 10 10 RX_ADAPT_DFE_EN_OVRD_EN 11 11 TX_DATA_EN_ATE_OVRD_VAL 12 12 TX_DATA_EN_ATE_OVRD_EN 13 13 RX_DATA_EN_ATE_OVRD_VAL 14 14 RX_DATA_EN_ATE_OVRD_EN 15 15 ixDPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN 2 0xe019 3 0 4294967295 RX_EQ_DELTA_IQ_OVRD_VAL 0 3 RX_EQ_DELTA_IQ_OVRD_EN 4 4 RESERVED_15_5 5 15 ixDPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN 2 0xe01a 5 0 4294967295 RX_TERM_CTRL_OVRD_VAL 0 2 RX_TERM_CTRL_OVRD_EN 3 3 TX_TERM_CTRL_OVRD_VAL 4 6 TX_TERM_CTRL_OVRD_EN 7 7 RESERVED_15_8 8 15 ixDPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TXRX_TERM_CTRL_IN 2 0xe01b 3 0 4294967295 RX_TERM_CTRL 0 2 TX_TERM_CTRL 3 5 RESERVED_15_6 6 15 ixDPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT_1 2 0xe01c 2 0 4294967295 RX_CLK_EN 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_EQ_OVRD_IN_1 2 0xe01d 4 0 4294967295 RX_EQ_AFE_GAIN_OVRD_VAL 0 3 RX_EQ_ATT_LVL_OVRD_VAL 4 6 RX_EQ_OVRD_EN 7 7 RESERVED_15_8 8 15 ixDPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_EQ_OVRD_IN_2 2 0xe01e 3 0 4294967295 RX_EQ_DFE_TAP1_OVRD_VAL 0 7 RX_EQ_CTLE_BOOST_OVRD_VAL 8 12 RESERVED_15_13 13 15 ixDPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_PH2_CAL 2 0xe01f 4 0 4294967295 PH2_CAL_ACK_VAL 0 0 PH2_CAL_REQ_VAL 1 1 PH2_CAL_REQ_OVRD_VAL 2 2 RESERVED_15_3 3 15 ixDPCSSYS_CR3_RAWLANEX_DIG_FSM_FSM_OVRD_CTL 2 0xe020 5 0 4294967295 FSM_JMP_ADDR 0 11 FSM_JMP_EN 12 12 FSM_CMD_START 13 13 FSM_OVRD_EN 14 14 FSM_BREAK 15 15 ixDPCSSYS_CR3_RAWLANEX_DIG_FSM_MEM_ADDR_MON 2 0xe021 1 0 4294967295 MEM_ADDR 0 15 ixDPCSSYS_CR3_RAWLANEX_DIG_FSM_STATUS_MON 2 0xe022 8 0 4294967295 STATE 0 4 CMD_RDY 5 5 ALU_OVFLW 6 6 ALU_RES_EQ0 7 7 WAIT_CNT_EQ0 8 8 WRMSK_DISABLED 9 9 RDMSK_DISABLED 10 10 RESERVED_15_11 11 15 ixDPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_RX_STARTUP_CAL 2 0xe023 2 0 4294967295 FAST_RX_STARTUP_CAL 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_RX_ADAPT 2 0xe024 2 0 4294967295 FAST_RX_ADAPT 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_RX_AFE_CAL 2 0xe025 2 0 4294967295 FAST_RX_AFE_CAL 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_RX_DFE_CAL 2 0xe026 2 0 4294967295 FAST_RX_DFE_CAL 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_RX_BYPASS_CAL 2 0xe027 2 0 4294967295 FAST_RX_BYPASS_CAL 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_RX_REFLVL_CAL 2 0xe028 2 0 4294967295 FAST_RX_REFLVL_CAL 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_RX_IQ_CAL 2 0xe029 2 0 4294967295 FAST_RX_IQ_CAL 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_RX_AFE_ADAPT 2 0xe02a 2 0 4294967295 FAST_RX_AFE_ADAPT 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_RX_DFE_ADAPT 2 0xe02b 2 0 4294967295 FAST_RX_DFE_ADAPT 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_SUP 2 0xe02c 2 0 4294967295 FAST_SUP 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_TX_CMN_MODE 2 0xe02d 2 0 4294967295 FAST_TX_CMN_MODE 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_TX_RXDET 2 0xe02e 2 0 4294967295 FAST_TX_RXDET 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_RX_PWRUP 2 0xe02f 2 0 4294967295 FAST_RX_PWRUP 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_RX_VCO_WAIT 2 0xe030 2 0 4294967295 FAST_RX_VCO_WAIT 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_RX_VCO_CAL 2 0xe031 2 0 4294967295 FAST_RX_VCO_CAL 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR3_RAWLANEX_DIG_FSM_CMNCAL_MPLL_STATUS 2 0xe032 3 0 4294967295 CMNCAL_MPLL_INIT 0 0 CMNCAL_MPLL_DONE 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_RX_CONT_CAL_ADAPT 2 0xe033 2 0 4294967295 FAST_RX_CONT_CAL_ADAPT 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_RX_CONT_ADAPT 2 0xe034 2 0 4294967295 FAST_RX_CONT_ADAPT 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_RX_CONT_DATA_CAL 2 0xe035 2 0 4294967295 FAST_RX_CONT_DATA_CAL 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_RX_CONT_PHASE_CAL 2 0xe036 2 0 4294967295 FAST_RX_CONT_PHASE_CAL 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_RX_CONT_AFE_CAL 2 0xe037 2 0 4294967295 FAST_RX_CONT_AFE_CAL 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_FLAGS 2 0xe038 12 0 4294967295 TX_FAST_DCC_CAL 0 0 RX_FAST_DCC_CAL 1 1 RX_FAST_VPHUD_CAL 2 2 RX_FAST_VREF_CAL 3 3 RX_FAST_SIGDET_CAL 4 4 RESERVED_2 5 7 TX_FAST_CONT_DCC_CAL 8 8 RX_FAST_CONT_DCC_CAL 9 9 RX_FAST_CONT_VPHUD_CAL 10 10 RX_FAST_CONT_VREF_CAL 11 11 RESERVED_1 12 14 TX_SKIP_SUP_CAL 15 15 ixDPCSSYS_CR3_RAWLANEX_DIG_FSM_CR_LOCK 2 0xe039 3 0 4294967295 CR_REG_LOCK 0 0 CR_MEM_LOCK 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR3_RAWLANEX_DIG_FSM_TX_DCC_FLAGS 2 0xe03a 4 0 4294967295 RATE 0 0 DIV 1 1 MPLL 2 2 RESERVED_15_3 3 15 ixDPCSSYS_CR3_RAWLANEX_DIG_FSM_TX_DCC_STATUS 2 0xe03b 2 0 4294967295 FLAG 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR3_RAWLANEX_DIG_FSM_OCLA 2 0xe03c 4 0 4294967295 PC_EN 0 0 REG_BANK1_EN 1 1 REG_BANK2_EN 2 2 RESERVED_15_3 3 15 ixDPCSSYS_CR3_RAWLANEX_DIG_FSM_TX_EQ_UPDATE_FLAG 2 0xe03d 2 0 4294967295 TX_EQ_UPDATE_FLAG 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR3_RAWLANEX_DIG_FSM_CMNCAL_RCAL_STATUS 2 0xe03e 3 0 4294967295 CMNCAL_RCAL_INIT 0 0 CMNCAL_RCAL_DONE 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR3_RAWLANEX_DIG_FSM_RX_IQ_PHASE_OFFSET 2 0xe03f 2 0 4294967295 RX_IQ_PHASE_OFFSET 0 3 RESERVED_15_4 4 15 ixDPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_RESET_RTN_REQ 2 0xe040 2 0 4294967295 RESET_RTN_REQ 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_RX_RESET_IRQ 2 0xe041 2 0 4294967295 RX_RESET 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_RX_REQ_IRQ 2 0xe042 2 0 4294967295 RX_REQ 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_RX_RATE_IRQ 2 0xe043 2 0 4294967295 RX_RATE_IRQ 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_RX_PSTATE_IRQ 2 0xe044 2 0 4294967295 RX_PSTATE_IRQ 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ 2 0xe045 2 0 4294967295 RX_ADAPT_REQ_IRQ 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ 2 0xe046 2 0 4294967295 RX_ADAPT_DIS_IRQ 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_RX_RESET_IRQ_CLR 2 0xe047 2 0 4294967295 RX_RESET_IRQ_CLR 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_RX_REQ_IRQ_CLR 2 0xe048 2 0 4294967295 RX_REQ_IRQ_CLR 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_RX_RATE_IRQ_CLR 2 0xe049 2 0 4294967295 RX_RATE_IRQ_CLR 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR 2 0xe04a 2 0 4294967295 RX_PSTATE_IRQ_CLR 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR 2 0xe04b 2 0 4294967295 RX_ADAPT_REQ_IRQ_CLR 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR 2 0xe04c 2 0 4294967295 RX_ADAPT_DIS_IRQ_CLR 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK 2 0xe04d 12 0 4294967295 RX_REQ_IRQ_MSK 0 0 RX_RATE_IRQ_MSK 1 1 RX_PSTATE_IRQ_MSK 2 2 RX_ADAPT_REQ_IRQ_MSK 3 3 RX_ADAPT_DIS_IRQ_MSK 4 4 RX_RESET_IRQ_MSK 5 5 LANE_XCVR_MODE_IRQ_MSK 6 6 RX_PH2_CAL_REQ_IRQ_MSK 7 7 RX_PH2_CAL_DIS_IRQ_MSK 8 8 LANE_RX2TX_SER_LB_EN_IRQ_MSK 9 9 DCC_ONDMD_IRQ_MSK 10 10 RESERVED_15_11 11 15 ixDPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK_2 2 0xe04e 3 0 4294967295 TX_RESET_IRQ_MSK 0 0 TX_REQ_IRQ_MSK 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ 2 0xe04f 2 0 4294967295 LANE_XCVR_MODE_IRQ 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR 2 0xe050 2 0 4294967295 LANE_XCVR_MODE_IRQ_CLR 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ 2 0xe051 2 0 4294967295 RX_PH2_CAL_REQ_IRQ 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ 2 0xe052 2 0 4294967295 RX_PH2_CAL_DIS_IRQ 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR 2 0xe053 2 0 4294967295 RX_PH2_CAL_REQ_IRQ_CLR 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR 2 0xe054 2 0 4294967295 RX_PH2_CAL_DIS_IRQ_CLR 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ 2 0xe055 2 0 4294967295 LANE_RX2TX_SER_LB_EN_IRQ 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR 2 0xe056 2 0 4294967295 LANE_RX2TX_SER_LB_EN_IRQ_CLR 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_DCC_ONDMD_IRQ 2 0xe057 2 0 4294967295 IRQ 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_TX_RESET_IRQ 2 0xe058 2 0 4294967295 TX_RESET 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_TX_REQ_IRQ 2 0xe059 2 0 4294967295 TX_REQ 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_TX_RESET_IRQ_CLR 2 0xe05a 2 0 4294967295 TX_RESET_IRQ_CLR 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_TX_REQ_IRQ_CLR 2 0xe05b 2 0 4294967295 TX_REQ_IRQ_CLR 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_LANE_OVRD_IN 2 0xe060 4 0 4294967295 LANE_MPLLA_EN_IN 0 0 LANE_MPLLB_EN_IN 1 1 LANE_OVRD_EN 2 2 RESERVED_15_3 3 15 ixDPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_LANE_OVRD_OUT 2 0xe061 4 0 4294967295 LANE_MPLLA_EN_OUT 0 0 LANE_MPLLB_EN_OUT 1 1 LANE_OVRD_EN 2 2 RESERVED_15_3 3 15 ixDPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_SUP_OVRD_IN 2 0xe062 4 0 4294967295 MPLLA_STATE 0 0 MPLLB_STATE 1 1 SUP_STATE_OVRD_EN 2 2 RESERVED_15_3 3 15 ixDPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_SUP_PMA_IN 2 0xe063 3 0 4294967295 MPLLA_STATE 0 0 MPLLB_STATE 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT 2 0xe064 16 0 4294967295 TX_REQ_OVRD_VAL 0 0 TX_REQ_OVRD_EN 1 1 TX_RESET_OVRD_VAL 2 2 TX_RESET_OVRD_EN 3 3 TX_BEACON_EN_OVRD_VAL 4 4 TX_BEACON_EN_OVRD_EN 5 5 TX_ASYNC_DRV_EN_OVRD_VAL 6 6 TX_ASYNC_DRV_EN_OVRD_EN 7 7 TX_ASYNC_EN_OVRD_VAL 8 8 TX_ASYNC_EN_OVRD_EN 9 9 TX_DWORD_CLK_SYNC_OVRD_VAL 10 10 TX_DWORD_CLK_SYNC_OVRD_EN 11 11 LANE_TX2RX_SER_LB_EN_OVRD_VAL 12 12 LANE_TX2RX_SER_LB_EN_OVRD_EN 13 13 TX_PMA_DATA_EN_OVRD_VAL_R 14 14 TX_PMA_DATA_EN_OVRD_EN_R 15 15 ixDPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_TX_PMA_IN 2 0xe065 2 0 4294967295 ACK 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT 2 0xe066 9 0 4294967295 RX_REQ_OVRD_VAL 0 0 RX_REQ_OVRD_EN 1 1 RX_RESET_OVRD_VAL 2 2 RX_RESET_OVRD_EN 3 3 LANE_RX2TX_PAR_LB_EN_OVRD_VAL 4 4 LANE_RX2TX_PAR_LB_EN_OVRD_EN 5 5 RX_PMA_DATA_EN_OVRD_VAL_R 6 6 RX_PMA_DATA_EN_OVRD_EN_R 7 7 RESERVED_15_8 8 15 ixDPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_RX_PMA_IN 2 0xe067 2 0 4294967295 ACK 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_LANE_RTUNE_CTL 2 0xe068 2 0 4294967295 LANE_RTUNE_REQ 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_SUP_PMA_IN_1 2 0xe069 2 0 4294967295 RTUNE_ACK 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_IN 2 0xe06a 9 0 4294967295 RX_PMA_PWM_WORD_CLK_R 0 0 RX_PMA_PWM_WORD_CLK_OVRD_EN 1 1 RX_PMA_PWM_DATA_R 2 2 RX_PMA_PWM_DATA_OVRD_EN 3 3 RX_PMA_PWM_CLK_R 4 4 RX_PMA_PWM_CLK_OVRD_EN 5 5 RX_PMA_TERM_CTL_R 6 7 RX_PMA_TERM_CTL_OVRD_EN 8 8 RESERVED_15_9 9 15 ixDPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_OUT 2 0xe06b 7 0 4294967295 RX_PMA_PWM_EN 0 0 RX_PMA_PWM_EN_OVRD_EN 1 1 RX_PMA_PWM_CLK_SEL 2 3 RX_PMA_PWM_CLK_SEL_OVRD_EN 4 4 RX_PMA_ASYNC_EN 5 5 RX_PMA_ASYNC_EN_OVRD_EN 6 6 RESERVED_15_7 7 15 ixDPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_RX_ADAPT_OVRD_OUT 2 0xe06c 3 0 4294967295 RX_PMA_IQ_PHASE_ADJUST_MAP_OVRD_VAL 0 6 RX_PMA_IQ_PHASE_ADJUST_MAP_OVRD_EN 7 7 RESERVED_15_8 8 15 ixDPCSSYS_CR3_RAWLANEX_DIG_TX_CTL_TX_FSM_CTL 2 0xe080 6 0 4294967295 TX_WAIT_MPLL_OFF_TIME 0 6 TX_P2_ALLOW_RXDET 7 7 TX_P1_ALLOW_RXDET 8 8 TX_P0S_ALLOW_RXDET 9 9 TX_P0_ALLOW_RXDET 10 10 RESERVED_15_11 11 15 ixDPCSSYS_CR3_RAWLANEX_DIG_TX_CTL_TX_CLK_CTL 2 0xe081 4 0 4294967295 TX_CLK_EN 0 0 TX_CLK_SEL 1 4 ASYNC_BEACON_WAIT_TIME 5 10 RESERVED_15_11 11 15 ixDPCSSYS_CR3_RAWLANEX_DIG_TX_CTL_TX_DCC_CONT_STATUS 2 0xe082 2 0 4294967295 ENABLE 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR3_RAWLANEX_DIG_TX_CTL_OCLA 2 0xe083 2 0 4294967295 FSM_EN 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR3_RAWLANEX_DIG_TX_CTL_UPCS_OCLA 2 0xe084 3 0 4294967295 DATA_EN 0 1 CLK_EN 2 2 RESERVED_15_3 3 15 ixDPCSSYS_CR3_RAWLANEX_DIG_RX_CTL_RX_FSM_CTL 2 0xe0a0 3 0 4294967295 EN_RX_CTL_FSM 0 0 RATE_CHG_IN_P1 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR3_RAWLANEX_DIG_RX_CTL_RX_LOS_MASK_CTL 2 0xe0a1 2 0 4294967295 RX_LOS_MASK_CNT 0 8 RESERVED_15_9 9 15 ixDPCSSYS_CR3_RAWLANEX_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL 2 0xe0a2 2 0 4294967295 RX_DATA_EN_OVRD_CNT 0 4 INT_REF_TRCK_CNT 5 15 ixDPCSSYS_CR3_RAWLANEX_DIG_RX_CTL_OFFCAN_CONT_STATUS 2 0xe0a3 2 0 4294967295 ENABLE 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR3_RAWLANEX_DIG_RX_CTL_ADAPT_CONT_STATUS 2 0xe0a4 2 0 4294967295 ENABLE 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR3_RAWLANEX_DIG_RX_CTL_UPCS_OCLA 2 0xe0a5 3 0 4294967295 DATA_EN 0 2 CLK_EN 3 3 RESERVED_15_4 4 15 ixDPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN 2 0xe0c0 11 0 4294967295 RATE_OVRD_VAL 0 1 RATE_OVRD_EN 2 2 WIDTH_OVRD_VAL 3 4 WIDTH_OVRD_EN 5 5 PSTATE_OVRD_VAL 6 7 PSTATE_OVRD_EN 8 8 LPD_OVRD_VAL 9 9 LPD_OVRD_EN 10 10 LANE_RX2TX_PAR_LB_EN_OVRD_VAL 11 11 LANE_RX2TX_PAR_LB_EN_OVRD_EN 12 12 RESERVED_15_13 13 15 ixDPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN 2 0xe0c1 12 0 4294967295 PSTATE 0 1 LPD 2 2 WIDTH 3 4 RATE 5 7 MPLLB_SEL 8 8 MPLL_EN 9 9 OVRD_EN 10 10 MSTR_MPLLA_STATE 11 11 MSTR_MPLLB_STATE 12 12 MSTR_MPLL_OVRD_EN 13 13 TX_ASYNC_EN_OVR_VAL 14 14 TX_ASYNC_EN_OVR_EN 15 15 ixDPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1 2 0xe0c2 13 0 4294967295 DETRX_REQ_OVRD_VAL 0 0 DETRX_REQ_OVRD_EN 1 1 VBOOST_EN_OVRD_VAL 2 2 VBOOST_EN_OVRD_EN 3 3 IBOOST_LVL_OVRD_VAL 4 7 IBOOST_LVL_OVRD_EN 8 8 TX_BEACON_EN_OVR_VAL 9 9 TX_BEACON_EN_OVR_EN 10 10 LANE_TX2RX_SER_LB_EN_OVRD_VAL 11 11 LANE_TX2RX_SER_LB_EN_OVRD_EN 12 12 TX_ASYNC_DATA_OVRD_VAL 13 13 TX_ASYNC_DATA_OVRD_EN 14 14 RESERVED_15_15 15 15 ixDPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_MASTER_MPLL_LOOP 2 0xe0c3 3 0 4294967295 MPLLB_LOOP_EN 0 0 MPLLA_LOOP_EN 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1 2 0xe0c4 11 0 4294967295 RESERVED 0 1 RX_LOS_LFPS_EN_OVRD_VAL 2 2 RX_LOS_LFPS_EN_OVRD_EN 3 3 RX_LOS_THRSHLD_OVRD_VAL 4 6 RX_LOS_THRSHLD_OVRD_EN 7 7 ADAPT_REQ 8 8 ADAPT_REQ_OVRD_EN 9 9 ADAPT_CONT 10 10 OFFCAN_CONT 11 11 CONT_OVRD_EN 12 12 RESERVED_15_13 13 15 ixDPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_2 2 0xe0c5 4 0 4294967295 VCO_LD_VAL_OVRD 0 12 VCO_LD_VAL_OVRD_EN 13 13 VCO_LOWFREQ_VAL_OVRD 14 14 VCO_LOWFREQ_VAL_OVRD_EN 15 15 ixDPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_3 2 0xe0c6 3 0 4294967295 REF_LD_VAL_OVRD 0 6 REF_LD_VAL_OVRD_EN 7 7 RESERVED_15_8 8 15 ixDPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT_2 2 0xe0c7 3 0 4294967295 RX_VALID 0 0 RX_VALID_OVRD_EN 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_2 2 0xe0c8 7 0 4294967295 LANE_TX2RX_SER_LB_EN_OVRD_VAL 0 0 LANE_TX2RX_SER_LB_EN_OVRD_EN 1 1 TX_DATA_EN_OVRD_VAL_R 2 2 TX_DATA_EN_OVRD_EN_R 3 3 TX_ASYNC_DATA_OVRD_VAL_R 4 4 TX_ASYNC_DATA_OVRD_EN_R 5 5 RESERVED_15_6 6 15 ixDPCSSYS_CR4_SUP_DIG_IDCODE_LO 2 0x0 1 0 4294967295 DATA 0 0 ixDPCSSYS_CR4_SUP_DIG_IDCODE_HI 2 0x1 1 0 4294967295 DATA 0 0 ixDPCSSYS_CR4_SUP_DIG_REFCLK_OVRD_IN 2 0x2 12 0 4294967295 REF_CLK_EN 0 0 REF_CLK_EN_OVRD_EN 1 1 REF_USE_PAD 2 2 REF_USE_PAD_OVRD_EN 3 3 REF_CLK_RANGE 4 8 REF_CLK_RANGE_OVRD_EN 9 9 BG_EN 10 10 BG_EN_OVRD_EN 11 11 HDMIMODE_EN 12 12 HDMIMODE_ENABLE_OVRD_EN 13 13 SUP_PRE_HP_OVRD 14 14 SUP_PRE_HP_OVRD_EN 15 15 ixDPCSSYS_CR4_SUP_DIG_MPLLA_DIV_CLK_OVRD_IN 2 0x3 4 0 4294967295 MPLLA_DIV_CLK_EN 0 0 MPLLA_DIV_MULTIPLIER 1 8 MPLLA_DIV_OVRD_EN 9 9 RESERVED_15_10 10 15 ixDPCSSYS_CR4_SUP_DIG_MPLLA_HDMI_CLK_OVRD_IN 2 0x4 4 0 4294967295 MPLLA_HDMI_PIXEL_CLK_DIV 0 1 MPLLA_HDMI_DIV 2 4 MPLLA_HDMI_OVRD_EN 5 5 RESERVED_15_6 6 15 ixDPCSSYS_CR4_SUP_DIG_MPLLB_DIV_CLK_OVRD_IN 2 0x5 4 0 4294967295 MPLLB_DIV_CLK_EN 0 0 MPLLB_DIV_MULTIPLIER 1 8 MPLLB_DIV_OVRD_EN 9 9 RESERVED_15_10 10 15 ixDPCSSYS_CR4_SUP_DIG_MPLLB_HDMI_CLK_OVRD_IN 2 0x6 4 0 4294967295 MPLLB_HDMI_PIXEL_CLK_DIV 0 1 MPLLB_HDMI_DIV 2 4 MPLLB_HDMI_OVRD_EN 5 5 RESERVED_15_6 6 15 ixDPCSSYS_CR4_SUP_DIG_MPLLA_OVRD_IN_0 2 0x7 12 0 4294967295 MPLLA_EN 0 0 MPLLA_DIV5_CLK_EN 1 1 MPLLA_TX_CLK_DIV 2 4 OVRD_EN 5 5 MPLLA_V2I 6 7 MPLLA_STANDBY 8 8 MPLLA_FREQ_VCO 9 10 MPLLA_CAL_FORCE 11 11 MPLL_FRACN_EN 12 12 MPLLA_CLK_SYNC_OVRD 13 13 MPLLA_CLK_SYNC_OVRD_EN 14 14 RESERVED_15_15 15 15 ixDPCSSYS_CR4_SUP_DIG_MPLLA_OVRD_IN_1 2 0x8 2 0 4294967295 MPLLA_MULTIPLIER 0 11 RESERVED_15_12 12 15 ixDPCSSYS_CR4_SUP_DIG_MPLLA_OVRD_IN_2 2 0x9 7 0 4294967295 MPLLA_SSC_EN 0 0 MPLLA_SSC_OVRD_EN 1 1 MPLLA_SSC_UP_SPREAD 2 2 MPLLA_PMIX_EN 3 3 MPLLA_WORD_DIV2_EN 4 4 MPLLA_FRACN_CFG_UPDATE_EN 5 5 RESERVED_15_6 6 15 ixDPCSSYS_CR4_SUP_DIG_MPLLA_SSC_PEAK_1 2 0xa 1 0 4294967295 MPLLA_SSC_PEAK_15_0 0 15 ixDPCSSYS_CR4_SUP_DIG_MPLLA_SSC_PEAK_2 2 0xb 2 0 4294967295 MPLLA_SSC_PEAK_19_16 0 3 RESERVED_15_4 4 15 ixDPCSSYS_CR4_SUP_DIG_MPLLA_SSC_STEPSIZE_1 2 0xc 1 0 4294967295 MPLLA_SSC_STEPSIZE_15_0 0 15 ixDPCSSYS_CR4_SUP_DIG_MPLLA_SSC_STEPSIZE_2 2 0xd 2 0 4294967295 MPLLA_SSC_STEPSIZE_20_16 0 4 RESERVED_15_5 5 15 ixDPCSSYS_CR4_SUP_DIG_MPLLA_OVRD_IN_3 2 0xe 1 0 4294967295 MPLLA_FRACN_QUOT 0 15 ixDPCSSYS_CR4_SUP_DIG_MPLLA_OVRD_IN_4 2 0xf 1 0 4294967295 MPLLA_FRACN_REM 0 15 ixDPCSSYS_CR4_SUP_DIG_MPLLA_OVRD_IN_5 2 0x10 1 0 4294967295 MPLLA_FRACN_DEN 0 15 ixDPCSSYS_CR4_SUP_DIG_MPLLA_CP_OVRD_IN 2 0x11 3 0 4294967295 MPLLA_CP_PROP 0 6 MPLLA_CP_INT 7 13 RESERVED_15_14 14 15 ixDPCSSYS_CR4_SUP_DIG_MPLLA_CP_GS_OVRD_IN 2 0x12 4 0 4294967295 MPLLA_CP_PROP_GS 0 6 MPLLA_CP_PROP_GS_OVR_EN 7 7 MPLLA_CP_INT_GS 8 14 MPLLA_CP_INT_GS_OVR_EN 15 15 ixDPCSSYS_CR4_SUP_DIG_MPLLB_OVRD_IN_0 2 0x13 12 0 4294967295 MPLLB_EN 0 0 MPLLB_DIV5_CLK_EN 1 1 MPLLB_TX_CLK_DIV 2 4 OVRD_EN 5 5 MPLLB_V2I 6 7 MPLLB_STANDBY 8 8 MPLLB_FREQ_VCO 9 10 MPLLB_CAL_FORCE 11 11 MPLL_FRACN_EN 12 12 MPLLB_CLK_SYNC_OVRD 13 13 MPLLB_CLK_SYNC_OVRD_EN 14 14 RESERVED_15_15 15 15 ixDPCSSYS_CR4_SUP_DIG_MPLLB_OVRD_IN_1 2 0x14 2 0 4294967295 MPLLB_MULTIPLIER 0 11 RESERVED_15_12 12 15 ixDPCSSYS_CR4_SUP_DIG_MPLLB_OVRD_IN_2 2 0x15 7 0 4294967295 MPLLB_SSC_EN 0 0 MPLLB_SSC_OVRD_EN 1 1 MPLLB_SSC_UP_SPREAD 2 2 MPLLB_PMIX_EN 3 3 MPLLB_WORD_DIV2_EN 4 4 MPLLB_FRACN_CFG_UPDATE_EN 5 5 RESERVED_15_6 6 15 ixDPCSSYS_CR4_SUP_DIG_MPLLB_SSC_PEAK_1 2 0x16 1 0 4294967295 MPLLB_SSC_PEAK_15_0 0 15 ixDPCSSYS_CR4_SUP_DIG_MPLLB_SSC_PEAK_2 2 0x17 2 0 4294967295 MPLLB_SSC_PEAK_19_16 0 3 RESERVED_15_4 4 15 ixDPCSSYS_CR4_SUP_DIG_MPLLB_SSC_STEPSIZE_1 2 0x18 1 0 4294967295 MPLLB_SSC_STEPSIZE_15_0 0 15 ixDPCSSYS_CR4_SUP_DIG_MPLLB_SSC_STEPSIZE_2 2 0x19 2 0 4294967295 MPLLB_SSC_STEPSIZE_20_16 0 4 RESERVED_15_5 5 15 ixDPCSSYS_CR4_SUP_DIG_MPLLB_OVRD_IN_3 2 0x1a 1 0 4294967295 MPLLB_FRACN_QUOT 0 15 ixDPCSSYS_CR4_SUP_DIG_MPLLB_OVRD_IN_4 2 0x1b 1 0 4294967295 MPLLB_FRACN_REM 0 15 ixDPCSSYS_CR4_SUP_DIG_MPLLB_OVRD_IN_5 2 0x1c 1 0 4294967295 MPLLB_FRACN_DEN 0 15 ixDPCSSYS_CR4_SUP_DIG_MPLLB_CP_OVRD_IN 2 0x1d 3 0 4294967295 MPLLB_CP_PROP 0 6 MPLLB_CP_INT 7 13 RESERVED_15_14 14 15 ixDPCSSYS_CR4_SUP_DIG_MPLLB_CP_GS_OVRD_IN 2 0x1e 4 0 4294967295 MPLLB_CP_PROP_GS 0 6 MPLLB_CP_PROP_GS_OVR_EN 7 7 MPLLB_CP_INT_GS 8 14 MPLLB_CP_INT_GS_OVR_EN 15 15 ixDPCSSYS_CR4_SUP_DIG_SUP_OVRD_IN 2 0x1f 8 0 4294967295 PRESCALER_OVRD_EN 0 0 RTUNE_REQ 1 1 RTUNE_OVRD_EN 2 2 TX_CAL_CODE 3 6 TX_CAL_CODE_EN 7 7 REF_ALT_CLK_LP_SEL_OVRD 8 8 REF_ALT_CLK_LP_SEL_OVRD_EN 9 9 RESERVED_15_10 10 15 ixDPCSSYS_CR4_SUP_DIG_PRESCALER_OVRD_IN 2 0x20 6 0 4294967295 DCO_RANGE 0 1 DCO_FINETUNE 2 7 REF_CLK_MPLLB_DIV 8 10 REF_CLK_MPLLA_DIV 11 13 REF_CLKDET_RESULT 14 14 REF_CLKDET_EN 15 15 ixDPCSSYS_CR4_SUP_DIG_SUP_OVRD_OUT 2 0x21 12 0 4294967295 RTUNE_ACK 0 0 RTUNE_ACK_OVRD_EN 1 1 MPLLA_STATE 2 2 MPLLA_STATE_OVRD_EN 3 3 MPLLB_STATE 4 4 MPLLB_STATE_OVRD_EN 5 5 BG_LANE_STATE 6 6 BG_LANE_STATE_OVRD_EN 7 7 BG_SUP_STATE 8 8 BG_SUP_STATE_OVRD_EN 9 9 REF_CLK_ACK 10 10 RESERVED_15_11 11 15 ixDPCSSYS_CR4_SUP_DIG_LVL_OVRD_IN 2 0x22 7 0 4294967295 RX_VREF_CTRL 0 2 RX_VREF_CTRL_EN 3 3 TX_VBOOST_LVL 4 6 TX_VBOOST_LVL_EN 7 7 SUP_RX_VCO_VREF_SEL_OVR 8 10 SUP_RX_VCO_VREF_SEL_OVR_EN 11 11 RESERVED_15_12 12 15 ixDPCSSYS_CR4_SUP_DIG_MPLLA_ASIC_IN_0 2 0x24 9 0 4294967295 MPLLA_EN 0 0 MPLLA_DIV5_CLK_EN 1 1 MPLLA_TX_CLK_DIV 2 4 MPLLA_V2I 5 6 MPLLA_STANDBY 7 7 MPLLA_FREQ_VCO 8 9 MPLLA_CAL_FORCE 10 10 MPLLA_FRACN_EN 11 11 RESERVED_15_12 12 15 ixDPCSSYS_CR4_SUP_DIG_MPLLA_ASIC_IN_1 2 0x25 2 0 4294967295 MPLLA_MULTIPLIER 0 11 RESERVED_15_12 12 15 ixDPCSSYS_CR4_SUP_DIG_MPLLA_ASIC_IN_2 2 0x26 7 0 4294967295 MPLLA_SSC_EN 0 0 MPLLA_SSC_UP_SPREAD 1 1 MPLLA_PMIX_EN 2 2 MPLLA_WORD_DIV2_EN 3 3 MPLLA_FRACN_CFG_UPDATE_EN 4 4 MPLLA_CLK_SYNC 5 5 RESERVED_15_6 6 15 ixDPCSSYS_CR4_SUP_DIG_MPLLA_ASIC_IN_3 2 0x27 1 0 4294967295 MPLLA_SSC_PEAK_15_0 0 15 ixDPCSSYS_CR4_SUP_DIG_MPLLA_ASIC_IN_4 2 0x28 2 0 4294967295 MPLLA_SSC_PEAK_19_16 0 3 RESERVED_15_4 4 15 ixDPCSSYS_CR4_SUP_DIG_MPLLA_ASIC_IN_5 2 0x29 1 0 4294967295 MPLLA_SSC_STEPSIZE_15_0 0 15 ixDPCSSYS_CR4_SUP_DIG_MPLLA_ASIC_IN_6 2 0x2a 2 0 4294967295 MPLLA_SSC_STEPSIZE_20_16 0 3 RESERVED_15_4 4 15 ixDPCSSYS_CR4_SUP_DIG_MPLLB_ASIC_IN_0 2 0x2b 9 0 4294967295 MPLLB_EN 0 0 MPLLB_DIV5_CLK_EN 1 1 MPLLB_TX_CLK_DIV 2 4 MPLLB_V2I 5 6 MPLLB_STANDBY 7 7 MPLLB_FREQ_VCO 8 9 MPLLB_CAL_FORCE 10 10 MPLLB_FRACN_EN 11 11 RESERVED_15_12 12 15 ixDPCSSYS_CR4_SUP_DIG_MPLLB_ASIC_IN_1 2 0x2c 2 0 4294967295 MPLLB_MULTIPLIER 0 11 RESERVED_15_12 12 15 ixDPCSSYS_CR4_SUP_DIG_MPLLB_ASIC_IN_2 2 0x2d 7 0 4294967295 MPLLB_SSC_EN 0 0 MPLLB_SSC_UP_SPREAD 1 1 MPLLB_PMIX_EN 2 2 MPLLB_WORD_DIV2_EN 3 3 MPLLB_FRACN_CFG_UPDATE_EN 4 4 MPLLB_CLK_SYNC 5 5 RESERVED_15_6 6 15 ixDPCSSYS_CR4_SUP_DIG_MPLLB_ASIC_IN_3 2 0x2e 1 0 4294967295 MPLLB_SSC_PEAK_15_0 0 15 ixDPCSSYS_CR4_SUP_DIG_MPLLB_ASIC_IN_4 2 0x2f 2 0 4294967295 MPLLB_SSC_PEAK_19_16 0 3 RESERVED_15_4 4 15 ixDPCSSYS_CR4_SUP_DIG_MPLLB_ASIC_IN_5 2 0x30 1 0 4294967295 MPLLB_SSC_STEPSIZE_15_0 0 15 ixDPCSSYS_CR4_SUP_DIG_MPLLB_ASIC_IN_6 2 0x31 2 0 4294967295 MPLLB_SSC_STEPSIZE_20_16 0 3 RESERVED_15_4 4 15 ixDPCSSYS_CR4_SUP_DIG_MPLLA_DIV_CLK_ASIC_IN 2 0x32 3 0 4294967295 MPLLA_DIV_CLK_EN 0 0 MPLLA_DIV_MULTIPLIER 1 8 RESERVED_15_9 9 15 ixDPCSSYS_CR4_SUP_DIG_MPLLA_HDMI_CLK_ASIC_IN 2 0x33 3 0 4294967295 MPLLA_HDMI_PIXEL_CLK_DIV 0 1 MPLLA_HDMI_DIV 2 4 RESERVED_15_5 5 15 ixDPCSSYS_CR4_SUP_DIG_MPLLB_DIV_CLK_ASIC_IN 2 0x34 3 0 4294967295 MPLLB_DIV_CLK_EN 0 0 MPLLB_DIV_MULTIPLIER 1 8 RESERVED_15_9 9 15 ixDPCSSYS_CR4_SUP_DIG_MPLLB_HDMI_CLK_ASIC_IN 2 0x35 3 0 4294967295 MPLLB_HDMI_PIXEL_CLK_DIV 0 1 MPLLB_HDMI_DIV 2 4 RESERVED_15_5 5 15 ixDPCSSYS_CR4_SUP_DIG_ASIC_IN 2 0x36 12 0 4294967295 PHY_RESET 0 0 REF_CLK_EN 1 1 REF_USE_PAD 2 2 TEST_BURNIN 3 3 TEST_POWERDOWN 4 4 RTUNE_REQ 5 5 RTUNE_ACK 6 6 MPLLA_STATE 7 7 MPLLB_STATE 8 8 TEST_TX_REF_CLK_EN 9 9 REF_ALT_CLK_LP_SEL 10 10 RESERVED_15_11 11 15 ixDPCSSYS_CR4_SUP_DIG_LVL_ASIC_IN 2 0x37 4 0 4294967295 RX_VREF_CTRL 0 2 TX_VBOOST_LVL 3 5 SUP_RX_VCO_VREF_SEL 6 8 RESERVED_15_9 9 15 ixDPCSSYS_CR4_SUP_DIG_BANDGAP_ASIC_IN 2 0x38 2 0 4294967295 BG_EN 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR4_SUP_DIG_MPLLA_CP_ASIC_IN 2 0x39 3 0 4294967295 MPLLA_CP_PROP 0 6 MPLLA_CP_INT 7 13 RESERVED_15_14 14 15 ixDPCSSYS_CR4_SUP_DIG_MPLLA_CP_GS_ASIC_IN 2 0x3a 3 0 4294967295 MPLLA_CP_PROP_GS 0 6 MPLLA_CP_INT_GS 7 13 RESERVED_15_14 14 15 ixDPCSSYS_CR4_SUP_DIG_MPLLB_CP_ASIC_IN 2 0x3b 3 0 4294967295 MPLLB_CP_PROP 0 6 MPLLB_CP_INT 7 13 RESERVED_15_14 14 15 ixDPCSSYS_CR4_SUP_DIG_MPLLB_CP_GS_ASIC_IN 2 0x3c 3 0 4294967295 MPLLB_CP_PROP_GS 0 6 MPLLB_CP_INT_GS 7 13 RESERVED_15_14 14 15 ixDPCSSYS_CR4_SUP_ANA_PRESCALER_CTRL 2 0x40 7 0 4294967295 PSCALER_ATB_SELECT 0 0 PSCALER_MEAS_VREG 0 0 PSCALER_OVRD_FAST_START 0 0 PSCALER_FAST_START_REG 0 0 PSCALER_VREG_BOOST 0 0 PSCALER_HYST_REF 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR4_SUP_ANA_RTUNE_CTRL 2 0x41 9 0 4294967295 RT_ATB 0 0 RT_SEL_ATBF 0 0 RT_SEL_ATBP 0 0 RT_VP4O8_EN 0 0 RT_DAC_CHOP 0 0 RT_DAC_MODE 0 0 RT_EN_FRCON 0 0 PSCALER_VREG_FB_DIV_CTRL 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR4_SUP_ANA_BG1 2 0x42 6 0 4294967295 SUP_SEL_VBG_VREF 0 0 SUP_SEL_VPHUD_VREF 0 0 NC4 4 4 SUP_SEL_VPLL_REF 0 0 RT_VREF_SEL 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR4_SUP_ANA_BG2 2 0x43 9 0 4294967295 SUP_BYPASS_BG 0 0 SUP_CHOP_EN 0 0 SUP_TEMP_MEAS 0 0 VPHUD_SELREF 0 0 ATB_EXT_MEAS_EN 0 0 RT_TX_OFFSET_EN 0 0 SUP_SEL_TX_SWING_VREF 0 0 PSCALER_VREG_OVERRIDE_RING_CTRL 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR4_SUP_ANA_SWITCH_PWR_MEAS 2 0x44 3 0 4294967295 SUP_ATB_SW 0 0 SUP_TIE 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR4_SUP_ANA_BG3 2 0x45 4 0 4294967295 SUP_SEL_RX_VCO_TC_VREF 0 0 SUP_SEL_RX_CAL_VREF 0 0 NC7_4 4 7 RESERVED_15_8 8 15 ixDPCSSYS_CR4_SUP_ANA_MPLLA_MISC1 2 0x46 7 0 4294967295 OVRD_GEAR_RC_FILT 0 0 OVRD_TEST_RC_FILT 0 0 TEST_VREG_DIV 0 0 VBG_EN 0 0 COUNT_SEL_LOCK 0 0 PHASE_SEL_LOCK 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR4_SUP_ANA_MPLLA_MISC2 2 0x47 8 0 4294967295 OVRD_PR_BYPASS 0 0 PR_BYPASS 0 0 OVRD_GEARSHIFT 0 0 GEARSHIFT_REG 0 0 TEST_LOCK_GEAR 0 0 EN_CAL_SPO 0 0 TEST_BOOST 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR4_SUP_ANA_MPLLA_OVRD 2 0x48 9 0 4294967295 OVRD_ENABLE 0 0 ENABLE_REG 0 0 OVRD_CAL 0 0 CAL_REG 0 0 OVRD_FB_CLK_EN 0 0 FB_CLK_EN_REG 0 0 OVRD_RESET 0 0 RESET_REG 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR4_SUP_ANA_MPLLA_ATB1 2 0x49 3 0 4294967295 MEAS_IV_WRAP 0 0 ATB_SELECT 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR4_SUP_ANA_MPLLA_ATB2 2 0x4a 2 0 4294967295 MEAS_IV_PLL 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR4_SUP_ANA_MPLLA_ATB3 2 0x4b 3 0 4294967295 MEAS_IV_BIAS 0 0 CTR_UPLL_TUNNING 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR4_SUP_ANA_MPLLA_CTR1 2 0x4c 5 0 4294967295 CTR_ICP_INT 0 0 CTR_VREF_EN 0 0 CTR_VREF_VMARG 0 0 CTR_CP_PLL 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR4_SUP_ANA_MPLLA_CTR2 2 0x4d 2 0 4294967295 CTR_REGS_PLL 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR4_SUP_ANA_MPLLA_CTR3 2 0x4e 4 0 4294967295 CTR_REGS_CP_PLL 0 0 CTR_SPO_PLL 0 0 CTR_VINT_CAP 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR4_SUP_ANA_MPLLA_CTR4 2 0x4f 7 0 4294967295 CTR_CP_8X 0 0 CTR_FIL_REG 0 0 CTR_CP_PROP_REF 0 0 CTR_DOUBLER_GAIN 0 0 CTR_TEST_CASC 0 0 CTR_RC_FITER 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR4_SUP_ANA_MPLLA_CTR5 2 0x50 8 0 4294967295 CTR_STANDBY_MODE 0 0 CTR_LEG_SR_CON 0 0 CTR_VREG_RING_OVERRIDE 0 0 CTR_SPO_SPEED_OVERRIDE 0 0 CTR_BYPASS_LOCK_SPO_CAL 0 0 CTR_LOCK_SPO_CAL 0 0 CTR_UPLL_RESERVED 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR4_SUP_ANA_MPLLA_RESERVED1 2 0x51 8 0 4294967295 CTR_REF_FBK_BYPASS 0 0 CTR_BYPASS_TX 0 0 CTR_VREG_CLK_BYPASS 0 0 CTR_VREG_CLK_PMIX_BYPASS 0 0 CTR_VREG_RIGHT_BYPASS 0 0 CTR_VREG_LEFT_BYPASS 0 0 CTR_LEFT_RIGHT_GAIN 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR4_SUP_ANA_MPLLA_RESERVED2 2 0x52 5 0 4294967295 CTR_DLL_MODE_90 0 0 CTR_DLL_RESERVED 0 0 CTR_DIV24_DSQ_ENZ 0 0 CTR_DIV4 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR4_SUP_ANA_MPLLB_MISC1 2 0x53 7 0 4294967295 OVRD_GEAR_RC_FILT 0 0 OVRD_TEST_RC_FILT 0 0 TEST_VREG_DIV 0 0 VBG_EN 0 0 COUNT_SEL_LOCK 0 0 PHASE_SEL_LOCK 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR4_SUP_ANA_MPLLB_MISC2 2 0x54 8 0 4294967295 OVRD_PR_BYPASS 0 0 PR_BYPASS 0 0 OVRD_GEARSHIFT 0 0 GEARSHIFT_REG 0 0 TEST_LOCK_GEAR 0 0 EN_CAL_SPO 0 0 TEST_BOOST 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR4_SUP_ANA_MPLLB_OVRD 2 0x55 9 0 4294967295 OVRD_ENABLE 0 0 ENABLE_REG 0 0 OVRD_CAL 0 0 CAL_REG 0 0 OVRD_FB_CLK_EN 0 0 FB_CLK_EN_REG 0 0 OVRD_RESET 0 0 RESET_REG 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR4_SUP_ANA_MPLLB_ATB1 2 0x56 3 0 4294967295 MEAS_IV_WRAP 0 0 ATB_SELECT 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR4_SUP_ANA_MPLLB_ATB2 2 0x57 2 0 4294967295 MEAS_IV_PLL 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR4_SUP_ANA_MPLLB_ATB3 2 0x58 3 0 4294967295 MEAS_IV_BIAS 0 0 CTR_UPLL_TUNNING 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR4_SUP_ANA_MPLLB_CTR1 2 0x59 5 0 4294967295 CTR_ICP_INT 0 0 CTR_VREF_EN 0 0 CTR_VREF_VMARG 0 0 CTR_CP_PLL 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR4_SUP_ANA_MPLLB_CTR2 2 0x5a 2 0 4294967295 CTR_REGS_PLL 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR4_SUP_ANA_MPLLB_CTR3 2 0x5b 4 0 4294967295 CTR_REGS_CP_PLL 0 0 CTR_SPO_PLL 0 0 CTR_VINT_CAP 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR4_SUP_ANA_MPLLB_CTR4 2 0x5c 7 0 4294967295 CTR_CP_8X 0 0 CTR_FIL_REG 0 0 CTR_CP_PROP_REF 0 0 CTR_DOUBLER_GAIN 0 0 CTR_TEST_CASC 0 0 CTR_RC_FITER 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR4_SUP_ANA_MPLLB_CTR5 2 0x5d 8 0 4294967295 CTR_STANDBY_MODE 0 0 CTR_LEG_SR_CON 0 0 CTR_VREG_RING_OVERRIDE 0 0 CTR_SPO_SPEED_OVERRIDE 0 0 CTR_BYPASS_LOCK_SPO_CAL 0 0 CTR_LOCK_SPO_CAL 0 0 CTR_UPLL_RESERVED 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR4_SUP_ANA_MPLLB_RESERVED1 2 0x5e 8 0 4294967295 CTR_REF_FBK_BYPASS 0 0 CTR_BYPASS_TX 0 0 CTR_VREG_CLK_BYPASS 0 0 CTR_VREG_CLK_PMIX_BYPASS 0 0 CTR_VREG_RIGHT_BYPASS 0 0 CTR_VREG_LEFT_BYPASS 0 0 CTR_LEFT_RIGHT_GAIN 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR4_SUP_ANA_MPLLB_RESERVED2 2 0x5f 5 0 4294967295 CTR_DLL_MODE_90 0 0 CTR_DLL_RESERVED 0 0 CTR_DIV24_DSQ_ENZ 0 0 CTR_DIV4 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD 2 0x61 8 0 4294967295 OVRD_SEL 0 0 MPLL_FBDIGCLK_EN 1 1 MPLL_PCLK_EN 2 2 FAST_MPLL_PWRUP 3 3 FAST_MPLL_LOCK 4 4 DTB_SEL 5 9 DIV10_EN 10 10 RESERVED 11 15 ixDPCSSYS_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT 2 0x62 11 0 4294967295 FSM_STATE 0 3 MPLL_R_LANES 4 4 MPLL_L_LANES 5 5 MPLL_PCLK_EN 6 6 MPLL_OUTPUT_EN 7 7 MPLL_FBCLK_EN 8 8 MPLL_CAL 9 9 MPLL_RST 10 10 MPLL_ANA_EN 11 11 MPLL_LOCK 12 12 RESERVED_15_13 13 15 ixDPCSSYS_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE 2 0x63 3 0 4294967295 MAX_RANGE 0 4 DAC_IN 5 9 RESERVED_15_10 10 15 ixDPCSSYS_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_LOCK 2 0x64 3 0 4294967295 LOCK_TIME 0 7 STABLE_TIME 8 13 RESERVED_15_14 14 15 ixDPCSSYS_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS 2 0x65 2 0 4294967295 GEARSHIFT_TIME 0 7 PRESET_TIME 8 15 ixDPCSSYS_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE 2 0x66 3 0 4294967295 PWRDN_WAIT_TIME 0 5 PCLK_EN_TIME 6 11 RESERVED_15_12 12 15 ixDPCSSYS_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2 2 0x67 3 0 4294967295 PCLK_DIS_TIME 0 5 PWRDN_TIME 6 11 RESERVED_15_12 12 15 ixDPCSSYS_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_CAL 2 0x68 3 0 4294967295 MPLL_CAL 0 0 MPLL_CAL_OVRD_EN 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT 2 0x69 2 0 4294967295 MPLL_ANA_DAC_OUT 0 4 RESERVED_15_5 5 15 ixDPCSSYS_CR4_SUP_DIG_MPLLA_SSC_GEN_SPREAD_TYPE 2 0x6b 3 0 4294967295 SPREAD_TYPE 0 1 OVR_EN 2 2 RESERVED_15_3 3 15 ixDPCSSYS_CR4_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD 2 0x6d 8 0 4294967295 OVRD_SEL 0 0 MPLL_FBDIGCLK_EN 1 1 MPLL_PCLK_EN 2 2 FAST_MPLL_PWRUP 3 3 FAST_MPLL_LOCK 4 4 DTB_SEL 5 9 DIV10_EN 10 10 RESERVED 11 15 ixDPCSSYS_CR4_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT 2 0x6e 11 0 4294967295 FSM_STATE 0 3 MPLL_R_LANES 4 4 MPLL_L_LANES 5 5 MPLL_PCLK_EN 6 6 MPLL_OUTPUT_EN 7 7 MPLL_FBCLK_EN 8 8 MPLL_CAL 9 9 MPLL_RST 10 10 MPLL_ANA_EN 11 11 MPLL_LOCK 12 12 RESERVED_15_13 13 15 ixDPCSSYS_CR4_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE 2 0x6f 3 0 4294967295 MAX_RANGE 0 4 DAC_IN 5 9 RESERVED_15_10 10 15 ixDPCSSYS_CR4_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_LOCK 2 0x70 3 0 4294967295 LOCK_TIME 0 7 STABLE_TIME 8 13 RESERVED_15_14 14 15 ixDPCSSYS_CR4_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS 2 0x71 2 0 4294967295 GEARSHIFT_TIME 0 7 PRESET_TIME 8 15 ixDPCSSYS_CR4_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE 2 0x72 3 0 4294967295 PWRDN_WAIT_TIME 0 5 PCLK_EN_TIME 6 11 RESERVED_15_12 12 15 ixDPCSSYS_CR4_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2 2 0x73 3 0 4294967295 PCLK_DIS_TIME 0 5 PWRDN_TIME 6 11 RESERVED_15_12 12 15 ixDPCSSYS_CR4_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_CAL 2 0x74 3 0 4294967295 MPLL_CAL 0 0 MPLL_CAL_OVRD_EN 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR4_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT 2 0x75 2 0 4294967295 MPLL_ANA_DAC_OUT 0 4 RESERVED_15_5 5 15 ixDPCSSYS_CR4_SUP_DIG_MPLLB_SSC_GEN_SPREAD_TYPE 2 0x77 3 0 4294967295 SPREAD_TYPE 0 1 OVR_EN 2 2 RESERVED_15_3 3 15 ixDPCSSYS_CR4_SUP_DIG_CLK_RST_BG_PWRUP_TIME_0 2 0x78 3 0 4294967295 BG_SUP_EN_TIME 0 8 FAST_BG_WAIT 9 9 RESERVED_15_10 10 15 ixDPCSSYS_CR4_SUP_DIG_CLK_RST_BG_PWRUP_TIME_1 2 0x79 2 0 4294967295 BG_LANE_EN_TIME 0 8 RESERVED_15_9 9 15 ixDPCSSYS_CR4_SUP_DIG_CLK_RST_BG_PWRUP_TIME_2 2 0x7a 3 0 4294967295 BG_KICK_START_EN_TIME 0 7 BG_SUP_STATE_UPD_EN 8 8 RESERVED_15_9 9 15 ixDPCSSYS_CR4_SUP_DIG_CLK_RST_REF_PWRUP_TIME_0 2 0x7b 3 0 4294967295 REF_VREG_FAST_START_TIME 0 4 FAST_REF_WAIT 5 5 RESERVED_15_6 6 15 ixDPCSSYS_CR4_SUP_DIG_CLK_RST_REF_VPHUD 2 0x7c 3 0 4294967295 SUP_ANA_VPHUD_SELVPH_I 0 0 SUP_ANA_VPHUD_EN_I 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR4_SUP_DIG_RTUNE_CONFIG 2 0x81 5 0 4294967295 RX_CAL_EN 0 0 FAST_RTUNE 1 1 TX_CAL_EN 2 2 SUP_ANA_TERM_CTRL 3 5 RESERVED_15_6 6 15 ixDPCSSYS_CR4_SUP_DIG_RTUNE_STAT 2 0x82 3 0 4294967295 STAT 0 9 DTB_RTUNE 10 11 RESERVED_15_12 12 15 ixDPCSSYS_CR4_SUP_DIG_RTUNE_RX_SET_VAL 2 0x83 2 0 4294967295 RX_SET_VAL 0 5 RESERVED_15_6 6 15 ixDPCSSYS_CR4_SUP_DIG_RTUNE_TXDN_SET_VAL 2 0x84 2 0 4294967295 TXDN_SET_VAL 0 9 RESERVED_15_10 10 15 ixDPCSSYS_CR4_SUP_DIG_RTUNE_TXUP_SET_VAL 2 0x85 2 0 4294967295 TXUP_SET_VAL 0 9 RESERVED_15_10 10 15 ixDPCSSYS_CR4_SUP_DIG_RTUNE_RX_STAT 2 0x86 2 0 4294967295 RX_STAT 0 5 RESERVED_15_6 6 15 ixDPCSSYS_CR4_SUP_DIG_RTUNE_TXDN_STAT 2 0x87 2 0 4294967295 TXDN_STAT 0 9 RESERVED_15_10 10 15 ixDPCSSYS_CR4_SUP_DIG_RTUNE_TXUP_STAT 2 0x88 2 0 4294967295 TXUP_STAT 0 9 RESERVED_15_10 10 15 ixDPCSSYS_CR4_SUP_DIG_RTUNE_CONFIG_CNT0 2 0x89 4 0 4294967295 RT_RESULT_TIME 0 3 RT_EVAL_TIME 4 7 RT_RST_TIME 8 11 RT_ACK_TIME 12 15 ixDPCSSYS_CR4_SUP_DIG_RTUNE_CONFIG_CNT1 2 0x8a 3 0 4294967295 RT_TXDN_SETTLE_TIME 0 3 RT_PWRUP_TIME 4 8 RESERVED_15_9 9 15 ixDPCSSYS_CR4_SUP_DIG_RTUNE_TX_CAL_CODE 2 0x8b 2 0 4294967295 VALUE 0 3 RESERVED_15_4 4 15 ixDPCSSYS_CR4_SUP_DIG_ANA_MPLLA_OVRD_OUT_0 2 0x8c 16 0 4294967295 MPLLA_WORD_CLK_EN 0 0 MPLLA_HDMI_CLK_EN 1 1 MPLLA_DIV_CLK_EN 2 2 MPLLA_OUTPUT_EN 3 3 MPLLA_CLK_EN_OVRD_EN 4 4 MPLLA_OUTPUT_L_EN 5 5 MPLLA_OUTPUT_R_EN 6 6 MPLLA_ANA_EN 7 7 MPLLA_RST 8 8 MPLLA_CAL 9 9 MPLLA_DIV5_CLK_EN 10 10 MPLLA_DIV10_CLK_EN 11 11 MPLLA_FBCLK_EN 12 12 MPLLA_GEARSHIFT_EN 13 13 MPLLA_STANDBY 14 14 OVRD_SEL 15 15 ixDPCSSYS_CR4_SUP_DIG_ANA_MPLLA_OVRD_OUT_1 2 0x8d 2 0 4294967295 MPLLA_ANA_INT 0 9 RESERVED_15_10 10 15 ixDPCSSYS_CR4_SUP_DIG_ANA_MPLLA_OVRD_OUT_2 2 0x8e 3 0 4294967295 MPLLA_CP_PROP 0 6 MPLLA_CP_INT 7 13 RESERVED_15_14 14 15 ixDPCSSYS_CR4_SUP_DIG_ANA_MPLLB_OVRD_OUT_0 2 0x8f 16 0 4294967295 MPLLB_WORD_CLK_EN 0 0 MPLLB_HDMI_CLK_EN 1 1 MPLLB_DIV_CLK_EN 2 2 MPLLB_OUTPUT_EN 3 3 MPLLB_CLK_EN_OVRD_EN 4 4 MPLLB_OUTPUT_L_EN 5 5 MPLLB_OUTPUT_R_EN 6 6 MPLLB_ANA_EN 7 7 MPLLB_RST 8 8 MPLLB_CAL 9 9 MPLLB_DIV5_CLK_EN 10 10 MPLLB_DIV10_CLK_EN 11 11 MPLLB_FBCLK_EN 12 12 MPLLB_GEARSHIFT_EN 13 13 MPLLB_STANDBY 14 14 OVRD_SEL 15 15 ixDPCSSYS_CR4_SUP_DIG_ANA_MPLLB_OVRD_OUT_1 2 0x90 2 0 4294967295 MPLLB_ANA_INT 0 9 RESERVED_15_10 10 15 ixDPCSSYS_CR4_SUP_DIG_ANA_MPLLB_OVRD_OUT_2 2 0x91 3 0 4294967295 MPLLB_CP_PROP 0 6 MPLLB_CP_INT 7 13 RESERVED_15_14 14 15 ixDPCSSYS_CR4_SUP_DIG_ANA_RTUNE_OVRD_OUT 2 0x92 6 0 4294967295 RTUNE_COMP_RST 0 0 RTUNE_MODE 1 2 RTUNE_EN 3 3 RTUNE_VALUE 4 13 RTUNE_OVRD_EN 14 14 RESERVED_15_15 15 15 ixDPCSSYS_CR4_SUP_DIG_ANA_STAT 2 0x93 3 0 4294967295 RT_ANA_COMP_RESULT 0 0 REF_ANA_CLKDET_RESULT 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR4_SUP_DIG_ANA_BG_OVRD_OUT 2 0x94 11 0 4294967295 BG_EN 0 0 BG_FAST_START 1 1 BG_KICK_START 2 2 BG_OVRD_EN 3 3 ANA_ASYNC_RST 4 4 ANA_ASYNC_RST_OVRD_EN 5 5 REF_VREG_FAST_START 6 6 REF_VREG_FAST_START_OVRD_EN 7 7 REF_VREG_REF_SEL 8 9 REF_VREG_REF_SEL_OVRD_EN 10 10 RESERVED_15_11 11 15 ixDPCSSYS_CR4_SUP_DIG_ANA_MPLLA_PMIX_OVRD_OUT 2 0x95 5 0 4294967295 MPLLA_PMIX_SEL 0 5 MPLLA_PMIX_EN 6 6 MPLLA_PMIX_SEL_OVRD_EN 7 7 MPLLA_PMIX_EN_OVRD_EN 8 8 RESERVED_15_9 9 15 ixDPCSSYS_CR4_SUP_DIG_ANA_MPLLB_PMIX_OVRD_OUT 2 0x96 5 0 4294967295 MPLLB_PMIX_SEL 0 5 MPLLB_PMIX_EN 6 6 MPLLB_PMIX_SEL_OVRD_EN 7 7 MPLLB_PMIX_EN_OVRD_EN 8 8 RESERVED_15_9 9 15 ixDPCSSYS_CR4_LANE0_DIG_ASIC_LANE_OVRD_IN 2 0x1000 5 0 4294967295 LANE_TX2RX_SER_LB 0 0 LANE_RX2TX_PAR_LB 1 1 EN 2 2 RX_ACJTAG_EN 3 3 RESERVED_15_4 4 15 ixDPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_0 2 0x1001 12 0 4294967295 REQ 0 0 REQ_OVRD_EN 1 1 PSTATE 2 3 PSTATE_OVRD_EN 4 4 RATE 5 7 RATE_OVRD_EN 8 8 WIDTH 9 10 WIDTH_OVRD_EN 11 11 MPLLB_SEL 12 12 MPLLB_SEL_OVRD_EN 13 13 DATA_EN 14 14 DATA_EN_OVRD_EN 15 15 ixDPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_1 2 0x1002 11 0 4294967295 NYQUIST_DATA 0 0 DISABLE 1 1 BEACON_EN 2 2 EN 3 3 TX_MAIN_CURSOR 4 9 MAIN_OVRD_EN 10 10 ASYNC_DRV_EN 11 11 ASYNC_DRV_OVRD_EN 12 12 TX_VREGDRV_BYP_OVRD 13 13 TX_VREGDRV_BYP_OVRD_EN 14 14 RESERVED_15_15 15 15 ixDPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_2 2 0x1003 6 0 4294967295 TX_PRE_CURSOR 0 5 PRE_OVRD_EN 6 6 TX_POST_CURSOR 7 12 POST_OVRD_EN 13 13 HDMIMODE_EN 14 14 HDMIMODE_ENABLE_OVRD_EN 15 15 ixDPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_3 2 0x1004 15 0 4294967295 CLK_RDY 0 0 CLK_RDY_OVRD_EN 1 1 DETECT_RX_REQ 2 2 DETECT_RX_REQ_OVRD_EN 3 3 INVERT 4 4 INVERT_OVRD_EN 5 5 LPD 6 6 LPD_OVRD_EN 7 7 TX_DC_COUP_EN 8 8 TX_DC_COUP_EN_OVRD_EN 9 9 PMA_EXTENDED_FIFO_EN 10 10 PMA_EXTENDED_FIFO_EN_OVRD_EN 11 11 TX_MPHY_MODE_EN 12 12 TX_MPHY_MODE_EN_OVRD_EN 13 13 RESERVED_15_14 14 15 ixDPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_4 2 0x1005 3 0 4294967295 RESET 0 0 RESET_OVRD_EN 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_OUT 2 0x1006 5 0 4294967295 TX_ACK 0 0 EN_TX_ACK 1 1 DETRX_RESULT 2 2 EN_DETRX_RESULT 3 3 RESERVED_15_4 4 15 ixDPCSSYS_CR4_LANE0_DIG_ASIC_RX_OVRD_OUT_0 2 0x100f 9 0 4294967295 ACK 0 0 ACK_OVRD_EN 1 1 ADAPT_STS 2 3 ADAPT_STS_OVRD_EN 4 4 RX_ASYNC_DATA 5 5 RX_ASYNC_DATA_OVRD_EN 6 6 RX_SQ_WEAKKEEP_OUT 7 7 RX_SQ_WEAKKEEP_OUT_OVRD_EN 8 8 RESERVED_15_9 9 15 ixDPCSSYS_CR4_LANE0_DIG_ASIC_LANE_ASIC_IN 2 0x1010 3 0 4294967295 LANE_TX2RX_SER_LB 0 0 LANE_RX2TX_PAR_LB 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR4_LANE0_DIG_ASIC_TX_ASIC_IN_0 2 0x1011 12 0 4294967295 CLK_RDY 0 0 RESET 1 1 INVERT 2 2 DATA_EN 3 3 REQ 4 4 LPD 5 5 PSTATE 6 7 RATE 8 10 WIDTH 11 12 MPLLB_SEL 13 13 DETECT_RX_REQ 14 14 DISABLE 15 15 ixDPCSSYS_CR4_LANE0_DIG_ASIC_TX_ASIC_IN_1 2 0x1012 7 0 4294967295 BEACON_EN 0 0 TX_MAIN_CURSOR 1 6 TX_ASYNC_EN 7 7 TX_ASYNC_DATA 8 8 TX_ASYNC_DRV_EN 9 9 TX_VREGDRV_BYP 10 10 RESERVED_15_11 11 15 ixDPCSSYS_CR4_LANE0_DIG_ASIC_TX_ASIC_IN_2 2 0x1013 3 0 4294967295 TX_PRE_CURSOR 0 5 TX_POST_CURSOR 6 11 RESERVED_15_12 12 15 ixDPCSSYS_CR4_LANE0_DIG_ASIC_TX_ASIC_OUT 2 0x1014 3 0 4294967295 TX_ACK 0 0 DETRX_RESULT 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR4_LANE0_DIG_ASIC_RX_ASIC_OUT_0 2 0x101b 4 0 4294967295 ACK 0 0 VALID 1 1 ADAPT_STS 2 3 RESERVED_15_4 4 15 ixDPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_5 2 0x101d 15 0 4294967295 RPTR_EN_MASTER_LANE 0 0 RPTR_EN_MASTER_LANE_OVRD_EN 1 1 DIG_CLK_EN_OTHER_LANE 2 2 DIG_CLK_EN_OTHER_LANE_OVRD_EN 3 3 DIG_CLK_STATE_MASTER_LANE 4 4 DIG_CLK_STATE_MASTER_LANE_OVRD_EN 5 5 SHIFT_MASTER_LANE 6 6 SHIFT_MASTER_LANE_ORVD_EN 7 7 SHIFT_ACK_OTHER_LANE 8 8 SHIFT_ACK_OTHER_LANE_OVRD_EN 9 9 LANE_MASTER 10 10 LANE_MASTER_OVRD_IN_EN 11 11 TX_DWORD_CLK_SYNC_OVRD 12 12 TX_DWORD_CLK_SYNC_OVRD_EN 13 13 RESERVED_15_14 14 15 ixDPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_OUT_1 2 0x101e 11 0 4294967295 RPTR_EN_OUT 0 0 RPTR_EN_OUT_OVRD_EN 1 1 DIG_CLK_EN_OUT 2 2 DIG_CLK_EN_OUT_OVRD_EN 3 3 DIG_CLK_STATE_OUT 4 4 DIG_CLK_STATE_OUT_OVRD_EN 5 5 SHIFT_OUT 6 6 SHIFT_OUT_OVRD_EN 7 7 SHIFT_ACK_OUT 8 8 SHIFT_ACK_OUT_OVRD_EN 9 9 RESERVED_15_10 10 15 ixDPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0 2 0x1020 11 0 4294967295 TX_P0_ANA_REFGEN_EN 0 0 TX_P0_ANA_VCM_HOLD 1 1 TX_P0_ANA_CLK_EN 2 2 TX_P0_ANA_WORD_CLK_EN 3 3 TX_P0_ANA_RESET 4 4 TX_P0_ANA_SERIAL_EN 5 5 TX_P0_DIG_CLK_EN 6 6 TX_P0_DATA_EN 7 7 TX_P0_ALLOW_RXDET 8 8 TX_P0_ANA_DCC_COMP_CAL_EN 9 9 RESERVED_15_10 10 15 ixDPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S 2 0x1021 11 0 4294967295 TX_P0S_ANA_REFGEN_EN 0 0 TX_P0S_ANA_VCM_HOLD 1 1 TX_P0S_ANA_CLK_EN 2 2 TX_P0S_ANA_WORD_CLK_EN 3 3 TX_P0S_ANA_RESET 4 4 TX_P0S_ANA_SERIAL_EN 5 5 TX_P0S_DIG_CLK_EN 6 6 TX_P0S_DATA_EN 7 7 TX_P0S_ALLOW_RXDET 8 8 TX_P0S_ANA_DCC_COMP_CAL_EN 9 9 RESERVED_15_10 10 15 ixDPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1 2 0x1022 11 0 4294967295 TX_P1_ANA_REFGEN_EN 0 0 TX_P1_ANA_VCM_HOLD 1 1 TX_P1_ANA_CLK_EN 2 2 TX_P1_ANA_WORD_CLK_EN 3 3 TX_P1_ANA_RESET 4 4 TX_P1_ANA_SERIAL_EN 5 5 TX_P1_DIG_CLK_EN 6 6 TX_P1_DATA_EN 7 7 TX_P1_ALLOW_RXDET 8 8 TX_P1_ANA_DCC_COMP_CAL_EN 9 9 RESERVED_15_10 10 15 ixDPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2 2 0x1023 12 0 4294967295 TX_P2_ANA_REFGEN_EN 0 0 TX_P2_ANA_VCM_HOLD 1 1 TX_P2_ANA_CLK_EN 2 2 TX_P2_ANA_WORD_CLK_EN 3 3 TX_P2_ANA_RESET 4 4 TX_P2_ANA_SERIAL_EN 5 5 TX_P2_DIG_CLK_EN 6 6 TX_P2_DATA_EN 7 7 TX_P2_ALLOW_RXDET 8 8 TX_P2_ALLOW_VBOOST 9 9 TX_P2_ANA_DCC_COMP_CAL_EN 10 10 RESERVED_15_11 11 15 ixDPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_0 2 0x1024 2 0 4294967295 TX_REFGEN_EN_TIME 0 7 TX_CLK_EN 8 15 ixDPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_1 2 0x1025 2 0 4294967295 TX_VCM_HOLD_TIME_14_0 0 14 SKIP_TX_VCM_HOLD_WAIT 15 15 ixDPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_2 2 0x1026 2 0 4294967295 TX_VBOOST_DIS_TIME_12_0 0 12 DTB_SEL 13 15 ixDPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_3 2 0x1027 3 0 4294967295 TX_VCM_HOLD_TIME_17_15 0 2 TX_VBOOST_DIS_TIME_13 3 3 RESERVED_15_4 4 15 ixDPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_4 2 0x1028 2 0 4294967295 TX_VCM_HOLD_GS_TIME 0 14 SKIP_TX_VCM_HOLD_GS_PULSE 15 15 ixDPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_5 2 0x1029 5 0 4294967295 TX_RXDET_TIME 0 9 FAST_TX_RXDET 10 10 TX_RESET_TIME 11 12 TX_SERIAL_EN_TIME 13 14 RESERVED_15_15 15 15 ixDPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_DCC_CR_BANK_ADDR 2 0x102a 1 0 4294967295 ADDR 0 15 ixDPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_DCC_CR_BANK_DATA 2 0x102b 1 0 4294967295 DATA 0 15 ixDPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_DCC_DAC_CTRL 2 0x102c 2 0 4294967295 CTRL 0 7 RESERVED_15_8 8 15 ixDPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_DCC_DAC_RANGE 2 0x102d 2 0 4294967295 CTRL 0 1 RESERVED_15_2 2 15 ixDPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_DCC_DAC_SEL 2 0x102e 6 0 4294967295 SEL 0 2 REQ 3 3 CTRL_UPD 4 4 RANGE_UPD 5 5 BIN_HOT 6 6 RESERVED_15_7 7 15 ixDPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_DCC_DAC_ACK 2 0x102f 2 0 4294967295 ACK 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_DCC_DAC_ADDR 2 0x1030 1 0 4294967295 ADDR 0 15 ixDPCSSYS_CR4_LANE0_DIG_TX_CLK_ALIGN_TX_CTL_0 2 0x1031 4 0 4294967295 TX_NUM_2UI_SHIFTS_16B_MODE 0 3 TX_NUM_2UI_SHIFTS_20B_MODE 4 7 TX_FIFO_BYPASS 8 8 RESERVED_15_9 9 15 ixDPCSSYS_CR4_LANE0_DIG_TX_LBERT_CTL 2 0x1032 4 0 4294967295 MODE 0 3 TRIGGER_ERR 4 4 PAT0 5 14 RESERVED_15_15 15 15 ixDPCSSYS_CR4_LANE0_DIG_RX_STAT_LD_VAL_1 2 0x1080 2 0 4294967295 SC1_LD_VAL 0 14 SC1_START 15 15 ixDPCSSYS_CR4_LANE0_DIG_RX_STAT_DATA_MSK 2 0x1081 1 0 4294967295 DATA_MSK_15_0 0 15 ixDPCSSYS_CR4_LANE0_DIG_RX_STAT_MATCH_CTL0 2 0x1082 4 0 4294967295 PTTRN_MSK_CR1A_4_0 0 4 PTTRN_CR1A_4_0 5 9 DATA_MSK_19_16 10 13 SCOPE_DLY 14 15 ixDPCSSYS_CR4_LANE0_DIG_RX_STAT_MATCH_CTL1 2 0x1083 5 0 4294967295 PTTRN_CR1B_EN 0 0 PTTRN_MSK_CR1B_4_0 1 5 PTTRN_CR1B_4_0 6 10 PTTRN_CR1A_ADPT_EN 11 11 RESERVED_15_12 12 15 ixDPCSSYS_CR4_LANE0_DIG_RX_STAT_STAT_CTL0 2 0x1084 10 0 4294967295 RESERVED_0 0 0 CORR_SHFT_SEL_VGA 1 1 CORR_SHFT_SEL 2 2 CORR_SRC_SEL 3 4 CORR_MODE_EN 5 5 STAT_SHFT_SEL 6 9 STAT_SRC_SEL 10 12 STAT_RXCLK_SEL 13 13 SC_TIMER_MODE 14 14 SKIP_EN 15 15 ixDPCSSYS_CR4_LANE0_DIG_RX_STAT_STAT_CTL1 2 0x1085 13 0 4294967295 STAT_CNT_0_EN 0 0 STAT_CNT_1_EN 1 1 STAT_CNT_2_EN 2 2 STAT_CNT_3_EN 3 3 STAT_CNT_4_EN 4 4 STAT_CNT_5_EN 5 5 STAT_CNT_6_EN 6 6 RESERVED_8_7 7 8 SC_PAUSE 9 9 STAT_CLK_EN 10 10 DATA_DLY_SEL 11 12 VLD_LOSS_CLR 13 13 VLD_CTL 14 15 ixDPCSSYS_CR4_LANE0_DIG_RX_STAT_SMPL_CNT1 2 0x1086 2 0 4294967295 SMPL_CNT1 0 14 SMPL_CNT1_DONE 15 15 ixDPCSSYS_CR4_LANE0_DIG_RX_STAT_STAT_CNT_0 2 0x1087 2 0 4294967295 STAT_CNT_0 0 14 SMPL_CNT1_DONE 15 15 ixDPCSSYS_CR4_LANE0_DIG_RX_STAT_STAT_CNT_1 2 0x1088 2 0 4294967295 STAT_CNT_1 0 14 SMPL_CNT1_DONE 15 15 ixDPCSSYS_CR4_LANE0_DIG_RX_STAT_STAT_CNT_2 2 0x1089 2 0 4294967295 STAT_CNT_2 0 14 SMPL_CNT1_DONE 15 15 ixDPCSSYS_CR4_LANE0_DIG_RX_STAT_STAT_CNT_3 2 0x108a 2 0 4294967295 STAT_CNT_3 0 14 SMPL_CNT1_DONE 15 15 ixDPCSSYS_CR4_LANE0_DIG_RX_STAT_STAT_CNT_4 2 0x108b 2 0 4294967295 STAT_CNT_4 0 14 SMPL_CNT1_DONE 15 15 ixDPCSSYS_CR4_LANE0_DIG_RX_STAT_STAT_CNT_5 2 0x108c 2 0 4294967295 STAT_CNT_5 0 14 SMPL_CNT1_DONE 15 15 ixDPCSSYS_CR4_LANE0_DIG_RX_STAT_STAT_CNT_6 2 0x108d 2 0 4294967295 STAT_CNT_6 0 14 SMPL_CNT1_DONE 15 15 ixDPCSSYS_CR4_LANE0_DIG_RX_STAT_CAL_COMP_CLK_CTL 2 0x108e 3 0 4294967295 PRECHRGE_CNT 0 2 REF_DIV_CNT 3 5 RESERVED_15_6 6 15 ixDPCSSYS_CR4_LANE0_DIG_RX_STAT_MATCH_CTL2 2 0x108f 2 0 4294967295 PTTRN_CR1A_19_5 0 14 RESERVED_15_15 15 15 ixDPCSSYS_CR4_LANE0_DIG_RX_STAT_MATCH_CTL3 2 0x1090 2 0 4294967295 PTTRN_MSK_CR1A_19_5 0 14 RESERVED_15_15 15 15 ixDPCSSYS_CR4_LANE0_DIG_RX_STAT_MATCH_CTL4 2 0x1091 2 0 4294967295 PTTRN_CR1B_19_5 0 14 RESERVED_15_15 15 15 ixDPCSSYS_CR4_LANE0_DIG_RX_STAT_MATCH_CTL5 2 0x1092 2 0 4294967295 PTTRN_MSK_CR1B_19_5 0 14 RESERVED_15_15 15 15 ixDPCSSYS_CR4_LANE0_DIG_RX_STAT_STAT_CTL2 2 0x1093 4 0 4294967295 DATA_DLY_SEL_2 0 0 SCOPE_DLY_2 1 1 DISABLE_SAMPLE_COUNT 2 2 RESERVED_15_3 3 15 ixDPCSSYS_CR4_LANE0_DIG_RX_STAT_STAT_STOP 2 0x1094 2 0 4294967295 SC1_STOP 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR4_LANE0_DIG_ANA_TX_OVRD_OUT 2 0x10a0 15 0 4294967295 TX_ANA_CLK_SHIFT 0 0 TX_ANA_DATA_EN 1 1 TX_ANA_REFGEN_EN 2 2 TX_ANA_VCM_HOLD 3 3 TX_ANA_CLK_EN 4 4 TX_ANA_WORD_CLK_EN 5 5 TX_ANA_MPLLA_CLK_EN 6 6 TX_ANA_MPLLB_CLK_EN 7 7 TX_ANA_RESET 8 8 TX_ANA_SERIAL_EN 9 9 TX_ANA_DATA_RATE 10 11 RESERVED 12 12 TX_DIV4_EN 13 13 TX_RXDET_EN 14 14 TX_OVRD_EN 15 15 ixDPCSSYS_CR4_LANE0_DIG_ANA_TX_TERM_CODE_OVRD_OUT 2 0x10a1 5 0 4294967295 TX_TERM_CODE 0 9 TX_TERM_OVRD_EN 10 10 TX_DRV_SRC 11 12 TX_DRV_SRC_OVRD_EN 13 13 RESERVED_15_14 14 15 ixDPCSSYS_CR4_LANE0_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT 2 0x10a2 3 0 4294967295 TX_TERM_DN_CLK 0 0 TX_TERM_CLK_SELF_CLEAR_DISABLE 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR4_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_0 2 0x10a3 3 0 4294967295 TX_ANA_LOAD_CLK 0 0 TX_ANA_CTRL_LEG_PULL_EN_13_0 1 14 TX_EQ_OVRD_EN 15 15 ixDPCSSYS_CR4_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_1 2 0x10a4 2 0 4294967295 TX_ANA_CTRL_LEG_PULL_EN_19_14 0 5 RESERVED_15_6 6 15 ixDPCSSYS_CR4_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_2 2 0x10a5 4 0 4294967295 RESERVED 0 2 TX_ANA_CTRL_EQ_MUX_SEL 3 6 TX_ANA_CTRL_PRE 7 12 RESERVED_15_13 13 15 ixDPCSSYS_CR4_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_3 2 0x10a6 2 0 4294967295 TX_ANA_CTRL_POST 0 8 RESERVED_15_9 9 15 ixDPCSSYS_CR4_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_4 2 0x10a7 1 0 4294967295 TX_ANA_CTRL_LEG_PULL_DIR_19_4 0 15 ixDPCSSYS_CR4_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_5 2 0x10a8 2 0 4294967295 TX_ANA_CTRL_LEG_PULL_DIR_3_0 0 3 RESERVED_15_4 4 15 ixDPCSSYS_CR4_LANE0_DIG_ANA_STATUS_0 2 0x10bb 9 0 4294967295 TX_ANA_CLK_SHIFT_ACK 0 0 TX_ANA_RXDETP_RESULT 1 1 TX_ANA_RXDETM_RESULT 2 2 TX_ANA_LOOPBACK_EN 3 3 TX_ANA_CLK_LB_EN 4 4 RX_ANA_CAL_RESULT 5 5 RX_ANA_SCOPE_DATA 6 6 TX_ANA_DCC_CAL_RESULT 7 7 TX_ANA_CTRL_EQ_MUX 8 15 ixDPCSSYS_CR4_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT 2 0x10c2 8 0 4294967295 TX_ANA_DCC_CAL_RANGE 0 1 TX_ANA_DCC_CAL_RANGE_OVRD_EN 2 2 TX_ANA_DCC_CAL_COMP_EN 3 3 TX_ANA_DCC_CAL_COMP_EN_OVRD_EN 4 4 TX_ANA_DCC_CAL_CTRL 5 12 TX_ANA_DCC_CAL_CTRL_OVRD_EN 13 13 TX_ANA_DCC_CAL_CTRL_EN 14 14 TX_ANA_DCC_CAL_CTRL_EN_OVRD_EN 15 15 ixDPCSSYS_CR4_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2 2 0x10c3 5 0 4294967295 TX_ANA_DCC_CAL_CTRL_SEL 0 2 TX_ANA_DCC_CAL_CTRL_SEL_OVRD_EN 3 3 TX_ANA_DCC_CLK_COMP 4 4 TX_ANA_DCC_CLK_COMP_OVRD_EN 5 5 RESERVED_15_6 6 15 ixDPCSSYS_CR4_LANE0_DIG_ANA_TX_OVRD_OUT_2 2 0x10c4 6 0 4294967295 TX_ANA_FAST_START 0 0 TX_ANA_FAST_START_OVRD_EN 1 1 TX_CLK_LB_EN 2 2 TX_CLK_LB_EN_OVRD_EN 3 3 TX_ACJTAG_EN 4 4 RESERVED_15_5 5 15 ixDPCSSYS_CR4_LANE0_ANA_TX_OVRD_MEAS 2 0x10e0 9 0 4294967295 OVRD_CLK_SHIFT 0 0 CLK_SHIFT_REG 0 0 MEAS_ATB_CAL_MUX 0 0 MEAS_ATB_CAL_COMP 0 0 OVRD_VCM_HOLD 0 0 VCM_HOLD_REG 0 0 PULL_UP_REG 0 0 PULL_DN_REG 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR4_LANE0_ANA_TX_PWR_OVRD 2 0x10e1 9 0 4294967295 OVRD_TX_LOOPBACK 0 0 LOOPBACK_EN_REG 0 0 REFGEN_EN_REG 0 0 CLK_DIV_EN_REG 0 0 DATA_EN_REG_INT 0 0 CLK_EN_REG 0 0 SERIAL_EN_REG 0 0 OVRD_EN 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR4_LANE0_ANA_TX_ALT_BUS 2 0x10e2 6 0 4294967295 DRV_SOURCE_REG 0 0 OVRD_ALT_BUS 0 0 ATB_S_ENABLE 0 0 TX_ALT_RINGO 0 0 JTAG_DATA_REG 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR4_LANE0_ANA_TX_ATB1 2 0x10e3 9 0 4294967295 MEAS_ATB_GD 0 0 MEAS_ATB_VDDH 0 0 OVERRIDE_RXDETREF 0 0 MEAS_ATB_VPTX 0 0 OVERRIDE_REGREF 0 0 MEAS_ATB_VREG_DRV 0 0 MEAS_ATB_VREG 0 0 MEAS_ATB_VPH_HALF 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR4_LANE0_ANA_TX_ATB2 2 0x10e4 9 0 4294967295 MEAS_ATB_VCM 0 0 MEAS_ATB_CAL_VDAC_CM 0 0 MEAS_ATB_CAL_VDAC_DIFF 0 0 MEAS_ATB_TXM 0 0 MEAS_ATB_TXP 0 0 MEAS_ATB_RXDETREF 0 0 LFPS_HIGH_PRIORITY 0 0 OSC_DIV4_EN 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR4_LANE0_ANA_TX_DCC_DAC 2 0x10e5 2 0 4294967295 DCC_DAC_REG 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR4_LANE0_ANA_TX_DCC_CTRL1 2 0x10e6 7 0 4294967295 NC0 0 0 OVRD_DCC_DAC_CTRL_SEL 0 0 DCC_DAC_CTRL_SEL_REG 0 0 OVRD_DCC_DAC_CTRL_EN 0 0 DCC_DAC_CTRL_EN_REG 0 0 OVRD_DCC_DAC_REG 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR4_LANE0_ANA_TX_TERM_CODE 2 0x10e7 2 0 4294967295 TERM_CODE_REG_70 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR4_LANE0_ANA_TX_TERM_CODE_CTRL 2 0x10e8 8 0 4294967295 VREG_BOOST_1 0 0 OVRD_UPDATE_TERM 0 0 UPDATE_TERM_REG 0 0 OVRD_RESET_TERM 0 0 RESET_TERM_REG 0 0 OVRD_TERM_CODE 0 0 TERM_CODE_REG_98 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR4_LANE0_ANA_TX_OVRD_CLK 2 0x10e9 9 0 4294967295 VREG_BOOST_0 0 0 CLK_LB_EN_REG 0 0 OVRD_LB_EN 0 0 MPLLB_CLK_EN_REG 0 0 MPLLA_CLK_EN_REG 0 0 OVRD_MPLLAB_EN 0 0 WORD_CLK_EN_REG 0 0 OVRD_WORD_CLK_EN 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR4_LANE0_ANA_TX_MISC1 2 0x10ea 8 0 4294967295 MEAS_ATB_CAL_CLK_ALIGN 0 0 OVRD_DCC_DAC_CTRL_RANGE 0 0 DCC_DAC_CTRL_RANGE_REG 0 0 OVRD_VREF_SEL 0 0 VREF_SEL_REG 0 0 FORCE_ATB_TXM 0 0 FORCE_ATB_TXP 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR4_LANE0_ANA_TX_MISC2 2 0x10eb 8 0 4294967295 TX_PEAKING_LVL 0 0 VREG_CP_GAIN_CTRL 0 0 TX_SLEW_EN 0 0 EN_INV_POST 0 0 EN_INV_PRE 0 0 TX_VREG_EN_BYP 0 0 TX_VDRIVER_PULLDN_EN 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR4_LANE0_ANA_TX_MISC3 2 0x10ec 4 0 4294967295 TX_VREG_OVRD_RING_CTRL 0 0 TX_DCC_LOWV 0 0 NC7_2 2 7 RESERVED_15_8 8 15 ixDPCSSYS_CR4_LANE0_ANA_TX_RESERVED2 2 0x10ed 2 0 4294967295 NC7_0 0 7 RESERVED_15_8 8 15 ixDPCSSYS_CR4_LANE0_ANA_TX_RESERVED3 2 0x10ee 2 0 4294967295 NC7_0 0 7 RESERVED_15_8 8 15 ixDPCSSYS_CR4_LANE0_ANA_TX_RESERVED4 2 0x10ef 2 0 4294967295 NC7_0 0 7 RESERVED_15_8 8 15 ixDPCSSYS_CR4_LANE1_DIG_ASIC_LANE_OVRD_IN 2 0x1100 5 0 4294967295 LANE_TX2RX_SER_LB 0 0 LANE_RX2TX_PAR_LB 1 1 EN 2 2 RX_ACJTAG_EN 3 3 RESERVED_15_4 4 15 ixDPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_0 2 0x1101 12 0 4294967295 REQ 0 0 REQ_OVRD_EN 1 1 PSTATE 2 3 PSTATE_OVRD_EN 4 4 RATE 5 7 RATE_OVRD_EN 8 8 WIDTH 9 10 WIDTH_OVRD_EN 11 11 MPLLB_SEL 12 12 MPLLB_SEL_OVRD_EN 13 13 DATA_EN 14 14 DATA_EN_OVRD_EN 15 15 ixDPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_1 2 0x1102 11 0 4294967295 NYQUIST_DATA 0 0 DISABLE 1 1 BEACON_EN 2 2 EN 3 3 TX_MAIN_CURSOR 4 9 MAIN_OVRD_EN 10 10 ASYNC_DRV_EN 11 11 ASYNC_DRV_OVRD_EN 12 12 TX_VREGDRV_BYP_OVRD 13 13 TX_VREGDRV_BYP_OVRD_EN 14 14 RESERVED_15_15 15 15 ixDPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_2 2 0x1103 6 0 4294967295 TX_PRE_CURSOR 0 5 PRE_OVRD_EN 6 6 TX_POST_CURSOR 7 12 POST_OVRD_EN 13 13 HDMIMODE_EN 14 14 HDMIMODE_ENABLE_OVRD_EN 15 15 ixDPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_3 2 0x1104 15 0 4294967295 CLK_RDY 0 0 CLK_RDY_OVRD_EN 1 1 DETECT_RX_REQ 2 2 DETECT_RX_REQ_OVRD_EN 3 3 INVERT 4 4 INVERT_OVRD_EN 5 5 LPD 6 6 LPD_OVRD_EN 7 7 TX_DC_COUP_EN 8 8 TX_DC_COUP_EN_OVRD_EN 9 9 PMA_EXTENDED_FIFO_EN 10 10 PMA_EXTENDED_FIFO_EN_OVRD_EN 11 11 TX_MPHY_MODE_EN 12 12 TX_MPHY_MODE_EN_OVRD_EN 13 13 RESERVED_15_14 14 15 ixDPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_4 2 0x1105 3 0 4294967295 RESET 0 0 RESET_OVRD_EN 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_OUT 2 0x1106 5 0 4294967295 TX_ACK 0 0 EN_TX_ACK 1 1 DETRX_RESULT 2 2 EN_DETRX_RESULT 3 3 RESERVED_15_4 4 15 ixDPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_0 2 0x1107 11 0 4294967295 REQ 0 0 REQ_OVRD_EN 1 1 DATA_EN 2 2 DATA_EN_OVRD_EN 3 3 PSTATE 4 5 PSTATE_OVRD_EN 6 6 RATE 7 8 RATE_OVRD_EN 9 9 WIDTH 10 11 WIDTH_OVRD_EN 12 12 RESERVED_15_13 13 15 ixDPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_1 2 0x1108 5 0 4294967295 RX_REF_LD_VAL_5_0 0 5 RX_CDR_VCO_LOWFREQ 6 6 EN 7 7 RX_REF_LD_VAL_6 8 8 RESERVED_15_9 9 15 ixDPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_2 2 0x1109 3 0 4294967295 RX_VCO_LD_VAL 0 12 EN 13 13 RESERVED_15_14 14 15 ixDPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_3 2 0x110a 11 0 4294967295 CDR_TRACK_EN 0 0 CDR_TRACK_EN_OVRD_EN 1 1 CDR_SSC_EN 2 2 CDR_SSC_EN_OVRD_EN 3 3 ALIGN_EN 4 4 ALIGN_EN_OVRD_EN 5 5 CLK_SHIFT 6 6 CLK_SHIFT_OVRD_EN 7 7 DISABLE 8 8 DISABLE_OVRD_EN 9 9 RESERVED_15_10 10 15 ixDPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_4 2 0x110b 11 0 4294967295 LPD 0 0 LPD_OVRD_EN 1 1 INVERT 2 2 INVERT_OVRD_EN 3 3 ADAPT_AFE_EN 4 4 ADAPT_DFE_EN 5 5 ADPT_OVRD_EN 6 6 TERM_EN 7 7 TERM_ACDC 8 8 TERM_OVRD_EN 9 9 RESERVED_15_10 10 15 ixDPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_5 2 0x110c 3 0 4294967295 RESET 0 0 RESET_OVRD_EN 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0 2 0x110d 4 0 4294967295 EQ_ATT_LVL 0 2 EQ_AFE_GAIN 3 6 RESERVED 7 10 EQ_CTLE_BOOST 11 15 ixDPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1 2 0x110e 3 0 4294967295 EQ_DFE_TAP2 0 6 EQ_DFE_TAP1 7 14 EQ_OVRD_EN 15 15 ixDPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_OUT_0 2 0x110f 9 0 4294967295 ACK 0 0 ACK_OVRD_EN 1 1 ADAPT_STS 2 3 ADAPT_STS_OVRD_EN 4 4 RX_ASYNC_DATA 5 5 RX_ASYNC_DATA_OVRD_EN 6 6 RX_SQ_WEAKKEEP_OUT 7 7 RX_SQ_WEAKKEEP_OUT_OVRD_EN 8 8 RESERVED_15_9 9 15 ixDPCSSYS_CR4_LANE1_DIG_ASIC_LANE_ASIC_IN 2 0x1110 3 0 4294967295 LANE_TX2RX_SER_LB 0 0 LANE_RX2TX_PAR_LB 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR4_LANE1_DIG_ASIC_TX_ASIC_IN_0 2 0x1111 12 0 4294967295 CLK_RDY 0 0 RESET 1 1 INVERT 2 2 DATA_EN 3 3 REQ 4 4 LPD 5 5 PSTATE 6 7 RATE 8 10 WIDTH 11 12 MPLLB_SEL 13 13 DETECT_RX_REQ 14 14 DISABLE 15 15 ixDPCSSYS_CR4_LANE1_DIG_ASIC_TX_ASIC_IN_1 2 0x1112 7 0 4294967295 BEACON_EN 0 0 TX_MAIN_CURSOR 1 6 TX_ASYNC_EN 7 7 TX_ASYNC_DATA 8 8 TX_ASYNC_DRV_EN 9 9 TX_VREGDRV_BYP 10 10 RESERVED_15_11 11 15 ixDPCSSYS_CR4_LANE1_DIG_ASIC_TX_ASIC_IN_2 2 0x1113 3 0 4294967295 TX_PRE_CURSOR 0 5 TX_POST_CURSOR 6 11 RESERVED_15_12 12 15 ixDPCSSYS_CR4_LANE1_DIG_ASIC_TX_ASIC_OUT 2 0x1114 3 0 4294967295 TX_ACK 0 0 DETRX_RESULT 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR4_LANE1_DIG_ASIC_RX_ASIC_IN_0 2 0x1115 13 0 4294967295 RESET 0 0 INVERT 1 1 DATA_EN 2 2 REQ 3 3 LPD 4 4 PSTATE 5 6 RATE 7 8 WIDTH 9 10 RESERVED 11 11 ADAPT_AFE_EN 12 12 ADAPT_DFE_EN 13 13 CDR_TRACK_EN 14 14 RESERVED_15_15 15 15 ixDPCSSYS_CR4_LANE1_DIG_ASIC_RX_ASIC_IN_1 2 0x1116 7 0 4294967295 CDR_SSC_EN 0 0 ALIGN_EN 1 1 CLK_SHIFT 2 2 DISABLE 3 3 RX_TERM_EN 4 4 RX_TERM_ACDC 5 5 RESERVED_15_6 6 15 ixDPCSSYS_CR4_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0 2 0x1117 4 0 4294967295 EQ_ATT_LVL 0 2 EQ_AFE_GAIN 3 6 RESERVED 7 10 EQ_CTLE_BOOST 11 15 ixDPCSSYS_CR4_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_1 2 0x1118 3 0 4294967295 EQ_DFE_TAP2 0 6 EQ_DFE_TAP1 7 14 RESERVED_15_15 15 15 ixDPCSSYS_CR4_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0 2 0x1119 3 0 4294967295 RX_CDR_VCO_LOWFREQ 0 0 RX_REF_LD_VAL 1 7 RESERVED_15_8 8 15 ixDPCSSYS_CR4_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1 2 0x111a 2 0 4294967295 RX_VCO_LD_VAL 0 12 RESERVED_15_13 13 15 ixDPCSSYS_CR4_LANE1_DIG_ASIC_RX_ASIC_OUT_0 2 0x111b 4 0 4294967295 ACK 0 0 VALID 1 1 ADAPT_STS 2 3 RESERVED_15_4 4 15 ixDPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_6 2 0x111c 10 0 4294967295 RX_PWM_CLK_SEL 0 1 RX_PWM_CLK_SEL_OVRD_EN 2 2 RX_TERM_LCC_ON 3 3 RX_TERM_LS_ON 4 4 RX_TERM_LS_LCC_ON_OVRD_EN 5 5 RX_TERM_CTL 6 7 RX_TERM_CTL_OVRD_EN 8 8 RX_PWM_EN 9 9 RX_PWM_EN_OVRD_EN 10 10 RESERVED_15_11 11 15 ixDPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_5 2 0x111d 15 0 4294967295 RPTR_EN_MASTER_LANE 0 0 RPTR_EN_MASTER_LANE_OVRD_EN 1 1 DIG_CLK_EN_OTHER_LANE 2 2 DIG_CLK_EN_OTHER_LANE_OVRD_EN 3 3 DIG_CLK_STATE_MASTER_LANE 4 4 DIG_CLK_STATE_MASTER_LANE_OVRD_EN 5 5 SHIFT_MASTER_LANE 6 6 SHIFT_MASTER_LANE_ORVD_EN 7 7 SHIFT_ACK_OTHER_LANE 8 8 SHIFT_ACK_OTHER_LANE_OVRD_EN 9 9 LANE_MASTER 10 10 LANE_MASTER_OVRD_IN_EN 11 11 TX_DWORD_CLK_SYNC_OVRD 12 12 TX_DWORD_CLK_SYNC_OVRD_EN 13 13 RESERVED_15_14 14 15 ixDPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_OUT_1 2 0x111e 11 0 4294967295 RPTR_EN_OUT 0 0 RPTR_EN_OUT_OVRD_EN 1 1 DIG_CLK_EN_OUT 2 2 DIG_CLK_EN_OUT_OVRD_EN 3 3 DIG_CLK_STATE_OUT 4 4 DIG_CLK_STATE_OUT_OVRD_EN 5 5 SHIFT_OUT 6 6 SHIFT_OUT_OVRD_EN 7 7 SHIFT_ACK_OUT 8 8 SHIFT_ACK_OUT_OVRD_EN 9 9 RESERVED_15_10 10 15 ixDPCSSYS_CR4_LANE1_DIG_ASIC_OCLA 2 0x111f 3 0 4294967295 RX_DWORD_OCLA_CLK_EN 0 0 RX_DWORD_OCLA_DATA_EN 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0 2 0x1120 11 0 4294967295 TX_P0_ANA_REFGEN_EN 0 0 TX_P0_ANA_VCM_HOLD 1 1 TX_P0_ANA_CLK_EN 2 2 TX_P0_ANA_WORD_CLK_EN 3 3 TX_P0_ANA_RESET 4 4 TX_P0_ANA_SERIAL_EN 5 5 TX_P0_DIG_CLK_EN 6 6 TX_P0_DATA_EN 7 7 TX_P0_ALLOW_RXDET 8 8 TX_P0_ANA_DCC_COMP_CAL_EN 9 9 RESERVED_15_10 10 15 ixDPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S 2 0x1121 11 0 4294967295 TX_P0S_ANA_REFGEN_EN 0 0 TX_P0S_ANA_VCM_HOLD 1 1 TX_P0S_ANA_CLK_EN 2 2 TX_P0S_ANA_WORD_CLK_EN 3 3 TX_P0S_ANA_RESET 4 4 TX_P0S_ANA_SERIAL_EN 5 5 TX_P0S_DIG_CLK_EN 6 6 TX_P0S_DATA_EN 7 7 TX_P0S_ALLOW_RXDET 8 8 TX_P0S_ANA_DCC_COMP_CAL_EN 9 9 RESERVED_15_10 10 15 ixDPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1 2 0x1122 11 0 4294967295 TX_P1_ANA_REFGEN_EN 0 0 TX_P1_ANA_VCM_HOLD 1 1 TX_P1_ANA_CLK_EN 2 2 TX_P1_ANA_WORD_CLK_EN 3 3 TX_P1_ANA_RESET 4 4 TX_P1_ANA_SERIAL_EN 5 5 TX_P1_DIG_CLK_EN 6 6 TX_P1_DATA_EN 7 7 TX_P1_ALLOW_RXDET 8 8 TX_P1_ANA_DCC_COMP_CAL_EN 9 9 RESERVED_15_10 10 15 ixDPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2 2 0x1123 12 0 4294967295 TX_P2_ANA_REFGEN_EN 0 0 TX_P2_ANA_VCM_HOLD 1 1 TX_P2_ANA_CLK_EN 2 2 TX_P2_ANA_WORD_CLK_EN 3 3 TX_P2_ANA_RESET 4 4 TX_P2_ANA_SERIAL_EN 5 5 TX_P2_DIG_CLK_EN 6 6 TX_P2_DATA_EN 7 7 TX_P2_ALLOW_RXDET 8 8 TX_P2_ALLOW_VBOOST 9 9 TX_P2_ANA_DCC_COMP_CAL_EN 10 10 RESERVED_15_11 11 15 ixDPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_0 2 0x1124 2 0 4294967295 TX_REFGEN_EN_TIME 0 7 TX_CLK_EN 8 15 ixDPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_1 2 0x1125 2 0 4294967295 TX_VCM_HOLD_TIME_14_0 0 14 SKIP_TX_VCM_HOLD_WAIT 15 15 ixDPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_2 2 0x1126 2 0 4294967295 TX_VBOOST_DIS_TIME_12_0 0 12 DTB_SEL 13 15 ixDPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_3 2 0x1127 3 0 4294967295 TX_VCM_HOLD_TIME_17_15 0 2 TX_VBOOST_DIS_TIME_13 3 3 RESERVED_15_4 4 15 ixDPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_4 2 0x1128 2 0 4294967295 TX_VCM_HOLD_GS_TIME 0 14 SKIP_TX_VCM_HOLD_GS_PULSE 15 15 ixDPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_5 2 0x1129 5 0 4294967295 TX_RXDET_TIME 0 9 FAST_TX_RXDET 10 10 TX_RESET_TIME 11 12 TX_SERIAL_EN_TIME 13 14 RESERVED_15_15 15 15 ixDPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_DCC_CR_BANK_ADDR 2 0x112a 1 0 4294967295 ADDR 0 15 ixDPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_DCC_CR_BANK_DATA 2 0x112b 1 0 4294967295 DATA 0 15 ixDPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_DCC_DAC_CTRL 2 0x112c 2 0 4294967295 CTRL 0 7 RESERVED_15_8 8 15 ixDPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_DCC_DAC_RANGE 2 0x112d 2 0 4294967295 CTRL 0 1 RESERVED_15_2 2 15 ixDPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_DCC_DAC_SEL 2 0x112e 6 0 4294967295 SEL 0 2 REQ 3 3 CTRL_UPD 4 4 RANGE_UPD 5 5 BIN_HOT 6 6 RESERVED_15_7 7 15 ixDPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_DCC_DAC_ACK 2 0x112f 2 0 4294967295 ACK 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_DCC_DAC_ADDR 2 0x1130 1 0 4294967295 ADDR 0 15 ixDPCSSYS_CR4_LANE1_DIG_TX_CLK_ALIGN_TX_CTL_0 2 0x1131 4 0 4294967295 TX_NUM_2UI_SHIFTS_16B_MODE 0 3 TX_NUM_2UI_SHIFTS_20B_MODE 4 7 TX_FIFO_BYPASS 8 8 RESERVED_15_9 9 15 ixDPCSSYS_CR4_LANE1_DIG_TX_LBERT_CTL 2 0x1132 4 0 4294967295 MODE 0 3 TRIGGER_ERR 4 4 PAT0 5 14 RESERVED_15_15 15 15 ixDPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0 2 0x1140 12 0 4294967295 RX_P0_ANA_AFE_EN 0 0 RX_P0_ANA_CLK_VREG_EN 1 1 RESERVED_1 2 2 RX_P0_ANA_CLK_EN 3 3 RESERVED_0 4 4 RX_P0_ANA_DESER_EN 5 5 RX_P0_ANA_CDR_EN 6 6 RX_P0_VCO_FREQ_RST 7 7 RX_P0_VCO_CAL_RST 8 8 RX_P0_VCO_CONTCAL_EN 9 9 RX_P0_DIG_CLK_EN 10 10 RESERVED_15_11 11 15 ixDPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S 2 0x1141 12 0 4294967295 RX_P0S_ANA_AFE_EN 0 0 RX_P0S_ANA_CLK_VREG_EN 1 1 RESERVED_2 2 2 RX_P0S_ANA_CLK_EN 3 3 RESERVED_4 4 4 RX_P0S_ANA_DESER_EN 5 5 RX_P0S_ANA_CDR_EN 6 6 RX_P0S_VCO_FREQ_RST 7 7 RX_P0S_VCO_CAL_RST 8 8 RX_P0S_VCO_CONTCAL_EN 9 9 RX_P0S_DIG_CLK_EN 10 10 RESERVED_15_11 11 15 ixDPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1 2 0x1142 12 0 4294967295 RX_P1_ANA_AFE_EN 0 0 RX_P1_ANA_CLK_VREG_EN 1 1 RESERVED_2 2 2 RX_P1_ANA_CLK_EN 3 3 RESERVED_4 4 4 RX_P1_ANA_DESER_EN 5 5 RX_P1_ANA_CDR_EN 6 6 RX_P1_VCO_FREQ_RST 7 7 RX_P1_VCO_CAL_RST 8 8 RX_P1_VCO_CONTCAL_EN 9 9 RX_P1_DIG_CLK_EN 10 10 RESERVED_15_11 11 15 ixDPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2 2 0x1143 12 0 4294967295 RX_P2_ANA_AFE_EN 0 0 RX_P2_ANA_CLK_VREG_EN 1 1 RESERVED_2 2 2 RX_P2_ANA_CLK_EN 3 3 RESERVED_4 4 4 RX_P2_ANA_DESER_EN 5 5 RX_P2_ANA_CDR_EN 6 6 RX_P2_VCO_FREQ_RST 7 7 RX_P2_VCO_CAL_RST 8 8 RX_P2_VCO_CONTCAL_EN 9 9 RX_P2_DIG_CLK_EN 10 10 RESERVED_15_11 11 15 ixDPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1 2 0x1145 5 0 4294967295 RX_AFE_EN_TIME 0 5 FAST_RX_AFE_EN 6 6 RX_VREG_EN_TIME 7 12 FAST_RX_VREG_EN 13 13 RESERVED_15_14 14 15 ixDPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_2 2 0x1146 4 0 4294967295 RX_CLK_EN_TIME 0 5 FAST_RX_CLK_EN 6 6 RX_FAST_START_TIME 7 10 RESERVED_15_11 11 15 ixDPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_3 2 0x1147 5 0 4294967295 RX_RATE_TIME 0 1 RSVD_3_7_2 2 7 RX_CDR_EN_TIME 8 11 RX_DESER_EN_TIME 12 13 RX_DESER_DIS_TIME 14 15 ixDPCSSYS_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0 2 0x1148 8 0 4294967295 INT_GAIN_CAL_FIXED_CNT 0 4 INT_GAIN_CAL_FIXED_CNT_EN 5 5 INT_GAIN_CAL_CNT_SHIFT 6 8 INT_GAIN_CAL_BOUNCE_CNT 9 11 DISABLE_BIN_HOLD 12 12 DISABLE_INT_GAIN_HOLD 13 13 DISABLE_COARSE_CALDONE 14 14 RESERVED_15_15 15 15 ixDPCSSYS_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1 2 0x1149 7 0 4294967295 RX_VCO_OVRD_SEL 0 0 RX_VCO_FREQ_RST 1 1 RX_VCO_CAL_RST 2 2 RX_VCO_CONTCAL_EN 3 3 DISABLE_INT_CAL_MODE 4 4 DPLL_CAL_UG 5 8 DTB_SEL 9 15 ixDPCSSYS_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2 2 0x114a 4 0 4294967295 FREQ_TUNE_START_VAL 0 9 FREQ_TUNE_CAL_STEPS 10 13 SKIP_RX_VCO_FREQ_TUNE_CAL 14 14 SKIP_RX_VCO_CAL 15 15 ixDPCSSYS_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0 2 0x114b 4 0 4294967295 RX_VCO_STARTUP_TIME 0 6 RX_VCO_UPDATE_TIME 7 10 RX_VCO_CNTR_PWRUP_TIME 11 14 FAST_RX_VCO_WAIT 15 15 ixDPCSSYS_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1 2 0x114c 2 0 4294967295 RX_VCO_CNTR_SETTLE_TIME 0 2 RESERVED_15_3 3 15 ixDPCSSYS_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0 2 0x114d 6 0 4294967295 RX_ANA_CDR_FREQ_TUNE 0 9 RX_ANA_VCO_CNTR_PD 10 10 RX_ANA_VCO_CNTR_EN 11 11 RX_ANA_CDR_STARTUP 12 12 RX_ANA_CDR_VCO_EN 13 13 RESERVED_15_14 14 15 ixDPCSSYS_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1 2 0x114e 7 0 4294967295 RX_VCO_FSM_STATE 0 3 RX_VCO_FREQ_RST 4 4 RX_VCO_CAL_RST 5 5 RX_VCO_CONTCAL_EN 6 6 RX_VCO_CAL_DONE 7 7 DPLL_FREQ_RST 8 8 RESERVED_15_9 9 15 ixDPCSSYS_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_2 2 0x114f 4 0 4294967295 VCO_CNTR_FINAL 0 12 VCOCLK_TOO_FAST 13 13 RX_VCO_CORRECT 14 14 RX_VCO_UP 15 15 ixDPCSSYS_CR4_LANE1_DIG_RX_RX_ALIGN_XAUI_COMM_MASK 2 0x1150 2 0 4294967295 XAUI_COMM_MASK 0 9 RESERVED_15_10 10 15 ixDPCSSYS_CR4_LANE1_DIG_RX_LBERT_CTL 2 0x1151 3 0 4294967295 MODE 0 3 SYNC 4 4 RESERVED_15_5 5 15 ixDPCSSYS_CR4_LANE1_DIG_RX_LBERT_ERR 2 0x1152 2 0 4294967295 COUNT 0 14 OV14 15 15 ixDPCSSYS_CR4_LANE1_DIG_RX_CDR_CDR_CTL_0 2 0x1153 7 0 4294967295 PHDET_EN 0 1 PHDET_EDGE 2 3 PHDET_POL 4 4 PHDET_EN_PR_MODE 5 5 ALWAYS_REALIGN 6 6 DTB_SEL 7 10 RESERVED_15_11 11 15 ixDPCSSYS_CR4_LANE1_DIG_RX_CDR_CDR_CTL_1 2 0x1154 2 0 4294967295 SSC_OFF_CNT0 0 9 SSC_OFF_CNT1 10 15 ixDPCSSYS_CR4_LANE1_DIG_RX_CDR_CDR_CTL_2 2 0x1155 2 0 4294967295 SSC_ON_CNT0 0 8 SSC_ON_CNT1 9 15 ixDPCSSYS_CR4_LANE1_DIG_RX_CDR_CDR_CTL_3 2 0x1156 6 0 4294967295 SSC_OFF_PHUG0 0 2 SSC_OFF_PHUG1 3 5 SSC_OFF_FRUG0 6 8 OVRD_DPLL_GAIN 9 9 PHUG_OVRD_VALUE 10 12 FRUG_OVRD_VALUE 13 15 ixDPCSSYS_CR4_LANE1_DIG_RX_CDR_CDR_CTL_4 2 0x1157 6 0 4294967295 SSC_OFF_FRUG1 0 2 SSC_ON_FRUG0 3 5 SSC_ON_FRUG1 6 8 SSC_ON_PHUG0 9 11 SSC_ON_PHUG1 12 14 RESERVED_15_15 15 15 ixDPCSSYS_CR4_LANE1_DIG_RX_CDR_STAT 2 0x1158 3 0 4294967295 PHUG_VALUE 0 2 FRUG_VALUE 3 5 RESERVED_15_6 6 15 ixDPCSSYS_CR4_LANE1_DIG_RX_DPLL_FREQ 2 0x1159 2 0 4294967295 VAL 0 13 RESERVED_15_14 14 15 ixDPCSSYS_CR4_LANE1_DIG_RX_DPLL_FREQ_BOUND_0 2 0x115a 3 0 4294967295 FREQ_BOUND_EN 0 0 UPPER_FREQ_BOUND 1 10 RESERVED_15_11 11 15 ixDPCSSYS_CR4_LANE1_DIG_RX_DPLL_FREQ_BOUND_1 2 0x115b 2 0 4294967295 LOWER_FREQ_BOUND 0 9 RESERVED_15_10 10 15 ixDPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_0 2 0x1160 4 0 4294967295 N_TOP_ASM1 0 9 N_TGG_ASM1 10 13 START_ASM1 14 14 ADPT_CLK_DIV4_EN 15 15 ixDPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1 2 0x1161 5 0 4294967295 N_WAIT_ASM1 0 6 FAST_AFE_DFE_SETTLE 7 7 CTLE_POLE_OVRD_VAL 8 10 CTLE_POLE_OVRD_EN 11 11 RESERVED_15_12 12 15 ixDPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_2 2 0x1162 3 0 4294967295 TGG_PTTRN_0 0 4 TGG_PTTRN_1 5 9 RESERVED_15_10 10 15 ixDPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3 2 0x1163 8 0 4294967295 CTLE_EN 0 4 VGA_EN 5 5 ATT_EN 6 6 DFE_EN 7 11 EYEHE_EN 12 12 EYEHO_EN 13 13 TGG_EN 14 14 ESL_TWICE_DSL 15 15 ixDPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_4 2 0x1164 4 0 4294967295 CTLE_TH 0 3 VGA_TH 4 7 DFE1_TH 8 11 DFE2_TH 12 15 ixDPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_5 2 0x1165 4 0 4294967295 DFE3_TH 0 3 DFE4_TH 4 7 DFE5_TH 8 11 TH_OFFSET 12 15 ixDPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6 2 0x1166 6 0 4294967295 CTLE_MU 0 2 VGA_MU 3 5 ATT_MU 6 8 VGA_SAT_CNT 9 11 VGA_SAT_CNT_STICKY 12 12 ATT_LOW_TH 13 15 ixDPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_7 2 0x1167 4 0 4294967295 VGA_MIN_SAT 0 4 VGA_LEV_HIGH 5 9 VGA_LEV_LOW 10 14 RESERVED_15_15 15 15 ixDPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8 2 0x1168 6 0 4294967295 DFE1_MU 0 2 DFE2_MU 3 5 DFE3_MU 6 8 DFE4_MU 9 11 DFE5_MU 12 14 RESERVED_15_15 15 15 ixDPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_9 2 0x1169 2 0 4294967295 ERR_SLE_ADPT_INIT 0 7 ERR_SLO_ADPT_INIT 8 15 ixDPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG 2 0x116a 6 0 4294967295 RST_ADPT_ATT 0 0 RST_ADPT_VGA 1 1 RST_ADPT_CTLE_BOOST 2 2 RST_ADPT_CTLE_POLE 3 3 RST_ADPT_TAP1 4 4 RESERVED_15_5 5 15 ixDPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ATT_STATUS 2 0x116b 3 0 4294967295 ATT_ADPT_CODE 0 7 ASM1_DON 8 8 RESERVED_15_9 9 15 ixDPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_VGA_STATUS 2 0x116c 3 0 4294967295 VGA_ADPT_CODE 0 9 ASM1_DONE 10 10 RESERVED_15_11 11 15 ixDPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_CTLE_STATUS 2 0x116d 4 0 4294967295 CTLE_BOOST_ADPT_CODE 0 9 CTLE_POLE_ADPT_CODE 10 12 ASM1_DONE 13 13 RESERVED_15_14 14 15 ixDPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_DFE_TAP1_STATUS 2 0x116e 3 0 4294967295 DFE_TAP1_ADPT_CODE 0 12 ASM1_DONE 13 13 RESERVED_15_14 14 15 ixDPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_DFE_TAP2_STATUS 2 0x116f 3 0 4294967295 DFE_TAP2_ADPT_CODE 0 11 ASM1_DONE 12 12 RESERVED_15_13 13 15 ixDPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_DFE_TAP3_STATUS 2 0x1170 3 0 4294967295 DFE_TAP3_ADPT_CODE 0 11 ASM1_DONE 12 12 RESERVED_15_13 13 15 ixDPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_DFE_TAP4_STATUS 2 0x1171 3 0 4294967295 DFE_TAP4_ADPT_CODE 0 11 ASM1_DONE 12 12 RESERVED_15_13 13 15 ixDPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_DFE_TAP5_STATUS 2 0x1172 3 0 4294967295 DFE_TAP5_ADPT_CODE 0 11 ASM1_DONE 12 12 RESERVED_15_13 13 15 ixDPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_DFE_DATA_EVEN_VDAC_OFST 2 0x1173 2 0 4294967295 DFE_DATA_EVEN_VDAC_OFST 0 7 RESERVED_15_8 8 15 ixDPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_DFE_DATA_ODD_VDAC_OFST 2 0x1174 2 0 4294967295 DFE_DATA_ODD_VDAC_OFST 0 7 RESERVED_15_8 8 15 ixDPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN 2 0x1175 2 0 4294967295 RX_ANA_SLICER_CTRL_E 0 3 RESERVED_15_4 4 15 ixDPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD 2 0x1176 2 0 4294967295 RX_ANA_SLICER_CTRL_O 0 3 RESERVED_15_4 4 15 ixDPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST 2 0x1177 2 0 4294967295 DFE_ERROR_EVEN_VDAC_OFST 0 7 RESERVED_15_8 8 15 ixDPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST 2 0x1178 2 0 4294967295 DFE_ERROR_ODD_VDAC_OFST 0 7 RESERVED_15_8 8 15 ixDPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL 2 0x1179 2 0 4294967295 E_SLO_LVL 0 7 E_SLE_LVL 8 15 ixDPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_RESET 2 0x117a 2 0 4294967295 RESET_ASM1 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1 2 0x117b 4 0 4294967295 DFE_T1_IDAC 0 4 DFE_T2_IDAC 5 9 DCC_START_IDAC 10 14 RESERVED_15_15 15 15 ixDPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2 2 0x117c 3 0 4294967295 DFE_DAT_EVEN_VDAC 0 4 DFE_DAT_ODD_VDAC 5 9 RESERVED_15_10 10 15 ixDPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3 2 0x117d 3 0 4294967295 DFE_ERR_EVEN_VDAC 0 4 DFE_ERR_ODD_VDAC 5 9 RESERVED_15_10 10 15 ixDPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_CR_BANK_ADDR 2 0x117e 1 0 4294967295 ADDR 0 15 ixDPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_CR_BANK_DATA 2 0x117f 1 0 4294967295 DATA 0 15 ixDPCSSYS_CR4_LANE1_DIG_RX_STAT_LD_VAL_1 2 0x1180 2 0 4294967295 SC1_LD_VAL 0 14 SC1_START 15 15 ixDPCSSYS_CR4_LANE1_DIG_RX_STAT_DATA_MSK 2 0x1181 1 0 4294967295 DATA_MSK_15_0 0 15 ixDPCSSYS_CR4_LANE1_DIG_RX_STAT_MATCH_CTL0 2 0x1182 4 0 4294967295 PTTRN_MSK_CR1A_4_0 0 4 PTTRN_CR1A_4_0 5 9 DATA_MSK_19_16 10 13 SCOPE_DLY 14 15 ixDPCSSYS_CR4_LANE1_DIG_RX_STAT_MATCH_CTL1 2 0x1183 5 0 4294967295 PTTRN_CR1B_EN 0 0 PTTRN_MSK_CR1B_4_0 1 5 PTTRN_CR1B_4_0 6 10 PTTRN_CR1A_ADPT_EN 11 11 RESERVED_15_12 12 15 ixDPCSSYS_CR4_LANE1_DIG_RX_STAT_STAT_CTL0 2 0x1184 10 0 4294967295 RESERVED_0 0 0 CORR_SHFT_SEL_VGA 1 1 CORR_SHFT_SEL 2 2 CORR_SRC_SEL 3 4 CORR_MODE_EN 5 5 STAT_SHFT_SEL 6 9 STAT_SRC_SEL 10 12 STAT_RXCLK_SEL 13 13 SC_TIMER_MODE 14 14 SKIP_EN 15 15 ixDPCSSYS_CR4_LANE1_DIG_RX_STAT_STAT_CTL1 2 0x1185 13 0 4294967295 STAT_CNT_0_EN 0 0 STAT_CNT_1_EN 1 1 STAT_CNT_2_EN 2 2 STAT_CNT_3_EN 3 3 STAT_CNT_4_EN 4 4 STAT_CNT_5_EN 5 5 STAT_CNT_6_EN 6 6 RESERVED_8_7 7 8 SC_PAUSE 9 9 STAT_CLK_EN 10 10 DATA_DLY_SEL 11 12 VLD_LOSS_CLR 13 13 VLD_CTL 14 15 ixDPCSSYS_CR4_LANE1_DIG_RX_STAT_SMPL_CNT1 2 0x1186 2 0 4294967295 SMPL_CNT1 0 14 SMPL_CNT1_DONE 15 15 ixDPCSSYS_CR4_LANE1_DIG_RX_STAT_STAT_CNT_0 2 0x1187 2 0 4294967295 STAT_CNT_0 0 14 SMPL_CNT1_DONE 15 15 ixDPCSSYS_CR4_LANE1_DIG_RX_STAT_STAT_CNT_1 2 0x1188 2 0 4294967295 STAT_CNT_1 0 14 SMPL_CNT1_DONE 15 15 ixDPCSSYS_CR4_LANE1_DIG_RX_STAT_STAT_CNT_2 2 0x1189 2 0 4294967295 STAT_CNT_2 0 14 SMPL_CNT1_DONE 15 15 ixDPCSSYS_CR4_LANE1_DIG_RX_STAT_STAT_CNT_3 2 0x118a 2 0 4294967295 STAT_CNT_3 0 14 SMPL_CNT1_DONE 15 15 ixDPCSSYS_CR4_LANE1_DIG_RX_STAT_STAT_CNT_4 2 0x118b 2 0 4294967295 STAT_CNT_4 0 14 SMPL_CNT1_DONE 15 15 ixDPCSSYS_CR4_LANE1_DIG_RX_STAT_STAT_CNT_5 2 0x118c 2 0 4294967295 STAT_CNT_5 0 14 SMPL_CNT1_DONE 15 15 ixDPCSSYS_CR4_LANE1_DIG_RX_STAT_STAT_CNT_6 2 0x118d 2 0 4294967295 STAT_CNT_6 0 14 SMPL_CNT1_DONE 15 15 ixDPCSSYS_CR4_LANE1_DIG_RX_STAT_CAL_COMP_CLK_CTL 2 0x118e 3 0 4294967295 PRECHRGE_CNT 0 2 REF_DIV_CNT 3 5 RESERVED_15_6 6 15 ixDPCSSYS_CR4_LANE1_DIG_RX_STAT_MATCH_CTL2 2 0x118f 2 0 4294967295 PTTRN_CR1A_19_5 0 14 RESERVED_15_15 15 15 ixDPCSSYS_CR4_LANE1_DIG_RX_STAT_MATCH_CTL3 2 0x1190 2 0 4294967295 PTTRN_MSK_CR1A_19_5 0 14 RESERVED_15_15 15 15 ixDPCSSYS_CR4_LANE1_DIG_RX_STAT_MATCH_CTL4 2 0x1191 2 0 4294967295 PTTRN_CR1B_19_5 0 14 RESERVED_15_15 15 15 ixDPCSSYS_CR4_LANE1_DIG_RX_STAT_MATCH_CTL5 2 0x1192 2 0 4294967295 PTTRN_MSK_CR1B_19_5 0 14 RESERVED_15_15 15 15 ixDPCSSYS_CR4_LANE1_DIG_RX_STAT_STAT_CTL2 2 0x1193 4 0 4294967295 DATA_DLY_SEL_2 0 0 SCOPE_DLY_2 1 1 DISABLE_SAMPLE_COUNT 2 2 RESERVED_15_3 3 15 ixDPCSSYS_CR4_LANE1_DIG_RX_STAT_STAT_STOP 2 0x1194 2 0 4294967295 SC1_STOP 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR4_LANE1_DIG_MPHY_RX_PWM_CTL 2 0x1195 3 0 4294967295 RX_PWM_POL 0 0 RX_PWM_DATA_POL 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR4_LANE1_DIG_MPHY_RX_TERM_LS_CTL 2 0x1196 2 0 4294967295 RX_TERM_LCC_CNT 0 2 RESERVED_15_3 3 15 ixDPCSSYS_CR4_LANE1_DIG_MPHY_RX_ANA_PWM_CLK_STABLE_CNT 2 0x1197 2 0 4294967295 PWM_CLK_STABLE_CNT 0 3 RESERVED_15_4 4 15 ixDPCSSYS_CR4_LANE1_DIG_ANA_TX_OVRD_OUT 2 0x11a0 15 0 4294967295 TX_ANA_CLK_SHIFT 0 0 TX_ANA_DATA_EN 1 1 TX_ANA_REFGEN_EN 2 2 TX_ANA_VCM_HOLD 3 3 TX_ANA_CLK_EN 4 4 TX_ANA_WORD_CLK_EN 5 5 TX_ANA_MPLLA_CLK_EN 6 6 TX_ANA_MPLLB_CLK_EN 7 7 TX_ANA_RESET 8 8 TX_ANA_SERIAL_EN 9 9 TX_ANA_DATA_RATE 10 11 RESERVED 12 12 TX_DIV4_EN 13 13 TX_RXDET_EN 14 14 TX_OVRD_EN 15 15 ixDPCSSYS_CR4_LANE1_DIG_ANA_TX_TERM_CODE_OVRD_OUT 2 0x11a1 5 0 4294967295 TX_TERM_CODE 0 9 TX_TERM_OVRD_EN 10 10 TX_DRV_SRC 11 12 TX_DRV_SRC_OVRD_EN 13 13 RESERVED_15_14 14 15 ixDPCSSYS_CR4_LANE1_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT 2 0x11a2 3 0 4294967295 TX_TERM_DN_CLK 0 0 TX_TERM_CLK_SELF_CLEAR_DISABLE 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR4_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_0 2 0x11a3 3 0 4294967295 TX_ANA_LOAD_CLK 0 0 TX_ANA_CTRL_LEG_PULL_EN_13_0 1 14 TX_EQ_OVRD_EN 15 15 ixDPCSSYS_CR4_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_1 2 0x11a4 2 0 4294967295 TX_ANA_CTRL_LEG_PULL_EN_19_14 0 5 RESERVED_15_6 6 15 ixDPCSSYS_CR4_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_2 2 0x11a5 4 0 4294967295 RESERVED 0 2 TX_ANA_CTRL_EQ_MUX_SEL 3 6 TX_ANA_CTRL_PRE 7 12 RESERVED_15_13 13 15 ixDPCSSYS_CR4_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_3 2 0x11a6 2 0 4294967295 TX_ANA_CTRL_POST 0 8 RESERVED_15_9 9 15 ixDPCSSYS_CR4_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_4 2 0x11a7 1 0 4294967295 TX_ANA_CTRL_LEG_PULL_DIR_19_4 0 15 ixDPCSSYS_CR4_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_5 2 0x11a8 2 0 4294967295 TX_ANA_CTRL_LEG_PULL_DIR_3_0 0 3 RESERVED_15_4 4 15 ixDPCSSYS_CR4_LANE1_DIG_ANA_RX_CTL_OVRD_OUT 2 0x11a9 9 0 4294967295 RESERVED 0 0 RX_ANA_DATA_RATE 1 2 RX_ANA_WORD_CLK_EN 3 3 RX_ANA_DIV4_EN 4 4 RX_ANA_DFE_TAPS_EN 5 5 RX_ANA_ADAPTATION_EN 6 6 RX_LBK_CLK_EN 7 7 RX_CTL_OVRD_EN 8 8 RESERVED_15_9 9 15 ixDPCSSYS_CR4_LANE1_DIG_ANA_RX_PWR_OVRD_OUT 2 0x11aa 9 0 4294967295 RX_ANA_AFE_EN 0 0 RX_ANA_CLK_VREG_EN 1 1 RX_ANA_CLK_DCC_EN 2 2 RX_ANA_CLK_EN 3 3 RX_ANA_CDR_EN 4 4 RX_ANA_DESERIAL_EN 5 5 RX_PWR_OVRD_EN 6 6 RX_ANA_FAST_START 7 7 RESERVED_15_8 8 15 ixDPCSSYS_CR4_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0 2 0x11ab 7 0 4294967295 RX_ANA_CDR_VCO_EN 0 0 RX_ANA_CDR_STARTUP 1 1 RX_VCO_CDR_OVRD_EN 2 2 RX_ANA_CDR_FREQ_TUNE 3 12 RX_ANA_VCO_CNTR_EN 13 13 RX_ANA_VCO_CNTR_CLK 14 14 RX_CDR_FREQ_TUNE_OVRD_EN 15 15 ixDPCSSYS_CR4_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_1 2 0x11ac 3 0 4294967295 RX_ANA_CDR_VCO_LOWFREQ 0 0 RX_ANA_VCO_CNTR_PD 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR4_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_2 2 0x11ad 3 0 4294967295 RX_ANA_CDR_FREQ_TUNE_CLK 0 0 CDR_FREQ_TUNE_CLK_SELF_CLEAR_DISABLE 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR4_LANE1_DIG_ANA_RX_CAL 2 0x11ae 7 0 4294967295 RX_ANA_CAL_MUXA_SEL 0 4 RX_ANA_CAL_MUXB_SEL 5 9 RX_ANA_CAL_LPFBYP_EN 10 10 RESERVED 11 11 RX_ANA_SLICER_CAL_EN 12 12 RX_ANA_CAL_MODE 13 14 RX_ANA_CAL_COMP_EN 15 15 ixDPCSSYS_CR4_LANE1_DIG_ANA_RX_DAC_CTRL 2 0x11af 2 0 4294967295 RX_ANA_CAL_DAC_CTRL 0 7 RESERVED_15_8 8 15 ixDPCSSYS_CR4_LANE1_DIG_ANA_RX_DAC_CTRL_OVRD 2 0x11b0 2 0 4294967295 RX_CAL_DAC_CTRL_OVRD 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR4_LANE1_DIG_ANA_RX_DAC_CTRL_SEL 2 0x11b1 2 0 4294967295 RX_ANA_CAL_DAC_CTRL_SEL 0 4 RESERVED_15_5 5 15 ixDPCSSYS_CR4_LANE1_DIG_ANA_RX_AFE_ATT_VGA 2 0x11b2 5 0 4294967295 RX_ANA_AFE_ATT_LVL 0 2 RX_ANA_AFE_GAIN 3 6 RESERVED 7 10 RX_AFE_OVRD_EN 11 11 RESERVED_15_12 12 15 ixDPCSSYS_CR4_LANE1_DIG_ANA_RX_AFE_CTLE 2 0x11b3 3 0 4294967295 RESERVED 0 2 RX_ANA_AFE_CTLE_BOOST 3 7 RESERVED_15_8 8 15 ixDPCSSYS_CR4_LANE1_DIG_ANA_RX_SCOPE 2 0x11b4 7 0 4294967295 RX_ANA_SCOPE_EN 0 0 RX_ANA_SCOPE_SEL 1 2 RX_ANA_SCOPE_PH_CLK 3 3 RX_ANA_SCOPE_PHASE 4 11 RX_ANA_SCOPE_CLK_EN 12 12 RX_SCOPE_SELF_CLEAR_DISABLE 13 13 RESERVED_15_14 14 15 ixDPCSSYS_CR4_LANE1_DIG_ANA_RX_SLICER_CTRL 2 0x11b5 4 0 4294967295 RX_ANA_SLICER_CTRL_E 0 3 RX_ANA_SLICER_CTRL_O 4 7 RX_ANA_SLICER_CTRL_OVRD_EN 8 8 RESERVED_15_9 9 15 ixDPCSSYS_CR4_LANE1_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST 2 0x11b6 2 0 4294967295 RX_ANA_IQ_PHASE_ADJUST 0 6 RESERVED_15_7 7 15 ixDPCSSYS_CR4_LANE1_DIG_ANA_RX_ANA_IQ_SENSE_EN 2 0x11b7 2 0 4294967295 RX_ANA_IQ_SENSE_EN 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR4_LANE1_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN 2 0x11b8 3 0 4294967295 RX_ANA_CAL_DAC_CTRL_EN 0 0 DAC_CTRL_SELF_CLEAR_DISABLE 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR4_LANE1_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE 2 0x11b9 3 0 4294967295 RX_ANA_AFE_UPDATE_EN 0 0 AFE_UPDATE_SELF_CLEAR_DISABLE 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR4_LANE1_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK 2 0x11ba 3 0 4294967295 RX_ANA_IQ_PHASE_ADJUST_CLK 0 0 PHASE_ADJUST_SELF_CLEAR_DISABLE 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR4_LANE1_DIG_ANA_STATUS_0 2 0x11bb 9 0 4294967295 TX_ANA_CLK_SHIFT_ACK 0 0 TX_ANA_RXDETP_RESULT 1 1 TX_ANA_RXDETM_RESULT 2 2 TX_ANA_LOOPBACK_EN 3 3 TX_ANA_CLK_LB_EN 4 4 RX_ANA_CAL_RESULT 5 5 RX_ANA_SCOPE_DATA 6 6 TX_ANA_DCC_CAL_RESULT 7 7 TX_ANA_CTRL_EQ_MUX 8 15 ixDPCSSYS_CR4_LANE1_DIG_ANA_STATUS_1 2 0x11bc 2 0 4294967295 RX_ANA_VCO_CNTR 0 12 RESERVED_15_13 13 15 ixDPCSSYS_CR4_LANE1_DIG_ANA_RX_TERM_CODE_OVRD_OUT 2 0x11bd 3 0 4294967295 RX_TERM_CODE 0 5 RX_TERM_OVRD_EN 6 6 RESERVED_15_7 7 15 ixDPCSSYS_CR4_LANE1_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT 2 0x11be 3 0 4294967295 RX_TERM_CLK 0 0 RX_TERM_CLK_SELF_CLEAR_DISABLE 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR4_LANE1_DIG_ANA_MPHY_OVRD_OUT 2 0x11bf 9 0 4294967295 RX_ANA_SQ_CTRL_TRESH 0 2 RX_ANA_SQ_CTRL_TRESH_OVRD_EN 3 3 RX_ANA_SQ_CTRL_RESP 4 5 RX_ANA_SQ_CTRL_RESP_OVRD_EN 6 6 RX_ANA_PWM_EN 7 7 RX_ANA_PWM_EN_OVRD_EN 8 8 RX_ANA_PWM_CLK_SEL 9 10 RX_ANA_PWM_CLK_SEL_OVRD_EN 11 11 RESERVED_15_12 12 15 ixDPCSSYS_CR4_LANE1_DIG_ANA_SIGDET_OVRD_OUT_1 2 0x11c0 7 0 4294967295 RX_ANA_SIGDET_HF_THRESH 0 2 RX_ANA_SIGDET_HF_THRESH_OVRD_EN 3 3 RX_ANA_SIGDET_HF_CAL_TUNE 4 9 RX_ANA_SIGDET_CAL_TUNE_OVRD_EN 10 10 RX_ANA_SIGDET_CAL_EN 11 11 RX_ANA_SIGDET_CAL_EN_OVRD_EN 12 12 RESERVED_15_13 13 15 ixDPCSSYS_CR4_LANE1_DIG_ANA_SIGDET_OVRD_OUT_2 2 0x11c1 7 0 4294967295 RX_ANA_SIGDET_LF_THRESH 0 2 RX_ANA_SIGDET_LF_THRESH_OVRD_EN 3 3 RX_ANA_SIGDET_LF_FILTER_EN 4 4 RX_ANA_SIGDET_LF_FILTER_EN_OVRD_EN 5 5 RX_ANA_SIGDET_CAL_TUNE 6 11 RX_ANA_SIGDET_CAL_TUNE_OVRD_EN 12 12 RESERVED_15_13 13 15 ixDPCSSYS_CR4_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT 2 0x11c2 8 0 4294967295 TX_ANA_DCC_CAL_RANGE 0 1 TX_ANA_DCC_CAL_RANGE_OVRD_EN 2 2 TX_ANA_DCC_CAL_COMP_EN 3 3 TX_ANA_DCC_CAL_COMP_EN_OVRD_EN 4 4 TX_ANA_DCC_CAL_CTRL 5 12 TX_ANA_DCC_CAL_CTRL_OVRD_EN 13 13 TX_ANA_DCC_CAL_CTRL_EN 14 14 TX_ANA_DCC_CAL_CTRL_EN_OVRD_EN 15 15 ixDPCSSYS_CR4_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2 2 0x11c3 5 0 4294967295 TX_ANA_DCC_CAL_CTRL_SEL 0 2 TX_ANA_DCC_CAL_CTRL_SEL_OVRD_EN 3 3 TX_ANA_DCC_CLK_COMP 4 4 TX_ANA_DCC_CLK_COMP_OVRD_EN 5 5 RESERVED_15_6 6 15 ixDPCSSYS_CR4_LANE1_DIG_ANA_TX_OVRD_OUT_2 2 0x11c4 6 0 4294967295 TX_ANA_FAST_START 0 0 TX_ANA_FAST_START_OVRD_EN 1 1 TX_CLK_LB_EN 2 2 TX_CLK_LB_EN_OVRD_EN 3 3 TX_ACJTAG_EN 4 4 RESERVED_15_5 5 15 ixDPCSSYS_CR4_LANE1_ANA_TX_OVRD_MEAS 2 0x11e0 9 0 4294967295 OVRD_CLK_SHIFT 0 0 CLK_SHIFT_REG 0 0 MEAS_ATB_CAL_MUX 0 0 MEAS_ATB_CAL_COMP 0 0 OVRD_VCM_HOLD 0 0 VCM_HOLD_REG 0 0 PULL_UP_REG 0 0 PULL_DN_REG 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR4_LANE1_ANA_TX_PWR_OVRD 2 0x11e1 9 0 4294967295 OVRD_TX_LOOPBACK 0 0 LOOPBACK_EN_REG 0 0 REFGEN_EN_REG 0 0 CLK_DIV_EN_REG 0 0 DATA_EN_REG_INT 0 0 CLK_EN_REG 0 0 SERIAL_EN_REG 0 0 OVRD_EN 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR4_LANE1_ANA_TX_ALT_BUS 2 0x11e2 6 0 4294967295 DRV_SOURCE_REG 0 0 OVRD_ALT_BUS 0 0 ATB_S_ENABLE 0 0 TX_ALT_RINGO 0 0 JTAG_DATA_REG 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR4_LANE1_ANA_TX_ATB1 2 0x11e3 9 0 4294967295 MEAS_ATB_GD 0 0 MEAS_ATB_VDDH 0 0 OVERRIDE_RXDETREF 0 0 MEAS_ATB_VPTX 0 0 OVERRIDE_REGREF 0 0 MEAS_ATB_VREG_DRV 0 0 MEAS_ATB_VREG 0 0 MEAS_ATB_VPH_HALF 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR4_LANE1_ANA_TX_ATB2 2 0x11e4 9 0 4294967295 MEAS_ATB_VCM 0 0 MEAS_ATB_CAL_VDAC_CM 0 0 MEAS_ATB_CAL_VDAC_DIFF 0 0 MEAS_ATB_TXM 0 0 MEAS_ATB_TXP 0 0 MEAS_ATB_RXDETREF 0 0 LFPS_HIGH_PRIORITY 0 0 OSC_DIV4_EN 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR4_LANE1_ANA_TX_DCC_DAC 2 0x11e5 2 0 4294967295 DCC_DAC_REG 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR4_LANE1_ANA_TX_DCC_CTRL1 2 0x11e6 7 0 4294967295 NC0 0 0 OVRD_DCC_DAC_CTRL_SEL 0 0 DCC_DAC_CTRL_SEL_REG 0 0 OVRD_DCC_DAC_CTRL_EN 0 0 DCC_DAC_CTRL_EN_REG 0 0 OVRD_DCC_DAC_REG 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR4_LANE1_ANA_TX_TERM_CODE 2 0x11e7 2 0 4294967295 TERM_CODE_REG_70 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR4_LANE1_ANA_TX_TERM_CODE_CTRL 2 0x11e8 8 0 4294967295 VREG_BOOST_1 0 0 OVRD_UPDATE_TERM 0 0 UPDATE_TERM_REG 0 0 OVRD_RESET_TERM 0 0 RESET_TERM_REG 0 0 OVRD_TERM_CODE 0 0 TERM_CODE_REG_98 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR4_LANE1_ANA_TX_OVRD_CLK 2 0x11e9 9 0 4294967295 VREG_BOOST_0 0 0 CLK_LB_EN_REG 0 0 OVRD_LB_EN 0 0 MPLLB_CLK_EN_REG 0 0 MPLLA_CLK_EN_REG 0 0 OVRD_MPLLAB_EN 0 0 WORD_CLK_EN_REG 0 0 OVRD_WORD_CLK_EN 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR4_LANE1_ANA_TX_MISC1 2 0x11ea 8 0 4294967295 MEAS_ATB_CAL_CLK_ALIGN 0 0 OVRD_DCC_DAC_CTRL_RANGE 0 0 DCC_DAC_CTRL_RANGE_REG 0 0 OVRD_VREF_SEL 0 0 VREF_SEL_REG 0 0 FORCE_ATB_TXM 0 0 FORCE_ATB_TXP 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR4_LANE1_ANA_TX_MISC2 2 0x11eb 8 0 4294967295 TX_PEAKING_LVL 0 0 VREG_CP_GAIN_CTRL 0 0 TX_SLEW_EN 0 0 EN_INV_POST 0 0 EN_INV_PRE 0 0 TX_VREG_EN_BYP 0 0 TX_VDRIVER_PULLDN_EN 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR4_LANE1_ANA_TX_MISC3 2 0x11ec 4 0 4294967295 TX_VREG_OVRD_RING_CTRL 0 0 TX_DCC_LOWV 0 0 NC7_2 2 7 RESERVED_15_8 8 15 ixDPCSSYS_CR4_LANE1_ANA_TX_RESERVED2 2 0x11ed 2 0 4294967295 NC7_0 0 7 RESERVED_15_8 8 15 ixDPCSSYS_CR4_LANE1_ANA_TX_RESERVED3 2 0x11ee 2 0 4294967295 NC7_0 0 7 RESERVED_15_8 8 15 ixDPCSSYS_CR4_LANE1_ANA_TX_RESERVED4 2 0x11ef 2 0 4294967295 NC7_0 0 7 RESERVED_15_8 8 15 ixDPCSSYS_CR4_LANE1_ANA_RX_CLK_1 2 0x11f0 8 0 4294967295 CDR_VCO_STARTUP_CODE 0 0 CDR_VCO_TEMP_COMP_EN 0 0 CDR_VCO_USE_UNCAL_BIAS 0 0 OVERRIDE_CDR_EN 0 0 OVRD_CLK_EN 0 0 CLK_EN_REG 0 0 NC7 7 7 RESERVED_15_8 8 15 ixDPCSSYS_CR4_LANE1_ANA_RX_CLK_2 2 0x11f1 5 0 4294967295 IQ_PHASE_ADJUST_REG 0 0 OVRD_IQ_PHASE_ADJUST 0 0 RX_LOOPBACK_CLK_REG 0 0 OVRD_RX_LOOPBACK_CLK 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR4_LANE1_ANA_RX_CDR_DES 2 0x11f2 7 0 4294967295 OVRD_WORD_CLK_EN 0 0 WORD_CLK_EN_REG 0 0 PHDET_ODD_REG 0 0 PHDET_EVEN_REG 0 0 SIGDET_VREF_EXT_EN 0 0 NC7_5 5 7 RESERVED_15_8 8 15 ixDPCSSYS_CR4_LANE1_ANA_RX_SLC_CTRL 2 0x11f3 3 0 4294967295 RX_SLICER_CTRL_O_REG 0 0 RX_SLICER_CTRL_E_REG 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR4_LANE1_ANA_RX_PWR_CTRL1 2 0x11f4 8 0 4294967295 OVRD_ACJT_EN 0 0 ACJT_EN_REG 0 0 OVRD_AFE_EN 0 0 AFE_EN_REG 0 0 AFE_CM_SEL 0 0 ATT_PULLDN_EN 0 0 NC7_7 7 7 RESERVED_15_8 8 15 ixDPCSSYS_CR4_LANE1_ANA_RX_PWR_CTRL2 2 0x11f5 9 0 4294967295 OVRD_DFE_EN 0 0 DFE_EN_REG 0 0 OVRD_DESERIAL_EN 0 0 DESERIAL_EN_REG 0 0 OVRD_LOOPBACK_EN 0 0 LOOPBACK_EN_REG 0 0 OVRD_FAST_START 0 0 FAST_START_REG 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR4_LANE1_ANA_RX_SQ 2 0x11f6 7 0 4294967295 SQ_CTRL_RESP_REG 0 0 OVRD_SQ_CTRL_RESP 0 0 NC4_3 3 4 SQ_CTRL_TRESH_REG 0 0 OVRD_SQ_CTRL_TRESH 0 0 AFE_LOOPBACK_SEL 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR4_LANE1_ANA_RX_CAL1 2 0x11f7 5 0 4294967295 DFE_TAPS_EN_REG 0 0 OVRD_DFE_TAPS_EN 0 0 CAL_MUXB_SEL_REG 0 0 OVRD_CAL_MUXB_SEL 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR4_LANE1_ANA_RX_CAL2 2 0x11f8 5 0 4294967295 AFE_PD_EQ_OFFSET 0 0 CAL_IDACS_USE_UNCAL 0 0 CAL_MUXA_SEL_REG 0 0 OVRD_CAL_MUXA_SEL 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR4_LANE1_ANA_RX_ATB_REGREF 2 0x11f9 8 0 4294967295 OVERRIDE_REGREF_VCO 0 0 OVERRIDE_REGREF_CLK 0 0 OVERRIDE_REGREF_IQC 0 0 BOOST_REGREF_IQC 0 0 OVRD_RX_SLICER_CTRL 0 0 OVRD_RX_TERM_AC_DCZ 0 0 RX_TERM_AC_DCZ_REG 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR4_LANE1_ANA_RX_ATB_MEAS1 2 0x11fa 9 0 4294967295 MASTER_ATB_EN 0 0 MEAS_ATB_VP 0 0 MEAS_ATB_GD 0 0 MEAS_ATB_VREG_VCO 0 0 MEAS_ATB_VREG_CLK 0 0 MEAS_ATB_VREG_IQC 0 0 REGS_FB_DIV_CTRL 0 0 RX_VREG_CLK_BYPASS 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR4_LANE1_ANA_RX_ATB_MEAS2 2 0x11fb 2 0 4294967295 MEAS_ATB_RX 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR4_LANE1_ANA_RX_ATB_MEAS3 2 0x11fc 7 0 4294967295 MEAS_ATB_CDR_VCO_GD 0 0 MEAS_ATB_CDR_VCO_VIREF_200U 0 0 MEAS_ATB_VIBIAS_CDR_VCO 0 0 MEAS_ATB_CDR_VCO_VOSC 0 0 MEAS_ATB_CAL_MUX 0 0 RX_VREG_OVERRIDE_RING_CTRL 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR4_LANE1_ANA_RX_ATB_MEAS4 2 0x11fd 3 0 4294967295 MEAS_ATB_CAL_VREF 0 0 NC7 7 7 RESERVED_15_8 8 15 ixDPCSSYS_CR4_LANE1_ANA_RX_ATB_FRC 2 0x11fe 2 0 4294967295 FRC_ATB_CAL_VREF 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR4_LANE1_ANA_RX_RESERVED1 2 0x11ff 2 0 4294967295 NC7_0 0 7 RESERVED_15_8 8 15 ixDPCSSYS_CR4_LANE2_DIG_ASIC_LANE_OVRD_IN 2 0x1200 5 0 4294967295 LANE_TX2RX_SER_LB 0 0 LANE_RX2TX_PAR_LB 1 1 EN 2 2 RX_ACJTAG_EN 3 3 RESERVED_15_4 4 15 ixDPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_0 2 0x1201 12 0 4294967295 REQ 0 0 REQ_OVRD_EN 1 1 PSTATE 2 3 PSTATE_OVRD_EN 4 4 RATE 5 7 RATE_OVRD_EN 8 8 WIDTH 9 10 WIDTH_OVRD_EN 11 11 MPLLB_SEL 12 12 MPLLB_SEL_OVRD_EN 13 13 DATA_EN 14 14 DATA_EN_OVRD_EN 15 15 ixDPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_1 2 0x1202 11 0 4294967295 NYQUIST_DATA 0 0 DISABLE 1 1 BEACON_EN 2 2 EN 3 3 TX_MAIN_CURSOR 4 9 MAIN_OVRD_EN 10 10 ASYNC_DRV_EN 11 11 ASYNC_DRV_OVRD_EN 12 12 TX_VREGDRV_BYP_OVRD 13 13 TX_VREGDRV_BYP_OVRD_EN 14 14 RESERVED_15_15 15 15 ixDPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_2 2 0x1203 6 0 4294967295 TX_PRE_CURSOR 0 5 PRE_OVRD_EN 6 6 TX_POST_CURSOR 7 12 POST_OVRD_EN 13 13 HDMIMODE_EN 14 14 HDMIMODE_ENABLE_OVRD_EN 15 15 ixDPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_3 2 0x1204 15 0 4294967295 CLK_RDY 0 0 CLK_RDY_OVRD_EN 1 1 DETECT_RX_REQ 2 2 DETECT_RX_REQ_OVRD_EN 3 3 INVERT 4 4 INVERT_OVRD_EN 5 5 LPD 6 6 LPD_OVRD_EN 7 7 TX_DC_COUP_EN 8 8 TX_DC_COUP_EN_OVRD_EN 9 9 PMA_EXTENDED_FIFO_EN 10 10 PMA_EXTENDED_FIFO_EN_OVRD_EN 11 11 TX_MPHY_MODE_EN 12 12 TX_MPHY_MODE_EN_OVRD_EN 13 13 RESERVED_15_14 14 15 ixDPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_4 2 0x1205 3 0 4294967295 RESET 0 0 RESET_OVRD_EN 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_OUT 2 0x1206 5 0 4294967295 TX_ACK 0 0 EN_TX_ACK 1 1 DETRX_RESULT 2 2 EN_DETRX_RESULT 3 3 RESERVED_15_4 4 15 ixDPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_0 2 0x1207 11 0 4294967295 REQ 0 0 REQ_OVRD_EN 1 1 DATA_EN 2 2 DATA_EN_OVRD_EN 3 3 PSTATE 4 5 PSTATE_OVRD_EN 6 6 RATE 7 8 RATE_OVRD_EN 9 9 WIDTH 10 11 WIDTH_OVRD_EN 12 12 RESERVED_15_13 13 15 ixDPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_1 2 0x1208 5 0 4294967295 RX_REF_LD_VAL_5_0 0 5 RX_CDR_VCO_LOWFREQ 6 6 EN 7 7 RX_REF_LD_VAL_6 8 8 RESERVED_15_9 9 15 ixDPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_2 2 0x1209 3 0 4294967295 RX_VCO_LD_VAL 0 12 EN 13 13 RESERVED_15_14 14 15 ixDPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_3 2 0x120a 11 0 4294967295 CDR_TRACK_EN 0 0 CDR_TRACK_EN_OVRD_EN 1 1 CDR_SSC_EN 2 2 CDR_SSC_EN_OVRD_EN 3 3 ALIGN_EN 4 4 ALIGN_EN_OVRD_EN 5 5 CLK_SHIFT 6 6 CLK_SHIFT_OVRD_EN 7 7 DISABLE 8 8 DISABLE_OVRD_EN 9 9 RESERVED_15_10 10 15 ixDPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_4 2 0x120b 11 0 4294967295 LPD 0 0 LPD_OVRD_EN 1 1 INVERT 2 2 INVERT_OVRD_EN 3 3 ADAPT_AFE_EN 4 4 ADAPT_DFE_EN 5 5 ADPT_OVRD_EN 6 6 TERM_EN 7 7 TERM_ACDC 8 8 TERM_OVRD_EN 9 9 RESERVED_15_10 10 15 ixDPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_5 2 0x120c 3 0 4294967295 RESET 0 0 RESET_OVRD_EN 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0 2 0x120d 4 0 4294967295 EQ_ATT_LVL 0 2 EQ_AFE_GAIN 3 6 RESERVED 7 10 EQ_CTLE_BOOST 11 15 ixDPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1 2 0x120e 3 0 4294967295 EQ_DFE_TAP2 0 6 EQ_DFE_TAP1 7 14 EQ_OVRD_EN 15 15 ixDPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_OUT_0 2 0x120f 9 0 4294967295 ACK 0 0 ACK_OVRD_EN 1 1 ADAPT_STS 2 3 ADAPT_STS_OVRD_EN 4 4 RX_ASYNC_DATA 5 5 RX_ASYNC_DATA_OVRD_EN 6 6 RX_SQ_WEAKKEEP_OUT 7 7 RX_SQ_WEAKKEEP_OUT_OVRD_EN 8 8 RESERVED_15_9 9 15 ixDPCSSYS_CR4_LANE2_DIG_ASIC_LANE_ASIC_IN 2 0x1210 3 0 4294967295 LANE_TX2RX_SER_LB 0 0 LANE_RX2TX_PAR_LB 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR4_LANE2_DIG_ASIC_TX_ASIC_IN_0 2 0x1211 12 0 4294967295 CLK_RDY 0 0 RESET 1 1 INVERT 2 2 DATA_EN 3 3 REQ 4 4 LPD 5 5 PSTATE 6 7 RATE 8 10 WIDTH 11 12 MPLLB_SEL 13 13 DETECT_RX_REQ 14 14 DISABLE 15 15 ixDPCSSYS_CR4_LANE2_DIG_ASIC_TX_ASIC_IN_1 2 0x1212 7 0 4294967295 BEACON_EN 0 0 TX_MAIN_CURSOR 1 6 TX_ASYNC_EN 7 7 TX_ASYNC_DATA 8 8 TX_ASYNC_DRV_EN 9 9 TX_VREGDRV_BYP 10 10 RESERVED_15_11 11 15 ixDPCSSYS_CR4_LANE2_DIG_ASIC_TX_ASIC_IN_2 2 0x1213 3 0 4294967295 TX_PRE_CURSOR 0 5 TX_POST_CURSOR 6 11 RESERVED_15_12 12 15 ixDPCSSYS_CR4_LANE2_DIG_ASIC_TX_ASIC_OUT 2 0x1214 3 0 4294967295 TX_ACK 0 0 DETRX_RESULT 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR4_LANE2_DIG_ASIC_RX_ASIC_IN_0 2 0x1215 13 0 4294967295 RESET 0 0 INVERT 1 1 DATA_EN 2 2 REQ 3 3 LPD 4 4 PSTATE 5 6 RATE 7 8 WIDTH 9 10 RESERVED 11 11 ADAPT_AFE_EN 12 12 ADAPT_DFE_EN 13 13 CDR_TRACK_EN 14 14 RESERVED_15_15 15 15 ixDPCSSYS_CR4_LANE2_DIG_ASIC_RX_ASIC_IN_1 2 0x1216 7 0 4294967295 CDR_SSC_EN 0 0 ALIGN_EN 1 1 CLK_SHIFT 2 2 DISABLE 3 3 RX_TERM_EN 4 4 RX_TERM_ACDC 5 5 RESERVED_15_6 6 15 ixDPCSSYS_CR4_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0 2 0x1217 4 0 4294967295 EQ_ATT_LVL 0 2 EQ_AFE_GAIN 3 6 RESERVED 7 10 EQ_CTLE_BOOST 11 15 ixDPCSSYS_CR4_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_1 2 0x1218 3 0 4294967295 EQ_DFE_TAP2 0 6 EQ_DFE_TAP1 7 14 RESERVED_15_15 15 15 ixDPCSSYS_CR4_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0 2 0x1219 3 0 4294967295 RX_CDR_VCO_LOWFREQ 0 0 RX_REF_LD_VAL 1 7 RESERVED_15_8 8 15 ixDPCSSYS_CR4_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1 2 0x121a 2 0 4294967295 RX_VCO_LD_VAL 0 12 RESERVED_15_13 13 15 ixDPCSSYS_CR4_LANE2_DIG_ASIC_RX_ASIC_OUT_0 2 0x121b 4 0 4294967295 ACK 0 0 VALID 1 1 ADAPT_STS 2 3 RESERVED_15_4 4 15 ixDPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_6 2 0x121c 10 0 4294967295 RX_PWM_CLK_SEL 0 1 RX_PWM_CLK_SEL_OVRD_EN 2 2 RX_TERM_LCC_ON 3 3 RX_TERM_LS_ON 4 4 RX_TERM_LS_LCC_ON_OVRD_EN 5 5 RX_TERM_CTL 6 7 RX_TERM_CTL_OVRD_EN 8 8 RX_PWM_EN 9 9 RX_PWM_EN_OVRD_EN 10 10 RESERVED_15_11 11 15 ixDPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_5 2 0x121d 15 0 4294967295 RPTR_EN_MASTER_LANE 0 0 RPTR_EN_MASTER_LANE_OVRD_EN 1 1 DIG_CLK_EN_OTHER_LANE 2 2 DIG_CLK_EN_OTHER_LANE_OVRD_EN 3 3 DIG_CLK_STATE_MASTER_LANE 4 4 DIG_CLK_STATE_MASTER_LANE_OVRD_EN 5 5 SHIFT_MASTER_LANE 6 6 SHIFT_MASTER_LANE_ORVD_EN 7 7 SHIFT_ACK_OTHER_LANE 8 8 SHIFT_ACK_OTHER_LANE_OVRD_EN 9 9 LANE_MASTER 10 10 LANE_MASTER_OVRD_IN_EN 11 11 TX_DWORD_CLK_SYNC_OVRD 12 12 TX_DWORD_CLK_SYNC_OVRD_EN 13 13 RESERVED_15_14 14 15 ixDPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_OUT_1 2 0x121e 11 0 4294967295 RPTR_EN_OUT 0 0 RPTR_EN_OUT_OVRD_EN 1 1 DIG_CLK_EN_OUT 2 2 DIG_CLK_EN_OUT_OVRD_EN 3 3 DIG_CLK_STATE_OUT 4 4 DIG_CLK_STATE_OUT_OVRD_EN 5 5 SHIFT_OUT 6 6 SHIFT_OUT_OVRD_EN 7 7 SHIFT_ACK_OUT 8 8 SHIFT_ACK_OUT_OVRD_EN 9 9 RESERVED_15_10 10 15 ixDPCSSYS_CR4_LANE2_DIG_ASIC_OCLA 2 0x121f 3 0 4294967295 RX_DWORD_OCLA_CLK_EN 0 0 RX_DWORD_OCLA_DATA_EN 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0 2 0x1220 11 0 4294967295 TX_P0_ANA_REFGEN_EN 0 0 TX_P0_ANA_VCM_HOLD 1 1 TX_P0_ANA_CLK_EN 2 2 TX_P0_ANA_WORD_CLK_EN 3 3 TX_P0_ANA_RESET 4 4 TX_P0_ANA_SERIAL_EN 5 5 TX_P0_DIG_CLK_EN 6 6 TX_P0_DATA_EN 7 7 TX_P0_ALLOW_RXDET 8 8 TX_P0_ANA_DCC_COMP_CAL_EN 9 9 RESERVED_15_10 10 15 ixDPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S 2 0x1221 11 0 4294967295 TX_P0S_ANA_REFGEN_EN 0 0 TX_P0S_ANA_VCM_HOLD 1 1 TX_P0S_ANA_CLK_EN 2 2 TX_P0S_ANA_WORD_CLK_EN 3 3 TX_P0S_ANA_RESET 4 4 TX_P0S_ANA_SERIAL_EN 5 5 TX_P0S_DIG_CLK_EN 6 6 TX_P0S_DATA_EN 7 7 TX_P0S_ALLOW_RXDET 8 8 TX_P0S_ANA_DCC_COMP_CAL_EN 9 9 RESERVED_15_10 10 15 ixDPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1 2 0x1222 11 0 4294967295 TX_P1_ANA_REFGEN_EN 0 0 TX_P1_ANA_VCM_HOLD 1 1 TX_P1_ANA_CLK_EN 2 2 TX_P1_ANA_WORD_CLK_EN 3 3 TX_P1_ANA_RESET 4 4 TX_P1_ANA_SERIAL_EN 5 5 TX_P1_DIG_CLK_EN 6 6 TX_P1_DATA_EN 7 7 TX_P1_ALLOW_RXDET 8 8 TX_P1_ANA_DCC_COMP_CAL_EN 9 9 RESERVED_15_10 10 15 ixDPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2 2 0x1223 12 0 4294967295 TX_P2_ANA_REFGEN_EN 0 0 TX_P2_ANA_VCM_HOLD 1 1 TX_P2_ANA_CLK_EN 2 2 TX_P2_ANA_WORD_CLK_EN 3 3 TX_P2_ANA_RESET 4 4 TX_P2_ANA_SERIAL_EN 5 5 TX_P2_DIG_CLK_EN 6 6 TX_P2_DATA_EN 7 7 TX_P2_ALLOW_RXDET 8 8 TX_P2_ALLOW_VBOOST 9 9 TX_P2_ANA_DCC_COMP_CAL_EN 10 10 RESERVED_15_11 11 15 ixDPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_0 2 0x1224 2 0 4294967295 TX_REFGEN_EN_TIME 0 7 TX_CLK_EN 8 15 ixDPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_1 2 0x1225 2 0 4294967295 TX_VCM_HOLD_TIME_14_0 0 14 SKIP_TX_VCM_HOLD_WAIT 15 15 ixDPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_2 2 0x1226 2 0 4294967295 TX_VBOOST_DIS_TIME_12_0 0 12 DTB_SEL 13 15 ixDPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_3 2 0x1227 3 0 4294967295 TX_VCM_HOLD_TIME_17_15 0 2 TX_VBOOST_DIS_TIME_13 3 3 RESERVED_15_4 4 15 ixDPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_4 2 0x1228 2 0 4294967295 TX_VCM_HOLD_GS_TIME 0 14 SKIP_TX_VCM_HOLD_GS_PULSE 15 15 ixDPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_5 2 0x1229 5 0 4294967295 TX_RXDET_TIME 0 9 FAST_TX_RXDET 10 10 TX_RESET_TIME 11 12 TX_SERIAL_EN_TIME 13 14 RESERVED_15_15 15 15 ixDPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_DCC_CR_BANK_ADDR 2 0x122a 1 0 4294967295 ADDR 0 15 ixDPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_DCC_CR_BANK_DATA 2 0x122b 1 0 4294967295 DATA 0 15 ixDPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_DCC_DAC_CTRL 2 0x122c 2 0 4294967295 CTRL 0 7 RESERVED_15_8 8 15 ixDPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_DCC_DAC_RANGE 2 0x122d 2 0 4294967295 CTRL 0 1 RESERVED_15_2 2 15 ixDPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_DCC_DAC_SEL 2 0x122e 6 0 4294967295 SEL 0 2 REQ 3 3 CTRL_UPD 4 4 RANGE_UPD 5 5 BIN_HOT 6 6 RESERVED_15_7 7 15 ixDPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_DCC_DAC_ACK 2 0x122f 2 0 4294967295 ACK 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_DCC_DAC_ADDR 2 0x1230 1 0 4294967295 ADDR 0 15 ixDPCSSYS_CR4_LANE2_DIG_TX_CLK_ALIGN_TX_CTL_0 2 0x1231 4 0 4294967295 TX_NUM_2UI_SHIFTS_16B_MODE 0 3 TX_NUM_2UI_SHIFTS_20B_MODE 4 7 TX_FIFO_BYPASS 8 8 RESERVED_15_9 9 15 ixDPCSSYS_CR4_LANE2_DIG_TX_LBERT_CTL 2 0x1232 4 0 4294967295 MODE 0 3 TRIGGER_ERR 4 4 PAT0 5 14 RESERVED_15_15 15 15 ixDPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0 2 0x1240 12 0 4294967295 RX_P0_ANA_AFE_EN 0 0 RX_P0_ANA_CLK_VREG_EN 1 1 RESERVED_1 2 2 RX_P0_ANA_CLK_EN 3 3 RESERVED_0 4 4 RX_P0_ANA_DESER_EN 5 5 RX_P0_ANA_CDR_EN 6 6 RX_P0_VCO_FREQ_RST 7 7 RX_P0_VCO_CAL_RST 8 8 RX_P0_VCO_CONTCAL_EN 9 9 RX_P0_DIG_CLK_EN 10 10 RESERVED_15_11 11 15 ixDPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S 2 0x1241 12 0 4294967295 RX_P0S_ANA_AFE_EN 0 0 RX_P0S_ANA_CLK_VREG_EN 1 1 RESERVED_2 2 2 RX_P0S_ANA_CLK_EN 3 3 RESERVED_4 4 4 RX_P0S_ANA_DESER_EN 5 5 RX_P0S_ANA_CDR_EN 6 6 RX_P0S_VCO_FREQ_RST 7 7 RX_P0S_VCO_CAL_RST 8 8 RX_P0S_VCO_CONTCAL_EN 9 9 RX_P0S_DIG_CLK_EN 10 10 RESERVED_15_11 11 15 ixDPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1 2 0x1242 12 0 4294967295 RX_P1_ANA_AFE_EN 0 0 RX_P1_ANA_CLK_VREG_EN 1 1 RESERVED_2 2 2 RX_P1_ANA_CLK_EN 3 3 RESERVED_4 4 4 RX_P1_ANA_DESER_EN 5 5 RX_P1_ANA_CDR_EN 6 6 RX_P1_VCO_FREQ_RST 7 7 RX_P1_VCO_CAL_RST 8 8 RX_P1_VCO_CONTCAL_EN 9 9 RX_P1_DIG_CLK_EN 10 10 RESERVED_15_11 11 15 ixDPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2 2 0x1243 12 0 4294967295 RX_P2_ANA_AFE_EN 0 0 RX_P2_ANA_CLK_VREG_EN 1 1 RESERVED_2 2 2 RX_P2_ANA_CLK_EN 3 3 RESERVED_4 4 4 RX_P2_ANA_DESER_EN 5 5 RX_P2_ANA_CDR_EN 6 6 RX_P2_VCO_FREQ_RST 7 7 RX_P2_VCO_CAL_RST 8 8 RX_P2_VCO_CONTCAL_EN 9 9 RX_P2_DIG_CLK_EN 10 10 RESERVED_15_11 11 15 ixDPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1 2 0x1245 5 0 4294967295 RX_AFE_EN_TIME 0 5 FAST_RX_AFE_EN 6 6 RX_VREG_EN_TIME 7 12 FAST_RX_VREG_EN 13 13 RESERVED_15_14 14 15 ixDPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_2 2 0x1246 4 0 4294967295 RX_CLK_EN_TIME 0 5 FAST_RX_CLK_EN 6 6 RX_FAST_START_TIME 7 10 RESERVED_15_11 11 15 ixDPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_3 2 0x1247 5 0 4294967295 RX_RATE_TIME 0 1 RSVD_3_7_2 2 7 RX_CDR_EN_TIME 8 11 RX_DESER_EN_TIME 12 13 RX_DESER_DIS_TIME 14 15 ixDPCSSYS_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0 2 0x1248 8 0 4294967295 INT_GAIN_CAL_FIXED_CNT 0 4 INT_GAIN_CAL_FIXED_CNT_EN 5 5 INT_GAIN_CAL_CNT_SHIFT 6 8 INT_GAIN_CAL_BOUNCE_CNT 9 11 DISABLE_BIN_HOLD 12 12 DISABLE_INT_GAIN_HOLD 13 13 DISABLE_COARSE_CALDONE 14 14 RESERVED_15_15 15 15 ixDPCSSYS_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1 2 0x1249 7 0 4294967295 RX_VCO_OVRD_SEL 0 0 RX_VCO_FREQ_RST 1 1 RX_VCO_CAL_RST 2 2 RX_VCO_CONTCAL_EN 3 3 DISABLE_INT_CAL_MODE 4 4 DPLL_CAL_UG 5 8 DTB_SEL 9 15 ixDPCSSYS_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2 2 0x124a 4 0 4294967295 FREQ_TUNE_START_VAL 0 9 FREQ_TUNE_CAL_STEPS 10 13 SKIP_RX_VCO_FREQ_TUNE_CAL 14 14 SKIP_RX_VCO_CAL 15 15 ixDPCSSYS_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0 2 0x124b 4 0 4294967295 RX_VCO_STARTUP_TIME 0 6 RX_VCO_UPDATE_TIME 7 10 RX_VCO_CNTR_PWRUP_TIME 11 14 FAST_RX_VCO_WAIT 15 15 ixDPCSSYS_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1 2 0x124c 2 0 4294967295 RX_VCO_CNTR_SETTLE_TIME 0 2 RESERVED_15_3 3 15 ixDPCSSYS_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0 2 0x124d 6 0 4294967295 RX_ANA_CDR_FREQ_TUNE 0 9 RX_ANA_VCO_CNTR_PD 10 10 RX_ANA_VCO_CNTR_EN 11 11 RX_ANA_CDR_STARTUP 12 12 RX_ANA_CDR_VCO_EN 13 13 RESERVED_15_14 14 15 ixDPCSSYS_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1 2 0x124e 7 0 4294967295 RX_VCO_FSM_STATE 0 3 RX_VCO_FREQ_RST 4 4 RX_VCO_CAL_RST 5 5 RX_VCO_CONTCAL_EN 6 6 RX_VCO_CAL_DONE 7 7 DPLL_FREQ_RST 8 8 RESERVED_15_9 9 15 ixDPCSSYS_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_2 2 0x124f 4 0 4294967295 VCO_CNTR_FINAL 0 12 VCOCLK_TOO_FAST 13 13 RX_VCO_CORRECT 14 14 RX_VCO_UP 15 15 ixDPCSSYS_CR4_LANE2_DIG_RX_RX_ALIGN_XAUI_COMM_MASK 2 0x1250 2 0 4294967295 XAUI_COMM_MASK 0 9 RESERVED_15_10 10 15 ixDPCSSYS_CR4_LANE2_DIG_RX_LBERT_CTL 2 0x1251 3 0 4294967295 MODE 0 3 SYNC 4 4 RESERVED_15_5 5 15 ixDPCSSYS_CR4_LANE2_DIG_RX_LBERT_ERR 2 0x1252 2 0 4294967295 COUNT 0 14 OV14 15 15 ixDPCSSYS_CR4_LANE2_DIG_RX_CDR_CDR_CTL_0 2 0x1253 7 0 4294967295 PHDET_EN 0 1 PHDET_EDGE 2 3 PHDET_POL 4 4 PHDET_EN_PR_MODE 5 5 ALWAYS_REALIGN 6 6 DTB_SEL 7 10 RESERVED_15_11 11 15 ixDPCSSYS_CR4_LANE2_DIG_RX_CDR_CDR_CTL_1 2 0x1254 2 0 4294967295 SSC_OFF_CNT0 0 9 SSC_OFF_CNT1 10 15 ixDPCSSYS_CR4_LANE2_DIG_RX_CDR_CDR_CTL_2 2 0x1255 2 0 4294967295 SSC_ON_CNT0 0 8 SSC_ON_CNT1 9 15 ixDPCSSYS_CR4_LANE2_DIG_RX_CDR_CDR_CTL_3 2 0x1256 6 0 4294967295 SSC_OFF_PHUG0 0 2 SSC_OFF_PHUG1 3 5 SSC_OFF_FRUG0 6 8 OVRD_DPLL_GAIN 9 9 PHUG_OVRD_VALUE 10 12 FRUG_OVRD_VALUE 13 15 ixDPCSSYS_CR4_LANE2_DIG_RX_CDR_CDR_CTL_4 2 0x1257 6 0 4294967295 SSC_OFF_FRUG1 0 2 SSC_ON_FRUG0 3 5 SSC_ON_FRUG1 6 8 SSC_ON_PHUG0 9 11 SSC_ON_PHUG1 12 14 RESERVED_15_15 15 15 ixDPCSSYS_CR4_LANE2_DIG_RX_CDR_STAT 2 0x1258 3 0 4294967295 PHUG_VALUE 0 2 FRUG_VALUE 3 5 RESERVED_15_6 6 15 ixDPCSSYS_CR4_LANE2_DIG_RX_DPLL_FREQ 2 0x1259 2 0 4294967295 VAL 0 13 RESERVED_15_14 14 15 ixDPCSSYS_CR4_LANE2_DIG_RX_DPLL_FREQ_BOUND_0 2 0x125a 3 0 4294967295 FREQ_BOUND_EN 0 0 UPPER_FREQ_BOUND 1 10 RESERVED_15_11 11 15 ixDPCSSYS_CR4_LANE2_DIG_RX_DPLL_FREQ_BOUND_1 2 0x125b 2 0 4294967295 LOWER_FREQ_BOUND 0 9 RESERVED_15_10 10 15 ixDPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_0 2 0x1260 4 0 4294967295 N_TOP_ASM1 0 9 N_TGG_ASM1 10 13 START_ASM1 14 14 ADPT_CLK_DIV4_EN 15 15 ixDPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1 2 0x1261 5 0 4294967295 N_WAIT_ASM1 0 6 FAST_AFE_DFE_SETTLE 7 7 CTLE_POLE_OVRD_VAL 8 10 CTLE_POLE_OVRD_EN 11 11 RESERVED_15_12 12 15 ixDPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_2 2 0x1262 3 0 4294967295 TGG_PTTRN_0 0 4 TGG_PTTRN_1 5 9 RESERVED_15_10 10 15 ixDPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3 2 0x1263 8 0 4294967295 CTLE_EN 0 4 VGA_EN 5 5 ATT_EN 6 6 DFE_EN 7 11 EYEHE_EN 12 12 EYEHO_EN 13 13 TGG_EN 14 14 ESL_TWICE_DSL 15 15 ixDPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_4 2 0x1264 4 0 4294967295 CTLE_TH 0 3 VGA_TH 4 7 DFE1_TH 8 11 DFE2_TH 12 15 ixDPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_5 2 0x1265 4 0 4294967295 DFE3_TH 0 3 DFE4_TH 4 7 DFE5_TH 8 11 TH_OFFSET 12 15 ixDPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6 2 0x1266 6 0 4294967295 CTLE_MU 0 2 VGA_MU 3 5 ATT_MU 6 8 VGA_SAT_CNT 9 11 VGA_SAT_CNT_STICKY 12 12 ATT_LOW_TH 13 15 ixDPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_7 2 0x1267 4 0 4294967295 VGA_MIN_SAT 0 4 VGA_LEV_HIGH 5 9 VGA_LEV_LOW 10 14 RESERVED_15_15 15 15 ixDPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8 2 0x1268 6 0 4294967295 DFE1_MU 0 2 DFE2_MU 3 5 DFE3_MU 6 8 DFE4_MU 9 11 DFE5_MU 12 14 RESERVED_15_15 15 15 ixDPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_9 2 0x1269 2 0 4294967295 ERR_SLE_ADPT_INIT 0 7 ERR_SLO_ADPT_INIT 8 15 ixDPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG 2 0x126a 6 0 4294967295 RST_ADPT_ATT 0 0 RST_ADPT_VGA 1 1 RST_ADPT_CTLE_BOOST 2 2 RST_ADPT_CTLE_POLE 3 3 RST_ADPT_TAP1 4 4 RESERVED_15_5 5 15 ixDPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ATT_STATUS 2 0x126b 3 0 4294967295 ATT_ADPT_CODE 0 7 ASM1_DON 8 8 RESERVED_15_9 9 15 ixDPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_VGA_STATUS 2 0x126c 3 0 4294967295 VGA_ADPT_CODE 0 9 ASM1_DONE 10 10 RESERVED_15_11 11 15 ixDPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_CTLE_STATUS 2 0x126d 4 0 4294967295 CTLE_BOOST_ADPT_CODE 0 9 CTLE_POLE_ADPT_CODE 10 12 ASM1_DONE 13 13 RESERVED_15_14 14 15 ixDPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_DFE_TAP1_STATUS 2 0x126e 3 0 4294967295 DFE_TAP1_ADPT_CODE 0 12 ASM1_DONE 13 13 RESERVED_15_14 14 15 ixDPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_DFE_TAP2_STATUS 2 0x126f 3 0 4294967295 DFE_TAP2_ADPT_CODE 0 11 ASM1_DONE 12 12 RESERVED_15_13 13 15 ixDPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_DFE_TAP3_STATUS 2 0x1270 3 0 4294967295 DFE_TAP3_ADPT_CODE 0 11 ASM1_DONE 12 12 RESERVED_15_13 13 15 ixDPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_DFE_TAP4_STATUS 2 0x1271 3 0 4294967295 DFE_TAP4_ADPT_CODE 0 11 ASM1_DONE 12 12 RESERVED_15_13 13 15 ixDPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_DFE_TAP5_STATUS 2 0x1272 3 0 4294967295 DFE_TAP5_ADPT_CODE 0 11 ASM1_DONE 12 12 RESERVED_15_13 13 15 ixDPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_DFE_DATA_EVEN_VDAC_OFST 2 0x1273 2 0 4294967295 DFE_DATA_EVEN_VDAC_OFST 0 7 RESERVED_15_8 8 15 ixDPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_DFE_DATA_ODD_VDAC_OFST 2 0x1274 2 0 4294967295 DFE_DATA_ODD_VDAC_OFST 0 7 RESERVED_15_8 8 15 ixDPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN 2 0x1275 2 0 4294967295 RX_ANA_SLICER_CTRL_E 0 3 RESERVED_15_4 4 15 ixDPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD 2 0x1276 2 0 4294967295 RX_ANA_SLICER_CTRL_O 0 3 RESERVED_15_4 4 15 ixDPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST 2 0x1277 2 0 4294967295 DFE_ERROR_EVEN_VDAC_OFST 0 7 RESERVED_15_8 8 15 ixDPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST 2 0x1278 2 0 4294967295 DFE_ERROR_ODD_VDAC_OFST 0 7 RESERVED_15_8 8 15 ixDPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL 2 0x1279 2 0 4294967295 E_SLO_LVL 0 7 E_SLE_LVL 8 15 ixDPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_RESET 2 0x127a 2 0 4294967295 RESET_ASM1 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1 2 0x127b 4 0 4294967295 DFE_T1_IDAC 0 4 DFE_T2_IDAC 5 9 DCC_START_IDAC 10 14 RESERVED_15_15 15 15 ixDPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2 2 0x127c 3 0 4294967295 DFE_DAT_EVEN_VDAC 0 4 DFE_DAT_ODD_VDAC 5 9 RESERVED_15_10 10 15 ixDPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3 2 0x127d 3 0 4294967295 DFE_ERR_EVEN_VDAC 0 4 DFE_ERR_ODD_VDAC 5 9 RESERVED_15_10 10 15 ixDPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_CR_BANK_ADDR 2 0x127e 1 0 4294967295 ADDR 0 15 ixDPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_CR_BANK_DATA 2 0x127f 1 0 4294967295 DATA 0 15 ixDPCSSYS_CR4_LANE2_DIG_RX_STAT_LD_VAL_1 2 0x1280 2 0 4294967295 SC1_LD_VAL 0 14 SC1_START 15 15 ixDPCSSYS_CR4_LANE2_DIG_RX_STAT_DATA_MSK 2 0x1281 1 0 4294967295 DATA_MSK_15_0 0 15 ixDPCSSYS_CR4_LANE2_DIG_RX_STAT_MATCH_CTL0 2 0x1282 4 0 4294967295 PTTRN_MSK_CR1A_4_0 0 4 PTTRN_CR1A_4_0 5 9 DATA_MSK_19_16 10 13 SCOPE_DLY 14 15 ixDPCSSYS_CR4_LANE2_DIG_RX_STAT_MATCH_CTL1 2 0x1283 5 0 4294967295 PTTRN_CR1B_EN 0 0 PTTRN_MSK_CR1B_4_0 1 5 PTTRN_CR1B_4_0 6 10 PTTRN_CR1A_ADPT_EN 11 11 RESERVED_15_12 12 15 ixDPCSSYS_CR4_LANE2_DIG_RX_STAT_STAT_CTL0 2 0x1284 10 0 4294967295 RESERVED_0 0 0 CORR_SHFT_SEL_VGA 1 1 CORR_SHFT_SEL 2 2 CORR_SRC_SEL 3 4 CORR_MODE_EN 5 5 STAT_SHFT_SEL 6 9 STAT_SRC_SEL 10 12 STAT_RXCLK_SEL 13 13 SC_TIMER_MODE 14 14 SKIP_EN 15 15 ixDPCSSYS_CR4_LANE2_DIG_RX_STAT_STAT_CTL1 2 0x1285 13 0 4294967295 STAT_CNT_0_EN 0 0 STAT_CNT_1_EN 1 1 STAT_CNT_2_EN 2 2 STAT_CNT_3_EN 3 3 STAT_CNT_4_EN 4 4 STAT_CNT_5_EN 5 5 STAT_CNT_6_EN 6 6 RESERVED_8_7 7 8 SC_PAUSE 9 9 STAT_CLK_EN 10 10 DATA_DLY_SEL 11 12 VLD_LOSS_CLR 13 13 VLD_CTL 14 15 ixDPCSSYS_CR4_LANE2_DIG_RX_STAT_SMPL_CNT1 2 0x1286 2 0 4294967295 SMPL_CNT1 0 14 SMPL_CNT1_DONE 15 15 ixDPCSSYS_CR4_LANE2_DIG_RX_STAT_STAT_CNT_0 2 0x1287 2 0 4294967295 STAT_CNT_0 0 14 SMPL_CNT1_DONE 15 15 ixDPCSSYS_CR4_LANE2_DIG_RX_STAT_STAT_CNT_1 2 0x1288 2 0 4294967295 STAT_CNT_1 0 14 SMPL_CNT1_DONE 15 15 ixDPCSSYS_CR4_LANE2_DIG_RX_STAT_STAT_CNT_2 2 0x1289 2 0 4294967295 STAT_CNT_2 0 14 SMPL_CNT1_DONE 15 15 ixDPCSSYS_CR4_LANE2_DIG_RX_STAT_STAT_CNT_3 2 0x128a 2 0 4294967295 STAT_CNT_3 0 14 SMPL_CNT1_DONE 15 15 ixDPCSSYS_CR4_LANE2_DIG_RX_STAT_STAT_CNT_4 2 0x128b 2 0 4294967295 STAT_CNT_4 0 14 SMPL_CNT1_DONE 15 15 ixDPCSSYS_CR4_LANE2_DIG_RX_STAT_STAT_CNT_5 2 0x128c 2 0 4294967295 STAT_CNT_5 0 14 SMPL_CNT1_DONE 15 15 ixDPCSSYS_CR4_LANE2_DIG_RX_STAT_STAT_CNT_6 2 0x128d 2 0 4294967295 STAT_CNT_6 0 14 SMPL_CNT1_DONE 15 15 ixDPCSSYS_CR4_LANE2_DIG_RX_STAT_CAL_COMP_CLK_CTL 2 0x128e 3 0 4294967295 PRECHRGE_CNT 0 2 REF_DIV_CNT 3 5 RESERVED_15_6 6 15 ixDPCSSYS_CR4_LANE2_DIG_RX_STAT_MATCH_CTL2 2 0x128f 2 0 4294967295 PTTRN_CR1A_19_5 0 14 RESERVED_15_15 15 15 ixDPCSSYS_CR4_LANE2_DIG_RX_STAT_MATCH_CTL3 2 0x1290 2 0 4294967295 PTTRN_MSK_CR1A_19_5 0 14 RESERVED_15_15 15 15 ixDPCSSYS_CR4_LANE2_DIG_RX_STAT_MATCH_CTL4 2 0x1291 2 0 4294967295 PTTRN_CR1B_19_5 0 14 RESERVED_15_15 15 15 ixDPCSSYS_CR4_LANE2_DIG_RX_STAT_MATCH_CTL5 2 0x1292 2 0 4294967295 PTTRN_MSK_CR1B_19_5 0 14 RESERVED_15_15 15 15 ixDPCSSYS_CR4_LANE2_DIG_RX_STAT_STAT_CTL2 2 0x1293 4 0 4294967295 DATA_DLY_SEL_2 0 0 SCOPE_DLY_2 1 1 DISABLE_SAMPLE_COUNT 2 2 RESERVED_15_3 3 15 ixDPCSSYS_CR4_LANE2_DIG_RX_STAT_STAT_STOP 2 0x1294 2 0 4294967295 SC1_STOP 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR4_LANE2_DIG_MPHY_RX_PWM_CTL 2 0x1295 3 0 4294967295 RX_PWM_POL 0 0 RX_PWM_DATA_POL 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR4_LANE2_DIG_MPHY_RX_TERM_LS_CTL 2 0x1296 2 0 4294967295 RX_TERM_LCC_CNT 0 2 RESERVED_15_3 3 15 ixDPCSSYS_CR4_LANE2_DIG_MPHY_RX_ANA_PWM_CLK_STABLE_CNT 2 0x1297 2 0 4294967295 PWM_CLK_STABLE_CNT 0 3 RESERVED_15_4 4 15 ixDPCSSYS_CR4_LANE2_DIG_ANA_TX_OVRD_OUT 2 0x12a0 15 0 4294967295 TX_ANA_CLK_SHIFT 0 0 TX_ANA_DATA_EN 1 1 TX_ANA_REFGEN_EN 2 2 TX_ANA_VCM_HOLD 3 3 TX_ANA_CLK_EN 4 4 TX_ANA_WORD_CLK_EN 5 5 TX_ANA_MPLLA_CLK_EN 6 6 TX_ANA_MPLLB_CLK_EN 7 7 TX_ANA_RESET 8 8 TX_ANA_SERIAL_EN 9 9 TX_ANA_DATA_RATE 10 11 RESERVED 12 12 TX_DIV4_EN 13 13 TX_RXDET_EN 14 14 TX_OVRD_EN 15 15 ixDPCSSYS_CR4_LANE2_DIG_ANA_TX_TERM_CODE_OVRD_OUT 2 0x12a1 5 0 4294967295 TX_TERM_CODE 0 9 TX_TERM_OVRD_EN 10 10 TX_DRV_SRC 11 12 TX_DRV_SRC_OVRD_EN 13 13 RESERVED_15_14 14 15 ixDPCSSYS_CR4_LANE2_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT 2 0x12a2 3 0 4294967295 TX_TERM_DN_CLK 0 0 TX_TERM_CLK_SELF_CLEAR_DISABLE 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR4_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_0 2 0x12a3 3 0 4294967295 TX_ANA_LOAD_CLK 0 0 TX_ANA_CTRL_LEG_PULL_EN_13_0 1 14 TX_EQ_OVRD_EN 15 15 ixDPCSSYS_CR4_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_1 2 0x12a4 2 0 4294967295 TX_ANA_CTRL_LEG_PULL_EN_19_14 0 5 RESERVED_15_6 6 15 ixDPCSSYS_CR4_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_2 2 0x12a5 4 0 4294967295 RESERVED 0 2 TX_ANA_CTRL_EQ_MUX_SEL 3 6 TX_ANA_CTRL_PRE 7 12 RESERVED_15_13 13 15 ixDPCSSYS_CR4_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_3 2 0x12a6 2 0 4294967295 TX_ANA_CTRL_POST 0 8 RESERVED_15_9 9 15 ixDPCSSYS_CR4_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_4 2 0x12a7 1 0 4294967295 TX_ANA_CTRL_LEG_PULL_DIR_19_4 0 15 ixDPCSSYS_CR4_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_5 2 0x12a8 2 0 4294967295 TX_ANA_CTRL_LEG_PULL_DIR_3_0 0 3 RESERVED_15_4 4 15 ixDPCSSYS_CR4_LANE2_DIG_ANA_RX_CTL_OVRD_OUT 2 0x12a9 9 0 4294967295 RESERVED 0 0 RX_ANA_DATA_RATE 1 2 RX_ANA_WORD_CLK_EN 3 3 RX_ANA_DIV4_EN 4 4 RX_ANA_DFE_TAPS_EN 5 5 RX_ANA_ADAPTATION_EN 6 6 RX_LBK_CLK_EN 7 7 RX_CTL_OVRD_EN 8 8 RESERVED_15_9 9 15 ixDPCSSYS_CR4_LANE2_DIG_ANA_RX_PWR_OVRD_OUT 2 0x12aa 9 0 4294967295 RX_ANA_AFE_EN 0 0 RX_ANA_CLK_VREG_EN 1 1 RX_ANA_CLK_DCC_EN 2 2 RX_ANA_CLK_EN 3 3 RX_ANA_CDR_EN 4 4 RX_ANA_DESERIAL_EN 5 5 RX_PWR_OVRD_EN 6 6 RX_ANA_FAST_START 7 7 RESERVED_15_8 8 15 ixDPCSSYS_CR4_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0 2 0x12ab 7 0 4294967295 RX_ANA_CDR_VCO_EN 0 0 RX_ANA_CDR_STARTUP 1 1 RX_VCO_CDR_OVRD_EN 2 2 RX_ANA_CDR_FREQ_TUNE 3 12 RX_ANA_VCO_CNTR_EN 13 13 RX_ANA_VCO_CNTR_CLK 14 14 RX_CDR_FREQ_TUNE_OVRD_EN 15 15 ixDPCSSYS_CR4_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_1 2 0x12ac 3 0 4294967295 RX_ANA_CDR_VCO_LOWFREQ 0 0 RX_ANA_VCO_CNTR_PD 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR4_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_2 2 0x12ad 3 0 4294967295 RX_ANA_CDR_FREQ_TUNE_CLK 0 0 CDR_FREQ_TUNE_CLK_SELF_CLEAR_DISABLE 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR4_LANE2_DIG_ANA_RX_CAL 2 0x12ae 7 0 4294967295 RX_ANA_CAL_MUXA_SEL 0 4 RX_ANA_CAL_MUXB_SEL 5 9 RX_ANA_CAL_LPFBYP_EN 10 10 RESERVED 11 11 RX_ANA_SLICER_CAL_EN 12 12 RX_ANA_CAL_MODE 13 14 RX_ANA_CAL_COMP_EN 15 15 ixDPCSSYS_CR4_LANE2_DIG_ANA_RX_DAC_CTRL 2 0x12af 2 0 4294967295 RX_ANA_CAL_DAC_CTRL 0 7 RESERVED_15_8 8 15 ixDPCSSYS_CR4_LANE2_DIG_ANA_RX_DAC_CTRL_OVRD 2 0x12b0 2 0 4294967295 RX_CAL_DAC_CTRL_OVRD 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR4_LANE2_DIG_ANA_RX_DAC_CTRL_SEL 2 0x12b1 2 0 4294967295 RX_ANA_CAL_DAC_CTRL_SEL 0 4 RESERVED_15_5 5 15 ixDPCSSYS_CR4_LANE2_DIG_ANA_RX_AFE_ATT_VGA 2 0x12b2 5 0 4294967295 RX_ANA_AFE_ATT_LVL 0 2 RX_ANA_AFE_GAIN 3 6 RESERVED 7 10 RX_AFE_OVRD_EN 11 11 RESERVED_15_12 12 15 ixDPCSSYS_CR4_LANE2_DIG_ANA_RX_AFE_CTLE 2 0x12b3 3 0 4294967295 RESERVED 0 2 RX_ANA_AFE_CTLE_BOOST 3 7 RESERVED_15_8 8 15 ixDPCSSYS_CR4_LANE2_DIG_ANA_RX_SCOPE 2 0x12b4 7 0 4294967295 RX_ANA_SCOPE_EN 0 0 RX_ANA_SCOPE_SEL 1 2 RX_ANA_SCOPE_PH_CLK 3 3 RX_ANA_SCOPE_PHASE 4 11 RX_ANA_SCOPE_CLK_EN 12 12 RX_SCOPE_SELF_CLEAR_DISABLE 13 13 RESERVED_15_14 14 15 ixDPCSSYS_CR4_LANE2_DIG_ANA_RX_SLICER_CTRL 2 0x12b5 4 0 4294967295 RX_ANA_SLICER_CTRL_E 0 3 RX_ANA_SLICER_CTRL_O 4 7 RX_ANA_SLICER_CTRL_OVRD_EN 8 8 RESERVED_15_9 9 15 ixDPCSSYS_CR4_LANE2_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST 2 0x12b6 2 0 4294967295 RX_ANA_IQ_PHASE_ADJUST 0 6 RESERVED_15_7 7 15 ixDPCSSYS_CR4_LANE2_DIG_ANA_RX_ANA_IQ_SENSE_EN 2 0x12b7 2 0 4294967295 RX_ANA_IQ_SENSE_EN 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR4_LANE2_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN 2 0x12b8 3 0 4294967295 RX_ANA_CAL_DAC_CTRL_EN 0 0 DAC_CTRL_SELF_CLEAR_DISABLE 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR4_LANE2_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE 2 0x12b9 3 0 4294967295 RX_ANA_AFE_UPDATE_EN 0 0 AFE_UPDATE_SELF_CLEAR_DISABLE 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR4_LANE2_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK 2 0x12ba 3 0 4294967295 RX_ANA_IQ_PHASE_ADJUST_CLK 0 0 PHASE_ADJUST_SELF_CLEAR_DISABLE 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR4_LANE2_DIG_ANA_STATUS_0 2 0x12bb 9 0 4294967295 TX_ANA_CLK_SHIFT_ACK 0 0 TX_ANA_RXDETP_RESULT 1 1 TX_ANA_RXDETM_RESULT 2 2 TX_ANA_LOOPBACK_EN 3 3 TX_ANA_CLK_LB_EN 4 4 RX_ANA_CAL_RESULT 5 5 RX_ANA_SCOPE_DATA 6 6 TX_ANA_DCC_CAL_RESULT 7 7 TX_ANA_CTRL_EQ_MUX 8 15 ixDPCSSYS_CR4_LANE2_DIG_ANA_STATUS_1 2 0x12bc 2 0 4294967295 RX_ANA_VCO_CNTR 0 12 RESERVED_15_13 13 15 ixDPCSSYS_CR4_LANE2_DIG_ANA_RX_TERM_CODE_OVRD_OUT 2 0x12bd 3 0 4294967295 RX_TERM_CODE 0 5 RX_TERM_OVRD_EN 6 6 RESERVED_15_7 7 15 ixDPCSSYS_CR4_LANE2_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT 2 0x12be 3 0 4294967295 RX_TERM_CLK 0 0 RX_TERM_CLK_SELF_CLEAR_DISABLE 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR4_LANE2_DIG_ANA_MPHY_OVRD_OUT 2 0x12bf 9 0 4294967295 RX_ANA_SQ_CTRL_TRESH 0 2 RX_ANA_SQ_CTRL_TRESH_OVRD_EN 3 3 RX_ANA_SQ_CTRL_RESP 4 5 RX_ANA_SQ_CTRL_RESP_OVRD_EN 6 6 RX_ANA_PWM_EN 7 7 RX_ANA_PWM_EN_OVRD_EN 8 8 RX_ANA_PWM_CLK_SEL 9 10 RX_ANA_PWM_CLK_SEL_OVRD_EN 11 11 RESERVED_15_12 12 15 ixDPCSSYS_CR4_LANE2_DIG_ANA_SIGDET_OVRD_OUT_1 2 0x12c0 7 0 4294967295 RX_ANA_SIGDET_HF_THRESH 0 2 RX_ANA_SIGDET_HF_THRESH_OVRD_EN 3 3 RX_ANA_SIGDET_HF_CAL_TUNE 4 9 RX_ANA_SIGDET_CAL_TUNE_OVRD_EN 10 10 RX_ANA_SIGDET_CAL_EN 11 11 RX_ANA_SIGDET_CAL_EN_OVRD_EN 12 12 RESERVED_15_13 13 15 ixDPCSSYS_CR4_LANE2_DIG_ANA_SIGDET_OVRD_OUT_2 2 0x12c1 7 0 4294967295 RX_ANA_SIGDET_LF_THRESH 0 2 RX_ANA_SIGDET_LF_THRESH_OVRD_EN 3 3 RX_ANA_SIGDET_LF_FILTER_EN 4 4 RX_ANA_SIGDET_LF_FILTER_EN_OVRD_EN 5 5 RX_ANA_SIGDET_CAL_TUNE 6 11 RX_ANA_SIGDET_CAL_TUNE_OVRD_EN 12 12 RESERVED_15_13 13 15 ixDPCSSYS_CR4_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT 2 0x12c2 8 0 4294967295 TX_ANA_DCC_CAL_RANGE 0 1 TX_ANA_DCC_CAL_RANGE_OVRD_EN 2 2 TX_ANA_DCC_CAL_COMP_EN 3 3 TX_ANA_DCC_CAL_COMP_EN_OVRD_EN 4 4 TX_ANA_DCC_CAL_CTRL 5 12 TX_ANA_DCC_CAL_CTRL_OVRD_EN 13 13 TX_ANA_DCC_CAL_CTRL_EN 14 14 TX_ANA_DCC_CAL_CTRL_EN_OVRD_EN 15 15 ixDPCSSYS_CR4_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2 2 0x12c3 5 0 4294967295 TX_ANA_DCC_CAL_CTRL_SEL 0 2 TX_ANA_DCC_CAL_CTRL_SEL_OVRD_EN 3 3 TX_ANA_DCC_CLK_COMP 4 4 TX_ANA_DCC_CLK_COMP_OVRD_EN 5 5 RESERVED_15_6 6 15 ixDPCSSYS_CR4_LANE2_DIG_ANA_TX_OVRD_OUT_2 2 0x12c4 6 0 4294967295 TX_ANA_FAST_START 0 0 TX_ANA_FAST_START_OVRD_EN 1 1 TX_CLK_LB_EN 2 2 TX_CLK_LB_EN_OVRD_EN 3 3 TX_ACJTAG_EN 4 4 RESERVED_15_5 5 15 ixDPCSSYS_CR4_LANE2_ANA_TX_OVRD_MEAS 2 0x12e0 9 0 4294967295 OVRD_CLK_SHIFT 0 0 CLK_SHIFT_REG 0 0 MEAS_ATB_CAL_MUX 0 0 MEAS_ATB_CAL_COMP 0 0 OVRD_VCM_HOLD 0 0 VCM_HOLD_REG 0 0 PULL_UP_REG 0 0 PULL_DN_REG 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR4_LANE2_ANA_TX_PWR_OVRD 2 0x12e1 9 0 4294967295 OVRD_TX_LOOPBACK 0 0 LOOPBACK_EN_REG 0 0 REFGEN_EN_REG 0 0 CLK_DIV_EN_REG 0 0 DATA_EN_REG_INT 0 0 CLK_EN_REG 0 0 SERIAL_EN_REG 0 0 OVRD_EN 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR4_LANE2_ANA_TX_ALT_BUS 2 0x12e2 6 0 4294967295 DRV_SOURCE_REG 0 0 OVRD_ALT_BUS 0 0 ATB_S_ENABLE 0 0 TX_ALT_RINGO 0 0 JTAG_DATA_REG 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR4_LANE2_ANA_TX_ATB1 2 0x12e3 9 0 4294967295 MEAS_ATB_GD 0 0 MEAS_ATB_VDDH 0 0 OVERRIDE_RXDETREF 0 0 MEAS_ATB_VPTX 0 0 OVERRIDE_REGREF 0 0 MEAS_ATB_VREG_DRV 0 0 MEAS_ATB_VREG 0 0 MEAS_ATB_VPH_HALF 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR4_LANE2_ANA_TX_ATB2 2 0x12e4 9 0 4294967295 MEAS_ATB_VCM 0 0 MEAS_ATB_CAL_VDAC_CM 0 0 MEAS_ATB_CAL_VDAC_DIFF 0 0 MEAS_ATB_TXM 0 0 MEAS_ATB_TXP 0 0 MEAS_ATB_RXDETREF 0 0 LFPS_HIGH_PRIORITY 0 0 OSC_DIV4_EN 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR4_LANE2_ANA_TX_DCC_DAC 2 0x12e5 2 0 4294967295 DCC_DAC_REG 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR4_LANE2_ANA_TX_DCC_CTRL1 2 0x12e6 7 0 4294967295 NC0 0 0 OVRD_DCC_DAC_CTRL_SEL 0 0 DCC_DAC_CTRL_SEL_REG 0 0 OVRD_DCC_DAC_CTRL_EN 0 0 DCC_DAC_CTRL_EN_REG 0 0 OVRD_DCC_DAC_REG 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR4_LANE2_ANA_TX_TERM_CODE 2 0x12e7 2 0 4294967295 TERM_CODE_REG_70 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR4_LANE2_ANA_TX_TERM_CODE_CTRL 2 0x12e8 8 0 4294967295 VREG_BOOST_1 0 0 OVRD_UPDATE_TERM 0 0 UPDATE_TERM_REG 0 0 OVRD_RESET_TERM 0 0 RESET_TERM_REG 0 0 OVRD_TERM_CODE 0 0 TERM_CODE_REG_98 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR4_LANE2_ANA_TX_OVRD_CLK 2 0x12e9 9 0 4294967295 VREG_BOOST_0 0 0 CLK_LB_EN_REG 0 0 OVRD_LB_EN 0 0 MPLLB_CLK_EN_REG 0 0 MPLLA_CLK_EN_REG 0 0 OVRD_MPLLAB_EN 0 0 WORD_CLK_EN_REG 0 0 OVRD_WORD_CLK_EN 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR4_LANE2_ANA_TX_MISC1 2 0x12ea 8 0 4294967295 MEAS_ATB_CAL_CLK_ALIGN 0 0 OVRD_DCC_DAC_CTRL_RANGE 0 0 DCC_DAC_CTRL_RANGE_REG 0 0 OVRD_VREF_SEL 0 0 VREF_SEL_REG 0 0 FORCE_ATB_TXM 0 0 FORCE_ATB_TXP 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR4_LANE2_ANA_TX_MISC2 2 0x12eb 8 0 4294967295 TX_PEAKING_LVL 0 0 VREG_CP_GAIN_CTRL 0 0 TX_SLEW_EN 0 0 EN_INV_POST 0 0 EN_INV_PRE 0 0 TX_VREG_EN_BYP 0 0 TX_VDRIVER_PULLDN_EN 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR4_LANE2_ANA_TX_MISC3 2 0x12ec 4 0 4294967295 TX_VREG_OVRD_RING_CTRL 0 0 TX_DCC_LOWV 0 0 NC7_2 2 7 RESERVED_15_8 8 15 ixDPCSSYS_CR4_LANE2_ANA_TX_RESERVED2 2 0x12ed 2 0 4294967295 NC7_0 0 7 RESERVED_15_8 8 15 ixDPCSSYS_CR4_LANE2_ANA_TX_RESERVED3 2 0x12ee 2 0 4294967295 NC7_0 0 7 RESERVED_15_8 8 15 ixDPCSSYS_CR4_LANE2_ANA_TX_RESERVED4 2 0x12ef 2 0 4294967295 NC7_0 0 7 RESERVED_15_8 8 15 ixDPCSSYS_CR4_LANE2_ANA_RX_CLK_1 2 0x12f0 8 0 4294967295 CDR_VCO_STARTUP_CODE 0 0 CDR_VCO_TEMP_COMP_EN 0 0 CDR_VCO_USE_UNCAL_BIAS 0 0 OVERRIDE_CDR_EN 0 0 OVRD_CLK_EN 0 0 CLK_EN_REG 0 0 NC7 7 7 RESERVED_15_8 8 15 ixDPCSSYS_CR4_LANE2_ANA_RX_CLK_2 2 0x12f1 5 0 4294967295 IQ_PHASE_ADJUST_REG 0 0 OVRD_IQ_PHASE_ADJUST 0 0 RX_LOOPBACK_CLK_REG 0 0 OVRD_RX_LOOPBACK_CLK 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR4_LANE2_ANA_RX_CDR_DES 2 0x12f2 7 0 4294967295 OVRD_WORD_CLK_EN 0 0 WORD_CLK_EN_REG 0 0 PHDET_ODD_REG 0 0 PHDET_EVEN_REG 0 0 SIGDET_VREF_EXT_EN 0 0 NC7_5 5 7 RESERVED_15_8 8 15 ixDPCSSYS_CR4_LANE2_ANA_RX_SLC_CTRL 2 0x12f3 3 0 4294967295 RX_SLICER_CTRL_O_REG 0 0 RX_SLICER_CTRL_E_REG 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR4_LANE2_ANA_RX_PWR_CTRL1 2 0x12f4 8 0 4294967295 OVRD_ACJT_EN 0 0 ACJT_EN_REG 0 0 OVRD_AFE_EN 0 0 AFE_EN_REG 0 0 AFE_CM_SEL 0 0 ATT_PULLDN_EN 0 0 NC7_7 7 7 RESERVED_15_8 8 15 ixDPCSSYS_CR4_LANE2_ANA_RX_PWR_CTRL2 2 0x12f5 9 0 4294967295 OVRD_DFE_EN 0 0 DFE_EN_REG 0 0 OVRD_DESERIAL_EN 0 0 DESERIAL_EN_REG 0 0 OVRD_LOOPBACK_EN 0 0 LOOPBACK_EN_REG 0 0 OVRD_FAST_START 0 0 FAST_START_REG 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR4_LANE2_ANA_RX_SQ 2 0x12f6 7 0 4294967295 SQ_CTRL_RESP_REG 0 0 OVRD_SQ_CTRL_RESP 0 0 NC4_3 3 4 SQ_CTRL_TRESH_REG 0 0 OVRD_SQ_CTRL_TRESH 0 0 AFE_LOOPBACK_SEL 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR4_LANE2_ANA_RX_CAL1 2 0x12f7 5 0 4294967295 DFE_TAPS_EN_REG 0 0 OVRD_DFE_TAPS_EN 0 0 CAL_MUXB_SEL_REG 0 0 OVRD_CAL_MUXB_SEL 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR4_LANE2_ANA_RX_CAL2 2 0x12f8 5 0 4294967295 AFE_PD_EQ_OFFSET 0 0 CAL_IDACS_USE_UNCAL 0 0 CAL_MUXA_SEL_REG 0 0 OVRD_CAL_MUXA_SEL 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR4_LANE2_ANA_RX_ATB_REGREF 2 0x12f9 8 0 4294967295 OVERRIDE_REGREF_VCO 0 0 OVERRIDE_REGREF_CLK 0 0 OVERRIDE_REGREF_IQC 0 0 BOOST_REGREF_IQC 0 0 OVRD_RX_SLICER_CTRL 0 0 OVRD_RX_TERM_AC_DCZ 0 0 RX_TERM_AC_DCZ_REG 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR4_LANE2_ANA_RX_ATB_MEAS1 2 0x12fa 9 0 4294967295 MASTER_ATB_EN 0 0 MEAS_ATB_VP 0 0 MEAS_ATB_GD 0 0 MEAS_ATB_VREG_VCO 0 0 MEAS_ATB_VREG_CLK 0 0 MEAS_ATB_VREG_IQC 0 0 REGS_FB_DIV_CTRL 0 0 RX_VREG_CLK_BYPASS 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR4_LANE2_ANA_RX_ATB_MEAS2 2 0x12fb 2 0 4294967295 MEAS_ATB_RX 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR4_LANE2_ANA_RX_ATB_MEAS3 2 0x12fc 7 0 4294967295 MEAS_ATB_CDR_VCO_GD 0 0 MEAS_ATB_CDR_VCO_VIREF_200U 0 0 MEAS_ATB_VIBIAS_CDR_VCO 0 0 MEAS_ATB_CDR_VCO_VOSC 0 0 MEAS_ATB_CAL_MUX 0 0 RX_VREG_OVERRIDE_RING_CTRL 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR4_LANE2_ANA_RX_ATB_MEAS4 2 0x12fd 3 0 4294967295 MEAS_ATB_CAL_VREF 0 0 NC7 7 7 RESERVED_15_8 8 15 ixDPCSSYS_CR4_LANE2_ANA_RX_ATB_FRC 2 0x12fe 2 0 4294967295 FRC_ATB_CAL_VREF 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR4_LANE2_ANA_RX_RESERVED1 2 0x12ff 2 0 4294967295 NC7_0 0 7 RESERVED_15_8 8 15 ixDPCSSYS_CR4_LANE3_DIG_ASIC_LANE_OVRD_IN 2 0x1300 5 0 4294967295 LANE_TX2RX_SER_LB 0 0 LANE_RX2TX_PAR_LB 1 1 EN 2 2 RX_ACJTAG_EN 3 3 RESERVED_15_4 4 15 ixDPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_0 2 0x1301 12 0 4294967295 REQ 0 0 REQ_OVRD_EN 1 1 PSTATE 2 3 PSTATE_OVRD_EN 4 4 RATE 5 7 RATE_OVRD_EN 8 8 WIDTH 9 10 WIDTH_OVRD_EN 11 11 MPLLB_SEL 12 12 MPLLB_SEL_OVRD_EN 13 13 DATA_EN 14 14 DATA_EN_OVRD_EN 15 15 ixDPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_1 2 0x1302 11 0 4294967295 NYQUIST_DATA 0 0 DISABLE 1 1 BEACON_EN 2 2 EN 3 3 TX_MAIN_CURSOR 4 9 MAIN_OVRD_EN 10 10 ASYNC_DRV_EN 11 11 ASYNC_DRV_OVRD_EN 12 12 TX_VREGDRV_BYP_OVRD 13 13 TX_VREGDRV_BYP_OVRD_EN 14 14 RESERVED_15_15 15 15 ixDPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_2 2 0x1303 6 0 4294967295 TX_PRE_CURSOR 0 5 PRE_OVRD_EN 6 6 TX_POST_CURSOR 7 12 POST_OVRD_EN 13 13 HDMIMODE_EN 14 14 HDMIMODE_ENABLE_OVRD_EN 15 15 ixDPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_3 2 0x1304 15 0 4294967295 CLK_RDY 0 0 CLK_RDY_OVRD_EN 1 1 DETECT_RX_REQ 2 2 DETECT_RX_REQ_OVRD_EN 3 3 INVERT 4 4 INVERT_OVRD_EN 5 5 LPD 6 6 LPD_OVRD_EN 7 7 TX_DC_COUP_EN 8 8 TX_DC_COUP_EN_OVRD_EN 9 9 PMA_EXTENDED_FIFO_EN 10 10 PMA_EXTENDED_FIFO_EN_OVRD_EN 11 11 TX_MPHY_MODE_EN 12 12 TX_MPHY_MODE_EN_OVRD_EN 13 13 RESERVED_15_14 14 15 ixDPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_4 2 0x1305 3 0 4294967295 RESET 0 0 RESET_OVRD_EN 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_OUT 2 0x1306 5 0 4294967295 TX_ACK 0 0 EN_TX_ACK 1 1 DETRX_RESULT 2 2 EN_DETRX_RESULT 3 3 RESERVED_15_4 4 15 ixDPCSSYS_CR4_LANE3_DIG_ASIC_RX_OVRD_OUT_0 2 0x130f 9 0 4294967295 ACK 0 0 ACK_OVRD_EN 1 1 ADAPT_STS 2 3 ADAPT_STS_OVRD_EN 4 4 RX_ASYNC_DATA 5 5 RX_ASYNC_DATA_OVRD_EN 6 6 RX_SQ_WEAKKEEP_OUT 7 7 RX_SQ_WEAKKEEP_OUT_OVRD_EN 8 8 RESERVED_15_9 9 15 ixDPCSSYS_CR4_LANE3_DIG_ASIC_LANE_ASIC_IN 2 0x1310 3 0 4294967295 LANE_TX2RX_SER_LB 0 0 LANE_RX2TX_PAR_LB 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR4_LANE3_DIG_ASIC_TX_ASIC_IN_0 2 0x1311 12 0 4294967295 CLK_RDY 0 0 RESET 1 1 INVERT 2 2 DATA_EN 3 3 REQ 4 4 LPD 5 5 PSTATE 6 7 RATE 8 10 WIDTH 11 12 MPLLB_SEL 13 13 DETECT_RX_REQ 14 14 DISABLE 15 15 ixDPCSSYS_CR4_LANE3_DIG_ASIC_TX_ASIC_IN_1 2 0x1312 7 0 4294967295 BEACON_EN 0 0 TX_MAIN_CURSOR 1 6 TX_ASYNC_EN 7 7 TX_ASYNC_DATA 8 8 TX_ASYNC_DRV_EN 9 9 TX_VREGDRV_BYP 10 10 RESERVED_15_11 11 15 ixDPCSSYS_CR4_LANE3_DIG_ASIC_TX_ASIC_IN_2 2 0x1313 3 0 4294967295 TX_PRE_CURSOR 0 5 TX_POST_CURSOR 6 11 RESERVED_15_12 12 15 ixDPCSSYS_CR4_LANE3_DIG_ASIC_TX_ASIC_OUT 2 0x1314 3 0 4294967295 TX_ACK 0 0 DETRX_RESULT 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR4_LANE3_DIG_ASIC_RX_ASIC_OUT_0 2 0x131b 4 0 4294967295 ACK 0 0 VALID 1 1 ADAPT_STS 2 3 RESERVED_15_4 4 15 ixDPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_5 2 0x131d 15 0 4294967295 RPTR_EN_MASTER_LANE 0 0 RPTR_EN_MASTER_LANE_OVRD_EN 1 1 DIG_CLK_EN_OTHER_LANE 2 2 DIG_CLK_EN_OTHER_LANE_OVRD_EN 3 3 DIG_CLK_STATE_MASTER_LANE 4 4 DIG_CLK_STATE_MASTER_LANE_OVRD_EN 5 5 SHIFT_MASTER_LANE 6 6 SHIFT_MASTER_LANE_ORVD_EN 7 7 SHIFT_ACK_OTHER_LANE 8 8 SHIFT_ACK_OTHER_LANE_OVRD_EN 9 9 LANE_MASTER 10 10 LANE_MASTER_OVRD_IN_EN 11 11 TX_DWORD_CLK_SYNC_OVRD 12 12 TX_DWORD_CLK_SYNC_OVRD_EN 13 13 RESERVED_15_14 14 15 ixDPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_OUT_1 2 0x131e 11 0 4294967295 RPTR_EN_OUT 0 0 RPTR_EN_OUT_OVRD_EN 1 1 DIG_CLK_EN_OUT 2 2 DIG_CLK_EN_OUT_OVRD_EN 3 3 DIG_CLK_STATE_OUT 4 4 DIG_CLK_STATE_OUT_OVRD_EN 5 5 SHIFT_OUT 6 6 SHIFT_OUT_OVRD_EN 7 7 SHIFT_ACK_OUT 8 8 SHIFT_ACK_OUT_OVRD_EN 9 9 RESERVED_15_10 10 15 ixDPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0 2 0x1320 11 0 4294967295 TX_P0_ANA_REFGEN_EN 0 0 TX_P0_ANA_VCM_HOLD 1 1 TX_P0_ANA_CLK_EN 2 2 TX_P0_ANA_WORD_CLK_EN 3 3 TX_P0_ANA_RESET 4 4 TX_P0_ANA_SERIAL_EN 5 5 TX_P0_DIG_CLK_EN 6 6 TX_P0_DATA_EN 7 7 TX_P0_ALLOW_RXDET 8 8 TX_P0_ANA_DCC_COMP_CAL_EN 9 9 RESERVED_15_10 10 15 ixDPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S 2 0x1321 11 0 4294967295 TX_P0S_ANA_REFGEN_EN 0 0 TX_P0S_ANA_VCM_HOLD 1 1 TX_P0S_ANA_CLK_EN 2 2 TX_P0S_ANA_WORD_CLK_EN 3 3 TX_P0S_ANA_RESET 4 4 TX_P0S_ANA_SERIAL_EN 5 5 TX_P0S_DIG_CLK_EN 6 6 TX_P0S_DATA_EN 7 7 TX_P0S_ALLOW_RXDET 8 8 TX_P0S_ANA_DCC_COMP_CAL_EN 9 9 RESERVED_15_10 10 15 ixDPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1 2 0x1322 11 0 4294967295 TX_P1_ANA_REFGEN_EN 0 0 TX_P1_ANA_VCM_HOLD 1 1 TX_P1_ANA_CLK_EN 2 2 TX_P1_ANA_WORD_CLK_EN 3 3 TX_P1_ANA_RESET 4 4 TX_P1_ANA_SERIAL_EN 5 5 TX_P1_DIG_CLK_EN 6 6 TX_P1_DATA_EN 7 7 TX_P1_ALLOW_RXDET 8 8 TX_P1_ANA_DCC_COMP_CAL_EN 9 9 RESERVED_15_10 10 15 ixDPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2 2 0x1323 12 0 4294967295 TX_P2_ANA_REFGEN_EN 0 0 TX_P2_ANA_VCM_HOLD 1 1 TX_P2_ANA_CLK_EN 2 2 TX_P2_ANA_WORD_CLK_EN 3 3 TX_P2_ANA_RESET 4 4 TX_P2_ANA_SERIAL_EN 5 5 TX_P2_DIG_CLK_EN 6 6 TX_P2_DATA_EN 7 7 TX_P2_ALLOW_RXDET 8 8 TX_P2_ALLOW_VBOOST 9 9 TX_P2_ANA_DCC_COMP_CAL_EN 10 10 RESERVED_15_11 11 15 ixDPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_0 2 0x1324 2 0 4294967295 TX_REFGEN_EN_TIME 0 7 TX_CLK_EN 8 15 ixDPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_1 2 0x1325 2 0 4294967295 TX_VCM_HOLD_TIME_14_0 0 14 SKIP_TX_VCM_HOLD_WAIT 15 15 ixDPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_2 2 0x1326 2 0 4294967295 TX_VBOOST_DIS_TIME_12_0 0 12 DTB_SEL 13 15 ixDPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_3 2 0x1327 3 0 4294967295 TX_VCM_HOLD_TIME_17_15 0 2 TX_VBOOST_DIS_TIME_13 3 3 RESERVED_15_4 4 15 ixDPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_4 2 0x1328 2 0 4294967295 TX_VCM_HOLD_GS_TIME 0 14 SKIP_TX_VCM_HOLD_GS_PULSE 15 15 ixDPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_5 2 0x1329 5 0 4294967295 TX_RXDET_TIME 0 9 FAST_TX_RXDET 10 10 TX_RESET_TIME 11 12 TX_SERIAL_EN_TIME 13 14 RESERVED_15_15 15 15 ixDPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_DCC_CR_BANK_ADDR 2 0x132a 1 0 4294967295 ADDR 0 15 ixDPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_DCC_CR_BANK_DATA 2 0x132b 1 0 4294967295 DATA 0 15 ixDPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_DCC_DAC_CTRL 2 0x132c 2 0 4294967295 CTRL 0 7 RESERVED_15_8 8 15 ixDPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_DCC_DAC_RANGE 2 0x132d 2 0 4294967295 CTRL 0 1 RESERVED_15_2 2 15 ixDPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_DCC_DAC_SEL 2 0x132e 6 0 4294967295 SEL 0 2 REQ 3 3 CTRL_UPD 4 4 RANGE_UPD 5 5 BIN_HOT 6 6 RESERVED_15_7 7 15 ixDPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_DCC_DAC_ACK 2 0x132f 2 0 4294967295 ACK 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_DCC_DAC_ADDR 2 0x1330 1 0 4294967295 ADDR 0 15 ixDPCSSYS_CR4_LANE3_DIG_TX_CLK_ALIGN_TX_CTL_0 2 0x1331 4 0 4294967295 TX_NUM_2UI_SHIFTS_16B_MODE 0 3 TX_NUM_2UI_SHIFTS_20B_MODE 4 7 TX_FIFO_BYPASS 8 8 RESERVED_15_9 9 15 ixDPCSSYS_CR4_LANE3_DIG_TX_LBERT_CTL 2 0x1332 4 0 4294967295 MODE 0 3 TRIGGER_ERR 4 4 PAT0 5 14 RESERVED_15_15 15 15 ixDPCSSYS_CR4_LANE3_DIG_RX_STAT_LD_VAL_1 2 0x1380 2 0 4294967295 SC1_LD_VAL 0 14 SC1_START 15 15 ixDPCSSYS_CR4_LANE3_DIG_RX_STAT_DATA_MSK 2 0x1381 1 0 4294967295 DATA_MSK_15_0 0 15 ixDPCSSYS_CR4_LANE3_DIG_RX_STAT_MATCH_CTL0 2 0x1382 4 0 4294967295 PTTRN_MSK_CR1A_4_0 0 4 PTTRN_CR1A_4_0 5 9 DATA_MSK_19_16 10 13 SCOPE_DLY 14 15 ixDPCSSYS_CR4_LANE3_DIG_RX_STAT_MATCH_CTL1 2 0x1383 5 0 4294967295 PTTRN_CR1B_EN 0 0 PTTRN_MSK_CR1B_4_0 1 5 PTTRN_CR1B_4_0 6 10 PTTRN_CR1A_ADPT_EN 11 11 RESERVED_15_12 12 15 ixDPCSSYS_CR4_LANE3_DIG_RX_STAT_STAT_CTL0 2 0x1384 10 0 4294967295 RESERVED_0 0 0 CORR_SHFT_SEL_VGA 1 1 CORR_SHFT_SEL 2 2 CORR_SRC_SEL 3 4 CORR_MODE_EN 5 5 STAT_SHFT_SEL 6 9 STAT_SRC_SEL 10 12 STAT_RXCLK_SEL 13 13 SC_TIMER_MODE 14 14 SKIP_EN 15 15 ixDPCSSYS_CR4_LANE3_DIG_RX_STAT_STAT_CTL1 2 0x1385 13 0 4294967295 STAT_CNT_0_EN 0 0 STAT_CNT_1_EN 1 1 STAT_CNT_2_EN 2 2 STAT_CNT_3_EN 3 3 STAT_CNT_4_EN 4 4 STAT_CNT_5_EN 5 5 STAT_CNT_6_EN 6 6 RESERVED_8_7 7 8 SC_PAUSE 9 9 STAT_CLK_EN 10 10 DATA_DLY_SEL 11 12 VLD_LOSS_CLR 13 13 VLD_CTL 14 15 ixDPCSSYS_CR4_LANE3_DIG_RX_STAT_SMPL_CNT1 2 0x1386 2 0 4294967295 SMPL_CNT1 0 14 SMPL_CNT1_DONE 15 15 ixDPCSSYS_CR4_LANE3_DIG_RX_STAT_STAT_CNT_0 2 0x1387 2 0 4294967295 STAT_CNT_0 0 14 SMPL_CNT1_DONE 15 15 ixDPCSSYS_CR4_LANE3_DIG_RX_STAT_STAT_CNT_1 2 0x1388 2 0 4294967295 STAT_CNT_1 0 14 SMPL_CNT1_DONE 15 15 ixDPCSSYS_CR4_LANE3_DIG_RX_STAT_STAT_CNT_2 2 0x1389 2 0 4294967295 STAT_CNT_2 0 14 SMPL_CNT1_DONE 15 15 ixDPCSSYS_CR4_LANE3_DIG_RX_STAT_STAT_CNT_3 2 0x138a 2 0 4294967295 STAT_CNT_3 0 14 SMPL_CNT1_DONE 15 15 ixDPCSSYS_CR4_LANE3_DIG_RX_STAT_STAT_CNT_4 2 0x138b 2 0 4294967295 STAT_CNT_4 0 14 SMPL_CNT1_DONE 15 15 ixDPCSSYS_CR4_LANE3_DIG_RX_STAT_STAT_CNT_5 2 0x138c 2 0 4294967295 STAT_CNT_5 0 14 SMPL_CNT1_DONE 15 15 ixDPCSSYS_CR4_LANE3_DIG_RX_STAT_STAT_CNT_6 2 0x138d 2 0 4294967295 STAT_CNT_6 0 14 SMPL_CNT1_DONE 15 15 ixDPCSSYS_CR4_LANE3_DIG_RX_STAT_CAL_COMP_CLK_CTL 2 0x138e 3 0 4294967295 PRECHRGE_CNT 0 2 REF_DIV_CNT 3 5 RESERVED_15_6 6 15 ixDPCSSYS_CR4_LANE3_DIG_RX_STAT_MATCH_CTL2 2 0x138f 2 0 4294967295 PTTRN_CR1A_19_5 0 14 RESERVED_15_15 15 15 ixDPCSSYS_CR4_LANE3_DIG_RX_STAT_MATCH_CTL3 2 0x1390 2 0 4294967295 PTTRN_MSK_CR1A_19_5 0 14 RESERVED_15_15 15 15 ixDPCSSYS_CR4_LANE3_DIG_RX_STAT_MATCH_CTL4 2 0x1391 2 0 4294967295 PTTRN_CR1B_19_5 0 14 RESERVED_15_15 15 15 ixDPCSSYS_CR4_LANE3_DIG_RX_STAT_MATCH_CTL5 2 0x1392 2 0 4294967295 PTTRN_MSK_CR1B_19_5 0 14 RESERVED_15_15 15 15 ixDPCSSYS_CR4_LANE3_DIG_RX_STAT_STAT_CTL2 2 0x1393 4 0 4294967295 DATA_DLY_SEL_2 0 0 SCOPE_DLY_2 1 1 DISABLE_SAMPLE_COUNT 2 2 RESERVED_15_3 3 15 ixDPCSSYS_CR4_LANE3_DIG_RX_STAT_STAT_STOP 2 0x1394 2 0 4294967295 SC1_STOP 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR4_LANE3_DIG_ANA_TX_OVRD_OUT 2 0x13a0 15 0 4294967295 TX_ANA_CLK_SHIFT 0 0 TX_ANA_DATA_EN 1 1 TX_ANA_REFGEN_EN 2 2 TX_ANA_VCM_HOLD 3 3 TX_ANA_CLK_EN 4 4 TX_ANA_WORD_CLK_EN 5 5 TX_ANA_MPLLA_CLK_EN 6 6 TX_ANA_MPLLB_CLK_EN 7 7 TX_ANA_RESET 8 8 TX_ANA_SERIAL_EN 9 9 TX_ANA_DATA_RATE 10 11 RESERVED 12 12 TX_DIV4_EN 13 13 TX_RXDET_EN 14 14 TX_OVRD_EN 15 15 ixDPCSSYS_CR4_LANE3_DIG_ANA_TX_TERM_CODE_OVRD_OUT 2 0x13a1 5 0 4294967295 TX_TERM_CODE 0 9 TX_TERM_OVRD_EN 10 10 TX_DRV_SRC 11 12 TX_DRV_SRC_OVRD_EN 13 13 RESERVED_15_14 14 15 ixDPCSSYS_CR4_LANE3_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT 2 0x13a2 3 0 4294967295 TX_TERM_DN_CLK 0 0 TX_TERM_CLK_SELF_CLEAR_DISABLE 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR4_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_0 2 0x13a3 3 0 4294967295 TX_ANA_LOAD_CLK 0 0 TX_ANA_CTRL_LEG_PULL_EN_13_0 1 14 TX_EQ_OVRD_EN 15 15 ixDPCSSYS_CR4_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_1 2 0x13a4 2 0 4294967295 TX_ANA_CTRL_LEG_PULL_EN_19_14 0 5 RESERVED_15_6 6 15 ixDPCSSYS_CR4_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_2 2 0x13a5 4 0 4294967295 RESERVED 0 2 TX_ANA_CTRL_EQ_MUX_SEL 3 6 TX_ANA_CTRL_PRE 7 12 RESERVED_15_13 13 15 ixDPCSSYS_CR4_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_3 2 0x13a6 2 0 4294967295 TX_ANA_CTRL_POST 0 8 RESERVED_15_9 9 15 ixDPCSSYS_CR4_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_4 2 0x13a7 1 0 4294967295 TX_ANA_CTRL_LEG_PULL_DIR_19_4 0 15 ixDPCSSYS_CR4_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_5 2 0x13a8 2 0 4294967295 TX_ANA_CTRL_LEG_PULL_DIR_3_0 0 3 RESERVED_15_4 4 15 ixDPCSSYS_CR4_LANE3_DIG_ANA_STATUS_0 2 0x13bb 9 0 4294967295 TX_ANA_CLK_SHIFT_ACK 0 0 TX_ANA_RXDETP_RESULT 1 1 TX_ANA_RXDETM_RESULT 2 2 TX_ANA_LOOPBACK_EN 3 3 TX_ANA_CLK_LB_EN 4 4 RX_ANA_CAL_RESULT 5 5 RX_ANA_SCOPE_DATA 6 6 TX_ANA_DCC_CAL_RESULT 7 7 TX_ANA_CTRL_EQ_MUX 8 15 ixDPCSSYS_CR4_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT 2 0x13c2 8 0 4294967295 TX_ANA_DCC_CAL_RANGE 0 1 TX_ANA_DCC_CAL_RANGE_OVRD_EN 2 2 TX_ANA_DCC_CAL_COMP_EN 3 3 TX_ANA_DCC_CAL_COMP_EN_OVRD_EN 4 4 TX_ANA_DCC_CAL_CTRL 5 12 TX_ANA_DCC_CAL_CTRL_OVRD_EN 13 13 TX_ANA_DCC_CAL_CTRL_EN 14 14 TX_ANA_DCC_CAL_CTRL_EN_OVRD_EN 15 15 ixDPCSSYS_CR4_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2 2 0x13c3 5 0 4294967295 TX_ANA_DCC_CAL_CTRL_SEL 0 2 TX_ANA_DCC_CAL_CTRL_SEL_OVRD_EN 3 3 TX_ANA_DCC_CLK_COMP 4 4 TX_ANA_DCC_CLK_COMP_OVRD_EN 5 5 RESERVED_15_6 6 15 ixDPCSSYS_CR4_LANE3_DIG_ANA_TX_OVRD_OUT_2 2 0x13c4 6 0 4294967295 TX_ANA_FAST_START 0 0 TX_ANA_FAST_START_OVRD_EN 1 1 TX_CLK_LB_EN 2 2 TX_CLK_LB_EN_OVRD_EN 3 3 TX_ACJTAG_EN 4 4 RESERVED_15_5 5 15 ixDPCSSYS_CR4_LANE3_ANA_TX_OVRD_MEAS 2 0x13e0 9 0 4294967295 OVRD_CLK_SHIFT 0 0 CLK_SHIFT_REG 0 0 MEAS_ATB_CAL_MUX 0 0 MEAS_ATB_CAL_COMP 0 0 OVRD_VCM_HOLD 0 0 VCM_HOLD_REG 0 0 PULL_UP_REG 0 0 PULL_DN_REG 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR4_LANE3_ANA_TX_PWR_OVRD 2 0x13e1 9 0 4294967295 OVRD_TX_LOOPBACK 0 0 LOOPBACK_EN_REG 0 0 REFGEN_EN_REG 0 0 CLK_DIV_EN_REG 0 0 DATA_EN_REG_INT 0 0 CLK_EN_REG 0 0 SERIAL_EN_REG 0 0 OVRD_EN 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR4_LANE3_ANA_TX_ALT_BUS 2 0x13e2 6 0 4294967295 DRV_SOURCE_REG 0 0 OVRD_ALT_BUS 0 0 ATB_S_ENABLE 0 0 TX_ALT_RINGO 0 0 JTAG_DATA_REG 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR4_LANE3_ANA_TX_ATB1 2 0x13e3 9 0 4294967295 MEAS_ATB_GD 0 0 MEAS_ATB_VDDH 0 0 OVERRIDE_RXDETREF 0 0 MEAS_ATB_VPTX 0 0 OVERRIDE_REGREF 0 0 MEAS_ATB_VREG_DRV 0 0 MEAS_ATB_VREG 0 0 MEAS_ATB_VPH_HALF 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR4_LANE3_ANA_TX_ATB2 2 0x13e4 9 0 4294967295 MEAS_ATB_VCM 0 0 MEAS_ATB_CAL_VDAC_CM 0 0 MEAS_ATB_CAL_VDAC_DIFF 0 0 MEAS_ATB_TXM 0 0 MEAS_ATB_TXP 0 0 MEAS_ATB_RXDETREF 0 0 LFPS_HIGH_PRIORITY 0 0 OSC_DIV4_EN 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR4_LANE3_ANA_TX_DCC_DAC 2 0x13e5 2 0 4294967295 DCC_DAC_REG 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR4_LANE3_ANA_TX_DCC_CTRL1 2 0x13e6 7 0 4294967295 NC0 0 0 OVRD_DCC_DAC_CTRL_SEL 0 0 DCC_DAC_CTRL_SEL_REG 0 0 OVRD_DCC_DAC_CTRL_EN 0 0 DCC_DAC_CTRL_EN_REG 0 0 OVRD_DCC_DAC_REG 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR4_LANE3_ANA_TX_TERM_CODE 2 0x13e7 2 0 4294967295 TERM_CODE_REG_70 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR4_LANE3_ANA_TX_TERM_CODE_CTRL 2 0x13e8 8 0 4294967295 VREG_BOOST_1 0 0 OVRD_UPDATE_TERM 0 0 UPDATE_TERM_REG 0 0 OVRD_RESET_TERM 0 0 RESET_TERM_REG 0 0 OVRD_TERM_CODE 0 0 TERM_CODE_REG_98 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR4_LANE3_ANA_TX_OVRD_CLK 2 0x13e9 9 0 4294967295 VREG_BOOST_0 0 0 CLK_LB_EN_REG 0 0 OVRD_LB_EN 0 0 MPLLB_CLK_EN_REG 0 0 MPLLA_CLK_EN_REG 0 0 OVRD_MPLLAB_EN 0 0 WORD_CLK_EN_REG 0 0 OVRD_WORD_CLK_EN 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR4_LANE3_ANA_TX_MISC1 2 0x13ea 8 0 4294967295 MEAS_ATB_CAL_CLK_ALIGN 0 0 OVRD_DCC_DAC_CTRL_RANGE 0 0 DCC_DAC_CTRL_RANGE_REG 0 0 OVRD_VREF_SEL 0 0 VREF_SEL_REG 0 0 FORCE_ATB_TXM 0 0 FORCE_ATB_TXP 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR4_LANE3_ANA_TX_MISC2 2 0x13eb 8 0 4294967295 TX_PEAKING_LVL 0 0 VREG_CP_GAIN_CTRL 0 0 TX_SLEW_EN 0 0 EN_INV_POST 0 0 EN_INV_PRE 0 0 TX_VREG_EN_BYP 0 0 TX_VDRIVER_PULLDN_EN 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR4_LANE3_ANA_TX_MISC3 2 0x13ec 4 0 4294967295 TX_VREG_OVRD_RING_CTRL 0 0 TX_DCC_LOWV 0 0 NC7_2 2 7 RESERVED_15_8 8 15 ixDPCSSYS_CR4_LANE3_ANA_TX_RESERVED2 2 0x13ed 2 0 4294967295 NC7_0 0 7 RESERVED_15_8 8 15 ixDPCSSYS_CR4_LANE3_ANA_TX_RESERVED3 2 0x13ee 2 0 4294967295 NC7_0 0 7 RESERVED_15_8 8 15 ixDPCSSYS_CR4_LANE3_ANA_TX_RESERVED4 2 0x13ef 2 0 4294967295 NC7_0 0 7 RESERVED_15_8 8 15 ixDPCSSYS_CR4_RAWCMN_DIG_CMN_CTL 2 0x2000 2 0 4294967295 PHY_FUNC_RST 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR4_RAWCMN_DIG_MPLLA_OVRD_IN 2 0x2001 10 0 4294967295 MPLLA_WORD_DIV2_EN_OVRD_VAL 0 0 MPLLA_WORD_DIV2_EN_OVRD_EN 1 1 MPLLA_TX_CLK_DIV_OVRD_VAL 2 4 MPLLA_TX_CLK_DIV_OVRD_EN 5 5 MPLLA_DIV10_CLK_EN_OVRD_VAL 6 6 MPLLA_DIV10_CLK_EN_OVRD_EN 7 7 MPLLA_DIV8_CLK_EN_OVRD_VAL 8 8 MPLLA_DIV8_CLK_EN_OVRD_EN 9 9 MPLLA_BW_OVRD_EN 10 10 RESERVED_15_11 11 15 ixDPCSSYS_CR4_RAWCMN_DIG_MPLLA_BW_OVRD_IN 2 0x2002 1 0 4294967295 MPLLA_BW_OVRD_VAL 0 15 ixDPCSSYS_CR4_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_0 2 0x2003 7 0 4294967295 MPLLA_SSC_RANGE_OVRD_VAL 0 2 MPLLA_SSC_RANGE_OVRD_EN 3 3 MPLLA_SSC_CLK_SEL_OVRD_VAL 4 6 MPLLA_SSC_CLK_SEL_OVRD_EN 7 7 MPLLA_SSC_EN_OVRD_VAL 8 8 MPLLA_SSC_EN_OVRD_EN 9 9 RESERVED_15_10 10 15 ixDPCSSYS_CR4_RAWCMN_DIG_MPLLB_OVRD_IN 2 0x2004 10 0 4294967295 MPLLB_WORD_DIV2_EN_OVRD_VAL 0 0 MPLLB_WORD_DIV2_EN_OVRD_EN 1 1 MPLLB_TX_CLK_DIV_OVRD_VAL 2 4 MPLLB_TX_CLK_DIV_OVRD_EN 5 5 MPLLB_DIV10_CLK_EN_OVRD_VAL 6 6 MPLLB_DIV10_CLK_EN_OVRD_EN 7 7 MPLLB_DIV8_CLK_EN_OVRD_VAL 8 8 MPLLB_DIV8_CLK_EN_OVRD_EN 9 9 MPLLB_BW_OVRD_EN 10 10 RESERVED_15_11 11 15 ixDPCSSYS_CR4_RAWCMN_DIG_MPLLB_BW_OVRD_IN 2 0x2005 1 0 4294967295 MPLLB_BW_OVRD_VAL 0 15 ixDPCSSYS_CR4_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_0 2 0x2006 7 0 4294967295 MPLLB_SSC_RANGE_OVRD_VAL 0 2 MPLLB_SSC_RANGE_OVRD_EN 3 3 MPLLB_SSC_CLK_SEL_OVRD_VAL 4 6 MPLLB_SSC_CLK_SEL_OVRD_EN 7 7 MPLLB_SSC_EN_OVRD_VAL 8 8 MPLLB_SSC_EN_OVRD_EN 9 9 RESERVED_15_10 10 15 ixDPCSSYS_CR4_RAWCMN_DIG_LANE_FSM_OP_XTND 2 0x2007 2 0 4294967295 DATA 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR4_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_1 2 0x2008 3 0 4294967295 MPLLA_FRACN_CTRL_OVRD_VAL 0 10 MPLLA_FRACN_CTRL_OVRD_EN 11 11 RESERVED_15_12 12 15 ixDPCSSYS_CR4_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_1 2 0x2009 3 0 4294967295 MPLLB_FRACN_CTRL_OVRD_VAL 0 10 MPLLB_FRACN_CTRL_OVRD_EN 11 11 RESERVED_15_12 12 15 ixDPCSSYS_CR4_RAWCMN_DIG_CMN_CTL_1 2 0x200a 13 0 4294967295 MPLLA_INIT_CAL_DISABLE_OVRD_VAL 0 0 MPLLA_INIT_CAL_DISABLE_OVRD_EN 1 1 MPLLB_INIT_CAL_DISABLE_OVRD_VAL 2 2 MPLLB_INIT_CAL_DISABLE_OVRD_EN 3 3 RTUNE_REQ_OVRD_VAL 4 4 RTUNE_REQ_OVRD_EN 5 5 HDMIMODE_ENABLE_OVRD_VAL 6 6 HDMIMODE_ENABLE_OVRD_EN 7 7 TX_PWM_CLK_SEL_OVRD_VAL 8 9 TX_PWM_CLK_SEL_OVRD_EN 10 10 TX_PWM_CLK_EN_OVRD_VAL 11 11 TX_PWM_CLK_EN_OVRD_EN 12 12 RESERVED_15_13 13 15 ixDPCSSYS_CR4_RAWCMN_DIG_MPLL_STATE_CTL 2 0x200b 8 0 4294967295 MPLL_OFF_TIME 0 5 MPLLA_STATE 6 6 MPLLB_STATE 7 7 MPLL_STATE_OVRD_OUT_EN 8 8 MPLL_FORCE_ON_TIME 9 12 MPLLB_BANK_SEL 13 13 MPLLA_BANK_SEL 14 14 RESERVED_15_15 15 15 ixDPCSSYS_CR4_RAWCMN_DIG_TX_CAL_CODE 2 0x200c 2 0 4294967295 DATA 0 0 RESERVED_15_4 4 15 ixDPCSSYS_CR4_RAWCMN_DIG_SRAM_INIT_DONE 2 0x200d 2 0 4294967295 DATA 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR4_RAWCMN_DIG_OCLA 2 0x200e 3 0 4294967295 DIV2_CLK_EN 0 0 TCA_OCLA_PROBE_SEL 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR4_RAWCMN_DIG_SUP_ANA_OVRD 2 0x200f 7 0 4294967295 REF_ALT_CLK_LP_SEL_OVRD_EN 0 0 REF_ALT_CLK_LP_SEL_OVRD_VAL 1 1 SUP_PRE_HP_OVRD_EN 2 2 SUP_PRE_HP_OVRD_VAL 3 3 SUP_RX_VCO_VREF_SEL_OVRD_EN 4 4 SUP_RX_VCO_VREF_SEL_OVRD_VAL 5 7 RESERVED_15_8 8 15 ixDPCSSYS_CR4_RAWCMN_DIG_PCS_RAW_ID_CODE 2 0x2010 1 0 4294967295 DATA 0 0 ixDPCSSYS_CR4_RAWCMN_DIG_FW_ID_CODE_1 2 0x2011 1 0 4294967295 W_ID_CODE_1 0 15 ixDPCSSYS_CR4_RAWCMN_DIG_FW_ID_CODE_2 2 0x2012 1 0 4294967295 W_ID_CODE_2 0 15 ixDPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_0 2 0x2020 2 0 4294967295 RTUNE_RX_VAL_0 0 5 RESERVED_15_6 6 15 ixDPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_0 2 0x2021 2 0 4294967295 RTUNE_TXDN_VAL_0 0 9 RESERVED_15_10 10 15 ixDPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_0 2 0x2022 2 0 4294967295 RTUNE_TXUP_VAL_0 0 9 RESERVED_15_10 10 15 ixDPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_1 2 0x2023 2 0 4294967295 RTUNE_RX_VAL_1 0 5 RESERVED_15_6 6 15 ixDPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_1 2 0x2024 2 0 4294967295 RTUNE_TXDN_VAL_1 0 9 RESERVED_15_10 10 15 ixDPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_1 2 0x2025 2 0 4294967295 RTUNE_TXUP_VAL_1 0 9 RESERVED_15_10 10 15 ixDPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_2 2 0x2026 2 0 4294967295 RTUNE_RX_VAL_2 0 5 RESERVED_15_6 6 15 ixDPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_2 2 0x2027 2 0 4294967295 RTUNE_TXDN_VAL_2 0 9 RESERVED_15_10 10 15 ixDPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_2 2 0x2028 2 0 4294967295 RTUNE_TXUP_VAL_2 0 9 RESERVED_15_10 10 15 ixDPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_3 2 0x2029 2 0 4294967295 RTUNE_RX_VAL_3 0 5 RESERVED_15_6 6 15 ixDPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_3 2 0x202a 2 0 4294967295 RTUNE_TXDN_VAL_3 0 9 RESERVED_15_10 10 15 ixDPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_3 2 0x202b 2 0 4294967295 RTUNE_TXUP_VAL_3 0 9 RESERVED_15_10 10 15 ixDPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_4 2 0x202c 2 0 4294967295 RTUNE_RX_VAL_4 0 5 RESERVED_15_6 6 15 ixDPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_4 2 0x202d 2 0 4294967295 RTUNE_TXDN_VAL_4 0 9 RESERVED_15_10 10 15 ixDPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_4 2 0x202e 2 0 4294967295 RTUNE_TXUP_VAL_4 0 9 RESERVED_15_10 10 15 ixDPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_5 2 0x202f 2 0 4294967295 RTUNE_RX_VAL_5 0 5 RESERVED_15_6 6 15 ixDPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_5 2 0x2030 2 0 4294967295 RTUNE_TXDN_VAL_5 0 9 RESERVED_15_10 10 15 ixDPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_5 2 0x2031 2 0 4294967295 RTUNE_TXUP_VAL_5 0 9 RESERVED_15_10 10 15 ixDPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_6 2 0x2032 2 0 4294967295 RTUNE_RX_VAL_6 0 5 RESERVED_15_6 6 15 ixDPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_6 2 0x2033 2 0 4294967295 RTUNE_TXDN_VAL_6 0 9 RESERVED_15_10 10 15 ixDPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_6 2 0x2034 2 0 4294967295 RTUNE_TXUP_VAL_6 0 9 RESERVED_15_10 10 15 ixDPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_7 2 0x2035 2 0 4294967295 RTUNE_RX_VAL_7 0 5 RESERVED_15_6 6 15 ixDPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_7 2 0x2036 2 0 4294967295 RTUNE_TXDN_VAL_7 0 9 RESERVED_15_10 10 15 ixDPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_7 2 0x2037 2 0 4294967295 RTUNE_TXUP_VAL_7 0 9 RESERVED_15_10 10 15 ixDPCSSYS_CR4_RAWCMN_DIG_AON_CMN_SRAM_BL_CFG 2 0x2038 5 0 4294967295 SRAM_PGATE_BL_EN 0 0 SRAM_BL_ROM 1 1 SRAM_BL_BYPASS 2 2 SRAM_BL_START 3 3 RESERVED_15_4 4 15 ixDPCSSYS_CR4_RAWCMN_DIG_AON_CMN_PG_OVRD_IN 2 0x2039 7 0 4294967295 PMA_PWR_STABLE_OVRD 0 0 PCS_PWR_STABLE_OVRD 1 1 PG_RESET_OVRD_VAL 2 2 PG_RESET_OVRD_EN 3 3 PG_MODE_EN_OVRD_VAL 4 4 PG_MODE_EN_OVRD_EN 5 5 RESERVED_15_6 6 15 ixDPCSSYS_CR4_RAWCMN_DIG_AON_CMN_PG_OVRD_OUT 2 0x203a 8 0 4294967295 PMA_PWR_EN_OVRD 0 0 PCS_PWR_EN_OVRD 1 1 MON_IN_VALID_OVRD_VAL 2 2 MON_IN_VALID_OVRD_EN 3 3 MON_IN_PULL_DOWN 4 4 ANA_ISOLATION_EN_OVRD_EN 5 5 ANA_ISOLATION_EN_OVRD_VAL 6 6 RESERVED_15_7 7 15 ixDPCSSYS_CR4_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN 2 0x203b 11 0 4294967295 MPLLA_FORCE_EN_OVRD_VAL 0 0 MPLLA_FORCE_EN_OVRD_EN 1 1 MPLLB_FORCE_EN_OVRD_VAL 2 2 MPLLB_FORCE_EN_OVRD_EN 3 3 REF_CLK_EN_OVRD_VAL 4 4 REF_CLK_EN_OVRD_EN 5 5 MPLLA_FORCE_ACK_OVRD_VAL 6 6 MPLLA_FORCE_ACK_OVRD_EN 7 7 MPLLB_FORCE_ACK_OVRD_VAL 8 8 MPLLB_FORCE_ACK_OVRD_EN 9 9 RESERVED_15_10 10 15 ixDPCSSYS_CR4_RAWCMN_DIG_AON_CMN_VREF_STATS 2 0x203c 3 0 4294967295 SUP_ANA_VPHUD_SELVPH 0 0 VREF_CAL_DONE 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RES_OVRD_IN 2 0x203d 8 0 4294967295 RES_REQ_IN 0 0 RES_ACK_IN 1 1 RES_OVRD_EN 2 2 RES_REQ_OUT 3 3 RES_REQ_OUT_OVRD_EN 4 4 RES_ACK_OUT 5 5 RES_ACK_OUT_OVRD_EN 6 6 RESERVED_15_7 7 15 ixDPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RES_ASIC_IN_OUT 2 0x203e 5 0 4294967295 RES_REQ_IN 0 0 RES_REQ_OUT 1 1 RES_ACK_IN 2 2 RES_ACK_OUT 3 3 RESERVED_15_4 4 15 ixDPCSSYS_CR4_RAWCMN_DIG_AON_CMN_REF_RANGE_OVRD 2 0x203f 3 0 4294967295 OVRD_VAL 0 4 OVRD_EN 5 5 RESERVED_15_6 6 15 ixDPCSSYS_CR4_RAWCMN_DIG_AON_CMN_MISC_CONF_IN_1 2 0x2040 2 0 4294967295 MPLL_PWRDN_TIME 0 9 RESERVED_15_10 10 15 ixDPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN 2 0x3000 12 0 4294967295 PSTATE 0 1 LPD 2 2 WIDTH 3 4 RATE 5 7 MPLLB_SEL 8 8 MPLL_EN 9 9 OVRD_EN 10 10 MSTR_MPLLA_STATE 11 11 MSTR_MPLLB_STATE 12 12 MSTR_MPLL_OVRD_EN 13 13 TX_ASYNC_EN_OVR_VAL 14 14 TX_ASYNC_EN_OVR_EN 15 15 ixDPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1 2 0x3001 13 0 4294967295 RESET_OVRD_VAL 0 0 RESET_OVRD_EN 1 1 REQ_OVRD_VAL 2 2 REQ_OVRD_EN 3 3 DETRX_REQ_OVRD_VAL 4 4 DETRX_REQ_OVRD_EN 5 5 VBOOST_EN_OVRD_VAL 6 6 VBOOST_EN_OVRD_EN 7 7 IBOOST_LVL_OVRD_VAL 8 11 IBOOST_LVL_OVRD_EN 12 12 TX_BEACON_EN_OVR_VAL 13 13 TX_BEACON_EN_OVR_EN 14 14 RESERVED_15_15 15 15 ixDPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_PCS_IN 2 0x3002 12 0 4294967295 RESET 0 0 REQ 1 1 PSTATE 2 3 LPD 4 4 WIDTH 5 6 RATE 7 9 MPLLB_SEL 10 10 MPLL_EN 11 11 MSTR_MPLLA_STATE 12 12 MSTR_MPLLB_STATE 13 13 DETRX_REQ 14 14 RESERVED_15_15 15 15 ixDPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_OVRD_OUT 2 0x3003 6 0 4294967295 ACK 0 0 DETRX_RESULT 1 1 EN_CTL 2 2 TX_DWORD_CLK_SYNC_OVRD_VAL 3 3 TX_DWORD_CLK_SYNC_OVRD_EN 4 4 RESERVED_15_5 5 15 ixDPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_PCS_OUT 2 0x3004 2 0 4294967295 ACK 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN 2 0x3005 12 0 4294967295 RATE 0 1 WIDTH 2 3 PSTATE 4 5 LPD 6 6 OVRD_EN 7 7 ADAPT_AFE_EN 8 8 ADAPT_DFE_EN 9 9 LANE_RX2TX_PAR_LB_EN_OVRD_VAL 10 10 LANE_RX2TX_PAR_LB_EN_OVRD_EN 11 11 RX_DATA_EN_OVRD_VAL_R 12 12 RX_DATA_EN_OVRD_EN_R 13 13 RESERVED_15_14 14 15 ixDPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1 2 0x3006 12 0 4294967295 RESET_OVRD_VAL 0 0 RESET_OVRD_EN 1 1 REQ_OVRD_VAL 2 2 REQ_OVRD_EN 3 3 RX_LOS_THRSHLD_OVRD_VAL 4 6 RX_LOS_THRSHLD_OVRD_EN 7 7 ADAPT_REQ 8 8 ADAPT_REQ_OVRD_EN 9 9 ADAPT_CONT 10 10 OFFCAN_CONT 11 11 CONT_OVRD_EN 12 12 RESERVED_15_13 13 15 ixDPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_2 2 0x3007 4 0 4294967295 VCO_LD_VAL_OVRD 0 12 VCO_LD_VAL_OVRD_EN 13 13 VCO_LOWFREQ_VAL_OVRD 14 14 VCO_LOWFREQ_VAL_OVRD_EN 15 15 ixDPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_3 2 0x3008 3 0 4294967295 REF_LD_VAL_OVRD 0 6 REF_LD_VAL_OVRD_EN 7 7 RESERVED_15_8 8 15 ixDPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_PCS_IN 2 0x3009 13 0 4294967295 REQ 0 0 RATE 1 2 WIDTH 3 4 PSTATE 5 6 LPD 7 7 CDR_VCO_LOWFREQ 8 8 ADAPT_AFE_EN 9 9 ADAPT_DFE_EN 10 10 ADAPT_REQ 11 11 ADAPT_CONT 12 12 OFFCAN_CONT 13 13 RESET 14 14 RESERVED_15_15 15 15 ixDPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_1 2 0x300a 2 0 4294967295 REF_LD_VAL 0 6 RESERVED_15_7 7 15 ixDPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_2 2 0x300b 2 0 4294967295 VCO_LD_VAL 0 12 RESERVED_15_13 13 15 ixDPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_3 2 0x300c 4 0 4294967295 EQ_ATT_LVL 0 2 EQ_VGA1_GAIN 3 6 EQ_VGA2_GAIN 7 10 EQ_CTLE_BOOST 11 15 ixDPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_4 2 0x300d 3 0 4294967295 EQ_CTLE_POLE 0 2 EQ_DFE_TAP1 3 10 RESERVED_15_11 11 15 ixDPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT 2 0x300e 3 0 4294967295 ACK 0 0 EN_CTL 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_PCS_OUT 2 0x300f 2 0 4294967295 ACK 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_ADAPT_ACK 2 0x3010 2 0 4294967295 RX_ADAPT_ACK 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_ADAPT_FOM 2 0x3011 2 0 4294967295 RX_ADAPT_FOM 0 7 RESERVED_15_8 8 15 ixDPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_TXPRE_DIR 2 0x3012 2 0 4294967295 RX_TXPRE_DIR 0 1 RESERVED_15_2 2 15 ixDPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_TXMAIN_DIR 2 0x3013 2 0 4294967295 RX_TXMAIN_DIR 0 1 RESERVED_15_2 2 15 ixDPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_TXPOST_DIR 2 0x3014 2 0 4294967295 RX_TXPOST_DIR 0 1 RESERVED_15_2 2 15 ixDPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_LANE_NUMBER 2 0x3015 2 0 4294967295 LANE_NUMBER 0 3 RESERVED_15_4 4 15 ixDPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RESERVED_1 2 0x3016 1 0 4294967295 RESERVED_REG_1 0 15 ixDPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RESERVED_2 2 0x3017 1 0 4294967295 RESERVED_REG_2 0 15 ixDPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN 2 0x3018 16 0 4294967295 RX_RESET_ATE_OVRD_VAL 0 0 RX_RESET_ATE_OVRD_EN 1 1 TX_RESET_ATE_OVRD_VAL 2 2 TX_RESET_ATE_OVRD_EN 3 3 RX_REQ_ATE_OVRD_VAL 4 4 RX_REQ_ATE_OVRD_EN 5 5 TX_REQ_ATE_OVRD_VAL 6 6 TX_REQ_ATE_OVRD_EN 7 7 RX_ADAPT_AFE_EN_OVRD_VAL 8 8 RX_ADAPT_AFE_EN_OVRD_EN 9 9 RX_ADAPT_DFE_EN_OVRD_VAL 10 10 RX_ADAPT_DFE_EN_OVRD_EN 11 11 TX_DATA_EN_ATE_OVRD_VAL 12 12 TX_DATA_EN_ATE_OVRD_EN 13 13 RX_DATA_EN_ATE_OVRD_VAL 14 14 RX_DATA_EN_ATE_OVRD_EN 15 15 ixDPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN 2 0x3019 3 0 4294967295 RX_EQ_DELTA_IQ_OVRD_VAL 0 3 RX_EQ_DELTA_IQ_OVRD_EN 4 4 RESERVED_15_5 5 15 ixDPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN 2 0x301a 5 0 4294967295 RX_TERM_CTRL_OVRD_VAL 0 2 RX_TERM_CTRL_OVRD_EN 3 3 TX_TERM_CTRL_OVRD_VAL 4 6 TX_TERM_CTRL_OVRD_EN 7 7 RESERVED_15_8 8 15 ixDPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TXRX_TERM_CTRL_IN 2 0x301b 3 0 4294967295 RX_TERM_CTRL 0 2 TX_TERM_CTRL 3 5 RESERVED_15_6 6 15 ixDPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT_1 2 0x301c 2 0 4294967295 RX_CLK_EN 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_EQ_OVRD_IN_1 2 0x301d 4 0 4294967295 RX_EQ_AFE_GAIN_OVRD_VAL 0 3 RX_EQ_ATT_LVL_OVRD_VAL 4 6 RX_EQ_OVRD_EN 7 7 RESERVED_15_8 8 15 ixDPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_EQ_OVRD_IN_2 2 0x301e 3 0 4294967295 RX_EQ_DFE_TAP1_OVRD_VAL 0 7 RX_EQ_CTLE_BOOST_OVRD_VAL 8 12 RESERVED_15_13 13 15 ixDPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_PH2_CAL 2 0x301f 4 0 4294967295 PH2_CAL_ACK_VAL 0 0 PH2_CAL_REQ_VAL 1 1 PH2_CAL_REQ_OVRD_VAL 2 2 RESERVED_15_3 3 15 ixDPCSSYS_CR4_RAWLANE0_DIG_FSM_FSM_OVRD_CTL 2 0x3020 5 0 4294967295 FSM_JMP_ADDR 0 11 FSM_JMP_EN 12 12 FSM_CMD_START 13 13 FSM_OVRD_EN 14 14 FSM_BREAK 15 15 ixDPCSSYS_CR4_RAWLANE0_DIG_FSM_MEM_ADDR_MON 2 0x3021 1 0 4294967295 MEM_ADDR 0 15 ixDPCSSYS_CR4_RAWLANE0_DIG_FSM_STATUS_MON 2 0x3022 8 0 4294967295 STATE 0 4 CMD_RDY 5 5 ALU_OVFLW 6 6 ALU_RES_EQ0 7 7 WAIT_CNT_EQ0 8 8 WRMSK_DISABLED 9 9 RDMSK_DISABLED 10 10 RESERVED_15_11 11 15 ixDPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_RX_STARTUP_CAL 2 0x3023 2 0 4294967295 FAST_RX_STARTUP_CAL 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_RX_ADAPT 2 0x3024 2 0 4294967295 FAST_RX_ADAPT 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_RX_AFE_CAL 2 0x3025 2 0 4294967295 FAST_RX_AFE_CAL 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_RX_DFE_CAL 2 0x3026 2 0 4294967295 FAST_RX_DFE_CAL 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_RX_BYPASS_CAL 2 0x3027 2 0 4294967295 FAST_RX_BYPASS_CAL 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_RX_REFLVL_CAL 2 0x3028 2 0 4294967295 FAST_RX_REFLVL_CAL 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_RX_IQ_CAL 2 0x3029 2 0 4294967295 FAST_RX_IQ_CAL 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_RX_AFE_ADAPT 2 0x302a 2 0 4294967295 FAST_RX_AFE_ADAPT 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_RX_DFE_ADAPT 2 0x302b 2 0 4294967295 FAST_RX_DFE_ADAPT 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_SUP 2 0x302c 2 0 4294967295 FAST_SUP 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_TX_CMN_MODE 2 0x302d 2 0 4294967295 FAST_TX_CMN_MODE 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_TX_RXDET 2 0x302e 2 0 4294967295 FAST_TX_RXDET 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_RX_PWRUP 2 0x302f 2 0 4294967295 FAST_RX_PWRUP 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_RX_VCO_WAIT 2 0x3030 2 0 4294967295 FAST_RX_VCO_WAIT 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_RX_VCO_CAL 2 0x3031 2 0 4294967295 FAST_RX_VCO_CAL 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR4_RAWLANE0_DIG_FSM_CMNCAL_MPLL_STATUS 2 0x3032 3 0 4294967295 CMNCAL_MPLL_INIT 0 0 CMNCAL_MPLL_DONE 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_RX_CONT_CAL_ADAPT 2 0x3033 2 0 4294967295 FAST_RX_CONT_CAL_ADAPT 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_RX_CONT_ADAPT 2 0x3034 2 0 4294967295 FAST_RX_CONT_ADAPT 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_RX_CONT_DATA_CAL 2 0x3035 2 0 4294967295 FAST_RX_CONT_DATA_CAL 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_RX_CONT_PHASE_CAL 2 0x3036 2 0 4294967295 FAST_RX_CONT_PHASE_CAL 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_RX_CONT_AFE_CAL 2 0x3037 2 0 4294967295 FAST_RX_CONT_AFE_CAL 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_FLAGS 2 0x3038 12 0 4294967295 TX_FAST_DCC_CAL 0 0 RX_FAST_DCC_CAL 1 1 RX_FAST_VPHUD_CAL 2 2 RX_FAST_VREF_CAL 3 3 RX_FAST_SIGDET_CAL 4 4 RESERVED_2 5 7 TX_FAST_CONT_DCC_CAL 8 8 RX_FAST_CONT_DCC_CAL 9 9 RX_FAST_CONT_VPHUD_CAL 10 10 RX_FAST_CONT_VREF_CAL 11 11 RESERVED_1 12 14 TX_SKIP_SUP_CAL 15 15 ixDPCSSYS_CR4_RAWLANE0_DIG_FSM_CR_LOCK 2 0x3039 3 0 4294967295 CR_REG_LOCK 0 0 CR_MEM_LOCK 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR4_RAWLANE0_DIG_FSM_TX_DCC_FLAGS 2 0x303a 4 0 4294967295 RATE 0 0 DIV 1 1 MPLL 2 2 RESERVED_15_3 3 15 ixDPCSSYS_CR4_RAWLANE0_DIG_FSM_TX_DCC_STATUS 2 0x303b 2 0 4294967295 FLAG 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR4_RAWLANE0_DIG_FSM_OCLA 2 0x303c 4 0 4294967295 PC_EN 0 0 REG_BANK1_EN 1 1 REG_BANK2_EN 2 2 RESERVED_15_3 3 15 ixDPCSSYS_CR4_RAWLANE0_DIG_FSM_TX_EQ_UPDATE_FLAG 2 0x303d 2 0 4294967295 TX_EQ_UPDATE_FLAG 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR4_RAWLANE0_DIG_FSM_CMNCAL_RCAL_STATUS 2 0x303e 3 0 4294967295 CMNCAL_RCAL_INIT 0 0 CMNCAL_RCAL_DONE 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR4_RAWLANE0_DIG_FSM_RX_IQ_PHASE_OFFSET 2 0x303f 2 0 4294967295 RX_IQ_PHASE_OFFSET 0 3 RESERVED_15_4 4 15 ixDPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_RESET_RTN_REQ 2 0x3040 2 0 4294967295 RESET_RTN_REQ 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_RX_RESET_IRQ 2 0x3041 2 0 4294967295 RX_RESET 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_RX_REQ_IRQ 2 0x3042 2 0 4294967295 RX_REQ 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_RX_RATE_IRQ 2 0x3043 2 0 4294967295 RX_RATE_IRQ 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_RX_PSTATE_IRQ 2 0x3044 2 0 4294967295 RX_PSTATE_IRQ 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ 2 0x3045 2 0 4294967295 RX_ADAPT_REQ_IRQ 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ 2 0x3046 2 0 4294967295 RX_ADAPT_DIS_IRQ 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_RX_RESET_IRQ_CLR 2 0x3047 2 0 4294967295 RX_RESET_IRQ_CLR 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_RX_REQ_IRQ_CLR 2 0x3048 2 0 4294967295 RX_REQ_IRQ_CLR 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_RX_RATE_IRQ_CLR 2 0x3049 2 0 4294967295 RX_RATE_IRQ_CLR 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR 2 0x304a 2 0 4294967295 RX_PSTATE_IRQ_CLR 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR 2 0x304b 2 0 4294967295 RX_ADAPT_REQ_IRQ_CLR 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR 2 0x304c 2 0 4294967295 RX_ADAPT_DIS_IRQ_CLR 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK 2 0x304d 12 0 4294967295 RX_REQ_IRQ_MSK 0 0 RX_RATE_IRQ_MSK 1 1 RX_PSTATE_IRQ_MSK 2 2 RX_ADAPT_REQ_IRQ_MSK 3 3 RX_ADAPT_DIS_IRQ_MSK 4 4 RX_RESET_IRQ_MSK 5 5 LANE_XCVR_MODE_IRQ_MSK 6 6 RX_PH2_CAL_REQ_IRQ_MSK 7 7 RX_PH2_CAL_DIS_IRQ_MSK 8 8 LANE_RX2TX_SER_LB_EN_IRQ_MSK 9 9 DCC_ONDMD_IRQ_MSK 10 10 RESERVED_15_11 11 15 ixDPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK_2 2 0x304e 3 0 4294967295 TX_RESET_IRQ_MSK 0 0 TX_REQ_IRQ_MSK 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ 2 0x304f 2 0 4294967295 LANE_XCVR_MODE_IRQ 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR 2 0x3050 2 0 4294967295 LANE_XCVR_MODE_IRQ_CLR 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ 2 0x3051 2 0 4294967295 RX_PH2_CAL_REQ_IRQ 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ 2 0x3052 2 0 4294967295 RX_PH2_CAL_DIS_IRQ 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR 2 0x3053 2 0 4294967295 RX_PH2_CAL_REQ_IRQ_CLR 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR 2 0x3054 2 0 4294967295 RX_PH2_CAL_DIS_IRQ_CLR 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ 2 0x3055 2 0 4294967295 LANE_RX2TX_SER_LB_EN_IRQ 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR 2 0x3056 2 0 4294967295 LANE_RX2TX_SER_LB_EN_IRQ_CLR 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_DCC_ONDMD_IRQ 2 0x3057 2 0 4294967295 IRQ 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_TX_RESET_IRQ 2 0x3058 2 0 4294967295 TX_RESET 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_TX_REQ_IRQ 2 0x3059 2 0 4294967295 TX_REQ 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_TX_RESET_IRQ_CLR 2 0x305a 2 0 4294967295 TX_RESET_IRQ_CLR 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_TX_REQ_IRQ_CLR 2 0x305b 2 0 4294967295 TX_REQ_IRQ_CLR 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_LANE_OVRD_IN 2 0x3060 4 0 4294967295 LANE_MPLLA_EN_IN 0 0 LANE_MPLLB_EN_IN 1 1 LANE_OVRD_EN 2 2 RESERVED_15_3 3 15 ixDPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_LANE_OVRD_OUT 2 0x3061 4 0 4294967295 LANE_MPLLA_EN_OUT 0 0 LANE_MPLLB_EN_OUT 1 1 LANE_OVRD_EN 2 2 RESERVED_15_3 3 15 ixDPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_SUP_OVRD_IN 2 0x3062 4 0 4294967295 MPLLA_STATE 0 0 MPLLB_STATE 1 1 SUP_STATE_OVRD_EN 2 2 RESERVED_15_3 3 15 ixDPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_SUP_PMA_IN 2 0x3063 3 0 4294967295 MPLLA_STATE 0 0 MPLLB_STATE 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT 2 0x3064 16 0 4294967295 TX_REQ_OVRD_VAL 0 0 TX_REQ_OVRD_EN 1 1 TX_RESET_OVRD_VAL 2 2 TX_RESET_OVRD_EN 3 3 TX_BEACON_EN_OVRD_VAL 4 4 TX_BEACON_EN_OVRD_EN 5 5 TX_ASYNC_DRV_EN_OVRD_VAL 6 6 TX_ASYNC_DRV_EN_OVRD_EN 7 7 TX_ASYNC_EN_OVRD_VAL 8 8 TX_ASYNC_EN_OVRD_EN 9 9 TX_DWORD_CLK_SYNC_OVRD_VAL 10 10 TX_DWORD_CLK_SYNC_OVRD_EN 11 11 LANE_TX2RX_SER_LB_EN_OVRD_VAL 12 12 LANE_TX2RX_SER_LB_EN_OVRD_EN 13 13 TX_PMA_DATA_EN_OVRD_VAL_R 14 14 TX_PMA_DATA_EN_OVRD_EN_R 15 15 ixDPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_TX_PMA_IN 2 0x3065 2 0 4294967295 ACK 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT 2 0x3066 9 0 4294967295 RX_REQ_OVRD_VAL 0 0 RX_REQ_OVRD_EN 1 1 RX_RESET_OVRD_VAL 2 2 RX_RESET_OVRD_EN 3 3 LANE_RX2TX_PAR_LB_EN_OVRD_VAL 4 4 LANE_RX2TX_PAR_LB_EN_OVRD_EN 5 5 RX_PMA_DATA_EN_OVRD_VAL_R 6 6 RX_PMA_DATA_EN_OVRD_EN_R 7 7 RESERVED_15_8 8 15 ixDPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_RX_PMA_IN 2 0x3067 2 0 4294967295 ACK 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_LANE_RTUNE_CTL 2 0x3068 2 0 4294967295 LANE_RTUNE_REQ 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_SUP_PMA_IN_1 2 0x3069 2 0 4294967295 RTUNE_ACK 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_IN 2 0x306a 9 0 4294967295 RX_PMA_PWM_WORD_CLK_R 0 0 RX_PMA_PWM_WORD_CLK_OVRD_EN 1 1 RX_PMA_PWM_DATA_R 2 2 RX_PMA_PWM_DATA_OVRD_EN 3 3 RX_PMA_PWM_CLK_R 4 4 RX_PMA_PWM_CLK_OVRD_EN 5 5 RX_PMA_TERM_CTL_R 6 7 RX_PMA_TERM_CTL_OVRD_EN 8 8 RESERVED_15_9 9 15 ixDPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_OUT 2 0x306b 7 0 4294967295 RX_PMA_PWM_EN 0 0 RX_PMA_PWM_EN_OVRD_EN 1 1 RX_PMA_PWM_CLK_SEL 2 3 RX_PMA_PWM_CLK_SEL_OVRD_EN 4 4 RX_PMA_ASYNC_EN 5 5 RX_PMA_ASYNC_EN_OVRD_EN 6 6 RESERVED_15_7 7 15 ixDPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_RX_ADAPT_OVRD_OUT 2 0x306c 3 0 4294967295 RX_PMA_IQ_PHASE_ADJUST_MAP_OVRD_VAL 0 6 RX_PMA_IQ_PHASE_ADJUST_MAP_OVRD_EN 7 7 RESERVED_15_8 8 15 ixDPCSSYS_CR4_RAWLANE0_DIG_TX_CTL_TX_FSM_CTL 2 0x3080 6 0 4294967295 TX_WAIT_MPLL_OFF_TIME 0 6 TX_P2_ALLOW_RXDET 7 7 TX_P1_ALLOW_RXDET 8 8 TX_P0S_ALLOW_RXDET 9 9 TX_P0_ALLOW_RXDET 10 10 RESERVED_15_11 11 15 ixDPCSSYS_CR4_RAWLANE0_DIG_TX_CTL_TX_CLK_CTL 2 0x3081 4 0 4294967295 TX_CLK_EN 0 0 TX_CLK_SEL 1 4 ASYNC_BEACON_WAIT_TIME 5 10 RESERVED_15_11 11 15 ixDPCSSYS_CR4_RAWLANE0_DIG_TX_CTL_TX_DCC_CONT_STATUS 2 0x3082 2 0 4294967295 ENABLE 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR4_RAWLANE0_DIG_TX_CTL_OCLA 2 0x3083 2 0 4294967295 FSM_EN 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR4_RAWLANE0_DIG_TX_CTL_UPCS_OCLA 2 0x3084 3 0 4294967295 DATA_EN 0 1 CLK_EN 2 2 RESERVED_15_3 3 15 ixDPCSSYS_CR4_RAWLANE0_DIG_RX_CTL_RX_FSM_CTL 2 0x30a0 3 0 4294967295 EN_RX_CTL_FSM 0 0 RATE_CHG_IN_P1 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR4_RAWLANE0_DIG_RX_CTL_RX_LOS_MASK_CTL 2 0x30a1 2 0 4294967295 RX_LOS_MASK_CNT 0 8 RESERVED_15_9 9 15 ixDPCSSYS_CR4_RAWLANE0_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL 2 0x30a2 2 0 4294967295 RX_DATA_EN_OVRD_CNT 0 4 INT_REF_TRCK_CNT 5 15 ixDPCSSYS_CR4_RAWLANE0_DIG_RX_CTL_OFFCAN_CONT_STATUS 2 0x30a3 2 0 4294967295 ENABLE 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR4_RAWLANE0_DIG_RX_CTL_ADAPT_CONT_STATUS 2 0x30a4 2 0 4294967295 ENABLE 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR4_RAWLANE0_DIG_RX_CTL_UPCS_OCLA 2 0x30a5 3 0 4294967295 DATA_EN 0 2 CLK_EN 3 3 RESERVED_15_4 4 15 ixDPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN 2 0x30c0 11 0 4294967295 RATE_OVRD_VAL 0 1 RATE_OVRD_EN 2 2 WIDTH_OVRD_VAL 3 4 WIDTH_OVRD_EN 5 5 PSTATE_OVRD_VAL 6 7 PSTATE_OVRD_EN 8 8 LPD_OVRD_VAL 9 9 LPD_OVRD_EN 10 10 LANE_RX2TX_PAR_LB_EN_OVRD_VAL 11 11 LANE_RX2TX_PAR_LB_EN_OVRD_EN 12 12 RESERVED_15_13 13 15 ixDPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN 2 0x30c1 12 0 4294967295 PSTATE 0 1 LPD 2 2 WIDTH 3 4 RATE 5 7 MPLLB_SEL 8 8 MPLL_EN 9 9 OVRD_EN 10 10 MSTR_MPLLA_STATE 11 11 MSTR_MPLLB_STATE 12 12 MSTR_MPLL_OVRD_EN 13 13 TX_ASYNC_EN_OVR_VAL 14 14 TX_ASYNC_EN_OVR_EN 15 15 ixDPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1 2 0x30c2 13 0 4294967295 DETRX_REQ_OVRD_VAL 0 0 DETRX_REQ_OVRD_EN 1 1 VBOOST_EN_OVRD_VAL 2 2 VBOOST_EN_OVRD_EN 3 3 IBOOST_LVL_OVRD_VAL 4 7 IBOOST_LVL_OVRD_EN 8 8 TX_BEACON_EN_OVR_VAL 9 9 TX_BEACON_EN_OVR_EN 10 10 LANE_TX2RX_SER_LB_EN_OVRD_VAL 11 11 LANE_TX2RX_SER_LB_EN_OVRD_EN 12 12 TX_ASYNC_DATA_OVRD_VAL 13 13 TX_ASYNC_DATA_OVRD_EN 14 14 RESERVED_15_15 15 15 ixDPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_MASTER_MPLL_LOOP 2 0x30c3 3 0 4294967295 MPLLB_LOOP_EN 0 0 MPLLA_LOOP_EN 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1 2 0x30c4 11 0 4294967295 RESERVED 0 1 RX_LOS_LFPS_EN_OVRD_VAL 2 2 RX_LOS_LFPS_EN_OVRD_EN 3 3 RX_LOS_THRSHLD_OVRD_VAL 4 6 RX_LOS_THRSHLD_OVRD_EN 7 7 ADAPT_REQ 8 8 ADAPT_REQ_OVRD_EN 9 9 ADAPT_CONT 10 10 OFFCAN_CONT 11 11 CONT_OVRD_EN 12 12 RESERVED_15_13 13 15 ixDPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_2 2 0x30c5 4 0 4294967295 VCO_LD_VAL_OVRD 0 12 VCO_LD_VAL_OVRD_EN 13 13 VCO_LOWFREQ_VAL_OVRD 14 14 VCO_LOWFREQ_VAL_OVRD_EN 15 15 ixDPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_3 2 0x30c6 3 0 4294967295 REF_LD_VAL_OVRD 0 6 REF_LD_VAL_OVRD_EN 7 7 RESERVED_15_8 8 15 ixDPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT_2 2 0x30c7 3 0 4294967295 RX_VALID 0 0 RX_VALID_OVRD_EN 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_2 2 0x30c8 7 0 4294967295 LANE_TX2RX_SER_LB_EN_OVRD_VAL 0 0 LANE_TX2RX_SER_LB_EN_OVRD_EN 1 1 TX_DATA_EN_OVRD_VAL_R 2 2 TX_DATA_EN_OVRD_EN_R 3 3 TX_ASYNC_DATA_OVRD_VAL_R 4 4 TX_ASYNC_DATA_OVRD_EN_R 5 5 RESERVED_15_6 6 15 ixDPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN 2 0x3100 12 0 4294967295 PSTATE 0 1 LPD 2 2 WIDTH 3 4 RATE 5 7 MPLLB_SEL 8 8 MPLL_EN 9 9 OVRD_EN 10 10 MSTR_MPLLA_STATE 11 11 MSTR_MPLLB_STATE 12 12 MSTR_MPLL_OVRD_EN 13 13 TX_ASYNC_EN_OVR_VAL 14 14 TX_ASYNC_EN_OVR_EN 15 15 ixDPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1 2 0x3101 13 0 4294967295 RESET_OVRD_VAL 0 0 RESET_OVRD_EN 1 1 REQ_OVRD_VAL 2 2 REQ_OVRD_EN 3 3 DETRX_REQ_OVRD_VAL 4 4 DETRX_REQ_OVRD_EN 5 5 VBOOST_EN_OVRD_VAL 6 6 VBOOST_EN_OVRD_EN 7 7 IBOOST_LVL_OVRD_VAL 8 11 IBOOST_LVL_OVRD_EN 12 12 TX_BEACON_EN_OVR_VAL 13 13 TX_BEACON_EN_OVR_EN 14 14 RESERVED_15_15 15 15 ixDPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_PCS_IN 2 0x3102 12 0 4294967295 RESET 0 0 REQ 1 1 PSTATE 2 3 LPD 4 4 WIDTH 5 6 RATE 7 9 MPLLB_SEL 10 10 MPLL_EN 11 11 MSTR_MPLLA_STATE 12 12 MSTR_MPLLB_STATE 13 13 DETRX_REQ 14 14 RESERVED_15_15 15 15 ixDPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_OVRD_OUT 2 0x3103 6 0 4294967295 ACK 0 0 DETRX_RESULT 1 1 EN_CTL 2 2 TX_DWORD_CLK_SYNC_OVRD_VAL 3 3 TX_DWORD_CLK_SYNC_OVRD_EN 4 4 RESERVED_15_5 5 15 ixDPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_PCS_OUT 2 0x3104 2 0 4294967295 ACK 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN 2 0x3105 12 0 4294967295 RATE 0 1 WIDTH 2 3 PSTATE 4 5 LPD 6 6 OVRD_EN 7 7 ADAPT_AFE_EN 8 8 ADAPT_DFE_EN 9 9 LANE_RX2TX_PAR_LB_EN_OVRD_VAL 10 10 LANE_RX2TX_PAR_LB_EN_OVRD_EN 11 11 RX_DATA_EN_OVRD_VAL_R 12 12 RX_DATA_EN_OVRD_EN_R 13 13 RESERVED_15_14 14 15 ixDPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1 2 0x3106 12 0 4294967295 RESET_OVRD_VAL 0 0 RESET_OVRD_EN 1 1 REQ_OVRD_VAL 2 2 REQ_OVRD_EN 3 3 RX_LOS_THRSHLD_OVRD_VAL 4 6 RX_LOS_THRSHLD_OVRD_EN 7 7 ADAPT_REQ 8 8 ADAPT_REQ_OVRD_EN 9 9 ADAPT_CONT 10 10 OFFCAN_CONT 11 11 CONT_OVRD_EN 12 12 RESERVED_15_13 13 15 ixDPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_2 2 0x3107 4 0 4294967295 VCO_LD_VAL_OVRD 0 12 VCO_LD_VAL_OVRD_EN 13 13 VCO_LOWFREQ_VAL_OVRD 14 14 VCO_LOWFREQ_VAL_OVRD_EN 15 15 ixDPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_3 2 0x3108 3 0 4294967295 REF_LD_VAL_OVRD 0 6 REF_LD_VAL_OVRD_EN 7 7 RESERVED_15_8 8 15 ixDPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_PCS_IN 2 0x3109 13 0 4294967295 REQ 0 0 RATE 1 2 WIDTH 3 4 PSTATE 5 6 LPD 7 7 CDR_VCO_LOWFREQ 8 8 ADAPT_AFE_EN 9 9 ADAPT_DFE_EN 10 10 ADAPT_REQ 11 11 ADAPT_CONT 12 12 OFFCAN_CONT 13 13 RESET 14 14 RESERVED_15_15 15 15 ixDPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_1 2 0x310a 2 0 4294967295 REF_LD_VAL 0 6 RESERVED_15_7 7 15 ixDPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_2 2 0x310b 2 0 4294967295 VCO_LD_VAL 0 12 RESERVED_15_13 13 15 ixDPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_3 2 0x310c 4 0 4294967295 EQ_ATT_LVL 0 2 EQ_VGA1_GAIN 3 6 EQ_VGA2_GAIN 7 10 EQ_CTLE_BOOST 11 15 ixDPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_4 2 0x310d 3 0 4294967295 EQ_CTLE_POLE 0 2 EQ_DFE_TAP1 3 10 RESERVED_15_11 11 15 ixDPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT 2 0x310e 3 0 4294967295 ACK 0 0 EN_CTL 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_PCS_OUT 2 0x310f 2 0 4294967295 ACK 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_ADAPT_ACK 2 0x3110 2 0 4294967295 RX_ADAPT_ACK 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_ADAPT_FOM 2 0x3111 2 0 4294967295 RX_ADAPT_FOM 0 7 RESERVED_15_8 8 15 ixDPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_TXPRE_DIR 2 0x3112 2 0 4294967295 RX_TXPRE_DIR 0 1 RESERVED_15_2 2 15 ixDPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_TXMAIN_DIR 2 0x3113 2 0 4294967295 RX_TXMAIN_DIR 0 1 RESERVED_15_2 2 15 ixDPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_TXPOST_DIR 2 0x3114 2 0 4294967295 RX_TXPOST_DIR 0 1 RESERVED_15_2 2 15 ixDPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_LANE_NUMBER 2 0x3115 2 0 4294967295 LANE_NUMBER 0 3 RESERVED_15_4 4 15 ixDPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RESERVED_1 2 0x3116 1 0 4294967295 RESERVED_REG_1 0 15 ixDPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RESERVED_2 2 0x3117 1 0 4294967295 RESERVED_REG_2 0 15 ixDPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN 2 0x3118 16 0 4294967295 RX_RESET_ATE_OVRD_VAL 0 0 RX_RESET_ATE_OVRD_EN 1 1 TX_RESET_ATE_OVRD_VAL 2 2 TX_RESET_ATE_OVRD_EN 3 3 RX_REQ_ATE_OVRD_VAL 4 4 RX_REQ_ATE_OVRD_EN 5 5 TX_REQ_ATE_OVRD_VAL 6 6 TX_REQ_ATE_OVRD_EN 7 7 RX_ADAPT_AFE_EN_OVRD_VAL 8 8 RX_ADAPT_AFE_EN_OVRD_EN 9 9 RX_ADAPT_DFE_EN_OVRD_VAL 10 10 RX_ADAPT_DFE_EN_OVRD_EN 11 11 TX_DATA_EN_ATE_OVRD_VAL 12 12 TX_DATA_EN_ATE_OVRD_EN 13 13 RX_DATA_EN_ATE_OVRD_VAL 14 14 RX_DATA_EN_ATE_OVRD_EN 15 15 ixDPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN 2 0x3119 3 0 4294967295 RX_EQ_DELTA_IQ_OVRD_VAL 0 3 RX_EQ_DELTA_IQ_OVRD_EN 4 4 RESERVED_15_5 5 15 ixDPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN 2 0x311a 5 0 4294967295 RX_TERM_CTRL_OVRD_VAL 0 2 RX_TERM_CTRL_OVRD_EN 3 3 TX_TERM_CTRL_OVRD_VAL 4 6 TX_TERM_CTRL_OVRD_EN 7 7 RESERVED_15_8 8 15 ixDPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TXRX_TERM_CTRL_IN 2 0x311b 3 0 4294967295 RX_TERM_CTRL 0 2 TX_TERM_CTRL 3 5 RESERVED_15_6 6 15 ixDPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT_1 2 0x311c 2 0 4294967295 RX_CLK_EN 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_EQ_OVRD_IN_1 2 0x311d 4 0 4294967295 RX_EQ_AFE_GAIN_OVRD_VAL 0 3 RX_EQ_ATT_LVL_OVRD_VAL 4 6 RX_EQ_OVRD_EN 7 7 RESERVED_15_8 8 15 ixDPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_EQ_OVRD_IN_2 2 0x311e 3 0 4294967295 RX_EQ_DFE_TAP1_OVRD_VAL 0 7 RX_EQ_CTLE_BOOST_OVRD_VAL 8 12 RESERVED_15_13 13 15 ixDPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_PH2_CAL 2 0x311f 4 0 4294967295 PH2_CAL_ACK_VAL 0 0 PH2_CAL_REQ_VAL 1 1 PH2_CAL_REQ_OVRD_VAL 2 2 RESERVED_15_3 3 15 ixDPCSSYS_CR4_RAWLANE1_DIG_FSM_FSM_OVRD_CTL 2 0x3120 5 0 4294967295 FSM_JMP_ADDR 0 11 FSM_JMP_EN 12 12 FSM_CMD_START 13 13 FSM_OVRD_EN 14 14 FSM_BREAK 15 15 ixDPCSSYS_CR4_RAWLANE1_DIG_FSM_MEM_ADDR_MON 2 0x3121 1 0 4294967295 MEM_ADDR 0 15 ixDPCSSYS_CR4_RAWLANE1_DIG_FSM_STATUS_MON 2 0x3122 8 0 4294967295 STATE 0 4 CMD_RDY 5 5 ALU_OVFLW 6 6 ALU_RES_EQ0 7 7 WAIT_CNT_EQ0 8 8 WRMSK_DISABLED 9 9 RDMSK_DISABLED 10 10 RESERVED_15_11 11 15 ixDPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_RX_STARTUP_CAL 2 0x3123 2 0 4294967295 FAST_RX_STARTUP_CAL 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_RX_ADAPT 2 0x3124 2 0 4294967295 FAST_RX_ADAPT 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_RX_AFE_CAL 2 0x3125 2 0 4294967295 FAST_RX_AFE_CAL 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_RX_DFE_CAL 2 0x3126 2 0 4294967295 FAST_RX_DFE_CAL 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_RX_BYPASS_CAL 2 0x3127 2 0 4294967295 FAST_RX_BYPASS_CAL 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_RX_REFLVL_CAL 2 0x3128 2 0 4294967295 FAST_RX_REFLVL_CAL 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_RX_IQ_CAL 2 0x3129 2 0 4294967295 FAST_RX_IQ_CAL 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_RX_AFE_ADAPT 2 0x312a 2 0 4294967295 FAST_RX_AFE_ADAPT 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_RX_DFE_ADAPT 2 0x312b 2 0 4294967295 FAST_RX_DFE_ADAPT 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_SUP 2 0x312c 2 0 4294967295 FAST_SUP 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_TX_CMN_MODE 2 0x312d 2 0 4294967295 FAST_TX_CMN_MODE 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_TX_RXDET 2 0x312e 2 0 4294967295 FAST_TX_RXDET 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_RX_PWRUP 2 0x312f 2 0 4294967295 FAST_RX_PWRUP 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_RX_VCO_WAIT 2 0x3130 2 0 4294967295 FAST_RX_VCO_WAIT 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_RX_VCO_CAL 2 0x3131 2 0 4294967295 FAST_RX_VCO_CAL 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR4_RAWLANE1_DIG_FSM_CMNCAL_MPLL_STATUS 2 0x3132 3 0 4294967295 CMNCAL_MPLL_INIT 0 0 CMNCAL_MPLL_DONE 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_RX_CONT_CAL_ADAPT 2 0x3133 2 0 4294967295 FAST_RX_CONT_CAL_ADAPT 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_RX_CONT_ADAPT 2 0x3134 2 0 4294967295 FAST_RX_CONT_ADAPT 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_RX_CONT_DATA_CAL 2 0x3135 2 0 4294967295 FAST_RX_CONT_DATA_CAL 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_RX_CONT_PHASE_CAL 2 0x3136 2 0 4294967295 FAST_RX_CONT_PHASE_CAL 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_RX_CONT_AFE_CAL 2 0x3137 2 0 4294967295 FAST_RX_CONT_AFE_CAL 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_FLAGS 2 0x3138 12 0 4294967295 TX_FAST_DCC_CAL 0 0 RX_FAST_DCC_CAL 1 1 RX_FAST_VPHUD_CAL 2 2 RX_FAST_VREF_CAL 3 3 RX_FAST_SIGDET_CAL 4 4 RESERVED_2 5 7 TX_FAST_CONT_DCC_CAL 8 8 RX_FAST_CONT_DCC_CAL 9 9 RX_FAST_CONT_VPHUD_CAL 10 10 RX_FAST_CONT_VREF_CAL 11 11 RESERVED_1 12 14 TX_SKIP_SUP_CAL 15 15 ixDPCSSYS_CR4_RAWLANE1_DIG_FSM_CR_LOCK 2 0x3139 3 0 4294967295 CR_REG_LOCK 0 0 CR_MEM_LOCK 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR4_RAWLANE1_DIG_FSM_TX_DCC_FLAGS 2 0x313a 4 0 4294967295 RATE 0 0 DIV 1 1 MPLL 2 2 RESERVED_15_3 3 15 ixDPCSSYS_CR4_RAWLANE1_DIG_FSM_TX_DCC_STATUS 2 0x313b 2 0 4294967295 FLAG 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR4_RAWLANE1_DIG_FSM_OCLA 2 0x313c 4 0 4294967295 PC_EN 0 0 REG_BANK1_EN 1 1 REG_BANK2_EN 2 2 RESERVED_15_3 3 15 ixDPCSSYS_CR4_RAWLANE1_DIG_FSM_TX_EQ_UPDATE_FLAG 2 0x313d 2 0 4294967295 TX_EQ_UPDATE_FLAG 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR4_RAWLANE1_DIG_FSM_CMNCAL_RCAL_STATUS 2 0x313e 3 0 4294967295 CMNCAL_RCAL_INIT 0 0 CMNCAL_RCAL_DONE 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR4_RAWLANE1_DIG_FSM_RX_IQ_PHASE_OFFSET 2 0x313f 2 0 4294967295 RX_IQ_PHASE_OFFSET 0 3 RESERVED_15_4 4 15 ixDPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_RESET_RTN_REQ 2 0x3140 2 0 4294967295 RESET_RTN_REQ 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_RX_RESET_IRQ 2 0x3141 2 0 4294967295 RX_RESET 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_RX_REQ_IRQ 2 0x3142 2 0 4294967295 RX_REQ 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_RX_RATE_IRQ 2 0x3143 2 0 4294967295 RX_RATE_IRQ 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_RX_PSTATE_IRQ 2 0x3144 2 0 4294967295 RX_PSTATE_IRQ 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ 2 0x3145 2 0 4294967295 RX_ADAPT_REQ_IRQ 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ 2 0x3146 2 0 4294967295 RX_ADAPT_DIS_IRQ 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_RX_RESET_IRQ_CLR 2 0x3147 2 0 4294967295 RX_RESET_IRQ_CLR 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_RX_REQ_IRQ_CLR 2 0x3148 2 0 4294967295 RX_REQ_IRQ_CLR 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_RX_RATE_IRQ_CLR 2 0x3149 2 0 4294967295 RX_RATE_IRQ_CLR 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR 2 0x314a 2 0 4294967295 RX_PSTATE_IRQ_CLR 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR 2 0x314b 2 0 4294967295 RX_ADAPT_REQ_IRQ_CLR 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR 2 0x314c 2 0 4294967295 RX_ADAPT_DIS_IRQ_CLR 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK 2 0x314d 12 0 4294967295 RX_REQ_IRQ_MSK 0 0 RX_RATE_IRQ_MSK 1 1 RX_PSTATE_IRQ_MSK 2 2 RX_ADAPT_REQ_IRQ_MSK 3 3 RX_ADAPT_DIS_IRQ_MSK 4 4 RX_RESET_IRQ_MSK 5 5 LANE_XCVR_MODE_IRQ_MSK 6 6 RX_PH2_CAL_REQ_IRQ_MSK 7 7 RX_PH2_CAL_DIS_IRQ_MSK 8 8 LANE_RX2TX_SER_LB_EN_IRQ_MSK 9 9 DCC_ONDMD_IRQ_MSK 10 10 RESERVED_15_11 11 15 ixDPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK_2 2 0x314e 3 0 4294967295 TX_RESET_IRQ_MSK 0 0 TX_REQ_IRQ_MSK 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ 2 0x314f 2 0 4294967295 LANE_XCVR_MODE_IRQ 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR 2 0x3150 2 0 4294967295 LANE_XCVR_MODE_IRQ_CLR 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ 2 0x3151 2 0 4294967295 RX_PH2_CAL_REQ_IRQ 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ 2 0x3152 2 0 4294967295 RX_PH2_CAL_DIS_IRQ 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR 2 0x3153 2 0 4294967295 RX_PH2_CAL_REQ_IRQ_CLR 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR 2 0x3154 2 0 4294967295 RX_PH2_CAL_DIS_IRQ_CLR 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ 2 0x3155 2 0 4294967295 LANE_RX2TX_SER_LB_EN_IRQ 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR 2 0x3156 2 0 4294967295 LANE_RX2TX_SER_LB_EN_IRQ_CLR 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_DCC_ONDMD_IRQ 2 0x3157 2 0 4294967295 IRQ 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_TX_RESET_IRQ 2 0x3158 2 0 4294967295 TX_RESET 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_TX_REQ_IRQ 2 0x3159 2 0 4294967295 TX_REQ 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_TX_RESET_IRQ_CLR 2 0x315a 2 0 4294967295 TX_RESET_IRQ_CLR 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_TX_REQ_IRQ_CLR 2 0x315b 2 0 4294967295 TX_REQ_IRQ_CLR 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_LANE_OVRD_IN 2 0x3160 4 0 4294967295 LANE_MPLLA_EN_IN 0 0 LANE_MPLLB_EN_IN 1 1 LANE_OVRD_EN 2 2 RESERVED_15_3 3 15 ixDPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_LANE_OVRD_OUT 2 0x3161 4 0 4294967295 LANE_MPLLA_EN_OUT 0 0 LANE_MPLLB_EN_OUT 1 1 LANE_OVRD_EN 2 2 RESERVED_15_3 3 15 ixDPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_SUP_OVRD_IN 2 0x3162 4 0 4294967295 MPLLA_STATE 0 0 MPLLB_STATE 1 1 SUP_STATE_OVRD_EN 2 2 RESERVED_15_3 3 15 ixDPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_SUP_PMA_IN 2 0x3163 3 0 4294967295 MPLLA_STATE 0 0 MPLLB_STATE 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT 2 0x3164 16 0 4294967295 TX_REQ_OVRD_VAL 0 0 TX_REQ_OVRD_EN 1 1 TX_RESET_OVRD_VAL 2 2 TX_RESET_OVRD_EN 3 3 TX_BEACON_EN_OVRD_VAL 4 4 TX_BEACON_EN_OVRD_EN 5 5 TX_ASYNC_DRV_EN_OVRD_VAL 6 6 TX_ASYNC_DRV_EN_OVRD_EN 7 7 TX_ASYNC_EN_OVRD_VAL 8 8 TX_ASYNC_EN_OVRD_EN 9 9 TX_DWORD_CLK_SYNC_OVRD_VAL 10 10 TX_DWORD_CLK_SYNC_OVRD_EN 11 11 LANE_TX2RX_SER_LB_EN_OVRD_VAL 12 12 LANE_TX2RX_SER_LB_EN_OVRD_EN 13 13 TX_PMA_DATA_EN_OVRD_VAL_R 14 14 TX_PMA_DATA_EN_OVRD_EN_R 15 15 ixDPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_TX_PMA_IN 2 0x3165 2 0 4294967295 ACK 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT 2 0x3166 9 0 4294967295 RX_REQ_OVRD_VAL 0 0 RX_REQ_OVRD_EN 1 1 RX_RESET_OVRD_VAL 2 2 RX_RESET_OVRD_EN 3 3 LANE_RX2TX_PAR_LB_EN_OVRD_VAL 4 4 LANE_RX2TX_PAR_LB_EN_OVRD_EN 5 5 RX_PMA_DATA_EN_OVRD_VAL_R 6 6 RX_PMA_DATA_EN_OVRD_EN_R 7 7 RESERVED_15_8 8 15 ixDPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_RX_PMA_IN 2 0x3167 2 0 4294967295 ACK 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_LANE_RTUNE_CTL 2 0x3168 2 0 4294967295 LANE_RTUNE_REQ 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_SUP_PMA_IN_1 2 0x3169 2 0 4294967295 RTUNE_ACK 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_IN 2 0x316a 9 0 4294967295 RX_PMA_PWM_WORD_CLK_R 0 0 RX_PMA_PWM_WORD_CLK_OVRD_EN 1 1 RX_PMA_PWM_DATA_R 2 2 RX_PMA_PWM_DATA_OVRD_EN 3 3 RX_PMA_PWM_CLK_R 4 4 RX_PMA_PWM_CLK_OVRD_EN 5 5 RX_PMA_TERM_CTL_R 6 7 RX_PMA_TERM_CTL_OVRD_EN 8 8 RESERVED_15_9 9 15 ixDPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_OUT 2 0x316b 7 0 4294967295 RX_PMA_PWM_EN 0 0 RX_PMA_PWM_EN_OVRD_EN 1 1 RX_PMA_PWM_CLK_SEL 2 3 RX_PMA_PWM_CLK_SEL_OVRD_EN 4 4 RX_PMA_ASYNC_EN 5 5 RX_PMA_ASYNC_EN_OVRD_EN 6 6 RESERVED_15_7 7 15 ixDPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_RX_ADAPT_OVRD_OUT 2 0x316c 3 0 4294967295 RX_PMA_IQ_PHASE_ADJUST_MAP_OVRD_VAL 0 6 RX_PMA_IQ_PHASE_ADJUST_MAP_OVRD_EN 7 7 RESERVED_15_8 8 15 ixDPCSSYS_CR4_RAWLANE1_DIG_TX_CTL_TX_FSM_CTL 2 0x3180 6 0 4294967295 TX_WAIT_MPLL_OFF_TIME 0 6 TX_P2_ALLOW_RXDET 7 7 TX_P1_ALLOW_RXDET 8 8 TX_P0S_ALLOW_RXDET 9 9 TX_P0_ALLOW_RXDET 10 10 RESERVED_15_11 11 15 ixDPCSSYS_CR4_RAWLANE1_DIG_TX_CTL_TX_CLK_CTL 2 0x3181 4 0 4294967295 TX_CLK_EN 0 0 TX_CLK_SEL 1 4 ASYNC_BEACON_WAIT_TIME 5 10 RESERVED_15_11 11 15 ixDPCSSYS_CR4_RAWLANE1_DIG_TX_CTL_TX_DCC_CONT_STATUS 2 0x3182 2 0 4294967295 ENABLE 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR4_RAWLANE1_DIG_TX_CTL_OCLA 2 0x3183 2 0 4294967295 FSM_EN 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR4_RAWLANE1_DIG_TX_CTL_UPCS_OCLA 2 0x3184 3 0 4294967295 DATA_EN 0 1 CLK_EN 2 2 RESERVED_15_3 3 15 ixDPCSSYS_CR4_RAWLANE1_DIG_RX_CTL_RX_FSM_CTL 2 0x31a0 3 0 4294967295 EN_RX_CTL_FSM 0 0 RATE_CHG_IN_P1 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR4_RAWLANE1_DIG_RX_CTL_RX_LOS_MASK_CTL 2 0x31a1 2 0 4294967295 RX_LOS_MASK_CNT 0 8 RESERVED_15_9 9 15 ixDPCSSYS_CR4_RAWLANE1_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL 2 0x31a2 2 0 4294967295 RX_DATA_EN_OVRD_CNT 0 4 INT_REF_TRCK_CNT 5 15 ixDPCSSYS_CR4_RAWLANE1_DIG_RX_CTL_OFFCAN_CONT_STATUS 2 0x31a3 2 0 4294967295 ENABLE 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR4_RAWLANE1_DIG_RX_CTL_ADAPT_CONT_STATUS 2 0x31a4 2 0 4294967295 ENABLE 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR4_RAWLANE1_DIG_RX_CTL_UPCS_OCLA 2 0x31a5 3 0 4294967295 DATA_EN 0 2 CLK_EN 3 3 RESERVED_15_4 4 15 ixDPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN 2 0x31c0 11 0 4294967295 RATE_OVRD_VAL 0 1 RATE_OVRD_EN 2 2 WIDTH_OVRD_VAL 3 4 WIDTH_OVRD_EN 5 5 PSTATE_OVRD_VAL 6 7 PSTATE_OVRD_EN 8 8 LPD_OVRD_VAL 9 9 LPD_OVRD_EN 10 10 LANE_RX2TX_PAR_LB_EN_OVRD_VAL 11 11 LANE_RX2TX_PAR_LB_EN_OVRD_EN 12 12 RESERVED_15_13 13 15 ixDPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN 2 0x31c1 12 0 4294967295 PSTATE 0 1 LPD 2 2 WIDTH 3 4 RATE 5 7 MPLLB_SEL 8 8 MPLL_EN 9 9 OVRD_EN 10 10 MSTR_MPLLA_STATE 11 11 MSTR_MPLLB_STATE 12 12 MSTR_MPLL_OVRD_EN 13 13 TX_ASYNC_EN_OVR_VAL 14 14 TX_ASYNC_EN_OVR_EN 15 15 ixDPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1 2 0x31c2 13 0 4294967295 DETRX_REQ_OVRD_VAL 0 0 DETRX_REQ_OVRD_EN 1 1 VBOOST_EN_OVRD_VAL 2 2 VBOOST_EN_OVRD_EN 3 3 IBOOST_LVL_OVRD_VAL 4 7 IBOOST_LVL_OVRD_EN 8 8 TX_BEACON_EN_OVR_VAL 9 9 TX_BEACON_EN_OVR_EN 10 10 LANE_TX2RX_SER_LB_EN_OVRD_VAL 11 11 LANE_TX2RX_SER_LB_EN_OVRD_EN 12 12 TX_ASYNC_DATA_OVRD_VAL 13 13 TX_ASYNC_DATA_OVRD_EN 14 14 RESERVED_15_15 15 15 ixDPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_MASTER_MPLL_LOOP 2 0x31c3 3 0 4294967295 MPLLB_LOOP_EN 0 0 MPLLA_LOOP_EN 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1 2 0x31c4 11 0 4294967295 RESERVED 0 1 RX_LOS_LFPS_EN_OVRD_VAL 2 2 RX_LOS_LFPS_EN_OVRD_EN 3 3 RX_LOS_THRSHLD_OVRD_VAL 4 6 RX_LOS_THRSHLD_OVRD_EN 7 7 ADAPT_REQ 8 8 ADAPT_REQ_OVRD_EN 9 9 ADAPT_CONT 10 10 OFFCAN_CONT 11 11 CONT_OVRD_EN 12 12 RESERVED_15_13 13 15 ixDPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_2 2 0x31c5 4 0 4294967295 VCO_LD_VAL_OVRD 0 12 VCO_LD_VAL_OVRD_EN 13 13 VCO_LOWFREQ_VAL_OVRD 14 14 VCO_LOWFREQ_VAL_OVRD_EN 15 15 ixDPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_3 2 0x31c6 3 0 4294967295 REF_LD_VAL_OVRD 0 6 REF_LD_VAL_OVRD_EN 7 7 RESERVED_15_8 8 15 ixDPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT_2 2 0x31c7 3 0 4294967295 RX_VALID 0 0 RX_VALID_OVRD_EN 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_2 2 0x31c8 7 0 4294967295 LANE_TX2RX_SER_LB_EN_OVRD_VAL 0 0 LANE_TX2RX_SER_LB_EN_OVRD_EN 1 1 TX_DATA_EN_OVRD_VAL_R 2 2 TX_DATA_EN_OVRD_EN_R 3 3 TX_ASYNC_DATA_OVRD_VAL_R 4 4 TX_ASYNC_DATA_OVRD_EN_R 5 5 RESERVED_15_6 6 15 ixDPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN 2 0x3200 12 0 4294967295 PSTATE 0 1 LPD 2 2 WIDTH 3 4 RATE 5 7 MPLLB_SEL 8 8 MPLL_EN 9 9 OVRD_EN 10 10 MSTR_MPLLA_STATE 11 11 MSTR_MPLLB_STATE 12 12 MSTR_MPLL_OVRD_EN 13 13 TX_ASYNC_EN_OVR_VAL 14 14 TX_ASYNC_EN_OVR_EN 15 15 ixDPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1 2 0x3201 13 0 4294967295 RESET_OVRD_VAL 0 0 RESET_OVRD_EN 1 1 REQ_OVRD_VAL 2 2 REQ_OVRD_EN 3 3 DETRX_REQ_OVRD_VAL 4 4 DETRX_REQ_OVRD_EN 5 5 VBOOST_EN_OVRD_VAL 6 6 VBOOST_EN_OVRD_EN 7 7 IBOOST_LVL_OVRD_VAL 8 11 IBOOST_LVL_OVRD_EN 12 12 TX_BEACON_EN_OVR_VAL 13 13 TX_BEACON_EN_OVR_EN 14 14 RESERVED_15_15 15 15 ixDPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_PCS_IN 2 0x3202 12 0 4294967295 RESET 0 0 REQ 1 1 PSTATE 2 3 LPD 4 4 WIDTH 5 6 RATE 7 9 MPLLB_SEL 10 10 MPLL_EN 11 11 MSTR_MPLLA_STATE 12 12 MSTR_MPLLB_STATE 13 13 DETRX_REQ 14 14 RESERVED_15_15 15 15 ixDPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_OVRD_OUT 2 0x3203 6 0 4294967295 ACK 0 0 DETRX_RESULT 1 1 EN_CTL 2 2 TX_DWORD_CLK_SYNC_OVRD_VAL 3 3 TX_DWORD_CLK_SYNC_OVRD_EN 4 4 RESERVED_15_5 5 15 ixDPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_PCS_OUT 2 0x3204 2 0 4294967295 ACK 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN 2 0x3205 12 0 4294967295 RATE 0 1 WIDTH 2 3 PSTATE 4 5 LPD 6 6 OVRD_EN 7 7 ADAPT_AFE_EN 8 8 ADAPT_DFE_EN 9 9 LANE_RX2TX_PAR_LB_EN_OVRD_VAL 10 10 LANE_RX2TX_PAR_LB_EN_OVRD_EN 11 11 RX_DATA_EN_OVRD_VAL_R 12 12 RX_DATA_EN_OVRD_EN_R 13 13 RESERVED_15_14 14 15 ixDPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1 2 0x3206 12 0 4294967295 RESET_OVRD_VAL 0 0 RESET_OVRD_EN 1 1 REQ_OVRD_VAL 2 2 REQ_OVRD_EN 3 3 RX_LOS_THRSHLD_OVRD_VAL 4 6 RX_LOS_THRSHLD_OVRD_EN 7 7 ADAPT_REQ 8 8 ADAPT_REQ_OVRD_EN 9 9 ADAPT_CONT 10 10 OFFCAN_CONT 11 11 CONT_OVRD_EN 12 12 RESERVED_15_13 13 15 ixDPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_2 2 0x3207 4 0 4294967295 VCO_LD_VAL_OVRD 0 12 VCO_LD_VAL_OVRD_EN 13 13 VCO_LOWFREQ_VAL_OVRD 14 14 VCO_LOWFREQ_VAL_OVRD_EN 15 15 ixDPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_3 2 0x3208 3 0 4294967295 REF_LD_VAL_OVRD 0 6 REF_LD_VAL_OVRD_EN 7 7 RESERVED_15_8 8 15 ixDPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_PCS_IN 2 0x3209 13 0 4294967295 REQ 0 0 RATE 1 2 WIDTH 3 4 PSTATE 5 6 LPD 7 7 CDR_VCO_LOWFREQ 8 8 ADAPT_AFE_EN 9 9 ADAPT_DFE_EN 10 10 ADAPT_REQ 11 11 ADAPT_CONT 12 12 OFFCAN_CONT 13 13 RESET 14 14 RESERVED_15_15 15 15 ixDPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_1 2 0x320a 2 0 4294967295 REF_LD_VAL 0 6 RESERVED_15_7 7 15 ixDPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_2 2 0x320b 2 0 4294967295 VCO_LD_VAL 0 12 RESERVED_15_13 13 15 ixDPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_3 2 0x320c 4 0 4294967295 EQ_ATT_LVL 0 2 EQ_VGA1_GAIN 3 6 EQ_VGA2_GAIN 7 10 EQ_CTLE_BOOST 11 15 ixDPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_4 2 0x320d 3 0 4294967295 EQ_CTLE_POLE 0 2 EQ_DFE_TAP1 3 10 RESERVED_15_11 11 15 ixDPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT 2 0x320e 3 0 4294967295 ACK 0 0 EN_CTL 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_PCS_OUT 2 0x320f 2 0 4294967295 ACK 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_ADAPT_ACK 2 0x3210 2 0 4294967295 RX_ADAPT_ACK 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_ADAPT_FOM 2 0x3211 2 0 4294967295 RX_ADAPT_FOM 0 7 RESERVED_15_8 8 15 ixDPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_TXPRE_DIR 2 0x3212 2 0 4294967295 RX_TXPRE_DIR 0 1 RESERVED_15_2 2 15 ixDPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_TXMAIN_DIR 2 0x3213 2 0 4294967295 RX_TXMAIN_DIR 0 1 RESERVED_15_2 2 15 ixDPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_TXPOST_DIR 2 0x3214 2 0 4294967295 RX_TXPOST_DIR 0 1 RESERVED_15_2 2 15 ixDPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_LANE_NUMBER 2 0x3215 2 0 4294967295 LANE_NUMBER 0 3 RESERVED_15_4 4 15 ixDPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RESERVED_1 2 0x3216 1 0 4294967295 RESERVED_REG_1 0 15 ixDPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RESERVED_2 2 0x3217 1 0 4294967295 RESERVED_REG_2 0 15 ixDPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN 2 0x3218 16 0 4294967295 RX_RESET_ATE_OVRD_VAL 0 0 RX_RESET_ATE_OVRD_EN 1 1 TX_RESET_ATE_OVRD_VAL 2 2 TX_RESET_ATE_OVRD_EN 3 3 RX_REQ_ATE_OVRD_VAL 4 4 RX_REQ_ATE_OVRD_EN 5 5 TX_REQ_ATE_OVRD_VAL 6 6 TX_REQ_ATE_OVRD_EN 7 7 RX_ADAPT_AFE_EN_OVRD_VAL 8 8 RX_ADAPT_AFE_EN_OVRD_EN 9 9 RX_ADAPT_DFE_EN_OVRD_VAL 10 10 RX_ADAPT_DFE_EN_OVRD_EN 11 11 TX_DATA_EN_ATE_OVRD_VAL 12 12 TX_DATA_EN_ATE_OVRD_EN 13 13 RX_DATA_EN_ATE_OVRD_VAL 14 14 RX_DATA_EN_ATE_OVRD_EN 15 15 ixDPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN 2 0x3219 3 0 4294967295 RX_EQ_DELTA_IQ_OVRD_VAL 0 3 RX_EQ_DELTA_IQ_OVRD_EN 4 4 RESERVED_15_5 5 15 ixDPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN 2 0x321a 5 0 4294967295 RX_TERM_CTRL_OVRD_VAL 0 2 RX_TERM_CTRL_OVRD_EN 3 3 TX_TERM_CTRL_OVRD_VAL 4 6 TX_TERM_CTRL_OVRD_EN 7 7 RESERVED_15_8 8 15 ixDPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TXRX_TERM_CTRL_IN 2 0x321b 3 0 4294967295 RX_TERM_CTRL 0 2 TX_TERM_CTRL 3 5 RESERVED_15_6 6 15 ixDPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT_1 2 0x321c 2 0 4294967295 RX_CLK_EN 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_EQ_OVRD_IN_1 2 0x321d 4 0 4294967295 RX_EQ_AFE_GAIN_OVRD_VAL 0 3 RX_EQ_ATT_LVL_OVRD_VAL 4 6 RX_EQ_OVRD_EN 7 7 RESERVED_15_8 8 15 ixDPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_EQ_OVRD_IN_2 2 0x321e 3 0 4294967295 RX_EQ_DFE_TAP1_OVRD_VAL 0 7 RX_EQ_CTLE_BOOST_OVRD_VAL 8 12 RESERVED_15_13 13 15 ixDPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_PH2_CAL 2 0x321f 4 0 4294967295 PH2_CAL_ACK_VAL 0 0 PH2_CAL_REQ_VAL 1 1 PH2_CAL_REQ_OVRD_VAL 2 2 RESERVED_15_3 3 15 ixDPCSSYS_CR4_RAWLANE2_DIG_FSM_FSM_OVRD_CTL 2 0x3220 5 0 4294967295 FSM_JMP_ADDR 0 11 FSM_JMP_EN 12 12 FSM_CMD_START 13 13 FSM_OVRD_EN 14 14 FSM_BREAK 15 15 ixDPCSSYS_CR4_RAWLANE2_DIG_FSM_MEM_ADDR_MON 2 0x3221 1 0 4294967295 MEM_ADDR 0 15 ixDPCSSYS_CR4_RAWLANE2_DIG_FSM_STATUS_MON 2 0x3222 8 0 4294967295 STATE 0 4 CMD_RDY 5 5 ALU_OVFLW 6 6 ALU_RES_EQ0 7 7 WAIT_CNT_EQ0 8 8 WRMSK_DISABLED 9 9 RDMSK_DISABLED 10 10 RESERVED_15_11 11 15 ixDPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_RX_STARTUP_CAL 2 0x3223 2 0 4294967295 FAST_RX_STARTUP_CAL 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_RX_ADAPT 2 0x3224 2 0 4294967295 FAST_RX_ADAPT 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_RX_AFE_CAL 2 0x3225 2 0 4294967295 FAST_RX_AFE_CAL 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_RX_DFE_CAL 2 0x3226 2 0 4294967295 FAST_RX_DFE_CAL 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_RX_BYPASS_CAL 2 0x3227 2 0 4294967295 FAST_RX_BYPASS_CAL 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_RX_REFLVL_CAL 2 0x3228 2 0 4294967295 FAST_RX_REFLVL_CAL 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_RX_IQ_CAL 2 0x3229 2 0 4294967295 FAST_RX_IQ_CAL 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_RX_AFE_ADAPT 2 0x322a 2 0 4294967295 FAST_RX_AFE_ADAPT 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_RX_DFE_ADAPT 2 0x322b 2 0 4294967295 FAST_RX_DFE_ADAPT 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_SUP 2 0x322c 2 0 4294967295 FAST_SUP 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_TX_CMN_MODE 2 0x322d 2 0 4294967295 FAST_TX_CMN_MODE 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_TX_RXDET 2 0x322e 2 0 4294967295 FAST_TX_RXDET 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_RX_PWRUP 2 0x322f 2 0 4294967295 FAST_RX_PWRUP 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_RX_VCO_WAIT 2 0x3230 2 0 4294967295 FAST_RX_VCO_WAIT 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_RX_VCO_CAL 2 0x3231 2 0 4294967295 FAST_RX_VCO_CAL 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR4_RAWLANE2_DIG_FSM_CMNCAL_MPLL_STATUS 2 0x3232 3 0 4294967295 CMNCAL_MPLL_INIT 0 0 CMNCAL_MPLL_DONE 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_RX_CONT_CAL_ADAPT 2 0x3233 2 0 4294967295 FAST_RX_CONT_CAL_ADAPT 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_RX_CONT_ADAPT 2 0x3234 2 0 4294967295 FAST_RX_CONT_ADAPT 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_RX_CONT_DATA_CAL 2 0x3235 2 0 4294967295 FAST_RX_CONT_DATA_CAL 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_RX_CONT_PHASE_CAL 2 0x3236 2 0 4294967295 FAST_RX_CONT_PHASE_CAL 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_RX_CONT_AFE_CAL 2 0x3237 2 0 4294967295 FAST_RX_CONT_AFE_CAL 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_FLAGS 2 0x3238 12 0 4294967295 TX_FAST_DCC_CAL 0 0 RX_FAST_DCC_CAL 1 1 RX_FAST_VPHUD_CAL 2 2 RX_FAST_VREF_CAL 3 3 RX_FAST_SIGDET_CAL 4 4 RESERVED_2 5 7 TX_FAST_CONT_DCC_CAL 8 8 RX_FAST_CONT_DCC_CAL 9 9 RX_FAST_CONT_VPHUD_CAL 10 10 RX_FAST_CONT_VREF_CAL 11 11 RESERVED_1 12 14 TX_SKIP_SUP_CAL 15 15 ixDPCSSYS_CR4_RAWLANE2_DIG_FSM_CR_LOCK 2 0x3239 3 0 4294967295 CR_REG_LOCK 0 0 CR_MEM_LOCK 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR4_RAWLANE2_DIG_FSM_TX_DCC_FLAGS 2 0x323a 4 0 4294967295 RATE 0 0 DIV 1 1 MPLL 2 2 RESERVED_15_3 3 15 ixDPCSSYS_CR4_RAWLANE2_DIG_FSM_TX_DCC_STATUS 2 0x323b 2 0 4294967295 FLAG 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR4_RAWLANE2_DIG_FSM_OCLA 2 0x323c 4 0 4294967295 PC_EN 0 0 REG_BANK1_EN 1 1 REG_BANK2_EN 2 2 RESERVED_15_3 3 15 ixDPCSSYS_CR4_RAWLANE2_DIG_FSM_TX_EQ_UPDATE_FLAG 2 0x323d 2 0 4294967295 TX_EQ_UPDATE_FLAG 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR4_RAWLANE2_DIG_FSM_CMNCAL_RCAL_STATUS 2 0x323e 3 0 4294967295 CMNCAL_RCAL_INIT 0 0 CMNCAL_RCAL_DONE 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR4_RAWLANE2_DIG_FSM_RX_IQ_PHASE_OFFSET 2 0x323f 2 0 4294967295 RX_IQ_PHASE_OFFSET 0 3 RESERVED_15_4 4 15 ixDPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_RESET_RTN_REQ 2 0x3240 2 0 4294967295 RESET_RTN_REQ 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_RX_RESET_IRQ 2 0x3241 2 0 4294967295 RX_RESET 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_RX_REQ_IRQ 2 0x3242 2 0 4294967295 RX_REQ 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_RX_RATE_IRQ 2 0x3243 2 0 4294967295 RX_RATE_IRQ 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_RX_PSTATE_IRQ 2 0x3244 2 0 4294967295 RX_PSTATE_IRQ 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ 2 0x3245 2 0 4294967295 RX_ADAPT_REQ_IRQ 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ 2 0x3246 2 0 4294967295 RX_ADAPT_DIS_IRQ 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_RX_RESET_IRQ_CLR 2 0x3247 2 0 4294967295 RX_RESET_IRQ_CLR 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_RX_REQ_IRQ_CLR 2 0x3248 2 0 4294967295 RX_REQ_IRQ_CLR 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_RX_RATE_IRQ_CLR 2 0x3249 2 0 4294967295 RX_RATE_IRQ_CLR 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR 2 0x324a 2 0 4294967295 RX_PSTATE_IRQ_CLR 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR 2 0x324b 2 0 4294967295 RX_ADAPT_REQ_IRQ_CLR 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR 2 0x324c 2 0 4294967295 RX_ADAPT_DIS_IRQ_CLR 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK 2 0x324d 12 0 4294967295 RX_REQ_IRQ_MSK 0 0 RX_RATE_IRQ_MSK 1 1 RX_PSTATE_IRQ_MSK 2 2 RX_ADAPT_REQ_IRQ_MSK 3 3 RX_ADAPT_DIS_IRQ_MSK 4 4 RX_RESET_IRQ_MSK 5 5 LANE_XCVR_MODE_IRQ_MSK 6 6 RX_PH2_CAL_REQ_IRQ_MSK 7 7 RX_PH2_CAL_DIS_IRQ_MSK 8 8 LANE_RX2TX_SER_LB_EN_IRQ_MSK 9 9 DCC_ONDMD_IRQ_MSK 10 10 RESERVED_15_11 11 15 ixDPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK_2 2 0x324e 3 0 4294967295 TX_RESET_IRQ_MSK 0 0 TX_REQ_IRQ_MSK 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ 2 0x324f 2 0 4294967295 LANE_XCVR_MODE_IRQ 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR 2 0x3250 2 0 4294967295 LANE_XCVR_MODE_IRQ_CLR 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ 2 0x3251 2 0 4294967295 RX_PH2_CAL_REQ_IRQ 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ 2 0x3252 2 0 4294967295 RX_PH2_CAL_DIS_IRQ 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR 2 0x3253 2 0 4294967295 RX_PH2_CAL_REQ_IRQ_CLR 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR 2 0x3254 2 0 4294967295 RX_PH2_CAL_DIS_IRQ_CLR 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ 2 0x3255 2 0 4294967295 LANE_RX2TX_SER_LB_EN_IRQ 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR 2 0x3256 2 0 4294967295 LANE_RX2TX_SER_LB_EN_IRQ_CLR 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_DCC_ONDMD_IRQ 2 0x3257 2 0 4294967295 IRQ 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_TX_RESET_IRQ 2 0x3258 2 0 4294967295 TX_RESET 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_TX_REQ_IRQ 2 0x3259 2 0 4294967295 TX_REQ 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_TX_RESET_IRQ_CLR 2 0x325a 2 0 4294967295 TX_RESET_IRQ_CLR 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_TX_REQ_IRQ_CLR 2 0x325b 2 0 4294967295 TX_REQ_IRQ_CLR 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_LANE_OVRD_IN 2 0x3260 4 0 4294967295 LANE_MPLLA_EN_IN 0 0 LANE_MPLLB_EN_IN 1 1 LANE_OVRD_EN 2 2 RESERVED_15_3 3 15 ixDPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_LANE_OVRD_OUT 2 0x3261 4 0 4294967295 LANE_MPLLA_EN_OUT 0 0 LANE_MPLLB_EN_OUT 1 1 LANE_OVRD_EN 2 2 RESERVED_15_3 3 15 ixDPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_SUP_OVRD_IN 2 0x3262 4 0 4294967295 MPLLA_STATE 0 0 MPLLB_STATE 1 1 SUP_STATE_OVRD_EN 2 2 RESERVED_15_3 3 15 ixDPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_SUP_PMA_IN 2 0x3263 3 0 4294967295 MPLLA_STATE 0 0 MPLLB_STATE 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT 2 0x3264 16 0 4294967295 TX_REQ_OVRD_VAL 0 0 TX_REQ_OVRD_EN 1 1 TX_RESET_OVRD_VAL 2 2 TX_RESET_OVRD_EN 3 3 TX_BEACON_EN_OVRD_VAL 4 4 TX_BEACON_EN_OVRD_EN 5 5 TX_ASYNC_DRV_EN_OVRD_VAL 6 6 TX_ASYNC_DRV_EN_OVRD_EN 7 7 TX_ASYNC_EN_OVRD_VAL 8 8 TX_ASYNC_EN_OVRD_EN 9 9 TX_DWORD_CLK_SYNC_OVRD_VAL 10 10 TX_DWORD_CLK_SYNC_OVRD_EN 11 11 LANE_TX2RX_SER_LB_EN_OVRD_VAL 12 12 LANE_TX2RX_SER_LB_EN_OVRD_EN 13 13 TX_PMA_DATA_EN_OVRD_VAL_R 14 14 TX_PMA_DATA_EN_OVRD_EN_R 15 15 ixDPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_TX_PMA_IN 2 0x3265 2 0 4294967295 ACK 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT 2 0x3266 9 0 4294967295 RX_REQ_OVRD_VAL 0 0 RX_REQ_OVRD_EN 1 1 RX_RESET_OVRD_VAL 2 2 RX_RESET_OVRD_EN 3 3 LANE_RX2TX_PAR_LB_EN_OVRD_VAL 4 4 LANE_RX2TX_PAR_LB_EN_OVRD_EN 5 5 RX_PMA_DATA_EN_OVRD_VAL_R 6 6 RX_PMA_DATA_EN_OVRD_EN_R 7 7 RESERVED_15_8 8 15 ixDPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_RX_PMA_IN 2 0x3267 2 0 4294967295 ACK 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_LANE_RTUNE_CTL 2 0x3268 2 0 4294967295 LANE_RTUNE_REQ 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_SUP_PMA_IN_1 2 0x3269 2 0 4294967295 RTUNE_ACK 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_IN 2 0x326a 9 0 4294967295 RX_PMA_PWM_WORD_CLK_R 0 0 RX_PMA_PWM_WORD_CLK_OVRD_EN 1 1 RX_PMA_PWM_DATA_R 2 2 RX_PMA_PWM_DATA_OVRD_EN 3 3 RX_PMA_PWM_CLK_R 4 4 RX_PMA_PWM_CLK_OVRD_EN 5 5 RX_PMA_TERM_CTL_R 6 7 RX_PMA_TERM_CTL_OVRD_EN 8 8 RESERVED_15_9 9 15 ixDPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_OUT 2 0x326b 7 0 4294967295 RX_PMA_PWM_EN 0 0 RX_PMA_PWM_EN_OVRD_EN 1 1 RX_PMA_PWM_CLK_SEL 2 3 RX_PMA_PWM_CLK_SEL_OVRD_EN 4 4 RX_PMA_ASYNC_EN 5 5 RX_PMA_ASYNC_EN_OVRD_EN 6 6 RESERVED_15_7 7 15 ixDPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_RX_ADAPT_OVRD_OUT 2 0x326c 3 0 4294967295 RX_PMA_IQ_PHASE_ADJUST_MAP_OVRD_VAL 0 6 RX_PMA_IQ_PHASE_ADJUST_MAP_OVRD_EN 7 7 RESERVED_15_8 8 15 ixDPCSSYS_CR4_RAWLANE2_DIG_TX_CTL_TX_FSM_CTL 2 0x3280 6 0 4294967295 TX_WAIT_MPLL_OFF_TIME 0 6 TX_P2_ALLOW_RXDET 7 7 TX_P1_ALLOW_RXDET 8 8 TX_P0S_ALLOW_RXDET 9 9 TX_P0_ALLOW_RXDET 10 10 RESERVED_15_11 11 15 ixDPCSSYS_CR4_RAWLANE2_DIG_TX_CTL_TX_CLK_CTL 2 0x3281 4 0 4294967295 TX_CLK_EN 0 0 TX_CLK_SEL 1 4 ASYNC_BEACON_WAIT_TIME 5 10 RESERVED_15_11 11 15 ixDPCSSYS_CR4_RAWLANE2_DIG_TX_CTL_TX_DCC_CONT_STATUS 2 0x3282 2 0 4294967295 ENABLE 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR4_RAWLANE2_DIG_TX_CTL_OCLA 2 0x3283 2 0 4294967295 FSM_EN 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR4_RAWLANE2_DIG_TX_CTL_UPCS_OCLA 2 0x3284 3 0 4294967295 DATA_EN 0 1 CLK_EN 2 2 RESERVED_15_3 3 15 ixDPCSSYS_CR4_RAWLANE2_DIG_RX_CTL_RX_FSM_CTL 2 0x32a0 3 0 4294967295 EN_RX_CTL_FSM 0 0 RATE_CHG_IN_P1 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR4_RAWLANE2_DIG_RX_CTL_RX_LOS_MASK_CTL 2 0x32a1 2 0 4294967295 RX_LOS_MASK_CNT 0 8 RESERVED_15_9 9 15 ixDPCSSYS_CR4_RAWLANE2_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL 2 0x32a2 2 0 4294967295 RX_DATA_EN_OVRD_CNT 0 4 INT_REF_TRCK_CNT 5 15 ixDPCSSYS_CR4_RAWLANE2_DIG_RX_CTL_OFFCAN_CONT_STATUS 2 0x32a3 2 0 4294967295 ENABLE 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR4_RAWLANE2_DIG_RX_CTL_ADAPT_CONT_STATUS 2 0x32a4 2 0 4294967295 ENABLE 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR4_RAWLANE2_DIG_RX_CTL_UPCS_OCLA 2 0x32a5 3 0 4294967295 DATA_EN 0 2 CLK_EN 3 3 RESERVED_15_4 4 15 ixDPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN 2 0x32c0 11 0 4294967295 RATE_OVRD_VAL 0 1 RATE_OVRD_EN 2 2 WIDTH_OVRD_VAL 3 4 WIDTH_OVRD_EN 5 5 PSTATE_OVRD_VAL 6 7 PSTATE_OVRD_EN 8 8 LPD_OVRD_VAL 9 9 LPD_OVRD_EN 10 10 LANE_RX2TX_PAR_LB_EN_OVRD_VAL 11 11 LANE_RX2TX_PAR_LB_EN_OVRD_EN 12 12 RESERVED_15_13 13 15 ixDPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN 2 0x32c1 12 0 4294967295 PSTATE 0 1 LPD 2 2 WIDTH 3 4 RATE 5 7 MPLLB_SEL 8 8 MPLL_EN 9 9 OVRD_EN 10 10 MSTR_MPLLA_STATE 11 11 MSTR_MPLLB_STATE 12 12 MSTR_MPLL_OVRD_EN 13 13 TX_ASYNC_EN_OVR_VAL 14 14 TX_ASYNC_EN_OVR_EN 15 15 ixDPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1 2 0x32c2 13 0 4294967295 DETRX_REQ_OVRD_VAL 0 0 DETRX_REQ_OVRD_EN 1 1 VBOOST_EN_OVRD_VAL 2 2 VBOOST_EN_OVRD_EN 3 3 IBOOST_LVL_OVRD_VAL 4 7 IBOOST_LVL_OVRD_EN 8 8 TX_BEACON_EN_OVR_VAL 9 9 TX_BEACON_EN_OVR_EN 10 10 LANE_TX2RX_SER_LB_EN_OVRD_VAL 11 11 LANE_TX2RX_SER_LB_EN_OVRD_EN 12 12 TX_ASYNC_DATA_OVRD_VAL 13 13 TX_ASYNC_DATA_OVRD_EN 14 14 RESERVED_15_15 15 15 ixDPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_MASTER_MPLL_LOOP 2 0x32c3 3 0 4294967295 MPLLB_LOOP_EN 0 0 MPLLA_LOOP_EN 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1 2 0x32c4 11 0 4294967295 RESERVED 0 1 RX_LOS_LFPS_EN_OVRD_VAL 2 2 RX_LOS_LFPS_EN_OVRD_EN 3 3 RX_LOS_THRSHLD_OVRD_VAL 4 6 RX_LOS_THRSHLD_OVRD_EN 7 7 ADAPT_REQ 8 8 ADAPT_REQ_OVRD_EN 9 9 ADAPT_CONT 10 10 OFFCAN_CONT 11 11 CONT_OVRD_EN 12 12 RESERVED_15_13 13 15 ixDPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_2 2 0x32c5 4 0 4294967295 VCO_LD_VAL_OVRD 0 12 VCO_LD_VAL_OVRD_EN 13 13 VCO_LOWFREQ_VAL_OVRD 14 14 VCO_LOWFREQ_VAL_OVRD_EN 15 15 ixDPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_3 2 0x32c6 3 0 4294967295 REF_LD_VAL_OVRD 0 6 REF_LD_VAL_OVRD_EN 7 7 RESERVED_15_8 8 15 ixDPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT_2 2 0x32c7 3 0 4294967295 RX_VALID 0 0 RX_VALID_OVRD_EN 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_2 2 0x32c8 7 0 4294967295 LANE_TX2RX_SER_LB_EN_OVRD_VAL 0 0 LANE_TX2RX_SER_LB_EN_OVRD_EN 1 1 TX_DATA_EN_OVRD_VAL_R 2 2 TX_DATA_EN_OVRD_EN_R 3 3 TX_ASYNC_DATA_OVRD_VAL_R 4 4 TX_ASYNC_DATA_OVRD_EN_R 5 5 RESERVED_15_6 6 15 ixDPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN 2 0x3300 12 0 4294967295 PSTATE 0 1 LPD 2 2 WIDTH 3 4 RATE 5 7 MPLLB_SEL 8 8 MPLL_EN 9 9 OVRD_EN 10 10 MSTR_MPLLA_STATE 11 11 MSTR_MPLLB_STATE 12 12 MSTR_MPLL_OVRD_EN 13 13 TX_ASYNC_EN_OVR_VAL 14 14 TX_ASYNC_EN_OVR_EN 15 15 ixDPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1 2 0x3301 13 0 4294967295 RESET_OVRD_VAL 0 0 RESET_OVRD_EN 1 1 REQ_OVRD_VAL 2 2 REQ_OVRD_EN 3 3 DETRX_REQ_OVRD_VAL 4 4 DETRX_REQ_OVRD_EN 5 5 VBOOST_EN_OVRD_VAL 6 6 VBOOST_EN_OVRD_EN 7 7 IBOOST_LVL_OVRD_VAL 8 11 IBOOST_LVL_OVRD_EN 12 12 TX_BEACON_EN_OVR_VAL 13 13 TX_BEACON_EN_OVR_EN 14 14 RESERVED_15_15 15 15 ixDPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_PCS_IN 2 0x3302 12 0 4294967295 RESET 0 0 REQ 1 1 PSTATE 2 3 LPD 4 4 WIDTH 5 6 RATE 7 9 MPLLB_SEL 10 10 MPLL_EN 11 11 MSTR_MPLLA_STATE 12 12 MSTR_MPLLB_STATE 13 13 DETRX_REQ 14 14 RESERVED_15_15 15 15 ixDPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_OVRD_OUT 2 0x3303 6 0 4294967295 ACK 0 0 DETRX_RESULT 1 1 EN_CTL 2 2 TX_DWORD_CLK_SYNC_OVRD_VAL 3 3 TX_DWORD_CLK_SYNC_OVRD_EN 4 4 RESERVED_15_5 5 15 ixDPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_PCS_OUT 2 0x3304 2 0 4294967295 ACK 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN 2 0x3305 12 0 4294967295 RATE 0 1 WIDTH 2 3 PSTATE 4 5 LPD 6 6 OVRD_EN 7 7 ADAPT_AFE_EN 8 8 ADAPT_DFE_EN 9 9 LANE_RX2TX_PAR_LB_EN_OVRD_VAL 10 10 LANE_RX2TX_PAR_LB_EN_OVRD_EN 11 11 RX_DATA_EN_OVRD_VAL_R 12 12 RX_DATA_EN_OVRD_EN_R 13 13 RESERVED_15_14 14 15 ixDPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1 2 0x3306 12 0 4294967295 RESET_OVRD_VAL 0 0 RESET_OVRD_EN 1 1 REQ_OVRD_VAL 2 2 REQ_OVRD_EN 3 3 RX_LOS_THRSHLD_OVRD_VAL 4 6 RX_LOS_THRSHLD_OVRD_EN 7 7 ADAPT_REQ 8 8 ADAPT_REQ_OVRD_EN 9 9 ADAPT_CONT 10 10 OFFCAN_CONT 11 11 CONT_OVRD_EN 12 12 RESERVED_15_13 13 15 ixDPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_2 2 0x3307 4 0 4294967295 VCO_LD_VAL_OVRD 0 12 VCO_LD_VAL_OVRD_EN 13 13 VCO_LOWFREQ_VAL_OVRD 14 14 VCO_LOWFREQ_VAL_OVRD_EN 15 15 ixDPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_3 2 0x3308 3 0 4294967295 REF_LD_VAL_OVRD 0 6 REF_LD_VAL_OVRD_EN 7 7 RESERVED_15_8 8 15 ixDPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_PCS_IN 2 0x3309 13 0 4294967295 REQ 0 0 RATE 1 2 WIDTH 3 4 PSTATE 5 6 LPD 7 7 CDR_VCO_LOWFREQ 8 8 ADAPT_AFE_EN 9 9 ADAPT_DFE_EN 10 10 ADAPT_REQ 11 11 ADAPT_CONT 12 12 OFFCAN_CONT 13 13 RESET 14 14 RESERVED_15_15 15 15 ixDPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_1 2 0x330a 2 0 4294967295 REF_LD_VAL 0 6 RESERVED_15_7 7 15 ixDPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_2 2 0x330b 2 0 4294967295 VCO_LD_VAL 0 12 RESERVED_15_13 13 15 ixDPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_3 2 0x330c 4 0 4294967295 EQ_ATT_LVL 0 2 EQ_VGA1_GAIN 3 6 EQ_VGA2_GAIN 7 10 EQ_CTLE_BOOST 11 15 ixDPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_4 2 0x330d 3 0 4294967295 EQ_CTLE_POLE 0 2 EQ_DFE_TAP1 3 10 RESERVED_15_11 11 15 ixDPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT 2 0x330e 3 0 4294967295 ACK 0 0 EN_CTL 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_PCS_OUT 2 0x330f 2 0 4294967295 ACK 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_ADAPT_ACK 2 0x3310 2 0 4294967295 RX_ADAPT_ACK 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_ADAPT_FOM 2 0x3311 2 0 4294967295 RX_ADAPT_FOM 0 7 RESERVED_15_8 8 15 ixDPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_TXPRE_DIR 2 0x3312 2 0 4294967295 RX_TXPRE_DIR 0 1 RESERVED_15_2 2 15 ixDPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_TXMAIN_DIR 2 0x3313 2 0 4294967295 RX_TXMAIN_DIR 0 1 RESERVED_15_2 2 15 ixDPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_TXPOST_DIR 2 0x3314 2 0 4294967295 RX_TXPOST_DIR 0 1 RESERVED_15_2 2 15 ixDPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_LANE_NUMBER 2 0x3315 2 0 4294967295 LANE_NUMBER 0 3 RESERVED_15_4 4 15 ixDPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RESERVED_1 2 0x3316 1 0 4294967295 RESERVED_REG_1 0 15 ixDPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RESERVED_2 2 0x3317 1 0 4294967295 RESERVED_REG_2 0 15 ixDPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN 2 0x3318 16 0 4294967295 RX_RESET_ATE_OVRD_VAL 0 0 RX_RESET_ATE_OVRD_EN 1 1 TX_RESET_ATE_OVRD_VAL 2 2 TX_RESET_ATE_OVRD_EN 3 3 RX_REQ_ATE_OVRD_VAL 4 4 RX_REQ_ATE_OVRD_EN 5 5 TX_REQ_ATE_OVRD_VAL 6 6 TX_REQ_ATE_OVRD_EN 7 7 RX_ADAPT_AFE_EN_OVRD_VAL 8 8 RX_ADAPT_AFE_EN_OVRD_EN 9 9 RX_ADAPT_DFE_EN_OVRD_VAL 10 10 RX_ADAPT_DFE_EN_OVRD_EN 11 11 TX_DATA_EN_ATE_OVRD_VAL 12 12 TX_DATA_EN_ATE_OVRD_EN 13 13 RX_DATA_EN_ATE_OVRD_VAL 14 14 RX_DATA_EN_ATE_OVRD_EN 15 15 ixDPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN 2 0x3319 3 0 4294967295 RX_EQ_DELTA_IQ_OVRD_VAL 0 3 RX_EQ_DELTA_IQ_OVRD_EN 4 4 RESERVED_15_5 5 15 ixDPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN 2 0x331a 5 0 4294967295 RX_TERM_CTRL_OVRD_VAL 0 2 RX_TERM_CTRL_OVRD_EN 3 3 TX_TERM_CTRL_OVRD_VAL 4 6 TX_TERM_CTRL_OVRD_EN 7 7 RESERVED_15_8 8 15 ixDPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TXRX_TERM_CTRL_IN 2 0x331b 3 0 4294967295 RX_TERM_CTRL 0 2 TX_TERM_CTRL 3 5 RESERVED_15_6 6 15 ixDPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT_1 2 0x331c 2 0 4294967295 RX_CLK_EN 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_EQ_OVRD_IN_1 2 0x331d 4 0 4294967295 RX_EQ_AFE_GAIN_OVRD_VAL 0 3 RX_EQ_ATT_LVL_OVRD_VAL 4 6 RX_EQ_OVRD_EN 7 7 RESERVED_15_8 8 15 ixDPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_EQ_OVRD_IN_2 2 0x331e 3 0 4294967295 RX_EQ_DFE_TAP1_OVRD_VAL 0 7 RX_EQ_CTLE_BOOST_OVRD_VAL 8 12 RESERVED_15_13 13 15 ixDPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_PH2_CAL 2 0x331f 4 0 4294967295 PH2_CAL_ACK_VAL 0 0 PH2_CAL_REQ_VAL 1 1 PH2_CAL_REQ_OVRD_VAL 2 2 RESERVED_15_3 3 15 ixDPCSSYS_CR4_RAWLANE3_DIG_FSM_FSM_OVRD_CTL 2 0x3320 5 0 4294967295 FSM_JMP_ADDR 0 11 FSM_JMP_EN 12 12 FSM_CMD_START 13 13 FSM_OVRD_EN 14 14 FSM_BREAK 15 15 ixDPCSSYS_CR4_RAWLANE3_DIG_FSM_MEM_ADDR_MON 2 0x3321 1 0 4294967295 MEM_ADDR 0 15 ixDPCSSYS_CR4_RAWLANE3_DIG_FSM_STATUS_MON 2 0x3322 8 0 4294967295 STATE 0 4 CMD_RDY 5 5 ALU_OVFLW 6 6 ALU_RES_EQ0 7 7 WAIT_CNT_EQ0 8 8 WRMSK_DISABLED 9 9 RDMSK_DISABLED 10 10 RESERVED_15_11 11 15 ixDPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_RX_STARTUP_CAL 2 0x3323 2 0 4294967295 FAST_RX_STARTUP_CAL 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_RX_ADAPT 2 0x3324 2 0 4294967295 FAST_RX_ADAPT 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_RX_AFE_CAL 2 0x3325 2 0 4294967295 FAST_RX_AFE_CAL 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_RX_DFE_CAL 2 0x3326 2 0 4294967295 FAST_RX_DFE_CAL 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_RX_BYPASS_CAL 2 0x3327 2 0 4294967295 FAST_RX_BYPASS_CAL 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_RX_REFLVL_CAL 2 0x3328 2 0 4294967295 FAST_RX_REFLVL_CAL 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_RX_IQ_CAL 2 0x3329 2 0 4294967295 FAST_RX_IQ_CAL 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_RX_AFE_ADAPT 2 0x332a 2 0 4294967295 FAST_RX_AFE_ADAPT 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_RX_DFE_ADAPT 2 0x332b 2 0 4294967295 FAST_RX_DFE_ADAPT 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_SUP 2 0x332c 2 0 4294967295 FAST_SUP 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_TX_CMN_MODE 2 0x332d 2 0 4294967295 FAST_TX_CMN_MODE 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_TX_RXDET 2 0x332e 2 0 4294967295 FAST_TX_RXDET 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_RX_PWRUP 2 0x332f 2 0 4294967295 FAST_RX_PWRUP 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_RX_VCO_WAIT 2 0x3330 2 0 4294967295 FAST_RX_VCO_WAIT 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_RX_VCO_CAL 2 0x3331 2 0 4294967295 FAST_RX_VCO_CAL 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR4_RAWLANE3_DIG_FSM_CMNCAL_MPLL_STATUS 2 0x3332 3 0 4294967295 CMNCAL_MPLL_INIT 0 0 CMNCAL_MPLL_DONE 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_RX_CONT_CAL_ADAPT 2 0x3333 2 0 4294967295 FAST_RX_CONT_CAL_ADAPT 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_RX_CONT_ADAPT 2 0x3334 2 0 4294967295 FAST_RX_CONT_ADAPT 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_RX_CONT_DATA_CAL 2 0x3335 2 0 4294967295 FAST_RX_CONT_DATA_CAL 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_RX_CONT_PHASE_CAL 2 0x3336 2 0 4294967295 FAST_RX_CONT_PHASE_CAL 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_RX_CONT_AFE_CAL 2 0x3337 2 0 4294967295 FAST_RX_CONT_AFE_CAL 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_FLAGS 2 0x3338 12 0 4294967295 TX_FAST_DCC_CAL 0 0 RX_FAST_DCC_CAL 1 1 RX_FAST_VPHUD_CAL 2 2 RX_FAST_VREF_CAL 3 3 RX_FAST_SIGDET_CAL 4 4 RESERVED_2 5 7 TX_FAST_CONT_DCC_CAL 8 8 RX_FAST_CONT_DCC_CAL 9 9 RX_FAST_CONT_VPHUD_CAL 10 10 RX_FAST_CONT_VREF_CAL 11 11 RESERVED_1 12 14 TX_SKIP_SUP_CAL 15 15 ixDPCSSYS_CR4_RAWLANE3_DIG_FSM_CR_LOCK 2 0x3339 3 0 4294967295 CR_REG_LOCK 0 0 CR_MEM_LOCK 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR4_RAWLANE3_DIG_FSM_TX_DCC_FLAGS 2 0x333a 4 0 4294967295 RATE 0 0 DIV 1 1 MPLL 2 2 RESERVED_15_3 3 15 ixDPCSSYS_CR4_RAWLANE3_DIG_FSM_TX_DCC_STATUS 2 0x333b 2 0 4294967295 FLAG 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR4_RAWLANE3_DIG_FSM_OCLA 2 0x333c 4 0 4294967295 PC_EN 0 0 REG_BANK1_EN 1 1 REG_BANK2_EN 2 2 RESERVED_15_3 3 15 ixDPCSSYS_CR4_RAWLANE3_DIG_FSM_TX_EQ_UPDATE_FLAG 2 0x333d 2 0 4294967295 TX_EQ_UPDATE_FLAG 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR4_RAWLANE3_DIG_FSM_CMNCAL_RCAL_STATUS 2 0x333e 3 0 4294967295 CMNCAL_RCAL_INIT 0 0 CMNCAL_RCAL_DONE 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR4_RAWLANE3_DIG_FSM_RX_IQ_PHASE_OFFSET 2 0x333f 2 0 4294967295 RX_IQ_PHASE_OFFSET 0 3 RESERVED_15_4 4 15 ixDPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_RESET_RTN_REQ 2 0x3340 2 0 4294967295 RESET_RTN_REQ 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_RX_RESET_IRQ 2 0x3341 2 0 4294967295 RX_RESET 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_RX_REQ_IRQ 2 0x3342 2 0 4294967295 RX_REQ 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_RX_RATE_IRQ 2 0x3343 2 0 4294967295 RX_RATE_IRQ 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_RX_PSTATE_IRQ 2 0x3344 2 0 4294967295 RX_PSTATE_IRQ 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ 2 0x3345 2 0 4294967295 RX_ADAPT_REQ_IRQ 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ 2 0x3346 2 0 4294967295 RX_ADAPT_DIS_IRQ 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_RX_RESET_IRQ_CLR 2 0x3347 2 0 4294967295 RX_RESET_IRQ_CLR 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_RX_REQ_IRQ_CLR 2 0x3348 2 0 4294967295 RX_REQ_IRQ_CLR 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_RX_RATE_IRQ_CLR 2 0x3349 2 0 4294967295 RX_RATE_IRQ_CLR 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR 2 0x334a 2 0 4294967295 RX_PSTATE_IRQ_CLR 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR 2 0x334b 2 0 4294967295 RX_ADAPT_REQ_IRQ_CLR 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR 2 0x334c 2 0 4294967295 RX_ADAPT_DIS_IRQ_CLR 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK 2 0x334d 12 0 4294967295 RX_REQ_IRQ_MSK 0 0 RX_RATE_IRQ_MSK 1 1 RX_PSTATE_IRQ_MSK 2 2 RX_ADAPT_REQ_IRQ_MSK 3 3 RX_ADAPT_DIS_IRQ_MSK 4 4 RX_RESET_IRQ_MSK 5 5 LANE_XCVR_MODE_IRQ_MSK 6 6 RX_PH2_CAL_REQ_IRQ_MSK 7 7 RX_PH2_CAL_DIS_IRQ_MSK 8 8 LANE_RX2TX_SER_LB_EN_IRQ_MSK 9 9 DCC_ONDMD_IRQ_MSK 10 10 RESERVED_15_11 11 15 ixDPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK_2 2 0x334e 3 0 4294967295 TX_RESET_IRQ_MSK 0 0 TX_REQ_IRQ_MSK 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ 2 0x334f 2 0 4294967295 LANE_XCVR_MODE_IRQ 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR 2 0x3350 2 0 4294967295 LANE_XCVR_MODE_IRQ_CLR 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ 2 0x3351 2 0 4294967295 RX_PH2_CAL_REQ_IRQ 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ 2 0x3352 2 0 4294967295 RX_PH2_CAL_DIS_IRQ 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR 2 0x3353 2 0 4294967295 RX_PH2_CAL_REQ_IRQ_CLR 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR 2 0x3354 2 0 4294967295 RX_PH2_CAL_DIS_IRQ_CLR 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ 2 0x3355 2 0 4294967295 LANE_RX2TX_SER_LB_EN_IRQ 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR 2 0x3356 2 0 4294967295 LANE_RX2TX_SER_LB_EN_IRQ_CLR 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_DCC_ONDMD_IRQ 2 0x3357 2 0 4294967295 IRQ 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_TX_RESET_IRQ 2 0x3358 2 0 4294967295 TX_RESET 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_TX_REQ_IRQ 2 0x3359 2 0 4294967295 TX_REQ 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_TX_RESET_IRQ_CLR 2 0x335a 2 0 4294967295 TX_RESET_IRQ_CLR 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_TX_REQ_IRQ_CLR 2 0x335b 2 0 4294967295 TX_REQ_IRQ_CLR 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_LANE_OVRD_IN 2 0x3360 4 0 4294967295 LANE_MPLLA_EN_IN 0 0 LANE_MPLLB_EN_IN 1 1 LANE_OVRD_EN 2 2 RESERVED_15_3 3 15 ixDPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_LANE_OVRD_OUT 2 0x3361 4 0 4294967295 LANE_MPLLA_EN_OUT 0 0 LANE_MPLLB_EN_OUT 1 1 LANE_OVRD_EN 2 2 RESERVED_15_3 3 15 ixDPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_SUP_OVRD_IN 2 0x3362 4 0 4294967295 MPLLA_STATE 0 0 MPLLB_STATE 1 1 SUP_STATE_OVRD_EN 2 2 RESERVED_15_3 3 15 ixDPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_SUP_PMA_IN 2 0x3363 3 0 4294967295 MPLLA_STATE 0 0 MPLLB_STATE 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT 2 0x3364 16 0 4294967295 TX_REQ_OVRD_VAL 0 0 TX_REQ_OVRD_EN 1 1 TX_RESET_OVRD_VAL 2 2 TX_RESET_OVRD_EN 3 3 TX_BEACON_EN_OVRD_VAL 4 4 TX_BEACON_EN_OVRD_EN 5 5 TX_ASYNC_DRV_EN_OVRD_VAL 6 6 TX_ASYNC_DRV_EN_OVRD_EN 7 7 TX_ASYNC_EN_OVRD_VAL 8 8 TX_ASYNC_EN_OVRD_EN 9 9 TX_DWORD_CLK_SYNC_OVRD_VAL 10 10 TX_DWORD_CLK_SYNC_OVRD_EN 11 11 LANE_TX2RX_SER_LB_EN_OVRD_VAL 12 12 LANE_TX2RX_SER_LB_EN_OVRD_EN 13 13 TX_PMA_DATA_EN_OVRD_VAL_R 14 14 TX_PMA_DATA_EN_OVRD_EN_R 15 15 ixDPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_TX_PMA_IN 2 0x3365 2 0 4294967295 ACK 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT 2 0x3366 9 0 4294967295 RX_REQ_OVRD_VAL 0 0 RX_REQ_OVRD_EN 1 1 RX_RESET_OVRD_VAL 2 2 RX_RESET_OVRD_EN 3 3 LANE_RX2TX_PAR_LB_EN_OVRD_VAL 4 4 LANE_RX2TX_PAR_LB_EN_OVRD_EN 5 5 RX_PMA_DATA_EN_OVRD_VAL_R 6 6 RX_PMA_DATA_EN_OVRD_EN_R 7 7 RESERVED_15_8 8 15 ixDPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_RX_PMA_IN 2 0x3367 2 0 4294967295 ACK 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_LANE_RTUNE_CTL 2 0x3368 2 0 4294967295 LANE_RTUNE_REQ 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_SUP_PMA_IN_1 2 0x3369 2 0 4294967295 RTUNE_ACK 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_IN 2 0x336a 9 0 4294967295 RX_PMA_PWM_WORD_CLK_R 0 0 RX_PMA_PWM_WORD_CLK_OVRD_EN 1 1 RX_PMA_PWM_DATA_R 2 2 RX_PMA_PWM_DATA_OVRD_EN 3 3 RX_PMA_PWM_CLK_R 4 4 RX_PMA_PWM_CLK_OVRD_EN 5 5 RX_PMA_TERM_CTL_R 6 7 RX_PMA_TERM_CTL_OVRD_EN 8 8 RESERVED_15_9 9 15 ixDPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_OUT 2 0x336b 7 0 4294967295 RX_PMA_PWM_EN 0 0 RX_PMA_PWM_EN_OVRD_EN 1 1 RX_PMA_PWM_CLK_SEL 2 3 RX_PMA_PWM_CLK_SEL_OVRD_EN 4 4 RX_PMA_ASYNC_EN 5 5 RX_PMA_ASYNC_EN_OVRD_EN 6 6 RESERVED_15_7 7 15 ixDPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_RX_ADAPT_OVRD_OUT 2 0x336c 3 0 4294967295 RX_PMA_IQ_PHASE_ADJUST_MAP_OVRD_VAL 0 6 RX_PMA_IQ_PHASE_ADJUST_MAP_OVRD_EN 7 7 RESERVED_15_8 8 15 ixDPCSSYS_CR4_RAWLANE3_DIG_TX_CTL_TX_FSM_CTL 2 0x3380 6 0 4294967295 TX_WAIT_MPLL_OFF_TIME 0 6 TX_P2_ALLOW_RXDET 7 7 TX_P1_ALLOW_RXDET 8 8 TX_P0S_ALLOW_RXDET 9 9 TX_P0_ALLOW_RXDET 10 10 RESERVED_15_11 11 15 ixDPCSSYS_CR4_RAWLANE3_DIG_TX_CTL_TX_CLK_CTL 2 0x3381 4 0 4294967295 TX_CLK_EN 0 0 TX_CLK_SEL 1 4 ASYNC_BEACON_WAIT_TIME 5 10 RESERVED_15_11 11 15 ixDPCSSYS_CR4_RAWLANE3_DIG_TX_CTL_TX_DCC_CONT_STATUS 2 0x3382 2 0 4294967295 ENABLE 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR4_RAWLANE3_DIG_TX_CTL_OCLA 2 0x3383 2 0 4294967295 FSM_EN 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR4_RAWLANE3_DIG_TX_CTL_UPCS_OCLA 2 0x3384 3 0 4294967295 DATA_EN 0 1 CLK_EN 2 2 RESERVED_15_3 3 15 ixDPCSSYS_CR4_RAWLANE3_DIG_RX_CTL_RX_FSM_CTL 2 0x33a0 3 0 4294967295 EN_RX_CTL_FSM 0 0 RATE_CHG_IN_P1 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR4_RAWLANE3_DIG_RX_CTL_RX_LOS_MASK_CTL 2 0x33a1 2 0 4294967295 RX_LOS_MASK_CNT 0 8 RESERVED_15_9 9 15 ixDPCSSYS_CR4_RAWLANE3_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL 2 0x33a2 2 0 4294967295 RX_DATA_EN_OVRD_CNT 0 4 INT_REF_TRCK_CNT 5 15 ixDPCSSYS_CR4_RAWLANE3_DIG_RX_CTL_OFFCAN_CONT_STATUS 2 0x33a3 2 0 4294967295 ENABLE 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR4_RAWLANE3_DIG_RX_CTL_ADAPT_CONT_STATUS 2 0x33a4 2 0 4294967295 ENABLE 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR4_RAWLANE3_DIG_RX_CTL_UPCS_OCLA 2 0x33a5 3 0 4294967295 DATA_EN 0 2 CLK_EN 3 3 RESERVED_15_4 4 15 ixDPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN 2 0x33c0 11 0 4294967295 RATE_OVRD_VAL 0 1 RATE_OVRD_EN 2 2 WIDTH_OVRD_VAL 3 4 WIDTH_OVRD_EN 5 5 PSTATE_OVRD_VAL 6 7 PSTATE_OVRD_EN 8 8 LPD_OVRD_VAL 9 9 LPD_OVRD_EN 10 10 LANE_RX2TX_PAR_LB_EN_OVRD_VAL 11 11 LANE_RX2TX_PAR_LB_EN_OVRD_EN 12 12 RESERVED_15_13 13 15 ixDPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN 2 0x33c1 12 0 4294967295 PSTATE 0 1 LPD 2 2 WIDTH 3 4 RATE 5 7 MPLLB_SEL 8 8 MPLL_EN 9 9 OVRD_EN 10 10 MSTR_MPLLA_STATE 11 11 MSTR_MPLLB_STATE 12 12 MSTR_MPLL_OVRD_EN 13 13 TX_ASYNC_EN_OVR_VAL 14 14 TX_ASYNC_EN_OVR_EN 15 15 ixDPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1 2 0x33c2 13 0 4294967295 DETRX_REQ_OVRD_VAL 0 0 DETRX_REQ_OVRD_EN 1 1 VBOOST_EN_OVRD_VAL 2 2 VBOOST_EN_OVRD_EN 3 3 IBOOST_LVL_OVRD_VAL 4 7 IBOOST_LVL_OVRD_EN 8 8 TX_BEACON_EN_OVR_VAL 9 9 TX_BEACON_EN_OVR_EN 10 10 LANE_TX2RX_SER_LB_EN_OVRD_VAL 11 11 LANE_TX2RX_SER_LB_EN_OVRD_EN 12 12 TX_ASYNC_DATA_OVRD_VAL 13 13 TX_ASYNC_DATA_OVRD_EN 14 14 RESERVED_15_15 15 15 ixDPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_MASTER_MPLL_LOOP 2 0x33c3 3 0 4294967295 MPLLB_LOOP_EN 0 0 MPLLA_LOOP_EN 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1 2 0x33c4 11 0 4294967295 RESERVED 0 1 RX_LOS_LFPS_EN_OVRD_VAL 2 2 RX_LOS_LFPS_EN_OVRD_EN 3 3 RX_LOS_THRSHLD_OVRD_VAL 4 6 RX_LOS_THRSHLD_OVRD_EN 7 7 ADAPT_REQ 8 8 ADAPT_REQ_OVRD_EN 9 9 ADAPT_CONT 10 10 OFFCAN_CONT 11 11 CONT_OVRD_EN 12 12 RESERVED_15_13 13 15 ixDPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_2 2 0x33c5 4 0 4294967295 VCO_LD_VAL_OVRD 0 12 VCO_LD_VAL_OVRD_EN 13 13 VCO_LOWFREQ_VAL_OVRD 14 14 VCO_LOWFREQ_VAL_OVRD_EN 15 15 ixDPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_3 2 0x33c6 3 0 4294967295 REF_LD_VAL_OVRD 0 6 REF_LD_VAL_OVRD_EN 7 7 RESERVED_15_8 8 15 ixDPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT_2 2 0x33c7 3 0 4294967295 RX_VALID 0 0 RX_VALID_OVRD_EN 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_2 2 0x33c8 7 0 4294967295 LANE_TX2RX_SER_LB_EN_OVRD_VAL 0 0 LANE_TX2RX_SER_LB_EN_OVRD_EN 1 1 TX_DATA_EN_OVRD_VAL_R 2 2 TX_DATA_EN_OVRD_EN_R 3 3 TX_ASYNC_DATA_OVRD_VAL_R 4 4 TX_ASYNC_DATA_OVRD_EN_R 5 5 RESERVED_15_6 6 15 ixDPCSSYS_CR4_RAWAONLANE0_DIG_AFE_ATT_IDAC_OFST 2 0x4000 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR4_RAWAONLANE0_DIG_AFE_CTLE_IDAC_OFST 2 0x4001 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR4_RAWAONLANE0_DIG_RX_ADPT_IQ 2 0x4002 2 0 4294967295 IQ_ADPT_VAL 0 6 RESERVED_15_7 7 15 ixDPCSSYS_CR4_RAWAONLANE0_DIG_RX_ADAPT_FOM 2 0x4003 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR4_RAWAONLANE0_DIG_DFE_SUMMER_ODD_IDAC_OFST 2 0x4004 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR4_RAWAONLANE0_DIG_DFE_PHASE_EVEN_VDAC_OFST 2 0x4005 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR4_RAWAONLANE0_DIG_DFE_PHASE_ODD_VDAC_OFST 2 0x4006 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR4_RAWAONLANE0_DIG_DFE_EVEN_REF_LVL 2 0x4007 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR4_RAWAONLANE0_DIG_DFE_ODD_REF_LVL 2 0x4008 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR4_RAWAONLANE0_DIG_RX_PHSADJ_LIN 2 0x4009 2 0 4294967295 DATA 0 0 RESERVED_15_5 5 15 ixDPCSSYS_CR4_RAWAONLANE0_DIG_RX_PHSADJ_MAP 2 0x400a 2 0 4294967295 DATA 0 0 RESERVED_15_5 5 15 ixDPCSSYS_CR4_RAWAONLANE0_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST 2 0x400b 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR4_RAWAONLANE0_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST 2 0x400c 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR4_RAWAONLANE0_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST 2 0x400d 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR4_RAWAONLANE0_DIG_DFE_DATA_ODD_LOW_VDAC_OFST 2 0x400e 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR4_RAWAONLANE0_DIG_DFE_BYPASS_EVEN_VDAC_OFST 2 0x400f 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR4_RAWAONLANE0_DIG_DFE_BYPASS_ODD_VDAC_OFST 2 0x4010 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR4_RAWAONLANE0_DIG_DFE_ERROR_EVEN_VDAC_OFST 2 0x4011 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR4_RAWAONLANE0_DIG_DFE_ERROR_ODD_VDAC_OFST 2 0x4012 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR4_RAWAONLANE0_DIG_RX_IQ_PHASE_ADJUST 2 0x4013 2 0 4294967295 DATA 0 0 RESERVED_15_7 7 15 ixDPCSSYS_CR4_RAWAONLANE0_DIG_MPLLA_COARSE_TUNE 2 0x4014 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR4_RAWAONLANE0_DIG_MPLLB_COARSE_TUNE 2 0x4015 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR4_RAWAONLANE0_DIG_INIT_PWRUP_DONE 2 0x4016 3 0 4294967295 DATA 0 0 PH2_PWRUP_DONE 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR4_RAWAONLANE0_DIG_RX_ADPT_ATT 2 0x4017 2 0 4294967295 ATT_ADPT_VAL 0 7 RESERVED_15_8 8 15 ixDPCSSYS_CR4_RAWAONLANE0_DIG_RX_ADPT_VGA 2 0x4018 2 0 4294967295 VGA_ADPT_VAL 0 9 RESERVED_15_10 10 15 ixDPCSSYS_CR4_RAWAONLANE0_DIG_RX_ADPT_CTLE 2 0x4019 3 0 4294967295 CTLE_BOOST_ADPT_VAL 0 9 CTLE_POLE_ADPT_VAL 10 12 RESERVED_15_13 13 15 ixDPCSSYS_CR4_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP1 2 0x401a 2 0 4294967295 DFE_TAP1_ADPT_VAL 0 12 RESERVED_15_13 13 15 ixDPCSSYS_CR4_RAWAONLANE0_DIG_RX_ADAPT_DONE 2 0x401b 2 0 4294967295 DATA 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR4_RAWAONLANE0_DIG_FAST_FLAGS 2 0x401c 16 0 4294967295 FAST_RX_STARTUP_CAL 0 0 FAST_RX_ADAPT 1 1 FAST_RX_AFE_CAL 2 2 FAST_RX_DFE_CAL 3 3 FAST_RX_BYPASS_CAL 4 4 FAST_RX_REFLVL_CAL 5 5 FAST_RX_IQ_CAL 6 6 FAST_RX_AFE_ADAPT 7 7 FAST_RX_DFE_ADAPT 8 8 FAST_SUP 9 9 FAST_TX_CMN_MODE 10 10 FAST_TX_RXDET 11 11 FAST_RX_PWRUP 12 12 FAST_RX_VCO_WAIT 13 13 FAST_RX_VCO_CAL 14 14 RESERVED_15_15 15 15 ixDPCSSYS_CR4_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP2 2 0x401d 2 0 4294967295 DFE_TAP2_ADPT_VAL 0 11 RESERVED_15_12 12 15 ixDPCSSYS_CR4_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP3 2 0x401e 2 0 4294967295 DFE_TAP3_ADPT_VAL 0 11 RESERVED_15_12 12 15 ixDPCSSYS_CR4_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP4 2 0x401f 2 0 4294967295 DFE_TAP4_ADPT_VAL 0 11 RESERVED_15_12 12 15 ixDPCSSYS_CR4_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP5 2 0x4020 2 0 4294967295 DFE_TAP5_ADPT_VAL 0 11 RESERVED_15_12 12 15 ixDPCSSYS_CR4_RAWAONLANE0_DIG_RX_SLICER_CTRL_EVEN 2 0x4021 2 0 4294967295 RX_ANA_SLICER_CTRL_E 0 3 RESERVED_15_4 4 15 ixDPCSSYS_CR4_RAWAONLANE0_DIG_RX_SLICER_CTRL_ODD 2 0x4022 2 0 4294967295 RX_ANA_SLICER_CTRL_O 0 3 RESERVED_15_4 4 15 ixDPCSSYS_CR4_RAWAONLANE0_DIG_LANE_CMNCAL_MPLL_STATUS 2 0x4023 3 0 4294967295 LANE_CMNCAL_MPLL_INIT 0 0 LANE_CMNCAL_MPLL_DONE 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR4_RAWAONLANE0_DIG_ADPT_CTL_0 2 0x4024 1 0 4294967295 VAL 0 15 ixDPCSSYS_CR4_RAWAONLANE0_DIG_ADPT_CTL_1 2 0x4025 1 0 4294967295 VAL 0 15 ixDPCSSYS_CR4_RAWAONLANE0_DIG_ADPT_CTL_2 2 0x4026 1 0 4294967295 VAL 0 15 ixDPCSSYS_CR4_RAWAONLANE0_DIG_ADPT_CTL_3 2 0x4027 1 0 4294967295 VAL 0 15 ixDPCSSYS_CR4_RAWAONLANE0_DIG_ADPT_CTL_4 2 0x4028 1 0 4294967295 VAL 0 15 ixDPCSSYS_CR4_RAWAONLANE0_DIG_ADPT_CTL_5 2 0x4029 1 0 4294967295 VAL 0 15 ixDPCSSYS_CR4_RAWAONLANE0_DIG_ADPT_CTL_6 2 0x402a 1 0 4294967295 VAL 0 15 ixDPCSSYS_CR4_RAWAONLANE0_DIG_ADPT_CTL_7 2 0x402b 1 0 4294967295 VAL 0 15 ixDPCSSYS_CR4_RAWAONLANE0_DIG_MPLL_DISABLE 2 0x402c 3 0 4294967295 LANE_MPLLA_DISABLE 0 0 LANE_MPLLB_DISABLE 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR4_RAWAONLANE0_DIG_FAST_FLAGS_2 2 0x402d 16 0 4294967295 FAST_RX_CONT_CAL_ADAPT 0 0 FAST_RX_CONT_ADAPT 1 1 FAST_RX_CONT_DATA_CAL 2 2 FAST_RX_CONT_PHASE_CAL 3 3 FAST_RX_CONT_AFE_CAL 4 4 FAST_TX_CONT_DCC_CAL 5 5 FAST_RX_CONT_DCC_CAL 6 6 FAST_RX_CONT_VPHUD_CAL 7 7 FAST_RX_CONT_VREF_CAL 8 8 FAST_TX_DCC_CAL 9 9 FAST_RX_DCC_CAL 10 10 FAST_RX_VPHUD_CAL 11 11 FAST_RX_VREF_CAL 12 12 SKIP_TX_RTUNE_CAL 13 13 FAST_RX_SIGDET_CAL 14 14 RESERVED_15_15 15 15 ixDPCSSYS_CR4_RAWAONLANE0_DIG_LANE_CMNCAL_RCAL_STATUS 2 0x402e 3 0 4294967295 LANE_CMNCAL_RCAL_INIT 0 0 LANE_CMNCAL_RCAL_DONE 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR4_RAWAONLANE0_DIG_TXRX_OVRD_IN 2 0x402f 5 0 4294967295 RX_DISABLE_OVRD_VAL 0 0 RX_DISABLE_OVRD_EN 1 1 TX_DISABLE_OVRD_VAL 2 2 TX_DISABLE_OVRD_EN 3 3 RESERVED_15_4 4 15 ixDPCSSYS_CR4_RAWAONLANE0_DIG_RX_LOS_MASK_CTL 2 0x4030 2 0 4294967295 RX_LOS_MASK_CNT 0 8 RESERVED_15_9 9 15 ixDPCSSYS_CR4_RAWAONLANE0_DIG_RX_SIGDET_FILT_CTRL 2 0x4031 5 0 4294967295 ISOLATE_SIGDET_HF 0 0 RX_SIGDEF_HF_FILT_OVR_DIS 1 1 RX_SIGDEF_HF_FILT_OVR 2 2 RX_SIGDET_LF_OUT_FILT_EN 3 3 RESERVED_15_4 4 15 ixDPCSSYS_CR4_RAWAONLANE0_DIG_STATS 2 0x4032 3 0 4294967295 RX_VREFGEN_MASTER 0 0 RX_PMA_SQ_OUT 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR4_RAWAONLANE0_DIG_RX_OVRD_OUT_1 2 0x4033 11 0 4294967295 RX_PMA_SQ_CTRL_TRESH_OVRD_VAL 0 2 RX_PMA_SQ_CTRL_TRESH_OVRD_EN 3 3 RX_PMA_SQ_CTRL_RESP_OVRD_VAL 4 5 RX_PMA_SQ_CTRL_RESP_OVRD_EN 6 6 RX_PMA_SQ_WEAKKEEP_OVRD_VAL 7 7 RX_PMA_SQ_WEAKKEEP_OVRD_EN 8 8 RX_PMA_SQ_INV_POLARITY_OVRD_VAL 9 9 RX_PMA_SQ_INV_POLARITY_OVRD_EN 10 10 RX_PMA_SQ_EN_OVRD_VAL 11 11 RX_PMA_SQ_EN_OVRD_EN 12 12 RESERVED_15_13 13 15 ixDPCSSYS_CR4_RAWAONLANE0_DIG_RX_OVRD_OUT_2 2 0x4034 9 0 4294967295 RX_PMA_VREFGEN_EN_OVRD_VAL 0 0 RX_PMA_VREFGEN_EN_OVRD_EN 1 1 RX_SQ_OUT_OVRD_VAL 2 2 RX_SQ_OUT_OVRD_EN 3 3 RX_PMA_TERM_ACDC_OVRD_VAL 4 4 RX_PMA_TERM_ACDC_OVRD_EN 5 5 RX_PMA_TERM_EN_OVRD_VAL 6 6 RX_PMA_TERM_EN_OVRD_EN 7 7 RESERVED_15_8 8 15 ixDPCSSYS_CR4_RAWAONLANE0_DIG_RX_OVRD_OUT_3 2 0x4035 7 0 4294967295 RX_PMA_SIGDET_LF_FILTER_EN_OVRD_VAL 0 0 RX_PMA_SIGDET_LF_FILTER_EN_OVRD_EN 1 1 RX_PMA_SIGDET_LF_EN_OVRD_VAL 2 2 RX_PMA_SIGDET_LF_EN_OVRD_EN 3 3 RX_PMA_SIGDET_HF_EN_OVRD_VAL 4 4 RX_PMA_SIGDET_HF_EN_OVRD_EN 5 5 RESERVED_15_6 6 15 ixDPCSSYS_CR4_RAWAONLANE0_DIG_RX_SIGDET_CAL 2 0x4036 4 0 4294967295 RX_PMA_SIGDET_LF_THRESHOLD 0 2 RX_PMA_SIGDET_HF_THRESHOLD 3 5 RX_PMA_SIGDET_CAL_EN 6 6 RESERVED_15_7 7 15 ixDPCSSYS_CR4_RAWAONLANE0_DIG_RX_SIGDET_HF_CODE 2 0x4037 2 0 4294967295 RX_PMA_SIGDET_HF_CAL_TUNE 0 5 RESERVED_15_6 6 15 ixDPCSSYS_CR4_RAWAONLANE0_DIG_RX_SIGDET_LF_CODE 2 0x4038 2 0 4294967295 RX_PMA_SIGDET_LF_CAL_TUNE 0 5 RESERVED_15_6 6 15 ixDPCSSYS_CR4_RAWAONLANE0_DIG_RX_VREFGEN_EN 2 0x4039 2 0 4294967295 PULL_UP 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR4_RAWAONLANE0_DIG_CAL_IOFF_CODE 2 0x403a 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR4_RAWAONLANE0_DIG_CAL_ICONST_CODE 2 0x403b 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR4_RAWAONLANE0_DIG_CAL_VREFGEN_CODE 2 0x403c 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR4_RAWAONLANE0_DIG_RX_DCC_CAL_ICM_CODE_0 2 0x403d 2 0 4294967295 RX_DCC_CAL_ICM_CODE 0 9 RESERVED_15_10 10 15 ixDPCSSYS_CR4_RAWAONLANE0_DIG_RX_DCC_CAL_IDF_CODE_0 2 0x403e 2 0 4294967295 RX_DCC_CAL_IDF_CODE 0 9 RESERVED_15_10 10 15 ixDPCSSYS_CR4_RAWAONLANE0_DIG_RX_DCC_CAL_QCM_CODE_0 2 0x403f 2 0 4294967295 RX_DCC_CAL_QCM_CODE 0 9 RESERVED_15_10 10 15 ixDPCSSYS_CR4_RAWAONLANE0_DIG_RX_DCC_CAL_QDF_CODE_0 2 0x4040 2 0 4294967295 RX_DCC_CAL_QDF_CODE 0 9 RESERVED_15_10 10 15 ixDPCSSYS_CR4_RAWAONLANE0_DIG_RX_DCC_CAL_ICM_CODE_1 2 0x4041 2 0 4294967295 RX_DCC_CAL_ICM_CODE 0 9 RESERVED_15_10 10 15 ixDPCSSYS_CR4_RAWAONLANE0_DIG_RX_DCC_CAL_IDF_CODE_1 2 0x4042 2 0 4294967295 RX_DCC_CAL_IDF_CODE 0 9 RESERVED_15_10 10 15 ixDPCSSYS_CR4_RAWAONLANE0_DIG_RX_DCC_CAL_QCM_CODE_1 2 0x4043 2 0 4294967295 RX_DCC_CAL_QCM_CODE 0 9 RESERVED_15_10 10 15 ixDPCSSYS_CR4_RAWAONLANE0_DIG_RX_DCC_CAL_QDF_CODE_1 2 0x4044 2 0 4294967295 RX_DCC_CAL_QDF_CODE 0 9 RESERVED_15_10 10 15 ixDPCSSYS_CR4_RAWAONLANE0_DIG_TX_DCC_BANK_ADDR 2 0x4045 1 0 4294967295 ADDR 0 15 ixDPCSSYS_CR4_RAWAONLANE0_DIG_TX_DCC_BANK_DATA 2 0x4046 1 0 4294967295 DATA 0 15 ixDPCSSYS_CR4_RAWAONLANE0_DIG_TX_DCC_CONT 2 0x4047 2 0 4294967295 EN 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR4_RAWAONLANE0_DIG_MPLL_BG_CTL 2 0x4048 3 0 4294967295 MPLL_STATE_WAIT 0 0 MPLL_STATE_DLY_EN 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR4_RAWAONLANE0_DIG_SIGDET_OUT_OVRD 2 0x4049 5 0 4294967295 RX_SIGDET_HF_OUT_OVRD_VAL 0 0 RX_SIGDET_HF_OUT_OVRD_EN 1 1 RX_SIGDET_LF_OUT_OVRD_VAL 2 2 RX_SIGDET_LF_OUT_OVRD_EN 3 3 RESERVED_15_4 4 15 ixDPCSSYS_CR4_RAWAONLANE0_DIG_SIGDET_OUT_IN 2 0x404a 3 0 4294967295 RX_SIGDET_HF_OUT_OVRD_VAL 0 0 RX_SIGDET_LF_OUT_OVRD_VAL 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR4_RAWAONLANE0_DIG_FW_MM_CONFIG 2 0x404b 1 0 4294967295 DATA 0 0 ixDPCSSYS_CR4_RAWAONLANE0_DIG_FW_ADPT_CONFIG 2 0x404c 2 0 4294967295 REF_LVL_ADPT 0 7 FW_CONFIG 8 15 ixDPCSSYS_CR4_RAWAONLANE0_DIG_FW_CALIB_CONFIG 2 0x404d 1 0 4294967295 FW_CALIB 0 15 ixDPCSSYS_CR4_RAWAONLANE0_DIG_LANE_XCVR_MODE_OVRD_IN 2 0x404e 3 0 4294967295 LANE_XCVR_MODE_OVRD_VAL 0 1 LANE_XCVR_MODE_OVRD_EN 2 2 RESERVED_15_3 3 15 ixDPCSSYS_CR4_RAWAONLANE0_DIG_LANE_XCVR_MODE_IN 2 0x404f 2 0 4294967295 LANE_XCVR_MODE 0 1 RESERVED_15_2 2 15 ixDPCSSYS_CR4_RAWAONLANE0_DIG_RX_SIGDET_CONFIG 2 0x4050 4 0 4294967295 RX_SIGDET_HF_FILTER_COUNTER 0 4 RX_SIGDET_LF_FILTER_COUNTER 5 9 RX_SIGDET_LF_HOLD 10 10 RESERVED_15_11 11 15 ixDPCSSYS_CR4_RAWAONLANE0_DIG_TX_DCC_CONFIG 2 0x4051 1 0 4294967295 DATA 0 0 ixDPCSSYS_CR4_RAWAONLANE1_DIG_AFE_ATT_IDAC_OFST 2 0x4100 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR4_RAWAONLANE1_DIG_AFE_CTLE_IDAC_OFST 2 0x4101 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR4_RAWAONLANE1_DIG_RX_ADPT_IQ 2 0x4102 2 0 4294967295 IQ_ADPT_VAL 0 6 RESERVED_15_7 7 15 ixDPCSSYS_CR4_RAWAONLANE1_DIG_RX_ADAPT_FOM 2 0x4103 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR4_RAWAONLANE1_DIG_DFE_SUMMER_ODD_IDAC_OFST 2 0x4104 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR4_RAWAONLANE1_DIG_DFE_PHASE_EVEN_VDAC_OFST 2 0x4105 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR4_RAWAONLANE1_DIG_DFE_PHASE_ODD_VDAC_OFST 2 0x4106 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR4_RAWAONLANE1_DIG_DFE_EVEN_REF_LVL 2 0x4107 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR4_RAWAONLANE1_DIG_DFE_ODD_REF_LVL 2 0x4108 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR4_RAWAONLANE1_DIG_RX_PHSADJ_LIN 2 0x4109 2 0 4294967295 DATA 0 0 RESERVED_15_5 5 15 ixDPCSSYS_CR4_RAWAONLANE1_DIG_RX_PHSADJ_MAP 2 0x410a 2 0 4294967295 DATA 0 0 RESERVED_15_5 5 15 ixDPCSSYS_CR4_RAWAONLANE1_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST 2 0x410b 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR4_RAWAONLANE1_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST 2 0x410c 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR4_RAWAONLANE1_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST 2 0x410d 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR4_RAWAONLANE1_DIG_DFE_DATA_ODD_LOW_VDAC_OFST 2 0x410e 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR4_RAWAONLANE1_DIG_DFE_BYPASS_EVEN_VDAC_OFST 2 0x410f 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR4_RAWAONLANE1_DIG_DFE_BYPASS_ODD_VDAC_OFST 2 0x4110 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR4_RAWAONLANE1_DIG_DFE_ERROR_EVEN_VDAC_OFST 2 0x4111 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR4_RAWAONLANE1_DIG_DFE_ERROR_ODD_VDAC_OFST 2 0x4112 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR4_RAWAONLANE1_DIG_RX_IQ_PHASE_ADJUST 2 0x4113 2 0 4294967295 DATA 0 0 RESERVED_15_7 7 15 ixDPCSSYS_CR4_RAWAONLANE1_DIG_MPLLA_COARSE_TUNE 2 0x4114 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR4_RAWAONLANE1_DIG_MPLLB_COARSE_TUNE 2 0x4115 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR4_RAWAONLANE1_DIG_INIT_PWRUP_DONE 2 0x4116 3 0 4294967295 DATA 0 0 PH2_PWRUP_DONE 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR4_RAWAONLANE1_DIG_RX_ADPT_ATT 2 0x4117 2 0 4294967295 ATT_ADPT_VAL 0 7 RESERVED_15_8 8 15 ixDPCSSYS_CR4_RAWAONLANE1_DIG_RX_ADPT_VGA 2 0x4118 2 0 4294967295 VGA_ADPT_VAL 0 9 RESERVED_15_10 10 15 ixDPCSSYS_CR4_RAWAONLANE1_DIG_RX_ADPT_CTLE 2 0x4119 3 0 4294967295 CTLE_BOOST_ADPT_VAL 0 9 CTLE_POLE_ADPT_VAL 10 12 RESERVED_15_13 13 15 ixDPCSSYS_CR4_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP1 2 0x411a 2 0 4294967295 DFE_TAP1_ADPT_VAL 0 12 RESERVED_15_13 13 15 ixDPCSSYS_CR4_RAWAONLANE1_DIG_RX_ADAPT_DONE 2 0x411b 2 0 4294967295 DATA 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR4_RAWAONLANE1_DIG_FAST_FLAGS 2 0x411c 16 0 4294967295 FAST_RX_STARTUP_CAL 0 0 FAST_RX_ADAPT 1 1 FAST_RX_AFE_CAL 2 2 FAST_RX_DFE_CAL 3 3 FAST_RX_BYPASS_CAL 4 4 FAST_RX_REFLVL_CAL 5 5 FAST_RX_IQ_CAL 6 6 FAST_RX_AFE_ADAPT 7 7 FAST_RX_DFE_ADAPT 8 8 FAST_SUP 9 9 FAST_TX_CMN_MODE 10 10 FAST_TX_RXDET 11 11 FAST_RX_PWRUP 12 12 FAST_RX_VCO_WAIT 13 13 FAST_RX_VCO_CAL 14 14 RESERVED_15_15 15 15 ixDPCSSYS_CR4_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP2 2 0x411d 2 0 4294967295 DFE_TAP2_ADPT_VAL 0 11 RESERVED_15_12 12 15 ixDPCSSYS_CR4_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP3 2 0x411e 2 0 4294967295 DFE_TAP3_ADPT_VAL 0 11 RESERVED_15_12 12 15 ixDPCSSYS_CR4_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP4 2 0x411f 2 0 4294967295 DFE_TAP4_ADPT_VAL 0 11 RESERVED_15_12 12 15 ixDPCSSYS_CR4_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP5 2 0x4120 2 0 4294967295 DFE_TAP5_ADPT_VAL 0 11 RESERVED_15_12 12 15 ixDPCSSYS_CR4_RAWAONLANE1_DIG_RX_SLICER_CTRL_EVEN 2 0x4121 2 0 4294967295 RX_ANA_SLICER_CTRL_E 0 3 RESERVED_15_4 4 15 ixDPCSSYS_CR4_RAWAONLANE1_DIG_RX_SLICER_CTRL_ODD 2 0x4122 2 0 4294967295 RX_ANA_SLICER_CTRL_O 0 3 RESERVED_15_4 4 15 ixDPCSSYS_CR4_RAWAONLANE1_DIG_LANE_CMNCAL_MPLL_STATUS 2 0x4123 3 0 4294967295 LANE_CMNCAL_MPLL_INIT 0 0 LANE_CMNCAL_MPLL_DONE 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR4_RAWAONLANE1_DIG_ADPT_CTL_0 2 0x4124 1 0 4294967295 VAL 0 15 ixDPCSSYS_CR4_RAWAONLANE1_DIG_ADPT_CTL_1 2 0x4125 1 0 4294967295 VAL 0 15 ixDPCSSYS_CR4_RAWAONLANE1_DIG_ADPT_CTL_2 2 0x4126 1 0 4294967295 VAL 0 15 ixDPCSSYS_CR4_RAWAONLANE1_DIG_ADPT_CTL_3 2 0x4127 1 0 4294967295 VAL 0 15 ixDPCSSYS_CR4_RAWAONLANE1_DIG_ADPT_CTL_4 2 0x4128 1 0 4294967295 VAL 0 15 ixDPCSSYS_CR4_RAWAONLANE1_DIG_ADPT_CTL_5 2 0x4129 1 0 4294967295 VAL 0 15 ixDPCSSYS_CR4_RAWAONLANE1_DIG_ADPT_CTL_6 2 0x412a 1 0 4294967295 VAL 0 15 ixDPCSSYS_CR4_RAWAONLANE1_DIG_ADPT_CTL_7 2 0x412b 1 0 4294967295 VAL 0 15 ixDPCSSYS_CR4_RAWAONLANE1_DIG_MPLL_DISABLE 2 0x412c 3 0 4294967295 LANE_MPLLA_DISABLE 0 0 LANE_MPLLB_DISABLE 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR4_RAWAONLANE1_DIG_FAST_FLAGS_2 2 0x412d 16 0 4294967295 FAST_RX_CONT_CAL_ADAPT 0 0 FAST_RX_CONT_ADAPT 1 1 FAST_RX_CONT_DATA_CAL 2 2 FAST_RX_CONT_PHASE_CAL 3 3 FAST_RX_CONT_AFE_CAL 4 4 FAST_TX_CONT_DCC_CAL 5 5 FAST_RX_CONT_DCC_CAL 6 6 FAST_RX_CONT_VPHUD_CAL 7 7 FAST_RX_CONT_VREF_CAL 8 8 FAST_TX_DCC_CAL 9 9 FAST_RX_DCC_CAL 10 10 FAST_RX_VPHUD_CAL 11 11 FAST_RX_VREF_CAL 12 12 SKIP_TX_RTUNE_CAL 13 13 FAST_RX_SIGDET_CAL 14 14 RESERVED_15_15 15 15 ixDPCSSYS_CR4_RAWAONLANE1_DIG_LANE_CMNCAL_RCAL_STATUS 2 0x412e 3 0 4294967295 LANE_CMNCAL_RCAL_INIT 0 0 LANE_CMNCAL_RCAL_DONE 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR4_RAWAONLANE1_DIG_TXRX_OVRD_IN 2 0x412f 5 0 4294967295 RX_DISABLE_OVRD_VAL 0 0 RX_DISABLE_OVRD_EN 1 1 TX_DISABLE_OVRD_VAL 2 2 TX_DISABLE_OVRD_EN 3 3 RESERVED_15_4 4 15 ixDPCSSYS_CR4_RAWAONLANE1_DIG_RX_LOS_MASK_CTL 2 0x4130 2 0 4294967295 RX_LOS_MASK_CNT 0 8 RESERVED_15_9 9 15 ixDPCSSYS_CR4_RAWAONLANE1_DIG_RX_SIGDET_FILT_CTRL 2 0x4131 5 0 4294967295 ISOLATE_SIGDET_HF 0 0 RX_SIGDEF_HF_FILT_OVR_DIS 1 1 RX_SIGDEF_HF_FILT_OVR 2 2 RX_SIGDET_LF_OUT_FILT_EN 3 3 RESERVED_15_4 4 15 ixDPCSSYS_CR4_RAWAONLANE1_DIG_STATS 2 0x4132 3 0 4294967295 RX_VREFGEN_MASTER 0 0 RX_PMA_SQ_OUT 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR4_RAWAONLANE1_DIG_RX_OVRD_OUT_1 2 0x4133 11 0 4294967295 RX_PMA_SQ_CTRL_TRESH_OVRD_VAL 0 2 RX_PMA_SQ_CTRL_TRESH_OVRD_EN 3 3 RX_PMA_SQ_CTRL_RESP_OVRD_VAL 4 5 RX_PMA_SQ_CTRL_RESP_OVRD_EN 6 6 RX_PMA_SQ_WEAKKEEP_OVRD_VAL 7 7 RX_PMA_SQ_WEAKKEEP_OVRD_EN 8 8 RX_PMA_SQ_INV_POLARITY_OVRD_VAL 9 9 RX_PMA_SQ_INV_POLARITY_OVRD_EN 10 10 RX_PMA_SQ_EN_OVRD_VAL 11 11 RX_PMA_SQ_EN_OVRD_EN 12 12 RESERVED_15_13 13 15 ixDPCSSYS_CR4_RAWAONLANE1_DIG_RX_OVRD_OUT_2 2 0x4134 9 0 4294967295 RX_PMA_VREFGEN_EN_OVRD_VAL 0 0 RX_PMA_VREFGEN_EN_OVRD_EN 1 1 RX_SQ_OUT_OVRD_VAL 2 2 RX_SQ_OUT_OVRD_EN 3 3 RX_PMA_TERM_ACDC_OVRD_VAL 4 4 RX_PMA_TERM_ACDC_OVRD_EN 5 5 RX_PMA_TERM_EN_OVRD_VAL 6 6 RX_PMA_TERM_EN_OVRD_EN 7 7 RESERVED_15_8 8 15 ixDPCSSYS_CR4_RAWAONLANE1_DIG_RX_OVRD_OUT_3 2 0x4135 7 0 4294967295 RX_PMA_SIGDET_LF_FILTER_EN_OVRD_VAL 0 0 RX_PMA_SIGDET_LF_FILTER_EN_OVRD_EN 1 1 RX_PMA_SIGDET_LF_EN_OVRD_VAL 2 2 RX_PMA_SIGDET_LF_EN_OVRD_EN 3 3 RX_PMA_SIGDET_HF_EN_OVRD_VAL 4 4 RX_PMA_SIGDET_HF_EN_OVRD_EN 5 5 RESERVED_15_6 6 15 ixDPCSSYS_CR4_RAWAONLANE1_DIG_RX_SIGDET_CAL 2 0x4136 4 0 4294967295 RX_PMA_SIGDET_LF_THRESHOLD 0 2 RX_PMA_SIGDET_HF_THRESHOLD 3 5 RX_PMA_SIGDET_CAL_EN 6 6 RESERVED_15_7 7 15 ixDPCSSYS_CR4_RAWAONLANE1_DIG_RX_SIGDET_HF_CODE 2 0x4137 2 0 4294967295 RX_PMA_SIGDET_HF_CAL_TUNE 0 5 RESERVED_15_6 6 15 ixDPCSSYS_CR4_RAWAONLANE1_DIG_RX_SIGDET_LF_CODE 2 0x4138 2 0 4294967295 RX_PMA_SIGDET_LF_CAL_TUNE 0 5 RESERVED_15_6 6 15 ixDPCSSYS_CR4_RAWAONLANE1_DIG_RX_VREFGEN_EN 2 0x4139 2 0 4294967295 PULL_UP 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR4_RAWAONLANE1_DIG_CAL_IOFF_CODE 2 0x413a 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR4_RAWAONLANE1_DIG_CAL_ICONST_CODE 2 0x413b 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR4_RAWAONLANE1_DIG_CAL_VREFGEN_CODE 2 0x413c 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR4_RAWAONLANE1_DIG_RX_DCC_CAL_ICM_CODE_0 2 0x413d 2 0 4294967295 RX_DCC_CAL_ICM_CODE 0 9 RESERVED_15_10 10 15 ixDPCSSYS_CR4_RAWAONLANE1_DIG_RX_DCC_CAL_IDF_CODE_0 2 0x413e 2 0 4294967295 RX_DCC_CAL_IDF_CODE 0 9 RESERVED_15_10 10 15 ixDPCSSYS_CR4_RAWAONLANE1_DIG_RX_DCC_CAL_QCM_CODE_0 2 0x413f 2 0 4294967295 RX_DCC_CAL_QCM_CODE 0 9 RESERVED_15_10 10 15 ixDPCSSYS_CR4_RAWAONLANE1_DIG_RX_DCC_CAL_QDF_CODE_0 2 0x4140 2 0 4294967295 RX_DCC_CAL_QDF_CODE 0 9 RESERVED_15_10 10 15 ixDPCSSYS_CR4_RAWAONLANE1_DIG_RX_DCC_CAL_ICM_CODE_1 2 0x4141 2 0 4294967295 RX_DCC_CAL_ICM_CODE 0 9 RESERVED_15_10 10 15 ixDPCSSYS_CR4_RAWAONLANE1_DIG_RX_DCC_CAL_IDF_CODE_1 2 0x4142 2 0 4294967295 RX_DCC_CAL_IDF_CODE 0 9 RESERVED_15_10 10 15 ixDPCSSYS_CR4_RAWAONLANE1_DIG_RX_DCC_CAL_QCM_CODE_1 2 0x4143 2 0 4294967295 RX_DCC_CAL_QCM_CODE 0 9 RESERVED_15_10 10 15 ixDPCSSYS_CR4_RAWAONLANE1_DIG_RX_DCC_CAL_QDF_CODE_1 2 0x4144 2 0 4294967295 RX_DCC_CAL_QDF_CODE 0 9 RESERVED_15_10 10 15 ixDPCSSYS_CR4_RAWAONLANE1_DIG_TX_DCC_BANK_ADDR 2 0x4145 1 0 4294967295 ADDR 0 15 ixDPCSSYS_CR4_RAWAONLANE1_DIG_TX_DCC_BANK_DATA 2 0x4146 1 0 4294967295 DATA 0 15 ixDPCSSYS_CR4_RAWAONLANE1_DIG_TX_DCC_CONT 2 0x4147 2 0 4294967295 EN 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR4_RAWAONLANE1_DIG_MPLL_BG_CTL 2 0x4148 3 0 4294967295 MPLL_STATE_WAIT 0 0 MPLL_STATE_DLY_EN 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR4_RAWAONLANE1_DIG_SIGDET_OUT_OVRD 2 0x4149 5 0 4294967295 RX_SIGDET_HF_OUT_OVRD_VAL 0 0 RX_SIGDET_HF_OUT_OVRD_EN 1 1 RX_SIGDET_LF_OUT_OVRD_VAL 2 2 RX_SIGDET_LF_OUT_OVRD_EN 3 3 RESERVED_15_4 4 15 ixDPCSSYS_CR4_RAWAONLANE1_DIG_SIGDET_OUT_IN 2 0x414a 3 0 4294967295 RX_SIGDET_HF_OUT_OVRD_VAL 0 0 RX_SIGDET_LF_OUT_OVRD_VAL 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR4_RAWAONLANE1_DIG_FW_MM_CONFIG 2 0x414b 1 0 4294967295 DATA 0 0 ixDPCSSYS_CR4_RAWAONLANE1_DIG_FW_ADPT_CONFIG 2 0x414c 2 0 4294967295 REF_LVL_ADPT 0 7 FW_CONFIG 8 15 ixDPCSSYS_CR4_RAWAONLANE1_DIG_FW_CALIB_CONFIG 2 0x414d 1 0 4294967295 FW_CALIB 0 15 ixDPCSSYS_CR4_RAWAONLANE1_DIG_LANE_XCVR_MODE_OVRD_IN 2 0x414e 3 0 4294967295 LANE_XCVR_MODE_OVRD_VAL 0 1 LANE_XCVR_MODE_OVRD_EN 2 2 RESERVED_15_3 3 15 ixDPCSSYS_CR4_RAWAONLANE1_DIG_LANE_XCVR_MODE_IN 2 0x414f 2 0 4294967295 LANE_XCVR_MODE 0 1 RESERVED_15_2 2 15 ixDPCSSYS_CR4_RAWAONLANE1_DIG_RX_SIGDET_CONFIG 2 0x4150 4 0 4294967295 RX_SIGDET_HF_FILTER_COUNTER 0 4 RX_SIGDET_LF_FILTER_COUNTER 5 9 RX_SIGDET_LF_HOLD 10 10 RESERVED_15_11 11 15 ixDPCSSYS_CR4_RAWAONLANE1_DIG_TX_DCC_CONFIG 2 0x4151 1 0 4294967295 DATA 0 0 ixDPCSSYS_CR4_RAWAONLANE2_DIG_AFE_ATT_IDAC_OFST 2 0x4200 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR4_RAWAONLANE2_DIG_AFE_CTLE_IDAC_OFST 2 0x4201 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR4_RAWAONLANE2_DIG_RX_ADPT_IQ 2 0x4202 2 0 4294967295 IQ_ADPT_VAL 0 6 RESERVED_15_7 7 15 ixDPCSSYS_CR4_RAWAONLANE2_DIG_RX_ADAPT_FOM 2 0x4203 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR4_RAWAONLANE2_DIG_DFE_SUMMER_ODD_IDAC_OFST 2 0x4204 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR4_RAWAONLANE2_DIG_DFE_PHASE_EVEN_VDAC_OFST 2 0x4205 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR4_RAWAONLANE2_DIG_DFE_PHASE_ODD_VDAC_OFST 2 0x4206 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR4_RAWAONLANE2_DIG_DFE_EVEN_REF_LVL 2 0x4207 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR4_RAWAONLANE2_DIG_DFE_ODD_REF_LVL 2 0x4208 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR4_RAWAONLANE2_DIG_RX_PHSADJ_LIN 2 0x4209 2 0 4294967295 DATA 0 0 RESERVED_15_5 5 15 ixDPCSSYS_CR4_RAWAONLANE2_DIG_RX_PHSADJ_MAP 2 0x420a 2 0 4294967295 DATA 0 0 RESERVED_15_5 5 15 ixDPCSSYS_CR4_RAWAONLANE2_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST 2 0x420b 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR4_RAWAONLANE2_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST 2 0x420c 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR4_RAWAONLANE2_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST 2 0x420d 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR4_RAWAONLANE2_DIG_DFE_DATA_ODD_LOW_VDAC_OFST 2 0x420e 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR4_RAWAONLANE2_DIG_DFE_BYPASS_EVEN_VDAC_OFST 2 0x420f 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR4_RAWAONLANE2_DIG_DFE_BYPASS_ODD_VDAC_OFST 2 0x4210 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR4_RAWAONLANE2_DIG_DFE_ERROR_EVEN_VDAC_OFST 2 0x4211 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR4_RAWAONLANE2_DIG_DFE_ERROR_ODD_VDAC_OFST 2 0x4212 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR4_RAWAONLANE2_DIG_RX_IQ_PHASE_ADJUST 2 0x4213 2 0 4294967295 DATA 0 0 RESERVED_15_7 7 15 ixDPCSSYS_CR4_RAWAONLANE2_DIG_MPLLA_COARSE_TUNE 2 0x4214 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR4_RAWAONLANE2_DIG_MPLLB_COARSE_TUNE 2 0x4215 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR4_RAWAONLANE2_DIG_INIT_PWRUP_DONE 2 0x4216 3 0 4294967295 DATA 0 0 PH2_PWRUP_DONE 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR4_RAWAONLANE2_DIG_RX_ADPT_ATT 2 0x4217 2 0 4294967295 ATT_ADPT_VAL 0 7 RESERVED_15_8 8 15 ixDPCSSYS_CR4_RAWAONLANE2_DIG_RX_ADPT_VGA 2 0x4218 2 0 4294967295 VGA_ADPT_VAL 0 9 RESERVED_15_10 10 15 ixDPCSSYS_CR4_RAWAONLANE2_DIG_RX_ADPT_CTLE 2 0x4219 3 0 4294967295 CTLE_BOOST_ADPT_VAL 0 9 CTLE_POLE_ADPT_VAL 10 12 RESERVED_15_13 13 15 ixDPCSSYS_CR4_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP1 2 0x421a 2 0 4294967295 DFE_TAP1_ADPT_VAL 0 12 RESERVED_15_13 13 15 ixDPCSSYS_CR4_RAWAONLANE2_DIG_RX_ADAPT_DONE 2 0x421b 2 0 4294967295 DATA 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR4_RAWAONLANE2_DIG_FAST_FLAGS 2 0x421c 16 0 4294967295 FAST_RX_STARTUP_CAL 0 0 FAST_RX_ADAPT 1 1 FAST_RX_AFE_CAL 2 2 FAST_RX_DFE_CAL 3 3 FAST_RX_BYPASS_CAL 4 4 FAST_RX_REFLVL_CAL 5 5 FAST_RX_IQ_CAL 6 6 FAST_RX_AFE_ADAPT 7 7 FAST_RX_DFE_ADAPT 8 8 FAST_SUP 9 9 FAST_TX_CMN_MODE 10 10 FAST_TX_RXDET 11 11 FAST_RX_PWRUP 12 12 FAST_RX_VCO_WAIT 13 13 FAST_RX_VCO_CAL 14 14 RESERVED_15_15 15 15 ixDPCSSYS_CR4_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP2 2 0x421d 2 0 4294967295 DFE_TAP2_ADPT_VAL 0 11 RESERVED_15_12 12 15 ixDPCSSYS_CR4_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP3 2 0x421e 2 0 4294967295 DFE_TAP3_ADPT_VAL 0 11 RESERVED_15_12 12 15 ixDPCSSYS_CR4_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP4 2 0x421f 2 0 4294967295 DFE_TAP4_ADPT_VAL 0 11 RESERVED_15_12 12 15 ixDPCSSYS_CR4_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP5 2 0x4220 2 0 4294967295 DFE_TAP5_ADPT_VAL 0 11 RESERVED_15_12 12 15 ixDPCSSYS_CR4_RAWAONLANE2_DIG_RX_SLICER_CTRL_EVEN 2 0x4221 2 0 4294967295 RX_ANA_SLICER_CTRL_E 0 3 RESERVED_15_4 4 15 ixDPCSSYS_CR4_RAWAONLANE2_DIG_RX_SLICER_CTRL_ODD 2 0x4222 2 0 4294967295 RX_ANA_SLICER_CTRL_O 0 3 RESERVED_15_4 4 15 ixDPCSSYS_CR4_RAWAONLANE2_DIG_LANE_CMNCAL_MPLL_STATUS 2 0x4223 3 0 4294967295 LANE_CMNCAL_MPLL_INIT 0 0 LANE_CMNCAL_MPLL_DONE 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR4_RAWAONLANE2_DIG_ADPT_CTL_0 2 0x4224 1 0 4294967295 VAL 0 15 ixDPCSSYS_CR4_RAWAONLANE2_DIG_ADPT_CTL_1 2 0x4225 1 0 4294967295 VAL 0 15 ixDPCSSYS_CR4_RAWAONLANE2_DIG_ADPT_CTL_2 2 0x4226 1 0 4294967295 VAL 0 15 ixDPCSSYS_CR4_RAWAONLANE2_DIG_ADPT_CTL_3 2 0x4227 1 0 4294967295 VAL 0 15 ixDPCSSYS_CR4_RAWAONLANE2_DIG_ADPT_CTL_4 2 0x4228 1 0 4294967295 VAL 0 15 ixDPCSSYS_CR4_RAWAONLANE2_DIG_ADPT_CTL_5 2 0x4229 1 0 4294967295 VAL 0 15 ixDPCSSYS_CR4_RAWAONLANE2_DIG_ADPT_CTL_6 2 0x422a 1 0 4294967295 VAL 0 15 ixDPCSSYS_CR4_RAWAONLANE2_DIG_ADPT_CTL_7 2 0x422b 1 0 4294967295 VAL 0 15 ixDPCSSYS_CR4_RAWAONLANE2_DIG_MPLL_DISABLE 2 0x422c 3 0 4294967295 LANE_MPLLA_DISABLE 0 0 LANE_MPLLB_DISABLE 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR4_RAWAONLANE2_DIG_FAST_FLAGS_2 2 0x422d 16 0 4294967295 FAST_RX_CONT_CAL_ADAPT 0 0 FAST_RX_CONT_ADAPT 1 1 FAST_RX_CONT_DATA_CAL 2 2 FAST_RX_CONT_PHASE_CAL 3 3 FAST_RX_CONT_AFE_CAL 4 4 FAST_TX_CONT_DCC_CAL 5 5 FAST_RX_CONT_DCC_CAL 6 6 FAST_RX_CONT_VPHUD_CAL 7 7 FAST_RX_CONT_VREF_CAL 8 8 FAST_TX_DCC_CAL 9 9 FAST_RX_DCC_CAL 10 10 FAST_RX_VPHUD_CAL 11 11 FAST_RX_VREF_CAL 12 12 SKIP_TX_RTUNE_CAL 13 13 FAST_RX_SIGDET_CAL 14 14 RESERVED_15_15 15 15 ixDPCSSYS_CR4_RAWAONLANE2_DIG_LANE_CMNCAL_RCAL_STATUS 2 0x422e 3 0 4294967295 LANE_CMNCAL_RCAL_INIT 0 0 LANE_CMNCAL_RCAL_DONE 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR4_RAWAONLANE2_DIG_TXRX_OVRD_IN 2 0x422f 5 0 4294967295 RX_DISABLE_OVRD_VAL 0 0 RX_DISABLE_OVRD_EN 1 1 TX_DISABLE_OVRD_VAL 2 2 TX_DISABLE_OVRD_EN 3 3 RESERVED_15_4 4 15 ixDPCSSYS_CR4_RAWAONLANE2_DIG_RX_LOS_MASK_CTL 2 0x4230 2 0 4294967295 RX_LOS_MASK_CNT 0 8 RESERVED_15_9 9 15 ixDPCSSYS_CR4_RAWAONLANE2_DIG_RX_SIGDET_FILT_CTRL 2 0x4231 5 0 4294967295 ISOLATE_SIGDET_HF 0 0 RX_SIGDEF_HF_FILT_OVR_DIS 1 1 RX_SIGDEF_HF_FILT_OVR 2 2 RX_SIGDET_LF_OUT_FILT_EN 3 3 RESERVED_15_4 4 15 ixDPCSSYS_CR4_RAWAONLANE2_DIG_STATS 2 0x4232 3 0 4294967295 RX_VREFGEN_MASTER 0 0 RX_PMA_SQ_OUT 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR4_RAWAONLANE2_DIG_RX_OVRD_OUT_1 2 0x4233 11 0 4294967295 RX_PMA_SQ_CTRL_TRESH_OVRD_VAL 0 2 RX_PMA_SQ_CTRL_TRESH_OVRD_EN 3 3 RX_PMA_SQ_CTRL_RESP_OVRD_VAL 4 5 RX_PMA_SQ_CTRL_RESP_OVRD_EN 6 6 RX_PMA_SQ_WEAKKEEP_OVRD_VAL 7 7 RX_PMA_SQ_WEAKKEEP_OVRD_EN 8 8 RX_PMA_SQ_INV_POLARITY_OVRD_VAL 9 9 RX_PMA_SQ_INV_POLARITY_OVRD_EN 10 10 RX_PMA_SQ_EN_OVRD_VAL 11 11 RX_PMA_SQ_EN_OVRD_EN 12 12 RESERVED_15_13 13 15 ixDPCSSYS_CR4_RAWAONLANE2_DIG_RX_OVRD_OUT_2 2 0x4234 9 0 4294967295 RX_PMA_VREFGEN_EN_OVRD_VAL 0 0 RX_PMA_VREFGEN_EN_OVRD_EN 1 1 RX_SQ_OUT_OVRD_VAL 2 2 RX_SQ_OUT_OVRD_EN 3 3 RX_PMA_TERM_ACDC_OVRD_VAL 4 4 RX_PMA_TERM_ACDC_OVRD_EN 5 5 RX_PMA_TERM_EN_OVRD_VAL 6 6 RX_PMA_TERM_EN_OVRD_EN 7 7 RESERVED_15_8 8 15 ixDPCSSYS_CR4_RAWAONLANE2_DIG_RX_OVRD_OUT_3 2 0x4235 7 0 4294967295 RX_PMA_SIGDET_LF_FILTER_EN_OVRD_VAL 0 0 RX_PMA_SIGDET_LF_FILTER_EN_OVRD_EN 1 1 RX_PMA_SIGDET_LF_EN_OVRD_VAL 2 2 RX_PMA_SIGDET_LF_EN_OVRD_EN 3 3 RX_PMA_SIGDET_HF_EN_OVRD_VAL 4 4 RX_PMA_SIGDET_HF_EN_OVRD_EN 5 5 RESERVED_15_6 6 15 ixDPCSSYS_CR4_RAWAONLANE2_DIG_RX_SIGDET_CAL 2 0x4236 4 0 4294967295 RX_PMA_SIGDET_LF_THRESHOLD 0 2 RX_PMA_SIGDET_HF_THRESHOLD 3 5 RX_PMA_SIGDET_CAL_EN 6 6 RESERVED_15_7 7 15 ixDPCSSYS_CR4_RAWAONLANE2_DIG_RX_SIGDET_HF_CODE 2 0x4237 2 0 4294967295 RX_PMA_SIGDET_HF_CAL_TUNE 0 5 RESERVED_15_6 6 15 ixDPCSSYS_CR4_RAWAONLANE2_DIG_RX_SIGDET_LF_CODE 2 0x4238 2 0 4294967295 RX_PMA_SIGDET_LF_CAL_TUNE 0 5 RESERVED_15_6 6 15 ixDPCSSYS_CR4_RAWAONLANE2_DIG_RX_VREFGEN_EN 2 0x4239 2 0 4294967295 PULL_UP 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR4_RAWAONLANE2_DIG_CAL_IOFF_CODE 2 0x423a 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR4_RAWAONLANE2_DIG_CAL_ICONST_CODE 2 0x423b 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR4_RAWAONLANE2_DIG_CAL_VREFGEN_CODE 2 0x423c 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR4_RAWAONLANE2_DIG_RX_DCC_CAL_ICM_CODE_0 2 0x423d 2 0 4294967295 RX_DCC_CAL_ICM_CODE 0 9 RESERVED_15_10 10 15 ixDPCSSYS_CR4_RAWAONLANE2_DIG_RX_DCC_CAL_IDF_CODE_0 2 0x423e 2 0 4294967295 RX_DCC_CAL_IDF_CODE 0 9 RESERVED_15_10 10 15 ixDPCSSYS_CR4_RAWAONLANE2_DIG_RX_DCC_CAL_QCM_CODE_0 2 0x423f 2 0 4294967295 RX_DCC_CAL_QCM_CODE 0 9 RESERVED_15_10 10 15 ixDPCSSYS_CR4_RAWAONLANE2_DIG_RX_DCC_CAL_QDF_CODE_0 2 0x4240 2 0 4294967295 RX_DCC_CAL_QDF_CODE 0 9 RESERVED_15_10 10 15 ixDPCSSYS_CR4_RAWAONLANE2_DIG_RX_DCC_CAL_ICM_CODE_1 2 0x4241 2 0 4294967295 RX_DCC_CAL_ICM_CODE 0 9 RESERVED_15_10 10 15 ixDPCSSYS_CR4_RAWAONLANE2_DIG_RX_DCC_CAL_IDF_CODE_1 2 0x4242 2 0 4294967295 RX_DCC_CAL_IDF_CODE 0 9 RESERVED_15_10 10 15 ixDPCSSYS_CR4_RAWAONLANE2_DIG_RX_DCC_CAL_QCM_CODE_1 2 0x4243 2 0 4294967295 RX_DCC_CAL_QCM_CODE 0 9 RESERVED_15_10 10 15 ixDPCSSYS_CR4_RAWAONLANE2_DIG_RX_DCC_CAL_QDF_CODE_1 2 0x4244 2 0 4294967295 RX_DCC_CAL_QDF_CODE 0 9 RESERVED_15_10 10 15 ixDPCSSYS_CR4_RAWAONLANE2_DIG_TX_DCC_BANK_ADDR 2 0x4245 1 0 4294967295 ADDR 0 15 ixDPCSSYS_CR4_RAWAONLANE2_DIG_TX_DCC_BANK_DATA 2 0x4246 1 0 4294967295 DATA 0 15 ixDPCSSYS_CR4_RAWAONLANE2_DIG_TX_DCC_CONT 2 0x4247 2 0 4294967295 EN 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR4_RAWAONLANE2_DIG_MPLL_BG_CTL 2 0x4248 3 0 4294967295 MPLL_STATE_WAIT 0 0 MPLL_STATE_DLY_EN 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR4_RAWAONLANE2_DIG_SIGDET_OUT_OVRD 2 0x4249 5 0 4294967295 RX_SIGDET_HF_OUT_OVRD_VAL 0 0 RX_SIGDET_HF_OUT_OVRD_EN 1 1 RX_SIGDET_LF_OUT_OVRD_VAL 2 2 RX_SIGDET_LF_OUT_OVRD_EN 3 3 RESERVED_15_4 4 15 ixDPCSSYS_CR4_RAWAONLANE2_DIG_SIGDET_OUT_IN 2 0x424a 3 0 4294967295 RX_SIGDET_HF_OUT_OVRD_VAL 0 0 RX_SIGDET_LF_OUT_OVRD_VAL 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR4_RAWAONLANE2_DIG_FW_MM_CONFIG 2 0x424b 1 0 4294967295 DATA 0 0 ixDPCSSYS_CR4_RAWAONLANE2_DIG_FW_ADPT_CONFIG 2 0x424c 2 0 4294967295 REF_LVL_ADPT 0 7 FW_CONFIG 8 15 ixDPCSSYS_CR4_RAWAONLANE2_DIG_FW_CALIB_CONFIG 2 0x424d 1 0 4294967295 FW_CALIB 0 15 ixDPCSSYS_CR4_RAWAONLANE2_DIG_LANE_XCVR_MODE_OVRD_IN 2 0x424e 3 0 4294967295 LANE_XCVR_MODE_OVRD_VAL 0 1 LANE_XCVR_MODE_OVRD_EN 2 2 RESERVED_15_3 3 15 ixDPCSSYS_CR4_RAWAONLANE2_DIG_LANE_XCVR_MODE_IN 2 0x424f 2 0 4294967295 LANE_XCVR_MODE 0 1 RESERVED_15_2 2 15 ixDPCSSYS_CR4_RAWAONLANE2_DIG_RX_SIGDET_CONFIG 2 0x4250 4 0 4294967295 RX_SIGDET_HF_FILTER_COUNTER 0 4 RX_SIGDET_LF_FILTER_COUNTER 5 9 RX_SIGDET_LF_HOLD 10 10 RESERVED_15_11 11 15 ixDPCSSYS_CR4_RAWAONLANE2_DIG_TX_DCC_CONFIG 2 0x4251 1 0 4294967295 DATA 0 0 ixDPCSSYS_CR4_RAWAONLANE3_DIG_AFE_ATT_IDAC_OFST 2 0x4300 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR4_RAWAONLANE3_DIG_AFE_CTLE_IDAC_OFST 2 0x4301 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR4_RAWAONLANE3_DIG_RX_ADPT_IQ 2 0x4302 2 0 4294967295 IQ_ADPT_VAL 0 6 RESERVED_15_7 7 15 ixDPCSSYS_CR4_RAWAONLANE3_DIG_RX_ADAPT_FOM 2 0x4303 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR4_RAWAONLANE3_DIG_DFE_SUMMER_ODD_IDAC_OFST 2 0x4304 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR4_RAWAONLANE3_DIG_DFE_PHASE_EVEN_VDAC_OFST 2 0x4305 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR4_RAWAONLANE3_DIG_DFE_PHASE_ODD_VDAC_OFST 2 0x4306 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR4_RAWAONLANE3_DIG_DFE_EVEN_REF_LVL 2 0x4307 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR4_RAWAONLANE3_DIG_DFE_ODD_REF_LVL 2 0x4308 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR4_RAWAONLANE3_DIG_RX_PHSADJ_LIN 2 0x4309 2 0 4294967295 DATA 0 0 RESERVED_15_5 5 15 ixDPCSSYS_CR4_RAWAONLANE3_DIG_RX_PHSADJ_MAP 2 0x430a 2 0 4294967295 DATA 0 0 RESERVED_15_5 5 15 ixDPCSSYS_CR4_RAWAONLANE3_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST 2 0x430b 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR4_RAWAONLANE3_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST 2 0x430c 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR4_RAWAONLANE3_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST 2 0x430d 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR4_RAWAONLANE3_DIG_DFE_DATA_ODD_LOW_VDAC_OFST 2 0x430e 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR4_RAWAONLANE3_DIG_DFE_BYPASS_EVEN_VDAC_OFST 2 0x430f 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR4_RAWAONLANE3_DIG_DFE_BYPASS_ODD_VDAC_OFST 2 0x4310 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR4_RAWAONLANE3_DIG_DFE_ERROR_EVEN_VDAC_OFST 2 0x4311 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR4_RAWAONLANE3_DIG_DFE_ERROR_ODD_VDAC_OFST 2 0x4312 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR4_RAWAONLANE3_DIG_RX_IQ_PHASE_ADJUST 2 0x4313 2 0 4294967295 DATA 0 0 RESERVED_15_7 7 15 ixDPCSSYS_CR4_RAWAONLANE3_DIG_MPLLA_COARSE_TUNE 2 0x4314 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR4_RAWAONLANE3_DIG_MPLLB_COARSE_TUNE 2 0x4315 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR4_RAWAONLANE3_DIG_INIT_PWRUP_DONE 2 0x4316 3 0 4294967295 DATA 0 0 PH2_PWRUP_DONE 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR4_RAWAONLANE3_DIG_RX_ADPT_ATT 2 0x4317 2 0 4294967295 ATT_ADPT_VAL 0 7 RESERVED_15_8 8 15 ixDPCSSYS_CR4_RAWAONLANE3_DIG_RX_ADPT_VGA 2 0x4318 2 0 4294967295 VGA_ADPT_VAL 0 9 RESERVED_15_10 10 15 ixDPCSSYS_CR4_RAWAONLANE3_DIG_RX_ADPT_CTLE 2 0x4319 3 0 4294967295 CTLE_BOOST_ADPT_VAL 0 9 CTLE_POLE_ADPT_VAL 10 12 RESERVED_15_13 13 15 ixDPCSSYS_CR4_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP1 2 0x431a 2 0 4294967295 DFE_TAP1_ADPT_VAL 0 12 RESERVED_15_13 13 15 ixDPCSSYS_CR4_RAWAONLANE3_DIG_RX_ADAPT_DONE 2 0x431b 2 0 4294967295 DATA 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR4_RAWAONLANE3_DIG_FAST_FLAGS 2 0x431c 16 0 4294967295 FAST_RX_STARTUP_CAL 0 0 FAST_RX_ADAPT 1 1 FAST_RX_AFE_CAL 2 2 FAST_RX_DFE_CAL 3 3 FAST_RX_BYPASS_CAL 4 4 FAST_RX_REFLVL_CAL 5 5 FAST_RX_IQ_CAL 6 6 FAST_RX_AFE_ADAPT 7 7 FAST_RX_DFE_ADAPT 8 8 FAST_SUP 9 9 FAST_TX_CMN_MODE 10 10 FAST_TX_RXDET 11 11 FAST_RX_PWRUP 12 12 FAST_RX_VCO_WAIT 13 13 FAST_RX_VCO_CAL 14 14 RESERVED_15_15 15 15 ixDPCSSYS_CR4_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP2 2 0x431d 2 0 4294967295 DFE_TAP2_ADPT_VAL 0 11 RESERVED_15_12 12 15 ixDPCSSYS_CR4_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP3 2 0x431e 2 0 4294967295 DFE_TAP3_ADPT_VAL 0 11 RESERVED_15_12 12 15 ixDPCSSYS_CR4_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP4 2 0x431f 2 0 4294967295 DFE_TAP4_ADPT_VAL 0 11 RESERVED_15_12 12 15 ixDPCSSYS_CR4_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP5 2 0x4320 2 0 4294967295 DFE_TAP5_ADPT_VAL 0 11 RESERVED_15_12 12 15 ixDPCSSYS_CR4_RAWAONLANE3_DIG_RX_SLICER_CTRL_EVEN 2 0x4321 2 0 4294967295 RX_ANA_SLICER_CTRL_E 0 3 RESERVED_15_4 4 15 ixDPCSSYS_CR4_RAWAONLANE3_DIG_RX_SLICER_CTRL_ODD 2 0x4322 2 0 4294967295 RX_ANA_SLICER_CTRL_O 0 3 RESERVED_15_4 4 15 ixDPCSSYS_CR4_RAWAONLANE3_DIG_LANE_CMNCAL_MPLL_STATUS 2 0x4323 3 0 4294967295 LANE_CMNCAL_MPLL_INIT 0 0 LANE_CMNCAL_MPLL_DONE 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR4_RAWAONLANE3_DIG_ADPT_CTL_0 2 0x4324 1 0 4294967295 VAL 0 15 ixDPCSSYS_CR4_RAWAONLANE3_DIG_ADPT_CTL_1 2 0x4325 1 0 4294967295 VAL 0 15 ixDPCSSYS_CR4_RAWAONLANE3_DIG_ADPT_CTL_2 2 0x4326 1 0 4294967295 VAL 0 15 ixDPCSSYS_CR4_RAWAONLANE3_DIG_ADPT_CTL_3 2 0x4327 1 0 4294967295 VAL 0 15 ixDPCSSYS_CR4_RAWAONLANE3_DIG_ADPT_CTL_4 2 0x4328 1 0 4294967295 VAL 0 15 ixDPCSSYS_CR4_RAWAONLANE3_DIG_ADPT_CTL_5 2 0x4329 1 0 4294967295 VAL 0 15 ixDPCSSYS_CR4_RAWAONLANE3_DIG_ADPT_CTL_6 2 0x432a 1 0 4294967295 VAL 0 15 ixDPCSSYS_CR4_RAWAONLANE3_DIG_ADPT_CTL_7 2 0x432b 1 0 4294967295 VAL 0 15 ixDPCSSYS_CR4_RAWAONLANE3_DIG_MPLL_DISABLE 2 0x432c 3 0 4294967295 LANE_MPLLA_DISABLE 0 0 LANE_MPLLB_DISABLE 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR4_RAWAONLANE3_DIG_FAST_FLAGS_2 2 0x432d 16 0 4294967295 FAST_RX_CONT_CAL_ADAPT 0 0 FAST_RX_CONT_ADAPT 1 1 FAST_RX_CONT_DATA_CAL 2 2 FAST_RX_CONT_PHASE_CAL 3 3 FAST_RX_CONT_AFE_CAL 4 4 FAST_TX_CONT_DCC_CAL 5 5 FAST_RX_CONT_DCC_CAL 6 6 FAST_RX_CONT_VPHUD_CAL 7 7 FAST_RX_CONT_VREF_CAL 8 8 FAST_TX_DCC_CAL 9 9 FAST_RX_DCC_CAL 10 10 FAST_RX_VPHUD_CAL 11 11 FAST_RX_VREF_CAL 12 12 SKIP_TX_RTUNE_CAL 13 13 FAST_RX_SIGDET_CAL 14 14 RESERVED_15_15 15 15 ixDPCSSYS_CR4_RAWAONLANE3_DIG_LANE_CMNCAL_RCAL_STATUS 2 0x432e 3 0 4294967295 LANE_CMNCAL_RCAL_INIT 0 0 LANE_CMNCAL_RCAL_DONE 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR4_RAWAONLANE3_DIG_TXRX_OVRD_IN 2 0x432f 5 0 4294967295 RX_DISABLE_OVRD_VAL 0 0 RX_DISABLE_OVRD_EN 1 1 TX_DISABLE_OVRD_VAL 2 2 TX_DISABLE_OVRD_EN 3 3 RESERVED_15_4 4 15 ixDPCSSYS_CR4_RAWAONLANE3_DIG_RX_LOS_MASK_CTL 2 0x4330 2 0 4294967295 RX_LOS_MASK_CNT 0 8 RESERVED_15_9 9 15 ixDPCSSYS_CR4_RAWAONLANE3_DIG_RX_SIGDET_FILT_CTRL 2 0x4331 5 0 4294967295 ISOLATE_SIGDET_HF 0 0 RX_SIGDEF_HF_FILT_OVR_DIS 1 1 RX_SIGDEF_HF_FILT_OVR 2 2 RX_SIGDET_LF_OUT_FILT_EN 3 3 RESERVED_15_4 4 15 ixDPCSSYS_CR4_RAWAONLANE3_DIG_STATS 2 0x4332 3 0 4294967295 RX_VREFGEN_MASTER 0 0 RX_PMA_SQ_OUT 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR4_RAWAONLANE3_DIG_RX_OVRD_OUT_1 2 0x4333 11 0 4294967295 RX_PMA_SQ_CTRL_TRESH_OVRD_VAL 0 2 RX_PMA_SQ_CTRL_TRESH_OVRD_EN 3 3 RX_PMA_SQ_CTRL_RESP_OVRD_VAL 4 5 RX_PMA_SQ_CTRL_RESP_OVRD_EN 6 6 RX_PMA_SQ_WEAKKEEP_OVRD_VAL 7 7 RX_PMA_SQ_WEAKKEEP_OVRD_EN 8 8 RX_PMA_SQ_INV_POLARITY_OVRD_VAL 9 9 RX_PMA_SQ_INV_POLARITY_OVRD_EN 10 10 RX_PMA_SQ_EN_OVRD_VAL 11 11 RX_PMA_SQ_EN_OVRD_EN 12 12 RESERVED_15_13 13 15 ixDPCSSYS_CR4_RAWAONLANE3_DIG_RX_OVRD_OUT_2 2 0x4334 9 0 4294967295 RX_PMA_VREFGEN_EN_OVRD_VAL 0 0 RX_PMA_VREFGEN_EN_OVRD_EN 1 1 RX_SQ_OUT_OVRD_VAL 2 2 RX_SQ_OUT_OVRD_EN 3 3 RX_PMA_TERM_ACDC_OVRD_VAL 4 4 RX_PMA_TERM_ACDC_OVRD_EN 5 5 RX_PMA_TERM_EN_OVRD_VAL 6 6 RX_PMA_TERM_EN_OVRD_EN 7 7 RESERVED_15_8 8 15 ixDPCSSYS_CR4_RAWAONLANE3_DIG_RX_OVRD_OUT_3 2 0x4335 7 0 4294967295 RX_PMA_SIGDET_LF_FILTER_EN_OVRD_VAL 0 0 RX_PMA_SIGDET_LF_FILTER_EN_OVRD_EN 1 1 RX_PMA_SIGDET_LF_EN_OVRD_VAL 2 2 RX_PMA_SIGDET_LF_EN_OVRD_EN 3 3 RX_PMA_SIGDET_HF_EN_OVRD_VAL 4 4 RX_PMA_SIGDET_HF_EN_OVRD_EN 5 5 RESERVED_15_6 6 15 ixDPCSSYS_CR4_RAWAONLANE3_DIG_RX_SIGDET_CAL 2 0x4336 4 0 4294967295 RX_PMA_SIGDET_LF_THRESHOLD 0 2 RX_PMA_SIGDET_HF_THRESHOLD 3 5 RX_PMA_SIGDET_CAL_EN 6 6 RESERVED_15_7 7 15 ixDPCSSYS_CR4_RAWAONLANE3_DIG_RX_SIGDET_HF_CODE 2 0x4337 2 0 4294967295 RX_PMA_SIGDET_HF_CAL_TUNE 0 5 RESERVED_15_6 6 15 ixDPCSSYS_CR4_RAWAONLANE3_DIG_RX_SIGDET_LF_CODE 2 0x4338 2 0 4294967295 RX_PMA_SIGDET_LF_CAL_TUNE 0 5 RESERVED_15_6 6 15 ixDPCSSYS_CR4_RAWAONLANE3_DIG_RX_VREFGEN_EN 2 0x4339 2 0 4294967295 PULL_UP 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR4_RAWAONLANE3_DIG_CAL_IOFF_CODE 2 0x433a 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR4_RAWAONLANE3_DIG_CAL_ICONST_CODE 2 0x433b 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR4_RAWAONLANE3_DIG_CAL_VREFGEN_CODE 2 0x433c 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR4_RAWAONLANE3_DIG_RX_DCC_CAL_ICM_CODE_0 2 0x433d 2 0 4294967295 RX_DCC_CAL_ICM_CODE 0 9 RESERVED_15_10 10 15 ixDPCSSYS_CR4_RAWAONLANE3_DIG_RX_DCC_CAL_IDF_CODE_0 2 0x433e 2 0 4294967295 RX_DCC_CAL_IDF_CODE 0 9 RESERVED_15_10 10 15 ixDPCSSYS_CR4_RAWAONLANE3_DIG_RX_DCC_CAL_QCM_CODE_0 2 0x433f 2 0 4294967295 RX_DCC_CAL_QCM_CODE 0 9 RESERVED_15_10 10 15 ixDPCSSYS_CR4_RAWAONLANE3_DIG_RX_DCC_CAL_QDF_CODE_0 2 0x4340 2 0 4294967295 RX_DCC_CAL_QDF_CODE 0 9 RESERVED_15_10 10 15 ixDPCSSYS_CR4_RAWAONLANE3_DIG_RX_DCC_CAL_ICM_CODE_1 2 0x4341 2 0 4294967295 RX_DCC_CAL_ICM_CODE 0 9 RESERVED_15_10 10 15 ixDPCSSYS_CR4_RAWAONLANE3_DIG_RX_DCC_CAL_IDF_CODE_1 2 0x4342 2 0 4294967295 RX_DCC_CAL_IDF_CODE 0 9 RESERVED_15_10 10 15 ixDPCSSYS_CR4_RAWAONLANE3_DIG_RX_DCC_CAL_QCM_CODE_1 2 0x4343 2 0 4294967295 RX_DCC_CAL_QCM_CODE 0 9 RESERVED_15_10 10 15 ixDPCSSYS_CR4_RAWAONLANE3_DIG_RX_DCC_CAL_QDF_CODE_1 2 0x4344 2 0 4294967295 RX_DCC_CAL_QDF_CODE 0 9 RESERVED_15_10 10 15 ixDPCSSYS_CR4_RAWAONLANE3_DIG_TX_DCC_BANK_ADDR 2 0x4345 1 0 4294967295 ADDR 0 15 ixDPCSSYS_CR4_RAWAONLANE3_DIG_TX_DCC_BANK_DATA 2 0x4346 1 0 4294967295 DATA 0 15 ixDPCSSYS_CR4_RAWAONLANE3_DIG_TX_DCC_CONT 2 0x4347 2 0 4294967295 EN 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR4_RAWAONLANE3_DIG_MPLL_BG_CTL 2 0x4348 3 0 4294967295 MPLL_STATE_WAIT 0 0 MPLL_STATE_DLY_EN 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR4_RAWAONLANE3_DIG_SIGDET_OUT_OVRD 2 0x4349 5 0 4294967295 RX_SIGDET_HF_OUT_OVRD_VAL 0 0 RX_SIGDET_HF_OUT_OVRD_EN 1 1 RX_SIGDET_LF_OUT_OVRD_VAL 2 2 RX_SIGDET_LF_OUT_OVRD_EN 3 3 RESERVED_15_4 4 15 ixDPCSSYS_CR4_RAWAONLANE3_DIG_SIGDET_OUT_IN 2 0x434a 3 0 4294967295 RX_SIGDET_HF_OUT_OVRD_VAL 0 0 RX_SIGDET_LF_OUT_OVRD_VAL 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR4_RAWAONLANE3_DIG_FW_MM_CONFIG 2 0x434b 1 0 4294967295 DATA 0 0 ixDPCSSYS_CR4_RAWAONLANE3_DIG_FW_ADPT_CONFIG 2 0x434c 2 0 4294967295 REF_LVL_ADPT 0 7 FW_CONFIG 8 15 ixDPCSSYS_CR4_RAWAONLANE3_DIG_FW_CALIB_CONFIG 2 0x434d 1 0 4294967295 FW_CALIB 0 15 ixDPCSSYS_CR4_RAWAONLANE3_DIG_LANE_XCVR_MODE_OVRD_IN 2 0x434e 3 0 4294967295 LANE_XCVR_MODE_OVRD_VAL 0 1 LANE_XCVR_MODE_OVRD_EN 2 2 RESERVED_15_3 3 15 ixDPCSSYS_CR4_RAWAONLANE3_DIG_LANE_XCVR_MODE_IN 2 0x434f 2 0 4294967295 LANE_XCVR_MODE 0 1 RESERVED_15_2 2 15 ixDPCSSYS_CR4_RAWAONLANE3_DIG_RX_SIGDET_CONFIG 2 0x4350 4 0 4294967295 RX_SIGDET_HF_FILTER_COUNTER 0 4 RX_SIGDET_LF_FILTER_COUNTER 5 9 RX_SIGDET_LF_HOLD 10 10 RESERVED_15_11 11 15 ixDPCSSYS_CR4_RAWAONLANE3_DIG_TX_DCC_CONFIG 2 0x4351 1 0 4294967295 DATA 0 0 ixDPCSSYS_CR4_RAWAONLANEX_DIG_AFE_ATT_IDAC_OFST 2 0x7000 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR4_RAWAONLANEX_DIG_AFE_CTLE_IDAC_OFST 2 0x7001 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR4_RAWAONLANEX_DIG_RX_ADPT_IQ 2 0x7002 2 0 4294967295 IQ_ADPT_VAL 0 6 RESERVED_15_7 7 15 ixDPCSSYS_CR4_RAWAONLANEX_DIG_RX_ADAPT_FOM 2 0x7003 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR4_RAWAONLANEX_DIG_DFE_SUMMER_ODD_IDAC_OFST 2 0x7004 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR4_RAWAONLANEX_DIG_DFE_PHASE_EVEN_VDAC_OFST 2 0x7005 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR4_RAWAONLANEX_DIG_DFE_PHASE_ODD_VDAC_OFST 2 0x7006 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR4_RAWAONLANEX_DIG_DFE_EVEN_REF_LVL 2 0x7007 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR4_RAWAONLANEX_DIG_DFE_ODD_REF_LVL 2 0x7008 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR4_RAWAONLANEX_DIG_RX_PHSADJ_LIN 2 0x7009 2 0 4294967295 DATA 0 0 RESERVED_15_5 5 15 ixDPCSSYS_CR4_RAWAONLANEX_DIG_RX_PHSADJ_MAP 2 0x700a 2 0 4294967295 DATA 0 0 RESERVED_15_5 5 15 ixDPCSSYS_CR4_RAWAONLANEX_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST 2 0x700b 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR4_RAWAONLANEX_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST 2 0x700c 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR4_RAWAONLANEX_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST 2 0x700d 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR4_RAWAONLANEX_DIG_DFE_DATA_ODD_LOW_VDAC_OFST 2 0x700e 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR4_RAWAONLANEX_DIG_DFE_BYPASS_EVEN_VDAC_OFST 2 0x700f 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR4_RAWAONLANEX_DIG_DFE_BYPASS_ODD_VDAC_OFST 2 0x7010 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR4_RAWAONLANEX_DIG_DFE_ERROR_EVEN_VDAC_OFST 2 0x7011 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR4_RAWAONLANEX_DIG_DFE_ERROR_ODD_VDAC_OFST 2 0x7012 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR4_RAWAONLANEX_DIG_RX_IQ_PHASE_ADJUST 2 0x7013 2 0 4294967295 DATA 0 0 RESERVED_15_7 7 15 ixDPCSSYS_CR4_RAWAONLANEX_DIG_MPLLA_COARSE_TUNE 2 0x7014 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR4_RAWAONLANEX_DIG_MPLLB_COARSE_TUNE 2 0x7015 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR4_RAWAONLANEX_DIG_INIT_PWRUP_DONE 2 0x7016 3 0 4294967295 DATA 0 0 PH2_PWRUP_DONE 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR4_RAWAONLANEX_DIG_RX_ADPT_ATT 2 0x7017 2 0 4294967295 ATT_ADPT_VAL 0 7 RESERVED_15_8 8 15 ixDPCSSYS_CR4_RAWAONLANEX_DIG_RX_ADPT_VGA 2 0x7018 2 0 4294967295 VGA_ADPT_VAL 0 9 RESERVED_15_10 10 15 ixDPCSSYS_CR4_RAWAONLANEX_DIG_RX_ADPT_CTLE 2 0x7019 3 0 4294967295 CTLE_BOOST_ADPT_VAL 0 9 CTLE_POLE_ADPT_VAL 10 12 RESERVED_15_13 13 15 ixDPCSSYS_CR4_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP1 2 0x701a 2 0 4294967295 DFE_TAP1_ADPT_VAL 0 12 RESERVED_15_13 13 15 ixDPCSSYS_CR4_RAWAONLANEX_DIG_RX_ADAPT_DONE 2 0x701b 2 0 4294967295 DATA 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR4_RAWAONLANEX_DIG_FAST_FLAGS 2 0x701c 16 0 4294967295 FAST_RX_STARTUP_CAL 0 0 FAST_RX_ADAPT 1 1 FAST_RX_AFE_CAL 2 2 FAST_RX_DFE_CAL 3 3 FAST_RX_BYPASS_CAL 4 4 FAST_RX_REFLVL_CAL 5 5 FAST_RX_IQ_CAL 6 6 FAST_RX_AFE_ADAPT 7 7 FAST_RX_DFE_ADAPT 8 8 FAST_SUP 9 9 FAST_TX_CMN_MODE 10 10 FAST_TX_RXDET 11 11 FAST_RX_PWRUP 12 12 FAST_RX_VCO_WAIT 13 13 FAST_RX_VCO_CAL 14 14 RESERVED_15_15 15 15 ixDPCSSYS_CR4_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP2 2 0x701d 2 0 4294967295 DFE_TAP2_ADPT_VAL 0 11 RESERVED_15_12 12 15 ixDPCSSYS_CR4_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP3 2 0x701e 2 0 4294967295 DFE_TAP3_ADPT_VAL 0 11 RESERVED_15_12 12 15 ixDPCSSYS_CR4_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP4 2 0x701f 2 0 4294967295 DFE_TAP4_ADPT_VAL 0 11 RESERVED_15_12 12 15 ixDPCSSYS_CR4_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP5 2 0x7020 2 0 4294967295 DFE_TAP5_ADPT_VAL 0 11 RESERVED_15_12 12 15 ixDPCSSYS_CR4_RAWAONLANEX_DIG_RX_SLICER_CTRL_EVEN 2 0x7021 2 0 4294967295 RX_ANA_SLICER_CTRL_E 0 3 RESERVED_15_4 4 15 ixDPCSSYS_CR4_RAWAONLANEX_DIG_RX_SLICER_CTRL_ODD 2 0x7022 2 0 4294967295 RX_ANA_SLICER_CTRL_O 0 3 RESERVED_15_4 4 15 ixDPCSSYS_CR4_RAWAONLANEX_DIG_LANE_CMNCAL_MPLL_STATUS 2 0x7023 3 0 4294967295 LANE_CMNCAL_MPLL_INIT 0 0 LANE_CMNCAL_MPLL_DONE 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR4_RAWAONLANEX_DIG_ADPT_CTL_0 2 0x7024 1 0 4294967295 VAL 0 15 ixDPCSSYS_CR4_RAWAONLANEX_DIG_ADPT_CTL_1 2 0x7025 1 0 4294967295 VAL 0 15 ixDPCSSYS_CR4_RAWAONLANEX_DIG_ADPT_CTL_2 2 0x7026 1 0 4294967295 VAL 0 15 ixDPCSSYS_CR4_RAWAONLANEX_DIG_ADPT_CTL_3 2 0x7027 1 0 4294967295 VAL 0 15 ixDPCSSYS_CR4_RAWAONLANEX_DIG_ADPT_CTL_4 2 0x7028 1 0 4294967295 VAL 0 15 ixDPCSSYS_CR4_RAWAONLANEX_DIG_ADPT_CTL_5 2 0x7029 1 0 4294967295 VAL 0 15 ixDPCSSYS_CR4_RAWAONLANEX_DIG_ADPT_CTL_6 2 0x702a 1 0 4294967295 VAL 0 15 ixDPCSSYS_CR4_RAWAONLANEX_DIG_ADPT_CTL_7 2 0x702b 1 0 4294967295 VAL 0 15 ixDPCSSYS_CR4_RAWAONLANEX_DIG_MPLL_DISABLE 2 0x702c 3 0 4294967295 LANE_MPLLA_DISABLE 0 0 LANE_MPLLB_DISABLE 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR4_RAWAONLANEX_DIG_FAST_FLAGS_2 2 0x702d 16 0 4294967295 FAST_RX_CONT_CAL_ADAPT 0 0 FAST_RX_CONT_ADAPT 1 1 FAST_RX_CONT_DATA_CAL 2 2 FAST_RX_CONT_PHASE_CAL 3 3 FAST_RX_CONT_AFE_CAL 4 4 FAST_TX_CONT_DCC_CAL 5 5 FAST_RX_CONT_DCC_CAL 6 6 FAST_RX_CONT_VPHUD_CAL 7 7 FAST_RX_CONT_VREF_CAL 8 8 FAST_TX_DCC_CAL 9 9 FAST_RX_DCC_CAL 10 10 FAST_RX_VPHUD_CAL 11 11 FAST_RX_VREF_CAL 12 12 SKIP_TX_RTUNE_CAL 13 13 FAST_RX_SIGDET_CAL 14 14 RESERVED_15_15 15 15 ixDPCSSYS_CR4_RAWAONLANEX_DIG_LANE_CMNCAL_RCAL_STATUS 2 0x702e 3 0 4294967295 LANE_CMNCAL_RCAL_INIT 0 0 LANE_CMNCAL_RCAL_DONE 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR4_RAWAONLANEX_DIG_TXRX_OVRD_IN 2 0x702f 5 0 4294967295 RX_DISABLE_OVRD_VAL 0 0 RX_DISABLE_OVRD_EN 1 1 TX_DISABLE_OVRD_VAL 2 2 TX_DISABLE_OVRD_EN 3 3 RESERVED_15_4 4 15 ixDPCSSYS_CR4_RAWAONLANEX_DIG_RX_LOS_MASK_CTL 2 0x7030 2 0 4294967295 RX_LOS_MASK_CNT 0 8 RESERVED_15_9 9 15 ixDPCSSYS_CR4_RAWAONLANEX_DIG_RX_SIGDET_FILT_CTRL 2 0x7031 5 0 4294967295 ISOLATE_SIGDET_HF 0 0 RX_SIGDEF_HF_FILT_OVR_DIS 1 1 RX_SIGDEF_HF_FILT_OVR 2 2 RX_SIGDET_LF_OUT_FILT_EN 3 3 RESERVED_15_4 4 15 ixDPCSSYS_CR4_RAWAONLANEX_DIG_STATS 2 0x7032 3 0 4294967295 RX_VREFGEN_MASTER 0 0 RX_PMA_SQ_OUT 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR4_RAWAONLANEX_DIG_RX_OVRD_OUT_1 2 0x7033 11 0 4294967295 RX_PMA_SQ_CTRL_TRESH_OVRD_VAL 0 2 RX_PMA_SQ_CTRL_TRESH_OVRD_EN 3 3 RX_PMA_SQ_CTRL_RESP_OVRD_VAL 4 5 RX_PMA_SQ_CTRL_RESP_OVRD_EN 6 6 RX_PMA_SQ_WEAKKEEP_OVRD_VAL 7 7 RX_PMA_SQ_WEAKKEEP_OVRD_EN 8 8 RX_PMA_SQ_INV_POLARITY_OVRD_VAL 9 9 RX_PMA_SQ_INV_POLARITY_OVRD_EN 10 10 RX_PMA_SQ_EN_OVRD_VAL 11 11 RX_PMA_SQ_EN_OVRD_EN 12 12 RESERVED_15_13 13 15 ixDPCSSYS_CR4_RAWAONLANEX_DIG_RX_OVRD_OUT_2 2 0x7034 9 0 4294967295 RX_PMA_VREFGEN_EN_OVRD_VAL 0 0 RX_PMA_VREFGEN_EN_OVRD_EN 1 1 RX_SQ_OUT_OVRD_VAL 2 2 RX_SQ_OUT_OVRD_EN 3 3 RX_PMA_TERM_ACDC_OVRD_VAL 4 4 RX_PMA_TERM_ACDC_OVRD_EN 5 5 RX_PMA_TERM_EN_OVRD_VAL 6 6 RX_PMA_TERM_EN_OVRD_EN 7 7 RESERVED_15_8 8 15 ixDPCSSYS_CR4_RAWAONLANEX_DIG_RX_OVRD_OUT_3 2 0x7035 7 0 4294967295 RX_PMA_SIGDET_LF_FILTER_EN_OVRD_VAL 0 0 RX_PMA_SIGDET_LF_FILTER_EN_OVRD_EN 1 1 RX_PMA_SIGDET_LF_EN_OVRD_VAL 2 2 RX_PMA_SIGDET_LF_EN_OVRD_EN 3 3 RX_PMA_SIGDET_HF_EN_OVRD_VAL 4 4 RX_PMA_SIGDET_HF_EN_OVRD_EN 5 5 RESERVED_15_6 6 15 ixDPCSSYS_CR4_RAWAONLANEX_DIG_RX_SIGDET_CAL 2 0x7036 4 0 4294967295 RX_PMA_SIGDET_LF_THRESHOLD 0 2 RX_PMA_SIGDET_HF_THRESHOLD 3 5 RX_PMA_SIGDET_CAL_EN 6 6 RESERVED_15_7 7 15 ixDPCSSYS_CR4_RAWAONLANEX_DIG_RX_SIGDET_HF_CODE 2 0x7037 2 0 4294967295 RX_PMA_SIGDET_HF_CAL_TUNE 0 5 RESERVED_15_6 6 15 ixDPCSSYS_CR4_RAWAONLANEX_DIG_RX_SIGDET_LF_CODE 2 0x7038 2 0 4294967295 RX_PMA_SIGDET_LF_CAL_TUNE 0 5 RESERVED_15_6 6 15 ixDPCSSYS_CR4_RAWAONLANEX_DIG_RX_VREFGEN_EN 2 0x7039 2 0 4294967295 PULL_UP 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR4_RAWAONLANEX_DIG_CAL_IOFF_CODE 2 0x703a 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR4_RAWAONLANEX_DIG_CAL_ICONST_CODE 2 0x703b 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR4_RAWAONLANEX_DIG_CAL_VREFGEN_CODE 2 0x703c 2 0 4294967295 DATA 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR4_RAWAONLANEX_DIG_RX_DCC_CAL_ICM_CODE_0 2 0x703d 2 0 4294967295 RX_DCC_CAL_ICM_CODE 0 9 RESERVED_15_10 10 15 ixDPCSSYS_CR4_RAWAONLANEX_DIG_RX_DCC_CAL_IDF_CODE_0 2 0x703e 2 0 4294967295 RX_DCC_CAL_IDF_CODE 0 9 RESERVED_15_10 10 15 ixDPCSSYS_CR4_RAWAONLANEX_DIG_RX_DCC_CAL_QCM_CODE_0 2 0x703f 2 0 4294967295 RX_DCC_CAL_QCM_CODE 0 9 RESERVED_15_10 10 15 ixDPCSSYS_CR4_RAWAONLANEX_DIG_RX_DCC_CAL_QDF_CODE_0 2 0x7040 2 0 4294967295 RX_DCC_CAL_QDF_CODE 0 9 RESERVED_15_10 10 15 ixDPCSSYS_CR4_RAWAONLANEX_DIG_RX_DCC_CAL_ICM_CODE_1 2 0x7041 2 0 4294967295 RX_DCC_CAL_ICM_CODE 0 9 RESERVED_15_10 10 15 ixDPCSSYS_CR4_RAWAONLANEX_DIG_RX_DCC_CAL_IDF_CODE_1 2 0x7042 2 0 4294967295 RX_DCC_CAL_IDF_CODE 0 9 RESERVED_15_10 10 15 ixDPCSSYS_CR4_RAWAONLANEX_DIG_RX_DCC_CAL_QCM_CODE_1 2 0x7043 2 0 4294967295 RX_DCC_CAL_QCM_CODE 0 9 RESERVED_15_10 10 15 ixDPCSSYS_CR4_RAWAONLANEX_DIG_RX_DCC_CAL_QDF_CODE_1 2 0x7044 2 0 4294967295 RX_DCC_CAL_QDF_CODE 0 9 RESERVED_15_10 10 15 ixDPCSSYS_CR4_RAWAONLANEX_DIG_TX_DCC_BANK_ADDR 2 0x7045 1 0 4294967295 ADDR 0 15 ixDPCSSYS_CR4_RAWAONLANEX_DIG_TX_DCC_BANK_DATA 2 0x7046 1 0 4294967295 DATA 0 15 ixDPCSSYS_CR4_RAWAONLANEX_DIG_TX_DCC_CONT 2 0x7047 2 0 4294967295 EN 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR4_RAWAONLANEX_DIG_MPLL_BG_CTL 2 0x7048 3 0 4294967295 MPLL_STATE_WAIT 0 0 MPLL_STATE_DLY_EN 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR4_RAWAONLANEX_DIG_SIGDET_OUT_OVRD 2 0x7049 5 0 4294967295 RX_SIGDET_HF_OUT_OVRD_VAL 0 0 RX_SIGDET_HF_OUT_OVRD_EN 1 1 RX_SIGDET_LF_OUT_OVRD_VAL 2 2 RX_SIGDET_LF_OUT_OVRD_EN 3 3 RESERVED_15_4 4 15 ixDPCSSYS_CR4_RAWAONLANEX_DIG_SIGDET_OUT_IN 2 0x704a 3 0 4294967295 RX_SIGDET_HF_OUT_OVRD_VAL 0 0 RX_SIGDET_LF_OUT_OVRD_VAL 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR4_RAWAONLANEX_DIG_FW_MM_CONFIG 2 0x704b 1 0 4294967295 DATA 0 0 ixDPCSSYS_CR4_RAWAONLANEX_DIG_FW_ADPT_CONFIG 2 0x704c 2 0 4294967295 REF_LVL_ADPT 0 7 FW_CONFIG 8 15 ixDPCSSYS_CR4_RAWAONLANEX_DIG_FW_CALIB_CONFIG 2 0x704d 1 0 4294967295 FW_CALIB 0 15 ixDPCSSYS_CR4_RAWAONLANEX_DIG_LANE_XCVR_MODE_OVRD_IN 2 0x704e 3 0 4294967295 LANE_XCVR_MODE_OVRD_VAL 0 1 LANE_XCVR_MODE_OVRD_EN 2 2 RESERVED_15_3 3 15 ixDPCSSYS_CR4_RAWAONLANEX_DIG_LANE_XCVR_MODE_IN 2 0x704f 2 0 4294967295 LANE_XCVR_MODE 0 1 RESERVED_15_2 2 15 ixDPCSSYS_CR4_RAWAONLANEX_DIG_RX_SIGDET_CONFIG 2 0x7050 4 0 4294967295 RX_SIGDET_HF_FILTER_COUNTER 0 4 RX_SIGDET_LF_FILTER_COUNTER 5 9 RX_SIGDET_LF_HOLD 10 10 RESERVED_15_11 11 15 ixDPCSSYS_CR4_RAWAONLANEX_DIG_TX_DCC_CONFIG 2 0x7051 1 0 4294967295 DATA 0 0 ixDPCSSYS_CR4_SUPX_DIG_IDCODE_LO 2 0x8000 1 0 4294967295 DATA 0 0 ixDPCSSYS_CR4_SUPX_DIG_IDCODE_HI 2 0x8001 1 0 4294967295 DATA 0 0 ixDPCSSYS_CR4_SUPX_DIG_REFCLK_OVRD_IN 2 0x8002 12 0 4294967295 REF_CLK_EN 0 0 REF_CLK_EN_OVRD_EN 1 1 REF_USE_PAD 2 2 REF_USE_PAD_OVRD_EN 3 3 REF_CLK_RANGE 4 8 REF_CLK_RANGE_OVRD_EN 9 9 BG_EN 10 10 BG_EN_OVRD_EN 11 11 HDMIMODE_EN 12 12 HDMIMODE_ENABLE_OVRD_EN 13 13 SUP_PRE_HP_OVRD 14 14 SUP_PRE_HP_OVRD_EN 15 15 ixDPCSSYS_CR4_SUPX_DIG_MPLLA_DIV_CLK_OVRD_IN 2 0x8003 4 0 4294967295 MPLLA_DIV_CLK_EN 0 0 MPLLA_DIV_MULTIPLIER 1 8 MPLLA_DIV_OVRD_EN 9 9 RESERVED_15_10 10 15 ixDPCSSYS_CR4_SUPX_DIG_MPLLA_HDMI_CLK_OVRD_IN 2 0x8004 4 0 4294967295 MPLLA_HDMI_PIXEL_CLK_DIV 0 1 MPLLA_HDMI_DIV 2 4 MPLLA_HDMI_OVRD_EN 5 5 RESERVED_15_6 6 15 ixDPCSSYS_CR4_SUPX_DIG_MPLLB_DIV_CLK_OVRD_IN 2 0x8005 4 0 4294967295 MPLLB_DIV_CLK_EN 0 0 MPLLB_DIV_MULTIPLIER 1 8 MPLLB_DIV_OVRD_EN 9 9 RESERVED_15_10 10 15 ixDPCSSYS_CR4_SUPX_DIG_MPLLB_HDMI_CLK_OVRD_IN 2 0x8006 4 0 4294967295 MPLLB_HDMI_PIXEL_CLK_DIV 0 1 MPLLB_HDMI_DIV 2 4 MPLLB_HDMI_OVRD_EN 5 5 RESERVED_15_6 6 15 ixDPCSSYS_CR4_SUPX_DIG_MPLLA_OVRD_IN_0 2 0x8007 12 0 4294967295 MPLLA_EN 0 0 MPLLA_DIV5_CLK_EN 1 1 MPLLA_TX_CLK_DIV 2 4 OVRD_EN 5 5 MPLLA_V2I 6 7 MPLLA_STANDBY 8 8 MPLLA_FREQ_VCO 9 10 MPLLA_CAL_FORCE 11 11 MPLL_FRACN_EN 12 12 MPLLA_CLK_SYNC_OVRD 13 13 MPLLA_CLK_SYNC_OVRD_EN 14 14 RESERVED_15_15 15 15 ixDPCSSYS_CR4_SUPX_DIG_MPLLA_OVRD_IN_1 2 0x8008 2 0 4294967295 MPLLA_MULTIPLIER 0 11 RESERVED_15_12 12 15 ixDPCSSYS_CR4_SUPX_DIG_MPLLA_OVRD_IN_2 2 0x8009 7 0 4294967295 MPLLA_SSC_EN 0 0 MPLLA_SSC_OVRD_EN 1 1 MPLLA_SSC_UP_SPREAD 2 2 MPLLA_PMIX_EN 3 3 MPLLA_WORD_DIV2_EN 4 4 MPLLA_FRACN_CFG_UPDATE_EN 5 5 RESERVED_15_6 6 15 ixDPCSSYS_CR4_SUPX_DIG_MPLLA_SSC_PEAK_1 2 0x800a 1 0 4294967295 MPLLA_SSC_PEAK_15_0 0 15 ixDPCSSYS_CR4_SUPX_DIG_MPLLA_SSC_PEAK_2 2 0x800b 2 0 4294967295 MPLLA_SSC_PEAK_19_16 0 3 RESERVED_15_4 4 15 ixDPCSSYS_CR4_SUPX_DIG_MPLLA_SSC_STEPSIZE_1 2 0x800c 1 0 4294967295 MPLLA_SSC_STEPSIZE_15_0 0 15 ixDPCSSYS_CR4_SUPX_DIG_MPLLA_SSC_STEPSIZE_2 2 0x800d 2 0 4294967295 MPLLA_SSC_STEPSIZE_20_16 0 4 RESERVED_15_5 5 15 ixDPCSSYS_CR4_SUPX_DIG_MPLLA_OVRD_IN_3 2 0x800e 1 0 4294967295 MPLLA_FRACN_QUOT 0 15 ixDPCSSYS_CR4_SUPX_DIG_MPLLA_OVRD_IN_4 2 0x800f 1 0 4294967295 MPLLA_FRACN_REM 0 15 ixDPCSSYS_CR4_SUPX_DIG_MPLLA_OVRD_IN_5 2 0x8010 1 0 4294967295 MPLLA_FRACN_DEN 0 15 ixDPCSSYS_CR4_SUPX_DIG_MPLLA_CP_OVRD_IN 2 0x8011 3 0 4294967295 MPLLA_CP_PROP 0 6 MPLLA_CP_INT 7 13 RESERVED_15_14 14 15 ixDPCSSYS_CR4_SUPX_DIG_MPLLA_CP_GS_OVRD_IN 2 0x8012 4 0 4294967295 MPLLA_CP_PROP_GS 0 6 MPLLA_CP_PROP_GS_OVR_EN 7 7 MPLLA_CP_INT_GS 8 14 MPLLA_CP_INT_GS_OVR_EN 15 15 ixDPCSSYS_CR4_SUPX_DIG_MPLLB_OVRD_IN_0 2 0x8013 12 0 4294967295 MPLLB_EN 0 0 MPLLB_DIV5_CLK_EN 1 1 MPLLB_TX_CLK_DIV 2 4 OVRD_EN 5 5 MPLLB_V2I 6 7 MPLLB_STANDBY 8 8 MPLLB_FREQ_VCO 9 10 MPLLB_CAL_FORCE 11 11 MPLL_FRACN_EN 12 12 MPLLB_CLK_SYNC_OVRD 13 13 MPLLB_CLK_SYNC_OVRD_EN 14 14 RESERVED_15_15 15 15 ixDPCSSYS_CR4_SUPX_DIG_MPLLB_OVRD_IN_1 2 0x8014 2 0 4294967295 MPLLB_MULTIPLIER 0 11 RESERVED_15_12 12 15 ixDPCSSYS_CR4_SUPX_DIG_MPLLB_OVRD_IN_2 2 0x8015 7 0 4294967295 MPLLB_SSC_EN 0 0 MPLLB_SSC_OVRD_EN 1 1 MPLLB_SSC_UP_SPREAD 2 2 MPLLB_PMIX_EN 3 3 MPLLB_WORD_DIV2_EN 4 4 MPLLB_FRACN_CFG_UPDATE_EN 5 5 RESERVED_15_6 6 15 ixDPCSSYS_CR4_SUPX_DIG_MPLLB_SSC_PEAK_1 2 0x8016 1 0 4294967295 MPLLB_SSC_PEAK_15_0 0 15 ixDPCSSYS_CR4_SUPX_DIG_MPLLB_SSC_PEAK_2 2 0x8017 2 0 4294967295 MPLLB_SSC_PEAK_19_16 0 3 RESERVED_15_4 4 15 ixDPCSSYS_CR4_SUPX_DIG_MPLLB_SSC_STEPSIZE_1 2 0x8018 1 0 4294967295 MPLLB_SSC_STEPSIZE_15_0 0 15 ixDPCSSYS_CR4_SUPX_DIG_MPLLB_SSC_STEPSIZE_2 2 0x8019 2 0 4294967295 MPLLB_SSC_STEPSIZE_20_16 0 4 RESERVED_15_5 5 15 ixDPCSSYS_CR4_SUPX_DIG_MPLLB_OVRD_IN_3 2 0x801a 1 0 4294967295 MPLLB_FRACN_QUOT 0 15 ixDPCSSYS_CR4_SUPX_DIG_MPLLB_OVRD_IN_4 2 0x801b 1 0 4294967295 MPLLB_FRACN_REM 0 15 ixDPCSSYS_CR4_SUPX_DIG_MPLLB_OVRD_IN_5 2 0x801c 1 0 4294967295 MPLLB_FRACN_DEN 0 15 ixDPCSSYS_CR4_SUPX_DIG_MPLLB_CP_OVRD_IN 2 0x801d 3 0 4294967295 MPLLB_CP_PROP 0 6 MPLLB_CP_INT 7 13 RESERVED_15_14 14 15 ixDPCSSYS_CR4_SUPX_DIG_MPLLB_CP_GS_OVRD_IN 2 0x801e 4 0 4294967295 MPLLB_CP_PROP_GS 0 6 MPLLB_CP_PROP_GS_OVR_EN 7 7 MPLLB_CP_INT_GS 8 14 MPLLB_CP_INT_GS_OVR_EN 15 15 ixDPCSSYS_CR4_SUPX_DIG_SUP_OVRD_IN 2 0x801f 8 0 4294967295 PRESCALER_OVRD_EN 0 0 RTUNE_REQ 1 1 RTUNE_OVRD_EN 2 2 TX_CAL_CODE 3 6 TX_CAL_CODE_EN 7 7 REF_ALT_CLK_LP_SEL_OVRD 8 8 REF_ALT_CLK_LP_SEL_OVRD_EN 9 9 RESERVED_15_10 10 15 ixDPCSSYS_CR4_SUPX_DIG_PRESCALER_OVRD_IN 2 0x8020 6 0 4294967295 DCO_RANGE 0 1 DCO_FINETUNE 2 7 REF_CLK_MPLLB_DIV 8 10 REF_CLK_MPLLA_DIV 11 13 REF_CLKDET_RESULT 14 14 REF_CLKDET_EN 15 15 ixDPCSSYS_CR4_SUPX_DIG_SUP_OVRD_OUT 2 0x8021 12 0 4294967295 RTUNE_ACK 0 0 RTUNE_ACK_OVRD_EN 1 1 MPLLA_STATE 2 2 MPLLA_STATE_OVRD_EN 3 3 MPLLB_STATE 4 4 MPLLB_STATE_OVRD_EN 5 5 BG_LANE_STATE 6 6 BG_LANE_STATE_OVRD_EN 7 7 BG_SUP_STATE 8 8 BG_SUP_STATE_OVRD_EN 9 9 REF_CLK_ACK 10 10 RESERVED_15_11 11 15 ixDPCSSYS_CR4_SUPX_DIG_LVL_OVRD_IN 2 0x8022 7 0 4294967295 RX_VREF_CTRL 0 2 RX_VREF_CTRL_EN 3 3 TX_VBOOST_LVL 4 6 TX_VBOOST_LVL_EN 7 7 SUP_RX_VCO_VREF_SEL_OVR 8 10 SUP_RX_VCO_VREF_SEL_OVR_EN 11 11 RESERVED_15_12 12 15 ixDPCSSYS_CR4_SUPX_DIG_MPLLA_ASIC_IN_0 2 0x8024 9 0 4294967295 MPLLA_EN 0 0 MPLLA_DIV5_CLK_EN 1 1 MPLLA_TX_CLK_DIV 2 4 MPLLA_V2I 5 6 MPLLA_STANDBY 7 7 MPLLA_FREQ_VCO 8 9 MPLLA_CAL_FORCE 10 10 MPLLA_FRACN_EN 11 11 RESERVED_15_12 12 15 ixDPCSSYS_CR4_SUPX_DIG_MPLLA_ASIC_IN_1 2 0x8025 2 0 4294967295 MPLLA_MULTIPLIER 0 11 RESERVED_15_12 12 15 ixDPCSSYS_CR4_SUPX_DIG_MPLLA_ASIC_IN_2 2 0x8026 7 0 4294967295 MPLLA_SSC_EN 0 0 MPLLA_SSC_UP_SPREAD 1 1 MPLLA_PMIX_EN 2 2 MPLLA_WORD_DIV2_EN 3 3 MPLLA_FRACN_CFG_UPDATE_EN 4 4 MPLLA_CLK_SYNC 5 5 RESERVED_15_6 6 15 ixDPCSSYS_CR4_SUPX_DIG_MPLLA_ASIC_IN_3 2 0x8027 1 0 4294967295 MPLLA_SSC_PEAK_15_0 0 15 ixDPCSSYS_CR4_SUPX_DIG_MPLLA_ASIC_IN_4 2 0x8028 2 0 4294967295 MPLLA_SSC_PEAK_19_16 0 3 RESERVED_15_4 4 15 ixDPCSSYS_CR4_SUPX_DIG_MPLLA_ASIC_IN_5 2 0x8029 1 0 4294967295 MPLLA_SSC_STEPSIZE_15_0 0 15 ixDPCSSYS_CR4_SUPX_DIG_MPLLA_ASIC_IN_6 2 0x802a 2 0 4294967295 MPLLA_SSC_STEPSIZE_20_16 0 3 RESERVED_15_4 4 15 ixDPCSSYS_CR4_SUPX_DIG_MPLLB_ASIC_IN_0 2 0x802b 9 0 4294967295 MPLLB_EN 0 0 MPLLB_DIV5_CLK_EN 1 1 MPLLB_TX_CLK_DIV 2 4 MPLLB_V2I 5 6 MPLLB_STANDBY 7 7 MPLLB_FREQ_VCO 8 9 MPLLB_CAL_FORCE 10 10 MPLLB_FRACN_EN 11 11 RESERVED_15_12 12 15 ixDPCSSYS_CR4_SUPX_DIG_MPLLB_ASIC_IN_1 2 0x802c 2 0 4294967295 MPLLB_MULTIPLIER 0 11 RESERVED_15_12 12 15 ixDPCSSYS_CR4_SUPX_DIG_MPLLB_ASIC_IN_2 2 0x802d 7 0 4294967295 MPLLB_SSC_EN 0 0 MPLLB_SSC_UP_SPREAD 1 1 MPLLB_PMIX_EN 2 2 MPLLB_WORD_DIV2_EN 3 3 MPLLB_FRACN_CFG_UPDATE_EN 4 4 MPLLB_CLK_SYNC 5 5 RESERVED_15_6 6 15 ixDPCSSYS_CR4_SUPX_DIG_MPLLB_ASIC_IN_3 2 0x802e 1 0 4294967295 MPLLB_SSC_PEAK_15_0 0 15 ixDPCSSYS_CR4_SUPX_DIG_MPLLB_ASIC_IN_4 2 0x802f 2 0 4294967295 MPLLB_SSC_PEAK_19_16 0 3 RESERVED_15_4 4 15 ixDPCSSYS_CR4_SUPX_DIG_MPLLB_ASIC_IN_5 2 0x8030 1 0 4294967295 MPLLB_SSC_STEPSIZE_15_0 0 15 ixDPCSSYS_CR4_SUPX_DIG_MPLLB_ASIC_IN_6 2 0x8031 2 0 4294967295 MPLLB_SSC_STEPSIZE_20_16 0 3 RESERVED_15_4 4 15 ixDPCSSYS_CR4_SUPX_DIG_MPLLA_DIV_CLK_ASIC_IN 2 0x8032 3 0 4294967295 MPLLA_DIV_CLK_EN 0 0 MPLLA_DIV_MULTIPLIER 1 8 RESERVED_15_9 9 15 ixDPCSSYS_CR4_SUPX_DIG_MPLLA_HDMI_CLK_ASIC_IN 2 0x8033 3 0 4294967295 MPLLA_HDMI_PIXEL_CLK_DIV 0 1 MPLLA_HDMI_DIV 2 4 RESERVED_15_5 5 15 ixDPCSSYS_CR4_SUPX_DIG_MPLLB_DIV_CLK_ASIC_IN 2 0x8034 3 0 4294967295 MPLLB_DIV_CLK_EN 0 0 MPLLB_DIV_MULTIPLIER 1 8 RESERVED_15_9 9 15 ixDPCSSYS_CR4_SUPX_DIG_MPLLB_HDMI_CLK_ASIC_IN 2 0x8035 3 0 4294967295 MPLLB_HDMI_PIXEL_CLK_DIV 0 1 MPLLB_HDMI_DIV 2 4 RESERVED_15_5 5 15 ixDPCSSYS_CR4_SUPX_DIG_ASIC_IN 2 0x8036 12 0 4294967295 PHY_RESET 0 0 REF_CLK_EN 1 1 REF_USE_PAD 2 2 TEST_BURNIN 3 3 TEST_POWERDOWN 4 4 RTUNE_REQ 5 5 RTUNE_ACK 6 6 MPLLA_STATE 7 7 MPLLB_STATE 8 8 TEST_TX_REF_CLK_EN 9 9 REF_ALT_CLK_LP_SEL 10 10 RESERVED_15_11 11 15 ixDPCSSYS_CR4_SUPX_DIG_LVL_ASIC_IN 2 0x8037 4 0 4294967295 RX_VREF_CTRL 0 2 TX_VBOOST_LVL 3 5 SUP_RX_VCO_VREF_SEL 6 8 RESERVED_15_9 9 15 ixDPCSSYS_CR4_SUPX_DIG_BANDGAP_ASIC_IN 2 0x8038 2 0 4294967295 BG_EN 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR4_SUPX_DIG_MPLLA_CP_ASIC_IN 2 0x8039 3 0 4294967295 MPLLA_CP_PROP 0 6 MPLLA_CP_INT 7 13 RESERVED_15_14 14 15 ixDPCSSYS_CR4_SUPX_DIG_MPLLA_CP_GS_ASIC_IN 2 0x803a 3 0 4294967295 MPLLA_CP_PROP_GS 0 6 MPLLA_CP_INT_GS 7 13 RESERVED_15_14 14 15 ixDPCSSYS_CR4_SUPX_DIG_MPLLB_CP_ASIC_IN 2 0x803b 3 0 4294967295 MPLLB_CP_PROP 0 6 MPLLB_CP_INT 7 13 RESERVED_15_14 14 15 ixDPCSSYS_CR4_SUPX_DIG_MPLLB_CP_GS_ASIC_IN 2 0x803c 3 0 4294967295 MPLLB_CP_PROP_GS 0 6 MPLLB_CP_INT_GS 7 13 RESERVED_15_14 14 15 ixDPCSSYS_CR4_SUPX_ANA_PRESCALER_CTRL 2 0x8040 7 0 4294967295 PSCALER_ATB_SELECT 0 0 PSCALER_MEAS_VREG 0 0 PSCALER_OVRD_FAST_START 0 0 PSCALER_FAST_START_REG 0 0 PSCALER_VREG_BOOST 0 0 PSCALER_HYST_REF 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR4_SUPX_ANA_RTUNE_CTRL 2 0x8041 9 0 4294967295 RT_ATB 0 0 RT_SEL_ATBF 0 0 RT_SEL_ATBP 0 0 RT_VP4O8_EN 0 0 RT_DAC_CHOP 0 0 RT_DAC_MODE 0 0 RT_EN_FRCON 0 0 PSCALER_VREG_FB_DIV_CTRL 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR4_SUPX_ANA_BG1 2 0x8042 6 0 4294967295 SUP_SEL_VBG_VREF 0 0 SUP_SEL_VPHUD_VREF 0 0 NC4 4 4 SUP_SEL_VPLL_REF 0 0 RT_VREF_SEL 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR4_SUPX_ANA_BG2 2 0x8043 9 0 4294967295 SUP_BYPASS_BG 0 0 SUP_CHOP_EN 0 0 SUP_TEMP_MEAS 0 0 VPHUD_SELREF 0 0 ATB_EXT_MEAS_EN 0 0 RT_TX_OFFSET_EN 0 0 SUP_SEL_TX_SWING_VREF 0 0 PSCALER_VREG_OVERRIDE_RING_CTRL 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR4_SUPX_ANA_SWITCH_PWR_MEAS 2 0x8044 3 0 4294967295 SUP_ATB_SW 0 0 SUP_TIE 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR4_SUPX_ANA_BG3 2 0x8045 4 0 4294967295 SUP_SEL_RX_VCO_TC_VREF 0 0 SUP_SEL_RX_CAL_VREF 0 0 NC7_4 4 7 RESERVED_15_8 8 15 ixDPCSSYS_CR4_SUPX_ANA_MPLLA_MISC1 2 0x8046 7 0 4294967295 OVRD_GEAR_RC_FILT 0 0 OVRD_TEST_RC_FILT 0 0 TEST_VREG_DIV 0 0 VBG_EN 0 0 COUNT_SEL_LOCK 0 0 PHASE_SEL_LOCK 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR4_SUPX_ANA_MPLLA_MISC2 2 0x8047 8 0 4294967295 OVRD_PR_BYPASS 0 0 PR_BYPASS 0 0 OVRD_GEARSHIFT 0 0 GEARSHIFT_REG 0 0 TEST_LOCK_GEAR 0 0 EN_CAL_SPO 0 0 TEST_BOOST 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR4_SUPX_ANA_MPLLA_OVRD 2 0x8048 9 0 4294967295 OVRD_ENABLE 0 0 ENABLE_REG 0 0 OVRD_CAL 0 0 CAL_REG 0 0 OVRD_FB_CLK_EN 0 0 FB_CLK_EN_REG 0 0 OVRD_RESET 0 0 RESET_REG 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR4_SUPX_ANA_MPLLA_ATB1 2 0x8049 3 0 4294967295 MEAS_IV_WRAP 0 0 ATB_SELECT 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR4_SUPX_ANA_MPLLA_ATB2 2 0x804a 2 0 4294967295 MEAS_IV_PLL 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR4_SUPX_ANA_MPLLA_ATB3 2 0x804b 3 0 4294967295 MEAS_IV_BIAS 0 0 CTR_UPLL_TUNNING 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR4_SUPX_ANA_MPLLA_CTR1 2 0x804c 5 0 4294967295 CTR_ICP_INT 0 0 CTR_VREF_EN 0 0 CTR_VREF_VMARG 0 0 CTR_CP_PLL 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR4_SUPX_ANA_MPLLA_CTR2 2 0x804d 2 0 4294967295 CTR_REGS_PLL 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR4_SUPX_ANA_MPLLA_CTR3 2 0x804e 4 0 4294967295 CTR_REGS_CP_PLL 0 0 CTR_SPO_PLL 0 0 CTR_VINT_CAP 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR4_SUPX_ANA_MPLLA_CTR4 2 0x804f 7 0 4294967295 CTR_CP_8X 0 0 CTR_FIL_REG 0 0 CTR_CP_PROP_REF 0 0 CTR_DOUBLER_GAIN 0 0 CTR_TEST_CASC 0 0 CTR_RC_FITER 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR4_SUPX_ANA_MPLLA_CTR5 2 0x8050 8 0 4294967295 CTR_STANDBY_MODE 0 0 CTR_LEG_SR_CON 0 0 CTR_VREG_RING_OVERRIDE 0 0 CTR_SPO_SPEED_OVERRIDE 0 0 CTR_BYPASS_LOCK_SPO_CAL 0 0 CTR_LOCK_SPO_CAL 0 0 CTR_UPLL_RESERVED 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR4_SUPX_ANA_MPLLA_RESERVED1 2 0x8051 8 0 4294967295 CTR_REF_FBK_BYPASS 0 0 CTR_BYPASS_TX 0 0 CTR_VREG_CLK_BYPASS 0 0 CTR_VREG_CLK_PMIX_BYPASS 0 0 CTR_VREG_RIGHT_BYPASS 0 0 CTR_VREG_LEFT_BYPASS 0 0 CTR_LEFT_RIGHT_GAIN 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR4_SUPX_ANA_MPLLA_RESERVED2 2 0x8052 5 0 4294967295 CTR_DLL_MODE_90 0 0 CTR_DLL_RESERVED 0 0 CTR_DIV24_DSQ_ENZ 0 0 CTR_DIV4 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR4_SUPX_ANA_MPLLB_MISC1 2 0x8053 7 0 4294967295 OVRD_GEAR_RC_FILT 0 0 OVRD_TEST_RC_FILT 0 0 TEST_VREG_DIV 0 0 VBG_EN 0 0 COUNT_SEL_LOCK 0 0 PHASE_SEL_LOCK 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR4_SUPX_ANA_MPLLB_MISC2 2 0x8054 8 0 4294967295 OVRD_PR_BYPASS 0 0 PR_BYPASS 0 0 OVRD_GEARSHIFT 0 0 GEARSHIFT_REG 0 0 TEST_LOCK_GEAR 0 0 EN_CAL_SPO 0 0 TEST_BOOST 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR4_SUPX_ANA_MPLLB_OVRD 2 0x8055 9 0 4294967295 OVRD_ENABLE 0 0 ENABLE_REG 0 0 OVRD_CAL 0 0 CAL_REG 0 0 OVRD_FB_CLK_EN 0 0 FB_CLK_EN_REG 0 0 OVRD_RESET 0 0 RESET_REG 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR4_SUPX_ANA_MPLLB_ATB1 2 0x8056 3 0 4294967295 MEAS_IV_WRAP 0 0 ATB_SELECT 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR4_SUPX_ANA_MPLLB_ATB2 2 0x8057 2 0 4294967295 MEAS_IV_PLL 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR4_SUPX_ANA_MPLLB_ATB3 2 0x8058 3 0 4294967295 MEAS_IV_BIAS 0 0 CTR_UPLL_TUNNING 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR4_SUPX_ANA_MPLLB_CTR1 2 0x8059 5 0 4294967295 CTR_ICP_INT 0 0 CTR_VREF_EN 0 0 CTR_VREF_VMARG 0 0 CTR_CP_PLL 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR4_SUPX_ANA_MPLLB_CTR2 2 0x805a 2 0 4294967295 CTR_REGS_PLL 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR4_SUPX_ANA_MPLLB_CTR3 2 0x805b 4 0 4294967295 CTR_REGS_CP_PLL 0 0 CTR_SPO_PLL 0 0 CTR_VINT_CAP 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR4_SUPX_ANA_MPLLB_CTR4 2 0x805c 7 0 4294967295 CTR_CP_8X 0 0 CTR_FIL_REG 0 0 CTR_CP_PROP_REF 0 0 CTR_DOUBLER_GAIN 0 0 CTR_TEST_CASC 0 0 CTR_RC_FITER 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR4_SUPX_ANA_MPLLB_CTR5 2 0x805d 8 0 4294967295 CTR_STANDBY_MODE 0 0 CTR_LEG_SR_CON 0 0 CTR_VREG_RING_OVERRIDE 0 0 CTR_SPO_SPEED_OVERRIDE 0 0 CTR_BYPASS_LOCK_SPO_CAL 0 0 CTR_LOCK_SPO_CAL 0 0 CTR_UPLL_RESERVED 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR4_SUPX_ANA_MPLLB_RESERVED1 2 0x805e 8 0 4294967295 CTR_REF_FBK_BYPASS 0 0 CTR_BYPASS_TX 0 0 CTR_VREG_CLK_BYPASS 0 0 CTR_VREG_CLK_PMIX_BYPASS 0 0 CTR_VREG_RIGHT_BYPASS 0 0 CTR_VREG_LEFT_BYPASS 0 0 CTR_LEFT_RIGHT_GAIN 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR4_SUPX_ANA_MPLLB_RESERVED2 2 0x805f 5 0 4294967295 CTR_DLL_MODE_90 0 0 CTR_DLL_RESERVED 0 0 CTR_DIV24_DSQ_ENZ 0 0 CTR_DIV4 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR4_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD 2 0x8061 8 0 4294967295 OVRD_SEL 0 0 MPLL_FBDIGCLK_EN 1 1 MPLL_PCLK_EN 2 2 FAST_MPLL_PWRUP 3 3 FAST_MPLL_LOCK 4 4 DTB_SEL 5 9 DIV10_EN 10 10 RESERVED 11 15 ixDPCSSYS_CR4_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT 2 0x8062 11 0 4294967295 FSM_STATE 0 3 MPLL_R_LANES 4 4 MPLL_L_LANES 5 5 MPLL_PCLK_EN 6 6 MPLL_OUTPUT_EN 7 7 MPLL_FBCLK_EN 8 8 MPLL_CAL 9 9 MPLL_RST 10 10 MPLL_ANA_EN 11 11 MPLL_LOCK 12 12 RESERVED_15_13 13 15 ixDPCSSYS_CR4_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE 2 0x8063 3 0 4294967295 MAX_RANGE 0 4 DAC_IN 5 9 RESERVED_15_10 10 15 ixDPCSSYS_CR4_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_LOCK 2 0x8064 3 0 4294967295 LOCK_TIME 0 7 STABLE_TIME 8 13 RESERVED_15_14 14 15 ixDPCSSYS_CR4_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS 2 0x8065 2 0 4294967295 GEARSHIFT_TIME 0 7 PRESET_TIME 8 15 ixDPCSSYS_CR4_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE 2 0x8066 3 0 4294967295 PWRDN_WAIT_TIME 0 5 PCLK_EN_TIME 6 11 RESERVED_15_12 12 15 ixDPCSSYS_CR4_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2 2 0x8067 3 0 4294967295 PCLK_DIS_TIME 0 5 PWRDN_TIME 6 11 RESERVED_15_12 12 15 ixDPCSSYS_CR4_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_CAL 2 0x8068 3 0 4294967295 MPLL_CAL 0 0 MPLL_CAL_OVRD_EN 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR4_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT 2 0x8069 2 0 4294967295 MPLL_ANA_DAC_OUT 0 4 RESERVED_15_5 5 15 ixDPCSSYS_CR4_SUPX_DIG_MPLLA_SSC_GEN_SPREAD_TYPE 2 0x806b 3 0 4294967295 SPREAD_TYPE 0 1 OVR_EN 2 2 RESERVED_15_3 3 15 ixDPCSSYS_CR4_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD 2 0x806d 8 0 4294967295 OVRD_SEL 0 0 MPLL_FBDIGCLK_EN 1 1 MPLL_PCLK_EN 2 2 FAST_MPLL_PWRUP 3 3 FAST_MPLL_LOCK 4 4 DTB_SEL 5 9 DIV10_EN 10 10 RESERVED 11 15 ixDPCSSYS_CR4_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT 2 0x806e 11 0 4294967295 FSM_STATE 0 3 MPLL_R_LANES 4 4 MPLL_L_LANES 5 5 MPLL_PCLK_EN 6 6 MPLL_OUTPUT_EN 7 7 MPLL_FBCLK_EN 8 8 MPLL_CAL 9 9 MPLL_RST 10 10 MPLL_ANA_EN 11 11 MPLL_LOCK 12 12 RESERVED_15_13 13 15 ixDPCSSYS_CR4_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE 2 0x806f 3 0 4294967295 MAX_RANGE 0 4 DAC_IN 5 9 RESERVED_15_10 10 15 ixDPCSSYS_CR4_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_LOCK 2 0x8070 3 0 4294967295 LOCK_TIME 0 7 STABLE_TIME 8 13 RESERVED_15_14 14 15 ixDPCSSYS_CR4_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS 2 0x8071 2 0 4294967295 GEARSHIFT_TIME 0 7 PRESET_TIME 8 15 ixDPCSSYS_CR4_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE 2 0x8072 3 0 4294967295 PWRDN_WAIT_TIME 0 5 PCLK_EN_TIME 6 11 RESERVED_15_12 12 15 ixDPCSSYS_CR4_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2 2 0x8073 3 0 4294967295 PCLK_DIS_TIME 0 5 PWRDN_TIME 6 11 RESERVED_15_12 12 15 ixDPCSSYS_CR4_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_CAL 2 0x8074 3 0 4294967295 MPLL_CAL 0 0 MPLL_CAL_OVRD_EN 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR4_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT 2 0x8075 2 0 4294967295 MPLL_ANA_DAC_OUT 0 4 RESERVED_15_5 5 15 ixDPCSSYS_CR4_SUPX_DIG_MPLLB_SSC_GEN_SPREAD_TYPE 2 0x8077 3 0 4294967295 SPREAD_TYPE 0 1 OVR_EN 2 2 RESERVED_15_3 3 15 ixDPCSSYS_CR4_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_0 2 0x8078 3 0 4294967295 BG_SUP_EN_TIME 0 8 FAST_BG_WAIT 9 9 RESERVED_15_10 10 15 ixDPCSSYS_CR4_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_1 2 0x8079 2 0 4294967295 BG_LANE_EN_TIME 0 8 RESERVED_15_9 9 15 ixDPCSSYS_CR4_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_2 2 0x807a 3 0 4294967295 BG_KICK_START_EN_TIME 0 7 BG_SUP_STATE_UPD_EN 8 8 RESERVED_15_9 9 15 ixDPCSSYS_CR4_SUPX_DIG_CLK_RST_REF_PWRUP_TIME_0 2 0x807b 3 0 4294967295 REF_VREG_FAST_START_TIME 0 4 FAST_REF_WAIT 5 5 RESERVED_15_6 6 15 ixDPCSSYS_CR4_SUPX_DIG_CLK_RST_REF_VPHUD 2 0x807c 3 0 4294967295 SUP_ANA_VPHUD_SELVPH_I 0 0 SUP_ANA_VPHUD_EN_I 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR4_SUPX_DIG_RTUNE_CONFIG 2 0x8081 5 0 4294967295 RX_CAL_EN 0 0 FAST_RTUNE 1 1 TX_CAL_EN 2 2 SUP_ANA_TERM_CTRL 3 5 RESERVED_15_6 6 15 ixDPCSSYS_CR4_SUPX_DIG_RTUNE_STAT 2 0x8082 3 0 4294967295 STAT 0 9 DTB_RTUNE 10 11 RESERVED_15_12 12 15 ixDPCSSYS_CR4_SUPX_DIG_RTUNE_RX_SET_VAL 2 0x8083 2 0 4294967295 RX_SET_VAL 0 5 RESERVED_15_6 6 15 ixDPCSSYS_CR4_SUPX_DIG_RTUNE_TXDN_SET_VAL 2 0x8084 2 0 4294967295 TXDN_SET_VAL 0 9 RESERVED_15_10 10 15 ixDPCSSYS_CR4_SUPX_DIG_RTUNE_TXUP_SET_VAL 2 0x8085 2 0 4294967295 TXUP_SET_VAL 0 9 RESERVED_15_10 10 15 ixDPCSSYS_CR4_SUPX_DIG_RTUNE_RX_STAT 2 0x8086 2 0 4294967295 RX_STAT 0 5 RESERVED_15_6 6 15 ixDPCSSYS_CR4_SUPX_DIG_RTUNE_TXDN_STAT 2 0x8087 2 0 4294967295 TXDN_STAT 0 9 RESERVED_15_10 10 15 ixDPCSSYS_CR4_SUPX_DIG_RTUNE_TXUP_STAT 2 0x8088 2 0 4294967295 TXUP_STAT 0 9 RESERVED_15_10 10 15 ixDPCSSYS_CR4_SUPX_DIG_RTUNE_CONFIG_CNT0 2 0x8089 4 0 4294967295 RT_RESULT_TIME 0 3 RT_EVAL_TIME 4 7 RT_RST_TIME 8 11 RT_ACK_TIME 12 15 ixDPCSSYS_CR4_SUPX_DIG_RTUNE_CONFIG_CNT1 2 0x808a 3 0 4294967295 RT_TXDN_SETTLE_TIME 0 3 RT_PWRUP_TIME 4 8 RESERVED_15_9 9 15 ixDPCSSYS_CR4_SUPX_DIG_RTUNE_TX_CAL_CODE 2 0x808b 2 0 4294967295 VALUE 0 3 RESERVED_15_4 4 15 ixDPCSSYS_CR4_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0 2 0x808c 16 0 4294967295 MPLLA_WORD_CLK_EN 0 0 MPLLA_HDMI_CLK_EN 1 1 MPLLA_DIV_CLK_EN 2 2 MPLLA_OUTPUT_EN 3 3 MPLLA_CLK_EN_OVRD_EN 4 4 MPLLA_OUTPUT_L_EN 5 5 MPLLA_OUTPUT_R_EN 6 6 MPLLA_ANA_EN 7 7 MPLLA_RST 8 8 MPLLA_CAL 9 9 MPLLA_DIV5_CLK_EN 10 10 MPLLA_DIV10_CLK_EN 11 11 MPLLA_FBCLK_EN 12 12 MPLLA_GEARSHIFT_EN 13 13 MPLLA_STANDBY 14 14 OVRD_SEL 15 15 ixDPCSSYS_CR4_SUPX_DIG_ANA_MPLLA_OVRD_OUT_1 2 0x808d 2 0 4294967295 MPLLA_ANA_INT 0 9 RESERVED_15_10 10 15 ixDPCSSYS_CR4_SUPX_DIG_ANA_MPLLA_OVRD_OUT_2 2 0x808e 3 0 4294967295 MPLLA_CP_PROP 0 6 MPLLA_CP_INT 7 13 RESERVED_15_14 14 15 ixDPCSSYS_CR4_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0 2 0x808f 16 0 4294967295 MPLLB_WORD_CLK_EN 0 0 MPLLB_HDMI_CLK_EN 1 1 MPLLB_DIV_CLK_EN 2 2 MPLLB_OUTPUT_EN 3 3 MPLLB_CLK_EN_OVRD_EN 4 4 MPLLB_OUTPUT_L_EN 5 5 MPLLB_OUTPUT_R_EN 6 6 MPLLB_ANA_EN 7 7 MPLLB_RST 8 8 MPLLB_CAL 9 9 MPLLB_DIV5_CLK_EN 10 10 MPLLB_DIV10_CLK_EN 11 11 MPLLB_FBCLK_EN 12 12 MPLLB_GEARSHIFT_EN 13 13 MPLLB_STANDBY 14 14 OVRD_SEL 15 15 ixDPCSSYS_CR4_SUPX_DIG_ANA_MPLLB_OVRD_OUT_1 2 0x8090 2 0 4294967295 MPLLB_ANA_INT 0 9 RESERVED_15_10 10 15 ixDPCSSYS_CR4_SUPX_DIG_ANA_MPLLB_OVRD_OUT_2 2 0x8091 3 0 4294967295 MPLLB_CP_PROP 0 6 MPLLB_CP_INT 7 13 RESERVED_15_14 14 15 ixDPCSSYS_CR4_SUPX_DIG_ANA_RTUNE_OVRD_OUT 2 0x8092 6 0 4294967295 RTUNE_COMP_RST 0 0 RTUNE_MODE 1 2 RTUNE_EN 3 3 RTUNE_VALUE 4 13 RTUNE_OVRD_EN 14 14 RESERVED_15_15 15 15 ixDPCSSYS_CR4_SUPX_DIG_ANA_STAT 2 0x8093 3 0 4294967295 RT_ANA_COMP_RESULT 0 0 REF_ANA_CLKDET_RESULT 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR4_SUPX_DIG_ANA_BG_OVRD_OUT 2 0x8094 11 0 4294967295 BG_EN 0 0 BG_FAST_START 1 1 BG_KICK_START 2 2 BG_OVRD_EN 3 3 ANA_ASYNC_RST 4 4 ANA_ASYNC_RST_OVRD_EN 5 5 REF_VREG_FAST_START 6 6 REF_VREG_FAST_START_OVRD_EN 7 7 REF_VREG_REF_SEL 8 9 REF_VREG_REF_SEL_OVRD_EN 10 10 RESERVED_15_11 11 15 ixDPCSSYS_CR4_SUPX_DIG_ANA_MPLLA_PMIX_OVRD_OUT 2 0x8095 5 0 4294967295 MPLLA_PMIX_SEL 0 5 MPLLA_PMIX_EN 6 6 MPLLA_PMIX_SEL_OVRD_EN 7 7 MPLLA_PMIX_EN_OVRD_EN 8 8 RESERVED_15_9 9 15 ixDPCSSYS_CR4_SUPX_DIG_ANA_MPLLB_PMIX_OVRD_OUT 2 0x8096 5 0 4294967295 MPLLB_PMIX_SEL 0 5 MPLLB_PMIX_EN 6 6 MPLLB_PMIX_SEL_OVRD_EN 7 7 MPLLB_PMIX_EN_OVRD_EN 8 8 RESERVED_15_9 9 15 ixDPCSSYS_CR4_LANEX_DIG_ASIC_LANE_OVRD_IN 2 0x9000 5 0 4294967295 LANE_TX2RX_SER_LB 0 0 LANE_RX2TX_PAR_LB 1 1 EN 2 2 RX_ACJTAG_EN 3 3 RESERVED_15_4 4 15 ixDPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_0 2 0x9001 12 0 4294967295 REQ 0 0 REQ_OVRD_EN 1 1 PSTATE 2 3 PSTATE_OVRD_EN 4 4 RATE 5 7 RATE_OVRD_EN 8 8 WIDTH 9 10 WIDTH_OVRD_EN 11 11 MPLLB_SEL 12 12 MPLLB_SEL_OVRD_EN 13 13 DATA_EN 14 14 DATA_EN_OVRD_EN 15 15 ixDPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_1 2 0x9002 11 0 4294967295 NYQUIST_DATA 0 0 DISABLE 1 1 BEACON_EN 2 2 EN 3 3 TX_MAIN_CURSOR 4 9 MAIN_OVRD_EN 10 10 ASYNC_DRV_EN 11 11 ASYNC_DRV_OVRD_EN 12 12 TX_VREGDRV_BYP_OVRD 13 13 TX_VREGDRV_BYP_OVRD_EN 14 14 RESERVED_15_15 15 15 ixDPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_2 2 0x9003 6 0 4294967295 TX_PRE_CURSOR 0 5 PRE_OVRD_EN 6 6 TX_POST_CURSOR 7 12 POST_OVRD_EN 13 13 HDMIMODE_EN 14 14 HDMIMODE_ENABLE_OVRD_EN 15 15 ixDPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_3 2 0x9004 15 0 4294967295 CLK_RDY 0 0 CLK_RDY_OVRD_EN 1 1 DETECT_RX_REQ 2 2 DETECT_RX_REQ_OVRD_EN 3 3 INVERT 4 4 INVERT_OVRD_EN 5 5 LPD 6 6 LPD_OVRD_EN 7 7 TX_DC_COUP_EN 8 8 TX_DC_COUP_EN_OVRD_EN 9 9 PMA_EXTENDED_FIFO_EN 10 10 PMA_EXTENDED_FIFO_EN_OVRD_EN 11 11 TX_MPHY_MODE_EN 12 12 TX_MPHY_MODE_EN_OVRD_EN 13 13 RESERVED_15_14 14 15 ixDPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_4 2 0x9005 3 0 4294967295 RESET 0 0 RESET_OVRD_EN 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_OUT 2 0x9006 5 0 4294967295 TX_ACK 0 0 EN_TX_ACK 1 1 DETRX_RESULT 2 2 EN_DETRX_RESULT 3 3 RESERVED_15_4 4 15 ixDPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_0 2 0x9007 11 0 4294967295 REQ 0 0 REQ_OVRD_EN 1 1 DATA_EN 2 2 DATA_EN_OVRD_EN 3 3 PSTATE 4 5 PSTATE_OVRD_EN 6 6 RATE 7 8 RATE_OVRD_EN 9 9 WIDTH 10 11 WIDTH_OVRD_EN 12 12 RESERVED_15_13 13 15 ixDPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_1 2 0x9008 5 0 4294967295 RX_REF_LD_VAL_5_0 0 5 RX_CDR_VCO_LOWFREQ 6 6 EN 7 7 RX_REF_LD_VAL_6 8 8 RESERVED_15_9 9 15 ixDPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_2 2 0x9009 3 0 4294967295 RX_VCO_LD_VAL 0 12 EN 13 13 RESERVED_15_14 14 15 ixDPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_3 2 0x900a 11 0 4294967295 CDR_TRACK_EN 0 0 CDR_TRACK_EN_OVRD_EN 1 1 CDR_SSC_EN 2 2 CDR_SSC_EN_OVRD_EN 3 3 ALIGN_EN 4 4 ALIGN_EN_OVRD_EN 5 5 CLK_SHIFT 6 6 CLK_SHIFT_OVRD_EN 7 7 DISABLE 8 8 DISABLE_OVRD_EN 9 9 RESERVED_15_10 10 15 ixDPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_4 2 0x900b 11 0 4294967295 LPD 0 0 LPD_OVRD_EN 1 1 INVERT 2 2 INVERT_OVRD_EN 3 3 ADAPT_AFE_EN 4 4 ADAPT_DFE_EN 5 5 ADPT_OVRD_EN 6 6 TERM_EN 7 7 TERM_ACDC 8 8 TERM_OVRD_EN 9 9 RESERVED_15_10 10 15 ixDPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_5 2 0x900c 3 0 4294967295 RESET 0 0 RESET_OVRD_EN 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0 2 0x900d 4 0 4294967295 EQ_ATT_LVL 0 2 EQ_AFE_GAIN 3 6 RESERVED 7 10 EQ_CTLE_BOOST 11 15 ixDPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1 2 0x900e 3 0 4294967295 EQ_DFE_TAP2 0 6 EQ_DFE_TAP1 7 14 EQ_OVRD_EN 15 15 ixDPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_OUT_0 2 0x900f 9 0 4294967295 ACK 0 0 ACK_OVRD_EN 1 1 ADAPT_STS 2 3 ADAPT_STS_OVRD_EN 4 4 RX_ASYNC_DATA 5 5 RX_ASYNC_DATA_OVRD_EN 6 6 RX_SQ_WEAKKEEP_OUT 7 7 RX_SQ_WEAKKEEP_OUT_OVRD_EN 8 8 RESERVED_15_9 9 15 ixDPCSSYS_CR4_LANEX_DIG_ASIC_LANE_ASIC_IN 2 0x9010 3 0 4294967295 LANE_TX2RX_SER_LB 0 0 LANE_RX2TX_PAR_LB 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR4_LANEX_DIG_ASIC_TX_ASIC_IN_0 2 0x9011 12 0 4294967295 CLK_RDY 0 0 RESET 1 1 INVERT 2 2 DATA_EN 3 3 REQ 4 4 LPD 5 5 PSTATE 6 7 RATE 8 10 WIDTH 11 12 MPLLB_SEL 13 13 DETECT_RX_REQ 14 14 DISABLE 15 15 ixDPCSSYS_CR4_LANEX_DIG_ASIC_TX_ASIC_IN_1 2 0x9012 7 0 4294967295 BEACON_EN 0 0 TX_MAIN_CURSOR 1 6 TX_ASYNC_EN 7 7 TX_ASYNC_DATA 8 8 TX_ASYNC_DRV_EN 9 9 TX_VREGDRV_BYP 10 10 RESERVED_15_11 11 15 ixDPCSSYS_CR4_LANEX_DIG_ASIC_TX_ASIC_IN_2 2 0x9013 3 0 4294967295 TX_PRE_CURSOR 0 5 TX_POST_CURSOR 6 11 RESERVED_15_12 12 15 ixDPCSSYS_CR4_LANEX_DIG_ASIC_TX_ASIC_OUT 2 0x9014 3 0 4294967295 TX_ACK 0 0 DETRX_RESULT 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR4_LANEX_DIG_ASIC_RX_ASIC_IN_0 2 0x9015 13 0 4294967295 RESET 0 0 INVERT 1 1 DATA_EN 2 2 REQ 3 3 LPD 4 4 PSTATE 5 6 RATE 7 8 WIDTH 9 10 RESERVED 11 11 ADAPT_AFE_EN 12 12 ADAPT_DFE_EN 13 13 CDR_TRACK_EN 14 14 RESERVED_15_15 15 15 ixDPCSSYS_CR4_LANEX_DIG_ASIC_RX_ASIC_IN_1 2 0x9016 7 0 4294967295 CDR_SSC_EN 0 0 ALIGN_EN 1 1 CLK_SHIFT 2 2 DISABLE 3 3 RX_TERM_EN 4 4 RX_TERM_ACDC 5 5 RESERVED_15_6 6 15 ixDPCSSYS_CR4_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0 2 0x9017 4 0 4294967295 EQ_ATT_LVL 0 2 EQ_AFE_GAIN 3 6 RESERVED 7 10 EQ_CTLE_BOOST 11 15 ixDPCSSYS_CR4_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_1 2 0x9018 3 0 4294967295 EQ_DFE_TAP2 0 6 EQ_DFE_TAP1 7 14 RESERVED_15_15 15 15 ixDPCSSYS_CR4_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0 2 0x9019 3 0 4294967295 RX_CDR_VCO_LOWFREQ 0 0 RX_REF_LD_VAL 1 7 RESERVED_15_8 8 15 ixDPCSSYS_CR4_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1 2 0x901a 2 0 4294967295 RX_VCO_LD_VAL 0 12 RESERVED_15_13 13 15 ixDPCSSYS_CR4_LANEX_DIG_ASIC_RX_ASIC_OUT_0 2 0x901b 4 0 4294967295 ACK 0 0 VALID 1 1 ADAPT_STS 2 3 RESERVED_15_4 4 15 ixDPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_6 2 0x901c 10 0 4294967295 RX_PWM_CLK_SEL 0 1 RX_PWM_CLK_SEL_OVRD_EN 2 2 RX_TERM_LCC_ON 3 3 RX_TERM_LS_ON 4 4 RX_TERM_LS_LCC_ON_OVRD_EN 5 5 RX_TERM_CTL 6 7 RX_TERM_CTL_OVRD_EN 8 8 RX_PWM_EN 9 9 RX_PWM_EN_OVRD_EN 10 10 RESERVED_15_11 11 15 ixDPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_5 2 0x901d 15 0 4294967295 RPTR_EN_MASTER_LANE 0 0 RPTR_EN_MASTER_LANE_OVRD_EN 1 1 DIG_CLK_EN_OTHER_LANE 2 2 DIG_CLK_EN_OTHER_LANE_OVRD_EN 3 3 DIG_CLK_STATE_MASTER_LANE 4 4 DIG_CLK_STATE_MASTER_LANE_OVRD_EN 5 5 SHIFT_MASTER_LANE 6 6 SHIFT_MASTER_LANE_ORVD_EN 7 7 SHIFT_ACK_OTHER_LANE 8 8 SHIFT_ACK_OTHER_LANE_OVRD_EN 9 9 LANE_MASTER 10 10 LANE_MASTER_OVRD_IN_EN 11 11 TX_DWORD_CLK_SYNC_OVRD 12 12 TX_DWORD_CLK_SYNC_OVRD_EN 13 13 RESERVED_15_14 14 15 ixDPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_OUT_1 2 0x901e 11 0 4294967295 RPTR_EN_OUT 0 0 RPTR_EN_OUT_OVRD_EN 1 1 DIG_CLK_EN_OUT 2 2 DIG_CLK_EN_OUT_OVRD_EN 3 3 DIG_CLK_STATE_OUT 4 4 DIG_CLK_STATE_OUT_OVRD_EN 5 5 SHIFT_OUT 6 6 SHIFT_OUT_OVRD_EN 7 7 SHIFT_ACK_OUT 8 8 SHIFT_ACK_OUT_OVRD_EN 9 9 RESERVED_15_10 10 15 ixDPCSSYS_CR4_LANEX_DIG_ASIC_OCLA 2 0x901f 3 0 4294967295 RX_DWORD_OCLA_CLK_EN 0 0 RX_DWORD_OCLA_DATA_EN 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0 2 0x9020 11 0 4294967295 TX_P0_ANA_REFGEN_EN 0 0 TX_P0_ANA_VCM_HOLD 1 1 TX_P0_ANA_CLK_EN 2 2 TX_P0_ANA_WORD_CLK_EN 3 3 TX_P0_ANA_RESET 4 4 TX_P0_ANA_SERIAL_EN 5 5 TX_P0_DIG_CLK_EN 6 6 TX_P0_DATA_EN 7 7 TX_P0_ALLOW_RXDET 8 8 TX_P0_ANA_DCC_COMP_CAL_EN 9 9 RESERVED_15_10 10 15 ixDPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S 2 0x9021 11 0 4294967295 TX_P0S_ANA_REFGEN_EN 0 0 TX_P0S_ANA_VCM_HOLD 1 1 TX_P0S_ANA_CLK_EN 2 2 TX_P0S_ANA_WORD_CLK_EN 3 3 TX_P0S_ANA_RESET 4 4 TX_P0S_ANA_SERIAL_EN 5 5 TX_P0S_DIG_CLK_EN 6 6 TX_P0S_DATA_EN 7 7 TX_P0S_ALLOW_RXDET 8 8 TX_P0S_ANA_DCC_COMP_CAL_EN 9 9 RESERVED_15_10 10 15 ixDPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1 2 0x9022 11 0 4294967295 TX_P1_ANA_REFGEN_EN 0 0 TX_P1_ANA_VCM_HOLD 1 1 TX_P1_ANA_CLK_EN 2 2 TX_P1_ANA_WORD_CLK_EN 3 3 TX_P1_ANA_RESET 4 4 TX_P1_ANA_SERIAL_EN 5 5 TX_P1_DIG_CLK_EN 6 6 TX_P1_DATA_EN 7 7 TX_P1_ALLOW_RXDET 8 8 TX_P1_ANA_DCC_COMP_CAL_EN 9 9 RESERVED_15_10 10 15 ixDPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2 2 0x9023 12 0 4294967295 TX_P2_ANA_REFGEN_EN 0 0 TX_P2_ANA_VCM_HOLD 1 1 TX_P2_ANA_CLK_EN 2 2 TX_P2_ANA_WORD_CLK_EN 3 3 TX_P2_ANA_RESET 4 4 TX_P2_ANA_SERIAL_EN 5 5 TX_P2_DIG_CLK_EN 6 6 TX_P2_DATA_EN 7 7 TX_P2_ALLOW_RXDET 8 8 TX_P2_ALLOW_VBOOST 9 9 TX_P2_ANA_DCC_COMP_CAL_EN 10 10 RESERVED_15_11 11 15 ixDPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_0 2 0x9024 2 0 4294967295 TX_REFGEN_EN_TIME 0 7 TX_CLK_EN 8 15 ixDPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_1 2 0x9025 2 0 4294967295 TX_VCM_HOLD_TIME_14_0 0 14 SKIP_TX_VCM_HOLD_WAIT 15 15 ixDPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_2 2 0x9026 2 0 4294967295 TX_VBOOST_DIS_TIME_12_0 0 12 DTB_SEL 13 15 ixDPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_3 2 0x9027 3 0 4294967295 TX_VCM_HOLD_TIME_17_15 0 2 TX_VBOOST_DIS_TIME_13 3 3 RESERVED_15_4 4 15 ixDPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_4 2 0x9028 2 0 4294967295 TX_VCM_HOLD_GS_TIME 0 14 SKIP_TX_VCM_HOLD_GS_PULSE 15 15 ixDPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_5 2 0x9029 5 0 4294967295 TX_RXDET_TIME 0 9 FAST_TX_RXDET 10 10 TX_RESET_TIME 11 12 TX_SERIAL_EN_TIME 13 14 RESERVED_15_15 15 15 ixDPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_DCC_CR_BANK_ADDR 2 0x902a 1 0 4294967295 ADDR 0 15 ixDPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_DCC_CR_BANK_DATA 2 0x902b 1 0 4294967295 DATA 0 15 ixDPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_DCC_DAC_CTRL 2 0x902c 2 0 4294967295 CTRL 0 7 RESERVED_15_8 8 15 ixDPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_DCC_DAC_RANGE 2 0x902d 2 0 4294967295 CTRL 0 1 RESERVED_15_2 2 15 ixDPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_DCC_DAC_SEL 2 0x902e 6 0 4294967295 SEL 0 2 REQ 3 3 CTRL_UPD 4 4 RANGE_UPD 5 5 BIN_HOT 6 6 RESERVED_15_7 7 15 ixDPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_DCC_DAC_ACK 2 0x902f 2 0 4294967295 ACK 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_DCC_DAC_ADDR 2 0x9030 1 0 4294967295 ADDR 0 15 ixDPCSSYS_CR4_LANEX_DIG_TX_CLK_ALIGN_TX_CTL_0 2 0x9031 4 0 4294967295 TX_NUM_2UI_SHIFTS_16B_MODE 0 3 TX_NUM_2UI_SHIFTS_20B_MODE 4 7 TX_FIFO_BYPASS 8 8 RESERVED_15_9 9 15 ixDPCSSYS_CR4_LANEX_DIG_TX_LBERT_CTL 2 0x9032 4 0 4294967295 MODE 0 3 TRIGGER_ERR 4 4 PAT0 5 14 RESERVED_15_15 15 15 ixDPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0 2 0x9040 12 0 4294967295 RX_P0_ANA_AFE_EN 0 0 RX_P0_ANA_CLK_VREG_EN 1 1 RESERVED_1 2 2 RX_P0_ANA_CLK_EN 3 3 RESERVED_0 4 4 RX_P0_ANA_DESER_EN 5 5 RX_P0_ANA_CDR_EN 6 6 RX_P0_VCO_FREQ_RST 7 7 RX_P0_VCO_CAL_RST 8 8 RX_P0_VCO_CONTCAL_EN 9 9 RX_P0_DIG_CLK_EN 10 10 RESERVED_15_11 11 15 ixDPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S 2 0x9041 12 0 4294967295 RX_P0S_ANA_AFE_EN 0 0 RX_P0S_ANA_CLK_VREG_EN 1 1 RESERVED_2 2 2 RX_P0S_ANA_CLK_EN 3 3 RESERVED_4 4 4 RX_P0S_ANA_DESER_EN 5 5 RX_P0S_ANA_CDR_EN 6 6 RX_P0S_VCO_FREQ_RST 7 7 RX_P0S_VCO_CAL_RST 8 8 RX_P0S_VCO_CONTCAL_EN 9 9 RX_P0S_DIG_CLK_EN 10 10 RESERVED_15_11 11 15 ixDPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1 2 0x9042 12 0 4294967295 RX_P1_ANA_AFE_EN 0 0 RX_P1_ANA_CLK_VREG_EN 1 1 RESERVED_2 2 2 RX_P1_ANA_CLK_EN 3 3 RESERVED_4 4 4 RX_P1_ANA_DESER_EN 5 5 RX_P1_ANA_CDR_EN 6 6 RX_P1_VCO_FREQ_RST 7 7 RX_P1_VCO_CAL_RST 8 8 RX_P1_VCO_CONTCAL_EN 9 9 RX_P1_DIG_CLK_EN 10 10 RESERVED_15_11 11 15 ixDPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2 2 0x9043 12 0 4294967295 RX_P2_ANA_AFE_EN 0 0 RX_P2_ANA_CLK_VREG_EN 1 1 RESERVED_2 2 2 RX_P2_ANA_CLK_EN 3 3 RESERVED_4 4 4 RX_P2_ANA_DESER_EN 5 5 RX_P2_ANA_CDR_EN 6 6 RX_P2_VCO_FREQ_RST 7 7 RX_P2_VCO_CAL_RST 8 8 RX_P2_VCO_CONTCAL_EN 9 9 RX_P2_DIG_CLK_EN 10 10 RESERVED_15_11 11 15 ixDPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1 2 0x9045 5 0 4294967295 RX_AFE_EN_TIME 0 5 FAST_RX_AFE_EN 6 6 RX_VREG_EN_TIME 7 12 FAST_RX_VREG_EN 13 13 RESERVED_15_14 14 15 ixDPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_2 2 0x9046 4 0 4294967295 RX_CLK_EN_TIME 0 5 FAST_RX_CLK_EN 6 6 RX_FAST_START_TIME 7 10 RESERVED_15_11 11 15 ixDPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_3 2 0x9047 5 0 4294967295 RX_RATE_TIME 0 1 RSVD_3_7_2 2 7 RX_CDR_EN_TIME 8 11 RX_DESER_EN_TIME 12 13 RX_DESER_DIS_TIME 14 15 ixDPCSSYS_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0 2 0x9048 8 0 4294967295 INT_GAIN_CAL_FIXED_CNT 0 4 INT_GAIN_CAL_FIXED_CNT_EN 5 5 INT_GAIN_CAL_CNT_SHIFT 6 8 INT_GAIN_CAL_BOUNCE_CNT 9 11 DISABLE_BIN_HOLD 12 12 DISABLE_INT_GAIN_HOLD 13 13 DISABLE_COARSE_CALDONE 14 14 RESERVED_15_15 15 15 ixDPCSSYS_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1 2 0x9049 7 0 4294967295 RX_VCO_OVRD_SEL 0 0 RX_VCO_FREQ_RST 1 1 RX_VCO_CAL_RST 2 2 RX_VCO_CONTCAL_EN 3 3 DISABLE_INT_CAL_MODE 4 4 DPLL_CAL_UG 5 8 DTB_SEL 9 15 ixDPCSSYS_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2 2 0x904a 4 0 4294967295 FREQ_TUNE_START_VAL 0 9 FREQ_TUNE_CAL_STEPS 10 13 SKIP_RX_VCO_FREQ_TUNE_CAL 14 14 SKIP_RX_VCO_CAL 15 15 ixDPCSSYS_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0 2 0x904b 4 0 4294967295 RX_VCO_STARTUP_TIME 0 6 RX_VCO_UPDATE_TIME 7 10 RX_VCO_CNTR_PWRUP_TIME 11 14 FAST_RX_VCO_WAIT 15 15 ixDPCSSYS_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1 2 0x904c 2 0 4294967295 RX_VCO_CNTR_SETTLE_TIME 0 2 RESERVED_15_3 3 15 ixDPCSSYS_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0 2 0x904d 6 0 4294967295 RX_ANA_CDR_FREQ_TUNE 0 9 RX_ANA_VCO_CNTR_PD 10 10 RX_ANA_VCO_CNTR_EN 11 11 RX_ANA_CDR_STARTUP 12 12 RX_ANA_CDR_VCO_EN 13 13 RESERVED_15_14 14 15 ixDPCSSYS_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1 2 0x904e 7 0 4294967295 RX_VCO_FSM_STATE 0 3 RX_VCO_FREQ_RST 4 4 RX_VCO_CAL_RST 5 5 RX_VCO_CONTCAL_EN 6 6 RX_VCO_CAL_DONE 7 7 DPLL_FREQ_RST 8 8 RESERVED_15_9 9 15 ixDPCSSYS_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_2 2 0x904f 4 0 4294967295 VCO_CNTR_FINAL 0 12 VCOCLK_TOO_FAST 13 13 RX_VCO_CORRECT 14 14 RX_VCO_UP 15 15 ixDPCSSYS_CR4_LANEX_DIG_RX_RX_ALIGN_XAUI_COMM_MASK 2 0x9050 2 0 4294967295 XAUI_COMM_MASK 0 9 RESERVED_15_10 10 15 ixDPCSSYS_CR4_LANEX_DIG_RX_LBERT_CTL 2 0x9051 3 0 4294967295 MODE 0 3 SYNC 4 4 RESERVED_15_5 5 15 ixDPCSSYS_CR4_LANEX_DIG_RX_LBERT_ERR 2 0x9052 2 0 4294967295 COUNT 0 14 OV14 15 15 ixDPCSSYS_CR4_LANEX_DIG_RX_CDR_CDR_CTL_0 2 0x9053 7 0 4294967295 PHDET_EN 0 1 PHDET_EDGE 2 3 PHDET_POL 4 4 PHDET_EN_PR_MODE 5 5 ALWAYS_REALIGN 6 6 DTB_SEL 7 10 RESERVED_15_11 11 15 ixDPCSSYS_CR4_LANEX_DIG_RX_CDR_CDR_CTL_1 2 0x9054 2 0 4294967295 SSC_OFF_CNT0 0 9 SSC_OFF_CNT1 10 15 ixDPCSSYS_CR4_LANEX_DIG_RX_CDR_CDR_CTL_2 2 0x9055 2 0 4294967295 SSC_ON_CNT0 0 8 SSC_ON_CNT1 9 15 ixDPCSSYS_CR4_LANEX_DIG_RX_CDR_CDR_CTL_3 2 0x9056 6 0 4294967295 SSC_OFF_PHUG0 0 2 SSC_OFF_PHUG1 3 5 SSC_OFF_FRUG0 6 8 OVRD_DPLL_GAIN 9 9 PHUG_OVRD_VALUE 10 12 FRUG_OVRD_VALUE 13 15 ixDPCSSYS_CR4_LANEX_DIG_RX_CDR_CDR_CTL_4 2 0x9057 6 0 4294967295 SSC_OFF_FRUG1 0 2 SSC_ON_FRUG0 3 5 SSC_ON_FRUG1 6 8 SSC_ON_PHUG0 9 11 SSC_ON_PHUG1 12 14 RESERVED_15_15 15 15 ixDPCSSYS_CR4_LANEX_DIG_RX_CDR_STAT 2 0x9058 3 0 4294967295 PHUG_VALUE 0 2 FRUG_VALUE 3 5 RESERVED_15_6 6 15 ixDPCSSYS_CR4_LANEX_DIG_RX_DPLL_FREQ 2 0x9059 2 0 4294967295 VAL 0 13 RESERVED_15_14 14 15 ixDPCSSYS_CR4_LANEX_DIG_RX_DPLL_FREQ_BOUND_0 2 0x905a 3 0 4294967295 FREQ_BOUND_EN 0 0 UPPER_FREQ_BOUND 1 10 RESERVED_15_11 11 15 ixDPCSSYS_CR4_LANEX_DIG_RX_DPLL_FREQ_BOUND_1 2 0x905b 2 0 4294967295 LOWER_FREQ_BOUND 0 9 RESERVED_15_10 10 15 ixDPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_0 2 0x9060 4 0 4294967295 N_TOP_ASM1 0 9 N_TGG_ASM1 10 13 START_ASM1 14 14 ADPT_CLK_DIV4_EN 15 15 ixDPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1 2 0x9061 5 0 4294967295 N_WAIT_ASM1 0 6 FAST_AFE_DFE_SETTLE 7 7 CTLE_POLE_OVRD_VAL 8 10 CTLE_POLE_OVRD_EN 11 11 RESERVED_15_12 12 15 ixDPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_2 2 0x9062 3 0 4294967295 TGG_PTTRN_0 0 4 TGG_PTTRN_1 5 9 RESERVED_15_10 10 15 ixDPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3 2 0x9063 8 0 4294967295 CTLE_EN 0 4 VGA_EN 5 5 ATT_EN 6 6 DFE_EN 7 11 EYEHE_EN 12 12 EYEHO_EN 13 13 TGG_EN 14 14 ESL_TWICE_DSL 15 15 ixDPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_4 2 0x9064 4 0 4294967295 CTLE_TH 0 3 VGA_TH 4 7 DFE1_TH 8 11 DFE2_TH 12 15 ixDPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_5 2 0x9065 4 0 4294967295 DFE3_TH 0 3 DFE4_TH 4 7 DFE5_TH 8 11 TH_OFFSET 12 15 ixDPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6 2 0x9066 6 0 4294967295 CTLE_MU 0 2 VGA_MU 3 5 ATT_MU 6 8 VGA_SAT_CNT 9 11 VGA_SAT_CNT_STICKY 12 12 ATT_LOW_TH 13 15 ixDPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_7 2 0x9067 4 0 4294967295 VGA_MIN_SAT 0 4 VGA_LEV_HIGH 5 9 VGA_LEV_LOW 10 14 RESERVED_15_15 15 15 ixDPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8 2 0x9068 6 0 4294967295 DFE1_MU 0 2 DFE2_MU 3 5 DFE3_MU 6 8 DFE4_MU 9 11 DFE5_MU 12 14 RESERVED_15_15 15 15 ixDPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_9 2 0x9069 2 0 4294967295 ERR_SLE_ADPT_INIT 0 7 ERR_SLO_ADPT_INIT 8 15 ixDPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG 2 0x906a 6 0 4294967295 RST_ADPT_ATT 0 0 RST_ADPT_VGA 1 1 RST_ADPT_CTLE_BOOST 2 2 RST_ADPT_CTLE_POLE 3 3 RST_ADPT_TAP1 4 4 RESERVED_15_5 5 15 ixDPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ATT_STATUS 2 0x906b 3 0 4294967295 ATT_ADPT_CODE 0 7 ASM1_DON 8 8 RESERVED_15_9 9 15 ixDPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_VGA_STATUS 2 0x906c 3 0 4294967295 VGA_ADPT_CODE 0 9 ASM1_DONE 10 10 RESERVED_15_11 11 15 ixDPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_CTLE_STATUS 2 0x906d 4 0 4294967295 CTLE_BOOST_ADPT_CODE 0 9 CTLE_POLE_ADPT_CODE 10 12 ASM1_DONE 13 13 RESERVED_15_14 14 15 ixDPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_DFE_TAP1_STATUS 2 0x906e 3 0 4294967295 DFE_TAP1_ADPT_CODE 0 12 ASM1_DONE 13 13 RESERVED_15_14 14 15 ixDPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_DFE_TAP2_STATUS 2 0x906f 3 0 4294967295 DFE_TAP2_ADPT_CODE 0 11 ASM1_DONE 12 12 RESERVED_15_13 13 15 ixDPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_DFE_TAP3_STATUS 2 0x9070 3 0 4294967295 DFE_TAP3_ADPT_CODE 0 11 ASM1_DONE 12 12 RESERVED_15_13 13 15 ixDPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_DFE_TAP4_STATUS 2 0x9071 3 0 4294967295 DFE_TAP4_ADPT_CODE 0 11 ASM1_DONE 12 12 RESERVED_15_13 13 15 ixDPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_DFE_TAP5_STATUS 2 0x9072 3 0 4294967295 DFE_TAP5_ADPT_CODE 0 11 ASM1_DONE 12 12 RESERVED_15_13 13 15 ixDPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_DFE_DATA_EVEN_VDAC_OFST 2 0x9073 2 0 4294967295 DFE_DATA_EVEN_VDAC_OFST 0 7 RESERVED_15_8 8 15 ixDPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_DFE_DATA_ODD_VDAC_OFST 2 0x9074 2 0 4294967295 DFE_DATA_ODD_VDAC_OFST 0 7 RESERVED_15_8 8 15 ixDPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN 2 0x9075 2 0 4294967295 RX_ANA_SLICER_CTRL_E 0 3 RESERVED_15_4 4 15 ixDPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD 2 0x9076 2 0 4294967295 RX_ANA_SLICER_CTRL_O 0 3 RESERVED_15_4 4 15 ixDPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST 2 0x9077 2 0 4294967295 DFE_ERROR_EVEN_VDAC_OFST 0 7 RESERVED_15_8 8 15 ixDPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST 2 0x9078 2 0 4294967295 DFE_ERROR_ODD_VDAC_OFST 0 7 RESERVED_15_8 8 15 ixDPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL 2 0x9079 2 0 4294967295 E_SLO_LVL 0 7 E_SLE_LVL 8 15 ixDPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_RESET 2 0x907a 2 0 4294967295 RESET_ASM1 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1 2 0x907b 4 0 4294967295 DFE_T1_IDAC 0 4 DFE_T2_IDAC 5 9 DCC_START_IDAC 10 14 RESERVED_15_15 15 15 ixDPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2 2 0x907c 3 0 4294967295 DFE_DAT_EVEN_VDAC 0 4 DFE_DAT_ODD_VDAC 5 9 RESERVED_15_10 10 15 ixDPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3 2 0x907d 3 0 4294967295 DFE_ERR_EVEN_VDAC 0 4 DFE_ERR_ODD_VDAC 5 9 RESERVED_15_10 10 15 ixDPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_CR_BANK_ADDR 2 0x907e 1 0 4294967295 ADDR 0 15 ixDPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_CR_BANK_DATA 2 0x907f 1 0 4294967295 DATA 0 15 ixDPCSSYS_CR4_LANEX_DIG_RX_STAT_LD_VAL_1 2 0x9080 2 0 4294967295 SC1_LD_VAL 0 14 SC1_START 15 15 ixDPCSSYS_CR4_LANEX_DIG_RX_STAT_DATA_MSK 2 0x9081 1 0 4294967295 DATA_MSK_15_0 0 15 ixDPCSSYS_CR4_LANEX_DIG_RX_STAT_MATCH_CTL0 2 0x9082 4 0 4294967295 PTTRN_MSK_CR1A_4_0 0 4 PTTRN_CR1A_4_0 5 9 DATA_MSK_19_16 10 13 SCOPE_DLY 14 15 ixDPCSSYS_CR4_LANEX_DIG_RX_STAT_MATCH_CTL1 2 0x9083 5 0 4294967295 PTTRN_CR1B_EN 0 0 PTTRN_MSK_CR1B_4_0 1 5 PTTRN_CR1B_4_0 6 10 PTTRN_CR1A_ADPT_EN 11 11 RESERVED_15_12 12 15 ixDPCSSYS_CR4_LANEX_DIG_RX_STAT_STAT_CTL0 2 0x9084 10 0 4294967295 RESERVED_0 0 0 CORR_SHFT_SEL_VGA 1 1 CORR_SHFT_SEL 2 2 CORR_SRC_SEL 3 4 CORR_MODE_EN 5 5 STAT_SHFT_SEL 6 9 STAT_SRC_SEL 10 12 STAT_RXCLK_SEL 13 13 SC_TIMER_MODE 14 14 SKIP_EN 15 15 ixDPCSSYS_CR4_LANEX_DIG_RX_STAT_STAT_CTL1 2 0x9085 13 0 4294967295 STAT_CNT_0_EN 0 0 STAT_CNT_1_EN 1 1 STAT_CNT_2_EN 2 2 STAT_CNT_3_EN 3 3 STAT_CNT_4_EN 4 4 STAT_CNT_5_EN 5 5 STAT_CNT_6_EN 6 6 RESERVED_8_7 7 8 SC_PAUSE 9 9 STAT_CLK_EN 10 10 DATA_DLY_SEL 11 12 VLD_LOSS_CLR 13 13 VLD_CTL 14 15 ixDPCSSYS_CR4_LANEX_DIG_RX_STAT_SMPL_CNT1 2 0x9086 2 0 4294967295 SMPL_CNT1 0 14 SMPL_CNT1_DONE 15 15 ixDPCSSYS_CR4_LANEX_DIG_RX_STAT_STAT_CNT_0 2 0x9087 2 0 4294967295 STAT_CNT_0 0 14 SMPL_CNT1_DONE 15 15 ixDPCSSYS_CR4_LANEX_DIG_RX_STAT_STAT_CNT_1 2 0x9088 2 0 4294967295 STAT_CNT_1 0 14 SMPL_CNT1_DONE 15 15 ixDPCSSYS_CR4_LANEX_DIG_RX_STAT_STAT_CNT_2 2 0x9089 2 0 4294967295 STAT_CNT_2 0 14 SMPL_CNT1_DONE 15 15 ixDPCSSYS_CR4_LANEX_DIG_RX_STAT_STAT_CNT_3 2 0x908a 2 0 4294967295 STAT_CNT_3 0 14 SMPL_CNT1_DONE 15 15 ixDPCSSYS_CR4_LANEX_DIG_RX_STAT_STAT_CNT_4 2 0x908b 2 0 4294967295 STAT_CNT_4 0 14 SMPL_CNT1_DONE 15 15 ixDPCSSYS_CR4_LANEX_DIG_RX_STAT_STAT_CNT_5 2 0x908c 2 0 4294967295 STAT_CNT_5 0 14 SMPL_CNT1_DONE 15 15 ixDPCSSYS_CR4_LANEX_DIG_RX_STAT_STAT_CNT_6 2 0x908d 2 0 4294967295 STAT_CNT_6 0 14 SMPL_CNT1_DONE 15 15 ixDPCSSYS_CR4_LANEX_DIG_RX_STAT_CAL_COMP_CLK_CTL 2 0x908e 3 0 4294967295 PRECHRGE_CNT 0 2 REF_DIV_CNT 3 5 RESERVED_15_6 6 15 ixDPCSSYS_CR4_LANEX_DIG_RX_STAT_MATCH_CTL2 2 0x908f 2 0 4294967295 PTTRN_CR1A_19_5 0 14 RESERVED_15_15 15 15 ixDPCSSYS_CR4_LANEX_DIG_RX_STAT_MATCH_CTL3 2 0x9090 2 0 4294967295 PTTRN_MSK_CR1A_19_5 0 14 RESERVED_15_15 15 15 ixDPCSSYS_CR4_LANEX_DIG_RX_STAT_MATCH_CTL4 2 0x9091 2 0 4294967295 PTTRN_CR1B_19_5 0 14 RESERVED_15_15 15 15 ixDPCSSYS_CR4_LANEX_DIG_RX_STAT_MATCH_CTL5 2 0x9092 2 0 4294967295 PTTRN_MSK_CR1B_19_5 0 14 RESERVED_15_15 15 15 ixDPCSSYS_CR4_LANEX_DIG_RX_STAT_STAT_CTL2 2 0x9093 4 0 4294967295 DATA_DLY_SEL_2 0 0 SCOPE_DLY_2 1 1 DISABLE_SAMPLE_COUNT 2 2 RESERVED_15_3 3 15 ixDPCSSYS_CR4_LANEX_DIG_RX_STAT_STAT_STOP 2 0x9094 2 0 4294967295 SC1_STOP 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR4_LANEX_DIG_MPHY_RX_PWM_CTL 2 0x9095 3 0 4294967295 RX_PWM_POL 0 0 RX_PWM_DATA_POL 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR4_LANEX_DIG_MPHY_RX_TERM_LS_CTL 2 0x9096 2 0 4294967295 RX_TERM_LCC_CNT 0 2 RESERVED_15_3 3 15 ixDPCSSYS_CR4_LANEX_DIG_MPHY_RX_ANA_PWM_CLK_STABLE_CNT 2 0x9097 2 0 4294967295 PWM_CLK_STABLE_CNT 0 3 RESERVED_15_4 4 15 ixDPCSSYS_CR4_LANEX_DIG_ANA_TX_OVRD_OUT 2 0x90a0 15 0 4294967295 TX_ANA_CLK_SHIFT 0 0 TX_ANA_DATA_EN 1 1 TX_ANA_REFGEN_EN 2 2 TX_ANA_VCM_HOLD 3 3 TX_ANA_CLK_EN 4 4 TX_ANA_WORD_CLK_EN 5 5 TX_ANA_MPLLA_CLK_EN 6 6 TX_ANA_MPLLB_CLK_EN 7 7 TX_ANA_RESET 8 8 TX_ANA_SERIAL_EN 9 9 TX_ANA_DATA_RATE 10 11 RESERVED 12 12 TX_DIV4_EN 13 13 TX_RXDET_EN 14 14 TX_OVRD_EN 15 15 ixDPCSSYS_CR4_LANEX_DIG_ANA_TX_TERM_CODE_OVRD_OUT 2 0x90a1 5 0 4294967295 TX_TERM_CODE 0 9 TX_TERM_OVRD_EN 10 10 TX_DRV_SRC 11 12 TX_DRV_SRC_OVRD_EN 13 13 RESERVED_15_14 14 15 ixDPCSSYS_CR4_LANEX_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT 2 0x90a2 3 0 4294967295 TX_TERM_DN_CLK 0 0 TX_TERM_CLK_SELF_CLEAR_DISABLE 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR4_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_0 2 0x90a3 3 0 4294967295 TX_ANA_LOAD_CLK 0 0 TX_ANA_CTRL_LEG_PULL_EN_13_0 1 14 TX_EQ_OVRD_EN 15 15 ixDPCSSYS_CR4_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_1 2 0x90a4 2 0 4294967295 TX_ANA_CTRL_LEG_PULL_EN_19_14 0 5 RESERVED_15_6 6 15 ixDPCSSYS_CR4_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_2 2 0x90a5 4 0 4294967295 RESERVED 0 2 TX_ANA_CTRL_EQ_MUX_SEL 3 6 TX_ANA_CTRL_PRE 7 12 RESERVED_15_13 13 15 ixDPCSSYS_CR4_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_3 2 0x90a6 2 0 4294967295 TX_ANA_CTRL_POST 0 8 RESERVED_15_9 9 15 ixDPCSSYS_CR4_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_4 2 0x90a7 1 0 4294967295 TX_ANA_CTRL_LEG_PULL_DIR_19_4 0 15 ixDPCSSYS_CR4_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_5 2 0x90a8 2 0 4294967295 TX_ANA_CTRL_LEG_PULL_DIR_3_0 0 3 RESERVED_15_4 4 15 ixDPCSSYS_CR4_LANEX_DIG_ANA_RX_CTL_OVRD_OUT 2 0x90a9 9 0 4294967295 RESERVED 0 0 RX_ANA_DATA_RATE 1 2 RX_ANA_WORD_CLK_EN 3 3 RX_ANA_DIV4_EN 4 4 RX_ANA_DFE_TAPS_EN 5 5 RX_ANA_ADAPTATION_EN 6 6 RX_LBK_CLK_EN 7 7 RX_CTL_OVRD_EN 8 8 RESERVED_15_9 9 15 ixDPCSSYS_CR4_LANEX_DIG_ANA_RX_PWR_OVRD_OUT 2 0x90aa 9 0 4294967295 RX_ANA_AFE_EN 0 0 RX_ANA_CLK_VREG_EN 1 1 RX_ANA_CLK_DCC_EN 2 2 RX_ANA_CLK_EN 3 3 RX_ANA_CDR_EN 4 4 RX_ANA_DESERIAL_EN 5 5 RX_PWR_OVRD_EN 6 6 RX_ANA_FAST_START 7 7 RESERVED_15_8 8 15 ixDPCSSYS_CR4_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0 2 0x90ab 7 0 4294967295 RX_ANA_CDR_VCO_EN 0 0 RX_ANA_CDR_STARTUP 1 1 RX_VCO_CDR_OVRD_EN 2 2 RX_ANA_CDR_FREQ_TUNE 3 12 RX_ANA_VCO_CNTR_EN 13 13 RX_ANA_VCO_CNTR_CLK 14 14 RX_CDR_FREQ_TUNE_OVRD_EN 15 15 ixDPCSSYS_CR4_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_1 2 0x90ac 3 0 4294967295 RX_ANA_CDR_VCO_LOWFREQ 0 0 RX_ANA_VCO_CNTR_PD 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR4_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_2 2 0x90ad 3 0 4294967295 RX_ANA_CDR_FREQ_TUNE_CLK 0 0 CDR_FREQ_TUNE_CLK_SELF_CLEAR_DISABLE 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR4_LANEX_DIG_ANA_RX_CAL 2 0x90ae 7 0 4294967295 RX_ANA_CAL_MUXA_SEL 0 4 RX_ANA_CAL_MUXB_SEL 5 9 RX_ANA_CAL_LPFBYP_EN 10 10 RESERVED 11 11 RX_ANA_SLICER_CAL_EN 12 12 RX_ANA_CAL_MODE 13 14 RX_ANA_CAL_COMP_EN 15 15 ixDPCSSYS_CR4_LANEX_DIG_ANA_RX_DAC_CTRL 2 0x90af 2 0 4294967295 RX_ANA_CAL_DAC_CTRL 0 7 RESERVED_15_8 8 15 ixDPCSSYS_CR4_LANEX_DIG_ANA_RX_DAC_CTRL_OVRD 2 0x90b0 2 0 4294967295 RX_CAL_DAC_CTRL_OVRD 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR4_LANEX_DIG_ANA_RX_DAC_CTRL_SEL 2 0x90b1 2 0 4294967295 RX_ANA_CAL_DAC_CTRL_SEL 0 4 RESERVED_15_5 5 15 ixDPCSSYS_CR4_LANEX_DIG_ANA_RX_AFE_ATT_VGA 2 0x90b2 5 0 4294967295 RX_ANA_AFE_ATT_LVL 0 2 RX_ANA_AFE_GAIN 3 6 RESERVED 7 10 RX_AFE_OVRD_EN 11 11 RESERVED_15_12 12 15 ixDPCSSYS_CR4_LANEX_DIG_ANA_RX_AFE_CTLE 2 0x90b3 3 0 4294967295 RESERVED 0 2 RX_ANA_AFE_CTLE_BOOST 3 7 RESERVED_15_8 8 15 ixDPCSSYS_CR4_LANEX_DIG_ANA_RX_SCOPE 2 0x90b4 7 0 4294967295 RX_ANA_SCOPE_EN 0 0 RX_ANA_SCOPE_SEL 1 2 RX_ANA_SCOPE_PH_CLK 3 3 RX_ANA_SCOPE_PHASE 4 11 RX_ANA_SCOPE_CLK_EN 12 12 RX_SCOPE_SELF_CLEAR_DISABLE 13 13 RESERVED_15_14 14 15 ixDPCSSYS_CR4_LANEX_DIG_ANA_RX_SLICER_CTRL 2 0x90b5 4 0 4294967295 RX_ANA_SLICER_CTRL_E 0 3 RX_ANA_SLICER_CTRL_O 4 7 RX_ANA_SLICER_CTRL_OVRD_EN 8 8 RESERVED_15_9 9 15 ixDPCSSYS_CR4_LANEX_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST 2 0x90b6 2 0 4294967295 RX_ANA_IQ_PHASE_ADJUST 0 6 RESERVED_15_7 7 15 ixDPCSSYS_CR4_LANEX_DIG_ANA_RX_ANA_IQ_SENSE_EN 2 0x90b7 2 0 4294967295 RX_ANA_IQ_SENSE_EN 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR4_LANEX_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN 2 0x90b8 3 0 4294967295 RX_ANA_CAL_DAC_CTRL_EN 0 0 DAC_CTRL_SELF_CLEAR_DISABLE 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR4_LANEX_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE 2 0x90b9 3 0 4294967295 RX_ANA_AFE_UPDATE_EN 0 0 AFE_UPDATE_SELF_CLEAR_DISABLE 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR4_LANEX_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK 2 0x90ba 3 0 4294967295 RX_ANA_IQ_PHASE_ADJUST_CLK 0 0 PHASE_ADJUST_SELF_CLEAR_DISABLE 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR4_LANEX_DIG_ANA_STATUS_0 2 0x90bb 9 0 4294967295 TX_ANA_CLK_SHIFT_ACK 0 0 TX_ANA_RXDETP_RESULT 1 1 TX_ANA_RXDETM_RESULT 2 2 TX_ANA_LOOPBACK_EN 3 3 TX_ANA_CLK_LB_EN 4 4 RX_ANA_CAL_RESULT 5 5 RX_ANA_SCOPE_DATA 6 6 TX_ANA_DCC_CAL_RESULT 7 7 TX_ANA_CTRL_EQ_MUX 8 15 ixDPCSSYS_CR4_LANEX_DIG_ANA_STATUS_1 2 0x90bc 2 0 4294967295 RX_ANA_VCO_CNTR 0 12 RESERVED_15_13 13 15 ixDPCSSYS_CR4_LANEX_DIG_ANA_RX_TERM_CODE_OVRD_OUT 2 0x90bd 3 0 4294967295 RX_TERM_CODE 0 5 RX_TERM_OVRD_EN 6 6 RESERVED_15_7 7 15 ixDPCSSYS_CR4_LANEX_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT 2 0x90be 3 0 4294967295 RX_TERM_CLK 0 0 RX_TERM_CLK_SELF_CLEAR_DISABLE 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR4_LANEX_DIG_ANA_MPHY_OVRD_OUT 2 0x90bf 9 0 4294967295 RX_ANA_SQ_CTRL_TRESH 0 2 RX_ANA_SQ_CTRL_TRESH_OVRD_EN 3 3 RX_ANA_SQ_CTRL_RESP 4 5 RX_ANA_SQ_CTRL_RESP_OVRD_EN 6 6 RX_ANA_PWM_EN 7 7 RX_ANA_PWM_EN_OVRD_EN 8 8 RX_ANA_PWM_CLK_SEL 9 10 RX_ANA_PWM_CLK_SEL_OVRD_EN 11 11 RESERVED_15_12 12 15 ixDPCSSYS_CR4_LANEX_DIG_ANA_SIGDET_OVRD_OUT_1 2 0x90c0 7 0 4294967295 RX_ANA_SIGDET_HF_THRESH 0 2 RX_ANA_SIGDET_HF_THRESH_OVRD_EN 3 3 RX_ANA_SIGDET_HF_CAL_TUNE 4 9 RX_ANA_SIGDET_CAL_TUNE_OVRD_EN 10 10 RX_ANA_SIGDET_CAL_EN 11 11 RX_ANA_SIGDET_CAL_EN_OVRD_EN 12 12 RESERVED_15_13 13 15 ixDPCSSYS_CR4_LANEX_DIG_ANA_SIGDET_OVRD_OUT_2 2 0x90c1 7 0 4294967295 RX_ANA_SIGDET_LF_THRESH 0 2 RX_ANA_SIGDET_LF_THRESH_OVRD_EN 3 3 RX_ANA_SIGDET_LF_FILTER_EN 4 4 RX_ANA_SIGDET_LF_FILTER_EN_OVRD_EN 5 5 RX_ANA_SIGDET_CAL_TUNE 6 11 RX_ANA_SIGDET_CAL_TUNE_OVRD_EN 12 12 RESERVED_15_13 13 15 ixDPCSSYS_CR4_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT 2 0x90c2 8 0 4294967295 TX_ANA_DCC_CAL_RANGE 0 1 TX_ANA_DCC_CAL_RANGE_OVRD_EN 2 2 TX_ANA_DCC_CAL_COMP_EN 3 3 TX_ANA_DCC_CAL_COMP_EN_OVRD_EN 4 4 TX_ANA_DCC_CAL_CTRL 5 12 TX_ANA_DCC_CAL_CTRL_OVRD_EN 13 13 TX_ANA_DCC_CAL_CTRL_EN 14 14 TX_ANA_DCC_CAL_CTRL_EN_OVRD_EN 15 15 ixDPCSSYS_CR4_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2 2 0x90c3 5 0 4294967295 TX_ANA_DCC_CAL_CTRL_SEL 0 2 TX_ANA_DCC_CAL_CTRL_SEL_OVRD_EN 3 3 TX_ANA_DCC_CLK_COMP 4 4 TX_ANA_DCC_CLK_COMP_OVRD_EN 5 5 RESERVED_15_6 6 15 ixDPCSSYS_CR4_LANEX_DIG_ANA_TX_OVRD_OUT_2 2 0x90c4 6 0 4294967295 TX_ANA_FAST_START 0 0 TX_ANA_FAST_START_OVRD_EN 1 1 TX_CLK_LB_EN 2 2 TX_CLK_LB_EN_OVRD_EN 3 3 TX_ACJTAG_EN 4 4 RESERVED_15_5 5 15 ixDPCSSYS_CR4_LANEX_ANA_TX_OVRD_MEAS 2 0x90e0 9 0 4294967295 OVRD_CLK_SHIFT 0 0 CLK_SHIFT_REG 0 0 MEAS_ATB_CAL_MUX 0 0 MEAS_ATB_CAL_COMP 0 0 OVRD_VCM_HOLD 0 0 VCM_HOLD_REG 0 0 PULL_UP_REG 0 0 PULL_DN_REG 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR4_LANEX_ANA_TX_PWR_OVRD 2 0x90e1 9 0 4294967295 OVRD_TX_LOOPBACK 0 0 LOOPBACK_EN_REG 0 0 REFGEN_EN_REG 0 0 CLK_DIV_EN_REG 0 0 DATA_EN_REG_INT 0 0 CLK_EN_REG 0 0 SERIAL_EN_REG 0 0 OVRD_EN 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR4_LANEX_ANA_TX_ALT_BUS 2 0x90e2 6 0 4294967295 DRV_SOURCE_REG 0 0 OVRD_ALT_BUS 0 0 ATB_S_ENABLE 0 0 TX_ALT_RINGO 0 0 JTAG_DATA_REG 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR4_LANEX_ANA_TX_ATB1 2 0x90e3 9 0 4294967295 MEAS_ATB_GD 0 0 MEAS_ATB_VDDH 0 0 OVERRIDE_RXDETREF 0 0 MEAS_ATB_VPTX 0 0 OVERRIDE_REGREF 0 0 MEAS_ATB_VREG_DRV 0 0 MEAS_ATB_VREG 0 0 MEAS_ATB_VPH_HALF 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR4_LANEX_ANA_TX_ATB2 2 0x90e4 9 0 4294967295 MEAS_ATB_VCM 0 0 MEAS_ATB_CAL_VDAC_CM 0 0 MEAS_ATB_CAL_VDAC_DIFF 0 0 MEAS_ATB_TXM 0 0 MEAS_ATB_TXP 0 0 MEAS_ATB_RXDETREF 0 0 LFPS_HIGH_PRIORITY 0 0 OSC_DIV4_EN 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR4_LANEX_ANA_TX_DCC_DAC 2 0x90e5 2 0 4294967295 DCC_DAC_REG 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR4_LANEX_ANA_TX_DCC_CTRL1 2 0x90e6 7 0 4294967295 NC0 0 0 OVRD_DCC_DAC_CTRL_SEL 0 0 DCC_DAC_CTRL_SEL_REG 0 0 OVRD_DCC_DAC_CTRL_EN 0 0 DCC_DAC_CTRL_EN_REG 0 0 OVRD_DCC_DAC_REG 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR4_LANEX_ANA_TX_TERM_CODE 2 0x90e7 2 0 4294967295 TERM_CODE_REG_70 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR4_LANEX_ANA_TX_TERM_CODE_CTRL 2 0x90e8 8 0 4294967295 VREG_BOOST_1 0 0 OVRD_UPDATE_TERM 0 0 UPDATE_TERM_REG 0 0 OVRD_RESET_TERM 0 0 RESET_TERM_REG 0 0 OVRD_TERM_CODE 0 0 TERM_CODE_REG_98 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR4_LANEX_ANA_TX_OVRD_CLK 2 0x90e9 9 0 4294967295 VREG_BOOST_0 0 0 CLK_LB_EN_REG 0 0 OVRD_LB_EN 0 0 MPLLB_CLK_EN_REG 0 0 MPLLA_CLK_EN_REG 0 0 OVRD_MPLLAB_EN 0 0 WORD_CLK_EN_REG 0 0 OVRD_WORD_CLK_EN 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR4_LANEX_ANA_TX_MISC1 2 0x90ea 8 0 4294967295 MEAS_ATB_CAL_CLK_ALIGN 0 0 OVRD_DCC_DAC_CTRL_RANGE 0 0 DCC_DAC_CTRL_RANGE_REG 0 0 OVRD_VREF_SEL 0 0 VREF_SEL_REG 0 0 FORCE_ATB_TXM 0 0 FORCE_ATB_TXP 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR4_LANEX_ANA_TX_MISC2 2 0x90eb 8 0 4294967295 TX_PEAKING_LVL 0 0 VREG_CP_GAIN_CTRL 0 0 TX_SLEW_EN 0 0 EN_INV_POST 0 0 EN_INV_PRE 0 0 TX_VREG_EN_BYP 0 0 TX_VDRIVER_PULLDN_EN 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR4_LANEX_ANA_TX_MISC3 2 0x90ec 4 0 4294967295 TX_VREG_OVRD_RING_CTRL 0 0 TX_DCC_LOWV 0 0 NC7_2 2 7 RESERVED_15_8 8 15 ixDPCSSYS_CR4_LANEX_ANA_TX_RESERVED2 2 0x90ed 2 0 4294967295 NC7_0 0 7 RESERVED_15_8 8 15 ixDPCSSYS_CR4_LANEX_ANA_TX_RESERVED3 2 0x90ee 2 0 4294967295 NC7_0 0 7 RESERVED_15_8 8 15 ixDPCSSYS_CR4_LANEX_ANA_TX_RESERVED4 2 0x90ef 2 0 4294967295 NC7_0 0 7 RESERVED_15_8 8 15 ixDPCSSYS_CR4_LANEX_ANA_RX_CLK_1 2 0x90f0 8 0 4294967295 CDR_VCO_STARTUP_CODE 0 0 CDR_VCO_TEMP_COMP_EN 0 0 CDR_VCO_USE_UNCAL_BIAS 0 0 OVERRIDE_CDR_EN 0 0 OVRD_CLK_EN 0 0 CLK_EN_REG 0 0 NC7 7 7 RESERVED_15_8 8 15 ixDPCSSYS_CR4_LANEX_ANA_RX_CLK_2 2 0x90f1 5 0 4294967295 IQ_PHASE_ADJUST_REG 0 0 OVRD_IQ_PHASE_ADJUST 0 0 RX_LOOPBACK_CLK_REG 0 0 OVRD_RX_LOOPBACK_CLK 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR4_LANEX_ANA_RX_CDR_DES 2 0x90f2 7 0 4294967295 OVRD_WORD_CLK_EN 0 0 WORD_CLK_EN_REG 0 0 PHDET_ODD_REG 0 0 PHDET_EVEN_REG 0 0 SIGDET_VREF_EXT_EN 0 0 NC7_5 5 7 RESERVED_15_8 8 15 ixDPCSSYS_CR4_LANEX_ANA_RX_SLC_CTRL 2 0x90f3 3 0 4294967295 RX_SLICER_CTRL_O_REG 0 0 RX_SLICER_CTRL_E_REG 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR4_LANEX_ANA_RX_PWR_CTRL1 2 0x90f4 8 0 4294967295 OVRD_ACJT_EN 0 0 ACJT_EN_REG 0 0 OVRD_AFE_EN 0 0 AFE_EN_REG 0 0 AFE_CM_SEL 0 0 ATT_PULLDN_EN 0 0 NC7_7 7 7 RESERVED_15_8 8 15 ixDPCSSYS_CR4_LANEX_ANA_RX_PWR_CTRL2 2 0x90f5 9 0 4294967295 OVRD_DFE_EN 0 0 DFE_EN_REG 0 0 OVRD_DESERIAL_EN 0 0 DESERIAL_EN_REG 0 0 OVRD_LOOPBACK_EN 0 0 LOOPBACK_EN_REG 0 0 OVRD_FAST_START 0 0 FAST_START_REG 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR4_LANEX_ANA_RX_SQ 2 0x90f6 7 0 4294967295 SQ_CTRL_RESP_REG 0 0 OVRD_SQ_CTRL_RESP 0 0 NC4_3 3 4 SQ_CTRL_TRESH_REG 0 0 OVRD_SQ_CTRL_TRESH 0 0 AFE_LOOPBACK_SEL 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR4_LANEX_ANA_RX_CAL1 2 0x90f7 5 0 4294967295 DFE_TAPS_EN_REG 0 0 OVRD_DFE_TAPS_EN 0 0 CAL_MUXB_SEL_REG 0 0 OVRD_CAL_MUXB_SEL 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR4_LANEX_ANA_RX_CAL2 2 0x90f8 5 0 4294967295 AFE_PD_EQ_OFFSET 0 0 CAL_IDACS_USE_UNCAL 0 0 CAL_MUXA_SEL_REG 0 0 OVRD_CAL_MUXA_SEL 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR4_LANEX_ANA_RX_ATB_REGREF 2 0x90f9 8 0 4294967295 OVERRIDE_REGREF_VCO 0 0 OVERRIDE_REGREF_CLK 0 0 OVERRIDE_REGREF_IQC 0 0 BOOST_REGREF_IQC 0 0 OVRD_RX_SLICER_CTRL 0 0 OVRD_RX_TERM_AC_DCZ 0 0 RX_TERM_AC_DCZ_REG 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR4_LANEX_ANA_RX_ATB_MEAS1 2 0x90fa 9 0 4294967295 MASTER_ATB_EN 0 0 MEAS_ATB_VP 0 0 MEAS_ATB_GD 0 0 MEAS_ATB_VREG_VCO 0 0 MEAS_ATB_VREG_CLK 0 0 MEAS_ATB_VREG_IQC 0 0 REGS_FB_DIV_CTRL 0 0 RX_VREG_CLK_BYPASS 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR4_LANEX_ANA_RX_ATB_MEAS2 2 0x90fb 2 0 4294967295 MEAS_ATB_RX 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR4_LANEX_ANA_RX_ATB_MEAS3 2 0x90fc 7 0 4294967295 MEAS_ATB_CDR_VCO_GD 0 0 MEAS_ATB_CDR_VCO_VIREF_200U 0 0 MEAS_ATB_VIBIAS_CDR_VCO 0 0 MEAS_ATB_CDR_VCO_VOSC 0 0 MEAS_ATB_CAL_MUX 0 0 RX_VREG_OVERRIDE_RING_CTRL 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR4_LANEX_ANA_RX_ATB_MEAS4 2 0x90fd 3 0 4294967295 MEAS_ATB_CAL_VREF 0 0 NC7 7 7 RESERVED_15_8 8 15 ixDPCSSYS_CR4_LANEX_ANA_RX_ATB_FRC 2 0x90fe 2 0 4294967295 FRC_ATB_CAL_VREF 0 0 RESERVED_15_8 8 15 ixDPCSSYS_CR4_LANEX_ANA_RX_RESERVED1 2 0x90ff 2 0 4294967295 NC7_0 0 7 RESERVED_15_8 8 15 ixDPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN 2 0xe000 12 0 4294967295 PSTATE 0 1 LPD 2 2 WIDTH 3 4 RATE 5 7 MPLLB_SEL 8 8 MPLL_EN 9 9 OVRD_EN 10 10 MSTR_MPLLA_STATE 11 11 MSTR_MPLLB_STATE 12 12 MSTR_MPLL_OVRD_EN 13 13 TX_ASYNC_EN_OVR_VAL 14 14 TX_ASYNC_EN_OVR_EN 15 15 ixDPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1 2 0xe001 13 0 4294967295 RESET_OVRD_VAL 0 0 RESET_OVRD_EN 1 1 REQ_OVRD_VAL 2 2 REQ_OVRD_EN 3 3 DETRX_REQ_OVRD_VAL 4 4 DETRX_REQ_OVRD_EN 5 5 VBOOST_EN_OVRD_VAL 6 6 VBOOST_EN_OVRD_EN 7 7 IBOOST_LVL_OVRD_VAL 8 11 IBOOST_LVL_OVRD_EN 12 12 TX_BEACON_EN_OVR_VAL 13 13 TX_BEACON_EN_OVR_EN 14 14 RESERVED_15_15 15 15 ixDPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_PCS_IN 2 0xe002 12 0 4294967295 RESET 0 0 REQ 1 1 PSTATE 2 3 LPD 4 4 WIDTH 5 6 RATE 7 9 MPLLB_SEL 10 10 MPLL_EN 11 11 MSTR_MPLLA_STATE 12 12 MSTR_MPLLB_STATE 13 13 DETRX_REQ 14 14 RESERVED_15_15 15 15 ixDPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_OVRD_OUT 2 0xe003 6 0 4294967295 ACK 0 0 DETRX_RESULT 1 1 EN_CTL 2 2 TX_DWORD_CLK_SYNC_OVRD_VAL 3 3 TX_DWORD_CLK_SYNC_OVRD_EN 4 4 RESERVED_15_5 5 15 ixDPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_PCS_OUT 2 0xe004 2 0 4294967295 ACK 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN 2 0xe005 12 0 4294967295 RATE 0 1 WIDTH 2 3 PSTATE 4 5 LPD 6 6 OVRD_EN 7 7 ADAPT_AFE_EN 8 8 ADAPT_DFE_EN 9 9 LANE_RX2TX_PAR_LB_EN_OVRD_VAL 10 10 LANE_RX2TX_PAR_LB_EN_OVRD_EN 11 11 RX_DATA_EN_OVRD_VAL_R 12 12 RX_DATA_EN_OVRD_EN_R 13 13 RESERVED_15_14 14 15 ixDPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1 2 0xe006 12 0 4294967295 RESET_OVRD_VAL 0 0 RESET_OVRD_EN 1 1 REQ_OVRD_VAL 2 2 REQ_OVRD_EN 3 3 RX_LOS_THRSHLD_OVRD_VAL 4 6 RX_LOS_THRSHLD_OVRD_EN 7 7 ADAPT_REQ 8 8 ADAPT_REQ_OVRD_EN 9 9 ADAPT_CONT 10 10 OFFCAN_CONT 11 11 CONT_OVRD_EN 12 12 RESERVED_15_13 13 15 ixDPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_2 2 0xe007 4 0 4294967295 VCO_LD_VAL_OVRD 0 12 VCO_LD_VAL_OVRD_EN 13 13 VCO_LOWFREQ_VAL_OVRD 14 14 VCO_LOWFREQ_VAL_OVRD_EN 15 15 ixDPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_3 2 0xe008 3 0 4294967295 REF_LD_VAL_OVRD 0 6 REF_LD_VAL_OVRD_EN 7 7 RESERVED_15_8 8 15 ixDPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_PCS_IN 2 0xe009 13 0 4294967295 REQ 0 0 RATE 1 2 WIDTH 3 4 PSTATE 5 6 LPD 7 7 CDR_VCO_LOWFREQ 8 8 ADAPT_AFE_EN 9 9 ADAPT_DFE_EN 10 10 ADAPT_REQ 11 11 ADAPT_CONT 12 12 OFFCAN_CONT 13 13 RESET 14 14 RESERVED_15_15 15 15 ixDPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_1 2 0xe00a 2 0 4294967295 REF_LD_VAL 0 6 RESERVED_15_7 7 15 ixDPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_2 2 0xe00b 2 0 4294967295 VCO_LD_VAL 0 12 RESERVED_15_13 13 15 ixDPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_3 2 0xe00c 4 0 4294967295 EQ_ATT_LVL 0 2 EQ_VGA1_GAIN 3 6 EQ_VGA2_GAIN 7 10 EQ_CTLE_BOOST 11 15 ixDPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_4 2 0xe00d 3 0 4294967295 EQ_CTLE_POLE 0 2 EQ_DFE_TAP1 3 10 RESERVED_15_11 11 15 ixDPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT 2 0xe00e 3 0 4294967295 ACK 0 0 EN_CTL 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_PCS_OUT 2 0xe00f 2 0 4294967295 ACK 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_ADAPT_ACK 2 0xe010 2 0 4294967295 RX_ADAPT_ACK 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_ADAPT_FOM 2 0xe011 2 0 4294967295 RX_ADAPT_FOM 0 7 RESERVED_15_8 8 15 ixDPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_TXPRE_DIR 2 0xe012 2 0 4294967295 RX_TXPRE_DIR 0 1 RESERVED_15_2 2 15 ixDPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_TXMAIN_DIR 2 0xe013 2 0 4294967295 RX_TXMAIN_DIR 0 1 RESERVED_15_2 2 15 ixDPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_TXPOST_DIR 2 0xe014 2 0 4294967295 RX_TXPOST_DIR 0 1 RESERVED_15_2 2 15 ixDPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_LANE_NUMBER 2 0xe015 2 0 4294967295 LANE_NUMBER 0 3 RESERVED_15_4 4 15 ixDPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RESERVED_1 2 0xe016 1 0 4294967295 RESERVED_REG_1 0 15 ixDPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RESERVED_2 2 0xe017 1 0 4294967295 RESERVED_REG_2 0 15 ixDPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN 2 0xe018 16 0 4294967295 RX_RESET_ATE_OVRD_VAL 0 0 RX_RESET_ATE_OVRD_EN 1 1 TX_RESET_ATE_OVRD_VAL 2 2 TX_RESET_ATE_OVRD_EN 3 3 RX_REQ_ATE_OVRD_VAL 4 4 RX_REQ_ATE_OVRD_EN 5 5 TX_REQ_ATE_OVRD_VAL 6 6 TX_REQ_ATE_OVRD_EN 7 7 RX_ADAPT_AFE_EN_OVRD_VAL 8 8 RX_ADAPT_AFE_EN_OVRD_EN 9 9 RX_ADAPT_DFE_EN_OVRD_VAL 10 10 RX_ADAPT_DFE_EN_OVRD_EN 11 11 TX_DATA_EN_ATE_OVRD_VAL 12 12 TX_DATA_EN_ATE_OVRD_EN 13 13 RX_DATA_EN_ATE_OVRD_VAL 14 14 RX_DATA_EN_ATE_OVRD_EN 15 15 ixDPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN 2 0xe019 3 0 4294967295 RX_EQ_DELTA_IQ_OVRD_VAL 0 3 RX_EQ_DELTA_IQ_OVRD_EN 4 4 RESERVED_15_5 5 15 ixDPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN 2 0xe01a 5 0 4294967295 RX_TERM_CTRL_OVRD_VAL 0 2 RX_TERM_CTRL_OVRD_EN 3 3 TX_TERM_CTRL_OVRD_VAL 4 6 TX_TERM_CTRL_OVRD_EN 7 7 RESERVED_15_8 8 15 ixDPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TXRX_TERM_CTRL_IN 2 0xe01b 3 0 4294967295 RX_TERM_CTRL 0 2 TX_TERM_CTRL 3 5 RESERVED_15_6 6 15 ixDPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT_1 2 0xe01c 2 0 4294967295 RX_CLK_EN 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_EQ_OVRD_IN_1 2 0xe01d 4 0 4294967295 RX_EQ_AFE_GAIN_OVRD_VAL 0 3 RX_EQ_ATT_LVL_OVRD_VAL 4 6 RX_EQ_OVRD_EN 7 7 RESERVED_15_8 8 15 ixDPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_EQ_OVRD_IN_2 2 0xe01e 3 0 4294967295 RX_EQ_DFE_TAP1_OVRD_VAL 0 7 RX_EQ_CTLE_BOOST_OVRD_VAL 8 12 RESERVED_15_13 13 15 ixDPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_PH2_CAL 2 0xe01f 4 0 4294967295 PH2_CAL_ACK_VAL 0 0 PH2_CAL_REQ_VAL 1 1 PH2_CAL_REQ_OVRD_VAL 2 2 RESERVED_15_3 3 15 ixDPCSSYS_CR4_RAWLANEX_DIG_FSM_FSM_OVRD_CTL 2 0xe020 5 0 4294967295 FSM_JMP_ADDR 0 11 FSM_JMP_EN 12 12 FSM_CMD_START 13 13 FSM_OVRD_EN 14 14 FSM_BREAK 15 15 ixDPCSSYS_CR4_RAWLANEX_DIG_FSM_MEM_ADDR_MON 2 0xe021 1 0 4294967295 MEM_ADDR 0 15 ixDPCSSYS_CR4_RAWLANEX_DIG_FSM_STATUS_MON 2 0xe022 8 0 4294967295 STATE 0 4 CMD_RDY 5 5 ALU_OVFLW 6 6 ALU_RES_EQ0 7 7 WAIT_CNT_EQ0 8 8 WRMSK_DISABLED 9 9 RDMSK_DISABLED 10 10 RESERVED_15_11 11 15 ixDPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_RX_STARTUP_CAL 2 0xe023 2 0 4294967295 FAST_RX_STARTUP_CAL 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_RX_ADAPT 2 0xe024 2 0 4294967295 FAST_RX_ADAPT 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_RX_AFE_CAL 2 0xe025 2 0 4294967295 FAST_RX_AFE_CAL 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_RX_DFE_CAL 2 0xe026 2 0 4294967295 FAST_RX_DFE_CAL 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_RX_BYPASS_CAL 2 0xe027 2 0 4294967295 FAST_RX_BYPASS_CAL 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_RX_REFLVL_CAL 2 0xe028 2 0 4294967295 FAST_RX_REFLVL_CAL 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_RX_IQ_CAL 2 0xe029 2 0 4294967295 FAST_RX_IQ_CAL 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_RX_AFE_ADAPT 2 0xe02a 2 0 4294967295 FAST_RX_AFE_ADAPT 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_RX_DFE_ADAPT 2 0xe02b 2 0 4294967295 FAST_RX_DFE_ADAPT 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_SUP 2 0xe02c 2 0 4294967295 FAST_SUP 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_TX_CMN_MODE 2 0xe02d 2 0 4294967295 FAST_TX_CMN_MODE 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_TX_RXDET 2 0xe02e 2 0 4294967295 FAST_TX_RXDET 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_RX_PWRUP 2 0xe02f 2 0 4294967295 FAST_RX_PWRUP 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_RX_VCO_WAIT 2 0xe030 2 0 4294967295 FAST_RX_VCO_WAIT 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_RX_VCO_CAL 2 0xe031 2 0 4294967295 FAST_RX_VCO_CAL 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR4_RAWLANEX_DIG_FSM_CMNCAL_MPLL_STATUS 2 0xe032 3 0 4294967295 CMNCAL_MPLL_INIT 0 0 CMNCAL_MPLL_DONE 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_RX_CONT_CAL_ADAPT 2 0xe033 2 0 4294967295 FAST_RX_CONT_CAL_ADAPT 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_RX_CONT_ADAPT 2 0xe034 2 0 4294967295 FAST_RX_CONT_ADAPT 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_RX_CONT_DATA_CAL 2 0xe035 2 0 4294967295 FAST_RX_CONT_DATA_CAL 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_RX_CONT_PHASE_CAL 2 0xe036 2 0 4294967295 FAST_RX_CONT_PHASE_CAL 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_RX_CONT_AFE_CAL 2 0xe037 2 0 4294967295 FAST_RX_CONT_AFE_CAL 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_FLAGS 2 0xe038 12 0 4294967295 TX_FAST_DCC_CAL 0 0 RX_FAST_DCC_CAL 1 1 RX_FAST_VPHUD_CAL 2 2 RX_FAST_VREF_CAL 3 3 RX_FAST_SIGDET_CAL 4 4 RESERVED_2 5 7 TX_FAST_CONT_DCC_CAL 8 8 RX_FAST_CONT_DCC_CAL 9 9 RX_FAST_CONT_VPHUD_CAL 10 10 RX_FAST_CONT_VREF_CAL 11 11 RESERVED_1 12 14 TX_SKIP_SUP_CAL 15 15 ixDPCSSYS_CR4_RAWLANEX_DIG_FSM_CR_LOCK 2 0xe039 3 0 4294967295 CR_REG_LOCK 0 0 CR_MEM_LOCK 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR4_RAWLANEX_DIG_FSM_TX_DCC_FLAGS 2 0xe03a 4 0 4294967295 RATE 0 0 DIV 1 1 MPLL 2 2 RESERVED_15_3 3 15 ixDPCSSYS_CR4_RAWLANEX_DIG_FSM_TX_DCC_STATUS 2 0xe03b 2 0 4294967295 FLAG 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR4_RAWLANEX_DIG_FSM_OCLA 2 0xe03c 4 0 4294967295 PC_EN 0 0 REG_BANK1_EN 1 1 REG_BANK2_EN 2 2 RESERVED_15_3 3 15 ixDPCSSYS_CR4_RAWLANEX_DIG_FSM_TX_EQ_UPDATE_FLAG 2 0xe03d 2 0 4294967295 TX_EQ_UPDATE_FLAG 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR4_RAWLANEX_DIG_FSM_CMNCAL_RCAL_STATUS 2 0xe03e 3 0 4294967295 CMNCAL_RCAL_INIT 0 0 CMNCAL_RCAL_DONE 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR4_RAWLANEX_DIG_FSM_RX_IQ_PHASE_OFFSET 2 0xe03f 2 0 4294967295 RX_IQ_PHASE_OFFSET 0 3 RESERVED_15_4 4 15 ixDPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_RESET_RTN_REQ 2 0xe040 2 0 4294967295 RESET_RTN_REQ 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_RX_RESET_IRQ 2 0xe041 2 0 4294967295 RX_RESET 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_RX_REQ_IRQ 2 0xe042 2 0 4294967295 RX_REQ 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_RX_RATE_IRQ 2 0xe043 2 0 4294967295 RX_RATE_IRQ 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_RX_PSTATE_IRQ 2 0xe044 2 0 4294967295 RX_PSTATE_IRQ 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ 2 0xe045 2 0 4294967295 RX_ADAPT_REQ_IRQ 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ 2 0xe046 2 0 4294967295 RX_ADAPT_DIS_IRQ 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_RX_RESET_IRQ_CLR 2 0xe047 2 0 4294967295 RX_RESET_IRQ_CLR 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_RX_REQ_IRQ_CLR 2 0xe048 2 0 4294967295 RX_REQ_IRQ_CLR 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_RX_RATE_IRQ_CLR 2 0xe049 2 0 4294967295 RX_RATE_IRQ_CLR 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR 2 0xe04a 2 0 4294967295 RX_PSTATE_IRQ_CLR 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR 2 0xe04b 2 0 4294967295 RX_ADAPT_REQ_IRQ_CLR 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR 2 0xe04c 2 0 4294967295 RX_ADAPT_DIS_IRQ_CLR 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK 2 0xe04d 12 0 4294967295 RX_REQ_IRQ_MSK 0 0 RX_RATE_IRQ_MSK 1 1 RX_PSTATE_IRQ_MSK 2 2 RX_ADAPT_REQ_IRQ_MSK 3 3 RX_ADAPT_DIS_IRQ_MSK 4 4 RX_RESET_IRQ_MSK 5 5 LANE_XCVR_MODE_IRQ_MSK 6 6 RX_PH2_CAL_REQ_IRQ_MSK 7 7 RX_PH2_CAL_DIS_IRQ_MSK 8 8 LANE_RX2TX_SER_LB_EN_IRQ_MSK 9 9 DCC_ONDMD_IRQ_MSK 10 10 RESERVED_15_11 11 15 ixDPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK_2 2 0xe04e 3 0 4294967295 TX_RESET_IRQ_MSK 0 0 TX_REQ_IRQ_MSK 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ 2 0xe04f 2 0 4294967295 LANE_XCVR_MODE_IRQ 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR 2 0xe050 2 0 4294967295 LANE_XCVR_MODE_IRQ_CLR 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ 2 0xe051 2 0 4294967295 RX_PH2_CAL_REQ_IRQ 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ 2 0xe052 2 0 4294967295 RX_PH2_CAL_DIS_IRQ 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR 2 0xe053 2 0 4294967295 RX_PH2_CAL_REQ_IRQ_CLR 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR 2 0xe054 2 0 4294967295 RX_PH2_CAL_DIS_IRQ_CLR 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ 2 0xe055 2 0 4294967295 LANE_RX2TX_SER_LB_EN_IRQ 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR 2 0xe056 2 0 4294967295 LANE_RX2TX_SER_LB_EN_IRQ_CLR 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_DCC_ONDMD_IRQ 2 0xe057 2 0 4294967295 IRQ 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_TX_RESET_IRQ 2 0xe058 2 0 4294967295 TX_RESET 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_TX_REQ_IRQ 2 0xe059 2 0 4294967295 TX_REQ 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_TX_RESET_IRQ_CLR 2 0xe05a 2 0 4294967295 TX_RESET_IRQ_CLR 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_TX_REQ_IRQ_CLR 2 0xe05b 2 0 4294967295 TX_REQ_IRQ_CLR 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_LANE_OVRD_IN 2 0xe060 4 0 4294967295 LANE_MPLLA_EN_IN 0 0 LANE_MPLLB_EN_IN 1 1 LANE_OVRD_EN 2 2 RESERVED_15_3 3 15 ixDPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_LANE_OVRD_OUT 2 0xe061 4 0 4294967295 LANE_MPLLA_EN_OUT 0 0 LANE_MPLLB_EN_OUT 1 1 LANE_OVRD_EN 2 2 RESERVED_15_3 3 15 ixDPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_SUP_OVRD_IN 2 0xe062 4 0 4294967295 MPLLA_STATE 0 0 MPLLB_STATE 1 1 SUP_STATE_OVRD_EN 2 2 RESERVED_15_3 3 15 ixDPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_SUP_PMA_IN 2 0xe063 3 0 4294967295 MPLLA_STATE 0 0 MPLLB_STATE 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT 2 0xe064 16 0 4294967295 TX_REQ_OVRD_VAL 0 0 TX_REQ_OVRD_EN 1 1 TX_RESET_OVRD_VAL 2 2 TX_RESET_OVRD_EN 3 3 TX_BEACON_EN_OVRD_VAL 4 4 TX_BEACON_EN_OVRD_EN 5 5 TX_ASYNC_DRV_EN_OVRD_VAL 6 6 TX_ASYNC_DRV_EN_OVRD_EN 7 7 TX_ASYNC_EN_OVRD_VAL 8 8 TX_ASYNC_EN_OVRD_EN 9 9 TX_DWORD_CLK_SYNC_OVRD_VAL 10 10 TX_DWORD_CLK_SYNC_OVRD_EN 11 11 LANE_TX2RX_SER_LB_EN_OVRD_VAL 12 12 LANE_TX2RX_SER_LB_EN_OVRD_EN 13 13 TX_PMA_DATA_EN_OVRD_VAL_R 14 14 TX_PMA_DATA_EN_OVRD_EN_R 15 15 ixDPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_TX_PMA_IN 2 0xe065 2 0 4294967295 ACK 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT 2 0xe066 9 0 4294967295 RX_REQ_OVRD_VAL 0 0 RX_REQ_OVRD_EN 1 1 RX_RESET_OVRD_VAL 2 2 RX_RESET_OVRD_EN 3 3 LANE_RX2TX_PAR_LB_EN_OVRD_VAL 4 4 LANE_RX2TX_PAR_LB_EN_OVRD_EN 5 5 RX_PMA_DATA_EN_OVRD_VAL_R 6 6 RX_PMA_DATA_EN_OVRD_EN_R 7 7 RESERVED_15_8 8 15 ixDPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_RX_PMA_IN 2 0xe067 2 0 4294967295 ACK 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_LANE_RTUNE_CTL 2 0xe068 2 0 4294967295 LANE_RTUNE_REQ 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_SUP_PMA_IN_1 2 0xe069 2 0 4294967295 RTUNE_ACK 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_IN 2 0xe06a 9 0 4294967295 RX_PMA_PWM_WORD_CLK_R 0 0 RX_PMA_PWM_WORD_CLK_OVRD_EN 1 1 RX_PMA_PWM_DATA_R 2 2 RX_PMA_PWM_DATA_OVRD_EN 3 3 RX_PMA_PWM_CLK_R 4 4 RX_PMA_PWM_CLK_OVRD_EN 5 5 RX_PMA_TERM_CTL_R 6 7 RX_PMA_TERM_CTL_OVRD_EN 8 8 RESERVED_15_9 9 15 ixDPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_OUT 2 0xe06b 7 0 4294967295 RX_PMA_PWM_EN 0 0 RX_PMA_PWM_EN_OVRD_EN 1 1 RX_PMA_PWM_CLK_SEL 2 3 RX_PMA_PWM_CLK_SEL_OVRD_EN 4 4 RX_PMA_ASYNC_EN 5 5 RX_PMA_ASYNC_EN_OVRD_EN 6 6 RESERVED_15_7 7 15 ixDPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_RX_ADAPT_OVRD_OUT 2 0xe06c 3 0 4294967295 RX_PMA_IQ_PHASE_ADJUST_MAP_OVRD_VAL 0 6 RX_PMA_IQ_PHASE_ADJUST_MAP_OVRD_EN 7 7 RESERVED_15_8 8 15 ixDPCSSYS_CR4_RAWLANEX_DIG_TX_CTL_TX_FSM_CTL 2 0xe080 6 0 4294967295 TX_WAIT_MPLL_OFF_TIME 0 6 TX_P2_ALLOW_RXDET 7 7 TX_P1_ALLOW_RXDET 8 8 TX_P0S_ALLOW_RXDET 9 9 TX_P0_ALLOW_RXDET 10 10 RESERVED_15_11 11 15 ixDPCSSYS_CR4_RAWLANEX_DIG_TX_CTL_TX_CLK_CTL 2 0xe081 4 0 4294967295 TX_CLK_EN 0 0 TX_CLK_SEL 1 4 ASYNC_BEACON_WAIT_TIME 5 10 RESERVED_15_11 11 15 ixDPCSSYS_CR4_RAWLANEX_DIG_TX_CTL_TX_DCC_CONT_STATUS 2 0xe082 2 0 4294967295 ENABLE 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR4_RAWLANEX_DIG_TX_CTL_OCLA 2 0xe083 2 0 4294967295 FSM_EN 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR4_RAWLANEX_DIG_TX_CTL_UPCS_OCLA 2 0xe084 3 0 4294967295 DATA_EN 0 1 CLK_EN 2 2 RESERVED_15_3 3 15 ixDPCSSYS_CR4_RAWLANEX_DIG_RX_CTL_RX_FSM_CTL 2 0xe0a0 3 0 4294967295 EN_RX_CTL_FSM 0 0 RATE_CHG_IN_P1 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR4_RAWLANEX_DIG_RX_CTL_RX_LOS_MASK_CTL 2 0xe0a1 2 0 4294967295 RX_LOS_MASK_CNT 0 8 RESERVED_15_9 9 15 ixDPCSSYS_CR4_RAWLANEX_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL 2 0xe0a2 2 0 4294967295 RX_DATA_EN_OVRD_CNT 0 4 INT_REF_TRCK_CNT 5 15 ixDPCSSYS_CR4_RAWLANEX_DIG_RX_CTL_OFFCAN_CONT_STATUS 2 0xe0a3 2 0 4294967295 ENABLE 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR4_RAWLANEX_DIG_RX_CTL_ADAPT_CONT_STATUS 2 0xe0a4 2 0 4294967295 ENABLE 0 0 RESERVED_15_1 1 15 ixDPCSSYS_CR4_RAWLANEX_DIG_RX_CTL_UPCS_OCLA 2 0xe0a5 3 0 4294967295 DATA_EN 0 2 CLK_EN 3 3 RESERVED_15_4 4 15 ixDPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN 2 0xe0c0 11 0 4294967295 RATE_OVRD_VAL 0 1 RATE_OVRD_EN 2 2 WIDTH_OVRD_VAL 3 4 WIDTH_OVRD_EN 5 5 PSTATE_OVRD_VAL 6 7 PSTATE_OVRD_EN 8 8 LPD_OVRD_VAL 9 9 LPD_OVRD_EN 10 10 LANE_RX2TX_PAR_LB_EN_OVRD_VAL 11 11 LANE_RX2TX_PAR_LB_EN_OVRD_EN 12 12 RESERVED_15_13 13 15 ixDPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN 2 0xe0c1 12 0 4294967295 PSTATE 0 1 LPD 2 2 WIDTH 3 4 RATE 5 7 MPLLB_SEL 8 8 MPLL_EN 9 9 OVRD_EN 10 10 MSTR_MPLLA_STATE 11 11 MSTR_MPLLB_STATE 12 12 MSTR_MPLL_OVRD_EN 13 13 TX_ASYNC_EN_OVR_VAL 14 14 TX_ASYNC_EN_OVR_EN 15 15 ixDPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1 2 0xe0c2 13 0 4294967295 DETRX_REQ_OVRD_VAL 0 0 DETRX_REQ_OVRD_EN 1 1 VBOOST_EN_OVRD_VAL 2 2 VBOOST_EN_OVRD_EN 3 3 IBOOST_LVL_OVRD_VAL 4 7 IBOOST_LVL_OVRD_EN 8 8 TX_BEACON_EN_OVR_VAL 9 9 TX_BEACON_EN_OVR_EN 10 10 LANE_TX2RX_SER_LB_EN_OVRD_VAL 11 11 LANE_TX2RX_SER_LB_EN_OVRD_EN 12 12 TX_ASYNC_DATA_OVRD_VAL 13 13 TX_ASYNC_DATA_OVRD_EN 14 14 RESERVED_15_15 15 15 ixDPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_MASTER_MPLL_LOOP 2 0xe0c3 3 0 4294967295 MPLLB_LOOP_EN 0 0 MPLLA_LOOP_EN 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1 2 0xe0c4 11 0 4294967295 RESERVED 0 1 RX_LOS_LFPS_EN_OVRD_VAL 2 2 RX_LOS_LFPS_EN_OVRD_EN 3 3 RX_LOS_THRSHLD_OVRD_VAL 4 6 RX_LOS_THRSHLD_OVRD_EN 7 7 ADAPT_REQ 8 8 ADAPT_REQ_OVRD_EN 9 9 ADAPT_CONT 10 10 OFFCAN_CONT 11 11 CONT_OVRD_EN 12 12 RESERVED_15_13 13 15 ixDPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_2 2 0xe0c5 4 0 4294967295 VCO_LD_VAL_OVRD 0 12 VCO_LD_VAL_OVRD_EN 13 13 VCO_LOWFREQ_VAL_OVRD 14 14 VCO_LOWFREQ_VAL_OVRD_EN 15 15 ixDPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_3 2 0xe0c6 3 0 4294967295 REF_LD_VAL_OVRD 0 6 REF_LD_VAL_OVRD_EN 7 7 RESERVED_15_8 8 15 ixDPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT_2 2 0xe0c7 3 0 4294967295 RX_VALID 0 0 RX_VALID_OVRD_EN 1 1 RESERVED_15_2 2 15 ixDPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_2 2 0xe0c8 7 0 4294967295 LANE_TX2RX_SER_LB_EN_OVRD_VAL 0 0 LANE_TX2RX_SER_LB_EN_OVRD_EN 1 1 TX_DATA_EN_OVRD_VAL_R 2 2 TX_DATA_EN_OVRD_EN_R 3 3 TX_ASYNC_DATA_OVRD_VAL_R 4 4 TX_ASYNC_DATA_OVRD_EN_R 5 5 RESERVED_15_6 6 15